From 68da45479fd289281017768a8cfa51b2f642ac07 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Michael=20Niew=C3=B6hner?= Date: Sat, 19 Oct 2019 11:57:05 +0200 Subject: [PATCH 0001/1242] soc/intel: skl,cnl,icl: rely on TOLUM as cbmem_top returned by FSP MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Instead of doing our own calculations, rely on TOLUM returned by FSP for cbmem_top. This (hopefully) saves us from making mistakes in weird calculations of offsets and alignments. Further this makes it easier to implement e.g. SGX PRMRR size selection via Kconfig as we do not have to make any assumptions about alignments but can simply pass (valid) values to FSP. Tested successfully on X11SSM-F Change-Id: If66a00d1320917bc68afb32c19db0e24c6732812 Signed-off-by: Michael Niewöhner Reviewed-on: https://review.coreboot.org/c/coreboot/+/36136 Reviewed-by: Arthur Heymans Reviewed-by: Aaron Durbin Reviewed-by: Nico Huber Tested-by: build bot (Jenkins) --- src/drivers/intel/fsp2_0/hand_off_block.c | 6 + src/drivers/intel/fsp2_0/hob_verify.c | 6 - src/soc/intel/cannonlake/include/soc/ebda.h | 5 +- src/soc/intel/cannonlake/memmap.c | 163 +---------------- .../block/include/intelblocks/systemagent.h | 6 - .../block/systemagent/systemagent_early.c | 71 -------- src/soc/intel/icelake/include/soc/ebda.h | 5 +- src/soc/intel/icelake/memmap.c | 143 +-------------- src/soc/intel/skylake/include/soc/ebda.h | 5 +- src/soc/intel/skylake/memmap.c | 170 +----------------- 10 files changed, 33 insertions(+), 547 deletions(-) diff --git a/src/drivers/intel/fsp2_0/hand_off_block.c b/src/drivers/intel/fsp2_0/hand_off_block.c index 65ceb2058c..d2c2b784cf 100644 --- a/src/drivers/intel/fsp2_0/hand_off_block.c +++ b/src/drivers/intel/fsp2_0/hand_off_block.c @@ -300,3 +300,9 @@ const void *fsp_find_nv_storage_data(size_t *size) { return fsp_find_extension_hob_by_guid(fsp_nv_storage_guid, size); } + +void fsp_find_bootloader_tolum(struct range_entry *re) +{ + if (fsp_find_range_hob(re, fsp_bootloader_tolum_guid)) + die("9.3: FSP_BOOTLOADER_TOLUM_HOB missing!\n"); +} diff --git a/src/drivers/intel/fsp2_0/hob_verify.c b/src/drivers/intel/fsp2_0/hob_verify.c index e2937d7f7a..0c28a9a82d 100644 --- a/src/drivers/intel/fsp2_0/hob_verify.c +++ b/src/drivers/intel/fsp2_0/hob_verify.c @@ -16,12 +16,6 @@ #include #include -void fsp_find_bootloader_tolum(struct range_entry *re) -{ - if (fsp_find_range_hob(re, fsp_bootloader_tolum_guid)) - die("9.3: FSP_BOOTLOADER_TOLUM_HOB missing!\n"); -} - void fsp_verify_memory_init_hobs(void) { struct range_entry fsp_mem; diff --git a/src/soc/intel/cannonlake/include/soc/ebda.h b/src/soc/intel/cannonlake/include/soc/ebda.h index ad62394588..4ed6566838 100644 --- a/src/soc/intel/cannonlake/include/soc/ebda.h +++ b/src/soc/intel/cannonlake/include/soc/ebda.h @@ -19,9 +19,8 @@ #include struct ebda_config { - uint32_t signature; /* 0x00 - EBDA signature */ - uint32_t tolum_base; /* 0x04 - coreboot memory start */ - uint32_t reserved_mem_size; /* 0x08 - chipset reserved memory size */ + uint32_t signature; /* EBDA signature */ + uint32_t cbmem_top; /* coreboot memory start */ }; #endif diff --git a/src/soc/intel/cannonlake/memmap.c b/src/soc/intel/cannonlake/memmap.c index 7a0d89717b..63e7acdb85 100644 --- a/src/soc/intel/cannonlake/memmap.c +++ b/src/soc/intel/cannonlake/memmap.c @@ -15,141 +15,15 @@ */ #include -#include #include -#include -#include -#include -#include -#include #include #include #include -#include -#include #include -#include "chip.h" - -static bool is_ptt_enable(void) -{ - if ((read32((void *)PTT_TXT_BASE_ADDRESS) & PTT_PRESENT) == - PTT_PRESENT) - return true; - - return false; -} - -/* Calculate PTT size */ -static size_t get_ptt_size(void) -{ - /* Allocate 4KB for PTT if enabled */ - return is_ptt_enable() ? 4*KiB : 0; -} - -/* Calculate ME Stolen size */ -static size_t get_imr_size(void) -{ - size_t imr_size; - - /* ME stolen memory */ - imr_size = MCHBAR32(IMRLIMIT) - MCHBAR32(IMRBASE); - - return imr_size; -} - -/* Calculate PRMRR size based on user input PRMRR size and alignment */ -static size_t get_prmrr_size(uintptr_t dram_base, - const struct soc_intel_cannonlake_config *config) -{ - uintptr_t prmrr_base = dram_base; - size_t prmrr_size; - - prmrr_size = config->PrmrrSize; - - /* Allocate PRMRR memory for C6DRAM */ - if (!prmrr_size) { - if (config->enable_c6dram) - prmrr_size = 1*MiB; - else - return 0; - } - - /* - * PRMRR Sizes that are > 1MB and < 32MB are - * not supported and will fail out. - */ - if ((prmrr_size > 1*MiB) && (prmrr_size < 32*MiB)) - die("PRMRR Sizes that are > 1MB and < 32MB are not" - "supported!\n"); - - prmrr_base -= prmrr_size; - if (prmrr_size >= 32*MiB) - prmrr_base = ALIGN_DOWN(prmrr_base, 128*MiB); - else - prmrr_base = ALIGN_DOWN(prmrr_base, 16*MiB); - /* PRMRR Area Size */ - prmrr_size = dram_base - prmrr_base; - - return prmrr_size; -} - -/* Calculate Intel Traditional Memory size based on GSM, DSM, TSEG and DPR. */ -static size_t calculate_traditional_mem_size(uintptr_t dram_base, - const struct device *dev) -{ - uintptr_t traditional_mem_base = dram_base; - size_t traditional_mem_size; - - if (dev->enabled) { - /* Read BDSM from Host Bridge */ - traditional_mem_base -= sa_get_dsm_size(); - - /* Read BGSM from Host Bridge */ - traditional_mem_base -= sa_get_gsm_size(); - } - /* Get TSEG size */ - traditional_mem_base -= sa_get_tseg_size(); - - /* Get DPR size */ - if (CONFIG(SA_ENABLE_DPR)) - traditional_mem_base -= sa_get_dpr_size(); - - /* Traditional Area Size */ - traditional_mem_size = dram_base - traditional_mem_base; - - return traditional_mem_size; -} - -/* - * Calculate Intel Reserved Memory size based on - * PRMRR size, Me stolen memory and PTT selection. - */ -static size_t calculate_reserved_mem_size(uintptr_t dram_base, - const struct device *dev) -{ - uintptr_t reserve_mem_base = dram_base; - size_t reserve_mem_size; - const struct soc_intel_cannonlake_config *config; - - config = config_of(dev); - - /* Get PRMRR size */ - reserve_mem_base -= get_prmrr_size(reserve_mem_base, config); - - /* Get Tracehub size */ - reserve_mem_base -= get_imr_size(); - - /* Get PTT size */ - reserve_mem_base -= get_ptt_size(); - - /* Traditional Area Size */ - reserve_mem_size = dram_base - reserve_mem_base; - - return reserve_mem_size; -} - /* + * Fill up memory layout information + * * Host Memory Map: * * +--------------------------+ TOUUD @@ -181,37 +55,12 @@ static size_t calculate_reserved_mem_size(uintptr_t dram_base, * the base registers from each other to determine sizes of the regions. In * other words, the memory map is in a fixed order no matter what. */ -static uintptr_t calculate_dram_base(size_t *reserved_mem_size) -{ - uintptr_t dram_base; - const struct device *dev; - - dev = pcidev_on_root(SA_DEV_SLOT_IGD, 0); - if (!dev) - die_with_post_code(POST_HW_INIT_FAILURE, - "ERROR - IGD device not found!"); - - /* Read TOLUD from Host Bridge offset */ - dram_base = sa_get_tolud_base(); - - /* Get Intel Traditional Memory Range Size */ - dram_base -= calculate_traditional_mem_size(dram_base, dev); - - /* Get Intel Reserved Memory Range Size */ - *reserved_mem_size = calculate_reserved_mem_size(dram_base, dev); - - dram_base -= *reserved_mem_size; - - return dram_base; -} - -/* Fill up memory layout information */ void fill_soc_memmap_ebda(struct ebda_config *cfg) { - size_t chipset_mem_size; + struct range_entry tolum; - cfg->tolum_base = calculate_dram_base(&chipset_mem_size); - cfg->reserved_mem_size = chipset_mem_size; + fsp_find_bootloader_tolum(&tolum); + cfg->cbmem_top = range_entry_end(&tolum); } void cbmem_top_init(void) @@ -253,5 +102,5 @@ void *cbmem_top_chipset(void) retrieve_ebda_object(&ebda_cfg); - return (void *)(uintptr_t)ebda_cfg.tolum_base; + return (void *)(uintptr_t)ebda_cfg.cbmem_top; } diff --git a/src/soc/intel/common/block/include/intelblocks/systemagent.h b/src/soc/intel/common/block/include/intelblocks/systemagent.h index ae9213c395..163d97e899 100644 --- a/src/soc/intel/common/block/include/intelblocks/systemagent.h +++ b/src/soc/intel/common/block/include/intelblocks/systemagent.h @@ -76,18 +76,12 @@ void enable_pam_region(void); void enable_power_aware_intr(void); /* API to get TOLUD base address */ uintptr_t sa_get_tolud_base(void); -/* API to get DSM size */ -size_t sa_get_dsm_size(void); /* API to get GSM base address */ uintptr_t sa_get_gsm_base(void); -/* API to get GSM size */ -size_t sa_get_gsm_size(void); /* API to get TSEG base address */ uintptr_t sa_get_tseg_base(void); /* API to get TSEG size */ size_t sa_get_tseg_size(void); -/* API to get DPR size */ -size_t sa_get_dpr_size(void); /* * SoC overrides * diff --git a/src/soc/intel/common/block/systemagent/systemagent_early.c b/src/soc/intel/common/block/systemagent/systemagent_early.c index 8c89c07e26..d6f129d679 100644 --- a/src/soc/intel/common/block/systemagent/systemagent_early.c +++ b/src/soc/intel/common/block/systemagent/systemagent_early.c @@ -139,63 +139,12 @@ uintptr_t sa_get_tolud_base(void) return ALIGN_DOWN(pci_read_config32(SA_DEV_ROOT, TOLUD), 1*MiB); } -static uint16_t sa_get_ggc_reg(void) -{ - return pci_read_config16(SA_DEV_ROOT, GGC); -} - -/* - * Internal Graphics Pre-allocated Memory - As per Intel FSP UPD Header - * definition, size of memory preallocatred for internal graphics can be - * configured based on below lists: - * - * 0x00:0MB, 0x01:32MB, 0x02:64MB, 0x03:96MB, 0x04:128MB, 0x05:160MB, - * 0xF0:4MB, 0xF1:8MB, 0xF2:12MB, 0xF3:16MB, 0xF4:20MB, 0xF5:24MB, 0xF6:28MB, - * 0xF7:32MB, 0xF8:36MB, 0xF9:40MB, 0xFA:44MB, 0xFB:48MB, 0xFC:52MB, 0xFD:56MB, - * 0xFE:60MB - * - * Today all existing SoCs(except Cannonlake) are supported under intel - * common code block design may not need to use any other values than 0x0-0x05 - * for GFX DSM range. DSM memory ranges between 0xF0-0xF6 are majorly for - * early SoC samples and validation requirement. This code block to justify - * all differnet possible ranges that FSP may support for a platform. - */ -size_t sa_get_dsm_size(void) -{ - uint32_t prealloc_memory; - uint16_t ggc; - - ggc = sa_get_ggc_reg(); - prealloc_memory = (ggc & G_GMS_MASK) >> G_GMS_OFFSET; - - if (prealloc_memory < 0xF0) - return prealloc_memory * 32*MiB; - else - return (prealloc_memory - 0xEF) * 4*MiB; -} - uintptr_t sa_get_gsm_base(void) { /* All regions concerned for have 1 MiB alignment. */ return ALIGN_DOWN(pci_read_config32(SA_DEV_ROOT, BGSM), 1*MiB); } -size_t sa_get_gsm_size(void) -{ - uint8_t ggms; - - ggms = (sa_get_ggc_reg() & G_GGMS_MASK) >> G_GGMS_OFFSET; - - /* - * Size of GSM: 0x0: No Preallocated Memory 0x1: 2MB Memory - * 0x2: 4MB Memory 0x3: 8MB Memory - */ - if (ggms) - return 1*MiB << ggms; - else - return 0; -} - uintptr_t sa_get_tseg_base(void) { /* All regions concerned for have 1 MiB alignment. */ @@ -206,23 +155,3 @@ size_t sa_get_tseg_size(void) { return sa_get_gsm_base() - sa_get_tseg_base(); } - -/* - * Get DPR size in case CONFIG_SA_ENABLE_DPR is selected by SoC. - */ -size_t sa_get_dpr_size(void) -{ - uintptr_t dpr_reg; - size_t size = 0; - /* - * DMA Protected Range can be reserved below TSEG for PCODE patch - * or TXT/BootGuard related data. Rather than report a base address - * the DPR register reports the TOP of the region, which is the same - * as TSEG base. The region size is reported in MiB in bits 11:4. - */ - dpr_reg = pci_read_config32(SA_DEV_ROOT, DPR); - if (dpr_reg & DPR_EPM) - size = (dpr_reg & DPR_SIZE_MASK) << 16; - - return size; -} diff --git a/src/soc/intel/icelake/include/soc/ebda.h b/src/soc/intel/icelake/include/soc/ebda.h index f4d89e993d..5cb5cdc004 100644 --- a/src/soc/intel/icelake/include/soc/ebda.h +++ b/src/soc/intel/icelake/include/soc/ebda.h @@ -19,9 +19,8 @@ #include struct ebda_config { - uint32_t signature; /* 0x00 - EBDA signature */ - uint32_t tolum_base; /* 0x04 - coreboot memory start */ - uint32_t reserved_mem_size; /* 0x08 - chipset reserved memory size */ + uint32_t signature; /* EBDA signature */ + uint32_t cbmem_top; /* coreboot memory start */ }; #endif diff --git a/src/soc/intel/icelake/memmap.c b/src/soc/intel/icelake/memmap.c index 76a8128520..a4fd2e8a48 100644 --- a/src/soc/intel/icelake/memmap.c +++ b/src/soc/intel/icelake/memmap.c @@ -14,121 +14,15 @@ */ #include -#include #include -#include -#include -#include -#include -#include #include #include #include -#include -#include -#include #include -/* Calculate ME Stolen size */ -static size_t get_imr_size(void) -{ - size_t imr_size; - - /* ME stolen memory */ - imr_size = MCHBAR32(IMRLIMIT) - MCHBAR32(IMRBASE); - - return imr_size; -} - -/* Calculate PRMRR size based on user input PRMRR size and alignment */ -static size_t get_prmrr_size(uintptr_t dram_base, - const struct soc_intel_icelake_config *config) -{ - uintptr_t prmrr_base = dram_base; - size_t prmrr_size; - - prmrr_size = config->PrmrrSize; - - /* Allocate PRMRR memory for C6DRAM */ - if (!prmrr_size) { - if (config->enable_c6dram) - prmrr_size = 1*MiB; - else - return 0; - } - - /* - * PRMRR Sizes that are > 1MB and < 32MB are - * not supported and will fail out. - */ - if ((prmrr_size > 1*MiB) && (prmrr_size < 32*MiB)) - die("PRMRR Sizes that are > 1MB and < 32MB are not" - "supported!\n"); - - prmrr_base -= prmrr_size; - if (prmrr_size >= 32*MiB) - prmrr_base = ALIGN_DOWN(prmrr_base, 128*MiB); - else - prmrr_base = ALIGN_DOWN(prmrr_base, 16*MiB); - /* PRMRR Area Size */ - prmrr_size = dram_base - prmrr_base; - - return prmrr_size; -} - -/* Calculate Intel Traditional Memory size based on GSM, DSM, TSEG and DPR. */ -static size_t calculate_traditional_mem_size(uintptr_t dram_base, - const struct device *dev) -{ - uintptr_t traditional_mem_base = dram_base; - size_t traditional_mem_size; - - if (dev->enabled) { - /* Read BDSM from Host Bridge */ - traditional_mem_base -= sa_get_dsm_size(); - - /* Read BGSM from Host Bridge */ - traditional_mem_base -= sa_get_gsm_size(); - } - /* Get TSEG size */ - traditional_mem_base -= sa_get_tseg_size(); - - /* Get DPR size */ - if (CONFIG(SA_ENABLE_DPR)) - traditional_mem_base -= sa_get_dpr_size(); - - /* Traditional Area Size */ - traditional_mem_size = dram_base - traditional_mem_base; - - return traditional_mem_size; -} - -/* - * Calculate Intel Reserved Memory size based on - * PRMRR size, Me stolen memory and PTT selection. - */ -static size_t calculate_reserved_mem_size(uintptr_t dram_base, - const struct device *dev) -{ - uintptr_t reserve_mem_base = dram_base; - size_t reserve_mem_size; - const struct soc_intel_icelake_config *config; - - config = config_of(dev); - - /* Get PRMRR size */ - reserve_mem_base -= get_prmrr_size(reserve_mem_base, config); - - /* Get Tracehub size */ - reserve_mem_base -= get_imr_size(); - - /* Traditional Area Size */ - reserve_mem_size = dram_base - reserve_mem_base; - - return reserve_mem_size; -} - /* + * Fill up memory layout information + * * Host Memory Map: * * +--------------------------+ TOUUD @@ -160,37 +54,12 @@ static size_t calculate_reserved_mem_size(uintptr_t dram_base, * the base registers from each other to determine sizes of the regions. In * other words, the memory map is in a fixed order no matter what. */ -static uintptr_t calculate_dram_base(size_t *reserved_mem_size) -{ - uintptr_t dram_base; - const struct device *dev; - - dev = pcidev_on_root(SA_DEV_SLOT_IGD, 0); - if (!dev) - die_with_post_code(POST_HW_INIT_FAILURE, - "ERROR - IGD device not found!"); - - /* Read TOLUD from Host Bridge offset */ - dram_base = sa_get_tolud_base(); - - /* Get Intel Traditional Memory Range Size */ - dram_base -= calculate_traditional_mem_size(dram_base, dev); - - /* Get Intel Reserved Memory Range Size */ - *reserved_mem_size = calculate_reserved_mem_size(dram_base, dev); - - dram_base -= *reserved_mem_size; - - return dram_base; -} - -/* Fill up memory layout information */ void fill_soc_memmap_ebda(struct ebda_config *cfg) { - size_t chipset_mem_size; + struct range_entry tolum; - cfg->tolum_base = calculate_dram_base(&chipset_mem_size); - cfg->reserved_mem_size = chipset_mem_size; + fsp_find_bootloader_tolum(&tolum); + cfg->cbmem_top = range_entry_end(&tolum); } void cbmem_top_init(void) @@ -232,5 +101,5 @@ void *cbmem_top_chipset(void) retrieve_ebda_object(&ebda_cfg); - return (void *)(uintptr_t)ebda_cfg.tolum_base; + return (void *)(uintptr_t)ebda_cfg.cbmem_top; } diff --git a/src/soc/intel/skylake/include/soc/ebda.h b/src/soc/intel/skylake/include/soc/ebda.h index ad62394588..4ed6566838 100644 --- a/src/soc/intel/skylake/include/soc/ebda.h +++ b/src/soc/intel/skylake/include/soc/ebda.h @@ -19,9 +19,8 @@ #include struct ebda_config { - uint32_t signature; /* 0x00 - EBDA signature */ - uint32_t tolum_base; /* 0x04 - coreboot memory start */ - uint32_t reserved_mem_size; /* 0x08 - chipset reserved memory size */ + uint32_t signature; /* EBDA signature */ + uint32_t cbmem_top; /* coreboot memory start */ }; #endif diff --git a/src/soc/intel/skylake/memmap.c b/src/soc/intel/skylake/memmap.c index 09dc6e9f0d..63e7acdb85 100644 --- a/src/soc/intel/skylake/memmap.c +++ b/src/soc/intel/skylake/memmap.c @@ -15,148 +15,15 @@ */ #include -#include -#include #include -#include -#include -#include -#include -#include +#include #include #include -#include -#include -#include #include -#include "chip.h" - -static bool is_ptt_enable(void) -{ - if ((read32((void *)PTT_TXT_BASE_ADDRESS) & PTT_PRESENT) == - PTT_PRESENT) - return true; - - return false; -} - -/* Calculate PTT size */ -static size_t get_ptt_size(void) -{ - /* Allocate 4KB for PTT if enabled */ - return is_ptt_enable() ? 4*KiB : 0; -} - -/* Calculate Trace Hub size */ -static size_t get_tracehub_size(uintptr_t dram_base, - const struct soc_intel_skylake_config *config) -{ - uintptr_t tracehub_base = dram_base; - size_t tracehub_size = 0; - - if (!config->ProbelessTrace) - return 0; - - /* GDXC MOT */ - tracehub_base -= GDXC_MOT_MEMORY_SIZE; - /* Round down to natural boundary according to PSMI size */ - tracehub_base = ALIGN_DOWN(tracehub_base, PSMI_BUFFER_AREA_SIZE); - /* GDXC IOT */ - tracehub_base -= GDXC_IOT_MEMORY_SIZE; - /* PSMI buffer area */ - tracehub_base -= PSMI_BUFFER_AREA_SIZE; - - /* Tracehub Area Size */ - tracehub_size = dram_base - tracehub_base; - - return tracehub_size; -} - -/* Calculate PRMRR size based on user input PRMRR size and alignment */ -static size_t get_prmrr_size(uintptr_t dram_base, - const struct soc_intel_skylake_config *config) -{ - uintptr_t prmrr_base = dram_base; - size_t prmrr_size = config->PrmrrSize; - - if (!prmrr_size) - return 0; - - /* - * PRMRR Sizes that are > 1MB and < 32MB are - * not supported and will fail out. - */ - if ((prmrr_size > 1*MiB) && (prmrr_size < 32*MiB)) - die("PRMRR Sizes that are > 1MB and < 32MB are not" - "supported!\n"); - - prmrr_base -= prmrr_size; - if (prmrr_size >= 32*MiB) - prmrr_base = ALIGN_DOWN(prmrr_base, 128*MiB); - - /* PRMRR Area Size */ - prmrr_size = dram_base - prmrr_base; - - return prmrr_size; -} - -/* Calculate Intel Traditional Memory size based on GSM, DSM, TSEG and DPR. */ -static size_t calculate_traditional_mem_size(uintptr_t dram_base) -{ - const struct device *igd_dev = pcidev_path_on_root(SA_DEVFN_IGD); - uintptr_t traditional_mem_base = dram_base; - size_t traditional_mem_size; - - if (igd_dev && igd_dev->enabled) { - /* Read BDSM from Host Bridge */ - traditional_mem_base -= sa_get_dsm_size(); - - /* Read BGSM from Host Bridge */ - traditional_mem_base -= sa_get_gsm_size(); - } - /* Get TSEG size */ - traditional_mem_base -= sa_get_tseg_size(); - - /* Get DPR size */ - if (CONFIG(SA_ENABLE_DPR)) - traditional_mem_base -= sa_get_dpr_size(); - - /* Traditional Area Size */ - traditional_mem_size = dram_base - traditional_mem_base; - - return traditional_mem_size; -} - -/* - * Calculate Intel Reserved Memory size based on - * PRMRR size, Trace Hub config and PTT selection. - */ -static size_t calculate_reserved_mem_size(uintptr_t dram_base) -{ - const struct device *dev = pcidev_path_on_root(SA_DEVFN_ROOT); - uintptr_t reserve_mem_base = dram_base; - size_t reserve_mem_size; - const struct soc_intel_skylake_config *config; - - config = config_of(dev); - - /* Get PRMRR size */ - reserve_mem_base -= get_prmrr_size(reserve_mem_base, config); - - /* Get Tracehub size */ - reserve_mem_base -= get_tracehub_size(reserve_mem_base, config); - - /* Get PTT size */ - reserve_mem_base -= get_ptt_size(); - - /* Traditional Area Size */ - reserve_mem_size = dram_base - reserve_mem_base; - - return reserve_mem_size; -} - /* + * Fill up memory layout information + * * Host Memory Map: * * +--------------------------+ TOUUD @@ -174,8 +41,8 @@ static size_t calculate_reserved_mem_size(uintptr_t dram_base) * +--------------------------+ DPR * | PRM (C6DRAM/SGX) | * +--------------------------+ PRMRR - * | Trace Memory | - * +--------------------------+ Probless Trace + * | ME Stolen Memory | + * +--------------------------+ ME Stolen * | PTT | * +--------------------------+ top_of_ram * | Reserved - FSP/CBMEM | @@ -188,31 +55,12 @@ static size_t calculate_reserved_mem_size(uintptr_t dram_base) * the base registers from each other to determine sizes of the regions. In * other words, the memory map is in a fixed order no matter what. */ -static uintptr_t calculate_dram_base(size_t *reserved_mem_size) -{ - uintptr_t dram_base; - - /* Read TOLUD from Host Bridge offset */ - dram_base = sa_get_tolud_base(); - - /* Get Intel Traditional Memory Range Size */ - dram_base -= calculate_traditional_mem_size(dram_base); - - /* Get Intel Reserved Memory Range Size */ - *reserved_mem_size = calculate_reserved_mem_size(dram_base); - - dram_base -= *reserved_mem_size; - - return dram_base; -} - -/* Fill up memory layout information */ void fill_soc_memmap_ebda(struct ebda_config *cfg) { - size_t chipset_mem_size; + struct range_entry tolum; - cfg->tolum_base = calculate_dram_base(&chipset_mem_size); - cfg->reserved_mem_size = chipset_mem_size; + fsp_find_bootloader_tolum(&tolum); + cfg->cbmem_top = range_entry_end(&tolum); } void cbmem_top_init(void) @@ -254,5 +102,5 @@ void *cbmem_top_chipset(void) retrieve_ebda_object(&ebda_cfg); - return (void *)(uintptr_t)ebda_cfg.tolum_base; + return (void *)(uintptr_t)ebda_cfg.cbmem_top; } From e75a64f822931a5fbdd80f20c4d168a5c346e01a Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Michael=20Niew=C3=B6hner?= Date: Sat, 19 Oct 2019 15:17:06 +0200 Subject: [PATCH 0002/1242] soc/intel: skl,cnl,icl: consolidate ebda and memmap MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit As of CB:36136 ebda and memmap are identical for skl, cnl and icl, thus move them to common code. Tested successfully on X11SSM-F Change-Id: I9a20c814d2a6874fcb4ff99ef1a7825d891f74e2 Signed-off-by: Michael Niewöhner Reviewed-on: https://review.coreboot.org/c/coreboot/+/36137 Reviewed-by: Nico Huber Tested-by: build bot (Jenkins) --- src/soc/intel/cannonlake/Makefile.inc | 4 - src/soc/intel/cannonlake/memmap.c | 106 ------------------ src/soc/intel/common/block/ebda/ebda.c | 26 +---- .../common/block/include/intelblocks/ebda.h | 49 ++------ .../intel/common/block/systemagent/memmap.c | 67 +++++++++++ src/soc/intel/icelake/Makefile.inc | 5 - src/soc/intel/icelake/memmap.c | 105 ----------------- src/soc/intel/skylake/Makefile.inc | 3 - src/soc/intel/skylake/memmap.c | 106 ------------------ 9 files changed, 80 insertions(+), 391 deletions(-) delete mode 100644 src/soc/intel/cannonlake/memmap.c delete mode 100644 src/soc/intel/icelake/memmap.c delete mode 100644 src/soc/intel/skylake/memmap.c diff --git a/src/soc/intel/cannonlake/Makefile.inc b/src/soc/intel/cannonlake/Makefile.inc index 5bc9409521..0fcbcd15e6 100644 --- a/src/soc/intel/cannonlake/Makefile.inc +++ b/src/soc/intel/cannonlake/Makefile.inc @@ -16,7 +16,6 @@ bootblock-y += pmutil.c bootblock-y += bootblock/report_platform.c bootblock-y += gspi.c bootblock-y += i2c.c -bootblock-y += memmap.c bootblock-y += spi.c bootblock-y += lpc.c bootblock-y += p2sb.c @@ -26,7 +25,6 @@ romstage-y += cnl_memcfg_init.c romstage-y += gspi.c romstage-y += i2c.c romstage-y += lpc.c -romstage-y += memmap.c romstage-y += pmutil.c romstage-y += reset.c romstage-y += spi.c @@ -44,7 +42,6 @@ ramstage-y += i2c.c ramstage-y += lockdown.c ramstage-y += lpc.c ramstage-y += me.c -ramstage-y += memmap.c ramstage-y += nhlt.c ramstage-y += p2sb.c ramstage-y += pmc.c @@ -66,7 +63,6 @@ smm-y += smihandler.c smm-y += uart.c smm-y += xhci.c -postcar-y += memmap.c postcar-y += pmutil.c postcar-y += i2c.c postcar-y += gspi.c diff --git a/src/soc/intel/cannonlake/memmap.c b/src/soc/intel/cannonlake/memmap.c deleted file mode 100644 index 63e7acdb85..0000000000 --- a/src/soc/intel/cannonlake/memmap.c +++ /dev/null @@ -1,106 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2014 Google Inc. - * Copyright (C) 2015-2017 Intel Corporation. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include -#include -#include -#include - -/* - * Fill up memory layout information - * - * Host Memory Map: - * - * +--------------------------+ TOUUD - * | | - * +--------------------------+ 4GiB - * | PCI Address Space | - * +--------------------------+ TOLUD (also maps into MC address space) - * | iGD | - * +--------------------------+ BDSM - * | GTT | - * +--------------------------+ BGSM - * | TSEG | - * +--------------------------+ TSEGMB - * | DMA Protected Region | - * +--------------------------+ DPR - * | PRM (C6DRAM/SGX) | - * +--------------------------+ PRMRR - * | ME Stolen Memory | - * +--------------------------+ ME Stolen - * | PTT | - * +--------------------------+ top_of_ram - * | Reserved - FSP/CBMEM | - * +--------------------------+ TOLUM - * | Usage DRAM | - * +--------------------------+ 0 - * - * Some of the base registers above can be equal making the size of those - * regions 0. The reason is because the memory controller internally subtracts - * the base registers from each other to determine sizes of the regions. In - * other words, the memory map is in a fixed order no matter what. - */ -void fill_soc_memmap_ebda(struct ebda_config *cfg) -{ - struct range_entry tolum; - - fsp_find_bootloader_tolum(&tolum); - cfg->cbmem_top = range_entry_end(&tolum); -} - -void cbmem_top_init(void) -{ - /* Fill up EBDA area */ - fill_ebda_area(); -} - -/* - * +-------------------------+ Top of RAM (aligned) - * | System Management Mode | - * | code and data | Length: CONFIG_TSEG_SIZE - * | (TSEG) | - * +-------------------------+ SMM base (aligned) - * | | - * | Chipset Reserved Memory | - * | | - * +-------------------------+ top_of_ram (aligned) - * | | - * | CBMEM Root | - * | | - * +-------------------------+ - * | | - * | FSP Reserved Memory | - * | | - * +-------------------------+ - * | | - * | Various CBMEM Entries | - * | | - * +-------------------------+ top_of_stack (8 byte aligned) - * | | - * | stack (CBMEM Entry) | - * | | - * +-------------------------+ - */ -void *cbmem_top_chipset(void) -{ - struct ebda_config ebda_cfg; - - retrieve_ebda_object(&ebda_cfg); - - return (void *)(uintptr_t)ebda_cfg.cbmem_top; -} diff --git a/src/soc/intel/common/block/ebda/ebda.c b/src/soc/intel/common/block/ebda/ebda.c index 6b0bd6752b..072023cd16 100644 --- a/src/soc/intel/common/block/ebda/ebda.c +++ b/src/soc/intel/common/block/ebda/ebda.c @@ -17,34 +17,14 @@ #include #include -/* - * Mainboard Override function - * - * Mainboard directory may implement below functionality for romstage. - */ - -/* Fill up EBDA structure inside Mainboard directory */ -__weak void create_mainboard_ebda(struct ebda_config *cfg) -{ - /* no-op */ -} - -static void create_soc_ebda(struct ebda_config *cfg) -{ - /* Create EBDA header */ - cfg->signature = EBDA_SIGNATURE; - /* Fill up memory layout information */ - fill_soc_memmap_ebda(cfg); -} - -void fill_ebda_area(void) +void initialize_ebda_area(void) { struct ebda_config ebda_cfg; /* Initialize EBDA area early during romstage. */ setup_default_ebda(); - create_soc_ebda(&ebda_cfg); - create_mainboard_ebda(&ebda_cfg); + ebda_cfg.signature = EBDA_SIGNATURE; + fill_memmap_ebda(&ebda_cfg); write_ebda_data(&ebda_cfg, sizeof(ebda_cfg)); } diff --git a/src/soc/intel/common/block/include/intelblocks/ebda.h b/src/soc/intel/common/block/include/intelblocks/ebda.h index 16124df7e0..48904f4705 100644 --- a/src/soc/intel/common/block/include/intelblocks/ebda.h +++ b/src/soc/intel/common/block/include/intelblocks/ebda.h @@ -16,52 +16,23 @@ #ifndef SOC_INTEL_COMMON_BLOCK_EBDA_H #define SOC_INTEL_COMMON_BLOCK_EBDA_H -#include - #define EBDA_SIGNATURE 0xebdaebda -/* - * Mainboard Override function - * - * Mainboard directory may implement below functionality for romstage. - */ +/* EBDA structure */ +struct ebda_config { + uint32_t signature; /* EBDA signature */ + uint32_t cbmem_top; /* coreboot memory start */ +}; -/* Fill up EBDA structure inside Mainboard directory */ -void create_mainboard_ebda(struct ebda_config *cfg); +/* Initialize EBDA and store structure into EBDA area */ +void initialize_ebda_area(void); /* - * SoC overrides - * - * All new SoC must implement below functionality for romstage. - */ -void fill_soc_memmap_ebda(struct ebda_config *cfg); - -/* - * API to perform below operation - * 1. Initialize EBDA area - * 2. Fill up EBDA structure inside SOC directory - * 3. Fill up EBDA structure inside Mainboard directory - * 4. Store EBDA structure into EBDA area - */ -void fill_ebda_area(void); - -/* Fill the ebda object pointed to by cfg. Object will be zero filled + * Fill the ebda object pointed to by cfg. Object will be zero filled * if signature check fails. */ void retrieve_ebda_object(struct ebda_config *cfg); -/* - * EBDA structure - * - * SOC should implement EBDA structure as per need - * as below. - * - * Note: First 4 bytes should be reserved for signature as - * 0xEBDA - * - * struct ebda_config { - * uint32_t signature; - * - * }; - */ +/* API for filling ebda with data in romstage */ +void fill_memmap_ebda(struct ebda_config *cfg); #endif diff --git a/src/soc/intel/common/block/systemagent/memmap.c b/src/soc/intel/common/block/systemagent/memmap.c index ea22aa6d18..809c13a1ff 100644 --- a/src/soc/intel/common/block/systemagent/memmap.c +++ b/src/soc/intel/common/block/systemagent/memmap.c @@ -19,15 +19,82 @@ #include #include #include +#include +#include #include #include +/* + * Expected Host Memory Map (we don't know 100% and not all regions are present on all SoCs): + * + * +---------------------------+ TOUUD + * | | + * +---------------------------+ TOM (if mem > 4GB) + * | CSME UMA (if mem > 4 GiB) | + * +---------------------------+ TOUUD + * | | + * +---------------------------+ 4GiB + * | PCI Address Space | + * +---------------------------+ TOM (if mem < 4GB) + * | CSME UMA (if mem < 4 GiB) | + * +---------------------------+ TOLUD (also maps into MC address space) + * | iGD / DSM | + * +---------------------------+ BDSM + * | GTT / GSM | + * +---------------------------+ TOLM + * | TSEG | + * +---------------------------+ TSEGMB + * | DMA Protected Region | + * +---------------------------+ DPR + * | PRM (C6DRAM/SGX) | + * +---------------------------+ PRMRR + * | Probeless Trace | + * +---------------------------+ ME Stolen + * | PTT | + * +---------------------------+ TOLUM / top_of_ram / cbmem_top + * | CBMEM Root | + * +---------------------------+ + * | FSP Reserved Memory | + * +---------------------------+ + * | various CBMEM entries | + * +---------------------------+ top_of_stack (8 byte aligned) + * | stack (CBMEM entry) | + * +---------------------------+ FSP TOLUM + * | | + * +---------------------------+ 0 + */ + void smm_region(uintptr_t *start, size_t *size) { *start = sa_get_tseg_base(); *size = sa_get_tseg_size(); } +#if CONFIG(SOC_INTEL_COMMON_BLOCK_EBDA) +void fill_memmap_ebda(struct ebda_config *cfg) +{ + struct range_entry tolum; + + fsp_find_bootloader_tolum(&tolum); + cfg->cbmem_top = range_entry_end(&tolum); +} + +void cbmem_top_init(void) +{ + /* Initialize EBDA area */ + initialize_ebda_area(); +} + +void *cbmem_top_chipset(void) +{ + struct ebda_config ebda_cfg; + + retrieve_ebda_object(&ebda_cfg); + + return (void *)(uintptr_t)ebda_cfg.cbmem_top; +} +#endif + void fill_postcar_frame(struct postcar_frame *pcf) { uintptr_t top_of_ram; diff --git a/src/soc/intel/icelake/Makefile.inc b/src/soc/intel/icelake/Makefile.inc index a4ebd20580..67a3a7114a 100644 --- a/src/soc/intel/icelake/Makefile.inc +++ b/src/soc/intel/icelake/Makefile.inc @@ -21,12 +21,10 @@ bootblock-y += bootblock/pch.c bootblock-y += bootblock/report_platform.c bootblock-y += espi.c bootblock-y += gpio.c -bootblock-y += memmap.c bootblock-y += p2sb.c romstage-y += espi.c romstage-y += gpio.c -romstage-y += memmap.c romstage-y += reset.c ramstage-y += acpi.c @@ -39,7 +37,6 @@ ramstage-y += fsp_params.c ramstage-y += gpio.c ramstage-y += graphics.c ramstage-y += lockdown.c -ramstage-y += memmap.c ramstage-y += p2sb.c ramstage-y += pmc.c ramstage-y += reset.c @@ -54,8 +51,6 @@ smm-y += pmutil.c smm-y += smihandler.c smm-y += uart.c -postcar-y += memmap.c - CPPFLAGS_common += -I$(src)/soc/intel/icelake CPPFLAGS_common += -I$(src)/soc/intel/icelake/include diff --git a/src/soc/intel/icelake/memmap.c b/src/soc/intel/icelake/memmap.c deleted file mode 100644 index a4fd2e8a48..0000000000 --- a/src/soc/intel/icelake/memmap.c +++ /dev/null @@ -1,105 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2018 Intel Corp. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include -#include -#include -#include - -/* - * Fill up memory layout information - * - * Host Memory Map: - * - * +--------------------------+ TOUUD - * | | - * +--------------------------+ 4GiB - * | PCI Address Space | - * +--------------------------+ TOLUD (also maps into MC address space) - * | iGD | - * +--------------------------+ BDSM - * | GTT | - * +--------------------------+ BGSM - * | TSEG | - * +--------------------------+ TSEGMB - * | DMA Protected Region | - * +--------------------------+ DPR - * | PRM (C6DRAM/SGX) | - * +--------------------------+ PRMRR - * | ME Stolen Memory | - * +--------------------------+ ME Stolen - * | PTT | - * +--------------------------+ top_of_ram - * | Reserved - FSP/CBMEM | - * +--------------------------+ TOLUM - * | Usage DRAM | - * +--------------------------+ 0 - * - * Some of the base registers above can be equal making the size of those - * regions 0. The reason is because the memory controller internally subtracts - * the base registers from each other to determine sizes of the regions. In - * other words, the memory map is in a fixed order no matter what. - */ -void fill_soc_memmap_ebda(struct ebda_config *cfg) -{ - struct range_entry tolum; - - fsp_find_bootloader_tolum(&tolum); - cfg->cbmem_top = range_entry_end(&tolum); -} - -void cbmem_top_init(void) -{ - /* Fill up EBDA area */ - fill_ebda_area(); -} - -/* - * +-------------------------+ Top of RAM (aligned) - * | System Management Mode | - * | code and data | Length: CONFIG_TSEG_SIZE - * | (TSEG) | - * +-------------------------+ SMM base (aligned) - * | | - * | Chipset Reserved Memory | - * | | - * +-------------------------+ top_of_ram (aligned) - * | | - * | CBMEM Root | - * | | - * +-------------------------+ - * | | - * | FSP Reserved Memory | - * | | - * +-------------------------+ - * | | - * | Various CBMEM Entries | - * | | - * +-------------------------+ top_of_stack (8 byte aligned) - * | | - * | stack (CBMEM Entry) | - * | | - * +-------------------------+ - */ -void *cbmem_top_chipset(void) -{ - struct ebda_config ebda_cfg; - - retrieve_ebda_object(&ebda_cfg); - - return (void *)(uintptr_t)ebda_cfg.cbmem_top; -} diff --git a/src/soc/intel/skylake/Makefile.inc b/src/soc/intel/skylake/Makefile.inc index cb0906c1d5..b049e84795 100644 --- a/src/soc/intel/skylake/Makefile.inc +++ b/src/soc/intel/skylake/Makefile.inc @@ -33,7 +33,6 @@ verstage-y += uart.c romstage-y += gpio.c romstage-y += gspi.c romstage-y += i2c.c -romstage-y += memmap.c romstage-y += me.c romstage-y += pmc.c romstage-y += pmutil.c @@ -54,7 +53,6 @@ ramstage-y += irq.c ramstage-y += lockdown.c ramstage-y += lpc.c ramstage-y += me.c -ramstage-y += memmap.c ramstage-y += p2sb.c ramstage-y += pmc.c ramstage-y += pmutil.c @@ -76,7 +74,6 @@ smm-y += smihandler.c smm-y += uart.c smm-y += xhci.c -postcar-y += memmap.c postcar-y += gspi.c postcar-y += spi.c postcar-y += i2c.c diff --git a/src/soc/intel/skylake/memmap.c b/src/soc/intel/skylake/memmap.c deleted file mode 100644 index 63e7acdb85..0000000000 --- a/src/soc/intel/skylake/memmap.c +++ /dev/null @@ -1,106 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2014 Google Inc. - * Copyright (C) 2015-2017 Intel Corporation. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include -#include -#include -#include - -/* - * Fill up memory layout information - * - * Host Memory Map: - * - * +--------------------------+ TOUUD - * | | - * +--------------------------+ 4GiB - * | PCI Address Space | - * +--------------------------+ TOLUD (also maps into MC address space) - * | iGD | - * +--------------------------+ BDSM - * | GTT | - * +--------------------------+ BGSM - * | TSEG | - * +--------------------------+ TSEGMB - * | DMA Protected Region | - * +--------------------------+ DPR - * | PRM (C6DRAM/SGX) | - * +--------------------------+ PRMRR - * | ME Stolen Memory | - * +--------------------------+ ME Stolen - * | PTT | - * +--------------------------+ top_of_ram - * | Reserved - FSP/CBMEM | - * +--------------------------+ TOLUM - * | Usage DRAM | - * +--------------------------+ 0 - * - * Some of the base registers above can be equal making the size of those - * regions 0. The reason is because the memory controller internally subtracts - * the base registers from each other to determine sizes of the regions. In - * other words, the memory map is in a fixed order no matter what. - */ -void fill_soc_memmap_ebda(struct ebda_config *cfg) -{ - struct range_entry tolum; - - fsp_find_bootloader_tolum(&tolum); - cfg->cbmem_top = range_entry_end(&tolum); -} - -void cbmem_top_init(void) -{ - /* Fill up EBDA area */ - fill_ebda_area(); -} - -/* - * +-------------------------+ Top of RAM (aligned) - * | System Management Mode | - * | code and data | Length: CONFIG_TSEG_SIZE - * | (TSEG) | - * +-------------------------+ SMM base (aligned) - * | | - * | Chipset Reserved Memory | - * | | - * +-------------------------+ top_of_ram (aligned) - * | | - * | CBMEM Root | - * | | - * +-------------------------+ - * | | - * | FSP Reserved Memory | - * | | - * +-------------------------+ - * | | - * | Various CBMEM Entries | - * | | - * +-------------------------+ top_of_stack (8 byte aligned) - * | | - * | stack (CBMEM Entry) | - * | | - * +-------------------------+ - */ -void *cbmem_top_chipset(void) -{ - struct ebda_config ebda_cfg; - - retrieve_ebda_object(&ebda_cfg); - - return (void *)(uintptr_t)ebda_cfg.cbmem_top; -} From 7736bfc443a913a9cde46406bcfc38015ec71f47 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Michael=20Niew=C3=B6hner?= Date: Tue, 22 Oct 2019 23:05:06 +0200 Subject: [PATCH 0003/1242] soc/intel/sgx: convert SGX and PRMRR devicetree options to Kconfig MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The devicetree is not made for user-choosable options, thus introduce Kconfig options for both SGX and the corresponding PRMRR size. The PRMRR size Kconfig has been implemented as a maximum value. At runtime the final PRMRR size gets selected by checking the supported values in MSR_PRMRR_VALID_CONFIG and trying to select the value nearest to the chosen one. When "Maximum" is chosen, the highest possibly value from the MSR gets used. When a too strict limit is set, coreboot will die, printing an error message. Tested successfully on X11SSM-F Change-Id: I5f08e85898304bba6680075ca5d6bce26aef9a4d Signed-off-by: Michael Niewöhner Reviewed-on: https://review.coreboot.org/c/coreboot/+/35799 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber --- .../variants/baseboard/devicetree.cb | 2 - src/mainboard/intel/glkrvp/Kconfig | 4 ++ .../glkrvp/variants/baseboard/devicetree.cb | 8 --- .../icelake_rvp/variants/icl_u/devicetree.cb | 2 - .../icelake_rvp/variants/icl_y/devicetree.cb | 2 - .../x11-lga1151-series/devicetree.cb | 4 -- src/soc/intel/apollolake/Makefile.inc | 1 + src/soc/intel/apollolake/chip.h | 12 ---- src/soc/intel/apollolake/cpu.c | 11 +--- src/soc/intel/apollolake/memmap.c | 7 +-- src/soc/intel/apollolake/romstage.c | 4 +- src/soc/intel/cannonlake/chip.h | 7 +-- .../intel/cannonlake/romstage/fsp_params.c | 3 +- src/soc/intel/common/block/cpu/Makefile.inc | 1 + src/soc/intel/common/block/cpu/cpulib.c | 41 ++++++++++++ .../common/block/include/intelblocks/cpulib.h | 4 ++ .../common/block/include/intelblocks/msr.h | 1 + src/soc/intel/common/block/sgx/Kconfig | 62 ++++++++++++++++++- src/soc/intel/common/block/sgx/sgx.c | 2 +- src/soc/intel/icelake/chip.h | 8 +-- src/soc/intel/icelake/romstage/fsp_params.c | 3 +- src/soc/intel/skylake/acpi.c | 2 +- src/soc/intel/skylake/chip.h | 11 ---- src/soc/intel/skylake/cpu.c | 7 +-- src/soc/intel/skylake/romstage/romstage.c | 3 +- 25 files changed, 130 insertions(+), 82 deletions(-) diff --git a/src/mainboard/google/dragonegg/variants/baseboard/devicetree.cb b/src/mainboard/google/dragonegg/variants/baseboard/devicetree.cb index bcad954885..d77633ddd7 100644 --- a/src/mainboard/google/dragonegg/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/dragonegg/variants/baseboard/devicetree.cb @@ -44,8 +44,6 @@ chip soc/intel/icelake # EC memory map range is 0x900-0x9ff register "gen3_dec" = "0x00fc0901" - register "PrmrrSize" = "0x10000000" - register "PcieRpEnable[0]" = "1" register "PcieRpEnable[1]" = "1" register "PcieRpEnable[2]" = "1" diff --git a/src/mainboard/intel/glkrvp/Kconfig b/src/mainboard/intel/glkrvp/Kconfig index 3380762736..ebb5a3a07b 100644 --- a/src/mainboard/intel/glkrvp/Kconfig +++ b/src/mainboard/intel/glkrvp/Kconfig @@ -86,4 +86,8 @@ config IS_GLK_RVP_1 bool "Is this RVP1?" default n +config SOC_INTEL_COMMON_BLOCK_SGX_ENABLE + bool + default y + endif # BOARD_INTEL_GLKRVP diff --git a/src/mainboard/intel/glkrvp/variants/baseboard/devicetree.cb b/src/mainboard/intel/glkrvp/variants/baseboard/devicetree.cb index d3d0b00c8e..c5ad27dca6 100644 --- a/src/mainboard/intel/glkrvp/variants/baseboard/devicetree.cb +++ b/src/mainboard/intel/glkrvp/variants/baseboard/devicetree.cb @@ -97,14 +97,6 @@ chip soc/intel/apollolake # Minimum SLP S3 assertion width 28ms. register "slp_s3_assertion_width_usecs" = "28000" - register "sgx_enable" = "1" - - # PRMRR size options - # 0x02000000 - 32MiB - # 0x04000000 - 64MiB - # 0x08000000 - 128MiB - register "PrmrrSize" = "128 * MiB" - register "pnp_settings" = "PNP_PERF_POWER" device domain 0 on diff --git a/src/mainboard/intel/icelake_rvp/variants/icl_u/devicetree.cb b/src/mainboard/intel/icelake_rvp/variants/icl_u/devicetree.cb index 6d7fad7623..12accedec4 100644 --- a/src/mainboard/intel/icelake_rvp/variants/icl_u/devicetree.cb +++ b/src/mainboard/intel/icelake_rvp/variants/icl_u/devicetree.cb @@ -48,8 +48,6 @@ chip soc/intel/icelake register "PchHdaDspEnable" = "1" register "PchHdaAudioLinkHda" = "1" - register "PrmrrSize" = "0x10000000" - register "PcieRpEnable[0]" = "1" register "PcieRpEnable[1]" = "1" register "PcieRpEnable[2]" = "1" diff --git a/src/mainboard/intel/icelake_rvp/variants/icl_y/devicetree.cb b/src/mainboard/intel/icelake_rvp/variants/icl_y/devicetree.cb index 4f4130853e..b12c0f7b6c 100644 --- a/src/mainboard/intel/icelake_rvp/variants/icl_y/devicetree.cb +++ b/src/mainboard/intel/icelake_rvp/variants/icl_y/devicetree.cb @@ -48,8 +48,6 @@ chip soc/intel/icelake register "PchHdaDspEnable" = "1" register "PchHdaAudioLinkHda" = "1" - register "PrmrrSize" = "0x10000000" - register "PcieRpEnable[0]" = "1" register "PcieRpEnable[1]" = "1" register "PcieRpEnable[2]" = "1" diff --git a/src/mainboard/supermicro/x11-lga1151-series/devicetree.cb b/src/mainboard/supermicro/x11-lga1151-series/devicetree.cb index 1b9dc271b6..b58fbf1470 100644 --- a/src/mainboard/supermicro/x11-lga1151-series/devicetree.cb +++ b/src/mainboard/supermicro/x11-lga1151-series/devicetree.cb @@ -17,10 +17,6 @@ chip soc/intel/skylake register "Device4Enable" = "1" register "SaGv" = "SaGv_Disabled" - # Enable SGX - register "sgx_enable" = "1" - register "PrmrrSize" = "128 * MiB" - register "pirqa_routing" = "PCH_IRQ11" register "pirqb_routing" = "PCH_IRQ10" register "pirqc_routing" = "PCH_IRQ11" diff --git a/src/soc/intel/apollolake/Makefile.inc b/src/soc/intel/apollolake/Makefile.inc index 5530e5c5ab..7655d5aa9a 100644 --- a/src/soc/intel/apollolake/Makefile.inc +++ b/src/soc/intel/apollolake/Makefile.inc @@ -1,5 +1,6 @@ ifeq ($(CONFIG_SOC_INTEL_APOLLOLAKE),y) +subdirs-y += ../../../cpu/intel/common subdirs-y += ../../../cpu/intel/microcode subdirs-y += ../../../cpu/intel/turbo subdirs-y += ../../../cpu/x86/lapic diff --git a/src/soc/intel/apollolake/chip.h b/src/soc/intel/apollolake/chip.h index 85cfff9af5..e5045d01b1 100644 --- a/src/soc/intel/apollolake/chip.h +++ b/src/soc/intel/apollolake/chip.h @@ -139,18 +139,6 @@ struct soc_intel_apollolake_config { /* GPIO SD card detect pin */ unsigned int sdcard_cd_gpio; - /* PRMRR size setting with three options - * 0x02000000 - 32MiB - * 0x04000000 - 64MiB - * 0x08000000 - 128MiB */ - uint32_t PrmrrSize; - - /* Enable SGX feature. - * Enabling SGX feature is 2 step process, - * (1) set sgx_enable = 1 - * (2) set PrmrrSize to supported size */ - uint8_t sgx_enable; - /* Select PNP Settings. * (0) Performance, * (1) Power diff --git a/src/soc/intel/apollolake/cpu.c b/src/soc/intel/apollolake/cpu.c index 6e826b863c..0b9466c4c5 100644 --- a/src/soc/intel/apollolake/cpu.c +++ b/src/soc/intel/apollolake/cpu.c @@ -72,13 +72,10 @@ static const struct reg_script core_msr_script[] = { void soc_core_init(struct device *cpu) { - config_t *conf = config_of_soc(); - /* Clear out pending MCEs */ /* TODO(adurbin): Some of these banks are core vs package scope. For now every CPU clears every bank. */ - if ((CONFIG(SOC_INTEL_COMMON_BLOCK_SGX) && conf->sgx_enable) || - acpi_get_sleep_type() == ACPI_S5) + if (CONFIG(SOC_INTEL_COMMON_BLOCK_SGX_ENABLE) || acpi_get_sleep_type() == ACPI_S5) mca_configure(); /* Set core MSRs */ @@ -91,7 +88,7 @@ void soc_core_init(struct device *cpu) enable_pm_timer_emulation(); /* Configure Core PRMRR for SGX. */ - if (CONFIG(SOC_INTEL_COMMON_BLOCK_SGX) && conf->sgx_enable) + if (CONFIG(SOC_INTEL_COMMON_BLOCK_SGX_ENABLE)) prmrr_core_configure(); /* Set Max Non-Turbo ratio if RAPL is disabled. */ @@ -255,11 +252,9 @@ static void relocation_handler(int cpu, uintptr_t curr_smbase, static void post_mp_init(void) { - config_t *conf = config_of_soc(); - smm_southbridge_enable(PWRBTN_EN | GBL_EN); - if (CONFIG(SOC_INTEL_COMMON_BLOCK_SGX) && conf->sgx_enable) + if (CONFIG(SOC_INTEL_COMMON_BLOCK_SGX_ENABLE)) mp_run_on_all_cpus(sgx_configure, NULL); } diff --git a/src/soc/intel/apollolake/memmap.c b/src/soc/intel/apollolake/memmap.c index 567ff1ebc6..de6a7d1f19 100644 --- a/src/soc/intel/apollolake/memmap.c +++ b/src/soc/intel/apollolake/memmap.c @@ -16,23 +16,20 @@ */ #include +#include #include #include "chip.h" void *cbmem_top_chipset(void) { - const config_t *config; void *tolum = (void *)sa_get_tseg_base(); if (!CONFIG(SOC_INTEL_GLK)) return tolum; - config = config_of_soc(); - /* FSP allocates 2x PRMRR Size Memory for alignment */ - if (config->sgx_enable) - tolum -= config->PrmrrSize * 2; + tolum -= get_prmrr_size() * 2; return tolum; } diff --git a/src/soc/intel/apollolake/romstage.c b/src/soc/intel/apollolake/romstage.c index 8418919bd2..258f4ffaf3 100644 --- a/src/soc/intel/apollolake/romstage.c +++ b/src/soc/intel/apollolake/romstage.c @@ -269,9 +269,7 @@ static void soc_memory_init_params(FSPM_UPD *mupd) /* Only for GLK */ FSP_M_CONFIG *m_cfg = &mupd->FspmConfig; - const config_t *config = config_of_soc(); - - m_cfg->PrmrrSize = config->PrmrrSize; + m_cfg->PrmrrSize = get_prmrr_size(); /* * CpuMemoryTest in FSP tests 0 to 1M of the RAM after MRC init. diff --git a/src/soc/intel/cannonlake/chip.h b/src/soc/intel/cannonlake/chip.h index b937699c3c..17afdd10da 100644 --- a/src/soc/intel/cannonlake/chip.h +++ b/src/soc/intel/cannonlake/chip.h @@ -261,12 +261,7 @@ struct soc_intel_cannonlake_config { /* Enable C6 DRAM */ uint8_t enable_c6dram; - /* - * PRMRR size setting with below options - * 0x00100000 - 1MiB - * 0x02000000 - 32MiB and beyond - */ - uint32_t PrmrrSize; + uint8_t PmTimerDisabled; /* diff --git a/src/soc/intel/cannonlake/romstage/fsp_params.c b/src/soc/intel/cannonlake/romstage/fsp_params.c index 3ba997df48..996c13577e 100644 --- a/src/soc/intel/cannonlake/romstage/fsp_params.c +++ b/src/soc/intel/cannonlake/romstage/fsp_params.c @@ -17,6 +17,7 @@ #include #include #include +#include #include #include #include @@ -48,7 +49,7 @@ static void soc_memory_init_params(FSP_M_CONFIG *m_cfg, const config_t *config) mask |= (1 << i); } m_cfg->PcieRpEnableMask = mask; - m_cfg->PrmrrSize = config->PrmrrSize; + m_cfg->PrmrrSize = get_prmrr_size(); m_cfg->EnableC6Dram = config->enable_c6dram; #if CONFIG(SOC_INTEL_COMETLAKE) m_cfg->SerialIoUartDebugControllerNumber = CONFIG_UART_FOR_CONSOLE; diff --git a/src/soc/intel/common/block/cpu/Makefile.inc b/src/soc/intel/common/block/cpu/Makefile.inc index a6c4f37cc4..f263053430 100644 --- a/src/soc/intel/common/block/cpu/Makefile.inc +++ b/src/soc/intel/common/block/cpu/Makefile.inc @@ -7,6 +7,7 @@ romstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_CAR) += car/exit_car.S romstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_CPU) += cpulib.c postcar-$(CONFIG_SOC_INTEL_COMMON_BLOCK_CAR) += car/exit_car.S +postcar-$(CONFIG_SOC_INTEL_COMMON_BLOCK_CPU) += cpulib.c postcar-$(CONFIG_FSP_CAR) += car/exit_car_fsp.S ramstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_CPU) += cpulib.c diff --git a/src/soc/intel/common/block/cpu/cpulib.c b/src/soc/intel/common/block/cpu/cpulib.c index 71e4dbf01b..89732f145a 100644 --- a/src/soc/intel/common/block/cpu/cpulib.c +++ b/src/soc/intel/common/block/cpu/cpulib.c @@ -325,3 +325,44 @@ void cpu_lt_lock_memory(void *unused) { msr_set_bit(MSR_LT_CONTROL, LT_CONTROL_LOCK_BIT); } + +int get_prmrr_size(void) +{ + msr_t msr; + int i; + int valid_size; + + if (CONFIG(SOC_INTEL_COMMON_BLOCK_SGX_PRMRR_DISABLED)) { + printk(BIOS_DEBUG, "PRMRR disabled by config.\n"); + return 0; + } + + msr = rdmsr(MSR_PRMRR_VALID_CONFIG); + if (!msr.lo) { + printk(BIOS_WARNING, "PRMRR not supported.\n"); + return 0; + } + + printk(BIOS_DEBUG, "MSR_PRMRR_VALID_CONFIG = 0x%08x\n", msr.lo); + + /* find the first (greatest) value that is lower than or equal to the selected size */ + for (i = 8; i >= 0; i--) { + valid_size = msr.lo & (1 << i); + + if (valid_size && valid_size <= CONFIG_SOC_INTEL_COMMON_BLOCK_SGX_PRMRR_SIZE) + break; + else if (i == 0) + valid_size = 0; + } + + /* die if we could not find a valid size within the limit */ + if (!valid_size) + die("Unsupported PRMRR size limit %i MiB, check your config!\n", + CONFIG_SOC_INTEL_COMMON_BLOCK_SGX_PRMRR_SIZE); + + printk(BIOS_DEBUG, "PRMRR size set to %i MiB\n", valid_size); + + valid_size *= MiB; + + return valid_size; +} diff --git a/src/soc/intel/common/block/include/intelblocks/cpulib.h b/src/soc/intel/common/block/include/intelblocks/cpulib.h index 1aa88e156d..a422094b26 100644 --- a/src/soc/intel/common/block/include/intelblocks/cpulib.h +++ b/src/soc/intel/common/block/include/intelblocks/cpulib.h @@ -18,6 +18,7 @@ #define SOC_INTEL_COMMON_BLOCK_CPULIB_H #include +#include /* * Set PERF_CTL MSR (0x199) P_Req with @@ -164,4 +165,7 @@ void mca_configure(void); /* Lock chipset memory registers to protect SMM */ void cpu_lt_lock_memory(void *unused); +/* Get the a supported PRMRR size in bytes with respect users choice */ +int get_prmrr_size(void); + #endif /* SOC_INTEL_COMMON_BLOCK_CPULIB_H */ diff --git a/src/soc/intel/common/block/include/intelblocks/msr.h b/src/soc/intel/common/block/include/intelblocks/msr.h index 3e67fd779d..8902d0992f 100644 --- a/src/soc/intel/common/block/include/intelblocks/msr.h +++ b/src/soc/intel/common/block/include/intelblocks/msr.h @@ -64,6 +64,7 @@ #define MSR_PRMRR_PHYS_MASK 0x1f5 #define PRMRR_PHYS_MASK_LOCK (1 << 10) #define PRMRR_PHYS_MASK_VALID (1 << 11) +#define MSR_PRMRR_VALID_CONFIG 0x1fb #define MSR_POWER_CTL 0x1fc #define POWER_CTL_C1E_MASK (1 << 1) #define MSR_EVICT_CTL 0x2e0 diff --git a/src/soc/intel/common/block/sgx/Kconfig b/src/soc/intel/common/block/sgx/Kconfig index 026c6afb0d..6e8323f333 100644 --- a/src/soc/intel/common/block/sgx/Kconfig +++ b/src/soc/intel/common/block/sgx/Kconfig @@ -4,9 +4,7 @@ config SOC_INTEL_COMMON_BLOCK_SGX select CPU_INTEL_COMMON_HYPERTHREADING default n help - Software Guard eXtension(SGX) Feature. Intel SGX is a set of new CPU - instructions that can be used by applications to set aside private - regions of code and data. + Intel Processor common SGX support config SOC_INTEL_COMMON_BLOCK_SGX_LOCK_MEMORY bool @@ -14,3 +12,61 @@ config SOC_INTEL_COMMON_BLOCK_SGX_LOCK_MEMORY default n help Lock memory before SGX activation. This is only needed if MCHECK does not do it. + +config SOC_INTEL_COMMON_BLOCK_SGX_ENABLE + bool "Enable Software Guard Extensions (SGX) if available" + depends on SOC_INTEL_COMMON_BLOCK_SGX + default n + help + Intel Software Guard Extensions (SGX) is a set of new CPU instructions that can be + used by applications to set aside private regions (so-called Secure Enclaves) of + code and data. + + SGX will only be enabled when supported by the CPU! + +config SOC_INTEL_COMMON_BLOCK_SGX_PRMRR_SIZE + int + default 256 if SOC_INTEL_COMMON_BLOCK_SGX_PRMRR_SIZE_MAX + default 256 if SOC_INTEL_COMMON_BLOCK_SGX_PRMRR_SIZE_256MB + default 128 if SOC_INTEL_COMMON_BLOCK_SGX_PRMRR_SIZE_128MB + default 64 if SOC_INTEL_COMMON_BLOCK_SGX_PRMRR_SIZE_64MB + default 32 if SOC_INTEL_COMMON_BLOCK_SGX_PRMRR_SIZE_32MB + default 1 if SOC_INTEL_COMMON_BLOCK_SGX_PRMRR_SIZE_1MB + +choice + prompt "PRMRR size" + default SOC_INTEL_COMMON_BLOCK_SGX_PRMRR_SIZE_MAX if SOC_INTEL_COMMON_BLOCK_SGX_ENABLE + default SOC_INTEL_COMMON_BLOCK_SGX_PRMRR_DISABLED if !SOC_INTEL_COMMON_BLOCK_SGX_ENABLE + help + PRMRR (Protected Memory Range) is the space in RAM that is used to provide a protected + memory area (e.g. for the Intel SGX Secure Enclaves). The memory region is accessible + only by the processor itself to protect the data from unauthorized access. + + This option selects the maximum size that gets reserved. Depending on the SoC a lower, + compatible value may be chosen at runtime as not all values are supported on all + families. + +config SOC_INTEL_COMMON_BLOCK_SGX_PRMRR_SIZE_MAX + bool "Maximum" + +config SOC_INTEL_COMMON_BLOCK_SGX_PRMRR_SIZE_256MB + bool "256 MiB" + +config SOC_INTEL_COMMON_BLOCK_SGX_PRMRR_SIZE_128MB + bool "128 MiB" + +config SOC_INTEL_COMMON_BLOCK_SGX_PRMRR_SIZE_64MB + bool "64 MiB" + +config SOC_INTEL_COMMON_BLOCK_SGX_PRMRR_SIZE_32MB + bool "32 MiB" + +config SOC_INTEL_COMMON_BLOCK_SGX_PRMRR_SIZE_1MB + depends on !SOC_INTEL_COMMON_BLOCK_SGX_ENABLE # SGX depends on PRMRR >= 32 MiB + bool "1 MiB" + +config SOC_INTEL_COMMON_BLOCK_SGX_PRMRR_DISABLED + depends on !SOC_INTEL_COMMON_BLOCK_SGX_ENABLE # SGX depends on PRMRR >= 32 MiB + bool "Disabled" + +endchoice diff --git a/src/soc/intel/common/block/sgx/sgx.c b/src/soc/intel/common/block/sgx/sgx.c index 842eb43994..6f0cfd8f0e 100644 --- a/src/soc/intel/common/block/sgx/sgx.c +++ b/src/soc/intel/common/block/sgx/sgx.c @@ -206,7 +206,7 @@ void sgx_configure(void *unused) { if (!is_sgx_supported() || !is_prmrr_set()) { - printk(BIOS_ERR, "SGX: pre-conditions not met\n"); + printk(BIOS_ERR, "SGX: not supported or pre-conditions not met\n"); return; } diff --git a/src/soc/intel/icelake/chip.h b/src/soc/intel/icelake/chip.h index fc9341c58b..ec625a0049 100644 --- a/src/soc/intel/icelake/chip.h +++ b/src/soc/intel/icelake/chip.h @@ -206,13 +206,9 @@ struct soc_intel_icelake_config { /* Enable C6 DRAM */ uint8_t enable_c6dram; - /* - * PRMRR size setting with below options - * 0x00100000 - 1MiB - * 0x02000000 - 32MiB and beyond - */ - uint32_t PrmrrSize; + uint8_t PmTimerDisabled; + /* Desired platform debug type. */ enum { DebugConsent_Disabled, diff --git a/src/soc/intel/icelake/romstage/fsp_params.c b/src/soc/intel/icelake/romstage/fsp_params.c index 5bf34213f0..1f9960410e 100644 --- a/src/soc/intel/icelake/romstage/fsp_params.c +++ b/src/soc/intel/icelake/romstage/fsp_params.c @@ -16,6 +16,7 @@ #include #include #include +#include #include #include #include @@ -60,7 +61,7 @@ static void soc_memory_init_params(FSP_M_CONFIG *m_cfg, mask |= (1 << i); } m_cfg->PcieRpEnableMask = mask; - m_cfg->PrmrrSize = config->PrmrrSize; + m_cfg->PrmrrSize = get_prmrr_size(); m_cfg->EnableC6Dram = config->enable_c6dram; /* Disable BIOS Guard */ m_cfg->BiosGuard = 0; diff --git a/src/soc/intel/skylake/acpi.c b/src/soc/intel/skylake/acpi.c index 2af5a53149..332f797dbb 100644 --- a/src/soc/intel/skylake/acpi.c +++ b/src/soc/intel/skylake/acpi.c @@ -205,7 +205,7 @@ static void acpi_create_gnvs(global_nvs_t *gnvs) gnvs->u2we = config->usb2_wake_enable_bitmap; gnvs->u3we = config->usb3_wake_enable_bitmap; - if (config->sgx_enable) + if (CONFIG(SOC_INTEL_COMMON_BLOCK_SGX_ENABLE)) sgx_fill_gnvs(gnvs); } diff --git a/src/soc/intel/skylake/chip.h b/src/soc/intel/skylake/chip.h index 944315b47e..636266632e 100644 --- a/src/soc/intel/skylake/chip.h +++ b/src/soc/intel/skylake/chip.h @@ -510,14 +510,6 @@ struct soc_intel_skylake_config { */ u8 SendVrMbxCmd; - /* - * PRMRR size setting with three options - * 0x02000000 - 32MiB - * 0x04000000 - 64MiB - * 0x08000000 - 128MiB - */ - u32 PrmrrSize; - /* Enable/Disable host reads to PMC XRAM registers */ u8 PchPmPmcReadDisable; @@ -576,9 +568,6 @@ struct soc_intel_skylake_config { u8 SlowSlewRateForGt; u8 SlowSlewRateForSa; - /* Enable SGX feature */ - u8 sgx_enable; - /* Enable/Disable EIST * 1b - Enabled * 0b - Disabled diff --git a/src/soc/intel/skylake/cpu.c b/src/soc/intel/skylake/cpu.c index bfed528a06..080dba0b13 100644 --- a/src/soc/intel/skylake/cpu.c +++ b/src/soc/intel/skylake/cpu.c @@ -442,8 +442,6 @@ static void cpu_lock_aesni(void) /* All CPUs including BSP will run the following function. */ void soc_core_init(struct device *cpu) { - config_t *conf = config_of_soc(); - /* Clear out pending MCEs */ /* TODO(adurbin): This should only be done on a cold boot. Also, some * of these banks are core vs package scope. For now every CPU clears @@ -479,7 +477,7 @@ void soc_core_init(struct device *cpu) enable_turbo(); /* Configure Core PRMRR for SGX. */ - if (conf->sgx_enable) + if (CONFIG(SOC_INTEL_COMMON_BLOCK_SGX_ENABLE)) prmrr_core_configure(); } @@ -502,7 +500,6 @@ static void fc_lock_configure(void *unused) static void post_mp_init(void) { int ret = 0; - config_t *conf = config_of_soc(); /* Set Max Ratio */ cpu_set_max_ratio(); @@ -519,7 +516,7 @@ static void post_mp_init(void) ret |= mp_run_on_all_cpus(vmx_configure, NULL); - if (conf->sgx_enable) + if (CONFIG(SOC_INTEL_COMMON_BLOCK_SGX_ENABLE)) ret |= mp_run_on_all_cpus(sgx_configure, NULL); ret |= mp_run_on_all_cpus(fc_lock_configure, NULL); diff --git a/src/soc/intel/skylake/romstage/romstage.c b/src/soc/intel/skylake/romstage/romstage.c index af89441194..a72b261a56 100644 --- a/src/soc/intel/skylake/romstage/romstage.c +++ b/src/soc/intel/skylake/romstage/romstage.c @@ -22,6 +22,7 @@ #include #include #include +#include #include #include #include @@ -237,7 +238,7 @@ static void soc_memory_init_params(FSP_M_CONFIG *m_cfg, m_cfg->CmdTriStateDis = config->CmdTriStateDis; m_cfg->DdrFreqLimit = config->DdrFreqLimit; m_cfg->VmxEnable = CONFIG(ENABLE_VMX); - m_cfg->PrmrrSize = config->PrmrrSize; + m_cfg->PrmrrSize = get_prmrr_size(); for (i = 0; i < ARRAY_SIZE(config->PcieRpEnable); i++) { if (config->PcieRpEnable[i]) mask |= (1< Date: Tue, 8 Oct 2019 17:23:06 -0500 Subject: [PATCH 0004/1242] google/auron: hook up libgfxinit Internal/external displays functional on all variants other than Samus. Unable to verify external outputs on Samus (USB-C using DP/HDMI adapter). Test: build/boot lulu variant with libgfxinit, verify internal/ external displays functional prior to OS display driver loaded. Both linear framebuffer and scaled VGA text modes functional. Change-Id: I867b2604861ebae02936e7fc0e7230a6adcb2d20 Signed-off-by: Matt DeVillier Reviewed-on: https://review.coreboot.org/c/coreboot/+/36107 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber --- src/mainboard/google/auron/Kconfig | 1 + src/mainboard/google/auron/Makefile.inc | 2 ++ src/mainboard/google/auron/gma-mainboard.ads | 30 ++++++++++++++++++++ 3 files changed, 33 insertions(+) create mode 100644 src/mainboard/google/auron/gma-mainboard.ads diff --git a/src/mainboard/google/auron/Kconfig b/src/mainboard/google/auron/Kconfig index 13348a348f..b4ef3a83ac 100644 --- a/src/mainboard/google/auron/Kconfig +++ b/src/mainboard/google/auron/Kconfig @@ -9,6 +9,7 @@ config BOARD_GOOGLE_BASEBOARD_AURON select HAVE_OPTION_TABLE select HAVE_ACPI_RESUME select MAINBOARD_HAS_CHROMEOS + select MAINBOARD_HAS_LIBGFXINIT select MAINBOARD_HAS_LPC_TPM select MAINBOARD_HAS_TPM1 select INTEL_INT15 diff --git a/src/mainboard/google/auron/Makefile.inc b/src/mainboard/google/auron/Makefile.inc index 6b1de0536c..ca42470796 100644 --- a/src/mainboard/google/auron/Makefile.inc +++ b/src/mainboard/google/auron/Makefile.inc @@ -35,3 +35,5 @@ subdirs-y += variants/$(VARIANT_DIR)/spd CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/variants/$(VARIANT_DIR)/include romstage-y += variants/$(VARIANT_DIR)/gpio.c + +ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads diff --git a/src/mainboard/google/auron/gma-mainboard.ads b/src/mainboard/google/auron/gma-mainboard.ads new file mode 100644 index 0000000000..d110261be2 --- /dev/null +++ b/src/mainboard/google/auron/gma-mainboard.ads @@ -0,0 +1,30 @@ +-- +-- This file is part of the coreboot project. +-- +-- This program is free software; you can redistribute it and/or modify +-- it under the terms of the GNU General Public License as published by +-- the Free Software Foundation; either version 2 of the License, or +-- (at your option) any later version. +-- +-- This program is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more details. +-- + +with HW.GFX.GMA; +with HW.GFX.GMA.Display_Probing; + +use HW.GFX.GMA; +use HW.GFX.GMA.Display_Probing; + +private package GMA.Mainboard is + + ports : constant Port_List := + (Internal, + HDMI1, + DP1, + DP2, + others => Disabled); + +end GMA.Mainboard; From facbf472244876049df61ea0b9577fac9722b08d Mon Sep 17 00:00:00 2001 From: Maxim Polyakov Date: Sun, 27 Oct 2019 15:07:00 +0300 Subject: [PATCH 0005/1242] superio/nuvoton/nct6791d: use SuperIO ACPI generator Adds SuperIO SSDT ACPI generator[1] support. It has been tested on Asrock H110M DVS motherboard [2]. [1] https://review.coreboot.org/c/coreboot/+/33033 [2] https://review.coreboot.org/c/coreboot/+/36381 Change-Id: Idad66546168bbd26f0a4241deb66e5bfd83367af Signed-off-by: Maxim Polyakov Reviewed-on: https://review.coreboot.org/c/coreboot/+/36379 Tested-by: build bot (Jenkins) Reviewed-by: Felix Held --- src/superio/nuvoton/nct6791d/Makefile.inc | 2 ++ src/superio/nuvoton/nct6791d/superio.c | 30 +++++++++++++++++++++-- 2 files changed, 30 insertions(+), 2 deletions(-) diff --git a/src/superio/nuvoton/nct6791d/Makefile.inc b/src/superio/nuvoton/nct6791d/Makefile.inc index db5c620646..a1299a4830 100644 --- a/src/superio/nuvoton/nct6791d/Makefile.inc +++ b/src/superio/nuvoton/nct6791d/Makefile.inc @@ -14,3 +14,5 @@ ## ramstage-$(CONFIG_SUPERIO_NUVOTON_NCT6791D) += superio.c +ramstage-$(CONFIG_SUPERIO_NUVOTON_NCT6791D) += ../../common/ssdt.c +ramstage-$(CONFIG_SUPERIO_NUVOTON_NCT6791D) += ../../common/generic.c diff --git a/src/superio/nuvoton/nct6791d/superio.c b/src/superio/nuvoton/nct6791d/superio.c index 23d5a6f824..08f0bfa3a6 100644 --- a/src/superio/nuvoton/nct6791d/superio.c +++ b/src/superio/nuvoton/nct6791d/superio.c @@ -22,10 +22,10 @@ #include #include #include - +#include +#include #include "nct6791d.h" - static void nct6791d_init(struct device *dev) { if (!dev->enabled) @@ -38,6 +38,27 @@ static void nct6791d_init(struct device *dev) } } +#if CONFIG(HAVE_ACPI_TABLES) +/* Provide ACPI HIDs for generic Super I/O SSDT */ +static const char *nct6791d_acpi_hid(const struct device *dev) +{ + if ((dev->path.type != DEVICE_PATH_PNP) || + (dev->path.pnp.port == 0) || + ((dev->path.pnp.device & 0xff) > NCT6791D_DS)) + return NULL; + + switch (dev->path.pnp.device & 0xff) { + case NCT6791D_SP1: /* falltrough */ + case NCT6791D_SP2: + return ACPI_HID_COM; + case NCT6791D_KBC: + return ACPI_HID_KEYBOARD; + default: + return ACPI_HID_PNP; + } +} +#endif + static struct device_operations ops = { .read_resources = pnp_read_resources, .set_resources = pnp_set_resources, @@ -45,6 +66,11 @@ static struct device_operations ops = { .enable = pnp_alt_enable, .init = nct6791d_init, .ops_pnp_mode = &pnp_conf_mode_8787_aa, +#if CONFIG(HAVE_ACPI_TABLES) + .acpi_fill_ssdt_generator = superio_common_fill_ssdt_generator, + .acpi_name = superio_common_ldn_acpi_name, + .acpi_hid = nct6791d_acpi_hid, +#endif }; static struct pnp_info pnp_dev_info[] = { From c4f77d943adcaeabb391f3f84e45d5fc7cdc12f6 Mon Sep 17 00:00:00 2001 From: Maxim Polyakov Date: Sun, 27 Oct 2019 15:07:00 +0300 Subject: [PATCH 0006/1242] mb/asrock/h110m: use SSDT generator for SuperIO Modifies the device tree to use the ACPI SSDT generator[1] for NCT6791D SuperIO, dropping the need to include code from the superio.asl, which was inherited from another chip (NCT6776) and required fixes. SSDT gen support for Nuvoton NCT6791D chip was added in the previous patch [2]. [1] https://review.coreboot.org/c/coreboot/+/33033 [2] https://review.coreboot.org/c/coreboot/+/36379 Change-Id: I57b67d10968e5e035536bcb0d8329ce09d50194b Signed-off-by: Maxim Polyakov Reviewed-on: https://review.coreboot.org/c/coreboot/+/36381 Tested-by: build bot (Jenkins) Reviewed-by: Felix Held --- src/mainboard/asrock/h110m/acpi/superio.asl | 25 --- src/mainboard/asrock/h110m/devicetree.cb | 195 ++++++++++---------- 2 files changed, 101 insertions(+), 119 deletions(-) diff --git a/src/mainboard/asrock/h110m/acpi/superio.asl b/src/mainboard/asrock/h110m/acpi/superio.asl index b671e3cb37..8b13789179 100644 --- a/src/mainboard/asrock/h110m/acpi/superio.asl +++ b/src/mainboard/asrock/h110m/acpi/superio.asl @@ -1,26 +1 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2018 Tristan Corrick - * - * This program is free software: you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ -#define SUPERIO_DEV SIO0 -#define SUPERIO_PNP_BASE 0x2e -#define NCT6776_SHOW_PP -#define NCT6776_SHOW_SP1 -#define NCT6776_SHOW_KBC -#define NCT6776_SHOW_HWM - -#undef NCT6776_SHOW_GPIO - -#include diff --git a/src/mainboard/asrock/h110m/devicetree.cb b/src/mainboard/asrock/h110m/devicetree.cb index b2a2d72df2..2d6b951de4 100644 --- a/src/mainboard/asrock/h110m/devicetree.cb +++ b/src/mainboard/asrock/h110m/devicetree.cb @@ -326,101 +326,108 @@ chip soc/intel/skylake device pci 1e.6 off end # SDCard device pci 1f.0 on # LPC bridge subsystemid 0x1849 0x1a43 - chip superio/nuvoton/nct6791d - device pnp 2e.0 off end # Floppy - device pnp 2e.1 on - # Global Control Registers - # Device IRQ Polarity - irq 0x13 = 0x00 - irq 0x14 = 0x00 - # Global Option - irq 0x24 = 0xfb - irq 0x27 = 0x10 - # Multi Function - irq 0x1a = 0xb0 - irq 0x1b = 0xe6 - irq 0x2a = 0x04 - irq 0x2c = 0x40 - irq 0x2d = 0x03 - # Parallel Port - io 0x60 = 0x0378 - irq 0x70 = 7 - drq 0x74 = 4 # No DMA - irq 0xf0 = 0x3c # Printer mode - end - device pnp 2e.2 on # UART A - io 0x60 = 0x03f8 - irq 0x70 = 4 - end - device pnp 2e.3 on # IR - io 0x60 = 0x02f8 - irq 0x70 = 3 - end - device pnp 2e.5 on # PS/2 KBC - io 0x60 = 0x0060 - io 0x62 = 0x0064 - irq 0x70 = 1 # Keyboard - irq 0x72 = 12 # Mouse - end - device pnp 2e.6 off end # CIR - device pnp 2e.7 on # GPIO6 - irq 0xf6 = 0xff - irq 0xf7 = 0xff - irq 0xf8 = 0xff - end - device pnp 2e.107 on # GPIO7 - irq 0xe0 = 0x7f - irq 0xe1 = 0x0d - end - device pnp 2e.207 on # GPIO8 - irq 0xe6 = 0xff - irq 0xe7 = 0xff - irq 0xed = 0xff - end - device pnp 2e.8 off end # WDT - device pnp 2e.108 on end # GPIO0 - device pnp 2e.308 off end # GPIO base - device pnp 2e.408 off end # WDTMEM - device pnp 2e.708 on end # GPIO1 - device pnp 2e.9 on end # GPIO2 - device pnp 2e.109 on # GPIO3 - irq 0xe4 = 0x7b - irq 0xe5 = 0x02 - irq 0xea = 0x04 - end - device pnp 2e.209 on # GPIO4 - irq 0xf0 = 0x7f - irq 0xf1 = 0x80 - end - device pnp 2e.309 on # GPIO5 - irq 0xf4 = 0xdf - irq 0xf5 = 0xd5 - end - device pnp 2e.a on - # Power RAM in S3 and let the PCH - # handle power failure actions - irq 0xe4 = 0x70 - # Set HWM reset source to LRESET# - irq 0xe7 = 0x01 - end # ACPI - device pnp 2e.b on # HWM, LED - io 0x60 = 0x0290 - io 0x62 = 0 - irq 0x70 = 0 - end - device pnp 2e.d off end # BCLK, WDT2, WDT_MEM - device pnp 2e.e off end # CIR wake-up - device pnp 2e.f off end # GPIO PP/OD - device pnp 2e.14 off end # SVID, Port 80 UART - device pnp 2e.16 off end # DS5 - device pnp 2e.116 off end # DS3 - device pnp 2e.316 on end # PCHDSW - device pnp 2e.416 off end # DSWWOPT - device pnp 2e.516 on end # DS3OPT - device pnp 2e.616 on end # DSDSS - device pnp 2e.716 off end # DSPU - end # superio/nuvoton/nct6791d + chip superio/common + device pnp 2e.0 on # passes SIO base addr to SSDT gen + + chip superio/nuvoton/nct6791d + device pnp 2e.1 on + # Global Control Registers + # Device IRQ Polarity + irq 0x13 = 0x00 + irq 0x14 = 0x00 + # Global Option + irq 0x24 = 0xfb + irq 0x27 = 0x10 + # Multi Function + irq 0x1a = 0xb0 + irq 0x1b = 0xe6 + irq 0x2a = 0x04 + irq 0x2c = 0x40 + irq 0x2d = 0x03 + + # Parallel Port + io 0x60 = 0x0378 + irq 0x70 = 7 + drq 0x74 = 4 # No DMA + irq 0xf0 = 0x3c # Printer mode + end + device pnp 2e.2 on # UART A + io 0x60 = 0x03f8 + irq 0x70 = 4 + end + device pnp 2e.3 on # IR + io 0x60 = 0x02f8 + irq 0x70 = 3 + end + device pnp 2e.5 on # PS/2 KBC + io 0x60 = 0x0060 + io 0x62 = 0x0064 + irq 0x70 = 1 # Keyboard + irq 0x72 = 12 # Mouse + end + device pnp 2e.6 off end # CIR + device pnp 2e.7 on # GPIO6 + irq 0xf6 = 0xff + irq 0xf7 = 0xff + irq 0xf8 = 0xff + end + device pnp 2e.107 on # GPIO7 + irq 0xe0 = 0x7f + irq 0xe1 = 0x0d + end + device pnp 2e.207 on # GPIO8 + irq 0xe6 = 0xff + irq 0xe7 = 0xff + irq 0xed = 0xff + end + device pnp 2e.8 off end # WDT + device pnp 2e.108 on end # GPIO0 + device pnp 2e.308 off end # GPIO base + device pnp 2e.408 off end # WDTMEM + device pnp 2e.708 on end # GPIO1 + device pnp 2e.9 on end # GPIO2 + device pnp 2e.109 on # GPIO3 + irq 0xe4 = 0x7b + irq 0xe5 = 0x02 + irq 0xea = 0x04 + end + device pnp 2e.209 on # GPIO4 + irq 0xf0 = 0x7f + irq 0xf1 = 0x80 + end + device pnp 2e.309 on # GPIO5 + irq 0xf4 = 0xdf + irq 0xf5 = 0xd5 + end + device pnp 2e.a on + # Power RAM in S3 and let the PCH + # handle power failure actions + irq 0xe4 = 0x70 + # Set HWM reset source to LRESET# + irq 0xe7 = 0x01 + end # ACPI + device pnp 2e.b on # HWM, LED + io 0x60 = 0x0290 + io 0x62 = 0 + irq 0x70 = 0 + end + device pnp 2e.d off end # BCLK, WDT2, WDT_MEM + device pnp 2e.e off end # CIR wake-up + device pnp 2e.f off end # GPIO PP/OD + device pnp 2e.14 off end # SVID, Port 80 UART + device pnp 2e.16 off end # DS5 + device pnp 2e.116 off end # DS3 + device pnp 2e.316 on end # PCHDSW + device pnp 2e.416 off end # DSWWOPT + device pnp 2e.516 on end # DS3OPT + device pnp 2e.616 on end # DSDSS + device pnp 2e.716 off end # DSPU + end # chip superio/nuvoton/nct6791d + + end # device pnp 2e.0 + end # chip superio/common + chip drivers/pc80/tpm device pnp 4e.0 on end # TPM module end From 0dd8fe7ec3c1b767ef228815a24cbb265802b9f4 Mon Sep 17 00:00:00 2001 From: Maxim Polyakov Date: Sun, 27 Oct 2019 15:07:00 +0300 Subject: [PATCH 0007/1242] superio/nuvoton/nct5539d: use SuperIO ACPI generator Adds SuperIO SSDT ACPI generator[1] support. Not tested on real hardware. [1] https://review.coreboot.org/c/coreboot/+/33033 Change-Id: If9fd56efd40ee0f860e206882418c8bdc7c16802 Signed-off-by: Maxim Polyakov Reviewed-on: https://review.coreboot.org/c/coreboot/+/36380 Tested-by: build bot (Jenkins) Reviewed-by: Felix Held --- src/superio/nuvoton/nct5539d/Makefile.inc | 2 ++ src/superio/nuvoton/nct5539d/superio.c | 25 +++++++++++++++++++++++ 2 files changed, 27 insertions(+) diff --git a/src/superio/nuvoton/nct5539d/Makefile.inc b/src/superio/nuvoton/nct5539d/Makefile.inc index 6e3fdf25a2..a6f3a022fe 100644 --- a/src/superio/nuvoton/nct5539d/Makefile.inc +++ b/src/superio/nuvoton/nct5539d/Makefile.inc @@ -14,3 +14,5 @@ ## ramstage-$(CONFIG_SUPERIO_NUVOTON_NCT5539D) += superio.c +ramstage-$(CONFIG_SUPERIO_NUVOTON_NCT5539D) += ../../common/ssdt.c +ramstage-$(CONFIG_SUPERIO_NUVOTON_NCT5539D) += ../../common/generic.c diff --git a/src/superio/nuvoton/nct5539d/superio.c b/src/superio/nuvoton/nct5539d/superio.c index e38f845042..4f2a4a5c16 100644 --- a/src/superio/nuvoton/nct5539d/superio.c +++ b/src/superio/nuvoton/nct5539d/superio.c @@ -40,6 +40,26 @@ static void nct5539d_init(struct device *dev) } } +#if CONFIG(HAVE_ACPI_TABLES) +/* Provide ACPI HIDs for generic Super I/O SSDT */ +static const char *nct5539d_acpi_hid(const struct device *dev) +{ + if ((dev->path.type != DEVICE_PATH_PNP) || + (dev->path.pnp.port == 0) || + ((dev->path.pnp.device & 0xff) > NCT5539D_DS)) + return NULL; + + switch (dev->path.pnp.device & 0xff) { + case NCT5539D_SP1: + return ACPI_HID_COM; + case NCT5539D_KBC: + return ACPI_HID_KEYBOARD; + default: + return ACPI_HID_PNP; + } +} +#endif + static struct device_operations ops = { .read_resources = pnp_read_resources, .set_resources = pnp_set_resources, @@ -47,6 +67,11 @@ static struct device_operations ops = { .enable = pnp_alt_enable, .init = nct5539d_init, .ops_pnp_mode = &pnp_conf_mode_8787_aa, +#if CONFIG(HAVE_ACPI_TABLES) + .acpi_fill_ssdt_generator = superio_common_fill_ssdt_generator, + .acpi_name = superio_common_ldn_acpi_name, + .acpi_hid = nct5539d_acpi_hid, +#endif }; static struct pnp_info pnp_dev_info[] = { From 3a2867329392a5f332cf1d144f093d5f965ac530 Mon Sep 17 00:00:00 2001 From: Maxim Polyakov Date: Sun, 27 Oct 2019 15:07:00 +0300 Subject: [PATCH 0008/1242] mb/asrock/h110m/devicetree: fix VR config info Removes unnecessary information about the Ring Sliced VR configuration from another board with FSP1.1 (which is no longer supported). Change-Id: Ia2b90d9ede782852c2127da972333bada378b217 Signed-off-by: Maxim Polyakov Reviewed-on: https://review.coreboot.org/c/coreboot/+/36378 Tested-by: build bot (Jenkins) Reviewed-by: Felix Held --- src/mainboard/asrock/h110m/devicetree.cb | 30 ++++++++++++------------ 1 file changed, 15 insertions(+), 15 deletions(-) diff --git a/src/mainboard/asrock/h110m/devicetree.cb b/src/mainboard/asrock/h110m/devicetree.cb index 2d6b951de4..bd51e40bf3 100644 --- a/src/mainboard/asrock/h110m/devicetree.cb +++ b/src/mainboard/asrock/h110m/devicetree.cb @@ -82,21 +82,21 @@ chip soc/intel/skylake # SLP_A Minimum Assertion Width. Values 0: 0ms, 1: 4s, 2: 98ms, 3: 2s register "PmConfigSlpAMinAssert" = "0x03" - # VR Settings Configuration for 5 Domains - #+----------------+-------+-------+-------------+-------------+-------+ - #| Domain/Setting | SA | IA | Ring Sliced | GT Unsliced | GT | - #+----------------+-------+-------+-------------+-------------+-------+ - #| Psi1Threshold | 20A | 20A | 20A | 20A | 20A | - #| Psi2Threshold | 4A | 5A | 5A | 5A | 5A | - #| Psi3Threshold | 1A | 1A | 1A | 1A | 1A | - #| Psi3Enable | 1 | 1 | 1 | 1 | 1 | - #| Psi4Enable | 1 | 1 | 1 | 1 | 1 | - #| ImonSlope | 0 | 0 | 0 | 0 | 0 | - #| ImonOffset | 0 | 0 | 0 | 0 | 0 | - #| IccMax* | 0 | 0 | 0 | 0 | 0 | - #| VrVoltageLimit | 1.52V | 1.52V | 1.52V | 1.52V | 1.52V | - #+----------------+-------+-------+-------------+-------------+-------+ - # * - is set automatically for the KBL-S/KBL-DT CPUs in the vr_config.c + # VR Settings Configuration + #+----------------+-------+-------+-------------+-------+ + #| Domain/Setting | SA | IA | GT Unsliced | GT | + #+----------------+-------+-------+-------------+-------+ + #| Psi1Threshold | 20A | 20A | 20A | 20A | + #| Psi2Threshold | 4A | 5A | 5A | 5A | + #| Psi3Threshold | 1A | 1A | 1A | 1A | + #| Psi3Enable | 1 | 1 | 1 | 1 | + #| Psi4Enable | 1 | 1 | 1 | 1 | + #| ImonSlope | 0 | 0 | 0 | 0 | + #| ImonOffset | 0 | 0 | 0 | 0 | + #| IccMax* | 0 | 0 | 0 | 0 | + #| VrVoltageLimit | 1.52V | 1.52V | 1.52V | 1.52V | + #+----------------+-------+-------+-------------+-------+ + # * - is set automatically in the vr_config.c register "domain_vr_config[VR_SYSTEM_AGENT]" = "{ .vr_config_enable = 1, \ .psi1threshold = VR_CFG_AMP(20), \ From 1e07d40027b65e7c5aa0926146f826e7038f7e4e Mon Sep 17 00:00:00 2001 From: Peichao Wang Date: Fri, 23 Aug 2019 15:55:24 +0800 Subject: [PATCH 0009/1242] mb/google/kahlee/treeya: Update STAPM parameters for Treeya Tune stapm percentage from 80 to 68 and time from 250 second to 90 second make them meet Lenovo temperature spec. BUG=b:143859022 TEST=build firmware and install it to DUT and run fishbowl 1000, check temperature whether meets spec. Signed-off-by: Peichao Wang Change-Id: I254140c9d242ed918b3b689d4fb4a1d0e871cd55 Reviewed-on: https://review.coreboot.org/c/coreboot/+/35042 Tested-by: build bot (Jenkins) Reviewed-by: Marshall Dawson Reviewed-by: Martin Roth --- src/mainboard/google/kahlee/variants/treeya/devicetree.cb | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/mainboard/google/kahlee/variants/treeya/devicetree.cb b/src/mainboard/google/kahlee/variants/treeya/devicetree.cb index 2e25340b6e..e8477eeb6a 100644 --- a/src/mainboard/google/kahlee/variants/treeya/devicetree.cb +++ b/src/mainboard/google/kahlee/variants/treeya/devicetree.cb @@ -20,8 +20,8 @@ chip soc/amd/stoneyridge register "dram_clear_on_reset" = "DRAM_CONTENTS_KEEP" register "uma_mode" = "UMAMODE_SPECIFIED_SIZE" register "uma_size" = "16 * MiB" - register "stapm_percent" = "80" - register "stapm_time_ms" = "2500000" + register "stapm_percent" = "68" + register "stapm_time_ms" = "900000" register "stapm_power_mw" = "7800" # Enable I2C0 for audio, USB3 hub at 400kHz From 127b820d243523fceefb4c5470a5050aa3666dfd Mon Sep 17 00:00:00 2001 From: Arthur Heymans Date: Sun, 20 Oct 2019 14:24:57 +0200 Subject: [PATCH 0010/1242] soc/intel/common: Don't link CAR teardown in romstage This is done in postcar stage. This also assumes CAR tear down will always be done in postcar stage. Change-Id: I0ff1624c20b9649ca0a8fa31c342bf99530076d7 Signed-off-by: Arthur Heymans Reviewed-on: https://review.coreboot.org/c/coreboot/+/36166 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin --- src/soc/intel/common/block/cpu/Makefile.inc | 1 - 1 file changed, 1 deletion(-) diff --git a/src/soc/intel/common/block/cpu/Makefile.inc b/src/soc/intel/common/block/cpu/Makefile.inc index f263053430..323d15739c 100644 --- a/src/soc/intel/common/block/cpu/Makefile.inc +++ b/src/soc/intel/common/block/cpu/Makefile.inc @@ -3,7 +3,6 @@ bootblock-$(CONFIG_SOC_INTEL_COMMON_BLOCK_CAR) += ../../../../../cpu/x86/early_r bootblock-$(CONFIG_FSP_CAR)+= car/cache_as_ram_fsp.S bootblock-$(CONFIG_SOC_INTEL_COMMON_BLOCK_CPU) += cpulib.c -romstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_CAR) += car/exit_car.S romstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_CPU) += cpulib.c postcar-$(CONFIG_SOC_INTEL_COMMON_BLOCK_CAR) += car/exit_car.S From acc88f8e66c4bee9397347f57a5553bbacbc2377 Mon Sep 17 00:00:00 2001 From: Arthur Heymans Date: Sun, 20 Oct 2019 14:29:59 +0200 Subject: [PATCH 0011/1242] drivers/intel/fsp2_0: Hide CONFIG_FSP_CAR CONFIG_FSP_CAR should not be a user visible option, but depends on the choice presented in the soc Kconfig. This also removes the dependencies on ADD_FSP_BINARIES. You need to included those for other stages too so there is no need to make this requirement explicit for FSP-T. Change-Id: Ida32e9c4f5839aef4d4deb7a1c7fabe6335a5d2a Signed-off-by: Arthur Heymans Reviewed-on: https://review.coreboot.org/c/coreboot/+/36169 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber --- src/drivers/intel/fsp2_0/Kconfig | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/src/drivers/intel/fsp2_0/Kconfig b/src/drivers/intel/fsp2_0/Kconfig index 765d6435f7..b434a514a4 100644 --- a/src/drivers/intel/fsp2_0/Kconfig +++ b/src/drivers/intel/fsp2_0/Kconfig @@ -123,8 +123,7 @@ config FSP_S_FILE The path and filename of the Intel FSP-S binary for this platform. config FSP_CAR - bool "Use FSP TempRamInit & TempRamExit APIs" - depends on ADD_FSP_BINARIES + bool default n help Use FSP APIs to initialize & Tear Down the Cache-As-Ram From cc5193604f1b2fcd6659888df22a1a6e06635482 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ky=C3=B6sti=20M=C3=A4lkki?= Date: Sun, 3 Nov 2019 08:24:48 +0200 Subject: [PATCH 0012/1242] cpu/ti/am335x: Extend monotonic timer to early stages MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit It is actually all completely broken, dmtimer.c is not really implemented. Change-Id: Ifb3f624930c9ef663fae30cd5ddcb1d3d46f06b1 Signed-off-by: Kyösti Mälkki Reviewed-on: https://review.coreboot.org/c/coreboot/+/36593 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin --- src/cpu/ti/am335x/Makefile.inc | 3 +++ 1 file changed, 3 insertions(+) diff --git a/src/cpu/ti/am335x/Makefile.inc b/src/cpu/ti/am335x/Makefile.inc index d3ef9701e8..e1a3b9c7b9 100644 --- a/src/cpu/ti/am335x/Makefile.inc +++ b/src/cpu/ti/am335x/Makefile.inc @@ -3,9 +3,12 @@ bootblock-y += bootblock_media.c bootblock-y += dmtimer.c bootblock-y += gpio.c bootblock-y += pinmux.c +bootblock-y += monotonic_timer.c romstage-y += nand.c romstage-y += cbmem.c +romstage-y += dmtimer.c +romstage-y += monotonic_timer.c ramstage-y += dmtimer.c ramstage-y += monotonic_timer.c From fe3250dbe6b27df7aa0cf0fa432a0b6a1ca5ebb8 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ky=C3=B6sti=20M=C3=A4lkki?= Date: Sun, 3 Nov 2019 08:18:15 +0200 Subject: [PATCH 0013/1242] bootblock: Add TS_START_BOOTBLOCK and TS_END_BOOTBLOCK MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Change-Id: I5617e5d9b7238ad7a894934910a3eae742d2d22d Signed-off-by: Kyösti Mälkki Reviewed-on: https://review.coreboot.org/c/coreboot/+/36594 Reviewed-by: Paul Menzel Reviewed-by: Arthur Heymans Tested-by: build bot (Jenkins) --- src/lib/bootblock.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/src/lib/bootblock.c b/src/lib/bootblock.c index 19841c6931..5fb606731a 100644 --- a/src/lib/bootblock.c +++ b/src/lib/bootblock.c @@ -51,6 +51,8 @@ static void bootblock_main_with_timestamp(uint64_t base_timestamp, timestamps[i].entry_stamp); } + timestamp_add_now(TS_START_BOOTBLOCK); + bootblock_soc_early_init(); bootblock_mainboard_early_init(); @@ -65,6 +67,8 @@ static void bootblock_main_with_timestamp(uint64_t base_timestamp, bootblock_soc_init(); bootblock_mainboard_init(); + timestamp_add_now(TS_END_BOOTBLOCK); + run_romstage(); } From 092fe558ee20950faf29d8e7d581a2631e6e1bb4 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ky=C3=B6sti=20M=C3=A4lkki?= Date: Fri, 1 Nov 2019 07:13:09 +0200 Subject: [PATCH 0014/1242] intel/i440bx: Switch to UDELAY_TSC and TSC_MONOTONIC_TIMER MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Note that due to UNKNOWN_TSC_RATE, each stage will have a slow run of calibrate_tsc_with_pit(). This is easy enough to fix with followup implementation of tsc_freq_mhz() for the cpu. Change-Id: I0f5e16993e19342dfc4801663e0025bb4cee022a Signed-off-by: Kyösti Mälkki Reviewed-on: https://review.coreboot.org/c/coreboot/+/36525 Reviewed-by: Arthur Heymans Tested-by: build bot (Jenkins) --- src/cpu/intel/slot_1/Kconfig | 3 ++- src/northbridge/intel/i440bx/Kconfig | 1 - 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/src/cpu/intel/slot_1/Kconfig b/src/cpu/intel/slot_1/Kconfig index 3d0522a09d..10001bdc5f 100644 --- a/src/cpu/intel/slot_1/Kconfig +++ b/src/cpu/intel/slot_1/Kconfig @@ -24,7 +24,8 @@ config SLOT_SPECIFIC_OPTIONS # dummy select CPU_INTEL_MODEL_6BX select CPU_INTEL_MODEL_6XX select NO_SMM - select NO_MONOTONIC_TIMER + select UDELAY_TSC + select TSC_MONOTONIC_TIMER select UNKNOWN_TSC_RATE config DCACHE_RAM_BASE diff --git a/src/northbridge/intel/i440bx/Kconfig b/src/northbridge/intel/i440bx/Kconfig index 45cdd9c7f1..df1e3650a4 100644 --- a/src/northbridge/intel/i440bx/Kconfig +++ b/src/northbridge/intel/i440bx/Kconfig @@ -17,7 +17,6 @@ config NORTHBRIDGE_INTEL_I440BX bool select NO_MMCONF_SUPPORT select HAVE_DEBUG_RAM_SETUP - select UDELAY_IO config SDRAMPWR_4DIMM bool From 385ea8219d2f09d3f9d2d194392cf696d4e2aed7 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ky=C3=B6sti=20M=C3=A4lkki?= Date: Fri, 1 Nov 2019 10:44:33 +0200 Subject: [PATCH 0015/1242] drivers/pc80: Remove UDELAY_IO MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Change-Id: I3ab62d9b1caa23305ad3b859e3c1949784ae0464 Signed-off-by: Kyösti Mälkki Reviewed-on: https://review.coreboot.org/c/coreboot/+/36533 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Rudolph --- src/drivers/pc80/pc/Kconfig | 4 ---- src/drivers/pc80/pc/Makefile.inc | 2 -- src/drivers/pc80/pc/udelay_io.c | 27 --------------------------- 3 files changed, 33 deletions(-) delete mode 100644 src/drivers/pc80/pc/udelay_io.c diff --git a/src/drivers/pc80/pc/Kconfig b/src/drivers/pc80/pc/Kconfig index bba45f6a64..06e6568f71 100644 --- a/src/drivers/pc80/pc/Kconfig +++ b/src/drivers/pc80/pc/Kconfig @@ -18,10 +18,6 @@ config DRIVERS_PS2_KEYBOARD this option, then you can say N here to speed up boot time. Otherwise say Y. -config UDELAY_IO - bool - default n - # This option is used in code but never selected. config UDELAY_TIMER2 bool diff --git a/src/drivers/pc80/pc/Makefile.inc b/src/drivers/pc80/pc/Makefile.inc index bd56cd43a1..67c40a1c19 100644 --- a/src/drivers/pc80/pc/Makefile.inc +++ b/src/drivers/pc80/pc/Makefile.inc @@ -2,8 +2,6 @@ ifeq ($(CONFIG_ARCH_X86),y) ramstage-y += isa-dma.c ramstage-y += i8259.c -ramstage-$(CONFIG_UDELAY_IO) += udelay_io.c -romstage-$(CONFIG_UDELAY_IO) += udelay_io.c ramstage-y += keyboard.c ramstage-$(CONFIG_SPKMODEM) += spkmodem.c romstage-$(CONFIG_SPKMODEM) += spkmodem.c diff --git a/src/drivers/pc80/pc/udelay_io.c b/src/drivers/pc80/pc/udelay_io.c deleted file mode 100644 index 4fe1caeed9..0000000000 --- a/src/drivers/pc80/pc/udelay_io.c +++ /dev/null @@ -1,27 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include - -void init_timer(void) -{ -} - -void udelay(unsigned int usecs) -{ - int i; - - for (i = 0; i < usecs; i++) - inb(0x80); -} From 00f0de3e145c34f524ab5ae403b65bfcc9493c30 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ky=C3=B6sti=20M=C3=A4lkki?= Date: Fri, 1 Nov 2019 10:45:51 +0200 Subject: [PATCH 0016/1242] drivers/pc80: Remove UDELAY_TIMER2 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Change-Id: Ibc0a5f6e7be78be15f56b252be45a288b925183a Signed-off-by: Kyösti Mälkki Reviewed-on: https://review.coreboot.org/c/coreboot/+/36534 Reviewed-by: Arthur Heymans Tested-by: build bot (Jenkins) --- src/drivers/pc80/pc/Kconfig | 5 ----- src/drivers/pc80/pc/i8254.c | 18 ------------------ 2 files changed, 23 deletions(-) diff --git a/src/drivers/pc80/pc/Kconfig b/src/drivers/pc80/pc/Kconfig index 06e6568f71..68138575ba 100644 --- a/src/drivers/pc80/pc/Kconfig +++ b/src/drivers/pc80/pc/Kconfig @@ -18,9 +18,4 @@ config DRIVERS_PS2_KEYBOARD this option, then you can say N here to speed up boot time. Otherwise say Y. -# This option is used in code but never selected. -config UDELAY_TIMER2 - bool - default n - endif diff --git a/src/drivers/pc80/pc/i8254.c b/src/drivers/pc80/pc/i8254.c index 654f84a6d7..5090f0c85b 100644 --- a/src/drivers/pc80/pc/i8254.c +++ b/src/drivers/pc80/pc/i8254.c @@ -32,24 +32,6 @@ void setup_i8254(void) outb(0x12, TIMER1_PORT); } -#if CONFIG(UDELAY_TIMER2) -static void load_timer2(unsigned int ticks) -{ - /* Set up the timer gate, turn off the speaker */ - outb((inb(PPC_PORTB) & ~PPCB_SPKR) | PPCB_T2GATE, PPC_PORTB); - outb(TIMER2_SEL | WORD_ACCESS | MODE0 | BINARY_COUNT, TIMER_MODE_PORT); - outb(ticks & 0xFF, TIMER2_PORT); - outb(ticks >> 8, TIMER2_PORT); -} - -void udelay(int usecs) -{ - load_timer2((usecs * TICKS_PER_MS) / 1000); - while ((inb(PPC_PORTB) & PPCB_T2OUT) == 0) - ; -} -#endif - #define CLOCK_TICK_RATE 1193180U /* Underlying HZ */ /* ------ Calibrate the TSC ------- From baa8c7819cdaa21feb04f3144e3914bcaa99bf9b Mon Sep 17 00:00:00 2001 From: Patrick Rudolph Date: Tue, 15 Oct 2019 14:52:29 +0200 Subject: [PATCH 0017/1242] mb/supermicro/x11ssh-tf: Disable i8042 support Even though the vendor firmware enables the i8042 I/O port, it doesn't feed valid data to those, but instead uses USB HID devices. Disable the KBC port in SuperI/O and report no KCS port using FADT. Fixes: * Fixes error message in Linux that i8042 keyboard couldn't be enabled. Tested on Supermicro X11SSH-TF: The virtual remote managment console still works. Change-Id: I1cdf648aa5bf1d0ec48520fa1e45bdaf043cb45d Signed-off-by: Patrick Rudolph Reviewed-on: https://review.coreboot.org/c/coreboot/+/36078 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel Reviewed-by: Nico Huber --- src/mainboard/supermicro/x11-lga1151-series/Kconfig | 1 + .../x11-lga1151-series/variants/x11ssh-tf/overridetree.cb | 7 +------ 2 files changed, 2 insertions(+), 6 deletions(-) diff --git a/src/mainboard/supermicro/x11-lga1151-series/Kconfig b/src/mainboard/supermicro/x11-lga1151-series/Kconfig index a3ed8af972..ea0214ad01 100644 --- a/src/mainboard/supermicro/x11-lga1151-series/Kconfig +++ b/src/mainboard/supermicro/x11-lga1151-series/Kconfig @@ -14,6 +14,7 @@ config BOARD_SUPERMICRO_BASEBOARD_X11_LGA1151_SERIES select IPMI_KCS select MAINBOARD_NO_FSP_GOP select SUPERIO_ASPEED_HAS_UART_DELAY_WORKAROUND + select NO_FADT_8042 if BOARD_SUPERMICRO_BASEBOARD_X11_LGA1151_SERIES diff --git a/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssh-tf/overridetree.cb b/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssh-tf/overridetree.cb index 3e587dc817..aace4f7487 100644 --- a/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssh-tf/overridetree.cb +++ b/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssh-tf/overridetree.cb @@ -114,12 +114,7 @@ chip soc/intel/skylake io 0x66 = 0xa30 irq 0x70 = 0xb end - device pnp 2e.5 on # Keyboard - io 0x60 = 0x60 - io 0x62 = 0x64 - irq 0x70 = 1 - irq 0x72 = 0xc - end + device pnp 2e.5 off end # KBC device pnp 2e.7 on end # GPIO device pnp 2e.b on # SUART3 io 0x60 = 0x3e8 From 92a75996160e2da57253b693b4e5c3284f437228 Mon Sep 17 00:00:00 2001 From: Elyes HAOUAS Date: Mon, 4 Nov 2019 15:03:31 +0100 Subject: [PATCH 0018/1242] src/Kconfig: Drop unused DEBUG_ACPI Change-Id: I135f3e6ec5e75df03331c0c46edb0be243af2adb Signed-off-by: Elyes HAOUAS Reviewed-on: https://review.coreboot.org/c/coreboot/+/36498 Reviewed-by: Nico Huber Tested-by: build bot (Jenkins) --- configs/config.emulation_qemu_x86_i440fx_debug | 1 - configs/config.lenovo_t400_vboot_and_debug | 1 - ...ig.lenovo_x201_all_debug_option_table_bt_on_wifi | 1 - src/Kconfig | 13 ------------- 4 files changed, 16 deletions(-) diff --git a/configs/config.emulation_qemu_x86_i440fx_debug b/configs/config.emulation_qemu_x86_i440fx_debug index ffca28bfb5..011f16356c 100644 --- a/configs/config.emulation_qemu_x86_i440fx_debug +++ b/configs/config.emulation_qemu_x86_i440fx_debug @@ -4,7 +4,6 @@ CONFIG_FATAL_ASSERTS=y CONFIG_DEBUG_CBFS=y CONFIG_DEBUG_PIRQ=y CONFIG_DEBUG_MALLOC=y -CONFIG_DEBUG_ACPI=y CONFIG_TRACE=y CONFIG_DEBUG_BOOT_STATE=y CONFIG_DEBUG_ADA_CODE=y diff --git a/configs/config.lenovo_t400_vboot_and_debug b/configs/config.lenovo_t400_vboot_and_debug index 5a1add6788..2923f94758 100644 --- a/configs/config.lenovo_t400_vboot_and_debug +++ b/configs/config.lenovo_t400_vboot_and_debug @@ -8,7 +8,6 @@ CONFIG_DEBUG_RAM_SETUP=y CONFIG_DEBUG_SMBUS=y CONFIG_DEBUG_SMI=y CONFIG_DEBUG_MALLOC=y -CONFIG_DEBUG_ACPI=y CONFIG_DEBUG_BOOT_STATE=y CONFIG_DEBUG_ADA_CODE=y CONFIG_H8_FN_KEY_AS_VBOOT_RECOVERY_SW=y diff --git a/configs/config.lenovo_x201_all_debug_option_table_bt_on_wifi b/configs/config.lenovo_x201_all_debug_option_table_bt_on_wifi index 1579aa3e1f..a75d91a32d 100644 --- a/configs/config.lenovo_x201_all_debug_option_table_bt_on_wifi +++ b/configs/config.lenovo_x201_all_debug_option_table_bt_on_wifi @@ -7,7 +7,6 @@ CONFIG_DEBUG_CBFS=y CONFIG_DEBUG_SMBUS=y CONFIG_DEBUG_SMI=y CONFIG_DEBUG_MALLOC=y -CONFIG_DEBUG_ACPI=y CONFIG_DEBUG_SPI_FLASH=y CONFIG_DEBUG_BOOT_STATE=y CONFIG_DEBUG_ADA_CODE=y diff --git a/src/Kconfig b/src/Kconfig index 793927a484..0d56291de4 100644 --- a/src/Kconfig +++ b/src/Kconfig @@ -840,19 +840,6 @@ config DEBUG_MALLOC If unsure, say N. -# Only visible if debug level is DEBUG (7) or SPEW (8) as it does additional -# printk(BIOS_DEBUG, ...) calls. -config DEBUG_ACPI - prompt "Output verbose ACPI debug messages" if DEFAULT_CONSOLE_LOGLEVEL_7 || DEFAULT_CONSOLE_LOGLEVEL_8 - bool - default n - help - This option enables additional ACPI related debug messages. - - Note: This option will slightly increase the size of the coreboot image. - - If unsure, say N. - config DEBUG_CONSOLE_INIT bool "Debug console initialisation code" default n From 15fcc86907dc6f8f782cfdc98808f508aa66082c Mon Sep 17 00:00:00 2001 From: Arthur Heymans Date: Tue, 8 Oct 2019 11:29:12 +0200 Subject: [PATCH 0019/1242] pci_mmio_cfg.h: Add a compile time error if MMCONF_BASE_ADDRESS is undefined if CONFIG_MMCONF_SUPPORT is set, add a compiletime error if CONFIG_MMCONF_BASE_ADDRESS is not defined. Change-Id: I0439e994d170e8ec564ce188e82a850e2a286a66 Signed-off-by: Arthur Heymans Reviewed-on: https://review.coreboot.org/c/coreboot/+/35883 Reviewed-by: Nico Huber Tested-by: build bot (Jenkins) --- src/include/device/pci_mmio_cfg.h | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/src/include/device/pci_mmio_cfg.h b/src/include/device/pci_mmio_cfg.h index 5567ed86ae..e3c5fe4873 100644 --- a/src/include/device/pci_mmio_cfg.h +++ b/src/include/device/pci_mmio_cfg.h @@ -90,6 +90,10 @@ void pci_mmio_write_config32(pci_devfn_t dev, uint16_t reg, uint32_t value) #if CONFIG(MMCONF_SUPPORT) +#if CONFIG_MMCONF_BASE_ADDRESS == 0 +#error "CONFIG_MMCONF_BASE_ADDRESS undefined!" +#endif + /* Avoid name collisions as different stages have different signature * for these functions. The _s_ stands for simple, fundamental IO or * MMIO variant. From ddcfcb8ebc64d71717407607323fd18e29fa651e Mon Sep 17 00:00:00 2001 From: Andrey Petrov Date: Mon, 28 Oct 2019 15:11:16 -0700 Subject: [PATCH 0020/1242] soc/intel/fsp_broadwell_de: Add CONFIG_IED_SIZE, drop CONFIG_SMM_TSEG_SIZE Fix regression introduced in recent SMM region handling overhaul. Previously IED region size was hardcoded in the code. However when chip code was modified to use smm_region() and friends, IED_SIZE define was not added and build system quetly substituted it with 0. Also, drop CONFIG_SMM_TSEG_SIZE which is now obsolete. TEST=tested on watson platform; without the patch tg3 NIC driver doesn't work properly and that gets solved with this patch Change-Id: Id6fb258e555bb507851886b0e75f1f53c3762276 Signed-off-by: Andrey Petrov Reviewed-on: https://review.coreboot.org/c/coreboot/+/36417 Reviewed-by: David Hendricks Tested-by: build bot (Jenkins) --- src/soc/intel/fsp_broadwell_de/Kconfig | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/soc/intel/fsp_broadwell_de/Kconfig b/src/soc/intel/fsp_broadwell_de/Kconfig index 4c50828e0d..b2f4968004 100644 --- a/src/soc/intel/fsp_broadwell_de/Kconfig +++ b/src/soc/intel/fsp_broadwell_de/Kconfig @@ -63,9 +63,9 @@ config VGA_BIOS bool default n -config SMM_TSEG_SIZE +config IED_REGION_SIZE hex - default 0x800000 + default 0x400000 config SMM_RESERVED_SIZE hex From 8119841ec0da8ab088ed23961d3a3e4b25551f18 Mon Sep 17 00:00:00 2001 From: Alex James Date: Tue, 22 Oct 2019 18:32:22 -0500 Subject: [PATCH 0021/1242] commonlib: Use __builtin_offsetof with supported compilers Use __builtin_offsetof (which is treated as a constant expression) with Clang & GCC. This also allows check_member to work with Clang 9. Signed-off-by: Alex James Change-Id: I8b5cb4110c13ee42114ecf65932d7f1e5636210e Reviewed-on: https://review.coreboot.org/c/coreboot/+/36249 Reviewed-by: Aaron Durbin Tested-by: build bot (Jenkins) --- src/commonlib/include/commonlib/helpers.h | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/src/commonlib/include/commonlib/helpers.h b/src/commonlib/include/commonlib/helpers.h index f3b71d7016..ca3b3c58f9 100644 --- a/src/commonlib/include/commonlib/helpers.h +++ b/src/commonlib/include/commonlib/helpers.h @@ -108,16 +108,16 @@ #define GHz (1000 * MHz) #ifndef offsetof +#ifdef __ROMCC__ #define offsetof(TYPE, MEMBER) ((size_t) &((TYPE *)0)->MEMBER) +#else +#define offsetof(TYPE, MEMBER) __builtin_offsetof(TYPE, MEMBER) +#endif #endif -#if !defined(__clang__) #define check_member(structure, member, offset) _Static_assert( \ offsetof(struct structure, member) == offset, \ "`struct " #structure "` offset for `" #member "` is not " #offset) -#else -#define check_member(structure, member, offset) -#endif /** * container_of - cast a member of a structure out to the containing structure From 397ce3c45fc8d2469c07565879c09d8fb00626ec Mon Sep 17 00:00:00 2001 From: Wim Vervoorn Date: Wed, 30 Oct 2019 17:06:58 +0100 Subject: [PATCH 0022/1242] vendorcode/eltan/security: Align mboot with coreboot tpm Align the eltan mboot support with coreboot tpm support to limit the amount of custom code. We now only support SHA256 pcrs, only single a single digest will be handled in a call. The pcr invalidation has been changed fixed values are now loaded while the correct algortihm is selected. BUG=N/A TEST=tested on fbg1701 Change-Id: Id11389ca90c1e6121293353402a2dd464a2e6727 Signed-off-by: Wim Vervoorn Reviewed-on: https://review.coreboot.org/c/coreboot/+/36483 Tested-by: build bot (Jenkins) Reviewed-by: Frans Hendriks --- src/mainboard/facebook/fbg1701/romstage.c | 6 +- src/vendorcode/eltan/security/mboot/mboot.c | 141 +++++------------- src/vendorcode/eltan/security/mboot/mboot.h | 15 +- .../eltan/security/mboot/mboot_func.c | 4 +- 4 files changed, 47 insertions(+), 119 deletions(-) diff --git a/src/mainboard/facebook/fbg1701/romstage.c b/src/mainboard/facebook/fbg1701/romstage.c index c10e8666bf..b6ea03f969 100644 --- a/src/mainboard/facebook/fbg1701/romstage.c +++ b/src/mainboard/facebook/fbg1701/romstage.c @@ -78,7 +78,7 @@ static const uint8_t crtm_version[] = CONFIG_VENDORCODE_ELTAN_CRTM_VERSION_STRING COREBOOT_VERSION COREBOOT_EXTRA_VERSION " " COREBOOT_BUILD; -int mb_crtm(EFI_TCG2_EVENT_ALGORITHM_BITMAP activePcr) +int mb_crtm(void) { int status = TPM_E_IOERROR; TCG_PCR_EVENT2_HDR tcgEventHdr; @@ -91,9 +91,9 @@ int mb_crtm(EFI_TCG2_EVENT_ALGORITHM_BITMAP activePcr) tcgEventHdr.eventSize = sizeof(crtm_version); printk(BIOS_DEBUG, "%s: EventSize - %u\n", __func__, tcgEventHdr.eventSize); - status = mboot_hash_extend_log(activePcr, 0, (uint8_t *)crtm_version, + status = mboot_hash_extend_log(0, (uint8_t *)crtm_version, tcgEventHdr.eventSize, &tcgEventHdr, - (uint8_t *)crtm_version, 0); + (uint8_t *)crtm_version); if (status) { printk(BIOS_DEBUG, "Measure CRTM Version returned 0x%x\n", status); } diff --git a/src/vendorcode/eltan/security/mboot/mboot.c b/src/vendorcode/eltan/security/mboot/mboot.c index b24bf3d480..4823c6aa00 100644 --- a/src/vendorcode/eltan/security/mboot/mboot.c +++ b/src/vendorcode/eltan/security/mboot/mboot.c @@ -120,92 +120,37 @@ int tpm2_get_capability_pcrs(TPML_PCR_SELECTION *Pcrs) * Calculates the hash over the data and extends it in active PCR banks and * then logs them in the event log. * - * @param[in] activePcr bitmap of active PCR banks in TPM. - * @param[in] flags flags associated with hash data. Currently - * unused. + * @param[in] flags flags associated with hash data. Currently unused. * @param[in] hashData data to be hashed. * @param[in] hashDataLen length of the data to be hashed. * @param[in] newEventHdr event header in TCG_PCR_EVENT2 format. * @param[in] eventLog description of the event. - * @param[in] invalid invalidate the pcr * * @retval TPM_SUCCESS Operation completed successfully. * @retval TPM_E_IOERROR Unexpected device behavior. */ -int mboot_hash_extend_log(EFI_TCG2_EVENT_ALGORITHM_BITMAP activePcr, - uint64_t flags, uint8_t *hashData, uint32_t hashDataLen, - TCG_PCR_EVENT2_HDR *newEventHdr, uint8_t *eventLog, uint8_t invalid) +int mboot_hash_extend_log(uint64_t flags, uint8_t *hashData, uint32_t hashDataLen, + TCG_PCR_EVENT2_HDR *newEventHdr, uint8_t *eventLog) { - int status; TPMT_HA *digest = NULL; - int digest_num = 0; - printk(BIOS_DEBUG, "%s: Hash Data Length: %zu bytes\n", __func__, - (size_t)hashDataLen); + printk(BIOS_DEBUG, "%s: Hash Data Length: %zu bytes\n", __func__, (size_t)hashDataLen); - if (invalid) { - digest = &(newEventHdr->digest.digests[digest_num]); - digest->hashAlg = TPM_ALG_ERROR; - digest_num++; + /* Generate SHA256 */ + digest = &(newEventHdr->digest.digests[0]); + if (flags & MBOOT_HASH_PROVIDED) { + /* The hash is provided as data */ + memcpy(digest->digest.sha256, (void *)hashData, hashDataLen); } else { - /* - * Generate SHA1 hash if SHA1 PCR bank is active in TPM - * currently - */ - if (activePcr & EFI_TCG2_BOOT_HASH_ALG_SHA1) { - digest = &(newEventHdr->digest.digests[digest_num]); - if (flags & MBOOT_HASH_PROVIDED) { - /* The hash is provided as data */ - memcpy(digest->digest.sha1, (void *)hashData, - VB2_SHA1_DIGEST_SIZE); - } else { - if (cb_sha_little_endian(VB2_HASH_SHA1, hashData, - hashDataLen, digest->digest.sha1)) - return TPM_E_IOERROR; - } - - digest->hashAlg = TPM_ALG_SHA1; - digest_num++; - - printk(BIOS_DEBUG, "%s: SHA1 Hash Digest:\n", __func__); - mboot_print_buffer(digest->digest.sha1, - VB2_SHA1_DIGEST_SIZE); - } - - /* - * Generate SHA256 hash if SHA256 PCR bank is active in TPM - * currently - */ - if (activePcr & EFI_TCG2_BOOT_HASH_ALG_SHA256) { - digest = &(newEventHdr->digest.digests[digest_num]); - if (flags & MBOOT_HASH_PROVIDED) { - /* The hash is provided as data */ - memcpy(digest->digest.sha256, - (void *)hashData, hashDataLen); - } else { - - if (cb_sha_little_endian(VB2_HASH_SHA256, hashData, - hashDataLen, digest->digest.sha256)) - return TPM_E_IOERROR; - } - digest->hashAlg = TPM_ALG_SHA256; - digest_num++; - - printk(BIOS_DEBUG, "%s: SHA256 Hash Digest:\n", - __func__); - mboot_print_buffer(digest->digest.sha256, - VB2_SHA256_DIGEST_SIZE); - } + if (cb_sha_little_endian(VB2_HASH_SHA256, hashData, hashDataLen, + digest->digest.sha256)) + return TPM_E_IOERROR; } - newEventHdr->digest.count = digest_num; + printk(BIOS_DEBUG, "%s: SHA256 Hash Digest:\n", __func__); + mboot_print_buffer(digest->digest.sha256, VB2_SHA256_DIGEST_SIZE); - status = tlcl_extend(newEventHdr->pcrIndex, (uint8_t *)&(newEventHdr->digest), - NULL); - if (status != TPM_SUCCESS) - printk(BIOS_DEBUG, "%s: returned 0x%x\n", __func__, status); - - return status; + return (tlcl_extend(newEventHdr->pcrIndex, (uint8_t *)&(newEventHdr->digest), NULL)); } /* @@ -215,13 +160,11 @@ int mboot_hash_extend_log(EFI_TCG2_EVENT_ALGORITHM_BITMAP activePcr, */ void invalidate_pcrs(void) { - int status, pcr; - TCG_PCR_EVENT2_HDR tcgEventHdr; - EFI_TCG2_EVENT_ALGORITHM_BITMAP ActivePcrs; - uint8_t invalidate; + int pcr; + int status; - ActivePcrs = tpm2_get_active_pcrs(); - invalidate = 1; + TCG_PCR_EVENT2_HDR tcgEventHdr; + uint8_t invalidate = 1; for (pcr = 0; pcr < 8; pcr++) { printk(BIOS_DEBUG, "%s: Invalidating PCR %d\n", __func__, pcr); @@ -230,10 +173,9 @@ void invalidate_pcrs(void) tcgEventHdr.eventType = EV_NO_ACTION; tcgEventHdr.eventSize = (uint32_t) sizeof(invalidate); - status = mboot_hash_extend_log(ActivePcrs, 0, - (uint8_t *)&invalidate, tcgEventHdr.eventSize, - &tcgEventHdr, (uint8_t *)"Invalidate PCR", invalidate); - + status = mboot_hash_extend_log(0, (uint8_t *)&invalidate, + tcgEventHdr.eventSize, &tcgEventHdr, + (uint8_t *)"Invalidate PCR"); if (status != TPM_SUCCESS) printk(BIOS_DEBUG, "%s: invalidating pcr %d returned" " 0x%x\n", __func__, pcr, status); @@ -288,7 +230,6 @@ void mboot_print_buffer(uint8_t *buffer, uint32_t bufferSize) /* * measures and logs the specified cbfs file. * - * @param[in] activePcr bitmap of active PCR banks in TPM. * @param[in] name name of the cbfs file to measure * @param[in] type data type of the cbfs file. * @param[in] pcr pcr to extend. @@ -298,9 +239,8 @@ void mboot_print_buffer(uint8_t *buffer, uint32_t bufferSize) * @retval TPM_SUCCESS Operation completed successfully. * @retval TPM_E_IOERROR Unexpected device behavior. */ -int mb_measure_log_worker(EFI_TCG2_EVENT_ALGORITHM_BITMAP activePcr, - const char *name, uint32_t type, uint32_t pcr, - TCG_EVENTTYPE eventType, const char *event_msg) +int mb_measure_log_worker(const char *name, uint32_t type, uint32_t pcr, + TCG_EVENTTYPE eventType, const char *event_msg) { int status; TCG_PCR_EVENT2_HDR tcgEventHdr; @@ -311,21 +251,18 @@ int mb_measure_log_worker(EFI_TCG2_EVENT_ALGORITHM_BITMAP activePcr, base = cbfs_boot_map_with_leak(name, type, &size); if (base == NULL) { - printk(BIOS_DEBUG, "%s: CBFS locate fail: %s\n", __func__, - name); + printk(BIOS_DEBUG, "%s: CBFS locate fail: %s\n", __func__, name); return VB2_ERROR_READ_FILE_OPEN; } - printk(BIOS_DEBUG, "%s: CBFS locate success: %s\n", - __func__, name); + printk(BIOS_DEBUG, "%s: CBFS locate success: %s\n", __func__, name); memset(&tcgEventHdr, 0, sizeof(tcgEventHdr)); tcgEventHdr.pcrIndex = pcr; tcgEventHdr.eventType = eventType; if (event_msg) tcgEventHdr.eventSize = (uint32_t) strlen(event_msg); - status = mboot_hash_extend_log(activePcr, 0, base, size, &tcgEventHdr, - (uint8_t *)event_msg, 0); + status = mboot_hash_extend_log(0, base, size, &tcgEventHdr, (uint8_t *)event_msg); return status; } @@ -436,18 +373,15 @@ int __attribute__((weak))mb_measure(int wake_from_s3) int __attribute__((weak))mb_measure_log_start(void) { int status; - EFI_TCG2_EVENT_ALGORITHM_BITMAP ActivePcrs; uint32_t i; - ActivePcrs = tpm2_get_active_pcrs(); - - if (ActivePcrs == 0x0) { - printk(BIOS_DEBUG, "%s: No Active PCR Bank in TPM.\n", + if ((tpm2_get_active_pcrs() & EFI_TCG2_BOOT_HASH_ALG_SHA256) == 0x0) { + printk(BIOS_DEBUG, "%s: SHA256 PCR Bank not active in TPM.\n", __func__); return TPM_E_IOERROR; } - status = mb_crtm(ActivePcrs); + status = mb_crtm(); if (status != TPM_SUCCESS) { printk(BIOS_DEBUG, "%s: Fail! CRTM Version can't be measured." " ABORTING!!!\n", __func__); @@ -458,7 +392,7 @@ int __attribute__((weak))mb_measure_log_start(void) /* Log the items defined by the mainboard */ for (i = 0; i < ARRAY_SIZE(mb_log_list); i++) { status = mb_measure_log_worker( - ActivePcrs, mb_log_list[i].cbfs_name, + mb_log_list[i].cbfs_name, mb_log_list[i].cbfs_type, mb_log_list[i].pcr, mb_log_list[i].eventType, mb_log_list[i].event_msg); @@ -490,12 +424,10 @@ static const uint8_t crtm_version[] = * The function can be overridden at the mainboard level my simply creating a * function with the same name there. * - * @param[in] activePcr bitmap of the support - * * @retval TPM_SUCCESS Operation completed successfully. * @retval TPM_E_IOERROR Unexpected device behavior. **/ -int __attribute__((weak))mb_crtm(EFI_TCG2_EVENT_ALGORITHM_BITMAP activePcr) +int __attribute__((weak))mb_crtm(void) { int status; TCG_PCR_EVENT2_HDR tcgEventHdr; @@ -511,9 +443,8 @@ int __attribute__((weak))mb_crtm(EFI_TCG2_EVENT_ALGORITHM_BITMAP activePcr) printk(BIOS_DEBUG, "%s: EventSize - %u\n", __func__, tcgEventHdr.eventSize); - status = mboot_hash_extend_log(activePcr, 0, (uint8_t *)crtm_version, - tcgEventHdr.eventSize, &tcgEventHdr, (uint8_t *)crtm_version, - 0); + status = mboot_hash_extend_log(0, (uint8_t *)crtm_version, tcgEventHdr.eventSize, + &tcgEventHdr, (uint8_t *)crtm_version); if (status) { printk(BIOS_DEBUG, "Measure CRTM Version returned 0x%x\n", status); return status; @@ -535,8 +466,8 @@ int __attribute__((weak))mb_crtm(EFI_TCG2_EVENT_ALGORITHM_BITMAP activePcr) msgPtr = NULL; tcgEventHdr.eventSize = 0; - status = mboot_hash_extend_log(activePcr, MBOOT_HASH_PROVIDED, hash, - sizeof(hash), &tcgEventHdr, msgPtr, 0); + status = mboot_hash_extend_log(MBOOT_HASH_PROVIDED, hash, sizeof(hash), &tcgEventHdr, + msgPtr); if (status) printk(BIOS_DEBUG, "Add ME hash returned 0x%x\n", status); diff --git a/src/vendorcode/eltan/security/mboot/mboot.h b/src/vendorcode/eltan/security/mboot/mboot.h index 96375aba5b..79f23087c2 100644 --- a/src/vendorcode/eltan/security/mboot/mboot.h +++ b/src/vendorcode/eltan/security/mboot/mboot.h @@ -89,16 +89,14 @@ typedef uint32_t EFI_TCG2_EVENT_ALGORITHM_BITMAP; */ #define MBOOT_HASH_PROVIDED (0x00000001) - int is_zero_buffer(void *buffer, unsigned int size); -int mboot_hash_extend_log(EFI_TCG2_EVENT_ALGORITHM_BITMAP activePcr, - uint64_t flags, uint8_t *hashData, uint32_t hashDataLen, - TCG_PCR_EVENT2_HDR *newEventHdr, uint8_t *eventLog, uint8_t invalid); +int mboot_hash_extend_log(uint64_t flags, uint8_t *hashData, uint32_t hashDataLen, + TCG_PCR_EVENT2_HDR *newEventHdr, uint8_t *eventLog); void mboot_print_buffer(uint8_t *buffer, uint32_t bufferSize); -int mb_crtm(EFI_TCG2_EVENT_ALGORITHM_BITMAP activePcr); +int mb_crtm(void); typedef struct { const char *cbfs_name; @@ -108,9 +106,8 @@ typedef struct { const char *event_msg; } mboot_measure_item_t; -int mb_measure_log_worker(EFI_TCG2_EVENT_ALGORITHM_BITMAP activePcr, - const char *name, uint32_t type, uint32_t pcr, - TCG_EVENTTYPE eventType, const char *event_msg); +int mb_measure_log_worker(const char *name, uint32_t type, uint32_t pcr, + TCG_EVENTTYPE eventType, const char *event_msg); int mb_measure_log_start(void); void invalidate_pcrs(void); @@ -122,7 +119,7 @@ int tpm2_get_capability_pcrs(TPML_PCR_SELECTION *Pcrs); int mb_measure(int wake_from_s3); int mb_entry(int wake_from_s3); -int log_efi_specid_event(EFI_TCG2_EVENT_ALGORITHM_BITMAP ActivePcrs); +int log_efi_specid_event(void); int log_event_tcg_20_format(TCG_PCR_EVENT2_HDR *EventHdr, uint8_t *EventLog); int log_event_tcg_12_format(TCG_PCR_EVENT2_HDR *EventHdr, uint8_t *EventLog); diff --git a/src/vendorcode/eltan/security/mboot/mboot_func.c b/src/vendorcode/eltan/security/mboot/mboot_func.c index ec66d345d0..67922048a2 100644 --- a/src/vendorcode/eltan/security/mboot/mboot_func.c +++ b/src/vendorcode/eltan/security/mboot/mboot_func.c @@ -1,7 +1,7 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2018 Eltan B.V. + * Copyright (C) 2018-2019 Eltan B.V. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -15,7 +15,7 @@ #include -int log_efi_specid_event(EFI_TCG2_EVENT_ALGORITHM_BITMAP ActivePcrs) { +int log_efi_specid_event(void) { return TPM_SUCCESS; } From 1058dd84f06fa2fcbdd99eb99da07dccdf5b9722 Mon Sep 17 00:00:00 2001 From: Wim Vervoorn Date: Fri, 1 Nov 2019 10:22:22 +0100 Subject: [PATCH 0023/1242] security/vboot: Removed vboot_prepare from vboot_locator When prog_locate() is called in the stage VBOOT is starting from and the image to be loaded is not the target image vboot_prepare() may be called too early. To prevent this vboot_prepare() is removed from the vboot_locator structure. This allows more control over the start of the vboot logic. To clarify the change the vboot_prepare() has been renamed to vboot_run_logic() and calls to initialize vboot have been added at the following places: postcar_loader: when VBOOT starts in ROMSTAGE romstage_loader: when VBOOT starts in BOOTBLOCK ramstage_loader: when VBOOT starts in ROMSTAGE BUG=N/A TEST=tested on facebook fbg1701 Change-Id: Id5e8fd78458c09dd3896bfd142bd49c2c3d686df Signed-off-by: Wim Vervoorn Reviewed-on: https://review.coreboot.org/c/coreboot/+/36543 Reviewed-by: Frans Hendriks Tested-by: build bot (Jenkins) --- src/arch/x86/postcar_loader.c | 3 +++ src/lib/prog_loaders.c | 5 +++++ src/security/vboot/vboot_common.h | 2 ++ src/security/vboot/vboot_loader.c | 3 +-- 4 files changed, 11 insertions(+), 2 deletions(-) diff --git a/src/arch/x86/postcar_loader.c b/src/arch/x86/postcar_loader.c index 0a5d50cc1a..868b770c18 100644 --- a/src/arch/x86/postcar_loader.c +++ b/src/arch/x86/postcar_loader.c @@ -23,6 +23,7 @@ #include #include #include +#include static inline void stack_push(struct postcar_frame *pcf, uint32_t val) { @@ -171,6 +172,8 @@ static void load_postcar_cbfs(struct prog *prog, struct postcar_frame *pcf) .prog = prog, }; + vboot_run_logic(); + if (prog_locate(prog)) die_with_post_code(POST_INVALID_ROM, "Failed to locate after CAR program.\n"); diff --git a/src/lib/prog_loaders.c b/src/lib/prog_loaders.c index 183a22bff0..72c1de1e34 100644 --- a/src/lib/prog_loaders.c +++ b/src/lib/prog_loaders.c @@ -30,6 +30,7 @@ #include #include #include +#include /* Only can represent up to 1 byte less than size_t. */ const struct mem_region_device addrspace_32bit = @@ -59,6 +60,8 @@ void run_romstage(void) struct prog romstage = PROG_INIT(PROG_ROMSTAGE, CONFIG_CBFS_PREFIX "/romstage"); + vboot_run_logic(); + if (prog_locate(&romstage)) goto fail; @@ -135,6 +138,8 @@ void run_ramstage(void) !CONFIG(NO_STAGE_CACHE)) run_ramstage_from_resume(&ramstage); + vboot_run_logic(); + if (prog_locate(&ramstage)) goto fail; diff --git a/src/security/vboot/vboot_common.h b/src/security/vboot/vboot_common.h index 8aadf9e420..42b4a6b59b 100644 --- a/src/security/vboot/vboot_common.h +++ b/src/security/vboot/vboot_common.h @@ -76,12 +76,14 @@ int vboot_developer_mode_enabled(void); int vboot_recovery_mode_enabled(void); int vboot_recovery_mode_memory_retrain(void); int vboot_can_enable_udc(void); +void vboot_run_logic(void); #else /* !CONFIG_VBOOT */ static inline int vboot_developer_mode_enabled(void) { return 0; } static inline int vboot_recovery_mode_enabled(void) { return 0; } static inline int vboot_recovery_mode_memory_retrain(void) { return 0; } /* If VBOOT is not enabled, we are okay enabling USB device controller (UDC). */ static inline int vboot_can_enable_udc(void) { return 1; } +static inline void vboot_run_logic(void) {} #endif #endif /* __VBOOT_VBOOT_COMMON_H__ */ diff --git a/src/security/vboot/vboot_loader.c b/src/security/vboot/vboot_loader.c index 3aac48d174..2b7ba83503 100644 --- a/src/security/vboot/vboot_loader.c +++ b/src/security/vboot/vboot_loader.c @@ -35,7 +35,7 @@ _Static_assert(!CONFIG(VBOOT_RETURN_FROM_VERSTAGE) || int vboot_executed CAR_GLOBAL; -static void vboot_prepare(void) +void vboot_run_logic(void) { if (verification_should_run()) { /* Note: this path is not used for VBOOT_RETURN_FROM_VERSTAGE */ @@ -90,6 +90,5 @@ static int vboot_locate(struct cbfs_props *props) const struct cbfs_locator vboot_locator = { .name = "VBOOT", - .prepare = vboot_prepare, .locate = vboot_locate, }; From 8fc523e3137cfdde970a3c87e22b8bbc586a3f7e Mon Sep 17 00:00:00 2001 From: Wim Vervoorn Date: Fri, 1 Nov 2019 12:43:58 +0100 Subject: [PATCH 0024/1242] drivers/intel/fsp2_0: Use strip_quotes for cbfs filenames The quotes were not stripped for the cbfs filenames of the FSP components. This is causing problems when the regions-for-file macro is executed (when VBOOT is enabled and the files should be filtered). BUG=N/A TEST=build Change-Id: I14267502cfab5308d3874a0c0fd18a71b08bb9f8 Signed-off-by: Wim Vervoorn Reviewed-on: https://review.coreboot.org/c/coreboot/+/36548 Reviewed-by: Frans Hendriks Reviewed-by: Nico Huber Tested-by: build bot (Jenkins) --- src/drivers/intel/fsp2_0/Makefile.inc | 26 ++++++++++++++----------- src/soc/intel/apollolake/Makefile.inc | 2 +- src/soc/intel/denverton_ns/Makefile.inc | 6 +++--- src/soc/intel/quark/Makefile.inc | 2 +- 4 files changed, 20 insertions(+), 16 deletions(-) diff --git a/src/drivers/intel/fsp2_0/Makefile.inc b/src/drivers/intel/fsp2_0/Makefile.inc index 8e69377789..806d8057ac 100644 --- a/src/drivers/intel/fsp2_0/Makefile.inc +++ b/src/drivers/intel/fsp2_0/Makefile.inc @@ -42,25 +42,29 @@ postcar-y += hand_off_block.c CPPFLAGS_common += -I$(src)/drivers/intel/fsp2_0/include +FSP_T_CBFS = $(call strip_quotes,$(CONFIG_FSP_T_CBFS)) +FSP_M_CBFS = $(call strip_quotes,$(CONFIG_FSP_M_CBFS)) +FSP_S_CBFS = $(call strip_quotes,$(CONFIG_FSP_S_CBFS)) + # Add FSP blobs into cbfs. SoC code may supply additional options with # -options, e.g --xip or -b -cbfs-files-$(CONFIG_FSP_CAR) += $(CONFIG_FSP_T_CBFS) -$(CONFIG_FSP_T_CBFS)-file := $(call strip_quotes,$(CONFIG_FSP_T_FILE)) -$(CONFIG_FSP_T_CBFS)-type := fsp +cbfs-files-$(CONFIG_FSP_CAR) += $(FSP_T_CBFS) +$(FSP_T_CBFS)-file := $(call strip_quotes,$(CONFIG_FSP_T_FILE)) +$(FSP_T_CBFS)-type := fsp ifeq ($(CONFIG_FSP_T_XIP),y) -$(CONFIG_FSP_T_CBFS)-options := --xip $(TXTIBB) +$(FSP_T_CBFS)-options := --xip $(TXTIBB) endif -cbfs-files-$(CONFIG_ADD_FSP_BINARIES) += $(CONFIG_FSP_M_CBFS) -$(CONFIG_FSP_M_CBFS)-file := $(call strip_quotes,$(CONFIG_FSP_M_FILE)) -$(CONFIG_FSP_M_CBFS)-type := fsp +cbfs-files-$(CONFIG_ADD_FSP_BINARIES) += $(FSP_M_CBFS) +$(FSP_M_CBFS)-file := $(call strip_quotes,$(CONFIG_FSP_M_FILE)) +$(FSP_M_CBFS)-type := fsp ifeq ($(CONFIG_FSP_M_XIP),y) -$(CONFIG_FSP_M_CBFS)-options := --xip $(TXTIBB) +$(FSP_M_CBFS)-options := --xip $(TXTIBB) endif -cbfs-files-$(CONFIG_ADD_FSP_BINARIES) += $(CONFIG_FSP_S_CBFS) -$(CONFIG_FSP_S_CBFS)-file := $(call strip_quotes,$(CONFIG_FSP_S_FILE)) -$(CONFIG_FSP_S_CBFS)-type := fsp +cbfs-files-$(CONFIG_ADD_FSP_BINARIES) += $(FSP_S_CBFS) +$(FSP_S_CBFS)-file := $(call strip_quotes,$(CONFIG_FSP_S_FILE)) +$(FSP_S_CBFS)-type := fsp ifeq ($(CONFIG_FSP_USE_REPO),y) $(obj)/Fsp_M.fd: $(call strip_quotes,$(CONFIG_FSP_FD_PATH)) diff --git a/src/soc/intel/apollolake/Makefile.inc b/src/soc/intel/apollolake/Makefile.inc index 7655d5aa9a..42cbab048f 100644 --- a/src/soc/intel/apollolake/Makefile.inc +++ b/src/soc/intel/apollolake/Makefile.inc @@ -108,7 +108,7 @@ endif CPPFLAGS_common += -I$(src)/soc/intel/apollolake/include # Since FSP-M runs in CAR we need to relocate it to a specific address -$(CONFIG_FSP_M_CBFS)-options := -b $(CONFIG_FSP_M_ADDR) +$(FSP_M_CBFS)-options := -b $(CONFIG_FSP_M_ADDR) # Handle GLK paging requirements ifeq ($(CONFIG_PAGING_IN_CACHE_AS_RAM),y) diff --git a/src/soc/intel/denverton_ns/Makefile.inc b/src/soc/intel/denverton_ns/Makefile.inc index 10bb665bd0..51ae1369c5 100644 --- a/src/soc/intel/denverton_ns/Makefile.inc +++ b/src/soc/intel/denverton_ns/Makefile.inc @@ -90,8 +90,8 @@ CPPFLAGS_common += -I$(src)/vendorcode/intel/fsp/fsp2_0/denverton_ns ##Set FSP binary blobs memory location -$(CONFIG_FSP_T_CBFS)-options := -b $(CONFIG_FSP_T_ADDR) --xip -$(CONFIG_FSP_M_CBFS)-options := -b $(CONFIG_FSP_M_ADDR) --xip -$(CONFIG_FSP_S_CBFS)-options := -b $(CONFIG_FSP_S_ADDR) --xip +$(FSP_T_CBFS)-options := -b $(CONFIG_FSP_T_ADDR) --xip +$(FSP_M_CBFS)-options := -b $(CONFIG_FSP_M_ADDR) --xip +$(FSP_S_CBFS)-options := -b $(CONFIG_FSP_S_ADDR) --xip endif ## CONFIG_SOC_INTEL_DENVERTON_NS diff --git a/src/soc/intel/quark/Makefile.inc b/src/soc/intel/quark/Makefile.inc index 3a58cc9235..f2413c8805 100644 --- a/src/soc/intel/quark/Makefile.inc +++ b/src/soc/intel/quark/Makefile.inc @@ -71,7 +71,7 @@ CPPFLAGS_common += -I$(src)/soc/intel/quark/include/soc/fsp CPPFLAGS_common += -I3rdparty/blobs/soc/intel/quark # Since FSP-M runs in CAR we need to relocate it to a specific address -$(CONFIG_FSP_M_CBFS)-options := -b $(CONFIG_FSP_ESRAM_LOC) +$(FSP_M_CBFS)-options := -b $(CONFIG_FSP_ESRAM_LOC) # Add the FSP binary to the CBFS image cbfs-files-$(CONFIG_ADD_FSP_RAW_BIN) += fsp.bin From 6b5bf407deb52a900ef0a8a0b99f853be1eb7e82 Mon Sep 17 00:00:00 2001 From: Ravi Sarawadi Date: Mon, 21 Oct 2019 22:25:04 -0700 Subject: [PATCH 0025/1242] soc/intel/common: Include Tigerlake device IDs Add Tigerlake specific CPU, System Agent, PCH, IGD device IDs. BUG=None BRANCH=None TEST=Build 'emerge-tglrvp coreboot' Signed-off-by: Ravi Sarawadi Change-Id: I19047354718bdf510dffee4659d885f1313a751b Reviewed-on: https://review.coreboot.org/c/coreboot/+/36225 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Rudolph Reviewed-by: Subrata Banik --- src/include/device/pci_ids.h | 55 +++++++++++++++++++ src/soc/intel/common/block/cpu/mp_init.c | 1 + src/soc/intel/common/block/cse/cse.c | 1 + src/soc/intel/common/block/dsp/dsp.c | 1 + .../intel/common/block/graphics/graphics.c | 4 ++ src/soc/intel/common/block/hda/hda.c | 1 + src/soc/intel/common/block/i2c/i2c.c | 8 +++ .../block/include/intelblocks/mp_init.h | 1 + src/soc/intel/common/block/lpc/lpc.c | 1 + src/soc/intel/common/block/p2sb/p2sb.c | 1 + src/soc/intel/common/block/pcie/pcie.c | 16 ++++++ src/soc/intel/common/block/pmc/pmc.c | 1 + src/soc/intel/common/block/sata/sata.c | 4 ++ src/soc/intel/common/block/smbus/smbus.c | 1 + src/soc/intel/common/block/spi/spi.c | 8 +++ src/soc/intel/common/block/sram/sram.c | 1 + .../common/block/systemagent/systemagent.c | 2 + src/soc/intel/common/block/uart/uart.c | 3 + src/soc/intel/common/block/xdci/xdci.c | 1 + src/soc/intel/common/block/xhci/xhci.c | 1 + 20 files changed, 112 insertions(+) diff --git a/src/include/device/pci_ids.h b/src/include/device/pci_ids.h index 3cab86bd1c..4d21f5b045 100644 --- a/src/include/device/pci_ids.h +++ b/src/include/device/pci_ids.h @@ -2767,6 +2767,7 @@ #define PCI_DEVICE_ID_INTEL_CMP_PREMIUM_U_LPC 0x0284 #define PCI_DEVICE_ID_INTEL_CMP_BASE_U_LPC 0x0285 #define PCI_DEVICE_ID_INTEL_CMP_SUPER_Y_LPC 0x0286 +#define PCI_DEVICE_ID_INTEL_TGL_ESPI 0xA083 /* Intel PCIE device ids */ #define PCI_DEVICE_ID_INTEL_SPT_LP_PCIE_RP1 0x9d10 @@ -2903,6 +2904,23 @@ #define PCI_DEVICE_ID_INTEL_ICP_LP_PCIE_RP15 0x34b6 #define PCI_DEVICE_ID_INTEL_ICP_LP_PCIE_RP16 0x34b7 +#define PCI_DEVICE_ID_INTEL_TGP_LP_PCIE_RP1 0xa0b8 +#define PCI_DEVICE_ID_INTEL_TGP_LP_PCIE_RP2 0xa0b9 +#define PCI_DEVICE_ID_INTEL_TGP_LP_PCIE_RP3 0xa0ba +#define PCI_DEVICE_ID_INTEL_TGP_LP_PCIE_RP4 0xa0bb +#define PCI_DEVICE_ID_INTEL_TGP_LP_PCIE_RP5 0xa0bc +#define PCI_DEVICE_ID_INTEL_TGP_LP_PCIE_RP6 0xa0bd +#define PCI_DEVICE_ID_INTEL_TGP_LP_PCIE_RP7 0xa0be +#define PCI_DEVICE_ID_INTEL_TGP_LP_PCIE_RP8 0xa0bf +#define PCI_DEVICE_ID_INTEL_TGP_LP_PCIE_RP9 0xa0b0 +#define PCI_DEVICE_ID_INTEL_TGP_LP_PCIE_RP10 0xa0b1 +#define PCI_DEVICE_ID_INTEL_TGP_LP_PCIE_RP11 0xa0b2 +#define PCI_DEVICE_ID_INTEL_TGP_LP_PCIE_RP12 0xa0b3 +#define PCI_DEVICE_ID_INTEL_TGP_LP_PCIE_RP13 0xa0b4 +#define PCI_DEVICE_ID_INTEL_TGP_LP_PCIE_RP14 0xa0b5 +#define PCI_DEVICE_ID_INTEL_TGP_LP_PCIE_RP15 0xa0b6 +#define PCI_DEVICE_ID_INTEL_TGP_LP_PCIE_RP16 0xa0b7 + #define PCI_DEVICE_ID_INTEL_CNP_H_PCIE_RP1 0xa338 #define PCI_DEVICE_ID_INTEL_CNP_H_PCIE_RP2 0xa339 #define PCI_DEVICE_ID_INTEL_CNP_H_PCIE_RP3 0xa33a @@ -2972,6 +2990,10 @@ #define PCI_DEVICE_ID_INTEL_CMP_SATA 0x02d5 #define PCI_DEVICE_ID_INTEL_CMP_PREMIUM_SATA 0x02d7 #define PCI_DEVICE_ID_INTEL_CMP_LP_SATA 0x02d3 +#define PCI_DEVICE_ID_INTEL_TGP_LP_SATA 0xa0d3 +#define PCI_DEVICE_ID_INTEL_TGP_SATA 0xa0d5 +#define PCI_DEVICE_ID_INTEL_TGP_PREMIUM_SATA 0xa0d7 +#define PCI_DEVICE_ID_INTEL_TGP_COMPAT_SATA 0x282a /* Intel PMC device Ids */ #define PCI_DEVICE_ID_INTEL_SPT_LP_PMC 0x9d21 @@ -2985,6 +3007,7 @@ #define PCI_DEVICE_ID_INTEL_CNP_H_PMC 0xa321 #define PCI_DEVICE_ID_INTEL_ICP_PMC 0x34a1 #define PCI_DEVICE_ID_INTEL_CMP_PMC 0x02a1 +#define PCI_DEVICE_ID_INTEL_TGP_PMC 0xa0a1 /* Intel I2C device Ids */ #define PCI_DEVICE_ID_INTEL_SPT_I2C0 0x9d60 @@ -3035,6 +3058,14 @@ #define PCI_DEVICE_ID_INTEL_CMP_I2C3 0x02eb #define PCI_DEVICE_ID_INTEL_CMP_I2C4 0x02c5 #define PCI_DEVICE_ID_INTEL_CMP_I2C5 0x02c6 +#define PCI_DEVICE_ID_INTEL_TGP_I2C0 0xa0e8 +#define PCI_DEVICE_ID_INTEL_TGP_I2C1 0xa0e9 +#define PCI_DEVICE_ID_INTEL_TGP_I2C2 0xa0ea +#define PCI_DEVICE_ID_INTEL_TGP_I2C3 0xa0eb +#define PCI_DEVICE_ID_INTEL_TGP_I2C4 0xa0c5 +#define PCI_DEVICE_ID_INTEL_TGP_I2C5 0xa0c6 +#define PCI_DEVICE_ID_INTEL_TGP_I2C6 0xa0d8 +#define PCI_DEVICE_ID_INTEL_TGP_I2C7 0xa0d9 /* Intel UART device Ids */ #define PCI_DEVICE_ID_INTEL_SPT_UART0 0x9d27 @@ -3066,6 +3097,9 @@ #define PCI_DEVICE_ID_INTEL_CMP_UART0 0x02a8 #define PCI_DEVICE_ID_INTEL_CMP_UART1 0x02a9 #define PCI_DEVICE_ID_INTEL_CMP_UART2 0x02c7 +#define PCI_DEVICE_ID_INTEL_TGP_UART0 0xa0a8 +#define PCI_DEVICE_ID_INTEL_TGP_UART1 0xa0a9 +#define PCI_DEVICE_ID_INTEL_TGP_UART2 0xa0c7 /* Intel SPI device Ids */ #define PCI_DEVICE_ID_INTEL_SPT_SPI1 0x9d24 @@ -3096,6 +3130,14 @@ #define PCI_DEVICE_ID_INTEL_CMP_SPI1 0x02ab #define PCI_DEVICE_ID_INTEL_CMP_SPI2 0x02fb #define PCI_DEVICE_ID_INTEL_CMP_HWSEQ_SPI 0x02a4 +#define PCI_DEVICE_ID_INTEL_TGP_SPI0 0xa0a4 +#define PCI_DEVICE_ID_INTEL_TGP_GSPI0 0xa0aa +#define PCI_DEVICE_ID_INTEL_TGP_GSPI1 0xa0ab +#define PCI_DEVICE_ID_INTEL_TGP_GSPI2 0x34fb +#define PCI_DEVICE_ID_INTEL_TGP_GSPI3 0xa0fd +#define PCI_DEVICE_ID_INTEL_TGP_GSPI4 0xa0fe +#define PCI_DEVICE_ID_INTEL_TGP_GSPI5 0xa0de +#define PCI_DEVICE_ID_INTEL_TGP_GSPI6 0xa0df /* Intel IGD device Ids */ #define PCI_DEVICE_ID_INTEL_SKL_GT1F_DT2 0x1902 @@ -3187,6 +3229,10 @@ #define PCI_DEVICE_ID_INTEL_CML_GT1_H_2 0x9B22 #define PCI_DEVICE_ID_INTEL_CML_GT2_H_1 0x9B44 #define PCI_DEVICE_ID_INTEL_CML_GT2_H_2 0x9B42 +#define PCI_DEVICE_ID_INTEL_TGL_GT1 0X9A60 +#define PCI_DEVICE_ID_INTEL_TGL_GT2_UY 0X9A49 +#define PCI_DEVICE_ID_INTEL_TGL_GT2 0XFF20 +#define PCI_DEVICE_ID_INTEL_TGL_GT2_Y 0X9A40 /* Intel Northbridge Ids */ #define PCI_DEVICE_ID_INTEL_APL_NB 0x5af0 @@ -3237,6 +3283,8 @@ #define PCI_DEVICE_ID_INTEL_CML_S_10_2 0x9B35 #define PCI_DEVICE_ID_INTEL_CML_H 0x9B54 #define PCI_DEVICE_ID_INTEL_CML_H_8_2 0x9B44 +#define PCI_DEVICE_ID_INTEL_TGL_ID_U 0x9A14 +#define PCI_DEVICE_ID_INTEL_TGL_ID_Y 0x9A12 /* Intel SMBUS device Ids */ #define PCI_DEVICE_ID_INTEL_SPT_LP_SMBUS 0x9d23 @@ -3247,6 +3295,7 @@ #define PCI_DEVICE_ID_INTEL_CNP_H_SMBUS 0xa323 #define PCI_DEVICE_ID_INTEL_ICP_LP_SMBUS 0x34a3 #define PCI_DEVICE_ID_INTEL_CMP_SMBUS 0x02a3 +#define PCI_DEVICE_ID_INTEL_TGP_LP_SMBUS 0xa0a3 /* Intel XHCI device Ids */ #define PCI_DEVICE_ID_INTEL_APL_XHCI 0x5aa8 @@ -3260,6 +3309,7 @@ #define PCI_DEVICE_ID_INTEL_CNP_H_XHCI 0xa36d #define PCI_DEVICE_ID_INTEL_ICP_LP_XHCI 0x34ed #define PCI_DEVICE_ID_INTEL_CMP_LP_XHCI 0x02ed +#define PCI_DEVICE_ID_INTEL_TGP_LP_XHCI 0xa0ed /* Intel P2SB device Ids */ #define PCI_DEVICE_ID_INTEL_APL_P2SB 0x5a92 @@ -3273,6 +3323,7 @@ #define PCI_DEVICE_ID_INTEL_CNP_H_P2SB 0xa320 #define PCI_DEVICE_ID_INTEL_ICL_P2SB 0x34a0 #define PCI_DEVICE_ID_INTEL_CMP_P2SB 0x02a0 +#define PCI_DEVICE_ID_INTEL_TGL_P2SB 0xa0a0 /* Intel SRAM device Ids */ #define PCI_DEVICE_ID_INTEL_APL_SRAM 0x5aec @@ -3281,6 +3332,7 @@ #define PCI_DEVICE_ID_INTEL_CNP_H_SRAM 0xa36f #define PCI_DEVICE_ID_INTEL_ICL_SRAM 0x34ef #define PCI_DEVICE_ID_INTEL_CMP_SRAM 0x02ef +#define PCI_DEVICE_ID_INTEL_TGL_SRAM 0xa0ef /* Intel AUDIO device Ids */ #define PCI_DEVICE_ID_INTEL_APL_AUDIO 0x5a98 @@ -3295,6 +3347,7 @@ #define PCI_DEVICE_ID_INTEL_ICL_AUDIO 0x34c8 #define PCI_DEVICE_ID_INTEL_CMP_AUDIO 0x02c8 #define PCI_DEVICE_ID_INTEL_BSW_AUDIO 0x2284 +#define PCI_DEVICE_ID_INTEL_TGL_AUDIO 0xa0c8 /* Intel HECI/ME device Ids */ #define PCI_DEVICE_ID_INTEL_APL_CSE0 0x5a9a @@ -3310,6 +3363,7 @@ #define PCI_DEVICE_ID_INTEL_CNP_H_CSE0 0xa360 #define PCI_DEVICE_ID_INTEL_ICL_CSE0 0x34e0 #define PCI_DEVICE_ID_INTEL_CMP_CSE0 0x02e0 +#define PCI_DEVICE_ID_INTEL_TGL_CSE0 0xa0e0 /* Intel XDCI device Ids */ #define PCI_DEVICE_ID_INTEL_APL_XDCI 0x5aaa @@ -3319,6 +3373,7 @@ #define PCI_DEVICE_ID_INTEL_CNP_H_XDCI 0xa36e #define PCI_DEVICE_ID_INTEL_ICP_LP_XDCI 0x34ee #define PCI_DEVICE_ID_INTEL_CMP_LP_XDCI 0x02ee +#define PCI_DEVICE_ID_INTEL_TGP_LP_XDCI 0xa0ee /* Intel SD device Ids */ #define PCI_DEVICE_ID_INTEL_APL_SD 0x5aca diff --git a/src/soc/intel/common/block/cpu/mp_init.c b/src/soc/intel/common/block/cpu/mp_init.c index 2c5061f1d6..df571ba775 100644 --- a/src/soc/intel/common/block/cpu/mp_init.c +++ b/src/soc/intel/common/block/cpu/mp_init.c @@ -84,6 +84,7 @@ static const struct cpu_device_id cpu_table[] = { { X86_VENDOR_INTEL, CPUID_COMETLAKE_U_K0_S0 }, { X86_VENDOR_INTEL, CPUID_COMETLAKE_H_S_6_2_P0 }, { X86_VENDOR_INTEL, CPUID_COMETLAKE_H_S_10_2_P0 }, + { X86_VENDOR_INTEL, CPUID_TIGERLAKE_A0 }, { 0, 0 }, }; diff --git a/src/soc/intel/common/block/cse/cse.c b/src/soc/intel/common/block/cse/cse.c index 0bd5c72ef5..5eb37611f5 100644 --- a/src/soc/intel/common/block/cse/cse.c +++ b/src/soc/intel/common/block/cse/cse.c @@ -754,6 +754,7 @@ static const unsigned short pci_device_ids[] = { PCI_DEVICE_ID_INTEL_CNP_H_CSE0, PCI_DEVICE_ID_INTEL_ICL_CSE0, PCI_DEVICE_ID_INTEL_CMP_CSE0, + PCI_DEVICE_ID_INTEL_TGL_CSE0, 0, }; diff --git a/src/soc/intel/common/block/dsp/dsp.c b/src/soc/intel/common/block/dsp/dsp.c index 277b6c5aab..947c002250 100644 --- a/src/soc/intel/common/block/dsp/dsp.c +++ b/src/soc/intel/common/block/dsp/dsp.c @@ -34,6 +34,7 @@ static const unsigned short pci_device_ids[] = { PCI_DEVICE_ID_INTEL_CNP_H_AUDIO, PCI_DEVICE_ID_INTEL_CMP_AUDIO, PCI_DEVICE_ID_INTEL_ICL_AUDIO, + PCI_DEVICE_ID_INTEL_TGL_AUDIO, 0, }; diff --git a/src/soc/intel/common/block/graphics/graphics.c b/src/soc/intel/common/block/graphics/graphics.c index 8e79eab54e..4efa60f5d2 100644 --- a/src/soc/intel/common/block/graphics/graphics.c +++ b/src/soc/intel/common/block/graphics/graphics.c @@ -207,6 +207,10 @@ static const unsigned short pci_device_ids[] = { PCI_DEVICE_ID_INTEL_CML_GT1_H_2, PCI_DEVICE_ID_INTEL_CML_GT2_H_1, PCI_DEVICE_ID_INTEL_CML_GT2_H_2, + PCI_DEVICE_ID_INTEL_TGL_GT1, + PCI_DEVICE_ID_INTEL_TGL_GT2_UY, + PCI_DEVICE_ID_INTEL_TGL_GT2, + PCI_DEVICE_ID_INTEL_TGL_GT2_Y, 0, }; diff --git a/src/soc/intel/common/block/hda/hda.c b/src/soc/intel/common/block/hda/hda.c index be8319c058..4a87e1a2ef 100644 --- a/src/soc/intel/common/block/hda/hda.c +++ b/src/soc/intel/common/block/hda/hda.c @@ -82,6 +82,7 @@ static const unsigned short pci_device_ids[] = { PCI_DEVICE_ID_INTEL_ICL_AUDIO, PCI_DEVICE_ID_INTEL_CMP_AUDIO, PCI_DEVICE_ID_INTEL_BSW_AUDIO, + PCI_DEVICE_ID_INTEL_TGL_AUDIO, 0 }; diff --git a/src/soc/intel/common/block/i2c/i2c.c b/src/soc/intel/common/block/i2c/i2c.c index fb7aea2c17..1749bf547a 100644 --- a/src/soc/intel/common/block/i2c/i2c.c +++ b/src/soc/intel/common/block/i2c/i2c.c @@ -235,6 +235,14 @@ static const unsigned short pci_device_ids[] = { PCI_DEVICE_ID_INTEL_CMP_I2C3, PCI_DEVICE_ID_INTEL_CMP_I2C4, PCI_DEVICE_ID_INTEL_CMP_I2C5, + PCI_DEVICE_ID_INTEL_TGP_I2C0, + PCI_DEVICE_ID_INTEL_TGP_I2C1, + PCI_DEVICE_ID_INTEL_TGP_I2C2, + PCI_DEVICE_ID_INTEL_TGP_I2C3, + PCI_DEVICE_ID_INTEL_TGP_I2C4, + PCI_DEVICE_ID_INTEL_TGP_I2C5, + PCI_DEVICE_ID_INTEL_TGP_I2C6, + PCI_DEVICE_ID_INTEL_TGP_I2C7, 0, }; diff --git a/src/soc/intel/common/block/include/intelblocks/mp_init.h b/src/soc/intel/common/block/include/intelblocks/mp_init.h index 5ef7641a3a..e5475383f7 100644 --- a/src/soc/intel/common/block/include/intelblocks/mp_init.h +++ b/src/soc/intel/common/block/include/intelblocks/mp_init.h @@ -51,6 +51,7 @@ #define CPUID_COMETLAKE_U_K0_S0 0xa0661 #define CPUID_COMETLAKE_H_S_6_2_P0 0xa0650 #define CPUID_COMETLAKE_H_S_10_2_P0 0xa0651 +#define CPUID_TIGERLAKE_A0 0x806c0 /* * MP Init callback function to Find CPU Topology. This function is common diff --git a/src/soc/intel/common/block/lpc/lpc.c b/src/soc/intel/common/block/lpc/lpc.c index eb7de081bc..c2b51bec9b 100644 --- a/src/soc/intel/common/block/lpc/lpc.c +++ b/src/soc/intel/common/block/lpc/lpc.c @@ -190,6 +190,7 @@ static const unsigned short pci_device_ids[] = { PCI_DEVICE_ID_INTEL_CMP_PREMIUM_U_LPC, PCI_DEVICE_ID_INTEL_CMP_BASE_U_LPC, PCI_DEVICE_ID_INTEL_CMP_SUPER_Y_LPC, + PCI_DEVICE_ID_INTEL_TGL_ESPI, 0 }; diff --git a/src/soc/intel/common/block/p2sb/p2sb.c b/src/soc/intel/common/block/p2sb/p2sb.c index 14e1fd90eb..981ad07872 100644 --- a/src/soc/intel/common/block/p2sb/p2sb.c +++ b/src/soc/intel/common/block/p2sb/p2sb.c @@ -179,6 +179,7 @@ static const unsigned short pci_device_ids[] = { PCI_DEVICE_ID_INTEL_CNP_H_P2SB, PCI_DEVICE_ID_INTEL_ICL_P2SB, PCI_DEVICE_ID_INTEL_CMP_P2SB, + PCI_DEVICE_ID_INTEL_TGL_P2SB, 0, }; diff --git a/src/soc/intel/common/block/pcie/pcie.c b/src/soc/intel/common/block/pcie/pcie.c index c8ca4f4d87..406a227387 100644 --- a/src/soc/intel/common/block/pcie/pcie.c +++ b/src/soc/intel/common/block/pcie/pcie.c @@ -250,6 +250,22 @@ static const unsigned short pcie_device_ids[] = { PCI_DEVICE_ID_INTEL_CMP_LP_PCIE_RP14, PCI_DEVICE_ID_INTEL_CMP_LP_PCIE_RP15, PCI_DEVICE_ID_INTEL_CMP_LP_PCIE_RP16, + PCI_DEVICE_ID_INTEL_TGP_LP_PCIE_RP1, + PCI_DEVICE_ID_INTEL_TGP_LP_PCIE_RP2, + PCI_DEVICE_ID_INTEL_TGP_LP_PCIE_RP3, + PCI_DEVICE_ID_INTEL_TGP_LP_PCIE_RP4, + PCI_DEVICE_ID_INTEL_TGP_LP_PCIE_RP5, + PCI_DEVICE_ID_INTEL_TGP_LP_PCIE_RP6, + PCI_DEVICE_ID_INTEL_TGP_LP_PCIE_RP7, + PCI_DEVICE_ID_INTEL_TGP_LP_PCIE_RP8, + PCI_DEVICE_ID_INTEL_TGP_LP_PCIE_RP9, + PCI_DEVICE_ID_INTEL_TGP_LP_PCIE_RP10, + PCI_DEVICE_ID_INTEL_TGP_LP_PCIE_RP11, + PCI_DEVICE_ID_INTEL_TGP_LP_PCIE_RP12, + PCI_DEVICE_ID_INTEL_TGP_LP_PCIE_RP13, + PCI_DEVICE_ID_INTEL_TGP_LP_PCIE_RP14, + PCI_DEVICE_ID_INTEL_TGP_LP_PCIE_RP15, + PCI_DEVICE_ID_INTEL_TGP_LP_PCIE_RP16, 0 }; diff --git a/src/soc/intel/common/block/pmc/pmc.c b/src/soc/intel/common/block/pmc/pmc.c index 2b148f2021..1d2aa61807 100644 --- a/src/soc/intel/common/block/pmc/pmc.c +++ b/src/soc/intel/common/block/pmc/pmc.c @@ -133,6 +133,7 @@ static const unsigned short pci_device_ids[] = { PCI_DEVICE_ID_INTEL_CNP_H_PMC, PCI_DEVICE_ID_INTEL_ICP_PMC, PCI_DEVICE_ID_INTEL_CMP_PMC, + PCI_DEVICE_ID_INTEL_TGP_PMC, 0 }; diff --git a/src/soc/intel/common/block/sata/sata.c b/src/soc/intel/common/block/sata/sata.c index 0c278f37f2..13ac32e766 100644 --- a/src/soc/intel/common/block/sata/sata.c +++ b/src/soc/intel/common/block/sata/sata.c @@ -96,6 +96,10 @@ static const unsigned short pci_device_ids[] = { PCI_DEVICE_ID_INTEL_CMP_SATA, PCI_DEVICE_ID_INTEL_CMP_PREMIUM_SATA, PCI_DEVICE_ID_INTEL_CMP_LP_SATA, + PCI_DEVICE_ID_INTEL_TGP_LP_SATA, + PCI_DEVICE_ID_INTEL_TGP_SATA, + PCI_DEVICE_ID_INTEL_TGP_PREMIUM_SATA, + PCI_DEVICE_ID_INTEL_TGP_COMPAT_SATA, 0 }; diff --git a/src/soc/intel/common/block/smbus/smbus.c b/src/soc/intel/common/block/smbus/smbus.c index 77b05c1826..56f54d7d17 100644 --- a/src/soc/intel/common/block/smbus/smbus.c +++ b/src/soc/intel/common/block/smbus/smbus.c @@ -95,6 +95,7 @@ static const unsigned short pci_device_ids[] = { PCI_DEVICE_ID_INTEL_KBP_H_LWB_SMBUS, PCI_DEVICE_ID_INTEL_ICP_LP_SMBUS, PCI_DEVICE_ID_INTEL_CMP_SMBUS, + PCI_DEVICE_ID_INTEL_TGP_LP_SMBUS, 0 }; diff --git a/src/soc/intel/common/block/spi/spi.c b/src/soc/intel/common/block/spi/spi.c index 365da2faa6..3c77cc4c81 100644 --- a/src/soc/intel/common/block/spi/spi.c +++ b/src/soc/intel/common/block/spi/spi.c @@ -81,6 +81,14 @@ static const unsigned short pci_device_ids[] = { PCI_DEVICE_ID_INTEL_CMP_SPI1, PCI_DEVICE_ID_INTEL_CMP_SPI2, PCI_DEVICE_ID_INTEL_CMP_HWSEQ_SPI, + PCI_DEVICE_ID_INTEL_TGP_SPI0, + PCI_DEVICE_ID_INTEL_TGP_GSPI0, + PCI_DEVICE_ID_INTEL_TGP_GSPI1, + PCI_DEVICE_ID_INTEL_TGP_GSPI2, + PCI_DEVICE_ID_INTEL_TGP_GSPI3, + PCI_DEVICE_ID_INTEL_TGP_GSPI4, + PCI_DEVICE_ID_INTEL_TGP_GSPI5, + PCI_DEVICE_ID_INTEL_TGP_GSPI6, 0 }; diff --git a/src/soc/intel/common/block/sram/sram.c b/src/soc/intel/common/block/sram/sram.c index 720b736904..47ba28f755 100644 --- a/src/soc/intel/common/block/sram/sram.c +++ b/src/soc/intel/common/block/sram/sram.c @@ -51,6 +51,7 @@ static const unsigned short pci_device_ids[] = { PCI_DEVICE_ID_INTEL_GLK_SRAM, PCI_DEVICE_ID_INTEL_ICL_SRAM, PCI_DEVICE_ID_INTEL_CMP_SRAM, + PCI_DEVICE_ID_INTEL_TGL_SRAM, 0, }; diff --git a/src/soc/intel/common/block/systemagent/systemagent.c b/src/soc/intel/common/block/systemagent/systemagent.c index e03942fb30..7ad565d8e8 100644 --- a/src/soc/intel/common/block/systemagent/systemagent.c +++ b/src/soc/intel/common/block/systemagent/systemagent.c @@ -362,6 +362,8 @@ static const unsigned short systemagent_ids[] = { PCI_DEVICE_ID_INTEL_CML_S_10_2, PCI_DEVICE_ID_INTEL_CML_H, PCI_DEVICE_ID_INTEL_CML_H_8_2, + PCI_DEVICE_ID_INTEL_TGL_ID_U, + PCI_DEVICE_ID_INTEL_TGL_ID_Y, 0 }; diff --git a/src/soc/intel/common/block/uart/uart.c b/src/soc/intel/common/block/uart/uart.c index 364835dd0f..718eaca96b 100644 --- a/src/soc/intel/common/block/uart/uart.c +++ b/src/soc/intel/common/block/uart/uart.c @@ -275,6 +275,9 @@ static const unsigned short pci_device_ids[] = { PCI_DEVICE_ID_INTEL_CMP_UART0, PCI_DEVICE_ID_INTEL_CMP_UART1, PCI_DEVICE_ID_INTEL_CMP_UART2, + PCI_DEVICE_ID_INTEL_TGP_UART0, + PCI_DEVICE_ID_INTEL_TGP_UART1, + PCI_DEVICE_ID_INTEL_TGP_UART2, 0, }; diff --git a/src/soc/intel/common/block/xdci/xdci.c b/src/soc/intel/common/block/xdci/xdci.c index d42a1eca59..92f3b15da3 100644 --- a/src/soc/intel/common/block/xdci/xdci.c +++ b/src/soc/intel/common/block/xdci/xdci.c @@ -43,6 +43,7 @@ static const unsigned short pci_device_ids[] = { PCI_DEVICE_ID_INTEL_CNP_H_XDCI, PCI_DEVICE_ID_INTEL_ICP_LP_XDCI, PCI_DEVICE_ID_INTEL_CMP_LP_XDCI, + PCI_DEVICE_ID_INTEL_TGP_LP_XDCI, 0 }; diff --git a/src/soc/intel/common/block/xhci/xhci.c b/src/soc/intel/common/block/xhci/xhci.c index 293fd36464..5930e23081 100644 --- a/src/soc/intel/common/block/xhci/xhci.c +++ b/src/soc/intel/common/block/xhci/xhci.c @@ -131,6 +131,7 @@ static const unsigned short pci_device_ids[] = { PCI_DEVICE_ID_INTEL_CNP_H_XHCI, PCI_DEVICE_ID_INTEL_ICP_LP_XHCI, PCI_DEVICE_ID_INTEL_CMP_LP_XHCI, + PCI_DEVICE_ID_INTEL_TGP_LP_XHCI, 0 }; From ef63c32b5843c8b585804aa7ba37a3e7da2b7b1a Mon Sep 17 00:00:00 2001 From: Nico Huber Date: Mon, 4 Nov 2019 16:21:25 +0100 Subject: [PATCH 0026/1242] arch/riscv: Don't link `stages.c` into ramstage It's superseded by `ramstage.S`. Change-Id: I81648da2f2af3ad73b3b51471c6fa2daac0540b1 Signed-off-by: Nico Huber Reviewed-on: https://review.coreboot.org/c/coreboot/+/36610 Reviewed-by: Paul Menzel Reviewed-by: Arthur Heymans Tested-by: build bot (Jenkins) --- src/arch/riscv/Makefile.inc | 1 - 1 file changed, 1 deletion(-) diff --git a/src/arch/riscv/Makefile.inc b/src/arch/riscv/Makefile.inc index 0039fab180..16f160e8db 100644 --- a/src/arch/riscv/Makefile.inc +++ b/src/arch/riscv/Makefile.inc @@ -140,7 +140,6 @@ ramstage-y += fp_asm.S ramstage-y += misaligned.c ramstage-y += sbi.c ramstage-y += virtual_memory.c -ramstage-y += stages.c ramstage-y += misc.c ramstage-y += smp.c ramstage-y += boot.c From 007af4251fe83326d581d158910ecff12059dbfe Mon Sep 17 00:00:00 2001 From: Elyes HAOUAS Date: Sun, 3 Nov 2019 14:31:35 +0100 Subject: [PATCH 0027/1242] superio/*/*/acpi: Improve the readability of the IndexField Change-Id: I64fdcbcbbd54334c1c551bc1346c6000ea82c97d Signed-off-by: Elyes HAOUAS Reviewed-on: https://review.coreboot.org/c/coreboot/+/36598 Tested-by: build bot (Jenkins) Reviewed-by: Felix Held --- src/superio/fintek/f81803a/acpi/superio.asl | 4 ++-- src/superio/ite/it8720f/acpi/superio.asl | 2 +- src/superio/ite/it8721f/acpi/superio.asl | 2 +- src/superio/ite/it8783ef/acpi/superio.asl | 2 +- src/superio/ite/it8786e/acpi/superio.asl | 2 +- src/superio/nuvoton/nct5539d/acpi/superio.asl | 2 +- src/superio/nuvoton/nct6776/acpi/superio.asl | 2 +- src/superio/nuvoton/npcd378/acpi/superio.asl | 2 +- src/superio/smsc/sch5147/acpi/superio.asl | 2 +- src/superio/winbond/w83627dhg/acpi/superio.asl | 2 +- src/superio/winbond/w83627hf/acpi/superio.asl | 6 +++--- 11 files changed, 14 insertions(+), 14 deletions(-) diff --git a/src/superio/fintek/f81803a/acpi/superio.asl b/src/superio/fintek/f81803a/acpi/superio.asl index ae8e6dc242..3112a4ba5a 100644 --- a/src/superio/fintek/f81803a/acpi/superio.asl +++ b/src/superio/fintek/f81803a/acpi/superio.asl @@ -38,7 +38,7 @@ * F81803A_SHOW_UARTA If defined, UARTA will be exposed. * F81803A_SHOW_UARTB If defined, UARTB will be exposed. * F81803A_SHOW_HWMON If defined, the hardware monitor will be exposed. - * F81803A_SHOW_PME If defined, the PME/EARP/ACPI will be exposed. + * F81803A_SHOW_PME If defined, the PME/EARP/ACPI will be exposed. * * Known issue: * Do not enable UARTA and UARTB simultaneously, Linux boot will crash. @@ -66,7 +66,7 @@ Device(SUPERIO_DEV) { PNP_ADDR_REG, 8, PNP_DATA_REG, 8 } - IndexField (ADDR, DATA, ByteAcc, NoLock, Preserve) + IndexField (PNP_ADDR_REG, PNP_DATA_REG, ByteAcc, NoLock, Preserve) { Offset (0x07), PNP_LOGICAL_DEVICE, 8, /* Logical device selector */ diff --git a/src/superio/ite/it8720f/acpi/superio.asl b/src/superio/ite/it8720f/acpi/superio.asl index 1e94655753..1c793e2ec9 100644 --- a/src/superio/ite/it8720f/acpi/superio.asl +++ b/src/superio/ite/it8720f/acpi/superio.asl @@ -66,7 +66,7 @@ Device(SUPERIO_DEV) { PNP_ADDR_REG, 8, PNP_DATA_REG, 8 } - IndexField (ADDR, DATA, ByteAcc, NoLock, Preserve) + IndexField (PNP_ADDR_REG, PNP_DATA_REG, ByteAcc, NoLock, Preserve) { Offset (0x02), CONFIGURE_CONTROL, 8, /* Global configure control */ diff --git a/src/superio/ite/it8721f/acpi/superio.asl b/src/superio/ite/it8721f/acpi/superio.asl index c680f7e69c..4c54a4a6e0 100644 --- a/src/superio/ite/it8721f/acpi/superio.asl +++ b/src/superio/ite/it8721f/acpi/superio.asl @@ -66,7 +66,7 @@ Device(SUPERIO_DEV) { PNP_ADDR_REG, 8, PNP_DATA_REG, 8 } - IndexField (ADDR, DATA, ByteAcc, NoLock, Preserve) + IndexField (PNP_ADDR_REG, PNP_DATA_REG, ByteAcc, NoLock, Preserve) { Offset (0x02), CONFIGURE_CONTROL, 8, /* Global configure control */ diff --git a/src/superio/ite/it8783ef/acpi/superio.asl b/src/superio/ite/it8783ef/acpi/superio.asl index d7a320e15b..ed30a810c1 100644 --- a/src/superio/ite/it8783ef/acpi/superio.asl +++ b/src/superio/ite/it8783ef/acpi/superio.asl @@ -71,7 +71,7 @@ Device(SUPERIO_DEV) { PNP_ADDR_REG, 8, PNP_DATA_REG, 8 } - IndexField (ADDR, DATA, ByteAcc, NoLock, Preserve) + IndexField (PNP_ADDR_REG, PNP_DATA_REG, ByteAcc, NoLock, Preserve) { Offset (0x02), CONFIGURE_CONTROL, 8, /* Global configure control */ diff --git a/src/superio/ite/it8786e/acpi/superio.asl b/src/superio/ite/it8786e/acpi/superio.asl index f860da643b..8ea0df1114 100644 --- a/src/superio/ite/it8786e/acpi/superio.asl +++ b/src/superio/ite/it8786e/acpi/superio.asl @@ -70,7 +70,7 @@ Device (SUPERIO_DEV) { PNP_ADDR_REG, 8, PNP_DATA_REG, 8 } - IndexField (ADDR, DATA, ByteAcc, NoLock, Preserve) + IndexField (PNP_ADDR_REG, PNP_DATA_REG, ByteAcc, NoLock, Preserve) { Offset (0x02), CONFIGURE_CONTROL, 8, /* Global configure control */ diff --git a/src/superio/nuvoton/nct5539d/acpi/superio.asl b/src/superio/nuvoton/nct5539d/acpi/superio.asl index e259b0146d..ce43a77c54 100644 --- a/src/superio/nuvoton/nct5539d/acpi/superio.asl +++ b/src/superio/nuvoton/nct5539d/acpi/superio.asl @@ -57,7 +57,7 @@ Device(SUPERIO_DEV) { PNP_ADDR_REG, 8, PNP_DATA_REG, 8, } - IndexField (ADDR, DATA, ByteAcc, NoLock, Preserve) + IndexField (PNP_ADDR_REG, PNP_DATA_REG, ByteAcc, NoLock, Preserve) { Offset (0x07), PNP_LOGICAL_DEVICE, 8, /* Logical device selector */ diff --git a/src/superio/nuvoton/nct6776/acpi/superio.asl b/src/superio/nuvoton/nct6776/acpi/superio.asl index abd5562e39..f6aed57dba 100644 --- a/src/superio/nuvoton/nct6776/acpi/superio.asl +++ b/src/superio/nuvoton/nct6776/acpi/superio.asl @@ -58,7 +58,7 @@ Device(SUPERIO_DEV) { PNP_ADDR_REG, 8, PNP_DATA_REG, 8, } - IndexField (ADDR, DATA, ByteAcc, NoLock, Preserve) + IndexField (PNP_ADDR_REG, PNP_DATA_REG, ByteAcc, NoLock, Preserve) { Offset (0x07), PNP_LOGICAL_DEVICE, 8, /* Logical device selector */ diff --git a/src/superio/nuvoton/npcd378/acpi/superio.asl b/src/superio/nuvoton/npcd378/acpi/superio.asl index a4813e334c..231488053c 100644 --- a/src/superio/nuvoton/npcd378/acpi/superio.asl +++ b/src/superio/nuvoton/npcd378/acpi/superio.asl @@ -47,7 +47,7 @@ Device(SUPERIO_DEV) { PNP_ADDR_REG, 8, PNP_DATA_REG, 8, } - IndexField (ADDR, DATA, ByteAcc, NoLock, Preserve) + IndexField (PNP_ADDR_REG, PNP_DATA_REG, ByteAcc, NoLock, Preserve) { Offset (0x07), PNP_LOGICAL_DEVICE, 8, /* Logical device selector */ diff --git a/src/superio/smsc/sch5147/acpi/superio.asl b/src/superio/smsc/sch5147/acpi/superio.asl index fb49743d63..6314d81cd4 100644 --- a/src/superio/smsc/sch5147/acpi/superio.asl +++ b/src/superio/smsc/sch5147/acpi/superio.asl @@ -57,7 +57,7 @@ Device(SUPERIO_DEV) { PNP_ADDR_REG, 8, PNP_DATA_REG, 8 } - IndexField (ADDR, DATA, ByteAcc, NoLock, Preserve) + IndexField (PNP_ADDR_REG, PNP_DATA_REG, ByteAcc, NoLock, Preserve) { Offset (0x07), PNP_LOGICAL_DEVICE, 8, /* Logical device selector */ diff --git a/src/superio/winbond/w83627dhg/acpi/superio.asl b/src/superio/winbond/w83627dhg/acpi/superio.asl index 301ee94230..e1f2e383d8 100644 --- a/src/superio/winbond/w83627dhg/acpi/superio.asl +++ b/src/superio/winbond/w83627dhg/acpi/superio.asl @@ -65,7 +65,7 @@ Device(SUPERIO_DEV) { PNP_ADDR_REG, 8, PNP_DATA_REG, 8 } - IndexField (ADDR, DATA, ByteAcc, NoLock, Preserve) + IndexField (PNP_ADDR_REG, PNP_DATA_REG, ByteAcc, NoLock, Preserve) { Offset (0x07), PNP_LOGICAL_DEVICE, 8, /* Logical device selector */ diff --git a/src/superio/winbond/w83627hf/acpi/superio.asl b/src/superio/winbond/w83627hf/acpi/superio.asl index ef4504c94e..87c13ac9a8 100644 --- a/src/superio/winbond/w83627hf/acpi/superio.asl +++ b/src/superio/winbond/w83627hf/acpi/superio.asl @@ -67,10 +67,10 @@ Device(SIO) { OperationRegion (CREG, SystemIO, 0x2E, 0x02) Field (CREG, ByteAcc, NoLock, Preserve) { - ADDR, 8, - DATA, 8 + PNP_ADDR_REG, 8, + PNP_DATA_REG, 8 } - IndexField (ADDR, DATA, ByteAcc, NoLock, Preserve) + IndexField (PNP_ADDR_REG, PNP_DATA_REG, ByteAcc, NoLock, Preserve) { Offset (0x02), RST, 1, /* Soft reset */ From 6a657c26462f9c5896e504cd4027e58bc6db7d86 Mon Sep 17 00:00:00 2001 From: Sumeet Pawnikar Date: Mon, 4 Nov 2019 14:31:06 +0530 Subject: [PATCH 0028/1242] mb/google/hatch/variants/helios: Update TSR3 sensor thresholds Update thermal threshold settings for TSR3 sensor. There is an issue fan is always running, even during system idle state. This change fixes this issue and fan starts only when it breaches the temperature threshold. BRANCH=None BUG=b:143861559 TEST=Built and tested on Helios system Change-Id: Ia417f8c51442005cc8c2251c188cebc197e0a773 Signed-off-by: Sumeet Pawnikar Reviewed-on: https://review.coreboot.org/c/coreboot/+/36609 Reviewed-by: Duncan Laurie Reviewed-by: Shelley Chen Reviewed-by: Furquan Shaikh Tested-by: build bot (Jenkins) --- .../helios/include/variant/acpi/dptf.asl | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/src/mainboard/google/hatch/variants/helios/include/variant/acpi/dptf.asl b/src/mainboard/google/hatch/variants/helios/include/variant/acpi/dptf.asl index 90943529b6..20a61d7df4 100644 --- a/src/mainboard/google/hatch/variants/helios/include/variant/acpi/dptf.asl +++ b/src/mainboard/google/hatch/variants/helios/include/variant/acpi/dptf.asl @@ -36,14 +36,14 @@ #define DPTF_TSR3_SENSOR_ID 3 #define DPTF_TSR3_SENSOR_NAME "CPU" -#define DPTF_TSR3_PASSIVE 85 -#define DPTF_TSR3_CRITICAL 100 -#define DPTF_TSR3_ACTIVE_AC0 0 -#define DPTF_TSR3_ACTIVE_AC1 0 -#define DPTF_TSR3_ACTIVE_AC2 0 -#define DPTF_TSR3_ACTIVE_AC3 0 -#define DPTF_TSR3_ACTIVE_AC4 0 -#define DPTF_TSR3_ACTIVE_AC5 0 +#define DPTF_TSR3_PASSIVE 90 +#define DPTF_TSR3_CRITICAL 105 +#define DPTF_TSR3_ACTIVE_AC0 87 +#define DPTF_TSR3_ACTIVE_AC1 85 +#define DPTF_TSR3_ACTIVE_AC2 83 +#define DPTF_TSR3_ACTIVE_AC3 80 +#define DPTF_TSR3_ACTIVE_AC4 78 +#define DPTF_TSR3_ACTIVE_AC5 75 #define DPTF_ENABLE_CHARGER #define DPTF_ENABLE_FAN_CONTROL From fb2a9d5ed86d9d5e5d7a8b20e71df0deba3bc5c0 Mon Sep 17 00:00:00 2001 From: Subrata Banik Date: Tue, 5 Nov 2019 18:30:05 +0530 Subject: [PATCH 0029/1242] soc/intel/icelake: Set FSP_TEMP_RAM_STACK unconditionally Icelake default selects PLATFORM_USES_FSP2_1 which means stack will be shared between FSP and coreboot (CONFIG_FSP_USES_CB_STACK) hence no need to have any other guard to assign FSP_TEMP_RAM_SIZE. Change-Id: Idbe393f7a63ad10f1ad3c9e7248593cf8eb115d9 Signed-off-by: Subrata Banik Reviewed-on: https://review.coreboot.org/c/coreboot/+/36628 Reviewed-by: Furquan Shaikh Reviewed-by: Arthur Heymans Tested-by: build bot (Jenkins) --- src/soc/intel/icelake/Kconfig | 1 - 1 file changed, 1 deletion(-) diff --git a/src/soc/intel/icelake/Kconfig b/src/soc/intel/icelake/Kconfig index a04993ddf2..71c7f8355c 100644 --- a/src/soc/intel/icelake/Kconfig +++ b/src/soc/intel/icelake/Kconfig @@ -78,7 +78,6 @@ config DCACHE_BSP_STACK_SIZE config FSP_TEMP_RAM_SIZE hex - depends on FSP_USES_CB_STACK default 0x10000 help The amount of anticipated heap usage in CAR by FSP. From b4741616ea3dc1f0b281376f9c5e0ffe75a1b15b Mon Sep 17 00:00:00 2001 From: Edward O'Callaghan Date: Wed, 23 Oct 2019 00:28:39 +1100 Subject: [PATCH 0030/1242] mainboard/google: Rework Hatch so that SPD in CBFS is optional All Hatch variants so far embed static SPD data encoded within the firmware image. However we wish the flexibility for romstage implementations that allow for reading the SPD data dynamically over SMBus. BRANCH=none BUG=b:143134702 TEST=./util/abuild/abuild -p none -t google/hatch -x -a Change-Id: Ie1637d08cdd85bc8d7c3b6f2d6f386d0e0c6589b Signed-off-by: Edward O'Callaghan Reviewed-on: https://review.coreboot.org/c/coreboot/+/36250 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh Reviewed-by: Aaron Durbin --- src/mainboard/google/hatch/Kconfig | 4 ++++ src/mainboard/google/hatch/Makefile.inc | 4 ++-- .../google/hatch/{romstage.c => romstage_spd_cbfs.c} | 0 3 files changed, 6 insertions(+), 2 deletions(-) rename src/mainboard/google/hatch/{romstage.c => romstage_spd_cbfs.c} (100%) diff --git a/src/mainboard/google/hatch/Kconfig b/src/mainboard/google/hatch/Kconfig index 004cc28633..219be2265a 100644 --- a/src/mainboard/google/hatch/Kconfig +++ b/src/mainboard/google/hatch/Kconfig @@ -58,6 +58,10 @@ config DIMM_SPD_SIZE int default 512 +config ROMSTAGE_SPD_CBFS + bool + default y + config DRIVER_TPM_SPI_BUS default 0x1 diff --git a/src/mainboard/google/hatch/Makefile.inc b/src/mainboard/google/hatch/Makefile.inc index 01a1eb85dd..a226bd623c 100644 --- a/src/mainboard/google/hatch/Makefile.inc +++ b/src/mainboard/google/hatch/Makefile.inc @@ -20,7 +20,7 @@ ramstage-y += ramstage.c ramstage-$(CONFIG_CHROMEOS) += chromeos.c ramstage-$(CONFIG_EC_GOOGLE_CHROMEEC) += ec.c -romstage-y += romstage.c +romstage-$(CONFIG_ROMSTAGE_SPD_CBFS) += romstage_spd_cbfs.c romstage-$(CONFIG_CHROMEOS) += chromeos.c verstage-$(CONFIG_CHROMEOS) += chromeos.c @@ -33,4 +33,4 @@ VARIANT_DIR:=$(call strip_quotes,$(CONFIG_VARIANT_DIR)) subdirs-y += variants/$(VARIANT_DIR) CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/variants/$(VARIANT_DIR)/include -subdirs-y += spd +subdirs-$(CONFIG_ROMSTAGE_SPD_CBFS) += spd diff --git a/src/mainboard/google/hatch/romstage.c b/src/mainboard/google/hatch/romstage_spd_cbfs.c similarity index 100% rename from src/mainboard/google/hatch/romstage.c rename to src/mainboard/google/hatch/romstage_spd_cbfs.c From f8251b98605264f3e353fc7b6146f686ec5295cc Mon Sep 17 00:00:00 2001 From: Patrick Rudolph Date: Fri, 13 Sep 2019 12:56:14 +0200 Subject: [PATCH 0031/1242] mb/emulation/qemu: Add VBOOT support Add VBOOT support for testing purposes. Add a 16 MiB FMAP containing RO + RW_A. Tested on qemu. Change-Id: I4039d77de44ade68c7bc1f8b4b0aa21387c50f8a Signed-off-by: Patrick Rudolph Reviewed-on: https://review.coreboot.org/c/coreboot/+/35400 Tested-by: build bot (Jenkins) Reviewed-by: Arthur Heymans --- src/mainboard/emulation/qemu-i440fx/Kconfig | 25 ++++++++++++++++++- .../emulation/qemu-i440fx/cmos.layout | 6 ++++- .../emulation/qemu-i440fx/vboot-rwa-16M.fmd | 19 ++++++++++++++ src/mainboard/emulation/qemu-q35/Kconfig | 25 ++++++++++++++++++- src/mainboard/emulation/qemu-q35/cmos.layout | 6 ++++- .../emulation/qemu-q35/vboot-rwa-16M.fmd | 19 ++++++++++++++ 6 files changed, 96 insertions(+), 4 deletions(-) create mode 100644 src/mainboard/emulation/qemu-i440fx/vboot-rwa-16M.fmd create mode 100644 src/mainboard/emulation/qemu-q35/vboot-rwa-16M.fmd diff --git a/src/mainboard/emulation/qemu-i440fx/Kconfig b/src/mainboard/emulation/qemu-i440fx/Kconfig index 3c5e3252f8..05246b6d6d 100644 --- a/src/mainboard/emulation/qemu-i440fx/Kconfig +++ b/src/mainboard/emulation/qemu-i440fx/Kconfig @@ -9,10 +9,33 @@ config BOARD_SPECIFIC_OPTIONS select HAVE_CMOS_DEFAULT select HAVE_PIRQ_TABLE select HAVE_ACPI_TABLES - select BOARD_ROMSIZE_KB_256 + select BOARD_ROMSIZE_KB_256 if !VBOOT + select BOARD_ROMSIZE_KB_16384 if VBOOT select MAINBOARD_HAS_NATIVE_VGA_INIT select MAINBOARD_FORCE_NATIVE_VGA_INIT +config VBOOT + select VBOOT_MUST_REQUEST_DISPLAY + select VBOOT_STARTS_IN_BOOTBLOCK + select VBOOT_SEPARATE_VERSTAGE + select VBOOT_VBNV_CMOS + select VBOOT_NO_BOARD_SUPPORT + select GBB_FLAG_DISABLE_LID_SHUTDOWN + select GBB_FLAG_DISABLE_PD_SOFTWARE_SYNC + select GBB_FLAG_DISABLE_EC_SOFTWARE_SYNC + select GBB_FLAG_DISABLE_FWMP + +config VBOOT_SLOTS_RW_A + default y + +config FMDFILE + string + default "src/mainboard/$(CONFIG_MAINBOARD_DIR)/vboot-rwa-16M.fmd" if VBOOT_SLOTS_RW_A + +config VBOOT_VBNV_OFFSET + hex + default 0x2c + config MAINBOARD_DIR string default emulation/qemu-i440fx diff --git a/src/mainboard/emulation/qemu-i440fx/cmos.layout b/src/mainboard/emulation/qemu-i440fx/cmos.layout index b238a379d8..247a6a08a5 100644 --- a/src/mainboard/emulation/qemu-i440fx/cmos.layout +++ b/src/mainboard/emulation/qemu-i440fx/cmos.layout @@ -7,6 +7,10 @@ entries 400 1 e 1 power_on_after_fail 412 4 e 6 debug_level 456 1 e 1 ECC_memory + +# VBOOT +464 128 r 0 vbnv + 1008 16 h 0 check_sum enumerations @@ -25,4 +29,4 @@ enumerations checksums -checksum 392 1007 1008 +checksum 392 463 1008 diff --git a/src/mainboard/emulation/qemu-i440fx/vboot-rwa-16M.fmd b/src/mainboard/emulation/qemu-i440fx/vboot-rwa-16M.fmd new file mode 100644 index 0000000000..0d2c9da297 --- /dev/null +++ b/src/mainboard/emulation/qemu-i440fx/vboot-rwa-16M.fmd @@ -0,0 +1,19 @@ +FLASH@0xff000000 0x1000000 { + SI_BIOS 0x1000000 { + RW_SECTION_A 0x7c0000 { + VBLOCK_A 0x10000 + FW_MAIN_A(CBFS) 0x74ffc0 + RW_FWID_A 0x40 + } + RW_VPD(PRESERVE) 0x1000 + + WP_RO { + FMAP 0x800 + RO_FRID 0x40 + RO_PADDING 0x7c0 + RO_VPD(PRESERVE) 0x1000 + GBB 0x1e000 + COREBOOT(CBFS) + } + } +} diff --git a/src/mainboard/emulation/qemu-q35/Kconfig b/src/mainboard/emulation/qemu-q35/Kconfig index bfa38ed84e..a86e844044 100644 --- a/src/mainboard/emulation/qemu-q35/Kconfig +++ b/src/mainboard/emulation/qemu-q35/Kconfig @@ -8,10 +8,33 @@ config BOARD_SPECIFIC_OPTIONS select HAVE_OPTION_TABLE # select HAVE_PIRQ_TABLE select HAVE_ACPI_TABLES - select BOARD_ROMSIZE_KB_2048 + select BOARD_ROMSIZE_KB_2048 if !VBOOT + select BOARD_ROMSIZE_KB_16384 if VBOOT select MAINBOARD_HAS_NATIVE_VGA_INIT select MAINBOARD_FORCE_NATIVE_VGA_INIT +config VBOOT + select VBOOT_MUST_REQUEST_DISPLAY + select VBOOT_STARTS_IN_BOOTBLOCK + select VBOOT_SEPARATE_VERSTAGE + select VBOOT_VBNV_CMOS + select VBOOT_NO_BOARD_SUPPORT + select GBB_FLAG_DISABLE_LID_SHUTDOWN + select GBB_FLAG_DISABLE_PD_SOFTWARE_SYNC + select GBB_FLAG_DISABLE_EC_SOFTWARE_SYNC + select GBB_FLAG_DISABLE_FWMP + +config FMDFILE + string + default "src/mainboard/$(CONFIG_MAINBOARD_DIR)/vboot-rwa-16M.fmd" if VBOOT_SLOTS_RW_A + +config VBOOT_SLOTS_RW_A + default y + +config VBOOT_VBNV_OFFSET + hex + default 0x2c + config MAINBOARD_DIR string default emulation/qemu-q35 diff --git a/src/mainboard/emulation/qemu-q35/cmos.layout b/src/mainboard/emulation/qemu-q35/cmos.layout index b238a379d8..247a6a08a5 100644 --- a/src/mainboard/emulation/qemu-q35/cmos.layout +++ b/src/mainboard/emulation/qemu-q35/cmos.layout @@ -7,6 +7,10 @@ entries 400 1 e 1 power_on_after_fail 412 4 e 6 debug_level 456 1 e 1 ECC_memory + +# VBOOT +464 128 r 0 vbnv + 1008 16 h 0 check_sum enumerations @@ -25,4 +29,4 @@ enumerations checksums -checksum 392 1007 1008 +checksum 392 463 1008 diff --git a/src/mainboard/emulation/qemu-q35/vboot-rwa-16M.fmd b/src/mainboard/emulation/qemu-q35/vboot-rwa-16M.fmd new file mode 100644 index 0000000000..0d2c9da297 --- /dev/null +++ b/src/mainboard/emulation/qemu-q35/vboot-rwa-16M.fmd @@ -0,0 +1,19 @@ +FLASH@0xff000000 0x1000000 { + SI_BIOS 0x1000000 { + RW_SECTION_A 0x7c0000 { + VBLOCK_A 0x10000 + FW_MAIN_A(CBFS) 0x74ffc0 + RW_FWID_A 0x40 + } + RW_VPD(PRESERVE) 0x1000 + + WP_RO { + FMAP 0x800 + RO_FRID 0x40 + RO_PADDING 0x7c0 + RO_VPD(PRESERVE) 0x1000 + GBB 0x1e000 + COREBOOT(CBFS) + } + } +} From 214661e00c15f4005fc85ba9bca859fab41ee36c Mon Sep 17 00:00:00 2001 From: Arthur Heymans Date: Mon, 4 Nov 2019 10:16:42 +0100 Subject: [PATCH 0032/1242] security/vboot/Kconfig: Remove unused symbols Change-Id: I417a2ff45b4a8f5bc800459a64f1c5a861fcd3d5 Signed-off-by: Arthur Heymans Reviewed-on: https://review.coreboot.org/c/coreboot/+/36605 Tested-by: build bot (Jenkins) Reviewed-by: HAOUAS Elyes --- src/mainboard/intel/galileo/Kconfig | 1 - src/security/vboot/Kconfig | 4 ---- 2 files changed, 5 deletions(-) diff --git a/src/mainboard/intel/galileo/Kconfig b/src/mainboard/intel/galileo/Kconfig index 37f88dd8f0..84f09c4f82 100644 --- a/src/mainboard/intel/galileo/Kconfig +++ b/src/mainboard/intel/galileo/Kconfig @@ -110,7 +110,6 @@ config VBOOT_WITH_CRYPTO_SHIELD select VBOOT_SEPARATE_VERSTAGE select VBOOT select VBOOT_STARTS_IN_BOOTBLOCK - select VBOOT_SOFT_REBOOT_WORKAROUND select VBOOT_VBNV_CMOS help Perform a verified boot using the TPM on the Crypto Shield board. diff --git a/src/security/vboot/Kconfig b/src/security/vboot/Kconfig index d6d74cac73..e3b8aa68e2 100644 --- a/src/security/vboot/Kconfig +++ b/src/security/vboot/Kconfig @@ -174,10 +174,6 @@ config VBOOT_HAS_REC_HASH_SPACE Set this option to indicate to vboot that recovery data hash space is present in TPM. -config VBOOT_SOFT_REBOOT_WORKAROUND - bool - default n - config VBOOT_LID_SWITCH bool default n From c01d0920bb75e0b2849c26421be0a3fac6bc6198 Mon Sep 17 00:00:00 2001 From: Nico Huber Date: Mon, 4 Nov 2019 16:32:01 +0100 Subject: [PATCH 0033/1242] arch/riscv: Rename `stages.c` to `romstage.c` It's only used for romstage and is incompatible to ramstages. The latter get `cbmem_top` passed as a third argument now. Also drop comments that don't apply to this file anymore. Change-Id: Ibabb022860f5d141ab35922f30e856da8473b529 Signed-off-by: Nico Huber Reviewed-on: https://review.coreboot.org/c/coreboot/+/36611 Tested-by: build bot (Jenkins) Reviewed-by: Arthur Heymans --- src/arch/riscv/Makefile.inc | 2 +- src/arch/riscv/{stages.c => romstage.c} | 9 --------- 2 files changed, 1 insertion(+), 10 deletions(-) rename src/arch/riscv/{stages.c => romstage.c} (73%) diff --git a/src/arch/riscv/Makefile.inc b/src/arch/riscv/Makefile.inc index 16f160e8db..003852324b 100644 --- a/src/arch/riscv/Makefile.inc +++ b/src/arch/riscv/Makefile.inc @@ -98,7 +98,7 @@ endif #CONFIG_ARCH_BOOTBLOCK_RISCV ifeq ($(CONFIG_ARCH_ROMSTAGE_RISCV),y) romstage-y += boot.c -romstage-y += stages.c +romstage-y += romstage.c romstage-y += misc.c romstage-$(ARCH_RISCV_PMP) += pmp.c romstage-y += smp.c diff --git a/src/arch/riscv/stages.c b/src/arch/riscv/romstage.c similarity index 73% rename from src/arch/riscv/stages.c rename to src/arch/riscv/romstage.c index 5b27508c47..d5f5a43ce1 100644 --- a/src/arch/riscv/stages.c +++ b/src/arch/riscv/romstage.c @@ -14,10 +14,6 @@ */ /* - * This file contains entry/exit functions for each stage during coreboot - * execution (bootblock entry and ramstage exit will depend on external - * loading). - * * Entry points must be placed at the location the previous stage jumps * to (the lowest address in the stage image). This is done by giving * stage_entry() its own section in .text and placing it first in the @@ -31,11 +27,6 @@ void stage_entry(int hart_id, void *fdt) { - /* - * Save the FDT pointer before entering ramstage, because mscratch - * might be overwritten in the trap handler, and there is code in - * ramstage that generates misaligned access faults. - */ HLS()->hart_id = hart_id; HLS()->fdt = fdt; smp_pause(CONFIG_RISCV_WORKING_HARTID); From 763eeecb30ed09cdfedbb811aacd19f24478afee Mon Sep 17 00:00:00 2001 From: Arthur Heymans Date: Sun, 3 Nov 2019 12:24:48 +0100 Subject: [PATCH 0034/1242] arch/riscv: Use FDT from calling argument when using FIT Only FIT payloads provide their own FDT. Change-Id: Id08a12ad7b72ad539e934a133acf2c4a5bcdf1f9 Signed-off-by: Arthur Heymans Reviewed-on: https://review.coreboot.org/c/coreboot/+/36599 Reviewed-by: Nico Huber Tested-by: build bot (Jenkins) --- src/arch/riscv/boot.c | 16 +++------------- 1 file changed, 3 insertions(+), 13 deletions(-) diff --git a/src/arch/riscv/boot.c b/src/arch/riscv/boot.c index 6a23b8a696..d3ae693376 100644 --- a/src/arch/riscv/boot.c +++ b/src/arch/riscv/boot.c @@ -38,20 +38,10 @@ static void do_arch_prog_run(struct arch_prog_run_args *args) { int hart_id; struct prog *prog = args->prog; - void *fdt = prog_entry_arg(prog); + void *fdt = HLS()->fdt; - /* - * Workaround selfboot putting the coreboot table into prog_entry_arg - */ - if (prog_cbfs_type(prog) == CBFS_TYPE_SELF) - fdt = HLS()->fdt; - - /* - * If prog_entry_arg is not set (e.g. by fit_payload), use fdt from HLS - * instead. - */ - if (fdt == NULL) - fdt = HLS()->fdt; + if (prog_cbfs_type(prog) == CBFS_TYPE_FIT) + fdt = prog_entry_arg(prog); if (ENV_RAMSTAGE && prog_type(prog) == PROG_PAYLOAD) { if (CONFIG(RISCV_OPENSBI)) From 51b1fc6e3929229e997fe16aa8f653bfcd112eeb Mon Sep 17 00:00:00 2001 From: Mathew King Date: Mon, 4 Nov 2019 12:29:41 -0700 Subject: [PATCH 0035/1242] mb/g/drallion: Consolidate 360 sensor board detection Create a single function to determine if the 360 sensor board is present on a device. BUG=b:143701965 TEST='emerge-drallion coreboot' Change-Id: I4100a9fdcfe6b7134fb238cb291cb5b0af4ec169 Signed-off-by: Mathew King Reviewed-on: https://review.coreboot.org/c/coreboot/+/36617 Tested-by: build bot (Jenkins) Reviewed-by: EricR Lai --- src/mainboard/google/drallion/variants/drallion/gpio.c | 9 ++------- .../drallion/variants/drallion/include/variant/variant.h | 9 +++++++++ src/mainboard/google/drallion/variants/drallion/sku.c | 6 ++---- 3 files changed, 13 insertions(+), 11 deletions(-) diff --git a/src/mainboard/google/drallion/variants/drallion/gpio.c b/src/mainboard/google/drallion/variants/drallion/gpio.c index 5657eeaae1..086dca0265 100644 --- a/src/mainboard/google/drallion/variants/drallion/gpio.c +++ b/src/mainboard/google/drallion/variants/drallion/gpio.c @@ -14,6 +14,7 @@ */ #include +#include #include #include #include @@ -274,17 +275,11 @@ const struct cros_gpio *variant_cros_gpios(size_t *num) return cros_gpios; } -static int is_ish_device_enabled(void) -{ - gpio_input(SENSOR_DET_360); - return gpio_get(SENSOR_DET_360) == 0; -} - void variant_mainboard_post_init_params(FSPM_UPD *mupd) { FSP_M_CONFIG *fsp_m_cfg = &mupd->FspmConfig; if (fsp_m_cfg->PchIshEnable) - fsp_m_cfg->PchIshEnable = is_ish_device_enabled(); + fsp_m_cfg->PchIshEnable = has_360_sensor_board(); /* * Disable memory channel by HW strap pin, HW default is enable diff --git a/src/mainboard/google/drallion/variants/drallion/include/variant/variant.h b/src/mainboard/google/drallion/variants/drallion/include/variant/variant.h index 508654faa5..bf08ec30dc 100644 --- a/src/mainboard/google/drallion/variants/drallion/include/variant/variant.h +++ b/src/mainboard/google/drallion/variants/drallion/include/variant/variant.h @@ -16,6 +16,9 @@ #ifndef VARIANT_H #define VARIANT_H +#include +#include + /* Need to update for Drallion with right SKU IDs*/ typedef struct { int id; @@ -36,4 +39,10 @@ const static sku_info skus[] = { /* Return memory SKU for the variant */ int variant_memory_sku(void); +/* Check if the device has a 360 sensor board present */ +static inline int has_360_sensor_board(void) +{ + return gpio_get(SENSOR_DET_360) == 0; +} + #endif diff --git a/src/mainboard/google/drallion/variants/drallion/sku.c b/src/mainboard/google/drallion/variants/drallion/sku.c index 72776299b0..736a14579a 100644 --- a/src/mainboard/google/drallion/variants/drallion/sku.c +++ b/src/mainboard/google/drallion/variants/drallion/sku.c @@ -14,15 +14,13 @@ */ #include -#include #include +#include #include -#include -#include static const uint32_t get_sku_index(void) { - return (gpio_get(SENSOR_DET_360) | (wilco_ec_signed_fw() << 1)); + return ((!has_360_sensor_board()) | (wilco_ec_signed_fw() << 1)); } uint32_t sku_id(void) From a0218958a046e102daabb297c2e9eb83cb244b1c Mon Sep 17 00:00:00 2001 From: Mathew King Date: Thu, 31 Oct 2019 11:55:25 -0600 Subject: [PATCH 0036/1242] mb/g/drallion: Override smbios enclosure type for drallion Drallion can be either a clamshell or convertible depending on the presence of the 360 sensor board. Set the smbios type 3 enclosure type to either CONVERTIBLE or LAPTOP accordingly. BUG=b:143701965 TEST='dmidecode -t 3' Type = Convertible with sensor board connected Type = Laptop with sensor board disconnected Change-Id: I766e9a4b22a490bc8252670a06504437e82f72d5 Signed-off-by: Mathew King Reviewed-on: https://review.coreboot.org/c/coreboot/+/36512 Reviewed-by: EricR Lai Tested-by: build bot (Jenkins) --- .../drallion/variants/drallion/Makefile.inc | 1 + .../drallion/variants/drallion/smbios.c | 24 +++++++++++++++++++ 2 files changed, 25 insertions(+) create mode 100644 src/mainboard/google/drallion/variants/drallion/smbios.c diff --git a/src/mainboard/google/drallion/variants/drallion/Makefile.inc b/src/mainboard/google/drallion/variants/drallion/Makefile.inc index ccbcb08da8..954c9d59cf 100644 --- a/src/mainboard/google/drallion/variants/drallion/Makefile.inc +++ b/src/mainboard/google/drallion/variants/drallion/Makefile.inc @@ -32,3 +32,4 @@ verstage-y += gpio.c romstage-y += memory.c ramstage-y += sku.c +ramstage-y += smbios.c diff --git a/src/mainboard/google/drallion/variants/drallion/smbios.c b/src/mainboard/google/drallion/variants/drallion/smbios.c new file mode 100644 index 0000000000..45bd31d7b0 --- /dev/null +++ b/src/mainboard/google/drallion/variants/drallion/smbios.c @@ -0,0 +1,24 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2019 Google LLC + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the + * GNU General Public License for more details. + */ + +#include +#include + +smbios_enclosure_type smbios_mainboard_enclosure_type(void) +{ + return has_360_sensor_board() ? + SMBIOS_ENCLOSURE_CONVERTIBLE : + SMBIOS_ENCLOSURE_LAPTOP; +} From 4e39c824e07f192c35afa88dcceee863528dbd32 Mon Sep 17 00:00:00 2001 From: Xiang Wang Date: Tue, 5 Nov 2019 12:00:39 +0800 Subject: [PATCH 0037/1242] lib: add calculate crc byte by byte Change-Id: I5cab1f90452b08a464ad7a2d7e75d97187452992 Signed-off-by: Xiang Wang Reviewed-on: https://review.coreboot.org/c/coreboot/+/36624 Tested-by: build bot (Jenkins) Reviewed-by: Julius Werner Reviewed-by: Patrick Georgi --- src/include/crc_byte.h | 40 ++++++++++++++++++++++++++++++++++++++++ src/lib/Makefile.inc | 8 ++++++++ src/lib/crc_byte.c | 38 ++++++++++++++++++++++++++++++++++++++ 3 files changed, 86 insertions(+) create mode 100644 src/include/crc_byte.h create mode 100644 src/lib/crc_byte.c diff --git a/src/include/crc_byte.h b/src/include/crc_byte.h new file mode 100644 index 0000000000..9315277d23 --- /dev/null +++ b/src/include/crc_byte.h @@ -0,0 +1,40 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 HardenedLinux + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef CRC_BYTE_H +#define CRC_BYTE_H + +#include + +/* This function is used to calculate crc7 byte by byte, with polynomial + * x^7 + x^3 + 1. + * + * prev_crc: old crc result (0 for first) + * data: new byte + * return value: new crc result + */ +uint8_t crc7_byte(uint8_t prev_crc, uint8_t data); + +/* This function is used to calculate crc16 byte by byte, with polynomial + * x^16 + x^12 + x^5 + 1. + * + * prev_crc: old crc result (0 for first) + * data: new byte + * return value: new crc result + */ +uint16_t crc16_byte(uint16_t prev_crc, uint8_t data); + + +#endif /* CRC_BYTE_H */ diff --git a/src/lib/Makefile.inc b/src/lib/Makefile.inc index da7b4bbdbc..3b7d57c76a 100644 --- a/src/lib/Makefile.inc +++ b/src/lib/Makefile.inc @@ -249,6 +249,14 @@ postcar-y += string.c ramstage-y += string.c smm-y += string.c +decompressor-y += crc_byte.c +bootblock-y += crc_byte.c +verstage-y += crc_byte.c +romstage-y += crc_byte.c +postcar-y += crc_byte.c +ramstage-y += crc_byte.c +smm-y += crc_byte.c + postcar-y += bootmode.c postcar-y += boot_device.c postcar-y += cbfs.c diff --git a/src/lib/crc_byte.c b/src/lib/crc_byte.c new file mode 100644 index 0000000000..0ac006363a --- /dev/null +++ b/src/lib/crc_byte.c @@ -0,0 +1,38 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 HardenedLinux + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include + +uint8_t crc7_byte(uint8_t prev_crc, uint8_t data) +{ + const uint8_t g = 0x89; + prev_crc ^= data; + for (int i = 0; i < 8; i++) { + if (prev_crc & 0x80) + prev_crc ^= g; + prev_crc <<= 1; + } + return prev_crc; +} + +uint16_t crc16_byte(uint16_t prev_crc, uint8_t data) +{ + prev_crc = (uint8_t)(prev_crc >> 8)|(prev_crc << 8); + prev_crc ^= data; + prev_crc ^= (uint8_t)(prev_crc & 0xff) >> 4; + prev_crc ^= (prev_crc << 8) << 4; + prev_crc ^= ((prev_crc & 0xff) << 4) << 1; + return prev_crc; +} From 55f01326cc04f8366a451bcaa4308531281a32d4 Mon Sep 17 00:00:00 2001 From: Arthur Heymans Date: Tue, 5 Nov 2019 12:06:59 +0100 Subject: [PATCH 0038/1242] util/lint/kconfig_lint: Handle glob prefix and suffix Change-Id: I9067a95ff171d6da58583b3d4f15596b4584d937 Signed-off-by: Arthur Heymans Reviewed-on: https://review.coreboot.org/c/coreboot/+/36626 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber Reviewed-by: Martin Roth --- util/lint/kconfig_lint | 9 ++++++--- 1 file changed, 6 insertions(+), 3 deletions(-) diff --git a/util/lint/kconfig_lint b/util/lint/kconfig_lint index 47f04941f2..1545c8299b 100755 --- a/util/lint/kconfig_lint +++ b/util/lint/kconfig_lint @@ -1213,9 +1213,11 @@ sub load_kconfig_file { my @dir_file_data; #recursively handle coreboot's new source glob operator - if ( $input_file =~ /^(.*?)\/\*\/(.*)$/ ) { + if ( $input_file =~ /^(.*?)\/(\w*)\*(\w*)\/(.*)$/ ) { my $dir_prefix = $1; - my $dir_suffix = $2; + my $dir_glob_prefix = $2; + my $dir_glob_suffix = $3; + my $dir_suffix = $4; if ( -d "$dir_prefix" ) { opendir( D, "$dir_prefix" ) || die "Can't open directory '$dir_prefix'\n"; @@ -1225,7 +1227,8 @@ sub load_kconfig_file { while ( my $directory = shift @dirlist ) { #ignore non-directory files - if ( ( -d "$dir_prefix/$directory" ) && !( $directory =~ /^\..*/ ) ) { + if ( ( -d "$dir_prefix/$directory" ) && !( $directory =~ /^\..*/ ) + && ( $directory =~ /\Q$dir_glob_prefix\E.*\Q$dir_glob_suffix\E/ ) ) { push @dir_file_data, load_kconfig_file( "$dir_prefix/$directory/$dir_suffix", $input_file, $loadline, 1, $loadfile, $loadline ); From aae81906b940c84b53944ec48d08074d8a0d153d Mon Sep 17 00:00:00 2001 From: Arthur Heymans Date: Mon, 4 Nov 2019 21:50:21 +0100 Subject: [PATCH 0039/1242] Kconfig: Organize debugging options per file extensions Change-Id: Ia4553fb4cd95d2f1fa86eecbf382e6e6dec52b92 Signed-off-by: Arthur Heymans Reviewed-on: https://review.coreboot.org/c/coreboot/+/36616 Reviewed-by: Nico Huber Tested-by: build bot (Jenkins) --- src/Kconfig | 2 +- src/cpu/x86/{Kconfig.debug => Kconfig.debug_cpu} | 0 2 files changed, 1 insertion(+), 1 deletion(-) rename src/cpu/x86/{Kconfig.debug => Kconfig.debug_cpu} (100%) diff --git a/src/Kconfig b/src/Kconfig index 0d56291de4..2b5f05ed1b 100644 --- a/src/Kconfig +++ b/src/Kconfig @@ -738,7 +738,7 @@ source "payloads/Kconfig" menu "Debugging" comment "CPU Debug Settings" -source "src/cpu/*/Kconfig.debug" +source "src/cpu/*/Kconfig.debug_cpu" comment "General Debug Settings" diff --git a/src/cpu/x86/Kconfig.debug b/src/cpu/x86/Kconfig.debug_cpu similarity index 100% rename from src/cpu/x86/Kconfig.debug rename to src/cpu/x86/Kconfig.debug_cpu From 71bd7e439fed00c73712be4f9522f412e3ab8559 Mon Sep 17 00:00:00 2001 From: Arthur Heymans Date: Sun, 20 Oct 2019 14:20:53 +0200 Subject: [PATCH 0040/1242] drivers/intel/fsp2_0: Move Debug options to "Debugging" Change-Id: I8e07c8186baf3d8e91b77c5afb731d26a1abfbaf Signed-off-by: Arthur Heymans Reviewed-on: https://review.coreboot.org/c/coreboot/+/36165 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber --- src/Kconfig | 3 ++ src/drivers/intel/fsp2_0/Kconfig | 38 ------------------- src/drivers/intel/fsp2_0/Kconfig.debug_blob | 41 +++++++++++++++++++++ 3 files changed, 44 insertions(+), 38 deletions(-) create mode 100644 src/drivers/intel/fsp2_0/Kconfig.debug_blob diff --git a/src/Kconfig b/src/Kconfig index 2b5f05ed1b..4002d43cee 100644 --- a/src/Kconfig +++ b/src/Kconfig @@ -740,6 +740,9 @@ menu "Debugging" comment "CPU Debug Settings" source "src/cpu/*/Kconfig.debug_cpu" +comment "BLOB Debug Settings" +source "src/drivers/intel/fsp*/Kconfig.debug_blob" + comment "General Debug Settings" # TODO: Better help text and detailed instructions. diff --git a/src/drivers/intel/fsp2_0/Kconfig b/src/drivers/intel/fsp2_0/Kconfig index b434a514a4..3403df99ae 100644 --- a/src/drivers/intel/fsp2_0/Kconfig +++ b/src/drivers/intel/fsp2_0/Kconfig @@ -37,32 +37,6 @@ config ADD_FSP_BINARIES Add the FSP-M and FSP-S binaries to CBFS. Currently coreboot does not use the FSP-T binary and it is not added. -config DISPLAY_FSP_CALLS_AND_STATUS - bool "Display the FSP calls and status" - default n - help - Display the FSP call entry point and parameters prior to calling FSP - and display the status upon return from FSP. - -config DISPLAY_FSP_HEADER - bool "Display the FSP header" - default n - help - Display the FSP header information when the FSP file is found. - -config DISPLAY_HOBS - bool "Display the hand-off-blocks" - default n - help - Display the FSP HOBs which are provided for coreboot. - -config DISPLAY_UPD_DATA - bool "Display UPD data" - default n - help - Display the user specified product data prior to memory - initialization. - config CPU_MICROCODE_CBFS_LEN hex "Microcode update region length in bytes" depends on FSP_CAR @@ -158,22 +132,10 @@ config FSP_TEMP_RAM_SIZE stack with coreboot/bootloader. Sync this value with Platform FSP integration guide recommendation. -config VERIFY_HOBS - bool "Verify the FSP hand-off-blocks" - default n - help - Verify that the HOBs required by coreboot are returned by FSP and - that the resource HOBs are in the correct order and position. - config RESET_ON_INVALID_RAMSTAGE_CACHE bool "Reset the system on S3 wake when ramstage cache invalid." default n -config DISPLAY_FSP_VERSION_INFO - bool "Display Firmware Ingredient Version Information" - help - Select this option to display Firmware version information. - config FSP2_0_USES_TPM_MRC_HASH bool depends on TPM1 || TPM2 diff --git a/src/drivers/intel/fsp2_0/Kconfig.debug_blob b/src/drivers/intel/fsp2_0/Kconfig.debug_blob new file mode 100644 index 0000000000..2b10c2df4f --- /dev/null +++ b/src/drivers/intel/fsp2_0/Kconfig.debug_blob @@ -0,0 +1,41 @@ +if PLATFORM_USES_FSP2_0 + +config DISPLAY_FSP_CALLS_AND_STATUS + bool "Display the FSP calls and status" + default n + help + Display the FSP call entry point and parameters prior to calling FSP + and display the status upon return from FSP. + +config DISPLAY_FSP_HEADER + bool "Display the FSP header" + default n + help + Display the FSP header information when the FSP file is found. + +config DISPLAY_HOBS + bool "Display the hand-off-blocks" + default n + help + Display the FSP HOBs which are provided for coreboot. + +config DISPLAY_UPD_DATA + bool "Display UPD data" + default n + help + Display the user specified product data prior to memory + initialization. + +config VERIFY_HOBS + bool "Verify the FSP hand-off-blocks" + default n + help + Verify that the HOBs required by coreboot are returned by FSP and + that the resource HOBs are in the correct order and position. + +config DISPLAY_FSP_VERSION_INFO + bool "Display Firmware Ingredient Version Information" + help + Select this option to display Firmware version information. + +endif # PLATFORM_USES_FSP2_0 From 08aeda6c14886d39e04382c7fe6d24c4b45c3b0a Mon Sep 17 00:00:00 2001 From: Arthur Heymans Date: Sun, 20 Oct 2019 14:27:40 +0200 Subject: [PATCH 0041/1242] soc/intel/common: Make native and FSP-T CAR init mutually exclusive postcar stage does not consume cpulib.c, so don't include it there. Change-Id: Ie723412dcf09151cdbb41e357ad9c2e4f393cb47 Signed-off-by: Arthur Heymans Reviewed-on: https://review.coreboot.org/c/coreboot/+/36168 Reviewed-by: Nico Huber Reviewed-by: Martin Roth Tested-by: build bot (Jenkins) --- src/soc/intel/common/block/cpu/Makefile.inc | 14 +++++++------- 1 file changed, 7 insertions(+), 7 deletions(-) diff --git a/src/soc/intel/common/block/cpu/Makefile.inc b/src/soc/intel/common/block/cpu/Makefile.inc index 323d15739c..deddb67a16 100644 --- a/src/soc/intel/common/block/cpu/Makefile.inc +++ b/src/soc/intel/common/block/cpu/Makefile.inc @@ -1,13 +1,13 @@ +ifeq ($(CONFIG_FSP_CAR),y) +bootblock-$(CONFIG_SOC_INTEL_COMMON_BLOCK_CPU)+= car/cache_as_ram_fsp.S +postcar-$(CONFIG_SOC_INTEL_COMMON_BLOCK_CPU) += car/exit_car_fsp.S +else bootblock-$(CONFIG_SOC_INTEL_COMMON_BLOCK_CAR) += car/cache_as_ram.S bootblock-$(CONFIG_SOC_INTEL_COMMON_BLOCK_CAR) += ../../../../../cpu/x86/early_reset.S -bootblock-$(CONFIG_FSP_CAR)+= car/cache_as_ram_fsp.S -bootblock-$(CONFIG_SOC_INTEL_COMMON_BLOCK_CPU) += cpulib.c - -romstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_CPU) += cpulib.c - postcar-$(CONFIG_SOC_INTEL_COMMON_BLOCK_CAR) += car/exit_car.S -postcar-$(CONFIG_SOC_INTEL_COMMON_BLOCK_CPU) += cpulib.c -postcar-$(CONFIG_FSP_CAR) += car/exit_car_fsp.S +endif +bootblock-$(CONFIG_SOC_INTEL_COMMON_BLOCK_CPU) += cpulib.c +romstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_CPU) += cpulib.c ramstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_CPU) += cpulib.c ramstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_CPU_MPINIT) += mp_init.c From 585786b69614b2dab3baeb09f21c33ecea0e8b45 Mon Sep 17 00:00:00 2001 From: Arthur Heymans Date: Sun, 20 Oct 2019 14:32:57 +0200 Subject: [PATCH 0042/1242] drivers/intel/fsp2_0: Hide the Kconfig option to run FSP-M XIP MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This is a property of the FSP, not something the user can decide. Change-Id: I2086e67d39e88215ee0f124583b810f7df072f80 Signed-off-by: Arthur Heymans Reviewed-on: https://review.coreboot.org/c/coreboot/+/36170 Tested-by: build bot (Jenkins) Reviewed-by: Michael Niewöhner Reviewed-by: Nico Huber --- src/drivers/intel/fsp2_0/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/drivers/intel/fsp2_0/Kconfig b/src/drivers/intel/fsp2_0/Kconfig index 3403df99ae..1fd4b0cae1 100644 --- a/src/drivers/intel/fsp2_0/Kconfig +++ b/src/drivers/intel/fsp2_0/Kconfig @@ -103,7 +103,7 @@ config FSP_CAR Use FSP APIs to initialize & Tear Down the Cache-As-Ram config FSP_M_XIP - bool "Is FSP-M XIP" + bool default n help Select this value when FSP-M is execute-in-place. From 2d90cb154706b41481cb3444a44c910266f49b96 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ky=C3=B6sti=20M=C3=A4lkki?= Date: Wed, 25 Sep 2019 13:41:04 +0300 Subject: [PATCH 0043/1242] arch/x86: Create preprocessed __ROMCC__ bootblock source MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Output file is used only as a debugging aid. Change-Id: Iea9e1a66409659b47dfa3945c63fa1a7874de1ca Signed-off-by: Kyösti Mälkki Reviewed-on: https://review.coreboot.org/c/coreboot/+/35602 Tested-by: build bot (Jenkins) Reviewed-by: Arthur Heymans --- src/arch/x86/Makefile.inc | 2 ++ 1 file changed, 2 insertions(+) diff --git a/src/arch/x86/Makefile.inc b/src/arch/x86/Makefile.inc index 447fd57a11..c15971ff7b 100644 --- a/src/arch/x86/Makefile.inc +++ b/src/arch/x86/Makefile.inc @@ -167,6 +167,8 @@ $(objgenerated)/bootblock.inc: $(src)/arch/x86/$(subst ",,$(CONFIG_BOOTBLOCK_SOU @printf " ROMCC $(subst $(obj)/,,$(@))\n" $(CC_bootblock) -D__ROMCC__ -D__PRE_RAM__ -D__BOOTBLOCK__ $(CPPFLAGS_bootblock) -MM -MT$(objgenerated)/bootblock.inc \ $< > $(objgenerated)/bootblock.inc.d + $(CC_bootblock) -D__ROMCC__ -D__PRE_RAM__ -D__BOOTBLOCK__ $(CPPFLAGS_bootblock) -E \ + $< -o $(objgenerated)/bootblock_romcc.c $(ROMCC) -c -S $(bootblock_romccflags) -I. $(CPPFLAGS_bootblock) $< -o $@ # bootblock.ld is part of $(bootblock-objs) From 46b125ab6bfd5afa72a10eed70af9196e2a8b79c Mon Sep 17 00:00:00 2001 From: Kane Chen Date: Wed, 9 Oct 2019 18:07:02 +0800 Subject: [PATCH 0044/1242] mb/google/hatch/variants/helios: Modify touchscreen power on sequence The previous values do not affect the touchscreen function. But, the previous values cause the power leakage in S0ix. from b/142368161: 1. Modify GPP_D: The specification define T1 >= 10ms. We change it to 12ms for a safety and low impact value in our mind. Enable pin as GPP_D9 is define to be AVDD in specification. Set it to 10ms to make it to be the final one to pull low during power off sequence . 2. Add GPP_C4: If we set stop_off_delay_ms to be 1. The true T4 we got will be 300us . Set stop_off_delay_ms to be 2 . True T4 will be 500us . So we change it to 5 to be a low impact value in our mind according to the true T4 value we got . BUG=b:142368161 BRANCH=Master TEST=emerge-hatch coreboot chromeos-bootimage ./util/abuild/abuild -p none -t google/hatch -x -a Signed-off-by: YenLu Chen Change-Id: I86c920ff1d5c0b510adde8a37f60003072d5f4e7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/35907 Reviewed-by: Furquan Shaikh Reviewed-by: Shelley Chen Tested-by: build bot (Jenkins) --- .../google/hatch/variants/helios/overridetree.cb | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a/src/mainboard/google/hatch/variants/helios/overridetree.cb b/src/mainboard/google/hatch/variants/helios/overridetree.cb index 262ae8d607..04bf6c12af 100644 --- a/src/mainboard/google/hatch/variants/helios/overridetree.cb +++ b/src/mainboard/google/hatch/variants/helios/overridetree.cb @@ -107,9 +107,13 @@ chip soc/intel/cannonlake register "generic.reset_off_delay_ms" = "1" register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D9)" - register "generic.enable_delay_ms" = "10" - register "generic.enable_off_delay_ms" = "1" + register "generic.enable_delay_ms" = "12" + register "generic.enable_off_delay_ms" = "10" register "generic.has_power_resource" = "1" + register "generic.stop_gpio" = + "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C4)" + register "generic.stop_delay_ms" = "15" + register "generic.stop_off_delay_ms" = "5" register "hid_desc_reg_offset" = "0x01" device i2c 5d on end end From 881f9cb7154ce9a7538507bb872041a2f41a002b Mon Sep 17 00:00:00 2001 From: Edward O'Callaghan Date: Wed, 30 Oct 2019 10:00:33 +1100 Subject: [PATCH 0045/1242] mainboard/google: Allow Hatch variants to read SPD data over SMBus All Hatch variants so far embed static SPD data encoded within the firmware image. However we wish the flexibility for romstage implementations that allow for reading the SPD data dynamically over SMBus. This romstage variant allows for reading the SPD data over SMBus. V.2: Dispence with memcpy(). V.3: Revert back to previous patch with memcpy(). V.4: Rewrite again to avoid memcpy(). BRANCH=none BUG=b:143134702 TEST=./util/abuild/abuild -p none -t google/hatch -x -a Change-Id: I3516a46b91840a9f6d1f4cffb2553d939d79cda2 Signed-off-by: Edward O'Callaghan Reviewed-on: https://review.coreboot.org/c/coreboot/+/36449 Reviewed-by: Furquan Shaikh Tested-by: build bot (Jenkins) --- src/mainboard/google/hatch/Kconfig | 6 ++- src/mainboard/google/hatch/Makefile.inc | 1 + .../google/hatch/romstage_spd_smbus.c | 50 +++++++++++++++++++ 3 files changed, 56 insertions(+), 1 deletion(-) create mode 100644 src/mainboard/google/hatch/romstage_spd_smbus.c diff --git a/src/mainboard/google/hatch/Kconfig b/src/mainboard/google/hatch/Kconfig index 219be2265a..e339693fcb 100644 --- a/src/mainboard/google/hatch/Kconfig +++ b/src/mainboard/google/hatch/Kconfig @@ -60,7 +60,11 @@ config DIMM_SPD_SIZE config ROMSTAGE_SPD_CBFS bool - default y + default y if !ROMSTAGE_SPD_SMBUS + +config ROMSTAGE_SPD_SMBUS + bool + default n config DRIVER_TPM_SPI_BUS default 0x1 diff --git a/src/mainboard/google/hatch/Makefile.inc b/src/mainboard/google/hatch/Makefile.inc index a226bd623c..7ad7849b58 100644 --- a/src/mainboard/google/hatch/Makefile.inc +++ b/src/mainboard/google/hatch/Makefile.inc @@ -21,6 +21,7 @@ ramstage-$(CONFIG_CHROMEOS) += chromeos.c ramstage-$(CONFIG_EC_GOOGLE_CHROMEEC) += ec.c romstage-$(CONFIG_ROMSTAGE_SPD_CBFS) += romstage_spd_cbfs.c +romstage-$(CONFIG_ROMSTAGE_SPD_SMBUS) += romstage_spd_smbus.c romstage-$(CONFIG_CHROMEOS) += chromeos.c verstage-$(CONFIG_CHROMEOS) += chromeos.c diff --git a/src/mainboard/google/hatch/romstage_spd_smbus.c b/src/mainboard/google/hatch/romstage_spd_smbus.c new file mode 100644 index 0000000000..74d59a59f5 --- /dev/null +++ b/src/mainboard/google/hatch/romstage_spd_smbus.c @@ -0,0 +1,50 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2019 Google LLC + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include +#include + +void mainboard_memory_init_params(FSPM_UPD *memupd) +{ + struct cnl_mb_cfg memcfg; + variant_memory_params(&memcfg); + + /* Read spd block to get memory config */ + struct spd_block blk = { + .addr_map = { 0x50, 0x52, }, + }; + + /* Access memory info through SMBUS. */ + get_spd_smbus(&blk); + memcfg.spd[0].read_type = READ_SPD_MEMPTR; + memcfg.spd[0].spd_spec.spd_data_ptr_info.spd_data_len = blk.len; + memcfg.spd[0].spd_spec.spd_data_ptr_info.spd_data_ptr = (uintptr_t)blk.spd_array[0]; + + memcfg.spd[1].read_type = NOT_EXISTING; + + memcfg.spd[2].read_type = READ_SPD_MEMPTR; + memcfg.spd[2].spd_spec.spd_data_ptr_info.spd_data_len = blk.len; + memcfg.spd[2].spd_spec.spd_data_ptr_info.spd_data_ptr = (uintptr_t)blk.spd_array[1]; + + memcfg.spd[3].read_type = NOT_EXISTING; + dump_spd_info(&blk); + + /* set to 2 VREF_CA goes to CH_A and VREF_DQ_B goes to CH_B. */ + memcfg.vref_ca_config = 2; + + cannonlake_memcfg_init(&memupd->FspmConfig, &memcfg); +} From 3042af62562346b2dbcc05f8c614d3380a84d559 Mon Sep 17 00:00:00 2001 From: Edward O'Callaghan Date: Wed, 30 Oct 2019 16:18:25 +1100 Subject: [PATCH 0046/1242] hatch: Create puff variant Includes: - gpio mappings, - overridetree.cb, - kconfig adjustments for reading spd over smbus. V.2: Rework devicetree with comments and drop some useless gpio maps. BUG=b:141658115 TEST=./util/abuild/abuild -p none -t google/hatch -x -a Change-Id: I6449c4fcc1df702ed4f0d35afd7b0981e4c72323 Signed-off-by: Edward O'Callaghan Reviewed-on: https://review.coreboot.org/c/coreboot/+/36452 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh --- src/mainboard/google/hatch/Kconfig | 2 + src/mainboard/google/hatch/Kconfig.name | 6 ++ .../google/hatch/variants/puff/Makefile.inc | 16 +++ .../google/hatch/variants/puff/gpio.c | 56 ++++++++++ .../puff/include/variant/acpi/dptf.asl | 1 + .../hatch/variants/puff/include/variant/ec.h | 21 ++++ .../variants/puff/include/variant/gpio.h | 21 ++++ .../hatch/variants/puff/overridetree.cb | 100 ++++++++++++++++++ 8 files changed, 223 insertions(+) create mode 100644 src/mainboard/google/hatch/variants/puff/Makefile.inc create mode 100644 src/mainboard/google/hatch/variants/puff/gpio.c create mode 100644 src/mainboard/google/hatch/variants/puff/include/variant/acpi/dptf.asl create mode 100644 src/mainboard/google/hatch/variants/puff/include/variant/ec.h create mode 100644 src/mainboard/google/hatch/variants/puff/include/variant/gpio.h create mode 100644 src/mainboard/google/hatch/variants/puff/overridetree.cb diff --git a/src/mainboard/google/hatch/Kconfig b/src/mainboard/google/hatch/Kconfig index e339693fcb..8488762eef 100644 --- a/src/mainboard/google/hatch/Kconfig +++ b/src/mainboard/google/hatch/Kconfig @@ -93,6 +93,7 @@ config MAINBOARD_PART_NUMBER default "Helios" if BOARD_GOOGLE_HELIOS default "Kindred" if BOARD_GOOGLE_KINDRED default "Kohaku" if BOARD_GOOGLE_KOHAKU + default "Puff" if BOARD_GOOGLE_PUFF config MAINBOARD_VENDOR string @@ -118,6 +119,7 @@ config VARIANT_DIR default "helios" if BOARD_GOOGLE_HELIOS default "kindred" if BOARD_GOOGLE_KINDRED default "kohaku" if BOARD_GOOGLE_KOHAKU + default "puff" if BOARD_GOOGLE_PUFF config VBOOT select HAS_RECOVERY_MRC_CACHE diff --git a/src/mainboard/google/hatch/Kconfig.name b/src/mainboard/google/hatch/Kconfig.name index 160194bcfb..2051e0f12a 100644 --- a/src/mainboard/google/hatch/Kconfig.name +++ b/src/mainboard/google/hatch/Kconfig.name @@ -32,3 +32,9 @@ config BOARD_GOOGLE_HELIOS select BOARD_ROMSIZE_KB_16384 select CHROMEOS_DSM_CALIB select DRIVERS_I2C_RT1011 + +config BOARD_GOOGLE_PUFF + bool "-> Puff" + select BOARD_GOOGLE_BASEBOARD_HATCH + select BOARD_ROMSIZE_KB_32768 + select ROMSTAGE_SPD_SMBUS diff --git a/src/mainboard/google/hatch/variants/puff/Makefile.inc b/src/mainboard/google/hatch/variants/puff/Makefile.inc new file mode 100644 index 0000000000..30daaf7f0c --- /dev/null +++ b/src/mainboard/google/hatch/variants/puff/Makefile.inc @@ -0,0 +1,16 @@ +## This file is part of the coreboot project. +## +## Copyright 2019 Google LLC +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +ramstage-y += gpio.c +bootblock-y += gpio.c diff --git a/src/mainboard/google/hatch/variants/puff/gpio.c b/src/mainboard/google/hatch/variants/puff/gpio.c new file mode 100644 index 0000000000..b8b54d3c9c --- /dev/null +++ b/src/mainboard/google/hatch/variants/puff/gpio.c @@ -0,0 +1,56 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2019 Google LLC + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the + * GNU General Public License for more details. + */ + +#include +#include +#include + +/* Early pad configuration in bootblock */ +static const struct pad_config early_gpio_table[] = { + /* B14 : GPP_B14_STRAP */ + PAD_NC(GPP_B14, NONE), + /* B22 : GPP_B22_STRAP */ + PAD_NC(GPP_B22, NONE), + /* E19 : GPP_E19_STRAP */ + PAD_NC(GPP_E19, NONE), + /* E21 : GPP_E21_STRAP */ + PAD_NC(GPP_E21, NONE), + /* B15 : H1_SLAVE_SPI_CS_L */ + PAD_CFG_NF(GPP_B15, NONE, DEEP, NF1), + /* B16 : H1_SLAVE_SPI_CLK */ + PAD_CFG_NF(GPP_B16, NONE, DEEP, NF1), + /* B17 : H1_SLAVE_SPI_MISO_R */ + PAD_CFG_NF(GPP_B17, NONE, DEEP, NF1), + /* B18 : H1_SLAVE_SPI_MOSI_R */ + PAD_CFG_NF(GPP_B18, NONE, DEEP, NF1), + /* C14 : BT_DISABLE_L */ + PAD_CFG_GPO(GPP_C14, 0, DEEP), + /* PCH_WP_OD */ + PAD_CFG_GPI(GPP_C20, NONE, DEEP), + /* C21 : H1_PCH_INT_ODL */ + PAD_CFG_GPI_APIC(GPP_C21, NONE, PLTRST, LEVEL, INVERT), + /* C23 : WLAN_PE_RST# */ + PAD_CFG_GPO(GPP_C23, 1, DEEP), + /* E1 : M2_SSD_PEDET */ + PAD_CFG_NF(GPP_E1, NONE, DEEP, NF1), + /* E5 : SATA_DEVSLP1 */ + PAD_CFG_NF(GPP_E5, NONE, PLTRST, NF1), +}; + +const struct pad_config *variant_early_gpio_table(size_t *num) +{ + *num = ARRAY_SIZE(early_gpio_table); + return early_gpio_table; +} diff --git a/src/mainboard/google/hatch/variants/puff/include/variant/acpi/dptf.asl b/src/mainboard/google/hatch/variants/puff/include/variant/acpi/dptf.asl new file mode 100644 index 0000000000..2c44a82365 --- /dev/null +++ b/src/mainboard/google/hatch/variants/puff/include/variant/acpi/dptf.asl @@ -0,0 +1 @@ +#include diff --git a/src/mainboard/google/hatch/variants/puff/include/variant/ec.h b/src/mainboard/google/hatch/variants/puff/include/variant/ec.h new file mode 100644 index 0000000000..768987d225 --- /dev/null +++ b/src/mainboard/google/hatch/variants/puff/include/variant/ec.h @@ -0,0 +1,21 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2019 Google LLC + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef VARIANT_EC_H +#define VARIANT_EC_H + +#include + +#endif diff --git a/src/mainboard/google/hatch/variants/puff/include/variant/gpio.h b/src/mainboard/google/hatch/variants/puff/include/variant/gpio.h new file mode 100644 index 0000000000..d99e2bbd65 --- /dev/null +++ b/src/mainboard/google/hatch/variants/puff/include/variant/gpio.h @@ -0,0 +1,21 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2019 Google LLC + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the + * GNU General Public License for more details. + */ + +#ifndef VARIANT_GPIO_H +#define VARIANT_GPIO_H + +#include + +#endif diff --git a/src/mainboard/google/hatch/variants/puff/overridetree.cb b/src/mainboard/google/hatch/variants/puff/overridetree.cb new file mode 100644 index 0000000000..d5e2e5afb5 --- /dev/null +++ b/src/mainboard/google/hatch/variants/puff/overridetree.cb @@ -0,0 +1,100 @@ +chip soc/intel/cannonlake + + register "SerialIoDevMode" = "{ + [PchSerialIoIndexI2C0] = PchSerialIoDisabled, + [PchSerialIoIndexI2C1] = PchSerialIoDisabled, + [PchSerialIoIndexI2C2] = PchSerialIoPci, + [PchSerialIoIndexI2C3] = PchSerialIoPci, + [PchSerialIoIndexI2C4] = PchSerialIoPci, + [PchSerialIoIndexI2C5] = PchSerialIoPci, + [PchSerialIoIndexSPI0] = PchSerialIoPci, + [PchSerialIoIndexSPI1] = PchSerialIoPci, + [PchSerialIoIndexSPI2] = PchSerialIoDisabled, + [PchSerialIoIndexUART0] = PchSerialIoSkipInit, + [PchSerialIoIndexUART1] = PchSerialIoDisabled, + [PchSerialIoIndexUART2] = PchSerialIoDisabled, + }" + + # Intel Common SoC Config + #+-------------------+---------------------------+ + #| Field | Value | + #+-------------------+---------------------------+ + #| GSPI0 | cr50 TPM. Early init is | + #| | required to set up a BAR | + #| | for TPM communication | + #| | before memory is up | + #| I2C0 | RFU | + #| I2C2 | PS175 | + #| I2C3 | MST | + #| I2C4 | Audio | + #+-------------------+---------------------------+ + register "common_soc_config" = "{ + .gspi[0] = { + .speed_mhz = 1, + .early_init = 1, + }, + .i2c[0] = { + .speed = I2C_SPEED_FAST, + .rise_time_ns = 0, + .fall_time_ns = 0, + }, + .i2c[1] = { + .speed = I2C_SPEED_FAST, + .rise_time_ns = 0, + .fall_time_ns = 0, + }, + .i2c[3] = { + .speed = I2C_SPEED_FAST, + .rise_time_ns = 0, + .fall_time_ns = 0, + }, + .i2c[4] = { + .speed = I2C_SPEED_FAST, + .rise_time_ns = 0, + .fall_time_ns = 0, + }, + }" + + # GPIO for SD card detect + register "sdcard_cd_gpio" = "vSD3_CD_B" + + device domain 0 on + device pci 15.0 off + # RFU - Reserved for Future Use. + end # I2C #0 + device pci 15.1 off end # I2C #1 + device pci 15.2 on +# chip drivers/i2c/generic +# register "name" = ""PS175"" +# register "desc" = ""PCON PS175"" +# register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C10)" +# register "stop_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C11)" +# register "has_power_resource" = "1" +# device i2c 15 on end +# end + end # I2C #2 + device pci 15.3 on +# chip drivers/i2c/generic +# register "name" = ""RTD21"" +# register "desc" = ""Realtek RTD2142"" +# device i2c 4a on end +# end + end # I2C #3 + device pci 19.0 on + chip drivers/i2c/generic + register "hid" = ""10EC5682"" + register "name" = ""RT58"" + register "desc" = ""Realtek RT5682"" + register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_BOTH(GPP_H0)" + register "property_count" = "1" + # Set the jd_src to RT5668_JD1 for jack detection + register "property_list[0].type" = "ACPI_DP_TYPE_INTEGER" + register "property_list[0].name" = ""realtek,jd-src"" + register "property_list[0].integer" = "1" + device i2c 1a on end + end + end #I2C #4 + device pci 1e.3 off end # GSPI #1 + end + +end From 32c8de10b03d0f7fccd4e4dc10a20f97e57cc428 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ky=C3=B6sti=20M=C3=A4lkki?= Date: Sat, 2 Nov 2019 09:39:36 +0200 Subject: [PATCH 0047/1242] Rangeley: Fix incorrect BCLK MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Not all Rangeley SKUs have a fixed 100MHz BCLK. As per BIOS Writer's Guide, BCLK is available in MSR_FSB_FREQ 0xCD[1:0]. Using fixed BCLK was causing wrong values of core frequencies in _PSS table for SKUs that do not have BCLK=100MHz. Change-Id: Id8e0244fab0283b74870950cb00a95aab2a7201f Signed-off-by: Hannah Williams Signed-off-by: Kyösti Mälkki Reviewed-on: https://review.coreboot.org/c/coreboot/+/35348 Reviewed-by: Aaron Durbin Tested-by: build bot (Jenkins) --- src/cpu/intel/common/fsb.c | 6 +++++- src/cpu/intel/fsp_model_406dx/acpi.c | 20 ++++++++++++++++++-- src/cpu/intel/fsp_model_406dx/model_406dx.h | 2 -- 3 files changed, 23 insertions(+), 5 deletions(-) diff --git a/src/cpu/intel/common/fsb.c b/src/cpu/intel/common/fsb.c index 14dbd60e24..0004eade89 100644 --- a/src/cpu/intel/common/fsb.c +++ b/src/cpu/intel/common/fsb.c @@ -32,6 +32,7 @@ static int get_fsb_tsc(int *fsb, int *ratio) static const short core_fsb[8] = { -1, 133, -1, 166, -1, 100, -1, -1 }; static const short core2_fsb[8] = { 266, 133, 200, 166, 333, 100, 400, -1 }; static const short f2x_fsb[8] = { 100, 133, 200, 166, 333, -1, -1, -1 }; + static const short rangeley_fsb[4] = { 83, 100, 133, 116 }; msr_t msr; get_fms(&c, cpuid_eax(1)); @@ -56,10 +57,13 @@ static int get_fsb_tsc(int *fsb, int *ratio) case 0x3a: /* IvyBridge BCLK fixed at 100MHz */ case 0x3c: /* Haswell BCLK fixed at 100MHz */ case 0x45: /* Haswell-ULT BCLK fixed at 100MHz */ - case 0x4d: /* Rangeley BCLK fixed at 100MHz */ *fsb = 100; *ratio = (rdmsr(MSR_PLATFORM_INFO).lo >> 8) & 0xff; break; + case 0x4d: /* Rangeley */ + *fsb = rangeley_fsb[rdmsr(MSR_FSB_FREQ).lo & 3]; + *ratio = (rdmsr(MSR_PLATFORM_INFO).lo >> 8) & 0xff; + break; default: return -2; } diff --git a/src/cpu/intel/fsp_model_406dx/acpi.c b/src/cpu/intel/fsp_model_406dx/acpi.c index 6672eab3d1..078905deac 100644 --- a/src/cpu/intel/fsp_model_406dx/acpi.c +++ b/src/cpu/intel/fsp_model_406dx/acpi.c @@ -13,6 +13,7 @@ */ #include +#include #include #include #include @@ -20,6 +21,7 @@ #include #include #include +#include #include #include #include "model_406dx.h" @@ -154,6 +156,20 @@ static int calculate_power(int tdp, int p1_ratio, int ratio) return (int)power; } +static int get_core_frequency_mhz(int ratio) +{ + int fsb, core_freq; + + /* Get BCLK - different SKUs can have different BCLK */ + fsb = get_timer_fsb(); + + printk(BIOS_DEBUG, "BCLK:%d MHz ratio:%d\n", fsb, ratio); + + core_freq = DIV_ROUND_CLOSEST(fsb * ratio, 100) * 100; + printk(BIOS_DEBUG, "core frequency for ratio(%d) %dMHz\n", ratio, core_freq); + return core_freq; +} + static void generate_P_state_entries(int core, int cores_per_package) { int ratio_min, ratio_max, ratio_turbo, ratio_step; @@ -177,7 +193,7 @@ static void generate_P_state_entries(int core, int cores_per_package) /* Max Non-Turbo Ratio */ ratio_max = (msr.lo >> 8) & 0xff; } - clock_max = ratio_max * RANGELEY_BCLK; + clock_max = get_core_frequency_mhz(ratio_max); /* Calculate CPU TDP in mW */ msr = rdmsr(MSR_PKG_POWER_SKU_UNIT); @@ -240,7 +256,7 @@ static void generate_P_state_entries(int core, int cores_per_package) /* Calculate power at this ratio */ power = calculate_power(power_max, ratio_max, ratio); - clock = ratio * RANGELEY_BCLK; + clock = get_core_frequency_mhz(ratio); acpigen_write_PSS_package( clock, /*MHz*/ diff --git a/src/cpu/intel/fsp_model_406dx/model_406dx.h b/src/cpu/intel/fsp_model_406dx/model_406dx.h index 53a77a98a3..140dc2e4bf 100644 --- a/src/cpu/intel/fsp_model_406dx/model_406dx.h +++ b/src/cpu/intel/fsp_model_406dx/model_406dx.h @@ -15,8 +15,6 @@ #ifndef _CPU_INTEL_MODEL_406DX_H #define _CPU_INTEL_MODEL_406DX_H -/* Rangeley bus clock is fixed at 100MHz */ -#define RANGELEY_BCLK 100 #define MSR_FEATURE_CONFIG 0x13c #define MSR_FLEX_RATIO 0x194 From 114e2e88305a6e1fc972a58a03b89a23685e5a48 Mon Sep 17 00:00:00 2001 From: Wim Vervoorn Date: Tue, 5 Nov 2019 14:09:16 +0100 Subject: [PATCH 0048/1242] lib/cbfs: Add fallback to RO region to cbfs_boot_locate With this change cbfs_boot_locate will check the RO (COREBOOT) region if a file can not be found in the active RW region. By doing so it is not required to duplicate static files that are not intended to be updated to the RW regions. The coreboot image can still be updated by adding the file to the RW region. This change is intended to support VBOOT on systems with a small flash device. BUG=N/A TEST=tested on facebook fbg1701 Change-Id: I81ceaf927280cef9a3f09621c796c451e9115211 Signed-off-by: Wim Vervoorn Reviewed-on: https://review.coreboot.org/c/coreboot/+/36545 Reviewed-by: Frans Hendriks Reviewed-by: Aaron Durbin Tested-by: build bot (Jenkins) --- Documentation/security/vboot/index.md | 20 ++++++++++++++++++++ src/lib/cbfs.c | 16 ++++++++++++++++ src/security/vboot/Kconfig | 9 +++++++++ 3 files changed, 45 insertions(+) diff --git a/Documentation/security/vboot/index.md b/Documentation/security/vboot/index.md index 97420893e5..400c2b5149 100644 --- a/Documentation/security/vboot/index.md +++ b/Documentation/security/vboot/index.md @@ -186,6 +186,26 @@ In addition to adding the coreboot files into the read-only region, enabling vboot causes the build script to add the read/write files into coreboot file systems in *FW_MAIN_A* and *FW_MAIN_B*. +**RO_REGION_ONLY** + +The files added to this list will only be placed in the read-only region and +not into the read/write coreboot file systems in *FW_MAIN_A* and *FW_MAIN_B*. + +**VBOOT_ENABLE_CBFS_FALLBACK** + +Normally coreboot will use the active read/write coreboot file system for all +of it's file access when VBOOT is active and is not in recovery mode. + +When the `VBOOT_ENABLE_CBFS_FALLBACK` option is enabled the cbfs file system will +first try to locate a file in the active read/write file system. If the file +doesn't exist here the file system will try to locate the file in the read-only +file system. + +This option can be used to prevent duplication of static data. Files can be +removed from the read/write partitions by adding them to the `RO_REGION_ONLY` +config. If a file needs to be changed in a later stage simply remove it from +this list. + *** ## Signing the coreboot Image diff --git a/src/lib/cbfs.c b/src/lib/cbfs.c index 9ac1bc084b..13b5afb6ea 100644 --- a/src/lib/cbfs.c +++ b/src/lib/cbfs.c @@ -62,6 +62,22 @@ int cbfs_boot_locate(struct cbfsf *fh, const char *name, uint32_t *type) } int ret = cbfs_locate(fh, &rdev, name, type); + + if (CONFIG(VBOOT_ENABLE_CBFS_FALLBACK) && ret) { + + /* + * When VBOOT_ENABLE_CBFS_FALLBACK is enabled and a file is not available in the + * active RW region, the RO (COREBOOT) region will be used to locate the file. + * + * This functionality makes it possible to avoid duplicate files in the RO + * and RW partitions while maintaining updateability. + * + * Files can be added to the RO_REGION_ONLY config option to use this feature. + */ + printk(BIOS_DEBUG, "Fall back to RO region for %s\n", name); + ret = cbfs_locate_file_in_region(fh, "COREBOOT", name, type); + } + if (!ret) if (vboot_measure_cbfs_hook(fh, name)) return -1; diff --git a/src/security/vboot/Kconfig b/src/security/vboot/Kconfig index e3b8aa68e2..87bb80a561 100644 --- a/src/security/vboot/Kconfig +++ b/src/security/vboot/Kconfig @@ -220,6 +220,15 @@ config RO_REGION_ONLY Add a space delimited list of filenames that should only be in the RO section. + +config VBOOT_ENABLE_CBFS_FALLBACK + bool + default n + depends on VBOOT_SLOTS_RW_A + help + When this option is enabled cbfs_boot_locate will look for a file in the RO + (COREBOOT) region if it isn't available in the active RW region. + menu "GBB configuration" config GBB_HWID From 1b1a26acdc814d0478bb5fda0b6664076a60fdf1 Mon Sep 17 00:00:00 2001 From: Subrata Banik Date: Tue, 5 Nov 2019 16:54:58 +0530 Subject: [PATCH 0049/1242] soc/intel/icelake: Refactor pch_early_init() code This patch keeps required pch_early_init() function like ABASE programming, GPE and RTC init into bootblock and moves remaining functions like TCO configuration and SMBUS init into romstage/pch.c in order to maintain only required chipset programming for bootblock and verstage. TEST=Able to build and boot ICL DE system. Change-Id: I4f0914242c3215f6bf76e41c468f544361a740d8 Signed-off-by: Subrata Banik Reviewed-on: https://review.coreboot.org/c/coreboot/+/36627 Reviewed-by: Aamir Bohra Reviewed-by: Furquan Shaikh Reviewed-by: Maulik V Vaghela Tested-by: build bot (Jenkins) --- src/soc/intel/icelake/bootblock/pch.c | 13 +--------- src/soc/intel/icelake/include/soc/romstage.h | 1 + src/soc/intel/icelake/romstage/Makefile.inc | 1 + src/soc/intel/icelake/romstage/pch.c | 27 ++++++++++++++++++++ src/soc/intel/icelake/romstage/romstage.c | 2 ++ 5 files changed, 32 insertions(+), 12 deletions(-) create mode 100644 src/soc/intel/icelake/romstage/pch.c diff --git a/src/soc/intel/icelake/bootblock/pch.c b/src/soc/intel/icelake/bootblock/pch.c index e95220b90e..b8a404b379 100644 --- a/src/soc/intel/icelake/bootblock/pch.c +++ b/src/soc/intel/icelake/bootblock/pch.c @@ -1,7 +1,7 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2018 Intel Corp. + * Copyright (C) 2018-2019 Intel Corp. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -23,17 +23,13 @@ #include #include #include -#include -#include #include -#include #include #include #include #include #include #include -#include #define PCR_PSF3_TO_SHDW_PMC_REG_BASE 0x0600 #define PCR_PSFX_TO_SHDW_BAR0 0 @@ -94,7 +90,6 @@ void bootblock_pch_early_init(void) soc_config_pwrmbase(); } - static void soc_config_acpibase(void) { uint32_t pmc_reg_value; @@ -163,12 +158,6 @@ void pch_early_init(void) */ soc_config_acpibase(); - /* Programming TCO_BASE_ADDRESS and TCO Timer Halt */ - tco_configure(); - - /* Program SMBUS_BASE_ADDRESS and Enable it */ - smbus_common_init(); - /* Set up GPE configuration */ pmc_gpe_init(); diff --git a/src/soc/intel/icelake/include/soc/romstage.h b/src/soc/intel/icelake/include/soc/romstage.h index e931811302..977c7c057a 100644 --- a/src/soc/intel/icelake/include/soc/romstage.h +++ b/src/soc/intel/icelake/include/soc/romstage.h @@ -20,6 +20,7 @@ void mainboard_memory_init_params(FSPM_UPD *mupd); void systemagent_early_init(void); +void pch_init(void); /* Board type */ enum board_type { diff --git a/src/soc/intel/icelake/romstage/Makefile.inc b/src/soc/intel/icelake/romstage/Makefile.inc index baa4d46e55..b42f3f4b7a 100644 --- a/src/soc/intel/icelake/romstage/Makefile.inc +++ b/src/soc/intel/icelake/romstage/Makefile.inc @@ -16,4 +16,5 @@ romstage-y += fsp_params.c romstage-y += ../../../../cpu/intel/car/romstage.c romstage-y += romstage.c +romstage-y += pch.c romstage-y += systemagent.c diff --git a/src/soc/intel/icelake/romstage/pch.c b/src/soc/intel/icelake/romstage/pch.c new file mode 100644 index 0000000000..88a7cc7163 --- /dev/null +++ b/src/soc/intel/icelake/romstage/pch.c @@ -0,0 +1,27 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include + +void pch_init(void) +{ + /* Programming TCO_BASE_ADDRESS and TCO Timer Halt */ + tco_configure(); + + /* Program SMBUS_BASE_ADDRESS and Enable it */ + smbus_common_init(); +} diff --git a/src/soc/intel/icelake/romstage/romstage.c b/src/soc/intel/icelake/romstage/romstage.c index 2c4ba67e04..7f1be731e8 100644 --- a/src/soc/intel/icelake/romstage/romstage.c +++ b/src/soc/intel/icelake/romstage/romstage.c @@ -116,6 +116,8 @@ void mainboard_romstage_entry(void) /* Program MCHBAR, DMIBAR, GDXBAR and EDRAMBAR */ systemagent_early_init(); + /* Program PCH init */ + pch_init(); /* initialize Heci interface */ heci_init(HECI1_BASE_ADDRESS); From 4e074033de11eebeb0f341f6d7a91eaab27f68ab Mon Sep 17 00:00:00 2001 From: Mario Scheithauer Date: Wed, 6 Nov 2019 11:01:00 +0100 Subject: [PATCH 0050/1242] soc/intel/{apl,dnv,quark}: Use strip_quotes for FSP options The commit 8fc523e3 (drivers/intel/fsp2_0: Use strip_quotes for cbfs filenames) breaks the Siemens APL mainboards as FSP-M never returns once it is called. The reason for this is that the -b option is missing when adding the FSP package to cbfs via cbfstool. This patch fixes this issue. TEST=tested on siemens/mc_apl5 Change-Id: I48e5fa36e1ad799d09714f53a3041f73b8ec3550 Signed-off-by: Mario Scheithauer Reviewed-on: https://review.coreboot.org/c/coreboot/+/36645 Reviewed-by: Subrata Banik Reviewed-by: David Guckian Reviewed-by: Patrick Georgi Tested-by: build bot (Jenkins) --- src/soc/intel/apollolake/Makefile.inc | 2 +- src/soc/intel/denverton_ns/Makefile.inc | 6 +++--- src/soc/intel/quark/Makefile.inc | 2 +- 3 files changed, 5 insertions(+), 5 deletions(-) diff --git a/src/soc/intel/apollolake/Makefile.inc b/src/soc/intel/apollolake/Makefile.inc index 42cbab048f..ef81e32abd 100644 --- a/src/soc/intel/apollolake/Makefile.inc +++ b/src/soc/intel/apollolake/Makefile.inc @@ -108,7 +108,7 @@ endif CPPFLAGS_common += -I$(src)/soc/intel/apollolake/include # Since FSP-M runs in CAR we need to relocate it to a specific address -$(FSP_M_CBFS)-options := -b $(CONFIG_FSP_M_ADDR) +$(call strip_quotes,$(CONFIG_FSP_M_CBFS))-options := -b $(CONFIG_FSP_M_ADDR) # Handle GLK paging requirements ifeq ($(CONFIG_PAGING_IN_CACHE_AS_RAM),y) diff --git a/src/soc/intel/denverton_ns/Makefile.inc b/src/soc/intel/denverton_ns/Makefile.inc index 51ae1369c5..4050f61811 100644 --- a/src/soc/intel/denverton_ns/Makefile.inc +++ b/src/soc/intel/denverton_ns/Makefile.inc @@ -90,8 +90,8 @@ CPPFLAGS_common += -I$(src)/vendorcode/intel/fsp/fsp2_0/denverton_ns ##Set FSP binary blobs memory location -$(FSP_T_CBFS)-options := -b $(CONFIG_FSP_T_ADDR) --xip -$(FSP_M_CBFS)-options := -b $(CONFIG_FSP_M_ADDR) --xip -$(FSP_S_CBFS)-options := -b $(CONFIG_FSP_S_ADDR) --xip +$(call strip_quotes,$(CONFIG_FSP_T_CBFS))-options := -b $(CONFIG_FSP_T_ADDR) --xip +$(call strip_quotes,$(CONFIG_FSP_M_CBFS))-options := -b $(CONFIG_FSP_M_ADDR) --xip +$(call strip_quotes,$(CONFIG_FSP_S_CBFS))-options := -b $(CONFIG_FSP_S_ADDR) --xip endif ## CONFIG_SOC_INTEL_DENVERTON_NS diff --git a/src/soc/intel/quark/Makefile.inc b/src/soc/intel/quark/Makefile.inc index f2413c8805..bd120abc9f 100644 --- a/src/soc/intel/quark/Makefile.inc +++ b/src/soc/intel/quark/Makefile.inc @@ -71,7 +71,7 @@ CPPFLAGS_common += -I$(src)/soc/intel/quark/include/soc/fsp CPPFLAGS_common += -I3rdparty/blobs/soc/intel/quark # Since FSP-M runs in CAR we need to relocate it to a specific address -$(FSP_M_CBFS)-options := -b $(CONFIG_FSP_ESRAM_LOC) +$(call strip_quotes,$(CONFIG_FSP_M_CBFS))-options := -b $(CONFIG_FSP_ESRAM_LOC) # Add the FSP binary to the CBFS image cbfs-files-$(CONFIG_ADD_FSP_RAW_BIN) += fsp.bin From 07f798d74c70a98c5616c0161488e974513e25fb Mon Sep 17 00:00:00 2001 From: Peichao Wang Date: Wed, 6 Nov 2019 17:49:53 +0800 Subject: [PATCH 0051/1242] mb/google/hatch/var/akemi: disable unused USB port for Akemi platform Akemi platform dosen't support WWAN device and unused USB2 port 3, 4, 5, 7, 8 and USB3 port 3, 4, 5 so close them. BUG=None TEST=FW_NAME="akemi" emerge-hatch coreboot chromeos-ec chromeos-bootimage Signed-off-by: Peichao.Wang Change-Id: I7eff4da77caea7d4fe46597320be134d34d78a22 Reviewed-on: https://review.coreboot.org/c/coreboot/+/36644 Tested-by: build bot (Jenkins) Reviewed-by: Tim Wawrzynczak --- .../hatch/variants/akemi/overridetree.cb | 106 ++++++++++++++++++ 1 file changed, 106 insertions(+) diff --git a/src/mainboard/google/hatch/variants/akemi/overridetree.cb b/src/mainboard/google/hatch/variants/akemi/overridetree.cb index 51395f9f5c..da669e4536 100644 --- a/src/mainboard/google/hatch/variants/akemi/overridetree.cb +++ b/src/mainboard/google/hatch/variants/akemi/overridetree.cb @@ -17,6 +17,24 @@ chip soc/intel/cannonlake [PchSerialIoIndexUART2] = PchSerialIoDisabled, }" + register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC2)" # Type-C Port 0 + register "usb2_ports[1]" = "USB2_PORT_TYPE_C(OC2)" # Type-C Port 1 + register "usb2_ports[2]" = "USB2_PORT_SHORT(OC3)" # Type-A Port 0 + register "usb2_ports[3]" = "USB2_PORT_EMPTY" # Unused + register "usb2_ports[4]" = "USB2_PORT_EMPTY" + register "usb2_ports[5]" = "USB2_PORT_EMPTY" # WWAN + register "usb2_ports[6]" = "USB2_PORT_LONG(OC_SKIP)" # Camera + register "usb2_ports[7]" = "USB2_PORT_EMPTY" + register "usb2_ports[8]" = "USB2_PORT_EMPTY" + register "usb2_ports[9]" = "USB2_PORT_MID(OC_SKIP)" # BT + + register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC2)" # Type-C Port 0 + register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC2)" # Type-C Port 1 + register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC3)" # Type-A Port 0 + register "usb3_ports[3]" = "USB3_PORT_EMPTY" # Unused + register "usb3_ports[4]" = "USB3_PORT_EMPTY" # WWAN + register "usb3_ports[5]" = "USB3_PORT_EMPTY" + # Intel Common SoC Config #+-------------------+---------------------------+ #| Field | Value | @@ -59,6 +77,94 @@ chip soc/intel/cannonlake register "ScsEmmcHs400Enabled" = "1" device domain 0 on + device pci 14.0 on + chip drivers/usb/acpi + register "desc" = ""Root Hub"" + register "type" = "UPC_TYPE_HUB" + device usb 0.0 on + chip drivers/usb/acpi + register "desc" = ""Left Type-C Port"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "group" = "ACPI_PLD_GROUP(1, 1)" + device usb 2.0 on end + end + chip drivers/usb/acpi + register "desc" = ""Right Type-C Port 1"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "group" = "ACPI_PLD_GROUP(2, 1)" + device usb 2.1 on end + end + chip drivers/usb/acpi + register "desc" = ""Left Type-A Port"" + register "type" = "UPC_TYPE_A" + register "group" = "ACPI_PLD_GROUP(1, 2)" + device usb 2.2 on end + end + chip drivers/usb/acpi + # No Type-A Port 1 + device usb 2.3 off end + end + chip drivers/usb/acpi + # Unused + device usb 2.4 off end + end + chip drivers/usb/acpi + # No WWAN + device usb 2.5 off end + end + chip drivers/usb/acpi + register "desc" = ""Camera"" + register "type" = "UPC_TYPE_INTERNAL" + device usb 2.6 on end + end + chip drivers/usb/acpi + # Unused + device usb 2.7 off end + end + chip drivers/usb/acpi + # Unused + device usb 2.8 off end + end + chip drivers/usb/acpi + register "desc" = ""Bluetooth"" + register "type" = "UPC_TYPE_INTERNAL" + register "reset_gpio" = + "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C14)" + device usb 2.9 on end + end + chip drivers/usb/acpi + register "desc" = ""Left Type-C Port"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "group" = "ACPI_PLD_GROUP(1, 1)" + device usb 3.0 on end + end + chip drivers/usb/acpi + register "desc" = ""Right Type-C Port 1"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "group" = "ACPI_PLD_GROUP(2, 1)" + device usb 3.1 on end + end + chip drivers/usb/acpi + register "desc" = ""Left Type-A Port"" + register "type" = "UPC_TYPE_USB3_A" + register "group" = "ACPI_PLD_GROUP(1, 2)" + device usb 3.2 on end + end + chip drivers/usb/acpi + # No Type-A Port 1 + device usb 3.3 off end + end + chip drivers/usb/acpi + # No WWAN + device usb 3.4 off end + end + chip drivers/usb/acpi + # Unused + device usb 3.5 off end + end + end + end + end # USB xHCI device pci 15.0 on chip drivers/i2c/generic register "hid" = ""ELAN0000"" From dd227a7d97fff248360d9e9d6df11e0dbc303959 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ky=C3=B6sti=20M=C3=A4lkki?= Date: Tue, 5 Nov 2019 18:20:41 +0200 Subject: [PATCH 0052/1242] mb/facebook/fbg1701: Remove some preprocessor guards MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Change-Id: Ia7289fa8337e1a93e620a52a67ca8cbdd78a66bc Signed-off-by: Kyösti Mälkki Reviewed-on: https://review.coreboot.org/c/coreboot/+/36633 Tested-by: build bot (Jenkins) Reviewed-by: Wim Vervoorn Reviewed-by: Frans Hendriks --- .../facebook/fbg1701/board_verified_boot.c | 14 ++------------ 1 file changed, 2 insertions(+), 12 deletions(-) diff --git a/src/mainboard/facebook/fbg1701/board_verified_boot.c b/src/mainboard/facebook/fbg1701/board_verified_boot.c index 1ccb0b8ea3..bb5768fdc1 100644 --- a/src/mainboard/facebook/fbg1701/board_verified_boot.c +++ b/src/mainboard/facebook/fbg1701/board_verified_boot.c @@ -15,7 +15,6 @@ #include "board_verified_boot.h" -#ifdef __BOOTBLOCK__ /* The items verified by the bootblock, the bootblock will not measure the * items to the TPM */ @@ -32,9 +31,7 @@ const verify_item_t bootblock_verify_list[] = { MBOOT_PCR_INDEX_0 }, { VERIFY_TERMINATOR, NULL, { { NULL, 0 } }, 0, 0 } }; -#endif -#if defined(__ROMSTAGE__) || defined(__POSTCAR__) /* The FSP is already checked in romstage */ static const verify_item_t ram_stage_additional_list[] = { { VERIFY_FILE, OP_ROM_VBT, { { NULL, CBFS_TYPE_RAW } }, @@ -44,10 +41,8 @@ static const verify_item_t ram_stage_additional_list[] = { { VERIFY_FILE, "fallback/dsdt.aml", { { NULL, CBFS_TYPE_RAW } }, HASH_IDX_DSDT, MBOOT_PCR_INDEX_2 }, { VERIFY_TERMINATOR, NULL, { { NULL, 0 } }, 0, 0 } - }; -#endif +}; -#ifdef __ROMSTAGE__ /* The items used by the romstage */ const verify_item_t romstage_verify_list[] = { { VERIFY_FILE, ROMSTAGE, { { NULL, CBFS_TYPE_STAGE } }, @@ -75,10 +70,8 @@ const verify_item_t ramstage_verify_list[] = { CBFS_TYPE_STAGE } }, HASH_IDX_RAM_STAGE, MBOOT_PCR_INDEX_0 }, { VERIFY_TERMINATOR, NULL, { { NULL, 0 } }, 0, 0 } }; -#endif -#ifdef __POSTCAR__ -/* POSTSTAGE */ +/* POSTCAR */ /* The items used by the postcar stage */ const verify_item_t postcar_verify_list[] = { { VERIFY_FILE, RAMSTAGE, { { ram_stage_additional_list, @@ -91,9 +84,7 @@ const verify_item_t postcar_verify_list[] = { MBOOT_PCR_INDEX_1 }, { VERIFY_TERMINATOR, NULL, { { NULL, 0 } }, 0, 0 } }; -#endif -#ifdef __RAMSTAGE__ /* RAMSTAGE */ const verify_item_t payload_verify_list[] = { { VERIFY_FILE, PAYLOAD, { { NULL, CBFS_TYPE_SELF | @@ -105,4 +96,3 @@ const verify_item_t payload_verify_list[] = { const verify_item_t oprom_verify_list[] = { { VERIFY_TERMINATOR, NULL, { { NULL, 0 } }, 0, 0 } }; -#endif From ed8eaab08a79f6a20b2bcffd5a1073e56812ac2b Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ky=C3=B6sti=20M=C3=A4lkki?= Date: Tue, 5 Nov 2019 17:12:42 +0200 Subject: [PATCH 0053/1242] eltan/security: Remove some preprocessor guards MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit We generally let garbage-collection take care of unused functions. While at it, move some related variable declarations in to the header file and declare them const like they should be. Change-Id: I7c6fa15bd45f861f13b6123ccb14c55415e42bc7 Signed-off-by: Kyösti Mälkki Reviewed-on: https://review.coreboot.org/c/coreboot/+/36632 Reviewed-by: Wim Vervoorn Reviewed-by: Patrick Georgi Tested-by: build bot (Jenkins) --- src/vendorcode/eltan/security/mboot/mboot.c | 2 - .../security/verified_boot/vboot_check.c | 69 +++++++------------ .../security/verified_boot/vboot_check.h | 9 +-- 3 files changed, 29 insertions(+), 51 deletions(-) diff --git a/src/vendorcode/eltan/security/mboot/mboot.c b/src/vendorcode/eltan/security/mboot/mboot.c index 4823c6aa00..228d1a0f59 100644 --- a/src/vendorcode/eltan/security/mboot/mboot.c +++ b/src/vendorcode/eltan/security/mboot/mboot.c @@ -266,7 +266,6 @@ int mb_measure_log_worker(const char *name, uint32_t type, uint32_t pcr, return status; } -#ifdef __PRE_RAM__ /* * Called from early romstage * @@ -473,4 +472,3 @@ int __attribute__((weak))mb_crtm(void) return status; } -#endif // __PRE_RAM__ diff --git a/src/vendorcode/eltan/security/verified_boot/vboot_check.c b/src/vendorcode/eltan/security/verified_boot/vboot_check.c index 88519bdd78..fdae7b8b46 100644 --- a/src/vendorcode/eltan/security/verified_boot/vboot_check.c +++ b/src/vendorcode/eltan/security/verified_boot/vboot_check.c @@ -276,13 +276,11 @@ void process_verify_list(const verify_item_t list[]) i++; } } -#ifdef __BOOTBLOCK__ + /* * BOOTBLOCK */ -extern verify_item_t bootblock_verify_list[]; - void verified_boot_bootblock_check(void) { printk(BIOS_SPEW, "%s: processing bootblock items\n", __func__); @@ -296,14 +294,6 @@ void verified_boot_bootblock_check(void) process_verify_list(bootblock_verify_list); } -static void vendor_secure_prepare(void) -{ - printk(BIOS_SPEW, "%s: bootblock\n", __func__); - verified_boot_bootblock_check(); -} -#endif //__BOOTBLOCK__ - -#ifdef __ROMSTAGE__ /* * ROMSTAGE */ @@ -330,33 +320,6 @@ void verified_boot_early_check(void) process_verify_list(romstage_verify_list); } -static int prepare_romstage = 0; - -static void vendor_secure_prepare(void) -{ - printk(BIOS_SPEW, "%s: romstage\n", __func__); - if (!prepare_romstage) { - verified_boot_early_check(); - prepare_romstage = 1; - } -} -#endif //__ROMSTAGE__ - -#ifdef __POSTCAR__ -/* - * POSTCAR - */ - -extern verify_item_t postcar_verify_list[]; - -static void vendor_secure_prepare(void) -{ - printk(BIOS_SPEW, "%s: postcar\n", __func__); - process_verify_list(postcar_verify_list); -} -#endif //__POSTCAR__ - -#ifdef __RAMSTAGE__ /* * RAM STAGE */ @@ -408,10 +371,6 @@ static int process_oprom_list(const verify_item_t list[], return 0; } -extern verify_item_t payload_verify_list[]; - -extern verify_item_t oprom_verify_list[]; - int verified_boot_should_run_oprom(struct rom_header *rom_header) { return process_oprom_list(oprom_verify_list, rom_header); @@ -419,10 +378,30 @@ int verified_boot_should_run_oprom(struct rom_header *rom_header) static void vendor_secure_prepare(void) { - printk(BIOS_SPEW, "%s: ramstage\n", __func__); - process_verify_list(payload_verify_list); + if (ENV_BOOTBLOCK) { + printk(BIOS_SPEW, "%s: bootblock\n", __func__); + verified_boot_bootblock_check(); + } + + if (ENV_ROMSTAGE) { + static int prepare_romstage = 0; + printk(BIOS_SPEW, "%s: romstage\n", __func__); + if (!prepare_romstage) { + verified_boot_early_check(); + prepare_romstage = 1; + } + } + + if (ENV_POSTCAR) { + printk(BIOS_SPEW, "%s: postcar\n", __func__); + process_verify_list(postcar_verify_list); + } + + if (ENV_RAMSTAGE) { + printk(BIOS_SPEW, "%s: ramstage\n", __func__); + process_verify_list(payload_verify_list); + } } -#endif //__RAMSTAGE__ const struct cbfs_locator cbfs_master_header_locator = { .name = "Vendorcode Header Locator", diff --git a/src/vendorcode/eltan/security/verified_boot/vboot_check.h b/src/vendorcode/eltan/security/verified_boot/vboot_check.h index 22f1edf948..36c8ffa8d3 100644 --- a/src/vendorcode/eltan/security/verified_boot/vboot_check.h +++ b/src/vendorcode/eltan/security/verified_boot/vboot_check.h @@ -32,12 +32,8 @@ /* These method verifies the SHA256 hash over the 'named' CBFS component. * 'type' denotes the type of CBFS component i.e. stage, payload or fsp. */ -#ifdef __BOOTBLOCK__ void verified_boot_bootblock_check(void); -#endif -#ifdef __ROMSTAGE__ void verified_boot_early_check(void); -#endif int verified_boot_check_manifest(void); @@ -75,4 +71,9 @@ typedef struct { void process_verify_list(const verify_item_t list[]); +extern const verify_item_t bootblock_verify_list[]; +extern const verify_item_t postcar_verify_list[]; +extern const verify_item_t payload_verify_list[]; +extern const verify_item_t oprom_verify_list[]; + #endif //VBOOT_CHECK_H From bf43f9ef13e972cb3ec7363fa6b89a96c0b7a0a0 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ky=C3=B6sti=20M=C3=A4lkki?= Date: Tue, 5 Nov 2019 17:55:15 +0200 Subject: [PATCH 0054/1242] eltan/security: Replace __BOOTBLOCK__ with ENV_BOOTBLOCK MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Change-Id: I6ec5a33cd6a6342adfe73c050e0c376bbefad96a Signed-off-by: Kyösti Mälkki Reviewed-on: https://review.coreboot.org/c/coreboot/+/36634 Tested-by: build bot (Jenkins) Reviewed-by: Wim Vervoorn Reviewed-by: Frans Hendriks --- src/vendorcode/eltan/security/verified_boot/vboot_check.c | 7 +------ 1 file changed, 1 insertion(+), 6 deletions(-) diff --git a/src/vendorcode/eltan/security/verified_boot/vboot_check.c b/src/vendorcode/eltan/security/verified_boot/vboot_check.c index fdae7b8b46..f77636b313 100644 --- a/src/vendorcode/eltan/security/verified_boot/vboot_check.c +++ b/src/vendorcode/eltan/security/verified_boot/vboot_check.c @@ -131,8 +131,6 @@ static int vendor_secure_locate(struct cbfs_props *props) return 0; } -#ifndef __BOOTBLOCK__ - /* * * measure_item @@ -168,7 +166,6 @@ static int measure_item(uint32_t pcr, uint8_t *hashData, uint32_t hashDataLen, } return status; } -#endif static void verified_boot_check_buffer(const char *name, void *start, size_t size, uint32_t hash_index, int32_t pcr) @@ -198,8 +195,7 @@ static void verified_boot_check_buffer(const char *name, void *start, size_t siz printk(BIOS_EMERG, "%s ", name); die("HASH verification failed!\n"); } else { -#ifndef __BOOTBLOCK__ - if (CONFIG(VENDORCODE_ELTAN_MBOOT)) { + if (!ENV_BOOTBLOCK && CONFIG(VENDORCODE_ELTAN_MBOOT)) { if (pcr != -1) { printk(BIOS_DEBUG, "%s: measuring %s\n", __func__, name); if (measure_item(pcr, digest, sizeof(digest), @@ -208,7 +204,6 @@ static void verified_boot_check_buffer(const char *name, void *start, size_t siz __func__); } } -#endif if (CONFIG(VENDORCODE_ELTAN_VBOOT)) printk(BIOS_DEBUG, "%s HASH verification success\n", name); } From c7fa911279a7ec6115e918ec0b630817cab932ae Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ky=C3=B6sti=20M=C3=A4lkki?= Date: Tue, 5 Nov 2019 17:57:41 +0200 Subject: [PATCH 0055/1242] eltan/security: Replace __PRE_RAM__ with ENV_ROMSTAGE_OR_BEFORE MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Change-Id: Id56a63a67b7eb70dce6687bb9c2734a711f611b3 Signed-off-by: Kyösti Mälkki Reviewed-on: https://review.coreboot.org/c/coreboot/+/36635 Reviewed-by: Wim Vervoorn Reviewed-by: Frans Hendriks Tested-by: build bot (Jenkins) --- src/vendorcode/eltan/security/verified_boot/vboot_check.c | 6 ++---- 1 file changed, 2 insertions(+), 4 deletions(-) diff --git a/src/vendorcode/eltan/security/verified_boot/vboot_check.c b/src/vendorcode/eltan/security/verified_boot/vboot_check.c index f77636b313..1dc1c3a37f 100644 --- a/src/vendorcode/eltan/security/verified_boot/vboot_check.c +++ b/src/vendorcode/eltan/security/verified_boot/vboot_check.c @@ -222,16 +222,14 @@ void verified_boot_check_cbfsfile(const char *name, uint32_t type, uint32_t hash start = cbfs_boot_map_with_leak(name, type & ~VERIFIED_BOOT_COPY_BLOCK, &size); if (start && size) { /* Speed up processing by copying the file content to memory first */ -#ifndef __PRE_RAM__ - if ((type & VERIFIED_BOOT_COPY_BLOCK) && (buffer) && (*buffer) && - ((uint32_t) start > (uint32_t)(~(CONFIG_CBFS_SIZE-1)))) { + if (!ENV_ROMSTAGE_OR_BEFORE && (type & VERIFIED_BOOT_COPY_BLOCK) && (buffer) && + (*buffer) && ((uint32_t) start > (uint32_t)(~(CONFIG_CBFS_SIZE-1)))) { printk(BIOS_DEBUG, "%s: move buffer to memory\n", __func__); /* Move the file to a memory bufferof which we know it doesn't harm */ memcpy(*buffer, start, size); start = *buffer; printk(BIOS_DEBUG, "%s: done\n", __func__); } -#endif // __PRE_RAM__ verified_boot_check_buffer(name, start, size, hash_index, pcr); } else { printk(BIOS_EMERG, "CBFS Failed to get file content for %s\n", name); From 44f1af2996c3727a3675a3dd3b7f199219e7fbf6 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ky=C3=B6sti=20M=C3=A4lkki?= Date: Wed, 6 Nov 2019 08:56:18 +0200 Subject: [PATCH 0056/1242] intel/braswell: Remove duplicate set_max_freq() prototypes MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Change-Id: I13ec9f477c64831848fb0e80b97bfbc10896c195 Signed-off-by: Kyösti Mälkki Reviewed-on: https://review.coreboot.org/c/coreboot/+/36640 Tested-by: build bot (Jenkins) Reviewed-by: Frans Hendriks --- src/soc/intel/braswell/bootblock/bootblock.c | 2 +- .../intel/braswell/include/soc/bootblock.h | 22 ------------------- src/soc/intel/braswell/include/soc/msr.h | 1 + src/soc/intel/braswell/include/soc/ramstage.h | 1 - src/soc/intel/braswell/include/soc/romstage.h | 1 - src/soc/intel/braswell/tsc_freq.c | 9 -------- 6 files changed, 2 insertions(+), 34 deletions(-) delete mode 100644 src/soc/intel/braswell/include/soc/bootblock.h diff --git a/src/soc/intel/braswell/bootblock/bootblock.c b/src/soc/intel/braswell/bootblock/bootblock.c index d8d953c8a7..53cff31569 100644 --- a/src/soc/intel/braswell/bootblock/bootblock.c +++ b/src/soc/intel/braswell/bootblock/bootblock.c @@ -20,11 +20,11 @@ #include #include #include -#include #include #include #include #include +#include #include #include diff --git a/src/soc/intel/braswell/include/soc/bootblock.h b/src/soc/intel/braswell/include/soc/bootblock.h deleted file mode 100644 index e6e25ccbb1..0000000000 --- a/src/soc/intel/braswell/include/soc/bootblock.h +++ /dev/null @@ -1,22 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2013 Google Inc. - * Copyright (C) 2015-2016 Intel Corp. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef _SOC_BOOTBLOCK_H_ -#define _SOC_BOOTBLOCK_H_ - -void set_max_freq(void); - -#endif /* _SOC_BOOTBLOCK_H_ */ diff --git a/src/soc/intel/braswell/include/soc/msr.h b/src/soc/intel/braswell/include/soc/msr.h index 6137820e9f..d0bfc8ad4a 100644 --- a/src/soc/intel/braswell/include/soc/msr.h +++ b/src/soc/intel/braswell/include/soc/msr.h @@ -41,5 +41,6 @@ /* Read BCLK from MSR */ unsigned int cpu_bus_freq_khz(void); +void set_max_freq(void); #endif /* _SOC_MSR_H_ */ diff --git a/src/soc/intel/braswell/include/soc/ramstage.h b/src/soc/intel/braswell/include/soc/ramstage.h index f197bc8e1f..17db2d8f75 100644 --- a/src/soc/intel/braswell/include/soc/ramstage.h +++ b/src/soc/intel/braswell/include/soc/ramstage.h @@ -98,7 +98,6 @@ enum { */ void soc_init_pre_device(struct soc_intel_braswell_config *config); void soc_init_cpus(struct device *dev); -void set_max_freq(void); void southcluster_enable_dev(struct device *dev); void scc_enable_acpi_mode(struct device *dev, int iosf_reg, int nvs_index); int SocStepping(void); diff --git a/src/soc/intel/braswell/include/soc/romstage.h b/src/soc/intel/braswell/include/soc/romstage.h index 9fad9bc5a0..c9b559ac35 100644 --- a/src/soc/intel/braswell/include/soc/romstage.h +++ b/src/soc/intel/braswell/include/soc/romstage.h @@ -24,7 +24,6 @@ void gfx_init(void); void punit_init(void); -void set_max_freq(void); /* romstage.c functions */ int chipset_prev_sleep_state(struct chipset_power_state *ps); diff --git a/src/soc/intel/braswell/tsc_freq.c b/src/soc/intel/braswell/tsc_freq.c index 28e3761165..923d10cfd5 100644 --- a/src/soc/intel/braswell/tsc_freq.c +++ b/src/soc/intel/braswell/tsc_freq.c @@ -17,11 +17,6 @@ #include #include #include -#if ENV_RAMSTAGE -#include -#else -#include -#endif #include static const unsigned int cpu_bus_clk_freq_table[] = { @@ -57,8 +52,6 @@ unsigned long tsc_freq_mhz(void) return (bclk_khz * ((platform_info.lo >> 8) & 0xff)) / 1000; } -#if !ENV_SMM - void set_max_freq(void) { msr_t perf_ctl; @@ -91,5 +84,3 @@ void set_max_freq(void) wrmsr(IA32_PERF_CTL, perf_ctl); } - -#endif /* ENV_SMM */ From 82c0e7e3d50cca20ed98d650d511071329e9f3a0 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ky=C3=B6sti=20M=C3=A4lkki?= Date: Tue, 5 Nov 2019 19:06:56 +0200 Subject: [PATCH 0057/1242] arch/x86: Drop some __SMM__ guards MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Change-Id: I64063bbae5b44f1f24566609a7f770c6d5f69fac Signed-off-by: Kyösti Mälkki Reviewed-on: https://review.coreboot.org/c/coreboot/+/36637 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi --- src/cpu/intel/fsp_model_406dx/model_406dx.h | 3 --- src/cpu/intel/model_2065x/model_2065x.h | 4 +--- src/cpu/intel/model_206ax/model_206ax.h | 4 +--- src/include/cpu/x86/smm.h | 2 -- src/mainboard/google/stout/ec.h | 5 +---- src/mainboard/hp/pavilion_m6_1035dx/ec.h | 2 -- src/mainboard/lenovo/g505s/ec.h | 2 -- src/mainboard/lenovo/s230u/ec.h | 2 -- src/northbridge/intel/nehalem/nehalem.h | 5 +---- src/northbridge/intel/sandybridge/sandybridge.h | 5 +---- src/soc/amd/picasso/include/soc/smi.h | 2 -- src/soc/amd/stoneyridge/include/soc/smi.h | 2 -- src/soc/intel/baytrail/include/soc/nvs.h | 3 +-- src/soc/intel/braswell/include/soc/nvs.h | 2 -- src/soc/intel/broadwell/include/soc/nvs.h | 3 +-- src/soc/intel/broadwell/include/soc/xhci.h | 2 -- src/soc/intel/denverton_ns/include/soc/nvs.h | 2 -- src/soc/intel/fsp_baytrail/include/soc/nvs.h | 3 +-- src/southbridge/amd/agesa/hudson/smi.h | 2 -- src/southbridge/amd/pi/hudson/smi.h | 2 -- src/southbridge/intel/bd82x6x/nvs.h | 2 -- src/southbridge/intel/fsp_rangeley/nvs.h | 3 +-- src/southbridge/intel/ibexpeak/nvs.h | 3 +-- src/southbridge/intel/lynxpoint/nvs.h | 2 -- 24 files changed, 10 insertions(+), 57 deletions(-) diff --git a/src/cpu/intel/fsp_model_406dx/model_406dx.h b/src/cpu/intel/fsp_model_406dx/model_406dx.h index 140dc2e4bf..adfec562ef 100644 --- a/src/cpu/intel/fsp_model_406dx/model_406dx.h +++ b/src/cpu/intel/fsp_model_406dx/model_406dx.h @@ -79,12 +79,9 @@ #define PSS_LATENCY_BUSMASTER 10 #ifndef __ROMCC__ -#ifdef __SMM__ /* Lock MSRs */ void intel_model_406dx_finalize_smm(void); -#else int cpu_config_tdp_levels(void); #endif -#endif #endif /* _CPU_INTEL_MODEL_406DX_H */ diff --git a/src/cpu/intel/model_2065x/model_2065x.h b/src/cpu/intel/model_2065x/model_2065x.h index 8087edb828..f6982d9ee9 100644 --- a/src/cpu/intel/model_2065x/model_2065x.h +++ b/src/cpu/intel/model_2065x/model_2065x.h @@ -69,14 +69,12 @@ #define PSS_LATENCY_TRANSITION 10 #define PSS_LATENCY_BUSMASTER 10 -#ifdef __SMM__ /* Lock MSRs */ void intel_model_2065x_finalize_smm(void); -#else + /* Configure power limits for turbo mode */ void set_power_limits(u8 power_limit_1_time); int cpu_config_tdp_levels(void); -#endif /* Sanity check config options. */ #if (CONFIG_SMM_TSEG_SIZE <= CONFIG_SMM_RESERVED_SIZE) diff --git a/src/cpu/intel/model_206ax/model_206ax.h b/src/cpu/intel/model_206ax/model_206ax.h index f2a0b71a5b..7017c128cb 100644 --- a/src/cpu/intel/model_206ax/model_206ax.h +++ b/src/cpu/intel/model_206ax/model_206ax.h @@ -93,14 +93,12 @@ # error "CONFIG_IED_REGION_SIZE is not a power of 2" #endif -#ifdef __SMM__ /* Lock MSRs */ void intel_model_206ax_finalize_smm(void); -#else + /* Configure power limits for turbo mode */ void set_power_limits(u8 power_limit_1_time); int cpu_config_tdp_levels(void); -#endif int get_platform_id(void); #endif diff --git a/src/include/cpu/x86/smm.h b/src/include/cpu/x86/smm.h index d8b9efeaa9..cf107b121a 100644 --- a/src/include/cpu/x86/smm.h +++ b/src/include/cpu/x86/smm.h @@ -86,7 +86,6 @@ struct smm_module_params { /* smm_handler_t is called with arg of smm_module_params pointer. */ typedef asmlinkage void (*smm_handler_t)(void *); -#ifdef __SMM__ /* SMM Runtime helpers. */ /* Entry point for SMM modules. */ @@ -95,7 +94,6 @@ asmlinkage void smm_handler_start(void *params); /* Retrieve SMM save state for a given CPU. WARNING: This does not take into * account CPUs which are configured to not save their state to RAM. */ void *smm_get_save_state(int cpu); -#endif /* __SMM__ */ /* SMM Module Loading API */ diff --git a/src/mainboard/google/stout/ec.h b/src/mainboard/google/stout/ec.h index 8c7882f565..f035e246be 100644 --- a/src/mainboard/google/stout/ec.h +++ b/src/mainboard/google/stout/ec.h @@ -22,10 +22,7 @@ #define EC_SMI_LID_CLOSED 0x2B #ifndef __ACPI__ -extern void stout_ec_init(void); -#endif - -#ifdef __SMM__ +void stout_ec_init(void); void stout_ec_finalize_smm(void); #endif diff --git a/src/mainboard/hp/pavilion_m6_1035dx/ec.h b/src/mainboard/hp/pavilion_m6_1035dx/ec.h index 40e33ee724..55672513e5 100644 --- a/src/mainboard/hp/pavilion_m6_1035dx/ec.h +++ b/src/mainboard/hp/pavilion_m6_1035dx/ec.h @@ -19,8 +19,6 @@ #include "mainboard.h" -#ifndef __SMM__ void pavilion_m6_1035dx_ec_init(void); -#endif #endif /* _MAINBOARD_HP_PAVILION_M6_1035DX_EC_H */ diff --git a/src/mainboard/lenovo/g505s/ec.h b/src/mainboard/lenovo/g505s/ec.h index 86fd673fa8..52a3ab71d8 100644 --- a/src/mainboard/lenovo/g505s/ec.h +++ b/src/mainboard/lenovo/g505s/ec.h @@ -19,8 +19,6 @@ #include "mainboard.h" -#ifndef __SMM__ void lenovo_g505s_ec_init(void); -#endif #endif /* _MAINBOARD_LENOVO_G505S_EC_H */ diff --git a/src/mainboard/lenovo/s230u/ec.h b/src/mainboard/lenovo/s230u/ec.h index 87fbc7f40e..a5bc4236ff 100644 --- a/src/mainboard/lenovo/s230u/ec.h +++ b/src/mainboard/lenovo/s230u/ec.h @@ -17,9 +17,7 @@ #ifndef _MAINBOARD_LENOVO_S230U_EC_H #define _MAINBOARD_LENOVO_S230U_EC_H -#ifndef __SMM__ void lenovo_s230u_ec_init(void); -#endif #define ECMM(x) (*((volatile u8 *)(CONFIG_EC_BASE_ADDRESS + x))) #define ec_mm_read(addr) (ECMM(0x100 + addr)) diff --git a/src/northbridge/intel/nehalem/nehalem.h b/src/northbridge/intel/nehalem/nehalem.h index ebec63d898..493c5b14cd 100644 --- a/src/northbridge/intel/nehalem/nehalem.h +++ b/src/northbridge/intel/nehalem/nehalem.h @@ -249,17 +249,14 @@ typedef struct { #define PCI_DEVICE_ID_SB 0x0104 #define PCI_DEVICE_ID_IB 0x0154 -#ifdef __SMM__ void intel_nehalem_finalize_smm(void); -#else /* !__SMM__ */ + int bridge_silicon_revision(void); void nehalem_early_initialization(int chipset_type); void nehalem_late_initialization(void); void mainboard_pre_raminit(void); void mainboard_get_spd_map(u8 *spd_addrmap); -#endif /* !__SMM__ */ - #endif #endif #endif /* __NORTHBRIDGE_INTEL_NEHALEM_NEHALEM_H__ */ diff --git a/src/northbridge/intel/sandybridge/sandybridge.h b/src/northbridge/intel/sandybridge/sandybridge.h index 8664c5d311..31d4358e7b 100644 --- a/src/northbridge/intel/sandybridge/sandybridge.h +++ b/src/northbridge/intel/sandybridge/sandybridge.h @@ -203,9 +203,8 @@ enum platform_type { #ifndef __ASSEMBLER__ -#ifdef __SMM__ void intel_sandybridge_finalize_smm(void); -#else /* !__SMM__ */ + int bridge_silicon_revision(void); void systemagent_early_init(void); void sandybridge_init_iommu(void); @@ -213,8 +212,6 @@ void sandybridge_late_initialization(void); void northbridge_romstage_finalize(int s3resume); void early_init_dmi(void); -#endif /* !__SMM__ */ - void pch_enable_lpc(void); void mainboard_early_init(int s3resume); void mainboard_config_superio(void); diff --git a/src/soc/amd/picasso/include/soc/smi.h b/src/soc/amd/picasso/include/soc/smi.h index 66c205096e..e7f9da6d9c 100644 --- a/src/soc/amd/picasso/include/soc/smi.h +++ b/src/soc/amd/picasso/include/soc/smi.h @@ -232,8 +232,6 @@ void disable_gevent_smi(uint8_t gevent); void gpe_configure_sci(const struct sci_source *scis, size_t num_gpes); void soc_route_sci(uint8_t event); -#ifndef __SMM__ void enable_smi_generation(void); -#endif #endif /* __SOUTHBRIDGE_AMD_PI_PICASSO_SMI_H__ */ diff --git a/src/soc/amd/stoneyridge/include/soc/smi.h b/src/soc/amd/stoneyridge/include/soc/smi.h index 000eed8554..5301dd72a0 100644 --- a/src/soc/amd/stoneyridge/include/soc/smi.h +++ b/src/soc/amd/stoneyridge/include/soc/smi.h @@ -235,8 +235,6 @@ void disable_gevent_smi(uint8_t gevent); void gpe_configure_sci(const struct sci_source *scis, size_t num_gpes); void soc_route_sci(uint8_t event); -#ifndef __SMM__ void enable_smi_generation(void); -#endif #endif /* __SOUTHBRIDGE_AMD_PI_STONEYRIDGE_SMI_H__ */ diff --git a/src/soc/intel/baytrail/include/soc/nvs.h b/src/soc/intel/baytrail/include/soc/nvs.h index 08ccbf44ff..4a89eb967e 100644 --- a/src/soc/intel/baytrail/include/soc/nvs.h +++ b/src/soc/intel/baytrail/include/soc/nvs.h @@ -104,9 +104,8 @@ typedef struct global_nvs_t { check_member(global_nvs_t, chromeos, GNVS_CHROMEOS_ACPI_OFFSET); void acpi_create_gnvs(global_nvs_t *gnvs); -#ifdef __SMM__ + /* Used in SMM to find the ACPI GNVS address */ global_nvs_t *smm_get_gnvs(void); -#endif #endif /* _BAYTRAIL_NVS_H_ */ diff --git a/src/soc/intel/braswell/include/soc/nvs.h b/src/soc/intel/braswell/include/soc/nvs.h index d2dc70659e..33800ef8fd 100644 --- a/src/soc/intel/braswell/include/soc/nvs.h +++ b/src/soc/intel/braswell/include/soc/nvs.h @@ -107,9 +107,7 @@ typedef struct global_nvs_t { check_member(global_nvs_t, chromeos, GNVS_CHROMEOS_ACPI_OFFSET); void acpi_create_gnvs(global_nvs_t *gnvs); -#if ENV_SMM /* Used in SMM to find the ACPI GNVS address */ global_nvs_t *smm_get_gnvs(void); -#endif #endif /* _SOC_NVS_H_ */ diff --git a/src/soc/intel/broadwell/include/soc/nvs.h b/src/soc/intel/broadwell/include/soc/nvs.h index 63c7bde23b..456fda6fa6 100644 --- a/src/soc/intel/broadwell/include/soc/nvs.h +++ b/src/soc/intel/broadwell/include/soc/nvs.h @@ -96,9 +96,8 @@ typedef struct global_nvs_t { check_member(global_nvs_t, chromeos, GNVS_CHROMEOS_ACPI_OFFSET); void acpi_create_gnvs(global_nvs_t *gnvs); -#ifdef __SMM__ + /* Used in SMM to find the ACPI GNVS address */ global_nvs_t *smm_get_gnvs(void); -#endif #endif diff --git a/src/soc/intel/broadwell/include/soc/xhci.h b/src/soc/intel/broadwell/include/soc/xhci.h index 33e4c2dd06..87a59345da 100644 --- a/src/soc/intel/broadwell/include/soc/xhci.h +++ b/src/soc/intel/broadwell/include/soc/xhci.h @@ -50,8 +50,6 @@ #define XHCI_PLSR_POLLING (7 << 5) /* Port is polling */ #define XHCI_PLSW_ENABLE (5 << 5) /* Transition from disabled */ -#ifdef __SMM__ void usb_xhci_sleep_prepare(pci_devfn_t dev, u8 slp_typ); -#endif #endif diff --git a/src/soc/intel/denverton_ns/include/soc/nvs.h b/src/soc/intel/denverton_ns/include/soc/nvs.h index 5a94b24bb6..8d1bc6a703 100644 --- a/src/soc/intel/denverton_ns/include/soc/nvs.h +++ b/src/soc/intel/denverton_ns/include/soc/nvs.h @@ -65,9 +65,7 @@ typedef struct global_nvs_t { } __packed global_nvs_t; -#ifdef __SMM__ /* Used in SMM to find the ACPI GNVS address */ global_nvs_t *smm_get_gnvs(void); -#endif #endif /* _DENVERTON_NS_NVS_H_ */ diff --git a/src/soc/intel/fsp_baytrail/include/soc/nvs.h b/src/soc/intel/fsp_baytrail/include/soc/nvs.h index d42763a5ac..df2fc60d71 100644 --- a/src/soc/intel/fsp_baytrail/include/soc/nvs.h +++ b/src/soc/intel/fsp_baytrail/include/soc/nvs.h @@ -65,9 +65,8 @@ typedef struct { } __packed global_nvs_t; void acpi_create_gnvs(global_nvs_t *gnvs); -#ifdef __SMM__ + /* Used in SMM to find the ACPI GNVS address */ global_nvs_t *smm_get_gnvs(void); -#endif #endif /* _BAYTRAIL_NVS_H_ */ diff --git a/src/southbridge/amd/agesa/hudson/smi.h b/src/southbridge/amd/agesa/hudson/smi.h index d1594f3da8..5e0c09a8e0 100644 --- a/src/southbridge/amd/agesa/hudson/smi.h +++ b/src/southbridge/amd/agesa/hudson/smi.h @@ -71,8 +71,6 @@ void hudson_configure_gevent_smi(uint8_t gevent, uint8_t mode, uint8_t level); void hudson_disable_gevent_smi(uint8_t gevent); void hudson_enable_acpi_cmd_smi(void); -#ifndef __SMM__ void hudson_enable_smi_generation(void); -#endif #endif /* _SOUTHBRIDGE_AMD_AGESA_HUDSON_SMI_H */ diff --git a/src/southbridge/amd/pi/hudson/smi.h b/src/southbridge/amd/pi/hudson/smi.h index dde9d6e4a7..684dca51c2 100644 --- a/src/southbridge/amd/pi/hudson/smi.h +++ b/src/southbridge/amd/pi/hudson/smi.h @@ -71,8 +71,6 @@ void hudson_configure_gevent_smi(uint8_t gevent, uint8_t mode, uint8_t level); void hudson_disable_gevent_smi(uint8_t gevent); void hudson_enable_acpi_cmd_smi(void); -#ifndef __SMM__ void hudson_enable_smi_generation(void); -#endif #endif /* _SOUTHBRIDGE_AMD_PI_HUDSON_SMI_H */ diff --git a/src/southbridge/intel/bd82x6x/nvs.h b/src/southbridge/intel/bd82x6x/nvs.h index 655851105e..a6b0bdbc55 100644 --- a/src/southbridge/intel/bd82x6x/nvs.h +++ b/src/southbridge/intel/bd82x6x/nvs.h @@ -155,8 +155,6 @@ typedef struct global_nvs_t { } __packed global_nvs_t; check_member(global_nvs_t, chromeos, GNVS_CHROMEOS_ACPI_OFFSET); -#ifdef __SMM__ /* Used in SMM to find the ACPI GNVS address */ global_nvs_t *smm_get_gnvs(void); -#endif void acpi_create_gnvs(global_nvs_t *gnvs); diff --git a/src/southbridge/intel/fsp_rangeley/nvs.h b/src/southbridge/intel/fsp_rangeley/nvs.h index 12de76999d..47fca685ce 100644 --- a/src/southbridge/intel/fsp_rangeley/nvs.h +++ b/src/southbridge/intel/fsp_rangeley/nvs.h @@ -146,7 +146,6 @@ typedef struct { } __packed global_nvs_t; void acpi_create_gnvs(global_nvs_t *gnvs); -#ifdef __SMM__ + /* Used in SMM to find the ACPI GNVS address */ global_nvs_t *smm_get_gnvs(void); -#endif diff --git a/src/southbridge/intel/ibexpeak/nvs.h b/src/southbridge/intel/ibexpeak/nvs.h index 36db12c043..a95639894f 100644 --- a/src/southbridge/intel/ibexpeak/nvs.h +++ b/src/southbridge/intel/ibexpeak/nvs.h @@ -153,8 +153,7 @@ typedef struct global_nvs_t { } __packed global_nvs_t; check_member(global_nvs_t, chromeos, GNVS_CHROMEOS_ACPI_OFFSET); -#ifdef __SMM__ /* Used in SMM to find the ACPI GNVS address */ global_nvs_t *smm_get_gnvs(void); -#endif + void acpi_create_gnvs(global_nvs_t *gnvs); diff --git a/src/southbridge/intel/lynxpoint/nvs.h b/src/southbridge/intel/lynxpoint/nvs.h index a8f0dea83c..3aca7bbda3 100644 --- a/src/southbridge/intel/lynxpoint/nvs.h +++ b/src/southbridge/intel/lynxpoint/nvs.h @@ -130,9 +130,7 @@ typedef struct global_nvs_t { } __packed global_nvs_t; check_member(global_nvs_t, chromeos, GNVS_CHROMEOS_ACPI_OFFSET); -#ifdef __SMM__ /* Used in SMM to find the ACPI GNVS address */ global_nvs_t *smm_get_gnvs(void); -#endif void acpi_create_gnvs(global_nvs_t * gnvs); From c86fc8e63d81251a5da80ed55e4fbc9900a900d9 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ky=C3=B6sti=20M=C3=A4lkki?= Date: Wed, 6 Nov 2019 06:32:27 +0200 Subject: [PATCH 0058/1242] sb,soc/intel: Reduce preprocessor use with ME debugging MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Change-Id: Iedd54730f140b6a7a40834f00d558ed99a345077 Signed-off-by: Kyösti Mälkki Reviewed-on: https://review.coreboot.org/c/coreboot/+/36639 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi --- src/soc/intel/broadwell/include/soc/me.h | 4 -- src/soc/intel/broadwell/me.c | 26 ++++----- src/soc/intel/broadwell/me_status.c | 6 +-- src/southbridge/intel/bd82x6x/me.c | 25 ++++----- src/southbridge/intel/bd82x6x/me_8.x.c | 22 ++++---- src/southbridge/intel/bd82x6x/me_status.c | 7 ++- src/southbridge/intel/ibexpeak/me.c | 7 ++- src/southbridge/intel/lynxpoint/me_9.x.c | 59 +++++++++------------ src/southbridge/intel/lynxpoint/me_status.c | 7 ++- 9 files changed, 70 insertions(+), 93 deletions(-) diff --git a/src/soc/intel/broadwell/include/soc/me.h b/src/soc/intel/broadwell/include/soc/me.h index a213e37047..69b75b49a0 100644 --- a/src/soc/intel/broadwell/include/soc/me.h +++ b/src/soc/intel/broadwell/include/soc/me.h @@ -493,11 +493,7 @@ struct me_fwcaps { void intel_me_hsio_version(uint16_t *version, uint16_t *checksum); -#if (CONFIG_DEFAULT_CONSOLE_LOGLEVEL >= BIOS_DEBUG) /* Defined in me_status.c for both romstage and ramstage */ void intel_me_status(void); -#else -static inline void intel_me_status(void) { } -#endif #endif diff --git a/src/soc/intel/broadwell/me.c b/src/soc/intel/broadwell/me.c index 6be17489e1..0461428ba5 100644 --- a/src/soc/intel/broadwell/me.c +++ b/src/soc/intel/broadwell/me.c @@ -58,11 +58,13 @@ static const char *me_bios_path_values[] = { /* MMIO base address for MEI interface */ static u8 *mei_base_address; -#if CONFIG(DEBUG_INTEL_ME) static void mei_dump(void *ptr, int dword, int offset, const char *type) { struct mei_csr *csr; + if (!CONFIG(DEBUG_INTEL_ME)) + return; + printk(BIOS_SPEW, "%-9s[%02x] : ", type, offset); switch (offset) { @@ -88,9 +90,6 @@ static void mei_dump(void *ptr, int dword, int offset, const char *type) break; } } -#else -# define mei_dump(ptr, dword, offset, type) do {} while (0) -#endif /* * ME/MEI access helpers using memcpy to avoid aliasing. @@ -483,7 +482,6 @@ static void me_print_fw_version(mbp_fw_version_name *vers_name) vers_name->hotfix_version, vers_name->build_version); } -#if CONFIG(DEBUG_INTEL_ME) static inline void print_cap(const char *name, int state) { printk(BIOS_DEBUG, "ME Capability: %-41s : %sabled\n", @@ -536,7 +534,6 @@ static void me_print_fwcaps(mbp_mefwcaps *cap) print_cap("TLS", cap->tls); print_cap("Wireless LAN (WLAN)", cap->wlan); } -#endif /* Send END OF POST message to the ME */ static int mkhi_end_of_post(void) @@ -804,9 +801,8 @@ static void intel_me_print_mbp(me_bios_payload *mbp_data) { me_print_fw_version(mbp_data->fw_version_name); -#if CONFIG(DEBUG_INTEL_ME) - me_print_fwcaps(mbp_data->fw_capabilities); -#endif + if (CONFIG(DEBUG_INTEL_ME)) + me_print_fwcaps(mbp_data->fw_capabilities); if (mbp_data->plat_time) { printk(BIOS_DEBUG, "ME: Wake Event to ME Reset: %u ms\n", @@ -912,12 +908,12 @@ static int intel_me_read_mbp(me_bios_payload *mbp_data, struct device *dev) } /* Dump out the MBP contents. */ -#if CONFIG(DEBUG_INTEL_ME) - printk(BIOS_INFO, "ME MBP: Header: items: %d, size dw: %d\n", - mbp->header.num_entries, mbp->header.mbp_size); - for (i = 0; i < mbp->header.mbp_size - 1; i++) - printk(BIOS_INFO, "ME MBP: %04x: 0x%08x\n", i, mbp->data[i]); -#endif + if (CONFIG(DEBUG_INTEL_ME)) { + printk(BIOS_INFO, "ME MBP: Header: items: %d, size dw: %d\n", + mbp->header.num_entries, mbp->header.mbp_size); + for (i = 0; i < mbp->header.mbp_size - 1; i++) + printk(BIOS_INFO, "ME MBP: %04x: 0x%08x\n", i, mbp->data[i]); + } #define ASSIGN_FIELD_PTR(field_, val_) \ { \ diff --git a/src/soc/intel/broadwell/me_status.c b/src/soc/intel/broadwell/me_status.c index 08fd48f845..1880da158b 100644 --- a/src/soc/intel/broadwell/me_status.c +++ b/src/soc/intel/broadwell/me_status.c @@ -34,8 +34,6 @@ static inline void me_read_dword_ptr(void *ptr, int offset) memcpy(ptr, &dword, sizeof(dword)); } -#if (CONFIG_DEFAULT_CONSOLE_LOGLEVEL >= BIOS_DEBUG) - /* HFS1[3:0] Current Working State Values */ static const char *me_cws_values[] = { [ME_HFS_CWS_RESET] = "Reset", @@ -210,6 +208,9 @@ static const char *me_progress_policy_values[] = { void intel_me_status(void) { + if (CONFIG_DEFAULT_CONSOLE_LOGLEVEL < BIOS_DEBUG) + return; + struct me_hfs _hfs, *hfs = &_hfs; struct me_hfs2 _hfs2, *hfs2 = &_hfs2; @@ -302,7 +303,6 @@ void intel_me_status(void) } printk(BIOS_DEBUG, "\n"); } -#endif void intel_me_hsio_version(uint16_t *version, uint16_t *checksum) { diff --git a/src/southbridge/intel/bd82x6x/me.c b/src/southbridge/intel/bd82x6x/me.c index ea60085624..5e355a110f 100644 --- a/src/southbridge/intel/bd82x6x/me.c +++ b/src/southbridge/intel/bd82x6x/me.c @@ -60,11 +60,13 @@ static const char *me_bios_path_values[] = { /* MMIO base address for MEI interface */ static u32 *mei_base_address; -#if CONFIG(DEBUG_INTEL_ME) static void mei_dump(void *ptr, int dword, int offset, const char *type) { struct mei_csr *csr; + if (!CONFIG(DEBUG_INTEL_ME)) + return; + printk(BIOS_SPEW, "%-9s[%02x] : ", type, offset); switch (offset) { @@ -90,9 +92,6 @@ static void mei_dump(void *ptr, int dword, int offset, const char *type) break; } } -#else -# define mei_dump(ptr,dword,offset,type) do {} while (0) -#endif /* * ME/MEI access helpers using memcpy to avoid aliasing. @@ -373,9 +372,8 @@ static int mkhi_end_of_post(void) } #endif -#if (CONFIG_DEFAULT_CONSOLE_LOGLEVEL >= BIOS_DEBUG) && !defined(__SMM__) /* Get ME firmware version */ -static int mkhi_get_fw_version(void) +static int __unused mkhi_get_fw_version(void) { struct me_fw_version version; struct mkhi_header mkhi = { @@ -412,7 +410,7 @@ static inline void print_cap(const char *name, int state) } /* Get ME Firmware Capabilities */ -static int mkhi_get_fwcaps(void) +static int __unused mkhi_get_fwcaps(void) { u32 rule_id = 0; struct me_fwcaps cap; @@ -454,7 +452,6 @@ static int mkhi_get_fwcaps(void) return 0; } -#endif #if CONFIG(CHROMEOS) && 0 /* DISABLED */ /* Tell ME to issue a global reset */ @@ -714,12 +711,12 @@ static void intel_me_init(struct device *dev) if (intel_mei_setup(dev) < 0) break; -#if (CONFIG_DEFAULT_CONSOLE_LOGLEVEL >= BIOS_DEBUG) - /* Print ME firmware version */ - mkhi_get_fw_version(); - /* Print ME firmware capabilities */ - mkhi_get_fwcaps(); -#endif + if (CONFIG_DEFAULT_CONSOLE_LOGLEVEL >= BIOS_DEBUG) { + /* Print ME firmware version */ + mkhi_get_fw_version(); + /* Print ME firmware capabilities */ + mkhi_get_fwcaps(); + } /* * Leave the ME unlocked in this path. diff --git a/src/southbridge/intel/bd82x6x/me_8.x.c b/src/southbridge/intel/bd82x6x/me_8.x.c index 54c3fff05c..c224cb4903 100644 --- a/src/southbridge/intel/bd82x6x/me_8.x.c +++ b/src/southbridge/intel/bd82x6x/me_8.x.c @@ -62,11 +62,14 @@ static int intel_me_read_mbp(me_bios_payload *mbp_data); /* MMIO base address for MEI interface */ static u32 *mei_base_address; -#if CONFIG(DEBUG_INTEL_ME) + static void mei_dump(void *ptr, int dword, int offset, const char *type) { struct mei_csr *csr; + if (!CONFIG(DEBUG_INTEL_ME)) + return; + printk(BIOS_SPEW, "%-9s[%02x] : ", type, offset); switch (offset) { @@ -92,9 +95,6 @@ static void mei_dump(void *ptr, int dword, int offset, const char *type) break; } } -#else -# define mei_dump(ptr,dword,offset,type) do {} while (0) -#endif /* * ME/MEI access helpers using memcpy to avoid aliasing. @@ -350,14 +350,13 @@ static inline int mei_sendrecv(struct mei_header *mei, struct mkhi_header *mkhi, return 0; } -#if (CONFIG_DEFAULT_CONSOLE_LOGLEVEL >= BIOS_DEBUG) && !defined(__SMM__) static inline void print_cap(const char *name, int state) { printk(BIOS_DEBUG, "ME Capability: %-41s : %sabled\n", name, state ? " en" : "dis"); } -static void me_print_fw_version(mbp_fw_version_name *vers_name) +static void __unused me_print_fw_version(mbp_fw_version_name *vers_name) { if (!vers_name->major_version) { printk(BIOS_ERR, "ME: mbp missing version report\n"); @@ -395,7 +394,7 @@ static int mkhi_get_fwcaps(mefwcaps_sku *cap) } /* Get ME Firmware Capabilities */ -static void me_print_fwcaps(mbp_fw_caps *caps_section) +static void __unused me_print_fwcaps(mbp_fw_caps *caps_section) { mefwcaps_sku *cap = &caps_section->fw_capabilities; if (!caps_section->available) { @@ -421,7 +420,6 @@ static void me_print_fwcaps(mbp_fw_caps *caps_section) print_cap("TLS", cap->tls); print_cap("Wireless LAN (WLAN)", cap->wlan); } -#endif #if CONFIG(CHROMEOS) && 0 /* DISABLED */ /* Tell ME to issue a global reset */ @@ -719,10 +717,10 @@ static void intel_me_init(struct device *dev) } #endif -#if (CONFIG_DEFAULT_CONSOLE_LOGLEVEL >= BIOS_DEBUG) - me_print_fw_version(&mbp_data.fw_version_name); - me_print_fwcaps(&mbp_data.fw_caps_sku); -#endif + if (CONFIG_DEFAULT_CONSOLE_LOGLEVEL >= BIOS_DEBUG) { + me_print_fw_version(&mbp_data.fw_version_name); + me_print_fwcaps(&mbp_data.fw_caps_sku); + } /* * Leave the ME unlocked in this path. diff --git a/src/southbridge/intel/bd82x6x/me_status.c b/src/southbridge/intel/bd82x6x/me_status.c index b202376653..4d9540a074 100644 --- a/src/southbridge/intel/bd82x6x/me_status.c +++ b/src/southbridge/intel/bd82x6x/me_status.c @@ -18,7 +18,6 @@ #include #include "me.h" -#if (CONFIG_DEFAULT_CONSOLE_LOGLEVEL >= BIOS_DEBUG) /* HFS1[3:0] Current Working State Values */ static const char *me_cws_values[] = { [ME_HFS_CWS_RESET] = "Reset", @@ -137,11 +136,12 @@ static const char *me_progress_policy_values[] = { [0x0f] = "ME cannot access the chipset descriptor region", [0x10] = "Required VSCC values for flash parts do not match", }; -#endif void intel_me_status(struct me_hfs *hfs, struct me_gmes *gmes) { -#if (CONFIG_DEFAULT_CONSOLE_LOGLEVEL >= BIOS_DEBUG) + if (CONFIG_DEFAULT_CONSOLE_LOGLEVEL < BIOS_DEBUG) + return; + /* Check Current States */ printk(BIOS_DEBUG, "ME: FW Partition Table : %s\n", hfs->fpt_bad ? "BAD" : "OK"); @@ -204,5 +204,4 @@ void intel_me_status(struct me_hfs *hfs, struct me_gmes *gmes) printk(BIOS_DEBUG, "Unknown 0x%02x", gmes->current_state); } printk(BIOS_DEBUG, "\n"); -#endif } diff --git a/src/southbridge/intel/ibexpeak/me.c b/src/southbridge/intel/ibexpeak/me.c index f804126654..c944f63ee1 100644 --- a/src/southbridge/intel/ibexpeak/me.c +++ b/src/southbridge/intel/ibexpeak/me.c @@ -59,11 +59,13 @@ static const char *me_bios_path_values[] = { /* MMIO base address for MEI interface */ static u32 *mei_base_address; -#if CONFIG(DEBUG_INTEL_ME) static void mei_dump(void *ptr, int dword, int offset, const char *type) { struct mei_csr *csr; + if (!CONFIG(DEBUG_INTEL_ME)) + return; + printk(BIOS_SPEW, "%-9s[%02x] : ", type, offset); switch (offset) { @@ -89,9 +91,6 @@ static void mei_dump(void *ptr, int dword, int offset, const char *type) break; } } -#else -# define mei_dump(ptr,dword,offset,type) do {} while (0) -#endif /* * ME/MEI access helpers using memcpy to avoid aliasing. diff --git a/src/southbridge/intel/lynxpoint/me_9.x.c b/src/southbridge/intel/lynxpoint/me_9.x.c index 59a8666547..1c45e2d99b 100644 --- a/src/southbridge/intel/lynxpoint/me_9.x.c +++ b/src/southbridge/intel/lynxpoint/me_9.x.c @@ -66,11 +66,13 @@ void intel_me_mbp_clear(pci_devfn_t dev); void intel_me_mbp_clear(struct device *dev); #endif -#if CONFIG(DEBUG_INTEL_ME) static void mei_dump(void *ptr, int dword, int offset, const char *type) { struct mei_csr *csr; + if (!CONFIG(DEBUG_INTEL_ME)) + return; + printk(BIOS_SPEW, "%-9s[%02x] : ", type, offset); switch (offset) { @@ -96,9 +98,6 @@ static void mei_dump(void *ptr, int dword, int offset, const char *type) break; } } -#else -# define mei_dump(ptr,dword,offset,type) do {} while (0) -#endif /* * ME/MEI access helpers using memcpy to avoid aliasing. @@ -380,7 +379,6 @@ static int mei_recv_msg(void *header, int header_bytes, return mei_wait_for_me_ready(); } -#if CONFIG(DEBUG_INTEL_ME) || defined(__SMM__) static inline int mei_sendrecv_mkhi(struct mkhi_header *mkhi, void *req_data, int req_bytes, void *rsp_data, int rsp_bytes) @@ -418,7 +416,6 @@ static inline int mei_sendrecv_mkhi(struct mkhi_header *mkhi, return 0; } -#endif /* CONFIG_DEBUG_INTEL_ME || __SMM__ */ /* * mbp give up routine. This path is taken if hfs.mpb_rdy is 0 or the read @@ -469,8 +466,7 @@ void intel_me_mbp_clear(struct device *dev) } } -#if (CONFIG_DEFAULT_CONSOLE_LOGLEVEL >= BIOS_DEBUG) && !defined(__SMM__) -static void me_print_fw_version(mbp_fw_version_name *vers_name) +static void __unused me_print_fw_version(mbp_fw_version_name *vers_name) { if (!vers_name) { printk(BIOS_ERR, "ME: mbp missing version report\n"); @@ -482,7 +478,6 @@ static void me_print_fw_version(mbp_fw_version_name *vers_name) vers_name->hotfix_version, vers_name->build_version); } -#if CONFIG(DEBUG_INTEL_ME) static inline void print_cap(const char *name, int state) { printk(BIOS_DEBUG, "ME Capability: %-41s : %sabled\n", @@ -510,7 +505,7 @@ static int mkhi_get_fwcaps(mbp_mefwcaps *cap) } /* Get ME Firmware Capabilities */ -static void me_print_fwcaps(mbp_mefwcaps *cap) +static void __unused me_print_fwcaps(mbp_mefwcaps *cap) { mbp_mefwcaps local_caps; if (!cap) { @@ -535,8 +530,6 @@ static void me_print_fwcaps(mbp_mefwcaps *cap) print_cap("TLS", cap->tls); print_cap("Wireless LAN (WLAN)", cap->wlan); } -#endif /* CONFIG_DEBUG_INTEL_ME */ -#endif #if CONFIG(CHROMEOS) && 0 /* DISABLED */ /* Tell ME to issue a global reset */ @@ -851,21 +844,21 @@ static void intel_me_init(struct device *dev) if (intel_me_read_mbp(&mbp_data, dev)) return; -#if (CONFIG_DEFAULT_CONSOLE_LOGLEVEL >= BIOS_DEBUG) - me_print_fw_version(mbp_data.fw_version_name); -#if CONFIG(DEBUG_INTEL_ME) - me_print_fwcaps(mbp_data.fw_capabilities); -#endif + if (CONFIG_DEFAULT_CONSOLE_LOGLEVEL >= BIOS_DEBUG) { + me_print_fw_version(mbp_data.fw_version_name); - if (mbp_data.plat_time) { - printk(BIOS_DEBUG, "ME: Wake Event to ME Reset: %u ms\n", - mbp_data.plat_time->wake_event_mrst_time_ms); - printk(BIOS_DEBUG, "ME: ME Reset to Platform Reset: %u ms\n", - mbp_data.plat_time->mrst_pltrst_time_ms); - printk(BIOS_DEBUG, "ME: Platform Reset to CPU Reset: %u ms\n", - mbp_data.plat_time->pltrst_cpurst_time_ms); + if (CONFIG(DEBUG_INTEL_ME)) + me_print_fwcaps(mbp_data.fw_capabilities); + + if (mbp_data.plat_time) { + printk(BIOS_DEBUG, "ME: Wake Event to ME Reset: %u ms\n", + mbp_data.plat_time->wake_event_mrst_time_ms); + printk(BIOS_DEBUG, "ME: ME Reset to Platform Reset: %u ms\n", + mbp_data.plat_time->mrst_pltrst_time_ms); + printk(BIOS_DEBUG, "ME: Platform Reset to CPU Reset: %u ms\n", + mbp_data.plat_time->pltrst_cpurst_time_ms); + } } -#endif /* Set clock enables according to devicetree */ if (config && config->icc_clock_disable) @@ -1004,15 +997,15 @@ static int intel_me_read_mbp(me_bios_payload *mbp_data, struct device *dev) #endif /* Dump out the MBP contents. */ -#if (CONFIG_DEFAULT_CONSOLE_LOGLEVEL >= BIOS_DEBUG) - printk(BIOS_INFO, "ME MBP: Header: items: %d, size dw: %d\n", - mbp->header.num_entries, mbp->header.mbp_size); -#if CONFIG(DEBUG_INTEL_ME) - for (i = 0; i < mbp->header.mbp_size - 1; i++) { - printk(BIOS_INFO, "ME MBP: %04x: 0x%08x\n", i, mbp->data[i]); + if (CONFIG_DEFAULT_CONSOLE_LOGLEVEL >= BIOS_DEBUG) { + printk(BIOS_INFO, "ME MBP: Header: items: %d, size dw: %d\n", + mbp->header.num_entries, mbp->header.mbp_size); + if (CONFIG(DEBUG_INTEL_ME)) { + for (i = 0; i < mbp->header.mbp_size - 1; i++) { + printk(BIOS_INFO, "ME MBP: %04x: 0x%08x\n", i, mbp->data[i]); + } + } } -#endif -#endif #define ASSIGN_FIELD_PTR(field_,val_) \ { \ diff --git a/src/southbridge/intel/lynxpoint/me_status.c b/src/southbridge/intel/lynxpoint/me_status.c index 9ca55529c3..ad8362d9d1 100644 --- a/src/southbridge/intel/lynxpoint/me_status.c +++ b/src/southbridge/intel/lynxpoint/me_status.c @@ -18,7 +18,6 @@ #include #include "me.h" -#if (CONFIG_DEFAULT_CONSOLE_LOGLEVEL >= BIOS_DEBUG) /* HFS1[3:0] Current Working State Values */ static const char *me_cws_values[] = { [ME_HFS_CWS_RESET] = "Reset", @@ -138,11 +137,12 @@ static const char *me_progress_policy_values[] = { [ME_HFS2_STATE_POLICY_DESCRIPTOR_ERR] = "ME cannot access the chipset descriptor region", [ME_HFS2_STATE_POLICY_VSCC_NO_MATCH] = "Required VSCC values for flash parts do not match", }; -#endif void intel_me_status(struct me_hfs *hfs, struct me_hfs2 *hfs2) { -#if (CONFIG_DEFAULT_CONSOLE_LOGLEVEL >= BIOS_DEBUG) + if (CONFIG_DEFAULT_CONSOLE_LOGLEVEL < BIOS_DEBUG) + return; + /* Check Current States */ printk(BIOS_DEBUG, "ME: FW Partition Table : %s\n", hfs->fpt_bad ? "BAD" : "OK"); @@ -206,5 +206,4 @@ void intel_me_status(struct me_hfs *hfs, struct me_hfs2 *hfs2) hfs2->progress_code, hfs2->current_state); } printk(BIOS_DEBUG, "\n"); -#endif } From 056fbe49ff9cccc7646371452431a05b47544057 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ky=C3=B6sti=20M=C3=A4lkki?= Date: Wed, 6 Nov 2019 12:07:05 +0200 Subject: [PATCH 0059/1242] ELOG, soc/intel: Avoid some preprocessor use MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Change-Id: I5378573f37daa4f09db332023027deda677c7aeb Signed-off-by: Kyösti Mälkki Reviewed-on: https://review.coreboot.org/c/coreboot/+/36646 Reviewed-by: Patrick Georgi Tested-by: build bot (Jenkins) --- src/soc/intel/baytrail/include/soc/pmc.h | 4 ---- src/soc/intel/baytrail/smm.c | 3 ++- src/soc/intel/braswell/include/soc/pm.h | 4 ---- src/soc/intel/braswell/smm.c | 3 ++- src/soc/intel/denverton_ns/include/soc/pmc.h | 10 ---------- src/soc/intel/fsp_baytrail/include/soc/pmc.h | 4 ---- src/soc/intel/fsp_baytrail/smm.c | 3 ++- 7 files changed, 6 insertions(+), 25 deletions(-) diff --git a/src/soc/intel/baytrail/include/soc/pmc.h b/src/soc/intel/baytrail/include/soc/pmc.h index 09d13221b3..6cdf419042 100644 --- a/src/soc/intel/baytrail/include/soc/pmc.h +++ b/src/soc/intel/baytrail/include/soc/pmc.h @@ -281,11 +281,7 @@ void enable_gpe(uint32_t mask); void disable_gpe(uint32_t mask); void disable_all_gpe(void); -#if CONFIG(ELOG) void southcluster_log_state(void); -#else -static inline void southcluster_log_state(void) {} -#endif /* Return non-zero when RTC failure happened. */ int rtc_failure(void); diff --git a/src/soc/intel/baytrail/smm.c b/src/soc/intel/baytrail/smm.c index 4f019229e4..9f10f70b61 100644 --- a/src/soc/intel/baytrail/smm.c +++ b/src/soc/intel/baytrail/smm.c @@ -38,7 +38,8 @@ void smm_southbridge_clear_state(void) uint32_t smi_en; /* Log events from chipset before clearing */ - southcluster_log_state(); + if (CONFIG(ELOG)) + southcluster_log_state(); printk(BIOS_DEBUG, "Initializing Southbridge SMI..."); printk(BIOS_SPEW, " pmbase = 0x%04x\n", get_pmbase()); diff --git a/src/soc/intel/braswell/include/soc/pm.h b/src/soc/intel/braswell/include/soc/pm.h index 5063342955..744fcf085f 100644 --- a/src/soc/intel/braswell/include/soc/pm.h +++ b/src/soc/intel/braswell/include/soc/pm.h @@ -242,11 +242,7 @@ void enable_gpe(uint32_t mask); void disable_gpe(uint32_t mask); void disable_all_gpe(void); -#if CONFIG(ELOG) void southcluster_log_state(void); -#else -static inline void southcluster_log_state(void) {} -#endif /* Return non-zero when RTC failure happened. */ int rtc_failure(void); diff --git a/src/soc/intel/braswell/smm.c b/src/soc/intel/braswell/smm.c index 364cda5b5a..c108a3629e 100644 --- a/src/soc/intel/braswell/smm.c +++ b/src/soc/intel/braswell/smm.c @@ -39,7 +39,8 @@ void smm_southbridge_clear_state(void) uint32_t smi_en; /* Log events from chipset before clearing */ - southcluster_log_state(); + if (CONFIG(ELOG)) + southcluster_log_state(); printk(BIOS_DEBUG, "Initializing Southbridge SMI..."); printk(BIOS_SPEW, " pmbase = 0x%04x\n", get_pmbase()); diff --git a/src/soc/intel/denverton_ns/include/soc/pmc.h b/src/soc/intel/denverton_ns/include/soc/pmc.h index af840a2f1a..62201d97a7 100644 --- a/src/soc/intel/denverton_ns/include/soc/pmc.h +++ b/src/soc/intel/denverton_ns/include/soc/pmc.h @@ -262,14 +262,4 @@ #define RST_CPU (1 << 2) #define SYS_RST (1 << 1) -#if !defined(__ASSEMBLER__) && !defined(__ACPI__) - -#if CONFIG(ELOG) -void southcluster_log_state(void); -#else -static inline void southcluster_log_state(void) {} -#endif - -#endif /* !defined(__ASSEMBLER__) && !defined(__ACPI__) */ - #endif /* _DENVERTON_NS_PMC_H_ */ diff --git a/src/soc/intel/fsp_baytrail/include/soc/pmc.h b/src/soc/intel/fsp_baytrail/include/soc/pmc.h index 71c8e10446..9e588addae 100644 --- a/src/soc/intel/fsp_baytrail/include/soc/pmc.h +++ b/src/soc/intel/fsp_baytrail/include/soc/pmc.h @@ -285,11 +285,7 @@ void disable_all_gpe(void); uint32_t chipset_prev_sleep_state(uint32_t clear); -#if CONFIG(ELOG) void southcluster_log_state(void); -#else -static inline void southcluster_log_state(void) {} -#endif #endif /* !defined(__ASSEMBLER__) && !defined(__ACPI__) */ diff --git a/src/soc/intel/fsp_baytrail/smm.c b/src/soc/intel/fsp_baytrail/smm.c index 0c40429aae..fbfd094c93 100644 --- a/src/soc/intel/fsp_baytrail/smm.c +++ b/src/soc/intel/fsp_baytrail/smm.c @@ -40,7 +40,8 @@ void smm_southbridge_clear_state(void) uint32_t smi_en; /* Log events from chipset before clearing */ - southcluster_log_state(); + if (CONFIG(ELOG)) + southcluster_log_state(); printk(BIOS_DEBUG, "Initializing Southbridge SMI..."); printk(BIOS_SPEW, " pmbase = 0x%04x\n", get_pmbase()); From 254933fba7cbbbc973fe611aedc585093afbbf8c Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ky=C3=B6sti=20M=C3=A4lkki?= Date: Wed, 6 Nov 2019 13:11:17 +0200 Subject: [PATCH 0060/1242] google/parrot: Remove ELOG_GSMI from EC MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit EC_HOST_EVENT_xxx are only defined with ec/chromeec. Change-Id: Idf7b04edc3fce147f7857691ce7d6a0ce03f43fe Signed-off-by: Kyösti Mälkki Reviewed-on: https://review.coreboot.org/c/coreboot/+/36649 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin --- src/mainboard/google/parrot/smihandler.c | 17 ----------------- 1 file changed, 17 deletions(-) diff --git a/src/mainboard/google/parrot/smihandler.c b/src/mainboard/google/parrot/smihandler.c index 92d361dd4c..c0a5d01385 100644 --- a/src/mainboard/google/parrot/smihandler.c +++ b/src/mainboard/google/parrot/smihandler.c @@ -29,9 +29,6 @@ static u8 mainboard_smi_ec(void) { u8 src; -#if CONFIG(ELOG_GSMI) - static int battery_critical_logged; -#endif ec_kbc_write_cmd(0x56); src = ec_kbc_read_ob(); @@ -39,20 +36,10 @@ static u8 mainboard_smi_ec(void) switch (src) { case EC_BATTERY_CRITICAL: -#if CONFIG(ELOG_GSMI) - if (!battery_critical_logged) - elog_add_event_byte(ELOG_TYPE_EC_EVENT, - EC_HOST_EVENT_BATTERY_CRITICAL); - battery_critical_logged = 1; -#endif break; case EC_LID_CLOSE: printk(BIOS_DEBUG, "LID CLOSED, SHUTDOWN\n"); -#if CONFIG(ELOG_GSMI) - elog_add_event_byte(ELOG_TYPE_EC_EVENT, - EC_HOST_EVENT_LID_CLOSED); -#endif /* Go to S5 */ write_pmbase32(PM1_CNT, read_pmbase32(PM1_CNT) | (0xf << 10)); break; @@ -71,10 +58,6 @@ void mainboard_smi_gpi(u32 gpi_sts) else if (gpi_sts & (1 << EC_LID_GPI)) { printk(BIOS_DEBUG, "LID CLOSED, SHUTDOWN\n"); -#if CONFIG(ELOG_GSMI) - elog_add_event_byte(ELOG_TYPE_EC_EVENT, - EC_HOST_EVENT_LID_CLOSED); -#endif /* Go to S5 */ write_pmbase32(PM1_CNT, read_pmbase32(PM1_CNT) | (0xf << 10)); } From 76ffa88e1e7830417e60cd778b9384bc0bbcb218 Mon Sep 17 00:00:00 2001 From: Frans Hendriks Date: Fri, 8 Nov 2019 08:54:47 +0100 Subject: [PATCH 0061/1242] configs/config.facebook_fbg1701: Add config file Enable vendorcode measured and verified boot. Use VBOOT test key for VENDORCODE_ELTAN_VBOOT_KEY_FILE BUG=N/A TEST=booting Embedded Linux 4.20 kernel on Facebook FBG1701 Change-Id: Ia2cb3bb873b2d5e7e9031e5b249d86605d8e0945 Signed-off-by: Frans Hendriks Reviewed-on: https://review.coreboot.org/c/coreboot/+/34343 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi --- configs/config.facebook_fbg1701 | 12 ++++++++++++ 1 file changed, 12 insertions(+) create mode 100644 configs/config.facebook_fbg1701 diff --git a/configs/config.facebook_fbg1701 b/configs/config.facebook_fbg1701 new file mode 100644 index 0000000000..b372bbeb29 --- /dev/null +++ b/configs/config.facebook_fbg1701 @@ -0,0 +1,12 @@ +CONFIG_VENDOR_FACEBOOK=y +CONFIG_C_ENV_BOOTBLOCK_SIZE=0x6000 +CONFIG_ONBOARD_SAMSUNG_MEM=y +CONFIG_CPU_MICROCODE_CBFS_LOC=0xFFF8B000 +CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_BINS=y +CONFIG_CPU_UCODE_BINARIES="3rdparty/intel-microcode/intel-ucode/06-4c-04" +CONFIG_VENDORCODE_ELTAN_MBOOT=y +CONFIG_VENDORCODE_ELTAN_VBOOT=y +CONFIG_VENDORCODE_ELTAN_VBOOT_KEY_FILE="3rdparty/vboot/tests/devkeys-acc/key_hadoken.vbpubk2" +CONFIG_RUN_FSP_GOP=y +CONFIG_DISPLAY_HOBS=y +CONFIG_DEFAULT_CONSOLE_LOGLEVEL_8=y From f307ffbe47f014bbea83a1da044e95210d66f56f Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ky=C3=B6sti=20M=C3=A4lkki?= Date: Wed, 6 Nov 2019 13:11:17 +0200 Subject: [PATCH 0062/1242] google/stout: Remove ELOG_GSMI from EC MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit EC_HOST_EVENT_xxx are only defined with ec/chromeec. Change-Id: Ie0a1349ab460142dc2744155a422b5ee22528e4c Signed-off-by: Kyösti Mälkki Reviewed-on: https://review.coreboot.org/c/coreboot/+/36663 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin --- src/mainboard/google/stout/ec.c | 15 --------------- 1 file changed, 15 deletions(-) diff --git a/src/mainboard/google/stout/ec.c b/src/mainboard/google/stout/ec.c index 660bb76361..59987a156d 100644 --- a/src/mainboard/google/stout/ec.c +++ b/src/mainboard/google/stout/ec.c @@ -75,10 +75,6 @@ void stout_ec_finalize_smm(void) if (ec_reg & 0x8) { printk(BIOS_ERR, " EC Fan Error\n"); critical_shutdown = 1; -#if CONFIG(ELOG_GSMI) - elog_add_event_word(EC_HOST_EVENT_BATTERY_CRITICAL, - EC_HOST_EVENT_THROTTLE_START); -#endif } @@ -86,10 +82,6 @@ void stout_ec_finalize_smm(void) if (ec_reg & 0x80) { printk(BIOS_ERR, " EC Thermal Device Error\n"); critical_shutdown = 1; -#if CONFIG(ELOG_GSMI) - elog_add_event_word(EC_HOST_EVENT_BATTERY_CRITICAL, - EC_HOST_EVENT_THERMAL); -#endif } @@ -99,17 +91,10 @@ void stout_ec_finalize_smm(void) if ((ec_reg & 0xCF) == 0xC0) { printk(BIOS_ERR, " EC Critical Battery Error\n"); critical_shutdown = 1; -#if CONFIG(ELOG_GSMI) - elog_add_event_word(ELOG_TYPE_EC_EVENT, - EC_HOST_EVENT_BATTERY_CRITICAL); -#endif } if ((ec_reg & 0x8F) == 0x8F) { printk(BIOS_ERR, " EC Read Battery Error\n"); -#if CONFIG(ELOG_GSMI) - elog_add_event_word(ELOG_TYPE_EC_EVENT, EC_HOST_EVENT_BATTERY); -#endif } From 930c31c63ab2e2a2654090f4968217f2cd3125f3 Mon Sep 17 00:00:00 2001 From: Subrata Banik Date: Fri, 1 Nov 2019 18:12:58 +0530 Subject: [PATCH 0063/1242] soc/intel/tigerlake/bootblock: Do initial SoC commit till bootblock Clone entirely from Icelake List of changes on top off initial icelake clone 1. Replace "Icelake" with "Tigerlake" 2. Replace "icl" with "tgl" 3. Replace "icp" with "tgp" 4. Rename structure based on Icelake with Tigerlake 5. Add CPU/PCH/SA EDS document number and chapter number 6. Add required headers into include/soc/ from ICL directory Tiger Lake specific changes will follow in subsequent patches. 1. Add Tigerlake specific device IDs (CPU/PCH/SA) Change-Id: Id7a05f4b183028550d805f02a8078ab69862a62e Signed-off-by: Subrata Banik Reviewed-on: https://review.coreboot.org/c/coreboot/+/36550 Tested-by: build bot (Jenkins) Reviewed-by: Maulik V Vaghela --- src/soc/intel/tigerlake/bootblock/bootblock.c | 44 ++++ src/soc/intel/tigerlake/bootblock/cpu.c | 37 ++++ src/soc/intel/tigerlake/bootblock/pch.c | 171 +++++++++++++++ .../tigerlake/bootblock/report_platform.c | 168 ++++++++++++++ .../intel/tigerlake/include/soc/bootblock.h | 28 +++ src/soc/intel/tigerlake/include/soc/espi.h | 59 +++++ src/soc/intel/tigerlake/include/soc/iomap.h | 84 +++++++ src/soc/intel/tigerlake/include/soc/p2sb.h | 30 +++ src/soc/intel/tigerlake/include/soc/pch.h | 29 +++ .../intel/tigerlake/include/soc/pci_devs.h | 205 ++++++++++++++++++ src/soc/intel/tigerlake/include/soc/pcr_ids.h | 50 +++++ src/soc/intel/tigerlake/include/soc/pm.h | 181 ++++++++++++++++ src/soc/intel/tigerlake/include/soc/smbus.h | 45 ++++ 13 files changed, 1131 insertions(+) create mode 100644 src/soc/intel/tigerlake/bootblock/bootblock.c create mode 100644 src/soc/intel/tigerlake/bootblock/cpu.c create mode 100644 src/soc/intel/tigerlake/bootblock/pch.c create mode 100644 src/soc/intel/tigerlake/bootblock/report_platform.c create mode 100644 src/soc/intel/tigerlake/include/soc/bootblock.h create mode 100644 src/soc/intel/tigerlake/include/soc/espi.h create mode 100644 src/soc/intel/tigerlake/include/soc/iomap.h create mode 100644 src/soc/intel/tigerlake/include/soc/p2sb.h create mode 100644 src/soc/intel/tigerlake/include/soc/pch.h create mode 100644 src/soc/intel/tigerlake/include/soc/pci_devs.h create mode 100644 src/soc/intel/tigerlake/include/soc/pcr_ids.h create mode 100644 src/soc/intel/tigerlake/include/soc/pm.h create mode 100644 src/soc/intel/tigerlake/include/soc/smbus.h diff --git a/src/soc/intel/tigerlake/bootblock/bootblock.c b/src/soc/intel/tigerlake/bootblock/bootblock.c new file mode 100644 index 0000000000..f6fe4c4dbd --- /dev/null +++ b/src/soc/intel/tigerlake/bootblock/bootblock.c @@ -0,0 +1,44 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include +#include +#include +#include +#include + +asmlinkage void bootblock_c_entry(uint64_t base_timestamp) +{ + /* Call lib/bootblock.c main */ + bootblock_main_with_basetime(base_timestamp); +} + +void bootblock_soc_early_init(void) +{ + bootblock_systemagent_early_init(); + bootblock_pch_early_init(); + bootblock_cpu_init(); + pch_early_iorange_init(); + if (CONFIG(INTEL_LPSS_UART_FOR_CONSOLE)) + uart_bootblock_init(); +} + +void bootblock_soc_init(void) +{ + report_platform_info(); + pch_early_init(); +} diff --git a/src/soc/intel/tigerlake/bootblock/cpu.c b/src/soc/intel/tigerlake/bootblock/cpu.c new file mode 100644 index 0000000000..1bae4fa804 --- /dev/null +++ b/src/soc/intel/tigerlake/bootblock/cpu.c @@ -0,0 +1,37 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* + * This file is created based on Intel Tiger Lake Processor PCH Datasheet + * Document number: 575857 + * Chapter number: 6 + */ + +#include +#include + +void bootblock_cpu_init(void) +{ + /* + * Tigerlake platform doesn't support booting from any other media + * (like eMMC on APL/GLK platform) than only booting from SPI device + * and on IA platform SPI is memory mapped hence enabling temporarily + * cacheing on memory-mapped spi boot media. + * + * This assumption will not hold good for APL/GLK platform where boot + * from eMMC is also possible options. + */ + fast_spi_cache_bios_region(); +} diff --git a/src/soc/intel/tigerlake/bootblock/pch.c b/src/soc/intel/tigerlake/bootblock/pch.c new file mode 100644 index 0000000000..c7ccbf8bab --- /dev/null +++ b/src/soc/intel/tigerlake/bootblock/pch.c @@ -0,0 +1,171 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* + * This file is created based on Intel Tiger Lake Processor PCH Datasheet + * Document number: 575857 + * Chapter number: 2, 3, 4, 27, 28 + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define PCR_PSF3_TO_SHDW_PMC_REG_BASE 0x0600 +#define PCR_PSFX_TO_SHDW_BAR0 0 +#define PCR_PSFX_TO_SHDW_BAR1 0x4 +#define PCR_PSFX_TO_SHDW_BAR2 0x8 +#define PCR_PSFX_TO_SHDW_BAR3 0xC +#define PCR_PSFX_TO_SHDW_BAR4 0x10 +#define PCR_PSFX_TO_SHDW_PCIEN_IOEN 0x01 +#define PCR_PSFX_T0_SHDW_PCIEN 0x1C + +#define PCR_DMI_DMICTL 0x2234 +#define PCR_DMI_DMICTL_SRLOCK (1 << 31) + +#define PCR_DMI_ACPIBA 0x27B4 +#define PCR_DMI_ACPIBDID 0x27B8 +#define PCR_DMI_PMBASEA 0x27AC +#define PCR_DMI_PMBASEC 0x27B0 + +#define PCR_DMI_LPCIOD 0x2770 +#define PCR_DMI_LPCIOE 0x2774 + +static void soc_config_pwrmbase(void) +{ + uint32_t reg32; + + /* + * Assign Resources to PWRMBASE + * Clear BIT 1-2 Command Register + */ + reg32 = pci_read_config32(PCH_DEV_PMC, PCI_COMMAND); + reg32 &= ~(PCI_COMMAND_MEMORY); + pci_write_config32(PCH_DEV_PMC, PCI_COMMAND, reg32); + + /* Program PWRM Base */ + pci_write_config32(PCH_DEV_PMC, PWRMBASE, PCH_PWRM_BASE_ADDRESS); + + /* Enable Bus Master and MMIO Space */ + reg32 = pci_read_config32(PCH_DEV_PMC, PCI_COMMAND); + reg32 |= PCI_COMMAND_MEMORY; + pci_write_config32(PCH_DEV_PMC, PCI_COMMAND, reg32); + + /* Enable PWRM in PMC */ + reg32 = read32((void *)(PCH_PWRM_BASE_ADDRESS + ACTL)); + write32((void *)(PCH_PWRM_BASE_ADDRESS + ACTL), reg32 | PWRM_EN); +} + +void bootblock_pch_early_init(void) +{ + fast_spi_early_init(SPI_BASE_ADDRESS); + gspi_early_bar_init(); + p2sb_enable_bar(); + p2sb_configure_hpet(); + + /* + * Enabling PWRM Base for accessing + * Global Reset Cause Register. + */ + soc_config_pwrmbase(); +} + +static void soc_config_acpibase(void) +{ + uint32_t pmc_reg_value; + + pmc_reg_value = pcr_read32(PID_PSF3, PCR_PSF3_TO_SHDW_PMC_REG_BASE + + PCR_PSFX_TO_SHDW_BAR4); + + if (pmc_reg_value != 0xffffffff) { + /* Disable Io Space before changing the address */ + pcr_rmw32(PID_PSF3, PCR_PSF3_TO_SHDW_PMC_REG_BASE + + PCR_PSFX_T0_SHDW_PCIEN, + ~PCR_PSFX_TO_SHDW_PCIEN_IOEN, 0); + /* Program ABASE in PSF3 PMC space BAR4*/ + pcr_write32(PID_PSF3, PCR_PSF3_TO_SHDW_PMC_REG_BASE + + PCR_PSFX_TO_SHDW_BAR4, + ACPI_BASE_ADDRESS); + /* Enable IO Space */ + pcr_rmw32(PID_PSF3, PCR_PSF3_TO_SHDW_PMC_REG_BASE + + PCR_PSFX_T0_SHDW_PCIEN, + ~0, PCR_PSFX_TO_SHDW_PCIEN_IOEN); + } +} + +static int pch_check_decode_enable(void) +{ + uint32_t dmi_control; + + /* + * This cycle decoding is only allowed to set when + * DMICTL.SRLOCK is 0. + */ + dmi_control = pcr_read32(PID_DMI, PCR_DMI_DMICTL); + if (dmi_control & PCR_DMI_DMICTL_SRLOCK) + return -1; + return 0; +} + +void pch_early_iorange_init(void) +{ + uint16_t io_enables = LPC_IOE_SUPERIO_2E_2F | LPC_IOE_KBC_60_64 | + LPC_IOE_EC_62_66 | LPC_IOE_LGE_200; + + /* IO Decode Range */ + if (CONFIG(DRIVERS_UART_8250IO)) + lpc_io_setup_comm_a_b(); + + /* IO Decode Enable */ + if (pch_check_decode_enable() == 0) { + io_enables = lpc_enable_fixed_io_ranges(io_enables); + /* + * Set up ESPI IO Enables PCR[DMI] + 2774h [15:0] to the same + * value program in ESPI PCI offset 82h. + */ + pcr_write16(PID_DMI, PCR_DMI_LPCIOE, io_enables); + } + + /* Program generic IO Decode Range */ + pch_enable_lpc(); +} + +void pch_early_init(void) +{ + /* + * Enabling ABASE for accessing PM1_STS, PM1_EN, PM1_CNT, + * GPE0_STS, GPE0_EN registers. + */ + soc_config_acpibase(); + + /* Set up GPE configuration */ + pmc_gpe_init(); + + enable_rtc_upper_bank(); +} diff --git a/src/soc/intel/tigerlake/bootblock/report_platform.c b/src/soc/intel/tigerlake/bootblock/report_platform.c new file mode 100644 index 0000000000..6a58ea7c97 --- /dev/null +++ b/src/soc/intel/tigerlake/bootblock/report_platform.c @@ -0,0 +1,168 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* + * This file is created based on Intel Tiger Lake Platform Stepping and IDs + * Document number: 605534 + * Chapter number: 2, 4, 5, 6 + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define BIOS_SIGN_ID 0x8B + +/* + * TODO: Add TGL specific CPU/SA/PCH IDs here + */ + +static inline uint8_t get_dev_revision(pci_devfn_t dev) +{ + return pci_read_config8(dev, PCI_REVISION_ID); +} + +static inline uint16_t get_dev_id(pci_devfn_t dev) +{ + return pci_read_config16(dev, PCI_DEVICE_ID); +} + +static void report_cpu_info(void) +{ + struct cpuid_result cpuidr; + u32 i, index, cpu_id, cpu_feature_flag; + const char cpu_not_found[] = "Platform info not available"; + const char *cpu_name = cpu_not_found; /* 48 bytes are reported */ + int vt, txt, aes; + msr_t microcode_ver; + static const char *const mode[] = {"NOT ", ""}; + const char *cpu_type = "Unknown"; + u32 p[13]; + + index = 0x80000000; + cpuidr = cpuid(index); + if (cpuidr.eax >= 0x80000004) { + int j = 0; + + for (i = 2; i <= 4; i++) { + cpuidr = cpuid(index + i); + p[j++] = cpuidr.eax; + p[j++] = cpuidr.ebx; + p[j++] = cpuidr.ecx; + p[j++] = cpuidr.edx; + } + p[12] = 0; + cpu_name = (char *)p; + + /* Skip leading spaces in CPU name string */ + while (cpu_name[0] == ' ' && strlen(cpu_name) > 0) + cpu_name++; + } + + microcode_ver.lo = 0; + microcode_ver.hi = 0; + wrmsr(BIOS_SIGN_ID, microcode_ver); + cpu_id = cpu_get_cpuid(); + microcode_ver = rdmsr(BIOS_SIGN_ID); + + /* Look for string to match the name */ + for (i = 0; i < ARRAY_SIZE(cpu_table); i++) { + if (cpu_table[i].cpuid == cpu_id) { + cpu_type = cpu_table[i].name; + break; + } + } + + printk(BIOS_DEBUG, "CPU: %s\n", cpu_name); + printk(BIOS_DEBUG, "CPU: ID %x, %s, ucode: %08x\n", + cpu_id, cpu_type, microcode_ver.hi); + + cpu_feature_flag = cpu_get_feature_flags_ecx(); + aes = (cpu_feature_flag & CPUID_AES) ? 1 : 0; + txt = (cpu_feature_flag & CPUID_SMX) ? 1 : 0; + vt = (cpu_feature_flag & CPUID_VMX) ? 1 : 0; + printk(BIOS_DEBUG, + "CPU: AES %ssupported, TXT %ssupported, VT %ssupported\n", + mode[aes], mode[txt], mode[vt]); +} + +static void report_mch_info(void) +{ + int i; + pci_devfn_t dev = SA_DEV_ROOT; + uint16_t mchid = get_dev_id(dev); + uint8_t mch_revision = get_dev_revision(dev); + const char *mch_type = "Unknown"; + + for (i = 0; i < ARRAY_SIZE(mch_table); i++) { + if (mch_table[i].mchid == mchid) { + mch_type = mch_table[i].name; + break; + } + } + + printk(BIOS_DEBUG, "MCH: device id %04x (rev %02x) is %s\n", + mchid, mch_revision, mch_type); +} + +static void report_pch_info(void) +{ + int i; + pci_devfn_t dev = PCH_DEV_ESPI; + uint16_t espiid = get_dev_id(dev); + const char *pch_type = "Unknown"; + + for (i = 0; i < ARRAY_SIZE(pch_table); i++) { + if (pch_table[i].espiid == espiid) { + pch_type = pch_table[i].name; + break; + } + } + printk(BIOS_DEBUG, "PCH: device id %04x (rev %02x) is %s\n", + espiid, get_dev_revision(dev), pch_type); +} + +static void report_igd_info(void) +{ + int i; + pci_devfn_t dev = SA_DEV_IGD; + uint16_t igdid = get_dev_id(dev); + const char *igd_type = "Unknown"; + + for (i = 0; i < ARRAY_SIZE(igd_table); i++) { + if (igd_table[i].igdid == igdid) { + igd_type = igd_table[i].name; + break; + } + } + printk(BIOS_DEBUG, "IGD: device id %04x (rev %02x) is %s\n", + igdid, get_dev_revision(dev), igd_type); +} + +void report_platform_info(void) +{ + report_cpu_info(); + report_mch_info(); + report_pch_info(); + report_igd_info(); +} diff --git a/src/soc/intel/tigerlake/include/soc/bootblock.h b/src/soc/intel/tigerlake/include/soc/bootblock.h new file mode 100644 index 0000000000..cb7417a107 --- /dev/null +++ b/src/soc/intel/tigerlake/include/soc/bootblock.h @@ -0,0 +1,28 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _SOC_TIGERLAKE_BOOTBLOCK_H_ +#define _SOC_TIGERLAKE_BOOTBLOCK_H_ + +/* Bootblock pre console init programming */ +void bootblock_cpu_init(void); +void bootblock_pch_early_init(void); + +/* Bootblock post console init programming */ +void pch_early_init(void); +void pch_early_iorange_init(void); +void report_platform_info(void); + +#endif diff --git a/src/soc/intel/tigerlake/include/soc/espi.h b/src/soc/intel/tigerlake/include/soc/espi.h new file mode 100644 index 0000000000..03cf8e8b55 --- /dev/null +++ b/src/soc/intel/tigerlake/include/soc/espi.h @@ -0,0 +1,59 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* + * This file is created based on Intel Tiger Lake Processor PCH Datasheet + * Document number: 575857 + * Chapter number: 2 + */ + +#ifndef _SOC_TIGERLAKE_ESPI_H_ +#define _SOC_TIGERLAKE_ESPI_H_ + +#include + +/* PCI Configuration Space (D31:F0): ESPI */ +#define SCI_IRQ_SEL (7 << 0) +#define SCIS_IRQ9 0 +#define SCIS_IRQ10 1 +#define SCIS_IRQ11 2 +#define SCIS_IRQ20 4 +#define SCIS_IRQ21 5 +#define SCIS_IRQ22 6 +#define SCIS_IRQ23 7 +#define SERIRQ_CNTL 0x64 +#define ESPI_IO_DEC 0x80 /* IO Decode Ranges Register */ +#define COMA_RANGE 0x0 /* 0x3F8 - 0x3FF COM1*/ +#define COMB_RANGE 0x1 /* 0x2F8 - 0x2FF COM2*/ +#define ESPI_GEN1_DEC 0x84 /* ESPI IF Generic Decode Range 1 */ +#define ESPI_GEN2_DEC 0x88 /* ESPI IF Generic Decode Range 2 */ +#define ESPI_GEN3_DEC 0x8c /* ESPI IF Generic Decode Range 3 */ +#define ESPI_GEN4_DEC 0x90 /* ESPI IF Generic Decode Range 4 */ +#define LGMR 0x98 /* ESPI Generic Memory Range */ +#define PCCTL 0xE0 /* PCI Clock Control */ +#define CLKRUN_EN (1 << 0) + +/* + * This function will help to differentiate between 2 PCH on single type of soc. + * Since same soc may have LP series pch or H series PCH, we need to + * differentiate by reading upper 8 bits of PCH device ids. + * + * Return: + * Return PCH_LP or PCH_H macro in case of respective device ID found. + * PCH_UNKNOWN_SERIES in case of invalid device ID. + */ +uint8_t get_pch_series(void); + +#endif diff --git a/src/soc/intel/tigerlake/include/soc/iomap.h b/src/soc/intel/tigerlake/include/soc/iomap.h new file mode 100644 index 0000000000..b3797c1513 --- /dev/null +++ b/src/soc/intel/tigerlake/include/soc/iomap.h @@ -0,0 +1,84 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* + * This file is created based on Intel Tiger Lake Firmware Architecture Specification + * Document number: 608531 + * Chapter number: 4 + */ + +#ifndef _SOC_TIGERLAKE_IOMAP_H_ +#define _SOC_TIGERLAKE_IOMAP_H_ + +/* + * Memory-mapped I/O registers. + */ +#define MCFG_BASE_ADDRESS CONFIG_MMCONF_BASE_ADDRESS +#define MCFG_BASE_SIZE 0x4000000 + +#define PCH_PRESERVED_BASE_ADDRESS 0xfc800000 +#define PCH_PRESERVED_BASE_SIZE 0x02000000 + +#define PCH_TRACE_HUB_BASE_ADDRESS 0xfc800000 +#define PCH_TRACE_HUB_BASE_SIZE 0x00800000 + +#define EARLY_I2C_BASE_ADDRESS 0xfe040000 +#define EARLY_I2C_BASE(x) (EARLY_I2C_BASE_ADDRESS + (0x1000 * (x))) + +#define MCH_BASE_ADDRESS 0xfed10000 +#define MCH_BASE_SIZE 0x8000 + +#define DMI_BASE_ADDRESS 0xfeda0000 +#define DMI_BASE_SIZE 0x1000 + +#define EP_BASE_ADDRESS 0xfeda1000 +#define EP_BASE_SIZE 0x1000 + +#define EDRAM_BASE_ADDRESS 0xfed80000 +#define EDRAM_BASE_SIZE 0x4000 + +#define REG_BASE_ADDRESS 0xfc000000 +#define REG_BASE_SIZE 0x1000 + +#define HPET_BASE_ADDRESS 0xfed00000 + +#define PCH_PWRM_BASE_ADDRESS 0xfe000000 +#define PCH_PWRM_BASE_SIZE 0x10000 + +#define SPI_BASE_ADDRESS 0xfe010000 +#define EARLY_GSPI_BASE_ADDRESS 0xfe011000 + +#define GPIO_BASE_SIZE 0x10000 + +#define HECI1_BASE_ADDRESS 0xfeda2000 + +#define VTD_BASE_ADDRESS 0xFED90000 +#define VTD_BASE_SIZE 0x00004000 +/* + * I/O port address space + */ +#define SMBUS_BASE_ADDRESS 0x0efa0 +#define SMBUS_BASE_SIZE 0x20 + +#define ACPI_BASE_ADDRESS 0x1800 +#define ACPI_BASE_SIZE 0x100 + +#define TCO_BASE_ADDRESS 0x400 +#define TCO_BASE_SIZE 0x20 + +#define P2SB_BAR CONFIG_PCR_BASE_ADDRESS +#define P2SB_SIZE (16 * MiB) + +#endif diff --git a/src/soc/intel/tigerlake/include/soc/p2sb.h b/src/soc/intel/tigerlake/include/soc/p2sb.h new file mode 100644 index 0000000000..46fdf47c59 --- /dev/null +++ b/src/soc/intel/tigerlake/include/soc/p2sb.h @@ -0,0 +1,30 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* + * This file is created based on Intel Tiger Lake Processor PCH Datasheet + * Document number: 575857 + * Chapter number: 3 + */ + +#ifndef _SOC_TIGERLAKE_P2SB_H_ +#define _SOC_TIGERLAKE_P2SB_H_ + +#define HPTC_OFFSET 0x60 +#define HPTC_ADDR_ENABLE_BIT (1 << 7) + +#define PCH_P2SB_EPMASK0 0x220 + +#endif diff --git a/src/soc/intel/tigerlake/include/soc/pch.h b/src/soc/intel/tigerlake/include/soc/pch.h new file mode 100644 index 0000000000..57ddeaf97f --- /dev/null +++ b/src/soc/intel/tigerlake/include/soc/pch.h @@ -0,0 +1,29 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _SOC_TIGERLAKE_PCH_H_ +#define _SOC_TIGERLAKE_PCH_H_ + +#include + +#define PCH_H 1 +#define PCH_LP 2 +#define PCH_UNKNOWN_SERIES 0xFF + +#define PCIE_CLK_NOTUSED 0xFF +#define PCIE_CLK_LAN 0x70 +#define PCIE_CLK_FREE 0x80 + +#endif diff --git a/src/soc/intel/tigerlake/include/soc/pci_devs.h b/src/soc/intel/tigerlake/include/soc/pci_devs.h new file mode 100644 index 0000000000..f54ab4b448 --- /dev/null +++ b/src/soc/intel/tigerlake/include/soc/pci_devs.h @@ -0,0 +1,205 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _SOC_TIGERLAKE_PCI_DEVS_H_ +#define _SOC_TIGERLAKE_PCI_DEVS_H_ + +#include + +#define _PCH_DEVFN(slot, func) PCI_DEVFN(PCH_DEV_SLOT_ ## slot, func) + +#if !defined(__SIMPLE_DEVICE__) +#include +#define _PCH_DEV(slot, func) pcidev_path_on_root_debug(_PCH_DEVFN(slot, func), __func__) +#else +#define _PCH_DEV(slot, func) PCI_DEV(0, PCH_DEV_SLOT_ ## slot, func) +#endif + +/* System Agent Devices */ + +#define SA_DEV_SLOT_ROOT 0x00 +#define SA_DEVFN_ROOT PCI_DEVFN(SA_DEV_SLOT_ROOT, 0) +#if defined(__SIMPLE_DEVICE__) +#define SA_DEV_ROOT PCI_DEV(0, SA_DEV_SLOT_ROOT, 0) +#endif + +#define SA_DEV_SLOT_IGD 0x02 +#define SA_DEVFN_IGD PCI_DEVFN(SA_DEV_SLOT_IGD, 0) +#define SA_DEV_IGD PCI_DEV(0, SA_DEV_SLOT_IGD, 0) + +#define SA_DEV_SLOT_DSP 0x04 +#define SA_DEVFN_DSP PCI_DEVFN(SA_DEV_SLOT_DSP, 0) +#define SA_DEV_DSP PCI_DEV(0, SA_DEV_SLOT_DSP, 0) + +/* PCH Devices */ +#define PCH_DEV_SLOT_THERMAL 0x12 +#define PCH_DEVFN_THERMAL _PCH_DEVFN(THERMAL, 0) +#define PCH_DEVFN_UFS _PCH_DEVFN(THERMAL, 5) +#define PCH_DEVFN_GSPI2 _PCH_DEVFN(THERMAL, 6) +#define PCH_DEV_THERMAL _PCH_DEV(THERMAL, 0) +#define PCH_DEV_UFS _PCH_DEV(THERMAL, 5) +#define PCH_DEV_GSPI2 _PCH_DEV(THERMAL, 6) + +#define PCH_DEV_SLOT_ISH 0x13 +#define PCH_DEVFN_ISH _PCH_DEVFN(ISH, 0) +#define PCH_DEV_ISH _PCH_DEV(ISH, 0) + +#define PCH_DEV_SLOT_XHCI 0x14 +#define PCH_DEVFN_XHCI _PCH_DEVFN(XHCI, 0) +#define PCH_DEVFN_USBOTG _PCH_DEVFN(XHCI, 1) +#define PCH_DEVFN_CNViWIFI _PCH_DEVFN(XHCI, 3) +#define PCH_DEVFN_SDCARD _PCH_DEVFN(XHCI, 5) +#define PCH_DEV_XHCI _PCH_DEV(XHCI, 0) +#define PCH_DEV_USBOTG _PCH_DEV(XHCI, 1) +#define PCH_DEV_CNViWIFI _PCH_DEV(XHCI, 3) +#define PCH_DEV_SDCARD _PCH_DEV(XHCI, 5) + +#define PCH_DEV_SLOT_SIO1 0x15 +#define PCH_DEVFN_I2C0 _PCH_DEVFN(SIO1, 0) +#define PCH_DEVFN_I2C1 _PCH_DEVFN(SIO1, 1) +#define PCH_DEVFN_I2C2 _PCH_DEVFN(SIO1, 2) +#define PCH_DEVFN_I2C3 _PCH_DEVFN(SIO1, 3) +#define PCH_DEV_I2C0 _PCH_DEV(SIO1, 0) +#define PCH_DEV_I2C1 _PCH_DEV(SIO1, 1) +#define PCH_DEV_I2C2 _PCH_DEV(SIO1, 2) +#define PCH_DEV_I2C3 _PCH_DEV(SIO1, 3) + +#define PCH_DEV_SLOT_CSE 0x16 +#define PCH_DEVFN_CSE _PCH_DEVFN(CSE, 0) +#define PCH_DEVFN_CSE_2 _PCH_DEVFN(CSE, 1) +#define PCH_DEVFN_CSE_IDER _PCH_DEVFN(CSE, 2) +#define PCH_DEVFN_CSE_KT _PCH_DEVFN(CSE, 3) +#define PCH_DEVFN_CSE_3 _PCH_DEVFN(CSE, 4) +#define PCH_DEVFN_CSE_4 _PCH_DEVFN(CSE, 5) +#define PCH_DEV_CSE _PCH_DEV(CSE, 0) +#define PCH_DEV_CSE_2 _PCH_DEV(CSE, 1) +#define PCH_DEV_CSE_IDER _PCH_DEV(CSE, 2) +#define PCH_DEV_CSE_KT _PCH_DEV(CSE, 3) +#define PCH_DEV_CSE_3 _PCH_DEV(CSE, 4) +#define PCH_DEV_CSE_4 _PCH_DEV(CSE, 5) + +#define PCH_DEV_SLOT_SATA 0x17 +#define PCH_DEVFN_SATA _PCH_DEVFN(SATA, 0) +#define PCH_DEV_SATA _PCH_DEV(SATA, 0) + +#define PCH_DEV_SLOT_SIO2 0x19 +#define PCH_DEVFN_I2C4 _PCH_DEVFN(SIO2, 0) +#define PCH_DEVFN_I2C5 _PCH_DEVFN(SIO2, 1) +#define PCH_DEVFN_UART2 _PCH_DEVFN(SIO2, 2) +#define PCH_DEV_I2C4 _PCH_DEV(SIO2, 0) +#define PCH_DEV_I2C5 _PCH_DEV(SIO2, 1) +#define PCH_DEV_UART2 _PCH_DEV(SIO2, 2) + +#define PCH_DEV_SLOT_STORAGE 0x1A +#define PCH_DEVFN_EMMC _PCH_DEVFN(STORAGE, 0) +#define PCH_DEV_EMMC _PCH_DEV(STORAGE, 0) + +#define PCH_DEV_SLOT_PCIE 0x1c +#define PCH_DEVFN_PCIE1 _PCH_DEVFN(PCIE, 0) +#define PCH_DEVFN_PCIE2 _PCH_DEVFN(PCIE, 1) +#define PCH_DEVFN_PCIE3 _PCH_DEVFN(PCIE, 2) +#define PCH_DEVFN_PCIE4 _PCH_DEVFN(PCIE, 3) +#define PCH_DEVFN_PCIE5 _PCH_DEVFN(PCIE, 4) +#define PCH_DEVFN_PCIE6 _PCH_DEVFN(PCIE, 5) +#define PCH_DEVFN_PCIE7 _PCH_DEVFN(PCIE, 6) +#define PCH_DEVFN_PCIE8 _PCH_DEVFN(PCIE, 7) +#define PCH_DEV_PCIE1 _PCH_DEV(PCIE, 0) +#define PCH_DEV_PCIE2 _PCH_DEV(PCIE, 1) +#define PCH_DEV_PCIE3 _PCH_DEV(PCIE, 2) +#define PCH_DEV_PCIE4 _PCH_DEV(PCIE, 3) +#define PCH_DEV_PCIE5 _PCH_DEV(PCIE, 4) +#define PCH_DEV_PCIE6 _PCH_DEV(PCIE, 5) +#define PCH_DEV_PCIE7 _PCH_DEV(PCIE, 6) +#define PCH_DEV_PCIE8 _PCH_DEV(PCIE, 7) + +#define PCH_DEV_SLOT_PCIE_1 0x1d +#define PCH_DEVFN_PCIE9 _PCH_DEVFN(PCIE_1, 0) +#define PCH_DEVFN_PCIE10 _PCH_DEVFN(PCIE_1, 1) +#define PCH_DEVFN_PCIE11 _PCH_DEVFN(PCIE_1, 2) +#define PCH_DEVFN_PCIE12 _PCH_DEVFN(PCIE_1, 3) +#define PCH_DEVFN_PCIE13 _PCH_DEVFN(PCIE_1, 4) +#define PCH_DEVFN_PCIE14 _PCH_DEVFN(PCIE_1, 5) +#define PCH_DEVFN_PCIE15 _PCH_DEVFN(PCIE_1, 6) +#define PCH_DEVFN_PCIE16 _PCH_DEVFN(PCIE_1, 7) +#define PCH_DEV_PCIE9 _PCH_DEV(PCIE_1, 0) +#define PCH_DEV_PCIE10 _PCH_DEV(PCIE_1, 1) +#define PCH_DEV_PCIE11 _PCH_DEV(PCIE_1, 2) +#define PCH_DEV_PCIE12 _PCH_DEV(PCIE_1, 3) +#define PCH_DEV_PCIE13 _PCH_DEV(PCIE_1, 4) +#define PCH_DEV_PCIE14 _PCH_DEV(PCIE_1, 5) +#define PCH_DEV_PCIE15 _PCH_DEV(PCIE_1, 6) +#define PCH_DEV_PCIE16 _PCH_DEV(PCIE_1, 7) + +#define PCH_DEV_SLOT_PCIE_2 0x1b +#define PCH_DEVFN_PCIE17 _PCH_DEVFN(PCIE_2, 0) +#define PCH_DEVFN_PCIE18 _PCH_DEVFN(PCIE_2, 1) +#define PCH_DEVFN_PCIE19 _PCH_DEVFN(PCIE_2, 2) +#define PCH_DEVFN_PCIE20 _PCH_DEVFN(PCIE_2, 3) +#define PCH_DEVFN_PCIE21 _PCH_DEVFN(PCIE_2, 4) +#define PCH_DEVFN_PCIE22 _PCH_DEVFN(PCIE_2, 5) +#define PCH_DEVFN_PCIE23 _PCH_DEVFN(PCIE_2, 6) +#define PCH_DEVFN_PCIE24 _PCH_DEVFN(PCIE_2, 7) +#define PCH_DEV_PCIE17 _PCH_DEV(PCIE_2, 0) +#define PCH_DEV_PCIE18 _PCH_DEV(PCIE_2, 1) +#define PCH_DEV_PCIE19 _PCH_DEV(PCIE_2, 2) +#define PCH_DEV_PCIE20 _PCH_DEV(PCIE_2, 3) +#define PCH_DEV_PCIE21 _PCH_DEV(PCIE_2, 4) +#define PCH_DEV_PCIE22 _PCH_DEV(PCIE_2, 5) +#define PCH_DEV_PCIE23 _PCH_DEV(PCIE_2, 6) +#define PCH_DEV_PCIE24 _PCH_DEV(PCIE_2, 7) + +#define PCH_DEV_SLOT_SIO3 0x1e +#define PCH_DEVFN_UART0 _PCH_DEVFN(SIO3, 0) +#define PCH_DEVFN_UART1 _PCH_DEVFN(SIO3, 1) +#define PCH_DEVFN_GSPI0 _PCH_DEVFN(SIO3, 2) +#define PCH_DEVFN_GSPI1 _PCH_DEVFN(SIO3, 3) +#define PCH_DEV_UART0 _PCH_DEV(SIO3, 0) +#define PCH_DEV_UART1 _PCH_DEV(SIO3, 1) +#define PCH_DEV_GSPI0 _PCH_DEV(SIO3, 2) +#define PCH_DEV_GSPI1 _PCH_DEV(SIO3, 3) + +#define PCH_DEV_SLOT_ESPI 0x1f +#define PCH_DEV_SLOT_LPC PCH_DEV_SLOT_ESPI +#define PCH_DEVFN_ESPI _PCH_DEVFN(ESPI, 0) +#define PCH_DEVFN_P2SB _PCH_DEVFN(ESPI, 1) +#define PCH_DEVFN_PMC _PCH_DEVFN(ESPI, 2) +#define PCH_DEVFN_HDA _PCH_DEVFN(ESPI, 3) +#define PCH_DEVFN_SMBUS _PCH_DEVFN(ESPI, 4) +#define PCH_DEVFN_SPI _PCH_DEVFN(ESPI, 5) +#define PCH_DEVFN_GBE _PCH_DEVFN(ESPI, 6) +#define PCH_DEVFN_TRACEHUB _PCH_DEVFN(ESPI, 7) +#define PCH_DEV_ESPI _PCH_DEV(ESPI, 0) +#define PCH_DEV_LPC PCH_DEV_ESPI +#define PCH_DEV_P2SB _PCH_DEV(ESPI, 1) + +#if !ENV_RAMSTAGE +/* + * PCH_DEV_PMC is intentionally not defined in RAMSTAGE since PMC device gets + * hidden from PCI bus after call to FSP-S. This leads to resource allocator + * dropping it from the root bus as unused device. All references to PCH_DEV_PMC + * would then return NULL and can go unnoticed if not handled properly. Since, + * this device does not have any special chip config associated with it, it is + * okay to not provide the definition for it in ramstage. + */ +#define PCH_DEV_PMC _PCH_DEV(ESPI, 2) +#endif + +#define PCH_DEV_HDA _PCH_DEV(ESPI, 3) +#define PCH_DEV_SMBUS _PCH_DEV(ESPI, 4) +#define PCH_DEV_SPI _PCH_DEV(ESPI, 5) +#define PCH_DEV_GBE _PCH_DEV(ESPI, 6) +#define PCH_DEV_TRACEHUB _PCH_DEV(ESPI, 7) + +#endif diff --git a/src/soc/intel/tigerlake/include/soc/pcr_ids.h b/src/soc/intel/tigerlake/include/soc/pcr_ids.h new file mode 100644 index 0000000000..16162d9ecc --- /dev/null +++ b/src/soc/intel/tigerlake/include/soc/pcr_ids.h @@ -0,0 +1,50 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* + * This file is created based on Intel Tiger Lake Processor PCH Datasheet + * Document number: 575857 + * Chapter number: 31-35 + */ + +#ifndef SOC_TIGERLAKE_PCR_H +#define SOC_TIGERLAKE_PCR_H +/* + * Port ids + */ +#define PID_EMMC 0x52 +#define PID_SDX 0x53 + +#define PID_GPIOCOM0 0x6e +#define PID_GPIOCOM1 0x6d +#define PID_GPIOCOM2 0x6c +#define PID_GPIOCOM4 0x6a +#define PID_GPIOCOM5 0x69 + +#define PID_DMI 0x88 +#define PID_PSTH 0x89 +#define PID_CSME0 0x90 +#define PID_ISCLK 0xad +#define PID_PSF1 0xba +#define PID_PSF2 0xbb +#define PID_PSF3 0xbc +#define PID_PSF4 0xbd +#define PID_SCS 0xc0 +#define PID_RTC 0xc3 +#define PID_ITSS 0xc4 +#define PID_ESPI 0xc7 +#define PID_SERIALIO 0xcb + +#endif diff --git a/src/soc/intel/tigerlake/include/soc/pm.h b/src/soc/intel/tigerlake/include/soc/pm.h new file mode 100644 index 0000000000..fb9b67bc23 --- /dev/null +++ b/src/soc/intel/tigerlake/include/soc/pm.h @@ -0,0 +1,181 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* + * This file is created based on Intel Tiger Lake Processor PCH Datasheet + * Document number: 575857 + * Chapter number: 4 + */ + +#ifndef _SOC_PM_H_ +#define _SOC_PM_H_ + +#define PM1_STS 0x00 +#define WAK_STS (1 << 15) +#define PCIEXPWAK_STS (1 << 14) +#define PRBTNOR_STS (1 << 11) +#define RTC_STS (1 << 10) +#define PWRBTN_STS (1 << 8) +#define GBL_STS (1 << 5) +#define BM_STS (1 << 4) +#define TMROF_STS (1 << 0) +#define PM1_EN 0x02 +#define PCIEXPWAK_DIS (1 << 14) +#define RTC_EN (1 << 10) +#define PWRBTN_EN (1 << 8) +#define GBL_EN (1 << 5) +#define TMROF_EN (1 << 0) +#define PM1_CNT 0x04 +#define GBL_RLS (1 << 2) +#define BM_RLD (1 << 1) +#define SCI_EN (1 << 0) +#define PM1_TMR 0x08 +#define SMI_EN 0x30 +#define XHCI_SMI_EN (1 << 31) +#define ME_SMI_EN (1 << 30) +#define ESPI_SMI_EN (1 << 28) +#define GPIO_UNLOCK_SMI_EN (1 << 27) +#define INTEL_USB2_EN (1 << 18) +#define LEGACY_USB2_EN (1 << 17) +#define PERIODIC_EN (1 << 14) +#define TCO_SMI_EN (1 << 13) +#define MCSMI_EN (1 << 11) +#define BIOS_RLS (1 << 7) +#define SWSMI_TMR_EN (1 << 6) +#define APMC_EN (1 << 5) +#define SLP_SMI_EN (1 << 4) +#define LEGACY_USB_EN (1 << 3) +#define BIOS_EN (1 << 2) +#define EOS (1 << 1) +#define GBL_SMI_EN (1 << 0) +#define SMI_STS 0x34 +#define SMI_STS_BITS 32 +#define XHCI_SMI_STS_BIT 31 +#define ME_SMI_STS_BIT 30 +#define ESPI_SMI_STS_BIT 28 +#define GPIO_UNLOCK_SMI_STS_BIT 27 +#define SPI_SMI_STS_BIT 26 +#define SCC_SMI_STS_BIT 25 +#define MONITOR_STS_BIT 21 +#define PCI_EXP_SMI_STS_BIT 20 +#define SMBUS_SMI_STS_BIT 16 +#define SERIRQ_SMI_STS_BIT 15 +#define PERIODIC_STS_BIT 14 +#define TCO_STS_BIT 13 +#define DEVMON_STS_BIT 12 +#define MCSMI_STS_BIT 11 +#define GPIO_STS_BIT 10 +#define GPE0_STS_BIT 9 +#define PM1_STS_BIT 8 +#define SWSMI_TMR_STS_BIT 6 +#define APM_STS_BIT 5 +#define SMI_ON_SLP_EN_STS_BIT 4 +#define LEGACY_USB_STS_BIT 3 +#define BIOS_STS_BIT 2 +#define GPE_CNTL 0x42 +#define SWGPE_CTRL (1 << 1) +#define DEVACT_STS 0x44 +#define PM2_CNT 0x50 + +#define GPE0_REG_MAX 4 +#define GPE0_REG_SIZE 32 +#define GPE0_STS(x) (0x60 + ((x) * 4)) +#define GPE_31_0 0 /* 0x60/0x70 = GPE[31:0] */ +#define GPE_63_32 1 /* 0x64/0x74 = GPE[63:32] */ +#define GPE_95_64 2 /* 0x68/0x78 = GPE[95:64] */ +#define GPE_STD 3 /* 0x6c/0x7c = Standard GPE */ +#define GPE_STS_RSVD GPE_STD +#define WADT_STS (1 << 18) +#define GPIO_T2_STS (1 << 15) +#define ESPI_STS (1 << 14) +#define PME_B0_STS (1 << 13) +#define ME_SCI_STS (1 << 12) +#define PME_STS (1 << 11) +#define BATLOW_STS (1 << 10) +#define PCI_EXP_STS (1 << 9) +#define SMB_WAK_STS (1 << 7) +#define TCOSCI_STS (1 << 6) +#define SWGPE_STS (1 << 2) +#define HOT_PLUG_STS (1 << 1) +#define GPE0_EN(x) (0x70 + ((x) * 4)) +#define WADT_EN (1 << 18) +#define GPIO_T2_EN (1 << 15) +#define ESPI_EN (1 << 14) +#define PME_B0_EN_BIT 13 +#define PME_B0_EN (1 << PME_B0_EN_BIT) +#define ME_SCI_EN (1 << 12) +#define PME_EN (1 << 11) +#define BATLOW_EN (1 << 10) +#define PCI_EXP_EN (1 << 9) +#define TCOSCI_EN (1 << 6) +#define SWGPE_EN (1 << 2) +#define HOT_PLUG_EN (1 << 1) + +#define EN_BLOCK 3 + +/* + * Enable SMI generation: + * - on APMC writes (io 0xb2) + * - on writes to SLP_EN (sleep states) + * - on writes to GBL_RLS (bios commands) + * - on eSPI events (does nothing on LPC systems) + * No SMIs: + * - on microcontroller writes (io 0x62/0x66) + * - on TCO events + */ +#define ENABLE_SMI_PARAMS \ + (APMC_EN | SLP_SMI_EN | GBL_SMI_EN | ESPI_SMI_EN | EOS) + +#define PSS_RATIO_STEP 2 +#define PSS_MAX_ENTRIES 8 +#define PSS_LATENCY_TRANSITION 10 +#define PSS_LATENCY_BUSMASTER 10 + +#if !defined(__ACPI__) + +#include +#include +#include +#include +#include + +struct chipset_power_state { + uint16_t pm1_sts; + uint16_t pm1_en; + uint32_t pm1_cnt; + uint16_t tco1_sts; + uint16_t tco2_sts; + uint32_t gpe0_sts[4]; + uint32_t gpe0_en[4]; + uint32_t gen_pmcon_a; + uint32_t gen_pmcon_b; + uint32_t gblrst_cause[2]; + uint32_t prev_sleep_state; +} __packed; + +/* Get base address PMC memory mapped registers. */ +uint8_t *pmc_mmio_regs(void); + +/* Get base address of TCO I/O registers. */ +uint16_t smbus_tco_regs(void); + +/* Set the DISB after DRAM init */ +void pmc_set_disb(void); + +/* Clear PMCON status bits */ +void pmc_clear_pmcon_sts(void); + +#endif /* !defined(__ACPI__) */ +#endif diff --git a/src/soc/intel/tigerlake/include/soc/smbus.h b/src/soc/intel/tigerlake/include/soc/smbus.h new file mode 100644 index 0000000000..9226fba4e1 --- /dev/null +++ b/src/soc/intel/tigerlake/include/soc/smbus.h @@ -0,0 +1,45 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* + * This file is created based on Intel Tiger Lake Processor PCH Datasheet + * Document number: 575857 + * Chapter number: 6 + */ + +#ifndef _SOC_TIGERLAKE_SMBUS_H_ +#define _SOC_TIGERLAKE_SMBUS_H_ + +/* IO and MMIO registers under primary BAR */ +/* Set address for PCH as SMBus slave role */ +#define SMB_RCV_SLVA 0x09 + +/* TCO registers and fields live behind TCOBASE I/O bar in SMBus device. */ +#define TCO1_STS 0x04 +#define TCO_TIMEOUT (1 << 3) +#define TCO2_STS 0x06 +#define TCO_STS_SECOND_TO (1 << 1) +#define TCO1_CNT 0x08 +#define TCO_LOCK (1 << 12) +#define TCO_TMR_HLT (1 << 11) + +/* + * Default slave address value for PCH. This value is set to match default + * value set by hardware. It is useful since PCH is able to respond even + * before CPU is up. This is reset by RSMRST# but not by PLTRST#. + */ +#define SMBUS_SLAVE_ADDR 0x44 + +#endif From baf6d6e203ed0fae762f40ba73c576034b6ffc40 Mon Sep 17 00:00:00 2001 From: Subrata Banik Date: Fri, 1 Nov 2019 18:23:33 +0530 Subject: [PATCH 0064/1242] soc/intel/tigerlake/romstage: Do initial SoC commit till romstage Clone entirely from Icelake List of changes on top off initial icelake clone 1. Replace "Icelake" with "Tigerlake" 2. Replace "icl" with "tgl" 3. Replace "icp" with "tgp" 4. Rename structure based on Icelake with Tigerlake 5. Remove and clean below files 5.a Clean up upd override in fsp_params.c, will be added once FSP available. 5.b Remove __weak functions from fsp_params.c 6. Add CPU/PCH/SA EDS document number and chapter number 7. Add required headers into include/soc/ from ICL directory Change-Id: I24980c196efb2c5569996ca4fb315c256cf9de87 Signed-off-by: Subrata Banik Reviewed-on: https://review.coreboot.org/c/coreboot/+/36552 Reviewed-by: Maulik V Vaghela Reviewed-by: Ronak Kanabar Reviewed-by: Rizwan Qureshi Reviewed-by: Arthur Heymans Reviewed-by: Furquan Shaikh Tested-by: build bot (Jenkins) --- .../intel/tigerlake/include/soc/romstage.h | 25 ++++ .../intel/tigerlake/include/soc/soc_chip.h | 21 +++ .../intel/tigerlake/include/soc/systemagent.h | 50 +++++++ src/soc/intel/tigerlake/romstage/Makefile.inc | 20 +++ src/soc/intel/tigerlake/romstage/fsp_params.c | 22 +++ src/soc/intel/tigerlake/romstage/pch.c | 27 ++++ src/soc/intel/tigerlake/romstage/romstage.c | 128 ++++++++++++++++++ .../intel/tigerlake/romstage/systemagent.c | 48 +++++++ 8 files changed, 341 insertions(+) create mode 100644 src/soc/intel/tigerlake/include/soc/romstage.h create mode 100644 src/soc/intel/tigerlake/include/soc/soc_chip.h create mode 100644 src/soc/intel/tigerlake/include/soc/systemagent.h create mode 100644 src/soc/intel/tigerlake/romstage/Makefile.inc create mode 100644 src/soc/intel/tigerlake/romstage/fsp_params.c create mode 100644 src/soc/intel/tigerlake/romstage/pch.c create mode 100644 src/soc/intel/tigerlake/romstage/romstage.c create mode 100644 src/soc/intel/tigerlake/romstage/systemagent.c diff --git a/src/soc/intel/tigerlake/include/soc/romstage.h b/src/soc/intel/tigerlake/include/soc/romstage.h new file mode 100644 index 0000000000..046e856920 --- /dev/null +++ b/src/soc/intel/tigerlake/include/soc/romstage.h @@ -0,0 +1,25 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _SOC_ROMSTAGE_H_ +#define _SOC_ROMSTAGE_H_ + +#include + +void mainboard_memory_init_params(FSPM_UPD *mupd); +void systemagent_early_init(void); +void pch_init(void); + +#endif /* _SOC_ROMSTAGE_H_ */ diff --git a/src/soc/intel/tigerlake/include/soc/soc_chip.h b/src/soc/intel/tigerlake/include/soc/soc_chip.h new file mode 100644 index 0000000000..3b02386375 --- /dev/null +++ b/src/soc/intel/tigerlake/include/soc/soc_chip.h @@ -0,0 +1,21 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the + * GNU General Public License for more details. + */ + +#ifndef _SOC_TIGERLAKE_SOC_CHIP_H_ +#define _SOC_TIGERLAKE_SOC_CHIP_H_ + +#include "../../chip.h" + +#endif /* _SOC_TIGERLAKE_SOC_CHIP_H_ */ diff --git a/src/soc/intel/tigerlake/include/soc/systemagent.h b/src/soc/intel/tigerlake/include/soc/systemagent.h new file mode 100644 index 0000000000..56a2bd8887 --- /dev/null +++ b/src/soc/intel/tigerlake/include/soc/systemagent.h @@ -0,0 +1,50 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* + * This file is created based on Intel Tiger Lake Processor SA Datasheet + * Document number: 571131 + * Chapter number: 3 + */ + +#ifndef SOC_TIGERLAKE_SYSTEMAGENT_H +#define SOC_TIGERLAKE_SYSTEMAGENT_H + +#include + +/* Device 0:0.0 PCI configuration space */ + +#define EPBAR 0x40 +#define DMIBAR 0x68 +#define SMRAM 0x88 /* System Management RAM Control */ +#define D_OPEN (1 << 6) +#define D_CLS (1 << 5) +#define D_LCK (1 << 4) +#define G_SMRAME (1 << 3) +#define C_BASE_SEG ((0 << 2) | (1 << 1) | (0 << 0)) + +#define BIOS_RESET_CPL 0x5da8 +#define EDRAMBAR 0x5408 +#define REGBAR 0x5420 + +#define MCH_PKG_POWER_LIMIT_LO 0x59a0 +#define MCH_PKG_POWER_LIMIT_HI 0x59a4 +#define MCH_DDR_POWER_LIMIT_LO 0x58e0 +#define MCH_DDR_POWER_LIMIT_HI 0x58e4 + +#define IMRBASE 0x6A40 +#define IMRLIMIT 0x6A48 + +#endif diff --git a/src/soc/intel/tigerlake/romstage/Makefile.inc b/src/soc/intel/tigerlake/romstage/Makefile.inc new file mode 100644 index 0000000000..8d151e3871 --- /dev/null +++ b/src/soc/intel/tigerlake/romstage/Makefile.inc @@ -0,0 +1,20 @@ +# +# This file is part of the coreboot project. +# +# Copyright (C) 2019 Intel Corporation +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; version 2 of the License. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# + +romstage-y += fsp_params.c +romstage-y += ../../../../cpu/intel/car/romstage.c +romstage-y += romstage.c +romstage-y += pch.c +romstage-y += systemagent.c diff --git a/src/soc/intel/tigerlake/romstage/fsp_params.c b/src/soc/intel/tigerlake/romstage/fsp_params.c new file mode 100644 index 0000000000..810cff4a20 --- /dev/null +++ b/src/soc/intel/tigerlake/romstage/fsp_params.c @@ -0,0 +1,22 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include + +void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version) +{ + /* TODO: Update with UPD override as FSP matures */ +} diff --git a/src/soc/intel/tigerlake/romstage/pch.c b/src/soc/intel/tigerlake/romstage/pch.c new file mode 100644 index 0000000000..88a7cc7163 --- /dev/null +++ b/src/soc/intel/tigerlake/romstage/pch.c @@ -0,0 +1,27 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include + +void pch_init(void) +{ + /* Programming TCO_BASE_ADDRESS and TCO Timer Halt */ + tco_configure(); + + /* Program SMBUS_BASE_ADDRESS and Enable it */ + smbus_common_init(); +} diff --git a/src/soc/intel/tigerlake/romstage/romstage.c b/src/soc/intel/tigerlake/romstage/romstage.c new file mode 100644 index 0000000000..17efc98fac --- /dev/null +++ b/src/soc/intel/tigerlake/romstage/romstage.c @@ -0,0 +1,128 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define FSP_SMBIOS_MEMORY_INFO_GUID \ +{ \ + 0xd4, 0x71, 0x20, 0x9b, 0x54, 0xb0, 0x0c, 0x4e, \ + 0x8d, 0x09, 0x11, 0xcf, 0x8b, 0x9f, 0x03, 0x23 \ +} + +/* Save the DIMM information for SMBIOS table 17 */ +static void save_dimm_info(void) +{ + int channel, dimm, dimm_max, index; + size_t hob_size; + const CONTROLLER_INFO *ctrlr_info; + const CHANNEL_INFO *channel_info; + const DIMM_INFO *src_dimm; + struct dimm_info *dest_dimm; + struct memory_info *mem_info; + const MEMORY_INFO_DATA_HOB *memory_info_hob; + const uint8_t smbios_memory_info_guid[16] = + FSP_SMBIOS_MEMORY_INFO_GUID; + + /* Locate the memory info HOB, presence validated by raminit */ + memory_info_hob = fsp_find_extension_hob_by_guid( + smbios_memory_info_guid, + &hob_size); + if (memory_info_hob == NULL || hob_size == 0) { + printk(BIOS_ERR, "SMBIOS MEMORY_INFO_DATA_HOB not found\n"); + return; + } + + /* + * Allocate CBMEM area for DIMM information used to populate SMBIOS + * table 17 + */ + mem_info = cbmem_add(CBMEM_ID_MEMINFO, sizeof(*mem_info)); + if (mem_info == NULL) { + printk(BIOS_ERR, "CBMEM entry for DIMM info missing\n"); + return; + } + memset(mem_info, 0, sizeof(*mem_info)); + + /* Describe the first N DIMMs in the system */ + index = 0; + dimm_max = ARRAY_SIZE(mem_info->dimm); + ctrlr_info = &memory_info_hob->Controller[0]; + for (channel = 0; channel < MAX_CH && index < dimm_max; channel++) { + channel_info = &ctrlr_info->ChannelInfo[channel]; + if (channel_info->Status != CHANNEL_PRESENT) + continue; + for (dimm = 0; dimm < MAX_DIMM && index < dimm_max; dimm++) { + src_dimm = &channel_info->DimmInfo[dimm]; + dest_dimm = &mem_info->dimm[index]; + + if (src_dimm->Status != DIMM_PRESENT) + continue; + + u8 memProfNum = memory_info_hob->MemoryProfile; + + /* Populate the DIMM information */ + dimm_info_fill(dest_dimm, + src_dimm->DimmCapacity, + memory_info_hob->MemoryType, + memory_info_hob->ConfiguredMemoryClockSpeed, + src_dimm->RankInDimm, + channel_info->ChannelId, + src_dimm->DimmId, + (const char *)src_dimm->ModulePartNum, + sizeof(src_dimm->ModulePartNum), + src_dimm->SpdSave + SPD_SAVE_OFFSET_SERIAL, + memory_info_hob->DataWidth, + memory_info_hob->VddVoltage[memProfNum], + memory_info_hob->EccSupport, + src_dimm->MfgId, + src_dimm->SpdModuleType); + index++; + } + } + mem_info->dimm_cnt = index; + printk(BIOS_DEBUG, "%d DIMMs found\n", mem_info->dimm_cnt); +} + +void mainboard_romstage_entry(void) +{ + bool s3wake; + struct chipset_power_state *ps = pmc_get_power_state(); + + /* Program MCHBAR, DMIBAR, GDXBAR and EDRAMBAR */ + systemagent_early_init(); + /* Program PCH init */ + pch_init(); + /* initialize Heci interface */ + heci_init(HECI1_BASE_ADDRESS); + + s3wake = pmc_fill_power_state(ps) == ACPI_S3; + fsp_memory_init(s3wake); + pmc_set_disb(); + if (!s3wake) + save_dimm_info(); +} diff --git a/src/soc/intel/tigerlake/romstage/systemagent.c b/src/soc/intel/tigerlake/romstage/systemagent.c new file mode 100644 index 0000000000..183089e9fb --- /dev/null +++ b/src/soc/intel/tigerlake/romstage/systemagent.c @@ -0,0 +1,48 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* + * This file is created based on Intel Tiger Lake Processor SA Datasheet + * Document number: 571131 + * Chapter number: 3 + */ + +#include +#include +#include +#include + +void systemagent_early_init(void) +{ + static const struct sa_mmio_descriptor soc_fixed_pci_resources[] = { + { MCHBAR, MCH_BASE_ADDRESS, MCH_BASE_SIZE, "MCHBAR" }, + { DMIBAR, DMI_BASE_ADDRESS, DMI_BASE_SIZE, "DMIBAR" }, + { EPBAR, EP_BASE_ADDRESS, EP_BASE_SIZE, "EPBAR" }, + }; + + static const struct sa_mmio_descriptor soc_fixed_mch_resources[] = { + { REGBAR, REG_BASE_ADDRESS, REG_BASE_SIZE, "REGBAR" }, + { EDRAMBAR, EDRAM_BASE_ADDRESS, EDRAM_BASE_SIZE, "EDRAMBAR" }, + }; + + /* Set Fixed MMIO address into PCI configuration space */ + sa_set_pci_bar(soc_fixed_pci_resources, + ARRAY_SIZE(soc_fixed_pci_resources)); + /* Set Fixed MMIO address into MCH base address */ + sa_set_mch_bar(soc_fixed_mch_resources, + ARRAY_SIZE(soc_fixed_mch_resources)); + /* Enable PAM registers */ + enable_pam_region(); +} From 91e89c5393535406f98f0f05354459a123f0885b Mon Sep 17 00:00:00 2001 From: Subrata Banik Date: Fri, 1 Nov 2019 18:30:01 +0530 Subject: [PATCH 0065/1242] soc/intel/tigerlake: Do initial SoC commit till ramstage Clone entirely from Icelake List of changes on top off initial icelake clone 1. Replace "Icelake" with "Tigerlake" 2. Replace "icl" with "tgl" 3. Replace "icp" with "tgp" 4. Rename structure based on Icelake with Tigerlake 5. Remove and clean below files 5.a Clean up upd override in fsp_params.c, will be added once FSP available. 5.b Remove __weak functions from fsp_params.c 5.c Remove dGPU over PCIE enable Kconfig option 6. Add CPU/PCH/SA EDS document number and chapter number 7. Remove unnecessary headers from .c files based on review Tiger Lake specific changes will follow in subsequent patches. 1. Include GPIO controller delta over ICL 2. FSP-S related UPD overrides as applicable Change-Id: Id95e2fa9b7a7c6b3b9233d2c438b25a6c4904bbb Signed-off-by: Ravi Sarawadi Signed-off-by: Subrata Banik Reviewed-on: https://review.coreboot.org/c/coreboot/+/36087 Reviewed-by: Maulik V Vaghela Reviewed-by: Ronak Kanabar Reviewed-by: Rizwan Qureshi Tested-by: build bot (Jenkins) --- src/soc/intel/tigerlake/Kconfig | 213 +++++++++++++ src/soc/intel/tigerlake/Makefile.inc | 58 ++++ src/soc/intel/tigerlake/acpi.c | 248 +++++++++++++++ src/soc/intel/tigerlake/chip.c | 175 +++++++++++ src/soc/intel/tigerlake/chip.h | 280 +++++++++++++++++ src/soc/intel/tigerlake/cpu.c | 268 ++++++++++++++++ src/soc/intel/tigerlake/elog.c | 132 ++++++++ src/soc/intel/tigerlake/espi.c | 248 +++++++++++++++ src/soc/intel/tigerlake/finalize.c | 126 ++++++++ src/soc/intel/tigerlake/fsp_params.c | 46 +++ src/soc/intel/tigerlake/gpio.c | 212 +++++++++++++ src/soc/intel/tigerlake/graphics.c | 94 ++++++ src/soc/intel/tigerlake/gspi.c | 37 +++ src/soc/intel/tigerlake/i2c.c | 62 ++++ src/soc/intel/tigerlake/include/soc/cpu.h | 49 +++ src/soc/intel/tigerlake/include/soc/gpe.h | 134 ++++++++ src/soc/intel/tigerlake/include/soc/gpio.h | 24 ++ .../intel/tigerlake/include/soc/gpio_defs.h | 276 +++++++++++++++++ .../tigerlake/include/soc/gpio_soc_defs.h | 292 ++++++++++++++++++ src/soc/intel/tigerlake/include/soc/irq.h | 106 +++++++ src/soc/intel/tigerlake/include/soc/itss.h | 26 ++ src/soc/intel/tigerlake/include/soc/msr.h | 24 ++ src/soc/intel/tigerlake/include/soc/nvs.h | 21 ++ src/soc/intel/tigerlake/include/soc/pmc.h | 151 +++++++++ .../intel/tigerlake/include/soc/ramstage.h | 27 ++ .../intel/tigerlake/include/soc/serialio.h | 48 +++ src/soc/intel/tigerlake/include/soc/smm.h | 38 +++ src/soc/intel/tigerlake/include/soc/usb.h | 152 +++++++++ src/soc/intel/tigerlake/lockdown.c | 78 +++++ src/soc/intel/tigerlake/p2sb.c | 49 +++ src/soc/intel/tigerlake/pmc.c | 114 +++++++ src/soc/intel/tigerlake/pmutil.c | 276 +++++++++++++++++ src/soc/intel/tigerlake/reset.c | 47 +++ src/soc/intel/tigerlake/sd.c | 43 +++ src/soc/intel/tigerlake/smihandler.c | 126 ++++++++ src/soc/intel/tigerlake/smmrelocate.c | 273 ++++++++++++++++ src/soc/intel/tigerlake/spi.c | 39 +++ src/soc/intel/tigerlake/systemagent.c | 73 +++++ src/soc/intel/tigerlake/uart.c | 76 +++++ 39 files changed, 4761 insertions(+) create mode 100644 src/soc/intel/tigerlake/Kconfig create mode 100644 src/soc/intel/tigerlake/Makefile.inc create mode 100644 src/soc/intel/tigerlake/acpi.c create mode 100644 src/soc/intel/tigerlake/chip.c create mode 100644 src/soc/intel/tigerlake/chip.h create mode 100644 src/soc/intel/tigerlake/cpu.c create mode 100644 src/soc/intel/tigerlake/elog.c create mode 100644 src/soc/intel/tigerlake/espi.c create mode 100644 src/soc/intel/tigerlake/finalize.c create mode 100644 src/soc/intel/tigerlake/fsp_params.c create mode 100644 src/soc/intel/tigerlake/gpio.c create mode 100644 src/soc/intel/tigerlake/graphics.c create mode 100644 src/soc/intel/tigerlake/gspi.c create mode 100644 src/soc/intel/tigerlake/i2c.c create mode 100644 src/soc/intel/tigerlake/include/soc/cpu.h create mode 100644 src/soc/intel/tigerlake/include/soc/gpe.h create mode 100644 src/soc/intel/tigerlake/include/soc/gpio.h create mode 100644 src/soc/intel/tigerlake/include/soc/gpio_defs.h create mode 100644 src/soc/intel/tigerlake/include/soc/gpio_soc_defs.h create mode 100644 src/soc/intel/tigerlake/include/soc/irq.h create mode 100644 src/soc/intel/tigerlake/include/soc/itss.h create mode 100644 src/soc/intel/tigerlake/include/soc/msr.h create mode 100644 src/soc/intel/tigerlake/include/soc/nvs.h create mode 100644 src/soc/intel/tigerlake/include/soc/pmc.h create mode 100644 src/soc/intel/tigerlake/include/soc/ramstage.h create mode 100644 src/soc/intel/tigerlake/include/soc/serialio.h create mode 100644 src/soc/intel/tigerlake/include/soc/smm.h create mode 100644 src/soc/intel/tigerlake/include/soc/usb.h create mode 100644 src/soc/intel/tigerlake/lockdown.c create mode 100644 src/soc/intel/tigerlake/p2sb.c create mode 100644 src/soc/intel/tigerlake/pmc.c create mode 100644 src/soc/intel/tigerlake/pmutil.c create mode 100644 src/soc/intel/tigerlake/reset.c create mode 100644 src/soc/intel/tigerlake/sd.c create mode 100644 src/soc/intel/tigerlake/smihandler.c create mode 100644 src/soc/intel/tigerlake/smmrelocate.c create mode 100644 src/soc/intel/tigerlake/spi.c create mode 100644 src/soc/intel/tigerlake/systemagent.c create mode 100644 src/soc/intel/tigerlake/uart.c diff --git a/src/soc/intel/tigerlake/Kconfig b/src/soc/intel/tigerlake/Kconfig new file mode 100644 index 0000000000..014606b882 --- /dev/null +++ b/src/soc/intel/tigerlake/Kconfig @@ -0,0 +1,213 @@ +config SOC_INTEL_TIGERLAKE + bool + help + Intel Tigerlake support + +if SOC_INTEL_TIGERLAKE + +config CPU_SPECIFIC_OPTIONS + def_bool y + select ACPI_INTEL_HARDWARE_SLEEP_VALUES + select ARCH_BOOTBLOCK_X86_32 + select ARCH_RAMSTAGE_X86_32 + select ARCH_ROMSTAGE_X86_32 + select ARCH_VERSTAGE_X86_32 + select BOOT_DEVICE_SPI_FLASH_RW_NOMMAP_EARLY if BOOT_DEVICE_SPI_FLASH + select BOOT_DEVICE_SUPPORTS_WRITES + select C_ENVIRONMENT_BOOTBLOCK + select CACHE_MRC_SETTINGS + select COMMON_FADT + select CPU_INTEL_FIRMWARE_INTERFACE_TABLE + select FSP_M_XIP + select GENERIC_GPIO_LIB + select HAVE_FSP_GOP + select INTEL_DESCRIPTOR_MODE_CAPABLE + select HAVE_SMI_HANDLER + select IDT_IN_EVERY_STAGE + select INTEL_GMA_ACPI + select INTEL_GMA_ADD_VBT if RUN_FSP_GOP + select IOAPIC + select MRC_SETTINGS_PROTECT + select PARALLEL_MP + select PARALLEL_MP_AP_WORK + select MICROCODE_BLOB_UNDISCLOSED + select PLATFORM_USES_FSP2_1 + select REG_SCRIPT + select SMP + select SOC_AHCI_PORT_IMPLEMENTED_INVERT + select PMC_GLOBAL_RESET_ENABLE_LOCK + select SOC_INTEL_COMMON + select SOC_INTEL_COMMON_ACPI_WAKE_SOURCE + select SOC_INTEL_COMMON_BLOCK + select SOC_INTEL_COMMON_BLOCK_ACPI + select SOC_INTEL_COMMON_BLOCK_CHIP_CONFIG + select SOC_INTEL_COMMON_BLOCK_CPU + select SOC_INTEL_COMMON_BLOCK_CPU_MPINIT + select SOC_INTEL_COMMON_BLOCK_EBDA + select SOC_INTEL_COMMON_BLOCK_GSPI_VERSION_2 + select SOC_INTEL_COMMON_BLOCK_HDA + select SOC_INTEL_COMMON_BLOCK_SA + select SOC_INTEL_COMMON_BLOCK_SMM + select SOC_INTEL_COMMON_BLOCK_SMM_IO_TRAP + select SOC_INTEL_COMMON_PCH_BASE + select SOC_INTEL_COMMON_RESET + select SSE2 + select SUPPORT_CPU_UCODE_IN_CBFS + select TSC_MONOTONIC_TIMER + select UDELAY_TSC + select UDK_2017_BINDING + select DISPLAY_FSP_VERSION_INFO + select HECI_DISABLE_USING_SMM + +config DCACHE_RAM_BASE + default 0xfef00000 + +config DCACHE_RAM_SIZE + default 0x40000 + help + The size of the cache-as-ram region required during bootblock + and/or romstage. + +config DCACHE_BSP_STACK_SIZE + hex + default 0x20400 + help + The amount of anticipated stack usage in CAR by bootblock and + other stages. In the case of FSP_USES_CB_STACK default value will be + sum of FSP-M stack requirement (128KiB) and CB romstage stack requirement (~1KiB). + +config FSP_TEMP_RAM_SIZE + hex + default 0x10000 + help + The amount of anticipated heap usage in CAR by FSP. + Refer to Platform FSP integration guide document to know + the exact FSP requirement for Heap setup. + +config IFD_CHIPSET + string + default "tgl" + +config IED_REGION_SIZE + hex + default 0x400000 + +config HEAP_SIZE + hex + default 0x8000 + +config MAX_ROOT_PORTS + int + default 16 + +config SMM_TSEG_SIZE + hex + default 0x800000 + +config SMM_RESERVED_SIZE + hex + default 0x200000 + +config PCR_BASE_ADDRESS + hex + default 0xfd000000 + help + This option allows you to select MMIO Base Address of sideband bus. + +config MMCONF_BASE_ADDRESS + hex + default 0xc0000000 + +config CPU_BCLK_MHZ + int + default 100 + +config SOC_INTEL_COMMON_BLOCK_GSPI_CLOCK_MHZ + int + default 120 + +config DRIVERS_I2C_DESIGNWARE_CLOCK_MHZ + int + default 133 + +config SOC_INTEL_COMMON_BLOCK_GSPI_MAX + int + default 3 + +config SOC_INTEL_I2C_DEV_MAX + int + default 6 + +config SOC_INTEL_UART_DEV_MAX + int + default 3 + +config CONSOLE_UART_BASE_ADDRESS + hex + default 0xfe032000 + depends on INTEL_LPSS_UART_FOR_CONSOLE + +# Clock divider parameters for 115200 baud rate +config SOC_INTEL_COMMON_LPSS_UART_CLK_M_VAL + hex + default 0x30 + +config SOC_INTEL_COMMON_LPSS_UART_CLK_N_VAL + hex + default 0xc35 + +config CHROMEOS + select CHROMEOS_RAMOOPS_DYNAMIC + +config VBOOT + select VBOOT_SEPARATE_VERSTAGE + select VBOOT_MUST_REQUEST_DISPLAY + select VBOOT_SAVE_RECOVERY_REASON_ON_REBOOT + select VBOOT_STARTS_IN_BOOTBLOCK + select VBOOT_VBNV_CMOS + select VBOOT_VBNV_CMOS_BACKUP_TO_FLASH + +config C_ENV_BOOTBLOCK_SIZE + hex + default 0xC000 + +config CBFS_SIZE + hex + default 0x200000 + +choice + prompt "Cache-as-ram implementation" + default USE_TIGERLAKE_CAR_NEM_ENHANCED + help + This option allows you to select how cache-as-ram (CAR) is set up. + +config USE_TIGERLAKE_CAR_NEM_ENHANCED + bool "Enhanced Non-evict mode" + select SOC_INTEL_COMMON_BLOCK_CAR + select INTEL_CAR_NEM_ENHANCED + help + A current limitation of NEM (Non-Evict mode) is that code and data + sizes are derived from the requirement to not write out any modified + cache line. With NEM, if there is no physical memory behind the + cached area, the modified data will be lost and NEM results will be + inconsistent. ENHANCED NEM guarantees that modified data is always + kept in cache while clean data is replaced. + +config USE_TIGERLAKE_FSP_CAR + bool "Use FSP CAR" + select FSP_CAR + help + Use FSP APIs to initialize and tear down the Cache-As-Ram. + +endchoice + +config FSP_HEADER_PATH + string "Location of FSP headers" + default "src/vendorcode/intel/fsp/fsp2_0/tigerlake/" + +config FSP_FD_PATH + string + depends on FSP_USE_REPO + default "3rdparty/fsp/TigerLakeFspBinPkg/Fsp.fd" + +endif diff --git a/src/soc/intel/tigerlake/Makefile.inc b/src/soc/intel/tigerlake/Makefile.inc new file mode 100644 index 0000000000..b402fa0d63 --- /dev/null +++ b/src/soc/intel/tigerlake/Makefile.inc @@ -0,0 +1,58 @@ +ifeq ($(CONFIG_SOC_INTEL_TIGERLAKE),y) + +subdirs-y += romstage +subdirs-y += ../../../cpu/intel/microcode +subdirs-y += ../../../cpu/intel/turbo +subdirs-y += ../../../cpu/x86/lapic +subdirs-y += ../../../cpu/x86/mtrr +subdirs-y += ../../../cpu/x86/smm +subdirs-y += ../../../cpu/x86/tsc + +# all (bootblock, verstage, romstage, postcar, ramstage) +all-y += gspi.c +all-y += i2c.c +all-y += pmutil.c +all-y += spi.c +all-y += uart.c + +bootblock-y += bootblock/bootblock.c +bootblock-y += bootblock/cpu.c +bootblock-y += bootblock/pch.c +bootblock-y += bootblock/report_platform.c +bootblock-y += espi.c +bootblock-y += gpio.c +bootblock-y += p2sb.c + +romstage-y += espi.c +romstage-y += gpio.c +romstage-y += reset.c + +ramstage-y += acpi.c +ramstage-y += chip.c +ramstage-y += cpu.c +ramstage-y += elog.c +ramstage-y += espi.c +ramstage-y += finalize.c +ramstage-y += fsp_params.c +ramstage-y += gpio.c +ramstage-y += graphics.c +ramstage-y += lockdown.c +ramstage-y += p2sb.c +ramstage-y += pmc.c +ramstage-y += reset.c +ramstage-y += smmrelocate.c +ramstage-y += systemagent.c +ramstage-y += sd.c + +smm-y += gpio.c +smm-y += p2sb.c +smm-y += pmc.c +smm-y += pmutil.c +smm-y += smihandler.c +smm-y += uart.c + + +CPPFLAGS_common += -I$(src)/soc/intel/tigerlake +CPPFLAGS_common += -I$(src)/soc/intel/tigerlake/include + +endif diff --git a/src/soc/intel/tigerlake/acpi.c b/src/soc/intel/tigerlake/acpi.c new file mode 100644 index 0000000000..225f4e8211 --- /dev/null +++ b/src/soc/intel/tigerlake/acpi.c @@ -0,0 +1,248 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/* + * List of supported C-states in this processor. + */ +enum { + C_STATE_C0, /* 0 */ + C_STATE_C1, /* 1 */ + C_STATE_C1E, /* 2 */ + C_STATE_C6_SHORT_LAT, /* 3 */ + C_STATE_C6_LONG_LAT, /* 4 */ + C_STATE_C7_SHORT_LAT, /* 5 */ + C_STATE_C7_LONG_LAT, /* 6 */ + C_STATE_C7S_SHORT_LAT, /* 7 */ + C_STATE_C7S_LONG_LAT, /* 8 */ + C_STATE_C8, /* 9 */ + C_STATE_C9, /* 10 */ + C_STATE_C10, /* 11 */ + NUM_C_STATES +}; + +#define MWAIT_RES(state, sub_state) \ + { \ + .addrl = (((state) << 4) | (sub_state)), \ + .space_id = ACPI_ADDRESS_SPACE_FIXED, \ + .bit_width = ACPI_FFIXEDHW_VENDOR_INTEL, \ + .bit_offset = ACPI_FFIXEDHW_CLASS_MWAIT, \ + .access_size = ACPI_FFIXEDHW_FLAG_HW_COORD, \ + } + +static const acpi_cstate_t cstate_map[NUM_C_STATES] = { + [C_STATE_C0] = {}, + [C_STATE_C1] = { + .latency = 0, + .power = C1_POWER, + .resource = MWAIT_RES(0, 0), + }, + [C_STATE_C1E] = { + .latency = 0, + .power = C1_POWER, + .resource = MWAIT_RES(0, 1), + }, + [C_STATE_C6_SHORT_LAT] = { + .latency = C_STATE_LATENCY_FROM_LAT_REG(0), + .power = C6_POWER, + .resource = MWAIT_RES(2, 0), + }, + [C_STATE_C6_LONG_LAT] = { + .latency = C_STATE_LATENCY_FROM_LAT_REG(0), + .power = C6_POWER, + .resource = MWAIT_RES(2, 1), + }, + [C_STATE_C7_SHORT_LAT] = { + .latency = C_STATE_LATENCY_FROM_LAT_REG(0), + .power = C7_POWER, + .resource = MWAIT_RES(3, 0), + }, + [C_STATE_C7_LONG_LAT] = { + .latency = C_STATE_LATENCY_FROM_LAT_REG(0), + .power = C7_POWER, + .resource = MWAIT_RES(3, 1), + }, + [C_STATE_C7S_SHORT_LAT] = { + .latency = C_STATE_LATENCY_FROM_LAT_REG(0), + .power = C7_POWER, + .resource = MWAIT_RES(3, 2), + }, + [C_STATE_C7S_LONG_LAT] = { + .latency = C_STATE_LATENCY_FROM_LAT_REG(0), + .power = C7_POWER, + .resource = MWAIT_RES(3, 3), + }, + [C_STATE_C8] = { + .latency = C_STATE_LATENCY_FROM_LAT_REG(0), + .power = C8_POWER, + .resource = MWAIT_RES(4, 0), + }, + [C_STATE_C9] = { + .latency = C_STATE_LATENCY_FROM_LAT_REG(0), + .power = C9_POWER, + .resource = MWAIT_RES(5, 0), + }, + [C_STATE_C10] = { + .latency = C_STATE_LATENCY_FROM_LAT_REG(0), + .power = C10_POWER, + .resource = MWAIT_RES(6, 0), + }, +}; + +static int cstate_set_non_s0ix[] = { + C_STATE_C1E, + C_STATE_C6_LONG_LAT, + C_STATE_C7S_LONG_LAT +}; + +static int cstate_set_s0ix[] = { + C_STATE_C1E, + C_STATE_C7S_LONG_LAT, + C_STATE_C10 +}; + +acpi_cstate_t *soc_get_cstate_map(size_t *entries) +{ + static acpi_cstate_t map[MAX(ARRAY_SIZE(cstate_set_s0ix), + ARRAY_SIZE(cstate_set_non_s0ix))]; + int *set; + int i; + + config_t *config = config_of_soc(); + + int is_s0ix_enable = config->s0ix_enable; + + if (is_s0ix_enable) { + *entries = ARRAY_SIZE(cstate_set_s0ix); + set = cstate_set_s0ix; + } else { + *entries = ARRAY_SIZE(cstate_set_non_s0ix); + set = cstate_set_non_s0ix; + } + + for (i = 0; i < *entries; i++) { + memcpy(&map[i], &cstate_map[set[i]], sizeof(acpi_cstate_t)); + map[i].ctype = i + 1; + } + return map; +} + +void soc_power_states_generation(int core_id, int cores_per_package) +{ + config_t *config = config_of_soc(); + + if (config->eist_enable) + /* Generate P-state tables */ + generate_p_state_entries(core_id, cores_per_package); +} + +void soc_fill_fadt(acpi_fadt_t *fadt) +{ + const uint16_t pmbase = ACPI_BASE_ADDRESS; + + config_t *config = config_of_soc(); + + if (!config->PmTimerDisabled) { + fadt->pm_tmr_blk = pmbase + PM1_TMR; + fadt->pm_tmr_len = 4; + fadt->x_pm_tmr_blk.space_id = 1; + fadt->x_pm_tmr_blk.bit_width = fadt->pm_tmr_len * 8; + fadt->x_pm_tmr_blk.bit_offset = 0; + fadt->x_pm_tmr_blk.access_size = 0; + fadt->x_pm_tmr_blk.addrl = pmbase + PM1_TMR; + fadt->x_pm_tmr_blk.addrh = 0x0; + } + + if (config->s0ix_enable) + fadt->flags |= ACPI_FADT_LOW_PWR_IDLE_S0; +} + +uint32_t soc_read_sci_irq_select(void) +{ + uintptr_t pmc_bar = soc_read_pmc_base(); + return read32((void *)pmc_bar + IRQ_REG); +} + +void acpi_create_gnvs(struct global_nvs_t *gnvs) +{ + config_t *config = config_of_soc(); + + /* Set unknown wake source */ + gnvs->pm1i = -1; + + /* CPU core count */ + gnvs->pcnt = dev_count_cpu(); + + if (CONFIG(CONSOLE_CBMEM)) + /* Update the mem console pointer. */ + gnvs->cbmc = (uintptr_t)cbmem_find(CBMEM_ID_CONSOLE); + + if (CONFIG(CHROMEOS)) { + /* Initialize Verified Boot data */ + chromeos_init_chromeos_acpi(&(gnvs->chromeos)); + if (CONFIG(EC_GOOGLE_CHROMEEC)) { + gnvs->chromeos.vbt2 = google_ec_running_ro() ? + ACTIVE_ECFW_RO : ACTIVE_ECFW_RW; + } else + gnvs->chromeos.vbt2 = ACTIVE_ECFW_RO; + } + + /* Enable DPTF based on mainboard configuration */ + gnvs->dpte = config->dptf_enable; + + /* Fill in the Wifi Region id */ + gnvs->cid1 = wifi_regulatory_domain(); + + /* Set USB2/USB3 wake enable bitmaps. */ + gnvs->u2we = config->usb2_wake_enable_bitmap; + gnvs->u3we = config->usb3_wake_enable_bitmap; +} + +uint32_t acpi_fill_soc_wake(uint32_t generic_pm1_en, + const struct chipset_power_state *ps) +{ + /* + * WAK_STS bit is set when the system is in one of the sleep states + * (via the SLP_EN bit) and an enabled wake event occurs. Upon setting + * this bit, the PMC will transition the system to the ON state and + * can only be set by hardware and can only be cleared by writing a one + * to this bit position. + */ + + generic_pm1_en |= WAK_STS | RTC_EN | PWRBTN_EN; + return generic_pm1_en; +} + +int soc_madt_sci_irq_polarity(int sci) +{ + return MP_IRQ_POLARITY_HIGH; +} diff --git a/src/soc/intel/tigerlake/chip.c b/src/soc/intel/tigerlake/chip.c new file mode 100644 index 0000000000..530893ceca --- /dev/null +++ b/src/soc/intel/tigerlake/chip.c @@ -0,0 +1,175 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#if CONFIG(HAVE_ACPI_TABLES) +const char *soc_acpi_name(const struct device *dev) +{ + if (dev->path.type == DEVICE_PATH_DOMAIN) + return "PCI0"; + + if (dev->path.type != DEVICE_PATH_PCI) + return NULL; + + switch (dev->path.pci.devfn) { + case SA_DEVFN_ROOT: return "MCHC"; + case SA_DEVFN_IGD: return "GFX0"; + case PCH_DEVFN_ISH: return "ISHB"; + case PCH_DEVFN_XHCI: return "XHCI"; + case PCH_DEVFN_USBOTG: return "XDCI"; + case PCH_DEVFN_THERMAL: return "THRM"; + case PCH_DEVFN_I2C0: return "I2C0"; + case PCH_DEVFN_I2C1: return "I2C1"; + case PCH_DEVFN_I2C2: return "I2C2"; + case PCH_DEVFN_I2C3: return "I2C3"; + case PCH_DEVFN_CSE: return "CSE1"; + case PCH_DEVFN_CSE_2: return "CSE2"; + case PCH_DEVFN_CSE_IDER: return "CSED"; + case PCH_DEVFN_CSE_KT: return "CSKT"; + case PCH_DEVFN_CSE_3: return "CSE3"; + case PCH_DEVFN_SATA: return "SATA"; + case PCH_DEVFN_UART2: return "UAR2"; + case PCH_DEVFN_I2C4: return "I2C4"; + case PCH_DEVFN_I2C5: return "I2C5"; + case PCH_DEVFN_PCIE1: return "RP01"; + case PCH_DEVFN_PCIE2: return "RP02"; + case PCH_DEVFN_PCIE3: return "RP03"; + case PCH_DEVFN_PCIE4: return "RP04"; + case PCH_DEVFN_PCIE5: return "RP05"; + case PCH_DEVFN_PCIE6: return "RP06"; + case PCH_DEVFN_PCIE7: return "RP07"; + case PCH_DEVFN_PCIE8: return "RP08"; + case PCH_DEVFN_PCIE9: return "RP09"; + case PCH_DEVFN_PCIE10: return "RP10"; + case PCH_DEVFN_PCIE11: return "RP11"; + case PCH_DEVFN_PCIE12: return "RP12"; + case PCH_DEVFN_PCIE13: return "RP13"; + case PCH_DEVFN_PCIE14: return "RP14"; + case PCH_DEVFN_PCIE15: return "RP15"; + case PCH_DEVFN_PCIE16: return "RP16"; + case PCH_DEVFN_PCIE17: return "RP17"; + case PCH_DEVFN_PCIE18: return "RP18"; + case PCH_DEVFN_PCIE19: return "RP19"; + case PCH_DEVFN_PCIE20: return "RP20"; + case PCH_DEVFN_PCIE21: return "RP21"; + case PCH_DEVFN_PCIE22: return "RP22"; + case PCH_DEVFN_PCIE23: return "RP23"; + case PCH_DEVFN_PCIE24: return "RP24"; + case PCH_DEVFN_UART0: return "UAR0"; + case PCH_DEVFN_UART1: return "UAR1"; + case PCH_DEVFN_GSPI0: return "SPI0"; + case PCH_DEVFN_GSPI1: return "SPI1"; + case PCH_DEVFN_GSPI2: return "SPI2"; + case PCH_DEVFN_EMMC: return "EMMC"; + case PCH_DEVFN_SDCARD: return "SDXC"; + /* Keeping ACPI device name coherent with ec.asl */ + case PCH_DEVFN_ESPI: return "LPCB"; + case PCH_DEVFN_P2SB: return "P2SB"; + case PCH_DEVFN_PMC: return "PMC_"; + case PCH_DEVFN_HDA: return "HDAS"; + case PCH_DEVFN_SMBUS: return "SBUS"; + case PCH_DEVFN_SPI: return "FSPI"; + case PCH_DEVFN_GBE: return "IGBE"; + case PCH_DEVFN_TRACEHUB:return "THUB"; + } + + return NULL; +} +#endif + +/* SoC rotine to fill GPIO PM mask and value for GPIO_MISCCFG register */ +static void soc_fill_gpio_pm_configuration(void) +{ + uint8_t value[TOTAL_GPIO_COMM]; + const config_t *config = config_of_soc(); + + if (config->gpio_override_pm) + memcpy(value, config->gpio_pm, sizeof(uint8_t) * + TOTAL_GPIO_COMM); + else + memset(value, MISCCFG_ENABLE_GPIO_PM_CONFIG, sizeof(uint8_t) * + TOTAL_GPIO_COMM); + + gpio_pm_configure(value, TOTAL_GPIO_COMM); +} + +void soc_init_pre_device(void *chip_info) +{ + /* Snapshot the current GPIO IRQ polarities. FSP is setting a + * default policy that doesn't honor boards' requirements. */ + itss_snapshot_irq_polarities(GPIO_IRQ_START, GPIO_IRQ_END); + + /* Perform silicon specific init. */ + fsp_silicon_init(romstage_handoff_is_resume()); + + /* Display FIRMWARE_VERSION_INFO_HOB */ + fsp_display_fvi_version_hob(); + + /* Restore GPIO IRQ polarities back to previous settings. */ + itss_restore_irq_polarities(GPIO_IRQ_START, GPIO_IRQ_END); + + soc_fill_gpio_pm_configuration(); +} + +static void pci_domain_set_resources(struct device *dev) +{ + assign_resources(dev->link_list); +} + +static struct device_operations pci_domain_ops = { + .read_resources = &pci_domain_read_resources, + .set_resources = &pci_domain_set_resources, + .scan_bus = &pci_domain_scan_bus, + #if CONFIG(HAVE_ACPI_TABLES) + .acpi_name = &soc_acpi_name, + #endif +}; + +static struct device_operations cpu_bus_ops = { + .read_resources = DEVICE_NOOP, + .set_resources = DEVICE_NOOP, + .enable_resources = DEVICE_NOOP, + .init = DEVICE_NOOP, + .acpi_fill_ssdt_generator = generate_cpu_entries, +}; + +static void soc_enable(struct device *dev) +{ + /* Set the operations if it is a special bus type */ + if (dev->path.type == DEVICE_PATH_DOMAIN) + dev->ops = &pci_domain_ops; + else if (dev->path.type == DEVICE_PATH_CPU_CLUSTER) + dev->ops = &cpu_bus_ops; +} + +struct chip_operations soc_intel_tigerlake_ops = { + CHIP_NAME("Intel Tigerlake") + .enable_dev = &soc_enable, + .init = &soc_init_pre_device, +}; diff --git a/src/soc/intel/tigerlake/chip.h b/src/soc/intel/tigerlake/chip.h new file mode 100644 index 0000000000..32dc02c666 --- /dev/null +++ b/src/soc/intel/tigerlake/chip.h @@ -0,0 +1,280 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _SOC_CHIP_H_ +#define _SOC_CHIP_H_ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +struct soc_intel_tigerlake_config { + + /* Common struct containing soc config data required by common code */ + struct soc_intel_common_config common_soc_config; + + /* GPE configuration */ + uint32_t gpe0_en_1; /* GPE0_EN_31_0 */ + uint32_t gpe0_en_2; /* GPE0_EN_63_32 */ + uint32_t gpe0_en_3; /* GPE0_EN_95_64 */ + uint32_t gpe0_en_4; /* GPE0_EN_127_96 / GPE_STD */ + + /* Gpio group routed to each dword of the GPE0 block. Values are + * of the form GPP_[A:G] or GPD. */ + uint8_t gpe0_dw0; /* GPE0_31_0 STS/EN */ + uint8_t gpe0_dw1; /* GPE0_63_32 STS/EN */ + uint8_t gpe0_dw2; /* GPE0_95_64 STS/EN */ + + /* Generic IO decode ranges */ + uint32_t gen1_dec; + uint32_t gen2_dec; + uint32_t gen3_dec; + uint32_t gen4_dec; + + /* Enable S0iX support */ + int s0ix_enable; + /* Enable DPTF support */ + int dptf_enable; + + /* Deep SX enable for both AC and DC */ + int deep_s3_enable_ac; + int deep_s3_enable_dc; + int deep_s5_enable_ac; + int deep_s5_enable_dc; + + /* Deep Sx Configuration + * DSX_EN_WAKE_PIN - Enable WAKE# pin + * DSX_EN_LAN_WAKE_PIN - Enable LAN_WAKE# pin + * DSX_DIS_AC_PRESENT_PD - Disable pull-down on AC_PRESENT pin */ + uint32_t deep_sx_config; + + /* TCC activation offset */ + uint32_t tcc_offset; + + uint64_t PlatformMemorySize; + uint8_t SmramMask; + uint8_t MrcFastBoot; + uint32_t TsegSize; + uint16_t MmioSize; + + /* DDR Frequency Limit. Maximum Memory Frequency Selections in Mhz. + * Options : 1067, 1333, 1600, 1867, 2133, 2400, 2667, 2933, 0(Auto) */ + uint16_t DdrFreqLimit; + + /* SAGV Low Frequency Selections in Mhz. + * Options : 1067, 1333, 1600, 1867, 2133, 2400, 2667, 2933, 0(Auto) */ + uint16_t FreqSaGvLow; + + /* SAGV Mid Frequency Selections in Mhz. + * Options : 1067, 1333, 1600, 1867, 2133, 2400, 2667, 2933, 0(Auto) */ + uint16_t FreqSaGvMid; + + /* System Agent dynamic frequency support. Only effects ULX/ULT CPUs. + * When enabled memory will be training at two different frequencies. + * 0:Disabled, 1:FixedLow, 2:FixedMid, 3:FixedHigh, 4:Enabled */ + enum { + SaGv_Disabled, + SaGv_FixedLow, + SaGv_FixedMid, + SaGv_FixedHigh, + SaGv_Enabled, + } SaGv; + + + /* Rank Margin Tool. 1:Enable, 0:Disable */ + uint8_t RMT; + + /* USB related */ + struct usb2_port_config usb2_ports[16]; + struct usb3_port_config usb3_ports[10]; + uint8_t SsicPortEnable; + /* Wake Enable Bitmap for USB2 ports */ + uint16_t usb2_wake_enable_bitmap; + /* Wake Enable Bitmap for USB3 ports */ + uint16_t usb3_wake_enable_bitmap; + + /* SATA related */ + uint8_t SataEnable; + uint8_t SataMode; + uint8_t SataSalpSupport; + uint8_t SataPortsEnable[8]; + uint8_t SataPortsDevSlp[8]; + + /* Audio related */ + uint8_t PchHdaEnable; + uint8_t PchHdaDspEnable; + + /* Enable/Disable HD Audio Link. Muxed with SSP0/SSP1/SNDW1 */ + uint8_t PchHdaAudioLinkHda; + uint8_t PchHdaAudioLinkDmic0; + uint8_t PchHdaAudioLinkDmic1; + uint8_t PchHdaAudioLinkSsp0; + uint8_t PchHdaAudioLinkSsp1; + uint8_t PchHdaAudioLinkSsp2; + uint8_t PchHdaAudioLinkSndw1; + uint8_t PchHdaAudioLinkSndw2; + uint8_t PchHdaAudioLinkSndw3; + uint8_t PchHdaAudioLinkSndw4; + + /* PCIe Root Ports */ + uint8_t PcieRpEnable[CONFIG_MAX_ROOT_PORTS]; + /* PCIe output clocks type to Pcie devices. + * 0-23: PCH rootport, 0x70: LAN, 0x80: unspecified but in use, + * 0xFF: not used */ + uint8_t PcieClkSrcUsage[CONFIG_MAX_ROOT_PORTS]; + /* PCIe ClkReq-to-ClkSrc mapping, number of clkreq signal assigned to + * clksrc. */ + uint8_t PcieClkSrcClkReq[CONFIG_MAX_ROOT_PORTS]; + + /* SMBus */ + uint8_t SmbusEnable; + + /* eMMC and SD */ + uint8_t ScsEmmcHs400Enabled; + /* Need to update DLL setting to get Emmc running at HS400 speed */ + uint8_t EmmcUseCustomDlls; + uint32_t EmmcTxCmdDelayRegValue; + uint32_t EmmcTxDataDelay1RegValue; + uint32_t EmmcTxDataDelay2RegValue; + uint32_t EmmcRxCmdDataDelay1RegValue; + uint32_t EmmcRxCmdDataDelay2RegValue; + uint32_t EmmcRxStrobeDelayRegValue; + + /* Enable if SD Card Power Enable Signal is Active High */ + uint8_t SdCardPowerEnableActiveHigh; + + /* Integrated Sensor */ + uint8_t PchIshEnable; + + /* Heci related */ + uint8_t Heci3Enabled; + + /* Gfx related */ + uint8_t IgdDvmt50PreAlloc; + uint8_t InternalGfx; + uint8_t SkipExtGfxScan; + + uint32_t GraphicsConfigPtr; + uint8_t Device4Enable; + + /* GPIO IRQ Select. The valid value is 14 or 15 */ + uint8_t GpioIrqRoute; + /* SCI IRQ Select. The valid value is 9, 10, 11, 20, 21, 22, 23 */ + uint8_t SciIrqSelect; + /* TCO IRQ Select. The valid value is 9, 10, 11, 20, 21, 22, 23 */ + uint8_t TcoIrqSelect; + uint8_t TcoIrqEnable; + + /* HeciEnabled decides the state of Heci1 at end of boot + * Setting to 0 (default) disables Heci1 and hides the device from OS */ + uint8_t HeciEnabled; + /* PL2 Override value in Watts */ + uint32_t tdp_pl2_override; + /* Intel Speed Shift Technology */ + uint8_t speed_shift_enable; + /* Enable VR specific mailbox command + * 00b - no VR specific cmd sent + * 01b - VR mailbox cmd specifically for the MPS IMPV8 VR will be sent + * 10b - VR specific cmd sent for PS4 exit issue + * 11b - Reserved */ + uint8_t SendVrMbxCmd; + + /* Enable/Disable EIST. 1b:Enabled, 0b:Disabled */ + uint8_t eist_enable; + + /* Enable C6 DRAM */ + uint8_t enable_c6dram; + + uint8_t PmTimerDisabled; + + /* Desired platform debug type. */ + enum { + DebugConsent_Disabled, + DebugConsent_DCI_DBC, + DebugConsent_DCI, + DebugConsent_USB3_DBC, + DebugConsent_XDP, /* XDP/Mipi60 */ + DebugConsent_USB2_DBC, + } DebugConsent; + /* + * SerialIO device mode selection: + * PchSerialIoDisabled, + * PchSerialIoPci, + * PchSerialIoHidden, + * PchSerialIoLegacyUart, + * PchSerialIoSkipInit + */ + uint8_t SerialIoI2cMode[CONFIG_SOC_INTEL_I2C_DEV_MAX]; + uint8_t SerialIoGSpiMode[CONFIG_SOC_INTEL_COMMON_BLOCK_GSPI_MAX]; + uint8_t SerialIoUartMode[CONFIG_SOC_INTEL_UART_DEV_MAX]; + /* + * GSPIn Default Chip Select Mode: + * 0:Hardware Mode, + * 1:Software Mode + */ + uint8_t SerialIoGSpiCsMode[CONFIG_SOC_INTEL_COMMON_BLOCK_GSPI_MAX]; + /* + * GSPIn Default Chip Select State: + * 0: Low, + * 1: High + */ + uint8_t SerialIoGSpiCsState[CONFIG_SOC_INTEL_COMMON_BLOCK_GSPI_MAX]; + + /* GPIO SD card detect pin */ + unsigned int sdcard_cd_gpio; + + /* Enable Pch iSCLK */ + uint8_t pch_isclk; + + /* CNVi BT Audio Offload: Enable/Disable BT Audio Offload. */ + enum { + PLATFORM_POR, + FORCE_ENABLE, + FORCE_DISABLE, + } CnviBtAudioOffload; + + /* + * Override GPIO PM configuration: + * 0: Use FSP default GPIO PM program, + * 1: coreboot to override GPIO PM program + */ + uint8_t gpio_override_pm; + + /* + * GPIO PM configuration: 0 to disable, 1 to enable power gating + * Bit 6-7: Reserved + * Bit 5: MISCCFG_GPSIDEDPCGEN + * Bit 4: MISCCFG_GPRCOMPCDLCGEN + * Bit 3: MISCCFG_GPRTCDLCGEN + * Bit 2: MISCCFG_GSXLCGEN + * Bit 1: MISCCFG_GPDPCGEN + * Bit 0: MISCCFG_GPDLCGEN + */ + uint8_t gpio_pm[TOTAL_GPIO_COMM]; +}; + +typedef struct soc_intel_tigerlake_config config_t; + +#endif diff --git a/src/soc/intel/tigerlake/cpu.c b/src/soc/intel/tigerlake/cpu.c new file mode 100644 index 0000000000..4174cd2d24 --- /dev/null +++ b/src/soc/intel/tigerlake/cpu.c @@ -0,0 +1,268 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* + * This file is created based on Intel Tiger Lake Processor CPU Datasheet + * Document number: 575683 + * Chapter number: 15 + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +static void soc_fsp_load(void) +{ + fsps_load(romstage_handoff_is_resume()); +} + +static void configure_isst(void) +{ + config_t *conf = config_of_soc(); + msr_t msr; + + if (conf->speed_shift_enable) { + /* + * Kernel driver checks CPUID.06h:EAX[Bit 7] to determine if HWP + * is supported or not. coreboot needs to configure MSR 0x1AA + * which is then reflected in the CPUID register. + */ + msr = rdmsr(MSR_MISC_PWR_MGMT); + msr.lo |= MISC_PWR_MGMT_ISST_EN; /* Enable Speed Shift */ + msr.lo |= MISC_PWR_MGMT_ISST_EN_INT; /* Enable Interrupt */ + msr.lo |= MISC_PWR_MGMT_ISST_EN_EPP; /* Enable EPP */ + wrmsr(MSR_MISC_PWR_MGMT, msr); + } else { + msr = rdmsr(MSR_MISC_PWR_MGMT); + msr.lo &= ~MISC_PWR_MGMT_ISST_EN; /* Disable Speed Shift */ + msr.lo &= ~MISC_PWR_MGMT_ISST_EN_INT; /* Disable Interrupt */ + msr.lo &= ~MISC_PWR_MGMT_ISST_EN_EPP; /* Disable EPP */ + wrmsr(MSR_MISC_PWR_MGMT, msr); + } +} + +static void configure_misc(void) +{ + msr_t msr; + + config_t *conf = config_of_soc(); + + msr = rdmsr(IA32_MISC_ENABLE); + msr.lo |= (1 << 0); /* Fast String enable */ + msr.lo |= (1 << 3); /* TM1/TM2/EMTTM enable */ + /* Set EIST status */ + cpu_set_eist(conf->eist_enable); + wrmsr(IA32_MISC_ENABLE, msr); + + /* Disable Thermal interrupts */ + msr.lo = 0; + msr.hi = 0; + wrmsr(IA32_THERM_INTERRUPT, msr); + + /* Enable package critical interrupt only */ + msr.lo = 1 << 4; + msr.hi = 0; + wrmsr(IA32_PACKAGE_THERM_INTERRUPT, msr); + + /* Enable PROCHOT */ + msr = rdmsr(MSR_POWER_CTL); + msr.lo |= (1 << 0); /* Enable Bi-directional PROCHOT as an input*/ + msr.lo |= (1 << 23); /* Lock it */ + wrmsr(MSR_POWER_CTL, msr); +} + +static void enable_lapic_tpr(void) +{ + msr_t msr; + + msr = rdmsr(MSR_PIC_MSG_CONTROL); + msr.lo &= ~(1 << 10); /* Enable APIC TPR updates */ + wrmsr(MSR_PIC_MSG_CONTROL, msr); +} + +static void configure_dca_cap(void) +{ + uint32_t feature_flag; + msr_t msr; + + /* Check feature flag in CPUID.(EAX=1):ECX[18]==1 */ + feature_flag = cpu_get_feature_flags_ecx(); + if (feature_flag & CPUID_DCA) { + msr = rdmsr(IA32_PLATFORM_DCA_CAP); + msr.lo |= 1; + wrmsr(IA32_PLATFORM_DCA_CAP, msr); + } +} + +static void enable_pm_timer_emulation(void) +{ + /* ACPI PM timer emulation */ + msr_t msr; + /* + * The derived frequency is calculated as follows: + * (CTC_FREQ * msr[63:32]) >> 32 = target frequency. + * Back solve the multiplier so the 3.579545MHz ACPI timer + * frequency is used. + */ + msr.hi = (3579545ULL << 32) / CTC_FREQ; + /* Set PM1 timer IO port and enable */ + msr.lo = (EMULATE_DELAY_VALUE << EMULATE_DELAY_OFFSET_VALUE) | + EMULATE_PM_TMR_EN | (ACPI_BASE_ADDRESS + PM1_TMR); + wrmsr(MSR_EMULATE_PM_TIMER, msr); +} + +static void set_energy_perf_bias(u8 policy) +{ + msr_t msr; + int ecx; + + /* Determine if energy efficient policy is supported. */ + ecx = cpuid_ecx(0x6); + if (!(ecx & (1 << 3))) + return; + + /* Energy Policy is bits 3:0 */ + msr = rdmsr(IA32_ENERGY_PERF_BIAS); + msr.lo &= ~0xf; + msr.lo |= policy & 0xf; + wrmsr(IA32_ENERGY_PERF_BIAS, msr); +} + +static void configure_c_states(void) +{ + msr_t msr; + + /* C-state Interrupt Response Latency Control 1 - package C6/C7 short */ + msr.hi = 0; + msr.lo = IRTL_VALID | IRTL_32768_NS | C_STATE_LATENCY_CONTROL_1_LIMIT; + wrmsr(MSR_C_STATE_LATENCY_CONTROL_1, msr); + + /* C-state Interrupt Response Latency Control 2 - package C6/C7 long */ + msr.hi = 0; + msr.lo = IRTL_VALID | IRTL_32768_NS | C_STATE_LATENCY_CONTROL_2_LIMIT; + wrmsr(MSR_C_STATE_LATENCY_CONTROL_2, msr); + + /* C-state Interrupt Response Latency Control 3 - package C8 */ + msr.hi = 0; + msr.lo = IRTL_VALID | IRTL_32768_NS | + C_STATE_LATENCY_CONTROL_3_LIMIT; + wrmsr(MSR_C_STATE_LATENCY_CONTROL_3, msr); + + /* C-state Interrupt Response Latency Control 4 - package C9 */ + msr.hi = 0; + msr.lo = IRTL_VALID | IRTL_32768_NS | + C_STATE_LATENCY_CONTROL_4_LIMIT; + wrmsr(MSR_C_STATE_LATENCY_CONTROL_4, msr); + + /* C-state Interrupt Response Latency Control 5 - package C10 */ + msr.hi = 0; + msr.lo = IRTL_VALID | IRTL_32768_NS | + C_STATE_LATENCY_CONTROL_5_LIMIT; + wrmsr(MSR_C_STATE_LATENCY_CONTROL_5, msr); +} + +/* All CPUs including BSP will run the following function. */ +void soc_core_init(struct device *cpu) +{ + /* Clear out pending MCEs */ + /* TODO(adurbin): This should only be done on a cold boot. Also, some + * of these banks are core vs package scope. For now every CPU clears + * every bank. */ + mca_configure(); + + /* Enable the local CPU apics */ + enable_lapic_tpr(); + setup_lapic(); + + /* Configure c-state interrupt response time */ + configure_c_states(); + + /* Configure Enhanced SpeedStep and Thermal Sensors */ + configure_misc(); + + /* Configure Intel Speed Shift */ + configure_isst(); + + /* Enable PM timer emulation */ + enable_pm_timer_emulation(); + + /* Enable Direct Cache Access */ + configure_dca_cap(); + + /* Set energy policy */ + set_energy_perf_bias(ENERGY_POLICY_NORMAL); + + /* Enable Turbo */ + enable_turbo(); +} + +static void per_cpu_smm_trigger(void) +{ + /* Relocate the SMM handler. */ + smm_relocate(); +} + +static void post_mp_init(void) +{ + /* Set Max Ratio */ + cpu_set_max_ratio(); + + /* + * Now that all APs have been relocated as well as the BSP let SMIs + * start flowing. + */ + smm_southbridge_enable(PWRBTN_EN | GBL_EN); + + /* Lock down the SMRAM space. */ + smm_lock(); +} + +static const struct mp_ops mp_ops = { + /* + * Skip Pre MP init MTRR programming as MTRRs are mirrored from BSP, + * that are set prior to ramstage. + * Real MTRRs programming are being done after resource allocation. + */ + .pre_mp_init = soc_fsp_load, + .get_cpu_count = get_cpu_count, + .get_smm_info = smm_info, + .get_microcode_info = get_microcode_info, + .pre_mp_smm_init = smm_initialize, + .per_cpu_smm_trigger = per_cpu_smm_trigger, + .relocation_handler = smm_relocation_handler, + .post_mp_init = post_mp_init, +}; + +void soc_init_cpus(struct bus *cpu_bus) +{ + if (mp_init_with_smm(cpu_bus, &mp_ops)) + printk(BIOS_ERR, "MP initialization failure.\n"); +} diff --git a/src/soc/intel/tigerlake/elog.c b/src/soc/intel/tigerlake/elog.c new file mode 100644 index 0000000000..2ec6b410df --- /dev/null +++ b/src/soc/intel/tigerlake/elog.c @@ -0,0 +1,132 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2015 Intel Corporation. + * Copyright 2019 Google LLC + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +static void pch_log_gpio_gpe(u32 gpe0_sts, u32 gpe0_en, int start) +{ + int i; + + gpe0_sts &= gpe0_en; + + for (i = 0; i <= 31; i++) { + if (gpe0_sts & (1 << i)) + elog_add_event_wake(ELOG_WAKE_SOURCE_GPIO, i + start); + } +} + +static void pch_log_wake_source(struct chipset_power_state *ps) +{ + /* Power Button */ + if (ps->pm1_sts & PWRBTN_STS) + elog_add_event_wake(ELOG_WAKE_SOURCE_PWRBTN, 0); + + /* RTC */ + if (ps->pm1_sts & RTC_STS) + elog_add_event_wake(ELOG_WAKE_SOURCE_RTC, 0); + + /* PCI Express (TODO: determine wake device) */ + if (ps->pm1_sts & PCIEXPWAK_STS) + elog_add_event_wake(ELOG_WAKE_SOURCE_PCIE, 0); + + /* PME (TODO: determine wake device) */ + if (ps->gpe0_sts[GPE_STD] & PME_STS) + elog_add_event_wake(ELOG_WAKE_SOURCE_PME, 0); + + /* Internal PME (TODO: determine wake device) */ + if (ps->gpe0_sts[GPE_STD] & PME_B0_STS) + elog_add_event_wake(ELOG_WAKE_SOURCE_PME_INTERNAL, 0); + + /* SMBUS Wake */ + if (ps->gpe0_sts[GPE_STD] & SMB_WAK_STS) + elog_add_event_wake(ELOG_WAKE_SOURCE_SMBUS, 0); + + /* Log GPIO events in set 1-3 */ + pch_log_gpio_gpe(ps->gpe0_sts[GPE_31_0], ps->gpe0_en[GPE_31_0], 0); + pch_log_gpio_gpe(ps->gpe0_sts[GPE_63_32], ps->gpe0_en[GPE_63_32], 32); + pch_log_gpio_gpe(ps->gpe0_sts[GPE_95_64], ps->gpe0_en[GPE_95_64], 64); + /* Treat the STD as an extension of GPIO to obtain visibility. */ + pch_log_gpio_gpe(ps->gpe0_sts[GPE_STD], ps->gpe0_en[GPE_STD], 96); +} + +static void pch_log_power_and_resets(struct chipset_power_state *ps) +{ + /* Thermal Trip */ + if (ps->gblrst_cause[0] & GBLRST_CAUSE0_THERMTRIP) + elog_add_event(ELOG_TYPE_THERM_TRIP); + + /* PWR_FLR Power Failure */ + if (ps->gen_pmcon_a & PWR_FLR) + elog_add_event(ELOG_TYPE_POWER_FAIL); + + /* SUS Well Power Failure */ + if (ps->gen_pmcon_a & SUS_PWR_FLR) + elog_add_event(ELOG_TYPE_SUS_POWER_FAIL); + + /* TCO Timeout */ + if (ps->prev_sleep_state != ACPI_S3 && + ps->tco2_sts & TCO_STS_SECOND_TO) + elog_add_event(ELOG_TYPE_TCO_RESET); + + /* Power Button Override */ + if (ps->pm1_sts & PRBTNOR_STS) + elog_add_event(ELOG_TYPE_POWER_BUTTON_OVERRIDE); + + /* RTC reset */ + if (ps->gen_pmcon_b & RTC_BATTERY_DEAD) + elog_add_event(ELOG_TYPE_RTC_RESET); + + /* Host Reset Status */ + if (ps->gen_pmcon_a & HOST_RST_STS) + elog_add_event(ELOG_TYPE_SYSTEM_RESET); + + /* ACPI Wake Event */ + if (ps->prev_sleep_state != ACPI_S0) + elog_add_event_byte(ELOG_TYPE_ACPI_WAKE, ps->prev_sleep_state); +} + +static void pch_log_state(void *unused) +{ + struct chipset_power_state *ps = pmc_get_power_state(); + + if (!ps) { + printk(BIOS_ERR, "chipset_power_state not found!\n"); + return; + } + + /* Power and Reset */ + pch_log_power_and_resets(ps); + + /* Wake Sources */ + if (ps->prev_sleep_state > ACPI_S0) + pch_log_wake_source(ps); +} + +BOOT_STATE_INIT_ENTRY(BS_DEV_INIT, BS_ON_EXIT, pch_log_state, NULL); + +void elog_gsmi_cb_platform_log_wake_source(void) +{ + struct chipset_power_state ps; + pmc_fill_pm_reg_info(&ps); + pch_log_wake_source(&ps); +} diff --git a/src/soc/intel/tigerlake/espi.c b/src/soc/intel/tigerlake/espi.c new file mode 100644 index 0000000000..932f76089d --- /dev/null +++ b/src/soc/intel/tigerlake/espi.c @@ -0,0 +1,248 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* + * This file is created based on Intel Tiger Lake Processor PCH Datasheet + * Document number: 575857 + * Chapter number: 2 + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/* +* As per the BWG, Chapter 5.9.1. "PCH BIOS component will reserve +* certain memory range as reserved range for BIOS usage. +* For this SOC, the range will be from 0FC800000h till FE7FFFFFh" +*/ +static const struct lpc_mmio_range tgl_lpc_fixed_mmio_ranges[] = { + { PCH_PRESERVED_BASE_ADDRESS, PCH_PRESERVED_BASE_SIZE }, + { 0, 0 } +}; + +const struct lpc_mmio_range *soc_get_fixed_mmio_ranges() +{ + return tgl_lpc_fixed_mmio_ranges; +} + +void soc_get_gen_io_dec_range(const struct device *dev, uint32_t *gen_io_dec) +{ + const config_t *config = config_of(dev); + + gen_io_dec[0] = config->gen1_dec; + gen_io_dec[1] = config->gen2_dec; + gen_io_dec[2] = config->gen3_dec; + gen_io_dec[3] = config->gen4_dec; +} + +void soc_setup_dmi_pcr_io_dec(uint32_t *gen_io_dec) +{ + /* Mirror these same settings in DMI PCR */ + pcr_write32(PID_DMI, PCR_DMI_LPCLGIR1, gen_io_dec[0]); + pcr_write32(PID_DMI, PCR_DMI_LPCLGIR2, gen_io_dec[1]); + pcr_write32(PID_DMI, PCR_DMI_LPCLGIR3, gen_io_dec[2]); + pcr_write32(PID_DMI, PCR_DMI_LPCLGIR4, gen_io_dec[3]); +} + +uint8_t get_pch_series(void) +{ + uint16_t lpc_did_hi_byte; + + /* + * Fetch upper 8 bits on ESPI device ID to determine PCH type + * Adding 1 to the offset to fetch upper 8 bits + */ + lpc_did_hi_byte = pci_read_config8(PCH_DEV_ESPI, PCI_DEVICE_ID + 1); + + if (lpc_did_hi_byte == 0x9D) + return PCH_LP; + else if (lpc_did_hi_byte == 0xA3) + return PCH_H; + else + return PCH_UNKNOWN_SERIES; +} + +#if ENV_RAMSTAGE +static void soc_mirror_dmi_pcr_io_dec(void) +{ + struct device *dev = pcidev_on_root(PCH_DEV_SLOT_ESPI, 0); + uint32_t io_dec_arr[] = { + pci_read_config32(dev, ESPI_GEN1_DEC), + pci_read_config32(dev, ESPI_GEN2_DEC), + pci_read_config32(dev, ESPI_GEN3_DEC), + pci_read_config32(dev, ESPI_GEN4_DEC), + }; + /* Mirror these same settings in DMI PCR */ + soc_setup_dmi_pcr_io_dec(&io_dec_arr[0]); +} + +static void pch_enable_ioapic(const struct device *dev) +{ + u32 reg32; + /* PCH-LP has 120 redirection entries */ + const int redir_entries = 120; + + set_ioapic_id((void *)IO_APIC_ADDR, 0x02); + + /* affirm full set of redirection table entries ("write once") */ + reg32 = io_apic_read((void *)IO_APIC_ADDR, 0x01); + + reg32 &= ~0x00ff0000; + reg32 |= (redir_entries - 1) << 16; + + io_apic_write((void *)IO_APIC_ADDR, 0x01, reg32); + + /* + * Select Boot Configuration register (0x03) and + * use Processor System Bus (0x01) to deliver interrupts. + */ + io_apic_write((void *)IO_APIC_ADDR, 0x03, 0x01); +} +/* + * PIRQ[n]_ROUT[3:0] - PIRQ Routing Control + * 0x00 - 0000 = Reserved + * 0x01 - 0001 = Reserved + * 0x02 - 0010 = Reserved + * 0x03 - 0011 = IRQ3 + * 0x04 - 0100 = IRQ4 + * 0x05 - 0101 = IRQ5 + * 0x06 - 0110 = IRQ6 + * 0x07 - 0111 = IRQ7 + * 0x08 - 1000 = Reserved + * 0x09 - 1001 = IRQ9 + * 0x0A - 1010 = IRQ10 + * 0x0B - 1011 = IRQ11 + * 0x0C - 1100 = IRQ12 + * 0x0D - 1101 = Reserved + * 0x0E - 1110 = IRQ14 + * 0x0F - 1111 = IRQ15 + * PIRQ[n]_ROUT[7] - PIRQ Routing Control + * 0x80 - The PIRQ is not routed. + */ + +void soc_pch_pirq_init(const struct device *dev) +{ + struct device *irq_dev; + uint8_t pch_interrupt_routing[MAX_PXRC_CONFIG]; + + pch_interrupt_routing[0] = PCH_IRQ11; + pch_interrupt_routing[1] = PCH_IRQ10; + pch_interrupt_routing[2] = PCH_IRQ11; + pch_interrupt_routing[3] = PCH_IRQ11; + pch_interrupt_routing[4] = PCH_IRQ11; + pch_interrupt_routing[5] = PCH_IRQ11; + pch_interrupt_routing[6] = PCH_IRQ11; + pch_interrupt_routing[7] = PCH_IRQ11; + + itss_irq_init(pch_interrupt_routing); + + for (irq_dev = all_devices; irq_dev; irq_dev = irq_dev->next) { + u8 int_pin = 0, int_line = 0; + + if (!irq_dev->enabled || irq_dev->path.type != DEVICE_PATH_PCI) + continue; + + int_pin = pci_read_config8(irq_dev, PCI_INTERRUPT_PIN); + + switch (int_pin) { + case 1: /* INTA# */ + int_line = PCH_IRQ11; + break; + case 2: /* INTB# */ + int_line = PCH_IRQ10; + break; + case 3: /* INTC# */ + int_line = PCH_IRQ11; + break; + case 4: /* INTD# */ + int_line = PCH_IRQ11; + break; + } + + if (!int_line) + continue; + + pci_write_config8(irq_dev, PCI_INTERRUPT_LINE, int_line); + } +} + +static void pch_misc_init(void) +{ + uint8_t reg8; + + /* Setup NMI on errors, disable SERR */ + reg8 = (inb(0x61)) & 0xf0; + outb((reg8 | (1 << 2)), 0x61); + + /* Disable NMI sources */ + outb((1 << 7), 0x70); +}; + +void lpc_soc_init(struct device *dev) +{ + /* Legacy initialization */ + isa_dma_init(); + pch_misc_init(); + + /* Enable CLKRUN_EN for power gating ESPI */ + lpc_enable_pci_clk_cntl(); + + /* Set ESPI Serial IRQ mode */ + if (CONFIG(SERIRQ_CONTINUOUS_MODE)) + lpc_set_serirq_mode(SERIRQ_CONTINUOUS); + else + lpc_set_serirq_mode(SERIRQ_QUIET); + + /* Interrupt configuration */ + pch_enable_ioapic(dev); + soc_pch_pirq_init(dev); + setup_i8259(); + i8259_configure_irq_trigger(9, 1); + soc_mirror_dmi_pcr_io_dec(); +} + +/* Fill up ESPI IO resource structure inside SoC directory */ +void pch_lpc_soc_fill_io_resources(struct device *dev) +{ + /* + * PMC pci device gets hidden from PCI bus due to Silicon + * policy hence bind ACPI BASE aka ABASE (offset 0x20) with + * ESPI IO resources to ensure that ABASE falls under PCI reserved + * IO memory range. + * + * Note: Don't add any more resource with same offset 0x20 + * under this device space. + */ + pch_lpc_add_new_resource(dev, PCI_BASE_ADDRESS_4, + ACPI_BASE_ADDRESS, ACPI_BASE_SIZE, IORESOURCE_IO | + IORESOURCE_ASSIGNED | IORESOURCE_FIXED); +} + +#endif diff --git a/src/soc/intel/tigerlake/finalize.c b/src/soc/intel/tigerlake/finalize.c new file mode 100644 index 0000000000..ac9dc24b50 --- /dev/null +++ b/src/soc/intel/tigerlake/finalize.c @@ -0,0 +1,126 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* + * This file is created based on Intel Tiger Lake Processor PCH Datasheet + * Document number: 575857 + * Chapter number: 4, 29 + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define CAMERA1_CLK 0x8000 /* Camera 1 Clock */ +#define CAMERA2_CLK 0x8080 /* Camera 2 Clock */ +#define CAM_CLK_EN (1 << 1) +#define MIPI_CLK (1 << 0) +#define HDPLL_CLK (0 << 0) + +static void pch_enable_isclk(void) +{ + pcr_or32(PID_ISCLK, CAMERA1_CLK, CAM_CLK_EN | MIPI_CLK); + pcr_or32(PID_ISCLK, CAMERA2_CLK, CAM_CLK_EN | MIPI_CLK); +} + +static void pch_handle_sideband(config_t *config) +{ + if (config->pch_isclk) + pch_enable_isclk(); +} + +static void pch_finalize(void) +{ + uint32_t reg32; + uint8_t *pmcbase; + config_t *config; + uint8_t reg8; + + /* TCO Lock down */ + tco_lockdown(); + + /* + * Set low maximum temp threshold value used for dynamic thermal sensor + * shutdown consideration. + * + * If Dynamic Thermal Shutdown is enabled then PMC logic shuts down the + * thermal sensor when CPU is in a C-state and DTS Temp <= LTT. + */ + pch_thermal_configuration(); + + /* + * Disable ACPI PM timer based on dt policy + * + * Disabling ACPI PM timer is necessary for XTAL OSC shutdown. + * Disabling ACPI PM timer also switches off TCO + * + * SA_DEV_ROOT device is used here instead of PCH_DEV_PMC since it is + * just required to get to chip config. PCH_DEV_PMC is hidden by this + * point and hence removed from the root bus. pcidev_path_on_root thus + * returns NULL for PCH_DEV_PMC device. + */ + config = config_of_soc(); + pmcbase = pmc_mmio_regs(); + if (config->PmTimerDisabled) { + reg8 = read8(pmcbase + PCH_PWRM_ACPI_TMR_CTL); + reg8 |= (1 << 1); + write8(pmcbase + PCH_PWRM_ACPI_TMR_CTL, reg8); + } + + /* Disable XTAL shutdown qualification for low power idle. */ + if (config->s0ix_enable) { + reg32 = read32(pmcbase + CPPMVRIC); + reg32 |= XTALSDQDIS; + write32(pmcbase + CPPMVRIC, reg32); + } + + pch_handle_sideband(config); + + pmc_clear_pmcon_sts(); +} + +static void soc_finalize(void *unused) +{ + printk(BIOS_DEBUG, "Finalizing chipset.\n"); + + pch_finalize(); + + printk(BIOS_DEBUG, "Finalizing SMM.\n"); + outb(APM_CNT_FINALIZE, APM_CNT); + + /* Indicate finalize step with post code */ + post_code(POST_OS_BOOT); +} + +BOOT_STATE_INIT_ENTRY(BS_OS_RESUME, BS_ON_ENTRY, soc_finalize, NULL); +BOOT_STATE_INIT_ENTRY(BS_PAYLOAD_LOAD, BS_ON_EXIT, soc_finalize, NULL); diff --git a/src/soc/intel/tigerlake/fsp_params.c b/src/soc/intel/tigerlake/fsp_params.c new file mode 100644 index 0000000000..18985a6495 --- /dev/null +++ b/src/soc/intel/tigerlake/fsp_params.c @@ -0,0 +1,46 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include + +static const pci_devfn_t serial_io_dev[] = { + PCH_DEVFN_I2C0, + PCH_DEVFN_I2C1, + PCH_DEVFN_I2C2, + PCH_DEVFN_I2C3, + PCH_DEVFN_I2C4, + PCH_DEVFN_I2C5, + PCH_DEVFN_GSPI0, + PCH_DEVFN_GSPI1, + PCH_DEVFN_GSPI2, + PCH_DEVFN_UART0, + PCH_DEVFN_UART1, + PCH_DEVFN_UART2 +}; + +/* UPD parameters to be initialized before SiliconInit */ +void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd) +{ + /* TODO: Update with UPD override as FSP matures */ +} + +/* Return list of SOC LPSS controllers */ +const pci_devfn_t *soc_lpss_controllers_list(size_t *size) +{ + *size = ARRAY_SIZE(serial_io_dev); + return serial_io_dev; +} diff --git a/src/soc/intel/tigerlake/gpio.c b/src/soc/intel/tigerlake/gpio.c new file mode 100644 index 0000000000..4a5880b824 --- /dev/null +++ b/src/soc/intel/tigerlake/gpio.c @@ -0,0 +1,212 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* + * This file is created based on Intel Tiger Lake Processor PCH Datasheet + * Document number: 575857 + * Chapter number: 27 + */ + +#include +#include +#include +#include + +static const struct reset_mapping rst_map[] = { + { .logical = PAD_CFG0_LOGICAL_RESET_RSMRST, .chipset = 0U << 30 }, + { .logical = PAD_CFG0_LOGICAL_RESET_DEEP, .chipset = 1U << 30 }, + { .logical = PAD_CFG0_LOGICAL_RESET_PLTRST, .chipset = 2U << 30 }, +}; + +static const struct reset_mapping rst_map_com0[] = { + { .logical = PAD_CFG0_LOGICAL_RESET_PWROK, .chipset = 0U << 30 }, + { .logical = PAD_CFG0_LOGICAL_RESET_DEEP, .chipset = 1U << 30 }, + { .logical = PAD_CFG0_LOGICAL_RESET_PLTRST, .chipset = 2U << 30 }, + { .logical = PAD_CFG0_LOGICAL_RESET_RSMRST, .chipset = 3U << 30 }, +}; + +/* + * The GPIO driver for Tigerlake on Windows/Linux expects 32 GPIOs per pad + * group, regardless of whether or not there is a physical pad for each + * exposed GPIO number. + * + * This results in the OS having a sparse GPIO map, and devices that need + * to export an ACPI GPIO must use the OS expected number. + * + * Not all pins are usable as GPIO and those groups do not have a pad base. + * + * This layout matches the Linux kernel pinctrl map for CNL-LP at: + * linux/drivers/pinctrl/intel/pinctrl-tigerlake.c + */ +static const struct pad_group tgl_community0_groups[] = { + INTEL_GPP_BASE(GPP_G0, GPP_G0, GPP_G7, 0), /* GPP_G */ + INTEL_GPP_BASE(GPP_G0, GPP_B0, GPP_B23, 32), /* GPP_B */ + INTEL_GPP(GPP_G0, GPIO_RSVD_0, GPIO_RSVD_1), + INTEL_GPP_BASE(GPP_G0, GPP_A0, GPP_A23, 64), /* GPP_A */ +}; + +static const struct pad_group tgl_community1_groups[] = { + INTEL_GPP_BASE(GPP_H0, GPP_H0, GPP_H23, 96), /* GPP_H */ + INTEL_GPP_BASE(GPP_H0, GPP_D0, GPIO_RSVD_2, 128), /* GPP_D */ + INTEL_GPP_BASE(GPP_H0, GPP_F0, GPP_F19, 160), /* GPP_F */ +}; + +/* This community is not visible to the OS */ +static const struct pad_group tgl_community2_groups[] = { + INTEL_GPP(GPD0, GPD0, GPD11), /* GPD */ +}; + + +static const struct pad_group tgl_community4_groups[] = { + INTEL_GPP_BASE(GPP_C0, GPP_C0, GPP_C23, 224), /* GPP_C */ + INTEL_GPP_BASE(GPP_C0, GPP_E0, GPP_E23, 256), /* GPP_E */ + INTEL_GPP(GPP_C0, GPIO_RSVD_3, GPIO_RSVD_8), +}; + + +static const struct pad_group tgl_community5_groups[] = { + INTEL_GPP_BASE(GPP_R0, GPP_R0, GPP_R7, 288), /* GPP_R */ + INTEL_GPP_BASE(GPP_C0, GPP_S0, GPP_S7, 320), /* GPP_S */ +}; + +static const struct pad_community tgl_communities[TOTAL_GPIO_COMM] = { + /* GPP G, B, A */ + [COMM_0] = { + .port = PID_GPIOCOM0, + .first_pad = GPP_G0, + .last_pad = GPP_A23, + .num_gpi_regs = NUM_GPIO_COM0_GPI_REGS, + .pad_cfg_base = PAD_CFG_BASE, + .host_own_reg_0 = HOSTSW_OWN_REG_0, + .gpi_int_sts_reg_0 = GPI_INT_STS_0, + .gpi_int_en_reg_0 = GPI_INT_EN_0, + .gpi_smi_sts_reg_0 = GPI_SMI_STS_0, + .gpi_smi_en_reg_0 = GPI_SMI_EN_0, + .max_pads_per_group = GPIO_MAX_NUM_PER_GROUP, + .name = "GPP_GBA", + .acpi_path = "\\_SB.PCI0.GPIO", + .reset_map = rst_map_com0, + .num_reset_vals = ARRAY_SIZE(rst_map_com0), + .groups = tgl_community0_groups, + .num_groups = ARRAY_SIZE(tgl_community0_groups), + }, + /* GPP H, D, F */ + [COMM_1] = { + .port = PID_GPIOCOM1, + .first_pad = GPP_H0, + .last_pad = GPP_F19, + .num_gpi_regs = NUM_GPIO_COM1_GPI_REGS, + .pad_cfg_base = PAD_CFG_BASE, + .host_own_reg_0 = HOSTSW_OWN_REG_0, + .gpi_int_sts_reg_0 = GPI_INT_STS_0, + .gpi_int_en_reg_0 = GPI_INT_EN_0, + .gpi_smi_sts_reg_0 = GPI_SMI_STS_0, + .gpi_smi_en_reg_0 = GPI_SMI_EN_0, + .max_pads_per_group = GPIO_MAX_NUM_PER_GROUP, + .name = "GPP_HDF", + .acpi_path = "\\_SB.PCI0.GPIO", + .reset_map = rst_map, + .num_reset_vals = ARRAY_SIZE(rst_map), + .groups = tgl_community1_groups, + .num_groups = ARRAY_SIZE(tgl_community1_groups), + }, + /* GPD */ + [COMM_2] = { + .port = PID_GPIOCOM2, + .first_pad = GPD0, + .last_pad = GPD11, + .num_gpi_regs = NUM_GPIO_COM2_GPI_REGS, + .pad_cfg_base = PAD_CFG_BASE, + .host_own_reg_0 = HOSTSW_OWN_REG_0, + .gpi_int_sts_reg_0 = GPI_INT_STS_0, + .gpi_int_en_reg_0 = GPI_INT_EN_0, + .gpi_smi_sts_reg_0 = GPI_SMI_STS_0, + .gpi_smi_en_reg_0 = GPI_SMI_EN_0, + .max_pads_per_group = GPIO_MAX_NUM_PER_GROUP, + .name = "GPD", + .acpi_path = "\\_SB.PCI0.GPIO", + .reset_map = rst_map, + .num_reset_vals = ARRAY_SIZE(rst_map), + .groups = tgl_community2_groups, + .num_groups = ARRAY_SIZE(tgl_community2_groups), + }, + /* GPP C, E */ + [COMM_3] = { + .port = PID_GPIOCOM4, + .first_pad = GPP_C0, + .last_pad = GPP_E23, + .num_gpi_regs = NUM_GPIO_COM4_GPI_REGS, + .pad_cfg_base = PAD_CFG_BASE, + .host_own_reg_0 = HOSTSW_OWN_REG_0, + .gpi_int_sts_reg_0 = GPI_INT_STS_0, + .gpi_int_en_reg_0 = GPI_INT_EN_0, + .gpi_smi_sts_reg_0 = GPI_SMI_STS_0, + .gpi_smi_en_reg_0 = GPI_SMI_EN_0, + .max_pads_per_group = GPIO_MAX_NUM_PER_GROUP, + .name = "GPP_CE", + .acpi_path = "\\_SB.PCI0.GPIO", + .reset_map = rst_map, + .num_reset_vals = ARRAY_SIZE(rst_map), + .groups = tgl_community4_groups, + .num_groups = ARRAY_SIZE(tgl_community4_groups), + }, + /* GPP R, S */ + [COMM_4] = { + .port = PID_GPIOCOM5, + .first_pad = GPP_R0, + .last_pad = GPP_S7, + .num_gpi_regs = NUM_GPIO_COM5_GPI_REGS, + .pad_cfg_base = PAD_CFG_BASE, + .host_own_reg_0 = HOSTSW_OWN_REG_0, + .gpi_int_sts_reg_0 = GPI_INT_STS_0, + .gpi_int_en_reg_0 = GPI_INT_EN_0, + .gpi_smi_sts_reg_0 = GPI_SMI_STS_0, + .gpi_smi_en_reg_0 = GPI_SMI_EN_0, + .max_pads_per_group = GPIO_MAX_NUM_PER_GROUP, + .name = "GPP_RS", + .acpi_path = "\\_SB.PCI0.GPIO", + .reset_map = rst_map, + .num_reset_vals = ARRAY_SIZE(rst_map), + .groups = tgl_community5_groups, + .num_groups = ARRAY_SIZE(tgl_community5_groups), + } +}; + +const struct pad_community *soc_gpio_get_community(size_t *num_communities) +{ + *num_communities = ARRAY_SIZE(tgl_communities); + return tgl_communities; +} + +const struct pmc_to_gpio_route *soc_pmc_gpio_routes(size_t *num) +{ + static const struct pmc_to_gpio_route routes[] = { + { PMC_GPP_G, GPP_G }, + { PMC_GPP_B, GPP_B }, + { PMC_GPP_A, GPP_A }, + { PMC_GPP_H, GPP_H }, + { PMC_GPP_D, GPP_D }, + { PMC_GPP_F, GPP_F }, + { PMC_GPD, GPD }, + { PMC_GPP_C, GPP_C }, + { PMC_GPP_E, GPP_E }, + { PMC_GPP_R, GPP_R }, + { PMC_GPP_S, GPP_S } + + }; + *num = ARRAY_SIZE(routes); + return routes; +} diff --git a/src/soc/intel/tigerlake/graphics.c b/src/soc/intel/tigerlake/graphics.c new file mode 100644 index 0000000000..c215384f10 --- /dev/null +++ b/src/soc/intel/tigerlake/graphics.c @@ -0,0 +1,94 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* + * This file is created based on Intel Tiger Lake Processor SA Datasheet + * Document number: 571131 + * Chapter number: 4 + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +uintptr_t fsp_soc_get_igd_bar(void) +{ + return graphics_get_memory_base(); +} + +void graphics_soc_init(struct device *dev) +{ + uint32_t ddi_buf_ctl; + + /* Skip IGD GT programming */ + if (CONFIG(SKIP_GRAPHICS_ENABLING)) + return; + + /* + * Enable DDI-A (eDP) 4-lane operation if the link is not up yet. + * This will allow the kernel to use 4-lane eDP links properly + * if the VBIOS or GOP driver do not execute. + */ + ddi_buf_ctl = graphics_gtt_read(DDI_BUF_CTL_A); + if (!acpi_is_wakeup_s3() && !(ddi_buf_ctl & DDI_BUF_CTL_ENABLE)) { + ddi_buf_ctl |= (DDI_A_4_LANES | DDI_INIT_DISPLAY_DETECTED | + DDI_BUF_IS_IDLE); + graphics_gtt_write(DDI_BUF_CTL_A, ddi_buf_ctl); + } + + /* + * GFX PEIM module inside FSP binary is taking care of graphics + * initialization based on RUN_FSP_GOP Kconfig + * option and input VBT file. Hence no need to load/execute legacy VGA + * OpROM in order to initialize GFX. + * + * In case of non-FSP solution, SoC need to select VGA_ROM_RUN + * Kconfig to perform GFX initialization through VGA OpRom. + */ + if (CONFIG(RUN_FSP_GOP)) + return; + + /* IGD needs to Bus Master */ + uint32_t reg32 = pci_read_config32(dev, PCI_COMMAND); + reg32 |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY | PCI_COMMAND_IO; + pci_write_config32(dev, PCI_COMMAND, reg32); + + /* Initialize PCI device, load/execute BIOS Option ROM */ + pci_dev_init(dev); +} + +uintptr_t graphics_soc_write_acpi_opregion(struct device *device, + uintptr_t current, struct acpi_rsdp *rsdp) +{ + igd_opregion_t *opregion; + + printk(BIOS_DEBUG, "ACPI: * IGD OpRegion\n"); + opregion = (igd_opregion_t *)current; + + if (intel_gma_init_igd_opregion(opregion) != CB_SUCCESS) + return current; + + current += sizeof(igd_opregion_t); + + return acpi_align_current(current); +} diff --git a/src/soc/intel/tigerlake/gspi.c b/src/soc/intel/tigerlake/gspi.c new file mode 100644 index 0000000000..2dc738ec97 --- /dev/null +++ b/src/soc/intel/tigerlake/gspi.c @@ -0,0 +1,37 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* + * This file is created based on Intel Tiger Lake Processor PCH Datasheet + * Document number: 575857 + * Chapter number: 11 + */ + +#include +#include + +int gspi_soc_bus_to_devfn(unsigned int gspi_bus) +{ + switch (gspi_bus) { + case 0: + return PCH_DEVFN_GSPI0; + case 1: + return PCH_DEVFN_GSPI1; + case 2: + return PCH_DEVFN_GSPI2; + } + return -1; +} diff --git a/src/soc/intel/tigerlake/i2c.c b/src/soc/intel/tigerlake/i2c.c new file mode 100644 index 0000000000..3d00372d59 --- /dev/null +++ b/src/soc/intel/tigerlake/i2c.c @@ -0,0 +1,62 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* + * This file is created based on Intel Tiger Lake Processor PCH Datasheet + * Document number: 575857 + * Chapter number: 13 + */ + +#include +#include +#include + +int dw_i2c_soc_devfn_to_bus(unsigned int devfn) +{ + switch (devfn) { + case PCH_DEVFN_I2C0: + return 0; + case PCH_DEVFN_I2C1: + return 1; + case PCH_DEVFN_I2C2: + return 2; + case PCH_DEVFN_I2C3: + return 3; + case PCH_DEVFN_I2C4: + return 4; + case PCH_DEVFN_I2C5: + return 5; + } + return -1; +} + +int dw_i2c_soc_bus_to_devfn(unsigned int bus) +{ + switch (bus) { + case 0: + return PCH_DEVFN_I2C0; + case 1: + return PCH_DEVFN_I2C1; + case 2: + return PCH_DEVFN_I2C2; + case 3: + return PCH_DEVFN_I2C3; + case 4: + return PCH_DEVFN_I2C4; + case 5: + return PCH_DEVFN_I2C5; + } + return -1; +} diff --git a/src/soc/intel/tigerlake/include/soc/cpu.h b/src/soc/intel/tigerlake/include/soc/cpu.h new file mode 100644 index 0000000000..210e6993ed --- /dev/null +++ b/src/soc/intel/tigerlake/include/soc/cpu.h @@ -0,0 +1,49 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2018 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _SOC_TIGERLAKE_CPU_H_ +#define _SOC_TIGERLAKE_CPU_H_ + +#include + +/* Latency times in units of 32768ns */ +#define C_STATE_LATENCY_CONTROL_0_LIMIT 0x9d +#define C_STATE_LATENCY_CONTROL_1_LIMIT 0x9d +#define C_STATE_LATENCY_CONTROL_2_LIMIT 0x9d +#define C_STATE_LATENCY_CONTROL_3_LIMIT 0x9d +#define C_STATE_LATENCY_CONTROL_4_LIMIT 0x9d +#define C_STATE_LATENCY_CONTROL_5_LIMIT 0x9d + +/* Power in units of mW */ +#define C1_POWER 0x3e8 +#define C6_POWER 0x15e +#define C7_POWER 0xc8 +#define C8_POWER 0xc8 +#define C9_POWER 0xc8 +#define C10_POWER 0xc8 + +/* Common Timer Copy (CTC) frequency - 38.4MHz. */ +#define CTC_FREQ 38400000 + +#define C_STATE_LATENCY_MICRO_SECONDS(limit, base) \ + (((1 << ((base)*5)) * (limit)) / 1000) +#define C_STATE_LATENCY_FROM_LAT_REG(reg) \ + C_STATE_LATENCY_MICRO_SECONDS(C_STATE_LATENCY_CONTROL_ ##reg## _LIMIT, \ + (IRTL_1024_NS >> 10)) + +/* Configure power limits for turbo mode */ +void set_power_limits(u8 power_limit_1_time); + +#endif diff --git a/src/soc/intel/tigerlake/include/soc/gpe.h b/src/soc/intel/tigerlake/include/soc/gpe.h new file mode 100644 index 0000000000..d946e2af13 --- /dev/null +++ b/src/soc/intel/tigerlake/include/soc/gpe.h @@ -0,0 +1,134 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2018 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _SOC_GPE_H_ +#define _SOC_GPE_H_ + +/* GPE_31_0 */ +#define GPE0_DW0_00 0 +#define GPE0_DW0_01 1 +#define GPE0_DW0_02 2 +#define GPE0_DW0_03 3 +#define GPE0_DW0_04 4 +#define GPE0_DW0_05 5 +#define GPE0_DW0_06 6 +#define GPE0_DW0_07 7 +#define GPE0_DW0_08 8 +#define GPE0_DW0_09 9 +#define GPE0_DW0_10 10 +#define GPE0_DW0_11 11 +#define GPE0_DW0_12 12 +#define GPE0_DW0_13 13 +#define GPE0_DW0_14 14 +#define GPE0_DW0_15 15 +#define GPE0_DW0_16 16 +#define GPE0_DW0_17 17 +#define GPE0_DW0_18 18 +#define GPE0_DW0_19 19 +#define GPE0_DW0_20 20 +#define GPE0_DW0_21 21 +#define GPE0_DW0_22 22 +#define GPE0_DW0_23 23 +#define GPE0_DW0_24 24 +#define GPE0_DW0_25 25 +#define GPE0_DW0_26 26 +#define GPE0_DW0_27 27 +#define GPE0_DW0_28 28 +#define GPE0_DW0_29 29 +#define GPE0_DW0_30 30 +#define GPE0_DW0_31 31 +/* GPE_63_32 */ +#define GPE0_DW1_00 32 +#define GPE0_DW1_01 33 +#define GPE0_DW1_02 34 +#define GPE0_DW1_03 36 +#define GPE0_DW1_04 36 +#define GPE0_DW1_05 37 +#define GPE0_DW1_06 38 +#define GPE0_DW1_07 39 +#define GPE0_DW1_08 40 +#define GPE0_DW1_09 41 +#define GPE0_DW1_10 42 +#define GPE0_DW1_11 43 +#define GPE0_DW1_12 44 +#define GPE0_DW1_13 45 +#define GPE0_DW1_14 46 +#define GPE0_DW1_15 47 +#define GPE0_DW1_16 48 +#define GPE0_DW1_17 49 +#define GPE0_DW1_18 50 +#define GPE0_DW1_19 51 +#define GPE0_DW1_20 52 +#define GPE0_DW1_21 53 +#define GPE0_DW1_22 54 +#define GPE0_DW1_23 55 +#define GPE0_DW1_24 56 +#define GPE0_DW1_25 57 +#define GPE0_DW1_26 58 +#define GPE0_DW1_27 59 +#define GPE0_DW1_28 60 +#define GPE0_DW1_29 61 +#define GPE0_DW1_30 62 +#define GPE0_DW1_31 63 +/* GPE_95_64 */ +#define GPE0_DW2_00 64 +#define GPE0_DW2_01 65 +#define GPE0_DW2_02 66 +#define GPE0_DW2_03 67 +#define GPE0_DW2_04 68 +#define GPE0_DW2_05 69 +#define GPE0_DW2_06 70 +#define GPE0_DW2_07 71 +#define GPE0_DW2_08 72 +#define GPE0_DW2_09 73 +#define GPE0_DW2_10 74 +#define GPE0_DW2_11 75 +#define GPE0_DW2_12 76 +#define GPE0_DW2_13 77 +#define GPE0_DW2_14 78 +#define GPE0_DW2_15 79 +#define GPE0_DW2_16 80 +#define GPE0_DW2_17 81 +#define GPE0_DW2_18 82 +#define GPE0_DW2_19 83 +#define GPE0_DW2_20 84 +#define GPE0_DW2_21 85 +#define GPE0_DW2_22 86 +#define GPE0_DW2_23 87 +#define GPE0_DW2_24 88 +#define GPE0_DW2_25 89 +#define GPE0_DW2_26 90 +#define GPE0_DW2_27 91 +#define GPE0_DW2_28 92 +#define GPE0_DW2_29 93 +#define GPE0_DW2_30 94 +#define GPE0_DW2_31 95 +/* GPE_STD */ +#define GPE0_HOT_PLUG 97 +#define GPE0_SWGPE 98 +#define GPE0_TCOSCI 102 +#define GPE0_SMB_WAK 103 +#define GPE0_PCI_EXP 105 +#define GPE0_BATLOW 106 +#define GPE0_PME 107 +#define GPE0_ME_SCI 108 +#define GPE0_PME_B0 109 +#define GPE0_ESPI 110 +#define GPE0_GPIO_T2 111 +#define GPE0_LAN_WAK 112 +#define GPE0_WADT 114 + +#define GPE_MAX GPE0_WADT +#endif /* _SOC_GPE_H_ */ diff --git a/src/soc/intel/tigerlake/include/soc/gpio.h b/src/soc/intel/tigerlake/include/soc/gpio.h new file mode 100644 index 0000000000..4b359b7452 --- /dev/null +++ b/src/soc/intel/tigerlake/include/soc/gpio.h @@ -0,0 +1,24 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2018 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _SOC_TIGERLAKE_GPIO_H_ +#define _SOC_TIGERLAKE_GPIO_H_ + +#include +#include + +#define CROS_GPIO_DEVICE_NAME "INT3455:00" + +#endif diff --git a/src/soc/intel/tigerlake/include/soc/gpio_defs.h b/src/soc/intel/tigerlake/include/soc/gpio_defs.h new file mode 100644 index 0000000000..bffebcd312 --- /dev/null +++ b/src/soc/intel/tigerlake/include/soc/gpio_defs.h @@ -0,0 +1,276 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2018 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _SOC_TIGERLAKE_GPIO_DEFS_H_ +#define _SOC_TIGERLAKE_GPIO_DEFS_H_ + +#ifndef __ACPI__ +#include +#endif +#include + + +#define GPIO_NUM_PAD_CFG_REGS 4 /* DW0, DW1, DW2, DW3 */ + +#define NUM_GPIO_COMx_GPI_REGS(n) \ + (ALIGN_UP((n), GPIO_MAX_NUM_PER_GROUP) / GPIO_MAX_NUM_PER_GROUP) + +#define NUM_GPIO_COM0_GPI_REGS NUM_GPIO_COMx_GPI_REGS(NUM_GPIO_COM0_PADS) +#define NUM_GPIO_COM1_GPI_REGS NUM_GPIO_COMx_GPI_REGS(NUM_GPIO_COM1_PADS) +#define NUM_GPIO_COM2_GPI_REGS NUM_GPIO_COMx_GPI_REGS(NUM_GPIO_COM2_PADS) +#define NUM_GPIO_COM4_GPI_REGS NUM_GPIO_COMx_GPI_REGS(NUM_GPIO_COM4_PADS) +#define NUM_GPIO_COM5_GPI_REGS NUM_GPIO_COMx_GPI_REGS(NUM_GPIO_COM5_PADS) + +#define NUM_GPI_STATUS_REGS \ + ((NUM_GPIO_COM0_GPI_REGS) +\ + (NUM_GPIO_COM1_GPI_REGS) +\ + (NUM_GPIO_COM2_GPI_REGS) +\ + (NUM_GPIO_COM4_GPI_REGS) +\ + (NUM_GPIO_COM5_GPI_REGS)) +/* + * IOxAPIC IRQs for the GPIOs + */ + +/* Group G */ +#define GPP_G0_IRQ 0x18 +#define GPP_G1_IRQ 0x19 +#define GPP_G2_IRQ 0x1a +#define GPP_G3_IRQ 0x1b +#define GPP_G4_IRQ 0x1c +#define GPP_G5_IRQ 0x1d +#define GPP_G6_IRQ 0x1e +#define GPP_G7_IRQ 0x1f + +/* Group B */ +#define GPP_B0_IRQ 0x20 +#define GPP_B1_IRQ 0x21 +#define GPP_B2_IRQ 0x22 +#define GPP_B3_IRQ 0x23 +#define GPP_B4_IRQ 0x24 +#define GPP_B5_IRQ 0x25 +#define GPP_B6_IRQ 0x26 +#define GPP_B7_IRQ 0x27 +#define GPP_B8_IRQ 0x28 +#define GPP_B9_IRQ 0x29 +#define GPP_B10_IRQ 0x2a +#define GPP_B11_IRQ 0x2b +#define GPP_B12_IRQ 0x2c +#define GPP_B13_IRQ 0x2d +#define GPP_B14_IRQ 0x2e +#define GPP_B15_IRQ 0x2f +#define GPP_B16_IRQ 0x30 +#define GPP_B17_IRQ 0x31 +#define GPP_B18_IRQ 0x32 +#define GPP_B19_IRQ 0x33 +#define GPP_B20_IRQ 0x34 +#define GPP_B21_IRQ 0x35 +#define GPP_B22_IRQ 0x36 +#define GPP_B23_IRQ 0x37 + +/* Group A */ +#define GPP_A0_IRQ 0x38 +#define GPP_A1_IRQ 0x39 +#define GPP_A2_IRQ 0x3a +#define GPP_A3_IRQ 0x3b +#define GPP_A4_IRQ 0x3c +#define GPP_A5_IRQ 0x3d +#define GPP_A6_IRQ 0x3e +#define GPP_A7_IRQ 0x3f +#define GPP_A8_IRQ 0x40 +#define GPP_A9_IRQ 0x41 +#define GPP_A10_IRQ 0x42 +#define GPP_A11_IRQ 0x43 +#define GPP_A12_IRQ 0x44 +#define GPP_A13_IRQ 0x45 +#define GPP_A14_IRQ 0x46 +#define GPP_A15_IRQ 0x47 +#define GPP_A16_IRQ 0x48 +#define GPP_A17_IRQ 0x49 +#define GPP_A18_IRQ 0x4a +#define GPP_A19_IRQ 0x4b +#define GPP_A20_IRQ 0x4c +#define GPP_A21_IRQ 0x4d +#define GPP_A22_IRQ 0x4e +#define GPP_A23_IRQ 0x4f + +/* Group H */ +#define GPP_H0_IRQ 0x70 +#define GPP_H1_IRQ 0x71 +#define GPP_H2_IRQ 0x72 +#define GPP_H3_IRQ 0x73 +#define GPP_H4_IRQ 0x74 +#define GPP_H5_IRQ 0x75 +#define GPP_H6_IRQ 0x76 +#define GPP_H7_IRQ 0x77 +#define GPP_H8_IRQ 0x18 +#define GPP_H9_IRQ 0x19 +#define GPP_H10_IRQ 0x1a +#define GPP_H11_IRQ 0x1b +#define GPP_H12_IRQ 0x1c +#define GPP_H13_IRQ 0x1d +#define GPP_H14_IRQ 0x1e +#define GPP_H15_IRQ 0x1f +#define GPP_H16_IRQ 0x20 +#define GPP_H17_IRQ 0x21 +#define GPP_H18_IRQ 0x22 +#define GPP_H19_IRQ 0x23 +#define GPP_H20_IRQ 0x24 +#define GPP_H21_IRQ 0x25 +#define GPP_H22_IRQ 0x26 +#define GPP_H23_IRQ 0x27 + +/* Group D */ +#define GPP_D0_IRQ 0x28 +#define GPP_D1_IRQ 0x29 +#define GPP_D2_IRQ 0x2a +#define GPP_D3_IRQ 0x2b +#define GPP_D4_IRQ 0x2c +#define GPP_D5_IRQ 0x2d +#define GPP_D6_IRQ 0x2e +#define GPP_D7_IRQ 0x2f +#define GPP_D8_IRQ 0x30 +#define GPP_D9_IRQ 0x31 +#define GPP_D10_IRQ 0x32 +#define GPP_D11_IRQ 0x33 +#define GPP_D12_IRQ 0x34 +#define GPP_D13_IRQ 0x35 +#define GPP_D14_IRQ 0x36 +#define GPP_D15_IRQ 0x37 +#define GPP_D16_IRQ 0x38 +#define GPP_D17_IRQ 0x39 +#define GPP_D18_IRQ 0x3a +#define GPP_D19_IRQ 0x3b + +/* Group F */ +#define GPP_F0_IRQ 0x40 +#define GPP_F1_IRQ 0x41 +#define GPP_F2_IRQ 0x42 +#define GPP_F3_IRQ 0x43 +#define GPP_F4_IRQ 0x44 +#define GPP_F5_IRQ 0x45 +#define GPP_F6_IRQ 0x46 +#define GPP_F7_IRQ 0x47 +#define GPP_F8_IRQ 0x48 +#define GPP_F9_IRQ 0x49 +#define GPP_F10_IRQ 0x4a +#define GPP_F11_IRQ 0x4b +#define GPP_F12_IRQ 0x4c +#define GPP_F13_IRQ 0x4d +#define GPP_F14_IRQ 0x4e +#define GPP_F15_IRQ 0x4f +#define GPP_F16_IRQ 0x50 +#define GPP_F17_IRQ 0x51 +#define GPP_F18_IRQ 0x52 +#define GPP_F19_IRQ 0x53 + +/* Group GPD */ +#define GPD0_IRQ 0x64 +#define GPD1_IRQ 0x65 +#define GPD2_IRQ 0x66 +#define GPD3_IRQ 0x67 +#define GPD4_IRQ 0x68 +#define GPD5_IRQ 0x69 +#define GPD6_IRQ 0x6a +#define GPD7_IRQ 0x6b +#define GPD8_IRQ 0x6c +#define GPD9_IRQ 0x6d +#define GPD10_IRQ 0x6e +#define GPD11_IRQ 0x6f + +/* Group C */ +#define GPP_C0_IRQ 0x5a +#define GPP_C1_IRQ 0x5b +#define GPP_C2_IRQ 0x5c +#define GPP_C3_IRQ 0x5d +#define GPP_C4_IRQ 0x5e +#define GPP_C5_IRQ 0x5f +#define GPP_C6_IRQ 0x60 +#define GPP_C7_IRQ 0x61 +#define GPP_C8_IRQ 0x62 +#define GPP_C9_IRQ 0x63 +#define GPP_C10_IRQ 0x64 +#define GPP_C11_IRQ 0x65 +#define GPP_C12_IRQ 0x66 +#define GPP_C13_IRQ 0x67 +#define GPP_C14_IRQ 0x68 +#define GPP_C15_IRQ 0x69 +#define GPP_C16_IRQ 0x6a +#define GPP_C17_IRQ 0x6b +#define GPP_C18_IRQ 0x6c +#define GPP_C19_IRQ 0x6d +#define GPP_C20_IRQ 0x6e +#define GPP_C21_IRQ 0x6f +#define GPP_C22_IRQ 0x70 +#define GPP_C23_IRQ 0x71 +/* Group E */ +#define GPP_E0_IRQ 0x72 +#define GPP_E1_IRQ 0x73 +#define GPP_E2_IRQ 0x74 +#define GPP_E3_IRQ 0x75 +#define GPP_E4_IRQ 0x76 +#define GPP_E5_IRQ 0x77 +#define GPP_E6_IRQ 0x18 +#define GPP_E7_IRQ 0x19 +#define GPP_E8_IRQ 0x1a +#define GPP_E9_IRQ 0x1b +#define GPP_E10_IRQ 0x1c +#define GPP_E11_IRQ 0x1d +#define GPP_E12_IRQ 0x1e +#define GPP_E13_IRQ 0x1f +#define GPP_E14_IRQ 0x20 +#define GPP_E15_IRQ 0x21 +#define GPP_E16_IRQ 0x22 +#define GPP_E17_IRQ 0x23 +#define GPP_E18_IRQ 0x24 +#define GPP_E19_IRQ 0x25 +#define GPP_E20_IRQ 0x26 +#define GPP_E21_IRQ 0x27 +#define GPP_E22_IRQ 0x28 +#define GPP_E23_IRQ 0x29 + +/* Group R*/ +#define GPP_R0_IRQ 0x50 +#define GPP_R1_IRQ 0x51 +#define GPP_R2_IRQ 0x52 +#define GPP_R3_IRQ 0x53 +#define GPP_R4_IRQ 0x54 +#define GPP_R5_IRQ 0x55 +#define GPP_R6_IRQ 0x56 +#define GPP_R7_IRQ 0x57 + +/* Group S */ +#define GPP_S0_IRQ 0x5c +#define GPP_S1_IRQ 0x5d +#define GPP_S2_IRQ 0x5e +#define GPP_S3_IRQ 0x5f +#define GPP_S4_IRQ 0x60 +#define GPP_S5_IRQ 0x61 +#define GPP_S6_IRQ 0x62 +#define GPP_S7_IRQ 0x63 + +/* Register defines. */ +#define GPIO_MISCCFG 0x10 +#define GPE_DW_SHIFT 8 +#define GPE_DW_MASK 0xfff00 +#define HOSTSW_OWN_REG_0 0xb0 +#define GPI_INT_STS_0 0x100 +#define GPI_INT_EN_0 0x110 +#define GPI_SMI_STS_0 0x180 +#define GPI_SMI_EN_0 0x1A0 +#define PAD_CFG_BASE 0x600 + +#define GPIORXSTATE_MASK 0x1 +#define GPIORXSTATE_SHIFT 1 +#endif diff --git a/src/soc/intel/tigerlake/include/soc/gpio_soc_defs.h b/src/soc/intel/tigerlake/include/soc/gpio_soc_defs.h new file mode 100644 index 0000000000..f0f2b11979 --- /dev/null +++ b/src/soc/intel/tigerlake/include/soc/gpio_soc_defs.h @@ -0,0 +1,292 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2018 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _SOC_TIGERLAKE_GPIO_SOC_DEFS_H_ +#define _SOC_TIGERLAKE_GPIO_SOC_DEFS_H_ + +/* + * Most of the fixed numbers and macros are based on the GPP groups. + * The GPIO groups are accessed through register blocks called + * communities. + */ +#define GPP_G 0x0 +#define GPP_B 0x1 +#define GPP_A 0x2 +#define GPP_R 0x3 +#define GPP_S 0x4 +#define GPD 0x5 +#define GPP_H 0x6 +#define GPP_D 0x7 +#define GPP_F 0x8 +#define GPP_VGPIO 0x9 +#define GPP_C 0xA +#define GPP_E 0xB + +#define GPIO_NUM_GROUPS 11 +#define GPIO_MAX_NUM_PER_GROUP 24 + +/* + * GPIOs are ordered monotonically increasing to match ACPI/OS driver. + */ + +/* Group G */ +#define GPP_G0 0 +#define GPP_G1 1 +#define GPP_G2 2 +#define GPP_G3 3 +#define GPP_G4 4 +#define GPP_G5 5 +#define GPP_G6 6 +#define GPP_G7 7 + +/* Group B */ +#define GPP_B0 8 +#define GPP_B1 9 +#define GPP_B2 10 +#define GPP_B3 11 +#define GPP_B4 12 +#define GPP_B5 13 +#define GPP_B6 14 +#define GPP_B7 15 +#define GPP_B8 16 +#define GPP_B9 17 +#define GPP_B10 18 +#define GPP_B11 19 +#define GPP_B12 20 +#define GPP_B13 21 +#define GPP_B14 22 +#define GPP_B15 23 +#define GPP_B16 24 +#define GPP_B17 25 +#define GPP_B18 26 +#define GPP_B19 27 +#define GPP_B20 28 +#define GPP_B21 29 +#define GPP_B22 30 +#define GPP_B23 31 +#define GPIO_RSVD_0 32 +#define GPIO_RSVD_1 33 + +/* Group A */ +#define GPP_A0 34 +#define GPP_A1 35 +#define GPP_A2 36 +#define GPP_A3 37 +#define GPP_A4 38 +#define GPP_A5 39 +#define GPP_A6 40 +#define GPP_A7 41 +#define GPP_A8 42 +#define GPP_A9 43 +#define GPP_A10 44 +#define GPP_A11 45 +#define GPP_A12 46 +#define GPP_A13 47 +#define GPP_A14 48 +#define GPP_A15 49 +#define GPP_A16 50 +#define GPP_A17 51 +#define GPP_A18 52 +#define GPP_A19 53 +#define GPP_A20 54 +#define GPP_A21 55 +#define GPP_A22 56 +#define GPP_A23 57 + +#define NUM_GPIO_COM0_PADS (GPP_A23 - GPP_G0 + 1) + +/* Group H */ +#define GPP_H0 58 +#define GPP_H1 59 +#define GPP_H2 60 +#define GPP_H3 61 +#define GPP_H4 62 +#define GPP_H5 63 +#define GPP_H6 64 +#define GPP_H7 65 +#define GPP_H8 66 +#define GPP_H9 67 +#define GPP_H10 68 +#define GPP_H11 69 +#define GPP_H12 70 +#define GPP_H13 71 +#define GPP_H14 72 +#define GPP_H15 73 +#define GPP_H16 74 +#define GPP_H17 75 +#define GPP_H18 76 +#define GPP_H19 77 +#define GPP_H20 78 +#define GPP_H21 79 +#define GPP_H22 80 +#define GPP_H23 81 + +/* Group D */ +#define GPP_D0 82 +#define GPP_D1 83 +#define GPP_D2 84 +#define GPP_D3 85 +#define GPP_D4 86 +#define GPP_D5 87 +#define GPP_D6 88 +#define GPP_D7 89 +#define GPP_D8 90 +#define GPP_D9 91 +#define GPP_D10 92 +#define GPP_D11 93 +#define GPP_D12 94 +#define GPP_D13 95 +#define GPP_D14 96 +#define GPP_D15 97 +#define GPP_D16 98 +#define GPP_D17 99 +#define GPP_D18 100 +#define GPP_D19 101 +#define GPIO_RSVD_2 102 + +/* Group F */ +#define GPP_F0 103 +#define GPP_F1 104 +#define GPP_F2 105 +#define GPP_F3 106 +#define GPP_F4 107 +#define GPP_F5 108 +#define GPP_F6 109 +#define GPP_F7 110 +#define GPP_F8 111 +#define GPP_F9 112 +#define GPP_F10 113 +#define GPP_F11 114 +#define GPP_F12 115 +#define GPP_F13 116 +#define GPP_F14 117 +#define GPP_F15 118 +#define GPP_F16 119 +#define GPP_F17 120 +#define GPP_F18 121 +#define GPP_F19 122 + +#define NUM_GPIO_COM1_PADS (GPP_F19 - GPP_H0 + 1) + + +/* Group GPD */ +#define GPD0 123 +#define GPD1 124 +#define GPD2 125 +#define GPD3 126 +#define GPD4 127 +#define GPD5 128 +#define GPD6 129 +#define GPD7 130 +#define GPD8 131 +#define GPD9 132 +#define GPD10 133 +#define GPD11 134 + +#define NUM_GPIO_COM2_PADS (GPD11 - GPD0 + 1) + + +/* Group C */ +#define GPP_C0 135 +#define GPP_C1 136 +#define GPP_C2 137 +#define GPP_C3 138 +#define GPP_C4 139 +#define GPP_C5 140 +#define GPP_C6 141 +#define GPP_C7 142 +#define GPP_C8 143 +#define GPP_C9 144 +#define GPP_C10 145 +#define GPP_C11 146 +#define GPP_C12 147 +#define GPP_C13 148 +#define GPP_C14 149 +#define GPP_C15 150 +#define GPP_C16 151 +#define GPP_C17 152 +#define GPP_C18 153 +#define GPP_C19 154 +#define GPP_C20 155 +#define GPP_C21 156 +#define GPP_C22 157 +#define GPP_C23 158 +#define GPIO_RSVD_3 159 +#define GPIO_RSVD_4 160 +#define GPIO_RSVD_5 161 +#define GPIO_RSVD_6 162 +#define GPIO_RSVD_7 163 +#define GPIO_RSVD_8 164 + +/* Group E */ +#define GPP_E0 165 +#define GPP_E1 166 +#define GPP_E2 167 +#define GPP_E3 168 +#define GPP_E4 169 +#define GPP_E5 170 +#define GPP_E6 171 +#define GPP_E7 172 +#define GPP_E8 173 +#define GPP_E9 174 +#define GPP_E10 175 +#define GPP_E11 176 +#define GPP_E12 177 +#define GPP_E13 178 +#define GPP_E14 179 +#define GPP_E15 180 +#define GPP_E16 181 +#define GPP_E17 182 +#define GPP_E18 183 +#define GPP_E19 184 +#define GPP_E20 185 +#define GPP_E21 186 +#define GPP_E22 187 +#define GPP_E23 188 + +#define NUM_GPIO_COM4_PADS (GPP_E23 - GPP_C0 + 1) + +/* Group R*/ +#define GPP_R0 189 +#define GPP_R1 190 +#define GPP_R2 191 +#define GPP_R3 192 +#define GPP_R4 193 +#define GPP_R5 194 +#define GPP_R6 195 +#define GPP_R7 196 + +/* Group S */ +#define GPP_S0 197 +#define GPP_S1 198 +#define GPP_S2 199 +#define GPP_S3 200 +#define GPP_S4 201 +#define GPP_S5 202 +#define GPP_S6 203 +#define GPP_S7 204 + +#define NUM_GPIO_COM5_PADS (GPP_S7 - GPP_R0 + 1) + +#define TOTAL_PADS 205 + +#define COMM_0 0 +#define COMM_1 1 +#define COMM_2 2 +#define COMM_3 3 +#define COMM_4 4 +#define TOTAL_GPIO_COMM 5 + +#endif diff --git a/src/soc/intel/tigerlake/include/soc/irq.h b/src/soc/intel/tigerlake/include/soc/irq.h new file mode 100644 index 0000000000..2f980ff472 --- /dev/null +++ b/src/soc/intel/tigerlake/include/soc/irq.h @@ -0,0 +1,106 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2018 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _SOC_IRQ_H_ +#define _SOC_IRQ_H_ + +#define GPIO_IRQ14 14 +#define GPIO_IRQ15 15 + +#define PCH_IRQ10 10 +#define PCH_IRQ11 11 + +#define SCI_IRQ9 9 +#define SCI_IRQ10 10 +#define SCI_IRQ11 11 +#define SCI_IRQ20 20 +#define SCI_IRQ21 21 +#define SCI_IRQ22 22 +#define SCI_IRQ23 23 + +#define TCO_IRQ9 9 +#define TCO_IRQ10 10 +#define TCO_IRQ11 11 +#define TCO_IRQ20 20 +#define TCO_IRQ21 21 +#define TCO_IRQ22 22 +#define TCO_IRQ23 23 + +#define LPSS_I2C0_IRQ 16 +#define LPSS_I2C1_IRQ 17 +#define LPSS_I2C2_IRQ 18 +#define LPSS_I2C3_IRQ 19 +#define LPSS_I2C4_IRQ 32 +#define LPSS_I2C5_IRQ 33 +#define LPSS_SPI0_IRQ 22 +#define LPSS_SPI1_IRQ 23 +#define LPSS_SPI2_IRQ 24 +#define LPSS_UART0_IRQ 20 +#define LPSS_UART1_IRQ 21 +#define LPSS_UART2_IRQ 34 +#define SDIO_IRQ 22 + +#define cAVS_INTA_IRQ 16 +#define SMBUS_INTA_IRQ 16 +#define SMBUS_INTB_IRQ 17 +#define GbE_INTA_IRQ 16 +#define GbE_INTC_IRQ 18 +#define TRACE_HUB_INTA_IRQ 16 +#define TRACE_HUB_INTD_IRQ 19 + +#define eMMC_IRQ 16 +#define SD_IRQ 19 + +#define PCIE_1_IRQ 16 +#define PCIE_2_IRQ 17 +#define PCIE_3_IRQ 18 +#define PCIE_4_IRQ 19 +#define PCIE_5_IRQ 16 +#define PCIE_6_IRQ 17 +#define PCIE_7_IRQ 18 +#define PCIE_8_IRQ 19 +#define PCIE_9_IRQ 16 +#define PCIE_10_IRQ 17 +#define PCIE_11_IRQ 18 +#define PCIE_12_IRQ 19 + +#define SATA_IRQ 16 + +#define HECI_1_IRQ 16 +#define HECI_2_IRQ 17 +#define IDER_IRQ 18 +#define KT_IRQ 19 +#define HECI_3_IRQ 16 + +#define XHCI_IRQ 16 +#define OTG_IRQ 17 +#define PMC_SRAM_IRQ 18 +#define THERMAL_IRQ 16 +#define CNViWIFI_IRQ 19 +#define UFS_IRQ 16 +#define CIO_INTA_IRQ 16 +#define CIO_INTD_IRQ 19 +#define ISH_IRQ 20 + +#define PEG_RP_INTA_IRQ 16 +#define PEG_RP_INTB_IRQ 17 +#define PEG_RP_INTC_IRQ 18 +#define PEG_RP_INTD_IRQ 19 + +#define IGFX_IRQ 16 +#define SA_THERMAL_IRQ 16 +#define IPU_IRQ 16 +#define GNA_IRQ 16 +#endif /* _SOC_IRQ_H_ */ diff --git a/src/soc/intel/tigerlake/include/soc/itss.h b/src/soc/intel/tigerlake/include/soc/itss.h new file mode 100644 index 0000000000..6631ccc27d --- /dev/null +++ b/src/soc/intel/tigerlake/include/soc/itss.h @@ -0,0 +1,26 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2018 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef SOC_INTEL_TGL_ITSS_H +#define SOC_INTEL_TGL_ITSS_H + +#define GPIO_IRQ_START 50 +#define GPIO_IRQ_END ITSS_MAX_IRQ + +#define ITSS_MAX_IRQ 119 +#define IRQS_PER_IPC 32 +#define NUM_IPC_REGS ((ITSS_MAX_IRQ + IRQS_PER_IPC - 1)/IRQS_PER_IPC) + +#endif /* SOC_INTEL_TGL_ITSS_H */ diff --git a/src/soc/intel/tigerlake/include/soc/msr.h b/src/soc/intel/tigerlake/include/soc/msr.h new file mode 100644 index 0000000000..2aa79af3d7 --- /dev/null +++ b/src/soc/intel/tigerlake/include/soc/msr.h @@ -0,0 +1,24 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2018 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _SOC_MSR_H_ +#define _SOC_MSR_H_ + +#include + +#define MSR_PIC_MSG_CONTROL 0x2e +#define MSR_VR_MISC_CONFIG2 0x636 + +#endif diff --git a/src/soc/intel/tigerlake/include/soc/nvs.h b/src/soc/intel/tigerlake/include/soc/nvs.h new file mode 100644 index 0000000000..c855df0305 --- /dev/null +++ b/src/soc/intel/tigerlake/include/soc/nvs.h @@ -0,0 +1,21 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2018 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _SOC_NVS_H_ +#define _SOC_NVS_H_ + +#include + +#endif diff --git a/src/soc/intel/tigerlake/include/soc/pmc.h b/src/soc/intel/tigerlake/include/soc/pmc.h new file mode 100644 index 0000000000..bae04ab352 --- /dev/null +++ b/src/soc/intel/tigerlake/include/soc/pmc.h @@ -0,0 +1,151 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2018 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _SOC_TIGERLAKE_PMC_H_ +#define _SOC_TIGERLAKE_PMC_H_ + +/* PCI Configuration Space (D31:F2): PMC */ +#define PWRMBASE 0x10 +#define ABASE 0x20 + +/* Memory mapped IO registers in PMC */ +#define GEN_PMCON_A 0x1020 +#define DC_PP_DIS (1 << 30) +#define DSX_PP_DIS (1 << 29) +#define AG3_PP_EN (1 << 28) +#define SX_PP_EN (1 << 27) +#define ALLOW_ICLK_PLL_SD_INC0 (1 << 26) +#define GBL_RST_STS (1 << 24) +#define DISB (1 << 23) +#define ALLOW_OPI_PLL_SD_INC0 (1 << 22) +#define MEM_SR (1 << 21) +#define ALLOW_SPXB_CG_INC0 (1 << 20) +#define ALLOW_L1LOW_C0 (1 << 19) +#define MS4V (1 << 18) +#define ALLOW_L1LOW_OPI_ON (1 << 17) +#define SUS_PWR_FLR (1 << 16) +#define PME_B0_S5_DIS (1 << 15) +#define PWR_FLR (1 << 14) +#define ALLOW_L1LOW_BCLKREQ_ON (1 << 13) +#define DIS_SLP_X_STRCH_SUS_UP (1 << 12) +#define SLP_S3_MIN_ASST_WDTH_MASK (3 << 10) +#define SLP_S3_MIN_ASST_WDTH_60USEC (0 << 10) +#define SLP_S3_MIN_ASST_WDTH_1MS (1 << 10) +#define SLP_S3_MIN_ASST_WDTH_50MS (2 << 10) +#define SLP_S3_MIN_ASST_WDTH_2S (3 << 10) +#define HOST_RST_STS (1 << 9) +#define ESPI_SMI_LOCK (1 << 8) +#define S4MAW_MASK (3 << 4) +#define S4MAW_1S (1 << 4) +#define S4MAW_2S (2 << 4) +#define S4MAW_3S (3 << 4) +#define S4MAW_4S (0 << 4) +#define S4ASE (1 << 3) +#define PER_SMI_SEL_MASK (3 << 1) +#define SMI_RATE_64S (0 << 1) +#define SMI_RATE_32S (1 << 1) +#define SMI_RATE_16S (2 << 1) +#define SMI_RATE_8S (3 << 1) +#define SLEEP_AFTER_POWER_FAIL (1 << 0) + +#define GEN_PMCON_B 0x1024 +#define SLP_STR_POL_LOCK (1 << 18) +#define ACPI_BASE_LOCK (1 << 17) +#define PM_DATA_BAR_DIS (1 << 16) +#define WOL_EN_OVRD (1 << 13) +#define BIOS_PCI_EXP_EN (1 << 10) +#define PWRBTN_LVL (1 << 9) +#define SMI_LOCK (1 << 4) +#define RTC_BATTERY_DEAD (1 << 2) + +#define ETR 0x1048 +#define CF9_LOCK (1 << 31) +#define CF9_GLB_RST (1 << 20) + +#define SSML 0x104C +#define SSML_SSL_DS (0 << 0) +#define SSML_SSL_EN (1 << 0) + +#define SSMC 0x1050 +#define SSMC_SSMS (1 << 0) + +#define SSMD 0x1054 +#define SSMD_SSD_MASK (0xffff << 0) + +#define PRSTS 0x1810 + +#define S3_PWRGATE_POL 0x1828 +#define S3DC_GATE_SUS (1 << 1) +#define S3AC_GATE_SUS (1 << 0) + +#define S4_PWRGATE_POL 0x182c +#define S4DC_GATE_SUS (1 << 1) +#define S4AC_GATE_SUS (1 << 0) + +#define S5_PWRGATE_POL 0x1830 +#define S5DC_GATE_SUS (1 << 15) +#define S5AC_GATE_SUS (1 << 14) + +#define DSX_CFG 0x1834 +#define REQ_CNV_NOWAKE_DSX (1 << 4) +#define REQ_BATLOW_DSX (1 << 3) +#define DSX_EN_WAKE_PIN (1 << 2) +#define DSX_DIS_AC_PRESENT_PD (1 << 1) +#define DSX_EN_LAN_WAKE_PIN (1 << 0) +#define DSX_CFG_MASK (0x1f << 0) + +#define PMSYNC_TPR_CFG 0x18C4 +#define PCH2CPU_TPR_CFG_LOCK (1 << 31) +#define PCH2CPU_TT_EN (1 << 26) + +#define PCH_PWRM_ACPI_TMR_CTL 0x18FC +#define GPIO_GPE_CFG 0x1920 +#define GPE0_DWX_MASK 0xf +#define GPE0_DW_SHIFT(x) (4*(x)) + +#define PMC_GPP_G 0x0 +#define PMC_GPP_B 0x1 +#define PMC_GPP_A 0x2 +#define PMC_GPP_R 0x3 +#define PMC_GPP_S 0x4 +#define PMC_GPD 0x5 +#define PMC_GPP_H 0x6 +#define PMC_GPP_D 0x7 +#define PMC_GPP_F 0x8 +#define PMC_GPP_C 0xA +#define PMC_GPP_E 0xB + +#define GBLRST_CAUSE0 0x1924 +#define GBLRST_CAUSE0_THERMTRIP (1 << 5) +#define GBLRST_CAUSE1 0x1928 + +#define CPPMVRIC 0x1B1C +#define XTALSDQDIS (1 << 22) + +#define IRQ_REG ACTL +#define SCI_IRQ_ADJUST 0 +#define ACTL 0x1BD8 +#define PWRM_EN (1 << 8) +#define ACPI_EN (1 << 7) +#define SCI_IRQ_SEL (7 << 0) + +#define SCIS_IRQ9 0 +#define SCIS_IRQ10 1 +#define SCIS_IRQ11 2 +#define SCIS_IRQ20 4 +#define SCIS_IRQ21 5 +#define SCIS_IRQ22 6 +#define SCIS_IRQ23 7 +#endif diff --git a/src/soc/intel/tigerlake/include/soc/ramstage.h b/src/soc/intel/tigerlake/include/soc/ramstage.h new file mode 100644 index 0000000000..606e2ffb8d --- /dev/null +++ b/src/soc/intel/tigerlake/include/soc/ramstage.h @@ -0,0 +1,27 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2018 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _SOC_RAMSTAGE_H_ +#define _SOC_RAMSTAGE_H_ + +#include +#include +#include +#include + +void mainboard_silicon_init_params(FSP_S_CONFIG *params); +void soc_init_pre_device(void *chip_info); + +#endif diff --git a/src/soc/intel/tigerlake/include/soc/serialio.h b/src/soc/intel/tigerlake/include/soc/serialio.h new file mode 100644 index 0000000000..cdf55157ff --- /dev/null +++ b/src/soc/intel/tigerlake/include/soc/serialio.h @@ -0,0 +1,48 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2018 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _SERIALIO_H_ +#define _SERIALIO_H_ + +enum { + PchSerialIoDisabled, + PchSerialIoPci, + PchSerialIoHidden, + PchSerialIoLegacyUart, + PchSerialIoSkipInit +}; + +enum { + PchSerialIoIndexI2C0, + PchSerialIoIndexI2C1, + PchSerialIoIndexI2C2, + PchSerialIoIndexI2C3, + PchSerialIoIndexI2C4, + PchSerialIoIndexI2C5 +}; + +enum { + PchSerialIoIndexGSPI0, + PchSerialIoIndexGSPI1, + PchSerialIoIndexGSPI2 +}; + +enum { + PchSerialIoIndexUART0, + PchSerialIoIndexUART1, + PchSerialIoIndexUART2 +}; + +#endif diff --git a/src/soc/intel/tigerlake/include/soc/smm.h b/src/soc/intel/tigerlake/include/soc/smm.h new file mode 100644 index 0000000000..43931679bf --- /dev/null +++ b/src/soc/intel/tigerlake/include/soc/smm.h @@ -0,0 +1,38 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2018 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _SOC_SMM_H_ +#define _SOC_SMM_H_ + +#include +#include +#include +#include + + +struct smm_relocation_params { + uintptr_t ied_base; + size_t ied_size; + msr_t smrr_base; + msr_t smrr_mask; + /* + * The smm_save_state_in_msrs field indicates if SMM save state + * locations live in MSRs. This indicates to the CPUs how to adjust + * the SMMBASE and IEDBASE + */ + int smm_save_state_in_msrs; +}; + +#endif diff --git a/src/soc/intel/tigerlake/include/soc/usb.h b/src/soc/intel/tigerlake/include/soc/usb.h new file mode 100644 index 0000000000..d2e50ef1e8 --- /dev/null +++ b/src/soc/intel/tigerlake/include/soc/usb.h @@ -0,0 +1,152 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2018 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + + +#ifndef _SOC_USB_H_ +#define _SOC_USB_H_ + +#include + +/* Per Port HS Transmitter Emphasis */ +#define USB2_EMP_OFF 0 +#define USB2_DE_EMP_ON 1 +#define USB2_PRE_EMP_ON 2 +#define USB2_DE_EMP_ON_PRE_EMP_ON 3 + +/* Per Port Half Bit Pre-emphasis */ +#define USB2_FULL_BIT_PRE_EMP 0 +#define USB2_HALF_BIT_PRE_EMP 1 + +/* Per Port HS Preemphasis Bias */ +#define USB2_BIAS_0MV 0 +#define USB2_BIAS_11P25MV 1 +#define USB2_BIAS_16P9MV 2 +#define USB2_BIAS_28P15MV 3 +#define USB2_BIAS_39P35MV 5 +#define USB2_BIAS_45MV 6 +#define USB2_BIAS_56P3MV 7 + +struct usb2_port_config { + uint8_t enable; + uint8_t ocpin; + uint8_t tx_bias; + uint8_t tx_emp_enable; + uint8_t pre_emp_bias; + uint8_t pre_emp_bit; +}; + +/* USB Overcurrent pins definition */ +enum { + OC0 = 0, + OC1, + OC2, + OC3, + OC4, + OC5, + OC6, + OC7, + OCMAX, + OC_SKIP = 0xff, /* Skip OC programming */ +}; + +/* Standard USB Port based on length: + * - External + * - Back Panel + * - OTG + * - M.2 + * - Internal device down */ + +#define USB2_PORT_EMPTY { \ + .enable = 0, \ + .ocpin = OC_SKIP, \ + .tx_bias = USB2_BIAS_0MV, \ + .tx_emp_enable = USB2_EMP_OFF, \ + .pre_emp_bias = USB2_BIAS_0MV, \ + .pre_emp_bit = USB2_HALF_BIT_PRE_EMP, \ +} + +/* Length = 11.5"-12" */ +#define USB2_PORT_LONG(pin) { \ + .enable = 1, \ + .ocpin = (pin), \ + .tx_bias = USB2_BIAS_39P35MV, \ + .tx_emp_enable = USB2_PRE_EMP_ON, \ + .pre_emp_bias = USB2_BIAS_56P3MV, \ + .pre_emp_bit = USB2_HALF_BIT_PRE_EMP, \ +} + +/* Length = 6"-11.49" */ +#define USB2_PORT_MID(pin) { \ + .enable = 1, \ + .ocpin = (pin), \ + .tx_bias = USB2_BIAS_0MV, \ + .tx_emp_enable = USB2_PRE_EMP_ON, \ + .pre_emp_bias = USB2_BIAS_56P3MV, \ + .pre_emp_bit = USB2_HALF_BIT_PRE_EMP, \ +} + +/* Length = 3"-5.99" */ +#define USB2_PORT_SHORT(pin) { \ + .enable = 1, \ + .ocpin = (pin), \ + .tx_bias = USB2_BIAS_39P35MV, \ + .tx_emp_enable = USB2_PRE_EMP_ON | USB2_DE_EMP_ON, \ + .pre_emp_bias = USB2_BIAS_39P35MV, \ + .pre_emp_bit = USB2_FULL_BIT_PRE_EMP, \ +} + +/* Max TX and Pre-emp settings */ +#define USB2_PORT_MAX(pin) { \ + .enable = 1, \ + .ocpin = (pin), \ + .tx_bias = USB2_BIAS_56P3MV, \ + .tx_emp_enable = USB2_PRE_EMP_ON, \ + .pre_emp_bias = USB2_BIAS_56P3MV, \ + .pre_emp_bit = USB2_HALF_BIT_PRE_EMP, \ +} + +/* Type-C Port, no BC1.2 charge detect module / MUX + * Length = 3.0" - 9.00" */ +#define USB2_PORT_TYPE_C(pin) { \ + .enable = 1, \ + .ocpin = (pin), \ + .tx_bias = USB2_BIAS_0MV, \ + .tx_emp_enable = USB2_PRE_EMP_ON, \ + .pre_emp_bias = USB2_BIAS_56P3MV, \ + .pre_emp_bit = USB2_HALF_BIT_PRE_EMP, \ +} + +struct usb3_port_config { + uint8_t enable; + uint8_t ocpin; + uint8_t tx_de_emp; + uint8_t tx_downscale_amp; +}; + +#define USB3_PORT_EMPTY { \ + .enable = 0, \ + .ocpin = OC_SKIP, \ + .tx_de_emp = 0x00, \ + .tx_downscale_amp = 0x00, \ +} + +#define USB3_PORT_DEFAULT(pin) { \ + .enable = 1, \ + .ocpin = (pin), \ + .tx_de_emp = 0x0, \ + .tx_downscale_amp = 0x00, \ +} + +#endif diff --git a/src/soc/intel/tigerlake/lockdown.c b/src/soc/intel/tigerlake/lockdown.c new file mode 100644 index 0000000000..08ae4ef455 --- /dev/null +++ b/src/soc/intel/tigerlake/lockdown.c @@ -0,0 +1,78 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* + * This file is created based on Intel Tiger Lake Processor PCH Datasheet + * Document number: 575857 + * Chapter number: 4 + */ + +#include +#include +#include +#include + +static void pmc_lock_pmsync(void) +{ + uint8_t *pmcbase; + uint32_t pmsyncreg; + + pmcbase = pmc_mmio_regs(); + + pmsyncreg = read32(pmcbase + PMSYNC_TPR_CFG); + pmsyncreg |= PCH2CPU_TPR_CFG_LOCK; + write32(pmcbase + PMSYNC_TPR_CFG, pmsyncreg); +} + +static void pmc_lock_abase(void) +{ + uint8_t *pmcbase; + uint32_t reg32; + + pmcbase = pmc_mmio_regs(); + + reg32 = read32(pmcbase + GEN_PMCON_B); + reg32 |= (SLP_STR_POL_LOCK | ACPI_BASE_LOCK); + write32(pmcbase + GEN_PMCON_B, reg32); +} + +static void pmc_lock_smi(void) +{ + uint8_t *pmcbase; + uint8_t reg8; + + pmcbase = pmc_mmio_regs(); + + reg8 = read8(pmcbase + GEN_PMCON_B); + reg8 |= SMI_LOCK; + write8(pmcbase + GEN_PMCON_B, reg8); +} + +static void pmc_lockdown_cfg(int chipset_lockdown) +{ + /* PMSYNC */ + pmc_lock_pmsync(); + /* Lock down ABASE and sleep stretching policy */ + pmc_lock_abase(); + + if (chipset_lockdown == CHIPSET_LOCKDOWN_COREBOOT) + pmc_lock_smi(); +} + +void soc_lockdown_config(int chipset_lockdown) +{ + /* PMC lock down configuration */ + pmc_lockdown_cfg(chipset_lockdown); +} diff --git a/src/soc/intel/tigerlake/p2sb.c b/src/soc/intel/tigerlake/p2sb.c new file mode 100644 index 0000000000..f5a3e70fce --- /dev/null +++ b/src/soc/intel/tigerlake/p2sb.c @@ -0,0 +1,49 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* + * This file is created based on Intel Tiger Lake Processor PCH Datasheet + * Document number: 575857 + * Chapter number: 3 + */ + +#include +#include + +void p2sb_soc_get_sb_mask(uint32_t *ep_mask, size_t count) +{ + uint32_t mask; + + if (count != P2SB_EP_MASK_MAX_REG) { + printk(BIOS_ERR, "Unable to program EPMASK registers\n"); + return; + } + + /* Remove the host accessing right to PSF register range. + * Set p2sb PCI offset EPMASK5 [29, 28, 27, 26] to disable Sideband + * access for PCI Root Bridge. + */ + mask = (1 << 29) | (1 << 28) | (1 << 27) | (1 << 26); + + ep_mask[P2SB_EP_MASK_5_REG] = mask; + + /* + * Set p2sb PCI offset EPMASK7 [31, 30] to disable Sideband + * access for Broadcast and Multicast. + */ + mask = (1 << 31) | (1 << 30); + + ep_mask[P2SB_EP_MASK_7_REG] = mask; +} diff --git a/src/soc/intel/tigerlake/pmc.c b/src/soc/intel/tigerlake/pmc.c new file mode 100644 index 0000000000..65284ec57c --- /dev/null +++ b/src/soc/intel/tigerlake/pmc.c @@ -0,0 +1,114 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* + * This file is created based on Intel Tiger Lake Processor PCH Datasheet + * Document number: 575857 + * Chapter number: 4 + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/* + * Set which power state system will be after reapplying + * the power (from G3 State) + */ +void pmc_soc_set_afterg3_en(const bool on) +{ + uint8_t reg8; + uint8_t *const pmcbase = pmc_mmio_regs(); + + reg8 = read8(pmcbase + GEN_PMCON_A); + if (on) + reg8 &= ~SLEEP_AFTER_POWER_FAIL; + else + reg8 |= SLEEP_AFTER_POWER_FAIL; + write8(pmcbase + GEN_PMCON_A, reg8); +} + +static void config_deep_sX(uint32_t offset, uint32_t mask, int sx, int enable) +{ + uint32_t reg; + uint8_t *pmcbase = pmc_mmio_regs(); + + printk(BIOS_DEBUG, "%sabling Deep S%c\n", + enable ? "En" : "Dis", sx + '0'); + reg = read32(pmcbase + offset); + if (enable) + reg |= mask; + else + reg &= ~mask; + write32(pmcbase + offset, reg); +} + +static void config_deep_s5(int on_ac, int on_dc) +{ + /* Treat S4 the same as S5. */ + config_deep_sX(S4_PWRGATE_POL, S4AC_GATE_SUS, 4, on_ac); + config_deep_sX(S4_PWRGATE_POL, S4DC_GATE_SUS, 4, on_dc); + config_deep_sX(S5_PWRGATE_POL, S5AC_GATE_SUS, 5, on_ac); + config_deep_sX(S5_PWRGATE_POL, S5DC_GATE_SUS, 5, on_dc); +} + +static void config_deep_s3(int on_ac, int on_dc) +{ + config_deep_sX(S3_PWRGATE_POL, S3AC_GATE_SUS, 3, on_ac); + config_deep_sX(S3_PWRGATE_POL, S3DC_GATE_SUS, 3, on_dc); +} + +static void config_deep_sx(uint32_t deepsx_config) +{ + uint32_t reg; + uint8_t *pmcbase = pmc_mmio_regs(); + + reg = read32(pmcbase + DSX_CFG); + reg &= ~DSX_CFG_MASK; + reg |= deepsx_config; + write32(pmcbase + DSX_CFG, reg); +} + +static void pmc_init(void *unused) +{ + const config_t *config = config_of_soc(); + + rtc_init(); + + pmc_set_power_failure_state(true); + pmc_gpe_init(); + + pmc_set_acpi_mode(); + + config_deep_s3(config->deep_s3_enable_ac, config->deep_s3_enable_dc); + config_deep_s5(config->deep_s5_enable_ac, config->deep_s5_enable_dc); + config_deep_sx(config->deep_sx_config); +} + +/* +* Initialize PMC controller. +* +* PMC controller gets hidden from PCI bus during FSP-Silicon init call. +* Hence PCI enumeration can't be used to initialize bus device and +* allocate resources. +*/ +BOOT_STATE_INIT_ENTRY(BS_DEV_INIT_CHIPS, BS_ON_EXIT, pmc_init, NULL); diff --git a/src/soc/intel/tigerlake/pmutil.c b/src/soc/intel/tigerlake/pmutil.c new file mode 100644 index 0000000000..53f86097ee --- /dev/null +++ b/src/soc/intel/tigerlake/pmutil.c @@ -0,0 +1,276 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* + * Helper functions for dealing with power management registers + * and the differences between PCH variants. + */ + +/* + * This file is created based on Intel Tiger Lake Processor PCH Datasheet + * Document number: 575857 + * Chapter number: 4 + */ + + +#define __SIMPLE_DEVICE__ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/* + * SMI + */ + +const char *const *soc_smi_sts_array(size_t *a) +{ + static const char *const smi_sts_bits[] = { + [BIOS_STS_BIT] = "BIOS", + [LEGACY_USB_STS_BIT] = "LEGACY_USB", + [SMI_ON_SLP_EN_STS_BIT] = "SLP_SMI", + [APM_STS_BIT] = "APM", + [SWSMI_TMR_STS_BIT] = "SWSMI_TMR", + [PM1_STS_BIT] = "PM1", + [GPE0_STS_BIT] = "GPE0", + [GPIO_STS_BIT] = "GPI", + [MCSMI_STS_BIT] = "MCSMI", + [DEVMON_STS_BIT] = "DEVMON", + [TCO_STS_BIT] = "TCO", + [PERIODIC_STS_BIT] = "PERIODIC", + [SERIRQ_SMI_STS_BIT] = "SERIRQ_SMI", + [SMBUS_SMI_STS_BIT] = "SMBUS_SMI", + [PCI_EXP_SMI_STS_BIT] = "PCI_EXP_SMI", + [MONITOR_STS_BIT] = "MONITOR", + [SPI_SMI_STS_BIT] = "SPI", + [GPIO_UNLOCK_SMI_STS_BIT] = "GPIO_UNLOCK", + [ESPI_SMI_STS_BIT] = "ESPI_SMI", + }; + + *a = ARRAY_SIZE(smi_sts_bits); + return smi_sts_bits; +} + +/* + * TCO + */ + +const char *const *soc_tco_sts_array(size_t *a) +{ + static const char *const tco_sts_bits[] = { + [0] = "NMI2SMI", + [1] = "SW_TCO", + [2] = "TCO_INT", + [3] = "TIMEOUT", + [7] = "NEWCENTURY", + [8] = "BIOSWR", + [9] = "DMISCI", + [10] = "DMISMI", + [12] = "DMISERR", + [13] = "SLVSEL", + [16] = "INTRD_DET", + [17] = "SECOND_TO", + [18] = "BOOT", + [20] = "SMLINK_SLV" + }; + + *a = ARRAY_SIZE(tco_sts_bits); + return tco_sts_bits; +} + +/* + * GPE0 + */ + +const char *const *soc_std_gpe_sts_array(size_t *a) +{ + static const char *const gpe_sts_bits[] = { + [1] = "HOTPLUG", + [2] = "SWGPE", + [6] = "TCO_SCI", + [7] = "SMB_WAK", + [9] = "PCI_EXP", + [10] = "BATLOW", + [11] = "PME", + [12] = "ME", + [13] = "PME_B0", + [14] = "eSPI", + [15] = "GPIO Tier-2", + [16] = "LAN_WAKE", + [18] = "WADT" + }; + + *a = ARRAY_SIZE(gpe_sts_bits); + return gpe_sts_bits; +} + +void pmc_set_disb(void) +{ + /* Set the DISB after DRAM init */ + uint8_t disb_val; + /* Only care about bits [23:16] of register GEN_PMCON_A */ + uint8_t *addr = (uint8_t *)(pmc_mmio_regs() + GEN_PMCON_A + 2); + + disb_val = read8(addr); + disb_val |= (DISB >> 16); + + /* Don't clear bits that are write-1-to-clear */ + disb_val &= ~((MS4V | SUS_PWR_FLR) >> 16); + write8(addr, disb_val); +} + +void pmc_clear_pmcon_sts(void) +{ + uint32_t reg_val; + uint8_t *addr; + addr = pmc_mmio_regs(); + + reg_val = read32(addr + GEN_PMCON_A); + /* Clear SUS_PWR_FLR, GBL_RST_STS, HOST_RST_STS, PWR_FLR bits + * while retaining MS4V write-1-to-clear bit */ + reg_val &= ~(MS4V); + + write32((addr + GEN_PMCON_A), reg_val); +} + +/* + * PMC controller gets hidden from PCI bus + * during FSP-Silicon init call. Hence PWRMBASE + * can't be accessible using PCI configuration space + * read/write. + */ +uint8_t *pmc_mmio_regs(void) +{ + return (void *)(uintptr_t)PCH_PWRM_BASE_ADDRESS; +} + +uintptr_t soc_read_pmc_base(void) +{ + return (uintptr_t)pmc_mmio_regs(); +} + +void soc_get_gpi_gpe_configs(uint8_t *dw0, uint8_t *dw1, uint8_t *dw2) +{ + DEVTREE_CONST struct soc_intel_tigerlake_config *config; + + config = config_of_soc(); + + /* Assign to out variable */ + *dw0 = config->gpe0_dw0; + *dw1 = config->gpe0_dw1; + *dw2 = config->gpe0_dw2; +} + +static int rtc_failed(uint32_t gen_pmcon_b) +{ + return !!(gen_pmcon_b & RTC_BATTERY_DEAD); +} + +int soc_get_rtc_failed(void) +{ + const struct chipset_power_state *ps = cbmem_find(CBMEM_ID_POWER_STATE); + + if (!ps) { + printk(BIOS_ERR, "Could not find power state in cbmem, RTC init aborted\n"); + return 1; + } + + return rtc_failed(ps->gen_pmcon_b); +} + +int vbnv_cmos_failed(void) +{ + return rtc_failed(read32(pmc_mmio_regs() + GEN_PMCON_B)); +} + +static inline int deep_s3_enabled(void) +{ + uint32_t deep_s3_pol; + + deep_s3_pol = read32(pmc_mmio_regs() + S3_PWRGATE_POL); + return !!(deep_s3_pol & (S3DC_GATE_SUS | S3AC_GATE_SUS)); +} + +/* Return 0, 3, or 5 to indicate the previous sleep state. */ +int soc_prev_sleep_state(const struct chipset_power_state *ps, + int prev_sleep_state) +{ + + /* + * Check for any power failure to determine if this a wake from + * S5 because the PCH does not set the WAK_STS bit when waking + * from a true G3 state. + */ + if (ps->gen_pmcon_a & (PWR_FLR | SUS_PWR_FLR)) + prev_sleep_state = ACPI_S5; + + /* + * If waking from S3 determine if deep S3 is enabled. If not, + * need to check both deep sleep well and normal suspend well. + * Otherwise just check deep sleep well. + */ + if (prev_sleep_state == ACPI_S3) { + /* PWR_FLR represents deep sleep power well loss. */ + uint32_t mask = PWR_FLR; + + /* If deep s3 isn't enabled check the suspend well too. */ + if (!deep_s3_enabled()) + mask |= SUS_PWR_FLR; + + if (ps->gen_pmcon_a & mask) + prev_sleep_state = ACPI_S5; + } + + return prev_sleep_state; +} + +void soc_fill_power_state(struct chipset_power_state *ps) +{ + uint8_t *pmc; + + ps->tco1_sts = tco_read_reg(TCO1_STS); + ps->tco2_sts = tco_read_reg(TCO2_STS); + + printk(BIOS_DEBUG, "TCO_STS: %04x %04x\n", + ps->tco1_sts, ps->tco2_sts); + + pmc = pmc_mmio_regs(); + ps->gen_pmcon_a = read32(pmc + GEN_PMCON_A); + ps->gen_pmcon_b = read32(pmc + GEN_PMCON_B); + ps->gblrst_cause[0] = read32(pmc + GBLRST_CAUSE0); + ps->gblrst_cause[1] = read32(pmc + GBLRST_CAUSE1); + + printk(BIOS_DEBUG, "GEN_PMCON: %08x %08x\n", + ps->gen_pmcon_a, ps->gen_pmcon_b); + + printk(BIOS_DEBUG, "GBLRST_CAUSE: %08x %08x\n", + ps->gblrst_cause[0], ps->gblrst_cause[1]); +} diff --git a/src/soc/intel/tigerlake/reset.c b/src/soc/intel/tigerlake/reset.c new file mode 100644 index 0000000000..674cf68dcc --- /dev/null +++ b/src/soc/intel/tigerlake/reset.c @@ -0,0 +1,47 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include +#include +#include +#include +#include + +void do_global_reset(void) +{ + /* Ask CSE to do the global reset */ + if (!send_heci_reset_req_message(GLOBAL_RESET)) + return; + + /* global reset if CSE fail to reset */ + pmc_global_reset_enable(1); + do_full_reset(); +} + +void chipset_handle_reset(uint32_t status) +{ + switch (status) { + case FSP_STATUS_RESET_REQUIRED_3: /* Global Reset */ + printk(BIOS_DEBUG, "GLOBAL RESET!!\n"); + global_reset(); + break; + default: + printk(BIOS_ERR, "unhandled reset type %x\n", status); + die("unknown reset type"); + break; + } +} diff --git a/src/soc/intel/tigerlake/sd.c b/src/soc/intel/tigerlake/sd.c new file mode 100644 index 0000000000..bc9dd9b26f --- /dev/null +++ b/src/soc/intel/tigerlake/sd.c @@ -0,0 +1,43 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* + * This file is created based on Intel Tiger Lake Processor PCH Datasheet + * Document number: 575857 + * Chapter number: 26 + */ + +#include +#include + +int sd_fill_soc_gpio_info(struct acpi_gpio *gpio, struct device *dev) +{ + config_t *config = config_of(dev); + + if (!config->sdcard_cd_gpio) + return -1; + + gpio->type = ACPI_GPIO_TYPE_INTERRUPT; + gpio->pull = ACPI_GPIO_PULL_NONE; + gpio->irq.mode = ACPI_IRQ_EDGE_TRIGGERED; + gpio->irq.polarity = ACPI_IRQ_ACTIVE_BOTH; + gpio->irq.shared = ACPI_IRQ_SHARED; + gpio->irq.wake = ACPI_IRQ_WAKE; + gpio->interrupt_debounce_timeout = 10000; /* 100ms */ + gpio->pin_count = 1; + gpio->pins[0] = config->sdcard_cd_gpio; + + return 0; +} diff --git a/src/soc/intel/tigerlake/smihandler.c b/src/soc/intel/tigerlake/smihandler.c new file mode 100644 index 0000000000..bf07beadb6 --- /dev/null +++ b/src/soc/intel/tigerlake/smihandler.c @@ -0,0 +1,126 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define CSME0_FBE 0xf +#define CSME0_BAR 0x0 +#define CSME0_FID 0xb0 + +const struct smm_save_state_ops *get_smm_save_state_ops(void) +{ + return &em64t101_smm_ops; +} + +static void pch_disable_heci(void) +{ + struct pcr_sbi_msg msg = { + .pid = PID_CSME0, + .offset = 0, + .opcode = PCR_WRITE, + .is_posted = false, + .fast_byte_enable = CSME0_FBE, + .bar = CSME0_BAR, + .fid = CSME0_FID + }; + /* Bit 0: Set to make HECI#1 Function disable */ + uint32_t data32 = 1; + uint8_t response; + int status; + + /* unhide p2sb device */ + p2sb_unhide(); + + /* Send SBI command to make HECI#1 function disable */ + status = pcr_execute_sideband_msg(&msg, &data32, &response); + if (status && response) + printk(BIOS_ERR, "Fail to make CSME function disable\n"); + + /* Ensure to Lock SBI interface after this command */ + p2sb_disable_sideband_access(); + + /* hide p2sb device */ + p2sb_hide(); +} + +/* + * Specific SOC SMI handler during ramstage finalize phase + * + * BIOS can't make CSME function disable as is due to POSTBOOT_SAI + * restriction in place from TGP chipset. Hence create SMI Handler to + * perform CSME function disabling logic during SMM mode. + */ +void smihandler_soc_at_finalize(void) +{ + const struct soc_intel_tigerlake_config *config; + + config = config_of_soc(); + + if (!config->HeciEnabled && CONFIG(HECI_DISABLE_USING_SMM)) + pch_disable_heci(); +} + +void smihandler_soc_check_illegal_access(uint32_t tco_sts) +{ + if (!((tco_sts & (1 << 8)) && CONFIG(SPI_FLASH_SMM) + && fast_spi_wpd_status())) + return; + + /* + * BWE is RW, so the SMI was caused by a + * write to BWE, not by a write to the BIOS + * + * This is the place where we notice someone + * is trying to tinker with the BIOS. We are + * trying to be nice and just ignore it. A more + * resolute answer would be to power down the + * box. + */ + printk(BIOS_DEBUG, "Switching back to RO\n"); + fast_spi_enable_wp(); +} + +/* SMI handlers that should be serviced in SCI mode too. */ +uint32_t smihandler_soc_get_sci_mask(void) +{ + uint32_t sci_mask = + SMI_HANDLER_SCI_EN(APM_STS_BIT) | + SMI_HANDLER_SCI_EN(SMI_ON_SLP_EN_STS_BIT); + + return sci_mask; +} + +const smi_handler_t southbridge_smi[SMI_STS_BITS] = { + [SMI_ON_SLP_EN_STS_BIT] = smihandler_southbridge_sleep, + [APM_STS_BIT] = smihandler_southbridge_apmc, + [PM1_STS_BIT] = smihandler_southbridge_pm1, + [GPE0_STS_BIT] = smihandler_southbridge_gpe0, + [GPIO_STS_BIT] = smihandler_southbridge_gpi, + [ESPI_SMI_STS_BIT] = smihandler_southbridge_espi, + [MCSMI_STS_BIT] = smihandler_southbridge_mc, + [TCO_STS_BIT] = smihandler_southbridge_tco, + [PERIODIC_STS_BIT] = smihandler_southbridge_periodic, + [MONITOR_STS_BIT] = smihandler_southbridge_monitor, +}; diff --git a/src/soc/intel/tigerlake/smmrelocate.c b/src/soc/intel/tigerlake/smmrelocate.c new file mode 100644 index 0000000000..b3f98362e5 --- /dev/null +++ b/src/soc/intel/tigerlake/smmrelocate.c @@ -0,0 +1,273 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/* This gets filled in and used during relocation. */ +static struct smm_relocation_params smm_reloc_params; + +static inline void write_smrr(struct smm_relocation_params *relo_params) +{ + printk(BIOS_DEBUG, "Writing SMRR. base = 0x%08x, mask=0x%08x\n", + relo_params->smrr_base.lo, relo_params->smrr_mask.lo); + wrmsr(IA32_SMRR_PHYS_BASE, relo_params->smrr_base); + wrmsr(IA32_SMRR_PHYS_MASK, relo_params->smrr_mask); +} + +static void update_save_state(int cpu, uintptr_t curr_smbase, + uintptr_t staggered_smbase, + struct smm_relocation_params *relo_params) +{ + u32 smbase; + u32 iedbase; + + /* + * The relocated handler runs with all CPUs concurrently. Therefore + * stagger the entry points adjusting SMBASE downwards by save state + * size * CPU num. + */ + smbase = staggered_smbase; + iedbase = relo_params->ied_base; + + printk(BIOS_DEBUG, "New SMBASE=0x%08x IEDBASE=0x%08x\n", + smbase, iedbase); + + /* + * All threads need to set IEDBASE and SMBASE to the relocated + * handler region. However, the save state location depends on the + * smm_save_state_in_msrs field in the relocation parameters. If + * smm_save_state_in_msrs is non-zero then the CPUs are relocating + * the SMM handler in parallel, and each CPUs save state area is + * located in their respective MSR space. If smm_save_state_in_msrs + * is zero then the SMM relocation is happening serially so the + * save state is at the same default location for all CPUs. + */ + if (relo_params->smm_save_state_in_msrs) { + msr_t smbase_msr; + msr_t iedbase_msr; + + smbase_msr.lo = smbase; + smbase_msr.hi = 0; + + /* + * According the BWG the IEDBASE MSR is in bits 63:32. It's + * not clear why it differs from the SMBASE MSR. + */ + iedbase_msr.lo = 0; + iedbase_msr.hi = iedbase; + + wrmsr(SMBASE_MSR, smbase_msr); + wrmsr(IEDBASE_MSR, iedbase_msr); + } else { + em64t101_smm_state_save_area_t *save_state; + + save_state = (void *)(curr_smbase + SMM_DEFAULT_SIZE - + sizeof(*save_state)); + + save_state->smbase = smbase; + save_state->iedbase = iedbase; + } +} + +/* Returns 1 if SMM MSR save state was set. */ +static int bsp_setup_msr_save_state(struct smm_relocation_params *relo_params) +{ + msr_t smm_mca_cap; + + smm_mca_cap = rdmsr(SMM_MCA_CAP_MSR); + if (smm_mca_cap.hi & SMM_CPU_SVRSTR_MASK) { + msr_t smm_feature_control; + + smm_feature_control = rdmsr(SMM_FEATURE_CONTROL_MSR); + smm_feature_control.hi = 0; + smm_feature_control.lo |= SMM_CPU_SAVE_EN; + wrmsr(SMM_FEATURE_CONTROL_MSR, smm_feature_control); + relo_params->smm_save_state_in_msrs = 1; + } + return relo_params->smm_save_state_in_msrs; +} + +/* + * The relocation work is actually performed in SMM context, but the code + * resides in the ramstage module. This occurs by trampolining from the default + * SMRAM entry point to here. + */ +void smm_relocation_handler(int cpu, uintptr_t curr_smbase, + uintptr_t staggered_smbase) +{ + msr_t mtrr_cap; + struct smm_relocation_params *relo_params = &smm_reloc_params; + + printk(BIOS_DEBUG, "In relocation handler: CPU %d\n", cpu); + + /* + * Determine if the processor supports saving state in MSRs. If so, + * enable it before the non-BSPs run so that SMM relocation can occur + * in parallel in the non-BSP CPUs. + */ + if (cpu == 0) { + /* + * If smm_save_state_in_msrs is 1 then that means this is the + * 2nd time through the relocation handler for the BSP. + * Parallel SMM handler relocation is taking place. However, + * it is desired to access other CPUs save state in the real + * SMM handler. Therefore, disable the SMM save state in MSRs + * feature. + */ + if (relo_params->smm_save_state_in_msrs) { + msr_t smm_feature_control; + + smm_feature_control = rdmsr(SMM_FEATURE_CONTROL_MSR); + smm_feature_control.lo &= ~SMM_CPU_SAVE_EN; + wrmsr(SMM_FEATURE_CONTROL_MSR, smm_feature_control); + } else if (bsp_setup_msr_save_state(relo_params)) + /* + * Just return from relocation handler if MSR save + * state is enabled. In that case the BSP will come + * back into the relocation handler to setup the new + * SMBASE as well disabling SMM save state in MSRs. + */ + return; + } + + /* Make appropriate changes to the save state map. */ + update_save_state(cpu, curr_smbase, staggered_smbase, relo_params); + + /* Write SMRR MSRs based on indicated support. */ + mtrr_cap = rdmsr(MTRR_CAP_MSR); + if (mtrr_cap.lo & SMRR_SUPPORTED) + write_smrr(relo_params); +} + +static void fill_in_relocation_params(struct smm_relocation_params *params) +{ + uintptr_t tseg_base; + size_t tseg_size; + /* All range registers are aligned to 4KiB */ + const u32 rmask = ~(4 * KiB - 1); + + smm_region(&tseg_base, &tseg_size); + + if (!IS_ALIGNED(tseg_base, tseg_size)) { + printk(BIOS_WARNING, + "TSEG base not aligned with TSEG SIZE! Not setting SMRR\n"); + return; + } + + smm_subregion(SMM_SUBREGION_CHIPSET, ¶ms->ied_base, ¶ms->ied_size); + + /* SMRR has 32-bits of valid address aligned to 4KiB. */ + params->smrr_base.lo = (tseg_base & rmask) | MTRR_TYPE_WRBACK; + params->smrr_base.hi = 0; + params->smrr_mask.lo = (~(tseg_size - 1) & rmask) | MTRR_PHYS_MASK_VALID; + params->smrr_mask.hi = 0; +} + +static void setup_ied_area(struct smm_relocation_params *params) +{ + char *ied_base; + + struct ied_header ied = { + .signature = "INTEL RSVD", + .size = params->ied_size, + .reserved = {0}, + }; + + ied_base = (void *)params->ied_base; + + printk(BIOS_DEBUG, "IED base = 0x%08x\n", (u32)params->ied_base); + printk(BIOS_DEBUG, "IED size = 0x%08x\n", (u32)params->ied_size); + + /* Place IED header at IEDBASE. */ + memcpy(ied_base, &ied, sizeof(ied)); + + /* Zero out 32KiB at IEDBASE + 1MiB */ + memset(ied_base + 1 * MiB, 0, 32 * KiB); +} + +void smm_info(uintptr_t *perm_smbase, size_t *perm_smsize, + size_t *smm_save_state_size) +{ + printk(BIOS_DEBUG, "Setting up SMI for CPU\n"); + + fill_in_relocation_params(&smm_reloc_params); + + smm_subregion(SMM_SUBREGION_HANDLER, perm_smbase, perm_smsize); + + if (smm_reloc_params.ied_size) + setup_ied_area(&smm_reloc_params); + + *smm_save_state_size = sizeof(em64t101_smm_state_save_area_t); +} + +void smm_initialize(void) +{ + /* Clear the SMM state in the southbridge. */ + smm_southbridge_clear_state(); + + /* + * Run the relocation handler for on the BSP to check and set up + * parallel SMM relocation. + */ + smm_initiate_relocation(); + + if (smm_reloc_params.smm_save_state_in_msrs) + printk(BIOS_DEBUG, "Doing parallel SMM relocation.\n"); +} + +void smm_relocate(void) +{ + /* + * If smm_save_state_in_msrs is non-zero then parallel SMM relocation + * shall take place. Run the relocation handler a second time on the + * BSP to do * the final move. For APs, a relocation handler always + * needs to be run. + */ + if (smm_reloc_params.smm_save_state_in_msrs) + smm_initiate_relocation_parallel(); + else if (!boot_cpu()) + smm_initiate_relocation(); +} + +void smm_lock(void) +{ + struct device *sa_dev = pcidev_path_on_root(SA_DEVFN_ROOT); + /* + * LOCK the SMM memory window and enable normal SMM. + * After running this function, only a full reset can + * make the SMM registers writable again. + */ + printk(BIOS_DEBUG, "Locking SMM.\n"); + pci_write_config8(sa_dev, SMRAM, D_LCK | G_SMRAME | C_BASE_SEG); +} diff --git a/src/soc/intel/tigerlake/spi.c b/src/soc/intel/tigerlake/spi.c new file mode 100644 index 0000000000..df4a593368 --- /dev/null +++ b/src/soc/intel/tigerlake/spi.c @@ -0,0 +1,39 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* + * This file is created based on Intel Tiger Lake Processor PCH Datasheet + * Document number: 575857 + * Chapter number: 7 + */ + +#include +#include + +int spi_soc_devfn_to_bus(unsigned int devfn) +{ + switch (devfn) { + case PCH_DEVFN_SPI: + return 0; + case PCH_DEVFN_GSPI0: + return 1; + case PCH_DEVFN_GSPI1: + return 2; + case PCH_DEVFN_GSPI2: + return 3; + } + return -1; +} diff --git a/src/soc/intel/tigerlake/systemagent.c b/src/soc/intel/tigerlake/systemagent.c new file mode 100644 index 0000000000..9c8f64573d --- /dev/null +++ b/src/soc/intel/tigerlake/systemagent.c @@ -0,0 +1,73 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* + * This file is created based on Intel Tiger Lake Processor SA Datasheet + * Document number: 571131 + * Chapter number: 3 + */ + +#include +#include +#include +#include +#include + +/* + * SoC implementation + * + * Add all known fixed memory ranges for Host Controller/Memory + * controller. + */ +void soc_add_fixed_mmio_resources(struct device *dev, int *index) +{ + static const struct sa_mmio_descriptor soc_fixed_resources[] = { + { PCIEXBAR, CONFIG_MMCONF_BASE_ADDRESS, CONFIG_SA_PCIEX_LENGTH, + "PCIEXBAR" }, + { MCHBAR, MCH_BASE_ADDRESS, MCH_BASE_SIZE, "MCHBAR" }, + { DMIBAR, DMI_BASE_ADDRESS, DMI_BASE_SIZE, "DMIBAR" }, + { EPBAR, EP_BASE_ADDRESS, EP_BASE_SIZE, "EPBAR" }, + { REGBAR, REG_BASE_ADDRESS, REG_BASE_SIZE, "REGBAR" }, + { EDRAMBAR, EDRAM_BASE_ADDRESS, EDRAM_BASE_SIZE, "EDRAMBAR" }, + /* + * PMC pci device gets hidden from PCI bus due to Silicon + * policy hence binding PMCBAR aka PWRMBASE (offset 0x10) with + * SA resources to ensure that PMCBAR falls under PCI reserved + * memory range. + * + * Note: Don't add any more resource with same offset 0x10 + * under this device space. + */ + { PCI_BASE_ADDRESS_0, PCH_PWRM_BASE_ADDRESS, PCH_PWRM_BASE_SIZE, + "PMCBAR" }, + }; + + sa_add_fixed_mmio_resources(dev, index, soc_fixed_resources, + ARRAY_SIZE(soc_fixed_resources)); +} + +/* + * SoC implementation + * + * Perform System Agent Initialization during Ramstage phase. + */ +void soc_systemagent_init(struct device *dev) +{ + /* Enable Power Aware Interrupt Routing */ + enable_power_aware_intr(); + + /* Enable BIOS Reset CPL */ + enable_bios_reset_cpl(); +} diff --git a/src/soc/intel/tigerlake/uart.c b/src/soc/intel/tigerlake/uart.c new file mode 100644 index 0000000000..b330e7791a --- /dev/null +++ b/src/soc/intel/tigerlake/uart.c @@ -0,0 +1,76 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 Intel Corporation + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* + * This file is created based on Intel Tiger Lake Processor PCH Datasheet + * Document number: 575857 + * Chapter number: 9 + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +const struct uart_gpio_pad_config uart_gpio_pads[] = { + { + .console_index = 0, + .gpios = { + PAD_CFG_NF(GPP_C8, NONE, DEEP, NF1), /* UART0 RX */ + PAD_CFG_NF(GPP_C9, NONE, DEEP, NF1), /* UART0 TX */ + }, + }, + { + .console_index = 1, + .gpios = { + PAD_CFG_NF(GPP_C12, NONE, DEEP, NF1), /* UART1 RX */ + PAD_CFG_NF(GPP_C13, NONE, DEEP, NF1), /* UART1 TX */ + }, + }, + { + .console_index = 2, + .gpios = { + PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1), /* UART2 RX */ + PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1), /* UART2 TX */ + }, + } +}; + +const int uart_max_index = ARRAY_SIZE(uart_gpio_pads); + +DEVTREE_CONST struct device *soc_uart_console_to_device(int uart_console) +{ + /* + * if index is valid, this function will return corresponding structure + * for uart console else will return NULL. + */ + switch (uart_console) { + case 0: + return pcidev_path_on_root(PCH_DEVFN_UART0); + case 1: + return pcidev_path_on_root(PCH_DEVFN_UART1); + case 2: + return pcidev_path_on_root(PCH_DEVFN_UART2); + default: + printk(BIOS_ERR, "Invalid UART console index\n"); + return NULL; + } +} From b8df689a6aaaa721103ed75d647decad2b4a9528 Mon Sep 17 00:00:00 2001 From: Subrata Banik Date: Fri, 1 Nov 2019 18:26:56 +0530 Subject: [PATCH 0066/1242] soc/intel/tigerlake/acpi: Copy acpi directory from icelake Clone entirely from Icelake List of changes on top off initial icelake clone 1. Removed Descriptor Name for Memory mapped SPI flash and local APIC in northbridge.asl 2. Rearranged code in gpio.asl to move RBUF object under _CRS and made the file use ASL2.0 syntax. 3. Make use of absolute path for scs.asl 4. Remove unused smbus.asl 5. Rearranged code in nothbridge.asl to move MCRS object under _CRS, use absolute variable path and added TODO for further clean up. 6. Refer absolute variable path in scs.asl Change-Id: If967cb5904f543ce21eb6e89421df0e5673d2238 Signed-off-by: Subrata Banik Reviewed-on: https://review.coreboot.org/c/coreboot/+/36553 Tested-by: build bot (Jenkins) Reviewed-by: Duncan Laurie --- src/soc/intel/tigerlake/acpi/gpio.asl | 133 +++++++ src/soc/intel/tigerlake/acpi/northbridge.asl | 342 +++++++++++++++++ src/soc/intel/tigerlake/acpi/pch_glan.asl | 29 ++ src/soc/intel/tigerlake/acpi/pch_hda.asl | 83 ++++ src/soc/intel/tigerlake/acpi/pci_irqs.asl | 138 +++++++ src/soc/intel/tigerlake/acpi/pcie.asl | 382 +++++++++++++++++++ src/soc/intel/tigerlake/acpi/platform.asl | 33 ++ src/soc/intel/tigerlake/acpi/scs.asl | 134 +++++++ src/soc/intel/tigerlake/acpi/serialio.asl | 88 +++++ src/soc/intel/tigerlake/acpi/southbridge.asl | 53 +++ src/soc/intel/tigerlake/acpi/xhci.asl | 71 ++++ 11 files changed, 1486 insertions(+) create mode 100644 src/soc/intel/tigerlake/acpi/gpio.asl create mode 100644 src/soc/intel/tigerlake/acpi/northbridge.asl create mode 100644 src/soc/intel/tigerlake/acpi/pch_glan.asl create mode 100644 src/soc/intel/tigerlake/acpi/pch_hda.asl create mode 100644 src/soc/intel/tigerlake/acpi/pci_irqs.asl create mode 100644 src/soc/intel/tigerlake/acpi/pcie.asl create mode 100644 src/soc/intel/tigerlake/acpi/platform.asl create mode 100644 src/soc/intel/tigerlake/acpi/scs.asl create mode 100644 src/soc/intel/tigerlake/acpi/serialio.asl create mode 100644 src/soc/intel/tigerlake/acpi/southbridge.asl create mode 100644 src/soc/intel/tigerlake/acpi/xhci.asl diff --git a/src/soc/intel/tigerlake/acpi/gpio.asl b/src/soc/intel/tigerlake/acpi/gpio.asl new file mode 100644 index 0000000000..98863e2486 --- /dev/null +++ b/src/soc/intel/tigerlake/acpi/gpio.asl @@ -0,0 +1,133 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ +#include +#include +#include + + +Device (GPIO) +{ + Name (_HID, "INT3455") + Name (_UID, 0) + Name (_DDN, "GPIO Controller") + + Method (_CRS, 0, NotSerialized) + { + Name (RBUF, ResourceTemplate() + { + Memory32Fixed (ReadWrite, 0, 0, COM0) + Memory32Fixed (ReadWrite, 0, 0, COM1) + Memory32Fixed (ReadWrite, 0, 0, COM2) + Memory32Fixed (ReadWrite, 0, 0, COM4) + Memory32Fixed (ReadWrite, 0, 0, COM5) + Interrupt (ResourceConsumer, Level, ActiveLow, Shared,,, GIRQ) + { GPIO_IRQ14 } + }) + + /* GPIO Community 0 */ + CreateDWordField (RBUF, COM0._BAS, BAS0) + CreateDWordField (RBUF, COM0._LEN, LEN0) + Store (PCRB (PID_GPIOCOM0), BAS0) + Store (GPIO_BASE_SIZE, LEN0) + + /* GPIO Community 1 */ + CreateDWordField (RBUF, COM1._BAS, BAS1) + CreateDWordField ( RBUF, COM1._LEN, LEN1) + Store (PCRB (PID_GPIOCOM1), BAS1) + Store (GPIO_BASE_SIZE, LEN1) + + /* GPIO Community 2 */ + CreateDWordField (RBUF, COM2._BAS, BAS2) + CreateDWordField (RBUF, COM2._LEN, LEN2) + Store (PCRB (PID_GPIOCOM2), BAS2) + Store (GPIO_BASE_SIZE, LEN2) + + /* GPIO Community 4 */ + CreateDWordField (RBUF, COM4._BAS, BAS4) + CreateDWordField (RBUF, COM4._LEN, LEN4) + Store (PCRB (PID_GPIOCOM4), BAS4) + Store (GPIO_BASE_SIZE, LEN4) + + /* GPIO Community 5 */ + CreateDWordField (RBUF, COM5._BAS, BAS5) + CreateDWordField (RBUF, COM5._LEN, LEN5) + Store (PCRB (PID_GPIOCOM5), BAS5) + Store (GPIO_BASE_SIZE, LEN5) + + Return (RBUF) + } + + Method (_STA, 0, NotSerialized) + { + Return (0xF) + } +} + +/* + * Get GPIO DW0 Address + * Arg0 - GPIO Number + */ +Method (GADD, 1, NotSerialized) +{ + /* GPIO Community 0 */ + If (Arg0 >= GPP_G0 && Arg0 <= GPP_A23) + { + Local0 = PID_GPIOCOM0 + Subtract (Arg0, GPP_A0, Local1) + } + /* GPIO Community 1 */ + If (Arg0 >= GPP_H0 && Arg0 <= GPP_F19) + { + Local0 = PID_GPIOCOM1 + Subtract (Arg0, GPP_D0, Local1) + } + /* GPIO Community 2 */ + If (Arg0 >= GPD0 && Arg0 <= GPD11) + { + Local0 = PID_GPIOCOM2 + Subtract (Arg0, GPD0, Local1) + } + /* GPIO Community 4 */ + If (Arg0 >= GPP_C0 && Arg0 <= GPP_E23) + { + Local0 = PID_GPIOCOM4 + Subtract (Arg0, GPP_C0, Local1) + } + /* GPIO Community 05*/ + If (Arg0 >= GPP_R0 && Arg0 <= GPP_S7) + { + Local0 = PID_GPIOCOM5 + Subtract (Arg0, GPP_R0, Local1) + } + Store (PCRB (Local0), Local2) + Add (Local2, PAD_CFG_BASE, Local2) + Return (Add (Local2, Multiply (Local1, 16))) +} + +/* + * Get GPIO Value + * Arg0 - GPIO Number + */ +Method (GRXS, 1, Serialized) +{ + OperationRegion (PREG, SystemMemory, GADD (Arg0), 4) + Field (PREG, AnyAcc, NoLock, Preserve) + { + VAL0, 32 + } + And (GPIORXSTATE_MASK, ShiftRight (VAL0, GPIORXSTATE_SHIFT), Local0) + + Return (Local0) +} diff --git a/src/soc/intel/tigerlake/acpi/northbridge.asl b/src/soc/intel/tigerlake/acpi/northbridge.asl new file mode 100644 index 0000000000..d6c2d346c6 --- /dev/null +++ b/src/soc/intel/tigerlake/acpi/northbridge.asl @@ -0,0 +1,342 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include + +#define BASE_32GB 0x800000000 +#define SIZE_16GB 0x400000000 + +Name (_HID, EisaId ("PNP0A08") /* PCI Express Bus */) // _HID: Hardware ID +Name (_CID, EisaId ("PNP0A03") /* PCI Bus */) // _CID: Compatible ID +Name (_SEG, Zero) // _SEG: PCI Segment +Name (_UID, Zero) // _UID: Unique ID + +Device (MCHC) +{ + Name (_ADR, 0x00000000) + + OperationRegion (MCHP, PCI_Config, 0x00, 0x100) + Field (MCHP, DWordAcc, NoLock, Preserve) + { + Offset(0x40), /* EPBAR (0:0:0:40) */ + EPEN, 1, /* Enable */ + , 11, + EPBR, 20, /* EPBAR [31:12] */ + + Offset(0x48), /* MCHBAR (0:0:0:48) */ + MHEN, 1, /* Enable */ + , 14, + MHBR, 17, /* MCHBAR [31:15] */ + + Offset(0x60), /* PCIEXBAR (0:0:0:60) */ + PXEN, 1, /* Enable */ + PXSZ, 2, /* PCI Express Size */ + , 23, + PXBR, 6, /* PCI Express BAR [31:26] */ + + Offset(0x68), /* DMIBAR (0:0:0:68) */ + DIEN, 1, /* Enable */ + , 11, + DIBR, 20, /* DMIBAR [31:12] */ + + Offset (0xa0), /* Top of Used Memory */ + TOM, 64, + + Offset (0xa8), /* Top of Upper Used Memory */ + TUUD, 64, + + Offset (0xbc), /* Top of Low Used Memory */ + TLUD, 32, + } +} + +Method (_CRS, 0, Serialized) +{ + Name (MCRS, ResourceTemplate () + { + /* Bus Numbers */ + WordBusNumber (ResourceProducer, MinFixed, MaxFixed, PosDecode, + 0x0000, 0x0000, 0x00ff, 0x0000, 0x0100) + + /* IO Region 0 */ + DWordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, + EntireRange, + 0x0000, 0x0000, 0x0cf7, 0x0000, 0x0cf8) + + /* PCI Config Space */ + Io (Decode16, 0x0cf8, 0x0cf8, 0x0001, 0x0008) + + /* IO Region 1 */ + DWordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, + EntireRange, + 0x0000, 0x0d00, 0xffff, 0x0000, 0xf300) + + /* VGA memory (0xa0000-0xbffff) */ + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, + Cacheable, ReadWrite, + 0x00000000, 0x000a0000, 0x000bffff, 0x00000000, + 0x00020000) + + /* OPROM reserved (0xc0000-0xc3fff) */ + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, + Cacheable, ReadWrite, + 0x00000000, 0x000c0000, 0x000c3fff, 0x00000000, + 0x00004000) + + /* OPROM reserved (0xc4000-0xc7fff) */ + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, + Cacheable, ReadWrite, + 0x00000000, 0x000c4000, 0x000c7fff, 0x00000000, + 0x00004000) + + /* OPROM reserved (0xc8000-0xcbfff) */ + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, + Cacheable, ReadWrite, + 0x00000000, 0x000c8000, 0x000cbfff, 0x00000000, + 0x00004000) + + /* OPROM reserved (0xcc000-0xcffff) */ + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, + Cacheable, ReadWrite, + 0x00000000, 0x000cc000, 0x000cffff, 0x00000000, + 0x00004000) + + /* OPROM reserved (0xd0000-0xd3fff) */ + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, + Cacheable, ReadWrite, + 0x00000000, 0x000d0000, 0x000d3fff, 0x00000000, + 0x00004000) + + /* OPROM reserved (0xd4000-0xd7fff) */ + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, + Cacheable, ReadWrite, + 0x00000000, 0x000d4000, 0x000d7fff, 0x00000000, + 0x00004000) + + /* OPROM reserved (0xd8000-0xdbfff) */ + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, + Cacheable, ReadWrite, + 0x00000000, 0x000d8000, 0x000dbfff, 0x00000000, + 0x00004000) + + /* OPROM reserved (0xdc000-0xdffff) */ + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, + Cacheable, ReadWrite, + 0x00000000, 0x000dc000, 0x000dffff, 0x00000000, + 0x00004000) + + /* BIOS Extension (0xe0000-0xe3fff) */ + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, + Cacheable, ReadWrite, + 0x00000000, 0x000e0000, 0x000e3fff, 0x00000000, + 0x00004000) + + /* BIOS Extension (0xe4000-0xe7fff) */ + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, + Cacheable, ReadWrite, + 0x00000000, 0x000e4000, 0x000e7fff, 0x00000000, + 0x00004000) + + /* BIOS Extension (0xe8000-0xebfff) */ + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, + Cacheable, ReadWrite, + 0x00000000, 0x000e8000, 0x000ebfff, 0x00000000, + 0x00004000) + + /* BIOS Extension (0xec000-0xeffff) */ + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, + Cacheable, ReadWrite, + 0x00000000, 0x000ec000, 0x000effff, 0x00000000, + 0x00004000) + + /* System BIOS (0xf0000-0xfffff) */ + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, + Cacheable, ReadWrite, + 0x00000000, 0x000f0000, 0x000fffff, 0x00000000, + 0x00010000) + + /* PCI Memory Region (TLUD - 0xdfffffff) */ + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, + NonCacheable, ReadWrite, + 0x00000000, 0x00000000, 0xdfffffff, 0x00000000, + 0xE0000000,,, PM01) + + /* PCI Memory Region (TUUD - (TUUD + ABOVE_4G_MMIO_SIZE)) */ + QWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, + NonCacheable, ReadWrite, + 0x00000000, 0x10000, 0x1ffff, 0x00000000, + 0x10000,,, PM02) + + /* PCH reserved resource (0xfc800000-0xfe7fffff) */ + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, + Cacheable, ReadWrite, + 0x00000000, PCH_PRESERVED_BASE_ADDRESS, 0xfe7fffff, + 0x00000000, PCH_PRESERVED_BASE_SIZE) + + /* TPM Area (0xfed40000-0xfed47fff) */ + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, + Cacheable, ReadWrite, + 0x00000000, 0xfed40000, 0xfed47fff, 0x00000000, + 0x00008000) + }) + + /* Find PCI resource area in MCRS */ + CreateDwordField (MCRS, PM01._MIN, PMIN) + CreateDwordField (MCRS, PM01._MAX, PMAX) + CreateDwordField (MCRS, PM01._LEN, PLEN) + + /* + * Fix up PCI memory region + * Start with Top of Lower Usable DRAM + */ + Store (\_SB.PCI0.MCHC.TLUD, PMIN) + Add (Subtract (PMAX, PMIN), 1, PLEN) + + /* Patch PM02 range based on Memory Size */ + CreateQwordField (MCRS, PM02._MIN, MMIN) + CreateQwordField (MCRS, PM02._MAX, MMAX) + CreateQwordField (MCRS, PM02._LEN, MLEN) + + Store (\_SB.PCI0.MCHC.TUUD, Local0) + + If (LLessEqual (Local0, BASE_32GB)) { + Store (BASE_32GB, MMIN) + Store (SIZE_16GB, MLEN) + } Else { + Store (0, MMIN) + Store (0, MLEN) + } + Subtract (Add (MMIN, MLEN), 1, MMAX) + + Return (MCRS) +} + +/* + * TODO: Clean up below functions and follow ASL2.0 code syntax + */ +Name (EP_B, 0) /* to store EP BAR */ +Name (MH_B, 0) /* to store MCH BAR */ +Name (PC_B, 0) /* to store PCIe BAR */ +Name (PC_L, 0) /* to store PCIe BAR Length */ +Name (DM_B, 0) /* to store DMI BAR */ + +/* Get MCH BAR */ +Method (GMHB, 0, Serialized) +{ + If (LEqual (MH_B, 0)) { + ShiftLeft (\_SB.PCI0.MCHC.MHBR, 15, MH_B) + } + Return (MH_B) +} + +/* Get EP BAR */ +Method (GEPB, 0, Serialized) +{ + If (LEqual (EP_B, 0)) { + ShiftLeft (\_SB.PCI0.MCHC.EPBR, 12, EP_B) + } + Return (EP_B) +} + +/* Get PCIe BAR */ +Method (GPCB, 0, Serialized) +{ + If (LEqual (PC_B, 0)) { + ShiftLeft (\_SB.PCI0.MCHC.PXBR, 26, PC_B) + } + Return (PC_B) +} + +/* Get PCIe Length */ +Method (GPCL, 0, Serialized) +{ + If (LEqual (PC_L, 0)) { + ShiftRight (0x10000000, \_SB.PCI0.MCHC.PXSZ, PC_L) + } + Return (PC_L) +} + +/* Get DMI BAR */ +Method (GDMB, 0, Serialized) +{ + If (LEqual (DM_B, 0)) { + ShiftLeft (\_SB.PCI0.MCHC.DIBR, 12, DM_B) + } + Return (DM_B) +} + +/* PCI Device Resource Consumption */ +Device (PDRC) +{ + Name (_HID, EISAID ("PNP0C02")) + Name (_UID, 1) + + Name (BUF0, ResourceTemplate () + { + /* MCH BAR _BAS will be updated in _CRS below according to + * B0:D0:F0:Reg.48h + */ + Memory32Fixed (ReadWrite, 0, 0x08000, MCHB) + + /* DMI BAR _BAS will be updated in _CRS below according to + * B0:D0:F0:Reg.68h + */ + Memory32Fixed (ReadWrite, 0, 0x01000, DMIB) + + /* EP BAR _BAS will be updated in _CRS below according to + * B0:D0:F0:Reg.40h + */ + Memory32Fixed (ReadWrite, 0, 0x01000, EGPB) + + /* PCI Express BAR _BAS and _LEN will be updated in + * _CRS below according to B0:D0:F0:Reg.60h + */ + Memory32Fixed (ReadWrite, 0, 0, PCIX) + + /* VTD engine memory range. + */ + Memory32Fixed (ReadOnly, VTD_BASE_ADDRESS, VTD_BASE_SIZE) + + /* Memory mapped SPI Flash range */ + Memory32Fixed (ReadOnly, 0xFFF00000, 0x1000000) + + /* Local APIC range(0xFEE0_0000 to 0xFEEF_FFFF) */ + Memory32Fixed (ReadOnly, 0xFEE00000, 0x100000) + + /* HPET address decode range */ + Memory32Fixed (ReadWrite, HPET_BASE_ADDRESS, 0x400) + }) + + Method (_CRS, 0, Serialized) + { + CreateDwordField (BUF0, ^MCHB._BAS, MBR0) + Store (\_SB.PCI0.GMHB (), MBR0) + + CreateDwordField (BUF0, ^DMIB._BAS, DBR0) + Store (\_SB.PCI0.GDMB (), DBR0) + + CreateDwordField (BUF0, ^EGPB._BAS, EBR0) + Store (\_SB.PCI0.GEPB (), EBR0) + + CreateDwordField (BUF0, ^PCIX._BAS, XBR0) + Store (\_SB.PCI0.GPCB (), XBR0) + + CreateDwordField (BUF0, ^PCIX._LEN, XSZ0) + Store (\_SB.PCI0.GPCL (), XSZ0) + + Return (BUF0) + } +} diff --git a/src/soc/intel/tigerlake/acpi/pch_glan.asl b/src/soc/intel/tigerlake/acpi/pch_glan.asl new file mode 100644 index 0000000000..260dd44962 --- /dev/null +++ b/src/soc/intel/tigerlake/acpi/pch_glan.asl @@ -0,0 +1,29 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * Copyright (C) 2014 Google Inc. + * Copyright (C) 2017-2108 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* Intel Gigabit Ethernet Controller 0:1f.6 */ + +Device (GLAN) +{ + Name (_ADR, 0x001f0006) + + Name (_S0W, 3) + + Name (_PRW, Package() {GPE0_PME_B0, 4}) + + Method (_DSW, 3) {} +} diff --git a/src/soc/intel/tigerlake/acpi/pch_hda.asl b/src/soc/intel/tigerlake/acpi/pch_hda.asl new file mode 100644 index 0000000000..708d0b56f1 --- /dev/null +++ b/src/soc/intel/tigerlake/acpi/pch_hda.asl @@ -0,0 +1,83 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* Audio Controller - Device 31, Function 3 */ + +Device (HDAS) +{ + Name (_ADR, 0x001f0003) + Name (_DDN, "Audio Controller") + Name (UUID, ToUUID ("A69F886E-6CEB-4594-A41F-7B5DCE24C553")) + + /* Device is D3 wake capable */ + Name (_S0W, 3) + + /* NHLT Table Address populated from GNVS values */ + Name (NBUF, ResourceTemplate () { + QWordMemory (ResourceConsumer, PosDecode, MinFixed, + MaxFixed, NonCacheable, ReadOnly, + 0, 0, 0, 0, 1,,, NHLT, AddressRangeACPI) + }) + + /* + * Device Specific Method + * Arg0 - UUID + * Arg1 - Revision + * Arg2 - Function Index + */ + Method (_DSM, 4) + { + If (LEqual (Arg0, ^UUID)) { + /* + * Function 0: Function Support Query + * Returns a bitmask of functions supported. + */ + If (LEqual (Arg2, Zero)) { + /* + * NHLT Query only supported for revision 1 and + * if NHLT address and length are set in NVS. + */ + If (LAnd (LEqual (Arg1, One), + LAnd (LNotEqual (NHLA, Zero), + LNotEqual (NHLL, Zero)))) { + Return (Buffer (One) { 0x03 }) + } Else { + Return (Buffer (One) { 0x01 }) + } + } + + /* + * Function 1: Query NHLT memory address used by + * Intel Offload Engine Driver to discover any non-HDA + * devices that are supported by the DSP. + * + * Returns a pointer to NHLT table in memory. + */ + If (LEqual (Arg2, One)) { + CreateQWordField (NBUF, ^NHLT._MIN, NBAS) + CreateQWordField (NBUF, ^NHLT._MAX, NMAS) + CreateQWordField (NBUF, ^NHLT._LEN, NLEN) + + Store (NHLA, NBAS) + Store (NHLA, NMAS) + Store (NHLL, NLEN) + + Return (NBUF) + } + } + + Return (Buffer (One) { 0x00 }) + } +} diff --git a/src/soc/intel/tigerlake/acpi/pci_irqs.asl b/src/soc/intel/tigerlake/acpi/pci_irqs.asl new file mode 100644 index 0000000000..19a3c12c01 --- /dev/null +++ b/src/soc/intel/tigerlake/acpi/pci_irqs.asl @@ -0,0 +1,138 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include + +Name (PICP, Package () { + /* PCI Bridge */ + /* cAVS, SMBus, GbE, Nothpeak */ + Package(){0x001FFFFF, 0, 0, cAVS_INTA_IRQ }, + Package(){0x001FFFFF, 1, 0, SMBUS_INTB_IRQ }, + Package(){0x001FFFFF, 2, 0, GbE_INTC_IRQ }, + Package(){0x001FFFFF, 3, 0, TRACE_HUB_INTD_IRQ }, + /* SerialIo and SCS */ + Package(){0x001EFFFF, 0, 0, LPSS_UART0_IRQ }, + Package(){0x001EFFFF, 1, 0, LPSS_UART1_IRQ }, + Package(){0x001EFFFF, 2, 0, LPSS_SPI0_IRQ }, + Package(){0x001EFFFF, 3, 0, LPSS_SPI1_IRQ }, + /* PCI Express Port 9-16 */ + Package(){0x001DFFFF, 0, 0, PCIE_9_IRQ }, + Package(){0x001DFFFF, 1, 0, PCIE_10_IRQ }, + Package(){0x001DFFFF, 2, 0, PCIE_11_IRQ }, + Package(){0x001DFFFF, 3, 0, PCIE_12_IRQ }, + /* PCI Express Port 1-8 */ + Package(){0x001CFFFF, 0, 0, PCIE_1_IRQ }, + Package(){0x001CFFFF, 1, 0, PCIE_2_IRQ }, + Package(){0x001CFFFF, 2, 0, PCIE_3_IRQ }, + Package(){0x001CFFFF, 3, 0, PCIE_4_IRQ }, + /* eMMC */ + Package(){0x001AFFFF, 0, 0, eMMC_IRQ }, + /* SerialIo */ + Package(){0x0019FFFF, 0, 0, LPSS_I2C4_IRQ }, + Package(){0x0019FFFF, 1, 0, LPSS_I2C5_IRQ }, + Package(){0x0019FFFF, 2, 0, LPSS_UART2_IRQ }, + /* SATA controller */ + Package(){0x0017FFFF, 0, 0, SATA_IRQ }, + /* CSME (HECI, IDE-R, Keyboard and Text redirection */ + Package(){0x0016FFFF, 0, 0, HECI_1_IRQ }, + Package(){0x0016FFFF, 1, 0, HECI_2_IRQ }, + Package(){0x0016FFFF, 2, 0, IDER_IRQ }, + Package(){0x0016FFFF, 3, 0, KT_IRQ }, + /* SerialIo */ + Package(){0x0015FFFF, 0, 0, LPSS_I2C0_IRQ }, + Package(){0x0015FFFF, 1, 0, LPSS_I2C1_IRQ }, + Package(){0x0015FFFF, 2, 0, LPSS_I2C2_IRQ }, + Package(){0x0015FFFF, 3, 0, LPSS_I2C3_IRQ }, + /* D20: xHCI, OTG, SRAM, CNVi WiFi */ + Package(){0x0014FFFF, 0, 0, XHCI_IRQ }, + Package(){0x0014FFFF, 1, 0, OTG_IRQ }, + Package(){0x0014FFFF, 2, 0, PMC_SRAM_IRQ }, + Package(){0x0014FFFF, 3, 0, CNViWIFI_IRQ }, + /* Integrated Sensor Hub */ + Package(){0x0013FFFF, 0, 0, ISH_IRQ }, + /* Thermal */ + Package(){0x0012FFFF, 0, 0, THERMAL_IRQ }, + /* Host Bridge */ + /* Root Port D1F0 */ + Package(){0x0001FFFF, 0, 0, PEG_RP_INTA_IRQ }, + Package(){0x0001FFFF, 1, 0, PEG_RP_INTB_IRQ }, + Package(){0x0001FFFF, 2, 0, PEG_RP_INTC_IRQ }, + Package(){0x0001FFFF, 3, 0, PEG_RP_INTD_IRQ }, + /* SA IGFX Device */ + Package(){0x0002FFFF, 0, 0, IGFX_IRQ }, + /* SA Thermal Device */ + Package(){0x0004FFFF, 0, 0, SA_THERMAL_IRQ }, + /* SA IPU Device */ + Package(){0x0005FFFF, 0, 0, IPU_IRQ }, + /* SA GNA Device */ + Package(){0x0008FFFF, 0, 0, GNA_IRQ }, +}) + +Name (PICN, Package () { + /* D31: cAVS, SMBus, GbE, Nothpeak */ + Package () { 0x001FFFFF, 0, 0, 11 }, + Package () { 0x001FFFFF, 1, 0, 10 }, + Package () { 0x001FFFFF, 2, 0, 11 }, + Package () { 0x001FFFFF, 3, 0, 11 }, + /* D30: Can't use PIC*/ + /* D29: PCI Express Port 9-16 */ + Package () { 0x001DFFFF, 0, 0, 11 }, + Package () { 0x001DFFFF, 1, 0, 10 }, + Package () { 0x001DFFFF, 2, 0, 11 }, + Package () { 0x001DFFFF, 3, 0, 11 }, + /* D28: PCI Express Port 1-8 */ + Package () { 0x001CFFFF, 0, 0, 11 }, + Package () { 0x001CFFFF, 1, 0, 10 }, + Package () { 0x001CFFFF, 2, 0, 11 }, + Package () { 0x001CFFFF, 3, 0, 11 }, + /* D26: Can't use PIC*/ + /* D25: Can't use PIC*/ + /* D23: SATA controller */ + Package () { 0x0017FFFF, 0, 0, 11 }, + /* D22: CSME (HECI, IDE-R, KT redirection */ + Package () { 0x0016FFFF, 0, 0, 11 }, + Package () { 0x0016FFFF, 1, 0, 10 }, + Package () { 0x0016FFFF, 2, 0, 11 }, + Package () { 0x0016FFFF, 3, 0, 11 }, + /* D20: xHCI, OTG, SRAM, CNVi WiFi */ + Package () { 0x0014FFFF, 0, 0, 11 }, + Package () { 0x0014FFFF, 1, 0, 10 }, + Package () { 0x0014FFFF, 2, 0, 11 }, + Package () { 0x0014FFFF, 3, 0, 11 }, + /* D18: Can't use PIC*/ + /* P.E.G. Root Port D1F0 */ + Package () { 0x0001FFFF, 0, 0, 11 }, + Package () { 0x0001FFFF, 1, 0, 10 }, + Package () { 0x0001FFFF, 2, 0, 11 }, + Package () { 0x0001FFFF, 3, 0, 11 }, + /* SA IGFX Device */ + Package () { 0x0002FFFF, 0, 0, 11 }, + /* SA Thermal Device */ + Package () { 0x0004FFFF, 0, 0, 11 }, + /* SA IPU Device */ + Package () { 0x0005FFFF, 0, 0, 11 }, + /* SA GNA Device */ + Package () { 0x0008FFFF, 0, 0, 11 }, +}) + +Method (_PRT) +{ + If (PICM) { + Return (^PICP) + } Else { + Return (^PICN) + } +} diff --git a/src/soc/intel/tigerlake/acpi/pcie.asl b/src/soc/intel/tigerlake/acpi/pcie.asl new file mode 100644 index 0000000000..0191454a5d --- /dev/null +++ b/src/soc/intel/tigerlake/acpi/pcie.asl @@ -0,0 +1,382 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* Intel PCH PCIe support */ + +Method (IRQM, 1, Serialized) { + + /* Interrupt Map INTA->INTA, INTB->INTB, INTC->INTC, INTD->INTD */ + Name (IQAA, Package () { + Package () { 0x0000ffff, 0, 0, 16 }, + Package () { 0x0000ffff, 1, 0, 17 }, + Package () { 0x0000ffff, 2, 0, 18 }, + Package () { 0x0000ffff, 3, 0, 19 } }) + Name (IQAP, Package () { + Package () { 0x0000ffff, 0, 0, 11 }, + Package () { 0x0000ffff, 1, 0, 10 }, + Package () { 0x0000ffff, 2, 0, 11 }, + Package () { 0x0000ffff, 3, 0, 11 } }) + + /* Interrupt Map INTA->INTB, INTB->INTC, INTC->INTD, INTD->INTA */ + Name (IQBA, Package () { + Package () { 0x0000ffff, 0, 0, 17 }, + Package () { 0x0000ffff, 1, 0, 18 }, + Package () { 0x0000ffff, 2, 0, 19 }, + Package () { 0x0000ffff, 3, 0, 16 } }) + Name (IQBP, Package () { + Package () { 0x0000ffff, 0, 0, 10 }, + Package () { 0x0000ffff, 1, 0, 11 }, + Package () { 0x0000ffff, 2, 0, 11 }, + Package () { 0x0000ffff, 3, 0, 11 } }) + + /* Interrupt Map INTA->INTC, INTB->INTD, INTC->INTA, INTD->INTB */ + Name (IQCA, Package () { + Package () { 0x0000ffff, 0, 0, 18 }, + Package () { 0x0000ffff, 1, 0, 19 }, + Package () { 0x0000ffff, 2, 0, 16 }, + Package () { 0x0000ffff, 3, 0, 17 } }) + Name (IQCP, Package () { + Package () { 0x0000ffff, 0, 0, 11 }, + Package () { 0x0000ffff, 1, 0, 11 }, + Package () { 0x0000ffff, 2, 0, 11 }, + Package () { 0x0000ffff, 3, 0, 10 } }) + + /* Interrupt Map INTA->INTD, INTB->INTA, INTC->INTB, INTD->INTC */ + Name (IQDA, Package () { + Package () { 0x0000ffff, 0, 0, 19 }, + Package () { 0x0000ffff, 1, 0, 16 }, + Package () { 0x0000ffff, 2, 0, 17 }, + Package () { 0x0000ffff, 3, 0, 18 } }) + Name (IQDP, Package () { + Package () { 0x0000ffff, 0, 0, 11 }, + Package () { 0x0000ffff, 1, 0, 11 }, + Package () { 0x0000ffff, 2, 0, 10 }, + Package () { 0x0000ffff, 3, 0, 11 } }) + + Switch (ToInteger (Arg0)) + { + Case (Package () { 1, 5, 9, 13 }) { + If (PICM) { + Return (IQAA) + } Else { + Return (IQAP) + } + } + + Case (Package () { 2, 6, 10, 14 }) { + If (PICM) { + Return (IQBA) + } Else { + Return (IQBP) + } + } + + Case (Package () { 3, 7, 11, 15 }) { + If (PICM) { + Return (IQCA) + } Else { + Return (IQCP) + } + } + + Case (Package () { 4, 8, 12, 16 }) { + If (PICM) { + Return (IQDA) + } Else { + Return (IQDP) + } + } + + Default { + If (PICM) { + Return (IQDA) + } Else { + Return (IQDP) + } + } + } +} + +Device (RP01) +{ + Name (_ADR, 0x001C0000) + + OperationRegion (RPCS, PCI_Config, 0x4c, 4) + Field (RPCS, AnyAcc, NoLock, Preserve) + { + , 24, + RPPN, 8, /* Root Port Number */ + } + + Method (_PRT) + { + Return (IRQM (RPPN)) + } +} + +Device (RP02) +{ + Name (_ADR, 0x001C0001) + + OperationRegion (RPCS, PCI_Config, 0x4c, 4) + Field (RPCS, AnyAcc, NoLock, Preserve) + { + , 24, + RPPN, 8, /* Root Port Number */ + } + + Method (_PRT) + { + Return (IRQM (RPPN)) + } +} + +Device (RP03) +{ + Name (_ADR, 0x001C0002) + + OperationRegion (RPCS, PCI_Config, 0x4c, 4) + Field (RPCS, AnyAcc, NoLock, Preserve) + { + , 24, + RPPN, 8, /* Root Port Number */ + } + + Method (_PRT) + { + Return (IRQM (RPPN)) + } +} + +Device (RP04) +{ + Name (_ADR, 0x001C0003) + + OperationRegion (RPCS, PCI_Config, 0x4c, 4) + Field (RPCS, AnyAcc, NoLock, Preserve) + { + , 24, + RPPN, 8, /* Root Port Number */ + } + + Method (_PRT) + { + Return (IRQM (RPPN)) + } +} + +Device (RP05) +{ + Name (_ADR, 0x001C0004) + + OperationRegion (RPCS, PCI_Config, 0x4c, 4) + Field (RPCS, AnyAcc, NoLock, Preserve) + { + , 24, + RPPN, 8, /* Root Port Number */ + } + + Method (_PRT) + { + Return (IRQM (RPPN)) + } +} + +Device (RP06) +{ + Name (_ADR, 0x001C0005) + + OperationRegion (RPCS, PCI_Config, 0x4c, 4) + Field (RPCS, AnyAcc, NoLock, Preserve) + { + , 24, + RPPN, 8, /* Root Port Number */ + } + + Method (_PRT) + { + Return (IRQM (RPPN)) + } +} + +Device (RP07) +{ + Name (_ADR, 0x001C0006) + + OperationRegion (RPCS, PCI_Config, 0x4c, 4) + Field (RPCS, AnyAcc, NoLock, Preserve) + { + , 24, + RPPN, 8, /* Root Port Number */ + } + + Method (_PRT) + { + Return (IRQM (RPPN)) + } +} + +Device (RP08) +{ + Name (_ADR, 0x001C0007) + + OperationRegion (RPCS, PCI_Config, 0x4c, 4) + Field (RPCS, AnyAcc, NoLock, Preserve) + { + , 24, + RPPN, 8, /* Root Port Number */ + } + + Method (_PRT) + { + Return (IRQM (RPPN)) + } +} + +Device (RP09) +{ + Name (_ADR, 0x001D0000) + + OperationRegion (RPCS, PCI_Config, 0x4c, 4) + Field (RPCS, AnyAcc, NoLock, Preserve) + { + , 24, + RPPN, 8, /* Root Port Number */ + } + + Method (_PRT) + { + Return (IRQM (RPPN)) + } +} + +Device (RP10) +{ + Name (_ADR, 0x001D0001) + + OperationRegion (RPCS, PCI_Config, 0x4c, 4) + Field (RPCS, AnyAcc, NoLock, Preserve) + { + , 24, + RPPN, 8, /* Root Port Number */ + } + + Method (_PRT) + { + Return (IRQM (RPPN)) + } +} + +Device (RP11) +{ + Name (_ADR, 0x001D0002) + + OperationRegion (RPCS, PCI_Config, 0x4c, 4) + Field (RPCS, AnyAcc, NoLock, Preserve) + { + , 24, + RPPN, 8, /* Root Port Number */ + } + + Method (_PRT) + { + Return (IRQM (RPPN)) + } +} + +Device (RP12) +{ + Name (_ADR, 0x001D0003) + + OperationRegion (RPCS, PCI_Config, 0x4c, 4) + Field (RPCS, AnyAcc, NoLock, Preserve) + { + , 24, + RPPN, 8, /* Root Port Number */ + } + + Method (_PRT) + { + Return (IRQM (RPPN)) + } +} + +Device (RP13) +{ + Name (_ADR, 0x001D0004) + + OperationRegion (RPCS, PCI_Config, 0x4c, 4) + Field (RPCS, AnyAcc, NoLock, Preserve) + { + , 24, + RPPN, 8, /* Root Port Number */ + } + + Method (_PRT) + { + Return (IRQM (RPPN)) + } +} + +Device (RP14) +{ + Name (_ADR, 0x001D0005) + + OperationRegion (RPCS, PCI_Config, 0x4c, 4) + Field (RPCS, AnyAcc, NoLock, Preserve) + { + , 24, + RPPN, 8, /* Root Port Number */ + } + + Method (_PRT) + { + Return (IRQM (RPPN)) + } +} + +Device (RP15) +{ + Name (_ADR, 0x001D0006) + + OperationRegion (RPCS, PCI_Config, 0x4c, 4) + Field (RPCS, AnyAcc, NoLock, Preserve) + { + , 24, + RPPN, 8, /* Root Port Number */ + } + + Method (_PRT) + { + Return (IRQM (RPPN)) + } +} + +Device (RP16) +{ + Name (_ADR, 0x001D0007) + + OperationRegion (RPCS, PCI_Config, 0x4c, 4) + Field (RPCS, AnyAcc, NoLock, Preserve) + { + , 24, + RPPN, 8, /* Root Port Number */ + } + + Method (_PRT) + { + Return (IRQM (RPPN)) + } +} diff --git a/src/soc/intel/tigerlake/acpi/platform.asl b/src/soc/intel/tigerlake/acpi/platform.asl new file mode 100644 index 0000000000..dde9b13186 --- /dev/null +++ b/src/soc/intel/tigerlake/acpi/platform.asl @@ -0,0 +1,33 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* Enable ACPI _SWS methods */ +#include +/* Generic indicator for sleep state */ +#include + +/* + * The _PIC method is called by the OS to choose between interrupt + * routing via the i8259 interrupt controller or the APIC. + * + * _PIC is called with a parameter of 0 for i8259 configuration and + * with a parameter of 1 for Local Apic/IOAPIC configuration. + */ + +Method (_PIC, 1) +{ + /* Remember the OS' IRQ routing choice. */ + Store (Arg0, PICM) +} diff --git a/src/soc/intel/tigerlake/acpi/scs.asl b/src/soc/intel/tigerlake/acpi/scs.asl new file mode 100644 index 0000000000..a9ff93c2ca --- /dev/null +++ b/src/soc/intel/tigerlake/acpi/scs.asl @@ -0,0 +1,134 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include + +Scope (\_SB.PCI0) { + + /* + * Clear register 0x1C20/0x4820 + * Arg0 - PCR Port ID + */ + Method(SCSC, 1, Serialized) + { + PCRA (Arg0, 0x1C20, 0x0) + PCRA (Arg0, 0x4820, 0x0) + } + + /* EMMC */ + Device(PEMC) { + Name(_ADR, 0x001A0000) + Name (_DDN, "eMMC Controller") + Name (TEMP, 0) + + OperationRegion(SCSR, PCI_Config, 0x00, 0x100) + Field(SCSR, WordAcc, NoLock, Preserve) { + Offset (0x84), /* PMECTRLSTATUS */ + PMCR, 16, + Offset (0xA2), /* PG_CONFIG */ + , 2, + PGEN, 1, /* PG_ENABLE */ + } + + Method(_INI) { + /* Clear register 0x1C20/0x4820 */ + SCSC (PID_EMMC) + } + + Method(_PS0, 0, Serialized) { + Stall (50) // Sleep 50 us + + Store(0, PGEN) // Disable PG + + /* Clear register 0x1C20/0x4820 */ + SCSC (PID_EMMC) + + /* Set Power State to D0 */ + And (PMCR, 0xFFFC, PMCR) + Store (PMCR, TEMP) + } + + Method(_PS3, 0, Serialized) { + Store(1, PGEN) // Enable PG + + /* Set Power State to D3 */ + Or (PMCR, 0x0003, PMCR) + Store (PMCR, TEMP) + } + + Device (CARD) + { + Name (_ADR, 0x00000008) + Method (_RMV, 0, NotSerialized) + { + Return (0) + } + } + } + + /* SD CARD */ + Device (SDXC) + { + Name (_ADR, 0x00140005) + Name (_DDN, "SD Controller") + Name (TEMP, 0) + + OperationRegion (SDPC, PCI_Config, 0x00, 0x100) + Field (SDPC, WordAcc, NoLock, Preserve) + { + Offset (0x84), /* PMECTRLSTATUS */ + PMCR, 16, + Offset (0xA2), /* PG_CONFIG */ + , 2, + PGEN, 1, /* PG_ENABLE */ + } + + Method(_INI) + { + /* Clear register 0x1C20/0x4820 */ + SCSC (PID_SDX) + } + + Method (_PS0, 0, Serialized) + { + Store (0, PGEN) /* Disable PG */ + + /* Clear register 0x1C20/0x4820 */ + SCSC (PID_SDX) + + /* Set Power State to D0 */ + And (PMCR, 0xFFFC, PMCR) + Store (PMCR, TEMP) + } + + Method (_PS3, 0, Serialized) + { + Store (1, PGEN) /* Enable PG */ + + /* Set Power State to D3 */ + Or (PMCR, 0x0003, PMCR) + Store (PMCR, TEMP) + } + + Device (CARD) + { + Name (_ADR, 0x00000008) + Method (_RMV, 0, NotSerialized) + { + Return (1) + } + } + } /* Device (SDXC) */ +} diff --git a/src/soc/intel/tigerlake/acpi/serialio.asl b/src/soc/intel/tigerlake/acpi/serialio.asl new file mode 100644 index 0000000000..0b0e3da678 --- /dev/null +++ b/src/soc/intel/tigerlake/acpi/serialio.asl @@ -0,0 +1,88 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* Intel Serial IO Devices */ + +Device (I2C0) +{ + Name (_ADR, 0x00150000) + Name (_DDN, "Serial IO I2C Controller 0") +} + +Device (I2C1) +{ + Name (_ADR, 0x00150001) + Name (_DDN, "Serial IO I2C Controller 1") +} + +Device (I2C2) +{ + Name (_ADR, 0x00150002) + Name (_DDN, "Serial IO I2C Controller 2") +} + +Device (I2C3) +{ + Name (_ADR, 0x00150003) + Name (_DDN, "Serial IO I2C Controller 3") +} + +Device (I2C4) +{ + Name (_ADR, 0x00190000) + Name (_DDN, "Serial IO I2C Controller 4") +} + +Device (I2C5) +{ + Name (_ADR, 0x00190001) + Name (_DDN, "Serial IO I2C Controller 5") +} + +Device (SPI0) +{ + Name (_ADR, 0x001e0002) + Name (_DDN, "Serial IO SPI Controller 0") +} + +Device (SPI1) +{ + Name (_ADR, 0x001e0003) + Name (_DDN, "Serial IO SPI Controller 1") +} + +Device (SPI2) +{ + Name (_ADR, 0x00120006) + Name (_DDN, "Serial IO SPI Controller 2") +} + +Device (UAR0) +{ + Name (_ADR, 0x001e0000) + Name (_DDN, "Serial IO UART Controller 0") +} + +Device (UAR1) +{ + Name (_ADR, 0x001e0001) + Name (_DDN, "Serial IO UART Controller 1") +} + +Device (UAR2) +{ + Name (_ADR, 0x00190002) + Name (_DDN, "Serial IO UART Controller 2") +} diff --git a/src/soc/intel/tigerlake/acpi/southbridge.asl b/src/soc/intel/tigerlake/acpi/southbridge.asl new file mode 100644 index 0000000000..7de8ac42d3 --- /dev/null +++ b/src/soc/intel/tigerlake/acpi/southbridge.asl @@ -0,0 +1,53 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include +#include + +/* PCI IRQ assignment */ +#include "pci_irqs.asl" + +/* PCR access */ +#include + +/* eMMC, SD Card */ +#include "scs.asl" + +/* GPIO controller */ +#include "gpio.asl" + +/* ESPI 0:1f.0 */ +#include + +/* PCH HDA */ +#include "pch_hda.asl" + +/* PCIE Ports */ +#include "pcie.asl" + +/* Serial IO */ +#include "serialio.asl" + +/* USB XHCI 0:14.0 */ +#include "xhci.asl" + +/* PCI _OSC */ +#include + +/* GBe 0:1f.6 */ +#include "pch_glan.asl" diff --git a/src/soc/intel/tigerlake/acpi/xhci.asl b/src/soc/intel/tigerlake/acpi/xhci.asl new file mode 100644 index 0000000000..8268bd516f --- /dev/null +++ b/src/soc/intel/tigerlake/acpi/xhci.asl @@ -0,0 +1,71 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include + +/* XHCI Controller 0:14.0 */ + +Device (XHCI) +{ + Name (_ADR, 0x00140000) + + Name (_PRW, Package () { GPE0_PME_B0, 3 }) + + Name (_S3D, 3) /* D3 supported in S3 */ + Name (_S0W, 3) /* D3 can wake device in S0 */ + Name (_S3W, 3) /* D3 can wake system from S3 */ + + Method (_PS0, 0, Serialized) + { + + } + + Method (_PS3, 0, Serialized) + { + + } + + /* Root Hub for Tigerlake-LP PCH */ + Device (RHUB) + { + Name (_ADR, Zero) + + /* USB2 */ + Device (HS01) { Name (_ADR, 1) } + Device (HS02) { Name (_ADR, 2) } + Device (HS03) { Name (_ADR, 3) } + Device (HS04) { Name (_ADR, 4) } + Device (HS05) { Name (_ADR, 5) } + Device (HS06) { Name (_ADR, 6) } + Device (HS07) { Name (_ADR, 7) } + Device (HS08) { Name (_ADR, 8) } + Device (HS09) { Name (_ADR, 9) } + Device (HS10) { Name (_ADR, 10) } + Device (HS11) { Name (_ADR, 11) } + Device (HS12) { Name (_ADR, 12) } + + /* USBr */ + Device (USR1) { Name (_ADR, 11) } + Device (USR2) { Name (_ADR, 12) } + + /* USB3 */ + Device (SS01) { Name (_ADR, 13) } + Device (SS02) { Name (_ADR, 14) } + Device (SS03) { Name (_ADR, 15) } + Device (SS04) { Name (_ADR, 16) } + Device (SS05) { Name (_ADR, 17) } + Device (SS06) { Name (_ADR, 18) } + } +} From 7e4bfe4b91cc8dbc18a4b940c26f372e471d49db Mon Sep 17 00:00:00 2001 From: Arthur Heymans Date: Tue, 5 Feb 2019 13:30:11 +0100 Subject: [PATCH 0067/1242] mb/asus/p5ql-em: Add mainboard MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Tested, working: - First dimm slot of each channel - USB, SATA - CPU FSB at 800, 1067 and 1333MHz - Libgfxinit on DVI and VGA slot - PCI slot - Realtek NIC (configure MAC address in Kconfig) - PEG slot - PS2 keyboard Tested, not working: - second dimm slot for each channel. Those are hooked up to the second rank of the channel, instead of rank 3 and 4. The raminit does not support such setups. Untested: - PCIe x1 slot, likely works fine - HDMI Tested using SeaBIOS 1.12, Linux 4.19. Change-Id: I88fe9c66dae079cd7eedcc9736c5922defbc0e5a Signed-off-by: Arthur Heymans Reviewed-on: https://review.coreboot.org/c/coreboot/+/31323 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki --- src/mainboard/asus/p5ql-em/Kconfig | 44 +++++ src/mainboard/asus/p5ql-em/Kconfig.name | 2 + src/mainboard/asus/p5ql-em/Makefile.inc | 16 ++ src/mainboard/asus/p5ql-em/acpi/ec.asl | 1 + .../asus/p5ql-em/acpi/ich10_pci_irqs.asl | 33 ++++ src/mainboard/asus/p5ql-em/acpi/superio.asl | 1 + src/mainboard/asus/p5ql-em/acpi_tables.c | 33 ++++ src/mainboard/asus/p5ql-em/board_info.txt | 6 + src/mainboard/asus/p5ql-em/cmos.default | 4 + src/mainboard/asus/p5ql-em/cmos.layout | 80 +++++++++ src/mainboard/asus/p5ql-em/data.vbt | Bin 0 -> 1899 bytes src/mainboard/asus/p5ql-em/devicetree.cb | 159 +++++++++++++++++ src/mainboard/asus/p5ql-em/dsdt.asl | 41 +++++ src/mainboard/asus/p5ql-em/gma-mainboard.ads | 29 +++ src/mainboard/asus/p5ql-em/gpio.c | 126 +++++++++++++ src/mainboard/asus/p5ql-em/hda_verb.c | 49 +++++ src/mainboard/asus/p5ql-em/romstage.c | 167 ++++++++++++++++++ 17 files changed, 791 insertions(+) create mode 100644 src/mainboard/asus/p5ql-em/Kconfig create mode 100644 src/mainboard/asus/p5ql-em/Kconfig.name create mode 100644 src/mainboard/asus/p5ql-em/Makefile.inc create mode 100644 src/mainboard/asus/p5ql-em/acpi/ec.asl create mode 100644 src/mainboard/asus/p5ql-em/acpi/ich10_pci_irqs.asl create mode 100644 src/mainboard/asus/p5ql-em/acpi/superio.asl create mode 100644 src/mainboard/asus/p5ql-em/acpi_tables.c create mode 100644 src/mainboard/asus/p5ql-em/board_info.txt create mode 100644 src/mainboard/asus/p5ql-em/cmos.default create mode 100644 src/mainboard/asus/p5ql-em/cmos.layout create mode 100644 src/mainboard/asus/p5ql-em/data.vbt create mode 100644 src/mainboard/asus/p5ql-em/devicetree.cb create mode 100644 src/mainboard/asus/p5ql-em/dsdt.asl create mode 100644 src/mainboard/asus/p5ql-em/gma-mainboard.ads create mode 100644 src/mainboard/asus/p5ql-em/gpio.c create mode 100644 src/mainboard/asus/p5ql-em/hda_verb.c create mode 100644 src/mainboard/asus/p5ql-em/romstage.c diff --git a/src/mainboard/asus/p5ql-em/Kconfig b/src/mainboard/asus/p5ql-em/Kconfig new file mode 100644 index 0000000000..403cf5525e --- /dev/null +++ b/src/mainboard/asus/p5ql-em/Kconfig @@ -0,0 +1,44 @@ +# +# This file is part of the coreboot project. +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; version 2 of the License. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# + +if BOARD_ASUS_P5QL_EM + +config BOARD_SPECIFIC_OPTIONS + def_bool y + select ARCH_X86 + select CPU_INTEL_SOCKET_LGA775 + select NORTHBRIDGE_INTEL_X4X + select SOUTHBRIDGE_INTEL_I82801JX + select SUPERIO_WINBOND_W83627DHG + select HAVE_ACPI_TABLES + select BOARD_ROMSIZE_KB_1024 + select HAVE_OPTION_TABLE + select HAVE_CMOS_DEFAULT + select HAVE_ACPI_RESUME + select INTEL_GMA_HAVE_VBT + select MAINBOARD_HAS_LIBGFXINIT + select REALTEK_8168_RESET + +config MAINBOARD_DIR + string + default "asus/p5ql-em" + +config MAINBOARD_PART_NUMBER + string + default "P5QL-EM" + +config MAX_CPUS + int + default 4 + +endif # BOARD_ASUS_P5QL_EM diff --git a/src/mainboard/asus/p5ql-em/Kconfig.name b/src/mainboard/asus/p5ql-em/Kconfig.name new file mode 100644 index 0000000000..4fe73a8c6f --- /dev/null +++ b/src/mainboard/asus/p5ql-em/Kconfig.name @@ -0,0 +1,2 @@ +config BOARD_ASUS_P5QL_EM + bool "P5QL-EM" diff --git a/src/mainboard/asus/p5ql-em/Makefile.inc b/src/mainboard/asus/p5ql-em/Makefile.inc new file mode 100644 index 0000000000..641e18f136 --- /dev/null +++ b/src/mainboard/asus/p5ql-em/Makefile.inc @@ -0,0 +1,16 @@ +# +# This file is part of the coreboot project. +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; version 2 of the License. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# + +romstage-y += gpio.c + +ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads diff --git a/src/mainboard/asus/p5ql-em/acpi/ec.asl b/src/mainboard/asus/p5ql-em/acpi/ec.asl new file mode 100644 index 0000000000..2997587d82 --- /dev/null +++ b/src/mainboard/asus/p5ql-em/acpi/ec.asl @@ -0,0 +1 @@ +/* dummy */ diff --git a/src/mainboard/asus/p5ql-em/acpi/ich10_pci_irqs.asl b/src/mainboard/asus/p5ql-em/acpi/ich10_pci_irqs.asl new file mode 100644 index 0000000000..37585da18d --- /dev/null +++ b/src/mainboard/asus/p5ql-em/acpi/ich10_pci_irqs.asl @@ -0,0 +1,33 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* This is board specific information: + * IRQ routing for the 0:1e.0 PCI bridge of the ICH10 + */ + +If (PICM) { + Return (Package() { + /* PCI slot */ + Package() { 0x0000ffff, 0, 0, 0x10}, + Package() { 0x0000ffff, 1, 0, 0x11}, + Package() { 0x0000ffff, 2, 0, 0x12}, + Package() { 0x0000ffff, 3, 0, 0x13}, + }) +} Else { + Return (Package() { + Package() { 0x0000ffff, 0, \_SB.PCI0.LPCB.LNKA, 0}, + Package() { 0x0000ffff, 1, \_SB.PCI0.LPCB.LNKB, 0}, + Package() { 0x0000ffff, 2, \_SB.PCI0.LPCB.LNKC, 0}, + Package() { 0x0000ffff, 3, \_SB.PCI0.LPCB.LNKD, 0}, + }) +} diff --git a/src/mainboard/asus/p5ql-em/acpi/superio.asl b/src/mainboard/asus/p5ql-em/acpi/superio.asl new file mode 100644 index 0000000000..8f414f586f --- /dev/null +++ b/src/mainboard/asus/p5ql-em/acpi/superio.asl @@ -0,0 +1 @@ +/* TODO */ diff --git a/src/mainboard/asus/p5ql-em/acpi_tables.c b/src/mainboard/asus/p5ql-em/acpi_tables.c new file mode 100644 index 0000000000..1dfb57bcdd --- /dev/null +++ b/src/mainboard/asus/p5ql-em/acpi_tables.c @@ -0,0 +1,33 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include + +void acpi_create_gnvs(global_nvs_t *gnvs) +{ + memset((void *)gnvs, 0, sizeof(*gnvs)); + + gnvs->pwrs = 1; /* Power state (AC = 1) */ + gnvs->osys = 2002; /* At least WINXP SP2 (HPET fix) */ + gnvs->apic = 1; /* Enable APIC */ + gnvs->mpen = 1; /* Enable Multi Processing */ + gnvs->cmap = 0x01; /* Enable COM 1 port */ +} + +/* TODO: Could work... */ +int get_cst_entries(acpi_cstate_t **entries) +{ + return 0; +} diff --git a/src/mainboard/asus/p5ql-em/board_info.txt b/src/mainboard/asus/p5ql-em/board_info.txt new file mode 100644 index 0000000000..ce64143eb7 --- /dev/null +++ b/src/mainboard/asus/p5ql-em/board_info.txt @@ -0,0 +1,6 @@ +Category: desktop +Board URL: https://www.asus.com/Motherboards/P5QLEM/ +ROM package: DIP-8 +ROM protocol: SPI +ROM socketed: y +Flashrom support: y diff --git a/src/mainboard/asus/p5ql-em/cmos.default b/src/mainboard/asus/p5ql-em/cmos.default new file mode 100644 index 0000000000..32960934e9 --- /dev/null +++ b/src/mainboard/asus/p5ql-em/cmos.default @@ -0,0 +1,4 @@ +boot_option=Fallback +debug_level=Debug +power_on_after_fail=Disable +nmi=Enable diff --git a/src/mainboard/asus/p5ql-em/cmos.layout b/src/mainboard/asus/p5ql-em/cmos.layout new file mode 100644 index 0000000000..9c707ad18e --- /dev/null +++ b/src/mainboard/asus/p5ql-em/cmos.layout @@ -0,0 +1,80 @@ +## +## This file is part of the coreboot project. +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +# ----------------------------------------------------------------- +entries + +# ----------------------------------------------------------------- +0 120 r 0 reserved_memory +#120 264 r 0 unused + +# ----------------------------------------------------------------- +# RTC_BOOT_BYTE (coreboot hardcoded) +384 1 e 4 boot_option +388 4 h 0 reboot_counter +#390 5 r 0 unused + +# ----------------------------------------------------------------- +# coreboot config options: console +395 4 e 6 debug_level + +# coreboot config options: southbridge +#408 1 e 0 unused +409 2 e 7 power_on_after_fail +411 1 e 1 nmi + +# coreboot config options: cpu +#424 8 r 0 unused + +# coreboot config options: northbridge +432 4 e 11 gfx_uma_size +#436 548 r 0 unused + +# coreboot config options: check sums +984 16 h 0 check_sum + +# ----------------------------------------------------------------- + +enumerations + +#ID value text +1 0 Disable +1 1 Enable +2 0 Enable +2 1 Disable +4 0 Fallback +4 1 Normal +6 0 Emergency +6 1 Alert +6 2 Critical +6 3 Error +6 4 Warning +6 5 Notice +6 6 Info +6 7 Debug +6 8 Spew +7 0 Disable +7 1 Enable +7 2 Keep +11 6 64M +11 7 128M +11 8 256M +11 9 96M +11 10 160M +11 11 224M +11 12 352M + +# ----------------------------------------------------------------- +checksums + +checksum 392 983 984 diff --git a/src/mainboard/asus/p5ql-em/data.vbt b/src/mainboard/asus/p5ql-em/data.vbt new file mode 100644 index 0000000000000000000000000000000000000000..5dd1803fa850451f6a5a6d65c506b0a05881e0b4 GIT binary patch literal 1899 zcmd6nO>7%Q6vzLwv%7X&+qH{noG8EqRh5gHWNoKb8iLsMN9%3f+Oe*#B%}&);(!Da2LuRlL_!erW_C>?N);i2#H`-@ z-pu^x?VFF?LyN_>s5mEUm6~(9B2?+X!qw0c)%Ta8TW?(~J8kD;u~sjg7VqF7o(ygO z0Cd3OdUnpT+!xlpZl-snvU0iWbyu!>qET{%bLo=T^?EDoUPrVRPdY+IibaYyu5>%% z?2YGFz23Z#(@8C|v(x!mA*^FFS!*U|S;vLQW#{w9=kv#6k#eO}Khtn)PTQ@Y74@bl zyDg{Hs+=j-o)wK|z3LX-cBLGP+@F2v+S<##E0>>J7n#x#L4mC)s`5gmEK1jUYtzE% zc12Tau8XF3-Rr&Rb*5tx8SO3)>kME9_A@ZPE#Nq1eS}4{sLq*T#Eg9`WISwCjJSS6 z&xoq6eFjYjCUtzV3^B}S`6G&Aq)Jo)f_%XKi$DWto-ZIjC}QY5i2toXpMaH{EzHd? z*v0aR>Zw|z*3L7K$KFmL_|g>?oP}Ci`umVHpS~Idr0#;z$rRdhDRT956*hRMRJjoZKo= z&Z`AX6Xm!d%JDx>Ll3D&ACf?y1xzZk{-obVO0mBgjNcy8*U?N98`@)BC%&$Y@-Xpj z?Po1Y{F+6z1o1njYboOQ>_>(~peHIlQR#_FPgHuM)K94X4ed)oZ(=6@N|F|0QQo&7 zp|$$?_rnQ4PnqvqlogUD(r?fOlceTyK&;9^b;qQ$XBiAaA#4xsr7;+Up8}msg5DtS zZpz;oqytVUaxQ}QA)?e}g7#n#d5_Zl-PtVJ_=B-m9Nj8uH!5UIMX~AezJ}I!PX0*i5OI&j4`)>|@ROW&LuKWv}h8unD5wyo6 + +#include +DefinitionBlock( + "dsdt.aml", + "DSDT", + 0x02, // DSDT revision: ACPI v2.0 and up + OEM_ID, + ACPI_TABLE_CREATOR, + 0x00000001 // OEM revision +) +{ + // global NVS and variables + #include + #include + + Scope (\_SB) { + Device (PCI0) + { + #include + #include + #include + } + } + + /* Chipset specific sleep states */ + #include +} diff --git a/src/mainboard/asus/p5ql-em/gma-mainboard.ads b/src/mainboard/asus/p5ql-em/gma-mainboard.ads new file mode 100644 index 0000000000..43a7d89a3a --- /dev/null +++ b/src/mainboard/asus/p5ql-em/gma-mainboard.ads @@ -0,0 +1,29 @@ +-- +-- This file is part of the coreboot project. +-- +-- This program is free software; you can redistribute it and/or modify +-- it under the terms of the GNU General Public License as published by +-- the Free Software Foundation; either version 2 of the License, or +-- (at your option) any later version. +-- +-- This program is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more details. +-- + +with HW.GFX.GMA; +with HW.GFX.GMA.Display_Probing; + +use HW.GFX.GMA; +use HW.GFX.GMA.Display_Probing; + +private package GMA.Mainboard is + + ports : constant Port_List := + (HDMI1, + HDMI2, + Analog, + others => Disabled); + +end GMA.Mainboard; diff --git a/src/mainboard/asus/p5ql-em/gpio.c b/src/mainboard/asus/p5ql-em/gpio.c new file mode 100644 index 0000000000..7e18c3dd50 --- /dev/null +++ b/src/mainboard/asus/p5ql-em/gpio.c @@ -0,0 +1,126 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include + +static const struct pch_gpio_set1 pch_gpio_set1_mode = { + .gpio0 = GPIO_MODE_GPIO, + .gpio1 = GPIO_MODE_GPIO, + .gpio6 = GPIO_MODE_GPIO, + .gpio7 = GPIO_MODE_GPIO, + .gpio8 = GPIO_MODE_GPIO, + .gpio10 = GPIO_MODE_GPIO, + .gpio12 = GPIO_MODE_GPIO, + .gpio13 = GPIO_MODE_GPIO, + .gpio14 = GPIO_MODE_GPIO, + .gpio18 = GPIO_MODE_GPIO, + .gpio19 = GPIO_MODE_GPIO, + .gpio20 = GPIO_MODE_GPIO, + .gpio21 = GPIO_MODE_GPIO, + .gpio22 = GPIO_MODE_GPIO, + .gpio24 = GPIO_MODE_GPIO, + .gpio27 = GPIO_MODE_GPIO, + .gpio28 = GPIO_MODE_GPIO, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_direction = { + .gpio0 = GPIO_DIR_INPUT, + .gpio1 = GPIO_DIR_INPUT, + .gpio6 = GPIO_DIR_INPUT, + .gpio7 = GPIO_DIR_INPUT, + .gpio8 = GPIO_DIR_INPUT, + .gpio10 = GPIO_DIR_INPUT, + .gpio12 = GPIO_DIR_OUTPUT, + .gpio13 = GPIO_DIR_INPUT, + .gpio14 = GPIO_DIR_INPUT, + .gpio18 = GPIO_DIR_OUTPUT, + .gpio19 = GPIO_DIR_INPUT, + .gpio20 = GPIO_DIR_OUTPUT, + .gpio21 = GPIO_DIR_OUTPUT, + .gpio22 = GPIO_DIR_INPUT, + .gpio24 = GPIO_DIR_OUTPUT, + .gpio27 = GPIO_DIR_OUTPUT, + .gpio28 = GPIO_DIR_OUTPUT, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_level = { + .gpio12 = GPIO_LEVEL_LOW, + .gpio18 = GPIO_LEVEL_HIGH, + .gpio20 = GPIO_LEVEL_HIGH, + .gpio21 = GPIO_LEVEL_HIGH, + .gpio24 = GPIO_LEVEL_LOW, + .gpio27 = GPIO_LEVEL_LOW, + .gpio28 = GPIO_LEVEL_LOW, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_invert = { + .gpio7 = GPIO_INVERT, + .gpio10 = GPIO_INVERT, + .gpio13 = GPIO_INVERT, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_blink = { +}; + +static const struct pch_gpio_set2 pch_gpio_set2_mode = { + .gpio32 = GPIO_MODE_GPIO, + .gpio33 = GPIO_MODE_GPIO, + .gpio34 = GPIO_MODE_GPIO, + .gpio35 = GPIO_MODE_GPIO, + .gpio36 = GPIO_MODE_GPIO, + .gpio37 = GPIO_MODE_GPIO, + .gpio38 = GPIO_MODE_GPIO, + .gpio39 = GPIO_MODE_GPIO, + .gpio48 = GPIO_MODE_GPIO, + .gpio49 = GPIO_MODE_GPIO, + .gpio56 = GPIO_MODE_GPIO, + .gpio57 = GPIO_MODE_GPIO, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_direction = { + .gpio32 = GPIO_DIR_OUTPUT, + .gpio33 = GPIO_DIR_OUTPUT, + .gpio34 = GPIO_DIR_OUTPUT, + .gpio35 = GPIO_DIR_OUTPUT, + .gpio36 = GPIO_DIR_INPUT, + .gpio37 = GPIO_DIR_INPUT, + .gpio38 = GPIO_DIR_INPUT, + .gpio39 = GPIO_DIR_INPUT, + .gpio48 = GPIO_DIR_INPUT, + .gpio49 = GPIO_DIR_OUTPUT, + .gpio56 = GPIO_DIR_INPUT, + .gpio57 = GPIO_DIR_INPUT, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_level = { + .gpio32 = GPIO_LEVEL_HIGH, + .gpio33 = GPIO_LEVEL_HIGH, + .gpio34 = GPIO_LEVEL_LOW, + .gpio35 = GPIO_LEVEL_LOW, + .gpio49 = GPIO_LEVEL_HIGH, +}; + +const struct pch_gpio_map mainboard_gpio_map = { + .set1 = { + .mode = &pch_gpio_set1_mode, + .direction = &pch_gpio_set1_direction, + .level = &pch_gpio_set1_level, + .blink = &pch_gpio_set1_blink, + .invert = &pch_gpio_set1_invert, + }, + .set2 = { + .mode = &pch_gpio_set2_mode, + .direction = &pch_gpio_set2_direction, + .level = &pch_gpio_set2_level, + }, +}; diff --git a/src/mainboard/asus/p5ql-em/hda_verb.c b/src/mainboard/asus/p5ql-em/hda_verb.c new file mode 100644 index 0000000000..3be50bb3b2 --- /dev/null +++ b/src/mainboard/asus/p5ql-em/hda_verb.c @@ -0,0 +1,49 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include + +const u32 cim_verb_data[] = { + /* coreboot specific header */ + 0x10ec0888, + 0x104382fe, // Subsystem ID + 13, // Number of entries + + /* Pin Widget Verb Table */ + AZALIA_PIN_CFG(0, 0x11, 0x99430130), + AZALIA_PIN_CFG(0, 0x14, 0x01014010), + AZALIA_PIN_CFG(0, 0x15, 0x01011012), + AZALIA_PIN_CFG(0, 0x16, 0x01016011), + AZALIA_PIN_CFG(0, 0x17, 0x01012014), + AZALIA_PIN_CFG(0, 0x18, 0x01a19840), + AZALIA_PIN_CFG(0, 0x19, 0x02a19c50), + AZALIA_PIN_CFG(0, 0x1a, 0x0181304f), + AZALIA_PIN_CFG(0, 0x1b, 0x02214c20), + AZALIA_PIN_CFG(0, 0x1c, 0x593301f0), + AZALIA_PIN_CFG(0, 0x1d, 0x4015e601), + AZALIA_PIN_CFG(0, 0x1e, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1f, 0x411111f0), + + /* HDMI audio */ + 0x80862803, + 0x80860101, + 1, + + AZALIA_PIN_CFG(1, 0x03, 0x18560010), +}; + +const u32 pc_beep_verbs[0] = {}; + +const u32 pc_beep_verbs_size = ARRAY_SIZE(pc_beep_verbs); +const u32 cim_verb_data_size = ARRAY_SIZE(cim_verb_data); diff --git a/src/mainboard/asus/p5ql-em/romstage.c b/src/mainboard/asus/p5ql-em/romstage.c new file mode 100644 index 0000000000..614f4874e1 --- /dev/null +++ b/src/mainboard/asus/p5ql-em/romstage.c @@ -0,0 +1,167 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define SERIAL_DEV PNP_DEV(0x2e, W83627DHG_SP1) +#define GPIO_DEV PNP_DEV(0x2e, W83627DHG_GPIO2345_V) +#define LPC_DEV PCI_DEV(0, 0x1f, 0) + +static u8 msr_get_fsb(void) +{ + u8 fsbcfg; + msr_t msr; + const u32 eax = cpuid_eax(1); + + /* Netburst */ + if (((eax >> 8) & 0xf) == 0xf) { + msr = rdmsr(MSR_EBC_FREQUENCY_ID); + fsbcfg = (msr.lo >> 16) & 0x7; + } else { /* Intel Core 2 */ + msr = rdmsr(MSR_FSB_FREQ); + fsbcfg = msr.lo & 0x7; + } + + return fsbcfg; +} + +/* BSEL MCH straps are not hooked up to the CPU as usual but to the SIO */ +static int setup_sio_gpio(void) +{ + int need_reset = 0; + u8 reg, old_reg; + + u8 bsel = msr_get_fsb(); + switch (bsel) { + case 0: + case 2: + case 4: + break; + default: + printk(BIOS_WARNING, + "BSEL: Unsupported FSB frequency, using 800MHz\n"); + bsel = 2; /* 800MHz */ + break; + } + + pnp_enter_ext_func_mode(GPIO_DEV); + pnp_set_logical_device(GPIO_DEV); + + /* + * P5QL-EM: + * BSEL0 -> not hooked up (not supported anyways) + * BSEL1 -> GPIO33 (inverted) + * BSEL2 -> GPIO40 + */ + reg = 0x92; + /* Multi-function Pin Selection */ + old_reg = pnp_read_config(GPIO_DEV, 0x2c); + pnp_write_config(GPIO_DEV, 0x2c, reg); + need_reset = (reg != old_reg); + + pnp_write_config(GPIO_DEV, 0x30, 0x0e); /* Enable GPIO3x,4x,5x */ + pnp_write_config(GPIO_DEV, 0xf0, 0xf3); /* GPIO3x direction */ + pnp_write_config(GPIO_DEV, 0xf2, 0x08); /* GPIO3x inversion */ + pnp_write_config(GPIO_DEV, 0xf4, 0x06); /* GPIO4x direction */ + + const int gpio33 = (bsel & 2) >> 1; + const int gpio40 = (bsel & 4) >> 2; + reg = (gpio33 << 3); + old_reg = pnp_read_config(GPIO_DEV, 0xf1); /* GPIO3x data */ + /* Set GPIO32 high like vendor firmware */ + pnp_write_config(GPIO_DEV, 0xf1, old_reg | reg | 4); + need_reset += ((reg & 0x8) != (old_reg & 0x8)); + + reg = gpio40; + old_reg = pnp_read_config(GPIO_DEV, 0xf5); /* GPIO4x data */ + pnp_write_config(GPIO_DEV, 0xf5, old_reg | reg); + need_reset += ((reg & 0x1) != (old_reg & 0x1)); + pnp_exit_ext_func_mode(GPIO_DEV); + + return need_reset; +} + +static void mb_gpio_init(void) +{ + /* Set the value for GPIO base address register and enable GPIO. */ + pci_write_config32(LPC_DEV, D31F0_GPIO_BASE, (DEFAULT_GPIOBASE | 1)); + pci_write_config8(LPC_DEV, D31F0_GPIO_CNTL, 0x10); + + setup_pch_gpios(&mainboard_gpio_map); + + /* Enable IOAPIC */ + RCBA8(0x31ff) = 0x03; + RCBA8(0x31ff); +} + +static void ich10_enable_lpc(void) +{ + /* Configure serial IRQs.*/ + pci_write_config16(LPC_DEV, D31F0_LPC_IODEC, 0x0010); + pci_write_config16(LPC_DEV, D31F0_LPC_EN, CNF1_LPC_EN | KBC_LPC_EN + | FDD_LPC_EN | LPT_LPC_EN | COMA_LPC_EN); + /* Hardware monitor IO range */ + pci_write_config32(LPC_DEV, D31F0_GEN1_DEC, 0x00000295); +} + +void mainboard_romstage_entry(void) +{ + /* This board has first dimm slot of each channel hooked up to + rank0 and rank1, while the second dimm slot is only connected + to rank1. The raminit does not support such setups + const u8 spd_addrmap[4] = { 0x50, 0x51, 0x52, 0x53 }; */ + const u8 spd_addrmap[4] = { 0x50, 0, 0x52, 0 }; + u8 boot_path = 0; + u8 s3_resume; + + /* Set southbridge and Super I/O GPIOs. */ + ich10_enable_lpc(); + mb_gpio_init(); + winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); + + console_init(); + + enable_smbus(); + + x4x_early_init(); + + s3_resume = southbridge_detect_s3_resume(); + if (s3_resume) + boot_path = BOOT_PATH_RESUME; + if (MCHBAR32(PMSTS_MCHBAR) & PMSTS_WARM_RESET) + boot_path = BOOT_PATH_WARM_RESET; + + if (!s3_resume && setup_sio_gpio()) { + printk(BIOS_DEBUG, "Needs reset to configure CPU BSEL straps\n"); + full_reset(); + } + + sdram_initialize(boot_path, spd_addrmap); + + x4x_late_init(s3_resume); + + printk(BIOS_DEBUG, "x4x late init complete\n"); +} From 9dd1a12f9c3199fe9f678a4997bb163a1eb1bb96 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ky=C3=B6sti=20M=C3=A4lkki?= Date: Wed, 6 Nov 2019 11:04:27 +0200 Subject: [PATCH 0068/1242] ELOG: Introduce elog_gsmi variants MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This avoids a lot of if (CONFIG(ELOG_GSMI)) boilerplate. Change-Id: I87d25c820daedeb33b3b474a6632a89ea80b0867 Signed-off-by: Kyösti Mälkki Reviewed-on: https://review.coreboot.org/c/coreboot/+/36647 Reviewed-by: Aaron Durbin Tested-by: build bot (Jenkins) --- src/ec/google/chromeec/smihandler.c | 4 ++-- src/include/elog.h | 10 ++++++++++ src/mainboard/google/auron/smihandler.c | 4 +--- src/mainboard/google/cyan/smihandler.c | 4 +--- src/mainboard/google/link/mainboard_smi.c | 4 +--- src/mainboard/google/rambi/mainboard_smi.c | 4 +--- src/mainboard/google/slippy/smihandler.c | 4 +--- src/mainboard/intel/strago/smihandler.c | 4 +--- src/soc/amd/picasso/smihandler.c | 3 +-- src/soc/amd/stoneyridge/smihandler.c | 3 +-- src/soc/intel/baytrail/smihandler.c | 15 ++++----------- src/soc/intel/braswell/smihandler.c | 16 +++++----------- src/soc/intel/broadwell/smihandler.c | 15 ++++----------- src/soc/intel/common/block/smm/smihandler.c | 7 +++---- src/soc/intel/fsp_baytrail/smihandler.c | 16 +++++----------- src/southbridge/intel/common/smihandler.c | 15 ++++----------- src/southbridge/intel/lynxpoint/smihandler.c | 15 ++++----------- 17 files changed, 49 insertions(+), 94 deletions(-) diff --git a/src/ec/google/chromeec/smihandler.c b/src/ec/google/chromeec/smihandler.c index eec888ecff..add0db3409 100644 --- a/src/ec/google/chromeec/smihandler.c +++ b/src/ec/google/chromeec/smihandler.c @@ -26,8 +26,8 @@ static int chromeec_process_one_event(void) uint8_t event = google_chromeec_get_event(); /* Log this event */ - if (CONFIG(ELOG_GSMI) && event) - elog_add_event_byte(ELOG_TYPE_EC_EVENT, event); + if (event) + elog_gsmi_add_event_byte(ELOG_TYPE_EC_EVENT, event); switch (event) { case EC_HOST_EVENT_LID_CLOSED: diff --git a/src/include/elog.h b/src/include/elog.h index 1692a809fc..8d1b3ba067 100644 --- a/src/include/elog.h +++ b/src/include/elog.h @@ -243,6 +243,16 @@ static inline int elog_smbios_write_type15(unsigned long *current, static inline int elog_add_extended_event(u8 type, u32 complement) { return 0; } #endif +#if CONFIG(ELOG_GSMI) +#define elog_gsmi_add_event elog_add_event +#define elog_gsmi_add_event_byte elog_add_event_byte +#define elog_gsmi_add_event_word elog_add_event_word +#else +static inline int elog_gsmi_add_event(u8 event_type) { return 0; } +static inline int elog_gsmi_add_event_byte(u8 event_type, u8 data) { return 0; } +static inline int elog_gsmi_add_event_word(u8 event_type, u16 data) { return 0; } +#endif + extern u32 gsmi_exec(u8 command, u32 *param); #if CONFIG(ELOG_BOOT_COUNT) diff --git a/src/mainboard/google/auron/smihandler.c b/src/mainboard/google/auron/smihandler.c index 790eeff77c..4cc0aa8221 100644 --- a/src/mainboard/google/auron/smihandler.c +++ b/src/mainboard/google/auron/smihandler.c @@ -33,11 +33,9 @@ static u8 mainboard_smi_ec(void) u8 cmd = google_chromeec_get_event(); u32 pm1_cnt; -#if CONFIG(ELOG_GSMI) /* Log this event */ if (cmd) - elog_add_event_byte(ELOG_TYPE_EC_EVENT, cmd); -#endif + elog_gsmi_add_event_byte(ELOG_TYPE_EC_EVENT, cmd); switch (cmd) { case EC_HOST_EVENT_LID_CLOSED: diff --git a/src/mainboard/google/cyan/smihandler.c b/src/mainboard/google/cyan/smihandler.c index 852d9c9a33..4db638441b 100644 --- a/src/mainboard/google/cyan/smihandler.c +++ b/src/mainboard/google/cyan/smihandler.c @@ -62,11 +62,9 @@ static uint8_t mainboard_smi_ec(void) uint16_t pmbase = get_pmbase(); uint32_t pm1_cnt; -#if CONFIG(ELOG_GSMI) /* Log this event */ if (cmd) - elog_add_event_byte(ELOG_TYPE_EC_EVENT, cmd); -#endif + elog_gsmi_add_event_byte(ELOG_TYPE_EC_EVENT, cmd); switch (cmd) { case EC_HOST_EVENT_LID_CLOSED: diff --git a/src/mainboard/google/link/mainboard_smi.c b/src/mainboard/google/link/mainboard_smi.c index 96ae1cc1c6..cd8fb092dd 100644 --- a/src/mainboard/google/link/mainboard_smi.c +++ b/src/mainboard/google/link/mainboard_smi.c @@ -32,11 +32,9 @@ static u8 mainboard_smi_ec(void) { u8 cmd = google_chromeec_get_event(); -#if CONFIG(ELOG_GSMI) /* Log this event */ if (cmd) - elog_add_event_byte(ELOG_TYPE_EC_EVENT, cmd); -#endif + elog_gsmi_add_event_byte(ELOG_TYPE_EC_EVENT, cmd); switch (cmd) { case EC_HOST_EVENT_LID_CLOSED: diff --git a/src/mainboard/google/rambi/mainboard_smi.c b/src/mainboard/google/rambi/mainboard_smi.c index 94f7b2b4cc..250e636fca 100644 --- a/src/mainboard/google/rambi/mainboard_smi.c +++ b/src/mainboard/google/rambi/mainboard_smi.c @@ -34,11 +34,9 @@ static uint8_t mainboard_smi_ec(void) uint16_t pmbase = get_pmbase(); uint32_t pm1_cnt; -#if CONFIG(ELOG_GSMI) /* Log this event */ if (cmd) - elog_add_event_byte(ELOG_TYPE_EC_EVENT, cmd); -#endif + elog_gsmi_add_event_byte(ELOG_TYPE_EC_EVENT, cmd); switch (cmd) { case EC_HOST_EVENT_LID_CLOSED: diff --git a/src/mainboard/google/slippy/smihandler.c b/src/mainboard/google/slippy/smihandler.c index 81a772c06b..48175880ce 100644 --- a/src/mainboard/google/slippy/smihandler.c +++ b/src/mainboard/google/slippy/smihandler.c @@ -41,11 +41,9 @@ static u8 mainboard_smi_ec(void) u8 cmd = google_chromeec_get_event(); u32 pm1_cnt; -#if CONFIG(ELOG_GSMI) /* Log this event */ if (cmd) - elog_add_event_byte(ELOG_TYPE_EC_EVENT, cmd); -#endif + elog_gsmi_add_event_byte(ELOG_TYPE_EC_EVENT, cmd); switch (cmd) { case EC_HOST_EVENT_LID_CLOSED: diff --git a/src/mainboard/intel/strago/smihandler.c b/src/mainboard/intel/strago/smihandler.c index 052e830171..a52c4ca76f 100644 --- a/src/mainboard/intel/strago/smihandler.c +++ b/src/mainboard/intel/strago/smihandler.c @@ -61,11 +61,9 @@ static uint8_t mainboard_smi_ec(void) uint16_t pmbase = get_pmbase(); uint32_t pm1_cnt; -#if CONFIG(ELOG_GSMI) /* Log this event */ if (cmd) - elog_add_event_byte(ELOG_TYPE_EC_EVENT, cmd); -#endif + elog_gsmi_add_event_byte(ELOG_TYPE_EC_EVENT, cmd); switch (cmd) { case EC_HOST_EVENT_LID_CLOSED: diff --git a/src/soc/amd/picasso/smihandler.c b/src/soc/amd/picasso/smihandler.c index 4995acb484..39c2dfd09b 100644 --- a/src/soc/amd/picasso/smihandler.c +++ b/src/soc/amd/picasso/smihandler.c @@ -153,8 +153,7 @@ static void sb_slp_typ_handler(void) if (slp_typ >= ACPI_S3) { /* Sleep Type Elog S3, S4, and S5 entry */ - if (CONFIG(ELOG_GSMI)) - elog_add_event_byte(ELOG_TYPE_ACPI_ENTER, slp_typ); + elog_gsmi_add_event_byte(ELOG_TYPE_ACPI_ENTER, slp_typ); wbinvd(); diff --git a/src/soc/amd/stoneyridge/smihandler.c b/src/soc/amd/stoneyridge/smihandler.c index 9eddf853b6..2b883972c9 100644 --- a/src/soc/amd/stoneyridge/smihandler.c +++ b/src/soc/amd/stoneyridge/smihandler.c @@ -153,8 +153,7 @@ static void sb_slp_typ_handler(void) if (slp_typ >= ACPI_S3) { /* Sleep Type Elog S3, S4, and S5 entry */ - if (CONFIG(ELOG_GSMI)) - elog_add_event_byte(ELOG_TYPE_ACPI_ENTER, slp_typ); + elog_gsmi_add_event_byte(ELOG_TYPE_ACPI_ENTER, slp_typ); wbinvd(); diff --git a/src/soc/intel/baytrail/smihandler.c b/src/soc/intel/baytrail/smihandler.c index 7de9d960a0..16e2d950b5 100644 --- a/src/soc/intel/baytrail/smihandler.c +++ b/src/soc/intel/baytrail/smihandler.c @@ -114,11 +114,9 @@ static void southbridge_smi_sleep(void) /* Do any mainboard sleep handling */ mainboard_smi_sleep(slp_typ); -#if CONFIG(ELOG_GSMI) /* Log S3, S4, and S5 entry */ if (slp_typ >= ACPI_S3) - elog_add_event_byte(ELOG_TYPE_ACPI_ENTER, slp_typ); -#endif + elog_gsmi_add_event_byte(ELOG_TYPE_ACPI_ENTER, slp_typ); /* Next, do the deed. */ @@ -210,7 +208,6 @@ static em64t100_smm_state_save_area_t *smi_apmc_find_state_save(uint8_t cmd) return NULL; } -#if CONFIG(ELOG_GSMI) static void southbridge_smi_gsmi(void) { u32 *ret, *param; @@ -231,7 +228,6 @@ static void southbridge_smi_gsmi(void) /* drivers/elog/gsmi.c */ *ret = gsmi_exec(sub_command, param); } -#endif static void finalize(void) { @@ -348,11 +344,10 @@ static void southbridge_smi_apmc(void) printk(BIOS_DEBUG, "SMI#: Setting GNVS to %p\n", gnvs); } break; -#if CONFIG(ELOG_GSMI) case APM_CNT_ELOG_GSMI: - southbridge_smi_gsmi(); + if (CONFIG(ELOG_GSMI)) + southbridge_smi_gsmi(); break; -#endif case APM_CNT_FINALIZE: finalize(); break; @@ -374,9 +369,7 @@ static void southbridge_smi_pm1(void) */ if (pm1_sts & PWRBTN_STS) { // power button pressed -#if CONFIG(ELOG_GSMI) - elog_add_event(ELOG_TYPE_POWER_BUTTON); -#endif + elog_gsmi_add_event(ELOG_TYPE_POWER_BUTTON); disable_pm1_control(-1UL); enable_pm1_control(SLP_EN | (SLP_TYP_S5 << SLP_TYP_SHIFT)); } diff --git a/src/soc/intel/braswell/smihandler.c b/src/soc/intel/braswell/smihandler.c index 174cd5d7ef..b94fe653ad 100644 --- a/src/soc/intel/braswell/smihandler.c +++ b/src/soc/intel/braswell/smihandler.c @@ -154,11 +154,10 @@ static void southbridge_smi_sleep(void) /* Do any mainboard sleep handling */ mainboard_smi_sleep(slp_typ); -#if CONFIG(ELOG_GSMI) /* Log S3, S4, and S5 entry */ if (slp_typ >= ACPI_S3) - elog_add_event_byte(ELOG_TYPE_ACPI_ENTER, slp_typ); -#endif + elog_gsmi_add_event_byte(ELOG_TYPE_ACPI_ENTER, slp_typ); + /* Clear pending GPE events */ clear_gpe_status(); @@ -260,7 +259,6 @@ static em64t100_smm_state_save_area_t *smi_apmc_find_state_save(uint8_t cmd) return NULL; } -#if CONFIG(ELOG_GSMI) static void southbridge_smi_gsmi(void) { u32 *ret, *param; @@ -281,7 +279,6 @@ static void southbridge_smi_gsmi(void) /* drivers/elog/gsmi.c */ *ret = gsmi_exec(sub_command, param); } -#endif static void finalize(void) { @@ -346,11 +343,10 @@ static void southbridge_smi_apmc(void) printk(BIOS_DEBUG, "SMI#: Setting GNVS to %p\n", gnvs); } break; -#if CONFIG(ELOG_GSMI) case APM_CNT_ELOG_GSMI: - southbridge_smi_gsmi(); + if (CONFIG(ELOG_GSMI)) + southbridge_smi_gsmi(); break; -#endif case APM_CNT_FINALIZE: finalize(); break; @@ -369,9 +365,7 @@ static void southbridge_smi_pm1(void) */ if (pm1_sts & PWRBTN_STS) { /* power button pressed */ -#if CONFIG(ELOG_GSMI) - elog_add_event(ELOG_TYPE_POWER_BUTTON); -#endif + elog_gsmi_add_event(ELOG_TYPE_POWER_BUTTON); disable_pm1_control(-1UL); enable_pm1_control(SLP_EN | (SLP_TYP_S5 << SLP_TYP_SHIFT)); } diff --git a/src/soc/intel/broadwell/smihandler.c b/src/soc/intel/broadwell/smihandler.c index bad158748d..d37f65a16f 100644 --- a/src/soc/intel/broadwell/smihandler.c +++ b/src/soc/intel/broadwell/smihandler.c @@ -179,11 +179,9 @@ static void southbridge_smi_sleep(void) /* USB sleep preparations */ usb_xhci_sleep_prepare(PCH_DEV_XHCI, slp_typ); -#if CONFIG(ELOG_GSMI) /* Log S3, S4, and S5 entry */ if (slp_typ >= ACPI_S3) - elog_add_event_byte(ELOG_TYPE_ACPI_ENTER, slp_typ); -#endif + elog_gsmi_add_event_byte(ELOG_TYPE_ACPI_ENTER, slp_typ); /* Clear pending GPE events */ clear_gpe_status(); @@ -293,7 +291,6 @@ static em64t101_smm_state_save_area_t *smi_apmc_find_state_save(u8 cmd) return NULL; } -#if CONFIG(ELOG_GSMI) static void southbridge_smi_gsmi(void) { u32 *ret, *param; @@ -314,7 +311,6 @@ static void southbridge_smi_gsmi(void) /* drivers/elog/gsmi.c */ *ret = gsmi_exec(sub_command, param); } -#endif static void finalize(void) { @@ -372,11 +368,10 @@ static void southbridge_smi_apmc(void) printk(BIOS_DEBUG, "SMI#: Setting GNVS to %p\n", gnvs); } break; -#if CONFIG(ELOG_GSMI) case APM_CNT_ELOG_GSMI: - southbridge_smi_gsmi(); + if (CONFIG(ELOG_GSMI)) + southbridge_smi_gsmi(); break; -#endif } mainboard_smi_apmc(reg8); @@ -391,9 +386,7 @@ static void southbridge_smi_pm1(void) */ if (pm1_sts & PWRBTN_STS) { /* power button pressed */ -#if CONFIG(ELOG_GSMI) - elog_add_event(ELOG_TYPE_POWER_BUTTON); -#endif + elog_gsmi_add_event(ELOG_TYPE_POWER_BUTTON); disable_pm1_control(-1UL); enable_pm1_control(SLP_EN | (SLP_TYP_S5 << 10)); } diff --git a/src/soc/intel/common/block/smm/smihandler.c b/src/soc/intel/common/block/smm/smihandler.c index 9e98aae564..0581d23021 100644 --- a/src/soc/intel/common/block/smm/smihandler.c +++ b/src/soc/intel/common/block/smm/smihandler.c @@ -195,8 +195,8 @@ void smihandler_southbridge_sleep( mainboard_smi_sleep(slp_typ); /* Log S3, S4, and S5 entry */ - if (slp_typ >= ACPI_S3 && CONFIG(ELOG_GSMI)) - elog_add_event_byte(ELOG_TYPE_ACPI_ENTER, slp_typ); + if (slp_typ >= ACPI_S3) + elog_gsmi_add_event_byte(ELOG_TYPE_ACPI_ENTER, slp_typ); /* Clear pending GPE events */ pmc_clear_all_gpe_status(); @@ -413,8 +413,7 @@ void smihandler_southbridge_pm1( */ if ((pm1_sts & PWRBTN_STS) && (pm1_en & PWRBTN_EN)) { /* power button pressed */ - if (CONFIG(ELOG_GSMI)) - elog_add_event(ELOG_TYPE_POWER_BUTTON); + elog_gsmi_add_event(ELOG_TYPE_POWER_BUTTON); pmc_disable_pm1_control(-1UL); pmc_enable_pm1_control(SLP_EN | (SLP_TYP_S5 << SLP_TYP_SHIFT)); } diff --git a/src/soc/intel/fsp_baytrail/smihandler.c b/src/soc/intel/fsp_baytrail/smihandler.c index 2a7376ad7d..1a8fb4b6e6 100644 --- a/src/soc/intel/fsp_baytrail/smihandler.c +++ b/src/soc/intel/fsp_baytrail/smihandler.c @@ -112,11 +112,9 @@ static void southbridge_smi_sleep(void) /* Do any mainboard sleep handling */ mainboard_smi_sleep(slp_typ); -#if CONFIG(ELOG_GSMI) /* Log S3, S4, and S5 entry */ if (slp_typ >= ACPI_S3) - elog_add_event_byte(ELOG_TYPE_ACPI_ENTER, slp_typ); -#endif + elog_gsmi_add_event_byte(ELOG_TYPE_ACPI_ENTER, slp_typ); /* Next, do the deed. */ @@ -208,7 +206,6 @@ static em64t100_smm_state_save_area_t *smi_apmc_find_state_save(uint8_t cmd) return NULL; } -#if CONFIG(ELOG_GSMI) static void southbridge_smi_gsmi(void) { u32 *ret, *param; @@ -229,7 +226,7 @@ static void southbridge_smi_gsmi(void) /* drivers/elog/gsmi.c */ *ret = gsmi_exec(sub_command, param); } -#endif + static void southbridge_smi_apmc(void) { uint8_t reg8; @@ -275,11 +272,10 @@ static void southbridge_smi_apmc(void) printk(BIOS_DEBUG, "SMI#: Setting GNVS to %p\n", gnvs); } break; -#if CONFIG(ELOG_GSMI) case APM_CNT_ELOG_GSMI: - southbridge_smi_gsmi(); + if (CONFIG(ELOG_GSMI)) + southbridge_smi_gsmi(); break; -#endif } mainboard_smi_apmc(reg8); @@ -294,9 +290,7 @@ static void southbridge_smi_pm1(void) */ if (pm1_sts & PWRBTN_STS) { // power button pressed -#if CONFIG(ELOG_GSMI) - elog_add_event(ELOG_TYPE_POWER_BUTTON); -#endif + elog_gsmi_add_event(ELOG_TYPE_POWER_BUTTON); disable_pm1_control(-1UL); enable_pm1_control(SLP_EN | (SLP_TYP_S5 << SLP_TYP_SHIFT)); } diff --git a/src/southbridge/intel/common/smihandler.c b/src/southbridge/intel/common/smihandler.c index 5582051bc5..7f376fd354 100644 --- a/src/southbridge/intel/common/smihandler.c +++ b/src/southbridge/intel/common/smihandler.c @@ -138,11 +138,9 @@ static void southbridge_smi_sleep(void) /* Do any mainboard sleep handling */ mainboard_smi_sleep(slp_typ); -#if CONFIG(ELOG_GSMI) /* Log S3, S4, and S5 entry */ if (slp_typ >= ACPI_S3) - elog_add_event_byte(ELOG_TYPE_ACPI_ENTER, slp_typ); -#endif + elog_gsmi_add_event_byte(ELOG_TYPE_ACPI_ENTER, slp_typ); /* Next, do the deed. */ @@ -246,7 +244,6 @@ em64t101_smm_state_save_area_t *smi_apmc_find_state_save(u8 cmd) return NULL; } -#if CONFIG(ELOG_GSMI) static void southbridge_smi_gsmi(void) { u32 *ret, *param; @@ -267,7 +264,6 @@ static void southbridge_smi_gsmi(void) /* drivers/elog/gsmi.c */ *ret = gsmi_exec(sub_command, param); } -#endif static void southbridge_smi_store(void) { @@ -338,11 +334,10 @@ static void southbridge_smi_apmc(void) southbridge_finalize_all(); mainboard_finalized = 1; break; -#if CONFIG(ELOG_GSMI) case APM_CNT_ELOG_GSMI: - southbridge_smi_gsmi(); + if (CONFIG(ELOG_GSMI)) + southbridge_smi_gsmi(); break; -#endif case APM_CNT_SMMSTORE: if (CONFIG(SMMSTORE)) southbridge_smi_store(); @@ -366,9 +361,7 @@ static void southbridge_smi_pm1(void) // power button pressed u32 reg32; reg32 = (7 << 10) | (1 << 13); -#if CONFIG(ELOG_GSMI) - elog_add_event(ELOG_TYPE_POWER_BUTTON); -#endif + elog_gsmi_add_event(ELOG_TYPE_POWER_BUTTON); write_pmbase32(PM1_CNT, reg32); } } diff --git a/src/southbridge/intel/lynxpoint/smihandler.c b/src/southbridge/intel/lynxpoint/smihandler.c index de2866e08c..61f86fb067 100644 --- a/src/southbridge/intel/lynxpoint/smihandler.c +++ b/src/southbridge/intel/lynxpoint/smihandler.c @@ -140,11 +140,9 @@ static void southbridge_smi_sleep(void) #endif usb_xhci_sleep_prepare(PCH_XHCI_DEV, slp_typ); -#if CONFIG(ELOG_GSMI) /* Log S3, S4, and S5 entry */ if (slp_typ >= ACPI_S3) - elog_add_event_byte(ELOG_TYPE_ACPI_ENTER, slp_typ); -#endif + elog_gsmi_add_event_byte(ELOG_TYPE_ACPI_ENTER, slp_typ); /* Next, do the deed. */ @@ -247,7 +245,6 @@ static em64t101_smm_state_save_area_t *smi_apmc_find_state_save(u8 cmd) return NULL; } -#if CONFIG(ELOG_GSMI) static void southbridge_smi_gsmi(void) { u32 *ret, *param; @@ -268,7 +265,6 @@ static void southbridge_smi_gsmi(void) /* drivers/elog/gsmi.c */ *ret = gsmi_exec(sub_command, param); } -#endif static void southbridge_smi_apmc(void) { @@ -332,11 +328,10 @@ static void southbridge_smi_apmc(void) case 0xca: usb_xhci_route_all(); break; -#if CONFIG(ELOG_GSMI) case APM_CNT_ELOG_GSMI: - southbridge_smi_gsmi(); + if (CONFIG(ELOG_GSMI)) + southbridge_smi_gsmi(); break; -#endif } mainboard_smi_apmc(reg8); @@ -351,9 +346,7 @@ static void southbridge_smi_pm1(void) */ if (pm1_sts & PWRBTN_STS) { // power button pressed -#if CONFIG(ELOG_GSMI) - elog_add_event(ELOG_TYPE_POWER_BUTTON); -#endif + elog_gsmi_add_event(ELOG_TYPE_POWER_BUTTON); disable_pm1_control(-1UL); enable_pm1_control(SLP_EN | (SLP_TYP_S5 << 10)); } From be5317f6d0084b1997ff7342fbf5a5af3eecd950 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ky=C3=B6sti=20M=C3=A4lkki?= Date: Wed, 6 Nov 2019 12:07:21 +0200 Subject: [PATCH 0069/1242] ELOG: Avoid some preprocessor use MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Change-Id: I8daf8868af2e8c2b07b0dda0eeaf863f2f550c59 Signed-off-by: Kyösti Mälkki Reviewed-on: https://review.coreboot.org/c/coreboot/+/36648 Reviewed-by: Aaron Durbin Tested-by: build bot (Jenkins) --- src/ec/quanta/ene_kb3940q/ec.c | 10 +++++----- src/soc/intel/broadwell/me.c | 4 +--- src/southbridge/intel/bd82x6x/me.c | 4 +--- src/southbridge/intel/bd82x6x/me_8.x.c | 4 +--- src/southbridge/intel/ibexpeak/lpc.c | 2 -- src/southbridge/intel/ibexpeak/me.c | 4 +--- src/southbridge/intel/lynxpoint/me_9.x.c | 4 +--- src/southbridge/intel/lynxpoint/smi.c | 6 +++--- 8 files changed, 13 insertions(+), 25 deletions(-) diff --git a/src/ec/quanta/ene_kb3940q/ec.c b/src/ec/quanta/ene_kb3940q/ec.c index 4fc38da99d..5de6336040 100644 --- a/src/ec/quanta/ene_kb3940q/ec.c +++ b/src/ec/quanta/ene_kb3940q/ec.c @@ -125,11 +125,11 @@ void ec_mem_write(u8 addr, u8 data) static void ene_kb3940q_log_events(void) { -#if CONFIG(ELOG) - u8 reason = ec_mem_read(EC_SHUTDOWN_REASON); - if (reason) - elog_add_event_byte(ELOG_TYPE_EC_SHUTDOWN, reason); -#endif + if (CONFIG(ELOG)) { + u8 reason = ec_mem_read(EC_SHUTDOWN_REASON); + if (reason) + elog_add_event_byte(ELOG_TYPE_EC_SHUTDOWN, reason); + } } static void ene_kb3940q_init(struct device *dev) diff --git a/src/soc/intel/broadwell/me.c b/src/soc/intel/broadwell/me.c index 0461428ba5..0021d2c48a 100644 --- a/src/soc/intel/broadwell/me.c +++ b/src/soc/intel/broadwell/me.c @@ -700,8 +700,7 @@ static me_bios_path intel_me_path(struct device *dev) path = ME_ERROR_BIOS_PATH; } -#if CONFIG(ELOG) - if (path != ME_NORMAL_BIOS_PATH) { + if (CONFIG(ELOG) && path != ME_NORMAL_BIOS_PATH) { struct elog_event_data_me_extended data = { .current_working_state = hfs.working_state, .operation_state = hfs.operation_state, @@ -715,7 +714,6 @@ static me_bios_path intel_me_path(struct device *dev) elog_add_event_raw(ELOG_TYPE_MANAGEMENT_ENGINE_EXT, &data, sizeof(data)); } -#endif return path; } diff --git a/src/southbridge/intel/bd82x6x/me.c b/src/southbridge/intel/bd82x6x/me.c index 5e355a110f..8adb95bdb3 100644 --- a/src/southbridge/intel/bd82x6x/me.c +++ b/src/southbridge/intel/bd82x6x/me.c @@ -585,8 +585,7 @@ static me_bios_path intel_me_path(struct device *dev) if (hfs.error_code || hfs.fpt_bad) path = ME_ERROR_BIOS_PATH; -#if CONFIG(ELOG) - if (path != ME_NORMAL_BIOS_PATH) { + if (CONFIG(ELOG) && path != ME_NORMAL_BIOS_PATH) { struct elog_event_data_me_extended data = { .current_working_state = hfs.working_state, .operation_state = hfs.operation_state, @@ -600,7 +599,6 @@ static me_bios_path intel_me_path(struct device *dev) elog_add_event_raw(ELOG_TYPE_MANAGEMENT_ENGINE_EXT, &data, sizeof(data)); } -#endif return path; } diff --git a/src/southbridge/intel/bd82x6x/me_8.x.c b/src/southbridge/intel/bd82x6x/me_8.x.c index c224cb4903..7af969517d 100644 --- a/src/southbridge/intel/bd82x6x/me_8.x.c +++ b/src/southbridge/intel/bd82x6x/me_8.x.c @@ -573,8 +573,7 @@ static me_bios_path intel_me_path(struct device *dev) path = ME_ERROR_BIOS_PATH; } -#if CONFIG(ELOG) - if (path != ME_NORMAL_BIOS_PATH) { + if (CONFIG(ELOG) && path != ME_NORMAL_BIOS_PATH) { struct elog_event_data_me_extended data = { .current_working_state = hfs.working_state, .operation_state = hfs.operation_state, @@ -588,7 +587,6 @@ static me_bios_path intel_me_path(struct device *dev) elog_add_event_raw(ELOG_TYPE_MANAGEMENT_ENGINE_EXT, &data, sizeof(data)); } -#endif return path; } diff --git a/src/southbridge/intel/ibexpeak/lpc.c b/src/southbridge/intel/ibexpeak/lpc.c index 36576563aa..64be11e9f9 100644 --- a/src/southbridge/intel/ibexpeak/lpc.c +++ b/src/southbridge/intel/ibexpeak/lpc.c @@ -286,9 +286,7 @@ static void pch_rtc_init(struct device *dev) if (rtc_failed) { reg8 &= ~RTC_BATTERY_DEAD; pci_write_config8(dev, GEN_PMCON_3, reg8); -#if CONFIG(ELOG) elog_add_event(ELOG_TYPE_RTC_RESET); -#endif } printk(BIOS_DEBUG, "rtc_failed = 0x%x\n", rtc_failed); diff --git a/src/southbridge/intel/ibexpeak/me.c b/src/southbridge/intel/ibexpeak/me.c index c944f63ee1..6aa33cad90 100644 --- a/src/southbridge/intel/ibexpeak/me.c +++ b/src/southbridge/intel/ibexpeak/me.c @@ -469,8 +469,7 @@ static me_bios_path intel_me_path(struct device *dev) if (hfs.error_code || hfs.fpt_bad) path = ME_ERROR_BIOS_PATH; -#if CONFIG(ELOG) - if (path != ME_NORMAL_BIOS_PATH) { + if (CONFIG(ELOG) && path != ME_NORMAL_BIOS_PATH) { struct elog_event_data_me_extended data = { .current_working_state = hfs.working_state, .operation_state = hfs.operation_state, @@ -484,7 +483,6 @@ static me_bios_path intel_me_path(struct device *dev) elog_add_event_raw(ELOG_TYPE_MANAGEMENT_ENGINE_EXT, &data, sizeof(data)); } -#endif return path; } diff --git a/src/southbridge/intel/lynxpoint/me_9.x.c b/src/southbridge/intel/lynxpoint/me_9.x.c index 1c45e2d99b..429fa42ab1 100644 --- a/src/southbridge/intel/lynxpoint/me_9.x.c +++ b/src/southbridge/intel/lynxpoint/me_9.x.c @@ -718,8 +718,7 @@ static me_bios_path intel_me_path(struct device *dev) path = ME_ERROR_BIOS_PATH; } -#if CONFIG(ELOG) - if (path != ME_NORMAL_BIOS_PATH) { + if (CONFIG(ELOG) && path != ME_NORMAL_BIOS_PATH) { struct elog_event_data_me_extended data = { .current_working_state = hfs.working_state, .operation_state = hfs.operation_state, @@ -733,7 +732,6 @@ static me_bios_path intel_me_path(struct device *dev) elog_add_event_raw(ELOG_TYPE_MANAGEMENT_ENGINE_EXT, &data, sizeof(data)); } -#endif return path; } diff --git a/src/southbridge/intel/lynxpoint/smi.c b/src/southbridge/intel/lynxpoint/smi.c index 4fb00b507a..e5c390ef50 100644 --- a/src/southbridge/intel/lynxpoint/smi.c +++ b/src/southbridge/intel/lynxpoint/smi.c @@ -29,10 +29,10 @@ void smm_southbridge_clear_state(void) { u32 smi_en; -#if CONFIG(ELOG) /* Log events from chipset before clearing */ - pch_log_state(); -#endif + if (CONFIG(ELOG)) + pch_log_state(); + printk(BIOS_DEBUG, "Initializing Southbridge SMI..."); printk(BIOS_SPEW, " ... pmbase = 0x%04x\n", get_pmbase()); From 21d6a27ac07d5233a7dd473d84c4c0b541059146 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ky=C3=B6sti=20M=C3=A4lkki?= Date: Tue, 5 Nov 2019 18:50:38 +0200 Subject: [PATCH 0070/1242] arch/x86: Replace some __SMM__ guards MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit We generally do not guard source in attempts to reduce the final object sizes, but rely on garbage collection. Most of the __unused attributes inserted here will be removed when remaining __SIMPLE_DEVICE__ guards can be removed. Change-Id: I2440931fab4f41d7e8249c082e6c9b5a9cd0ef13 Signed-off-by: Kyösti Mälkki Reviewed-on: https://review.coreboot.org/c/coreboot/+/36641 Reviewed-by: Aaron Durbin Tested-by: build bot (Jenkins) --- src/mainboard/google/stout/ec.c | 9 +------ src/soc/intel/baytrail/pmutil.c | 7 +++--- src/soc/intel/braswell/pmutil.c | 8 +++---- src/soc/intel/broadwell/xhci.c | 6 ++--- src/southbridge/intel/bd82x6x/me.c | 25 ++++++++----------- src/southbridge/intel/bd82x6x/me_8.x.c | 27 +++++++++------------ src/southbridge/intel/bd82x6x/pch.c | 7 ++---- src/southbridge/intel/common/gpio.c | 2 +- src/southbridge/intel/common/pmbase.c | 2 +- src/southbridge/intel/ibexpeak/me.c | 28 ++++++++++------------ src/southbridge/intel/lynxpoint/me_9.x.c | 26 ++++++++++++-------- src/southbridge/intel/lynxpoint/pch.c | 4 ++-- src/southbridge/intel/lynxpoint/usb_ehci.c | 6 ++--- src/southbridge/intel/lynxpoint/usb_xhci.c | 6 ++--- 14 files changed, 72 insertions(+), 91 deletions(-) diff --git a/src/mainboard/google/stout/ec.c b/src/mainboard/google/stout/ec.c index 59987a156d..0ea32bcfc3 100644 --- a/src/mainboard/google/stout/ec.c +++ b/src/mainboard/google/stout/ec.c @@ -17,6 +17,7 @@ #include #include #include +#include #include #include #include @@ -25,11 +26,6 @@ #include #include "ec.h" -#ifdef __SMM__ -#include -#endif - -#ifndef __SMM__ void stout_ec_init(void) { @@ -59,8 +55,6 @@ void stout_ec_init(void) // TODO: Power Limit Setting } -#else // SMM - void stout_ec_finalize_smm(void) { u8 ec_reg, critical_shutdown = 0; @@ -105,4 +99,3 @@ void stout_ec_finalize_smm(void) write_pmbase32(PM1_CNT, read_pmbase32(PM1_CNT) | (0xf << 10)); } } -#endif //__SMM__ diff --git a/src/soc/intel/baytrail/pmutil.c b/src/soc/intel/baytrail/pmutil.c index b740a03818..51174fc130 100644 --- a/src/soc/intel/baytrail/pmutil.c +++ b/src/soc/intel/baytrail/pmutil.c @@ -16,7 +16,9 @@ #include #include #include +#include #include +#include #include #include #include @@ -37,10 +39,7 @@ static inline pci_devfn_t get_pcu_dev(void) return pcu_dev; } -#else /* !__SMM__ */ -#include -#include - +#else static struct device *pcu_dev; static struct device *get_pcu_dev(void) { diff --git a/src/soc/intel/braswell/pmutil.c b/src/soc/intel/braswell/pmutil.c index 4bc621b80e..18cb04dd89 100644 --- a/src/soc/intel/braswell/pmutil.c +++ b/src/soc/intel/braswell/pmutil.c @@ -17,7 +17,9 @@ #include #include #include +#include #include +#include #include #include #include @@ -37,9 +39,7 @@ static inline pci_devfn_t get_pcu_dev(void) return pcu_dev; } -#else /* ENV_SMM */ -#include -#include +#else /* __SIMPLE_DEVICE__ */ static struct device *pcu_dev; static struct device *get_pcu_dev(void) @@ -48,7 +48,7 @@ static struct device *get_pcu_dev(void) pcu_dev = pcidev_on_root(PCU_DEV, 0); return pcu_dev; } -#endif /* ENV_SMM */ +#endif /* __SIMPLE_DEVICE__ */ uint16_t get_pmbase(void) { diff --git a/src/soc/intel/broadwell/xhci.c b/src/soc/intel/broadwell/xhci.c index 477998731d..00b8b8ca87 100644 --- a/src/soc/intel/broadwell/xhci.c +++ b/src/soc/intel/broadwell/xhci.c @@ -24,7 +24,7 @@ #include #include -#ifdef __SMM__ +#ifdef __SIMPLE_DEVICE__ static u8 *usb_xhci_mem_base(pci_devfn_t dev) { u32 mem_base = pci_read_config32(dev, PCI_BASE_ADDRESS_0); @@ -196,7 +196,7 @@ void usb_xhci_sleep_prepare(pci_devfn_t dev, u8 slp_typ) pci_or_config16(dev, XHCI_PWR_CTL_STS, XHCI_PWR_CTL_STATUS_PME); pci_or_config16(dev, XHCI_PWR_CTL_STS, XHCI_PWR_CTL_ENABLE_PME); } -#else /* !__SMM__ */ +#else /* !__SIMPLE_DEVICE__ */ static void xhci_init(struct device *dev) { @@ -235,4 +235,4 @@ static const struct pci_driver pch_usb_xhci __pci_driver = { .vendor = PCI_VENDOR_ID_INTEL, .devices = pci_device_ids, }; -#endif /* !__SMM__ */ +#endif /* !__SIMPLE_DEVICE__ */ diff --git a/src/southbridge/intel/bd82x6x/me.c b/src/southbridge/intel/bd82x6x/me.c index 8adb95bdb3..15f99cdf78 100644 --- a/src/southbridge/intel/bd82x6x/me.c +++ b/src/southbridge/intel/bd82x6x/me.c @@ -26,6 +26,8 @@ #include #include #include +#include +#include #include #include #include @@ -33,11 +35,6 @@ #include #include -#ifndef __SMM__ -#include -#include -#endif - #include "me.h" #include "pch.h" @@ -45,9 +42,8 @@ #include #endif -#ifndef __SMM__ /* Path that the BIOS should take based on ME state */ -static const char *me_bios_path_values[] = { +static const char *me_bios_path_values[] __unused = { [ME_NORMAL_BIOS_PATH] = "Normal", [ME_S3WAKE_BIOS_PATH] = "S3 Wake", [ME_ERROR_BIOS_PATH] = "Error", @@ -55,7 +51,6 @@ static const char *me_bios_path_values[] = { [ME_DISABLE_BIOS_PATH] = "Disable", [ME_FIRMWARE_UPDATE_BIOS_PATH] = "Firmware Update", }; -#endif /* MMIO base address for MEI interface */ static u32 *mei_base_address; @@ -112,7 +107,7 @@ static inline void mei_write_dword_ptr(void *ptr, int offset) mei_dump(ptr, dword, offset, "WRITE"); } -#ifndef __SMM__ +#ifndef __SIMPLE_DEVICE__ static inline void pci_read_dword_ptr(struct device *dev, void *ptr, int offset) { u32 dword = pci_read_config32(dev, offset); @@ -346,9 +341,8 @@ static inline int mei_sendrecv(struct mei_header *mei, struct mkhi_header *mkhi, return 0; } -#ifdef __SMM__ /* Send END OF POST message to the ME */ -static int mkhi_end_of_post(void) +static int __unused mkhi_end_of_post(void) { struct mkhi_header mkhi = { .group_id = MKHI_GROUP_ID_GEN, @@ -370,7 +364,6 @@ static int mkhi_end_of_post(void) printk(BIOS_INFO, "ME: END OF POST message successful\n"); return 0; } -#endif /* Get ME firmware version */ static int __unused mkhi_get_fw_version(void) @@ -486,7 +479,8 @@ int mkhi_global_reset(void) } #endif -#ifdef __SMM__ +#ifdef __SIMPLE_DEVICE__ + static void intel_me7_finalize_smm(void) { struct me_hfs hfs; @@ -536,7 +530,8 @@ void intel_me_finalize_smm(void) printk(BIOS_ERR, "No finalize handler for ME %08x.\n", did); } } -#else /* !__SMM__ */ + +#else /* Determine the path that we should take based on ME status */ static me_bios_path intel_me_path(struct device *dev) @@ -748,4 +743,4 @@ static const struct pci_driver intel_me __pci_driver = { .device = 0x1c3a, }; -#endif /* !__SMM__ */ +#endif /* __SIMPLE_DEVICE__ */ diff --git a/src/southbridge/intel/bd82x6x/me_8.x.c b/src/southbridge/intel/bd82x6x/me_8.x.c index 7af969517d..f13ced939a 100644 --- a/src/southbridge/intel/bd82x6x/me_8.x.c +++ b/src/southbridge/intel/bd82x6x/me_8.x.c @@ -24,6 +24,8 @@ #include #include +#include +#include #include #include #include @@ -33,11 +35,6 @@ #include #include -#ifndef __SMM__ -#include -#include -#endif - #include "me.h" #include "pch.h" @@ -46,9 +43,8 @@ #include #endif -#ifndef __SMM__ /* Path that the BIOS should take based on ME state */ -static const char *me_bios_path_values[] = { +static const char *me_bios_path_values[] __unused = { [ME_NORMAL_BIOS_PATH] = "Normal", [ME_S3WAKE_BIOS_PATH] = "S3 Wake", [ME_ERROR_BIOS_PATH] = "Error", @@ -57,7 +53,6 @@ static const char *me_bios_path_values[] = { [ME_FIRMWARE_UPDATE_BIOS_PATH] = "Firmware Update", }; static int intel_me_read_mbp(me_bios_payload *mbp_data); -#endif /* MMIO base address for MEI interface */ static u32 *mei_base_address; @@ -115,7 +110,7 @@ static inline void mei_write_dword_ptr(void *ptr, int offset) mei_dump(ptr, dword, offset, "WRITE"); } -#ifndef __SMM__ +#ifndef __SIMPLE_DEVICE__ static inline void pci_read_dword_ptr(struct device *dev, void *ptr, int offset) { u32 dword = pci_read_config32(dev, offset); @@ -453,10 +448,8 @@ static int mkhi_global_reset(void) } #endif -#ifdef __SMM__ - /* Send END OF POST message to the ME */ -static int mkhi_end_of_post(void) +static int __unused mkhi_end_of_post(void) { struct mkhi_header mkhi = { .group_id = MKHI_GROUP_ID_GEN, @@ -482,6 +475,8 @@ static int mkhi_end_of_post(void) return 0; } +#ifdef __SIMPLE_DEVICE__ + void intel_me8_finalize_smm(void) { struct me_hfs hfs; @@ -517,7 +512,7 @@ void intel_me8_finalize_smm(void) RCBA32_OR(FD2, PCH_DISABLE_MEI1); } -#else /* !__SMM__ */ +#else /* !__SIMPLE_DEVICE__ */ /* Determine the path that we should take based on ME status */ static me_bios_path intel_me_path(struct device *dev) @@ -752,6 +747,8 @@ static const struct pci_driver intel_me __pci_driver = { .device = 0x1e3a, }; +#endif /* !__SIMPLE_DEVICE__ */ + /****************************************************************************** * */ static u32 me_to_host_words_pending(void) @@ -783,7 +780,7 @@ static u32 host_to_me_words_room(void) * mbp seems to be following its own flow, let's retrieve it in a dedicated * function. */ -static int intel_me_read_mbp(me_bios_payload *mbp_data) +static int __unused intel_me_read_mbp(me_bios_payload *mbp_data) { mbp_header mbp_hdr; mbp_item_header mbp_item_hdr; @@ -907,5 +904,3 @@ static int intel_me_read_mbp(me_bios_payload *mbp_data) return 0; } - -#endif /* !__SMM__ */ diff --git a/src/southbridge/intel/bd82x6x/pch.c b/src/southbridge/intel/bd82x6x/pch.c index de7fc36ef6..3cd39a6706 100644 --- a/src/southbridge/intel/bd82x6x/pch.c +++ b/src/southbridge/intel/bd82x6x/pch.c @@ -17,12 +17,9 @@ #include #include -#ifdef __SMM__ -#include -#else /* !__SMM__ */ #include #include -#endif +#include #include #include @@ -145,7 +142,7 @@ void pch_iobp_update(u32 address, u32 andvalue, u32 orvalue) return; } -#ifndef __SMM__ +#ifndef __SIMPLE_DEVICE__ /* Set bit in function disable register to hide this device */ static void pch_hide_devfn(unsigned int devfn) { diff --git a/src/southbridge/intel/common/gpio.c b/src/southbridge/intel/common/gpio.c index 0669b5fcca..9731d75086 100644 --- a/src/southbridge/intel/common/gpio.c +++ b/src/southbridge/intel/common/gpio.c @@ -35,7 +35,7 @@ static u16 get_gpio_base(void) { -#if defined(__SMM__) +#ifdef __SIMPLE_DEVICE__ /* Don't assume GPIO_BASE is still the same */ return pci_read_config16(PCH_LPC_DEV, GPIO_BASE) & 0xfffe; #else diff --git a/src/southbridge/intel/common/pmbase.c b/src/southbridge/intel/common/pmbase.c index ae13272026..ff0410adba 100644 --- a/src/southbridge/intel/common/pmbase.c +++ b/src/southbridge/intel/common/pmbase.c @@ -38,7 +38,7 @@ u16 lpc_get_pmbase(void) { -#if defined(__SMM__) +#ifdef __SIMPLE_DEVICE__ /* Don't assume PMBASE is still the same */ return pci_read_config16(PCH_LPC_DEV, PMBASE) & 0xfffc; #else diff --git a/src/southbridge/intel/ibexpeak/me.c b/src/southbridge/intel/ibexpeak/me.c index 6aa33cad90..63dff6ace8 100644 --- a/src/southbridge/intel/ibexpeak/me.c +++ b/src/southbridge/intel/ibexpeak/me.c @@ -23,20 +23,17 @@ */ #include -#include -#include #include -#include +#include +#include +#include #include +#include +#include #include #include #include -#ifndef __SMM__ -#include -#include -#endif - #include "me.h" #include "pch.h" @@ -44,9 +41,8 @@ #include #endif -#ifndef __SMM__ /* Path that the BIOS should take based on ME state */ -static const char *me_bios_path_values[] = { +static const char *me_bios_path_values[] __unused = { [ME_NORMAL_BIOS_PATH] = "Normal", [ME_S3WAKE_BIOS_PATH] = "S3 Wake", [ME_ERROR_BIOS_PATH] = "Error", @@ -54,7 +50,6 @@ static const char *me_bios_path_values[] = { [ME_DISABLE_BIOS_PATH] = "Disable", [ME_FIRMWARE_UPDATE_BIOS_PATH] = "Firmware Update", }; -#endif /* MMIO base address for MEI interface */ static u32 *mei_base_address; @@ -111,7 +106,7 @@ static inline void mei_write_dword_ptr(void *ptr, int offset) mei_dump(ptr, dword, offset, "WRITE"); } -#ifndef __SMM__ +#ifndef __SIMPLE_DEVICE__ static inline void pci_read_dword_ptr(struct device *dev,void *ptr, int offset) { @@ -131,7 +126,6 @@ static inline void write_host_csr(struct mei_csr *csr) mei_write_dword_ptr(csr, MEI_H_CSR); } -#ifdef __SMM__ static inline void read_me_csr(struct mei_csr *csr) { mei_read_dword_ptr(csr, MEI_ME_CSR_HA); @@ -348,7 +342,7 @@ static inline int mei_sendrecv(struct mei_header *mei, struct mkhi_header *mkhi, } /* Send END OF POST message to the ME */ -static int mkhi_end_of_post(void) +static int __unused mkhi_end_of_post(void) { struct mkhi_header mkhi = { .group_id = MKHI_GROUP_ID_GEN, @@ -371,6 +365,8 @@ static int mkhi_end_of_post(void) return 0; } +#ifdef __SIMPLE_DEVICE__ + static void intel_me7_finalize_smm(void) { struct me_hfs hfs; @@ -420,7 +416,7 @@ void intel_me_finalize_smm(void) printk(BIOS_ERR, "No finalize handler for ME %08x.\n", did); } } -#else /* !__SMM__ */ +#else /* !__SIMPLE_DEVICE__ */ /* Determine the path that we should take based on ME status */ static me_bios_path intel_me_path(struct device *dev) @@ -629,4 +625,4 @@ static const struct pci_driver intel_me __pci_driver = { .devices = pci_device_ids }; -#endif /* !__SMM__ */ +#endif /* !__SIMPLE_DEVICE__ */ diff --git a/src/southbridge/intel/lynxpoint/me_9.x.c b/src/southbridge/intel/lynxpoint/me_9.x.c index 429fa42ab1..2df03c9cdc 100644 --- a/src/southbridge/intel/lynxpoint/me_9.x.c +++ b/src/southbridge/intel/lynxpoint/me_9.x.c @@ -45,9 +45,8 @@ #include #endif -#ifndef __SMM__ /* Path that the BIOS should take based on ME state */ -static const char *me_bios_path_values[] = { +static const char *me_bios_path_values[] __unused = { [ME_NORMAL_BIOS_PATH] = "Normal", [ME_S3WAKE_BIOS_PATH] = "S3 Wake", [ME_ERROR_BIOS_PATH] = "Error", @@ -56,7 +55,6 @@ static const char *me_bios_path_values[] = { [ME_FIRMWARE_UPDATE_BIOS_PATH] = "Firmware Update", }; static int intel_me_read_mbp(me_bios_payload *mbp_data, struct device *dev); -#endif /* MMIO base address for MEI interface */ static u32 *mei_base_address; @@ -557,10 +555,8 @@ static int mkhi_global_reset(void) } #endif -#ifdef __SMM__ - /* Send END OF POST message to the ME */ -static int mkhi_end_of_post(void) +static int __unused mkhi_end_of_post(void) { struct mkhi_header mkhi = { .group_id = MKHI_GROUP_ID_GEN, @@ -579,6 +575,8 @@ static int mkhi_end_of_post(void) return 0; } +#ifdef __SIMPLE_DEVICE__ + void intel_me_finalize_smm(void) { struct me_hfs hfs; @@ -619,7 +617,7 @@ void intel_me_finalize_smm(void) RCBA32_OR(FD2, PCH_DISABLE_MEI1); } -#else /* !__SMM__ */ +#else /* !__SIMPLE_DEVICE__ */ static inline int mei_sendrecv_icc(struct icc_header *icc, void *req_data, int req_bytes, @@ -901,6 +899,8 @@ static const struct pci_driver intel_me __pci_driver = { .devices= pci_device_ids, }; +#endif /* !__SIMPLE_DEVICE__ */ + /****************************************************************************** * */ static u32 me_to_host_words_pending(void) @@ -938,7 +938,7 @@ struct mbp_payload { * mbp seems to be following its own flow, let's retrieve it in a dedicated * function. */ -static int intel_me_read_mbp(me_bios_payload *mbp_data, struct device *dev) +static int __unused intel_me_read_mbp(me_bios_payload *mbp_data, struct device *dev) { mbp_header mbp_hdr; u32 me2host_pending; @@ -947,7 +947,11 @@ static int intel_me_read_mbp(me_bios_payload *mbp_data, struct device *dev) struct mbp_payload *mbp; int i; +#ifdef __SIMPLE_DEVICE__ + pci_read_dword_ptr(PCI_BDF(dev), &hfs2, PCI_ME_HFS2); +#else pci_read_dword_ptr(dev, &hfs2, PCI_ME_HFS2); +#endif if (!hfs2.mbp_rdy) { printk(BIOS_ERR, "ME: MBP not ready\n"); @@ -1057,8 +1061,10 @@ static int intel_me_read_mbp(me_bios_payload *mbp_data, struct device *dev) return 0; mbp_failure: +#ifdef __SIMPLE_DEVICE__ + intel_me_mbp_give_up(PCI_BDF(dev)); +#else intel_me_mbp_give_up(dev); +#endif return -1; } - -#endif /* !__SMM__ */ diff --git a/src/southbridge/intel/lynxpoint/pch.c b/src/southbridge/intel/lynxpoint/pch.c index dc7b9580d9..cb50c125ec 100644 --- a/src/southbridge/intel/lynxpoint/pch.c +++ b/src/southbridge/intel/lynxpoint/pch.c @@ -90,7 +90,7 @@ u16 get_gpiobase(void) return gpiobase; } -#ifndef __SMM__ +#ifndef __SIMPLE_DEVICE__ /* Put device in D3Hot Power State */ static void pch_enable_d3hot(struct device *dev) @@ -330,4 +330,4 @@ struct chip_operations southbridge_intel_lynxpoint_ops = { .enable_dev = pch_enable, }; -#endif /* __SMM__ */ +#endif /* __SIMPLE_DEVICE__ */ diff --git a/src/southbridge/intel/lynxpoint/usb_ehci.c b/src/southbridge/intel/lynxpoint/usb_ehci.c index bc86053eca..3e50beeb09 100644 --- a/src/southbridge/intel/lynxpoint/usb_ehci.c +++ b/src/southbridge/intel/lynxpoint/usb_ehci.c @@ -24,7 +24,7 @@ #include #include "pch.h" -#ifdef __SMM__ +#ifdef __SIMPLE_DEVICE__ void usb_ehci_disable(pci_devfn_t dev) { @@ -132,7 +132,7 @@ void usb_ehci_sleep_prepare(pci_devfn_t dev, u8 slp_typ) } } -#else /* !__SMM__ */ +#else /* !__SIMPLE_DEVICE__ */ static void usb_ehci_clock_gating(struct device *dev) { @@ -202,4 +202,4 @@ static const struct pci_driver pch_usb_ehci __pci_driver = { .devices = pci_device_ids, }; -#endif /* !__SMM__ */ +#endif /* !__SIMPLE_DEVICE__ */ diff --git a/src/southbridge/intel/lynxpoint/usb_xhci.c b/src/southbridge/intel/lynxpoint/usb_xhci.c index 686e06a6a9..4818d626f0 100644 --- a/src/southbridge/intel/lynxpoint/usb_xhci.c +++ b/src/southbridge/intel/lynxpoint/usb_xhci.c @@ -166,7 +166,7 @@ static void usb_xhci_reset_usb3(struct device *dev, int all) usb_xhci_reset_status_usb3(mem_base, port); } -#ifdef __SMM__ +#ifdef __SIMPLE_DEVICE__ /* Handler for XHCI controller on entry to S3/S4/S5 */ void usb_xhci_sleep_prepare(pci_devfn_t dev, u8 slp_typ) @@ -251,7 +251,7 @@ void usb_xhci_route_all(void) usb_xhci_reset_usb3(PCH_XHCI_DEV, 1); } -#else /* !__SMM__ */ +#else /* !__SIMPLE_DEVICE__ */ static void usb_xhci_clock_gating(struct device *dev) { @@ -395,4 +395,4 @@ static const struct pci_driver pch_usb_xhci __pci_driver = { .vendor = PCI_VENDOR_ID_INTEL, .devices = pci_device_ids, }; -#endif /* !__SMM__ */ +#endif /* !__SIMPLE_DEVICE__ */ From 7f22933e98ec70b31b939b2ab70d6b8715640848 Mon Sep 17 00:00:00 2001 From: Arthur Heymans Date: Fri, 8 Nov 2019 11:59:25 +0100 Subject: [PATCH 0071/1242] Kconfig: Remove untrue comment In the vast majority of cases the bootdevice is the bottleneck and compression increases bootspeed. Change-Id: Id0c11cf6d9a605d24e3148abb8d11a65d48a4529 Signed-off-by: Arthur Heymans Reviewed-on: https://review.coreboot.org/c/coreboot/+/36675 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin Reviewed-by: Nico Huber --- src/Kconfig | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) diff --git a/src/Kconfig b/src/Kconfig index 4002d43cee..56ebe82e02 100644 --- a/src/Kconfig +++ b/src/Kconfig @@ -154,9 +154,7 @@ config COMPRESS_RAMSTAGE depends on HAVE_RAMSTAGE # Default value set at the end of the file help - Compress ramstage to save memory in the flash image. Note - that decompression might slow down booting if the boot flash - is connected through a slow link (i.e. SPI). + Compress ramstage to save memory in the flash image. config COMPRESS_PRERAM_STAGES bool "Compress romstage and verstage with LZ4" From 55069d15d8a6dcd7f8eaaf36e85e5d7a53fdaae6 Mon Sep 17 00:00:00 2001 From: Arthur Heymans Date: Fri, 1 Nov 2019 21:53:36 +0100 Subject: [PATCH 0072/1242] arch/riscv: Pass cbmem_top to ramstage via calling argument Tested on the Qemu-Virt target both 32 and 64 bit. Change-Id: I5c74cd5d3ee292931c5bbd2e4075f88381429f72 Signed-off-by: Arthur Heymans Reviewed-on: https://review.coreboot.org/c/coreboot/+/36558 Reviewed-by: Nico Huber Tested-by: build bot (Jenkins) --- Documentation/arch/riscv/index.md | 3 +++ src/arch/riscv/Kconfig | 1 + src/arch/riscv/boot.c | 9 +++------ src/arch/riscv/ramstage.S | 7 +++++++ 4 files changed, 14 insertions(+), 6 deletions(-) diff --git a/Documentation/arch/riscv/index.md b/Documentation/arch/riscv/index.md index ea6a5cd47e..e0d37f591c 100644 --- a/Documentation/arch/riscv/index.md +++ b/Documentation/arch/riscv/index.md @@ -19,6 +19,9 @@ On entry to a stage or payload (including SELF payloads), * all harts are running. * A0 is the hart ID. * A1 is the pointer to the Flattened Device Tree (FDT). +* A2 contains the additional program calling argument: + - cbmem_top for ramstage + - the address of the payload for opensbi ## Additional payload handoff requirements The location of cbmem should be placed in a node in the FDT. diff --git a/src/arch/riscv/Kconfig b/src/arch/riscv/Kconfig index f2ca571c97..9ee781b4f0 100644 --- a/src/arch/riscv/Kconfig +++ b/src/arch/riscv/Kconfig @@ -90,6 +90,7 @@ config ARCH_ROMSTAGE_RISCV config ARCH_RAMSTAGE_RISCV bool default n + select RAMSTAGE_CBMEM_TOP_ARG config RISCV_USE_ARCH_TIMER bool diff --git a/src/arch/riscv/boot.c b/src/arch/riscv/boot.c index d3ae693376..aaaac485ea 100644 --- a/src/arch/riscv/boot.c +++ b/src/arch/riscv/boot.c @@ -36,7 +36,7 @@ struct arch_prog_run_args { static void do_arch_prog_run(struct arch_prog_run_args *args) { - int hart_id; + int hart_id = HLS()->hart_id; struct prog *prog = args->prog; void *fdt = HLS()->fdt; @@ -49,11 +49,8 @@ static void do_arch_prog_run(struct arch_prog_run_args *args) else run_payload(prog, fdt, RISCV_PAYLOAD_MODE_S); } else { - void (*doit)(int hart_id, void *fdt) = prog_entry(prog); - - hart_id = HLS()->hart_id; - - doit(hart_id, fdt); + void (*doit)(int hart_id, void *fdt, void *arg) = prog_entry(prog); + doit(hart_id, fdt, prog_entry_arg(prog)); } die("Failed to run stage"); diff --git a/src/arch/riscv/ramstage.S b/src/arch/riscv/ramstage.S index 28183e50e0..2468c231bc 100644 --- a/src/arch/riscv/ramstage.S +++ b/src/arch/riscv/ramstage.S @@ -20,6 +20,13 @@ .section ".text._start", "ax", %progbits .globl _start _start: + /* cbmem_top is passed via a2 */ + la t0, _cbmem_top_ptr +#if __riscv_xlen == 32 + sw a2, (t0) +#elif __riscv_xlen == 64 + sd a2, (t0) +#endif # initialize stack point for each hart # and the stack must be page-aligned. # 0xDEADBEEF used to check stack overflow From c4c5d85c220b6bd594c1c32f0aa74117c3b68a09 Mon Sep 17 00:00:00 2001 From: Arthur Heymans Date: Tue, 29 Oct 2019 07:32:48 +0100 Subject: [PATCH 0073/1242] lib/Kconfig: Remove RAMSTAGE_CBMEM_TOP_ARG MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit All targets now have the _cbmem_top_ptr symbol populated via calling arguments or in the nvidia/tegra210 case worked around by populating it with cbmem_top_chipset explicitly at the start of ramstage, so the Kconfig guarding this behavior can be removed. Change-Id: Ie7467629e58700e4d29f6e735840c22ed687f880 Signed-off-by: Arthur Heymans Reviewed-on: https://review.coreboot.org/c/coreboot/+/36422 Reviewed-by: Nico Huber Reviewed-by: Michael Niewöhner Reviewed-by: Aaron Durbin Tested-by: build bot (Jenkins) --- src/arch/arm/Kconfig | 1 - src/arch/arm64/Kconfig | 1 - src/arch/mips/Kconfig | 1 - src/arch/ppc64/Kconfig | 1 - src/arch/riscv/Kconfig | 1 - src/arch/x86/Kconfig | 1 - src/lib/Kconfig | 6 ------ src/lib/imd_cbmem.c | 6 ++---- 8 files changed, 2 insertions(+), 16 deletions(-) diff --git a/src/arch/arm/Kconfig b/src/arch/arm/Kconfig index 9e10378510..47c333bf6a 100644 --- a/src/arch/arm/Kconfig +++ b/src/arch/arm/Kconfig @@ -17,7 +17,6 @@ config ARCH_ROMSTAGE_ARM config ARCH_RAMSTAGE_ARM bool select ARCH_ARM - select RAMSTAGE_CBMEM_TOP_ARG source src/arch/arm/armv4/Kconfig source src/arch/arm/armv7/Kconfig diff --git a/src/arch/arm64/Kconfig b/src/arch/arm64/Kconfig index c7eafe649a..3d1d1843e0 100644 --- a/src/arch/arm64/Kconfig +++ b/src/arch/arm64/Kconfig @@ -17,7 +17,6 @@ config ARCH_ROMSTAGE_ARM64 config ARCH_RAMSTAGE_ARM64 bool select ARCH_ARM64 - select RAMSTAGE_CBMEM_TOP_ARG source src/arch/arm64/armv8/Kconfig diff --git a/src/arch/mips/Kconfig b/src/arch/mips/Kconfig index 321bfc91fd..9df514b21b 100644 --- a/src/arch/mips/Kconfig +++ b/src/arch/mips/Kconfig @@ -22,7 +22,6 @@ config ARCH_BOOTBLOCK_MIPS default n select BOOTBLOCK_CUSTOM select C_ENVIRONMENT_BOOTBLOCK - select RAMSTAGE_CBMEM_TOP_ARG config ARCH_VERSTAGE_MIPS bool diff --git a/src/arch/ppc64/Kconfig b/src/arch/ppc64/Kconfig index da9c155917..0699e910ce 100644 --- a/src/arch/ppc64/Kconfig +++ b/src/arch/ppc64/Kconfig @@ -1,6 +1,5 @@ config ARCH_PPC64 bool - select RAMSTAGE_CBMEM_TOP_ARG config ARCH_BOOTBLOCK_PPC64 bool diff --git a/src/arch/riscv/Kconfig b/src/arch/riscv/Kconfig index 9ee781b4f0..f2ca571c97 100644 --- a/src/arch/riscv/Kconfig +++ b/src/arch/riscv/Kconfig @@ -90,7 +90,6 @@ config ARCH_ROMSTAGE_RISCV config ARCH_RAMSTAGE_RISCV bool default n - select RAMSTAGE_CBMEM_TOP_ARG config RISCV_USE_ARCH_TIMER bool diff --git a/src/arch/x86/Kconfig b/src/arch/x86/Kconfig index 37b7d2daaa..c5a5642974 100644 --- a/src/arch/x86/Kconfig +++ b/src/arch/x86/Kconfig @@ -16,7 +16,6 @@ config ARCH_X86 default n select PCI select RELOCATABLE_MODULES - select RAMSTAGE_CBMEM_TOP_ARG # stage selectors for x86 diff --git a/src/lib/Kconfig b/src/lib/Kconfig index b94ac495b7..cb1e4a5cc8 100644 --- a/src/lib/Kconfig +++ b/src/lib/Kconfig @@ -24,12 +24,6 @@ config RAMSTAGE_LIBHWBASE help Selected by features that require `libhwbase` in ramstage. -config RAMSTAGE_CBMEM_TOP_ARG - bool - help - Select this if stages run after romstage get the cbmem_top - pointer as the function arguments when called from romstage. - config FLATTENED_DEVICE_TREE bool help diff --git a/src/lib/imd_cbmem.c b/src/lib/imd_cbmem.c index cbd4b8f887..38620d2d06 100644 --- a/src/lib/imd_cbmem.c +++ b/src/lib/imd_cbmem.c @@ -51,16 +51,14 @@ uintptr_t _cbmem_top_ptr; void *cbmem_top(void) { - if (ENV_ROMSTAGE - || ((ENV_POSTCAR || ENV_RAMSTAGE) - && !CONFIG(RAMSTAGE_CBMEM_TOP_ARG))) { + if (ENV_ROMSTAGE) { MAYBE_STATIC_BSS void *top = NULL; if (top) return top; top = cbmem_top_chipset(); return top; } - if ((ENV_POSTCAR || ENV_RAMSTAGE) && CONFIG(RAMSTAGE_CBMEM_TOP_ARG)) + if (ENV_POSTCAR || ENV_RAMSTAGE) return (void *)_cbmem_top_ptr; dead_code(); From cf5af24a94b614bbc3f3fb531eb5cccf2d8e00c6 Mon Sep 17 00:00:00 2001 From: Arthur Heymans Date: Mon, 4 Nov 2019 21:24:28 +0100 Subject: [PATCH 0074/1242] soc/intel/common/sa: Remove EBDA dependency MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Saving cbmem_top across stages is not needed anymore so EBDA should not be used. The guard to cbmem_top_chipset implementation was inappropriate. Change-Id: Ibbb3534b88de4f7b6fc39675a77461265605e56e Signed-off-by: Arthur Heymans Reviewed-on: https://review.coreboot.org/c/coreboot/+/36614 Tested-by: build bot (Jenkins) Reviewed-by: Michael Niewöhner --- src/soc/intel/cannonlake/Kconfig | 2 +- .../intel/common/block/systemagent/Kconfig | 6 +++++ .../common/block/systemagent/Makefile.inc | 1 + .../intel/common/block/systemagent/cbmem.c | 23 ++++++++++++++++ .../intel/common/block/systemagent/memmap.c | 27 ------------------- src/soc/intel/icelake/Kconfig | 2 +- src/soc/intel/skylake/Kconfig | 2 +- 7 files changed, 33 insertions(+), 30 deletions(-) create mode 100644 src/soc/intel/common/block/systemagent/cbmem.c diff --git a/src/soc/intel/cannonlake/Kconfig b/src/soc/intel/cannonlake/Kconfig index 3330a69081..70d2d9ab6e 100644 --- a/src/soc/intel/cannonlake/Kconfig +++ b/src/soc/intel/cannonlake/Kconfig @@ -88,7 +88,7 @@ config CPU_SPECIFIC_OPTIONS select SOC_INTEL_COMMON_BLOCK_CHIP_CONFIG select SOC_INTEL_COMMON_BLOCK_CPU select SOC_INTEL_COMMON_BLOCK_CPU_MPINIT - select SOC_INTEL_COMMON_BLOCK_EBDA + select SOC_INTEL_COMMON_BLOCK_SA_FSP_TOLUM select SOC_INTEL_COMMON_BLOCK_GPIO_DUAL_ROUTE_SUPPORT select SOC_INTEL_COMMON_BLOCK_GSPI_VERSION_2 select SOC_INTEL_COMMON_BLOCK_HDA diff --git a/src/soc/intel/common/block/systemagent/Kconfig b/src/soc/intel/common/block/systemagent/Kconfig index 1222573201..4c50d50c64 100644 --- a/src/soc/intel/common/block/systemagent/Kconfig +++ b/src/soc/intel/common/block/systemagent/Kconfig @@ -3,6 +3,12 @@ config SOC_INTEL_COMMON_BLOCK_SA help Intel Processor common System Agent support +config SOC_INTEL_COMMON_BLOCK_SA_FSP_TOLUM + bool + help + Select this if you want cbmem_top_chipset use the TOLUM returned + by the FSP HOB. + config MMCONF_BASE_ADDRESS hex default 0xe0000000 diff --git a/src/soc/intel/common/block/systemagent/Makefile.inc b/src/soc/intel/common/block/systemagent/Makefile.inc index 7e49ec7291..1cced4a0d1 100644 --- a/src/soc/intel/common/block/systemagent/Makefile.inc +++ b/src/soc/intel/common/block/systemagent/Makefile.inc @@ -6,3 +6,4 @@ ramstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_SA) += systemagent.c romstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_SA) += memmap.c ramstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_SA) += memmap.c postcar-$(CONFIG_SOC_INTEL_COMMON_BLOCK_SA) += memmap.c +romstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_SA_FSP_TOLUM) += cbmem.c diff --git a/src/soc/intel/common/block/systemagent/cbmem.c b/src/soc/intel/common/block/systemagent/cbmem.c new file mode 100644 index 0000000000..7e743dfcdd --- /dev/null +++ b/src/soc/intel/common/block/systemagent/cbmem.c @@ -0,0 +1,23 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include + +void *cbmem_top_chipset(void) +{ + struct range_entry tolum; + + fsp_find_bootloader_tolum(&tolum); + return (void *)(uintptr_t)range_entry_end(&tolum); +} diff --git a/src/soc/intel/common/block/systemagent/memmap.c b/src/soc/intel/common/block/systemagent/memmap.c index 809c13a1ff..2b0fdc4e14 100644 --- a/src/soc/intel/common/block/systemagent/memmap.c +++ b/src/soc/intel/common/block/systemagent/memmap.c @@ -19,8 +19,6 @@ #include #include #include -#include -#include #include #include @@ -70,31 +68,6 @@ void smm_region(uintptr_t *start, size_t *size) *size = sa_get_tseg_size(); } -#if CONFIG(SOC_INTEL_COMMON_BLOCK_EBDA) -void fill_memmap_ebda(struct ebda_config *cfg) -{ - struct range_entry tolum; - - fsp_find_bootloader_tolum(&tolum); - cfg->cbmem_top = range_entry_end(&tolum); -} - -void cbmem_top_init(void) -{ - /* Initialize EBDA area */ - initialize_ebda_area(); -} - -void *cbmem_top_chipset(void) -{ - struct ebda_config ebda_cfg; - - retrieve_ebda_object(&ebda_cfg); - - return (void *)(uintptr_t)ebda_cfg.cbmem_top; -} -#endif - void fill_postcar_frame(struct postcar_frame *pcf) { uintptr_t top_of_ram; diff --git a/src/soc/intel/icelake/Kconfig b/src/soc/intel/icelake/Kconfig index 71c7f8355c..0404af5c98 100644 --- a/src/soc/intel/icelake/Kconfig +++ b/src/soc/intel/icelake/Kconfig @@ -43,7 +43,7 @@ config CPU_SPECIFIC_OPTIONS select SOC_INTEL_COMMON_BLOCK_CHIP_CONFIG select SOC_INTEL_COMMON_BLOCK_CPU select SOC_INTEL_COMMON_BLOCK_CPU_MPINIT - select SOC_INTEL_COMMON_BLOCK_EBDA + select SOC_INTEL_COMMON_BLOCK_SA_FSP_TOLUM select SOC_INTEL_COMMON_BLOCK_GSPI_VERSION_2 select SOC_INTEL_COMMON_BLOCK_HDA select SOC_INTEL_COMMON_BLOCK_SA diff --git a/src/soc/intel/skylake/Kconfig b/src/soc/intel/skylake/Kconfig index d4720a21be..292963a66b 100644 --- a/src/soc/intel/skylake/Kconfig +++ b/src/soc/intel/skylake/Kconfig @@ -58,7 +58,7 @@ config CPU_SPECIFIC_OPTIONS select SOC_INTEL_COMMON_BLOCK_CHIP_CONFIG select SOC_INTEL_COMMON_BLOCK_CPU select SOC_INTEL_COMMON_BLOCK_CPU_MPINIT - select SOC_INTEL_COMMON_BLOCK_EBDA + select SOC_INTEL_COMMON_BLOCK_SA_FSP_TOLUM select SOC_INTEL_COMMON_BLOCK_GPIO_DUAL_ROUTE_SUPPORT select SOC_INTEL_COMMON_BLOCK_GPIO_LEGACY_MACROS select SOC_INTEL_COMMON_BLOCK_GPIO_PADCFG_PADTOL From 005e25de0fe79d3aa72062279b9642d21cc9916c Mon Sep 17 00:00:00 2001 From: Arthur Heymans Date: Sat, 26 Oct 2019 19:28:45 +0200 Subject: [PATCH 0075/1242] soc/intel/common/ebda: Drop code MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit There is no need to use EBDA to pass cbmem_top from romstage to later stages. Change-Id: I46e2459ff3c785f530cabc5930004ef920ffc89a Signed-off-by: Arthur Heymans Reviewed-on: https://review.coreboot.org/c/coreboot/+/36362 Tested-by: build bot (Jenkins) Reviewed-by: Michael Niewöhner Reviewed-by: Nico Huber --- src/soc/intel/cannonlake/include/soc/ebda.h | 26 ------------- src/soc/intel/common/block/ebda/Kconfig | 5 --- src/soc/intel/common/block/ebda/Makefile.inc | 3 -- src/soc/intel/common/block/ebda/ebda.c | 37 ------------------ .../common/block/include/intelblocks/ebda.h | 38 ------------------- src/soc/intel/icelake/include/soc/ebda.h | 26 ------------- src/soc/intel/skylake/include/soc/ebda.h | 26 ------------- 7 files changed, 161 deletions(-) delete mode 100644 src/soc/intel/cannonlake/include/soc/ebda.h delete mode 100644 src/soc/intel/common/block/ebda/Kconfig delete mode 100644 src/soc/intel/common/block/ebda/Makefile.inc delete mode 100644 src/soc/intel/common/block/ebda/ebda.c delete mode 100644 src/soc/intel/common/block/include/intelblocks/ebda.h delete mode 100644 src/soc/intel/icelake/include/soc/ebda.h delete mode 100644 src/soc/intel/skylake/include/soc/ebda.h diff --git a/src/soc/intel/cannonlake/include/soc/ebda.h b/src/soc/intel/cannonlake/include/soc/ebda.h deleted file mode 100644 index 4ed6566838..0000000000 --- a/src/soc/intel/cannonlake/include/soc/ebda.h +++ /dev/null @@ -1,26 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2017 Intel Corporation. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef SOC_EBDA_H -#define SOC_EBDA_H - -#include - -struct ebda_config { - uint32_t signature; /* EBDA signature */ - uint32_t cbmem_top; /* coreboot memory start */ -}; - -#endif diff --git a/src/soc/intel/common/block/ebda/Kconfig b/src/soc/intel/common/block/ebda/Kconfig deleted file mode 100644 index 67c7b48033..0000000000 --- a/src/soc/intel/common/block/ebda/Kconfig +++ /dev/null @@ -1,5 +0,0 @@ -config SOC_INTEL_COMMON_BLOCK_EBDA - bool - select EARLY_EBDA_INIT - help - Intel Processor common EBDA library support diff --git a/src/soc/intel/common/block/ebda/Makefile.inc b/src/soc/intel/common/block/ebda/Makefile.inc deleted file mode 100644 index beeba5176a..0000000000 --- a/src/soc/intel/common/block/ebda/Makefile.inc +++ /dev/null @@ -1,3 +0,0 @@ -romstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_EBDA) += ebda.c -ramstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_EBDA) += ebda.c -postcar-$(CONFIG_SOC_INTEL_COMMON_BLOCK_EBDA) += ebda.c diff --git a/src/soc/intel/common/block/ebda/ebda.c b/src/soc/intel/common/block/ebda/ebda.c deleted file mode 100644 index 072023cd16..0000000000 --- a/src/soc/intel/common/block/ebda/ebda.c +++ /dev/null @@ -1,37 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2017 Intel Corporation. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include - -void initialize_ebda_area(void) -{ - struct ebda_config ebda_cfg; - - /* Initialize EBDA area early during romstage. */ - setup_default_ebda(); - ebda_cfg.signature = EBDA_SIGNATURE; - fill_memmap_ebda(&ebda_cfg); - write_ebda_data(&ebda_cfg, sizeof(ebda_cfg)); -} - -void retrieve_ebda_object(struct ebda_config *cfg) -{ - read_ebda_data(cfg, sizeof(*cfg)); - - if (cfg->signature != EBDA_SIGNATURE) - memset(cfg, 0, sizeof(*cfg)); -} diff --git a/src/soc/intel/common/block/include/intelblocks/ebda.h b/src/soc/intel/common/block/include/intelblocks/ebda.h deleted file mode 100644 index 48904f4705..0000000000 --- a/src/soc/intel/common/block/include/intelblocks/ebda.h +++ /dev/null @@ -1,38 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2017 Intel Corporation. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef SOC_INTEL_COMMON_BLOCK_EBDA_H -#define SOC_INTEL_COMMON_BLOCK_EBDA_H - -#define EBDA_SIGNATURE 0xebdaebda - -/* EBDA structure */ -struct ebda_config { - uint32_t signature; /* EBDA signature */ - uint32_t cbmem_top; /* coreboot memory start */ -}; - -/* Initialize EBDA and store structure into EBDA area */ -void initialize_ebda_area(void); - -/* - * Fill the ebda object pointed to by cfg. Object will be zero filled - * if signature check fails. */ -void retrieve_ebda_object(struct ebda_config *cfg); - -/* API for filling ebda with data in romstage */ -void fill_memmap_ebda(struct ebda_config *cfg); - -#endif diff --git a/src/soc/intel/icelake/include/soc/ebda.h b/src/soc/intel/icelake/include/soc/ebda.h deleted file mode 100644 index 5cb5cdc004..0000000000 --- a/src/soc/intel/icelake/include/soc/ebda.h +++ /dev/null @@ -1,26 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2018 Intel Corporation. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef SOC_EBDA_H -#define SOC_EBDA_H - -#include - -struct ebda_config { - uint32_t signature; /* EBDA signature */ - uint32_t cbmem_top; /* coreboot memory start */ -}; - -#endif diff --git a/src/soc/intel/skylake/include/soc/ebda.h b/src/soc/intel/skylake/include/soc/ebda.h deleted file mode 100644 index 4ed6566838..0000000000 --- a/src/soc/intel/skylake/include/soc/ebda.h +++ /dev/null @@ -1,26 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2017 Intel Corporation. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef SOC_EBDA_H -#define SOC_EBDA_H - -#include - -struct ebda_config { - uint32_t signature; /* EBDA signature */ - uint32_t cbmem_top; /* coreboot memory start */ -}; - -#endif From 8b7cd43d5d5af1d192b0bbe34e6aff776df90a0f Mon Sep 17 00:00:00 2001 From: Arthur Heymans Date: Sat, 26 Oct 2019 20:31:41 +0200 Subject: [PATCH 0076/1242] arch/x86: Remove EARLY_EBDA_INIT support MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This is unused now. Change-Id: Ie8bc1d6761d66c5e1dda40c34c940cdba90646d2 Signed-off-by: Arthur Heymans Reviewed-on: https://review.coreboot.org/c/coreboot/+/36363 Tested-by: build bot (Jenkins) Reviewed-by: Michael Niewöhner Reviewed-by: Nico Huber Reviewed-by: Aaron Durbin --- src/arch/x86/Kconfig | 9 ------ src/arch/x86/Makefile.inc | 2 -- src/arch/x86/ebda.c | 48 +------------------------------- src/arch/x86/include/arch/ebda.h | 21 -------------- src/arch/x86/tables.c | 37 ------------------------ src/device/device.c | 9 ++---- 6 files changed, 3 insertions(+), 123 deletions(-) diff --git a/src/arch/x86/Kconfig b/src/arch/x86/Kconfig index c5a5642974..24a2065c0e 100644 --- a/src/arch/x86/Kconfig +++ b/src/arch/x86/Kconfig @@ -148,15 +148,6 @@ config PRERAM_CBMEM_CONSOLE_SIZE help Increase this value if preram cbmem console is getting truncated -config EARLY_EBDA_INIT - bool - default n - help - Initialize BIOS EBDA area early in romstage to allow bootloader to - use this region for storing data which can be available across - various stages. If user is selecting this option then its users - responsibility to perform EBDA initialization call during romstage. - config PC80_SYSTEM bool default y if ARCH_X86 diff --git a/src/arch/x86/Makefile.inc b/src/arch/x86/Makefile.inc index c15971ff7b..cc094d111f 100644 --- a/src/arch/x86/Makefile.inc +++ b/src/arch/x86/Makefile.inc @@ -226,7 +226,6 @@ romstage-$(CONFIG_HAVE_ACPI_RESUME) += acpi_s3.c romstage-$(CONFIG_C_ENVIRONMENT_BOOTBLOCK) += gdt_init.S romstage-y += cbmem.c romstage-y += cbfs_and_run.c -romstage-$(CONFIG_EARLY_EBDA_INIT) += ebda.c romstage-$(CONFIG_IDT_IN_EVERY_STAGE) += exception.c romstage-$(CONFIG_IDT_IN_EVERY_STAGE) += idt.S romstage-y += memmove.c @@ -261,7 +260,6 @@ postcar-generic-ccopts += -D__POSTCAR__ postcar-$(CONFIG_HAVE_ACPI_RESUME) += acpi_s3.c postcar-y += gdt_init.S postcar-y += cbfs_and_run.c -postcar-$(CONFIG_EARLY_EBDA_INIT) += ebda.c postcar-$(CONFIG_IDT_IN_EVERY_STAGE) += exception.c postcar-$(CONFIG_IDT_IN_EVERY_STAGE) += idt.S postcar-y += exit_car.S diff --git a/src/arch/x86/ebda.c b/src/arch/x86/ebda.c index d1212f9d32..f2727bb8fe 100644 --- a/src/arch/x86/ebda.c +++ b/src/arch/x86/ebda.c @@ -24,58 +24,12 @@ static void *get_ebda_start(void) return (void *)((uintptr_t)DEFAULT_EBDA_SEGMENT << 4); } -static bool is_length_valid(size_t dlength) -{ - /* Check if input data length is > DEFAULT_EBDA_SIZE */ - if (dlength > DEFAULT_EBDA_SIZE) - return false; - - /* Valid data length */ - return true; -} - /* * EBDA area is representing a 1KB memory area just below * the top of conventional memory (below 1MB) */ -/* - * write_ebda_data is a wrapper function to write into EBDA area - * - * data = data to be written into EBDA area - * length = input data size. - */ -void write_ebda_data(const void *data, size_t length) -{ - void *ebda; - - if (!is_length_valid(length)) - die("Input data length is > EBDA default size (1KiB)!"); - - ebda = get_ebda_start(); - - memcpy(ebda, data, length); -} - -/* - * read_ebda_data is a wrapper function to read from EBDA area - * - * data = data read from EBDA area based on input size - * length = read data size. - */ -void read_ebda_data(void *data, size_t length) -{ - void *ebda; - - if (!is_length_valid(length)) - die("Input data length is > EBDA default size (1KiB)!"); - - ebda = get_ebda_start(); - - memcpy(data, ebda, length); -} - -void setup_ebda(u32 low_memory_size, u16 ebda_segment, u16 ebda_size) +static void setup_ebda(u32 low_memory_size, u16 ebda_segment, u16 ebda_size) { u16 low_memory_kb; u16 ebda_kb; diff --git a/src/arch/x86/include/arch/ebda.h b/src/arch/x86/include/arch/ebda.h index 534fb3d590..6ee3332540 100644 --- a/src/arch/x86/include/arch/ebda.h +++ b/src/arch/x86/include/arch/ebda.h @@ -27,27 +27,6 @@ #define DEFAULT_EBDA_SEGMENT 0xF600 #define DEFAULT_EBDA_SIZE 0x400 -void setup_ebda(u32 low_memory_size, u16 ebda_segment, u16 ebda_size); void setup_default_ebda(void); -/* - * This read/write API only allows and assumes - * a single EBDA structure type for a platform. - */ - -/* - * write_ebda_data is a wrapper function to write into EBDA area - * - * data = data to be written into EBDA area - * length = input data size. - */ -void write_ebda_data(const void *data, size_t length); -/* - * read_ebda_data is a wrapper function to read from EBDA area - * - * data = data read from EBDA area based on input size - * length = read data size. - */ -void read_ebda_data(void *data, size_t length); - #endif diff --git a/src/arch/x86/tables.c b/src/arch/x86/tables.c index ddb0710c8a..8ecf86dc3f 100644 --- a/src/arch/x86/tables.c +++ b/src/arch/x86/tables.c @@ -194,41 +194,6 @@ static unsigned long write_smbios_table(unsigned long rom_table_end) #define FORWARDING_TABLE_ADDR ((uintptr_t)0x500) static uintptr_t forwarding_table = FORWARDING_TABLE_ADDR; -/* - * For EARLY_EBDA_INIT the BDA area will be wiped on the resume path which - * has the forwarding table entry. Therefore, when tables are written an - * entry is placed in cbmem that can be restored on OS resume to the proper - * location. - */ -static void stash_forwarding_table(uintptr_t addr, size_t sz) -{ - void *cbmem_addr = cbmem_add(CBMEM_ID_CBTABLE_FWD, sz); - - if (cbmem_addr == NULL) { - printk(BIOS_ERR, "Unable to allocate CBMEM forwarding entry.\n"); - return; - } - - memcpy(cbmem_addr, (void *)addr, sz); -} - -static void restore_forwarding_table(void *dest) -{ - const struct cbmem_entry *fwd_entry; - - fwd_entry = cbmem_entry_find(CBMEM_ID_CBTABLE_FWD); - - if (fwd_entry == NULL) { - printk(BIOS_ERR, "Unable to restore CBMEM forwarding entry.\n"); - return; - } - - memcpy(dest, cbmem_entry_start(fwd_entry), cbmem_entry_size(fwd_entry)); -} - -BOOT_STATE_INIT_ENTRY(BS_OS_RESUME, BS_ON_ENTRY, - restore_forwarding_table, (void *)FORWARDING_TABLE_ADDR); - void arch_write_tables(uintptr_t coreboot_table) { size_t sz; @@ -250,8 +215,6 @@ void arch_write_tables(uintptr_t coreboot_table) sz = write_coreboot_forwarding_table(forwarding_table, coreboot_table); - stash_forwarding_table(forwarding_table, sz); - forwarding_table += sz; /* Align up to page boundary for historical consistency. */ forwarding_table = ALIGN_UP(forwarding_table, 4*KiB); diff --git a/src/device/device.c b/src/device/device.c index 333f1f0f1d..5d9938ff0e 100644 --- a/src/device/device.c +++ b/src/device/device.c @@ -1165,13 +1165,8 @@ void dev_initialize(void) printk(BIOS_INFO, "Initializing devices...\n"); #if CONFIG(ARCH_X86) - /* - * Initialize EBDA area in ramstage if early - * initialization is not done. - */ - if (!CONFIG(EARLY_EBDA_INIT)) - /* Ensure EBDA is prepared before Option ROMs. */ - setup_default_ebda(); + /* Ensure EBDA is prepared before Option ROMs. */ + setup_default_ebda(); #endif /* First call the mainboard init. */ From 1c54bc4849a4ab6b78612b47ca0727bd16e8cf92 Mon Sep 17 00:00:00 2001 From: Arthur Heymans Date: Sun, 27 Oct 2019 07:18:41 +0100 Subject: [PATCH 0077/1242] lib/cbmem: Remove the cbmem_top_init() hook MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This hook is unused and with the need for initializing storage to share cbmem_top over other stages gone, there is likely no future need for this. Change-Id: I4ba9daea61b6d7b8949bbd2c4fb71d0a0fa20d93 Signed-off-by: Arthur Heymans Reviewed-on: https://review.coreboot.org/c/coreboot/+/36369 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber Reviewed-by: Michael Niewöhner Reviewed-by: Aaron Durbin --- src/include/cbmem.h | 5 ----- src/lib/imd_cbmem.c | 6 ------ 2 files changed, 11 deletions(-) diff --git a/src/include/cbmem.h b/src/include/cbmem.h index a22c420ad3..cf79f41a71 100644 --- a/src/include/cbmem.h +++ b/src/include/cbmem.h @@ -63,11 +63,6 @@ int cbmem_initialize_id_size(u32 id, u64 size); void cbmem_initialize_empty(void); void cbmem_initialize_empty_id_size(u32 id, u64 size); -/* Optional hook for platforms to initialize cbmem_top() value. When employed - * it's called a single time during boot at cbmem initialization/recovery - * time. */ -void cbmem_top_init(void); - /* Return the top address for dynamic cbmem. The address returned needs to * be consistent across romstage and ramstage, and it is required to be * below 4GiB for 32bit coreboot builds. On 64bit coreboot builds there's no diff --git a/src/lib/imd_cbmem.c b/src/lib/imd_cbmem.c index 38620d2d06..6eb3e6096c 100644 --- a/src/lib/imd_cbmem.c +++ b/src/lib/imd_cbmem.c @@ -130,10 +130,6 @@ void cbmem_initialize_empty(void) cbmem_initialize_empty_id_size(0, 0); } -void __weak cbmem_top_init(void) -{ -} - static void cbmem_top_init_once(void) { /* Call one-time hook on expected cbmem init during boot. This sequence @@ -141,8 +137,6 @@ static void cbmem_top_init_once(void) if (!ENV_ROMSTAGE) return; - cbmem_top_init(); - /* The test is only effective on X86 and when address hits UC memory. */ if (ENV_X86) quick_ram_check_or_die((uintptr_t)cbmem_top() - sizeof(u32)); From 074730c14c48a5cf6fc056371eef08e495bccc8f Mon Sep 17 00:00:00 2001 From: Arthur Heymans Date: Tue, 4 Jun 2019 14:05:53 +0200 Subject: [PATCH 0078/1242] sb/intel/common: Make linking rtc.c conditional Change-Id: I7321da453c0d9bb4a142c3c93103d8dc0ff416b7 Signed-off-by: Arthur Heymans Reviewed-on: https://review.coreboot.org/c/coreboot/+/33201 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber --- src/soc/intel/fsp_broadwell_de/Kconfig | 1 + src/southbridge/intel/bd82x6x/Kconfig | 1 + src/southbridge/intel/common/Kconfig | 4 ++++ src/southbridge/intel/common/Makefile.inc | 2 +- src/southbridge/intel/fsp_rangeley/Kconfig | 1 + src/southbridge/intel/i82371eb/Kconfig | 1 + src/southbridge/intel/i82801dx/Kconfig | 1 + src/southbridge/intel/i82801gx/Kconfig | 1 + src/southbridge/intel/i82801ix/Kconfig | 1 + src/southbridge/intel/i82801jx/Kconfig | 1 + src/southbridge/intel/ibexpeak/Kconfig | 1 + src/southbridge/intel/lynxpoint/Kconfig | 1 + 12 files changed, 15 insertions(+), 1 deletion(-) diff --git a/src/soc/intel/fsp_broadwell_de/Kconfig b/src/soc/intel/fsp_broadwell_de/Kconfig index b2f4968004..c5417ae79e 100644 --- a/src/soc/intel/fsp_broadwell_de/Kconfig +++ b/src/soc/intel/fsp_broadwell_de/Kconfig @@ -15,6 +15,7 @@ config CPU_SPECIFIC_OPTIONS select SOUTHBRIDGE_INTEL_COMMON select SOUTHBRIDGE_INTEL_COMMON_SPI select SOUTHBRIDGE_INTEL_COMMON_RESET + select SOUTHBRIDGE_INTEL_COMMON_RTC select PARALLEL_MP select SMP select IOAPIC diff --git a/src/southbridge/intel/bd82x6x/Kconfig b/src/southbridge/intel/bd82x6x/Kconfig index f5b8b36a35..f7c14330f5 100644 --- a/src/southbridge/intel/bd82x6x/Kconfig +++ b/src/southbridge/intel/bd82x6x/Kconfig @@ -31,6 +31,7 @@ config SOUTH_BRIDGE_OPTIONS # dummy select SOUTHBRIDGE_INTEL_COMMON_SPI select SOUTHBRIDGE_INTEL_COMMON_PMCLIB select SOUTHBRIDGE_INTEL_COMMON_PMBASE + select SOUTHBRIDGE_INTEL_COMMON_RTC select IOAPIC select HAVE_USBDEBUG_OPTIONS select HAVE_SMI_HANDLER diff --git a/src/southbridge/intel/common/Kconfig b/src/southbridge/intel/common/Kconfig index c5aaa80f8c..d9e3e333a9 100644 --- a/src/southbridge/intel/common/Kconfig +++ b/src/southbridge/intel/common/Kconfig @@ -6,6 +6,10 @@ config SOUTHBRIDGE_INTEL_COMMON_RESET bool select HAVE_CF9_RESET +config SOUTHBRIDGE_INTEL_COMMON_RTC + def_bool n + depends on SOUTHBRIDGE_INTEL_COMMON + config SOUTHBRIDGE_INTEL_COMMON_PMCLIB def_bool n depends on SOUTHBRIDGE_INTEL_COMMON diff --git a/src/southbridge/intel/common/Makefile.inc b/src/southbridge/intel/common/Makefile.inc index 5ca7daf8a5..d8091f79d7 100644 --- a/src/southbridge/intel/common/Makefile.inc +++ b/src/southbridge/intel/common/Makefile.inc @@ -53,6 +53,6 @@ ramstage-$(CONFIG_SOUTHBRIDGE_INTEL_COMMON_ACPI_MADT) += madt.c smm-$(CONFIG_SOUTHBRIDGE_INTEL_COMMON_FINALIZE) += finalize.c -all-y += rtc.c +all-$(CONFIG_SOUTHBRIDGE_INTEL_COMMON_RTC) += rtc.c endif diff --git a/src/southbridge/intel/fsp_rangeley/Kconfig b/src/southbridge/intel/fsp_rangeley/Kconfig index 3460ea62c5..821bd918bf 100644 --- a/src/southbridge/intel/fsp_rangeley/Kconfig +++ b/src/southbridge/intel/fsp_rangeley/Kconfig @@ -33,6 +33,7 @@ config SOUTH_BRIDGE_OPTIONS # dummy select SOUTHBRIDGE_INTEL_COMMON_SMBUS select SOUTHBRIDGE_INTEL_COMMON_WATCHDOG select SOUTHBRIDGE_INTEL_COMMON_PMBASE + select SOUTHBRIDGE_INTEL_COMMON_RTC config EHCI_BAR hex diff --git a/src/southbridge/intel/i82371eb/Kconfig b/src/southbridge/intel/i82371eb/Kconfig index 6552099ed9..1d984a2dca 100644 --- a/src/southbridge/intel/i82371eb/Kconfig +++ b/src/southbridge/intel/i82371eb/Kconfig @@ -2,6 +2,7 @@ config SOUTHBRIDGE_INTEL_I82371EB select ACPI_INTEL_HARDWARE_SLEEP_VALUES select SOUTHBRIDGE_INTEL_COMMON select SOUTHBRIDGE_INTEL_COMMON_SMBUS + select SOUTHBRIDGE_INTEL_COMMON_RTC bool config BOOTBLOCK_SOUTHBRIDGE_INIT diff --git a/src/southbridge/intel/i82801dx/Kconfig b/src/southbridge/intel/i82801dx/Kconfig index 12640b32a2..cb2bb7aa7f 100644 --- a/src/southbridge/intel/i82801dx/Kconfig +++ b/src/southbridge/intel/i82801dx/Kconfig @@ -22,6 +22,7 @@ config SOUTHBRIDGE_INTEL_I82801DX select HAVE_USBDEBUG select SOUTHBRIDGE_INTEL_COMMON select SOUTHBRIDGE_INTEL_COMMON_SMBUS + select SOUTHBRIDGE_INTEL_COMMON_RTC select HAVE_POWER_STATE_AFTER_FAILURE select HAVE_POWER_STATE_PREVIOUS_AFTER_FAILURE diff --git a/src/southbridge/intel/i82801gx/Kconfig b/src/southbridge/intel/i82801gx/Kconfig index 5053a1fb2a..b549712b89 100644 --- a/src/southbridge/intel/i82801gx/Kconfig +++ b/src/southbridge/intel/i82801gx/Kconfig @@ -32,6 +32,7 @@ config SOUTHBRIDGE_INTEL_I82801GX select INTEL_HAS_TOP_SWAP select SOUTHBRIDGE_INTEL_COMMON_SMM select SOUTHBRIDGE_INTEL_COMMON_WATCHDOG + select SOUTHBRIDGE_INTEL_COMMON_RTC if SOUTHBRIDGE_INTEL_I82801GX diff --git a/src/southbridge/intel/i82801ix/Kconfig b/src/southbridge/intel/i82801ix/Kconfig index 1d51f43cfa..12049e99ed 100644 --- a/src/southbridge/intel/i82801ix/Kconfig +++ b/src/southbridge/intel/i82801ix/Kconfig @@ -21,6 +21,7 @@ config SOUTHBRIDGE_INTEL_I82801IX select SOUTHBRIDGE_INTEL_COMMON_SPI if !BOARD_EMULATION_QEMU_X86_Q35 select SOUTHBRIDGE_INTEL_COMMON_RCBA_PIRQ select SOUTHBRIDGE_INTEL_COMMON_PMBASE + select SOUTHBRIDGE_INTEL_COMMON_RTC select IOAPIC select HAVE_USBDEBUG select USE_WATCHDOG_ON_BOOT diff --git a/src/southbridge/intel/i82801jx/Kconfig b/src/southbridge/intel/i82801jx/Kconfig index 430adf9ca0..6d14d2d533 100644 --- a/src/southbridge/intel/i82801jx/Kconfig +++ b/src/southbridge/intel/i82801jx/Kconfig @@ -22,6 +22,7 @@ config SOUTHBRIDGE_INTEL_I82801JX select SOUTHBRIDGE_INTEL_COMMON_RCBA_PIRQ select SOUTHBRIDGE_INTEL_COMMON_PMCLIB select SOUTHBRIDGE_INTEL_COMMON_PMBASE + select SOUTHBRIDGE_INTEL_COMMON_RTC select IOAPIC select HAVE_USBDEBUG select USE_WATCHDOG_ON_BOOT diff --git a/src/southbridge/intel/ibexpeak/Kconfig b/src/southbridge/intel/ibexpeak/Kconfig index 620736c70c..2dda2b42b9 100644 --- a/src/southbridge/intel/ibexpeak/Kconfig +++ b/src/southbridge/intel/ibexpeak/Kconfig @@ -35,6 +35,7 @@ config SOUTH_BRIDGE_OPTIONS # dummy select SOUTHBRIDGE_INTEL_COMMON_SMM select SOUTHBRIDGE_INTEL_COMMON_PMCLIB select SOUTHBRIDGE_INTEL_COMMON_PMBASE + select SOUTHBRIDGE_INTEL_COMMON_RTC select HAVE_USBDEBUG_OPTIONS select COMMON_FADT select ACPI_SATA_GENERATOR diff --git a/src/southbridge/intel/lynxpoint/Kconfig b/src/southbridge/intel/lynxpoint/Kconfig index 2c28940c3b..a600a3ffc1 100644 --- a/src/southbridge/intel/lynxpoint/Kconfig +++ b/src/southbridge/intel/lynxpoint/Kconfig @@ -28,6 +28,7 @@ config SOUTH_BRIDGE_OPTIONS # dummy select SOUTHBRIDGE_INTEL_COMMON_FINALIZE select SOUTHBRIDGE_INTEL_COMMON_PMCLIB select SOUTHBRIDGE_INTEL_COMMON_PMBASE + select SOUTHBRIDGE_INTEL_COMMON_RTC select IOAPIC select HAVE_SMI_HANDLER select HAVE_USBDEBUG_OPTIONS From 23a6c79126a6ccba4459ae8ac7d7aa245bacb466 Mon Sep 17 00:00:00 2001 From: Arthur Heymans Date: Sun, 13 Oct 2019 22:36:04 +0200 Subject: [PATCH 0079/1242] sb/intel/common: Make COMMON_RESET optional Change-Id: Id706919835100903dd4ebac2bbd2f3a44c2b6b60 Signed-off-by: Arthur Heymans Reviewed-on: https://review.coreboot.org/c/coreboot/+/36003 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Rudolph --- src/southbridge/intel/bd82x6x/Kconfig | 1 + src/southbridge/intel/common/Kconfig | 3 +-- src/southbridge/intel/fsp_rangeley/Kconfig | 1 + src/southbridge/intel/i82371eb/Kconfig | 1 + src/southbridge/intel/i82801dx/Kconfig | 1 + src/southbridge/intel/i82801gx/Kconfig | 1 + src/southbridge/intel/i82801ix/Kconfig | 1 + src/southbridge/intel/i82801jx/Kconfig | 1 + src/southbridge/intel/ibexpeak/Kconfig | 1 + src/southbridge/intel/lynxpoint/Kconfig | 1 + 10 files changed, 10 insertions(+), 2 deletions(-) diff --git a/src/southbridge/intel/bd82x6x/Kconfig b/src/southbridge/intel/bd82x6x/Kconfig index f7c14330f5..4a56005cf5 100644 --- a/src/southbridge/intel/bd82x6x/Kconfig +++ b/src/southbridge/intel/bd82x6x/Kconfig @@ -32,6 +32,7 @@ config SOUTH_BRIDGE_OPTIONS # dummy select SOUTHBRIDGE_INTEL_COMMON_PMCLIB select SOUTHBRIDGE_INTEL_COMMON_PMBASE select SOUTHBRIDGE_INTEL_COMMON_RTC + select SOUTHBRIDGE_INTEL_COMMON_RESET select IOAPIC select HAVE_USBDEBUG_OPTIONS select HAVE_SMI_HANDLER diff --git a/src/southbridge/intel/common/Kconfig b/src/southbridge/intel/common/Kconfig index d9e3e333a9..5674c2f397 100644 --- a/src/southbridge/intel/common/Kconfig +++ b/src/southbridge/intel/common/Kconfig @@ -1,9 +1,8 @@ config SOUTHBRIDGE_INTEL_COMMON def_bool n - select SOUTHBRIDGE_INTEL_COMMON_RESET config SOUTHBRIDGE_INTEL_COMMON_RESET - bool + def_bool n select HAVE_CF9_RESET config SOUTHBRIDGE_INTEL_COMMON_RTC diff --git a/src/southbridge/intel/fsp_rangeley/Kconfig b/src/southbridge/intel/fsp_rangeley/Kconfig index 821bd918bf..a25c430b10 100644 --- a/src/southbridge/intel/fsp_rangeley/Kconfig +++ b/src/southbridge/intel/fsp_rangeley/Kconfig @@ -34,6 +34,7 @@ config SOUTH_BRIDGE_OPTIONS # dummy select SOUTHBRIDGE_INTEL_COMMON_WATCHDOG select SOUTHBRIDGE_INTEL_COMMON_PMBASE select SOUTHBRIDGE_INTEL_COMMON_RTC + select SOUTHBRIDGE_INTEL_COMMON_RESET config EHCI_BAR hex diff --git a/src/southbridge/intel/i82371eb/Kconfig b/src/southbridge/intel/i82371eb/Kconfig index 1d984a2dca..f72592623d 100644 --- a/src/southbridge/intel/i82371eb/Kconfig +++ b/src/southbridge/intel/i82371eb/Kconfig @@ -3,6 +3,7 @@ config SOUTHBRIDGE_INTEL_I82371EB select SOUTHBRIDGE_INTEL_COMMON select SOUTHBRIDGE_INTEL_COMMON_SMBUS select SOUTHBRIDGE_INTEL_COMMON_RTC + select SOUTHBRIDGE_INTEL_COMMON_RESET bool config BOOTBLOCK_SOUTHBRIDGE_INIT diff --git a/src/southbridge/intel/i82801dx/Kconfig b/src/southbridge/intel/i82801dx/Kconfig index cb2bb7aa7f..7cf7b979ee 100644 --- a/src/southbridge/intel/i82801dx/Kconfig +++ b/src/southbridge/intel/i82801dx/Kconfig @@ -23,6 +23,7 @@ config SOUTHBRIDGE_INTEL_I82801DX select SOUTHBRIDGE_INTEL_COMMON select SOUTHBRIDGE_INTEL_COMMON_SMBUS select SOUTHBRIDGE_INTEL_COMMON_RTC + select SOUTHBRIDGE_INTEL_COMMON_RESET select HAVE_POWER_STATE_AFTER_FAILURE select HAVE_POWER_STATE_PREVIOUS_AFTER_FAILURE diff --git a/src/southbridge/intel/i82801gx/Kconfig b/src/southbridge/intel/i82801gx/Kconfig index b549712b89..37b5e6d6d2 100644 --- a/src/southbridge/intel/i82801gx/Kconfig +++ b/src/southbridge/intel/i82801gx/Kconfig @@ -33,6 +33,7 @@ config SOUTHBRIDGE_INTEL_I82801GX select SOUTHBRIDGE_INTEL_COMMON_SMM select SOUTHBRIDGE_INTEL_COMMON_WATCHDOG select SOUTHBRIDGE_INTEL_COMMON_RTC + select SOUTHBRIDGE_INTEL_COMMON_RESET if SOUTHBRIDGE_INTEL_I82801GX diff --git a/src/southbridge/intel/i82801ix/Kconfig b/src/southbridge/intel/i82801ix/Kconfig index 12049e99ed..52fc5ea96f 100644 --- a/src/southbridge/intel/i82801ix/Kconfig +++ b/src/southbridge/intel/i82801ix/Kconfig @@ -22,6 +22,7 @@ config SOUTHBRIDGE_INTEL_I82801IX select SOUTHBRIDGE_INTEL_COMMON_RCBA_PIRQ select SOUTHBRIDGE_INTEL_COMMON_PMBASE select SOUTHBRIDGE_INTEL_COMMON_RTC + select SOUTHBRIDGE_INTEL_COMMON_RESET select IOAPIC select HAVE_USBDEBUG select USE_WATCHDOG_ON_BOOT diff --git a/src/southbridge/intel/i82801jx/Kconfig b/src/southbridge/intel/i82801jx/Kconfig index 6d14d2d533..7a49e57887 100644 --- a/src/southbridge/intel/i82801jx/Kconfig +++ b/src/southbridge/intel/i82801jx/Kconfig @@ -23,6 +23,7 @@ config SOUTHBRIDGE_INTEL_I82801JX select SOUTHBRIDGE_INTEL_COMMON_PMCLIB select SOUTHBRIDGE_INTEL_COMMON_PMBASE select SOUTHBRIDGE_INTEL_COMMON_RTC + select SOUTHBRIDGE_INTEL_COMMON_RESET select IOAPIC select HAVE_USBDEBUG select USE_WATCHDOG_ON_BOOT diff --git a/src/southbridge/intel/ibexpeak/Kconfig b/src/southbridge/intel/ibexpeak/Kconfig index 2dda2b42b9..5afc6acaa0 100644 --- a/src/southbridge/intel/ibexpeak/Kconfig +++ b/src/southbridge/intel/ibexpeak/Kconfig @@ -36,6 +36,7 @@ config SOUTH_BRIDGE_OPTIONS # dummy select SOUTHBRIDGE_INTEL_COMMON_PMCLIB select SOUTHBRIDGE_INTEL_COMMON_PMBASE select SOUTHBRIDGE_INTEL_COMMON_RTC + select SOUTHBRIDGE_INTEL_COMMON_RESET select HAVE_USBDEBUG_OPTIONS select COMMON_FADT select ACPI_SATA_GENERATOR diff --git a/src/southbridge/intel/lynxpoint/Kconfig b/src/southbridge/intel/lynxpoint/Kconfig index a600a3ffc1..ac2a8f755a 100644 --- a/src/southbridge/intel/lynxpoint/Kconfig +++ b/src/southbridge/intel/lynxpoint/Kconfig @@ -29,6 +29,7 @@ config SOUTH_BRIDGE_OPTIONS # dummy select SOUTHBRIDGE_INTEL_COMMON_PMCLIB select SOUTHBRIDGE_INTEL_COMMON_PMBASE select SOUTHBRIDGE_INTEL_COMMON_RTC + select SOUTHBRIDGE_INTEL_COMMON_RESET select IOAPIC select HAVE_SMI_HANDLER select HAVE_USBDEBUG_OPTIONS From 1d4bdda47f030d01418936d3399856dddfa7f43b Mon Sep 17 00:00:00 2001 From: Arthur Heymans Date: Tue, 29 Oct 2019 18:33:30 +0100 Subject: [PATCH 0080/1242] sb/intel/common: Remove the SOUTHBRIDGE_INTEL_COMMON Kconfig symbol All code in southbridge/intel/common is now properly guarded by a Kconfig symbol, making SOUTHBRIDGE_INTEL_COMMON obsolete. Change-Id: Ifeccfaa9534f903e3f3543e1f9f3d5f3345b461e Signed-off-by: Arthur Heymans Reviewed-on: https://review.coreboot.org/c/coreboot/+/36438 Reviewed-by: Nico Huber Tested-by: build bot (Jenkins) --- src/soc/intel/fsp_broadwell_de/Kconfig | 1 - src/southbridge/intel/bd82x6x/Kconfig | 1 - src/southbridge/intel/common/Kconfig | 7 ------- src/southbridge/intel/common/Makefile.inc | 4 ---- src/southbridge/intel/fsp_rangeley/Kconfig | 1 - src/southbridge/intel/i82371eb/Kconfig | 1 - src/southbridge/intel/i82801dx/Kconfig | 1 - src/southbridge/intel/i82801gx/Kconfig | 1 - src/southbridge/intel/i82801ix/Kconfig | 1 - src/southbridge/intel/i82801jx/Kconfig | 1 - src/southbridge/intel/ibexpeak/Kconfig | 1 - src/southbridge/intel/lynxpoint/Kconfig | 1 - 12 files changed, 21 deletions(-) diff --git a/src/soc/intel/fsp_broadwell_de/Kconfig b/src/soc/intel/fsp_broadwell_de/Kconfig index c5417ae79e..4c45f29618 100644 --- a/src/soc/intel/fsp_broadwell_de/Kconfig +++ b/src/soc/intel/fsp_broadwell_de/Kconfig @@ -12,7 +12,6 @@ config CPU_SPECIFIC_OPTIONS select ARCH_VERSTAGE_X86_32 select ARCH_ROMSTAGE_X86_32 select ARCH_RAMSTAGE_X86_32 - select SOUTHBRIDGE_INTEL_COMMON select SOUTHBRIDGE_INTEL_COMMON_SPI select SOUTHBRIDGE_INTEL_COMMON_RESET select SOUTHBRIDGE_INTEL_COMMON_RTC diff --git a/src/southbridge/intel/bd82x6x/Kconfig b/src/southbridge/intel/bd82x6x/Kconfig index 4a56005cf5..f561fe53fb 100644 --- a/src/southbridge/intel/bd82x6x/Kconfig +++ b/src/southbridge/intel/bd82x6x/Kconfig @@ -24,7 +24,6 @@ if SOUTHBRIDGE_INTEL_BD82X6X || SOUTHBRIDGE_INTEL_C216 config SOUTH_BRIDGE_OPTIONS # dummy def_bool y select ACPI_INTEL_HARDWARE_SLEEP_VALUES - select SOUTHBRIDGE_INTEL_COMMON select SOUTHBRIDGE_INTEL_COMMON_FINALIZE select SOUTHBRIDGE_INTEL_COMMON_RCBA_PIRQ select SOUTHBRIDGE_INTEL_COMMON_SMBUS diff --git a/src/southbridge/intel/common/Kconfig b/src/southbridge/intel/common/Kconfig index 5674c2f397..57c0dbe19f 100644 --- a/src/southbridge/intel/common/Kconfig +++ b/src/southbridge/intel/common/Kconfig @@ -1,22 +1,16 @@ -config SOUTHBRIDGE_INTEL_COMMON - def_bool n - config SOUTHBRIDGE_INTEL_COMMON_RESET def_bool n select HAVE_CF9_RESET config SOUTHBRIDGE_INTEL_COMMON_RTC def_bool n - depends on SOUTHBRIDGE_INTEL_COMMON config SOUTHBRIDGE_INTEL_COMMON_PMCLIB def_bool n - depends on SOUTHBRIDGE_INTEL_COMMON depends on SOUTHBRIDGE_INTEL_COMMON_PMBASE config SOUTHBRIDGE_INTEL_COMMON_PMBASE def_bool n - depends on SOUTHBRIDGE_INTEL_COMMON config SOUTHBRIDGE_INTEL_COMMON_GPIO def_bool n @@ -86,7 +80,6 @@ config INTEL_CHIPSET_LOCKDOWN config SOUTHBRIDGE_INTEL_COMMON_WATCHDOG bool - depends on SOUTHBRIDGE_INTEL_COMMON depends on SOUTHBRIDGE_INTEL_COMMON_PMBASE if SOUTHBRIDGE_INTEL_COMMON_FINALIZE diff --git a/src/southbridge/intel/common/Makefile.inc b/src/southbridge/intel/common/Makefile.inc index d8091f79d7..68e423af59 100644 --- a/src/southbridge/intel/common/Makefile.inc +++ b/src/southbridge/intel/common/Makefile.inc @@ -25,8 +25,6 @@ romstage-$(CONFIG_SOUTHBRIDGE_INTEL_COMMON_PMCLIB) += pmclib.c ramstage-$(CONFIG_SOUTHBRIDGE_INTEL_COMMON_WATCHDOG) += watchdog.c -ifeq ($(CONFIG_SOUTHBRIDGE_INTEL_COMMON),y) - all-$(CONFIG_SOUTHBRIDGE_INTEL_COMMON_PMBASE) += pmbase.c smm-$(CONFIG_SOUTHBRIDGE_INTEL_COMMON_PMBASE) += pmbase.c @@ -54,5 +52,3 @@ ramstage-$(CONFIG_SOUTHBRIDGE_INTEL_COMMON_ACPI_MADT) += madt.c smm-$(CONFIG_SOUTHBRIDGE_INTEL_COMMON_FINALIZE) += finalize.c all-$(CONFIG_SOUTHBRIDGE_INTEL_COMMON_RTC) += rtc.c - -endif diff --git a/src/southbridge/intel/fsp_rangeley/Kconfig b/src/southbridge/intel/fsp_rangeley/Kconfig index a25c430b10..56c02b534d 100644 --- a/src/southbridge/intel/fsp_rangeley/Kconfig +++ b/src/southbridge/intel/fsp_rangeley/Kconfig @@ -29,7 +29,6 @@ config SOUTH_BRIDGE_OPTIONS # dummy select PCIEXP_COMMON_CLOCK select SPI_FLASH select INTEL_DESCRIPTOR_MODE_CAPABLE - select SOUTHBRIDGE_INTEL_COMMON select SOUTHBRIDGE_INTEL_COMMON_SMBUS select SOUTHBRIDGE_INTEL_COMMON_WATCHDOG select SOUTHBRIDGE_INTEL_COMMON_PMBASE diff --git a/src/southbridge/intel/i82371eb/Kconfig b/src/southbridge/intel/i82371eb/Kconfig index f72592623d..f5b5f4ee1e 100644 --- a/src/southbridge/intel/i82371eb/Kconfig +++ b/src/southbridge/intel/i82371eb/Kconfig @@ -1,6 +1,5 @@ config SOUTHBRIDGE_INTEL_I82371EB select ACPI_INTEL_HARDWARE_SLEEP_VALUES - select SOUTHBRIDGE_INTEL_COMMON select SOUTHBRIDGE_INTEL_COMMON_SMBUS select SOUTHBRIDGE_INTEL_COMMON_RTC select SOUTHBRIDGE_INTEL_COMMON_RESET diff --git a/src/southbridge/intel/i82801dx/Kconfig b/src/southbridge/intel/i82801dx/Kconfig index 7cf7b979ee..916560a87a 100644 --- a/src/southbridge/intel/i82801dx/Kconfig +++ b/src/southbridge/intel/i82801dx/Kconfig @@ -20,7 +20,6 @@ config SOUTHBRIDGE_INTEL_I82801DX select IOAPIC select HAVE_SMI_HANDLER select HAVE_USBDEBUG - select SOUTHBRIDGE_INTEL_COMMON select SOUTHBRIDGE_INTEL_COMMON_SMBUS select SOUTHBRIDGE_INTEL_COMMON_RTC select SOUTHBRIDGE_INTEL_COMMON_RESET diff --git a/src/southbridge/intel/i82801gx/Kconfig b/src/southbridge/intel/i82801gx/Kconfig index 37b5e6d6d2..b0cdfd416c 100644 --- a/src/southbridge/intel/i82801gx/Kconfig +++ b/src/southbridge/intel/i82801gx/Kconfig @@ -16,7 +16,6 @@ config SOUTHBRIDGE_INTEL_I82801GX bool select ACPI_INTEL_HARDWARE_SLEEP_VALUES - select SOUTHBRIDGE_INTEL_COMMON select IOAPIC select HAVE_USBDEBUG select USE_WATCHDOG_ON_BOOT diff --git a/src/southbridge/intel/i82801ix/Kconfig b/src/southbridge/intel/i82801ix/Kconfig index 52fc5ea96f..cd2f76d9b5 100644 --- a/src/southbridge/intel/i82801ix/Kconfig +++ b/src/southbridge/intel/i82801ix/Kconfig @@ -16,7 +16,6 @@ config SOUTHBRIDGE_INTEL_I82801IX bool - select SOUTHBRIDGE_INTEL_COMMON select SOUTHBRIDGE_INTEL_COMMON_SMBUS select SOUTHBRIDGE_INTEL_COMMON_SPI if !BOARD_EMULATION_QEMU_X86_Q35 select SOUTHBRIDGE_INTEL_COMMON_RCBA_PIRQ diff --git a/src/southbridge/intel/i82801jx/Kconfig b/src/southbridge/intel/i82801jx/Kconfig index 7a49e57887..eeb843e910 100644 --- a/src/southbridge/intel/i82801jx/Kconfig +++ b/src/southbridge/intel/i82801jx/Kconfig @@ -16,7 +16,6 @@ config SOUTHBRIDGE_INTEL_I82801JX bool - select SOUTHBRIDGE_INTEL_COMMON select SOUTHBRIDGE_INTEL_COMMON_SMBUS select SOUTHBRIDGE_INTEL_COMMON_SPI select SOUTHBRIDGE_INTEL_COMMON_RCBA_PIRQ diff --git a/src/southbridge/intel/ibexpeak/Kconfig b/src/southbridge/intel/ibexpeak/Kconfig index 5afc6acaa0..c84a66d313 100644 --- a/src/southbridge/intel/ibexpeak/Kconfig +++ b/src/southbridge/intel/ibexpeak/Kconfig @@ -27,7 +27,6 @@ config SOUTH_BRIDGE_OPTIONS # dummy select USE_WATCHDOG_ON_BOOT select PCIEXP_ASPM select PCIEXP_COMMON_CLOCK - select SOUTHBRIDGE_INTEL_COMMON select SOUTHBRIDGE_INTEL_COMMON_FINALIZE select SOUTHBRIDGE_INTEL_COMMON_RCBA_PIRQ select SOUTHBRIDGE_INTEL_COMMON_SMBUS diff --git a/src/southbridge/intel/lynxpoint/Kconfig b/src/southbridge/intel/lynxpoint/Kconfig index ac2a8f755a..95b9f625f2 100644 --- a/src/southbridge/intel/lynxpoint/Kconfig +++ b/src/southbridge/intel/lynxpoint/Kconfig @@ -21,7 +21,6 @@ if SOUTHBRIDGE_INTEL_LYNXPOINT config SOUTH_BRIDGE_OPTIONS # dummy def_bool y select ACPI_INTEL_HARDWARE_SLEEP_VALUES - select SOUTHBRIDGE_INTEL_COMMON select SOUTHBRIDGE_INTEL_COMMON_SMBUS select SOUTHBRIDGE_INTEL_COMMON_SPI select SOUTHBRIDGE_INTEL_COMMON_ACPI_MADT From 2abbe467658a8e4479c381330e85e126c8f42a90 Mon Sep 17 00:00:00 2001 From: Arthur Heymans Date: Tue, 4 Jun 2019 14:12:01 +0200 Subject: [PATCH 0081/1242] soc/intel/broadwell: Use common SB RTC code Change-Id: Iedb9a8962ac1b4107e9192b0be610fb92d2cfdc6 Signed-off-by: Arthur Heymans Reviewed-on: https://review.coreboot.org/c/coreboot/+/33202 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber --- src/soc/intel/broadwell/Kconfig | 1 + src/soc/intel/broadwell/include/soc/pm.h | 3 --- src/soc/intel/broadwell/lpc.c | 8 ++------ src/soc/intel/broadwell/pmutil.c | 26 ------------------------ 4 files changed, 3 insertions(+), 35 deletions(-) diff --git a/src/soc/intel/broadwell/Kconfig b/src/soc/intel/broadwell/Kconfig index 0bbb668c98..f69c7de4a7 100644 --- a/src/soc/intel/broadwell/Kconfig +++ b/src/soc/intel/broadwell/Kconfig @@ -19,6 +19,7 @@ config CPU_SPECIFIC_OPTIONS select SUPPORT_CPU_UCODE_IN_CBFS select HAVE_SMI_HANDLER select SOUTHBRIDGE_INTEL_COMMON_RESET + select SOUTHBRIDGE_INTEL_COMMON_RTC select HAVE_USBDEBUG select IOAPIC select REG_SCRIPT diff --git a/src/soc/intel/broadwell/include/soc/pm.h b/src/soc/intel/broadwell/include/soc/pm.h index 343cf2ba68..18004fa77d 100644 --- a/src/soc/intel/broadwell/include/soc/pm.h +++ b/src/soc/intel/broadwell/include/soc/pm.h @@ -155,7 +155,4 @@ void disable_gpe(uint32_t mask); /* Return the selected ACPI SCI IRQ */ int acpi_sci_irq(void); -/* Return non-zero when RTC failure happened. */ -int rtc_failure(void); - #endif diff --git a/src/soc/intel/broadwell/lpc.c b/src/soc/intel/broadwell/lpc.c index 873f594530..3392614303 100644 --- a/src/soc/intel/broadwell/lpc.c +++ b/src/soc/intel/broadwell/lpc.c @@ -42,6 +42,7 @@ #include #include #include +#include static void pch_enable_ioapic(struct device *dev) { @@ -190,11 +191,6 @@ static void pch_power_options(struct device *dev) enable_alt_smi(config->alt_gp_smi_en); } -static void pch_rtc_init(struct device *dev) -{ - cmos_init(rtc_failure()); -} - static const struct reg_script pch_misc_init_script[] = { /* Setup SLP signal assertion, SLP_S4=4s, SLP_S3=50ms */ REG_PCI_RMW16(GEN_PMCON_3, ~((3 << 4)|(1 << 10)), @@ -439,7 +435,7 @@ static void lpc_init(struct device *dev) { /* Legacy initialization */ isa_dma_init(); - pch_rtc_init(dev); + sb_rtc_init(); reg_script_run_on_dev(dev, pch_misc_init_script); /* Interrupt configuration */ diff --git a/src/soc/intel/broadwell/pmutil.c b/src/soc/intel/broadwell/pmutil.c index 322e96f4a0..00db6156ec 100644 --- a/src/soc/intel/broadwell/pmutil.c +++ b/src/soc/intel/broadwell/pmutil.c @@ -451,32 +451,6 @@ int acpi_sci_irq(void) return sci_irq; } -int rtc_failure(void) -{ - u8 reg8; - int rtc_failed; -#if defined(__SIMPLE_DEVICE__) - pci_devfn_t dev = PCH_DEV_LPC; -#else - struct device *dev = PCH_DEV_LPC; -#endif - - reg8 = pci_read_config8(dev, GEN_PMCON_3); - rtc_failed = reg8 & RTC_BATTERY_DEAD; - if (rtc_failed) { - reg8 &= ~RTC_BATTERY_DEAD; - pci_write_config8(dev, GEN_PMCON_3, reg8); - printk(BIOS_DEBUG, "rtc_failed = 0x%x\n", rtc_failed); - } - - return !!rtc_failed; -} - -int vbnv_cmos_failed(void) -{ - return rtc_failure(); -} - int vboot_platform_is_resuming(void) { if (!(inw(ACPI_BASE_ADDRESS + PM1_STS) & WAK_STS)) From 95755dd65d18955e375345f06da7966f137e7d62 Mon Sep 17 00:00:00 2001 From: Arthur Heymans Date: Tue, 4 Jun 2019 14:13:50 +0200 Subject: [PATCH 0082/1242] soc/intel/broadwell: Use common INTEL_SB SPI code Change-Id: Id906733ac3719c8d6835aad52ca87beb81b5771d Signed-off-by: Arthur Heymans Reviewed-on: https://review.coreboot.org/c/coreboot/+/33203 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber --- src/soc/intel/broadwell/Kconfig | 1 + src/soc/intel/broadwell/Makefile.inc | 5 - src/soc/intel/broadwell/include/soc/spi.h | 28 - src/soc/intel/broadwell/spi.c | 666 ---------------------- 4 files changed, 1 insertion(+), 699 deletions(-) delete mode 100644 src/soc/intel/broadwell/spi.c diff --git a/src/soc/intel/broadwell/Kconfig b/src/soc/intel/broadwell/Kconfig index f69c7de4a7..095ed988c6 100644 --- a/src/soc/intel/broadwell/Kconfig +++ b/src/soc/intel/broadwell/Kconfig @@ -20,6 +20,7 @@ config CPU_SPECIFIC_OPTIONS select HAVE_SMI_HANDLER select SOUTHBRIDGE_INTEL_COMMON_RESET select SOUTHBRIDGE_INTEL_COMMON_RTC + select SOUTHBRIDGE_INTEL_COMMON_SPI select HAVE_USBDEBUG select IOAPIC select REG_SCRIPT diff --git a/src/soc/intel/broadwell/Makefile.inc b/src/soc/intel/broadwell/Makefile.inc index 055a0049af..8f690cc4f6 100644 --- a/src/soc/intel/broadwell/Makefile.inc +++ b/src/soc/intel/broadwell/Makefile.inc @@ -58,11 +58,6 @@ romstage-y += smbus_common.c ramstage-y += smi.c smm-y += smihandler.c ramstage-y += smmrelocate.c -bootblock-y += spi.c -romstage-y += spi.c -postcar-y += spi.c -ramstage-y += spi.c -smm-$(CONFIG_SPI_FLASH_SMM) += spi.c ramstage-y += systemagent.c bootblock-y += tsc_freq.c ramstage-y += tsc_freq.c diff --git a/src/soc/intel/broadwell/include/soc/spi.h b/src/soc/intel/broadwell/include/soc/spi.h index 5ad62fd19d..f3572570ea 100644 --- a/src/soc/intel/broadwell/include/soc/spi.h +++ b/src/soc/intel/broadwell/include/soc/spi.h @@ -23,7 +23,6 @@ #define SPIBAR_OFFSET 0x3800 #define SPIBAR8(x) RCBA8(x + SPIBAR_OFFSET) -#define SPIBAR16(x) RCBA16(x + SPIBAR_OFFSET) #define SPIBAR32(x) RCBA32(x + SPIBAR_OFFSET) /* Registers within the SPIBAR */ @@ -31,15 +30,6 @@ #define SPIBAR_FDOC 0xb0 #define SPIBAR_FDOD 0xb4 -#define SPI_PRR_MAX 5 -#define SPI_PRR(x) (0x74 + ((x) * 4)) -#define SPI_PRR_SHIFT 12 -#define SPI_PRR_MASK 0x1fff -#define SPI_PRR_BASE_SHIFT 0 -#define SPI_PRR_LIMIT_SHIFT 16 -#define SPI_PRR_WPE (1 << 31) -#define SPI_PRR_RPE (1 << 15) - #define SPIBAR_PREOP 0x94 #define SPIBAR_OPTYPE 0x96 #define SPIBAR_OPMENU_LOWER 0x98 @@ -83,23 +73,5 @@ #define SPIBAR_HSFS 0x04 /* SPI hardware sequence status */ #define SPIBAR_HSFS_FLOCKDN (1 << 15)/* Flash Configuration Lock-Down */ -#define SPIBAR_HSFS_SCIP (1 << 5) /* SPI Cycle In Progress */ -#define SPIBAR_HSFS_AEL (1 << 2) /* SPI Access Error Log */ -#define SPIBAR_HSFS_FCERR (1 << 1) /* SPI Flash Cycle Error */ -#define SPIBAR_HSFS_FDONE (1 << 0) /* SPI Flash Cycle Done */ -#define SPIBAR_HSFC 0x06 /* SPI hardware sequence control */ -#define SPIBAR_HSFC_BYTE_COUNT(c) (((c - 1) & 0x3f) << 8) -#define SPIBAR_HSFC_CYCLE_READ (0 << 1) /* Read cycle */ -#define SPIBAR_HSFC_CYCLE_WRITE (2 << 1) /* Write cycle */ -#define SPIBAR_HSFC_CYCLE_ERASE (3 << 1) /* Erase cycle */ -#define SPIBAR_HSFC_GO (1 << 0) /* GO: start SPI transaction */ -#define SPIBAR_FADDR 0x08 /* SPI flash address */ -#define SPIBAR_FDATA(n) (0x10 + (4 * n)) /* SPI flash data */ -#define SPIBAR_SSFS 0x90 -#define SPIBAR_SSFS_ERROR (1 << 3) -#define SPIBAR_SSFS_DONE (1 << 2) -#define SPIBAR_SSFC 0x91 -#define SPIBAR_SSFC_DATA (1 << 14) -#define SPIBAR_SSFC_GO (1 << 1) #endif diff --git a/src/soc/intel/broadwell/spi.c b/src/soc/intel/broadwell/spi.c deleted file mode 100644 index ac893ea33d..0000000000 --- a/src/soc/intel/broadwell/spi.c +++ /dev/null @@ -1,666 +0,0 @@ -/* - * Copyright (C) 2014 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -/* This file is derived from the flashrom project. */ -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -typedef struct spi_slave ich_spi_slave; - -static int ichspi_lock = 0; - -typedef struct ich9_spi_regs { - uint32_t bfpr; - uint16_t hsfs; - uint16_t hsfc; - uint32_t faddr; - uint32_t _reserved0; - uint32_t fdata[16]; - uint32_t frap; - uint32_t freg[5]; - uint32_t _reserved1[3]; - uint32_t pr[5]; - uint32_t _reserved2[2]; - uint8_t ssfs; - uint8_t ssfc[3]; - uint16_t preop; - uint16_t optype; - uint8_t opmenu[8]; - uint32_t bbar; - uint8_t _reserved3[12]; - uint32_t fdoc; - uint32_t fdod; - uint8_t _reserved4[8]; - uint32_t afc; - uint32_t lvscc; - uint32_t uvscc; - uint8_t _reserved5[4]; - uint32_t fpb; - uint8_t _reserved6[28]; - uint32_t srdl; - uint32_t srdc; - uint32_t srd; -} __packed ich9_spi_regs; - -typedef struct ich_spi_controller { - int locked; - - uint8_t *opmenu; - int menubytes; - uint16_t *preop; - uint16_t *optype; - uint32_t *addr; - uint8_t *data; - unsigned int databytes; - uint8_t *status; - uint16_t *control; - uint32_t *bbar; -} ich_spi_controller; - -static ich_spi_controller cntlr; - -enum { - SPIS_SCIP = 0x0001, - SPIS_GRANT = 0x0002, - SPIS_CDS = 0x0004, - SPIS_FCERR = 0x0008, - SSFS_AEL = 0x0010, - SPIS_LOCK = 0x8000, - SPIS_RESERVED_MASK = 0x7ff0, - SSFS_RESERVED_MASK = 0x7fe2 -}; - -enum { - SPIC_SCGO = 0x000002, - SPIC_ACS = 0x000004, - SPIC_SPOP = 0x000008, - SPIC_DBC = 0x003f00, - SPIC_DS = 0x004000, - SPIC_SME = 0x008000, - SSFC_SCF_MASK = 0x070000, - SSFC_RESERVED = 0xf80000 -}; - -enum { - HSFS_FDONE = 0x0001, - HSFS_FCERR = 0x0002, - HSFS_AEL = 0x0004, - HSFS_BERASE_MASK = 0x0018, - HSFS_BERASE_SHIFT = 3, - HSFS_SCIP = 0x0020, - HSFS_FDOPSS = 0x2000, - HSFS_FDV = 0x4000, - HSFS_FLOCKDN = 0x8000 -}; - -enum { - HSFC_FGO = 0x0001, - HSFC_FCYCLE_MASK = 0x0006, - HSFC_FCYCLE_SHIFT = 1, - HSFC_FDBC_MASK = 0x3f00, - HSFC_FDBC_SHIFT = 8, - HSFC_FSMIE = 0x8000 -}; - -enum { - SPI_OPCODE_TYPE_READ_NO_ADDRESS = 0, - SPI_OPCODE_TYPE_WRITE_NO_ADDRESS = 1, - SPI_OPCODE_TYPE_READ_WITH_ADDRESS = 2, - SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS = 3 -}; - -#if CONFIG(DEBUG_SPI_FLASH) - -static u8 readb_(const void *addr) -{ - u8 v = read8(addr); - printk(BIOS_DEBUG, "read %2.2x from %4.4x\n", - v, ((unsigned int) addr & 0xffff) - 0xf020); - return v; -} - -static u16 readw_(const void *addr) -{ - u16 v = read16(addr); - printk(BIOS_DEBUG, "read %4.4x from %4.4x\n", - v, ((unsigned int) addr & 0xffff) - 0xf020); - return v; -} - -static u32 readl_(const void *addr) -{ - u32 v = read32(addr); - printk(BIOS_DEBUG, "read %8.8x from %4.4x\n", - v, ((unsigned int) addr & 0xffff) - 0xf020); - return v; -} - -static void writeb_(u8 b, void *addr) -{ - write8(addr, b); - printk(BIOS_DEBUG, "wrote %2.2x to %4.4x\n", - b, ((unsigned int) addr & 0xffff) - 0xf020); -} - -static void writew_(u16 b, void *addr) -{ - write16(addr, b); - printk(BIOS_DEBUG, "wrote %4.4x to %4.4x\n", - b, ((unsigned int) addr & 0xffff) - 0xf020); -} - -static void writel_(u32 b, void *addr) -{ - write32(addr, b); - printk(BIOS_DEBUG, "wrote %8.8x to %4.4x\n", - b, ((unsigned int) addr & 0xffff) - 0xf020); -} - -#else /* CONFIG_DEBUG_SPI_FLASH ^^^ enabled vvv NOT enabled */ - -#define readb_(a) read8(a) -#define readw_(a) read16(a) -#define readl_(a) read32(a) -#define writeb_(val, addr) write8(addr, val) -#define writew_(val, addr) write16(addr, val) -#define writel_(val, addr) write32(addr, val) - -#endif /* CONFIG_DEBUG_SPI_FLASH ^^^ NOT enabled */ - -static void write_reg(const void *value, void *dest, uint32_t size) -{ - const uint8_t *bvalue = value; - uint8_t *bdest = dest; - - while (size >= 4) { - writel_(*(const uint32_t *)bvalue, bdest); - bdest += 4; bvalue += 4; size -= 4; - } - while (size) { - writeb_(*bvalue, bdest); - bdest++; bvalue++; size--; - } -} - -static void read_reg(const void *src, void *value, uint32_t size) -{ - const uint8_t *bsrc = src; - uint8_t *bvalue = value; - - while (size >= 4) { - *(uint32_t *)bvalue = readl_(bsrc); - bsrc += 4; bvalue += 4; size -= 4; - } - while (size) { - *bvalue = readb_(bsrc); - bsrc++; bvalue++; size--; - } -} - -static void ich_set_bbar(uint32_t minaddr) -{ - const uint32_t bbar_mask = 0x00ffff00; - uint32_t ichspi_bbar; - - minaddr &= bbar_mask; - ichspi_bbar = readl_(cntlr.bbar) & ~bbar_mask; - ichspi_bbar |= minaddr; - writel_(ichspi_bbar, cntlr.bbar); -} - -#define MENU_BYTES member_size(struct ich9_spi_regs, opmenu) - -void spi_init(void) -{ - uint8_t *rcrb; /* Root Complex Register Block */ - uint32_t rcba; /* Root Complex Base Address */ - uint8_t bios_cntl; -#if defined(__SIMPLE_DEVICE__) - pci_devfn_t dev = PCH_DEV_LPC; -#else - struct device *dev = PCH_DEV_LPC; -#endif - ich9_spi_regs *ich9_spi; - - rcba = pci_read_config32(dev, 0xf0); - /* Bits 31-14 are the base address, 13-1 are reserved, 0 is enable. */ - rcrb = (uint8_t *)(rcba & 0xffffc000); - ich9_spi = (ich9_spi_regs *)(rcrb + 0x3800); - ichspi_lock = readw_(&ich9_spi->hsfs) & HSFS_FLOCKDN; - cntlr.opmenu = ich9_spi->opmenu; - cntlr.menubytes = sizeof(ich9_spi->opmenu); - cntlr.optype = &ich9_spi->optype; - cntlr.addr = &ich9_spi->faddr; - cntlr.data = (uint8_t *)ich9_spi->fdata; - cntlr.databytes = sizeof(ich9_spi->fdata); - cntlr.status = &ich9_spi->ssfs; - cntlr.control = (uint16_t *)ich9_spi->ssfc; - cntlr.bbar = &ich9_spi->bbar; - cntlr.preop = &ich9_spi->preop; - ich_set_bbar(0); - - /* Disable the BIOS write protect so write commands are allowed. */ - bios_cntl = pci_read_config8(dev, 0xdc); - bios_cntl &= ~(1 << 5); - pci_write_config8(dev, 0xdc, bios_cntl | 0x1); -} - -static void spi_init_cb(void *unused) -{ - spi_init(); -} - -BOOT_STATE_INIT_ENTRY(BS_DEV_INIT, BS_ON_ENTRY, spi_init_cb, NULL); - -typedef struct spi_transaction { - const uint8_t *out; - uint32_t bytesout; - uint8_t *in; - uint32_t bytesin; - uint8_t type; - uint8_t opcode; - uint32_t offset; -} spi_transaction; - -static inline void spi_use_out(spi_transaction *trans, unsigned int bytes) -{ - trans->out += bytes; - trans->bytesout -= bytes; -} - -static inline void spi_use_in(spi_transaction *trans, unsigned int bytes) -{ - trans->in += bytes; - trans->bytesin -= bytes; -} - -static void spi_setup_type(spi_transaction *trans) -{ - trans->type = 0xFF; - - /* Try to guess spi type from read/write sizes. */ - if (trans->bytesin == 0) { - if (trans->bytesout > 4) - /* - * If bytesin = 0 and bytesout > 4, we presume this is - * a write data operation, which is accompanied by an - * address. - */ - trans->type = SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS; - else - trans->type = SPI_OPCODE_TYPE_WRITE_NO_ADDRESS; - return; - } - - if (trans->bytesout == 1) { /* and bytesin is > 0 */ - trans->type = SPI_OPCODE_TYPE_READ_NO_ADDRESS; - return; - } - - if (trans->bytesout == 4) { /* and bytesin is > 0 */ - trans->type = SPI_OPCODE_TYPE_READ_WITH_ADDRESS; - } - - /* Fast read command is called with 5 bytes instead of 4 */ - if (trans->out[0] == SPI_OPCODE_FAST_READ && trans->bytesout == 5) { - trans->type = SPI_OPCODE_TYPE_READ_WITH_ADDRESS; - --trans->bytesout; - } -} - -static int spi_setup_opcode(spi_transaction *trans) -{ - uint16_t optypes; - uint8_t opmenu[MENU_BYTES]; - - trans->opcode = trans->out[0]; - spi_use_out(trans, 1); - if (!ichspi_lock) { - /* The lock is off, so just use index 0. */ - writeb_(trans->opcode, cntlr.opmenu); - optypes = readw_(cntlr.optype); - optypes = (optypes & 0xfffc) | (trans->type & 0x3); - writew_(optypes, cntlr.optype); - return 0; - } - - /* The lock is on. See if what we need is on the menu. */ - uint8_t optype; - uint16_t opcode_index; - - /* Write Enable is handled as atomic prefix */ - if (trans->opcode == SPI_OPCODE_WREN) - return 0; - - read_reg(cntlr.opmenu, opmenu, sizeof(opmenu)); - for (opcode_index = 0; opcode_index < ARRAY_SIZE(opmenu); opcode_index++) { - if (opmenu[opcode_index] == trans->opcode) - break; - } - - if (opcode_index == ARRAY_SIZE(opmenu)) { - printk(BIOS_DEBUG, "ICH SPI: Opcode %x not found\n", - trans->opcode); - return -1; - } - - optypes = readw_(cntlr.optype); - optype = (optypes >> (opcode_index * 2)) & 0x3; - if (trans->type == SPI_OPCODE_TYPE_WRITE_NO_ADDRESS && - optype == SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS && - trans->bytesout >= 3) { - /* We guessed wrong earlier. Fix it up. */ - trans->type = optype; - } - if (optype != trans->type) { - printk(BIOS_DEBUG, "ICH SPI: Transaction doesn't fit type %d\n", - optype); - return -1; - } - return opcode_index; -} - -static int spi_setup_offset(spi_transaction *trans) -{ - /* Separate the SPI address and data. */ - switch (trans->type) { - case SPI_OPCODE_TYPE_READ_NO_ADDRESS: - case SPI_OPCODE_TYPE_WRITE_NO_ADDRESS: - return 0; - case SPI_OPCODE_TYPE_READ_WITH_ADDRESS: - case SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS: - trans->offset = ((uint32_t)trans->out[0] << 16) | - ((uint32_t)trans->out[1] << 8) | - ((uint32_t)trans->out[2] << 0); - spi_use_out(trans, 3); - return 1; - default: - printk(BIOS_DEBUG, "Unrecognized SPI transaction type %#x\n", - trans->type); - return -1; - } -} - -/* - * Wait for up to 60ms til status register bit(s) turn 1 (in case wait_til_set - * below is True) or 0. In case the wait was for the bit(s) to set - write - * those bits back, which would cause resetting them. - * - * Return the last read status value on success or -1 on failure. - */ -static int ich_status_poll(u16 bitmask, int wait_til_set) -{ - int timeout = 6000; /* This will result in 60 ms */ - u16 status = 0; - - while (timeout--) { - status = readw_(cntlr.status); - if (wait_til_set ^ ((status & bitmask) == 0)) { - if (wait_til_set) - writew_((status & bitmask), cntlr.status); - return status; - } - udelay(10); - } - - printk(BIOS_DEBUG, "ICH SPI: SCIP timeout, read %x, expected %x\n", - status, bitmask); - return -1; -} - -static int spi_ctrlr_xfer(const struct spi_slave *slave, const void *dout, - size_t bytesout, void *din, size_t bytesin) -{ - uint16_t control; - int16_t opcode_index; - int with_address; - int status; - - spi_transaction trans = { - dout, bytesout, - din, bytesin, - 0xff, 0xff, 0 - }; - - /* There has to always at least be an opcode. */ - if (!bytesout || !dout) { - printk(BIOS_DEBUG, "ICH SPI: No opcode for transfer\n"); - return -1; - } - /* Make sure if we read something we have a place to put it. */ - if (bytesin != 0 && !din) { - printk(BIOS_DEBUG, "ICH SPI: Read but no target buffer\n"); - return -1; - } - - if (ich_status_poll(SPIS_SCIP, 0) == -1) - return -1; - - writew_(SPIS_CDS | SPIS_FCERR, cntlr.status); - - spi_setup_type(&trans); - opcode_index = spi_setup_opcode(&trans); - if (opcode_index < 0) - return -1; - with_address = spi_setup_offset(&trans); - if (with_address < 0) - return -1; - - if (trans.opcode == SPI_OPCODE_WREN) { - /* - * Treat Write Enable as Atomic Pre-Op if possible - * in order to prevent the Management Engine from - * issuing a transaction between WREN and DATA. - */ - if (!ichspi_lock) - writew_(trans.opcode, cntlr.preop); - return 0; - } - - /* Preset control fields */ - control = SPIC_SCGO | ((opcode_index & 0x07) << 4); - - /* Issue atomic preop cycle if needed */ - if (readw_(cntlr.preop)) - control |= SPIC_ACS; - - if (!trans.bytesout && !trans.bytesin) { - /* SPI addresses are 24 bit only */ - if (with_address) - writel_(trans.offset & 0x00FFFFFF, cntlr.addr); - - /* - * This is a 'no data' command (like Write Enable), its - * bytesout size was 1, decremented to zero while executing - * spi_setup_opcode() above. Tell the chip to send the - * command. - */ - writew_(control, cntlr.control); - - /* wait for the result */ - status = ich_status_poll(SPIS_CDS | SPIS_FCERR, 1); - if (status == -1) - return -1; - - if (status & SPIS_FCERR) { - printk(BIOS_DEBUG, - "ICH SPI: Command transaction error\n"); - return -1; - } - - return 0; - } - - /* - * Check if this is a write command attempting to transfer more bytes - * than the controller can handle. Iterations for writes are not - * supported here because each SPI write command needs to be preceded - * and followed by other SPI commands, and this sequence is controlled - * by the SPI chip driver. - */ - if (trans.bytesout > cntlr.databytes) { - printk(BIOS_DEBUG, "ICH SPI: Too much to write. Does your SPI" - " chip driver use CONTROLLER_PAGE_LIMIT?\n"); - return -1; - } - - /* - * Read or write up to databytes bytes at a time until everything has - * been sent. - */ - while (trans.bytesout || trans.bytesin) { - uint32_t data_length; - - /* SPI addresses are 24 bit only */ - /* http://www.intel.com/content/dam/www/public/us/en/documents/ - * datasheets/pentium-n3520-j2850-celeron-n2920-n2820-n2815- - * n2806-j1850-j1750-datasheet.pdf - */ - writel_(trans.offset & 0x00FFFFFF, cntlr.addr); - - if (trans.bytesout) - data_length = min(trans.bytesout, cntlr.databytes); - else - data_length = min(trans.bytesin, cntlr.databytes); - - /* Program data into FDATA0 to N */ - if (trans.bytesout) { - write_reg(trans.out, cntlr.data, data_length); - spi_use_out(&trans, data_length); - if (with_address) - trans.offset += data_length; - } - - /* Add proper control fields' values */ - control &= ~((cntlr.databytes - 1) << 8); - control |= SPIC_DS; - control |= (data_length - 1) << 8; - - /* write it */ - writew_(control, cntlr.control); - - /* Wait for Cycle Done Status or Flash Cycle Error. */ - status = ich_status_poll(SPIS_CDS | SPIS_FCERR, 1); - if (status == -1) - return -1; - - if (status & SPIS_FCERR) { - printk(BIOS_DEBUG, "ICH SPI: Data transaction error\n"); - return -1; - } - - if (trans.bytesin) { - read_reg(cntlr.data, trans.in, data_length); - spi_use_in(&trans, data_length); - if (with_address) - trans.offset += data_length; - } - } - - /* Clear atomic preop now that xfer is done */ - writew_(0, cntlr.preop); - - return 0; -} - -/* Use first empty Protected Range Register to cover region of flash */ -static int spi_flash_protect(const struct spi_flash *flash, - const struct region *region, - const enum ctrlr_prot_type type) -{ - u32 start = region_offset(region); - u32 end = start + region_sz(region) - 1; - u32 reg; - u32 protect_mask = 0; - int prr; - - /* Find first empty PRR */ - for (prr = 0; prr < SPI_PRR_MAX; prr++) { - reg = SPIBAR32(SPI_PRR(prr)); - if (reg == 0) - break; - } - if (prr >= SPI_PRR_MAX) { - printk(BIOS_ERR, "ERROR: No SPI PRR free!\n"); - return -1; - } - - /* Set protected range base and limit */ - reg = ((end >> SPI_PRR_SHIFT) & SPI_PRR_MASK); - reg <<= SPI_PRR_LIMIT_SHIFT; - reg |= ((start >> SPI_PRR_SHIFT) & SPI_PRR_MASK); - - switch (type) { - case WRITE_PROTECT: - protect_mask |= SPI_PRR_WPE; - break; - case READ_PROTECT: - protect_mask |= SPI_PRR_RPE; - break; - case READ_WRITE_PROTECT: - protect_mask |= (SPI_PRR_RPE | SPI_PRR_WPE); - break; - default: - printk(BIOS_ERR, "ERROR: Seeking invalid protection!\n"); - return -1; - } - - reg |= protect_mask; - - /* Set the PRR register and verify it is protected */ - SPIBAR32(SPI_PRR(prr)) = reg; - reg = SPIBAR32(SPI_PRR(prr)); - if (!(reg & protect_mask)) { - printk(BIOS_ERR, "ERROR: Unable to set SPI PRR %d\n", prr); - return -1; - } - - printk(BIOS_INFO, "%s: PRR %d is enabled for range 0x%08x-0x%08x\n", - __func__, prr, start, end); - return 0; -} - -static int xfer_vectors(const struct spi_slave *slave, - struct spi_op vectors[], size_t count) -{ - return spi_flash_vector_helper(slave, vectors, count, spi_ctrlr_xfer); -} - -static const struct spi_ctrlr spi_ctrlr = { - .xfer_vector = xfer_vectors, - .max_xfer_size = member_size(ich9_spi_regs, fdata), - .flash_protect = spi_flash_protect, -}; - -const struct spi_ctrlr_buses spi_ctrlr_bus_map[] = { - { - .ctrlr = &spi_ctrlr, - .bus_start = 0, - .bus_end = 0, - }, -}; - -const size_t spi_ctrlr_bus_map_count = ARRAY_SIZE(spi_ctrlr_bus_map); From 5efee3a2c28aa7e53074288733632fa06ac66046 Mon Sep 17 00:00:00 2001 From: Arthur Heymans Date: Sun, 13 Oct 2019 23:04:19 +0200 Subject: [PATCH 0083/1242] soc/intel/broadwell: Don't reinitialize SPI after lockdown With the common southbridge SPI code reinitialization after lockdown is not necessary, hence the SMM finalize call becomes a no-op. Change-Id: I4d7c6ba91dc9f0e0ce4e3228fdf859d5f3d5abf4 Signed-off-by: Arthur Heymans Reviewed-on: https://review.coreboot.org/c/coreboot/+/36004 Reviewed-by: Nico Huber Tested-by: build bot (Jenkins) --- src/soc/intel/broadwell/finalize.c | 6 ------ src/soc/intel/broadwell/smihandler.c | 19 ------------------- 2 files changed, 25 deletions(-) diff --git a/src/soc/intel/broadwell/finalize.c b/src/soc/intel/broadwell/finalize.c index 06cc18d67a..10ba1d7c15 100644 --- a/src/soc/intel/broadwell/finalize.c +++ b/src/soc/intel/broadwell/finalize.c @@ -112,12 +112,6 @@ static void broadwell_finalize(void *unused) MCHBAR32(0x6008) = MCHBAR32(0x6008); RCBA32(0x21a4) = RCBA32(0x21a4); - /* Re-init SPI after lockdown */ - spi_init(); - - printk(BIOS_DEBUG, "Finalizing SMM.\n"); - outb(APM_CNT_FINALIZE, APM_CNT); - /* Indicate finalize step with post code */ post_code(POST_OS_BOOT); } diff --git a/src/soc/intel/broadwell/smihandler.c b/src/soc/intel/broadwell/smihandler.c index d37f65a16f..ca99487eb5 100644 --- a/src/soc/intel/broadwell/smihandler.c +++ b/src/soc/intel/broadwell/smihandler.c @@ -312,22 +312,6 @@ static void southbridge_smi_gsmi(void) *ret = gsmi_exec(sub_command, param); } -static void finalize(void) -{ - static int finalize_done; - - if (finalize_done) { - printk(BIOS_DEBUG, "SMM already finalized.\n"); - return; - } - finalize_done = 1; - -#if CONFIG(SPI_FLASH_SMM) - /* Re-init SPI driver to handle locked BAR */ - spi_init(); -#endif -} - static void southbridge_smi_apmc(void) { u8 reg8; @@ -351,9 +335,6 @@ static void southbridge_smi_apmc(void) enable_pm1_control(SCI_EN); printk(BIOS_DEBUG, "SMI#: ACPI enabled.\n"); break; - case APM_CNT_FINALIZE: - finalize(); - break; case APM_CNT_GNVS_UPDATE: if (smm_initialized) { printk(BIOS_DEBUG, From 3c1e986119cdfece27e5bf953576fa01882bb773 Mon Sep 17 00:00:00 2001 From: Arthur Heymans Date: Sun, 13 Oct 2019 22:54:53 +0200 Subject: [PATCH 0084/1242] soc/intel/broadwell: Use common sb code for SPI lockdown configuration Change-Id: I5a8239f4e9e1f9728074ff5452c95d3138965d82 Signed-off-by: Arthur Heymans Reviewed-on: https://review.coreboot.org/c/coreboot/+/36005 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber --- src/soc/intel/broadwell/finalize.c | 13 ++----- src/soc/intel/broadwell/include/soc/spi.h | 41 ----------------------- 2 files changed, 3 insertions(+), 51 deletions(-) diff --git a/src/soc/intel/broadwell/finalize.c b/src/soc/intel/broadwell/finalize.c index 10ba1d7c15..1c5fdb8885 100644 --- a/src/soc/intel/broadwell/finalize.c +++ b/src/soc/intel/broadwell/finalize.c @@ -27,6 +27,7 @@ #include #include #include +#include const struct reg_script system_agent_finalize_script[] = { REG_PCI_OR16(0x50, 1 << 0), /* GGC */ @@ -57,16 +58,6 @@ const struct reg_script system_agent_finalize_script[] = { const struct reg_script pch_finalize_script[] = { #if !CONFIG(SPI_CONSOLE) - /* Set SPI opcode menu */ - REG_MMIO_WRITE16(RCBA_BASE_ADDRESS + SPIBAR_OFFSET + SPIBAR_PREOP, - SPI_OPPREFIX), - REG_MMIO_WRITE16(RCBA_BASE_ADDRESS + SPIBAR_OFFSET + SPIBAR_OPTYPE, - SPI_OPTYPE), - REG_MMIO_WRITE32(RCBA_BASE_ADDRESS + SPIBAR_OFFSET + - SPIBAR_OPMENU_LOWER, SPI_OPMENU_LOWER), - REG_MMIO_WRITE32(RCBA_BASE_ADDRESS + SPIBAR_OFFSET + - SPIBAR_OPMENU_UPPER, SPI_OPMENU_UPPER), - /* Lock SPIBAR */ REG_MMIO_OR32(RCBA_BASE_ADDRESS + SPIBAR_OFFSET + SPIBAR_HSFS, SPIBAR_HSFS_FLOCKDN), @@ -101,6 +92,8 @@ static void broadwell_finalize(void *unused) printk(BIOS_DEBUG, "Finalizing chipset.\n"); reg_script_run_on_dev(sa_dev, system_agent_finalize_script); + + spi_finalize_ops(); reg_script_run_on_dev(PCH_DEV_LPC, pch_finalize_script); /* Lock */ diff --git a/src/soc/intel/broadwell/include/soc/spi.h b/src/soc/intel/broadwell/include/soc/spi.h index f3572570ea..00b8a9542d 100644 --- a/src/soc/intel/broadwell/include/soc/spi.h +++ b/src/soc/intel/broadwell/include/soc/spi.h @@ -30,47 +30,6 @@ #define SPIBAR_FDOC 0xb0 #define SPIBAR_FDOD 0xb4 -#define SPIBAR_PREOP 0x94 -#define SPIBAR_OPTYPE 0x96 -#define SPIBAR_OPMENU_LOWER 0x98 -#define SPIBAR_OPMENU_UPPER 0x9c - -#define SPI_OPMENU_0 0x01 /* WRSR: Write Status Register */ -#define SPI_OPTYPE_0 0x01 /* Write, no address */ - -#define SPI_OPMENU_1 0x02 /* BYPR: Byte Program */ -#define SPI_OPTYPE_1 0x03 /* Write, address required */ - -#define SPI_OPMENU_2 0x03 /* READ: Read Data */ -#define SPI_OPTYPE_2 0x02 /* Read, address required */ - -#define SPI_OPMENU_3 0x05 /* RDSR: Read Status Register */ -#define SPI_OPTYPE_3 0x00 /* Read, no address */ - -#define SPI_OPMENU_4 0x20 /* SE20: Sector Erase 0x20 */ -#define SPI_OPTYPE_4 0x03 /* Write, address required */ - -#define SPI_OPMENU_5 0x9f /* RDID: Read ID */ -#define SPI_OPTYPE_5 0x00 /* Read, no address */ - -#define SPI_OPMENU_6 0xd8 /* BED8: Block Erase 0xd8 */ -#define SPI_OPTYPE_6 0x03 /* Write, address required */ - -#define SPI_OPMENU_7 0x0b /* FAST: Fast Read */ -#define SPI_OPTYPE_7 0x02 /* Read, address required */ - -#define SPI_OPMENU_UPPER ((SPI_OPMENU_7 << 24) | (SPI_OPMENU_6 << 16) | \ - (SPI_OPMENU_5 << 8) | SPI_OPMENU_4) -#define SPI_OPMENU_LOWER ((SPI_OPMENU_3 << 24) | (SPI_OPMENU_2 << 16) | \ - (SPI_OPMENU_1 << 8) | SPI_OPMENU_0) - -#define SPI_OPTYPE ((SPI_OPTYPE_7 << 14) | (SPI_OPTYPE_6 << 12) | \ - (SPI_OPTYPE_5 << 10) | (SPI_OPTYPE_4 << 8) | \ - (SPI_OPTYPE_3 << 6) | (SPI_OPTYPE_2 << 4) | \ - (SPI_OPTYPE_1 << 2) | (SPI_OPTYPE_0)) - -#define SPI_OPPREFIX ((0x50 << 8) | 0x06) /* EWSR and WREN */ - #define SPIBAR_HSFS 0x04 /* SPI hardware sequence status */ #define SPIBAR_HSFS_FLOCKDN (1 << 15)/* Flash Configuration Lock-Down */ From 8256ca0e14e57b17b27a81b16f220c94d728e117 Mon Sep 17 00:00:00 2001 From: Arthur Heymans Date: Mon, 21 Oct 2019 18:47:46 +0200 Subject: [PATCH 0085/1242] soc/intel/braswell: Update microcode before FSP The google FSP Braswell version has broken microcode update code and FSP checks at some point if the installed microcode version is non zero, so coreboot has to update it before calling FSP-T. This is fixed with newer FSP releases by Intel, but doing updates in coreboot won't hurt. Tested with both Intel FSP and google FSP. Change-Id: I3e81329854e823dc66fec191adbed617bb37d649 Signed-off-by: Arthur Heymans Reviewed-on: https://review.coreboot.org/c/coreboot/+/36198 Reviewed-by: Nico Huber Tested-by: build bot (Jenkins) --- src/drivers/intel/fsp1_1/Makefile.inc | 1 + src/drivers/intel/fsp1_1/cache_as_ram.S | 41 +++++++++++++++++++++++++ 2 files changed, 42 insertions(+) diff --git a/src/drivers/intel/fsp1_1/Makefile.inc b/src/drivers/intel/fsp1_1/Makefile.inc index 85c4e0e608..014311897f 100644 --- a/src/drivers/intel/fsp1_1/Makefile.inc +++ b/src/drivers/intel/fsp1_1/Makefile.inc @@ -19,6 +19,7 @@ verstage-$(CONFIG_SEPARATE_VERSTAGE) += verstage.c bootblock-$(CONFIG_USE_GENERIC_FSP_CAR_INC) += cache_as_ram.S bootblock-y += fsp_util.c +bootblock-y += ../../../cpu/intel/microcode/microcode_asm.S romstage-y += car.c romstage-y += fsp_util.c diff --git a/src/drivers/intel/fsp1_1/cache_as_ram.S b/src/drivers/intel/fsp1_1/cache_as_ram.S index ffafe9b4f3..f4638d9c18 100644 --- a/src/drivers/intel/fsp1_1/cache_as_ram.S +++ b/src/drivers/intel/fsp1_1/cache_as_ram.S @@ -11,6 +11,8 @@ * GNU General Public License for more details. */ +#include +#include #include /* @@ -43,6 +45,45 @@ bootblock_pre_c_entry: cache_as_ram: post_code(0x20) + /* Cache the rom and update the microcode */ +cache_rom: + /* Disable cache */ + movl %cr0, %eax + orl $CR0_CacheDisable, %eax + movl %eax, %cr0 + + movl $MTRR_PHYS_BASE(1), %ecx + xorl %edx, %edx + movl $(CACHE_ROM_BASE | MTRR_TYPE_WRPROT), %eax + wrmsr + + movl $MTRR_PHYS_MASK(1), %ecx + rdmsr + movl $(~(CACHE_ROM_SIZE - 1) | MTRR_PHYS_MASK_VALID), %eax + wrmsr + + /* Enable cache */ + movl %cr0, %eax + andl $(~(CR0_CacheDisable | CR0_NoWriteThrough)), %eax + invd + movl %eax, %cr0 + + /* Enable MTRR. */ + movl $MTRR_DEF_TYPE_MSR, %ecx + rdmsr + orl $MTRR_DEF_TYPE_EN, %eax + wrmsr + + /* The Google FSP release for Braswell has broken microcode update + code and FSP needs the installed microcode revision to be non zero. + It is better to have coreboot do it instead of relying on a fragile + blob. */ +update_microcode: + /* put the return address in %esp */ + movl $end_microcode_update, %esp + jmp update_bsp_microcode +end_microcode_update: + /* * Find the FSP binary in cbfs. * Make a fake stack that has the return value back to this code. From 12440ce63e3f96b32311f4ebde4ef0861dbcec02 Mon Sep 17 00:00:00 2001 From: Arthur Heymans Date: Wed, 23 Oct 2019 11:30:22 +0200 Subject: [PATCH 0086/1242] drivers/intel/fsp1_1: Fake microcode update to make FSP happy The FSP loops through microcode updates and at the end checks if the microcode revision is not zero. Since we update the microcode before loading FSP, this is the case and a fake microcode can be passed to the FSP. The advantage is that the Kconfig symbols to specify the location and the size of the microcode blob can be dropped. Change-Id: I63cfb7b19e9795da85566733fb4c1ff989e85d03 Signed-off-by: Arthur Heymans Reviewed-on: https://review.coreboot.org/c/coreboot/+/36255 Reviewed-by: Nico Huber Tested-by: build bot (Jenkins) --- src/drivers/intel/fsp1_1/Kconfig | 13 ------------- src/drivers/intel/fsp1_1/cache_as_ram.S | 23 +++++++++++++++++++++-- src/mainboard/facebook/fbg1701/Kconfig | 10 ---------- src/mainboard/portwell/m107/Kconfig | 10 ---------- 4 files changed, 21 insertions(+), 35 deletions(-) diff --git a/src/drivers/intel/fsp1_1/Kconfig b/src/drivers/intel/fsp1_1/Kconfig index 1d229520b8..5f8f5b5534 100644 --- a/src/drivers/intel/fsp1_1/Kconfig +++ b/src/drivers/intel/fsp1_1/Kconfig @@ -56,19 +56,6 @@ config FSP_LOC value that is set in the FSP binary. If the FSP needs to be moved, rebase the FSP with Intel's BCT (tool). -config CPU_MICROCODE_CBFS_LEN - hex "Microcode update region length in bytes" - default 0x0 - help - The length in bytes of the microcode update region. - -config CPU_MICROCODE_CBFS_LOC - hex "Microcode update base address in CBFS" - default 0x0 - help - The location (base address) in CBFS that contains the microcode update - binary. - config DISPLAY_HOBS bool "Display hand-off-blocks (HOBs)" default n diff --git a/src/drivers/intel/fsp1_1/cache_as_ram.S b/src/drivers/intel/fsp1_1/cache_as_ram.S index f4638d9c18..fea7acb2e2 100644 --- a/src/drivers/intel/fsp1_1/cache_as_ram.S +++ b/src/drivers/intel/fsp1_1/cache_as_ram.S @@ -239,11 +239,30 @@ fake_fsp_stack: .long CONFIG_FSP_LOC /* FSP base address */ CAR_init_params: - .long CONFIG_CPU_MICROCODE_CBFS_LOC /* Microcode Location */ - .long CONFIG_CPU_MICROCODE_CBFS_LEN /* Microcode Length */ + .long fake_microcode /* Microcode Location */ + .long fake_microcode_end - fake_microcode /* Microcode Length */ .long 0xFFFFFFFF - CONFIG_ROM_SIZE + 1 /* Firmware Location */ .long CONFIG_ROM_SIZE /* Firmware Length */ CAR_init_stack: .long CAR_init_done .long CAR_init_params + + /* coreboot updates microcode itself. FSP still needs a pointer + to something that looks like microcode, so provide it with fake + microcode. */ +fake_microcode: +fake_microcode_header_start: + .long 1 /* Header Version */ + .long 1 /* Microcode revision */ + .long 0x10232019 /* Date: Time of writing 23-10-2019 */ + .long 0x00010ff0 /* Sig: (non existing) Family: 0xf, Model: 0x1f, stepping: 0 */ + .long 0 /* Checksum: not checked by FSP, so won't care */ + .long 1 /* Loader Revision */ + .long 1 /* Processor Flags */ + .long fake_microcode_end - fake_microcode_header_end /* Data Size */ + .long fake_microcode_end - fake_microcode /* Total Size */ + .space 12 /* Reserved */ +fake_microcode_header_end: + .space 0x10 /* 16 bytes of empty data */ +fake_microcode_end: diff --git a/src/mainboard/facebook/fbg1701/Kconfig b/src/mainboard/facebook/fbg1701/Kconfig index 3ade727409..41d59ff450 100644 --- a/src/mainboard/facebook/fbg1701/Kconfig +++ b/src/mainboard/facebook/fbg1701/Kconfig @@ -50,16 +50,6 @@ config CBFS_SIZE hex default 0x00600000 -config CPU_MICROCODE_CBFS_LEN - hex - default 0x10C00 - help - This should be updated when the microcode patch changes. - -config CPU_MICROCODE_CBFS_LOC - hex - default 0xFFFE9400 - config MRC_SETTINGS_CACHE_SIZE hex default 0x08000 diff --git a/src/mainboard/portwell/m107/Kconfig b/src/mainboard/portwell/m107/Kconfig index 3ab20f0b77..e5e3ff590a 100644 --- a/src/mainboard/portwell/m107/Kconfig +++ b/src/mainboard/portwell/m107/Kconfig @@ -61,16 +61,6 @@ config CBFS_SIZE hex default 0x00800000 -config CPU_MICROCODE_CBFS_LEN - hex - default 0x10C00 - help - This should be updated when the microcode patch changes. - -config CPU_MICROCODE_CBFS_LOC - hex - default 0xFFFE9400 - config MRC_SETTINGS_CACHE_SIZE hex default 0x08000 From 1b95501fad0b94098a1e6c5be637efaf113dcb88 Mon Sep 17 00:00:00 2001 From: Patrick Rudolph Date: Tue, 5 Nov 2019 08:32:19 +0100 Subject: [PATCH 0087/1242] Documentation: Add some significant 4.11 release notes MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Change-Id: Ia881cfa9382d0b2fa2652696b912030af942b68a Signed-off-by: Patrick Rudolph Reviewed-on: https://review.coreboot.org/c/coreboot/+/36625 Tested-by: build bot (Jenkins) Reviewed-by: Arthur Heymans Reviewed-by: Kyösti Mälkki --- .../releases/coreboot-4.11-relnotes.md | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) diff --git a/Documentation/releases/coreboot-4.11-relnotes.md b/Documentation/releases/coreboot-4.11-relnotes.md index 7dd99a3522..38299c13a6 100644 --- a/Documentation/releases/coreboot-4.11-relnotes.md +++ b/Documentation/releases/coreboot-4.11-relnotes.md @@ -40,3 +40,22 @@ removed soon after release. Significant refactoring has bee done to achieve some consistency across platforms and to reduce code duplication. + +### Added VBOOT support to the following platforms: +* intel/gm45 +* intel/nehalem + +### Moved the following platforms to C_ENVIRONMENT_BOOTBLOCK: +* intel/gm45 +* intel/nehalem +* intel/braswell + +### Other +* Did cleanups around TSC timer +* Improved automatic VR configuration on SKL/KBL +* Filled additional fields in SMBIOS type 4 +* Removed magic value replay from Intel Nehalem/ibexpeak code base +* Added OpenSBI on RISCV platforms +* Did more preparations for Intel TXT support +* Did more preparations for x86_64 stage support +* Added SSDT generator for arbitrary SuperIO chips based on devicetree.cb From bc2f9a30f3a61e3d02baf7abcc5440407035f354 Mon Sep 17 00:00:00 2001 From: Changqi Hu Date: Fri, 8 Nov 2019 18:24:17 +0800 Subject: [PATCH 0088/1242] libpayload: usbmsc: update return value of CSW transfer When the first CSW transfer failed, get_csw function will retry CSW transfer again, but the return value is not updated. Change-Id: I289916baa08d0a189d659164a0002347f6f435db Signed-off-by: Changqi Hu Reviewed-on: https://review.coreboot.org/c/coreboot/+/36678 Tested-by: build bot (Jenkins) Reviewed-by: Hung-Te Lin Reviewed-by: Julius Werner --- payloads/libpayload/drivers/usb/usbmsc.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) mode change 100644 => 100755 payloads/libpayload/drivers/usb/usbmsc.c diff --git a/payloads/libpayload/drivers/usb/usbmsc.c b/payloads/libpayload/drivers/usb/usbmsc.c old mode 100644 new mode 100755 index 2412e99af3..d8b7bcea6e --- a/payloads/libpayload/drivers/usb/usbmsc.c +++ b/payloads/libpayload/drivers/usb/usbmsc.c @@ -232,9 +232,9 @@ get_csw (endpoint_t *ep, csw_t *csw) if (ret < 0) { clear_stall (ep); - if (ctrlr->bulk (ep, sizeof (csw_t), (u8 *) csw, 1) < 0) { + ret = ctrlr->bulk (ep, sizeof (csw_t), (u8 *) csw, 1); + if (ret < 0) return reset_transport (ep->dev); - } } if (ret != sizeof(csw_t) || csw->dCSWTag != tag || csw->dCSWSignature != csw_signature) { From 8f22136c051f04ef0102fd468ba01a0f10f1a37c Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Michael=20Niew=C3=B6hner?= Date: Fri, 8 Nov 2019 22:02:02 +0100 Subject: [PATCH 0089/1242] include/device: add pci mmio cfg address helpers MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add helpers for getting the pci mmio cfg address for a register. Change-Id: Ie6fe22cacc7241a51d47cbe9fc64f30fa49d5a80 Signed-off-by: Michael Niewöhner Reviewed-on: https://review.coreboot.org/c/coreboot/+/36686 Reviewed-by: Aaron Durbin Tested-by: build bot (Jenkins) --- src/include/device/pci_mmio_cfg.h | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) diff --git a/src/include/device/pci_mmio_cfg.h b/src/include/device/pci_mmio_cfg.h index e3c5fe4873..8f26ff29b0 100644 --- a/src/include/device/pci_mmio_cfg.h +++ b/src/include/device/pci_mmio_cfg.h @@ -86,6 +86,24 @@ void pci_mmio_write_config32(pci_devfn_t dev, uint16_t reg, uint32_t value) pcicfg(dev)->reg32[reg / sizeof(uint32_t)] = value; } +static __always_inline +uint8_t *pci_mmio_config8_addr(pci_devfn_t dev, uint16_t reg) +{ + return (uint8_t *)&pcicfg(dev)->reg8[reg]; +} + +static __always_inline +uint16_t *pci_mmio_config16_addr(pci_devfn_t dev, uint16_t reg) +{ + return (uint16_t *)&pcicfg(dev)->reg16[reg / sizeof(uint16_t)]; +} + +static __always_inline +uint32_t *pci_mmio_config32_addr(pci_devfn_t dev, uint16_t reg) +{ + return (uint32_t *)&pcicfg(dev)->reg32[reg / sizeof(uint32_t)]; +} + #endif /* !defined(__ROMCC__) */ #if CONFIG(MMCONF_SUPPORT) From 28552095d8a4eee588923a11c3f3921a2492b140 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Michael=20Niew=C3=B6hner?= Date: Sat, 2 Nov 2019 12:12:36 +0100 Subject: [PATCH 0090/1242] soc/intel/common: pmclib: add API to get ETR register address MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add a new API to get the ETR register address. Change-Id: I706f3e220d639a6133625e3cb7267f7009006af2 Signed-off-by: Michael Niewöhner Reviewed-on: https://review.coreboot.org/c/coreboot/+/36565 Reviewed-by: Aaron Durbin Tested-by: build bot (Jenkins) --- src/soc/intel/common/block/include/intelblocks/pmclib.h | 3 +++ 1 file changed, 3 insertions(+) diff --git a/src/soc/intel/common/block/include/intelblocks/pmclib.h b/src/soc/intel/common/block/include/intelblocks/pmclib.h index caf21f0ca6..7cc501df7e 100644 --- a/src/soc/intel/common/block/include/intelblocks/pmclib.h +++ b/src/soc/intel/common/block/include/intelblocks/pmclib.h @@ -169,6 +169,9 @@ void pmc_gpe_init(void); /* Returns PMC base address */ uintptr_t soc_read_pmc_base(void); +/* Returns pointer to the ETR register */ +uint32_t *soc_pmc_etr_addr(void); + /* * This function returns array of string which represents * names for the SMI status register bits. Size of the array is From b4d960b65aa126d4534189672322ec62dcd87bde Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Michael=20Niew=C3=B6hner?= Date: Sat, 2 Nov 2019 12:14:06 +0100 Subject: [PATCH 0091/1242] soc/intel/apollolake: add soc implementation for ETR address API MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add soc implementation for the new ETR address API. Change-Id: I1832f5f14055fc3dbb502289035130ca7a5d6d33 Signed-off-by: Michael Niewöhner Reviewed-on: https://review.coreboot.org/c/coreboot/+/36566 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin --- src/soc/intel/apollolake/pmutil.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/src/soc/intel/apollolake/pmutil.c b/src/soc/intel/apollolake/pmutil.c index 23e9732e91..559adad405 100644 --- a/src/soc/intel/apollolake/pmutil.c +++ b/src/soc/intel/apollolake/pmutil.c @@ -49,6 +49,11 @@ uintptr_t soc_read_pmc_base(void) return read_pmc_mmio_bar(); } +uint32_t *soc_pmc_etr_addr(void) +{ + return (uint32_t *)(soc_read_pmc_base() + ETR); +} + const char *const *soc_smi_sts_array(size_t *a) { static const char *const smi_sts_bits[] = { From 93d215cb05a05464fef14f26f638341da2ce3d59 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Michael=20Niew=C3=B6hner?= Date: Sat, 2 Nov 2019 12:14:06 +0100 Subject: [PATCH 0092/1242] soc/intel/cannonlake: add soc implementation for ETR address API MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add soc implementation for the new ETR address API. Change-Id: Ifc128099185a2c40ec3e7c5f84fcc42227c93f28 Signed-off-by: Michael Niewöhner Reviewed-on: https://review.coreboot.org/c/coreboot/+/36567 Reviewed-by: Aaron Durbin Tested-by: build bot (Jenkins) --- src/soc/intel/cannonlake/pmutil.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/src/soc/intel/cannonlake/pmutil.c b/src/soc/intel/cannonlake/pmutil.c index a543861406..428a89fe4b 100644 --- a/src/soc/intel/cannonlake/pmutil.c +++ b/src/soc/intel/cannonlake/pmutil.c @@ -172,6 +172,11 @@ uintptr_t soc_read_pmc_base(void) return (uintptr_t)pmc_mmio_regs(); } +uint32_t *soc_pmc_etr_addr(void) +{ + return (uint32_t *)(soc_read_pmc_base() + ETR); +} + void soc_get_gpi_gpe_configs(uint8_t *dw0, uint8_t *dw1, uint8_t *dw2) { DEVTREE_CONST struct soc_intel_cannonlake_config *config; From e919390f4735a762234630ab7e0807c14de45421 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Michael=20Niew=C3=B6hner?= Date: Sat, 2 Nov 2019 12:14:06 +0100 Subject: [PATCH 0093/1242] soc/intel/icelake: add soc implementation for ETR address API MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add soc implementation for the new ETR address API. Change-Id: I8383a60c2c4988948ab8b3e9a54330269d217868 Signed-off-by: Michael Niewöhner Reviewed-on: https://review.coreboot.org/c/coreboot/+/36568 Reviewed-by: Aaron Durbin Tested-by: build bot (Jenkins) --- src/soc/intel/icelake/pmutil.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/src/soc/intel/icelake/pmutil.c b/src/soc/intel/icelake/pmutil.c index c20da5018a..8efd426606 100644 --- a/src/soc/intel/icelake/pmutil.c +++ b/src/soc/intel/icelake/pmutil.c @@ -170,6 +170,11 @@ uintptr_t soc_read_pmc_base(void) return (uintptr_t)pmc_mmio_regs(); } +uint32_t *soc_pmc_etr_addr(void) +{ + return (uint32_t *)(soc_read_pmc_base() + ETR); +} + void soc_get_gpi_gpe_configs(uint8_t *dw0, uint8_t *dw1, uint8_t *dw2) { DEVTREE_CONST struct soc_intel_icelake_config *config; From f0564a9c44b79e9bfb1001f887348a653f7b7d56 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Michael=20Niew=C3=B6hner?= Date: Sun, 3 Nov 2019 10:26:04 +0100 Subject: [PATCH 0094/1242] include: introduce update* for mmio operations MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Introduce update* as equivalent of pci_update* for mmio operations. Change-Id: I9f188d586c09ee9f1e17290563f68970603204fb Signed-off-by: Michael Niewöhner Reviewed-on: https://review.coreboot.org/c/coreboot/+/36596 Reviewed-by: Aaron Durbin Tested-by: build bot (Jenkins) --- src/include/mmio.h | 45 +++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 45 insertions(+) create mode 100644 src/include/mmio.h diff --git a/src/include/mmio.h b/src/include/mmio.h new file mode 100644 index 0000000000..4f2c806cac --- /dev/null +++ b/src/include/mmio.h @@ -0,0 +1,45 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* + * mmio.h provides update*() as well as read/write*() from arch/mmio.h + */ + +#ifndef __MMIO_H__ +#define __MMIO_H__ + +#include +#include + +static __always_inline void update8(volatile void *addr, uint8_t mask, uint8_t or) +{ + uint8_t reg = read8(addr); + reg = (reg & mask) | or; + write8(addr, reg); +} + +static __always_inline void update16(volatile void *addr, uint16_t mask, uint16_t or) +{ + uint16_t reg = read16(addr); + reg = (reg & mask) | or; + write16(addr, reg); +} + +static __always_inline void update32(volatile void *addr, uint32_t mask, uint32_t or) +{ + uint32_t reg = read32(addr); + reg = (reg & mask) | or; + write32(addr, reg); +} + +#endif /* __MMIO_H__ */ From b1ea53d846b865d5fa1332fb2e31d0f2865a7fc0 Mon Sep 17 00:00:00 2001 From: Aaron Durbin Date: Fri, 8 Nov 2019 09:51:15 -0700 Subject: [PATCH 0095/1242] region: add rdev_chain_full() Instead of open coding an offset of 0 and querying the size of a region device provide a rdev_chain_full() helper function that does that for the caller. For the existing users that match this pattern convert them to using rdev_chain_full(). Change-Id: Ie316790a8a5b16a7f7e22f86f58bd2e633c19450 Signed-off-by: Aaron Durbin Reviewed-on: https://review.coreboot.org/c/coreboot/+/36683 Reviewed-by: Julius Werner Tested-by: build bot (Jenkins) --- src/commonlib/include/commonlib/cbfs.h | 5 ++--- src/commonlib/include/commonlib/region.h | 8 +++++++- src/lib/fmap.c | 3 +-- src/lib/region_file.c | 2 +- 4 files changed, 11 insertions(+), 7 deletions(-) diff --git a/src/commonlib/include/commonlib/cbfs.h b/src/commonlib/include/commonlib/cbfs.h index cadc8c92cc..b0aa9d3ddb 100644 --- a/src/commonlib/include/commonlib/cbfs.h +++ b/src/commonlib/include/commonlib/cbfs.h @@ -32,14 +32,13 @@ int cbfs_locate(struct cbfsf *fh, const struct region_device *cbfs, static inline void cbfs_file_data(struct region_device *data, const struct cbfsf *file) { - rdev_chain(data, &file->data, 0, region_device_sz(&file->data)); + rdev_chain_full(data, &file->data); } static inline void cbfs_file_metadata(struct region_device *metadata, const struct cbfsf *file) { - rdev_chain(metadata, &file->metadata, 0, - region_device_sz(&file->metadata)); + rdev_chain_full(metadata, &file->metadata); } /* diff --git a/src/commonlib/include/commonlib/region.h b/src/commonlib/include/commonlib/region.h index dca12dc741..f27a494d39 100644 --- a/src/commonlib/include/commonlib/region.h +++ b/src/commonlib/include/commonlib/region.h @@ -73,7 +73,6 @@ ssize_t rdev_eraseat(const struct region_device *rd, size_t offset, int rdev_chain(struct region_device *child, const struct region_device *parent, size_t offset, size_t size); - /* A region_device operations. */ struct region_device_ops { void *(*mmap)(const struct region_device *, size_t, size_t); @@ -145,6 +144,13 @@ static inline void *rdev_mmap_full(const struct region_device *rd) return rdev_mmap(rd, 0, region_device_sz(rd)); } +static inline int rdev_chain_full(struct region_device *child, + const struct region_device *parent) +{ + /* Chain full size of parent. */ + return rdev_chain(child, parent, 0, region_device_sz(parent)); +} + /* * Compute relative offset of the child (c) w.r.t. the parent (p). Returns < 0 * when child is not within the parent's region. diff --git a/src/lib/fmap.c b/src/lib/fmap.c index a427102210..f3ff071766 100644 --- a/src/lib/fmap.c +++ b/src/lib/fmap.c @@ -49,8 +49,7 @@ static int find_fmap_directory(struct region_device *fmrd) cache = car_get_var_ptr(&fmap_cache); if (region_device_sz(&cache->rdev)) - return rdev_chain(fmrd, &cache->rdev, 0, - region_device_sz(&cache->rdev)); + return rdev_chain_full(fmrd, &cache->rdev); } boot_device_init(); diff --git a/src/lib/region_file.c b/src/lib/region_file.c index e42c2afd1e..05d619c9a4 100644 --- a/src/lib/region_file.c +++ b/src/lib/region_file.c @@ -208,7 +208,7 @@ int region_file_init(struct region_file *f, const struct region_device *p) f->slot = RF_FATAL; /* Keep parent around for accessing data later. */ - if (rdev_chain(&f->rdev, p, 0, region_device_sz(p))) + if (rdev_chain_full(&f->rdev, p)) return -1; if (rdev_readat(p, &mb, 0, sizeof(mb)) < 0) { From 56aeae0400df8843b62bea85d0dbe27aaf0be325 Mon Sep 17 00:00:00 2001 From: Aaron Durbin Date: Fri, 8 Nov 2019 14:37:58 -0700 Subject: [PATCH 0096/1242] region: publicize region_end() and add region_device_end() Provide region_device_end() and make region_end() publically available for use to match a pattern of open coding the offset + size calculation for both struct region and struct region_device. Apply the use of the helpers where the usage matches in the code. Change-Id: Iaef5d007eef9a77f7f33b0e89298abef0197352d Signed-off-by: Aaron Durbin Reviewed-on: https://review.coreboot.org/c/coreboot/+/36689 Reviewed-by: Julius Werner Tested-by: build bot (Jenkins) --- src/commonlib/include/commonlib/region.h | 10 ++++++++++ src/commonlib/region.c | 5 ----- src/drivers/spi/winbond.c | 9 +++------ 3 files changed, 13 insertions(+), 11 deletions(-) diff --git a/src/commonlib/include/commonlib/region.h b/src/commonlib/include/commonlib/region.h index f27a494d39..39db1bb627 100644 --- a/src/commonlib/include/commonlib/region.h +++ b/src/commonlib/include/commonlib/region.h @@ -122,6 +122,11 @@ static inline size_t region_sz(const struct region *r) return r->size; } +static inline size_t region_end(const struct region *r) +{ + return region_offset(r) + region_sz(r); +} + static inline const struct region *region_device_region( const struct region_device *rdev) { @@ -138,6 +143,11 @@ static inline size_t region_device_offset(const struct region_device *rdev) return region_offset(region_device_region(rdev)); } +static inline size_t region_device_end(const struct region_device *rdev) +{ + return region_end(region_device_region(rdev)); +} + /* Memory map entire region device. Same semantics as rdev_mmap() above. */ static inline void *rdev_mmap_full(const struct region_device *rd) { diff --git a/src/commonlib/region.c b/src/commonlib/region.c index ca7b6efe4b..4a7e285747 100644 --- a/src/commonlib/region.c +++ b/src/commonlib/region.c @@ -15,11 +15,6 @@ #include #include -static inline size_t region_end(const struct region *r) -{ - return region_sz(r) + region_offset(r); -} - int region_is_subregion(const struct region *p, const struct region *c) { if (region_offset(c) < region_offset(p)) diff --git a/src/drivers/spi/winbond.c b/src/drivers/spi/winbond.c index 00a7bf90cd..fa9140ec01 100644 --- a/src/drivers/spi/winbond.c +++ b/src/drivers/spi/winbond.c @@ -431,8 +431,7 @@ static int winbond_get_write_protection(const struct spi_flash *flash, } printk(BIOS_DEBUG, "WINBOND: flash protected range 0x%08zx-0x%08zx\n", - region_offset(&wp_region), - region_offset(&wp_region) + region_sz(&wp_region)); + region_offset(&wp_region), region_end(&wp_region)); return region_is_subregion(&wp_region, region); } @@ -562,8 +561,7 @@ winbond_set_write_protection(const struct spi_flash *flash, int ret; /* Need to touch TOP or BOTTOM */ - if (region_offset(region) != 0 && - (region_offset(region) + region_sz(region)) != flash->size) + if (region_offset(region) != 0 && region_end(region) != flash->size) return -1; params = (const struct winbond_spi_flash_params *)flash->driver_private; @@ -654,8 +652,7 @@ winbond_set_write_protection(const struct spi_flash *flash, return ret; printk(BIOS_DEBUG, "WINBOND: write-protection set to range " - "0x%08zx-0x%08zx\n", region_offset(region), - region_offset(region) + region_sz(region)); + "0x%08zx-0x%08zx\n", region_offset(region), region_end(region)); return ret; } From 5c7b74a22bd69e5f41380eba1a3b3be61512d24d Mon Sep 17 00:00:00 2001 From: Shelley Chen Date: Wed, 6 Nov 2019 18:11:11 -0800 Subject: [PATCH 0097/1242] Helios: Set the reset delay for Goodix touchscreen to 120ms With the 0.71586+ Goodix FW, we can reduce the reset delay from 500ms to 120ms. We should do the change in coreboot device tree after we ensure Helios DVT build is flashed with 0.71586+ Goodix FW. BUG=b:142316026 BRANCH=None TEST=./util/abuild/abuild -p none -t google/hatch -x -a Change-Id: I000ee4ea84c598b437992f1000f6e5b561cae605 Signed-off-by: Shelley Chen Reviewed-on: https://review.coreboot.org/c/coreboot/+/36655 Tested-by: build bot (Jenkins) Reviewed-by: Philip Chen --- src/mainboard/google/hatch/variants/hatch/overridetree.cb | 2 +- src/mainboard/google/hatch/variants/helios/overridetree.cb | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/src/mainboard/google/hatch/variants/hatch/overridetree.cb b/src/mainboard/google/hatch/variants/hatch/overridetree.cb index bc6aa11cab..75c14efad5 100644 --- a/src/mainboard/google/hatch/variants/hatch/overridetree.cb +++ b/src/mainboard/google/hatch/variants/hatch/overridetree.cb @@ -98,7 +98,7 @@ chip soc/intel/cannonlake register "generic.probed" = "1" register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D15)" - register "generic.reset_delay_ms" = "500" + register "generic.reset_delay_ms" = "120" register "generic.reset_off_delay_ms" = "3" register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D9)" register "generic.enable_delay_ms" = "12" diff --git a/src/mainboard/google/hatch/variants/helios/overridetree.cb b/src/mainboard/google/hatch/variants/helios/overridetree.cb index 04bf6c12af..94639dcabe 100644 --- a/src/mainboard/google/hatch/variants/helios/overridetree.cb +++ b/src/mainboard/google/hatch/variants/helios/overridetree.cb @@ -103,7 +103,7 @@ chip soc/intel/cannonlake register "generic.probed" = "1" register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D15)" - register "generic.reset_delay_ms" = "500" + register "generic.reset_delay_ms" = "120" register "generic.reset_off_delay_ms" = "1" register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D9)" From e396c662c0916a8938cbc0cab4bd5820088e26a4 Mon Sep 17 00:00:00 2001 From: Julius Werner Date: Fri, 8 Nov 2019 22:51:16 -0800 Subject: [PATCH 0098/1242] rockchip/rk3288: Bump verstage size a little more RK3288 is running out of space again. I believe reducing the CBFS cache size this much should be safe. I don't really care to test it either though. We should probably just deprecate that SoC at some point, it's just causing too much pain. Change-Id: Id8f971606a7a183d3e9af8bbb1b353e518ec24c8 Signed-off-by: Julius Werner Reviewed-on: https://review.coreboot.org/c/coreboot/+/36692 Tested-by: build bot (Jenkins) Reviewed-by: Arthur Heymans Reviewed-by: Joel Kitching --- src/soc/rockchip/rk3288/include/soc/memlayout.ld | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/soc/rockchip/rk3288/include/soc/memlayout.ld b/src/soc/rockchip/rk3288/include/soc/memlayout.ld index 6320fadcba..94a672db0c 100644 --- a/src/soc/rockchip/rk3288/include/soc/memlayout.ld +++ b/src/soc/rockchip/rk3288/include/soc/memlayout.ld @@ -33,8 +33,8 @@ SECTIONS BOOTBLOCK(0xFF704004, 20K - 4) PRERAM_CBMEM_CONSOLE(0xFF709000, 2K) VBOOT2_WORK(0xFF709800, 12K) - OVERLAP_VERSTAGE_ROMSTAGE(0xFF70C800, 42K) - PRERAM_CBFS_CACHE(0xFF717000, 1K) + OVERLAP_VERSTAGE_ROMSTAGE(0xFF70C800, 42K + 768) + PRERAM_CBFS_CACHE(0xFF717300, 256) TIMESTAMP(0xFF717400, 0x180) STACK(0xFF717580, 3K - 0x180) SRAM_END(0xFF718000) From 10cfd4d7cfc3196449e3ba80f8d2538e113ef7e8 Mon Sep 17 00:00:00 2001 From: Elyes HAOUAS Date: Sat, 9 Nov 2019 08:05:03 +0100 Subject: [PATCH 0099/1242] mb/{x4x}: Remove unused 'include ' Change-Id: I82f1d4325ea87585137fa81567aa82b80454c704 Signed-off-by: Elyes HAOUAS Reviewed-on: https://review.coreboot.org/c/coreboot/+/36693 Tested-by: build bot (Jenkins) Reviewed-by: Arthur Heymans Reviewed-by: Angel Pons --- src/mainboard/asrock/g41c-gs/romstage.c | 1 - src/mainboard/asus/p5qc/romstage.c | 1 - src/mainboard/asus/p5qpl-am/romstage.c | 1 - src/mainboard/foxconn/g41s-k/romstage.c | 1 - src/mainboard/gigabyte/ga-g41m-es2l/romstage.c | 1 - src/mainboard/intel/dg41wv/romstage.c | 1 - src/mainboard/intel/dg43gt/romstage.c | 1 - src/mainboard/lenovo/thinkcentre_a58/romstage.c | 1 - 8 files changed, 8 deletions(-) diff --git a/src/mainboard/asrock/g41c-gs/romstage.c b/src/mainboard/asrock/g41c-gs/romstage.c index bb7a342d75..57d1ec2c2c 100644 --- a/src/mainboard/asrock/g41c-gs/romstage.c +++ b/src/mainboard/asrock/g41c-gs/romstage.c @@ -19,7 +19,6 @@ #include #include #include -#include #include #include #include diff --git a/src/mainboard/asus/p5qc/romstage.c b/src/mainboard/asus/p5qc/romstage.c index 1477d80ea3..fb30beeffb 100644 --- a/src/mainboard/asus/p5qc/romstage.c +++ b/src/mainboard/asus/p5qc/romstage.c @@ -23,7 +23,6 @@ #include #include #include -#include #define SERIAL_DEV PNP_DEV(0x2e, W83667HG_A_SP1) #define LPC_DEV PCI_DEV(0, 0x1f, 0) diff --git a/src/mainboard/asus/p5qpl-am/romstage.c b/src/mainboard/asus/p5qpl-am/romstage.c index 30480ad3d5..2836bf7941 100644 --- a/src/mainboard/asus/p5qpl-am/romstage.c +++ b/src/mainboard/asus/p5qpl-am/romstage.c @@ -22,7 +22,6 @@ #include #include #include -#include #include #include #include diff --git a/src/mainboard/foxconn/g41s-k/romstage.c b/src/mainboard/foxconn/g41s-k/romstage.c index 0bfbbfe28c..01473c80fc 100644 --- a/src/mainboard/foxconn/g41s-k/romstage.c +++ b/src/mainboard/foxconn/g41s-k/romstage.c @@ -19,7 +19,6 @@ #include #include #include -#include #include #include #include diff --git a/src/mainboard/gigabyte/ga-g41m-es2l/romstage.c b/src/mainboard/gigabyte/ga-g41m-es2l/romstage.c index d4ce9401c1..8ba173eec6 100644 --- a/src/mainboard/gigabyte/ga-g41m-es2l/romstage.c +++ b/src/mainboard/gigabyte/ga-g41m-es2l/romstage.c @@ -25,7 +25,6 @@ #include #include #include -#include #define SERIAL_DEV PNP_DEV(0x2e, IT8718F_SP1) #define GPIO_DEV PNP_DEV(0x2e, IT8718F_GPIO) diff --git a/src/mainboard/intel/dg41wv/romstage.c b/src/mainboard/intel/dg41wv/romstage.c index 81d50670e9..a6969ad4d2 100644 --- a/src/mainboard/intel/dg41wv/romstage.c +++ b/src/mainboard/intel/dg41wv/romstage.c @@ -19,7 +19,6 @@ #include #include #include -#include #include #include #include diff --git a/src/mainboard/intel/dg43gt/romstage.c b/src/mainboard/intel/dg43gt/romstage.c index 8207638a5b..018df1bedf 100644 --- a/src/mainboard/intel/dg43gt/romstage.c +++ b/src/mainboard/intel/dg43gt/romstage.c @@ -23,7 +23,6 @@ #include #include #include -#include #define SERIAL_DEV PNP_DEV(0x2e, W83627DHG_SP1) #define LPC_DEV PCI_DEV(0, 0x1f, 0) diff --git a/src/mainboard/lenovo/thinkcentre_a58/romstage.c b/src/mainboard/lenovo/thinkcentre_a58/romstage.c index cb84ce07f5..10889a9286 100644 --- a/src/mainboard/lenovo/thinkcentre_a58/romstage.c +++ b/src/mainboard/lenovo/thinkcentre_a58/romstage.c @@ -23,7 +23,6 @@ #include #include #include -#include #define SERIAL_DEV PNP_DEV(0x2e, SMSCSUPERIO_SP1) #define LPC_DEV PCI_DEV(0, 0x1f, 0) From aabc215962a18477fd383da63aef1b147fcee718 Mon Sep 17 00:00:00 2001 From: Elyes HAOUAS Date: Sat, 9 Nov 2019 09:31:38 +0100 Subject: [PATCH 0100/1242] src/mb: Remove redundant message befor 'system_reset()' Change-Id: Id5a6b7c731b65aafbb88a7c52a1f434dbab41f4a Signed-off-by: Elyes HAOUAS Reviewed-on: https://review.coreboot.org/c/coreboot/+/36694 Reviewed-by: Arthur Heymans Tested-by: build bot (Jenkins) --- src/mainboard/getac/p470/romstage.c | 1 - src/mainboard/ibase/mb899/romstage.c | 1 - src/mainboard/kontron/986lcd-m/romstage.c | 1 - src/mainboard/lenovo/t60/romstage.c | 1 - src/mainboard/roda/rk886ex/romstage.c | 1 - 5 files changed, 5 deletions(-) diff --git a/src/mainboard/getac/p470/romstage.c b/src/mainboard/getac/p470/romstage.c index dfc97d814c..6b5de90e74 100644 --- a/src/mainboard/getac/p470/romstage.c +++ b/src/mainboard/getac/p470/romstage.c @@ -213,7 +213,6 @@ void mainboard_romstage_entry(void) console_init(); if (MCHBAR16(SSKPD) == 0xCAFE) { - printk(BIOS_DEBUG, "soft reset detected, rebooting properly\n"); system_reset(); } diff --git a/src/mainboard/ibase/mb899/romstage.c b/src/mainboard/ibase/mb899/romstage.c index f1ecc1f040..3b17e3b634 100644 --- a/src/mainboard/ibase/mb899/romstage.c +++ b/src/mainboard/ibase/mb899/romstage.c @@ -185,7 +185,6 @@ void mainboard_romstage_entry(void) console_init(); if (MCHBAR16(SSKPD) == 0xCAFE) { - printk(BIOS_DEBUG, "soft reset detected, rebooting properly\n"); system_reset(); } diff --git a/src/mainboard/kontron/986lcd-m/romstage.c b/src/mainboard/kontron/986lcd-m/romstage.c index 189406225c..229e3594c8 100644 --- a/src/mainboard/kontron/986lcd-m/romstage.c +++ b/src/mainboard/kontron/986lcd-m/romstage.c @@ -228,7 +228,6 @@ void mainboard_romstage_entry(void) console_init(); if (MCHBAR16(SSKPD) == 0xCAFE) { - printk(BIOS_DEBUG, "soft reset detected, rebooting properly\n"); system_reset(); } diff --git a/src/mainboard/lenovo/t60/romstage.c b/src/mainboard/lenovo/t60/romstage.c index 756ebc8eeb..b003de8926 100644 --- a/src/mainboard/lenovo/t60/romstage.c +++ b/src/mainboard/lenovo/t60/romstage.c @@ -163,7 +163,6 @@ void mainboard_romstage_entry(void) console_init(); if (MCHBAR16(SSKPD) == 0xCAFE) { - printk(BIOS_DEBUG, "soft reset detected, rebooting properly\n"); system_reset(); } diff --git a/src/mainboard/roda/rk886ex/romstage.c b/src/mainboard/roda/rk886ex/romstage.c index 19a0e4a5a1..e7724e4485 100644 --- a/src/mainboard/roda/rk886ex/romstage.c +++ b/src/mainboard/roda/rk886ex/romstage.c @@ -184,7 +184,6 @@ void mainboard_romstage_entry(void) console_init(); if (MCHBAR16(SSKPD) == 0xCAFE) { - printk(BIOS_DEBUG, "soft reset detected, rebooting properly\n"); system_reset(); } From ca7f93d5674535da84d5fb216328d95b58ecc3aa Mon Sep 17 00:00:00 2001 From: Elyes HAOUAS Date: Sat, 9 Nov 2019 16:50:47 +0100 Subject: [PATCH 0101/1242] fsp{rangeley,baytrail,broadwell_de}: Fix dead assignment Change-Id: I0f02a4508b78cdb0706df6f288138a9db54e229e Signed-off-by: Elyes HAOUAS Reviewed-on: https://review.coreboot.org/c/coreboot/+/36703 Reviewed-by: Nico Huber Tested-by: build bot (Jenkins) --- src/northbridge/intel/fsp_rangeley/northbridge.c | 6 ++---- src/soc/intel/fsp_baytrail/northcluster.c | 6 ++---- src/soc/intel/fsp_broadwell_de/northcluster.c | 6 ++---- 3 files changed, 6 insertions(+), 12 deletions(-) diff --git a/src/northbridge/intel/fsp_rangeley/northbridge.c b/src/northbridge/intel/fsp_rangeley/northbridge.c index 63f2068725..4ebbe7ec15 100644 --- a/src/northbridge/intel/fsp_rangeley/northbridge.c +++ b/src/northbridge/intel/fsp_rangeley/northbridge.c @@ -76,7 +76,7 @@ static int get_pcie_bar(u32 *base) } -static int add_fixed_resources(struct device *dev, int index) +static void add_fixed_resources(struct device *dev, int index) { struct resource *resource; @@ -87,8 +87,6 @@ static int add_fixed_resources(struct device *dev, int index) IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED; mmio_resource(dev, index++, legacy_hole_base_k, legacy_hole_size_k); - - return index; } static void mc_add_dram_resources(struct device *dev) @@ -133,7 +131,7 @@ static void mc_add_dram_resources(struct device *dev) printk(BIOS_INFO, "Available memory above 4GB: %lluM\n", (bmbound_hi - 0x100000000) >> 20); } - index = add_fixed_resources(dev, index); + add_fixed_resources(dev, index); } static void mc_read_resources(struct device *dev) diff --git a/src/soc/intel/fsp_baytrail/northcluster.c b/src/soc/intel/fsp_baytrail/northcluster.c index 797039a27e..474ba84890 100644 --- a/src/soc/intel/fsp_baytrail/northcluster.c +++ b/src/soc/intel/fsp_baytrail/northcluster.c @@ -102,7 +102,7 @@ static int get_pcie_bar(u32 *base) } -static int add_fixed_resources(struct device *dev, int index) +static void add_fixed_resources(struct device *dev, int index) { struct resource *resource; @@ -113,8 +113,6 @@ static int add_fixed_resources(struct device *dev, int index) IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED; mmio_resource(dev, index++, legacy_hole_base_k, legacy_hole_size_k); - - return index; } static void mc_add_dram_resources(struct device *dev) @@ -157,7 +155,7 @@ static void mc_add_dram_resources(struct device *dev) printk(BIOS_INFO, "Available memory above 4GB: %lluM\n", highmem_size >> 20); - index = add_fixed_resources(dev, index); + add_fixed_resources(dev, index); } static void nc_read_resources(struct device *dev) diff --git a/src/soc/intel/fsp_broadwell_de/northcluster.c b/src/soc/intel/fsp_broadwell_de/northcluster.c index 2e27d37b16..a630c1bba4 100644 --- a/src/soc/intel/fsp_broadwell_de/northcluster.c +++ b/src/soc/intel/fsp_broadwell_de/northcluster.c @@ -30,7 +30,7 @@ static const int legacy_hole_base_k = 0xa0000 / 1024; static const int legacy_hole_size_k = 384; -static int add_fixed_resources(struct device *dev, int index) +static void add_fixed_resources(struct device *dev, int index) { struct resource *resource; u32 pcie_config_base, pcie_config_size; @@ -52,8 +52,6 @@ static int add_fixed_resources(struct device *dev, int index) IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED; mmio_resource(dev, index++, legacy_hole_base_k, legacy_hole_size_k); - - return index; } static void mc_add_dram_resources(struct device *dev) @@ -117,7 +115,7 @@ static void mc_add_dram_resources(struct device *dev) printk(BIOS_INFO, "Available memory above 4GB: %lluM\n", highmem_size >> 20); - index = add_fixed_resources(dev, index); + add_fixed_resources(dev, index); } static void nc_read_resources(struct device *dev) From 19825e8e375d1c4d0448e7ffe3bb2e2c230c9eea Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ky=C3=B6sti=20M=C3=A4lkki?= Date: Sat, 9 Nov 2019 13:23:15 +0200 Subject: [PATCH 0102/1242] Documentation: Add some significant 4.11 release notes MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Change-Id: I0f9a5afe85068e6ef2a0b0d088557b0dd1e5bd91 Signed-off-by: Kyösti Mälkki Reviewed-on: https://review.coreboot.org/c/coreboot/+/36697 Tested-by: build bot (Jenkins) Reviewed-by: Arthur Heymans --- Documentation/releases/coreboot-4.11-relnotes.md | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/Documentation/releases/coreboot-4.11-relnotes.md b/Documentation/releases/coreboot-4.11-relnotes.md index 38299c13a6..d4fed06e68 100644 --- a/Documentation/releases/coreboot-4.11-relnotes.md +++ b/Documentation/releases/coreboot-4.11-relnotes.md @@ -30,6 +30,15 @@ Preprocessor use of `defined(__PRE_RAM_)` have been mostly replaced with The remaining cases and `-D__PRE_RAM__` are to be removed soon after release. +### `__BOOTBLOCK__` et.al. are converted + +This applies to all `ENV_xxx` definitions found in ``. + +Write code without preprocessor directives whenever possible, replacing +`#ifdef __BOOTBLOCK__` with `if (ENV_BOOTBLOCK)` + +In cases where preprocessor is needed use `#if ENV_BOOTBLOCK` instead. + ### `CAR_GLOBAL` is removed where possible For all platform code with `NO_CAR_GLOBAL_MIGRATION=y`, any `CAR_GLOBAL` From 45ddb4344f73051855da6d4e87a5ba4b4c66af71 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ky=C3=B6sti=20M=C3=A4lkki?= Date: Sat, 2 Nov 2019 14:12:18 +0200 Subject: [PATCH 0103/1242] console,boot_state: Exclude printk() from reported times MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Use monotonic timer to accumulate the time spent in console code. For bootblock and romstage, only stage total is reported. For ramstage each boot_state is reported individually. Change-Id: Id3998bab553ff803a93257a3f2c7bfea44c31729 Signed-off-by: Kyösti Mälkki Reviewed-on: https://review.coreboot.org/c/coreboot/+/36574 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel Reviewed-by: Nico Huber --- src/arch/x86/postcar_loader.c | 2 ++ src/console/printk.c | 46 +++++++++++++++++++++++++++++++++++ src/include/console/console.h | 7 ++++++ src/lib/hardwaremain.c | 8 ++++++ src/lib/prog_loaders.c | 4 +++ 5 files changed, 67 insertions(+) diff --git a/src/arch/x86/postcar_loader.c b/src/arch/x86/postcar_loader.c index 868b770c18..b53cbf82af 100644 --- a/src/arch/x86/postcar_loader.c +++ b/src/arch/x86/postcar_loader.c @@ -228,6 +228,8 @@ void run_postcar_phase(struct postcar_frame *pcf) /* As postcar exist, it's end of romstage here */ timestamp_add_now(TS_END_ROMSTAGE); + console_time_report(); + prog_set_arg(&prog, cbmem_top()); prog_run(&prog); diff --git a/src/console/printk.c b/src/console/printk.c index 15c599dce0..4f9f547bc5 100644 --- a/src/console/printk.c +++ b/src/console/printk.c @@ -21,14 +21,56 @@ #include #include #include +#include #if (!defined(__PRE_RAM__) && CONFIG(HAVE_ROMSTAGE_CONSOLE_SPINLOCK)) || !CONFIG(HAVE_ROMSTAGE_CONSOLE_SPINLOCK) DECLARE_SPIN_LOCK(console_lock) #endif +#define TRACK_CONSOLE_TIME (CONFIG(HAVE_MONOTONIC_TIMER) && \ + (ENV_RAMSTAGE || !CONFIG(CAR_GLOBAL_MIGRATION))) + +static struct mono_time mt_start, mt_stop; +static long console_usecs; + +static void console_time_run(void) +{ + if (TRACK_CONSOLE_TIME) + timer_monotonic_get(&mt_start); +} + +static void console_time_stop(void) +{ + if (TRACK_CONSOLE_TIME) { + timer_monotonic_get(&mt_stop); + console_usecs += mono_time_diff_microseconds(&mt_start, &mt_stop); + } +} + +void console_time_report(void) +{ + if (!TRACK_CONSOLE_TIME) + return; + + printk(BIOS_DEBUG, "Accumulated console time in " ENV_STRING " %ld ms\n", + DIV_ROUND_CLOSEST(console_usecs, USECS_PER_MSEC)); +} + +long console_time_get_and_reset(void) +{ + if (!TRACK_CONSOLE_TIME) + return 0; + + long elapsed = console_usecs; + console_usecs = 0; + return elapsed; +} + void do_putchar(unsigned char byte) { + console_time_run(); console_tx_byte(byte); + console_time_stop(); } static void wrap_putchar(unsigned char byte, void *data) @@ -61,6 +103,8 @@ int do_vprintk(int msg_level, const char *fmt, va_list args) spin_lock(&console_lock); #endif + console_time_run(); + if (log_this == CONSOLE_LOG_FAST) { i = vtxprintf(wrap_putchar_cbmemc, fmt, args, NULL); } else { @@ -68,6 +112,8 @@ int do_vprintk(int msg_level, const char *fmt, va_list args) console_tx_flush(); } + console_time_stop(); + #ifdef __PRE_RAM__ #if CONFIG(HAVE_ROMSTAGE_CONSOLE_SPINLOCK) spin_unlock(romstage_console_lock()); diff --git a/src/include/console/console.h b/src/include/console/console.h index 1c2a276af0..607c96862e 100644 --- a/src/include/console/console.h +++ b/src/include/console/console.h @@ -64,6 +64,11 @@ asmlinkage void console_init(void); int console_log_level(int msg_level); void do_putchar(unsigned char byte); +/* Return number of microseconds elapsed from start of stage or the previous + get_and_reset() call. */ +long console_time_get_and_reset(void); +void console_time_report(void); + #define printk(LEVEL, fmt, args...) do_printk(LEVEL, fmt, ##args) #define vprintk(LEVEL, fmt, args) do_vprintk(LEVEL, fmt, args) @@ -87,6 +92,8 @@ static inline int console_log_level(int msg_level) { return 0; } static inline void printk(int LEVEL, const char *fmt, ...) {} static inline void vprintk(int LEVEL, const char *fmt, va_list args) {} static inline void do_putchar(unsigned char byte) {} +static inline long console_time_get_and_reset(void) { return 0; } +static inline void console_time_report(void) {} #endif int do_printk(int msg_level, const char *fmt, ...) diff --git a/src/lib/hardwaremain.c b/src/lib/hardwaremain.c index 51ff330d84..3fcf8829f3 100644 --- a/src/lib/hardwaremain.c +++ b/src/lib/hardwaremain.c @@ -63,6 +63,7 @@ static boot_state_t bs_payload_boot(void *arg); struct boot_state_times { int num_samples; struct mono_time samples[MAX_TIME_SAMPLES]; + long console_usecs[MAX_TIME_SAMPLES]; }; /* The prologue (BS_ON_ENTRY) and epilogue (BS_ON_EXIT) of a state can be @@ -241,6 +242,9 @@ static void bs_sample_time(struct boot_state *state) { struct mono_time *mt; + long console_usecs = console_time_get_and_reset(); + state->times.console_usecs[state->times.num_samples] = console_usecs; + mt = &state->times.samples[state->times.num_samples]; timer_monotonic_get(mt); state->times.num_samples++; @@ -257,6 +261,10 @@ static void bs_report_time(struct boot_state *state) run_time = mono_time_diff_microseconds(&samples[1], &samples[2]); exit_time = mono_time_diff_microseconds(&samples[2], &samples[3]); + entry_time -= state->times.console_usecs[1]; + run_time -= state->times.console_usecs[2]; + exit_time -= state->times.console_usecs[3]; + /* Report with millisecond precision to reduce log diffs. */ entry_time = DIV_ROUND_CLOSEST(entry_time, USECS_PER_MSEC); run_time = DIV_ROUND_CLOSEST(run_time, USECS_PER_MSEC); diff --git a/src/lib/prog_loaders.c b/src/lib/prog_loaders.c index 72c1de1e34..43f4689940 100644 --- a/src/lib/prog_loaders.c +++ b/src/lib/prog_loaders.c @@ -72,6 +72,8 @@ void run_romstage(void) timestamp_add_now(TS_END_COPYROM); + console_time_report(); + prog_run(&romstage); fail: @@ -155,6 +157,8 @@ void run_ramstage(void) timestamp_add_now(TS_END_COPYRAM); + console_time_report(); + /* This overrides the arg fetched from the relocatable module */ prog_set_arg(&ramstage, cbmem_top()); From 97012bd019896c589a4b736f17f5c1ad8f378924 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Michael=20Niew=C3=B6hner?= Date: Mon, 4 Nov 2019 22:07:29 +0100 Subject: [PATCH 0104/1242] soc/intel/apollolake: make use of common cbmem_top_chipset MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This replaces apollolake's own implementation of cbmem_top_chipset and selects the common code one. Change-Id: I11d12a6c8414a98d38be8b0dbf6dc57cd2efc5d6 Signed-off-by: Michael Niewöhner Reviewed-on: https://review.coreboot.org/c/coreboot/+/36618 Reviewed-by: Werner Zeh Reviewed-by: Arthur Heymans Tested-by: build bot (Jenkins) --- src/soc/intel/apollolake/Kconfig | 1 + src/soc/intel/apollolake/Makefile.inc | 4 --- src/soc/intel/apollolake/memmap.c | 35 --------------------------- 3 files changed, 1 insertion(+), 39 deletions(-) delete mode 100644 src/soc/intel/apollolake/memmap.c diff --git a/src/soc/intel/apollolake/Kconfig b/src/soc/intel/apollolake/Kconfig index 026f6da669..cd0c9cd0e8 100644 --- a/src/soc/intel/apollolake/Kconfig +++ b/src/soc/intel/apollolake/Kconfig @@ -84,6 +84,7 @@ config CPU_SPECIFIC_OPTIONS select SOC_INTEL_COMMON_BLOCK_SRAM select SOC_INTEL_COMMON_BLOCK_RTC select SOC_INTEL_COMMON_BLOCK_SA + select SOC_INTEL_COMMON_BLOCK_SA_FSP_TOLUM select SOC_INTEL_COMMON_BLOCK_SCS select SOC_INTEL_COMMON_BLOCK_TIMER select SOC_INTEL_COMMON_BLOCK_TCO diff --git a/src/soc/intel/apollolake/Makefile.inc b/src/soc/intel/apollolake/Makefile.inc index ef81e32abd..24375b3599 100644 --- a/src/soc/intel/apollolake/Makefile.inc +++ b/src/soc/intel/apollolake/Makefile.inc @@ -28,7 +28,6 @@ romstage-y += gspi.c romstage-y += heci.c romstage-y += i2c.c romstage-y += uart.c -romstage-y += memmap.c romstage-y += meminit.c ifeq ($(CONFIG_SOC_INTEL_GLK),y) romstage-y += meminit_util_glk.c @@ -59,7 +58,6 @@ ramstage-y += gspi.c ramstage-y += heci.c ramstage-y += i2c.c ramstage-y += lpc.c -ramstage-y += memmap.c ramstage-y += mmap_boot.c ramstage-y += uart.c ramstage-y += nhlt.c @@ -73,7 +71,6 @@ ramstage-y += xdci.c ramstage-y += sd.c ramstage-y += xhci.c -postcar-y += memmap.c postcar-y += mmap_boot.c postcar-y += spi.c postcar-y += i2c.c @@ -86,7 +83,6 @@ verstage-y += car.c verstage-y += i2c.c verstage-y += gspi.c verstage-y += heci.c -verstage-y += memmap.c verstage-y += mmap_boot.c verstage-y += uart.c verstage-y += pmutil.c diff --git a/src/soc/intel/apollolake/memmap.c b/src/soc/intel/apollolake/memmap.c deleted file mode 100644 index de6a7d1f19..0000000000 --- a/src/soc/intel/apollolake/memmap.c +++ /dev/null @@ -1,35 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2015 Intel Corp. - * (Written by Andrey Petrov for Intel Corp.) - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include - -#include "chip.h" - -void *cbmem_top_chipset(void) -{ - void *tolum = (void *)sa_get_tseg_base(); - - if (!CONFIG(SOC_INTEL_GLK)) - return tolum; - - /* FSP allocates 2x PRMRR Size Memory for alignment */ - tolum -= get_prmrr_size() * 2; - - return tolum; -} From 6754dcda744c7ff7850024b4da1990475b0dfa7f Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Michael=20Niew=C3=B6hner?= Date: Mon, 4 Nov 2019 22:07:29 +0100 Subject: [PATCH 0105/1242] soc/intel/quark: make use of common cbmem_top_chipset MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This replaces quark's own implementation of cbmem_top_chipset and selects the common code one. Change-Id: I445c471b654abfa922b20215e52a2794529be120 Signed-off-by: Michael Niewöhner Reviewed-on: https://review.coreboot.org/c/coreboot/+/36621 Tested-by: build bot (Jenkins) Reviewed-by: Arthur Heymans Reviewed-by: Nico Huber --- src/soc/intel/quark/Kconfig | 2 ++ src/soc/intel/quark/memmap.c | 17 ----------------- 2 files changed, 2 insertions(+), 17 deletions(-) diff --git a/src/soc/intel/quark/Kconfig b/src/soc/intel/quark/Kconfig index 461d230371..6938431728 100644 --- a/src/soc/intel/quark/Kconfig +++ b/src/soc/intel/quark/Kconfig @@ -32,6 +32,8 @@ config CPU_SPECIFIC_OPTIONS select PLATFORM_USES_FSP2_0 select SOC_INTEL_COMMON select SOC_INTEL_COMMON_RESET + select SOC_INTEL_COMMON_BLOCK + select SOC_INTEL_COMMON_BLOCK_SA_FSP_TOLUM select SOC_SETS_MSRS select SPI_FLASH select UART_OVERRIDE_REFCLK diff --git a/src/soc/intel/quark/memmap.c b/src/soc/intel/quark/memmap.c index 9ccaf55a1f..6cd2c9a73c 100644 --- a/src/soc/intel/quark/memmap.c +++ b/src/soc/intel/quark/memmap.c @@ -18,23 +18,6 @@ #include #include -void *cbmem_top_chipset(void) -{ - uint32_t top_of_memory; - - /* Determine the TSEG base */ - top_of_memory = reg_host_bridge_unit_read(QNC_MSG_FSBIC_REG_HSMMC); - top_of_memory &= SMM_START_MASK; - top_of_memory <<= 16; - - /* Reserve 64 KiB for RMU firmware */ - if (top_of_memory) - top_of_memory -= 0x10000; - - /* Return the top of memory */ - return (void *)top_of_memory; -} - void fill_postcar_frame(struct postcar_frame *pcf) { uintptr_t top_of_ram; From 0dc87ef90db6944a1854c5f9a6e932903ebad5a4 Mon Sep 17 00:00:00 2001 From: Werner Zeh Date: Tue, 22 Oct 2019 15:08:19 +0200 Subject: [PATCH 0106/1242] mb/siemens/mc_apl6: Add new mainboard based on mc_apl3 This patch adds a new mainboard variant called mc_apl6 which is based on mc_apl3. So far only the names have been adjusted with no further changes. Following commits will introduce the needed changes for this mainboard variant. Change-Id: Ic935f6cc1f037947b2c167696d40da8309e4d4f0 Signed-off-by: Werner Zeh Reviewed-on: https://review.coreboot.org/c/coreboot/+/36668 Tested-by: build bot (Jenkins) Reviewed-by: Mario Scheithauer --- src/mainboard/siemens/mc_apl1/Kconfig | 2 + src/mainboard/siemens/mc_apl1/Kconfig.name | 4 + .../siemens/mc_apl1/variants/mc_apl6/Kconfig | 12 + .../mc_apl1/variants/mc_apl6/Makefile.inc | 4 + .../mc_apl1/variants/mc_apl6/devicetree.cb | 107 +++++ .../siemens/mc_apl1/variants/mc_apl6/gpio.c | 413 ++++++++++++++++++ .../mc_apl1/variants/mc_apl6/mainboard.c | 121 +++++ 7 files changed, 663 insertions(+) create mode 100644 src/mainboard/siemens/mc_apl1/variants/mc_apl6/Kconfig create mode 100644 src/mainboard/siemens/mc_apl1/variants/mc_apl6/Makefile.inc create mode 100644 src/mainboard/siemens/mc_apl1/variants/mc_apl6/devicetree.cb create mode 100644 src/mainboard/siemens/mc_apl1/variants/mc_apl6/gpio.c create mode 100644 src/mainboard/siemens/mc_apl1/variants/mc_apl6/mainboard.c diff --git a/src/mainboard/siemens/mc_apl1/Kconfig b/src/mainboard/siemens/mc_apl1/Kconfig index 196ca28cdc..0b8cff3318 100644 --- a/src/mainboard/siemens/mc_apl1/Kconfig +++ b/src/mainboard/siemens/mc_apl1/Kconfig @@ -22,6 +22,7 @@ config VARIANT_DIR default "mc_apl3" if BOARD_SIEMENS_MC_APL3 default "mc_apl4" if BOARD_SIEMENS_MC_APL4 default "mc_apl5" if BOARD_SIEMENS_MC_APL5 + default "mc_apl6" if BOARD_SIEMENS_MC_APL6 config DEVICETREE string @@ -34,6 +35,7 @@ config MAINBOARD_PART_NUMBER default "MC APL3" if BOARD_SIEMENS_MC_APL3 default "MC APL4" if BOARD_SIEMENS_MC_APL4 default "MC APL5" if BOARD_SIEMENS_MC_APL5 + default "MC APL6" if BOARD_SIEMENS_MC_APL6 config UART_FOR_CONSOLE default 2 diff --git a/src/mainboard/siemens/mc_apl1/Kconfig.name b/src/mainboard/siemens/mc_apl1/Kconfig.name index 70f314d985..225dd19d44 100644 --- a/src/mainboard/siemens/mc_apl1/Kconfig.name +++ b/src/mainboard/siemens/mc_apl1/Kconfig.name @@ -19,3 +19,7 @@ config BOARD_SIEMENS_MC_APL4 config BOARD_SIEMENS_MC_APL5 bool "-> MC APL5" select BOARD_SIEMENS_BASEBOARD_MC_APL1 + +config BOARD_SIEMENS_MC_APL6 + bool "-> MC APL6" + select BOARD_SIEMENS_BASEBOARD_MC_APL1 diff --git a/src/mainboard/siemens/mc_apl1/variants/mc_apl6/Kconfig b/src/mainboard/siemens/mc_apl1/variants/mc_apl6/Kconfig new file mode 100644 index 0000000000..e0f2948a7d --- /dev/null +++ b/src/mainboard/siemens/mc_apl1/variants/mc_apl6/Kconfig @@ -0,0 +1,12 @@ + +if BOARD_SIEMENS_MC_APL6 + +config BOARD_SPECIFIC_OPTIONS + def_bool y + select DRIVER_INTEL_I210 + select DRIVERS_I2C_RX6110SA + select DRIVER_SIEMENS_NC_FPGA + select NC_FPGA_NOTIFY_CB_READY + select APL_SKIP_SET_POWER_LIMITS + +endif # BOARD_SIEMENS_MC_APL6 diff --git a/src/mainboard/siemens/mc_apl1/variants/mc_apl6/Makefile.inc b/src/mainboard/siemens/mc_apl1/variants/mc_apl6/Makefile.inc new file mode 100644 index 0000000000..a6b80e0832 --- /dev/null +++ b/src/mainboard/siemens/mc_apl1/variants/mc_apl6/Makefile.inc @@ -0,0 +1,4 @@ +romstage-y += gpio.c + +ramstage-y += gpio.c +ramstage-y += mainboard.c diff --git a/src/mainboard/siemens/mc_apl1/variants/mc_apl6/devicetree.cb b/src/mainboard/siemens/mc_apl1/variants/mc_apl6/devicetree.cb new file mode 100644 index 0000000000..e1e79b44ae --- /dev/null +++ b/src/mainboard/siemens/mc_apl1/variants/mc_apl6/devicetree.cb @@ -0,0 +1,107 @@ +chip soc/intel/apollolake + + device cpu_cluster 0 on + device lapic 0 on end + end + + register "sci_irq" = "SCIS_IRQ10" + + # Disable unused clkreq of PCIe root ports + register "pcie_rp_clkreq_pin[0]" = "CLKREQ_DISABLED" + register "pcie_rp_clkreq_pin[1]" = "CLKREQ_DISABLED" + register "pcie_rp_clkreq_pin[2]" = "CLKREQ_DISABLED" + register "pcie_rp_clkreq_pin[3]" = "CLKREQ_DISABLED" + register "pcie_rp_clkreq_pin[4]" = "CLKREQ_DISABLED" + register "pcie_rp_clkreq_pin[5]" = "CLKREQ_DISABLED" + + # EMMC TX DATA Delay 1 + # Refer to EDS-Vol2-22.3. + # [14:8] steps of delay for HS400, each 125ps. + # [6:0] steps of delay for SDR104/HS200, each 125ps. + register "emmc_tx_data_cntl1" = "0x0C16" + + # EMMC TX DATA Delay 2 + # Refer to EDS-Vol2-22.3. + # [30:24] steps of delay for SDR50, each 125ps. + # [22:16] steps of delay for DDR50, each 125ps. + # [14:8] steps of delay for SDR25/HS50, each 125ps. + # [6:0] steps of delay for SDR12, each 125ps. + register "emmc_tx_data_cntl2" = "0x28162828" + + # EMMC RX CMD/DATA Delay 1 + # Refer to EDS-Vol2-22.3. + # [30:24] steps of delay for SDR50, each 125ps. + # [22:16] steps of delay for DDR50, each 125ps. + # [14:8] steps of delay for SDR25/HS50, each 125ps. + # [6:0] steps of delay for SDR12, each 125ps. + register "emmc_rx_cmd_data_cntl1" = "0x00181717" + + # EMMC RX CMD/DATA Delay 2 + # Refer to EDS-Vol2-22.3. + # [17:16] stands for Rx Clock before Output Buffer + # [14:8] steps of delay for Auto Tuning Mode, each 125ps. + # [6:0] steps of delay for HS200, each 125ps. + register "emmc_rx_cmd_data_cntl2" = "0x10008" + + # 0:HS400(Default), 1:HS200, 2:DDR50 + register "emmc_host_max_speed" = "1" + + device domain 0 on + device pci 00.0 on end # - Host Bridge + device pci 00.1 off end # - DPTF + device pci 00.2 off end # - NPK + device pci 02.0 on end # - Gen - Display + device pci 03.0 off end # - Iunit + device pci 0d.0 on end # - P2SB + device pci 0d.1 off end # - PMC + device pci 0d.2 on end # - SPI + device pci 0d.3 off end # - Shared SRAM + device pci 0e.0 on end # - Audio + device pci 11.0 on end # - ISH + device pci 12.0 on end # - SATA + device pci 13.0 on end # - RP 2 - PCIe A 0 + device pci 13.1 on end # - RP 3 - PCIe A 1 + device pci 13.2 on end # - RP 4 - PCIe-A 2 + device pci 13.3 on end # - RP 5 - PCIe-A 3 + device pci 14.0 on end # - RP 0 - PCIe-B 0 + device pci 14.1 on end # - RP 1 - PCIe-B 1 + device pci 15.0 on end # - XHCI + device pci 15.1 off end # - XDCI + device pci 16.0 on # - I2C 0 + # Enable external RTC chip + chip drivers/i2c/rx6110sa + register "pmon_sampling" = "PMON_SAMPL_256_MS" + register "bks_on" = "0" + register "bks_off" = "1" + register "iocut_en" = "1" + register "set_user_date" = "1" + register "user_year" = "04" + register "user_month" = "07" + register "user_day" = "01" + register "user_weekday" = "4" + device i2c 0x32 on end # RTC RX6110 SA + end + end + device pci 16.1 off end # - I2C 1 + device pci 16.2 off end # - I2C 2 + device pci 16.3 off end # - I2C 3 + device pci 17.0 off end # - I2C 4 + device pci 17.1 off end # - I2C 5 + device pci 17.2 off end # - I2C 6 + device pci 17.3 off end # - I2C 7 + device pci 18.0 on end # - UART 0 + device pci 18.1 on end # - UART 1 + device pci 18.2 on end # - UART 2 + device pci 18.3 on end # - UART 3 + device pci 19.0 off end # - SPI 0 + device pci 19.1 off end # - SPI 1 + device pci 19.2 off end # - SPI 2 + device pci 1a.0 off end # - PWM + device pci 1b.0 off end # - SDCARD + device pci 1c.0 on end # - eMMC + device pci 1d.0 off end # - UFS + device pci 1e.0 off end # - SDIO + device pci 1f.0 on end # - LPC + device pci 1f.1 on end # - SMBUS + end +end diff --git a/src/mainboard/siemens/mc_apl1/variants/mc_apl6/gpio.c b/src/mainboard/siemens/mc_apl1/variants/mc_apl6/gpio.c new file mode 100644 index 0000000000..7401c74a01 --- /dev/null +++ b/src/mainboard/siemens/mc_apl1/variants/mc_apl6/gpio.c @@ -0,0 +1,413 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2016 Google Inc. + * Copyright (C) 2017-2018 Siemens AG + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the + * GNU General Public License for more details. + */ + +#include +#include + +/* + * Pad configuration in ramstage. The order largely follows the 'GPIO Muxing' + * table found in EDS vol 1, but some pins aren't grouped functionally in + * the table so those were moved for more logical grouping. + */ +static const struct pad_config gpio_table[] = { + + /* Southwest Community */ + + /* PCIE_WAKE[0:3]_N */ + PAD_CFG_NF(GPIO_205, NONE, DEEP, NF1), /* PCIE_WAKE0_N */ + PAD_CFG_NF(GPIO_206, NONE, DEEP, NF1), /* PCIE_WAKE1_N */ + PAD_CFG_NF(GPIO_207, NONE, DEEP, NF1), /* PCIE_WAKE2_N */ + PAD_CFG_NF(GPIO_208, NONE, DEEP, NF1), /* PCIE_WAKE3_N */ + + /* EMMC interface. */ + PAD_CFG_NF(GPIO_156, DN_20K, DEEP, NF1), /* EMMC_CLK */ + PAD_CFG_NF(GPIO_157, UP_20K, DEEP, NF1), /* EMMC_D0 */ + PAD_CFG_NF(GPIO_158, UP_20K, DEEP, NF1), /* EMMC_D1 */ + PAD_CFG_NF(GPIO_159, UP_20K, DEEP, NF1), /* EMMC_D2 */ + PAD_CFG_NF(GPIO_160, UP_20K, DEEP, NF1), /* EMMC_D3 */ + PAD_CFG_NF(GPIO_161, UP_20K, DEEP, NF1), /* EMMC_D4 */ + PAD_CFG_NF(GPIO_162, UP_20K, DEEP, NF1), /* EMMC_D5 */ + PAD_CFG_NF(GPIO_163, UP_20K, DEEP, NF1), /* EMMC_D6 */ + PAD_CFG_NF(GPIO_164, UP_20K, DEEP, NF1), /* EMMC_D7 */ + PAD_CFG_NF(GPIO_165, UP_20K, DEEP, NF1), /* EMMC_CMD */ + PAD_CFG_NF(GPIO_182, DN_20K, DEEP, NF1), /* EMMC_RCLK */ + + /* SDIO -- unused */ + PAD_CFG_GPI(GPIO_166, DN_20K, DEEP), /* SDIO_CLK */ + PAD_CFG_GPI(GPIO_167, UP_20K, DEEP), /* SDIO_D0 */ + /* Configure SDIO to enable power gating. */ + PAD_CFG_NF(GPIO_168, UP_20K, DEEP, NF1), /* SDIO_D1 */ + PAD_CFG_GPI(GPIO_169, UP_20K, DEEP), /* SDIO_D2 */ + PAD_CFG_GPI(GPIO_170, UP_20K, DEEP), /* SDIO_D3 */ + PAD_CFG_GPI(GPIO_171, UP_20K, DEEP), /* SDIO_CMD */ + + /* SDCARD */ + /* Pull down clock by 20K. */ + PAD_CFG_NF(GPIO_172, DN_20K, DEEP, NF1), /* SDCARD_CLK */ + PAD_CFG_NF(GPIO_173, UP_20K, DEEP, NF1), /* SDCARD_D0 */ + PAD_CFG_NF(GPIO_174, UP_20K, DEEP, NF1), /* SDCARD_D1 */ + PAD_CFG_NF(GPIO_175, UP_20K, DEEP, NF1), /* SDCARD_D2 */ + PAD_CFG_NF(GPIO_176, UP_20K, DEEP, NF1), /* SDCARD_D3 */ + /* Card detect is active LOW with external pull up. */ + PAD_CFG_NF(GPIO_177, UP_20K, DEEP, NF1), /* SDCARD_CD_N */ + PAD_CFG_NF(GPIO_178, UP_20K, DEEP, NF1), /* SDCARD_CMD */ + /* CLK feedback, internal signal, needs 20K pull down. */ + PAD_CFG_NF(GPIO_179, DN_20K, DEEP, NF1), /* SDCARD_CLK_FB */ + PAD_CFG_GPI(GPIO_186, UP_20K, DEEP), /* SDCARD_LVL_WP */ + /* EN_SD_SOCKET_PWR_L for SD slot power control. Default on. */ + PAD_CFG_TERM_GPO(GPIO_183, 1, DN_20K, DEEP), /* SDIO_PWR_DOWN_N */ + + /* SMBus */ + PAD_CFG_GPI(SMB_ALERTB, UP_20K, DEEP), /* SMB_ALERT _N */ + PAD_CFG_NF(SMB_CLK, NONE, DEEP, NF1), /* SMB_CLK */ + PAD_CFG_NF(SMB_DATA, NONE, DEEP, NF1), /* SMB_DATA */ + + /* LPC */ + PAD_CFG_NF(LPC_ILB_SERIRQ, NONE, DEEP, NF1), /* LPC_SERIRQ */ + PAD_CFG_NF(LPC_CLKOUT0, DN_20K, DEEP, NF1), /* LPC_CLKOUT0 */ + PAD_CFG_GPI(LPC_CLKOUT1, UP_20K, DEEP), /* LPC_CLKOUT1 */ + PAD_CFG_NF(LPC_AD0, NONE, DEEP, NF1), /* LPC_AD0 */ + PAD_CFG_NF(LPC_AD1, NONE, DEEP, NF1), /* LPC_AD1 */ + PAD_CFG_NF(LPC_AD2, NONE, DEEP, NF1), /* LPC_AD2 */ + PAD_CFG_NF(LPC_AD3, NONE, DEEP, NF1), /* LPC_AD3 */ + PAD_CFG_NF(LPC_CLKRUNB, NONE, DEEP, NF1), /* LPC_CLKRUN_N */ + PAD_CFG_NF(LPC_FRAMEB, NONE, DEEP, NF1), /* LPC_FRAME_N */ + + /* West Community */ + + /* I2C0 - I2C Level Shifter */ + PAD_CFG_NF(GPIO_124, NONE, DEEP, NF1), /* LPSS_I2C0_SDA */ + PAD_CFG_NF(GPIO_125, NONE, DEEP, NF1), /* LPSS_I2C0_SCL */ + + /* I2C[1:7] -- unused */ + PAD_CFG_GPI(GPIO_126, UP_20K, DEEP), /* LPSS_I2C1_SDA */ + PAD_CFG_GPI(GPIO_127, UP_20K, DEEP), /* LPSS_I2C1_SCL */ + PAD_CFG_GPI(GPIO_128, UP_20K, DEEP), /* LPSS_I2C2_SDA */ + PAD_CFG_GPI(GPIO_129, UP_20K, DEEP), /* LPSS_I2C2_SCL */ + PAD_CFG_GPI(GPIO_130, UP_20K, DEEP), /* LPSS_I2C3_SDA */ + PAD_CFG_GPI(GPIO_131, UP_20K, DEEP), /* LPSS_I2C3_SCL */ + PAD_CFG_GPI(GPIO_132, UP_20K, DEEP), /* LPSS_I2C4_SDA */ + PAD_CFG_GPI(GPIO_133, UP_20K, DEEP), /* LPSS_I2C4_SCL */ + PAD_CFG_GPI(GPIO_134, UP_20K, DEEP), /* LPSS_I2C5_SDA */ + PAD_CFG_GPI(GPIO_135, UP_20K, DEEP), /* LPSS_I2C5_SCL */ + PAD_CFG_GPI(GPIO_136, UP_20K, DEEP), /* LPSS_I2C6_SDA */ + PAD_CFG_GPI(GPIO_137, UP_20K, DEEP), /* LPSS_I2C6_SCL */ + PAD_CFG_GPI(GPIO_138, UP_20K, DEEP), /* LPSS_I2C7_SDA */ + PAD_CFG_GPI(GPIO_139, UP_20K, DEEP), /* LPSS_I2C7_SCL */ + + /* ISH_GPIO_[0:9] -- unused */ + PAD_CFG_GPI(GPIO_146, DN_20K, DEEP), /* ISH_GPIO_0 */ + PAD_CFG_GPI(GPIO_147, DN_20K, DEEP), /* ISH_GPIO_1 */ + PAD_CFG_GPI(GPIO_148, DN_20K, DEEP), /* ISH_GPIO_2 */ + PAD_CFG_GPI(GPIO_149, DN_20K, DEEP), /* ISH_GPIO_3 */ + PAD_CFG_GPI(GPIO_150, DN_20K, DEEP), /* ISH_GPIO_4 */ + PAD_CFG_GPI(GPIO_151, DN_20K, DEEP), /* ISH_GPIO_5 */ + PAD_CFG_GPI(GPIO_152, DN_20K, DEEP), /* ISH_GPIO_6 */ + PAD_CFG_GPI(GPIO_153, DN_20K, DEEP), /* ISH_GPIO_7 */ + PAD_CFG_GPI(GPIO_154, DN_20K, DEEP), /* ISH_GPIO_8 */ + PAD_CFG_GPI(GPIO_155, DN_20K, DEEP), /* ISH_GPIO_9 */ + + /* PCIE_CLKREQ[0:3]_N */ + PAD_CFG_NF(GPIO_209, NONE, DEEP, NF1), + PAD_CFG_NF(GPIO_210, NONE, DEEP, NF1), + PAD_CFG_NF(GPIO_211, NONE, DEEP, NF1), + PAD_CFG_NF(GPIO_212, NONE, DEEP, NF1), + + /* OSC_CLK_OUT_0 - RES_CLK_CPU_FPGA */ + PAD_CFG_NF(OSC_CLK_OUT_0, DN_20K, DEEP, NF1), + /* OSC_CLK_OUT_[1:4] -- unused */ + PAD_CFG_GPI(OSC_CLK_OUT_1, DN_20K, DEEP), + PAD_CFG_GPI(OSC_CLK_OUT_2, DN_20K, DEEP), + PAD_CFG_GPI(OSC_CLK_OUT_3, DN_20K, DEEP), + PAD_CFG_GPI(OSC_CLK_OUT_4, DN_20K, DEEP), + + /* PMU Signals */ + PAD_CFG_GPI(PMU_AC_PRESENT, NONE, DEEP), /* PMU_AC_PRESENT */ + PAD_CFG_NF(PMU_BATLOW_B, UP_20K, DEEP, NF1), /* PMU_BATLOW_N */ + PAD_CFG_NF(PMU_PLTRST_B, NONE, DEEP, NF1), /* PMU_PLTRST_N */ + PAD_CFG_NF(PMU_PWRBTN_B, UP_20K, DEEP, NF1), /* PMU_PWRBTN_N */ + PAD_CFG_NF(PMU_RESETBUTTON_B, NONE, DEEP, NF1), /* PMU_RSTBTN_N */ + /* PMU_SLP_S0_N */ + PAD_CFG_NF_IOSSTATE(PMU_SLP_S0_B, NONE, DEEP, NF1, IGNORE), + PAD_CFG_NF(PMU_SLP_S3_B, NONE, DEEP, NF1), /* PMU_SLP_S3_N */ + PAD_CFG_NF(PMU_SLP_S4_B, NONE, DEEP, NF1), /* PMU_SLP_S4_N */ + PAD_CFG_NF(PMU_SUSCLK, NONE, DEEP, NF1), /* PMU_SUSCLK */ + PAD_CFG_TERM_GPO(PMU_WAKE_B, 1, UP_20K, DEEP), /* EN_PP3300_EMMC */ + PAD_CFG_NF(SUS_STAT_B, NONE, DEEP, NF1), /* SUS_STAT_N */ + PAD_CFG_NF(SUSPWRDNACK, NONE, DEEP, NF1), /* SUSPWRDNACK */ + + /* Northwest Community */ + + /* DDI0 SDA and SCL -- unused */ + PAD_CFG_GPI(GPIO_187, DN_20K, DEEP), /* HV_DDI0_DDC_SDA */ + PAD_CFG_GPI(GPIO_188, DN_20K, DEEP), /* HV_DDI0_DDC_SCL */ + /* DDI1 SDA and SCL - Display-Port */ + PAD_CFG_NF(GPIO_189, NONE, DEEP, NF1), /* HV_DDI1_DDC_SDA */ + PAD_CFG_NF(GPIO_190, NONE, DEEP, NF1), /* HV_DDI1_DDC_SCL */ + + /* MIPI I2C -- unused */ + PAD_CFG_GPI(GPIO_191, DN_20K, DEEP), /* MIPI_I2C_SDA */ + PAD_CFG_GPI(GPIO_192, DN_20K, DEEP), /* MIPI_I2C_SCL */ + + /* Panel 0 control -- unused */ + PAD_CFG_TERM_GPO(GPIO_193, 0, DN_20K, DEEP), /* PNL0_VDDEN */ + PAD_CFG_TERM_GPO(GPIO_194, 0, DN_20K, DEEP), /* PNL0_BKLTEN */ + PAD_CFG_TERM_GPO(GPIO_195, 0, DN_20K, DEEP), /* PNL0_BKLTCTL */ + + /* Panel 1 control -- unused */ + PAD_CFG_GPI(GPIO_196, DN_20K, DEEP), /* PNL1_VDDEN */ + PAD_CFG_GPI(GPIO_197, DN_20K, DEEP), /* PNL1_BKLTEN */ + PAD_CFG_GPI(GPIO_198, DN_20K, DEEP), /* PNL1_BKLTCTL */ + + /* DDI[0:1]_HPD -- unused */ + PAD_CFG_GPI(GPIO_199, NONE, DEEP), /* XHPD_DP */ + PAD_CFG_GPI(GPIO_200, DN_20K, DEEP), /* unused */ + + /* MDSI signals -- unused */ + PAD_CFG_GPI(GPIO_201, DN_20K, DEEP), /* MDSI_A_TE */ + PAD_CFG_GPI(GPIO_202, DN_20K, DEEP), /* MDSI_C_TE */ + + /* USB overcurrent pins. */ + PAD_CFG_NF(GPIO_203, NONE, DEEP, NF1), /* USB_OC0_N */ + PAD_CFG_NF(GPIO_204, NONE, DEEP, NF1), /* USB_OC1_N */ + + /* PMC SPI -- almost entirely unused. */ + PAD_CFG_GPI(PMC_SPI_FS0, UP_20K, DEEP), /* CLP_NC */ + PAD_CFG_NF(PMC_SPI_FS1, UP_20K, DEEP, NF2), /* XHPD_EDP_APL */ + PAD_CFG_GPI(PMC_SPI_FS2, UP_20K, DEEP), + PAD_CFG_GPI(PMC_SPI_RXD, DN_20K, DEEP), + PAD_CFG_GPI(PMC_SPI_TXD, DN_20K, DEEP), + PAD_CFG_GPI(PMC_SPI_CLK, DN_20K, DEEP), + + /* PMIC Signals unused signals related to an old PMIC interface. */ + PAD_CFG_NF(PMIC_PWRGOOD, UP_20K, DEEP, NF1), /* PMIC_PWRGOOD */ + PAD_CFG_GPI(PMIC_RESET_B, DN_20K, DEEP), /* PMIC_RESET_B */ + PAD_CFG_TERM_GPO(GPIO_213, 0, DN_20K, DEEP), /* NFC_OUT_RESERVE */ + PAD_CFG_TERM_GPO(GPIO_214, 0, DN_20K, DEEP), /* NFC_EN */ + PAD_CFG_GPI(GPIO_215, DN_20K, DEEP), /* NFC_IN_RESERVE */ + /* THERMTRIP_N */ + PAD_CFG_NF(PMIC_THERMTRIP_B, UP_20K, DEEP, NF1), + PAD_CFG_TERM_GPO(PMIC_STDBY, 0, DN_20K, DEEP), /* unused */ + PAD_CFG_NF(PROCHOT_B, NONE, DEEP, NF1), /* PROCHOT_N */ + PAD_CFG_NF(PMIC_I2C_SCL, NONE, DEEP, NF1), /* PMIC_I2C_SCL */ + PAD_CFG_NF(PMIC_I2C_SDA, NONE, DEEP, NF1), /* PMIC_I2C_SDA */ + + /* I2S1 -- unused */ + PAD_CFG_GPI(GPIO_74, DN_20K, DEEP), /* I2S1_MCLK */ + PAD_CFG_GPI(GPIO_75, DN_20K, DEEP), /* I2S1_BCLK */ + PAD_CFG_GPI(GPIO_76, DN_20K, DEEP), /* I2S1_WS_SYNC */ + PAD_CFG_GPI(GPIO_77, DN_20K, DEEP), /* I2S1_SDI */ + PAD_CFG_GPI(GPIO_78, DN_20K, DEEP), /* I2S1_SDO */ + + /* DMIC or I2S4 -- unused */ + PAD_CFG_GPI(GPIO_79, DN_20K, DEEP), /* AVS_M_CLK_A1 */ + PAD_CFG_GPI(GPIO_80, DN_20K, DEEP), /* AVS_M_CLK_B1 */ + PAD_CFG_GPI(GPIO_81, DN_20K, DEEP), /* AVS_M_DATA_1 */ + PAD_CFG_GPI(GPIO_82, DN_20K, DEEP), /* AVS_M_CLK_AB2 */ + PAD_CFG_GPI(GPIO_83, DN_20K, DEEP), /* AVS_M_DATA_2 */ + + /* I2S2 -- unused */ + PAD_CFG_GPI(GPIO_84, DN_20K, DEEP), /* AVS_I2S2_MCLK */ + PAD_CFG_GPI(GPIO_85, DN_20K, DEEP), /* AVS_I2S2_BCLK */ + PAD_CFG_GPI(GPIO_86, DN_20K, DEEP), /* AVS_I2S2_WS_SYNC */ + PAD_CFG_GPI(GPIO_87, DN_20K, DEEP), /* AVS_I2S2_SDI */ + PAD_CFG_GPI(GPIO_88, DN_20K, DEEP), /* AVS_I2S2_SDO */ + + /* I2S3 -- unused */ + PAD_CFG_GPI(GPIO_89, DN_20K, DEEP), /* AVS_I2S3_BCLK */ + PAD_CFG_GPI(GPIO_90, DN_20K, DEEP), /* AVS_I2S3_WS_SYNC */ + PAD_CFG_GPI(GPIO_91, DN_20K, DEEP), /* AVS_I2S3_SDI */ + PAD_CFG_GPI(GPIO_92, DN_20K, DEEP), /* AVS_I2S3_SDO */ + + /* Fast SPI */ + /* FST_SPI_CS0_B */ + PAD_CFG_NF_IOSSTATE(GPIO_97, NATIVE, DEEP, NF1, IGNORE), + /* FST_SPI_CS1_B -- unused */ + PAD_CFG_GPI(GPIO_98, DN_20K, DEEP), + /* FST_SPI_MOSI_IO0 */ + PAD_CFG_NF_IOSSTATE(GPIO_99, NATIVE, DEEP, NF1, IGNORE), + /* FST_SPI_MISO_IO1 */ + PAD_CFG_NF_IOSSTATE(GPIO_100, NATIVE, DEEP, NF1, IGNORE), + /* FST_IO2 -- MEM_CONFIG0 */ + PAD_CFG_NF(GPIO_101, NATIVE, DEEP, NF1), + /* FST_IO3 -- MEM_CONFIG1 */ + PAD_CFG_NF(GPIO_102, NATIVE, DEEP, NF1), + /* FST_SPI_CLK */ + PAD_CFG_NF_IOSSTATE(GPIO_103, NATIVE, DEEP, NF1, IGNORE), + /* FST_SPI_CLK_FB */ + PAD_CFG_NF_IOSSTATE(FST_SPI_CLK_FB, NATIVE, DEEP, NF1, IGNORE), + + /* SIO_SPI_0 -- unused */ + PAD_CFG_GPI(GPIO_104, DN_20K, DEEP), /* GP_SSP_0_CLK */ + PAD_CFG_GPI(GPIO_105, DN_20K, DEEP), /* GP_SSP_0_FS0 */ + PAD_CFG_GPI(GPIO_106, UP_20K, DEEP), /* GP_SSP_0_FS1 */ + PAD_CFG_GPI(GPIO_109, DN_20K, DEEP), /* GP_SSP_0_RXD */ + PAD_CFG_GPI(GPIO_110, DN_20K, DEEP), /* GP_SSP_0_TXD */ + + /* SIO_SPI_1 -- unused */ + PAD_CFG_GPI(GPIO_111, DN_20K, DEEP), /* GP_SSP_1_CLK */ + PAD_CFG_GPI(GPIO_112, DN_20K, DEEP), /* GP_SSP_1_FS0 */ + PAD_CFG_GPI(GPIO_113, DN_20K, DEEP), /* GP_SSP_1_FS1 */ + PAD_CFG_GPI(GPIO_116, DN_20K, DEEP), /* GP_SSP_1_RXD */ + PAD_CFG_GPI(GPIO_117, DN_20K, DEEP), /* GP_SSP_1_TXD */ + + /* SIO_SPI_2 -- unused */ + PAD_CFG_GPI(GPIO_118, DN_20K, DEEP), /* GP_SSP_2_CLK */ + PAD_CFG_GPI(GPIO_119, DN_20K, DEEP), /* GP_SSP_2_FS0 */ + PAD_CFG_GPI(GPIO_120, DN_20K, DEEP), /* GP_SSP_2_FS1 */ + PAD_CFG_GPI(GPIO_121, DN_20K, DEEP), /* GP_SSP_2_FS2 */ + PAD_CFG_GPI(GPIO_122, DN_20K, DEEP), /* GP_SSP_2_RXD */ + PAD_CFG_GPI(GPIO_123, NONE, DEEP), /* GP_SSP_2_TXD */ + + /* North Community */ + + /* Debug tracing. */ + PAD_CFG_GPI(GPIO_0, DN_20K, DEEP), /* TRACE_0_CLK_VNN */ + PAD_CFG_GPI(GPIO_1, DN_20K, DEEP), /* TRACE_0_DATA0_VNN */ + PAD_CFG_GPI(GPIO_2, DN_20K, DEEP), /* TRACE_0_DATA1_VNN */ + PAD_CFG_GPI(GPIO_3, DN_20K, DEEP), /* TRACE_0_DATA2_VNN */ + PAD_CFG_GPI(GPIO_4, DN_20K, DEEP), /* TRACE_0_DATA3_VNN */ + PAD_CFG_GPI(GPIO_5, DN_20K, DEEP), /* TRACE_0_DATA4_VNN */ + PAD_CFG_GPI(GPIO_6, DN_20K, DEEP), /* TRACE_0_DATA5_VNN */ + PAD_CFG_GPI(GPIO_7, DN_20K, DEEP), /* TRACE_0_DATA6_VNN */ + PAD_CFG_GPI(GPIO_8, DN_20K, DEEP), /* TRACE_0_DATA7_VNN */ + + PAD_CFG_GPI(GPIO_9, DN_20K, DEEP), /* TRACE_1_CLK_VNN */ + PAD_CFG_GPI(GPIO_10, DN_20K, DEEP), /* TRACE_1_DATA0_VNN */ + PAD_CFG_GPI(GPIO_11, DN_20K, DEEP), /* TRACE_1_DATA1_VNN */ + PAD_CFG_GPI(GPIO_12, DN_20K, DEEP), /* TRACE_1_DATA2_VNN */ + PAD_CFG_GPI(GPIO_13, DN_20K, DEEP), /* TRACE_1_DATA3_VNN */ + PAD_CFG_GPI(GPIO_14, DN_20K, DEEP), /* TRACE_1_DATA4_VNN */ + PAD_CFG_GPI(GPIO_15, DN_20K, DEEP), /* TRACE_1_DATA5_VNN */ + PAD_CFG_GPI(GPIO_16, DN_20K, DEEP), /* TRACE_1_DATA6_VNN */ + PAD_CFG_GPI(GPIO_17, DN_20K, DEEP), /* TRACE_1_DATA7_VNN */ + + PAD_CFG_GPI(GPIO_18, DN_20K, DEEP), /* TRACE_2_CLK_VNN */ + PAD_CFG_GPI(GPIO_19, DN_20K, DEEP), /* TRACE_2_DATA0_VNN */ + PAD_CFG_GPI(GPIO_20, DN_20K, DEEP), /* TRACE_2_DATA1_VNN */ + PAD_CFG_GPI(GPIO_21, DN_20K, DEEP), /* TRACE_2_DATA2_VNN */ + PAD_CFG_GPI(GPIO_22, DN_20K, DEEP), /* TRACE_2_DATA3_VNN */ + PAD_CFG_GPI(GPIO_23, DN_20K, DEEP), /* TRACE_2_DATA4_VNN */ + PAD_CFG_GPI(GPIO_24, DN_20K, DEEP), /* TRACE_2_DATA5_VNN */ + PAD_CFG_GPI(GPIO_25, DN_20K, DEEP), /* TRACE_2_DATA6_VNN */ + PAD_CFG_GPI(GPIO_26, DN_20K, DEEP), /* TRACE_2_DATA7_VNN */ + + PAD_CFG_GPI(GPIO_27, DN_20K, DEEP), /* TRIGOUT_0 */ + PAD_CFG_GPI(GPIO_28, DN_20K, DEEP), /* TRIGOUT_1 */ + PAD_CFG_GPI(GPIO_29, DN_20K, DEEP), /* TRIGIN_0 */ + + PAD_CFG_GPI(GPIO_30, DN_20K, DEEP), /* ISH_GPIO_12 */ + PAD_CFG_TERM_GPO(GPIO_31, 1, UP_20K, DEEP), /* ISH_GPIO_13 */ + PAD_CFG_GPI(GPIO_32, UP_20K, DEEP), /* ISH_GPIO_14 */ + PAD_CFG_GPI(GPIO_33, DN_20K, DEEP), /* ISH_GPIO_15 */ + + /* PWM[0:3] -- unused */ + PAD_CFG_GPI(GPIO_34, DN_20K, DEEP), + PAD_CFG_GPI(GPIO_35, DN_20K, DEEP), + PAD_CFG_GPI(GPIO_36, DN_20K, DEEP), + PAD_CFG_GPI(GPIO_37, DN_20K, DEEP), + + /* LPSS_UART[0:2] */ + PAD_CFG_GPI(GPIO_38, UP_20K, DEEP), /* LPSS_UART0_RXD - unused */ + PAD_CFG_GPI(GPIO_39, DN_20K, DEEP), /* LPSS_UART0_TXD - unused */ + PAD_CFG_GPI(GPIO_40, DN_20K, DEEP), /* LPSS_UART0_RTS - unused */ + PAD_CFG_GPI(GPIO_41, UP_20K, DEEP), /* LPSS_UART0_CTS - unused */ + PAD_CFG_NF(GPIO_42, UP_20K, DEEP, NF1), /* LPSS_UART1_RXD */ + /* LPSS_UART1_TXD */ + PAD_CFG_NF_IOSSTATE(GPIO_43, NATIVE, DEEP, NF1, Tx1RxDCRx0), + PAD_CFG_GPI(GPIO_44, UP_20K, DEEP), /* LPSS_UART1_RTS - unused */ + PAD_CFG_GPI(GPIO_45, UP_20K, DEEP), /* LPSS_UART1_CTS - unused */ + PAD_CFG_NF(GPIO_46, UP_20K, DEEP, NF1), /* LPSS_UART2_RXD */ + /* LPSS_UART2_TXD */ + PAD_CFG_NF_IOSSTATE(GPIO_47, NATIVE, DEEP, NF1, Tx1RxDCRx0), + PAD_CFG_GPI(GPIO_48, DN_20K, DEEP), /* LPSS_UART2_RTS - unused */ + PAD_CFG_GPI(GPIO_49, UP_20K, DEEP), /* LPSS_UART2_CTS - unused */ + + /* Camera interface -- completely unused. */ + PAD_CFG_GPI(GPIO_62, DN_20K, DEEP), /* GP_CAMERASB00 */ + PAD_CFG_GPI(GPIO_63, DN_20K, DEEP), /* GP_CAMERASB01 */ + PAD_CFG_GPI(GPIO_64, DN_20K, DEEP), /* GP_CAMERASB02 */ + PAD_CFG_GPI(GPIO_65, DN_20K, DEEP), /* GP_CAMERASB03 */ + PAD_CFG_GPI(GPIO_66, DN_20K, DEEP), /* GP_CAMERASB04 */ + PAD_CFG_GPI(GPIO_67, DN_20K, DEEP), /* GP_CAMERASB05 */ + PAD_CFG_GPI(GPIO_68, DN_20K, DEEP), /* GP_CAMERASB06 */ + PAD_CFG_GPI(GPIO_69, DN_20K, DEEP), /* GP_CAMERASB07 */ + PAD_CFG_GPI(GPIO_70, UP_20K, DEEP), /* GP_CAMERASB08 */ + PAD_CFG_GPI(GPIO_71, UP_20K, DEEP), /* GP_CAMERASB09 */ + PAD_CFG_GPI(GPIO_72, UP_20K, DEEP), /* GP_CAMERASB10 */ + PAD_CFG_GPI(GPIO_73, UP_20K, DEEP), /* GP_CAMERASB11 */ + + /* CNV bridge described into IAFW Vol2. */ + /* GPIO_[216:219] described into EDS Vol1. */ + PAD_CFG_TERM_GPO(CNV_BRI_DT, 0, DN_20K, DEEP), /* Reserve of FPGA */ + PAD_CFG_TERM_GPO(CNV_BRI_RSP, 0, DN_20K, DEEP), /* Reserve of FPGA */ + PAD_CFG_TERM_GPO(CNV_RGI_DT, 0, DN_20K, DEEP), /* Reserve of FPGA */ + PAD_CFG_NF(CNV_RGI_RSP, UP_20K, DEEP, NF1), /* eMMC */ + + /* Serial VID */ + PAD_CFG_NF(SVID0_ALERT_B, NONE, DEEP, NF1), /* SVID0_ALERT_B */ + PAD_CFG_NF(SVID0_DATA, UP_20K, DEEP, NF1), /* SVID0_DATA */ + PAD_CFG_NF(SVID0_CLK, UP_20K, DEEP, NF1), /* SVID0_CLK */ +}; + +const struct pad_config *variant_gpio_table(size_t *num) +{ + *num = ARRAY_SIZE(gpio_table); + return gpio_table; +} + +/* GPIOs needed prior to ramstage. */ +static const struct pad_config early_gpio_table[] = { + + /* Debug tracing. */ + PAD_CFG_GPI(GPIO_0, DN_20K, DEEP), /* TRACE_0_CLK_VNN */ + PAD_CFG_GPI(GPIO_1, DN_20K, DEEP), /* TRACE_0_DATA0_VNN */ + PAD_CFG_GPI(GPIO_2, DN_20K, DEEP), /* TRACE_0_DATA1_VNN */ + PAD_CFG_GPI(GPIO_3, DN_20K, DEEP), /* TRACE_0_DATA2_VNN */ + PAD_CFG_GPI(GPIO_4, DN_20K, DEEP), /* TRACE_0_DATA3_VNN */ + PAD_CFG_GPI(GPIO_5, DN_20K, DEEP), /* TRACE_0_DATA4_VNN */ + PAD_CFG_GPI(GPIO_6, DN_20K, DEEP), /* TRACE_0_DATA5_VNN */ + PAD_CFG_GPI(GPIO_7, DN_20K, DEEP), /* TRACE_0_DATA6_VNN */ + PAD_CFG_GPI(GPIO_8, DN_20K, DEEP), /* TRACE_0_DATA7_VNN */ + + PAD_CFG_GPO(GPIO_13, 0, DEEP), /* PERST# */ + PAD_CFG_GPO(GPIO_15, 0, DEEP), /* PERST# */ + PAD_CFG_GPO(GPIO_17, 1, DEEP), /* PFET */ + PAD_CFG_GPO(GPIO_19, 1, DEEP), /* PFET */ + PAD_CFG_GPO(GPIO_152, 0, DEEP), /* PERST# */ + + /* SMBus */ + PAD_CFG_NF(SMB_CLK, NONE, DEEP, NF1), /* SMB_CLK */ + PAD_CFG_NF(SMB_DATA, NONE, DEEP, NF1), /* SMB_DATA */ + + /* LPC */ + PAD_CFG_NF(LPC_ILB_SERIRQ, NONE, DEEP, NF1), /* LPC_SERIRQ */ + PAD_CFG_NF(LPC_CLKOUT0, DN_20K, DEEP, NF1), /* LPC_CLKOUT0 */ + /* LPC_CLKOUT1 - unused */ + PAD_CFG_GPI(LPC_CLKOUT1, DN_20K, DEEP), + PAD_CFG_NF(LPC_AD0, NONE, DEEP, NF1), /* LPC_AD0 */ + PAD_CFG_NF(LPC_AD1, NONE, DEEP, NF1), /* LPC_AD1 */ + PAD_CFG_NF(LPC_AD2, NONE, DEEP, NF1), /* LPC_AD2 */ + PAD_CFG_NF(LPC_AD3, NONE, DEEP, NF1), /* LPC_AD3 */ + PAD_CFG_NF(LPC_CLKRUNB, NONE, DEEP, NF1), /* LPC_CLKRUN_N */ + PAD_CFG_NF(LPC_FRAMEB, NONE, DEEP, NF1), /* LPC_FRAME_N */ +}; + +const struct pad_config *variant_early_gpio_table(size_t *num) +{ + *num = ARRAY_SIZE(early_gpio_table); + return early_gpio_table; +} diff --git a/src/mainboard/siemens/mc_apl1/variants/mc_apl6/mainboard.c b/src/mainboard/siemens/mc_apl1/variants/mc_apl6/mainboard.c new file mode 100644 index 0000000000..6a883c6a26 --- /dev/null +++ b/src/mainboard/siemens/mc_apl1/variants/mc_apl6/mainboard.c @@ -0,0 +1,121 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2018 Siemens AG + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define TX_DWORD3 0xa8c + +void variant_mainboard_final(void) +{ + struct device *dev = NULL; + uint16_t cmd = 0; + + /* PIR6 register mapping for PCIe root ports + * INTA#->PIRQD#, INTB#->PIRQA#, INTC#->PIRQB#, INTD#-> PIRQC# + */ + pcr_write16(PID_ITSS, 0x314c, 0x2103); + + /* Enable CLKRUN_EN for power gating LPC */ + lpc_enable_pci_clk_cntl(); + + /* + * Enable LPC PCE (Power Control Enable) by setting IOSF-SB port 0xD2 + * offset 0x341D bit3 and bit0. + * Enable LPC CCE (Clock Control Enable) by setting IOSF-SB port 0xD2 + * offset 0x341C bit [3:0]. + */ + pcr_or32(PID_LPC, PCR_LPC_PRC, (PCR_LPC_CCE_EN | PCR_LPC_PCE_EN)); + + /* Set Master Enable for on-board PCI device. */ + dev = dev_find_device(PCI_VENDOR_ID_SIEMENS, 0x403e, 0); + if (dev) { + cmd = pci_read_config16(dev, PCI_COMMAND); + cmd |= PCI_COMMAND_MASTER; + pci_write_config16(dev, PCI_COMMAND, cmd); + + /* Disable clock outputs 0 and 2-4 (CLKOUT) for upstream + * XIO2001 PCIe to PCI Bridge. + */ + struct device *parent = dev->bus->dev; + if (parent && parent->device == PCI_DEVICE_ID_TI_XIO2001) + pci_write_config8(parent, 0xd8, 0x1d); + } + + /* Disable clock outputs 2-5 (CLKOUT) for another XIO2001 PCIe to PCI + * Bridge on this mainboard. + */ + dev = dev_find_device(PCI_VENDOR_ID_SIEMENS, 0x403f, 0); + if (dev) { + struct device *parent = dev->bus->dev; + if (parent && parent->device == PCI_DEVICE_ID_TI_XIO2001) + pci_write_config8(parent, 0xd8, 0x3c); + } + + /* Set Full Reset Bit in Reset Control Register (I/O port CF9h). + * When Bit 3 is set to 1 and then the reset button is pressed the PCH + * will drive SLP_S3 active (low). SLP_S3 is then used on the mainboard + * to generate the right reset timing. + */ + outb(FULL_RST, RST_CNT); +} + +static void wait_for_legacy_dev(void *unused) +{ + uint32_t legacy_delay, us_since_boot; + struct stopwatch sw; + + /* Open main hwinfo block. */ + if (hwilib_find_blocks("hwinfo.hex") != CB_SUCCESS) + return; + + /* Get legacy delay parameter from hwinfo. */ + if (hwilib_get_field(LegacyDelay, (uint8_t *) &legacy_delay, + sizeof(legacy_delay)) != sizeof(legacy_delay)) + return; + + us_since_boot = get_us_since_boot(); + /* No need to wait if the time since boot is already long enough.*/ + if (us_since_boot > legacy_delay) + return; + stopwatch_init_msecs_expire(&sw, (legacy_delay - us_since_boot) / 1000); + printk(BIOS_NOTICE, "Wait remaining %d of %d us for legacy devices...", + legacy_delay - us_since_boot, legacy_delay); + stopwatch_wait_until_expired(&sw); + printk(BIOS_NOTICE, "done!\n"); +} + +static void finalize_boot(void *unused) +{ + /* Set coreboot ready LED. */ + gpio_output(CNV_RGI_DT, 1); +} + +BOOT_STATE_INIT_ENTRY(BS_DEV_ENUMERATE, BS_ON_ENTRY, wait_for_legacy_dev, NULL); +BOOT_STATE_INIT_ENTRY(BS_PAYLOAD_BOOT, BS_ON_ENTRY, finalize_boot, NULL); From 7c276c0dd74623bc9e11584f3fb74e876823af9f Mon Sep 17 00:00:00 2001 From: Werner Zeh Date: Tue, 22 Oct 2019 15:22:21 +0200 Subject: [PATCH 0107/1242] mb/siemens/mc_apl6: Enable VBOOT per default mc_apl6 uses VBOOT scheme so enable it as default. Change-Id: I341180f3815ff9f3b2db801d9d989119a2585b03 Signed-off-by: Werner Zeh Reviewed-on: https://review.coreboot.org/c/coreboot/+/36669 Tested-by: build bot (Jenkins) Reviewed-by: Mario Scheithauer --- .../siemens/mc_apl1/variants/mc_apl6/Kconfig | 16 ++++++++++++++++ .../siemens/mc_apl1/variants/mc_apl6/gpio.c | 2 +- 2 files changed, 17 insertions(+), 1 deletion(-) diff --git a/src/mainboard/siemens/mc_apl1/variants/mc_apl6/Kconfig b/src/mainboard/siemens/mc_apl1/variants/mc_apl6/Kconfig index e0f2948a7d..864e808f17 100644 --- a/src/mainboard/siemens/mc_apl1/variants/mc_apl6/Kconfig +++ b/src/mainboard/siemens/mc_apl1/variants/mc_apl6/Kconfig @@ -8,5 +8,21 @@ config BOARD_SPECIFIC_OPTIONS select DRIVER_SIEMENS_NC_FPGA select NC_FPGA_NOTIFY_CB_READY select APL_SKIP_SET_POWER_LIMITS + select MAINBOARD_HAS_TPM2 + select MAINBOARD_HAS_LPC_TPM + select TPM_ON_FAST_SPI + +config VBOOT + select VBOOT_MEASURED_BOOT + select VBOOT_VBNV_FLASH + select VBOOT_NO_BOARD_SUPPORT + select GBB_FLAG_DISABLE_LID_SHUTDOWN + select GBB_FLAG_DISABLE_PD_SOFTWARE_SYNC + select GBB_FLAG_DISABLE_EC_SOFTWARE_SYNC + select GBB_FLAG_DISABLE_FWMP + +config FMDFILE + string + default "src/mainboard/$(CONFIG_MAINBOARD_DIR)/mc_apl_vboot.fmd" endif # BOARD_SIEMENS_MC_APL6 diff --git a/src/mainboard/siemens/mc_apl1/variants/mc_apl6/gpio.c b/src/mainboard/siemens/mc_apl1/variants/mc_apl6/gpio.c index 7401c74a01..43c2487032 100644 --- a/src/mainboard/siemens/mc_apl1/variants/mc_apl6/gpio.c +++ b/src/mainboard/siemens/mc_apl1/variants/mc_apl6/gpio.c @@ -253,7 +253,7 @@ static const struct pad_config gpio_table[] = { /* SIO_SPI_0 -- unused */ PAD_CFG_GPI(GPIO_104, DN_20K, DEEP), /* GP_SSP_0_CLK */ PAD_CFG_GPI(GPIO_105, DN_20K, DEEP), /* GP_SSP_0_FS0 */ - PAD_CFG_GPI(GPIO_106, UP_20K, DEEP), /* GP_SSP_0_FS1 */ + PAD_CFG_NF(GPIO_106, NATIVE, DEEP, NF3), /* FST_SPI_CS2_N */ PAD_CFG_GPI(GPIO_109, DN_20K, DEEP), /* GP_SSP_0_RXD */ PAD_CFG_GPI(GPIO_110, DN_20K, DEEP), /* GP_SSP_0_TXD */ From 4f7fe494a009a6edc37a5e897de5f5ae32fbb055 Mon Sep 17 00:00:00 2001 From: Werner Zeh Date: Fri, 8 Nov 2019 09:50:20 +0100 Subject: [PATCH 0108/1242] mb/siemens/mc_apl6: Adjust clock lines used on PCIe-2-PCI bridge On this mainboard variant the PCIe-2-PCI bridge is used a bit different. Adjust the switched off clock lines to match the mainboard configuration. Change-Id: I16f3b6eed0948c8201baecdfbb8052c6c1c335c8 Signed-off-by: Werner Zeh Reviewed-on: https://review.coreboot.org/c/coreboot/+/36671 Tested-by: build bot (Jenkins) Reviewed-by: Mario Scheithauer --- src/mainboard/siemens/mc_apl1/variants/mc_apl6/mainboard.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/mainboard/siemens/mc_apl1/variants/mc_apl6/mainboard.c b/src/mainboard/siemens/mc_apl1/variants/mc_apl6/mainboard.c index 6a883c6a26..f908ab6713 100644 --- a/src/mainboard/siemens/mc_apl1/variants/mc_apl6/mainboard.c +++ b/src/mainboard/siemens/mc_apl1/variants/mc_apl6/mainboard.c @@ -60,12 +60,12 @@ void variant_mainboard_final(void) cmd |= PCI_COMMAND_MASTER; pci_write_config16(dev, PCI_COMMAND, cmd); - /* Disable clock outputs 0 and 2-4 (CLKOUT) for upstream + /* Disable clock outputs 0-3 (CLKOUT) for upstream * XIO2001 PCIe to PCI Bridge. */ struct device *parent = dev->bus->dev; if (parent && parent->device == PCI_DEVICE_ID_TI_XIO2001) - pci_write_config8(parent, 0xd8, 0x1d); + pci_write_config8(parent, 0xd8, 0x0F); } /* Disable clock outputs 2-5 (CLKOUT) for another XIO2001 PCIe to PCI From a4b7befbd52baae6842b920ba4ab4a48766b8e56 Mon Sep 17 00:00:00 2001 From: Werner Zeh Date: Fri, 8 Nov 2019 11:49:01 +0100 Subject: [PATCH 0109/1242] mb/siemens/mc_apl6: Enable SDHCI and disable eMMC controller This mainboard variant uses SD-card and not eMMC. Therefore eMMC controller is disabled while SDHCI is enabled. Change-Id: I40b314905730b5d74c674d2251f8a4e5c807805f Signed-off-by: Werner Zeh Reviewed-on: https://review.coreboot.org/c/coreboot/+/36676 Reviewed-by: Mario Scheithauer Tested-by: build bot (Jenkins) --- .../mc_apl1/variants/mc_apl6/devicetree.cb | 36 ++----------------- 1 file changed, 2 insertions(+), 34 deletions(-) diff --git a/src/mainboard/siemens/mc_apl1/variants/mc_apl6/devicetree.cb b/src/mainboard/siemens/mc_apl1/variants/mc_apl6/devicetree.cb index e1e79b44ae..17b7fac9ec 100644 --- a/src/mainboard/siemens/mc_apl1/variants/mc_apl6/devicetree.cb +++ b/src/mainboard/siemens/mc_apl1/variants/mc_apl6/devicetree.cb @@ -14,38 +14,6 @@ chip soc/intel/apollolake register "pcie_rp_clkreq_pin[4]" = "CLKREQ_DISABLED" register "pcie_rp_clkreq_pin[5]" = "CLKREQ_DISABLED" - # EMMC TX DATA Delay 1 - # Refer to EDS-Vol2-22.3. - # [14:8] steps of delay for HS400, each 125ps. - # [6:0] steps of delay for SDR104/HS200, each 125ps. - register "emmc_tx_data_cntl1" = "0x0C16" - - # EMMC TX DATA Delay 2 - # Refer to EDS-Vol2-22.3. - # [30:24] steps of delay for SDR50, each 125ps. - # [22:16] steps of delay for DDR50, each 125ps. - # [14:8] steps of delay for SDR25/HS50, each 125ps. - # [6:0] steps of delay for SDR12, each 125ps. - register "emmc_tx_data_cntl2" = "0x28162828" - - # EMMC RX CMD/DATA Delay 1 - # Refer to EDS-Vol2-22.3. - # [30:24] steps of delay for SDR50, each 125ps. - # [22:16] steps of delay for DDR50, each 125ps. - # [14:8] steps of delay for SDR25/HS50, each 125ps. - # [6:0] steps of delay for SDR12, each 125ps. - register "emmc_rx_cmd_data_cntl1" = "0x00181717" - - # EMMC RX CMD/DATA Delay 2 - # Refer to EDS-Vol2-22.3. - # [17:16] stands for Rx Clock before Output Buffer - # [14:8] steps of delay for Auto Tuning Mode, each 125ps. - # [6:0] steps of delay for HS200, each 125ps. - register "emmc_rx_cmd_data_cntl2" = "0x10008" - - # 0:HS400(Default), 1:HS200, 2:DDR50 - register "emmc_host_max_speed" = "1" - device domain 0 on device pci 00.0 on end # - Host Bridge device pci 00.1 off end # - DPTF @@ -97,8 +65,8 @@ chip soc/intel/apollolake device pci 19.1 off end # - SPI 1 device pci 19.2 off end # - SPI 2 device pci 1a.0 off end # - PWM - device pci 1b.0 off end # - SDCARD - device pci 1c.0 on end # - eMMC + device pci 1b.0 on end # - SDCARD + device pci 1c.0 off end # - eMMC device pci 1d.0 off end # - UFS device pci 1e.0 off end # - SDIO device pci 1f.0 on end # - LPC From 9caadfe708c3e33b009f653025c59dc9d6aa0c40 Mon Sep 17 00:00:00 2001 From: Werner Zeh Date: Fri, 8 Nov 2019 11:51:33 +0100 Subject: [PATCH 0110/1242] mb/siemens/mc_apl6: Add TPM to devicetree The TPM chip needs to be added to the devicetree so that the ACPI tables will be generated for it. These ACPI table entry is used by the OS to get the location of the TPM chip. Change-Id: Ic40d1cf236dd849f04f088808d94b6dd81e3238a Signed-off-by: Werner Zeh Reviewed-on: https://review.coreboot.org/c/coreboot/+/36677 Tested-by: build bot (Jenkins) Reviewed-by: Mario Scheithauer --- .../siemens/mc_apl1/variants/mc_apl6/devicetree.cb | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/src/mainboard/siemens/mc_apl1/variants/mc_apl6/devicetree.cb b/src/mainboard/siemens/mc_apl1/variants/mc_apl6/devicetree.cb index 17b7fac9ec..e12972ccd8 100644 --- a/src/mainboard/siemens/mc_apl1/variants/mc_apl6/devicetree.cb +++ b/src/mainboard/siemens/mc_apl1/variants/mc_apl6/devicetree.cb @@ -69,7 +69,11 @@ chip soc/intel/apollolake device pci 1c.0 off end # - eMMC device pci 1d.0 off end # - UFS device pci 1e.0 off end # - SDIO - device pci 1f.0 on end # - LPC + device pci 1f.0 on # - LPC + chip drivers/pc80/tpm + device pnp 0c31.0 on end + end + end device pci 1f.1 on end # - SMBUS end end From 02a4a0d4717cc08d20b0b5b2afba1b80ba6f1f5b Mon Sep 17 00:00:00 2001 From: Arthur Heymans Date: Mon, 11 Nov 2019 09:24:18 +0100 Subject: [PATCH 0111/1242] soc/intel/tigerlake: Fix cbmem_top EBDA support was dropped. Change-Id: I83d838b79e2653d4e3764cfc7deaca9bb241deab Signed-off-by: Arthur Heymans Reviewed-on: https://review.coreboot.org/c/coreboot/+/36718 Reviewed-by: Subrata Banik Reviewed-by: Patrick Georgi Tested-by: build bot (Jenkins) --- src/soc/intel/tigerlake/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/soc/intel/tigerlake/Kconfig b/src/soc/intel/tigerlake/Kconfig index 014606b882..8ec4354448 100644 --- a/src/soc/intel/tigerlake/Kconfig +++ b/src/soc/intel/tigerlake/Kconfig @@ -43,7 +43,7 @@ config CPU_SPECIFIC_OPTIONS select SOC_INTEL_COMMON_BLOCK_CHIP_CONFIG select SOC_INTEL_COMMON_BLOCK_CPU select SOC_INTEL_COMMON_BLOCK_CPU_MPINIT - select SOC_INTEL_COMMON_BLOCK_EBDA + select SOC_INTEL_COMMON_BLOCK_SA_FSP_TOLUM select SOC_INTEL_COMMON_BLOCK_GSPI_VERSION_2 select SOC_INTEL_COMMON_BLOCK_HDA select SOC_INTEL_COMMON_BLOCK_SA From a1c259beef553c072b890951a328c85153035437 Mon Sep 17 00:00:00 2001 From: Wim Vervoorn Date: Fri, 1 Nov 2019 10:47:01 +0100 Subject: [PATCH 0112/1242] security/vboot: Add rw_region_only support to vboot In some case where the flash space is limited or when a large payload such as LinuxBoot is used, the RO region may not be large enough to contain all components that would normally be added. This patch adds the possibility to add specific components to the RW regions only in the same way as the RO_ONLY_SUPPORT does for the RO region. Please note: this applies only to the items that would normally be added to all regions. If the payload is directed to the RW region only, a recovery payload needs to be added to the RO region manually. BUG=N/A TEST=build Change-Id: Ie0df9b5dfc6df4f24efc5582a1aec9ecfb48c44d Signed-off-by: Wim Vervoorn Reviewed-on: https://review.coreboot.org/c/coreboot/+/36544 Reviewed-by: Arthur Heymans Reviewed-by: Frans Hendriks Tested-by: build bot (Jenkins) --- src/security/vboot/Kconfig | 7 +++++++ src/security/vboot/Makefile.inc | 12 ++++++++++-- 2 files changed, 17 insertions(+), 2 deletions(-) diff --git a/src/security/vboot/Kconfig b/src/security/vboot/Kconfig index 87bb80a561..70180c719a 100644 --- a/src/security/vboot/Kconfig +++ b/src/security/vboot/Kconfig @@ -220,6 +220,13 @@ config RO_REGION_ONLY Add a space delimited list of filenames that should only be in the RO section. +config RW_REGION_ONLY + string + default "" + depends on VBOOT_SLOTS_RW_A + help + Add a space delimited list of filenames that should only be in the + RW sections. config VBOOT_ENABLE_CBFS_FALLBACK bool diff --git a/src/security/vboot/Makefile.inc b/src/security/vboot/Makefile.inc index 31c0f5de26..3e5956cb10 100644 --- a/src/security/vboot/Makefile.inc +++ b/src/security/vboot/Makefile.inc @@ -170,13 +170,17 @@ VBOOT_PARTITIONS := COREBOOT # Check for RW_A partition ifeq ($(CONFIG_VBOOT_SLOTS_RW_A),y) VBOOT_PARTITIONS += FW_MAIN_A +RW_PARTITIONS := FW_MAIN_A endif # Check for RW_B partition ifeq ($(CONFIG_VBOOT_SLOTS_RW_AB),y) VBOOT_PARTITIONS += FW_MAIN_B +RW_PARTITIONS += FW_MAIN_B endif -# Define a list of files that need to be in RO only. +# Return the regions a specific file should be placed in. The files listed below and the ones +# that are specified in CONFIG_RO_REGION_ONLY are only specified in the RO region. The files +# specified in the CONFIG_RW_REGION_ONLY are only placed in the RW regions. # All other files will be installed into RO and RW regions # Use $(sort) to cut down on extra spaces that would be translated to commas regions-for-file = $(subst $(spc),$(comma),$(sort \ @@ -193,7 +197,11 @@ regions-for-file = $(subst $(spc),$(comma),$(sort \ cmos_layout.bin \ cmos.default \ $(call strip_quotes,$(CONFIG_RO_REGION_ONLY)) \ - ,$(1)),COREBOOT,$(VBOOT_PARTITIONS)))) + ,$(1)),COREBOOT,\ + $(if $(filter \ + $(call strip_quotes,$(CONFIG_RW_REGION_ONLY)) \ + ,$(1)), $(RW_PARTITIONS), $(VBOOT_PARTITIONS) ) \ + ))) CONFIG_GBB_HWID := $(call strip_quotes,$(CONFIG_GBB_HWID)) CONFIG_GBB_BMPFV_FILE := $(call strip_quotes,$(CONFIG_GBB_BMPFV_FILE)) From 0cc619bedc89aaef17715ba092c9ab2191d425eb Mon Sep 17 00:00:00 2001 From: Frans Hendriks Date: Fri, 8 Nov 2019 09:56:14 +0100 Subject: [PATCH 0113/1242] vendorcode/eltan/security/mboot/mboot.c: Correct parameter description The flags parameter of the tpm2_get_capability_pcrs() is used by mboot_hash_extend_log(). BUGS=NA TEST=Build Change-Id: Ia718d27f21d41a5e16230c74ca402ea6099470b2 Signed-off-by: Wim Vervoorn Reviewed-on: https://review.coreboot.org/c/coreboot/+/36680 Tested-by: build bot (Jenkins) Reviewed-by: Frans Hendriks --- src/vendorcode/eltan/security/mboot/mboot.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/vendorcode/eltan/security/mboot/mboot.c b/src/vendorcode/eltan/security/mboot/mboot.c index 228d1a0f59..c5523a5fd8 100644 --- a/src/vendorcode/eltan/security/mboot/mboot.c +++ b/src/vendorcode/eltan/security/mboot/mboot.c @@ -120,7 +120,7 @@ int tpm2_get_capability_pcrs(TPML_PCR_SELECTION *Pcrs) * Calculates the hash over the data and extends it in active PCR banks and * then logs them in the event log. * - * @param[in] flags flags associated with hash data. Currently unused. + * @param[in] flags flags associated with hash data. * @param[in] hashData data to be hashed. * @param[in] hashDataLen length of the data to be hashed. * @param[in] newEventHdr event header in TCG_PCR_EVENT2 format. From 46e68ac99adb0a7c83c39842679636081c4d77a9 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Michael=20Niew=C3=B6hner?= Date: Mon, 4 Nov 2019 22:07:29 +0100 Subject: [PATCH 0114/1242] soc/intel/denverton_ns: make use of common cbmem_top_chipset MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This replaces denverton_ns's own implementation of cbmem_top_chipset and selects the common code one. Change-Id: Idae96aabe2807e465bb7ab0f29910757d0346ce9 Signed-off-by: Michael Niewöhner Reviewed-on: https://review.coreboot.org/c/coreboot/+/36619 Reviewed-by: Arthur Heymans Reviewed-by: Nico Huber Reviewed-by: David Guckian Tested-by: build bot (Jenkins) --- src/soc/intel/denverton_ns/Kconfig | 1 + src/soc/intel/denverton_ns/acpi.c | 2 +- src/soc/intel/denverton_ns/memmap.c | 24 ------------------------ src/soc/intel/denverton_ns/systemagent.c | 7 +++++-- 4 files changed, 7 insertions(+), 27 deletions(-) diff --git a/src/soc/intel/denverton_ns/Kconfig b/src/soc/intel/denverton_ns/Kconfig index cb3713d3b0..b7d3d1affd 100644 --- a/src/soc/intel/denverton_ns/Kconfig +++ b/src/soc/intel/denverton_ns/Kconfig @@ -47,6 +47,7 @@ config CPU_SPECIFIC_OPTIONS select SOC_INTEL_COMMON_BLOCK_PMC select ACPI_INTEL_HARDWARE_SLEEP_VALUES # select SOC_INTEL_COMMON_BLOCK_SA + select SOC_INTEL_COMMON_BLOCK_SA_FSP_TOLUM select SOC_INTEL_COMMON_BLOCK_FAST_SPI select SOC_INTEL_COMMON_BLOCK_GPIO select SOC_INTEL_COMMON_BLOCK_PCR diff --git a/src/soc/intel/denverton_ns/acpi.c b/src/soc/intel/denverton_ns/acpi.c index e969a044a1..48b67b089d 100644 --- a/src/soc/intel/denverton_ns/acpi.c +++ b/src/soc/intel/denverton_ns/acpi.c @@ -81,7 +81,7 @@ void acpi_init_gnvs(global_nvs_t *gnvs) gnvs->pcnt = dev_count_cpu(); /* Top of Low Memory (start of resource allocation) */ - gnvs->tolm = top_of_32bit_ram(); + gnvs->tolm = (uintptr_t)cbmem_top(); #if CONFIG(CONSOLE_CBMEM) /* Update the mem console pointer. */ diff --git a/src/soc/intel/denverton_ns/memmap.c b/src/soc/intel/denverton_ns/memmap.c index b4761dbeef..c30f0e98c9 100644 --- a/src/soc/intel/denverton_ns/memmap.c +++ b/src/soc/intel/denverton_ns/memmap.c @@ -38,30 +38,6 @@ static inline uintptr_t system_agent_region_base(size_t reg) return ALIGN_DOWN(pci_read_config32(dev, reg), 1 * MiB); } -/* Returns min power of 2 >= size */ -static inline u32 power_of_2(u32 size) -{ - return size ? 1 << (1 + log2(size - 1)) : 0; -} - -u32 top_of_32bit_ram(void) -{ - u32 iqat_region_size = 0; - u32 tseg_region_size = system_agent_region_base(TOLUD) - - system_agent_region_base(TSEGMB); - -/* - * Add IQAT region size if enabled. - */ -#if CONFIG(IQAT_ENABLE) - iqat_region_size = CONFIG_IQAT_MEMORY_REGION_SIZE; -#endif - return system_agent_region_base(TOLUD) - - power_of_2(iqat_region_size + tseg_region_size); -} - -void *cbmem_top_chipset(void) { return (void *)top_of_32bit_ram(); } - static inline uintptr_t smm_region_start(void) { return system_agent_region_base(TSEGMB); diff --git a/src/soc/intel/denverton_ns/systemagent.c b/src/soc/intel/denverton_ns/systemagent.c index cc1d696d77..00d52287b6 100644 --- a/src/soc/intel/denverton_ns/systemagent.c +++ b/src/soc/intel/denverton_ns/systemagent.c @@ -15,6 +15,7 @@ * GNU General Public License for more details. */ +#include #include #include #include @@ -209,6 +210,7 @@ static void mc_add_dram_resources(struct device *dev) unsigned long index; struct resource *resource; uint64_t mc_values[NUM_MAP_ENTRIES]; + uintptr_t top_of_ram; /* Read in the MAP registers and report their values. */ mc_read_map_entries(dev, &mc_values[0]); @@ -246,6 +248,7 @@ static void mc_add_dram_resources(struct device *dev) * PCI_BASE_ADDRESS_0. */ index = 0; + top_of_ram = (uintptr_t)cbmem_top(); /* 0 - > 0xa0000 */ base_k = 0; @@ -254,12 +257,12 @@ static void mc_add_dram_resources(struct device *dev) /* 0x100000 -> top_of_ram */ base_k = 0x100000 >> 10; - size_k = (top_of_32bit_ram() >> 10) - base_k; + size_k = (top_of_ram >> 10) - base_k; ram_resource(dev, index++, base_k, size_k); /* top_of_ram -> TSEG */ resource = new_resource(dev, index++); - resource->base = top_of_32bit_ram(); + resource->base = top_of_ram; resource->size = mc_values[TSEG_REG] - resource->base; resource->flags = IORESOURCE_MEM | IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_RESERVE | From b8cd4b00497d74a4f28a22bad0f9b79ab88405e3 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Michael=20Niew=C3=B6hner?= Date: Mon, 4 Nov 2019 22:13:44 +0100 Subject: [PATCH 0115/1242] drivers/intel/fsp2_0: move common cbmem_top_chipset to fsp driver MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The common cbmem_top_chipset implementation uses the FSP bootloader HOB, thus move it to the fsp driver which is a more appropriate place. Change-Id: I914df51a7414eb72416f816ff8375a13d5716925 Signed-off-by: Michael Niewöhner Reviewed-on: https://review.coreboot.org/c/coreboot/+/36620 Reviewed-by: Arthur Heymans Reviewed-by: David Guckian Reviewed-by: Nico Huber Tested-by: build bot (Jenkins) --- src/drivers/intel/fsp2_0/Makefile.inc | 1 + .../block/systemagent => drivers/intel/fsp2_0}/cbmem.c | 0 src/soc/intel/apollolake/Kconfig | 1 - src/soc/intel/cannonlake/Kconfig | 1 - src/soc/intel/common/block/systemagent/Kconfig | 6 ------ src/soc/intel/common/block/systemagent/Makefile.inc | 1 - src/soc/intel/denverton_ns/Kconfig | 1 - src/soc/intel/icelake/Kconfig | 1 - src/soc/intel/quark/Kconfig | 2 -- src/soc/intel/skylake/Kconfig | 1 - 10 files changed, 1 insertion(+), 14 deletions(-) rename src/{soc/intel/common/block/systemagent => drivers/intel/fsp2_0}/cbmem.c (100%) diff --git a/src/drivers/intel/fsp2_0/Makefile.inc b/src/drivers/intel/fsp2_0/Makefile.inc index 806d8057ac..bc00cd42c8 100644 --- a/src/drivers/intel/fsp2_0/Makefile.inc +++ b/src/drivers/intel/fsp2_0/Makefile.inc @@ -22,6 +22,7 @@ romstage-$(CONFIG_VERIFY_HOBS) += hob_verify.c romstage-y += util.c romstage-y += memory_init.c romstage-$(CONFIG_MMA) += mma_core.c +romstage-y += cbmem.c ramstage-y += debug.c ramstage-$(CONFIG_RUN_FSP_GOP) += graphics.c diff --git a/src/soc/intel/common/block/systemagent/cbmem.c b/src/drivers/intel/fsp2_0/cbmem.c similarity index 100% rename from src/soc/intel/common/block/systemagent/cbmem.c rename to src/drivers/intel/fsp2_0/cbmem.c diff --git a/src/soc/intel/apollolake/Kconfig b/src/soc/intel/apollolake/Kconfig index cd0c9cd0e8..026f6da669 100644 --- a/src/soc/intel/apollolake/Kconfig +++ b/src/soc/intel/apollolake/Kconfig @@ -84,7 +84,6 @@ config CPU_SPECIFIC_OPTIONS select SOC_INTEL_COMMON_BLOCK_SRAM select SOC_INTEL_COMMON_BLOCK_RTC select SOC_INTEL_COMMON_BLOCK_SA - select SOC_INTEL_COMMON_BLOCK_SA_FSP_TOLUM select SOC_INTEL_COMMON_BLOCK_SCS select SOC_INTEL_COMMON_BLOCK_TIMER select SOC_INTEL_COMMON_BLOCK_TCO diff --git a/src/soc/intel/cannonlake/Kconfig b/src/soc/intel/cannonlake/Kconfig index 70d2d9ab6e..5731cff916 100644 --- a/src/soc/intel/cannonlake/Kconfig +++ b/src/soc/intel/cannonlake/Kconfig @@ -88,7 +88,6 @@ config CPU_SPECIFIC_OPTIONS select SOC_INTEL_COMMON_BLOCK_CHIP_CONFIG select SOC_INTEL_COMMON_BLOCK_CPU select SOC_INTEL_COMMON_BLOCK_CPU_MPINIT - select SOC_INTEL_COMMON_BLOCK_SA_FSP_TOLUM select SOC_INTEL_COMMON_BLOCK_GPIO_DUAL_ROUTE_SUPPORT select SOC_INTEL_COMMON_BLOCK_GSPI_VERSION_2 select SOC_INTEL_COMMON_BLOCK_HDA diff --git a/src/soc/intel/common/block/systemagent/Kconfig b/src/soc/intel/common/block/systemagent/Kconfig index 4c50d50c64..1222573201 100644 --- a/src/soc/intel/common/block/systemagent/Kconfig +++ b/src/soc/intel/common/block/systemagent/Kconfig @@ -3,12 +3,6 @@ config SOC_INTEL_COMMON_BLOCK_SA help Intel Processor common System Agent support -config SOC_INTEL_COMMON_BLOCK_SA_FSP_TOLUM - bool - help - Select this if you want cbmem_top_chipset use the TOLUM returned - by the FSP HOB. - config MMCONF_BASE_ADDRESS hex default 0xe0000000 diff --git a/src/soc/intel/common/block/systemagent/Makefile.inc b/src/soc/intel/common/block/systemagent/Makefile.inc index 1cced4a0d1..7e49ec7291 100644 --- a/src/soc/intel/common/block/systemagent/Makefile.inc +++ b/src/soc/intel/common/block/systemagent/Makefile.inc @@ -6,4 +6,3 @@ ramstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_SA) += systemagent.c romstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_SA) += memmap.c ramstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_SA) += memmap.c postcar-$(CONFIG_SOC_INTEL_COMMON_BLOCK_SA) += memmap.c -romstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_SA_FSP_TOLUM) += cbmem.c diff --git a/src/soc/intel/denverton_ns/Kconfig b/src/soc/intel/denverton_ns/Kconfig index b7d3d1affd..cb3713d3b0 100644 --- a/src/soc/intel/denverton_ns/Kconfig +++ b/src/soc/intel/denverton_ns/Kconfig @@ -47,7 +47,6 @@ config CPU_SPECIFIC_OPTIONS select SOC_INTEL_COMMON_BLOCK_PMC select ACPI_INTEL_HARDWARE_SLEEP_VALUES # select SOC_INTEL_COMMON_BLOCK_SA - select SOC_INTEL_COMMON_BLOCK_SA_FSP_TOLUM select SOC_INTEL_COMMON_BLOCK_FAST_SPI select SOC_INTEL_COMMON_BLOCK_GPIO select SOC_INTEL_COMMON_BLOCK_PCR diff --git a/src/soc/intel/icelake/Kconfig b/src/soc/intel/icelake/Kconfig index 0404af5c98..334dfbec64 100644 --- a/src/soc/intel/icelake/Kconfig +++ b/src/soc/intel/icelake/Kconfig @@ -43,7 +43,6 @@ config CPU_SPECIFIC_OPTIONS select SOC_INTEL_COMMON_BLOCK_CHIP_CONFIG select SOC_INTEL_COMMON_BLOCK_CPU select SOC_INTEL_COMMON_BLOCK_CPU_MPINIT - select SOC_INTEL_COMMON_BLOCK_SA_FSP_TOLUM select SOC_INTEL_COMMON_BLOCK_GSPI_VERSION_2 select SOC_INTEL_COMMON_BLOCK_HDA select SOC_INTEL_COMMON_BLOCK_SA diff --git a/src/soc/intel/quark/Kconfig b/src/soc/intel/quark/Kconfig index 6938431728..461d230371 100644 --- a/src/soc/intel/quark/Kconfig +++ b/src/soc/intel/quark/Kconfig @@ -32,8 +32,6 @@ config CPU_SPECIFIC_OPTIONS select PLATFORM_USES_FSP2_0 select SOC_INTEL_COMMON select SOC_INTEL_COMMON_RESET - select SOC_INTEL_COMMON_BLOCK - select SOC_INTEL_COMMON_BLOCK_SA_FSP_TOLUM select SOC_SETS_MSRS select SPI_FLASH select UART_OVERRIDE_REFCLK diff --git a/src/soc/intel/skylake/Kconfig b/src/soc/intel/skylake/Kconfig index 292963a66b..f5f1e30aaa 100644 --- a/src/soc/intel/skylake/Kconfig +++ b/src/soc/intel/skylake/Kconfig @@ -58,7 +58,6 @@ config CPU_SPECIFIC_OPTIONS select SOC_INTEL_COMMON_BLOCK_CHIP_CONFIG select SOC_INTEL_COMMON_BLOCK_CPU select SOC_INTEL_COMMON_BLOCK_CPU_MPINIT - select SOC_INTEL_COMMON_BLOCK_SA_FSP_TOLUM select SOC_INTEL_COMMON_BLOCK_GPIO_DUAL_ROUTE_SUPPORT select SOC_INTEL_COMMON_BLOCK_GPIO_LEGACY_MACROS select SOC_INTEL_COMMON_BLOCK_GPIO_PADCFG_PADTOL From f76c12a3fcf0e181cfb7358d3972c55b3d7fb6fa Mon Sep 17 00:00:00 2001 From: Arthur Heymans Date: Sun, 10 Nov 2019 19:55:53 +0100 Subject: [PATCH 0116/1242] mb/asus/p5ql-em: Fix S3 resume MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The superio VSBGATE# functionality needs to be enabled for ram to be powered during S3. Change-Id: I7b827e025de7d5b53c587872238a411fc9c2e762 Signed-off-by: Arthur Heymans Reviewed-on: https://review.coreboot.org/c/coreboot/+/36709 Reviewed-by: Angel Pons Reviewed-by: Kyösti Mälkki Tested-by: build bot (Jenkins) --- src/mainboard/asus/p5ql-em/devicetree.cb | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/src/mainboard/asus/p5ql-em/devicetree.cb b/src/mainboard/asus/p5ql-em/devicetree.cb index 8b5215e6e0..165340321b 100644 --- a/src/mainboard/asus/p5ql-em/devicetree.cb +++ b/src/mainboard/asus/p5ql-em/devicetree.cb @@ -138,7 +138,9 @@ chip northbridge/intel/x4x # Northbridge irq 0xe0 = 0xdf irq 0xf3 = 0x09 # RSVD SUSLED settings end - device pnp 2e.a off end # ACPI + device pnp 2e.a on # ACPI + irq 0xe4 = 0x10 # VSBGATE# to power dram during S3 + end device pnp 2e.b on # HWM, front panel LED io 0x60 = 0x290 irq 0x70 = 0 From 898ca04fa45fca21a5f9d0f46122e4e4ac46f2cf Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ky=C3=B6sti=20M=C3=A4lkki?= Date: Sun, 10 Nov 2019 18:20:36 +0200 Subject: [PATCH 0117/1242] AGESA: Select CBMEM_STAGE_CACHE with HAVE_ACPI_RESUME MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Fix regression with commit 0a4457f lib/stage_cache: Refactor Kconfig options AGESA platforms fail to resume from S3 suspend with CBMEM_STAGE_CACHE=n. For the time being the root cause is unknown. Change-Id: I11db0c883b6e39473d02e92b14cb3c6302aa728e Signed-off-by: Kyösti Mälkki Reviewed-on: https://review.coreboot.org/c/coreboot/+/36708 Tested-by: build bot (Jenkins) Reviewed-by: Arthur Heymans Reviewed-by: Mike Banon Reviewed-by: Nico Huber --- src/cpu/amd/agesa/Kconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/src/cpu/amd/agesa/Kconfig b/src/cpu/amd/agesa/Kconfig index b1fde2dcf7..d14eb4054f 100644 --- a/src/cpu/amd/agesa/Kconfig +++ b/src/cpu/amd/agesa/Kconfig @@ -27,6 +27,7 @@ config CPU_AMD_AGESA select UDELAY_LAPIC select LAPIC_MONOTONIC_TIMER select SPI_FLASH if HAVE_ACPI_RESUME + select CBMEM_STAGE_CACHE if HAVE_ACPI_RESUME select SMM_ASEG select NO_FIXED_XIP_ROM_SIZE From 77fe213b55bc2be4476cd30d8376592d1d02a24e Mon Sep 17 00:00:00 2001 From: Elyes HAOUAS Date: Tue, 29 Oct 2019 08:42:03 +0100 Subject: [PATCH 0118/1242] SMBIOS: Add 'CXL FLexbus 1.0' memory array location Change-Id: Ib66616ddefe6254c7c64f223c4f3f7cc8d198bb7 Signed-off-by: Elyes HAOUAS Reviewed-on: https://review.coreboot.org/c/coreboot/+/36427 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber --- src/include/smbios.h | 1 + 1 file changed, 1 insertion(+) diff --git a/src/include/smbios.h b/src/include/smbios.h index d230fb2e1e..129977636c 100644 --- a/src/include/smbios.h +++ b/src/include/smbios.h @@ -192,6 +192,7 @@ typedef enum { MEMORY_ARRAY_LOCATION_PC_98_C24_ADD_ON = 0xa1, MEMORY_ARRAY_LOCATION_PC_98_E_ADD_ON = 0xa2, MEMORY_ARRAY_LOCATION_PC_98_LOCAL_BUS_ADD_ON = 0xa3, + MEMORY_ARRAY_LOCATION_CXL_FLEXBUS_1_0_ADD_ON = 0xa4, } smbios_memory_array_location; typedef enum { From 187655cee06d2897fe1f516dcd9ce6ccab2da056 Mon Sep 17 00:00:00 2001 From: Elyes HAOUAS Date: Wed, 30 Oct 2019 09:06:43 +0100 Subject: [PATCH 0119/1242] mb/{google/fizz,razer/blade_stealth_kbl}: Add missing include Change-Id: Ia4e496d359036591131c1ec0243d64c58823ca63 Signed-off-by: Elyes HAOUAS Reviewed-on: https://review.coreboot.org/c/coreboot/+/36453 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber --- src/mainboard/google/fizz/mainboard.c | 1 + src/mainboard/razer/blade_stealth_kbl/romstage.c | 1 + 2 files changed, 2 insertions(+) diff --git a/src/mainboard/google/fizz/mainboard.c b/src/mainboard/google/fizz/mainboard.c index 6a7d452942..939778630c 100644 --- a/src/mainboard/google/fizz/mainboard.c +++ b/src/mainboard/google/fizz/mainboard.c @@ -16,6 +16,7 @@ #include #include #include +#include #include #include #include diff --git a/src/mainboard/razer/blade_stealth_kbl/romstage.c b/src/mainboard/razer/blade_stealth_kbl/romstage.c index 89903ab7c4..445f620020 100644 --- a/src/mainboard/razer/blade_stealth_kbl/romstage.c +++ b/src/mainboard/razer/blade_stealth_kbl/romstage.c @@ -17,6 +17,7 @@ */ #include +#include #include #include #include "spd/spd.h" From 23846825650d59993d841f3a8d8d954ea06bba70 Mon Sep 17 00:00:00 2001 From: Elyes HAOUAS Date: Wed, 30 Oct 2019 09:07:51 +0100 Subject: [PATCH 0120/1242] soc/mediatek: Add missing '#include ' Change-Id: I2e79ff3352fe974a070b7b3f5e4b5570ed2b294c Signed-off-by: Elyes HAOUAS Reviewed-on: https://review.coreboot.org/c/coreboot/+/36454 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber --- src/soc/mediatek/common/i2c.c | 1 + src/soc/mediatek/mt8183/spm.c | 1 + 2 files changed, 2 insertions(+) diff --git a/src/soc/mediatek/common/i2c.c b/src/soc/mediatek/common/i2c.c index e58bb9c4ea..1ca55ae717 100644 --- a/src/soc/mediatek/common/i2c.c +++ b/src/soc/mediatek/common/i2c.c @@ -15,6 +15,7 @@ #include #include +#include #include #include #include diff --git a/src/soc/mediatek/mt8183/spm.c b/src/soc/mediatek/mt8183/spm.c index 669970fb2f..9a08782953 100644 --- a/src/soc/mediatek/mt8183/spm.c +++ b/src/soc/mediatek/mt8183/spm.c @@ -15,6 +15,7 @@ #include #include +#include #include #include #include From b7e8505d96236e73db2d0440f1a5889cdba18697 Mon Sep 17 00:00:00 2001 From: Elyes HAOUAS Date: Sun, 20 Oct 2019 09:22:42 +0200 Subject: [PATCH 0121/1242] soc/{cannonlake,skylake}: Remove unused 'rdmsr(MSR_CONFIG_TDP_NOMINAL)' MSR_CONFIG_TDP_NOMINAL is used by 'cpu_get_tdp_nominal_ratio' to return the TDP Nominal Ratio. Change-Id: I4c8df7a4100c185c1430d993f7618ed00fc556ff Signed-off-by: Elyes HAOUAS Reviewed-on: https://review.coreboot.org/c/coreboot/+/36164 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber --- src/soc/intel/cannonlake/cpu.c | 1 - src/soc/intel/skylake/cpu.c | 1 - 2 files changed, 2 deletions(-) diff --git a/src/soc/intel/cannonlake/cpu.c b/src/soc/intel/cannonlake/cpu.c index 7f38279def..c3a27aeb36 100644 --- a/src/soc/intel/cannonlake/cpu.c +++ b/src/soc/intel/cannonlake/cpu.c @@ -220,7 +220,6 @@ void set_power_limits(u8 power_limit_1_time) /* Use nominal TDP values for CPUs with configurable TDP */ if (cpu_config_tdp_levels()) { - msr = rdmsr(MSR_CONFIG_TDP_NOMINAL); limit.hi = 0; limit.lo = cpu_get_tdp_nominal_ratio(); wrmsr(MSR_TURBO_ACTIVATION_RATIO, limit); diff --git a/src/soc/intel/skylake/cpu.c b/src/soc/intel/skylake/cpu.c index 080dba0b13..7a45693ad7 100644 --- a/src/soc/intel/skylake/cpu.c +++ b/src/soc/intel/skylake/cpu.c @@ -231,7 +231,6 @@ void set_power_limits(u8 power_limit_1_time) /* Use nominal TDP values for CPUs with configurable TDP */ if (cpu_config_tdp_levels()) { - msr = rdmsr(MSR_CONFIG_TDP_NOMINAL); limit.hi = 0; limit.lo = cpu_get_tdp_nominal_ratio(); wrmsr(MSR_TURBO_ACTIVATION_RATIO, limit); From 9764bc126ea8718cdc723714d8355e51e71aa65f Mon Sep 17 00:00:00 2001 From: Patrick Rudolph Date: Sun, 10 Nov 2019 16:48:23 +0100 Subject: [PATCH 0122/1242] mb/*: Fix default fmap with VBOOT_SLOTS_RW_A enabled Don't select the VBOOT fmap as default if VBOOT is disabled. Fixes a regression introduced by f8251b98 "mb/emulation/qemu: Add VBOOT support" where the default Kconfig settings wouldn't allow the qemu boards to run. Also fix the Supermicro x11-lga1151 series boards. Change-Id: I90414e2cc7e4c4a6ad67014bd4a7f9c8ff4da389 Signed-off-by: Patrick Rudolph Reviewed-on: https://review.coreboot.org/c/coreboot/+/36707 Reviewed-by: Arthur Heymans Reviewed-by: Nico Huber Tested-by: build bot (Jenkins) --- src/mainboard/emulation/qemu-i440fx/Kconfig | 4 ++++ src/mainboard/emulation/qemu-q35/Kconfig | 4 ++++ src/mainboard/supermicro/x11-lga1151-series/Kconfig | 4 ++++ 3 files changed, 12 insertions(+) diff --git a/src/mainboard/emulation/qemu-i440fx/Kconfig b/src/mainboard/emulation/qemu-i440fx/Kconfig index 05246b6d6d..8632ef67c2 100644 --- a/src/mainboard/emulation/qemu-i440fx/Kconfig +++ b/src/mainboard/emulation/qemu-i440fx/Kconfig @@ -25,9 +25,13 @@ config VBOOT select GBB_FLAG_DISABLE_EC_SOFTWARE_SYNC select GBB_FLAG_DISABLE_FWMP +if VBOOT + config VBOOT_SLOTS_RW_A default y +endif + config FMDFILE string default "src/mainboard/$(CONFIG_MAINBOARD_DIR)/vboot-rwa-16M.fmd" if VBOOT_SLOTS_RW_A diff --git a/src/mainboard/emulation/qemu-q35/Kconfig b/src/mainboard/emulation/qemu-q35/Kconfig index a86e844044..8b97495180 100644 --- a/src/mainboard/emulation/qemu-q35/Kconfig +++ b/src/mainboard/emulation/qemu-q35/Kconfig @@ -28,9 +28,13 @@ config FMDFILE string default "src/mainboard/$(CONFIG_MAINBOARD_DIR)/vboot-rwa-16M.fmd" if VBOOT_SLOTS_RW_A +if VBOOT + config VBOOT_SLOTS_RW_A default y +endif + config VBOOT_VBNV_OFFSET hex default 0x2c diff --git a/src/mainboard/supermicro/x11-lga1151-series/Kconfig b/src/mainboard/supermicro/x11-lga1151-series/Kconfig index ea0214ad01..5a99f7aac5 100644 --- a/src/mainboard/supermicro/x11-lga1151-series/Kconfig +++ b/src/mainboard/supermicro/x11-lga1151-series/Kconfig @@ -47,9 +47,13 @@ config VBOOT select GBB_FLAG_DISABLE_EC_SOFTWARE_SYNC select GBB_FLAG_DISABLE_FWMP +if VBOOT + config VBOOT_SLOTS_RW_AB default y +endif + config VBOOT_VBNV_OFFSET hex default 0x2a From 72f13e534bed0be4a3bc0999dc2fe772c322114f Mon Sep 17 00:00:00 2001 From: Bill XIE Date: Mon, 28 Oct 2019 00:16:05 +0800 Subject: [PATCH 0123/1242] ec/lenovo/h8: Make dock init in ramstage fully mainboard-specific Discussed in CB:36093, in the past many lenovo boards need to declare an empty h8_mainboard_init_dock() to satisfy h8.c. Now the confusing H8_DOCK_EARLY_INIT might be retired, and if a mainboard needs dock init (done with h8_mainboard_init_dock() in the past) in ramstage, (discussed in CB:4294 where H8_DOCK_EARLY_INIT is introduced) it can just do it in its own chip_ops.enable_dev function. Tested on X200. Testing on other affected targets may be necessary. Change-Id: I5737406d1f6cb6e91b2e2fa349a206a3dba988d1 Signed-off-by: Bill XIE Reviewed-on: https://review.coreboot.org/c/coreboot/+/36385 Tested-by: build bot (Jenkins) Reviewed-by: Arthur Heymans --- src/ec/lenovo/h8/Kconfig | 5 +---- src/ec/lenovo/h8/h8.c | 4 ---- src/ec/lenovo/h8/h8.h | 2 -- src/mainboard/lenovo/l520/mainboard.c | 4 ---- src/mainboard/lenovo/t400/Kconfig | 1 - src/mainboard/lenovo/t410/dock.c | 2 +- src/mainboard/lenovo/t410/dock.h | 2 +- src/mainboard/lenovo/t410/mainboard.c | 2 ++ src/mainboard/lenovo/t420/mainboard.c | 4 ---- src/mainboard/lenovo/t420s/mainboard.c | 4 ---- src/mainboard/lenovo/t430/mainboard.c | 4 ---- src/mainboard/lenovo/t430s/mainboard.c | 4 ---- src/mainboard/lenovo/t440p/mainboard.c | 4 ---- src/mainboard/lenovo/t520/mainboard.c | 4 ---- src/mainboard/lenovo/t530/mainboard.c | 4 ---- src/mainboard/lenovo/t60/Kconfig | 1 - src/mainboard/lenovo/x131e/mainboard.c | 4 ---- .../lenovo/x1_carbon_gen1/mainboard.c | 5 ----- src/mainboard/lenovo/x200/Makefile.inc | 2 +- src/mainboard/lenovo/x200/dock.h | 2 +- src/mainboard/lenovo/x200/mainboard.c | 3 +++ .../lenovo/x200/variants/x200/dock.c | 2 +- .../lenovo/x200/variants/x301/dock.c | 22 ------------------- src/mainboard/lenovo/x201/dock.c | 2 +- src/mainboard/lenovo/x201/dock.h | 2 +- src/mainboard/lenovo/x201/mainboard.c | 2 ++ src/mainboard/lenovo/x220/mainboard.c | 4 ---- src/mainboard/lenovo/x230/mainboard.c | 4 ---- src/mainboard/lenovo/x60/Kconfig | 1 - 29 files changed, 15 insertions(+), 91 deletions(-) delete mode 100644 src/mainboard/lenovo/x200/variants/x301/dock.c diff --git a/src/ec/lenovo/h8/Kconfig b/src/ec/lenovo/h8/Kconfig index f3df56a6c5..6bd290f50e 100644 --- a/src/ec/lenovo/h8/Kconfig +++ b/src/ec/lenovo/h8/Kconfig @@ -44,7 +44,4 @@ config H8_HAS_PRIMARY_FN_KEYS bool default n -endif - -config H8_DOCK_EARLY_INIT - bool +endif # EC_LENOVO_H8 diff --git a/src/ec/lenovo/h8/h8.c b/src/ec/lenovo/h8/h8.c index 3a99b52dd8..93a771c47d 100644 --- a/src/ec/lenovo/h8/h8.c +++ b/src/ec/lenovo/h8/h8.c @@ -353,10 +353,6 @@ static void h8_enable(struct device *dev) h8_charge_priority(val); h8_set_audio_mute(0); - -#if !CONFIG(H8_DOCK_EARLY_INIT) - h8_mainboard_init_dock(); -#endif } struct chip_operations ec_lenovo_h8_ops = { diff --git a/src/ec/lenovo/h8/h8.h b/src/ec/lenovo/h8/h8.h index 14948c55ce..6dad2889ad 100644 --- a/src/ec/lenovo/h8/h8.h +++ b/src/ec/lenovo/h8/h8.h @@ -36,8 +36,6 @@ int h8_ultrabay_device_present(void); u8 h8_build_id_and_function_spec_version(char *buf, u8 buf_len); void h8_usb_always_on(void); -void h8_mainboard_init_dock (void); - int h8_get_fn_key(void); int h8_get_sense_ready(void); diff --git a/src/mainboard/lenovo/l520/mainboard.c b/src/mainboard/lenovo/l520/mainboard.c index db695b1b4a..88c7884f28 100644 --- a/src/mainboard/lenovo/l520/mainboard.c +++ b/src/mainboard/lenovo/l520/mainboard.c @@ -26,10 +26,6 @@ static void mainboard_enable(struct device *dev) GMA_INT15_BOOT_DISPLAY_DEFAULT, 0); } -void h8_mainboard_init_dock(void) -{ -} - struct chip_operations mainboard_ops = { .enable_dev = mainboard_enable, }; diff --git a/src/mainboard/lenovo/t400/Kconfig b/src/mainboard/lenovo/t400/Kconfig index 8d286c442b..a68d1fa13e 100644 --- a/src/mainboard/lenovo/t400/Kconfig +++ b/src/mainboard/lenovo/t400/Kconfig @@ -10,7 +10,6 @@ config BOARD_SPECIFIC_OPTIONS select EC_LENOVO_PMH7 select EC_LENOVO_H8 select H8_HAS_BAT_TRESHOLDS_IMPL - select H8_DOCK_EARLY_INIT select BOARD_ROMSIZE_KB_8192 if !BOARD_LENOVO_R500 select BOARD_ROMSIZE_KB_4096 if BOARD_LENOVO_R500 select DRIVERS_GENERIC_IOAPIC diff --git a/src/mainboard/lenovo/t410/dock.c b/src/mainboard/lenovo/t410/dock.c index 317fb0513c..1575aa1906 100644 --- a/src/mainboard/lenovo/t410/dock.c +++ b/src/mainboard/lenovo/t410/dock.c @@ -22,7 +22,7 @@ #include #include -void h8_mainboard_init_dock(void) +void init_dock(void) { if (dock_present()) { printk(BIOS_DEBUG, "dock is connected\n"); diff --git a/src/mainboard/lenovo/t410/dock.h b/src/mainboard/lenovo/t410/dock.h index 4cd8c857a8..6a08d81836 100644 --- a/src/mainboard/lenovo/t410/dock.h +++ b/src/mainboard/lenovo/t410/dock.h @@ -15,7 +15,7 @@ #ifndef THINKPAD_X201_DOCK_H #define THINKPAD_X201_DOCK_H - +void init_dock(void); void dock_connect(void); void dock_disconnect(void); int dock_present(void); diff --git a/src/mainboard/lenovo/t410/mainboard.c b/src/mainboard/lenovo/t410/mainboard.c index 23b68fabc2..8b6a737e0e 100644 --- a/src/mainboard/lenovo/t410/mainboard.c +++ b/src/mainboard/lenovo/t410/mainboard.c @@ -19,12 +19,14 @@ #include #include #include +#include "dock.h" static void mainboard_enable(struct device *dev) { install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_INT_LVDS, GMA_INT15_PANEL_FIT_DEFAULT, GMA_INT15_BOOT_DISPLAY_LFP, 2); + init_dock(); } struct chip_operations mainboard_ops = { diff --git a/src/mainboard/lenovo/t420/mainboard.c b/src/mainboard/lenovo/t420/mainboard.c index 6c85abad29..bc6dcb17dc 100644 --- a/src/mainboard/lenovo/t420/mainboard.c +++ b/src/mainboard/lenovo/t420/mainboard.c @@ -26,10 +26,6 @@ static void mainboard_enable(struct device *dev) GMA_INT15_BOOT_DISPLAY_DEFAULT, 0); } -void h8_mainboard_init_dock(void) -{ -} - struct chip_operations mainboard_ops = { .enable_dev = mainboard_enable, }; diff --git a/src/mainboard/lenovo/t420s/mainboard.c b/src/mainboard/lenovo/t420s/mainboard.c index 6c85abad29..bc6dcb17dc 100644 --- a/src/mainboard/lenovo/t420s/mainboard.c +++ b/src/mainboard/lenovo/t420s/mainboard.c @@ -26,10 +26,6 @@ static void mainboard_enable(struct device *dev) GMA_INT15_BOOT_DISPLAY_DEFAULT, 0); } -void h8_mainboard_init_dock(void) -{ -} - struct chip_operations mainboard_ops = { .enable_dev = mainboard_enable, }; diff --git a/src/mainboard/lenovo/t430/mainboard.c b/src/mainboard/lenovo/t430/mainboard.c index 99a5bd8536..a86a90e553 100644 --- a/src/mainboard/lenovo/t430/mainboard.c +++ b/src/mainboard/lenovo/t430/mainboard.c @@ -17,10 +17,6 @@ #include #include -void h8_mainboard_init_dock (void) -{ -} - static void mainboard_enable(struct device *dev) { install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_INT_LVDS, diff --git a/src/mainboard/lenovo/t430s/mainboard.c b/src/mainboard/lenovo/t430s/mainboard.c index 6c85abad29..bc6dcb17dc 100644 --- a/src/mainboard/lenovo/t430s/mainboard.c +++ b/src/mainboard/lenovo/t430s/mainboard.c @@ -26,10 +26,6 @@ static void mainboard_enable(struct device *dev) GMA_INT15_BOOT_DISPLAY_DEFAULT, 0); } -void h8_mainboard_init_dock(void) -{ -} - struct chip_operations mainboard_ops = { .enable_dev = mainboard_enable, }; diff --git a/src/mainboard/lenovo/t440p/mainboard.c b/src/mainboard/lenovo/t440p/mainboard.c index dcfd5038fd..0881c2dda6 100644 --- a/src/mainboard/lenovo/t440p/mainboard.c +++ b/src/mainboard/lenovo/t440p/mainboard.c @@ -25,10 +25,6 @@ static void mainboard_enable(struct device *dev) GMA_INT15_BOOT_DISPLAY_DEFAULT, 0); } -void h8_mainboard_init_dock(void) -{ -} - struct chip_operations mainboard_ops = { .enable_dev = mainboard_enable, }; diff --git a/src/mainboard/lenovo/t520/mainboard.c b/src/mainboard/lenovo/t520/mainboard.c index bd4292a851..6825b6b29f 100644 --- a/src/mainboard/lenovo/t520/mainboard.c +++ b/src/mainboard/lenovo/t520/mainboard.c @@ -28,10 +28,6 @@ static void mainboard_enable(struct device *dev) GMA_INT15_BOOT_DISPLAY_DEFAULT, 0); } -void h8_mainboard_init_dock (void) -{ -} - struct chip_operations mainboard_ops = { .enable_dev = mainboard_enable, }; diff --git a/src/mainboard/lenovo/t530/mainboard.c b/src/mainboard/lenovo/t530/mainboard.c index 29c15e0f5a..144fde7f2e 100644 --- a/src/mainboard/lenovo/t530/mainboard.c +++ b/src/mainboard/lenovo/t530/mainboard.c @@ -29,10 +29,6 @@ static void mainboard_enable(struct device *dev) GMA_INT15_BOOT_DISPLAY_DEFAULT, 0); } -void h8_mainboard_init_dock (void) -{ -} - struct chip_operations mainboard_ops = { .enable_dev = mainboard_enable, }; diff --git a/src/mainboard/lenovo/t60/Kconfig b/src/mainboard/lenovo/t60/Kconfig index bc8fa293b2..436b035a1e 100644 --- a/src/mainboard/lenovo/t60/Kconfig +++ b/src/mainboard/lenovo/t60/Kconfig @@ -19,7 +19,6 @@ config BOARD_SPECIFIC_OPTIONS select BOARD_ROMSIZE_KB_2048 select HAVE_ACPI_TABLES select HAVE_ACPI_RESUME - select H8_DOCK_EARLY_INIT select HAVE_CMOS_DEFAULT select I945_LVDS select INTEL_GMA_HAVE_VBT diff --git a/src/mainboard/lenovo/x131e/mainboard.c b/src/mainboard/lenovo/x131e/mainboard.c index 1342aca9bc..50b4de1ee2 100644 --- a/src/mainboard/lenovo/x131e/mainboard.c +++ b/src/mainboard/lenovo/x131e/mainboard.c @@ -24,10 +24,6 @@ static void mainboard_enable(struct device *dev) GMA_INT15_BOOT_DISPLAY_DEFAULT, 0); } -void h8_mainboard_init_dock(void) -{ -} - struct chip_operations mainboard_ops = { .enable_dev = mainboard_enable, }; diff --git a/src/mainboard/lenovo/x1_carbon_gen1/mainboard.c b/src/mainboard/lenovo/x1_carbon_gen1/mainboard.c index 64cc15b6fe..bc6dcb17dc 100644 --- a/src/mainboard/lenovo/x1_carbon_gen1/mainboard.c +++ b/src/mainboard/lenovo/x1_carbon_gen1/mainboard.c @@ -29,8 +29,3 @@ static void mainboard_enable(struct device *dev) struct chip_operations mainboard_ops = { .enable_dev = mainboard_enable, }; - -/* TODO: this device doesnt have a dock */ -void h8_mainboard_init_dock (void) -{ -} diff --git a/src/mainboard/lenovo/x200/Makefile.inc b/src/mainboard/lenovo/x200/Makefile.inc index f6c2c0c074..7e38a78b4c 100644 --- a/src/mainboard/lenovo/x200/Makefile.inc +++ b/src/mainboard/lenovo/x200/Makefile.inc @@ -13,7 +13,7 @@ ## GNU General Public License for more details. ## -ramstage-y += variants/$(VARIANT_DIR)/dock.c +ramstage-$(CONFIG_BOARD_LENOVO_X200) += variants/$(VARIANT_DIR)/dock.c ramstage-y += cstates.c ramstage-y += blc.c romstage-y += variants/$(VARIANT_DIR)/gpio.c diff --git a/src/mainboard/lenovo/x200/dock.h b/src/mainboard/lenovo/x200/dock.h index 56f3fe0f7a..a129cd04a3 100644 --- a/src/mainboard/lenovo/x200/dock.h +++ b/src/mainboard/lenovo/x200/dock.h @@ -15,7 +15,7 @@ #ifndef THINKPAD_X200_DOCK_H #define THINKPAD_X200_DOCK_H - +void init_dock(void); void dock_connect(void); void dock_disconnect(void); int dock_present(void); diff --git a/src/mainboard/lenovo/x200/mainboard.c b/src/mainboard/lenovo/x200/mainboard.c index 1510ab7b17..37fe865e81 100644 --- a/src/mainboard/lenovo/x200/mainboard.c +++ b/src/mainboard/lenovo/x200/mainboard.c @@ -16,6 +16,7 @@ #include #include #include +#include "dock.h" static void fill_ssdt(struct device *device) { @@ -29,6 +30,8 @@ static void mainboard_enable(struct device *dev) GMA_INT15_BOOT_DISPLAY_DEFAULT, 2); dev->ops->acpi_fill_ssdt_generator = fill_ssdt; + if (CONFIG(BOARD_LENOVO_X200)) + init_dock(); } struct chip_operations mainboard_ops = { diff --git a/src/mainboard/lenovo/x200/variants/x200/dock.c b/src/mainboard/lenovo/x200/variants/x200/dock.c index bdd65a564a..8aa39bbd6e 100644 --- a/src/mainboard/lenovo/x200/variants/x200/dock.c +++ b/src/mainboard/lenovo/x200/variants/x200/dock.c @@ -23,7 +23,7 @@ #include "../../dock.h" -void h8_mainboard_init_dock(void) +void init_dock(void) { if (dock_present()) { printk(BIOS_DEBUG, "dock is connected\n"); diff --git a/src/mainboard/lenovo/x200/variants/x301/dock.c b/src/mainboard/lenovo/x200/variants/x301/dock.c deleted file mode 100644 index f8a2dc4260..0000000000 --- a/src/mainboard/lenovo/x200/variants/x301/dock.c +++ /dev/null @@ -1,22 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 Sven Schnelle - * Copyright (C) 2013 Vladimir Serbinenko - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include - -void h8_mainboard_init_dock(void) -{ -} diff --git a/src/mainboard/lenovo/x201/dock.c b/src/mainboard/lenovo/x201/dock.c index 652a144104..58510ced89 100644 --- a/src/mainboard/lenovo/x201/dock.c +++ b/src/mainboard/lenovo/x201/dock.c @@ -22,7 +22,7 @@ #include #include -void h8_mainboard_init_dock(void) +void init_dock(void) { if (dock_present()) { printk(BIOS_DEBUG, "dock is connected\n"); diff --git a/src/mainboard/lenovo/x201/dock.h b/src/mainboard/lenovo/x201/dock.h index 4cd8c857a8..6a08d81836 100644 --- a/src/mainboard/lenovo/x201/dock.h +++ b/src/mainboard/lenovo/x201/dock.h @@ -15,7 +15,7 @@ #ifndef THINKPAD_X201_DOCK_H #define THINKPAD_X201_DOCK_H - +void init_dock(void); void dock_connect(void); void dock_disconnect(void); int dock_present(void); diff --git a/src/mainboard/lenovo/x201/mainboard.c b/src/mainboard/lenovo/x201/mainboard.c index c021db185c..a403237e27 100644 --- a/src/mainboard/lenovo/x201/mainboard.c +++ b/src/mainboard/lenovo/x201/mainboard.c @@ -42,6 +42,8 @@ static void mainboard_enable(struct device *dev) install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_INT_LVDS, GMA_INT15_PANEL_FIT_DEFAULT, GMA_INT15_BOOT_DISPLAY_LFP, 2); + + init_dock(); } struct chip_operations mainboard_ops = { diff --git a/src/mainboard/lenovo/x220/mainboard.c b/src/mainboard/lenovo/x220/mainboard.c index 29c15e0f5a..144fde7f2e 100644 --- a/src/mainboard/lenovo/x220/mainboard.c +++ b/src/mainboard/lenovo/x220/mainboard.c @@ -29,10 +29,6 @@ static void mainboard_enable(struct device *dev) GMA_INT15_BOOT_DISPLAY_DEFAULT, 0); } -void h8_mainboard_init_dock (void) -{ -} - struct chip_operations mainboard_ops = { .enable_dev = mainboard_enable, }; diff --git a/src/mainboard/lenovo/x230/mainboard.c b/src/mainboard/lenovo/x230/mainboard.c index 29c15e0f5a..144fde7f2e 100644 --- a/src/mainboard/lenovo/x230/mainboard.c +++ b/src/mainboard/lenovo/x230/mainboard.c @@ -29,10 +29,6 @@ static void mainboard_enable(struct device *dev) GMA_INT15_BOOT_DISPLAY_DEFAULT, 0); } -void h8_mainboard_init_dock (void) -{ -} - struct chip_operations mainboard_ops = { .enable_dev = mainboard_enable, }; diff --git a/src/mainboard/lenovo/x60/Kconfig b/src/mainboard/lenovo/x60/Kconfig index e3aabf3485..a1a5fec7c0 100644 --- a/src/mainboard/lenovo/x60/Kconfig +++ b/src/mainboard/lenovo/x60/Kconfig @@ -22,7 +22,6 @@ config BOARD_SPECIFIC_OPTIONS select HAVE_ACPI_TABLES select HAVE_ACPI_RESUME select USE_OPTION_TABLE - select H8_DOCK_EARLY_INIT select DRIVERS_LENOVO_WACOM select I945_LVDS select INTEL_GMA_HAVE_VBT From de6f1218971135a877938f00b03e54fb51c2ab44 Mon Sep 17 00:00:00 2001 From: Hung-Te Lin Date: Sat, 9 Nov 2019 12:00:51 +0800 Subject: [PATCH 0124/1242] mb/google/kukui: Add new configs 'damu' and 'kappa' New boards introduced to Kukui family. BUG=None TEST=make # select damu and kappa Change-Id: I7154aeee921114b7d12bf586adca250df19a3883 Signed-off-by: Hung-Te Lin Reviewed-on: https://review.coreboot.org/c/coreboot/+/36699 Tested-by: build bot (Jenkins) Reviewed-by: Yu-Ping Wu Reviewed-by: Julius Werner --- src/mainboard/google/kukui/Kconfig | 2 ++ src/mainboard/google/kukui/Kconfig.name | 8 ++++++++ 2 files changed, 10 insertions(+) diff --git a/src/mainboard/google/kukui/Kconfig b/src/mainboard/google/kukui/Kconfig index e6d604e5e7..b909f1dd84 100644 --- a/src/mainboard/google/kukui/Kconfig +++ b/src/mainboard/google/kukui/Kconfig @@ -56,6 +56,8 @@ config MAINBOARD_PART_NUMBER default "Flapjack" if BOARD_GOOGLE_FLAPJACK default "Jacuzzi" if BOARD_GOOGLE_JACUZZI default "Juniper" if BOARD_GOOGLE_JUNIPER + default "Kappa" if BOARD_GOOGLE_KAPPA + default "Damu" if BOARD_GOOGLE_DAMU config DRIVER_TPM_SPI_BUS hex diff --git a/src/mainboard/google/kukui/Kconfig.name b/src/mainboard/google/kukui/Kconfig.name index c7772dd401..223e76a965 100644 --- a/src/mainboard/google/kukui/Kconfig.name +++ b/src/mainboard/google/kukui/Kconfig.name @@ -23,3 +23,11 @@ config BOARD_GOOGLE_JACUZZI config BOARD_GOOGLE_JUNIPER bool "-> Juniper" select BOARD_GOOGLE_KUKUI_COMMON + +config BOARD_GOOGLE_KAPPA + bool "-> Kappa" + select BOARD_GOOGLE_KUKUI_COMMON + +config BOARD_GOOGLE_DAMU + bool "-> Damu" + select BOARD_GOOGLE_KUKUI_COMMON From 6de0c141fd2dff4114e674b6ab93d88628993f5e Mon Sep 17 00:00:00 2001 From: Subrata Banik Date: Tue, 12 Nov 2019 10:38:50 +0530 Subject: [PATCH 0125/1242] soc/intel/tigerlake: Remove deprecated CONFIG_SOC_INTEL_COMMON_BLOCK_SA_FSP_TOLUM CB:36620 moves common cbmem_top_chipset to fsp driver hence no need to have dedicated kconfig as in SOC_INTEL_COMMON_BLOCK_SA_FSP_TOLUM Change-Id: I3914993754ba409867399e903e5d13e929a92e1d Signed-off-by: Subrata Banik Reviewed-on: https://review.coreboot.org/c/coreboot/+/36765 Tested-by: build bot (Jenkins) Reviewed-by: V Sowmya Reviewed-by: Arthur Heymans Reviewed-by: Angel Pons --- src/soc/intel/tigerlake/Kconfig | 1 - 1 file changed, 1 deletion(-) diff --git a/src/soc/intel/tigerlake/Kconfig b/src/soc/intel/tigerlake/Kconfig index 8ec4354448..c0fb7080e8 100644 --- a/src/soc/intel/tigerlake/Kconfig +++ b/src/soc/intel/tigerlake/Kconfig @@ -43,7 +43,6 @@ config CPU_SPECIFIC_OPTIONS select SOC_INTEL_COMMON_BLOCK_CHIP_CONFIG select SOC_INTEL_COMMON_BLOCK_CPU select SOC_INTEL_COMMON_BLOCK_CPU_MPINIT - select SOC_INTEL_COMMON_BLOCK_SA_FSP_TOLUM select SOC_INTEL_COMMON_BLOCK_GSPI_VERSION_2 select SOC_INTEL_COMMON_BLOCK_HDA select SOC_INTEL_COMMON_BLOCK_SA From 8a0dccc02beaa8de4d7359707170e8a914bc69c7 Mon Sep 17 00:00:00 2001 From: Elyes HAOUAS Date: Wed, 24 Jul 2019 10:14:20 +0200 Subject: [PATCH 0126/1242] vendorcode/intel/Kconfig: Hide UDK_VERSION when unneeded This cleans .config from unused UDK_VERSION's symbol. Change-Id: I2a17db711f615d388dbd964f67ff2cc7875c54fb Signed-off-by: Elyes HAOUAS Reviewed-on: https://review.coreboot.org/c/coreboot/+/34536 Reviewed-by: Nico Huber Tested-by: build bot (Jenkins) --- src/vendorcode/intel/Kconfig | 2 ++ 1 file changed, 2 insertions(+) diff --git a/src/vendorcode/intel/Kconfig b/src/vendorcode/intel/Kconfig index 7b5099514c..f341cfd7c5 100644 --- a/src/vendorcode/intel/Kconfig +++ b/src/vendorcode/intel/Kconfig @@ -28,6 +28,7 @@ config UDK_2015_BINDING config UDK_2017_BINDING def_bool n +if (UEFI_2_4_BINDING || UDK_2015_BINDING || UDK_2017_BINDING) config UDK_2013_VERSION int default 2013 @@ -47,3 +48,4 @@ config UDK_VERSION default UDK_2013_VERSION help UEFI Development Kit version for Platform +endif # {UEFI,UDK}_BINDING From 71a94301c08311ce385360f7c152497496295dde Mon Sep 17 00:00:00 2001 From: Patrick Georgi Date: Mon, 11 Nov 2019 17:13:54 +0100 Subject: [PATCH 0127/1242] Documentation: Add more entries to 4.11 release notes MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Change-Id: I1b013c4d7012f1db9591bea98ec1fe7acbc85afe Signed-off-by: Patrick Georgi Reviewed-on: https://review.coreboot.org/c/coreboot/+/36751 Reviewed-by: Kyösti Mälkki Reviewed-by: HAOUAS Elyes Tested-by: build bot (Jenkins) --- .../releases/coreboot-4.11-relnotes.md | 45 +++++++++++++++++-- 1 file changed, 42 insertions(+), 3 deletions(-) diff --git a/Documentation/releases/coreboot-4.11-relnotes.md b/Documentation/releases/coreboot-4.11-relnotes.md index d4fed06e68..b4515ffb9f 100644 --- a/Documentation/releases/coreboot-4.11-relnotes.md +++ b/Documentation/releases/coreboot-4.11-relnotes.md @@ -18,14 +18,17 @@ using AGESA family 12h, and because there were multiple, unique Coverity issues with it, the associated vendorcode will be removed shortly after this release. +Support for the MIPS architecture will also be removed shortly after +this release as the only board in the tree was a discontinued development +board and no other work has picked up MIPS support, so it's very likely +broken already. + Significant changes ------------------- -### Add significant changes here - ### `__PRE_RAM__` is deprecated -Preprocessor use of `defined(__PRE_RAM_)` have been mostly replaced with +Preprocessor use of `defined(__PRE_RAM__)` have been mostly replaced with `if (ENV_ROMSTAGE_OR_BEFORE)` or the inverse `if (ENV_RAMSTAGE)`. The remaining cases and `-D__PRE_RAM__` are to be removed soon after release. @@ -50,6 +53,42 @@ removed soon after release. Significant refactoring has bee done to achieve some consistency across platforms and to reduce code duplication. +### Build system amenities ### + +The build system now has an `all` class of source files to remove the need to +list source files for each and every source class (romstage, ramstage, ...) + +The site-local/ mechanism became more robust. + +### Stricter coding standards to improve security ### + +The build now fails on variable length arrays (that make it way too easy to +smash a stack) and case statements falling through without a note that it is +intentional. + +### Shorter file headers ### + +This project is still under way, but we started moving author information +from individual files into the global AUTHORS file (and there's the git +history for more details). + +In the future, we also want to replace the license headers (lots of lines) +in each file with spdx identifiers (one line) and so we added a LICENSES/ +directory that contains the full text of all the licenses that are used +throughout our tree. + +### Variant creation scripts ### + +To ease the creation of variant boards, `util/mainboard/` now contains +scripts to generate a new variant to a given board. These are still +specific to google/hatch at this time, but they're written with the idea +of becoming more generally useful. + +### Payloads ### + +Payload integration has been updated, coreinfo learned to cope with +UPPER CASE commands and libpayload knows how to deal with USB3 hubs. + ### Added VBOOT support to the following platforms: * intel/gm45 * intel/nehalem From 1b8102474e4b85935719cd7551f047ede807ee02 Mon Sep 17 00:00:00 2001 From: Werner Zeh Date: Mon, 11 Nov 2019 14:17:27 +0100 Subject: [PATCH 0128/1242] mb/siemens/mc_apl6: Enable VT-d feature This mainboard needs VT-d to be enabled. Do so in devicetree. Change-Id: I9f2f733163be019ac329660d7633b48c5d7896f1 Signed-off-by: Werner Zeh Reviewed-on: https://review.coreboot.org/c/coreboot/+/36749 Tested-by: build bot (Jenkins) Reviewed-by: Mario Scheithauer --- src/mainboard/siemens/mc_apl1/variants/mc_apl6/devicetree.cb | 3 +++ 1 file changed, 3 insertions(+) diff --git a/src/mainboard/siemens/mc_apl1/variants/mc_apl6/devicetree.cb b/src/mainboard/siemens/mc_apl1/variants/mc_apl6/devicetree.cb index e12972ccd8..3b52f65398 100644 --- a/src/mainboard/siemens/mc_apl1/variants/mc_apl6/devicetree.cb +++ b/src/mainboard/siemens/mc_apl1/variants/mc_apl6/devicetree.cb @@ -14,6 +14,9 @@ chip soc/intel/apollolake register "pcie_rp_clkreq_pin[4]" = "CLKREQ_DISABLED" register "pcie_rp_clkreq_pin[5]" = "CLKREQ_DISABLED" + # Enable Vtd feature + register "enable_vtd" = "1" + device domain 0 on device pci 00.0 on end # - Host Bridge device pci 00.1 off end # - DPTF From 8088584b37b96532d87d0b8a000925313a237749 Mon Sep 17 00:00:00 2001 From: Werner Zeh Date: Mon, 11 Nov 2019 15:52:55 +0100 Subject: [PATCH 0129/1242] payloads/external/GRUB2: Check for existing grub2 directory MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit When 'make clean' is executed and there is no source code cloned for GRUB2 in payloads/external/GRUB2/grub2 (so GRUB2 has never been used on this tree) an error message is thrown: "fatal: cannot change to 'grub2': No such file or directory" This error happens when there is no grub2 directory and is caused by line 20 in payloads/external/GRUB2/Makefile where a shell command is used to check the state of the git repo for grub2. Thought the target for this code (checkout) is not executed by 'make clean' the shell evaluates the command as part of the Makefile sourcing and encounters a missing directory. This patch fixes this error by checking for the project directory before the git status of the repo is evaluated. Change-Id: Ieaa919e1ee5ec2a1ec3c840fa07a6ec16d230e88 Signed-off-by: Werner Zeh Reviewed-on: https://review.coreboot.org/c/coreboot/+/36750 Tested-by: build bot (Jenkins) Reviewed-by: Michael Niewöhner Reviewed-by: Patrick Georgi --- payloads/external/GRUB2/Makefile | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/payloads/external/GRUB2/Makefile b/payloads/external/GRUB2/Makefile index 20afdc36c4..f13c12892a 100644 --- a/payloads/external/GRUB2/Makefile +++ b/payloads/external/GRUB2/Makefile @@ -17,7 +17,8 @@ checkout: echo " GIT GRUB2 $(NAME-y)" test -d $(project_dir) || git clone $(project_git_repo) $(project_dir) git -C $(project_dir) fetch -ifeq ("$(shell git -C $(project_dir) status --ignored=no --untracked-files=no --porcelain)",) +ifeq ("$(shell test -d $(project_dir) && \ + (git -C $(project_dir) status --ignored=no --untracked-files=no --porcelain))",) git -C $(project_dir) checkout -f $(TAG-y) else echo "WARNING: index/tree not clean, skipping update / force checkout." From 675cb9152e6704383cf402c55758ddea2c7a1e05 Mon Sep 17 00:00:00 2001 From: Bill XIE Date: Tue, 12 Nov 2019 01:19:25 +0800 Subject: [PATCH 0130/1242] util/autoport: Stop generate empty h8_mainboard_init_dock(). CB:36385 makes dock init in ramstage fully mainboard-specific, so keeping generating empty h8_mainboard_init_dock() for lenovo EC becomes unnecessary and problematic. Change-Id: I19f57f41403ffd0319cc86f21bec7e142095df83 Signed-off-by: Bill XIE Reviewed-on: https://review.coreboot.org/c/coreboot/+/36752 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi --- util/autoport/ec_lenovo.go | 14 -------------- util/autoport/readme.md | 6 +++--- 2 files changed, 3 insertions(+), 17 deletions(-) diff --git a/util/autoport/ec_lenovo.go b/util/autoport/ec_lenovo.go index c2dd333c73..9384896dc8 100644 --- a/util/autoport/ec_lenovo.go +++ b/util/autoport/ec_lenovo.go @@ -59,20 +59,6 @@ Method(_PTS,1) si.WriteString("#include \n") - dock := Create(ctx, "dock.c") - defer dock.Close() - - AddRAMStageFile("dock.c", "") - - dock.WriteString( - `#include - -void h8_mainboard_init_dock (void) -{ -/* FIXME: fill this if needed. */ -} -`) - /* FIXME:XX Move this to ec/lenovo. */ smi := Create(ctx, "smihandler.c") defer smi.Close() diff --git a/util/autoport/readme.md b/util/autoport/readme.md index fa349b906f..6d1c64c3eb 100644 --- a/util/autoport/readme.md +++ b/util/autoport/readme.md @@ -407,9 +407,9 @@ Keep `GPE_EC_WAKE` and `GPE_EC_SCI` in sync with `gpi*_routing`. `gpi*_routing` matching `GPE_EC_WAKE` or `GPE_EC_SCI` is set to `2` and all others are absent. -If your dock has LPC wires or needs some special treatement you -need to fill `h8_mainboard_init_dock` and add support code to -DSDT. See the code for `x60`, `x200` or `x201` +If your dock has LPC wires or needs some special treatement you may +need to add codes to initialize the dock and support code to +DSDT. See the `init_dock()` for `x60`, `x200` or `x201`. ## EC (generic laptop) From fecf77770b8e68b9ef82021ca53c31db93736d93 Mon Sep 17 00:00:00 2001 From: Arthur Heymans Date: Sat, 9 Nov 2019 14:19:04 +0100 Subject: [PATCH 0131/1242] sb/intel/i82801gx: Add common LPC decode code Generic LPC decode ranges can now be set from the devicetree. Change-Id: I1065ec770ad3a743286859efa39dca09ccb733a1 Signed-off-by: Arthur Heymans Reviewed-on: https://review.coreboot.org/c/coreboot/+/36700 Tested-by: build bot (Jenkins) Reviewed-by: HAOUAS Elyes Reviewed-by: Nico Huber Reviewed-by: Angel Pons --- src/mainboard/apple/macbook21/devicetree.cb | 4 + src/mainboard/apple/macbook21/romstage.c | 110 +----------------- src/mainboard/asrock/g41c-gs/romstage.c | 11 +- .../g41c-gs/variants/g41c-gs-r2/devicetree.cb | 2 + .../g41c-gs/variants/g41c-gs/devicetree.cb | 2 + .../g41c-gs/variants/g41m-gs/devicetree.cb | 2 + .../g41c-gs/variants/g41m-s3/devicetree.cb | 2 + .../variants/g41m-vs3-r2/devicetree.cb | 2 + src/mainboard/asus/p5gc-mx/devicetree.cb | 3 + src/mainboard/asus/p5gc-mx/romstage.c | 16 +-- src/mainboard/asus/p5qpl-am/devicetree.cb | 2 + src/mainboard/asus/p5qpl-am/romstage.c | 15 +-- src/mainboard/foxconn/d41s/devicetree.cb | 2 + src/mainboard/foxconn/d41s/early_init.c | 11 -- src/mainboard/foxconn/g41s-k/devicetree.cb | 2 + src/mainboard/foxconn/g41s-k/romstage.c | 12 +- src/mainboard/getac/p470/devicetree.cb | 4 + src/mainboard/getac/p470/romstage.c | 18 +-- .../gigabyte/ga-945gcm-s2l/devicetree.cb | 3 + .../gigabyte/ga-945gcm-s2l/romstage.c | 18 +-- .../gigabyte/ga-g41m-es2l/devicetree.cb | 2 + .../gigabyte/ga-g41m-es2l/romstage.c | 15 +-- src/mainboard/ibase/mb899/devicetree.cb | 3 + src/mainboard/ibase/mb899/romstage.c | 18 +-- src/mainboard/intel/d945gclf/devicetree.cb | 2 + src/mainboard/intel/d945gclf/romstage.c | 15 +-- src/mainboard/intel/dg41wv/devicetree.cb | 2 + src/mainboard/intel/dg41wv/romstage.c | 15 +-- src/mainboard/kontron/986lcd-m/devicetree.cb | 5 + src/mainboard/kontron/986lcd-m/romstage.c | 23 +--- src/mainboard/lenovo/t60/devicetree.cb | 4 + src/mainboard/lenovo/t60/romstage.c | 21 +--- .../lenovo/thinkcentre_a58/devicetree.cb | 2 + .../lenovo/thinkcentre_a58/romstage.c | 14 +-- src/mainboard/lenovo/x60/devicetree.cb | 4 + src/mainboard/lenovo/x60/romstage.c | 20 +--- src/mainboard/roda/rk886ex/devicetree.cb | 4 + src/mainboard/roda/rk886ex/romstage.c | 21 +--- src/southbridge/intel/i82801gx/Makefile.inc | 2 + .../intel/i82801gx/bootblock_gcc.c | 2 + src/southbridge/intel/i82801gx/chip.h | 6 + src/southbridge/intel/i82801gx/early_init.c | 52 +++++++++ src/southbridge/intel/i82801gx/i82801gx.h | 1 + 43 files changed, 156 insertions(+), 338 deletions(-) create mode 100644 src/southbridge/intel/i82801gx/early_init.c diff --git a/src/mainboard/apple/macbook21/devicetree.cb b/src/mainboard/apple/macbook21/devicetree.cb index 5ce28a27a9..137c8fc929 100644 --- a/src/mainboard/apple/macbook21/devicetree.cb +++ b/src/mainboard/apple/macbook21/devicetree.cb @@ -77,6 +77,10 @@ chip northbridge/intel/i945 register "c3_latency" = "0x23" register "p_cnt_throttling_supported" = "1" + register "gen1_dec" = "0x000c0681" + register "gen2_dec" = "0x000c1641" + register "gen4_dec" = "0x001c0301" + device pci 1b.0 on # Audio Controller subsystemid 0x8384 0x7680 end diff --git a/src/mainboard/apple/macbook21/romstage.c b/src/mainboard/apple/macbook21/romstage.c index 34cd378839..aced71ce6a 100644 --- a/src/mainboard/apple/macbook21/romstage.c +++ b/src/mainboard/apple/macbook21/romstage.c @@ -27,114 +27,6 @@ #include #include -static void ich7_enable_lpc(void) -{ - /* Enable Serial IRQ */ - pci_write_config8(PCI_DEV(0, 0x1f, 0), SERIRQ_CNTL, 0xd0); - - /* I/O Decode Ranges - * X60: 0x0210 == 00000010 00010000 - * Macbook21: 0x0010 == 00000000 00010000 - * Bit 9:8 LPT Decode Range. This field determines which range to - * decode for the LPT Port. - * 00 = 378h - 37Fh and 778h - 77Fh - * 10 = 3BCh - 3BEh and 7BCh - 7BEh - */ - pci_write_config16(PCI_DEV(0, 0x1f, 0), LPC_IO_DEC, 0x0010); - - /* LPC_EN--LPC I/F Enables Register - * X60: 0x1f0d == 00011111 00001101 - * Macbook21: 0x3807 == 00111000 00000111 - * Bit 13 CNF2_LPC_EN -- R/W. Microcontroller Enable # 2. - * 0 = Disable. - * 1 = Enables the decoding of the I/O locations 4Eh and 4Fh - * to the LPC interface. This range is used for a - * microcontroller. - * Bit 12 CNF1_LPC_EN -- R/W. Super I/O Enable. - * 0 = Disable. - * 1 = Enables the decoding of the I/O locations 2Eh and 2Fh - * to the LPC interface. This range is used for - * Super I/O devices. - * Bit 11 MC_LPC_EN -- R/W. Microcontroller Enable # 1. - * 0 = Disable. - * 1 = Enables the decoding of the I/O locations 62h and 66h - * to the LPC interface. This range is used for a - * microcontroller. - * Bit 10 KBC_LPC_EN -- R/W. Keyboard Enable. - * 0 = Disable. - * 1 = Enables the decoding of the I/O locations 60h and 64h - * to the LPC interface. This range is used for a - * microcontroller. - * Bit 9 GAMEH_LPC_EN -- R/W. High Gameport Enable - * 0 = Disable. - * 1 = Enables the decoding of the I/O locations 208h to 20Fh - * to the LPC interface. This range is used for a gameport. - * Bit 8 GAMEL_LPC_EN -- R/W. Low Gameport Enable - * 0 = Disable. - * 1 = Enables the decoding of the I/O locations 200h to 207h - * to the LPC interface. This range is used for a gameport. - * Bit 3 FDD_LPC_EN -- R/W. Floppy Drive Enable - * 0 = Disable. - * 1 = Enables the decoding of the FDD range to the LPC - * interface. This range is selected in the LPC_FDD/LPT - * Decode Range Register (D31:F0:80h, bit 12). - * Bit 2 LPT_LPC_EN -- R/W. Parallel Port Enable - * 0 = Disable. - * 1 = Enables the decoding of the LPT range to the LPC - * interface. This range is selected in the LPC_FDD/LPT - * Decode Range Register (D31:F0:80h, bit 9:8). - * Bit 1 COMB_LPC_EN -- R/W. Com Port B Enable - * 0 = Disable. - * 1 = Enables the decoding of the COMB range to the LPC - * interface. This range is selected in the LPC_COM Decode - * Range Register (D31:F0:80h, bits 6:4). - * Bit 0 COMA_LPC_EN -- R/W. Com Port A Enable - * 0 = Disable. - * 1 = Enables the decoding of the COMA range to the LPC - * interface. This range is selected in the LPC_COM Decode - * Range Register (D31:F0:80h, bits 3:2). - */ - pci_write_config16(PCI_DEV(0, 0x1f, 0), LPC_EN, CNF2_LPC_EN - | CNF1_LPC_EN | MC_LPC_EN | LPT_LPC_EN | COMB_LPC_EN - | COMA_LPC_EN); - - /* GEN1_DEC, LPC Interface Generic Decode Range 1 - * X60: 0x1601 0x007c == 00000000 01111100 00010110 00000001 - * Macbook21: 0x0681 0x000c == 00000000 00001100 00000110 10000001 - * Bit 31:24 Reserved. - * Bit 23:18 Generic I/O Decode Range Address[7:2] Mask: A `1' in any - * bit position indicates that any value in the corresponding - * address bit in a received cycle will be treated as a - * match. The corresponding bit in the Address field, below, - * is ignored. The mask is only provided for the lower 6 bits - * of the DWord address, allowing for decoding blocks up to - * 256 bytes in size. - * Bit 17:16 Reserved. - * Bit 15:2 Generic I/O Decode Range 1 Base Address (GEN1_BASE). This - * address is aligned on a 128-byte boundary, and must have - * address lines 31:16 as 0. NOTE: The Intel ICH7 does not - * provide decode down to the word or byte level. - * Bit 1 Reserved. - * Bit 0 Generic Decode Range 1 Enable (GEN1_EN) -- R/W. - * 0 = Disable. - * 1 = Enable the GEN1 I/O range to be forwarded to the LPC - * I/F - */ - pci_write_config32(PCI_DEV(0, 0x1f, 0), GEN1_DEC, 0x000c0681); - - /* GEN2_DEC, LPC Interface Generic Decode Range 2 - * X60: 0x15e1 0x000c == 00000000 00001100 00010101 11100001 - * Macbook21: 0x1641 0x000c == 00000000 00001100 00010110 01000001 - */ - pci_write_config32(PCI_DEV(0, 0x1f, 0), GEN2_DEC, 0x000c1641); - - /* GEN4_DEC, LPC Interface Generic Decode Range 4 - * X60: 0x0000 0x0000 - * Macbook21: 0x0301 0x001c == 00000000 00011100 00000011 00000001 - */ - pci_write_config32(PCI_DEV(0, 0x1f, 0), GEN4_DEC, 0x001c0301); -} - static void rcba_config(void) { /* V0CTL Virtual Channel 0 Resource Control */ @@ -205,7 +97,7 @@ void mainboard_romstage_entry(void) enable_lapic(); - ich7_enable_lpc(); + i82801gx_lpc_setup(); /* Set up the console */ console_init(); diff --git a/src/mainboard/asrock/g41c-gs/romstage.c b/src/mainboard/asrock/g41c-gs/romstage.c index 57d1ec2c2c..9de168c5e4 100644 --- a/src/mainboard/asrock/g41c-gs/romstage.c +++ b/src/mainboard/asrock/g41c-gs/romstage.c @@ -66,15 +66,6 @@ static void mb_lpc_setup(void) ich7_setup_cir(); } -static void ich7_enable_lpc(void) -{ - pci_write_config8(PCI_DEV(0, 0x1f, 0), SERIRQ_CNTL, 0xd0); - /* Decode range */ - pci_write_config16(PCI_DEV(0, 0x1f, 0), LPC_EN, CNF1_LPC_EN - | KBC_LPC_EN | LPT_LPC_EN | COMA_LPC_EN); - pci_write_config32(PCI_DEV(0, 0x1f, 0), GEN1_DEC, 0x000c0291); -} - void mainboard_romstage_entry(void) { // ch0 ch1 @@ -83,7 +74,7 @@ void mainboard_romstage_entry(void) u8 s3_resume; /* Set southbridge and Super I/O GPIOs. */ - ich7_enable_lpc(); + i82801gx_lpc_setup(); mb_lpc_setup(); console_init(); diff --git a/src/mainboard/asrock/g41c-gs/variants/g41c-gs-r2/devicetree.cb b/src/mainboard/asrock/g41c-gs/variants/g41c-gs-r2/devicetree.cb index acb8ac6702..b68aaa9fa7 100644 --- a/src/mainboard/asrock/g41c-gs/variants/g41c-gs-r2/devicetree.cb +++ b/src/mainboard/asrock/g41c-gs/variants/g41c-gs-r2/devicetree.cb @@ -54,6 +54,8 @@ chip northbridge/intel/x4x # Northbridge register "sata_ports_implemented" = "0x3" register "gpe0_en" = "0x440" + register "gen1_dec" = "0x000c0291" # Superio HWM + device pci 1b.0 on # Audio subsystemid 0x1849 0x3662 end diff --git a/src/mainboard/asrock/g41c-gs/variants/g41c-gs/devicetree.cb b/src/mainboard/asrock/g41c-gs/variants/g41c-gs/devicetree.cb index 805f2dac93..160d025ca7 100644 --- a/src/mainboard/asrock/g41c-gs/variants/g41c-gs/devicetree.cb +++ b/src/mainboard/asrock/g41c-gs/variants/g41c-gs/devicetree.cb @@ -48,6 +48,8 @@ chip northbridge/intel/x4x # Northbridge register "ide_enable_primary" = "0x1" register "gpe0_en" = "0x440" + register "gen1_dec" = "0x000c0291" # Superio HWM + device pci 1b.0 on # Audio subsystemid 0x1849 0x3662 end diff --git a/src/mainboard/asrock/g41c-gs/variants/g41m-gs/devicetree.cb b/src/mainboard/asrock/g41c-gs/variants/g41m-gs/devicetree.cb index f4d1dc4291..0a8f27546d 100644 --- a/src/mainboard/asrock/g41c-gs/variants/g41m-gs/devicetree.cb +++ b/src/mainboard/asrock/g41c-gs/variants/g41m-gs/devicetree.cb @@ -49,6 +49,8 @@ chip northbridge/intel/x4x # Northbridge register "sata_ports_implemented" = "0x3" register "gpe0_en" = "0x440" + register "gen1_dec" = "0x000c0291" # Superio HWM + device pci 1b.0 on # Audio subsystemid 0x1849 0x3662 end diff --git a/src/mainboard/asrock/g41c-gs/variants/g41m-s3/devicetree.cb b/src/mainboard/asrock/g41c-gs/variants/g41m-s3/devicetree.cb index 2fd6e4f649..8119ced94c 100644 --- a/src/mainboard/asrock/g41c-gs/variants/g41m-s3/devicetree.cb +++ b/src/mainboard/asrock/g41c-gs/variants/g41m-s3/devicetree.cb @@ -47,6 +47,8 @@ chip northbridge/intel/x4x # Northbridge register "sata_ports_implemented" = "0x3" register "gpe0_en" = "0x440" + register "gen1_dec" = "0x000c0291" # Superio HWM + device pci 1b.0 on # Audio subsystemid 0x1849 0x3662 end diff --git a/src/mainboard/asrock/g41c-gs/variants/g41m-vs3-r2/devicetree.cb b/src/mainboard/asrock/g41c-gs/variants/g41m-vs3-r2/devicetree.cb index 5479faf3e9..e5e3cf9b90 100644 --- a/src/mainboard/asrock/g41c-gs/variants/g41m-vs3-r2/devicetree.cb +++ b/src/mainboard/asrock/g41c-gs/variants/g41m-vs3-r2/devicetree.cb @@ -48,6 +48,8 @@ chip northbridge/intel/x4x # Northbridge register "ide_enable_primary" = "0x1" register "gpe0_en" = "0x440" + register "gen1_dec" = "0x000c0291" # Superio HWM + device pci 1b.0 on # Audio subsystemid 0x1849 0x3662 end diff --git a/src/mainboard/asus/p5gc-mx/devicetree.cb b/src/mainboard/asus/p5gc-mx/devicetree.cb index 972dc5dc1f..b5409a25bb 100644 --- a/src/mainboard/asus/p5gc-mx/devicetree.cb +++ b/src/mainboard/asus/p5gc-mx/devicetree.cb @@ -55,6 +55,9 @@ chip northbridge/intel/i945 register "p_cnt_throttling_supported" = "0" + # SuperIO Power Management Events + register "gen1_dec" = "0x00040291" + device pci 1b.0 on # High Definition Audio ioapic_irq 2 INTA 0x10 end diff --git a/src/mainboard/asus/p5gc-mx/romstage.c b/src/mainboard/asus/p5gc-mx/romstage.c index 58dac6e71c..3287b76416 100644 --- a/src/mainboard/asus/p5gc-mx/romstage.c +++ b/src/mainboard/asus/p5gc-mx/romstage.c @@ -96,20 +96,6 @@ static u8 msr_get_fsb(void) return fsbcfg; } -static void ich7_enable_lpc(void) -{ - // Enable Serial IRQ - pci_write_config8(PCI_DEV(0, 0x1f, 0), SERIRQ_CNTL, 0xd0); - // Set COM1/COM2 decode range - pci_write_config16(PCI_DEV(0, 0x1f, 0), LPC_IO_DEC, 0x0010); - // Enable COM1 - pci_write_config16(PCI_DEV(0, 0x1f, 0), LPC_EN, CNF1_LPC_EN - | KBC_LPC_EN | FDD_LPC_EN | LPT_LPC_EN | COMB_LPC_EN - | COMA_LPC_EN); - // Enable SuperIO Power Management Events - pci_write_config32(PCI_DEV(0, 0x1f, 0), GEN1_DEC, 0x00040291); -} - static void rcba_config(void) { /* Enable IOAPIC */ @@ -156,7 +142,7 @@ void mainboard_romstage_entry(void) enable_lapic(); - ich7_enable_lpc(); + i82801gx_lpc_setup(); winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); diff --git a/src/mainboard/asus/p5qpl-am/devicetree.cb b/src/mainboard/asus/p5qpl-am/devicetree.cb index bc023d24c9..5012f88605 100644 --- a/src/mainboard/asus/p5qpl-am/devicetree.cb +++ b/src/mainboard/asus/p5qpl-am/devicetree.cb @@ -45,6 +45,8 @@ chip northbridge/intel/x4x # Northbridge register "ide_enable_primary" = "0x1" register "gpe0_en" = "0x04000440" + register "gen1_dec" = "0x00000295" # HWM + device pci 1b.0 on end # Audio device pci 1c.0 on end # PCIe 1: PCIe x1 slot device pci 1c.1 on # PCIe 2: NIC diff --git a/src/mainboard/asus/p5qpl-am/romstage.c b/src/mainboard/asus/p5qpl-am/romstage.c index 2836bf7941..4653b42267 100644 --- a/src/mainboard/asus/p5qpl-am/romstage.c +++ b/src/mainboard/asus/p5qpl-am/romstage.c @@ -143,19 +143,6 @@ static void mb_lpc_setup(void) ich7_setup_cir(); } -static void ich7_enable_lpc(void) -{ - pci_write_config8(LPC_DEV, SERIRQ_CNTL, 0xd0); - /* Fixed IO decode ranges */ - pci_write_config16(LPC_DEV, LPC_IO_DEC, 0x0010); - /* LPC enable devices */ - pci_write_config16(LPC_DEV, LPC_EN, CNF1_LPC_EN | KBC_LPC_EN - | FDD_LPC_EN | LPT_LPC_EN - | COMB_LPC_EN | COMA_LPC_EN); - /* IO decode range: HWM on 0x295 */ - pci_write_config32(LPC_DEV, 0x84, 0x000295); -} - void mainboard_romstage_entry(void) { // ch0 ch1 @@ -164,7 +151,7 @@ void mainboard_romstage_entry(void) u8 s3_resume; /* Set southbridge and Super I/O GPIOs. */ - ich7_enable_lpc(); + i82801gx_lpc_setup(); mb_lpc_setup(); winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); diff --git a/src/mainboard/foxconn/d41s/devicetree.cb b/src/mainboard/foxconn/d41s/devicetree.cb index a611ee35c5..19d3e10cfb 100644 --- a/src/mainboard/foxconn/d41s/devicetree.cb +++ b/src/mainboard/foxconn/d41s/devicetree.cb @@ -43,6 +43,8 @@ chip northbridge/intel/pineview # Northbridge register "sata_ports_implemented" = "0x3" register "gpe0_en" = "0x441" + register "gen1_dec" = "0x00fc0a01" # Environment Controller + device pci 1b.0 on end # Audio device pci 1c.0 on end # PCIe 1 device pci 1c.1 on # PCIe 2 (NIC) diff --git a/src/mainboard/foxconn/d41s/early_init.c b/src/mainboard/foxconn/d41s/early_init.c index 6568d96139..ab1dae14ca 100644 --- a/src/mainboard/foxconn/d41s/early_init.c +++ b/src/mainboard/foxconn/d41s/early_init.c @@ -26,17 +26,6 @@ void bootblock_mainboard_early_init(void) { - /* Disable Serial IRQ */ - pci_write_config8(PCI_DEV(0, 0x1f, 0), SERIRQ_CNTL, 0xd0); - /* Decode range */ - pci_or_config16(PCI_DEV(0, 0x1f, 0), LPC_IO_DEC, 0x0010); - pci_write_config16(PCI_DEV(0, 0x1f, 0), LPC_EN, CNF1_LPC_EN | KBC_LPC_EN - | FDD_LPC_EN | LPT_LPC_EN | COMB_LPC_EN - | COMA_LPC_EN); - - /* Environment Controller */ - pci_write_config32(PCI_DEV(0, 0x1f, 0), GEN1_DEC, 0x00fc0a01); - ite_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); } diff --git a/src/mainboard/foxconn/g41s-k/devicetree.cb b/src/mainboard/foxconn/g41s-k/devicetree.cb index b196e24961..270d1355f1 100644 --- a/src/mainboard/foxconn/g41s-k/devicetree.cb +++ b/src/mainboard/foxconn/g41s-k/devicetree.cb @@ -49,6 +49,8 @@ chip northbridge/intel/x4x # Northbridge register "ide_enable_secondary" = "0x0" register "sata_ports_implemented" = "0x3" + register "gen1_dec" = "0x003c0a01" # Super I/O EC and GPIO + device pci 1b.0 on end # Audio device pci 1c.0 on end # PCIe 1 device pci 1c.1 on # PCIe 2 (NIC) diff --git a/src/mainboard/foxconn/g41s-k/romstage.c b/src/mainboard/foxconn/g41s-k/romstage.c index 01473c80fc..f423c11378 100644 --- a/src/mainboard/foxconn/g41s-k/romstage.c +++ b/src/mainboard/foxconn/g41s-k/romstage.c @@ -70,16 +70,6 @@ static void mb_lpc_setup(void) ich7_setup_cir(); } -static void ich7_enable_lpc(void) -{ - pci_write_config16(LPC_DEV, LPC_IO_DEC, 0x0010); - pci_write_config16(LPC_DEV, LPC_EN, CNF1_LPC_EN | KBC_LPC_EN | - FDD_LPC_EN | COMB_LPC_EN | COMA_LPC_EN); - - /* Decode 64 bytes at 0x0a00 to LPC for Super I/O EC and GPIO. */ - pci_write_config32(LPC_DEV, GEN1_DEC, 0x003c0a01); -} - void mainboard_romstage_entry(void) { // ch0 ch1 @@ -94,7 +84,7 @@ void mainboard_romstage_entry(void) u8 s3_resume; /* Set up southbridge and Super I/O GPIOs. */ - ich7_enable_lpc(); + i82801gx_lpc_setup(); mb_lpc_setup(); ite_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); diff --git a/src/mainboard/getac/p470/devicetree.cb b/src/mainboard/getac/p470/devicetree.cb index 81ee9b17aa..e2001d91d1 100644 --- a/src/mainboard/getac/p470/devicetree.cb +++ b/src/mainboard/getac/p470/devicetree.cb @@ -62,6 +62,10 @@ chip northbridge/intel/i945 register "docking_supported" = "1" register "p_cnt_throttling_supported" = "1" + register "gen1_dec" = "0x001c02e1" + register "gen2_dec" = "0x00fc0601" + register "gen3_dec" = "0x00040069" + device pci 1b.0 on end # High Definition Audio device pci 1c.0 on end # PCIe port 1 device pci 1c.1 on end # PCIe port 2 diff --git a/src/mainboard/getac/p470/romstage.c b/src/mainboard/getac/p470/romstage.c index 6b5de90e74..e27194aab9 100644 --- a/src/mainboard/getac/p470/romstage.c +++ b/src/mainboard/getac/p470/romstage.c @@ -51,26 +51,17 @@ static void setup_special_ich7_gpios(void) outl(gpios, DEFAULT_GPIOBASE + 0x0c); /* GP_LVL */ } -static void ich7_enable_lpc(void) +/* Override the default lpc decode ranges */ +static void mb_lpc_decode(void) { int lpt_en = 0; if (read_option(lpt, 0) != 0) lpt_en = LPT_LPC_EN; - // Enable Serial IRQ - pci_write_config8(PCI_DEV(0, 0x1f, 0), SERIRQ_CNTL, 0xd0); // decode range pci_write_config16(PCI_DEV(0, 0x1f, 0), LPC_IO_DEC, 0x0007); // decode range - pci_write_config16(PCI_DEV(0, 0x1f, 0), LPC_EN, CNF2_LPC_EN | CNF1_LPC_EN - | MC_LPC_EN | KBC_LPC_EN | GAMEH_LPC_EN | GAMEL_LPC_EN - | FDD_LPC_EN| lpt_en | COMB_LPC_EN | COMA_LPC_EN); - // Enable 0x02e0 - 0x2ff - pci_write_config32(PCI_DEV(0, 0x1f, 0), GEN1_DEC, 0x001c02e1); - // Enable 0x600 - 0x6ff - pci_write_config32(PCI_DEV(0, 0x1f, 0), GEN2_DEC, 0x00fc0601); - // Enable 0x68 - 0x6f - pci_write_config32(PCI_DEV(0, 0x1f, 0), GEN3_DEC, 0x00040069); + pci_update_config32(PCI_DEV(0, 0x1f, 0), LPC_EN, ~LPT_LPC_EN, lpt_en); } /* This box has two superios, so enabling serial becomes slightly excessive. @@ -206,7 +197,8 @@ void mainboard_romstage_entry(void) enable_lapic(); - ich7_enable_lpc(); + i82801gx_lpc_setup(); + mb_lpc_decode(); early_superio_config(); /* Set up the console */ diff --git a/src/mainboard/gigabyte/ga-945gcm-s2l/devicetree.cb b/src/mainboard/gigabyte/ga-945gcm-s2l/devicetree.cb index f7e8ccc9a6..ff5d57b39f 100644 --- a/src/mainboard/gigabyte/ga-945gcm-s2l/devicetree.cb +++ b/src/mainboard/gigabyte/ga-945gcm-s2l/devicetree.cb @@ -79,6 +79,9 @@ chip northbridge/intel/i945 register "p_cnt_throttling_supported" = "0" + register "gen1_dec" = "0x000c0801" # ??? + register "gen2_dec" = "0x00040291" # Environment Controller + device pci 1b.0 on # High Definition Audio ioapic_irq 2 INTA 0x10 end diff --git a/src/mainboard/gigabyte/ga-945gcm-s2l/romstage.c b/src/mainboard/gigabyte/ga-945gcm-s2l/romstage.c index 3a2c86da87..9a9e9473e6 100644 --- a/src/mainboard/gigabyte/ga-945gcm-s2l/romstage.c +++ b/src/mainboard/gigabyte/ga-945gcm-s2l/romstage.c @@ -56,22 +56,6 @@ static void setup_sio(void) ite_reg_write(EC_DEV, 0x30, 0xff); // Enable } -static void ich7_enable_lpc(void) -{ - // Enable Serial IRQ - pci_write_config8(PCI_DEV(0, 0x1f, 0), SERIRQ_CNTL, 0xd0); - // Set COM1/COM2 decode range - pci_write_config16(PCI_DEV(0, 0x1f, 0), LPC_IO_DEC, 0x0000); - // Enable COM1 - pci_write_config16(PCI_DEV(0, 0x1f, 0), LPC_EN, CNF2_LPC_EN - | CNF1_LPC_EN | KBC_LPC_EN | FDD_LPC_EN | LPT_LPC_EN - | COMA_LPC_EN); - // Enable SuperIO Power Management Events - pci_write_config32(PCI_DEV(0, 0x1f, 0), GEN1_DEC, 0x000c0801); - /* LPC decode range 2: Environment Controller */ - pci_write_config32(PCI_DEV(0, 0x1f, 0), GEN2_DEC, 0x00040291); -} - static void rcba_config(void) { /* Enable IOAPIC */ @@ -115,7 +99,7 @@ void mainboard_romstage_entry(void) int s3resume = 0, boot_mode = 0; enable_lapic(); - ich7_enable_lpc(); + i82801gx_lpc_setup(); /* Enable SuperIO PM */ setup_sio(); ite_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); diff --git a/src/mainboard/gigabyte/ga-g41m-es2l/devicetree.cb b/src/mainboard/gigabyte/ga-g41m-es2l/devicetree.cb index 7045dbf8e1..13da3e8704 100644 --- a/src/mainboard/gigabyte/ga-g41m-es2l/devicetree.cb +++ b/src/mainboard/gigabyte/ga-g41m-es2l/devicetree.cb @@ -50,6 +50,8 @@ chip northbridge/intel/x4x # Northbridge register "sata_ports_implemented" = "0x3" register "gpe0_en" = "0x40" + register "gen2_dec" = "0x007c0291" # HWM + device pci 1b.0 on # Audio subsystemid 0x1458 0xa002 end diff --git a/src/mainboard/gigabyte/ga-g41m-es2l/romstage.c b/src/mainboard/gigabyte/ga-g41m-es2l/romstage.c index 8ba173eec6..fa69d122cb 100644 --- a/src/mainboard/gigabyte/ga-g41m-es2l/romstage.c +++ b/src/mainboard/gigabyte/ga-g41m-es2l/romstage.c @@ -98,19 +98,6 @@ static void mb_gpio_init(void) ich7_setup_cir(); } -static void ich7_enable_lpc(void) -{ - /* Disable Serial IRQ */ - pci_write_config8(PCI_DEV(0, 0x1f, 0), SERIRQ_CNTL, 0x00); - /* Decode range */ - pci_write_config16(PCI_DEV(0, 0x1f, 0), LPC_IO_DEC, 0x0010); - pci_write_config16(PCI_DEV(0, 0x1f, 0), LPC_EN, - CNF1_LPC_EN | CNF2_LPC_EN | KBC_LPC_EN | FDD_LPC_EN - | LPT_LPC_EN | COMA_LPC_EN | COMB_LPC_EN); - - pci_write_config32(PCI_DEV(0, 0x1f, 0), GEN2_DEC, 0x007c0291); -} - void mainboard_romstage_entry(void) { // ch0 ch1 @@ -119,7 +106,7 @@ void mainboard_romstage_entry(void) u8 s3_resume; /* Set southbridge and Super I/O GPIOs. */ - ich7_enable_lpc(); + i82801gx_lpc_setup(); mb_gpio_init(); ite_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); diff --git a/src/mainboard/ibase/mb899/devicetree.cb b/src/mainboard/ibase/mb899/devicetree.cb index 97f7a7b49d..78743bd453 100644 --- a/src/mainboard/ibase/mb899/devicetree.cb +++ b/src/mainboard/ibase/mb899/devicetree.cb @@ -39,6 +39,9 @@ chip northbridge/intel/i945 register "c3_latency" = "85" register "p_cnt_throttling_supported" = "0" + register "gen1_dec" = "0x00fc0291" + register "gen4_dec" = "0x00000301" + #device pci 1b.0 on end # High Definition Audio device pci 1c.0 on end # PCIe device pci 1c.1 on end # PCIe diff --git a/src/mainboard/ibase/mb899/romstage.c b/src/mainboard/ibase/mb899/romstage.c index 3b17e3b634..fd258af554 100644 --- a/src/mainboard/ibase/mb899/romstage.c +++ b/src/mainboard/ibase/mb899/romstage.c @@ -32,22 +32,6 @@ #define SERIAL_DEV PNP_DEV(0x4e, W83627EHG_SP1) #define SUPERIO_DEV PNP_DEV(0x4e, 0) -static void ich7_enable_lpc(void) -{ - // Enable Serial IRQ - pci_write_config8(PCI_DEV(0, 0x1f, 0), SERIRQ_CNTL, 0xd0); - // Set COM1/COM2 decode range - pci_write_config16(PCI_DEV(0, 0x1f, 0), LPC_IO_DEC, 0x0010); - // Enable COM1/COM2/KBD/SuperIO1+2 - pci_write_config16(PCI_DEV(0, 0x1f, 0), LPC_EN, CNF2_LPC_EN - | CNF1_LPC_EN | KBC_LPC_EN | FDD_LPC_EN | COMA_LPC_EN - | COMB_LPC_EN); - // Enable HWM at 0x290 - pci_write_config32(PCI_DEV(0, 0x1f, 0), GEN1_DEC, 0x00fc0291); - // io 0x300 decode - pci_write_config32(PCI_DEV(0, 0x1f, 0), GEN4_DEC, 0x00000301); -} - /* This box has one superio * Also set up the GPIOs from the beginning. This is the "no schematic * but safe anyways" method. @@ -178,7 +162,7 @@ void mainboard_romstage_entry(void) enable_lapic(); - ich7_enable_lpc(); + i82801gx_lpc_setup(); early_superio_config_w83627ehg(); /* Set up the console */ diff --git a/src/mainboard/intel/d945gclf/devicetree.cb b/src/mainboard/intel/d945gclf/devicetree.cb index c01465c4e7..7114a29a83 100644 --- a/src/mainboard/intel/d945gclf/devicetree.cb +++ b/src/mainboard/intel/d945gclf/devicetree.cb @@ -52,6 +52,8 @@ chip northbridge/intel/i945 register "c3_latency" = "85" register "p_cnt_throttling_supported" = "0" + register "gen1_dec" = "0x0007c0681" # SuperIO Power Management + device pci 1b.0 on end # High Definition Audio device pci 1c.0 on end # PCIe port 1 device pci 1c.1 off end # PCIe port 2 diff --git a/src/mainboard/intel/d945gclf/romstage.c b/src/mainboard/intel/d945gclf/romstage.c index f0ae18823e..ba01379548 100644 --- a/src/mainboard/intel/d945gclf/romstage.c +++ b/src/mainboard/intel/d945gclf/romstage.c @@ -28,19 +28,6 @@ #define SERIAL_DEV PNP_DEV(0x2e, LPC47M15X_SP1) #define PME_DEV PNP_DEV(0x2e, LPC47M15X_PME) -static void ich7_enable_lpc(void) -{ - // Enable Serial IRQ - pci_write_config8(PCI_DEV(0, 0x1f, 0), SERIRQ_CNTL, 0xd0); - // Set COM1/COM2 decode range - pci_write_config16(PCI_DEV(0, 0x1f, 0), LPC_IO_DEC, 0x0010); - // Enable COM1 - pci_write_config16(PCI_DEV(0, 0x1f, 0), LPC_EN, CNF1_LPC_EN | KBC_LPC_EN - | FDD_LPC_EN | LPT_LPC_EN | COMA_LPC_EN); - // Enable SuperIO Power Management Events - pci_write_config32(PCI_DEV(0, 0x1f, 0), GEN1_DEC, 0x007c0681); -} - static void rcba_config(void) { /* Set up virtual channel 0 */ @@ -98,7 +85,7 @@ void mainboard_romstage_entry(void) enable_lapic(); - ich7_enable_lpc(); + i82801gx_lpc_setup(); /* Enable SuperIO PM */ lpc47m15x_enable_serial(PME_DEV, 0x680); lpc47m15x_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); /* 0x3f8 */ diff --git a/src/mainboard/intel/dg41wv/devicetree.cb b/src/mainboard/intel/dg41wv/devicetree.cb index 295fbc4f38..c00e998bcc 100644 --- a/src/mainboard/intel/dg41wv/devicetree.cb +++ b/src/mainboard/intel/dg41wv/devicetree.cb @@ -65,6 +65,8 @@ chip northbridge/intel/x4x # Northbridge register "ide_enable_primary" = "0x1" register "gpe0_en" = "0x440" + register "gen1_dec" = "0x00fc0a01" # HWM + device pci 1b.0 on # Audio subsystemid 0x8086 0x5756 end diff --git a/src/mainboard/intel/dg41wv/romstage.c b/src/mainboard/intel/dg41wv/romstage.c index a6969ad4d2..c0127b6c45 100644 --- a/src/mainboard/intel/dg41wv/romstage.c +++ b/src/mainboard/intel/dg41wv/romstage.c @@ -56,19 +56,6 @@ static void mb_lpc_setup(void) ich7_setup_cir(); } -static void ich7_enable_lpc(void) -{ - pci_write_config8(LPC_DEV, SERIRQ_CNTL, 0xd0); - /* Fixed IO decode ranges */ - pci_write_config16(LPC_DEV, LPC_IO_DEC, 0x0010); - /* LPC enable devices */ - pci_write_config16(LPC_DEV, LPC_EN, CNF2_LPC_EN | CNF1_LPC_EN - | KBC_LPC_EN | FDD_LPC_EN | LPT_LPC_EN - | COMB_LPC_EN | COMA_LPC_EN); - /* IO decode range: HWM on 0xa00 */ - pci_write_config32(LPC_DEV, 0x84, 0x00fc0a01); -} - void mainboard_romstage_entry(void) { // ch0 ch1 @@ -77,7 +64,7 @@ void mainboard_romstage_entry(void) u8 s3_resume; /* Set southbridge and Super I/O GPIOs. */ - ich7_enable_lpc(); + i82801gx_lpc_setup(); mb_lpc_setup(); winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); diff --git a/src/mainboard/kontron/986lcd-m/devicetree.cb b/src/mainboard/kontron/986lcd-m/devicetree.cb index e2c0d88a0a..741c47b8f9 100644 --- a/src/mainboard/kontron/986lcd-m/devicetree.cb +++ b/src/mainboard/kontron/986lcd-m/devicetree.cb @@ -39,6 +39,11 @@ chip northbridge/intel/i945 register "c3_latency" = "85" register "p_cnt_throttling_supported" = "0" + register "gen1_dec" = "0x00fc0a01" # HWM + register "gen2_dec" = "0x000403e9" # COM3 + register "gen3_dec" = "0x000402e9" # COM4 + register "gen4_dec" = "0x00000301" # ?? + device pci 1b.0 on end # High Definition Audio device pci 1c.0 on end # PCIe device pci 1c.1 on end # PCIe diff --git a/src/mainboard/kontron/986lcd-m/romstage.c b/src/mainboard/kontron/986lcd-m/romstage.c index 229e3594c8..cb01046010 100644 --- a/src/mainboard/kontron/986lcd-m/romstage.c +++ b/src/mainboard/kontron/986lcd-m/romstage.c @@ -34,28 +34,14 @@ #define SERIAL_DEV PNP_DEV(0x2e, W83627THG_SP1) -static void ich7_enable_lpc(void) +/* Override the default lpc decode ranges */ +static void mb_lpc_decode(void) { int lpt_en = 0; if (read_option(lpt, 0) != 0) lpt_en = LPT_LPC_EN; /* enable LPT */ - /* Enable Serial IRQ */ - pci_write_config8(PCI_DEV(0, 0x1f, 0), SERIRQ_CNTL, 0xd0); - /* Set COM1/COM2 decode range */ - pci_write_config16(PCI_DEV(0, 0x1f, 0), LPC_IO_DEC, 0x0010); - /* Enable COM1/COM2/KBD/SuperIO1+2 */ - pci_write_config16(PCI_DEV(0, 0x1f, 0), LPC_EN, CNF2_LPC_EN - | CNF1_LPC_EN | KBC_LPC_EN | FDD_LPC_EN | COMA_LPC_EN - | COMB_LPC_EN | lpt_en); - /* Enable HWM at 0xa00 */ - pci_write_config32(PCI_DEV(0, 0x1f, 0), GEN1_DEC, 0x00fc0a01); - /* COM3 decode */ - pci_write_config32(PCI_DEV(0, 0x1f, 0), GEN2_DEC, 0x000403e9); - /* COM4 decode */ - pci_write_config32(PCI_DEV(0, 0x1f, 0), GEN3_DEC, 0x000402e9); - /* io 0x300 decode */ - pci_write_config32(PCI_DEV(0, 0x1f, 0), GEN4_DEC, 0x00000301); + pci_update_config16(PCI_DEV(0, 0x1f, 0), LPC_EN, ~LPT_LPC_EN, lpt_en); } /* This box has two superios, so enabling serial becomes slightly excessive. @@ -221,7 +207,8 @@ void mainboard_romstage_entry(void) enable_lapic(); - ich7_enable_lpc(); + i82801gx_lpc_setup(); + mb_lpc_decode(); early_superio_config_w83627thg(); /* Set up the console */ diff --git a/src/mainboard/lenovo/t60/devicetree.cb b/src/mainboard/lenovo/t60/devicetree.cb index 70900eae2c..ada50f39ce 100644 --- a/src/mainboard/lenovo/t60/devicetree.cb +++ b/src/mainboard/lenovo/t60/devicetree.cb @@ -82,6 +82,10 @@ chip northbridge/intel/i945 register "docking_supported" = "1" register "p_cnt_throttling_supported" = "1" + register "gen1_dec" = "0x007c1601" + register "gen2_dec" = "0x000c15e1" + register "gen3_dec" = "0x001c1681" + device pci 1b.0 on # Audio Controller subsystemid 0x17aa 0x2010 end diff --git a/src/mainboard/lenovo/t60/romstage.c b/src/mainboard/lenovo/t60/romstage.c index b003de8926..ac78aae841 100644 --- a/src/mainboard/lenovo/t60/romstage.c +++ b/src/mainboard/lenovo/t60/romstage.c @@ -32,25 +32,11 @@ #include #include "dock.h" -static void ich7_enable_lpc(void) +/* Override the default lpc decode ranges */ +static void mb_lpc_decode(void) { - // Enable Serial IRQ - pci_write_config8(PCI_DEV(0, 0x1f, 0), SERIRQ_CNTL, 0xd0); // decode range pci_write_config16(PCI_DEV(0, 0x1f, 0), LPC_IO_DEC, 0x0210); - // decode range - pci_write_config16(PCI_DEV(0, 0x1f, 0), LPC_EN, CNF1_LPC_EN | MC_LPC_EN - | KBC_LPC_EN | GAMEH_LPC_EN | GAMEL_LPC_EN | FDD_LPC_EN - | LPT_LPC_EN | COMA_LPC_EN); - - /* range 0x1600 - 0x167f */ - pci_write_config32(PCI_DEV(0, 0x1f, 0), GEN1_DEC, 0x007c1601); - - /* range 0x15e0 - 0x15ef */ - pci_write_config32(PCI_DEV(0, 0x1f, 0), GEN2_DEC, 0x000c15e1); - - /* range 0x1680 - 0x169f */ - pci_write_config32(PCI_DEV(0, 0x1f, 0), GEN3_DEC, 0x001c1681); } static void early_superio_config(void) @@ -140,7 +126,8 @@ void mainboard_romstage_entry(void) enable_lapic(); - ich7_enable_lpc(); + i82801gx_lpc_setup(); + mb_lpc_decode(); /* We want early GPIO setup, to be able to detect legacy I/O module */ pci_write_config32(PCI_DEV(0, 0x1f, 0), GPIOBASE, DEFAULT_GPIOBASE | 1); diff --git a/src/mainboard/lenovo/thinkcentre_a58/devicetree.cb b/src/mainboard/lenovo/thinkcentre_a58/devicetree.cb index ace2bfbff2..5559f7dcfd 100644 --- a/src/mainboard/lenovo/thinkcentre_a58/devicetree.cb +++ b/src/mainboard/lenovo/thinkcentre_a58/devicetree.cb @@ -46,6 +46,8 @@ chip northbridge/intel/x4x # Northbridge register "ide_enable_primary" = "0x1" register "gpe0_en" = "0x440" + register "gen1_dec" = "0x00fc0a01" + device pci 1b.0 on end # Audio device pci 1c.0 on end # PCIe 1 device pci 1c.1 on # PCIe 2: NIC diff --git a/src/mainboard/lenovo/thinkcentre_a58/romstage.c b/src/mainboard/lenovo/thinkcentre_a58/romstage.c index 10889a9286..d632d9ddbf 100644 --- a/src/mainboard/lenovo/thinkcentre_a58/romstage.c +++ b/src/mainboard/lenovo/thinkcentre_a58/romstage.c @@ -42,18 +42,6 @@ static void mb_lpc_setup(void) ich7_setup_cir(); } -static void ich7_enable_lpc(void) -{ - pci_write_config8(LPC_DEV, SERIRQ_CNTL, 0xd0); - /* Fixed IO decode ranges */ - pci_write_config16(LPC_DEV, LPC_IO_DEC, 0x0010); - /* LPC enable devices */ - pci_write_config16(LPC_DEV, LPC_EN, CNF1_LPC_EN | KBC_LPC_EN - | FDD_LPC_EN | LPT_LPC_EN | COMA_LPC_EN); - /* IO decode range: HWM on 0xa00 */ - pci_write_config32(LPC_DEV, GEN1_DEC, 0x00fc0a01); -} - void mainboard_romstage_entry(void) { // ch0 ch1 @@ -62,7 +50,7 @@ void mainboard_romstage_entry(void) u8 s3_resume; /* Set southbridge and Super I/O GPIOs. */ - ich7_enable_lpc(); + i82801gx_lpc_setup(); mb_lpc_setup(); smscsuperio_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); diff --git a/src/mainboard/lenovo/x60/devicetree.cb b/src/mainboard/lenovo/x60/devicetree.cb index b3d87ccb4b..1a914fd009 100644 --- a/src/mainboard/lenovo/x60/devicetree.cb +++ b/src/mainboard/lenovo/x60/devicetree.cb @@ -76,6 +76,10 @@ chip northbridge/intel/i945 register "docking_supported" = "1" register "p_cnt_throttling_supported" = "1" + register "gen1_dec" = "0x007c1601" + register "gen2_dec" = "0x000c15e1" + register "gen3_dec" = "0x001c1681" + device pci 1b.0 on # Audio Controller subsystemid 0x17aa 0x2010 end diff --git a/src/mainboard/lenovo/x60/romstage.c b/src/mainboard/lenovo/x60/romstage.c index 34d8d7a435..1008bb0e22 100644 --- a/src/mainboard/lenovo/x60/romstage.c +++ b/src/mainboard/lenovo/x60/romstage.c @@ -33,24 +33,11 @@ #include #include "dock.h" -static void ich7_enable_lpc(void) +/* Override the default lpc decode ranges */ +static void mb_lpc_decode(void) { - // Enable Serial IRQ - pci_write_config8(PCI_DEV(0, 0x1f, 0), SERIRQ_CNTL, 0xd0); // decode range pci_write_config16(PCI_DEV(0, 0x1f, 0), LPC_IO_DEC, 0x0210); - // decode range - pci_write_config16(PCI_DEV(0, 0x1f, 0), LPC_EN, CNF1_LPC_EN | MC_LPC_EN - | KBC_LPC_EN | GAMEH_LPC_EN | GAMEL_LPC_EN | FDD_LPC_EN - | LPT_LPC_EN | COMA_LPC_EN); - /* range 0x1600 - 0x167f */ - pci_write_config32(PCI_DEV(0, 0x1f, 0), GEN1_DEC, 0x007c1601); - - /* range 0x15e0 - 0x15ef */ - pci_write_config32(PCI_DEV(0, 0x1f, 0), GEN2_DEC, 0x000c15e1); - - /* range 0x1680 - 0x169f */ - pci_write_config32(PCI_DEV(0, 0x1f, 0), GEN3_DEC, 0x001c1681); } static void early_superio_config(void) @@ -144,7 +131,8 @@ void mainboard_romstage_entry(void) pci_write_config8(PCI_DEV(0, 0x1f, 0), 0x4c, 0x10); /* 0x4c == GC */ setup_pch_gpios(&mainboard_gpio_map); - ich7_enable_lpc(); + i82801gx_lpc_setup(); + mb_lpc_decode(); dlpc_init(); /* dock_init initializes the DLPC switch on diff --git a/src/mainboard/roda/rk886ex/devicetree.cb b/src/mainboard/roda/rk886ex/devicetree.cb index 0ceef6a2fd..5bce304335 100644 --- a/src/mainboard/roda/rk886ex/devicetree.cb +++ b/src/mainboard/roda/rk886ex/devicetree.cb @@ -62,6 +62,10 @@ chip northbridge/intel/i945 register "ide_enable_primary" = "0x1" register "ide_enable_secondary" = "0x0" + register "gen1_dec" = "0x001c02e1" # COM3, COM4 + register "gen2_dec" = "0x00fc0601" # ?? + register "gen3_dec" = "0x00040069" # EC decode ?? + device pci 1b.0 off end # High Definition Audio device pci 1c.0 on end # PCIe port 1 device pci 1c.1 off end # PCIe port 2 diff --git a/src/mainboard/roda/rk886ex/romstage.c b/src/mainboard/roda/rk886ex/romstage.c index e7724e4485..019ec1b733 100644 --- a/src/mainboard/roda/rk886ex/romstage.c +++ b/src/mainboard/roda/rk886ex/romstage.c @@ -30,26 +30,16 @@ #include #include "option_table.h" -static void ich7_enable_lpc(void) +/* Override the default lpc decode ranges */ +static void mb_lpc_decode(void) { int lpt_en = 0; if (read_option(lpt, 0) != 0) lpt_en = LPT_LPC_EN; /* enable LPT */ - /* Enable Serial IRQ */ - pci_write_config8(PCI_DEV(0, 0x1f, 0), SERIRQ_CNTL, 0xd0); - /* decode range */ pci_write_config16(PCI_DEV(0, 0x1f, 0), LPC_IO_DEC, 0x0007); - /* decode range */ - pci_write_config16(PCI_DEV(0, 0x1f, 0), LPC_EN, CNF2_LPC_EN | CNF1_LPC_EN - | MC_LPC_EN | KBC_LPC_EN | GAMEH_LPC_EN | GAMEL_LPC_EN - | FDD_LPC_EN | lpt_en | COMB_LPC_EN | COMA_LPC_EN); - /* COM3 and COM4 decode? */ - pci_write_config32(PCI_DEV(0, 0x1f, 0), GEN1_DEC, 0x1c02e1); - /* ??decode?? */ - pci_write_config32(PCI_DEV(0, 0x1f, 0), GEN2_DEC, 0x00fc0601); - /* EC decode? */ - pci_write_config32(PCI_DEV(0, 0x1f, 0), GEN3_DEC, 0x00040069); + + pci_update_config16(PCI_DEV(0, 0x1f, 0), LPC_EN, ~LPT_LPC_EN, lpt_en); } /* This box has two superios, so enabling serial becomes slightly excessive. @@ -177,7 +167,8 @@ void mainboard_romstage_entry(void) enable_lapic(); - ich7_enable_lpc(); + i82801gx_lpc_setup(); + mb_lpc_decode(); early_superio_config(); /* Set up the console */ diff --git a/src/southbridge/intel/i82801gx/Makefile.inc b/src/southbridge/intel/i82801gx/Makefile.inc index 2e9d31a3e8..31264295ad 100644 --- a/src/southbridge/intel/i82801gx/Makefile.inc +++ b/src/southbridge/intel/i82801gx/Makefile.inc @@ -15,6 +15,7 @@ ifeq ($(CONFIG_SOUTHBRIDGE_INTEL_I82801GX),y) +bootblock-y += early_init.c bootblock-y += bootblock_gcc.c ramstage-y += i82801gx.c @@ -34,6 +35,7 @@ ramstage-srcs += src/mainboard/$(MAINBOARDDIR)/hda_verb.c smm-y += smihandler.c +romstage-y += early_init.c romstage-y += early_smbus.c romstage-y += early_cir.c diff --git a/src/southbridge/intel/i82801gx/bootblock_gcc.c b/src/southbridge/intel/i82801gx/bootblock_gcc.c index 996788888a..063a461e43 100644 --- a/src/southbridge/intel/i82801gx/bootblock_gcc.c +++ b/src/southbridge/intel/i82801gx/bootblock_gcc.c @@ -41,4 +41,6 @@ void bootblock_early_southbridge_init(void) /* Disable watchdog timer */ RCBA32(GCS) = RCBA32(GCS) | 0x20; + + i82801gx_lpc_setup(); } diff --git a/src/southbridge/intel/i82801gx/chip.h b/src/southbridge/intel/i82801gx/chip.h index 4e78c30db2..75b957573e 100644 --- a/src/southbridge/intel/i82801gx/chip.h +++ b/src/southbridge/intel/i82801gx/chip.h @@ -80,6 +80,12 @@ struct southbridge_intel_i82801gx_config { int docking_supported:1; int p_cnt_throttling_supported:1; int c3_latency; + + /* Additional LPC IO decode ranges */ + uint32_t gen1_dec; + uint32_t gen2_dec; + uint32_t gen3_dec; + uint32_t gen4_dec; }; #endif /* SOUTHBRIDGE_INTEL_I82801GX_CHIP_H */ diff --git a/src/southbridge/intel/i82801gx/early_init.c b/src/southbridge/intel/i82801gx/early_init.c new file mode 100644 index 0000000000..533aaefe14 --- /dev/null +++ b/src/southbridge/intel/i82801gx/early_init.c @@ -0,0 +1,52 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include "i82801gx.h" +#include "chip.h" + +void i82801gx_lpc_setup(void) +{ + const pci_devfn_t d31f0 = PCI_DEV(0, 0x1f, 0); + const struct device *dev = pcidev_on_root(0x1f, 0); + const struct southbridge_intel_i82801gx_config *config; + + /* Configure serial IRQs.*/ + pci_write_config8(d31f0, SERIRQ_CNTL, 0xd0); + /* + * Enable some common LPC IO ranges: + * - 0x2e/0x2f, 0x4e/0x4f often SuperIO + * - 0x60/0x64, 0x62/0x66 often KBC/EC + * - 0x3f0-0x3f5/0x3f7 FDD + * - 0x378-0x37f and 0x778-0x77f LPT + * - 0x2f8-0x2ff COMB + * - 0x3f8-0x3ff COMA + * - 0x208-0x20f GAMEH + * - 0x200-0x207 GAMEL + */ + pci_write_config16(d31f0, LPC_IO_DEC, 0x0010); + pci_write_config16(d31f0, LPC_EN, CNF2_LPC_EN | CNF1_LPC_EN + | MC_LPC_EN | KBC_LPC_EN | GAMEH_LPC_EN + | GAMEL_LPC_EN | FDD_LPC_EN | LPT_LPC_EN + | COMB_LPC_EN | COMA_LPC_EN); + + /* Set up generic decode ranges */ + if (!dev || !dev->chip_info) + return; + config = dev->chip_info; + + pci_write_config32(d31f0, GEN1_DEC, config->gen1_dec); + pci_write_config32(d31f0, GEN2_DEC, config->gen2_dec); + pci_write_config32(d31f0, GEN3_DEC, config->gen3_dec); + pci_write_config32(d31f0, GEN4_DEC, config->gen4_dec); +} diff --git a/src/southbridge/intel/i82801gx/i82801gx.h b/src/southbridge/intel/i82801gx/i82801gx.h index 8c85331af9..259fb49f54 100644 --- a/src/southbridge/intel/i82801gx/i82801gx.h +++ b/src/southbridge/intel/i82801gx/i82801gx.h @@ -40,6 +40,7 @@ void i82801gx_enable(struct device *dev); #endif void enable_smbus(void); +void i82801gx_lpc_setup(void); #if ENV_ROMSTAGE int smbus_read_byte(unsigned int device, unsigned int address); From c484da1a98610d783131a3a3998c0a999b97f9f5 Mon Sep 17 00:00:00 2001 From: Arthur Heymans Date: Sat, 9 Nov 2019 14:29:04 +0100 Subject: [PATCH 0132/1242] sb/intel/i82801jx: Add common code for LPC decode Change-Id: Id706da33f06ceeec39ea50301130770226f0474e Signed-off-by: Arthur Heymans Reviewed-on: https://review.coreboot.org/c/coreboot/+/36701 Tested-by: build bot (Jenkins) Reviewed-by: HAOUAS Elyes Reviewed-by: Nico Huber Reviewed-by: Angel Pons --- src/mainboard/asus/p5qc/romstage.c | 15 +----- .../asus/p5qc/variants/p5q_pro/devicetree.cb | 3 ++ .../asus/p5qc/variants/p5qc/devicetree.cb | 3 ++ .../asus/p5qc/variants/p5ql_pro/devicetree.cb | 3 ++ src/mainboard/asus/p5ql-em/devicetree.cb | 2 + src/mainboard/asus/p5ql-em/romstage.c | 12 +---- src/mainboard/intel/dg43gt/devicetree.cb | 3 ++ src/mainboard/intel/dg43gt/romstage.c | 15 +----- src/southbridge/intel/i82801jx/Makefile.inc | 1 + src/southbridge/intel/i82801jx/chip.h | 6 +++ src/southbridge/intel/i82801jx/early_init.c | 54 +++++++++++++++++++ src/southbridge/intel/i82801jx/i82801jx.h | 1 + 12 files changed, 79 insertions(+), 39 deletions(-) create mode 100644 src/southbridge/intel/i82801jx/early_init.c diff --git a/src/mainboard/asus/p5qc/romstage.c b/src/mainboard/asus/p5qc/romstage.c index fb30beeffb..3462a3d99d 100644 --- a/src/mainboard/asus/p5qc/romstage.c +++ b/src/mainboard/asus/p5qc/romstage.c @@ -51,19 +51,6 @@ static void mb_gpio_init(void) RCBA32(0x3f00) = 0x00000038; } -static void ich10_enable_lpc(void) -{ - /* Configure serial IRQs.*/ - pci_write_config16(LPC_DEV, D31F0_LPC_IODEC, 0x0010); - pci_write_config16(LPC_DEV, D31F0_LPC_EN, CNF2_LPC_EN | CNF1_LPC_EN - | KBC_LPC_EN | FDD_LPC_EN | LPT_LPC_EN | COMB_LPC_EN - | COMA_LPC_EN); - /* HW EC */ - pci_write_config32(LPC_DEV, D31F0_GEN1_DEC, 0x00000295); - /* ????? */ - pci_write_config32(LPC_DEV, D31F0_GEN2_DEC, 0x001c4701); -} - void mainboard_romstage_entry(void) { const u8 spd_addrmap[4] = { 0x50, 0x51, 0x52, 0x53 }; @@ -71,7 +58,7 @@ void mainboard_romstage_entry(void) u8 s3_resume; /* Set southbridge and Super I/O GPIOs. */ - ich10_enable_lpc(); + i82801jx_lpc_setup(); mb_gpio_init(); winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); diff --git a/src/mainboard/asus/p5qc/variants/p5q_pro/devicetree.cb b/src/mainboard/asus/p5qc/variants/p5q_pro/devicetree.cb index 6e0a40a651..fb818ffa7f 100644 --- a/src/mainboard/asus/p5qc/variants/p5q_pro/devicetree.cb +++ b/src/mainboard/asus/p5qc/variants/p5q_pro/devicetree.cb @@ -45,6 +45,9 @@ chip northbridge/intel/x4x # Northbridge # Enable PCIe ports 0,2,3 as slots. register "pcie_slot_implemented" = "0x31" + register "gen1_dec" = "0x00000295" + register "gen2_dec" = "0x001c4701" + device pci 19.0 off end # GBE device pci 1a.0 on end # USB device pci 1a.1 on end # USB diff --git a/src/mainboard/asus/p5qc/variants/p5qc/devicetree.cb b/src/mainboard/asus/p5qc/variants/p5qc/devicetree.cb index 902dcfdcb5..d89f5cc645 100644 --- a/src/mainboard/asus/p5qc/variants/p5qc/devicetree.cb +++ b/src/mainboard/asus/p5qc/variants/p5qc/devicetree.cb @@ -45,6 +45,9 @@ chip northbridge/intel/x4x # Northbridge # Enable PCIe ports 0,2,3 as slots. register "pcie_slot_implemented" = "0x31" + register "gen1_dec" = "0x00000295" + register "gen2_dec" = "0x001c4701" + device pci 19.0 off end # GBE device pci 1a.0 on end # USB device pci 1a.1 on end # USB diff --git a/src/mainboard/asus/p5qc/variants/p5ql_pro/devicetree.cb b/src/mainboard/asus/p5qc/variants/p5ql_pro/devicetree.cb index c596a42244..0428b50e9a 100644 --- a/src/mainboard/asus/p5qc/variants/p5ql_pro/devicetree.cb +++ b/src/mainboard/asus/p5qc/variants/p5ql_pro/devicetree.cb @@ -45,6 +45,9 @@ chip northbridge/intel/x4x # Northbridge # Enable PCIe ports 0,2,3 as slots. register "pcie_slot_implemented" = "0x31" + register "gen1_dec" = "0x00000295" + register "gen2_dec" = "0x001c4701" + device pci 19.0 off end # GBE device pci 1a.0 on end # USB device pci 1a.1 on end # USB diff --git a/src/mainboard/asus/p5ql-em/devicetree.cb b/src/mainboard/asus/p5ql-em/devicetree.cb index 165340321b..fd0b1034af 100644 --- a/src/mainboard/asus/p5ql-em/devicetree.cb +++ b/src/mainboard/asus/p5ql-em/devicetree.cb @@ -49,6 +49,8 @@ chip northbridge/intel/x4x # Northbridge # Enable PCIe ports 0,1,3,4,5 as slots. register "pcie_slot_implemented" = "0x3b" + register "gen1_dec" = "0x00000295" + device pci 19.0 off end # GBE device pci 1a.0 on # USB subsystemid 0x1043 0x82d4 diff --git a/src/mainboard/asus/p5ql-em/romstage.c b/src/mainboard/asus/p5ql-em/romstage.c index 614f4874e1..142ee73e49 100644 --- a/src/mainboard/asus/p5ql-em/romstage.c +++ b/src/mainboard/asus/p5ql-em/romstage.c @@ -117,16 +117,6 @@ static void mb_gpio_init(void) RCBA8(0x31ff); } -static void ich10_enable_lpc(void) -{ - /* Configure serial IRQs.*/ - pci_write_config16(LPC_DEV, D31F0_LPC_IODEC, 0x0010); - pci_write_config16(LPC_DEV, D31F0_LPC_EN, CNF1_LPC_EN | KBC_LPC_EN - | FDD_LPC_EN | LPT_LPC_EN | COMA_LPC_EN); - /* Hardware monitor IO range */ - pci_write_config32(LPC_DEV, D31F0_GEN1_DEC, 0x00000295); -} - void mainboard_romstage_entry(void) { /* This board has first dimm slot of each channel hooked up to @@ -138,7 +128,7 @@ void mainboard_romstage_entry(void) u8 s3_resume; /* Set southbridge and Super I/O GPIOs. */ - ich10_enable_lpc(); + i82801jx_lpc_setup(); mb_gpio_init(); winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); diff --git a/src/mainboard/intel/dg43gt/devicetree.cb b/src/mainboard/intel/dg43gt/devicetree.cb index be0b911a5a..38ae29b031 100644 --- a/src/mainboard/intel/dg43gt/devicetree.cb +++ b/src/mainboard/intel/dg43gt/devicetree.cb @@ -42,6 +42,9 @@ chip northbridge/intel/x4x # Northbridge # Enable PCIe ports 0,2,3 as slots. register "pcie_slot_implemented" = "0xb" + register "gen1_dec" = "0x00fc0601" + register "gen2_dec" = "0x00fc0291" + device pci 19.0 on end # GBE device pci 1a.0 on end # USB device pci 1a.1 on end # USB diff --git a/src/mainboard/intel/dg43gt/romstage.c b/src/mainboard/intel/dg43gt/romstage.c index 018df1bedf..6e645b5630 100644 --- a/src/mainboard/intel/dg43gt/romstage.c +++ b/src/mainboard/intel/dg43gt/romstage.c @@ -53,19 +53,6 @@ static void mb_gpio_init(void) RCBA32(0x3f00) = 0x0000000b; } -static void ich10_enable_lpc(void) -{ - /* Configure serial IRQs.*/ - pci_write_config16(LPC_DEV, D31F0_LPC_IODEC, 0x0010); - pci_write_config16(LPC_DEV, D31F0_LPC_EN, CNF2_LPC_EN | CNF1_LPC_EN - | MC_LPC_EN | KBC_LPC_EN | GAMEH_LPC_EN - | GAMEL_LPC_EN | FDD_LPC_EN | LPT_LPC_EN - | COMB_LPC_EN | COMA_LPC_EN); - pci_write_config32(LPC_DEV, D31F0_GEN1_DEC, 0xfc0601); - pci_write_config32(LPC_DEV, D31F0_GEN2_DEC, 0xfc0291); - pci_write_config32(LPC_DEV, D31F0_GEN3_DEC, 0); -} - void mainboard_romstage_entry(void) { const u8 spd_addrmap[4] = { 0x50, 0x51, 0x52, 0x53 }; @@ -73,7 +60,7 @@ void mainboard_romstage_entry(void) u8 s3_resume; /* Set southbridge and Super I/O GPIOs. */ - ich10_enable_lpc(); + i82801jx_lpc_setup(); mb_gpio_init(); winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); diff --git a/src/southbridge/intel/i82801jx/Makefile.inc b/src/southbridge/intel/i82801jx/Makefile.inc index 02da8146e9..30ed351970 100644 --- a/src/southbridge/intel/i82801jx/Makefile.inc +++ b/src/southbridge/intel/i82801jx/Makefile.inc @@ -31,6 +31,7 @@ ramstage-srcs += src/mainboard/$(MAINBOARDDIR)/hda_verb.c smm-y += smihandler.c +romstage-y += early_init.c romstage-y += early_smbus.c endif diff --git a/src/southbridge/intel/i82801jx/chip.h b/src/southbridge/intel/i82801jx/chip.h index 1712b8162c..e4c68fb95a 100644 --- a/src/southbridge/intel/i82801jx/chip.h +++ b/src/southbridge/intel/i82801jx/chip.h @@ -78,6 +78,12 @@ struct southbridge_intel_i82801jx_config { } pcie_power_limits[6]; uint8_t pcie_hotplug_map[8]; + + /* Additional LPC IO decode ranges */ + uint32_t gen1_dec; + uint32_t gen2_dec; + uint32_t gen3_dec; + uint32_t gen4_dec; }; #endif /* SOUTHBRIDGE_INTEL_I82801JX_CHIP_H */ diff --git a/src/southbridge/intel/i82801jx/early_init.c b/src/southbridge/intel/i82801jx/early_init.c new file mode 100644 index 0000000000..9d40cf2d27 --- /dev/null +++ b/src/southbridge/intel/i82801jx/early_init.c @@ -0,0 +1,54 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include "i82801jx.h" +#include "chip.h" + +void i82801jx_lpc_setup(void) +{ + const pci_devfn_t d31f0 = PCI_DEV(0, 0x1f, 0); + const struct device *dev = pcidev_on_root(0x1f, 0); + const struct southbridge_intel_i82801jx_config *config; + + /* Configure serial IRQs.*/ + pci_write_config8(d31f0, D31F0_SERIRQ_CNTL, 0xd0); + /* + * Enable some common LPC IO ranges: + * - 0x2e/0x2f, 0x4e/0x4f often SuperIO + * - 0x60/0x64, 0x62/0x66 often KBC/EC + * - 0x3f0-0x3f5/0x3f7 FDD + * - 0x378-0x37f and 0x778-0x77f LPT + * - 0x2f8-0x2ff COMB + * - 0x3f8-0x3ff COMA + * - 0x208-0x20f GAMEH + * - 0x200-0x207 GAMEL + */ + pci_write_config16(d31f0, D31F0_LPC_IODEC, 0x0010); + pci_write_config16(d31f0, D31F0_LPC_EN, CNF2_LPC_EN | CNF1_LPC_EN + | MC_LPC_EN | KBC_LPC_EN | GAMEH_LPC_EN + | GAMEL_LPC_EN | FDD_LPC_EN | LPT_LPC_EN + | COMB_LPC_EN | COMA_LPC_EN); + + + /* Set up generic decode ranges */ + if (!dev || !dev->chip_info) + return; + config = dev->chip_info; + + pci_write_config32(d31f0, D31F0_GEN1_DEC, config->gen1_dec); + pci_write_config32(d31f0, D31F0_GEN2_DEC, config->gen2_dec); + pci_write_config32(d31f0, D31F0_GEN3_DEC, config->gen3_dec); + pci_write_config32(d31f0, D31F0_GEN4_DEC, config->gen4_dec); +} diff --git a/src/southbridge/intel/i82801jx/i82801jx.h b/src/southbridge/intel/i82801jx/i82801jx.h index 7b882181ff..e302c8986a 100644 --- a/src/southbridge/intel/i82801jx/i82801jx.h +++ b/src/southbridge/intel/i82801jx/i82801jx.h @@ -234,6 +234,7 @@ int smbus_block_read(unsigned int device, unsigned int cmd, u8 bytes, u8 *buf); int smbus_block_write(unsigned int device, unsigned int cmd, u8 bytes, const u8 *buf); #endif +void i82801jx_lpc_setup(void); #endif From 11a34ec4c230ab9a6a825eae57eb848aa052a6ed Mon Sep 17 00:00:00 2001 From: Uwe Poeche Date: Mon, 28 Oct 2019 11:28:50 +0100 Subject: [PATCH 0133/1242] drivers/i2c/ptn3460: Provide chip driver for PTN3460 This patch provides a chip driver for the DP-2-LVDS bridge PTN3460. The bridge is configured via I2C. As the mainboard has all the information regarding the attached LCD type, there are three hooks into mainboard code to get the information like EDID data and PTN config. TEST=Display is working on Siemens mainboards (e.g. mc_tcu3, mc_apl1, ...). Change-Id: Ie4c8176cd16836fa5b8fd2f72faf7a55723b82f6 Signed-off-by: Uwe Poeche Reviewed-on: https://review.coreboot.org/c/coreboot/+/36642 Tested-by: build bot (Jenkins) Reviewed-by: Werner Zeh --- src/drivers/i2c/ptn3460/Kconfig | 5 + src/drivers/i2c/ptn3460/Makefile.inc | 1 + src/drivers/i2c/ptn3460/chip.h | 3 + src/drivers/i2c/ptn3460/ptn3460.c | 157 +++++++++++++++++++++++++++ src/drivers/i2c/ptn3460/ptn3460.h | 73 +++++++++++++ 5 files changed, 239 insertions(+) create mode 100644 src/drivers/i2c/ptn3460/Kconfig create mode 100644 src/drivers/i2c/ptn3460/Makefile.inc create mode 100644 src/drivers/i2c/ptn3460/chip.h create mode 100644 src/drivers/i2c/ptn3460/ptn3460.c create mode 100644 src/drivers/i2c/ptn3460/ptn3460.h diff --git a/src/drivers/i2c/ptn3460/Kconfig b/src/drivers/i2c/ptn3460/Kconfig new file mode 100644 index 0000000000..6dcdbc0915 --- /dev/null +++ b/src/drivers/i2c/ptn3460/Kconfig @@ -0,0 +1,5 @@ +config DRIVERS_I2C_PTN3460 + bool + default n + help + Enable support for external display bridge (eDP to LVDS) PTN3460. diff --git a/src/drivers/i2c/ptn3460/Makefile.inc b/src/drivers/i2c/ptn3460/Makefile.inc new file mode 100644 index 0000000000..abe9a0560b --- /dev/null +++ b/src/drivers/i2c/ptn3460/Makefile.inc @@ -0,0 +1 @@ +ramstage-$(CONFIG_DRIVERS_I2C_PTN3460) += ptn3460.c diff --git a/src/drivers/i2c/ptn3460/chip.h b/src/drivers/i2c/ptn3460/chip.h new file mode 100644 index 0000000000..8bd6d9e7d1 --- /dev/null +++ b/src/drivers/i2c/ptn3460/chip.h @@ -0,0 +1,3 @@ +struct drivers_i2c_ptn3460_config { + +}; diff --git a/src/drivers/i2c/ptn3460/ptn3460.c b/src/drivers/i2c/ptn3460/ptn3460.c new file mode 100644 index 0000000000..ef25745ed1 --- /dev/null +++ b/src/drivers/i2c/ptn3460/ptn3460.c @@ -0,0 +1,157 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 Siemens AG + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + + +#include +#include +#include + +#include "ptn3460.h" + +/** + * \brief This function selects one of 7 EDID-tables inside PTN3460 + * which should be emulated on display port and turn emulation ON + * @param *dev Pointer to the relevant I2C controller + * @param edid_num Number of EDID to emulate (0..6) + * @return PTN_SUCCESS or error code + */ +static int ptn_select_edid(struct device *dev, uint8_t edid_num) +{ + int status = 0; + u8 val; + + if (edid_num > PTN_MAX_EDID_NUM) + return PTN_INVALID_EDID; + val = (edid_num << 1) | PTN_ENABLE_EMULATION; + status = i2c_dev_writeb_at(dev, PTN_CONFIG_OFF + 4, val); + return status ? (PTN_BUS_ERROR | status) : PTN_SUCCESS; +} + +/** + * \brief This function writes one EDID data structure to PTN3460 + * @param *dev Pointer to the relevant I2C controller + * @param edid_num Number of EDID that must be written (0..6) + * @param *data Pointer to a buffer where data to write is stored in + * @return PTN_SUCCESS on success or error code + */ +static int ptn3460_write_edid(struct device *dev, u8 edid_num, u8 *data) +{ + int status; + int i; + + if (edid_num > PTN_MAX_EDID_NUM) + return PTN_INVALID_EDID; + + /* First enable access to the desired EDID table */ + status = i2c_dev_writeb_at(dev, PTN_CONFIG_OFF + 5, edid_num); + if (status) + return (PTN_BUS_ERROR | status); + + /* Now we can simply write EDID data to ptn3460 */ + for (i = 0; i < PTN_EDID_LEN; i++) { + status = i2c_dev_writeb_at(dev, PTN_EDID_OFF + i, data[i]); + if (status) + return (PTN_BUS_ERROR | status); + } + return PTN_SUCCESS; +} + +/** + * \brief This function sets up the DP2LVDS-converter to be used with the + * appropriate EDID data + * @param *dev Pointer to the I2C controller where PTN3460 is attached + */ +static void ptn3460_init(struct device *dev) +{ + struct ptn_3460_config cfg; + uint8_t edid_data[PTN_EDID_LEN], edid_tab, *ptr = (uint8_t *) &cfg; + int i, val; + + /* Mainboard provides EDID data. */ + if (mb_get_edid(edid_data) != CB_SUCCESS) { + printk(BIOS_ERR, "PTN3460 error: Unable to get EDID data from mainboard.\n"); + return; + } + + /* Mainboard decides which EDID table has to be used. */ + edid_tab = mb_select_edid_table(); + if (edid_tab > PTN_MAX_EDID_NUM) { + printk(BIOS_ERR, "PTN3460 error: invalid EDID table (%d) selected.\n", + edid_tab); + return; + } + /* Write EDID data into PTN. */ + val = ptn3460_write_edid(dev, edid_tab, edid_data); + if (val != PTN_SUCCESS) { + printk(BIOS_ERR, "PTN3460 error: writing EDID data into device failed.\n"); + return; + } + /* Activate the selected EDID block. */ + ptn_select_edid(dev, edid_tab); + /* Read out PTN configuration data. */ + for (i = 0; i < sizeof(struct ptn_3460_config); i++) { + val = i2c_dev_readb_at(dev, PTN_CONFIG_OFF + i); + if (val < 0) { + printk(BIOS_ERR, + "PTN3460 error: Unable to read config data from device.\n"); + return; + } + *ptr++ = (uint8_t)val; /* fill config structure via ptr */ + } + /* Mainboard can modify the configuration data. + Write back configuration data to PTN3460 if modified by mainboard */ + if (mb_adjust_cfg(&cfg) == PTN_CFG_MODIFIED) { + ptr = (uint8_t *) &cfg; + for (i = 0; i < sizeof(struct ptn_3460_config); i++) { + val = i2c_dev_writeb_at(dev, PTN_CONFIG_OFF + i, *ptr++); + if (val < 0) { + printk(BIOS_ERR, + "PTN3460 error: Unable to write config data.\n"); + return; + } + } + } +} + +__weak enum cb_err mb_get_edid(uint8_t edid_data[0x80]) +{ + return CB_ERR; +} +__weak uint8_t mb_select_edid_table(void) +{ + return 0; +} +__weak int mb_adjust_cfg(struct ptn_3460_config *cfg_ptr) +{ + return 0; +} + +static struct device_operations ptn3460_ops = { + .read_resources = DEVICE_NOOP, + .set_resources = DEVICE_NOOP, + .enable_resources = DEVICE_NOOP, + .init = ptn3460_init, + .final = DEVICE_NOOP +}; + +static void ptn3460_enable(struct device *dev) +{ + dev->ops = &ptn3460_ops; +} + +struct chip_operations drivers_i2c_ptn3460_ops = { + CHIP_NAME("PTN3460") + .enable_dev = ptn3460_enable +}; diff --git a/src/drivers/i2c/ptn3460/ptn3460.h b/src/drivers/i2c/ptn3460/ptn3460.h new file mode 100644 index 0000000000..4b9834eb9d --- /dev/null +++ b/src/drivers/i2c/ptn3460/ptn3460.h @@ -0,0 +1,73 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 Siemens AG + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _I2C_PTN3460_H_ +#define _I2C_PTN3460_H_ + +#include + +#define PTN_EDID_OFF 0x00 +#define PTN_EDID_LEN 0x80 +#define PTN_CONFIG_OFF 0x80 +#define PTN_CONFIG_LEN 0x19 +#define PTN_FLASH_CFG_OFF 0xE8 +#define PTN_FLASH_CFG_LEN 0x04 +#define PTN_MAX_EDID_NUM 6 +#define PTN_ENABLE_EMULATION (1 << 0) + +/* Define some error codes that can be used */ +#define PTN_SUCCESS 0x00000000 +#define PTN_CFG_MODIFIED 0x00000001 +#define PTN_BUS_ERROR 0x10000000 +#define PTN_INVALID_EDID 0x20000000 +#define PTN_INVALID_EDID_BLOCK 0x30000000 +#define PTN_ERROR 0x40000000 + +struct ptn_3460_config { + u8 dp_interface_ctrl; /* DisplayPort interface control */ + u8 lvds_interface_ctrl1; /* LVDS interface control register 1 */ + u8 lvds_interface_ctrl2; /* LVDS interface control register 2 */ + u8 lvds_interface_ctrl3; /* LVDS interface control register 3 */ + u8 edid_rom_emulation; /* select which EDID-block is emulated */ + u8 edid_rom_access_ctrl; /* select which EDID block to map to 0..0x7F */ + u8 pwm_min[3]; /* smallest PWM frequency for back light */ + u8 pwm_max[3]; /* biggest PWM frequency for back light */ + u8 fast_link_ctrl; /* Fast link training control register */ + u8 pin_cfg_ctrl1; /* Pin configuration control register 1 */ + u8 pin_cfg_ctrl2; /* Pin configuration control register 2 */ + u8 pwm_default; /* Default PWM bit count in DPCD register */ + u16 pwm_value; /* Current PWM bit count in DPCD register */ + u8 pwm_default_freq; /* Default PWM frequency in DPCD register */ + u8 t3_timing; /* Panel T3 timing value */ + u8 t12_timing; /* Panel T12 timing value */ + u8 backlight_ctrl; /* Back light control register */ + u8 t2_delay; /* Panel T2 delay */ + u8 t4_timing; /* Panel T4 timing value */ + u8 t5_delay; /* Panel T5 delay */ +} __packed; + +struct ptn_3460_flash { + u8 cmd; /* Flash command (erase or erase and flash) */ + u16 magic; /* Magic number needed by the flash algorithm */ + u8 trigger; /* Trigger for starting flash operation */ +} __packed; + +/* We need functions which we can call to get mainboard specific data */ +/* These functions can be implemented somewhere else but must exist. */ +extern enum cb_err mb_get_edid(uint8_t edid_data[0x80]); +extern uint8_t mb_select_edid_table(void); +extern int mb_adjust_cfg(struct ptn_3460_config *cfg_ptr); + +#endif /* _I2C_PTN3460_H_ */ From 996588521a2240397b4a89e5ad5f5708f930dbc8 Mon Sep 17 00:00:00 2001 From: Uwe Poeche Date: Tue, 5 Nov 2019 15:44:42 +0100 Subject: [PATCH 0134/1242] src/mainboard/siemens: Use PTN3460 chip driver This patch replaces and cleans up the redundant PTN3460 driver files in /mainboard/siemens directories by using the now available driver in src/drivers/i2c/ptn3460 and providing mainboard specific functions to the driver. TEST=Display is working on Siemens mainboards (e.g. mc_tcu3, mc_apl1, ...). Change-Id: I976a502e7176a356bab772758250db3cdff529b9 Signed-off-by: Uwe Poeche Reviewed-on: https://review.coreboot.org/c/coreboot/+/36643 Reviewed-by: Werner Zeh Tested-by: build bot (Jenkins) --- .../siemens/mc_apl1/variants/mc_apl1/Kconfig | 1 + .../mc_apl1/variants/mc_apl1/Makefile.inc | 2 +- .../mc_apl1/variants/mc_apl1/devicetree.cb | 4 + .../mc_apl1/include/variant/ptn3460.h | 91 -------- .../mc_apl1/variants/mc_apl1/lcd_panel.c | 102 +++++++++ .../mc_apl1/variants/mc_apl1/mainboard.c | 12 - .../mc_apl1/variants/mc_apl1/ptn3460.c | 171 -------------- .../siemens/mc_apl1/variants/mc_apl4/Kconfig | 1 + .../mc_apl1/variants/mc_apl4/Makefile.inc | 3 +- .../mc_apl1/variants/mc_apl4/devicetree.cb | 7 +- .../mc_apl4/include/variant/ptn3460.h | 91 -------- .../mc_apl1/variants/mc_apl4/lcd_panel.c | 103 +++++++++ .../mc_apl1/variants/mc_apl4/mainboard.c | 35 --- .../mc_apl1/variants/mc_apl4/ptn3460.c | 172 -------------- .../siemens/mc_apl1/variants/mc_apl5/Kconfig | 1 + .../mc_apl1/variants/mc_apl5/Makefile.inc | 2 +- .../mc_apl1/variants/mc_apl5/devicetree.cb | 4 + .../mc_apl5/include/variant/ptn3460.h | 91 -------- .../mc_apl1/variants/mc_apl5/lcd_panel.c | 128 +++++++++++ .../mc_apl1/variants/mc_apl5/mainboard.c | 12 - .../mc_apl1/variants/mc_apl5/ptn3460.c | 197 ----------------- src/mainboard/siemens/mc_tcu3/Kconfig | 1 + src/mainboard/siemens/mc_tcu3/Makefile.inc | 1 - src/mainboard/siemens/mc_tcu3/devicetree.cb | 7 +- src/mainboard/siemens/mc_tcu3/lcd_panel.c | 143 +++++++++--- src/mainboard/siemens/mc_tcu3/lcd_panel.h | 6 +- src/mainboard/siemens/mc_tcu3/mainboard.c | 4 - src/mainboard/siemens/mc_tcu3/ptn3460.c | 209 ------------------ src/mainboard/siemens/mc_tcu3/ptn3460.h | 72 ------ 29 files changed, 478 insertions(+), 1195 deletions(-) delete mode 100644 src/mainboard/siemens/mc_apl1/variants/mc_apl1/include/variant/ptn3460.h create mode 100644 src/mainboard/siemens/mc_apl1/variants/mc_apl1/lcd_panel.c delete mode 100644 src/mainboard/siemens/mc_apl1/variants/mc_apl1/ptn3460.c delete mode 100644 src/mainboard/siemens/mc_apl1/variants/mc_apl4/include/variant/ptn3460.h create mode 100644 src/mainboard/siemens/mc_apl1/variants/mc_apl4/lcd_panel.c delete mode 100644 src/mainboard/siemens/mc_apl1/variants/mc_apl4/mainboard.c delete mode 100644 src/mainboard/siemens/mc_apl1/variants/mc_apl4/ptn3460.c delete mode 100644 src/mainboard/siemens/mc_apl1/variants/mc_apl5/include/variant/ptn3460.h create mode 100644 src/mainboard/siemens/mc_apl1/variants/mc_apl5/lcd_panel.c delete mode 100644 src/mainboard/siemens/mc_apl1/variants/mc_apl5/ptn3460.c delete mode 100644 src/mainboard/siemens/mc_tcu3/ptn3460.c delete mode 100644 src/mainboard/siemens/mc_tcu3/ptn3460.h diff --git a/src/mainboard/siemens/mc_apl1/variants/mc_apl1/Kconfig b/src/mainboard/siemens/mc_apl1/variants/mc_apl1/Kconfig index 76d62fcf20..8b10a74ab5 100644 --- a/src/mainboard/siemens/mc_apl1/variants/mc_apl1/Kconfig +++ b/src/mainboard/siemens/mc_apl1/variants/mc_apl1/Kconfig @@ -8,5 +8,6 @@ config BOARD_SPECIFIC_OPTIONS select DRIVER_SIEMENS_NC_FPGA select NC_FPGA_NOTIFY_CB_READY select APL_SKIP_SET_POWER_LIMITS + select DRIVERS_I2C_PTN3460 endif # BOARD_SIEMENS_MC_APL1 diff --git a/src/mainboard/siemens/mc_apl1/variants/mc_apl1/Makefile.inc b/src/mainboard/siemens/mc_apl1/variants/mc_apl1/Makefile.inc index adf9aff0d4..81633a1d93 100644 --- a/src/mainboard/siemens/mc_apl1/variants/mc_apl1/Makefile.inc +++ b/src/mainboard/siemens/mc_apl1/variants/mc_apl1/Makefile.inc @@ -1,2 +1,2 @@ ramstage-y += mainboard.c -ramstage-y += ptn3460.c +ramstage-y += lcd_panel.c diff --git a/src/mainboard/siemens/mc_apl1/variants/mc_apl1/devicetree.cb b/src/mainboard/siemens/mc_apl1/variants/mc_apl1/devicetree.cb index d65ac4e0a4..0e72fcf743 100644 --- a/src/mainboard/siemens/mc_apl1/variants/mc_apl1/devicetree.cb +++ b/src/mainboard/siemens/mc_apl1/variants/mc_apl1/devicetree.cb @@ -93,6 +93,10 @@ chip soc/intel/apollolake register "user_weekday" = "4" device i2c 0x32 on end # RTC RX6110 SA end + # Enable external display bridge (eDP to LVDS) + chip drivers/i2c/ptn3460 + device i2c 0x20 on end # PTN3460 DP2LVDS Bridge + end end device pci 16.1 off end # - I2C 1 device pci 16.2 off end # - I2C 2 diff --git a/src/mainboard/siemens/mc_apl1/variants/mc_apl1/include/variant/ptn3460.h b/src/mainboard/siemens/mc_apl1/variants/mc_apl1/include/variant/ptn3460.h deleted file mode 100644 index 3ff35d9ee8..0000000000 --- a/src/mainboard/siemens/mc_apl1/variants/mc_apl1/include/variant/ptn3460.h +++ /dev/null @@ -1,91 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2014-2017 Siemens AG - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef PTN3460_H_ -#define PTN3460_H_ - -#include - -#define PTN_SLAVE_ADR 0x20 -#define PTN_I2C_CONTROLLER 0 - -#define PTN_EDID_OFF 0x00 -#define PTN_EDID_LEN 0x80 -#define PTN_CONFIG_OFF 0x80 -#define PTN_FLASH_CFG_OFF 0xE8 -#define PTN_FLASH_CFG_LEN 0x04 -#define PTN_MAX_EDID_NUM 6 - -/* Define some error codes that can be used. */ -#define PTN_NO_ERROR 0x00000000 -#define PTN_BUS_ERROR 0x10000000 -#define PTN_INVALID_EDID 0x20000000 - -struct ptn_3460_config { - /* DisplayPort interface control. */ - uint8_t dp_interface_ctrl; - /* LVDS interface control register 1. */ - uint8_t lvds_interface_ctrl1; - /* LVDS interface control register 2. */ - uint8_t lvds_interface_ctrl2; - /* LVDS interface control register 3. */ - uint8_t lvds_interface_ctrl3; - /* Select which EDID-block is emulated. */ - uint8_t edid_rom_emulation; - /* Select which EDID block to map to 0..0x7F. */ - uint8_t edid_rom_access_ctrl; - /* Smallest PWM frequency for back light. */ - uint8_t pwm_min[3]; - /* Biggest PWM frequency for back light. */ - uint8_t pwm_max[3]; - /* Fast link training control register. */ - uint8_t fast_link_ctrl; - /* Pin configuration control register 1. */ - uint8_t pin_cfg_ctrl1; - /* Pin configuration control register 2. */ - uint8_t pin_cfg_ctrl2; - /* Default PWM bit count in DPCD register. */ - uint8_t pwm_default; - /* Current PWM bit count in DPCD register. */ - uint16_t pwm_value; - /* Default PWM frequency in DPCD register. */ - uint8_t pwm_default_freq; - /* Panel T3 timing value. */ - uint8_t t3_timing; - /* Panel T12 timing value. */ - uint8_t t12_timing; - /* Back light control register. */ - uint8_t backlight_ctrl; - /* Panel T2 delay. */ - uint8_t t2_delay; - /* Panel T4 timing value. */ - uint8_t t4_timing; - /* Panel T5 delay. */ - uint8_t t5_delay; -} __packed; - -struct ptn_3460_flash { - /* Flash command (erase or erase and flash). */ - uint8_t cmd; - /* Magic number needed by the flash algorithm. */ - uint16_t magic; - /* Trigger for starting flash operation. */ - uint8_t trigger; -} __packed; - -int ptn3460_init(const char *hwi_block); -int ptn3460_write_edid(uint8_t edid_num, const uint8_t data[PTN_EDID_LEN]); -int ptn_select_edid(uint8_t edid_num); -#endif /* PTN3460_H_ */ diff --git a/src/mainboard/siemens/mc_apl1/variants/mc_apl1/lcd_panel.c b/src/mainboard/siemens/mc_apl1/variants/mc_apl1/lcd_panel.c new file mode 100644 index 0000000000..e61588a02e --- /dev/null +++ b/src/mainboard/siemens/mc_apl1/variants/mc_apl1/lcd_panel.c @@ -0,0 +1,102 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2014-2019 Siemens AG + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include +#include +#include + +/** \brief This function provides EDID data to the driver for DP2LVDS Bridge (PTN3460) + * @param edid_data pointer to EDID data in driver +*/ +enum cb_err mb_get_edid(uint8_t edid_data[0x80]) +{ + const char *hwi_block = "hwinfo.hex"; + + if (hwilib_find_blocks(hwi_block) != CB_SUCCESS) { + printk(BIOS_ERR, "LCD: Info block \"%s\" not found!\n", hwi_block); + return CB_ERR; + } + + /* Get EDID data from hwinfo block */ + if (hwilib_get_field(Edid, edid_data, PTN_EDID_LEN) != PTN_EDID_LEN) { + printk(BIOS_ERR, "LCD: No EDID data available in %s\n", hwi_block); + return CB_ERR; + } + return CB_SUCCESS; +} + +/** \brief This function provides EDID block [0..6] to the driver for DP2LVDS Bridge (PTN3460) + * which has to be used. +*/ +uint8_t mb_select_edid_table(void) +{ + return 6; /* With this mainboard we use EDID block 6 for emulation in PTN3460. */ +} + +/** \brief Function to enable mainboard to adjust the config data of PTN3460. + * @param *cfg_ptr Pointer to the PTN config structure to modify. + * @return -1 on error; PTN_CFG_MODIFIED if data was modified and needs to be updated. +*/ +int mb_adjust_cfg(struct ptn_3460_config *cfg) +{ + const char *hwi_block = "hwinfo.hex"; + uint8_t disp_con = 0, color_depth = 0; + + if (hwilib_find_blocks(hwi_block) != CB_SUCCESS) { + printk(BIOS_ERR, "LCD: Info block \"%s\" not found!\n", hwi_block); + return -1; + } + + if (hwilib_get_field(PF_DisplCon, &disp_con, sizeof(disp_con)) != sizeof(disp_con)) { + printk(BIOS_ERR, "LCD: Missing panel features from %s\n", hwi_block); + return -1; + } + if (hwilib_get_field(PF_Color_Depth, &color_depth, + sizeof(color_depth)) != sizeof(color_depth)) { + printk(BIOS_ERR, "LCD: Missing panel features from %s\n", hwi_block); + return -1; + } + /* Set up configuration data according to the hwinfo block we got. */ + cfg->dp_interface_ctrl = 0x00; + cfg->lvds_interface_ctrl1 = 0x00; + if (disp_con == PF_DISPLCON_LVDS_DUAL) { + /* Turn on dual LVDS lane and clock. */ + cfg->lvds_interface_ctrl1 |= 0x0b; + } + if (color_depth == PF_COLOR_DEPTH_6BIT) { + /* Use 18 bits per pixel. */ + cfg->lvds_interface_ctrl1 |= 0x20; + } + /* 1 % clock spreading, 300 mV LVDS swing. */ + cfg->lvds_interface_ctrl2 = 0x13; + /* No LVDS lane swap. */ + cfg->lvds_interface_ctrl3 = 0x00; + /* Delay T2 (VDD to LVDS active) by 16 ms. */ + cfg->t2_delay = 1; + /* 500 ms from LVDS to backlight active. */ + cfg->t3_timing = 10; + /* 1 second re-power delay. */ + cfg->t12_timing = 20; + /* 150 ms backlight off to LVDS inactive. */ + cfg->t4_timing = 3; + /* Delay T5 (LVDS to VDD inactive) by 16 ms. */ + cfg->t5_delay = 1; + /* Enable backlight control. */ + cfg->backlight_ctrl = 0; + + return PTN_CFG_MODIFIED; +} diff --git a/src/mainboard/siemens/mc_apl1/variants/mc_apl1/mainboard.c b/src/mainboard/siemens/mc_apl1/variants/mc_apl1/mainboard.c index df6fc21bde..f119d5d19b 100644 --- a/src/mainboard/siemens/mc_apl1/variants/mc_apl1/mainboard.c +++ b/src/mainboard/siemens/mc_apl1/variants/mc_apl1/mainboard.c @@ -26,25 +26,13 @@ #include #include #include -#include #define TX_DWORD3 0xa8c void variant_mainboard_final(void) { - int status; struct device *dev = NULL; - /* - * Set up the DP2LVDS converter. - * ptn3460_init() may only be executed after i2c bus init. - */ - status = ptn3460_init("hwinfo.hex"); - if (status) - printk(BIOS_ERR, "LCD: Set up PTN with status 0x%x\n", status); - else - printk(BIOS_INFO, "LCD: Set up PTN was successful.\n"); - /* * PIR6 register mapping for PCIe root ports * INTA#->PIRQB#, INTB#->PIRQC#, INTC#->PIRQD#, INTD#-> PIRQA# diff --git a/src/mainboard/siemens/mc_apl1/variants/mc_apl1/ptn3460.c b/src/mainboard/siemens/mc_apl1/variants/mc_apl1/ptn3460.c deleted file mode 100644 index c0770f3124..0000000000 --- a/src/mainboard/siemens/mc_apl1/variants/mc_apl1/ptn3460.c +++ /dev/null @@ -1,171 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2014-2017 Siemens AG - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include -#include -#include - -/** - * This function sets up the DP2LVDS-converter to be used with the appropriate - * lcd panel. - * - * @param *hwi_block Filename in CBFS of the block to use as HW-Info. - * @return 0 on success or HWI-Data/PTN error code. - */ -int ptn3460_init(const char *hwi_block) -{ - struct ptn_3460_config cfg; - int status; - uint8_t disp_con = 0, color_depth = 0; - uint8_t edid_data[PTN_EDID_LEN]; - int i; - - if (!hwi_block || hwilib_find_blocks(hwi_block) != CB_SUCCESS) { - printk(BIOS_ERR, "LCD: Info block \"%s\" not found!\n", - hwi_block); - return 1; - } - /* Get all needed information from hwinfo block. */ - if (hwilib_get_field(Edid, edid_data, sizeof(edid_data)) != - sizeof(edid_data)) { - printk(BIOS_ERR, "LCD: No EDID data available in %s\n", - hwi_block); - return 1; - } - if ((hwilib_get_field(PF_DisplCon, &disp_con, sizeof(disp_con)) != - sizeof(disp_con))) { - printk(BIOS_ERR, "LCD: Missing panel features from %s\n", - hwi_block); - return 1; - } - if (hwilib_get_field(PF_Color_Depth, &color_depth, sizeof(color_depth)) - != sizeof(color_depth)) { - printk(BIOS_ERR, "LCD: Missing panel features from %s\n", - hwi_block); - return 1; - } - /* - * Here, all the desired information for setting up DP2LVDS converter - * is present. Inside the converter, table 6 will be used for the - * timings. - */ - status = ptn3460_write_edid(6, edid_data); - if (status) - return status; - /* Select this table to be emulated. */ - ptn_select_edid(6); - /* Read PTN configuration data. */ - status = i2c_read_bytes(PTN_I2C_CONTROLLER, PTN_SLAVE_ADR, - PTN_CONFIG_OFF, (uint8_t *)&cfg, - sizeof(cfg)); - if (status) - return (PTN_BUS_ERROR | status); - /* Set up configuration data according to the hwinfo block we get. */ - cfg.dp_interface_ctrl = 0; - cfg.lvds_interface_ctrl1 = 0x00; - if (disp_con == PF_DISPLCON_LVDS_DUAL) - /* Turn on dual LVDS lane and clock. */ - cfg.lvds_interface_ctrl1 |= 0x0b; - if (color_depth == PF_COLOR_DEPTH_6BIT) - /* Use 18 bits per pixel. */ - cfg.lvds_interface_ctrl1 |= 0x20; - - /* 1 % clock spreading, 300 mV LVDS swing. */ - cfg.lvds_interface_ctrl2 = 0x13; - /* No LVDS signal swap. */ - cfg.lvds_interface_ctrl3 = 0x00; - /* Delay T2 (VDD to LVDS active) by 16 ms. */ - cfg.t2_delay = 1; - /* 250 ms from LVDS to backlight active. */ - cfg.t3_timing = 10; - /* 1 second re-power delay. */ - cfg.t12_timing = 20; - /* 150 ms backlight off to LVDS inactive. */ - cfg.t4_timing = 3; - /* Delay T5 (LVDS to VDD inactive) by 16 ms. */ - cfg.t5_delay = 1; - /* Enable backlight control. */ - cfg.backlight_ctrl = 0; - - /* Write back configuration data to PTN3460. */ - for (i = 0; i < sizeof(struct ptn_3460_config); i++) { - status = i2c_writeb(PTN_I2C_CONTROLLER, PTN_SLAVE_ADR, - PTN_CONFIG_OFF+i, - *(((uint8_t *)&cfg)+i)); - if (status) - return (PTN_BUS_ERROR | status); - } - - return PTN_NO_ERROR; -} - -/** - * This function writes one Extended Display Identification Data (EDID) - * structure to PTN3460. - * - * @param edid_num Number of EDID that must be written (0..6). - * @param *data Pointer to a buffer where data to write is stored in. - * @return 0 on success or error code. - */ -int ptn3460_write_edid(uint8_t edid_num, const uint8_t data[PTN_EDID_LEN]) -{ - int status; - int i; - - if (edid_num > PTN_MAX_EDID_NUM) - return PTN_INVALID_EDID; - - /* First enable access to the desired EDID table. */ - status = i2c_writeb(PTN_I2C_CONTROLLER, PTN_SLAVE_ADR, - PTN_CONFIG_OFF + 5, edid_num); - if (status) - return (PTN_BUS_ERROR | status); - - /* Now we can simply write EDID-data to ptn3460. */ - for (i = 0; i < PTN_EDID_LEN; i++) { - status = i2c_writeb(PTN_I2C_CONTROLLER, PTN_SLAVE_ADR, - PTN_EDID_OFF + i, data[i]); - if (status) - return (PTN_BUS_ERROR | status); - } - - return PTN_NO_ERROR; -} - -/** - * This function selects one of 7 EDID-tables inside PTN3460 which should be - * emulated on DisplayPort and turn emulation ON. - * - * @param edid_num Number of EDID to emulate (0..6). - * @return 0 on success or error code. - */ -int ptn_select_edid(uint8_t edid_num) -{ - int status; - uint8_t val; - - if (edid_num > PTN_MAX_EDID_NUM) - return PTN_INVALID_EDID; - /* Enable emulation of the desired EDID table. */ - val = (edid_num << 1) | 1; - status = i2c_writeb(PTN_I2C_CONTROLLER, PTN_SLAVE_ADR, - PTN_CONFIG_OFF + 4, val); - if (status) - return (PTN_BUS_ERROR | status); - else - return PTN_NO_ERROR; -} diff --git a/src/mainboard/siemens/mc_apl1/variants/mc_apl4/Kconfig b/src/mainboard/siemens/mc_apl1/variants/mc_apl4/Kconfig index 31317b9280..b10bdc846b 100644 --- a/src/mainboard/siemens/mc_apl1/variants/mc_apl4/Kconfig +++ b/src/mainboard/siemens/mc_apl1/variants/mc_apl4/Kconfig @@ -8,6 +8,7 @@ config BOARD_SPECIFIC_OPTIONS select MAINBOARD_HAS_TPM2 select MAINBOARD_HAS_LPC_TPM select TPM_ON_FAST_SPI + select DRIVERS_I2C_PTN3460 config UART_FOR_CONSOLE default 1 diff --git a/src/mainboard/siemens/mc_apl1/variants/mc_apl4/Makefile.inc b/src/mainboard/siemens/mc_apl1/variants/mc_apl4/Makefile.inc index 482abf83dc..b1e6a0f74f 100644 --- a/src/mainboard/siemens/mc_apl1/variants/mc_apl4/Makefile.inc +++ b/src/mainboard/siemens/mc_apl1/variants/mc_apl4/Makefile.inc @@ -2,5 +2,4 @@ romstage-y += memory.c romstage-y += gpio.c ramstage-y += gpio.c -ramstage-y += mainboard.c -ramstage-y += ptn3460.c +ramstage-y += lcd_panel.c diff --git a/src/mainboard/siemens/mc_apl1/variants/mc_apl4/devicetree.cb b/src/mainboard/siemens/mc_apl1/variants/mc_apl4/devicetree.cb index fc9885ce7f..4074bae3bc 100644 --- a/src/mainboard/siemens/mc_apl1/variants/mc_apl4/devicetree.cb +++ b/src/mainboard/siemens/mc_apl1/variants/mc_apl4/devicetree.cb @@ -75,7 +75,12 @@ chip soc/intel/apollolake device pci 17.0 on end # - I2C 4 device pci 17.1 on end # - I2C 5 device pci 17.2 on end # - I2C 6 - device pci 17.3 on end # - I2C 7 + device pci 17.3 on # - I2C 7 + # Enable external display bridge (eDP to LVDS) + chip drivers/i2c/ptn3460 + device i2c 0x60 on end # PTN3460 DP2LVDS Bridge + end + end device pci 18.0 on end # - UART 0 device pci 18.1 on end # - UART 1 device pci 18.2 on end # - UART 2 diff --git a/src/mainboard/siemens/mc_apl1/variants/mc_apl4/include/variant/ptn3460.h b/src/mainboard/siemens/mc_apl1/variants/mc_apl4/include/variant/ptn3460.h deleted file mode 100644 index 2a52bf5e02..0000000000 --- a/src/mainboard/siemens/mc_apl1/variants/mc_apl4/include/variant/ptn3460.h +++ /dev/null @@ -1,91 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2014-2018 Siemens AG - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef PTN3460_H_ -#define PTN3460_H_ - -#include - -#define PTN_SLAVE_ADR 0x60 -#define PTN_I2C_CONTROLLER 7 - -#define PTN_EDID_OFF 0x00 -#define PTN_EDID_LEN 0x80 -#define PTN_CONFIG_OFF 0x80 -#define PTN_FLASH_CFG_OFF 0xE8 -#define PTN_FLASH_CFG_LEN 0x04 -#define PTN_MAX_EDID_NUM 6 - -/* Define some error codes that can be used. */ -#define PTN_NO_ERROR 0x00000000 -#define PTN_BUS_ERROR 0x10000000 -#define PTN_INVALID_EDID 0x20000000 - -struct ptn_3460_config { - /* DisplayPort interface control. */ - uint8_t dp_interface_ctrl; - /* LVDS interface control register 1. */ - uint8_t lvds_interface_ctrl1; - /* LVDS interface control register 2. */ - uint8_t lvds_interface_ctrl2; - /* LVDS interface control register 3. */ - uint8_t lvds_interface_ctrl3; - /* Select which EDID-block is emulated. */ - uint8_t edid_rom_emulation; - /* Select which EDID block to map to 0..0x7F. */ - uint8_t edid_rom_access_ctrl; - /* Smallest PWM frequency for back light. */ - uint8_t pwm_min[3]; - /* Biggest PWM frequency for back light. */ - uint8_t pwm_max[3]; - /* Fast link training control register. */ - uint8_t fast_link_ctrl; - /* Pin configuration control register 1. */ - uint8_t pin_cfg_ctrl1; - /* Pin configuration control register 2. */ - uint8_t pin_cfg_ctrl2; - /* Default PWM bit count in DPCD register. */ - uint8_t pwm_default; - /* Current PWM bit count in DPCD register. */ - uint16_t pwm_value; - /* Default PWM frequency in DPCD register. */ - uint8_t pwm_default_freq; - /* Panel T3 timing value. */ - uint8_t t3_timing; - /* Panel T12 timing value. */ - uint8_t t12_timing; - /* Back light control register. */ - uint8_t backlight_ctrl; - /* Panel T2 delay. */ - uint8_t t2_delay; - /* Panel T4 timing value. */ - uint8_t t4_timing; - /* Panel T5 delay. */ - uint8_t t5_delay; -} __packed; - -struct ptn_3460_flash { - /* Flash command (erase or erase and flash). */ - uint8_t cmd; - /* Magic number needed by the flash algorithm. */ - uint16_t magic; - /* Trigger for starting flash operation. */ - uint8_t trigger; -} __packed; - -int ptn3460_init(const char *hwi_block); -int ptn3460_write_edid(uint8_t edid_num, const uint8_t data[PTN_EDID_LEN]); -int ptn_select_edid(uint8_t edid_num); -#endif /* PTN3460_H_ */ diff --git a/src/mainboard/siemens/mc_apl1/variants/mc_apl4/lcd_panel.c b/src/mainboard/siemens/mc_apl1/variants/mc_apl4/lcd_panel.c new file mode 100644 index 0000000000..abfcfe37a8 --- /dev/null +++ b/src/mainboard/siemens/mc_apl1/variants/mc_apl4/lcd_panel.c @@ -0,0 +1,103 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2014-2019 Siemens AG + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include +#include +#include + +/** \brief This function provides EDID data to the driver for DP2LVDS Bridge (PTN3460) + * @param edid_data pointer to EDID data in driver +*/ +enum cb_err mb_get_edid(uint8_t edid_data[0x80]) +{ + const char *hwi_block = "hwinfo.hex"; + + if (hwilib_find_blocks(hwi_block) != CB_SUCCESS) { + printk(BIOS_ERR, "LCD: Info block \"%s\" not found!\n", hwi_block); + return CB_ERR; + } + + /* Get EDID data from hwinfo block */ + if (hwilib_get_field(Edid, edid_data, PTN_EDID_LEN) != PTN_EDID_LEN) { + printk(BIOS_ERR, "LCD: No EDID data available in %s\n", hwi_block); + return CB_ERR; + } + return CB_SUCCESS; +} + +/** \brief This function provides EDID block [0..6] to the driver for DP2LVDS Bridge (PTN3460) + * which has to be used. +*/ +uint8_t mb_select_edid_table(void) +{ + return 6; /* With this mainboard we use EDID block 6 for emulation in PTN3460. */ +} + +/** \brief Function to enable mainboard to adjust the config data of PTN3460. + * @param *cfg_ptr Pointer to the PTN config structure to modify. + * @return -1 on error; PTN_CFG_MODIFIED if data was modified and needs to be updated. +*/ +int mb_adjust_cfg(struct ptn_3460_config *cfg) +{ + const char *hwi_block = "hwinfo.hex"; + uint8_t disp_con = 0, color_depth = 0; + + if (hwilib_find_blocks(hwi_block) != CB_SUCCESS) { + printk(BIOS_ERR, "LCD: Info block \"%s\" not found!\n", hwi_block); + return -1; + } + + if (hwilib_get_field(PF_DisplCon, &disp_con, sizeof(disp_con)) != sizeof(disp_con)) { + printk(BIOS_ERR, "LCD: Missing panel features from %s\n", hwi_block); + return -1; + } + if (hwilib_get_field(PF_Color_Depth, &color_depth, + sizeof(color_depth)) != sizeof(color_depth)) { + printk(BIOS_ERR, "LCD: Missing panel features from %s\n", hwi_block); + return -1; + } + /* Set up configuration data according to the hwinfo block we got. */ + cfg->dp_interface_ctrl = 0x00; + /* Use odd-bus for clock distribution only. */ + cfg->lvds_interface_ctrl1 = 0x01; + if (disp_con == PF_DISPLCON_LVDS_DUAL) { + /* Turn on dual LVDS lane and clock. */ + cfg->lvds_interface_ctrl1 |= 0x0b; + } + if (color_depth == PF_COLOR_DEPTH_6BIT) { + /* Use 18 bits per pixel. */ + cfg->lvds_interface_ctrl1 |= 0x20; + } + /* No clock spreading, 300 mV LVDS swing. */ + cfg->lvds_interface_ctrl2 = 0x03; + /* Swap LVDS lanes (N vs. P). */ + cfg->lvds_interface_ctrl3 = 0x04; + /* Delay T2 (VDD to LVDS active) by 16 ms. */ + cfg->t2_delay = 1; + /* 500 ms from LVDS to backlight active. */ + cfg->t3_timing = 10; + /* 1 second re-power delay. */ + cfg->t12_timing = 20; + /* 150 ms backlight off to LVDS inactive. */ + cfg->t4_timing = 3; + /* Delay T5 (LVDS to VDD inactive) by 16 ms. */ + cfg->t5_delay = 1; + /* Enable backlight control. */ + cfg->backlight_ctrl = 0; + + return PTN_CFG_MODIFIED; +} diff --git a/src/mainboard/siemens/mc_apl1/variants/mc_apl4/mainboard.c b/src/mainboard/siemens/mc_apl1/variants/mc_apl4/mainboard.c deleted file mode 100644 index 65e78bb378..0000000000 --- a/src/mainboard/siemens/mc_apl1/variants/mc_apl4/mainboard.c +++ /dev/null @@ -1,35 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2018 Siemens AG - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include -#include -#include - -void variant_mainboard_final(void) -{ - int status; - - /* - * Set up the DP2LVDS converter. - * ptn3460_init() may only be executed after i2c bus init. - */ - status = ptn3460_init("hwinfo.hex"); - if (status) - printk(BIOS_ERR, "LCD: Set up PTN with status 0x%x\n", status); - else - printk(BIOS_INFO, "LCD: Set up PTN was successful.\n"); -} diff --git a/src/mainboard/siemens/mc_apl1/variants/mc_apl4/ptn3460.c b/src/mainboard/siemens/mc_apl1/variants/mc_apl4/ptn3460.c deleted file mode 100644 index 47763ae5d8..0000000000 --- a/src/mainboard/siemens/mc_apl1/variants/mc_apl4/ptn3460.c +++ /dev/null @@ -1,172 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2014-2018 Siemens AG - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include -#include -#include - -/* - * This function sets up the DP2LVDS-converter to be used with the appropriate - * lcd panel. - * - * @param *hwi_block Filename in CBFS of the block to use as HW-Info. - * @return 0 on success or HWI-Data/PTN error code. - */ -int ptn3460_init(const char *hwi_block) -{ - struct ptn_3460_config cfg; - int status; - uint8_t disp_con = 0, color_depth = 0; - uint8_t edid_data[PTN_EDID_LEN]; - int i; - - if (!hwi_block || hwilib_find_blocks(hwi_block) != CB_SUCCESS) { - printk(BIOS_ERR, "LCD: Info block \"%s\" not found!\n", - hwi_block); - return 1; - } - /* Get all needed information from hwinfo block. */ - if (hwilib_get_field(Edid, edid_data, sizeof(edid_data)) != - sizeof(edid_data)) { - printk(BIOS_ERR, "LCD: No EDID data available in %s\n", - hwi_block); - return 1; - } - if ((hwilib_get_field(PF_DisplCon, &disp_con, sizeof(disp_con)) != - sizeof(disp_con))) { - printk(BIOS_ERR, "LCD: Missing panel features from %s\n", - hwi_block); - return 1; - } - if (hwilib_get_field(PF_Color_Depth, &color_depth, sizeof(color_depth)) - != sizeof(color_depth)) { - printk(BIOS_ERR, "LCD: Missing panel features from %s\n", - hwi_block); - return 1; - } - /* - * Here, all the desired information for setting up DP2LVDS converter - * is present. Inside the converter, table 6 will be used for the - * timings. - */ - status = ptn3460_write_edid(6, edid_data); - if (status) - return status; - /* Select this table to be emulated. */ - ptn_select_edid(6); - /* Read PTN configuration data. */ - status = i2c_read_bytes(PTN_I2C_CONTROLLER, PTN_SLAVE_ADR, - PTN_CONFIG_OFF, (uint8_t *)&cfg, - sizeof(cfg)); - if (status) - return (PTN_BUS_ERROR | status); - /* Set up configuration data according to the hwinfo block we get. */ - cfg.dp_interface_ctrl = 0; - /* Use odd-bus for clock distribution only. */ - cfg.lvds_interface_ctrl1 = 0x01; - if (disp_con == PF_DISPLCON_LVDS_DUAL) - /* Turn on dual LVDS lane and clock. */ - cfg.lvds_interface_ctrl1 |= 0x0b; - if (color_depth == PF_COLOR_DEPTH_6BIT) - /* Use 18 bits per pixel. */ - cfg.lvds_interface_ctrl1 |= 0x20; - - /* No clock spreading, 300 mV LVDS swing. */ - cfg.lvds_interface_ctrl2 = 0x03; - /* Swap LVDS signal (N vs. P). */ - cfg.lvds_interface_ctrl3 = 0x04; - /* Delay T2 (VDD to LVDS active) by 16 ms. */ - cfg.t2_delay = 1; - /* 250 ms from LVDS to backlight active. */ - cfg.t3_timing = 10; - /* 1 second re-power delay. */ - cfg.t12_timing = 20; - /* 150 ms backlight off to LVDS inactive. */ - cfg.t4_timing = 3; - /* Delay T5 (LVDS to VDD inactive) by 16 ms. */ - cfg.t5_delay = 1; - /* Enable backlight control. */ - cfg.backlight_ctrl = 0; - - /* Write back configuration data to PTN3460. */ - for (i = 0; i < sizeof(struct ptn_3460_config); i++) { - status = i2c_writeb(PTN_I2C_CONTROLLER, PTN_SLAVE_ADR, - PTN_CONFIG_OFF+i, - *(((uint8_t *)&cfg)+i)); - if (status) - return (PTN_BUS_ERROR | status); - } - - return PTN_NO_ERROR; -} - -/* - * This function writes one Extended Display Identification Data (EDID) - * structure to PTN3460. - * - * @param edid_num Number of EDID that must be written (0..6). - * @param *data Pointer to a buffer where data to write is stored in. - * @return 0 on success or error code. - */ -int ptn3460_write_edid(uint8_t edid_num, const uint8_t data[PTN_EDID_LEN]) -{ - int status; - int i; - - if (edid_num > PTN_MAX_EDID_NUM) - return PTN_INVALID_EDID; - - /* First enable access to the desired EDID table. */ - status = i2c_writeb(PTN_I2C_CONTROLLER, PTN_SLAVE_ADR, - PTN_CONFIG_OFF + 5, edid_num); - if (status) - return (PTN_BUS_ERROR | status); - - /* Now we can simply write EDID-data to ptn3460. */ - for (i = 0; i < PTN_EDID_LEN; i++) { - status = i2c_writeb(PTN_I2C_CONTROLLER, PTN_SLAVE_ADR, - PTN_EDID_OFF + i, data[i]); - if (status) - return (PTN_BUS_ERROR | status); - } - - return PTN_NO_ERROR; -} - -/* - * This function selects one of 7 EDID-tables inside PTN3460 which should be - * emulated on DisplayPort and turn emulation ON. - * - * @param edid_num Number of EDID to emulate (0..6). - * @return 0 on success or error code. - */ -int ptn_select_edid(uint8_t edid_num) -{ - int status; - uint8_t val; - - if (edid_num > PTN_MAX_EDID_NUM) - return PTN_INVALID_EDID; - /* Enable emulation of the desired EDID table. */ - val = (edid_num << 1) | 1; - status = i2c_writeb(PTN_I2C_CONTROLLER, PTN_SLAVE_ADR, - PTN_CONFIG_OFF + 4, val); - if (status) - return (PTN_BUS_ERROR | status); - else - return PTN_NO_ERROR; -} diff --git a/src/mainboard/siemens/mc_apl1/variants/mc_apl5/Kconfig b/src/mainboard/siemens/mc_apl1/variants/mc_apl5/Kconfig index 21d7ac7b78..e46a0de6f9 100644 --- a/src/mainboard/siemens/mc_apl1/variants/mc_apl5/Kconfig +++ b/src/mainboard/siemens/mc_apl1/variants/mc_apl5/Kconfig @@ -11,6 +11,7 @@ config BOARD_SPECIFIC_OPTIONS select MAINBOARD_HAS_TPM2 select MAINBOARD_HAS_LPC_TPM select TPM_ON_FAST_SPI + select DRIVERS_I2C_PTN3460 config CBFS_SIZE default 0xb4e000 diff --git a/src/mainboard/siemens/mc_apl1/variants/mc_apl5/Makefile.inc b/src/mainboard/siemens/mc_apl1/variants/mc_apl5/Makefile.inc index 03759d2633..bd81552afc 100644 --- a/src/mainboard/siemens/mc_apl1/variants/mc_apl5/Makefile.inc +++ b/src/mainboard/siemens/mc_apl1/variants/mc_apl5/Makefile.inc @@ -2,4 +2,4 @@ romstage-y += gpio.c ramstage-y += gpio.c ramstage-y += mainboard.c -ramstage-y += ptn3460.c +ramstage-y += lcd_panel.c diff --git a/src/mainboard/siemens/mc_apl1/variants/mc_apl5/devicetree.cb b/src/mainboard/siemens/mc_apl1/variants/mc_apl5/devicetree.cb index 3b28a26396..723ecb369c 100644 --- a/src/mainboard/siemens/mc_apl1/variants/mc_apl5/devicetree.cb +++ b/src/mainboard/siemens/mc_apl1/variants/mc_apl5/devicetree.cb @@ -84,6 +84,10 @@ chip soc/intel/apollolake register "user_weekday" = "4" device i2c 0x32 on end # RTC RX6110 SA end + # Enable external display bridge (eDP to LVDS) + chip drivers/i2c/ptn3460 + device i2c 0x20 on end # PTN3460 DP2LVDS Bridge + end end device pci 16.1 off end # - I2C 1 device pci 16.2 off end # - I2C 2 diff --git a/src/mainboard/siemens/mc_apl1/variants/mc_apl5/include/variant/ptn3460.h b/src/mainboard/siemens/mc_apl1/variants/mc_apl5/include/variant/ptn3460.h deleted file mode 100644 index 3ff35d9ee8..0000000000 --- a/src/mainboard/siemens/mc_apl1/variants/mc_apl5/include/variant/ptn3460.h +++ /dev/null @@ -1,91 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2014-2017 Siemens AG - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef PTN3460_H_ -#define PTN3460_H_ - -#include - -#define PTN_SLAVE_ADR 0x20 -#define PTN_I2C_CONTROLLER 0 - -#define PTN_EDID_OFF 0x00 -#define PTN_EDID_LEN 0x80 -#define PTN_CONFIG_OFF 0x80 -#define PTN_FLASH_CFG_OFF 0xE8 -#define PTN_FLASH_CFG_LEN 0x04 -#define PTN_MAX_EDID_NUM 6 - -/* Define some error codes that can be used. */ -#define PTN_NO_ERROR 0x00000000 -#define PTN_BUS_ERROR 0x10000000 -#define PTN_INVALID_EDID 0x20000000 - -struct ptn_3460_config { - /* DisplayPort interface control. */ - uint8_t dp_interface_ctrl; - /* LVDS interface control register 1. */ - uint8_t lvds_interface_ctrl1; - /* LVDS interface control register 2. */ - uint8_t lvds_interface_ctrl2; - /* LVDS interface control register 3. */ - uint8_t lvds_interface_ctrl3; - /* Select which EDID-block is emulated. */ - uint8_t edid_rom_emulation; - /* Select which EDID block to map to 0..0x7F. */ - uint8_t edid_rom_access_ctrl; - /* Smallest PWM frequency for back light. */ - uint8_t pwm_min[3]; - /* Biggest PWM frequency for back light. */ - uint8_t pwm_max[3]; - /* Fast link training control register. */ - uint8_t fast_link_ctrl; - /* Pin configuration control register 1. */ - uint8_t pin_cfg_ctrl1; - /* Pin configuration control register 2. */ - uint8_t pin_cfg_ctrl2; - /* Default PWM bit count in DPCD register. */ - uint8_t pwm_default; - /* Current PWM bit count in DPCD register. */ - uint16_t pwm_value; - /* Default PWM frequency in DPCD register. */ - uint8_t pwm_default_freq; - /* Panel T3 timing value. */ - uint8_t t3_timing; - /* Panel T12 timing value. */ - uint8_t t12_timing; - /* Back light control register. */ - uint8_t backlight_ctrl; - /* Panel T2 delay. */ - uint8_t t2_delay; - /* Panel T4 timing value. */ - uint8_t t4_timing; - /* Panel T5 delay. */ - uint8_t t5_delay; -} __packed; - -struct ptn_3460_flash { - /* Flash command (erase or erase and flash). */ - uint8_t cmd; - /* Magic number needed by the flash algorithm. */ - uint16_t magic; - /* Trigger for starting flash operation. */ - uint8_t trigger; -} __packed; - -int ptn3460_init(const char *hwi_block); -int ptn3460_write_edid(uint8_t edid_num, const uint8_t data[PTN_EDID_LEN]); -int ptn_select_edid(uint8_t edid_num); -#endif /* PTN3460_H_ */ diff --git a/src/mainboard/siemens/mc_apl1/variants/mc_apl5/lcd_panel.c b/src/mainboard/siemens/mc_apl1/variants/mc_apl5/lcd_panel.c new file mode 100644 index 0000000000..1b0f730d0b --- /dev/null +++ b/src/mainboard/siemens/mc_apl1/variants/mc_apl5/lcd_panel.c @@ -0,0 +1,128 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2014-2019 Siemens AG + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include +#include +#include +#include +#include + +static void igd_disable(void) +{ + struct device *root_dev = pcidev_path_on_root(SA_DEVFN_ROOT); + uint8_t deven; + uint16_t ggc; + + /* GMCH Graphics Control Register */ + ggc = pci_read_config16(root_dev, 0x50); + /* Set size of Graphics Translation Table Memory (GGMS) [7:6] + * to 0 and select 0 MB for Graphics Memory (GMS) [15:8]. */ + ggc &= ~(0xffc0); + /* Disable IGD VGA (IVD). */ + ggc |= 0x2; + pci_write_config16(root_dev, 0x50, ggc); + /* Device Enable Register */ + deven = pci_read_config8(root_dev, 0x54); + /* Disable IGD device (D2F0EN). */ + deven &= ~(0x10); + pci_write_config8(root_dev, 0x54, deven); +} + +/** \brief This function provides EDID data to the driver for DP2LVDS Bridge (PTN3460) + * @param edid_data pointer to EDID data in driver +*/ +enum cb_err mb_get_edid(uint8_t edid_data[0x80]) +{ + const char *hwi_block = "hwinfo.hex"; + + if (hwilib_find_blocks(hwi_block) != CB_SUCCESS) { + printk(BIOS_ERR, "LCD: Info block \"%s\" not found!\n", hwi_block); + return CB_ERR; + } + + /* Get EDID data from hwinfo block */ + if (hwilib_get_field(Edid, edid_data, PTN_EDID_LEN) != PTN_EDID_LEN) { + /* Disable IGD to avoid panel failures. */ + igd_disable(); + printk(BIOS_ERR, "LCD: No EDID data available in %s\n", hwi_block); + return CB_ERR; + } + return CB_SUCCESS; +} + +/** \brief This function provides EDID block [0..6] to the driver for DP2LVDS Bridge (PTN3460) + * which has to be used. +*/ +uint8_t mb_select_edid_table(void) +{ + return 6; /* With this mainboard we use EDID block 6 for emulation in PTN3460. */ +} + +/** \brief Function to enable mainboard to adjust the config data of PTN3460. + * @param *cfg_ptr Pointer to the PTN config structure to modify. + * @return -1 on error; PTN_CFG_MODIFIED if data was modified and needs to be updated. +*/ +int mb_adjust_cfg(struct ptn_3460_config *cfg) +{ + const char *hwi_block = "hwinfo.hex"; + uint8_t disp_con = 0, color_depth = 0; + + if (hwilib_find_blocks(hwi_block) != CB_SUCCESS) { + printk(BIOS_ERR, "LCD: Info block \"%s\" not found!\n", hwi_block); + return -1; + } + + if (hwilib_get_field(PF_DisplCon, &disp_con, sizeof(disp_con)) != sizeof(disp_con)) { + printk(BIOS_ERR, "LCD: Missing panel features from %s\n", hwi_block); + return -1; + } + if (hwilib_get_field(PF_Color_Depth, &color_depth, + sizeof(color_depth)) != sizeof(color_depth)) { + printk(BIOS_ERR, "LCD: Missing panel features from %s\n", hwi_block); + return -1; + } + /* Set up configuration data according to the hwinfo block we got. */ + cfg->dp_interface_ctrl = 0x00; + /* Drive LVDS clock for single mode on odd bus per default. */ + cfg->lvds_interface_ctrl1 = 0x01; + if (disp_con == PF_DISPLCON_LVDS_DUAL) { + /* Turn on dual LVDS lane and clock. */ + cfg->lvds_interface_ctrl1 |= 0x0b; + } + if (color_depth == PF_COLOR_DEPTH_6BIT) { + /* Use 18 bits per pixel. */ + cfg->lvds_interface_ctrl1 |= 0x20; + } + /* 1 % clock spreading, 300 mV LVDS swing. */ + cfg->lvds_interface_ctrl2 = 0x13; + /* No LVDS lane swap. */ + cfg->lvds_interface_ctrl3 = 0x00; + /* Delay T2 (VDD to LVDS active) by 16 ms. */ + cfg->t2_delay = 1; + /* 500 ms from LVDS to backlight active. */ + cfg->t3_timing = 10; + /* 1 second re-power delay. */ + cfg->t12_timing = 20; + /* 150 ms backlight off to LVDS inactive. */ + cfg->t4_timing = 3; + /* Delay T5 (LVDS to VDD inactive) by 16 ms. */ + cfg->t5_delay = 1; + /* Enable backlight control. */ + cfg->backlight_ctrl = 0; + + return PTN_CFG_MODIFIED; +} diff --git a/src/mainboard/siemens/mc_apl1/variants/mc_apl5/mainboard.c b/src/mainboard/siemens/mc_apl1/variants/mc_apl5/mainboard.c index e1b56bda13..f43cf8588c 100644 --- a/src/mainboard/siemens/mc_apl1/variants/mc_apl5/mainboard.c +++ b/src/mainboard/siemens/mc_apl1/variants/mc_apl5/mainboard.c @@ -27,26 +27,14 @@ #include #include #include -#include #define TX_DWORD3 0xa8c void variant_mainboard_final(void) { - int status; struct device *dev = NULL; uint16_t cmd; - /* - * Set up the DP2LVDS converter. - * ptn3460_init() may only be executed after i2c bus init. - */ - status = ptn3460_init("hwinfo.hex"); - if (status) - printk(BIOS_ERR, "LCD: Set up PTN with status 0x%x\n", status); - else - printk(BIOS_INFO, "LCD: Set up PTN was successful.\n"); - /* * PIR6 register mapping for PCIe root ports * INTA#->PIRQB#, INTB#->PIRQC#, INTC#->PIRQD#, INTD#-> PIRQA# diff --git a/src/mainboard/siemens/mc_apl1/variants/mc_apl5/ptn3460.c b/src/mainboard/siemens/mc_apl1/variants/mc_apl5/ptn3460.c deleted file mode 100644 index 2cc7dd4532..0000000000 --- a/src/mainboard/siemens/mc_apl1/variants/mc_apl5/ptn3460.c +++ /dev/null @@ -1,197 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2014-2017 Siemens AG - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include -#include -#include -#include -#include - -static void igd_disable(void) -{ - struct device *root_dev = pcidev_path_on_root(SA_DEVFN_ROOT); - uint8_t deven; - uint16_t ggc; - - /* GMCH Graphics Control Register */ - ggc = pci_read_config16(root_dev, 0x50); - /* Set size of Graphics Translation Table Memory (GGMS) [7:6] - * to 0 and select 0 MB for Graphics Memory (GMS) [15:8]. */ - ggc &= ~(0xffc0); - /* Disable IGD VGA (IVD). */ - ggc |= 0x2; - pci_write_config16(root_dev, 0x50, ggc); - /* Device Enable Register */ - deven = pci_read_config8(root_dev, 0x54); - /* Disable IGD device (D2F0EN). */ - deven &= ~(0x10); - pci_write_config8(root_dev, 0x54, deven); -} - -/** - * This function sets up the DP2LVDS-converter to be used with the appropriate - * lcd panel. - * - * @param *hwi_block Filename in CBFS of the block to use as HW-Info. - * @return 0 on success or HWI-Data/PTN error code. - */ -int ptn3460_init(const char *hwi_block) -{ - struct ptn_3460_config cfg; - int status; - uint8_t disp_con = 0, color_depth = 0; - uint8_t edid_data[PTN_EDID_LEN]; - int i; - - if (!hwi_block || hwilib_find_blocks(hwi_block) != CB_SUCCESS) { - printk(BIOS_ERR, "LCD: Info block \"%s\" not found!\n", - hwi_block); - return 1; - } - /* Get all needed information from hwinfo block. */ - if (hwilib_get_field(Edid, edid_data, sizeof(edid_data)) != - sizeof(edid_data)) { - /* Disable IGD to avoid panel failures. */ - igd_disable(); - printk(BIOS_ERR, "LCD: No EDID data available in %s\n", - hwi_block); - return 1; - } - if ((hwilib_get_field(PF_DisplCon, &disp_con, sizeof(disp_con)) != - sizeof(disp_con))) { - printk(BIOS_ERR, "LCD: Missing panel features from %s\n", - hwi_block); - return 1; - } - if (hwilib_get_field(PF_Color_Depth, &color_depth, sizeof(color_depth)) - != sizeof(color_depth)) { - printk(BIOS_ERR, "LCD: Missing panel features from %s\n", - hwi_block); - return 1; - } - /* - * Here, all the desired information for setting up DP2LVDS converter - * is present. Inside the converter, table 6 will be used for the - * timings. - */ - status = ptn3460_write_edid(6, edid_data); - if (status) - return status; - /* Select this table to be emulated. */ - ptn_select_edid(6); - /* Read PTN configuration data. */ - status = i2c_read_bytes(PTN_I2C_CONTROLLER, PTN_SLAVE_ADR, - PTN_CONFIG_OFF, (uint8_t *)&cfg, - sizeof(cfg)); - if (status) - return (PTN_BUS_ERROR | status); - /* Set up configuration data according to the hwinfo block we get. */ - cfg.dp_interface_ctrl = 0; - /* Drive LVDS clock for single mode on odd bus per default. */ - cfg.lvds_interface_ctrl1 = 0x01; - if (disp_con == PF_DISPLCON_LVDS_DUAL) - /* Turn on dual LVDS lane and clock. */ - cfg.lvds_interface_ctrl1 |= 0x0b; - if (color_depth == PF_COLOR_DEPTH_6BIT) - /* Use 18 bits per pixel. */ - cfg.lvds_interface_ctrl1 |= 0x20; - - /* 1 % clock spreading, 300 mV LVDS swing. */ - cfg.lvds_interface_ctrl2 = 0x13; - /* No LVDS signal swap. */ - cfg.lvds_interface_ctrl3 = 0x00; - /* Delay T2 (VDD to LVDS active) by 16 ms. */ - cfg.t2_delay = 1; - /* 250 ms from LVDS to backlight active. */ - cfg.t3_timing = 10; - /* 1 second re-power delay. */ - cfg.t12_timing = 20; - /* 150 ms backlight off to LVDS inactive. */ - cfg.t4_timing = 3; - /* Delay T5 (LVDS to VDD inactive) by 16 ms. */ - cfg.t5_delay = 1; - /* Enable backlight control. */ - cfg.backlight_ctrl = 0; - - /* Write back configuration data to PTN3460. */ - for (i = 0; i < sizeof(struct ptn_3460_config); i++) { - status = i2c_writeb(PTN_I2C_CONTROLLER, PTN_SLAVE_ADR, - PTN_CONFIG_OFF+i, - *(((uint8_t *)&cfg)+i)); - if (status) - return (PTN_BUS_ERROR | status); - } - - return PTN_NO_ERROR; -} - -/** - * This function writes one Extended Display Identification Data (EDID) - * structure to PTN3460. - * - * @param edid_num Number of EDID that must be written (0..6). - * @param *data Pointer to a buffer where data to write is stored in. - * @return 0 on success or error code. - */ -int ptn3460_write_edid(uint8_t edid_num, const uint8_t data[PTN_EDID_LEN]) -{ - int status; - int i; - - if (edid_num > PTN_MAX_EDID_NUM) - return PTN_INVALID_EDID; - - /* First enable access to the desired EDID table. */ - status = i2c_writeb(PTN_I2C_CONTROLLER, PTN_SLAVE_ADR, - PTN_CONFIG_OFF + 5, edid_num); - if (status) - return (PTN_BUS_ERROR | status); - - /* Now we can simply write EDID-data to ptn3460. */ - for (i = 0; i < PTN_EDID_LEN; i++) { - status = i2c_writeb(PTN_I2C_CONTROLLER, PTN_SLAVE_ADR, - PTN_EDID_OFF + i, data[i]); - if (status) - return (PTN_BUS_ERROR | status); - } - - return PTN_NO_ERROR; -} - -/** - * This function selects one of 7 EDID-tables inside PTN3460 which should be - * emulated on DisplayPort and turn emulation ON. - * - * @param edid_num Number of EDID to emulate (0..6). - * @return 0 on success or error code. - */ -int ptn_select_edid(uint8_t edid_num) -{ - int status; - uint8_t val; - - if (edid_num > PTN_MAX_EDID_NUM) - return PTN_INVALID_EDID; - /* Enable emulation of the desired EDID table. */ - val = (edid_num << 1) | 1; - status = i2c_writeb(PTN_I2C_CONTROLLER, PTN_SLAVE_ADR, - PTN_CONFIG_OFF + 4, val); - if (status) - return (PTN_BUS_ERROR | status); - else - return PTN_NO_ERROR; -} diff --git a/src/mainboard/siemens/mc_tcu3/Kconfig b/src/mainboard/siemens/mc_tcu3/Kconfig index 508aaebefb..8e01cdec4f 100644 --- a/src/mainboard/siemens/mc_tcu3/Kconfig +++ b/src/mainboard/siemens/mc_tcu3/Kconfig @@ -29,6 +29,7 @@ config BOARD_SPECIFIC_OPTIONS select USE_BLOBS select CBFS_AUTOGEN_ATTRIBUTES select USE_SIEMENS_HWILIB + select DRIVERS_I2C_PTN3460 config MAINBOARD_DIR string diff --git a/src/mainboard/siemens/mc_tcu3/Makefile.inc b/src/mainboard/siemens/mc_tcu3/Makefile.inc index 05b4e60193..3de042242b 100644 --- a/src/mainboard/siemens/mc_tcu3/Makefile.inc +++ b/src/mainboard/siemens/mc_tcu3/Makefile.inc @@ -17,4 +17,3 @@ ramstage-y += gpio.c ramstage-y += irqroute.c ramstage-y += lcd_panel.c -ramstage-y += ptn3460.c diff --git a/src/mainboard/siemens/mc_tcu3/devicetree.cb b/src/mainboard/siemens/mc_tcu3/devicetree.cb index 433eebeabf..a1416e490e 100644 --- a/src/mainboard/siemens/mc_tcu3/devicetree.cb +++ b/src/mainboard/siemens/mc_tcu3/devicetree.cb @@ -50,7 +50,12 @@ chip soc/intel/fsp_baytrail device pci 16.0 off end # 8086 0F37 - OTG controller device pci 17.0 on end # 8086 0F50 - EMMC 4.5 Port (MMC1 pins) - Only 1 EMMC port at a time device pci 18.0 on end # 8086 0F40 - SIO - DMA - device pci 18.1 on end # 8086 0F41 - I2C Port 1 + device pci 18.1 on # 8086 0F41 - I2C Port 1 + # Enable external display bridge (eDP to LVDS) + chip drivers/i2c/ptn3460 + device i2c 0x20 on end # PTN3460 DP2LVDS Bridge + end + end device pci 18.2 on end # 8086 0F42 - I2C Port 2 device pci 18.3 on end # 8086 0F43 - I2C Port 3 device pci 18.4 on end # 8086 0F44 - I2C Port 4 diff --git a/src/mainboard/siemens/mc_tcu3/lcd_panel.c b/src/mainboard/siemens/mc_tcu3/lcd_panel.c index c4456afb7a..c4660ee8cc 100644 --- a/src/mainboard/siemens/mc_tcu3/lcd_panel.c +++ b/src/mainboard/siemens/mc_tcu3/lcd_panel.c @@ -1,7 +1,7 @@ /* - * This file is part of the coreboot project. +* This file is part of the coreboot project. * - * Copyright (C) 2014 Siemens AG + * Copyright (C) 2014-2019 Siemens AG * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -14,17 +14,22 @@ */ #include +#include +#include +#include #include +#include + #include "soc/gpio.h" #include "lcd_panel.h" -#include "ptn3460.h" +# define MAX_HWI_NAME_LENGTH 20 /** \brief Reads GPIOs used for LCD panel encoding and returns the 4 bit value * @param no parameters * @return LCD panel type encoded in 4 bits */ -u8 get_lcd_panel_type(void) +static u8 get_lcd_panel_type(void) { u8 lcd_type_gpio; @@ -35,48 +40,134 @@ u8 get_lcd_panel_type(void) /* There is an inverter in this signals so we need to invert them as well */ return ((~lcd_type_gpio) & 0x0f); } - -/** \brief Set up LCD panel - * @param no parameters - * @return 0 on success otherwise error value +/** \brief This function checks which LCD panel type is used with the mainboard + * and provides the name of the matching EDID data set in CBFS. + * @param Pointer to the filename in CBFS where the EDID data is located + * @return CB_SUCCESS on success otherwise CB_ERR */ -int setup_lcd_panel(void) +static enum cb_err get_hwi_filename(char *hwi_block) { u8 lcd_type; - int status; - char blockname[33]; + enum cb_err ret = CB_SUCCESS; lcd_type = get_lcd_panel_type(); printk(BIOS_INFO, "LCD: Found panel type %d\n", lcd_type); switch (lcd_type) { case LCD_PANEL_TYPE_10_INCH: - strcpy(blockname, "hwinfo10.hex"); + strcpy(hwi_block, "hwinfo10.hex"); break; case LCD_PANEL_TYPE_12_INCH: - strcpy(blockname, "hwinfo12.hex"); + strcpy(hwi_block, "hwinfo12.hex"); break; case LCD_PANEL_TYPE_15_INCH: - strcpy(blockname, "hwinfo15.hex"); + strcpy(hwi_block, "hwinfo15.hex"); break; case LCD_PANEL_TYPE_19_INCH: - strcpy(blockname, "hwinfo19.hex"); + strcpy(hwi_block, "hwinfo19.hex"); break; case LCD_PANEL_TYPE_EDID: - strcpy(blockname, "hwinfo.hex"); + strcpy(hwi_block, "hwinfo.hex"); break; default: printk(BIOS_ERR, "LCD: No supported panel found.\n"); - return 1; + ret = CB_ERR; break; } - - /* Now that we have the panel type, set up the DP2LVDS converter */ - status = ptn3460_init(blockname); - if (status) - printk(BIOS_ERR, "LCD: Setup PTN with status 0x%x\n", status); - else - printk(BIOS_INFO, "LCD: Setup PTN with status 0x%x\n", status); - - return status; + return ret; +} + +/** \brief This function provides EDID data to the driver for DP2LVDS Bridge (PTN3460) + * @param edid_data pointer to EDID data in driver +*/ +enum cb_err mb_get_edid(uint8_t edid_data[0x80]) +{ + char hwi_block[MAX_HWI_NAME_LENGTH]; + + if (get_hwi_filename(hwi_block) != CB_SUCCESS) + return CB_ERR; + + if (hwilib_find_blocks(hwi_block) != CB_SUCCESS) { + printk(BIOS_ERR, "LCD: Info block \"%s\" not found!\n", hwi_block); + return CB_ERR; + } + + /* Get EDID data from hwinfo block */ + if (hwilib_get_field(Edid, edid_data, PTN_EDID_LEN) != PTN_EDID_LEN) { + printk(BIOS_ERR, "LCD: No EDID data available in %s\n", hwi_block); + return CB_ERR; + } + return CB_SUCCESS; +} + +/** \brief This function provides EDID block [0..6] to the driver for DP2LVDS Bridge (PTN3460) + * which has to be used. +*/ +uint8_t mb_select_edid_table(void) +{ + return 6; /* With this mainboard we use EDID block 6 for emulation in PTN3460. */ +} + +/** \brief Function to enable mainboard to adjust the config data of PTN3460. + * @param *cfg_ptr Pointer to the PTN config structure to modify. + * @return -1 on error; PTN_CFG_MODIFIED if data was modified and needs to be updated. +*/ +int mb_adjust_cfg(struct ptn_3460_config *cfg) +{ + char hwi_block[MAX_HWI_NAME_LENGTH]; + uint8_t disp_con = 0, color_depth = 0; + uint8_t hwid[4], tcu31_hwid[4] = {7, 9, 2, 0}; + + if (get_hwi_filename(hwi_block) != CB_SUCCESS) + return -1; + if (hwilib_find_blocks(hwi_block) != CB_SUCCESS) { + printk(BIOS_ERR, "LCD: Info block \"%s\" not found!\n", hwi_block); + return -1; + } + + if (hwilib_get_field(PF_DisplCon, &disp_con, sizeof(disp_con)) != sizeof(disp_con)) { + printk(BIOS_ERR, "LCD: Missing panel features from %s\n", hwi_block); + return -1; + } + if (hwilib_get_field(PF_Color_Depth, &color_depth, + sizeof(color_depth)) != sizeof(color_depth)) { + printk(BIOS_ERR, "LCD: Missing panel features from %s\n", hwi_block); + return -1; + } + /* Set up configuration data according to the hwinfo block we got. */ + cfg->dp_interface_ctrl = 0x00; + cfg->lvds_interface_ctrl1 = 0x00; + if (disp_con == PF_DISPLCON_LVDS_DUAL) { + /* Turn on dual LVDS lane and clock. */ + cfg->lvds_interface_ctrl1 |= 0x0b; + } + if (color_depth == PF_COLOR_DEPTH_6BIT) { + /* Use 18 bits per pixel. */ + cfg->lvds_interface_ctrl1 |= 0x20; + } + /* No clock spreading, 300 mV LVDS swing. */ + cfg->lvds_interface_ctrl2 = 0x03; + /* Swap LVDS even and odd lanes for HW-ID 7.9.2.0 only. */ + if (hwilib_get_field(HWID, hwid, sizeof(hwid)) == sizeof(hwid) && + !(memcmp(hwid, tcu31_hwid, sizeof(hwid)))) { + /* Swap LVDS even and odd lane. */ + cfg->lvds_interface_ctrl3 = 0x01; + } else { + /* no LVDS lane swap */ + cfg->lvds_interface_ctrl3 = 0x00; + } + /* Delay T2 (VDD to LVDS active) by 16 ms. */ + cfg->t2_delay = 1; + /* 500 ms from LVDS to backlight active. */ + cfg->t3_timing = 10; + /* 1 second re-power delay. */ + cfg->t12_timing = 20; + /* 150 ms backlight off to LVDS inactive. */ + cfg->t4_timing = 3; + /* Delay T5 (LVDS to VDD inactive) by 16 ms. */ + cfg->t5_delay = 1; + /* Enable backlight control. */ + cfg->backlight_ctrl = 0; + + return PTN_CFG_MODIFIED; } diff --git a/src/mainboard/siemens/mc_tcu3/lcd_panel.h b/src/mainboard/siemens/mc_tcu3/lcd_panel.h index a27cc52e4d..e119d7aaef 100644 --- a/src/mainboard/siemens/mc_tcu3/lcd_panel.h +++ b/src/mainboard/siemens/mc_tcu3/lcd_panel.h @@ -1,7 +1,7 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2014 Siemens AG + * Copyright (C) 2014-2019 Siemens AG * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -28,8 +28,4 @@ #define LCD_PANEL_TYPE_19_INCH 1 #define LCD_PANEL_TYPE_EDID 15 -u8 get_lcd_panel_type(void); -int setup_lcd_panel(void); - - #endif /* _LCD_PANEL_H_ */ diff --git a/src/mainboard/siemens/mc_tcu3/mainboard.c b/src/mainboard/siemens/mc_tcu3/mainboard.c index 955193fec2..7950572e99 100644 --- a/src/mainboard/siemens/mc_tcu3/mainboard.c +++ b/src/mainboard/siemens/mc_tcu3/mainboard.c @@ -23,8 +23,6 @@ #endif #include #include -#include "lcd_panel.h" - /** \brief This function will search for a MAC address which can be assigned * to a MACPHY. @@ -69,12 +67,10 @@ enum cb_err mainboard_get_mac_address(struct device *dev, uint8_t mac[6]) */ static void mainboard_enable(struct device *dev) { - } static void mainboard_final(void *chip_info) { - setup_lcd_panel(); } struct chip_operations mainboard_ops = { diff --git a/src/mainboard/siemens/mc_tcu3/ptn3460.c b/src/mainboard/siemens/mc_tcu3/ptn3460.c deleted file mode 100644 index 56f51f9647..0000000000 --- a/src/mainboard/siemens/mc_tcu3/ptn3460.c +++ /dev/null @@ -1,209 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2014-2019 Siemens AG - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include -#include -#include -#include -#include "soc/i2c.h" -#include "ptn3460.h" - -/** \brief This functions sets up the DP2LVDS-converter to be used with the - * appropriate lcd panel - * @param *hwi_block Filename in CBFS of the block to use as HW-Info - * @return 0 on success or error code - */ -int ptn3460_init(char *hwi_block) -{ - struct ptn_3460_config cfg; - int status; - uint8_t disp_con = 0, color_depth = 0; - uint8_t edid_data[0x80]; - uint8_t hwid[4], tcu31_hwid[4] = {7, 9, 2, 0}; - uint8_t i; - - if (!hwi_block || hwilib_find_blocks(hwi_block) != CB_SUCCESS) { - printk(BIOS_ERR, "LCD: Info block \"%s\" not found!\n", - hwi_block); - return 1; - } - - /* Get all needed information from hwinfo block */ - if (hwilib_get_field(Edid, edid_data, 0x80) != sizeof(edid_data)) { - printk(BIOS_ERR, "LCD: No EDID data available in %s\n", - hwi_block); - return 1; - } - if ((hwilib_get_field(PF_DisplCon, &disp_con, 1) != 1)) { - printk(BIOS_ERR, "LCD: Missing panel features from %s\n", - hwi_block); - return 1; - } - if (hwilib_get_field(PF_Color_Depth, &color_depth, 1) != 1) { - printk(BIOS_ERR, "LCD: Missing panel features from %s\n", - hwi_block); - return 1; - } - /* Here, all the desired information for setting up DP2LVDS converter*/ - /* are present. Inside the converter, table 6 will be used for */ - /* the timings. */ - if ((status = ptn3460_write_edid(6, edid_data)) != 0) - return status; - /* Select this table to be emulated */ - ptn_select_edid(6); - /* Read PTN configuration data */ - status = i2c_read_bytes(PTN_I2C_CONTROLLER, PTN_SLAVE_ADR, PTN_CONFIG_OFF, (u8 *) &cfg, - sizeof(struct ptn_3460_config)); - if (status) - return (PTN_BUS_ERROR | status); - - /* Set up configuration data according to the hwinfo blocks we get */ - cfg.dp_interface_ctrl = 0; - cfg.lvds_interface_ctrl1 = 0x00; - if (disp_con == PF_DISPLCON_LVDS_DUAL) - cfg.lvds_interface_ctrl1 |= 0x0b; /* Turn on dual LVDS lane and clock */ - if (color_depth == PF_COLOR_DEPTH_6BIT) - cfg.lvds_interface_ctrl1 |= 0x20; /* Use 18 bits per pixel */ - cfg.lvds_interface_ctrl2 = 0x03; /* no clock spreading, 300 mV LVDS swing */ - /* Swap LVDS even and odd lanes for HW-ID 7.9.2.0 only. */ - if (hwilib_get_field(HWID, hwid, sizeof(hwid)) == sizeof(hwid) && - !(memcmp(hwid, tcu31_hwid, sizeof(hwid)))) { - cfg.lvds_interface_ctrl3 = 0x01; /* swap LVDS even and odd */ - } else - cfg.lvds_interface_ctrl3 = 0x00; /* no LVDS signal swap */ - cfg.t2_delay = 1; /* Delay T2 (VDD to LVDS active) by 16 ms */ - cfg.t3_timing = 10; /* 500 ms from LVDS to backlight active */ - cfg.t12_timing = 20; /* 1 second re-power delay */ - cfg.t4_timing = 3; /* 150 ms backlight off to LVDS inactive */ - cfg.t5_delay = 1; /* Delay T5 (LVDS to VDD inactive) by 16 ms */ - cfg.backlight_ctrl = 0; /* Enable backlight control */ - - /* Write back configuration data to PTN3460 */ - for (i = 0; i < sizeof(struct ptn_3460_config); i++) { - status = i2c_writeb(PTN_I2C_CONTROLLER, PTN_SLAVE_ADR, PTN_CONFIG_OFF + i, - *(((uint8_t *) &cfg) + i)); - if (status) - return (PTN_BUS_ERROR | status); - } - - return PTN_NO_ERROR; -} - -/** \brief This functions reads one desired EDID data structure from PTN3460 - * @param edid_num Number of EDID that must be read (0..6) - * @param *data Pointer to a buffer where to store read data - * @return 0 on success or error code - */ -int ptn3460_read_edid(u8 edid_num, u8 *data) -{ - int status; - - if (edid_num > PTN_MAX_EDID_NUM) - return PTN_INVALID_EDID; - /* First enable access to the desired EDID table */ - status = i2c_writeb(PTN_I2C_CONTROLLER, PTN_SLAVE_ADR, PTN_CONFIG_OFF + 5, edid_num); - if (status) - return (PTN_BUS_ERROR | status); - - /* Now we can simply read back EDID-data */ - status = i2c_read_bytes(PTN_I2C_CONTROLLER, PTN_SLAVE_ADR, PTN_EDID_OFF, data, - PTN_EDID_LEN); - if (status) - return (PTN_BUS_ERROR | status); - else - return PTN_NO_ERROR; -} - -/** \brief This functions writes one EDID data structure to PTN3460 - * @param edid_num Number of EDID that must be written (0..6) - * @param *data Pointer to a buffer where data to write is stored in - * @return 0 on success or error code - */ -int ptn3460_write_edid(u8 edid_num, u8 *data) -{ - int status; - int i; - - if (edid_num > PTN_MAX_EDID_NUM) - return PTN_INVALID_EDID; - - /* First enable access to the desired EDID table */ - status = i2c_writeb(PTN_I2C_CONTROLLER, PTN_SLAVE_ADR, PTN_CONFIG_OFF + 5, edid_num); - if (status) - return (PTN_BUS_ERROR | status); - - /* Now we can simply write EDID-data to ptn3460 */ - for (i = 0; i < PTN_EDID_LEN; i++) { - status = i2c_writeb(PTN_I2C_CONTROLLER, PTN_SLAVE_ADR, PTN_EDID_OFF + i, - data[i]); - if (status) - return (PTN_BUS_ERROR | status); - } - return PTN_NO_ERROR; -} - -/** \brief This functions selects one of 7 EDID-tables inside PTN3460 - * which should be emulated on display port and turn emulation ON - * @param edid_num Number of EDID to emulate (0..6) - * @return 0 on success or error code - */ -int ptn_select_edid (u8 edid_num) -{ - int status; - u8 val; - - if (edid_num > PTN_MAX_EDID_NUM) - return PTN_INVALID_EDID; - /* Enable emulation of the desired EDID table */ - val = (edid_num << 1) | 1; - status = i2c_writeb(PTN_I2C_CONTROLLER, PTN_SLAVE_ADR, PTN_CONFIG_OFF + 4, val); - if (status) - return (PTN_BUS_ERROR | status); - else - return PTN_NO_ERROR; -} - -/** \brief This functions performs a flash operation which will write - * current configuration table (all the EDID-tables and the - * configuration space with a total amount of 1 KByte) - * to the internal flash of PTN3460 - * @param none - * @return 0 on success or error code - */ -int ptn3460_flash_config(void) -{ - int status, i; - struct ptn_3460_flash flash; - - flash.cmd = 0x01; /* perform erase and flash cycle */ - flash.magic = 0x7845; /* Magic number to protect flash operation */ - flash.trigger = 0x56; /* This value starts flash operation */ - - for (i = 0; i < sizeof(struct ptn_3460_flash); i++) { - status = i2c_writeb(PTN_I2C_CONTROLLER, PTN_SLAVE_ADR, PTN_FLASH_CFG_OFF+i, - *(((uint8_t *) &flash) + i)); - if (status) - return (PTN_BUS_ERROR | status); - } - if (status) { - return (PTN_BUS_ERROR | status); - } else { - /* To ensure the flash operation is finished, we have to wait 300 ms */ - mdelay(300); - return PTN_NO_ERROR; - } -} diff --git a/src/mainboard/siemens/mc_tcu3/ptn3460.h b/src/mainboard/siemens/mc_tcu3/ptn3460.h deleted file mode 100644 index 8dc002dc39..0000000000 --- a/src/mainboard/siemens/mc_tcu3/ptn3460.h +++ /dev/null @@ -1,72 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2014 Siemens AG - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef PTN3460_H_ -#define PTN3460_H_ - -#include "lcd_panel.h" - -#define PTN_SLAVE_ADR 0x20 -#define PTN_I2C_CONTROLLER 0 - -#define PTN_EDID_OFF 0x00 -#define PTN_EDID_LEN 0x80 -#define PTN_CONFIG_OFF 0x80 -#define PTN_CONFIG_LEN 0x19 -#define PTN_FLASH_CFG_OFF 0xE8 -#define PTN_FLASH_CFG_LEN 0x04 -#define PTN_MAX_EDID_NUM 6 - -/* Define some error codes that can be used */ -#define PTN_NO_ERROR 0x00000000 -#define PTN_BUS_ERROR 0x10000000 -#define PTN_INVALID_EDID 0x20000000 - -struct ptn_3460_config{ - u8 dp_interface_ctrl; /* DisplayPort interface control */ - u8 lvds_interface_ctrl1; /* LVDS interface control register 1 */ - u8 lvds_interface_ctrl2; /* LVDS interface control register 2 */ - u8 lvds_interface_ctrl3; /* LVDS interface control register 3 */ - u8 edid_rom_emulation; /* select which EDID-block is emulated */ - u8 edid_rom_access_ctrl; /* select which EDID block to map to 0..0x7F */ - u8 pwm_min[3]; /* smallest PWM frequency for back light */ - u8 pwm_max[3]; /* biggest PWM frequency for back light */ - u8 fast_link_ctrl; /* Fast link training control register */ - u8 pin_cfg_ctrl1; /* Pin configuration control register 1 */ - u8 pin_cfg_ctrl2; /* Pin configuration control register 2 */ - u8 pwm_default; /* Default PWM bit count in DPCD register */ - u16 pwm_value; /* Current PWM bit count in DPCD register */ - u8 pwm_default_freq; /* Default PWM frequency in DPCD register */ - u8 t3_timing; /* Panel T3 timing value */ - u8 t12_timing; /* Panel T12 timing value */ - u8 backlight_ctrl; /* Back light control register */ - u8 t2_delay; /* Panel T2 delay */ - u8 t4_timing; /* Panel T4 timing value */ - u8 t5_delay; /* Panel T5 delay */ -} __packed; - -struct ptn_3460_flash{ - u8 cmd; /* Flash command (erase or erase and flash) */ - u16 magic; /* Magic number needed by the flash algorithm */ - u8 trigger; /* Trigger for starting flash operation */ -} __packed; - - -int ptn3460_init(char *hwi_block); -int ptn3460_read_edid(u8 edid_num, u8 *data); -int ptn3460_write_edid(u8 edid_num, u8 *data); -int ptn_select_edid(u8 edid_num); -int ptn3460_flash_config(void); -#endif /* PTN3460_H_ */ From fee2fdecc2b6c260fcb6caf3348ee948a83cdbd7 Mon Sep 17 00:00:00 2001 From: Wisley Chen Date: Fri, 8 Nov 2019 09:56:54 +0800 Subject: [PATCH 0135/1242] /mb/google/hatch: add new memory config support 1. Add 16G 2666 2 bank group 2. Add 16G 3200 4 bank group BUG=b:142762387 TEST=boot with memory (KAAG165WA-BCT/H5ANAG6NCMR-XNC) Change-Id: I04810091ef2bf8ec1bd306ad141a70436638eac8 Signed-off-by: Wisley Chen Reviewed-on: https://review.coreboot.org/c/coreboot/+/36665 Tested-by: build bot (Jenkins) Reviewed-by: Paul Fagerburg --- .../google/hatch/spd/16G_2666_2bg.spd.hex | 32 +++++++++++++++++++ .../google/hatch/spd/16G_3200_4bg.spd.hex | 32 +++++++++++++++++++ 2 files changed, 64 insertions(+) create mode 100644 src/mainboard/google/hatch/spd/16G_2666_2bg.spd.hex create mode 100644 src/mainboard/google/hatch/spd/16G_3200_4bg.spd.hex diff --git a/src/mainboard/google/hatch/spd/16G_2666_2bg.spd.hex b/src/mainboard/google/hatch/spd/16G_2666_2bg.spd.hex new file mode 100644 index 0000000000..3b41882c32 --- /dev/null +++ b/src/mainboard/google/hatch/spd/16G_2666_2bg.spd.hex @@ -0,0 +1,32 @@ +23 11 0C 03 46 29 00 08 00 60 00 03 02 03 00 00 +00 00 06 0D F8 3F 00 00 6E 6E 6E 11 00 6E F0 0A +20 08 00 05 00 F0 2B 34 28 00 78 00 14 3C 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 16 36 0B 35 +16 36 0B 35 00 00 16 36 0B 35 16 36 0B 35 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 9C B5 00 00 00 00 E7 00 F7 4B +0F 11 02 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 DB 08 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 diff --git a/src/mainboard/google/hatch/spd/16G_3200_4bg.spd.hex b/src/mainboard/google/hatch/spd/16G_3200_4bg.spd.hex new file mode 100644 index 0000000000..ad044543f2 --- /dev/null +++ b/src/mainboard/google/hatch/spd/16G_3200_4bg.spd.hex @@ -0,0 +1,32 @@ +23 11 0C 03 85 21 91 08 00 60 00 03 01 03 00 00 +00 00 05 0D F8 FF 02 00 6E 6E 6E 11 00 6E F0 0A +20 08 00 05 00 A8 14 28 28 00 78 00 14 3C 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 16 36 0B 35 +16 36 0B 35 00 00 16 36 0B 35 16 36 0B 35 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 9C 00 00 00 00 00 E7 00 C0 6E +0F 01 1F 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 7D 21 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +80 AD 01 00 00 00 00 00 00 48 4D 41 41 31 47 53 +36 43 4D 52 36 4E 2D 58 4E 20 20 20 20 00 80 AD +FF 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 From df9cdcfc383ac38c2238fd6d640c9260028906f7 Mon Sep 17 00:00:00 2001 From: Arthur Heymans Date: Sat, 9 Nov 2019 06:50:20 +0100 Subject: [PATCH 0136/1242] arch/x86/car.ld: Rename suffix _start/_end This is more in line with how linker symbol for regions are defined. Change-Id: I0bd7ae59a27909ed0fd38e6f7193816cb57e76af Signed-off-by: Arthur Heymans Reviewed-on: https://review.coreboot.org/c/coreboot/+/36695 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin --- src/arch/x86/assembly_entry.S | 2 +- src/arch/x86/car.ld | 12 ++++++------ src/arch/x86/include/arch/symbols.h | 12 ++++++------ src/cpu/intel/car/core2/cache_as_ram.S | 2 +- src/cpu/intel/car/non-evict/cache_as_ram.S | 2 +- src/cpu/intel/car/p3/cache_as_ram.S | 2 +- src/cpu/intel/car/p4-netburst/cache_as_ram.S | 2 +- src/cpu/intel/car/romstage.c | 2 +- src/cpu/qemu-x86/cache_as_ram_bootblock.S | 2 +- src/drivers/usb/ehci_debug.c | 2 +- src/soc/intel/common/block/cpu/car/cache_as_ram.S | 2 +- src/soc/intel/quark/bootblock/esram_init.S | 2 +- src/soc/intel/quark/romstage/fsp_params.c | 2 +- 13 files changed, 23 insertions(+), 23 deletions(-) diff --git a/src/arch/x86/assembly_entry.S b/src/arch/x86/assembly_entry.S index c36dc1cb10..d9d6d4ecef 100644 --- a/src/arch/x86/assembly_entry.S +++ b/src/arch/x86/assembly_entry.S @@ -30,7 +30,7 @@ _start: call gdt_init /* reset stack pointer to CAR stack */ - mov $_car_stack_end, %esp + mov $_ecar_stack, %esp /* clear .bss section as it is not shared */ cld diff --git a/src/arch/x86/car.ld b/src/arch/x86/car.ld index 6ccbd8c236..74fc74b58e 100644 --- a/src/arch/x86/car.ld +++ b/src/arch/x86/car.ld @@ -37,9 +37,9 @@ * use CAR it can be reused. The chipset/SoC is expected to provide * the stack size. */ #if CONFIG(C_ENVIRONMENT_BOOTBLOCK) - _car_stack_start = .; + _car_stack = .; . += CONFIG_DCACHE_BSP_STACK_SIZE; - _car_stack_end = .; + _ecar_stack = .; #endif /* The pre-ram cbmem console as well as the timestamp region are fixed * in size. Therefore place them above the car global section so that @@ -59,10 +59,10 @@ TIMESTAMP(., 0x200) - _car_ehci_dbg_info_start = .; + _car_ehci_dbg_info = .; /* Reserve sizeof(struct ehci_dbg_info). */ . += 80; - _car_ehci_dbg_info_end = .; + _ecar_ehci_dbg_info = .; /* _bss and _ebss provide symbols to per-stage * variables that are not shared like the timestamp and the pre-ram @@ -87,8 +87,8 @@ _car_unallocated_start = .; #if !CONFIG(C_ENVIRONMENT_BOOTBLOCK) - _car_stack_start = .; - _car_stack_end = _car_region_end; + _car_stack = .; + _ecar_stack = _car_region_end; #endif _car_region_end = . + CONFIG_DCACHE_RAM_SIZE - (. - _car_region_start); } diff --git a/src/arch/x86/include/arch/symbols.h b/src/arch/x86/include/arch/symbols.h index f715e0a6d1..efe10fe524 100644 --- a/src/arch/x86/include/arch/symbols.h +++ b/src/arch/x86/include/arch/symbols.h @@ -27,15 +27,15 @@ extern char _car_region_end[]; * This is the stack area used for all stages that execute when cache-as-ram * is up. Area is not cleared in between stages. */ -extern char _car_stack_start[]; -extern char _car_stack_end[]; -#define _car_stack_size (_car_stack_end - _car_stack_start) +extern char _car_stack[]; +extern char _ecar_stack[]; +#define _car_stack_size (_ecar_stack - _car_stack) extern char _car_unallocated_start[]; -extern char _car_ehci_dbg_info_start[]; -extern char _car_ehci_dbg_info_end[]; +extern char _car_ehci_dbg_info[]; +extern char _ecar_ehci_dbg_info[]; #define _car_ehci_dbg_info_size \ - (_car_ehci_dbg_info_end - _car_ehci_dbg_info_start) + (_ecar_ehci_dbg_info - _car_ehci_dbg_info) #endif diff --git a/src/cpu/intel/car/core2/cache_as_ram.S b/src/cpu/intel/car/core2/cache_as_ram.S index a1bec12ede..0e0fa77bb0 100644 --- a/src/cpu/intel/car/core2/cache_as_ram.S +++ b/src/cpu/intel/car/core2/cache_as_ram.S @@ -173,7 +173,7 @@ addrsize_set_high: movl %eax, %cr0 /* Setup the stack. */ - mov $_car_stack_end, %esp + mov $_ecar_stack, %esp /* Need to align stack to 16 bytes at call instruction. Account for the pushes below. */ diff --git a/src/cpu/intel/car/non-evict/cache_as_ram.S b/src/cpu/intel/car/non-evict/cache_as_ram.S index 08ad195964..cd6972062c 100644 --- a/src/cpu/intel/car/non-evict/cache_as_ram.S +++ b/src/cpu/intel/car/non-evict/cache_as_ram.S @@ -215,7 +215,7 @@ end_microcode_update: movl %eax, %cr0 /* Setup the stack. */ - mov $_car_stack_end, %esp + mov $_ecar_stack, %esp /* Need to align stack to 16 bytes at call instruction. Account for the pushes below. */ diff --git a/src/cpu/intel/car/p3/cache_as_ram.S b/src/cpu/intel/car/p3/cache_as_ram.S index 33f0bfd2a3..a3487dbe34 100644 --- a/src/cpu/intel/car/p3/cache_as_ram.S +++ b/src/cpu/intel/car/p3/cache_as_ram.S @@ -161,7 +161,7 @@ addrsize_set_high: movl %eax, %cr0 /* Setup the stack. */ - mov $_car_stack_end, %esp + mov $_ecar_stack, %esp /* Need to align stack to 16 bytes at call instruction. Account for the pushes below. */ diff --git a/src/cpu/intel/car/p4-netburst/cache_as_ram.S b/src/cpu/intel/car/p4-netburst/cache_as_ram.S index 58e411dcc3..7815eb3235 100644 --- a/src/cpu/intel/car/p4-netburst/cache_as_ram.S +++ b/src/cpu/intel/car/p4-netburst/cache_as_ram.S @@ -376,7 +376,7 @@ fill_cache: rep stosl /* Setup the stack. */ - mov $_car_stack_end, %esp + mov $_ecar_stack, %esp /* Need to align stack to 16 bytes at call instruction. Account for the pushes below. */ diff --git a/src/cpu/intel/car/romstage.c b/src/cpu/intel/car/romstage.c index 547b1211df..1525233e39 100644 --- a/src/cpu/intel/car/romstage.c +++ b/src/cpu/intel/car/romstage.c @@ -46,7 +46,7 @@ static void romstage_main(unsigned long bist) printk(BIOS_DEBUG, "Romstage stack size limited to 0x%x!\n", size); - stack_base = (u32 *) (_car_stack_end - size); + stack_base = (u32 *) (_ecar_stack - size); for (i = 0; i < num_guards; i++) stack_base[i] = stack_guard; diff --git a/src/cpu/qemu-x86/cache_as_ram_bootblock.S b/src/cpu/qemu-x86/cache_as_ram_bootblock.S index f5678a1807..1fa0018dc8 100644 --- a/src/cpu/qemu-x86/cache_as_ram_bootblock.S +++ b/src/cpu/qemu-x86/cache_as_ram_bootblock.S @@ -34,7 +34,7 @@ cache_as_ram: post_code(0x21) - movl $_car_stack_end, %esp + movl $_ecar_stack, %esp /* Align the stack and keep aligned for call to bootblock_c_entry() */ and $0xfffffff0, %esp diff --git a/src/drivers/usb/ehci_debug.c b/src/drivers/usb/ehci_debug.c index ff237265eb..398f5db321 100644 --- a/src/drivers/usb/ehci_debug.c +++ b/src/drivers/usb/ehci_debug.c @@ -70,7 +70,7 @@ static inline struct ehci_debug_info *dbgp_ehci_info(void) /* The message likely does not show if we hit this. */ if (sizeof(*info) > _car_ehci_dbg_info_size) die("BUG: Increase ehci_dbg_info reserve in CAR"); - info = (void *)_car_ehci_dbg_info_start; + info = (void *)_car_ehci_dbg_info; } else { info = &glob_dbg_info; } diff --git a/src/soc/intel/common/block/cpu/car/cache_as_ram.S b/src/soc/intel/common/block/cpu/car/cache_as_ram.S index d5f5081c3c..471c18e407 100644 --- a/src/soc/intel/common/block/cpu/car/cache_as_ram.S +++ b/src/soc/intel/common/block/cpu/car/cache_as_ram.S @@ -170,7 +170,7 @@ car_init_done: post_code(0x29) /* Setup bootblock stack */ - mov $_car_stack_end, %esp + mov $_ecar_stack, %esp /* Need to align stack to 16 bytes at call instruction. Account for the two pushes below. */ diff --git a/src/soc/intel/quark/bootblock/esram_init.S b/src/soc/intel/quark/bootblock/esram_init.S index 13a4d63d3c..ca96ceb6e4 100644 --- a/src/soc/intel/quark/bootblock/esram_init.S +++ b/src/soc/intel/quark/bootblock/esram_init.S @@ -502,7 +502,7 @@ L44: */ /* Setup bootblock stack */ - movl $_car_stack_end, %esp + movl $_ecar_stack, %esp before_carstage: post_code(0x2b) diff --git a/src/soc/intel/quark/romstage/fsp_params.c b/src/soc/intel/quark/romstage/fsp_params.c index cd654d74de..681e126a13 100644 --- a/src/soc/intel/quark/romstage/fsp_params.c +++ b/src/soc/intel/quark/romstage/fsp_params.c @@ -118,7 +118,7 @@ void platform_fsp_memory_init_params_cb(FSPM_UPD *fspm_upd, uint32_t version) _car_unallocated_start); printk(BIOS_SPEW, "| coreboot data |\n"); printk(BIOS_SPEW, "+-------------------+ 0x%p\n", - _car_stack_end); + _ecar_stack); printk(BIOS_SPEW, "| coreboot stack |\n"); printk(BIOS_SPEW, "+-------------------+ 0x80000000 - ESRAM start\n\n"); From cd3c3167df7b00938f9a70933bdf2b9795655bdf Mon Sep 17 00:00:00 2001 From: Alexis Savery Date: Fri, 25 Oct 2019 16:14:49 -0700 Subject: [PATCH 0137/1242] mainboard/google/hatch: Create helios_diskswap variant Created helios_diskswap as a variant of helios (hatch variant). BUG=b:143378037 BRANCH=None TEST=none Change-Id: I6536b3908ec569e1ac42ea7c5be85701012ab177 Signed-off-by: Alexis Savery Reviewed-on: https://review.coreboot.org/c/coreboot/+/36447 Tested-by: build bot (Jenkins) Reviewed-by: Tim Wawrzynczak --- src/mainboard/google/hatch/Kconfig | 3 + src/mainboard/google/hatch/Kconfig.name | 7 + .../variants/helios_diskswap/overridetree.cb | 209 ++++++++++++++++++ 3 files changed, 219 insertions(+) create mode 100644 src/mainboard/google/hatch/variants/helios_diskswap/overridetree.cb diff --git a/src/mainboard/google/hatch/Kconfig b/src/mainboard/google/hatch/Kconfig index 8488762eef..6c0a94afe6 100644 --- a/src/mainboard/google/hatch/Kconfig +++ b/src/mainboard/google/hatch/Kconfig @@ -91,6 +91,7 @@ config MAINBOARD_PART_NUMBER default "Dratini" if BOARD_GOOGLE_DRATINI default "Hatch" if BOARD_GOOGLE_HATCH default "Helios" if BOARD_GOOGLE_HELIOS + default "Helios_Diskswap" if BOARD_GOOGLE_HELIOS_DISKSWAP default "Kindred" if BOARD_GOOGLE_KINDRED default "Kohaku" if BOARD_GOOGLE_KOHAKU default "Puff" if BOARD_GOOGLE_PUFF @@ -105,6 +106,7 @@ config MAX_CPUS config OVERRIDE_DEVICETREE string + default "variants/helios_diskswap/overridetree.cb" if BOARD_GOOGLE_HELIOS_DISKSWAP default "variants/$(CONFIG_VARIANT_DIR)/overridetree.cb" config TPM_TIS_ACPI_INTERRUPT @@ -117,6 +119,7 @@ config VARIANT_DIR default "dratini" if BOARD_GOOGLE_DRATINI default "hatch" if BOARD_GOOGLE_HATCH default "helios" if BOARD_GOOGLE_HELIOS + default "helios" if BOARD_GOOGLE_HELIOS_DISKSWAP default "kindred" if BOARD_GOOGLE_KINDRED default "kohaku" if BOARD_GOOGLE_KOHAKU default "puff" if BOARD_GOOGLE_PUFF diff --git a/src/mainboard/google/hatch/Kconfig.name b/src/mainboard/google/hatch/Kconfig.name index 2051e0f12a..ec12096269 100644 --- a/src/mainboard/google/hatch/Kconfig.name +++ b/src/mainboard/google/hatch/Kconfig.name @@ -38,3 +38,10 @@ config BOARD_GOOGLE_PUFF select BOARD_GOOGLE_BASEBOARD_HATCH select BOARD_ROMSIZE_KB_32768 select ROMSTAGE_SPD_SMBUS + +config BOARD_GOOGLE_HELIOS_DISKSWAP + bool "-> Helios_Diskswap" + select BOARD_GOOGLE_BASEBOARD_HATCH + select BOARD_ROMSIZE_KB_16384 + select CHROMEOS_DSM_CALIB + select DRIVERS_I2C_RT1011 diff --git a/src/mainboard/google/hatch/variants/helios_diskswap/overridetree.cb b/src/mainboard/google/hatch/variants/helios_diskswap/overridetree.cb new file mode 100644 index 0000000000..3bbf232a93 --- /dev/null +++ b/src/mainboard/google/hatch/variants/helios_diskswap/overridetree.cb @@ -0,0 +1,209 @@ +chip soc/intel/cannonlake + register "tdp_pl1_override" = "13" + register "tdp_pl2_override" = "64" + + register "SerialIoDevMode" = "{ + [PchSerialIoIndexI2C0] = PchSerialIoPci, + [PchSerialIoIndexI2C1] = PchSerialIoPci, + [PchSerialIoIndexI2C2] = PchSerialIoPci, + [PchSerialIoIndexI2C3] = PchSerialIoPci, + [PchSerialIoIndexI2C4] = PchSerialIoPci, + [PchSerialIoIndexI2C5] = PchSerialIoPci, + [PchSerialIoIndexSPI0] = PchSerialIoPci, + [PchSerialIoIndexSPI1] = PchSerialIoPci, + [PchSerialIoIndexSPI2] = PchSerialIoDisabled, + [PchSerialIoIndexUART0] = PchSerialIoSkipInit, + [PchSerialIoIndexUART1] = PchSerialIoDisabled, + [PchSerialIoIndexUART2] = PchSerialIoDisabled, + }" + + # Enable Root port 9(x2) for NVMe. + register "PcieRpEnable[8]" = "1" + register "PcieRpLtrEnable[8]" = "1" + # RP 9 uses CLK SRC 1 + register "PcieClkSrcUsage[1]" = "8" + # ClkReq-to-ClkSrc mapping for CLK SRC 1 + register "PcieClkSrcClkReq[1]" = "1" + + # Enable Root port 11(x2) for NVMe. + register "PcieRpEnable[10]" = "1" + register "PcieRpLtrEnable[10]" = "1" + # RP 11 uses CLK SRC 2 + register "PcieClkSrcUsage[2]" = "10" + # ClkReq-to-ClkSrc mapping for CLK SRC 2 + register "PcieClkSrcClkReq[2]" = "1" + + # No PCIe WiFi + register "PcieRpEnable[13]" = "0" + + # Intel Common SoC Config + #+-------------------+---------------------------+ + #| Field | Value | + #+-------------------+---------------------------+ + #| GSPI1 | FP MCU | + #| I2C0 | Trackpad | + #| I2C1 | Touchscreen | + #| I2C4 | Audio | + #+-------------------+---------------------------+ + register "common_soc_config" = "{ + .i2c[0] = { + .speed = I2C_SPEED_FAST, + .rise_time_ns = 50, + .fall_time_ns = 15, + .data_hold_time_ns = 330, + }, + .i2c[1] = { + .speed = I2C_SPEED_FAST, + .rise_time_ns = 60, + .fall_time_ns = 25, + }, + .i2c[3] = { + .speed = I2C_SPEED_FAST, + .rise_time_ns = 150, + .fall_time_ns = 150, + }, + .i2c[4] = { + .speed = I2C_SPEED_FAST, + .rise_time_ns = 120, + .fall_time_ns = 120, + }, + .gspi[0] = { + .speed_mhz = 1, + .early_init = 1, + }, + }" + + device domain 0 on + device pci 14.0 on + chip drivers/usb/acpi + device usb 0.0 on + chip drivers/usb/acpi + # No Type-A port + device usb 2.2 off end + end + chip drivers/usb/acpi + # No Type-A Port + device usb 2.3 off end + end + chip drivers/usb/acpi + # No WWAN + device usb 2.5 off end + end + chip drivers/usb/acpi + # No WWAN + device usb 3.4 off end + end + end + end + end + + # Native SD Card interface unused + device pci 14.5 off end + + device pci 15.0 on + chip drivers/i2c/generic + register "hid" = ""ELAN0000"" + register "desc" = ""ELAN Touchpad"" + register "irq" = "ACPI_IRQ_WAKE_EDGE_LOW(GPP_A21_IRQ)" + register "wake" = "GPE0_DW0_21" + device i2c 15 on end + end + end + + device pci 15.1 on + chip drivers/i2c/hid + register "generic.hid" = ""GDIX0000"" + register "generic.desc" = ""Goodix Touchscreen"" + register "generic.irq" = + "ACPI_IRQ_EDGE_LOW(GPP_D16_IRQ)" + register "generic.probed" = "1" + register "generic.reset_gpio" = + "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D15)" + register "generic.reset_delay_ms" = "500" + register "generic.reset_off_delay_ms" = "1" + register "generic.enable_gpio" = + "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D9)" + register "generic.enable_delay_ms" = "10" + register "generic.enable_off_delay_ms" = "1" + register "generic.has_power_resource" = "1" + register "hid_desc_reg_offset" = "0x01" + device i2c 5d on end + end + chip drivers/generic/gpio_keys + register "name" = ""PENH"" + register "gpio" = "ACPI_GPIO_IRQ_EDGE_BOTH(GPP_A8)" + register "key.wake" = "GPE0_DW0_08" + register "key.wakeup_event_action" = "EV_ACT_ASSERTED" + register "key.dev_name" = ""EJCT"" + register "key.linux_code" = "SW_PEN_INSERTED" + register "key.linux_input_type" = "EV_SW" + register "key.label" = ""pen_eject"" + device generic 0 on end + end + end # I2C 1 + + # I2C #2 unused + device pci 15.2 off end + + # I2C #3 unused + device pci 15.3 off end + + device pci 19.0 on + chip drivers/i2c/generic + register "hid" = ""10EC5682"" + register "name" = ""RT58"" + register "desc" = ""Realtek RT5682"" + register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_BOTH(GPP_H0)" + register "property_count" = "1" + # Set the jd_src to RT5668_JD1 for jack detection + register "property_list[0].type" = "ACPI_DP_TYPE_INTEGER" + register "property_list[0].name" = ""realtek,jd-src"" + register "property_list[0].integer" = "1" + device i2c 1a on end + end + chip drivers/i2c/generic + register "hid" = ""10EC1011"" + register "desc" = ""RT1011 Tweeter Left Speaker Amp"" + register "uid" = "0" + register "name" = ""TL"" + device i2c 38 on end + end + chip drivers/i2c/generic + register "hid" = ""10EC1011"" + register "desc" = ""RT1011 Tweeter Right Speaker Amp"" + register "uid" = "1" + register "name" = ""TR"" + device i2c 39 on end + end + chip drivers/i2c/generic + register "hid" = ""10EC1011"" + register "desc" = ""RT1011 Woofer Left Speaker Amp"" + register "uid" = "2" + register "name" = ""WL"" + device i2c 3a on end + end + chip drivers/i2c/generic + register "hid" = ""10EC1011"" + register "desc" = ""RT1011 Woofer Right Speaker Amp"" + register "uid" = "3" + register "name" = ""WR"" + device i2c 3b on end + end + end #I2C #4 + + device pci 1d.0 on end # PCI Express Port 9 (X2 NVMe) + device pci 1d.2 on end # PCI Express Port 11 (X2 NVMe) + + device pci 1e.3 on + chip drivers/spi/acpi + register "name" = ""CRFP"" + register "hid" = "ACPI_DT_NAMESPACE_HID" + register "uid" = "1" + register "compat_string" = ""google,cros-ec-spi"" + register "irq" = "ACPI_IRQ_WAKE_LEVEL_LOW(GPP_A23_IRQ)" + register "wake" = "GPE0_DW0_23" + device spi 1 on end + end # FPMCU + end # GSPI #1 + end +end From b6768370d1e15c6516faee6aad8371747458d3b7 Mon Sep 17 00:00:00 2001 From: Arthur Heymans Date: Mon, 11 Nov 2019 12:23:19 +0100 Subject: [PATCH 0138/1242] soc/intel/icelake: Remove FSP-T option in Kconfig MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This code lacks the temp_ram_init_params sybols so the FSP-T option fails to build. Change-Id: I2b6278bd64a3579ed3460af39ea244c7dfd51da4 Signed-off-by: Arthur Heymans Reviewed-on: https://review.coreboot.org/c/coreboot/+/36719 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber Reviewed-by: Michael Niewöhner --- src/soc/intel/icelake/Kconfig | 28 ++-------------------------- 1 file changed, 2 insertions(+), 26 deletions(-) diff --git a/src/soc/intel/icelake/Kconfig b/src/soc/intel/icelake/Kconfig index 334dfbec64..418c3171bd 100644 --- a/src/soc/intel/icelake/Kconfig +++ b/src/soc/intel/icelake/Kconfig @@ -50,6 +50,8 @@ config CPU_SPECIFIC_OPTIONS select SOC_INTEL_COMMON_BLOCK_SMM_IO_TRAP select SOC_INTEL_COMMON_PCH_BASE select SOC_INTEL_COMMON_RESET + select SOC_INTEL_COMMON_BLOCK_CAR + select INTEL_CAR_NEM_ENHANCED select SSE2 select SUPPORT_CPU_UCODE_IN_CBFS select TSC_MONOTONIC_TIMER @@ -174,32 +176,6 @@ config CBFS_SIZE hex default 0x200000 -choice - prompt "Cache-as-ram implementation" - default USE_ICELAKE_CAR_NEM_ENHANCED - help - This option allows you to select how cache-as-ram (CAR) is set up. - -config USE_ICELAKE_CAR_NEM_ENHANCED - bool "Enhanced Non-evict mode" - select SOC_INTEL_COMMON_BLOCK_CAR - select INTEL_CAR_NEM_ENHANCED - help - A current limitation of NEM (Non-Evict mode) is that code and data - sizes are derived from the requirement to not write out any modified - cache line. With NEM, if there is no physical memory behind the - cached area, the modified data will be lost and NEM results will be - inconsistent. ENHANCED NEM guarantees that modified data is always - kept in cache while clean data is replaced. - -config USE_ICELAKE_FSP_CAR - bool "Use FSP CAR" - select FSP_CAR - help - Use FSP APIs to initialize and tear down the Cache-As-Ram. - -endchoice - config FSP_HEADER_PATH string "Location of FSP headers" default "src/vendorcode/intel/fsp/fsp2_0/icelake/" From c6872f5524c70087d83d97f45bfbe55f1989f2d6 Mon Sep 17 00:00:00 2001 From: Arthur Heymans Date: Mon, 11 Nov 2019 12:29:56 +0100 Subject: [PATCH 0139/1242] soc/intel/tigerlake: Remove FSP-T option in Kconfig MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This code lacks the temp_ram_init_params sybols so the FSP-T option so it would fail to build. Change-Id: Ie7d75943d89a964d0189f921fc433e4b9adfb0c5 Signed-off-by: Arthur Heymans Reviewed-on: https://review.coreboot.org/c/coreboot/+/36720 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber Reviewed-by: Michael Niewöhner --- src/soc/intel/tigerlake/Kconfig | 28 ++-------------------------- 1 file changed, 2 insertions(+), 26 deletions(-) diff --git a/src/soc/intel/tigerlake/Kconfig b/src/soc/intel/tigerlake/Kconfig index c0fb7080e8..2824e52558 100644 --- a/src/soc/intel/tigerlake/Kconfig +++ b/src/soc/intel/tigerlake/Kconfig @@ -50,6 +50,8 @@ config CPU_SPECIFIC_OPTIONS select SOC_INTEL_COMMON_BLOCK_SMM_IO_TRAP select SOC_INTEL_COMMON_PCH_BASE select SOC_INTEL_COMMON_RESET + select SOC_INTEL_COMMON_BLOCK_CAR + select INTEL_CAR_NEM_ENHANCED select SSE2 select SUPPORT_CPU_UCODE_IN_CBFS select TSC_MONOTONIC_TIMER @@ -174,32 +176,6 @@ config CBFS_SIZE hex default 0x200000 -choice - prompt "Cache-as-ram implementation" - default USE_TIGERLAKE_CAR_NEM_ENHANCED - help - This option allows you to select how cache-as-ram (CAR) is set up. - -config USE_TIGERLAKE_CAR_NEM_ENHANCED - bool "Enhanced Non-evict mode" - select SOC_INTEL_COMMON_BLOCK_CAR - select INTEL_CAR_NEM_ENHANCED - help - A current limitation of NEM (Non-Evict mode) is that code and data - sizes are derived from the requirement to not write out any modified - cache line. With NEM, if there is no physical memory behind the - cached area, the modified data will be lost and NEM results will be - inconsistent. ENHANCED NEM guarantees that modified data is always - kept in cache while clean data is replaced. - -config USE_TIGERLAKE_FSP_CAR - bool "Use FSP CAR" - select FSP_CAR - help - Use FSP APIs to initialize and tear down the Cache-As-Ram. - -endchoice - config FSP_HEADER_PATH string "Location of FSP headers" default "src/vendorcode/intel/fsp/fsp2_0/tigerlake/" From 87c52809b2b6208ba51fea3ec379fdb6bacf250f Mon Sep 17 00:00:00 2001 From: Wim Vervoorn Date: Tue, 12 Nov 2019 11:15:23 +0100 Subject: [PATCH 0140/1242] lib/bootmem: Correct error message bootmem_allocate_buffer() displayed "unitialized", this is changed to "uninitialized". BUG=N/A TEST=build Change-Id: I84ae689ddb24f3e3d2387735faf3850e6bd6dfa9 Signed-off-by: Wim Vervoorn Reviewed-on: https://review.coreboot.org/c/coreboot/+/36772 Tested-by: build bot (Jenkins) Reviewed-by: Frans Hendriks Reviewed-by: Aaron Durbin --- src/lib/bootmem.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/lib/bootmem.c b/src/lib/bootmem.c index 45f7fe261d..8ca3bbd3f6 100644 --- a/src/lib/bootmem.c +++ b/src/lib/bootmem.c @@ -238,7 +238,7 @@ void *bootmem_allocate_buffer(size_t size) resource_t end; if (!bootmem_is_initialized()) { - printk(BIOS_ERR, "%s: lib unitialized!\n", __func__); + printk(BIOS_ERR, "%s: lib uninitialized!\n", __func__); return NULL; } From 799184397a06966403b9b2f3f5b53dba27eb272a Mon Sep 17 00:00:00 2001 From: Kane Chen Date: Fri, 8 Nov 2019 15:52:29 +0800 Subject: [PATCH 0141/1242] mb/google/hatch/variants/helios: Fix leakage voltage problem on touchscreen Set GPP_C4 default to low to fix leakage voltage problem on touchscreen during power on. BUG=b:142368161 BRANCH=Master TEST=emerge-hatch coreboot chromeos-ec chromeos-bootimage Flash FW to DUT, and make sure touchscreen works. Signed-off-by: Kane Chen Change-Id: Ie9197192c9d6dfb30c10559990c6010b1b2d3a45 Reviewed-on: https://review.coreboot.org/c/coreboot/+/36670 Reviewed-by: Tim Wawrzynczak Reviewed-by: Shelley Chen Reviewed-by: Subrata Banik Tested-by: build bot (Jenkins) --- src/mainboard/google/hatch/variants/helios/gpio.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/src/mainboard/google/hatch/variants/helios/gpio.c b/src/mainboard/google/hatch/variants/helios/gpio.c index bebcf32662..85eb3fc156 100644 --- a/src/mainboard/google/hatch/variants/helios/gpio.c +++ b/src/mainboard/google/hatch/variants/helios/gpio.c @@ -33,6 +33,8 @@ static const struct pad_config gpio_table[] = { PAD_NC(GPP_B19, NONE), /* C1 : SMBDATA ==> NC */ PAD_NC(GPP_C1, NONE), + /* C4 : TOUCHSCREEN_DIS_L */ + PAD_CFG_GPO(GPP_C4, 0, DEEP), /* C6 : GPP_C6 ==> NC */ PAD_NC(GPP_C6, NONE), /* C7 : GPP_C7 ==> NC */ From ead8a07cee63277da683e42ca820e1e853a3de17 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ky=C3=B6sti=20M=C3=A4lkki?= Date: Fri, 16 Aug 2019 08:05:52 +0300 Subject: [PATCH 0142/1242] intel/82801dx,ix: Rename SMM_ASEG functions MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Static declarations for use with SMM_ASEG conflict those declared globally for use with SMM_TSEG. Change-Id: I8d2984cd8fe6208417b2eda0c10da8fc7bb76cf1 Signed-off-by: Kyösti Mälkki Reviewed-on: https://review.coreboot.org/c/coreboot/+/35892 Reviewed-by: Arthur Heymans Tested-by: build bot (Jenkins) --- src/southbridge/intel/i82801dx/smi.c | 8 ++++---- src/southbridge/intel/i82801ix/smi.c | 8 ++++---- 2 files changed, 8 insertions(+), 8 deletions(-) diff --git a/src/southbridge/intel/i82801dx/smi.c b/src/southbridge/intel/i82801dx/smi.c index 521b98db04..dc53220fc1 100644 --- a/src/southbridge/intel/i82801dx/smi.c +++ b/src/southbridge/intel/i82801dx/smi.c @@ -235,7 +235,7 @@ static void smi_set_eos(void) extern uint8_t smm_relocation_start, smm_relocation_end; static void *default_smm_area = NULL; -static void smm_relocate(void) +static void aseg_smm_relocate(void) { u32 smi_en; u16 pm1_en; @@ -318,7 +318,7 @@ static void smm_relocate(void) outb(0x00, 0xb2); } -static void smm_install(void) +static void aseg_smm_install(void) { /* copy the real SMM handler */ memcpy((void *)0xa0000, _binary_smm_start, @@ -329,10 +329,10 @@ static void smm_install(void) void smm_init(void) { /* Put SMM code to 0xa0000 */ - smm_install(); + aseg_smm_install(); /* Put relocation code to 0x38000 and relocate SMBASE */ - smm_relocate(); + aseg_smm_relocate(); /* We're done. Make sure SMIs can happen! */ smi_set_eos(); diff --git a/src/southbridge/intel/i82801ix/smi.c b/src/southbridge/intel/i82801ix/smi.c index 0a80dd2ccf..5f73f411dc 100644 --- a/src/southbridge/intel/i82801ix/smi.c +++ b/src/southbridge/intel/i82801ix/smi.c @@ -45,7 +45,7 @@ static u16 pmbase = DEFAULT_PMBASE; extern uint8_t smm_relocation_start, smm_relocation_end; static void *default_smm_area = NULL; -static void smm_relocate(void) +static void aseg_smm_relocate(void) { u32 smi_en; u16 pm1_en; @@ -126,7 +126,7 @@ static void smm_relocate(void) static int smm_handler_copied = 0; -static void smm_install(void) +static void aseg_smm_install(void) { /* The first CPU running this gets to copy the SMM handler. But not all * of them. @@ -158,10 +158,10 @@ static void smm_install(void) void smm_init(void) { /* Put SMM code to 0xa0000 */ - smm_install(); + aseg_smm_install(); /* Put relocation code to 0x38000 and relocate SMBASE */ - smm_relocate(); + aseg_smm_relocate(); /* We're done. Make sure SMIs can happen! */ smi_set_eos(); From 0d92271d2cfcb98712b9e0a0c7c295bbe929b4ab Mon Sep 17 00:00:00 2001 From: Peichao Wang Date: Tue, 12 Nov 2019 08:36:53 +0800 Subject: [PATCH 0143/1242] spi: Add Winbond W25Q128JW_DTR SPI ROM support BUG=b:144297264 TEST=Boot with W25Q128JW_DTR and check MRC data save/restore works. Signed-off-by: Peichao Wang Change-Id: Ica6344556e5de94555b95dd7c6df5600614811e2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/36762 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan --- src/drivers/spi/winbond.c | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/src/drivers/spi/winbond.c b/src/drivers/spi/winbond.c index fa9140ec01..9e451171e5 100644 --- a/src/drivers/spi/winbond.c +++ b/src/drivers/spi/winbond.c @@ -261,6 +261,17 @@ static const struct winbond_spi_flash_params winbond_spi_flash_table[] = { .protection_granularity_shift = 18, .bp_bits = 3, }, + { + .id = 0x8018, + .l2_page_size_shift = 8, + .pages_per_sector_shift = 4, + .sectors_per_block_shift = 4, + .nr_blocks_shift = 8, + .name = "W25Q128JW", + .dual_spi = 1, + .protection_granularity_shift = 18, + .bp_bits = 3, + }, { .id = 0x4019, .l2_page_size_shift = 8, From b236352281405c3a6860b51af8acfd2e78c45e78 Mon Sep 17 00:00:00 2001 From: Arthur Heymans Date: Mon, 11 Nov 2019 18:40:50 +0100 Subject: [PATCH 0144/1242] sb/intel/i82801gx: Add a function to set up BAR This removes some of the sb code in the nb. Change-Id: I2ab894be93f210220fa55ddd10cd48889f308e5b Signed-off-by: Arthur Heymans Reviewed-on: https://review.coreboot.org/c/coreboot/+/36753 Tested-by: build bot (Jenkins) Reviewed-by: HAOUAS Elyes --- src/northbridge/intel/i945/early_init.c | 5 +---- src/northbridge/intel/pineview/early_init.c | 8 ++------ src/southbridge/intel/i82801gx/bootblock_gcc.c | 4 +--- src/southbridge/intel/i82801gx/early_init.c | 12 ++++++++++++ src/southbridge/intel/i82801gx/i82801gx.h | 1 + 5 files changed, 17 insertions(+), 13 deletions(-) diff --git a/src/northbridge/intel/i945/early_init.c b/src/northbridge/intel/i945/early_init.c index ee10fdccb6..a5bfe6f6a9 100644 --- a/src/northbridge/intel/i945/early_init.c +++ b/src/northbridge/intel/i945/early_init.c @@ -159,11 +159,8 @@ static void i945_setup_bars(void) /* Setting up Southbridge. In the northbridge code. */ printk(BIOS_DEBUG, "Setting up static southbridge registers..."); - pci_write_config32(PCI_DEV(0, 0x1f, 0), PMBASE, DEFAULT_PMBASE | 1); - pci_write_config8(PCI_DEV(0, 0x1f, 0), ACPI_CNTL, ACPI_EN); + i82801gx_setup_bars(); - pci_write_config32(PCI_DEV(0, 0x1f, 0), GPIOBASE, DEFAULT_GPIOBASE | 1); - pci_write_config8(PCI_DEV(0, 0x1f, 0), GPIO_CNTL, GPIO_EN); setup_pch_gpios(&mainboard_gpio_map); printk(BIOS_DEBUG, " done.\n"); diff --git a/src/northbridge/intel/pineview/early_init.c b/src/northbridge/intel/pineview/early_init.c index 1638f0e15a..3a9df510b7 100644 --- a/src/northbridge/intel/pineview/early_init.c +++ b/src/northbridge/intel/pineview/early_init.c @@ -158,12 +158,8 @@ static void pineview_setup_bars(void) { /* Setting up Southbridge. In the northbridge code. */ printk(BIOS_DEBUG, "Setting up static southbridge registers..."); - pci_write_config32(LPC, RCBA, (uintptr_t)DEFAULT_RCBA | 1); - pci_write_config32(LPC, PMBASE, DEFAULT_PMBASE | 1); - pci_write_config8(LPC, 0x44 /* ACPI_CNTL */, 0x80); /* Enable ACPI */ - pci_write_config32(LPC, GPIOBASE, DEFAULT_GPIOBASE | 1); - pci_write_config8(LPC, 0x4c /* GC */, 0x10); /* Enable GPIOs */ - pci_write_config32(LPC, 0x88, 0x007c0291); + + i82801gx_setup_bars(); pci_write_config32(PCI_DEV(0, 0x1e, 0), 0x1b, 0x20); printk(BIOS_DEBUG, " done.\n"); diff --git a/src/southbridge/intel/i82801gx/bootblock_gcc.c b/src/southbridge/intel/i82801gx/bootblock_gcc.c index 063a461e43..4c464ff920 100644 --- a/src/southbridge/intel/i82801gx/bootblock_gcc.c +++ b/src/southbridge/intel/i82801gx/bootblock_gcc.c @@ -32,9 +32,7 @@ void bootblock_early_southbridge_init(void) { enable_spi_prefetch(); - /* Enable RCBA */ - pci_devfn_t lpc_dev = PCI_DEV(0, 0x1f, 0); - pci_write_config32(lpc_dev, RCBA, (uintptr_t)DEFAULT_RCBA | 1); + i82801gx_setup_bars(); /* Enable upper 128bytes of CMOS */ RCBA32(0x3400) = (1 << 2); diff --git a/src/southbridge/intel/i82801gx/early_init.c b/src/southbridge/intel/i82801gx/early_init.c index 533aaefe14..7f5f442333 100644 --- a/src/southbridge/intel/i82801gx/early_init.c +++ b/src/southbridge/intel/i82801gx/early_init.c @@ -11,6 +11,7 @@ * GNU General Public License for more details. */ +#include #include #include "i82801gx.h" #include "chip.h" @@ -50,3 +51,14 @@ void i82801gx_lpc_setup(void) pci_write_config32(d31f0, GEN3_DEC, config->gen3_dec); pci_write_config32(d31f0, GEN4_DEC, config->gen4_dec); } + +void i82801gx_setup_bars(void) +{ + const pci_devfn_t d31f0 = PCI_DEV(0, 0x1f, 0); + pci_write_config32(d31f0, RCBA, (uint32_t)DEFAULT_RCBA | 1); + pci_write_config32(d31f0, PMBASE, DEFAULT_PMBASE | 1); + pci_write_config8(d31f0, ACPI_CNTL, ACPI_EN); + + pci_write_config32(d31f0, GPIOBASE, DEFAULT_GPIOBASE | 1); + pci_write_config8(d31f0, GPIO_CNTL, GPIO_EN); +} diff --git a/src/southbridge/intel/i82801gx/i82801gx.h b/src/southbridge/intel/i82801gx/i82801gx.h index 259fb49f54..9eea262997 100644 --- a/src/southbridge/intel/i82801gx/i82801gx.h +++ b/src/southbridge/intel/i82801gx/i82801gx.h @@ -41,6 +41,7 @@ void i82801gx_enable(struct device *dev); void enable_smbus(void); void i82801gx_lpc_setup(void); +void i82801gx_setup_bars(void); #if ENV_ROMSTAGE int smbus_read_byte(unsigned int device, unsigned int address); From dc972e17c70a7ca0ffe5e5ed1613838d48fe72a0 Mon Sep 17 00:00:00 2001 From: Arthur Heymans Date: Tue, 12 Nov 2019 08:35:05 +0100 Subject: [PATCH 0145/1242] nb/intel/x4x.h: Include stdint.h The structs and function definition in that header require it. Change-Id: I3466ff1a28459d0285e27d368314faf747e2eac1 Signed-off-by: Arthur Heymans Reviewed-on: https://review.coreboot.org/c/coreboot/+/36769 Tested-by: build bot (Jenkins) Reviewed-by: HAOUAS Elyes --- src/northbridge/intel/x4x/x4x.h | 1 + 1 file changed, 1 insertion(+) diff --git a/src/northbridge/intel/x4x/x4x.h b/src/northbridge/intel/x4x/x4x.h index 76d94c6c17..76e82d9494 100644 --- a/src/northbridge/intel/x4x/x4x.h +++ b/src/northbridge/intel/x4x/x4x.h @@ -18,6 +18,7 @@ #ifndef __NORTHBRIDGE_INTEL_X4X_H__ #define __NORTHBRIDGE_INTEL_X4X_H__ +#include #include "iomap.h" /* From 87074f904219744291f4fd56e0241d40f2dd583a Mon Sep 17 00:00:00 2001 From: Arthur Heymans Date: Mon, 11 Nov 2019 19:58:26 +0100 Subject: [PATCH 0146/1242] sb/intel/i82801jx: Enable upper 128bytes of CMOS The normal romcc bootblock uses this. Change-Id: I60f735f703a9208911f5cc8a81930535e574644d Signed-off-by: Arthur Heymans Reviewed-on: https://review.coreboot.org/c/coreboot/+/36755 Reviewed-by: Patrick Georgi Tested-by: build bot (Jenkins) --- src/southbridge/intel/i82801jx/bootblock.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/src/southbridge/intel/i82801jx/bootblock.c b/src/southbridge/intel/i82801jx/bootblock.c index fb2d5337b3..01faef34af 100644 --- a/src/southbridge/intel/i82801jx/bootblock.c +++ b/src/southbridge/intel/i82801jx/bootblock.c @@ -36,4 +36,7 @@ static void bootblock_southbridge_init(void) /* Enable RCBA */ pci_write_config32(PCI_DEV(0, 0x1f, 0), RCBA, (uintptr_t)DEFAULT_RCBA | 1); + + /* Enable upper 128bytes of CMOS. */ + RCBA32(0x3400) = (1 << 2); } From a2d123ea9872ff074c32272e7020553e5647ac64 Mon Sep 17 00:00:00 2001 From: Julius Werner Date: Tue, 12 Nov 2019 15:43:12 -0800 Subject: [PATCH 0147/1242] nvidia/tegra210: Enable RETURN_FROM_VERSTAGE to free up space All stages on this board are very close to the limit, so enable RETURN_FROM_VERSTAGE so that we can overlap verstage and romstage to use the available SRAM more effectively. (Coincidentally, this also reduces verstage size quite a bit... maybe we should consider just making this the default at some point, there are really no downsides.) Change-Id: I2b91fd13d147f964bcbd7b2850f8a0931ea060df Signed-off-by: Julius Werner Reviewed-on: https://review.coreboot.org/c/coreboot/+/36800 Tested-by: build bot (Jenkins) Reviewed-by: Arthur Heymans Reviewed-by: Aaron Durbin Reviewed-by: Patrick Georgi --- src/soc/nvidia/tegra210/Kconfig | 1 + src/soc/nvidia/tegra210/include/soc/memlayout.ld | 5 ++--- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/src/soc/nvidia/tegra210/Kconfig b/src/soc/nvidia/tegra210/Kconfig index 0e1efd7050..780fa18744 100644 --- a/src/soc/nvidia/tegra210/Kconfig +++ b/src/soc/nvidia/tegra210/Kconfig @@ -16,6 +16,7 @@ if SOC_NVIDIA_TEGRA210 config VBOOT select VBOOT_STARTS_IN_BOOTBLOCK select VBOOT_SEPARATE_VERSTAGE + select VBOOT_RETURN_FROM_VERSTAGE select VBOOT_MUST_REQUEST_DISPLAY config MAINBOARD_DO_DSI_INIT diff --git a/src/soc/nvidia/tegra210/include/soc/memlayout.ld b/src/soc/nvidia/tegra210/include/soc/memlayout.ld index 6d74ab928f..1134da6111 100644 --- a/src/soc/nvidia/tegra210/include/soc/memlayout.ld +++ b/src/soc/nvidia/tegra210/include/soc/memlayout.ld @@ -38,9 +38,8 @@ SECTIONS STACK(0x4000C400, 3K) #endif TIMESTAMP(0x4000D000, 2K) - BOOTBLOCK(0x4000D800, 30K) - VERSTAGE(0x40015000, 68k) - ROMSTAGE(0x40026000, 104K) + BOOTBLOCK(0x4000D800, 42K) + OVERLAP_VERSTAGE_ROMSTAGE(0x40018000, 160K) SRAM_END(0x40040000) DRAM_START(0x80000000) From a7fb23081cb03f85de0bd80944089b82af737e3d Mon Sep 17 00:00:00 2001 From: Andrey Petrov Date: Thu, 7 Nov 2019 09:48:41 -0800 Subject: [PATCH 0148/1242] arch/x86: Correctly determine number of enabled cores Instead of using MAX of (cores_enabled, MAX_CPUS), use MIN which is correct. TEST=tested with dmidecode Change-Id: Id0935f48e73c037bb7c0e1cf36f94d98a40a499c Signed-off-by: Andrey Petrov Reviewed-on: https://review.coreboot.org/c/coreboot/+/36662 Tested-by: build bot (Jenkins) Reviewed-by: David Hendricks Reviewed-by: Philipp Deppenwiese Reviewed-by: Nico Huber Reviewed-by: Arthur Heymans --- src/arch/x86/smbios.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/arch/x86/smbios.c b/src/arch/x86/smbios.c index 261888fc7f..725d808d56 100644 --- a/src/arch/x86/smbios.c +++ b/src/arch/x86/smbios.c @@ -659,7 +659,7 @@ static int smbios_write_type4(unsigned long *current, int handle) t->processor_type = 3; /* System Processor */ t->core_count = (res.ebx >> 16) & 0xff; /* Assume we enable all the cores always, capped only by MAX_CPUS */ - t->core_enabled = MAX(t->core_count, CONFIG_MAX_CPUS); + t->core_enabled = MIN(t->core_count, CONFIG_MAX_CPUS); t->l1_cache_handle = 0xffff; t->l2_cache_handle = 0xffff; t->l3_cache_handle = 0xffff; From 7630803b85c63fce6e90b3f95e58e8eb7369a912 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ky=C3=B6sti=20M=C3=A4lkki?= Date: Wed, 9 Oct 2019 10:26:32 +0300 Subject: [PATCH 0149/1242] sb/intel: Remove ENABLE_ACPI_MODE_IN_COREBOOT MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Change-Id: Ic807f4b4fc26232301f81c8076daf31fe58f217b Signed-off-by: Kyösti Mälkki Reviewed-on: https://review.coreboot.org/c/coreboot/+/36788 Tested-by: build bot (Jenkins) Reviewed-by: Arthur Heymans --- src/southbridge/intel/bd82x6x/lpc.c | 8 -------- src/southbridge/intel/i82801gx/lpc.c | 8 -------- src/southbridge/intel/i82801ix/lpc.c | 8 -------- src/southbridge/intel/i82801jx/lpc.c | 8 -------- src/southbridge/intel/ibexpeak/lpc.c | 8 -------- src/southbridge/intel/lynxpoint/lpc.c | 8 -------- 6 files changed, 48 deletions(-) diff --git a/src/southbridge/intel/bd82x6x/lpc.c b/src/southbridge/intel/bd82x6x/lpc.c index 5f0dd8c299..e7b7db86d8 100644 --- a/src/southbridge/intel/bd82x6x/lpc.c +++ b/src/southbridge/intel/bd82x6x/lpc.c @@ -43,8 +43,6 @@ #define NMI_OFF 0 -#define ENABLE_ACPI_MODE_IN_COREBOOT 0 - typedef struct southbridge_intel_bd82x6x_config config_t; /** @@ -421,15 +419,9 @@ static void enable_clock_gating(struct device *dev) static void pch_set_acpi_mode(void) { if (!acpi_is_wakeup_s3() && CONFIG(HAVE_SMI_HANDLER)) { -#if ENABLE_ACPI_MODE_IN_COREBOOT - printk(BIOS_DEBUG, "Enabling ACPI via APMC:\n"); - outb(APM_CNT_ACPI_ENABLE, APM_CNT); // Enable ACPI mode - printk(BIOS_DEBUG, "done.\n"); -#else printk(BIOS_DEBUG, "Disabling ACPI via APMC:\n"); outb(APM_CNT_ACPI_DISABLE, APM_CNT); // Disable ACPI mode printk(BIOS_DEBUG, "done.\n"); -#endif } } diff --git a/src/southbridge/intel/i82801gx/lpc.c b/src/southbridge/intel/i82801gx/lpc.c index 670c2f8ad1..7ba9492d50 100644 --- a/src/southbridge/intel/i82801gx/lpc.c +++ b/src/southbridge/intel/i82801gx/lpc.c @@ -41,8 +41,6 @@ #define NMI_OFF 0 -#define ENABLE_ACPI_MODE_IN_COREBOOT 0 - typedef struct southbridge_intel_i82801gx_config config_t; /** @@ -338,15 +336,9 @@ static void enable_clock_gating(void) static void i82801gx_set_acpi_mode(struct device *dev) { if (!acpi_is_wakeup_s3()) { -#if ENABLE_ACPI_MODE_IN_COREBOOT - printk(BIOS_DEBUG, "Enabling ACPI via APMC:\n"); - outb(APM_CNT_ACPI_ENABLE, APM_CNT); // Enable ACPI mode - printk(BIOS_DEBUG, "done.\n"); -#else printk(BIOS_DEBUG, "Disabling ACPI via APMC:\n"); outb(APM_CNT_ACPI_DISABLE, APM_CNT); // Disable ACPI mode printk(BIOS_DEBUG, "done.\n"); -#endif } else { printk(BIOS_DEBUG, "S3 wakeup, enabling ACPI via APMC\n"); outb(APM_CNT_ACPI_ENABLE, APM_CNT); diff --git a/src/southbridge/intel/i82801ix/lpc.c b/src/southbridge/intel/i82801ix/lpc.c index a79ade7291..16763bc71a 100644 --- a/src/southbridge/intel/i82801ix/lpc.c +++ b/src/southbridge/intel/i82801ix/lpc.c @@ -39,8 +39,6 @@ #define NMI_OFF 0 -#define ENABLE_ACPI_MODE_IN_COREBOOT 0 - typedef struct southbridge_intel_i82801ix_config config_t; static void i82801ix_enable_apic(struct device *dev) @@ -370,15 +368,9 @@ static void enable_clock_gating(void) static void i82801ix_set_acpi_mode(struct device *dev) { if (!acpi_is_wakeup_s3()) { -#if ENABLE_ACPI_MODE_IN_COREBOOT - printk(BIOS_DEBUG, "Enabling ACPI via APMC:\n"); - outb(APM_CNT_ACPI_ENABLE, APM_CNT); // Enable ACPI mode - printk(BIOS_DEBUG, "done.\n"); -#else printk(BIOS_DEBUG, "Disabling ACPI via APMC:\n"); outb(APM_CNT_ACPI_DISABLE, APM_CNT); // Disable ACPI mode printk(BIOS_DEBUG, "done.\n"); -#endif } else { printk(BIOS_DEBUG, "S3 wakeup, enabling ACPI via APMC\n"); outb(APM_CNT_ACPI_ENABLE, APM_CNT); diff --git a/src/southbridge/intel/i82801jx/lpc.c b/src/southbridge/intel/i82801jx/lpc.c index a39506976e..3e11a0887a 100644 --- a/src/southbridge/intel/i82801jx/lpc.c +++ b/src/southbridge/intel/i82801jx/lpc.c @@ -40,8 +40,6 @@ #define NMI_OFF 0 -#define ENABLE_ACPI_MODE_IN_COREBOOT 0 - typedef struct southbridge_intel_i82801jx_config config_t; static void i82801jx_enable_apic(struct device *dev) @@ -375,15 +373,9 @@ static void enable_clock_gating(void) static void i82801jx_set_acpi_mode(struct device *dev) { if (!acpi_is_wakeup_s3()) { -#if ENABLE_ACPI_MODE_IN_COREBOOT - printk(BIOS_DEBUG, "Enabling ACPI via APMC:\n"); - outb(APM_CNT_ACPI_ENABLE, APM_CNT); // Enable ACPI mode - printk(BIOS_DEBUG, "done.\n"); -#else printk(BIOS_DEBUG, "Disabling ACPI via APMC:\n"); outb(APM_CNT_ACPI_DISABLE, APM_CNT); // Disable ACPI mode printk(BIOS_DEBUG, "done.\n"); -#endif } else { printk(BIOS_DEBUG, "S3 wakeup, enabling ACPI via APMC\n"); outb(APM_CNT_ACPI_ENABLE, APM_CNT); diff --git a/src/southbridge/intel/ibexpeak/lpc.c b/src/southbridge/intel/ibexpeak/lpc.c index 64be11e9f9..2b48eab5b0 100644 --- a/src/southbridge/intel/ibexpeak/lpc.c +++ b/src/southbridge/intel/ibexpeak/lpc.c @@ -43,8 +43,6 @@ #define NMI_OFF 0 -#define ENABLE_ACPI_MODE_IN_COREBOOT 0 - typedef struct southbridge_intel_ibexpeak_config config_t; /** @@ -431,15 +429,9 @@ static void enable_clock_gating(struct device *dev) static void pch_set_acpi_mode(void) { if (!acpi_is_wakeup_s3() && CONFIG(HAVE_SMI_HANDLER)) { -#if ENABLE_ACPI_MODE_IN_COREBOOT - printk(BIOS_DEBUG, "Enabling ACPI via APMC:\n"); - outb(APM_CNT_ACPI_ENABLE, APM_CNT); // Enable ACPI mode - printk(BIOS_DEBUG, "done.\n"); -#else printk(BIOS_DEBUG, "Disabling ACPI via APMC:\n"); outb(APM_CNT_ACPI_DISABLE, APM_CNT); // Disable ACPI mode printk(BIOS_DEBUG, "done.\n"); -#endif } } diff --git a/src/southbridge/intel/lynxpoint/lpc.c b/src/southbridge/intel/lynxpoint/lpc.c index a1e026200b..c8e91c35a9 100644 --- a/src/southbridge/intel/lynxpoint/lpc.c +++ b/src/southbridge/intel/lynxpoint/lpc.c @@ -41,8 +41,6 @@ #define NMI_OFF 0 -#define ENABLE_ACPI_MODE_IN_COREBOOT 0 - typedef struct southbridge_intel_lynxpoint_config config_t; /** @@ -493,15 +491,9 @@ static void enable_lp_clock_gating(struct device *dev) static void pch_set_acpi_mode(void) { if (CONFIG(HAVE_SMI_HANDLER) && !acpi_is_wakeup_s3()) { -#if ENABLE_ACPI_MODE_IN_COREBOOT - printk(BIOS_DEBUG, "Enabling ACPI via APMC:\n"); - outb(APM_CNT_ACPI_ENABLE, APM_CNT); - printk(BIOS_DEBUG, "done.\n"); -#else printk(BIOS_DEBUG, "Disabling ACPI via APMC:\n"); outb(APM_CNT_ACPI_DISABLE, APM_CNT); printk(BIOS_DEBUG, "done.\n"); -#endif } } From cd0b67b30a3dd5cd51ff0e1ad06cdbfc8590fcf6 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ky=C3=B6sti=20M=C3=A4lkki?= Date: Wed, 9 Oct 2019 07:52:40 +0300 Subject: [PATCH 0150/1242] sb/intel/i82801dx,ix: Replace SMM_ASEG conditional MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit PARALLEL_MP path also calls smm_lock(). Change-Id: I270fc8266d118cd1e7245ea70b707a03aedac209 Signed-off-by: Kyösti Mälkki Reviewed-on: https://review.coreboot.org/c/coreboot/+/36789 Tested-by: build bot (Jenkins) Reviewed-by: Arthur Heymans --- src/southbridge/intel/i82801dx/lpc.c | 2 +- src/southbridge/intel/i82801ix/lpc.c | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/src/southbridge/intel/i82801dx/lpc.c b/src/southbridge/intel/i82801dx/lpc.c index 031a01a68b..a46f5a3707 100644 --- a/src/southbridge/intel/i82801dx/lpc.c +++ b/src/southbridge/intel/i82801dx/lpc.c @@ -304,7 +304,7 @@ static void lpc_init(struct device *dev) /* Don't allow evil boot loaders, kernels, or * userspace applications to deceive us: */ - if (CONFIG(HAVE_SMI_HANDLER)) + if (CONFIG(HAVE_SMI_HANDLER) && !CONFIG(PARALLEL_MP)) aseg_smm_lock(); } diff --git a/src/southbridge/intel/i82801ix/lpc.c b/src/southbridge/intel/i82801ix/lpc.c index 16763bc71a..3df9288530 100644 --- a/src/southbridge/intel/i82801ix/lpc.c +++ b/src/southbridge/intel/i82801ix/lpc.c @@ -423,7 +423,7 @@ static void lpc_init(struct device *dev) /* Don't allow evil boot loaders, kernels, or * userspace applications to deceive us: */ - if (CONFIG(HAVE_SMI_HANDLER) && CONFIG(SMM_ASEG)) + if (CONFIG(HAVE_SMI_HANDLER) && !CONFIG(PARALLEL_MP)) aseg_smm_lock(); } From 44da9e73c79edea8a2e7785ecf481b3eb23f813c Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ky=C3=B6sti=20M=C3=A4lkki?= Date: Wed, 9 Oct 2019 12:32:16 +0300 Subject: [PATCH 0151/1242] sb/intel/i82801gx,ix,jx: Move HAVE_SMI_HANDLER conditional MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Make these more consistent with later platforms. Followups will do a more complete refactoring of set_acpi_mode() implementations. Change-Id: I6a05b7600ebdc49915157eaff229459a1eea754c Signed-off-by: Kyösti Mälkki Reviewed-on: https://review.coreboot.org/c/coreboot/+/36790 Tested-by: build bot (Jenkins) Reviewed-by: Arthur Heymans --- src/southbridge/intel/i82801gx/lpc.c | 19 ++++++++++--------- src/southbridge/intel/i82801ix/lpc.c | 19 ++++++++++--------- src/southbridge/intel/i82801jx/lpc.c | 19 ++++++++++--------- 3 files changed, 30 insertions(+), 27 deletions(-) diff --git a/src/southbridge/intel/i82801gx/lpc.c b/src/southbridge/intel/i82801gx/lpc.c index 7ba9492d50..34250d396f 100644 --- a/src/southbridge/intel/i82801gx/lpc.c +++ b/src/southbridge/intel/i82801gx/lpc.c @@ -335,13 +335,15 @@ static void enable_clock_gating(void) static void i82801gx_set_acpi_mode(struct device *dev) { - if (!acpi_is_wakeup_s3()) { - printk(BIOS_DEBUG, "Disabling ACPI via APMC:\n"); - outb(APM_CNT_ACPI_DISABLE, APM_CNT); // Disable ACPI mode - printk(BIOS_DEBUG, "done.\n"); - } else { - printk(BIOS_DEBUG, "S3 wakeup, enabling ACPI via APMC\n"); - outb(APM_CNT_ACPI_ENABLE, APM_CNT); + if (CONFIG(HAVE_SMI_HANDLER)) { + if (!acpi_is_wakeup_s3()) { + printk(BIOS_DEBUG, "Disabling ACPI via APMC:\n"); + outb(APM_CNT_ACPI_DISABLE, APM_CNT); // Disable ACPI mode + printk(BIOS_DEBUG, "done.\n"); + } else { + printk(BIOS_DEBUG, "S3 wakeup, enabling ACPI via APMC\n"); + outb(APM_CNT_ACPI_ENABLE, APM_CNT); + } } } @@ -409,8 +411,7 @@ static void lpc_init(struct device *dev) /* Interrupt 9 should be level triggered (SCI) */ i8259_configure_irq_trigger(9, 1); - if (CONFIG(HAVE_SMI_HANDLER)) - i82801gx_set_acpi_mode(dev); + i82801gx_set_acpi_mode(dev); i82801gx_spi_init(); diff --git a/src/southbridge/intel/i82801ix/lpc.c b/src/southbridge/intel/i82801ix/lpc.c index 3df9288530..811b4b2820 100644 --- a/src/southbridge/intel/i82801ix/lpc.c +++ b/src/southbridge/intel/i82801ix/lpc.c @@ -367,13 +367,15 @@ static void enable_clock_gating(void) static void i82801ix_set_acpi_mode(struct device *dev) { - if (!acpi_is_wakeup_s3()) { - printk(BIOS_DEBUG, "Disabling ACPI via APMC:\n"); - outb(APM_CNT_ACPI_DISABLE, APM_CNT); // Disable ACPI mode - printk(BIOS_DEBUG, "done.\n"); - } else { - printk(BIOS_DEBUG, "S3 wakeup, enabling ACPI via APMC\n"); - outb(APM_CNT_ACPI_ENABLE, APM_CNT); + if (CONFIG(HAVE_SMI_HANDLER)) { + if (!acpi_is_wakeup_s3()) { + printk(BIOS_DEBUG, "Disabling ACPI via APMC:\n"); + outb(APM_CNT_ACPI_DISABLE, APM_CNT); // Disable ACPI mode + printk(BIOS_DEBUG, "done.\n"); + } else { + printk(BIOS_DEBUG, "S3 wakeup, enabling ACPI via APMC\n"); + outb(APM_CNT_ACPI_ENABLE, APM_CNT); + } } } @@ -417,8 +419,7 @@ static void lpc_init(struct device *dev) /* Interrupt 9 should be level triggered (SCI) */ i8259_configure_irq_trigger(9, 1); - if (CONFIG(HAVE_SMI_HANDLER)) - i82801ix_set_acpi_mode(dev); + i82801ix_set_acpi_mode(dev); /* Don't allow evil boot loaders, kernels, or * userspace applications to deceive us: diff --git a/src/southbridge/intel/i82801jx/lpc.c b/src/southbridge/intel/i82801jx/lpc.c index 3e11a0887a..a594452e04 100644 --- a/src/southbridge/intel/i82801jx/lpc.c +++ b/src/southbridge/intel/i82801jx/lpc.c @@ -372,13 +372,15 @@ static void enable_clock_gating(void) static void i82801jx_set_acpi_mode(struct device *dev) { - if (!acpi_is_wakeup_s3()) { - printk(BIOS_DEBUG, "Disabling ACPI via APMC:\n"); - outb(APM_CNT_ACPI_DISABLE, APM_CNT); // Disable ACPI mode - printk(BIOS_DEBUG, "done.\n"); - } else { - printk(BIOS_DEBUG, "S3 wakeup, enabling ACPI via APMC\n"); - outb(APM_CNT_ACPI_ENABLE, APM_CNT); + if (CONFIG(HAVE_SMI_HANDLER)) { + if (!acpi_is_wakeup_s3()) { + printk(BIOS_DEBUG, "Disabling ACPI via APMC:\n"); + outb(APM_CNT_ACPI_DISABLE, APM_CNT); // Disable ACPI mode + printk(BIOS_DEBUG, "done.\n"); + } else { + printk(BIOS_DEBUG, "S3 wakeup, enabling ACPI via APMC\n"); + outb(APM_CNT_ACPI_ENABLE, APM_CNT); + } } } @@ -422,8 +424,7 @@ static void lpc_init(struct device *dev) /* Interrupt 9 should be level triggered (SCI) */ i8259_configure_irq_trigger(9, 1); - if (CONFIG(HAVE_SMI_HANDLER)) - i82801jx_set_acpi_mode(dev); + i82801jx_set_acpi_mode(dev); } unsigned long acpi_fill_madt(unsigned long current) From 6abbd5b0acec1a874160ff5061d4077663649253 Mon Sep 17 00:00:00 2001 From: Julius Werner Date: Tue, 12 Nov 2019 15:13:12 -0800 Subject: [PATCH 0152/1242] cbfs: Make cbfs_master_header_props() externally available This patch makes the CBFS default locator .locate() callback externally available so that code which overrides cbfs_master_header_locator can reuse or wrap it and doesn't have to copy&paste the whole thing. Use it for the Eltan vendorcode implementation which previously did this. Change-Id: I54dad5c8ea64ea0fc472217e275daa815736991e Signed-off-by: Julius Werner Reviewed-on: https://review.coreboot.org/c/coreboot/+/36797 Reviewed-by: Wim Vervoorn Reviewed-by: Aaron Durbin Tested-by: build bot (Jenkins) --- src/include/cbfs.h | 3 ++ src/lib/cbfs.c | 2 +- .../security/verified_boot/vboot_check.c | 43 +------------------ 3 files changed, 5 insertions(+), 43 deletions(-) diff --git a/src/include/cbfs.h b/src/include/cbfs.h index 85e25b3d9b..f012441896 100644 --- a/src/include/cbfs.h +++ b/src/include/cbfs.h @@ -73,6 +73,9 @@ struct cbfs_props { size_t size; }; +/* Default CBFS locator .locate() callback that locates "COREBOOT" region. */ +int cbfs_master_header_props(struct cbfs_props *props); + /* Return < 0 on error otherwise props are filled out accordingly. */ int cbfs_boot_region_properties(struct cbfs_props *props); diff --git a/src/lib/cbfs.c b/src/lib/cbfs.c index 13b5afb6ea..1601f201fe 100644 --- a/src/lib/cbfs.c +++ b/src/lib/cbfs.c @@ -298,7 +298,7 @@ out: } /* This only supports the "COREBOOT" fmap region. */ -static int cbfs_master_header_props(struct cbfs_props *props) +int cbfs_master_header_props(struct cbfs_props *props) { struct cbfs_header header; const struct region_device *bdev; diff --git a/src/vendorcode/eltan/security/verified_boot/vboot_check.c b/src/vendorcode/eltan/security/verified_boot/vboot_check.c index 1dc1c3a37f..823c2de412 100644 --- a/src/vendorcode/eltan/security/verified_boot/vboot_check.c +++ b/src/vendorcode/eltan/security/verified_boot/vboot_check.c @@ -17,7 +17,6 @@ #include #include #include -#include "fmap_config.h" #define RSA_PUBLICKEY_FILE_NAME "vboot_public_key.bin" @@ -91,46 +90,6 @@ fail: return -1; } -static int vendor_secure_locate(struct cbfs_props *props) -{ - struct cbfs_header header; - const struct region_device *bdev; - int32_t rel_offset; - size_t offset; - - bdev = boot_device_ro(); - - if (bdev == NULL) - return -1; - - size_t fmap_top = ___FMAP__COREBOOT_BASE + ___FMAP__COREBOOT_SIZE; - - /* Find location of header using signed 32-bit offset from - * end of CBFS region. */ - offset = fmap_top - sizeof(int32_t); - if (rdev_readat(bdev, &rel_offset, offset, sizeof(int32_t)) < 0) - return -1; - - offset = fmap_top + rel_offset; - if (rdev_readat(bdev, &header, offset, sizeof(header)) < 0) - return -1; - - header.magic = ntohl(header.magic); - header.romsize = ntohl(header.romsize); - header.offset = ntohl(header.offset); - - if (header.magic != CBFS_HEADER_MAGIC) - return -1; - - props->offset = header.offset; - props->size = header.romsize; - props->size -= props->offset; - - printk(BIOS_SPEW, "CBFS @ %zx size %zx\n", props->offset, props->size); - - return 0; -} - /* * * measure_item @@ -399,5 +358,5 @@ static void vendor_secure_prepare(void) const struct cbfs_locator cbfs_master_header_locator = { .name = "Vendorcode Header Locator", .prepare = vendor_secure_prepare, - .locate = vendor_secure_locate + .locate = cbfs_master_header_props }; From cefe89ee7916b2c1fd6401456313f8a4d110735c Mon Sep 17 00:00:00 2001 From: Julius Werner Date: Wed, 6 Nov 2019 19:29:44 -0800 Subject: [PATCH 0153/1242] lib/fmap: Add optional pre-RAM cache This patch adds an optional pre-RAM cache for the FMAP which most platforms should be able to use, complementing the recently added post-RAM FMAP cache in CBMEM. vboot systems currently read the FMAP about half a dozen times from flash in verstage, which will all be coalesced into a single read with this patch. It will also help future vboot improvements since when FMAP reads become "free" vboot doesn't need to keep track of so much information separately. In order to make sure we have a single, well-defined point where the new cache is first initialized, eliminate the build-time hardcoding of the CBFS section offsets, so that all CBFS accesses explicitly read the FMAP. Add FMAP_CACHEs to all platforms that can afford it (other than the RISC-V things where I have no idea how they work), trying to take the space from things that look like they were oversized anyway (pre-RAM consoles and CBFS caches). Change-Id: I2820436776ef620bdc4481b5cd4b6957764248ea Signed-off-by: Julius Werner Reviewed-on: https://review.coreboot.org/c/coreboot/+/36657 Tested-by: build bot (Jenkins) Reviewed-by: Arthur Heymans Reviewed-by: Aaron Durbin Reviewed-by: Joel Kitching --- Makefile.inc | 2 +- src/arch/x86/car.ld | 1 + src/include/memlayout.h | 10 +- src/include/symbols.h | 1 + src/lib/Makefile.inc | 7 -- src/lib/cbfs.c | 6 +- src/lib/fmap.c | 119 +++++++++++++----- .../mediatek/mt8173/include/soc/memlayout.ld | 3 +- .../mediatek/mt8183/include/soc/memlayout.ld | 3 +- .../nvidia/tegra124/include/soc/memlayout.ld | 3 +- .../nvidia/tegra210/include/soc/memlayout.ld | 3 +- .../qualcomm/ipq40xx/include/soc/memlayout.ld | 3 +- .../qualcomm/ipq806x/include/soc/memlayout.ld | 3 +- .../qualcomm/qcs405/include/soc/memlayout.ld | 3 +- .../qualcomm/sc7180/include/soc/memlayout.ld | 1 + .../rockchip/rk3399/include/soc/memlayout.ld | 3 +- .../exynos5250/include/soc/memlayout.ld | 3 +- .../exynos5420/include/soc/memlayout.ld | 3 +- util/cbfstool/fmaptool.c | 23 +--- 19 files changed, 132 insertions(+), 68 deletions(-) diff --git a/Makefile.inc b/Makefile.inc index 8ecc0ef3b2..8de54a05a6 100644 --- a/Makefile.inc +++ b/Makefile.inc @@ -226,7 +226,7 @@ $(foreach type,ads adb, \ # Add handler to copy linker scripts define generic-objs_ld_template_gen de$(EMPTY)fine $(1)-objs_ld_template -$$(call src-to-obj,$1,$$(1).ld): $$(1).ld $(obj)/config.h +$$(call src-to-obj,$1,$$(1).ld): $$(1).ld $(obj)/config.h $(obj)/fmap_config.h @printf " CP $$$$(subst $$$$(obj)/,,$$$$(@))\n" $$(CC_$(1)) -MMD $$(CPPFLAGS_$(1)) $$($(1)-ld-ccopts) $(PREPROCESS_ONLY) -include $(obj)/config.h -MT $$$$@ -o $$$$@ $$$$< en$(EMPTY)def diff --git a/src/arch/x86/car.ld b/src/arch/x86/car.ld index 74fc74b58e..972cb5234b 100644 --- a/src/arch/x86/car.ld +++ b/src/arch/x86/car.ld @@ -58,6 +58,7 @@ #endif TIMESTAMP(., 0x200) + FMAP_CACHE(., FMAP_SIZE) _car_ehci_dbg_info = .; /* Reserve sizeof(struct ehci_dbg_info). */ diff --git a/src/include/memlayout.h b/src/include/memlayout.h index 0100e270c6..56dfb6a785 100644 --- a/src/include/memlayout.h +++ b/src/include/memlayout.h @@ -21,6 +21,8 @@ #include #include +#include "fmap_config.h" + /* Macros that the architecture can override. */ #ifndef ARCH_POINTER_ALIGN_SIZE #define ARCH_POINTER_ALIGN_SIZE 8 @@ -30,7 +32,8 @@ #define ARCH_CACHELINE_ALIGN_SIZE 64 #endif -#define STR(x) #x +#define STR(x) XSTR(x) +#define XSTR(x) #x #define ALIGN_COUNTER(align) \ . = ALIGN(align); @@ -73,6 +76,11 @@ ALIAS_REGION(cbfs_cache, preram_cbfs_cache) \ ALIAS_REGION(cbfs_cache, postram_cbfs_cache) +#define FMAP_CACHE(addr, sz) \ + REGION(fmap_cache, addr, sz, 4) \ + _ = ASSERT(sz == 0 || sz >= FMAP_SIZE, \ + STR(FMAP does not fit in FMAP_CACHE! (sz < FMAP_SIZE))); + #if ENV_ROMSTAGE_OR_BEFORE #define PRERAM_CBFS_CACHE(addr, size) \ REGION(preram_cbfs_cache, addr, size, 4) \ diff --git a/src/include/symbols.h b/src/include/symbols.h index 56df8d5734..eec47010e4 100644 --- a/src/include/symbols.h +++ b/src/include/symbols.h @@ -34,6 +34,7 @@ DECLARE_REGION(stack) DECLARE_REGION(preram_cbfs_cache) DECLARE_REGION(postram_cbfs_cache) DECLARE_REGION(cbfs_cache) +DECLARE_REGION(fmap_cache) DECLARE_REGION(payload) /* "program" always refers to the current execution unit. */ diff --git a/src/lib/Makefile.inc b/src/lib/Makefile.inc index 3b7d57c76a..dc0c46d460 100644 --- a/src/lib/Makefile.inc +++ b/src/lib/Makefile.inc @@ -208,13 +208,6 @@ $(call src-to-obj,smm,$(dir)/version.c) : $(obj)/build.h $(call src-to-obj,verstage,$(dir)/version.c) : $(obj)/build.h $(call src-to-obj,postcar,$(dir)/version.c) : $(obj)/build.h -$(call src-to-obj,bootblock,$(dir)/cbfs.c) : $(obj)/fmap_config.h -$(call src-to-obj,romstage,$(dir)/cbfs.c) : $(obj)/fmap_config.h -$(call src-to-obj,ramstage,$(dir)/cbfs.c) : $(obj)/fmap_config.h -$(call src-to-obj,smm,$(dir)/cbfs.c) : $(obj)/fmap_config.h -$(call src-to-obj,verstage,$(dir)/cbfs.c) : $(obj)/fmap_config.h -$(call src-to-obj,postcar,$(dir)/cbfs.c) : $(obj)/fmap_config.h - $(call src-to-obj,bootblock,$(dir)/fmap.c) : $(obj)/fmap_config.h $(call src-to-obj,romstage,$(dir)/fmap.c) : $(obj)/fmap_config.h $(call src-to-obj,ramstage,$(dir)/fmap.c) : $(obj)/fmap_config.h diff --git a/src/lib/cbfs.c b/src/lib/cbfs.c index 1601f201fe..27a1592e2b 100644 --- a/src/lib/cbfs.c +++ b/src/lib/cbfs.c @@ -26,7 +26,6 @@ #include #include #include -#include "fmap_config.h" #include #define ERROR(x...) printk(BIOS_ERR, "CBFS: " x) @@ -310,7 +309,10 @@ int cbfs_master_header_props(struct cbfs_props *props) if (bdev == NULL) return -1; - size_t fmap_top = ___FMAP__COREBOOT_BASE + ___FMAP__COREBOOT_SIZE; + struct region fmap_region; + if (fmap_locate_area("COREBOOT", &fmap_region)) + return -1; + size_t fmap_top = region_end(&fmap_region); /* Find location of header using signed 32-bit offset from * end of CBFS region. */ diff --git a/src/lib/fmap.c b/src/lib/fmap.c index f3ff071766..4b4179c769 100644 --- a/src/lib/fmap.c +++ b/src/lib/fmap.c @@ -15,12 +15,13 @@ #include #include +#include #include #include #include #include #include -#include +#include #include "fmap_config.h" @@ -31,26 +32,94 @@ static int fmap_print_once CAR_GLOBAL; static struct mem_region_device fmap_cache CAR_GLOBAL; +#define print_once(...) do { \ + if (!car_get_var(fmap_print_once)) \ + printk(__VA_ARGS__); \ + } while (0) + +DECLARE_OPTIONAL_REGION(fmap_cache); + uint64_t get_fmap_flash_offset(void) { return FMAP_OFFSET; } +static int check_signature(const struct fmap *fmap) +{ + return memcmp(fmap->signature, FMAP_SIGNATURE, sizeof(fmap->signature)); +} + +static void report(const struct fmap *fmap) +{ + print_once(BIOS_DEBUG, "FMAP: Found \"%s\" version %d.%d at %#x.\n", + fmap->name, fmap->ver_major, fmap->ver_minor, FMAP_OFFSET); + print_once(BIOS_DEBUG, "FMAP: base = %#llx size = %#x #areas = %d\n", + (long long)fmap->base, fmap->size, fmap->nareas); + car_set_var(fmap_print_once, 1); +} + +static void setup_preram_cache(struct mem_region_device *cache_mrdev) +{ + if (!ENV_ROMSTAGE_OR_BEFORE) { + /* We get here if ramstage makes an FMAP access before calling + cbmem_initialize(). We should avoid letting it come to that, + so print a warning. */ + print_once(BIOS_WARNING, + "WARNING: Post-RAM FMAP access too early for cache!\n"); + return; + } + + if (REGION_SIZE(fmap_cache) == 0) { + /* If you see this you really want to add an FMAP_CACHE to your + memlayout, unless you absolutely can't affort the 2K. */ + print_once(BIOS_NOTICE, + "NOTE: Running without FMAP_CACHE, should add it!\n"); + return; + } + + struct fmap *fmap = (struct fmap *)_fmap_cache; + if (!ENV_BOOTBLOCK) { + /* NOTE: This assumes that for all platforms running this code, + the bootblock is the first stage and the bootblock will make + at least one FMAP access (usually from finding CBFS). */ + if (!check_signature(fmap)) + goto register_cache; + + printk(BIOS_ERR, "ERROR: FMAP cache corrupted?!\n"); + } + + /* In case we fail below, make sure the cache is invalid. */ + memset(fmap->signature, 0, sizeof(fmap->signature)); + + boot_device_init(); + const struct region_device *boot_rdev = boot_device_ro(); + if (!boot_rdev) + return; + + /* memlayout statically guarantees that the FMAP_CACHE is big enough. */ + if (rdev_readat(boot_rdev, fmap, FMAP_OFFSET, FMAP_SIZE) != FMAP_SIZE) + return; + if (check_signature(fmap)) + return; + report(fmap); + +register_cache: + mem_region_device_ro_init(cache_mrdev, fmap, FMAP_SIZE); +} + static int find_fmap_directory(struct region_device *fmrd) { const struct region_device *boot; struct fmap *fmap; - size_t fmap_size; + struct mem_region_device *cache; size_t offset = FMAP_OFFSET; - if (cbmem_possibly_online() && !ENV_SMM) { - /* Try FMAP cache first */ - const struct mem_region_device *cache; - - cache = car_get_var_ptr(&fmap_cache); - if (region_device_sz(&cache->rdev)) - return rdev_chain_full(fmrd, &cache->rdev); - } + /* Try FMAP cache first */ + cache = car_get_var_ptr(&fmap_cache); + if (!region_device_sz(&cache->rdev)) + setup_preram_cache(cache); + if (region_device_sz(&cache->rdev)) + return rdev_chain_full(fmrd, &cache->rdev); boot_device_init(); boot = boot_device_ro(); @@ -58,32 +127,22 @@ static int find_fmap_directory(struct region_device *fmrd) if (boot == NULL) return -1; - fmap_size = sizeof(struct fmap); - - fmap = rdev_mmap(boot, offset, fmap_size); + fmap = rdev_mmap(boot, offset, sizeof(struct fmap)); if (fmap == NULL) return -1; - if (memcmp(fmap->signature, FMAP_SIGNATURE, sizeof(fmap->signature))) { + if (check_signature(fmap)) { printk(BIOS_DEBUG, "No FMAP found at %zx offset.\n", offset); rdev_munmap(boot, fmap); return -1; } - if (!car_get_var(fmap_print_once)) { - printk(BIOS_DEBUG, "FMAP: Found \"%s\" version %d.%d at %zx.\n", - fmap->name, fmap->ver_major, fmap->ver_minor, offset); - printk(BIOS_DEBUG, "FMAP: base = %llx size = %x #areas = %d\n", - (long long)fmap->base, fmap->size, fmap->nareas); - car_set_var(fmap_print_once, 1); - } - - fmap_size += fmap->nareas * sizeof(struct fmap_area); + report(fmap); rdev_munmap(boot, fmap); - return rdev_chain(fmrd, boot, offset, fmap_size); + return rdev_chain(fmrd, boot, offset, FMAP_SIZE); } int fmap_locate_area_as_rdev(const char *name, struct region_device *area) @@ -212,7 +271,7 @@ ssize_t fmap_overwrite_area(const char *name, const void *buffer, size_t size) return rdev_writeat(&rdev, buffer, 0, size); } -static void fmap_register_cache(int unused) +static void fmap_register_cbmem_cache(int unused) { const struct cbmem_entry *e; struct mem_region_device *mdev; @@ -232,7 +291,7 @@ static void fmap_register_cache(int unused) * The main reason to copy the FMAP into CBMEM is to make it available to the * OS on every architecture. As side effect use the CBMEM copy as cache. */ -static void fmap_setup_cache(int unused) +static void fmap_setup_cbmem_cache(int unused) { struct region_device fmrd; @@ -255,9 +314,9 @@ static void fmap_setup_cache(int unused) } /* Finally advertise the cache for the current stage */ - fmap_register_cache(unused); + fmap_register_cbmem_cache(unused); } -ROMSTAGE_CBMEM_INIT_HOOK(fmap_setup_cache) -RAMSTAGE_CBMEM_INIT_HOOK(fmap_register_cache) -POSTCAR_CBMEM_INIT_HOOK(fmap_register_cache) +ROMSTAGE_CBMEM_INIT_HOOK(fmap_setup_cbmem_cache) +RAMSTAGE_CBMEM_INIT_HOOK(fmap_register_cbmem_cache) +POSTCAR_CBMEM_INIT_HOOK(fmap_register_cbmem_cache) diff --git a/src/soc/mediatek/mt8173/include/soc/memlayout.ld b/src/soc/mediatek/mt8173/include/soc/memlayout.ld index adda86e11b..2358c3940c 100644 --- a/src/soc/mediatek/mt8173/include/soc/memlayout.ld +++ b/src/soc/mediatek/mt8173/include/soc/memlayout.ld @@ -40,7 +40,8 @@ SECTIONS SRAM_START(0x00100000) VBOOT2_WORK(0x00100000, 12K) VBOOT2_TPM_LOG(0x00103000, 2K) - PRERAM_CBMEM_CONSOLE(0x00103800, 14K) + FMAP_CACHE(0x00103800, 2K) + PRERAM_CBMEM_CONSOLE(0x00104000, 12K) WATCHDOG_TOMBSTONE(0x00107000, 4) PRERAM_CBFS_CACHE(0x00107004, 16K - 4) TIMESTAMP(0x0010B000, 4K) diff --git a/src/soc/mediatek/mt8183/include/soc/memlayout.ld b/src/soc/mediatek/mt8183/include/soc/memlayout.ld index 82e404f790..a8f464a3d8 100644 --- a/src/soc/mediatek/mt8183/include/soc/memlayout.ld +++ b/src/soc/mediatek/mt8183/include/soc/memlayout.ld @@ -34,7 +34,8 @@ SECTIONS VBOOT2_TPM_LOG(0x00103000, 2K) PRERAM_CBMEM_CONSOLE(0x00103800, 14K) WATCHDOG_TOMBSTONE(0x00107000, 4) - PRERAM_CBFS_CACHE(0x00107004, 48K - 4) + PRERAM_CBFS_CACHE(0x00107004, 46K - 4) + FMAP_CACHE(0x00112800, 2K) TIMESTAMP(0x00113000, 4K) STACK(0x00114000, 16K) TTB(0x00118000, 28K) diff --git a/src/soc/nvidia/tegra124/include/soc/memlayout.ld b/src/soc/nvidia/tegra124/include/soc/memlayout.ld index 7e2f9ec2af..7e2cc7ad58 100644 --- a/src/soc/nvidia/tegra124/include/soc/memlayout.ld +++ b/src/soc/nvidia/tegra124/include/soc/memlayout.ld @@ -28,7 +28,8 @@ SECTIONS SRAM_START(0x40000000) TTB(0x40000000, 16K + 32) PRERAM_CBMEM_CONSOLE(0x40004020, 6K - 32) - PRERAM_CBFS_CACHE(0x40005800, 16K) + FMAP_CACHE(0x40005800, 2K) + PRERAM_CBFS_CACHE(0x40006000, 14K) VBOOT2_WORK(0x40009800, 12K) VBOOT2_TPM_LOG(0x4000D800, 2K) STACK(0x4000E000, 8K) diff --git a/src/soc/nvidia/tegra210/include/soc/memlayout.ld b/src/soc/nvidia/tegra210/include/soc/memlayout.ld index 1134da6111..b7268d114b 100644 --- a/src/soc/nvidia/tegra210/include/soc/memlayout.ld +++ b/src/soc/nvidia/tegra210/include/soc/memlayout.ld @@ -29,7 +29,8 @@ SECTIONS { SRAM_START(0x40000000) PRERAM_CBMEM_CONSOLE(0x40000000, 2K) - PRERAM_CBFS_CACHE(0x40000800, 30K) + FMAP_CACHE(0x40000800, 2K) + PRERAM_CBFS_CACHE(0x40001000, 28K) VBOOT2_WORK(0x40008000, 12K) VBOOT2_TPM_LOG(0x4000B000, 2K) #if ENV_ARM64 diff --git a/src/soc/qualcomm/ipq40xx/include/soc/memlayout.ld b/src/soc/qualcomm/ipq40xx/include/soc/memlayout.ld index f1a7bc59d2..6ff1018272 100644 --- a/src/soc/qualcomm/ipq40xx/include/soc/memlayout.ld +++ b/src/soc/qualcomm/ipq40xx/include/soc/memlayout.ld @@ -34,7 +34,8 @@ SECTIONS /* This includes bootblock image, can be reused after bootblock starts */ /* UBER_SBL(0x0A0C0000, 48K) */ - PRERAM_CBFS_CACHE(0x0A0C0000, 93K) + PRERAM_CBFS_CACHE(0x0A0C0000, 92K) + FMAP_CACHE(0x0A0EF800, 2K) TTB(0x0A0F0000, 16K) TTB_SUBTABLES(0x0A0F4000, 4K) diff --git a/src/soc/qualcomm/ipq806x/include/soc/memlayout.ld b/src/soc/qualcomm/ipq806x/include/soc/memlayout.ld index 25db17587c..595d939d0b 100644 --- a/src/soc/qualcomm/ipq806x/include/soc/memlayout.ld +++ b/src/soc/qualcomm/ipq806x/include/soc/memlayout.ld @@ -38,7 +38,8 @@ SECTIONS QCA_SHARED_RAM(2A03F000, 4K) */ STACK(0x2A040000, 16K) - PRERAM_CBFS_CACHE(0x2A044000, 93K) + PRERAM_CBFS_CACHE(0x2A044000, 91K) + FMAP_CACHE(0x2A05B000, 2K) TTB_SUBTABLES(0x2A05B800, 2K) TTB(0x2A05C000, 16K) SRAM_END(0x2A060000) diff --git a/src/soc/qualcomm/qcs405/include/soc/memlayout.ld b/src/soc/qualcomm/qcs405/include/soc/memlayout.ld index 68642d67a2..dd013b5e8f 100644 --- a/src/soc/qualcomm/qcs405/include/soc/memlayout.ld +++ b/src/soc/qualcomm/qcs405/include/soc/memlayout.ld @@ -39,7 +39,8 @@ SECTIONS TIMESTAMP(0x8C4F000, 1K) PRERAM_CBMEM_CONSOLE(0x8C4F400, 32K) PRERAM_CBFS_CACHE(0x8C57400, 70K) - REGION(bsram_unused, 0x8C68C00, 0xA2400, 0x100) + FMAP_CACHE(0x8C68C00, 2K) + REGION(bsram_unused, 0x8C69400, 0xA1C00, 0x100) BSRAM_END(0x8D80000) DRAM_START(0x80000000) diff --git a/src/soc/qualcomm/sc7180/include/soc/memlayout.ld b/src/soc/qualcomm/sc7180/include/soc/memlayout.ld index b2ee3b20a0..3f43419d14 100644 --- a/src/soc/qualcomm/sc7180/include/soc/memlayout.ld +++ b/src/soc/qualcomm/sc7180/include/soc/memlayout.ld @@ -43,6 +43,7 @@ SECTIONS REGION(ddr_training, 0x14850000, 8K, 4K) REGION(qclib_serial_log, 0x14852000, 4K, 4K) REGION(ddr_information, 0x14853000, 1K, 1K) + FMAP_CACHE(0x14853400, 2K) REGION(dcb, 0x14870000, 16K, 4K) REGION(pmic, 0x14874000, 44K, 4K) REGION(limits_cfg, 0x1487F000, 4K, 4K) diff --git a/src/soc/rockchip/rk3399/include/soc/memlayout.ld b/src/soc/rockchip/rk3399/include/soc/memlayout.ld index 293057a091..4e46e2d764 100644 --- a/src/soc/rockchip/rk3399/include/soc/memlayout.ld +++ b/src/soc/rockchip/rk3399/include/soc/memlayout.ld @@ -33,7 +33,8 @@ SECTIONS #if ENV_RAMSTAGE REGION(bl31_sram, 0xFF8C0000, 64K, 1) #else - PRERAM_CBFS_CACHE(0xFF8C0000, 7K) + PRERAM_CBFS_CACHE(0xFF8C0000, 5K) + FMAP_CACHE(0xFF8C1400, 2K) TIMESTAMP(0xFF8C1C00, 1K) /* 0xFF8C2004 is the entry point address the masked ROM will jump to. */ OVERLAP_DECOMPRESSOR_VERSTAGE_ROMSTAGE(0xFF8C2004, 88K - 4) diff --git a/src/soc/samsung/exynos5250/include/soc/memlayout.ld b/src/soc/samsung/exynos5250/include/soc/memlayout.ld index 0bd319e45d..7e052f0f31 100644 --- a/src/soc/samsung/exynos5250/include/soc/memlayout.ld +++ b/src/soc/samsung/exynos5250/include/soc/memlayout.ld @@ -31,7 +31,8 @@ SECTIONS ROMSTAGE(0x2030000, 128K) /* 32K hole */ TTB(0x2058000, 16K) - PRERAM_CBFS_CACHE(0x205C000, 78K) + PRERAM_CBFS_CACHE(0x205C000, 76K) + FMAP_CACHE(0x206F000, 2K) VBOOT2_TPM_LOG(0x206F800, 2K) VBOOT2_WORK(0x2070000, 12K) STACK(0x2074000, 16K) diff --git a/src/soc/samsung/exynos5420/include/soc/memlayout.ld b/src/soc/samsung/exynos5420/include/soc/memlayout.ld index bc5d0669da..ff781d2228 100644 --- a/src/soc/samsung/exynos5420/include/soc/memlayout.ld +++ b/src/soc/samsung/exynos5420/include/soc/memlayout.ld @@ -32,7 +32,8 @@ SECTIONS ROMSTAGE(0x2030000, 128K) /* 32K hole */ TTB(0x2058000, 16K) - PRERAM_CBFS_CACHE(0x205C000, 76K) + PRERAM_CBFS_CACHE(0x205C000, 74K) + FMAP_CACHE(0x206E800, 2K) STACK(0x206F000, 16K) /* 1K hole for weird kernel-shared CPU/SMP state structure that doesn't * seem to be implemented right now? */ diff --git a/util/cbfstool/fmaptool.c b/util/cbfstool/fmaptool.c index faf65081fd..1c01ec0da9 100644 --- a/util/cbfstool/fmaptool.c +++ b/util/cbfstool/fmaptool.c @@ -24,6 +24,7 @@ #define STDIN_FILENAME_SENTINEL "-" #define HEADER_FMAP_OFFSET "FMAP_OFFSET" +#define HEADER_FMAP_SIZE "FMAP_SIZE" enum fmaptool_return { FMAPTOOL_EXIT_SUCCESS = 0, @@ -83,7 +84,8 @@ static void list_cbfs_section_names(FILE *out) } static bool write_header(const char *out_fname, - const struct flashmap_descriptor *root) + const struct flashmap_descriptor *root, + const int fmap_size) { assert(out_fname); @@ -100,21 +102,8 @@ static bool write_header(const char *out_fname, fputs("#ifndef FMAPTOOL_GENERATED_HEADER_H_\n", header); fputs("#define FMAPTOOL_GENERATED_HEADER_H_\n\n", header); - fprintf(header, "#define %s %#x\n\n", HEADER_FMAP_OFFSET, fmap_offset); - - /* also add defines for each CBFS-carrying fmap region: base and size */ - cbfs_section_iterator_t cbfs_it = cbfs_sections_iterator(); - while (cbfs_it) { - const struct flashmap_descriptor *item = - cbfs_sections_iterator_deref(cbfs_it); - assert(item->offset_known && item->size_known); - unsigned abs_base = fmd_calc_absolute_offset(root, item->name); - fprintf(header, "#define ___FMAP__%s_BASE 0x%x\n", - item->name, abs_base); - fprintf(header, "#define ___FMAP__%s_SIZE 0x%x\n", - item->name, item->size); - cbfs_sections_iterator_advance(&cbfs_it); - } + fprintf(header, "#define %s %#x\n", HEADER_FMAP_OFFSET, fmap_offset); + fprintf(header, "#define %s %#x\n\n", HEADER_FMAP_SIZE, fmap_size); fputs("#endif\n", header); @@ -245,7 +234,7 @@ int main(int argc, char **argv) fmap_destroy(flashmap); if (args.header_filename && - !write_header(args.header_filename, descriptor)) { + !write_header(args.header_filename, descriptor, size)) { full_fmd_cleanup(&descriptor); return FMAPTOOL_EXIT_FAILED_WRITING_HEADER; } From 32e13c0b003eab6941236fc04d0299f6a0bf0ca2 Mon Sep 17 00:00:00 2001 From: Julius Werner Date: Fri, 8 Nov 2019 13:06:20 -0800 Subject: [PATCH 0154/1242] cbfs: Stop checking master header The CBFS master header is a legacy structure that just conveys the same information we already have from the FMAP these days. We're still including it to support older CBFS implementations in some payloads, but there's no need for coreboot itself to follow this indirection anymore. This patch simplifies the default CBFS locator to just return the CBFS offset and size from the FMAP directly. Change-Id: I6b00dd7f276364d62fa1f637efbaee0e80607c49 Signed-off-by: Julius Werner Reviewed-on: https://review.coreboot.org/c/coreboot/+/36688 Reviewed-by: Wim Vervoorn Reviewed-by: Aaron Durbin Tested-by: build bot (Jenkins) --- src/include/cbfs.h | 2 +- src/lib/cbfs.c | 48 ++++--------------- src/soc/intel/apollolake/mmap_boot.c | 6 +-- .../security/verified_boot/vboot_check.c | 4 +- 4 files changed, 16 insertions(+), 44 deletions(-) diff --git a/src/include/cbfs.h b/src/include/cbfs.h index f012441896..d76fdd3e80 100644 --- a/src/include/cbfs.h +++ b/src/include/cbfs.h @@ -74,7 +74,7 @@ struct cbfs_props { }; /* Default CBFS locator .locate() callback that locates "COREBOOT" region. */ -int cbfs_master_header_props(struct cbfs_props *props); +int cbfs_default_props(struct cbfs_props *props); /* Return < 0 on error otherwise props are filled out accordingly. */ int cbfs_boot_region_properties(struct cbfs_props *props); diff --git a/src/lib/cbfs.c b/src/lib/cbfs.c index 27a1592e2b..408e685256 100644 --- a/src/lib/cbfs.c +++ b/src/lib/cbfs.c @@ -296,44 +296,16 @@ out: return 0; } -/* This only supports the "COREBOOT" fmap region. */ -int cbfs_master_header_props(struct cbfs_props *props) +/* The default locator to find the CBFS in the "COREBOOT" FMAP region. */ +int cbfs_default_props(struct cbfs_props *props) { - struct cbfs_header header; - const struct region_device *bdev; - int32_t rel_offset; - size_t offset; + struct region region; - bdev = boot_device_ro(); - - if (bdev == NULL) + if (fmap_locate_area("COREBOOT", ®ion)) return -1; - struct region fmap_region; - if (fmap_locate_area("COREBOOT", &fmap_region)) - return -1; - size_t fmap_top = region_end(&fmap_region); - - /* Find location of header using signed 32-bit offset from - * end of CBFS region. */ - offset = fmap_top - sizeof(int32_t); - if (rdev_readat(bdev, &rel_offset, offset, sizeof(int32_t)) < 0) - return -1; - - offset = fmap_top + (int32_t)le32_to_cpu(rel_offset); - if (rdev_readat(bdev, &header, offset, sizeof(header)) < 0) - return -1; - - header.magic = ntohl(header.magic); - header.romsize = ntohl(header.romsize); - header.offset = ntohl(header.offset); - - if (header.magic != CBFS_HEADER_MAGIC) - return -1; - - props->offset = header.offset; - props->size = header.romsize; - props->size -= props->offset; + props->offset = region_offset(®ion); + props->size = region_sz(®ion); printk(BIOS_SPEW, "CBFS @ %zx size %zx\n", props->offset, props->size); @@ -343,9 +315,9 @@ int cbfs_master_header_props(struct cbfs_props *props) /* This struct is marked as weak to allow a particular platform to * override the master header logic. This implementation should work for most * devices. */ -const struct cbfs_locator __weak cbfs_master_header_locator = { - .name = "Master Header Locator", - .locate = cbfs_master_header_props, +const struct cbfs_locator __weak cbfs_default_locator = { + .name = "COREBOOT Locator", + .locate = cbfs_default_props, }; extern const struct cbfs_locator vboot_locator; @@ -359,7 +331,7 @@ static const struct cbfs_locator *locators[] = { */ &vboot_locator, #endif - &cbfs_master_header_locator, + &cbfs_default_locator, }; int cbfs_boot_region_properties(struct cbfs_props *props) diff --git a/src/soc/intel/apollolake/mmap_boot.c b/src/soc/intel/apollolake/mmap_boot.c index 614b6031c4..631a834160 100644 --- a/src/soc/intel/apollolake/mmap_boot.c +++ b/src/soc/intel/apollolake/mmap_boot.c @@ -128,10 +128,10 @@ static int iafw_boot_region_properties(struct cbfs_props *props) } /* - * Named cbfs_master_header_locator so that it overrides the default, but - * incompatible locator in cbfs.c + * Named cbfs_default_locator so that it overrides the default, but incompatible + * locator in cbfs.c */ -const struct cbfs_locator cbfs_master_header_locator = { +const struct cbfs_locator cbfs_default_locator = { .name = "IAFW Locator", .locate = iafw_boot_region_properties, }; diff --git a/src/vendorcode/eltan/security/verified_boot/vboot_check.c b/src/vendorcode/eltan/security/verified_boot/vboot_check.c index 823c2de412..c58ace1cf6 100644 --- a/src/vendorcode/eltan/security/verified_boot/vboot_check.c +++ b/src/vendorcode/eltan/security/verified_boot/vboot_check.c @@ -355,8 +355,8 @@ static void vendor_secure_prepare(void) } } -const struct cbfs_locator cbfs_master_header_locator = { +const struct cbfs_locator cbfs_default_locator = { .name = "Vendorcode Header Locator", .prepare = vendor_secure_prepare, - .locate = cbfs_master_header_props + .locate = cbfs_default_props }; From 6aa81fa55e46a308e78506d6ee93a61fb569b6c6 Mon Sep 17 00:00:00 2001 From: Selma BENSAID Date: Fri, 25 Oct 2019 11:36:17 -0700 Subject: [PATCH 0155/1242] Fix sarien depthcharge make build CONFIG_MAINBOARD_DEPTHCHARGE is set to "" for boards not configuring it. Signed-off-by: Selma BENSAID Change-Id: If61a1371ad8baf165b09ce045fc1a6c205c2c0ae Reviewed-on: https://review.coreboot.org/c/coreboot/+/36336 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi --- payloads/external/Makefile.inc | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/payloads/external/Makefile.inc b/payloads/external/Makefile.inc index f6417fd946..b8af8c9120 100644 --- a/payloads/external/Makefile.inc +++ b/payloads/external/Makefile.inc @@ -29,10 +29,10 @@ endif ifeq ($(CONFIG_PAYLOAD_DEPTHCHARGE),y) PAYLOAD_CONFIG=payloads/external/depthcharge/depthcharge/.config $(PAYLOAD_CONFIG): payloads/external/depthcharge/depthcharge/build/depthcharge.elf -ifneq ($(CONFIG_MAINBOARD_DEPTHCHARGE),) - BOARD=$(CONFIG_MAINBOARD_DEPTHCHARGE) -else +ifeq ($(call strip_quotes,$(CONFIG_MAINBOARD_DEPTHCHARGE))),) BOARD=$(call ws_to_under,$(call strip_quotes,$(call tolower,$(CONFIG_MAINBOARD_PART_NUMBER)))) +else + BOARD=$(CONFIG_MAINBOARD_DEPTHCHARGE) endif #TODO: Figure out version endif From 10c8ad8d78e6d0117d34668015620a1d94ca4021 Mon Sep 17 00:00:00 2001 From: Arthur Heymans Date: Tue, 12 Nov 2019 11:27:34 +0100 Subject: [PATCH 0156/1242] nb/intel/i440bx: Remove unnecessary __SIMPLE_DEVICE__ This file is only included in romstage. Change-Id: Ib9ee6e88e7a6ef81034de608232a05e92a16d5f4 Signed-off-by: Arthur Heymans Reviewed-on: https://review.coreboot.org/c/coreboot/+/36773 Tested-by: build bot (Jenkins) Reviewed-by: HAOUAS Elyes --- src/northbridge/intel/i440bx/memmap.c | 2 -- 1 file changed, 2 deletions(-) diff --git a/src/northbridge/intel/i440bx/memmap.c b/src/northbridge/intel/i440bx/memmap.c index d260af6f32..5c47ed0608 100644 --- a/src/northbridge/intel/i440bx/memmap.c +++ b/src/northbridge/intel/i440bx/memmap.c @@ -13,8 +13,6 @@ * GNU General Public License for more details. */ -#define __SIMPLE_DEVICE__ - #include #include #include From ae695757f43a5a730e16132ab830d76c10ba8daf Mon Sep 17 00:00:00 2001 From: Subrata Banik Date: Tue, 12 Nov 2019 12:47:43 +0530 Subject: [PATCH 0157/1242] soc/intel/tigerlake: Include few more Tigerlake device IDs This patch performs below operations 1. Add few more MCH, ESPI and IGD IDs 2. Remove TGL-H IDs 3. Rename existing as per applicable names 4. Remove TODO from report_platform.c file 5. Include TGL IDs into report_platform.c file Change-Id: I7bb3334d0fe8ba72e394d1a63b3a73840b4eaf2f Signed-off-by: Subrata Banik Reviewed-on: https://review.coreboot.org/c/coreboot/+/36768 Tested-by: build bot (Jenkins) Reviewed-by: Maulik V Vaghela --- src/include/device/pci_ids.h | 44 +++++++++++-- .../intel/common/block/graphics/graphics.c | 8 +-- src/soc/intel/common/block/lpc/lpc.c | 33 +++++++++- .../common/block/systemagent/systemagent.c | 1 + .../tigerlake/bootblock/report_platform.c | 66 ++++++++++++++++++- 5 files changed, 138 insertions(+), 14 deletions(-) diff --git a/src/include/device/pci_ids.h b/src/include/device/pci_ids.h index 4d21f5b045..70cf3aa339 100644 --- a/src/include/device/pci_ids.h +++ b/src/include/device/pci_ids.h @@ -2767,7 +2767,38 @@ #define PCI_DEVICE_ID_INTEL_CMP_PREMIUM_U_LPC 0x0284 #define PCI_DEVICE_ID_INTEL_CMP_BASE_U_LPC 0x0285 #define PCI_DEVICE_ID_INTEL_CMP_SUPER_Y_LPC 0x0286 -#define PCI_DEVICE_ID_INTEL_TGL_ESPI 0xA083 +#define PCI_DEVICE_ID_INTEL_TGP_ESPI_0 0xA080 +#define PCI_DEVICE_ID_INTEL_TGP_SUPER_U_ESPI 0xA081 +#define PCI_DEVICE_ID_INTEL_TGP_PREMIUM_U_ESPI 0xA082 +#define PCI_DEVICE_ID_INTEL_TGP_BASE_U_ESPI 0xA083 +#define PCI_DEVICE_ID_INTEL_TGP_ESPI_1 0xA084 +#define PCI_DEVICE_ID_INTEL_TGP_ESPI_2 0xA085 +#define PCI_DEVICE_ID_INTEL_TGP_SUPER_Y_ESPI 0xA086 +#define PCI_DEVICE_ID_INTEL_TGP_PREMIUM_Y_ESPI 0xA087 +#define PCI_DEVICE_ID_INTEL_TGP_ESPI_3 0xA088 +#define PCI_DEVICE_ID_INTEL_TGP_ESPI_4 0xA089 +#define PCI_DEVICE_ID_INTEL_TGP_ESPI_5 0xA08A +#define PCI_DEVICE_ID_INTEL_TGP_ESPI_6 0xA08B +#define PCI_DEVICE_ID_INTEL_TGP_ESPI_7 0xA08C +#define PCI_DEVICE_ID_INTEL_TGP_ESPI_8 0xA08D +#define PCI_DEVICE_ID_INTEL_TGP_ESPI_9 0xA08E +#define PCI_DEVICE_ID_INTEL_TGP_ESPI_10 0xA08F +#define PCI_DEVICE_ID_INTEL_TGP_ESPI_11 0xA090 +#define PCI_DEVICE_ID_INTEL_TGP_ESPI_12 0xA091 +#define PCI_DEVICE_ID_INTEL_TGP_ESPI_13 0xA092 +#define PCI_DEVICE_ID_INTEL_TGP_ESPI_14 0xA093 +#define PCI_DEVICE_ID_INTEL_TGP_ESPI_15 0xA094 +#define PCI_DEVICE_ID_INTEL_TGP_ESPI_16 0xA095 +#define PCI_DEVICE_ID_INTEL_TGP_ESPI_17 0xA096 +#define PCI_DEVICE_ID_INTEL_TGP_ESPI_18 0xA097 +#define PCI_DEVICE_ID_INTEL_TGP_ESPI_19 0xA098 +#define PCI_DEVICE_ID_INTEL_TGP_ESPI_20 0xA099 +#define PCI_DEVICE_ID_INTEL_TGP_ESPI_21 0xA09A +#define PCI_DEVICE_ID_INTEL_TGP_ESPI_22 0xA09B +#define PCI_DEVICE_ID_INTEL_TGP_ESPI_23 0xA09C +#define PCI_DEVICE_ID_INTEL_TGP_ESPI_24 0xA09D +#define PCI_DEVICE_ID_INTEL_TGP_ESPI_25 0xA09E +#define PCI_DEVICE_ID_INTEL_TGP_ESPI_26 0xA09F /* Intel PCIE device ids */ #define PCI_DEVICE_ID_INTEL_SPT_LP_PCIE_RP1 0x9d10 @@ -3229,10 +3260,10 @@ #define PCI_DEVICE_ID_INTEL_CML_GT1_H_2 0x9B22 #define PCI_DEVICE_ID_INTEL_CML_GT2_H_1 0x9B44 #define PCI_DEVICE_ID_INTEL_CML_GT2_H_2 0x9B42 -#define PCI_DEVICE_ID_INTEL_TGL_GT1 0X9A60 -#define PCI_DEVICE_ID_INTEL_TGL_GT2_UY 0X9A49 -#define PCI_DEVICE_ID_INTEL_TGL_GT2 0XFF20 -#define PCI_DEVICE_ID_INTEL_TGL_GT2_Y 0X9A40 +#define PCI_DEVICE_ID_INTEL_TGL_GT0 0x9A7F +#define PCI_DEVICE_ID_INTEL_TGL_GT2_ULT 0x9A49 +#define PCI_DEVICE_ID_INTEL_TGL_GT3_ULT 0x9A52 +#define PCI_DEVICE_ID_INTEL_TGL_GT2_ULX 0x9A40 /* Intel Northbridge Ids */ #define PCI_DEVICE_ID_INTEL_APL_NB 0x5af0 @@ -3284,7 +3315,8 @@ #define PCI_DEVICE_ID_INTEL_CML_H 0x9B54 #define PCI_DEVICE_ID_INTEL_CML_H_8_2 0x9B44 #define PCI_DEVICE_ID_INTEL_TGL_ID_U 0x9A14 -#define PCI_DEVICE_ID_INTEL_TGL_ID_Y 0x9A12 +#define PCI_DEVICE_ID_INTEL_TGL_ID_U_1 0x9A12 +#define PCI_DEVICE_ID_INTEL_TGL_ID_Y 0x9A10 /* Intel SMBUS device Ids */ #define PCI_DEVICE_ID_INTEL_SPT_LP_SMBUS 0x9d23 diff --git a/src/soc/intel/common/block/graphics/graphics.c b/src/soc/intel/common/block/graphics/graphics.c index 4efa60f5d2..df838c0c88 100644 --- a/src/soc/intel/common/block/graphics/graphics.c +++ b/src/soc/intel/common/block/graphics/graphics.c @@ -207,10 +207,10 @@ static const unsigned short pci_device_ids[] = { PCI_DEVICE_ID_INTEL_CML_GT1_H_2, PCI_DEVICE_ID_INTEL_CML_GT2_H_1, PCI_DEVICE_ID_INTEL_CML_GT2_H_2, - PCI_DEVICE_ID_INTEL_TGL_GT1, - PCI_DEVICE_ID_INTEL_TGL_GT2_UY, - PCI_DEVICE_ID_INTEL_TGL_GT2, - PCI_DEVICE_ID_INTEL_TGL_GT2_Y, + PCI_DEVICE_ID_INTEL_TGL_GT0, + PCI_DEVICE_ID_INTEL_TGL_GT2_ULT, + PCI_DEVICE_ID_INTEL_TGL_GT2_ULX, + PCI_DEVICE_ID_INTEL_TGL_GT3_ULT, 0, }; diff --git a/src/soc/intel/common/block/lpc/lpc.c b/src/soc/intel/common/block/lpc/lpc.c index c2b51bec9b..249e6d6256 100644 --- a/src/soc/intel/common/block/lpc/lpc.c +++ b/src/soc/intel/common/block/lpc/lpc.c @@ -190,7 +190,38 @@ static const unsigned short pci_device_ids[] = { PCI_DEVICE_ID_INTEL_CMP_PREMIUM_U_LPC, PCI_DEVICE_ID_INTEL_CMP_BASE_U_LPC, PCI_DEVICE_ID_INTEL_CMP_SUPER_Y_LPC, - PCI_DEVICE_ID_INTEL_TGL_ESPI, + PCI_DEVICE_ID_INTEL_TGP_ESPI_0, + PCI_DEVICE_ID_INTEL_TGP_SUPER_U_ESPI, + PCI_DEVICE_ID_INTEL_TGP_PREMIUM_U_ESPI, + PCI_DEVICE_ID_INTEL_TGP_BASE_U_ESPI, + PCI_DEVICE_ID_INTEL_TGP_ESPI_1, + PCI_DEVICE_ID_INTEL_TGP_ESPI_2, + PCI_DEVICE_ID_INTEL_TGP_SUPER_Y_ESPI, + PCI_DEVICE_ID_INTEL_TGP_PREMIUM_Y_ESPI, + PCI_DEVICE_ID_INTEL_TGP_ESPI_3, + PCI_DEVICE_ID_INTEL_TGP_ESPI_4, + PCI_DEVICE_ID_INTEL_TGP_ESPI_5, + PCI_DEVICE_ID_INTEL_TGP_ESPI_6, + PCI_DEVICE_ID_INTEL_TGP_ESPI_7, + PCI_DEVICE_ID_INTEL_TGP_ESPI_8, + PCI_DEVICE_ID_INTEL_TGP_ESPI_9, + PCI_DEVICE_ID_INTEL_TGP_ESPI_10, + PCI_DEVICE_ID_INTEL_TGP_ESPI_11, + PCI_DEVICE_ID_INTEL_TGP_ESPI_12, + PCI_DEVICE_ID_INTEL_TGP_ESPI_13, + PCI_DEVICE_ID_INTEL_TGP_ESPI_14, + PCI_DEVICE_ID_INTEL_TGP_ESPI_15, + PCI_DEVICE_ID_INTEL_TGP_ESPI_16, + PCI_DEVICE_ID_INTEL_TGP_ESPI_17, + PCI_DEVICE_ID_INTEL_TGP_ESPI_18, + PCI_DEVICE_ID_INTEL_TGP_ESPI_19, + PCI_DEVICE_ID_INTEL_TGP_ESPI_20, + PCI_DEVICE_ID_INTEL_TGP_ESPI_21, + PCI_DEVICE_ID_INTEL_TGP_ESPI_22, + PCI_DEVICE_ID_INTEL_TGP_ESPI_23, + PCI_DEVICE_ID_INTEL_TGP_ESPI_24, + PCI_DEVICE_ID_INTEL_TGP_ESPI_25, + PCI_DEVICE_ID_INTEL_TGP_ESPI_26, 0 }; diff --git a/src/soc/intel/common/block/systemagent/systemagent.c b/src/soc/intel/common/block/systemagent/systemagent.c index 7ad565d8e8..5f7d5af82c 100644 --- a/src/soc/intel/common/block/systemagent/systemagent.c +++ b/src/soc/intel/common/block/systemagent/systemagent.c @@ -363,6 +363,7 @@ static const unsigned short systemagent_ids[] = { PCI_DEVICE_ID_INTEL_CML_H, PCI_DEVICE_ID_INTEL_CML_H_8_2, PCI_DEVICE_ID_INTEL_TGL_ID_U, + PCI_DEVICE_ID_INTEL_TGL_ID_U_1, PCI_DEVICE_ID_INTEL_TGL_ID_Y, 0 }; diff --git a/src/soc/intel/tigerlake/bootblock/report_platform.c b/src/soc/intel/tigerlake/bootblock/report_platform.c index 6a58ea7c97..41061ee03b 100644 --- a/src/soc/intel/tigerlake/bootblock/report_platform.c +++ b/src/soc/intel/tigerlake/bootblock/report_platform.c @@ -33,9 +33,69 @@ #define BIOS_SIGN_ID 0x8B -/* - * TODO: Add TGL specific CPU/SA/PCH IDs here - */ +static struct { + u32 cpuid; + const char *name; +} cpu_table[] = { + { CPUID_TIGERLAKE_A0, "Tigerlake A0" }, +}; + +static struct { + u16 mchid; + const char *name; +} mch_table[] = { + { PCI_DEVICE_ID_INTEL_TGL_ID_U, "Tigerlake-U-4-2" }, + { PCI_DEVICE_ID_INTEL_TGL_ID_U_1, "Tigerlake-U-4-3e" }, + { PCI_DEVICE_ID_INTEL_TGL_ID_Y, "Tigerlake-Y-4-2" }, +}; + +static struct { + u16 espiid; + const char *name; +} pch_table[] = { + { PCI_DEVICE_ID_INTEL_TGP_ESPI_0, "Tigerlake-Base SKU" }, + { PCI_DEVICE_ID_INTEL_TGP_SUPER_U_ESPI, "Tigerlake-U Super SKU" }, + { PCI_DEVICE_ID_INTEL_TGP_PREMIUM_U_ESPI, "Tigerlake-U Premium SKU" }, + { PCI_DEVICE_ID_INTEL_TGP_BASE_U_ESPI, "Tigerlake-U Base SKU" }, + { PCI_DEVICE_ID_INTEL_TGP_ESPI_1, "Tigerlake-Base SKU" }, + { PCI_DEVICE_ID_INTEL_TGP_ESPI_2, "Tigerlake-Base SKU" }, + { PCI_DEVICE_ID_INTEL_TGP_SUPER_Y_ESPI, "Tigerlake-Y Super SKU" }, + { PCI_DEVICE_ID_INTEL_TGP_PREMIUM_Y_ESPI, "Tigerlake-Y Premium SKU" }, + { PCI_DEVICE_ID_INTEL_TGP_ESPI_3, "Tigerlake-Base SKU" }, + { PCI_DEVICE_ID_INTEL_TGP_ESPI_4, "Tigerlake-Base SKU" }, + { PCI_DEVICE_ID_INTEL_TGP_ESPI_5, "Tigerlake-Base SKU" }, + { PCI_DEVICE_ID_INTEL_TGP_ESPI_6, "Tigerlake-Base SKU" }, + { PCI_DEVICE_ID_INTEL_TGP_ESPI_7, "Tigerlake-Base SKU" }, + { PCI_DEVICE_ID_INTEL_TGP_ESPI_8, "Tigerlake-Base SKU" }, + { PCI_DEVICE_ID_INTEL_TGP_ESPI_9, "Tigerlake-Base SKU" }, + { PCI_DEVICE_ID_INTEL_TGP_ESPI_10, "Tigerlake-Base SKU" }, + { PCI_DEVICE_ID_INTEL_TGP_ESPI_11, "Tigerlake-Base SKU" }, + { PCI_DEVICE_ID_INTEL_TGP_ESPI_12, "Tigerlake-Base SKU" }, + { PCI_DEVICE_ID_INTEL_TGP_ESPI_13, "Tigerlake-Base SKU" }, + { PCI_DEVICE_ID_INTEL_TGP_ESPI_14, "Tigerlake-Base SKU" }, + { PCI_DEVICE_ID_INTEL_TGP_ESPI_15, "Tigerlake-Base SKU" }, + { PCI_DEVICE_ID_INTEL_TGP_ESPI_16, "Tigerlake-Base SKU" }, + { PCI_DEVICE_ID_INTEL_TGP_ESPI_17, "Tigerlake-Base SKU" }, + { PCI_DEVICE_ID_INTEL_TGP_ESPI_18, "Tigerlake-Base SKU" }, + { PCI_DEVICE_ID_INTEL_TGP_ESPI_19, "Tigerlake-Base SKU" }, + { PCI_DEVICE_ID_INTEL_TGP_ESPI_20, "Tigerlake-Base SKU" }, + { PCI_DEVICE_ID_INTEL_TGP_ESPI_21, "Tigerlake-Base SKU" }, + { PCI_DEVICE_ID_INTEL_TGP_ESPI_22, "Tigerlake-Base SKU" }, + { PCI_DEVICE_ID_INTEL_TGP_ESPI_23, "Tigerlake-Base SKU" }, + { PCI_DEVICE_ID_INTEL_TGP_ESPI_24, "Tigerlake-Base SKU" }, + { PCI_DEVICE_ID_INTEL_TGP_ESPI_25, "Tigerlake-Base SKU" }, + { PCI_DEVICE_ID_INTEL_TGP_ESPI_26, "Tigerlake-Base SKU" }, +}; + +static struct { + u16 igdid; + const char *name; +} igd_table[] = { + { PCI_DEVICE_ID_INTEL_TGL_GT0, "Tigerlake U GT0" }, + { PCI_DEVICE_ID_INTEL_TGL_GT2_ULT, "Tigerlake U GT2" }, + { PCI_DEVICE_ID_INTEL_TGL_GT2_ULX, "Tigerlake Y GT2" }, + { PCI_DEVICE_ID_INTEL_TGL_GT3_ULT, "Tigerlake U GT3" }, +}; static inline uint8_t get_dev_revision(pci_devfn_t dev) { From 571b14ef2374599888ff4e38c19522a081adefde Mon Sep 17 00:00:00 2001 From: Wisley Chen Date: Fri, 8 Nov 2019 13:51:31 +0800 Subject: [PATCH 0158/1242] /mb/google/hatch/var/dratini: Add new memory support 1. ram id 8: 16G 2666 2 bank groups memory 2. ram id 9: 16G 3200 4 bank groups memory BUG=b:142762387 TEST=boot with memory (KAAG165WA-BCT/H5ANAG6NCMR-XNC) Change-Id: Ic63d911458b59de11c12ce776f6f7d04b1eb3b6c Signed-off-by: Wisley Chen Reviewed-on: https://review.coreboot.org/c/coreboot/+/36667 Reviewed-by: Patrick Georgi Reviewed-by: Paul Fagerburg Tested-by: build bot (Jenkins) --- .../google/hatch/variants/dratini/Makefile.inc | 18 ++++++++++-------- 1 file changed, 10 insertions(+), 8 deletions(-) diff --git a/src/mainboard/google/hatch/variants/dratini/Makefile.inc b/src/mainboard/google/hatch/variants/dratini/Makefile.inc index 8b7e3d1014..4ed09c9a76 100644 --- a/src/mainboard/google/hatch/variants/dratini/Makefile.inc +++ b/src/mainboard/google/hatch/variants/dratini/Makefile.inc @@ -12,14 +12,16 @@ ## GNU General Public License for more details. ## -SPD_SOURCES = 4G_2400 # 0b000 -SPD_SOURCES += empty_ddr4 # 0b001 -SPD_SOURCES += 8G_2400 # 0b010 -SPD_SOURCES += 8G_2666 # 0b011 -SPD_SOURCES += 16G_2400 # 0b100 -SPD_SOURCES += 16G_2666 # 0b101 -SPD_SOURCES += 8G_3200 # 0b110 -SPD_SOURCES += 16G_3200 # 0b111 +SPD_SOURCES = 4G_2400 # 0b0000 +SPD_SOURCES += empty_ddr4 # 0b0001 +SPD_SOURCES += 8G_2400 # 0b0010 +SPD_SOURCES += 8G_2666 # 0b0011 +SPD_SOURCES += 16G_2400 # 0b0100 +SPD_SOURCES += 16G_2666 # 0b0101 +SPD_SOURCES += 8G_3200 # 0b0110 +SPD_SOURCES += 16G_3200 # 0b0111 +SPD_SOURCES += 16G_2666_2bg # 0b1000 +SPD_SOURCES += 16G_3200_4bg # 0b1001 bootblock-y += gpio.c ramstage-y += gpio.c From 949ff57bcaa3bf7e196b36c90124989a36ba93a5 Mon Sep 17 00:00:00 2001 From: Wisley Chen Date: Wed, 13 Nov 2019 19:02:19 +0800 Subject: [PATCH 0159/1242] /mb/google/hatch: clean manufacturing information in spd Clean the vendor/manufacturing information in 16G_3200_4bg spd to become generic spd. BUG=None TEST=emerge-hatch coreboot Change-Id: I163dc4631a6b71efd36c75cfe1fc759040113387 Signed-off-by: Wisley Chen Reviewed-on: https://review.coreboot.org/c/coreboot/+/36810 Reviewed-by: Paul Fagerburg Tested-by: build bot (Jenkins) --- .../google/hatch/spd/16G_3200_4bg.spd.hex | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/src/mainboard/google/hatch/spd/16G_3200_4bg.spd.hex b/src/mainboard/google/hatch/spd/16G_3200_4bg.spd.hex index ad044543f2..1605947d00 100644 --- a/src/mainboard/google/hatch/spd/16G_3200_4bg.spd.hex +++ b/src/mainboard/google/hatch/spd/16G_3200_4bg.spd.hex @@ -13,14 +13,14 @@ 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 7D 21 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -80 AD 01 00 00 00 00 00 00 48 4D 41 41 31 47 53 -36 43 4D 52 36 4E 2D 58 4E 20 20 20 20 00 80 AD -FF 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 From 399b6c11efaff64cb86a879dc9047a97538e790f Mon Sep 17 00:00:00 2001 From: Arthur Heymans Date: Mon, 11 Nov 2019 19:12:57 +0100 Subject: [PATCH 0160/1242] sb/intel/i82801gx: Add common early code Remove some of the code duplication on i82801gx. x4x boards are left untouched for now since that northbridge also supports i82801jx. The order of some things has changed: - on i945 early_ich7_init is now done before the raminit - enabling the IOAPIC is done before the raminit Change-Id: Ie39549938891e17667a8819b49a78b9c71c8ec9e Signed-off-by: Arthur Heymans Reviewed-on: https://review.coreboot.org/c/coreboot/+/36754 Reviewed-by: Angel Pons Reviewed-by: HAOUAS Elyes Tested-by: build bot (Jenkins) --- src/mainboard/apple/macbook21/romstage.c | 36 +------------ src/mainboard/asus/p5gc-mx/romstage.c | 37 +------------ src/mainboard/getac/p470/romstage.c | 36 +------------ .../gigabyte/ga-945gcm-s2l/romstage.c | 36 +------------ src/mainboard/ibase/mb899/romstage.c | 36 +------------ src/mainboard/intel/d945gclf/romstage.c | 36 +------------ src/mainboard/kontron/986lcd-m/romstage.c | 37 +------------ src/mainboard/lenovo/t60/romstage.c | 46 ++-------------- src/mainboard/lenovo/x60/romstage.c | 41 ++------------ src/mainboard/roda/rk886ex/romstage.c | 36 +------------ src/northbridge/intel/i945/early_init.c | 16 ------ src/northbridge/intel/pineview/early_init.c | 18 ------- src/northbridge/intel/pineview/romstage.c | 11 +--- src/southbridge/intel/i82801gx/early_init.c | 53 +++++++++++++++++++ src/southbridge/intel/i82801gx/i82801gx.h | 1 + 15 files changed, 71 insertions(+), 405 deletions(-) diff --git a/src/mainboard/apple/macbook21/romstage.c b/src/mainboard/apple/macbook21/romstage.c index aced71ce6a..41c0e9f384 100644 --- a/src/mainboard/apple/macbook21/romstage.c +++ b/src/mainboard/apple/macbook21/romstage.c @@ -48,9 +48,6 @@ static void rcba_config(void) RCBA16(D28IR) = 0x3201; RCBA16(D27IR) = 0x3216; - /* Enable IOAPIC */ - RCBA8(OIC) = 0x03; - /* Disable unused devices */ RCBA32(FD) |= FD_INTLAN; @@ -61,35 +58,6 @@ static void rcba_config(void) RCBA32(0x1e98) = 0x000c0801; } -static void early_ich7_init(void) -{ - uint8_t reg8; - uint32_t reg32; - - /* program secondary mlt XXX byte? */ - pci_write_config8(PCI_DEV(0, 0x1e, 0), SMLT, 0x20); - - /* reset rtc power status */ - reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), GEN_PMCON_3); - reg8 &= ~RTC_BATTERY_DEAD; - pci_write_config8(PCI_DEV(0, 0x1f, 0), GEN_PMCON_3, reg8); - - /* usb transient disconnect */ - reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xad); - reg8 |= (3 << 0); - pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xad, reg8); - - reg32 = pci_read_config32(PCI_DEV(0, 0x1d, 7), 0xfc); - reg32 |= (1 << 29) | (1 << 17); - pci_write_config32(PCI_DEV(0, 0x1d, 7), 0xfc, reg32); - - reg32 = pci_read_config32(PCI_DEV(0, 0x1d, 7), 0xdc); - reg32 |= (1 << 31) | (1 << 27); - pci_write_config32(PCI_DEV(0, 0x1d, 7), 0xdc, reg32); - - ich7_setup_cir(); -} - void mainboard_romstage_entry(void) { int s3resume = 0; @@ -111,6 +79,7 @@ void mainboard_romstage_entry(void) /* Perform some early chipset initialization required * before RAM initialization can work */ + i82801gx_early_init(); i945_early_initialization(); s3resume = southbridge_detect_s3_resume(); @@ -123,9 +92,6 @@ void mainboard_romstage_entry(void) sdram_initialize(s3resume ? 2 : 0, spd_addrmap); - /* Perform some initialization that must run before stage2 */ - early_ich7_init(); - /* This should probably go away. Until now it is required * and mainboard specific */ diff --git a/src/mainboard/asus/p5gc-mx/romstage.c b/src/mainboard/asus/p5gc-mx/romstage.c index 3287b76416..0cc38a03e8 100644 --- a/src/mainboard/asus/p5gc-mx/romstage.c +++ b/src/mainboard/asus/p5gc-mx/romstage.c @@ -98,42 +98,9 @@ static u8 msr_get_fsb(void) static void rcba_config(void) { - /* Enable IOAPIC */ - RCBA8(OIC) = 0x03; - /* Enable PCIe Root Port Clock Gate */ RCBA32(CG) = 0x00000001; } - -static void early_ich7_init(void) -{ - uint8_t reg8; - uint32_t reg32; - - // program secondary mlt XXX byte? - pci_write_config8(PCI_DEV(0, 0x1e, 0), SMLT, 0x20); - - // reset rtc power status - reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), GEN_PMCON_3); - reg8 &= ~RTC_BATTERY_DEAD; - pci_write_config8(PCI_DEV(0, 0x1f, 0), GEN_PMCON_3, reg8); - - // usb transient disconnect - reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xad); - reg8 |= (3 << 0); - pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xad, reg8); - - reg32 = pci_read_config32(PCI_DEV(0, 0x1d, 7), 0xfc); - reg32 |= (1 << 29) | (1 << 17); - pci_write_config32(PCI_DEV(0, 0x1d, 7), 0xfc, reg32); - - reg32 = pci_read_config32(PCI_DEV(0, 0x1d, 7), 0xdc); - reg32 |= (1 << 31) | (1 << 27); - pci_write_config32(PCI_DEV(0, 0x1d, 7), 0xdc, reg32); - - ich7_setup_cir(); -} - void mainboard_romstage_entry(void) { int s3resume = 0, boot_mode = 0; @@ -157,6 +124,7 @@ void mainboard_romstage_entry(void) /* Perform some early chipset initialization required * before RAM initialization can work */ + i82801gx_early_init(); i945_early_initialization(); s3resume = southbridge_detect_s3_resume(); @@ -179,9 +147,6 @@ void mainboard_romstage_entry(void) sdram_initialize(s3resume ? 2 : boot_mode, NULL); - /* Perform some initialization that must run before stage2 */ - early_ich7_init(); - /* This should probably go away. Until now it is required * and mainboard specific */ diff --git a/src/mainboard/getac/p470/romstage.c b/src/mainboard/getac/p470/romstage.c index e27194aab9..8c41190b02 100644 --- a/src/mainboard/getac/p470/romstage.c +++ b/src/mainboard/getac/p470/romstage.c @@ -143,9 +143,6 @@ static void rcba_config(void) RCBA16(D28IR) = 0x3201; RCBA16(D27IR) = 0x3216; - /* Enable IOAPIC */ - RCBA8(OIC) = 0x03; - /* Disable unused devices */ RCBA32(FD) |= FD_INTLAN; @@ -162,35 +159,6 @@ static void rcba_config(void) RCBA32(0x1e98) = 0x000c0801; } -static void early_ich7_init(void) -{ - uint8_t reg8; - uint32_t reg32; - - // program secondary mlt XXX byte? - pci_write_config8(PCI_DEV(0, 0x1e, 0), SMLT, 0x20); - - // reset rtc power status - reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), GEN_PMCON_3); - reg8 &= ~RTC_BATTERY_DEAD; - pci_write_config8(PCI_DEV(0, 0x1f, 0), GEN_PMCON_3, reg8); - - // usb transient disconnect - reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xad); - reg8 |= (3 << 0); - pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xad, reg8); - - reg32 = pci_read_config32(PCI_DEV(0, 0x1d, 7), 0xfc); - reg32 |= (1 << 29) | (1 << 17); - pci_write_config32(PCI_DEV(0, 0x1d, 7), 0xfc, reg32); - - reg32 = pci_read_config32(PCI_DEV(0, 0x1d, 7), 0xdc); - reg32 |= (1 << 31) | (1 << 27); - pci_write_config32(PCI_DEV(0, 0x1d, 7), 0xdc, reg32); - - ich7_setup_cir(); -} - void mainboard_romstage_entry(void) { int s3resume = 0; @@ -211,6 +179,7 @@ void mainboard_romstage_entry(void) /* Perform some early chipset initialization required * before RAM initialization can work */ + i82801gx_early_init(); i945_early_initialization(); setup_special_ich7_gpios(); @@ -225,9 +194,6 @@ void mainboard_romstage_entry(void) sdram_initialize(s3resume ? 2 : 0, NULL); - /* Perform some initialization that must run before stage2 */ - early_ich7_init(); - /* This should probably go away. Until now it is required * and mainboard specific */ diff --git a/src/mainboard/gigabyte/ga-945gcm-s2l/romstage.c b/src/mainboard/gigabyte/ga-945gcm-s2l/romstage.c index 9a9e9473e6..cd1345148d 100644 --- a/src/mainboard/gigabyte/ga-945gcm-s2l/romstage.c +++ b/src/mainboard/gigabyte/ga-945gcm-s2l/romstage.c @@ -58,42 +58,10 @@ static void setup_sio(void) static void rcba_config(void) { - /* Enable IOAPIC */ - RCBA8(OIC) = 0x03; - /* Enable PCIe Root Port Clock Gate */ RCBA32(CG) = 0x00000001; } -static void early_ich7_init(void) -{ - uint8_t reg8; - uint32_t reg32; - - // program secondary mlt XXX byte? - pci_write_config8(PCI_DEV(0, 0x1e, 0), SMLT, 0x20); - - // reset rtc power status - reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), GEN_PMCON_3); - reg8 &= ~RTC_BATTERY_DEAD; - pci_write_config8(PCI_DEV(0, 0x1f, 0), GEN_PMCON_3, reg8); - - // usb transient disconnect - reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xad); - reg8 |= (3 << 0); - pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xad, reg8); - - reg32 = pci_read_config32(PCI_DEV(0, 0x1d, 7), 0xfc); - reg32 |= (1 << 29) | (1 << 17); - pci_write_config32(PCI_DEV(0, 0x1d, 7), 0xfc, reg32); - - reg32 = pci_read_config32(PCI_DEV(0, 0x1d, 7), 0xdc); - reg32 |= (1 << 31) | (1 << 27); - pci_write_config32(PCI_DEV(0, 0x1d, 7), 0xdc, reg32); - - ich7_setup_cir(); -} - void mainboard_romstage_entry(void) { int s3resume = 0, boot_mode = 0; @@ -118,6 +86,7 @@ void mainboard_romstage_entry(void) /* Perform some early chipset initialization required * before RAM initialization can work */ + i82801gx_early_init(); i945_early_initialization(); s3resume = southbridge_detect_s3_resume(); @@ -130,9 +99,6 @@ void mainboard_romstage_entry(void) sdram_initialize(s3resume ? 2 : boot_mode, NULL); - /* Perform some initialization that must run before stage2 */ - early_ich7_init(); - /* This should probably go away. Until now it is required * and mainboard specific */ diff --git a/src/mainboard/ibase/mb899/romstage.c b/src/mainboard/ibase/mb899/romstage.c index fd258af554..47e28a8dc1 100644 --- a/src/mainboard/ibase/mb899/romstage.c +++ b/src/mainboard/ibase/mb899/romstage.c @@ -120,42 +120,10 @@ static void rcba_config(void) RCBA16(D28IR) = 0x3201; RCBA16(D27IR) = 0x0146; - /* Enable IOAPIC */ - RCBA8(OIC) = 0x03; - /* Enable PCIe Root Port Clock Gate */ // RCBA32(0x341c) = 0x00000001; } -static void early_ich7_init(void) -{ - uint8_t reg8; - uint32_t reg32; - - // program secondary mlt XXX byte? - pci_write_config8(PCI_DEV(0, 0x1e, 0), SMLT, 0x20); - - // reset rtc power status - reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), GEN_PMCON_3); - reg8 &= ~RTC_BATTERY_DEAD; - pci_write_config8(PCI_DEV(0, 0x1f, 0), GEN_PMCON_3, reg8); - - // usb transient disconnect - reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xad); - reg8 |= (3 << 0); - pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xad, reg8); - - reg32 = pci_read_config32(PCI_DEV(0, 0x1d, 7), 0xfc); - reg32 |= (1 << 29) | (1 << 17); - pci_write_config32(PCI_DEV(0, 0x1d, 7), 0xfc, reg32); - - reg32 = pci_read_config32(PCI_DEV(0, 0x1d, 7), 0xdc); - reg32 |= (1 << 31) | (1 << 27); - pci_write_config32(PCI_DEV(0, 0x1d, 7), 0xdc, reg32); - - ich7_setup_cir(); -} - void mainboard_romstage_entry(void) { int s3resume = 0; @@ -175,6 +143,7 @@ void mainboard_romstage_entry(void) /* Perform some early chipset initialization required * before RAM initialization can work */ + i82801gx_early_init(); i945_early_initialization(); s3resume = southbridge_detect_s3_resume(); @@ -187,9 +156,6 @@ void mainboard_romstage_entry(void) sdram_initialize(s3resume ? 2 : 0, NULL); - /* Perform some initialization that must run before stage2 */ - early_ich7_init(); - /* This should probably go away. Until now it is required * and mainboard specific */ diff --git a/src/mainboard/intel/d945gclf/romstage.c b/src/mainboard/intel/d945gclf/romstage.c index ba01379548..ada6e61c00 100644 --- a/src/mainboard/intel/d945gclf/romstage.c +++ b/src/mainboard/intel/d945gclf/romstage.c @@ -40,9 +40,6 @@ static void rcba_config(void) RCBA16(D28IR) = 0x3201; RCBA16(D27IR) = 0x0146; - /* Enable IOAPIC */ - RCBA8(OIC) = 0x03; - /* Disable unused devices */ RCBA32(FD) |= FD_INTLAN; @@ -50,35 +47,6 @@ static void rcba_config(void) // RCBA32(0x341c) = 0x00000001; } -static void early_ich7_init(void) -{ - uint8_t reg8; - uint32_t reg32; - - // program secondary mlt XXX byte? - pci_write_config8(PCI_DEV(0, 0x1e, 0), SMLT, 0x20); - - // reset rtc power status - reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), GEN_PMCON_3); - reg8 &= ~RTC_BATTERY_DEAD; - pci_write_config8(PCI_DEV(0, 0x1f, 0), GEN_PMCON_3, reg8); - - // usb transient disconnect - reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xad); - reg8 |= (3 << 0); - pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xad, reg8); - - reg32 = pci_read_config32(PCI_DEV(0, 0x1d, 7), 0xfc); - reg32 |= (1 << 29) | (1 << 17); - pci_write_config32(PCI_DEV(0, 0x1d, 7), 0xfc, reg32); - - reg32 = pci_read_config32(PCI_DEV(0, 0x1d, 7), 0xdc); - reg32 |= (1 << 31) | (1 << 27); - pci_write_config32(PCI_DEV(0, 0x1d, 7), 0xdc, reg32); - - ich7_setup_cir(); -} - void mainboard_romstage_entry(void) { int s3resume = 0, boot_mode = 0; @@ -101,6 +69,7 @@ void mainboard_romstage_entry(void) /* Perform some early chipset initialization required * before RAM initialization can work */ + i82801gx_early_init(); i945_early_initialization(); s3resume = southbridge_detect_s3_resume(); @@ -113,9 +82,6 @@ void mainboard_romstage_entry(void) sdram_initialize(s3resume ? 2 : boot_mode, NULL); - /* Perform some initialization that must run before stage2 */ - early_ich7_init(); - /* This should probably go away. Until now it is required * and mainboard specific */ diff --git a/src/mainboard/kontron/986lcd-m/romstage.c b/src/mainboard/kontron/986lcd-m/romstage.c index cb01046010..d67a60b1e8 100644 --- a/src/mainboard/kontron/986lcd-m/romstage.c +++ b/src/mainboard/kontron/986lcd-m/romstage.c @@ -165,40 +165,7 @@ static void rcba_config(void) RCBA16(D28IR) = 0x3210; RCBA16(D27IR) = 0x3210; - /* Enable IOAPIC */ - RCBA8(OIC) = 0x03; - /* Enable PCIe Root Port Clock Gate */ - -} - -static void early_ich7_init(void) -{ - uint8_t reg8; - uint32_t reg32; - - /* program secondary mlt XXX byte? */ - pci_write_config8(PCI_DEV(0, 0x1e, 0), SMLT, 0x20); - - /* reset rtc power status */ - reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), GEN_PMCON_3); - reg8 &= ~RTC_BATTERY_DEAD; - pci_write_config8(PCI_DEV(0, 0x1f, 0), GEN_PMCON_3, reg8); - - /* usb transient disconnect */ - reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xad); - reg8 |= (3 << 0); - pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xad, reg8); - - reg32 = pci_read_config32(PCI_DEV(0, 0x1d, 7), 0xfc); - reg32 |= (1 << 29) | (1 << 17); - pci_write_config32(PCI_DEV(0, 0x1d, 7), 0xfc, reg32); - - reg32 = pci_read_config32(PCI_DEV(0, 0x1d, 7), 0xdc); - reg32 |= (1 << 31) | (1 << 27); - pci_write_config32(PCI_DEV(0, 0x1d, 7), 0xdc, reg32); - - ich7_setup_cir(); } void mainboard_romstage_entry(void) @@ -221,6 +188,7 @@ void mainboard_romstage_entry(void) /* Perform some early chipset initialization required * before RAM initialization can work */ + i82801gx_early_init(); i945_early_initialization(); s3resume = southbridge_detect_s3_resume(); @@ -233,9 +201,6 @@ void mainboard_romstage_entry(void) sdram_initialize(s3resume ? 2 : 0, NULL); - /* Perform some initialization that must run before stage2 */ - early_ich7_init(); - /* This should probably go away. Until now it is required * and mainboard specific */ diff --git a/src/mainboard/lenovo/t60/romstage.c b/src/mainboard/lenovo/t60/romstage.c index ac78aae841..ab49e6e979 100644 --- a/src/mainboard/lenovo/t60/romstage.c +++ b/src/mainboard/lenovo/t60/romstage.c @@ -76,9 +76,6 @@ static void rcba_config(void) RCBA16(D28IR) = 0x7654; RCBA16(D27IR) = 0x0010; - /* Enable IOAPIC */ - RCBA8(OIC) = 0x03; - /* Disable unused devices */ RCBA32(FD) |= FD_INTLAN; @@ -89,35 +86,6 @@ static void rcba_config(void) RCBA64(IOTR3) = 0x000200f0000c0801ULL; } -static void early_ich7_init(void) -{ - uint8_t reg8; - uint32_t reg32; - - // program secondary mlt XXX byte? - pci_write_config8(PCI_DEV(0, 0x1e, 0), SMLT, 0x20); - - // reset rtc power status - reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), GEN_PMCON_3); - reg8 &= ~RTC_BATTERY_DEAD; - pci_write_config8(PCI_DEV(0, 0x1f, 0), GEN_PMCON_3, reg8); - - // usb transient disconnect - reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xad); - reg8 |= (3 << 0); - pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xad, reg8); - - reg32 = pci_read_config32(PCI_DEV(0, 0x1d, 7), 0xfc); - reg32 |= (1 << 29) | (1 << 17); - pci_write_config32(PCI_DEV(0, 0x1d, 7), 0xfc, reg32); - - reg32 = pci_read_config32(PCI_DEV(0, 0x1d, 7), 0xdc); - reg32 |= (1 << 31) | (1 << 27); - pci_write_config32(PCI_DEV(0, 0x1d, 7), 0xdc, reg32); - - ich7_setup_cir(); -} - void mainboard_romstage_entry(void) { int s3resume = 0; @@ -126,15 +94,13 @@ void mainboard_romstage_entry(void) enable_lapic(); + /* Set up GPIO's early since it is needed for dock init */ + i82801gx_setup_bars(); + setup_pch_gpios(&mainboard_gpio_map); + i82801gx_lpc_setup(); mb_lpc_decode(); - /* We want early GPIO setup, to be able to detect legacy I/O module */ - pci_write_config32(PCI_DEV(0, 0x1f, 0), GPIOBASE, DEFAULT_GPIOBASE | 1); - /* Enable GPIOs */ - pci_write_config8(PCI_DEV(0, 0x1f, 0), 0x4c /* GC */, 0x10); - setup_pch_gpios(&mainboard_gpio_map); - dock_err = dlpc_init(); /* We prefer Legacy I/O module over docking */ @@ -156,6 +122,7 @@ void mainboard_romstage_entry(void) /* Perform some early chipset initialization required * before RAM initialization can work */ + i82801gx_early_init(); i945_early_initialization(); s3resume = southbridge_detect_s3_resume(); @@ -168,9 +135,6 @@ void mainboard_romstage_entry(void) sdram_initialize(s3resume ? 2 : 0, spd_addrmap); - /* Perform some initialization that must run before stage2 */ - early_ich7_init(); - /* This should probably go away. Until now it is required * and mainboard specific */ diff --git a/src/mainboard/lenovo/x60/romstage.c b/src/mainboard/lenovo/x60/romstage.c index 1008bb0e22..6eeb2d12ba 100644 --- a/src/mainboard/lenovo/x60/romstage.c +++ b/src/mainboard/lenovo/x60/romstage.c @@ -77,9 +77,6 @@ static void rcba_config(void) RCBA16(D28IR) = 0x7654; RCBA16(D27IR) = 0x0010; - /* Enable IOAPIC */ - RCBA8(OIC) = 0x03; - /* Disable unused devices */ RCBA32(FD) |= FD_INTLAN; @@ -90,35 +87,6 @@ static void rcba_config(void) RCBA64(IOTR3) = 0x000200f0000c0801ULL; } -static void early_ich7_init(void) -{ - uint8_t reg8; - uint32_t reg32; - - // program secondary mlt XXX byte? - pci_write_config8(PCI_DEV(0, 0x1e, 0), SMLT, 0x20); - - // reset rtc power status - reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), GEN_PMCON_3); - reg8 &= ~RTC_BATTERY_DEAD; - pci_write_config8(PCI_DEV(0, 0x1f, 0), GEN_PMCON_3, reg8); - - // usb transient disconnect - reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xad); - reg8 |= (3 << 0); - pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xad, reg8); - - reg32 = pci_read_config32(PCI_DEV(0, 0x1d, 7), 0xfc); - reg32 |= (1 << 29) | (1 << 17); - pci_write_config32(PCI_DEV(0, 0x1d, 7), 0xfc, reg32); - - reg32 = pci_read_config32(PCI_DEV(0, 0x1d, 7), 0xdc); - reg32 |= (1 << 31) | (1 << 27); - pci_write_config32(PCI_DEV(0, 0x1d, 7), 0xdc, reg32); - - ich7_setup_cir(); -} - void mainboard_romstage_entry(void) { int s3resume = 0; @@ -126,9 +94,8 @@ void mainboard_romstage_entry(void) enable_lapic(); - /* Enable GPIOs */ - pci_write_config32(PCI_DEV(0, 0x1f, 0), GPIOBASE, DEFAULT_GPIOBASE | 1); - pci_write_config8(PCI_DEV(0, 0x1f, 0), 0x4c, 0x10); /* 0x4c == GC */ + /* Set up GPIO's early since it is needed for dock init */ + i82801gx_setup_bars(); setup_pch_gpios(&mainboard_gpio_map); i82801gx_lpc_setup(); @@ -161,6 +128,7 @@ void mainboard_romstage_entry(void) /* Perform some early chipset initialization required * before RAM initialization can work */ + i82801gx_early_init(); i945_early_initialization(); s3resume = southbridge_detect_s3_resume(); @@ -173,9 +141,6 @@ void mainboard_romstage_entry(void) sdram_initialize(s3resume ? 2 : 0, spd_addrmap); - /* Perform some initialization that must run before stage2 */ - early_ich7_init(); - /* This should probably go away. Until now it is required * and mainboard specific */ diff --git a/src/mainboard/roda/rk886ex/romstage.c b/src/mainboard/roda/rk886ex/romstage.c index 019ec1b733..f1a638dad1 100644 --- a/src/mainboard/roda/rk886ex/romstage.c +++ b/src/mainboard/roda/rk886ex/romstage.c @@ -108,9 +108,6 @@ static void rcba_config(void) RCBA16(D28IR) = 0x3201; RCBA16(D27IR) = 0x3216; - /* Enable IOAPIC */ - RCBA8(OIC) = 0x03; - /* Disable unused devices */ RCBA32(FD) |= FD_INTLAN; @@ -125,35 +122,6 @@ static void rcba_config(void) RCBA32(0x1e98) = 0x000c0801; } -static void early_ich7_init(void) -{ - uint8_t reg8; - uint32_t reg32; - - /* program secondary mlt XXX byte? */ - pci_write_config8(PCI_DEV(0, 0x1e, 0), SMLT, 0x20); - - /* reset rtc power status */ - reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), GEN_PMCON_3); - reg8 &= ~RTC_BATTERY_DEAD; - pci_write_config8(PCI_DEV(0, 0x1f, 0), GEN_PMCON_3, reg8); - - /* usb transient disconnect */ - reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xad); - reg8 |= (3 << 0); - pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xad, reg8); - - reg32 = pci_read_config32(PCI_DEV(0, 0x1d, 7), 0xfc); - reg32 |= (1 << 29) | (1 << 17); - pci_write_config32(PCI_DEV(0, 0x1d, 7), 0xfc, reg32); - - reg32 = pci_read_config32(PCI_DEV(0, 0x1d, 7), 0xdc); - reg32 |= (1 << 31) | (1 << 27); - pci_write_config32(PCI_DEV(0, 0x1d, 7), 0xdc, reg32); - - ich7_setup_cir(); -} - static void init_artec_dongle(void) { /* Enable 4MB decoding */ @@ -181,6 +149,7 @@ void mainboard_romstage_entry(void) /* Perform some early chipset initialization required * before RAM initialization can work */ + i82801gx_early_init(); i945_early_initialization(); /* This has to happen after i945_early_initialization() */ @@ -196,9 +165,6 @@ void mainboard_romstage_entry(void) sdram_initialize(s3resume ? 2 : 0, NULL); - /* Perform some initialization that must run before stage2 */ - early_ich7_init(); - /* This should probably go away. Until now it is required * and mainboard specific */ diff --git a/src/northbridge/intel/i945/early_init.c b/src/northbridge/intel/i945/early_init.c index a5bfe6f6a9..13dce61325 100644 --- a/src/northbridge/intel/i945/early_init.c +++ b/src/northbridge/intel/i945/early_init.c @@ -23,7 +23,6 @@ #include #include #include -#include #include #include "i945.h" @@ -156,21 +155,6 @@ static void i945_setup_bars(void) if (i945_silicon_revision() == 0) printk(BIOS_INFO, "Warning: i945 silicon revision A0 might not work correctly.\n"); - /* Setting up Southbridge. In the northbridge code. */ - printk(BIOS_DEBUG, "Setting up static southbridge registers..."); - - i82801gx_setup_bars(); - - setup_pch_gpios(&mainboard_gpio_map); - printk(BIOS_DEBUG, " done.\n"); - - printk(BIOS_DEBUG, "Disabling Watchdog reboot..."); - RCBA32(GCS) = RCBA32(GCS) | (1 << 5); /* No reset */ - outw((1 << 11), DEFAULT_PMBASE | 0x60 | 0x08); /* halt timer */ - outw((1 << 3), DEFAULT_PMBASE | 0x60 | 0x04); /* clear timeout */ - outw((1 << 1), DEFAULT_PMBASE | 0x60 | 0x06); /* clear 2nd timeout */ - printk(BIOS_DEBUG, " done.\n"); - printk(BIOS_DEBUG, "Setting up static northbridge registers..."); /* Set up all hardcoded northbridge BARs */ pci_write_config32(PCI_DEV(0, 0x00, 0), EPBAR, DEFAULT_EPBAR | 1); diff --git a/src/northbridge/intel/pineview/early_init.c b/src/northbridge/intel/pineview/early_init.c index 3a9df510b7..6698fa85e0 100644 --- a/src/northbridge/intel/pineview/early_init.c +++ b/src/northbridge/intel/pineview/early_init.c @@ -136,8 +136,6 @@ static void early_misc_setup(void) pci_write_config8(LPC, 0x8, 0x0); RCBA32(0x3410) = 0x00020465; - ich7_setup_cir(); - pci_write_config32(PCI_DEV(0, 0x1d, 0), 0xca, 0x1); pci_write_config32(PCI_DEV(0, 0x1d, 1), 0xca, 0x1); pci_write_config32(PCI_DEV(0, 0x1d, 2), 0xca, 0x1); @@ -156,22 +154,6 @@ static void early_misc_setup(void) static void pineview_setup_bars(void) { - /* Setting up Southbridge. In the northbridge code. */ - printk(BIOS_DEBUG, "Setting up static southbridge registers..."); - - i82801gx_setup_bars(); - - pci_write_config32(PCI_DEV(0, 0x1e, 0), 0x1b, 0x20); - printk(BIOS_DEBUG, " done.\n"); - - printk(BIOS_DEBUG, "Disabling Watchdog reboot..."); - RCBA32(GCS) = RCBA32(GCS) | (1 << 5); /* No reset */ - outw((1 << 11), DEFAULT_PMBASE | 0x60 | 0x08); /* halt timer */ - printk(BIOS_DEBUG, " done.\n"); - - /* Enable upper 128bytes of CMOS */ - RCBA32(0x3400) = (1 << 2); - printk(BIOS_DEBUG, "Setting up static northbridge registers..."); pci_write_config8(D0F0, 0x8, 0x69); diff --git a/src/northbridge/intel/pineview/romstage.c b/src/northbridge/intel/pineview/romstage.c index e60738ced5..e324c05327 100644 --- a/src/northbridge/intel/pineview/romstage.c +++ b/src/northbridge/intel/pineview/romstage.c @@ -24,7 +24,6 @@ #include #include #include -#include #include #include #include @@ -36,9 +35,6 @@ static void rcba_config(void) /* Set up virtual channel 0 */ RCBA32(0x0014) = 0x80000001; RCBA32(0x001c) = 0x03128010; - - /* Enable IOAPIC */ - RCBA8(OIC) = 0x03; } __weak void mb_pirq_setup(void) @@ -55,17 +51,12 @@ void mainboard_romstage_entry(void) enable_lapic(); - /* Enable GPIOs */ - pci_write_config32(LPC_DEV, GPIO_BASE, DEFAULT_GPIOBASE | 1); - pci_write_config8(LPC_DEV, GPIO_CNTL, 0x10); - - setup_pch_gpios(&mainboard_gpio_map); - enable_smbus(); /* Perform some early chipset initialization required * before RAM initialization can work */ + i82801gx_early_init(); pineview_early_initialization(); post_code(0x30); diff --git a/src/southbridge/intel/i82801gx/early_init.c b/src/southbridge/intel/i82801gx/early_init.c index 7f5f442333..0bd6198e2c 100644 --- a/src/southbridge/intel/i82801gx/early_init.c +++ b/src/southbridge/intel/i82801gx/early_init.c @@ -12,7 +12,10 @@ */ #include +#include #include +#include +#include #include "i82801gx.h" #include "chip.h" @@ -62,3 +65,53 @@ void i82801gx_setup_bars(void) pci_write_config32(d31f0, GPIOBASE, DEFAULT_GPIOBASE | 1); pci_write_config8(d31f0, GPIO_CNTL, GPIO_EN); } + +#define TCO_BASE 0x60 + +#if ENV_ROMSTAGE +void i82801gx_early_init(void) +{ + uint8_t reg8; + uint32_t reg32; + /* Setting up Southbridge. In the northbridge code. */ + printk(BIOS_DEBUG, "Setting up static southbridge registers..."); + i82801gx_setup_bars(); + + setup_pch_gpios(&mainboard_gpio_map); + printk(BIOS_DEBUG, " done.\n"); + + printk(BIOS_DEBUG, "Disabling Watchdog reboot..."); + RCBA32(GCS) = RCBA32(GCS) | (1 << 5); /* No reset */ + write_pmbase16(TCO_BASE + 0x8, (1 << 11)); /* halt timer */ + write_pmbase16(TCO_BASE + 0x4, (1 << 3)); /* clear timeout */ + write_pmbase16(TCO_BASE + 0x6, (1 << 1)); /* clear 2nd timeout */ + printk(BIOS_DEBUG, " done.\n"); + + /* program secondary mlt XXX byte? */ + pci_write_config8(PCI_DEV(0, 0x1e, 0), SMLT, 0x20); + + /* reset rtc power status */ + reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), GEN_PMCON_3); + reg8 &= ~RTC_BATTERY_DEAD; + pci_write_config8(PCI_DEV(0, 0x1f, 0), GEN_PMCON_3, reg8); + + /* usb transient disconnect */ + reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xad); + reg8 |= (3 << 0); + pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xad, reg8); + + reg32 = pci_read_config32(PCI_DEV(0, 0x1d, 7), 0xfc); + reg32 |= (1 << 29) | (1 << 17); + pci_write_config32(PCI_DEV(0, 0x1d, 7), 0xfc, reg32); + + reg32 = pci_read_config32(PCI_DEV(0, 0x1d, 7), 0xdc); + reg32 |= (1 << 31) | (1 << 27); + pci_write_config32(PCI_DEV(0, 0x1d, 7), 0xdc, reg32); + + /* Enable IOAPIC */ + RCBA8(OIC) = 0x03; + RCBA8(OIC); + + ich7_setup_cir(); +} +#endif diff --git a/src/southbridge/intel/i82801gx/i82801gx.h b/src/southbridge/intel/i82801gx/i82801gx.h index 9eea262997..3d27faafad 100644 --- a/src/southbridge/intel/i82801gx/i82801gx.h +++ b/src/southbridge/intel/i82801gx/i82801gx.h @@ -42,6 +42,7 @@ void i82801gx_enable(struct device *dev); void enable_smbus(void); void i82801gx_lpc_setup(void); void i82801gx_setup_bars(void); +void i82801gx_early_init(void); #if ENV_ROMSTAGE int smbus_read_byte(unsigned int device, unsigned int address); From aa990e928910e35edb115095898c4668becdf1d8 Mon Sep 17 00:00:00 2001 From: Arthur Heymans Date: Mon, 11 Nov 2019 20:08:12 +0100 Subject: [PATCH 0161/1242] sb/intel/i82801jx: Move early sb init to a common place Setting southbridge GPIO is now done after console init, which should be fine. This code is partially copied from i82801ix. Change-Id: I51dd30de4a82898b0f1d8c4308e8de4a00d1b7aa Signed-off-by: Arthur Heymans Reviewed-on: https://review.coreboot.org/c/coreboot/+/36756 Reviewed-by: Angel Pons Reviewed-by: Patrick Georgi Tested-by: build bot (Jenkins) --- src/mainboard/asus/p5qc/romstage.c | 18 +----- src/mainboard/asus/p5ql-em/romstage.c | 16 +----- src/mainboard/intel/dg43gt/romstage.c | 18 +----- src/northbridge/intel/x4x/early_init.c | 20 ++++--- src/southbridge/intel/i82801jx/early_init.c | 61 +++++++++++++++++++++ src/southbridge/intel/i82801jx/i82801jx.h | 1 + 6 files changed, 81 insertions(+), 53 deletions(-) diff --git a/src/mainboard/asus/p5qc/romstage.c b/src/mainboard/asus/p5qc/romstage.c index 3462a3d99d..9a90f74189 100644 --- a/src/mainboard/asus/p5qc/romstage.c +++ b/src/mainboard/asus/p5qc/romstage.c @@ -17,7 +17,6 @@ #include #include #include -#include #include #include #include @@ -31,20 +30,8 @@ * We should use standard gpio.h eventually */ -static void mb_gpio_init(void) +static void mb_misc_rcba(void) { - /* Set the value for GPIO base address register and enable GPIO. */ - pci_write_config32(LPC_DEV, D31F0_GPIO_BASE, (DEFAULT_GPIOBASE | 1)); - pci_write_config8(LPC_DEV, D31F0_GPIO_CNTL, 0x10); - - setup_pch_gpios(&mainboard_gpio_map); - - /* Set default GPIOs on superio: TODO (here or in ramstage) */ - - /* Enable IOAPIC */ - RCBA8(0x31ff) = 0x03; - RCBA8(0x31ff); - /* TODO? */ RCBA32(RCBA_CG) = 0xbf7f001f; RCBA32(0x3430) = 0x00000002; @@ -59,13 +46,14 @@ void mainboard_romstage_entry(void) /* Set southbridge and Super I/O GPIOs. */ i82801jx_lpc_setup(); - mb_gpio_init(); + mb_misc_rcba(); winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); console_init(); enable_smbus(); + i82801jx_early_init(); x4x_early_init(); s3_resume = southbridge_detect_s3_resume(); diff --git a/src/mainboard/asus/p5ql-em/romstage.c b/src/mainboard/asus/p5ql-em/romstage.c index 142ee73e49..c7ade1c541 100644 --- a/src/mainboard/asus/p5ql-em/romstage.c +++ b/src/mainboard/asus/p5ql-em/romstage.c @@ -16,7 +16,6 @@ #include #include #include -#include #include #include #include @@ -104,19 +103,6 @@ static int setup_sio_gpio(void) return need_reset; } -static void mb_gpio_init(void) -{ - /* Set the value for GPIO base address register and enable GPIO. */ - pci_write_config32(LPC_DEV, D31F0_GPIO_BASE, (DEFAULT_GPIOBASE | 1)); - pci_write_config8(LPC_DEV, D31F0_GPIO_CNTL, 0x10); - - setup_pch_gpios(&mainboard_gpio_map); - - /* Enable IOAPIC */ - RCBA8(0x31ff) = 0x03; - RCBA8(0x31ff); -} - void mainboard_romstage_entry(void) { /* This board has first dimm slot of each channel hooked up to @@ -129,13 +115,13 @@ void mainboard_romstage_entry(void) /* Set southbridge and Super I/O GPIOs. */ i82801jx_lpc_setup(); - mb_gpio_init(); winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); console_init(); enable_smbus(); + i82801jx_early_init(); x4x_early_init(); s3_resume = southbridge_detect_s3_resume(); diff --git a/src/mainboard/intel/dg43gt/romstage.c b/src/mainboard/intel/dg43gt/romstage.c index 6e645b5630..b851f98627 100644 --- a/src/mainboard/intel/dg43gt/romstage.c +++ b/src/mainboard/intel/dg43gt/romstage.c @@ -17,7 +17,6 @@ #include #include #include -#include #include #include #include @@ -31,20 +30,8 @@ * We should use standard gpio.h eventually */ -static void mb_gpio_init(void) +static void mb_misc_rcba(void) { - /* Set the value for GPIO base address register and enable GPIO. */ - pci_write_config32(LPC_DEV, D31F0_GPIO_BASE, (DEFAULT_GPIOBASE | 1)); - pci_write_config8(LPC_DEV, D31F0_GPIO_CNTL, 0x10); - - setup_pch_gpios(&mainboard_gpio_map); - - /* Set default GPIOs on superio: TODO (here or in ramstage) */ - - /* Enable IOAPIC */ - RCBA8(0x31ff) = 0x03; - RCBA8(0x31ff); - RCBA32(0x3410) = 0x00060464; RCBA32(RCBA_BUC) &= ~BUC_LAND; RCBA32(0x3418) = 0x01320001; @@ -61,13 +48,14 @@ void mainboard_romstage_entry(void) /* Set southbridge and Super I/O GPIOs. */ i82801jx_lpc_setup(); - mb_gpio_init(); + mb_misc_rcba(); winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); console_init(); enable_smbus(); + i82801jx_early_init(); x4x_early_init(); s3_resume = southbridge_detect_s3_resume(); diff --git a/src/northbridge/intel/x4x/early_init.c b/src/northbridge/intel/x4x/early_init.c index a58f2ba6e9..d48b8f0263 100644 --- a/src/northbridge/intel/x4x/early_init.c +++ b/src/northbridge/intel/x4x/early_init.c @@ -42,8 +42,10 @@ void x4x_early_init(void) pci_write_config32(d0f0, D0F0_EPBAR_LO, DEFAULT_EPBAR | 1); /* Setup PMBASE */ - pci_write_config32(PCI_DEV(0, 0x1f, 0), PMBASE, DEFAULT_PMBASE | 1); - pci_write_config8(PCI_DEV(0, 0x1f, 0), ACPI_CNTL, 0x80); + if (!CONFIG(SOUTHBRIDGE_INTEL_I82801JX)) { + pci_write_config32(PCI_DEV(0, 0x1f, 0), PMBASE, DEFAULT_PMBASE | 1); + pci_write_config8(PCI_DEV(0, 0x1f, 0), ACPI_CNTL, 0x80); + } /* Setup HECIBAR */ pci_write_config32(PCI_DEV(0, 3, 0), 0x10, DEFAULT_HECIBAR); @@ -57,12 +59,14 @@ void x4x_early_init(void) pci_write_config8(d0f0, D0F0_PAM(5), 0x33); pci_write_config8(d0f0, D0F0_PAM(6), 0x33); - printk(BIOS_DEBUG, "Disabling Watchdog reboot..."); - RCBA32(GCS) = RCBA32(GCS) | (1 << 5); /* No reset */ - outw(1 << 11, DEFAULT_PMBASE + 0x60 + 0x08); /* halt timer */ - outw(1 << 3, DEFAULT_PMBASE + 0x60 + 0x04); /* clear timeout */ - outw(1 << 1, DEFAULT_PMBASE + 0x60 + 0x06); /* clear 2nd timeout */ - printk(BIOS_DEBUG, " done.\n"); + if (!CONFIG(SOUTHBRIDGE_INTEL_I82801JX)) { + printk(BIOS_DEBUG, "Disabling Watchdog reboot..."); + RCBA32(GCS) = RCBA32(GCS) | (1 << 5); /* No reset */ + outw(1 << 11, DEFAULT_PMBASE + 0x60 + 0x08); /* halt timer */ + outw(1 << 3, DEFAULT_PMBASE + 0x60 + 0x04); /* clear timeout */ + outw(1 << 1, DEFAULT_PMBASE + 0x60 + 0x06); /* clear 2nd timeout */ + printk(BIOS_DEBUG, " done.\n"); + } if (!(pci_read_config32(d0f0, D0F0_CAPID0 + 4) & (1 << (46 - 32)))) { /* Enable internal GFX */ diff --git a/src/southbridge/intel/i82801jx/early_init.c b/src/southbridge/intel/i82801jx/early_init.c index 9d40cf2d27..469073240e 100644 --- a/src/southbridge/intel/i82801jx/early_init.c +++ b/src/southbridge/intel/i82801jx/early_init.c @@ -12,7 +12,10 @@ * GNU General Public License for more details. */ +#include #include +#include +#include #include "i82801jx.h" #include "chip.h" @@ -52,3 +55,61 @@ void i82801jx_lpc_setup(void) pci_write_config32(d31f0, D31F0_GEN3_DEC, config->gen3_dec); pci_write_config32(d31f0, D31F0_GEN4_DEC, config->gen4_dec); } + +static void i82801jx_setup_bars(void) +{ + const pci_devfn_t d31f0 = PCI_DEV(0, 0x1f, 0); + + /* Set up RCBA. */ + pci_write_config32(d31f0, RCBA, (uintptr_t)DEFAULT_RCBA | 1); + + /* Set up PMBASE. */ + pci_write_config32(d31f0, D31F0_PMBASE, DEFAULT_PMBASE | 1); + /* Enable PMBASE. */ + pci_write_config8(d31f0, D31F0_ACPI_CNTL, 0x80); + + /* Set up GPIOBASE. */ + pci_write_config32(d31f0, D31F0_GPIO_BASE, DEFAULT_GPIOBASE); + /* Enable GPIO. */ + pci_write_config8(d31f0, D31F0_GPIO_CNTL, + pci_read_config8(d31f0, D31F0_GPIO_CNTL) | 0x10); +} + +#define TCO_BASE 0x60 + +void i82801jx_early_init(void) +{ + const pci_devfn_t d31f0 = PCI_DEV(0, 0x1f, 0); + + printk(BIOS_DEBUG, "Setting up static southbridge registers..."); + i82801jx_setup_bars(); + printk(BIOS_DEBUG, " done.\n"); + + setup_pch_gpios(&mainboard_gpio_map); + + printk(BIOS_DEBUG, "Disabling Watchdog reboot..."); + RCBA32(GCS) = RCBA32(GCS) | (1 << 5); /* No reset */ + write_pmbase16(TCO_BASE + 0x8, (1 << 11)); /* halt timer */ + write_pmbase16(TCO_BASE + 0x4, (1 << 3)); /* clear timeout */ + write_pmbase16(TCO_BASE + 0x6, (1 << 1)); /* clear 2nd timeout */ + printk(BIOS_DEBUG, " done.\n"); + + /* Enable IOAPIC */ + RCBA8(OIC) = 0x3; + RCBA8(OIC); + + /* Initialize power management initialization + register early as it affects reboot behavior. */ + /* Bit 20 activates global reset of host and ME on cf9 writes of 0x6 + and 0xe (required if ME is disabled but present), bit 31 locks it. + The other bits are 'must write'. */ + u8 reg8 = pci_read_config8(d31f0, 0xac); + reg8 |= (1 << 31) | (1 << 30) | (1 << 20) | (3 << 8); + pci_write_config8(d31f0, 0xac, reg8); + + /* TODO: If RTC power failed, reset RTC state machine + (set, then reset RTC 0x0b bit7) */ + + /* TODO: Check power state bits in GEN_PMCON_2 (D31F0 0xa2) + before they get cleared. */ +} diff --git a/src/southbridge/intel/i82801jx/i82801jx.h b/src/southbridge/intel/i82801jx/i82801jx.h index e302c8986a..d406d1d631 100644 --- a/src/southbridge/intel/i82801jx/i82801jx.h +++ b/src/southbridge/intel/i82801jx/i82801jx.h @@ -235,6 +235,7 @@ int smbus_block_write(unsigned int device, unsigned int cmd, u8 bytes, const u8 *buf); #endif void i82801jx_lpc_setup(void); +void i82801jx_early_init(void); #endif From 2452afbe04584d48a9d76535f943c0cfc641aa19 Mon Sep 17 00:00:00 2001 From: Arthur Heymans Date: Mon, 11 Nov 2019 20:18:24 +0100 Subject: [PATCH 0162/1242] mb/*/*(ich7/x4x): Use common early southbridge init One functional change is that southbridge GPIO init is moved after console init. Change-Id: I53e6f177aadcdaa8c45593e0a8098e8d3c400d27 Signed-off-by: Arthur Heymans Reviewed-on: https://review.coreboot.org/c/coreboot/+/36757 Reviewed-by: Angel Pons Reviewed-by: Patrick Georgi Reviewed-by: HAOUAS Elyes Tested-by: build bot (Jenkins) --- src/mainboard/asrock/g41c-gs/romstage.c | 14 +------------- src/mainboard/asus/p5qpl-am/romstage.c | 18 +----------------- src/mainboard/foxconn/g41s-k/romstage.c | 14 +------------- .../gigabyte/ga-g41m-es2l/romstage.c | 19 +++---------------- src/mainboard/intel/dg41wv/romstage.c | 14 +------------- .../lenovo/thinkcentre_a58/romstage.c | 18 +----------------- src/northbridge/intel/x4x/early_init.c | 15 --------------- 7 files changed, 8 insertions(+), 104 deletions(-) diff --git a/src/mainboard/asrock/g41c-gs/romstage.c b/src/mainboard/asrock/g41c-gs/romstage.c index 9de168c5e4..b054897509 100644 --- a/src/mainboard/asrock/g41c-gs/romstage.c +++ b/src/mainboard/asrock/g41c-gs/romstage.c @@ -20,7 +20,6 @@ #include #include #include -#include #include #include #include @@ -35,12 +34,6 @@ static void mb_lpc_setup(void) { - /* Set the value for GPIO base address register and enable GPIO. */ - pci_write_config32(LPC_DEV, GPIO_BASE, (DEFAULT_GPIOBASE | 1)); - pci_write_config8(LPC_DEV, GPIO_CNTL, 0x10); - - setup_pch_gpios(&mainboard_gpio_map); - /* Set GPIOs on superio, enable UART */ if (CONFIG(SUPERIO_NUVOTON_NCT6776)) { nuvoton_pnp_enter_conf_state(SERIAL_DEV_R2); @@ -58,12 +51,6 @@ static void mb_lpc_setup(void) /* IRQ routing */ RCBA16(D31IR) = 0x0132; RCBA16(D29IR) = 0x0237; - - /* Enable IOAPIC */ - RCBA8(OIC) = 0x03; - RCBA8(OIC); - - ich7_setup_cir(); } void mainboard_romstage_entry(void) @@ -81,6 +68,7 @@ void mainboard_romstage_entry(void) enable_smbus(); + i82801gx_early_init(); x4x_early_init(); s3_resume = southbridge_detect_s3_resume(); diff --git a/src/mainboard/asus/p5qpl-am/romstage.c b/src/mainboard/asus/p5qpl-am/romstage.c index 4653b42267..de3972db4e 100644 --- a/src/mainboard/asus/p5qpl-am/romstage.c +++ b/src/mainboard/asus/p5qpl-am/romstage.c @@ -23,7 +23,6 @@ #include #include #include -#include #include #include #include @@ -128,21 +127,6 @@ static int setup_sio_gpio(void) return need_reset; } -static void mb_lpc_setup(void) -{ - /* Set the value for GPIO base address register and enable GPIO. */ - pci_write_config32(LPC_DEV, GPIO_BASE, (DEFAULT_GPIOBASE | 1)); - pci_write_config8(LPC_DEV, GPIO_CNTL, 0x10); - - setup_pch_gpios(&mainboard_gpio_map); - - /* Enable IOAPIC */ - RCBA8(0x31ff) = 0x03; - RCBA8(0x31ff); - - ich7_setup_cir(); -} - void mainboard_romstage_entry(void) { // ch0 ch1 @@ -152,13 +136,13 @@ void mainboard_romstage_entry(void) /* Set southbridge and Super I/O GPIOs. */ i82801gx_lpc_setup(); - mb_lpc_setup(); winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); console_init(); enable_smbus(); + i82801gx_early_init(); x4x_early_init(); s3_resume = southbridge_detect_s3_resume(); diff --git a/src/mainboard/foxconn/g41s-k/romstage.c b/src/mainboard/foxconn/g41s-k/romstage.c index f423c11378..45ff7e458e 100644 --- a/src/mainboard/foxconn/g41s-k/romstage.c +++ b/src/mainboard/foxconn/g41s-k/romstage.c @@ -20,7 +20,6 @@ #include #include #include -#include #include #include #include @@ -32,12 +31,6 @@ static void mb_lpc_setup(void) { - /* Set the value for GPIO base address register and enable GPIO. */ - pci_write_config32(LPC_DEV, GPIO_BASE, (DEFAULT_GPIOBASE | 1)); - pci_write_config8(LPC_DEV, GPIO_CNTL, 0x10); - - setup_pch_gpios(&mainboard_gpio_map); - /* Set up GPIOs on Super I/O. */ ite_reg_write(GPIO_DEV, 0x25, 0x01); ite_reg_write(GPIO_DEV, 0x26, 0x04); @@ -61,13 +54,7 @@ static void mb_lpc_setup(void) RCBA16(D30IR) = 0x3241; RCBA16(D29IR) = 0x0237; - /* Enable IOAPIC. */ - RCBA8(OIC) = 0x03; - RCBA8(OIC); - RCBA32(FD) |= FD_INTLAN; - - ich7_setup_cir(); } void mainboard_romstage_entry(void) @@ -92,6 +79,7 @@ void mainboard_romstage_entry(void) enable_smbus(); + i82801gx_early_init(); x4x_early_init(); s3_resume = southbridge_detect_s3_resume(); diff --git a/src/mainboard/gigabyte/ga-g41m-es2l/romstage.c b/src/mainboard/gigabyte/ga-g41m-es2l/romstage.c index fa69d122cb..16b157b2dd 100644 --- a/src/mainboard/gigabyte/ga-g41m-es2l/romstage.c +++ b/src/mainboard/gigabyte/ga-g41m-es2l/romstage.c @@ -19,7 +19,6 @@ #include #include #include -#include #include #include #include @@ -35,19 +34,12 @@ * We should use standard gpio.h eventually */ -static void mb_gpio_init(void) +static void mb_lpc_init(void) { pci_devfn_t dev; /* Southbridge GPIOs. */ dev = PCI_DEV(0x0, 0x1f, 0x0); - - /* Set the value for GPIO base address register and enable GPIO. */ - pci_write_config32(dev, GPIO_BASE, (DEFAULT_GPIOBASE | 1)); - pci_write_config8(dev, GPIO_CNTL, 0x10); - - setup_pch_gpios(&mainboard_gpio_map); - /* Set default GPIOs on superio */ ite_reg_write(GPIO_DEV, 0x25, 0x00); ite_reg_write(GPIO_DEV, 0x26, 0xc7); @@ -90,12 +82,6 @@ static void mb_gpio_init(void) RCBA32(D31IR) = 0x00410032; RCBA32(D29IR) = 0x32100237; RCBA32(D27IR) = 0x00000000; - - /* Enable IOAPIC */ - RCBA8(OIC) = 0x03; - RCBA8(OIC); - - ich7_setup_cir(); } void mainboard_romstage_entry(void) @@ -107,7 +93,7 @@ void mainboard_romstage_entry(void) /* Set southbridge and Super I/O GPIOs. */ i82801gx_lpc_setup(); - mb_gpio_init(); + mb_lpc_init(); ite_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); /* Disable SIO reboot */ @@ -117,6 +103,7 @@ void mainboard_romstage_entry(void) enable_smbus(); + i82801gx_early_init(); x4x_early_init(); s3_resume = southbridge_detect_s3_resume(); diff --git a/src/mainboard/intel/dg41wv/romstage.c b/src/mainboard/intel/dg41wv/romstage.c index c0127b6c45..0d7c162272 100644 --- a/src/mainboard/intel/dg41wv/romstage.c +++ b/src/mainboard/intel/dg41wv/romstage.c @@ -20,7 +20,6 @@ #include #include #include -#include #include #include #include @@ -31,12 +30,6 @@ static void mb_lpc_setup(void) { - /* Set the value for GPIO base address register and enable GPIO. */ - pci_write_config32(LPC_DEV, GPIO_BASE, (DEFAULT_GPIOBASE | 1)); - pci_write_config8(LPC_DEV, GPIO_CNTL, 0x10); - - setup_pch_gpios(&mainboard_gpio_map); - /* Set GPIOs on superio, enable UART */ pnp_enter_ext_func_mode(SERIAL_DEV); pnp_set_logical_device(SERIAL_DEV); @@ -48,12 +41,6 @@ static void mb_lpc_setup(void) /* IRQ routing */ RCBA16(D31IR) = 0x0132; RCBA16(D29IR) = 0x0237; - - /* Enable IOAPIC */ - RCBA8(0x31ff) = 0x03; - RCBA8(0x31ff); - - ich7_setup_cir(); } void mainboard_romstage_entry(void) @@ -72,6 +59,7 @@ void mainboard_romstage_entry(void) enable_smbus(); + i82801gx_early_init(); x4x_early_init(); s3_resume = southbridge_detect_s3_resume(); diff --git a/src/mainboard/lenovo/thinkcentre_a58/romstage.c b/src/mainboard/lenovo/thinkcentre_a58/romstage.c index d632d9ddbf..8be2c86734 100644 --- a/src/mainboard/lenovo/thinkcentre_a58/romstage.c +++ b/src/mainboard/lenovo/thinkcentre_a58/romstage.c @@ -17,7 +17,6 @@ #include #include -#include #include #include #include @@ -27,21 +26,6 @@ #define SERIAL_DEV PNP_DEV(0x2e, SMSCSUPERIO_SP1) #define LPC_DEV PCI_DEV(0, 0x1f, 0) -static void mb_lpc_setup(void) -{ - /* Set the value for GPIO base address register and enable GPIO. */ - pci_write_config32(LPC_DEV, GPIO_BASE, (DEFAULT_GPIOBASE | 1)); - pci_write_config8(LPC_DEV, GPIO_CNTL, 0x10); - - setup_pch_gpios(&mainboard_gpio_map); - - /* Enable IOAPIC */ - RCBA8(0x31ff) = 0x03; - RCBA8(0x31ff); - - ich7_setup_cir(); -} - void mainboard_romstage_entry(void) { // ch0 ch1 @@ -51,13 +35,13 @@ void mainboard_romstage_entry(void) /* Set southbridge and Super I/O GPIOs. */ i82801gx_lpc_setup(); - mb_lpc_setup(); smscsuperio_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); console_init(); enable_smbus(); + i82801gx_early_init(); x4x_early_init(); s3_resume = southbridge_detect_s3_resume(); diff --git a/src/northbridge/intel/x4x/early_init.c b/src/northbridge/intel/x4x/early_init.c index d48b8f0263..f89411e482 100644 --- a/src/northbridge/intel/x4x/early_init.c +++ b/src/northbridge/intel/x4x/early_init.c @@ -41,12 +41,6 @@ void x4x_early_init(void) /* Setup EPBAR. */ pci_write_config32(d0f0, D0F0_EPBAR_LO, DEFAULT_EPBAR | 1); - /* Setup PMBASE */ - if (!CONFIG(SOUTHBRIDGE_INTEL_I82801JX)) { - pci_write_config32(PCI_DEV(0, 0x1f, 0), PMBASE, DEFAULT_PMBASE | 1); - pci_write_config8(PCI_DEV(0, 0x1f, 0), ACPI_CNTL, 0x80); - } - /* Setup HECIBAR */ pci_write_config32(PCI_DEV(0, 3, 0), 0x10, DEFAULT_HECIBAR); @@ -59,15 +53,6 @@ void x4x_early_init(void) pci_write_config8(d0f0, D0F0_PAM(5), 0x33); pci_write_config8(d0f0, D0F0_PAM(6), 0x33); - if (!CONFIG(SOUTHBRIDGE_INTEL_I82801JX)) { - printk(BIOS_DEBUG, "Disabling Watchdog reboot..."); - RCBA32(GCS) = RCBA32(GCS) | (1 << 5); /* No reset */ - outw(1 << 11, DEFAULT_PMBASE + 0x60 + 0x08); /* halt timer */ - outw(1 << 3, DEFAULT_PMBASE + 0x60 + 0x04); /* clear timeout */ - outw(1 << 1, DEFAULT_PMBASE + 0x60 + 0x06); /* clear 2nd timeout */ - printk(BIOS_DEBUG, " done.\n"); - } - if (!(pci_read_config32(d0f0, D0F0_CAPID0 + 4) & (1 << (46 - 32)))) { /* Enable internal GFX */ pci_write_config32(d0f0, D0F0_DEVEN, BOARD_DEVEN); From a1928cfa28e4a589a9f8c1b349edd234c38d87ec Mon Sep 17 00:00:00 2001 From: Arthur Heymans Date: Wed, 13 Nov 2019 10:51:59 +0100 Subject: [PATCH 0163/1242] sb/intel/i82801gx: Don't setup CIR when the northbridge is x4x The northbridge code to set up DMI is not correct and the CIR bits relate to that. This fixes a regression caused by 2437fe9 'sb/intel/i82801gx: Move CIR init to a common place', where payloads hang on southbridge IO. Change-Id: Iabb54d9954d442a1a7b48a6c6e76faa8079a4c71 Signed-off-by: Arthur Heymans Reviewed-on: https://review.coreboot.org/c/coreboot/+/36809 Reviewed-by: Angel Pons Reviewed-by: Patrick Georgi Tested-by: build bot (Jenkins) --- src/southbridge/intel/i82801gx/early_init.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/src/southbridge/intel/i82801gx/early_init.c b/src/southbridge/intel/i82801gx/early_init.c index 0bd6198e2c..f91a5dc1d0 100644 --- a/src/southbridge/intel/i82801gx/early_init.c +++ b/src/southbridge/intel/i82801gx/early_init.c @@ -112,6 +112,9 @@ void i82801gx_early_init(void) RCBA8(OIC) = 0x03; RCBA8(OIC); - ich7_setup_cir(); + /* A lot of CIR bits relate DMI setup which is likely not correctly + done for x4x. The issue is also present on ICH10. */ + if (!CONFIG(NORTHBRIDGE_INTEL_X4X)) + ich7_setup_cir(); } #endif From 348002c3055de539377b8223e5a9af0a1ac8c92e Mon Sep 17 00:00:00 2001 From: Joel Kitching Date: Wed, 13 Nov 2019 16:17:34 +0000 Subject: [PATCH 0164/1242] Update vboot submodule to upstream master Updating from commit id b2c8984d: 2019-10-01 06:01:59 +0000 - (vboot: fix compile error with MOCK_TPM) to commit id 87276ffe: 2019-11-07 17:46:09 +0800 - (futility: updater: Clean up hard-coded section names to preserve) This brings in 48 new commits. Change-Id: Iabaadc63227b856d0a2b7f3b23fe8c41b28d8eae Signed-off-by: Joel Kitching Reviewed-on: https://review.coreboot.org/c/coreboot/+/36813 Tested-by: build bot (Jenkins) Reviewed-by: Julius Werner --- 3rdparty/vboot | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/3rdparty/vboot b/3rdparty/vboot index b2c8984d37..87276ffed4 160000 --- a/3rdparty/vboot +++ b/3rdparty/vboot @@ -1 +1 @@ -Subproject commit b2c8984d37e378b2faad170d4ec9b378c0c2b145 +Subproject commit 87276ffed46b3c64ff62153ac8599a79b9bcb683 From 50b999feb842ed116aeaa885d361da776d267ad6 Mon Sep 17 00:00:00 2001 From: Frans Hendriks Date: Fri, 8 Nov 2019 13:55:45 +0100 Subject: [PATCH 0165/1242] {drivers,mainboard}: Move FSP logo support to fsp1_1 Support to display a logo using FSP 1.1 currently resides in facebook fbg1701 mainboard. The related support is moved to drivers/intel/fsp1_1 and used by the Facebook fbg1701 mainboard. The storage for the uncompressed logo is changed. We don't use .bss any longer as the logo doesn't need to be available at runtime. BUG=N/A TEST=booting Facebook fbg1701 Change-Id: I276e6e14fc87d0b95fe5fdf7b617afd26769de79 Signed-off-by: Wim Vervoorn Reviewed-on: https://review.coreboot.org/c/coreboot/+/36679 Tested-by: build bot (Jenkins) Reviewed-by: Frans Hendriks --- src/commonlib/include/commonlib/cbmem_id.h | 1 + src/drivers/intel/fsp1_1/Kconfig | 12 +++++ src/drivers/intel/fsp1_1/Makefile.inc | 7 +++ .../intel/fsp1_1/include/fsp/ramstage.h | 1 + .../logo.h => drivers/intel/fsp1_1/logo.c} | 18 +++++--- src/drivers/intel/fsp1_1/ramstage.c | 14 ++++++ src/mainboard/facebook/fbg1701/Kconfig | 9 ---- src/mainboard/facebook/fbg1701/Makefile.inc | 6 --- src/mainboard/facebook/fbg1701/logo.c | 46 ------------------- src/mainboard/facebook/fbg1701/ramstage.c | 13 ------ 10 files changed, 46 insertions(+), 81 deletions(-) rename src/{mainboard/facebook/fbg1701/logo.h => drivers/intel/fsp1_1/logo.c} (60%) delete mode 100644 src/mainboard/facebook/fbg1701/logo.c diff --git a/src/commonlib/include/commonlib/cbmem_id.h b/src/commonlib/include/commonlib/cbmem_id.h index 54a0dee55a..b063cd1937 100644 --- a/src/commonlib/include/commonlib/cbmem_id.h +++ b/src/commonlib/include/commonlib/cbmem_id.h @@ -79,6 +79,7 @@ #define CBMEM_ID_ROM2 0x524f4d32 #define CBMEM_ID_ROM3 0x524f4d33 #define CBMEM_ID_FMAP 0x464d4150 +#define CBMEM_ID_FSP_LOGO 0x4c4f474f #define CBMEM_ID_TO_NAME_TABLE \ { CBMEM_ID_ACPI, "ACPI " }, \ diff --git a/src/drivers/intel/fsp1_1/Kconfig b/src/drivers/intel/fsp1_1/Kconfig index 5f8f5b5534..989c4547f5 100644 --- a/src/drivers/intel/fsp1_1/Kconfig +++ b/src/drivers/intel/fsp1_1/Kconfig @@ -91,4 +91,16 @@ config SKIP_FSP_CAR help Selected by platforms that implement their own CAR setup. +config FSP1_1_DISPLAY_LOGO + bool "Enable logo" + default n + help + Uses the FSP to display the boot logo. This method supports a + BMP file only. The uncompressed size can be up to 1 MB. + +config FSP1_1_LOGO_FILE_NAME + string "Logo file" + depends on FSP1_1_DISPLAY_LOGO + default "3rdparty/blobs/mainboard/$(MAINBOARDDIR)/logo.bmp" + endif #PLATFORM_USES_FSP1_1 diff --git a/src/drivers/intel/fsp1_1/Makefile.inc b/src/drivers/intel/fsp1_1/Makefile.inc index 014311897f..7b08fb4408 100644 --- a/src/drivers/intel/fsp1_1/Makefile.inc +++ b/src/drivers/intel/fsp1_1/Makefile.inc @@ -32,6 +32,7 @@ ramstage-$(CONFIG_RUN_FSP_GOP) += fsp_gop.c ramstage-y += fsp_relocate.c ramstage-y += fsp_util.c ramstage-y += hob.c +ramstage-$(CONFIG_FSP1_1_DISPLAY_LOGO) += logo.c ramstage-y += ramstage.c ramstage-$(CONFIG_INTEL_GMA_ADD_VBT) += vbt.c ramstage-$(CONFIG_MMA) += mma_core.c @@ -53,4 +54,10 @@ fsp.bin-options := --xip $(TXTIBB) fsp.bin-COREBOOT-position := $(CONFIG_FSP_LOC) endif +# Add logo to the cbfs image +cbfs-files-$(CONFIG_FSP1_1_DISPLAY_LOGO) += logo.bmp +logo.bmp-file := $(call strip_quotes,$(CONFIG_FSP1_1_LOGO_FILE_NAME)) +logo.bmp-type := raw +logo.bmp-compression := LZMA + endif diff --git a/src/drivers/intel/fsp1_1/include/fsp/ramstage.h b/src/drivers/intel/fsp1_1/include/fsp/ramstage.h index 1c9210b464..a5eac0e279 100644 --- a/src/drivers/intel/fsp1_1/include/fsp/ramstage.h +++ b/src/drivers/intel/fsp1_1/include/fsp/ramstage.h @@ -33,6 +33,7 @@ void soc_silicon_init_params(SILICON_INIT_UPD *params); void mainboard_silicon_init_params(SILICON_INIT_UPD *params); void soc_display_silicon_init_params(const SILICON_INIT_UPD *old, SILICON_INIT_UPD *new); +void load_logo(SILICON_INIT_UPD *params); void load_vbt(uint8_t s3_resume, SILICON_INIT_UPD *params); #endif /* _INTEL_COMMON_RAMSTAGE_H_ */ diff --git a/src/mainboard/facebook/fbg1701/logo.h b/src/drivers/intel/fsp1_1/logo.c similarity index 60% rename from src/mainboard/facebook/fbg1701/logo.h rename to src/drivers/intel/fsp1_1/logo.c index 0682d3fa2d..03b2715f43 100644 --- a/src/mainboard/facebook/fbg1701/logo.h +++ b/src/drivers/intel/fsp1_1/logo.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2019 Eltan B.V. - * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; version 2 of the License. @@ -13,9 +11,15 @@ * GNU General Public License for more details. */ -#ifndef LOGO_H -#define LOGO_H +#include +#include +#include +#include -void *load_logo(size_t *logo_size); - -#endif +void load_logo(SILICON_INIT_UPD *params) +{ + params->PcdLogoSize = cbfs_boot_load_file("logo.bmp", (void *)params->PcdLogoPtr, + params->PcdLogoSize, CBFS_TYPE_RAW); + if (!params->PcdLogoSize) + params->PcdLogoPtr = 0; +} diff --git a/src/drivers/intel/fsp1_1/ramstage.c b/src/drivers/intel/fsp1_1/ramstage.c index d278d08ed2..70bedc50af 100644 --- a/src/drivers/intel/fsp1_1/ramstage.c +++ b/src/drivers/intel/fsp1_1/ramstage.c @@ -21,6 +21,7 @@ #include #include #include +#include /* SOC initialization after FSP silicon init */ __weak void soc_after_silicon_init(void) @@ -68,6 +69,7 @@ void fsp_run_silicon_init(FSP_INFO_HEADER *fsp_info_header, int is_s3_wakeup) EFI_STATUS status; UPD_DATA_REGION *upd_ptr; VPD_DATA_REGION *vpd_ptr; + const struct cbmem_entry *logo_entry; /* Display the FSP header */ if (fsp_info_header == NULL) { @@ -94,6 +96,14 @@ void fsp_run_silicon_init(FSP_INFO_HEADER *fsp_info_header, int is_s3_wakeup) load_vbt(is_s3_wakeup, &silicon_init_params); mainboard_silicon_init_params(&silicon_init_params); + if (CONFIG(FSP1_1_DISPLAY_LOGO) && !is_s3_wakeup) { + silicon_init_params.PcdLogoSize = 1 * MiB; + logo_entry = cbmem_entry_add(CBMEM_ID_FSP_LOGO, + silicon_init_params.PcdLogoSize); + silicon_init_params.PcdLogoPtr = (UINT32)cbmem_entry_start(logo_entry); + load_logo(&silicon_init_params); + } + /* Display the UPD data */ if (CONFIG(DISPLAY_UPD_DATA)) soc_display_silicon_init_params(original_params, @@ -111,6 +121,10 @@ void fsp_run_silicon_init(FSP_INFO_HEADER *fsp_info_header, int is_s3_wakeup) timestamp_add_now(TS_FSP_SILICON_INIT_END); printk(BIOS_DEBUG, "FspSiliconInit returned 0x%08x\n", status); + /* The logo_entry can be freed up now as it is not required any longer */ + if (CONFIG(FSP1_1_DISPLAY_LOGO) && !is_s3_wakeup) + cbmem_entry_remove(logo_entry); + /* Mark graphics init done after SiliconInit if VBT was provided */ #if CONFIG(RUN_FSP_GOP) /* GraphicsConfigPtr doesn't exist in Quark X1000's FSP, so this needs diff --git a/src/mainboard/facebook/fbg1701/Kconfig b/src/mainboard/facebook/fbg1701/Kconfig index 41d59ff450..5e71db018a 100644 --- a/src/mainboard/facebook/fbg1701/Kconfig +++ b/src/mainboard/facebook/fbg1701/Kconfig @@ -58,15 +58,6 @@ config FSP_LOC hex default 0xfff9c000 -config FSP1_1_DISPLAY_LOGO - bool "Enable logo" - default n - -config FSP1_1_LOGO_FILE_NAME - string "Logo file" - depends on FSP1_1_DISPLAY_LOGO - default "3rdparty/blobs/mainboard/$(MAINBOARDDIR)/logo.bmp" - config VENDORCODE_ELTAN_OEM_MANIFEST_LOC hex default 0xFFFE9000 diff --git a/src/mainboard/facebook/fbg1701/Makefile.inc b/src/mainboard/facebook/fbg1701/Makefile.inc index a273f41682..ac4e571653 100644 --- a/src/mainboard/facebook/fbg1701/Makefile.inc +++ b/src/mainboard/facebook/fbg1701/Makefile.inc @@ -28,17 +28,11 @@ ramstage-y += cpld.c ramstage-y += gpio.c ramstage-y += hda_verb.c ramstage-y += irqroute.c -ramstage-$(CONFIG_FSP1_1_DISPLAY_LOGO) += logo.c ramstage-y += ramstage.c ramstage-y += w25q64.c romstage-y += cpld.c -cbfs-files-$(CONFIG_FSP1_1_DISPLAY_LOGO) += logo.bmp -logo.bmp-file := $(call strip_quotes,$(CONFIG_FSP1_1_LOGO_FILE_NAME)) -logo.bmp-type := raw -logo.bmp-compression := LZMA - # Order of names in SPD_SOURCES is important! SPD_SOURCES = SAMSUNG_K4B8G1646D-MYKO SPD_SOURCES += MICRON_MT41K512M16HA-125A diff --git a/src/mainboard/facebook/fbg1701/logo.c b/src/mainboard/facebook/fbg1701/logo.c deleted file mode 100644 index 3823c71fdc..0000000000 --- a/src/mainboard/facebook/fbg1701/logo.c +++ /dev/null @@ -1,46 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2017 Patrick Rudolph - * Copyright (C) 2018-2019 Eltan B.V. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include -#include "logo.h" - -static char logo_data[1 * MiB]; -static size_t logo_data_sz = 0; - -void *load_logo(size_t *logo_size) -{ - const char *filename = "logo.bmp"; - - if (logo_data_sz != 0) { - if (logo_size) - *logo_size = logo_data_sz; - return (void *)logo_data; - } - - logo_data_sz = - cbfs_boot_load_file(filename, logo_data, sizeof(logo_data), CBFS_TYPE_RAW); - if (logo_data_sz == 0) - return NULL; - - if (logo_size) - *logo_size = logo_data_sz; - - printk(BIOS_DEBUG, "Found a Logo of %zu bytes after decompression\n", logo_data_sz); - - return (void *)logo_data; -} diff --git a/src/mainboard/facebook/fbg1701/ramstage.c b/src/mainboard/facebook/fbg1701/ramstage.c index 9b25b983f7..055c733fef 100644 --- a/src/mainboard/facebook/fbg1701/ramstage.c +++ b/src/mainboard/facebook/fbg1701/ramstage.c @@ -19,7 +19,6 @@ #include #include #include "cpld.h" -#include "logo.h" struct edp_data { u8 payload_length; @@ -359,16 +358,4 @@ static void mainboard_configure_edp_bridge(void) void mainboard_silicon_init_params(SILICON_INIT_UPD *params) { mainboard_configure_edp_bridge(); - - if (CONFIG(FSP1_1_DISPLAY_LOGO)) { - size_t logo_len; - void *logo = NULL; - - logo = load_logo(&logo_len); - - if (logo) { - params->PcdLogoPtr = (u32)logo; - params->PcdLogoSize = logo_len; - } - } } From b23f392766eb3263a8bb530b8a71edbd779c1dce Mon Sep 17 00:00:00 2001 From: Wim Vervoorn Date: Tue, 12 Nov 2019 09:46:47 +0100 Subject: [PATCH 0166/1242] vendorcode/amd/agesa: Correct typo Correct typo of 'uninitialized' BUG=N/A TEST=build Change-Id: I43c6eb0287d23546a2abb330c7cc8585a33b27b5 Signed-off-by: Wim Vervoorn Reviewed-on: https://review.coreboot.org/c/coreboot/+/36776 Reviewed-by: Frans Hendriks Reviewed-by: HAOUAS Elyes Tested-by: build bot (Jenkins) --- src/vendorcode/amd/agesa/f14/AGESA.h | 2 +- src/vendorcode/amd/agesa/f15tn/AGESA.h | 2 +- src/vendorcode/amd/agesa/f16kb/AGESA.h | 2 +- 3 files changed, 3 insertions(+), 3 deletions(-) diff --git a/src/vendorcode/amd/agesa/f14/AGESA.h b/src/vendorcode/amd/agesa/f14/AGESA.h index 5a87d293cb..9bf9207789 100644 --- a/src/vendorcode/amd/agesa/f14/AGESA.h +++ b/src/vendorcode/amd/agesa/f14/AGESA.h @@ -369,7 +369,7 @@ typedef struct { IN UINT8 Socket; ///< The Socket on which this Link is located IN UINT8 Link; ///< The Link about to be initialized // Customization fields - IN FINAL_LINK_STATE LinkState; ///< The link may be left unitialized, or powered off. + IN FINAL_LINK_STATE LinkState; ///< The link may be left uninitialized, or powered off. } IGNORE_LINK; diff --git a/src/vendorcode/amd/agesa/f15tn/AGESA.h b/src/vendorcode/amd/agesa/f15tn/AGESA.h index 21ce58c791..ce3e857490 100644 --- a/src/vendorcode/amd/agesa/f15tn/AGESA.h +++ b/src/vendorcode/amd/agesa/f15tn/AGESA.h @@ -370,7 +370,7 @@ typedef struct { IN UINT8 Socket; ///< The Socket on which this Link is located IN UINT8 Link; ///< The Link about to be initialized // Customization fields - IN FINAL_LINK_STATE LinkState; ///< The link may be left unitialized, or powered off. + IN FINAL_LINK_STATE LinkState; ///< The link may be left uninitialized, or powered off. } IGNORE_LINK; diff --git a/src/vendorcode/amd/agesa/f16kb/AGESA.h b/src/vendorcode/amd/agesa/f16kb/AGESA.h index 9262896858..b9b4354d26 100644 --- a/src/vendorcode/amd/agesa/f16kb/AGESA.h +++ b/src/vendorcode/amd/agesa/f16kb/AGESA.h @@ -371,7 +371,7 @@ typedef struct { IN UINT8 Socket; ///< The Socket on which this Link is located IN UINT8 Link; ///< The Link about to be initialized // Customization fields - IN FINAL_LINK_STATE LinkState; ///< The link may be left unitialized, or powered off. + IN FINAL_LINK_STATE LinkState; ///< The link may be left uninitialized, or powered off. } IGNORE_LINK; From b134945ec1fd367c00cc641e929f9e39c8351df9 Mon Sep 17 00:00:00 2001 From: Xiang Wang Date: Tue, 27 Aug 2019 15:57:23 +0800 Subject: [PATCH 0167/1242] drivers/spi: add drivers for sdcard mounted on the spi bus Currently supports initialization, read, write, and erase operations. Tested on HiFive Uneashed implementation follows SD association's SPI access protocol, found as doc http://t.cn/AiB8quFZ Change-Id: I464d2334b8227e448c1c7e324c0455023cffb72a Signed-off-by: Xiang Wang Reviewed-on: https://review.coreboot.org/c/coreboot/+/35118 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi --- src/drivers/spi/Kconfig | 7 + src/drivers/spi/Makefile.inc | 1 + src/drivers/spi/spi_sdcard.c | 813 +++++++++++++++++++++++++++++++++++ src/include/spi_sdcard.h | 60 +++ 4 files changed, 881 insertions(+) create mode 100644 src/drivers/spi/spi_sdcard.c create mode 100644 src/include/spi_sdcard.h diff --git a/src/drivers/spi/Kconfig b/src/drivers/spi/Kconfig index 8b9c25ee98..8300026674 100644 --- a/src/drivers/spi/Kconfig +++ b/src/drivers/spi/Kconfig @@ -28,6 +28,13 @@ config SPI_FLASH Select this option if your chipset driver needs to store certain data in the SPI flash. +config SPI_SDCARD + bool + default n + help + Select this option if your chipset driver needs to store certain + data in the SPI sdcard. + if SPI_FLASH # Keep at 0 because lots of boards assume this default. diff --git a/src/drivers/spi/Makefile.inc b/src/drivers/spi/Makefile.inc index e55233e9d8..6dbc43a6d7 100644 --- a/src/drivers/spi/Makefile.inc +++ b/src/drivers/spi/Makefile.inc @@ -15,6 +15,7 @@ $(1)-y += spi-generic.c $(1)-y += bitbang.c $(1)-$(CONFIG_COMMON_CBFS_SPI_WRAPPER) += cbfs_spi.c $(1)-$(CONFIG_SPI_FLASH) += spi_flash.c +$(1)-$(CONFIG_SPI_SDCARD) += spi_sdcard.c $(1)-$(CONFIG_BOOT_DEVICE_SPI_FLASH_RW_NOMMAP$(2)) += boot_device_rw_nommap.c $(1)-$(CONFIG_CONSOLE_SPI_FLASH) += flashconsole.c $(1)-$(CONFIG_SPI_FLASH_ADESTO) += adesto.c diff --git a/src/drivers/spi/spi_sdcard.c b/src/drivers/spi/spi_sdcard.c new file mode 100644 index 0000000000..c2f8da6ff4 --- /dev/null +++ b/src/drivers/spi/spi_sdcard.c @@ -0,0 +1,813 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 HardenedLinux + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ +#include +#include +#include +#include +#include +#include +#include + +//#define SPI_SDCARD_DEBUG + +#ifdef SPI_SDCARD_DEBUG +#define dprintk(fmt, args...) \ + printk(BIOS_DEBUG, fmt, ##args) +#else +#define dprintk(fmt, args...) \ + do {} while (0) +#endif + +#define SDCARD_TYPE_SDSC 1 +#define SDCARD_TYPE_SDHC 2 +#define SDCARD_TYPE_SDXC 3 + +/* CMD */ +#define GO_IDLE_STATE 0 +#define SEND_OP_COND 1 +#define SWITCH_FUNC 6 +#define SEND_IF_COND 8 +#define SEND_CSD 9 +#define SEND_CID 10 +#define STOP_TRANSMISSION 12 +#define SEND_STATUS 13 +#define SET_BLOCKLEN 16 +#define READ_SINGLE_BLOCK 17 +#define READ_MULTIPLEBLOCK 18 +#define WRITE_BLOCK 24 +#define WRITE_MULTIPLEBLOCK 25 +#define PROGRAM_CSD 27 +#define SET_WRITE_PROT 28 +#define CLR_WRITE_PROT 29 +#define SEND_WRITE_PROT 30 +#define ERASE_WR_BLK_START_ADDR 32 +#define ERASE_WR_BLK_END_ADDR 33 +#define ERASE 38 +#define LOCK_UNLOCK 42 +#define APP_CMD 55 +#define GEN_CMD 56 +#define READ_OCR 58 +#define CRC_ON_OFF 59 + +/* ACMD */ +#define SD_STATUS 13 +#define SEND_NUM_WR_BLOCKS 22 +#define SET_WR_BLK_ERASE_COUNT 23 +#define SD_SEND_OP_COND 41 +#define SET_CLR_CARD_DETECT 42 +#define SEND_SCR 51 + +/* control tokens */ +#define CT_BLOCK_START 0xfe +#define CT_MULTIPLE_BLOCK_START 0xfc +#define CT_MULTIPLE_BLOCK_STOP 0xfd +#define CT_RESPONSE_MASK 0x1f +#define CT_RESPONSE_ACCEPTED 0x05 +#define CT_RESPONSE_REJECTED_CRC 0x0b +#define CT_RESPONSE_REJECTED_WRITE_ERR 0x0d + +/* response type */ +#define RSP_R1 0 +#define RSP_R1b 1 +#define RSP_R2 2 +#define RSP_R3 3 +#define RSP_R4 4 +#define RSP_R5 5 +#define RSP_R7 7 + +#define RSP_ERR_CARD_IS_LOCKED (1 << 0) +#define RSP_ERR_WP_ERASE_SKIP (1 << 1) +#define RSP_ERR_GENERAL (1 << 2) +#define RSP_ERR_CC (1 << 3) +#define RSP_ERR_ECC (1 << 4) +#define RSP_ERR_WP_VIOLATION (1 << 5) +#define RSP_ERR_ERASE_PARAM (1 << 6) +#define RSP_ERR_OUT_OF_RANGE (1 << 7) +#define RSP_ERR_IN_IDLE (1 << 8) +#define RSP_ERR_ERASE_RESET (1 << 9) +#define RSP_ERR_ILLEGAL_COMMAND (1 << 10) +#define RSP_ERR_COM_CRC (1 << 11) +#define RSP_ERR_ERASE_SEQUENCE (1 << 12) +#define RSP_ERR_ADDRESS (1 << 13) +#define RSP_ERR_PARAMETER (1 << 14) + +#define BLOCK_SIZE 512 + +static unsigned long long extract_bits(uint8_t *buff, + int width, int start, int end) +{ + unsigned long long r = 0; + for (int i = end; i >= start; i--) { + int bitpos = width - i - 1; + int b = bitpos / 8; + int shift = 7 - bitpos % 8; + r = (r << 1) | ((buff[b] >> shift) & 1); + } + return r; +} + +static void spi_sdcard_enable_cs(const struct spi_sdcard *card) +{ + spi_claim_bus(&card->slave); +} + +static void spi_sdcard_disable_cs(const struct spi_sdcard *card) +{ + spi_release_bus(&card->slave); +} + +static void spi_sdcard_sendbyte(const struct spi_sdcard *card, uint8_t b) +{ + dprintk("sdcard -> %#x\n", b); + spi_xfer(&card->slave, &b, 1, NULL, 0); +} + +static uint8_t spi_sdcard_recvbyte(const struct spi_sdcard *card) +{ + uint8_t b, t = 0xff; + spi_xfer(&card->slave, &t, 1, &b, 1); + dprintk("sdcard <- %#x\n", b); + return b; +} + +static uint8_t spi_sdcard_calculate_command_crc(uint8_t cmd, uint32_t argument) +{ + uint8_t crc = 0; + crc = crc7_byte(crc, (cmd | 0x40) & 0x7f); + crc = crc7_byte(crc, (argument >> (3 * 8)) & 0xff); + crc = crc7_byte(crc, (argument >> (2 * 8)) & 0xff); + crc = crc7_byte(crc, (argument >> (1 * 8)) & 0xff); + crc = crc7_byte(crc, (argument >> (0 * 8)) & 0xff); + return crc | 1; +} + +static int lookup_cmd_response_type(uint8_t cmd) +{ + switch (cmd) { + case GO_IDLE_STATE: + case SEND_OP_COND: + case SWITCH_FUNC: + case SEND_CSD: + case SEND_CID: + case SET_BLOCKLEN: + case READ_SINGLE_BLOCK: + case READ_MULTIPLEBLOCK: + case WRITE_BLOCK: + case WRITE_MULTIPLEBLOCK: + case PROGRAM_CSD: + case SEND_WRITE_PROT: + case ERASE_WR_BLK_START_ADDR: + case ERASE_WR_BLK_END_ADDR: + case LOCK_UNLOCK: + case APP_CMD: + case GEN_CMD: + case CRC_ON_OFF: + return RSP_R1; + case STOP_TRANSMISSION: + case SET_WRITE_PROT: + case CLR_WRITE_PROT: + case ERASE: + return RSP_R1b; + case SEND_STATUS: + return RSP_R2; + case READ_OCR: + return RSP_R3; + case SEND_IF_COND: + return RSP_R7; + } + return -1; +} + +static int lookup_acmd_response_type(uint8_t cmd) +{ + switch (cmd) { + case SEND_NUM_WR_BLOCKS: + case SET_WR_BLK_ERASE_COUNT: + case SD_SEND_OP_COND: + case SET_CLR_CARD_DETECT: + case SEND_SCR: + return RSP_R1; + case SD_STATUS: + return RSP_R2; + } + return -1; +} + +static int lookup_response_length(int response_type) +{ + switch (response_type) { + case RSP_R1: + case RSP_R1b: + return 1; + case RSP_R2: + return 2; + case RSP_R3: + case RSP_R7: + return 5; + } + return -1; +} + +static int response_resolve(int response_type, uint8_t *response, + uint32_t *out_register) +{ + __unused static const char * const sd_err[] = { + "Card is locked", + "wp erase skip | lock/unlok cmd failed", + "error", + "CC error", + "card err failed", + "wp violation", + "erase param", + "out of range | csd overwrite", + "in idle state", + "erase reset", + "illegal command", + "com crc error", + "erase sequence error", + "address error", + "parameter error" + }; + uint8_t r1 = 0, r2 = 0; + + if ((response_type == RSP_R1) + || (response_type == RSP_R1b) + || (response_type == RSP_R2) + || (response_type == RSP_R3) + || (response_type == RSP_R7)) + r1 = response[0]; + + if (response_type == RSP_R2) + r2 = response[1]; + + if (((response_type == RSP_R3) || (response_type == RSP_R7)) + && (out_register != NULL)) { + *out_register = 0; + *out_register = (*out_register << 8) | response[1]; + *out_register = (*out_register << 8) | response[2]; + *out_register = (*out_register << 8) | response[3]; + *out_register = (*out_register << 8) | response[4]; + } + + if (r1 != 0 || r2 != 0) { + int i = 0; + uint16_t r = (r1 << 8) | r2; + while (r) { + if (r & 1) + dprintk("SDCARD ERROR: %s\n", sd_err[i]); + r = r >> 1; + i++; + } + return (r1 << 8) | r2; + } + + return 0; +} + +static int spi_sdcard_do_command_help(const struct spi_sdcard *card, + int is_acmd, + uint8_t cmd, + uint32_t argument, + uint32_t *out_register) +{ + int ret, type, length, wait; + uint8_t crc, c, response[5]; + + /* calculate crc for command */ + crc = spi_sdcard_calculate_command_crc(cmd, argument); + + if (is_acmd) + dprintk("\nsdcard execute acmd%d, argument = %#x, crc = %#x\n", + cmd, argument, crc); + else + dprintk("\nsdcard execute cmd%d, argument = %#x, crc = %#x\n", + cmd, argument, crc); + + /* lookup response type of command */ + if (!is_acmd) + type = lookup_cmd_response_type(cmd); + else + type = lookup_acmd_response_type(cmd); + + /* lookup response length of command */ + length = lookup_response_length(type); + + /* enable cs */ + spi_sdcard_enable_cs(card); + + /* just delay 8 clocks */ + spi_sdcard_recvbyte(card); + + /* send command */ + spi_sdcard_sendbyte(card, (cmd | 0x40) & 0x7f); + /* send argument */ + spi_sdcard_sendbyte(card, (argument >> (8 * 3)) & 0xff); + spi_sdcard_sendbyte(card, (argument >> (8 * 2)) & 0xff); + spi_sdcard_sendbyte(card, (argument >> (8 * 1)) & 0xff); + spi_sdcard_sendbyte(card, (argument >> (8 * 0)) & 0xff); + /* send crc */ + spi_sdcard_sendbyte(card, crc); + + /* waitting for response */ + wait = 0xffff; + while (((c = spi_sdcard_recvbyte(card)) & 0x80) && --wait) + ; + if (!wait) { + spi_sdcard_disable_cs(card); + return -1; /* timeout */ + } + + /* obtain response */ + for (int i = 0; i < length; i++) { + response[i] = c; + c = spi_sdcard_recvbyte(card); + } + + if (type == RSP_R1b) { + /* waitting done */ + wait = 0xffffff; + while (c == 0 && --wait) + c = spi_sdcard_recvbyte(card); + if (!wait) { + spi_sdcard_disable_cs(card); + return -1; /* timeout */ + } + } + + spi_sdcard_disable_cs(card); + + ret = response_resolve(type, response, out_register); + + return ret; +} + +static int spi_sdcard_do_command(const struct spi_sdcard *card, + uint8_t cmd, + uint32_t argument, + uint32_t *out_register) +{ + return spi_sdcard_do_command_help(card, 0, cmd, argument, out_register); +} + +static int spi_sdcard_do_app_command(const struct spi_sdcard *card, + uint8_t cmd, + uint32_t argument, + uint32_t *out_register) +{ + /* CMD55 */ + spi_sdcard_do_command(card, APP_CMD, 0, NULL); + return spi_sdcard_do_command_help(card, 1, cmd, argument, out_register); +} + + +size_t spi_sdcard_size(const struct spi_sdcard *card) +{ + int wait; + uint8_t csd[16]; + uint16_t c = 0; + + /* CMD9, send csd (128bits register) */ + if (spi_sdcard_do_command(card, SEND_CSD, 0, NULL)) + return -1; + + /* enable CS */ + spi_sdcard_enable_cs(card); + + /* waitting start block token */ + wait = 0xffff; + while ((spi_sdcard_recvbyte(card) != CT_BLOCK_START) && --wait) + ; + if (!wait) { + spi_sdcard_disable_cs(card); + return -1; + } + + /* receive data */ + for (int i = 0; i < 16; i++) { + csd[i] = spi_sdcard_recvbyte(card); + c = crc16_byte(c, csd[i]); + } + + /* receive crc and verify check sum */ + if (((c >> 8) & 0xff) != spi_sdcard_recvbyte(card)) { + spi_sdcard_disable_cs(card); + return -1; + } + if (((c >> 0) & 0xff) != spi_sdcard_recvbyte(card)) { + spi_sdcard_disable_cs(card); + return -1; + } + + /* disable cs */ + spi_sdcard_disable_cs(card); + + if (extract_bits(csd, 128, 126, 127) == 0) { + /* csd version 1.0 */ + size_t c_size = extract_bits(csd, 128, 62, 73); + size_t mult = extract_bits(csd, 128, 47, 49); + size_t read_bl_len = extract_bits(csd, 128, 80, 83); + return (c_size + 1) * mult * (1 << read_bl_len); + } + + if (extract_bits(csd, 128, 126, 127) == 1) { + /* csd version 2.0 */ + size_t c_size = extract_bits(csd, 128, 48, 69); + return (c_size + 1) * 512 * 1024; + } + + return -1; +} + +int spi_sdcard_init(struct spi_sdcard *card, + const unsigned int bus, const unsigned int cs) +{ + int resolve, wait; + uint32_t ocr; + + /* initialize spi controller */ + spi_setup_slave(bus, cs, &card->slave); + + /* must wait at least 74 clock ticks after reset + * disable cs pin to enter spi mode */ + spi_sdcard_disable_cs(card); + for (int i = 0; i < 10; i++) + spi_sdcard_sendbyte(card, 0xff); + + /* CMD0, reset sdcard */ + wait = 0xffff; + while ((spi_sdcard_do_command(card, GO_IDLE_STATE, 0, NULL) + != RSP_ERR_IN_IDLE) && --wait) + ; + if (!wait) + return -1; /* timeout */ + + /* CMD8 */ + resolve = spi_sdcard_do_command(card, SEND_IF_COND, 0x1aa, NULL); + if (resolve & RSP_ERR_ILLEGAL_COMMAND) { + /* ACMD41, initialize card */ + wait = 0xffff; + while ((resolve = spi_sdcard_do_app_command(card, + SD_SEND_OP_COND, 0, NULL)) && --wait) + ; + if ((resolve & RSP_ERR_ILLEGAL_COMMAND) || !wait) { + wait = 0xffff; + /* CMD1, initialize card for 2.1mm SD Memory Card */ + while (spi_sdcard_do_app_command(card, SEND_OP_COND, + 0, NULL) && --wait) + ; + if (!wait) + return -1; /* unknown card */ + } + } else { + /* ACMD41, initialize card */ + wait = 0xffff; + while (spi_sdcard_do_app_command(card, SD_SEND_OP_COND, + 0x40000000, NULL) && --wait) + ; + if (!wait) + return -1; + } + + /* CMD58, read ocr register */ + if (spi_sdcard_do_command(card, READ_OCR, 0, &ocr)) + return -1; + + /* CMD16, set block length to 512 bytes */ + if (spi_sdcard_do_command(card, SET_BLOCKLEN, 512, NULL)) + return -1; + + /* CCS is bit30 of ocr register + * CCS = 0 -> SDSC + * CCS = 1 -> SDHC/SDXC + * */ + if ((ocr & 0x40000000) == 0) + card->type = SDCARD_TYPE_SDSC; + else { + /* size > 32G -> SDXC */ + if (spi_sdcard_size(card) > 32LL * 1024 * 1024 * 1024) + card->type = SDCARD_TYPE_SDXC; + else + card->type = SDCARD_TYPE_SDHC; + } + + return 0; +} + +int spi_sdcard_single_read(const struct spi_sdcard *card, + size_t block_address, + void *buff) +{ + int wait; + uint16_t c = 0; + + if (card->type == SDCARD_TYPE_SDSC) + block_address = block_address * 512; + + /* CMD17, start single block read */ + if (spi_sdcard_do_command(card, READ_SINGLE_BLOCK, block_address, NULL)) + return -1; + + /* enable cs */ + spi_sdcard_enable_cs(card); + + /* waitting start block token */ + wait = 0xffff; + while ((spi_sdcard_recvbyte(card) != CT_BLOCK_START) && --wait) + ; + if (!wait) { /* timeout */ + spi_sdcard_disable_cs(card); + return -1; + } + + /* receive data */ + for (int i = 0; i < 512; i++) { + ((uint8_t *)buff)[i] = spi_sdcard_recvbyte(card); + c = crc16_byte(c, ((uint8_t *)buff)[i]); + } + + /* receive crc and verify check sum */ + if (((c >> 8) & 0xff) != spi_sdcard_recvbyte(card)) { + spi_sdcard_disable_cs(card); + return -1; + } + if (((c >> 0) & 0xff) != spi_sdcard_recvbyte(card)) { + spi_sdcard_disable_cs(card); + return -1; + } + + /* disable cs */ + spi_sdcard_disable_cs(card); + + return 0; +} + +int spi_sdcard_multiple_read(const struct spi_sdcard *card, + size_t start_block_address, + size_t end_block_address, + void *buff) +{ + int wait; + int block_num = end_block_address - start_block_address + 1; + if (card->type == SDCARD_TYPE_SDSC) { + start_block_address = start_block_address * 512; + end_block_address = end_block_address * 512; + } + /* CMD18, start multiple block read */ + if (spi_sdcard_do_command(card, + READ_MULTIPLEBLOCK, start_block_address, NULL)) + return -1; + + /* enable cs */ + spi_sdcard_enable_cs(card); + + for (int i = 0; i < block_num; i++) { + uint16_t c = 0; + + /* waitting start block token */ + wait = 0xffff; + while ((spi_sdcard_recvbyte(card) != CT_BLOCK_START) && --wait) + ; + if (!wait) { /* timeout */ + spi_sdcard_disable_cs(card); + return -1; + } + + /* receive data */ + for (int k = 0; k < 512; k++) { + uint8_t tmp = spi_sdcard_recvbyte(card); + ((uint8_t *)buff)[512 * i + k] = tmp; + c = crc16_byte(c, tmp); + } + + /* receive crc and verify check sum */ + if (((c >> 8) & 0xff) != spi_sdcard_recvbyte(card)) { + spi_sdcard_disable_cs(card); + return -1; + } + if (((c >> 0) & 0xff) != spi_sdcard_recvbyte(card)) { + spi_sdcard_disable_cs(card); + return -1; + } + } + + /* disable cs */ + spi_sdcard_disable_cs(card); + + if (spi_sdcard_do_command(card, STOP_TRANSMISSION, 0, NULL)) + if (spi_sdcard_do_command(card, SEND_STATUS, 0, NULL)) + return -1; + + return 0; +} + +int spi_sdcard_read(const struct spi_sdcard *card, + void *dest, + size_t offset, + size_t count) +{ + size_t start_block_address = offset / BLOCK_SIZE; + size_t end_block_address = (offset + count - 1) / BLOCK_SIZE; + size_t has_begin = !!(offset % BLOCK_SIZE); + size_t has_end = !!((offset + count) % BLOCK_SIZE); + + if (start_block_address == end_block_address) { + uint8_t tmp[BLOCK_SIZE]; + size_t o = offset % BLOCK_SIZE; + size_t l = count; + if (spi_sdcard_single_read(card, start_block_address, tmp)) + return -1; + memcpy(dest, tmp + o, l); + return 0; + } + + if (has_begin) { + uint8_t tmp[BLOCK_SIZE]; + size_t o = offset % BLOCK_SIZE; + size_t l = BLOCK_SIZE - o; + if (spi_sdcard_single_read(card, start_block_address, tmp)) + return -1; + memcpy(dest, tmp + o, l); + } + + if (start_block_address + has_begin <= end_block_address - has_end) { + size_t start_lba = start_block_address + has_begin; + size_t end_lba = end_block_address - has_end; + size_t o = has_begin ? BLOCK_SIZE - offset % BLOCK_SIZE : 0; + if (start_lba < end_lba) { + if (spi_sdcard_multiple_read(card, start_lba, end_lba, + dest + o)) + return -1; + } else { + if (spi_sdcard_single_read(card, start_lba, dest + o)) + return -1; + } + } + + if (has_end) { + uint8_t tmp[BLOCK_SIZE]; + size_t o = 0; + size_t l = (offset + count) % BLOCK_SIZE; + if (spi_sdcard_single_read(card, end_block_address, tmp)) + return -1; + memcpy(dest + count - l, tmp + o, l); + } + + return 0; +} + +int spi_sdcard_single_write(const struct spi_sdcard *card, + size_t block_address, + void *buff) +{ + int wait; + uint16_t c = 0; + if (card->type == SDCARD_TYPE_SDSC) + block_address = block_address * 512; + + if (spi_sdcard_do_command(card, WRITE_BLOCK, block_address, NULL)) + return -1; + + /* eanbele cs */ + spi_sdcard_enable_cs(card); + + /* send start block token */ + spi_sdcard_sendbyte(card, CT_BLOCK_START); + + /* send data */ + for (int i = 0; i < 512; i++) { + spi_sdcard_sendbyte(card, ((uint8_t *)buff)[i]); + c = crc16_byte(c, ((uint8_t *)buff)[i]); + } + + /* send crc check sum */ + spi_sdcard_sendbyte(card, 0xff & (c >> 8)); + spi_sdcard_sendbyte(card, 0xff & (c >> 0)); + + /* recevie and verify data response token */ + c = spi_sdcard_recvbyte(card); + if ((c & CT_RESPONSE_MASK) != CT_RESPONSE_ACCEPTED) { + spi_sdcard_disable_cs(card); + return -1; + } + + wait = 0xffff; + while ((spi_sdcard_recvbyte(card) == 0) && --wait) + ;/* wait for complete */ + if (!wait) { + spi_sdcard_disable_cs(card); + return -1; + } + + /* disable cs */ + spi_sdcard_disable_cs(card); + + return 0; +} + +int spi_sdcard_multiple_write(const struct spi_sdcard *card, + size_t start_block_address, + size_t end_block_address, + void *buff) +{ + int wait, ret = 0; + int block_num = end_block_address - start_block_address + 1; + if (card->type == SDCARD_TYPE_SDSC) { + start_block_address = start_block_address * 512; + end_block_address = end_block_address * 512; + } + + if (spi_sdcard_do_command(card, WRITE_MULTIPLEBLOCK, + start_block_address, NULL)) + return -1; + + /* enable cs */ + spi_sdcard_enable_cs(card); + + for (int i = 0; i < block_num; i++) { + uint16_t c = 0; + + ret = -1; + + /* send start block token */ + spi_sdcard_sendbyte(card, CT_MULTIPLE_BLOCK_START); + + /* send data */ + for (int k = 0; k < 512; k++) { + uint8_t tmp = ((uint8_t *)buff)[512 * i + k]; + spi_sdcard_sendbyte(card, tmp); + c = crc16_byte(c, tmp); + } + + /* send crc check sum */ + spi_sdcard_sendbyte(card, 0xff & (c >> 8)); + spi_sdcard_sendbyte(card, 0xff & (c >> 0)); + + /* recevie and verify data response token */ + c = spi_sdcard_recvbyte(card); + if ((c & CT_RESPONSE_MASK) != CT_RESPONSE_ACCEPTED) + break; + + wait = 0xffff; + while ((spi_sdcard_recvbyte(card) == 0) && --wait) + ;/* wait for complete */ + if (!wait) + break; + + ret = 0; + } + + /* send stop transmission token */ + spi_sdcard_sendbyte(card, CT_MULTIPLE_BLOCK_STOP); + + /* disable cs */ + spi_sdcard_disable_cs(card); + + if (spi_sdcard_do_command(card, STOP_TRANSMISSION, 0, NULL)) + if (spi_sdcard_do_command(card, SEND_STATUS, 0, NULL)) + return -1; + + return ret; +} + +int spi_sdcard_erase(const struct spi_sdcard *card, + size_t start_block_address, + size_t end_block_address) +{ + if (card->type == SDCARD_TYPE_SDSC) { + start_block_address = start_block_address * 512; + end_block_address = end_block_address * 512; + } + + /* CMD32, set erase start address */ + if (spi_sdcard_do_command(card, ERASE_WR_BLK_START_ADDR, + start_block_address, NULL)) + return -1; + + /* CMD33, set erase end address */ + if (spi_sdcard_do_command(card, ERASE_WR_BLK_END_ADDR, + end_block_address, NULL)) + return -1; + + /* CMD38, erase */ + if (spi_sdcard_do_command(card, ERASE, 0, NULL)) + return -1; + + return 0; +} + +int spi_sdcard_erase_all(const struct spi_sdcard *card) +{ + return spi_sdcard_erase(card, 0, spi_sdcard_size(card) / BLOCK_SIZE); +} diff --git a/src/include/spi_sdcard.h b/src/include/spi_sdcard.h new file mode 100644 index 0000000000..ca0dd1d10a --- /dev/null +++ b/src/include/spi_sdcard.h @@ -0,0 +1,60 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 HardenedLinux + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _SPI_SDCARD_H_ +#define _SPI_SDCARD_H_ + +struct spi_sdcard { + int type; + struct spi_slave slave; +}; + +int spi_sdcard_init(struct spi_sdcard *card, + const unsigned int bus, + const unsigned int cs); + +int spi_sdcard_single_read(const struct spi_sdcard *card, + size_t block_address, + void *buff); + +int spi_sdcard_multiple_read(const struct spi_sdcard *card, + size_t start_block_address, + size_t end_block_address, + void *buff); + +int spi_sdcard_single_write(const struct spi_sdcard *card, + size_t block_address, + void *buff); + +int spi_sdcard_read(const struct spi_sdcard *card, + void *dest, + size_t offset, + size_t count); + +int spi_sdcard_multiple_write(const struct spi_sdcard *card, + size_t start_block_address, + size_t end_block_address, + void *buff); + +int spi_sdcard_erase(const struct spi_sdcard *card, + size_t start_block_address, + size_t end_block_address); + +int spi_sdcard_erase_all(const struct spi_sdcard *card); + +/* get the sdcard size in bytes */ +size_t spi_sdcard_size(const struct spi_sdcard *card); + +#endif /* _SPI_SDCARD_H_ */ From d5777264600bc1d611d6669688bf8a33dac966e2 Mon Sep 17 00:00:00 2001 From: Xiang Wang Date: Tue, 27 Aug 2019 16:04:54 +0800 Subject: [PATCH 0168/1242] soc/sifive/fu540: Support booting from SD card Change-Id: I18948d31c0bf0bf9d641480a35fc710b9ee8ae84 Signed-off-by: Xiang Wang Reviewed-on: https://review.coreboot.org/c/coreboot/+/35119 Tested-by: build bot (Jenkins) Reviewed-by: Arthur Heymans --- src/mainboard/sifive/hifive-unleashed/Kconfig | 1 + src/mainboard/sifive/hifive-unleashed/media.c | 72 ++++++++++++++++--- src/soc/sifive/fu540/include/soc/memlayout.ld | 2 + 3 files changed, 66 insertions(+), 9 deletions(-) diff --git a/src/mainboard/sifive/hifive-unleashed/Kconfig b/src/mainboard/sifive/hifive-unleashed/Kconfig index 24531787ef..fc9bc1eeb9 100644 --- a/src/mainboard/sifive/hifive-unleashed/Kconfig +++ b/src/mainboard/sifive/hifive-unleashed/Kconfig @@ -19,6 +19,7 @@ config BOARD_SPECIFIC_OPTIONS select BOARD_ROMSIZE_KB_32768 select MISSING_BOARD_RESET select FLATTENED_DEVICE_TREE + select SPI_SDCARD config HEAP_SIZE default 0x10000 diff --git a/src/mainboard/sifive/hifive-unleashed/media.c b/src/mainboard/sifive/hifive-unleashed/media.c index b0198a7abe..45d1f1a613 100644 --- a/src/mainboard/sifive/hifive-unleashed/media.c +++ b/src/mainboard/sifive/hifive-unleashed/media.c @@ -15,15 +15,60 @@ */ #include +#include +#include +#include +#include #include +#include +#include +#include + +/* follow is the FSBL boot device defined by ZSBL of sifive + * FSBL replaced by bootblock of coreboot + * MSEL_SPInx1 -> test if boot from memory-mapped on SPIn + * MSEL_SPInx4 -> test if boot from memory-mapped on QPIn + * MSEL_SPInSD -> test if boot from sdcard mount on SPIn */ +#define MSEL_SPI0x1(m) (((m) == 5) || ((m) == 14)) +#define MSEL_SPI0x4(m) (((m) == 6) || ((m) == 10) || ((m) == 15)) +#define MSEL_SPI1x1(m) ((m) == 12) +#define MSEL_SPI1x4(m) (((m) == 7) || ((m) == 13)) +#define MSEL_SPI1SD(m) ((m) == 8) +#define MSEL_SPI2x1(m) ((m) == 9) +#define MSEL_SPI2SD(m) ((m) == 11) + +static struct spi_sdcard card; /* At 0x20000000: A 256MiB long memory-mapped view of the flash at QSPI0 */ -static struct mem_region_device mdev = +static struct mem_region_device spi_mdev = MEM_REGION_DEV_RO_INIT((void *)0x20000000, CONFIG_ROM_SIZE); +static ssize_t unleashed_sd_readat(const struct region_device *rdev, void *dest, + size_t offset, size_t count) +{ + spi_sdcard_read(&card, dest, offset, count); + return count; +} + +static const struct region_device_ops unleashed_sd_ops = { + .mmap = mmap_helper_rdev_mmap, + .munmap = mmap_helper_rdev_munmap, + .readat = unleashed_sd_readat, +}; + + +static struct mmap_helper_region_device sd_mdev = + MMAP_HELPER_REGION_INIT(&unleashed_sd_ops, 0, CONFIG_ROM_SIZE); + const struct region_device *boot_device_ro(void) { - return &mdev.rdev; + uint32_t m = read32((uint32_t *)FU540_MSEL); + if (MSEL_SPI0x1(m) || MSEL_SPI0x4(m)) + return &spi_mdev.rdev; + if (MSEL_SPI2SD(m)) + return &sd_mdev.rdev; + die("Wrong configuration of MSEL\n"); + return NULL; } const static struct fu540_spi_mmap_config spi_mmap_config = { @@ -39,11 +84,20 @@ const static struct fu540_spi_mmap_config spi_mmap_config = { void boot_device_init(void) { - struct spi_slave slave; - - /* initialize spi controller */ - spi_setup_slave(0, 0, &slave); - - /* map flash to memory space */ - fu540_spi_mmap(&slave, &spi_mmap_config); + uint32_t m = read32((uint32_t *)FU540_MSEL); + if (MSEL_SPI0x1(m) || MSEL_SPI0x4(m)) { + struct spi_slave slave; + /* initialize spi controller */ + spi_setup_slave(0, 0, &slave); + /* map flash to memory space */ + fu540_spi_mmap(&slave, &spi_mmap_config); + return; + } + if (MSEL_SPI2SD(m)) { + spi_sdcard_init(&card, 2, 0); + mmap_helper_device_init(&sd_mdev, + _cbfs_cache, REGION_SIZE(cbfs_cache)); + return; + } + die("Wrong configuration of MSEL\n"); } diff --git a/src/soc/sifive/fu540/include/soc/memlayout.ld b/src/soc/sifive/fu540/include/soc/memlayout.ld index 1d11aa0452..df30ede510 100644 --- a/src/soc/sifive/fu540/include/soc/memlayout.ld +++ b/src/soc/sifive/fu540/include/soc/memlayout.ld @@ -28,10 +28,12 @@ SECTIONS CAR_STACK(FU540_L2LIM + 64K, 20K) PRERAM_CBMEM_CONSOLE(FU540_L2LIM + 84K, 8K) ROMSTAGE(FU540_L2LIM + 128K, 128K) + PRERAM_CBFS_CACHE(FU540_L2LIM + 256K, 128K) L2LIM_END(FU540_L2LIM + 2M) DRAM_START(FU540_DRAM) REGION(opensbi, FU540_DRAM, 128K, 4K) RAMSTAGE(FU540_DRAM + 128K, 256K) MEM_STACK(FU540_DRAM + 448K, 20K) + POSTRAM_CBFS_CACHE(FU540_DRAM + 512K, 32M - 512K) } From dd0dc1ac9234fd2d6e786146739172eba0d4564f Mon Sep 17 00:00:00 2001 From: Wim Vervoorn Date: Thu, 14 Nov 2019 14:42:24 +0100 Subject: [PATCH 0169/1242] security/intel: Hide Intel submenu when INTEL TXT is disabled An empty submenu Intel is displayed in security menu when INTEL_TXT is disabled. Enable submenu Intel only when INTEL_TXT is enabled. BUG=N/A TEST=build Change-Id: Iff1d84ff60a15259b60c6205a63a27ecb26346a3 Signed-off-by: Wim Vervoorn Reviewed-on: https://review.coreboot.org/c/coreboot/+/36852 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber --- src/security/intel/Kconfig | 4 ---- src/security/intel/txt/Kconfig | 4 ++++ 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/src/security/intel/Kconfig b/src/security/intel/Kconfig index 333e3857ac..a4525e7b9b 100644 --- a/src/security/intel/Kconfig +++ b/src/security/intel/Kconfig @@ -13,8 +13,4 @@ ## GNU General Public License for more details. ## -menu "Intel" - source "src/security/intel/txt/Kconfig" - -endmenu # Intel diff --git a/src/security/intel/txt/Kconfig b/src/security/intel/txt/Kconfig index 011a41cdc3..97d24fd6c9 100644 --- a/src/security/intel/txt/Kconfig +++ b/src/security/intel/txt/Kconfig @@ -26,6 +26,8 @@ config INTEL_TXT if INTEL_TXT +menu "Intel" + config INTEL_TXT_BIOSACM_FILE string "BIOS ACM file" default "3rdparty/blobs/soc/intel/fsp_broadwell_de/biosacm.bin" if SOC_INTEL_FSP_BROADWELL_DE @@ -51,4 +53,6 @@ config INTEL_TXT_BIOSACM_ALIGNMENT Exceptions are Ivy- and Sandy Bridge with 64KB and Purely with 256KB alignment size. Please overwrite it SoC specific. +endmenu # Intel + endif From 211792feaba4a5cc26b4e3f17e905c3e899eb07f Mon Sep 17 00:00:00 2001 From: Julius Werner Date: Wed, 13 Nov 2019 11:28:27 -0800 Subject: [PATCH 0170/1242] rockchip/rk3288: Split free SRAM more evenly between stages When CB:33068 disabled the bootblock console on RK3288, it saved a whooping 7K of SRAM, but it didn't readjust the stage boundaries to spread that bounty evenly. This patch moves 4K of free space from the bootblock to verstage/romstage to allow for future expansion. Change-Id: I68a09ba80bde0d4f17fba1f7b38c63b7cf2a4672 Signed-off-by: Julius Werner Reviewed-on: https://review.coreboot.org/c/coreboot/+/36826 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi --- src/soc/rockchip/rk3288/include/soc/memlayout.ld | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/src/soc/rockchip/rk3288/include/soc/memlayout.ld b/src/soc/rockchip/rk3288/include/soc/memlayout.ld index 94a672db0c..f8e186c9d6 100644 --- a/src/soc/rockchip/rk3288/include/soc/memlayout.ld +++ b/src/soc/rockchip/rk3288/include/soc/memlayout.ld @@ -30,10 +30,10 @@ SECTIONS SRAM_START(0xFF700000) TTB(0xFF700000, 16K) - BOOTBLOCK(0xFF704004, 20K - 4) - PRERAM_CBMEM_CONSOLE(0xFF709000, 2K) - VBOOT2_WORK(0xFF709800, 12K) - OVERLAP_VERSTAGE_ROMSTAGE(0xFF70C800, 42K + 768) + BOOTBLOCK(0xFF704004, 16K - 4) + PRERAM_CBMEM_CONSOLE(0xFF708000, 2K) + VBOOT2_WORK(0xFF708800, 12K) + OVERLAP_VERSTAGE_ROMSTAGE(0xFF70B800, 46K + 768) PRERAM_CBFS_CACHE(0xFF717300, 256) TIMESTAMP(0xFF717400, 0x180) STACK(0xFF717580, 3K - 0x180) From d3c58fdc6436b2c4455b07fe764fcae471a65433 Mon Sep 17 00:00:00 2001 From: Arthur Heymans Date: Sun, 27 Oct 2019 07:13:55 +0100 Subject: [PATCH 0171/1242] soc/qualcomm: Link cbmem.c only in romstage Change-Id: I008fcca024fecf462c4b550b8dedbf4b06e491b8 Signed-off-by: Arthur Heymans Reviewed-on: https://review.coreboot.org/c/coreboot/+/36368 Reviewed-by: Nico Huber Reviewed-by: Patrick Rudolph Tested-by: build bot (Jenkins) --- src/mainboard/google/gale/mmu.c | 3 ++- src/mainboard/google/storm/mmu.c | 7 +++---- src/soc/qualcomm/ipq40xx/Makefile.inc | 2 -- src/soc/qualcomm/ipq40xx/cbmem.c | 2 +- src/soc/qualcomm/ipq806x/Makefile.inc | 1 - src/soc/qualcomm/ipq806x/cbmem.c | 2 +- 6 files changed, 7 insertions(+), 10 deletions(-) diff --git a/src/mainboard/google/gale/mmu.c b/src/mainboard/google/gale/mmu.c index bf46f7a0d9..7ac8b9207a 100644 --- a/src/mainboard/google/gale/mmu.c +++ b/src/mainboard/google/gale/mmu.c @@ -38,7 +38,8 @@ void setup_dram_mappings(enum dram_state dram) /* Map DMA memory */ mmu_config_range(DMA_START, DMA_SIZE, DCACHE_OFF); /* Mark cbmem backing store as ready. */ - ipq_cbmem_backing_store_ready(); + if (ENV_ROMSTAGE) + ipq_cbmem_backing_store_ready(); } else { mmu_disable_range(DRAM_START, DRAM_SIZE); /* Map DMA memory */ diff --git a/src/mainboard/google/storm/mmu.c b/src/mainboard/google/storm/mmu.c index 9750cc16e8..3f1515ab06 100644 --- a/src/mainboard/google/storm/mmu.c +++ b/src/mainboard/google/storm/mmu.c @@ -35,10 +35,9 @@ void setup_dram_mappings(enum dram_state dram) mmu_config_range(DRAM_START, DRAM_SIZE, DCACHE_WRITEBACK); /* Map DMA memory */ mmu_config_range(DMA_START, DMA_SIZE, DCACHE_OFF); -#if ENV_ROMSTAGE - /* Mark cbmem backing store as ready. */ - ipq_cbmem_backing_store_ready(); -#endif + if (ENV_ROMSTAGE) + /* Mark cbmem backing store as ready. */ + ipq_cbmem_backing_store_ready(); } else { mmu_disable_range(DRAM_START, DRAM_SIZE); /* Map DMA memory */ diff --git a/src/soc/qualcomm/ipq40xx/Makefile.inc b/src/soc/qualcomm/ipq40xx/Makefile.inc index 6447acf1d6..b20ae24d60 100644 --- a/src/soc/qualcomm/ipq40xx/Makefile.inc +++ b/src/soc/qualcomm/ipq40xx/Makefile.inc @@ -16,7 +16,6 @@ ifeq ($(CONFIG_SOC_QC_IPQ40XX),y) bootblock-y += clock.c -bootblock-y += cbmem.c bootblock-y += gpio.c bootblock-$(CONFIG_SPI_FLASH) += spi.c bootblock-y += timer.c @@ -43,7 +42,6 @@ romstage-y += blsp.c romstage-y += qup.c ramstage-y += blobs_init.c -ramstage-y += cbmem.c ramstage-y += clock.c ramstage-y += gpio.c ramstage-y += lcc.c diff --git a/src/soc/qualcomm/ipq40xx/cbmem.c b/src/soc/qualcomm/ipq40xx/cbmem.c index 972c6258c9..9970758d91 100644 --- a/src/soc/qualcomm/ipq40xx/cbmem.c +++ b/src/soc/qualcomm/ipq40xx/cbmem.c @@ -31,7 +31,7 @@ void *cbmem_top_chipset(void) * with components that utilize cbmem in romstage (e.g. vboot_locator * for loading ipq blobs before DRAM is initialized). */ - if (ENV_ROMSTAGE && (cbmem_backing_store_ready == 0)) + if (cbmem_backing_store_ready == 0) return NULL; return _memlayout_cbmem_top; diff --git a/src/soc/qualcomm/ipq806x/Makefile.inc b/src/soc/qualcomm/ipq806x/Makefile.inc index 1fd134a7b3..67d54d2b98 100644 --- a/src/soc/qualcomm/ipq806x/Makefile.inc +++ b/src/soc/qualcomm/ipq806x/Makefile.inc @@ -42,7 +42,6 @@ romstage-y += gsbi.c romstage-y += qup.c ramstage-y += blobs_init.c -ramstage-y += cbmem.c ramstage-y += clock.c ramstage-y += gpio.c ramstage-y += lcc.c diff --git a/src/soc/qualcomm/ipq806x/cbmem.c b/src/soc/qualcomm/ipq806x/cbmem.c index 6dc92a0c11..32f303e81e 100644 --- a/src/soc/qualcomm/ipq806x/cbmem.c +++ b/src/soc/qualcomm/ipq806x/cbmem.c @@ -32,7 +32,7 @@ void *cbmem_top_chipset(void) * (e.g. vboot_locator for loading ipq blobs before DRAM is * initialized). */ - if (ENV_ROMSTAGE && (cbmem_backing_store_ready == 0)) + if (cbmem_backing_store_ready == 0) return NULL; return _memlayout_cbmem_top; From 2332c7459ebb81c4dd4c3cc8b19beca820e93968 Mon Sep 17 00:00:00 2001 From: Joel Kitching Date: Wed, 23 Oct 2019 15:01:37 +0800 Subject: [PATCH 0172/1242] vboot: use vboot persistent context vb2_context object is now stored on the workbuf as part of vb2_shared_data. Use vboot's new API functions vb2api_init and vb2api_relocate to create and move the workbuf. BUG=b:124141368, chromium:994060 TEST=Build locally BRANCH=none Change-Id: I051be1e47bf79b15a1689d49a5d4c031e9363dfa Signed-off-by: Joel Kitching Also-Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/third_party/coreboot/+/1902339 Reviewed-on: https://review.coreboot.org/c/coreboot/+/36300 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi Reviewed-by: Stefan Reinauer Reviewed-by: Maulik V Vaghela --- 3rdparty/vboot | 2 +- src/mainboard/google/drallion/chromeos.c | 4 +- src/mainboard/google/sarien/chromeos.c | 4 +- src/security/vboot/bootmode.c | 2 +- src/security/vboot/common.c | 74 ++++++++++++++---------- src/security/vboot/misc.h | 13 ++--- src/security/vboot/vboot_logic.c | 69 +++++++++++----------- 7 files changed, 89 insertions(+), 79 deletions(-) diff --git a/3rdparty/vboot b/3rdparty/vboot index 87276ffed4..ecdca931ae 160000 --- a/3rdparty/vboot +++ b/3rdparty/vboot @@ -1 +1 @@ -Subproject commit 87276ffed46b3c64ff62153ac8599a79b9bcb683 +Subproject commit ecdca931ae0637d1a9498f64862939bd5bb99e0b diff --git a/src/mainboard/google/drallion/chromeos.c b/src/mainboard/google/drallion/chromeos.c index 0eb311bb9d..00571ed6bc 100644 --- a/src/mainboard/google/drallion/chromeos.c +++ b/src/mainboard/google/drallion/chromeos.c @@ -95,8 +95,8 @@ int get_recovery_mode_switch(void) * and the value from the TPM would be wrong anyway since the verstage * read would have cleared the value on the TPM. * - * The TPM recovery request is passed between stages through the - * vboot_get_shared_data or cbmem depending on stage. + * The TPM recovery request is passed between stages through vboot data + * or cbmem depending on stage. */ if (ENV_VERSTAGE && tlcl_cr50_get_recovery_button(&cr50_state) == TPM_SUCCESS && diff --git a/src/mainboard/google/sarien/chromeos.c b/src/mainboard/google/sarien/chromeos.c index 6643d9b55d..bdd414c77c 100644 --- a/src/mainboard/google/sarien/chromeos.c +++ b/src/mainboard/google/sarien/chromeos.c @@ -93,8 +93,8 @@ int get_recovery_mode_switch(void) * and the value from the TPM would be wrong anyway since the verstage * read would have cleared the value on the TPM. * - * The TPM recovery request is passed between stages through the - * vboot_get_shared_data or cbmem depending on stage. + * The TPM recovery request is passed between stages through vboot data + * or cbmem depending on stage. */ if (ENV_VERSTAGE && tlcl_cr50_get_recovery_button(&cr50_state) == TPM_SUCCESS && diff --git a/src/security/vboot/bootmode.c b/src/security/vboot/bootmode.c index 4625bcdff2..0ab0431f46 100644 --- a/src/security/vboot/bootmode.c +++ b/src/security/vboot/bootmode.c @@ -26,7 +26,7 @@ static int vboot_get_recovery_reason_shared_data(void) { - struct vb2_shared_data *sd = vboot_get_shared_data(); + struct vb2_shared_data *sd = vb2_get_sd(vboot_get_context()); assert(sd); return sd->recovery_reason; } diff --git a/src/security/vboot/common.c b/src/security/vboot/common.c index 626fbc52a4..043748cbef 100644 --- a/src/security/vboot/common.c +++ b/src/security/vboot/common.c @@ -24,6 +24,8 @@ #include #include +static struct vb2_context *vboot_ctx CAR_GLOBAL; + struct vboot_working_data *vboot_get_working_data(void) { struct vboot_working_data *wd = NULL; @@ -40,43 +42,45 @@ struct vboot_working_data *vboot_get_working_data(void) return wd; } -void vboot_init_work_context(struct vb2_context *ctx) +static inline void *vboot_get_workbuf(struct vboot_working_data *wd) { + return (void *)((uintptr_t)wd + wd->buffer_offset); +} + +struct vb2_context *vboot_get_context(void) +{ + struct vb2_context **vboot_ctx_ptr = car_get_var_ptr(&vboot_ctx); struct vboot_working_data *wd; - /* First initialize the working data region. */ + /* Return if context has already been initialized/restored. */ + if (*vboot_ctx_ptr) + return *vboot_ctx_ptr; + wd = vboot_get_working_data(); - memset(wd, 0, VB2_FIRMWARE_WORKBUF_RECOMMENDED_SIZE); + + /* Restore context from a previous stage. */ + if (vboot_logic_executed()) { + assert(vb2api_reinit(vboot_get_workbuf(wd), + vboot_ctx_ptr) == VB2_SUCCESS); + return *vboot_ctx_ptr; + } + + assert(verification_should_run()); /* * vboot prefers 16-byte alignment. This takes away 16 bytes * from the VBOOT2_WORK region, but the vboot devs said that's okay. */ + memset(wd, 0, sizeof(*wd)); wd->buffer_offset = ALIGN_UP(sizeof(*wd), 16); wd->buffer_size = VB2_FIRMWARE_WORKBUF_RECOMMENDED_SIZE - wd->buffer_offset; - /* Initialize the vb2_context. */ - memset(ctx, 0, sizeof(*ctx)); - ctx->workbuf = (void *)vboot_get_shared_data(); - ctx->workbuf_size = wd->buffer_size; -} + /* Initialize vb2_shared_data and friends. */ + assert(vb2api_init(vboot_get_workbuf(wd), wd->buffer_size, + vboot_ctx_ptr) == VB2_SUCCESS); -void vboot_finalize_work_context(struct vb2_context *ctx) -{ - /* - * Shrink buffer_size so that vboot_migrate_cbmem knows how - * much of vboot_working_data needs to be copied into CBMEM - * (if applicable), and so that downstream users know how much - * of the workbuf is currently used. - */ - vboot_get_working_data()->buffer_size = ctx->workbuf_used; -} - -struct vb2_shared_data *vboot_get_shared_data(void) -{ - struct vboot_working_data *wd = vboot_get_working_data(); - return (void *)((uintptr_t)wd + wd->buffer_offset); + return *vboot_ctx_ptr; } int vboot_get_selected_region(struct region *region) @@ -126,17 +130,25 @@ int vboot_is_slot_selected(void) */ static void vboot_migrate_cbmem(int unused) { - const struct vboot_working_data *wd_preram = + const size_t cbmem_size = VB2_KERNEL_WORKBUF_RECOMMENDED_SIZE; + struct vboot_working_data *wd_preram = (struct vboot_working_data *)_vboot2_work; - size_t cbmem_size = wd_preram->buffer_offset + wd_preram->buffer_size; struct vboot_working_data *wd_cbmem = cbmem_add(CBMEM_ID_VBOOT_WORKBUF, cbmem_size); assert(wd_cbmem != NULL); - - printk(BIOS_DEBUG, - "VBOOT: copying vboot_working_data (%zu bytes) to CBMEM...\n", - cbmem_size); - memcpy(wd_cbmem, wd_preram, cbmem_size); + memcpy(wd_cbmem, wd_preram, sizeof(struct vboot_working_data)); + /* + * TODO(chromium:1021452): buffer_size is uint16_t and not large enough + * to hold the kernel verification workbuf size. The only code which + * reads this value is in lb_vboot_workbuf() for lb_range->range_size. + * This value being zero doesn't cause any problems, since it is never + * read downstream. Fix or deprecate vboot_working_data. + */ + wd_cbmem->buffer_size = 0; + vb2api_relocate(vboot_get_workbuf(wd_cbmem), + vboot_get_workbuf(wd_preram), + cbmem_size - wd_cbmem->buffer_offset, + car_get_var_ptr(&vboot_ctx)); } ROMSTAGE_CBMEM_INIT_HOOK(vboot_migrate_cbmem) #else @@ -144,7 +156,7 @@ static void vboot_setup_cbmem(int unused) { struct vboot_working_data *wd_cbmem = cbmem_add(CBMEM_ID_VBOOT_WORKBUF, - VB2_FIRMWARE_WORKBUF_RECOMMENDED_SIZE); + VB2_KERNEL_WORKBUF_RECOMMENDED_SIZE); assert(wd_cbmem != NULL); } ROMSTAGE_CBMEM_INIT_HOOK(vboot_setup_cbmem) diff --git a/src/security/vboot/misc.h b/src/security/vboot/misc.h index 1458354ffc..b45fc9c60d 100644 --- a/src/security/vboot/misc.h +++ b/src/security/vboot/misc.h @@ -29,10 +29,11 @@ struct selected_region { }; /* - * this is placed at the start of the vboot work buffer. selected_region is used - * for the verstage to return the location of the selected slot. buffer is used - * by the vboot2 core. Keep the struct CPU architecture agnostic as it crosses - * stage boundaries. + * Stores vboot-related information. selected_region is used by verstage to + * store the location of the selected slot. buffer is used by vboot to store + * its work buffer. vb2_context is contained within this work buffer, and is + * accessible via vboot_init_context() and vboot_get_context() (see below). + * Keep the struct CPU architecture agnostic as it crosses stage boundaries. */ struct vboot_working_data { struct selected_region selected_region; @@ -54,9 +55,7 @@ struct vboot_working_data { * Source: security/vboot/common.c */ struct vboot_working_data *vboot_get_working_data(void); -void vboot_init_work_context(struct vb2_context *ctx); -void vboot_finalize_work_context(struct vb2_context *ctx); -struct vb2_shared_data *vboot_get_shared_data(void); +struct vb2_context *vboot_get_context(void); /* Returns 0 on success. < 0 on failure. */ int vboot_get_selected_region(struct region *region); diff --git a/src/security/vboot/vboot_logic.c b/src/security/vboot/vboot_logic.c index da6231ae65..511014711d 100644 --- a/src/security/vboot/vboot_logic.c +++ b/src/security/vboot/vboot_logic.c @@ -319,17 +319,17 @@ ROMSTAGE_CBMEM_INIT_HOOK(vboot_log_and_clear_recovery_mode_switch) */ void verstage_main(void) { - struct vb2_context ctx; + struct vb2_context *ctx; struct region_device fw_main; vb2_error_t rv; timestamp_add_now(TS_START_VBOOT); /* Set up context and work buffer */ - vboot_init_work_context(&ctx); + ctx = vboot_get_context(); /* Initialize and read nvdata from non-volatile storage. */ - vbnv_init(ctx.nvdata); + vbnv_init(ctx->nvdata); /* Set S3 resume flag if vboot should behave differently when selecting * which slot to boot. This is only relevant to vboot if the platform @@ -337,51 +337,51 @@ void verstage_main(void) * the same slot that it booted from. */ if (CONFIG(RESUME_PATH_SAME_AS_BOOT) && vboot_platform_is_resuming()) - ctx.flags |= VB2_CONTEXT_S3_RESUME; + ctx->flags |= VB2_CONTEXT_S3_RESUME; /* Read secdata from TPM. Initialize TPM if secdata not found. We don't * check the return value here because vb2api_fw_phase1 will catch * invalid secdata and tell us what to do (=reboot). */ timestamp_add_now(TS_START_TPMINIT); - if (vboot_setup_tpm(&ctx) == TPM_SUCCESS) - antirollback_read_space_firmware(&ctx); + if (vboot_setup_tpm(ctx) == TPM_SUCCESS) + antirollback_read_space_firmware(ctx); timestamp_add_now(TS_END_TPMINIT); /* Enable measured boot mode */ if (CONFIG(VBOOT_MEASURED_BOOT) && - !(ctx.flags & VB2_CONTEXT_S3_RESUME)) { + !(ctx->flags & VB2_CONTEXT_S3_RESUME)) { if (vboot_init_crtm() != VB2_SUCCESS) die_with_post_code(POST_INVALID_ROM, "Initializing measured boot mode failed!"); } if (get_recovery_mode_switch()) { - ctx.flags |= VB2_CONTEXT_FORCE_RECOVERY_MODE; + ctx->flags |= VB2_CONTEXT_FORCE_RECOVERY_MODE; if (CONFIG(VBOOT_DISABLE_DEV_ON_RECOVERY)) - ctx.flags |= VB2_CONTEXT_DISABLE_DEVELOPER_MODE; + ctx->flags |= VB2_CONTEXT_DISABLE_DEVELOPER_MODE; } if (CONFIG(VBOOT_WIPEOUT_SUPPORTED) && get_wipeout_mode_switch()) - ctx.flags |= VB2_CONTEXT_FORCE_WIPEOUT_MODE; + ctx->flags |= VB2_CONTEXT_FORCE_WIPEOUT_MODE; if (CONFIG(VBOOT_LID_SWITCH) && !get_lid_switch()) - ctx.flags |= VB2_CONTEXT_NOFAIL_BOOT; + ctx->flags |= VB2_CONTEXT_NOFAIL_BOOT; /* Mainboard/SoC always initializes display. */ if (!CONFIG(VBOOT_MUST_REQUEST_DISPLAY)) - ctx.flags |= VB2_CONTEXT_DISPLAY_INIT; + ctx->flags |= VB2_CONTEXT_DISPLAY_INIT; /* Do early init (set up secdata and NVRAM, load GBB) */ printk(BIOS_INFO, "Phase 1\n"); - rv = vb2api_fw_phase1(&ctx); + rv = vb2api_fw_phase1(ctx); /* Jot down some information from vboot which may be required later on in coreboot boot flow. */ - if (ctx.flags & VB2_CONTEXT_DISPLAY_INIT) + if (ctx->flags & VB2_CONTEXT_DISPLAY_INIT) /* Mainboard/SoC should initialize display. */ vboot_get_working_data()->flags |= VBOOT_WD_FLAG_DISPLAY_INIT; - if (ctx.flags & VB2_CONTEXT_DEVELOPER_MODE) + if (ctx->flags & VB2_CONTEXT_DEVELOPER_MODE) vboot_get_working_data()->flags |= VBOOT_WD_FLAG_DEVELOPER_MODE; if (rv) { @@ -393,58 +393,58 @@ void verstage_main(void) */ if (rv == VB2_ERROR_API_PHASE1_RECOVERY) { printk(BIOS_INFO, "Recovery requested (%x)\n", rv); - save_if_needed(&ctx); - extend_pcrs(&ctx); /* ignore failures */ + save_if_needed(ctx); + extend_pcrs(ctx); /* ignore failures */ goto verstage_main_exit; } printk(BIOS_INFO, "Reboot requested (%x)\n", rv); - save_if_needed(&ctx); + save_if_needed(ctx); vboot_reboot(); } /* Determine which firmware slot to boot (based on NVRAM) */ printk(BIOS_INFO, "Phase 2\n"); - rv = vb2api_fw_phase2(&ctx); + rv = vb2api_fw_phase2(ctx); if (rv) { printk(BIOS_INFO, "Reboot requested (%x)\n", rv); - save_if_needed(&ctx); + save_if_needed(ctx); vboot_reboot(); } /* Try that slot (verify its keyblock and preamble) */ printk(BIOS_INFO, "Phase 3\n"); timestamp_add_now(TS_START_VERIFY_SLOT); - rv = vb2api_fw_phase3(&ctx); + rv = vb2api_fw_phase3(ctx); timestamp_add_now(TS_END_VERIFY_SLOT); if (rv) { printk(BIOS_INFO, "Reboot requested (%x)\n", rv); - save_if_needed(&ctx); + save_if_needed(ctx); vboot_reboot(); } printk(BIOS_INFO, "Phase 4\n"); - rv = locate_firmware(&ctx, &fw_main); + rv = locate_firmware(ctx, &fw_main); if (rv) die_with_post_code(POST_INVALID_ROM, "Failed to read FMAP to locate firmware"); - rv = hash_body(&ctx, &fw_main); - save_if_needed(&ctx); + rv = hash_body(ctx, &fw_main); + save_if_needed(ctx); if (rv) { printk(BIOS_INFO, "Reboot requested (%x)\n", rv); vboot_reboot(); } /* Only extend PCRs once on boot. */ - if (!(ctx.flags & VB2_CONTEXT_S3_RESUME)) { + if (!(ctx->flags & VB2_CONTEXT_S3_RESUME)) { timestamp_add_now(TS_START_TPMPCR); - rv = extend_pcrs(&ctx); + rv = extend_pcrs(ctx); if (rv) { printk(BIOS_WARNING, "Failed to extend TPM PCRs (%#x)\n", rv); - vb2api_fail(&ctx, VB2_RECOVERY_RO_TPM_U_ERROR, rv); - save_if_needed(&ctx); + vb2api_fail(ctx, VB2_RECOVERY_RO_TPM_U_ERROR, rv); + save_if_needed(ctx); vboot_reboot(); } timestamp_add_now(TS_END_TPMPCR); @@ -456,8 +456,8 @@ void verstage_main(void) rv = antirollback_lock_space_firmware(); if (rv) { printk(BIOS_INFO, "Failed to lock TPM (%x)\n", rv); - vb2api_fail(&ctx, VB2_RECOVERY_RO_TPM_L_ERROR, 0); - save_if_needed(&ctx); + vb2api_fail(ctx, VB2_RECOVERY_RO_TPM_L_ERROR, 0); + save_if_needed(ctx); vboot_reboot(); } timestamp_add_now(TS_END_TPMLOCK); @@ -468,14 +468,14 @@ void verstage_main(void) if (rv) { printk(BIOS_INFO, "Failed to lock rec hash space(%x)\n", rv); - vb2api_fail(&ctx, VB2_RECOVERY_RO_TPM_REC_HASH_L_ERROR, + vb2api_fail(ctx, VB2_RECOVERY_RO_TPM_REC_HASH_L_ERROR, 0); - save_if_needed(&ctx); + save_if_needed(ctx); vboot_reboot(); } } - printk(BIOS_INFO, "Slot %c is selected\n", is_slot_a(&ctx) ? 'A' : 'B'); + printk(BIOS_INFO, "Slot %c is selected\n", is_slot_a(ctx) ? 'A' : 'B'); vboot_set_selected_region(region_device_region(&fw_main)); verstage_main_exit: @@ -487,6 +487,5 @@ void verstage_main(void) /* Save recovery reason in case of unexpected reboots on x86. */ vboot_save_recovery_reason_vbnv(); - vboot_finalize_work_context(&ctx); timestamp_add_now(TS_END_VBOOT); } From 9fc8cf89e881f252ab95ce080046b3143aa0c734 Mon Sep 17 00:00:00 2001 From: Yu-Ping Wu Date: Wed, 13 Nov 2019 15:57:45 +0800 Subject: [PATCH 0173/1242] security/vboot: Remove flags from struct vboot_working_data Since now we have persistent context, the usage of the flags can be replaced with vb2_context.flags. BRANCH=none BUG=chromium:1021452 TEST=emerge-kukui coreboot Change-Id: I8e5757a8cc09712c3acde9cbaab910b7498681b4 Signed-off-by: Yu-Ping Wu Reviewed-on: https://review.coreboot.org/c/coreboot/+/36808 Tested-by: build bot (Jenkins) Reviewed-by: Julius Werner --- src/lib/bootmode.c | 6 +++--- src/security/vboot/bootmode.c | 4 ++-- src/security/vboot/misc.h | 9 --------- src/security/vboot/vboot_logic.c | 8 -------- 4 files changed, 5 insertions(+), 22 deletions(-) diff --git a/src/lib/bootmode.c b/src/lib/bootmode.c index 2465966b3a..06f6d05e47 100644 --- a/src/lib/bootmode.c +++ b/src/lib/bootmode.c @@ -16,6 +16,7 @@ #include #include #include +#include static int gfx_init_done = -1; @@ -33,14 +34,13 @@ void gfx_set_init_done(int done) int display_init_required(void) { - /* For vboot, always honor VBOOT_WD_FLAG_DISPLAY_INIT. */ + /* For vboot, always honor VB2_CONTEXT_DISPLAY_INIT. */ if (CONFIG(VBOOT)) { /* Must always select MUST_REQUEST_DISPLAY when using this function. */ if (!CONFIG(VBOOT_MUST_REQUEST_DISPLAY)) dead_code(); - return vboot_get_working_data()->flags - & VBOOT_WD_FLAG_DISPLAY_INIT; + return vboot_get_context()->flags & VB2_CONTEXT_DISPLAY_INIT; } /* By default always initialize display. */ diff --git a/src/security/vboot/bootmode.c b/src/security/vboot/bootmode.c index 0ab0431f46..bc89e732cf 100644 --- a/src/security/vboot/bootmode.c +++ b/src/security/vboot/bootmode.c @@ -148,8 +148,8 @@ int vboot_recovery_mode_memory_retrain(void) int vboot_developer_mode_enabled(void) { - return cbmem_possibly_online() && - vboot_get_working_data()->flags & VBOOT_WD_FLAG_DEVELOPER_MODE; + return vboot_logic_executed() && + vboot_get_context()->flags & VB2_CONTEXT_DEVELOPER_MODE; } #if CONFIG(VBOOT_NO_BOARD_SUPPORT) diff --git a/src/security/vboot/misc.h b/src/security/vboot/misc.h index b45fc9c60d..455773cc7c 100644 --- a/src/security/vboot/misc.h +++ b/src/security/vboot/misc.h @@ -37,20 +37,11 @@ struct selected_region { */ struct vboot_working_data { struct selected_region selected_region; - uint32_t flags; /* offset of the buffer from the start of this struct */ uint16_t buffer_offset; uint16_t buffer_size; }; -/* - * Definitions for vboot_working_data.flags values. - */ -/* vboot requests display initialization from coreboot. */ -#define VBOOT_WD_FLAG_DISPLAY_INIT (1 << 0) -/* vboot has selected developer mode. */ -#define VBOOT_WD_FLAG_DEVELOPER_MODE (1 << 1) - /* * Source: security/vboot/common.c */ diff --git a/src/security/vboot/vboot_logic.c b/src/security/vboot/vboot_logic.c index 511014711d..c4389a9bc1 100644 --- a/src/security/vboot/vboot_logic.c +++ b/src/security/vboot/vboot_logic.c @@ -376,14 +376,6 @@ void verstage_main(void) printk(BIOS_INFO, "Phase 1\n"); rv = vb2api_fw_phase1(ctx); - /* Jot down some information from vboot which may be required later on - in coreboot boot flow. */ - if (ctx->flags & VB2_CONTEXT_DISPLAY_INIT) - /* Mainboard/SoC should initialize display. */ - vboot_get_working_data()->flags |= VBOOT_WD_FLAG_DISPLAY_INIT; - if (ctx->flags & VB2_CONTEXT_DEVELOPER_MODE) - vboot_get_working_data()->flags |= VBOOT_WD_FLAG_DEVELOPER_MODE; - if (rv) { /* * If vb2api_fw_phase1 fails, check for return value. From ffe4eba38065d5acb8e74ceb3bddd21f1a0a9005 Mon Sep 17 00:00:00 2001 From: Wim Vervoorn Date: Thu, 14 Nov 2019 11:06:35 +0100 Subject: [PATCH 0174/1242] vendor/eltan/security: Removed long lines from vboot_check Removed long lines from the verified_boot_check_buffer() function. BUG=N/A TEST=build Change-Id: I2ea0ae82bd531355111d6b45c67bdc2b1759b7bc Signed-off-by: Wim Vervoorn Reviewed-on: https://review.coreboot.org/c/coreboot/+/36849 Tested-by: build bot (Jenkins) Reviewed-by: Frans Hendriks --- src/vendorcode/eltan/security/verified_boot/vboot_check.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/src/vendorcode/eltan/security/verified_boot/vboot_check.c b/src/vendorcode/eltan/security/verified_boot/vboot_check.c index c58ace1cf6..f139449651 100644 --- a/src/vendorcode/eltan/security/verified_boot/vboot_check.c +++ b/src/vendorcode/eltan/security/verified_boot/vboot_check.c @@ -142,7 +142,8 @@ static void verified_boot_check_buffer(const char *name, void *start, size_t siz else hash_algorithm = VB2_HASH_SHA256; - status = cb_sha_little_endian(hash_algorithm, (const uint8_t *)start, size, digest); + status = cb_sha_little_endian(hash_algorithm, (const uint8_t *)start, size, + digest); if ((CONFIG(VENDORCODE_ELTAN_VBOOT) && memcmp((void *)( (uint8_t *)CONFIG_VENDORCODE_ELTAN_OEM_MANIFEST_LOC + sizeof(digest) * hash_index), digest, sizeof(digest))) || status) { @@ -156,7 +157,8 @@ static void verified_boot_check_buffer(const char *name, void *start, size_t siz } else { if (!ENV_BOOTBLOCK && CONFIG(VENDORCODE_ELTAN_MBOOT)) { if (pcr != -1) { - printk(BIOS_DEBUG, "%s: measuring %s\n", __func__, name); + printk(BIOS_DEBUG, "%s: measuring %s\n", __func__, + name); if (measure_item(pcr, digest, sizeof(digest), (int8_t *)name, 0)) printk(BIOS_DEBUG, "%s: measuring failed!\n", From e4240f3e01a2bd0093d9a2a63e61319d65655e7b Mon Sep 17 00:00:00 2001 From: Wim Vervoorn Date: Wed, 13 Nov 2019 16:41:00 +0100 Subject: [PATCH 0175/1242] mb/facebook/fbg1701: Align handling of bootblock and publickey The bootblock measurement was handled using the romstage_verify_list() and the public_key in the mb_log_list. This is confusing as these are both read-only items that should be handled in the same way. Both will be handled in the romstage_verify_list(). BUG=N/A TEST=tested on fbg1701 Change-Id: If05198deec85188f39a221a8b755798755afa5bb Signed-off-by: Wim Vervoorn Reviewed-on: https://review.coreboot.org/c/coreboot/+/36814 Tested-by: build bot (Jenkins) Reviewed-by: Frans Hendriks --- src/mainboard/facebook/fbg1701/board_mboot.h | 4 ---- src/mainboard/facebook/fbg1701/board_verified_boot.c | 11 ++++++++++- 2 files changed, 10 insertions(+), 5 deletions(-) diff --git a/src/mainboard/facebook/fbg1701/board_mboot.h b/src/mainboard/facebook/fbg1701/board_mboot.h index 5a23630570..5cfb091451 100644 --- a/src/mainboard/facebook/fbg1701/board_mboot.h +++ b/src/mainboard/facebook/fbg1701/board_mboot.h @@ -23,9 +23,5 @@ const mboot_measure_item_t mb_log_list[] = { #if CONFIG(VENDORCODE_ELTAN_VBOOT) { "oemmanifest.bin", CBFS_TYPE_RAW, MBOOT_PCR_INDEX_7, EV_NO_ACTION, NULL }, -#if CONFIG(VENDORCODE_ELTAN_VBOOT_SIGNED_MANIFEST) - { "vboot_public_key.bin", CBFS_TYPE_RAW, MBOOT_PCR_INDEX_6, - EV_NO_ACTION, NULL }, -#endif #endif }; diff --git a/src/mainboard/facebook/fbg1701/board_verified_boot.c b/src/mainboard/facebook/fbg1701/board_verified_boot.c index bb5768fdc1..09f4e6791e 100644 --- a/src/mainboard/facebook/fbg1701/board_verified_boot.c +++ b/src/mainboard/facebook/fbg1701/board_verified_boot.c @@ -43,7 +43,10 @@ static const verify_item_t ram_stage_additional_list[] = { { VERIFY_TERMINATOR, NULL, { { NULL, 0 } }, 0, 0 } }; -/* The items used by the romstage */ +/* + * The items used by the romstage. Bootblock and PublicKey are added here to make sure they + * are measured + */ const verify_item_t romstage_verify_list[] = { { VERIFY_FILE, ROMSTAGE, { { NULL, CBFS_TYPE_STAGE } }, HASH_IDX_ROM_STAGE, MBOOT_PCR_INDEX_0 }, @@ -61,6 +64,12 @@ const verify_item_t romstage_verify_list[] = { { { (void *)0xffffffff - CONFIG_C_ENV_BOOTBLOCK_SIZE + 1, CONFIG_C_ENV_BOOTBLOCK_SIZE, } }, HASH_IDX_BOOTBLOCK, MBOOT_PCR_INDEX_0 }, +#if CONFIG(VENDORCODE_ELTAN_VBOOT_SIGNED_MANIFEST) + { VERIFY_BLOCK, "PublicKey", + { { (void *)CONFIG_VENDORCODE_ELTAN_VBOOT_KEY_LOCATION, + CONFIG_VENDORCODE_ELTAN_VBOOT_KEY_SIZE, } }, HASH_IDX_PUBLICKEY, + MBOOT_PCR_INDEX_6 }, +#endif { VERIFY_TERMINATOR, NULL, { { NULL, 0 } }, 0, 0 } }; From 5ec8069f8087b4c0b5a12df19a45d49613f1d984 Mon Sep 17 00:00:00 2001 From: Wim Vervoorn Date: Wed, 13 Nov 2019 16:50:00 +0100 Subject: [PATCH 0176/1242] mb/facebook/fbg1701: Correct the postcar_verify_list The postcar_verify_list should contain the items that should be verified before the postcar stage is started. BUG=N/A TEST=build Change-Id: I328858e4803873fed6d47313def5e7b9a434e8ad Signed-off-by: Wim Vervoorn Reviewed-on: https://review.coreboot.org/c/coreboot/+/36815 Tested-by: build bot (Jenkins) Reviewed-by: Frans Hendriks --- .../facebook/fbg1701/board_verified_boot.c | 15 ++------------- 1 file changed, 2 insertions(+), 13 deletions(-) diff --git a/src/mainboard/facebook/fbg1701/board_verified_boot.c b/src/mainboard/facebook/fbg1701/board_verified_boot.c index 09f4e6791e..7421a14e67 100644 --- a/src/mainboard/facebook/fbg1701/board_verified_boot.c +++ b/src/mainboard/facebook/fbg1701/board_verified_boot.c @@ -56,10 +56,6 @@ const verify_item_t romstage_verify_list[] = { MBOOT_PCR_INDEX_1 }, { VERIFY_FILE, "spd.bin", { { NULL, CBFS_TYPE_SPD } }, HASH_IDX_SPD0, MBOOT_PCR_INDEX_1 }, -#if CONFIG(POSTCAR_STAGE) - { VERIFY_FILE, POSTCAR, { { NULL, CBFS_TYPE_STAGE } }, - HASH_IDX_POSTCAR_STAGE, MBOOT_PCR_INDEX_0 }, -#endif { VERIFY_BLOCK, "BootBlock", { { (void *)0xffffffff - CONFIG_C_ENV_BOOTBLOCK_SIZE + 1, CONFIG_C_ENV_BOOTBLOCK_SIZE, } }, HASH_IDX_BOOTBLOCK, @@ -80,17 +76,10 @@ const verify_item_t ramstage_verify_list[] = { { VERIFY_TERMINATOR, NULL, { { NULL, 0 } }, 0, 0 } }; -/* POSTCAR */ /* The items used by the postcar stage */ const verify_item_t postcar_verify_list[] = { - { VERIFY_FILE, RAMSTAGE, { { ram_stage_additional_list, - CBFS_TYPE_STAGE } }, HASH_IDX_RAM_STAGE, MBOOT_PCR_INDEX_0 }, - { VERIFY_FILE, MICROCODE, { { NULL, CBFS_TYPE_MICROCODE } }, - HASH_IDX_MICROCODE, MBOOT_PCR_INDEX_1 }, - { VERIFY_FILE, FSP, { { NULL, CBFS_TYPE_FSP } }, HASH_IDX_FSP, - MBOOT_PCR_INDEX_1 }, - { VERIFY_FILE, "spd.bin", { { NULL, CBFS_TYPE_SPD } }, HASH_IDX_SPD0, - MBOOT_PCR_INDEX_1 }, + { VERIFY_FILE, POSTCAR, { { NULL, CBFS_TYPE_STAGE } }, + HASH_IDX_POSTCAR_STAGE, MBOOT_PCR_INDEX_0 }, { VERIFY_TERMINATOR, NULL, { { NULL, 0 } }, 0, 0 } }; From 85e680a94a16b724f7482ab4f601047c91f31870 Mon Sep 17 00:00:00 2001 From: Wim Vervoorn Date: Wed, 13 Nov 2019 16:58:57 +0100 Subject: [PATCH 0177/1242] mb/facebook/fbg1701: Removed unused include file Removed unused include file. BUG=N/A TEST=build Change-Id: I040b695a893b51de06f9658abdca8867727f053d Signed-off-by: Wim Vervoorn Reviewed-on: https://review.coreboot.org/c/coreboot/+/36818 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi Reviewed-by: Frans Hendriks --- src/mainboard/facebook/fbg1701/board_verified_boot.h | 1 - 1 file changed, 1 deletion(-) diff --git a/src/mainboard/facebook/fbg1701/board_verified_boot.h b/src/mainboard/facebook/fbg1701/board_verified_boot.h index 30fcd8b1c2..0f79579050 100644 --- a/src/mainboard/facebook/fbg1701/board_verified_boot.h +++ b/src/mainboard/facebook/fbg1701/board_verified_boot.h @@ -16,7 +16,6 @@ #ifndef BOARD_VERIFIED_BOOT_H #define BOARD_VERIFIED_BOOT_H -#include #include #include "onboard.h" From 7ea8b8866aed3551941d7f919bb8d6bb83ca5b30 Mon Sep 17 00:00:00 2001 From: Wim Vervoorn Date: Wed, 13 Nov 2019 17:13:09 +0100 Subject: [PATCH 0178/1242] vendorcode/eltan/security: Add all verify_lists to include file Some of the verify lists were added to the include file while others are on vboot_check.c. Also added the ramstage_verify_list. BUG=N/A TEST=tested on fbg1701 Change-Id: If4f1d8b2278277d0af78e357ecce0d5bef441179 Signed-off-by: Wim Vervoorn Reviewed-on: https://review.coreboot.org/c/coreboot/+/36820 Reviewed-by: Frans Hendriks Reviewed-by: Aaron Durbin Tested-by: build bot (Jenkins) --- src/vendorcode/eltan/security/verified_boot/vboot_check.c | 2 -- src/vendorcode/eltan/security/verified_boot/vboot_check.h | 2 ++ 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/src/vendorcode/eltan/security/verified_boot/vboot_check.c b/src/vendorcode/eltan/security/verified_boot/vboot_check.c index f139449651..c053263d61 100644 --- a/src/vendorcode/eltan/security/verified_boot/vboot_check.c +++ b/src/vendorcode/eltan/security/verified_boot/vboot_check.c @@ -252,8 +252,6 @@ void verified_boot_bootblock_check(void) * ROMSTAGE */ -extern verify_item_t romstage_verify_list[]; - void verified_boot_early_check(void) { printk(BIOS_SPEW, "%s: processing early items\n", __func__); diff --git a/src/vendorcode/eltan/security/verified_boot/vboot_check.h b/src/vendorcode/eltan/security/verified_boot/vboot_check.h index 36c8ffa8d3..bd284925ae 100644 --- a/src/vendorcode/eltan/security/verified_boot/vboot_check.h +++ b/src/vendorcode/eltan/security/verified_boot/vboot_check.h @@ -72,7 +72,9 @@ typedef struct { void process_verify_list(const verify_item_t list[]); extern const verify_item_t bootblock_verify_list[]; +extern const verify_item_t romstage_verify_list[]; extern const verify_item_t postcar_verify_list[]; +extern const verify_item_t ramstage_verify_list[]; extern const verify_item_t payload_verify_list[]; extern const verify_item_t oprom_verify_list[]; From e05dc17d4b25589d4677913692298eaf305f4247 Mon Sep 17 00:00:00 2001 From: Wim Vervoorn Date: Thu, 14 Nov 2019 09:50:59 +0100 Subject: [PATCH 0179/1242] vendorcode/eltan/security: Remove cbfs prepare and locate The prepare functionality will be removed from cbfs support and the eltan verified boot is the only software using it. This is not really required as we can use the prog_locate_hook() for this functionality. BUG=N/A TEST=tested on fbg1701 Change-Id: I189cbad4b24bbbb0840ce6100c89a42a327c5456 Signed-off-by: Wim Vervoorn Reviewed-on: https://review.coreboot.org/c/coreboot/+/36821 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin Reviewed-by: Frans Hendriks --- .../eltan/security/verified_boot/vboot_check.c | 9 ++------- 1 file changed, 2 insertions(+), 7 deletions(-) diff --git a/src/vendorcode/eltan/security/verified_boot/vboot_check.c b/src/vendorcode/eltan/security/verified_boot/vboot_check.c index c053263d61..36090ecd43 100644 --- a/src/vendorcode/eltan/security/verified_boot/vboot_check.c +++ b/src/vendorcode/eltan/security/verified_boot/vboot_check.c @@ -328,7 +328,7 @@ int verified_boot_should_run_oprom(struct rom_header *rom_header) return process_oprom_list(oprom_verify_list, rom_header); } -static void vendor_secure_prepare(void) +int prog_locate_hook(struct prog *prog) { if (ENV_BOOTBLOCK) { printk(BIOS_SPEW, "%s: bootblock\n", __func__); @@ -353,10 +353,5 @@ static void vendor_secure_prepare(void) printk(BIOS_SPEW, "%s: ramstage\n", __func__); process_verify_list(payload_verify_list); } + return 0; } - -const struct cbfs_locator cbfs_default_locator = { - .name = "Vendorcode Header Locator", - .prepare = vendor_secure_prepare, - .locate = cbfs_default_props -}; From f4a304722aed79577e9b4d23b0f536db35f2d5dc Mon Sep 17 00:00:00 2001 From: Wim Vervoorn Date: Thu, 14 Nov 2019 10:03:25 +0100 Subject: [PATCH 0180/1242] vendorcode/eltan/security: Cleanup prog_locate_hook Cleanup of the prog_locate_hook routine so the actual coreboot flow is more clearly reflected in the code. Remove logging that is not really needed. BUG=N/A TEST=tested on fbg1701 Change-Id: Iab6c75beac35d043d296336021c0bce1f828cf34 Signed-off-by: Wim Vervoorn Reviewed-on: https://review.coreboot.org/c/coreboot/+/36846 Reviewed-by: Aaron Durbin Tested-by: build bot (Jenkins) --- .../security/verified_boot/vboot_check.c | 27 +++++++++---------- 1 file changed, 12 insertions(+), 15 deletions(-) diff --git a/src/vendorcode/eltan/security/verified_boot/vboot_check.c b/src/vendorcode/eltan/security/verified_boot/vboot_check.c index 36090ecd43..0633042539 100644 --- a/src/vendorcode/eltan/security/verified_boot/vboot_check.c +++ b/src/vendorcode/eltan/security/verified_boot/vboot_check.c @@ -330,28 +330,25 @@ int verified_boot_should_run_oprom(struct rom_header *rom_header) int prog_locate_hook(struct prog *prog) { - if (ENV_BOOTBLOCK) { - printk(BIOS_SPEW, "%s: bootblock\n", __func__); + if (ENV_BOOTBLOCK) verified_boot_bootblock_check(); - } if (ENV_ROMSTAGE) { - static int prepare_romstage = 0; - printk(BIOS_SPEW, "%s: romstage\n", __func__); - if (!prepare_romstage) { + if (prog->type == PROG_REFCODE) verified_boot_early_check(); - prepare_romstage = 1; - } + + if (CONFIG(POSTCAR_STAGE) && prog->type == PROG_POSTCAR) + process_verify_list(postcar_verify_list); + + if (!CONFIG(POSTCAR_STAGE) && prog->type == PROG_RAMSTAGE) + process_verify_list(ramstage_verify_list); } - if (ENV_POSTCAR) { - printk(BIOS_SPEW, "%s: postcar\n", __func__); - process_verify_list(postcar_verify_list); - } + if (ENV_POSTCAR && prog->type == PROG_RAMSTAGE) + process_verify_list(ramstage_verify_list); - if (ENV_RAMSTAGE) { - printk(BIOS_SPEW, "%s: ramstage\n", __func__); + if (ENV_RAMSTAGE && prog->type == PROG_PAYLOAD) process_verify_list(payload_verify_list); - } + return 0; } From 0bb4f0c766649758abd6f8faaaadf868fcb01917 Mon Sep 17 00:00:00 2001 From: Wim Vervoorn Date: Wed, 13 Nov 2019 16:52:22 +0100 Subject: [PATCH 0181/1242] mb/facebook/fbg1701: Only verify the publickey when needed The public key should only be validated if the manifest is signed. BUG=N/A TEST=testedd on fbg1701 Change-Id: I703ed442e0b1926859f593ce9ca84133013224ea Signed-off-by: Wim Vervoorn Reviewed-on: https://review.coreboot.org/c/coreboot/+/36816 Tested-by: build bot (Jenkins) Reviewed-by: Frans Hendriks --- src/mainboard/facebook/fbg1701/board_verified_boot.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/src/mainboard/facebook/fbg1701/board_verified_boot.c b/src/mainboard/facebook/fbg1701/board_verified_boot.c index 7421a14e67..685515bbca 100644 --- a/src/mainboard/facebook/fbg1701/board_verified_boot.c +++ b/src/mainboard/facebook/fbg1701/board_verified_boot.c @@ -25,10 +25,12 @@ const verify_item_t bootblock_verify_list[] = { { { (void *)0xffffffff - CONFIG_C_ENV_BOOTBLOCK_SIZE + 1, CONFIG_C_ENV_BOOTBLOCK_SIZE, } }, HASH_IDX_BOOTBLOCK, MBOOT_PCR_INDEX_0 }, +#if CONFIG(VENDORCODE_ELTAN_VBOOT_SIGNED_MANIFEST) { VERIFY_BLOCK, "PublicKey", { { (void *)CONFIG_VENDORCODE_ELTAN_VBOOT_KEY_LOCATION, CONFIG_VENDORCODE_ELTAN_VBOOT_KEY_SIZE, } }, HASH_IDX_PUBLICKEY, MBOOT_PCR_INDEX_0 }, +#endif { VERIFY_TERMINATOR, NULL, { { NULL, 0 } }, 0, 0 } }; From 628beff58c622fd6741601273bf79507513b2f0a Mon Sep 17 00:00:00 2001 From: Wim Vervoorn Date: Wed, 13 Nov 2019 17:01:33 +0100 Subject: [PATCH 0182/1242] mb/facebook/fbg1701: Stagenames now use CONFIG_CBFS_PREFIX Change from hardcoded "fallback/*" to using CONFIG_CBFS_PREFIX. BUG=N/A TEST=tested on fbg1701 Change-Id: Ie728d01ebb93edd88516e91528ecaaa3f139b7a9 Signed-off-by: Wim Vervoorn Reviewed-on: https://review.coreboot.org/c/coreboot/+/36819 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi Reviewed-by: Frans Hendriks --- src/mainboard/facebook/fbg1701/onboard.h | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/src/mainboard/facebook/fbg1701/onboard.h b/src/mainboard/facebook/fbg1701/onboard.h index cb784daf69..c22a63a04a 100644 --- a/src/mainboard/facebook/fbg1701/onboard.h +++ b/src/mainboard/facebook/fbg1701/onboard.h @@ -27,10 +27,10 @@ /* Define the items to be measured or verified */ #define FSP (const char *)"fsp.bin" #define CMOS_LAYOUT (const char *)"cmos_layout.bin" -#define RAMSTAGE (const char *)"fallback/ramstage" -#define ROMSTAGE (const char *)"fallback/romstage" -#define PAYLOAD (const char *)"fallback/payload" -#define POSTCAR (const char *)"fallback/postcar" +#define RAMSTAGE (const char *)CONFIG_CBFS_PREFIX"/ramstage" +#define ROMSTAGE (const char *)CONFIG_CBFS_PREFIX"/romstage" +#define PAYLOAD (const char *)CONFIG_CBFS_PREFIX"/payload" +#define POSTCAR (const char *)CONFIG_CBFS_PREFIX"/postcar" #define OP_ROM_VBT (const char *)"vbt.bin" #define MICROCODE (const char *)"cpu_microcode_blob.bin" From 959eb162bbaf8e94d8eae5450bb2740d82f78b5c Mon Sep 17 00:00:00 2001 From: Wim Vervoorn Date: Wed, 13 Nov 2019 16:57:22 +0100 Subject: [PATCH 0183/1242] mb/facebook/fbg1701: Changed the order of the verify_lists Changed the order of the verify lists and updated the comments to reflect the order of execution. This makes the list easier to understand and maintain. BUG=N/A TEST=tested on fbg1701 Change-Id: Ia656fbf07e5d42bafd328eaba69b660e5a1e4f1a Signed-off-by: Wim Vervoorn Reviewed-on: https://review.coreboot.org/c/coreboot/+/36817 Reviewed-by: Patrick Georgi Reviewed-by: Frans Hendriks Tested-by: build bot (Jenkins) --- .../facebook/fbg1701/board_verified_boot.c | 41 ++++++++++--------- 1 file changed, 22 insertions(+), 19 deletions(-) diff --git a/src/mainboard/facebook/fbg1701/board_verified_boot.c b/src/mainboard/facebook/fbg1701/board_verified_boot.c index 685515bbca..a4d18e74c0 100644 --- a/src/mainboard/facebook/fbg1701/board_verified_boot.c +++ b/src/mainboard/facebook/fbg1701/board_verified_boot.c @@ -34,17 +34,6 @@ const verify_item_t bootblock_verify_list[] = { { VERIFY_TERMINATOR, NULL, { { NULL, 0 } }, 0, 0 } }; -/* The FSP is already checked in romstage */ -static const verify_item_t ram_stage_additional_list[] = { - { VERIFY_FILE, OP_ROM_VBT, { { NULL, CBFS_TYPE_RAW } }, - HASH_IDX_OPROM, MBOOT_PCR_INDEX_2 }, - { VERIFY_FILE, "logo.bmp", { { NULL, CBFS_TYPE_RAW } }, - HASH_IDX_LOGO, MBOOT_PCR_INDEX_2 }, - { VERIFY_FILE, "fallback/dsdt.aml", { { NULL, CBFS_TYPE_RAW } }, - HASH_IDX_DSDT, MBOOT_PCR_INDEX_2 }, - { VERIFY_TERMINATOR, NULL, { { NULL, 0 } }, 0, 0 } -}; - /* * The items used by the romstage. Bootblock and PublicKey are added here to make sure they * are measured @@ -71,13 +60,6 @@ const verify_item_t romstage_verify_list[] = { { VERIFY_TERMINATOR, NULL, { { NULL, 0 } }, 0, 0 } }; -/* The items used by the ramstage */ -const verify_item_t ramstage_verify_list[] = { - { VERIFY_FILE, RAMSTAGE, { { ram_stage_additional_list, - CBFS_TYPE_STAGE } }, HASH_IDX_RAM_STAGE, MBOOT_PCR_INDEX_0 }, - { VERIFY_TERMINATOR, NULL, { { NULL, 0 } }, 0, 0 } -}; - /* The items used by the postcar stage */ const verify_item_t postcar_verify_list[] = { { VERIFY_FILE, POSTCAR, { { NULL, CBFS_TYPE_STAGE } }, @@ -85,7 +67,27 @@ const verify_item_t postcar_verify_list[] = { { VERIFY_TERMINATOR, NULL, { { NULL, 0 } }, 0, 0 } }; -/* RAMSTAGE */ +/* + * The items used by the ramstage. FSP and microcode are already checked in the + * romstage verify list + */ +static const verify_item_t ram_stage_additional_list[] = { + { VERIFY_FILE, OP_ROM_VBT, { { NULL, CBFS_TYPE_RAW } }, + HASH_IDX_OPROM, MBOOT_PCR_INDEX_2 }, + { VERIFY_FILE, "logo.bmp", { { NULL, CBFS_TYPE_RAW } }, + HASH_IDX_LOGO, MBOOT_PCR_INDEX_2 }, + { VERIFY_FILE, "fallback/dsdt.aml", { { NULL, CBFS_TYPE_RAW } }, + HASH_IDX_DSDT, MBOOT_PCR_INDEX_2 }, + { VERIFY_TERMINATOR, NULL, { { NULL, 0 } }, 0, 0 } +}; + +const verify_item_t ramstage_verify_list[] = { + { VERIFY_FILE, RAMSTAGE, { { ram_stage_additional_list, + CBFS_TYPE_STAGE } }, HASH_IDX_RAM_STAGE, MBOOT_PCR_INDEX_0 }, + { VERIFY_TERMINATOR, NULL, { { NULL, 0 } }, 0, 0 } +}; + +/* items used by the payload */ const verify_item_t payload_verify_list[] = { { VERIFY_FILE, PAYLOAD, { { NULL, CBFS_TYPE_SELF | VERIFIED_BOOT_COPY_BLOCK } }, HASH_IDX_PAYLOAD, @@ -93,6 +95,7 @@ const verify_item_t payload_verify_list[] = { { VERIFY_TERMINATOR, NULL, { { NULL, 0 } }, 0, 0 } }; +/* list of allowed options roms */ const verify_item_t oprom_verify_list[] = { { VERIFY_TERMINATOR, NULL, { { NULL, 0 } }, 0, 0 } }; From fa85ba279fd1eceb5e48a553930a8b5d3d3b0cc0 Mon Sep 17 00:00:00 2001 From: Wim Vervoorn Date: Thu, 14 Nov 2019 15:04:48 +0100 Subject: [PATCH 0184/1242] mb/facebook/fbg1701: Remove logo from verify list when disabled Remove the logo.bmp file from the verify list when FSP1_1_DISPLAY_LOGO is not set. BUG=N/A TEST=build Change-Id: I87eac0b3cbe9450d5623b5331d8de096f140b595 Signed-off-by: Wim Vervoorn Reviewed-on: https://review.coreboot.org/c/coreboot/+/36853 Reviewed-by: Frans Hendriks Tested-by: build bot (Jenkins) --- src/mainboard/facebook/fbg1701/board_verified_boot.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/src/mainboard/facebook/fbg1701/board_verified_boot.c b/src/mainboard/facebook/fbg1701/board_verified_boot.c index a4d18e74c0..d2ba78de2b 100644 --- a/src/mainboard/facebook/fbg1701/board_verified_boot.c +++ b/src/mainboard/facebook/fbg1701/board_verified_boot.c @@ -74,8 +74,10 @@ const verify_item_t postcar_verify_list[] = { static const verify_item_t ram_stage_additional_list[] = { { VERIFY_FILE, OP_ROM_VBT, { { NULL, CBFS_TYPE_RAW } }, HASH_IDX_OPROM, MBOOT_PCR_INDEX_2 }, +#if CONFIG(FSP1_1_DISPLAY_LOGO) { VERIFY_FILE, "logo.bmp", { { NULL, CBFS_TYPE_RAW } }, HASH_IDX_LOGO, MBOOT_PCR_INDEX_2 }, +#endif { VERIFY_FILE, "fallback/dsdt.aml", { { NULL, CBFS_TYPE_RAW } }, HASH_IDX_DSDT, MBOOT_PCR_INDEX_2 }, { VERIFY_TERMINATOR, NULL, { { NULL, 0 } }, 0, 0 } From 700c024057321792991f984d603aaecec2c813b0 Mon Sep 17 00:00:00 2001 From: Wim Vervoorn Date: Thu, 14 Nov 2019 12:58:36 +0100 Subject: [PATCH 0185/1242] Documentation/mb/portwell/pq7-m107.md: Update microcode blob The microcode is available in 3rdparty microcode now. This ucode can be used. BUG=N/A TEST=build Change-Id: I1d83a58e9051fa9402666f05e4f2c43e76026dfb Signed-off-by: Wim Vervoorn Reviewed-on: https://review.coreboot.org/c/coreboot/+/36854 Reviewed-by: Arthur Heymans Reviewed-by: Frans Hendriks Tested-by: build bot (Jenkins) --- Documentation/mainboard/portwell/pq7-m107.md | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/Documentation/mainboard/portwell/pq7-m107.md b/Documentation/mainboard/portwell/pq7-m107.md index 71bd26a100..f7e5142bb4 100644 --- a/Documentation/mainboard/portwell/pq7-m107.md +++ b/Documentation/mainboard/portwell/pq7-m107.md @@ -14,8 +14,7 @@ menu. This board currently requires: fsp blob 3rdparty/fsp/BraswellFspBinPkg/FspBin/BSWFSP.fd -Microcode Intel Braswell cpuid 1046C4 version 410 - (Used pre-built binary retrieved from Intel site) +Microcode 3rdparty/intel-microcode/intel-ucode/06-4c-04 ## Flashing coreboot From 0a8e8e84f1cba64784fd9f2e7ae95a7121618faa Mon Sep 17 00:00:00 2001 From: Frans Hendriks Date: Thu, 14 Nov 2019 12:57:26 +0100 Subject: [PATCH 0186/1242] Documentation/mb/facebook/fbg1701.md: Update microcode blob The microcode is available in 3rdparty microcode now. This ucode can be used. BUG=N/A TEST=build Change-Id: I52a04c7dc97608f868ee0b415bbbb328937f18f7 Signed-off-by: Wim Vervoorn Reviewed-on: https://review.coreboot.org/c/coreboot/+/36855 Tested-by: build bot (Jenkins) Reviewed-by: Frans Hendriks --- Documentation/mainboard/facebook/fbg1701.md | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) mode change 100755 => 100644 Documentation/mainboard/facebook/fbg1701.md diff --git a/Documentation/mainboard/facebook/fbg1701.md b/Documentation/mainboard/facebook/fbg1701.md old mode 100755 new mode 100644 index e59627721a..06bf42fc98 --- a/Documentation/mainboard/facebook/fbg1701.md +++ b/Documentation/mainboard/facebook/fbg1701.md @@ -14,8 +14,7 @@ Mainboard menu. This board currently requires: fsp blob 3rdparty/fsp/BraswellFspBinPkg/FspBin/BSWFSP.fd -Microcode Intel Braswell cpuid 1046C4 version 410 - (Used pre-built binary retrieved from Intel site) +Microcode 3rdparty/intel-microcode/intel-ucode/06-4c-04 ## Flashing coreboot From 92fe375737943a4dc4d54665b1385090ee5738bb Mon Sep 17 00:00:00 2001 From: Sheng-Liang Pan Date: Tue, 12 Nov 2019 17:16:51 +0800 Subject: [PATCH 0187/1242] mb/google/octopus/variants/bobba: support LTE power sequence GPIOs related to power sequnce are GPIO_67 - EN_PP3300 GPIO_117 - FULL_CARD_POWER_ON_OFF GPIO_161 - PLT_RST_LTE_L 1. Power on: GPIO_67 -> 0ms -> GPIO_117 -> 30ms -> GPIO_161 2. Power off: GPIO_161 -> 30ms -> GPIO_117 -> 100ms -> GPIO_67 3. Power reset: - keep GPIO_67 and GPIO_117 high and - pull down GPIO_161 for 30ms then release it. BUG=b:144327240 BRANCH=octopus TEST=build image and verify on the DUT with LTE DB. Change-Id: I68b71425391eda1e92806fecdb9c8dcd54f0b95a Signed-off-by: Pan Sheng-Liang Reviewed-on: https://review.coreboot.org/c/coreboot/+/36771 Reviewed-by: Justin TerAvest Reviewed-by: Karthik Ramasubramanian Reviewed-by: Henry Sun Tested-by: build bot (Jenkins) --- .../google/octopus/variants/bobba/gpio.c | 61 ++++++++++++++++++- .../google/octopus/variants/bobba/variant.c | 58 ++++++++++++++++++ 2 files changed, 117 insertions(+), 2 deletions(-) diff --git a/src/mainboard/google/octopus/variants/bobba/gpio.c b/src/mainboard/google/octopus/variants/bobba/gpio.c index 6bfe54aec7..7c522c78ef 100644 --- a/src/mainboard/google/octopus/variants/bobba/gpio.c +++ b/src/mainboard/google/octopus/variants/bobba/gpio.c @@ -19,6 +19,13 @@ #include #include +enum { + SKU_37_DROID = 37, /* LTE */ + SKU_38_DROID = 38, /* LTE + Touch */ + SKU_39_DROID = 39, /* LTE + KB backlight*/ + SKU_40_DROID = 40, /* LTE + Touch + KB backlight*/ +}; + static const struct pad_config default_override_table[] = { PAD_NC(GPIO_104, UP_20K), @@ -29,9 +36,59 @@ static const struct pad_config default_override_table[] = { PAD_NC(GPIO_213, DN_20K), }; +static const struct pad_config lte_override_table[] = { + /* Default override table. */ + PAD_NC(GPIO_104, UP_20K), + + /* EN_PP3300_TOUCHSCREEN */ + PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_146, 0, DEEP, NONE, Tx0RxDCRx0, + DISPUPD), + + PAD_NC(GPIO_213, DN_20K), + + /* Be specific to LTE SKU */ + /* UART2-CTS_B -- EN_PP3300_DX_LTE_SOC */ + PAD_CFG_GPO(GPIO_67, 1, PWROK), + + /* PCIE_WAKE1_B -- FULL_CARD_POWER_OFF */ + PAD_CFG_GPO(GPIO_117, 1, PWROK), + + /* AVS_I2S1_MCLK -- PLT_RST_LTE_L */ + PAD_CFG_GPO(GPIO_161, 1, DEEP), +}; + const struct pad_config *variant_override_gpio_table(size_t *num) { - *num = ARRAY_SIZE(default_override_table); + uint32_t sku_id; + sku_id = get_board_sku(); - return default_override_table; + switch (sku_id) { + case SKU_37_DROID: + case SKU_38_DROID: + case SKU_39_DROID: + case SKU_40_DROID: + *num = ARRAY_SIZE(lte_override_table); + return lte_override_table; + default: + *num = ARRAY_SIZE(default_override_table); + return default_override_table; + } +} + +static const struct pad_config lte_early_override_table[] = { + /* UART2-CTS_B -- EN_PP3300_DX_LTE_SOC */ + PAD_CFG_GPO(GPIO_67, 1, PWROK), + + /* PCIE_WAKE1_B -- FULL_CARD_POWER_OFF */ + PAD_CFG_GPO(GPIO_117, 1, PWROK), + + /* AVS_I2S1_MCLK -- PLT_RST_LTE_L */ + PAD_CFG_GPO(GPIO_161, 0, DEEP), +}; + +const struct pad_config *variant_early_override_gpio_table(size_t *num) +{ + *num = ARRAY_SIZE(lte_early_override_table); + + return lte_early_override_table; } diff --git a/src/mainboard/google/octopus/variants/bobba/variant.c b/src/mainboard/google/octopus/variants/bobba/variant.c index 05a331a1eb..1f6e80db78 100644 --- a/src/mainboard/google/octopus/variants/bobba/variant.c +++ b/src/mainboard/google/octopus/variants/bobba/variant.c @@ -13,8 +13,47 @@ * GNU General Public License for more details. */ +#include +#include #include #include +#include +#include + +enum { + SKU_37_DROID = 37, /* LTE */ + SKU_38_DROID = 38, /* LTE + Touch */ + SKU_39_DROID = 39, /* LTE + KB backlight*/ + SKU_40_DROID = 40, /* LTE + Touch + KB backlight*/ +}; + +struct gpio_with_delay { + gpio_t gpio; + unsigned int delay_msecs; +}; + +static void power_off_lte_module(u8 slp_typ) +{ + const struct gpio_with_delay lte_power_off_gpios[] = { + { + GPIO_161, /* AVS_I2S1_MCLK -- PLT_RST_LTE_L */ + 30, + }, + { + GPIO_117, /* PCIE_WAKE1_B -- FULL_CARD_POWER_OFF */ + 100 + }, + { + GPIO_67, /* UART2-CTS_B -- EN_PP3300_DX_LTE_SOC */ + 0 + } + }; + + for (int i = 0; i < ARRAY_SIZE(lte_power_off_gpios); i++) { + gpio_output(lte_power_off_gpios[i].gpio, 0); + mdelay(lte_power_off_gpios[i].delay_msecs); + } +} const char *get_wifi_sar_cbfs_filename(void) { @@ -27,3 +66,22 @@ const char *get_wifi_sar_cbfs_filename(void) return filename; } + +void variant_smi_sleep(u8 slp_typ) +{ + /* Currently use cases here all target to S5 therefore we do early return + * here for saving one transaction to the EC for getting SKU ID. */ + if (slp_typ != ACPI_S5) + return; + + switch (get_board_sku()) { + case SKU_37_DROID: + case SKU_38_DROID: + case SKU_39_DROID: + case SKU_40_DROID: + power_off_lte_module(slp_typ); + return; + default: + return; + } +} From ef36cdd06d8680bc61d6a712b36d28fd2f3c20b9 Mon Sep 17 00:00:00 2001 From: Sheng-Liang Pan Date: Thu, 14 Nov 2019 18:39:36 +0800 Subject: [PATCH 0188/1242] mb/google/octopus/variants/bobba: Add SX9310 sensor to devicetree Add semtech SAR sensor. BUG=b:143449140 BRANCH=octopus TEST=Boot kernel with sx931x driver, i2cdetect show UU on slave address. Change-Id: Icfb8acf1bac73973748aa7443c95147c60bad770 Signed-off-by: Pan Sheng-Liang Reviewed-on: https://review.coreboot.org/c/coreboot/+/36850 Reviewed-by: Justin TerAvest Reviewed-by: Karthik Ramasubramanian Tested-by: build bot (Jenkins) --- src/mainboard/google/octopus/Kconfig | 1 + .../octopus/variants/bobba/overridetree.cb | 37 +++++++++++++++++++ 2 files changed, 38 insertions(+) diff --git a/src/mainboard/google/octopus/Kconfig b/src/mainboard/google/octopus/Kconfig index 7b07c2ca24..f67f64272c 100644 --- a/src/mainboard/google/octopus/Kconfig +++ b/src/mainboard/google/octopus/Kconfig @@ -8,6 +8,7 @@ config BOARD_GOOGLE_BASEBOARD_OCTOPUS select DRIVERS_I2C_DA7219 select DRIVERS_I2C_GENERIC select DRIVERS_I2C_HID + select DRIVERS_I2C_SX9310 select DRIVERS_SPI_ACPI select DRIVERS_USB_ACPI select EC_GOOGLE_CHROMEEC diff --git a/src/mainboard/google/octopus/variants/bobba/overridetree.cb b/src/mainboard/google/octopus/variants/bobba/overridetree.cb index 0230a29a89..6cd4c61796 100644 --- a/src/mainboard/google/octopus/variants/bobba/overridetree.cb +++ b/src/mainboard/google/octopus/variants/bobba/overridetree.cb @@ -67,6 +67,12 @@ chip soc/intel/apollolake .rise_time_ns = 88, .fall_time_ns = 16, }, + .i2c[1] = { + .speed = I2C_SPEED_FAST, + .rise_time_ns = 66, + .fall_time_ns = 90, + .data_hold_time_ns = 350, + }, .i2c[5] = { .speed = I2C_SPEED_FAST, .rise_time_ns = 104, @@ -109,6 +115,37 @@ chip soc/intel/apollolake device generic 0 on end end end # - I2C 0 + device pci 16.1 on + chip drivers/i2c/sx9310 + register "desc" = ""SAR Proximity Sensor"" + register "irq" = "ACPI_IRQ_LEVEL_LOW(GPIO_214_IRQ)" + register "uid" = "1" + register "reg_prox_ctrl0" = "0x10" + register "reg_prox_ctrl1" = "0x00" + register "reg_prox_ctrl2" = "0x84" + register "reg_prox_ctrl3" = "0x0e" + register "reg_prox_ctrl4" = "0x07" + register "reg_prox_ctrl5" = "0xc6" + register "reg_prox_ctrl6" = "0x20" + register "reg_prox_ctrl7" = "0x0d" + register "reg_prox_ctrl8" = "0x8d" + register "reg_prox_ctrl9" = "0x43" + register "reg_prox_ctrl10" = "0x11" + register "reg_prox_ctrl11" = "0x00" + register "reg_prox_ctrl12" = "0x00" + register "reg_prox_ctrl13" = "0x00" + register "reg_prox_ctrl14" = "0x00" + register "reg_prox_ctrl15" = "0x00" + register "reg_prox_ctrl16" = "0x00" + register "reg_prox_ctrl17" = "0x00" + register "reg_prox_ctrl18" = "0x00" + register "reg_prox_ctrl19" = "0x00" + register "reg_sar_ctrl0" = "0x50" + register "reg_sar_ctrl1" = "0x8a" + register "reg_sar_ctrl2" = "0x3c" + device i2c 28 on end + end + end # - I2C 1 device pci 17.1 on chip drivers/i2c/da7219 register "irq" = "ACPI_IRQ_LEVEL_LOW(GPIO_137_IRQ)" From 5aa0a53e5ff64e83f893a26153fb35cde4a05cd4 Mon Sep 17 00:00:00 2001 From: Hung-Te Lin Date: Thu, 14 Nov 2019 17:47:47 +0800 Subject: [PATCH 0189/1242] mb/google/kukui: Add new board 'kakadu' Add a new Kukui follower 'kakadu'. BUG=None TEST=make # select kakadu Change-Id: I9f25ce90285828c43435e45d9361ee7128d407fa Signed-off-by: Hung-Te Lin Reviewed-on: https://review.coreboot.org/c/coreboot/+/36848 Reviewed-by: Yu-Ping Wu Reviewed-by: Julius Werner Tested-by: build bot (Jenkins) --- src/mainboard/google/kukui/Kconfig | 1 + src/mainboard/google/kukui/Kconfig.name | 4 ++++ 2 files changed, 5 insertions(+) diff --git a/src/mainboard/google/kukui/Kconfig b/src/mainboard/google/kukui/Kconfig index b909f1dd84..c5c7a86d7e 100644 --- a/src/mainboard/google/kukui/Kconfig +++ b/src/mainboard/google/kukui/Kconfig @@ -53,6 +53,7 @@ config MAINBOARD_PART_NUMBER default "Kukui" if BOARD_GOOGLE_KUKUI default "Krane" if BOARD_GOOGLE_KRANE default "Kodama" if BOARD_GOOGLE_KODAMA + default "Kadadu" if BOARD_GOOGLE_KAKADU default "Flapjack" if BOARD_GOOGLE_FLAPJACK default "Jacuzzi" if BOARD_GOOGLE_JACUZZI default "Juniper" if BOARD_GOOGLE_JUNIPER diff --git a/src/mainboard/google/kukui/Kconfig.name b/src/mainboard/google/kukui/Kconfig.name index 223e76a965..4b12034a5d 100644 --- a/src/mainboard/google/kukui/Kconfig.name +++ b/src/mainboard/google/kukui/Kconfig.name @@ -12,6 +12,10 @@ config BOARD_GOOGLE_KODAMA bool "-> Kodama" select BOARD_GOOGLE_KUKUI_COMMON +config BOARD_GOOGLE_KAKADU + bool "-> Kakadu" + select BOARD_GOOGLE_KUKUI_COMMON + config BOARD_GOOGLE_FLAPJACK bool "-> Flapjack" select BOARD_GOOGLE_KUKUI_COMMON From 5885ffef326ff41b2bad80e42e1795a2982754b3 Mon Sep 17 00:00:00 2001 From: Subrata Banik Date: Thu, 14 Nov 2019 11:08:51 +0530 Subject: [PATCH 0190/1242] soc/intel/common: Make alignment proper for comments Change-Id: If932582d03bb2f6d3d14c9bce45cf2030f3b3c4e Signed-off-by: Subrata Banik Reviewed-on: https://review.coreboot.org/c/coreboot/+/36838 Tested-by: build bot (Jenkins) Reviewed-by: V Sowmya Reviewed-by: HAOUAS Elyes --- src/soc/intel/common/block/cpu/car/cache_as_ram.S | 2 +- .../intel/common/block/include/intelblocks/xhci.h | 8 ++++---- src/soc/intel/common/hda_verb.c | 14 +++++++------- 3 files changed, 12 insertions(+), 12 deletions(-) diff --git a/src/soc/intel/common/block/cpu/car/cache_as_ram.S b/src/soc/intel/common/block/cpu/car/cache_as_ram.S index 471c18e407..0992d85acd 100644 --- a/src/soc/intel/common/block/cpu/car/cache_as_ram.S +++ b/src/soc/intel/common/block/cpu/car/cache_as_ram.S @@ -177,7 +177,7 @@ car_init_done: andl $0xfffffff0, %esp sub $8, %esp - /*push TSC value to stack*/ + /* push TSC value to stack */ movd %mm2, %eax pushl %eax /* tsc[63:32] */ movd %mm1, %eax diff --git a/src/soc/intel/common/block/include/intelblocks/xhci.h b/src/soc/intel/common/block/include/intelblocks/xhci.h index dd95bfb024..0b3aa050e1 100644 --- a/src/soc/intel/common/block/include/intelblocks/xhci.h +++ b/src/soc/intel/common/block/include/intelblocks/xhci.h @@ -18,7 +18,7 @@ #include -/** +/* * struct xhci_usb_info - Data containing number of USB ports & offset. * @usb2_port_status_reg: Offset to USB2 port status register. * @num_usb2_ports: Number of USB2 ports. @@ -32,7 +32,7 @@ struct xhci_usb_info { uint32_t num_usb3_ports; }; -/** +/* * pch_xhci_update_wake_event() - Identify and log XHCI wake events. * @info: Information about number of USB ports and their status reg offset. * @@ -46,7 +46,7 @@ bool pch_xhci_update_wake_event(const struct xhci_usb_info *info); void soc_xhci_init(struct device *dev); -/** +/* * soc_get_xhci_usb_info() - Get the information about USB2 & USB3 ports. * * This function is used to get USB ports and status register offset information @@ -56,7 +56,7 @@ void soc_xhci_init(struct device *dev); */ const struct xhci_usb_info *soc_get_xhci_usb_info(void); -/** +/* * usb_xhci_disable_unused() - Disable unused USB devices * @ext_usb_xhci_en_cb: Callback function to be invoked, supplied by mainboard, * to identify the status of externally visible USB ports. diff --git a/src/soc/intel/common/hda_verb.c b/src/soc/intel/common/hda_verb.c index 3edad9be1e..03a23dfe0a 100644 --- a/src/soc/intel/common/hda_verb.c +++ b/src/soc/intel/common/hda_verb.c @@ -20,7 +20,7 @@ #include #include "hda_verb.h" -/** +/* * Set bits in a register and wait for status */ static int set_bits(void *port, u32 mask, u32 val) @@ -52,7 +52,7 @@ static int set_bits(void *port, u32 mask, u32 val) return 0; } -/** +/* * Probe for supported codecs */ int hda_codec_detect(u8 *base) @@ -95,7 +95,7 @@ no_codec: return 0; } -/** +/* * Wait 50usec for the codec to indicate it is ready * no response would imply that the codec is non-operative */ @@ -116,7 +116,7 @@ static int hda_wait_for_ready(u8 *base) return -1; } -/** +/* * Wait 50usec for the codec to indicate that it accepted * the previous command. No response would imply that the code * is non-operative @@ -145,7 +145,7 @@ static int hda_wait_for_valid(u8 *base) return -1; } -/** +/* * Find a specific entry within a verb table * * @param verb_table_bytes: verb table size in bytes @@ -190,7 +190,7 @@ static u32 hda_find_verb(u32 verb_table_bytes, return 0; } -/** +/* * Write a supplied verb table */ int hda_codec_write(u8 *base, u32 size, const u32 *data) @@ -210,7 +210,7 @@ int hda_codec_write(u8 *base, u32 size, const u32 *data) return 0; } -/** +/* * Initialize codec, then find the verb table and write it */ int hda_codec_init(u8 *base, int addr, int verb_size, const u32 *verb_data) From 5d14c76f1ae62d0543614340f4b588adf4f506eb Mon Sep 17 00:00:00 2001 From: Subrata Banik Date: Thu, 14 Nov 2019 12:14:39 +0530 Subject: [PATCH 0191/1242] soc/intel/{icl,tgl}: Rename pch_early_init() to pch_init() This patch renames pch_early_init() function as per review feedback CB:36550 Change-Id: I9f638e738d1a910b688cc3e51795230b2e542f82 Signed-off-by: Subrata Banik Reviewed-on: https://review.coreboot.org/c/coreboot/+/36841 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi Reviewed-by: V Sowmya --- src/soc/intel/icelake/bootblock/bootblock.c | 2 +- src/soc/intel/icelake/bootblock/pch.c | 2 +- src/soc/intel/icelake/include/soc/bootblock.h | 2 +- src/soc/intel/tigerlake/bootblock/bootblock.c | 2 +- src/soc/intel/tigerlake/bootblock/pch.c | 2 +- src/soc/intel/tigerlake/include/soc/bootblock.h | 2 +- 6 files changed, 6 insertions(+), 6 deletions(-) diff --git a/src/soc/intel/icelake/bootblock/bootblock.c b/src/soc/intel/icelake/bootblock/bootblock.c index f348c1be6a..fce3cc424c 100644 --- a/src/soc/intel/icelake/bootblock/bootblock.c +++ b/src/soc/intel/icelake/bootblock/bootblock.c @@ -40,5 +40,5 @@ void bootblock_soc_early_init(void) void bootblock_soc_init(void) { report_platform_info(); - pch_early_init(); + pch_init(); } diff --git a/src/soc/intel/icelake/bootblock/pch.c b/src/soc/intel/icelake/bootblock/pch.c index b8a404b379..fd2ffd2c88 100644 --- a/src/soc/intel/icelake/bootblock/pch.c +++ b/src/soc/intel/icelake/bootblock/pch.c @@ -150,7 +150,7 @@ void pch_early_iorange_init(void) pch_enable_lpc(); } -void pch_early_init(void) +void pch_init(void) { /* * Enabling ABASE for accessing PM1_STS, PM1_EN, PM1_CNT, diff --git a/src/soc/intel/icelake/include/soc/bootblock.h b/src/soc/intel/icelake/include/soc/bootblock.h index 4ca2c37288..22e632fc75 100644 --- a/src/soc/intel/icelake/include/soc/bootblock.h +++ b/src/soc/intel/icelake/include/soc/bootblock.h @@ -21,7 +21,7 @@ void bootblock_cpu_init(void); void bootblock_pch_early_init(void); /* Bootblock post console init programming */ -void pch_early_init(void); +void pch_init(void); void pch_early_iorange_init(void); void report_platform_info(void); diff --git a/src/soc/intel/tigerlake/bootblock/bootblock.c b/src/soc/intel/tigerlake/bootblock/bootblock.c index f6fe4c4dbd..a4f965947d 100644 --- a/src/soc/intel/tigerlake/bootblock/bootblock.c +++ b/src/soc/intel/tigerlake/bootblock/bootblock.c @@ -40,5 +40,5 @@ void bootblock_soc_early_init(void) void bootblock_soc_init(void) { report_platform_info(); - pch_early_init(); + pch_init(); } diff --git a/src/soc/intel/tigerlake/bootblock/pch.c b/src/soc/intel/tigerlake/bootblock/pch.c index c7ccbf8bab..1ef4928fa6 100644 --- a/src/soc/intel/tigerlake/bootblock/pch.c +++ b/src/soc/intel/tigerlake/bootblock/pch.c @@ -156,7 +156,7 @@ void pch_early_iorange_init(void) pch_enable_lpc(); } -void pch_early_init(void) +void pch_init(void) { /* * Enabling ABASE for accessing PM1_STS, PM1_EN, PM1_CNT, diff --git a/src/soc/intel/tigerlake/include/soc/bootblock.h b/src/soc/intel/tigerlake/include/soc/bootblock.h index cb7417a107..6dbbfecd02 100644 --- a/src/soc/intel/tigerlake/include/soc/bootblock.h +++ b/src/soc/intel/tigerlake/include/soc/bootblock.h @@ -21,7 +21,7 @@ void bootblock_cpu_init(void); void bootblock_pch_early_init(void); /* Bootblock post console init programming */ -void pch_early_init(void); +void pch_init(void); void pch_early_iorange_init(void); void report_platform_info(void); From b75f504bb0b5c2d2edd8bae1432b1fbdc12c1aed Mon Sep 17 00:00:00 2001 From: Aaron Durbin Date: Fri, 8 Nov 2019 15:18:31 -0700 Subject: [PATCH 0192/1242] cbfs: remove prepare() callback from struct cbfs_locator The prepare() callback is no longer utilized in the code. Remove the callback and support for it. Change-Id: Ic438e5a80850a3df619dbbfdecb522a9dc2c1949 Signed-off-by: Aaron Durbin Reviewed-on: https://review.coreboot.org/c/coreboot/+/36690 Tested-by: build bot (Jenkins) Reviewed-by: Frans Hendriks Reviewed-by: Julius Werner Reviewed-by: Wim Vervoorn --- src/include/cbfs.h | 8 +------- src/lib/cbfs.c | 13 ------------- src/lib/prog_loaders.c | 2 -- 3 files changed, 1 insertion(+), 22 deletions(-) diff --git a/src/include/cbfs.h b/src/include/cbfs.h index d76fdd3e80..60129d3bb2 100644 --- a/src/include/cbfs.h +++ b/src/include/cbfs.h @@ -79,16 +79,10 @@ int cbfs_default_props(struct cbfs_props *props); /* Return < 0 on error otherwise props are filled out accordingly. */ int cbfs_boot_region_properties(struct cbfs_props *props); -/* Allow external logic to take action prior to locating a program - * (stage or payload). */ -void cbfs_prepare_program_locate(void); - /* Object used to identify location of current cbfs to use for cbfs_boot_* - * operations. It's used by cbfs_boot_region_properties() and - * cbfs_prepare_program_locate(). */ + * operations. It's used by cbfs_boot_region_properties(). */ struct cbfs_locator { const char *name; - void (*prepare)(void); /* Returns 0 on successful fill of cbfs properties. */ int (*locate)(struct cbfs_props *props); }; diff --git a/src/lib/cbfs.c b/src/lib/cbfs.c index 408e685256..fbe6e43496 100644 --- a/src/lib/cbfs.c +++ b/src/lib/cbfs.c @@ -359,16 +359,3 @@ int cbfs_boot_region_properties(struct cbfs_props *props) return -1; } - -void cbfs_prepare_program_locate(void) -{ - int i; - - boot_device_init(); - - for (i = 0; i < ARRAY_SIZE(locators); i++) { - if (locators[i]->prepare == NULL) - continue; - locators[i]->prepare(); - } -} diff --git a/src/lib/prog_loaders.c b/src/lib/prog_loaders.c index 43f4689940..57874967ec 100644 --- a/src/lib/prog_loaders.c +++ b/src/lib/prog_loaders.c @@ -43,8 +43,6 @@ int prog_locate(struct prog *prog) if (prog_locate_hook(prog)) return -1; - cbfs_prepare_program_locate(); - if (cbfs_boot_locate(&file, prog_name(prog), NULL)) return -1; From 7dfbaab6deabdc8c6d77eb8ffdb091d19946ae75 Mon Sep 17 00:00:00 2001 From: Frans Hendriks Date: Fri, 15 Nov 2019 12:34:22 +0100 Subject: [PATCH 0193/1242] 3rdparty/blobs: Add Facebook FBG1701 descriptor and Intel ME Upgrade to blobs version with descriptor and Intel ME binary BUG=N/A TEST=booting Facebook FBG1701 Change-Id: I2143b94a81eebfb22d99833aaf1f3743983dd80c Signed-off-by: Frans Hendriks Reviewed-on: https://review.coreboot.org/c/coreboot/+/34442 Reviewed-by: Patrick Georgi Reviewed-by: Wim Vervoorn Tested-by: build bot (Jenkins) --- 3rdparty/blobs | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/3rdparty/blobs b/3rdparty/blobs index 62aa0e0c54..034b278184 160000 --- a/3rdparty/blobs +++ b/3rdparty/blobs @@ -1 +1 @@ -Subproject commit 62aa0e0c54295bbb7b1a3e5e73f960bafdb59d04 +Subproject commit 034b27818450428f70aa9316c8bd0d65bacd8ee8 From bd3ac9c0b0d25dc365238be37d33af1f5c0f6525 Mon Sep 17 00:00:00 2001 From: Frans Hendriks Date: Thu, 25 Jul 2019 09:05:43 +0200 Subject: [PATCH 0194/1242] mb/facebook/fbg1701: Select HAVE_IFD_BIN and HAVE_ME_BIN Add IFD and ME binary to generate complete SPI image. BUG=N/A TEST=Boot Embedded Linux 4.20 on Facebook FBG-1701 Change-Id: I9370bf9f2bba8887988bc6484524f6cf53bed8db Signed-off-by: Frans Hendriks Reviewed-on: https://review.coreboot.org/c/coreboot/+/34448 Reviewed-by: Wim Vervoorn Reviewed-by: Patrick Georgi Reviewed-by: Paul Menzel Tested-by: build bot (Jenkins) --- src/mainboard/facebook/fbg1701/Kconfig | 2 ++ 1 file changed, 2 insertions(+) diff --git a/src/mainboard/facebook/fbg1701/Kconfig b/src/mainboard/facebook/fbg1701/Kconfig index 5e71db018a..c92626b7fa 100644 --- a/src/mainboard/facebook/fbg1701/Kconfig +++ b/src/mainboard/facebook/fbg1701/Kconfig @@ -19,6 +19,8 @@ config BOARD_SPECIFIC_OPTIONS def_bool y select BOARD_ROMSIZE_KB_8192 select HAVE_ACPI_TABLES + select HAVE_IFD_BIN + select HAVE_ME_BIN select HAVE_OPTION_TABLE select MAINBOARD_HAS_LPC_TPM select MAINBOARD_HAS_TPM2 From dc7b2de88bb56d3284c3ab6227cffefd8c76836b Mon Sep 17 00:00:00 2001 From: Wim Vervoorn Date: Thu, 7 Nov 2019 15:57:25 +0100 Subject: [PATCH 0195/1242] soc/intel/skylake/acpi/dptf: Disable DTRP when no DPTF_TSRX_SENSOR_ID is defined On mainboards without DPTF_TSRX_SENSOR_ID method DTRP is never called Only add the DTRP method when at least one sensor is enabled. BUG=N/A TEST=build Change-Id: I4fb26d5bbb7b334e759e7073b680f830f412467e Signed-off-by: Wim Vervoorn Reviewed-on: https://review.coreboot.org/c/coreboot/+/36856 Reviewed-by: Patrick Georgi Tested-by: build bot (Jenkins) --- src/soc/intel/skylake/acpi/dptf/thermal.asl | 2 ++ 1 file changed, 2 insertions(+) diff --git a/src/soc/intel/skylake/acpi/dptf/thermal.asl b/src/soc/intel/skylake/acpi/dptf/thermal.asl index 71f7b83db2..5f3548e014 100644 --- a/src/soc/intel/skylake/acpi/dptf/thermal.asl +++ b/src/soc/intel/skylake/acpi/dptf/thermal.asl @@ -75,6 +75,7 @@ Method (TPET) #endif } +#if defined(DPTF_TSR0_SENSOR_ID) || defined(DPTF_TSR1_SENSOR_ID) || defined(DPTF_TSR2_SENSOR_ID) /* * Method to return trip temperature value depending upon the device mode. * Arg0 --> Value to return when device is in tablet mode @@ -92,6 +93,7 @@ Method (DTRP, 2, Serialized) } #endif } +#endif #ifdef DPTF_TSR0_SENSOR_ID From bf53acca5e9c6b61086e42eb9e73fd4bb59a6f31 Mon Sep 17 00:00:00 2001 From: Arthur Heymans Date: Mon, 11 Nov 2019 21:14:39 +0100 Subject: [PATCH 0196/1242] nb/intel/x4x: Move boilerplate romstage to a common location This adds 3 mb romstage callbacks: - void mb_lpc_setup(void) to be used to set up the superio - void mb_get_spd_map(u8 spd_map[4]) to get I2C addresses of SPDs - (optional)mb_pre_raminit_setup(int s3_resume) to set up mainboard specific things before the raminit. Change-Id: Ic3b838856b3076ed05eeeea7c0656c2078462272 Signed-off-by: Arthur Heymans Reviewed-on: https://review.coreboot.org/c/coreboot/+/36758 Reviewed-by: Patrick Georgi Tested-by: build bot (Jenkins) --- src/mainboard/asrock/g41c-gs/romstage.c | 39 ++-------- src/mainboard/asus/p5qc/romstage.c | 48 +++---------- src/mainboard/asus/p5ql-em/romstage.c | 53 +++++--------- src/mainboard/asus/p5qpl-am/romstage.c | 50 ++++--------- src/mainboard/foxconn/g41s-k/romstage.c | 51 +++---------- .../gigabyte/ga-g41m-es2l/romstage.c | 48 +++---------- src/mainboard/intel/dg41wv/romstage.c | 42 ++--------- src/mainboard/intel/dg43gt/romstage.c | 48 +++---------- .../lenovo/thinkcentre_a58/romstage.c | 41 ++--------- src/northbridge/intel/x4x/Makefile.inc | 1 + src/northbridge/intel/x4x/romstage.c | 71 +++++++++++++++++++ src/northbridge/intel/x4x/x4x.h | 3 + 12 files changed, 156 insertions(+), 339 deletions(-) create mode 100644 src/northbridge/intel/x4x/romstage.c diff --git a/src/mainboard/asrock/g41c-gs/romstage.c b/src/mainboard/asrock/g41c-gs/romstage.c index b054897509..06e13eb652 100644 --- a/src/mainboard/asrock/g41c-gs/romstage.c +++ b/src/mainboard/asrock/g41c-gs/romstage.c @@ -16,11 +16,7 @@ */ #include -#include -#include -#include #include -#include #include #include #include @@ -30,9 +26,8 @@ #define SERIAL_DEV_R2 PNP_DEV(0x2e, NCT6776_SP1) #define SERIAL_DEV_R1 PNP_DEV(0x2e, W83627DHG_SP1) #define SUPERIO_DEV PNP_DEV(0x2e, 0) -#define LPC_DEV PCI_DEV(0, 0x1f, 0) -static void mb_lpc_setup(void) +void mb_lpc_setup(void) { /* Set GPIOs on superio, enable UART */ if (CONFIG(SUPERIO_NUVOTON_NCT6776)) { @@ -53,34 +48,8 @@ static void mb_lpc_setup(void) RCBA16(D29IR) = 0x0237; } -void mainboard_romstage_entry(void) +void mb_get_spd_map(u8 spd_map[4]) { - // ch0 ch1 - const u8 spd_addrmap[4] = { 0x50, 0, 0x52, 0 }; - u8 boot_path = 0; - u8 s3_resume; - - /* Set southbridge and Super I/O GPIOs. */ - i82801gx_lpc_setup(); - mb_lpc_setup(); - - console_init(); - - enable_smbus(); - - i82801gx_early_init(); - x4x_early_init(); - - s3_resume = southbridge_detect_s3_resume(); - if (s3_resume) - boot_path = BOOT_PATH_RESUME; - if (MCHBAR32(PMSTS_MCHBAR) & PMSTS_WARM_RESET) - boot_path = BOOT_PATH_WARM_RESET; - - sdram_initialize(boot_path, spd_addrmap); - - x4x_late_init(s3_resume); - - printk(BIOS_DEBUG, "x4x late init complete\n"); - + spd_map[0] = 0x50; + spd_map[2] = 0x52; } diff --git a/src/mainboard/asus/p5qc/romstage.c b/src/mainboard/asus/p5qc/romstage.c index 9a90f74189..53aa176b38 100644 --- a/src/mainboard/asus/p5qc/romstage.c +++ b/src/mainboard/asus/p5qc/romstage.c @@ -14,57 +14,27 @@ * GNU General Public License for more details. */ -#include -#include #include -#include #include -#include #include #include #define SERIAL_DEV PNP_DEV(0x2e, W83667HG_A_SP1) -#define LPC_DEV PCI_DEV(0, 0x1f, 0) -/* Early mainboard specific GPIO setup. - * We should use standard gpio.h eventually - */ - -static void mb_misc_rcba(void) +void mb_lpc_setup(void) { /* TODO? */ RCBA32(RCBA_CG) = 0xbf7f001f; RCBA32(0x3430) = 0x00000002; RCBA32(0x3f00) = 0x00000038; -} -void mainboard_romstage_entry(void) -{ - const u8 spd_addrmap[4] = { 0x50, 0x51, 0x52, 0x53 }; - u8 boot_path = 0; - u8 s3_resume; - - /* Set southbridge and Super I/O GPIOs. */ - i82801jx_lpc_setup(); - mb_misc_rcba(); winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); - - console_init(); - - enable_smbus(); - - i82801jx_early_init(); - x4x_early_init(); - - s3_resume = southbridge_detect_s3_resume(); - if (s3_resume) - boot_path = BOOT_PATH_RESUME; - if (MCHBAR32(PMSTS_MCHBAR) & PMSTS_WARM_RESET) - boot_path = BOOT_PATH_WARM_RESET; - - sdram_initialize(boot_path, spd_addrmap); - - x4x_late_init(s3_resume); - - printk(BIOS_DEBUG, "x4x late init complete\n"); +} + +void mb_get_spd_map(u8 spd_map[4]) +{ + spd_map[0] = 0x50; + spd_map[1] = 0x51; + spd_map[2] = 0x52; + spd_map[3] = 0x53; } diff --git a/src/mainboard/asus/p5ql-em/romstage.c b/src/mainboard/asus/p5ql-em/romstage.c index c7ade1c541..fa22a645d4 100644 --- a/src/mainboard/asus/p5ql-em/romstage.c +++ b/src/mainboard/asus/p5ql-em/romstage.c @@ -12,22 +12,22 @@ * GNU General Public License for more details. */ -#include #include #include -#include -#include #include #include #include -#include #include #include #include #define SERIAL_DEV PNP_DEV(0x2e, W83627DHG_SP1) #define GPIO_DEV PNP_DEV(0x2e, W83627DHG_GPIO2345_V) -#define LPC_DEV PCI_DEV(0, 0x1f, 0) + +void mb_lpc_setup(void) +{ + winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); +} static u8 msr_get_fsb(void) { @@ -103,41 +103,20 @@ static int setup_sio_gpio(void) return need_reset; } -void mainboard_romstage_entry(void) +void mb_pre_raminit_setup(int s3_resume) { - /* This board has first dimm slot of each channel hooked up to - rank0 and rank1, while the second dimm slot is only connected - to rank1. The raminit does not support such setups - const u8 spd_addrmap[4] = { 0x50, 0x51, 0x52, 0x53 }; */ - const u8 spd_addrmap[4] = { 0x50, 0, 0x52, 0 }; - u8 boot_path = 0; - u8 s3_resume; - - /* Set southbridge and Super I/O GPIOs. */ - i82801jx_lpc_setup(); - winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); - - console_init(); - - enable_smbus(); - - i82801jx_early_init(); - x4x_early_init(); - - s3_resume = southbridge_detect_s3_resume(); - if (s3_resume) - boot_path = BOOT_PATH_RESUME; - if (MCHBAR32(PMSTS_MCHBAR) & PMSTS_WARM_RESET) - boot_path = BOOT_PATH_WARM_RESET; - if (!s3_resume && setup_sio_gpio()) { printk(BIOS_DEBUG, "Needs reset to configure CPU BSEL straps\n"); full_reset(); } - - sdram_initialize(boot_path, spd_addrmap); - - x4x_late_init(s3_resume); - - printk(BIOS_DEBUG, "x4x late init complete\n"); +} + +void mb_get_spd_map(u8 spd_map[4]) +{ + /* This board has first dimm slot of each channel hooked up to + rank0 and rank1, while the second dimm slot is only connected + to rank1. The raminit does not support such setups. So only the + first dimms of each channel are used. */ + spd_map[0] = 0x50; + spd_map[2] = 0x52; } diff --git a/src/mainboard/asus/p5qpl-am/romstage.c b/src/mainboard/asus/p5qpl-am/romstage.c index de3972db4e..ad16c0f72a 100644 --- a/src/mainboard/asus/p5qpl-am/romstage.c +++ b/src/mainboard/asus/p5qpl-am/romstage.c @@ -17,20 +17,20 @@ #include #include -#include #include -#include #include #include #include -#include -#include #include #include #define SERIAL_DEV PNP_DEV(0x2e, W83627DHG_SP1) #define GPIO_DEV PNP_DEV(0x2e, W83627DHG_GPIO2345_V) -#define LPC_DEV PCI_DEV(0, 0x1f, 0) + +void mb_lpc_setup(void) +{ + winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); +} static u8 msr_get_fsb(void) { @@ -127,40 +127,16 @@ static int setup_sio_gpio(void) return need_reset; } -void mainboard_romstage_entry(void) +void mb_pre_raminit_setup(int s3_resume) { - // ch0 ch1 - const u8 spd_addrmap[4] = { 0x50, 0, 0x52, 0 }; - u8 boot_path = 0; - u8 s3_resume; - - /* Set southbridge and Super I/O GPIOs. */ - i82801gx_lpc_setup(); - winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); - - console_init(); - - enable_smbus(); - - i82801gx_early_init(); - x4x_early_init(); - - s3_resume = southbridge_detect_s3_resume(); - if (s3_resume) - boot_path = BOOT_PATH_RESUME; - if (MCHBAR32(PMSTS_MCHBAR) & PMSTS_WARM_RESET) - boot_path = BOOT_PATH_WARM_RESET; - if (!s3_resume && setup_sio_gpio()) { - printk(BIOS_DEBUG, - "Needs reset to configure CPU BSEL straps\n"); + printk(BIOS_DEBUG, "Needs reset to configure CPU BSEL straps\n"); full_reset(); } - - sdram_initialize(boot_path, spd_addrmap); - - x4x_late_init(s3_resume); - - printk(BIOS_DEBUG, "x4x late init complete\n"); - +} + +void mb_get_spd_map(u8 spd_map[4]) +{ + spd_map[0] = 0x50; + spd_map[2] = 0x52; } diff --git a/src/mainboard/foxconn/g41s-k/romstage.c b/src/mainboard/foxconn/g41s-k/romstage.c index 45ff7e458e..b4bd77d78b 100644 --- a/src/mainboard/foxconn/g41s-k/romstage.c +++ b/src/mainboard/foxconn/g41s-k/romstage.c @@ -16,20 +16,15 @@ * GNU General Public License for more details. */ -#include -#include -#include #include -#include #include #include #include -#define LPC_DEV PCI_DEV(0, 0x1f, 0) #define SERIAL_DEV PNP_DEV(0x2e, IT8720F_SP1) #define GPIO_DEV PNP_DEV(0x2e, IT8720F_GPIO) -static void mb_lpc_setup(void) +void mb_lpc_setup(void) { /* Set up GPIOs on Super I/O. */ ite_reg_write(GPIO_DEV, 0x25, 0x01); @@ -55,43 +50,13 @@ static void mb_lpc_setup(void) RCBA16(D29IR) = 0x0237; RCBA32(FD) |= FD_INTLAN; -} -void mainboard_romstage_entry(void) -{ - // ch0 ch1 -#if CONFIG(BOARD_FOXCONN_G41S_K) - const u8 spd_addrmap[4] = { 0x50, 0, 0, 0 }; -#else - /* TODO adapt raminit such that other slots can be used - * for single rank dimms */ - const u8 spd_addrmap[4] = { 0x50, 0, 0x52, 0 }; -#endif - u8 boot_path = 0; - u8 s3_resume; - - /* Set up southbridge and Super I/O GPIOs. */ - i82801gx_lpc_setup(); - mb_lpc_setup(); ite_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); - - console_init(); - - enable_smbus(); - - i82801gx_early_init(); - x4x_early_init(); - - s3_resume = southbridge_detect_s3_resume(); - if (s3_resume) - boot_path = BOOT_PATH_RESUME; - if (MCHBAR32(PMSTS_MCHBAR) & PMSTS_WARM_RESET) - boot_path = BOOT_PATH_WARM_RESET; - - sdram_initialize(boot_path, spd_addrmap); - - x4x_late_init(s3_resume); - - printk(BIOS_DEBUG, "x4x late init complete\n"); - +} + +void mb_get_spd_map(u8 spd_map[4]) +{ + spd_map[0] = 0x50; + if (CONFIG(BOARD_FOXCONN_G41M)) + spd_map[2] = 0x52; } diff --git a/src/mainboard/gigabyte/ga-g41m-es2l/romstage.c b/src/mainboard/gigabyte/ga-g41m-es2l/romstage.c index 16b157b2dd..bde4f33bef 100644 --- a/src/mainboard/gigabyte/ga-g41m-es2l/romstage.c +++ b/src/mainboard/gigabyte/ga-g41m-es2l/romstage.c @@ -14,14 +14,9 @@ * GNU General Public License for more details. */ -#include -#include #include -#include #include -#include #include -#include #include #include @@ -34,7 +29,7 @@ * We should use standard gpio.h eventually */ -static void mb_lpc_init(void) +void mb_lpc_setup(void) { pci_devfn_t dev; @@ -73,6 +68,11 @@ static void mb_lpc_init(void) ite_reg_write(EC_DEV, 0x70, 0x00); // Don't use IRQ9 ite_reg_write(EC_DEV, 0x30, 0x01); // Enable + ite_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); + + /* Disable SIO reboot */ + ite_reg_write(GPIO_DEV, 0xEF, 0x7E); + /* IRQ routing */ RCBA32(D31IP) = 0x00002210; RCBA32(D30IP) = 0x00002100; @@ -84,38 +84,8 @@ static void mb_lpc_init(void) RCBA32(D27IR) = 0x00000000; } -void mainboard_romstage_entry(void) +void mb_get_spd_map(u8 spd_map[4]) { - // ch0 ch1 - const u8 spd_addrmap[4] = { 0x50, 0, 0x52, 0 }; - u8 boot_path = 0; - u8 s3_resume; - - /* Set southbridge and Super I/O GPIOs. */ - i82801gx_lpc_setup(); - mb_lpc_init(); - ite_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); - - /* Disable SIO reboot */ - ite_reg_write(GPIO_DEV, 0xEF, 0x7E); - - console_init(); - - enable_smbus(); - - i82801gx_early_init(); - x4x_early_init(); - - s3_resume = southbridge_detect_s3_resume(); - if (s3_resume) - boot_path = BOOT_PATH_RESUME; - if (MCHBAR32(PMSTS_MCHBAR) & PMSTS_WARM_RESET) - boot_path = BOOT_PATH_WARM_RESET; - - sdram_initialize(boot_path, spd_addrmap); - - x4x_late_init(s3_resume); - - printk(BIOS_DEBUG, "x4x late init complete\n"); - + spd_map[0] = 0x50; + spd_map[2] = 0x52; } diff --git a/src/mainboard/intel/dg41wv/romstage.c b/src/mainboard/intel/dg41wv/romstage.c index 0d7c162272..ff018af5f6 100644 --- a/src/mainboard/intel/dg41wv/romstage.c +++ b/src/mainboard/intel/dg41wv/romstage.c @@ -16,19 +16,14 @@ */ #include -#include -#include -#include #include -#include #include #include #include #define SERIAL_DEV PNP_DEV(0x2e, W83627DHG_SP1) -#define LPC_DEV PCI_DEV(0, 0x1f, 0) -static void mb_lpc_setup(void) +void mb_lpc_setup(void) { /* Set GPIOs on superio, enable UART */ pnp_enter_ext_func_mode(SERIAL_DEV); @@ -38,40 +33,15 @@ static void mb_lpc_setup(void) pnp_exit_ext_func_mode(SERIAL_DEV); + winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); + /* IRQ routing */ RCBA16(D31IR) = 0x0132; RCBA16(D29IR) = 0x0237; } -void mainboard_romstage_entry(void) +void mb_get_spd_map(u8 spd_map[4]) { - // ch0 ch1 - const u8 spd_addrmap[4] = { 0x50, 0, 0x52, 0 }; - u8 boot_path = 0; - u8 s3_resume; - - /* Set southbridge and Super I/O GPIOs. */ - i82801gx_lpc_setup(); - mb_lpc_setup(); - winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); - - console_init(); - - enable_smbus(); - - i82801gx_early_init(); - x4x_early_init(); - - s3_resume = southbridge_detect_s3_resume(); - if (s3_resume) - boot_path = BOOT_PATH_RESUME; - if (MCHBAR32(PMSTS_MCHBAR) & PMSTS_WARM_RESET) - boot_path = BOOT_PATH_WARM_RESET; - - sdram_initialize(boot_path, spd_addrmap); - - x4x_late_init(s3_resume); - - printk(BIOS_DEBUG, "x4x late init complete\n"); - + spd_map[0] = 0x50; + spd_map[2] = 0x52; } diff --git a/src/mainboard/intel/dg43gt/romstage.c b/src/mainboard/intel/dg43gt/romstage.c index b851f98627..71fd87ad74 100644 --- a/src/mainboard/intel/dg43gt/romstage.c +++ b/src/mainboard/intel/dg43gt/romstage.c @@ -14,23 +14,14 @@ * GNU General Public License for more details. */ -#include -#include #include -#include #include -#include #include #include #define SERIAL_DEV PNP_DEV(0x2e, W83627DHG_SP1) -#define LPC_DEV PCI_DEV(0, 0x1f, 0) -/* Early mainboard specific GPIO setup. - * We should use standard gpio.h eventually - */ - -static void mb_misc_rcba(void) +void mb_lpc_setup(void) { RCBA32(0x3410) = 0x00060464; RCBA32(RCBA_BUC) &= ~BUC_LAND; @@ -38,35 +29,14 @@ static void mb_misc_rcba(void) RCBA32(0x341c) = 0xbf7f001f; RCBA32(0x3430) = 0x00000002; RCBA32(0x3f00) = 0x0000000b; -} -void mainboard_romstage_entry(void) -{ - const u8 spd_addrmap[4] = { 0x50, 0x51, 0x52, 0x53 }; - u8 boot_path = 0; - u8 s3_resume; - - /* Set southbridge and Super I/O GPIOs. */ - i82801jx_lpc_setup(); - mb_misc_rcba(); winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); - - console_init(); - - enable_smbus(); - - i82801jx_early_init(); - x4x_early_init(); - - s3_resume = southbridge_detect_s3_resume(); - if (s3_resume) - boot_path = BOOT_PATH_RESUME; - if (MCHBAR32(PMSTS_MCHBAR) & PMSTS_WARM_RESET) - boot_path = BOOT_PATH_WARM_RESET; - - sdram_initialize(boot_path, spd_addrmap); - - x4x_late_init(s3_resume); - - printk(BIOS_DEBUG, "x4x late init complete\n"); +} + +void mb_get_spd_map(u8 spd_map[4]) +{ + spd_map[0] = 0x50; + spd_map[1] = 0x51; + spd_map[2] = 0x52; + spd_map[3] = 0x53; } diff --git a/src/mainboard/lenovo/thinkcentre_a58/romstage.c b/src/mainboard/lenovo/thinkcentre_a58/romstage.c index 8be2c86734..5594cbdda6 100644 --- a/src/mainboard/lenovo/thinkcentre_a58/romstage.c +++ b/src/mainboard/lenovo/thinkcentre_a58/romstage.c @@ -15,45 +15,18 @@ * GNU General Public License for more details. */ -#include -#include -#include #include -#include -#include #include #define SERIAL_DEV PNP_DEV(0x2e, SMSCSUPERIO_SP1) -#define LPC_DEV PCI_DEV(0, 0x1f, 0) -void mainboard_romstage_entry(void) +void mb_lpc_setup(void) { - // ch0 ch1 - const u8 spd_addrmap[4] = { 0x50, 0, 0x52, 0 }; - u8 boot_path = 0; - u8 s3_resume; - - /* Set southbridge and Super I/O GPIOs. */ - i82801gx_lpc_setup(); smscsuperio_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); - - console_init(); - - enable_smbus(); - - i82801gx_early_init(); - x4x_early_init(); - - s3_resume = southbridge_detect_s3_resume(); - if (s3_resume) - boot_path = BOOT_PATH_RESUME; - if (MCHBAR32(PMSTS_MCHBAR) & PMSTS_WARM_RESET) - boot_path = BOOT_PATH_WARM_RESET; - - sdram_initialize(boot_path, spd_addrmap); - - x4x_late_init(s3_resume); - - printk(BIOS_DEBUG, "x4x late init complete\n"); - +} + +void mb_get_spd_map(u8 spd_map[4]) +{ + spd_map[0] = 0x50; + spd_map[2] = 0x52; } diff --git a/src/northbridge/intel/x4x/Makefile.inc b/src/northbridge/intel/x4x/Makefile.inc index b7fd2fe7ae..79a03cb77e 100644 --- a/src/northbridge/intel/x4x/Makefile.inc +++ b/src/northbridge/intel/x4x/Makefile.inc @@ -23,6 +23,7 @@ romstage-y += memmap.c romstage-y += rcven.c romstage-y += raminit_tables.c romstage-y += dq_dqs.c +romstage-y += romstage.c ramstage-y += acpi.c ramstage-y += memmap.c diff --git a/src/northbridge/intel/x4x/romstage.c b/src/northbridge/intel/x4x/romstage.c new file mode 100644 index 0000000000..c3a503643f --- /dev/null +++ b/src/northbridge/intel/x4x/romstage.c @@ -0,0 +1,71 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include +#include +#include + +#if CONFIG(SOUTHBRIDGE_INTEL_I82801JX) +#include +#elif CONFIG(SOUTHBRIDGE_INTEL_I82801GX) +#include +#endif + +__weak void mb_pre_raminit_setup(int s3_resume) +{ +} + +void mainboard_romstage_entry(void) +{ + u8 spd_addr_map[4] = {}; + u8 boot_path = 0; + u8 s3_resume; + +#if CONFIG(SOUTHBRIDGE_INTEL_I82801JX) + i82801jx_lpc_setup(); +#elif CONFIG(SOUTHBRIDGE_INTEL_I82801GX) + i82801gx_lpc_setup(); +#endif + + mb_lpc_setup(); + + console_init(); + + enable_smbus(); + +#if CONFIG(SOUTHBRIDGE_INTEL_I82801JX) + i82801jx_early_init(); +#elif CONFIG(SOUTHBRIDGE_INTEL_I82801GX) + i82801gx_early_init(); +#endif + + x4x_early_init(); + + s3_resume = southbridge_detect_s3_resume(); + mb_pre_raminit_setup(s3_resume); + + if (s3_resume) + boot_path = BOOT_PATH_RESUME; + if (MCHBAR32(PMSTS_MCHBAR) & PMSTS_WARM_RESET) + boot_path = BOOT_PATH_WARM_RESET; + + mb_get_spd_map(spd_addr_map); + sdram_initialize(boot_path, spd_addr_map); + + x4x_late_init(s3_resume); + + printk(BIOS_DEBUG, "x4x late init complete\n"); +} diff --git a/src/northbridge/intel/x4x/x4x.h b/src/northbridge/intel/x4x/x4x.h index 76e82d9494..e4a6c215d8 100644 --- a/src/northbridge/intel/x4x/x4x.h +++ b/src/northbridge/intel/x4x/x4x.h @@ -373,6 +373,9 @@ enum ddr2_signals { void x4x_early_init(void); void x4x_late_init(int s3resume); +void mb_lpc_setup(void); +void mb_get_spd_map(u8 spd_map[4]); +void mb_pre_raminit_setup(int s3_resume); u32 decode_igd_memory_size(u32 gms); u32 decode_igd_gtt_size(u32 gsm); u32 decode_tseg_size(const u32 esmramc); From dc584c3f221bb59ee6b89e5517617b9d1d74bcf3 Mon Sep 17 00:00:00 2001 From: Arthur Heymans Date: Tue, 12 Nov 2019 20:37:21 +0100 Subject: [PATCH 0197/1242] nb/intel/i945: Move boilerplate romstage to a common location This adds callbacks for mainboard specific init. Change-Id: Ib67bc492a7b7f02f9b57a52fd6730e16501b436e Signed-off-by: Arthur Heymans Reviewed-on: https://review.coreboot.org/c/coreboot/+/36787 Reviewed-by: HAOUAS Elyes Tested-by: build bot (Jenkins) --- src/mainboard/apple/macbook21/romstage.c | 57 +--------- src/mainboard/asus/p5gc-mx/romstage.c | 61 ++--------- src/mainboard/getac/p470/romstage.c | 61 +---------- .../gigabyte/ga-945gcm-s2l/romstage.c | 66 ++---------- src/mainboard/ibase/mb899/romstage.c | 55 +--------- src/mainboard/intel/d945gclf/romstage.c | 52 +-------- src/mainboard/kontron/986lcd-m/romstage.c | 59 +---------- src/mainboard/lenovo/t60/romstage.c | 92 +++++----------- src/mainboard/lenovo/x60/romstage.c | 100 +++++------------- src/mainboard/roda/rk886ex/romstage.c | 56 +--------- src/northbridge/intel/i945/Makefile.inc | 1 + src/northbridge/intel/i945/i945.h | 12 +++ src/northbridge/intel/i945/romstage.c | 95 +++++++++++++++++ 13 files changed, 189 insertions(+), 578 deletions(-) create mode 100644 src/northbridge/intel/i945/romstage.c diff --git a/src/mainboard/apple/macbook21/romstage.c b/src/mainboard/apple/macbook21/romstage.c index 41c0e9f384..d4654de118 100644 --- a/src/mainboard/apple/macbook21/romstage.c +++ b/src/mainboard/apple/macbook21/romstage.c @@ -15,19 +15,10 @@ * GNU General Public License for more details. */ -#include -#include -#include -#include -#include -#include -#include #include -#include #include -#include -static void rcba_config(void) +void mainboard_late_rcba_config(void) { /* V0CTL Virtual Channel 0 Resource Control */ RCBA32(0x0014) = 0x80000001; @@ -57,49 +48,3 @@ static void rcba_config(void) RCBA32(0x1e9c) = 0x000200f0; RCBA32(0x1e98) = 0x000c0801; } - -void mainboard_romstage_entry(void) -{ - int s3resume = 0; - const u8 spd_addrmap[2 * DIMM_SOCKETS] = { 0x50, 0x51, 0x52, 0x53 }; - - enable_lapic(); - - i82801gx_lpc_setup(); - - /* Set up the console */ - console_init(); - - if (MCHBAR16(SSKPD) == 0xCAFE) { - printk(BIOS_DEBUG, - "Soft reset detected, rebooting properly.\n"); - system_reset(); - } - - /* Perform some early chipset initialization required - * before RAM initialization can work - */ - i82801gx_early_init(); - i945_early_initialization(); - - s3resume = southbridge_detect_s3_resume(); - - /* Enable SPD ROMs and DDR-II DRAM */ - enable_smbus(); - - if (CONFIG(DEBUG_RAM_SETUP)) - dump_spd_registers(); - - sdram_initialize(s3resume ? 2 : 0, spd_addrmap); - - /* This should probably go away. Until now it is required - * and mainboard specific - */ - rcba_config(); - - /* Chipset Errata! */ - fixup_i945_errata(); - - /* Initialize the internal PCIe links before we go into stage2 */ - i945_late_initialization(s3resume); -} diff --git a/src/mainboard/asus/p5gc-mx/romstage.c b/src/mainboard/asus/p5gc-mx/romstage.c index 0cc38a03e8..eef603bbf5 100644 --- a/src/mainboard/asus/p5gc-mx/romstage.c +++ b/src/mainboard/asus/p5gc-mx/romstage.c @@ -19,16 +19,11 @@ #include #include #include -#include -#include #include #include #include -#include #include -#include #include -#include #include #include #include @@ -96,65 +91,27 @@ static u8 msr_get_fsb(void) return fsbcfg; } -static void rcba_config(void) +void mainboard_late_rcba_config(void) { /* Enable PCIe Root Port Clock Gate */ RCBA32(CG) = 0x00000001; } -void mainboard_romstage_entry(void) + +void mainboard_pre_raminit_config(int s3_resume) { - int s3resume = 0, boot_mode = 0; - u8 c_bsel = msr_get_fsb(); - - enable_lapic(); - - i82801gx_lpc_setup(); - - winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); - - /* Set up the console */ - console_init(); - - if (MCHBAR16(SSKPD) == 0xCAFE) { - printk(BIOS_DEBUG, "soft reset detected.\n"); - boot_mode = 1; - } - - /* Perform some early chipset initialization required - * before RAM initialization can work - */ - i82801gx_early_init(); - i945_early_initialization(); - - s3resume = southbridge_detect_s3_resume(); - /* * Result is that FSB is incorrect on s3 resume (fixed at 800MHz). * Some CPU accept this others don't. */ - if (!s3resume && setup_sio_gpio(c_bsel)) { + if (!s3_resume && setup_sio_gpio(c_bsel)) { printk(BIOS_DEBUG, "Needs reset to configure CPU BSEL straps\n"); full_reset(); } - - /* Enable SPD ROMs and DDR-II DRAM */ - enable_smbus(); - - if (CONFIG(DEBUG_RAM_SETUP)) - dump_spd_registers(); - - sdram_initialize(s3resume ? 2 : boot_mode, NULL); - - /* This should probably go away. Until now it is required - * and mainboard specific - */ - rcba_config(); - - /* Chipset Errata! */ - fixup_i945_errata(); - - /* Initialize the internal PCIe links before we go into stage2 */ - i945_late_initialization(s3resume); +} + +void mainboard_superio_config(void) +{ + winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); } diff --git a/src/mainboard/getac/p470/romstage.c b/src/mainboard/getac/p470/romstage.c index 8c41190b02..2da9d06ff9 100644 --- a/src/mainboard/getac/p470/romstage.c +++ b/src/mainboard/getac/p470/romstage.c @@ -16,22 +16,16 @@ #include #include -#include #include #include #include -#include -#include #include #include -#include #include -#include #include -#include #include "option_table.h" -static void setup_special_ich7_gpios(void) +void mainboard_pre_raminit_config(int s3_resume) { u32 gpios; @@ -52,7 +46,7 @@ static void setup_special_ich7_gpios(void) } /* Override the default lpc decode ranges */ -static void mb_lpc_decode(void) +void mainboard_lpc_decode(void) { int lpt_en = 0; if (read_option(lpt, 0) != 0) @@ -81,7 +75,7 @@ static void pnp_exit_ext_func_mode(pnp_devfn_t dev) outb(0xaa, port); } -static void early_superio_config(void) +void mainboard_superio_config(void) { pnp_devfn_t dev; @@ -126,7 +120,7 @@ static void early_superio_config(void) pnp_exit_ext_func_mode(dev); } -static void rcba_config(void) +void mainboard_late_rcba_config(void) { /* Set up virtual channel 0 */ //RCBA32(0x0014) = 0x80000001; @@ -158,50 +152,3 @@ static void rcba_config(void) RCBA32(0x1e9c) = 0x000200f0; RCBA32(0x1e98) = 0x000c0801; } - -void mainboard_romstage_entry(void) -{ - int s3resume = 0; - - enable_lapic(); - - i82801gx_lpc_setup(); - mb_lpc_decode(); - early_superio_config(); - - /* Set up the console */ - console_init(); - - if (MCHBAR16(SSKPD) == 0xCAFE) { - system_reset(); - } - - /* Perform some early chipset initialization required - * before RAM initialization can work - */ - i82801gx_early_init(); - i945_early_initialization(); - - setup_special_ich7_gpios(); - - s3resume = southbridge_detect_s3_resume(); - - /* Enable SPD ROMs and DDR-II DRAM */ - enable_smbus(); - - if (CONFIG(DEBUG_RAM_SETUP)) - dump_spd_registers(); - - sdram_initialize(s3resume ? 2 : 0, NULL); - - /* This should probably go away. Until now it is required - * and mainboard specific - */ - rcba_config(); - - /* Chipset Errata! */ - fixup_i945_errata(); - - /* Initialize the internal PCIe links before we go into stage2 */ - i945_late_initialization(s3resume); -} diff --git a/src/mainboard/gigabyte/ga-945gcm-s2l/romstage.c b/src/mainboard/gigabyte/ga-945gcm-s2l/romstage.c index cd1345148d..467a66f959 100644 --- a/src/mainboard/gigabyte/ga-945gcm-s2l/romstage.c +++ b/src/mainboard/gigabyte/ga-945gcm-s2l/romstage.c @@ -14,25 +14,17 @@ * GNU General Public License for more details. */ -#include -#include -#include -#include #include #include -#include -#include #include -#include #include -#include #define SERIAL_DEV PNP_DEV(0x2e, IT8718F_SP1) #define GPIO_DEV PNP_DEV(0x2e, IT8718F_GPIO) #define EC_DEV PNP_DEV(0x2e, IT8718F_EC) #define SUPERIO_DEV PNP_DEV(0x2e, 0) -static void setup_sio(void) +void mainboard_superio_config(void) { /* Set default GPIOs on superio */ ite_reg_write(GPIO_DEV, 0x25, 0x40); @@ -54,59 +46,15 @@ static void setup_sio(void) ite_reg_write(EC_DEV, 0x70, 0x00); // Don't use IRQ9 ite_reg_write(EC_DEV, 0x30, 0xff); // Enable -} -static void rcba_config(void) -{ - /* Enable PCIe Root Port Clock Gate */ - RCBA32(CG) = 0x00000001; -} - -void mainboard_romstage_entry(void) -{ - int s3resume = 0, boot_mode = 0; - enable_lapic(); - - i82801gx_lpc_setup(); - /* Enable SuperIO PM */ - setup_sio(); ite_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); /* Disable SIO reboot */ ite_reg_write(GPIO_DEV, 0xEF, 0x7E); - - /* Set up the console */ - console_init(); - - if (MCHBAR16(SSKPD) == 0xCAFE) { - printk(BIOS_DEBUG, "soft reset detected.\n"); - boot_mode = 1; - } - - /* Perform some early chipset initialization required - * before RAM initialization can work - */ - i82801gx_early_init(); - i945_early_initialization(); - - s3resume = southbridge_detect_s3_resume(); - - /* Enable SPD ROMs and DDR-II DRAM */ - enable_smbus(); - - if (CONFIG(DEBUG_RAM_SETUP)) - dump_spd_registers(); - - sdram_initialize(s3resume ? 2 : boot_mode, NULL); - - /* This should probably go away. Until now it is required - * and mainboard specific - */ - rcba_config(); - - /* Chipset Errata! */ - fixup_i945_errata(); - - /* Initialize the internal PCIe links before we go into stage2 */ - i945_late_initialization(s3resume); +} + +void mainboard_late_rcba_config(void) +{ + /* Enable PCIe Root Port Clock Gate */ + RCBA32(CG) = 0x00000001; } diff --git a/src/mainboard/ibase/mb899/romstage.c b/src/mainboard/ibase/mb899/romstage.c index 47e28a8dc1..2bc3cde103 100644 --- a/src/mainboard/ibase/mb899/romstage.c +++ b/src/mainboard/ibase/mb899/romstage.c @@ -14,20 +14,13 @@ */ #include -#include #include -#include -#include -#include #include -#include #include #include -#include #include #include #include -#include #define SERIAL_DEV PNP_DEV(0x4e, W83627EHG_SP1) #define SUPERIO_DEV PNP_DEV(0x4e, 0) @@ -36,7 +29,7 @@ * Also set up the GPIOs from the beginning. This is the "no schematic * but safe anyways" method. */ -static void early_superio_config_w83627ehg(void) +void mainboard_superio_config(void) { pnp_devfn_t dev; @@ -103,7 +96,7 @@ static void early_superio_config_w83627ehg(void) pnp_exit_conf_state(dev); } -static void rcba_config(void) +void mainboard_late_rcba_config(void) { /* Set up virtual channel 0 */ //RCBA32(0x0014) = 0x80000001; @@ -123,47 +116,3 @@ static void rcba_config(void) /* Enable PCIe Root Port Clock Gate */ // RCBA32(0x341c) = 0x00000001; } - -void mainboard_romstage_entry(void) -{ - int s3resume = 0; - - enable_lapic(); - - i82801gx_lpc_setup(); - early_superio_config_w83627ehg(); - - /* Set up the console */ - console_init(); - - if (MCHBAR16(SSKPD) == 0xCAFE) { - system_reset(); - } - - /* Perform some early chipset initialization required - * before RAM initialization can work - */ - i82801gx_early_init(); - i945_early_initialization(); - - s3resume = southbridge_detect_s3_resume(); - - /* Enable SPD ROMs and DDR-II DRAM */ - enable_smbus(); - - if (CONFIG(DEBUG_RAM_SETUP)) - dump_spd_registers(); - - sdram_initialize(s3resume ? 2 : 0, NULL); - - /* This should probably go away. Until now it is required - * and mainboard specific - */ - rcba_config(); - - /* Chipset Errata! */ - fixup_i945_errata(); - - /* Initialize the internal PCIe links before we go into stage2 */ - i945_late_initialization(s3resume); -} diff --git a/src/mainboard/intel/d945gclf/romstage.c b/src/mainboard/intel/d945gclf/romstage.c index ada6e61c00..7a8f5d1656 100644 --- a/src/mainboard/intel/d945gclf/romstage.c +++ b/src/mainboard/intel/d945gclf/romstage.c @@ -13,22 +13,14 @@ * GNU General Public License for more details. */ -#include -#include -#include -#include #include -#include -#include #include -#include #include -#include #define SERIAL_DEV PNP_DEV(0x2e, LPC47M15X_SP1) #define PME_DEV PNP_DEV(0x2e, LPC47M15X_PME) -static void rcba_config(void) +void mainboard_late_rcba_config(void) { /* Set up virtual channel 0 */ //RCBA32(0x0014) = 0x80000001; @@ -47,49 +39,9 @@ static void rcba_config(void) // RCBA32(0x341c) = 0x00000001; } -void mainboard_romstage_entry(void) +void mainboard_superio_config(void) { - int s3resume = 0, boot_mode = 0; - - enable_lapic(); - - i82801gx_lpc_setup(); /* Enable SuperIO PM */ lpc47m15x_enable_serial(PME_DEV, 0x680); lpc47m15x_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); /* 0x3f8 */ - - /* Set up the console */ - console_init(); - - if (MCHBAR16(SSKPD) == 0xCAFE) { - printk(BIOS_DEBUG, "soft reset detected.\n"); - boot_mode = 1; - } - - /* Perform some early chipset initialization required - * before RAM initialization can work - */ - i82801gx_early_init(); - i945_early_initialization(); - - s3resume = southbridge_detect_s3_resume(); - - /* Enable SPD ROMs and DDR-II DRAM */ - enable_smbus(); - - if (CONFIG(DEBUG_RAM_SETUP)) - dump_spd_registers(); - - sdram_initialize(s3resume ? 2 : boot_mode, NULL); - - /* This should probably go away. Until now it is required - * and mainboard specific - */ - rcba_config(); - - /* Chipset Errata! */ - fixup_i945_errata(); - - /* Initialize the internal PCIe links before we go into stage2 */ - i945_late_initialization(s3resume); } diff --git a/src/mainboard/kontron/986lcd-m/romstage.c b/src/mainboard/kontron/986lcd-m/romstage.c index d67a60b1e8..2c894534f3 100644 --- a/src/mainboard/kontron/986lcd-m/romstage.c +++ b/src/mainboard/kontron/986lcd-m/romstage.c @@ -13,20 +13,12 @@ * GNU General Public License for more details. */ -#include -#include -#include -#include -#include -#include #include #include #include #include #include -#include #include -#include #include #include @@ -35,7 +27,7 @@ #define SERIAL_DEV PNP_DEV(0x2e, W83627THG_SP1) /* Override the default lpc decode ranges */ -static void mb_lpc_decode(void) +void mainboard_lpc_decode(void) { int lpt_en = 0; if (read_option(lpt, 0) != 0) @@ -49,7 +41,7 @@ static void mb_lpc_decode(void) * the two. Also set up the GPIOs from the beginning. This is the "no schematic * but safe anyways" method. */ -static void early_superio_config_w83627thg(void) +void mainboard_superio_config(void) { pnp_devfn_t dev; @@ -149,7 +141,7 @@ static void early_superio_config_w83627thg(void) pnp_exit_conf_state(dev); } -static void rcba_config(void) +void mainboard_late_rcba_config(void) { /* Set up virtual channel 0 */ @@ -167,48 +159,3 @@ static void rcba_config(void) /* Enable PCIe Root Port Clock Gate */ } - -void mainboard_romstage_entry(void) -{ - int s3resume = 0; - - enable_lapic(); - - i82801gx_lpc_setup(); - mb_lpc_decode(); - early_superio_config_w83627thg(); - - /* Set up the console */ - console_init(); - - if (MCHBAR16(SSKPD) == 0xCAFE) { - system_reset(); - } - - /* Perform some early chipset initialization required - * before RAM initialization can work - */ - i82801gx_early_init(); - i945_early_initialization(); - - s3resume = southbridge_detect_s3_resume(); - - /* Enable SPD ROMs and DDR-II DRAM */ - enable_smbus(); - - if (CONFIG(DEBUG_RAM_SETUP)) - dump_spd_registers(); - - sdram_initialize(s3resume ? 2 : 0, NULL); - - /* This should probably go away. Until now it is required - * and mainboard specific - */ - rcba_config(); - - /* Chipset Errata! */ - fixup_i945_errata(); - - /* Initialize the internal PCIe links before we go into stage2 */ - i945_late_initialization(s3resume); -} diff --git a/src/mainboard/lenovo/t60/romstage.c b/src/mainboard/lenovo/t60/romstage.c index ab49e6e979..5076ada75f 100644 --- a/src/mainboard/lenovo/t60/romstage.c +++ b/src/mainboard/lenovo/t60/romstage.c @@ -15,25 +15,18 @@ * GNU General Public License for more details. */ -#include -#include #include +#include #include #include -#include #include -#include -#include -#include #include -#include #include #include -#include #include "dock.h" /* Override the default lpc decode ranges */ -static void mb_lpc_decode(void) +void mainboard_lpc_decode(void) { // decode range pci_write_config16(PCI_DEV(0, 0x1f, 0), LPC_IO_DEC, 0x0210); @@ -55,7 +48,25 @@ static void early_superio_config(void) pnp_set_enable(dev, 1); } -static void rcba_config(void) +void mainboard_superio_config(void) +{ + /* Set up GPIO's early since it is needed for dock init */ + i82801gx_setup_bars(); + setup_pch_gpios(&mainboard_gpio_map); + + int dock_err = dlpc_init(); + + /* We prefer Legacy I/O module over docking */ + if (legacy_io_present()) { + legacy_io_init(); + early_superio_config(); + } else if (!dock_err && dock_present()) { + dock_connect(); + early_superio_config(); + } +} + +void mainboard_late_rcba_config(void) { /* Set up virtual channel 0 */ RCBA32(V0CTL) = 0x80000001; @@ -86,63 +97,8 @@ static void rcba_config(void) RCBA64(IOTR3) = 0x000200f0000c0801ULL; } -void mainboard_romstage_entry(void) +void mainboard_get_spd_map(u8 spd_map[4]) { - int s3resume = 0; - int dock_err; - const u8 spd_addrmap[2 * DIMM_SOCKETS] = { 0x50, 0, 0x51, 0 }; - - enable_lapic(); - - /* Set up GPIO's early since it is needed for dock init */ - i82801gx_setup_bars(); - setup_pch_gpios(&mainboard_gpio_map); - - i82801gx_lpc_setup(); - mb_lpc_decode(); - - dock_err = dlpc_init(); - - /* We prefer Legacy I/O module over docking */ - if (legacy_io_present()) { - legacy_io_init(); - early_superio_config(); - } else if (!dock_err && dock_present()) { - dock_connect(); - early_superio_config(); - } - - /* Setup the console */ - console_init(); - - if (MCHBAR16(SSKPD) == 0xCAFE) { - system_reset(); - } - - /* Perform some early chipset initialization required - * before RAM initialization can work - */ - i82801gx_early_init(); - i945_early_initialization(); - - s3resume = southbridge_detect_s3_resume(); - - /* Enable SPD ROMs and DDR-II DRAM */ - enable_smbus(); - - if (CONFIG(DEBUG_RAM_SETUP)) - dump_spd_registers(); - - sdram_initialize(s3resume ? 2 : 0, spd_addrmap); - - /* This should probably go away. Until now it is required - * and mainboard specific - */ - rcba_config(); - - /* Chipset Errata! */ - fixup_i945_errata(); - - /* Initialize the internal PCIe links before we go into stage2 */ - i945_late_initialization(s3resume); + spd_map[0] = 0x50; + spd_map[2] = 0x51; } diff --git a/src/mainboard/lenovo/x60/romstage.c b/src/mainboard/lenovo/x60/romstage.c index 6eeb2d12ba..d230aa3c57 100644 --- a/src/mainboard/lenovo/x60/romstage.c +++ b/src/mainboard/lenovo/x60/romstage.c @@ -15,26 +15,18 @@ * GNU General Public License for more details. */ -#include -#include #include +#include +#include #include #include -#include -#include -#include -#include -#include -#include #include -#include #include #include -#include #include "dock.h" /* Override the default lpc decode ranges */ -static void mb_lpc_decode(void) +void mainboard_lpc_decode(void) { // decode range pci_write_config16(PCI_DEV(0, 0x1f, 0), LPC_IO_DEC, 0x0210); @@ -56,7 +48,24 @@ static void early_superio_config(void) pnp_set_enable(dev, 1); } -static void rcba_config(void) +void mainboard_superio_config(void) +{ + /* Set up GPIO's early since it is needed for dock init */ + i82801gx_setup_bars(); + setup_pch_gpios(&mainboard_gpio_map); + + dlpc_init(); + /* dock_init initializes the DLPC switch on + * thinpad side, so this is required even + * if we're undocked. + */ + if (dock_present()) { + dock_connect(); + early_superio_config(); + } +} + +void mainboard_late_rcba_config(void) { /* Set up virtual channel 0 */ RCBA32(V0CTL) = 0x80000001; @@ -87,68 +96,9 @@ static void rcba_config(void) RCBA64(IOTR3) = 0x000200f0000c0801ULL; } -void mainboard_romstage_entry(void) + +void mainboard_get_spd_map(u8 spd_map[4]) { - int s3resume = 0; - const u8 spd_addrmap[2 * DIMM_SOCKETS] = { 0x50, 0, 0x51, 0 }; - - enable_lapic(); - - /* Set up GPIO's early since it is needed for dock init */ - i82801gx_setup_bars(); - setup_pch_gpios(&mainboard_gpio_map); - - i82801gx_lpc_setup(); - mb_lpc_decode(); - - dlpc_init(); - /* dock_init initializes the DLPC switch on - * thinpad side, so this is required even - * if we're undocked. - */ - if (dock_present()) { - dock_connect(); - early_superio_config(); - } - - /* Set up the console */ - console_init(); - - if (dock_present()) - printk(BIOS_DEBUG, "Dock is present\n"); - else - printk(BIOS_DEBUG, "Dock is not present\n"); - - if (MCHBAR16(SSKPD) == 0xCAFE) { - printk(BIOS_DEBUG, - "Soft reset detected, rebooting properly.\n"); - system_reset(); - } - - /* Perform some early chipset initialization required - * before RAM initialization can work - */ - i82801gx_early_init(); - i945_early_initialization(); - - s3resume = southbridge_detect_s3_resume(); - - /* Enable SPD ROMs and DDR-II DRAM */ - enable_smbus(); - - if (CONFIG(DEBUG_RAM_SETUP)) - dump_spd_registers(); - - sdram_initialize(s3resume ? 2 : 0, spd_addrmap); - - /* This should probably go away. Until now it is required - * and mainboard specific - */ - rcba_config(); - - /* Chipset Errata! */ - fixup_i945_errata(); - - /* Initialize the internal PCIe links before we go into stage2 */ - i945_late_initialization(s3resume); + spd_map[0] = 0x50; + spd_map[2] = 0x51; } diff --git a/src/mainboard/roda/rk886ex/romstage.c b/src/mainboard/roda/rk886ex/romstage.c index f1a638dad1..388c61a9a6 100644 --- a/src/mainboard/roda/rk886ex/romstage.c +++ b/src/mainboard/roda/rk886ex/romstage.c @@ -20,18 +20,13 @@ #include #include #include -#include #include -#include -#include #include -#include #include -#include #include "option_table.h" /* Override the default lpc decode ranges */ -static void mb_lpc_decode(void) +void mainboard_lpc_decode(void) { int lpt_en = 0; if (read_option(lpt, 0) != 0) @@ -59,7 +54,7 @@ static void pnp_exit_ext_func_mode(pnp_devfn_t dev) outb(0xaa, port); } -static void early_superio_config(void) +void mainboard_superio_config(void) { pnp_devfn_t dev; @@ -94,7 +89,7 @@ static void early_superio_config(void) pnp_exit_ext_func_mode(dev); } -static void rcba_config(void) +void mainboard_late_rcba_config(void) { /* Set up virtual channel 0 */ @@ -129,50 +124,7 @@ static void init_artec_dongle(void) outb(0xf4, 0x88); } -void mainboard_romstage_entry(void) +void mainboard_pre_raminit_config(int s3_resume) { - int s3resume = 0; - - enable_lapic(); - - i82801gx_lpc_setup(); - mb_lpc_decode(); - early_superio_config(); - - /* Set up the console */ - console_init(); - - if (MCHBAR16(SSKPD) == 0xCAFE) { - system_reset(); - } - - /* Perform some early chipset initialization required - * before RAM initialization can work - */ - i82801gx_early_init(); - i945_early_initialization(); - - /* This has to happen after i945_early_initialization() */ init_artec_dongle(); - - s3resume = southbridge_detect_s3_resume(); - - /* Enable SPD ROMs and DDR-II DRAM */ - enable_smbus(); - - if (CONFIG(DEBUG_RAM_SETUP)) - dump_spd_registers(); - - sdram_initialize(s3resume ? 2 : 0, NULL); - - /* This should probably go away. Until now it is required - * and mainboard specific - */ - rcba_config(); - - /* Chipset Errata! */ - fixup_i945_errata(); - - /* Initialize the internal PCIe links before we go into stage2 */ - i945_late_initialization(s3resume); } diff --git a/src/northbridge/intel/i945/Makefile.inc b/src/northbridge/intel/i945/Makefile.inc index af3c23580c..585d61b218 100644 --- a/src/northbridge/intel/i945/Makefile.inc +++ b/src/northbridge/intel/i945/Makefile.inc @@ -20,6 +20,7 @@ ramstage-y += northbridge.c ramstage-y += gma.c ramstage-y += acpi.c +romstage-y += romstage.c romstage-y += memmap.c romstage-y += raminit.c romstage-y += early_init.c diff --git a/src/northbridge/intel/i945/i945.h b/src/northbridge/intel/i945/i945.h index 4dd5379469..e9e6f4d094 100644 --- a/src/northbridge/intel/i945/i945.h +++ b/src/northbridge/intel/i945/i945.h @@ -375,6 +375,18 @@ void sdram_dump_mchbar_registers(void); u32 decode_igd_memory_size(u32 gms); u32 decode_tseg_size(const u8 esmramc); +/* Romstage mainboard callbacks */ +/* Optional: Override the default LPC config. */ +void mainboard_lpc_decode(void); +/* Optional: Initialize the superio for serial output. */ +void mainboard_superio_config(void); +/* Optional: mainboard specific init after console init and before raminit. */ +void mainboard_pre_raminit_config(int s3_resume); +/* Mainboard specific RCBA init. Happens after raminit. */ +void mainboard_late_rcba_config(void); +/* Optional: mainboard callback to get SPD map */ +void mainboard_get_spd_map(u8 spd_map[4]); + #endif /* __ACPI__ */ #endif /* NORTHBRIDGE_INTEL_I945_H */ diff --git a/src/northbridge/intel/i945/romstage.c b/src/northbridge/intel/i945/romstage.c new file mode 100644 index 0000000000..c11a78ab0e --- /dev/null +++ b/src/northbridge/intel/i945/romstage.c @@ -0,0 +1,95 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +__weak void mainboard_lpc_decode(void) +{ +} + +__weak void mainboard_superio_config(void) +{ +} + +__weak void mainboard_pre_raminit_config(int s3_resume) +{ +} + +__weak void mainboard_get_spd_map(u8 spd_map[4]) +{ + spd_map[0] = 0x50; + spd_map[1] = 0x51; + spd_map[2] = 0x52; + spd_map[3] = 0x53; +} + +void mainboard_romstage_entry(void) +{ + int s3resume = 0; + u8 spd_map[4] = {}; + + enable_lapic(); + + i82801gx_lpc_setup(); + mainboard_lpc_decode(); + mainboard_superio_config(); + + /* Set up the console */ + console_init(); + + if (MCHBAR16(SSKPD) == 0xCAFE) { + system_reset(); + } + + /* Perform some early chipset initialization required + * before RAM initialization can work + */ + i82801gx_early_init(); + i945_early_initialization(); + + s3resume = southbridge_detect_s3_resume(); + + /* Enable SPD ROMs and DDR-II DRAM */ + enable_smbus(); + + mainboard_pre_raminit_config(s3resume); + + if (CONFIG(DEBUG_RAM_SETUP)) + dump_spd_registers(); + + mainboard_get_spd_map(spd_map); + + sdram_initialize(s3resume ? 2 : 0, spd_map); + + /* This should probably go away. Until now it is required + * and mainboard specific + */ + mainboard_late_rcba_config(); + + /* Chipset Errata! */ + fixup_i945_errata(); + + /* Initialize the internal PCIe links before we go into stage2 */ + i945_late_initialization(s3resume); +} From e27c013f39f0433dac57a754b3484553a536f30d Mon Sep 17 00:00:00 2001 From: Arthur Heymans Date: Tue, 12 Nov 2019 23:34:13 +0100 Subject: [PATCH 0198/1242] nb/intel/i945: Move to C_ENVIRONMENT_BOOTBLOCK Console init in bootblock will be done in a separate CL. Change-Id: Ia2405013f262d904aa82be323e928223dbb4296c Signed-off-by: Arthur Heymans Reviewed-on: https://review.coreboot.org/c/coreboot/+/36795 Reviewed-by: HAOUAS Elyes Tested-by: build bot (Jenkins) --- src/cpu/intel/car/core2/cache_as_ram.S | 4 -- src/cpu/intel/car/p4-netburst/cache_as_ram.S | 8 ---- src/cpu/intel/socket_441/Kconfig | 9 ++++ src/cpu/intel/socket_441/Makefile.inc | 3 +- src/cpu/intel/socket_m/Kconfig | 8 ++++ src/cpu/intel/socket_m/Makefile.inc | 3 +- src/northbridge/intel/i945/Kconfig | 6 +-- src/northbridge/intel/i945/Makefile.inc | 2 + src/northbridge/intel/i945/bootblock.c | 7 ++- src/southbridge/intel/i82801gx/Kconfig | 4 -- src/southbridge/intel/i82801gx/Makefile.inc | 2 +- src/southbridge/intel/i82801gx/bootblock.c | 15 ++++--- .../intel/i82801gx/bootblock_gcc.c | 44 ------------------- 13 files changed, 38 insertions(+), 77 deletions(-) delete mode 100644 src/southbridge/intel/i82801gx/bootblock_gcc.c diff --git a/src/cpu/intel/car/core2/cache_as_ram.S b/src/cpu/intel/car/core2/cache_as_ram.S index 0e0fa77bb0..73618d92f6 100644 --- a/src/cpu/intel/car/core2/cache_as_ram.S +++ b/src/cpu/intel/car/core2/cache_as_ram.S @@ -18,14 +18,10 @@ #define CACHE_AS_RAM_SIZE CONFIG_DCACHE_RAM_SIZE #define CACHE_AS_RAM_BASE CONFIG_DCACHE_RAM_BASE -#if CONFIG(C_ENVIRONMENT_BOOTBLOCK) #if ((CONFIG_C_ENV_BOOTBLOCK_SIZE & (CONFIG_C_ENV_BOOTBLOCK_SIZE - 1)) != 0) #error "CONFIG_C_ENV_BOOTBLOCK_SIZE must be a power of 2!" #endif #define XIP_ROM_SIZE CONFIG_C_ENV_BOOTBLOCK_SIZE -#else -#define XIP_ROM_SIZE CONFIG_XIP_ROM_SIZE -#endif .global bootblock_pre_c_entry diff --git a/src/cpu/intel/car/p4-netburst/cache_as_ram.S b/src/cpu/intel/car/p4-netburst/cache_as_ram.S index 7815eb3235..fdeb0af8ec 100644 --- a/src/cpu/intel/car/p4-netburst/cache_as_ram.S +++ b/src/cpu/intel/car/p4-netburst/cache_as_ram.S @@ -18,22 +18,14 @@ /* Macro to access Local APIC registers at default base. */ #define LAPIC(x) $(LAPIC_DEFAULT_BASE | LAPIC_ ## x) -#if !CONFIG(C_ENVIRONMENT_BOOTBLOCK) -/* Fixed location, ASSERTED in failover.ld if it changes. */ -.set ap_sipi_vector_in_rom, 0xff -#endif #define CACHE_AS_RAM_SIZE CONFIG_DCACHE_RAM_SIZE #define CACHE_AS_RAM_BASE CONFIG_DCACHE_RAM_BASE -#if CONFIG(C_ENVIRONMENT_BOOTBLOCK) #if ((CONFIG_C_ENV_BOOTBLOCK_SIZE & (CONFIG_C_ENV_BOOTBLOCK_SIZE - 1)) != 0) #error "CONFIG_C_ENV_BOOTBLOCK_SIZE must be a power of 2!" #endif #define XIP_ROM_SIZE CONFIG_C_ENV_BOOTBLOCK_SIZE -#else -#define XIP_ROM_SIZE CONFIG_XIP_ROM_SIZE -#endif .global bootblock_pre_c_entry diff --git a/src/cpu/intel/socket_441/Kconfig b/src/cpu/intel/socket_441/Kconfig index ac249c5755..af43f72e53 100644 --- a/src/cpu/intel/socket_441/Kconfig +++ b/src/cpu/intel/socket_441/Kconfig @@ -8,6 +8,11 @@ config SOCKET_SPECIFIC_OPTIONS # dummy select CPU_INTEL_MODEL_106CX select MMX select SSE + select SETUP_XIP_CACHE + +config C_ENV_BOOTBLOCK_SIZE + hex + default 0x4000 config DCACHE_RAM_BASE hex @@ -17,4 +22,8 @@ config DCACHE_RAM_SIZE hex default 0x8000 +config DCACHE_BSP_STACK_SIZE + hex + default 0x2000 + endif # CPU_INTEL_SOCKET_441 diff --git a/src/cpu/intel/socket_441/Makefile.inc b/src/cpu/intel/socket_441/Makefile.inc index 7993294a17..e21bf03ff5 100644 --- a/src/cpu/intel/socket_441/Makefile.inc +++ b/src/cpu/intel/socket_441/Makefile.inc @@ -8,7 +8,8 @@ subdirs-y += ../microcode subdirs-y += ../hyperthreading subdirs-y += ../speedstep -cpu_incs-y += $(src)/cpu/intel/car/p4-netburst/cache_as_ram.S +bootblock-y += ../car/p4-netburst/cache_as_ram.S +bootblock-y += ../car/bootblock.c postcar-y += ../car/p4-netburst/exit_car.S romstage-y += ../car/romstage.c diff --git a/src/cpu/intel/socket_m/Kconfig b/src/cpu/intel/socket_m/Kconfig index 02330f9cb8..8b1f5edda5 100644 --- a/src/cpu/intel/socket_m/Kconfig +++ b/src/cpu/intel/socket_m/Kconfig @@ -18,4 +18,12 @@ config DCACHE_RAM_SIZE hex default 0x8000 +config DCACHE_BSP_STACK_SIZE + hex + default 0x2000 + +config C_ENV_BOOTBLOCK_SIZE + hex + default 0x8000 + endif diff --git a/src/cpu/intel/socket_m/Makefile.inc b/src/cpu/intel/socket_m/Makefile.inc index 96f16dc6b3..61e4e58f13 100644 --- a/src/cpu/intel/socket_m/Makefile.inc +++ b/src/cpu/intel/socket_m/Makefile.inc @@ -9,7 +9,8 @@ subdirs-y += ../microcode subdirs-y += ../hyperthreading subdirs-y += ../speedstep -cpu_incs-y += $(src)/cpu/intel/car/core2/cache_as_ram.S +bootblock-y += ../car/core2/cache_as_ram.S +bootblock-y += ../car/bootblock.c postcar-y += ../car/p4-netburst/exit_car.S romstage-y += ../car/romstage.c diff --git a/src/northbridge/intel/i945/Kconfig b/src/northbridge/intel/i945/Kconfig index 0159bf2fde..5aa004d9eb 100644 --- a/src/northbridge/intel/i945/Kconfig +++ b/src/northbridge/intel/i945/Kconfig @@ -27,16 +27,14 @@ config NORTHBRIDGE_SPECIFIC_OPTIONS # dummy select INTEL_EDID select HAVE_VGA_TEXT_FRAMEBUFFER if MAINBOARD_DO_NATIVE_VGA_INIT select PARALLEL_MP + select C_ENVIRONMENT_BOOTBLOCK + select NO_BOOTBLOCK_CONSOLE config NORTHBRIDGE_INTEL_SUBTYPE_I945GC def_bool n config NORTHBRIDGE_INTEL_SUBTYPE_I945GM def_bool n -config BOOTBLOCK_NORTHBRIDGE_INIT - string - default "northbridge/intel/i945/bootblock.c" - config VGA_BIOS_ID string default "8086,27a2" if NORTHBRIDGE_INTEL_SUBTYPE_I945GM diff --git a/src/northbridge/intel/i945/Makefile.inc b/src/northbridge/intel/i945/Makefile.inc index 585d61b218..36dee6e571 100644 --- a/src/northbridge/intel/i945/Makefile.inc +++ b/src/northbridge/intel/i945/Makefile.inc @@ -15,6 +15,8 @@ ifeq ($(CONFIG_NORTHBRIDGE_INTEL_I945),y) +bootblock-y += bootblock.c + ramstage-y += memmap.c ramstage-y += northbridge.c ramstage-y += gma.c diff --git a/src/northbridge/intel/i945/bootblock.c b/src/northbridge/intel/i945/bootblock.c index 604088b1f3..e86abe5ab1 100644 --- a/src/northbridge/intel/i945/bootblock.c +++ b/src/northbridge/intel/i945/bootblock.c @@ -11,12 +11,11 @@ * GNU General Public License for more details. */ +#include #include +#include "i945.h" -/* Just re-define this instead of including i945.h. It blows up romcc. */ -#define PCIEXBAR 0x48 - -static void bootblock_northbridge_init(void) +void bootblock_early_northbridge_init(void) { uint32_t reg; diff --git a/src/southbridge/intel/i82801gx/Kconfig b/src/southbridge/intel/i82801gx/Kconfig index b0cdfd416c..17ee4fcab3 100644 --- a/src/southbridge/intel/i82801gx/Kconfig +++ b/src/southbridge/intel/i82801gx/Kconfig @@ -40,10 +40,6 @@ config EHCI_BAR hex default 0xfef00000 -config BOOTBLOCK_SOUTHBRIDGE_INIT - string - default "southbridge/intel/i82801gx/bootblock.c" - config HPET_MIN_TICKS hex default 0x80 diff --git a/src/southbridge/intel/i82801gx/Makefile.inc b/src/southbridge/intel/i82801gx/Makefile.inc index 31264295ad..c9ed899578 100644 --- a/src/southbridge/intel/i82801gx/Makefile.inc +++ b/src/southbridge/intel/i82801gx/Makefile.inc @@ -16,7 +16,7 @@ ifeq ($(CONFIG_SOUTHBRIDGE_INTEL_I82801GX),y) bootblock-y += early_init.c -bootblock-y += bootblock_gcc.c +bootblock-y += bootblock.c ramstage-y += i82801gx.c ramstage-y += ac97.c diff --git a/src/southbridge/intel/i82801gx/bootblock.c b/src/southbridge/intel/i82801gx/bootblock.c index 9d94d0cd25..4c464ff920 100644 --- a/src/southbridge/intel/i82801gx/bootblock.c +++ b/src/southbridge/intel/i82801gx/bootblock.c @@ -14,14 +14,13 @@ */ #include +#include #include "i82801gx.h" static void enable_spi_prefetch(void) { u8 reg8; - pci_devfn_t dev; - - dev = PCI_DEV(0, 0x1f, 0); + pci_devfn_t dev = PCI_DEV(0, 0x1f, 0); reg8 = pci_read_config8(dev, BIOS_CNTL); reg8 &= ~(3 << 2); @@ -29,13 +28,17 @@ static void enable_spi_prefetch(void) pci_write_config8(dev, BIOS_CNTL, reg8); } -static void bootblock_southbridge_init(void) +void bootblock_early_southbridge_init(void) { enable_spi_prefetch(); - /* Enable RCBA */ - pci_write_config32(PCI_DEV(0, 0x1f, 0), RCBA, (uintptr_t)DEFAULT_RCBA | 1); + i82801gx_setup_bars(); /* Enable upper 128bytes of CMOS */ RCBA32(0x3400) = (1 << 2); + + /* Disable watchdog timer */ + RCBA32(GCS) = RCBA32(GCS) | 0x20; + + i82801gx_lpc_setup(); } diff --git a/src/southbridge/intel/i82801gx/bootblock_gcc.c b/src/southbridge/intel/i82801gx/bootblock_gcc.c deleted file mode 100644 index 4c464ff920..0000000000 --- a/src/southbridge/intel/i82801gx/bootblock_gcc.c +++ /dev/null @@ -1,44 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 Sven Schnelle - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include "i82801gx.h" - -static void enable_spi_prefetch(void) -{ - u8 reg8; - pci_devfn_t dev = PCI_DEV(0, 0x1f, 0); - - reg8 = pci_read_config8(dev, BIOS_CNTL); - reg8 &= ~(3 << 2); - reg8 |= (2 << 2); /* Prefetching and Caching Enabled */ - pci_write_config8(dev, BIOS_CNTL, reg8); -} - -void bootblock_early_southbridge_init(void) -{ - enable_spi_prefetch(); - - i82801gx_setup_bars(); - - /* Enable upper 128bytes of CMOS */ - RCBA32(0x3400) = (1 << 2); - - /* Disable watchdog timer */ - RCBA32(GCS) = RCBA32(GCS) | 0x20; - - i82801gx_lpc_setup(); -} From c583920a748fb8bd7999142433ad08641b06283d Mon Sep 17 00:00:00 2001 From: Arthur Heymans Date: Tue, 12 Nov 2019 23:48:42 +0100 Subject: [PATCH 0199/1242] nb/intel/i945: Initialize console in bootblock Change-Id: Ic6ea158714998195614a63ee46a057f405de5616 Signed-off-by: Arthur Heymans Reviewed-on: https://review.coreboot.org/c/coreboot/+/36796 Tested-by: build bot (Jenkins) Reviewed-by: HAOUAS Elyes --- src/ec/lenovo/pmh7/Makefile.inc | 1 + src/mainboard/apple/macbook21/Makefile.inc | 2 ++ .../apple/macbook21/{romstage.c => early_init.c} | 0 src/mainboard/asus/p5gc-mx/Makefile.inc | 2 ++ src/mainboard/asus/p5gc-mx/{romstage.c => early_init.c} | 3 ++- src/mainboard/getac/p470/Makefile.inc | 2 ++ src/mainboard/getac/p470/{romstage.c => early_init.c} | 3 ++- src/mainboard/gigabyte/ga-945gcm-s2l/Makefile.inc | 2 ++ .../gigabyte/ga-945gcm-s2l/{romstage.c => early_init.c} | 3 ++- src/mainboard/ibase/mb899/Makefile.inc | 2 ++ src/mainboard/ibase/mb899/{romstage.c => early_init.c} | 3 ++- src/mainboard/intel/d945gclf/Makefile.inc | 2 ++ .../intel/d945gclf/{romstage.c => early_init.c} | 3 ++- src/mainboard/kontron/986lcd-m/Makefile.inc | 2 ++ .../kontron/986lcd-m/{romstage.c => early_init.c} | 3 ++- src/mainboard/lenovo/t60/Makefile.inc | 4 ++++ src/mainboard/lenovo/t60/{romstage.c => early_init.c} | 3 ++- src/mainboard/lenovo/x60/Makefile.inc | 4 ++++ src/mainboard/lenovo/x60/{romstage.c => early_init.c} | 3 ++- src/mainboard/roda/rk886ex/Makefile.inc | 2 ++ src/mainboard/roda/rk886ex/{romstage.c => early_init.c} | 3 ++- src/northbridge/intel/i945/Kconfig | 1 - src/northbridge/intel/i945/i945.h | 2 -- src/northbridge/intel/i945/romstage.c | 9 --------- src/southbridge/intel/common/Makefile.inc | 1 + 25 files changed, 44 insertions(+), 21 deletions(-) rename src/mainboard/apple/macbook21/{romstage.c => early_init.c} (100%) rename src/mainboard/asus/p5gc-mx/{romstage.c => early_init.c} (97%) rename src/mainboard/getac/p470/{romstage.c => early_init.c} (98%) rename src/mainboard/gigabyte/ga-945gcm-s2l/{romstage.c => early_init.c} (96%) rename src/mainboard/ibase/mb899/{romstage.c => early_init.c} (97%) rename src/mainboard/intel/d945gclf/{romstage.c => early_init.c} (94%) rename src/mainboard/kontron/986lcd-m/{romstage.c => early_init.c} (98%) rename src/mainboard/lenovo/t60/{romstage.c => early_init.c} (97%) rename src/mainboard/lenovo/x60/{romstage.c => early_init.c} (97%) rename src/mainboard/roda/rk886ex/{romstage.c => early_init.c} (98%) diff --git a/src/ec/lenovo/pmh7/Makefile.inc b/src/ec/lenovo/pmh7/Makefile.inc index d5524dca1f..c7c95c0009 100644 --- a/src/ec/lenovo/pmh7/Makefile.inc +++ b/src/ec/lenovo/pmh7/Makefile.inc @@ -1,5 +1,6 @@ ifeq ($(CONFIG_EC_LENOVO_PMH7),y) +bootblock-y += pmh7.c ramstage-y += pmh7.c smm-y += pmh7.c romstage-y += pmh7.c diff --git a/src/mainboard/apple/macbook21/Makefile.inc b/src/mainboard/apple/macbook21/Makefile.inc index 3dae61e8a8..b4f8b6573a 100644 --- a/src/mainboard/apple/macbook21/Makefile.inc +++ b/src/mainboard/apple/macbook21/Makefile.inc @@ -1 +1,3 @@ romstage-y += gpio.c +bootblock-y += early_init.c +romstage-y += early_init.c diff --git a/src/mainboard/apple/macbook21/romstage.c b/src/mainboard/apple/macbook21/early_init.c similarity index 100% rename from src/mainboard/apple/macbook21/romstage.c rename to src/mainboard/apple/macbook21/early_init.c diff --git a/src/mainboard/asus/p5gc-mx/Makefile.inc b/src/mainboard/asus/p5gc-mx/Makefile.inc index f3d7e76263..a34f3f31c7 100644 --- a/src/mainboard/asus/p5gc-mx/Makefile.inc +++ b/src/mainboard/asus/p5gc-mx/Makefile.inc @@ -1,2 +1,4 @@ ramstage-y += cstates.c romstage-y += gpio.c +bootblock-y += early_init.c +romstage-y += early_init.c diff --git a/src/mainboard/asus/p5gc-mx/romstage.c b/src/mainboard/asus/p5gc-mx/early_init.c similarity index 97% rename from src/mainboard/asus/p5gc-mx/romstage.c rename to src/mainboard/asus/p5gc-mx/early_init.c index eef603bbf5..6d37fed2ef 100644 --- a/src/mainboard/asus/p5gc-mx/romstage.c +++ b/src/mainboard/asus/p5gc-mx/early_init.c @@ -15,6 +15,7 @@ * GNU General Public License for more details. */ +#include #include #include #include @@ -111,7 +112,7 @@ void mainboard_pre_raminit_config(int s3_resume) } } -void mainboard_superio_config(void) +void bootblock_mainboard_early_init(void) { winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); } diff --git a/src/mainboard/getac/p470/Makefile.inc b/src/mainboard/getac/p470/Makefile.inc index ed9d39cec6..c8c8e0cc4a 100644 --- a/src/mainboard/getac/p470/Makefile.inc +++ b/src/mainboard/getac/p470/Makefile.inc @@ -15,3 +15,5 @@ ramstage-y += cstates.c romstage-y += gpio.c +bootblock-y += early_init.c +romstage-y += early_init.c diff --git a/src/mainboard/getac/p470/romstage.c b/src/mainboard/getac/p470/early_init.c similarity index 98% rename from src/mainboard/getac/p470/romstage.c rename to src/mainboard/getac/p470/early_init.c index 2da9d06ff9..3684c1c943 100644 --- a/src/mainboard/getac/p470/romstage.c +++ b/src/mainboard/getac/p470/early_init.c @@ -14,6 +14,7 @@ * GNU General Public License for more details. */ +#include #include #include #include @@ -75,7 +76,7 @@ static void pnp_exit_ext_func_mode(pnp_devfn_t dev) outb(0xaa, port); } -void mainboard_superio_config(void) +void bootblock_mainboard_early_init(void) { pnp_devfn_t dev; diff --git a/src/mainboard/gigabyte/ga-945gcm-s2l/Makefile.inc b/src/mainboard/gigabyte/ga-945gcm-s2l/Makefile.inc index f3d7e76263..a34f3f31c7 100644 --- a/src/mainboard/gigabyte/ga-945gcm-s2l/Makefile.inc +++ b/src/mainboard/gigabyte/ga-945gcm-s2l/Makefile.inc @@ -1,2 +1,4 @@ ramstage-y += cstates.c romstage-y += gpio.c +bootblock-y += early_init.c +romstage-y += early_init.c diff --git a/src/mainboard/gigabyte/ga-945gcm-s2l/romstage.c b/src/mainboard/gigabyte/ga-945gcm-s2l/early_init.c similarity index 96% rename from src/mainboard/gigabyte/ga-945gcm-s2l/romstage.c rename to src/mainboard/gigabyte/ga-945gcm-s2l/early_init.c index 467a66f959..7b82059580 100644 --- a/src/mainboard/gigabyte/ga-945gcm-s2l/romstage.c +++ b/src/mainboard/gigabyte/ga-945gcm-s2l/early_init.c @@ -14,6 +14,7 @@ * GNU General Public License for more details. */ +#include #include #include #include @@ -24,7 +25,7 @@ #define EC_DEV PNP_DEV(0x2e, IT8718F_EC) #define SUPERIO_DEV PNP_DEV(0x2e, 0) -void mainboard_superio_config(void) +void bootblock_mainboard_early_init(void) { /* Set default GPIOs on superio */ ite_reg_write(GPIO_DEV, 0x25, 0x40); diff --git a/src/mainboard/ibase/mb899/Makefile.inc b/src/mainboard/ibase/mb899/Makefile.inc index 3f072f553f..992c3736a7 100644 --- a/src/mainboard/ibase/mb899/Makefile.inc +++ b/src/mainboard/ibase/mb899/Makefile.inc @@ -1,3 +1,5 @@ ramstage-y += superio_hwm.c ramstage-y += cstates.c romstage-y += gpio.c +bootblock-y += early_init.c +romstage-y += early_init.c diff --git a/src/mainboard/ibase/mb899/romstage.c b/src/mainboard/ibase/mb899/early_init.c similarity index 97% rename from src/mainboard/ibase/mb899/romstage.c rename to src/mainboard/ibase/mb899/early_init.c index 2bc3cde103..ba8d30cf29 100644 --- a/src/mainboard/ibase/mb899/romstage.c +++ b/src/mainboard/ibase/mb899/early_init.c @@ -13,6 +13,7 @@ * GNU General Public License for more details. */ +#include #include #include #include @@ -29,7 +30,7 @@ * Also set up the GPIOs from the beginning. This is the "no schematic * but safe anyways" method. */ -void mainboard_superio_config(void) +void bootblock_mainboard_early_init(void) { pnp_devfn_t dev; diff --git a/src/mainboard/intel/d945gclf/Makefile.inc b/src/mainboard/intel/d945gclf/Makefile.inc index f3d7e76263..a34f3f31c7 100644 --- a/src/mainboard/intel/d945gclf/Makefile.inc +++ b/src/mainboard/intel/d945gclf/Makefile.inc @@ -1,2 +1,4 @@ ramstage-y += cstates.c romstage-y += gpio.c +bootblock-y += early_init.c +romstage-y += early_init.c diff --git a/src/mainboard/intel/d945gclf/romstage.c b/src/mainboard/intel/d945gclf/early_init.c similarity index 94% rename from src/mainboard/intel/d945gclf/romstage.c rename to src/mainboard/intel/d945gclf/early_init.c index 7a8f5d1656..c8dd3619c8 100644 --- a/src/mainboard/intel/d945gclf/romstage.c +++ b/src/mainboard/intel/d945gclf/early_init.c @@ -13,6 +13,7 @@ * GNU General Public License for more details. */ +#include #include #include #include @@ -39,7 +40,7 @@ void mainboard_late_rcba_config(void) // RCBA32(0x341c) = 0x00000001; } -void mainboard_superio_config(void) +void bootblock_mainboard_early_init(void) { /* Enable SuperIO PM */ lpc47m15x_enable_serial(PME_DEV, 0x680); diff --git a/src/mainboard/kontron/986lcd-m/Makefile.inc b/src/mainboard/kontron/986lcd-m/Makefile.inc index f3d7e76263..a34f3f31c7 100644 --- a/src/mainboard/kontron/986lcd-m/Makefile.inc +++ b/src/mainboard/kontron/986lcd-m/Makefile.inc @@ -1,2 +1,4 @@ ramstage-y += cstates.c romstage-y += gpio.c +bootblock-y += early_init.c +romstage-y += early_init.c diff --git a/src/mainboard/kontron/986lcd-m/romstage.c b/src/mainboard/kontron/986lcd-m/early_init.c similarity index 98% rename from src/mainboard/kontron/986lcd-m/romstage.c rename to src/mainboard/kontron/986lcd-m/early_init.c index 2c894534f3..48fe4935ae 100644 --- a/src/mainboard/kontron/986lcd-m/romstage.c +++ b/src/mainboard/kontron/986lcd-m/early_init.c @@ -13,6 +13,7 @@ * GNU General Public License for more details. */ +#include #include #include #include @@ -41,7 +42,7 @@ void mainboard_lpc_decode(void) * the two. Also set up the GPIOs from the beginning. This is the "no schematic * but safe anyways" method. */ -void mainboard_superio_config(void) +void bootblock_mainboard_early_init(void) { pnp_devfn_t dev; diff --git a/src/mainboard/lenovo/t60/Makefile.inc b/src/mainboard/lenovo/t60/Makefile.inc index f646af8fd5..b604b6b126 100644 --- a/src/mainboard/lenovo/t60/Makefile.inc +++ b/src/mainboard/lenovo/t60/Makefile.inc @@ -14,5 +14,9 @@ ## smm-y += dock.c +bootblock-y += dock.c romstage-y += dock.c +bootblock-y += gpio.c romstage-y += gpio.c +bootblock-y += early_init.c +romstage-y += early_init.c diff --git a/src/mainboard/lenovo/t60/romstage.c b/src/mainboard/lenovo/t60/early_init.c similarity index 97% rename from src/mainboard/lenovo/t60/romstage.c rename to src/mainboard/lenovo/t60/early_init.c index 5076ada75f..d3de1e4c94 100644 --- a/src/mainboard/lenovo/t60/romstage.c +++ b/src/mainboard/lenovo/t60/early_init.c @@ -15,6 +15,7 @@ * GNU General Public License for more details. */ +#include #include #include #include @@ -48,7 +49,7 @@ static void early_superio_config(void) pnp_set_enable(dev, 1); } -void mainboard_superio_config(void) +void bootblock_mainboard_early_init(void) { /* Set up GPIO's early since it is needed for dock init */ i82801gx_setup_bars(); diff --git a/src/mainboard/lenovo/x60/Makefile.inc b/src/mainboard/lenovo/x60/Makefile.inc index a7ad539a1f..7fb2f0268e 100644 --- a/src/mainboard/lenovo/x60/Makefile.inc +++ b/src/mainboard/lenovo/x60/Makefile.inc @@ -14,6 +14,10 @@ ## smm-y += dock.c +bootblock-y += dock.c romstage-y += dock.c ramstage-y += dock.c +bootblock-y += gpio.c romstage-y += gpio.c +bootblock-y += early_init.c +romstage-y += early_init.c diff --git a/src/mainboard/lenovo/x60/romstage.c b/src/mainboard/lenovo/x60/early_init.c similarity index 97% rename from src/mainboard/lenovo/x60/romstage.c rename to src/mainboard/lenovo/x60/early_init.c index d230aa3c57..459c2461ca 100644 --- a/src/mainboard/lenovo/x60/romstage.c +++ b/src/mainboard/lenovo/x60/early_init.c @@ -15,6 +15,7 @@ * GNU General Public License for more details. */ +#include #include #include #include @@ -48,7 +49,7 @@ static void early_superio_config(void) pnp_set_enable(dev, 1); } -void mainboard_superio_config(void) +void bootblock_mainboard_early_init(void) { /* Set up GPIO's early since it is needed for dock init */ i82801gx_setup_bars(); diff --git a/src/mainboard/roda/rk886ex/Makefile.inc b/src/mainboard/roda/rk886ex/Makefile.inc index 2c68d384d1..ab011673fd 100644 --- a/src/mainboard/roda/rk886ex/Makefile.inc +++ b/src/mainboard/roda/rk886ex/Makefile.inc @@ -16,3 +16,5 @@ ramstage-y += m3885.c ramstage-y += cstates.c romstage-y += gpio.c +bootblock-y += early_init.c +romstage-y += early_init.c diff --git a/src/mainboard/roda/rk886ex/romstage.c b/src/mainboard/roda/rk886ex/early_init.c similarity index 98% rename from src/mainboard/roda/rk886ex/romstage.c rename to src/mainboard/roda/rk886ex/early_init.c index 388c61a9a6..dff1a6fe03 100644 --- a/src/mainboard/roda/rk886ex/romstage.c +++ b/src/mainboard/roda/rk886ex/early_init.c @@ -14,6 +14,7 @@ * GNU General Public License for more details. */ +#include #include #include #include @@ -54,7 +55,7 @@ static void pnp_exit_ext_func_mode(pnp_devfn_t dev) outb(0xaa, port); } -void mainboard_superio_config(void) +void bootblock_mainboard_early_init(void) { pnp_devfn_t dev; diff --git a/src/northbridge/intel/i945/Kconfig b/src/northbridge/intel/i945/Kconfig index 5aa004d9eb..a0550ec3c7 100644 --- a/src/northbridge/intel/i945/Kconfig +++ b/src/northbridge/intel/i945/Kconfig @@ -28,7 +28,6 @@ config NORTHBRIDGE_SPECIFIC_OPTIONS # dummy select HAVE_VGA_TEXT_FRAMEBUFFER if MAINBOARD_DO_NATIVE_VGA_INIT select PARALLEL_MP select C_ENVIRONMENT_BOOTBLOCK - select NO_BOOTBLOCK_CONSOLE config NORTHBRIDGE_INTEL_SUBTYPE_I945GC def_bool n diff --git a/src/northbridge/intel/i945/i945.h b/src/northbridge/intel/i945/i945.h index e9e6f4d094..82f80ff725 100644 --- a/src/northbridge/intel/i945/i945.h +++ b/src/northbridge/intel/i945/i945.h @@ -378,8 +378,6 @@ u32 decode_tseg_size(const u8 esmramc); /* Romstage mainboard callbacks */ /* Optional: Override the default LPC config. */ void mainboard_lpc_decode(void); -/* Optional: Initialize the superio for serial output. */ -void mainboard_superio_config(void); /* Optional: mainboard specific init after console init and before raminit. */ void mainboard_pre_raminit_config(int s3_resume); /* Mainboard specific RCBA init. Happens after raminit. */ diff --git a/src/northbridge/intel/i945/romstage.c b/src/northbridge/intel/i945/romstage.c index c11a78ab0e..479588129d 100644 --- a/src/northbridge/intel/i945/romstage.c +++ b/src/northbridge/intel/i945/romstage.c @@ -28,10 +28,6 @@ __weak void mainboard_lpc_decode(void) { } -__weak void mainboard_superio_config(void) -{ -} - __weak void mainboard_pre_raminit_config(int s3_resume) { } @@ -51,12 +47,7 @@ void mainboard_romstage_entry(void) enable_lapic(); - i82801gx_lpc_setup(); mainboard_lpc_decode(); - mainboard_superio_config(); - - /* Set up the console */ - console_init(); if (MCHBAR16(SSKPD) == 0xCAFE) { system_reset(); diff --git a/src/southbridge/intel/common/Makefile.inc b/src/southbridge/intel/common/Makefile.inc index 68e423af59..9ff0ebc5a1 100644 --- a/src/southbridge/intel/common/Makefile.inc +++ b/src/southbridge/intel/common/Makefile.inc @@ -32,6 +32,7 @@ bootblock-$(CONFIG_USBDEBUG) += usb_debug.c romstage-$(CONFIG_USBDEBUG) += usb_debug.c ramstage-$(CONFIG_USBDEBUG) += usb_debug.c +bootblock-$(CONFIG_SOUTHBRIDGE_INTEL_COMMON_GPIO) += gpio.c romstage-$(CONFIG_SOUTHBRIDGE_INTEL_COMMON_GPIO) += gpio.c ramstage-$(CONFIG_SOUTHBRIDGE_INTEL_COMMON_GPIO) += gpio.c smm-$(CONFIG_SOUTHBRIDGE_INTEL_COMMON_GPIO) += gpio.c From 7843bd560e65b0a83e99b42bdd58dd6363656c56 Mon Sep 17 00:00:00 2001 From: Arthur Heymans Date: Mon, 11 Nov 2019 21:56:37 +0100 Subject: [PATCH 0200/1242] nb/intel/x4x: Move to C_ENVIRONMENT_BOOTBLOCK There is some overlap between things done in bootblock and romstage like setting BARs. Change-Id: Icd1de34c3b5c0f36f2a5249116d1829ee3956f38 Signed-off-by: Arthur Heymans Reviewed-on: https://review.coreboot.org/c/coreboot/+/36759 Reviewed-by: Patrick Georgi Tested-by: build bot (Jenkins) --- src/cpu/intel/socket_LGA775/Kconfig | 4 ++++ src/cpu/intel/socket_LGA775/Makefile.inc | 7 +++++++ src/mainboard/asrock/g41c-gs/Makefile.inc | 3 +++ .../asrock/g41c-gs/{romstage.c => early_init.c} | 3 ++- src/mainboard/asus/p5qc/Makefile.inc | 3 +++ src/mainboard/asus/p5qc/{romstage.c => early_init.c} | 3 ++- src/mainboard/asus/p5ql-em/Makefile.inc | 3 +++ .../asus/p5ql-em/{romstage.c => early_init.c} | 3 ++- src/mainboard/asus/p5qpl-am/Makefile.inc | 3 +++ .../asus/p5qpl-am/{romstage.c => early_init.c} | 3 ++- src/mainboard/foxconn/g41s-k/Makefile.inc | 3 +++ .../foxconn/g41s-k/{romstage.c => early_init.c} | 3 ++- src/mainboard/gigabyte/ga-g41m-es2l/Makefile.inc | 3 +++ .../gigabyte/ga-g41m-es2l/{romstage.c => early_init.c} | 3 ++- src/mainboard/intel/dg41wv/Makefile.inc | 3 +++ .../intel/dg41wv/{romstage.c => early_init.c} | 3 ++- src/mainboard/intel/dg43gt/Makefile.inc | 3 +++ .../intel/dg43gt/{romstage.c => early_init.c} | 3 ++- src/mainboard/lenovo/thinkcentre_a58/Makefile.inc | 3 +++ .../thinkcentre_a58/{romstage.c => early_init.c} | 3 ++- src/northbridge/intel/x4x/Kconfig | 5 +---- src/northbridge/intel/x4x/Makefile.inc | 2 ++ src/northbridge/intel/x4x/bootblock.c | 8 +++----- src/northbridge/intel/x4x/romstage.c | 10 ---------- src/northbridge/intel/x4x/x4x.h | 1 - src/southbridge/intel/i82801jx/Kconfig | 5 ----- src/southbridge/intel/i82801jx/Makefile.inc | 3 +++ src/southbridge/intel/i82801jx/bootblock.c | 9 +++++---- src/southbridge/intel/i82801jx/early_init.c | 2 +- src/southbridge/intel/i82801jx/i82801jx.h | 1 + 30 files changed, 72 insertions(+), 39 deletions(-) rename src/mainboard/asrock/g41c-gs/{romstage.c => early_init.c} (96%) rename src/mainboard/asus/p5qc/{romstage.c => early_init.c} (94%) rename src/mainboard/asus/p5ql-em/{romstage.c => early_init.c} (97%) rename src/mainboard/asus/p5qpl-am/{romstage.c => early_init.c} (98%) rename src/mainboard/foxconn/g41s-k/{romstage.c => early_init.c} (96%) rename src/mainboard/gigabyte/ga-g41m-es2l/{romstage.c => early_init.c} (97%) rename src/mainboard/intel/dg41wv/{romstage.c => early_init.c} (94%) rename src/mainboard/intel/dg43gt/{romstage.c => early_init.c} (94%) rename src/mainboard/lenovo/thinkcentre_a58/{romstage.c => early_init.c} (93%) diff --git a/src/cpu/intel/socket_LGA775/Kconfig b/src/cpu/intel/socket_LGA775/Kconfig index 8b227bd7e4..8db932ce58 100644 --- a/src/cpu/intel/socket_LGA775/Kconfig +++ b/src/cpu/intel/socket_LGA775/Kconfig @@ -19,6 +19,10 @@ config DCACHE_RAM_SIZE hex default 0x4000 # 16 kB +config DCACHE_BSP_STACK_SIZE + hex + default 0x2000 + config DCACHE_RAM_BASE hex default 0xfeffc000 # 4GB - 16MB - DCACHE_RAM_SIZE diff --git a/src/cpu/intel/socket_LGA775/Makefile.inc b/src/cpu/intel/socket_LGA775/Makefile.inc index ceb084c900..a7984a9dfb 100644 --- a/src/cpu/intel/socket_LGA775/Makefile.inc +++ b/src/cpu/intel/socket_LGA775/Makefile.inc @@ -13,7 +13,14 @@ subdirs-y += ../microcode subdirs-y += ../hyperthreading subdirs-y += ../speedstep +ifneq ($(CONFIG_C_ENVIRONMENT_BOOTBLOCK),y) cpu_incs-y += $(src)/cpu/intel/car/p4-netburst/cache_as_ram.S +else +bootblock-y += ../car/p4-netburst/cache_as_ram.S +bootblock-y += ../car/bootblock.c +bootblock-y += ../../x86/early_reset.S +endif + postcar-y += ../car/p4-netburst/exit_car.S romstage-y += ../car/romstage.c diff --git a/src/mainboard/asrock/g41c-gs/Makefile.inc b/src/mainboard/asrock/g41c-gs/Makefile.inc index 82e72fbb81..ab352cb73d 100644 --- a/src/mainboard/asrock/g41c-gs/Makefile.inc +++ b/src/mainboard/asrock/g41c-gs/Makefile.inc @@ -1,4 +1,7 @@ ramstage-y += cstates.c romstage-y += variants/$(VARIANT_DIR)/gpio.c +bootblock-y += early_init.c +romstage-y += early_init.c + ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads diff --git a/src/mainboard/asrock/g41c-gs/romstage.c b/src/mainboard/asrock/g41c-gs/early_init.c similarity index 96% rename from src/mainboard/asrock/g41c-gs/romstage.c rename to src/mainboard/asrock/g41c-gs/early_init.c index 06e13eb652..c7c7b730a6 100644 --- a/src/mainboard/asrock/g41c-gs/romstage.c +++ b/src/mainboard/asrock/g41c-gs/early_init.c @@ -15,6 +15,7 @@ * GNU General Public License for more details. */ +#include #include #include #include @@ -27,7 +28,7 @@ #define SERIAL_DEV_R1 PNP_DEV(0x2e, W83627DHG_SP1) #define SUPERIO_DEV PNP_DEV(0x2e, 0) -void mb_lpc_setup(void) +void bootblock_mainboard_early_init(void) { /* Set GPIOs on superio, enable UART */ if (CONFIG(SUPERIO_NUVOTON_NCT6776)) { diff --git a/src/mainboard/asus/p5qc/Makefile.inc b/src/mainboard/asus/p5qc/Makefile.inc index 5c1d211ca7..88c57200d9 100644 --- a/src/mainboard/asus/p5qc/Makefile.inc +++ b/src/mainboard/asus/p5qc/Makefile.inc @@ -13,5 +13,8 @@ CONFIG_GPIO_C:=$(call strip_quotes, $(CONFIG_GPIO_C)) +bootblock-y += early_init.c +romstage-y += early_init.c + ramstage-y += cstates.c romstage-y += $(CONFIG_GPIO_C) diff --git a/src/mainboard/asus/p5qc/romstage.c b/src/mainboard/asus/p5qc/early_init.c similarity index 94% rename from src/mainboard/asus/p5qc/romstage.c rename to src/mainboard/asus/p5qc/early_init.c index 53aa176b38..cbc84ba101 100644 --- a/src/mainboard/asus/p5qc/romstage.c +++ b/src/mainboard/asus/p5qc/early_init.c @@ -14,6 +14,7 @@ * GNU General Public License for more details. */ +#include #include #include #include @@ -21,7 +22,7 @@ #define SERIAL_DEV PNP_DEV(0x2e, W83667HG_A_SP1) -void mb_lpc_setup(void) +void bootblock_mainboard_early_init(void) { /* TODO? */ RCBA32(RCBA_CG) = 0xbf7f001f; diff --git a/src/mainboard/asus/p5ql-em/Makefile.inc b/src/mainboard/asus/p5ql-em/Makefile.inc index 641e18f136..ba881b7eeb 100644 --- a/src/mainboard/asus/p5ql-em/Makefile.inc +++ b/src/mainboard/asus/p5ql-em/Makefile.inc @@ -11,6 +11,9 @@ # GNU General Public License for more details. # +bootblock-y += early_init.c + romstage-y += gpio.c +romstage-y += early_init.c ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads diff --git a/src/mainboard/asus/p5ql-em/romstage.c b/src/mainboard/asus/p5ql-em/early_init.c similarity index 97% rename from src/mainboard/asus/p5ql-em/romstage.c rename to src/mainboard/asus/p5ql-em/early_init.c index fa22a645d4..38038012f7 100644 --- a/src/mainboard/asus/p5ql-em/romstage.c +++ b/src/mainboard/asus/p5ql-em/early_init.c @@ -12,6 +12,7 @@ * GNU General Public License for more details. */ +#include #include #include #include @@ -24,7 +25,7 @@ #define SERIAL_DEV PNP_DEV(0x2e, W83627DHG_SP1) #define GPIO_DEV PNP_DEV(0x2e, W83627DHG_GPIO2345_V) -void mb_lpc_setup(void) +void bootblock_mainboard_early_init(void) { winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); } diff --git a/src/mainboard/asus/p5qpl-am/Makefile.inc b/src/mainboard/asus/p5qpl-am/Makefile.inc index 82e72fbb81..ab352cb73d 100644 --- a/src/mainboard/asus/p5qpl-am/Makefile.inc +++ b/src/mainboard/asus/p5qpl-am/Makefile.inc @@ -1,4 +1,7 @@ ramstage-y += cstates.c romstage-y += variants/$(VARIANT_DIR)/gpio.c +bootblock-y += early_init.c +romstage-y += early_init.c + ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads diff --git a/src/mainboard/asus/p5qpl-am/romstage.c b/src/mainboard/asus/p5qpl-am/early_init.c similarity index 98% rename from src/mainboard/asus/p5qpl-am/romstage.c rename to src/mainboard/asus/p5qpl-am/early_init.c index ad16c0f72a..5987033a09 100644 --- a/src/mainboard/asus/p5qpl-am/romstage.c +++ b/src/mainboard/asus/p5qpl-am/early_init.c @@ -15,6 +15,7 @@ * GNU General Public License for more details. */ +#include #include #include #include @@ -27,7 +28,7 @@ #define SERIAL_DEV PNP_DEV(0x2e, W83627DHG_SP1) #define GPIO_DEV PNP_DEV(0x2e, W83627DHG_GPIO2345_V) -void mb_lpc_setup(void) +void bootblock_mainboard_early_init(void) { winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); } diff --git a/src/mainboard/foxconn/g41s-k/Makefile.inc b/src/mainboard/foxconn/g41s-k/Makefile.inc index ca8de4d597..161c623eaa 100644 --- a/src/mainboard/foxconn/g41s-k/Makefile.inc +++ b/src/mainboard/foxconn/g41s-k/Makefile.inc @@ -1,6 +1,9 @@ ramstage-y += cstates.c romstage-y += gpio.c +bootblock-y += early_init.c +romstage-y += early_init.c + ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += variants/$(VARIANT_DIR)/gma-mainboard.ads CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/variants/$(VARIANT_DIR)/ diff --git a/src/mainboard/foxconn/g41s-k/romstage.c b/src/mainboard/foxconn/g41s-k/early_init.c similarity index 96% rename from src/mainboard/foxconn/g41s-k/romstage.c rename to src/mainboard/foxconn/g41s-k/early_init.c index b4bd77d78b..454b1ea0b0 100644 --- a/src/mainboard/foxconn/g41s-k/romstage.c +++ b/src/mainboard/foxconn/g41s-k/early_init.c @@ -16,6 +16,7 @@ * GNU General Public License for more details. */ +#include #include #include #include @@ -24,7 +25,7 @@ #define SERIAL_DEV PNP_DEV(0x2e, IT8720F_SP1) #define GPIO_DEV PNP_DEV(0x2e, IT8720F_GPIO) -void mb_lpc_setup(void) +void bootblock_mainboard_early_init(void) { /* Set up GPIOs on Super I/O. */ ite_reg_write(GPIO_DEV, 0x25, 0x01); diff --git a/src/mainboard/gigabyte/ga-g41m-es2l/Makefile.inc b/src/mainboard/gigabyte/ga-g41m-es2l/Makefile.inc index 0786d6fca5..4100476891 100644 --- a/src/mainboard/gigabyte/ga-g41m-es2l/Makefile.inc +++ b/src/mainboard/gigabyte/ga-g41m-es2l/Makefile.inc @@ -1,4 +1,7 @@ ramstage-y += cstates.c romstage-y += gpio.c +bootblock-y += early_init.c +romstage-y += early_init.c + ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads diff --git a/src/mainboard/gigabyte/ga-g41m-es2l/romstage.c b/src/mainboard/gigabyte/ga-g41m-es2l/early_init.c similarity index 97% rename from src/mainboard/gigabyte/ga-g41m-es2l/romstage.c rename to src/mainboard/gigabyte/ga-g41m-es2l/early_init.c index bde4f33bef..4540d4e03d 100644 --- a/src/mainboard/gigabyte/ga-g41m-es2l/romstage.c +++ b/src/mainboard/gigabyte/ga-g41m-es2l/early_init.c @@ -14,6 +14,7 @@ * GNU General Public License for more details. */ +#include #include #include #include @@ -29,7 +30,7 @@ * We should use standard gpio.h eventually */ -void mb_lpc_setup(void) +void bootblock_mainboard_early_init(void) { pci_devfn_t dev; diff --git a/src/mainboard/intel/dg41wv/Makefile.inc b/src/mainboard/intel/dg41wv/Makefile.inc index 0786d6fca5..4100476891 100644 --- a/src/mainboard/intel/dg41wv/Makefile.inc +++ b/src/mainboard/intel/dg41wv/Makefile.inc @@ -1,4 +1,7 @@ ramstage-y += cstates.c romstage-y += gpio.c +bootblock-y += early_init.c +romstage-y += early_init.c + ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads diff --git a/src/mainboard/intel/dg41wv/romstage.c b/src/mainboard/intel/dg41wv/early_init.c similarity index 94% rename from src/mainboard/intel/dg41wv/romstage.c rename to src/mainboard/intel/dg41wv/early_init.c index ff018af5f6..3cb40955d0 100644 --- a/src/mainboard/intel/dg41wv/romstage.c +++ b/src/mainboard/intel/dg41wv/early_init.c @@ -15,6 +15,7 @@ * GNU General Public License for more details. */ +#include #include #include #include @@ -23,7 +24,7 @@ #define SERIAL_DEV PNP_DEV(0x2e, W83627DHG_SP1) -void mb_lpc_setup(void) +void bootblock_mainboard_early_init(void) { /* Set GPIOs on superio, enable UART */ pnp_enter_ext_func_mode(SERIAL_DEV); diff --git a/src/mainboard/intel/dg43gt/Makefile.inc b/src/mainboard/intel/dg43gt/Makefile.inc index 6b3d94a037..f89d1302e3 100644 --- a/src/mainboard/intel/dg43gt/Makefile.inc +++ b/src/mainboard/intel/dg43gt/Makefile.inc @@ -14,4 +14,7 @@ ramstage-y += cstates.c romstage-y += gpio.c +bootblock-y += early_init.c +romstage-y += early_init.c + ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads diff --git a/src/mainboard/intel/dg43gt/romstage.c b/src/mainboard/intel/dg43gt/early_init.c similarity index 94% rename from src/mainboard/intel/dg43gt/romstage.c rename to src/mainboard/intel/dg43gt/early_init.c index 71fd87ad74..8457707ba1 100644 --- a/src/mainboard/intel/dg43gt/romstage.c +++ b/src/mainboard/intel/dg43gt/early_init.c @@ -14,6 +14,7 @@ * GNU General Public License for more details. */ +#include #include #include #include @@ -21,7 +22,7 @@ #define SERIAL_DEV PNP_DEV(0x2e, W83627DHG_SP1) -void mb_lpc_setup(void) +void bootblock_mainboard_early_init(void) { RCBA32(0x3410) = 0x00060464; RCBA32(RCBA_BUC) &= ~BUC_LAND; diff --git a/src/mainboard/lenovo/thinkcentre_a58/Makefile.inc b/src/mainboard/lenovo/thinkcentre_a58/Makefile.inc index 0786d6fca5..4100476891 100644 --- a/src/mainboard/lenovo/thinkcentre_a58/Makefile.inc +++ b/src/mainboard/lenovo/thinkcentre_a58/Makefile.inc @@ -1,4 +1,7 @@ ramstage-y += cstates.c romstage-y += gpio.c +bootblock-y += early_init.c +romstage-y += early_init.c + ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads diff --git a/src/mainboard/lenovo/thinkcentre_a58/romstage.c b/src/mainboard/lenovo/thinkcentre_a58/early_init.c similarity index 93% rename from src/mainboard/lenovo/thinkcentre_a58/romstage.c rename to src/mainboard/lenovo/thinkcentre_a58/early_init.c index 5594cbdda6..a8f6443948 100644 --- a/src/mainboard/lenovo/thinkcentre_a58/romstage.c +++ b/src/mainboard/lenovo/thinkcentre_a58/early_init.c @@ -15,12 +15,13 @@ * GNU General Public License for more details. */ +#include #include #include #define SERIAL_DEV PNP_DEV(0x2e, SMSCSUPERIO_SP1) -void mb_lpc_setup(void) +void bootblock_mainboard_early_init(void) { smscsuperio_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); } diff --git a/src/northbridge/intel/x4x/Kconfig b/src/northbridge/intel/x4x/Kconfig index 8f002c6a8f..2a54e2495e 100644 --- a/src/northbridge/intel/x4x/Kconfig +++ b/src/northbridge/intel/x4x/Kconfig @@ -26,15 +26,12 @@ config NORTHBRIDGE_SPECIFIC_OPTIONS # dummy select INTEL_GMA_ACPI select CACHE_MRC_SETTINGS select PARALLEL_MP + select C_ENVIRONMENT_BOOTBLOCK config CBFS_SIZE hex default 0x100000 if !SOUTHBRIDGE_INTEL_I82801GX -config BOOTBLOCK_NORTHBRIDGE_INIT - string - default "northbridge/intel/x4x/bootblock.c" - config VGA_BIOS_ID string default "8086,2e32" diff --git a/src/northbridge/intel/x4x/Makefile.inc b/src/northbridge/intel/x4x/Makefile.inc index 79a03cb77e..cde7121f93 100644 --- a/src/northbridge/intel/x4x/Makefile.inc +++ b/src/northbridge/intel/x4x/Makefile.inc @@ -16,6 +16,8 @@ ifeq ($(CONFIG_NORTHBRIDGE_INTEL_X4X),y) +bootblock-y += bootblock.c + romstage-y += early_init.c romstage-y += raminit.c romstage-y += raminit_ddr23.c diff --git a/src/northbridge/intel/x4x/bootblock.c b/src/northbridge/intel/x4x/bootblock.c index e733287e93..64643dd79c 100644 --- a/src/northbridge/intel/x4x/bootblock.c +++ b/src/northbridge/intel/x4x/bootblock.c @@ -15,13 +15,11 @@ */ #include +#include +#include "x4x.h" #include "iomap.h" -/* Just re-define these instead of including x4x.h. It blows up romcc. */ -#define D0F0_PCIEXBAR_LO 0x60 -#define D0F0_PCIEXBAR_HI 0x64 - -static void bootblock_northbridge_init(void) +void bootblock_early_northbridge_init(void) { uint32_t reg32; diff --git a/src/northbridge/intel/x4x/romstage.c b/src/northbridge/intel/x4x/romstage.c index c3a503643f..eae87f3674 100644 --- a/src/northbridge/intel/x4x/romstage.c +++ b/src/northbridge/intel/x4x/romstage.c @@ -34,16 +34,6 @@ void mainboard_romstage_entry(void) u8 boot_path = 0; u8 s3_resume; -#if CONFIG(SOUTHBRIDGE_INTEL_I82801JX) - i82801jx_lpc_setup(); -#elif CONFIG(SOUTHBRIDGE_INTEL_I82801GX) - i82801gx_lpc_setup(); -#endif - - mb_lpc_setup(); - - console_init(); - enable_smbus(); #if CONFIG(SOUTHBRIDGE_INTEL_I82801JX) diff --git a/src/northbridge/intel/x4x/x4x.h b/src/northbridge/intel/x4x/x4x.h index e4a6c215d8..aaaa28aeac 100644 --- a/src/northbridge/intel/x4x/x4x.h +++ b/src/northbridge/intel/x4x/x4x.h @@ -373,7 +373,6 @@ enum ddr2_signals { void x4x_early_init(void); void x4x_late_init(int s3resume); -void mb_lpc_setup(void); void mb_get_spd_map(u8 spd_map[4]); void mb_pre_raminit_setup(int s3_resume); u32 decode_igd_memory_size(u32 gms); diff --git a/src/southbridge/intel/i82801jx/Kconfig b/src/southbridge/intel/i82801jx/Kconfig index eeb843e910..7f44fcfc1d 100644 --- a/src/southbridge/intel/i82801jx/Kconfig +++ b/src/southbridge/intel/i82801jx/Kconfig @@ -51,9 +51,4 @@ config INTEL_DESCRIPTOR_MODE_REQUIRED config HPET_MIN_TICKS hex default 0x80 - -config BOOTBLOCK_SOUTHBRIDGE_INIT - string - default "southbridge/intel/i82801jx/bootblock.c" - endif diff --git a/src/southbridge/intel/i82801jx/Makefile.inc b/src/southbridge/intel/i82801jx/Makefile.inc index 30ed351970..1527b8adb0 100644 --- a/src/southbridge/intel/i82801jx/Makefile.inc +++ b/src/southbridge/intel/i82801jx/Makefile.inc @@ -16,6 +16,9 @@ ifeq ($(CONFIG_SOUTHBRIDGE_INTEL_I82801JX),y) +bootblock-y += bootblock.c +bootblock-y += early_init.c + ramstage-y += i82801jx.c ramstage-y += pci.c ramstage-y += lpc.c diff --git a/src/southbridge/intel/i82801jx/bootblock.c b/src/southbridge/intel/i82801jx/bootblock.c index 01faef34af..b6016793c2 100644 --- a/src/southbridge/intel/i82801jx/bootblock.c +++ b/src/southbridge/intel/i82801jx/bootblock.c @@ -14,6 +14,7 @@ */ #include +#include #include "i82801jx.h" static void enable_spi_prefetch(void) @@ -29,14 +30,14 @@ static void enable_spi_prefetch(void) pci_write_config8(dev, 0xdc, reg8); } -static void bootblock_southbridge_init(void) +void bootblock_early_southbridge_init(void) { enable_spi_prefetch(); - /* Enable RCBA */ - pci_write_config32(PCI_DEV(0, 0x1f, 0), RCBA, - (uintptr_t)DEFAULT_RCBA | 1); + i82801jx_setup_bars(); /* Enable upper 128bytes of CMOS. */ RCBA32(0x3400) = (1 << 2); + + i82801jx_lpc_setup(); } diff --git a/src/southbridge/intel/i82801jx/early_init.c b/src/southbridge/intel/i82801jx/early_init.c index 469073240e..1afc6b365f 100644 --- a/src/southbridge/intel/i82801jx/early_init.c +++ b/src/southbridge/intel/i82801jx/early_init.c @@ -56,7 +56,7 @@ void i82801jx_lpc_setup(void) pci_write_config32(d31f0, D31F0_GEN4_DEC, config->gen4_dec); } -static void i82801jx_setup_bars(void) +void i82801jx_setup_bars(void) { const pci_devfn_t d31f0 = PCI_DEV(0, 0x1f, 0); diff --git a/src/southbridge/intel/i82801jx/i82801jx.h b/src/southbridge/intel/i82801jx/i82801jx.h index d406d1d631..26a99f42f7 100644 --- a/src/southbridge/intel/i82801jx/i82801jx.h +++ b/src/southbridge/intel/i82801jx/i82801jx.h @@ -235,6 +235,7 @@ int smbus_block_write(unsigned int device, unsigned int cmd, u8 bytes, const u8 *buf); #endif void i82801jx_lpc_setup(void); +void i82801jx_setup_bars(void); void i82801jx_early_init(void); #endif From 5e8afce88f3bd4914be0b472559486c59fe58f41 Mon Sep 17 00:00:00 2001 From: Nico Huber Date: Sat, 12 Oct 2019 15:16:33 +0200 Subject: [PATCH 0201/1242] soc/intel: Implement PCIe RP devicetree update based on LCAP MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Most of the current implementations for FSP-based platforms make (sometimes wrong) assumptions how FSP reorders root ports and what is specified in the devicetree. We don't have to make assumptions though, and can read the root-port number from the PCIe link capapilities (LCAP) instead. This is also what we do in ASL code for years already. This new implementation acts solely on information read from the PCI config space. In a first round, we scan all possible DEVFNs and store which root port has that DEVFN now. Then, we walk through the devicetree that still only knows devices that were originally mentioned in `devicetree.cb`, update device paths and unlink vanished devices. To be most compatible, we work with the following constraints: o Use only standard PCI config registers. o Most notable, don't try to read the registers that configure the function numbers. FSP has undocumented ways to block access to non-standard registers. o Don't make assumptions what function is assigned to hidden devices. The following assumptions were made, though: o The absolute root-port numbering as documented in datasheets matches what is read from LCAP. o This numbering doesn't contain any gaps. o Original root-port function numbers below a PCI device start at function zero and also don't contain any gaps. Change-Id: Ib17d2b6fd34608603db3936d638bdf5acb46d717 Signed-off-by: Nico Huber Reviewed-on: https://review.coreboot.org/c/coreboot/+/35985 Reviewed-by: Aaron Durbin Reviewed-by: Michael Niewöhner Reviewed-by: Patrick Rudolph Tested-by: build bot (Jenkins) --- src/include/device/pci_def.h | 1 + .../block/include/intelblocks/pcie_rp.h | 50 +++++ src/soc/intel/common/block/pcie/Makefile.inc | 1 + src/soc/intel/common/block/pcie/pcie_rp.c | 177 ++++++++++++++++++ 4 files changed, 229 insertions(+) create mode 100644 src/soc/intel/common/block/include/intelblocks/pcie_rp.h create mode 100644 src/soc/intel/common/block/pcie/pcie_rp.c diff --git a/src/include/device/pci_def.h b/src/include/device/pci_def.h index c8b86d5b44..d906445157 100644 --- a/src/include/device/pci_def.h +++ b/src/include/device/pci_def.h @@ -426,6 +426,7 @@ #define PCI_EXP_LNKCAP_L0SEL 0x7000 /* L0s Exit Latency */ #define PCI_EXP_LNKCAP_L1EL 0x38000 /* L1 Exit Latency */ #define PCI_EXP_CLK_PM 0x40000 /* Clock Power Management */ +#define PCI_EXP_LNKCAP_PORT 0xff000000 /* Port Number */ #define PCI_EXP_LNKCTL 16 /* Link Control */ #define PCI_EXP_LNKCTL_RL 0x20 /* Retrain Link */ #define PCI_EXP_LNKCTL_CCC 0x40 /* Common Clock COnfiguration */ diff --git a/src/soc/intel/common/block/include/intelblocks/pcie_rp.h b/src/soc/intel/common/block/include/intelblocks/pcie_rp.h new file mode 100644 index 0000000000..52fde28310 --- /dev/null +++ b/src/soc/intel/common/block/include/intelblocks/pcie_rp.h @@ -0,0 +1,50 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef SOC_INTEL_COMMON_BLOCK_PCIE_RP_H +#define SOC_INTEL_COMMON_BLOCK_PCIE_RP_H + +#include + +/* + * The PCIe Root Ports usually come in groups of up to 8 PCI-device + * functions. + * + * `slot` is the PCI device/slot number of such a group. + * `count` is the number of functions within the group. It is assumed that + * the first group includes the RPs 1 to the first group's `count` and that + * adjacent groups follow without gaps in the numbering. + */ +struct pcie_rp_group { + unsigned int slot; + unsigned int count; +}; + +/* + * Update PCI paths of the root ports in the devicetree. + * + * Depending on the board layout and physical presence of downstream + * devices, individual root-port functions can be hidden and reordered. + * If we have device nodes for root ports in the static `devicetree.cb`, + * we need to update their PCI paths, so the nodes still control the + * correct root port. Device nodes for disabled root ports will be + * unlinked from the bus, to not interfere with PCI enumeration. + * + * Call this once, after root ports have been reordered, but before PCI + * enumeration. + * + * `groups` points to a list of groups terminated by an entry with `count == 0`. + */ +void pcie_rp_update_devicetree(const struct pcie_rp_group *groups); + +#endif /* SOC_INTEL_COMMON_BLOCK_PCIE_RP_H */ diff --git a/src/soc/intel/common/block/pcie/Makefile.inc b/src/soc/intel/common/block/pcie/Makefile.inc index ac311a7abd..0cded9dce7 100644 --- a/src/soc/intel/common/block/pcie/Makefile.inc +++ b/src/soc/intel/common/block/pcie/Makefile.inc @@ -1 +1,2 @@ ramstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_PCIE) += pcie.c +ramstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_PCIE) += pcie_rp.c diff --git a/src/soc/intel/common/block/pcie/pcie_rp.c b/src/soc/intel/common/block/pcie/pcie_rp.c new file mode 100644 index 0000000000..96f92f0861 --- /dev/null +++ b/src/soc/intel/common/block/pcie/pcie_rp.c @@ -0,0 +1,177 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 Nico Huber + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include + +#include +#include +#include +#include +#include +#include +#include + +static int pcie_rp_original_idx( + const struct pcie_rp_group *const group, + const unsigned int offset, + const pci_devfn_t dev) +{ + const uint16_t clist = pci_s_find_capability(dev, PCI_CAP_ID_PCIE); + if (clist == 0) { + printk(BIOS_WARNING, + "%s: Can't find PCIe capapilities for PCI: 00:%02x.%x, ignoring.\n", + __func__, group->slot, PCI_FUNC(PCI_DEV2DEVFN(dev))); + return -1; + } + + const uint16_t xcap = pci_s_read_config16(dev, clist + PCI_EXP_FLAGS); + if ((xcap & PCI_EXP_FLAGS_TYPE) >> 4 != PCI_EXP_TYPE_ROOT_PORT) { + printk(BIOS_WARNING, "%s: Non root-port found at PCI: 00:%02x.%x, ignoring.\n", + __func__, group->slot, PCI_FUNC(PCI_DEV2DEVFN(dev))); + return -1; + } + + const uint32_t lcap = pci_s_read_config32(dev, clist + PCI_EXP_LNKCAP); + /* Read 1-based absolute port number. This reflects the numbering + scheme that Intel uses in their documentation and what we use + as index (0-based, though) in our mapping. */ + const unsigned int port_num = (lcap & PCI_EXP_LNKCAP_PORT) >> 24; + + /* `port_num` is 1-based, `offset` is 0-based. */ + if (port_num <= offset || port_num > offset + group->count) { + printk(BIOS_WARNING, "%s: Unexpected root-port number '%u'" + " at PCI: 00:%02x.%x, ignoring.\n", + __func__, port_num, group->slot, PCI_FUNC(PCI_DEV2DEVFN(dev))); + return -1; + } + + return port_num - 1; +} + +/* Scan actual PCI config space to reconstruct current mapping */ +static void pcie_rp_scan_groups(int mapping[], const struct pcie_rp_group *const groups) +{ + unsigned int offset = 0; + const struct pcie_rp_group *group; + for (group = groups; group->count; ++group) { + unsigned int fn; + for (fn = 0; fn < group->count; ++fn) { + const pci_devfn_t dev = PCI_DEV(0, group->slot, fn); + const uint16_t did = pci_s_read_config16(dev, PCI_DEVICE_ID); + if (did == 0xffff) { + if (fn == 0) + break; + continue; + } + + const int rp_idx = pcie_rp_original_idx(group, offset, dev); + if (rp_idx < 0) + continue; + if (mapping[rp_idx] != -1) { + printk(BIOS_WARNING, "%s: Root Port #%u reported by PCI: " + "00:%02x.%x already reported by PCI: 00:%02x.%x!\n", + __func__, rp_idx + 1, group->slot, fn, + group->slot, mapping[rp_idx]); + continue; + } + + printk(BIOS_INFO, "Found PCIe Root Port #%u at PCI: 00:%02x.%x.\n", + rp_idx + 1, group->slot, fn); + mapping[rp_idx] = fn; + } + offset += group->count; + } +} + +/* Returns `true` if the device should be unlinked. */ +static bool pcie_rp_update_dev( + struct device *const dev, + const struct pcie_rp_group *const groups, + const int mapping[]) +{ + if (dev->path.type != DEVICE_PATH_PCI) + return false; + + /* Find matching group and offset. */ + unsigned int offset = 0; + const struct pcie_rp_group *group; + for (group = groups; group->count; ++group) { + if (PCI_SLOT(dev->path.pci.devfn) == group->slot && + PCI_FUNC(dev->path.pci.devfn) < group->count) + break; + offset += group->count; + } + if (!group->count) + return false; + + /* Now update based on what we know. */ + const int rp_idx = offset + PCI_FUNC(dev->path.pci.devfn); + const int new_fn = mapping[rp_idx]; + if (new_fn < 0) { + if (dev->enabled) { + printk(BIOS_NOTICE, "%s: Couldn't find PCIe Root Port #%u " + "(originally %s) which was enabled in devicetree, removing.\n", + __func__, rp_idx + 1, dev_path(dev)); + } + return true; + } else if (PCI_FUNC(dev->path.pci.devfn) != new_fn) { + printk(BIOS_INFO, + "Remapping PCIe Root Port #%u from %s to new function number %u.\n", + rp_idx + 1, dev_path(dev), new_fn); + dev->path.pci.devfn = PCI_DEVFN(PCI_SLOT(dev->path.pci.devfn), new_fn); + } + return false; +} + +void pcie_rp_update_devicetree(const struct pcie_rp_group *const groups) +{ + /* Maps absolute root-port numbers to function numbers. + Negative if disabled, new function number otherwise. */ + int mapping[CONFIG_MAX_ROOT_PORTS]; + unsigned int offset, i; + + struct bus *const root = pci_root_bus(); + if (!root) + return; + + offset = 0; + const struct pcie_rp_group *group; + for (group = groups; group->count; ++group) + offset += group->count; + + if (offset > ARRAY_SIZE(mapping)) { + printk(BIOS_ERR, "%s: Error: Group exceeds CONFIG_MAX_ROOT_PORTS.\n", __func__); + return; + } + + /* Assume everything we don't encounter later is disabled */ + for (i = 0; i < ARRAY_SIZE(mapping); ++i) + mapping[i] = -1; + + pcie_rp_scan_groups(mapping, groups); + + struct device *dev; + struct device **link = &root->children; + for (dev = *link; dev; dev = *link) { + if (pcie_rp_update_dev(dev, groups, mapping)) { + /* Unlink vanished device. */ + *link = dev->sibling; + dev->sibling = NULL; + continue; + } + + link = &dev->sibling; + } +} From ad91b18c6418d2ed862e54cc26019172561200af Mon Sep 17 00:00:00 2001 From: Nico Huber Date: Sat, 12 Oct 2019 15:16:33 +0200 Subject: [PATCH 0202/1242] intel/skylake: Use new PCIe RP devicetree update MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The old code stumbled when the whole first group of root ports was disabled and also made the (sometimes wrong) assumption that FSP would only hide function 0 if we explicitly told it to disable it. Change-Id: Ia6938ca6929c6d9d0293c4f0f0421e38bf53fb55 Signed-off-by: Nico Huber Reviewed-on: https://review.coreboot.org/c/coreboot/+/36702 Reviewed-by: Michael Niewöhner Reviewed-by: Patrick Rudolph Tested-by: build bot (Jenkins) --- src/soc/intel/skylake/chip.c | 139 +++++------------------------------ 1 file changed, 17 insertions(+), 122 deletions(-) diff --git a/src/soc/intel/skylake/chip.c b/src/soc/intel/skylake/chip.c index 7987f46954..1e0803c67b 100644 --- a/src/soc/intel/skylake/chip.c +++ b/src/soc/intel/skylake/chip.c @@ -15,10 +15,8 @@ #include #include -#include #include #include -#include #include #include #include @@ -27,6 +25,7 @@ #include #include #include +#include #include #include #include @@ -44,129 +43,22 @@ #include "chip.h" -struct pcie_entry { - unsigned int devfn; - unsigned int func_count; +static const struct pcie_rp_group pch_lp_rp_groups[] = { + { .slot = PCH_DEV_SLOT_PCIE, .count = 8 }, + { .slot = PCH_DEV_SLOT_PCIE_1, .count = 4 }, + { 0 } }; -/* - * According to table 2-2 in doc#546717: - * PCI bus[function] ID - * D28:[F0 - F7] 0xA110 - 0xA117 - * D29:[F0 - F7] 0xA118 - 0xA11F - * D27:[F0 - F3] 0xA167 - 0xA16A - */ -static const struct pcie_entry pcie_table_skl_pch_h[] = { - {PCH_DEVFN_PCIE1, 8}, - {PCH_DEVFN_PCIE9, 8}, - {PCH_DEVFN_PCIE17, 4}, +static const struct pcie_rp_group pch_h_rp_groups[] = { + { .slot = PCH_DEV_SLOT_PCIE, .count = 8 }, + { .slot = PCH_DEV_SLOT_PCIE_1, .count = 8 }, + /* Sunrise Point PCH-H actually only has 4 ports in the + third group. But that would require a runtime check + and probing 4 non-existent ports shouldn't hurt. */ + { .slot = PCH_DEV_SLOT_PCIE_2, .count = 8 }, + { 0 } }; -/* - * According to table 2-2 in doc#564464: - * PCI bus[function] ID - * D28:[F0 - F7] 0xA290 - 0xA297 - * D29:[F0 - F7] 0xA298 - 0xA29F - * D27:[F0 - F7] 0xA2E7 - 0xA2EE - */ -static const struct pcie_entry pcie_table_kbl_pch_h[] = { - {PCH_DEVFN_PCIE1, 8}, - {PCH_DEVFN_PCIE9, 8}, - {PCH_DEVFN_PCIE17, 8}, -}; - -/* - * According to table 2-2 in doc#567995/545659: - * PCI bus[function] ID - * D28:[F0 - F7] 0x9D10 - 0x9D17 - * D29:[F0 - F3] 0x9D18 - 0x9D1B - */ -static const struct pcie_entry pcie_table_skl_pch_lp[] = { - {PCH_DEVFN_PCIE1, 8}, - {PCH_DEVFN_PCIE9, 4}, -}; - -/* - * If the PCIe root port at function 0 is disabled, - * the PCIe root ports might be coalesced after FSP silicon init. - * The below function will swap the devfn of the first enabled device - * in devicetree and function 0 resides a pci device - * so that it won't confuse coreboot. - */ -static void pcie_update_device_tree(const struct pcie_entry *pcie_rp_group, - size_t pci_groups) -{ - struct device *func0; - unsigned int devfn, devfn0; - int i, group; - unsigned int inc = PCI_DEVFN(0, 1); - - for (group = 0; group < pci_groups; group++) { - devfn0 = pcie_rp_group[group].devfn; - func0 = pcidev_path_on_root(devfn0); - if (func0 == NULL) - continue; - - /* No more functions if function 0 is disabled. */ - if (pci_read_config32(func0, PCI_VENDOR_ID) == 0xffffffff) - continue; - - devfn = devfn0 + inc; - - /* - * Increase function by 1. - * Then find first enabled device to replace func0 - * as that port was move to func0. - */ - for (i = 1; i < pcie_rp_group[group].func_count; - i++, devfn += inc) { - struct device *dev = pcidev_path_on_root(devfn); - if (dev == NULL || !dev->enabled) - continue; - - /* - * Found the first enabled device in - * a given dev number. - */ - printk(BIOS_INFO, "PCI func %d was swapped" - " to func 0.\n", i); - func0->path.pci.devfn = dev->path.pci.devfn; - dev->path.pci.devfn = devfn0; - break; - } - } -} - -static void pcie_override_devicetree_after_silicon_init(void) -{ - uint16_t id, id_mask; - - id = pci_read_config16(PCH_DEV_PCIE1, PCI_DEVICE_ID); - /* - * We may read an ID other than func 0 after FSP-S. - * Strip out 4 least significant bits. - */ - id_mask = id & ~0xf; - printk(BIOS_INFO, "Override DT after FSP-S, PCH is "); - if (id_mask == (PCI_DEVICE_ID_INTEL_SPT_LP_PCIE_RP1 & ~0xf)) { - printk(BIOS_INFO, "KBL/SKL PCH-LP SKU\n"); - pcie_update_device_tree(&pcie_table_skl_pch_lp[0], - ARRAY_SIZE(pcie_table_skl_pch_lp)); - } else if (id_mask == (PCI_DEVICE_ID_INTEL_KBP_H_PCIE_RP1 & ~0xf)) { - printk(BIOS_INFO, "KBL PCH-H SKU\n"); - pcie_update_device_tree(&pcie_table_kbl_pch_h[0], - ARRAY_SIZE(pcie_table_kbl_pch_h)); - } else if (id_mask == (PCI_DEVICE_ID_INTEL_SPT_H_PCIE_RP1 & ~0xf)) { - printk(BIOS_INFO, "SKL PCH-H SKU\n"); - pcie_update_device_tree(&pcie_table_skl_pch_h[0], - ARRAY_SIZE(pcie_table_skl_pch_h)); - } else { - printk(BIOS_ERR, "[BUG] PCIE Root Port id 0x%x" - " is not found\n", id); - return; - } -} - void soc_init_pre_device(void *chip_info) { /* Snapshot the current GPIO IRQ polarities. FSP is setting a @@ -187,7 +79,10 @@ void soc_init_pre_device(void *chip_info) itss_restore_irq_polarities(GPIO_IRQ_START, GPIO_IRQ_END); /* swap enabled PCI ports in device tree if needed */ - pcie_override_devicetree_after_silicon_init(); + if (CONFIG(SKYLAKE_SOC_PCH_H)) + pcie_rp_update_devicetree(pch_h_rp_groups); + else + pcie_rp_update_devicetree(pch_lp_rp_groups); } void soc_fsp_load(void) From 751c496c742ad7ea0c35b138cc3bf02d6856e4b3 Mon Sep 17 00:00:00 2001 From: Patrick Georgi Date: Fri, 15 Nov 2019 11:36:12 +0100 Subject: [PATCH 0203/1242] vboot: update comment The comment in the source referred to an earlier approach, so update it to match current reality. Change-Id: I9a23ec0a719fb623cfd465c397ef7ef16550b93c Signed-off-by: Patrick Georgi Reviewed-on: https://review.coreboot.org/c/coreboot/+/36862 Tested-by: build bot (Jenkins) Reviewed-by: Joel Kitching --- src/security/vboot/misc.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/security/vboot/misc.h b/src/security/vboot/misc.h index 455773cc7c..812bbe7267 100644 --- a/src/security/vboot/misc.h +++ b/src/security/vboot/misc.h @@ -32,7 +32,7 @@ struct selected_region { * Stores vboot-related information. selected_region is used by verstage to * store the location of the selected slot. buffer is used by vboot to store * its work buffer. vb2_context is contained within this work buffer, and is - * accessible via vboot_init_context() and vboot_get_context() (see below). + * accessible via vboot_get_context() declared below. * Keep the struct CPU architecture agnostic as it crosses stage boundaries. */ struct vboot_working_data { From c50847e51ed0351d262b844919d67bee6372b25a Mon Sep 17 00:00:00 2001 From: Joel Kitching Date: Fri, 15 Nov 2019 18:58:54 +0800 Subject: [PATCH 0204/1242] vboot: remove vboot_possibly_executed function vboot_possibly_executed previously provided some better compile-time code elimination, before CB:32716 made vboot_logic_executed capable of that directly. BUG=b:124141368, TEST=make clean && make test-abuild BRANCH=none Change-Id: If5ca8f03c51e1ced20e1215b1cfdde54da3d001f Signed-off-by: Joel Kitching Reviewed-on: https://review.coreboot.org/c/coreboot/+/36863 Reviewed-by: Patrick Georgi Reviewed-by: Aaron Durbin Tested-by: build bot (Jenkins) --- src/security/vboot/bootmode.c | 24 +----------------------- 1 file changed, 1 insertion(+), 23 deletions(-) diff --git a/src/security/vboot/bootmode.c b/src/security/vboot/bootmode.c index bc89e732cf..0cab0c8559 100644 --- a/src/security/vboot/bootmode.c +++ b/src/security/vboot/bootmode.c @@ -64,27 +64,6 @@ static void vboot_clear_recovery_reason_vbnv(void *unused) BOOT_STATE_INIT_ENTRY(BS_DEV_INIT, BS_ON_EXIT, vboot_clear_recovery_reason_vbnv, NULL); -/* - * Returns 1 if vboot is being used and currently in a stage which might have - * already executed vboot verification. - */ -static int vboot_possibly_executed(void) -{ - if (CONFIG(VBOOT_STARTS_IN_BOOTBLOCK)) { - if (ENV_BOOTBLOCK && CONFIG(VBOOT_SEPARATE_VERSTAGE)) - return 0; - return 1; - } - - if (CONFIG(VBOOT_STARTS_IN_ROMSTAGE)) { - if (ENV_BOOTBLOCK) - return 0; - return 1; - } - - return 0; -} - /* * vb2_check_recovery_request looks up different components to identify if there * is a recovery request and returns appropriate reason code: @@ -113,8 +92,7 @@ int vboot_check_recovery_request(void) * Identify if vboot verification is already complete and no slot * was selected i.e. recovery path was requested. */ - if (vboot_possibly_executed() && vboot_logic_executed() && - !vboot_is_slot_selected()) + if (vboot_logic_executed() && !vboot_is_slot_selected()) return vboot_get_recovery_reason_shared_data(); return 0; From 46cc24d94e9a1a225d10637650f56ff2272ba3dc Mon Sep 17 00:00:00 2001 From: Wim Vervoorn Date: Thu, 14 Nov 2019 11:45:03 +0100 Subject: [PATCH 0205/1242] vendorcode/security/eltan: Allocate memory from bootmem to speed up hashing The verified_boot_check_cbfsfile() will now try to allocate a buffer from bootmem if the item in the list has the VERIFIED_BOOT_COPY_BLOCK attribute set. For large payloads this speeds up the hash operation. BUG=N/A TEST=build Change-Id: Ifa0c93632c59d05ae6d32f8785009a3c3568abc5 Signed-off-by: Wim Vervoorn Reviewed-on: https://review.coreboot.org/c/coreboot/+/36822 Tested-by: build bot (Jenkins) Reviewed-by: Frans Hendriks --- .../security/verified_boot/vboot_check.c | 32 +++++++++++++++---- 1 file changed, 26 insertions(+), 6 deletions(-) diff --git a/src/vendorcode/eltan/security/verified_boot/vboot_check.c b/src/vendorcode/eltan/security/verified_boot/vboot_check.c index 0633042539..9fb83707bf 100644 --- a/src/vendorcode/eltan/security/verified_boot/vboot_check.c +++ b/src/vendorcode/eltan/security/verified_boot/vboot_check.c @@ -14,6 +14,7 @@ * GNU General Public License for more details. */ #include +#include #include #include #include @@ -183,13 +184,32 @@ void verified_boot_check_cbfsfile(const char *name, uint32_t type, uint32_t hash start = cbfs_boot_map_with_leak(name, type & ~VERIFIED_BOOT_COPY_BLOCK, &size); if (start && size) { /* Speed up processing by copying the file content to memory first */ - if (!ENV_ROMSTAGE_OR_BEFORE && (type & VERIFIED_BOOT_COPY_BLOCK) && (buffer) && - (*buffer) && ((uint32_t) start > (uint32_t)(~(CONFIG_CBFS_SIZE-1)))) { + if (!ENV_ROMSTAGE_OR_BEFORE && (type & VERIFIED_BOOT_COPY_BLOCK)) { + + if ((buffer) && (*buffer) && (*filesize >= size) && + ((uint32_t) start > (uint32_t)(~(CONFIG_CBFS_SIZE-1)))) { + + /* Use the buffer passed in if possible */ printk(BIOS_DEBUG, "%s: move buffer to memory\n", __func__); - /* Move the file to a memory bufferof which we know it doesn't harm */ - memcpy(*buffer, start, size); - start = *buffer; - printk(BIOS_DEBUG, "%s: done\n", __func__); + /* Move the file to memory buffer passed in */ + memcpy(*buffer, start, size); + start = *buffer; + printk(BIOS_DEBUG, "%s: done\n", __func__); + + } else if (ENV_RAMSTAGE) { + /* Try to allocate a buffer from boot_mem */ + void *local_buffer = bootmem_allocate_buffer(size); + + if (local_buffer) { + + /* Use the allocated buffer */ + printk(BIOS_DEBUG, "%s: move file to memory\n", + __func__); + memcpy(local_buffer, start, size); + start = local_buffer; + printk(BIOS_DEBUG, "%s: done\n", __func__); + } + } } verified_boot_check_buffer(name, start, size, hash_index, pcr); } else { From e5ca52bbba584aa6b654383c06e1b5161f6738d9 Mon Sep 17 00:00:00 2001 From: Patrick Georgi Date: Fri, 15 Nov 2019 12:23:10 +0000 Subject: [PATCH 0206/1242] Update opensbi submodule to upstream master Updating from commit id e561c63: 2019-10-02 17:03:58 +0530 - (lib: Fix coldboot race condition observed on emulators/simulators) to commit id 215421c: 2019-11-11 16:40:34 -0800 - (lib: Remove date and time from init message) This brings in 13 new commits and allows reproducible builds with opensbi. Change-Id: I0fb9e0921b017822defa8b56df5a0f3e014d7f33 Signed-off-by: Patrick Georgi Reviewed-on: https://review.coreboot.org/c/coreboot/+/36866 Tested-by: build bot (Jenkins) Reviewed-by: Arthur Heymans --- 3rdparty/opensbi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/3rdparty/opensbi b/3rdparty/opensbi index e561c63036..215421ca61 160000 --- a/3rdparty/opensbi +++ b/3rdparty/opensbi @@ -1 +1 @@ -Subproject commit e561c6303639ed510183da25d3d54555a53371c9 +Subproject commit 215421ca610a64b8ec188c96ea8588ae2de41fb7 From 767de0aac753bb67f53d13c48207ade22b094a7e Mon Sep 17 00:00:00 2001 From: Arthur Heymans Date: Fri, 15 Nov 2019 19:19:53 +0100 Subject: [PATCH 0207/1242] sb/intel/i82801gx: Only include SPI code with SPI boot devices On devices lacking SPI boot devices there is a hefty timeout penalty on probing for flash chips and this code would not be useful anyway. Change-Id: I0bec11372ef54c1e1e611b81f7013932257f4ca6 Signed-off-by: Arthur Heymans Reviewed-on: https://review.coreboot.org/c/coreboot/+/36868 Reviewed-by: Nico Huber Reviewed-by: HAOUAS Elyes Tested-by: build bot (Jenkins) --- src/southbridge/intel/i82801gx/Kconfig | 2 +- src/southbridge/intel/i82801gx/lpc.c | 3 ++- 2 files changed, 3 insertions(+), 2 deletions(-) diff --git a/src/southbridge/intel/i82801gx/Kconfig b/src/southbridge/intel/i82801gx/Kconfig index 17ee4fcab3..bf9880ac27 100644 --- a/src/southbridge/intel/i82801gx/Kconfig +++ b/src/southbridge/intel/i82801gx/Kconfig @@ -23,7 +23,7 @@ config SOUTHBRIDGE_INTEL_I82801GX select COMMON_FADT select SOUTHBRIDGE_INTEL_COMMON_GPIO select SOUTHBRIDGE_INTEL_COMMON_SMBUS - select SOUTHBRIDGE_INTEL_COMMON_SPI + select SOUTHBRIDGE_INTEL_COMMON_SPI if BOOT_DEVICE_SPI_FLASH select SOUTHBRIDGE_INTEL_COMMON_PMCLIB select SOUTHBRIDGE_INTEL_COMMON_PMBASE select HAVE_INTEL_CHIPSET_LOCKDOWN diff --git a/src/southbridge/intel/i82801gx/lpc.c b/src/southbridge/intel/i82801gx/lpc.c index 34250d396f..0330af0060 100644 --- a/src/southbridge/intel/i82801gx/lpc.c +++ b/src/southbridge/intel/i82801gx/lpc.c @@ -616,7 +616,8 @@ static void lpc_final(struct device *dev) if (!CONFIG(INTEL_CHIPSET_LOCKDOWN)) return; - spi_finalize_ops(); + if (CONFIG(BOOT_DEVICE_SPI_FLASH)) + spi_finalize_ops(); /* Lock SPIBAR */ SPIBAR16(0) = SPIBAR16(0) | (1 << 15); From ba071cdbfbabe24a7e00bea23d0fcb084986fbfb Mon Sep 17 00:00:00 2001 From: Arthur Heymans Date: Fri, 15 Nov 2019 19:46:45 +0100 Subject: [PATCH 0208/1242] mb/{kontron/968lcd-m,roda/rk886ex}: select non-SPI These mainboard don't feature a SPI flash. The SPI init code will timeout on probing for a SPI flash which takes a lot of time. Not including all SPI drivers also lightens the uncompressed ramstage of about 17K or 7K compressed. Change-Id: Icc7bf62d56fc2ef38854402e658830b8d59c737f Signed-off-by: Arthur Heymans Reviewed-on: https://review.coreboot.org/c/coreboot/+/36870 Reviewed-by: Nico Huber Tested-by: build bot (Jenkins) --- src/mainboard/kontron/986lcd-m/Kconfig | 1 + src/mainboard/roda/rk886ex/Kconfig | 1 + 2 files changed, 2 insertions(+) diff --git a/src/mainboard/kontron/986lcd-m/Kconfig b/src/mainboard/kontron/986lcd-m/Kconfig index 9dadd55cbe..5584eb3111 100644 --- a/src/mainboard/kontron/986lcd-m/Kconfig +++ b/src/mainboard/kontron/986lcd-m/Kconfig @@ -16,6 +16,7 @@ config BOARD_SPECIFIC_OPTIONS select BOARD_ROMSIZE_KB_1024 select INTEL_INT15 select OVERRIDE_CLOCK_DISABLE + select BOOT_DEVICE_NOT_SPI_FLASH config MAINBOARD_DIR string diff --git a/src/mainboard/roda/rk886ex/Kconfig b/src/mainboard/roda/rk886ex/Kconfig index 9e97529dca..563b77392e 100644 --- a/src/mainboard/roda/rk886ex/Kconfig +++ b/src/mainboard/roda/rk886ex/Kconfig @@ -18,6 +18,7 @@ config BOARD_SPECIFIC_OPTIONS select HAVE_ACPI_RESUME select BOARD_ROMSIZE_KB_1024 select INTEL_INT15 + select BOOT_DEVICE_NOT_SPI_FLASH config MAINBOARD_DIR string From 0f476df76b6d022c139edc33dc2c892d7e6a4eaf Mon Sep 17 00:00:00 2001 From: Arthur Heymans Date: Fri, 15 Nov 2019 20:52:16 +0100 Subject: [PATCH 0209/1242] README.md: Remove link to deprecated wiki Change-Id: I4af62fdf4bfc34433d9f7dcf32acd1078b533a43 Signed-off-by: Arthur Heymans Reviewed-on: https://review.coreboot.org/c/coreboot/+/36872 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi --- README.md | 1 - 1 file changed, 1 deletion(-) diff --git a/README.md b/README.md index b13ace5d78..14879c1484 100644 --- a/README.md +++ b/README.md @@ -34,7 +34,6 @@ coreboot supports a wide range of chipsets, devices, and mainboards. For details please consult: * - * Build Requirements From e32d16f9d7a10cf5c65e62d428d0eafda137e552 Mon Sep 17 00:00:00 2001 From: Wim Vervoorn Date: Thu, 14 Nov 2019 14:10:28 +0100 Subject: [PATCH 0210/1242] vendorcode/eltan/security: Move eltan security from chipset to security menu The eltan security items ended up in the chipset menu which is not desired. Now the eltan security option (when enabled in mainboard) shows up in the security menu. BUG=N/A TEST=build Change-Id: I3b2aa3836e8d9a3242c6d1f3ba7b7821a5cfb9d3 Signed-off-by: Wim Vervoorn Reviewed-on: https://review.coreboot.org/c/coreboot/+/36851 Tested-by: build bot (Jenkins) Reviewed-by: Frans Hendriks --- src/Kconfig | 1 + src/vendorcode/eltan/Kconfig | 21 --------------------- src/vendorcode/eltan/security/Kconfig | 9 +++++++++ 3 files changed, 10 insertions(+), 21 deletions(-) delete mode 100644 src/vendorcode/eltan/Kconfig diff --git a/src/Kconfig b/src/Kconfig index 56ebe82e02..ba9ae86067 100644 --- a/src/Kconfig +++ b/src/Kconfig @@ -461,6 +461,7 @@ endmenu menu "Security" source "src/security/Kconfig" +source "src/vendorcode/eltan/security/Kconfig" endmenu diff --git a/src/vendorcode/eltan/Kconfig b/src/vendorcode/eltan/Kconfig deleted file mode 100644 index 30bb8b8ab8..0000000000 --- a/src/vendorcode/eltan/Kconfig +++ /dev/null @@ -1,21 +0,0 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2019 Eltan B.V. -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; version 2 of the License. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## - -config USE_VENDORCODE_ELTAN - bool - -if USE_VENDORCODE_ELTAN -source src/vendorcode/eltan/security/Kconfig -endif diff --git a/src/vendorcode/eltan/security/Kconfig b/src/vendorcode/eltan/security/Kconfig index 6b93d2a97a..1cc0365720 100644 --- a/src/vendorcode/eltan/security/Kconfig +++ b/src/vendorcode/eltan/security/Kconfig @@ -12,7 +12,16 @@ ## GNU General Public License for more details. ## +config USE_VENDORCODE_ELTAN + bool + +if USE_VENDORCODE_ELTAN + menu "Eltan Security Settings" + source src/vendorcode/eltan/security/mboot/Kconfig source src/vendorcode/eltan/security/verified_boot/Kconfig + endmenu + +endif From bcd1d1c32e4648b2878dcc673e558791deb75efe Mon Sep 17 00:00:00 2001 From: Shelley Chen Date: Fri, 15 Nov 2019 09:58:18 -0800 Subject: [PATCH 0211/1242] kohaku: Set GPP_A10 to NC Setting GPP_A10 to NC now that older boards are deprecated and this GPIO is not in use anymore. BUG=b:142056166 BRANCH=hatch TEST=./util/abuild/abuild -p none -t google/hatch -x -a Change-Id: If8a249a3dcba90bb4ccb5e3f02595e680f789f93 Signed-off-by: Shelley Chen Reviewed-on: https://review.coreboot.org/c/coreboot/+/36869 Reviewed-by: Tim Wawrzynczak Reviewed-by: Paul Fagerburg Tested-by: build bot (Jenkins) --- src/mainboard/google/hatch/variants/kohaku/gpio.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/mainboard/google/hatch/variants/kohaku/gpio.c b/src/mainboard/google/hatch/variants/kohaku/gpio.c index 7bf9a0cd5f..87c586d5a2 100644 --- a/src/mainboard/google/hatch/variants/kohaku/gpio.c +++ b/src/mainboard/google/hatch/variants/kohaku/gpio.c @@ -23,8 +23,8 @@ static const struct pad_config gpio_table[] = { PAD_NC(GPP_A0, NONE), /* A6 : SERIRQ ==> NC */ PAD_NC(GPP_A6, NONE), - /* A10 : PEN_RESET_ODL for old revision devices */ - PAD_CFG_GPO(GPP_A10, 1, DEEP), + /* A10 : GPP_A10 ==> NC */ + PAD_NC(GPP_A10, NONE), /* A16 : EMR_GARAGE_DET (notification) */ PAD_CFG_GPI_GPIO_DRIVER(GPP_A16, NONE, PLTRST), /* A17 : PIRQA# ==> NC */ From e477626d821f76fa846b9b7b99cfbcbf21eefc00 Mon Sep 17 00:00:00 2001 From: Hung-Te Lin Date: Wed, 13 Nov 2019 17:37:17 +0800 Subject: [PATCH 0212/1242] soc/mediatek/mt8183: Get more space for PreRAM memconsole Leave more space for PreRAM memconsole especially for seeing complete logs when doing DRAM full calibration (that outputs in 200+k to UART): - Shrink Full-K mem space (the ELF blob today needs ~132K) - Move PRERAM_CBFS_CACHE to L2C since it's no used after DRAM is up - Shrink TIMESTAMP to 1k (all other non-MTK ARM SOCs use only 1k) - Incease PRERAM_CBMEM_CONSOLE to 63k-4 - Reordered few sections to align at better locations BUG=b:144542023 TEST=emerge-kukui coreboot chromeos-bootimage; boot and see logs Change-Id: I8696fb01653c0a581cf62e687dc523cb6fed9a32 Signed-off-by: Hung-Te Lin Reviewed-on: https://review.coreboot.org/c/coreboot/+/36859 Tested-by: build bot (Jenkins) Reviewed-by: Julius Werner --- src/soc/mediatek/mt8183/include/soc/memlayout.ld | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/src/soc/mediatek/mt8183/include/soc/memlayout.ld b/src/soc/mediatek/mt8183/include/soc/memlayout.ld index a8f464a3d8..996d2ecbc8 100644 --- a/src/soc/mediatek/mt8183/include/soc/memlayout.ld +++ b/src/soc/mediatek/mt8183/include/soc/memlayout.ld @@ -32,11 +32,10 @@ SECTIONS SRAM_START(0x00100000) VBOOT2_WORK(0x00100000, 12K) VBOOT2_TPM_LOG(0x00103000, 2K) - PRERAM_CBMEM_CONSOLE(0x00103800, 14K) - WATCHDOG_TOMBSTONE(0x00107000, 4) - PRERAM_CBFS_CACHE(0x00107004, 46K - 4) - FMAP_CACHE(0x00112800, 2K) - TIMESTAMP(0x00113000, 4K) + FMAP_CACHE(0x00103800, 2K) + WATCHDOG_TOMBSTONE(0x00104000, 4) + PRERAM_CBMEM_CONSOLE(0x00104004, 63K - 4) + TIMESTAMP(0x00113c00, 1K) STACK(0x00114000, 16K) TTB(0x00118000, 28K) DMA_COHERENT(0x0011f000, 4K) @@ -45,7 +44,8 @@ SECTIONS SRAM_L2C_START(0x00200000) OVERLAP_DECOMPRESSOR_VERSTAGE_ROMSTAGE(0x00201000, 188K) BOOTBLOCK(0x00230000, 64K) - DRAM_INIT_CODE(0x00240000, 256K) + DRAM_INIT_CODE(0x00240000, 208K) + PRERAM_CBFS_CACHE(0x00274000, 48K) SRAM_L2C_END(0x00280000) DRAM_START(0x40000000) From 3557f124586851ee89deccf91c66c9ea50f9ffd4 Mon Sep 17 00:00:00 2001 From: Thejaswani Putta Date: Tue, 5 Nov 2019 17:51:58 -0800 Subject: [PATCH 0213/1242] libpayload: keyboard: Ignore special keys Some special keys emit a prefix scan code 0xE0. We will ignore all these except for the power button, F12 and cursor keys on drallion. Media key mapping is set in depthcharge and will be sent to libpayload keyboard driver. Whichever board requires this change will update its own media key mapping. BUG:b:139511038 TEST=boot in recovery mode, press F12 to go to diagnostic mode and power button to confirm. Also in recovery mode left arrow, right arrow, up arrow, down arrow changes the language on the firmware screen. Change-Id: I1c11939d18391bebe53ca21cf33a096ba369cd56 Signed-off-by: Thejaswani Putta Reviewed-on: https://review.coreboot.org/c/coreboot/+/36654 Reviewed-by: EricR Lai Reviewed-by: Mathew King Tested-by: build bot (Jenkins) --- payloads/libpayload/drivers/i8042/keyboard.c | 11 +++++++++++ payloads/libpayload/include/libpayload.h | 1 + 2 files changed, 12 insertions(+) diff --git a/payloads/libpayload/drivers/i8042/keyboard.c b/payloads/libpayload/drivers/i8042/keyboard.c index 48d35a07f7..f9932ed4ed 100644 --- a/payloads/libpayload/drivers/i8042/keyboard.c +++ b/payloads/libpayload/drivers/i8042/keyboard.c @@ -35,6 +35,7 @@ #include "i8042.h" #define POWER_BUTTON 0x90 +#define MEDIA_KEY_PREFIX 0xE0 struct layout_maps { const char *country; @@ -43,6 +44,7 @@ struct layout_maps { static struct layout_maps *map; static int modifier = 0; +int (*media_key_mapping_callback)(char ch); static struct layout_maps keyboard_layouts[] = { #if CONFIG(LP_PC_KEYBOARD_LAYOUT_US) @@ -230,6 +232,11 @@ int keyboard_getmodifier(void) return modifier; } +void initialize_keyboard_media_key_mapping_callback(int (*media_key_mapper)(char)) +{ + media_key_mapping_callback = media_key_mapper; +} + int keyboard_getchar(void) { unsigned char ch; @@ -239,6 +246,10 @@ int keyboard_getchar(void) while (!keyboard_havechar()) ; ch = keyboard_get_scancode(); + if ((media_key_mapping_callback != NULL) && (ch == MEDIA_KEY_PREFIX)) { + ch = keyboard_get_scancode(); + return media_key_mapping_callback(ch); + } if (!(ch & 0x80) && ch < 0x59) { shift = diff --git a/payloads/libpayload/include/libpayload.h b/payloads/libpayload/include/libpayload.h index 80bfaae6bf..bfe9da5f40 100644 --- a/payloads/libpayload/include/libpayload.h +++ b/payloads/libpayload/include/libpayload.h @@ -187,6 +187,7 @@ unsigned char keyboard_get_scancode(void); int keyboard_getchar(void); int keyboard_set_layout(char *country); int keyboard_getmodifier(void); +void initialize_keyboard_media_key_mapping_callback(int (*media_key_mapper)(char)); enum KEYBOARD_MODIFIERS { KB_MOD_SHIFT = (1 << 0), From e7087a19bc158e1bbbe6b2bfaef53e38a644f99c Mon Sep 17 00:00:00 2001 From: Wim Vervoorn Date: Fri, 15 Nov 2019 14:02:02 +0100 Subject: [PATCH 0214/1242] security/vboot: Add config option to always enable the display In order to always show the bootlogo very early in coreboot we need the option to always enable the display when VBOOT is enabled. To do this a config option is added to make sure this functionality can be provided without interfering with systems that require the standard VBOOT display handing. BUG=N/A TEST=tested on facebook fbg1701. Change-Id: I3ffaac85d2082717bb9608d536f7cec66a583789 Signed-off-by: Wim Vervoorn Reviewed-on: https://review.coreboot.org/c/coreboot/+/36547 Tested-by: build bot (Jenkins) Reviewed-by: Frans Hendriks Reviewed-by: Nico Huber --- src/security/vboot/Kconfig | 6 ++++++ src/security/vboot/vboot_logic.c | 2 +- 2 files changed, 7 insertions(+), 1 deletion(-) diff --git a/src/security/vboot/Kconfig b/src/security/vboot/Kconfig index 70180c719a..89e12323b6 100644 --- a/src/security/vboot/Kconfig +++ b/src/security/vboot/Kconfig @@ -167,6 +167,12 @@ config VBOOT_MUST_REQUEST_DISPLAY Unless display is specifically requested, the video option ROM is not loaded, and any other native display initialization code is not run. +config VBOOT_ALWAYS_ENABLE_DISPLAY + bool "Force to always enable display" + default n + help + Set this option to indicate to vboot that display should always be enabled. + config VBOOT_HAS_REC_HASH_SPACE bool default n diff --git a/src/security/vboot/vboot_logic.c b/src/security/vboot/vboot_logic.c index c4389a9bc1..5facd283ee 100644 --- a/src/security/vboot/vboot_logic.c +++ b/src/security/vboot/vboot_logic.c @@ -369,7 +369,7 @@ void verstage_main(void) ctx->flags |= VB2_CONTEXT_NOFAIL_BOOT; /* Mainboard/SoC always initializes display. */ - if (!CONFIG(VBOOT_MUST_REQUEST_DISPLAY)) + if (!CONFIG(VBOOT_MUST_REQUEST_DISPLAY) || CONFIG(VBOOT_ALWAYS_ENABLE_DISPLAY)) ctx->flags |= VB2_CONTEXT_DISPLAY_INIT; /* Do early init (set up secdata and NVRAM, load GBB) */ From 05d7d82d37ae04ec4cf3579eb1c0f7bf0c0b7aa2 Mon Sep 17 00:00:00 2001 From: Elyes HAOUAS Date: Sat, 16 Nov 2019 09:11:41 +0100 Subject: [PATCH 0215/1242] mb/{i945,ich7}: Remove redundant write on V0CTL RCBA32(V0CTL)= 0x80000001 already done inhere i945/early_init.c Change-Id: Ia775f4e6158a217b48629d289845537e7ccf5e79 Signed-off-by: Elyes HAOUAS Reviewed-on: https://review.coreboot.org/c/coreboot/+/36877 Tested-by: build bot (Jenkins) Reviewed-by: Arthur Heymans Reviewed-by: Nico Huber --- src/mainboard/apple/macbook21/early_init.c | 3 --- src/mainboard/getac/p470/early_init.c | 3 --- src/mainboard/ibase/mb899/early_init.c | 3 --- src/mainboard/intel/d945gclf/early_init.c | 3 --- src/mainboard/kontron/986lcd-m/early_init.c | 2 -- src/mainboard/lenovo/t60/early_init.c | 3 --- src/mainboard/lenovo/x60/early_init.c | 3 --- src/mainboard/roda/rk886ex/early_init.c | 2 -- 8 files changed, 22 deletions(-) diff --git a/src/mainboard/apple/macbook21/early_init.c b/src/mainboard/apple/macbook21/early_init.c index d4654de118..081e55ade4 100644 --- a/src/mainboard/apple/macbook21/early_init.c +++ b/src/mainboard/apple/macbook21/early_init.c @@ -20,9 +20,6 @@ void mainboard_late_rcba_config(void) { - /* V0CTL Virtual Channel 0 Resource Control */ - RCBA32(0x0014) = 0x80000001; - /* Device 1f interrupt pin register */ RCBA32(0x3100) = 0x00042210; RCBA32(0x3108) = 0x10004321; diff --git a/src/mainboard/getac/p470/early_init.c b/src/mainboard/getac/p470/early_init.c index 3684c1c943..c75caada6e 100644 --- a/src/mainboard/getac/p470/early_init.c +++ b/src/mainboard/getac/p470/early_init.c @@ -123,9 +123,6 @@ void bootblock_mainboard_early_init(void) void mainboard_late_rcba_config(void) { - /* Set up virtual channel 0 */ - //RCBA32(0x0014) = 0x80000001; - /* Device 1f interrupt pin register */ RCBA32(D31IP) = 0x00042220; /* Device 1d interrupt pin register */ diff --git a/src/mainboard/ibase/mb899/early_init.c b/src/mainboard/ibase/mb899/early_init.c index ba8d30cf29..0b005022d8 100644 --- a/src/mainboard/ibase/mb899/early_init.c +++ b/src/mainboard/ibase/mb899/early_init.c @@ -99,9 +99,6 @@ void bootblock_mainboard_early_init(void) void mainboard_late_rcba_config(void) { - /* Set up virtual channel 0 */ - //RCBA32(0x0014) = 0x80000001; - /* Device 1f interrupt pin register */ RCBA32(D31IP) = 0x00042210; /* Device 1d interrupt pin register */ diff --git a/src/mainboard/intel/d945gclf/early_init.c b/src/mainboard/intel/d945gclf/early_init.c index c8dd3619c8..b4818e49ca 100644 --- a/src/mainboard/intel/d945gclf/early_init.c +++ b/src/mainboard/intel/d945gclf/early_init.c @@ -23,9 +23,6 @@ void mainboard_late_rcba_config(void) { - /* Set up virtual channel 0 */ - //RCBA32(0x0014) = 0x80000001; - /* dev irq route register */ RCBA16(D31IR) = 0x0132; RCBA16(D30IR) = 0x0146; diff --git a/src/mainboard/kontron/986lcd-m/early_init.c b/src/mainboard/kontron/986lcd-m/early_init.c index 48fe4935ae..31cb20998d 100644 --- a/src/mainboard/kontron/986lcd-m/early_init.c +++ b/src/mainboard/kontron/986lcd-m/early_init.c @@ -144,8 +144,6 @@ void bootblock_mainboard_early_init(void) void mainboard_late_rcba_config(void) { - /* Set up virtual channel 0 */ - /* Device 1f interrupt pin register */ RCBA32(D31IP) = 0x00042210; /* Device 1d interrupt pin register */ diff --git a/src/mainboard/lenovo/t60/early_init.c b/src/mainboard/lenovo/t60/early_init.c index d3de1e4c94..edd167a7ec 100644 --- a/src/mainboard/lenovo/t60/early_init.c +++ b/src/mainboard/lenovo/t60/early_init.c @@ -69,9 +69,6 @@ void bootblock_mainboard_early_init(void) void mainboard_late_rcba_config(void) { - /* Set up virtual channel 0 */ - RCBA32(V0CTL) = 0x80000001; - /* Device 1f interrupt pin register */ RCBA32(D31IP) = 0x00001230; RCBA32(D29IP) = 0x40004321; diff --git a/src/mainboard/lenovo/x60/early_init.c b/src/mainboard/lenovo/x60/early_init.c index 459c2461ca..8cf5ab498d 100644 --- a/src/mainboard/lenovo/x60/early_init.c +++ b/src/mainboard/lenovo/x60/early_init.c @@ -68,9 +68,6 @@ void bootblock_mainboard_early_init(void) void mainboard_late_rcba_config(void) { - /* Set up virtual channel 0 */ - RCBA32(V0CTL) = 0x80000001; - /* Device 1f interrupt pin register */ RCBA32(D31IP) = 0x00001230; RCBA32(D29IP) = 0x40004321; diff --git a/src/mainboard/roda/rk886ex/early_init.c b/src/mainboard/roda/rk886ex/early_init.c index dff1a6fe03..f3e24e0f3b 100644 --- a/src/mainboard/roda/rk886ex/early_init.c +++ b/src/mainboard/roda/rk886ex/early_init.c @@ -92,8 +92,6 @@ void bootblock_mainboard_early_init(void) void mainboard_late_rcba_config(void) { - /* Set up virtual channel 0 */ - /* Device 1f interrupt pin register */ RCBA32(D31IP) = 0x00042220; From dc2e7c6e0fb1331a7808c226992c71e07f9ca7bd Mon Sep 17 00:00:00 2001 From: Arthur Heymans Date: Tue, 12 Nov 2019 16:17:26 +0100 Subject: [PATCH 0216/1242] nb/intel/sandybridge: Make the mainboard_early_init hook optional This adds an empty weakly linked default. The rationale behind this change is that without the callback some features might not work but that the result is likely still able to boot, so it can be made optional. Change-Id: I62c8010aa81fc45d208e9293feb2f45b45f34a82 Signed-off-by: Arthur Heymans Reviewed-on: https://review.coreboot.org/c/coreboot/+/36780 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber --- src/mainboard/apple/macbookair4_2/romstage.c | 4 ---- src/mainboard/asrock/b75pro3-m/romstage.c | 4 ---- src/mainboard/asus/h61m-cs/romstage.c | 4 ---- src/mainboard/asus/maximus_iv_gene-z/romstage.c | 4 ---- src/mainboard/asus/p8h61-m_lx/romstage.c | 4 ---- src/mainboard/asus/p8h61-m_pro/romstage.c | 4 ---- src/mainboard/asus/p8z77-m_pro/romstage.c | 4 ---- src/mainboard/compulab/intense_pc/romstage.c | 4 ---- src/mainboard/gigabyte/ga-b75m-d3h/romstage.c | 4 ---- src/mainboard/gigabyte/ga-h61m-s2pv/romstage.c | 4 ---- src/mainboard/google/butterfly/romstage.c | 4 ---- src/mainboard/google/parrot/romstage.c | 4 ---- src/mainboard/hp/2570p/romstage.c | 4 ---- src/mainboard/hp/2760p/romstage.c | 4 ---- src/mainboard/hp/8460p/romstage.c | 4 ---- src/mainboard/hp/8470p/romstage.c | 4 ---- src/mainboard/hp/8770w/romstage.c | 4 ---- src/mainboard/hp/compaq_8200_elite_sff/romstage.c | 4 ---- src/mainboard/hp/folio_9470m/romstage.c | 4 ---- src/mainboard/hp/revolve_810_g1/romstage.c | 4 ---- src/mainboard/hp/z220_sff_workstation/romstage.c | 4 ---- src/mainboard/intel/dcp847ske/early_southbridge.c | 4 ---- src/mainboard/intel/emeraldlake2/romstage.c | 4 ---- src/mainboard/lenovo/l520/romstage.c | 4 ---- src/mainboard/lenovo/s230u/romstage.c | 4 ---- src/mainboard/lenovo/t430s/variants/t431s/romstage.c | 4 ---- src/mainboard/lenovo/x131e/romstage.c | 4 ---- src/mainboard/lenovo/x1_carbon_gen1/romstage.c | 4 ---- src/mainboard/lenovo/x220/romstage.c | 4 ---- src/mainboard/lenovo/x230/romstage.c | 4 ---- src/mainboard/msi/ms7707/romstage.c | 4 ---- src/mainboard/roda/rv11/romstage.c | 4 ---- src/mainboard/sapphire/pureplatinumh61/romstage.c | 4 ---- src/northbridge/intel/sandybridge/romstage.c | 4 ++++ src/northbridge/intel/sandybridge/sandybridge.h | 2 ++ 35 files changed, 6 insertions(+), 132 deletions(-) diff --git a/src/mainboard/apple/macbookair4_2/romstage.c b/src/mainboard/apple/macbookair4_2/romstage.c index d04582d1ed..a7c543dd49 100644 --- a/src/mainboard/apple/macbookair4_2/romstage.c +++ b/src/mainboard/apple/macbookair4_2/romstage.c @@ -49,10 +49,6 @@ const struct southbridge_usb_port mainboard_usb_ports[] = { { 1, 0, -1 }, }; -void mainboard_early_init(int s3resume) -{ -} - void mainboard_config_superio(void) { } diff --git a/src/mainboard/asrock/b75pro3-m/romstage.c b/src/mainboard/asrock/b75pro3-m/romstage.c index da895b31fd..fe6d1833d2 100644 --- a/src/mainboard/asrock/b75pro3-m/romstage.c +++ b/src/mainboard/asrock/b75pro3-m/romstage.c @@ -48,10 +48,6 @@ const struct southbridge_usb_port mainboard_usb_ports[] = { { 1, 0, 6 }, }; -void mainboard_early_init(int s3resume) -{ -} - void mainboard_config_superio(void) { /* Set GPIOs on superio, enable UART */ diff --git a/src/mainboard/asus/h61m-cs/romstage.c b/src/mainboard/asus/h61m-cs/romstage.c index 2064f14e22..37b07e51d9 100644 --- a/src/mainboard/asus/h61m-cs/romstage.c +++ b/src/mainboard/asus/h61m-cs/romstage.c @@ -52,10 +52,6 @@ const struct southbridge_usb_port mainboard_usb_ports[] = { { 1, 0, 6 }, }; -void mainboard_early_init(int s3resume) -{ -} - void mainboard_config_superio(void) { nuvoton_pnp_enter_conf_state(SIO_DEV); diff --git a/src/mainboard/asus/maximus_iv_gene-z/romstage.c b/src/mainboard/asus/maximus_iv_gene-z/romstage.c index fcf78d2e68..6cf206b47c 100644 --- a/src/mainboard/asus/maximus_iv_gene-z/romstage.c +++ b/src/mainboard/asus/maximus_iv_gene-z/romstage.c @@ -48,10 +48,6 @@ void mainboard_rcba_config(void) { } -void mainboard_early_init(int s3resume) -{ -} - void mainboard_config_superio(void) { static const pnp_devfn_t GLOBAL_PSEUDO_DEV = PNP_DEV(0x2e, 0); diff --git a/src/mainboard/asus/p8h61-m_lx/romstage.c b/src/mainboard/asus/p8h61-m_lx/romstage.c index 09ca7db238..5f94d17cf4 100644 --- a/src/mainboard/asus/p8h61-m_lx/romstage.c +++ b/src/mainboard/asus/p8h61-m_lx/romstage.c @@ -51,10 +51,6 @@ void mainboard_rcba_config(void) { } -void mainboard_early_init(int s3resume) -{ -} - void mainboard_config_superio(void) { nuvoton_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); diff --git a/src/mainboard/asus/p8h61-m_pro/romstage.c b/src/mainboard/asus/p8h61-m_pro/romstage.c index 73848285a9..60d311d98c 100644 --- a/src/mainboard/asus/p8h61-m_pro/romstage.c +++ b/src/mainboard/asus/p8h61-m_pro/romstage.c @@ -53,10 +53,6 @@ const struct southbridge_usb_port mainboard_usb_ports[] = { { 1, 0, 6 }, }; -void mainboard_early_init(int s3resume) -{ -} - void mainboard_config_superio(void) { /* Enable UART */ diff --git a/src/mainboard/asus/p8z77-m_pro/romstage.c b/src/mainboard/asus/p8z77-m_pro/romstage.c index 9c5e443908..db2d303e8c 100644 --- a/src/mainboard/asus/p8z77-m_pro/romstage.c +++ b/src/mainboard/asus/p8z77-m_pro/romstage.c @@ -56,10 +56,6 @@ const struct southbridge_usb_port mainboard_usb_ports[] = { { 0, 2, 6 } /* Port 13: Unused. Asus propietary DEBUG_PORT ??? */ }; -void mainboard_early_init(int s3resume) -{ -} - void mainboard_config_superio(void) { /* Setup COM/UART */ diff --git a/src/mainboard/compulab/intense_pc/romstage.c b/src/mainboard/compulab/intense_pc/romstage.c index f74e94d042..8198d8af6e 100644 --- a/src/mainboard/compulab/intense_pc/romstage.c +++ b/src/mainboard/compulab/intense_pc/romstage.c @@ -60,10 +60,6 @@ const struct southbridge_usb_port mainboard_usb_ports[] = { { 1, 0, 6 }, }; -void mainboard_early_init(int s3resume) -{ -} - void mainboard_config_superio(void) { const u16 port = SIO_PORT; diff --git a/src/mainboard/gigabyte/ga-b75m-d3h/romstage.c b/src/mainboard/gigabyte/ga-b75m-d3h/romstage.c index ecbd393b2b..f67d51b8be 100644 --- a/src/mainboard/gigabyte/ga-b75m-d3h/romstage.c +++ b/src/mainboard/gigabyte/ga-b75m-d3h/romstage.c @@ -78,10 +78,6 @@ const struct southbridge_usb_port mainboard_usb_ports[] = { { 1, 5, 6 }, }; -void mainboard_early_init(int s3resume) -{ -} - /* FIXME: The GA-B75M-D3V only has two DIMM slots! */ void mainboard_get_spd(spd_raw_data *spd, bool id_only) { diff --git a/src/mainboard/gigabyte/ga-h61m-s2pv/romstage.c b/src/mainboard/gigabyte/ga-h61m-s2pv/romstage.c index 8a17ac9a56..1df5bfd80c 100644 --- a/src/mainboard/gigabyte/ga-h61m-s2pv/romstage.c +++ b/src/mainboard/gigabyte/ga-h61m-s2pv/romstage.c @@ -48,10 +48,6 @@ const struct southbridge_usb_port mainboard_usb_ports[] = { { 1, 0, 6 }, }; -void mainboard_early_init(int s3resume) -{ -} - void mainboard_config_superio(void) { if (!CONFIG(NO_UART_ON_SUPERIO)) { diff --git a/src/mainboard/google/butterfly/romstage.c b/src/mainboard/google/butterfly/romstage.c index 844f754cfc..449ccf507e 100644 --- a/src/mainboard/google/butterfly/romstage.c +++ b/src/mainboard/google/butterfly/romstage.c @@ -112,10 +112,6 @@ void mainboard_get_spd(spd_raw_data *spd, bool id_only) read_spd(&spd[2], 0x52, id_only); } -void mainboard_early_init(int s3resume) -{ -} - void mainboard_config_superio(void) { } diff --git a/src/mainboard/google/parrot/romstage.c b/src/mainboard/google/parrot/romstage.c index 210c7fc04c..8893819446 100644 --- a/src/mainboard/google/parrot/romstage.c +++ b/src/mainboard/google/parrot/romstage.c @@ -84,10 +84,6 @@ void mainboard_rcba_config(void) RCBA32(FD) = reg32; } -void mainboard_early_init(int s3resume) -{ -} - void mainboard_fill_pei_data(struct pei_data *pei_data) { struct pei_data pei_data_template = { diff --git a/src/mainboard/hp/2570p/romstage.c b/src/mainboard/hp/2570p/romstage.c index 6ffc3409a5..4f7ca3a18c 100644 --- a/src/mainboard/hp/2570p/romstage.c +++ b/src/mainboard/hp/2570p/romstage.c @@ -45,10 +45,6 @@ const struct southbridge_usb_port mainboard_usb_ports[] = { { 0, 0, 6 }, }; -void mainboard_early_init(int s3resume) -{ -} - void mainboard_config_superio(void) { kbc1126_enter_conf(); diff --git a/src/mainboard/hp/2760p/romstage.c b/src/mainboard/hp/2760p/romstage.c index b448f79259..a696faec36 100644 --- a/src/mainboard/hp/2760p/romstage.c +++ b/src/mainboard/hp/2760p/romstage.c @@ -44,10 +44,6 @@ const struct southbridge_usb_port mainboard_usb_ports[] = { { 1, 1, 6 }, }; -void mainboard_early_init(int s3resume) -{ -} - void mainboard_config_superio(void) { kbc1126_enter_conf(); diff --git a/src/mainboard/hp/8460p/romstage.c b/src/mainboard/hp/8460p/romstage.c index 72a62c9eb3..77c355bb23 100644 --- a/src/mainboard/hp/8460p/romstage.c +++ b/src/mainboard/hp/8460p/romstage.c @@ -48,10 +48,6 @@ const struct southbridge_usb_port mainboard_usb_ports[] = { { 1, 0, 6 }, /* docking */ }; -void mainboard_early_init(int s3resume) -{ -} - void mainboard_config_superio(void) { lpc47n217_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); diff --git a/src/mainboard/hp/8470p/romstage.c b/src/mainboard/hp/8470p/romstage.c index 83f382d0a4..890e65b07c 100644 --- a/src/mainboard/hp/8470p/romstage.c +++ b/src/mainboard/hp/8470p/romstage.c @@ -47,10 +47,6 @@ const struct southbridge_usb_port mainboard_usb_ports[] = { { 1, 0, 6 }, }; -void mainboard_early_init(int s3resume) -{ -} - void mainboard_config_superio(void) { lpc47n217_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); diff --git a/src/mainboard/hp/8770w/romstage.c b/src/mainboard/hp/8770w/romstage.c index 2bd9162beb..49a5b1af48 100644 --- a/src/mainboard/hp/8770w/romstage.c +++ b/src/mainboard/hp/8770w/romstage.c @@ -48,10 +48,6 @@ const struct southbridge_usb_port mainboard_usb_ports[] = { { 1, 0, 6 }, /* Conn (eSATA Combo) */ }; -void mainboard_early_init(int s3resume) -{ -} - void mainboard_config_superio(void) { lpc47n217_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); diff --git a/src/mainboard/hp/compaq_8200_elite_sff/romstage.c b/src/mainboard/hp/compaq_8200_elite_sff/romstage.c index 258eac74b2..90cfcc93aa 100644 --- a/src/mainboard/hp/compaq_8200_elite_sff/romstage.c +++ b/src/mainboard/hp/compaq_8200_elite_sff/romstage.c @@ -52,10 +52,6 @@ const struct southbridge_usb_port mainboard_usb_ports[] = { { 1, 0, -1 }, }; -void mainboard_early_init(int s3resume) -{ -} - void mainboard_config_superio(void) { if (CONFIG(CONSOLE_SERIAL)) diff --git a/src/mainboard/hp/folio_9470m/romstage.c b/src/mainboard/hp/folio_9470m/romstage.c index 061a06877c..3f174a19fb 100644 --- a/src/mainboard/hp/folio_9470m/romstage.c +++ b/src/mainboard/hp/folio_9470m/romstage.c @@ -46,10 +46,6 @@ const struct southbridge_usb_port mainboard_usb_ports[] = { { 0, 0, 6 }, /* B1P6 */ }; -void mainboard_early_init(int s3resume) -{ -} - void mainboard_config_superio(void) { kbc1126_enter_conf(); diff --git a/src/mainboard/hp/revolve_810_g1/romstage.c b/src/mainboard/hp/revolve_810_g1/romstage.c index 5c83a91511..8a40578f0a 100644 --- a/src/mainboard/hp/revolve_810_g1/romstage.c +++ b/src/mainboard/hp/revolve_810_g1/romstage.c @@ -50,10 +50,6 @@ const struct southbridge_usb_port mainboard_usb_ports[] = { { 0, 0, 6 }, /* B1P6 */ }; -void mainboard_early_init(int s3resume) -{ -} - void mainboard_config_superio(void) { kbc1126_enter_conf(); diff --git a/src/mainboard/hp/z220_sff_workstation/romstage.c b/src/mainboard/hp/z220_sff_workstation/romstage.c index 6c139ed34d..bd0a377580 100644 --- a/src/mainboard/hp/z220_sff_workstation/romstage.c +++ b/src/mainboard/hp/z220_sff_workstation/romstage.c @@ -52,10 +52,6 @@ const struct southbridge_usb_port mainboard_usb_ports[] = { { 1, 0, 7 }, }; -void mainboard_early_init(int s3resume) -{ -} - void mainboard_config_superio(void) { if (CONFIG(CONSOLE_SERIAL)) diff --git a/src/mainboard/intel/dcp847ske/early_southbridge.c b/src/mainboard/intel/dcp847ske/early_southbridge.c index 984629574c..7f3a58d0f2 100644 --- a/src/mainboard/intel/dcp847ske/early_southbridge.c +++ b/src/mainboard/intel/dcp847ske/early_southbridge.c @@ -52,10 +52,6 @@ void mainboard_rcba_config(void) MCHBAR32(0x0104) |= 0x00001000; } -void mainboard_early_init(int s3resume) -{ -} - static const u16 hwm_initvals[] = { HWM_BANK(0), HWM_INITVAL(0xae, 0x01), /* Enable PECI Agent0 */ diff --git a/src/mainboard/intel/emeraldlake2/romstage.c b/src/mainboard/intel/emeraldlake2/romstage.c index d56576e2e5..e7959ef32f 100644 --- a/src/mainboard/intel/emeraldlake2/romstage.c +++ b/src/mainboard/intel/emeraldlake2/romstage.c @@ -153,10 +153,6 @@ void mainboard_get_spd(spd_raw_data *spd, bool id_only) read_spd(&spd[2], 0x52, id_only); } -void mainboard_early_init(int s3resume) -{ -} - int mainboard_should_reset_usb(int s3resume) { return !s3resume; diff --git a/src/mainboard/lenovo/l520/romstage.c b/src/mainboard/lenovo/l520/romstage.c index 82f63776d9..fc67e5adcf 100644 --- a/src/mainboard/lenovo/l520/romstage.c +++ b/src/mainboard/lenovo/l520/romstage.c @@ -47,10 +47,6 @@ const struct southbridge_usb_port mainboard_usb_ports[] = { { 1, 0, -1 }, }; -void mainboard_early_init(int s3resume) -{ -} - void mainboard_config_superio(void) { } diff --git a/src/mainboard/lenovo/s230u/romstage.c b/src/mainboard/lenovo/s230u/romstage.c index 754c49aa4f..48d26c2519 100644 --- a/src/mainboard/lenovo/s230u/romstage.c +++ b/src/mainboard/lenovo/s230u/romstage.c @@ -64,10 +64,6 @@ const struct southbridge_usb_port mainboard_usb_ports[] = { { 1, 1, 6 }, }; -void mainboard_early_init(int s3resume) -{ -} - void mainboard_config_superio(void) { } diff --git a/src/mainboard/lenovo/t430s/variants/t431s/romstage.c b/src/mainboard/lenovo/t430s/variants/t431s/romstage.c index e7b43db487..3f62f06c58 100644 --- a/src/mainboard/lenovo/t430s/variants/t431s/romstage.c +++ b/src/mainboard/lenovo/t430s/variants/t431s/romstage.c @@ -54,7 +54,3 @@ void mainboard_get_spd(spd_raw_data *spd, bool id_only) memcpy(&spd[0], spd_file, spd_file_len); read_spd(&spd[2], 0x51, id_only); } - -void mainboard_early_init(int s3resume) -{ -} diff --git a/src/mainboard/lenovo/x131e/romstage.c b/src/mainboard/lenovo/x131e/romstage.c index 2a6ee2733b..6f176c78f7 100644 --- a/src/mainboard/lenovo/x131e/romstage.c +++ b/src/mainboard/lenovo/x131e/romstage.c @@ -51,10 +51,6 @@ void mainboard_get_spd(spd_raw_data *spd, bool id_only) read_spd(&spd[2], 0x52, id_only); } -void mainboard_early_init(int s3resume) -{ -} - void mainboard_config_superio(void) { } diff --git a/src/mainboard/lenovo/x1_carbon_gen1/romstage.c b/src/mainboard/lenovo/x1_carbon_gen1/romstage.c index b779c4eff5..eb2a5b19f5 100644 --- a/src/mainboard/lenovo/x1_carbon_gen1/romstage.c +++ b/src/mainboard/lenovo/x1_carbon_gen1/romstage.c @@ -104,10 +104,6 @@ void mainboard_get_spd(spd_raw_data *spd, bool id_only) memcpy(&spd[2], memory, 256); } -void mainboard_early_init(int s3resume) -{ -} - void mainboard_config_superio(void) { } diff --git a/src/mainboard/lenovo/x220/romstage.c b/src/mainboard/lenovo/x220/romstage.c index af92f9ba8e..8460208ddb 100644 --- a/src/mainboard/lenovo/x220/romstage.c +++ b/src/mainboard/lenovo/x220/romstage.c @@ -91,10 +91,6 @@ void mainboard_get_spd(spd_raw_data *spd, bool id_only) read_spd (&spd[2], 0x51, id_only); } -void mainboard_early_init(int s3resume) -{ -} - void mainboard_config_superio(void) { } diff --git a/src/mainboard/lenovo/x230/romstage.c b/src/mainboard/lenovo/x230/romstage.c index 60016a4f07..6f1013567b 100644 --- a/src/mainboard/lenovo/x230/romstage.c +++ b/src/mainboard/lenovo/x230/romstage.c @@ -56,10 +56,6 @@ void mainboard_get_spd(spd_raw_data *spd, bool id_only) read_spd (&spd[2], 0x51, id_only); } -void mainboard_early_init(int s3resume) -{ -} - void mainboard_config_superio(void) { } diff --git a/src/mainboard/msi/ms7707/romstage.c b/src/mainboard/msi/ms7707/romstage.c index a797f5099c..8f83c8684c 100644 --- a/src/mainboard/msi/ms7707/romstage.c +++ b/src/mainboard/msi/ms7707/romstage.c @@ -49,10 +49,6 @@ const struct southbridge_usb_port mainboard_usb_ports[] = { {1, 0, 6}, }; -void mainboard_early_init(int s3resume) -{ -} - void mainboard_config_superio(void) { } diff --git a/src/mainboard/roda/rv11/romstage.c b/src/mainboard/roda/rv11/romstage.c index b36725c213..a54a9ad6ce 100644 --- a/src/mainboard/roda/rv11/romstage.c +++ b/src/mainboard/roda/rv11/romstage.c @@ -27,10 +27,6 @@ void mainboard_rcba_config(void) RCBA32(FD) = reg32; } -void mainboard_early_init(int s3resume) -{ -} - int mainboard_should_reset_usb(int s3resume) { return !s3resume; diff --git a/src/mainboard/sapphire/pureplatinumh61/romstage.c b/src/mainboard/sapphire/pureplatinumh61/romstage.c index ff5bb701a8..7fcde773b1 100644 --- a/src/mainboard/sapphire/pureplatinumh61/romstage.c +++ b/src/mainboard/sapphire/pureplatinumh61/romstage.c @@ -48,10 +48,6 @@ const struct southbridge_usb_port mainboard_usb_ports[] = { { 1, 0, 6 }, }; -void mainboard_early_init(int s3resume) -{ -} - void mainboard_config_superio(void) { } diff --git a/src/northbridge/intel/sandybridge/romstage.c b/src/northbridge/intel/sandybridge/romstage.c index 55f2928213..92882b4b61 100644 --- a/src/northbridge/intel/sandybridge/romstage.c +++ b/src/northbridge/intel/sandybridge/romstage.c @@ -30,6 +30,10 @@ #include #include +__weak void mainboard_early_init(int s3_resume) +{ +} + static void early_pch_reset_pmcon(void) { u8 reg8; diff --git a/src/northbridge/intel/sandybridge/sandybridge.h b/src/northbridge/intel/sandybridge/sandybridge.h index 31d4358e7b..d667e36571 100644 --- a/src/northbridge/intel/sandybridge/sandybridge.h +++ b/src/northbridge/intel/sandybridge/sandybridge.h @@ -213,6 +213,8 @@ void northbridge_romstage_finalize(int s3resume); void early_init_dmi(void); void pch_enable_lpc(void); +/* mainboard_early_init: Optional mainboard callback run after console init + but before raminit. */ void mainboard_early_init(int s3resume); void mainboard_config_superio(void); int mainboard_should_reset_usb(int s3resume); From 3457df1730bf4446fa0e0042e43cc0c0e7bd1073 Mon Sep 17 00:00:00 2001 From: Arthur Heymans Date: Sat, 16 Nov 2019 10:04:41 +0100 Subject: [PATCH 0217/1242] sb/intel/common: Properly guard USB debug The declarations in usb_debug.c needs to be guarded in order to not conflict with other chipsets. Change-Id: I84c3401b9419f2878c2cfdf81147fa854018f9ae Signed-off-by: Arthur Heymans Reviewed-on: https://review.coreboot.org/c/coreboot/+/36878 Reviewed-by: Nico Huber Reviewed-by: Mike Banon Tested-by: build bot (Jenkins) --- src/southbridge/intel/bd82x6x/Kconfig | 1 + src/southbridge/intel/common/Kconfig | 4 ++++ src/southbridge/intel/common/Makefile.inc | 6 +++--- src/southbridge/intel/fsp_rangeley/Kconfig | 2 +- src/southbridge/intel/i82801dx/Kconfig | 2 +- src/southbridge/intel/i82801gx/Kconfig | 2 +- src/southbridge/intel/i82801ix/Kconfig | 2 +- src/southbridge/intel/i82801jx/Kconfig | 2 +- src/southbridge/intel/ibexpeak/Kconfig | 2 +- src/southbridge/intel/lynxpoint/Kconfig | 1 + 10 files changed, 15 insertions(+), 9 deletions(-) diff --git a/src/southbridge/intel/bd82x6x/Kconfig b/src/southbridge/intel/bd82x6x/Kconfig index f561fe53fb..c01e2b9eed 100644 --- a/src/southbridge/intel/bd82x6x/Kconfig +++ b/src/southbridge/intel/bd82x6x/Kconfig @@ -47,6 +47,7 @@ config SOUTH_BRIDGE_OPTIONS # dummy select SOUTHBRIDGE_INTEL_COMMON_SMM select SOUTHBRIDGE_INTEL_COMMON_ACPI_MADT select SOUTHBRIDGE_INTEL_COMMON_WATCHDOG + select SOUTHBRIDGE_INTEL_COMMON_USB_DEBUG config EHCI_BAR hex diff --git a/src/southbridge/intel/common/Kconfig b/src/southbridge/intel/common/Kconfig index 57c0dbe19f..18bcd2e4a6 100644 --- a/src/southbridge/intel/common/Kconfig +++ b/src/southbridge/intel/common/Kconfig @@ -46,6 +46,10 @@ config SOUTHBRIDGE_INTEL_COMMON_ACPI_MADT config SOUTHBRIDGE_INTEL_COMMON_FINALIZE bool +config SOUTHBRIDGE_INTEL_COMMON_USB_DEBUG + def_bool n + select HAVE_USBDEBUG + config INTEL_DESCRIPTOR_MODE_CAPABLE def_bool n help diff --git a/src/southbridge/intel/common/Makefile.inc b/src/southbridge/intel/common/Makefile.inc index 9ff0ebc5a1..c8521e1b5a 100644 --- a/src/southbridge/intel/common/Makefile.inc +++ b/src/southbridge/intel/common/Makefile.inc @@ -28,9 +28,9 @@ ramstage-$(CONFIG_SOUTHBRIDGE_INTEL_COMMON_WATCHDOG) += watchdog.c all-$(CONFIG_SOUTHBRIDGE_INTEL_COMMON_PMBASE) += pmbase.c smm-$(CONFIG_SOUTHBRIDGE_INTEL_COMMON_PMBASE) += pmbase.c -bootblock-$(CONFIG_USBDEBUG) += usb_debug.c -romstage-$(CONFIG_USBDEBUG) += usb_debug.c -ramstage-$(CONFIG_USBDEBUG) += usb_debug.c +bootblock-$(CONFIG_SOUTHBRIDGE_INTEL_COMMON_USB_DEBUG) += usb_debug.c +romstage-$(CONFIG_SOUTHBRIDGE_INTEL_COMMON_USB_DEBUG) += usb_debug.c +ramstage-$(CONFIG_SOUTHBRIDGE_INTEL_COMMON_USB_DEBUG) += usb_debug.c bootblock-$(CONFIG_SOUTHBRIDGE_INTEL_COMMON_GPIO) += gpio.c romstage-$(CONFIG_SOUTHBRIDGE_INTEL_COMMON_GPIO) += gpio.c diff --git a/src/southbridge/intel/fsp_rangeley/Kconfig b/src/southbridge/intel/fsp_rangeley/Kconfig index 56c02b534d..076a2bce55 100644 --- a/src/southbridge/intel/fsp_rangeley/Kconfig +++ b/src/southbridge/intel/fsp_rangeley/Kconfig @@ -23,7 +23,6 @@ config SOUTH_BRIDGE_OPTIONS # dummy def_bool y select ACPI_INTEL_HARDWARE_SLEEP_VALUES select IOAPIC - select HAVE_USBDEBUG select USE_WATCHDOG_ON_BOOT select PCIEXP_ASPM select PCIEXP_COMMON_CLOCK @@ -34,6 +33,7 @@ config SOUTH_BRIDGE_OPTIONS # dummy select SOUTHBRIDGE_INTEL_COMMON_PMBASE select SOUTHBRIDGE_INTEL_COMMON_RTC select SOUTHBRIDGE_INTEL_COMMON_RESET + select SOUTHBRIDGE_INTEL_COMMON_USB_DEBUG config EHCI_BAR hex diff --git a/src/southbridge/intel/i82801dx/Kconfig b/src/southbridge/intel/i82801dx/Kconfig index 916560a87a..5dad02ef2f 100644 --- a/src/southbridge/intel/i82801dx/Kconfig +++ b/src/southbridge/intel/i82801dx/Kconfig @@ -19,10 +19,10 @@ config SOUTHBRIDGE_INTEL_I82801DX select ACPI_INTEL_HARDWARE_SLEEP_VALUES select IOAPIC select HAVE_SMI_HANDLER - select HAVE_USBDEBUG select SOUTHBRIDGE_INTEL_COMMON_SMBUS select SOUTHBRIDGE_INTEL_COMMON_RTC select SOUTHBRIDGE_INTEL_COMMON_RESET + select SOUTHBRIDGE_INTEL_COMMON_USB_DEBUG select HAVE_POWER_STATE_AFTER_FAILURE select HAVE_POWER_STATE_PREVIOUS_AFTER_FAILURE diff --git a/src/southbridge/intel/i82801gx/Kconfig b/src/southbridge/intel/i82801gx/Kconfig index bf9880ac27..2d95fc2371 100644 --- a/src/southbridge/intel/i82801gx/Kconfig +++ b/src/southbridge/intel/i82801gx/Kconfig @@ -17,7 +17,6 @@ config SOUTHBRIDGE_INTEL_I82801GX bool select ACPI_INTEL_HARDWARE_SLEEP_VALUES select IOAPIC - select HAVE_USBDEBUG select USE_WATCHDOG_ON_BOOT select HAVE_SMI_HANDLER select COMMON_FADT @@ -33,6 +32,7 @@ config SOUTHBRIDGE_INTEL_I82801GX select SOUTHBRIDGE_INTEL_COMMON_WATCHDOG select SOUTHBRIDGE_INTEL_COMMON_RTC select SOUTHBRIDGE_INTEL_COMMON_RESET + select SOUTHBRIDGE_INTEL_COMMON_USB_DEBUG if SOUTHBRIDGE_INTEL_I82801GX diff --git a/src/southbridge/intel/i82801ix/Kconfig b/src/southbridge/intel/i82801ix/Kconfig index cd2f76d9b5..836397822a 100644 --- a/src/southbridge/intel/i82801ix/Kconfig +++ b/src/southbridge/intel/i82801ix/Kconfig @@ -23,7 +23,6 @@ config SOUTHBRIDGE_INTEL_I82801IX select SOUTHBRIDGE_INTEL_COMMON_RTC select SOUTHBRIDGE_INTEL_COMMON_RESET select IOAPIC - select HAVE_USBDEBUG select USE_WATCHDOG_ON_BOOT select HAVE_SMI_HANDLER select HAVE_USBDEBUG_OPTIONS @@ -33,6 +32,7 @@ config SOUTHBRIDGE_INTEL_I82801IX select INTEL_DESCRIPTOR_MODE_CAPABLE select ACPI_INTEL_HARDWARE_SLEEP_VALUES select SOUTHBRIDGE_INTEL_COMMON_WATCHDOG + select SOUTHBRIDGE_INTEL_COMMON_USB_DEBUG if SOUTHBRIDGE_INTEL_I82801IX diff --git a/src/southbridge/intel/i82801jx/Kconfig b/src/southbridge/intel/i82801jx/Kconfig index 7f44fcfc1d..161290f852 100644 --- a/src/southbridge/intel/i82801jx/Kconfig +++ b/src/southbridge/intel/i82801jx/Kconfig @@ -24,7 +24,6 @@ config SOUTHBRIDGE_INTEL_I82801JX select SOUTHBRIDGE_INTEL_COMMON_RTC select SOUTHBRIDGE_INTEL_COMMON_RESET select IOAPIC - select HAVE_USBDEBUG select USE_WATCHDOG_ON_BOOT select HAVE_SMI_HANDLER select HAVE_USBDEBUG_OPTIONS @@ -36,6 +35,7 @@ config SOUTHBRIDGE_INTEL_I82801JX select HAVE_POWER_STATE_AFTER_FAILURE select HAVE_POWER_STATE_PREVIOUS_AFTER_FAILURE select SOUTHBRIDGE_INTEL_COMMON_WATCHDOG + select SOUTHBRIDGE_INTEL_COMMON_USB_DEBUG if SOUTHBRIDGE_INTEL_I82801JX diff --git a/src/southbridge/intel/ibexpeak/Kconfig b/src/southbridge/intel/ibexpeak/Kconfig index c84a66d313..f9723fb2d8 100644 --- a/src/southbridge/intel/ibexpeak/Kconfig +++ b/src/southbridge/intel/ibexpeak/Kconfig @@ -22,7 +22,6 @@ config SOUTH_BRIDGE_OPTIONS # dummy def_bool y select ACPI_INTEL_HARDWARE_SLEEP_VALUES select IOAPIC - select HAVE_USBDEBUG select HAVE_SMI_HANDLER select USE_WATCHDOG_ON_BOOT select PCIEXP_ASPM @@ -45,6 +44,7 @@ config SOUTH_BRIDGE_OPTIONS # dummy select HAVE_POWER_STATE_AFTER_FAILURE select HAVE_POWER_STATE_PREVIOUS_AFTER_FAILURE select SOUTHBRIDGE_INTEL_COMMON_WATCHDOG + select SOUTHBRIDGE_INTEL_COMMON_USB_DEBUG config EHCI_BAR hex diff --git a/src/southbridge/intel/lynxpoint/Kconfig b/src/southbridge/intel/lynxpoint/Kconfig index 95b9f625f2..ef071f28ed 100644 --- a/src/southbridge/intel/lynxpoint/Kconfig +++ b/src/southbridge/intel/lynxpoint/Kconfig @@ -45,6 +45,7 @@ config SOUTH_BRIDGE_OPTIONS # dummy select HAVE_POWER_STATE_AFTER_FAILURE select HAVE_POWER_STATE_PREVIOUS_AFTER_FAILURE select SOUTHBRIDGE_INTEL_COMMON_WATCHDOG + select SOUTHBRIDGE_INTEL_COMMON_USB_DEBUG config INTEL_LYNXPOINT_LP bool From 2c43bf7969e5b16f0611ce1686b9f665d87d7f8e Mon Sep 17 00:00:00 2001 From: Arthur Heymans Date: Sat, 16 Nov 2019 12:53:28 +0100 Subject: [PATCH 0218/1242] soc/amd/stoneyridge: Fix building with USBDEBUG Change-Id: I425583377cba8d57acabfd59922f421d1fb5891f Signed-off-by: Arthur Heymans Reviewed-on: https://review.coreboot.org/c/coreboot/+/36883 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber --- src/soc/amd/stoneyridge/enable_usbdebug.c | 1 + 1 file changed, 1 insertion(+) diff --git a/src/soc/amd/stoneyridge/enable_usbdebug.c b/src/soc/amd/stoneyridge/enable_usbdebug.c index 19b9550847..5e623e8ab0 100644 --- a/src/soc/amd/stoneyridge/enable_usbdebug.c +++ b/src/soc/amd/stoneyridge/enable_usbdebug.c @@ -22,6 +22,7 @@ #include #include #include +#include pci_devfn_t pci_ehci_dbg_dev(unsigned int hcd_idx) { From c63649bdbbeddbdb742b4335af0313fc1c3bd552 Mon Sep 17 00:00:00 2001 From: Arthur Heymans Date: Sat, 16 Nov 2019 12:13:03 +0100 Subject: [PATCH 0219/1242] */Makefile: Always build enable_usbdebug.c MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This always builds the usb debug callback functions when implemented. They get garbage collected if CONFIG_USBDEBUG is not set. Change-Id: I33051df583645cd00d08e06774383763172d5822 Signed-off-by: Arthur Heymans Reviewed-on: https://review.coreboot.org/c/coreboot/+/36881 Tested-by: build bot (Jenkins) Reviewed-by: Mike Banon Reviewed-by: Nico Huber Reviewed-by: Kyösti Mälkki --- src/soc/amd/stoneyridge/Makefile.inc | 6 +++--- src/soc/intel/broadwell/Makefile.inc | 6 +++--- src/southbridge/amd/agesa/hudson/Makefile.inc | 6 +++--- src/southbridge/amd/pi/hudson/Makefile.inc | 6 +++--- src/southbridge/amd/sb700/Makefile.inc | 6 +++--- src/southbridge/amd/sb800/Makefile.inc | 6 +++--- src/southbridge/nvidia/ck804/Makefile.inc | 6 +++--- src/southbridge/nvidia/mcp55/Makefile.inc | 6 +++--- 8 files changed, 24 insertions(+), 24 deletions(-) diff --git a/src/soc/amd/stoneyridge/Makefile.inc b/src/soc/amd/stoneyridge/Makefile.inc index 53aabf5d65..b74bc68cc3 100644 --- a/src/soc/amd/stoneyridge/Makefile.inc +++ b/src/soc/amd/stoneyridge/Makefile.inc @@ -42,7 +42,7 @@ bootblock-y += BiosCallOuts.c bootblock-y += bootblock/bootblock.c bootblock-y += gpio.c bootblock-y += i2c.c -bootblock-$(CONFIG_USBDEBUG) += enable_usbdebug.c +bootblock-y += enable_usbdebug.c bootblock-y += monotonic_timer.c bootblock-y += pmutil.c bootblock-y += reset.c @@ -54,7 +54,7 @@ bootblock-$(CONFIG_HAVE_SMI_HANDLER) += smi_util.c romstage-y += BiosCallOuts.c romstage-y += i2c.c romstage-y += romstage.c -romstage-$(CONFIG_USBDEBUG) += enable_usbdebug.c +romstage-y += enable_usbdebug.c romstage-y += gpio.c romstage-y += monotonic_timer.c romstage-y += pmutil.c @@ -89,7 +89,7 @@ ramstage-y += i2c.c ramstage-y += chip.c ramstage-y += cpu.c ramstage-y += mca.c -ramstage-$(CONFIG_USBDEBUG) += enable_usbdebug.c +ramstage-y += enable_usbdebug.c ramstage-$(CONFIG_HAVE_ACPI_TABLES) += acpi.c ramstage-y += gpio.c ramstage-y += monotonic_timer.c diff --git a/src/soc/intel/broadwell/Makefile.inc b/src/soc/intel/broadwell/Makefile.inc index 8f690cc4f6..03aa3fbd08 100644 --- a/src/soc/intel/broadwell/Makefile.inc +++ b/src/soc/intel/broadwell/Makefile.inc @@ -65,9 +65,9 @@ romstage-y += tsc_freq.c smm-y += tsc_freq.c postcar-y += tsc_freq.c verstage-y += tsc_freq.c -bootblock-$(CONFIG_USBDEBUG) += usb_debug.c -romstage-$(CONFIG_USBDEBUG) += usb_debug.c -ramstage-$(CONFIG_USBDEBUG) += usb_debug.c +bootblock-y += usb_debug.c +romstage-y += usb_debug.c +ramstage-y += usb_debug.c ramstage-y += ehci.c ramstage-y += xhci.c smm-y += xhci.c diff --git a/src/southbridge/amd/agesa/hudson/Makefile.inc b/src/southbridge/amd/agesa/hudson/Makefile.inc index cd0a1d53e1..8ad82d2766 100644 --- a/src/southbridge/amd/agesa/hudson/Makefile.inc +++ b/src/southbridge/amd/agesa/hudson/Makefile.inc @@ -17,9 +17,9 @@ ramstage-y += sd.c ramstage-$(CONFIG_HAVE_ACPI_TABLES) += fadt.c ramstage-y += reset.c -bootblock-$(CONFIG_USBDEBUG) += enable_usbdebug.c -romstage-$(CONFIG_USBDEBUG) += enable_usbdebug.c -ramstage-$(CONFIG_USBDEBUG) += enable_usbdebug.c +bootblock-y += enable_usbdebug.c +romstage-y += enable_usbdebug.c +ramstage-y += enable_usbdebug.c romstage-y += early_setup.c ramstage-$(CONFIG_SPI_FLASH) += spi.c diff --git a/src/southbridge/amd/pi/hudson/Makefile.inc b/src/southbridge/amd/pi/hudson/Makefile.inc index 4b4b138214..0eccadb4f9 100644 --- a/src/southbridge/amd/pi/hudson/Makefile.inc +++ b/src/southbridge/amd/pi/hudson/Makefile.inc @@ -28,10 +28,10 @@ # #***************************************************************************** -bootblock-$(CONFIG_USBDEBUG) += enable_usbdebug.c +bootblock-y += enable_usbdebug.c romstage-y += early_setup.c -romstage-$(CONFIG_USBDEBUG) += enable_usbdebug.c +romstage-y += enable_usbdebug.c romstage-$(CONFIG_HUDSON_IMC_FWM) += imc.c romstage-y += smbus.c romstage-y += smbus_spd.c @@ -41,7 +41,7 @@ verstage-y += early_setup.c verstage-y += reset.c verstage-$(CONFIG_HUDSON_UART) += uart.c -ramstage-$(CONFIG_USBDEBUG) += enable_usbdebug.c +ramstage-y += enable_usbdebug.c ramstage-$(CONFIG_HAVE_ACPI_TABLES) += fadt.c ramstage-$(CONFIG_SOUTHBRIDGE_AMD_PI_KERN) += gpio.c ramstage-y += hda.c diff --git a/src/southbridge/amd/sb700/Makefile.inc b/src/southbridge/amd/sb700/Makefile.inc index 17d0a3abc0..0a20a8c8b3 100644 --- a/src/southbridge/amd/sb700/Makefile.inc +++ b/src/southbridge/amd/sb700/Makefile.inc @@ -14,9 +14,9 @@ romstage-y += reset.c ramstage-y += reset.c ramstage-y += spi.c -bootblock-$(CONFIG_USBDEBUG) += enable_usbdebug.c -romstage-$(CONFIG_USBDEBUG) += enable_usbdebug.c -ramstage-$(CONFIG_USBDEBUG) += enable_usbdebug.c +bootblock-y += enable_usbdebug.c +romstage-y += enable_usbdebug.c +ramstage-y += enable_usbdebug.c romstage-y += early_setup.c romstage-y += smbus.c diff --git a/src/southbridge/amd/sb800/Makefile.inc b/src/southbridge/amd/sb800/Makefile.inc index fd2577ce39..276ca29acd 100644 --- a/src/southbridge/amd/sb800/Makefile.inc +++ b/src/southbridge/amd/sb800/Makefile.inc @@ -12,9 +12,9 @@ ramstage-y += pcie.c ramstage-$(CONFIG_HAVE_ACPI_TABLES) += fadt.c ramstage-y += reset.c -bootblock-$(CONFIG_USBDEBUG) += enable_usbdebug.c -romstage-$(CONFIG_USBDEBUG) += enable_usbdebug.c -ramstage-$(CONFIG_USBDEBUG) += enable_usbdebug.c +bootblock-y += enable_usbdebug.c +romstage-y += enable_usbdebug.c +ramstage-y += enable_usbdebug.c romstage-y += ramtop.c ramstage-y += ramtop.c diff --git a/src/southbridge/nvidia/ck804/Makefile.inc b/src/southbridge/nvidia/ck804/Makefile.inc index 68495c5f1b..e74c70b180 100644 --- a/src/southbridge/nvidia/ck804/Makefile.inc +++ b/src/southbridge/nvidia/ck804/Makefile.inc @@ -17,9 +17,9 @@ ramstage-y += reset.c ramstage-$(CONFIG_HAVE_ACPI_TABLES) += fadt.c -bootblock-$(CONFIG_USBDEBUG) += enable_usbdebug.c -romstage-$(CONFIG_USBDEBUG) += enable_usbdebug.c -ramstage-$(CONFIG_USBDEBUG) += enable_usbdebug.c +bootblock-y += enable_usbdebug.c +romstage-y += enable_usbdebug.c +ramstage-y += enable_usbdebug.c romstage-y += early_smbus.c bootblock-y += romstrap.ld diff --git a/src/southbridge/nvidia/mcp55/Makefile.inc b/src/southbridge/nvidia/mcp55/Makefile.inc index db0b3100ec..d9c4134453 100644 --- a/src/southbridge/nvidia/mcp55/Makefile.inc +++ b/src/southbridge/nvidia/mcp55/Makefile.inc @@ -17,9 +17,9 @@ ramstage-$(CONFIG_HAVE_ACPI_TABLES) += fadt.c ramstage-y += reset.c -bootblock-$(CONFIG_USBDEBUG) += enable_usbdebug.c -romstage-$(CONFIG_USBDEBUG) += enable_usbdebug.c -ramstage-$(CONFIG_USBDEBUG) += enable_usbdebug.c +bootblock-y += enable_usbdebug.c +romstage-y += enable_usbdebug.c +ramstage-y += enable_usbdebug.c romstage-y += early_smbus.c romstage-y += early_ctrl.c From 1e245c1536b6748ba706ac38204b5d5f9b8a7510 Mon Sep 17 00:00:00 2001 From: Nico Huber Date: Mon, 18 Nov 2019 01:10:14 +0100 Subject: [PATCH 0220/1242] Documentation/releases: Add more c-env-bb platforms for 4.11 Change-Id: Ie5c83befc8e595016c63729a19e7e71438c996b5 Signed-off-by: Nico Huber Reviewed-on: https://review.coreboot.org/c/coreboot/+/36919 Tested-by: build bot (Jenkins) Reviewed-by: HAOUAS Elyes --- Documentation/releases/coreboot-4.11-relnotes.md | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/releases/coreboot-4.11-relnotes.md b/Documentation/releases/coreboot-4.11-relnotes.md index b4515ffb9f..505a9cca1a 100644 --- a/Documentation/releases/coreboot-4.11-relnotes.md +++ b/Documentation/releases/coreboot-4.11-relnotes.md @@ -94,6 +94,8 @@ UPPER CASE commands and libpayload knows how to deal with USB3 hubs. * intel/nehalem ### Moved the following platforms to C_ENVIRONMENT_BOOTBLOCK: +* intel/i945 +* intel/x4x * intel/gm45 * intel/nehalem * intel/braswell From 934b8da442a04978c6320299c616d3e8f05cb731 Mon Sep 17 00:00:00 2001 From: Nico Huber Date: Mon, 18 Nov 2019 01:23:18 +0100 Subject: [PATCH 0221/1242] Documentation/releases: Add libgfxinit changes in 4.11 Change-Id: Id7babdc9b1d908fa90ebac098a019615fa00b973 Signed-off-by: Nico Huber Reviewed-on: https://review.coreboot.org/c/coreboot/+/36920 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi --- Documentation/releases/coreboot-4.11-relnotes.md | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/Documentation/releases/coreboot-4.11-relnotes.md b/Documentation/releases/coreboot-4.11-relnotes.md index 505a9cca1a..fa0da77a68 100644 --- a/Documentation/releases/coreboot-4.11-relnotes.md +++ b/Documentation/releases/coreboot-4.11-relnotes.md @@ -100,6 +100,19 @@ UPPER CASE commands and libpayload knows how to deal with USB3 hubs. * intel/nehalem * intel/braswell +### libgfxinit ### + +Most notable, dynamic CDClk configuration was added to libgfxinit, +to support higher resolution displays without changes in the static +configuration. It also received some fixes for better DP and eDP +compatibility, better error recovery for Intel's fickle GMBus and +updated platform support: +* Correct HDMI clock limit for G45. +* DP support for Ibex Peak (Ironlake graphics). +* Fixed scaling on eDP for Broadwell. +* Support for ULX variants of Haswell and later. +* Support for Kaby, Amber, Coffee and Whiskey Lake. + ### Other * Did cleanups around TSC timer * Improved automatic VR configuration on SKL/KBL From 9c538348d8ccaef2c3dd6b898a1f44b00ea59690 Mon Sep 17 00:00:00 2001 From: Arthur Heymans Date: Tue, 12 Nov 2019 16:42:33 +0100 Subject: [PATCH 0222/1242] nb/intel/sandybridge: Make the mainboard_rcba_config hook optional This also changes the name to mainboard_late_rcba_config to better reflect what it does. This adds an empty weakly linked default. The rationale behind this change is that without an implementation of the hook some features might not work but that the result is likely still able to boot, so it can be made optional. Change-Id: I1897d0f5ca7427d304a425f5256cd43c088ff936 Signed-off-by: Arthur Heymans Reviewed-on: https://review.coreboot.org/c/coreboot/+/36781 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber --- src/mainboard/apple/macbookair4_2/romstage.c | 2 +- src/mainboard/asrock/b75pro3-m/romstage.c | 4 ---- src/mainboard/asus/h61m-cs/romstage.c | 4 ---- src/mainboard/asus/maximus_iv_gene-z/romstage.c | 4 ---- src/mainboard/asus/p8h61-m_lx/romstage.c | 4 ---- src/mainboard/asus/p8h61-m_pro/romstage.c | 4 ---- src/mainboard/asus/p8z77-m_pro/romstage.c | 4 ---- src/mainboard/compulab/intense_pc/romstage.c | 2 +- src/mainboard/gigabyte/ga-b75m-d3h/romstage.c | 2 +- src/mainboard/gigabyte/ga-h61m-s2pv/romstage.c | 4 ---- src/mainboard/google/butterfly/romstage.c | 2 +- src/mainboard/google/link/romstage.c | 2 +- src/mainboard/google/parrot/romstage.c | 2 +- src/mainboard/google/stout/romstage.c | 2 +- src/mainboard/hp/2570p/romstage.c | 4 ---- src/mainboard/hp/2760p/romstage.c | 4 ---- src/mainboard/hp/8460p/romstage.c | 4 ---- src/mainboard/hp/8470p/romstage.c | 4 ---- src/mainboard/hp/8770w/romstage.c | 4 ---- src/mainboard/hp/compaq_8200_elite_sff/romstage.c | 4 ---- src/mainboard/hp/folio_9470m/romstage.c | 4 ---- src/mainboard/hp/revolve_810_g1/romstage.c | 2 +- src/mainboard/hp/z220_sff_workstation/romstage.c | 4 ---- src/mainboard/intel/dcp847ske/early_southbridge.c | 2 +- src/mainboard/intel/emeraldlake2/romstage.c | 5 ----- src/mainboard/kontron/ktqm77/romstage.c | 2 +- src/mainboard/lenovo/l520/romstage.c | 4 ---- src/mainboard/lenovo/s230u/romstage.c | 2 +- src/mainboard/lenovo/t420/romstage.c | 4 ---- src/mainboard/lenovo/t420s/romstage.c | 4 ---- src/mainboard/lenovo/t430/romstage.c | 4 ---- src/mainboard/lenovo/t430s/romstage.c | 4 ---- src/mainboard/lenovo/t520/romstage.c | 4 ---- src/mainboard/lenovo/t530/romstage.c | 4 ---- src/mainboard/lenovo/x131e/romstage.c | 4 ---- src/mainboard/lenovo/x1_carbon_gen1/romstage.c | 4 ---- src/mainboard/lenovo/x220/romstage.c | 4 ---- src/mainboard/lenovo/x230/romstage.c | 4 ---- src/mainboard/msi/ms7707/romstage.c | 4 ---- src/mainboard/roda/rv11/romstage.c | 2 +- src/mainboard/samsung/lumpy/romstage.c | 2 +- src/mainboard/samsung/stumpy/romstage.c | 2 +- src/mainboard/sapphire/pureplatinumh61/romstage.c | 2 +- src/northbridge/intel/sandybridge/romstage.c | 6 +++++- src/southbridge/intel/bd82x6x/pch.h | 4 +++- 45 files changed, 23 insertions(+), 130 deletions(-) diff --git a/src/mainboard/apple/macbookair4_2/romstage.c b/src/mainboard/apple/macbookair4_2/romstage.c index a7c543dd49..5522ea013e 100644 --- a/src/mainboard/apple/macbookair4_2/romstage.c +++ b/src/mainboard/apple/macbookair4_2/romstage.c @@ -27,7 +27,7 @@ void pch_enable_lpc(void) pci_write_config32(PCI_DEV(0, 0x1f, 0), 0xac, 0x80000000); } -void mainboard_rcba_config(void) +void mainboard_late_rcba_config(void) { /* Disable devices. */ RCBA32(0x3414) = 0x00000020; diff --git a/src/mainboard/asrock/b75pro3-m/romstage.c b/src/mainboard/asrock/b75pro3-m/romstage.c index fe6d1833d2..fe1416b908 100644 --- a/src/mainboard/asrock/b75pro3-m/romstage.c +++ b/src/mainboard/asrock/b75pro3-m/romstage.c @@ -27,10 +27,6 @@ void pch_enable_lpc(void) { } -void mainboard_rcba_config(void) -{ -} - const struct southbridge_usb_port mainboard_usb_ports[] = { { 1, 0, 0 }, { 1, 0, 0 }, diff --git a/src/mainboard/asus/h61m-cs/romstage.c b/src/mainboard/asus/h61m-cs/romstage.c index 37b07e51d9..4c8eda74fe 100644 --- a/src/mainboard/asus/h61m-cs/romstage.c +++ b/src/mainboard/asus/h61m-cs/romstage.c @@ -31,10 +31,6 @@ void pch_enable_lpc(void) { } -void mainboard_rcba_config(void) -{ -} - const struct southbridge_usb_port mainboard_usb_ports[] = { { 1, 0, 0 }, { 1, 0, 0 }, diff --git a/src/mainboard/asus/maximus_iv_gene-z/romstage.c b/src/mainboard/asus/maximus_iv_gene-z/romstage.c index 6cf206b47c..e29dd0f160 100644 --- a/src/mainboard/asus/maximus_iv_gene-z/romstage.c +++ b/src/mainboard/asus/maximus_iv_gene-z/romstage.c @@ -44,10 +44,6 @@ void pch_enable_lpc(void) { } -void mainboard_rcba_config(void) -{ -} - void mainboard_config_superio(void) { static const pnp_devfn_t GLOBAL_PSEUDO_DEV = PNP_DEV(0x2e, 0); diff --git a/src/mainboard/asus/p8h61-m_lx/romstage.c b/src/mainboard/asus/p8h61-m_lx/romstage.c index 5f94d17cf4..01ae6030ad 100644 --- a/src/mainboard/asus/p8h61-m_lx/romstage.c +++ b/src/mainboard/asus/p8h61-m_lx/romstage.c @@ -47,10 +47,6 @@ void pch_enable_lpc(void) CNF1_LPC_EN | KBC_LPC_EN | LPT_LPC_EN | COMA_LPC_EN); } -void mainboard_rcba_config(void) -{ -} - void mainboard_config_superio(void) { nuvoton_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); diff --git a/src/mainboard/asus/p8h61-m_pro/romstage.c b/src/mainboard/asus/p8h61-m_pro/romstage.c index 60d311d98c..3736ab6b65 100644 --- a/src/mainboard/asus/p8h61-m_pro/romstage.c +++ b/src/mainboard/asus/p8h61-m_pro/romstage.c @@ -32,10 +32,6 @@ void pch_enable_lpc(void) KBC_LPC_EN | LPT_LPC_EN | COMA_LPC_EN); } -void mainboard_rcba_config(void) -{ -} - const struct southbridge_usb_port mainboard_usb_ports[] = { { 1, 0, 0 }, { 1, 0, 0 }, diff --git a/src/mainboard/asus/p8z77-m_pro/romstage.c b/src/mainboard/asus/p8z77-m_pro/romstage.c index db2d303e8c..5fff2e143c 100644 --- a/src/mainboard/asus/p8z77-m_pro/romstage.c +++ b/src/mainboard/asus/p8z77-m_pro/romstage.c @@ -34,10 +34,6 @@ void pch_enable_lpc(void) { } -void mainboard_rcba_config(void) -{ -} - const struct southbridge_usb_port mainboard_usb_ports[] = { /* {enable, current, oc_pin} */ { 1, 2, 0 }, /* Port 0: USB3 front internal header, top */ diff --git a/src/mainboard/compulab/intense_pc/romstage.c b/src/mainboard/compulab/intense_pc/romstage.c index 8198d8af6e..f44a7e8edd 100644 --- a/src/mainboard/compulab/intense_pc/romstage.c +++ b/src/mainboard/compulab/intense_pc/romstage.c @@ -39,7 +39,7 @@ void pch_enable_lpc(void) #endif } -void mainboard_rcba_config(void) +void mainboard_late_rcba_config(void) { RCBA32(0x3414) = 0x00000000; } diff --git a/src/mainboard/gigabyte/ga-b75m-d3h/romstage.c b/src/mainboard/gigabyte/ga-b75m-d3h/romstage.c index f67d51b8be..25e1d0385e 100644 --- a/src/mainboard/gigabyte/ga-b75m-d3h/romstage.c +++ b/src/mainboard/gigabyte/ga-b75m-d3h/romstage.c @@ -87,7 +87,7 @@ void mainboard_get_spd(spd_raw_data *spd, bool id_only) read_spd(&spd[3], 0x53, id_only); } -void mainboard_rcba_config(void) +void mainboard_late_rcba_config(void) { /* Enable HECI */ RCBA32(FD2) &= ~0x2; diff --git a/src/mainboard/gigabyte/ga-h61m-s2pv/romstage.c b/src/mainboard/gigabyte/ga-h61m-s2pv/romstage.c index 1df5bfd80c..57cc0706d9 100644 --- a/src/mainboard/gigabyte/ga-h61m-s2pv/romstage.c +++ b/src/mainboard/gigabyte/ga-h61m-s2pv/romstage.c @@ -27,10 +27,6 @@ void pch_enable_lpc(void) { } -void mainboard_rcba_config(void) -{ -} - const struct southbridge_usb_port mainboard_usb_ports[] = { { 1, 0, 0 }, { 1, 0, 0 }, diff --git a/src/mainboard/google/butterfly/romstage.c b/src/mainboard/google/butterfly/romstage.c index 449ccf507e..3aef9d0a09 100644 --- a/src/mainboard/google/butterfly/romstage.c +++ b/src/mainboard/google/butterfly/romstage.c @@ -35,7 +35,7 @@ void pch_enable_lpc(void) pci_write_config16(PCH_LPC_DEV, LPC_EN, KBC_LPC_EN | MC_LPC_EN); } -void mainboard_rcba_config(void) +void mainboard_late_rcba_config(void) { u32 reg32; diff --git a/src/mainboard/google/link/romstage.c b/src/mainboard/google/link/romstage.c index d42572b632..628e2a0052 100644 --- a/src/mainboard/google/link/romstage.c +++ b/src/mainboard/google/link/romstage.c @@ -39,7 +39,7 @@ void pch_enable_lpc(void) GAMEL_LPC_EN | COMA_LPC_EN); } -void mainboard_rcba_config(void) +void mainboard_late_rcba_config(void) { /* * GFX INTA -> PIRQA (MSI) diff --git a/src/mainboard/google/parrot/romstage.c b/src/mainboard/google/parrot/romstage.c index 8893819446..604cf7b284 100644 --- a/src/mainboard/google/parrot/romstage.c +++ b/src/mainboard/google/parrot/romstage.c @@ -30,7 +30,7 @@ void pch_enable_lpc(void) { } -void mainboard_rcba_config(void) +void mainboard_late_rcba_config(void) { u32 reg32; diff --git a/src/mainboard/google/stout/romstage.c b/src/mainboard/google/stout/romstage.c index 6690c6863c..cbbae2ee07 100644 --- a/src/mainboard/google/stout/romstage.c +++ b/src/mainboard/google/stout/romstage.c @@ -43,7 +43,7 @@ void pch_enable_lpc(void) CNF1_LPC_EN | FDD_LPC_EN); } -void mainboard_rcba_config(void) +void mainboard_late_rcba_config(void) { u32 reg32; diff --git a/src/mainboard/hp/2570p/romstage.c b/src/mainboard/hp/2570p/romstage.c index 4f7ca3a18c..8d36f6b27d 100644 --- a/src/mainboard/hp/2570p/romstage.c +++ b/src/mainboard/hp/2570p/romstage.c @@ -24,10 +24,6 @@ void pch_enable_lpc(void) { } -void mainboard_rcba_config(void) -{ -} - const struct southbridge_usb_port mainboard_usb_ports[] = { { 1, 1, 0 }, { 0, 1, 0 }, diff --git a/src/mainboard/hp/2760p/romstage.c b/src/mainboard/hp/2760p/romstage.c index a696faec36..5bf8789618 100644 --- a/src/mainboard/hp/2760p/romstage.c +++ b/src/mainboard/hp/2760p/romstage.c @@ -23,10 +23,6 @@ void pch_enable_lpc(void) { } -void mainboard_rcba_config(void) -{ -} - const struct southbridge_usb_port mainboard_usb_ports[] = { { 1, 1, 0 }, { 1, 1, 0 }, diff --git a/src/mainboard/hp/8460p/romstage.c b/src/mainboard/hp/8460p/romstage.c index 77c355bb23..397810eba7 100644 --- a/src/mainboard/hp/8460p/romstage.c +++ b/src/mainboard/hp/8460p/romstage.c @@ -27,10 +27,6 @@ void pch_enable_lpc(void) { } -void mainboard_rcba_config(void) -{ -} - const struct southbridge_usb_port mainboard_usb_ports[] = { { 1, 1, 0 }, /* USB0, eSATA */ { 1, 0, 0 }, /* USB charger */ diff --git a/src/mainboard/hp/8470p/romstage.c b/src/mainboard/hp/8470p/romstage.c index 890e65b07c..513b3756e8 100644 --- a/src/mainboard/hp/8470p/romstage.c +++ b/src/mainboard/hp/8470p/romstage.c @@ -26,10 +26,6 @@ void pch_enable_lpc(void) { } -void mainboard_rcba_config(void) -{ -} - const struct southbridge_usb_port mainboard_usb_ports[] = { { 1, 1, 0 }, { 1, 1, 0 }, diff --git a/src/mainboard/hp/8770w/romstage.c b/src/mainboard/hp/8770w/romstage.c index 49a5b1af48..d3034fb565 100644 --- a/src/mainboard/hp/8770w/romstage.c +++ b/src/mainboard/hp/8770w/romstage.c @@ -27,10 +27,6 @@ void pch_enable_lpc(void) { } -void mainboard_rcba_config(void) -{ -} - const struct southbridge_usb_port mainboard_usb_ports[] = { { 1, 1, 0 }, /* Dock USB3.0 */ { 1, 1, 0 }, /* Conn */ diff --git a/src/mainboard/hp/compaq_8200_elite_sff/romstage.c b/src/mainboard/hp/compaq_8200_elite_sff/romstage.c index 90cfcc93aa..3e726cfb80 100644 --- a/src/mainboard/hp/compaq_8200_elite_sff/romstage.c +++ b/src/mainboard/hp/compaq_8200_elite_sff/romstage.c @@ -31,10 +31,6 @@ void pch_enable_lpc(void) { } -void mainboard_rcba_config(void) -{ -} - const struct southbridge_usb_port mainboard_usb_ports[] = { { 1, 0, -1 }, { 1, 0, -1 }, diff --git a/src/mainboard/hp/folio_9470m/romstage.c b/src/mainboard/hp/folio_9470m/romstage.c index 3f174a19fb..969b666d8f 100644 --- a/src/mainboard/hp/folio_9470m/romstage.c +++ b/src/mainboard/hp/folio_9470m/romstage.c @@ -25,10 +25,6 @@ void pch_enable_lpc(void) { } -void mainboard_rcba_config(void) -{ -} - const struct southbridge_usb_port mainboard_usb_ports[] = { { 1, 1, 0 }, /* SSP1: dock */ { 1, 1, 0 }, /* SSP2: left, EHCI Debug */ diff --git a/src/mainboard/hp/revolve_810_g1/romstage.c b/src/mainboard/hp/revolve_810_g1/romstage.c index 8a40578f0a..844bb2f4e3 100644 --- a/src/mainboard/hp/revolve_810_g1/romstage.c +++ b/src/mainboard/hp/revolve_810_g1/romstage.c @@ -28,7 +28,7 @@ void pch_enable_lpc(void) { } -void mainboard_rcba_config(void) +void mainboard_late_rcba_config(void) { RCBA32(BUC) = 0x00000000; } diff --git a/src/mainboard/hp/z220_sff_workstation/romstage.c b/src/mainboard/hp/z220_sff_workstation/romstage.c index bd0a377580..2e0a50806c 100644 --- a/src/mainboard/hp/z220_sff_workstation/romstage.c +++ b/src/mainboard/hp/z220_sff_workstation/romstage.c @@ -31,10 +31,6 @@ void pch_enable_lpc(void) { } -void mainboard_rcba_config(void) -{ -} - const struct southbridge_usb_port mainboard_usb_ports[] = { { 1, 0, 0 }, { 1, 0, 0 }, diff --git a/src/mainboard/intel/dcp847ske/early_southbridge.c b/src/mainboard/intel/dcp847ske/early_southbridge.c index 7f3a58d0f2..1cd58b0ba5 100644 --- a/src/mainboard/intel/dcp847ske/early_southbridge.c +++ b/src/mainboard/intel/dcp847ske/early_southbridge.c @@ -31,7 +31,7 @@ void pch_enable_lpc(void) { } -void mainboard_rcba_config(void) +void mainboard_late_rcba_config(void) { /* Disable devices */ RCBA32(FD) |= PCH_DISABLE_P2P | PCH_DISABLE_XHCI; diff --git a/src/mainboard/intel/emeraldlake2/romstage.c b/src/mainboard/intel/emeraldlake2/romstage.c index e7959ef32f..16a16de33f 100644 --- a/src/mainboard/intel/emeraldlake2/romstage.c +++ b/src/mainboard/intel/emeraldlake2/romstage.c @@ -43,11 +43,6 @@ void pch_enable_lpc(void) } } -void mainboard_rcba_config(void) -{ - southbridge_configure_default_intmap(); -} - void mainboard_config_superio(void) { const u16 port = SIO_PORT; diff --git a/src/mainboard/kontron/ktqm77/romstage.c b/src/mainboard/kontron/ktqm77/romstage.c index f778f96432..37713e1657 100644 --- a/src/mainboard/kontron/ktqm77/romstage.c +++ b/src/mainboard/kontron/ktqm77/romstage.c @@ -43,7 +43,7 @@ void pch_enable_lpc(void) COMA_LPC_EN | COMB_LPC_EN); } -void mainboard_rcba_config(void) +void mainboard_late_rcba_config(void) { u32 reg32; diff --git a/src/mainboard/lenovo/l520/romstage.c b/src/mainboard/lenovo/l520/romstage.c index fc67e5adcf..37182f855d 100644 --- a/src/mainboard/lenovo/l520/romstage.c +++ b/src/mainboard/lenovo/l520/romstage.c @@ -26,10 +26,6 @@ void pch_enable_lpc(void) { } -void mainboard_rcba_config(void) -{ -} - const struct southbridge_usb_port mainboard_usb_ports[] = { { 1, 0, -1 }, { 1, 0, -1 }, diff --git a/src/mainboard/lenovo/s230u/romstage.c b/src/mainboard/lenovo/s230u/romstage.c index 48d26c2519..ee1d0ed19c 100644 --- a/src/mainboard/lenovo/s230u/romstage.c +++ b/src/mainboard/lenovo/s230u/romstage.c @@ -42,7 +42,7 @@ void pch_enable_lpc(void) ec_mm_set_bit(0x3b, 4); } -void mainboard_rcba_config(void) +void mainboard_late_rcba_config(void) { /* Disable devices. */ RCBA32(BUC) = 0x00000020; diff --git a/src/mainboard/lenovo/t420/romstage.c b/src/mainboard/lenovo/t420/romstage.c index e7851f3edb..7036ec40fe 100644 --- a/src/mainboard/lenovo/t420/romstage.c +++ b/src/mainboard/lenovo/t420/romstage.c @@ -54,10 +54,6 @@ void pch_enable_lpc(void) pci_write_config32(PCH_LPC_DEV, ETR3, 0x10000); } -void mainboard_rcba_config(void) -{ -} - // OC3 set in bios to port 2-7, OC7 set in bios to port 10-13 const struct southbridge_usb_port mainboard_usb_ports[] = { { 1, 1, 0 }, /* P0: system port 4, OC0 */ diff --git a/src/mainboard/lenovo/t420s/romstage.c b/src/mainboard/lenovo/t420s/romstage.c index 72cbcad245..7b97ff7e75 100644 --- a/src/mainboard/lenovo/t420s/romstage.c +++ b/src/mainboard/lenovo/t420s/romstage.c @@ -54,10 +54,6 @@ void pch_enable_lpc(void) pci_write_config32(PCH_LPC_DEV, ETR3, 0x10000); } -void mainboard_rcba_config(void) -{ -} - const struct southbridge_usb_port mainboard_usb_ports[] = { { 0, 1, -1 }, /* P0 empty */ { 1, 1, 1 }, /* P1 system port 2 (To system port) (EHCI debug), OC 1 */ diff --git a/src/mainboard/lenovo/t430/romstage.c b/src/mainboard/lenovo/t430/romstage.c index 3caa443fe9..0cff5d2b59 100644 --- a/src/mainboard/lenovo/t430/romstage.c +++ b/src/mainboard/lenovo/t430/romstage.c @@ -53,10 +53,6 @@ void pch_enable_lpc(void) { } -void mainboard_rcba_config(void) -{ -} - /* FIXME: used T530 values here */ const struct southbridge_usb_port mainboard_usb_ports[] = { { 1, 1, 0 }, diff --git a/src/mainboard/lenovo/t430s/romstage.c b/src/mainboard/lenovo/t430s/romstage.c index 34793d1301..298673b5dd 100644 --- a/src/mainboard/lenovo/t430s/romstage.c +++ b/src/mainboard/lenovo/t430s/romstage.c @@ -24,10 +24,6 @@ void pch_enable_lpc(void) pci_write_config32(PCH_LPC_DEV, ETR3, 0x10000); } -void mainboard_rcba_config(void) -{ -} - void mainboard_config_superio(void) { } diff --git a/src/mainboard/lenovo/t520/romstage.c b/src/mainboard/lenovo/t520/romstage.c index 75e331e6d4..52898faa45 100644 --- a/src/mainboard/lenovo/t520/romstage.c +++ b/src/mainboard/lenovo/t520/romstage.c @@ -56,10 +56,6 @@ void pch_enable_lpc(void) pci_write_config32(PCH_LPC_DEV, ETR3, 0x10000); } -void mainboard_rcba_config(void) -{ -} - const struct southbridge_usb_port mainboard_usb_ports[] = { { 1, 1, 0 }, /* P0 left dual conn, OC 0 */ { 1, 1, 1 }, /* P1 system onboard USB (eSATA), (EHCI debug), OC 1 */ diff --git a/src/mainboard/lenovo/t530/romstage.c b/src/mainboard/lenovo/t530/romstage.c index cb17a27dda..e0b0455c75 100644 --- a/src/mainboard/lenovo/t530/romstage.c +++ b/src/mainboard/lenovo/t530/romstage.c @@ -56,10 +56,6 @@ void pch_enable_lpc(void) pci_write_config32(PCH_LPC_DEV, ETR3, 0x10000); } -void mainboard_rcba_config(void) -{ -} - void mainboard_early_init(int s3resume) { hybrid_graphics_init(); diff --git a/src/mainboard/lenovo/x131e/romstage.c b/src/mainboard/lenovo/x131e/romstage.c index 6f176c78f7..a1d3e88ad7 100644 --- a/src/mainboard/lenovo/x131e/romstage.c +++ b/src/mainboard/lenovo/x131e/romstage.c @@ -24,10 +24,6 @@ void pch_enable_lpc(void) { } -void mainboard_rcba_config(void) -{ -} - const struct southbridge_usb_port mainboard_usb_ports[] = { {1, 1, 0}, /* P0: USB 3.0 1 (OC0) */ {1, 1, 0}, /* P1: USB 3.0 2 (OC0) */ diff --git a/src/mainboard/lenovo/x1_carbon_gen1/romstage.c b/src/mainboard/lenovo/x1_carbon_gen1/romstage.c index eb2a5b19f5..f4d2a3c70a 100644 --- a/src/mainboard/lenovo/x1_carbon_gen1/romstage.c +++ b/src/mainboard/lenovo/x1_carbon_gen1/romstage.c @@ -68,10 +68,6 @@ static uint8_t *get_spd_data(int spd_index) return spd_file + spd_index * 256; } -void mainboard_rcba_config(void) -{ -} - void mainboard_get_spd(spd_raw_data *spd, bool id_only) { uint8_t *memory; diff --git a/src/mainboard/lenovo/x220/romstage.c b/src/mainboard/lenovo/x220/romstage.c index 8460208ddb..7989fd6298 100644 --- a/src/mainboard/lenovo/x220/romstage.c +++ b/src/mainboard/lenovo/x220/romstage.c @@ -32,10 +32,6 @@ void pch_enable_lpc(void) pci_write_config32(PCH_LPC_DEV, ETR3, 0x10000); } -void mainboard_rcba_config(void) -{ -} - void mainboard_fill_pei_data(struct pei_data *pei_data) { struct pei_data pei_data_template = { diff --git a/src/mainboard/lenovo/x230/romstage.c b/src/mainboard/lenovo/x230/romstage.c index 6f1013567b..3e9ea2c371 100644 --- a/src/mainboard/lenovo/x230/romstage.c +++ b/src/mainboard/lenovo/x230/romstage.c @@ -29,10 +29,6 @@ void pch_enable_lpc(void) pci_write_config32(PCH_LPC_DEV, ETR3, 0x10000); } -void mainboard_rcba_config(void) -{ -} - const struct southbridge_usb_port mainboard_usb_ports[] = { { 1, 0, 0 }, /* P0 (left, fan side), OC 0 */ { 1, 0, 1 }, /* P1 (left touchpad side), OC 1 */ diff --git a/src/mainboard/msi/ms7707/romstage.c b/src/mainboard/msi/ms7707/romstage.c index 8f83c8684c..399d44b2a4 100644 --- a/src/mainboard/msi/ms7707/romstage.c +++ b/src/mainboard/msi/ms7707/romstage.c @@ -28,10 +28,6 @@ void pch_enable_lpc(void) pci_write_config16(PCI_DEV(0, 0x1f, 0), 0xa4, reg16); } -void mainboard_rcba_config(void) -{ -} - const struct southbridge_usb_port mainboard_usb_ports[] = { {1, 0, 0}, {1, 0, 0}, diff --git a/src/mainboard/roda/rv11/romstage.c b/src/mainboard/roda/rv11/romstage.c index a54a9ad6ce..f1681384a8 100644 --- a/src/mainboard/roda/rv11/romstage.c +++ b/src/mainboard/roda/rv11/romstage.c @@ -16,7 +16,7 @@ #include #include -void mainboard_rcba_config(void) +void mainboard_late_rcba_config(void) { u32 reg32; diff --git a/src/mainboard/samsung/lumpy/romstage.c b/src/mainboard/samsung/lumpy/romstage.c index d4b6dd834b..ddcf2ad9e6 100644 --- a/src/mainboard/samsung/lumpy/romstage.c +++ b/src/mainboard/samsung/lumpy/romstage.c @@ -51,7 +51,7 @@ void pch_enable_lpc(void) #endif } -void mainboard_rcba_config(void) +void mainboard_late_rcba_config(void) { /* * GFX INTA -> PIRQA (MSI) diff --git a/src/mainboard/samsung/stumpy/romstage.c b/src/mainboard/samsung/stumpy/romstage.c index 77fd16016d..06659978e5 100644 --- a/src/mainboard/samsung/stumpy/romstage.c +++ b/src/mainboard/samsung/stumpy/romstage.c @@ -62,7 +62,7 @@ void pch_enable_lpc(void) #endif } -void mainboard_rcba_config(void) +void mainboard_late_rcba_config(void) { /* * GFX INTA -> PIRQA (MSI) diff --git a/src/mainboard/sapphire/pureplatinumh61/romstage.c b/src/mainboard/sapphire/pureplatinumh61/romstage.c index 7fcde773b1..3c9cc829d7 100644 --- a/src/mainboard/sapphire/pureplatinumh61/romstage.c +++ b/src/mainboard/sapphire/pureplatinumh61/romstage.c @@ -26,7 +26,7 @@ void pch_enable_lpc(void) pci_write_config32(PCI_DEV(0, 0x1f, 0), 0xac, 0x00010000); } -void mainboard_rcba_config(void) +void mainboard_late_rcba_config(void) { /* Disable devices. */ RCBA32(0x3414) = 0x00000020; diff --git a/src/northbridge/intel/sandybridge/romstage.c b/src/northbridge/intel/sandybridge/romstage.c index 92882b4b61..c76d2f4f4a 100644 --- a/src/northbridge/intel/sandybridge/romstage.c +++ b/src/northbridge/intel/sandybridge/romstage.c @@ -34,6 +34,10 @@ __weak void mainboard_early_init(int s3_resume) { } +__weak void mainboard_late_rcba_config(void) +{ +} + static void early_pch_reset_pmcon(void) { u8 reg8; @@ -100,7 +104,7 @@ void mainboard_romstage_entry(void) southbridge_configure_default_intmap(); southbridge_rcba_config(); - mainboard_rcba_config(); + mainboard_late_rcba_config(); post_code(0x3d); diff --git a/src/southbridge/intel/bd82x6x/pch.h b/src/southbridge/intel/bd82x6x/pch.h index ac976c2982..d4cd86eaa5 100644 --- a/src/southbridge/intel/bd82x6x/pch.h +++ b/src/southbridge/intel/bd82x6x/pch.h @@ -72,7 +72,9 @@ int smbus_read_byte(unsigned int device, unsigned int address); void early_thermal_init(void); void southbridge_configure_default_intmap(void); void southbridge_rcba_config(void); -void mainboard_rcba_config(void); +/* Optional mainboard hook to do additional configuration + on the RCBA config space. It is called after the raminit. */ +void mainboard_late_rcba_config(void); void early_pch_init_native(void); void early_pch_init(void); void early_pch_init_native_dmi_pre(void); From 2b28a160618018b4d7b7930362e1088c2313901b Mon Sep 17 00:00:00 2001 From: Arthur Heymans Date: Tue, 12 Nov 2019 17:21:08 +0100 Subject: [PATCH 0223/1242] sb/intel/bd82x6x: Make the pch_enable_lpc hook optional This also changes the name to mainboard_pch_lpc_setup to better reflect that it is an optional mainboard hook. This adds an empty weakly linked default. The rationale behind this change is that without an implementation of the hook some features might not work but that the result is likely still able to boot, so it can be made optional. Change-Id: Ie8e6056b4c4aed3739d2d12b4224de36fe217189 Signed-off-by: Arthur Heymans Reviewed-on: https://review.coreboot.org/c/coreboot/+/36782 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber --- src/mainboard/apple/macbookair4_2/romstage.c | 2 +- src/mainboard/asrock/b75pro3-m/romstage.c | 4 ---- src/mainboard/asus/h61m-cs/romstage.c | 4 ---- src/mainboard/asus/maximus_iv_gene-z/romstage.c | 4 ---- src/mainboard/asus/p8h61-m_lx/romstage.c | 2 +- src/mainboard/asus/p8h61-m_pro/romstage.c | 2 +- src/mainboard/asus/p8z77-m_pro/romstage.c | 4 ---- src/mainboard/compulab/intense_pc/romstage.c | 2 +- src/mainboard/gigabyte/ga-b75m-d3h/romstage.c | 2 +- src/mainboard/gigabyte/ga-h61m-s2pv/romstage.c | 4 ---- src/mainboard/google/butterfly/romstage.c | 2 +- src/mainboard/google/link/romstage.c | 2 +- src/mainboard/google/parrot/romstage.c | 4 ---- src/mainboard/google/stout/romstage.c | 2 +- src/mainboard/hp/2570p/romstage.c | 4 ---- src/mainboard/hp/2760p/romstage.c | 4 ---- src/mainboard/hp/8460p/romstage.c | 4 ---- src/mainboard/hp/8470p/romstage.c | 4 ---- src/mainboard/hp/8770w/romstage.c | 4 ---- src/mainboard/hp/compaq_8200_elite_sff/romstage.c | 4 ---- src/mainboard/hp/folio_9470m/romstage.c | 4 ---- src/mainboard/hp/revolve_810_g1/romstage.c | 4 ---- src/mainboard/hp/z220_sff_workstation/romstage.c | 4 ---- src/mainboard/intel/dcp847ske/early_southbridge.c | 4 ---- src/mainboard/intel/emeraldlake2/romstage.c | 2 +- src/mainboard/kontron/ktqm77/romstage.c | 2 +- src/mainboard/lenovo/l520/romstage.c | 4 ---- src/mainboard/lenovo/s230u/romstage.c | 2 +- src/mainboard/lenovo/t420/romstage.c | 2 +- src/mainboard/lenovo/t420s/romstage.c | 2 +- src/mainboard/lenovo/t430/romstage.c | 4 ---- src/mainboard/lenovo/t430s/romstage.c | 2 +- src/mainboard/lenovo/t520/romstage.c | 2 +- src/mainboard/lenovo/t530/romstage.c | 2 +- src/mainboard/lenovo/x131e/romstage.c | 4 ---- src/mainboard/lenovo/x1_carbon_gen1/romstage.c | 2 +- src/mainboard/lenovo/x220/romstage.c | 2 +- src/mainboard/lenovo/x230/romstage.c | 2 +- src/mainboard/msi/ms7707/romstage.c | 2 +- src/mainboard/roda/rv11/variants/rv11/romstage.c | 4 ---- src/mainboard/roda/rv11/variants/rw11/romstage.c | 4 ---- src/mainboard/samsung/lumpy/romstage.c | 2 +- src/mainboard/samsung/stumpy/romstage.c | 2 +- src/mainboard/sapphire/pureplatinumh61/romstage.c | 2 +- src/northbridge/intel/sandybridge/sandybridge.h | 1 - src/southbridge/intel/bd82x6x/early_pch.c | 6 +++++- src/southbridge/intel/bd82x6x/pch.h | 3 +++ 47 files changed, 31 insertions(+), 109 deletions(-) diff --git a/src/mainboard/apple/macbookair4_2/romstage.c b/src/mainboard/apple/macbookair4_2/romstage.c index 5522ea013e..f445eea28e 100644 --- a/src/mainboard/apple/macbookair4_2/romstage.c +++ b/src/mainboard/apple/macbookair4_2/romstage.c @@ -20,7 +20,7 @@ #include #include -void pch_enable_lpc(void) +void mainboard_pch_lpc_setup(void) { pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x82, 0x3f0f); pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x80, 0x0070); diff --git a/src/mainboard/asrock/b75pro3-m/romstage.c b/src/mainboard/asrock/b75pro3-m/romstage.c index fe1416b908..983de07ff7 100644 --- a/src/mainboard/asrock/b75pro3-m/romstage.c +++ b/src/mainboard/asrock/b75pro3-m/romstage.c @@ -23,10 +23,6 @@ #define SERIAL_DEV PNP_DEV(0x2e, NCT6776_SP1) -void pch_enable_lpc(void) -{ -} - const struct southbridge_usb_port mainboard_usb_ports[] = { { 1, 0, 0 }, { 1, 0, 0 }, diff --git a/src/mainboard/asus/h61m-cs/romstage.c b/src/mainboard/asus/h61m-cs/romstage.c index 4c8eda74fe..2aa243f4e8 100644 --- a/src/mainboard/asus/h61m-cs/romstage.c +++ b/src/mainboard/asus/h61m-cs/romstage.c @@ -27,10 +27,6 @@ #define SIO_DEV PNP_DEV(SIO_PORT, 0) #define ACPI_DEV PNP_DEV(SIO_PORT, NCT6779D_ACPI) -void pch_enable_lpc(void) -{ -} - const struct southbridge_usb_port mainboard_usb_ports[] = { { 1, 0, 0 }, { 1, 0, 0 }, diff --git a/src/mainboard/asus/maximus_iv_gene-z/romstage.c b/src/mainboard/asus/maximus_iv_gene-z/romstage.c index e29dd0f160..c1e3975294 100644 --- a/src/mainboard/asus/maximus_iv_gene-z/romstage.c +++ b/src/mainboard/asus/maximus_iv_gene-z/romstage.c @@ -40,10 +40,6 @@ const struct southbridge_usb_port mainboard_usb_ports[] = { { 1, 0, 6 }, }; -void pch_enable_lpc(void) -{ -} - void mainboard_config_superio(void) { static const pnp_devfn_t GLOBAL_PSEUDO_DEV = PNP_DEV(0x2e, 0); diff --git a/src/mainboard/asus/p8h61-m_lx/romstage.c b/src/mainboard/asus/p8h61-m_lx/romstage.c index 01ae6030ad..d3361919a7 100644 --- a/src/mainboard/asus/p8h61-m_lx/romstage.c +++ b/src/mainboard/asus/p8h61-m_lx/romstage.c @@ -41,7 +41,7 @@ const struct southbridge_usb_port mainboard_usb_ports[] = { { 1, 0, 6 }, }; -void pch_enable_lpc(void) +void mainboard_pch_lpc_setup(void) { pci_or_config16(PCH_LPC_DEV, LPC_EN, CNF1_LPC_EN | KBC_LPC_EN | LPT_LPC_EN | COMA_LPC_EN); diff --git a/src/mainboard/asus/p8h61-m_pro/romstage.c b/src/mainboard/asus/p8h61-m_pro/romstage.c index 3736ab6b65..ff5a67748d 100644 --- a/src/mainboard/asus/p8h61-m_pro/romstage.c +++ b/src/mainboard/asus/p8h61-m_pro/romstage.c @@ -25,7 +25,7 @@ #define SERIAL_DEV PNP_DEV(0x2e, NCT6776_SP1) #define ACPI_DEV PNP_DEV(0x2e, NCT6776_ACPI) -void pch_enable_lpc(void) +void mainboard_pch_lpc_setup(void) { /* Enable the Super IO */ pci_write_config16(PCH_LPC_DEV, LPC_EN, CNF1_LPC_EN | diff --git a/src/mainboard/asus/p8z77-m_pro/romstage.c b/src/mainboard/asus/p8z77-m_pro/romstage.c index 5fff2e143c..4963c3102c 100644 --- a/src/mainboard/asus/p8z77-m_pro/romstage.c +++ b/src/mainboard/asus/p8z77-m_pro/romstage.c @@ -30,10 +30,6 @@ #define GLOBAL_DEV PNP_DEV(0x2e, 0) #define SERIAL_DEV PNP_DEV(0x2e, NCT6779D_SP2) -void pch_enable_lpc(void) -{ -} - const struct southbridge_usb_port mainboard_usb_ports[] = { /* {enable, current, oc_pin} */ { 1, 2, 0 }, /* Port 0: USB3 front internal header, top */ diff --git a/src/mainboard/compulab/intense_pc/romstage.c b/src/mainboard/compulab/intense_pc/romstage.c index f44a7e8edd..4176703ac7 100644 --- a/src/mainboard/compulab/intense_pc/romstage.c +++ b/src/mainboard/compulab/intense_pc/romstage.c @@ -22,7 +22,7 @@ #define SIO_PORT 0x164e -void pch_enable_lpc(void) +void mainboard_pch_lpc_setup(void) { pci_devfn_t dev = PCH_LPC_DEV; diff --git a/src/mainboard/gigabyte/ga-b75m-d3h/romstage.c b/src/mainboard/gigabyte/ga-b75m-d3h/romstage.c index 25e1d0385e..a5d4c35b34 100644 --- a/src/mainboard/gigabyte/ga-b75m-d3h/romstage.c +++ b/src/mainboard/gigabyte/ga-b75m-d3h/romstage.c @@ -25,7 +25,7 @@ #define SIO_GPIO PNP_DEV(SUPERIO_BASE, IT8728F_GPIO) #define SERIAL_DEV PNP_DEV(SUPERIO_BASE, 0x01) -void pch_enable_lpc(void) +void mainboard_pch_lpc_setup(void) { pci_write_config32(PCH_LPC_DEV, ETR3, 0x10000); } diff --git a/src/mainboard/gigabyte/ga-h61m-s2pv/romstage.c b/src/mainboard/gigabyte/ga-h61m-s2pv/romstage.c index 57cc0706d9..a68070fbe6 100644 --- a/src/mainboard/gigabyte/ga-h61m-s2pv/romstage.c +++ b/src/mainboard/gigabyte/ga-h61m-s2pv/romstage.c @@ -23,10 +23,6 @@ #define SUPERIO_GPIO PNP_DEV(0x2e, IT8728F_GPIO) #define SERIAL_DEV PNP_DEV(0x2e, 0x01) -void pch_enable_lpc(void) -{ -} - const struct southbridge_usb_port mainboard_usb_ports[] = { { 1, 0, 0 }, { 1, 0, 0 }, diff --git a/src/mainboard/google/butterfly/romstage.c b/src/mainboard/google/butterfly/romstage.c index 3aef9d0a09..e1d948d89f 100644 --- a/src/mainboard/google/butterfly/romstage.c +++ b/src/mainboard/google/butterfly/romstage.c @@ -28,7 +28,7 @@ #include #endif -void pch_enable_lpc(void) +void mainboard_pch_lpc_setup(void) { /* EC Decode Range Port60/64 and Port62/66 */ /* Enable EC and PS/2 Keyboard/Mouse*/ diff --git a/src/mainboard/google/link/romstage.c b/src/mainboard/google/link/romstage.c index 628e2a0052..3fd90e9b17 100644 --- a/src/mainboard/google/link/romstage.c +++ b/src/mainboard/google/link/romstage.c @@ -32,7 +32,7 @@ #include -void pch_enable_lpc(void) +void mainboard_pch_lpc_setup(void) { /* Enable PS/2 Keyboard/Mouse, EC areas and COM1 */ pci_write_config16(PCH_LPC_DEV, LPC_EN, KBC_LPC_EN | MC_LPC_EN | \ diff --git a/src/mainboard/google/parrot/romstage.c b/src/mainboard/google/parrot/romstage.c index 604cf7b284..caff3f5436 100644 --- a/src/mainboard/google/parrot/romstage.c +++ b/src/mainboard/google/parrot/romstage.c @@ -26,10 +26,6 @@ #include #include "ec/compal/ene932/ec.h" -void pch_enable_lpc(void) -{ -} - void mainboard_late_rcba_config(void) { u32 reg32; diff --git a/src/mainboard/google/stout/romstage.c b/src/mainboard/google/stout/romstage.c index cbbae2ee07..d8e04eaa63 100644 --- a/src/mainboard/google/stout/romstage.c +++ b/src/mainboard/google/stout/romstage.c @@ -30,7 +30,7 @@ #include "ec.h" #include "onboard.h" -void pch_enable_lpc(void) +void mainboard_pch_lpc_setup(void) { /* * Enable: diff --git a/src/mainboard/hp/2570p/romstage.c b/src/mainboard/hp/2570p/romstage.c index 8d36f6b27d..f1d1e905f3 100644 --- a/src/mainboard/hp/2570p/romstage.c +++ b/src/mainboard/hp/2570p/romstage.c @@ -20,10 +20,6 @@ #include #include -void pch_enable_lpc(void) -{ -} - const struct southbridge_usb_port mainboard_usb_ports[] = { { 1, 1, 0 }, { 0, 1, 0 }, diff --git a/src/mainboard/hp/2760p/romstage.c b/src/mainboard/hp/2760p/romstage.c index 5bf8789618..acf5b1895a 100644 --- a/src/mainboard/hp/2760p/romstage.c +++ b/src/mainboard/hp/2760p/romstage.c @@ -19,10 +19,6 @@ #include #include -void pch_enable_lpc(void) -{ -} - const struct southbridge_usb_port mainboard_usb_ports[] = { { 1, 1, 0 }, { 1, 1, 0 }, diff --git a/src/mainboard/hp/8460p/romstage.c b/src/mainboard/hp/8460p/romstage.c index 397810eba7..4e4b175366 100644 --- a/src/mainboard/hp/8460p/romstage.c +++ b/src/mainboard/hp/8460p/romstage.c @@ -23,10 +23,6 @@ #define SERIAL_DEV PNP_DEV(0x4e, LPC47N217_SP1) -void pch_enable_lpc(void) -{ -} - const struct southbridge_usb_port mainboard_usb_ports[] = { { 1, 1, 0 }, /* USB0, eSATA */ { 1, 0, 0 }, /* USB charger */ diff --git a/src/mainboard/hp/8470p/romstage.c b/src/mainboard/hp/8470p/romstage.c index 513b3756e8..8c9b29ef01 100644 --- a/src/mainboard/hp/8470p/romstage.c +++ b/src/mainboard/hp/8470p/romstage.c @@ -22,10 +22,6 @@ #define SERIAL_DEV PNP_DEV(0x4e, LPC47N217_SP1) -void pch_enable_lpc(void) -{ -} - const struct southbridge_usb_port mainboard_usb_ports[] = { { 1, 1, 0 }, { 1, 1, 0 }, diff --git a/src/mainboard/hp/8770w/romstage.c b/src/mainboard/hp/8770w/romstage.c index d3034fb565..8eefe4d6a2 100644 --- a/src/mainboard/hp/8770w/romstage.c +++ b/src/mainboard/hp/8770w/romstage.c @@ -23,10 +23,6 @@ #define SERIAL_DEV PNP_DEV(0x4e, LPC47N217_SP1) -void pch_enable_lpc(void) -{ -} - const struct southbridge_usb_port mainboard_usb_ports[] = { { 1, 1, 0 }, /* Dock USB3.0 */ { 1, 1, 0 }, /* Conn */ diff --git a/src/mainboard/hp/compaq_8200_elite_sff/romstage.c b/src/mainboard/hp/compaq_8200_elite_sff/romstage.c index 3e726cfb80..df581fe542 100644 --- a/src/mainboard/hp/compaq_8200_elite_sff/romstage.c +++ b/src/mainboard/hp/compaq_8200_elite_sff/romstage.c @@ -27,10 +27,6 @@ #define SERIAL_DEV PNP_DEV(0x2e, NPCD378_SP2) -void pch_enable_lpc(void) -{ -} - const struct southbridge_usb_port mainboard_usb_ports[] = { { 1, 0, -1 }, { 1, 0, -1 }, diff --git a/src/mainboard/hp/folio_9470m/romstage.c b/src/mainboard/hp/folio_9470m/romstage.c index 969b666d8f..07ee1eb283 100644 --- a/src/mainboard/hp/folio_9470m/romstage.c +++ b/src/mainboard/hp/folio_9470m/romstage.c @@ -21,10 +21,6 @@ #include #include -void pch_enable_lpc(void) -{ -} - const struct southbridge_usb_port mainboard_usb_ports[] = { { 1, 1, 0 }, /* SSP1: dock */ { 1, 1, 0 }, /* SSP2: left, EHCI Debug */ diff --git a/src/mainboard/hp/revolve_810_g1/romstage.c b/src/mainboard/hp/revolve_810_g1/romstage.c index 844bb2f4e3..24247420ab 100644 --- a/src/mainboard/hp/revolve_810_g1/romstage.c +++ b/src/mainboard/hp/revolve_810_g1/romstage.c @@ -24,10 +24,6 @@ #include #include -void pch_enable_lpc(void) -{ -} - void mainboard_late_rcba_config(void) { RCBA32(BUC) = 0x00000000; diff --git a/src/mainboard/hp/z220_sff_workstation/romstage.c b/src/mainboard/hp/z220_sff_workstation/romstage.c index 2e0a50806c..0b9ffe4d56 100644 --- a/src/mainboard/hp/z220_sff_workstation/romstage.c +++ b/src/mainboard/hp/z220_sff_workstation/romstage.c @@ -27,10 +27,6 @@ #define SERIAL_DEV PNP_DEV(0x2e, NPCD378_SP2) -void pch_enable_lpc(void) -{ -} - const struct southbridge_usb_port mainboard_usb_ports[] = { { 1, 0, 0 }, { 1, 0, 0 }, diff --git a/src/mainboard/intel/dcp847ske/early_southbridge.c b/src/mainboard/intel/dcp847ske/early_southbridge.c index 1cd58b0ba5..8f38270388 100644 --- a/src/mainboard/intel/dcp847ske/early_southbridge.c +++ b/src/mainboard/intel/dcp847ske/early_southbridge.c @@ -27,10 +27,6 @@ #include "superio.h" #include "thermal.h" -void pch_enable_lpc(void) -{ -} - void mainboard_late_rcba_config(void) { /* Disable devices */ diff --git a/src/mainboard/intel/emeraldlake2/romstage.c b/src/mainboard/intel/emeraldlake2/romstage.c index 16a16de33f..2cfb5569fb 100644 --- a/src/mainboard/intel/emeraldlake2/romstage.c +++ b/src/mainboard/intel/emeraldlake2/romstage.c @@ -28,7 +28,7 @@ #define SIO_PORT 0x164e -void pch_enable_lpc(void) +void mainboard_pch_lpc_setup(void) { pci_devfn_t dev = PCH_LPC_DEV; diff --git a/src/mainboard/kontron/ktqm77/romstage.c b/src/mainboard/kontron/ktqm77/romstage.c index 37713e1657..3b49653f97 100644 --- a/src/mainboard/kontron/ktqm77/romstage.c +++ b/src/mainboard/kontron/ktqm77/romstage.c @@ -27,7 +27,7 @@ #include #include -void pch_enable_lpc(void) +void mainboard_pch_lpc_setup(void) { /* Set COM3/COM1 decode ranges: 0x3e8/0x3f8 */ pci_write_config16(PCH_LPC_DEV, LPC_IO_DEC, 0x0070); diff --git a/src/mainboard/lenovo/l520/romstage.c b/src/mainboard/lenovo/l520/romstage.c index 37182f855d..af73537f24 100644 --- a/src/mainboard/lenovo/l520/romstage.c +++ b/src/mainboard/lenovo/l520/romstage.c @@ -22,10 +22,6 @@ #include #include -void pch_enable_lpc(void) -{ -} - const struct southbridge_usb_port mainboard_usb_ports[] = { { 1, 0, -1 }, { 1, 0, -1 }, diff --git a/src/mainboard/lenovo/s230u/romstage.c b/src/mainboard/lenovo/s230u/romstage.c index ee1d0ed19c..0552170668 100644 --- a/src/mainboard/lenovo/s230u/romstage.c +++ b/src/mainboard/lenovo/s230u/romstage.c @@ -27,7 +27,7 @@ #define SPD_LEN 256 -void pch_enable_lpc(void) +void mainboard_pch_lpc_setup(void) { pci_write_config32(PCH_LPC_DEV, ETR3, 0x10000); diff --git a/src/mainboard/lenovo/t420/romstage.c b/src/mainboard/lenovo/t420/romstage.c index 7036ec40fe..e04803f165 100644 --- a/src/mainboard/lenovo/t420/romstage.c +++ b/src/mainboard/lenovo/t420/romstage.c @@ -49,7 +49,7 @@ static void hybrid_graphics_init(void) pci_write_config32(PCI_DEV(0, 0, 0), DEVEN, reg32); } -void pch_enable_lpc(void) +void mainboard_pch_lpc_setup(void) { pci_write_config32(PCH_LPC_DEV, ETR3, 0x10000); } diff --git a/src/mainboard/lenovo/t420s/romstage.c b/src/mainboard/lenovo/t420s/romstage.c index 7b97ff7e75..764997297e 100644 --- a/src/mainboard/lenovo/t420s/romstage.c +++ b/src/mainboard/lenovo/t420s/romstage.c @@ -49,7 +49,7 @@ static void hybrid_graphics_init(void) pci_write_config32(PCI_DEV(0, 0, 0), DEVEN, reg32); } -void pch_enable_lpc(void) +void mainboard_pch_lpc_setup(void) { pci_write_config32(PCH_LPC_DEV, ETR3, 0x10000); } diff --git a/src/mainboard/lenovo/t430/romstage.c b/src/mainboard/lenovo/t430/romstage.c index 0cff5d2b59..f1e724be47 100644 --- a/src/mainboard/lenovo/t430/romstage.c +++ b/src/mainboard/lenovo/t430/romstage.c @@ -49,10 +49,6 @@ static void hybrid_graphics_init(void) pci_write_config32(PCI_DEV(0, 0, 0), DEVEN, reg32); } -void pch_enable_lpc(void) -{ -} - /* FIXME: used T530 values here */ const struct southbridge_usb_port mainboard_usb_ports[] = { { 1, 1, 0 }, diff --git a/src/mainboard/lenovo/t430s/romstage.c b/src/mainboard/lenovo/t430s/romstage.c index 298673b5dd..6503c9a920 100644 --- a/src/mainboard/lenovo/t430s/romstage.c +++ b/src/mainboard/lenovo/t430s/romstage.c @@ -19,7 +19,7 @@ #include #include -void pch_enable_lpc(void) +void mainboard_pch_lpc_setup(void) { pci_write_config32(PCH_LPC_DEV, ETR3, 0x10000); } diff --git a/src/mainboard/lenovo/t520/romstage.c b/src/mainboard/lenovo/t520/romstage.c index 52898faa45..caf54bd5df 100644 --- a/src/mainboard/lenovo/t520/romstage.c +++ b/src/mainboard/lenovo/t520/romstage.c @@ -51,7 +51,7 @@ static void hybrid_graphics_init(void) pci_write_config32(PCI_DEV(0, 0, 0), DEVEN, reg32); } -void pch_enable_lpc(void) +void mainboard_pch_lpc_setup(void) { pci_write_config32(PCH_LPC_DEV, ETR3, 0x10000); } diff --git a/src/mainboard/lenovo/t530/romstage.c b/src/mainboard/lenovo/t530/romstage.c index e0b0455c75..85c3090bb5 100644 --- a/src/mainboard/lenovo/t530/romstage.c +++ b/src/mainboard/lenovo/t530/romstage.c @@ -51,7 +51,7 @@ static void hybrid_graphics_init(void) pci_write_config32(PCI_DEV(0, 0, 0), DEVEN, reg32); } -void pch_enable_lpc(void) +void mainboard_pch_lpc_setup(void) { pci_write_config32(PCH_LPC_DEV, ETR3, 0x10000); } diff --git a/src/mainboard/lenovo/x131e/romstage.c b/src/mainboard/lenovo/x131e/romstage.c index a1d3e88ad7..45d6b88099 100644 --- a/src/mainboard/lenovo/x131e/romstage.c +++ b/src/mainboard/lenovo/x131e/romstage.c @@ -20,10 +20,6 @@ #include #include -void pch_enable_lpc(void) -{ -} - const struct southbridge_usb_port mainboard_usb_ports[] = { {1, 1, 0}, /* P0: USB 3.0 1 (OC0) */ {1, 1, 0}, /* P1: USB 3.0 2 (OC0) */ diff --git a/src/mainboard/lenovo/x1_carbon_gen1/romstage.c b/src/mainboard/lenovo/x1_carbon_gen1/romstage.c index f4d2a3c70a..1f027ffab8 100644 --- a/src/mainboard/lenovo/x1_carbon_gen1/romstage.c +++ b/src/mainboard/lenovo/x1_carbon_gen1/romstage.c @@ -28,7 +28,7 @@ #include #include -void pch_enable_lpc(void) +void mainboard_pch_lpc_setup(void) { pci_write_config32(PCH_LPC_DEV, ETR3, 0x10000); } diff --git a/src/mainboard/lenovo/x220/romstage.c b/src/mainboard/lenovo/x220/romstage.c index 7989fd6298..72dd8dddca 100644 --- a/src/mainboard/lenovo/x220/romstage.c +++ b/src/mainboard/lenovo/x220/romstage.c @@ -27,7 +27,7 @@ #include #include -void pch_enable_lpc(void) +void mainboard_pch_lpc_setup(void) { pci_write_config32(PCH_LPC_DEV, ETR3, 0x10000); } diff --git a/src/mainboard/lenovo/x230/romstage.c b/src/mainboard/lenovo/x230/romstage.c index 3e9ea2c371..56f5a90670 100644 --- a/src/mainboard/lenovo/x230/romstage.c +++ b/src/mainboard/lenovo/x230/romstage.c @@ -24,7 +24,7 @@ #include #include -void pch_enable_lpc(void) +void mainboard_pch_lpc_setup(void) { pci_write_config32(PCH_LPC_DEV, ETR3, 0x10000); } diff --git a/src/mainboard/msi/ms7707/romstage.c b/src/mainboard/msi/ms7707/romstage.c index 399d44b2a4..1dd3fd06a8 100644 --- a/src/mainboard/msi/ms7707/romstage.c +++ b/src/mainboard/msi/ms7707/romstage.c @@ -20,7 +20,7 @@ #include #include -void pch_enable_lpc(void) +void mainboard_pch_lpc_setup(void) { u16 reg16; reg16 = pci_read_config16(PCI_DEV(0, 0x1f, 0), 0xa4); diff --git a/src/mainboard/roda/rv11/variants/rv11/romstage.c b/src/mainboard/roda/rv11/variants/rv11/romstage.c index 4491370cbf..38c4064772 100644 --- a/src/mainboard/roda/rv11/variants/rv11/romstage.c +++ b/src/mainboard/roda/rv11/variants/rv11/romstage.c @@ -21,10 +21,6 @@ #include #include -void pch_enable_lpc(void) -{ -} - void mainboard_config_superio(void) { } diff --git a/src/mainboard/roda/rv11/variants/rw11/romstage.c b/src/mainboard/roda/rv11/variants/rw11/romstage.c index f355578b6e..7321dac398 100644 --- a/src/mainboard/roda/rv11/variants/rw11/romstage.c +++ b/src/mainboard/roda/rv11/variants/rw11/romstage.c @@ -25,10 +25,6 @@ #include #include -void pch_enable_lpc(void) -{ -} - void mainboard_config_superio(void) { const pnp_devfn_t dev = PNP_DEV(0x2e, IT8783EF_GPIO); diff --git a/src/mainboard/samsung/lumpy/romstage.c b/src/mainboard/samsung/lumpy/romstage.c index ddcf2ad9e6..d6ded7a559 100644 --- a/src/mainboard/samsung/lumpy/romstage.c +++ b/src/mainboard/samsung/lumpy/romstage.c @@ -33,7 +33,7 @@ #include #endif -void pch_enable_lpc(void) +void mainboard_pch_lpc_setup(void) { /* Set COM1/COM2 decode range */ pci_write_config16(PCH_LPC_DEV, LPC_IO_DEC, 0x0010); diff --git a/src/mainboard/samsung/stumpy/romstage.c b/src/mainboard/samsung/stumpy/romstage.c index 06659978e5..35dc055baa 100644 --- a/src/mainboard/samsung/stumpy/romstage.c +++ b/src/mainboard/samsung/stumpy/romstage.c @@ -45,7 +45,7 @@ #define SERIAL_DEV PNP_DEV(0x2e, IT8772F_SP1) #define GPIO_DEV PNP_DEV(0x2e, IT8772F_GPIO) -void pch_enable_lpc(void) +void mainboard_pch_lpc_setup(void) { /* Set COM1/COM2 decode range */ pci_write_config16(PCH_LPC_DEV, LPC_IO_DEC, 0x0010); diff --git a/src/mainboard/sapphire/pureplatinumh61/romstage.c b/src/mainboard/sapphire/pureplatinumh61/romstage.c index 3c9cc829d7..bc08fd8bf2 100644 --- a/src/mainboard/sapphire/pureplatinumh61/romstage.c +++ b/src/mainboard/sapphire/pureplatinumh61/romstage.c @@ -21,7 +21,7 @@ #include #include -void pch_enable_lpc(void) +void mainboard_pch_lpc_setup(void) { pci_write_config32(PCI_DEV(0, 0x1f, 0), 0xac, 0x00010000); } diff --git a/src/northbridge/intel/sandybridge/sandybridge.h b/src/northbridge/intel/sandybridge/sandybridge.h index d667e36571..cfda2e838b 100644 --- a/src/northbridge/intel/sandybridge/sandybridge.h +++ b/src/northbridge/intel/sandybridge/sandybridge.h @@ -212,7 +212,6 @@ void sandybridge_late_initialization(void); void northbridge_romstage_finalize(int s3resume); void early_init_dmi(void); -void pch_enable_lpc(void); /* mainboard_early_init: Optional mainboard callback run after console init but before raminit. */ void mainboard_early_init(int s3resume); diff --git a/src/southbridge/intel/bd82x6x/early_pch.c b/src/southbridge/intel/bd82x6x/early_pch.c index d8fd7ad6a5..8ffb22e140 100644 --- a/src/southbridge/intel/bd82x6x/early_pch.c +++ b/src/southbridge/intel/bd82x6x/early_pch.c @@ -286,12 +286,16 @@ static void pch_enable_lpc_decode(void) pci_write_config32(PCH_LPC_DEV, LPC_GEN4_DEC, config->gen4_dec); } +__weak void mainboard_pch_lpc_setup(void) +{ +} + void early_pch_init(void) { pch_enable_lpc_decode(); - pch_enable_lpc(); + mainboard_pch_lpc_setup(); pch_enable_bars(); diff --git a/src/southbridge/intel/bd82x6x/pch.h b/src/southbridge/intel/bd82x6x/pch.h index d4cd86eaa5..127fb61cce 100644 --- a/src/southbridge/intel/bd82x6x/pch.h +++ b/src/southbridge/intel/bd82x6x/pch.h @@ -75,6 +75,9 @@ void southbridge_rcba_config(void); /* Optional mainboard hook to do additional configuration on the RCBA config space. It is called after the raminit. */ void mainboard_late_rcba_config(void); +/* Optional mainboard hook to do additional LPC configuration + or to override what is set up by default. */ +void mainboard_pch_lpc_setup(void); void early_pch_init_native(void); void early_pch_init(void); void early_pch_init_native_dmi_pre(void); From 67d59d1756423a96aca5249b59c4e3759b2f3721 Mon Sep 17 00:00:00 2001 From: Arthur Heymans Date: Sat, 16 Nov 2019 20:06:20 +0100 Subject: [PATCH 0224/1242] nb/intel/sandybridge: Configure DCACHE_BSP_STACK_SIZE The romstage default is to set stack guards at 0x2000 below end of stack. The code is now overwrites some of the stack guards so increase the stack size to a comfortable 0x2800. Change-Id: I91f559383a987241b343e743d11291f2c100f7f5 Signed-off-by: Arthur Heymans Reviewed-on: https://review.coreboot.org/c/coreboot/+/36884 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber --- src/northbridge/intel/sandybridge/Kconfig | 3 +++ 1 file changed, 3 insertions(+) diff --git a/src/northbridge/intel/sandybridge/Kconfig b/src/northbridge/intel/sandybridge/Kconfig index 64ce4d82d9..288dd093bf 100644 --- a/src/northbridge/intel/sandybridge/Kconfig +++ b/src/northbridge/intel/sandybridge/Kconfig @@ -76,6 +76,9 @@ config DCACHE_RAM_BASE hex default 0xfefe0000 +config DCACHE_BSP_STACK_SIZE + hex + default 0x2800 if USE_NATIVE_RAMINIT From 360d94745feea766de7ef19487ba9158221faca0 Mon Sep 17 00:00:00 2001 From: Arthur Heymans Date: Tue, 12 Nov 2019 18:11:03 +0100 Subject: [PATCH 0225/1242] nb/intel/sandybridge: Move to C_ENVIRONMENT_BOOTBLOCK There is some overlap between romstage and bootblock. LPC setup and BAR initialization is now done twice. The rationale is that the romstage should not depend too much on the bootblock, since it can reside in a RO fmap region. Enabling the console will be done in a followup patch. Change-Id: I4d0ba29111a5df6f19033f5ce95adcc0d9adc1fd Signed-off-by: Arthur Heymans Reviewed-on: https://review.coreboot.org/c/coreboot/+/36783 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber --- src/cpu/intel/model_206ax/Kconfig | 6 +-- src/cpu/intel/model_206ax/Makefile.inc | 6 ++- src/cpu/intel/model_206ax/bootblock.c | 37 +------------------ .../apple/macbookair4_2/Makefile.inc | 1 + src/mainboard/asrock/b75pro3-m/Makefile.inc | 1 + src/mainboard/asus/h61m-cs/Makefile.inc | 1 + .../asus/maximus_iv_gene-z/Makefile.inc | 1 + src/mainboard/asus/p8h61-m_lx/Makefile.inc | 1 + src/mainboard/asus/p8h61-m_pro/Makefile.inc | 1 + src/mainboard/asus/p8z77-m_pro/Makefile.inc | 1 + .../compulab/intense_pc/Makefile.inc | 1 + .../gigabyte/ga-b75m-d3h/Makefile.inc | 1 + .../gigabyte/ga-h61m-s2pv/Makefile.inc | 1 + src/mainboard/google/butterfly/Makefile.inc | 1 + src/mainboard/google/link/Makefile.inc | 1 + src/mainboard/google/parrot/Makefile.inc | 1 + src/mainboard/google/stout/Makefile.inc | 1 + src/mainboard/hp/2570p/Makefile.inc | 1 + src/mainboard/hp/2760p/Makefile.inc | 1 + src/mainboard/hp/8460p/Makefile.inc | 1 + src/mainboard/hp/8470p/Makefile.inc | 1 + src/mainboard/hp/8770w/Makefile.inc | 1 + .../hp/compaq_8200_elite_sff/Makefile.inc | 1 + src/mainboard/hp/folio_9470m/Makefile.inc | 1 + src/mainboard/hp/revolve_810_g1/Makefile.inc | 1 + .../hp/z220_sff_workstation/Makefile.inc | 1 + src/mainboard/intel/dcp847ske/Makefile.inc | 1 + src/mainboard/intel/emeraldlake2/Makefile.inc | 1 + src/mainboard/kontron/ktqm77/Makefile.inc | 1 + src/mainboard/lenovo/l520/Makefile.inc | 1 + src/mainboard/lenovo/s230u/Makefile.inc | 1 + src/mainboard/lenovo/t420/Makefile.inc | 1 + src/mainboard/lenovo/t420s/Makefile.inc | 1 + src/mainboard/lenovo/t430/Makefile.inc | 1 + src/mainboard/lenovo/t430s/Makefile.inc | 1 + src/mainboard/lenovo/t520/Makefile.inc | 1 + src/mainboard/lenovo/t530/Makefile.inc | 1 + src/mainboard/lenovo/x131e/Makefile.inc | 1 + .../lenovo/x1_carbon_gen1/Makefile.inc | 1 + src/mainboard/lenovo/x220/Makefile.inc | 1 + src/mainboard/lenovo/x230/Makefile.inc | 1 + src/mainboard/msi/ms7707/Makefile.inc | 1 + src/mainboard/roda/rv11/Makefile.inc | 1 + src/mainboard/samsung/lumpy/Makefile.inc | 1 + src/mainboard/samsung/stumpy/Makefile.inc | 1 + .../sapphire/pureplatinumh61/Makefile.inc | 1 + src/northbridge/intel/sandybridge/Kconfig | 4 -- .../intel/sandybridge/Makefile.inc | 3 +- src/northbridge/intel/sandybridge/bootblock.c | 7 ++-- src/southbridge/intel/bd82x6x/Kconfig | 4 -- src/southbridge/intel/bd82x6x/Makefile.inc | 3 ++ src/southbridge/intel/bd82x6x/bootblock.c | 16 +++----- 52 files changed, 65 insertions(+), 64 deletions(-) diff --git a/src/cpu/intel/model_206ax/Kconfig b/src/cpu/intel/model_206ax/Kconfig index 8dae6ecc30..223703eb84 100644 --- a/src/cpu/intel/model_206ax/Kconfig +++ b/src/cpu/intel/model_206ax/Kconfig @@ -21,10 +21,8 @@ config CPU_SPECIFIC_OPTIONS select CPU_INTEL_COMMON_TIMEBASE select PARALLEL_MP select NO_FIXED_XIP_ROM_SIZE - -config BOOTBLOCK_CPU_INIT - string - default "cpu/intel/model_206ax/bootblock.c" + select C_ENVIRONMENT_BOOTBLOCK + select NO_BOOTBLOCK_CONSOLE config SMM_TSEG_SIZE hex diff --git a/src/cpu/intel/model_206ax/Makefile.inc b/src/cpu/intel/model_206ax/Makefile.inc index 391d126e77..d824da141b 100644 --- a/src/cpu/intel/model_206ax/Makefile.inc +++ b/src/cpu/intel/model_206ax/Makefile.inc @@ -21,7 +21,11 @@ smm-y += finalize.c cpu_microcode_bins += $(wildcard 3rdparty/intel-microcode/intel-ucode/06-2a-*) cpu_microcode_bins += $(wildcard 3rdparty/intel-microcode/intel-ucode/06-3a-*) -cpu_incs-y += $(src)/cpu/intel/car/non-evict/cache_as_ram.S +bootblock-y += bootblock.c +bootblock-y += ../car/non-evict/cache_as_ram.S +bootblock-y += ../../x86/early_reset.S +bootblock-y += ../car/bootblock.c + postcar-y += ../car/non-evict/exit_car.S romstage-y += ../car/romstage.c diff --git a/src/cpu/intel/model_206ax/bootblock.c b/src/cpu/intel/model_206ax/bootblock.c index 72b4a672c2..da0333f4bc 100644 --- a/src/cpu/intel/model_206ax/bootblock.c +++ b/src/cpu/intel/model_206ax/bootblock.c @@ -13,13 +13,11 @@ #include #include -#include #include -#include #include #include +#include -#include #include "model_206ax.h" #if CONFIG(SOUTHBRIDGE_INTEL_BD82X6X) || \ @@ -30,35 +28,6 @@ #error "CPU must be paired with Intel BD82X6X or C216 southbridge" #endif -static void set_var_mtrr(unsigned int reg, unsigned int base, unsigned int size, - unsigned int type) - -{ - /* Bit Bit 32-35 of MTRRphysMask should be set to 1 */ - /* FIXME: It only support 4G less range */ - msr_t basem, maskm; - basem.lo = base | type; - basem.hi = 0; - wrmsr(MTRR_PHYS_BASE(reg), basem); - maskm.lo = ~(size - 1) | MTRR_PHYS_MASK_VALID; - maskm.hi = (1 << (CONFIG_CPU_ADDR_BITS - 32)) - 1; - wrmsr(MTRR_PHYS_MASK(reg), maskm); -} - -static void enable_rom_caching(void) -{ - msr_t msr; - - disable_cache(); - set_var_mtrr(1, CACHE_ROM_BASE, CACHE_ROM_SIZE, MTRR_TYPE_WRPROT); - enable_cache(); - - /* Enable Variable MTRRs */ - msr.hi = 0x00000000; - msr.lo = 0x00000800; - wrmsr(MTRR_DEF_TYPE_MSR, msr); -} - static void set_flex_ratio_to_tdp_nominal(void) { msr_t flex_ratio, msr; @@ -109,10 +78,8 @@ static void set_flex_ratio_to_tdp_nominal(void) halt(); } -static void bootblock_cpu_init(void) +void bootblock_early_cpu_init(void) { /* Set flex ratio and reset if needed */ set_flex_ratio_to_tdp_nominal(); - enable_rom_caching(); - intel_update_microcode_from_cbfs(); } diff --git a/src/mainboard/apple/macbookair4_2/Makefile.inc b/src/mainboard/apple/macbookair4_2/Makefile.inc index a41ee25641..da821939cc 100644 --- a/src/mainboard/apple/macbookair4_2/Makefile.inc +++ b/src/mainboard/apple/macbookair4_2/Makefile.inc @@ -1,3 +1,4 @@ +bootblock-y += gpio.c romstage-y += gpio.c ramstage-y += gnvs.c diff --git a/src/mainboard/asrock/b75pro3-m/Makefile.inc b/src/mainboard/asrock/b75pro3-m/Makefile.inc index 017967b614..df00e3749e 100644 --- a/src/mainboard/asrock/b75pro3-m/Makefile.inc +++ b/src/mainboard/asrock/b75pro3-m/Makefile.inc @@ -13,6 +13,7 @@ ## GNU General Public License for more details. ## +bootblock-y += gpio.c romstage-y += gpio.c ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads diff --git a/src/mainboard/asus/h61m-cs/Makefile.inc b/src/mainboard/asus/h61m-cs/Makefile.inc index ebe01aea99..af2b6742f0 100644 --- a/src/mainboard/asus/h61m-cs/Makefile.inc +++ b/src/mainboard/asus/h61m-cs/Makefile.inc @@ -1,2 +1,3 @@ +bootblock-y += gpio.c romstage-y += gpio.c ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads diff --git a/src/mainboard/asus/maximus_iv_gene-z/Makefile.inc b/src/mainboard/asus/maximus_iv_gene-z/Makefile.inc index f81e828632..0547b4d643 100644 --- a/src/mainboard/asus/maximus_iv_gene-z/Makefile.inc +++ b/src/mainboard/asus/maximus_iv_gene-z/Makefile.inc @@ -14,5 +14,6 @@ ## GNU General Public License for more details. ## +bootblock-y += gpio.c romstage-y += gpio.c ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads diff --git a/src/mainboard/asus/p8h61-m_lx/Makefile.inc b/src/mainboard/asus/p8h61-m_lx/Makefile.inc index 7c1bf9ecd4..9ee5136945 100644 --- a/src/mainboard/asus/p8h61-m_lx/Makefile.inc +++ b/src/mainboard/asus/p8h61-m_lx/Makefile.inc @@ -14,5 +14,6 @@ ## GNU General Public License for more details. ## +bootblock-y += gpio.c romstage-y += gpio.c ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads diff --git a/src/mainboard/asus/p8h61-m_pro/Makefile.inc b/src/mainboard/asus/p8h61-m_pro/Makefile.inc index ea035d3876..620a9c06a2 100644 --- a/src/mainboard/asus/p8h61-m_pro/Makefile.inc +++ b/src/mainboard/asus/p8h61-m_pro/Makefile.inc @@ -1,3 +1,4 @@ +bootblock-y += gpio.c romstage-y += gpio.c ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads diff --git a/src/mainboard/asus/p8z77-m_pro/Makefile.inc b/src/mainboard/asus/p8z77-m_pro/Makefile.inc index 0cc398a5e7..8fc0eadbcc 100644 --- a/src/mainboard/asus/p8z77-m_pro/Makefile.inc +++ b/src/mainboard/asus/p8z77-m_pro/Makefile.inc @@ -14,6 +14,7 @@ ## GNU General Public License for more details. ## +bootblock-y += gpio.c romstage-y += gpio.c ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads diff --git a/src/mainboard/compulab/intense_pc/Makefile.inc b/src/mainboard/compulab/intense_pc/Makefile.inc index ea035d3876..620a9c06a2 100644 --- a/src/mainboard/compulab/intense_pc/Makefile.inc +++ b/src/mainboard/compulab/intense_pc/Makefile.inc @@ -1,3 +1,4 @@ +bootblock-y += gpio.c romstage-y += gpio.c ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads diff --git a/src/mainboard/gigabyte/ga-b75m-d3h/Makefile.inc b/src/mainboard/gigabyte/ga-b75m-d3h/Makefile.inc index 07fc277c28..f5b33bd644 100644 --- a/src/mainboard/gigabyte/ga-b75m-d3h/Makefile.inc +++ b/src/mainboard/gigabyte/ga-b75m-d3h/Makefile.inc @@ -13,6 +13,7 @@ ## GNU General Public License for more details. ## +bootblock-y += variants/$(VARIANT_DIR)/gpio.c romstage-y += variants/$(VARIANT_DIR)/gpio.c ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += variants/$(VARIANT_DIR)/gma-mainboard.ads diff --git a/src/mainboard/gigabyte/ga-h61m-s2pv/Makefile.inc b/src/mainboard/gigabyte/ga-h61m-s2pv/Makefile.inc index fe7cc81bb9..5166ce06af 100644 --- a/src/mainboard/gigabyte/ga-h61m-s2pv/Makefile.inc +++ b/src/mainboard/gigabyte/ga-h61m-s2pv/Makefile.inc @@ -1,3 +1,4 @@ +bootblock-y += variants/$(VARIANT_DIR)/gpio.c romstage-y += variants/$(VARIANT_DIR)/gpio.c ramstage-y += variants/$(VARIANT_DIR)/hda_verb.c diff --git a/src/mainboard/google/butterfly/Makefile.inc b/src/mainboard/google/butterfly/Makefile.inc index b6654b8c0a..fa9a4a9068 100644 --- a/src/mainboard/google/butterfly/Makefile.inc +++ b/src/mainboard/google/butterfly/Makefile.inc @@ -17,6 +17,7 @@ ramstage-y += ec.c romstage-y += chromeos.c ramstage-y += chromeos.c +bootblock-y += gpio.c romstage-y += gpio.c smm-y += mainboard_smi.c diff --git a/src/mainboard/google/link/Makefile.inc b/src/mainboard/google/link/Makefile.inc index e6c7be181c..724150c138 100644 --- a/src/mainboard/google/link/Makefile.inc +++ b/src/mainboard/google/link/Makefile.inc @@ -40,4 +40,5 @@ $(SPD_BIN): $(SPD_DEPS) cbfs-files-y += spd.bin spd.bin-file := $(SPD_BIN) spd.bin-type := spd +bootblock-y += gpio.c romstage-y += gpio.c diff --git a/src/mainboard/google/parrot/Makefile.inc b/src/mainboard/google/parrot/Makefile.inc index 393d582995..67324bdff0 100644 --- a/src/mainboard/google/parrot/Makefile.inc +++ b/src/mainboard/google/parrot/Makefile.inc @@ -17,6 +17,7 @@ ramstage-y += ec.c romstage-$(CONFIG_CHROMEOS) += chromeos.c ramstage-$(CONFIG_CHROMEOS) += chromeos.c +bootblock-y += gpio.c romstage-y += gpio.c ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads diff --git a/src/mainboard/google/stout/Makefile.inc b/src/mainboard/google/stout/Makefile.inc index f4f2284de4..59ac22dbae 100644 --- a/src/mainboard/google/stout/Makefile.inc +++ b/src/mainboard/google/stout/Makefile.inc @@ -22,6 +22,7 @@ smm-y += mainboard_smi.c smm-y += ec.c SRC_ROOT = $(src)/mainboard/google/stout +bootblock-y += gpio.c romstage-y += gpio.c ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads diff --git a/src/mainboard/hp/2570p/Makefile.inc b/src/mainboard/hp/2570p/Makefile.inc index 7a00ccebd7..4fbf73bbd3 100644 --- a/src/mainboard/hp/2570p/Makefile.inc +++ b/src/mainboard/hp/2570p/Makefile.inc @@ -13,6 +13,7 @@ ## GNU General Public License for more details. ## +bootblock-y += gpio.c romstage-y += gpio.c ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads diff --git a/src/mainboard/hp/2760p/Makefile.inc b/src/mainboard/hp/2760p/Makefile.inc index 7a00ccebd7..4fbf73bbd3 100644 --- a/src/mainboard/hp/2760p/Makefile.inc +++ b/src/mainboard/hp/2760p/Makefile.inc @@ -13,6 +13,7 @@ ## GNU General Public License for more details. ## +bootblock-y += gpio.c romstage-y += gpio.c ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads diff --git a/src/mainboard/hp/8460p/Makefile.inc b/src/mainboard/hp/8460p/Makefile.inc index 7a00ccebd7..4fbf73bbd3 100644 --- a/src/mainboard/hp/8460p/Makefile.inc +++ b/src/mainboard/hp/8460p/Makefile.inc @@ -13,6 +13,7 @@ ## GNU General Public License for more details. ## +bootblock-y += gpio.c romstage-y += gpio.c ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads diff --git a/src/mainboard/hp/8470p/Makefile.inc b/src/mainboard/hp/8470p/Makefile.inc index 7a00ccebd7..4fbf73bbd3 100644 --- a/src/mainboard/hp/8470p/Makefile.inc +++ b/src/mainboard/hp/8470p/Makefile.inc @@ -13,6 +13,7 @@ ## GNU General Public License for more details. ## +bootblock-y += gpio.c romstage-y += gpio.c ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads diff --git a/src/mainboard/hp/8770w/Makefile.inc b/src/mainboard/hp/8770w/Makefile.inc index d57c9b5707..910d6a6191 100644 --- a/src/mainboard/hp/8770w/Makefile.inc +++ b/src/mainboard/hp/8770w/Makefile.inc @@ -13,4 +13,5 @@ ## GNU General Public License for more details. ## +bootblock-y += gpio.c romstage-y += gpio.c diff --git a/src/mainboard/hp/compaq_8200_elite_sff/Makefile.inc b/src/mainboard/hp/compaq_8200_elite_sff/Makefile.inc index ebe01aea99..af2b6742f0 100644 --- a/src/mainboard/hp/compaq_8200_elite_sff/Makefile.inc +++ b/src/mainboard/hp/compaq_8200_elite_sff/Makefile.inc @@ -1,2 +1,3 @@ +bootblock-y += gpio.c romstage-y += gpio.c ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads diff --git a/src/mainboard/hp/folio_9470m/Makefile.inc b/src/mainboard/hp/folio_9470m/Makefile.inc index 7a00ccebd7..4fbf73bbd3 100644 --- a/src/mainboard/hp/folio_9470m/Makefile.inc +++ b/src/mainboard/hp/folio_9470m/Makefile.inc @@ -13,6 +13,7 @@ ## GNU General Public License for more details. ## +bootblock-y += gpio.c romstage-y += gpio.c ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads diff --git a/src/mainboard/hp/revolve_810_g1/Makefile.inc b/src/mainboard/hp/revolve_810_g1/Makefile.inc index 7a211f4aad..574f56e107 100644 --- a/src/mainboard/hp/revolve_810_g1/Makefile.inc +++ b/src/mainboard/hp/revolve_810_g1/Makefile.inc @@ -13,6 +13,7 @@ ## GNU General Public License for more details. ## +bootblock-y += gpio.c romstage-y += gpio.c ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads diff --git a/src/mainboard/hp/z220_sff_workstation/Makefile.inc b/src/mainboard/hp/z220_sff_workstation/Makefile.inc index ebe01aea99..af2b6742f0 100644 --- a/src/mainboard/hp/z220_sff_workstation/Makefile.inc +++ b/src/mainboard/hp/z220_sff_workstation/Makefile.inc @@ -1,2 +1,3 @@ +bootblock-y += gpio.c romstage-y += gpio.c ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads diff --git a/src/mainboard/intel/dcp847ske/Makefile.inc b/src/mainboard/intel/dcp847ske/Makefile.inc index 96bac06a0a..ec86d8455d 100644 --- a/src/mainboard/intel/dcp847ske/Makefile.inc +++ b/src/mainboard/intel/dcp847ske/Makefile.inc @@ -1,4 +1,5 @@ romstage-y += early_southbridge.c +bootblock-y += gpio.c romstage-y += gpio.c ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads smm-y += smihandler.c diff --git a/src/mainboard/intel/emeraldlake2/Makefile.inc b/src/mainboard/intel/emeraldlake2/Makefile.inc index b3bf53f028..974241dcc2 100644 --- a/src/mainboard/intel/emeraldlake2/Makefile.inc +++ b/src/mainboard/intel/emeraldlake2/Makefile.inc @@ -15,4 +15,5 @@ romstage-y += chromeos.c ramstage-y += chromeos.c +bootblock-y += gpio.c romstage-y += gpio.c diff --git a/src/mainboard/kontron/ktqm77/Makefile.inc b/src/mainboard/kontron/ktqm77/Makefile.inc index ea035d3876..620a9c06a2 100644 --- a/src/mainboard/kontron/ktqm77/Makefile.inc +++ b/src/mainboard/kontron/ktqm77/Makefile.inc @@ -1,3 +1,4 @@ +bootblock-y += gpio.c romstage-y += gpio.c ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads diff --git a/src/mainboard/lenovo/l520/Makefile.inc b/src/mainboard/lenovo/l520/Makefile.inc index 2ce116f90c..14cd059011 100644 --- a/src/mainboard/lenovo/l520/Makefile.inc +++ b/src/mainboard/lenovo/l520/Makefile.inc @@ -14,6 +14,7 @@ ## romstage-y += romstage.c +bootblock-y += gpio.c romstage-y += gpio.c smm-y += smihandler.c diff --git a/src/mainboard/lenovo/s230u/Makefile.inc b/src/mainboard/lenovo/s230u/Makefile.inc index 88626a275a..aa4c4f879d 100644 --- a/src/mainboard/lenovo/s230u/Makefile.inc +++ b/src/mainboard/lenovo/s230u/Makefile.inc @@ -1,3 +1,4 @@ +bootblock-y += gpio.c romstage-y += gpio.c ramstage-y += ec.c smm-y += smihandler.c diff --git a/src/mainboard/lenovo/t420/Makefile.inc b/src/mainboard/lenovo/t420/Makefile.inc index 30cf715194..3914f51561 100644 --- a/src/mainboard/lenovo/t420/Makefile.inc +++ b/src/mainboard/lenovo/t420/Makefile.inc @@ -14,6 +14,7 @@ ## smm-y += smihandler.c +bootblock-y += gpio.c romstage-y += gpio.c ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads diff --git a/src/mainboard/lenovo/t420s/Makefile.inc b/src/mainboard/lenovo/t420s/Makefile.inc index 30cf715194..3914f51561 100644 --- a/src/mainboard/lenovo/t420s/Makefile.inc +++ b/src/mainboard/lenovo/t420s/Makefile.inc @@ -14,6 +14,7 @@ ## smm-y += smihandler.c +bootblock-y += gpio.c romstage-y += gpio.c ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads diff --git a/src/mainboard/lenovo/t430/Makefile.inc b/src/mainboard/lenovo/t430/Makefile.inc index 558ab0a966..409d4842a9 100644 --- a/src/mainboard/lenovo/t430/Makefile.inc +++ b/src/mainboard/lenovo/t430/Makefile.inc @@ -1,4 +1,5 @@ romstage-y += romstage.c +bootblock-y += gpio.c romstage-y += gpio.c smm-y += smihandler.c diff --git a/src/mainboard/lenovo/t430s/Makefile.inc b/src/mainboard/lenovo/t430s/Makefile.inc index 4008f5ab07..425047fe44 100644 --- a/src/mainboard/lenovo/t430s/Makefile.inc +++ b/src/mainboard/lenovo/t430s/Makefile.inc @@ -14,6 +14,7 @@ ## smm-y += smihandler.c +bootblock-y += variants/$(VARIANT_DIR)/gpio.c romstage-y += variants/$(VARIANT_DIR)/gpio.c romstage-y += variants/$(VARIANT_DIR)/romstage.c ramstage-y += variants/$(VARIANT_DIR)/hda_verb.c diff --git a/src/mainboard/lenovo/t520/Makefile.inc b/src/mainboard/lenovo/t520/Makefile.inc index ee4669c055..5310bbf530 100644 --- a/src/mainboard/lenovo/t520/Makefile.inc +++ b/src/mainboard/lenovo/t520/Makefile.inc @@ -14,6 +14,7 @@ ## smm-y += smihandler.c +bootblock-y += variants/$(VARIANT_DIR)/gpio.c romstage-y += variants/$(VARIANT_DIR)/gpio.c romstage-y += variants/$(VARIANT_DIR)/romstage.c ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads diff --git a/src/mainboard/lenovo/t530/Makefile.inc b/src/mainboard/lenovo/t530/Makefile.inc index ee4669c055..5310bbf530 100644 --- a/src/mainboard/lenovo/t530/Makefile.inc +++ b/src/mainboard/lenovo/t530/Makefile.inc @@ -14,6 +14,7 @@ ## smm-y += smihandler.c +bootblock-y += variants/$(VARIANT_DIR)/gpio.c romstage-y += variants/$(VARIANT_DIR)/gpio.c romstage-y += variants/$(VARIANT_DIR)/romstage.c ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads diff --git a/src/mainboard/lenovo/x131e/Makefile.inc b/src/mainboard/lenovo/x131e/Makefile.inc index 7a00ccebd7..4fbf73bbd3 100644 --- a/src/mainboard/lenovo/x131e/Makefile.inc +++ b/src/mainboard/lenovo/x131e/Makefile.inc @@ -13,6 +13,7 @@ ## GNU General Public License for more details. ## +bootblock-y += gpio.c romstage-y += gpio.c ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads diff --git a/src/mainboard/lenovo/x1_carbon_gen1/Makefile.inc b/src/mainboard/lenovo/x1_carbon_gen1/Makefile.inc index 63b41a49a2..8ce77fc77d 100644 --- a/src/mainboard/lenovo/x1_carbon_gen1/Makefile.inc +++ b/src/mainboard/lenovo/x1_carbon_gen1/Makefile.inc @@ -16,6 +16,7 @@ subdirs-y += spd smm-y += smihandler.c +bootblock-y += gpio.c romstage-y += gpio.c ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads diff --git a/src/mainboard/lenovo/x220/Makefile.inc b/src/mainboard/lenovo/x220/Makefile.inc index a1cbc4cea5..c0ba457c57 100644 --- a/src/mainboard/lenovo/x220/Makefile.inc +++ b/src/mainboard/lenovo/x220/Makefile.inc @@ -14,6 +14,7 @@ ## smm-y += smihandler.c +bootblock-y += variants/$(VARIANT_DIR)/gpio.c romstage-y += variants/$(VARIANT_DIR)/gpio.c romstage-y += variants/$(VARIANT_DIR)/romstage.c diff --git a/src/mainboard/lenovo/x230/Makefile.inc b/src/mainboard/lenovo/x230/Makefile.inc index 30cf715194..3914f51561 100644 --- a/src/mainboard/lenovo/x230/Makefile.inc +++ b/src/mainboard/lenovo/x230/Makefile.inc @@ -14,6 +14,7 @@ ## smm-y += smihandler.c +bootblock-y += gpio.c romstage-y += gpio.c ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads diff --git a/src/mainboard/msi/ms7707/Makefile.inc b/src/mainboard/msi/ms7707/Makefile.inc index 3dae61e8a8..0ec849f5b5 100644 --- a/src/mainboard/msi/ms7707/Makefile.inc +++ b/src/mainboard/msi/ms7707/Makefile.inc @@ -1 +1,2 @@ +bootblock-y += gpio.c romstage-y += gpio.c diff --git a/src/mainboard/roda/rv11/Makefile.inc b/src/mainboard/roda/rv11/Makefile.inc index 5b5ca65a52..422b448e24 100644 --- a/src/mainboard/roda/rv11/Makefile.inc +++ b/src/mainboard/roda/rv11/Makefile.inc @@ -13,6 +13,7 @@ ## GNU General Public License for more details. ## +bootblock-y += gpio.c romstage-y += gpio.c romstage-y += variants/$(VARIANT_DIR)/romstage.c diff --git a/src/mainboard/samsung/lumpy/Makefile.inc b/src/mainboard/samsung/lumpy/Makefile.inc index 7f8f9663d7..3e28bd4878 100644 --- a/src/mainboard/samsung/lumpy/Makefile.inc +++ b/src/mainboard/samsung/lumpy/Makefile.inc @@ -27,6 +27,7 @@ $(SPD_BIN): cbfs-files-y += spd.bin spd.bin-file := $(SPD_BIN) spd.bin-type := spd +bootblock-y += gpio.c romstage-y += gpio.c ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads diff --git a/src/mainboard/samsung/stumpy/Makefile.inc b/src/mainboard/samsung/stumpy/Makefile.inc index a91a06193a..497accadb9 100644 --- a/src/mainboard/samsung/stumpy/Makefile.inc +++ b/src/mainboard/samsung/stumpy/Makefile.inc @@ -15,6 +15,7 @@ romstage-y += chromeos.c ramstage-y += chromeos.c +bootblock-y += gpio.c romstage-y += gpio.c ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads diff --git a/src/mainboard/sapphire/pureplatinumh61/Makefile.inc b/src/mainboard/sapphire/pureplatinumh61/Makefile.inc index 7c555f9c32..4cf022a474 100644 --- a/src/mainboard/sapphire/pureplatinumh61/Makefile.inc +++ b/src/mainboard/sapphire/pureplatinumh61/Makefile.inc @@ -14,6 +14,7 @@ # GNU General Public License for more details. # +bootblock-y += gpio.c romstage-y += gpio.c ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads diff --git a/src/northbridge/intel/sandybridge/Kconfig b/src/northbridge/intel/sandybridge/Kconfig index 288dd093bf..0502b50014 100644 --- a/src/northbridge/intel/sandybridge/Kconfig +++ b/src/northbridge/intel/sandybridge/Kconfig @@ -62,10 +62,6 @@ config VGA_BIOS_ID string default "8086,0106" -config BOOTBLOCK_NORTHBRIDGE_INIT - string - default "northbridge/intel/sandybridge/bootblock.c" - config MMCONF_BASE_ADDRESS hex default 0xf0000000 diff --git a/src/northbridge/intel/sandybridge/Makefile.inc b/src/northbridge/intel/sandybridge/Makefile.inc index 77d1fdbb84..7390d2b40b 100644 --- a/src/northbridge/intel/sandybridge/Makefile.inc +++ b/src/northbridge/intel/sandybridge/Makefile.inc @@ -15,6 +15,8 @@ ifeq ($(CONFIG_NORTHBRIDGE_INTEL_SANDYBRIDGE),y) +bootblock-y += bootblock.c + ramstage-y += memmap.c ramstage-y += northbridge.c ramstage-y += pcie.c @@ -44,7 +46,6 @@ mrc.bin-type := mrc endif romstage-y += romstage.c romstage-y += early_init.c -romstage-y += ../../../arch/x86/walkcbfs.S smm-y += finalize.c diff --git a/src/northbridge/intel/sandybridge/bootblock.c b/src/northbridge/intel/sandybridge/bootblock.c index 15e2de1bcc..40819bf7eb 100644 --- a/src/northbridge/intel/sandybridge/bootblock.c +++ b/src/northbridge/intel/sandybridge/bootblock.c @@ -12,11 +12,10 @@ */ #include +#include +#include "sandybridge.h" -/* Just re-define this instead of including sandybridge.h. It blows up romcc. */ -#define PCIEXBAR 0x60 - -static void bootblock_northbridge_init(void) +void bootblock_early_northbridge_init(void) { uint32_t reg; diff --git a/src/southbridge/intel/bd82x6x/Kconfig b/src/southbridge/intel/bd82x6x/Kconfig index c01e2b9eed..1c7e9b7da6 100644 --- a/src/southbridge/intel/bd82x6x/Kconfig +++ b/src/southbridge/intel/bd82x6x/Kconfig @@ -57,10 +57,6 @@ config DRAM_RESET_GATE_GPIO int default 60 -config BOOTBLOCK_SOUTHBRIDGE_INIT - string - default "southbridge/intel/bd82x6x/bootblock.c" - config SERIRQ_CONTINUOUS_MODE bool default n diff --git a/src/southbridge/intel/bd82x6x/Makefile.inc b/src/southbridge/intel/bd82x6x/Makefile.inc index b23fa7a327..5140d23388 100644 --- a/src/southbridge/intel/bd82x6x/Makefile.inc +++ b/src/southbridge/intel/bd82x6x/Makefile.inc @@ -15,6 +15,9 @@ ifeq ($(CONFIG_SOUTHBRIDGE_INTEL_C216)$(CONFIG_SOUTHBRIDGE_INTEL_BD82X6X),y) +bootblock-y += bootblock.c +bootblock-y += early_pch.c + ramstage-y += pch.c ramstage-y += azalia.c ramstage-y += lpc.c diff --git a/src/southbridge/intel/bd82x6x/bootblock.c b/src/southbridge/intel/bd82x6x/bootblock.c index 0086fe3281..1a8242f8d4 100644 --- a/src/southbridge/intel/bd82x6x/bootblock.c +++ b/src/southbridge/intel/bd82x6x/bootblock.c @@ -13,6 +13,7 @@ * GNU General Public License for more details. */ +#include #include #include "pch.h" @@ -32,18 +33,8 @@ static void enable_spi_prefetch(void) static void enable_port80_on_lpc(void) { - pci_devfn_t dev = PCH_LPC_DEV; - /* Enable port 80 POST on LPC */ - pci_write_config32(dev, RCBA, (uintptr_t)DEFAULT_RCBA | 1); -#if 0 RCBA32(GCS) &= (~0x04); -#else - volatile u32 *gcs = (volatile u32 *)(DEFAULT_RCBA + GCS); - u32 reg32 = *gcs; - reg32 = reg32 & ~0x04; - *gcs = reg32; -#endif } static void set_spi_speed(void) @@ -66,9 +57,12 @@ static void set_spi_speed(void) RCBA8(0x3893) = ssfc; } -static void bootblock_southbridge_init(void) +void bootblock_early_southbridge_init(void) { enable_spi_prefetch(); + + early_pch_init(); + enable_port80_on_lpc(); set_spi_speed(); From 59eb2fdb6b06618311ef118996ca8c1d28a85ffc Mon Sep 17 00:00:00 2001 From: Arthur Heymans Date: Sat, 16 Nov 2019 23:50:01 +0100 Subject: [PATCH 0226/1242] ec/hp/kbc1126: Include early_init.c in bootblock Change-Id: I198709efe1eb5d2022d0fbd640901238e696eaa6 Signed-off-by: Arthur Heymans Reviewed-on: https://review.coreboot.org/c/coreboot/+/36885 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Rudolph --- src/ec/hp/kbc1126/Makefile.inc | 1 + 1 file changed, 1 insertion(+) diff --git a/src/ec/hp/kbc1126/Makefile.inc b/src/ec/hp/kbc1126/Makefile.inc index 83b78f0112..a70a223d24 100644 --- a/src/ec/hp/kbc1126/Makefile.inc +++ b/src/ec/hp/kbc1126/Makefile.inc @@ -53,6 +53,7 @@ ifeq ($(CONFIG_KBC1126_FIRMWARE),) endif ramstage-y += ec.c +bootblock-y += early_init.c romstage-y += early_init.c endif From fa5d0f835b1f3bb8907e616913cbf7b91d09ef26 Mon Sep 17 00:00:00 2001 From: Arthur Heymans Date: Tue, 12 Nov 2019 19:11:50 +0100 Subject: [PATCH 0227/1242] nb/intel/sandybridge: Set up console in bootblock Change-Id: Ia041b63201b2a4a2fe6ab11e3497c460f88061d1 Signed-off-by: Arthur Heymans Reviewed-on: https://review.coreboot.org/c/coreboot/+/36784 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber --- src/cpu/intel/model_206ax/Kconfig | 1 - src/mainboard/apple/macbookair4_2/Makefile.inc | 2 ++ .../apple/macbookair4_2/{romstage.c => early_init.c} | 4 ---- src/mainboard/asrock/b75pro3-m/Makefile.inc | 2 ++ src/mainboard/asrock/b75pro3-m/{romstage.c => early_init.c} | 3 ++- src/mainboard/asus/h61m-cs/Makefile.inc | 2 ++ src/mainboard/asus/h61m-cs/{romstage.c => early_init.c} | 3 ++- src/mainboard/asus/maximus_iv_gene-z/Makefile.inc | 2 ++ .../asus/maximus_iv_gene-z/{romstage.c => early_init.c} | 3 ++- src/mainboard/asus/p8h61-m_lx/Makefile.inc | 2 ++ src/mainboard/asus/p8h61-m_lx/{romstage.c => early_init.c} | 3 ++- src/mainboard/asus/p8h61-m_pro/Makefile.inc | 2 ++ src/mainboard/asus/p8h61-m_pro/{romstage.c => early_init.c} | 3 ++- src/mainboard/asus/p8z77-m_pro/Makefile.inc | 2 ++ src/mainboard/asus/p8z77-m_pro/{romstage.c => early_init.c} | 3 ++- src/mainboard/compulab/intense_pc/Makefile.inc | 2 ++ .../compulab/intense_pc/{romstage.c => early_init.c} | 3 ++- src/mainboard/gigabyte/ga-b75m-d3h/Makefile.inc | 2 ++ .../gigabyte/ga-b75m-d3h/{romstage.c => early_init.c} | 3 ++- src/mainboard/gigabyte/ga-h61m-s2pv/Makefile.inc | 2 ++ .../gigabyte/ga-h61m-s2pv/{romstage.c => early_init.c} | 3 ++- src/mainboard/google/butterfly/Makefile.inc | 2 ++ src/mainboard/google/butterfly/{romstage.c => early_init.c} | 5 ----- src/mainboard/google/link/Makefile.inc | 2 ++ src/mainboard/google/link/{romstage.c => early_init.c} | 4 ---- src/mainboard/google/parrot/Makefile.inc | 2 ++ src/mainboard/google/parrot/{romstage.c => early_init.c} | 4 ---- src/mainboard/google/stout/Makefile.inc | 2 ++ src/mainboard/google/stout/{romstage.c => early_init.c} | 4 ---- src/mainboard/hp/2570p/Makefile.inc | 2 ++ src/mainboard/hp/2570p/{romstage.c => early_init.c} | 3 ++- src/mainboard/hp/2760p/Makefile.inc | 2 ++ src/mainboard/hp/2760p/{romstage.c => early_init.c} | 3 ++- src/mainboard/hp/8460p/Makefile.inc | 2 ++ src/mainboard/hp/8460p/{romstage.c => early_init.c} | 3 ++- src/mainboard/hp/8470p/Makefile.inc | 2 ++ src/mainboard/hp/8470p/{romstage.c => early_init.c} | 3 ++- src/mainboard/hp/8770w/Makefile.inc | 2 ++ src/mainboard/hp/8770w/{romstage.c => early_init.c} | 3 ++- src/mainboard/hp/compaq_8200_elite_sff/Makefile.inc | 2 ++ .../hp/compaq_8200_elite_sff/{romstage.c => early_init.c} | 3 ++- src/mainboard/hp/folio_9470m/Makefile.inc | 2 ++ src/mainboard/hp/folio_9470m/{romstage.c => early_init.c} | 3 ++- src/mainboard/hp/revolve_810_g1/Makefile.inc | 2 ++ .../hp/revolve_810_g1/{romstage.c => early_init.c} | 3 ++- src/mainboard/hp/z220_sff_workstation/Makefile.inc | 2 ++ .../hp/z220_sff_workstation/{romstage.c => early_init.c} | 3 ++- src/mainboard/intel/dcp847ske/Makefile.inc | 1 + src/mainboard/intel/dcp847ske/early_southbridge.c | 3 ++- src/mainboard/intel/emeraldlake2/Makefile.inc | 2 ++ .../intel/emeraldlake2/{romstage.c => early_init.c} | 3 ++- src/mainboard/kontron/ktqm77/Makefile.inc | 2 ++ src/mainboard/kontron/ktqm77/{romstage.c => early_init.c} | 3 ++- src/mainboard/lenovo/l520/Makefile.inc | 3 ++- src/mainboard/lenovo/l520/{romstage.c => early_init.c} | 4 ---- src/mainboard/lenovo/s230u/Makefile.inc | 2 ++ src/mainboard/lenovo/s230u/{romstage.c => early_init.c} | 4 ---- src/mainboard/lenovo/t420/Makefile.inc | 2 ++ src/mainboard/lenovo/t420/{romstage.c => early_init.c} | 4 ---- src/mainboard/lenovo/t420s/Makefile.inc | 2 ++ src/mainboard/lenovo/t420s/{romstage.c => early_init.c} | 4 ---- src/mainboard/lenovo/t430/Makefile.inc | 3 ++- src/mainboard/lenovo/t430/{romstage.c => early_init.c} | 4 ---- src/mainboard/lenovo/t430s/Makefile.inc | 2 ++ src/mainboard/lenovo/t430s/{romstage.c => early_init.c} | 4 ---- src/mainboard/lenovo/t520/Makefile.inc | 2 ++ src/mainboard/lenovo/t520/{romstage.c => early_init.c} | 4 ---- src/mainboard/lenovo/t530/Makefile.inc | 2 ++ src/mainboard/lenovo/t530/{romstage.c => early_init.c} | 4 ---- src/mainboard/lenovo/x131e/Makefile.inc | 2 ++ src/mainboard/lenovo/x131e/{romstage.c => early_init.c} | 4 ---- src/mainboard/lenovo/x1_carbon_gen1/Makefile.inc | 2 ++ .../lenovo/x1_carbon_gen1/{romstage.c => early_init.c} | 4 ---- src/mainboard/lenovo/x220/Makefile.inc | 2 ++ src/mainboard/lenovo/x220/{romstage.c => early_init.c} | 4 ---- src/mainboard/lenovo/x230/Makefile.inc | 2 ++ src/mainboard/lenovo/x230/{romstage.c => early_init.c} | 4 ---- src/mainboard/msi/ms7707/Makefile.inc | 2 ++ src/mainboard/msi/ms7707/{romstage.c => early_init.c} | 4 ---- src/mainboard/roda/rv11/Makefile.inc | 5 ++++- src/mainboard/roda/rv11/{romstage.c => early_init.c} | 0 .../roda/rv11/variants/rv11/{romstage.c => early_init.c} | 4 ---- .../roda/rv11/variants/rw11/{romstage.c => early_init.c} | 3 ++- src/mainboard/samsung/lumpy/Makefile.inc | 2 ++ src/mainboard/samsung/lumpy/{romstage.c => early_init.c} | 4 ---- src/mainboard/samsung/stumpy/Makefile.inc | 2 ++ src/mainboard/samsung/stumpy/{romstage.c => early_init.c} | 3 ++- src/mainboard/sapphire/pureplatinumh61/Makefile.inc | 2 ++ .../sapphire/pureplatinumh61/{romstage.c => early_init.c} | 4 ---- src/northbridge/intel/sandybridge/romstage.c | 6 ------ src/northbridge/intel/sandybridge/sandybridge.h | 1 - 91 files changed, 133 insertions(+), 119 deletions(-) rename src/mainboard/apple/macbookair4_2/{romstage.c => early_init.c} (97%) rename src/mainboard/asrock/b75pro3-m/{romstage.c => early_init.c} (95%) rename src/mainboard/asus/h61m-cs/{romstage.c => early_init.c} (95%) rename src/mainboard/asus/maximus_iv_gene-z/{romstage.c => early_init.c} (96%) rename src/mainboard/asus/p8h61-m_lx/{romstage.c => early_init.c} (95%) rename src/mainboard/asus/p8h61-m_pro/{romstage.c => early_init.c} (96%) rename src/mainboard/asus/p8z77-m_pro/{romstage.c => early_init.c} (98%) rename src/mainboard/compulab/intense_pc/{romstage.c => early_init.c} (97%) rename src/mainboard/gigabyte/ga-b75m-d3h/{romstage.c => early_init.c} (97%) rename src/mainboard/gigabyte/ga-h61m-s2pv/{romstage.c => early_init.c} (95%) rename src/mainboard/google/butterfly/{romstage.c => early_init.c} (99%) rename src/mainboard/google/link/{romstage.c => early_init.c} (99%) rename src/mainboard/google/parrot/{romstage.c => early_init.c} (99%) rename src/mainboard/google/stout/{romstage.c => early_init.c} (99%) rename src/mainboard/hp/2570p/{romstage.c => early_init.c} (95%) rename src/mainboard/hp/2760p/{romstage.c => early_init.c} (94%) rename src/mainboard/hp/8460p/{romstage.c => early_init.c} (95%) rename src/mainboard/hp/8470p/{romstage.c => early_init.c} (95%) rename src/mainboard/hp/8770w/{romstage.c => early_init.c} (96%) rename src/mainboard/hp/compaq_8200_elite_sff/{romstage.c => early_init.c} (95%) rename src/mainboard/hp/folio_9470m/{romstage.c => early_init.c} (95%) rename src/mainboard/hp/revolve_810_g1/{romstage.c => early_init.c} (96%) rename src/mainboard/hp/z220_sff_workstation/{romstage.c => early_init.c} (95%) rename src/mainboard/intel/emeraldlake2/{romstage.c => early_init.c} (98%) rename src/mainboard/kontron/ktqm77/{romstage.c => early_init.c} (98%) rename src/mainboard/lenovo/l520/{romstage.c => early_init.c} (96%) rename src/mainboard/lenovo/s230u/{romstage.c => early_init.c} (98%) rename src/mainboard/lenovo/t420/{romstage.c => early_init.c} (98%) rename src/mainboard/lenovo/t420s/{romstage.c => early_init.c} (98%) rename src/mainboard/lenovo/t430/{romstage.c => early_init.c} (97%) rename src/mainboard/lenovo/t430s/{romstage.c => early_init.c} (95%) rename src/mainboard/lenovo/t520/{romstage.c => early_init.c} (98%) rename src/mainboard/lenovo/t530/{romstage.c => early_init.c} (97%) rename src/mainboard/lenovo/x131e/{romstage.c => early_init.c} (97%) rename src/mainboard/lenovo/x1_carbon_gen1/{romstage.c => early_init.c} (98%) rename src/mainboard/lenovo/x220/{romstage.c => early_init.c} (98%) rename src/mainboard/lenovo/x230/{romstage.c => early_init.c} (97%) rename src/mainboard/msi/ms7707/{romstage.c => early_init.c} (97%) rename src/mainboard/roda/rv11/{romstage.c => early_init.c} (100%) rename src/mainboard/roda/rv11/variants/rv11/{romstage.c => early_init.c} (98%) rename src/mainboard/roda/rv11/variants/rw11/{romstage.c => early_init.c} (98%) rename src/mainboard/samsung/lumpy/{romstage.c => early_init.c} (99%) rename src/mainboard/samsung/stumpy/{romstage.c => early_init.c} (99%) rename src/mainboard/sapphire/pureplatinumh61/{romstage.c => early_init.c} (97%) diff --git a/src/cpu/intel/model_206ax/Kconfig b/src/cpu/intel/model_206ax/Kconfig index 223703eb84..f316329552 100644 --- a/src/cpu/intel/model_206ax/Kconfig +++ b/src/cpu/intel/model_206ax/Kconfig @@ -22,7 +22,6 @@ config CPU_SPECIFIC_OPTIONS select PARALLEL_MP select NO_FIXED_XIP_ROM_SIZE select C_ENVIRONMENT_BOOTBLOCK - select NO_BOOTBLOCK_CONSOLE config SMM_TSEG_SIZE hex diff --git a/src/mainboard/apple/macbookair4_2/Makefile.inc b/src/mainboard/apple/macbookair4_2/Makefile.inc index da821939cc..665a95f195 100644 --- a/src/mainboard/apple/macbookair4_2/Makefile.inc +++ b/src/mainboard/apple/macbookair4_2/Makefile.inc @@ -7,3 +7,5 @@ spd.bin-file := spd.bin spd.bin-type := spd ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads +bootblock-y += early_init.c +romstage-y += early_init.c diff --git a/src/mainboard/apple/macbookair4_2/romstage.c b/src/mainboard/apple/macbookair4_2/early_init.c similarity index 97% rename from src/mainboard/apple/macbookair4_2/romstage.c rename to src/mainboard/apple/macbookair4_2/early_init.c index f445eea28e..bfd070ca1c 100644 --- a/src/mainboard/apple/macbookair4_2/romstage.c +++ b/src/mainboard/apple/macbookair4_2/early_init.c @@ -49,10 +49,6 @@ const struct southbridge_usb_port mainboard_usb_ports[] = { { 1, 0, -1 }, }; -void mainboard_config_superio(void) -{ -} - void mainboard_get_spd(spd_raw_data *spd, bool id_only) { void *spd_file; diff --git a/src/mainboard/asrock/b75pro3-m/Makefile.inc b/src/mainboard/asrock/b75pro3-m/Makefile.inc index df00e3749e..598cd90e49 100644 --- a/src/mainboard/asrock/b75pro3-m/Makefile.inc +++ b/src/mainboard/asrock/b75pro3-m/Makefile.inc @@ -17,3 +17,5 @@ bootblock-y += gpio.c romstage-y += gpio.c ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads +bootblock-y += early_init.c +romstage-y += early_init.c diff --git a/src/mainboard/asrock/b75pro3-m/romstage.c b/src/mainboard/asrock/b75pro3-m/early_init.c similarity index 95% rename from src/mainboard/asrock/b75pro3-m/romstage.c rename to src/mainboard/asrock/b75pro3-m/early_init.c index 983de07ff7..296c2de0e7 100644 --- a/src/mainboard/asrock/b75pro3-m/romstage.c +++ b/src/mainboard/asrock/b75pro3-m/early_init.c @@ -14,6 +14,7 @@ * GNU General Public License for more details. */ +#include #include #include #include @@ -40,7 +41,7 @@ const struct southbridge_usb_port mainboard_usb_ports[] = { { 1, 0, 6 }, }; -void mainboard_config_superio(void) +void bootblock_mainboard_early_init(void) { /* Set GPIOs on superio, enable UART */ nuvoton_pnp_enter_conf_state(SERIAL_DEV); diff --git a/src/mainboard/asus/h61m-cs/Makefile.inc b/src/mainboard/asus/h61m-cs/Makefile.inc index af2b6742f0..f0b34f9840 100644 --- a/src/mainboard/asus/h61m-cs/Makefile.inc +++ b/src/mainboard/asus/h61m-cs/Makefile.inc @@ -1,3 +1,5 @@ bootblock-y += gpio.c romstage-y += gpio.c ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads +bootblock-y += early_init.c +romstage-y += early_init.c diff --git a/src/mainboard/asus/h61m-cs/romstage.c b/src/mainboard/asus/h61m-cs/early_init.c similarity index 95% rename from src/mainboard/asus/h61m-cs/romstage.c rename to src/mainboard/asus/h61m-cs/early_init.c index 2aa243f4e8..2720e7a676 100644 --- a/src/mainboard/asus/h61m-cs/romstage.c +++ b/src/mainboard/asus/h61m-cs/early_init.c @@ -15,6 +15,7 @@ * GNU General Public License for more details. */ +#include #include #include #include @@ -44,7 +45,7 @@ const struct southbridge_usb_port mainboard_usb_ports[] = { { 1, 0, 6 }, }; -void mainboard_config_superio(void) +void bootblock_mainboard_early_init(void) { nuvoton_pnp_enter_conf_state(SIO_DEV); pnp_set_logical_device(ACPI_DEV); diff --git a/src/mainboard/asus/maximus_iv_gene-z/Makefile.inc b/src/mainboard/asus/maximus_iv_gene-z/Makefile.inc index 0547b4d643..be8d9c3e85 100644 --- a/src/mainboard/asus/maximus_iv_gene-z/Makefile.inc +++ b/src/mainboard/asus/maximus_iv_gene-z/Makefile.inc @@ -17,3 +17,5 @@ bootblock-y += gpio.c romstage-y += gpio.c ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads +bootblock-y += early_init.c +romstage-y += early_init.c diff --git a/src/mainboard/asus/maximus_iv_gene-z/romstage.c b/src/mainboard/asus/maximus_iv_gene-z/early_init.c similarity index 96% rename from src/mainboard/asus/maximus_iv_gene-z/romstage.c rename to src/mainboard/asus/maximus_iv_gene-z/early_init.c index c1e3975294..4b4fbbe483 100644 --- a/src/mainboard/asus/maximus_iv_gene-z/romstage.c +++ b/src/mainboard/asus/maximus_iv_gene-z/early_init.c @@ -14,6 +14,7 @@ * GNU General Public License for more details. */ +#include #include #include #include @@ -40,7 +41,7 @@ const struct southbridge_usb_port mainboard_usb_ports[] = { { 1, 0, 6 }, }; -void mainboard_config_superio(void) +void bootblock_mainboard_early_init(void) { static const pnp_devfn_t GLOBAL_PSEUDO_DEV = PNP_DEV(0x2e, 0); static const pnp_devfn_t ACPI_DEV = PNP_DEV(0x2e, NCT6776_ACPI); diff --git a/src/mainboard/asus/p8h61-m_lx/Makefile.inc b/src/mainboard/asus/p8h61-m_lx/Makefile.inc index 9ee5136945..28f5e60f5d 100644 --- a/src/mainboard/asus/p8h61-m_lx/Makefile.inc +++ b/src/mainboard/asus/p8h61-m_lx/Makefile.inc @@ -17,3 +17,5 @@ bootblock-y += gpio.c romstage-y += gpio.c ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads +bootblock-y += early_init.c +romstage-y += early_init.c diff --git a/src/mainboard/asus/p8h61-m_lx/romstage.c b/src/mainboard/asus/p8h61-m_lx/early_init.c similarity index 95% rename from src/mainboard/asus/p8h61-m_lx/romstage.c rename to src/mainboard/asus/p8h61-m_lx/early_init.c index d3361919a7..7dc8cd5334 100644 --- a/src/mainboard/asus/p8h61-m_lx/romstage.c +++ b/src/mainboard/asus/p8h61-m_lx/early_init.c @@ -14,6 +14,7 @@ * GNU General Public License for more details. */ +#include #include #include #include @@ -47,7 +48,7 @@ void mainboard_pch_lpc_setup(void) CNF1_LPC_EN | KBC_LPC_EN | LPT_LPC_EN | COMA_LPC_EN); } -void mainboard_config_superio(void) +void bootblock_mainboard_early_init(void) { nuvoton_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); } diff --git a/src/mainboard/asus/p8h61-m_pro/Makefile.inc b/src/mainboard/asus/p8h61-m_pro/Makefile.inc index 620a9c06a2..e402ffa605 100644 --- a/src/mainboard/asus/p8h61-m_pro/Makefile.inc +++ b/src/mainboard/asus/p8h61-m_pro/Makefile.inc @@ -2,3 +2,5 @@ bootblock-y += gpio.c romstage-y += gpio.c ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads +bootblock-y += early_init.c +romstage-y += early_init.c diff --git a/src/mainboard/asus/p8h61-m_pro/romstage.c b/src/mainboard/asus/p8h61-m_pro/early_init.c similarity index 96% rename from src/mainboard/asus/p8h61-m_pro/romstage.c rename to src/mainboard/asus/p8h61-m_pro/early_init.c index ff5a67748d..4b02505bef 100644 --- a/src/mainboard/asus/p8h61-m_pro/romstage.c +++ b/src/mainboard/asus/p8h61-m_pro/early_init.c @@ -13,6 +13,7 @@ * GNU General Public License for more details. */ +#include #include #include #include @@ -49,7 +50,7 @@ const struct southbridge_usb_port mainboard_usb_ports[] = { { 1, 0, 6 }, }; -void mainboard_config_superio(void) +void bootblock_mainboard_early_init(void) { /* Enable UART */ nuvoton_pnp_enter_conf_state(GLOBAL_DEV); diff --git a/src/mainboard/asus/p8z77-m_pro/Makefile.inc b/src/mainboard/asus/p8z77-m_pro/Makefile.inc index 8fc0eadbcc..e9fbd3cf88 100644 --- a/src/mainboard/asus/p8z77-m_pro/Makefile.inc +++ b/src/mainboard/asus/p8z77-m_pro/Makefile.inc @@ -18,3 +18,5 @@ bootblock-y += gpio.c romstage-y += gpio.c ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads +bootblock-y += early_init.c +romstage-y += early_init.c diff --git a/src/mainboard/asus/p8z77-m_pro/romstage.c b/src/mainboard/asus/p8z77-m_pro/early_init.c similarity index 98% rename from src/mainboard/asus/p8z77-m_pro/romstage.c rename to src/mainboard/asus/p8z77-m_pro/early_init.c index 4963c3102c..ce479a8609 100644 --- a/src/mainboard/asus/p8z77-m_pro/romstage.c +++ b/src/mainboard/asus/p8z77-m_pro/early_init.c @@ -13,6 +13,7 @@ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. */ +#include #include #include #include @@ -48,7 +49,7 @@ const struct southbridge_usb_port mainboard_usb_ports[] = { { 0, 2, 6 } /* Port 13: Unused. Asus propietary DEBUG_PORT ??? */ }; -void mainboard_config_superio(void) +void bootblock_mainboard_early_init(void) { /* Setup COM/UART */ nuvoton_pnp_enter_conf_state(GLOBAL_DEV); diff --git a/src/mainboard/compulab/intense_pc/Makefile.inc b/src/mainboard/compulab/intense_pc/Makefile.inc index 620a9c06a2..e402ffa605 100644 --- a/src/mainboard/compulab/intense_pc/Makefile.inc +++ b/src/mainboard/compulab/intense_pc/Makefile.inc @@ -2,3 +2,5 @@ bootblock-y += gpio.c romstage-y += gpio.c ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads +bootblock-y += early_init.c +romstage-y += early_init.c diff --git a/src/mainboard/compulab/intense_pc/romstage.c b/src/mainboard/compulab/intense_pc/early_init.c similarity index 97% rename from src/mainboard/compulab/intense_pc/romstage.c rename to src/mainboard/compulab/intense_pc/early_init.c index 4176703ac7..73acc46802 100644 --- a/src/mainboard/compulab/intense_pc/romstage.c +++ b/src/mainboard/compulab/intense_pc/early_init.c @@ -13,6 +13,7 @@ * GNU General Public License for more details. */ +#include #include #include #include @@ -60,7 +61,7 @@ const struct southbridge_usb_port mainboard_usb_ports[] = { { 1, 0, 6 }, }; -void mainboard_config_superio(void) +void bootblock_mainboard_early_init(void) { const u16 port = SIO_PORT; const u16 runtime_port = 0x180; diff --git a/src/mainboard/gigabyte/ga-b75m-d3h/Makefile.inc b/src/mainboard/gigabyte/ga-b75m-d3h/Makefile.inc index f5b33bd644..0abe48248e 100644 --- a/src/mainboard/gigabyte/ga-b75m-d3h/Makefile.inc +++ b/src/mainboard/gigabyte/ga-b75m-d3h/Makefile.inc @@ -21,3 +21,5 @@ ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += variants/$(VARIANT_DIR)/gma-mainb subdirs-y += variants/$(VARIANT_DIR) CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/variants/$(VARIANT_DIR)/include +bootblock-y += early_init.c +romstage-y += early_init.c diff --git a/src/mainboard/gigabyte/ga-b75m-d3h/romstage.c b/src/mainboard/gigabyte/ga-b75m-d3h/early_init.c similarity index 97% rename from src/mainboard/gigabyte/ga-b75m-d3h/romstage.c rename to src/mainboard/gigabyte/ga-b75m-d3h/early_init.c index a5d4c35b34..0a863fffd2 100644 --- a/src/mainboard/gigabyte/ga-b75m-d3h/romstage.c +++ b/src/mainboard/gigabyte/ga-b75m-d3h/early_init.c @@ -13,6 +13,7 @@ * GNU General Public License for more details. */ +#include #include #include #include @@ -30,7 +31,7 @@ void mainboard_pch_lpc_setup(void) pci_write_config32(PCH_LPC_DEV, ETR3, 0x10000); } -void mainboard_config_superio(void) +void bootblock_mainboard_early_init(void) { /* Initialize SuperIO */ ite_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); diff --git a/src/mainboard/gigabyte/ga-h61m-s2pv/Makefile.inc b/src/mainboard/gigabyte/ga-h61m-s2pv/Makefile.inc index 5166ce06af..9916927d25 100644 --- a/src/mainboard/gigabyte/ga-h61m-s2pv/Makefile.inc +++ b/src/mainboard/gigabyte/ga-h61m-s2pv/Makefile.inc @@ -3,3 +3,5 @@ romstage-y += variants/$(VARIANT_DIR)/gpio.c ramstage-y += variants/$(VARIANT_DIR)/hda_verb.c ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads +bootblock-y += early_init.c +romstage-y += early_init.c diff --git a/src/mainboard/gigabyte/ga-h61m-s2pv/romstage.c b/src/mainboard/gigabyte/ga-h61m-s2pv/early_init.c similarity index 95% rename from src/mainboard/gigabyte/ga-h61m-s2pv/romstage.c rename to src/mainboard/gigabyte/ga-h61m-s2pv/early_init.c index a68070fbe6..4157b09097 100644 --- a/src/mainboard/gigabyte/ga-h61m-s2pv/romstage.c +++ b/src/mainboard/gigabyte/ga-h61m-s2pv/early_init.c @@ -13,6 +13,7 @@ * GNU General Public License for more details. */ +#include #include #include #include @@ -40,7 +41,7 @@ const struct southbridge_usb_port mainboard_usb_ports[] = { { 1, 0, 6 }, }; -void mainboard_config_superio(void) +void bootblock_mainboard_early_init(void) { if (!CONFIG(NO_UART_ON_SUPERIO)) { /* Enable serial port */ diff --git a/src/mainboard/google/butterfly/Makefile.inc b/src/mainboard/google/butterfly/Makefile.inc index fa9a4a9068..18f200647a 100644 --- a/src/mainboard/google/butterfly/Makefile.inc +++ b/src/mainboard/google/butterfly/Makefile.inc @@ -23,3 +23,5 @@ romstage-y += gpio.c smm-y += mainboard_smi.c ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads +bootblock-y += early_init.c +romstage-y += early_init.c diff --git a/src/mainboard/google/butterfly/romstage.c b/src/mainboard/google/butterfly/early_init.c similarity index 99% rename from src/mainboard/google/butterfly/romstage.c rename to src/mainboard/google/butterfly/early_init.c index e1d948d89f..d6566d1b09 100644 --- a/src/mainboard/google/butterfly/romstage.c +++ b/src/mainboard/google/butterfly/early_init.c @@ -112,11 +112,6 @@ void mainboard_get_spd(spd_raw_data *spd, bool id_only) read_spd(&spd[2], 0x52, id_only); } -void mainboard_config_superio(void) -{ -} - - void mainboard_fill_pei_data(struct pei_data *pei_data) { struct pei_data pei_data_template = { diff --git a/src/mainboard/google/link/Makefile.inc b/src/mainboard/google/link/Makefile.inc index 724150c138..22c28c8059 100644 --- a/src/mainboard/google/link/Makefile.inc +++ b/src/mainboard/google/link/Makefile.inc @@ -42,3 +42,5 @@ spd.bin-file := $(SPD_BIN) spd.bin-type := spd bootblock-y += gpio.c romstage-y += gpio.c +bootblock-y += early_init.c +romstage-y += early_init.c diff --git a/src/mainboard/google/link/romstage.c b/src/mainboard/google/link/early_init.c similarity index 99% rename from src/mainboard/google/link/romstage.c rename to src/mainboard/google/link/early_init.c index 3fd90e9b17..9d985e622c 100644 --- a/src/mainboard/google/link/romstage.c +++ b/src/mainboard/google/link/early_init.c @@ -201,7 +201,3 @@ int mainboard_should_reset_usb(int s3resume) { return !s3resume; } - -void mainboard_config_superio(void) -{ -} diff --git a/src/mainboard/google/parrot/Makefile.inc b/src/mainboard/google/parrot/Makefile.inc index 67324bdff0..a2ed11e580 100644 --- a/src/mainboard/google/parrot/Makefile.inc +++ b/src/mainboard/google/parrot/Makefile.inc @@ -21,3 +21,5 @@ bootblock-y += gpio.c romstage-y += gpio.c ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads +bootblock-y += early_init.c +romstage-y += early_init.c diff --git a/src/mainboard/google/parrot/romstage.c b/src/mainboard/google/parrot/early_init.c similarity index 99% rename from src/mainboard/google/parrot/romstage.c rename to src/mainboard/google/parrot/early_init.c index caff3f5436..3c07dc8c54 100644 --- a/src/mainboard/google/parrot/romstage.c +++ b/src/mainboard/google/parrot/early_init.c @@ -155,10 +155,6 @@ void mainboard_get_spd(spd_raw_data *spd, bool id_only) read_spd(&spd[2], 0x52, id_only); } -void mainboard_config_superio(void) -{ -} - int mainboard_should_reset_usb(int s3resume) { return !s3resume; diff --git a/src/mainboard/google/stout/Makefile.inc b/src/mainboard/google/stout/Makefile.inc index 59ac22dbae..3add36258b 100644 --- a/src/mainboard/google/stout/Makefile.inc +++ b/src/mainboard/google/stout/Makefile.inc @@ -26,3 +26,5 @@ bootblock-y += gpio.c romstage-y += gpio.c ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads +bootblock-y += early_init.c +romstage-y += early_init.c diff --git a/src/mainboard/google/stout/romstage.c b/src/mainboard/google/stout/early_init.c similarity index 99% rename from src/mainboard/google/stout/romstage.c rename to src/mainboard/google/stout/early_init.c index d8e04eaa63..6ee982ad73 100644 --- a/src/mainboard/google/stout/romstage.c +++ b/src/mainboard/google/stout/early_init.c @@ -198,10 +198,6 @@ int mainboard_should_reset_usb(int s3resume) return !s3resume; } -void mainboard_config_superio(void) -{ -} - const struct southbridge_usb_port mainboard_usb_ports[] = { /* enabled usb oc pin length */ {1, 0, 0}, /* P0: USB 3.0 1 (OC0) */ diff --git a/src/mainboard/hp/2570p/Makefile.inc b/src/mainboard/hp/2570p/Makefile.inc index 4fbf73bbd3..1d258758be 100644 --- a/src/mainboard/hp/2570p/Makefile.inc +++ b/src/mainboard/hp/2570p/Makefile.inc @@ -17,3 +17,5 @@ bootblock-y += gpio.c romstage-y += gpio.c ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads +bootblock-y += early_init.c +romstage-y += early_init.c diff --git a/src/mainboard/hp/2570p/romstage.c b/src/mainboard/hp/2570p/early_init.c similarity index 95% rename from src/mainboard/hp/2570p/romstage.c rename to src/mainboard/hp/2570p/early_init.c index f1d1e905f3..226367a569 100644 --- a/src/mainboard/hp/2570p/romstage.c +++ b/src/mainboard/hp/2570p/early_init.c @@ -14,6 +14,7 @@ * GNU General Public License for more details. */ +#include #include #include #include @@ -37,7 +38,7 @@ const struct southbridge_usb_port mainboard_usb_ports[] = { { 0, 0, 6 }, }; -void mainboard_config_superio(void) +void bootblock_mainboard_early_init(void) { kbc1126_enter_conf(); kbc1126_mailbox_init(); diff --git a/src/mainboard/hp/2760p/Makefile.inc b/src/mainboard/hp/2760p/Makefile.inc index 4fbf73bbd3..1d258758be 100644 --- a/src/mainboard/hp/2760p/Makefile.inc +++ b/src/mainboard/hp/2760p/Makefile.inc @@ -17,3 +17,5 @@ bootblock-y += gpio.c romstage-y += gpio.c ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads +bootblock-y += early_init.c +romstage-y += early_init.c diff --git a/src/mainboard/hp/2760p/romstage.c b/src/mainboard/hp/2760p/early_init.c similarity index 94% rename from src/mainboard/hp/2760p/romstage.c rename to src/mainboard/hp/2760p/early_init.c index acf5b1895a..98806de9f4 100644 --- a/src/mainboard/hp/2760p/romstage.c +++ b/src/mainboard/hp/2760p/early_init.c @@ -13,6 +13,7 @@ * GNU General Public License for more details. */ +#include #include #include #include @@ -36,7 +37,7 @@ const struct southbridge_usb_port mainboard_usb_ports[] = { { 1, 1, 6 }, }; -void mainboard_config_superio(void) +void bootblock_mainboard_early_init(void) { kbc1126_enter_conf(); kbc1126_mailbox_init(); diff --git a/src/mainboard/hp/8460p/Makefile.inc b/src/mainboard/hp/8460p/Makefile.inc index 4fbf73bbd3..1d258758be 100644 --- a/src/mainboard/hp/8460p/Makefile.inc +++ b/src/mainboard/hp/8460p/Makefile.inc @@ -17,3 +17,5 @@ bootblock-y += gpio.c romstage-y += gpio.c ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads +bootblock-y += early_init.c +romstage-y += early_init.c diff --git a/src/mainboard/hp/8460p/romstage.c b/src/mainboard/hp/8460p/early_init.c similarity index 95% rename from src/mainboard/hp/8460p/romstage.c rename to src/mainboard/hp/8460p/early_init.c index 4e4b175366..9c2a4b1139 100644 --- a/src/mainboard/hp/8460p/romstage.c +++ b/src/mainboard/hp/8460p/early_init.c @@ -14,6 +14,7 @@ * GNU General Public License for more details. */ +#include #include #include #include @@ -40,7 +41,7 @@ const struct southbridge_usb_port mainboard_usb_ports[] = { { 1, 0, 6 }, /* docking */ }; -void mainboard_config_superio(void) +void bootblock_mainboard_early_init(void) { lpc47n217_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); kbc1126_enter_conf(); diff --git a/src/mainboard/hp/8470p/Makefile.inc b/src/mainboard/hp/8470p/Makefile.inc index 4fbf73bbd3..1d258758be 100644 --- a/src/mainboard/hp/8470p/Makefile.inc +++ b/src/mainboard/hp/8470p/Makefile.inc @@ -17,3 +17,5 @@ bootblock-y += gpio.c romstage-y += gpio.c ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads +bootblock-y += early_init.c +romstage-y += early_init.c diff --git a/src/mainboard/hp/8470p/romstage.c b/src/mainboard/hp/8470p/early_init.c similarity index 95% rename from src/mainboard/hp/8470p/romstage.c rename to src/mainboard/hp/8470p/early_init.c index 8c9b29ef01..8dbe15815d 100644 --- a/src/mainboard/hp/8470p/romstage.c +++ b/src/mainboard/hp/8470p/early_init.c @@ -13,6 +13,7 @@ * GNU General Public License for more details. */ +#include #include #include #include @@ -39,7 +40,7 @@ const struct southbridge_usb_port mainboard_usb_ports[] = { { 1, 0, 6 }, }; -void mainboard_config_superio(void) +void bootblock_mainboard_early_init(void) { lpc47n217_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); kbc1126_enter_conf(); diff --git a/src/mainboard/hp/8770w/Makefile.inc b/src/mainboard/hp/8770w/Makefile.inc index 910d6a6191..f4b387abed 100644 --- a/src/mainboard/hp/8770w/Makefile.inc +++ b/src/mainboard/hp/8770w/Makefile.inc @@ -15,3 +15,5 @@ bootblock-y += gpio.c romstage-y += gpio.c +bootblock-y += early_init.c +romstage-y += early_init.c diff --git a/src/mainboard/hp/8770w/romstage.c b/src/mainboard/hp/8770w/early_init.c similarity index 96% rename from src/mainboard/hp/8770w/romstage.c rename to src/mainboard/hp/8770w/early_init.c index 8eefe4d6a2..3bd2ed7f51 100644 --- a/src/mainboard/hp/8770w/romstage.c +++ b/src/mainboard/hp/8770w/early_init.c @@ -14,6 +14,7 @@ * GNU General Public License for more details. */ +#include #include #include #include @@ -40,7 +41,7 @@ const struct southbridge_usb_port mainboard_usb_ports[] = { { 1, 0, 6 }, /* Conn (eSATA Combo) */ }; -void mainboard_config_superio(void) +void bootblock_mainboard_early_init(void) { lpc47n217_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); kbc1126_enter_conf(); diff --git a/src/mainboard/hp/compaq_8200_elite_sff/Makefile.inc b/src/mainboard/hp/compaq_8200_elite_sff/Makefile.inc index af2b6742f0..f0b34f9840 100644 --- a/src/mainboard/hp/compaq_8200_elite_sff/Makefile.inc +++ b/src/mainboard/hp/compaq_8200_elite_sff/Makefile.inc @@ -1,3 +1,5 @@ bootblock-y += gpio.c romstage-y += gpio.c ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads +bootblock-y += early_init.c +romstage-y += early_init.c diff --git a/src/mainboard/hp/compaq_8200_elite_sff/romstage.c b/src/mainboard/hp/compaq_8200_elite_sff/early_init.c similarity index 95% rename from src/mainboard/hp/compaq_8200_elite_sff/romstage.c rename to src/mainboard/hp/compaq_8200_elite_sff/early_init.c index df581fe542..882a604899 100644 --- a/src/mainboard/hp/compaq_8200_elite_sff/romstage.c +++ b/src/mainboard/hp/compaq_8200_elite_sff/early_init.c @@ -16,6 +16,7 @@ * GNU General Public License for more details. */ +#include #include #include #include @@ -44,7 +45,7 @@ const struct southbridge_usb_port mainboard_usb_ports[] = { { 1, 0, -1 }, }; -void mainboard_config_superio(void) +void bootblock_mainboard_early_init(void) { if (CONFIG(CONSOLE_SERIAL)) nuvoton_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); diff --git a/src/mainboard/hp/folio_9470m/Makefile.inc b/src/mainboard/hp/folio_9470m/Makefile.inc index 4fbf73bbd3..1d258758be 100644 --- a/src/mainboard/hp/folio_9470m/Makefile.inc +++ b/src/mainboard/hp/folio_9470m/Makefile.inc @@ -17,3 +17,5 @@ bootblock-y += gpio.c romstage-y += gpio.c ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads +bootblock-y += early_init.c +romstage-y += early_init.c diff --git a/src/mainboard/hp/folio_9470m/romstage.c b/src/mainboard/hp/folio_9470m/early_init.c similarity index 95% rename from src/mainboard/hp/folio_9470m/romstage.c rename to src/mainboard/hp/folio_9470m/early_init.c index 07ee1eb283..e5a1892023 100644 --- a/src/mainboard/hp/folio_9470m/romstage.c +++ b/src/mainboard/hp/folio_9470m/early_init.c @@ -15,6 +15,7 @@ * GNU General Public License for more details. */ +#include #include #include #include @@ -38,7 +39,7 @@ const struct southbridge_usb_port mainboard_usb_ports[] = { { 0, 0, 6 }, /* B1P6 */ }; -void mainboard_config_superio(void) +void bootblock_mainboard_early_init(void) { kbc1126_enter_conf(); kbc1126_mailbox_init(); diff --git a/src/mainboard/hp/revolve_810_g1/Makefile.inc b/src/mainboard/hp/revolve_810_g1/Makefile.inc index 574f56e107..0a15c42fdd 100644 --- a/src/mainboard/hp/revolve_810_g1/Makefile.inc +++ b/src/mainboard/hp/revolve_810_g1/Makefile.inc @@ -20,3 +20,5 @@ ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads # FIXME: Other varients with same size onboard ram may exist. SPD_SOURCES = hynix_4g +bootblock-y += early_init.c +romstage-y += early_init.c diff --git a/src/mainboard/hp/revolve_810_g1/romstage.c b/src/mainboard/hp/revolve_810_g1/early_init.c similarity index 96% rename from src/mainboard/hp/revolve_810_g1/romstage.c rename to src/mainboard/hp/revolve_810_g1/early_init.c index 24247420ab..b464ce3daa 100644 --- a/src/mainboard/hp/revolve_810_g1/romstage.c +++ b/src/mainboard/hp/revolve_810_g1/early_init.c @@ -15,6 +15,7 @@ * GNU General Public License for more details. */ +#include #include #include #include @@ -46,7 +47,7 @@ const struct southbridge_usb_port mainboard_usb_ports[] = { { 0, 0, 6 }, /* B1P6 */ }; -void mainboard_config_superio(void) +void bootblock_mainboard_early_init(void) { kbc1126_enter_conf(); kbc1126_mailbox_init(); diff --git a/src/mainboard/hp/z220_sff_workstation/Makefile.inc b/src/mainboard/hp/z220_sff_workstation/Makefile.inc index af2b6742f0..f0b34f9840 100644 --- a/src/mainboard/hp/z220_sff_workstation/Makefile.inc +++ b/src/mainboard/hp/z220_sff_workstation/Makefile.inc @@ -1,3 +1,5 @@ bootblock-y += gpio.c romstage-y += gpio.c ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads +bootblock-y += early_init.c +romstage-y += early_init.c diff --git a/src/mainboard/hp/z220_sff_workstation/romstage.c b/src/mainboard/hp/z220_sff_workstation/early_init.c similarity index 95% rename from src/mainboard/hp/z220_sff_workstation/romstage.c rename to src/mainboard/hp/z220_sff_workstation/early_init.c index 0b9ffe4d56..fd70690079 100644 --- a/src/mainboard/hp/z220_sff_workstation/romstage.c +++ b/src/mainboard/hp/z220_sff_workstation/early_init.c @@ -16,6 +16,7 @@ * GNU General Public License for more details. */ +#include #include #include #include @@ -44,7 +45,7 @@ const struct southbridge_usb_port mainboard_usb_ports[] = { { 1, 0, 7 }, }; -void mainboard_config_superio(void) +void bootblock_mainboard_early_init(void) { if (CONFIG(CONSOLE_SERIAL)) nuvoton_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); diff --git a/src/mainboard/intel/dcp847ske/Makefile.inc b/src/mainboard/intel/dcp847ske/Makefile.inc index ec86d8455d..28bc7c7cc9 100644 --- a/src/mainboard/intel/dcp847ske/Makefile.inc +++ b/src/mainboard/intel/dcp847ske/Makefile.inc @@ -1,3 +1,4 @@ +bootblock-y += early_southbridge.c romstage-y += early_southbridge.c bootblock-y += gpio.c romstage-y += gpio.c diff --git a/src/mainboard/intel/dcp847ske/early_southbridge.c b/src/mainboard/intel/dcp847ske/early_southbridge.c index 8f38270388..53f5564a97 100644 --- a/src/mainboard/intel/dcp847ske/early_southbridge.c +++ b/src/mainboard/intel/dcp847ske/early_southbridge.c @@ -16,6 +16,7 @@ * GNU General Public License for more details. */ +#include #include #include #include @@ -160,7 +161,7 @@ static void superio_init(void) SUPERIO_LOCK; } -void mainboard_config_superio(void) +void bootblock_mainboard_early_init(void) { superio_init(); hwm_init(); diff --git a/src/mainboard/intel/emeraldlake2/Makefile.inc b/src/mainboard/intel/emeraldlake2/Makefile.inc index 974241dcc2..3e78db075b 100644 --- a/src/mainboard/intel/emeraldlake2/Makefile.inc +++ b/src/mainboard/intel/emeraldlake2/Makefile.inc @@ -17,3 +17,5 @@ romstage-y += chromeos.c ramstage-y += chromeos.c bootblock-y += gpio.c romstage-y += gpio.c +bootblock-y += early_init.c +romstage-y += early_init.c diff --git a/src/mainboard/intel/emeraldlake2/romstage.c b/src/mainboard/intel/emeraldlake2/early_init.c similarity index 98% rename from src/mainboard/intel/emeraldlake2/romstage.c rename to src/mainboard/intel/emeraldlake2/early_init.c index 2cfb5569fb..94a46550b2 100644 --- a/src/mainboard/intel/emeraldlake2/romstage.c +++ b/src/mainboard/intel/emeraldlake2/early_init.c @@ -14,6 +14,7 @@ * GNU General Public License for more details. */ +#include #include #include #include @@ -43,7 +44,7 @@ void mainboard_pch_lpc_setup(void) } } -void mainboard_config_superio(void) +void bootblock_mainboard_early_init(void) { const u16 port = SIO_PORT; const u16 runtime_port = 0x180; diff --git a/src/mainboard/kontron/ktqm77/Makefile.inc b/src/mainboard/kontron/ktqm77/Makefile.inc index 620a9c06a2..e402ffa605 100644 --- a/src/mainboard/kontron/ktqm77/Makefile.inc +++ b/src/mainboard/kontron/ktqm77/Makefile.inc @@ -2,3 +2,5 @@ bootblock-y += gpio.c romstage-y += gpio.c ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads +bootblock-y += early_init.c +romstage-y += early_init.c diff --git a/src/mainboard/kontron/ktqm77/romstage.c b/src/mainboard/kontron/ktqm77/early_init.c similarity index 98% rename from src/mainboard/kontron/ktqm77/romstage.c rename to src/mainboard/kontron/ktqm77/early_init.c index 3b49653f97..6a483bc670 100644 --- a/src/mainboard/kontron/ktqm77/romstage.c +++ b/src/mainboard/kontron/ktqm77/early_init.c @@ -14,6 +14,7 @@ * GNU General Public License for more details. */ +#include #include #include #include @@ -54,7 +55,7 @@ void mainboard_late_rcba_config(void) RCBA32(FD) = reg32; } -void mainboard_config_superio(void) +void bootblock_mainboard_early_init(void) { int lvds_3v = 0; /* 0 (5V) or 1 (3V3) */ int dis_bl_inv = 1; /* backlight inversion: 1 = disabled, 0 = enabled */ diff --git a/src/mainboard/lenovo/l520/Makefile.inc b/src/mainboard/lenovo/l520/Makefile.inc index 14cd059011..c03276795c 100644 --- a/src/mainboard/lenovo/l520/Makefile.inc +++ b/src/mainboard/lenovo/l520/Makefile.inc @@ -13,9 +13,10 @@ ## GNU General Public License for more details. ## -romstage-y += romstage.c bootblock-y += gpio.c romstage-y += gpio.c smm-y += smihandler.c ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads +bootblock-y += early_init.c +romstage-y += early_init.c diff --git a/src/mainboard/lenovo/l520/romstage.c b/src/mainboard/lenovo/l520/early_init.c similarity index 96% rename from src/mainboard/lenovo/l520/romstage.c rename to src/mainboard/lenovo/l520/early_init.c index af73537f24..d63a667737 100644 --- a/src/mainboard/lenovo/l520/romstage.c +++ b/src/mainboard/lenovo/l520/early_init.c @@ -39,10 +39,6 @@ const struct southbridge_usb_port mainboard_usb_ports[] = { { 1, 0, -1 }, }; -void mainboard_config_superio(void) -{ -} - void mainboard_get_spd(spd_raw_data *spd, bool id_only) { read_spd(&spd[0], 0x50, id_only); diff --git a/src/mainboard/lenovo/s230u/Makefile.inc b/src/mainboard/lenovo/s230u/Makefile.inc index aa4c4f879d..12e77097e4 100644 --- a/src/mainboard/lenovo/s230u/Makefile.inc +++ b/src/mainboard/lenovo/s230u/Makefile.inc @@ -16,3 +16,5 @@ SPD_SOURCES += samsung_2gb # 0b0111 SPD_SOURCES += hynix_2gb # 0b1000 ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads +bootblock-y += early_init.c +romstage-y += early_init.c diff --git a/src/mainboard/lenovo/s230u/romstage.c b/src/mainboard/lenovo/s230u/early_init.c similarity index 98% rename from src/mainboard/lenovo/s230u/romstage.c rename to src/mainboard/lenovo/s230u/early_init.c index 0552170668..6bc92b2cac 100644 --- a/src/mainboard/lenovo/s230u/romstage.c +++ b/src/mainboard/lenovo/s230u/early_init.c @@ -64,10 +64,6 @@ const struct southbridge_usb_port mainboard_usb_ports[] = { { 1, 1, 6 }, }; -void mainboard_config_superio(void) -{ -} - static const char *mainboard_spd_names[9] = { "ELPIDA 4GB", "SAMSUNG 4GB", diff --git a/src/mainboard/lenovo/t420/Makefile.inc b/src/mainboard/lenovo/t420/Makefile.inc index 3914f51561..080812e44a 100644 --- a/src/mainboard/lenovo/t420/Makefile.inc +++ b/src/mainboard/lenovo/t420/Makefile.inc @@ -18,3 +18,5 @@ bootblock-y += gpio.c romstage-y += gpio.c ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads +bootblock-y += early_init.c +romstage-y += early_init.c diff --git a/src/mainboard/lenovo/t420/romstage.c b/src/mainboard/lenovo/t420/early_init.c similarity index 98% rename from src/mainboard/lenovo/t420/romstage.c rename to src/mainboard/lenovo/t420/early_init.c index e04803f165..50e62586a5 100644 --- a/src/mainboard/lenovo/t420/romstage.c +++ b/src/mainboard/lenovo/t420/early_init.c @@ -82,7 +82,3 @@ void mainboard_early_init(int s3resume) { hybrid_graphics_init(); } - -void mainboard_config_superio(void) -{ -} diff --git a/src/mainboard/lenovo/t420s/Makefile.inc b/src/mainboard/lenovo/t420s/Makefile.inc index 3914f51561..080812e44a 100644 --- a/src/mainboard/lenovo/t420s/Makefile.inc +++ b/src/mainboard/lenovo/t420s/Makefile.inc @@ -18,3 +18,5 @@ bootblock-y += gpio.c romstage-y += gpio.c ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads +bootblock-y += early_init.c +romstage-y += early_init.c diff --git a/src/mainboard/lenovo/t420s/romstage.c b/src/mainboard/lenovo/t420s/early_init.c similarity index 98% rename from src/mainboard/lenovo/t420s/romstage.c rename to src/mainboard/lenovo/t420s/early_init.c index 764997297e..1357a0ae52 100644 --- a/src/mainboard/lenovo/t420s/romstage.c +++ b/src/mainboard/lenovo/t420s/early_init.c @@ -81,7 +81,3 @@ void mainboard_early_init(int s3resume) { hybrid_graphics_init(); } - -void mainboard_config_superio(void) -{ -} diff --git a/src/mainboard/lenovo/t430/Makefile.inc b/src/mainboard/lenovo/t430/Makefile.inc index 409d4842a9..0f49600c7d 100644 --- a/src/mainboard/lenovo/t430/Makefile.inc +++ b/src/mainboard/lenovo/t430/Makefile.inc @@ -1,6 +1,7 @@ -romstage-y += romstage.c bootblock-y += gpio.c romstage-y += gpio.c smm-y += smihandler.c ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads +bootblock-y += early_init.c +romstage-y += early_init.c diff --git a/src/mainboard/lenovo/t430/romstage.c b/src/mainboard/lenovo/t430/early_init.c similarity index 97% rename from src/mainboard/lenovo/t430/romstage.c rename to src/mainboard/lenovo/t430/early_init.c index f1e724be47..74c8b60883 100644 --- a/src/mainboard/lenovo/t430/romstage.c +++ b/src/mainboard/lenovo/t430/early_init.c @@ -72,10 +72,6 @@ void mainboard_early_init(int s3resume) hybrid_graphics_init(); } -void mainboard_config_superio(void) -{ -} - void mainboard_get_spd(spd_raw_data *spd, bool id_only) { read_spd(&spd[0], 0x50, id_only); diff --git a/src/mainboard/lenovo/t430s/Makefile.inc b/src/mainboard/lenovo/t430s/Makefile.inc index 425047fe44..d0e69a838f 100644 --- a/src/mainboard/lenovo/t430s/Makefile.inc +++ b/src/mainboard/lenovo/t430s/Makefile.inc @@ -20,3 +20,5 @@ romstage-y += variants/$(VARIANT_DIR)/romstage.c ramstage-y += variants/$(VARIANT_DIR)/hda_verb.c ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads subdirs-$(CONFIG_BOARD_LENOVO_T431S) += variants/$(VARIANT_DIR)/spd +bootblock-y += early_init.c +romstage-y += early_init.c diff --git a/src/mainboard/lenovo/t430s/romstage.c b/src/mainboard/lenovo/t430s/early_init.c similarity index 95% rename from src/mainboard/lenovo/t430s/romstage.c rename to src/mainboard/lenovo/t430s/early_init.c index 6503c9a920..0757c06fbd 100644 --- a/src/mainboard/lenovo/t430s/romstage.c +++ b/src/mainboard/lenovo/t430s/early_init.c @@ -23,7 +23,3 @@ void mainboard_pch_lpc_setup(void) { pci_write_config32(PCH_LPC_DEV, ETR3, 0x10000); } - -void mainboard_config_superio(void) -{ -} diff --git a/src/mainboard/lenovo/t520/Makefile.inc b/src/mainboard/lenovo/t520/Makefile.inc index 5310bbf530..8f3c154418 100644 --- a/src/mainboard/lenovo/t520/Makefile.inc +++ b/src/mainboard/lenovo/t520/Makefile.inc @@ -18,3 +18,5 @@ bootblock-y += variants/$(VARIANT_DIR)/gpio.c romstage-y += variants/$(VARIANT_DIR)/gpio.c romstage-y += variants/$(VARIANT_DIR)/romstage.c ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads +bootblock-y += early_init.c +romstage-y += early_init.c diff --git a/src/mainboard/lenovo/t520/romstage.c b/src/mainboard/lenovo/t520/early_init.c similarity index 98% rename from src/mainboard/lenovo/t520/romstage.c rename to src/mainboard/lenovo/t520/early_init.c index caf54bd5df..cfa69b7082 100644 --- a/src/mainboard/lenovo/t520/romstage.c +++ b/src/mainboard/lenovo/t520/early_init.c @@ -77,7 +77,3 @@ void mainboard_early_init(int s3resume) { hybrid_graphics_init(); } - -void mainboard_config_superio(void) -{ -} diff --git a/src/mainboard/lenovo/t530/Makefile.inc b/src/mainboard/lenovo/t530/Makefile.inc index 5310bbf530..8f3c154418 100644 --- a/src/mainboard/lenovo/t530/Makefile.inc +++ b/src/mainboard/lenovo/t530/Makefile.inc @@ -18,3 +18,5 @@ bootblock-y += variants/$(VARIANT_DIR)/gpio.c romstage-y += variants/$(VARIANT_DIR)/gpio.c romstage-y += variants/$(VARIANT_DIR)/romstage.c ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads +bootblock-y += early_init.c +romstage-y += early_init.c diff --git a/src/mainboard/lenovo/t530/romstage.c b/src/mainboard/lenovo/t530/early_init.c similarity index 97% rename from src/mainboard/lenovo/t530/romstage.c rename to src/mainboard/lenovo/t530/early_init.c index 85c3090bb5..34c61e4e49 100644 --- a/src/mainboard/lenovo/t530/romstage.c +++ b/src/mainboard/lenovo/t530/early_init.c @@ -60,7 +60,3 @@ void mainboard_early_init(int s3resume) { hybrid_graphics_init(); } - -void mainboard_config_superio(void) -{ -} diff --git a/src/mainboard/lenovo/x131e/Makefile.inc b/src/mainboard/lenovo/x131e/Makefile.inc index 4fbf73bbd3..1d258758be 100644 --- a/src/mainboard/lenovo/x131e/Makefile.inc +++ b/src/mainboard/lenovo/x131e/Makefile.inc @@ -17,3 +17,5 @@ bootblock-y += gpio.c romstage-y += gpio.c ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads +bootblock-y += early_init.c +romstage-y += early_init.c diff --git a/src/mainboard/lenovo/x131e/romstage.c b/src/mainboard/lenovo/x131e/early_init.c similarity index 97% rename from src/mainboard/lenovo/x131e/romstage.c rename to src/mainboard/lenovo/x131e/early_init.c index 45d6b88099..fe9fec0cb6 100644 --- a/src/mainboard/lenovo/x131e/romstage.c +++ b/src/mainboard/lenovo/x131e/early_init.c @@ -42,7 +42,3 @@ void mainboard_get_spd(spd_raw_data *spd, bool id_only) read_spd(&spd[0], 0x50, id_only); read_spd(&spd[2], 0x52, id_only); } - -void mainboard_config_superio(void) -{ -} diff --git a/src/mainboard/lenovo/x1_carbon_gen1/Makefile.inc b/src/mainboard/lenovo/x1_carbon_gen1/Makefile.inc index 8ce77fc77d..f6331a61d1 100644 --- a/src/mainboard/lenovo/x1_carbon_gen1/Makefile.inc +++ b/src/mainboard/lenovo/x1_carbon_gen1/Makefile.inc @@ -20,3 +20,5 @@ bootblock-y += gpio.c romstage-y += gpio.c ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads +bootblock-y += early_init.c +romstage-y += early_init.c diff --git a/src/mainboard/lenovo/x1_carbon_gen1/romstage.c b/src/mainboard/lenovo/x1_carbon_gen1/early_init.c similarity index 98% rename from src/mainboard/lenovo/x1_carbon_gen1/romstage.c rename to src/mainboard/lenovo/x1_carbon_gen1/early_init.c index 1f027ffab8..c70b21d36b 100644 --- a/src/mainboard/lenovo/x1_carbon_gen1/romstage.c +++ b/src/mainboard/lenovo/x1_carbon_gen1/early_init.c @@ -99,7 +99,3 @@ void mainboard_get_spd(spd_raw_data *spd, bool id_only) memcpy(&spd[0], memory, 256); memcpy(&spd[2], memory, 256); } - -void mainboard_config_superio(void) -{ -} diff --git a/src/mainboard/lenovo/x220/Makefile.inc b/src/mainboard/lenovo/x220/Makefile.inc index c0ba457c57..4363770d28 100644 --- a/src/mainboard/lenovo/x220/Makefile.inc +++ b/src/mainboard/lenovo/x220/Makefile.inc @@ -19,3 +19,5 @@ romstage-y += variants/$(VARIANT_DIR)/gpio.c romstage-y += variants/$(VARIANT_DIR)/romstage.c ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads +bootblock-y += early_init.c +romstage-y += early_init.c diff --git a/src/mainboard/lenovo/x220/romstage.c b/src/mainboard/lenovo/x220/early_init.c similarity index 98% rename from src/mainboard/lenovo/x220/romstage.c rename to src/mainboard/lenovo/x220/early_init.c index 72dd8dddca..8ee807cb5d 100644 --- a/src/mainboard/lenovo/x220/romstage.c +++ b/src/mainboard/lenovo/x220/early_init.c @@ -87,10 +87,6 @@ void mainboard_get_spd(spd_raw_data *spd, bool id_only) read_spd (&spd[2], 0x51, id_only); } -void mainboard_config_superio(void) -{ -} - int mainboard_should_reset_usb(int s3resume) { return !s3resume; diff --git a/src/mainboard/lenovo/x230/Makefile.inc b/src/mainboard/lenovo/x230/Makefile.inc index 3914f51561..080812e44a 100644 --- a/src/mainboard/lenovo/x230/Makefile.inc +++ b/src/mainboard/lenovo/x230/Makefile.inc @@ -18,3 +18,5 @@ bootblock-y += gpio.c romstage-y += gpio.c ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads +bootblock-y += early_init.c +romstage-y += early_init.c diff --git a/src/mainboard/lenovo/x230/romstage.c b/src/mainboard/lenovo/x230/early_init.c similarity index 97% rename from src/mainboard/lenovo/x230/romstage.c rename to src/mainboard/lenovo/x230/early_init.c index 56f5a90670..b737e7de83 100644 --- a/src/mainboard/lenovo/x230/romstage.c +++ b/src/mainboard/lenovo/x230/early_init.c @@ -51,7 +51,3 @@ void mainboard_get_spd(spd_raw_data *spd, bool id_only) read_spd (&spd[0], 0x50, id_only); read_spd (&spd[2], 0x51, id_only); } - -void mainboard_config_superio(void) -{ -} diff --git a/src/mainboard/msi/ms7707/Makefile.inc b/src/mainboard/msi/ms7707/Makefile.inc index 0ec849f5b5..2fa05da9ac 100644 --- a/src/mainboard/msi/ms7707/Makefile.inc +++ b/src/mainboard/msi/ms7707/Makefile.inc @@ -1,2 +1,4 @@ bootblock-y += gpio.c romstage-y += gpio.c +bootblock-y += early_init.c +romstage-y += early_init.c diff --git a/src/mainboard/msi/ms7707/romstage.c b/src/mainboard/msi/ms7707/early_init.c similarity index 97% rename from src/mainboard/msi/ms7707/romstage.c rename to src/mainboard/msi/ms7707/early_init.c index 1dd3fd06a8..480e196e90 100644 --- a/src/mainboard/msi/ms7707/romstage.c +++ b/src/mainboard/msi/ms7707/early_init.c @@ -45,10 +45,6 @@ const struct southbridge_usb_port mainboard_usb_ports[] = { {1, 0, 6}, }; -void mainboard_config_superio(void) -{ -} - void mainboard_get_spd(spd_raw_data *spd, bool id_only) { read_spd(&spd[0], 0x50, id_only); diff --git a/src/mainboard/roda/rv11/Makefile.inc b/src/mainboard/roda/rv11/Makefile.inc index 422b448e24..a3d6d5913f 100644 --- a/src/mainboard/roda/rv11/Makefile.inc +++ b/src/mainboard/roda/rv11/Makefile.inc @@ -16,7 +16,10 @@ bootblock-y += gpio.c romstage-y += gpio.c -romstage-y += variants/$(VARIANT_DIR)/romstage.c +bootblock-y += variants/$(VARIANT_DIR)/early_init.c +romstage-y += variants/$(VARIANT_DIR)/early_init.c ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += variants/$(VARIANT_DIR)/gma-mainboard.ads CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/variants/$(VARIANT_DIR)/include +bootblock-y += early_init.c +romstage-y += early_init.c diff --git a/src/mainboard/roda/rv11/romstage.c b/src/mainboard/roda/rv11/early_init.c similarity index 100% rename from src/mainboard/roda/rv11/romstage.c rename to src/mainboard/roda/rv11/early_init.c diff --git a/src/mainboard/roda/rv11/variants/rv11/romstage.c b/src/mainboard/roda/rv11/variants/rv11/early_init.c similarity index 98% rename from src/mainboard/roda/rv11/variants/rv11/romstage.c rename to src/mainboard/roda/rv11/variants/rv11/early_init.c index 38c4064772..5081c005aa 100644 --- a/src/mainboard/roda/rv11/variants/rv11/romstage.c +++ b/src/mainboard/roda/rv11/variants/rv11/early_init.c @@ -21,10 +21,6 @@ #include #include -void mainboard_config_superio(void) -{ -} - void mainboard_fill_pei_data(struct pei_data *const pei_data) { const struct pei_data pei_data_template = { diff --git a/src/mainboard/roda/rv11/variants/rw11/romstage.c b/src/mainboard/roda/rv11/variants/rw11/early_init.c similarity index 98% rename from src/mainboard/roda/rv11/variants/rw11/romstage.c rename to src/mainboard/roda/rv11/variants/rw11/early_init.c index 7321dac398..f3865fc359 100644 --- a/src/mainboard/roda/rv11/variants/rw11/romstage.c +++ b/src/mainboard/roda/rv11/variants/rw11/early_init.c @@ -13,6 +13,7 @@ * GNU General Public License for more details. */ +#include #include #include #include @@ -25,7 +26,7 @@ #include #include -void mainboard_config_superio(void) +void bootblock_mainboard_early_init(void) { const pnp_devfn_t dev = PNP_DEV(0x2e, IT8783EF_GPIO); diff --git a/src/mainboard/samsung/lumpy/Makefile.inc b/src/mainboard/samsung/lumpy/Makefile.inc index 3e28bd4878..e6e65aa096 100644 --- a/src/mainboard/samsung/lumpy/Makefile.inc +++ b/src/mainboard/samsung/lumpy/Makefile.inc @@ -31,3 +31,5 @@ bootblock-y += gpio.c romstage-y += gpio.c ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads +bootblock-y += early_init.c +romstage-y += early_init.c diff --git a/src/mainboard/samsung/lumpy/romstage.c b/src/mainboard/samsung/lumpy/early_init.c similarity index 99% rename from src/mainboard/samsung/lumpy/romstage.c rename to src/mainboard/samsung/lumpy/early_init.c index d6ded7a559..6bc545c57e 100644 --- a/src/mainboard/samsung/lumpy/romstage.c +++ b/src/mainboard/samsung/lumpy/early_init.c @@ -232,7 +232,3 @@ int mainboard_should_reset_usb(int s3resume) { return !s3resume; } - -void mainboard_config_superio(void) -{ -} diff --git a/src/mainboard/samsung/stumpy/Makefile.inc b/src/mainboard/samsung/stumpy/Makefile.inc index 497accadb9..de233ce0cd 100644 --- a/src/mainboard/samsung/stumpy/Makefile.inc +++ b/src/mainboard/samsung/stumpy/Makefile.inc @@ -19,3 +19,5 @@ bootblock-y += gpio.c romstage-y += gpio.c ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads +bootblock-y += early_init.c +romstage-y += early_init.c diff --git a/src/mainboard/samsung/stumpy/romstage.c b/src/mainboard/samsung/stumpy/early_init.c similarity index 99% rename from src/mainboard/samsung/stumpy/romstage.c rename to src/mainboard/samsung/stumpy/early_init.c index 35dc055baa..03cb8d70a3 100644 --- a/src/mainboard/samsung/stumpy/romstage.c +++ b/src/mainboard/samsung/stumpy/early_init.c @@ -14,6 +14,7 @@ * GNU General Public License for more details. */ +#include #include #include #include @@ -239,7 +240,7 @@ int mainboard_should_reset_usb(int s3resume) } } -void mainboard_config_superio(void) +void bootblock_mainboard_early_init(void) { setup_sio_gpios(); diff --git a/src/mainboard/sapphire/pureplatinumh61/Makefile.inc b/src/mainboard/sapphire/pureplatinumh61/Makefile.inc index 4cf022a474..8d8f3ee51f 100644 --- a/src/mainboard/sapphire/pureplatinumh61/Makefile.inc +++ b/src/mainboard/sapphire/pureplatinumh61/Makefile.inc @@ -18,3 +18,5 @@ bootblock-y += gpio.c romstage-y += gpio.c ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads +bootblock-y += early_init.c +romstage-y += early_init.c diff --git a/src/mainboard/sapphire/pureplatinumh61/romstage.c b/src/mainboard/sapphire/pureplatinumh61/early_init.c similarity index 97% rename from src/mainboard/sapphire/pureplatinumh61/romstage.c rename to src/mainboard/sapphire/pureplatinumh61/early_init.c index bc08fd8bf2..be665617a4 100644 --- a/src/mainboard/sapphire/pureplatinumh61/romstage.c +++ b/src/mainboard/sapphire/pureplatinumh61/early_init.c @@ -48,10 +48,6 @@ const struct southbridge_usb_port mainboard_usb_ports[] = { { 1, 0, 6 }, }; -void mainboard_config_superio(void) -{ -} - void mainboard_get_spd(spd_raw_data *spd, bool id_only) { read_spd(&spd[0], 0x50, id_only); diff --git a/src/northbridge/intel/sandybridge/romstage.c b/src/northbridge/intel/sandybridge/romstage.c index c76d2f4f4a..079e1b13ba 100644 --- a/src/northbridge/intel/sandybridge/romstage.c +++ b/src/northbridge/intel/sandybridge/romstage.c @@ -63,17 +63,11 @@ void mainboard_romstage_entry(void) /* Init LPC, GPIO, BARs, disable watchdog ... */ early_pch_init(); - /* Initialize superio */ - mainboard_config_superio(); - /* USB is initialized in MRC if MRC is used. */ if (CONFIG(USE_NATIVE_RAMINIT)) { early_usb_init(mainboard_usb_ports); } - /* Initialize console device(s) */ - console_init(); - /* Perform some early chipset initialization required * before RAM initialization can work */ diff --git a/src/northbridge/intel/sandybridge/sandybridge.h b/src/northbridge/intel/sandybridge/sandybridge.h index cfda2e838b..dff943dd92 100644 --- a/src/northbridge/intel/sandybridge/sandybridge.h +++ b/src/northbridge/intel/sandybridge/sandybridge.h @@ -215,7 +215,6 @@ void early_init_dmi(void); /* mainboard_early_init: Optional mainboard callback run after console init but before raminit. */ void mainboard_early_init(int s3resume); -void mainboard_config_superio(void); int mainboard_should_reset_usb(int s3resume); void perform_raminit(int s3resume); enum platform_type get_platform_type(void); From 770e73d0a2d7842fb86d024930643eac48e22c69 Mon Sep 17 00:00:00 2001 From: Nico Huber Date: Sat, 16 Nov 2019 23:57:18 +0100 Subject: [PATCH 0228/1242] mb/apple/macbookair4_2: Drop unnecessary PCH config mainboard_pch_lpc_setup() and mainboard_late_rcba_config() did 4 things here on top of the generic PCH code: 1. Enabling LPC decoding for gameports. It seems unlikely that anything is using these ports and there is no code to support gameports. 2. Decoding of COM3 instead of COM2. What COM? 3. Premature locking of ETR3/global reset. Bad idea. 4. Disabling the GbE port in BUC. Already done by PCH code. Change-Id: Ie92dbf5c6813435995c4d24ed807ffc8d125953a Signed-off-by: Nico Huber Reviewed-on: https://review.coreboot.org/c/coreboot/+/36886 Tested-by: build bot (Jenkins) Reviewed-by: Arthur Heymans --- src/mainboard/apple/macbookair4_2/early_init.c | 12 ------------ 1 file changed, 12 deletions(-) diff --git a/src/mainboard/apple/macbookair4_2/early_init.c b/src/mainboard/apple/macbookair4_2/early_init.c index bfd070ca1c..860d9d46dd 100644 --- a/src/mainboard/apple/macbookair4_2/early_init.c +++ b/src/mainboard/apple/macbookair4_2/early_init.c @@ -20,18 +20,6 @@ #include #include -void mainboard_pch_lpc_setup(void) -{ - pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x82, 0x3f0f); - pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x80, 0x0070); - pci_write_config32(PCI_DEV(0, 0x1f, 0), 0xac, 0x80000000); -} - -void mainboard_late_rcba_config(void) -{ - /* Disable devices. */ - RCBA32(0x3414) = 0x00000020; -} const struct southbridge_usb_port mainboard_usb_ports[] = { { 1, 0, -1 }, { 1, 0, -1 }, From 8d6d3fa109ca6895008639e12b0eb48d700e8665 Mon Sep 17 00:00:00 2001 From: Nico Huber Date: Sun, 17 Nov 2019 00:09:17 +0100 Subject: [PATCH 0229/1242] mb/asus/p8h61-m*: Drop unnecessary PCH config The generic PCH code already sets up a superset of these decodings. Change-Id: I90bca37c46b89c35f323225fc3c087f1630397e4 Signed-off-by: Nico Huber Reviewed-on: https://review.coreboot.org/c/coreboot/+/36887 Tested-by: build bot (Jenkins) Reviewed-by: Tristan Corrick Reviewed-by: Arthur Heymans --- src/mainboard/asus/p8h61-m_lx/early_init.c | 6 ------ src/mainboard/asus/p8h61-m_pro/early_init.c | 7 ------- 2 files changed, 13 deletions(-) diff --git a/src/mainboard/asus/p8h61-m_lx/early_init.c b/src/mainboard/asus/p8h61-m_lx/early_init.c index 7dc8cd5334..a2fc02e2ce 100644 --- a/src/mainboard/asus/p8h61-m_lx/early_init.c +++ b/src/mainboard/asus/p8h61-m_lx/early_init.c @@ -42,12 +42,6 @@ const struct southbridge_usb_port mainboard_usb_ports[] = { { 1, 0, 6 }, }; -void mainboard_pch_lpc_setup(void) -{ - pci_or_config16(PCH_LPC_DEV, LPC_EN, - CNF1_LPC_EN | KBC_LPC_EN | LPT_LPC_EN | COMA_LPC_EN); -} - void bootblock_mainboard_early_init(void) { nuvoton_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); diff --git a/src/mainboard/asus/p8h61-m_pro/early_init.c b/src/mainboard/asus/p8h61-m_pro/early_init.c index 4b02505bef..df00e6dab1 100644 --- a/src/mainboard/asus/p8h61-m_pro/early_init.c +++ b/src/mainboard/asus/p8h61-m_pro/early_init.c @@ -26,13 +26,6 @@ #define SERIAL_DEV PNP_DEV(0x2e, NCT6776_SP1) #define ACPI_DEV PNP_DEV(0x2e, NCT6776_ACPI) -void mainboard_pch_lpc_setup(void) -{ - /* Enable the Super IO */ - pci_write_config16(PCH_LPC_DEV, LPC_EN, CNF1_LPC_EN | - KBC_LPC_EN | LPT_LPC_EN | COMA_LPC_EN); -} - const struct southbridge_usb_port mainboard_usb_ports[] = { { 1, 0, 0 }, { 1, 0, 0 }, From ce20697513b1a6455c743aef43d40f91b0085af9 Mon Sep 17 00:00:00 2001 From: Nico Huber Date: Sun, 17 Nov 2019 00:42:57 +0100 Subject: [PATCH 0230/1242] mb/compulab/intense_pc: Clean PCH and super-i/o config up The generic PCH code already enables a superset of LPC decoding. Move UART setup to bootblock_mainboard_early_init() where it is expected. Last but not least, remove an odd write to BUCs (RCBA+0x3414) and beyond, as it's an 8-bit register and shouldn't be bluntly zeroed. Change-Id: I24a4ccf6a529460a83f48522d2e05e6ad6614f81 Signed-off-by: Nico Huber Reviewed-on: https://review.coreboot.org/c/coreboot/+/36888 Tested-by: build bot (Jenkins) Reviewed-by: Arthur Heymans --- .../compulab/intense_pc/early_init.c | 25 +++---------------- 1 file changed, 4 insertions(+), 21 deletions(-) diff --git a/src/mainboard/compulab/intense_pc/early_init.c b/src/mainboard/compulab/intense_pc/early_init.c index 73acc46802..cb5f4454b5 100644 --- a/src/mainboard/compulab/intense_pc/early_init.c +++ b/src/mainboard/compulab/intense_pc/early_init.c @@ -23,27 +23,6 @@ #define SIO_PORT 0x164e -void mainboard_pch_lpc_setup(void) -{ - pci_devfn_t dev = PCH_LPC_DEV; - - /* Enable SuperIO */ - u16 lpc_config = CNF1_LPC_EN | CNF2_LPC_EN; - pci_write_config16(dev, LPC_EN, lpc_config); - -#if CONFIG(DRIVERS_UART_8250IO) - /* Enable COM1 */ - if (sio1007_enable_uart_at(SIO_PORT)) { - pci_write_config16(dev, LPC_EN, - lpc_config | COMA_LPC_EN); - } -#endif -} - -void mainboard_late_rcba_config(void) -{ - RCBA32(0x3414) = 0x00000000; -} const struct southbridge_usb_port mainboard_usb_ports[] = { { 1, 1, 0 }, { 1, 1, 0 }, @@ -66,6 +45,10 @@ void bootblock_mainboard_early_init(void) const u16 port = SIO_PORT; const u16 runtime_port = 0x180; + /* Enable COM1 if requested */ + if (CONFIG(DRIVERS_UART_8250IO)) + sio1007_enable_uart_at(port); + /* Turn on configuration mode. */ outb(0x55, port); From 89b8c238306e18792433717053649b61b91f57e6 Mon Sep 17 00:00:00 2001 From: Nico Huber Date: Sun, 17 Nov 2019 00:58:15 +0100 Subject: [PATCH 0231/1242] mb/{gigabyte,lenovo}: Remove spurious setting of ETR3 bit 16 This bit is used to indicate xHCI routing across reboots. If anything, coreboot should act on it, not set it during boot. ASL code would be supposed to set it. Change-Id: Id14647ac4e591cfa042ca8aad6dfc6ccda35c74a Signed-off-by: Nico Huber Reviewed-on: https://review.coreboot.org/c/coreboot/+/36889 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Rudolph Reviewed-by: Arthur Heymans --- .../gigabyte/ga-b75m-d3h/early_init.c | 5 ---- src/mainboard/lenovo/s230u/early_init.c | 2 -- src/mainboard/lenovo/t420/early_init.c | 5 ---- src/mainboard/lenovo/t420s/early_init.c | 5 ---- src/mainboard/lenovo/t430s/Makefile.inc | 2 -- src/mainboard/lenovo/t430s/early_init.c | 25 ------------------- src/mainboard/lenovo/t520/early_init.c | 5 ---- src/mainboard/lenovo/t530/early_init.c | 5 ---- .../lenovo/x1_carbon_gen1/early_init.c | 5 ---- src/mainboard/lenovo/x220/early_init.c | 5 ---- src/mainboard/lenovo/x230/early_init.c | 5 ---- 11 files changed, 69 deletions(-) delete mode 100644 src/mainboard/lenovo/t430s/early_init.c diff --git a/src/mainboard/gigabyte/ga-b75m-d3h/early_init.c b/src/mainboard/gigabyte/ga-b75m-d3h/early_init.c index 0a863fffd2..65616ffa19 100644 --- a/src/mainboard/gigabyte/ga-b75m-d3h/early_init.c +++ b/src/mainboard/gigabyte/ga-b75m-d3h/early_init.c @@ -26,11 +26,6 @@ #define SIO_GPIO PNP_DEV(SUPERIO_BASE, IT8728F_GPIO) #define SERIAL_DEV PNP_DEV(SUPERIO_BASE, 0x01) -void mainboard_pch_lpc_setup(void) -{ - pci_write_config32(PCH_LPC_DEV, ETR3, 0x10000); -} - void bootblock_mainboard_early_init(void) { /* Initialize SuperIO */ diff --git a/src/mainboard/lenovo/s230u/early_init.c b/src/mainboard/lenovo/s230u/early_init.c index 6bc92b2cac..7c302b8999 100644 --- a/src/mainboard/lenovo/s230u/early_init.c +++ b/src/mainboard/lenovo/s230u/early_init.c @@ -29,8 +29,6 @@ void mainboard_pch_lpc_setup(void) { - pci_write_config32(PCH_LPC_DEV, ETR3, 0x10000); - /* Memory map KB9012 EC registers */ pci_write_config32( PCH_LPC_DEV, LGMR, diff --git a/src/mainboard/lenovo/t420/early_init.c b/src/mainboard/lenovo/t420/early_init.c index 50e62586a5..8afd150129 100644 --- a/src/mainboard/lenovo/t420/early_init.c +++ b/src/mainboard/lenovo/t420/early_init.c @@ -49,11 +49,6 @@ static void hybrid_graphics_init(void) pci_write_config32(PCI_DEV(0, 0, 0), DEVEN, reg32); } -void mainboard_pch_lpc_setup(void) -{ - pci_write_config32(PCH_LPC_DEV, ETR3, 0x10000); -} - // OC3 set in bios to port 2-7, OC7 set in bios to port 10-13 const struct southbridge_usb_port mainboard_usb_ports[] = { { 1, 1, 0 }, /* P0: system port 4, OC0 */ diff --git a/src/mainboard/lenovo/t420s/early_init.c b/src/mainboard/lenovo/t420s/early_init.c index 1357a0ae52..e2cdebfe35 100644 --- a/src/mainboard/lenovo/t420s/early_init.c +++ b/src/mainboard/lenovo/t420s/early_init.c @@ -49,11 +49,6 @@ static void hybrid_graphics_init(void) pci_write_config32(PCI_DEV(0, 0, 0), DEVEN, reg32); } -void mainboard_pch_lpc_setup(void) -{ - pci_write_config32(PCH_LPC_DEV, ETR3, 0x10000); -} - const struct southbridge_usb_port mainboard_usb_ports[] = { { 0, 1, -1 }, /* P0 empty */ { 1, 1, 1 }, /* P1 system port 2 (To system port) (EHCI debug), OC 1 */ diff --git a/src/mainboard/lenovo/t430s/Makefile.inc b/src/mainboard/lenovo/t430s/Makefile.inc index d0e69a838f..425047fe44 100644 --- a/src/mainboard/lenovo/t430s/Makefile.inc +++ b/src/mainboard/lenovo/t430s/Makefile.inc @@ -20,5 +20,3 @@ romstage-y += variants/$(VARIANT_DIR)/romstage.c ramstage-y += variants/$(VARIANT_DIR)/hda_verb.c ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads subdirs-$(CONFIG_BOARD_LENOVO_T431S) += variants/$(VARIANT_DIR)/spd -bootblock-y += early_init.c -romstage-y += early_init.c diff --git a/src/mainboard/lenovo/t430s/early_init.c b/src/mainboard/lenovo/t430s/early_init.c deleted file mode 100644 index 0757c06fbd..0000000000 --- a/src/mainboard/lenovo/t430s/early_init.c +++ /dev/null @@ -1,25 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007-2010 coresystems GmbH - * Copyright (C) 2011 The ChromiumOS Authors. All rights reserved. - * Copyright (C) 2014 Vladimir Serbinenko - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include - -void mainboard_pch_lpc_setup(void) -{ - pci_write_config32(PCH_LPC_DEV, ETR3, 0x10000); -} diff --git a/src/mainboard/lenovo/t520/early_init.c b/src/mainboard/lenovo/t520/early_init.c index cfa69b7082..ad8e1520bb 100644 --- a/src/mainboard/lenovo/t520/early_init.c +++ b/src/mainboard/lenovo/t520/early_init.c @@ -51,11 +51,6 @@ static void hybrid_graphics_init(void) pci_write_config32(PCI_DEV(0, 0, 0), DEVEN, reg32); } -void mainboard_pch_lpc_setup(void) -{ - pci_write_config32(PCH_LPC_DEV, ETR3, 0x10000); -} - const struct southbridge_usb_port mainboard_usb_ports[] = { { 1, 1, 0 }, /* P0 left dual conn, OC 0 */ { 1, 1, 1 }, /* P1 system onboard USB (eSATA), (EHCI debug), OC 1 */ diff --git a/src/mainboard/lenovo/t530/early_init.c b/src/mainboard/lenovo/t530/early_init.c index 34c61e4e49..aeb27a6d28 100644 --- a/src/mainboard/lenovo/t530/early_init.c +++ b/src/mainboard/lenovo/t530/early_init.c @@ -51,11 +51,6 @@ static void hybrid_graphics_init(void) pci_write_config32(PCI_DEV(0, 0, 0), DEVEN, reg32); } -void mainboard_pch_lpc_setup(void) -{ - pci_write_config32(PCH_LPC_DEV, ETR3, 0x10000); -} - void mainboard_early_init(int s3resume) { hybrid_graphics_init(); diff --git a/src/mainboard/lenovo/x1_carbon_gen1/early_init.c b/src/mainboard/lenovo/x1_carbon_gen1/early_init.c index c70b21d36b..c65b45482e 100644 --- a/src/mainboard/lenovo/x1_carbon_gen1/early_init.c +++ b/src/mainboard/lenovo/x1_carbon_gen1/early_init.c @@ -28,11 +28,6 @@ #include #include -void mainboard_pch_lpc_setup(void) -{ - pci_write_config32(PCH_LPC_DEV, ETR3, 0x10000); -} - const struct southbridge_usb_port mainboard_usb_ports[] = { /* enabled, current, OC pin */ { 0, 3, 0 }, /* P00 disconnected */ diff --git a/src/mainboard/lenovo/x220/early_init.c b/src/mainboard/lenovo/x220/early_init.c index 8ee807cb5d..7a29d1840b 100644 --- a/src/mainboard/lenovo/x220/early_init.c +++ b/src/mainboard/lenovo/x220/early_init.c @@ -27,11 +27,6 @@ #include #include -void mainboard_pch_lpc_setup(void) -{ - pci_write_config32(PCH_LPC_DEV, ETR3, 0x10000); -} - void mainboard_fill_pei_data(struct pei_data *pei_data) { struct pei_data pei_data_template = { diff --git a/src/mainboard/lenovo/x230/early_init.c b/src/mainboard/lenovo/x230/early_init.c index b737e7de83..a6853a1d74 100644 --- a/src/mainboard/lenovo/x230/early_init.c +++ b/src/mainboard/lenovo/x230/early_init.c @@ -24,11 +24,6 @@ #include #include -void mainboard_pch_lpc_setup(void) -{ - pci_write_config32(PCH_LPC_DEV, ETR3, 0x10000); -} - const struct southbridge_usb_port mainboard_usb_ports[] = { { 1, 0, 0 }, /* P0 (left, fan side), OC 0 */ { 1, 0, 1 }, /* P1 (left touchpad side), OC 1 */ From 3ad93615be8ac71308bdaa90a5ddd6ed57a304a1 Mon Sep 17 00:00:00 2001 From: Nico Huber Date: Sun, 17 Nov 2019 01:06:02 +0100 Subject: [PATCH 0232/1242] mb/gigabyte/ga-b75m-d3h: Drop useless function-disable setting This bit is already cleared by a reset. Change-Id: Ib71496011c9621476a7327ba309f367c7fa971e4 Signed-off-by: Nico Huber Reviewed-on: https://review.coreboot.org/c/coreboot/+/36890 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Rudolph Reviewed-by: Arthur Heymans --- src/mainboard/gigabyte/ga-b75m-d3h/early_init.c | 6 ------ 1 file changed, 6 deletions(-) diff --git a/src/mainboard/gigabyte/ga-b75m-d3h/early_init.c b/src/mainboard/gigabyte/ga-b75m-d3h/early_init.c index 65616ffa19..265e5114bc 100644 --- a/src/mainboard/gigabyte/ga-b75m-d3h/early_init.c +++ b/src/mainboard/gigabyte/ga-b75m-d3h/early_init.c @@ -82,9 +82,3 @@ void mainboard_get_spd(spd_raw_data *spd, bool id_only) read_spd(&spd[2], 0x52, id_only); read_spd(&spd[3], 0x53, id_only); } - -void mainboard_late_rcba_config(void) -{ - /* Enable HECI */ - RCBA32(FD2) &= ~0x2; -} From e036aaede49c3add3b1d9ce6ef7ae7f849b0683f Mon Sep 17 00:00:00 2001 From: Nico Huber Date: Sun, 17 Nov 2019 01:24:44 +0100 Subject: [PATCH 0233/1242] mb/google(sandybrige): Clean up LPC and IOAPIC configuration Only set LPC decode bits that the generic PCH code doesn't set yet. And don't enable the IOAPIC, which is already done by generic code. Change-Id: I9d2f6a9ad3f5d83573e07596f2763edc75f4ee64 Signed-off-by: Nico Huber Reviewed-on: https://review.coreboot.org/c/coreboot/+/36891 Tested-by: build bot (Jenkins) Reviewed-by: Arthur Heymans --- src/mainboard/google/butterfly/early_init.c | 12 ------------ src/mainboard/google/link/early_init.c | 10 ++-------- src/mainboard/google/parrot/early_init.c | 5 ----- src/mainboard/google/stout/early_init.c | 18 ------------------ 4 files changed, 2 insertions(+), 43 deletions(-) diff --git a/src/mainboard/google/butterfly/early_init.c b/src/mainboard/google/butterfly/early_init.c index d6566d1b09..19910bac99 100644 --- a/src/mainboard/google/butterfly/early_init.c +++ b/src/mainboard/google/butterfly/early_init.c @@ -28,13 +28,6 @@ #include #endif -void mainboard_pch_lpc_setup(void) -{ - /* EC Decode Range Port60/64 and Port62/66 */ - /* Enable EC and PS/2 Keyboard/Mouse*/ - pci_write_config16(PCH_LPC_DEV, LPC_EN, KBC_LPC_EN | MC_LPC_EN); -} - void mainboard_late_rcba_config(void) { u32 reg32; @@ -76,11 +69,6 @@ void mainboard_late_rcba_config(void) DIR_ROUTE(D25IR, PIRQA, PIRQB, PIRQC, PIRQD); DIR_ROUTE(D22IR, PIRQA, PIRQB, PIRQC, PIRQD); - /* Enable IOAPIC (generic) */ - RCBA16(OIC) = 0x0100; - /* PCH BWG says to read back the IOAPIC enable register */ - (void) RCBA16(OIC); - /* Disable unused devices (board specific) */ reg32 = RCBA32(FD); /* Disable PCI bridge so MRC does not probe this bus */ diff --git a/src/mainboard/google/link/early_init.c b/src/mainboard/google/link/early_init.c index 9d985e622c..8c58054463 100644 --- a/src/mainboard/google/link/early_init.c +++ b/src/mainboard/google/link/early_init.c @@ -34,9 +34,8 @@ void mainboard_pch_lpc_setup(void) { - /* Enable PS/2 Keyboard/Mouse, EC areas and COM1 */ - pci_write_config16(PCH_LPC_DEV, LPC_EN, KBC_LPC_EN | MC_LPC_EN | \ - GAMEL_LPC_EN | COMA_LPC_EN); + /* Enable additional 0x200..0x207 for EC */ + pci_or_config16(PCH_LPC_DEV, LPC_EN, GAMEL_LPC_EN); } void mainboard_late_rcba_config(void) @@ -74,11 +73,6 @@ void mainboard_late_rcba_config(void) DIR_ROUTE(D26IR, PIRQF, PIRQE, PIRQG, PIRQH); DIR_ROUTE(D25IR, PIRQA, PIRQB, PIRQC, PIRQD); DIR_ROUTE(D22IR, PIRQA, PIRQB, PIRQC, PIRQD); - - /* Enable IOAPIC (generic) */ - RCBA16(OIC) = 0x0100; - /* PCH BWG says to read back the IOAPIC enable register */ - (void) RCBA16(OIC); } static uint8_t *locate_spd(void) diff --git a/src/mainboard/google/parrot/early_init.c b/src/mainboard/google/parrot/early_init.c index 3c07dc8c54..7310b01b7f 100644 --- a/src/mainboard/google/parrot/early_init.c +++ b/src/mainboard/google/parrot/early_init.c @@ -68,11 +68,6 @@ void mainboard_late_rcba_config(void) DIR_ROUTE(D25IR, PIRQA, PIRQB, PIRQC, PIRQD); DIR_ROUTE(D22IR, PIRQA, PIRQB, PIRQC, PIRQD); - /* Enable IOAPIC (generic) */ - RCBA16(OIC) = 0x0100; - /* PCH BWG says to read back the IOAPIC enable register */ - (void) RCBA16(OIC); - /* Disable unused devices (board specific) */ reg32 = RCBA32(FD); /* Disable PCI bridge so MRC does not probe this bus */ diff --git a/src/mainboard/google/stout/early_init.c b/src/mainboard/google/stout/early_init.c index 6ee982ad73..94d409297c 100644 --- a/src/mainboard/google/stout/early_init.c +++ b/src/mainboard/google/stout/early_init.c @@ -30,19 +30,6 @@ #include "ec.h" #include "onboard.h" -void mainboard_pch_lpc_setup(void) -{ - /* - * Enable: - * EC Decode Range Port62/66 - * SuperIO Port2E/2F - * PS/2 Keyboard/Mouse Port60/64 - * FDD Port3F0h-3F5h and Port3F7h - */ - pci_write_config16(PCH_LPC_DEV, LPC_EN, KBC_LPC_EN | MC_LPC_EN | - CNF1_LPC_EN | FDD_LPC_EN); -} - void mainboard_late_rcba_config(void) { u32 reg32; @@ -85,11 +72,6 @@ void mainboard_late_rcba_config(void) DIR_ROUTE(D22IR, PIRQA, PIRQB, PIRQC, PIRQD); DIR_ROUTE(D20IR, PIRQD, PIRQE, PIRQF, PIRQG); - /* Enable IOAPIC (generic) */ - RCBA16(OIC) = 0x0100; - /* PCH BWG says to read back the IOAPIC enable register */ - (void) RCBA16(OIC); - /* Disable unused devices (board specific) */ reg32 = RCBA32(FD); /* Disable PCI bridge so MRC does not probe this bus */ From 9f2eca50eaeb8a1b2d53867e8659d889f5ac5ad5 Mon Sep 17 00:00:00 2001 From: Nico Huber Date: Sun, 17 Nov 2019 01:27:54 +0100 Subject: [PATCH 0234/1242] mb/hp/revolve_810_g1: Don't clear BUC and beyond The BUC register is actually 8 bits wide and shouldn't be bluntly cleared. Change-Id: I2ffd2d161005e839e730102b56af4f66efeb551e Signed-off-by: Nico Huber Reviewed-on: https://review.coreboot.org/c/coreboot/+/36892 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Rudolph Reviewed-by: Arthur Heymans --- src/mainboard/hp/revolve_810_g1/early_init.c | 5 ----- 1 file changed, 5 deletions(-) diff --git a/src/mainboard/hp/revolve_810_g1/early_init.c b/src/mainboard/hp/revolve_810_g1/early_init.c index b464ce3daa..1245201963 100644 --- a/src/mainboard/hp/revolve_810_g1/early_init.c +++ b/src/mainboard/hp/revolve_810_g1/early_init.c @@ -25,11 +25,6 @@ #include #include -void mainboard_late_rcba_config(void) -{ - RCBA32(BUC) = 0x00000000; -} - const struct southbridge_usb_port mainboard_usb_ports[] = { { 1, 1, 0 }, { 1, 0, 0 }, From 052e3ef3345b0281de7a0f751ab6d3fd1b4d6932 Mon Sep 17 00:00:00 2001 From: Nico Huber Date: Sun, 17 Nov 2019 01:35:14 +0100 Subject: [PATCH 0235/1242] mb/intel/emeraldlake2: Revise early init Move UART initialization to bootblock_mainboard_early_init() and don't override the generic LPC decode settings. Change-Id: Icdab36ae0324175d3d51a050784b94a53d4b3b7c Signed-off-by: Nico Huber Reviewed-on: https://review.coreboot.org/c/coreboot/+/36893 Tested-by: build bot (Jenkins) Reviewed-by: Arthur Heymans --- src/mainboard/intel/emeraldlake2/early_init.c | 17 ++--------------- 1 file changed, 2 insertions(+), 15 deletions(-) diff --git a/src/mainboard/intel/emeraldlake2/early_init.c b/src/mainboard/intel/emeraldlake2/early_init.c index 94a46550b2..7aabf7c1ec 100644 --- a/src/mainboard/intel/emeraldlake2/early_init.c +++ b/src/mainboard/intel/emeraldlake2/early_init.c @@ -29,26 +29,13 @@ #define SIO_PORT 0x164e -void mainboard_pch_lpc_setup(void) -{ - pci_devfn_t dev = PCH_LPC_DEV; - - /* Enable SuperIO + PS/2 Keyboard/Mouse */ - u16 lpc_config = CNF1_LPC_EN | CNF2_LPC_EN | KBC_LPC_EN; - pci_write_config16(dev, LPC_EN, lpc_config); - - /* Enable COM1 */ - if (sio1007_enable_uart_at(SIO_PORT)) { - pci_write_config16(dev, LPC_EN, - lpc_config | COMA_LPC_EN); - } -} - void bootblock_mainboard_early_init(void) { const u16 port = SIO_PORT; const u16 runtime_port = 0x180; + sio1007_enable_uart_at(port); + /* Turn on configuration mode. */ outb(0x55, port); From cc32a6980797abc5ce6365ce4c4c8c7418c8c224 Mon Sep 17 00:00:00 2001 From: Nico Huber Date: Sun, 17 Nov 2019 01:45:50 +0100 Subject: [PATCH 0236/1242] mb/lenovo/s230u: Don't write BUC and beyond The BUC register is actually only 8 bits wide and setting bit 5 (disabling GbE) is already done by generic code. Change-Id: I4b8e14606c319e8bfc48d6757087f28af1bd5dfb Signed-off-by: Nico Huber Reviewed-on: https://review.coreboot.org/c/coreboot/+/36894 Tested-by: build bot (Jenkins) Reviewed-by: Arthur Heymans --- src/mainboard/lenovo/s230u/early_init.c | 5 ----- 1 file changed, 5 deletions(-) diff --git a/src/mainboard/lenovo/s230u/early_init.c b/src/mainboard/lenovo/s230u/early_init.c index 7c302b8999..2de0637140 100644 --- a/src/mainboard/lenovo/s230u/early_init.c +++ b/src/mainboard/lenovo/s230u/early_init.c @@ -40,11 +40,6 @@ void mainboard_pch_lpc_setup(void) ec_mm_set_bit(0x3b, 4); } -void mainboard_late_rcba_config(void) -{ - /* Disable devices. */ - RCBA32(BUC) = 0x00000020; -} const struct southbridge_usb_port mainboard_usb_ports[] = { { 1, 1, 0 }, { 1, 0, 0 }, From 25128a79970bc9756ad33e1f1740e11321d1ff40 Mon Sep 17 00:00:00 2001 From: Nico Huber Date: Sun, 17 Nov 2019 01:24:44 +0100 Subject: [PATCH 0237/1242] mb/samsung: Clean up LPC and IOAPIC configuration Don't overwrite the LPC decode config of the generic PCH code, move UART init into bootblock_mainboard_early_init() and don't enable the IOAPIC, which is already done by generic code. Change-Id: I90d090f5bff29174e68981fea3c3f04c666b1d28 Signed-off-by: Nico Huber Reviewed-on: https://review.coreboot.org/c/coreboot/+/36895 Tested-by: build bot (Jenkins) Reviewed-by: Arthur Heymans --- src/mainboard/samsung/lumpy/early_init.c | 24 ++++------------------ src/mainboard/samsung/stumpy/early_init.c | 25 +++-------------------- 2 files changed, 7 insertions(+), 42 deletions(-) diff --git a/src/mainboard/samsung/lumpy/early_init.c b/src/mainboard/samsung/lumpy/early_init.c index 6bc545c57e..af4e55dc22 100644 --- a/src/mainboard/samsung/lumpy/early_init.c +++ b/src/mainboard/samsung/lumpy/early_init.c @@ -17,6 +17,7 @@ #include #include #include +#include #include #include #include @@ -33,22 +34,10 @@ #include #endif -void mainboard_pch_lpc_setup(void) +void bootblock_mainboard_early_init(void) { - /* Set COM1/COM2 decode range */ - pci_write_config16(PCH_LPC_DEV, LPC_IO_DEC, 0x0010); - -#if CONFIG(DRIVERS_UART_8250IO) - /* Enable SuperIO + EC + KBC + COM1 + lpc47n207 config*/ - pci_write_config16(PCH_LPC_DEV, LPC_EN, CNF1_LPC_EN | MC_LPC_EN | - KBC_LPC_EN | CNF2_LPC_EN | COMA_LPC_EN); - - try_enabling_LPC47N207_uart(); -#else - /* Enable SuperIO + EC + KBC */ - pci_write_config16(PCH_LPC_DEV, LPC_EN, CNF1_LPC_EN | MC_LPC_EN | - KBC_LPC_EN); -#endif + if (CONFIG(DRIVERS_UART_8250IO)) + try_enabling_LPC47N207_uart(); } void mainboard_late_rcba_config(void) @@ -88,11 +77,6 @@ void mainboard_late_rcba_config(void) DIR_ROUTE(D26IR, PIRQB, PIRQC, PIRQD, PIRQA); DIR_ROUTE(D25IR, PIRQA, PIRQB, PIRQC, PIRQD); DIR_ROUTE(D22IR, PIRQA, PIRQB, PIRQC, PIRQD); - - /* Enable IOAPIC (generic) */ - RCBA16(OIC) = 0x0100; - /* PCH BWG says to read back the IOAPIC enable register */ - (void) RCBA16(OIC); } static const uint8_t *locate_spd(void) diff --git a/src/mainboard/samsung/stumpy/early_init.c b/src/mainboard/samsung/stumpy/early_init.c index 03cb8d70a3..7fca8adfcc 100644 --- a/src/mainboard/samsung/stumpy/early_init.c +++ b/src/mainboard/samsung/stumpy/early_init.c @@ -46,23 +46,6 @@ #define SERIAL_DEV PNP_DEV(0x2e, IT8772F_SP1) #define GPIO_DEV PNP_DEV(0x2e, IT8772F_GPIO) -void mainboard_pch_lpc_setup(void) -{ - /* Set COM1/COM2 decode range */ - pci_write_config16(PCH_LPC_DEV, LPC_IO_DEC, 0x0010); - -#if CONFIG(DRIVERS_UART_8250IO) - /* Enable SuperIO + PS/2 Keyboard/Mouse + COM1 + lpc47n207 config*/ - pci_write_config16(PCH_LPC_DEV, LPC_EN, CNF1_LPC_EN | KBC_LPC_EN |\ - CNF2_LPC_EN | COMA_LPC_EN); - - try_enabling_LPC47N207_uart(); -#else - /* Enable SuperIO + PS/2 Keyboard/Mouse */ - pci_write_config16(PCH_LPC_DEV, LPC_EN, CNF1_LPC_EN | KBC_LPC_EN); -#endif -} - void mainboard_late_rcba_config(void) { /* @@ -97,11 +80,6 @@ void mainboard_late_rcba_config(void) DIR_ROUTE(D26IR, PIRQE, PIRQF, PIRQG, PIRQH); DIR_ROUTE(D25IR, PIRQA, PIRQB, PIRQC, PIRQD); DIR_ROUTE(D22IR, PIRQA, PIRQB, PIRQC, PIRQD); - - /* Enable IOAPIC (generic) */ - RCBA16(OIC) = 0x0100; - /* PCH BWG says to read back the IOAPIC enable register */ - (void) RCBA16(OIC); } static void setup_sio_gpios(void) @@ -242,6 +220,9 @@ int mainboard_should_reset_usb(int s3resume) void bootblock_mainboard_early_init(void) { + if (CONFIG(DRIVERS_UART_8250IO)) + try_enabling_LPC47N207_uart(); + setup_sio_gpios(); /* Early SuperIO setup */ From 6b7b016b6006feb22b48a44b25fd71f1f39ad9cb Mon Sep 17 00:00:00 2001 From: Nico Huber Date: Sun, 17 Nov 2019 01:45:50 +0100 Subject: [PATCH 0238/1242] mb/sapphire/pureplatinumh61: Don't write BUC and beyond The BUC register is actually only 8 bits wide and setting bit 5 (disabling GbE) is already done by generic code. Change-Id: I729a2a28f4b0d94eddd070dc89b7341ac0c35e4a Signed-off-by: Nico Huber Reviewed-on: https://review.coreboot.org/c/coreboot/+/36900 Tested-by: build bot (Jenkins) Reviewed-by: Arthur Heymans --- src/mainboard/sapphire/pureplatinumh61/early_init.c | 5 ----- 1 file changed, 5 deletions(-) diff --git a/src/mainboard/sapphire/pureplatinumh61/early_init.c b/src/mainboard/sapphire/pureplatinumh61/early_init.c index be665617a4..9a1b6856ff 100644 --- a/src/mainboard/sapphire/pureplatinumh61/early_init.c +++ b/src/mainboard/sapphire/pureplatinumh61/early_init.c @@ -26,11 +26,6 @@ void mainboard_pch_lpc_setup(void) pci_write_config32(PCI_DEV(0, 0x1f, 0), 0xac, 0x00010000); } -void mainboard_late_rcba_config(void) -{ - /* Disable devices. */ - RCBA32(0x3414) = 0x00000020; -} const struct southbridge_usb_port mainboard_usb_ports[] = { { 1, 0, 0 }, { 1, 0, 0 }, From 1d29b7bbceed82a2161e249474086169ac3039f4 Mon Sep 17 00:00:00 2001 From: Nico Huber Date: Sun, 17 Nov 2019 02:43:08 +0100 Subject: [PATCH 0239/1242] mb/intel/dcp847ske: Disable xHCI via devicetree This is supported by generic PCH code now. Change-Id: Id5d764c97e47cdb08a68d03002ebebd996769914 Signed-off-by: Nico Huber Reviewed-on: https://review.coreboot.org/c/coreboot/+/36901 Tested-by: build bot (Jenkins) Reviewed-by: Arthur Heymans --- src/mainboard/intel/dcp847ske/devicetree.cb | 1 + src/mainboard/intel/dcp847ske/early_southbridge.c | 2 +- 2 files changed, 2 insertions(+), 1 deletion(-) diff --git a/src/mainboard/intel/dcp847ske/devicetree.cb b/src/mainboard/intel/dcp847ske/devicetree.cb index ac152d85f9..6ed7c03120 100644 --- a/src/mainboard/intel/dcp847ske/devicetree.cb +++ b/src/mainboard/intel/dcp847ske/devicetree.cb @@ -39,6 +39,7 @@ chip northbridge/intel/sandybridge register "gen1_dec" = "0x00fc0a01" # SuperIO @0xa00-0xaff + device pci 14.0 off end # USB xHCI device pci 16.0 on end # Management Engine Interface 1 device pci 16.1 off end # Management Engine Interface 2 device pci 16.2 off end # Management Engine IDE-R diff --git a/src/mainboard/intel/dcp847ske/early_southbridge.c b/src/mainboard/intel/dcp847ske/early_southbridge.c index 53f5564a97..1f76db8e52 100644 --- a/src/mainboard/intel/dcp847ske/early_southbridge.c +++ b/src/mainboard/intel/dcp847ske/early_southbridge.c @@ -31,7 +31,7 @@ void mainboard_late_rcba_config(void) { /* Disable devices */ - RCBA32(FD) |= PCH_DISABLE_P2P | PCH_DISABLE_XHCI; + RCBA32(FD) |= PCH_DISABLE_P2P; #if CONFIG(USE_NATIVE_RAMINIT) /* Enable Gigabit Ethernet */ From 6760e0bdcd37e904c121800652cd2ac3920d9cd9 Mon Sep 17 00:00:00 2001 From: Nico Huber Date: Sun, 17 Nov 2019 02:34:53 +0100 Subject: [PATCH 0240/1242] sb/intel/bd82x6x: Handle enabling of GbE The integrated GbE port is toggled via the Backed-Up Control (BUC) register. We already disable it according to the devicetree setting but never enabled it. This could lead to the confusing situation that it was disabled before (different build, vendor BIOS, etc.) but shouldn't be anymore. As we need a full reset after enabling GbE, do it in early PCH init. Change-Id: I9db3d1923684b938d2c9f5b369b0953570c7fc15 Signed-off-by: Nico Huber Reviewed-on: https://review.coreboot.org/c/coreboot/+/36902 Tested-by: build bot (Jenkins) Reviewed-by: Arthur Heymans --- .../intel/dcp847ske/early_southbridge.c | 10 ------- src/southbridge/intel/bd82x6x/early_pch.c | 28 ++++++++++++++++++- src/southbridge/intel/bd82x6x/pch.c | 2 +- 3 files changed, 28 insertions(+), 12 deletions(-) diff --git a/src/mainboard/intel/dcp847ske/early_southbridge.c b/src/mainboard/intel/dcp847ske/early_southbridge.c index 1f76db8e52..34310a0094 100644 --- a/src/mainboard/intel/dcp847ske/early_southbridge.c +++ b/src/mainboard/intel/dcp847ske/early_southbridge.c @@ -33,16 +33,6 @@ void mainboard_late_rcba_config(void) /* Disable devices */ RCBA32(FD) |= PCH_DISABLE_P2P; -#if CONFIG(USE_NATIVE_RAMINIT) - /* Enable Gigabit Ethernet */ - if (RCBA32(BUC) & PCH_DISABLE_GBE) { - RCBA32(BUC) &= ~PCH_DISABLE_GBE; - /* Datasheet says clearing the bit requires a reset after */ - printk(BIOS_DEBUG, "Enabled gigabit ethernet, reset once.\n"); - full_reset(); - } -#endif - /* Set "mobile" bit in MCH (which makes sense layout-wise). */ /* Note sure if this has any effect at all though. */ MCHBAR32(0x0004) |= 0x00001000; diff --git a/src/southbridge/intel/bd82x6x/early_pch.c b/src/southbridge/intel/bd82x6x/early_pch.c index 8ffb22e140..b12ad38f47 100644 --- a/src/southbridge/intel/bd82x6x/early_pch.c +++ b/src/southbridge/intel/bd82x6x/early_pch.c @@ -16,6 +16,7 @@ #include #include #include +#include #include #include #include @@ -253,6 +254,30 @@ static void pch_generic_setup(void) write_pmbase16(TCO1_CNT, 1 << 11); /* halt timer */ } +static void pch_enable_gbe(void) +{ + uint8_t wanted_buc; + + /* Don't do this in the bootblock, it might be RO. So one + couldn't change the setting later in an updated romstage. */ + if (ENV_BOOTBLOCK) + return; + + const struct device *const gbe = pcidev_on_root(0x19, 0); + if (gbe && gbe->enabled) + wanted_buc = RCBA8(BUC) & ~PCH_DISABLE_GBE; + else + wanted_buc = RCBA8(BUC) | PCH_DISABLE_GBE; + + if (RCBA8(BUC) != wanted_buc) { + RCBA8(BUC) = wanted_buc; + /* Be double sure not to reset for naught. */ + if (RCBA8(BUC) != wanted_buc) + return; + full_reset(); + } +} + static void pch_enable_lpc_decode(void) { /* @@ -292,7 +317,6 @@ __weak void mainboard_pch_lpc_setup(void) void early_pch_init(void) { - pch_enable_lpc_decode(); mainboard_pch_lpc_setup(); @@ -301,5 +325,7 @@ void early_pch_init(void) pch_generic_setup(); + pch_enable_gbe(); + setup_pch_gpios(&mainboard_gpio_map); } diff --git a/src/southbridge/intel/bd82x6x/pch.c b/src/southbridge/intel/bd82x6x/pch.c index 3cd39a6706..5c2b130b7e 100644 --- a/src/southbridge/intel/bd82x6x/pch.c +++ b/src/southbridge/intel/bd82x6x/pch.c @@ -166,7 +166,7 @@ static void pch_hide_devfn(unsigned int devfn) RCBA32_OR(FD2, PCH_DISABLE_KT); break; case PCI_DEVFN(25, 0): /* Gigabit Ethernet */ - RCBA32_OR(BUC, PCH_DISABLE_GBE); + /* BUC is already handled in `early_pch.c`. */ break; case PCI_DEVFN(26, 0): /* EHCI #2 */ RCBA32_OR(FD, PCH_DISABLE_EHCI2); From 47bf4986815407393c1cf02922c882ed0f336bb2 Mon Sep 17 00:00:00 2001 From: Nico Huber Date: Sun, 17 Nov 2019 02:58:00 +0100 Subject: [PATCH 0241/1242] nb/intel/sandybridge/mrc: Handle P2P disabling via devicetree Some Sandy Bridge boards disabled the PCI-to-PCI bridge early to avoid probing by the MRC. We can do that for all boards instead, based on the devicetree setting. Change-Id: Ie64774628fde77db2a379bdba6a921a31e52fa0d Signed-off-by: Nico Huber Reviewed-on: https://review.coreboot.org/c/coreboot/+/36903 Tested-by: build bot (Jenkins) Reviewed-by: Arthur Heymans --- src/mainboard/google/butterfly/early_init.c | 8 -------- src/mainboard/google/parrot/early_init.c | 8 -------- src/mainboard/google/stout/early_init.c | 8 -------- src/mainboard/intel/dcp847ske/early_southbridge.c | 3 --- src/mainboard/kontron/ktqm77/early_init.c | 11 ----------- src/mainboard/roda/rv11/early_init.c | 11 ----------- src/northbridge/intel/sandybridge/raminit_mrc.c | 13 +++++++++++++ 7 files changed, 13 insertions(+), 49 deletions(-) diff --git a/src/mainboard/google/butterfly/early_init.c b/src/mainboard/google/butterfly/early_init.c index 19910bac99..4980fa8dfb 100644 --- a/src/mainboard/google/butterfly/early_init.c +++ b/src/mainboard/google/butterfly/early_init.c @@ -30,8 +30,6 @@ void mainboard_late_rcba_config(void) { - u32 reg32; - /* * GFX INTA -> PIRQA (MSI) * D28IP_P1IP WLAN INTA -> PIRQB @@ -68,12 +66,6 @@ void mainboard_late_rcba_config(void) DIR_ROUTE(D26IR, PIRQF, PIRQE, PIRQG, PIRQH); DIR_ROUTE(D25IR, PIRQA, PIRQB, PIRQC, PIRQD); DIR_ROUTE(D22IR, PIRQA, PIRQB, PIRQC, PIRQD); - - /* Disable unused devices (board specific) */ - reg32 = RCBA32(FD); - /* Disable PCI bridge so MRC does not probe this bus */ - reg32 |= PCH_DISABLE_P2P; - RCBA32(FD) = reg32; } const struct southbridge_usb_port mainboard_usb_ports[] = { diff --git a/src/mainboard/google/parrot/early_init.c b/src/mainboard/google/parrot/early_init.c index 7310b01b7f..74c5c8694f 100644 --- a/src/mainboard/google/parrot/early_init.c +++ b/src/mainboard/google/parrot/early_init.c @@ -28,8 +28,6 @@ void mainboard_late_rcba_config(void) { - u32 reg32; - /* * GFX INTA -> PIRQA (MSI) * D28IP_P2IP WLAN INTA -> PIRQB @@ -67,12 +65,6 @@ void mainboard_late_rcba_config(void) DIR_ROUTE(D26IR, PIRQF, PIRQE, PIRQG, PIRQH); DIR_ROUTE(D25IR, PIRQA, PIRQB, PIRQC, PIRQD); DIR_ROUTE(D22IR, PIRQA, PIRQB, PIRQC, PIRQD); - - /* Disable unused devices (board specific) */ - reg32 = RCBA32(FD); - /* Disable PCI bridge so MRC does not probe this bus */ - reg32 |= PCH_DISABLE_P2P; - RCBA32(FD) = reg32; } void mainboard_fill_pei_data(struct pei_data *pei_data) diff --git a/src/mainboard/google/stout/early_init.c b/src/mainboard/google/stout/early_init.c index 94d409297c..754bec60bb 100644 --- a/src/mainboard/google/stout/early_init.c +++ b/src/mainboard/google/stout/early_init.c @@ -32,8 +32,6 @@ void mainboard_late_rcba_config(void) { - u32 reg32; - /* * GFX INTA -> PIRQA (MSI) * D20IP_XHCI XHCI INTA -> PIRQD (MSI) @@ -71,12 +69,6 @@ void mainboard_late_rcba_config(void) DIR_ROUTE(D25IR, PIRQA, PIRQB, PIRQC, PIRQD); DIR_ROUTE(D22IR, PIRQA, PIRQB, PIRQC, PIRQD); DIR_ROUTE(D20IR, PIRQD, PIRQE, PIRQF, PIRQG); - - /* Disable unused devices (board specific) */ - reg32 = RCBA32(FD); - /* Disable PCI bridge so MRC does not probe this bus */ - reg32 |= PCH_DISABLE_P2P; - RCBA32(FD) = reg32; } /* diff --git a/src/mainboard/intel/dcp847ske/early_southbridge.c b/src/mainboard/intel/dcp847ske/early_southbridge.c index 34310a0094..9cdcd5dec2 100644 --- a/src/mainboard/intel/dcp847ske/early_southbridge.c +++ b/src/mainboard/intel/dcp847ske/early_southbridge.c @@ -30,9 +30,6 @@ void mainboard_late_rcba_config(void) { - /* Disable devices */ - RCBA32(FD) |= PCH_DISABLE_P2P; - /* Set "mobile" bit in MCH (which makes sense layout-wise). */ /* Note sure if this has any effect at all though. */ MCHBAR32(0x0004) |= 0x00001000; diff --git a/src/mainboard/kontron/ktqm77/early_init.c b/src/mainboard/kontron/ktqm77/early_init.c index 6a483bc670..eac19f47bb 100644 --- a/src/mainboard/kontron/ktqm77/early_init.c +++ b/src/mainboard/kontron/ktqm77/early_init.c @@ -44,17 +44,6 @@ void mainboard_pch_lpc_setup(void) COMA_LPC_EN | COMB_LPC_EN); } -void mainboard_late_rcba_config(void) -{ - u32 reg32; - - /* Disable unused devices (board specific) */ - reg32 = RCBA32(FD); - /* Disable PCI bridge so MRC does not probe this bus */ - reg32 |= PCH_DISABLE_P2P; - RCBA32(FD) = reg32; -} - void bootblock_mainboard_early_init(void) { int lvds_3v = 0; /* 0 (5V) or 1 (3V3) */ diff --git a/src/mainboard/roda/rv11/early_init.c b/src/mainboard/roda/rv11/early_init.c index f1681384a8..5c5e8d8b93 100644 --- a/src/mainboard/roda/rv11/early_init.c +++ b/src/mainboard/roda/rv11/early_init.c @@ -16,17 +16,6 @@ #include #include -void mainboard_late_rcba_config(void) -{ - u32 reg32; - - /* Disable unused devices (board specific) */ - reg32 = RCBA32(FD); - /* Disable PCI bridge so MRC does not probe this bus */ - reg32 |= PCH_DISABLE_P2P; - RCBA32(FD) = reg32; -} - int mainboard_should_reset_usb(int s3resume) { return !s3resume; diff --git a/src/northbridge/intel/sandybridge/raminit_mrc.c b/src/northbridge/intel/sandybridge/raminit_mrc.c index a8acfbf980..29c766a59f 100644 --- a/src/northbridge/intel/sandybridge/raminit_mrc.c +++ b/src/northbridge/intel/sandybridge/raminit_mrc.c @@ -18,6 +18,7 @@ #include #include #include +#include #include #include #include @@ -382,6 +383,16 @@ static void devicetree_fill_pei_data(struct pei_data *pei_data) pei_data->usb3.xhci_streams = cfg->usb3.xhci_streams; } +static void disable_p2p(void) +{ + /* Disable PCI-to-PCI bridge early to prevent probing by MRC. */ + const struct device *const p2p = pcidev_on_root(0x1e, 0); + if (p2p && p2p->enabled) + return; + + RCBA32(FD) |= PCH_DISABLE_P2P; +} + void perform_raminit(int s3resume) { int cbmem_was_initted; @@ -423,6 +434,8 @@ void perform_raminit(int s3resume) } } + disable_p2p(); + pei_data.boot_mode = s3resume ? 2 : 0; timestamp_add_now(TS_BEFORE_INITRAM); sdram_initialize(&pei_data); From 556cc26337bc3b36b20f139b5627de441eba88ef Mon Sep 17 00:00:00 2001 From: Wim Vervoorn Date: Mon, 11 Nov 2019 14:28:32 +0100 Subject: [PATCH 0242/1242] src: Ignore Redundant offset remarks in ASL code IASL reports unnecessary/redundant use of offset operator. These messages are only masking usefull messages. Add -vw 2158 so this message isn't reported. BUG=N/A TEST=build Change-Id: Ie8507d3b3cb6f2e75cb87cd3e4bcc4280df27f77 Signed-off-by: Wim Vervoorn Reviewed-on: https://review.coreboot.org/c/coreboot/+/36857 Reviewed-by: Paul Menzel Reviewed-by: Patrick Georgi Tested-by: build bot (Jenkins) --- Makefile.inc | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/Makefile.inc b/Makefile.inc index 8de54a05a6..d3aa8856b4 100644 --- a/Makefile.inc +++ b/Makefile.inc @@ -258,7 +258,10 @@ endef # ResourceTemplate is the correct code. # As it's valid ASL, disable the warning. EMPTY_RESOURCE_TEMPLATE_WARNING = 3150 -IGNORED_IASL_WARNINGS = -vw $(EMPTY_RESOURCE_TEMPLATE_WARNING) +# Redundant offset remarks are not useful in any way and are masking useful +# ones that might indicate an issue so it is better to hide them. +REDUNDANT_OFFSET_REMARK = 2158 +IGNORED_IASL_WARNINGS = -vw $(EMPTY_RESOURCE_TEMPLATE_WARNING) -vw $(REDUNDANT_OFFSET_REMARK) define asl_template $(CONFIG_CBFS_PREFIX)/$(1).aml-file = $(obj)/$(1).aml From 4100c2a6e3d214dc679eb359de959de08b8d96f8 Mon Sep 17 00:00:00 2001 From: Patrick Georgi Date: Wed, 15 May 2019 21:39:57 +0200 Subject: [PATCH 0243/1242] build system: Add various compiler flags that enable warnings on UB Some types of Undefined Behavior can be determined statically at compile time and gcc now has a set of flags that make it emit warnings in that case instead of doing the __builtin_trap() / optimize / UD2-opcode dance that silently breaks the resulting binary. BUG=chromium:958270 BRANCH=none TEST=abuild passes (probably not) Change-Id: I3aa5ca00c9838cc7517160069310a1ef85372027 Signed-off-by: Patrick Georgi Reviewed-on: https://review.coreboot.org/c/coreboot/+/32814 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin --- Makefile.inc | 1 + 1 file changed, 1 insertion(+) diff --git a/Makefile.inc b/Makefile.inc index d3aa8856b4..66144cd2ac 100644 --- a/Makefile.inc +++ b/Makefile.inc @@ -419,6 +419,7 @@ CFLAGS_common += -fno-delete-null-pointer-checks ifeq ($(CCC_ANALYZER_OUTPUT_FORMAT),) CFLAGS_common += -Wno-packed-not-aligned CFLAGS_common += -fconserve-stack +CFLAGS_common += -Wnull-dereference -Wreturn-type # cf. commit f69a99db (coreboot: x86: enable gc-sections) CFLAGS_common += -Wno-unused-but-set-variable endif From 85b41445b5c4df5833eceb7e1602408dc6c68662 Mon Sep 17 00:00:00 2001 From: Julius Werner Date: Mon, 11 Nov 2019 16:49:56 -0800 Subject: [PATCH 0244/1242] ipq40xx: Run python script without explicit 'python' call This patch changes the ipq40xx Makefile.inc to follow established coreboot practice of calling Python scripts directly rather than invoking the 'python' interpreter explicitly. This has the added effect of honoring the scripts shebang (which in this case is set to 'python2'). Change-Id: If96e8313527c411ef1bb6386e03b6a209c750131 Signed-off-by: Julius Werner Reviewed-on: https://review.coreboot.org/c/coreboot/+/36763 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi --- src/soc/qualcomm/ipq40xx/Makefile.inc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/soc/qualcomm/ipq40xx/Makefile.inc b/src/soc/qualcomm/ipq40xx/Makefile.inc index b20ae24d60..5a0529e119 100644 --- a/src/soc/qualcomm/ipq40xx/Makefile.inc +++ b/src/soc/qualcomm/ipq40xx/Makefile.inc @@ -62,7 +62,7 @@ ifeq ($(CONFIG_USE_BLOBS),y) $(objcbfs)/bootblock.bin: $(call strip_quotes,$(CONFIG_SBL_ELF)) \ $(objcbfs)/bootblock.elf @printf " CRXBL $(subst $(obj)/,,$(^)) $(subst $(obj)/,,$(@))\n" - @python $(CONFIG_SBL_UTIL_PATH)/createxbl.py -f $(CONFIG_SBL_ELF) \ + @$(CONFIG_SBL_UTIL_PATH)/createxbl.py -f $(CONFIG_SBL_ELF) \ -s $(objcbfs)/bootblock.elf -o $@ -a 32 -b 32 endif From a2148377b5605e96860476bd7cffbabc6e92542e Mon Sep 17 00:00:00 2001 From: Julius Werner Date: Wed, 13 Nov 2019 19:50:33 -0800 Subject: [PATCH 0245/1242] include: Make stdbool.h a separate file This patch moves the traditional POSIX stdbool.h definitions out from stdint.h into their own file. This helps for using these definitions in commonlib code which may be compiled in different environments. For coreboot everything should chain-include this stuff via types.h anyway so nothing should change. Change-Id: Ic8d52be80b64d8e9564f3aee8975cb25e4c187f5 Signed-off-by: Julius Werner Reviewed-on: https://review.coreboot.org/c/coreboot/+/36837 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi --- src/arch/x86/include/arch/cpu.h | 3 +-- src/drivers/vpd/vpd.h | 2 +- src/ec/google/chromeec/ec.h | 3 +-- src/include/bootmem.h | 4 ++-- src/include/console/usb.h | 2 +- src/include/device/device.h | 3 +-- src/include/stdbool.h | 16 ++++++++++++++++ src/include/stdint.h | 9 --------- src/include/types.h | 3 ++- src/lib/imd.c | 1 + src/security/memory/memory.c | 2 +- .../common/block/include/intelblocks/cpulib.h | 3 +-- .../common/block/include/intelblocks/fast_spi.h | 3 +-- .../intel/common/block/include/intelblocks/pcr.h | 2 +- src/soc/mediatek/mt8183/include/soc/mt6358.h | 2 ++ 15 files changed, 32 insertions(+), 26 deletions(-) create mode 100644 src/include/stdbool.h diff --git a/src/arch/x86/include/arch/cpu.h b/src/arch/x86/include/arch/cpu.h index 9133f53065..d74d6de7b5 100644 --- a/src/arch/x86/include/arch/cpu.h +++ b/src/arch/x86/include/arch/cpu.h @@ -14,8 +14,7 @@ #ifndef ARCH_CPU_H #define ARCH_CPU_H -#include -#include +#include /* * EFLAGS bits diff --git a/src/drivers/vpd/vpd.h b/src/drivers/vpd/vpd.h index 244a7be6d7..1bae5132cd 100644 --- a/src/drivers/vpd/vpd.h +++ b/src/drivers/vpd/vpd.h @@ -7,7 +7,7 @@ #ifndef __VPD_H__ #define __VPD_H__ -#include +#include #define GOOGLE_VPD_2_0_OFFSET 0x600 diff --git a/src/ec/google/chromeec/ec.h b/src/ec/google/chromeec/ec.h index 9fb9c391cc..5ef4366117 100644 --- a/src/ec/google/chromeec/ec.h +++ b/src/ec/google/chromeec/ec.h @@ -17,8 +17,7 @@ #ifndef _EC_GOOGLE_CHROMEEC_EC_H #define _EC_GOOGLE_CHROMEEC_EC_H -#include -#include +#include #include "ec_commands.h" /* Fill in base and size of the IO port resources used. */ diff --git a/src/include/bootmem.h b/src/include/bootmem.h index 2e33fcdf76..53e2d0f9db 100644 --- a/src/include/bootmem.h +++ b/src/include/bootmem.h @@ -16,9 +16,9 @@ #ifndef BOOTMEM_H #define BOOTMEM_H -#include -#include #include +#include +#include /** * Bootmem types match to LB_MEM tags, except for the following: diff --git a/src/include/console/usb.h b/src/include/console/usb.h index 33edbf6e5f..ad57d522dc 100644 --- a/src/include/console/usb.h +++ b/src/include/console/usb.h @@ -17,7 +17,7 @@ #ifndef _CONSOLE_USB_H_ #define _CONSOLE_USB_H_ -#include +#include void usbdebug_init(void); int usbdebug_hw_init(bool force); diff --git a/src/include/device/device.h b/src/include/device/device.h index 405d816e15..b1c1651ec9 100644 --- a/src/include/device/device.h +++ b/src/include/device/device.h @@ -9,11 +9,10 @@ */ #if !defined(__ROMCC__) -#include -#include #include #include #include +#include struct device; struct pci_operations; diff --git a/src/include/stdbool.h b/src/include/stdbool.h new file mode 100644 index 0000000000..2eeb70ef5b --- /dev/null +++ b/src/include/stdbool.h @@ -0,0 +1,16 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef __STDBOOL_H__ +#define __STDBOOL_H__ + +#include + +#ifdef __ROMCC__ +typedef uint8_t bool; +#else +typedef _Bool bool; +#endif +#define true 1 +#define false 0 + +#endif /* __STDBOOL_H__ */ diff --git a/src/include/stdint.h b/src/include/stdint.h index 0a8e153d6a..67b0b0be08 100644 --- a/src/include/stdint.h +++ b/src/include/stdint.h @@ -101,13 +101,4 @@ typedef uint64_t u64; #define UINTMAX_MAX UINT64_MAX #endif -/* TODO: move into stdbool.h */ -#ifdef __ROMCC__ -typedef uint8_t bool; -#else -typedef _Bool bool; -#endif -#define true 1 -#define false 0 - #endif /* STDINT_H */ diff --git a/src/include/types.h b/src/include/types.h index 5902bc268a..30f243ff99 100644 --- a/src/include/types.h +++ b/src/include/types.h @@ -16,7 +16,8 @@ #ifndef __TYPES_H #define __TYPES_H -/* types.h is supposed to provide stdint and stddef defined in here: */ +/* types.h is supposed to provide the standard headers defined in here: */ +#include #include #include diff --git a/src/lib/imd.c b/src/lib/imd.c index 17ec2d9a48..b5fc34a9a0 100644 --- a/src/lib/imd.c +++ b/src/lib/imd.c @@ -19,6 +19,7 @@ #include #include #include +#include /* For more details on implementation and usage please see the imd.h header. */ diff --git a/src/security/memory/memory.c b/src/security/memory/memory.c index 14f28578b5..c815236c9c 100644 --- a/src/security/memory/memory.c +++ b/src/security/memory/memory.c @@ -14,7 +14,7 @@ * GNU General Public License for more details. */ -#include +#include #include "memory.h" /** diff --git a/src/soc/intel/common/block/include/intelblocks/cpulib.h b/src/soc/intel/common/block/include/intelblocks/cpulib.h index a422094b26..84e750e2af 100644 --- a/src/soc/intel/common/block/include/intelblocks/cpulib.h +++ b/src/soc/intel/common/block/include/intelblocks/cpulib.h @@ -17,8 +17,7 @@ #ifndef SOC_INTEL_COMMON_BLOCK_CPULIB_H #define SOC_INTEL_COMMON_BLOCK_CPULIB_H -#include -#include +#include /* * Set PERF_CTL MSR (0x199) P_Req with diff --git a/src/soc/intel/common/block/include/intelblocks/fast_spi.h b/src/soc/intel/common/block/include/intelblocks/fast_spi.h index 6499ca5f5c..e0e664931b 100644 --- a/src/soc/intel/common/block/include/intelblocks/fast_spi.h +++ b/src/soc/intel/common/block/include/intelblocks/fast_spi.h @@ -16,8 +16,7 @@ #ifndef SOC_INTEL_COMMON_BLOCK_FAST_SPI_H #define SOC_INTEL_COMMON_BLOCK_FAST_SPI_H -#include -#include +#include /* * Disable the BIOS write protect and Enable Prefetching and Caching. diff --git a/src/soc/intel/common/block/include/intelblocks/pcr.h b/src/soc/intel/common/block/include/intelblocks/pcr.h index c3af2fddc3..c6554a36e5 100644 --- a/src/soc/intel/common/block/include/intelblocks/pcr.h +++ b/src/soc/intel/common/block/include/intelblocks/pcr.h @@ -20,7 +20,7 @@ #define PCR_PORTID_SHIFT 16 #if !defined(__ACPI__) -#include +#include uint32_t pcr_read32(uint8_t pid, uint16_t offset); uint16_t pcr_read16(uint8_t pid, uint16_t offset); diff --git a/src/soc/mediatek/mt8183/include/soc/mt6358.h b/src/soc/mediatek/mt8183/include/soc/mt6358.h index 6b74695bab..1c3e563df8 100644 --- a/src/soc/mediatek/mt8183/include/soc/mt6358.h +++ b/src/soc/mediatek/mt8183/include/soc/mt6358.h @@ -16,6 +16,8 @@ #ifndef __SOC_MEDIATEK_MT6358_H__ #define __SOC_MEDIATEK_MT6358_H__ +#include + enum { PMIC_SWCID = 0x000a, PMIC_VM_MODE = 0x004e, From 9f19dd9f617a6167442fac536d628b04471de59a Mon Sep 17 00:00:00 2001 From: Julius Werner Date: Mon, 18 Nov 2019 18:21:27 -0800 Subject: [PATCH 0246/1242] mmio: Fix buffer_to_fifo32() order of arguments buffer_to_fifo32() is a simple wrapper to buffer_to_fifo32_prefix(), but unfortunately its arguments are swapped. This patch fixes the issue. Change-Id: I6414bf51dd9de681b3b87bbaf4ea4efc815f7ae1 Signed-off-by: Julius Werner Reviewed-on: https://review.coreboot.org/c/coreboot/+/36942 Reviewed-by: Hung-Te Lin Tested-by: build bot (Jenkins) --- payloads/libpayload/include/libpayload.h | 2 +- src/include/device/mmio.h | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/payloads/libpayload/include/libpayload.h b/payloads/libpayload/include/libpayload.h index bfe9da5f40..0bd5db8257 100644 --- a/payloads/libpayload/include/libpayload.h +++ b/payloads/libpayload/include/libpayload.h @@ -458,7 +458,7 @@ void buffer_to_fifo32_prefix(void *buffer, u32 prefix, int prefsz, size_t size, static inline void buffer_to_fifo32(void *buffer, size_t size, void *fifo, int fifo_stride, int fifo_width) { - buffer_to_fifo32_prefix(buffer, size, 0, 0, fifo, + buffer_to_fifo32_prefix(buffer, 0, 0, size, fifo, fifo_stride, fifo_width); } #endif diff --git a/src/include/device/mmio.h b/src/include/device/mmio.h index df36eb6f96..6596cf89ed 100644 --- a/src/include/device/mmio.h +++ b/src/include/device/mmio.h @@ -48,7 +48,7 @@ void buffer_to_fifo32_prefix(void *buffer, u32 prefix, int prefsz, size_t size, static inline void buffer_to_fifo32(void *buffer, size_t size, void *fifo, int fifo_stride, int fifo_width) { - buffer_to_fifo32_prefix(buffer, size, 0, 0, fifo, + buffer_to_fifo32_prefix(buffer, 0, 0, size, fifo, fifo_stride, fifo_width); } From ceb7e68c48eafbfa9b735842159e01e8d2123a93 Mon Sep 17 00:00:00 2001 From: Elyes HAOUAS Date: Tue, 19 Nov 2019 00:27:13 +0100 Subject: [PATCH 0247/1242] xcompile: Explicitly disable warning address-of-packed-member With GCC 9.x has a new warning *address-of-packed-member*. > -Waddress-of-packed-member > > Warn when the address of packed member of struct or union is > taken, which usually results in an unaligned pointer value. > This is enabled by default. This results in the build errors below, for example, with GCC 9.2 from Debian Sid/unstable. src/southbridge/intel/common/spi.c: In function 'spi_init': src/southbridge/intel/common/spi.c:298:19: error: taking address of packed member of 'struct ich7_spi_regs' may result in an unaligned pointer value [-Werror=address-of-packed-member] 298 | cntlr->optype = &ich7_spi->optype; | ^~~~~~~~~~~~~~~~~ Therefore, explicitly disable the warning. Change-Id: I01d0dcdd0f8252ab65b91f40bb5f5c5e8177a293 Signed-off-by: Elyes HAOUAS Signed-off-by: Paul Menzel Reviewed-on: https://review.coreboot.org/c/coreboot/+/36940 Reviewed-by: Patrick Georgi Reviewed-by: Jacob Garber Tested-by: build bot (Jenkins) --- util/xcompile/xcompile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/util/xcompile/xcompile b/util/xcompile/xcompile index f431625878..2d3da1e00e 100755 --- a/util/xcompile/xcompile +++ b/util/xcompile/xcompile @@ -227,7 +227,7 @@ SUBARCH_SUPPORTED+=${TSUPP-${TARCH}} GCC_CC_${TARCH}:=${GCC} GCC_CFLAGS_${TARCH}:=${CFLAGS_GCC} # Generally available for GCC's cc1: -GCC_CFLAGS_${TARCH}+=-Wlogical-op +GCC_CFLAGS_${TARCH}+=-Wlogical-op -Wno-address-of-packed-member GCC_ADAFLAGS_${TARCH}:=${CFLAGS_GCC} GCC_COMPILER_RT_${TARCH}:=${CC_RT_GCC} GCC_COMPILER_RT_FLAGS_${TARCH}:=${CC_RT_EXTRA_GCC} From 7fc928656e791064c46a4748f86466930bdf2de6 Mon Sep 17 00:00:00 2001 From: Julius Werner Date: Mon, 18 Nov 2019 13:01:06 -0800 Subject: [PATCH 0248/1242] lib/fmap: Disable pre-RAM cache for FSP 1.0 Due to the way CAR teardown is handled in FSP 1.0, the results of car_get_var_ptr() aren't always reliable, which can break things when running with FMAP cache. It might be possible to fix this but would make the code rather complicated, so let's just disable the feature on these platforms and hope they die out soon. Also allow this option to be used by platforms that don't have space for the cache and want to save a little more code. Change-Id: I7ffb1b8b08a7ca3fe8d53dc827e2c8521da064c7 Signed-off-by: Julius Werner Reviewed-on: https://review.coreboot.org/c/coreboot/+/36937 Tested-by: build bot (Jenkins) Reviewed-by: Werner Zeh Reviewed-by: Patrick Georgi --- src/arch/x86/car.ld | 3 +++ src/drivers/intel/fsp1_0/Kconfig | 1 + src/lib/Kconfig | 7 +++++++ src/lib/fmap.c | 11 +++++++---- src/soc/rockchip/rk3288/Kconfig | 1 + 5 files changed, 19 insertions(+), 4 deletions(-) diff --git a/src/arch/x86/car.ld b/src/arch/x86/car.ld index 972cb5234b..3680250993 100644 --- a/src/arch/x86/car.ld +++ b/src/arch/x86/car.ld @@ -58,7 +58,10 @@ #endif TIMESTAMP(., 0x200) + +#if !CONFIG(NO_FMAP_CACHE) FMAP_CACHE(., FMAP_SIZE) +#endif _car_ehci_dbg_info = .; /* Reserve sizeof(struct ehci_dbg_info). */ diff --git a/src/drivers/intel/fsp1_0/Kconfig b/src/drivers/intel/fsp1_0/Kconfig index 32a07771ee..1a1d4f7072 100644 --- a/src/drivers/intel/fsp1_0/Kconfig +++ b/src/drivers/intel/fsp1_0/Kconfig @@ -15,6 +15,7 @@ config PLATFORM_USES_FSP1_0 bool default n select CAR_GLOBAL_MIGRATION + select NO_FMAP_CACHE # doesn't work with CAR_GLOBAL restrictions help Selected for Intel processors/platform combinations that use the Intel Firmware Support Package (FSP) 1.0 for initialization. diff --git a/src/lib/Kconfig b/src/lib/Kconfig index cb1e4a5cc8..dd9974a817 100644 --- a/src/lib/Kconfig +++ b/src/lib/Kconfig @@ -68,3 +68,10 @@ config HWBASE_DIRECT_PCIDEV def_bool y endif + +config NO_FMAP_CACHE + bool + help + If your platform really doesn't want to use an FMAP cache (e.g. due to + space constraints), you can select this to disable warnings and save + a bit more code. diff --git a/src/lib/fmap.c b/src/lib/fmap.c index 4b4179c769..48aab8f3d5 100644 --- a/src/lib/fmap.c +++ b/src/lib/fmap.c @@ -60,6 +60,9 @@ static void report(const struct fmap *fmap) static void setup_preram_cache(struct mem_region_device *cache_mrdev) { + if (CONFIG(NO_FMAP_CACHE)) + return; + if (!ENV_ROMSTAGE_OR_BEFORE) { /* We get here if ramstage makes an FMAP access before calling cbmem_initialize(). We should avoid letting it come to that, @@ -70,10 +73,10 @@ static void setup_preram_cache(struct mem_region_device *cache_mrdev) } if (REGION_SIZE(fmap_cache) == 0) { - /* If you see this you really want to add an FMAP_CACHE to your - memlayout, unless you absolutely can't affort the 2K. */ - print_once(BIOS_NOTICE, - "NOTE: Running without FMAP_CACHE, should add it!\n"); + /* If you see this you should add FMAP_CACHE() to your memlayout + (or select NO_FMAP_CACHE if you can't afford the 2K). */ + print_once(BIOS_ERR, + "ERROR: FMAP_CACHE enabled but no region provided!\n"); return; } diff --git a/src/soc/rockchip/rk3288/Kconfig b/src/soc/rockchip/rk3288/Kconfig index 3aebab9754..6a44ccd2e0 100644 --- a/src/soc/rockchip/rk3288/Kconfig +++ b/src/soc/rockchip/rk3288/Kconfig @@ -29,6 +29,7 @@ config SOC_ROCKCHIP_RK3288 select MAINBOARD_FORCE_NATIVE_VGA_INIT select HAVE_LINEAR_FRAMEBUFFER select NO_BOOTBLOCK_CONSOLE + select NO_FMAP_CACHE if SOC_ROCKCHIP_RK3288 From 6098da9ea81067b91e67793aac05bc534edd5c3b Mon Sep 17 00:00:00 2001 From: Marshall Dawson Date: Fri, 15 Nov 2019 16:09:32 -0700 Subject: [PATCH 0249/1242] sb/amd/hudson: Fix typo in GEC firmware name Correct what looks to be errant characters in the makefile variable for the Gigabit Ethernet Controller. This should have no effect on any mainboards as none select the HUDSON_GEC_FWM symbol. Change-Id: Icb861d872973aaf2b653440cae00057d5ad89b20 Signed-off-by: Marshall Dawson Reviewed-on: https://review.coreboot.org/c/coreboot/+/36876 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi --- src/southbridge/amd/agesa/hudson/Makefile.inc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/southbridge/amd/agesa/hudson/Makefile.inc b/src/southbridge/amd/agesa/hudson/Makefile.inc index 8ad82d2766..5cb3755e8b 100644 --- a/src/southbridge/amd/agesa/hudson/Makefile.inc +++ b/src/southbridge/amd/agesa/hudson/Makefile.inc @@ -54,7 +54,7 @@ add_opt_prefix=$(if $(call strip_quotes, $(1)), $(2) $(call strip_quotes, $(1)), OPT_HUDSON_XHCI_FWM_FILE=$(call add_opt_prefix, $(CONFIG_HUDSON_XHCI_FWM_FILE), --xhci) OPT_HUDSON_IMC_FWM_FILE=$(call add_opt_prefix, $(CONFIG_HUDSON_IMC_FWM_FILE), --imc) -OPT_HUDSON_GEC_FWM_FILE=$(call add_opt_prefix, $(CONFIG_HUDSON_GEC_FWM_FILEddd), --gec) +OPT_HUDSON_GEC_FWM_FILE=$(call add_opt_prefix, $(CONFIG_HUDSON_GEC_FWM_FILE), --gec) $(obj)/amdfw.rom: $(call strip_quotes, $(CONFIG_HUDSON_XHCI_FWM_FILE)) \ $(call strip_quotes, $(CONFIG_HUDSON_IMC_FWM_FILE)) \ From a9112169267b209e72d5cf274fddb53f5febd7d2 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Michael=20Niew=C3=B6hner?= Date: Mon, 18 Nov 2019 19:51:57 +0100 Subject: [PATCH 0250/1242] docs: intel fsp: add memory retraining bug on SPS systems MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit FSP2.0 forces MRC retraining on cold boot on Intel SPS systems. Change-Id: I3ce812309b46bdb580557916a775043fda63667f Signed-off-by: Michael Niewöhner Reviewed-on: https://review.coreboot.org/c/coreboot/+/36935 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi --- .../supermicro/x11-lga1151-series/x11-lga1151-series.md | 2 +- Documentation/soc/intel/fsp/index.md | 6 ++++++ 2 files changed, 7 insertions(+), 1 deletion(-) diff --git a/Documentation/mainboard/supermicro/x11-lga1151-series/x11-lga1151-series.md b/Documentation/mainboard/supermicro/x11-lga1151-series/x11-lga1151-series.md index adee88acb2..2cb945ae14 100644 --- a/Documentation/mainboard/supermicro/x11-lga1151-series/x11-lga1151-series.md +++ b/Documentation/mainboard/supermicro/x11-lga1151-series/x11-lga1151-series.md @@ -31,7 +31,7 @@ Look at the [flashing tutorial] and the board-specific section. These issues apply to all boards. Have a look at the board-specific issues, too. - TianoCore doesn't work with Aspeed NGI, as it's text mode only (Fix is WIP CB:35726) -- MRC caching does not work with cold boot +- MRC caching does not work on cold boot with Intel SPS (see [Intel FSP2.0]) ## ToDo diff --git a/Documentation/soc/intel/fsp/index.md b/Documentation/soc/intel/fsp/index.md index aac7b35a50..769b98b4fc 100644 --- a/Documentation/soc/intel/fsp/index.md +++ b/Documentation/soc/intel/fsp/index.md @@ -34,6 +34,11 @@ those are fixed. If possible a workaround is described here as well. * Workaround: none * Issue on public tracker: [Issue 22] +* MRC forces memory re-training on cold boot on boards with Intel SPS + * Releases 3.7.1, 3.7.6 + * Workaround: Flash Intel ME instead of SPS + * Issue on public tracker: [Issue 41] + ### BraswellFsp * Internal UART can't be disabled using PcdEnableHsuart* * Release MR2 @@ -66,4 +71,5 @@ those are fixed. If possible a workaround is described here as well. [Issue 15]: https://github.com/IntelFsp/FSP/issues/15 [Issue 22]: https://github.com/IntelFsp/FSP/issues/22 [Issue 35]: https://github.com/IntelFsp/FSP/issues/35 +[Issue 41]: https://github.com/IntelFsp/FSP/issues/41 From 2141bbbd4a1e41747a7ce7b047c4d81cc5b2cd29 Mon Sep 17 00:00:00 2001 From: Patrick Georgi Date: Tue, 19 Nov 2019 12:24:02 +0100 Subject: [PATCH 0251/1242] mb/google/octopus: Disable fmap cache for meep By removing this code, we get approximately back to where the board was before the fmap cache feature was added, which is small enough for the Chromium OS default configuration for the board to fit into the 32KB that the bootblock can use on the chipset again. Change-Id: I52c0c30a14929913ded144bf086c12938e9c2699 Signed-off-by: Patrick Georgi Reviewed-on: https://review.coreboot.org/c/coreboot/+/36925 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber --- src/mainboard/google/octopus/Kconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/src/mainboard/google/octopus/Kconfig b/src/mainboard/google/octopus/Kconfig index f67f64272c..d712600158 100644 --- a/src/mainboard/google/octopus/Kconfig +++ b/src/mainboard/google/octopus/Kconfig @@ -22,6 +22,7 @@ config BOARD_GOOGLE_BASEBOARD_OCTOPUS select MAINBOARD_HAS_SPI_TPM_CR50 select MAINBOARD_HAS_TPM2 select GOOGLE_SMBIOS_MAINBOARD_VERSION + select NO_FMAP_CACHE if BOARD_GOOGLE_MEEP if BOARD_GOOGLE_BASEBOARD_OCTOPUS From 53b549c43d97cebda68902ddcb9737e074a667c9 Mon Sep 17 00:00:00 2001 From: Patrick Georgi Date: Mon, 18 Nov 2019 09:21:28 +0100 Subject: [PATCH 0252/1242] configs: add google/meep cros config as regression test This config is a slightly stripped configuration of the Chromium OS configuration used in production. Apparently the bootblock fills up faster than usual on this device, resulting in address overflows. Add this config here so we'll notice early in the future. Change-Id: I3145bba63d32ddb9d00fd98d3cb774bf9ddd69a6 Signed-off-by: Patrick Georgi Reviewed-on: https://review.coreboot.org/c/coreboot/+/36923 Reviewed-by: Nico Huber Reviewed-by: Paul Menzel Reviewed-by: Arthur Heymans Tested-by: build bot (Jenkins) --- configs/config.google_meep_cros | 41 +++++++++++++++++++++++++++++++++ 1 file changed, 41 insertions(+) create mode 100644 configs/config.google_meep_cros diff --git a/configs/config.google_meep_cros b/configs/config.google_meep_cros new file mode 100644 index 0000000000..3963fd4a98 --- /dev/null +++ b/configs/config.google_meep_cros @@ -0,0 +1,41 @@ +CONFIG_VENDOR_GOOGLE=y +CONFIG_BOARD_GOOGLE_MEEP=y + +CONFIG_PAYLOAD_NONE=y +CONFIG_RESET_ON_INVALID_RAMSTAGE_CACHE=y +CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_SMM=y +CONFIG_USE_BLOBS=y +CONFIG_ANY_TOOLCHAIN=y + +# Chrome OS +CONFIG_CHROMEOS=y +CONFIG_HAS_RECOVERY_MRC_CACHE=y +CONFIG_MRC_CLEAR_NORMAL_CACHE_ON_RECOVERY_RETRAIN=y + +# Event Logging +CONFIG_CMOS_POST=y +CONFIG_CMOS_POST_EXTRA=y +CONFIG_CMOS_POST_OFFSET=0x70 +CONFIG_COLLECT_TIMESTAMPS=y +CONFIG_ELOG=y +CONFIG_ELOG_GSMI=y +CONFIG_ELOG_BOOT_COUNT=y +CONFIG_ELOG_BOOT_COUNT_CMOS_OFFSET=144 + +# Firmware Support Package +CONFIG_ADD_FSP_BINARIES=y +# CONFIG_RUN_FSP_GOP is not set + +# Management Engine +# CONFIG_LOCK_MANAGEMENT_ENGINE is not set + +# CONFIG_CONSOLE_SERIAL is not set + +CONFIG_FATAL_ASSERTS=y +CONFIG_CONSOLE_SERIAL=y +CONFIG_CONSOLE_SERIAL_115200=y +# CONFIG_DRIVERS_UART_8250IO is not set +# GLK specific setting to auto select all the correct settings. +CONFIG_UART_DEBUG=y +CONFIG_NO_BOOTBLOCK_CONSOLE=y From 44b54aa947caedef662e5401f006e96f58d1f70d Mon Sep 17 00:00:00 2001 From: Paul Menzel Date: Fri, 20 Sep 2019 10:09:12 +0200 Subject: [PATCH 0253/1242] Documentation: Reword Supermicro X10SLM+-F datasheet references Change-Id: I24c4254ef65edcddadcf0386e0cbe996a5e99458 Signed-off-by: Paul Menzel Reviewed-on: https://review.coreboot.org/c/coreboot/+/35486 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi --- Documentation/mainboard/supermicro/x10slm-f.md | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/Documentation/mainboard/supermicro/x10slm-f.md b/Documentation/mainboard/supermicro/x10slm-f.md index acb2c84fa2..703608028a 100644 --- a/Documentation/mainboard/supermicro/x10slm-f.md +++ b/Documentation/mainboard/supermicro/x10slm-f.md @@ -68,7 +68,7 @@ region is not readable even by the host. The main firmware flash chip is an SOIC-8 package located near the CMOS battery and SATA ports. It should come with a sticker attached that states the firmware revision (e.g. "X10SLH 4.424"). The chip model is -an N25Q128A, and the datasheet can be found [here][N25Q128A]. +an N25Q128A ([datasheet][N25Q128A]). As with [internal programming](#internal-programming), [flashrom] works reliably: @@ -87,8 +87,7 @@ way without issue. This board has an ASPEED [AST2400], which has BMC functionality. The BMC firmware resides in a 32 MiB SOIC-16 chip just above the [AST2400]. -This chip is an MX25L25635F, whose datasheet can be found -[here][MX25L25635F]. +This chip is an MX25L25635F ([datasheet][MX25L25635F]). ### Removing the BMC functionality From 593172c7c388d061c196203bd82650396bac1f68 Mon Sep 17 00:00:00 2001 From: Arthur Heymans Date: Thu, 17 Oct 2019 22:10:59 +0200 Subject: [PATCH 0254/1242] util/docker/Makefile: Add documentation docker image targets Run - make -C util/docker doc.coreboot.org to build the docker image - make -C util/docker docker-build-docs to build the documentation - make -C docker-livehtml-docs to serve autoupdated documentation over http://0.0.0.0:8000 Change-Id: Ic07f216f8d90d6e212383250b852dc91575304c3 Signed-off-by: Arthur Heymans Reviewed-on: https://review.coreboot.org/c/coreboot/+/36104 Reviewed-by: Patrick Georgi Tested-by: build bot (Jenkins) --- util/docker/Makefile | 23 +++++++++++++++++++++++ 1 file changed, 23 insertions(+) diff --git a/util/docker/Makefile b/util/docker/Makefile index 6925b57fdf..619de854c0 100644 --- a/util/docker/Makefile +++ b/util/docker/Makefile @@ -71,6 +71,10 @@ coreboot-jenkins-node: test-docker upload-coreboot-jenkins-node: test-docker-login $(DOCKER) push coreboot/coreboot-jenkins-node:$(COREBOOT_IMAGE_TAG) +doc.coreboot.org: test-docker + $(DOCKER) build --force-rm -t doc.coreboot.org \ + $(top)/util/docker/doc.coreboot.org/ + docker-killall: test-docker @if [ -n "$$($(DOCKER) ps | grep 'coreboot')" ]; then \ $(DOCKER) kill $$($(DOCKER) ps | grep 'coreboot' | cut -f1 -d ' '); \ @@ -166,12 +170,27 @@ docker-jenkins-attach: -it "$$(docker ps | grep coreboot-jenkins-node | cut -f1 -d' ')" \ /bin/bash -l +docker-build-docs: test-docker +docker-build-docs: + $(DOCKER) run -it --rm \ + --user $(UID):$(GID) \ + -v "$(top)/:/data-in/:ro" \ + -v "$(top)/Documentation/_build/:/data-out/" \ + doc.coreboot.org + +docker-livehtml-docs: test-docker +docker-livehtml-docs: + $(DOCKER) run -it --rm \ + --net=host -v "$(top)/:/data-in/:ro" \ + doc.coreboot.org livehtml + help: @echo "Commands for working with docker images:" @echo " coreboot-sdk - Build coreboot-sdk container" @echo " upload-coreboot-sdk - Upload coreboot-sdk to hub.docker.com" @echo " coreboot-jenkins-node - Build coreboot-jenkins-node container" @echo " upload-coreboot-jenkins-node - Upload coreboot-jenkins-node to hub.docker.com" + @echo " doc.coreboot.org - Build doc.coreboot.org container" @echo " clean-coreboot-containers - Remove all docker coreboot containers" @echo " clean-coreboot-images - Remove all docker coreboot images" @echo " clean-docker - Remove docker coreboot containers & images" @@ -186,6 +205,8 @@ help: @echo " " @echo " docker-jenkins-server - Run coreboot-jenkins-node image (for server)" @echo " docker-jenkins-attach - Open shell in running jenkins server" + @echo " docker-build-docs - Build the documentation" + @echo " docker-livehtml-docs - Run sphinx-autobuild" @echo @echo "Variables:" @echo " COREBOOT_JENKINS_PORT=$(COREBOOT_JENKINS_PORT)" @@ -197,7 +218,9 @@ help: .PHONY: test-docker test-docker-login .PHONY: coreboot-jenkins-node upload-coreboot-jenkins-node .PHONY: coreboot-sdk upload-coreboot-sdk +.PHONY: doc.coreboot.org .PHONY: clean-coreboot-containers clean-coreboot-images .PHONY: docker-abuild .PHONY: docker-what-jenkins-does docker-shell docker-jenkins-server docker-jenkins-attach +.PHONY: docker-build-docs docker-livehtml-docs .PHONY: help From e61b4c360e41033b41ead5a964f3a79c57f428b7 Mon Sep 17 00:00:00 2001 From: Paul Menzel Date: Mon, 30 Sep 2019 13:57:45 +0200 Subject: [PATCH 0255/1242] util/chromeos: Indent code blocks instead of using ``` This uses less lines, is the original Markdown syntax, and for short blocks better readable. Change-Id: Id96ad0f65980dfb943eef3cde5626d56f97622f9 Signed-off-by: Paul Menzel Reviewed-on: https://review.coreboot.org/c/coreboot/+/35729 Reviewed-by: Patrick Georgi Tested-by: build bot (Jenkins) --- util/chromeos/README.md | 23 ++++++++++------------- 1 file changed, 10 insertions(+), 13 deletions(-) diff --git a/util/chromeos/README.md b/util/chromeos/README.md index 0b9a7d74d8..964c6c5a76 100644 --- a/util/chromeos/README.md +++ b/util/chromeos/README.md @@ -11,14 +11,13 @@ image server, unpacks it, extracts the firmware update shell archive, extracts the firmware images from the shell archive. To download all Chrome OS firmware images, run -``` -$ ./crosfirmware.sh -``` + + $ ./crosfirmware.sh + To download, e.g. the Panther firmware image, run -``` -$ ./crosfirmware.sh panther -``` + + $ ./crosfirmware.sh panther ## extract_blobs.sh @@ -33,12 +32,10 @@ and `mrc.bin`. compatible format. Usage: -``` -$ ./gen_test_hwid.sh BOARD_NAME -``` + + $ ./gen_test_hwid.sh BOARD_NAME Example: -``` -$ ./gen_test_hwid.sh Kukui -KUKUI TEST 9847 -``` + + $ ./gen_test_hwid.sh Kukui + KUKUI TEST 9847 From 0209f3dd15f20b4286d80fbf42a476e9aec5efae Mon Sep 17 00:00:00 2001 From: Patrick Rudolph Date: Wed, 16 Oct 2019 08:58:26 +0200 Subject: [PATCH 0256/1242] Documentation: Remove duplicated entry The mainboard was accidently added due to bad rebase. Change-Id: Ie7215e551651dbbc8d92316c48e455405923a30b Signed-off-by: Patrick Rudolph Reviewed-on: https://review.coreboot.org/c/coreboot/+/36077 Reviewed-by: Nico Huber Tested-by: build bot (Jenkins) --- Documentation/mainboard/index.md | 4 ---- 1 file changed, 4 deletions(-) diff --git a/Documentation/mainboard/index.md b/Documentation/mainboard/index.md index 8e88443ac3..60302cbe0f 100644 --- a/Documentation/mainboard/index.md +++ b/Documentation/mainboard/index.md @@ -95,10 +95,6 @@ The boards in this section are not real mainboards, but emulators. - [T440p](lenovo/t440p.md) -## Portwell - -- [PQ7-M107](portwell/pq7-m107.md) - ## MSI - [MS-7707](msi/ms7707/ms7707.md) From ab8edda14a622ab46bdfd01b877d75c7bd385a4d Mon Sep 17 00:00:00 2001 From: Patrick Georgi Date: Tue, 19 Nov 2019 14:44:48 +0100 Subject: [PATCH 0257/1242] Documentation/releases: Finalize 4.11, start 4.12 Fill in some stats using our repo analysis scripts in util/release/, thank the contributors, add some prose about notable achievements since 4.10. Also start a new doc for 4.12. Change-Id: I10a39081762d6e01f4040f717d36662975e4c8e9 Signed-off-by: Patrick Georgi Reviewed-on: https://review.coreboot.org/c/coreboot/+/36948 Reviewed-by: Arthur Heymans Tested-by: build bot (Jenkins) --- .../releases/coreboot-4.11-relnotes.md | 105 ++++++++++++++++-- .../releases/coreboot-4.12-relnotes.md | 16 +++ Documentation/releases/index.md | 3 +- 3 files changed, 115 insertions(+), 9 deletions(-) create mode 100644 Documentation/releases/coreboot-4.12-relnotes.md diff --git a/Documentation/releases/coreboot-4.11-relnotes.md b/Documentation/releases/coreboot-4.11-relnotes.md index fa0da77a68..2d0b5cf5b5 100644 --- a/Documentation/releases/coreboot-4.11-relnotes.md +++ b/Documentation/releases/coreboot-4.11-relnotes.md @@ -1,18 +1,99 @@ Upcoming release - coreboot 4.11 ================================ -The 4.11 release is planned for October 2019 +coreboot 4.11 was released on November 19th. -Update this document with changes that should be in the release -notes. -* Please use Markdown. -* See the [4.9](coreboot-4.9-relnotes.md) and [4.10](coreboot-4.10-relnotes.md) - release notes for the general format. -* The chip and board additions and removals will be updated right - before the release, so those do not need to be added. +This release cycle was a bit shorter to get closer to our regular +schedule of releasing in spring and autumn. + +Since 4.10 there were 1630 new commits by over 130 developers. +Of these, about 30 contributed to coreboot for the first time. + +Thank you to all contributors who made 4.11 what it is and welcome +to the project to all new contributors! Clean Up -------- + +The past few months saw lots of cleanup across the source tree: + +The included headers in source files were stripped down to avoid reading +unused headers, and unused code fragments, duplicate preprocessor symbols +and configuration options were eliminated. Even ACPI got its share +of attention, making our tables and bytecode more standards compliant +than ever. + +The code across Intel's chipsets was unified some more into drivers for +common function blocks, an effort we're more confident will succeed now +that Intel itself is driving it. + +Chipset work +------------ + +Most activity in the last couple months was on Intel support, +specifically the Kaby Lake and Cannon Lake drivers were extended +for the generations following them. + +On ARM, the Mediatek 8173 chipset support saw significant work while +the AMD side worked on getting Picasso support in. + +But everything else also saw some action, the relatively old +(e.g. Intel GM45, Via VX900), the tiny (RISC-V) and the obscure +(Quark). + +Verified Boot +------------- + +The vboot feature that Chromebooks brought into coreboot was extended +to work on devices that weren't specially adapted for it: In addition +to its original device family it's now supported on various Lenovo +laptops, Open Compute Project systems and Siemens industrial machines. + +Eltan's support for measured boot continues to be integrated with +vboot, sharing data structures and generally working together where +possible. + +New devices +----------- + +With 4.11 there's the beginning of support for Intel Tiger Lake and +Qualcomm's SC7180 SoCs, while we removed the unmaintained support +for Allwinner's A10 SoC. + +There are also 25 new mainboards in our tree: + +* AMD PADMELON +* ASUS P5QL-EM +* EMULATION QEMU-AARCH64 +* GOOGLE AKEMI +* GOOGLE ARCADA CML +* GOOGLE DAMU +* GOOGLE DOOD +* GOOGLE DRALLION +* GOOGLE DRATINI +* GOOGLE JACUZZI +* GOOGLE JUNIPER +* GOOGLE KAKADU +* GOOGLE KAPPA +* GOOGLE PUFF +* GOOGLE SARIEN CML +* GOOGLE TREEYA +* GOOGLE TROGDOR +* LENOVO R60 +* LENOVO T410 +* LENOVO THINKPAD T440P +* LENOVO X301 +* RAZER BLADE-STEALTH KBL +* SIEMENS MC-APL6 +* SUPERMICRO X11SSH-TF +* SUPERMICRO X11SSM-F + +In addition to the Cubieboard (which uses the A10 SoC), we also +removed Google Hatch WHL. + +Deprecations +------------ + Because there was only a single developer board (AMD Torpedo) using AGESA family 12h, and because there were multiple, unique Coverity issues with it, the associated vendorcode will @@ -23,6 +104,11 @@ this release as the only board in the tree was a discontinued development board and no other work has picked up MIPS support, so it's very likely broken already. +After more than a year of planning and following the announcement in +coreboot 4.10, platforms not using relocatable ramstage, a C bootblock +and, on systems using Cache as RAM, a postcar stage, won't be supported +going forward. + Significant changes ------------------- @@ -90,14 +176,17 @@ Payload integration has been updated, coreinfo learned to cope with UPPER CASE commands and libpayload knows how to deal with USB3 hubs. ### Added VBOOT support to the following platforms: + * intel/gm45 * intel/nehalem ### Moved the following platforms to C_ENVIRONMENT_BOOTBLOCK: + * intel/i945 * intel/x4x * intel/gm45 * intel/nehalem +* intel/sandybridge * intel/braswell ### libgfxinit ### diff --git a/Documentation/releases/coreboot-4.12-relnotes.md b/Documentation/releases/coreboot-4.12-relnotes.md new file mode 100644 index 0000000000..f9c5f7ed74 --- /dev/null +++ b/Documentation/releases/coreboot-4.12-relnotes.md @@ -0,0 +1,16 @@ +Upcoming release - coreboot 4.12 +================================ + +The 4.12 release is planned for April 2020 + +Update this document with changes that should be in the release +notes. +* Please use Markdown. +* See the past few release notes for the general format. +* The chip and board additions and removals will be updated right + before the release, so those do not need to be added. + +Significant changes +------------------- + +### Add significant changes here diff --git a/Documentation/releases/index.md b/Documentation/releases/index.md index c49a61a29d..0a990f6d7b 100644 --- a/Documentation/releases/index.md +++ b/Documentation/releases/index.md @@ -11,6 +11,7 @@ Release notes for previous releases * [4.8 - May 2018](coreboot-4.8.1-relnotes.md) * [4.9 - December 2018](coreboot-4.9-relnotes.md) * [4.10 - July 2019](coreboot-4.10-relnotes.md) +* [4.11 - November 2019](coreboot-4.11-relnotes.md) The checklist contains instructions to ensure that a release covers all important things and provides a reliable format for tarballs, branch @@ -22,4 +23,4 @@ Upcoming release ---------------- Please add to the release notes as changes are added: -* [4.11 - October 2019](coreboot-4.11-relnotes.md) +* [4.12 - April 2020](coreboot-4.12-relnotes.md) From 29c8fa4769de86ba0b5f7a8791124121ff7dbe74 Mon Sep 17 00:00:00 2001 From: Yu-Ping Wu Date: Mon, 18 Nov 2019 11:25:47 +0800 Subject: [PATCH 0258/1242] security/vboot: Remove vboot_named_region_device(_rw) Remove vboot_named_region_device(_rw) and use fmap_locate_area_as_rdev(_rw) directly. BRANCH=none BUG=none TEST=emerge-kukui coreboot Change-Id: I244ac4e01ae5b80285162b3baffc0b30aa057bfb Signed-off-by: Yu-Ping Wu Reviewed-on: https://review.coreboot.org/c/coreboot/+/36922 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin --- src/security/vboot/vbnv_flash.c | 3 ++- src/security/vboot/vboot_common.c | 10 ---------- src/security/vboot/vboot_common.h | 6 ------ src/security/vboot/vboot_logic.c | 5 +++-- 4 files changed, 5 insertions(+), 19 deletions(-) diff --git a/src/security/vboot/vbnv_flash.c b/src/security/vboot/vbnv_flash.c index 908846fe70..86c43cd302 100644 --- a/src/security/vboot/vbnv_flash.c +++ b/src/security/vboot/vbnv_flash.c @@ -16,6 +16,7 @@ #include #include #include +#include #include #include #include @@ -67,7 +68,7 @@ static int init_vbnv(void) int offset; int i; - if (vboot_named_region_device_rw("RW_NVRAM", rdev) || + if (fmap_locate_area_as_rdev_rw("RW_NVRAM", rdev) || region_device_sz(rdev) < BLOB_SIZE) { printk(BIOS_ERR, "%s: failed to locate NVRAM\n", __func__); return 1; diff --git a/src/security/vboot/vboot_common.c b/src/security/vboot/vboot_common.c index 2d35c6be05..a24b220a9c 100644 --- a/src/security/vboot/vboot_common.c +++ b/src/security/vboot/vboot_common.c @@ -24,16 +24,6 @@ #include #include -int vboot_named_region_device(const char *name, struct region_device *rdev) -{ - return fmap_locate_area_as_rdev(name, rdev); -} - -int vboot_named_region_device_rw(const char *name, struct region_device *rdev) -{ - return fmap_locate_area_as_rdev_rw(name, rdev); -} - /* Check if it is okay to enable USB Device Controller (UDC). */ int vboot_can_enable_udc(void) { diff --git a/src/security/vboot/vboot_common.h b/src/security/vboot/vboot_common.h index 42b4a6b59b..a20ab62bd4 100644 --- a/src/security/vboot/vboot_common.h +++ b/src/security/vboot/vboot_common.h @@ -20,12 +20,6 @@ #include #include -/* Locate vboot area by name. Returns 0 on success and -1 on error. */ -int vboot_named_region_device(const char *name, struct region_device *rdev); - -/* Like vboot_named_region_device() but provides a RW region device. */ -int vboot_named_region_device_rw(const char *name, struct region_device *rdev); - /* * Function to check if there is a request to enter recovery mode. Returns * reason code if request to enter recovery mode is present, otherwise 0. diff --git a/src/security/vboot/vboot_logic.c b/src/security/vboot/vboot_logic.c index 5facd283ee..71371cdb75 100644 --- a/src/security/vboot/vboot_logic.c +++ b/src/security/vboot/vboot_logic.c @@ -19,6 +19,7 @@ #include #include #include +#include #include #include #include @@ -78,7 +79,7 @@ vb2_error_t vb2ex_read_resource(struct vb2_context *ctx, return VB2_ERROR_EX_READ_RESOURCE_INDEX; } - if (vboot_named_region_device(name, &rdev)) + if (fmap_locate_area_as_rdev(name, &rdev)) return VB2_ERROR_EX_READ_RESOURCE_SIZE; if (rdev_readat(&rdev, buf, offset, size) != size) @@ -265,7 +266,7 @@ static int locate_firmware(struct vb2_context *ctx, else name = "FW_MAIN_B"; - return vboot_named_region_device(name, fw_main); + return fmap_locate_area_as_rdev(name, fw_main); } /** From 5027ecfb1987cf06efc772a0bee0a1fe1dc38049 Mon Sep 17 00:00:00 2001 From: Julius Werner Date: Wed, 30 Oct 2019 16:08:40 -0700 Subject: [PATCH 0259/1242] Remove google/urara mainboard This board never really existed and nobody has any hardware left over for it. Change-Id: Icdba4f5209725995e4a55dcdbc299a9e91a5869a Signed-off-by: Julius Werner Reviewed-on: https://review.coreboot.org/c/coreboot/+/36490 Tested-by: build bot (Jenkins) Reviewed-by: Arthur Heymans --- src/mainboard/google/urara/Kconfig | 55 ----- src/mainboard/google/urara/Kconfig.name | 2 - src/mainboard/google/urara/Makefile.inc | 25 --- src/mainboard/google/urara/board_info.txt | 5 - src/mainboard/google/urara/boardid.c | 98 -------- src/mainboard/google/urara/bootblock.c | 248 --------------------- src/mainboard/google/urara/chromeos.c | 36 --- src/mainboard/google/urara/chromeos.fmd | 32 --- src/mainboard/google/urara/devicetree.cb | 22 -- src/mainboard/google/urara/mainboard.c | 55 ----- src/mainboard/google/urara/memlayout.ld | 16 -- src/mainboard/google/urara/urara_boardid.h | 38 ---- 12 files changed, 632 deletions(-) delete mode 100644 src/mainboard/google/urara/Kconfig delete mode 100644 src/mainboard/google/urara/Kconfig.name delete mode 100644 src/mainboard/google/urara/Makefile.inc delete mode 100644 src/mainboard/google/urara/board_info.txt delete mode 100644 src/mainboard/google/urara/boardid.c delete mode 100644 src/mainboard/google/urara/bootblock.c delete mode 100644 src/mainboard/google/urara/chromeos.c delete mode 100644 src/mainboard/google/urara/chromeos.fmd delete mode 100644 src/mainboard/google/urara/devicetree.cb delete mode 100644 src/mainboard/google/urara/mainboard.c delete mode 100644 src/mainboard/google/urara/memlayout.ld delete mode 100644 src/mainboard/google/urara/urara_boardid.h diff --git a/src/mainboard/google/urara/Kconfig b/src/mainboard/google/urara/Kconfig deleted file mode 100644 index 3cbe7ed5f9..0000000000 --- a/src/mainboard/google/urara/Kconfig +++ /dev/null @@ -1,55 +0,0 @@ -# -# This file is part of the coreboot project. -# -# Copyright (C) 2014 Imagination Technologies -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; version 2 of -# the License. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# - -if BOARD_GOOGLE_URARA - -config BOARD_SPECIFIC_OPTIONS - def_bool y - select BOARD_ROMSIZE_KB_512 - select SPI_FLASH_WINBOND - select CPU_IMGTEC_PISTACHIO - select COMMON_CBFS_SPI_WRAPPER - select SPI_FLASH - -config MAINBOARD_DIR - string - default "google/urara" - -config MAINBOARD_PART_NUMBER - string - default "ImgTec Pistachio Virtual Platform" - -config BOOTBLOCK_MAINBOARD_INIT - string - default "mainboard/google/urara/bootblock.c" - -config DRAM_SIZE_MB - int - default 256 - -config TTYS0_LCS - int - default 3 - -config CONSOLE_SERIAL_UART_ADDRESS - hex - depends on DRIVERS_UART - default 0xB8101500 - -config BOOT_DEVICE_SPI_FLASH_BUS - int - default 1 -endif diff --git a/src/mainboard/google/urara/Kconfig.name b/src/mainboard/google/urara/Kconfig.name deleted file mode 100644 index edc935ad6f..0000000000 --- a/src/mainboard/google/urara/Kconfig.name +++ /dev/null @@ -1,2 +0,0 @@ -config BOARD_GOOGLE_URARA - bool "Urara" diff --git a/src/mainboard/google/urara/Makefile.inc b/src/mainboard/google/urara/Makefile.inc deleted file mode 100644 index 7ad779d350..0000000000 --- a/src/mainboard/google/urara/Makefile.inc +++ /dev/null @@ -1,25 +0,0 @@ -# -# This file is part of the coreboot project. -# -# Copyright 2014 Imagination Technologies Ltd. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; version 2 of -# the License. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# - -bootblock-y += boardid.c -ramstage-y += boardid.c -romstage-$(CONFIG_CHROMEOS) += chromeos.c -ramstage-$(CONFIG_CHROMEOS) += chromeos.c -ramstage-y += mainboard.c - -bootblock-y += memlayout.ld -romstage-y += memlayout.ld -ramstage-y += memlayout.ld diff --git a/src/mainboard/google/urara/board_info.txt b/src/mainboard/google/urara/board_info.txt deleted file mode 100644 index 0458abdaca..0000000000 --- a/src/mainboard/google/urara/board_info.txt +++ /dev/null @@ -1,5 +0,0 @@ -Vendor name: Google -Board name: Urara Imgtec Pistachio reference board -Category: eval -ROM protocol: SPI -ROM socketed: n diff --git a/src/mainboard/google/urara/boardid.c b/src/mainboard/google/urara/boardid.c deleted file mode 100644 index 9a6b64eb78..0000000000 --- a/src/mainboard/google/urara/boardid.c +++ /dev/null @@ -1,98 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2014 Imagination Technologies - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include - -#include -#include -#include - -#include "mainboard/google/urara/urara_boardid.h" - -/* Name of the CBFS file were the board ID string is read from. */ -#define CBFS_BOARD_ID_FILE_NAME "board_id" - -const struct bid_map { - const char *board_name; - uint8_t board_id; - struct board_hw hardware; -} board_id_map[] = { - {"urara", URARA_BOARD_ID_BUB, {0} }, - {"buranku", URARA_BOARD_ID_BURANKU, {3} }, - {"derwent", URARA_BOARD_ID_DERWENT, {3} }, - {"jaguar", URARA_BOARD_ID_JAGUAR, {3} }, - {"kennet", URARA_BOARD_ID_KENNET, {3} }, - {"space", URARA_BOARD_ID_SPACE, {3} }, -}; - -static int cached_board_id = -1; - -static uint8_t retrieve_board_id(void) -{ - const char *board_id_file_name = CBFS_BOARD_ID_FILE_NAME; - char *file_contents; - int i; - size_t length; - - file_contents = cbfs_boot_map_with_leak(board_id_file_name, - CBFS_TYPE_RAW, &length); - - if (!file_contents) { - printk(BIOS_WARNING, - "board_id: failed to locate file '%s'\n", - board_id_file_name); - return 0; - } - - for (i = 0; i < ARRAY_SIZE(board_id_map); i++) { - const struct bid_map *entry = board_id_map + i; - - if ((strlen(entry->board_name) == length) && - !strncmp(entry->board_name, file_contents, length)) { - printk(BIOS_INFO, "board_id: name '%s', ID %d\n", - entry->board_name, entry->board_id); - return entry->board_id; - } - } - - printk(BIOS_WARNING, "board_id: no match for board name '%.*s'\n", - length, file_contents); - printk(BIOS_WARNING, "board_id: will use default board ID 0\n"); - - return 0; -} - -const struct board_hw *board_get_hw(void) -{ - int i; - uint8_t bid = board_id(); - - for (i = 0; i < ARRAY_SIZE(board_id_map); i++) { - if (bid == board_id_map[i].board_id) - return &(board_id_map[i].hardware); - } - - return 0; -} - -uint32_t board_id(void) -{ - if (cached_board_id == -1) - cached_board_id = retrieve_board_id(); - - return cached_board_id; -} diff --git a/src/mainboard/google/urara/bootblock.c b/src/mainboard/google/urara/bootblock.c deleted file mode 100644 index 16e75809d3..0000000000 --- a/src/mainboard/google/urara/bootblock.c +++ /dev/null @@ -1,248 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2014 Imagination Technologies - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include -#include -#include -#include - -#include "urara_boardid.h" - -#define PADS_FUNCTION_SELECT0_ADDR (0xB8101C00 + 0xC0) - -#define GPIO_BIT_EN_ADDR(bank) (0xB8101C00 + 0x200 + (0x24 * (bank))) -#define PAD_DRIVE_STRENGTH_ADDR(bank) (0xB8101C00 + 0x120 + (0x4 * (bank))) -#define MAX_NO_MFIOS 89 -#define PAD_DRIVE_STRENGTH_LENGTH 2 -#define PAD_DRIVE_STRENGTH_MASK 0x3 - -typedef enum { - DRIVE_STRENGTH_2mA = 0, - DRIVE_STRENGTH_4mA = 1, - DRIVE_STRENGTH_8mA = 2, - DRIVE_STRENGTH_12mA = 3 -} drive_strength; - -/* MFIO definitions for UART1 */ -#define UART1_RXD_MFIO 59 -#define UART1_TXD_MFIO 60 - -/* MFIO definitions for SPIM */ -#define SPIM1_D0_TXD_MFIO 5 -#define SPIM1_D1_RXD_MFIO 4 -#define SPIM1_MCLK_MFIO 3 -#define SPIM1_D2_MFIO 6 -#define SPIM1_D3_MFIO 7 -#define SPIM1_CS0_MFIO 0 - -/* MFIO definitions for I2C */ -#define I2C_DATA_MFIO(i) (28 + (2*(i))) -#define I2C_CLK_MFIO(i) (29 + (2*(i))) -#define I2C_DATA_FUNCTION_OFFSET(i) (20 + (2*(i))) -#define I2C_CLK_FUNCTION_OFFSET(i) (21 + (2*(i))) -#define I2C_DATA_FUNCTION_MASK 0x1 -#define I2C_CLK_FUNCTION_MASK 0x1 - -static void pad_drive_strength(u32 pad, drive_strength strength) -{ - u32 reg, drive_strength_shift; - - assert(pad <= MAX_NO_MFIOS); - assert(!(strength & ~(PAD_DRIVE_STRENGTH_MASK))); - - /* Set drive strength value */ - drive_strength_shift = (pad % 16) * PAD_DRIVE_STRENGTH_LENGTH; - reg = read32_x(PAD_DRIVE_STRENGTH_ADDR(pad / 16)); - reg &= ~(PAD_DRIVE_STRENGTH_MASK << drive_strength_shift); - reg |= strength << drive_strength_shift; - write32_x(PAD_DRIVE_STRENGTH_ADDR(pad / 16), reg); -} - -static void uart1_mfio_setup(void) -{ - u32 reg, mfio_mask; - - /* - * Disable GPIO for UART1 MFIOs - * All UART MFIOs have MFIO/16 = 3, therefore we use GPIO pad 3 - * This is the only function (0) of these MFIOs and therfore there - * is no need to set up a function number in the corresponding - * function select register. - */ - reg = read32_x(GPIO_BIT_EN_ADDR(3)); - mfio_mask = 1 << (UART1_RXD_MFIO % 16); - mfio_mask |= 1 << (UART1_TXD_MFIO % 16); - /* Clear relevant bits */ - reg &= ~mfio_mask; - /* - * Set corresponding bits in the upper half word - * in order to be able to modify the chosen pins - */ - reg |= mfio_mask << 16; - write32_x(GPIO_BIT_EN_ADDR(3), reg); -} - -static void spim1_mfio_setup(void) -{ - u32 reg, mfio_mask; - /* - * Disable GPIO for SPIM1 MFIOs - * All SPFI1 MFIOs have MFIO/16 = 0, therefore we use GPIO pad 0 - * This is the only function (0) of these MFIOs and therfore there - * is no need to set up a function number in the corresponding - * function select register. - */ - reg = read32_x(GPIO_BIT_EN_ADDR(0)); - - /* Disable GPIO for SPIM1 MFIOs */ - mfio_mask = 1 << (SPIM1_D0_TXD_MFIO % 16); - mfio_mask |= 1 << (SPIM1_D1_RXD_MFIO % 16); - mfio_mask |= 1 << (SPIM1_MCLK_MFIO % 16); - mfio_mask |= 1 << (SPIM1_D2_MFIO % 16); - mfio_mask |= 1 << (SPIM1_D3_MFIO % 16); - mfio_mask |= 1 << (SPIM1_CS0_MFIO % 16); - - /* Clear relevant bits */ - reg &= ~mfio_mask; - /* - * Set corresponding bits in the upper half word - * in order to be able to modify the chosen pins - */ - reg |= mfio_mask << 16; - write32_x(GPIO_BIT_EN_ADDR(0), reg); - - /* Set drive strength to maximum for these MFIOs */ - pad_drive_strength(SPIM1_CS0_MFIO, DRIVE_STRENGTH_12mA); - pad_drive_strength(SPIM1_D1_RXD_MFIO, DRIVE_STRENGTH_12mA); - pad_drive_strength(SPIM1_D0_TXD_MFIO, DRIVE_STRENGTH_12mA); - pad_drive_strength(SPIM1_D2_MFIO, DRIVE_STRENGTH_12mA); - pad_drive_strength(SPIM1_D3_MFIO, DRIVE_STRENGTH_12mA); - pad_drive_strength(SPIM1_MCLK_MFIO, DRIVE_STRENGTH_12mA); -} - -static void i2c_mfio_setup(int interface) -{ - u32 reg, mfio_mask; - - assert(interface < 4); - /* - * Disable GPIO for I2C MFIOs - */ - reg = read32_x(GPIO_BIT_EN_ADDR(I2C_DATA_MFIO(interface) / 16)); - mfio_mask = 1 << (I2C_DATA_MFIO(interface) % 16); - mfio_mask |= 1 << (I2C_CLK_MFIO(interface) % 16); - /* Clear relevant bits */ - reg &= ~mfio_mask; - /* - * Set corresponding bits in the upper half word - * in order to be able to modify the chosen pins - */ - reg |= mfio_mask << 16; - write32_x(GPIO_BIT_EN_ADDR(I2C_DATA_MFIO(interface) / 16), reg); - - /* for I2C0 and I2C1: - * Set bits to 0 (clear) which is the primary function - * for these MFIOs; those bits will all be set to 1 by - * default. - * There is no need to do that for I2C2 and I2C3 - */ - if (interface > 1) - return; - reg = read32_x(PADS_FUNCTION_SELECT0_ADDR); - reg &= ~(I2C_DATA_FUNCTION_MASK << - I2C_DATA_FUNCTION_OFFSET(interface)); - reg &= ~(I2C_CLK_FUNCTION_MASK << - I2C_CLK_FUNCTION_OFFSET(interface)); - write32_x(PADS_FUNCTION_SELECT0_ADDR, reg); -} - -static void bootblock_mainboard_init(void) -{ - int ret; - - /* System PLL divided by 2 -> 350 MHz */ - /* The same frequency will be the input frequency for the SPFI block */ - system_clk_setup(1); - - /* MIPS CPU dividers: division by 1 -> 546 MHz - * This is set up as we cannot make any assumption about - * the values set or not by the boot ROM code */ - mips_clk_setup(0, 0); - - /* Setup system PLL at 700 MHz */ - ret = sys_pll_setup(2, 1, 13, 350); - if (ret != CLOCKS_OK) - return; - /* Setup MIPS PLL at 546 MHz */ - ret = mips_pll_setup(2, 1, 1, 21); - if (ret != CLOCKS_OK) - return; - - /* - * Move peripheral clock control from RPU to MIPS. - * The RPU gate register is not managed in Linux so disable its default - * values and assign MIPS gate register the default values. - * *Note*: All unused clocks will be gated by Linux - */ - setup_clk_gate_defaults(); - - /* Setup SPIM1 MFIOs */ - spim1_mfio_setup(); - /* Setup UART1 clock and MFIOs - * System PLL divided by 5 divided by 76 -> 1.8421 Mhz - */ - uart1_clk_setup(4, 75); - uart1_mfio_setup(); -} - - -static int init_extra_hardware(void) -{ - const struct board_hw *hardware; - - /* Obtain information about current board */ - hardware = board_get_hw(); - if (!hardware) { - printk(BIOS_ERR, "%s: Invalid hardware information.\n", - __func__); - return -1; - } - - /* Setup USB clock - * System clock divided by 7 -> 50 MHz - */ - if (usb_clk_setup(6, 2, 7) != CLOCKS_OK) { - printk(BIOS_ERR, "%s: Failed to set up USB clock.\n", - __func__); - return -1; - } - - /* Setup I2C clocks and MFIOs - * System clock divided by 4 divided by 3 -> 29.1(6) MHz - */ - i2c_clk_setup(3, 2, hardware->i2c_interface); - i2c_mfio_setup(hardware->i2c_interface); - - /* Ethernet clocks setup: ENET as clock source */ - eth_clk_setup(0, 6); - /* ROM clock setup: system clock divided by 2 -> 175 MHz */ - /* Hash accelerator is driven from the ROM clock */ - rom_clk_setup(1); - - return 0; -} diff --git a/src/mainboard/google/urara/chromeos.c b/src/mainboard/google/urara/chromeos.c deleted file mode 100644 index 3f7ec32864..0000000000 --- a/src/mainboard/google/urara/chromeos.c +++ /dev/null @@ -1,36 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright 2014 Google Technologies - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include -#include - -int get_write_protect_state(void) -{ - printk(BIOS_ERR, "%s unsupported, but called\n", __func__); - return 0; -} - -void fill_lb_gpios(struct lb_gpios *gpios) -{ - printk(BIOS_ERR, "%s unsupported, but called\n", __func__); -} - -int get_recovery_mode_switch(void) -{ - printk(BIOS_ERR, "%s unsupported, but called\n", __func__); - return 0; -} diff --git a/src/mainboard/google/urara/chromeos.fmd b/src/mainboard/google/urara/chromeos.fmd deleted file mode 100644 index 4bc0db4dc6..0000000000 --- a/src/mainboard/google/urara/chromeos.fmd +++ /dev/null @@ -1,32 +0,0 @@ -FLASH@0x0 0x200000 { - WP_RO@0x0 0x100000 { - RO_SECTION@0x0 0xf0000 { - BOOTBLOCK@0 128K - COREBOOT(CBFS)@0x20000 0x60000 - FMAP@0xe0000 0x1000 - GBB@0xe1000 0xef00 - RO_FRID@0xeff00 0x100 - } - RO_VPD(PRESERVE)@0xf0000 0x10000 - } - RW_SECTION_A@0x100000 0x70000 { - VBLOCK_A@0x0 0x2000 - FW_MAIN_A(CBFS)@0x2000 0x6df00 - RW_FWID_A@0x6ff00 0x100 - } - RW_SHARED@0x170000 0x2000 { - SHARED_DATA@0x0 0x2000 - } - RW_GPT@0x172000 0x2000 { - RW_GPT_PRIMARY@0x0 0x1000 - RW_GPT_SECONDARY@0x1000 0x1000 - } - RW_ELOG(PRESERVE)@0x174000 0x4000 - RW_VPD(PRESERVE)@0x178000 0x8000 - RW_SECTION_B@0x180000 0x70000 { - VBLOCK_B@0x0 0x2000 - FW_MAIN_B(CBFS)@0x2000 0x6df00 - RW_FWID_B@0x6ff00 0x100 - } - RW_NVRAM(PRESERVE)@0x1f0000 0x10000 -} diff --git a/src/mainboard/google/urara/devicetree.cb b/src/mainboard/google/urara/devicetree.cb deleted file mode 100644 index d865add4c9..0000000000 --- a/src/mainboard/google/urara/devicetree.cb +++ /dev/null @@ -1,22 +0,0 @@ -# -# This file is part of the coreboot project. -# -# Copyright (C) 2014 Imagination Technologies -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; version 2 of -# the License. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# - -chip soc/imgtec/pistachio - device cpu_cluster 0 on end - chip drivers/generic/generic # I2C0 controller - device i2c 6 on end # Fake component for testing - end -end diff --git a/src/mainboard/google/urara/mainboard.c b/src/mainboard/google/urara/mainboard.c deleted file mode 100644 index 7bf8b908a3..0000000000 --- a/src/mainboard/google/urara/mainboard.c +++ /dev/null @@ -1,55 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2014 Imagination Technologies - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ -#include -#include -#include -#include - -#include - -static void mainboard_init(struct device *dev) -{ -#if CONFIG(CHROMEOS) - /* Copy WIFI calibration data into CBMEM. */ - cbmem_add_vpd_calibration_data(); -#endif -} - -static void mainboard_enable(struct device *dev) -{ - printk(BIOS_INFO, "Enable Pistachio device...\n"); - dev->ops->init = &mainboard_init; -} - -struct chip_operations mainboard_ops = { - .enable_dev = mainboard_enable, -}; - -void lb_board(struct lb_header *header) -{ - struct lb_range *dma; - - dma = (struct lb_range *)lb_new_record(header); - dma->tag = LB_TAG_DMA; - dma->size = sizeof(*dma); - dma->range_start = (uintptr_t)_dma_coherent; - dma->range_size = REGION_SIZE(dma_coherent); - -#if CONFIG(CHROMEOS) - /* Retrieve the switch interface MAC addresses. */ - lb_table_add_macs_from_vpd(header); -#endif -} diff --git a/src/mainboard/google/urara/memlayout.ld b/src/mainboard/google/urara/memlayout.ld deleted file mode 100644 index 14703291b1..0000000000 --- a/src/mainboard/google/urara/memlayout.ld +++ /dev/null @@ -1,16 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (c) 2012 - 2013 The Linux Foundation. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include diff --git a/src/mainboard/google/urara/urara_boardid.h b/src/mainboard/google/urara/urara_boardid.h deleted file mode 100644 index fbd9179a8a..0000000000 --- a/src/mainboard/google/urara/urara_boardid.h +++ /dev/null @@ -1,38 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2015 Google, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef __MAINBOARD_GOOGLE_URARA_URARA_BOARDID_H__ -#define __MAINBOARD_GOOGLE_URARA_URARA_BOARDID_H__ - -#include - -/* - * List of URARA derivatives board ID definitions. They are stored in uint8_t - * across the code, using #defines here not to imply any specific size. - */ -#define URARA_BOARD_ID_BUB 0 -#define URARA_BOARD_ID_BURANKU 1 -#define URARA_BOARD_ID_DERWENT 2 -#define URARA_BOARD_ID_JAGUAR 3 -#define URARA_BOARD_ID_KENNET 4 -#define URARA_BOARD_ID_SPACE 5 - -struct board_hw { - uint8_t i2c_interface; -}; - -const struct board_hw *board_get_hw(void); - -#endif From 63c444a69b98bc8a86719699423b3273cc5759e8 Mon Sep 17 00:00:00 2001 From: Julius Werner Date: Wed, 30 Oct 2019 16:12:24 -0700 Subject: [PATCH 0260/1242] Remove imgtec/pistachio SoC After removing urara no board still uses this SoC, and there are no plans to add any in the future (I'm not sure if the chip really exists tbh...). Change-Id: Ic4628fdfacc9fb19b6210394d96431fdb5f8e8f1 Signed-off-by: Julius Werner Reviewed-on: https://review.coreboot.org/c/coreboot/+/36491 Reviewed-by: Arthur Heymans Tested-by: build bot (Jenkins) --- .gitignore | 1 - Documentation/util.md | 3 - Makefile.inc | 7 +- payloads/libpayload/drivers/Makefile.inc | 1 - payloads/libpayload/drivers/timer/Kconfig | 3 - src/soc/imgtec/Kconfig | 2 - src/soc/imgtec/pistachio/Kconfig | 34 - src/soc/imgtec/pistachio/Makefile.inc | 48 -- src/soc/imgtec/pistachio/bootblock.c | 62 -- src/soc/imgtec/pistachio/cbmem.c | 24 - src/soc/imgtec/pistachio/clocks.c | 513 --------------- src/soc/imgtec/pistachio/ddr2_init.c | 443 ------------- src/soc/imgtec/pistachio/ddr3_init.c | 514 --------------- src/soc/imgtec/pistachio/include/soc/clocks.h | 43 -- src/soc/imgtec/pistachio/include/soc/cpu.h | 35 -- .../imgtec/pistachio/include/soc/ddr_init.h | 26 - .../pistachio/include/soc/ddr_private_reg.h | 142 ----- src/soc/imgtec/pistachio/include/soc/gpio.h | 21 - .../imgtec/pistachio/include/soc/memlayout.ld | 70 --- src/soc/imgtec/pistachio/include/soc/spi.h | 357 ----------- src/soc/imgtec/pistachio/monotonic_timer.c | 53 -- src/soc/imgtec/pistachio/reset.c | 26 - src/soc/imgtec/pistachio/romstage.c | 39 -- src/soc/imgtec/pistachio/soc.c | 44 -- src/soc/imgtec/pistachio/spi.c | 587 ------------------ src/soc/imgtec/pistachio/uart.c | 158 ----- util/bimgtool/Makefile | 16 - util/bimgtool/bimgtool.c | 430 ------------- util/bimgtool/description.md | 3 - 29 files changed, 1 insertion(+), 3704 deletions(-) delete mode 100644 src/soc/imgtec/Kconfig delete mode 100644 src/soc/imgtec/pistachio/Kconfig delete mode 100644 src/soc/imgtec/pistachio/Makefile.inc delete mode 100644 src/soc/imgtec/pistachio/bootblock.c delete mode 100644 src/soc/imgtec/pistachio/cbmem.c delete mode 100644 src/soc/imgtec/pistachio/clocks.c delete mode 100644 src/soc/imgtec/pistachio/ddr2_init.c delete mode 100644 src/soc/imgtec/pistachio/ddr3_init.c delete mode 100644 src/soc/imgtec/pistachio/include/soc/clocks.h delete mode 100644 src/soc/imgtec/pistachio/include/soc/cpu.h delete mode 100644 src/soc/imgtec/pistachio/include/soc/ddr_init.h delete mode 100644 src/soc/imgtec/pistachio/include/soc/ddr_private_reg.h delete mode 100644 src/soc/imgtec/pistachio/include/soc/gpio.h delete mode 100644 src/soc/imgtec/pistachio/include/soc/memlayout.ld delete mode 100644 src/soc/imgtec/pistachio/include/soc/spi.h delete mode 100644 src/soc/imgtec/pistachio/monotonic_timer.c delete mode 100644 src/soc/imgtec/pistachio/reset.c delete mode 100644 src/soc/imgtec/pistachio/romstage.c delete mode 100644 src/soc/imgtec/pistachio/soc.c delete mode 100644 src/soc/imgtec/pistachio/spi.c delete mode 100644 src/soc/imgtec/pistachio/uart.c delete mode 100644 util/bimgtool/Makefile delete mode 100644 util/bimgtool/bimgtool.c delete mode 100644 util/bimgtool/description.md diff --git a/.gitignore b/.gitignore index b90a93fa1d..84b3af10e2 100644 --- a/.gitignore +++ b/.gitignore @@ -85,7 +85,6 @@ util/*/.dependencies util/*/.test util/amdfwtool/amdfwtool util/archive/archive -util/bimgtool/bimgtool util/bincfg/bincfg util/board_status/board-status util/bucts/bucts diff --git a/Documentation/util.md b/Documentation/util.md index 021af791c7..1a8f36db2b 100644 --- a/Documentation/util.md +++ b/Documentation/util.md @@ -14,9 +14,6 @@ settings. `Perl` platform. `C` * __autoport__ - Automated porting coreboot to Sandy Bridge/Ivy Bridge platforms `Go` -* __bimgtool__ - A simple tool which generates and verifies boot images -in the BIMG format, used in systems designed by Imagination -Technologies, for example the Pistachio SoC. `C` * __bincfg__ - Compiler/Decompiler for data blobs with specs `Lex` `Yacc` * __board_status__ - Tools to collect logs and upload them to the board diff --git a/Makefile.inc b/Makefile.inc index 66144cd2ac..fdbbdee21a 100644 --- a/Makefile.inc +++ b/Makefile.inc @@ -488,7 +488,7 @@ endif additional-dirs := $(objutil)/cbfstool $(objutil)/romcc $(objutil)/ifdtool \ $(objutil)/options $(objutil)/amdfwtool \ - $(objutil)/cbootimage $(objutil)/bimgtool + $(objutil)/cbootimage export $(COREBOOT_EXPORTS) @@ -581,11 +581,6 @@ FUTILITY?=$(objutil)/futility/futility subdirs-y += util/nvidia -BIMGTOOL:=$(objutil)/bimgtool/bimgtool -$(BIMGTOOL): $(top)/util/bimgtool/bimgtool.c - @printf " HOSTCC $(subst $(obj)/,,$(@))\n" - $(HOSTCC) $(HOSTCFLAGS) -o $@ $< - $(obj)/config.h: $(objutil)/kconfig/conf ####################################################################### diff --git a/payloads/libpayload/drivers/Makefile.inc b/payloads/libpayload/drivers/Makefile.inc index b4e75943f3..a3916700df 100644 --- a/payloads/libpayload/drivers/Makefile.inc +++ b/payloads/libpayload/drivers/Makefile.inc @@ -54,7 +54,6 @@ ifneq ($(CONFIG_LP_TIMER_GENERIC_HZ),0) libc-y += timer/generic.c endif libc-$(CONFIG_LP_TIMER_RDTSC) += timer/rdtsc.c -libc-$(CONFIG_LP_TIMER_IMG_PISTACHIO) += timer/img_pistachio.c libc-$(CONFIG_LP_TIMER_ARM64_ARCH) += timer/arm64_arch_timer.c # Video console drivers diff --git a/payloads/libpayload/drivers/timer/Kconfig b/payloads/libpayload/drivers/timer/Kconfig index 5a61dfab51..e3bd0e96b7 100644 --- a/payloads/libpayload/drivers/timer/Kconfig +++ b/payloads/libpayload/drivers/timer/Kconfig @@ -50,9 +50,6 @@ config TIMER_RK3288 config TIMER_RK3399 bool "Timer for Rockchip RK3399" -config TIMER_IMG_PISTACHIO - bool "Timer for IMG Pistachio" - config TIMER_MTK bool "Timer for MediaTek" diff --git a/src/soc/imgtec/Kconfig b/src/soc/imgtec/Kconfig deleted file mode 100644 index 18c6ba1dfd..0000000000 --- a/src/soc/imgtec/Kconfig +++ /dev/null @@ -1,2 +0,0 @@ -# Load all chipsets -source "src/soc/imgtec/*/Kconfig" diff --git a/src/soc/imgtec/pistachio/Kconfig b/src/soc/imgtec/pistachio/Kconfig deleted file mode 100644 index 30d7bee2c0..0000000000 --- a/src/soc/imgtec/pistachio/Kconfig +++ /dev/null @@ -1,34 +0,0 @@ -# -# This file is part of the coreboot project. -# -# Copyright (C) 2014 Imagination Technologies -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; version 2 of -# the License. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# - -config CPU_IMGTEC_PISTACHIO - select ARCH_MIPS - select ARCH_BOOTBLOCK_MIPS - select ARCH_VERSTAGE_MIPS - select ARCH_ROMSTAGE_MIPS - select ARCH_RAMSTAGE_MIPS - select HAVE_UART_SPECIAL - select GENERIC_GPIO_LIB - select UART_OVERRIDE_REFCLK - bool - -if CPU_IMGTEC_PISTACHIO - -config BOOTBLOCK_CPU_INIT - string - default "soc/imgtec/pistachio/bootblock.c" - -endif diff --git a/src/soc/imgtec/pistachio/Makefile.inc b/src/soc/imgtec/pistachio/Makefile.inc deleted file mode 100644 index 9392d302a2..0000000000 --- a/src/soc/imgtec/pistachio/Makefile.inc +++ /dev/null @@ -1,48 +0,0 @@ -# -# This file is part of the coreboot project. -# -# Copyright (C) 2014 Imagination Technologies -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; version 2 of -# the License. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# - -ifeq ($(CONFIG_CPU_IMGTEC_PISTACHIO),y) - -# We enable CBFS_SPI_WRAPPER for Pistachio targets. -bootblock-y += clocks.c -bootblock-y += spi.c -romstage-y += spi.c -ramstage-y += spi.c - -bootblock-y += uart.c -romstage-y += uart.c -ramstage-y += uart.c - -bootblock-y += monotonic_timer.c - -ramstage-y += monotonic_timer.c -ramstage-y += soc.c -ramstage-y += reset.c - -romstage-y += cbmem.c -romstage-y += ddr2_init.c -romstage-y += ddr3_init.c -romstage-y += romstage.c -romstage-y += monotonic_timer.c - -CPPFLAGS_common += -Isrc/soc/imgtec/pistachio/include/ - -# Create a complete bootblock which will start up the system -$(objcbfs)/bootblock.bin: $(objcbfs)/bootblock.raw.bin $(BIMGTOOL) - @printf " BIMGTOOL $(subst $(obj)/,,$(@))\n" - $(BIMGTOOL) $< $@ $(call loadaddr,bootblock) - -endif diff --git a/src/soc/imgtec/pistachio/bootblock.c b/src/soc/imgtec/pistachio/bootblock.c deleted file mode 100644 index ac4a74070c..0000000000 --- a/src/soc/imgtec/pistachio/bootblock.c +++ /dev/null @@ -1,62 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2014 Imagination Technologies - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include -#include -#include - -static void bootblock_cpu_init(void) -{ - uint32_t cause; - - /* - * Make sure the count register is counting by clearing the "Disable - * Counter" bit, in case it is set. - */ - cause = read_c0_cause(); - if (cause & C0_CAUSE_DC) - write_c0_cause(cause & ~(C0_CAUSE_DC)); - - /* And make sure that it starts from zero. */ - write_c0_count(0); -} - -static void bootblock_mmu_init(void) -{ - uint32_t null_guard_size = 1 * MiB; - uint32_t dram_base, dram_size; - - write_c0_wired(0); - - dram_base = (uint32_t)_dram; - dram_size = CONFIG_DRAM_SIZE_MB * MiB; - - /* - * To be able to catch NULL pointer dereference attempts, lets not map - * memory close to zero. - */ - if (dram_base < null_guard_size) { - dram_base += null_guard_size; - dram_size -= null_guard_size; - } - assert(!identity_map((uint32_t)_sram, REGION_SIZE(sram), - C0_ENTRYLO_COHERENCY_WB)); - assert(!identity_map(dram_base, dram_size, C0_ENTRYLO_COHERENCY_WB)); - assert(!identity_map((uint32_t)_soc_registers, - REGION_SIZE(soc_registers), C0_ENTRYLO_COHERENCY_UC)); -} diff --git a/src/soc/imgtec/pistachio/cbmem.c b/src/soc/imgtec/pistachio/cbmem.c deleted file mode 100644 index 92bc1ce868..0000000000 --- a/src/soc/imgtec/pistachio/cbmem.c +++ /dev/null @@ -1,24 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2014 Imagination Technologies - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include - -void *cbmem_top_chipset(void) -{ - return _dram + (CONFIG_DRAM_SIZE_MB << 20); -} diff --git a/src/soc/imgtec/pistachio/clocks.c b/src/soc/imgtec/pistachio/clocks.c deleted file mode 100644 index aa54ebc43e..0000000000 --- a/src/soc/imgtec/pistachio/clocks.c +++ /dev/null @@ -1,513 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2014 Imagination Technologies - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include -#include -#include - -/* Definitions for PLL enable */ -#define PISTACHIO_CLOCK_SWITCH 0xB8144200 - -#define SYS_EXTERN_PLL_BYPASS_MASK 0x00002000 -#define SYS_PLL_CTRL4_ADDR 0xB8144048 -#define SYS_INTERNAL_PLL_BYPASS_MASK 0x10000000 -#define SYS_PLL_PD_CTRL_ADDR 0xB8144044 -#define SYS_PLL_PD_CTRL_PD_MASK 0x00000039 -#define SYS_PLL_DACPD_ADDR 0xB8144044 -#define SYS_PLL_DACPD_MASK 0x00000002 -#define SYS_PLL_DSMPD_ADDR 0xB8144044 -#define SYS_PLL_DSMPD_MASK 0x00000004 - -#define MIPS_EXTERN_PLL_BYPASS_MASK 0x00000002 -#define MIPS_PLL_CTRL2_ADDR 0xB8144008 -#define MIPS_INTERNAL_PLL_BYPASS_MASK 0x10000000 -#define MIPS_PLL_PD_CTRL_ADDR 0xB8144004 -#define MIPS_PLL_PD_CTRL_PD_MASK 0x0D000000 -#define MIPS_PLL_DSMPD_ADDR 0xB8144004 -#define MIPS_PLL_DSMPD_MASK 0x02000000 - -/* Definitions for PLL dividers */ -#define SYS_PLL_POSTDIV_ADDR 0xB8144040 -#define SYS_PLL_POSTDIV1_MASK 0x07000000 -#define SYS_PLL_POSTDIV1_SHIFT 24 -#define SYS_PLL_POSTDIV2_MASK 0x38000000 -#define SYS_PLL_POSTDIV2_SHIFT 27 -#define SYS_PLL_STATUS_ADDR 0xB8144038 -#define SYS_PLL_STATUS_LOCK_MASK 0x00000001 - -#define SYS_PLL_REFDIV_ADDR 0xB814403C -#define SYS_PLL_REFDIV_MASK 0x0000003F -#define SYS_PLL_REFDIV_SHIFT 0 -#define SYS_PLL_FEEDBACK_ADDR 0xB814403C -#define SYS_PLL_FEEDBACK_MASK 0x0003FFC0 -#define SYS_PLL_FEEDBACK_SHIFT 6 - -#define MIPS_PLL_POSTDIV_ADDR 0xB8144004 -#define MIPS_PLL_POSTDIV1_MASK 0x001C0000 -#define MIPS_PLL_POSTDIV1_SHIFT 18 -#define MIPS_PLL_POSTDIV2_MASK 0x00E00000 -#define MIPS_PLL_POSTDIV2_SHIFT 21 -#define MIPS_PLL_STATUS_ADDR 0xB8144000 -#define MIPS_PLL_STATUS_LOCK_MASK 0x00000001 - -#define MIPS_REFDIV_ADDR 0xB8144004 -#define MIPS_REFDIV_MASK 0x0000003F -#define MIPS_REFDIV_SHIFT 0 -#define MIPS_FEEDBACK_ADDR 0xB8144004 -#define MIPS_FEEDBACK_MASK 0x0003FFC0 -#define MIPS_FEEDBACK_SHIFT 6 - -/* Definitions for system clock setup */ -#define SYSCLKINTERNAL_CTRL_ADDR 0xB8144244 -#define SYSCLKINTERNAL_MASK 0X00000007 - -/* Definitions for MIPS clock setup */ -#define MIPSCLKINTERNAL_CTRL_ADDR 0xB8144204 -#define MIPSCLKINTERNAL_MASK 0x00000003 -#define MIPSCLKOUT_CTRL_ADDR 0xB8144208 -#define MIPSCLKOUT_MASK 0x000000FF - -/* Peripheral Clock gate reg */ -#define MIPS_CLOCK_GATE_ADDR 0xB8144900 -#define RPU_CLOCK_GATE_ADDR 0xB8144904 -#define MIPS_CLOCK_GATE_ALL_ON 0x3fff -#define RPU_CLOCK_GATE_ALL_OFF 0x0 - -/* Definitions for USB clock setup */ -#define USBPHYCLKOUT_CTRL_ADDR 0xB814422C -#define USBPHYCLKOUT_MASK 0X0000003F -#define USBPHYCONTROL1_ADDR 0xB8149004 -#define USBPHYCONTROL1_FSEL_SHIFT 2 -#define USBPHYCONTROL1_FSEL_MASK 0x1C -#define USBPHYSTRAPCTRL_ADDR 0xB8149010 -#define USBPHYSTRAPCTRL_REFCLKSEL_SHIFT 4 -#define USBPHYSTRAPCTRL_REFCLKSEL_MASK 0x30 -#define USBPHYSTATUS_ADDR 0xB8149014 -#define USBPHYSTATUS_RX_PHY_CLK_MASK 0x200 -#define USBPHYSTATUS_RX_UTMI_CLK_MASK 0x100 -#define USBPHYSTATUS_VBUS_FAULT_MASK 0x80 - -/* Definitions for UART0/1 setup */ -#define UART0CLKINTERNAL_CTRL_ADDR 0xB8144234 -#define UART0CLKINTERNAL_MASK 0x00000007 -#define UART0CLKOUT_CTRL_ADDR 0xB8144238 -#define UART0CLKOUT_MASK 0x000003FF -#define UART1CLKINTERNAL_CTRL_ADDR 0xB814423C -#define UART1CLKINTERNAL_MASK 0x00000007 -#define UART1CLKOUT_CTRL_ADDR 0xB8144240 -#define UART1CLKOUT_MASK 0x000003FF - -/* Definitions for I2C setup */ -#define I2CCLKDIV1_CTRL_ADDR(i) (0xB8144800 + 0x013C + (2*(i)*4)) -#define I2CCLKDIV1_MASK 0x0000007F -#define I2CCLKOUT_CTRL_ADDR(i) (0xB8144800 + 0x0140 + (2*(i)*4)) -#define I2CCLKOUT_MASK 0x0000007F - -/* Definitions for ROM clock setup */ -#define ROMCLKOUT_CTRL_ADDR 0xB814490C -#define ROMCLKOUT_MASK 0x0000007F - -/* Definitions for ETH clock setup */ -#define ENETCLKMUX_MASK 0x00004000 -#define ENETCLKDIV_CTRL_ADDR 0xB8144230 -#define ENETCLKDIV_MASK 0x0000003F - -/* Definitions for timeout values */ -#define PLL_TIMEOUT_VALUE_US 20000 -#define USB_TIMEOUT_VALUE_US 200000 -#define SYS_CLK_LOCK_DELAY 3 - -struct pll_parameters { - u32 external_bypass_mask; - u32 ctrl_addr; - u32 internal_bypass_mask; - u32 power_down_ctrl_addr; - u32 power_down_ctrl_mask; - u32 dacpd_addr; - u32 dacpd_mask; - u32 dsmpd_addr; - u32 dsmpd_mask; - u32 postdiv_addr; - u32 postdiv1_shift; - u32 postdiv1_mask; - u32 postdiv2_shift; - u32 postdiv2_mask; - u32 status_addr; - u32 status_lock_mask; - u32 refdivider; - u32 refdiv_addr; - u32 refdiv_shift; - u32 refdiv_mask; - u32 feedback; - u32 feedback_addr; - u32 feedback_shift; - u32 feedback_mask; -}; - -enum plls { - SYS_PLL = 0, - MIPS_PLL = 1 -}; - -static struct pll_parameters pll_params[] = { - [SYS_PLL] = { - .external_bypass_mask = SYS_EXTERN_PLL_BYPASS_MASK, - .ctrl_addr = SYS_PLL_CTRL4_ADDR, - .internal_bypass_mask = SYS_INTERNAL_PLL_BYPASS_MASK, - .power_down_ctrl_addr = SYS_PLL_PD_CTRL_ADDR, - .power_down_ctrl_mask = SYS_PLL_PD_CTRL_PD_MASK, - /* Noise cancellation */ - .dacpd_addr = SYS_PLL_DACPD_ADDR, - .dacpd_mask = SYS_PLL_DACPD_MASK, - .dsmpd_addr = SYS_PLL_DSMPD_ADDR, - /* 0 - Integer mode - * SYS_PLL_DSMPD_MASK - Fractional mode - */ - .dsmpd_mask = 0, - .postdiv_addr = SYS_PLL_POSTDIV_ADDR, - .postdiv1_shift = SYS_PLL_POSTDIV1_SHIFT, - .postdiv1_mask = SYS_PLL_POSTDIV1_MASK, - .postdiv2_shift = SYS_PLL_POSTDIV2_SHIFT, - .postdiv2_mask = SYS_PLL_POSTDIV2_MASK, - .status_addr = SYS_PLL_STATUS_ADDR, - .status_lock_mask = SYS_PLL_STATUS_LOCK_MASK, - .refdivider = 0, /* Not defined yet */ - .refdiv_addr = SYS_PLL_REFDIV_ADDR, - .refdiv_shift = SYS_PLL_REFDIV_SHIFT, - .refdiv_mask = SYS_PLL_REFDIV_MASK, - .feedback = 0, /* Not defined yet */ - .feedback_addr = SYS_PLL_FEEDBACK_ADDR, - .feedback_shift = SYS_PLL_FEEDBACK_SHIFT, - .feedback_mask = SYS_PLL_FEEDBACK_MASK - }, - - [MIPS_PLL] = { - .external_bypass_mask = MIPS_EXTERN_PLL_BYPASS_MASK, - .ctrl_addr = MIPS_PLL_CTRL2_ADDR, - .internal_bypass_mask = MIPS_INTERNAL_PLL_BYPASS_MASK, - .power_down_ctrl_addr = MIPS_PLL_PD_CTRL_ADDR, - .power_down_ctrl_mask = MIPS_PLL_PD_CTRL_PD_MASK, - .dacpd_addr = 0, - .dacpd_mask = 0, - .dsmpd_addr = MIPS_PLL_DSMPD_ADDR, - .dsmpd_mask = MIPS_PLL_DSMPD_MASK, - .postdiv_addr = MIPS_PLL_POSTDIV_ADDR, - .postdiv1_shift = MIPS_PLL_POSTDIV1_SHIFT, - .postdiv1_mask = MIPS_PLL_POSTDIV1_MASK, - .postdiv2_shift = MIPS_PLL_POSTDIV2_SHIFT, - .postdiv2_mask = MIPS_PLL_POSTDIV2_MASK, - .status_addr = MIPS_PLL_STATUS_ADDR, - .status_lock_mask = MIPS_PLL_STATUS_LOCK_MASK, - .refdivider = 0, /* Not defined yet */ - .refdiv_addr = MIPS_REFDIV_ADDR, - .refdiv_shift = MIPS_REFDIV_SHIFT, - .refdiv_mask = MIPS_REFDIV_MASK, - .feedback = 0, /* Not defined yet */ - .feedback_addr = MIPS_FEEDBACK_ADDR, - .feedback_shift = MIPS_FEEDBACK_SHIFT, - .feedback_mask = MIPS_FEEDBACK_MASK - } -}; - -static int pll_setup(struct pll_parameters *param, u8 divider1, u8 divider2) -{ - u32 reg; - struct stopwatch sw; - - /* Check input parameters */ - assert(!((divider1 << param->postdiv1_shift) & - ~(param->postdiv1_mask))); - assert(!((divider2 << param->postdiv2_shift) & - ~(param->postdiv2_mask))); - - /* Temporary bypass PLL (select XTAL as clock input) */ - reg = read32_x(PISTACHIO_CLOCK_SWITCH); - reg &= ~(param->external_bypass_mask); - write32_x(PISTACHIO_CLOCK_SWITCH, reg); - - /* Un-bypass PLL's internal bypass */ - reg = read32_x(param->ctrl_addr); - reg &= ~(param->internal_bypass_mask); - write32_x(param->ctrl_addr, reg); - - /* Disable power down */ - reg = read32_x(param->power_down_ctrl_addr); - reg &= ~(param->power_down_ctrl_mask); - write32_x(param->power_down_ctrl_addr, reg); - - /* Noise cancellation */ - if (param->dacpd_addr) { - reg = read32_x(param->dacpd_addr); - reg &= ~(param->dacpd_mask); - write32_x(param->dacpd_addr, reg); - } - - /* Functional mode */ - if (param->dsmpd_addr) { - reg = read32_x(param->dsmpd_addr); - reg &= ~(param->dsmpd_mask); - write32_x(param->dsmpd_addr, reg); - } - - if (param->feedback_addr) { - assert(!((param->feedback << param->feedback_shift) & - ~(param->feedback_mask))); - reg = read32_x(param->feedback_addr); - reg &= ~(param->feedback_mask); - reg |= (param->feedback << param->feedback_shift) & - param->feedback_mask; - write32_x(param->feedback_addr, reg); - } - - if (param->refdiv_addr) { - assert(!((param->refdivider << param->refdiv_shift) & - ~(param->refdiv_mask))); - reg = read32_x(param->refdiv_addr); - reg &= ~(param->refdiv_mask); - reg |= (param->refdivider << param->refdiv_shift) & - param->refdiv_mask; - write32_x(param->refdiv_addr, reg); - } - - /* Read postdivider register value */ - reg = read32_x(param->postdiv_addr); - /* Set divider 1 */ - reg &= ~(param->postdiv1_mask); - reg |= (divider1 << param->postdiv1_shift) & - param->postdiv1_mask; - /* Set divider 2 */ - reg &= ~(param->postdiv2_mask); - reg |= (divider2 << param->postdiv2_shift) & - param->postdiv2_mask; - /* Write back to register */ - write32_x(param->postdiv_addr, reg); - - /* Waiting for PLL to lock*/ - stopwatch_init_usecs_expire(&sw, PLL_TIMEOUT_VALUE_US); - while (!(read32_x(param->status_addr) & param->status_lock_mask)) { - if (stopwatch_expired(&sw)) - return PLL_TIMEOUT; - } - - /* Start using PLL */ - reg = read32_x(PISTACHIO_CLOCK_SWITCH); - reg |= param->external_bypass_mask; - write32_x(PISTACHIO_CLOCK_SWITCH, reg); - - return CLOCKS_OK; -} - -int sys_pll_setup(u8 divider1, u8 divider2, u8 refdivider, u32 feedback) -{ - pll_params[SYS_PLL].refdivider = refdivider; - pll_params[SYS_PLL].feedback = feedback; - return pll_setup(&(pll_params[SYS_PLL]), divider1, divider2); -} - -int mips_pll_setup(u8 divider1, u8 divider2, u8 refdivider, u32 feedback) -{ - pll_params[MIPS_PLL].refdivider = refdivider; - pll_params[MIPS_PLL].feedback = feedback; - return pll_setup(&(pll_params[MIPS_PLL]), divider1, divider2); -} - -/* - * uart1_clk_setup: sets up clocks for UART1 - * divider1: 3-bit divider value - * divider2: 10-bit divider value - */ -void uart1_clk_setup(u8 divider1, u16 divider2) -{ - u32 reg; - - /* Check input parameters */ - assert(!(divider1 & ~(UART1CLKINTERNAL_MASK))); - assert(!(divider2 & ~(UART1CLKOUT_MASK))); - - /* Set divider 1 */ - reg = read32_x(UART1CLKINTERNAL_CTRL_ADDR); - reg &= ~UART1CLKINTERNAL_MASK; - reg |= divider1 & UART1CLKINTERNAL_MASK; - write32_x(UART1CLKINTERNAL_CTRL_ADDR, reg); - - /* Set divider 2 */ - reg = read32_x(UART1CLKOUT_CTRL_ADDR); - reg &= ~UART1CLKOUT_MASK; - reg |= divider2 & UART1CLKOUT_MASK; - write32_x(UART1CLKOUT_CTRL_ADDR, reg); -} - -/* - * i2c_clk_setup: sets up clocks for I2C - * divider1: 7-bit divider value - * divider2: 7-bit divider value - */ -void i2c_clk_setup(u8 divider1, u16 divider2, u8 interface) -{ - u32 reg; - - /* Check input parameters */ - assert(!(divider1 & ~(I2CCLKDIV1_MASK))); - assert(!(divider2 & ~(I2CCLKOUT_MASK))); - assert(interface < 4); - /* Set divider 1 */ - reg = read32_x(I2CCLKDIV1_CTRL_ADDR(interface)); - reg &= ~I2CCLKDIV1_MASK; - reg |= divider1 & I2CCLKDIV1_MASK; - write32_x(I2CCLKDIV1_CTRL_ADDR(interface), reg); - - /* Set divider 2 */ - reg = read32_x(I2CCLKOUT_CTRL_ADDR(interface)); - reg &= ~I2CCLKOUT_MASK; - reg |= divider2 & I2CCLKOUT_MASK; - write32_x(I2CCLKOUT_CTRL_ADDR(interface), reg); -} - -/* system_clk_setup: sets up the system (peripheral) clock */ -void system_clk_setup(u8 divider) -{ - u32 reg; - - /* Check input parameters */ - assert(!(divider & ~(SYSCLKINTERNAL_MASK))); - - /* Set system clock divider */ - reg = read32_x(SYSCLKINTERNAL_CTRL_ADDR); - reg &= ~SYSCLKINTERNAL_MASK; - reg |= divider & SYSCLKINTERNAL_MASK; - write32_x(SYSCLKINTERNAL_CTRL_ADDR, reg); - - /* Small delay to cover a maximum lock time of 1500 cycles */ - udelay(SYS_CLK_LOCK_DELAY); -} - -void mips_clk_setup(u8 divider1, u8 divider2) -{ - u32 reg; - - /* Check input parameters */ - assert(!(divider1 & ~(MIPSCLKINTERNAL_MASK))); - assert(!(divider2 & ~(MIPSCLKOUT_MASK))); - - /* Set divider 1 */ - reg = read32_x(MIPSCLKINTERNAL_CTRL_ADDR); - reg &= ~MIPSCLKINTERNAL_MASK; - reg |= divider1 & MIPSCLKINTERNAL_MASK; - write32_x(MIPSCLKINTERNAL_CTRL_ADDR, reg); - - /* Set divider 2 */ - reg = read32_x(MIPSCLKOUT_CTRL_ADDR); - reg &= ~MIPSCLKOUT_MASK; - reg |= divider2 & MIPSCLKOUT_MASK; - write32_x(MIPSCLKOUT_CTRL_ADDR, reg); -} - -/* usb_clk_setup: sets up USB clock */ -int usb_clk_setup(u8 divider, u8 refclksel, u8 fsel) -{ - u32 reg; - struct stopwatch sw; - - /* Check input parameters */ - assert(!(divider & ~(USBPHYCLKOUT_MASK))); - assert(!((refclksel << USBPHYSTRAPCTRL_REFCLKSEL_SHIFT) & - ~(USBPHYSTRAPCTRL_REFCLKSEL_MASK))); - assert(!((fsel << USBPHYCONTROL1_FSEL_SHIFT) & - ~(USBPHYCONTROL1_FSEL_MASK))); - - /* Set USB divider */ - reg = read32_x(USBPHYCLKOUT_CTRL_ADDR); - reg &= ~USBPHYCLKOUT_MASK; - reg |= divider & USBPHYCLKOUT_MASK; - write32_x(USBPHYCLKOUT_CTRL_ADDR, reg); - - /* Set REFCLKSEL */ - reg = read32_x(USBPHYSTRAPCTRL_ADDR); - reg &= ~USBPHYSTRAPCTRL_REFCLKSEL_MASK; - reg |= (refclksel << USBPHYSTRAPCTRL_REFCLKSEL_SHIFT) & - USBPHYSTRAPCTRL_REFCLKSEL_MASK; - write32_x(USBPHYSTRAPCTRL_ADDR, reg); - - /* Set FSEL */ - reg = read32_x(USBPHYCONTROL1_ADDR); - reg &= ~USBPHYCONTROL1_FSEL_MASK; - reg |= (fsel << USBPHYCONTROL1_FSEL_SHIFT) & - USBPHYCONTROL1_FSEL_MASK; - write32_x(USBPHYCONTROL1_ADDR, reg); - - /* Waiting for USB clock status */ - stopwatch_init_usecs_expire(&sw, USB_TIMEOUT_VALUE_US); - while (1) { - reg = read32_x(USBPHYSTATUS_ADDR); - if (reg & USBPHYSTATUS_VBUS_FAULT_MASK) - return USB_VBUS_FAULT; - if (stopwatch_expired(&sw)) - return USB_TIMEOUT; - /* Check if USB is set up properly */ - if ((reg & USBPHYSTATUS_RX_PHY_CLK_MASK) && - (reg & USBPHYSTATUS_RX_UTMI_CLK_MASK)) - break; - } - - return CLOCKS_OK; -} - -void rom_clk_setup(u8 divider) -{ - u32 reg; - - /* Check input parameter */ - assert(!(divider & ~(ROMCLKOUT_MASK))); - - /* Set ROM divider */ - reg = read32_x(ROMCLKOUT_CTRL_ADDR); - reg &= ~ROMCLKOUT_MASK; - reg |= divider & ROMCLKOUT_MASK; - write32_x(ROMCLKOUT_CTRL_ADDR, reg); -} - -void eth_clk_setup(u8 mux, u8 divider) -{ - - u32 reg; - - /* Check input parameters */ - assert(!(divider & ~(ENETCLKDIV_MASK))); - /* This can be either 0 or 1, selecting between - * ENET and system clock as clocksource */ - assert(!(mux & ~(0x1))); - - /* Set ETH divider */ - reg = read32_x(ENETCLKDIV_CTRL_ADDR); - reg &= ~ENETCLKDIV_MASK; - reg |= divider & ENETCLKDIV_MASK; - write32_x(ENETCLKDIV_CTRL_ADDR, reg); - - /* Select source */ - if (mux) { - reg = read32_x(PISTACHIO_CLOCK_SWITCH); - reg |= ENETCLKMUX_MASK; - write32_x(PISTACHIO_CLOCK_SWITCH, reg); - } -} - -void setup_clk_gate_defaults(void) -{ - write32_x(MIPS_CLOCK_GATE_ADDR, MIPS_CLOCK_GATE_ALL_ON); - write32_x(RPU_CLOCK_GATE_ADDR, RPU_CLOCK_GATE_ALL_OFF); -} diff --git a/src/soc/imgtec/pistachio/ddr2_init.c b/src/soc/imgtec/pistachio/ddr2_init.c deleted file mode 100644 index 39b553df24..0000000000 --- a/src/soc/imgtec/pistachio/ddr2_init.c +++ /dev/null @@ -1,443 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2014 Imagination Technologies - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include -#include - -#define BL8 0 - -/* - * Configuration for the Winbond W972GG6JB-25 part using - * Synopsys DDR uMCTL and DDR Phy - */ -int init_ddr2(void) -{ - - /* - * Reset the AXI bridge and DDR Controller in case any spurious - * writes have already happened to DDR - note must be done together, - * not sequentially - */ - write32_x(TOPLEVEL_REGS + DDR_CTRL_OFFSET, 0x00000000); - write32_x(TOPLEVEL_REGS + DDR_CTRL_OFFSET, 0x0000000F); - /* - * Dummy read to fence the access between the reset above - * and thw DDR controller writes below - */ - read32_x(TOPLEVEL_REGS + DDR_CTRL_OFFSET); - /* Timings for 400MHz - * therefore 200MHz (5ns) uMCTL (Internal) Rate - */ - /* TOGCNT1U: Toggle Counter 1U Register: 1us 200h C8h */ - write32_x(DDR_PCTL + DDR_PCTL_TOGCNT1U_OFFSET, 0x000000C8); - /* TINIT: t_init Timing Register: at least 200us 200h C8h */ - write32_x(DDR_PCTL + DDR_PCTL_TINIT_OFFSET, 0x000000C8); - /* TRSTH: Reset High Time Register DDR3 ONLY */ - write32_x(DDR_PCTL + DDR_PCTL_TRSTH_OFFSET, 0x00000000); - /* TOGCNT100N: Toggle Counter 100N Register: 20d, 14h*/ - write32_x(DDR_PCTL + DDR_PCTL_TOGG_CNTR_100NS_OFFSET, 0x00000014); - /* DTUAWDT DTU Address Width Register - * 1:0 column_addr_width Def 10 - 7 3 10 bits - * 4:3 bank_addr_width Def 3 - 2 1 3 bits (8 bank) - * 7:6 row_addr_width Def 14 - 13 1 3 bits - * 10:9 number_ranks Def 1 - 1 0 0 1 Rank - */ - write32_x(DDR_PCTL + DDR_PCTL_DTUAWDT_OFFSET, 0x0000004B); - /* MCFG - * 0 BL 0 = 4 1 = 8 - * 1 RDRIMM 0 - * 2 BL8 Burst Terminate 0 - * 3 2T = 0 - * 4 Multi Rank 0 - * 5 DDR3 En 0 - * 6 LPDDR S4 En - * 7 BST En 0, 1 for LPDDR2/3 - * 15:8 Power down Idle, passed by argument - * 16 Power Down Type, passed by argument - * 17 Power Down Exit 0 = slow, 1 = fast, pba - * 19:18 tFAW 45ns = 9 clk 5*2 -1 1h - * 21:20 mDDR/LPDDR2 BL 0 - * 23:22 mDDR/LPDDR2 Enable 0 - * 31:24 mDDR/LPDDR2/3 Dynamic Clock Stop 0 - */ - write32_x(DDR_PCTL + DDR_PCTL_MCFG_OFFSET, - 0x00060000 | (BL8 ? 0x1 : 0x0)); - /* MCFG1: Memory Configuration-1 Register - * c7:0 sr_idle Self Refresh Idle Entery 32 * nclks 14h, set 0 for BUB - * 10:8 Fine tune MCFG.19:18 -1 - * 15:11 Reserved - * 23:16 Hardware Idle Period NA 0 - * 30:24 Reserved - * 31 c_active_in_pin exit auto clk stop NA 0 - */ - write32_x(DDR_PCTL + DDR_PCTL_MCFG1_OFFSET, 0x00000100); - /* DCR DRAM Config - * 2:0 SDRAM => DDR2 2 - * 3 DDR 8 Bank 1 - * 6:4 Primary DQ DDR3 Only 0 - * 7 Multi-Purpose Register DDR3 Only 0 - * 9:8 DDRTYPE LPDDR2 00 - * 26:10 Reserved - * 27 NOSRA No Simultaneous Rank Access 0 - * 28 DDR 2T 0 - * 29 UDIMM NA 0 - * 30 RDIMM NA 0 - * 31 TPD LPDDR2 0 - */ - write32_x(DDR_PHY + DDRPHY_DCR_OFFSET, 0x0000000A); - /* Generate to use with PHY and PCTL - * MR0 : MR Register, bits 12:0 imported dfrom MR - * 2:0 BL 8 011 - * 3 BT Sequential 0 Interleaved 1 = 0 - * 6:4 CL 6 - * 7 TM Normal 0 - * 8 DLL Reset 1 (self Clearing) - * 11:9 WR 15 ns 6 (101) - * 12 PD Slow 1 Fast 0 0 - * 15:13 RSVD RSVD - * 31:16 Reserved - */ - write32_x(DDR_PHY + DDRPHY_MR_OFFSET, 0x00000B62 | (BL8 ? 0x1 : 0x0)); - /* MR1 : EMR Register - * Generate to use with PHY and PCTL - * 0 DE DLL Enable 0 Disable 1 - * 1 DIC Output Driver Imp Ctl 0 Full, 1 Half - * 6,2 ODT 0 Disable, 1 75R, 2 150R, 3 50R; LSB: 2, MSB: 6 - * 5:3 AL = 0 - * 9:7 OCD = 0 - * 10 DQS 0 diff, 1 single = 0 - * 11 RDQS NA 0 - * 12 QOFF Normal mode 0 - * 15:13 RSVD - * 31:16 Reserved - */ - write32_x(DDR_PHY + DDRPHY_EMR_OFFSET, 0x00000044); - /* MR2 : EMR2 Register - * Generate to use with PHY and PCTL - * 2:0 PASR, NA 000 - * 3 DDC NA 0 - * 6:4 RSVD - * 7 SFR 0 - * 15:8 RSVD - * 31:16 Reserved - */ - write32_x(DDR_PHY + DDRPHY_EMR2_OFFSET, 0x00000000); - /* DSGCR - * 0 PUREN Def 1 - * 1 BDISEN Def 1 - * 2 ZUEN Def 1 - * 3 LPIOPD DEf 1 0 - * 4 LPDLLPD DEf 1 0 - * 7:5 DQSGX DQS Extention set to 1 - advised by Synopsys - * 10:8 DQSGE DQS Early Gate - 1 - advised by Sysnopsys - * 11 NOBUB No Bubbles, adds latency 1 - * 12 FXDLAT Fixed Read Latency 0 - * 15:13 Reserved - * 19:16 CKEPDD CKE Power Down 0000 - * 23:20 ODTPDD ODT Power Down 0000 - * 24 NL2PD Power Down Non LPDDR2 pins 0 - * 25 NL2OE Output Enable Non LPDDR2 pins 1 - * 26 TPDPD LPDDR Only 0 - * 27 TPDOE LPDDR Only 0 - * 28 CKOE Output Enable Clk's 1 - * 29 ODTOE Output Enable ODT 1 - * 30 RSTOE RST# Output Enable 1 - * 31 CKEOE CKE Output Enable 1 - */ - write32_x(DDR_PHY + DDRPHY_DSGCR_OFFSET, 0xF2000927); - /* Sysnopsys advised 500R pullup/pulldown DQS DQSN */ - write32_x(DDR_PHY + DDRPHY_DXCCR_OFFSET, 0x00000C40); - /* DTPR0 : DRAM Timing Params 0 - * 1:0 tMRD 2 - * 4:2 tRTP 3 - * 7:5 tWTR 3 - * 11:8 tRP 6 - * 15:12 tRCD 6 - * 20:16 tRAS 18 - * 24:21 tRRD 4 - * 30:25 tRC 24 (23) - * 31 tCCD 0 BL/2 Cas to Cas - */ - write32_x(DDR_PHY + DDRPHY_DTPR0_OFFSET, 0x3092666E); - /* DTPR1 : DRAM Timing Params 1 - * 1:0 ODT On/Off Del Std 0 - * 2 tRTW Rd2Wr Del 0 std 1 +1 0 - * 8:3 tFAW 4 Bank Act 45ns = 18 18 - * 10:9 tMOD DDR3 Only 0 - * 11 tRTODT DDR3 Only 0 - * 15:12 Reserved - * 23:16 tRFC 195ns 78 def 131 78d - * 26:24 tDQSCK LPDDR2 only 1 - * 29:27 tDQSCKmax 1 - * 31:30 Reserved - */ - write32_x(DDR_PHY + DDRPHY_DTPR1_OFFSET, 0x094E0092); - /* DTPR2 : DRAM Timing Params 2 - * 9:0 tXS exit SR def 200, 200d - * 14:10 tXP PD Exit Del 8 3 - * 18:15 tCKE CKE Min pulse 3 - * 28:19 tDLLK DLL Lock time 200d - * 32:29 Reserved - */ - write32_x(DDR_PHY + DDRPHY_DTPR2_OFFSET, 0x06418CC8); - /* PTR0 : PHY Timing Params 0 - * 5:0 tDLLRST Def 27 - * 17:6 tDLLLOCK Def 2750 - * 21:18 tITMSRST Def 8 - * 31:22 Reserved 0 - */ - write32_x(DDR_PHY + DDRPHY_PTR0_OFFSET, 0x0022AF9B); - /* PTR1 : PHY Timing Params 1 - * 18:0 : tDINITO DRAM Init time 200us 80,000 Dec 0x13880 - * 29:19 : tDINIT1 DRAM Init time 400ns 160 Dec 0xA0 - */ - write32_x(DDR_PHY + DDRPHY_PTR1_OFFSET, 0x05013880); - /* DQS gating configuration: passive windowing mode */ - /* - * PGCR: PHY General cofiguration register - * 0 ITM DDR mode: 0 - * 1 DQS gading configuration: passive windowing 1 - * 2 DQS drift compensation: not supported in passive windowing 0 - * 4:3 DQS drift limit 0 - * 8:5 Digital test output select 0 - * 11:9 CK Enable: one bit for each 3 CK pair: 0x7 - * 13:12 CK Disable values: 0x2 - * 14 CK Invert 0 - * 15 IO loopback 0 - * 17:16 I/O DDR mode 0 - * 21:18 Ranks enable by training: 0xF - * 23:22 Impedance clock divider select 0x2 - * 24 Power down disable 1 - * 28:25 Refresh during training 0 - * 29 loopback DQS shift 0 - * 30 loopback DQS gating 0 - * 31 loopback mode 0 - */ - write32_x(DDR_PHY + DDRPHY_PGCR_OFFSET, 0x01BC2E02); - /* PGSR : Wait for INIT/DLL/Z Done from Power on Reset */ - if (wait_for_completion(DDR_PHY + DDRPHY_PGSR_OFFSET, 0x00000007)) - return DDR_TIMEOUT; - /* PIR : use PHY for DRAM Init */ - write32_x(DDR_PHY + DDRPHY_PIR_OFFSET, 0x000001DF); - /* PGSR : Wait for DRAM Init Done */ - if (wait_for_completion(DDR_PHY + DDRPHY_PGSR_OFFSET, 0x0000001F)) - return DDR_TIMEOUT; - /* Disable Impedance Calibration */ - write32_x(DDR_PHY + DDRPHY_ZQ0CR0_OFFSET, 0x3000014A); - write32_x(DDR_PHY + DDRPHY_ZQ1CR0_OFFSET, 0x3000014A); - - /* DF1STAT0 : wait for DFI_INIT_COMPLETE */ - if (wait_for_completion(DDR_PCTL + DDR_PCTL_DFISTAT0_OFFSET, - 0x00000001)) - return DDR_TIMEOUT; - /* POWCTL : Start the memory Power Up seq*/ - write32_x(DDR_PCTL + DDR_PCTL_POWCTL_OFFSET, 0x00000001); - /* POWSTAT : wait for POWER_UP_DONE */ - if (wait_for_completion(DDR_PCTL + DDR_PCTL_POWSTAT_OFFSET, - 0x00000001)) - return DDR_TIMEOUT; - /* - * TREFI : t_refi Timing Register 1X - * 12:0 t_refi 7.8us in 100ns 0x4E - * 15:13 Reserved 0 - * 18:16 num_add_ref 0 - * 30:19 Reserved 0 - * 31 Update 1 - */ - write32_x(DDR_PCTL + DDR_PCTL_TREFI_OFFSET, 0x8000004E); - /* TMRD : t_mrd Timing Register -- Range 2 to 3 */ - write32_x(DDR_PCTL + DDR_PCTL_TMRD_OFFSET, 0x00000002); - /* - * TRFC : t_rfc Timing Register -- Range 15 to 131 - * 195ns / 2.5ns 78 x4E - */ - write32_x(DDR_PCTL + DDR_PCTL_TRFC_OFFSET, 0x0000004E); - /* TRP : t_rp Timing Register -- Range 3 to 7 - * 4:0 tRP 12.5 / 2.5 = 5 6 For Now 6-6-6 - * 17:16 rpea_extra tRPall 8 bank 1 - */ - write32_x(DDR_PCTL + DDR_PCTL_TRP_OFFSET, 0x00010006); - /* TAL : Additive Latency Register -- AL in MR1 */ - write32_x(DDR_PCTL + DDR_PCTL_TAL_OFFSET, 0x00000000); - /* DFITPHYWRLAT : Write cmd to dfi_wrdata_en */ - write32_x(DDR_PCTL + DDR_PCTL_DFIWRLAT_OFFSET, 0x00000002); - /* DFITRDDATAEN : Read cmd to dfi_rddata_en */ - write32_x(DDR_PCTL + DDR_PCTL_DFITRDDATAEN_OFFSET, 0x00000002); - /* TCL : CAS Latency Timing Register -- CASL in MR0 6-6-6 */ - write32_x(DDR_PCTL + DDR_PCTL_TCL_OFFSET, 0x00000006); - /* TCWL : CAS Write Latency Register --CASL-1 */ - write32_x(DDR_PCTL + DDR_PCTL_TCWL_OFFSET, 0x00000005); - /* - * TRAS : Activate to Precharge cmd time - * Range 8 to 24: 45ns / 2.5ns = 18d - */ - write32_x(DDR_PCTL + DDR_PCTL_TRAS_OFFSET, 0x00000012); - /* - * TRC : Min. ROW cycle time - * Range 11 to 31: 57.5ns / 2.5ns = 23d Playing safe 24 - */ - write32_x(DDR_PCTL + DDR_PCTL_TRC_OFFSET, 0x00000018); - /* - * TRCD : Row to Column Delay - * Range 3 to 7 (TCL = TRCD): 2.5ns / 2.5ns = 5 but running 6-6-6 6 - */ - write32_x(DDR_PCTL + DDR_PCTL_TRCD_OFFSET, 0x00000006); - /* TRRD : Row to Row delay -- Range 2 to 6: 2K Page 10ns / 2.5ns = 4*/ - write32_x(DDR_PCTL + DDR_PCTL_TRRD_OFFSET, 0x00000004); - /* TRTP : Read to Precharge time -- Range 2 to 4: 7.3ns / 2.5ns = 3 */ - write32_x(DDR_PCTL + DDR_PCTL_TRTP_OFFSET, 0x00000003); - /* TWR : Write recovery time -- WR in MR0: 15ns / 2.5ns = 6 - */ - write32_x(DDR_PCTL + DDR_PCTL_TWR_OFFSET, 0x00000006); - /* - * TWTR : Write to read turn around time - * Range 2 to 4: 7.3ns / 2.5ns = 3 - */ - write32_x(DDR_PCTL + DDR_PCTL_TWTR_OFFSET, 0x00000003); - /* TEXSR : Exit Self Refresh to first valid cmd: tXS 200*/ - write32_x(DDR_PCTL + DDR_PCTL_TEXSR_OFFSET, 0x000000C8); - /* - * TXP : Exit Power Down to first valid cmd - * tXP 2, Settingto 3 to match PHY - */ - write32_x(DDR_PCTL + DDR_PCTL_TXP_OFFSET, 0x00000003); - /* - * TDQS : t_dqs Timing Register - * DQS additional turn around Rank 2 Rank (1 Rank) Def 1 - */ - write32_x(DDR_PCTL + DDR_PCTL_TDQS_OFFSET, 0x00000001); - /*TRTW : Read to Write turn around time Def 3 - * Actual gap t_bl + t_rtw - */ - write32_x(DDR_PCTL + DDR_PCTL_TRTW_OFFSET, 0x00000003); - /* TCKE : CKE min pulse width DEf 3 */ - write32_x(DDR_PCTL + DDR_PCTL_TCKE_OFFSET, 0x00000003); - /* - * TXPDLL : Slow Exit Power Down to first valid cmd delay - * tXARDS 10+AL = 10 - */ - write32_x(DDR_PCTL + DDR_PCTL_TXPDLL_OFFSET, 0x0000000A); - /* - * TCKESR : Min CKE Low width for Self refresh entry to exit - * t_ckesr = 0 DDR2 - */ - write32_x(DDR_PCTL + DDR_PCTL_TCKESR_OFFSET, 0x00000000); - /* SCFG : State Configuration Register (Enabling Self Refresh) - * 0 LP_en Leave Off for Bring Up 0 - * 5:1 Reserved - * 6 Synopsys Internal Only 0 - * 7 Enale PHY indication of LP Opportunity 1 - * 11:8 bbflags_timing max UPCTL_TCU_SED_P - tRP (16 - 6) Use 4 - * 16:12 Additional delay on accertion of ac_pdd 4 - * 31:17 Reserved - */ - write32_x(DDR_PCTL + DDR_PCTL_SCFG_OFFSET, 0x00004480); - /* - * DFITPHYWRDATA : dfi_wrdata_en to drive wr data - * DFI Clks wrdata_en to wrdata Def 1 - */ - write32_x(DDR_PCTL + DDR_PCTL_DFITPHYWRDATA_OFFSET, 0x00000000); - /* - * DFITPHYRDLAT : dfi_rddata_en to dfi_rddata_valid - * DFI clks max rddata_en to rddata_valid Def 15 - */ - write32_x(DDR_PCTL + DDR_PCTL_DFITPHYRDLAT_OFFSET, 0x00000008); - /* MCMD : PREA, Addr 0 Bank 0 Rank 0 Del 0 - * 3:0 cmd_opcode PREA 00001 - * 16:4 cmd_addr 0 - * 19:17 bank_addr 0 - * 23:20 rank_sel 0 0001 - * 27:24 cmddelay 0 - * 30:24 Reserved - */ - write32_x(DDR_PCTL + DDR_PCTL_MCMD_OFFSET, 0x80100001); - /* MRS cmd wait for completion */ - if (wait_for_completion(DDR_PCTL + DDR_PCTL_MCMD_OFFSET, 0x00100001)) - return DDR_TIMEOUT; - /* SCTL : UPCTL switch INIT CONFIG State */ - write32_x(DDR_PCTL + DDR_PCTL_SCTL_OFFSET, 0x00000001); - /* STAT : Wait for Switch INIT to Config State */ - if (wait_for_completion(DDR_PCTL + DDR_PCTL_STAT_OFFSET, 0x00000001)) - return DDR_TIMEOUT; - /* DFISTCFG0 : Drive various DFI signals appropriately - * 0 dfi_init_start 0 - * 1 dfi_freq_ratio_en 1 - * 2 dfi_data_byte_disable_en 1 - */ - write32_x(DDR_PCTL + DDR_PCTL_DFISTCFG0_OFFSET, 0x00000003); - /* DFISTCFG1 : Enable various DFI support - * 0 dfi_dram_clk_disable_en 1 - * 1 dfi_dram_clk_disable_en_pdp only lPDDR 0 - */ - write32_x(DDR_PCTL + DDR_PCTL_DFISTCFG1_OFFSET, 0x00000001); - /* DFISTCFG2 : Enable Parity and asoc interrupt - * 0 dfi_parity_in Enable 1 - * 1 Interrupt on dfi_parity_error 1 - */ - write32_x(DDR_PCTL + DDR_PCTL_DFISTCFG2_OFFSET, 0x00000003); - /* DFILPCFG0 : DFI Low Power Interface Configuration - * 0 Enable DFI LP IF during PD 1 - * 3:1 Reserved - * 7:4 DFI tlp_wakeup time 0 - * 8 Enable DFI LP IF during SR 1 - * 11:9 Reserved - * 15:12 dfi_lp_wakeup in SR 0 - * 19:16 tlp_resp DFI 2.1 recomend 7 - * 23:20 Reserved - * 24 Enable DFI LP in Deep Power Down 0 - * 27:25 Reserved - * 31:28 DFI LP Deep Power Down Value 0 - */ - write32_x(DDR_PCTL + DDR_PCTL_DFILPCFG0_OFFSET, 0x00070101); - /* DFIODTCFG : DFI ODT Configuration - * Only Enabled on Rank0 Writes - * 0 rank0_odt_read_nsel 0 - * 1 rank0_odt_read_sel 0 - * 2 rank0_odt_write_nsel 0 - * 3 rank0_odt_write_sel 1 - */ - write32_x(DDR_PCTL + DDR_PCTL_DFIODTCFG_OFFSET, 0x00000008); - /* DFIODTCFG1 : DFI ODT Configuration - * 4:0 odt_lat_w 4 - * 12:8 odt_lat_r 0 Def - * 4:0 odt_len_bl8_w 6 Def - * 12:8 odt_len_bl8_r 6 Def - */ - write32_x(DDR_PCTL + DDR_PCTL_DFIODTCFG1_OFFSET, 0x06060004); - /* DCFG : DRAM Density 256 Mb 16 Bit IO Width - * 1:0 Devicw Width 1 x8, 2 x16, 3 x32 2 - * 5:2 Density 2Gb = 5 - * 6 Dram Type (MDDR/LPDDR2) Only 0 - * 7 Reserved 0 - * 10:8 Address Map R/B/C = 1 - * 31:11 Reserved - */ - write32_x(DDR_PCTL + DDR_PCTL_DCFG_OFFSET, 0x00000116); - /* PCFG_0 : Port 0 AXI config */ - if (BL8) - write32_x(DDR_PCTL + DDR_PCTL_PCFG0_OFFSET, 0x000800A0); - else - write32_x(DDR_PCTL + DDR_PCTL_PCFG0_OFFSET, 0x000400A0); - /* SCTL : UPCTL switch Config to ACCESS State */ - write32_x(DDR_PCTL + DDR_PCTL_SCTL_OFFSET, 0x00000002); - /* STAT : Wait for switch CFG -> GO State */ - if (wait_for_completion(DDR_PCTL + DDR_PCTL_STAT_OFFSET, 0x3)) - return DDR_TIMEOUT; - - return 0; -} diff --git a/src/soc/imgtec/pistachio/ddr3_init.c b/src/soc/imgtec/pistachio/ddr3_init.c deleted file mode 100644 index 7392525d23..0000000000 --- a/src/soc/imgtec/pistachio/ddr3_init.c +++ /dev/null @@ -1,514 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2014 Imagination Technologies - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include -#include - -/* - * Configuration for the Winbond W631GG6KB part using - * Synopsys DDR uMCTL and DDR Phy - */ -int init_ddr3(void) -{ - uint32_t temp_rw_val; - - temp_rw_val = read32_x(TOPLEVEL_REGS + DDR_CTRL_OFFSET); - /* Set CLK_EN = 1 */ - temp_rw_val |= 0x2; - write32_x(TOPLEVEL_REGS + DDR_CTRL_OFFSET, temp_rw_val); - read32_x(TOPLEVEL_REGS + DDR_CTRL_OFFSET); - /* - * Reset the AXI bridge and DDR Controller in case any spurious - * writes have already happened to DDR - */ - /* Drive the 3 resets low */ - write32_x(TOPLEVEL_REGS + DDR_CTRL_OFFSET, 0x00000002); - read32_x(TOPLEVEL_REGS + DDR_CTRL_OFFSET); - read32_x(TOPLEVEL_REGS + DDR_CTRL_OFFSET); - - /* And release */ - write32_x(TOPLEVEL_REGS + DDR_CTRL_OFFSET, 0x0000000F); - /* Dummy read to fence the access between the reset above and - * the DDR controller writes below - */ - read32_x(TOPLEVEL_REGS + DDR_CTRL_OFFSET); - - /* Timings for 400MHz - * therefore 200MHz (5ns) uMCTL (Internal) Rate - */ - /* TOGCNT1U: Toggle Counter 1U Register: 1us 200h C8h */ - write32_x(DDR_PCTL + DDR_PCTL_TOGCNT1U_OFFSET, 0x000000C8); - /* TINIT: t_init Timing Register: at least 200us 200h C8h */ - write32_x(DDR_PCTL + DDR_PCTL_TINIT_OFFSET, 0x000000C8); - /* TRSTH: Reset High Time Register DDR3 ONLY */ - write32_x(DDR_PCTL + DDR_PCTL_TRSTH_OFFSET, 0x000001F4); - /* TOGCNT100N: Toggle Counter 100N Register: 20d, 14h*/ - write32_x(DDR_PCTL + DDR_PCTL_TOGG_CNTR_100NS_OFFSET, 0x00000014); - /* DTUAWDT DTU Address Width Register - * 1:0 column_addr_width Def 10 - 7 3 10 bits - * 4:3 bank_addr_width Def 3 - 2 1 3 bits (8 bank) - * 7:6 row_addr_width Def 14 - 13 1 3 bits - * 10:9 number_ranks Def 1 - 1 0 0 1 Rank - */ - write32_x(DDR_PCTL + DDR_PCTL_DTUAWDT_OFFSET, 0x0000004B); - /* MCFG - * 0 BL 1 -> 8 fixed - * 1 RDRIMM 0 - * 2 BL8 Burst Terminate 0 - * 3 2T = 0 - * 4 Multi Rank 0 - * 5 DDR3 En 1 - * 6 LPDDR S4 En - * 7 BST En 0, 1 for LPDDR2/3 - * 15:8 Power down Idle, passed by argument - * 16 Power Down Type, passed by argument - * 17 Power Down Exit 0 = slow, 1 = fast, pba - * 19:18 tFAW 45ns = 9 clk 5*2 -1 1h - * 21:20 mDDR/LPDDR2 BL 0 - * 23:22 mDDR/LPDDR2 Enable 0 - * 31:24 mDDR/LPDDR2/3 Dynamic Clock Stop 0 - */ - write32_x(DDR_PCTL + DDR_PCTL_MCFG_OFFSET, 0x00060021); - /* MCFG1: Memory Configuration-1 Register - * c7:0 sr_idle Self Refresh Idle Entery 32 * nclks 14h, set 0 for BUB - * 10:8 Fine tune MCFG.19:18 -1 - * 15:11 Reserved - * 23:16 Hardware Idle Period NA 0 - * 30:24 Reserved - * 31 c_active_in_pin exit auto clk stop NA 0 - */ - write32_x(DDR_PCTL + DDR_PCTL_MCFG1_OFFSET, 0x00000100); - /* DCR DRAM Config - * 2:0 SDRAM => DDR3 3 - * 3 DDR 8 Bank 1 - * 6:4 Primary DQ DDR3 Only 0 - * 7 Multi-Purpose Register DDR3 Only 0 - * 9:8 DDRTYPE LPDDR2 00 - * 26:10 Reserved - * 27 NOSRA No Simultaneous Rank Access 0 - * 28 DDR 2T 0 - * 29 UDIMM NA 0 - * 30 RDIMM NA 0 - * 31 TPD LPDDR2 0 - */ - write32_x(DDR_PHY + DDRPHY_DCR_OFFSET, 0x0000000B); - /* Generate to use with PHY and PCTL - * MR0 : DDR3 mode register 0 - * 1:0 BL 8 fixed 00 - * 3 BT Sequential 0 Interleaved 1 = 0 - * 6:4,2 CL 6 - * 7 TM Normal 0 - * 8 DLL Reset 1 (self Clearing) - * 11:9 WR 15 ns 6 (010) - * 12 PD Slow 1 Fast 0 0 - * 15:13 RSVD RSVD - * 31:16 Reserved - */ - write32_x(DDR_PHY + DDRPHY_MR_OFFSET, 0x00001520); - /* MR1 : DDR3 mode register 1 - * Generate to use with PHY and PCTL - * 0 DE DLL Enable 0 Disable 1 - * 5,1 DIC Output Driver RZQ/6 - * 9,6,2 ODT RZQ/4 - * 4:3 AL = 0 - * 7 write leveling enabled 0 - * 10 DQS 0 diff, 1 single = 0 - * 11 TDQS NA 0 - * 12 QOFF Normal mode 0 - * 15:13 RSVD - * 31:16 Reserved - */ - write32_x(DDR_PHY + DDRPHY_EMR_OFFSET, 0x00000004); - /* MR2 : DDR3 mode register 2 - * Generate to use with PHY and PCTL - * 2:0 PASR, NA 000 - * 3 CWL 000 (5) tck = 22.5ns - * 6 auto self-refresh 1 - * 7 SRT normal 0 - * 8 RSVD - * 10:9 dynamic ODT 10 RZQ/2 - * 31:11 Reserved - */ - write32_x(DDR_PHY + DDRPHY_EMR2_OFFSET, 0x00000440); - /* MR3: DDR3 mode register 3 - * 1:0 MPRLOC 00 - * 2 MPR 0 - */ - write32_x(DDR_PHY + DDRPHY_EMR3_OFFSET, 0x00000000); - /* DTAR : Data Training Register - * 11:0 Data Training Column Address - * 27:12 Data Training Row Address - * 30:28 Data Training Bank Address - * 31 Data Training Use MPR (DDR3 Only) - */ - write32_x(DDR_PHY + DDRPHY_DTAR_OFFSET, 0x00000000); - /* DSGCR - * 0 PUREN Def 1 - * 1 BDISEN Def 1 - * 2 ZUEN Def 1 - * 3 LPIOPD DEf 1 0 - * 4 LPDLLPD DEf 1 0 - * 7:5 DQSGX DQS Extention set to 1 - advised by Synopsys - * 10:8 DQSGE DQS Early Gate - 1 - advised by Sysnopsys - * 11 NOBUB No Bubbles, adds latency 1 - * 12 FXDLAT Fixed Read Latency 0 - * 15:13 Reserved - * 19:16 CKEPDD CKE Power Down 0000 - * 23:20 ODTPDD ODT Power Down 0000 - * 24 NL2PD Power Down Non LPDDR2 pins 0 - * 25 NL2OE Output Enable Non LPDDR2 pins 1 - * 26 TPDPD LPDDR Only 0 - * 27 TPDOE LPDDR Only 1 - * 28 CKOE Output Enable Clk's 1 - * 29 ODTOE Output Enable ODT 1 - * 30 RSTOE RST# Output Enable 1 - * 31 CKEOE CKE Output Enable 1 - */ - write32_x(DDR_PHY + DDRPHY_DSGCR_OFFSET, 0xFA000927); - /* Sysnopsys advised 500R pullup/pulldown DQS DQSN */ - write32_x(DDR_PHY + DDRPHY_DXCCR_OFFSET, 0x00000C40); - /* DTPR0 : DRAM Timing Params 0 - * 1:0 tMRD 0 - * 4:2 tRTP 2 - * 7:5 tWTR 4 - * 11:8 tRP 6 - * 15:12 tRCD 6 - * 20:16 tRAS 15 - * 24:21 tRRD 4 for x16 - * 30:25 tRC 21 - * 31 tCCD 0 BL/2 Cas to Cas - */ - write32_x(DDR_PHY + DDRPHY_DTPR0_OFFSET, 0x2A8F6688); - /* DTPR1 : DRAM Timing Params 1 - * 1:0 ODT On/Off Del Std 0 - * 2 tRTW Rd2Wr Del 0 std 1 +1 0 - * 8:3 tFAW 20 Clk - * 10:9 tMOD DDR3 Only 15 - * 11 tRTODT DDR3 Only 0 - * 15:12 Reserved - * 23:16 tRFC 160ns 64 ref 131 - * 26:24 tDQSCK LPDDR2 only 1 - * 29:27 tDQSCKmax 1 - * 31:30 Reserved - */ - write32_x(DDR_PHY + DDRPHY_DTPR1_OFFSET, 0x094006A0); - /* DTPR2 : DRAM Timing Params 2 - * 9:0 tXS exit SR def 512d - * 14:10 tXP PD Exit Del 8 5 - * 18:15 tCKE CKE Min pulse 5 - * 28:19 tDLLK DLL Lock time 512d - * 32:29 Reserved - */ - write32_x(DDR_PHY + DDRPHY_DTPR2_OFFSET, 0x10029600); - /* PTR0 : PHY Timing Params 0 - * 5:0 tDLLRST Def 27 - * 17:6 tDLLLOCK Def 2750 - * 21:18 tITMSRST Def 8 - * 31:22 Reserved 0 - */ - write32_x(DDR_PHY + DDRPHY_PTR0_OFFSET, 0x0022AF9B); - /* PTR1 : PHY Timing Params 1 - * 18:0 : tDINITO DRAM Init time 500us 200,000 Dec 0x30D40 - * 29:19 : tDINIT1 DRAM Init time tRFC + 10ns 68 - */ - write32_x(DDR_PHY + DDRPHY_PTR1_OFFSET, 0x02230D40); - /* DQS gating configuration: passive windowing mode */ - /* - * PGCR: PHY General cofiguration register - * 0 ITM DDR mode: 0 - * 1 DQS gading configuration: passive windowing 1 - * 2 DQS drift compensation: not supported in passive windowing 0 - * 4:3 DQS drift limit 0 - * 8:5 Digital test output select 0 - * 11:9 CK Enable: one bit for each 3 CK pair: 0x7 - * 13:12 CK Disable values: 0x2 - * 14 CK Invert 0 - * 15 IO loopback 0 - * 17:16 I/O DDR mode 0 - * 21:18 Ranks enable by training: 0xF - * 23:22 Impedance clock divider select 0x2 - * 24 Power down disable 1 - * 28:25 Refresh during training 0 - * 29 loopback DQS shift 0 - * 30 loopback DQS gating 0 - * 31 loopback mode 0 - */ - write32_x(DDR_PHY + DDRPHY_PGCR_OFFSET, 0x01BC2E02); - - /* PGSR : Wait for INIT/DLL/Z Done from Power on Reset */ - if (wait_for_completion(DDR_PHY + DDRPHY_PGSR_OFFSET, 0x00000007)) - return DDR_TIMEOUT; - /* PIR : PHY controlled init */ - write32_x(DDR_PHY + DDRPHY_PIR_OFFSET, 0x0000001F); - /* PGSR : Wait for DRAM Init Done */ - if (wait_for_completion(DDR_PHY + DDRPHY_PGSR_OFFSET, 0x00000007)) - return DDR_TIMEOUT; - /* PIR : controller DRAM initialization */ - write32_x(DDR_PHY + DDRPHY_PIR_OFFSET, 0x00040001); - /* PGSR : Wait for DRAM Init Done */ - if (wait_for_completion(DDR_PHY + DDRPHY_PGSR_OFFSET, 0x0000000F)) - return DDR_TIMEOUT; - /********************************************************************/ - /* DF1STAT0 : wait for DFI_INIT_COMPLETE */ - if (wait_for_completion(DDR_PCTL + DDR_PCTL_DFISTAT0_OFFSET, - 0x00000001)) - return DDR_TIMEOUT; - /* POWCTL : Start the memory Power Up seq*/ - write32_x(DDR_PCTL + DDR_PCTL_POWCTL_OFFSET, 0x80000001); - /* POWSTAT : wait for POWER_UP_DONE */ - if (wait_for_completion(DDR_PCTL + DDR_PCTL_POWSTAT_OFFSET, - 0x00000001)) - return DDR_TIMEOUT; - /* - * TREFI : t_refi Timing Register 1X - * 12:0 t_refi 7.8us in 100ns 0x4E - * 15:13 Reserved 0 - * 18:16 num_add_ref 0 - * 30:19 Reserved 0 - * 31 Update 1 - */ - write32_x(DDR_PCTL + DDR_PCTL_TREFI_OFFSET, 0x8000004E); - /* TMRD : t_mrd Timing Register -- Range 2 to 4*/ - write32_x(DDR_PCTL + DDR_PCTL_TMRD_OFFSET, 0x00000004); - /* - * TRFC : t_rfc Timing Register -- Range 15 to 131 - * 195ns / 2.5ns 78 x4E - */ - write32_x(DDR_PCTL + DDR_PCTL_TRFC_OFFSET, 0x0000004E); - /* TRP : t_rp Timing Register -- Range 3 to 7 - * 4:0 tRP 12.5 / 2.5 = 5 6 For Now 6-6-6 - * 17:16 rpea_extra DDR3 - value 0 - */ - write32_x(DDR_PCTL + DDR_PCTL_TRP_OFFSET, 0x00000006); - /* TAL : Additive Latency Register -- AL in MR1 */ - write32_x(DDR_PCTL + DDR_PCTL_TAL_OFFSET, 0x00000000); - /* TCL : CAS Latency Timing Register -- CASL in MR0 6-6-6 */ - write32_x(DDR_PCTL + DDR_PCTL_TCL_OFFSET, 0x00000006); - /* TCWL : CAS Write Latency Register --CASL-1 */ - write32_x(DDR_PCTL + DDR_PCTL_TCWL_OFFSET, 0x00000005); - /* TRAS : Activate to Precharge cmd time 15 45ns / 2.5ns = 18d */ - write32_x(DDR_PCTL + DDR_PCTL_TRAS_OFFSET, 0x0000000F); - /* TRC : Min. ROW cycle time 21 - * 57.5ns / 2.5ns = 23d Playing safe 24 - */ - write32_x(DDR_PCTL + DDR_PCTL_TRC_OFFSET, 0x00000015); - /* TRCD : Row to Column Delay # Range 3 to 7 (TCL = TRCD) - * 12.5ns / 2.5ns = 5 but running 6-6-6 6 - */ - write32_x(DDR_PCTL + DDR_PCTL_TRCD_OFFSET, 0x00000006); - /* TRRD : Row to Row delay -- Range 2 to 6 - * 2K Page 10ns / 2.5ns = 4 - */ - write32_x(DDR_PCTL + DDR_PCTL_TRRD_OFFSET, 0x00000004); - /* TRTP : Read to Precharge time -- Range 2 to 4 - * Largest 4 or 7.5ns / 2.5ns = 4 - */ - write32_x(DDR_PCTL + DDR_PCTL_TRTP_OFFSET, 0x00000004); - /* TWR : Write recovery time -- WR in MR0: 15ns / 2.5ns = 6 */ - write32_x(DDR_PCTL + DDR_PCTL_TWR_OFFSET, 0x00000006); - /* TWTR : Write to read turn around time -- Range 2 to 4 - * Largest 4 or 7.5ns / 2.5ns = 4 - */ - write32_x(DDR_PCTL + DDR_PCTL_TWTR_OFFSET, 0x00000004); - /* TEXSR : Exit Self Refresh to first valid cmd: tXS 512 */ - write32_x(DDR_PCTL + DDR_PCTL_TEXSR_OFFSET, 0x00000200); - /* TXP : Exit Power Down to first valid cmd - * tXP 2, Settingto 3 to match PHY - */ - write32_x(DDR_PCTL + DDR_PCTL_TXP_OFFSET, 0x00000003); - /* TDQS : t_dqs Timing Register - * DQS additional turn around Rank 2 Rank (1 Rank) Def 1 - */ - write32_x(DDR_PCTL + DDR_PCTL_TDQS_OFFSET, 0x00000001); - /* TRTW : Read to Write turn around time Def 3 - * Actual gap t_bl + t_rtw - */ - write32_x(DDR_PCTL + DDR_PCTL_TRTW_OFFSET, 0x00000003); - /* TCKE : CKE min pulse width DEf 3 */ - write32_x(DDR_PCTL + DDR_PCTL_TCKE_OFFSET, 0x00000003); - /* TXPDLL : Slow Exit Power Down to first valid cmd delay - * tXARDS 10+AL = 10 - */ - write32_x(DDR_PCTL + DDR_PCTL_TXPDLL_OFFSET, 0x0000000A); - /* TCKESR : Min CKE Low width for Self refresh entry to exit - * t_ckesr = 0 DDR2 - */ - write32_x(DDR_PCTL + DDR_PCTL_TCKESR_OFFSET, 0x00000004); - /* TMOD : MRS to any Non-MRS command -- Range 0 to 31 */ - write32_x(DDR_PCTL + DDR_PCTL_TMOD_OFFSET, 0x0000000F); - /* TZQCS : SDRAM ZQ Calibration Short Period */ - write32_x(DDR_PCTL + DDR_PCTL_TZQCS_OFFSET, 0x00000040); - /* TZQCL : SDRAM ZQ Calibration Long Period */ - write32_x(DDR_PCTL + DDR_PCTL_TZQCL_OFFSET, 0x00000200); - /* SCFG : State Configuration Register (Enabling Self Refresh) - * 0 LP_en Leave Off for Bring Up 0 - * 5:1 Reserved - * 6 Synopsys Internal Only 0 - * 7 Enale PHY indication of LP Opportunity 1 - * 11:8 bbflags_timing max UPCTL_TCU_SED_P - tRP (16 - 6) Use 4 - * 16:12 Additional delay on accertion of ac_pdd 4 - * 31:17 Reserved - */ - write32_x(DDR_PCTL + DDR_PCTL_SCFG_OFFSET, 0x00004480); - /* TREFI_MEM_DDR3 */ - write32_x(DDR_PCTL + DDR_PCTL_TREFI_MEM_DDR3_OFFSET, 0x00000C30); - - /* DFITPHYWRLAT : Write cmd to dfi_wrdata_en */ - write32_x(DDR_PCTL + DDR_PCTL_DFIWRLAT_OFFSET, 0x00000002); - /* DFITRDDATAEN : Read cmd to dfi_rddata_en */ - write32_x(DDR_PCTL + DDR_PCTL_DFITRDDATAEN_OFFSET, 0x00000002); - /* - * DFITPHYWRDATA : dfi_wrdata_en to drive wr data - * DFI Clks wrdata_en to wrdata Def 1 - */ - write32_x(DDR_PCTL + DDR_PCTL_DFITPHYWRDATA_OFFSET, 0x00000000); - /* - * DFITPHYRDLAT : dfi_rddata_en to dfi_rddata_valid - * DFI clks max rddata_en to rddata_valid Def 15 - */ - write32_x(DDR_PCTL + DDR_PCTL_DFITPHYRDLAT_OFFSET, 0x00000008); - /* DFISTCFG0 : Drive various DFI signals appropriately - * 0 dfi_init_start 1 - * 1 dfi_freq_ratio_en 1 - * 2 dfi_data_byte_disable_en 1 - */ - write32_x(DDR_PCTL + DDR_PCTL_DFISTCFG0_OFFSET, 0x00000007); - /* DFISTCFG1 : Enable various DFI support - * 0 dfi_dram_clk_disable_en 1 - * 1 dfi_dram_clk_disable_en_pdp only lPDDR 0 - */ - write32_x(DDR_PCTL + DDR_PCTL_DFISTCFG1_OFFSET, 0x00000001); - /* DFISTCFG2 : Enable Parity and asoc interrupt - * 0 dfi_parity_in Enable 1 - * 1 Interrupt on dfi_parity_error 1 - */ - write32_x(DDR_PCTL + DDR_PCTL_DFISTCFG2_OFFSET, 0x00000003); - /* DFILPCFG0 : DFI Low Power Interface Configuration - * 0 Enable DFI LP IF during PD 1 - * 3:1 Reserved - * 7:4 DFI tlp_wakeup time 0 - * 8 Enable DFI LP IF during SR 1 - * 11:9 Reserved - * 15:12 dfi_lp_wakeup in SR 0 - * 19:16 tlp_resp DFI 2.1 recomend 7 - * 23:20 Reserved - * 24 Enable DFI LP in Deep Power Down 0 - * 27:25 Reserved - * 31:28 DFI LP Deep Power Down Value 0 - */ - write32_x(DDR_PCTL + DDR_PCTL_DFILPCFG0_OFFSET, 0x00070101); - /* DFIODTCFG : DFI ODT Configuration - * Only Enabled on Rank0 Writes - * 0 rank0_odt_read_nsel 0 - * 1 rank0_odt_read_sel 0 - * 2 rank0_odt_write_nsel 0 - * 3 rank0_odt_write_sel 1 - */ - write32_x(DDR_PCTL + DDR_PCTL_DFIODTCFG_OFFSET, 0x00000008); - /* DFIODTCFG1 : DFI ODT Configuration - * 4:0 odt_lat_w 0 - * 12:8 odt_lat_r 0 Def - * 4:0 odt_len_bl8_w 6 Def - * 12:8 odt_len_bl8_r 6 Def - */ - write32_x(DDR_PCTL + DDR_PCTL_DFIODTCFG1_OFFSET, 0x060600000); - - /* Memory initialization */ - /* MCMD : PREA, Addr 0 Bank 0 Rank 0 Del 0 - * 3:0 cmd_opcode PREA 00001 - * 16:4 cmd_addr 0 - * 19:17 bank_addr 0 - * 23:20 rank_sel 0 0001 - * 27:24 cmddelay 0 - * 30:24 Reserved - */ - /* MCMD: MR2 */ - write32_x(DDR_PCTL + DDR_PCTL_MCMD_OFFSET, 0x80004403); - /* MRS cmd wait for completion */ - if (wait_for_completion(DDR_PCTL + DDR_PCTL_MCMD_OFFSET, 0x00004403)) - return DDR_TIMEOUT; - /* MCMD: MR3 */ - write32_x(DDR_PCTL + DDR_PCTL_MCMD_OFFSET, 0x80000003); - /* MRS cmd wait for completion */ - if (wait_for_completion(DDR_PCTL + DDR_PCTL_MCMD_OFFSET, 0x00000003)) - return DDR_TIMEOUT; - /* MCMD: MR1 */ - write32_x(DDR_PCTL + DDR_PCTL_MCMD_OFFSET, 0x80000043); - /* MRS cmd wait for completion */ - if (wait_for_completion(DDR_PCTL + DDR_PCTL_MCMD_OFFSET, 0x00000043)) - return DDR_TIMEOUT; - /* MCMD: MR0 */ - write32_x(DDR_PCTL + DDR_PCTL_MCMD_OFFSET, 0x80015203); - /* MRS cmd wait for completion */ - if (wait_for_completion(DDR_PCTL + DDR_PCTL_MCMD_OFFSET, 0x00015203)) - return DDR_TIMEOUT; - /* MCMD: ZQS cmd, long 5 short 4 */ - write32_x(DDR_PCTL + DDR_PCTL_MCMD_OFFSET, 0x80104005); - /* MRS cmd wait for completion */ - if (wait_for_completion(DDR_PCTL + DDR_PCTL_MCMD_OFFSET, 0x00104005)) - return DDR_TIMEOUT; - /* MCMD: deselect command */ - write32_x(DDR_PCTL + DDR_PCTL_MCMD_OFFSET, 0x80100000); - /* MRS cmd wait for completion */ - if (wait_for_completion(DDR_PCTL + DDR_PCTL_MCMD_OFFSET, 0x00100000)) - return DDR_TIMEOUT; - /* MCMD: deselect command */ - write32_x(DDR_PCTL + DDR_PCTL_MCMD_OFFSET, 0x8010000A); - /* MRS cmd wait for completion */ - if (wait_for_completion(DDR_PCTL + DDR_PCTL_MCMD_OFFSET, 0x0010000A)) - return DDR_TIMEOUT; - - /* DCFG : DRAM Density 256 Mb 16 Bit IO Width - * 1:0 Devicw Width 1 x8, 2 x16, 3 x32 2 - * 5:2 Density 2Gb = 5 - * 6 Dram Type (MDDR/LPDDR2) Only 0 - * 7 Reserved 0 - * 10:8 Address Map R/B/C = 1 - * 31:11 Reserved - */ - write32_x(DDR_PCTL + DDR_PCTL_DCFG_OFFSET, 0x00000116); - /* PCFG_0 : Port 0 AXI config */ - write32_x(DDR_PCTL + DDR_PCTL_PCFG0_OFFSET, 0x000800A0); - /* SCTL : UPCTL switch INIT CONFIG State */ - write32_x(DDR_PCTL + DDR_PCTL_SCTL_OFFSET, 0x00000001); - /* STAT : Wait for Switch INIT to Config State */ - if (wait_for_completion(DDR_PCTL + DDR_PCTL_STAT_OFFSET, 0x00000001)) - return DDR_TIMEOUT; - /* STAT : Wait for Switch INIT to Config State */ - write32_x(DDR_PCTL + DDR_PCTL_CMDTSTATEN_OFFSET, 0x00000001); - /* STAT : Wait for Switch INIT to Config State */ - if (wait_for_completion(DDR_PCTL + DDR_PCTL_CMDTSTAT_OFFSET, - 0x00000001)) - return DDR_TIMEOUT; - /* Use PHY for DRAM init */ - write32_x(DDR_PHY + DDRPHY_PIR_OFFSET, 0x00000181); - /* STAT : Wait for Switch INIT to Config State */ - if (wait_for_completion(DDR_PHY + DDRPHY_PGSR_OFFSET, 0x00000001F)) - return DDR_TIMEOUT; - /* Disable Impedance Calibration */ - write32_x(DDR_PHY + DDRPHY_ZQ0CR0_OFFSET, 0x3000014A); - write32_x(DDR_PHY + DDRPHY_ZQ1CR0_OFFSET, 0x3000014A); - - /* SCTL : UPCTL switch Config to ACCESS State */ - write32_x(DDR_PCTL + DDR_PCTL_SCTL_OFFSET, 0x00000002); - /* STAT : Wait for switch CFG -> GO State */ - if (wait_for_completion(DDR_PCTL + DDR_PCTL_STAT_OFFSET, 0x3)) - return DDR_TIMEOUT; - - return 0; -} diff --git a/src/soc/imgtec/pistachio/include/soc/clocks.h b/src/soc/imgtec/pistachio/include/soc/clocks.h deleted file mode 100644 index 27ba6d6c20..0000000000 --- a/src/soc/imgtec/pistachio/include/soc/clocks.h +++ /dev/null @@ -1,43 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2014 Imagination Technologies - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ - -#ifndef __SOC_IMGTEC_PISTACHIO_CLOCKS_H__ -#define __SOC_IMGTEC_PISTACHIO_CLOCKS_H__ - -#include - -/* Functions for PLL setting */ -int sys_pll_setup(u8 divider1, u8 divider2, u8 predivider, u32 feedback); -int mips_pll_setup(u8 divider1, u8 divider2, u8 predivider, u32 feedback); - -/* Peripheral divider setting */ -void system_clk_setup(u8 divider); -void mips_clk_setup(u8 divider1, u8 divider2); -void uart1_clk_setup(u8 divider1, u16 divider2); -void i2c_clk_setup(u8 divider1, u16 divider2, u8 interface); -int usb_clk_setup(u8 divider, u8 refclksel, u8 fsel); -void rom_clk_setup(u8 divider); -void eth_clk_setup(u8 mux, u8 divider); -void setup_clk_gate_defaults(void); -enum { - CLOCKS_OK = 0, - PLL_TIMEOUT = -1, - USB_TIMEOUT = -2, - USB_VBUS_FAULT = -3 -}; - -#endif diff --git a/src/soc/imgtec/pistachio/include/soc/cpu.h b/src/soc/imgtec/pistachio/include/soc/cpu.h deleted file mode 100644 index c22dceba45..0000000000 --- a/src/soc/imgtec/pistachio/include/soc/cpu.h +++ /dev/null @@ -1,35 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2014 Imagination Technologies - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ - -#ifndef __SOC_IMGTEC_DANUBE_CPU_H__ -#define __SOC_IMGTEC_DANUBE_CPU_H__ - -#include - -#define IMG_SPIM0_BASE_ADDRESS 0xB8100F00 -#define IMG_SPIM1_BASE_ADDRESS 0xB8101000 - -/* - * This register holds the FPGA image version - * If we're not working on the FPGA this will be 0 - */ -#define PRIMARY_FPGA_VERSION 0xB8149060 -#define IMG_PLATFORM_ID() read32_x(PRIMARY_FPGA_VERSION) -#define IMG_PLATFORM_ID_FPGA 0xD1400003 /* Last FPGA image */ -#define IMG_PLATFORM_ID_SILICON 0 - -#endif diff --git a/src/soc/imgtec/pistachio/include/soc/ddr_init.h b/src/soc/imgtec/pistachio/include/soc/ddr_init.h deleted file mode 100644 index d8b5b19bae..0000000000 --- a/src/soc/imgtec/pistachio/include/soc/ddr_init.h +++ /dev/null @@ -1,26 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2014 Imagination Technologies - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ - -#ifndef __SOC_IMGTEC_PISTACHIO_DDR_INIT_H__ -#define __SOC_IMGTEC_PISTACHIO_DDR_INIT_H__ - -#define DDR_TIMEOUT -1 - -int init_ddr2(void); -int init_ddr3(void); - -#endif diff --git a/src/soc/imgtec/pistachio/include/soc/ddr_private_reg.h b/src/soc/imgtec/pistachio/include/soc/ddr_private_reg.h deleted file mode 100644 index eab5b3a142..0000000000 --- a/src/soc/imgtec/pistachio/include/soc/ddr_private_reg.h +++ /dev/null @@ -1,142 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2014 Imagination Technologies - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ - -#ifndef __SOC_IMGTEC_PISTACHIO_DDR_PRIVATE_REG_H__ -#define __SOC_IMGTEC_PISTACHIO_DDR_PRIVATE_REG_H__ - -#include -#include - -#define MAX_WAIT_MICROS 100000 - -#define TOPLEVEL_REGS 0xB8149000 - -#define DDR_CTRL_OFFSET (0x0020) -#define DDR_CLK_EN_MASK (0x00000002) -#define DDR_CLK_EN_SHIFT (1) -#define DDR_CLK_EN_LENGTH (1) - -#define DDR_PCTL 0xB8180000 -#define DDR_PCTL_SCFG_OFFSET (0x0000) -#define DDR_PCTL_SCTL_OFFSET (0x0004) -#define DDR_PCTL_STAT_OFFSET (0x0008) -#define DDR_PCTL_MCMD_OFFSET (0x0040) -#define DDR_PCTL_POWCTL_OFFSET (0x0044) -#define DDR_PCTL_POWSTAT_OFFSET (0x0048) -#define DDR_PCTL_CMDTSTAT_OFFSET (0x004C) -#define DDR_PCTL_CMDTSTATEN_OFFSET (0x0050) -#define DDR_PCTL_MCFG1_OFFSET (0x007C) -#define DDR_PCTL_MCFG_OFFSET (0x0080) -#define DDR_PCTL_MSTAT_OFFSET (0x0088) -#define DDR_PCTL_DTUAWDT_OFFSET (0x00B0) -#define DDR_PCTL_TOGCNT1U_OFFSET (0x00C0) -#define DDR_PCTL_TINIT_OFFSET (0x00C4) -#define DDR_PCTL_TRSTH_OFFSET (0x00C8) -#define DDR_PCTL_TOGG_CNTR_100NS_OFFSET (0x00CC) -#define DDR_PCTL_TREFI_OFFSET (0x00D0) -#define DDR_PCTL_TMRD_OFFSET (0x00D4) -#define DDR_PCTL_TRFC_OFFSET (0x00D8) -#define DDR_PCTL_TRP_OFFSET (0x00DC) -#define DDR_PCTL_TRTW_OFFSET (0x00E0) -#define DDR_PCTL_TAL_OFFSET (0x00E4) -#define DDR_PCTL_TCL_OFFSET (0x00E8) -#define DDR_PCTL_TCWL_OFFSET (0x00EC) -#define DDR_PCTL_TRAS_OFFSET (0x00F0) -#define DDR_PCTL_TRC_OFFSET (0x00F4) -#define DDR_PCTL_TRCD_OFFSET (0x00F8) -#define DDR_PCTL_TRRD_OFFSET (0x00FC) -#define DDR_PCTL_TRTP_OFFSET (0x0100) -#define DDR_PCTL_TWR_OFFSET (0x0104) -#define DDR_PCTL_TWTR_OFFSET (0x0108) -#define DDR_PCTL_TEXSR_OFFSET (0x010C) -#define DDR_PCTL_TXP_OFFSET (0x0110) -#define DDR_PCTL_TXPDLL_OFFSET (0x0114) -#define DDR_PCTL_TZQCS_OFFSET (0x0118) -#define DDR_PCTL_TDQS_OFFSET (0x0120) -#define DDR_PCTL_TCKE_OFFSET (0x012C) -#define DDR_PCTL_TMOD_OFFSET (0x0130) -#define DDR_PCTL_TZQCL_OFFSET (0x0138) -#define DDR_PCTL_TCKESR_OFFSET (0x0140) -#define DDR_PCTL_TREFI_MEM_DDR3_OFFSET (0x0148) -#define DDR_PCTL_DTUWACTL_OFFSET (0x0200) -#define DDR_PCTL_DTURACTL_OFFSET (0x0204) -#define DDR_PCTL_DTUCFG_OFFSET (0x0208) -#define DDR_PCTL_DTUECTL_OFFSET (0x020C) -#define DDR_PCTL_DTUWD0_OFFSET (0x0210) -#define DDR_PCTL_DTUWD1_OFFSET (0x0214) -#define DDR_PCTL_DTUWD2_OFFSET (0x0218) -#define DDR_PCTL_DTUWD3_OFFSET (0x021C) -#define DDR_PCTL_DFIODTCFG_OFFSET (0x0244) -#define DDR_PCTL_DFIODTCFG1_OFFSET (0x0248) -#define DDR_PCTL_DFITPHYWRDATA_OFFSET (0x0250) -#define DDR_PCTL_DFIWRLAT_OFFSET (0x0254) -#define DDR_PCTL_DFITRDDATAEN_OFFSET (0x0260) -#define DDR_PCTL_DFITPHYRDLAT_OFFSET (0x0264) -#define DDR_PCTL_DFIUPDCFG_OFFSET (0x0290) -#define DDR_PCTL_DFISTAT0_OFFSET (0x02C0) -#define DDR_PCTL_DFISTCFG0_OFFSET (0x02C4) -#define DDR_PCTL_DFISTCFG1_OFFSET (0x02C8) -#define DDR_PCTL_DFISTCFG2_OFFSET (0x02D8) -#define DDR_PCTL_DFILPCFG0_OFFSET (0x02F0) -#define DDR_PCTL_PCFG0_OFFSET (0x0400) -#define DDR_PCTL_CCFG_OFFSET (0x0480) -#define DDR_PCTL_DCFG_OFFSET (0x0484) -#define DDR_PCTL_CCFG1_OFFSET (0x048C) - -#define DDR_PHY 0xB8180800 -#define DDRPHY_PIR_OFFSET (0x0004) -#define DDRPHY_PGCR_OFFSET (0x0008) -#define DDRPHY_PGSR_OFFSET (0x000C) -#define DDRPHY_DLLGCR_OFFSET (0x0010) -#define DDRPHY_PTR0_OFFSET (0x0018) -#define DDRPHY_PTR1_OFFSET (0x001C) -#define DDRPHY_DXCCR_OFFSET (0x0028) -#define DDRPHY_DSGCR_OFFSET (0x002C) -#define DDRPHY_DCR_OFFSET (0x0030) -#define DDRPHY_DTPR0_OFFSET (0x0034) -#define DDRPHY_DTPR1_OFFSET (0x0038) -#define DDRPHY_DTPR2_OFFSET (0x003C) -#define DDRPHY_MR_OFFSET (0x0040) -#define DDRPHY_EMR_OFFSET (0x0044) -#define DDRPHY_EMR2_OFFSET (0x0048) -#define DDRPHY_EMR3_OFFSET (0x004C) -#define DDRPHY_DTAR_OFFSET (0x0054) -#define DDRPHY_BISTRR_OFFSET (0x0100) -#define DDRPHY_BISTWCR_OFFSET (0x010C) -#define DDRPHY_BISTAR0_OFFSET (0x0114) -#define DDRPHY_BISTAR1_OFFSET (0x0118) -#define DDRPHY_BISTAR2_OFFSET (0x011C) -#define DDRPHY_BISTUDPR_OFFSET (0x0120) -#define DDRPHY_BISTGSR_OFFSET (0x0124) -#define DDRPHY_ZQ0CR0_OFFSET (0x0180) -#define DDRPHY_ZQ1CR0_OFFSET (0x0190) - -#define DDR_TIMEOUT_VALUE_US 100000 - -static int wait_for_completion(u32 reg, u32 exp_val) -{ - struct stopwatch sw; - - stopwatch_init_usecs_expire(&sw, DDR_TIMEOUT_VALUE_US); - while (read32_x(reg) != exp_val) { - if (stopwatch_expired(&sw)) - return DDR_TIMEOUT; - } - return 0; -} - -#endif diff --git a/src/soc/imgtec/pistachio/include/soc/gpio.h b/src/soc/imgtec/pistachio/include/soc/gpio.h deleted file mode 100644 index 64f2e27c8b..0000000000 --- a/src/soc/imgtec/pistachio/include/soc/gpio.h +++ /dev/null @@ -1,21 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright 2014 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef __SOC_IMGTECH_PISTACHIO_GPIO_H__ -#define __SOC_IMGTECH_PISTACHIO_GPIO_H__ - -typedef unsigned int gpio_t; - -#endif // __SOC_IMGTECH_PISTACHIO_GPIO_H__ diff --git a/src/soc/imgtec/pistachio/include/soc/memlayout.ld b/src/soc/imgtec/pistachio/include/soc/memlayout.ld deleted file mode 100644 index cd81093fab..0000000000 --- a/src/soc/imgtec/pistachio/include/soc/memlayout.ld +++ /dev/null @@ -1,70 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright 2014 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include - -#include - -/* SRAM memory is mapped in two different locations. Define regions in both for - * full overlap checking and use this to guarantee they're kept in sync. */ -#define ASSERT_MIRRORED(r1, r2) \ - _ = ASSERT((_e##r1 - _##r1) == (_e##r2 - _##r2) && \ - (_##r1 & 0x7fffffff) == (_##r2 & 0x7fffffff), \ - STR(r1 and r2 do not match!)); - -SECTIONS -{ - /* - * All of DRAM (other than the DMA coherent area) is accessed through - * the identity mapping. - */ - DRAM_START(0x00000000) - /* DMA coherent area: accessed via KSEG1. */ - DMA_COHERENT(0x00100000, 1M) - POSTRAM_CBFS_CACHE(0x00200000, 512K) - RAMSTAGE(0x00280000, 128K) - - /* 0x18100000 -> 0x18540000 */ - SOC_REGISTERS(0x18100000, 0x440000) - /* - * GRAM becomes the SRAM. Accessed through KSEG0 in the bootblock - * and then through the identity mapping in ROM stage. - */ - SRAM_START(0x1a000000) - REGION(gram_bootblock, 0x1a000000, 28K, 1) - ROMSTAGE(0x1a007000, 60K) - VBOOT2_WORK(0x1a016000, 12K) - VBOOT2_TPM_LOG(0x1a019000, 2K) - PRERAM_CBFS_CACHE(0x1a019800, 46K) - SRAM_END(0x1a066000) - - /* Bootblock executes out of KSEG0 and sets up the identity mapping. - * This is identical to SRAM above, and thus also limited 64K and - * needs to avoid conflicts with items set up above. - */ - BOOTBLOCK(0x9a000000, 28K) - REGION(kseg0_romstage, 0x9a007000, 60K, 1) - - /* - * Let's use SRAM for stack and CBMEM console. Always accessed - * through KSEG0. - */ - STACK(0x9b000000, 8K) - PRERAM_CBMEM_CONSOLE(0x9b002000, 8K) - -} - -ASSERT_MIRRORED(bootblock, gram_bootblock) -ASSERT_MIRRORED(romstage, kseg0_romstage) diff --git a/src/soc/imgtec/pistachio/include/soc/spi.h b/src/soc/imgtec/pistachio/include/soc/spi.h deleted file mode 100644 index f23cca5821..0000000000 --- a/src/soc/imgtec/pistachio/include/soc/spi.h +++ /dev/null @@ -1,357 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2014 Imagination Technologies - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - - -#ifndef __SOC_IMGTEC_DANUBE_SPI_H__ -#define __SOC_IMGTEC_DANUBE_SPI_H__ - -#include - -#define spi_read_reg_field(regval, field) \ -( \ - ((field##_MASK) == 0xFFFFFFFF) ? \ - (regval) : \ - (((regval) & (field##_MASK)) >> (field##_SHIFT))\ -) - -#define spi_write_reg_field(regval, field, val) \ -( \ - ((field##_MASK) == 0xFFFFFFFF) ? \ - (val) : \ - (((regval) & ~(field##_MASK)) | \ - (((val) << (field##_SHIFT)) & (field##_MASK))) \ -) - -/* - * Parameter register - * Each of these corresponds to a single port (ie CS line) in the interface - * Fields Name Description - * ====== ==== =========== - * b31:24 CLK_RATE Bit Clock rate = (24.576 * value / 512) MHz - * b23:16 CS_SETUP Chip Select setup = (40 * value) ns - * b15:8 CS_HOLD Chip Select hold = (40 * value) ns - * b7:0 CS_DELAY Chip Select delay = (40 * value) ns - */ - -#define SPIM_CLK_DIVIDE_MASK (0xFF000000) -#define SPIM_CS_SETUP_MASK (0x00FF0000) -#define SPIM_CS_HOLD_MASK (0x0000FF00) -#define SPIM_CS_DELAY_MASK (0x000000FF) -#define SPIM_CS_PARAM_MASK (SPIM_CS_SETUP_MASK \ - | SPIM_CS_HOLD_MASK \ - | SPIM_CS_DELAY_MASK) - -#define SPIM_CLK_DIVIDE_SHIFT (24) -#define SPIM_CS_SETUP_SHIFT (16) -#define SPIM_CS_HOLD_SHIFT (8) -#define SPIM_CS_DELAY_SHIFT (0) -#define SPIM_CS_PARAM_SHIFT (0) - -/* Control register */ - -#define SPFI_DRIBBLE_COUNT_MASK (0x000e0000) -#define SPFI_MEMORY_IF_MASK (0x00008000) -#define SPIM_BYTE_DELAY_MASK (0x00004000) -#define SPIM_CS_DEASSERT_MASK (0x00002000) -#define SPIM_CONTINUE_MASK (0x00001000) -#define SPIM_SOFT_RESET_MASK (0x00000800) -#define SPIM_SEND_DMA_MASK (0x00000400) -#define SPIM_GET_DMA_MASK (0x00000200) -#define SPIM_EDGE_TX_RX_MASK (0x00000100) -#define SPFI_TRNSFR_MODE_MASK (0x000000e0) -#define SPFI_TRNSFR_MODE_DQ_MASK (0x0000001c) -#define SPFI_TX_RX_MASK (0x00000002) -#define SPFI_EN_MASK (0x00000001) - -#define SPFI_DRIBBLE_COUNT_SHIFT (17) -#define SPFI_MEMORY_IF_SHIFT (15) -#define SPIM_BYTE_DELAY_SHIFT (14) -#define SPIM_CS_DEASSERT_SHIFT (13) -#define SPIM_CONTINUE_SHIFT (12) -#define SPIM_SOFT_RESET_SHIFT (11) -#define SPIM_SEND_DMA_SHIFT (10) -#define SPIM_GET_DMA_SHIFT (9) -#define SPIM_EDGE_TX_RX_SHIFT (8) -#define SPFI_TRNSFR_MODE_SHIFT (5) -#define SPFI_TRNSFR_MODE_DQ_SHIFT (2) -#define SPFI_TX_RX_SHIFT (1) -#define SPFI_EN_SHIFT (0) - -/* Transaction register */ - -#define SPFI_TSIZE_MASK (0xffff0000) -#define SPFI_CMD_LENGTH_MASK (0x0000e000) -#define SPFI_ADDR_LENGTH_MASK (0x00001c00) -#define SPFI_DUMMY_LENGTH_MASK (0x000003e0) -#define SPFI_PI_LENGTH_MASK (0x0000001c) - -#define SPFI_TSIZE_SHIFT (16) -#define SPFI_CMD_LENGTH_SHIFT (13) -#define SPFI_ADDR_LENGTH_SHIFT (10) -#define SPFI_DUMMY_LENGTH_SHIFT (5) -#define SPFI_PI_LENGTH_SHIFT (2) - -/* Port state register */ - -#define SPFI_PORT_SELECT_MASK (0x00700000) -/* WARNING the following bits are reversed */ -#define SPFI_CLOCK0_IDLE_MASK (0x000f8000) -#define SPFI_CLOCK0_PHASE_MASK (0x00007c00) -#define SPFI_CS0_IDLE_MASK (0x000003e0) -#define SPFI_DATA0_IDLE_MASK (0x0000001f) - -#define SPIM_CLOCK0_IDLE_MASK (0x000f8000) -#define SPIM_CLOCK0_PHASE_MASK (0x00007c00) -#define SPIM_CS0_IDLE_MASK (0x000003e0) -#define SPIM_DATA0_IDLE_MASK (0x0000001f) - -#define SPIM_PORT0_MASK (0x00084210) - -#define SPFI_PORT_SELECT_SHIFT (20) -/* WARNING the following bits are reversed, bit 0 is highest */ -#define SPFI_CLOCK0_IDLE_SHIFT (19) -#define SPFI_CLOCK0_PHASE_SHIFT (14) -#define SPFI_CS0_IDLE_SHIFT (9) -#define SPFI_DATA0_IDLE_SHIFT (4) - -#define SPIM_CLOCK0_IDLE_SHIFT (19) -#define SPIM_CLOCK0_PHASE_SHIFT (14) -#define SPIM_CS0_IDLE_SHIFT (9) -#define SPIM_DATA0_IDLE_SHIFT (4) - - -/* - * Interrupt registers - * SPFI_GDOF_MASK means Rx buffer full, not an overflow, because clock stalls - * SPFI_SDUF_MASK means Tx buffer empty, not an underflow, because clock stalls - */ -#define SPFI_IACCESS_MASK (0x00001000) -#define SPFI_GDEX8BIT_MASK (0x00000800) -#define SPFI_ALLDONE_MASK (0x00000200) -#define SPFI_GDFUL_MASK (0x00000100) -#define SPFI_GDHF_MASK (0x00000080) -#define SPFI_GDEX32BIT_MASK (0x00000040) -#define SPFI_GDTRIG_MASK (0x00000020) -#define SPFI_SDFUL_MASK (0x00000008) -#define SPFI_SDHF_MASK (0x00000004) -#define SPFI_SDE_MASK (0x00000002) -#define SPFI_SDTRIG_MASK (0x00000001) - -#define SPFI_IACCESS_SHIFT (12) -#define SPFI_GDEX8BIT_SHIFT (11) -#define SPFI_ALLDONE_SHIFT (9) -#define SPFI_GDFUL_SHIFT (8) -#define SPFI_GDHF_SHIFT (7) -#define SPFI_GDEX32BIT_SHIFT (6) -#define SPFI_GDTRIG_SHIFT (5) -#define SPFI_SDFUL_SHIFT (3) -#define SPFI_SDHF_SHIFT (2) -#define SPFI_SDE_SHIFT (1) -#define SPFI_SDTRIG_SHIFT (0) - - -/* SPFI register block */ - -#define SPFI_PORT_0_PARAM_REG_OFFSET (0x00) -#define SPFI_PORT_1_PARAM_REG_OFFSET (0x04) -#define SPFI_PORT_2_PARAM_REG_OFFSET (0x08) -#define SPFI_PORT_3_PARAM_REG_OFFSET (0x0C) -#define SPFI_PORT_4_PARAM_REG_OFFSET (0x10) -#define SPFI_CONTROL_REG_OFFSET (0x14) -#define SPFI_TRANSACTION_REG_OFFSET (0x18) -#define SPFI_PORT_STATE_REG_OFFSET (0x1C) - -#define SPFI_SEND_LONG_REG_OFFSET (0x20) -#define SPFI_SEND_BYTE_REG_OFFSET (0x24) -#define SPFI_GET_LONG_REG_OFFSET (0x28) -#define SPFI_GET_BYTE_REG_OFFSET (0x2C) - -#define SPFI_INT_STATUS_REG_OFFSET (0x30) -#define SPFI_INT_ENABLE_REG_OFFSET (0x34) -#define SPFI_INT_CLEAR_REG_OFFSET (0x38) - -#define SPFI_IMMEDIATE_STATUS_REG_OFFSET (0x3c) - -#define SPFI_FLASH_BASE_ADDRESS_REG_OFFSET (0x48) -#define SPFI_FLASH_STATUS_REG_OFFSET (0x4C) - -#define IMG_FALSE 0 -#define IMG_TRUE 1 - -/* Number of SPIM interfaces*/ -#define SPIM_NUM_BLOCKS 2 -/* Number of chip select lines supported by the SPI master port. */ -#define SPIM_NUM_PORTS_PER_BLOCK (SPIM_DUMMY_CS) -/* Maximum transfer size (in bytes) for the SPI master port. */ -#define SPIM_MAX_TRANSFER_BYTES (0xFFFF) -/* Maximum size of a flash command: command bytes+address_bytes. */ -#define SPIM_MAX_FLASH_COMMAND_BYTES (0x8) -/* Write operation to fifo done in blocks of 16 words (64 bytes) */ -#define SPIM_MAX_BLOCK_BYTES (0x40) -/* Number of tries until timeout error is returned*/ -#define SPI_TIMEOUT_VALUE_US 500000 - -/* SPIM initialisation function return value.*/ -enum spim_return { - /* Initialisation parameters are valid. */ - SPIM_OK = 0, - /* Mode parameter is invalid. */ - SPIM_INVALID_SPI_MODE, - /* Chip select idle level is invalid. */ - SPIM_INVALID_CS_IDLE_LEVEL, - /* Data idle level is invalid. */ - SPIM_INVALID_DATA_IDLE_LEVEL, - /* Chip select line parameter is invalid. */ - SPIM_INVALID_CS_LINE, - /* Transfer size parameter is invalid. */ - SPIM_INVALID_SIZE, - /* Read/write parameter is invalid. */ - SPIM_INVALID_READ_WRITE, - /* Continue parameter is invalid. */ - SPIM_INVALID_CONTINUE, - /* Invalid block index */ - SPIM_INVALID_BLOCK_INDEX, - /* Extended error values */ - /* Invalid bit rate */ - SPIM_INVALID_BIT_RATE, - /* Invalid CS hold value */ - SPIM_INVALID_CS_HOLD_VALUE, - /* API function called before API is initialised */ - SPIM_API_NOT_INITIALISED, - /* SPI driver initialisation failed */ - SPIM_DRIVER_INIT_ERROR, - /* Invalid transfer description */ - SPIM_INVALID_TRANSFER_DESC, - /* Timeout */ - SPIM_TIMEOUT - -}; - -/* This type defines the SPI Mode.*/ -enum spim_mode { - /* Mode 0 (clock idle low, data valid on first clock transition). */ - SPIM_MODE_0 = 0, - /* Mode 1 (clock idle low, data valid on second clock transition). */ - SPIM_MODE_1, - /* Mode 2 (clock idle high, data valid on first clock transition). */ - SPIM_MODE_2, - /* Mode 3 (clock idle high, data valid on second clock transition). */ - SPIM_MODE_3 - -}; - -/* This type defines the SPIM device numbers (chip select lines). */ -enum spim_device { - /* Device 0 (CS0). */ - SPIM_DEVICE0 = 0, - /* Device 1 (CS1). */ - SPIM_DEVICE1, - /* Device 2 (CS2). */ - SPIM_DEVICE2, - /* Device 3 (CS3). */ - SPIM_DEVICE3, - /* Device 4 (CS4). */ - SPIM_DEVICE4, - /* Dummy chip select. */ - SPIM_DUMMY_CS - -}; - -/* This structure defines communication parameters for a slave device */ -struct spim_device_parameters { - /* Bit rate value.*/ - unsigned char bitrate; - /* - * Chip select set up time. - * Time taken between chip select going active and activity occurring - * on the clock, calculated by dividing the desired set up time in ns - * by the Input clock period. (setup time / Input clock freq) - */ - unsigned char cs_setup; - /* - * Chip select hold time. - * Time after the last clock pulse before chip select goes inactive, - * calculated by dividing the desired hold time in ns by the - * Input clock period (hold time / Input clock freq). - */ - unsigned char cs_hold; - /* - * Chip select delay time (CS minimum inactive time). - * Minimum time after chip select goes inactive before chip select - * can go active again, calculated by dividing the desired delay time - * in ns by the Input clock period (delay time / Input clock freq). - */ - unsigned char cs_delay; - /* SPI Mode. */ - enum spim_mode spi_mode; - /* Chip select idle level (0=low, 1=high, Others=invalid). */ - unsigned int cs_idle_level; - /* Data idle level (0=low, 1=high, Others=invalid). */ - unsigned int data_idle_level; - -}; - -/* Command transfer mode */ -enum command_mode { - /* Command, address, dummy and PI cycles are transferred on sio0 */ - SPIM_CMD_MODE_0 = 0, - /* - * Command and Address are transferred on sio0 port only but dummy - * cycles and PI is transferred on all the interface ports. - */ - SPIM_CMD_MODE_1, - /* - * Command is transferred on sio0 port only but address, dummy - * and PI is transferred on all the interface portS - */ - SPIM_CMD_MODE_2, - /* - * Command, address, dummy and PI bytes are transferred on all - * the interfaces - */ - SPIM_CMD_MODE_3 -}; - -/* Data transfer mode */ -enum transfer_mode { - /* Transfer data in single mode */ - SPIM_DMODE_SINGLE = 0, - /* Transfer data in dual mode */ - SPIM_DMODE_DUAL, - /* Transfer data in quad mode */ - SPIM_DMODE_QUAD -}; - -/* This structure contains parameters that describe an SPIM operation. */ -struct spim_buffer { - /* The buffer to read from or write to. */ - unsigned char *buffer; - - /* Number of bytes to read/write. Valid range is 0 to 65536 bytes. */ - unsigned int size; - - /* Read/write select. TRUE for read, FALSE for write, Others-invalid.*/ - int isread; - - /* - * ByteDelay select. - * Selects whether or not a delay is inserted between bytes. - * 0 - Minimum inter-byte delay - * 1 - Inter-byte delay of (cs_hold/master_clk half period)*master_clk. - */ - int inter_byte_delay; -}; - -#endif /* __SOC_IMGTEC_DANUBE_SPI_H__ */ diff --git a/src/soc/imgtec/pistachio/monotonic_timer.c b/src/soc/imgtec/pistachio/monotonic_timer.c deleted file mode 100644 index 3bc65a54ae..0000000000 --- a/src/soc/imgtec/pistachio/monotonic_timer.c +++ /dev/null @@ -1,53 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright 2014 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include -#include -#include - -#define PISTACHIO_CLOCK_SWITCH 0xB8144200 -#define MIPS_EXTERN_PLL_BYPASS_MASK 0x00000002 - -static int get_count_mhz_freq(void) -{ - static unsigned int count_mhz_freq; - - if (!count_mhz_freq) { - if (IMG_PLATFORM_ID() != IMG_PLATFORM_ID_SILICON) - count_mhz_freq = 25; /* FPGA board */ - else { - /* If MIPS PLL external bypass bit is set, it means - * that the MIPS PLL is already set up to work at a - * frequency of 550 MHz; otherwise, the crystal is - * used with a frequency of 52 MHz - */ - if (read32_x(PISTACHIO_CLOCK_SWITCH) & - MIPS_EXTERN_PLL_BYPASS_MASK) - /* Half MIPS PLL freq. */ - count_mhz_freq = 275; - else - /* Half Xtal freq. */ - count_mhz_freq = 26; - } - } - return count_mhz_freq; -} - -void timer_monotonic_get(struct mono_time *mt) -{ - mono_time_set_usecs(mt, read_c0_count() / get_count_mhz_freq()); -} diff --git a/src/soc/imgtec/pistachio/reset.c b/src/soc/imgtec/pistachio/reset.c deleted file mode 100644 index cc563372b4..0000000000 --- a/src/soc/imgtec/pistachio/reset.c +++ /dev/null @@ -1,26 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright 2014 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include - -#define PISTACHIO_WD_ADDR 0xB8102100 -#define PISTACHIO_WD_SW_RST_OFFSET 0x0000 - -void do_board_reset(void) -{ - /* Generate system reset */ - write32_x(PISTACHIO_WD_ADDR + PISTACHIO_WD_SW_RST_OFFSET, 0x1); -} diff --git a/src/soc/imgtec/pistachio/romstage.c b/src/soc/imgtec/pistachio/romstage.c deleted file mode 100644 index 8e44ea8749..0000000000 --- a/src/soc/imgtec/pistachio/romstage.c +++ /dev/null @@ -1,39 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2014 Imagination Technologies - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include -#include -#include - -void main(void) -{ - int error; - console_init(); - error = init_ddr2(); - - if (!error) { - /* - * When romstage is running it's always on the reboot path and - * never a resume path where cbmem recovery is required. - * Therefore, always initialize the cbmem area to be empty. - */ - cbmem_initialize_empty(); - run_ramstage(); - } - halt(); -} diff --git a/src/soc/imgtec/pistachio/soc.c b/src/soc/imgtec/pistachio/soc.c deleted file mode 100644 index 156d1dea47..0000000000 --- a/src/soc/imgtec/pistachio/soc.c +++ /dev/null @@ -1,44 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright 2014 The Chromium OS Authors. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include - -static void soc_read_resources(struct device *dev) -{ - ram_resource(dev, 0, (uintptr_t)_dram / KiB, - (CONFIG_DRAM_SIZE_MB * MiB) / KiB); -} - -static void soc_init(struct device *dev) -{ - printk(BIOS_INFO, "CPU: Imgtec Pistachio\n"); -} - -static struct device_operations soc_ops = { - .read_resources = soc_read_resources, - .init = soc_init, -}; - -static void enable_soc_dev(struct device *dev) -{ - dev->ops = &soc_ops; -} - -struct chip_operations soc_imgtec_pistachio_ops = { - CHIP_NAME("SOC: Imgtec Pistachio") - .enable_dev = enable_soc_dev, -}; diff --git a/src/soc/imgtec/pistachio/spi.c b/src/soc/imgtec/pistachio/spi.c deleted file mode 100644 index acbbd909bd..0000000000 --- a/src/soc/imgtec/pistachio/spi.c +++ /dev/null @@ -1,587 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2014 Imagination Technologies - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include - -/* Imgtec controller uses 16 bit packet length. */ -#define IMGTEC_SPI_MAX_TRANSFER_SIZE ((1 << 16) - 1) - -struct img_spi_slave { - /* SPIM instance device parameters */ - struct spim_device_parameters device_parameters; - /* SPIM instance base address */ - u32 base; - /* Boolean property that is TRUE if API has been initialised */ - int initialised; -}; - -/* Allocate memory for the maximum number of devices */ -static struct -img_spi_slave img_spi_slaves[SPIM_NUM_BLOCKS*SPIM_NUM_PORTS_PER_BLOCK]; - -/* - * Wait for the bit at the shift position to be set in reg - * If the bit is not set in SPI_TIMEOUT_VALUE_US return with error - */ -static int wait_status(u32 reg, u32 shift) -{ - struct stopwatch sw; - - stopwatch_init_usecs_expire(&sw, SPI_TIMEOUT_VALUE_US); - while (!(read32_x(reg) & (1 << shift))) { - if (stopwatch_expired(&sw)) - return -SPIM_TIMEOUT; - } - return SPIM_OK; -} - -static struct img_spi_slave *get_img_slave(const struct spi_slave *slave) -{ - return img_spi_slaves + slave->bus * SPIM_NUM_PORTS_PER_BLOCK + - slave->cs; -} - -/* Transmitter function. Fills TX FIFO with data before enabling SPIM */ -static int transmitdata(const struct spi_slave *slave, u8 *buffer, u32 size) -{ - u32 blocksize, base, write_data; - int ret; - struct img_spi_slave *img_slave = get_img_slave(slave); - - base = img_slave->base; - while (size) { - /* Wait until FIFO empty */ - write32_x(base + SPFI_INT_CLEAR_REG_OFFSET, SPFI_SDE_MASK); - ret = wait_status(base + SPFI_INT_STATUS_REG_OFFSET, - SPFI_SDE_SHIFT); - if (ret) - return ret; - - /* - * Write to FIFO in blocks of 16 words (64 bytes) - * Do 32bit writes first. - */ - blocksize = SPIM_MAX_BLOCK_BYTES; - while ((size >= sizeof(u32)) && blocksize) { - memcpy(&write_data, buffer, sizeof(u32)); - write32_x(base + SPFI_SEND_LONG_REG_OFFSET, write_data); - buffer += sizeof(u32); - size -= sizeof(u32); - blocksize -= sizeof(u32); - } - while (size && blocksize) { - write32_x(base + SPFI_SEND_BYTE_REG_OFFSET, *buffer); - buffer++; - size--; - blocksize--; - } - } - return SPIM_OK; -} - -/* Receiver function */ -static int receivedata(const struct spi_slave *slave, u8 *buffer, u32 size) -{ - u32 read_data, base; - int ret; - struct img_spi_slave *img_slave = get_img_slave(slave); - - base = img_slave->base; - /* - * Do 32bit reads first. Clear status GDEX32BIT here so that the first - * status reg. read gets the actual bit state - */ - write32_x(base + SPFI_INT_CLEAR_REG_OFFSET, SPFI_GDEX32BIT_MASK); - while (size >= sizeof(u32)) { - ret = wait_status(base + SPFI_INT_STATUS_REG_OFFSET, - SPFI_GDEX32BIT_SHIFT); - if (ret) - return ret; - read_data = read32_x(base + SPFI_GET_LONG_REG_OFFSET); - memcpy(buffer, &read_data, sizeof(u32)); - buffer += sizeof(u32); - size -= sizeof(u32); - /* Clear interrupt status on GDEX32BITL */ - write32_x(base + SPFI_INT_CLEAR_REG_OFFSET, SPFI_GDEX32BIT_MASK); - } - - /* - * Do the remaining 8bit reads. Clear status GDEX8BIT here so that - * the first status reg. read gets the actual bit state - */ - write32_x(base + SPFI_INT_CLEAR_REG_OFFSET, SPFI_GDEX8BIT_MASK); - while (size) { - ret = wait_status(base + SPFI_INT_STATUS_REG_OFFSET, - SPFI_GDEX8BIT_SHIFT); - if (ret) - return ret; - *buffer = read32_x(base + SPFI_GET_BYTE_REG_OFFSET); - buffer++; - size--; - /* Clear interrupt status on SPFI_GDEX8BIT */ - write32_x(base + SPFI_INT_CLEAR_REG_OFFSET, SPFI_GDEX8BIT_MASK); - } - return SPIM_OK; -} - -/* Sets port parameters in port state register. */ -static void setparams(const struct spi_slave *slave, u32 port, - struct spim_device_parameters *params) -{ - u32 spim_parameters, port_state, base; - struct img_spi_slave *img_slave = get_img_slave(slave); - - base = img_slave->base; - spim_parameters = 0; - port_state = read32_x(base + SPFI_PORT_STATE_REG_OFFSET); - port_state &= ~((SPIM_PORT0_MASK>>port)|SPFI_PORT_SELECT_MASK); - port_state |= params->cs_idle_level<<(SPIM_CS0_IDLE_SHIFT-port); - port_state |= - params->data_idle_level<<(SPIM_DATA0_IDLE_SHIFT-port); - - /* Clock idle level and phase */ - switch (params->spi_mode) { - case SPIM_MODE_0: - break; - case SPIM_MODE_1: - port_state |= (1 << (SPIM_CLOCK0_PHASE_SHIFT - port)); - break; - case SPIM_MODE_2: - port_state |= (1 << (SPIM_CLOCK0_IDLE_SHIFT - port)); - break; - case SPIM_MODE_3: - port_state |= (1 << (SPIM_CLOCK0_IDLE_SHIFT - port)) | - (1 << (SPIM_CLOCK0_PHASE_SHIFT - port)); - break; - } - /* Set port state register */ - write32_x(base + SPFI_PORT_STATE_REG_OFFSET, port_state); - - /* Set up values to be written to device parameter register */ - spim_parameters |= params->bitrate << SPIM_CLK_DIVIDE_SHIFT; - spim_parameters |= params->cs_setup << SPIM_CS_SETUP_SHIFT; - spim_parameters |= params->cs_hold << SPIM_CS_HOLD_SHIFT; - spim_parameters |= params->cs_delay << SPIM_CS_DELAY_SHIFT; - - write32_x(base + SPFI_PORT_0_PARAM_REG_OFFSET + 4 * port, - spim_parameters); -} - -/* Sets up transaction register */ -static u32 transaction_reg_setup(struct spim_buffer *first, - struct spim_buffer *second) -{ - u32 reg = 0; - - /* 2nd transfer exists? */ - if (second) { - /* - * If second transfer exists, it's a "command followed by data" - * type of transfer and first transfer is defined by - * CMD_LENGTH, ADDR_LENGTH, DUMMY_LENGTH... fields of - * transaction register - */ - reg = spi_write_reg_field(reg, SPFI_CMD_LENGTH, 1); - reg = spi_write_reg_field(reg, SPFI_ADDR_LENGTH, - first->size - 1); - reg = spi_write_reg_field(reg, SPFI_DUMMY_LENGTH, 0); - /* Set data size (size of the second transfer) */ - reg = spi_write_reg_field(reg, SPFI_TSIZE, second->size); - } else { - /* Set data size, in this case size of the 1st transfer */ - reg = spi_write_reg_field(reg, SPFI_TSIZE, first->size); - } - return reg; -} - -/* Sets up control register */ -static u32 control_reg_setup(struct spim_buffer *first, - struct spim_buffer *second) -{ - u32 reg; - - /* Enable SPFI */ - reg = SPFI_EN_MASK; - reg |= first->inter_byte_delay ? SPIM_BYTE_DELAY_MASK : 0; - - /* Set up the transfer mode */ - reg = spi_write_reg_field(reg, SPFI_TRNSFR_MODE_DQ, SPIM_CMD_MODE_0); - reg = spi_write_reg_field(reg, SPFI_TRNSFR_MODE, SPIM_DMODE_SINGLE); - reg = spi_write_reg_field(reg, SPIM_EDGE_TX_RX, 1); - - if (second) { - /* Set TX bit if the 2nd transaction is 'send' */ - reg = spi_write_reg_field(reg, SPFI_TX_RX, - second->isread ? 0 : 1); - /* - * Set send/get DMA for both transactions - * (first is always 'send') - */ - reg = spi_write_reg_field(reg, SPIM_SEND_DMA, 1); - if (second->isread) - reg = spi_write_reg_field(reg, SPIM_GET_DMA, 1); - - } else { - /* Set TX bit if the 1st transaction is 'send' */ - reg |= first->isread ? 0 : SPFI_TX_RX_MASK; - /* Set send/get DMA */ - reg |= first->isread ? SPIM_GET_DMA_MASK : SPIM_SEND_DMA_MASK; - } - return reg; -} - -/* Checks the given buffer information */ -static int check_buffers(const struct spi_slave *slave, struct spim_buffer *first, - struct spim_buffer *second){ - - struct img_spi_slave *img_slave = get_img_slave(slave); - - if (!(img_slave->initialised)) - return -SPIM_API_NOT_INITIALISED; - /* - * First operation must always be defined - * It can be either a read or a write and its size cannot be bigge - * than SPIM_MAX_TANSFER_BYTES = 64KB - 1 (0xFFFF) - */ - if (!first) - return -SPIM_INVALID_READ_WRITE; - if (first->size > SPIM_MAX_TRANSFER_BYTES) - return -SPIM_INVALID_SIZE; - if (first->isread > 1) - return -SPIM_INVALID_READ_WRITE; - /* Check operation parameters for 'second' */ - if (second) { - /* - * If the second operation is defined it must be a read - * operation and its size must not be bigger than - * SPIM_MAX_TANSFER_BYTES = 64KB - 1 (0xFFFF) - */ - if (second->size > SPIM_MAX_TRANSFER_BYTES) - return -SPIM_INVALID_SIZE; - if (!second->isread) - return -SPIM_INVALID_READ_WRITE; - /* - * If the second operations is defined, the first operation - * must be a write and its size cannot be bigger than - * SPIM_MAX_FLASH_COMMAND_BYTES(8): command size (1) + - * address size (7). - */ - if (first->isread) - return -SPIM_INVALID_READ_WRITE; - if (first->size > SPIM_MAX_FLASH_COMMAND_BYTES) - return -SPIM_INVALID_SIZE; - - } - return SPIM_OK; -} - -/* Checks the set bitrate */ -static int check_bitrate(u32 rate) -{ - /* Bitrate must be 1, 2, 4, 8, 16, 32, 64, or 128 */ - switch (rate) { - case 1: - case 2: - case 4: - case 8: - case 16: - case 32: - case 64: - case 128: - return SPIM_OK; - default: - return -SPIM_INVALID_BIT_RATE; - } - return -SPIM_INVALID_BIT_RATE; -} - -/* Checks device parameters for errors */ -static int check_device_params(struct spim_device_parameters *pdev_param) -{ - if (pdev_param->spi_mode < SPIM_MODE_0 || - pdev_param->spi_mode > SPIM_MODE_3) - return -SPIM_INVALID_SPI_MODE; - if (check_bitrate(pdev_param->bitrate) != SPIM_OK) - return -SPIM_INVALID_BIT_RATE; - if (pdev_param->cs_idle_level > 1) - return -SPIM_INVALID_CS_IDLE_LEVEL; - if (pdev_param->data_idle_level > 1) - return -SPIM_INVALID_DATA_IDLE_LEVEL; - return SPIM_OK; -} - -/* Function that carries out read/write operations */ -static int spim_io(const struct spi_slave *slave, struct spim_buffer *first, - struct spim_buffer *second) -{ - u32 reg, base; - int i, trans_count, ret; - struct spim_buffer *transaction[2]; - struct img_spi_slave *img_slave = get_img_slave(slave); - - base = img_slave->base; - - ret = check_buffers(slave, first, second); - if (ret) - return ret; - - /* - * Soft reset peripheral internals, this will terminate any - * pending transactions - */ - write32_x(base + SPFI_CONTROL_REG_OFFSET, SPIM_SOFT_RESET_MASK); - write32_x(base + SPFI_CONTROL_REG_OFFSET, 0); - /* Port state register */ - reg = read32_x(base + SPFI_PORT_STATE_REG_OFFSET); - reg = spi_write_reg_field(reg, SPFI_PORT_SELECT, slave->cs); - write32_x(base + SPFI_PORT_STATE_REG_OFFSET, reg); - /* Set transaction register */ - reg = transaction_reg_setup(first, second); - write32_x(base + SPFI_TRANSACTION_REG_OFFSET, reg); - /* Clear status */ - write32_x(base + SPFI_INT_CLEAR_REG_OFFSET, 0xffffffff); - /* Set control register */ - reg = control_reg_setup(first, second); - write32_x(base + SPFI_CONTROL_REG_OFFSET, reg); - /* First transaction always exists */ - transaction[0] = first; - trans_count = 1; - /* Is there a second transaction? */ - if (second) { - transaction[1] = second; - trans_count++; - } - /* Now write/read FIFO's */ - for (i = 0; i < trans_count; i++) - /* Which transaction to execute, "Send" or "Get"? */ - if (transaction[i]->isread) { - /* Get */ - ret = receivedata(slave, transaction[i]->buffer, - transaction[i]->size); - if (ret) { - printk(BIOS_ERR, - "%s: Error: receive data failed.\n", - __func__); - return ret; - } - } else { - /* Send */ - ret = transmitdata(slave, transaction[i]->buffer, - transaction[i]->size); - if (ret) { - printk(BIOS_ERR, - "%s: Error: transmit data failed.\n", - __func__); - return ret; - } - } - - /* Wait for end of the transaction */ - ret = wait_status(base + SPFI_INT_STATUS_REG_OFFSET, - SPFI_ALLDONE_SHIFT); - if (ret) - return ret; - /* - * Soft reset peripheral internals, this will terminate any - * pending transactions - */ - write32_x(base + SPFI_CONTROL_REG_OFFSET, SPIM_SOFT_RESET_MASK); - write32_x(base + SPFI_CONTROL_REG_OFFSET, 0); - - return SPIM_OK; -} - -/* Claim the bus and prepare it for communication */ -static int spi_ctrlr_claim_bus(const struct spi_slave *slave) -{ - int ret; - struct img_spi_slave *img_slave; - - if (!slave) { - printk(BIOS_ERR, "%s: Error: slave was not set up.\n", - __func__); - return -SPIM_API_NOT_INITIALISED; - } - img_slave = get_img_slave(slave); - if (img_slave->initialised) - return SPIM_OK; - /* Check device parameters */ - ret = check_device_params(&(img_slave->device_parameters)); - if (ret) { - printk(BIOS_ERR, "%s: Error: incorrect device parameters.\n", - __func__); - return ret; - } - /* Set device parameters */ - setparams(slave, slave->cs, &(img_slave->device_parameters)); - /* Soft reset peripheral internals */ - write32_x(img_slave->base + SPFI_CONTROL_REG_OFFSET, - SPIM_SOFT_RESET_MASK); - write32_x(img_slave->base + SPFI_CONTROL_REG_OFFSET, 0); - img_slave->initialised = IMG_TRUE; - return SPIM_OK; -} - -/* Release the SPI bus */ -static void spi_ctrlr_release_bus(const struct spi_slave *slave) -{ - struct img_spi_slave *img_slave; - - if (!slave) { - printk(BIOS_ERR, "%s: Error: slave was not set up.\n", - __func__); - return; - } - img_slave = get_img_slave(slave); - img_slave->initialised = IMG_FALSE; - /* Soft reset peripheral internals */ - write32_x(img_slave->base + SPFI_CONTROL_REG_OFFSET, - SPIM_SOFT_RESET_MASK); - write32_x(img_slave->base + SPFI_CONTROL_REG_OFFSET, 0); -} - -/* SPI transfer */ -static int do_spi_xfer(const struct spi_slave *slave, const void *dout, - size_t bytesout, void *din, size_t bytesin) -{ - struct spim_buffer buff_0; - struct spim_buffer buff_1; - - /* If we only have a read or a write operation - * the parameters for it will be put in the first buffer - */ - buff_0.buffer = (dout) ? (void *)dout : (void *)din; - buff_0.size = (dout) ? bytesout : bytesin; - buff_0.isread = (dout) ? IMG_FALSE : IMG_TRUE; - buff_0.inter_byte_delay = 0; - - if (dout && din) { - /* Set up the read buffer to receive our data */ - buff_1.buffer = din; - buff_1.size = bytesin; - buff_1.isread = IMG_TRUE; - buff_1.inter_byte_delay = 0; - } - return spim_io(slave, &buff_0, (dout && din) ? &buff_1 : NULL); -} - -static int spi_ctrlr_xfer(const struct spi_slave *slave, const void *dout, - size_t bytesout, void *din, size_t bytesin) -{ - unsigned int in_sz, out_sz; - int ret; - - if (!slave) { - printk(BIOS_ERR, "%s: Error: slave was not set up.\n", - __func__); - return -SPIM_API_NOT_INITIALISED; - } - if (!dout && !din) { - printk(BIOS_ERR, "%s: Error: both buffers are NULL.\n", - __func__); - return -SPIM_INVALID_TRANSFER_DESC; - } - - while (bytesin || bytesout) { - in_sz = min(IMGTEC_SPI_MAX_TRANSFER_SIZE, bytesin); - out_sz = min(IMGTEC_SPI_MAX_TRANSFER_SIZE, bytesout); - - ret = do_spi_xfer(slave, dout, out_sz, din, in_sz); - if (ret) - return ret; - - bytesin -= in_sz; - bytesout -= out_sz; - - if (bytesin) - din += in_sz; - else - din = NULL; - - if (bytesout) - dout += out_sz; - else - dout = NULL; - } - - return SPIM_OK; -} - -static int spi_ctrlr_setup(const struct spi_slave *slave) -{ - struct img_spi_slave *img_slave = NULL; - struct spim_device_parameters *device_parameters; - u32 base; - - switch (slave->bus) { - case 0: - base = IMG_SPIM0_BASE_ADDRESS; - break; - case 1: - base = IMG_SPIM1_BASE_ADDRESS; - break; - default: - printk(BIOS_ERR, "%s: Error: unsupported bus.\n", - __func__); - return -1; - } - if (slave->cs > SPIM_DEVICE4) { - printk(BIOS_ERR, "%s: Error: unsupported chipselect.\n", - __func__); - return -1; - } - - img_slave = get_img_slave(slave); - device_parameters = &(img_slave->device_parameters); - - img_slave->base = base; - - device_parameters->bitrate = 64; - device_parameters->cs_setup = 0; - device_parameters->cs_hold = 0; - device_parameters->cs_delay = 0; - device_parameters->spi_mode = SPIM_MODE_0; - device_parameters->cs_idle_level = 1; - device_parameters->data_idle_level = 0; - img_slave->initialised = IMG_FALSE; - - return 0; -} - -static const struct spi_ctrlr spi_ctrlr = { - .setup = spi_ctrlr_setup, - .claim_bus = spi_ctrlr_claim_bus, - .release_bus = spi_ctrlr_release_bus, - .xfer = spi_ctrlr_xfer, - .max_xfer_size = IMGTEC_SPI_MAX_TRANSFER_SIZE, -}; - -const struct spi_ctrlr_buses spi_ctrlr_bus_map[] = { - { - .ctrlr = &spi_ctrlr, - .bus_start = 0, - .bus_end = 1, - }, -}; - -const size_t spi_ctrlr_bus_map_count = ARRAY_SIZE(spi_ctrlr_bus_map); diff --git a/src/soc/imgtec/pistachio/uart.c b/src/soc/imgtec/pistachio/uart.c deleted file mode 100644 index d5042d546d..0000000000 --- a/src/soc/imgtec/pistachio/uart.c +++ /dev/null @@ -1,158 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2003 Eric Biederman - * Copyright (C) 2006-2010 coresystems GmbH - * Copyright (C) 2014 Imagination Technologies - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include -#include -#include -#include - -/* Should support 8250, 16450, 16550, 16550A type UARTs */ - -/* Expected character delay at 1200bps is 9ms for a working UART - * and no flow-control. Assume UART as stuck if shift register - * or FIFO takes more than 50ms per character to appear empty. - */ -#define SINGLE_CHAR_TIMEOUT (50 * 1000) -#define FIFO_TIMEOUT (16 * SINGLE_CHAR_TIMEOUT) -#define UART_SHIFT 2 - -#define GEN_ACCESSOR(name, idx) \ -static inline uint8_t read_##name(unsigned int base_port) \ -{ \ - return read8((void *)(base_port + (idx << UART_SHIFT))); \ -} \ - \ -static inline void write_##name(unsigned int base_port, uint8_t val) \ -{ \ - write8((void *)(base_port + (idx << UART_SHIFT)), val); \ -} - -GEN_ACCESSOR(rbr, UART8250_RBR) -GEN_ACCESSOR(tbr, UART8250_TBR) -GEN_ACCESSOR(ier, UART8250_IER) -GEN_ACCESSOR(fcr, UART8250_FCR) -GEN_ACCESSOR(lcr, UART8250_LCR) -GEN_ACCESSOR(mcr, UART8250_MCR) -GEN_ACCESSOR(lsr, UART8250_LSR) -GEN_ACCESSOR(dll, UART8250_DLL) -GEN_ACCESSOR(dlm, UART8250_DLM) - -static int uart8250_mem_can_tx_byte(unsigned int base_port) -{ - return read_lsr(base_port) & UART8250_LSR_THRE; -} - -static void uart8250_mem_tx_byte(unsigned int base_port, unsigned char data) -{ - unsigned long int i = SINGLE_CHAR_TIMEOUT; - while (i-- && !uart8250_mem_can_tx_byte(base_port)) - udelay(1); - write_tbr(base_port, data); -} - -static void uart8250_mem_tx_flush(unsigned int base_port) -{ - unsigned long int i = FIFO_TIMEOUT; - while (i-- && !(read_lsr(base_port) & UART8250_LSR_TEMT)) - udelay(1); -} - -static int uart8250_mem_can_rx_byte(unsigned int base_port) -{ - return read_lsr(base_port) & UART8250_LSR_DR; -} - -static unsigned char uart8250_mem_rx_byte(unsigned int base_port) -{ - unsigned long int i = SINGLE_CHAR_TIMEOUT; - while (i-- && !uart8250_mem_can_rx_byte(base_port)) - udelay(1); - if (i) - return read_rbr(base_port); - else - return 0x0; -} - -static void uart8250_mem_init(unsigned int base_port, unsigned int divisor) -{ - /* Disable interrupts */ - write_ier(base_port, 0x0); - /* Enable FIFOs */ - write_fcr(base_port, UART8250_FCR_FIFO_EN); - - /* Assert DTR and RTS so the other end is happy */ - write_mcr(base_port, UART8250_MCR_DTR | UART8250_MCR_RTS); - - /* DLAB on */ - write_lcr(base_port, UART8250_LCR_DLAB | CONFIG_TTYS0_LCS); - - write_dll(base_port, divisor & 0xFF); - write_dlm(base_port, (divisor >> 8) & 0xFF); - - /* Set to 3 for 8N1 */ - write_lcr(base_port, CONFIG_TTYS0_LCS); -} - -unsigned int uart_platform_refclk(void) -{ - /* 1.8433179 MHz */ - return 1843318; -} - -void uart_init(int idx) -{ - u32 base = CONFIG_CONSOLE_SERIAL_UART_ADDRESS; - if (!base) - return; - - unsigned int div; - div = uart_baudrate_divisor(get_uart_baudrate(), - uart_platform_refclk(), 16); - uart8250_mem_init(base, div); -} - -void uart_tx_byte(int idx, unsigned char data) -{ - uart8250_mem_tx_byte(CONFIG_CONSOLE_SERIAL_UART_ADDRESS, data); -} - -unsigned char uart_rx_byte(int idx) -{ - return uart8250_mem_rx_byte(CONFIG_CONSOLE_SERIAL_UART_ADDRESS); -} - -void uart_tx_flush(int idx) -{ - uart8250_mem_tx_flush(CONFIG_CONSOLE_SERIAL_UART_ADDRESS); -} - -void uart_fill_lb(void *data) -{ - struct lb_serial serial; - serial.type = LB_SERIAL_TYPE_MEMORY_MAPPED; - serial.baseaddr = CONFIG_CONSOLE_SERIAL_UART_ADDRESS; - serial.baud = get_uart_baudrate(); - serial.regwidth = 1 << UART_SHIFT; - serial.input_hertz = uart_platform_refclk(); - serial.uart_pci_addr = CONFIG_UART_PCI_ADDR; - lb_add_serial(&serial, data); - - lb_add_console(LB_TAG_CONSOLE_SERIAL8250MEM, data); -} diff --git a/util/bimgtool/Makefile b/util/bimgtool/Makefile deleted file mode 100644 index 05ddf7d757..0000000000 --- a/util/bimgtool/Makefile +++ /dev/null @@ -1,16 +0,0 @@ -obj ?= $(CURDIR) - -HOSTCC ?= gcc -CFLAGS ?= -g -CFLAGS += -D_7ZIP_ST -CFLAGS += -Wall -Wundef -Wstrict-prototypes -Wmissing-prototypes -CFLAGS += -Wwrite-strings -Wredundant-decls -Wno-trigraphs -CFLAGS += -Wstrict-aliasing -Wshadow -Werror - -all: $(obj)/bimgtool - -clean: - rm -f $(obj)/bimgtool - -$(obj)/bimgtool: bimgtool.c - $(HOSTCC) $(CFLAGS) -o $@ $^ diff --git a/util/bimgtool/bimgtool.c b/util/bimgtool/bimgtool.c deleted file mode 100644 index 518674cf64..0000000000 --- a/util/bimgtool/bimgtool.c +++ /dev/null @@ -1,430 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright 2014 Imagination Technologies Ltd. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include -#include -#include -#include -#include - -struct bimg_header { - uint32_t magic; - uint16_t ver_major; - uint16_t ver_minor; - uint32_t data_size; - uint32_t entry_addr; - uint32_t flags; - uint32_t data_crc; - uint32_t crc; -} __attribute__((packed)); - -struct bimg_data_header { - uint32_t size; - uint32_t dest_addr; - uint16_t dummy; - uint16_t crc; -} __attribute__((packed)); - -struct crc_t { - uint16_t (*crc_f)(uint16_t crc, void *void_buf, size_t size); - uint32_t crc_init; - uint16_t ver_major; - uint16_t ver_minor; -}; - - -#define BIMG_MAGIC /* y */ 0xabbadaba /* doo! */ - -#define BIMG_OP_MASK (0xf << 0) -#define BIMG_OP_EXEC_RETURN (0x1 << 0) -#define BIMG_OP_EXEC_NO_RETURN (0x2 << 0) -#define BIMG_DATA_CHECKSUM (0x1 << 4) - -/* Typical use case for this utility. */ -#define BIMG_FLAGS (BIMG_OP_EXEC_NO_RETURN | BIMG_DATA_CHECKSUM) - -#define MAX_RECORD_BYTES 0x8000 - -#define CRC_16 - -#define error(msg...) fprintf(stderr, "ERROR: " msg) - -#define error_ret(ret, msg...) { \ - error(msg); \ - return ret; \ -} - -#if defined(CRC_X25) -static uint16_t crc_x25(uint16_t crc, void *void_buf, size_t size) -{ - static const uint16_t crc_table[16] = { - 0x0000, 0x1021, 0x2042, 0x3063, - 0x4084, 0x50a5, 0x60c6, 0x70e7, - 0x8108, 0x9129, 0xa14a, 0xb16b, - 0xc18c, 0xd1ad, 0xe1ce, 0xf1ef, - }; - uint8_t *buf, data; - - for (buf = void_buf; size; size--) { - data = *buf++; - crc = (crc << 4) ^ crc_table[((crc >> 12) ^ (data >> 4)) & 0xf]; - crc = (crc << 4) ^ crc_table[((crc >> 12) ^ (data >> 0)) & 0xf]; - } - - return crc; -} -#endif - -#if defined(CRC_16) -static uint16_t crc_16(uint16_t crc, void *void_buf, size_t size) -{ - /* - * CRC table for the CRC-16. - * The poly is 0x8005 (x^16 + x^15 + x^2 + 1) - */ - static const uint16_t crc16_table[256] = { - 0x0000, 0xC0C1, 0xC181, 0x0140, 0xC301, 0x03C0, 0x0280, 0xC241, - 0xC601, 0x06C0, 0x0780, 0xC741, 0x0500, 0xC5C1, 0xC481, 0x0440, - 0xCC01, 0x0CC0, 0x0D80, 0xCD41, 0x0F00, 0xCFC1, 0xCE81, 0x0E40, - 0x0A00, 0xCAC1, 0xCB81, 0x0B40, 0xC901, 0x09C0, 0x0880, 0xC841, - 0xD801, 0x18C0, 0x1980, 0xD941, 0x1B00, 0xDBC1, 0xDA81, 0x1A40, - 0x1E00, 0xDEC1, 0xDF81, 0x1F40, 0xDD01, 0x1DC0, 0x1C80, 0xDC41, - 0x1400, 0xD4C1, 0xD581, 0x1540, 0xD701, 0x17C0, 0x1680, 0xD641, - 0xD201, 0x12C0, 0x1380, 0xD341, 0x1100, 0xD1C1, 0xD081, 0x1040, - 0xF001, 0x30C0, 0x3180, 0xF141, 0x3300, 0xF3C1, 0xF281, 0x3240, - 0x3600, 0xF6C1, 0xF781, 0x3740, 0xF501, 0x35C0, 0x3480, 0xF441, - 0x3C00, 0xFCC1, 0xFD81, 0x3D40, 0xFF01, 0x3FC0, 0x3E80, 0xFE41, - 0xFA01, 0x3AC0, 0x3B80, 0xFB41, 0x3900, 0xF9C1, 0xF881, 0x3840, - 0x2800, 0xE8C1, 0xE981, 0x2940, 0xEB01, 0x2BC0, 0x2A80, 0xEA41, - 0xEE01, 0x2EC0, 0x2F80, 0xEF41, 0x2D00, 0xEDC1, 0xEC81, 0x2C40, - 0xE401, 0x24C0, 0x2580, 0xE541, 0x2700, 0xE7C1, 0xE681, 0x2640, - 0x2200, 0xE2C1, 0xE381, 0x2340, 0xE101, 0x21C0, 0x2080, 0xE041, - 0xA001, 0x60C0, 0x6180, 0xA141, 0x6300, 0xA3C1, 0xA281, 0x6240, - 0x6600, 0xA6C1, 0xA781, 0x6740, 0xA501, 0x65C0, 0x6480, 0xA441, - 0x6C00, 0xACC1, 0xAD81, 0x6D40, 0xAF01, 0x6FC0, 0x6E80, 0xAE41, - 0xAA01, 0x6AC0, 0x6B80, 0xAB41, 0x6900, 0xA9C1, 0xA881, 0x6840, - 0x7800, 0xB8C1, 0xB981, 0x7940, 0xBB01, 0x7BC0, 0x7A80, 0xBA41, - 0xBE01, 0x7EC0, 0x7F80, 0xBF41, 0x7D00, 0xBDC1, 0xBC81, 0x7C40, - 0xB401, 0x74C0, 0x7580, 0xB541, 0x7700, 0xB7C1, 0xB681, 0x7640, - 0x7200, 0xB2C1, 0xB381, 0x7340, 0xB101, 0x71C0, 0x7080, 0xB041, - 0x5000, 0x90C1, 0x9181, 0x5140, 0x9301, 0x53C0, 0x5280, 0x9241, - 0x9601, 0x56C0, 0x5780, 0x9741, 0x5500, 0x95C1, 0x9481, 0x5440, - 0x9C01, 0x5CC0, 0x5D80, 0x9D41, 0x5F00, 0x9FC1, 0x9E81, 0x5E40, - 0x5A00, 0x9AC1, 0x9B81, 0x5B40, 0x9901, 0x59C0, 0x5880, 0x9841, - 0x8801, 0x48C0, 0x4980, 0x8941, 0x4B00, 0x8BC1, 0x8A81, 0x4A40, - 0x4E00, 0x8EC1, 0x8F81, 0x4F40, 0x8D01, 0x4DC0, 0x4C80, 0x8C41, - 0x4400, 0x84C1, 0x8581, 0x4540, 0x8701, 0x47C0, 0x4680, 0x8641, - 0x8201, 0x42C0, 0x4380, 0x8341, 0x4100, 0x81C1, 0x8081, 0x4040 - }; - uint8_t *buf, data; - - for (buf = void_buf; size; size--) { - data = *buf++; - crc = (crc >> 8) ^ crc16_table[(crc ^ data) & 0xff]; - } - - return crc; -} -#endif - -static const struct crc_t crc_type = { -#if defined(CRC_16) - .crc_f = crc_16, - .crc_init = 0, - .ver_major = 2, - .ver_minor = 0 -#elif defined(CRC_X25) - .crc_f = crc_x25, - .crc_init = 0xffff, - .ver_major = 1, - .ver_minor = 0 -#endif -}; - -static int write_binary(FILE *out, FILE *in, struct bimg_header *hdr) -{ - static uint8_t file_buf[MAX_RECORD_BYTES]; - struct bimg_data_header data_hdr = { 0 }; - size_t n_written; - - data_hdr.dest_addr = hdr->entry_addr; - - /* - * The read binary data has to be split in chunks of max 64KiB - 1 byte - * (SPI controller limitation). Each chunk will have its own header in - * order to respect the BIMG format. - */ - while ((data_hdr.size = fread(file_buf, 1, sizeof(file_buf), in))) { - data_hdr.crc = crc_type.crc_f(crc_type.crc_init, &data_hdr, - sizeof(data_hdr) - sizeof(data_hdr.crc)); - - if (fwrite(&data_hdr, sizeof(data_hdr), 1, out) != 1) - error_ret(-EIO, "Failed to write data header: %d\n", - errno); - - n_written = fwrite(file_buf, 1, data_hdr.size, out); - if (n_written != data_hdr.size) - error_ret(-EIO, "Failed to write to output file: %d\n", - errno); - - data_hdr.dest_addr += n_written; - hdr->data_size += sizeof(data_hdr) + n_written; - hdr->data_crc = crc_type.crc_f(hdr->data_crc, - file_buf, n_written); - } - - if (ferror(in)) - error_ret(-EIO, "Failed to read input file\n"); - - return 0; -} - -static int write_final(FILE *out, struct bimg_header *hdr) -{ - struct bimg_data_header data_hdr = { - .size = 0, - .dest_addr = ~0, - }; - - data_hdr.crc = crc_type.crc_f(crc_type.crc_init, &data_hdr, - sizeof(data_hdr) - sizeof(data_hdr.crc)); - - if (fwrite(&data_hdr, sizeof(data_hdr), 1, out) != 1) - error_ret(-EIO, "Failed to write data header: %d\n", errno); - - hdr->data_size += sizeof(data_hdr); - - return 0; -} - -static const char *help_message = - "Usage: bimgtool [ ]\n" - "\n" - "This is a simple tool which generates and verifies boot images in\n" - "the BIMG format, used in systems designed by Imagination\n" - "Technologies, for example the Pistachio SoC. This version of the\n" - "tool works with BIMG images version %d.\n" - "\n" - " input: The binary file to be converted to a BIMG\n" - " or verified\n" - " output: The name of the output BIMG file\n" - " base-address: The address in memory at which you wish the " - " input binary to be loaded.\n"; - -static void usage(FILE *f) -{ - fprintf(f, help_message, crc_type.ver_major); -} - -static int verify_file(FILE *f) -{ - struct bimg_header file_header; - struct bimg_data_header data_header; - char *file_pointer; - char *file_data; - struct stat buf; - int data_size; - int fd = fileno(f); - uint32_t data_crc = crc_type.crc_init; - uint32_t crc_result; - - if (fread(&file_header, 1, sizeof(struct bimg_header), f) != - sizeof(struct bimg_header)) { - perror("Problems trying to read input file header\n"); - return -1; - } - - if (fstat(fd, &buf)) { - perror("Problems trying to stat input file\n"); - return -1; - } - - if (file_header.magic != BIMG_MAGIC) { - fprintf(stderr, "Wrong magic value %#x\n", file_header.magic); - return -1; - } - - crc_result = crc_type.crc_f(crc_type.crc_init, &file_header, - sizeof(file_header) - - sizeof(file_header.crc)); - if (file_header.crc != crc_result) { - fprintf(stderr, "File header CRC mismatch\n"); - return -1; - } - - if ((file_header.data_size + sizeof(struct bimg_header)) > - buf.st_size) { - fprintf(stderr, "Data size too big: %d > %zd\n", - file_header.data_size, buf.st_size); - return -1; - } - - if (file_header.ver_major != crc_type.ver_major) { - fprintf(stderr, "Image version mismatch: %d\n", - file_header.ver_major); - return -1; - } - - if ((file_header.flags & BIMG_FLAGS) != BIMG_FLAGS) { - fprintf(stderr, "Unexpected file header flags: %#x\n", - file_header.flags); - return -1; - } - - if (file_header.ver_minor != crc_type.ver_minor) { - fprintf(stderr, - "Minor version mismatch: %d, will try anyways\n", - file_header.ver_minor); - } - - data_size = file_header.data_size; - file_pointer = malloc(data_size); - if (!file_pointer) { - fprintf(stderr, "Failed to allocate %d bytes\n", - file_header.data_size); - return -1; - } - - if (fread(file_pointer, 1, data_size, f) != data_size) { - fprintf(stderr, "Failed to read %d bytes\n", data_size); - free(file_pointer); - return -1; - } - - file_data = file_pointer; - while (data_size > 0) { - memcpy(&data_header, file_data, sizeof(data_header)); - - /* Check the data block header integrity. */ - crc_result = crc_type.crc_f(crc_type.crc_init, &data_header, - sizeof(data_header) - - sizeof(data_header.crc)); - if (data_header.crc != crc_result) { - fprintf(stderr, "Data header CRC mismatch at %d\n", - file_header.data_size - data_size); - free(file_pointer); - return -1; - } - - /* - * Add the block data to the CRC stream, the last block size - * will be zero. - */ - file_data += sizeof(data_header); - data_crc = crc_type.crc_f(data_crc, - file_data, data_header.size); - - data_size -= data_header.size + sizeof(data_header); - file_data += data_header.size; - } - - if (data_size) { - fprintf(stderr, "File size mismatch\n"); - free(file_pointer); - return -1; - } - - if (data_crc != file_header.data_crc) { - fprintf(stderr, "File data CRC mismatch\n"); - free(file_pointer); - return -1; - } - - free(file_pointer); - return 0; -} - -int main(int argc, char *argv[]) -{ - const char *in_filename, *out_filename; - FILE *in_file, *out_file; - int err; - struct bimg_header hdr = { - .magic = BIMG_MAGIC, - .ver_major = crc_type.ver_major, - .ver_minor = crc_type.ver_minor, - .flags = BIMG_FLAGS, - .data_crc = crc_type.crc_init, - }; - - if ((argc != 4) && (argc != 2)) { - usage(stderr); - goto out_err; - } - - in_filename = argv[1]; - - in_file = fopen(in_filename, "r"); - if (!in_file) { - error("Failed to open input file '%s'\n", in_filename); - goto out_err; - } - - if (argc == 2) - return verify_file(in_file); - - out_filename = argv[2]; - hdr.entry_addr = strtoul(argv[3], NULL, 16); - - out_file = fopen(out_filename, "w"); - if (!out_file) { - error("Failed to open output file '%s'\n", out_filename); - goto out_err_close_in; - } - - if (fseek(out_file, sizeof(hdr), SEEK_SET)) { - error("Failed to seek past header: %d\n", errno); - goto out_err_close_out; - } - - err = write_binary(out_file, in_file, &hdr); - if (err) { - error("Failed to write binary: %d\n", err); - goto out_err_close_out; - } - - err = write_final(out_file, &hdr); - if (err) { - error("Failed to write final record: %d\n", err); - goto out_err_close_out; - } - - hdr.crc = crc_type.crc_f(crc_type.crc_init, &hdr, - sizeof(hdr) - sizeof(hdr.crc)); - - if (fseek(out_file, 0, SEEK_SET)) { - error("Failed to seek to header: %d\n", errno); - goto out_err_close_out; - } - - if (fwrite(&hdr, sizeof(hdr), 1, out_file) != 1) { - error("Failed to write header: %d\n", errno); - goto out_err_close_out; - } - - fclose(in_file); - fclose(out_file); - return EXIT_SUCCESS; - -out_err_close_out: - fclose(out_file); -out_err_close_in: - fclose(in_file); -out_err: - return EXIT_FAILURE; -} diff --git a/util/bimgtool/description.md b/util/bimgtool/description.md deleted file mode 100644 index aa1059a8dc..0000000000 --- a/util/bimgtool/description.md +++ /dev/null @@ -1,3 +0,0 @@ -A simple tool which generates and verifies boot images in the BIMG -format, used in systems designed by Imagination Technologies, for -example the Pistachio SoC. `C` From f96d9051c2b39544300d35f64ce92502e1e230c0 Mon Sep 17 00:00:00 2001 From: Julius Werner Date: Fri, 16 Aug 2019 15:35:39 -0700 Subject: [PATCH 0261/1242] Remove MIPS architecture The MIPS architecture port has been added 5+ years ago in order to support a Chrome OS project that ended up going nowhere. No other board has used it since and nobody is still willing or has the expertise and hardware to maintain it. We have decided that it has become too much of a mainenance burden and the chance of anyone ever reviving it seems too slim at this point. This patch eliminates all MIPS code and MIPS-specific hacks. Change-Id: I5e49451cd055bbab0a15dcae5f53e0172e6e2ebe Signed-off-by: Julius Werner Reviewed-on: https://review.coreboot.org/c/coreboot/+/34919 Reviewed-by: Arthur Heymans Reviewed-by: Hung-Te Lin Tested-by: build bot (Jenkins) --- Documentation/contributing/project_ideas.md | 4 +- MAINTAINERS | 6 - payloads/libpayload/Kconfig | 9 +- payloads/libpayload/Makefile | 2 - payloads/libpayload/Makefile.inc | 1 - payloads/libpayload/arch/mips/Kconfig | 24 --- payloads/libpayload/arch/mips/Makefile.inc | 33 --- payloads/libpayload/arch/mips/cache.c | 72 ------- payloads/libpayload/arch/mips/coreboot.c | 51 ----- payloads/libpayload/arch/mips/dummy_media.c | 42 ---- payloads/libpayload/arch/mips/exception.c | 103 --------- payloads/libpayload/arch/mips/exception_asm.S | 200 ------------------ payloads/libpayload/arch/mips/gdb.c | 27 --- payloads/libpayload/arch/mips/head.S | 96 --------- .../libpayload/arch/mips/libpayload.ldscript | 86 -------- payloads/libpayload/arch/mips/main.c | 58 ----- payloads/libpayload/arch/mips/selfboot.c | 36 ---- payloads/libpayload/arch/mips/string.c | 77 ------- payloads/libpayload/arch/mips/sysinfo.c | 49 ----- payloads/libpayload/arch/mips/timer.c | 52 ----- payloads/libpayload/arch/mips/util.S | 22 -- payloads/libpayload/bin/lpgcc | 10 +- payloads/libpayload/configs/defconfig-mips | 6 - .../libpayload/drivers/timer/img_pistachio.c | 38 ---- .../libpayload/include/mips/arch/byteorder.h | 39 ---- payloads/libpayload/include/mips/arch/cache.h | 94 -------- payloads/libpayload/include/mips/arch/cpu.h | 92 -------- .../libpayload/include/mips/arch/exception.h | 86 -------- payloads/libpayload/include/mips/arch/io.h | 63 ------ .../libpayload/include/mips/arch/stdint.h | 91 -------- payloads/libpayload/include/mips/arch/types.h | 72 ------- .../libpayload/include/mips/arch/virtual.h | 34 --- payloads/libpayload/libc/64bit_div.c | 141 ------------ payloads/libpayload/libc/Makefile.inc | 4 - payloads/libpayload/sample/Makefile | 1 - src/arch/mips/Kconfig | 38 ---- src/arch/mips/Makefile.inc | 93 -------- src/arch/mips/ashldi3.c | 53 ----- src/arch/mips/boot.c | 23 -- src/arch/mips/bootblock.S | 42 ---- src/arch/mips/bootblock_simple.c | 42 ---- src/arch/mips/cache.c | 114 ---------- src/arch/mips/include/arch/bootblock_common.h | 24 --- src/arch/mips/include/arch/byteorder.h | 23 -- src/arch/mips/include/arch/cache.h | 48 ----- src/arch/mips/include/arch/cbconfig.h | 26 --- src/arch/mips/include/arch/cpu.h | 172 --------------- src/arch/mips/include/arch/early_variables.h | 27 --- src/arch/mips/include/arch/exception.h | 19 -- src/arch/mips/include/arch/header.ld | 26 --- src/arch/mips/include/arch/hlt.h | 23 -- src/arch/mips/include/arch/memlayout.h | 29 --- src/arch/mips/include/arch/mmio.h | 64 ------ src/arch/mips/include/arch/mmu.h | 53 ----- src/arch/mips/include/arch/pci_ops.h | 19 -- src/arch/mips/include/arch/stages.h | 22 -- src/arch/mips/include/arch/types.h | 59 ------ src/arch/mips/mmu.c | 98 --------- src/arch/mips/stages.c | 23 -- src/arch/mips/tables.c | 28 --- src/console/vtxprintf.c | 4 - src/cpu/Makefile.inc | 1 - src/drivers/spi/cbfs_spi.c | 2 +- src/include/rules.h | 18 -- src/vendorcode/google/chromeos/Makefile.inc | 3 +- toolchain.inc | 3 - util/README.md | 3 - util/cbfstool/cbfs.h | 2 +- util/crossgcc/Makefile | 10 +- util/crossgcc/Makefile.inc | 6 +- util/crossgcc/README | 1 - util/crossgcc/buildgcc | 3 +- .../board-status.html/tohtml.sh | 3 - util/release/genrelnotes | 5 - util/xcompile/xcompile | 20 +- 75 files changed, 15 insertions(+), 3078 deletions(-) delete mode 100644 payloads/libpayload/arch/mips/Kconfig delete mode 100644 payloads/libpayload/arch/mips/Makefile.inc delete mode 100644 payloads/libpayload/arch/mips/cache.c delete mode 100644 payloads/libpayload/arch/mips/coreboot.c delete mode 100644 payloads/libpayload/arch/mips/dummy_media.c delete mode 100644 payloads/libpayload/arch/mips/exception.c delete mode 100644 payloads/libpayload/arch/mips/exception_asm.S delete mode 100644 payloads/libpayload/arch/mips/gdb.c delete mode 100644 payloads/libpayload/arch/mips/head.S delete mode 100644 payloads/libpayload/arch/mips/libpayload.ldscript delete mode 100644 payloads/libpayload/arch/mips/main.c delete mode 100644 payloads/libpayload/arch/mips/selfboot.c delete mode 100644 payloads/libpayload/arch/mips/string.c delete mode 100644 payloads/libpayload/arch/mips/sysinfo.c delete mode 100644 payloads/libpayload/arch/mips/timer.c delete mode 100644 payloads/libpayload/arch/mips/util.S delete mode 100644 payloads/libpayload/configs/defconfig-mips delete mode 100644 payloads/libpayload/drivers/timer/img_pistachio.c delete mode 100644 payloads/libpayload/include/mips/arch/byteorder.h delete mode 100644 payloads/libpayload/include/mips/arch/cache.h delete mode 100644 payloads/libpayload/include/mips/arch/cpu.h delete mode 100644 payloads/libpayload/include/mips/arch/exception.h delete mode 100644 payloads/libpayload/include/mips/arch/io.h delete mode 100644 payloads/libpayload/include/mips/arch/stdint.h delete mode 100644 payloads/libpayload/include/mips/arch/types.h delete mode 100644 payloads/libpayload/include/mips/arch/virtual.h delete mode 100644 payloads/libpayload/libc/64bit_div.c delete mode 100644 src/arch/mips/Kconfig delete mode 100644 src/arch/mips/Makefile.inc delete mode 100644 src/arch/mips/ashldi3.c delete mode 100644 src/arch/mips/boot.c delete mode 100644 src/arch/mips/bootblock.S delete mode 100644 src/arch/mips/bootblock_simple.c delete mode 100644 src/arch/mips/cache.c delete mode 100644 src/arch/mips/include/arch/bootblock_common.h delete mode 100644 src/arch/mips/include/arch/byteorder.h delete mode 100644 src/arch/mips/include/arch/cache.h delete mode 100644 src/arch/mips/include/arch/cbconfig.h delete mode 100644 src/arch/mips/include/arch/cpu.h delete mode 100644 src/arch/mips/include/arch/early_variables.h delete mode 100644 src/arch/mips/include/arch/exception.h delete mode 100644 src/arch/mips/include/arch/header.ld delete mode 100644 src/arch/mips/include/arch/hlt.h delete mode 100644 src/arch/mips/include/arch/memlayout.h delete mode 100644 src/arch/mips/include/arch/mmio.h delete mode 100644 src/arch/mips/include/arch/mmu.h delete mode 100644 src/arch/mips/include/arch/pci_ops.h delete mode 100644 src/arch/mips/include/arch/stages.h delete mode 100644 src/arch/mips/include/arch/types.h delete mode 100644 src/arch/mips/mmu.c delete mode 100644 src/arch/mips/stages.c delete mode 100644 src/arch/mips/tables.c diff --git a/Documentation/contributing/project_ideas.md b/Documentation/contributing/project_ideas.md index 21a756d99a..5bc4cacea5 100644 --- a/Documentation/contributing/project_ideas.md +++ b/Documentation/contributing/project_ideas.md @@ -64,7 +64,7 @@ across architectures. ### Mentors * Timothy Pearson -## Support QEMU AArch64 or MIPS +## Support QEMU AArch64 Having QEMU support for the architectures coreboot can boot helps with some (limited) compatibility testing: While QEMU generally doesn't need much hardware init, any CPU state changes in the boot flow will likely @@ -105,7 +105,7 @@ would help to ensure code quality and make the runtime code more robust. ### Mentors * Werner Zeh -## Port payloads to ARM, AArch64, MIPS or RISC-V +## Port payloads to ARM, AArch64 or RISC-V While we have a rather big set of payloads for x86 based platforms, all other architectures are rather limited. Improve the situation by porting a payload to one of the platforms, for example GRUB2, U-Boot (the UI part), Tianocore, diff --git a/MAINTAINERS b/MAINTAINERS index 9abbdb1527..8e03c13102 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -477,12 +477,6 @@ F: util/arm_boot_tools/ F: util/exynos/ F: util/ipqheader/ -MIPS ARCHITECTURE -F: src/arch/mips/ -F: src/cpu/mips/ -F: src/soc/imgtec/ -F: util/bimgtool/ - X86 ARCHITECTURE F: src/arch/x86/ F: src/cpu/x86/ diff --git a/payloads/libpayload/Kconfig b/payloads/libpayload/Kconfig index 97b970b0f1..d216f61dc8 100644 --- a/payloads/libpayload/Kconfig +++ b/payloads/libpayload/Kconfig @@ -114,11 +114,6 @@ config ARCH_ARM64 help Support the ARM64 architecture -config ARCH_MIPS - bool "MIPS" - help - Support the MIPS architecture - endchoice config MULTIBOOT @@ -147,12 +142,11 @@ config BASE_ADDRESS hex "Base address" default 0x04000000 if ARCH_ARM default 0x80100000 if ARCH_ARM64 - default 0x00000000 if ARCH_MIPS default 0x00100000 if ARCH_X86 help This is the base address for the payload. - If unsure, set to 0x00100000 on x86, 0x00000000 on MIPS, + If unsure, set to 0x00100000 on x86, 0x04000000 on ARM or 0x80100000 on ARM64. endmenu @@ -452,5 +446,4 @@ config IO_ADDRESS_SPACE source "arch/arm/Kconfig" source "arch/arm64/Kconfig" -source "arch/mips/Kconfig" source "arch/x86/Kconfig" diff --git a/payloads/libpayload/Makefile b/payloads/libpayload/Makefile index b1ab302794..e5f49a6701 100644 --- a/payloads/libpayload/Makefile +++ b/payloads/libpayload/Makefile @@ -95,7 +95,6 @@ include $(HAVE_DOTCONFIG) ARCHDIR-$(CONFIG_LP_ARCH_ARM) := arm ARCHDIR-$(CONFIG_LP_ARCH_ARM64) := arm64 -ARCHDIR-$(CONFIG_LP_ARCH_MIPS) := mips ARCHDIR-$(CONFIG_LP_ARCH_X86) := x86 ARCH-y := $(ARCHDIR-y) @@ -105,7 +104,6 @@ ARCH-y := $(ARCHDIR-y) ARCH-$(CONFIG_LP_ARCH_ARM) := arm ARCH-$(CONFIG_LP_ARCH_ARM64) := arm64 ARCH-$(CONFIG_LP_ARCH_X86) := x86_32 -ARCH-$(CONFIG_LP_ARCH_MIPS) := mips # Three cases where we don't need fully populated $(obj) lists: # 1. when no .config exists diff --git a/payloads/libpayload/Makefile.inc b/payloads/libpayload/Makefile.inc index 4863d3f1da..1b7986cbc6 100644 --- a/payloads/libpayload/Makefile.inc +++ b/payloads/libpayload/Makefile.inc @@ -33,7 +33,6 @@ export KERNELVERSION := 0.2.0 ARCHDIR-$(CONFIG_LP_ARCH_ARM) := arm ARCHDIR-$(CONFIG_LP_ARCH_ARM64) := arm64 -ARCHDIR-$(CONFIG_LP_ARCH_MIPS) := mips ARCHDIR-$(CONFIG_LP_ARCH_X86) := x86 DESTDIR ?= install diff --git a/payloads/libpayload/arch/mips/Kconfig b/payloads/libpayload/arch/mips/Kconfig deleted file mode 100644 index b6e326b967..0000000000 --- a/payloads/libpayload/arch/mips/Kconfig +++ /dev/null @@ -1,24 +0,0 @@ -# -# This file is part of the libpayload project. -# -# Copyright (C) 2014 Imagination Technologies -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; version 2 of -# the License. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# - - -if ARCH_MIPS - -config ARCH_SPECIFIC_OPTIONS # dummy - def_bool y - select LITTLE_ENDIAN - -endif diff --git a/payloads/libpayload/arch/mips/Makefile.inc b/payloads/libpayload/arch/mips/Makefile.inc deleted file mode 100644 index 2bd112f6b8..0000000000 --- a/payloads/libpayload/arch/mips/Makefile.inc +++ /dev/null @@ -1,33 +0,0 @@ -# -# This file is part of the libpayload project. -# -# Copyright (C) 2014 Imagination Technologies -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; version 2 of -# the License. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# - -############################################################################### -CFLAGS += -march=mips32r2 -mxgot - -head.o-y += head.S - -libc-y += cache.c -libc-y += coreboot.c -libc-y += dummy_media.c -libc-y += exception_asm.S -libc-y += exception.c -libc-y += gdb.c -libc-y += main.c -libc-y += selfboot.c -libc-y += sysinfo.c -libc-y += string.c -libc-y += timer.c -libc-y += util.S diff --git a/payloads/libpayload/arch/mips/cache.c b/payloads/libpayload/arch/mips/cache.c deleted file mode 100644 index 4338415c5f..0000000000 --- a/payloads/libpayload/arch/mips/cache.c +++ /dev/null @@ -1,72 +0,0 @@ -/* - * This file is part of the libpayload project. - * - * Copyright (C) 2014 Imagination Technologies - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include - - -void dcache_clean_all(void) -{ - /* TODO */ -} - -void dcache_invalidate_all(void) -{ - /* TODO */ -} -void dcache_clean_invalidate_all(void) -{ - /* TODO */ -} - -void tlb_invalidate_all(void) -{ - /* TODO */ -} - -unsigned int dcache_line_bytes(void) -{ - /* TO DO */ - return 0; -} - -void dcache_mmu_disable(void) -{ - /* TODO */ -} - -void dcache_mmu_enable(void) -{ - /* TODO */ -} - -void cache_sync_instructions(void) -{ - /* TODO */ -} - -void mmu_init(void) -{ - /* TODO */ -} - -void mmu_disable_range(unsigned long start_mb, unsigned long size_mb) -{ - /* TODO */ -} -void mmu_config_range(unsigned long start_mb, unsigned long size_mb, - enum dcache_policy policy) -{ - /* TODO */ -} diff --git a/payloads/libpayload/arch/mips/coreboot.c b/payloads/libpayload/arch/mips/coreboot.c deleted file mode 100644 index e2b5557cba..0000000000 --- a/payloads/libpayload/arch/mips/coreboot.c +++ /dev/null @@ -1,51 +0,0 @@ -/* - * This file is part of the libpayload project. - * - * Copyright (C) 2014 Imagination Technologies - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include - -/* This pointer gets set in head.S and is passed in from coreboot. */ -void *cb_header_ptr; - -static void cb_parse_dma(void *ptr) -{ - struct lb_range *dma = (struct lb_range *)ptr; - init_dma_memory(bus_to_virt(dma->range_start), dma->range_size); -} - -/* Architecture specific */ -int cb_parse_arch_specific(struct cb_record *rec, struct sysinfo_t *info) -{ - switch (rec->tag) { - case CB_TAG_DMA: - cb_parse_dma(rec); - break; - default: - return 0; - } - return 1; - -} - -int get_coreboot_info(struct sysinfo_t *info) -{ - return cb_parse_header(cb_header_ptr, 1, info); -} - -void *get_cb_header_ptr(void) -{ - return cb_header_ptr; -} diff --git a/payloads/libpayload/arch/mips/dummy_media.c b/payloads/libpayload/arch/mips/dummy_media.c deleted file mode 100644 index 112d7feec8..0000000000 --- a/payloads/libpayload/arch/mips/dummy_media.c +++ /dev/null @@ -1,42 +0,0 @@ -/* - * This file is part of the libpayload project. - * - * Copyright (C) 2014 Google, Inc. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. - */ -#define LIBPAYLOAD - -#include - -/* The generic cbfs code relies on the libpayload_init_default_cbfs_media - * symbol. Therefore, provide an implementation that just throws an error. */ - -int libpayload_init_default_cbfs_media(struct cbfs_media *media); - -__attribute__((weak)) int libpayload_init_default_cbfs_media( - struct cbfs_media *media) -{ - return -1; -} diff --git a/payloads/libpayload/arch/mips/exception.c b/payloads/libpayload/arch/mips/exception.c deleted file mode 100644 index e488f2e3bd..0000000000 --- a/payloads/libpayload/arch/mips/exception.c +++ /dev/null @@ -1,103 +0,0 @@ -/* - * This file is part of the libpayload project. - * - * Copyright (C) 2014 Imagination Technologies - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include -#include - -u32 exception_stack[0x400] __attribute__((aligned(8))); -struct exception_state_t exception_state; - -static const char *names[EXC_COUNT] = { - [EXC_CACHE_ERROR] = "Cache error exception", - [EXC_TLB_REFILL_AND_ALL] = "TLB refill or general exception", - [EXC_INTERRUPT] = "Interrupt", - [EXC_EJTAG_DEBUG] = "EJTAG debug exception" -}; - -static void dump_exception_state(void) -{ - printf("%s exception!\n", names[exception_state_ptr->vector]); - printf("\nRegisters:\n"); - printf("ZERO:\t0x%08x\n", exception_state_ptr->regs.zero); - printf("AT:\t0x%08x\n", exception_state_ptr->regs.at); - printf("V0:\t0x%08x\n", exception_state_ptr->regs.v0); - printf("V1:\t0x%08x\n", exception_state_ptr->regs.v1); - printf("A0:\t0x%08x\n", exception_state_ptr->regs.a0); - printf("A1:\t0x%08x\n", exception_state_ptr->regs.a1); - printf("A2:\t0x%08x\n", exception_state_ptr->regs.a2); - printf("A3:\t0x%08x\n", exception_state_ptr->regs.a3); - printf("T0:\t0x%08x\n", exception_state_ptr->regs.t0); - printf("T1:\t0x%08x\n", exception_state_ptr->regs.t1); - printf("T2:\t0x%08x\n", exception_state_ptr->regs.t2); - printf("T3:\t0x%08x\n", exception_state_ptr->regs.t3); - printf("T4:\t0x%08x\n", exception_state_ptr->regs.t4); - printf("T5:\t0x%08x\n", exception_state_ptr->regs.t5); - printf("T6:\t0x%08x\n", exception_state_ptr->regs.t6); - printf("T7:\t0x%08x\n", exception_state_ptr->regs.t7); - printf("S0:\t0x%08x\n", exception_state_ptr->regs.s0); - printf("S1:\t0x%08x\n", exception_state_ptr->regs.s1); - printf("S2:\t0x%08x\n", exception_state_ptr->regs.s2); - printf("S3:\t0x%08x\n", exception_state_ptr->regs.s3); - printf("S4:\t0x%08x\n", exception_state_ptr->regs.s4); - printf("S5:\t0x%08x\n", exception_state_ptr->regs.s5); - printf("S6:\t0x%08x\n", exception_state_ptr->regs.s6); - printf("S7:\t0x%08x\n", exception_state_ptr->regs.s7); - printf("T8:\t0x%08x\n", exception_state_ptr->regs.t8); - printf("T9:\t0x%08x\n", exception_state_ptr->regs.t9); - printf("K0:\t0x%08x\n", exception_state_ptr->regs.k0); - printf("K1:\t0x%08x\n", exception_state_ptr->regs.k1); - printf("GP:\t0x%08x\n", exception_state_ptr->regs.gp); - printf("SP:\t0x%08x\n", exception_state_ptr->regs.sp); - printf("FP:\t0x%08x\n", exception_state_ptr->regs.fp); - printf("RA:\t0x%08x\n", exception_state_ptr->regs.ra); -} - -static void dump_stack(uintptr_t addr, size_t bytes) -{ - int i, j; - const int words_per_line = 8; - int words_to_print; - uint32_t *ptr = (uint32_t *) - (addr & ~(words_per_line * sizeof(*ptr) - 1)); - - printf("Dumping stack:\n"); - words_to_print = bytes/sizeof(*ptr); - for (i = words_to_print; i >= 0; i -= words_per_line) { - printf("%p: ", ptr + i); - for (j = i; j < i + words_per_line; j++) - printf("%08x ", *(ptr + j)); - printf("\n"); - } -} - - -void exception_dispatch(void) -{ - u32 vec = exception_state_ptr->vector; - die_if(vec >= EXC_COUNT || !names[vec], "Bad exception vector %u", vec); - - dump_exception_state(); - dump_stack(exception_state_ptr->regs.sp, 512); - halt(); -} - -void exception_init(void) -{ - exception_stack_end = exception_stack + ARRAY_SIZE(exception_stack); - exception_state_ptr = &exception_state; - exception_init_asm(); -} diff --git a/payloads/libpayload/arch/mips/exception_asm.S b/payloads/libpayload/arch/mips/exception_asm.S deleted file mode 100644 index 118c12d965..0000000000 --- a/payloads/libpayload/arch/mips/exception_asm.S +++ /dev/null @@ -1,200 +0,0 @@ -/* - * This file is part of the libpayload project. - * - * Copyright (C) 2014 Imagination Technologies - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#define STATUS_REGISTER $12,0 -#define BOOT_EXC_VECTOR_MASK (1 << 22) -#define EBASE_REGISTER $15,1 -#define EXCEPTION_BASE_MASK (0xFFFFF000) - - /* Don't reorder instructions */ - .set noreorder - .set noat - - .align 4 - .global exception_stack_end -exception_stack_end: - .word 0 - - .global exception_state_ptr -exception_state_ptr: - .word 0 - -/* Temporary variables. */ -ret_addr: - .word 0 -exception_sp: - .word 0 -vector: - .word 0 - -/* Cache error */ -.org 0x100 - li $v0, 0x0 - la $at, vector - sw $v0, 0x00($at) - b exception_common - nop - -/* TLB refill and all others */ -.org 0x180 - li $v0, 0x1 - la $at, vector - sw $v0, 0x00($at) - b exception_common - nop - -/* Interrupt */ -.org 0x200 - li $v0, 0x2 - la $at, vector - sw $v0, 0x00($at) - b exception_common - nop - -/* EJTAG debug exception */ -.org 0x480 - li $v0, 0x3 - la $at, vector - sw $v0, 0x00($at) - b exception_common - nop - -exception_common: - /* Obtain return address of exception */ - la $v0, ret_addr - sw $ra, 0x00($v0) - - /* Initialize $gp */ - bal 1f - nop - .word _gp -1: - lw $gp, 0($ra) - - la $at, exception_sp - sw $sp, 0x00($at) - lw $sp, exception_state_ptr - - /* Save all registers */ - sw $zero, 0x00($sp) - sw $at, 0x04($sp) - sw $v0, 0x08($sp) - sw $v1, 0x0C($sp) - sw $a0, 0x10($sp) - sw $a1, 0x14($sp) - sw $a2, 0x18($sp) - sw $a3, 0x1C($sp) - sw $t0, 0x20($sp) - sw $t1, 0x34($sp) - sw $t2, 0x28($sp) - sw $t3, 0x2C($sp) - sw $t4, 0x30($sp) - sw $t5, 0x34($sp) - sw $t6, 0x38($sp) - sw $t7, 0x3C($sp) - sw $s0, 0x40($sp) - sw $s1, 0x44($sp) - sw $s2, 0x48($sp) - sw $s3, 0x4C($sp) - sw $s4, 0x50($sp) - sw $s5, 0x54($sp) - sw $s6, 0x58($sp) - sw $s7, 0x5C($sp) - sw $t8, 0x60($sp) - sw $t9, 0x64($sp) - sw $k0, 0x68($sp) - sw $k1, 0x6C($sp) - sw $gp, 0x70($sp) - lw $v0, exception_sp - sw $v0, 0x74($sp) - sw $fp, 0x78($sp) - lw $v0, ret_addr - sw $v0, 0x7C($sp) - lw $v0, vector - sw $v0, 0x80($sp) - - /* Point SP to the stack for C code */ - lw $sp, exception_stack_end - /* Give control to exception dispatch */ - la $a2, exception_dispatch - jalr $a2 - nop - lw $sp, exception_state_ptr - /* Restore registers */ - lw $zero, 0x00($sp) - lw $at, 0x04($sp) - lw $v0, 0x08($sp) - lw $v1, 0x0C($sp) - lw $a0, 0x10($sp) - lw $a1, 0x14($sp) - lw $a2, 0x18($sp) - lw $a3, 0x1C($sp) - lw $t0, 0x20($sp) - lw $t1, 0x24($sp) - lw $t2, 0x28($sp) - lw $t3, 0x2C($sp) - lw $t4, 0x30($sp) - lw $t5, 0x34($sp) - lw $t6, 0x38($sp) - lw $t7, 0x3C($sp) - lw $s0, 0x40($sp) - lw $s1, 0x44($sp) - lw $s2, 0x48($sp) - lw $s3, 0x4C($sp) - lw $s4, 0x50($sp) - lw $s5, 0x54($sp) - lw $s6, 0x58($sp) - lw $s7, 0x5C($sp) - lw $t8, 0x60($sp) - lw $t9, 0x64($sp) - lw $k0, 0x68($sp) - sw $k1, 0x6C($sp) - sw $gp, 0x70($sp) - sw $fp, 0x78($sp) - sw $ra, 0x7C($sp) - /* Return */ - eret - - .global exception_init_asm -exception_init_asm: - .set push - /* Make sure boot exception vector is 1 before writing EBASE */ - mfc0 $t0, STATUS_REGISTER - li $t1, BOOT_EXC_VECTOR_MASK - or $t0, $t0, $t1 - mtc0 $t0, STATUS_REGISTER - - /*Prepare base address */ - la $t1, exception_stack_end - li $t2, EXCEPTION_BASE_MASK - and $t1, $t1, $t2 - - /* Prepare EBASE register value */ - mfc0 $t0, EBASE_REGISTER - li $t2, ~(EXCEPTION_BASE_MASK) - and $t0, $t0, $t2 - /* Filling base address */ - or $t0, $t0, $t1 - mtc0 $t0, EBASE_REGISTER - - /* Clear boot exception vector bit for EBASE value to take effect */ - mfc0 $t0, STATUS_REGISTER - li $t1, ~BOOT_EXC_VECTOR_MASK - and $t0, $t0, $t1 - mtc0 $t0, STATUS_REGISTER - - .set pop - /* Return */ - jr $ra diff --git a/payloads/libpayload/arch/mips/gdb.c b/payloads/libpayload/arch/mips/gdb.c deleted file mode 100644 index 7fd741aeb1..0000000000 --- a/payloads/libpayload/arch/mips/gdb.c +++ /dev/null @@ -1,27 +0,0 @@ -/* - * This file is part of the libpayload project. - * - * Copyright (C) 2014 Imagination Technologies - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - - -#include -#include - - -void gdb_arch_init(void) -{ -} - -void gdb_arch_enter(void) -{ -} diff --git a/payloads/libpayload/arch/mips/head.S b/payloads/libpayload/arch/mips/head.S deleted file mode 100644 index 203e0ae1bf..0000000000 --- a/payloads/libpayload/arch/mips/head.S +++ /dev/null @@ -1,96 +0,0 @@ -/* - * This file is part of the libpayload project. - * - * Copyright (C) 2014 Imagination Technologies - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include - - /* Disable interrupts and mark the kernel mode */ - .macro setup_c0_status clr - .set push - mfc0 $t0, $CP0_STATUS - or $t0, ST0_CU0 | 0x1f | \clr - xor $t0, 0x1f | \clr - mtc0 $t0, $CP0_STATUS - .set noreorder - sll $zero, 3 - .set pop - .endm - - /* Don't reorder instructions */ - .set noreorder - - .align 4 - - .global cb_header_ptr -cb_header_ptr: - .word 0 - - .global old_sp -old_sp: - .word 0 - - - .global _entry, _leave - .text - -/* Our entry point */ -_entry: - - /* - * This function saves off the previous stack and switches us to our - * own execution environment. - */ - - /* Clear watch and cause registers */ - mtc0 $zero, $CP0_WATCHLO - mtc0 $zero, $CP0_WATCHHI - mtc0 $zero, $CP0_CAUSE - - /* Disable interrupts */ - setup_c0_status 0 - - /* Don't use at in synthetic instr. */ - .set noat - - /* Init timer */ - mtc0 $zero, $CP0_COUNT - mtc0 $zero, $CP0_COMPARE - - /* Initialize $gp */ - bal 1f - nop - .word _gp -1: - lw $gp, 0($ra) - - /* Save off the location of the coreboot tables */ - la $at, cb_header_ptr - sw $a0, 0x00($at) - - /* Save old stack pointer */ - la $at, old_sp - sw $sp, 0x00($at) - - /* Setup new stack */ - la $sp, _stack - - /* Let's rock */ - la $a2, start_main - jalr $a2 - nop -_leave: - /* Restore old stack. */ - lw $sp, old_sp - /* Return to the original context. */ - eret diff --git a/payloads/libpayload/arch/mips/libpayload.ldscript b/payloads/libpayload/arch/mips/libpayload.ldscript deleted file mode 100644 index 351c2254fb..0000000000 --- a/payloads/libpayload/arch/mips/libpayload.ldscript +++ /dev/null @@ -1,86 +0,0 @@ -/* - * This file is part of the libpayload project. - * - * Copyright (C) 2014 Imagination Technologies - * - * Based on src/arch/arm/ramstage.ld: - * Written by Johan Rydberg, based on work by Daniel Kahlin. - * Rewritten by Eric Biederman - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -OUTPUT_ARCH(mips) - -ENTRY(_entry) - -SECTIONS -{ - . = CONFIG_LP_BASE_ADDRESS; - - . = ALIGN(16); - _start = .; - - .text : { - *(.text._entry) - *(.text) - *(.text.*) - } - - .rodata : { - *(.rodata) - *(.rodata.*) - } - - .data : { - *(.data) - *(.data.*) - } - - _edata = .; - - .sdata : { - *(.srodata) - *(.sdata) - } - - _bss = .; - .bss : { - *(.sbss) - *(.sbss.*) - *(.bss) - *(.bss.*) - *(COMMON) - - /* Stack and heap */ - - . = ALIGN(16); - _heap = .; - . += CONFIG_LP_HEAP_SIZE; - . = ALIGN(16); - _eheap = .; - - _estack = .; - . += CONFIG_LP_STACK_SIZE; - . = ALIGN(16); - _stack = .; - } - _ebss = .; - - _end = .; - - /DISCARD/ : { - *(.comment) - *(.note*) - *(.reginfo) - - } -} diff --git a/payloads/libpayload/arch/mips/main.c b/payloads/libpayload/arch/mips/main.c deleted file mode 100644 index 7a71f90fa6..0000000000 --- a/payloads/libpayload/arch/mips/main.c +++ /dev/null @@ -1,58 +0,0 @@ -/* - * This file is part of the libpayload project. - * - * Copyright (C) 2014 Imagination Technologies - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include - -/* The argc value to pass to main() */ -int main_argc; -/* The argv value to pass to main() */ -char *main_argv[MAX_ARGC_COUNT]; - -/* - * This is our C entry function - set up the system - * and jump into the payload entry point. - */ -void start_main(void); -void start_main(void) -{ - extern int main(int argc, char **argv); - - /* Gather system information. */ - lib_get_sysinfo(); - - /* Optionally set up the consoles. */ -#if !CONFIG(LP_SKIP_CONSOLE_INIT) - console_init(); -#endif - - exception_init(); - /* - * Any other system init that has to happen before the - * user gets control goes here - */ - - /* - * Go to the entry point. - * In the future we may care about the return value. - */ - - (void) main(main_argc, (main_argc != 0) ? main_argv : NULL); - - /* - * Returning here will go to the _leave function to return - * us to the original context. - */ -} diff --git a/payloads/libpayload/arch/mips/selfboot.c b/payloads/libpayload/arch/mips/selfboot.c deleted file mode 100644 index c69583134c..0000000000 --- a/payloads/libpayload/arch/mips/selfboot.c +++ /dev/null @@ -1,36 +0,0 @@ -/* - * Copyright 2014 Google Inc. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. - */ - -#include - -extern void *cb_header_ptr; - -void selfboot(void *entry) -{ - void (*entry_func)(void *) = entry; - entry_func(cb_header_ptr); -} diff --git a/payloads/libpayload/arch/mips/string.c b/payloads/libpayload/arch/mips/string.c deleted file mode 100644 index 79cc8d260a..0000000000 --- a/payloads/libpayload/arch/mips/string.c +++ /dev/null @@ -1,77 +0,0 @@ - /* - * This file is part of the libpayload project. - * - * Copyright (C) 2014 Imagination Technologies - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include "string.h" - -/* - * Alternative string functions to the default ones are added - * because there is no guarantee that the provided source and - * destination addresses are properly aligned; - * The default string functions work with multiple of 4 bytes - * (sizeof(unsinged long)); MIPS will use LW/SW instructions - * for these operations and if the source and destination - * addresses are not aligned it will trigger an exception. - */ - -void *memcpy(void *dest, const void *src, size_t n) -{ - u8 *ptr_d = dest; - const u8 *ptr_s = src; - size_t i; - - for (i = 0; i < n; i++) - *ptr_d++ = *ptr_s++; - - return dest; -} - -void *memmove(void *dest, const void *src, size_t n) -{ - if ((src < dest) && (dest - src < n)) { - u8 *ptr_d = dest; - const u8 *ptr_s = src; - - /* copy backwards */ - while (n--) - ptr_d[n] = ptr_s[n]; - - return dest; - } - - /* copy forwards */ - return memcpy(dest, src, n); -} - -void *memset(void *s, int c, size_t n) -{ - u8 *ptr = s; - size_t i; - - for (i = 0; i < n; i++) - *ptr++ = c; - - return s; -} - -int memcmp(const void *s1, const void *s2, size_t n) -{ - size_t i; - - for (i = 0; i < n; i++) - if (((u8 *)s1)[i] != ((u8 *)s2)[i]) - return ((u8 *)s1)[i] - ((u8 *)s2)[i]; - return 0; -} diff --git a/payloads/libpayload/arch/mips/sysinfo.c b/payloads/libpayload/arch/mips/sysinfo.c deleted file mode 100644 index 49c6c84feb..0000000000 --- a/payloads/libpayload/arch/mips/sysinfo.c +++ /dev/null @@ -1,49 +0,0 @@ -/* - * This file is part of the libpayload project. - * - * Copyright (C) 2014 Imagination Technologies - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include -#include - -/* - * This is a global structure that is used through the library - we set it - * up initially with some dummy values - hopefully they will be overridden. - */ -struct sysinfo_t lib_sysinfo = { - .cpu_khz = 200, -}; - -int lib_get_sysinfo(void) -{ - int ret; - - /* Get the CPU speed (for delays). */ - lib_sysinfo.cpu_khz = get_cpu_speed(); - - /* Get information from the coreboot tables, - * if they exist */ - ret = get_coreboot_info(&lib_sysinfo); - - /* If we can't get a good memory range, use the default. */ - if (!lib_sysinfo.n_memranges) { - lib_sysinfo.n_memranges = 1; - lib_sysinfo.memrange[0].base = 0; - lib_sysinfo.memrange[0].size = 1024 * 1024; - lib_sysinfo.memrange[0].type = CB_MEM_RAM; - } - - return ret; -} diff --git a/payloads/libpayload/arch/mips/timer.c b/payloads/libpayload/arch/mips/timer.c deleted file mode 100644 index a066f676d1..0000000000 --- a/payloads/libpayload/arch/mips/timer.c +++ /dev/null @@ -1,52 +0,0 @@ -/* - * This file is part of the libpayload project. - * - * Copyright (C) 2014 Imagination Technologies - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include - -#define PISTACHIO_CLOCK_SWITCH 0xB8144200 -#define MIPS_EXTERN_PLL_BYPASS_MASK 0x00000002 - -/** - * @ingroup arch - * Global variable containing the speed of the processor in KHz. - */ -u32 cpu_khz; - -/** - * Calculate the speed of the processor for use in delays. - * - * @return The CPU speed in kHz. - */ -unsigned int get_cpu_speed(void) -{ - if (IMG_PLATFORM_ID() != IMG_PLATFORM_ID_SILICON) - cpu_khz = 50000; /* FPGA board */ - else { - /* If MIPS PLL external bypass bit is set, it means - * that the MIPS PLL is already set up to work at a - * frequency of 550 MHz; otherwise, the crystal is - * used with a frequency of 52 MHz - */ - if (read32(PISTACHIO_CLOCK_SWITCH) & - MIPS_EXTERN_PLL_BYPASS_MASK) - cpu_khz = 550000; - else - cpu_khz = 52000; - } - - return cpu_khz; -} diff --git a/payloads/libpayload/arch/mips/util.S b/payloads/libpayload/arch/mips/util.S deleted file mode 100644 index 986a34c5d4..0000000000 --- a/payloads/libpayload/arch/mips/util.S +++ /dev/null @@ -1,22 +0,0 @@ -/* - * This file is part of the libpayload project. - * - * Copyright (C) 2014 Imagination Technologies - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - - .global halt - .text - .align 4 - .type halt, function -halt: - j halt - nop diff --git a/payloads/libpayload/bin/lpgcc b/payloads/libpayload/bin/lpgcc index b3ef342ff2..c233f82950 100755 --- a/payloads/libpayload/bin/lpgcc +++ b/payloads/libpayload/bin/lpgcc @@ -80,12 +80,6 @@ if [ "$CONFIG_LP_ARCH_ARM64" = "y" ]; then _ARCHEXTRA="" _ARCH=arm64 fi -if [ "$CONFIG_LP_ARCH_MIPS" = "y" ]; then - _ARCHINCDIR=$_INCDIR/mips - _ARCHLIBDIR=$_LIBDIR/mips - _ARCHEXTRA="" - _ARCH=mips -fi if [ "$CONFIG_LP_ARCH_X86" = "y" ]; then _ARCHINCDIR=$_INCDIR/x86 _ARCHLIBDIR=$_LIBDIR/x86 @@ -170,9 +164,7 @@ if [ $DOLINK -eq 0 ]; then $DEFAULT_CC $CMDLINE $_CFLAGS else - if [ -z "${CONFIG_LP_ARCH_MIPS}" ]; then - _LIBGCC=`$DEFAULT_CC $_ARCHEXTRA -print-libgcc-file-name` - fi + _LIBGCC=`$DEFAULT_CC $_ARCHEXTRA -print-libgcc-file-name` if [ -f $_ARCHLIBDIR/head.o ]; then HEAD_O=$_ARCHLIBDIR/head.o elif [ -f $BASE/../build/head.o ]; then diff --git a/payloads/libpayload/configs/defconfig-mips b/payloads/libpayload/configs/defconfig-mips deleted file mode 100644 index 4a0a914ac3..0000000000 --- a/payloads/libpayload/configs/defconfig-mips +++ /dev/null @@ -1,6 +0,0 @@ -CONFIG_LP_ARCH_MIPS=y -CONFIG_LP_COREBOOT_VIDEO_CONSOLE=y -CONFIG_LP_PC_KEYBOARD=y -CONFIG_LP_TIMER_IMG_PISTACHIO=y -# CONFIG_LP_USB_EHCI is not set -# CONFIG_LP_USB_XHCI is not set diff --git a/payloads/libpayload/drivers/timer/img_pistachio.c b/payloads/libpayload/drivers/timer/img_pistachio.c deleted file mode 100644 index d11c3ff283..0000000000 --- a/payloads/libpayload/drivers/timer/img_pistachio.c +++ /dev/null @@ -1,38 +0,0 @@ -/* - * This file is part of the libpayload project. - * - * Copyright (C) 2014 Imagination Technologies - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include - -uint64_t timer_hz(void) -{ - return (uint64_t)lib_sysinfo.cpu_khz * 1000; -} - -uint64_t timer_raw_value(void) -{ - static uint64_t total_ticks = 0; - uint8_t overflow = 0; - uint32_t current_ticks = read_c0_count() * 2; - - /* It assumes only one overflow happened since the last call */ - if (current_ticks <= (uint32_t)total_ticks) - overflow = 1; - /* The least significant part(32 bits) of total_ticks will always - * become equal to current ticks */ - total_ticks = (((total_ticks >> 32) + overflow) << 32) + - current_ticks; - return total_ticks; -} diff --git a/payloads/libpayload/include/mips/arch/byteorder.h b/payloads/libpayload/include/mips/arch/byteorder.h deleted file mode 100644 index 40412d232c..0000000000 --- a/payloads/libpayload/include/mips/arch/byteorder.h +++ /dev/null @@ -1,39 +0,0 @@ -/* - * This file is part of the libpayload project. - * - * Copyright (C) 2014 Imagination Technologies - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef __MIPS_ARCH_BYTEORDER_H__ -#define __MIPS_ARCH_BYTEORDER_H__ - -#include -#include - -#ifndef __ORDER_LITTLE_ENDIAN__ -#error "What endian are you!?" -#endif - -#define cpu_to_le64(x) ((uint64_t)(x)) -#define le64_to_cpu(x) ((uint64_t)(x)) -#define cpu_to_le32(x) ((uint32_t)(x)) -#define le32_to_cpu(x) ((uint32_t)(x)) -#define cpu_to_le16(x) ((uint16_t)(x)) -#define le16_to_cpu(x) ((uint16_t)(x)) -#define cpu_to_be64(x) swab64(x) -#define be64_to_cpu(x) swab64(x) -#define cpu_to_be32(x) swab32((x)) -#define be32_to_cpu(x) swab32((x)) -#define cpu_to_be16(x) swab16((x)) -#define be16_to_cpu(x) swab16((x)) - -#endif /* __MIPS_ARCH_BYTEORDER_H__ */ diff --git a/payloads/libpayload/include/mips/arch/cache.h b/payloads/libpayload/include/mips/arch/cache.h deleted file mode 100644 index e65a2a00ae..0000000000 --- a/payloads/libpayload/include/mips/arch/cache.h +++ /dev/null @@ -1,94 +0,0 @@ -/* - * This file is part of the libpayload project. - * - * Copyright (C) 2014 Imagination Technologies - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef __MIPS_ARCH_CACHE_H__ -#define __MIPS_ARCH_CACHE_H__ - - -#include -#include - - -/* - * Sync primitives - */ - -/* data memory barrier */ -static inline void dmb(void) -{ - /* TODO */ -} - -/* data sync barrier */ -static inline void dsb(void) -{ - /* TODO */ -} - -/* instruction sync barrier */ -static inline void isb(void) -{ - /* TODO */ -} - - -/* - * Cache maintenance API - */ - -/* dcache clean and invalidate all */ -void dcache_clean_invalidate_all(void); - -/* dcache clean all */ -void dcache_clean_all(void); - -/* dcache invalidate all (on current level given by CCSELR) */ -void dcache_invalidate_all(void); - -/* returns number of bytes per cache line */ -unsigned int dcache_line_bytes(void); - -/* dcache and MMU disable */ -void dcache_mmu_disable(void); - -/* dcache and MMU enable */ -void dcache_mmu_enable(void); - -/* perform all icache/dcache maintenance needed after loading new code */ -void cache_sync_instructions(void); - -/* tlb invalidate all */ -void tlb_invalidate_all(void); - -/* - * Generalized setup/init functions - */ - -/* mmu initialization (set page table address, set permissions, etc) */ -void mmu_init(void); - -enum dcache_policy { - DCACHE_OFF, - DCACHE_WRITEBACK, - DCACHE_WRITETHROUGH, -}; - -/* disable the mmu for a range. Primarily useful to lock out address 0. */ -void mmu_disable_range(unsigned long start_mb, unsigned long size_mb); -/* mmu range configuration (set dcache policy) */ -void mmu_config_range(unsigned long start_mb, unsigned long size_mb, - enum dcache_policy policy); - -#endif /* __MIPS_ARCH_CACHE_H__ */ diff --git a/payloads/libpayload/include/mips/arch/cpu.h b/payloads/libpayload/include/mips/arch/cpu.h deleted file mode 100644 index 93e42ea455..0000000000 --- a/payloads/libpayload/include/mips/arch/cpu.h +++ /dev/null @@ -1,92 +0,0 @@ -/* - * This file is part of the libpayload project. - * - * Copyright (C) 2014 Imagination Technologies - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ - -#ifndef __MIPS_ARCH_CPU_H__ -#define __MIPS_ARCH_CPU_H__ - -/* - * Reading at this address allows to identify the platform the code is running - * on - */ - -/* - * This register holds the FPGA image version - * If we're not working on the FPGA this will be 0 - */ -#define PRIMARY_FPGA_VERSION 0xB8149060 -#define IMG_PLATFORM_ID() read32(PRIMARY_FPGA_VERSION) -#define IMG_PLATFORM_ID_FPGA 0xD1400003 /* Last FPGA image */ -#define IMG_PLATFORM_ID_SILICON 0 - -#define CP0_COUNT 9 -#define CP0_COMPARE 11 -#define CP0_STATUS 12 -#define CP0_CAUSE 13 -#define CP0_WATCHLO 18 -#define CP0_WATCHHI 19 - -/* coprocessor 0 enable */ -#define ST0_CU0 (1 << 28) -#define C0_CAUSE_DC (1 << 27) - -/*************************************************************************** - * The following section was copied from arch/mips/include/asm/mipsregs.h in - * the 3.14 kernel tree. - */ - -/* - * Macros to access the system control coprocessor - */ - -#define __read_32bit_c0_register(source, sel) \ -({ int __res; \ - if (sel == 0) \ - __asm__ __volatile__( \ - "mfc0\t%0, " #source "\n\t" \ - : "=r" (__res)); \ - else \ - __asm__ __volatile__( \ - ".set\tmips32\n\t" \ - "mfc0\t%0, " #source ", " #sel "\n\t" \ - ".set\tmips0\n\t" \ - : "=r" (__res)); \ - __res; \ -}) - -#define __write_32bit_c0_register(register, sel, value) \ -do { \ - if (sel == 0) \ - __asm__ __volatile__( \ - "mtc0\t%z0, " #register "\n\t" \ - : : "Jr" ((unsigned int)(value))); \ - else \ - __asm__ __volatile__( \ - ".set\tmips32\n\t" \ - "mtc0\t%z0, " #register ", " #sel "\n\t" \ - ".set\tmips0" \ - : : "Jr" ((unsigned int)(value))); \ -} while (0) - -/* Shortcuts to access various internal registers, keep adding as needed. */ -#define read_c0_count() __read_32bit_c0_register($9, 0) -#define write_c0_count(val) __write_32bit_c0_register($9, 0, (val)) - -#define read_c0_cause() __read_32bit_c0_register($13, 0) -#define write_c0_cause(val) __write_32bit_c0_register($13, 0, (val)) -/***************************************************************************/ - -#endif /* __MIPS_ARCH_CPU_H__ */ diff --git a/payloads/libpayload/include/mips/arch/exception.h b/payloads/libpayload/include/mips/arch/exception.h deleted file mode 100644 index 27f0b6417b..0000000000 --- a/payloads/libpayload/include/mips/arch/exception.h +++ /dev/null @@ -1,86 +0,0 @@ -/* - * This file is part of the libpayload project. - * - * Copyright (C) 2014 Imagination Technologies - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef __MIPS_ARCH_EXCEPTION_H__ -#define __MIPS_ARCH_EXCEPTION_H__ - -#include - -void exception_init_asm(void); -void exception_dispatch(void); - -struct exception_state_t { - struct { - /* Always 0: just to keep the series complete */ - u32 zero; - /* Reserved for the assembler */ - /* TODO: is this actually needed here? */ - u32 at; - /* v0-v1: expression evaluation */ - u32 v0; - u32 v1; - /* a0-a3: Arguments */ - u32 a0; - u32 a1; - u32 a2; - u32 a3; - /* t0-t3: Temporary registers for expression evaluation */ - u32 t0; - u32 t1; - u32 t2; - u32 t3; - u32 t4; - u32 t5; - u32 t6; - u32 t7; - /* s0-s7: Saved registers */ - u32 s0; - u32 s1; - u32 s2; - u32 s3; - u32 s4; - u32 s5; - u32 s6; - u32 s7; - /* t8-t9: Temporary registers for expression evaluation */ - u32 t8; - u32 t9; - /* k0-k1: reserved for SO kernel */ - u32 k0; - u32 k1; - /* Global pointer */ - u32 gp; - /* Stack pointer */ - u32 sp; - /* Frame pointer */ - u32 fp; - /* Return address */ - u32 ra; - } regs; - u32 vector; -} __packed; - -extern struct exception_state_t *exception_state_ptr; -extern u32 *exception_stack_end; - -enum { - EXC_CACHE_ERROR = 0, - EXC_TLB_REFILL_AND_ALL = 1, - EXC_INTERRUPT = 2, - EXC_EJTAG_DEBUG = 3, - EXC_COUNT -}; - -#endif /* __MIPS_ARCH_EXCEPTION_H__ */ diff --git a/payloads/libpayload/include/mips/arch/io.h b/payloads/libpayload/include/mips/arch/io.h deleted file mode 100644 index f86f45fbd5..0000000000 --- a/payloads/libpayload/include/mips/arch/io.h +++ /dev/null @@ -1,63 +0,0 @@ -/* - * This file is part of the libpayload project. - * - * Copyright (C) 2014 Imagination Technologies - * - * Based on arch/armv7/include/arch/io.h: - * Copyright 2013 Google Inc. - * Copyright (C) 1996-2000 Russell King - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef __MIPS_ARCH_IO_H__ -#define __MIPS_ARCH_IO_H__ - -#include -#include -#include - -#define read8(a) (*(volatile uint8_t *) (a)) -#define read16(a) (*(volatile uint16_t *) (a)) -#define read32(a) (*(volatile uint32_t *) (a)) - -#define write8(v, a) (*(volatile uint8_t *) (a) = (v)) -#define write16(v, a) (*(volatile uint16_t *) (a) = (v)) -#define write32(v, a) (*(volatile uint32_t *) (a) = (v)) - - -/* - * Clear and set bits in one shot. These macros can be used to clear and - * set multiple bits in a register using a single call. These macros can - * also be used to set a multiple-bit bit pattern using a mask, by - * specifying the mask in the 'clear' parameter and the new bit pattern - * in the 'set' parameter. - */ - -#define out_arch(type, endian, a, v) write##type(cpu_to_##endian(v), a) -#define in_arch(type, endian, a) endian##_to_cpu(read##type(a)) - -#define readb(a) read8(a) -#define readw(a) read16(a) -#define readl(a) read32(a) - -#define inb(a) read8(a) -#define inw(a) read16(a) -#define inl(a) read32(a) - -#define writeb(v, a) write8(v, a) -#define writew(v, a) write16(v, a) -#define writel(v, a) write32(v, a) - -#define outb(v, a) write8(v, a) -#define outw(v, a) write16(v, a) -#define outl(v, a) write32(v, a) - -#endif /* __MIPS_ARCH_IO_H__ */ diff --git a/payloads/libpayload/include/mips/arch/stdint.h b/payloads/libpayload/include/mips/arch/stdint.h deleted file mode 100644 index 18fa54f531..0000000000 --- a/payloads/libpayload/include/mips/arch/stdint.h +++ /dev/null @@ -1,91 +0,0 @@ -/* - * This file is part of the libpayload project. - * - * Based on src/arch/armv7/include/stdint.h - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef __MIPS_STDINT_H__ -#define __MIPS_STDINT_H__ - -#if defined(__GNUC__) -#define __HAVE_LONG_LONG__ 1 -#else -#define __HAVE_LONG_LONG__ 0 -#endif - -/* Exact integral types */ -typedef unsigned char uint8_t; -typedef signed char int8_t; - -typedef unsigned short uint16_t; -typedef signed short int16_t; - -typedef unsigned int uint32_t; -typedef signed int int32_t; - -#if __HAVE_LONG_LONG__ -typedef unsigned long long uint64_t; -typedef signed long long int64_t; -#endif - -/* Small types */ -typedef unsigned char uint_least8_t; -typedef signed char int_least8_t; - -typedef unsigned short uint_least16_t; -typedef signed short int_least16_t; - -typedef unsigned int uint_least32_t; -typedef signed int int_least32_t; - -#if __HAVE_LONG_LONG__ -typedef unsigned long long uint_least64_t; -typedef signed long long int_least64_t; -#endif - -/* Fast Types */ -typedef unsigned char uint_fast8_t; -typedef signed char int_fast8_t; - -typedef unsigned int uint_fast16_t; -typedef signed int int_fast16_t; - -typedef unsigned int uint_fast32_t; -typedef signed int int_fast32_t; - -#if __HAVE_LONG_LONG__ -typedef unsigned long long uint_fast64_t; -typedef signed long long int_fast64_t; -#endif - -/* Largest integral types */ -#if __HAVE_LONG_LONG__ -typedef long long int intmax_t; -typedef unsigned long long uintmax_t; -#else -typedef long int intmax_t; -typedef unsigned long int uintmax_t; -#endif - -typedef uint8_t u8; -typedef uint16_t u16; -typedef uint32_t u32; -#if __HAVE_LONG_LONG__ -typedef uint64_t u64; -#endif -typedef int8_t s8; -typedef int16_t s16; -typedef int32_t s32; - -#undef __HAVE_LONG_LONG__ - -#endif /* __MIPS_STDINT_H__ */ diff --git a/payloads/libpayload/include/mips/arch/types.h b/payloads/libpayload/include/mips/arch/types.h deleted file mode 100644 index afa3a37e87..0000000000 --- a/payloads/libpayload/include/mips/arch/types.h +++ /dev/null @@ -1,72 +0,0 @@ -/* - * This file is part of the libpayload project. - * - * Copyright (C) 2014 Imagination Technologies - * - * Based on src/arch/armv7/include/arch/types.h - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef __MIPS_ARCH_TYPES_H -#define __MIPS_ARCH_TYPES_H - -#include - -typedef unsigned short umode_t; - -/* - * __xx is ok: it doesn't pollute the POSIX namespace. Use these in the - * header files exported to user space - */ - -typedef __signed__ char __s8; -typedef unsigned char __u8; - -typedef __signed__ short __s16; -typedef unsigned short __u16; - -typedef __signed__ int __s32; -typedef unsigned int __u32; - -#if defined(__GNUC__) -__extension__ typedef __signed__ long long __s64; -__extension__ typedef unsigned long long __u64; -#endif - -typedef signed char s8; -typedef unsigned char u8; - -typedef signed short s16; -typedef unsigned short u16; - -typedef signed int s32; -typedef unsigned int u32; - -typedef signed long long s64; -typedef unsigned long long u64; - -#define BITS_PER_LONG 32 - -/* Dma addresses are 32-bits wide. */ - -typedef u32 dma_addr_t; - -typedef unsigned long phys_addr_t; -typedef unsigned long phys_size_t; - -typedef long time_t; -typedef long suseconds_t; - -#ifndef NULL -#define NULL ((void *)0) -#endif - -#endif /* __MIPS_ARCH_TYPES_H */ diff --git a/payloads/libpayload/include/mips/arch/virtual.h b/payloads/libpayload/include/mips/arch/virtual.h deleted file mode 100644 index da791eecdf..0000000000 --- a/payloads/libpayload/include/mips/arch/virtual.h +++ /dev/null @@ -1,34 +0,0 @@ -/* - * This file is part of the libpayload project. - * - * Copyright (C) 2014 Imagination Technologies - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef __MIPS_ARCH_VIRTUAL_H -#define __MIPS_ARCH_VIRTUAL_H - -#define KSEG0_BASE 0x80000000 -#define KSEG1_BASE 0xA0000000 - -#define kseg0_to_phys(virt) ((unsigned long)(virt) - KSEG0_BASE) -#define phys_to_kseg0(phys) ((void *)((unsigned long)(phys) + KSEG0_BASE)) - -#define kseg1_to_phys(virt) ((unsigned long)(virt) - KSEG1_BASE) -#define phys_to_kseg1(phys) ((void *)((unsigned long)(phys) + KSEG1_BASE)) - -#define virt_to_phys(virt) ((unsigned long)(virt)) -#define phys_to_virt(phys) ((void *)(unsigned long)(phys)) - -#define virt_to_bus(virt) kseg1_to_phys(virt) -#define bus_to_virt(phys) phys_to_kseg1(phys) - -#endif diff --git a/payloads/libpayload/libc/64bit_div.c b/payloads/libpayload/libc/64bit_div.c deleted file mode 100644 index 5cd5bc5e95..0000000000 --- a/payloads/libpayload/libc/64bit_div.c +++ /dev/null @@ -1,141 +0,0 @@ -/* - * This file is part of the libpayload project. - * - * Copyright 2014 Google Inc. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. - */ - -#include -#include - -#if !CONFIG(LP_LITTLE_ENDIAN) -#error this code is for little endian only -#endif - -union overlay64 { - uint64_t longw; - struct { - uint32_t lower; - uint32_t higher; - } words; -}; - - -uint64_t __ashldi3(uint64_t num, unsigned shift) -{ - union overlay64 output; - - output.longw = num; - if (shift >= 32) { - output.words.higher = output.words.lower << (shift - 32); - output.words.lower = 0; - } else { - if (!shift) - return num; - output.words.higher = (output.words.higher << shift) | - (output.words.lower >> (32 - shift)); - output.words.lower = output.words.lower << shift; - } - return output.longw; -} - -uint64_t __lshrdi3(uint64_t num, unsigned shift) -{ - union overlay64 output; - - output.longw = num; - if (shift >= 32) { - output.words.lower = output.words.higher >> (shift - 32); - output.words.higher = 0; - } else { - if (!shift) - return num; - output.words.lower = output.words.lower >> shift | - (output.words.higher << (32 - shift)); - output.words.higher = output.words.higher >> shift; - } - return output.longw; -} - -#define MAX_32BIT_UINT ((((uint64_t)1) << 32) - 1) - -static uint64_t _64bit_divide(uint64_t dividend, - uint64_t divider, uint64_t *rem_p) -{ - uint64_t result = 0; - - /* - * If divider is zero - let the rest of the system care about the - * exception. - */ - if (!divider) - return 1/(uint32_t)divider; - - /* As an optimization, let's not use 64 bit division unless we must. */ - if (dividend <= MAX_32BIT_UINT) { - if (divider > MAX_32BIT_UINT) { - result = 0; - if (rem_p) - *rem_p = divider; - } else { - result = (uint32_t) dividend / (uint32_t) divider; - if (rem_p) - *rem_p = (uint32_t) dividend % - (uint32_t) divider; - } - return result; - } - - while (divider <= dividend) { - uint64_t locald = divider; - uint64_t limit = __lshrdi3(dividend, 1); - int shifts = 0; - - while (locald <= limit) { - shifts++; - locald = locald + locald; - } - result |= __ashldi3(1, shifts); - dividend -= locald; - } - - if (rem_p) - *rem_p = dividend; - - return result; -} - -uint64_t __udivdi3(uint64_t num, uint64_t den) -{ - return _64bit_divide(num, den, NULL); -} - -uint64_t __umoddi3(uint64_t num, uint64_t den) -{ - uint64_t v = 0; - - _64bit_divide(num, den, &v); - return v; -} diff --git a/payloads/libpayload/libc/Makefile.inc b/payloads/libpayload/libc/Makefile.inc index edef62cc4d..348dc117ea 100644 --- a/payloads/libpayload/libc/Makefile.inc +++ b/payloads/libpayload/libc/Makefile.inc @@ -39,7 +39,3 @@ libc-$(CONFIG_LP_LIBC) += hexdump.c libc-$(CONFIG_LP_LIBC) += die.c libc-$(CONFIG_LP_LIBC) += coreboot.c libc-$(CONFIG_LP_LIBC) += fmap.c - -ifeq ($(CONFIG_LP_ARCH_MIPS),y) -libc-$(CONFIG_LP_LIBC) += 64bit_div.c -endif diff --git a/payloads/libpayload/sample/Makefile b/payloads/libpayload/sample/Makefile index 18121dfe80..b67d876efa 100644 --- a/payloads/libpayload/sample/Makefile +++ b/payloads/libpayload/sample/Makefile @@ -34,7 +34,6 @@ include ../.xcompile ARCH-$(CONFIG_LP_ARCH_ARM) := arm ARCH-$(CONFIG_LP_ARCH_X86) := x86_32 ARCH-$(CONFIG_LP_ARCH_ARM64) := arm64 -ARCH-$(CONFIG_LP_ARCH_MIPS) := mips CC := $(CC_$(ARCH-y)) AS := $(AS_$(ARCH-y)) diff --git a/src/arch/mips/Kconfig b/src/arch/mips/Kconfig deleted file mode 100644 index 9df514b21b..0000000000 --- a/src/arch/mips/Kconfig +++ /dev/null @@ -1,38 +0,0 @@ -# -# This file is part of the coreboot project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; version 2 of -# the License. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# - -config ARCH_MIPS - bool - -if ARCH_MIPS - -config ARCH_BOOTBLOCK_MIPS - bool - default n - select BOOTBLOCK_CUSTOM - select C_ENVIRONMENT_BOOTBLOCK - -config ARCH_VERSTAGE_MIPS - bool - default n - -config ARCH_ROMSTAGE_MIPS - bool - default n - -config ARCH_RAMSTAGE_MIPS - bool - default n - -endif # if ARCH_MIPS diff --git a/src/arch/mips/Makefile.inc b/src/arch/mips/Makefile.inc deleted file mode 100644 index 7130abaaa0..0000000000 --- a/src/arch/mips/Makefile.inc +++ /dev/null @@ -1,93 +0,0 @@ -# -# This file is part of the coreboot project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; version 2 of -# the License. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# - -############################################################################### -# MIPS specific options -############################################################################### - -ifeq ($(CONFIG_ARCH_RAMSTAGE_MIPS),y) -check-ramstage-overlap-regions += stack -endif - -############################################################################### -# bootblock -############################################################################### - -ifeq ($(CONFIG_ARCH_BOOTBLOCK_MIPS),y) - -bootblock-y += boot.c -bootblock-y += bootblock.S -bootblock-y += bootblock_simple.c -bootblock-y += cache.c -bootblock-y += mmu.c -bootblock-y += stages.c -bootblock-y += ../../lib/memcpy.c -bootblock-y += ../../lib/memmove.c -bootblock-y += ../../lib/memset.c - -# Much of the assembly code is generated by the compiler, and may contain -# terms which the preprocessor will happily go on to replace. For example -# "mips" would be replaced with "1". Clear all the built in definitions to -# prevent that. -bootblock-S-ccopts += -undef - -$(objcbfs)/bootblock.debug: $$(bootblock-objs) $(obj)/config.h - @printf " LINK $(subst $(obj)/,,$(@))\n" - $(LD_bootblock) $(LDFLAGS_bootblock) -o $@ -L$(obj) -T $(call src-to-obj,bootblock,src/mainboard/$(MAINBOARDDIR)/memlayout.ld) --whole-archive --start-group $(filter-out %.ld,$(bootblock-objs)) --end-group - -endif # CONFIG_ARCH_BOOTBLOCK_MIPS - -############################################################################### -# romstage -############################################################################### - -ifeq ($(CONFIG_ARCH_ROMSTAGE_MIPS),y) - -romstage-y += boot.c -romstage-y += cache.c -romstage-y += mmu.c -romstage-y += stages.c -romstage-y += ../../lib/memcpy.c -romstage-y += ../../lib/memmove.c -romstage-y += ../../lib/memset.c - -$(objcbfs)/romstage.debug: $$(romstage-objs) - @printf " LINK $(subst $(obj)/,,$(@))\n" - $(LD_romstage) $(LDFLAGS_romstage) -o $@ -L$(obj) -T $(call src-to-obj,romstage,src/mainboard/$(MAINBOARDDIR)/memlayout.ld) --whole-archive --start-group $(filter-out %.ld,$(romstage-objs)) --end-group - -endif # CONFIG_ARCH_ROMSTAGE_MIPS - -############################################################################### -# ramstage -############################################################################### - -ifeq ($(CONFIG_ARCH_RAMSTAGE_MIPS),y) - -ramstage-y += ashldi3.c -ramstage-y += boot.c -ramstage-y += cache.c -ramstage-y += mmu.c -ramstage-y += stages.c -ramstage-y += tables.c -ramstage-y += ../../lib/memcpy.c -ramstage-y += ../../lib/memmove.c -ramstage-y += ../../lib/memset.c - -ramstage-srcs += $(wildcard src/mainboard/$(MAINBOARDDIR)/mainboard.c) - -$(objcbfs)/ramstage.debug: $$(ramstage-objs) - @printf " CC $(subst $(obj)/,,$(@))\n" - $(LD_ramstage) $(LDFLAGS_ramstage) -o $@ -L$(obj) -T $(call src-to-obj,ramstage,src/mainboard/$(MAINBOARDDIR)/memlayout.ld) --whole-archive --start-group $(filter-out %.ld,$(ramstage-objs)) --end-group - -endif # CONFIG_ARCH_RAMSTAGE_MIPS diff --git a/src/arch/mips/ashldi3.c b/src/arch/mips/ashldi3.c deleted file mode 100644 index e3282f55ea..0000000000 --- a/src/arch/mips/ashldi3.c +++ /dev/null @@ -1,53 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Based on linux arch/mips/lib/ashldi3.c - */ - -#ifndef __ORDER_LITTLE_ENDIAN__ -#errror "What endian are you!?" -#endif - -typedef unsigned int word_type; -long long __ashldi3(long long u, word_type b); - -struct DWstruct { - int low, high; -}; -typedef union { - struct DWstruct s; - long long ll; -} DWunion; - -long long __ashldi3(long long u, word_type b) -{ - DWunion uu, w; - word_type bm; - - if (b == 0) - return u; - - uu.ll = u; - bm = 32 - b; - - if (bm <= 0) { - w.s.low = 0; - w.s.high = (unsigned int) uu.s.low << -bm; - } else { - const unsigned int carries = (unsigned int) uu.s.low >> bm; - - w.s.low = (unsigned int) uu.s.low << b; - w.s.high = ((unsigned int) uu.s.high << b) | carries; - } - - return w.ll; -} diff --git a/src/arch/mips/boot.c b/src/arch/mips/boot.c deleted file mode 100644 index a8518cd094..0000000000 --- a/src/arch/mips/boot.c +++ /dev/null @@ -1,23 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include - -void arch_prog_run(struct prog *prog) -{ - void *cb_tables = prog_entry_arg(prog); - void (*doit)(void *) = prog_entry(prog); - - doit(cb_tables); -} diff --git a/src/arch/mips/bootblock.S b/src/arch/mips/bootblock.S deleted file mode 100644 index 8ae1cfd7fa..0000000000 --- a/src/arch/mips/bootblock.S +++ /dev/null @@ -1,42 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -.set noreorder /* Prevent assembler from "optimizing" this code. */ - -.section ".text._start", "ax", %progbits -.globl _start -_start: - /* Set the stack pointer */ - la $sp, _estack - - /* - * Initialise the stack to a known value, used later to check for - * overflow. - */ - la $t0, _stack - addi $t1, $sp, -4 - li $t2, 0xdeadbeef -1: sw $t2, 0($t0) - bne $t0, $t1, 1b - addi $t0, $t0, 4 - - /* Run main */ - b mips_main - - /* - * Should never return from main. Make sure there is no branch in the - * branch delay slot. - */ -2: nop - b 2b - nop /* Make sure there is no branch after this either. */ diff --git a/src/arch/mips/bootblock_simple.c b/src/arch/mips/bootblock_simple.c deleted file mode 100644 index be0b176b90..0000000000 --- a/src/arch/mips/bootblock_simple.c +++ /dev/null @@ -1,42 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include -#include - -/* called from assembly in bootblock.S */ -void mips_main(void); - -void mips_main(void) -{ - bootblock_cpu_init(); - - /* Mainboard basic init */ - bootblock_mainboard_init(); - -#if CONFIG(BOOTBLOCK_CONSOLE) - console_init(); -#endif - - bootblock_mmu_init(); - - if (init_extra_hardware()) - printk(BIOS_ERR, "bootblock_simple: failed to init HW.\n"); - else - run_romstage(); - - halt(); -} diff --git a/src/arch/mips/cache.c b/src/arch/mips/cache.c deleted file mode 100644 index 2b56174898..0000000000 --- a/src/arch/mips/cache.c +++ /dev/null @@ -1,114 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include -#include -#include - -/* cache_op: issues cache operation for specified address */ -#define cache_op(op, addr) \ -({ \ - __asm__ __volatile__( \ - ".set push\n\t" \ - ".set noreorder\n\t" \ - ".set mips32\n\t" \ - "cache %0, %1\n\t" \ - ".set mips0\n\t" \ - ".set pop\n\t" \ - : \ - : "i" (op), "R" (*(unsigned char *)(addr))); \ -}) - -#define MIPS_CONFIG1_DL_SHIFT 10 -#define MIPS_CONFIG1_DL_MASK (0x00000007) -#define MIPS_CONFIG1_IL_SHIFT 19 -#define MIPS_CONFIG1_IL_MASK (0x00000007) -#define MIPS_CONFIG2_SL_SHIFT 4 -#define MIPS_CONFIG2_SL_MASK (0x0000000F) - -/* - * get_cache_line_size: - * Read config register - * Isolate instruction cache line size - * Interpret value as per MIPS manual: 2 << value - * Return cache line size - */ -static int get_cache_line_size(uint8_t type) -{ - switch (type) { - case ICACHE: - return 2 << ((read_c0_config1() >> MIPS_CONFIG1_IL_SHIFT) & - MIPS_CONFIG1_IL_MASK); - case DCACHE: - return 2 << ((read_c0_config1() >> MIPS_CONFIG1_DL_SHIFT) & - MIPS_CONFIG1_DL_MASK); - case L2CACHE: - return 2 << ((read_c0_config2() >> MIPS_CONFIG2_SL_SHIFT) & - MIPS_CONFIG2_SL_MASK); - default: - printk(BIOS_ERR, "%s: Error: unsupported cache type.\n", - __func__); - return 0; - } - return 0; -} - -void perform_cache_operation(uintptr_t start, size_t size, uint8_t operation) -{ - u32 line_size, line_mask; - uintptr_t end; - - line_size = get_cache_line_size((operation >> CACHE_TYPE_SHIFT) & - CACHE_TYPE_MASK); - if (!line_size) - return; - line_mask = ~(line_size-1); - end = (start + (line_size - 1) + size) & line_mask; - start &= line_mask; - if ((operation & L2CACHE) == L2CACHE) - write_c0_l23taglo(0); - while (start < end) { - switch (operation) { - case CACHE_CODE(ICACHE, WB_INVD): - cache_op(CACHE_CODE(ICACHE, WB_INVD), start); - break; - case CACHE_CODE(DCACHE, WB_INVD): - cache_op(CACHE_CODE(DCACHE, WB_INVD), start); - break; - case CACHE_CODE(L2CACHE, WB_INVD): - cache_op(CACHE_CODE(L2CACHE, WB_INVD), start); - break; - default: - return; - } - start += line_size; - } - asm("sync"); -} - -void cache_invalidate_all(uintptr_t start, size_t size) -{ - perform_cache_operation(start, size, CACHE_CODE(ICACHE, WB_INVD)); - perform_cache_operation(start, size, CACHE_CODE(DCACHE, WB_INVD)); - perform_cache_operation(start, size, CACHE_CODE(L2CACHE, WB_INVD)); -} - -void arch_segment_loaded(uintptr_t start, size_t size, int flags) -{ - cache_invalidate_all(start, size); - if (flags & SEG_FINAL) - cache_invalidate_all((uintptr_t)_cbfs_cache, - REGION_SIZE(cbfs_cache)); -} diff --git a/src/arch/mips/include/arch/bootblock_common.h b/src/arch/mips/include/arch/bootblock_common.h deleted file mode 100644 index b930b5c4e7..0000000000 --- a/src/arch/mips/include/arch/bootblock_common.h +++ /dev/null @@ -1,24 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifdef CONFIG_BOOTBLOCK_CPU_INIT -#include CONFIG_BOOTBLOCK_CPU_INIT -#endif - -#ifdef CONFIG_BOOTBLOCK_MAINBOARD_INIT -#include CONFIG_BOOTBLOCK_MAINBOARD_INIT -#else -static void bootblock_mainboard_init(void) -{ -} -#endif diff --git a/src/arch/mips/include/arch/byteorder.h b/src/arch/mips/include/arch/byteorder.h deleted file mode 100644 index 7c0ce47176..0000000000 --- a/src/arch/mips/include/arch/byteorder.h +++ /dev/null @@ -1,23 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef __MIPS_ARCH_BYTEORDER_H -#define __MIPS_ARCH_BYTEORDER_H - -#ifndef __ORDER_LITTLE_ENDIAN__ -#errror "What endian are you!?" -#endif - -#define __LITTLE_ENDIAN 1234 - -#endif /* __MIPS_ARCH_BYTEORDER_H */ diff --git a/src/arch/mips/include/arch/cache.h b/src/arch/mips/include/arch/cache.h deleted file mode 100644 index c610c991cf..0000000000 --- a/src/arch/mips/include/arch/cache.h +++ /dev/null @@ -1,48 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef __MIPS_ARCH_CACHE_H -#define __MIPS_ARCH_CACHE_H - -#include -#include - -#define CACHE_TYPE_SHIFT (0) -#define CACHE_OP_SHIFT (2) -#define CACHE_TYPE_MASK (0x3) -#define CACHE_OP_MASK (0x7) - -/* Cache type */ -#define ICACHE 0x00 -#define DCACHE 0x01 -#define L2CACHE 0x03 - -/* Cache operation*/ -#define WB_INVD 0x05 - -#define CACHE_CODE(type, op) ((((type) & (CACHE_TYPE_MASK)) << \ - (CACHE_TYPE_SHIFT)) | \ - (((op) & (CACHE_OP_MASK)) << (CACHE_OP_SHIFT))) - -/* Perform cache operation on cache lines for target addresses */ -void perform_cache_operation(uintptr_t start, size_t size, uint8_t operation); -/* Invalidate all caches: instruction, data, L2 data */ -void cache_invalidate_all(uintptr_t start, size_t size); - -/* TODO: Global cache API. Implement properly once we finally have a MIPS board - again where we can figure out what exactly these should be doing. */ -static inline void dcache_clean_all(void) {} -static inline void dcache_invalidate_all(void) {} -static inline void dcache_clean_invalidate_all(void) {} - -#endif /* __MIPS_ARCH_CACHE_H */ diff --git a/src/arch/mips/include/arch/cbconfig.h b/src/arch/mips/include/arch/cbconfig.h deleted file mode 100644 index 35c1387895..0000000000 --- a/src/arch/mips/include/arch/cbconfig.h +++ /dev/null @@ -1,26 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef _ARCH_CBCONFIG_H_ -#define _ARCH_CBCONFIG_H_ - -/* - * Instead of using Kconfig variables for internal coreboot infrastructure - * variables that are architecture dependent land those things in this file. - * If it's not obvious all variables that are used in the common code need - * to have the same name across all architectures. - */ - -#define COREBOOT_TABLE_SIZE 0x2000 - -#endif diff --git a/src/arch/mips/include/arch/cpu.h b/src/arch/mips/include/arch/cpu.h deleted file mode 100644 index 61eb0828cf..0000000000 --- a/src/arch/mips/include/arch/cpu.h +++ /dev/null @@ -1,172 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef __MIPS_ARCH_CPU_H -#define __MIPS_ARCH_CPU_H - -#include - -#define asmlinkage - -struct cpu_driver { - struct device_operations *ops; - const struct cpu_device_id *id_table; -}; - -struct thread; - -struct cpu_info { - struct device *cpu; - unsigned long index; -}; - - -/*************************************************************************** - * The following section was copied from arch/mips/include/asm/mipsregs.h in - * the 3.14 kernel tree. - */ - -/* - * Macros to access the system control coprocessor - */ - -#define __read_32bit_c0_register(source, sel) \ -({ int __res; \ - if (sel == 0) \ - __asm__ __volatile__( \ - "mfc0\t%0, " #source "\n\t" \ - : "=r" (__res)); \ - else \ - __asm__ __volatile__( \ - ".set\tmips32\n\t" \ - "mfc0\t%0, " #source ", " #sel "\n\t" \ - ".set\tmips0\n\t" \ - : "=r" (__res)); \ - __res; \ -}) - -#define __write_32bit_c0_register(register, sel, value) \ -do { \ - if (sel == 0) \ - __asm__ __volatile__( \ - "mtc0\t%z0, " #register "\n\t" \ - : : "Jr" ((unsigned int)(value))); \ - else \ - __asm__ __volatile__( \ - ".set\tmips32\n\t" \ - "mtc0\t%z0, " #register ", " #sel "\n\t" \ - ".set\tmips0" \ - : : "Jr" ((unsigned int)(value))); \ -} while (0) - -/* Shortcuts to access various internal registers, keep adding as needed. */ -#define read_c0_index() __read_32bit_c0_register($0, 0) -#define write_c0_index(val) __write_32bit_c0_register($0, 0, (val)) - -#define read_c0_entrylo0() __read_32bit_c0_register($2, 0) -#define write_c0_entrylo0(val) __write_32bit_c0_register($2, 0, (val)) - -#define read_c0_entrylo1() __read_32bit_c0_register($3, 0) -#define write_c0_entrylo1(val) __write_32bit_c0_register($3, 0, (val)) - -#define read_c0_pagemask() __read_32bit_c0_register($5, 0) -#define write_c0_pagemask(val) __write_32bit_c0_register($5, 0, (val)) - -#define read_c0_wired() __read_32bit_c0_register($6, 0) -#define write_c0_wired(val) __write_32bit_c0_register($6, 0, (val)) - -#define read_c0_count() __read_32bit_c0_register($9, 0) -#define write_c0_count(val) __write_32bit_c0_register($9, 0, (val)) - -#define read_c0_entryhi() __read_32bit_c0_register($10, 0) -#define write_c0_entryhi(val) __write_32bit_c0_register($10, 0, (val)) - -#define read_c0_cause() __read_32bit_c0_register($13, 0) -#define write_c0_cause(val) __write_32bit_c0_register($13, 0, (val)) - -#define read_c0_config1() __read_32bit_c0_register($16, 1) -#define write_c0_config1(val) __write_32bit_c0_register($16, 1, (val)) - -#define read_c0_config2() __read_32bit_c0_register($16, 2) -#define write_c0_config2(val) __write_32bit_c0_register($16, 2, (val)) - -#define read_c0_l23taglo() __read_32bit_c0_register($28, 4) -#define write_c0_l23taglo(val) __write_32bit_c0_register($28, 4, (val)) - - -#define C0_ENTRYLO_PFN_SHIFT 6 - -#define C0_ENTRYLO_COHERENCY_MASK 0x00000038 -#define C0_ENTRYLO_COHERENCY_SHIFT 3 -/* Cacheable, write-back, non-coherent */ -#define C0_ENTRYLO_COHERENCY_WB (0x3 << C0_ENTRYLO_COHERENCY_SHIFT) -/* Uncached, non-coherent */ -#define C0_ENTRYLO_COHERENCY_UC (0x2 << C0_ENTRYLO_COHERENCY_SHIFT) - -/* Writeable */ -#define C0_ENTRYLO_D (0x1 << 2) -/* Valid */ -#define C0_ENTRYLO_V (0x1 << 1) -/* Global */ -#define C0_ENTRYLO_G (0x1 << 0) - -#define C0_PAGEMASK_SHIFT 13 -#define C0_PAGEMASK_MASK 0xffff - -#define C0_WIRED_MASK 0x3f - -#define C0_CAUSE_DC (1 << 27) - -#define C0_CONFIG1_MMUSIZE_SHIFT 25 -#define C0_CONFIG1_MMUSIZE_MASK 0x3f - -/* Hazard handling */ -static inline void __nop(void) -{ - __asm__ __volatile__("nop"); -} - -static inline void __ssnop(void) -{ - __asm__ __volatile__("sll\t$0, $0, 1"); -} - -#define mtc0_tlbw_hazard() \ -do { \ - __nop(); \ - __nop(); \ -} while (0) - -#define tlbw_use_hazard() \ -do { \ - __nop(); \ - __nop(); \ - __nop(); \ -} while (0) - -#define tlb_probe_hazard() \ -do { \ - __nop(); \ - __nop(); \ - __nop(); \ -} while (0) - -#define back_to_back_c0_hazard() \ -do { \ - __ssnop(); \ - __ssnop(); \ - __ssnop(); \ -} while (0) -/**************************************************************************/ - -#endif /* __MIPS_ARCH_CPU_H */ diff --git a/src/arch/mips/include/arch/early_variables.h b/src/arch/mips/include/arch/early_variables.h deleted file mode 100644 index 6ad82606c4..0000000000 --- a/src/arch/mips/include/arch/early_variables.h +++ /dev/null @@ -1,27 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef __MIPS_ARCH_EARLY_VARIABLES_H -#define __MIPS_ARCH_EARLY_VARIABLES_H - -#define CAR_GLOBAL -#define CAR_MIGRATE(migrate_fn_) - -static inline void *car_get_var_ptr(void *var) { return var; } -#define car_get_var(var) (var) -#define car_set_var(var, val) { (var) = (val); } - -#define car_get_ptr car_get_var -#define car_set_ptr car_set_var - -#endif /* __MIPS_ARCH_EARLY_VARIABLES_H */ diff --git a/src/arch/mips/include/arch/exception.h b/src/arch/mips/include/arch/exception.h deleted file mode 100644 index a0ab9ecebd..0000000000 --- a/src/arch/mips/include/arch/exception.h +++ /dev/null @@ -1,19 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef __MIPS_ARCH_EXCEPTION_H -#define __MIPS_ARCH_EXCEPTION_H - -static inline void exception_init(void) {} - -#endif /* __MIPS_ARCH_EXCEPTION_H */ diff --git a/src/arch/mips/include/arch/header.ld b/src/arch/mips/include/arch/header.ld deleted file mode 100644 index 7f832eb51c..0000000000 --- a/src/arch/mips/include/arch/header.ld +++ /dev/null @@ -1,26 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -/* We use ELF as output format. So that we can debug the code in some form. */ -OUTPUT_ARCH(mips) - -PHDRS -{ - to_load PT_LOAD; -} - -#if ENV_BOOTBLOCK -ENTRY(_start) -#else -ENTRY(stage_entry) -#endif diff --git a/src/arch/mips/include/arch/hlt.h b/src/arch/mips/include/arch/hlt.h deleted file mode 100644 index 5feafe2b85..0000000000 --- a/src/arch/mips/include/arch/hlt.h +++ /dev/null @@ -1,23 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef __MIPS_ARCH_HLT_H -#define __MIPS_ARCH_HLT_H - -static inline __always_inline void hlt(void) -{ - for (;;) - ; -} - -#endif /* __MIPS_ARCH_HLT_H */ diff --git a/src/arch/mips/include/arch/memlayout.h b/src/arch/mips/include/arch/memlayout.h deleted file mode 100644 index bf862a30ea..0000000000 --- a/src/arch/mips/include/arch/memlayout.h +++ /dev/null @@ -1,29 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -/* This file contains macro definitions for memlayout.ld linker scripts. */ - -#ifndef __ARCH_MEMLAYOUT_H -#define __ARCH_MEMLAYOUT_H - -/* MIPS stacks need 8-byte alignment and stay in one place through ramstage. */ -/* TODO: Double-check that that's the correct alignment for our ABI. */ -#define STACK(addr, size) \ - REGION(stack, addr, size, 8) \ - _ = ASSERT(size >= 2K, "stack should be >= 2K, see toolchain.inc"); - -#define DMA_COHERENT(addr, size) REGION(dma_coherent, addr, size, 4K) - -#define SOC_REGISTERS(addr, size) REGION(soc_registers, addr, size, 4) - -#endif /* __ARCH_MEMLAYOUT_H */ diff --git a/src/arch/mips/include/arch/mmio.h b/src/arch/mips/include/arch/mmio.h deleted file mode 100644 index 2564e3b60d..0000000000 --- a/src/arch/mips/include/arch/mmio.h +++ /dev/null @@ -1,64 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef __ARCH_MMIO_H__ -#define __ARCH_MMIO_H__ - -#include -#include -#include - -static inline uint8_t read8(const volatile void *addr) -{ - asm("sync"); - return *(volatile uint8_t *)addr; -} - -static inline uint16_t read16(const volatile void *addr) -{ - asm("sync"); - return *(volatile uint16_t *)addr; -} - -static inline uint32_t read32(const volatile void *addr) -{ - asm("sync"); - return *(volatile uint32_t *)addr; -} - -static inline void write8(volatile void *addr, uint8_t val) -{ - asm("sync"); - *(volatile uint8_t *)addr = val; - asm("sync"); -} - -static inline void write16(volatile void *addr, uint16_t val) -{ - asm("sync"); - *(volatile uint16_t *)addr = val; - asm("sync"); -} - -static inline void write32(volatile void *addr, uint32_t val) -{ - asm("sync"); - *(volatile uint32_t *)addr = val; - asm("sync"); -} - -/* Fixing soc/imgtech/pistachio seemed painful at the time. */ -#define read32_x(addr) read32((void *)(addr)) -#define write32_x(addr, val) write32((void *)(addr), (val)) - -#endif /* __MIPS_ARCH_IO_H */ diff --git a/src/arch/mips/include/arch/mmu.h b/src/arch/mips/include/arch/mmu.h deleted file mode 100644 index f7377bb88c..0000000000 --- a/src/arch/mips/include/arch/mmu.h +++ /dev/null @@ -1,53 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef __MIPS_ARCH_MMU_H -#define __MIPS_ARCH_MMU_H - -#include -#include -#include - -static inline void tlb_write_indexed(void) -{ - __asm__ __volatile__( - ".set noreorder\n\t" - "tlbwi\n\t" - ".set reorder"); -} - -static inline uint32_t get_max_pagesize(void) -{ - uint32_t max_pgsize; - - write_c0_pagemask(C0_PAGEMASK_MASK << C0_PAGEMASK_SHIFT); - back_to_back_c0_hazard(); - max_pgsize = (((read_c0_pagemask() >> C0_PAGEMASK_SHIFT) & - C0_PAGEMASK_MASK) + 1) * 4 * KiB; - - return max_pgsize; -} - -static inline uint32_t get_tlb_size(void) -{ - uint32_t tlbsize; - - tlbsize = ((read_c0_config1() >> C0_CONFIG1_MMUSIZE_SHIFT) & - C0_CONFIG1_MMUSIZE_MASK) + 1; - - return tlbsize; -} - -int identity_map(uint32_t start, size_t len, uint32_t coherency); - -#endif /* __MIPS_ARCH_MMU_H */ diff --git a/src/arch/mips/include/arch/pci_ops.h b/src/arch/mips/include/arch/pci_ops.h deleted file mode 100644 index da397cf3b8..0000000000 --- a/src/arch/mips/include/arch/pci_ops.h +++ /dev/null @@ -1,19 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef ARCH_MIPS_PCI_OPS_H -#define ARCH_MIPS_PCI_OPS_H - -#include - -#endif diff --git a/src/arch/mips/include/arch/stages.h b/src/arch/mips/include/arch/stages.h deleted file mode 100644 index 3da02da1ca..0000000000 --- a/src/arch/mips/include/arch/stages.h +++ /dev/null @@ -1,22 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef __MIPS_ARCH_STAGES_H -#define __MIPS_ARCH_STAGES_H - -#include -#include - -void stage_entry(uintptr_t stage_arg); - -#endif /* __MIPS_ARCH_STAGES_H */ diff --git a/src/arch/mips/include/arch/types.h b/src/arch/mips/include/arch/types.h deleted file mode 100644 index fa14b6a684..0000000000 --- a/src/arch/mips/include/arch/types.h +++ /dev/null @@ -1,59 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef __MIPS_ARCH_TYPES_H -#define __MIPS_ARCH_TYPES_H - -typedef unsigned short umode_t; - -/* - * __xx is ok: it doesn't pollute the POSIX namespace. Use these in the - * header files exported to user space - */ - -typedef __signed__ char __s8; -typedef unsigned char __u8; - -typedef __signed__ short __s16; -typedef unsigned short __u16; - -typedef __signed__ int __s32; -typedef unsigned int __u32; - -#if defined(__GNUC__) -__extension__ typedef __signed__ long long __s64; -__extension__ typedef unsigned long long __u64; -#endif - -typedef signed char s8; -typedef unsigned char u8; - -typedef signed short s16; -typedef unsigned short u16; - -typedef signed int s32; -typedef unsigned int u32; - -typedef signed long long s64; -typedef unsigned long long u64; - -#define BITS_PER_LONG 32 - -/* Dma addresses are 32-bits wide. */ - -typedef u32 dma_addr_t; - -typedef unsigned long phys_addr_t; -typedef unsigned long phys_size_t; - -#endif /* __MIPS_ARCH_TYPES_H */ diff --git a/src/arch/mips/mmu.c b/src/arch/mips/mmu.c deleted file mode 100644 index 5ef276d273..0000000000 --- a/src/arch/mips/mmu.c +++ /dev/null @@ -1,98 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include -#include -#include - -#define MIN_PAGE_SIZE (4 * KiB) - -static int add_wired_tlb_entry(uint32_t entrylo0, uint32_t entrylo1, - uint32_t entryhi, uint32_t pgsize) -{ - uint32_t tlbindex; - - tlbindex = read_c0_wired(); - if (tlbindex >= get_tlb_size() || tlbindex >= C0_WIRED_MASK) { - printk(BIOS_ERR, "Ran out of TLB entries\n"); - return -1; - } - write_c0_wired(tlbindex + 1); - write_c0_index(tlbindex); - write_c0_pagemask(((pgsize / MIN_PAGE_SIZE) - 1) << C0_PAGEMASK_SHIFT); - write_c0_entryhi(entryhi); - write_c0_entrylo0(entrylo0); - write_c0_entrylo1(entrylo1); - mtc0_tlbw_hazard(); - tlb_write_indexed(); - tlbw_use_hazard(); - - return 0; -} - -static uint32_t pick_pagesize(uint32_t start, uint32_t len) -{ - uint32_t pgsize, max_pgsize; - - max_pgsize = get_max_pagesize(); - for (pgsize = max_pgsize; - pgsize >= MIN_PAGE_SIZE; - pgsize = pgsize / 4) { - /* - * Each TLB entry maps a pair of virtual pages. To avoid - * aliasing, pick the largest page size that is at most - * half the size of the region we're trying to map. - */ - if (IS_ALIGNED(start, 2 * pgsize) && (2 * pgsize <= len)) - break; - } - - return pgsize; -} - -/* - * Identity map the memory from [start,start+len] in the TLB using the - * largest suitable page size so as to conserve TLB entries. - */ -int identity_map(uint32_t start, size_t len, uint32_t coherency) -{ - uint32_t pgsize, pfn, entryhi, entrylo0, entrylo1; - - coherency &= C0_ENTRYLO_COHERENCY_MASK; - while (len > 0) { - pgsize = pick_pagesize(start, len); - entryhi = start; - pfn = start >> 12; - entrylo0 = (pfn << C0_ENTRYLO_PFN_SHIFT) | coherency | - C0_ENTRYLO_D | C0_ENTRYLO_V | C0_ENTRYLO_G; - start += pgsize; - len -= MIN(len, pgsize); - if (len >= pgsize) { - pfn = start >> 12; - entrylo1 = (pfn << C0_ENTRYLO_PFN_SHIFT) | - coherency | C0_ENTRYLO_D | C0_ENTRYLO_V | - C0_ENTRYLO_G; - start += pgsize; - len -= MIN(len, pgsize); - } else { - entrylo1 = 0; - } - if (add_wired_tlb_entry(entrylo0, entrylo1, entryhi, pgsize)) - return -1; - } - - return 0; -} diff --git a/src/arch/mips/stages.c b/src/arch/mips/stages.c deleted file mode 100644 index bf31153d98..0000000000 --- a/src/arch/mips/stages.c +++ /dev/null @@ -1,23 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include - -void stage_entry(uintptr_t stage_arg) -{ - if (!ENV_ROMSTAGE_OR_BEFORE) - _cbmem_top_ptr = stage_arg; - main(); -} diff --git a/src/arch/mips/tables.c b/src/arch/mips/tables.c deleted file mode 100644 index e9de4bfd71..0000000000 --- a/src/arch/mips/tables.c +++ /dev/null @@ -1,28 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include - -void arch_write_tables(uintptr_t coreboot_table) -{ -} - -void bootmem_arch_add_ranges(void) -{ -} - -void lb_arch_add_records(struct lb_header *header) -{ -} diff --git a/src/console/vtxprintf.c b/src/console/vtxprintf.c index 1efe55a332..b9e43692d8 100644 --- a/src/console/vtxprintf.c +++ b/src/console/vtxprintf.c @@ -20,10 +20,6 @@ #define call_tx(x) tx_byte(x, data) -#if !CONFIG(ARCH_MIPS) -#define SUPPORT_64BIT_INTS -#endif - #define ZEROPAD 1 /* pad with zero */ #define SIGN 2 /* unsigned/signed long */ #define PLUS 4 /* show plus */ diff --git a/src/cpu/Makefile.inc b/src/cpu/Makefile.inc index 66ee2f9169..bf857f8ffe 100644 --- a/src/cpu/Makefile.inc +++ b/src/cpu/Makefile.inc @@ -4,7 +4,6 @@ subdirs-y += allwinner subdirs-y += amd subdirs-y += armltd -subdirs-y += imgtec subdirs-y += intel subdirs-y += ti subdirs-y += via diff --git a/src/drivers/spi/cbfs_spi.c b/src/drivers/spi/cbfs_spi.c index fca61004ff..c68b9061f8 100644 --- a/src/drivers/spi/cbfs_spi.c +++ b/src/drivers/spi/cbfs_spi.c @@ -53,7 +53,7 @@ static ssize_t spi_readat(const struct region_device *rd, void *b, u64 speed; /* KiB/s */ int bps; /* Bits per second */ - speed = size * 1000 / usecs; + speed = size * (u64)1000 / usecs; bps = speed * 8; printk(BIOS_DEBUG, "read SPI %#zx %#zx: %ld us, %lld KB/s, %d.%03d Mbps\n", diff --git a/src/include/rules.h b/src/include/rules.h index 0436198363..9e13ee65a6 100644 --- a/src/include/rules.h +++ b/src/include/rules.h @@ -173,7 +173,6 @@ #define ENV_ARMV7 0 #endif #define ENV_ARMV8 0 -#define ENV_MIPS 0 #define ENV_RISCV 0 #define ENV_X86 0 #define ENV_X86_32 0 @@ -189,19 +188,6 @@ #else #define ENV_ARMV8 0 #endif -#define ENV_MIPS 0 -#define ENV_RISCV 0 -#define ENV_X86 0 -#define ENV_X86_32 0 -#define ENV_X86_64 0 - -#elif defined(__ARCH_mips__) -#define ENV_ARM 0 -#define ENV_ARM64 0 -#define ENV_ARMV4 0 -#define ENV_ARMV7 0 -#define ENV_ARMV8 0 -#define ENV_MIPS 1 #define ENV_RISCV 0 #define ENV_X86 0 #define ENV_X86_32 0 @@ -213,7 +199,6 @@ #define ENV_ARMV4 0 #define ENV_ARMV7 0 #define ENV_ARMV8 0 -#define ENV_MIPS 0 #define ENV_RISCV 1 #define ENV_X86 0 #define ENV_X86_32 0 @@ -225,7 +210,6 @@ #define ENV_ARMV4 0 #define ENV_ARMV7 0 #define ENV_ARMV8 0 -#define ENV_MIPS 0 #define ENV_RISCV 0 #define ENV_X86 1 #define ENV_X86_32 1 @@ -237,7 +221,6 @@ #define ENV_ARMV4 0 #define ENV_ARMV7 0 #define ENV_ARMV8 0 -#define ENV_MIPS 0 #define ENV_RISCV 0 #define ENV_X86 1 #define ENV_X86_32 0 @@ -249,7 +232,6 @@ #define ENV_ARMV4 0 #define ENV_ARMV7 0 #define ENV_ARMV8 0 -#define ENV_MIPS 0 #define ENV_RISCV 0 #define ENV_X86 0 #define ENV_X86_32 0 diff --git a/src/vendorcode/google/chromeos/Makefile.inc b/src/vendorcode/google/chromeos/Makefile.inc index 05acdeec9a..b509af7483 100644 --- a/src/vendorcode/google/chromeos/Makefile.inc +++ b/src/vendorcode/google/chromeos/Makefile.inc @@ -23,8 +23,7 @@ ramstage-$(CONFIG_HAVE_REGULATORY_DOMAIN) += wrdd.c ramstage-$(CONFIG_USE_SAR) += sar.c ramstage-$(CONFIG_CHROMEOS_DSM_CALIB) += dsm_calib.c ramstage-$(CONFIG_TPM_CR50) += cr50_enable_update.c -ifeq ($(CONFIG_ARCH_MIPS),) + bootblock-y += watchdog.c verstage-y += watchdog.c ramstage-y += watchdog.c -endif diff --git a/toolchain.inc b/toolchain.inc index 4c0408ccfd..af085b4cad 100644 --- a/toolchain.inc +++ b/toolchain.inc @@ -56,12 +56,10 @@ ARCHDIR-x86_64 := x86 ARCHDIR-arm := arm ARCHDIR-arm64 := arm64 ARCHDIR-riscv := riscv -ARCHDIR-mips := mips ARCHDIR-ppc64 := ppc64 CFLAGS_arm += CFLAGS_arm64 += -mgeneral-regs-only -CFLAGS_mips += -mips32r2 -G 0 -mno-abicalls -fno-pic CFLAGS_riscv += CFLAGS_x86_32 += CFLAGS_x86_64 += -mcmodel=large -mno-red-zone @@ -83,7 +81,6 @@ CFLAGS_ppc64 += ifeq ($(CONFIG_COMPILER_GCC),y) CFLAGS_arm += -Wstack-usage=1536 CFLAGS_arm64 += -Wstack-usage=1536 -CFLAGS_mips += -Wstack-usage=1536 CFLAGS_riscv += -Wstack-usage=1536 CFLAGS_ppc64 += -Wstack-usage=1536 endif diff --git a/util/README.md b/util/README.md index 470013ed25..55bcaab637 100644 --- a/util/README.md +++ b/util/README.md @@ -9,9 +9,6 @@ settings. `Perl` platform. `C` * __autoport__ - Automated porting coreboot to Sandy Bridge/Ivy Bridge platforms `Go` -* __bimgtool__ - A simple tool which generates and verifies boot images -in the BIMG format, used in systems designed by Imagination -Technologies, for example the Pistachio SoC. `C` * __bincfg__ - Compiler/Decompiler for data blobs with specs `Lex` `Yacc` * __board_status__ - Tools to collect logs and upload them to the board diff --git a/util/cbfstool/cbfs.h b/util/cbfstool/cbfs.h index 4bc95ab4da..f0c215d0d7 100644 --- a/util/cbfstool/cbfs.h +++ b/util/cbfstool/cbfs.h @@ -65,7 +65,7 @@ struct cbfs_header { #define CBFS_ARCHITECTURE_X86 0x00000001 #define CBFS_ARCHITECTURE_ARM 0x00000010 #define CBFS_ARCHITECTURE_AARCH64 0x0000aa64 -#define CBFS_ARCHITECTURE_MIPS 0x00000100 +#define CBFS_ARCHITECTURE_MIPS 0x00000100 /* deprecated */ #define CBFS_ARCHITECTURE_RISCV 0xc001d0de #define CBFS_ARCHITECTURE_PPC64 0x407570ff diff --git a/util/crossgcc/Makefile b/util/crossgcc/Makefile index c4f4262e87..db8b769287 100644 --- a/util/crossgcc/Makefile +++ b/util/crossgcc/Makefile @@ -8,12 +8,12 @@ DEST ?= $(CURDIR)/xgcc # Example: BUILDGCC_OPTIONS=-c to remove temporary files before build all all_with_gdb: - $(MAKE) build-i386 build-x64 build-arm build-mips \ + $(MAKE) build-i386 build-x64 build-arm \ build-riscv build-aarch64 build-ppc64 build-nds32le \ build_clang build_iasl build_make build_nasm all_without_gdb: - $(MAKE) SKIP_GDB=1 build-i386 build-x64 build-arm build-mips \ + $(MAKE) SKIP_GDB=1 build-i386 build-x64 build-arm \ build-riscv build-aarch64 build-ppc64 build-nds32le \ build_clang build_iasl build_make build_nasm @@ -59,9 +59,6 @@ build-arm: build-aarch64: @$(MAKE) build_tools BUILD_PLATFORM=aarch64-elf -build-mips: - @$(MAKE) build_tools BUILD_PLATFORM=mipsel-elf - build-riscv: # GDB is currently not supported on RISC-V @$(MAKE) build_gcc BUILD_PLATFORM=riscv-elf @@ -88,7 +85,6 @@ distclean: clean .PHONY: build_gcc build_iasl build_gdb build_clang all all_with_gdb \ all_without_gdb build_tools build-i386 build-x64 build-arm \ - build-aarch64 build-mips build-riscv build-ppc64 build-nds32le \ - build-nasm \ + build-aarch64 build-riscv build-ppc64 build-nds32le build-nasm \ clean distclean clean_tempfiles .NOTPARALLEL: diff --git a/util/crossgcc/Makefile.inc b/util/crossgcc/Makefile.inc index 0ef6b9c1e3..108612fd0a 100644 --- a/util/crossgcc/Makefile.inc +++ b/util/crossgcc/Makefile.inc @@ -13,7 +13,7 @@ ## GNU General Public License for more details. ## -TOOLCHAIN_ARCHES := i386 x64 arm aarch64 mips riscv ppc64 nds32le +TOOLCHAIN_ARCHES := i386 x64 arm aarch64 riscv ppc64 nds32le help_toolchain help:: @echo '*** Toolchain targets ***' @@ -39,9 +39,9 @@ crossgcc: clean-for-update $(MAKE) -C util/crossgcc all_without_gdb SKIP_CLANG=1 .PHONY: crossgcc crossgcc-i386 crossgcc-x64 crossgcc-arm crossgcc-aarch64 \ - crossgcc-mips crossgcc-riscv crossgcc-power8 crossgcc-clean iasl \ + crossgcc-riscv crossgcc-power8 crossgcc-clean iasl \ clang crosstools-i386 crosstools-x64 crosstools-arm \ - crosstools-aarch64 crosstools-mips crosstools-riscv crosstools-power8 \ + crosstools-aarch64 crosstools-riscv crosstools-power8 \ jenkins-build-toolchain gnumake nasm $(foreach arch,$(TOOLCHAIN_ARCHES),crossgcc-$(arch)): clean-for-update diff --git a/util/crossgcc/README b/util/crossgcc/README index 5ce9304aa7..c40454f3d9 100644 --- a/util/crossgcc/README +++ b/util/crossgcc/README @@ -7,7 +7,6 @@ known working: i386-elf x86_64-elf powerpc-elf - mipsel-elf arm-elf armv7a-eabi aarch64-elf diff --git a/util/crossgcc/buildgcc b/util/crossgcc/buildgcc index b75b90a877..0ce8f20851 100755 --- a/util/crossgcc/buildgcc +++ b/util/crossgcc/buildgcc @@ -604,7 +604,7 @@ myhelp() printf " (defaults to $TARGETARCH)\n" printf " [-S|--scripting] build scripting support for GDB\n\n" printf "Platforms for GCC & GDB:\n" - printf " x86_64 i386-elf i386-mingw32 mipsel-elf riscv-elf arm aarch64\n" + printf " x86_64 i386-elf i386-mingw32 riscv-elf arm aarch64\n" printf " powerpc64le-linux-gnu nds32le-elf\n\n" } @@ -1018,7 +1018,6 @@ case "$TARGETARCH" in x86_64*) TARGETARCH=x86_64-elf;; i386-elf) ;; i386-mingw32) ;; - mipsel-elf) ;; riscv-elf) TARGETARCH=riscv64-elf;; powerpc64*-linux*) ;; i386*) TARGETARCH=i386-elf;; diff --git a/util/docker/coreboot.org-status/board-status.html/tohtml.sh b/util/docker/coreboot.org-status/board-status.html/tohtml.sh index 41de9ff238..8522fd579b 100755 --- a/util/docker/coreboot.org-status/board-status.html/tohtml.sh +++ b/util/docker/coreboot.org-status/board-status.html/tohtml.sh @@ -334,9 +334,6 @@ EOF TI_AM335X) cpu_nice="TI AM335X"; socket_nice="?";; - IMGTEC_PISTACHIO) - cpu_nice="Imagination Technologies Pistachio"; - socket_nice="—";; INTEL_APOLLOLAKE) cpu_nice="Intel® Apollo Lake"; socket_nice="—";; diff --git a/util/release/genrelnotes b/util/release/genrelnotes index 2867cbffee..25c2993658 100755 --- a/util/release/genrelnotes +++ b/util/release/genrelnotes @@ -353,11 +353,6 @@ get_log_dedupe "ARM" \ get_log_dedupe "RISC-V" \ "$(for codedir in $(grep -rl "_RISCV" --include=Kconfig | grep -v 'payloads/\|drivers/\|vendorcode/\|console' ); do dirname "$codedir"; done | grep -v '^src$')" \ "riscv\|risc-v\|sifive" - -get_log_dedupe "MIPS" \ - "$(for codedir in $(grep -rl "_MIPS" --include=Kconfig | \ - grep -v 'src/mainboard\|payloads/\|drivers/\|vendorcode/\|console' ); \ - do dirname "$codedir"; done | grep -v '^src$')" } get_log_dedupe "X86 intel" \ diff --git a/util/xcompile/xcompile b/util/xcompile/xcompile index 2d3da1e00e..f3400fef49 100755 --- a/util/xcompile/xcompile +++ b/util/xcompile/xcompile @@ -195,14 +195,6 @@ detect_special_flags() { "$LDFLAGS --fix-cortex-a53-843419" && \ LDFLAGS_ARM64_A53_ERRATUM_843419+=" --fix-cortex-a53-843419" ;; - mipsel) - testcc "$GCC" "$CFLAGS_GCC -mno-abicalls -fno-pic" && \ - CFLAGS_GCC+=" -mno-abicalls -fno-pic" - - # Enforce little endian mode. - testcc "$GCC" "$CFLAGS_GCC -EL" && \ - CFLAGS_GCC+=" -EL" - ;; esac } @@ -314,7 +306,7 @@ EOF } # Architecture definitions -SUPPORTED_ARCHITECTURES="arm arm64 mipsel riscv x64 x86 ppc64" +SUPPORTED_ARCHITECTURES="arm arm64 riscv x64 x86 ppc64" # TARCH: local name for the architecture # (used as CC_${TARCH} in the build system) @@ -367,16 +359,6 @@ arch_config_x86() { CC_RT_EXTRA_GCC="--wrap __divdi3 --wrap __udivdi3 --wrap __moddi3 --wrap __umoddi3" } -arch_config_mipsel() { - TARCH="mips" - TBFDARCHS="tradlittlemips littlemips" - TCLIST="mipsel" - TWIDTH="32" - TSUPP="mips mipsel" - TABI="elf" - TENDIAN="EL" -} - arch_config_ppc64() { TARCH="ppc64" TBFDARCHS="powerpc" From 26d2dad98058b68cc888b1df5c87d943f4a64cef Mon Sep 17 00:00:00 2001 From: Patrick Georgi Date: Tue, 19 Nov 2019 17:36:11 +0100 Subject: [PATCH 0262/1242] Documentation/releases: 4.11 isn't "upcoming" anymore. Change-Id: I7102519b171c3e5269fefaa66d12d605f5d9ddb5 Signed-off-by: Patrick Georgi Reviewed-on: https://review.coreboot.org/c/coreboot/+/36974 Reviewed-by: HAOUAS Elyes Tested-by: build bot (Jenkins) --- Documentation/releases/coreboot-4.11-relnotes.md | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/Documentation/releases/coreboot-4.11-relnotes.md b/Documentation/releases/coreboot-4.11-relnotes.md index 2d0b5cf5b5..890c2d7c36 100644 --- a/Documentation/releases/coreboot-4.11-relnotes.md +++ b/Documentation/releases/coreboot-4.11-relnotes.md @@ -1,5 +1,5 @@ -Upcoming release - coreboot 4.11 -================================ +coreboot 4.11 +============= coreboot 4.11 was released on November 19th. From 4f1d6ff42eed54214587ffc621d2d4d10b06a1fc Mon Sep 17 00:00:00 2001 From: Patrick Georgi Date: Tue, 19 Nov 2019 17:54:32 +0100 Subject: [PATCH 0263/1242] Documentation/releases: Releasing includes announcing on the list Change-Id: I063997d51a80b1b244a0cb35ae90446610ef2c21 Signed-off-by: Patrick Georgi Reviewed-on: https://review.coreboot.org/c/coreboot/+/36975 Reviewed-by: Jacob Garber Tested-by: build bot (Jenkins) --- Documentation/releases/checklist.md | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/releases/checklist.md b/Documentation/releases/checklist.md index ad00ce8de7..f25f336c00 100644 --- a/Documentation/releases/checklist.md +++ b/Documentation/releases/checklist.md @@ -72,6 +72,7 @@ be more frequent than was needed, so we scaled it back to twice a year. - [ ] Update download page to point to files, push to repo - [ ] Write and publish blog post with release notes. - [ ] Update the topic in the irc channel that the release is done. +- [ ] Announce the release to the mailing list ## Pre-Release tasks Announce the upcoming release to the mailing list release 2 weeks ahead From dc0b1875a9196e593d9f25c4edbfd3b37c93e727 Mon Sep 17 00:00:00 2001 From: Joe Moore Date: Sun, 20 Oct 2019 11:08:13 -0600 Subject: [PATCH 0264/1242] mainboard/amd: Remove AMD Torpedo mainboard This also permits removal of vc/amd/agesa/f12, as it was the only mainboard using it. That will in turn allow resolving some unique Coverity issues reported against that source. Change-Id: I73f570f01fcb5ba0e306508a569ea97f432596b3 Signed-off-by: Joe Moore Reviewed-on: https://review.coreboot.org/c/coreboot/+/36173 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth --- src/mainboard/amd/torpedo/BiosCallOuts.c | 187 -- src/mainboard/amd/torpedo/Kconfig | 137 -- src/mainboard/amd/torpedo/Kconfig.name | 2 - src/mainboard/amd/torpedo/Makefile.inc | 37 - src/mainboard/amd/torpedo/Oem.h | 217 -- src/mainboard/amd/torpedo/OemCustomize.c | 131 -- src/mainboard/amd/torpedo/OptionsIds.h | 56 - src/mainboard/amd/torpedo/acpi/ide.asl | 240 -- src/mainboard/amd/torpedo/acpi/routing.asl | 308 --- src/mainboard/amd/torpedo/acpi/sata.asl | 145 -- src/mainboard/amd/torpedo/acpi/usb.asl | 0 src/mainboard/amd/torpedo/acpi_tables.c | 52 - src/mainboard/amd/torpedo/board_info.txt | 1 - src/mainboard/amd/torpedo/buildOpts.c | 221 -- src/mainboard/amd/torpedo/cmos.layout | 68 - src/mainboard/amd/torpedo/devicetree.cb | 85 - src/mainboard/amd/torpedo/dsdt.asl | 1109 ---------- src/mainboard/amd/torpedo/fadt.c | 213 -- src/mainboard/amd/torpedo/gpio.c | 441 ---- src/mainboard/amd/torpedo/gpio.h | 2296 -------------------- src/mainboard/amd/torpedo/irq_tables.c | 103 - src/mainboard/amd/torpedo/mainboard.c | 33 - src/mainboard/amd/torpedo/mptable.c | 232 -- src/mainboard/amd/torpedo/platform_cfg.h | 1220 ----------- src/mainboard/amd/torpedo/pmio.h | 30 - src/mainboard/amd/torpedo/romstage.c | 25 - 26 files changed, 7589 deletions(-) delete mode 100644 src/mainboard/amd/torpedo/BiosCallOuts.c delete mode 100644 src/mainboard/amd/torpedo/Kconfig delete mode 100644 src/mainboard/amd/torpedo/Kconfig.name delete mode 100644 src/mainboard/amd/torpedo/Makefile.inc delete mode 100644 src/mainboard/amd/torpedo/Oem.h delete mode 100644 src/mainboard/amd/torpedo/OemCustomize.c delete mode 100644 src/mainboard/amd/torpedo/OptionsIds.h delete mode 100644 src/mainboard/amd/torpedo/acpi/ide.asl delete mode 100644 src/mainboard/amd/torpedo/acpi/routing.asl delete mode 100644 src/mainboard/amd/torpedo/acpi/sata.asl delete mode 100644 src/mainboard/amd/torpedo/acpi/usb.asl delete mode 100644 src/mainboard/amd/torpedo/acpi_tables.c delete mode 100644 src/mainboard/amd/torpedo/board_info.txt delete mode 100644 src/mainboard/amd/torpedo/buildOpts.c delete mode 100644 src/mainboard/amd/torpedo/cmos.layout delete mode 100644 src/mainboard/amd/torpedo/devicetree.cb delete mode 100644 src/mainboard/amd/torpedo/dsdt.asl delete mode 100644 src/mainboard/amd/torpedo/fadt.c delete mode 100644 src/mainboard/amd/torpedo/gpio.c delete mode 100644 src/mainboard/amd/torpedo/gpio.h delete mode 100644 src/mainboard/amd/torpedo/irq_tables.c delete mode 100644 src/mainboard/amd/torpedo/mainboard.c delete mode 100644 src/mainboard/amd/torpedo/mptable.c delete mode 100644 src/mainboard/amd/torpedo/platform_cfg.h delete mode 100644 src/mainboard/amd/torpedo/pmio.h delete mode 100644 src/mainboard/amd/torpedo/romstage.c diff --git a/src/mainboard/amd/torpedo/BiosCallOuts.c b/src/mainboard/amd/torpedo/BiosCallOuts.c deleted file mode 100644 index e7b0e29584..0000000000 --- a/src/mainboard/amd/torpedo/BiosCallOuts.c +++ /dev/null @@ -1,187 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include -#include "Hudson-2.h" -#include -#include - -static AGESA_STATUS board_BeforeDramInit (UINT32 Func, UINTN Data, VOID *ConfigPtr); -static AGESA_STATUS board_GnbPcieSlotReset (UINT32 Func, UINTN Data, VOID *ConfigPtr); - -const BIOS_CALLOUT_STRUCT BiosCallouts[] = -{ - {AGESA_DO_RESET, agesa_Reset }, - {AGESA_READ_SPD, agesa_ReadSpd }, - {AGESA_READ_SPD_RECOVERY, agesa_NoopUnsupported }, - {AGESA_RUNFUNC_ONAP, agesa_RunFuncOnAp }, - {AGESA_GNB_PCIE_SLOT_RESET, board_GnbPcieSlotReset }, - {AGESA_GET_IDS_INIT_DATA, agesa_EmptyIdsInitData }, - {AGESA_HOOKBEFORE_DRAM_INIT, board_BeforeDramInit }, - {AGESA_HOOKBEFORE_DRAM_INIT_RECOVERY, agesa_NoopSuccess }, - {AGESA_HOOKBEFORE_DQS_TRAINING, agesa_NoopSuccess }, - {AGESA_HOOKBEFORE_EXIT_SELF_REF, agesa_NoopSuccess }, -}; -const int BiosCalloutsLen = ARRAY_SIZE(BiosCallouts); - -/* Call the host environment interface to provide a user hook opportunity. */ -static AGESA_STATUS board_BeforeDramInit (UINT32 Func, UINTN Data, VOID *ConfigPtr) -{ - AGESA_STATUS Status; - UINTN FcnData; - MEM_DATA_STRUCT *MemData; - UINT32 AcpiMmioAddr; - UINT32 GpioMmioAddr; - UINT8 Data8; - UINT16 Data16; - - FcnData = Data; - MemData = ConfigPtr; - - Status = AGESA_SUCCESS; - /* Get SB MMIO Base (AcpiMmioAddr) */ - WriteIo8 (0xCD6, 0x27); - Data8 = ReadIo8(0xCD7); - Data16 = Data8 << 8; - WriteIo8 (0xCD6, 0x26); - Data8 = ReadIo8(0xCD7); - Data16 |= Data8; - AcpiMmioAddr = (UINT32)Data16 << 16; - GpioMmioAddr = AcpiMmioAddr + GPIO_BASE; - - switch (MemData->ParameterListPtr->DDR3Voltage) { - case VOLT1_35: - Data8 = Read64Mem8 (GpioMmioAddr+SB_GPIO_REG178); - Data8 &= ~(UINT8)BIT6; - Write64Mem8(GpioMmioAddr+SB_GPIO_REG178, Data8); - Data8 = Read64Mem8 (GpioMmioAddr+SB_GPIO_REG179); - Data8 |= (UINT8)BIT6; - Write64Mem8(GpioMmioAddr+SB_GPIO_REG179, Data8); - break; - case VOLT1_25: - Data8 = Read64Mem8 (GpioMmioAddr+SB_GPIO_REG178); - Data8 &= ~(UINT8)BIT6; - Write64Mem8(GpioMmioAddr+SB_GPIO_REG178, Data8); - Data8 = Read64Mem8 (GpioMmioAddr+SB_GPIO_REG179); - Data8 &= ~(UINT8)BIT6; - Write64Mem8(GpioMmioAddr+SB_GPIO_REG179, Data8); - break; - case VOLT1_5: - default: - Data8 = Read64Mem8 (GpioMmioAddr+SB_GPIO_REG178); - Data8 |= (UINT8)BIT6; - Write64Mem8(GpioMmioAddr+SB_GPIO_REG178, Data8); - } - return Status; -} - -/* PCIE slot reset control */ -static AGESA_STATUS board_GnbPcieSlotReset (UINT32 Func, UINTN Data, VOID *ConfigPtr) -{ - AGESA_STATUS Status; - UINTN FcnData; - PCIe_SLOT_RESET_INFO *ResetInfo; - - UINT32 GpioMmioAddr; - UINT32 AcpiMmioAddr; - UINT8 Data8; - UINT16 Data16; - - FcnData = Data; - ResetInfo = ConfigPtr; - // Get SB MMIO Base (AcpiMmioAddr) - WriteIo8(0xCD6, 0x27); - Data8 = ReadIo8(0xCD7); - Data16 = Data8 << 8; - WriteIo8(0xCD6, 0x26); - Data8 = ReadIo8(0xCD7); - Data16 |= Data8; - AcpiMmioAddr = (UINT32)Data16 << 16; - Status = AGESA_UNSUPPORTED; - GpioMmioAddr = AcpiMmioAddr + GPIO_BASE; - - if (ResetInfo->ResetControl == DeassertSlotReset) { - if (ResetInfo->ResetId & (BIT2+BIT3)) { //de-assert - // [GPIO] GPIO45: PE_GPIO1 MXM_POWER_ENABLE, SET HIGH - Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG45); - if (Data8 & BIT7) { - Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG28); - while (!(Data8 & BIT7)) { - Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG28); - } - // GPIO44: PE_GPIO0 MXM Reset - Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG44); - Data8 |= BIT6 ; - Write64Mem8 (GpioMmioAddr+SB_GPIO_REG44, Data8); - Status = AGESA_SUCCESS; - } - } else { - Status = AGESA_UNSUPPORTED; - } - // Travis - Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG24); - Data8 |= BIT6; - Write64Mem8 (GpioMmioAddr+SB_GPIO_REG24, Data8); - //DE-Assert ALL PCIE RESET - // APU GPP0 (Dev 4) - Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG25); - Data8 |= BIT6; - Write64Mem8 (GpioMmioAddr+SB_GPIO_REG25, Data8); - // APU GPP1 (Dev 5) - Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG01); - Data8 |= BIT6; - Write64Mem8 (GpioMmioAddr+SB_GPIO_REG01, Data8); - // APU GPP2 (Dev 6) - Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG00); - Data8 |= BIT6; - Write64Mem8 (GpioMmioAddr+SB_GPIO_REG00, Data8); - // APU GPP3 (Dev 7) - Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG27); - Data8 |= BIT6; - Write64Mem8 (GpioMmioAddr+SB_GPIO_REG27, Data8); - } else { - if (ResetInfo->ResetId & (BIT2+BIT3)) { //Pcie Slot Reset is supported - // GPIO44: PE_GPIO0 MXM Reset - Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG44); - Data8 &= ~(UINT8)BIT6; - Write64Mem8 (GpioMmioAddr+SB_GPIO_REG44, Data8); - Status = AGESA_SUCCESS; - } - // Travis - Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG24); - Data8 &= ~(UINT8)BIT6; - Write64Mem8 (GpioMmioAddr+SB_GPIO_REG24, Data8); - //Assert ALL PCIE RESET - // APU GPP0 (Dev 4) - Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG25); - Data8 &= ~(UINT8)BIT6; - Write64Mem8 (GpioMmioAddr+SB_GPIO_REG25, Data8); - // APU GPP1 (Dev 5) - Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG01); - Data8 &= ~(UINT8)BIT6; - Write64Mem8 (GpioMmioAddr+SB_GPIO_REG01, Data8); - // APU GPP2 (Dev 6) - Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG00); - Data8 &= ~(UINT8)BIT6; - Write64Mem8 (GpioMmioAddr+SB_GPIO_REG00, Data8); - // APU GPP3 (Dev 7) - Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG27); - Data8 &= ~(UINT8)BIT6; - Write64Mem8 (GpioMmioAddr+SB_GPIO_REG27, Data8); - } - return Status; -} diff --git a/src/mainboard/amd/torpedo/Kconfig b/src/mainboard/amd/torpedo/Kconfig deleted file mode 100644 index 7f72c0bf2f..0000000000 --- a/src/mainboard/amd/torpedo/Kconfig +++ /dev/null @@ -1,137 +0,0 @@ -# -# This file is part of the coreboot project. -# -# Copyright (C) 2011 Advanced Micro Devices, Inc. -# -# This program is free software; you can redistribute it and/or modify -# it under the terms of the GNU General Public License as published by -# the Free Software Foundation; version 2 of the License. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# - -if BOARD_AMD_TORPEDO - -config BOARD_SPECIFIC_OPTIONS - def_bool y - select CPU_AMD_AGESA_FAMILY12 - select NORTHBRIDGE_AMD_AGESA_FAMILY12 - select SOUTHBRIDGE_AMD_CIMX_SB900 - select SUPERIO_SMSC_KBC1100 - select HAVE_OPTION_TABLE - select HAVE_PIRQ_TABLE - select HAVE_MP_TABLE - select HAVE_ACPI_TABLES - select BOARD_ROMSIZE_KB_2048 - select GFXUMA - -config MAINBOARD_DIR - string - default amd/torpedo - -config MAINBOARD_PART_NUMBER - string - default "Torpedo" - -config HW_MEM_HOLE_SIZEK - hex - default 0x200000 - -config MAX_CPUS - int - default 4 - -config HT_CHAIN_END_UNITID_BASE - hex - default 0x1 - -config HT_CHAIN_UNITID_BASE - hex - default 0x0 - -config IRQ_SLOT_COUNT - int - default 11 - -config ONBOARD_VGA_IS_PRIMARY - bool - default y - -config VGA_BIOS - bool - default n - -#config VGA_BIOS_FILE -# string "VGA BIOS path and filename" -# depends on VGA_BIOS -# default "rom/video/LlanoGenericVbios.bin" - -config VGA_BIOS_ID - string "VGA device PCI IDs" - depends on VGA_BIOS - default "1002,9641" - -config AHCI_BIOS - bool - default n - -#config AHCI_BIOS_FILE -# string "AHCI ROM path and filename" -# depends on AHCI_BIOS -# default "rom/ahci/sb900.bin" - -config AHCI_BIOS_ID - string "AHCI device PCI IDs" - depends on AHCI_BIOS - default "1022,7801" - -config XHC_BIOS - bool - default n - -#config XHC_BIOS_FILE -# string "XHC BIOS path and filename" -# depends on XHC_BIOS -# default "rom/xhc/Xhc.rom" - -config XHC_BIOS_ID - string "XHC device PCI IDs" - depends on XHC_BIOS - default "1022,7812" - -config SATA_CONTROLLER_MODE - hex - default 0x0 - -config ONBOARD_LAN - bool - default y - -config ONBOARD_1394 - bool - default y - -config ONBOARD_USB30 - bool - default n - -config ONBOARD_BLUETOOTH - bool - default y - -config ONBOARD_WEBCAM - bool - default y - -config ONBOARD_TRAVIS - bool - default y - -config ONBOARD_LIGHTSENSOR - bool - default n - -endif # BOARD_AMD_TORPEDO diff --git a/src/mainboard/amd/torpedo/Kconfig.name b/src/mainboard/amd/torpedo/Kconfig.name deleted file mode 100644 index 066ff630a7..0000000000 --- a/src/mainboard/amd/torpedo/Kconfig.name +++ /dev/null @@ -1,2 +0,0 @@ -config BOARD_AMD_TORPEDO - bool "Torpedo" diff --git a/src/mainboard/amd/torpedo/Makefile.inc b/src/mainboard/amd/torpedo/Makefile.inc deleted file mode 100644 index 778b9828de..0000000000 --- a/src/mainboard/amd/torpedo/Makefile.inc +++ /dev/null @@ -1,37 +0,0 @@ -# -# This file is part of the coreboot project. -# -# Copyright (C) 2011 Advanced Micro Devices, Inc. -# -# This program is free software; you can redistribute it and/or modify -# it under the terms of the GNU General Public License as published by -# the Free Software Foundation; version 2 of the License. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# - -ifeq ($(CONFIG_AHCI_BIOS),y) -stripped_ahcibios_id = $(call strip_quotes,$(CONFIG_AHCI_BIOS_ID)) -cbfs-files-$(CONFIG_AHCI_BIOS) += pci$(stripped_ahcibios_id).rom -pci$(stripped_ahcibios_id).rom-file := $(call strip_quotes,$(CONFIG_AHCI_BIOS_FILE)) -pci$(stripped_ahcibios_id).rom-type := optionrom -endif - -ifeq ($(CONFIG_XHC_BIOS),y) -stripped_xhcbios_id = $(call strip_quotes,$(CONFIG_XHC_BIOS_ID)) -cbfs-files-$(CONFIG_XHC_BIOS) += pci$(stripped_xhcbios_id).rom -pci$(stripped_xhcbios_id).rom-file := $(call strip_quotes,$(CONFIG_XHC_BIOS_FILE)) -pci$(stripped_xhcbios_id).rom-type := optionrom -endif - -romstage-y += buildOpts.c -romstage-y += BiosCallOuts.c -romstage-y += OemCustomize.c -romstage-y += gpio.c - -ramstage-y += buildOpts.c -ramstage-y += BiosCallOuts.c -ramstage-y += OemCustomize.c diff --git a/src/mainboard/amd/torpedo/Oem.h b/src/mainboard/amd/torpedo/Oem.h deleted file mode 100644 index 07567aaed6..0000000000 --- a/src/mainboard/amd/torpedo/Oem.h +++ /dev/null @@ -1,217 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ -#ifndef BIOS_SIZE - #define BIOS_SIZE 0x04 //04 - 1MB -#endif -#define LEGACY_FREE 0x00 -#if !CONFIG(ONBOARD_USB30) - #define XHCI_SUPPORT 0x01 -#endif - -//#define ACPI_SLEEP_TRAP 0x01 // No sleep trap smi support in coreboot. -//#define SPREAD_SPECTRUM_EPROM_LOAD 0x01 - -/** - * Module Specific Defines for platform BIOS - * - */ - -/** - * PCIEX_BASE_ADDRESS - Define PCIE base address - */ -#ifdef MOVE_PCIEBAR_TO_F0000000 - #define PCIEX_BASE_ADDRESS 0xF7000000 -#else - #define PCIEX_BASE_ADDRESS 0xE0000000 -#endif - -/** - * SMBUS0_BASE_ADDRESS - Smbus base address - * - */ -#ifndef SMBUS0_BASE_ADDRESS - #define SMBUS0_BASE_ADDRESS 0xB00 -#endif - -/** - * SMBUS1_BASE_ADDRESS - Smbus1 (ASF) base address - * - */ -#ifndef SMBUS1_BASE_ADDRESS - #define SMBUS1_BASE_ADDRESS 0xB20 -#endif - -/** - * SIO_PME_BASE_ADDRESS - Super IO PME base address - * - */ -#ifndef SIO_PME_BASE_ADDRESS - #define SIO_PME_BASE_ADDRESS 0xE00 -#endif - -/** - * SPI_BASE_ADDRESS - SPI controller (ROM) base address - * - */ -#ifndef SPI_BASE_ADDRESS - #define SPI_BASE_ADDRESS 0xFEC10000 -#endif - -/** - * WATCHDOG_TIMER_BASE_ADDRESS - WATCHDOG timer base address - * - */ -#ifndef WATCHDOG_TIMER_BASE_ADDRESS - #define WATCHDOG_TIMER_BASE_ADDRESS 0xFEC000F0 // Watchdog Timer Base Address -#endif - -/** - * HPET_BASE_ADDRESS - HPET base address - * - */ -#ifndef HPET_BASE_ADDRESS - #define HPET_BASE_ADDRESS 0xFED00000 // HPET Base address -#endif - -/** - * ALT_ADDR_400 - For some BIOS codebases which use 0x400 as ACPI base address - * - */ -#ifdef ALT_ADDR_400 - #define ACPI_BLK_BASE 0x400 -#else - #define ACPI_BLK_BASE 0x800 -#endif - -#define PM1_STATUS_OFFSET 0x00 -#define PM1_ENABLE_OFFSET 0x02 -#define PM1_CONTROL_OFFSET 0x04 -#define PM_TIMER_OFFSET 0x08 -#define CPU_CONTROL_OFFSET 0x10 -#define EVENT_STATUS_OFFSET 0x20 -#define EVENT_ENABLE_OFFSET 0x24 - -/** - * PM1_EVT_BLK_ADDRESS - ACPI power management Event Block base address - * - */ -#define PM1_EVT_BLK_ADDRESS ACPI_BLK_BASE + PM1_STATUS_OFFSET // AcpiPm1EvtBlkAddr - -/** - * PM1_CNT_BLK_ADDRESS - ACPI power management Control block base address - * - */ -#define PM1_CNT_BLK_ADDRESS ACPI_BLK_BASE + PM1_CONTROL_OFFSET // AcpiPm1CntBlkAddr - -/** - * PM1_TMR_BLK_ADDRESS - ACPI power management Timer block base address - * - */ -#define PM1_TMR_BLK_ADDRESS ACPI_BLK_BASE + PM_TIMER_OFFSET // AcpiPmTmrBlkAddr - -/** - * CPU_CNT_BLK_ADDRESS - ACPI power management CPU Control block base address - * - */ -#define CPU_CNT_BLK_ADDRESS ACPI_BLK_BASE + CPU_CONTROL_OFFSET // CpuControlBlkAddr - -/** - * GPE0_BLK_ADDRESS - ACPI power management General Purpose Event block base address - * - */ -#define GPE0_BLK_ADDRESS ACPI_BLK_BASE + EVENT_STATUS_OFFSET // AcpiGpe0BlkAddr - -/** - * SMI_CMD_PORT - ACPI SMI Command block base address - * - */ -#define SMI_CMD_PORT 0xB0 // SmiCmdPortAddr - -/** - * ACPI_PMA_CNT_BLK_ADDRESS - ACPI power management additional control block base address - * - */ -#define ACPI_PMA_CNT_BLK_ADDRESS 0xFE00 // AcpiPmaCntBlkAddr - -/** - * SATA_IDE_MODE_SSID - Sata controller IDE mode SSID. - * Define value for SSID while SATA controller set to IDE mode. - */ -#define SATA_IDE_MODE_SSID 0x78001022 -/** - * SATA_RAID_MODE_SSID - Sata controller RAID mode SSID. - * Define value for SSID while SATA controller set to RAID mode. - */ -#define SATA_RAID_MODE_SSID 0x78021022 - -/** - * SATA_RAID5_MODE_SSID - Sata controller RAID5 mode SSID. - * Define value for SSID while SATA controller set to RAID5 mode. - */ -#define SATA_RAID5_MODE_SSID 0x78031022 - -/** - * SATA_AHCI_MODE_SSID - Sata controller AHCI mode SSID. - * Define value for SSID while SATA controller set to AHCI mode. - */ -#define SATA_AHCI_SSID 0x78011022 - -/** - * OHCI_SSID - All SB OHCI controllers SSID value. - * - */ -#define OHCI_SSID 0x78071022 - -/** - * EHCI_SSID - All SB EHCI controllers SSID value. - * - */ -#define EHCI_SSID 0x78081022 - -/** - * OHCI4_SSID - OHCI (USB 1.1 mode *HW force) controllers SSID value. - * - */ -#define OHCI4_SSID 0x78091022 - -/** - * SMBUS_SSID - Smbus controller (South Bridge device 0x14 function 0) SSID value. - * - */ -#define SMBUS_SSID 0x780B1022 - -/** - * IDE_SSID - SATA IDE controller (South Bridge device 0x14 function 1) SSID value. - * - */ -#define IDE_SSID 0x780C1022 - -/** - * AZALIA_SSID - AZALIA controller (South Bridge device 0x14 function 2) SSID value. - * - */ -#define AZALIA_SSID 0x780D1022 - -/** - * LPC_SSID - LPC controller (South Bridge device 0x14 function 3) SSID value. - * - */ -#define LPC_SSID 0x780E1022 - -/** - * PCIB_SSID - PCIB controller (South Bridge device 0x14 function 4) SSID value. - * - */ -#define PCIB_SSID 0x780F1022 diff --git a/src/mainboard/amd/torpedo/OemCustomize.c b/src/mainboard/amd/torpedo/OemCustomize.c deleted file mode 100644 index 1ad6cde9db..0000000000 --- a/src/mainboard/amd/torpedo/OemCustomize.c +++ /dev/null @@ -1,131 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - - -#include -#include - -static const PCIe_PORT_DESCRIPTOR PortList[] = { - // Initialize Port descriptor (PCIe port, Lanes 8:15, PCI Device Number 2, ...) - { - 0, - PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 8, 15), - PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 2, - HotplugDisabled, - PcieGenMaxSupported, - PcieGenMaxSupported, - AspmDisabled, BIT2) - }, - // Initialize Port descriptor (PCIe port, Lanes 16:19, PCI Device Number 3, ...) - { - 0, - PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 16, 19), - PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 3, - HotplugDisabled, - PcieGenMaxSupported, - PcieGenMaxSupported, - AspmDisabled, BIT3) - }, - // Initialize Port descriptor (PCIe port, Lanes 4, PCI Device Number 4, ...) - { - 0, - PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 4, 4), - PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 4, - HotplugDisabled, - PcieGenMaxSupported, - PcieGenMaxSupported, - AspmDisabled, 0) - }, - // Initialize Port descriptor (PCIe port, Lanes 5, PCI Device Number 5, ...) - { - 0, - PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 5, 5), - PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 5, - HotplugDisabled, - PcieGenMaxSupported, - PcieGenMaxSupported, - AspmDisabled, 0) - }, - // Initialize Port descriptor (PCIe port, Lanes 6, PCI Device Number 6, ...) - { - 0, - PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 6, 6), - PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 6, - HotplugDisabled, - PcieGenMaxSupported, - PcieGenMaxSupported, - AspmDisabled, 0) - }, - // Initialize Port descriptor (PCIe port, Lanes 7, PCI Device Number 7, ...) - { - DESCRIPTOR_TERMINATE_LIST, - PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 7, 7), - PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 7, - HotplugDisabled, - PcieGenMaxSupported, - PcieGenMaxSupported, - AspmDisabled, 0) - } -}; - -static const PCIe_DDI_DESCRIPTOR DdiList[] = { - // Initialize Ddi descriptor (DDI interface Lanes 24:27, DdA, ...) - { - 0, - PCIE_ENGINE_DATA_INITIALIZER(PcieDdiEngine, 24, 27), - PCIE_DDI_DATA_INITIALIZER(ConnectorTypeNutmegDpToVga, Aux2, Hdp2) - }, - // Initialize Ddi descriptor (DDI interface Lanes 28:31, DdB, ...) - { - DESCRIPTOR_TERMINATE_LIST, - PCIE_ENGINE_DATA_INITIALIZER(PcieDdiEngine, 28, 31), - PCIE_DDI_DATA_INITIALIZER(ConnectorTypeEDP, Aux1, Hdp1) - } -}; - -static const PCIe_COMPLEX_DESCRIPTOR PcieComplex = { - .Flags = DESCRIPTOR_TERMINATE_LIST, - .SocketId = 0, - .PciePortList = PortList, - .DdiLinkList = DdiList, -}; - -void board_BeforeInitEarly(struct sysinfo *cb, AMD_EARLY_PARAMS *InitEarly) -{ - InitEarly->GnbConfig.PcieComplexList = &PcieComplex; - InitEarly->GnbConfig.PsppPolicy = 0; -} - -/*---------------------------------------------------------------------------------------- - * CUSTOMER OVERIDES MEMORY TABLE - *---------------------------------------------------------------------------------------- - */ - -/* - * Platform Specific Overriding Table allows IBV/OEM to pass in platform information to AGESA - * (e.g. MemClk routing, the number of DIMM slots per channel,...). If PlatformSpecificTable - * is populated, AGESA will base its settings on the data from the table. Otherwise, it will - * use its default conservative settings. - */ -static CONST PSO_ENTRY ROMDATA PlatformMemoryTable[] = { - NUMBER_OF_DIMMS_SUPPORTED(ANY_SOCKET, ANY_CHANNEL, 1), - NUMBER_OF_CHANNELS_SUPPORTED(ANY_SOCKET, 2), - PSO_END -}; - -void board_BeforeInitPost(struct sysinfo *cb, AMD_POST_PARAMS *InitPost) -{ - InitPost->MemConfig.PlatformMemoryConfiguration = (PSO_ENTRY *)PlatformMemoryTable; -} diff --git a/src/mainboard/amd/torpedo/OptionsIds.h b/src/mainboard/amd/torpedo/OptionsIds.h deleted file mode 100644 index 45abcabf77..0000000000 --- a/src/mainboard/amd/torpedo/OptionsIds.h +++ /dev/null @@ -1,56 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -/** - * @file - * - * IDS Option File - * - * This file is used to switch on/off IDS features. - * - */ -#ifndef _OPTION_IDS_H_ -#define _OPTION_IDS_H_ - -/** - * - * This file generates the defaults tables for the Integrated Debug Support - * Module. The documented build options are imported from a user controlled - * file for processing. The build options for the Integrated Debug Support - * Module are listed below: - * - * IDSOPT_IDS_ENABLED - * IDSOPT_ERROR_TRAP_ENABLED - * IDSOPT_CONTROL_ENABLED - * IDSOPT_TRACING_ENABLED - * IDSOPT_PERF_ANALYSIS - * IDSOPT_ASSERT_ENABLED - * IDS_DEBUG_PORT - * IDSOPT_CAR_CORRUPTION_CHECK_ENABLED - * - **/ - -//#define IDSOPT_IDS_ENABLED TRUE -//#define IDSOPT_TRACING_ENABLED TRUE -#define IDSOPT_ASSERT_ENABLED TRUE - -//#define IDSOPT_DEBUG_ENABLED FALSE -//#undef IDSOPT_HOST_SIMNOW -//#define IDSOPT_HOST_SIMNOW FALSE -//#undef IDSOPT_HOST_HDT -//#define IDSOPT_HOST_HDT FALSE -//#define IDS_DEBUG_PORT 0x80 - -#endif diff --git a/src/mainboard/amd/torpedo/acpi/ide.asl b/src/mainboard/amd/torpedo/acpi/ide.asl deleted file mode 100644 index 59ea078593..0000000000 --- a/src/mainboard/amd/torpedo/acpi/ide.asl +++ /dev/null @@ -1,240 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -/* -Scope (_SB) { - Device(PCI0) { - Device(IDEC) { - Name(_ADR, 0x00140001) - #include "ide.asl" - } - } -} -*/ - -/* Some timing tables */ -Name(UDTT, Package(){ /* Udma timing table */ - 120, 90, 60, 45, 30, 20, 15, 0 /* UDMA modes 0 -> 6 */ -}) - -Name(MDTT, Package(){ /* MWDma timing table */ - 480, 150, 120, 0 /* Legacy DMA modes 0 -> 2 */ -}) - -Name(POTT, Package(){ /* Pio timing table */ - 600, 390, 270, 180, 120, 0 /* PIO modes 0 -> 4 */ -}) - -/* Some timing register value tables */ -Name(MDRT, Package(){ /* MWDma timing register table */ - 0x77, 0x21, 0x20, 0xFF /* Legacy DMA modes 0 -> 2 */ -}) - -Name(PORT, Package(){ - 0x99, 0x47, 0x34, 0x22, 0x20, 0x99 /* PIO modes 0 -> 4 */ -}) - -OperationRegion(ICRG, PCI_Config, 0x40, 0x20) /* ide control registers */ - Field(ICRG, AnyAcc, NoLock, Preserve) -{ - PPTS, 8, /* Primary PIO Slave Timing */ - PPTM, 8, /* Primary PIO Master Timing */ - OFFSET(0x04), PMTS, 8, /* Primary MWDMA Slave Timing */ - PMTM, 8, /* Primary MWDMA Master Timing */ - OFFSET(0x08), PPCR, 8, /* Primary PIO Control */ - OFFSET(0x0A), PPMM, 4, /* Primary PIO master Mode */ - PPSM, 4, /* Primary PIO slave Mode */ - OFFSET(0x14), PDCR, 2, /* Primary UDMA Control */ - OFFSET(0x16), PDMM, 4, /* Primary UltraDMA Mode */ - PDSM, 4, /* Primary UltraDMA Mode */ -} - -Method(GTTM, 1) /* get total time*/ -{ - Store(And(Arg0, 0x0F), Local0) /* Recovery Width */ - Increment(Local0) - Store(ShiftRight(Arg0, 4), Local1) /* Command Width */ - Increment(Local1) - Return(Multiply(30, Add(Local0, Local1))) -} - -Device(PRID) -{ - Name (_ADR, Zero) - Method(_GTM, 0, Serialized) - { - NAME(OTBF, Buffer(20) { /* out buffer */ - 0xFF, 0xFF, 0xFF, 0xFF, - 0xFF, 0xFF, 0xFF, 0xFF, - 0xFF, 0xFF, 0xFF, 0xFF, - 0xFF, 0xFF, 0xFF, 0xFF, 0x00, 0x00, 0x00, 0x00 - }) - - CreateDwordField(OTBF, 0, PSD0) /* PIO spd0 */ - CreateDwordField(OTBF, 4, DSD0) /* DMA spd0 */ - CreateDwordField(OTBF, 8, PSD1) /* PIO spd1 */ - CreateDwordField(OTBF, 12, DSD1) /* DMA spd1 */ - CreateDwordField(OTBF, 16, BFFG) /* buffer flags */ - - /* Just return if the channel is disabled */ - If(And(PPCR, 0x01)) { /* primary PIO control */ - Return(OTBF) - } - - /* Always tell them independent timing available and IOChannelReady used on both drives */ - Or(BFFG, 0x1A, BFFG) - - Store(GTTM(PPTM), PSD0) /* save total time of primary PIO master timming to PIO spd0 */ - Store(GTTM(PPTS), PSD1) /* save total time of primary PIO slave Timing to PIO spd1 */ - - If(And(PDCR, 0x01)) { /* It's under UDMA mode */ - Or(BFFG, 0x01, BFFG) - Store(DerefOf(Index(UDTT, PDMM)), DSD0) - } - Else { - Store(GTTM(PMTM), DSD0) /* Primary MWDMA Master Timing, DmaSpd0 */ - } - - If(And(PDCR, 0x02)) { /* It's under UDMA mode */ - Or(BFFG, 0x04, BFFG) - Store(DerefOf(Index(UDTT, PDSM)), DSD1) - } - Else { - Store(GTTM(PMTS), DSD1) /* Primary MWDMA Slave Timing, DmaSpd0 */ - } - - Return(OTBF) /* out buffer */ - } /* End Method(_GTM) */ - - Method(_STM, 3, Serialized) - { - NAME(INBF, Buffer(20) { /* in buffer */ - 0xFF, 0xFF, 0xFF, 0xFF, - 0xFF, 0xFF, 0xFF, 0xFF, - 0xFF, 0xFF, 0xFF, 0xFF, - 0xFF, 0xFF, 0xFF, 0xFF, 0x00, 0x00, 0x00, 0x00 - }) - - CreateDwordField(INBF, 0, PSD0) /* PIO spd0 */ - CreateDwordField(INBF, 4, DSD0) /* PIO spd0 */ - CreateDwordField(INBF, 8, PSD1) /* PIO spd1 */ - CreateDwordField(INBF, 12, DSD1) /* DMA spd1 */ - CreateDwordField(INBF, 16, BFFG) /*buffer flag */ - - Store(Match(POTT, MLE, PSD0, MTR, 0, 0), Local0) - Divide(Local0, 5, PPMM,) /* Primary PIO master Mode */ - Store(Match(POTT, MLE, PSD1, MTR, 0, 0), Local1) - Divide(Local1, 5, PPSM,) /* Primary PIO slave Mode */ - - Store(DerefOf(Index(PORT, Local0)), PPTM) /* Primary PIO Master Timing */ - Store(DerefOf(Index(PORT, Local1)), PPTS) /* Primary PIO Slave Timing */ - - If(And(BFFG, 0x01)) { /* Drive 0 is under UDMA mode */ - Store(Match(UDTT, MLE, DSD0, MTR, 0, 0), Local0) - Divide(Local0, 7, PDMM,) - Or(PDCR, 0x01, PDCR) - } - Else { - If(LNotEqual(DSD0, 0xFFFFFFFF)) { - Store(Match(MDTT, MLE, DSD0, MTR, 0, 0), Local0) - Store(DerefOf(Index(MDRT, Local0)), PMTM) - } - } - - If(And(BFFG, 0x04)) { /* Drive 1 is under UDMA mode */ - Store(Match(UDTT, MLE, DSD1, MTR, 0, 0), Local0) - Divide(Local0, 7, PDSM,) - Or(PDCR, 0x02, PDCR) - } - Else { - If(LNotEqual(DSD1, 0xFFFFFFFF)) { - Store(Match(MDTT, MLE, DSD1, MTR, 0, 0), Local0) - Store(DerefOf(Index(MDRT, Local0)), PMTS) - } - } - /* Return(INBF) */ - } /*End Method(_STM) */ - Device(MST) - { - Name(_ADR, 0) - Method(_GTF, 0, Serialized) { - Name(CMBF, Buffer(21) { - 0x03, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xEF, - 0x03, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xEF, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xF5 - }) - CreateByteField(CMBF, 1, POMD) - CreateByteField(CMBF, 8, DMMD) - CreateByteField(CMBF, 5, CMDA) - CreateByteField(CMBF, 12, CMDB) - CreateByteField(CMBF, 19, CMDC) - - Store(0xA0, CMDA) - Store(0xA0, CMDB) - Store(0xA0, CMDC) - - Or(PPMM, 0x08, POMD) - - If(And(PDCR, 0x01)) { - Or(PDMM, 0x40, DMMD) - } - Else { - Store(Match - (MDTT, MLE, GTTM(PMTM), - MTR, 0, 0), Local0) - If(LLess(Local0, 3)) { - Or(0x20, Local0, DMMD) - } - } - Return(CMBF) - } - } /* End Device(MST) */ - - Device(SLAV) - { - Name(_ADR, 1) - Method(_GTF, 0, Serialized) { - Name(CMBF, Buffer(21) { - 0x03, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xEF, - 0x03, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xEF, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xF5 - }) - CreateByteField(CMBF, 1, POMD) - CreateByteField(CMBF, 8, DMMD) - CreateByteField(CMBF, 5, CMDA) - CreateByteField(CMBF, 12, CMDB) - CreateByteField(CMBF, 19, CMDC) - - Store(0xB0, CMDA) - Store(0xB0, CMDB) - Store(0xB0, CMDC) - - Or(PPSM, 0x08, POMD) - - If(And(PDCR, 0x02)) { - Or(PDSM, 0x40, DMMD) - } - Else { - Store(Match - (MDTT, MLE, GTTM(PMTS), - MTR, 0, 0), Local0) - If(LLess(Local0, 3)) { - Or(0x20, Local0, DMMD) - } - } - Return(CMBF) - } - } /* End Device(SLAV) */ -} diff --git a/src/mainboard/amd/torpedo/acpi/routing.asl b/src/mainboard/amd/torpedo/acpi/routing.asl deleted file mode 100644 index 5df2eeb3af..0000000000 --- a/src/mainboard/amd/torpedo/acpi/routing.asl +++ /dev/null @@ -1,308 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -/* -#include -DefinitionBlock ("DSDT.AML", "DSDT", 0x01, OEM_ID, ACPI_TABLE_CREATOR, 0x00010001 - ) - { - #include "routing.asl" - } -*/ - -/* Routing is in System Bus scope */ -Scope(\_SB) { - Name(PR0, Package(){ - /* NB devices */ - /* Bus 0, Dev 0 - RS780 Host Controller */ - /* Bus 0, Dev 1 - PCI Bridge for Internal Graphics */ - Package(){0x0001FFFF, 0, INTC, 0 }, - Package(){0x0001FFFF, 1, INTD, 0 }, - /* Bus 0, Dev 2 - */ - Package(){0x0002FFFF, 0, INTC, 0 }, - Package(){0x0002FFFF, 1, INTD, 0 }, - Package(){0x0002FFFF, 2, INTA, 0 }, - Package(){0x0002FFFF, 3, INTB, 0 }, - /* Bus 0, Dev 3 - */ - Package(){0x0003FFFF, 0, INTD, 0 }, - Package(){0x0003FFFF, 1, INTA, 0 }, - Package(){0x0003FFFF, 2, INTB, 0 }, - Package(){0x0003FFFF, 3, INTC, 0 }, - /* Bus 0, Dev 4 - PCIe Bridge for Express Card Slot */ - Package(){0x0004FFFF, 0, INTA, 0 }, - Package(){0x0004FFFF, 1, INTB, 0 }, - Package(){0x0004FFFF, 2, INTC, 0 }, - Package(){0x0004FFFF, 3, INTD, 0 }, - /* Bus 0, Dev 5 - General purpose PCIe bridge 5 */ - Package(){0x0005FFFF, 0, INTB, 0 }, - Package(){0x0005FFFF, 1, INTC, 0 }, - Package(){0x0005FFFF, 2, INTD, 0 }, - Package(){0x0005FFFF, 3, INTA, 0 }, - /* Bus 0, Dev 6 - PCIe Bridge for Ethernet Chip */ - Package(){0x0006FFFF, 0, INTC, 0 }, - Package(){0x0006FFFF, 1, INTD, 0 }, - Package(){0x0006FFFF, 2, INTA, 0 }, - Package(){0x0006FFFF, 3, INTB, 0 }, - /* Bus 0, Dev 7 - PCIe Bridge for x1 PCIe Slot */ - Package(){0x0007FFFF, 0, INTD, 0 }, - Package(){0x0007FFFF, 1, INTA, 0 }, - Package(){0x0007FFFF, 2, INTB, 0 }, - Package(){0x0007FFFF, 3, INTC, 0 }, - - /* SB devices */ - /* Bus 0, Dev 20 - F0:SMBus/ACPI,F1:IDE;F2:HDAudio;F3:LPC;F4:PCIBridge;F5:USB */ - Package(){0x0014FFFF, 0, INTA, 0 }, - Package(){0x0014FFFF, 1, INTB, 0 }, - Package(){0x0014FFFF, 2, INTC, 0 }, - Package(){0x0014FFFF, 3, INTD, 0 }, - /* Bus 0, Dev 18,19,22 - USB: OHCI,EHCI */ - Package(){0x0012FFFF, 0, INTC, 0 }, - Package(){0x0012FFFF, 1, INTB, 0 }, - Package(){0x0013FFFF, 0, INTC, 0 }, - Package(){0x0013FFFF, 1, INTB, 0 }, - Package(){0x0016FFFF, 0, INTC, 0 }, - Package(){0x0016FFFF, 1, INTB, 0 }, - Package(){0x0010FFFF, 0, INTC, 0 }, - Package(){0x0010FFFF, 1, INTB, 0 }, - /* Bus 0, Dev 17 - SATA controller #2 */ - Package(){0x0011FFFF, 0, INTD, 0 }, - /* Bus 0, Dev 21 - PCIe Bridge for x1 PCIe Slot */ - Package(){0x0015FFFF, 0, INTA, 0 }, - Package(){0x0015FFFF, 1, INTB, 0 }, - Package(){0x0015FFFF, 2, INTC, 0 }, - Package(){0x0015FFFF, 3, INTD, 0 }, - }) - - Name(APR0, Package(){ - /* NB devices in APIC mode */ - /* Bus 0, Dev 0 - RS780 Host Controller */ - /* Bus 0, Dev 1 - PCI Bridge for Internal Graphics */ - Package(){0x0001FFFF, 0, 0, 18 }, - Package(){0x0001FFFF, 1, 0, 19 }, - /* Bus 0, Dev 2 */ - Package(){0x0002FFFF, 0, 0, 18 }, - Package(){0x0002FFFF, 1, 0, 19 }, - Package(){0x0002FFFF, 2, 0, 16 }, - Package(){0x0002FFFF, 3, 0, 17 }, - /* Bus 0, Dev 3 */ - Package(){0x0003FFFF, 0, 0, 19 }, - Package(){0x0003FFFF, 1, 0, 16 }, - Package(){0x0003FFFF, 2, 0, 17 }, - Package(){0x0003FFFF, 3, 0, 18 }, - /* Bus 0, Dev 4 - PCIe Bridge for Express Card Slot */ - Package(){0x0004FFFF, 0, 0, 16 }, - Package(){0x0004FFFF, 1, 0, 17 }, - Package(){0x0004FFFF, 2, 0, 18 }, - Package(){0x0004FFFF, 3, 0, 19 }, - /* Bus 0, Dev 5 - General purpose PCIe bridge 5 */ - Package(){0x0005FFFF, 0, 0, 17 }, - Package(){0x0005FFFF, 1, 0, 18 }, - Package(){0x0005FFFF, 2, 0, 19 }, - Package(){0x0005FFFF, 3, 0, 16 }, - /* Bus 0, Dev 6 - General purpose PCIe bridge 6 */ - Package(){0x0006FFFF, 0, 0, 18 }, - Package(){0x0006FFFF, 1, 0, 19 }, - Package(){0x0006FFFF, 2, 0, 16 }, - Package(){0x0006FFFF, 3, 0, 17 }, - /* Bus 0, Dev 7 - PCIe Bridge for network card */ - Package(){0x0007FFFF, 0, 0, 19 }, - Package(){0x0007FFFF, 1, 0, 16 }, - Package(){0x0007FFFF, 2, 0, 17 }, - Package(){0x0007FFFF, 3, 0, 18 }, - - /* SB devices in APIC mode */ - /* Bus 0, Dev 20 - F0:SMBus/ACPI, F1:IDE; F2:HDAudio; F3:LPC; F4:PCIBridge; F5:USB */ - Package(){0x0014FFFF, 0, 0, 16 }, - Package(){0x0014FFFF, 1, 0, 17 }, - Package(){0x0014FFFF, 2, 0, 18 }, - Package(){0x0014FFFF, 3, 0, 19 }, - /* Bus 0, Dev 18,19,22 - USB: OHCI,EHCI*/ - Package(){0x0012FFFF, 0, 0, 18 }, - Package(){0x0012FFFF, 1, 0, 17 }, - Package(){0x0013FFFF, 0, 0, 18 }, - Package(){0x0013FFFF, 1, 0, 17 }, - Package(){0x0016FFFF, 0, 0, 18 }, - Package(){0x0016FFFF, 1, 0, 17 }, - Package(){0x0010FFFF, 0, 0, 18 }, - Package(){0x0010FFFF, 1, 0, 17 }, - /* Bus 0, Dev 17 - SATA controller #2 */ - Package(){0x0011FFFF, 0, 0, 19 }, - /* Bus 0, Dev 21 - PCIe Bridge for x1 PCIe Slot */ - Package(){0x0015FFFF, 0, 0, 16 }, - Package(){0x0015FFFF, 1, 0, 17 }, - Package(){0x0015FFFF, 2, 0, 18 }, - Package(){0x0015FFFF, 3, 0, 19 }, - }) - - Name(PS2, Package(){ - /* For Device(PBR2) PIC mode*/ - Package(){0x0000FFFF, 0, INTC, 0 }, - Package(){0x0000FFFF, 1, INTD, 0 }, - Package(){0x0000FFFF, 2, INTA, 0 }, - Package(){0x0000FFFF, 3, INTB, 0 }, - }) - - Name(APS2, Package(){ - /* For Device(PBR2) APIC mode*/ - Package(){0x0000FFFF, 0, 0, 18 }, - Package(){0x0000FFFF, 1, 0, 19 }, - Package(){0x0000FFFF, 2, 0, 16 }, - Package(){0x0000FFFF, 3, 0, 17 }, - }) - - Name(PS3, Package(){ - /* For Device(PBR3) PIC mode*/ - Package(){0x0000FFFF, 0, INTD, 0 }, - Package(){0x0000FFFF, 1, INTA, 0 }, - Package(){0x0000FFFF, 2, INTB, 0 }, - Package(){0x0000FFFF, 3, INTC, 0 }, - }) - - Name(APS3, Package(){ - /* For Device(PBR3) APIC mode*/ - Package(){0x0000FFFF, 0, 0, 19 }, - Package(){0x0000FFFF, 1, 0, 16 }, - Package(){0x0000FFFF, 2, 0, 17 }, - Package(){0x0000FFFF, 3, 0, 18 }, - }) - - Name(PS4, Package(){ - /* For Device(PBR4) PIC mode*/ - Package(){0x0000FFFF, 0, INTA, 0 }, - Package(){0x0000FFFF, 1, INTB, 0 }, - Package(){0x0000FFFF, 2, INTC, 0 }, - Package(){0x0000FFFF, 3, INTD, 0 }, - }) - - Name(APS4, Package(){ - /* For Device(PBR4) APIC mode*/ - Package(){0x0000FFFF, 0, 0, 16 }, - Package(){0x0000FFFF, 1, 0, 17 }, - Package(){0x0000FFFF, 2, 0, 18 }, - Package(){0x0000FFFF, 3, 0, 19 }, - }) - - Name(PS5, Package(){ - /* For Device(PBR5) PIC mode*/ - Package(){0x0000FFFF, 0, INTB, 0 }, - Package(){0x0000FFFF, 1, INTC, 0 }, - Package(){0x0000FFFF, 2, INTD, 0 }, - Package(){0x0000FFFF, 3, INTA, 0 }, - }) - - Name(APS5, Package(){ - /* For Device(PBR5) APIC mode*/ - Package(){0x0000FFFF, 0, 0, 17 }, - Package(){0x0000FFFF, 1, 0, 18 }, - Package(){0x0000FFFF, 2, 0, 19 }, - Package(){0x0000FFFF, 3, 0, 16 }, - }) - - Name(PS6, Package(){ - /* For Device(PBR6) PIC mode*/ - Package(){0x0000FFFF, 0, INTC, 0 }, - Package(){0x0000FFFF, 1, INTD, 0 }, - Package(){0x0000FFFF, 2, INTA, 0 }, - Package(){0x0000FFFF, 3, INTB, 0 }, - }) - - Name(APS6, Package(){ - /* For Device(PBR6) APIC mode*/ - Package(){0x0000FFFF, 0, 0, 18 }, - Package(){0x0000FFFF, 1, 0, 19 }, - Package(){0x0000FFFF, 2, 0, 16 }, - Package(){0x0000FFFF, 3, 0, 17 }, - }) - - Name(PS7, Package(){ - /* For Device(PBR7) PIC mode*/ - Package(){0x0000FFFF, 0, INTD, 0 }, - Package(){0x0000FFFF, 1, INTA, 0 }, - Package(){0x0000FFFF, 2, INTB, 0 }, - Package(){0x0000FFFF, 3, INTC, 0 }, - }) - - Name(APS7, Package(){ - /* For Device(PBR7) APIC mode*/ - Package(){0x0000FFFF, 0, 0, 19 }, - Package(){0x0000FFFF, 1, 0, 16 }, - Package(){0x0000FFFF, 2, 0, 17 }, - Package(){0x0000FFFF, 3, 0, 18 }, - }) - - Name(PE0, Package(){ - /* For Device(PE20) PIC mode*/ - Package(){0x0000FFFF, 0, INTA, 0 }, - Package(){0x0000FFFF, 1, INTB, 0 }, - Package(){0x0000FFFF, 2, INTC, 0 }, - Package(){0x0000FFFF, 3, INTD, 0 }, - }) - - Name(APE0, Package(){ - /* For Device(PE20) APIC mode*/ - Package(){0x0000FFFF, 0, 0, 16 }, - Package(){0x0000FFFF, 1, 0, 17 }, - Package(){0x0000FFFF, 2, 0, 18 }, - Package(){0x0000FFFF, 3, 0, 19 }, - }) - - Name(PE1, Package(){ - /* For Device(PE21) PIC mode*/ - Package(){0x0000FFFF, 0, INTB, 0 }, - Package(){0x0000FFFF, 1, INTC, 0 }, - Package(){0x0000FFFF, 2, INTD, 0 }, - Package(){0x0000FFFF, 3, INTA, 0 }, - }) - - Name(APE1, Package(){ - /* For Device(PE21) APIC mode*/ - Package(){0x0000FFFF, 0, 0, 17 }, - Package(){0x0000FFFF, 1, 0, 18 }, - Package(){0x0000FFFF, 2, 0, 19 }, - Package(){0x0000FFFF, 3, 0, 16 }, - }) - - Name(PE2, Package(){ - /* For Device(PE22) PIC mode*/ - Package(){0x0000FFFF, 0, INTC, 0 }, - Package(){0x0000FFFF, 1, INTD, 0 }, - Package(){0x0000FFFF, 2, INTA, 0 }, - Package(){0x0000FFFF, 3, INTB, 0 }, - }) - - Name(APE2, Package(){ - /* For Device(PE22) APIC mode*/ - Package(){0x0000FFFF, 0, 0, 18 }, - Package(){0x0000FFFF, 1, 0, 19 }, - Package(){0x0000FFFF, 2, 0, 16 }, - Package(){0x0000FFFF, 3, 0, 17 }, - }) - - Name(PE3, Package(){ - /* For Device(PE23) PIC mode*/ - Package(){0x0000FFFF, 0, INTD, 0 }, - Package(){0x0000FFFF, 1, INTA, 0 }, - Package(){0x0000FFFF, 2, INTB, 0 }, - Package(){0x0000FFFF, 3, INTC, 0 }, - }) - - Name(APE3, Package(){ - /* For Device(PE23) APIC mode*/ - Package(){0x0000FFFF, 0, 0, 19 }, - Package(){0x0000FFFF, 1, 0, 16 }, - Package(){0x0000FFFF, 2, 0, 17 }, - Package(){0x0000FFFF, 3, 0, 18 }, - }) -} diff --git a/src/mainboard/amd/torpedo/acpi/sata.asl b/src/mainboard/amd/torpedo/acpi/sata.asl deleted file mode 100644 index 9e0e535da6..0000000000 --- a/src/mainboard/amd/torpedo/acpi/sata.asl +++ /dev/null @@ -1,145 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -/* simple name description */ - -/* -Scope (_SB) { - Device(PCI0) { - Device(SATA) { - Name(_ADR, 0x00110000) - #include "sata.asl" - } - } -} -*/ - -Name(STTM, Buffer(20) { - 0x78, 0x00, 0x00, 0x00, 0x0f, 0x00, 0x00, 0x00, - 0x78, 0x00, 0x00, 0x00, 0x0f, 0x00, 0x00, 0x00, - 0x1f, 0x00, 0x00, 0x00 -}) - -/* Start by clearing the PhyRdyChg bits */ -Method(_INI) { - \_GPE._L1F() -} - -Device(PMRY) -{ - Name(_ADR, 0) - Method(_GTM, 0x0, NotSerialized) { - Return(STTM) - } - Method(_STM, 0x3, NotSerialized) {} - - Device(PMST) { - Name(_ADR, 0) - Method(_STA,0) { - if (LGreater(P0IS,0)) { - return (0x0F) /* sata is visible */ - } - else { - return (0x00) /* sata is missing */ - } - } - }/* end of PMST */ - - Device(PSLA) - { - Name(_ADR, 1) - Method(_STA,0) { - if (LGreater(P1IS,0)) { - return (0x0F) /* sata is visible */ - } - else { - return (0x00) /* sata is missing */ - } - } - } /* end of PSLA */ -} /* end of PMRY */ - - -Device(SEDY) -{ - Name(_ADR, 1) /* IDE Scondary Channel */ - Method(_GTM, 0x0, NotSerialized) { - Return(STTM) - } - Method(_STM, 0x3, NotSerialized) {} - - Device(SMST) - { - Name(_ADR, 0) - Method(_STA,0) { - if (LGreater(P2IS,0)) { - return (0x0F) /* sata is visible */ - } - else { - return (0x00) /* sata is missing */ - } - } - } /* end of SMST */ - - Device(SSLA) - { - Name(_ADR, 1) - Method(_STA,0) { - if (LGreater(P3IS,0)) { - return (0x0F) /* sata is visible */ - } - else { - return (0x00) /* sata is missing */ - } - } - } /* end of SSLA */ -} /* end of SEDY */ - -/* SATA Hot Plug Support */ -Scope(\_GPE) { - Method(_L1F,0x0,NotSerialized) { - if (\_SB.P0PR) { - if (LGreater(\_SB.P0IS,0)) { - sleep(32) - } - Notify(\_SB.PCI0.STCR.PMRY.PMST, 0x01) /* NOTIFY_DEVICE_CHECK */ - store(one, \_SB.P0PR) - } - - if (\_SB.P1PR) { - if (LGreater(\_SB.P1IS,0)) { - sleep(32) - } - Notify(\_SB.PCI0.STCR.PMRY.PSLA, 0x01) /* NOTIFY_DEVICE_CHECK */ - store(one, \_SB.P1PR) - } - - if (\_SB.P2PR) { - if (LGreater(\_SB.P2IS,0)) { - sleep(32) - } - Notify(\_SB.PCI0.STCR.SEDY.SMST, 0x01) /* NOTIFY_DEVICE_CHECK */ - store(one, \_SB.P2PR) - } - - if (\_SB.P3PR) { - if (LGreater(\_SB.P3IS,0)) { - sleep(32) - } - Notify(\_SB.PCI0.STCR.SEDY.SSLA, 0x01) /* NOTIFY_DEVICE_CHECK */ - store(one, \_SB.P3PR) - } - } -} diff --git a/src/mainboard/amd/torpedo/acpi/usb.asl b/src/mainboard/amd/torpedo/acpi/usb.asl deleted file mode 100644 index e69de29bb2..0000000000 diff --git a/src/mainboard/amd/torpedo/acpi_tables.c b/src/mainboard/amd/torpedo/acpi_tables.c deleted file mode 100644 index 7d7d86cc95..0000000000 --- a/src/mainboard/amd/torpedo/acpi_tables.c +++ /dev/null @@ -1,52 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include - -extern u32 apicid_sb900; - -unsigned long acpi_fill_madt(unsigned long current) -{ - /* create all subtables for processors */ - current += acpi_create_madt_lapic((acpi_madt_lapic_t *)current, 0, 0); - current += acpi_create_madt_lapic((acpi_madt_lapic_t *)current, 1, 1); - current += acpi_create_madt_lapic((acpi_madt_lapic_t *)current, 2, 2); - current += acpi_create_madt_lapic((acpi_madt_lapic_t *)current, 3, 3); - - /* Write SB900 IOAPIC, only one */ - current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, apicid_sb900, - IO_APIC_ADDR, 0); - - current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) - current, 0, 0, 2, 0); - current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) - current, 0, 9, 9, 0xF); - - /* 0: mean bus 0--->ISA */ - /* 0: PIC 0 */ - /* 2: APIC 2 */ - /* 5 mean: 0101 --> Edge-triggered, Active high */ - - /* create all subtables for processors */ - current += acpi_create_madt_lapic_nmi((acpi_madt_lapic_nmi_t *)current, 0, 5, 1); - current += acpi_create_madt_lapic_nmi((acpi_madt_lapic_nmi_t *)current, 1, 5, 1); - current += acpi_create_madt_lapic_nmi((acpi_madt_lapic_nmi_t *)current, 2, 5, 1); - current += acpi_create_madt_lapic_nmi((acpi_madt_lapic_nmi_t *)current, 3, 5, 1); - /* 1: LINT1 connect to NMI */ - - return current; -} diff --git a/src/mainboard/amd/torpedo/board_info.txt b/src/mainboard/amd/torpedo/board_info.txt deleted file mode 100644 index b351b8e696..0000000000 --- a/src/mainboard/amd/torpedo/board_info.txt +++ /dev/null @@ -1 +0,0 @@ -Category: eval diff --git a/src/mainboard/amd/torpedo/buildOpts.c b/src/mainboard/amd/torpedo/buildOpts.c deleted file mode 100644 index fbeee9aedd..0000000000 --- a/src/mainboard/amd/torpedo/buildOpts.c +++ /dev/null @@ -1,221 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -/** - * @file - * - * AMD User options selection for a Sabine/Lynx platform solution system - * - * This file is placed in the user's platform directory and contains the - * build option selections desired for that platform. - * - * For Information about this file, see @ref platforminstall. - * - */ - -#include -#include - - -/* Select the CPU family. */ -#define INSTALL_FAMILY_10_SUPPORT FALSE -#define INSTALL_FAMILY_12_SUPPORT TRUE -#define INSTALL_FAMILY_14_SUPPORT FALSE -#define INSTALL_FAMILY_15_SUPPORT FALSE - -/* Select the CPU socket type. */ -#define INSTALL_G34_SOCKET_SUPPORT FALSE -#define INSTALL_C32_SOCKET_SUPPORT FALSE -#define INSTALL_S1G3_SOCKET_SUPPORT FALSE -#define INSTALL_S1G4_SOCKET_SUPPORT FALSE -#define INSTALL_ASB2_SOCKET_SUPPORT FALSE -#define INSTALL_FS1_SOCKET_SUPPORT TRUE -#define INSTALL_FM1_SOCKET_SUPPORT FALSE -#define INSTALL_FP1_SOCKET_SUPPORT TRUE -#define INSTALL_FT1_SOCKET_SUPPORT FALSE -#define INSTALL_AM3_SOCKET_SUPPORT FALSE - -/* - * Agesa optional capabilities selection. - * Uncomment and mark FALSE those features you wish to include in the build. - * Comment out or mark TRUE those features you want to REMOVE from the build. - */ - -#define BLDOPT_REMOVE_UDIMMS_SUPPORT FALSE -#define BLDOPT_REMOVE_RDIMMS_SUPPORT FALSE -#define BLDOPT_REMOVE_ECC_SUPPORT FALSE -#define BLDOPT_REMOVE_BANK_INTERLEAVE FALSE -#define BLDOPT_REMOVE_DCT_INTERLEAVE FALSE -#define BLDOPT_REMOVE_NODE_INTERLEAVE TRUE -#define BLDOPT_REMOVE_PARALLEL_TRAINING TRUE -#define BLDOPT_REMOVE_ONLINE_SPARE_SUPPORT TRUE -#define BLDOPT_REMOVE_MEM_RESTORE_SUPPORT FALSE -#define BLDOPT_REMOVE_DDR2_SUPPORT TRUE -#define BLDOPT_REMOVE_DDR3_SUPPORT FALSE -#define BLDOPT_REMOVE_MULTISOCKET_SUPPORT TRUE -#define BLDOPT_REMOVE_ACPI_PSTATES FALSE -#define BLDOPT_REMOVE_SRAT TRUE -#define BLDOPT_REMOVE_SLIT TRUE -#define BLDOPT_REMOVE_WHEA TRUE -#define BLDOPT_REMOVE_DMI FALSE -#define BLDOPT_REMOVE_EARLY_SAMPLES TRUE -#define BLDCFG_REMOVE_ACPI_PSTATES_PPC FALSE -#define BLDCFG_REMOVE_ACPI_PSTATES_PCT FALSE -#define BLDCFG_REMOVE_ACPI_PSTATES_PSD FALSE -#define BLDCFG_REMOVE_ACPI_PSTATES_PSS FALSE -#define BLDCFG_REMOVE_ACPI_PSTATES_XPSS FALSE - -//For revision C single-link processors -#define BLDCFG_SUPPORT_ACPI_PSTATES_PSD_INDPX TRUE - - -/***************************************************************************** - * Define the RELEASE VERSION string - * - * The Release Version string should identify the next planned release. - * When a branch is made in preparation for a release, the release manager - * should change/confirm that the branch version of this file contains the - * string matching the desired version for the release. The trunk version of - * the file should always contain a trailing 'X'. This will make sure that a - * development build from trunk will not be confused for a released version. - * The release manager will need to remove the trailing 'X' and update the - * version string as appropriate for the release. The trunk copy of this file - * should also be updated/incremented for the next expected version, + trailing 'X' - ****************************************************************************/ - // This is the delivery package title, "LlanoPI " - // This string MUST be exactly 8 characters long -#define AGESA_PACKAGE_STRING {'L', 'l', 'a', 'n', 'o', 'P', 'I', ' '} - - // This is the release version number of the AGESA component - // This string MUST be exactly 12 characters long -#define AGESA_VERSION_STRING {'V', '1', '.', '1', '.', '0', '.', '0', ' ', ' ', ' ', ' '} - -/* The following definitions specify the default values for various parameters - * in which there are no clearly defined defaults to be used in the common file. - * The values below are based on product and BKDG content, please consult the - * AGESA Memory team for consultation. - */ -#define DFLT_SCRUB_DRAM_RATE (0) -#define DFLT_SCRUB_L2_RATE (0) -#define DFLT_SCRUB_L3_RATE (0) -#define DFLT_SCRUB_IC_RATE (0) -#define DFLT_SCRUB_DC_RATE (0) -#define DFLT_MEMORY_QUADRANK_TYPE QUADRANK_UNBUFFERED -#define DFLT_VRM_SLEW_RATE (5000) - -/* Build configuration values here. - */ -#define BLDCFG_VRM_CURRENT_LIMIT 65000 //240000 //120000 -#define BLDCFG_VRM_LOW_POWER_THRESHOLD 15000 // 0 -#define BLDCFG_VRM_INRUSH_CURRENT_LIMIT 0 -#define BLDCFG_PLAT_NUM_IO_APICS 3 -#define BLDCFG_CORE_LEVELING_MODE CORE_LEVEL_LOWEST -#define BLDCFG_MEM_INIT_PSTATE 0 - -#define BLDCFG_AMD_PLATFORM_TYPE AMD_PLATFORM_MOBILE - -#define BLDCFG_MEMORY_BUS_FREQUENCY_LIMIT DDR1866_FREQUENCY //DDR1066_FREQUENCY -#define BLDCFG_MEMORY_MODE_UNGANGED TRUE -#define BLDCFG_MEMORY_QUAD_RANK_CAPABLE TRUE -#define BLDCFG_MEMORY_QUADRANK_TYPE QUADRANK_REGISTERED -#define BLDCFG_MEMORY_RDIMM_CAPABLE TRUE -#define BLDCFG_MEMORY_UDIMM_CAPABLE TRUE -#define BLDCFG_MEMORY_SODIMM_CAPABLE TRUE -#define BLDCFG_MEMORY_ENABLE_BANK_INTERLEAVING TRUE -#define BLDCFG_MEMORY_ENABLE_NODE_INTERLEAVING FALSE -#define BLDCFG_MEMORY_CHANNEL_INTERLEAVING TRUE -#define BLDCFG_MEMORY_POWER_DOWN TRUE -#define BLDCFG_POWER_DOWN_MODE POWER_DOWN_BY_CHIP_SELECT -#define BLDCFG_ONLINE_SPARE FALSE -#define BLDCFG_MEMORY_PARITY_ENABLE FALSE -#define BLDCFG_BANK_SWIZZLE TRUE -#define BLDCFG_TIMING_MODE_SELECT TIMING_MODE_AUTO -#define BLDCFG_MEMORY_CLOCK_SELECT DDR800_FREQUENCY -#define BLDCFG_DQS_TRAINING_CONTROL TRUE -#define BLDCFG_IGNORE_SPD_CHECKSUM FALSE -#define BLDCFG_USE_BURST_MODE FALSE -#define BLDCFG_MEMORY_ALL_CLOCKS_ON FALSE -#define BLDCFG_ENABLE_ECC_FEATURE TRUE -#define BLDCFG_ECC_REDIRECTION FALSE -#define BLDCFG_SCRUB_DRAM_RATE 0 -#define BLDCFG_SCRUB_L2_RATE 0 -#define BLDCFG_SCRUB_L3_RATE 0 -#define BLDCFG_SCRUB_IC_RATE 0 -#define BLDCFG_SCRUB_DC_RATE 0 -#define BLDCFG_ECC_SYNC_FLOOD FALSE -#define BLDCFG_ECC_SYMBOL_SIZE 4 -#define BLDCFG_HEAP_DRAM_ADDRESS 0xB0000 -#define BLDCFG_1GB_ALIGN FALSE -#define BLDCFG_VRM_HIGH_SPEED_ENABLE TRUE -//#define BLDCFG_PROCESSOR_SCOPE_NAME0 'C' -//#define BLDCFG_PROCESSOR_SCOPE_NAME1 '0' - -//enable HW C1E -#define BLDCFG_PLATFORM_C1E_MODE 0 //C1eModeHardware -//#define BLDCFG_PLATFORM_C1E_OPDATA 0x415 -#define BLDCFG_PLATFORM_CSTATE_MODE CStateModeC6 //0 //CStateModeC6 -//#define BLDCFG_PLATFORM_CSTATE_OPDATA 0x840 //Specifies a free block of 8 consecutive I/O ports to be used to place the CPU into C6 -#define BLDCFG_PLATFORM_CSTATE_IO_BASE_ADDRESS 0x840 //Specifies a free block of 8 consecutive I/O ports to be used to place the CPU into C6 - - -//#define BLDCFG_VRM_NB_CURRENT_LIMIT 0 // Not currently used on Llano/Ontario -#define BLDCFG_VRM_NB_LOW_POWER_THRESHOLD 1 // Zero - disable NBPSI_L, Non-zero - enable NBPSI_L. Default is Zero. -//#define BLDCFG_VRM_NB_SLEW_RATE 5000 // Used in calculating the VSRampSlamTime per BKDG. Defaults to 5000, same as core VRM. Cannot be zero. -//#define BLDCFG_VRM_NB_ADDITIONAL_DELAY 0 // Not currently used on Llano/Ontario -//#define BLDCFG_VRM_NB_HIGH_SPEED_ENABLE 0 // Not currently used on Llano/Ontario -//#define BLDCFG_VRM_NB_INRUSH_CURRENT_LIMIT 0 // Not currently used on Llano/Ontario - -#define BLDCFG_UMA_ABOVE4G_SUPPORT TRUE -#define BLDCFG_STEREO_3D_PINOUT TRUE - -/* Process the options... - * This file include MUST occur AFTER the user option selection settings - */ -CONST AP_MTRR_SETTINGS ROMDATA LlanoApMtrrSettingsList[] = -{ - { AMD_AP_MTRR_FIX64k_00000, 0x1E1E1E1E1E1E1E1Eull }, - { AMD_AP_MTRR_FIX16k_80000, 0x1E1E1E1E1E1E1E1Eull }, - { AMD_AP_MTRR_FIX16k_A0000, 0x0000000000000000ull }, - { AMD_AP_MTRR_FIX4k_C0000, 0x0000000000000000ull }, - { AMD_AP_MTRR_FIX4k_C8000, 0x0000000000000000ull }, - { AMD_AP_MTRR_FIX4k_D0000, 0x0000000000000000ull }, - { AMD_AP_MTRR_FIX4k_D8000, 0x0000000000000000ull }, - { AMD_AP_MTRR_FIX4k_E0000, 0x1818181818181818ull }, - { AMD_AP_MTRR_FIX4k_E8000, 0x1818181818181818ull }, - { AMD_AP_MTRR_FIX4k_F0000, 0x1818181818181818ull }, - { AMD_AP_MTRR_FIX4k_F8000, 0x1818181818181818ull }, - { CPU_LIST_TERMINAL } -}; - -#define BLDCFG_AP_MTRR_SETTINGS_LIST &LlanoApMtrrSettingsList -//#define OPTION_NB_LCLK_DPM_INIT FALSE -//#define OPTION_POWER_GATE FALSE -//#define OPTION_PCIE_POWER_GATE FALSE -//#define OPTION_ALIB FALSE -//#define OPTION_PCIe_MID_INIT FALSE -//#define OPTION_NB_MID_INIT FALSE - -#include "cpuRegisters.h" -#include "cpuFamRegisters.h" -#include "cpuFamilyTranslation.h" -#include "AdvancedApi.h" -#include "heapManager.h" -#include "CreateStruct.h" -#include "cpuFeatures.h" -#include "Table.h" -#include "cpuEarlyInit.h" -#include "cpuLateInit.h" -#include "GnbInterface.h" -#include diff --git a/src/mainboard/amd/torpedo/cmos.layout b/src/mainboard/amd/torpedo/cmos.layout deleted file mode 100644 index f9f52f7546..0000000000 --- a/src/mainboard/amd/torpedo/cmos.layout +++ /dev/null @@ -1,68 +0,0 @@ -#***************************************************************************** -# -# This file is part of the coreboot project. -# -# Copyright (C) 2011 Advanced Micro Devices, Inc. -# -# This program is free software; you can redistribute it and/or modify -# it under the terms of the GNU General Public License as published by -# the Free Software Foundation; version 2 of the License. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -#***************************************************************************** - -entries - -0 384 r 0 reserved_memory -384 1 e 4 boot_option -388 4 h 0 reboot_counter -#392 3 r 0 unused -395 1 e 1 hw_scrubber -396 1 e 1 interleave_chip_selects -397 2 e 8 max_mem_clock -399 1 e 2 multi_core -400 1 e 1 power_on_after_fail -412 4 e 6 debug_level -440 4 e 9 slow_cpu -444 1 e 1 nmi -445 1 e 1 iommu -456 1 e 1 ECC_memory -728 256 h 0 user_data -984 16 h 0 check_sum -# Reserve the extended AMD configuration registers -1000 24 r 0 amd_reserved - - - -enumerations - -#ID value text -1 0 Disable -1 1 Enable -2 0 Enable -2 1 Disable -4 0 Fallback -4 1 Normal -6 5 Notice -6 6 Info -6 7 Debug -6 8 Spew -8 0 400Mhz -8 1 333Mhz -8 2 266Mhz -8 3 200Mhz -9 0 off -9 1 87.5% -9 2 75.0% -9 3 62.5% -9 4 50.0% -9 5 37.5% -9 6 25.0% -9 7 12.5% - -checksums - -checksum 392 983 984 diff --git a/src/mainboard/amd/torpedo/devicetree.cb b/src/mainboard/amd/torpedo/devicetree.cb deleted file mode 100644 index 2adfb27274..0000000000 --- a/src/mainboard/amd/torpedo/devicetree.cb +++ /dev/null @@ -1,85 +0,0 @@ -# -# This file is part of the coreboot project. -# -# Copyright (C) 2011 Advanced Micro Devices, Inc. -# -# This program is free software; you can redistribute it and/or modify -# it under the terms of the GNU General Public License as published by -# the Free Software Foundation; version 2 of the License. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -chip northbridge/amd/agesa/family12/root_complex - device cpu_cluster 0 on - chip cpu/amd/agesa/family12 - device lapic 0 on end - end - end - device domain 0 on - subsystemid 0x1022 0x1705 inherit - chip northbridge/amd/agesa/family12 # CPU side of HT root complex - chip northbridge/amd/agesa/family12 # PCI side of HT root complex - device pci 0.0 on end # Root Complex - device pci 1.0 on end # Internal Graphics Bridge - device pci 1.1 on end # Audio Controller - device pci 2.0 on end # Root Port - device pci 3.0 on end # Root Port - device pci 4.0 on end # PCIE P2P bridge - device pci 5.0 on end # PCIE P2P bridge - device pci 6.0 on end # PCIE P2P bridge - device pci 7.0 on end # PCIE P2P bridge - device pci 8.0 on end # NB/SB Link P2P bridge - end # agesa northbridge - chip southbridge/amd/cimx/sb900 # it is under NB/SB Link, but on the same pri bus - device pci 10.0 on end # USB XHCI - device pci 10.1 on end # USB XHCI - device pci 11.0 on end # SATA - device pci 12.0 on end # USB - device pci 12.2 on end # USB - device pci 13.0 on end # USB - device pci 13.2 on end # USB - device pci 14.0 on # SM - chip drivers/generic/generic #dimm 0-0-0 - device i2c 50 on end - end - chip drivers/generic/generic #dimm 0-0-1 - device i2c 51 on end - end - end # SM - device pci 14.1 on end # IDE - device pci 14.2 on end # HDA - device pci 14.3 on # LPC - chip superio/smsc/kbc1100 - device pnp 2e.7 on # Keyboard - io 0x60 = 0x60 - io 0x62 = 0x64 - irq 0x70 = 1 - irq 0x72 = 12 - end - end # kbc1100 - end #LPC - device pci 14.4 on end # PCI bridge - device pci 14.5 on end # USB 2 - device pci 14.6 on end # Ethernet Controller - device pci 14.7 on end # SD Flash Controller - device pci 15.0 on end # PCIe PortA - device pci 15.1 on end # PCIe PortB - device pci 15.2 on end # PCIe PortC - device pci 15.3 on end # PCIe PortD - register "gpp_configuration" = "4" #1:1:1:1 - register "boot_switch_sata_ide" = "0" # 0: boot from SATA. 1: IDE - end #southbridge/amd/cimx/sb900 - device pci 18.0 on end - device pci 18.1 on end - device pci 18.2 on end - device pci 18.3 on end - device pci 18.4 on end - device pci 18.5 on end - device pci 18.6 on end - device pci 18.7 on end - end #chip northbridge/amd/agesa/family12 # CPU side of HT root complex - end #domain -end #northbridge/amd/agesa/family12/root_complex diff --git a/src/mainboard/amd/torpedo/dsdt.asl b/src/mainboard/amd/torpedo/dsdt.asl deleted file mode 100644 index 48f8e1fe30..0000000000 --- a/src/mainboard/amd/torpedo/dsdt.asl +++ /dev/null @@ -1,1109 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -/* DefinitionBlock Statement */ -#include -DefinitionBlock ( - "DSDT.AML", /* Output filename */ - "DSDT", /* Signature */ - 0x02, /* DSDT Revision, needs to be 2 for 64bit */ - OEM_ID, - ACPI_TABLE_CREATOR, - 0x00010001 /* OEM Revision */ - ) -{ /* Start of ASL file */ - /* #include */ /* Include global debug methods if needed */ - - /* Data to be patched by the BIOS during POST */ - /* FIXME the patching is not done yet! */ - /* Memory related values */ - Name(LOMH, 0x0) /* Start of unused memory in C0000-E0000 range */ - Name(PBAD, 0x0) /* Address of BIOS area (If TOM2 != 0, Addr >> 16) */ - Name(PBLN, 0x0) /* Length of BIOS area */ - - Name(PCBA, 0xE0000000) /* Base address of PCIe config space */ - Name(HPBA, 0xFED00000) /* Base address of HPET table */ - - /* Some global data */ - Name(OSV, Ones) /* Assume nothing */ - Name(GPIC, 0x1) /* Assume PIC */ - - /* - * Processor Object - * - */ - Scope (\_PR) { /* define processor scope */ - Device (C000) { - Name (_HID, "ACPI0007") - Name (_UID, 0) - } - Device (C001) { - Name (_HID, "ACPI0007") - Name (_UID, 1) - } - Device (C002) { - Name (_HID, "ACPI0007") - Name (_UID, 2) - } - Device (C003) { - Name (_HID, "ACPI0007") - Name (_UID, 3) - } - } /* End _PR scope */ - - /* PIC IRQ mapping registers, C00h-C01h. */ - OperationRegion(PIRQ, SystemIO, 0x00000C00, 0x00000002) - Field(PIRQ, ByteAcc, NoLock, Preserve) { - PIDX, 0x00000008, - PDAT, 0x00000008, /* Offset: 1h */ - } - IndexField(PIDX, PDAT, ByteAcc, NoLock, Preserve) { - PIRA, 0x00000008, /* Index 0 */ - PIRB, 0x00000008, /* Index 1 */ - PIRC, 0x00000008, /* Index 2 */ - PIRD, 0x00000008, /* Index 3 */ - PIRE, 0x00000008, /* Index 4 */ - PIRF, 0x00000008, /* Index 5 */ - PIRG, 0x00000008, /* Index 6 */ - PIRH, 0x00000008, /* Index 7 */ - Offset(0x10), - PIRS, 0x00000008, - Offset(0x13), - HDAD, 0x00000008, - , 0x00000008, - GEC, 0x00000008, - Offset(0x30), - USB1, 0x00000008, - USB2, 0x00000008, - USB3, 0x00000008, - USB4, 0x00000008, - USB5, 0x00000008, - USB6, 0x00000008, - USB7, 0x00000008, - Offset(0x40), - IDE, 0x00000008, - SATA, 0x00000008, - Offset(0x50), - GPP0, 0x00000008, - GPP1, 0x00000008, - GPP2, 0x00000008, - GPP3, 0x00000008 - } - - /* PCI Error control register */ - OperationRegion(PERC, SystemIO, 0x00000C14, 0x00000001) - Field(PERC, ByteAcc, NoLock, Preserve) { - SENS, 0x00000001, - PENS, 0x00000001, - SENE, 0x00000001, - PENE, 0x00000001, - } - - /* Client Management index/data registers */ - OperationRegion(CMT, SystemIO, 0x00000C50, 0x00000002) - Field(CMT, ByteAcc, NoLock, Preserve) { - CMTI, 8, - /* Client Management Data register */ - G64E, 1, - G64O, 1, - G32O, 2, - , 2, - GPSL, 2, - } - - /* GPM Port register */ - OperationRegion(GPT, SystemIO, 0x00000C52, 0x00000001) - Field(GPT, ByteAcc, NoLock, Preserve) { - GPB0,1, - GPB1,1, - GPB2,1, - GPB3,1, - GPB4,1, - GPB5,1, - GPB6,1, - GPB7,1, - } - - /* Flash ROM program enable register */ - OperationRegion(FRE, SystemIO, 0x00000C6F, 0x00000001) - Field(FRE, ByteAcc, NoLock, Preserve) { - , 0x00000006, - FLRE, 0x00000001, - } - - /* PM2 index/data registers */ - OperationRegion(PM2R, SystemIO, 0x00000CD0, 0x00000002) - Field(PM2R, ByteAcc, NoLock, Preserve) { - PM2I, 0x00000008, - PM2D, 0x00000008, - } - - /* Power Management I/O registers, TODO:PMIO is quite different in SB900. */ - OperationRegion(PMRG, SystemIO, 0x00000CD6, 0x00000002) - Field(PMRG, ByteAcc, NoLock, Preserve) { - PMRI, 0x00000008, - PMRD, 0x00000008, - } - IndexField (PMRI, PMRD, ByteAcc, NoLock, Preserve) { - Offset(0x24), - MMSO,32, - Offset(0x37), /* GPMLevelConfig0 */ - , 3, - PLC0, 1, - PLC1, 1, - PLC2, 1, - PLC3, 1, - PLC8, 1, - Offset(0x38), /* GPMLevelConfig1 */ - , 1, - PLC4, 1, - PLC5, 1, - , 1, - PLC6, 1, - PLC7, 1, - Offset(0x50), - HPAD,32, - Offset(0x60), - P1EB,16, - Offset(0x65), /* UsbPMControl */ - , 4, - URRE, 1, - Offset(0x96), /* GPM98IN */ - G8IS, 1, - G9IS, 1, - Offset(0x9A), /* EnhanceControl */ - ,7, - HPDE, 1, - Offset(0xC8), - ,2, - SPRE,1, - TPDE,1, - Offset(0xF0), - ,3, - RSTU,1 - } - - /* PM1 Event Block - * First word is PM1_Status, Second word is PM1_Enable - */ - OperationRegion(P1E0, SystemIO, P1EB, 0x04) - Field(P1E0, ByteAcc, NoLock, Preserve) { - ,14, - PEWS,1, - WSTA,1, - ,14, - PEWD,1 - } - - OperationRegion (GRAM, SystemMemory, 0x0400, 0x0100) - Field (GRAM, ByteAcc, Lock, Preserve) - { - Offset (0x10), - FLG0, 8 - } - - Scope(\_SB) { - /* PCIe Configuration Space for 16 busses */ - OperationRegion(PCFG, SystemMemory, PCBA, 0x01000000) /* Each bus consumes 1MB */ - Field(PCFG, ByteAcc, NoLock, Preserve) { - /* Byte offsets are computed using the following technique: - * ((bus number + 1) * ((device number * 8) * 4096)) + register offset - * The 8 comes from 8 functions per device, and 4096 bytes per function config space - */ - Offset(0x00088024), /* Byte offset to SATA register 24h - Bus 0, Device 17, Function 0 */ - STB5, 32, - Offset(0x00098042), /* Byte offset to OHCI0 register 42h - Bus 0, Device 19, Function 0 */ - PT0D, 1, - PT1D, 1, - PT2D, 1, - PT3D, 1, - PT4D, 1, - PT5D, 1, - PT6D, 1, - PT7D, 1, - PT8D, 1, - PT9D, 1, - Offset(0x000A0004), /* Byte offset to SMBUS register 4h - Bus 0, Device 20, Function 0 */ - SBIE, 1, - SBME, 1, - Offset(0x000A0008), /* Byte offset to SMBUS register 8h - Bus 0, Device 20, Function 0 */ - SBRI, 8, - Offset(0x000A0014), /* Byte offset to SMBUS register 14h - Bus 0, Device 20, Function 0 */ - SBB1, 32, - Offset(0x000A0078), /* Byte offset to SMBUS register 78h - Bus 0, Device 20, Function 0 */ - ,14, - P92E, 1, /* Port92 decode enable */ - } - - OperationRegion(SB5, SystemMemory, STB5, 0x1000) - Field(SB5, AnyAcc, NoLock, Preserve){ - /* Port 0 */ - Offset(0x120), /* Port 0 Task file status */ - P0ER, 1, - , 2, - P0DQ, 1, - , 3, - P0BY, 1, - Offset(0x128), /* Port 0 Serial ATA status */ - P0DD, 4, - , 4, - P0IS, 4, - Offset(0x12C), /* Port 0 Serial ATA control */ - P0DI, 4, - Offset(0x130), /* Port 0 Serial ATA error */ - , 16, - P0PR, 1, - - /* Port 1 */ - offset(0x1A0), /* Port 1 Task file status */ - P1ER, 1, - , 2, - P1DQ, 1, - , 3, - P1BY, 1, - Offset(0x1A8), /* Port 1 Serial ATA status */ - P1DD, 4, - , 4, - P1IS, 4, - Offset(0x1AC), /* Port 1 Serial ATA control */ - P1DI, 4, - Offset(0x1B0), /* Port 1 Serial ATA error */ - , 16, - P1PR, 1, - - /* Port 2 */ - Offset(0x220), /* Port 2 Task file status */ - P2ER, 1, - , 2, - P2DQ, 1, - , 3, - P2BY, 1, - Offset(0x228), /* Port 2 Serial ATA status */ - P2DD, 4, - , 4, - P2IS, 4, - Offset(0x22C), /* Port 2 Serial ATA control */ - P2DI, 4, - Offset(0x230), /* Port 2 Serial ATA error */ - , 16, - P2PR, 1, - - /* Port 3 */ - Offset(0x2A0), /* Port 3 Task file status */ - P3ER, 1, - , 2, - P3DQ, 1, - , 3, - P3BY, 1, - Offset(0x2A8), /* Port 3 Serial ATA status */ - P3DD, 4, - , 4, - P3IS, 4, - Offset(0x2AC), /* Port 3 Serial ATA control */ - P3DI, 4, - Offset(0x2B0), /* Port 3 Serial ATA error */ - , 16, - P3PR, 1, - } - } - - - #include "acpi/routing.asl" - - Scope(\_SB) { - - /* Debug Port registers, 80h. */ - OperationRegion(DBBG, SystemIO, 0x00000080, 0x00000001) - Field(DBBG, ByteAcc, NoLock, Preserve) { - DBG8, 0x00000008, - } - - Method(_PIC, 1) { - Store(Arg0, GPIC) - If (GPIC) { - Store(0xAA, \_SB.DBG8) - \_SB.DSPI() - } else { - Store(0xAC, \_SB.DBG8) - } - } - - Method(DSPI, 0) { - \_SB.GRUA(0x1F) - \_SB.GRUB(0x1F) - \_SB.GRUC(0x1F) - \_SB.GRUD(0x1F) - Store(0x1F, PIRE) - Store(0x1F, PIRF) - Store(0x1F, PIRG) - Store(0x1F, PIRH) - } - - Method(GRUA, 1) { - Store(Arg0, PIRA) - Store(Arg0, HDAD) - Store(Arg0, GEC) - Store(Arg0, GPP0) - Store(Arg0, GPP0) - } - - Method(GRUB, 1) { - Store(Arg0, PIRB) - Store(Arg0, USB2) - Store(Arg0, USB4) - Store(Arg0, USB6) - Store(Arg0, GPP1) - Store(Arg0, IDE) - } - - Method(GRUC, 1) { - Store(Arg0, PIRC) - Store(Arg0, USB1) - Store(Arg0, USB3) - Store(Arg0, USB5) - Store(Arg0, USB7) - Store(Arg0, GPP2) - } - - Method(GRUD, 1) { - Store(Arg0, PIRD) - Store(Arg0, SATA) - Store(Arg0, GPP3) - } - - Name(IRQB, ResourceTemplate() { - IRQ(Level, ActiveLow, Shared) { - 15 - }}) - - Name(IRQP, ResourceTemplate() { - IRQ(Level, ActiveLow, Shared) { - 3, 4, 5, 7, 10, 11, 12, 14, 15 - }}) - - Device(INTA) { - Name(_HID, EISAID("PNP0C0F")) - Name(_UID, 1) - Method(_STA, 0) { - if (PIRA) { - Return(0x0B) - } else { - Return(0x09) - } - } - Method(_DIS ,0) { - \_SB.GRUA(0x1F) - } - Method(_PRS ,0) { - Return(IRQP) - } - Method(_CRS ,0) { - CreateWordField(IRQB, 1, IRQN) - ShiftLeft(1, PIRA, IRQN) - Return(IRQB) - } - Method(_SRS, 1) { - CreateWordField(Arg0, 1, IRQM) - FindSetRightBit(IRQM, Local0) - Decrement(Local0) - \_SB.GRUA(Local0) - } - } - - Device(INTB) { - Name(_HID, EISAID("PNP0C0F")) - Name(_UID, 2) - Method(_STA, 0) { - if (PIRB) { - Return(0x0B) - } else { - Return(0x09) - } - } - Method(_DIS ,0) { - \_SB.GRUB(0x1F) - } - Method(_PRS ,0) { - Return(IRQP) - } - Method(_CRS ,0) { - CreateWordField(IRQB, 1, IRQN) - ShiftLeft(1, PIRB, IRQN) - Return(IRQB) - } - Method(_SRS, 1) { - CreateWordField(Arg0, 1, IRQM) - FindSetRightBit(IRQM, Local0) - Decrement(Local0) - \_SB.GRUB(Local0) - } - } - - Device(INTC) { - Name(_HID, EISAID("PNP0C0F")) - Name(_UID, 3) - Method(_STA, 0) { - if (PIRC) { - Return(0x0B) - } else { - Return(0x09) - } - } - Method(_DIS ,0) { - \_SB.GRUC(0x1F) - } - Method(_PRS ,0) { - Return(IRQP) - } - Method(_CRS ,0) { - CreateWordField(IRQB, 1, IRQN) - ShiftLeft(1, PIRC, IRQN) - Return(IRQB) - } - Method(_SRS, 1) { - CreateWordField(Arg0, 1, IRQM) - FindSetRightBit(IRQM, Local0) - Decrement(Local0) - \_SB.GRUC(Local0) - } - } - - Device(INTD) { - Name(_HID, EISAID("PNP0C0F")) - Name(_UID, 4) - Method(_STA, 0) { - if (PIRD) { - Return(0x0B) - } else { - Return(0x09) - } - } - Method(_DIS ,0) { - \_SB.GRUD(0x1F) - } - Method(_PRS ,0) { - Return(IRQP) - } - Method(_CRS ,0) { - CreateWordField(IRQB, 1, IRQN) - ShiftLeft(1, PIRD, IRQN) - Return(IRQB) - } - Method(_SRS, 1) { - CreateWordField(Arg0, 1, IRQM) - FindSetRightBit(IRQM, Local0) - Decrement(Local0) - \_SB.GRUD(Local0) - } - } - - Device(INTE) { - Name(_HID, EISAID("PNP0C0F")) - Name(_UID, 5) - Method(_STA, 0) { - if (PIRE) { - Return(0x0B) - } else { - Return(0x09) - } - } - Method(_DIS ,0) { - Store(0x1F, PIRE) - } - Method(_PRS ,0) { - Return(IRQP) - } - Method(_CRS ,0) { - CreateWordField(IRQB, 1, IRQN) - ShiftLeft(1, PIRE, IRQN) - Return(IRQB) - } - Method(_SRS, 1) { - CreateWordField(Arg0, 1, IRQM) - FindSetRightBit(IRQM, Local0) - Decrement(Local0) - Store(Local0, PIRE) - } - } - - Device(INTF) { - Name(_HID, EISAID("PNP0C0F")) - Name(_UID, 6) - Method(_STA, 0) { - if (PIRF) { - Return(0x0B) - } else { - Return(0x09) - } - } - Method(_DIS ,0) { - Store(0x1F, PIRF) - } - Method(_PRS ,0) { - Return(IRQP) - } - Method(_CRS ,0) { - CreateWordField(IRQB, 1, IRQN) - ShiftLeft(1, PIRF, IRQN) - Return(IRQB) - } - Method(_SRS, 1) { - CreateWordField(Arg0, 1, IRQM) - FindSetRightBit(IRQM, Local0) - Decrement(Local0) - Store(Local0, PIRF) - } - } - - Device(INTG) { - Name(_HID, EISAID("PNP0C0F")) - Name(_UID, 7) - Method(_STA, 0) { - if (PIRG) { - Return(0x0B) - } else { - Return(0x09) - } - } - Method(_DIS ,0) { - Store(0x1F, PIRG) - } - Method(_PRS ,0) { - Return(IRQP) - } - Method(_CRS ,0) { - CreateWordField(IRQB, 1, IRQN) - ShiftLeft(1, PIRG, IRQN) - Return(IRQB) - } - Method(_SRS, 1) { - CreateWordField(Arg0, 1, IRQM) - FindSetRightBit(IRQM, Local0) - Decrement(Local0) - Store(Local0, PIRG) - } - } - - Device(INTH) { - Name(_HID, EISAID("PNP0C0F")) - Name(_UID, 8) - Method(_STA, 0) { - if (PIRH) { - Return(0x0B) - } else { - Return(0x09) - } - } - Method(_DIS ,0) { - Store(0x1F, PIRH) - } - Method(_PRS ,0) { - Return(IRQP) - } - Method(_CRS ,0) { - CreateWordField(IRQB, 1, IRQN) - ShiftLeft(1, PIRH, IRQN) - Return(IRQB) - } - Method(_SRS, 1) { - CreateWordField(Arg0, 1, IRQM) - FindSetRightBit(IRQM, Local0) - Decrement(Local0) - Store(Local0, PIRH) - } - } - } /* End Scope(_SB) */ - - /* Contains the supported sleep states for this chipset */ - #include - - /* Wake status package */ - Name(WKST,Package(){Zero, Zero}) - - /* - * \_PTS - Prepare to Sleep method - * - * Entry: - * Arg0=The value of the sleeping state S1=1, S2=2, etc - * - * Exit: - * -none- - * - * The _PTS control method is executed at the beginning of the sleep process - * for S1-S5. The sleeping value is passed to the _PTS control method. This - * control method may be executed a relatively long time before entering the - * sleep state and the OS may abort the operation without notification to - * the ACPI driver. This method cannot modify the configuration or power - * state of any device in the system. - */ - Method(\_PTS, 1) { - /* DBGO("\\_PTS\n") */ - /* DBGO("From S0 to S") */ - /* DBGO(Arg0) */ - /* DBGO("\n") */ - - /* Don't allow PCIRST# to reset USB */ - if (LEqual(Arg0,3)){ - Store(0,URRE) - } - - /* Clear sleep SMI status flag and enable sleep SMI trap. */ - /*Store(One, CSSM) - Store(One, SSEN)*/ - - /* On older chips, clear PciExpWakeDisEn */ - /*if (LLessEqual(\_SB.SBRI, 0x13)) { - * Store(0,\_SB.PWDE) - *} - */ - - /* Clear wake status structure. */ - Store(0, Index(WKST,0)) - Store(0, Index(WKST,1)) - } /* End Method(\_PTS) */ - - /* - * The following method results in a "not a valid reserved NameSeg" - * warning so I have commented it out for the duration. It isn't - * used, so it could be removed. - * - * - * \_GTS OEM Going To Sleep method - * - * Entry: - * Arg0=The value of the sleeping state S1=1, S2=2 - * - * Exit: - * -none- - * - * Method(\_GTS, 1) { - * DBGO("\\_GTS\n") - * DBGO("From S0 to S") - * DBGO(Arg0) - * DBGO("\n") - * } - */ - - /* - * \_BFS OEM Back From Sleep method - * - * Entry: - * Arg0=The value of the sleeping state S1=1, S2=2 - * - * Exit: - * -none- - */ - Method(\_BFS, 1) { - /* DBGO("\\_BFS\n") */ - /* DBGO("From S") */ - /* DBGO(Arg0) */ - /* DBGO(" to S0\n") */ - } - - /* - * \_WAK System Wake method - * - * Entry: - * Arg0=The value of the sleeping state S1=1, S2=2 - * - * Exit: - * Return package of 2 DWords - * Dword 1 - Status - * 0x00000000 wake succeeded - * 0x00000001 Wake was signaled but failed due to lack of power - * 0x00000002 Wake was signaled but failed due to thermal condition - * Dword 2 - Power Supply state - * if non-zero the effective S-state the power supply entered - */ - Method(\_WAK, 1) { - /* DBGO("\\_WAK\n") */ - /* DBGO("From S") */ - /* DBGO(Arg0) */ - /* DBGO(" to S0\n") */ - - /* Re-enable HPET */ - Store(1,HPDE) - - /* Restore PCIRST# so it resets USB */ - if (LEqual(Arg0,3)){ - Store(1,URRE) - } - - /* Arbitrarily clear PciExpWakeStatus */ - Store(PEWS, Local0) - Store(Local0, PEWS) - - /* if (DeRefOf(Index(WKST,0))) { - * Store(0, Index(WKST,1)) - * } else { - * Store(Arg0, Index(WKST,1)) - * } - */ - Return(WKST) - } /* End Method(\_WAK) */ - - Scope(\_GPE) { /* Start Scope GPE */ - } /* End Scope GPE */ - - /* System Bus */ - Scope(\_SB) { /* Start \_SB scope */ - #include /* global utility methods expected within the \_SB scope */ - - /* Primary (and only) IDE channel */ - Device(IDEC) { - Name(_ADR, 0x00140001) - #include "acpi/ide.asl" - } /* end IDEC */ - - /* _SB.PCI0 */ - /* Note: Only need HID on Primary Bus */ - Device(PCI0) { - External (TOM1) - External (TOM2) - Name(_HID, EISAID("PNP0A03")) - Name(_ADR, 0x00180000) /* Dev# = BSP Dev#, Func# = 0 */ - Method(_BBN, 0) { /* Bus number = 0 */ - Return(0) - } - Method(_STA, 0) { - /* DBGO("\\_SB\\PCI0\\_STA\n") */ - Return(0x0B) /* Status is visible */ - } - Method(_PRT,0) { - If(GPIC){ Return(APR0) } /* APIC mode */ - Return (PR0) /* PIC Mode */ - } /* end _PRT */ - - /* Describe the Northbridge devices */ - Device(AMRT) { - Name(_ADR, 0x00000000) - } /* end AMRT */ - - /* The internal GFX bridge */ - Device(AGPB) { - Name(_ADR, 0x00010000) - Method(_STA,0) { - Return(0x0F) - } - } /* end AGPB */ - - /* The external GFX bridge */ - Device(PBR2) { - Name(_ADR, 0x00020000) - Method(_PRT,0) { - If(GPIC){ Return(APS2) } /* APIC mode */ - Return (PS2) /* PIC Mode */ - } /* end _PRT */ - } /* end PBR2 */ - - /* The external GFX bridge */ - Device(PBR3) { - Name(_ADR, 0x00030000) - Method(_PRT,0) { - If(GPIC){ Return(APS3) } /* APIC mode */ - Return (PS3) /* PIC Mode */ - } /* end _PRT */ - } /* end PBR3 */ - - Device(PBR4) { - Name(_ADR, 0x00040000) - Method(_PRT,0) { - If(GPIC){ Return(APS4) } /* APIC mode */ - Return (PS4) /* PIC Mode */ - } /* end _PRT */ - } /* end PBR4 */ - - Device(PBR5) { - Name(_ADR, 0x00050000) - Method(_PRT,0) { - If(GPIC){ Return(APS5) } /* APIC mode */ - Return (PS5) /* PIC Mode */ - } /* end _PRT */ - } /* end PBR5 */ - - Device(PBR6) { - Name(_ADR, 0x00060000) - Method(_PRT,0) { - If(GPIC){ Return(APS6) } /* APIC mode */ - Return (PS6) /* PIC Mode */ - } /* end _PRT */ - } /* end PBR6 */ - - /* The onboard EtherNet chip */ - Device(PBR7) { - Name(_ADR, 0x00070000) - Method(_PRT,0) { - If(GPIC){ Return(APS7) } /* APIC mode */ - Return (PS7) /* PIC Mode */ - } /* end _PRT */ - } /* end PBR7 */ - - Device(PE20) { - Name(_ADR, 0x00150000) - Method(_PRT,0) { - If(GPIC){ Return(APE0) } /* APIC mode */ - Return (PE0) /* PIC Mode */ - } /* end _PRT */ - } /* end PE20 */ - Device(PE21) { - Name(_ADR, 0x00150001) - Method(_PRT,0) { - If(GPIC){ Return(APE1) } /* APIC mode */ - Return (PE1) /* PIC Mode */ - } /* end _PRT */ - } /* end PE21 */ - Device(PE22) { - Name(_ADR, 0x00150002) - Method(_PRT,0) { - If(GPIC){ Return(APE2) } /* APIC mode */ - Return (APE2) /* PIC Mode */ - } /* end _PRT */ - } /* end PE22 */ - Device(PE23) { - Name(_ADR, 0x00150003) - Method(_PRT,0) { - If(GPIC){ Return(APE3) } /* APIC mode */ - Return (PE3) /* PIC Mode */ - } /* end _PRT */ - } /* end PE23 */ - - /* Describe the Southbridge devices */ - Device(AZHD) { - Name(_ADR, 0x00140002) - OperationRegion(AZPD, PCI_Config, 0x00, 0x100) - Field(AZPD, AnyAcc, NoLock, Preserve) { - offset (0x42), - NSDI, 1, - NSDO, 1, - NSEN, 1, - } - } /* end AZHD */ - - Device(GEC) { - Name(_ADR, 0x00140006) - } /* end GEC */ - - Device(UOH1) { - Name(_ADR, 0x00120000) - #include "acpi/usb.asl" - } /* end UOH1 */ - - Device(UOH3) { - Name(_ADR, 0x00130000) - #include "acpi/usb.asl" - } /* end UOH3 */ - - Device(UOH5) { - Name(_ADR, 0x00160000) - #include "acpi/usb.asl" - } /* end UOH5 */ - - Device(UEH1) { - Name(_ADR, 0x00140005) - #include "acpi/usb.asl" - } /* end UEH1 */ - - Device(UOH2) { - Name(_ADR, 0x00120002) - #include "acpi/usb.asl" - } /* end UOH2 */ - - Device(UOH4) { - Name(_ADR, 0x00130002) - #include "acpi/usb.asl" - } /* end UOH4 */ - - Device(UOH6) { - Name(_ADR, 0x00160002) - #include "acpi/usb.asl" - } /* end UOH5 */ - - Device(XHC0) { - Name(_ADR, 0x00100000) - #include "acpi/usb.asl" - } /* end XHC0 */ - - Device(XHC1) { - Name(_ADR, 0x00100001) - #include "acpi/usb.asl" - } /* end XHC1 */ - - Device(SBUS) { - Name(_ADR, 0x00140000) - } /* end SBUS */ - - Device(LIBR) { - Name(_ADR, 0x00140003) - /* Real Time Clock Device */ - Device(RTC0) { - Name(_HID, EISAID("PNP0B00")) /* AT Real Time Clock (not PIIX4 compatible) */ - Name(_CRS, ResourceTemplate() { - IRQNoFlags(){8} - IO(Decode16,0x0070, 0x0070, 0, 2) - /* IO(Decode16,0x0070, 0x0070, 0, 4) */ - }) - } /* End Device(_SB.PCI0.LpcIsaBr.RTC0) */ - - Device(TMR) { /* Timer */ - Name(_HID,EISAID("PNP0100")) /* System Timer */ - Name(_CRS, ResourceTemplate() { - IRQNoFlags(){0} - IO(Decode16, 0x0040, 0x0040, 0, 4) - /* IO(Decode16, 0x0048, 0x0048, 0, 4) */ - }) - } /* End Device(_SB.PCI0.LpcIsaBr.TMR) */ - - Device(SPKR) { /* Speaker */ - Name(_HID,EISAID("PNP0800")) /* AT style speaker */ - Name(_CRS, ResourceTemplate() { - IO(Decode16, 0x0061, 0x0061, 0, 1) - }) - } /* End Device(_SB.PCI0.LpcIsaBr.SPKR) */ - - Device(PIC) { - Name(_HID,EISAID("PNP0000")) /* AT Interrupt Controller */ - Name(_CRS, ResourceTemplate() { - IRQNoFlags(){2} - IO(Decode16,0x0020, 0x0020, 0, 2) - IO(Decode16,0x00A0, 0x00A0, 0, 2) - /* IO(Decode16, 0x00D0, 0x00D0, 0x10, 0x02) */ - /* IO(Decode16, 0x04D0, 0x04D0, 0x10, 0x02) */ - }) - } /* End Device(_SB.PCI0.LpcIsaBr.PIC) */ - - Device(MAD) { /* 8257 DMA */ - Name(_HID,EISAID("PNP0200")) /* Hardware Device ID */ - Name(_CRS, ResourceTemplate() { - DMA(Compatibility,BusMaster,Transfer8){4} - IO(Decode16, 0x0000, 0x0000, 0x10, 0x10) - IO(Decode16, 0x0081, 0x0081, 0x01, 0x03) - IO(Decode16, 0x0087, 0x0087, 0x01, 0x01) - IO(Decode16, 0x0089, 0x0089, 0x01, 0x03) - IO(Decode16, 0x008F, 0x008F, 0x01, 0x01) - IO(Decode16, 0x00C0, 0x00C0, 0x10, 0x20) - }) /* End Name(_SB.PCI0.LpcIsaBr.MAD._CRS) */ - } /* End Device(_SB.PCI0.LpcIsaBr.MAD) */ - - Device(COPR) { - Name(_HID,EISAID("PNP0C04")) /* Math Coprocessor */ - Name(_CRS, ResourceTemplate() { - IO(Decode16, 0x00F0, 0x00F0, 0, 0x10) - IRQNoFlags(){13} - }) - } /* End Device(_SB.PCI0.LpcIsaBr.COPR) */ -#if 0 - Device(HPTM) { - Name(_HID,EISAID("PNP0103")) - Name(CRS,ResourceTemplate() { - Memory32Fixed(ReadOnly,0xFED00000, 0x00000400, HPT) /* 1kb reserved space */ - }) - Method(_STA, 0) { - Return(0x0F) /* sata is visible */ - } - Method(_CRS, 0) { - CreateDwordField(CRS, ^HPT._BAS, HPBX) - Store(HPBA, HPBX) - Return(CRS) - } - } /* End Device(_SB.PCI0.LpcIsaBr.COPR) */ -#endif - Device (PS2M) { - Name (_HID, EisaId ("PNP0F13")) - Name (_CRS, ResourceTemplate () { - IRQNoFlags () {12} - }) - Method (_STA, 0, NotSerialized) { - And (FLG0, 0x04, Local0) - If (LEqual (Local0, 0x04)) { - Return (0x0F) - } Else { - Return (0x00) - } - } - } - - Device (PS2K) { - Name (_HID, EisaId ("PNP0303")) - Name (_CRS, ResourceTemplate () { - IO (Decode16, 0x0060, 0x0060, 0x01, 0x01) - IO (Decode16, 0x0064, 0x0064, 0x01, 0x01) - IRQNoFlags () {1} - }) - } - } /* end LIBR */ - - Device(STCR) { - Name(_ADR, 0x00110000) - #include "acpi/sata.asl" - } /* end STCR */ - - /* Primary (and only) IDE channel */ - Device(IDEC) { - Name(_ADR, 0x00140001) - #include "acpi/ide.asl" - } /* end IDEC */ - - Name(CRES, ResourceTemplate() { - IO(Decode16, 0x0CF8, 0x0CF8, 1, 8) - - WORDIO(ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, - 0x0000, /* address granularity */ - 0x0000, /* range minimum */ - 0x0CF7, /* range maximum */ - 0x0000, /* translation */ - 0x0CF8 /* length */ - ) - - WORDIO(ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, - 0x0000, /* address granularity */ - 0x0D00, /* range minimum */ - 0xFFFF, /* range maximum */ - 0x0000, /* translation */ - 0xF300 /* length */ - ) - - /* memory space for PCI BARs below 4GB */ - Memory32Fixed(ReadOnly, 0x00000000, 0x00000000, MMIO) - }) /* End Name(_SB.PCI0.CRES) */ - - Method(_CRS, 0) { - /* DBGO("\\_SB\\PCI0\\_CRS\n") */ - CreateDWordField(CRES, ^MMIO._BAS, MM1B) - CreateDWordField(CRES, ^MMIO._LEN, MM1L) - /* - * Declare memory between TOM1 and 4GB as available - * for PCI MMIO. - * Use ShiftLeft to avoid 64bit constant (for XP). - * This will work even if the OS does 32bit arithmetic, as - * 32bit (0x00000000 - TOM1) will wrap and give the same - * result as 64bit (0x100000000 - TOM1). - */ - Store(TOM1, MM1B) - ShiftLeft(0x10000000, 4, Local0) - Subtract(Local0, TOM1, Local0) - Store(Local0, MM1L) - - Return(CRES) /* note to change the Name buffer */ - } /* end of Method(_SB.PCI0._CRS) */ - } /* End Device(PCI0) */ - - Device(PWRB) { /* Start Power button device */ - Name(_HID, EISAID("PNP0C0C")) - Name(_UID, 0xAA) - Name(_STA, 0x0B) /* sata is invisible */ - } - } /* End \_SB scope */ -} -/* End of ASL file */ diff --git a/src/mainboard/amd/torpedo/fadt.c b/src/mainboard/amd/torpedo/fadt.c deleted file mode 100644 index 08763bd82a..0000000000 --- a/src/mainboard/amd/torpedo/fadt.c +++ /dev/null @@ -1,213 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - - -/* - * ACPI - create the Fixed ACPI Description Tables (FADT) - */ - -#include -#include -#include -#include -#include -#include -#include - -/*extern*/ u16 pm_base = 0x800; -/* pm_base should be set in sb ACPI */ -/* pm_base should be got from bar2 of sb900. Here I compact ACPI - * registers into 32 bytes limit. - * */ - -#define ACPI_PM_EVT_BLK (pm_base + 0x00) /* 4 bytes */ -#define ACPI_PM1_CNT_BLK (pm_base + 0x04) /* 2 bytes */ -#define ACPI_PM2_CNT_BLK (pm_base + 0x0F) /* 1 byte */ -#define ACPI_PM_TMR_BLK (pm_base + 0x08) /* 4 bytes */ -#define ACPI_GPE0_BLK (pm_base + 0x20) /* 8 bytes */ -#define ACPI_CPU_CONTORL (pm_base + 0x10) /* 6 bytes */ -void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt) -{ - u16 val = 0; - acpi_header_t *header = &(fadt->header); - - pm_base &= 0xFFFF; - printk(BIOS_DEBUG, "pm_base: 0x%04x\n", pm_base); - - /* Prepare the header */ - memset((void *)fadt, 0, sizeof(acpi_fadt_t)); - memcpy(header->signature, "FACP", 4); - header->length = sizeof(acpi_fadt_t); - header->revision = ACPI_FADT_REV_ACPI_1_0; - memcpy(header->oem_id, OEM_ID, 6); - memcpy(header->oem_table_id, ACPI_TABLE_CREATOR, 8); - memcpy(header->asl_compiler_id, ASLC, 4); - header->asl_compiler_revision = asl_revision; - - if ((uintptr_t)facs > 0xffffffff) - printk(BIOS_DEBUG, "ACPI: FACS lives above 4G\n"); - else - fadt->firmware_ctrl = (uintptr_t)facs; - - if ((uintptr_t)dsdt > 0xffffffff) - printk(BIOS_DEBUG, "ACPI: DSDT lives above 4G\n"); - else - fadt->dsdt = (uintptr_t)dsdt; - - /* 3 = Workstation, 4 = Enterprise Server, 7 = Performance Server */ - fadt->preferred_pm_profile = 0x03; - fadt->sci_int = 9; - /* disable system management mode by setting to 0: */ - fadt->smi_cmd = 0; - fadt->acpi_enable = 0xf0; - fadt->acpi_disable = 0xf1; - fadt->s4bios_req = 0x0; - fadt->pstate_cnt = 0xe2; - - val = PM1_EVT_BLK_ADDRESS; - WritePMIO(SB_PMIOA_REG60, AccWidthUint16, &val); - val = PM1_CNT_BLK_ADDRESS; - WritePMIO(SB_PMIOA_REG62, AccWidthUint16, &val); - val = PM1_TMR_BLK_ADDRESS; - WritePMIO(SB_PMIOA_REG64, AccWidthUint16, &val); - val = GPE0_BLK_ADDRESS; - WritePMIO(SB_PMIOA_REG68, AccWidthUint16, &val); - - /* CpuControl is in \_PR.CP00, 6 bytes */ - val = CPU_CNT_BLK_ADDRESS; - WritePMIO(SB_PMIOA_REG66, AccWidthUint16, &val); - val = 0; - WritePMIO(SB_PMIOA_REG6A, AccWidthUint16, &val); - - val = ACPI_PM2_CNT_BLK; - WritePMIO(SB_PMIOA_REG6E, AccWidthUint16, &val); - - /* AcpiDecodeEnable, When set, SB uses the contents of the - * PM registers at index 60-6B to decode ACPI I/O address. - * AcpiSmiEn & SmiCmdEn */ - val = BIT0 | BIT1 | BIT2 | BIT4; - WritePMIO(SB_PMIOA_REG74, AccWidthUint16, &val); - - /* RTC_En_En, TMR_En_En, GBL_EN_EN */ - outl(0x1, ACPI_PM1_CNT_BLK); /* set SCI_EN */ - fadt->pm1a_evt_blk = ACPI_PM_EVT_BLK; - fadt->pm1b_evt_blk = 0x0000; - fadt->pm1a_cnt_blk = ACPI_PM1_CNT_BLK; - fadt->pm1b_cnt_blk = 0x0000; - fadt->pm2_cnt_blk = ACPI_PM2_CNT_BLK; - fadt->pm_tmr_blk = ACPI_PM_TMR_BLK; - fadt->gpe0_blk = ACPI_GPE0_BLK; - fadt->gpe1_blk = 0x0000; /* we dont have gpe1 block, do we? */ - - fadt->pm1_evt_len = 4; - fadt->pm1_cnt_len = 2; - fadt->pm2_cnt_len = 1; - fadt->pm_tmr_len = 4; - fadt->gpe0_blk_len = 8; - fadt->gpe1_blk_len = 0; - fadt->gpe1_base = 0; - - fadt->cst_cnt = 0xe3; - fadt->p_lvl2_lat = 101; - fadt->p_lvl3_lat = 1001; - fadt->flush_size = 0; - fadt->flush_stride = 0; - fadt->duty_offset = 1; - fadt->duty_width = 3; - fadt->day_alrm = 0; /* 0x7d these have to be */ - fadt->mon_alrm = 0; /* 0x7e added to cmos.layout */ - fadt->century = 0; /* 0x7f to make rtc alrm work */ - fadt->iapc_boot_arch = 0x3; /* See table 5-11 */ - fadt->flags = 0x0001c1a5;/* 0x25; */ - - fadt->res2 = 0; - - fadt->reset_reg.space_id = 1; - fadt->reset_reg.bit_width = 8; - fadt->reset_reg.bit_offset = 0; - fadt->reset_reg.access_size = 0; - fadt->reset_reg.addrl = 0xcf9; - fadt->reset_reg.addrh = 0x0; - - fadt->reset_value = 6; - fadt->x_firmware_ctl_l = ((uintptr_t)facs) & 0xffffffff; - fadt->x_firmware_ctl_h = ((uint64_t)(uintptr_t)facs) >> 32; - fadt->x_dsdt_l = ((uintptr_t)dsdt) & 0xffffffff; - fadt->x_dsdt_h = ((uint64_t)(uintptr_t)dsdt) >> 32; - - fadt->x_pm1a_evt_blk.space_id = 1; - fadt->x_pm1a_evt_blk.bit_width = 32; - fadt->x_pm1a_evt_blk.bit_offset = 0; - fadt->x_pm1a_evt_blk.access_size = 0; - fadt->x_pm1a_evt_blk.addrl = ACPI_PM_EVT_BLK; - fadt->x_pm1a_evt_blk.addrh = 0x0; - - fadt->x_pm1b_evt_blk.space_id = 1; - fadt->x_pm1b_evt_blk.bit_width = 4; - fadt->x_pm1b_evt_blk.bit_offset = 0; - fadt->x_pm1b_evt_blk.access_size = 0; - fadt->x_pm1b_evt_blk.addrl = 0x0; - fadt->x_pm1b_evt_blk.addrh = 0x0; - - - fadt->x_pm1a_cnt_blk.space_id = 1; - fadt->x_pm1a_cnt_blk.bit_width = 16; - fadt->x_pm1a_cnt_blk.bit_offset = 0; - fadt->x_pm1a_cnt_blk.access_size = 0; - fadt->x_pm1a_cnt_blk.addrl = ACPI_PM1_CNT_BLK; - fadt->x_pm1a_cnt_blk.addrh = 0x0; - - fadt->x_pm1b_cnt_blk.space_id = 1; - fadt->x_pm1b_cnt_blk.bit_width = 2; - fadt->x_pm1b_cnt_blk.bit_offset = 0; - fadt->x_pm1b_cnt_blk.access_size = 0; - fadt->x_pm1b_cnt_blk.addrl = 0x0; - fadt->x_pm1b_cnt_blk.addrh = 0x0; - - - fadt->x_pm2_cnt_blk.space_id = 1; - fadt->x_pm2_cnt_blk.bit_width = 0; - fadt->x_pm2_cnt_blk.bit_offset = 0; - fadt->x_pm2_cnt_blk.access_size = 0; - fadt->x_pm2_cnt_blk.addrl = ACPI_PM2_CNT_BLK; - fadt->x_pm2_cnt_blk.addrh = 0x0; - - - fadt->x_pm_tmr_blk.space_id = 1; - fadt->x_pm_tmr_blk.bit_width = 32; - fadt->x_pm_tmr_blk.bit_offset = 0; - fadt->x_pm_tmr_blk.access_size = 0; - fadt->x_pm_tmr_blk.addrl = ACPI_PM_TMR_BLK; - fadt->x_pm_tmr_blk.addrh = 0x0; - - - fadt->x_gpe0_blk.space_id = 1; - fadt->x_gpe0_blk.bit_width = 32; - fadt->x_gpe0_blk.bit_offset = 0; - fadt->x_gpe0_blk.access_size = 0; - fadt->x_gpe0_blk.addrl = ACPI_GPE0_BLK; - fadt->x_gpe0_blk.addrh = 0x0; - - - fadt->x_gpe1_blk.space_id = 1; - fadt->x_gpe1_blk.bit_width = 0; - fadt->x_gpe1_blk.bit_offset = 0; - fadt->x_gpe1_blk.access_size = 0; - fadt->x_gpe1_blk.addrl = 0; - fadt->x_gpe1_blk.addrh = 0x0; - - header->checksum = acpi_checksum((void *)fadt, sizeof(acpi_fadt_t)); - -} diff --git a/src/mainboard/amd/torpedo/gpio.c b/src/mainboard/amd/torpedo/gpio.c deleted file mode 100644 index 51e35713ea..0000000000 --- a/src/mainboard/amd/torpedo/gpio.c +++ /dev/null @@ -1,441 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include "gpio.h" -#include - - -#ifndef SB_GPIO_REG01 -#define SB_GPIO_REG01 1 -#endif - -#ifndef SB_GPIO_REG07 -#define SB_GPIO_REG07 7 -#endif - -#ifndef SB_GPIO_REG25 -#define SB_GPIO_REG25 25 -#endif - -#ifndef SB_GPIO_REG26 -#define SB_GPIO_REG26 26 -#endif - -#ifndef SB_GPIO_REG27 -#define SB_GPIO_REG27 27 -#endif - -void gpioEarlyInit(void) { - u8 Flags; - u8 Data8 = 0; - u8 StripInfo = 0; - u8 BoardType = 1; - u8 RegIndex8 = 0; - u8 boardRevC = 0x2; - u16 Data16 = 0; - u32 Index = 0; - u32 AcpiMmioAddr = 0; - u32 GpioMmioAddr = 0; - u32 IoMuxMmioAddr = 0; - u32 MiscMmioAddr = 0; - u32 SmiMmioAddr = 0; - u32 andMask32 = 0; - - // Enable HUDSON MMIO Base (AcpiMmioAddr) - ReadPMIO (SB_PMIOA_REG24, AccWidthUint8, &Data8); - Data8 |= BIT0; - WritePMIO (SB_PMIOA_REG24, AccWidthUint8, &Data8); - // Get HUDSON MMIO Base (AcpiMmioAddr) - ReadPMIO (SB_PMIOA_REG24 + 3, AccWidthUint8, &Data8); - Data16 = Data8 << 8; - ReadPMIO (SB_PMIOA_REG24 + 2, AccWidthUint8, &Data8); - Data16 |= Data8; - AcpiMmioAddr = (u32)Data16 << 16; - GpioMmioAddr = AcpiMmioAddr + GPIO_BASE; - IoMuxMmioAddr = AcpiMmioAddr + IOMUX_BASE; - MiscMmioAddr = AcpiMmioAddr + MISC_BASE; - Data8 = Mmio8_G (MiscMmioAddr, SB_MISC_REG80); - if ((Data8 & BIT4) == 0) { - BoardType = 0; // external clock board - } - Data8 = Mmio8_G (GpioMmioAddr, GPIO_30); - StripInfo = (Data8 & BIT7) >> 7; - Data8 = Mmio8_G (GpioMmioAddr, GPIO_31); - StripInfo |= (Data8 & BIT7) >> 6; - if (StripInfo < boardRevC) { // for old board. Rev B - Mmio8_And_Or (IoMuxMmioAddr, GPIO_111, 0x00, 3); // function 3 - Mmio8_And_Or (IoMuxMmioAddr, GPIO_113, 0x00, 0); // function 0 - } - for (Index = 0; Index < MAX_GPIO_NO; Index++) { - if (!(((Index >= GPIO_RSVD_ZONE0_S) && (Index <= GPIO_RSVD_ZONE0_E)) || ((Index >= GPIO_RSVD_ZONE1_S) && (Index <= GPIO_RSVD_ZONE1_E)))) { - if ((StripInfo >= boardRevC) || ((Index != GPIO_111) && (Index != GPIO_113))) { - // Configure multi-function - Mmio8_And_Or (IoMuxMmioAddr, Index, 0x00, (gpio_table[Index].select & ~NonGpio)); - } - // Configure GPIO - if(!((gpio_table[Index].NonGpioGevent & NonGpio))) { - Mmio8_And_Or (GpioMmioAddr, Index, 0xDF, gpio_table[Index].type); - Mmio8_And_Or (GpioMmioAddr, Index, 0xA3, gpio_table[Index].value); - } - if (Index == GPIO_65) { - if (BoardType == 0) { - Mmio8_And_Or (IoMuxMmioAddr, GPIO_65, 0x00, 3); // function 3 - } - } - } - // Configure GEVENT - if ((Index >= GEVENT_00) && (Index <= GEVENT_23) && ((gevent_table[Index - GEVENT_00].EventEnable))) { - SmiMmioAddr = AcpiMmioAddr + SMI_BASE; - - andMask32 = ~(1 << (Index - GEVENT_00)); - - //EventEnable: 0-Disable, 1-Enable - Mmio32_And_Or(SmiMmioAddr, SMIREG_EVENT_ENABLE, andMask32, (gevent_table[Index - GEVENT_00].EventEnable << (Index - GEVENT_00))); - - //SciTrig: 0-Falling Edge, 1-Rising Edge - Mmio32_And_Or(SmiMmioAddr, SMIREG_SCITRIG, andMask32, (gevent_table[Index - GEVENT_00].SciTrig << (Index - GEVENT_00))); - - //SciLevl: 0-Edge trigger, 1-Level Trigger - Mmio32_And_Or(SmiMmioAddr, SMIREG_SCILEVEL, andMask32, (gevent_table[Index - GEVENT_00].SciLevl << (Index - GEVENT_00))); - - //SmiSciEn: 0-Not send SMI, 1-Send SMI - Mmio32_And_Or(SmiMmioAddr, SMIREG_SMISCIEN, andMask32, (gevent_table[Index - GEVENT_00].SmiSciEn << (Index - GEVENT_00))); - - //SciS0En: 0-Disable, 1-Enable - Mmio32_And_Or(SmiMmioAddr, SMIREG_SCIS0EN, andMask32, (gevent_table[Index - GEVENT_00].SciS0En << (Index - GEVENT_00))); - - //SciMap: 00000b ~ 11111b - RegIndex8 = (u8)((Index - GEVENT_00) >> 2); - Data8 = (u8)(((Index - GEVENT_00) & 0x3) * 8); - Mmio32_And_Or(SmiMmioAddr, SMIREG_SCIMAP0+RegIndex8, ~(GEVENT_SCIMASK << Data8), (gevent_table[Index - GEVENT_00].SciMap << Data8)); - - //SmiTrig: 0-Active Low, 1-Active High - Mmio32_And_Or(SmiMmioAddr, SMIREG_SMITRIG, ~(gevent_table[Index - GEVENT_00].SmiTrig << (Index - GEVENT_00)), (gevent_table[Index - GEVENT_00].SmiTrig << (Index - GEVENT_00))); - - //SmiControl: 0-Disable, 1-SMI, 2-NMI, 3-IRQ13 - RegIndex8 = (u8)((Index - GEVENT_00) >> 4); - Data8 = (u8)(((Index - GEVENT_00) & 0xF) * 2); - Mmio32_And_Or(SmiMmioAddr, SMIREG_SMICONTROL0+RegIndex8, ~(SMICONTROL_MASK << Data8), (gevent_table[Index - GEVENT_00].SmiControl << Data8)); - } - } - - // - // config MXM - // GPIO9: Input for MXM_PRESENT2# - // GPIO10: Input for MXM_PRESENT1# - // GPIO28: Input for MXM_PWRGD - // GPIO35: Output for MXM Reset - // GPIO45: Output for MXM Power Enable, active HIGH - // GPIO55: Output for MXM_PWR_EN, 1 - Enable, 0 - Disable - // GPIO32: Output for PCIE_SW, 1 - MXM, 0 - LASSO - // - // set INTE#/GPIO32 as GPO for PCIE_SW - RWMEM (IoMuxMmioAddr + SB_GPIO_REG32, AccWidthUint8, 00, 0x1); // GPIO - RWMEM (GpioMmioAddr + SB_GPIO_REG32, AccWidthUint8, 0x03, 0); // GPO - RWMEM (GpioMmioAddr + SB_GPIO_REG32, AccWidthUint8, 0x23, BIT3+BIT6); - - // set SATA_IS4#/FANOUT3/GPIO55 as GPO for MXM_PWR_EN - RWMEM (IoMuxMmioAddr + SB_GPIO_REG55, AccWidthUint8, 00, 0x2); // GPIO - RWMEM (GpioMmioAddr + SB_GPIO_REG55, AccWidthUint8, 0x03, 0); // GPO - - // set AD9/GPIO9 as GPI for MXM_PRESENT2# - RWMEM (IoMuxMmioAddr + SB_GPIO_REG09, AccWidthUint8, 00, 0x1); // GPIO - RWMEM (GpioMmioAddr + SB_GPIO_REG09, AccWidthUint8, 0x03, BIT5); // GPI - - // set AD10/GPIO10 as GPI for MXM_PRESENT1# - RWMEM (IoMuxMmioAddr + SB_GPIO_REG10, AccWidthUint8, 00, 0x1); // GPIO - RWMEM (GpioMmioAddr + SB_GPIO_REG10, AccWidthUint8, 0x03, BIT5); // GPI - - // set GNT1#/GPIO44 as GPO for MXM Reset - RWMEM (IoMuxMmioAddr + SB_GPIO_REG44, AccWidthUint8, 00, 0x1); // GPIO - RWMEM (GpioMmioAddr + SB_GPIO_REG44, AccWidthUint8, 0x03, 0); // GPO - - // set GNT2#/SD_LED/GPO45 as GPO for MXM Power Enable - RWMEM (IoMuxMmioAddr + SB_GPIO_REG45, AccWidthUint8, 00, 0x2); // GPIO - RWMEM (GpioMmioAddr + SB_GPIO_REG45, AccWidthUint8, 0x03, 0); // GPO - - // set AD28/GPIO28 as GPI for MXM_PWRGD - RWMEM (IoMuxMmioAddr + SB_GPIO_REG28, AccWidthUint8, 00, 0x1); // GPIO - RWMEM (GpioMmioAddr + SB_GPIO_REG28, AccWidthUint8, 0x03, BIT5); // GPI - - // set BIT3 = 1 (PULLUP disable), BIT4 = 0 (PULLDOWN Disable), BIT6 = 0 (Output LOW) - RWMEM (GpioMmioAddr + SB_GPIO_REG55, AccWidthUint8, 0x23, BIT3); - RWMEM (GpioMmioAddr + SB_GPIO_REG09, AccWidthUint8, 0x23, BIT3); - RWMEM (GpioMmioAddr + SB_GPIO_REG10, AccWidthUint8, 0x23, BIT3); - RWMEM (GpioMmioAddr + SB_GPIO_REG44, AccWidthUint8, 0x23, BIT3); - RWMEM (GpioMmioAddr + SB_GPIO_REG45, AccWidthUint8, 0x23, BIT3); - RWMEM (GpioMmioAddr + SB_GPIO_REG28, AccWidthUint8, 0x23, BIT3); - - // - // [GPIO] STRP_DATA: 1->RS880M VCC_NB 1.0V. 0->RS880M VCC_NB 1.1V (Default). - // - //Fusion_Llano BLWriteNBMISC_Dword (ATI_MISC_REG42, (BLReadNBMISC_Dword (ATI_MISC_REG42) | BIT20)); - //Fusion_Llano BLWriteNBMISC_Dword (ATI_MISC_REG40, (BLReadNBMISC_Dword (ATI_MISC_REG40) & (~BIT20))); - - // check if there any GFX card - Flags = 0; - // Value32 = MmPci32 (0, SB_ISA_BUS, SB_ISA_DEV, SB_ISA_FUNC, R_SB_ISA_GPIO_CONTROL); - // Data8 = Mmio8 (GpioMmioAddr, SB_GPIO_REG09); - ReadMEM (GpioMmioAddr + SB_GPIO_REG09, AccWidthUint8, &Data8); - if (!(Data8 & BIT7)) - { - //Data8 = Mmio8 (GpioMmioAddr, SB_GPIO_REG10); - ReadMEM (GpioMmioAddr + SB_GPIO_REG10, AccWidthUint8, &Data8); - if (!(Data8 & BIT7)) - { - Flags = 1; - } - } - if (Flags) - { - // [GPIO] GPIO44: PE_GPIO0 MXM Reset set to 0 for reset, ENH164467 - RWMEM (GpioMmioAddr + SB_GPIO_REG44, AccWidthUint8, 0xBF, 0); - - // [GPIO] GPIO45: PE_GPIO1 MXM_POWER_ENABLE, SET HIGH - RWMEM (GpioMmioAddr + SB_GPIO_REG45, AccWidthUint8, 0xFF, BIT6); - - //PeiStall (PeiServices, NULL, 100); //delay 100 ms (should be >1ms) - SbStall (10000); - - // Write the GPIO55(MXM_PWR_EN) to enable the integrated power module - RWMEM (GpioMmioAddr + SB_GPIO_REG55, AccWidthUint8, 0xFF, BIT6); - - //PeiStall (PeiServices, NULL, 100); //delay 100 ms (should be >1ms) - // WAIT POWER READY: GPIO28 (MXM_PWRGD) - //while (!(Mmio8 (GpioMmioAddr, SB_GPIO_REG28) && BIT7)){} - ReadMEM (GpioMmioAddr + SB_GPIO_REG28, AccWidthUint8, &Data8); - while (!(Data8 & BIT7)) - { - ReadMEM (GpioMmioAddr + SB_GPIO_REG28, AccWidthUint8, &Data8); - } - // [GPIO] GPIO44: PE_GPIO0 MXM Reset set to 1 for reset - //RWMEM (GpioMmioAddr + SB_GPIO_REG44, AccWidthUint8, 0xBF, BIT6); - } - else - { - // Write the GPIO55(MXM_PWR_EN) to disable the integrated power module - RWMEM (GpioMmioAddr + SB_GPIO_REG55, AccWidthUint8, 0xBF, 0); - - //PeiStall (PeiServices, NULL, 100); //delay 100 ms (should be >1ms) - SbStall (10000); - - // [GPIO] GPIO45: PE_GPIO1 MXM_POWER_ENABLE down - RWMEM (GpioMmioAddr + SB_GPIO_REG45, AccWidthUint8, 0xBF, 0); - } - - // - // APU GPP0: On board LAN - // GPIO25: PCIE_RST#_LAN, LOW active - // GPIO63: LAN_CLKREQ# - // GPIO197: LOM_POWER, HIGH Active - // Clock: GPP_CLK3 - // - // Set EC_PWM0/EC_TIMER0/GPIO197 as GPO for LOM_POWER - RWMEM (IoMuxMmioAddr + SB_GPIO_REG197, AccWidthUint8, 00, 0x2); // GPIO -// RWMEM (GpioMmioAddr + SB_GPIO_REG197, AccWidthUint8, 0x03, 0); // GPO - RWMEM (GpioMmioAddr + SB_GPIO_REG197, AccWidthUint8, 0x03, BIT6); // output HIGH - RWMEM (GpioMmioAddr + SB_GPIO_REG197, AccWidthUint8, 0x63, BIT3); // pullup DISABLE - - // Setup AD25/GPIO25 as GPO for PCIE_RST#_LAN: - RWMEM (IoMuxMmioAddr + SB_GPIO_REG25, AccWidthUint8, 00, 0x1); // GPIO -// RWMEM (GpioMmioAddr + SB_GPIO_REG25, AccWidthUint8, 0x03, 0); // GPO - RWMEM (GpioMmioAddr + SB_GPIO_REG25, AccWidthUint8, 0x03, BIT6); // output HIGH - RWMEM (GpioMmioAddr + SB_GPIO_REG25, AccWidthUint8, 0x63, BIT3); // pullup DISABLE - - - // set CLK_REQ3#/SATA_IS1#/GPIO63 as CLK_REQ for LAN_CLKREQ# - RWMEM (IoMuxMmioAddr + SB_GPIO_REG63, AccWidthUint8, 00, 0x0); // CLK_REQ3# - RWMEM (MiscMmioAddr + SB_MISC_REG00+1, AccWidthUint8, 0x0F, 0xF0); // Enable GPP_CLK3 - - // - // APU GPP1: WUSB - // GPIO1: MPCIE_RST2#, LOW active - // GPIO13: WU_DISABLE#, LOW active - // GPIO177: MPICE_PD2, 1 - DISABLE, 0 - ENABLE (Default) - // - // Setup VIN2/SATA1_1/GPIO177 as GPO for MPCIE_PD2#: wireless disable - RWMEM (IoMuxMmioAddr + SB_GPIO_REG177, AccWidthUint8, 00, 0x2); // GPIO -// RWMEM (GpioMmioAddr + SB_GPIO_REG177, AccWidthUint8, 0x03, 0); // GPO - RWMEM (GpioMmioAddr + SB_GPIO_REG177, AccWidthUint8, 0x03, 0); // output LOW - RWMEM (GpioMmioAddr + SB_GPIO_REG177, AccWidthUint8, 0x63, BIT3); // pullup DISABLE - - // Setup AD01/GPIO01 as GPO for MPCIE_RST2# - RWMEM (IoMuxMmioAddr + SB_GPIO_REG01, AccWidthUint8, 00, 0x1); // GPIO -// RWMEM (GpioMmioAddr + SB_GPIO_REG01, AccWidthUint8, 0x03, 0); // GPO - RWMEM (GpioMmioAddr + SB_GPIO_REG01, AccWidthUint8, 0x03, BIT6); // output LOW - RWMEM (GpioMmioAddr + SB_GPIO_REG01, AccWidthUint8, 0x63, BIT3); // pullup DISABLE - - // Setup AD13/GPIO13 as GPO for WU_DISABLE#: disable WUSB -// RWMEM (IoMuxMmioAddr + SB_GPIO_REG13, AccWidthUint8, 00, 0x1); // GPIO -// RWMEM (GpioMmioAddr + SB_GPIO_REG13, AccWidthUint8, 0x03, 0); // GPO -// RWMEM (GpioMmioAddr + SB_GPIO_REG13, AccWidthUint8, 0x03, BIT6); // output HIGH -// RWMEM (GpioMmioAddr + SB_GPIO_REG13, AccWidthUint8, 0x63, BIT3); // pullup DISABLE - - // - // APU GPP2: WWAN - // GPIO0: MPCIE_RST1#, LOW active - // GPIO14: WP_DISABLE#, LOW active - // GPIO176: MPICE_PD1, 1 - DISABLE, 0 - ENABLE (Default) - // - // Set VIN1/GPIO176 as GPO for MPCIE_PD1# for wireless disable - RWMEM (IoMuxMmioAddr + SB_GPIO_REG176, AccWidthUint8, 00, 0x1); // GPIO -// RWMEM (GpioMmioAddr + SB_GPIO_REG176, AccWidthUint8, 0x03, 0); // GPO - RWMEM (GpioMmioAddr + SB_GPIO_REG176, AccWidthUint8, 0x03, 0); // output LOW - RWMEM (GpioMmioAddr + SB_GPIO_REG176, AccWidthUint8, 0x63, BIT3); // pullup DISABLE - - // Set AD00/GPIO00 as GPO for MPCIE_RST1# - RWMEM (IoMuxMmioAddr + SB_GPIO_REG00, AccWidthUint8, 00, 0x1); // GPIO -// RWMEM (GpioMmioAddr + SB_GPIO_REG00, AccWidthUint8, 0x03, 0); // GPO -// RWMEM (GpioMmioAddr + SB_GPIO_REG00, AccWidthUint8, 0x03, BIT6); // output LOW - RWMEM (GpioMmioAddr + SB_GPIO_REG00, AccWidthUint8, 0x63, BIT3); // pullup DISABLE - - // Set AD14/GPIO14 as GPO for WP_DISABLE#: disable WWAN -// RWMEM (IoMuxMmioAddr + SB_GPIO_REG14, AccWidthUint8, 00, 0x1); // GPIO -// RWMEM (GpioMmioAddr + SB_GPIO_REG14, AccWidthUint8, 0x03, 0); // GPO -// RWMEM (GpioMmioAddr + SB_GPIO_REG14, AccWidthUint8, 0x03, BIT6); -// RWMEM (GpioMmioAddr + SB_GPIO_REG14, AccWidthUint8, 0x63, BIT3); - - // - // APU GPP3: 1394 - // GPIO59: Power control, HIGH active - // GPIO27: PCIE_RST#_1394, LOW active - // GPIO41: CLKREQ# - // Clock: GPP_CLK8 - // - // Setup SATA_IS5#/FANIN3/GPIO59 as GPO for 1394_ON: - RWMEM (IoMuxMmioAddr + SB_GPIO_REG59, AccWidthUint8, 00, 0x2); // GPIO -// RWMEM (GpioMmioAddr + SB_GPIO_REG59, AccWidthUint8, 0x03, 0); // GPO - RWMEM (GpioMmioAddr + SB_GPIO_REG59, AccWidthUint8, 0x03, BIT6); // output HIGH - RWMEM (GpioMmioAddr + SB_GPIO_REG59, AccWidthUint8, 0x63, BIT3); // pullup DISABLE - - // Setup AD27/GPIO27 as GPO for MPCIE_RST#_1394 - RWMEM (IoMuxMmioAddr + SB_GPIO_REG27, AccWidthUint8, 00, 0x1); // GPIO -// RWMEM (GpioMmioAddr + SB_GPIO_REG27, AccWidthUint8, 0x03, 0); // GPO - RWMEM (GpioMmioAddr + SB_GPIO_REG27, AccWidthUint8, 0x03, BIT6); // output HIGH - RWMEM (GpioMmioAddr + SB_GPIO_REG27, AccWidthUint8, 0x63, BIT3); // pullup DISABLE - - // set REQ2#/CLK_REQ2#/GPIO41 as CLK_REQ# - RWMEM (IoMuxMmioAddr + SB_GPIO_REG41, AccWidthUint8, 00, 0x1); // CLK_REQ2# - - // set AZ_SDIN3/GPIO170 as GPO for GPIO_GATE_C - RWMEM (IoMuxMmioAddr + SB_GPIO_REG170, AccWidthUint8, 00, 0x1); // GPIO - RWMEM (GpioMmioAddr + SB_GPIO_REG170, AccWidthUint8, 0x03, 0); // GPO - RWMEM (GpioMmioAddr + SB_GPIO_REG170, AccWidthUint8, 0x03, BIT6); // output HIGH - RWMEM (GpioMmioAddr + SB_GPIO_REG170, AccWidthUint8, 0x63, BIT3); // pullup DISABLE - // To fix glitch issue - RWMEM (GpioMmioAddr + SB_GPIO_REG170, AccWidthUint8, 0xBF, 0); // set GPIO_GATE_C to LOW - // - // Enable/Disable OnBoard LAN - // - if (!CONFIG(ONBOARD_LAN)) - { // 1 - DISABLED - RWMEM (GpioMmioAddr + SB_GPIO_REG197, AccWidthUint8, 0xBF, 0); // LOM_POWER off - RWMEM (GpioMmioAddr + SB_GPIO_REG25, AccWidthUint8, 0xBF, 0); - RWMEM (GpioMmioAddr + SB_GPIO_REG63, AccWidthUint8, 0xFF, BIT3); // PULL UP - DISABLED - RWMEM (MiscMmioAddr + SB_MISC_REG00+1, AccWidthUint8, 0x0F, 0); // Disable GPP_CLK3 - } -// else -// { // 0 - AUTO -// // set BIT3 = 1 (PULLUP disable), BIT4 = 0 (PULLDOWN Disable) -// RWMEM (GpioMmioAddr + SB_GPIO_REG197, AccWidthUint8, 0x23, BIT3); -// RWMEM (GpioMmioAddr + SB_GPIO_REG25, AccWidthUint8, 0x23, BIT3); -// } - - - // - // Enable/Disable 1394 - // - if (!CONFIG(ONBOARD_1394)) - { // 1 - DISABLED -// RWMEM (GpioMmioAddr + SB_GPIO_REG170, AccWidthUint8, 0xBF, 0); // set GPIO_GATE_C to LOW - RWMEM (GpioMmioAddr + SB_GPIO_REG59, AccWidthUint8, 0xBF, 0); // 1394 power off - RWMEM (GpioMmioAddr + SB_GPIO_REG27, AccWidthUint8, 0xBF, 0); - RWMEM (GpioMmioAddr + SB_GPIO_REG41, AccWidthUint8, 0xFF, BIT3); // pullup DISABLE - RWMEM (MiscMmioAddr + SB_MISC_REG04, AccWidthUint8, 0xF0, 0); // DISABLE GPP_CLK8 -// RWMEM (GpioMmioAddr + SB_GPIO_REG170, AccWidthUint8, 0xBF, BIT6); // set GPIO_GATE_C to HIGH - } -// else -// { // 0 - AUTO -// // set BIT3 = 1 (PULLUP disable), BIT4 = 0 (PULLDOWN Disable), BIT6 = 1 (output HIGH) -// RWMEM (GpioMmioAddr + SB_GPIO_REG27, AccWidthUint8, 0x03, BIT6); -// RWMEM (GpioMmioAddr + SB_GPIO_REG27, AccWidthUint8, 0x63, BIT3); -// -// RWMEM (GpioMmioAddr + SB_GPIO_REG59, AccWidthUint8, 0x03, BIT6); -// RWMEM (GpioMmioAddr + SB_GPIO_REG59, AccWidthUint8, 0x63, BIT3); -// } - -// -// external USB 3.0 control: -// amdExternalUSBController: CMOS, 0 - AUTO, 1 - DISABLE -// GPIO26: PCIE_RST#_USB3.0 -// GPIO46: PCIE_USB30_CLKREQ# -// GPIO200: NEC_USB30_PWR_EN, 0 - OFF, 1 - ON -// Clock: GPP_CLK7 -// GPIO172 used as FCH_USB3.0PORT_EN# 0:ENABLE; 1:DISABLE -// if ((Amd_SystemConfiguration.XhciSwitch == 1) || (SystemConfiguration.amdExternalUSBController == 1)) { -// disable Onboard NEC USB3.0 controller - if (!CONFIG(ONBOARD_USB30)) { - RWMEM (GpioMmioAddr + SB_GPIO_REG200, AccWidthUint8, 0xBF, 0); - RWMEM (GpioMmioAddr + SB_GPIO_REG26, AccWidthUint8, 0xBF, 0); - RWMEM (GpioMmioAddr + SB_GPIO_REG46, AccWidthUint8, 0xFF, BIT3); // PULL_UP DISABLE - RWMEM (MiscMmioAddr + SB_MISC_REG00+3, AccWidthUint8, 0x0F, 0); // DISABLE GPP_CLK7 - RWMEM (GpioMmioAddr + SB_GPIO_REG172, AccWidthUint8, 0xBF, 0); // FCH_USB3.0PORT_EN# 0:ENABLE; 1:DISABLE - } -// } - -// -// BlueTooth control: BT_ON -// amdBlueTooth: CMOS, 0 - AUTO, 1 - DISABLE -// GPIO07: BT_ON, 0 - OFF, 1 - ON -// - if (!CONFIG(ONBOARD_BLUETOOTH)) { - //- if (SystemConfiguration.amdBlueTooth == 1) { - RWMEM (GpioMmioAddr + SB_GPIO_REG07, AccWidthUint8, 0xBF, 0); - //- } - } - -// -// WebCam control: -// amdWebCam: CMOS, 0 - AUTO, 1 - DISABLE -// GPIO34: WEBCAM_ON#, 0 - ON, 1 - OFF -// - if (!CONFIG(ONBOARD_WEBCAM)) { - //- if (SystemConfiguration.amdWebCam == 1) { - RWMEM (GpioMmioAddr + SB_GPIO_REG34, AccWidthUint8, 0xBF, BIT6); - //- } - } - -// -// Travis enable: -// amdTravisCtrl: CMOS, 0 - DISABLE, 1 - ENABLE -// GPIO66: TRAVIS_EN#, 0 - ENABLE, 1 - DISABLE -// - if (!CONFIG(ONBOARD_TRAVIS)) { - //- if (SystemConfiguration.amdTravisCtrl == 0) { - RWMEM (GpioMmioAddr + SB_GPIO_REG66, AccWidthUint8, 0xBF, BIT6); - //- } - } - -// -// Disable Light Sensor if needed -// - if (CONFIG(ONBOARD_LIGHTSENSOR)) { - //- if (SystemConfiguration.amdLightSensor == 1) { - RWMEM (IoMuxMmioAddr + SB_GEVENT_REG12, AccWidthUint8, 0x00, 0x1); - //- } - } - -} diff --git a/src/mainboard/amd/torpedo/gpio.h b/src/mainboard/amd/torpedo/gpio.h deleted file mode 100644 index 938de5323e..0000000000 --- a/src/mainboard/amd/torpedo/gpio.h +++ /dev/null @@ -1,2296 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef _GPIO_H_ -#define _GPIO_H_ - -#include -#include "cbtypes.h" - -#define Mmio_Address( BaseAddr, Register ) \ - ( (UINTN)BaseAddr + \ - (UINTN)(Register) \ - ) - -#define Mmio32_Ptr( BaseAddr, Register ) \ - ( (volatile u32 *)Mmio_Address( BaseAddr, Register ) ) - -#define Mmio32_G( BaseAddr, Register ) \ - *Mmio32_Ptr( BaseAddr, Register ) - -#define Mmio32_And_Or( BaseAddr, Register, AndData, OrData ) \ - Mmio32_G( BaseAddr, Register ) = \ - (u32) ( \ - ( Mmio32_G( BaseAddr, Register ) & \ - (u32)(AndData) \ - ) | \ - (u32)(OrData) \ - ) - -#define Mmio8_Ptr( BaseAddr, Register ) \ - ( (volatile u8 *)Mmio_Address( BaseAddr, Register ) ) - -#define Mmio8_G( BaseAddr, Register ) \ - *Mmio8_Ptr( BaseAddr, Register ) - -#define Mmio8_And_Or( BaseAddr, Register, AndData, OrData ) \ - Mmio8_G( BaseAddr, Register ) = \ - (u8) ( \ - ( Mmio8_G( BaseAddr, Register ) & \ - (u8)(AndData) \ - ) | \ - (u8)(OrData) \ - ) - -#define SMIREG_EVENT_ENABLE 0x04 -#define SMIREG_SCITRIG 0x08 -#define SMIREG_SCILEVEL 0x0C -#define SMIREG_SMISCIEN 0x14 -#define SMIREG_SCIS0EN 0x20 -#define SMIREG_SCIMAP0 0x40 -#define SMIREG_SCIMAP1 0x44 -#define SMIREG_SCIMAP2 0x48 -#define SMIREG_SCIMAP3 0x4C -#define SMIREG_SCIMAP4 0x50 -#define SMIREG_SCIMAP5 0x54 -#define SMIREG_SCIMAP6 0x58 -#define SMIREG_SCIMAP7 0x5C -#define SMIREG_SCIMAP8 0x60 -#define SMIREG_SCIMAP9 0x64 -#define SMIREG_SCIMAP10 0x68 -#define SMIREG_SCIMAP11 0x6C -#define SMIREG_SCIMAP12 0x70 -#define SMIREG_SCIMAP13 0x74 -#define SMIREG_SCIMAP14 0x78 -#define SMIREG_SCIMAP15 0x7C -#define SMIREG_SMITRIG 0x98 -#define SMIREG_SMICONTROL0 0xA0 -#define SMIREG_SMICONTROL1 0xA4 - -#define FUNCTION0 0 -#define FUNCTION1 1 -#define FUNCTION2 2 -#define FUNCTION3 3 -#define NonGpio 0x80 // BIT7 - -// S0-domain General Purpose I/O: GPIO 00~67 -#define GPIO_00_SELECT FUNCTION1+NonGpio // MPCIE_RST1# for J3703, LOW ACTIVE, HIGH DEFAULT -#define GPIO_01_SELECT FUNCTION1+NonGpio // MPCIE_RST2# for J3711, LOW ACTIVE, HIGH DEFAULT -#define GPIO_02_SELECT FUNCTION1 // MPCIE_RST0# for J3700, LOW ACTIVE, HIGH DEFAULT -#define GPIO_03_SELECT FUNCTION1+NonGpio // NOT USED -#define GPIO_04_SELECT FUNCTION1+NonGpio // x1 gpp reset, for J3701, low active, HIGH DEFAULT -#define GPIO_05_SELECT FUNCTION1+NonGpio // express card reset, for J2500, low active, HIGH DEFAULT -#define GPIO_06_SELECT FUNCTION0+NonGpio //NOT USED -#define GPIO_07_SELECT FUNCTION1 // BT_ON, 1: BT ON(DEFAULT); 0: BT OFF -#define GPIO_08_SELECT FUNCTION1 // PEX_STD_SW#, 1:Low Level Mode(default); 0:Standard(desktop) Swing Level -#define GPIO_09_SELECT FUNCTION1+NonGpio // MXM_PRESENT2#, INPUT, LOW MEANS MXM IS INSTALLED -#define GPIO_10_SELECT FUNCTION1+NonGpio // MXM_PRESENT1#, INPUT, LOW MEANS MXM IS INSTALLED -#define GPIO_11_SELECT FUNCTION0+NonGpio // NOT USED -#define GPIO_12_SELECT FUNCTION1 // WL_DISABLE#, DISABLE THE WALN IN J3702 -#define GPIO_13_SELECT FUNCTION1 // WU_DISABLE#, DISABLE THE WUSB IN J3711 -#define GPIO_14_SELECT FUNCTION1 // WP_DISABLE, DISABLE THE WWAN IN J3703 -#define GPIO_15_SELECT FUNCTION1+NonGpio // NOT USED, //FUNCTION1, Reset_CEC# Low Active, High default -#define GPIO_16_SELECT FUNCTION0+NonGpio // NOT USED -#define GPIO_17_SELECT FUNCTION0+NonGpio // NOT USED -#define GPIO_18_SELECT FUNCTION0+NonGpio // NOT USED -#define GPIO_19_SELECT FUNCTION1 // For LASSO_DET# detection when Gevent14# is asserted. -#define GPIO_20_SELECT FUNCTION1 // PX_MUX for DOCKING card, PX MUX selection in mux mode. dGPU enable with high(option) -#define GPIO_21_SELECT FUNCTION1 // DOCK_MUX for DCKING card, MUX selection output. Docking display enabled when high(option) -#define GPIO_22_SELECT FUNCTION1 // SB_PWR_LV, INDICATE TO THE MXM THE SYSTEM IS IN LOW BATTERY MODE - // 1:BATTERY IS FINE(DEFAULT) - // 0:BATTERY IS LOW -#define GPIO_23_SELECT FUNCTION1 // CODEC_ON.1: CODEC ON (default)0: CODEC OFF -#define GPIO_24_SELECT FUNCTION1 // Travis reset,Low active High default -#define GPIO_25_SELECT FUNCTION1+NonGpio // PCIE_RST# for LAN (AND gate with PCIE_RST#); default high -#define GPIO_26_SELECT FUNCTION1+NonGpio // PCIE_RST# for USB3.0 (AND gate with PCIE_RST#); default high -#define GPIO_27_SELECT FUNCTION1+NonGpio // PCIE_RST# for 1394 (AND gate with PCIE_RST#); default high -#define GPIO_28_SELECT FUNCTION1 // MXM PWRGD INDICATOR, INPUT -#define GPIO_29_SELECT FUNCTION1 // MEM HOT, LOW ACTIVE, OUTPUT -#define GPIO_30_SELECT FUNCTION1 // INPUT, DEFINE THE BOARD REVISION 0 -#define GPIO_31_SELECT FUNCTION1 // INPUT, DEFINE THE BOARD REVISION 1 - // 00 - REVA - // 01 - REVB - // 10 - REVC - // 11 - REVD -#define GPIO_32_SELECT FUNCTION1+NonGpio // PCIE_SW - HIGH:MXM; LOW:LASSO -#define GPIO_33_SELECT FUNCTION1 // USB3.0 DETECT of Express Card:USB3.0_DET#, Low active. - // 0:USB3.0 I/F in Express CARD - // 1:PCIE I/F in Express CARD detection -#define GPIO_34_SELECT FUNCTION1 // WEBCAM_ON#. 0: ON (default) 1: OFF -#define GPIO_35_SELECT FUNCTION1 // ODD_DA_INTH# -#define GPIO_36_SELECT FUNCTION0+NonGpio // PCICLK FOR KBC -#define GPIO_37_SELECT FUNCTION0+NonGpio // NOT USED -#define GPIO_38_SELECT FUNCTION0+NonGpio // NOT USED -#define GPIO_39_SELECT FUNCTION0+NonGpio // NOT USED -#define GPIO_40_SELECT FUNCTION1 // For DOCK# detection when Gevent14# is asserted. -#define GPIO_41_SELECT FUNCTION1+NonGpio // 1394 CLK REQ# -#define GPIO_42_SELECT FUNCTION1+NonGpio // X4 GPP CLK REQ# -#define GPIO_43_SELECT FUNCTION0+NonGpio // SMBUS0, CLOCK -#define GPIO_44_SELECT FUNCTION1+NonGpio // PEGPIO0, RESET THE MXM MODULE -#define GPIO_45_SELECT FUNCTION2+NonGpio // PEGPIO1, 1:MXM IS POWER ON; 0:MXM IS OFF -#define GPIO_46_SELECT FUNCTION1+NonGpio // USB3.0_CLKREQ# -#define GPIO_47_SELECT FUNCTION0+NonGpio // SMBUS0, DATA -#define GPIO_48_SELECT FUNCTION0+NonGpio // SERIRQ -#define GPIO_49_SELECT FUNCTION0+NonGpio // LDRQ#1 -#define GPIO_50_SELECT FUNCTION2 // SMARTVOLTAGE TO CONTROL THE 5V - 1:5V; 0:4.56V -#define GPIO_51_SELECT FUNCTION0+NonGpio // back-up for SMARTVOLTAGE1 -#define GPIO_52_SELECT FUNCTION0+NonGpio // CPU FAN OUT -#define GPIO_53_SELECT FUNCTION1 // ODD POWER ENABLE, HIGH ACTIVE -#define GPIO_54_SELECT FUNCTION0+NonGpio // SB_PROCHOT, OUTPUT, LOW ACTIVE -#define GPIO_55_SELECT FUNCTION2+NonGpio // MXM POWER ENABLE(POWER ON MODULE) - // 1:ENABLE; 0:DISABLE - // DEFAULT VALUE DEPENDS ON GPIO 9 AND 10 -#define GPIO_56_SELECT FUNCTION0+NonGpio //HDD2_POWER/HDD0_POWER/CPU FAN ;CPU FAN -#define GPIO_57_SELECT FUNCTION1 // HDD0_POWER -#define GPIO_58_SELECT FUNCTION1 // HDD2_POWER -#define GPIO_59_SELECT FUNCTION2+NonGpio // 1394 POWER, OUTPUT, HIGH ACTIVE -#define GPIO_60_SELECT FUNCTION0+NonGpio // EXPCARD_CLKREQ# -#define GPIO_61_SELECT FUNCTION0+NonGpio // PE0_CLKREQ#, FROM J3700 -#define GPIO_62_SELECT FUNCTION0+NonGpio // PE2_CLKREQ#, FROM J3711 -#define GPIO_63_SELECT FUNCTION0+NonGpio // LAN_CLKREQ# -#define GPIO_64_SELECT FUNCTION0+NonGpio // PE1_CLKREQ#, FROM J3703 -#define GPIO_65_SELECT FUNCTION0+NonGpio // MXM CLK REQ#, FROM MXM -#define GPIO_66_SELECT FUNCTION1 // USED AS TRAVIS_EN#; 0:ENABLE as default -#define GPIO_67_SELECT FUNCTION0+NonGpio // USED AS SATA_ACT# -#define GPIO_68_SELECT FUNCTION0+NonGpio -#define GPIO_69_SELECT FUNCTION0+NonGpio -#define GPIO_70_SELECT FUNCTION0+NonGpio -#define GPIO_71_SELECT FUNCTION0+NonGpio -#define GPIO_72_SELECT FUNCTION0+NonGpio -#define GPIO_73_SELECT FUNCTION0+NonGpio -#define GPIO_74_SELECT FUNCTION0+NonGpio -#define GPIO_75_SELECT FUNCTION0+NonGpio -#define GPIO_76_SELECT FUNCTION0+NonGpio -#define GPIO_77_SELECT FUNCTION0+NonGpio -#define GPIO_78_SELECT FUNCTION0+NonGpio -#define GPIO_79_SELECT FUNCTION0+NonGpio -#define GPIO_80_SELECT FUNCTION0+NonGpio -#define GPIO_81_SELECT FUNCTION0+NonGpio -#define GPIO_82_SELECT FUNCTION0+NonGpio -#define GPIO_83_SELECT FUNCTION0+NonGpio -#define GPIO_84_SELECT FUNCTION0+NonGpio -#define GPIO_85_SELECT FUNCTION0+NonGpio -#define GPIO_86_SELECT FUNCTION0+NonGpio -#define GPIO_87_SELECT FUNCTION0+NonGpio -#define GPIO_88_SELECT FUNCTION0+NonGpio -#define GPIO_89_SELECT FUNCTION0+NonGpio -#define GPIO_90_SELECT FUNCTION0+NonGpio -#define GPIO_91_SELECT FUNCTION0+NonGpio -#define GPIO_92_SELECT FUNCTION0+NonGpio -#define GPIO_93_SELECT FUNCTION0+NonGpio -#define GPIO_94_SELECT FUNCTION0+NonGpio -#define GPIO_95_SELECT FUNCTION0+NonGpio -// GEVENT 00~23 are mapped to GPIO 96~119 -#define GPIO_96_SELECT FUNCTION0 // GA20IN/GEVENT0# -#define GPIO_97_SELECT FUNCTION0 // KBRST#/GEVENT1# -#define GPIO_98_SELECT FUNCTION0 // THRMTRIP#/SMBALERT#/GEVENT2# -> APU_THERMTRIP -#define GPIO_99_SELECT FUNCTION1 // LPC_PME#/GEVENT3# -> EC_SCI# -#define GPIO_100_SELECT FUNCTION2 // PCIE_RST2#/PCI_PME#/GEVENT4# -> APU_MEMHOT# -#define GPIO_101_SELECT FUNCTION1 // LPC_PD#/GEVENT5# -> hotplug of express card, low active -#define GPIO_102_SELECT FUNCTION0+NonGpio // USB_OC6#/IR_TX1/ GEVENT6# -> NOT USED, - // there is a confliction to IR function when this pin is as a GEVENT. -#define GPIO_103_SELECT FUNCTION0+NonGpio // DDR3_RST#/GEVENT7#/VGA_PD -> VGA_PD, - // special pin difination for SB900 VGA OUTPUT, high active, - // VGA power for Hudson-M2 will be down when it was asserted. -#define GPIO_104_SELECT FUNCTION0 // WAKE#/GEVENT8# -> WAKEUP, low active -#define GPIO_105_SELECT FUNCTION2 // SPI_HOLD/GBE_LED1/GEVENT9# - WF_RADIO (wireless radio) -#define GPIO_106_SELECT FUNCTION0 // GBE_LED2/GEVENT10# -> GBE_LED2 -#define GPIO_107_SELECT FUNCTION0+NonGpio // GBE_STAT0/GEVENT11# -> GBE_STAT0 -#define GPIO_108_SELECT FUNCTION2 // USB_OC0#/TRST#/GEVENT12# -> SMBALERT# (Light Sensor), low active - // [option for SPI_TPM_CS# in Hudson-M2 A12)] -#define GPIO_109_SELECT FUNCTION0 // USB_OC1#/TDI/GEVENT13# - USB OC for 0, 1,2,3 & USB_OC expresscard (usb4) & - // USB3.0 PORT0,1:low active,disable all usb ports and new card power at a same time -#define GPIO_110_SELECT FUNCTION2 // USB_OC2#/TCK/GEVENT14# -> Lasso detect or Dock detect, - // plus judge GPIO40 and GPIO19 level,low is assert. - // LASSO_DET# :0 & GPIO19:0 -----> LASSO is present (default) - // DOCK#:0 & GPIO40:0 -----------> DOCK is present(option) -#define GPIO_111_SELECT FUNCTION1+NonGpio // USB_OC3#/AC_PRES/TDO/GEVENT15# -> AC_PRES, high active -#define GPIO_112_SELECT FUNCTION2 // USB_OC4#/IR_RX0/GEVENT16# -> ODD_DA, ODD device attention, - // low active, when it's low, BIOS will enbale ODD_PWR -#define GPIO_113_SELECT FUNCTION2 // USB_OC5#/IR_TX0/GEVENT17# -> use TWARN mapping to trigger GEVENT17# -#define GPIO_114_SELECT FUNCTION2 // BLINK/USB_OC7#/GEVENT18# -> BLINK -#define GPIO_115_SELECT FUNCTION0 // SYS_RESET#/GEVENT19# -> SYS_RST# -#define GPIO_116_SELECT FUNCTION0 // R_RX1/GEVENT20# -> IR INPUT -#define GPIO_117_SELECT FUNCTION1+NonGpio // SPI_CS3#/GBE_STAT1/GEVENT21# -> GBE_STAT1 -#define GPIO_118_SELECT FUNCTION1 // RI#/GEVENT22# -> LID_CLOSED# -#define GPIO_119_SELECT FUNCTION0 // LPC_SMI#/GEVENT23# -> EC_SMI -#define GPIO_120_SELECT FUNCTION0+NonGpio -#define GPIO_121_SELECT FUNCTION0+NonGpio -#define GPIO_122_SELECT FUNCTION0+NonGpio -#define GPIO_123_SELECT FUNCTION0+NonGpio -#define GPIO_124_SELECT FUNCTION0+NonGpio -#define GPIO_125_SELECT FUNCTION0+NonGpio -#define GPIO_126_SELECT FUNCTION0+NonGpio -#define GPIO_127_SELECT FUNCTION0+NonGpio -#define GPIO_128_SELECT FUNCTION0+NonGpio -#define GPIO_129_SELECT FUNCTION0+NonGpio -#define GPIO_130_SELECT FUNCTION0+NonGpio -#define GPIO_131_SELECT FUNCTION0+NonGpio -#define GPIO_132_SELECT FUNCTION0+NonGpio -#define GPIO_133_SELECT FUNCTION0+NonGpio -#define GPIO_134_SELECT FUNCTION0+NonGpio -#define GPIO_135_SELECT FUNCTION0+NonGpio -#define GPIO_136_SELECT FUNCTION0+NonGpio -#define GPIO_137_SELECT FUNCTION0+NonGpio -#define GPIO_138_SELECT FUNCTION0+NonGpio -#define GPIO_139_SELECT FUNCTION0+NonGpio -#define GPIO_140_SELECT FUNCTION0+NonGpio -#define GPIO_141_SELECT FUNCTION0+NonGpio -#define GPIO_142_SELECT FUNCTION0+NonGpio -#define GPIO_143_SELECT FUNCTION0+NonGpio -#define GPIO_144_SELECT FUNCTION0+NonGpio -#define GPIO_145_SELECT FUNCTION0+NonGpio -#define GPIO_146_SELECT FUNCTION0+NonGpio -#define GPIO_147_SELECT FUNCTION0+NonGpio -#define GPIO_148_SELECT FUNCTION0+NonGpio -#define GPIO_149_SELECT FUNCTION0+NonGpio -#define GPIO_150_SELECT FUNCTION0+NonGpio -#define GPIO_151_SELECT FUNCTION0+NonGpio -#define GPIO_152_SELECT FUNCTION0+NonGpio -#define GPIO_153_SELECT FUNCTION0+NonGpio -#define GPIO_154_SELECT FUNCTION0+NonGpio -#define GPIO_155_SELECT FUNCTION0+NonGpio -#define GPIO_156_SELECT FUNCTION0+NonGpio -#define GPIO_157_SELECT FUNCTION0+NonGpio -#define GPIO_158_SELECT FUNCTION0+NonGpio -#define GPIO_159_SELECT FUNCTION0+NonGpio -#define GPIO_160_SELECT FUNCTION0+NonGpio - -// S5-domain General Purpose I/O -#define GPIO_161_SELECT FUNCTION0+NonGpio // ROM_RST# -#define GPIO_162_SELECT FUNCTION0+NonGpio // SPI ROM -#define GPIO_163_SELECT FUNCTION0+NonGpio // SPI ROM -#define GPIO_164_SELECT FUNCTION0+NonGpio // SPI ROM -#define GPIO_165_SELECT FUNCTION0+NonGpio // SPI ROM -#define GPIO_166_SELECT FUNCTION1+NonGpio // GBE_STAT2 -#define GPIO_167_SELECT FUNCTION0+NonGpio // AZ_SDATA_IN0 -#define GPIO_168_SELECT FUNCTION0+NonGpio // AZ_SDATA_IN1 -#define GPIO_169_SELECT FUNCTION0+NonGpio // AZ_SDATA_IN2 -#define GPIO_170_SELECT FUNCTION1+NonGpio // gating the power control signal for ODD, see BIOS requirements doc for detail. -#define GPIO_171_SELECT FUNCTION0+NonGpio // TEMPIN0, -#define GPIO_172_SELECT FUNCTION1 // used as FCH_USB3.0PORT_EN# - 0:ENABLE; 1:DISABLE -#define GPIO_173_SELECT FUNCTION0+NonGpio // TEMPIN3 -#define GPIO_174_SELECT FUNCTION1+NonGpio // USED AS TALERT# -#define GPIO_175_SELECT FUNCTION1 // WLAN, WIRELESS DISABLE 1:DISABLE; 0:ENABLE -#define GPIO_176_SELECT FUNCTION1+NonGpio // WWAN, WIRELESS DISABLE 1:DISABLE; 0:ENABLE -#define GPIO_177_SELECT FUNCTION2+NonGpio // WUSB, WIRELESS DISABLE 1:DISABLE; 0:ENABLE -#define GPIO_178_SELECT FUNCTION2 // MEM_1V5 -#define GPIO_179_SELECT FUNCTION2 // MEM_1V35 -#define GPIO_180_SELECT FUNCTION0+NonGpio // Use as VIN VDDIO -#define GPIO_181_SELECT FUNCTION0+NonGpio // Use as VIN VDDR -#define GPIO_182_SELECT FUNCTION1+NonGpio // GBE_LED3 -#define GPIO_183_SELECT FUNCTION0+NonGpio // GBE_LED0 -#define GPIO_184_SELECT FUNCTION1+NonGpio // USED AS LLB# -#define GPIO_185_SELECT FUNCTION0+NonGpio // USED AS USB -#define GPIO_186_SELECT FUNCTION0+NonGpio // USED AS USB -#define GPIO_187_SELECT FUNCTION2 // USED AS AC LED INDICATOR, LOW ACTIVE -#define GPIO_188_SELECT FUNCTION2 // default used AS BATT LED INDICATOR, LOW ACTIVE - // option for HDMI CEC signal OW ACTIVE -#define GPIO_189_SELECT FUNCTION1 // USED AS AC_OK RECEIVER, INPUT, low active -#define GPIO_190_SELECT FUNCTION1 // USED TO MONITER INTERRUPT FROM BATT CHARGER, INPUT -#define GPIO_191_SELECT FUNCTION0+NonGpio // TOUCH PAD, DATA -#define GPIO_192_SELECT FUNCTION0+NonGpio // TOUCH PAD, CLK -#define GPIO_193_SELECT FUNCTION0+NonGpio // SMBUS CLK, -#define GPIO_194_SELECT FUNCTION0+NonGpio // SMBUS, DATA -#define GPIO_195_SELECT FUNCTION0+NonGpio // SMBUS CLK, -#define GPIO_196_SELECT FUNCTION0+NonGpio // SMBUS, DATA -#define GPIO_197_SELECT FUNCTION2+NonGpio // Default GPIO for LOM_POWER, high active - // RESERVED FOR LCD BACKLIGHT PWM -#define GPIO_198_SELECT FUNCTION0+NonGpio // IMC SCROLL LED CONTROL -#define GPIO_199_SELECT FUNCTION3 // STRAP TO SELECT BOOT ROM - H:LPC ROM L: SPI ROM -#define GPIO_200_SELECT FUNCTION2 // NEC USB3.0 POWER CONTROL 1:ON(DEFAULT); 0:OFF -#define GPIO_201_SELECT FUNCTION0+NonGpio // KSI -#define GPIO_202_SELECT FUNCTION0+NonGpio // KSI -#define GPIO_203_SELECT FUNCTION0+NonGpio // KSI -#define GPIO_204_SELECT FUNCTION0+NonGpio // KSI -#define GPIO_205_SELECT FUNCTION0+NonGpio // KSI -#define GPIO_206_SELECT FUNCTION0+NonGpio // KSI -#define GPIO_207_SELECT FUNCTION0+NonGpio // KSI -#define GPIO_208_SELECT FUNCTION0+NonGpio // KSI -#define GPIO_209_SELECT FUNCTION0+NonGpio // KSO -#define GPIO_210_SELECT FUNCTION0+NonGpio // KSO -#define GPIO_211_SELECT FUNCTION0+NonGpio // KSO -#define GPIO_212_SELECT FUNCTION0+NonGpio // KSO -#define GPIO_213_SELECT FUNCTION0+NonGpio // KSO -#define GPIO_214_SELECT FUNCTION0+NonGpio // KSO -#define GPIO_215_SELECT FUNCTION0+NonGpio // KSO -#define GPIO_216_SELECT FUNCTION0+NonGpio // KSO -#define GPIO_217_SELECT FUNCTION0+NonGpio // KSO -#define GPIO_218_SELECT FUNCTION0+NonGpio // KSO -#define GPIO_219_SELECT FUNCTION0+NonGpio // KSO -#define GPIO_220_SELECT FUNCTION0+NonGpio // KSO -#define GPIO_221_SELECT FUNCTION0+NonGpio // KSO -#define GPIO_222_SELECT FUNCTION0+NonGpio // KSO -#define GPIO_223_SELECT FUNCTION0+NonGpio // KSO -#define GPIO_224_SELECT FUNCTION0+NonGpio // KSO -#define GPIO_225_SELECT FUNCTION2+NonGpio // KSO -#define GPIO_226_SELECT FUNCTION2+NonGpio // KSO -#define GPIO_227_SELECT FUNCTION0+NonGpio // SMBUS CLK, -#define GPIO_228_SELECT FUNCTION0+NonGpio // SMBUS, DATA -#define GPIO_229_SELECT FUNCTION0+NonGpio // DP1_HPD - -#define TYPE_GPI (1 << 5) -#define TYPE_GPO (0 << 5) - -#define GPIO_00_TYPE TYPE_GPO -#define GPIO_01_TYPE TYPE_GPO -#define GPIO_02_TYPE TYPE_GPO -#define GPIO_03_TYPE TYPE_GPO -#define GPIO_04_TYPE TYPE_GPO -#define GPIO_05_TYPE TYPE_GPO -#define GPIO_06_TYPE TYPE_GPO -#define GPIO_07_TYPE TYPE_GPO -#define GPIO_08_TYPE TYPE_GPO -#define GPIO_09_TYPE TYPE_GPI -#define GPIO_10_TYPE TYPE_GPI -#define GPIO_11_TYPE TYPE_GPO -#define GPIO_12_TYPE TYPE_GPO -#define GPIO_13_TYPE TYPE_GPO -#define GPIO_14_TYPE TYPE_GPO -#define GPIO_15_TYPE TYPE_GPO -#define GPIO_16_TYPE TYPE_GPO -#define GPIO_17_TYPE TYPE_GPO -#define GPIO_18_TYPE TYPE_GPO -#define GPIO_19_TYPE TYPE_GPO -#define GPIO_20_TYPE TYPE_GPO -#define GPIO_21_TYPE TYPE_GPO -#define GPIO_22_TYPE TYPE_GPO -#define GPIO_23_TYPE TYPE_GPO -#define GPIO_24_TYPE TYPE_GPO -#define GPIO_25_TYPE TYPE_GPO -#define GPIO_26_TYPE TYPE_GPO -#define GPIO_27_TYPE TYPE_GPO -#define GPIO_28_TYPE TYPE_GPI -#define GPIO_29_TYPE TYPE_GPO -#define GPIO_30_TYPE TYPE_GPI -#define GPIO_31_TYPE TYPE_GPI -#define GPIO_32_TYPE TYPE_GPO -#define GPIO_33_TYPE TYPE_GPI -#define GPIO_34_TYPE TYPE_GPO -#define GPIO_35_TYPE TYPE_GPO -#define GPIO_36_TYPE TYPE_GPO -#define GPIO_37_TYPE TYPE_GPO -#define GPIO_38_TYPE TYPE_GPO -#define GPIO_39_TYPE TYPE_GPO -#define GPIO_40_TYPE TYPE_GPO -#define GPIO_41_TYPE TYPE_GPI -#define GPIO_42_TYPE TYPE_GPI -#define GPIO_43_TYPE TYPE_GPO -#define GPIO_44_TYPE TYPE_GPO -#define GPIO_45_TYPE TYPE_GPO -#define GPIO_46_TYPE TYPE_GPI -#define GPIO_47_TYPE TYPE_GPO -#define GPIO_48_TYPE TYPE_GPO -#define GPIO_49_TYPE TYPE_GPO -#define GPIO_50_TYPE TYPE_GPO -#define GPIO_51_TYPE TYPE_GPO -#define GPIO_52_TYPE TYPE_GPO -#define GPIO_53_TYPE TYPE_GPO -#define GPIO_54_TYPE TYPE_GPO -#define GPIO_55_TYPE TYPE_GPO -#define GPIO_56_TYPE TYPE_GPI -#define GPIO_57_TYPE TYPE_GPO -#define GPIO_58_TYPE TYPE_GPO -#define GPIO_59_TYPE TYPE_GPO -#define GPIO_60_TYPE TYPE_GPI -#define GPIO_61_TYPE TYPE_GPI -#define GPIO_62_TYPE TYPE_GPI -#define GPIO_63_TYPE TYPE_GPI -#define GPIO_64_TYPE TYPE_GPI -#define GPIO_65_TYPE TYPE_GPI -#define GPIO_66_TYPE TYPE_GPO -#define GPIO_67_TYPE TYPE_GPO -#define GPIO_68_TYPE TYPE_GPO -#define GPIO_69_TYPE TYPE_GPO -#define GPIO_70_TYPE TYPE_GPO -#define GPIO_71_TYPE TYPE_GPO -#define GPIO_72_TYPE TYPE_GPO -#define GPIO_73_TYPE TYPE_GPO -#define GPIO_74_TYPE TYPE_GPO -#define GPIO_75_TYPE TYPE_GPO -#define GPIO_76_TYPE TYPE_GPO -#define GPIO_77_TYPE TYPE_GPO -#define GPIO_78_TYPE TYPE_GPO -#define GPIO_79_TYPE TYPE_GPO -#define GPIO_80_TYPE TYPE_GPO -#define GPIO_81_TYPE TYPE_GPO -#define GPIO_82_TYPE TYPE_GPO -#define GPIO_83_TYPE TYPE_GPO -#define GPIO_84_TYPE TYPE_GPO -#define GPIO_85_TYPE TYPE_GPO -#define GPIO_86_TYPE TYPE_GPO -#define GPIO_87_TYPE TYPE_GPO -#define GPIO_88_TYPE TYPE_GPO -#define GPIO_89_TYPE TYPE_GPO -#define GPIO_90_TYPE TYPE_GPO -#define GPIO_91_TYPE TYPE_GPO -#define GPIO_92_TYPE TYPE_GPO -#define GPIO_93_TYPE TYPE_GPO -#define GPIO_94_TYPE TYPE_GPO -#define GPIO_95_TYPE TYPE_GPO - -// GEVENT 00 ~ 23 are mapped to GPIO 96 ~ 119 -#define GPIO_96_TYPE TYPE_GPI -#define GPIO_97_TYPE TYPE_GPI -#define GPIO_98_TYPE TYPE_GPI -#define GPIO_99_TYPE TYPE_GPI -#define GPIO_100_TYPE TYPE_GPI -#define GPIO_101_TYPE TYPE_GPI -#define GPIO_102_TYPE TYPE_GPO -#define GPIO_103_TYPE TYPE_GPO -#define GPIO_104_TYPE TYPE_GPI -#define GPIO_105_TYPE TYPE_GPI -#define GPIO_106_TYPE TYPE_GPO -#define GPIO_107_TYPE TYPE_GPI -#define GPIO_108_TYPE TYPE_GPI -#define GPIO_109_TYPE TYPE_GPI -#define GPIO_110_TYPE TYPE_GPI -#define GPIO_111_TYPE TYPE_GPI -#define GPIO_112_TYPE TYPE_GPI -#define GPIO_113_TYPE TYPE_GPI -#define GPIO_114_TYPE TYPE_GPO -#define GPIO_115_TYPE TYPE_GPI -#define GPIO_116_TYPE TYPE_GPI -#define GPIO_117_TYPE TYPE_GPI -#define GPIO_118_TYPE TYPE_GPI -#define GPIO_119_TYPE TYPE_GPI - -#define GPIO_120_TYPE TYPE_GPO -#define GPIO_121_TYPE TYPE_GPO -#define GPIO_122_TYPE TYPE_GPO -#define GPIO_123_TYPE TYPE_GPO -#define GPIO_124_TYPE TYPE_GPO -#define GPIO_125_TYPE TYPE_GPO -#define GPIO_126_TYPE TYPE_GPO -#define GPIO_127_TYPE TYPE_GPO -#define GPIO_128_TYPE TYPE_GPO -#define GPIO_129_TYPE TYPE_GPO -#define GPIO_130_TYPE TYPE_GPO -#define GPIO_131_TYPE TYPE_GPO -#define GPIO_132_TYPE TYPE_GPO -#define GPIO_133_TYPE TYPE_GPO -#define GPIO_134_TYPE TYPE_GPO -#define GPIO_135_TYPE TYPE_GPO -#define GPIO_136_TYPE TYPE_GPO -#define GPIO_137_TYPE TYPE_GPO -#define GPIO_138_TYPE TYPE_GPO -#define GPIO_139_TYPE TYPE_GPO -#define GPIO_140_TYPE TYPE_GPO -#define GPIO_141_TYPE TYPE_GPO -#define GPIO_142_TYPE TYPE_GPO -#define GPIO_143_TYPE TYPE_GPO -#define GPIO_144_TYPE TYPE_GPO -#define GPIO_145_TYPE TYPE_GPO -#define GPIO_146_TYPE TYPE_GPO -#define GPIO_147_TYPE TYPE_GPO -#define GPIO_148_TYPE TYPE_GPO -#define GPIO_149_TYPE TYPE_GPO -#define GPIO_150_TYPE TYPE_GPO -#define GPIO_151_TYPE TYPE_GPO -#define GPIO_152_TYPE TYPE_GPO -#define GPIO_153_TYPE TYPE_GPO -#define GPIO_154_TYPE TYPE_GPO -#define GPIO_155_TYPE TYPE_GPO -#define GPIO_156_TYPE TYPE_GPO -#define GPIO_157_TYPE TYPE_GPO -#define GPIO_158_TYPE TYPE_GPO -#define GPIO_159_TYPE TYPE_GPO -#define GPIO_160_TYPE TYPE_GPO -#define GPIO_161_TYPE TYPE_GPO -#define GPIO_162_TYPE TYPE_GPO -#define GPIO_163_TYPE TYPE_GPO -#define GPIO_164_TYPE TYPE_GPI -#define GPIO_165_TYPE TYPE_GPO -#define GPIO_166_TYPE TYPE_GPI -#define GPIO_167_TYPE TYPE_GPI -#define GPIO_168_TYPE TYPE_GPI -#define GPIO_169_TYPE TYPE_GPI -#define GPIO_170_TYPE TYPE_GPO -#define GPIO_171_TYPE TYPE_GPI -#define GPIO_172_TYPE TYPE_GPO -#define GPIO_173_TYPE TYPE_GPI -#define GPIO_174_TYPE TYPE_GPI -#define GPIO_175_TYPE TYPE_GPO -#define GPIO_176_TYPE TYPE_GPO -#define GPIO_177_TYPE TYPE_GPO -#define GPIO_178_TYPE TYPE_GPO -#define GPIO_179_TYPE TYPE_GPO -#define GPIO_180_TYPE TYPE_GPO -#define GPIO_181_TYPE TYPE_GPO -#define GPIO_182_TYPE TYPE_GPO -#define GPIO_183_TYPE TYPE_GPO -#define GPIO_184_TYPE TYPE_GPI -#define GPIO_185_TYPE TYPE_GPO -#define GPIO_186_TYPE TYPE_GPO -#define GPIO_187_TYPE TYPE_GPO -#define GPIO_188_TYPE TYPE_GPO -#define GPIO_189_TYPE TYPE_GPI -#define GPIO_190_TYPE TYPE_GPI -#define GPIO_191_TYPE TYPE_GPO -#define GPIO_192_TYPE TYPE_GPO -#define GPIO_193_TYPE TYPE_GPO -#define GPIO_194_TYPE TYPE_GPO -#define GPIO_195_TYPE TYPE_GPO -#define GPIO_196_TYPE TYPE_GPO -#define GPIO_197_TYPE TYPE_GPO -#define GPIO_198_TYPE TYPE_GPO -#define GPIO_199_TYPE TYPE_GPI -#define GPIO_200_TYPE TYPE_GPO -#define GPIO_201_TYPE TYPE_GPI -#define GPIO_202_TYPE TYPE_GPI -#define GPIO_203_TYPE TYPE_GPI -#define GPIO_204_TYPE TYPE_GPI -#define GPIO_205_TYPE TYPE_GPI -#define GPIO_206_TYPE TYPE_GPI -#define GPIO_207_TYPE TYPE_GPI -#define GPIO_208_TYPE TYPE_GPI -#define GPIO_209_TYPE TYPE_GPO -#define GPIO_210_TYPE TYPE_GPO -#define GPIO_211_TYPE TYPE_GPO -#define GPIO_212_TYPE TYPE_GPO -#define GPIO_213_TYPE TYPE_GPO -#define GPIO_214_TYPE TYPE_GPO -#define GPIO_215_TYPE TYPE_GPO -#define GPIO_216_TYPE TYPE_GPO -#define GPIO_217_TYPE TYPE_GPO -#define GPIO_218_TYPE TYPE_GPO -#define GPIO_219_TYPE TYPE_GPO -#define GPIO_220_TYPE TYPE_GPO -#define GPIO_221_TYPE TYPE_GPO -#define GPIO_222_TYPE TYPE_GPO -#define GPIO_223_TYPE TYPE_GPO -#define GPIO_224_TYPE TYPE_GPO -#define GPIO_225_TYPE TYPE_GPO -#define GPIO_226_TYPE TYPE_GPO -#define GPIO_227_TYPE TYPE_GPO -#define GPIO_228_TYPE TYPE_GPO -#define GPIO_229_TYPE TYPE_GPO - -#define GPO_LOW (0 << 6) -#define GPO_HI (1 << 6) - -#define GPO_00_LEVEL GPO_HI -#define GPO_01_LEVEL GPO_HI -#define GPO_02_LEVEL GPO_HI -#define GPO_03_LEVEL GPO_HI -#define GPO_04_LEVEL GPO_HI -#define GPO_05_LEVEL GPO_HI -#define GPO_06_LEVEL GPO_HI -#define GPO_07_LEVEL GPO_HI -#define GPO_08_LEVEL GPO_HI -#define GPO_09_LEVEL GPO_LOW -#define GPO_10_LEVEL GPO_LOW -#define GPO_11_LEVEL GPO_HI -#define GPO_12_LEVEL GPO_HI -#define GPO_13_LEVEL GPO_HI -#define GPO_14_LEVEL GPO_HI -#define GPO_15_LEVEL GPO_HI -#define GPO_16_LEVEL GPO_HI -#define GPO_17_LEVEL GPO_HI -#define GPO_18_LEVEL GPO_HI -#define GPO_19_LEVEL GPO_LOW -#define GPO_20_LEVEL GPO_LOW -#define GPO_21_LEVEL GPO_LOW -#define GPO_22_LEVEL GPO_HI -#define GPO_23_LEVEL GPO_HI -#define GPO_24_LEVEL GPO_HI -#define GPO_25_LEVEL GPO_HI -#define GPO_26_LEVEL GPO_HI -#define GPO_27_LEVEL GPO_HI -#define GPO_28_LEVEL GPO_LOW -#define GPO_29_LEVEL GPO_HI -#define GPO_30_LEVEL GPO_LOW -#define GPO_31_LEVEL GPO_LOW -#define GPO_32_LEVEL GPO_HI -#define GPO_33_LEVEL GPO_LOW -#define GPO_34_LEVEL GPO_LOW -#define GPO_35_LEVEL GPO_LOW -#define GPO_36_LEVEL GPO_LOW -#define GPO_37_LEVEL GPO_HI -#define GPO_38_LEVEL GPO_HI -#define GPO_39_LEVEL GPO_HI -#define GPO_40_LEVEL GPO_LOW -#define GPO_41_LEVEL GPO_LOW -#define GPO_42_LEVEL GPO_LOW -#define GPO_43_LEVEL GPO_LOW -#define GPO_44_LEVEL GPO_HI -#define GPO_45_LEVEL GPO_HI -#define GPO_46_LEVEL GPO_LOW -#define GPO_47_LEVEL GPO_LOW -#define GPO_48_LEVEL GPO_LOW -#define GPO_49_LEVEL GPO_HI -#define GPO_50_LEVEL GPO_HI -#define GPO_51_LEVEL GPO_LOW -#define GPO_52_LEVEL GPO_HI -#define GPO_53_LEVEL GPO_HI -#define GPO_54_LEVEL GPO_LOW -#define GPO_55_LEVEL GPO_LOW -#define GPO_56_LEVEL GPO_LOW -#define GPO_57_LEVEL GPO_HI -#define GPO_58_LEVEL GPO_HI -#define GPO_59_LEVEL GPO_HI -#define GPO_60_LEVEL GPO_LOW -#define GPO_61_LEVEL GPO_LOW -#define GPO_62_LEVEL GPO_LOW -#define GPO_63_LEVEL GPO_LOW -#define GPO_64_LEVEL GPO_LOW -#define GPO_65_LEVEL GPO_LOW -#define GPO_66_LEVEL GPO_LOW -#define GPO_67_LEVEL GPO_LOW -#define GPO_68_LEVEL GPO_LOW -#define GPO_69_LEVEL GPO_LOW -#define GPO_70_LEVEL GPO_LOW -#define GPO_71_LEVEL GPO_LOW -#define GPO_72_LEVEL GPO_LOW -#define GPO_73_LEVEL GPO_LOW -#define GPO_74_LEVEL GPO_LOW -#define GPO_75_LEVEL GPO_LOW -#define GPO_76_LEVEL GPO_LOW -#define GPO_77_LEVEL GPO_LOW -#define GPO_78_LEVEL GPO_LOW -#define GPO_79_LEVEL GPO_LOW -#define GPO_80_LEVEL GPO_LOW -#define GPO_81_LEVEL GPO_LOW -#define GPO_82_LEVEL GPO_LOW -#define GPO_83_LEVEL GPO_LOW -#define GPO_84_LEVEL GPO_LOW -#define GPO_85_LEVEL GPO_LOW -#define GPO_86_LEVEL GPO_LOW -#define GPO_87_LEVEL GPO_LOW -#define GPO_88_LEVEL GPO_LOW -#define GPO_89_LEVEL GPO_LOW -#define GPO_90_LEVEL GPO_LOW -#define GPO_91_LEVEL GPO_LOW -#define GPO_92_LEVEL GPO_LOW -#define GPO_93_LEVEL GPO_LOW -#define GPO_94_LEVEL GPO_LOW -#define GPO_95_LEVEL GPO_LOW -#define GPO_96_LEVEL GPO_LOW -#define GPO_97_LEVEL GPO_LOW -#define GPO_98_LEVEL GPO_LOW -#define GPO_99_LEVEL GPO_LOW -#define GPO_100_LEVEL GPO_LOW -#define GPO_101_LEVEL GPO_LOW -#define GPO_102_LEVEL GPO_LOW -#define GPO_103_LEVEL GPO_LOW -#define GPO_104_LEVEL GPO_LOW -#define GPO_105_LEVEL GPO_LOW -#define GPO_106_LEVEL GPO_LOW -#define GPO_107_LEVEL GPO_LOW -#define GPO_108_LEVEL GPO_HI -#define GPO_109_LEVEL GPO_LOW -#define GPO_110_LEVEL GPO_HI -#define GPO_111_LEVEL GPO_HI -#define GPO_112_LEVEL GPO_HI -#define GPO_113_LEVEL GPO_LOW -#define GPO_114_LEVEL GPO_LOW -#define GPO_115_LEVEL GPO_LOW -#define GPO_116_LEVEL GPO_LOW -#define GPO_117_LEVEL GPO_LOW -#define GPO_118_LEVEL GPO_LOW -#define GPO_119_LEVEL GPO_LOW -#define GPO_120_LEVEL GPO_LOW -#define GPO_121_LEVEL GPO_LOW -#define GPO_122_LEVEL GPO_LOW -#define GPO_123_LEVEL GPO_LOW -#define GPO_124_LEVEL GPO_LOW -#define GPO_125_LEVEL GPO_LOW -#define GPO_126_LEVEL GPO_LOW -#define GPO_127_LEVEL GPO_LOW -#define GPO_128_LEVEL GPO_LOW -#define GPO_129_LEVEL GPO_LOW -#define GPO_130_LEVEL GPO_LOW -#define GPO_131_LEVEL GPO_LOW -#define GPO_132_LEVEL GPO_LOW -#define GPO_133_LEVEL GPO_LOW -#define GPO_134_LEVEL GPO_LOW -#define GPO_135_LEVEL GPO_LOW -#define GPO_136_LEVEL GPO_LOW -#define GPO_137_LEVEL GPO_LOW -#define GPO_138_LEVEL GPO_LOW -#define GPO_139_LEVEL GPO_LOW -#define GPO_140_LEVEL GPO_LOW -#define GPO_141_LEVEL GPO_LOW -#define GPO_142_LEVEL GPO_LOW -#define GPO_143_LEVEL GPO_LOW -#define GPO_144_LEVEL GPO_LOW -#define GPO_145_LEVEL GPO_LOW -#define GPO_146_LEVEL GPO_LOW -#define GPO_147_LEVEL GPO_LOW -#define GPO_148_LEVEL GPO_LOW -#define GPO_149_LEVEL GPO_LOW -#define GPO_150_LEVEL GPO_LOW -#define GPO_151_LEVEL GPO_LOW -#define GPO_152_LEVEL GPO_LOW -#define GPO_153_LEVEL GPO_LOW -#define GPO_154_LEVEL GPO_LOW -#define GPO_155_LEVEL GPO_LOW -#define GPO_156_LEVEL GPO_LOW -#define GPO_157_LEVEL GPO_LOW -#define GPO_158_LEVEL GPO_LOW -#define GPO_159_LEVEL GPO_LOW -#define GPO_160_LEVEL GPO_LOW -#define GPO_161_LEVEL GPO_LOW -#define GPO_162_LEVEL GPO_LOW -#define GPO_163_LEVEL GPO_LOW -#define GPO_164_LEVEL GPO_LOW -#define GPO_165_LEVEL GPO_LOW -#define GPO_166_LEVEL GPO_LOW -#define GPO_167_LEVEL GPO_LOW -#define GPO_168_LEVEL GPO_LOW -#define GPO_169_LEVEL GPO_LOW -#define GPO_170_LEVEL GPO_HI -#define GPO_171_LEVEL GPO_LOW -#define GPO_172_LEVEL GPO_HI // FCH_USB3.0PORT_EN# 0:ENABLE; 1:DISABLE -#define GPO_173_LEVEL GPO_LOW -#define GPO_174_LEVEL GPO_LOW -#define GPO_175_LEVEL GPO_LOW -#define GPO_176_LEVEL GPO_LOW -#define GPO_177_LEVEL GPO_LOW -#define GPO_178_LEVEL GPO_HI // AMD.SR BU to set VDDIO level to 1.5V for Barb BU -#define GPO_179_LEVEL GPO_HI -#define GPO_180_LEVEL GPO_HI -#define GPO_181_LEVEL GPO_LOW -#define GPO_182_LEVEL GPO_HI -#define GPO_183_LEVEL GPO_LOW -#define GPO_184_LEVEL GPO_LOW -#define GPO_185_LEVEL GPO_LOW -#define GPO_186_LEVEL GPO_LOW -#define GPO_187_LEVEL GPO_LOW -#define GPO_188_LEVEL GPO_LOW -#define GPO_189_LEVEL GPO_LOW -#define GPO_190_LEVEL GPO_LOW -#define GPO_191_LEVEL GPO_LOW -#define GPO_192_LEVEL GPO_LOW -#define GPO_193_LEVEL GPO_LOW -#define GPO_194_LEVEL GPO_LOW -#define GPO_195_LEVEL GPO_LOW -#define GPO_196_LEVEL GPO_LOW -#define GPO_197_LEVEL GPO_LOW -#define GPO_198_LEVEL GPO_LOW -#define GPO_199_LEVEL GPO_LOW -#define GPO_200_LEVEL GPO_HI -#define GPO_201_LEVEL GPO_LOW -#define GPO_202_LEVEL GPO_LOW -#define GPO_203_LEVEL GPO_LOW -#define GPO_204_LEVEL GPO_LOW -#define GPO_205_LEVEL GPO_LOW -#define GPO_206_LEVEL GPO_LOW -#define GPO_207_LEVEL GPO_LOW -#define GPO_208_LEVEL GPO_LOW -#define GPO_209_LEVEL GPO_LOW -#define GPO_210_LEVEL GPO_LOW -#define GPO_211_LEVEL GPO_LOW -#define GPO_212_LEVEL GPO_LOW -#define GPO_213_LEVEL GPO_LOW -#define GPO_214_LEVEL GPO_LOW -#define GPO_215_LEVEL GPO_LOW -#define GPO_216_LEVEL GPO_LOW -#define GPO_217_LEVEL GPO_LOW -#define GPO_218_LEVEL GPO_LOW -#define GPO_219_LEVEL GPO_LOW -#define GPO_220_LEVEL GPO_LOW -#define GPO_221_LEVEL GPO_LOW -#define GPO_222_LEVEL GPO_LOW -#define GPO_223_LEVEL GPO_LOW -#define GPO_224_LEVEL GPO_LOW -#define GPO_225_LEVEL GPO_LOW -#define GPO_226_LEVEL GPO_LOW -#define GPO_227_LEVEL GPO_LOW -#define GPO_228_LEVEL GPO_LOW -#define GPO_229_LEVEL GPO_LOW - -#define GPIO_NONSTICKY (0 << 2) -#define GPIO_STICKY (1 << 2) - -#define GPIO_00_STICKY GPIO_NONSTICKY -#define GPIO_01_STICKY GPIO_NONSTICKY -#define GPIO_02_STICKY GPIO_NONSTICKY -#define GPIO_03_STICKY GPIO_NONSTICKY -#define GPIO_04_STICKY GPIO_NONSTICKY -#define GPIO_05_STICKY GPIO_NONSTICKY -#define GPIO_06_STICKY GPIO_NONSTICKY -#define GPIO_07_STICKY GPIO_NONSTICKY -#define GPIO_08_STICKY GPIO_NONSTICKY -#define GPIO_09_STICKY GPIO_NONSTICKY -#define GPIO_10_STICKY GPIO_NONSTICKY -#define GPIO_11_STICKY GPIO_NONSTICKY -#define GPIO_12_STICKY GPIO_NONSTICKY -#define GPIO_13_STICKY GPIO_NONSTICKY -#define GPIO_14_STICKY GPIO_NONSTICKY -#define GPIO_15_STICKY GPIO_NONSTICKY -#define GPIO_16_STICKY GPIO_NONSTICKY -#define GPIO_17_STICKY GPIO_STICKY -#define GPIO_18_STICKY GPIO_NONSTICKY -#define GPIO_19_STICKY GPIO_NONSTICKY -#define GPIO_20_STICKY GPIO_NONSTICKY -#define GPIO_21_STICKY GPIO_NONSTICKY -#define GPIO_22_STICKY GPIO_NONSTICKY -#define GPIO_23_STICKY GPIO_NONSTICKY -#define GPIO_24_STICKY GPIO_NONSTICKY -#define GPIO_25_STICKY GPIO_NONSTICKY -#define GPIO_26_STICKY GPIO_NONSTICKY -#define GPIO_27_STICKY GPIO_NONSTICKY -#define GPIO_28_STICKY GPIO_NONSTICKY -#define GPIO_29_STICKY GPIO_NONSTICKY -#define GPIO_30_STICKY GPIO_NONSTICKY -#define GPIO_31_STICKY GPIO_NONSTICKY -#define GPIO_32_STICKY GPIO_NONSTICKY -#define GPIO_33_STICKY GPIO_NONSTICKY -#define GPIO_34_STICKY GPIO_NONSTICKY -#define GPIO_35_STICKY GPIO_NONSTICKY -#define GPIO_36_STICKY GPIO_NONSTICKY -#define GPIO_37_STICKY GPIO_NONSTICKY -#define GPIO_38_STICKY GPIO_NONSTICKY -#define GPIO_39_STICKY GPIO_NONSTICKY -#define GPIO_40_STICKY GPIO_NONSTICKY -#define GPIO_41_STICKY GPIO_NONSTICKY -#define GPIO_42_STICKY GPIO_NONSTICKY -#define GPIO_43_STICKY GPIO_NONSTICKY -#define GPIO_44_STICKY GPIO_NONSTICKY -#define GPIO_45_STICKY GPIO_NONSTICKY -#define GPIO_46_STICKY GPIO_NONSTICKY -#define GPIO_47_STICKY GPIO_NONSTICKY -#define GPIO_48_STICKY GPIO_NONSTICKY -#define GPIO_49_STICKY GPIO_NONSTICKY -#define GPIO_50_STICKY GPIO_NONSTICKY -#define GPIO_51_STICKY GPIO_NONSTICKY -#define GPIO_52_STICKY GPIO_NONSTICKY -#define GPIO_53_STICKY GPIO_NONSTICKY -#define GPIO_54_STICKY GPIO_NONSTICKY -#define GPIO_55_STICKY GPIO_NONSTICKY -#define GPIO_56_STICKY GPIO_NONSTICKY -#define GPIO_57_STICKY GPIO_NONSTICKY -#define GPIO_58_STICKY GPIO_NONSTICKY -#define GPIO_59_STICKY GPIO_NONSTICKY -#define GPIO_60_STICKY GPIO_NONSTICKY -#define GPIO_61_STICKY GPIO_NONSTICKY -#define GPIO_62_STICKY GPIO_NONSTICKY -#define GPIO_63_STICKY GPIO_NONSTICKY -#define GPIO_64_STICKY GPIO_NONSTICKY -#define GPIO_65_STICKY GPIO_NONSTICKY -#define GPIO_66_STICKY GPIO_NONSTICKY -#define GPIO_67_STICKY GPIO_NONSTICKY -#define GPIO_68_STICKY GPIO_NONSTICKY -#define GPIO_69_STICKY GPIO_NONSTICKY -#define GPIO_70_STICKY GPIO_NONSTICKY -#define GPIO_71_STICKY GPIO_NONSTICKY -#define GPIO_72_STICKY GPIO_NONSTICKY -#define GPIO_73_STICKY GPIO_NONSTICKY -#define GPIO_74_STICKY GPIO_NONSTICKY -#define GPIO_75_STICKY GPIO_NONSTICKY -#define GPIO_76_STICKY GPIO_NONSTICKY -#define GPIO_77_STICKY GPIO_NONSTICKY -#define GPIO_78_STICKY GPIO_NONSTICKY -#define GPIO_79_STICKY GPIO_NONSTICKY -#define GPIO_80_STICKY GPIO_NONSTICKY -#define GPIO_81_STICKY GPIO_NONSTICKY -#define GPIO_82_STICKY GPIO_NONSTICKY -#define GPIO_83_STICKY GPIO_NONSTICKY -#define GPIO_84_STICKY GPIO_NONSTICKY -#define GPIO_85_STICKY GPIO_NONSTICKY -#define GPIO_86_STICKY GPIO_NONSTICKY -#define GPIO_87_STICKY GPIO_NONSTICKY -#define GPIO_88_STICKY GPIO_NONSTICKY -#define GPIO_89_STICKY GPIO_NONSTICKY -#define GPIO_90_STICKY GPIO_NONSTICKY -#define GPIO_91_STICKY GPIO_NONSTICKY -#define GPIO_92_STICKY GPIO_NONSTICKY -#define GPIO_93_STICKY GPIO_NONSTICKY -#define GPIO_94_STICKY GPIO_NONSTICKY -#define GPIO_95_STICKY GPIO_NONSTICKY -#define GPIO_96_STICKY GPIO_NONSTICKY -#define GPIO_97_STICKY GPIO_NONSTICKY -#define GPIO_98_STICKY GPIO_NONSTICKY -#define GPIO_99_STICKY GPIO_NONSTICKY -#define GPIO_100_STICKY GPIO_NONSTICKY -#define GPIO_101_STICKY GPIO_NONSTICKY -#define GPIO_102_STICKY GPIO_STICKY -#define GPIO_103_STICKY GPIO_STICKY -#define GPIO_104_STICKY GPIO_NONSTICKY -#define GPIO_105_STICKY GPIO_NONSTICKY -#define GPIO_106_STICKY GPIO_NONSTICKY -#define GPIO_107_STICKY GPIO_NONSTICKY -#define GPIO_108_STICKY GPIO_STICKY -#define GPIO_109_STICKY GPIO_NONSTICKY -#define GPIO_110_STICKY GPIO_NONSTICKY -#define GPIO_111_STICKY GPIO_NONSTICKY -#define GPIO_112_STICKY GPIO_NONSTICKY -#define GPIO_113_STICKY GPIO_NONSTICKY -#define GPIO_114_STICKY GPIO_NONSTICKY -#define GPIO_115_STICKY GPIO_NONSTICKY -#define GPIO_116_STICKY GPIO_NONSTICKY -#define GPIO_117_STICKY GPIO_NONSTICKY -#define GPIO_118_STICKY GPIO_NONSTICKY -#define GPIO_119_STICKY GPIO_NONSTICKY -#define GPIO_120_STICKY GPIO_NONSTICKY -#define GPIO_121_STICKY GPIO_NONSTICKY -#define GPIO_122_STICKY GPIO_NONSTICKY -#define GPIO_123_STICKY GPIO_NONSTICKY -#define GPIO_124_STICKY GPIO_NONSTICKY -#define GPIO_125_STICKY GPIO_NONSTICKY -#define GPIO_126_STICKY GPIO_NONSTICKY -#define GPIO_127_STICKY GPIO_NONSTICKY -#define GPIO_128_STICKY GPIO_NONSTICKY -#define GPIO_129_STICKY GPIO_NONSTICKY -#define GPIO_130_STICKY GPIO_NONSTICKY -#define GPIO_131_STICKY GPIO_NONSTICKY -#define GPIO_132_STICKY GPIO_NONSTICKY -#define GPIO_133_STICKY GPIO_NONSTICKY -#define GPIO_134_STICKY GPIO_NONSTICKY -#define GPIO_135_STICKY GPIO_NONSTICKY -#define GPIO_136_STICKY GPIO_NONSTICKY -#define GPIO_137_STICKY GPIO_NONSTICKY -#define GPIO_138_STICKY GPIO_NONSTICKY -#define GPIO_139_STICKY GPIO_NONSTICKY -#define GPIO_140_STICKY GPIO_NONSTICKY -#define GPIO_141_STICKY GPIO_NONSTICKY -#define GPIO_142_STICKY GPIO_NONSTICKY -#define GPIO_143_STICKY GPIO_NONSTICKY -#define GPIO_144_STICKY GPIO_NONSTICKY -#define GPIO_145_STICKY GPIO_NONSTICKY -#define GPIO_146_STICKY GPIO_NONSTICKY -#define GPIO_147_STICKY GPIO_NONSTICKY -#define GPIO_148_STICKY GPIO_NONSTICKY -#define GPIO_149_STICKY GPIO_NONSTICKY -#define GPIO_150_STICKY GPIO_NONSTICKY -#define GPIO_151_STICKY GPIO_NONSTICKY -#define GPIO_152_STICKY GPIO_NONSTICKY -#define GPIO_153_STICKY GPIO_NONSTICKY -#define GPIO_154_STICKY GPIO_NONSTICKY -#define GPIO_155_STICKY GPIO_NONSTICKY -#define GPIO_156_STICKY GPIO_NONSTICKY -#define GPIO_157_STICKY GPIO_NONSTICKY -#define GPIO_158_STICKY GPIO_NONSTICKY -#define GPIO_159_STICKY GPIO_NONSTICKY -#define GPIO_160_STICKY GPIO_NONSTICKY -#define GPIO_161_STICKY GPIO_NONSTICKY -#define GPIO_162_STICKY GPIO_NONSTICKY -#define GPIO_163_STICKY GPIO_NONSTICKY -#define GPIO_164_STICKY GPIO_NONSTICKY -#define GPIO_165_STICKY GPIO_NONSTICKY -#define GPIO_166_STICKY GPIO_NONSTICKY -#define GPIO_167_STICKY GPIO_NONSTICKY -#define GPIO_168_STICKY GPIO_NONSTICKY -#define GPIO_169_STICKY GPIO_NONSTICKY -#define GPIO_170_STICKY GPIO_STICKY -#define GPIO_171_STICKY GPIO_NONSTICKY -#define GPIO_172_STICKY GPIO_STICKY -#define GPIO_173_STICKY GPIO_NONSTICKY -#define GPIO_174_STICKY GPIO_NONSTICKY -#define GPIO_175_STICKY GPIO_NONSTICKY -#define GPIO_176_STICKY GPIO_NONSTICKY -#define GPIO_177_STICKY GPIO_NONSTICKY -#define GPIO_178_STICKY GPIO_NONSTICKY -#define GPIO_179_STICKY GPIO_NONSTICKY -#define GPIO_180_STICKY GPIO_NONSTICKY -#define GPIO_181_STICKY GPIO_NONSTICKY -#define GPIO_182_STICKY GPIO_NONSTICKY -#define GPIO_183_STICKY GPIO_NONSTICKY -#define GPIO_184_STICKY GPIO_NONSTICKY -#define GPIO_185_STICKY GPIO_NONSTICKY -#define GPIO_186_STICKY GPIO_NONSTICKY -#define GPIO_187_STICKY GPIO_NONSTICKY -#define GPIO_188_STICKY GPIO_NONSTICKY -#define GPIO_189_STICKY GPIO_NONSTICKY -#define GPIO_190_STICKY GPIO_NONSTICKY -#define GPIO_191_STICKY GPIO_NONSTICKY -#define GPIO_192_STICKY GPIO_NONSTICKY -#define GPIO_193_STICKY GPIO_NONSTICKY -#define GPIO_194_STICKY GPIO_NONSTICKY -#define GPIO_195_STICKY GPIO_NONSTICKY -#define GPIO_196_STICKY GPIO_NONSTICKY -#define GPIO_197_STICKY GPIO_NONSTICKY -#define GPIO_198_STICKY GPIO_NONSTICKY -#define GPIO_199_STICKY GPIO_NONSTICKY -#define GPIO_200_STICKY GPIO_NONSTICKY -#define GPIO_201_STICKY GPIO_NONSTICKY -#define GPIO_202_STICKY GPIO_NONSTICKY -#define GPIO_203_STICKY GPIO_NONSTICKY -#define GPIO_204_STICKY GPIO_NONSTICKY -#define GPIO_205_STICKY GPIO_NONSTICKY -#define GPIO_206_STICKY GPIO_NONSTICKY -#define GPIO_207_STICKY GPIO_NONSTICKY -#define GPIO_208_STICKY GPIO_NONSTICKY -#define GPIO_209_STICKY GPIO_NONSTICKY -#define GPIO_210_STICKY GPIO_NONSTICKY -#define GPIO_211_STICKY GPIO_NONSTICKY -#define GPIO_212_STICKY GPIO_NONSTICKY -#define GPIO_213_STICKY GPIO_NONSTICKY -#define GPIO_214_STICKY GPIO_NONSTICKY -#define GPIO_215_STICKY GPIO_NONSTICKY -#define GPIO_216_STICKY GPIO_NONSTICKY -#define GPIO_217_STICKY GPIO_NONSTICKY -#define GPIO_218_STICKY GPIO_NONSTICKY -#define GPIO_219_STICKY GPIO_NONSTICKY -#define GPIO_220_STICKY GPIO_NONSTICKY -#define GPIO_221_STICKY GPIO_NONSTICKY -#define GPIO_222_STICKY GPIO_NONSTICKY -#define GPIO_223_STICKY GPIO_NONSTICKY -#define GPIO_224_STICKY GPIO_NONSTICKY -#define GPIO_225_STICKY GPIO_NONSTICKY -#define GPIO_226_STICKY GPIO_NONSTICKY -#define GPIO_227_STICKY GPIO_NONSTICKY -#define GPIO_228_STICKY GPIO_NONSTICKY -#define GPIO_229_STICKY GPIO_NONSTICKY - -#define PULLUP_ENABLE (0 << 3) -#define PULLUP_DISABLE (1 << 3) - -#define GPIO_00_PULLUP PULLUP_DISABLE -#define GPIO_01_PULLUP PULLUP_DISABLE -#define GPIO_02_PULLUP PULLUP_DISABLE -#define GPIO_03_PULLUP PULLUP_DISABLE -#define GPIO_04_PULLUP PULLUP_DISABLE -#define GPIO_05_PULLUP PULLUP_DISABLE -#define GPIO_06_PULLUP PULLUP_DISABLE -#define GPIO_07_PULLUP PULLUP_DISABLE -#define GPIO_08_PULLUP PULLUP_DISABLE -#define GPIO_09_PULLUP PULLUP_DISABLE -#define GPIO_10_PULLUP PULLUP_DISABLE -#define GPIO_11_PULLUP PULLUP_DISABLE -#define GPIO_12_PULLUP PULLUP_DISABLE -#define GPIO_13_PULLUP PULLUP_DISABLE -#define GPIO_14_PULLUP PULLUP_DISABLE -#define GPIO_15_PULLUP PULLUP_DISABLE -#define GPIO_16_PULLUP PULLUP_DISABLE -#define GPIO_17_PULLUP PULLUP_DISABLE -#define GPIO_18_PULLUP PULLUP_DISABLE -#define GPIO_19_PULLUP PULLUP_DISABLE -#define GPIO_20_PULLUP PULLUP_DISABLE -#define GPIO_21_PULLUP PULLUP_DISABLE -#define GPIO_22_PULLUP PULLUP_DISABLE -#define GPIO_23_PULLUP PULLUP_DISABLE -#define GPIO_24_PULLUP PULLUP_DISABLE -#define GPIO_25_PULLUP PULLUP_DISABLE -#define GPIO_26_PULLUP PULLUP_DISABLE -#define GPIO_27_PULLUP PULLUP_DISABLE -#define GPIO_28_PULLUP PULLUP_DISABLE -#define GPIO_29_PULLUP PULLUP_DISABLE -#define GPIO_30_PULLUP PULLUP_DISABLE -#define GPIO_31_PULLUP PULLUP_DISABLE -#define GPIO_32_PULLUP PULLUP_DISABLE -#define GPIO_33_PULLUP PULLUP_DISABLE -#define GPIO_34_PULLUP PULLUP_DISABLE -#define GPIO_35_PULLUP PULLUP_DISABLE -#define GPIO_36_PULLUP PULLUP_DISABLE -#define GPIO_37_PULLUP PULLUP_DISABLE -#define GPIO_38_PULLUP PULLUP_DISABLE -#define GPIO_39_PULLUP PULLUP_DISABLE -#define GPIO_40_PULLUP PULLUP_DISABLE -#define GPIO_41_PULLUP PULLUP_DISABLE -#define GPIO_42_PULLUP PULLUP_DISABLE -#define GPIO_43_PULLUP PULLUP_DISABLE -#define GPIO_44_PULLUP PULLUP_DISABLE -#define GPIO_45_PULLUP PULLUP_DISABLE -#define GPIO_46_PULLUP PULLUP_DISABLE -#define GPIO_47_PULLUP PULLUP_DISABLE -#define GPIO_48_PULLUP PULLUP_DISABLE -#define GPIO_49_PULLUP PULLUP_DISABLE -#define GPIO_50_PULLUP PULLUP_DISABLE -#define GPIO_51_PULLUP PULLUP_DISABLE -#define GPIO_52_PULLUP PULLUP_DISABLE -#define GPIO_53_PULLUP PULLUP_DISABLE -#define GPIO_54_PULLUP PULLUP_DISABLE -#define GPIO_55_PULLUP PULLUP_DISABLE -#define GPIO_56_PULLUP PULLUP_DISABLE -#define GPIO_57_PULLUP PULLUP_DISABLE -#define GPIO_58_PULLUP PULLUP_DISABLE -#define GPIO_59_PULLUP PULLUP_DISABLE -#define GPIO_60_PULLUP PULLUP_DISABLE -#define GPIO_61_PULLUP PULLUP_DISABLE -#define GPIO_62_PULLUP PULLUP_DISABLE -#define GPIO_63_PULLUP PULLUP_DISABLE -#define GPIO_64_PULLUP PULLUP_DISABLE -#define GPIO_65_PULLUP PULLUP_DISABLE -#define GPIO_66_PULLUP PULLUP_DISABLE -#define GPIO_67_PULLUP PULLUP_DISABLE -#define GPIO_68_PULLUP PULLUP_DISABLE -#define GPIO_69_PULLUP PULLUP_DISABLE -#define GPIO_70_PULLUP PULLUP_DISABLE -#define GPIO_71_PULLUP PULLUP_DISABLE -#define GPIO_72_PULLUP PULLUP_DISABLE -#define GPIO_73_PULLUP PULLUP_DISABLE -#define GPIO_74_PULLUP PULLUP_DISABLE -#define GPIO_75_PULLUP PULLUP_DISABLE -#define GPIO_76_PULLUP PULLUP_DISABLE -#define GPIO_77_PULLUP PULLUP_DISABLE -#define GPIO_78_PULLUP PULLUP_DISABLE -#define GPIO_79_PULLUP PULLUP_DISABLE -#define GPIO_80_PULLUP PULLUP_DISABLE -#define GPIO_80_PULLUP PULLUP_DISABLE -#define GPIO_81_PULLUP PULLUP_DISABLE -#define GPIO_82_PULLUP PULLUP_DISABLE -#define GPIO_83_PULLUP PULLUP_DISABLE -#define GPIO_84_PULLUP PULLUP_DISABLE -#define GPIO_85_PULLUP PULLUP_DISABLE -#define GPIO_86_PULLUP PULLUP_DISABLE -#define GPIO_87_PULLUP PULLUP_DISABLE -#define GPIO_88_PULLUP PULLUP_DISABLE -#define GPIO_89_PULLUP PULLUP_DISABLE -#define GPIO_90_PULLUP PULLUP_DISABLE -#define GPIO_91_PULLUP PULLUP_DISABLE -#define GPIO_92_PULLUP PULLUP_DISABLE -#define GPIO_93_PULLUP PULLUP_DISABLE -#define GPIO_94_PULLUP PULLUP_DISABLE -#define GPIO_95_PULLUP PULLUP_DISABLE -#define GPIO_96_PULLUP PULLUP_DISABLE -#define GPIO_97_PULLUP PULLUP_DISABLE -#define GPIO_98_PULLUP PULLUP_DISABLE -#define GPIO_99_PULLUP PULLUP_DISABLE -#define GPIO_100_PULLUP PULLUP_DISABLE -#define GPIO_101_PULLUP PULLUP_DISABLE -#define GPIO_102_PULLUP PULLUP_DISABLE -#define GPIO_103_PULLUP PULLUP_DISABLE -#define GPIO_104_PULLUP PULLUP_DISABLE -#define GPIO_105_PULLUP PULLUP_DISABLE -#define GPIO_106_PULLUP PULLUP_DISABLE -#define GPIO_107_PULLUP PULLUP_DISABLE -#define GPIO_108_PULLUP PULLUP_DISABLE -#define GPIO_109_PULLUP PULLUP_DISABLE -#define GPIO_110_PULLUP PULLUP_DISABLE -#define GPIO_111_PULLUP PULLUP_DISABLE -#define GPIO_112_PULLUP PULLUP_DISABLE -#define GPIO_113_PULLUP PULLUP_DISABLE -#define GPIO_114_PULLUP PULLUP_DISABLE -#define GPIO_115_PULLUP PULLUP_DISABLE -#define GPIO_116_PULLUP PULLUP_DISABLE -#define GPIO_117_PULLUP PULLUP_DISABLE -#define GPIO_118_PULLUP PULLUP_ENABLE -#define GPIO_119_PULLUP PULLUP_DISABLE -#define GPIO_120_PULLUP PULLUP_DISABLE -#define GPIO_121_PULLUP PULLUP_DISABLE -#define GPIO_122_PULLUP PULLUP_DISABLE -#define GPIO_123_PULLUP PULLUP_DISABLE -#define GPIO_124_PULLUP PULLUP_DISABLE -#define GPIO_125_PULLUP PULLUP_DISABLE -#define GPIO_126_PULLUP PULLUP_DISABLE -#define GPIO_127_PULLUP PULLUP_DISABLE -#define GPIO_128_PULLUP PULLUP_DISABLE -#define GPIO_129_PULLUP PULLUP_DISABLE -#define GPIO_130_PULLUP PULLUP_DISABLE -#define GPIO_131_PULLUP PULLUP_DISABLE -#define GPIO_132_PULLUP PULLUP_DISABLE -#define GPIO_133_PULLUP PULLUP_DISABLE -#define GPIO_134_PULLUP PULLUP_DISABLE -#define GPIO_135_PULLUP PULLUP_DISABLE -#define GPIO_136_PULLUP PULLUP_DISABLE -#define GPIO_137_PULLUP PULLUP_DISABLE -#define GPIO_138_PULLUP PULLUP_DISABLE -#define GPIO_139_PULLUP PULLUP_DISABLE -#define GPIO_140_PULLUP PULLUP_DISABLE -#define GPIO_141_PULLUP PULLUP_DISABLE -#define GPIO_142_PULLUP PULLUP_DISABLE -#define GPIO_143_PULLUP PULLUP_DISABLE -#define GPIO_144_PULLUP PULLUP_DISABLE -#define GPIO_145_PULLUP PULLUP_DISABLE -#define GPIO_146_PULLUP PULLUP_DISABLE -#define GPIO_147_PULLUP PULLUP_DISABLE -#define GPIO_148_PULLUP PULLUP_DISABLE -#define GPIO_149_PULLUP PULLUP_DISABLE -#define GPIO_150_PULLUP PULLUP_DISABLE -#define GPIO_151_PULLUP PULLUP_DISABLE -#define GPIO_152_PULLUP PULLUP_DISABLE -#define GPIO_153_PULLUP PULLUP_DISABLE -#define GPIO_154_PULLUP PULLUP_DISABLE -#define GPIO_155_PULLUP PULLUP_DISABLE -#define GPIO_156_PULLUP PULLUP_DISABLE -#define GPIO_157_PULLUP PULLUP_DISABLE -#define GPIO_158_PULLUP PULLUP_DISABLE -#define GPIO_159_PULLUP PULLUP_DISABLE -#define GPIO_160_PULLUP PULLUP_DISABLE -#define GPIO_161_PULLUP PULLUP_DISABLE -#define GPIO_162_PULLUP PULLUP_DISABLE -#define GPIO_163_PULLUP PULLUP_DISABLE -#define GPIO_164_PULLUP PULLUP_DISABLE -#define GPIO_165_PULLUP PULLUP_DISABLE -#define GPIO_166_PULLUP PULLUP_DISABLE -#define GPIO_167_PULLUP PULLUP_DISABLE -#define GPIO_168_PULLUP PULLUP_DISABLE -#define GPIO_169_PULLUP PULLUP_DISABLE -#define GPIO_170_PULLUP PULLUP_DISABLE -#define GPIO_171_PULLUP PULLUP_DISABLE -#define GPIO_172_PULLUP PULLUP_DISABLE -#define GPIO_173_PULLUP PULLUP_DISABLE -#define GPIO_174_PULLUP PULLUP_DISABLE -#define GPIO_175_PULLUP PULLUP_DISABLE -#define GPIO_176_PULLUP PULLUP_DISABLE -#define GPIO_177_PULLUP PULLUP_DISABLE -#define GPIO_178_PULLUP PULLUP_DISABLE -#define GPIO_179_PULLUP PULLUP_DISABLE -#define GPIO_180_PULLUP PULLUP_DISABLE -#define GPIO_180_PULLUP PULLUP_DISABLE -#define GPIO_181_PULLUP PULLUP_DISABLE -#define GPIO_182_PULLUP PULLUP_DISABLE -#define GPIO_183_PULLUP PULLUP_DISABLE -#define GPIO_184_PULLUP PULLUP_DISABLE -#define GPIO_185_PULLUP PULLUP_DISABLE -#define GPIO_186_PULLUP PULLUP_DISABLE -#define GPIO_187_PULLUP PULLUP_DISABLE -#define GPIO_188_PULLUP PULLUP_DISABLE -#define GPIO_189_PULLUP PULLUP_DISABLE -#define GPIO_190_PULLUP PULLUP_DISABLE -#define GPIO_191_PULLUP PULLUP_DISABLE -#define GPIO_192_PULLUP PULLUP_DISABLE -#define GPIO_193_PULLUP PULLUP_DISABLE -#define GPIO_194_PULLUP PULLUP_DISABLE -#define GPIO_195_PULLUP PULLUP_DISABLE -#define GPIO_196_PULLUP PULLUP_DISABLE -#define GPIO_197_PULLUP PULLUP_DISABLE -#define GPIO_198_PULLUP PULLUP_DISABLE -#define GPIO_199_PULLUP PULLUP_DISABLE -#define GPIO_200_PULLUP PULLUP_DISABLE -#define GPIO_201_PULLUP PULLUP_DISABLE -#define GPIO_202_PULLUP PULLUP_DISABLE -#define GPIO_203_PULLUP PULLUP_DISABLE -#define GPIO_204_PULLUP PULLUP_DISABLE -#define GPIO_205_PULLUP PULLUP_DISABLE -#define GPIO_206_PULLUP PULLUP_DISABLE -#define GPIO_207_PULLUP PULLUP_DISABLE -#define GPIO_208_PULLUP PULLUP_DISABLE -#define GPIO_209_PULLUP PULLUP_DISABLE -#define GPIO_210_PULLUP PULLUP_DISABLE -#define GPIO_211_PULLUP PULLUP_DISABLE -#define GPIO_212_PULLUP PULLUP_DISABLE -#define GPIO_213_PULLUP PULLUP_DISABLE -#define GPIO_214_PULLUP PULLUP_DISABLE -#define GPIO_215_PULLUP PULLUP_DISABLE -#define GPIO_216_PULLUP PULLUP_DISABLE -#define GPIO_217_PULLUP PULLUP_DISABLE -#define GPIO_218_PULLUP PULLUP_DISABLE -#define GPIO_219_PULLUP PULLUP_DISABLE -#define GPIO_220_PULLUP PULLUP_DISABLE -#define GPIO_221_PULLUP PULLUP_DISABLE -#define GPIO_222_PULLUP PULLUP_DISABLE -#define GPIO_223_PULLUP PULLUP_DISABLE -#define GPIO_224_PULLUP PULLUP_DISABLE -#define GPIO_225_PULLUP PULLUP_DISABLE -#define GPIO_226_PULLUP PULLUP_DISABLE -#define GPIO_227_PULLUP PULLUP_DISABLE -#define GPIO_228_PULLUP PULLUP_DISABLE -#define GPIO_229_PULLUP PULLUP_DISABLE - -#define PULLDOWN_ENABLE (1 << 4) -#define PULLDOWN_DISABLE (0 << 4) - -#define GPIO_00_PULLDOWN PULLDOWN_DISABLE -#define GPIO_01_PULLDOWN PULLDOWN_DISABLE -#define GPIO_02_PULLDOWN PULLDOWN_DISABLE -#define GPIO_03_PULLDOWN PULLDOWN_DISABLE -#define GPIO_04_PULLDOWN PULLDOWN_DISABLE -#define GPIO_05_PULLDOWN PULLDOWN_DISABLE -#define GPIO_06_PULLDOWN PULLDOWN_DISABLE -#define GPIO_07_PULLDOWN PULLDOWN_DISABLE -#define GPIO_08_PULLDOWN PULLDOWN_DISABLE -#define GPIO_09_PULLDOWN PULLDOWN_DISABLE -#define GPIO_10_PULLDOWN PULLDOWN_DISABLE -#define GPIO_11_PULLDOWN PULLDOWN_DISABLE -#define GPIO_12_PULLDOWN PULLDOWN_DISABLE -#define GPIO_13_PULLDOWN PULLDOWN_DISABLE -#define GPIO_14_PULLDOWN PULLDOWN_DISABLE -#define GPIO_15_PULLDOWN PULLDOWN_DISABLE -#define GPIO_16_PULLDOWN PULLDOWN_DISABLE -#define GPIO_17_PULLDOWN PULLDOWN_DISABLE -#define GPIO_18_PULLDOWN PULLDOWN_DISABLE -#define GPIO_19_PULLDOWN PULLDOWN_DISABLE -#define GPIO_20_PULLDOWN PULLDOWN_DISABLE -#define GPIO_21_PULLDOWN PULLDOWN_DISABLE -#define GPIO_22_PULLDOWN PULLDOWN_DISABLE -#define GPIO_23_PULLDOWN PULLDOWN_DISABLE -#define GPIO_24_PULLDOWN PULLDOWN_DISABLE -#define GPIO_25_PULLDOWN PULLDOWN_DISABLE -#define GPIO_26_PULLDOWN PULLDOWN_DISABLE -#define GPIO_27_PULLDOWN PULLDOWN_DISABLE -#define GPIO_28_PULLDOWN PULLDOWN_DISABLE -#define GPIO_29_PULLDOWN PULLDOWN_DISABLE -#define GPIO_30_PULLDOWN PULLDOWN_DISABLE -#define GPIO_31_PULLDOWN PULLDOWN_DISABLE -#define GPIO_32_PULLDOWN PULLDOWN_DISABLE -#define GPIO_33_PULLDOWN PULLDOWN_DISABLE -#define GPIO_34_PULLDOWN PULLDOWN_DISABLE -#define GPIO_35_PULLDOWN PULLDOWN_DISABLE -#define GPIO_36_PULLDOWN PULLDOWN_DISABLE -#define GPIO_37_PULLDOWN PULLDOWN_DISABLE -#define GPIO_38_PULLDOWN PULLDOWN_DISABLE -#define GPIO_39_PULLDOWN PULLDOWN_DISABLE -#define GPIO_40_PULLDOWN PULLDOWN_DISABLE -#define GPIO_41_PULLDOWN PULLDOWN_DISABLE -#define GPIO_42_PULLDOWN PULLDOWN_DISABLE -#define GPIO_43_PULLDOWN PULLDOWN_DISABLE -#define GPIO_44_PULLDOWN PULLDOWN_DISABLE -#define GPIO_45_PULLDOWN PULLDOWN_DISABLE -#define GPIO_46_PULLDOWN PULLDOWN_DISABLE -#define GPIO_47_PULLDOWN PULLDOWN_DISABLE -#define GPIO_48_PULLDOWN PULLDOWN_DISABLE -#define GPIO_49_PULLDOWN PULLDOWN_DISABLE -#define GPIO_50_PULLDOWN PULLDOWN_DISABLE -#define GPIO_51_PULLDOWN PULLDOWN_DISABLE -#define GPIO_52_PULLDOWN PULLDOWN_DISABLE -#define GPIO_53_PULLDOWN PULLDOWN_DISABLE -#define GPIO_54_PULLDOWN PULLDOWN_DISABLE -#define GPIO_55_PULLDOWN PULLDOWN_DISABLE -#define GPIO_56_PULLDOWN PULLDOWN_DISABLE -#define GPIO_57_PULLDOWN PULLDOWN_DISABLE -#define GPIO_58_PULLDOWN PULLDOWN_DISABLE -#define GPIO_59_PULLDOWN PULLDOWN_DISABLE -#define GPIO_60_PULLDOWN PULLDOWN_DISABLE -#define GPIO_61_PULLDOWN PULLDOWN_DISABLE -#define GPIO_62_PULLDOWN PULLDOWN_DISABLE -#define GPIO_63_PULLDOWN PULLDOWN_DISABLE -#define GPIO_64_PULLDOWN PULLDOWN_DISABLE -#define GPIO_65_PULLDOWN PULLDOWN_DISABLE -#define GPIO_66_PULLDOWN PULLDOWN_DISABLE -#define GPIO_67_PULLDOWN PULLDOWN_DISABLE -#define GPIO_68_PULLDOWN PULLDOWN_DISABLE -#define GPIO_69_PULLDOWN PULLDOWN_DISABLE -#define GPIO_70_PULLDOWN PULLDOWN_DISABLE -#define GPIO_71_PULLDOWN PULLDOWN_DISABLE -#define GPIO_72_PULLDOWN PULLDOWN_DISABLE -#define GPIO_73_PULLDOWN PULLDOWN_DISABLE -#define GPIO_74_PULLDOWN PULLDOWN_DISABLE -#define GPIO_75_PULLDOWN PULLDOWN_DISABLE -#define GPIO_76_PULLDOWN PULLDOWN_DISABLE -#define GPIO_77_PULLDOWN PULLDOWN_DISABLE -#define GPIO_78_PULLDOWN PULLDOWN_DISABLE -#define GPIO_79_PULLDOWN PULLDOWN_DISABLE -#define GPIO_80_PULLDOWN PULLDOWN_DISABLE -#define GPIO_80_PULLDOWN PULLDOWN_DISABLE -#define GPIO_81_PULLDOWN PULLDOWN_DISABLE -#define GPIO_82_PULLDOWN PULLDOWN_DISABLE -#define GPIO_83_PULLDOWN PULLDOWN_DISABLE -#define GPIO_84_PULLDOWN PULLDOWN_DISABLE -#define GPIO_85_PULLDOWN PULLDOWN_DISABLE -#define GPIO_86_PULLDOWN PULLDOWN_DISABLE -#define GPIO_87_PULLDOWN PULLDOWN_DISABLE -#define GPIO_88_PULLDOWN PULLDOWN_DISABLE -#define GPIO_89_PULLDOWN PULLDOWN_DISABLE -#define GPIO_90_PULLDOWN PULLDOWN_DISABLE -#define GPIO_91_PULLDOWN PULLDOWN_DISABLE -#define GPIO_92_PULLDOWN PULLDOWN_DISABLE -#define GPIO_93_PULLDOWN PULLDOWN_DISABLE -#define GPIO_94_PULLDOWN PULLDOWN_DISABLE -#define GPIO_95_PULLDOWN PULLDOWN_DISABLE -#define GPIO_96_PULLDOWN PULLDOWN_DISABLE -#define GPIO_97_PULLDOWN PULLDOWN_DISABLE -#define GPIO_98_PULLDOWN PULLDOWN_DISABLE -#define GPIO_99_PULLDOWN PULLDOWN_DISABLE -#define GPIO_100_PULLDOWN PULLDOWN_DISABLE -#define GPIO_101_PULLDOWN PULLDOWN_DISABLE -#define GPIO_102_PULLDOWN PULLDOWN_DISABLE -#define GPIO_103_PULLDOWN PULLDOWN_DISABLE -#define GPIO_104_PULLDOWN PULLDOWN_DISABLE -#define GPIO_105_PULLDOWN PULLDOWN_DISABLE -#define GPIO_106_PULLDOWN PULLDOWN_DISABLE -#define GPIO_107_PULLDOWN PULLDOWN_DISABLE -#define GPIO_108_PULLDOWN PULLDOWN_DISABLE -#define GPIO_109_PULLDOWN PULLDOWN_DISABLE -#define GPIO_110_PULLDOWN PULLDOWN_DISABLE -#define GPIO_111_PULLDOWN PULLDOWN_DISABLE -#define GPIO_112_PULLDOWN PULLDOWN_DISABLE -#define GPIO_113_PULLDOWN PULLDOWN_DISABLE -#define GPIO_114_PULLDOWN PULLDOWN_DISABLE -#define GPIO_115_PULLDOWN PULLDOWN_DISABLE -#define GPIO_116_PULLDOWN PULLDOWN_DISABLE -#define GPIO_117_PULLDOWN PULLDOWN_DISABLE -#define GPIO_118_PULLDOWN PULLDOWN_DISABLE -#define GPIO_119_PULLDOWN PULLDOWN_DISABLE -#define GPIO_120_PULLDOWN PULLDOWN_DISABLE -#define GPIO_121_PULLDOWN PULLDOWN_DISABLE -#define GPIO_122_PULLDOWN PULLDOWN_DISABLE -#define GPIO_123_PULLDOWN PULLDOWN_DISABLE -#define GPIO_124_PULLDOWN PULLDOWN_DISABLE -#define GPIO_125_PULLDOWN PULLDOWN_DISABLE -#define GPIO_126_PULLDOWN PULLDOWN_DISABLE -#define GPIO_127_PULLDOWN PULLDOWN_DISABLE -#define GPIO_128_PULLDOWN PULLDOWN_DISABLE -#define GPIO_129_PULLDOWN PULLDOWN_DISABLE -#define GPIO_130_PULLDOWN PULLDOWN_DISABLE -#define GPIO_131_PULLDOWN PULLDOWN_DISABLE -#define GPIO_132_PULLDOWN PULLDOWN_DISABLE -#define GPIO_133_PULLDOWN PULLDOWN_DISABLE -#define GPIO_134_PULLDOWN PULLDOWN_DISABLE -#define GPIO_135_PULLDOWN PULLDOWN_DISABLE -#define GPIO_136_PULLDOWN PULLDOWN_DISABLE -#define GPIO_137_PULLDOWN PULLDOWN_DISABLE -#define GPIO_138_PULLDOWN PULLDOWN_DISABLE -#define GPIO_139_PULLDOWN PULLDOWN_DISABLE -#define GPIO_140_PULLDOWN PULLDOWN_DISABLE -#define GPIO_141_PULLDOWN PULLDOWN_DISABLE -#define GPIO_142_PULLDOWN PULLDOWN_DISABLE -#define GPIO_143_PULLDOWN PULLDOWN_DISABLE -#define GPIO_144_PULLDOWN PULLDOWN_DISABLE -#define GPIO_145_PULLDOWN PULLDOWN_DISABLE -#define GPIO_146_PULLDOWN PULLDOWN_DISABLE -#define GPIO_147_PULLDOWN PULLDOWN_DISABLE -#define GPIO_148_PULLDOWN PULLDOWN_DISABLE -#define GPIO_149_PULLDOWN PULLDOWN_DISABLE -#define GPIO_150_PULLDOWN PULLDOWN_DISABLE -#define GPIO_151_PULLDOWN PULLDOWN_DISABLE -#define GPIO_152_PULLDOWN PULLDOWN_DISABLE -#define GPIO_153_PULLDOWN PULLDOWN_DISABLE -#define GPIO_154_PULLDOWN PULLDOWN_DISABLE -#define GPIO_155_PULLDOWN PULLDOWN_DISABLE -#define GPIO_156_PULLDOWN PULLDOWN_DISABLE -#define GPIO_157_PULLDOWN PULLDOWN_DISABLE -#define GPIO_158_PULLDOWN PULLDOWN_DISABLE -#define GPIO_159_PULLDOWN PULLDOWN_DISABLE -#define GPIO_160_PULLDOWN PULLDOWN_DISABLE -#define GPIO_161_PULLDOWN PULLDOWN_DISABLE -#define GPIO_162_PULLDOWN PULLDOWN_ENABLE -#define GPIO_163_PULLDOWN PULLDOWN_ENABLE -#define GPIO_164_PULLDOWN PULLDOWN_ENABLE -#define GPIO_165_PULLDOWN PULLDOWN_DISABLE -#define GPIO_166_PULLDOWN PULLDOWN_DISABLE -#define GPIO_167_PULLDOWN PULLDOWN_ENABLE -#define GPIO_168_PULLDOWN PULLDOWN_DISABLE -#define GPIO_169_PULLDOWN PULLDOWN_DISABLE -#define GPIO_170_PULLDOWN PULLDOWN_DISABLE -#define GPIO_171_PULLDOWN PULLDOWN_DISABLE -#define GPIO_172_PULLDOWN PULLDOWN_DISABLE -#define GPIO_173_PULLDOWN PULLDOWN_DISABLE -#define GPIO_174_PULLDOWN PULLDOWN_DISABLE -#define GPIO_175_PULLDOWN PULLDOWN_DISABLE -#define GPIO_176_PULLDOWN PULLDOWN_DISABLE -#define GPIO_177_PULLDOWN PULLDOWN_DISABLE -#define GPIO_178_PULLDOWN PULLDOWN_DISABLE -#define GPIO_179_PULLDOWN PULLDOWN_DISABLE -#define GPIO_180_PULLDOWN PULLDOWN_DISABLE -#define GPIO_180_PULLDOWN PULLDOWN_DISABLE -#define GPIO_181_PULLDOWN PULLDOWN_DISABLE -#define GPIO_182_PULLDOWN PULLDOWN_DISABLE -#define GPIO_183_PULLDOWN PULLDOWN_DISABLE -#define GPIO_184_PULLDOWN PULLDOWN_DISABLE -#define GPIO_185_PULLDOWN PULLDOWN_ENABLE -#define GPIO_186_PULLDOWN PULLDOWN_ENABLE -#define GPIO_187_PULLDOWN PULLDOWN_DISABLE -#define GPIO_188_PULLDOWN PULLDOWN_DISABLE -#define GPIO_189_PULLDOWN PULLDOWN_DISABLE -#define GPIO_190_PULLDOWN PULLDOWN_DISABLE -#define GPIO_191_PULLDOWN PULLDOWN_DISABLE -#define GPIO_192_PULLDOWN PULLDOWN_DISABLE -#define GPIO_193_PULLDOWN PULLDOWN_DISABLE -#define GPIO_194_PULLDOWN PULLDOWN_DISABLE -#define GPIO_195_PULLDOWN PULLDOWN_DISABLE -#define GPIO_196_PULLDOWN PULLDOWN_DISABLE -#define GPIO_197_PULLDOWN PULLDOWN_DISABLE -#define GPIO_198_PULLDOWN PULLDOWN_DISABLE -#define GPIO_199_PULLDOWN PULLDOWN_DISABLE -#define GPIO_200_PULLDOWN PULLDOWN_DISABLE -#define GPIO_201_PULLDOWN PULLDOWN_DISABLE -#define GPIO_202_PULLDOWN PULLDOWN_DISABLE -#define GPIO_203_PULLDOWN PULLDOWN_DISABLE -#define GPIO_204_PULLDOWN PULLDOWN_DISABLE -#define GPIO_205_PULLDOWN PULLDOWN_DISABLE -#define GPIO_206_PULLDOWN PULLDOWN_DISABLE -#define GPIO_207_PULLDOWN PULLDOWN_DISABLE -#define GPIO_208_PULLDOWN PULLDOWN_DISABLE -#define GPIO_209_PULLDOWN PULLDOWN_DISABLE -#define GPIO_210_PULLDOWN PULLDOWN_DISABLE -#define GPIO_211_PULLDOWN PULLDOWN_DISABLE -#define GPIO_212_PULLDOWN PULLDOWN_DISABLE -#define GPIO_213_PULLDOWN PULLDOWN_DISABLE -#define GPIO_214_PULLDOWN PULLDOWN_DISABLE -#define GPIO_215_PULLDOWN PULLDOWN_DISABLE -#define GPIO_216_PULLDOWN PULLDOWN_DISABLE -#define GPIO_217_PULLDOWN PULLDOWN_DISABLE -#define GPIO_218_PULLDOWN PULLDOWN_DISABLE -#define GPIO_219_PULLDOWN PULLDOWN_DISABLE -#define GPIO_220_PULLDOWN PULLDOWN_DISABLE -#define GPIO_221_PULLDOWN PULLDOWN_DISABLE -#define GPIO_222_PULLDOWN PULLDOWN_DISABLE -#define GPIO_223_PULLDOWN PULLDOWN_DISABLE -#define GPIO_224_PULLDOWN PULLDOWN_DISABLE -#define GPIO_225_PULLDOWN PULLDOWN_DISABLE -#define GPIO_226_PULLDOWN PULLDOWN_DISABLE -#define GPIO_227_PULLDOWN PULLDOWN_DISABLE -#define GPIO_228_PULLDOWN PULLDOWN_DISABLE -#define GPIO_229_PULLDOWN PULLDOWN_DISABLE - -#define EVENT_DISABLE 0 -#define EVENT_ENABLE 1 - -#define GEVENT_00_EVENTENABLE EVENT_DISABLE -#define GEVENT_01_EVENTENABLE EVENT_DISABLE -#define GEVENT_02_EVENTENABLE EVENT_ENABLE // APU THERMTRIP# -#define GEVENT_03_EVENTENABLE EVENT_ENABLE // EC_SCI# -#define GEVENT_04_EVENTENABLE EVENT_ENABLE // APU_MEMHOT# -#define GEVENT_05_EVENTENABLE EVENT_ENABLE // PCIE_EXPCARD_PWREN# -#define GEVENT_06_EVENTENABLE EVENT_DISABLE -#define GEVENT_07_EVENTENABLE EVENT_DISABLE -#define GEVENT_08_EVENTENABLE EVENT_DISABLE -#define GEVENT_09_EVENTENABLE EVENT_ENABLE // WF_RADIO -#define GEVENT_10_EVENTENABLE EVENT_DISABLE -#define GEVENT_11_EVENTENABLE EVENT_DISABLE -#define GEVENT_12_EVENTENABLE EVENT_ENABLE // SMBALERT# -#define GEVENT_13_EVENTENABLE EVENT_DISABLE -#define GEVENT_14_EVENTENABLE EVENT_ENABLE // LASSO_DET#/DOCK# -#define GEVENT_15_EVENTENABLE EVENT_ENABLE // ODD_PLUGIN# -#define GEVENT_16_EVENTENABLE EVENT_ENABLE // ODD_DA -#define GEVENT_17_EVENTENABLE EVENT_ENABLE // TWARN -#define GEVENT_18_EVENTENABLE EVENT_DISABLE -#define GEVENT_19_EVENTENABLE EVENT_DISABLE -#define GEVENT_20_EVENTENABLE EVENT_DISABLE -#define GEVENT_21_EVENTENABLE EVENT_DISABLE -#define GEVENT_22_EVENTENABLE EVENT_ENABLE // LID_CLOSE# -#define GEVENT_23_EVENTENABLE EVENT_DISABLE // EC_SMI# - -#define SCITRIG_LOW 0 -#define SCITRIG_HI 1 - -#define GEVENT_00_SCITRIG SCITRIG_LOW -#define GEVENT_01_SCITRIG SCITRIG_LOW -#define GEVENT_02_SCITRIG SCITRIG_LOW -#define GEVENT_03_SCITRIG SCITRIG_LOW -#define GEVENT_04_SCITRIG SCITRIG_LOW -#define GEVENT_05_SCITRIG SCITRIG_LOW -#define GEVENT_06_SCITRIG SCITRIG_LOW -#define GEVENT_07_SCITRIG SCITRIG_LOW -#define GEVENT_08_SCITRIG SCITRIG_LOW -#define GEVENT_09_SCITRIG SCITRIG_LOW -#define GEVENT_10_SCITRIG SCITRIG_LOW -#define GEVENT_11_SCITRIG SCITRIG_LOW -#define GEVENT_12_SCITRIG SCITRIG_LOW -#define GEVENT_13_SCITRIG SCITRIG_LOW -#define GEVENT_14_SCITRIG SCITRIG_LOW -#define GEVENT_15_SCITRIG SCITRIG_LOW -#define GEVENT_16_SCITRIG SCITRIG_LOW -#define GEVENT_17_SCITRIG SCITRIG_HI -#define GEVENT_18_SCITRIG SCITRIG_LOW -#define GEVENT_19_SCITRIG SCITRIG_LOW -#define GEVENT_20_SCITRIG SCITRIG_LOW -#define GEVENT_21_SCITRIG SCITRIG_LOW -#define GEVENT_22_SCITRIG SCITRIG_LOW -#define GEVENT_23_SCITRIG SCITRIG_LOW - -#define SCILEVEL_EDGE 0 -#define SCILEVEL_LEVEL 1 - -#define GEVENT_00_SCILEVEL SCILEVEL_EDGE -#define GEVENT_01_SCILEVEL SCILEVEL_EDGE -#define GEVENT_02_SCILEVEL SCILEVEL_EDGE -#define GEVENT_03_SCILEVEL SCILEVEL_EDGE -#define GEVENT_04_SCILEVEL SCILEVEL_EDGE -#define GEVENT_05_SCILEVEL SCILEVEL_EDGE -#define GEVENT_06_SCILEVEL SCILEVEL_EDGE -#define GEVENT_07_SCILEVEL SCILEVEL_EDGE -#define GEVENT_08_SCILEVEL SCILEVEL_EDGE -#define GEVENT_09_SCILEVEL SCILEVEL_EDGE -#define GEVENT_10_SCILEVEL SCILEVEL_EDGE -#define GEVENT_11_SCILEVEL SCILEVEL_EDGE -#define GEVENT_12_SCILEVEL SCILEVEL_EDGE -#define GEVENT_13_SCILEVEL SCILEVEL_EDGE -#define GEVENT_14_SCILEVEL SCILEVEL_EDGE -#define GEVENT_15_SCILEVEL SCILEVEL_EDGE -#define GEVENT_16_SCILEVEL SCILEVEL_EDGE -#define GEVENT_17_SCILEVEL SCILEVEL_EDGE -#define GEVENT_18_SCILEVEL SCILEVEL_EDGE -#define GEVENT_19_SCILEVEL SCILEVEL_EDGE -#define GEVENT_20_SCILEVEL SCILEVEL_EDGE -#define GEVENT_21_SCILEVEL SCILEVEL_EDGE -#define GEVENT_22_SCILEVEL SCILEVEL_EDGE -#define GEVENT_23_SCILEVEL SCILEVEL_EDGE - -#define SMISCI_DISABLE 0 -#define SMISCI_ENABLE 1 - -#define GEVENT_00_SMISCIEN SMISCI_DISABLE -#define GEVENT_01_SMISCIEN SMISCI_DISABLE -#define GEVENT_02_SMISCIEN SMISCI_DISABLE -#define GEVENT_03_SMISCIEN SMISCI_DISABLE -#define GEVENT_04_SMISCIEN SMISCI_DISABLE -#define GEVENT_05_SMISCIEN SMISCI_DISABLE -#define GEVENT_06_SMISCIEN SMISCI_DISABLE -#define GEVENT_07_SMISCIEN SMISCI_DISABLE -#define GEVENT_08_SMISCIEN SMISCI_DISABLE -#define GEVENT_09_SMISCIEN SMISCI_DISABLE -#define GEVENT_10_SMISCIEN SMISCI_DISABLE -#define GEVENT_11_SMISCIEN SMISCI_DISABLE -#define GEVENT_12_SMISCIEN SMISCI_DISABLE -#define GEVENT_13_SMISCIEN SMISCI_DISABLE -#define GEVENT_14_SMISCIEN SMISCI_DISABLE -#define GEVENT_15_SMISCIEN SMISCI_DISABLE -#define GEVENT_16_SMISCIEN SMISCI_DISABLE -#define GEVENT_17_SMISCIEN SMISCI_DISABLE -#define GEVENT_18_SMISCIEN SMISCI_DISABLE -#define GEVENT_19_SMISCIEN SMISCI_DISABLE -#define GEVENT_20_SMISCIEN SMISCI_DISABLE -#define GEVENT_21_SMISCIEN SMISCI_DISABLE -#define GEVENT_22_SMISCIEN SMISCI_DISABLE -#define GEVENT_23_SMISCIEN SMISCI_DISABLE - -#define SCIS0_DISABLE 0 -#define SCIS0_ENABLE 1 - -#define GEVENT_00_SCIS0EN SCIS0_DISABLE -#define GEVENT_01_SCIS0EN SCIS0_DISABLE -#define GEVENT_02_SCIS0EN SCIS0_DISABLE -#define GEVENT_03_SCIS0EN SCIS0_DISABLE -#define GEVENT_04_SCIS0EN SCIS0_DISABLE -#define GEVENT_05_SCIS0EN SCIS0_DISABLE -#define GEVENT_06_SCIS0EN SCIS0_DISABLE -#define GEVENT_07_SCIS0EN SCIS0_DISABLE -#define GEVENT_08_SCIS0EN SCIS0_DISABLE -#define GEVENT_09_SCIS0EN SCIS0_DISABLE -#define GEVENT_10_SCIS0EN SCIS0_DISABLE -#define GEVENT_11_SCIS0EN SCIS0_DISABLE -#define GEVENT_12_SCIS0EN SCIS0_DISABLE -#define GEVENT_13_SCIS0EN SCIS0_DISABLE -#define GEVENT_14_SCIS0EN SCIS0_DISABLE -#define GEVENT_15_SCIS0EN SCIS0_DISABLE -#define GEVENT_16_SCIS0EN SCIS0_DISABLE -#define GEVENT_17_SCIS0EN SCIS0_DISABLE -#define GEVENT_18_SCIS0EN SCIS0_DISABLE -#define GEVENT_19_SCIS0EN SCIS0_DISABLE -#define GEVENT_20_SCIS0EN SCIS0_DISABLE -#define GEVENT_21_SCIS0EN SCIS0_DISABLE -#define GEVENT_22_SCIS0EN SCIS0_DISABLE -#define GEVENT_23_SCIS0EN SCIS0_DISABLE - -#define GEVENT_SCIMASK 0x1F -#define GEVENT_00_SCIMAP 0 -#define GEVENT_01_SCIMAP 1 -#define GEVENT_02_SCIMAP 2 -#define GEVENT_03_SCIMAP 3 -#define GEVENT_04_SCIMAP 4 -#define GEVENT_05_SCIMAP 5 -#define GEVENT_06_SCIMAP 6 -#define GEVENT_07_SCIMAP 7 -#define GEVENT_08_SCIMAP 8 -#define GEVENT_09_SCIMAP 9 -#define GEVENT_10_SCIMAP 10 -#define GEVENT_11_SCIMAP 11 -#define GEVENT_12_SCIMAP 12 -#define GEVENT_13_SCIMAP 13 -#define GEVENT_14_SCIMAP 14 -#define GEVENT_15_SCIMAP 15 -#define GEVENT_16_SCIMAP 16 -#define GEVENT_17_SCIMAP 17 -#define GEVENT_18_SCIMAP 18 -#define GEVENT_19_SCIMAP 19 -#define GEVENT_20_SCIMAP 20 -#define GEVENT_21_SCIMAP 21 -#define GEVENT_22_SCIMAP 22 -#define GEVENT_23_SCIMAP 23 - -#define SMITRIG_LOW 0 -#define SMITRIG_HI 1 - -#define GEVENT_00_SMITRIG SMITRIG_HI -#define GEVENT_01_SMITRIG SMITRIG_HI -#define GEVENT_02_SMITRIG SMITRIG_HI -#define GEVENT_03_SMITRIG SMITRIG_HI -#define GEVENT_04_SMITRIG SMITRIG_HI -#define GEVENT_05_SMITRIG SMITRIG_HI -#define GEVENT_06_SMITRIG SMITRIG_HI -#define GEVENT_07_SMITRIG SMITRIG_HI -#define GEVENT_08_SMITRIG SMITRIG_HI -#define GEVENT_09_SMITRIG SMITRIG_HI -#define GEVENT_10_SMITRIG SMITRIG_HI -#define GEVENT_11_SMITRIG SMITRIG_HI -#define GEVENT_12_SMITRIG SMITRIG_HI -#define GEVENT_13_SMITRIG SMITRIG_HI -#define GEVENT_14_SMITRIG SMITRIG_HI -#define GEVENT_15_SMITRIG SMITRIG_HI -#define GEVENT_16_SMITRIG SMITRIG_HI -#define GEVENT_17_SMITRIG SMITRIG_HI -#define GEVENT_18_SMITRIG SMITRIG_HI -#define GEVENT_19_SMITRIG SMITRIG_HI -#define GEVENT_20_SMITRIG SMITRIG_HI -#define GEVENT_21_SMITRIG SMITRIG_HI -#define GEVENT_22_SMITRIG SMITRIG_HI -#define GEVENT_23_SMITRIG SMITRIG_HI - -#define SMICONTROL_MASK 3 -#define SMICONTROL_DISABLE 0 -#define SMICONTROL_SMI 1 -#define SMICONTROL_NMI 2 -#define SMICONTROL_IRQ13 3 - -#define GEVENT_00_SMICONTROL SMICONTROL_DISABLE -#define GEVENT_01_SMICONTROL SMICONTROL_DISABLE -#define GEVENT_02_SMICONTROL SMICONTROL_DISABLE -#define GEVENT_03_SMICONTROL SMICONTROL_DISABLE -#define GEVENT_04_SMICONTROL SMICONTROL_DISABLE -#define GEVENT_05_SMICONTROL SMICONTROL_DISABLE -#define GEVENT_06_SMICONTROL SMICONTROL_DISABLE -#define GEVENT_07_SMICONTROL SMICONTROL_DISABLE -#define GEVENT_08_SMICONTROL SMICONTROL_DISABLE -#define GEVENT_09_SMICONTROL SMICONTROL_DISABLE -#define GEVENT_10_SMICONTROL SMICONTROL_DISABLE -#define GEVENT_11_SMICONTROL SMICONTROL_DISABLE -#define GEVENT_12_SMICONTROL SMICONTROL_DISABLE -#define GEVENT_13_SMICONTROL SMICONTROL_DISABLE -#define GEVENT_14_SMICONTROL SMICONTROL_DISABLE -#define GEVENT_15_SMICONTROL SMICONTROL_DISABLE -#define GEVENT_16_SMICONTROL SMICONTROL_DISABLE -#define GEVENT_17_SMICONTROL SMICONTROL_DISABLE -#define GEVENT_18_SMICONTROL SMICONTROL_DISABLE -#define GEVENT_19_SMICONTROL SMICONTROL_DISABLE -#define GEVENT_20_SMICONTROL SMICONTROL_DISABLE -#define GEVENT_21_SMICONTROL SMICONTROL_DISABLE -#define GEVENT_22_SMICONTROL SMICONTROL_DISABLE -#define GEVENT_23_SMICONTROL SMICONTROL_DISABLE - -#define GPIO_RSVD_ZONE0_S GPIO_81 -#define GPIO_RSVD_ZONE0_E GPIO_95 -#define GPIO_RSVD_ZONE1_S GPIO_120 -#define GPIO_RSVD_ZONE1_E GPIO_127 - -typedef enum _GPIO_COUNT -{ - GPIO_00 = 0, - GPIO_01, - GPIO_02, - GPIO_03, - GPIO_04, - GPIO_05, - GPIO_06, - GPIO_07, - GPIO_08, - GPIO_09, - GPIO_10, - GPIO_11, - GPIO_12, - GPIO_13, - GPIO_14, - GPIO_15, - GPIO_16, - GPIO_17, - GPIO_18, - GPIO_19, - GPIO_20, - GPIO_21, - GPIO_22, - GPIO_23, - GPIO_24, - GPIO_25, - GPIO_26, - GPIO_27, - GPIO_28, - GPIO_29, - GPIO_30, - GPIO_31, - GPIO_32, - GPIO_33, - GPIO_34, - GPIO_35, - GPIO_36, - GPIO_37, - GPIO_38, - GPIO_39, - GPIO_40, - GPIO_41, - GPIO_42, - GPIO_43, - GPIO_44, - GPIO_45, - GPIO_46, - GPIO_47, - GPIO_48, - GPIO_49, - GPIO_50, - GPIO_51, - GPIO_52, - GPIO_53, - GPIO_54, - GPIO_55, - GPIO_56, - GPIO_57, - GPIO_58, - GPIO_59, - GPIO_60, - GPIO_61, - GPIO_62, - GPIO_63, - GPIO_64, - GPIO_65, - GPIO_66, - GPIO_67, - GPIO_68, - GPIO_69, - GPIO_70, - GPIO_71, - GPIO_72, - GPIO_73, - GPIO_74, - GPIO_75, - GPIO_76, - GPIO_77, - GPIO_78, - GPIO_79, - GPIO_80, - GPIO_81, - GPIO_82, - GPIO_83, - GPIO_84, - GPIO_85, - GPIO_86, - GPIO_87, - GPIO_88, - GPIO_89, - GPIO_90, - GPIO_91, - GPIO_92, - GPIO_93, - GPIO_94, - GPIO_95, - GPIO_96, - GPIO_97, - GPIO_98, - GPIO_99, - GPIO_100, - GPIO_101, - GPIO_102, - GPIO_103, - GPIO_104, - GPIO_105, - GPIO_106, - GPIO_107, - GPIO_108, - GPIO_109, - GPIO_110, - GPIO_111, - GPIO_112, - GPIO_113, - GPIO_114, - GPIO_115, - GPIO_116, - GPIO_117, - GPIO_118, - GPIO_119, - GPIO_120, - GPIO_121, - GPIO_122, - GPIO_123, - GPIO_124, - GPIO_125, - GPIO_126, - GPIO_127, - GPIO_128, - GPIO_129, - GPIO_130, - GPIO_131, - GPIO_132, - GPIO_133, - GPIO_134, - GPIO_135, - GPIO_136, - GPIO_137, - GPIO_138, - GPIO_139, - GPIO_140, - GPIO_141, - GPIO_142, - GPIO_143, - GPIO_144, - GPIO_145, - GPIO_146, - GPIO_147, - GPIO_148, - GPIO_149, - GPIO_150, - GPIO_151, - GPIO_152, - GPIO_153, - GPIO_154, - GPIO_155, - GPIO_156, - GPIO_157, - GPIO_158, - GPIO_159, - GPIO_160, - GPIO_161, - GPIO_162, - GPIO_163, - GPIO_164, - GPIO_165, - GPIO_166, - GPIO_167, - GPIO_168, - GPIO_169, - GPIO_170, - GPIO_171, - GPIO_172, - GPIO_173, - GPIO_174, - GPIO_175, - GPIO_176, - GPIO_177, - GPIO_178, - GPIO_179, - GPIO_180, - GPIO_181, - GPIO_182, - GPIO_183, - GPIO_184, - GPIO_185, - GPIO_186, - GPIO_187, - GPIO_188, - GPIO_189, - GPIO_190, - GPIO_191, - GPIO_192, - GPIO_193, - GPIO_194, - GPIO_195, - GPIO_196, - GPIO_197, - GPIO_198, - GPIO_199, - GPIO_200, - GPIO_201, - GPIO_202, - GPIO_203, - GPIO_204, - GPIO_205, - GPIO_206, - GPIO_207, - GPIO_208, - GPIO_209, - GPIO_210, - GPIO_211, - GPIO_212, - GPIO_213, - GPIO_214, - GPIO_215, - GPIO_216, - GPIO_217, - GPIO_218, - GPIO_219, - GPIO_220, - GPIO_221, - GPIO_222, - GPIO_223, - GPIO_224, - GPIO_225, - GPIO_226, - GPIO_227, - GPIO_228, - GPIO_229, - MAX_GPIO_NO -} GPIO_COUNT; - -typedef struct _GPIO_SETTINGS -{ - u8 select; - u8 type; - u8 value; - u8 NonGpioGevent; -} GPIO_SETTINGS; - -const GPIO_SETTINGS gpio_table[]= -{ - {GPIO_00_SELECT, GPIO_00_TYPE, GPO_00_LEVEL+GPIO_00_STICKY+GPIO_00_PULLUP+GPIO_00_PULLDOWN, GPIO_00_SELECT}, - {GPIO_01_SELECT, GPIO_01_TYPE, GPO_01_LEVEL+GPIO_01_STICKY+GPIO_01_PULLUP+GPIO_01_PULLDOWN, GPIO_01_SELECT}, - {GPIO_02_SELECT, GPIO_02_TYPE, GPO_02_LEVEL+GPIO_02_STICKY+GPIO_02_PULLUP+GPIO_02_PULLDOWN, GPIO_02_SELECT}, - {GPIO_03_SELECT, GPIO_03_TYPE, GPO_03_LEVEL+GPIO_03_STICKY+GPIO_03_PULLUP+GPIO_03_PULLDOWN, GPIO_03_SELECT}, - {GPIO_04_SELECT, GPIO_04_TYPE, GPO_04_LEVEL+GPIO_04_STICKY+GPIO_04_PULLUP+GPIO_04_PULLDOWN, GPIO_04_SELECT}, - {GPIO_05_SELECT, GPIO_05_TYPE, GPO_05_LEVEL+GPIO_05_STICKY+GPIO_05_PULLUP+GPIO_05_PULLDOWN, GPIO_05_SELECT}, - {GPIO_06_SELECT, GPIO_06_TYPE, GPO_06_LEVEL+GPIO_06_STICKY+GPIO_06_PULLUP+GPIO_06_PULLDOWN, GPIO_06_SELECT}, - {GPIO_07_SELECT, GPIO_07_TYPE, GPO_07_LEVEL+GPIO_07_STICKY+GPIO_07_PULLUP+GPIO_07_PULLDOWN, GPIO_07_SELECT}, - {GPIO_08_SELECT, GPIO_08_TYPE, GPO_08_LEVEL+GPIO_08_STICKY+GPIO_08_PULLUP+GPIO_08_PULLDOWN, GPIO_08_SELECT}, - {GPIO_09_SELECT, GPIO_09_TYPE, GPO_09_LEVEL+GPIO_09_STICKY+GPIO_09_PULLUP+GPIO_09_PULLDOWN, GPIO_09_SELECT}, - {GPIO_10_SELECT, GPIO_10_TYPE, GPO_10_LEVEL+GPIO_10_STICKY+GPIO_10_PULLUP+GPIO_10_PULLDOWN, GPIO_10_SELECT}, - {GPIO_11_SELECT, GPIO_11_TYPE, GPO_11_LEVEL+GPIO_11_STICKY+GPIO_11_PULLUP+GPIO_11_PULLDOWN, GPIO_11_SELECT}, - {GPIO_12_SELECT, GPIO_12_TYPE, GPO_12_LEVEL+GPIO_12_STICKY+GPIO_12_PULLUP+GPIO_12_PULLDOWN, GPIO_12_SELECT}, - {GPIO_13_SELECT, GPIO_13_TYPE, GPO_13_LEVEL+GPIO_13_STICKY+GPIO_13_PULLUP+GPIO_13_PULLDOWN, GPIO_13_SELECT}, - {GPIO_14_SELECT, GPIO_14_TYPE, GPO_14_LEVEL+GPIO_14_STICKY+GPIO_14_PULLUP+GPIO_14_PULLDOWN, GPIO_14_SELECT}, - {GPIO_15_SELECT, GPIO_15_TYPE, GPO_15_LEVEL+GPIO_15_STICKY+GPIO_15_PULLUP+GPIO_15_PULLDOWN, GPIO_15_SELECT}, - {GPIO_16_SELECT, GPIO_16_TYPE, GPO_16_LEVEL+GPIO_16_STICKY+GPIO_16_PULLUP+GPIO_16_PULLDOWN, GPIO_16_SELECT}, - {GPIO_17_SELECT, GPIO_17_TYPE, GPO_17_LEVEL+GPIO_17_STICKY+GPIO_17_PULLUP+GPIO_17_PULLDOWN, GPIO_17_SELECT}, - {GPIO_18_SELECT, GPIO_18_TYPE, GPO_18_LEVEL+GPIO_18_STICKY+GPIO_18_PULLUP+GPIO_18_PULLDOWN, GPIO_18_SELECT}, - {GPIO_19_SELECT, GPIO_19_TYPE, GPO_19_LEVEL+GPIO_19_STICKY+GPIO_19_PULLUP+GPIO_19_PULLDOWN, GPIO_19_SELECT}, - {GPIO_20_SELECT, GPIO_20_TYPE, GPO_20_LEVEL+GPIO_20_STICKY+GPIO_20_PULLUP+GPIO_20_PULLDOWN, GPIO_20_SELECT}, - {GPIO_21_SELECT, GPIO_21_TYPE, GPO_21_LEVEL+GPIO_21_STICKY+GPIO_21_PULLUP+GPIO_21_PULLDOWN, GPIO_21_SELECT}, - {GPIO_22_SELECT, GPIO_22_TYPE, GPO_22_LEVEL+GPIO_22_STICKY+GPIO_22_PULLUP+GPIO_22_PULLDOWN, GPIO_22_SELECT}, - {GPIO_23_SELECT, GPIO_23_TYPE, GPO_23_LEVEL+GPIO_23_STICKY+GPIO_23_PULLUP+GPIO_23_PULLDOWN, GPIO_23_SELECT}, - {GPIO_24_SELECT, GPIO_24_TYPE, GPO_24_LEVEL+GPIO_24_STICKY+GPIO_24_PULLUP+GPIO_24_PULLDOWN, GPIO_24_SELECT}, - {GPIO_25_SELECT, GPIO_25_TYPE, GPO_25_LEVEL+GPIO_25_STICKY+GPIO_25_PULLUP+GPIO_25_PULLDOWN, GPIO_25_SELECT}, - {GPIO_26_SELECT, GPIO_26_TYPE, GPO_26_LEVEL+GPIO_26_STICKY+GPIO_26_PULLUP+GPIO_26_PULLDOWN, GPIO_26_SELECT}, - {GPIO_27_SELECT, GPIO_27_TYPE, GPO_27_LEVEL+GPIO_27_STICKY+GPIO_27_PULLUP+GPIO_27_PULLDOWN, GPIO_27_SELECT}, - {GPIO_28_SELECT, GPIO_28_TYPE, GPO_28_LEVEL+GPIO_28_STICKY+GPIO_28_PULLUP+GPIO_28_PULLDOWN, GPIO_28_SELECT}, - {GPIO_29_SELECT, GPIO_29_TYPE, GPO_29_LEVEL+GPIO_29_STICKY+GPIO_29_PULLUP+GPIO_29_PULLDOWN, GPIO_29_SELECT}, - {GPIO_30_SELECT, GPIO_30_TYPE, GPO_30_LEVEL+GPIO_30_STICKY+GPIO_30_PULLUP+GPIO_30_PULLDOWN, GPIO_30_SELECT}, - {GPIO_31_SELECT, GPIO_31_TYPE, GPO_31_LEVEL+GPIO_31_STICKY+GPIO_31_PULLUP+GPIO_31_PULLDOWN, GPIO_31_SELECT}, - {GPIO_32_SELECT, GPIO_32_TYPE, GPO_32_LEVEL+GPIO_32_STICKY+GPIO_32_PULLUP+GPIO_32_PULLDOWN, GPIO_32_SELECT}, - {GPIO_33_SELECT, GPIO_33_TYPE, GPO_33_LEVEL+GPIO_33_STICKY+GPIO_33_PULLUP+GPIO_33_PULLDOWN, GPIO_33_SELECT}, - {GPIO_34_SELECT, GPIO_34_TYPE, GPO_34_LEVEL+GPIO_34_STICKY+GPIO_34_PULLUP+GPIO_34_PULLDOWN, GPIO_34_SELECT}, - {GPIO_35_SELECT, GPIO_35_TYPE, GPO_35_LEVEL+GPIO_35_STICKY+GPIO_35_PULLUP+GPIO_35_PULLDOWN, GPIO_35_SELECT}, - {GPIO_36_SELECT, GPIO_36_TYPE, GPO_36_LEVEL+GPIO_36_STICKY+GPIO_36_PULLUP+GPIO_36_PULLDOWN, GPIO_36_SELECT}, - {GPIO_37_SELECT, GPIO_37_TYPE, GPO_37_LEVEL+GPIO_37_STICKY+GPIO_37_PULLUP+GPIO_37_PULLDOWN, GPIO_37_SELECT}, - {GPIO_38_SELECT, GPIO_38_TYPE, GPO_38_LEVEL+GPIO_38_STICKY+GPIO_38_PULLUP+GPIO_38_PULLDOWN, GPIO_38_SELECT}, - {GPIO_39_SELECT, GPIO_39_TYPE, GPO_39_LEVEL+GPIO_39_STICKY+GPIO_39_PULLUP+GPIO_39_PULLDOWN, GPIO_39_SELECT}, - {GPIO_40_SELECT, GPIO_40_TYPE, GPO_40_LEVEL+GPIO_40_STICKY+GPIO_40_PULLUP+GPIO_40_PULLDOWN, GPIO_40_SELECT}, - {GPIO_41_SELECT, GPIO_41_TYPE, GPO_41_LEVEL+GPIO_41_STICKY+GPIO_41_PULLUP+GPIO_41_PULLDOWN, GPIO_41_SELECT}, - {GPIO_42_SELECT, GPIO_42_TYPE, GPO_42_LEVEL+GPIO_42_STICKY+GPIO_42_PULLUP+GPIO_42_PULLDOWN, GPIO_42_SELECT}, - {GPIO_43_SELECT, GPIO_43_TYPE, GPO_43_LEVEL+GPIO_43_STICKY+GPIO_43_PULLUP+GPIO_43_PULLDOWN, GPIO_43_SELECT}, - {GPIO_44_SELECT, GPIO_44_TYPE, GPO_44_LEVEL+GPIO_44_STICKY+GPIO_44_PULLUP+GPIO_44_PULLDOWN, GPIO_44_SELECT}, - {GPIO_45_SELECT, GPIO_45_TYPE, GPO_45_LEVEL+GPIO_45_STICKY+GPIO_45_PULLUP+GPIO_45_PULLDOWN, GPIO_45_SELECT}, - {GPIO_46_SELECT, GPIO_46_TYPE, GPO_46_LEVEL+GPIO_46_STICKY+GPIO_46_PULLUP+GPIO_46_PULLDOWN, GPIO_46_SELECT}, - {GPIO_47_SELECT, GPIO_47_TYPE, GPO_47_LEVEL+GPIO_47_STICKY+GPIO_47_PULLUP+GPIO_47_PULLDOWN, GPIO_47_SELECT}, - {GPIO_48_SELECT, GPIO_48_TYPE, GPO_48_LEVEL+GPIO_48_STICKY+GPIO_48_PULLUP+GPIO_48_PULLDOWN, GPIO_48_SELECT}, - {GPIO_49_SELECT, GPIO_49_TYPE, GPO_49_LEVEL+GPIO_49_STICKY+GPIO_49_PULLUP+GPIO_49_PULLDOWN, GPIO_49_SELECT}, - {GPIO_50_SELECT, GPIO_50_TYPE, GPO_50_LEVEL+GPIO_50_STICKY+GPIO_50_PULLUP+GPIO_50_PULLDOWN, GPIO_50_SELECT}, - {GPIO_51_SELECT, GPIO_51_TYPE, GPO_51_LEVEL+GPIO_51_STICKY+GPIO_51_PULLUP+GPIO_51_PULLDOWN, GPIO_51_SELECT}, - {GPIO_52_SELECT, GPIO_52_TYPE, GPO_52_LEVEL+GPIO_52_STICKY+GPIO_52_PULLUP+GPIO_52_PULLDOWN, GPIO_52_SELECT}, - {GPIO_53_SELECT, GPIO_53_TYPE, GPO_53_LEVEL+GPIO_53_STICKY+GPIO_53_PULLUP+GPIO_53_PULLDOWN, GPIO_53_SELECT}, - {GPIO_54_SELECT, GPIO_54_TYPE, GPO_54_LEVEL+GPIO_54_STICKY+GPIO_54_PULLUP+GPIO_54_PULLDOWN, GPIO_54_SELECT}, - {GPIO_55_SELECT, GPIO_55_TYPE, GPO_55_LEVEL+GPIO_55_STICKY+GPIO_55_PULLUP+GPIO_55_PULLDOWN, GPIO_55_SELECT}, - {GPIO_56_SELECT, GPIO_56_TYPE, GPO_56_LEVEL+GPIO_56_STICKY+GPIO_56_PULLUP+GPIO_56_PULLDOWN, GPIO_56_SELECT}, - {GPIO_57_SELECT, GPIO_57_TYPE, GPO_57_LEVEL+GPIO_57_STICKY+GPIO_57_PULLUP+GPIO_57_PULLDOWN, GPIO_57_SELECT}, - {GPIO_58_SELECT, GPIO_58_TYPE, GPO_58_LEVEL+GPIO_58_STICKY+GPIO_58_PULLUP+GPIO_58_PULLDOWN, GPIO_58_SELECT}, - {GPIO_59_SELECT, GPIO_59_TYPE, GPO_59_LEVEL+GPIO_59_STICKY+GPIO_59_PULLUP+GPIO_59_PULLDOWN, GPIO_59_SELECT}, - {GPIO_60_SELECT, GPIO_60_TYPE, GPO_60_LEVEL+GPIO_60_STICKY+GPIO_60_PULLUP+GPIO_60_PULLDOWN, GPIO_60_SELECT}, - {GPIO_61_SELECT, GPIO_61_TYPE, GPO_61_LEVEL+GPIO_61_STICKY+GPIO_61_PULLUP+GPIO_61_PULLDOWN, GPIO_61_SELECT}, - {GPIO_62_SELECT, GPIO_62_TYPE, GPO_62_LEVEL+GPIO_62_STICKY+GPIO_62_PULLUP+GPIO_62_PULLDOWN, GPIO_62_SELECT}, - {GPIO_63_SELECT, GPIO_63_TYPE, GPO_63_LEVEL+GPIO_63_STICKY+GPIO_63_PULLUP+GPIO_63_PULLDOWN, GPIO_63_SELECT}, - {GPIO_64_SELECT, GPIO_64_TYPE, GPO_64_LEVEL+GPIO_64_STICKY+GPIO_64_PULLUP+GPIO_64_PULLDOWN, GPIO_64_SELECT}, - {GPIO_65_SELECT, GPIO_65_TYPE, GPO_65_LEVEL+GPIO_65_STICKY+GPIO_65_PULLUP+GPIO_65_PULLDOWN, GPIO_65_SELECT}, - {GPIO_66_SELECT, GPIO_66_TYPE, GPO_66_LEVEL+GPIO_66_STICKY+GPIO_66_PULLUP+GPIO_66_PULLDOWN, GPIO_66_SELECT}, - {GPIO_67_SELECT, GPIO_67_TYPE, GPO_67_LEVEL+GPIO_67_STICKY+GPIO_67_PULLUP+GPIO_67_PULLDOWN, GPIO_67_SELECT}, - {GPIO_68_SELECT, GPIO_68_TYPE, GPO_68_LEVEL+GPIO_68_STICKY+GPIO_68_PULLUP+GPIO_68_PULLDOWN, GPIO_68_SELECT}, - {GPIO_69_SELECT, GPIO_69_TYPE, GPO_69_LEVEL+GPIO_69_STICKY+GPIO_69_PULLUP+GPIO_69_PULLDOWN, GPIO_69_SELECT}, - {GPIO_70_SELECT, GPIO_70_TYPE, GPO_70_LEVEL+GPIO_70_STICKY+GPIO_70_PULLUP+GPIO_70_PULLDOWN, GPIO_70_SELECT}, - {GPIO_71_SELECT, GPIO_71_TYPE, GPO_71_LEVEL+GPIO_71_STICKY+GPIO_71_PULLUP+GPIO_71_PULLDOWN, GPIO_71_SELECT}, - {GPIO_72_SELECT, GPIO_72_TYPE, GPO_72_LEVEL+GPIO_72_STICKY+GPIO_72_PULLUP+GPIO_72_PULLDOWN, GPIO_72_SELECT}, - {GPIO_73_SELECT, GPIO_73_TYPE, GPO_73_LEVEL+GPIO_73_STICKY+GPIO_73_PULLUP+GPIO_73_PULLDOWN, GPIO_73_SELECT}, - {GPIO_74_SELECT, GPIO_74_TYPE, GPO_74_LEVEL+GPIO_74_STICKY+GPIO_74_PULLUP+GPIO_74_PULLDOWN, GPIO_74_SELECT}, - {GPIO_75_SELECT, GPIO_75_TYPE, GPO_75_LEVEL+GPIO_75_STICKY+GPIO_75_PULLUP+GPIO_75_PULLDOWN, GPIO_75_SELECT}, - {GPIO_76_SELECT, GPIO_76_TYPE, GPO_76_LEVEL+GPIO_76_STICKY+GPIO_76_PULLUP+GPIO_76_PULLDOWN, GPIO_76_SELECT}, - {GPIO_77_SELECT, GPIO_77_TYPE, GPO_77_LEVEL+GPIO_77_STICKY+GPIO_77_PULLUP+GPIO_77_PULLDOWN, GPIO_77_SELECT}, - {GPIO_78_SELECT, GPIO_78_TYPE, GPO_78_LEVEL+GPIO_78_STICKY+GPIO_78_PULLUP+GPIO_78_PULLDOWN, GPIO_78_SELECT}, - {GPIO_79_SELECT, GPIO_79_TYPE, GPO_79_LEVEL+GPIO_79_STICKY+GPIO_79_PULLUP+GPIO_79_PULLDOWN, GPIO_79_SELECT}, - {GPIO_80_SELECT, GPIO_80_TYPE, GPO_80_LEVEL+GPIO_80_STICKY+GPIO_80_PULLUP+GPIO_80_PULLDOWN, GPIO_80_SELECT}, - {GPIO_81_SELECT, GPIO_81_TYPE, GPO_81_LEVEL+GPIO_81_STICKY+GPIO_81_PULLUP+GPIO_81_PULLDOWN, GPIO_81_SELECT}, - {GPIO_82_SELECT, GPIO_82_TYPE, GPO_82_LEVEL+GPIO_82_STICKY+GPIO_82_PULLUP+GPIO_82_PULLDOWN, GPIO_82_SELECT}, - {GPIO_83_SELECT, GPIO_83_TYPE, GPO_83_LEVEL+GPIO_83_STICKY+GPIO_83_PULLUP+GPIO_83_PULLDOWN, GPIO_83_SELECT}, - {GPIO_84_SELECT, GPIO_84_TYPE, GPO_84_LEVEL+GPIO_84_STICKY+GPIO_84_PULLUP+GPIO_84_PULLDOWN, GPIO_84_SELECT}, - {GPIO_85_SELECT, GPIO_85_TYPE, GPO_85_LEVEL+GPIO_85_STICKY+GPIO_85_PULLUP+GPIO_85_PULLDOWN, GPIO_85_SELECT}, - {GPIO_86_SELECT, GPIO_86_TYPE, GPO_86_LEVEL+GPIO_86_STICKY+GPIO_86_PULLUP+GPIO_86_PULLDOWN, GPIO_86_SELECT}, - {GPIO_87_SELECT, GPIO_87_TYPE, GPO_87_LEVEL+GPIO_87_STICKY+GPIO_87_PULLUP+GPIO_87_PULLDOWN, GPIO_87_SELECT}, - {GPIO_88_SELECT, GPIO_88_TYPE, GPO_88_LEVEL+GPIO_88_STICKY+GPIO_88_PULLUP+GPIO_88_PULLDOWN, GPIO_88_SELECT}, - {GPIO_89_SELECT, GPIO_89_TYPE, GPO_89_LEVEL+GPIO_89_STICKY+GPIO_89_PULLUP+GPIO_89_PULLDOWN, GPIO_89_SELECT}, - {GPIO_90_SELECT, GPIO_90_TYPE, GPO_90_LEVEL+GPIO_90_STICKY+GPIO_90_PULLUP+GPIO_90_PULLDOWN, GPIO_90_SELECT}, - {GPIO_91_SELECT, GPIO_91_TYPE, GPO_91_LEVEL+GPIO_91_STICKY+GPIO_91_PULLUP+GPIO_91_PULLDOWN, GPIO_91_SELECT}, - {GPIO_92_SELECT, GPIO_92_TYPE, GPO_92_LEVEL+GPIO_92_STICKY+GPIO_92_PULLUP+GPIO_92_PULLDOWN, GPIO_92_SELECT}, - {GPIO_93_SELECT, GPIO_93_TYPE, GPO_93_LEVEL+GPIO_93_STICKY+GPIO_93_PULLUP+GPIO_93_PULLDOWN, GPIO_93_SELECT}, - {GPIO_94_SELECT, GPIO_94_TYPE, GPO_94_LEVEL+GPIO_94_STICKY+GPIO_94_PULLUP+GPIO_94_PULLDOWN, GPIO_94_SELECT}, - {GPIO_95_SELECT, GPIO_95_TYPE, GPO_95_LEVEL+GPIO_95_STICKY+GPIO_95_PULLUP+GPIO_95_PULLDOWN, GPIO_95_SELECT}, - {GPIO_96_SELECT, GPIO_96_TYPE, GPO_96_LEVEL+GPIO_96_STICKY+GPIO_96_PULLUP+GPIO_96_PULLDOWN, GPIO_96_SELECT}, - {GPIO_97_SELECT, GPIO_97_TYPE, GPO_97_LEVEL+GPIO_97_STICKY+GPIO_97_PULLUP+GPIO_97_PULLDOWN, GPIO_97_SELECT}, - {GPIO_98_SELECT, GPIO_98_TYPE, GPO_98_LEVEL+GPIO_98_STICKY+GPIO_98_PULLUP+GPIO_98_PULLDOWN, GPIO_98_SELECT}, - {GPIO_99_SELECT, GPIO_99_TYPE, GPO_99_LEVEL+GPIO_99_STICKY+GPIO_99_PULLUP+GPIO_99_PULLDOWN, GPIO_99_SELECT}, - {GPIO_100_SELECT, GPIO_100_TYPE, GPO_100_LEVEL+GPIO_100_STICKY+GPIO_100_PULLUP+GPIO_100_PULLDOWN, GPIO_100_SELECT}, - {GPIO_101_SELECT, GPIO_101_TYPE, GPO_101_LEVEL+GPIO_101_STICKY+GPIO_101_PULLUP+GPIO_101_PULLDOWN, GPIO_101_SELECT}, - {GPIO_102_SELECT, GPIO_102_TYPE, GPO_102_LEVEL+GPIO_102_STICKY+GPIO_102_PULLUP+GPIO_102_PULLDOWN, GPIO_102_SELECT}, - {GPIO_103_SELECT, GPIO_103_TYPE, GPO_103_LEVEL+GPIO_103_STICKY+GPIO_103_PULLUP+GPIO_103_PULLDOWN, GPIO_103_SELECT}, - {GPIO_104_SELECT, GPIO_104_TYPE, GPO_104_LEVEL+GPIO_104_STICKY+GPIO_104_PULLUP+GPIO_104_PULLDOWN, GPIO_104_SELECT}, - {GPIO_105_SELECT, GPIO_105_TYPE, GPO_105_LEVEL+GPIO_105_STICKY+GPIO_105_PULLUP+GPIO_105_PULLDOWN, GPIO_105_SELECT}, - {GPIO_106_SELECT, GPIO_106_TYPE, GPO_106_LEVEL+GPIO_106_STICKY+GPIO_106_PULLUP+GPIO_106_PULLDOWN, GPIO_106_SELECT}, - {GPIO_107_SELECT, GPIO_107_TYPE, GPO_107_LEVEL+GPIO_107_STICKY+GPIO_107_PULLUP+GPIO_107_PULLDOWN, GPIO_107_SELECT}, - {GPIO_108_SELECT, GPIO_108_TYPE, GPO_108_LEVEL+GPIO_108_STICKY+GPIO_108_PULLUP+GPIO_108_PULLDOWN, GPIO_108_SELECT}, - {GPIO_109_SELECT, GPIO_109_TYPE, GPO_109_LEVEL+GPIO_109_STICKY+GPIO_109_PULLUP+GPIO_109_PULLDOWN, GPIO_109_SELECT}, - {GPIO_110_SELECT, GPIO_110_TYPE, GPO_110_LEVEL+GPIO_110_STICKY+GPIO_110_PULLUP+GPIO_110_PULLDOWN, GPIO_110_SELECT}, - {GPIO_111_SELECT, GPIO_111_TYPE, GPO_111_LEVEL+GPIO_111_STICKY+GPIO_111_PULLUP+GPIO_111_PULLDOWN, GPIO_111_SELECT}, - {GPIO_112_SELECT, GPIO_112_TYPE, GPO_112_LEVEL+GPIO_112_STICKY+GPIO_112_PULLUP+GPIO_112_PULLDOWN, GPIO_112_SELECT}, - {GPIO_113_SELECT, GPIO_113_TYPE, GPO_113_LEVEL+GPIO_113_STICKY+GPIO_113_PULLUP+GPIO_113_PULLDOWN, GPIO_113_SELECT}, - {GPIO_114_SELECT, GPIO_114_TYPE, GPO_114_LEVEL+GPIO_114_STICKY+GPIO_114_PULLUP+GPIO_114_PULLDOWN, GPIO_114_SELECT}, - {GPIO_115_SELECT, GPIO_115_TYPE, GPO_115_LEVEL+GPIO_115_STICKY+GPIO_115_PULLUP+GPIO_115_PULLDOWN, GPIO_115_SELECT}, - {GPIO_116_SELECT, GPIO_116_TYPE, GPO_116_LEVEL+GPIO_116_STICKY+GPIO_116_PULLUP+GPIO_116_PULLDOWN, GPIO_116_SELECT}, - {GPIO_117_SELECT, GPIO_117_TYPE, GPO_117_LEVEL+GPIO_117_STICKY+GPIO_117_PULLUP+GPIO_117_PULLDOWN, GPIO_117_SELECT}, - {GPIO_118_SELECT, GPIO_118_TYPE, GPO_118_LEVEL+GPIO_118_STICKY+GPIO_118_PULLUP+GPIO_118_PULLDOWN, GPIO_118_SELECT}, - {GPIO_119_SELECT, GPIO_119_TYPE, GPO_119_LEVEL+GPIO_119_STICKY+GPIO_119_PULLUP+GPIO_119_PULLDOWN, GPIO_119_SELECT}, - {GPIO_120_SELECT, GPIO_120_TYPE, GPO_120_LEVEL+GPIO_120_STICKY+GPIO_120_PULLUP+GPIO_120_PULLDOWN, GPIO_120_SELECT}, - {GPIO_121_SELECT, GPIO_121_TYPE, GPO_121_LEVEL+GPIO_121_STICKY+GPIO_121_PULLUP+GPIO_121_PULLDOWN, GPIO_121_SELECT}, - {GPIO_122_SELECT, GPIO_122_TYPE, GPO_122_LEVEL+GPIO_122_STICKY+GPIO_122_PULLUP+GPIO_122_PULLDOWN, GPIO_122_SELECT}, - {GPIO_123_SELECT, GPIO_123_TYPE, GPO_123_LEVEL+GPIO_123_STICKY+GPIO_123_PULLUP+GPIO_123_PULLDOWN, GPIO_123_SELECT}, - {GPIO_124_SELECT, GPIO_124_TYPE, GPO_124_LEVEL+GPIO_124_STICKY+GPIO_124_PULLUP+GPIO_124_PULLDOWN, GPIO_124_SELECT}, - {GPIO_125_SELECT, GPIO_125_TYPE, GPO_125_LEVEL+GPIO_125_STICKY+GPIO_125_PULLUP+GPIO_125_PULLDOWN, GPIO_125_SELECT}, - {GPIO_126_SELECT, GPIO_126_TYPE, GPO_126_LEVEL+GPIO_126_STICKY+GPIO_126_PULLUP+GPIO_126_PULLDOWN, GPIO_126_SELECT}, - {GPIO_127_SELECT, GPIO_127_TYPE, GPO_127_LEVEL+GPIO_127_STICKY+GPIO_127_PULLUP+GPIO_127_PULLDOWN, GPIO_127_SELECT}, - {GPIO_128_SELECT, GPIO_128_TYPE, GPO_128_LEVEL+GPIO_128_STICKY+GPIO_128_PULLUP+GPIO_128_PULLDOWN, GPIO_128_SELECT}, - {GPIO_129_SELECT, GPIO_129_TYPE, GPO_129_LEVEL+GPIO_129_STICKY+GPIO_129_PULLUP+GPIO_129_PULLDOWN, GPIO_129_SELECT}, - {GPIO_130_SELECT, GPIO_130_TYPE, GPO_130_LEVEL+GPIO_130_STICKY+GPIO_130_PULLUP+GPIO_130_PULLDOWN, GPIO_130_SELECT}, - {GPIO_131_SELECT, GPIO_131_TYPE, GPO_131_LEVEL+GPIO_131_STICKY+GPIO_131_PULLUP+GPIO_131_PULLDOWN, GPIO_131_SELECT}, - {GPIO_132_SELECT, GPIO_132_TYPE, GPO_132_LEVEL+GPIO_132_STICKY+GPIO_132_PULLUP+GPIO_132_PULLDOWN, GPIO_132_SELECT}, - {GPIO_133_SELECT, GPIO_133_TYPE, GPO_133_LEVEL+GPIO_133_STICKY+GPIO_133_PULLUP+GPIO_133_PULLDOWN, GPIO_133_SELECT}, - {GPIO_134_SELECT, GPIO_134_TYPE, GPO_134_LEVEL+GPIO_134_STICKY+GPIO_134_PULLUP+GPIO_134_PULLDOWN, GPIO_134_SELECT}, - {GPIO_135_SELECT, GPIO_135_TYPE, GPO_135_LEVEL+GPIO_135_STICKY+GPIO_135_PULLUP+GPIO_135_PULLDOWN, GPIO_135_SELECT}, - {GPIO_136_SELECT, GPIO_136_TYPE, GPO_136_LEVEL+GPIO_136_STICKY+GPIO_136_PULLUP+GPIO_136_PULLDOWN, GPIO_136_SELECT}, - {GPIO_137_SELECT, GPIO_137_TYPE, GPO_137_LEVEL+GPIO_137_STICKY+GPIO_137_PULLUP+GPIO_137_PULLDOWN, GPIO_137_SELECT}, - {GPIO_138_SELECT, GPIO_138_TYPE, GPO_138_LEVEL+GPIO_138_STICKY+GPIO_138_PULLUP+GPIO_138_PULLDOWN, GPIO_138_SELECT}, - {GPIO_139_SELECT, GPIO_139_TYPE, GPO_139_LEVEL+GPIO_139_STICKY+GPIO_139_PULLUP+GPIO_139_PULLDOWN, GPIO_139_SELECT}, - {GPIO_140_SELECT, GPIO_140_TYPE, GPO_140_LEVEL+GPIO_140_STICKY+GPIO_140_PULLUP+GPIO_140_PULLDOWN, GPIO_140_SELECT}, - {GPIO_141_SELECT, GPIO_141_TYPE, GPO_141_LEVEL+GPIO_141_STICKY+GPIO_141_PULLUP+GPIO_141_PULLDOWN, GPIO_141_SELECT}, - {GPIO_142_SELECT, GPIO_142_TYPE, GPO_142_LEVEL+GPIO_142_STICKY+GPIO_142_PULLUP+GPIO_142_PULLDOWN, GPIO_142_SELECT}, - {GPIO_143_SELECT, GPIO_143_TYPE, GPO_143_LEVEL+GPIO_143_STICKY+GPIO_143_PULLUP+GPIO_143_PULLDOWN, GPIO_143_SELECT}, - {GPIO_144_SELECT, GPIO_144_TYPE, GPO_144_LEVEL+GPIO_144_STICKY+GPIO_144_PULLUP+GPIO_144_PULLDOWN, GPIO_144_SELECT}, - {GPIO_145_SELECT, GPIO_145_TYPE, GPO_145_LEVEL+GPIO_145_STICKY+GPIO_145_PULLUP+GPIO_145_PULLDOWN, GPIO_145_SELECT}, - {GPIO_146_SELECT, GPIO_146_TYPE, GPO_146_LEVEL+GPIO_146_STICKY+GPIO_146_PULLUP+GPIO_146_PULLDOWN, GPIO_146_SELECT}, - {GPIO_147_SELECT, GPIO_147_TYPE, GPO_147_LEVEL+GPIO_147_STICKY+GPIO_147_PULLUP+GPIO_147_PULLDOWN, GPIO_147_SELECT}, - {GPIO_148_SELECT, GPIO_148_TYPE, GPO_148_LEVEL+GPIO_148_STICKY+GPIO_148_PULLUP+GPIO_148_PULLDOWN, GPIO_148_SELECT}, - {GPIO_149_SELECT, GPIO_149_TYPE, GPO_149_LEVEL+GPIO_149_STICKY+GPIO_149_PULLUP+GPIO_149_PULLDOWN, GPIO_149_SELECT}, - {GPIO_150_SELECT, GPIO_150_TYPE, GPO_150_LEVEL+GPIO_150_STICKY+GPIO_150_PULLUP+GPIO_150_PULLDOWN, GPIO_150_SELECT}, - {GPIO_151_SELECT, GPIO_151_TYPE, GPO_151_LEVEL+GPIO_151_STICKY+GPIO_151_PULLUP+GPIO_151_PULLDOWN, GPIO_151_SELECT}, - {GPIO_152_SELECT, GPIO_152_TYPE, GPO_152_LEVEL+GPIO_152_STICKY+GPIO_152_PULLUP+GPIO_152_PULLDOWN, GPIO_152_SELECT}, - {GPIO_153_SELECT, GPIO_153_TYPE, GPO_153_LEVEL+GPIO_153_STICKY+GPIO_153_PULLUP+GPIO_153_PULLDOWN, GPIO_153_SELECT}, - {GPIO_154_SELECT, GPIO_154_TYPE, GPO_154_LEVEL+GPIO_154_STICKY+GPIO_154_PULLUP+GPIO_154_PULLDOWN, GPIO_154_SELECT}, - {GPIO_155_SELECT, GPIO_155_TYPE, GPO_155_LEVEL+GPIO_155_STICKY+GPIO_155_PULLUP+GPIO_155_PULLDOWN, GPIO_155_SELECT}, - {GPIO_156_SELECT, GPIO_156_TYPE, GPO_156_LEVEL+GPIO_156_STICKY+GPIO_156_PULLUP+GPIO_156_PULLDOWN, GPIO_156_SELECT}, - {GPIO_157_SELECT, GPIO_157_TYPE, GPO_157_LEVEL+GPIO_157_STICKY+GPIO_157_PULLUP+GPIO_157_PULLDOWN, GPIO_157_SELECT}, - {GPIO_158_SELECT, GPIO_158_TYPE, GPO_158_LEVEL+GPIO_158_STICKY+GPIO_158_PULLUP+GPIO_158_PULLDOWN, GPIO_158_SELECT}, - {GPIO_159_SELECT, GPIO_159_TYPE, GPO_159_LEVEL+GPIO_159_STICKY+GPIO_159_PULLUP+GPIO_159_PULLDOWN, GPIO_159_SELECT}, - {GPIO_160_SELECT, GPIO_160_TYPE, GPO_160_LEVEL+GPIO_160_STICKY+GPIO_160_PULLUP+GPIO_160_PULLDOWN, GPIO_160_SELECT}, - {GPIO_161_SELECT, GPIO_161_TYPE, GPO_161_LEVEL+GPIO_161_STICKY+GPIO_161_PULLUP+GPIO_161_PULLDOWN, GPIO_161_SELECT}, - {GPIO_162_SELECT, GPIO_162_TYPE, GPO_162_LEVEL+GPIO_162_STICKY+GPIO_162_PULLUP+GPIO_162_PULLDOWN, GPIO_162_SELECT}, - {GPIO_163_SELECT, GPIO_163_TYPE, GPO_163_LEVEL+GPIO_163_STICKY+GPIO_163_PULLUP+GPIO_163_PULLDOWN, GPIO_163_SELECT}, - {GPIO_164_SELECT, GPIO_164_TYPE, GPO_164_LEVEL+GPIO_164_STICKY+GPIO_164_PULLUP+GPIO_164_PULLDOWN, GPIO_164_SELECT}, - {GPIO_165_SELECT, GPIO_165_TYPE, GPO_165_LEVEL+GPIO_165_STICKY+GPIO_165_PULLUP+GPIO_165_PULLDOWN, GPIO_165_SELECT}, - {GPIO_166_SELECT, GPIO_166_TYPE, GPO_166_LEVEL+GPIO_166_STICKY+GPIO_166_PULLUP+GPIO_166_PULLDOWN, GPIO_166_SELECT}, - {GPIO_167_SELECT, GPIO_167_TYPE, GPO_167_LEVEL+GPIO_167_STICKY+GPIO_167_PULLUP+GPIO_167_PULLDOWN, GPIO_167_SELECT}, - {GPIO_168_SELECT, GPIO_168_TYPE, GPO_168_LEVEL+GPIO_168_STICKY+GPIO_168_PULLUP+GPIO_168_PULLDOWN, GPIO_168_SELECT}, - {GPIO_169_SELECT, GPIO_169_TYPE, GPO_169_LEVEL+GPIO_169_STICKY+GPIO_169_PULLUP+GPIO_169_PULLDOWN, GPIO_169_SELECT}, - {GPIO_170_SELECT, GPIO_170_TYPE, GPO_170_LEVEL+GPIO_170_STICKY+GPIO_170_PULLUP+GPIO_170_PULLDOWN, GPIO_170_SELECT}, - {GPIO_171_SELECT, GPIO_171_TYPE, GPO_171_LEVEL+GPIO_171_STICKY+GPIO_171_PULLUP+GPIO_171_PULLDOWN, GPIO_171_SELECT}, - {GPIO_172_SELECT, GPIO_172_TYPE, GPO_172_LEVEL+GPIO_172_STICKY+GPIO_172_PULLUP+GPIO_172_PULLDOWN, GPIO_172_SELECT}, - {GPIO_173_SELECT, GPIO_173_TYPE, GPO_173_LEVEL+GPIO_173_STICKY+GPIO_173_PULLUP+GPIO_173_PULLDOWN, GPIO_173_SELECT}, - {GPIO_174_SELECT, GPIO_174_TYPE, GPO_174_LEVEL+GPIO_174_STICKY+GPIO_174_PULLUP+GPIO_174_PULLDOWN, GPIO_174_SELECT}, - {GPIO_175_SELECT, GPIO_175_TYPE, GPO_175_LEVEL+GPIO_175_STICKY+GPIO_175_PULLUP+GPIO_175_PULLDOWN, GPIO_175_SELECT}, - {GPIO_176_SELECT, GPIO_176_TYPE, GPO_176_LEVEL+GPIO_176_STICKY+GPIO_176_PULLUP+GPIO_176_PULLDOWN, GPIO_176_SELECT}, - {GPIO_177_SELECT, GPIO_177_TYPE, GPO_177_LEVEL+GPIO_177_STICKY+GPIO_177_PULLUP+GPIO_177_PULLDOWN, GPIO_177_SELECT}, - {GPIO_178_SELECT, GPIO_178_TYPE, GPO_178_LEVEL+GPIO_178_STICKY+GPIO_178_PULLUP+GPIO_178_PULLDOWN, GPIO_178_SELECT}, - {GPIO_179_SELECT, GPIO_179_TYPE, GPO_179_LEVEL+GPIO_179_STICKY+GPIO_179_PULLUP+GPIO_179_PULLDOWN, GPIO_179_SELECT}, - {GPIO_180_SELECT, GPIO_180_TYPE, GPO_180_LEVEL+GPIO_180_STICKY+GPIO_180_PULLUP+GPIO_180_PULLDOWN, GPIO_180_SELECT}, - {GPIO_181_SELECT, GPIO_181_TYPE, GPO_181_LEVEL+GPIO_181_STICKY+GPIO_181_PULLUP+GPIO_181_PULLDOWN, GPIO_181_SELECT}, - {GPIO_182_SELECT, GPIO_182_TYPE, GPO_182_LEVEL+GPIO_182_STICKY+GPIO_182_PULLUP+GPIO_182_PULLDOWN, GPIO_182_SELECT}, - {GPIO_183_SELECT, GPIO_183_TYPE, GPO_183_LEVEL+GPIO_183_STICKY+GPIO_183_PULLUP+GPIO_183_PULLDOWN, GPIO_183_SELECT}, - {GPIO_184_SELECT, GPIO_184_TYPE, GPO_184_LEVEL+GPIO_184_STICKY+GPIO_184_PULLUP+GPIO_184_PULLDOWN, GPIO_184_SELECT}, - {GPIO_185_SELECT, GPIO_185_TYPE, GPO_185_LEVEL+GPIO_185_STICKY+GPIO_185_PULLUP+GPIO_185_PULLDOWN, GPIO_185_SELECT}, - {GPIO_186_SELECT, GPIO_186_TYPE, GPO_186_LEVEL+GPIO_186_STICKY+GPIO_186_PULLUP+GPIO_186_PULLDOWN, GPIO_186_SELECT}, - {GPIO_187_SELECT, GPIO_187_TYPE, GPO_187_LEVEL+GPIO_187_STICKY+GPIO_187_PULLUP+GPIO_187_PULLDOWN, GPIO_187_SELECT}, - {GPIO_188_SELECT, GPIO_188_TYPE, GPO_188_LEVEL+GPIO_188_STICKY+GPIO_188_PULLUP+GPIO_188_PULLDOWN, GPIO_188_SELECT}, - {GPIO_189_SELECT, GPIO_189_TYPE, GPO_189_LEVEL+GPIO_189_STICKY+GPIO_189_PULLUP+GPIO_189_PULLDOWN, GPIO_189_SELECT}, - {GPIO_190_SELECT, GPIO_190_TYPE, GPO_190_LEVEL+GPIO_190_STICKY+GPIO_190_PULLUP+GPIO_190_PULLDOWN, GPIO_190_SELECT}, - {GPIO_191_SELECT, GPIO_191_TYPE, GPO_191_LEVEL+GPIO_191_STICKY+GPIO_191_PULLUP+GPIO_191_PULLDOWN, GPIO_191_SELECT}, - {GPIO_192_SELECT, GPIO_192_TYPE, GPO_192_LEVEL+GPIO_192_STICKY+GPIO_192_PULLUP+GPIO_192_PULLDOWN, GPIO_192_SELECT}, - {GPIO_193_SELECT, GPIO_193_TYPE, GPO_193_LEVEL+GPIO_193_STICKY+GPIO_193_PULLUP+GPIO_193_PULLDOWN, GPIO_193_SELECT}, - {GPIO_194_SELECT, GPIO_194_TYPE, GPO_194_LEVEL+GPIO_194_STICKY+GPIO_194_PULLUP+GPIO_194_PULLDOWN, GPIO_194_SELECT}, - {GPIO_195_SELECT, GPIO_195_TYPE, GPO_195_LEVEL+GPIO_195_STICKY+GPIO_195_PULLUP+GPIO_195_PULLDOWN, GPIO_195_SELECT}, - {GPIO_196_SELECT, GPIO_196_TYPE, GPO_196_LEVEL+GPIO_196_STICKY+GPIO_196_PULLUP+GPIO_196_PULLDOWN, GPIO_196_SELECT}, - {GPIO_197_SELECT, GPIO_197_TYPE, GPO_197_LEVEL+GPIO_197_STICKY+GPIO_197_PULLUP+GPIO_197_PULLDOWN, GPIO_197_SELECT}, - {GPIO_198_SELECT, GPIO_198_TYPE, GPO_198_LEVEL+GPIO_198_STICKY+GPIO_198_PULLUP+GPIO_198_PULLDOWN, GPIO_198_SELECT}, - {GPIO_199_SELECT, GPIO_199_TYPE, GPO_199_LEVEL+GPIO_199_STICKY+GPIO_199_PULLUP+GPIO_199_PULLDOWN, GPIO_199_SELECT}, - {GPIO_200_SELECT, GPIO_200_TYPE, GPO_200_LEVEL+GPIO_200_STICKY+GPIO_200_PULLUP+GPIO_200_PULLDOWN, GPIO_200_SELECT}, - {GPIO_201_SELECT, GPIO_201_TYPE, GPO_201_LEVEL+GPIO_201_STICKY+GPIO_201_PULLUP+GPIO_201_PULLDOWN, GPIO_201_SELECT}, - {GPIO_202_SELECT, GPIO_202_TYPE, GPO_202_LEVEL+GPIO_202_STICKY+GPIO_202_PULLUP+GPIO_202_PULLDOWN, GPIO_202_SELECT}, - {GPIO_203_SELECT, GPIO_203_TYPE, GPO_203_LEVEL+GPIO_203_STICKY+GPIO_203_PULLUP+GPIO_203_PULLDOWN, GPIO_203_SELECT}, - {GPIO_204_SELECT, GPIO_204_TYPE, GPO_204_LEVEL+GPIO_204_STICKY+GPIO_204_PULLUP+GPIO_204_PULLDOWN, GPIO_204_SELECT}, - {GPIO_205_SELECT, GPIO_205_TYPE, GPO_205_LEVEL+GPIO_205_STICKY+GPIO_205_PULLUP+GPIO_205_PULLDOWN, GPIO_205_SELECT}, - {GPIO_206_SELECT, GPIO_206_TYPE, GPO_206_LEVEL+GPIO_206_STICKY+GPIO_206_PULLUP+GPIO_206_PULLDOWN, GPIO_206_SELECT}, - {GPIO_207_SELECT, GPIO_207_TYPE, GPO_207_LEVEL+GPIO_207_STICKY+GPIO_207_PULLUP+GPIO_207_PULLDOWN, GPIO_207_SELECT}, - {GPIO_208_SELECT, GPIO_208_TYPE, GPO_208_LEVEL+GPIO_208_STICKY+GPIO_208_PULLUP+GPIO_208_PULLDOWN, GPIO_208_SELECT}, - {GPIO_209_SELECT, GPIO_209_TYPE, GPO_209_LEVEL+GPIO_209_STICKY+GPIO_209_PULLUP+GPIO_209_PULLDOWN, GPIO_209_SELECT}, - {GPIO_210_SELECT, GPIO_210_TYPE, GPO_210_LEVEL+GPIO_210_STICKY+GPIO_210_PULLUP+GPIO_210_PULLDOWN, GPIO_210_SELECT}, - {GPIO_211_SELECT, GPIO_211_TYPE, GPO_211_LEVEL+GPIO_211_STICKY+GPIO_211_PULLUP+GPIO_211_PULLDOWN, GPIO_211_SELECT}, - {GPIO_212_SELECT, GPIO_212_TYPE, GPO_212_LEVEL+GPIO_212_STICKY+GPIO_212_PULLUP+GPIO_212_PULLDOWN, GPIO_212_SELECT}, - {GPIO_213_SELECT, GPIO_213_TYPE, GPO_213_LEVEL+GPIO_213_STICKY+GPIO_213_PULLUP+GPIO_213_PULLDOWN, GPIO_213_SELECT}, - {GPIO_214_SELECT, GPIO_214_TYPE, GPO_214_LEVEL+GPIO_214_STICKY+GPIO_214_PULLUP+GPIO_214_PULLDOWN, GPIO_214_SELECT}, - {GPIO_215_SELECT, GPIO_215_TYPE, GPO_215_LEVEL+GPIO_215_STICKY+GPIO_215_PULLUP+GPIO_215_PULLDOWN, GPIO_215_SELECT}, - {GPIO_216_SELECT, GPIO_216_TYPE, GPO_216_LEVEL+GPIO_216_STICKY+GPIO_216_PULLUP+GPIO_216_PULLDOWN, GPIO_216_SELECT}, - {GPIO_217_SELECT, GPIO_217_TYPE, GPO_217_LEVEL+GPIO_217_STICKY+GPIO_217_PULLUP+GPIO_217_PULLDOWN, GPIO_217_SELECT}, - {GPIO_218_SELECT, GPIO_218_TYPE, GPO_218_LEVEL+GPIO_218_STICKY+GPIO_218_PULLUP+GPIO_218_PULLDOWN, GPIO_218_SELECT}, - {GPIO_219_SELECT, GPIO_219_TYPE, GPO_219_LEVEL+GPIO_219_STICKY+GPIO_219_PULLUP+GPIO_219_PULLDOWN, GPIO_219_SELECT}, - {GPIO_220_SELECT, GPIO_220_TYPE, GPO_220_LEVEL+GPIO_220_STICKY+GPIO_220_PULLUP+GPIO_220_PULLDOWN, GPIO_220_SELECT}, - {GPIO_221_SELECT, GPIO_221_TYPE, GPO_221_LEVEL+GPIO_221_STICKY+GPIO_221_PULLUP+GPIO_221_PULLDOWN, GPIO_221_SELECT}, - {GPIO_222_SELECT, GPIO_222_TYPE, GPO_222_LEVEL+GPIO_222_STICKY+GPIO_222_PULLUP+GPIO_222_PULLDOWN, GPIO_222_SELECT}, - {GPIO_223_SELECT, GPIO_223_TYPE, GPO_223_LEVEL+GPIO_223_STICKY+GPIO_223_PULLUP+GPIO_223_PULLDOWN, GPIO_223_SELECT}, - {GPIO_224_SELECT, GPIO_224_TYPE, GPO_224_LEVEL+GPIO_224_STICKY+GPIO_224_PULLUP+GPIO_224_PULLDOWN, GPIO_224_SELECT}, - {GPIO_225_SELECT, GPIO_225_TYPE, GPO_225_LEVEL+GPIO_225_STICKY+GPIO_225_PULLUP+GPIO_225_PULLDOWN, GPIO_225_SELECT}, - {GPIO_226_SELECT, GPIO_226_TYPE, GPO_226_LEVEL+GPIO_226_STICKY+GPIO_226_PULLUP+GPIO_226_PULLDOWN, GPIO_226_SELECT}, - {GPIO_227_SELECT, GPIO_227_TYPE, GPO_227_LEVEL+GPIO_227_STICKY+GPIO_227_PULLUP+GPIO_227_PULLDOWN, GPIO_227_SELECT}, - {GPIO_228_SELECT, GPIO_228_TYPE, GPO_228_LEVEL+GPIO_228_STICKY+GPIO_228_PULLUP+GPIO_228_PULLDOWN, GPIO_228_SELECT}, - {GPIO_229_SELECT, GPIO_229_TYPE, GPO_229_LEVEL+GPIO_229_STICKY+GPIO_229_PULLUP+GPIO_229_PULLDOWN, GPIO_229_SELECT}, -}; - -typedef enum _GEVENT_COUNT -{ - GEVENT_00 = 0x60, - GEVENT_01, - GEVENT_02, - GEVENT_03, - GEVENT_04, - GEVENT_05, - GEVENT_06, - GEVENT_07, - GEVENT_08, - GEVENT_09, - GEVENT_10, - GEVENT_11, - GEVENT_12, - GEVENT_13, - GEVENT_14, - GEVENT_15, - GEVENT_16, - GEVENT_17, - GEVENT_18, - GEVENT_19, - GEVENT_20, - GEVENT_21, - GEVENT_22, - GEVENT_23 -} GEVENT_COUNT; - -typedef struct _GEVENT_SETTINGS -{ - u8 EventEnable; // 0: Disable, 1: Enable - u8 SciTrig; // 0: Falling Edge, 1: Rising Edge - u8 SciLevl; // 0: Edge trigger, 1: Level Trigger - u8 SmiSciEn; // 0: Not send SMI, 1: Send SMI - u8 SciS0En; // 0: Disable, 1: Enable - u8 SciMap; // 0000b->1111b - u8 SmiTrig; // 0: Active Low, 1: Active High - u8 SmiControl; // 0: Disable, 1: SMI 2: NMI 3: IRQ13 -} GEVENT_SETTINGS; - -const GEVENT_SETTINGS gevent_table[] = -{ - {GEVENT_00_EVENTENABLE, GEVENT_00_SCITRIG, GEVENT_00_SCILEVEL, GEVENT_00_SMISCIEN, GEVENT_00_SCIS0EN, GEVENT_00_SCIMAP, GEVENT_00_SMITRIG, GEVENT_00_SMICONTROL}, - {GEVENT_01_EVENTENABLE, GEVENT_01_SCITRIG, GEVENT_01_SCILEVEL, GEVENT_01_SMISCIEN, GEVENT_01_SCIS0EN, GEVENT_01_SCIMAP, GEVENT_01_SMITRIG, GEVENT_01_SMICONTROL}, - {GEVENT_02_EVENTENABLE, GEVENT_02_SCITRIG, GEVENT_02_SCILEVEL, GEVENT_02_SMISCIEN, GEVENT_02_SCIS0EN, GEVENT_02_SCIMAP, GEVENT_02_SMITRIG, GEVENT_02_SMICONTROL}, - {GEVENT_03_EVENTENABLE, GEVENT_03_SCITRIG, GEVENT_03_SCILEVEL, GEVENT_03_SMISCIEN, GEVENT_03_SCIS0EN, GEVENT_03_SCIMAP, GEVENT_03_SMITRIG, GEVENT_03_SMICONTROL}, - {GEVENT_04_EVENTENABLE, GEVENT_04_SCITRIG, GEVENT_04_SCILEVEL, GEVENT_04_SMISCIEN, GEVENT_04_SCIS0EN, GEVENT_04_SCIMAP, GEVENT_04_SMITRIG, GEVENT_04_SMICONTROL}, - {GEVENT_05_EVENTENABLE, GEVENT_05_SCITRIG, GEVENT_05_SCILEVEL, GEVENT_05_SMISCIEN, GEVENT_05_SCIS0EN, GEVENT_05_SCIMAP, GEVENT_05_SMITRIG, GEVENT_05_SMICONTROL}, - {GEVENT_06_EVENTENABLE, GEVENT_06_SCITRIG, GEVENT_06_SCILEVEL, GEVENT_06_SMISCIEN, GEVENT_06_SCIS0EN, GEVENT_06_SCIMAP, GEVENT_06_SMITRIG, GEVENT_06_SMICONTROL}, - {GEVENT_07_EVENTENABLE, GEVENT_07_SCITRIG, GEVENT_07_SCILEVEL, GEVENT_07_SMISCIEN, GEVENT_07_SCIS0EN, GEVENT_07_SCIMAP, GEVENT_07_SMITRIG, GEVENT_07_SMICONTROL}, - {GEVENT_08_EVENTENABLE, GEVENT_08_SCITRIG, GEVENT_08_SCILEVEL, GEVENT_08_SMISCIEN, GEVENT_08_SCIS0EN, GEVENT_08_SCIMAP, GEVENT_08_SMITRIG, GEVENT_08_SMICONTROL}, - {GEVENT_09_EVENTENABLE, GEVENT_09_SCITRIG, GEVENT_09_SCILEVEL, GEVENT_09_SMISCIEN, GEVENT_09_SCIS0EN, GEVENT_09_SCIMAP, GEVENT_09_SMITRIG, GEVENT_09_SMICONTROL}, - {GEVENT_10_EVENTENABLE, GEVENT_10_SCITRIG, GEVENT_10_SCILEVEL, GEVENT_10_SMISCIEN, GEVENT_10_SCIS0EN, GEVENT_10_SCIMAP, GEVENT_10_SMITRIG, GEVENT_10_SMICONTROL}, - {GEVENT_11_EVENTENABLE, GEVENT_11_SCITRIG, GEVENT_11_SCILEVEL, GEVENT_11_SMISCIEN, GEVENT_11_SCIS0EN, GEVENT_11_SCIMAP, GEVENT_11_SMITRIG, GEVENT_11_SMICONTROL}, - {GEVENT_12_EVENTENABLE, GEVENT_12_SCITRIG, GEVENT_12_SCILEVEL, GEVENT_12_SMISCIEN, GEVENT_12_SCIS0EN, GEVENT_12_SCIMAP, GEVENT_12_SMITRIG, GEVENT_12_SMICONTROL}, - {GEVENT_13_EVENTENABLE, GEVENT_13_SCITRIG, GEVENT_13_SCILEVEL, GEVENT_13_SMISCIEN, GEVENT_13_SCIS0EN, GEVENT_13_SCIMAP, GEVENT_13_SMITRIG, GEVENT_13_SMICONTROL}, - {GEVENT_14_EVENTENABLE, GEVENT_14_SCITRIG, GEVENT_14_SCILEVEL, GEVENT_14_SMISCIEN, GEVENT_14_SCIS0EN, GEVENT_14_SCIMAP, GEVENT_14_SMITRIG, GEVENT_14_SMICONTROL}, - {GEVENT_15_EVENTENABLE, GEVENT_15_SCITRIG, GEVENT_15_SCILEVEL, GEVENT_15_SMISCIEN, GEVENT_15_SCIS0EN, GEVENT_15_SCIMAP, GEVENT_15_SMITRIG, GEVENT_15_SMICONTROL}, - {GEVENT_16_EVENTENABLE, GEVENT_16_SCITRIG, GEVENT_16_SCILEVEL, GEVENT_16_SMISCIEN, GEVENT_16_SCIS0EN, GEVENT_16_SCIMAP, GEVENT_16_SMITRIG, GEVENT_16_SMICONTROL}, - {GEVENT_17_EVENTENABLE, GEVENT_17_SCITRIG, GEVENT_17_SCILEVEL, GEVENT_17_SMISCIEN, GEVENT_17_SCIS0EN, GEVENT_17_SCIMAP, GEVENT_17_SMITRIG, GEVENT_17_SMICONTROL}, - {GEVENT_18_EVENTENABLE, GEVENT_18_SCITRIG, GEVENT_18_SCILEVEL, GEVENT_18_SMISCIEN, GEVENT_18_SCIS0EN, GEVENT_18_SCIMAP, GEVENT_18_SMITRIG, GEVENT_18_SMICONTROL}, - {GEVENT_19_EVENTENABLE, GEVENT_19_SCITRIG, GEVENT_19_SCILEVEL, GEVENT_19_SMISCIEN, GEVENT_19_SCIS0EN, GEVENT_19_SCIMAP, GEVENT_19_SMITRIG, GEVENT_19_SMICONTROL}, - {GEVENT_20_EVENTENABLE, GEVENT_20_SCITRIG, GEVENT_20_SCILEVEL, GEVENT_20_SMISCIEN, GEVENT_20_SCIS0EN, GEVENT_20_SCIMAP, GEVENT_20_SMITRIG, GEVENT_20_SMICONTROL}, - {GEVENT_21_EVENTENABLE, GEVENT_21_SCITRIG, GEVENT_21_SCILEVEL, GEVENT_21_SMISCIEN, GEVENT_21_SCIS0EN, GEVENT_21_SCIMAP, GEVENT_21_SMITRIG, GEVENT_21_SMICONTROL}, - {GEVENT_22_EVENTENABLE, GEVENT_22_SCITRIG, GEVENT_22_SCILEVEL, GEVENT_22_SMISCIEN, GEVENT_22_SCIS0EN, GEVENT_22_SCIMAP, GEVENT_22_SMITRIG, GEVENT_22_SMICONTROL}, - {GEVENT_23_EVENTENABLE, GEVENT_23_SCITRIG, GEVENT_23_SCILEVEL, GEVENT_23_SMISCIEN, GEVENT_23_SCIS0EN, GEVENT_23_SCIMAP, GEVENT_23_SMITRIG, GEVENT_23_SMICONTROL}, -}; - -#endif /* _GPIO_H_ */ diff --git a/src/mainboard/amd/torpedo/irq_tables.c b/src/mainboard/amd/torpedo/irq_tables.c deleted file mode 100644 index 9ebe58ae65..0000000000 --- a/src/mainboard/amd/torpedo/irq_tables.c +++ /dev/null @@ -1,103 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include -#include -#include - -static void write_pirq_info(struct irq_info *pirq_info, u8 bus, u8 devfn, - u8 link0, u16 bitmap0, u8 link1, u16 bitmap1, - u8 link2, u16 bitmap2, u8 link3, u16 bitmap3, - u8 slot, u8 rfu) -{ - pirq_info->bus = bus; - pirq_info->devfn = devfn; - pirq_info->irq[0].link = link0; - pirq_info->irq[0].bitmap = bitmap0; - pirq_info->irq[1].link = link1; - pirq_info->irq[1].bitmap = bitmap1; - pirq_info->irq[2].link = link2; - pirq_info->irq[2].bitmap = bitmap2; - pirq_info->irq[3].link = link3; - pirq_info->irq[3].bitmap = bitmap3; - pirq_info->slot = slot; - pirq_info->rfu = rfu; -} - -unsigned long write_pirq_routing_table(unsigned long addr) -{ - - struct irq_routing_table *pirq; - struct irq_info *pirq_info; - u32 slot_num; - u8 *v; - - u8 sum = 0; - int i; - - /* Align the table to be 16 byte aligned. */ - addr += 15; - addr &= ~15; - - /* This table must be between 0xf0000 & 0x100000 */ - printk(BIOS_INFO, "Writing IRQ routing tables to 0x%lx...", addr); - - pirq = (void *)(addr); - v = (u8 *) (addr); - - pirq->signature = PIRQ_SIGNATURE; - pirq->version = PIRQ_VERSION; - - pirq->rtr_bus = 0; - pirq->rtr_devfn = PCI_DEVFN(0x14, 4); - - pirq->exclusive_irqs = 0; - - pirq->rtr_vendor = 0x1002; - pirq->rtr_device = 0x4384; - - pirq->miniport_data = 0; - - memset(pirq->rfu, 0, sizeof(pirq->rfu)); - - pirq_info = (void *)(&pirq->checksum + 1); - slot_num = 0; - - /* pci bridge */ - write_pirq_info(pirq_info, 0, PCI_DEVFN(0x14, 4), - 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, - 0); - pirq_info++; - - slot_num++; - - pirq->size = 32 + 16 * slot_num; - - for (i = 0; i < pirq->size; i++) - sum += v[i]; - - sum = pirq->checksum - sum; - - if (sum != pirq->checksum) { - pirq->checksum = sum; - } - - printk(BIOS_INFO, "write_pirq_routing_table done.\n"); - - return (unsigned long)pirq_info; - -} diff --git a/src/mainboard/amd/torpedo/mainboard.c b/src/mainboard/amd/torpedo/mainboard.c deleted file mode 100644 index becfb2537b..0000000000 --- a/src/mainboard/amd/torpedo/mainboard.c +++ /dev/null @@ -1,33 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include - -#define ONE_MB 0x100000 -//#define SMBUS_IO_BASE 0x6000 - - -/************************************************* -* enable the dedicated function in torpedo board. -*************************************************/ -static void mainboard_enable(struct device *dev) -{ - printk(BIOS_INFO, "Mainboard " CONFIG_MAINBOARD_PART_NUMBER " Enable. dev=0x%p\n", dev); -} - -struct chip_operations mainboard_ops = { - .enable_dev = mainboard_enable, -}; diff --git a/src/mainboard/amd/torpedo/mptable.c b/src/mainboard/amd/torpedo/mptable.c deleted file mode 100644 index 811154379f..0000000000 --- a/src/mainboard/amd/torpedo/mptable.c +++ /dev/null @@ -1,232 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#define IO_APIC_ID CONFIG_MAX_CPUS -u32 apicid_sb900; - -u8 picr_data[] = { - 0x0B,0x0B,0x0B,0x0B,0x1F,0x1F,0x1F,0x1F,0xFA,0xF1,0x00,0x00,0x1F,0x1F,0x1F,0x1F, - 0x09,0x1F,0x1F,0x0B,0x1F,0x0B,0x1F,0x1F,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00, - 0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, - 0x0B,0x0B,0x0B,0x0B,0x0B,0x0B,0x0B,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, - 0x0B,0x0B,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, - 0x0B,0x0B,0x0B,0x0B -}; -u8 intr_data[] = { - 0x10,0x11,0x12,0x13,0x14,0x15,0x16,0x17,0x00,0x00,0x00,0x00,0x1F,0x1F,0x1F,0x1F, - 0x09,0x1F,0x1F,0x10,0x1F,0x12,0x1F,0x10,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00, - 0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, - 0x12,0x11,0x12,0x11,0x12,0x11,0x12,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, - 0x11,0x13,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, - 0x10,0x11,0x12,0x13 -}; - -static void smp_add_mpc_entry(struct mp_config_table *mc, unsigned int length) -{ - mc->mpc_length += length; - mc->mpc_entry_count++; -} -static void my_smp_write_bus(struct mp_config_table *mc, - unsigned char id, const char *bustype) -{ - struct mpc_config_bus *mpc; - mpc = smp_next_mpc_entry(mc); - memset(mpc, '\0', sizeof(*mpc)); - mpc->mpc_type = MP_BUS; - mpc->mpc_busid = id; - memcpy(mpc->mpc_bustype, bustype, sizeof(mpc->mpc_bustype)); - smp_add_mpc_entry(mc, sizeof(*mpc)); -} -static void *smp_write_config_table(void *v) -{ - struct mp_config_table *mc; - int bus_isa; - int boot_apic_id; - unsigned int apic_version; - unsigned int cpu_features; - unsigned int cpu_feature_flags; - struct cpuid_result result; - unsigned long cpu_flag; - - mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); - - mptable_init(mc, LOCAL_APIC_ADDR); - memcpy(mc->mpc_oem, "AMD ", 8); - - /*Inagua used dure core CPU with one die */ - boot_apic_id = lapicid(); - apic_version = lapic_read(LAPIC_LVR) & 0xff; - result = cpuid(1); - cpu_features = result.eax; - cpu_feature_flags = result.edx; - cpu_flag = MPC_CPU_ENABLED | MPC_CPU_BOOTPROCESSOR; - smp_write_processor(mc, - 0, apic_version, - cpu_flag, cpu_features, cpu_feature_flags - ); - - cpu_flag = MPC_CPU_ENABLED; - smp_write_processor(mc, - 1, apic_version, - cpu_flag, cpu_features, cpu_feature_flags - ); - - //mptable_write_buses(mc, NULL, &bus_isa); - my_smp_write_bus(mc, 0, "PCI "); - my_smp_write_bus(mc, 1, "PCI "); - bus_isa = 0x02; - my_smp_write_bus(mc, bus_isa, "ISA "); - - /* I/O APICs: APIC ID Version State Address */ - - u8 *dword; - u8 byte; - - ReadPMIO(SB_PMIOA_REG34, AccWidthUint32, &dword); - dword = (u8 *)(((uintptr_t) dword) & 0xFFFFFFF0); - /* Set IO APIC ID onto IO_APIC_ID */ - write32 (dword, 0x00); - write32 (dword + 0x10, IO_APIC_ID << 24); - apicid_sb900 = IO_APIC_ID; - smp_write_ioapic(mc, apicid_sb900, 0x21, dword); - - /* PIC IRQ routine */ - for (byte = 0x0; byte < sizeof(picr_data); byte ++) { - outb(byte, 0xC00); - outb(picr_data[byte], 0xC01); - } - - /* APIC IRQ routine */ - for (byte = 0x0; byte < sizeof(intr_data); byte ++) { - outb(byte | 0x80, 0xC00); - outb(intr_data[byte], 0xC01); - } - - /* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ -#define IO_LOCAL_INT(type, intr, apicid, pin) \ - smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin)); - - //mptable_add_isa_interrupts(mc, bus_isa, apicid_sb900, 0); - /*I/O Ints: Type Trigger Polarity Bus ID IRQ APIC ID PIN# */ - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, apicid_sb900, 0x0); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x1, apicid_sb900, 0x1); - smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x2, apicid_sb900, 0x2); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x3, apicid_sb900, 0x3); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x4, apicid_sb900, 0x4); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0, 0x49, apicid_sb900, 0x11); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x6, apicid_sb900, 0x6); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x7, apicid_sb900, 0x7); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x8, apicid_sb900, 0x8); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x9, apicid_sb900, 0x9); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_isa, 0xa, apicid_sb900, 0xa); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_isa, 0x1c, apicid_sb900, 0x13); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0xc, apicid_sb900, 0xc); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0xd, apicid_sb900, 0xd); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0xe, apicid_sb900, 0xe); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0xf, apicid_sb900, 0xf); - - /* PCI interrupts are level triggered, and are - * associated with a specific bus/device/function tuple. - */ -#define PCI_INT(bus, dev, int_sign, pin) \ - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(int_sign)), apicid_sb900, (pin)) - - /* Internal VGA */ - PCI_INT(0x0, 0x01, 0x0, intr_data[0x02]); - PCI_INT(0x0, 0x01, 0x1, intr_data[0x03]); - - /* SMBUS */ - PCI_INT(0x0, 0x14, 0x0, 0x10); - - /* HD Audio */ - PCI_INT(0x0, 0x14, 0x0, intr_data[0x13]); - - /* USB */ - PCI_INT(0x0, 0x12, 0x0, intr_data[0x30]); - PCI_INT(0x0, 0x12, 0x1, intr_data[0x31]); - PCI_INT(0x0, 0x13, 0x0, intr_data[0x32]); - PCI_INT(0x0, 0x13, 0x1, intr_data[0x33]); - PCI_INT(0x0, 0x16, 0x0, intr_data[0x34]); - PCI_INT(0x0, 0x16, 0x1, intr_data[0x35]); - PCI_INT(0x0, 0x14, 0x2, intr_data[0x36]); - - /* sata */ - PCI_INT(0x0, 0x11, 0x0, intr_data[0x40]); - PCI_INT(0x0, 0x11, 0x0, intr_data[0x41]); - - - /* on board NIC & Slot PCIE. */ - - /* PCI slots */ - struct device *dev = pcidev_on_root(0x14, 4); - if (dev && dev->enabled) { - u8 bus_pci = dev->link_list->secondary; - - /* PCI_SLOT 0. */ - PCI_INT(bus_pci, 0x5, 0x0, 0x14); - PCI_INT(bus_pci, 0x5, 0x1, 0x15); - PCI_INT(bus_pci, 0x5, 0x2, 0x16); - PCI_INT(bus_pci, 0x5, 0x3, 0x17); - - /* PCI_SLOT 1. */ - PCI_INT(bus_pci, 0x6, 0x0, 0x15); - PCI_INT(bus_pci, 0x6, 0x1, 0x16); - PCI_INT(bus_pci, 0x6, 0x2, 0x17); - PCI_INT(bus_pci, 0x6, 0x3, 0x14); - - /* PCI_SLOT 2. */ - PCI_INT(bus_pci, 0x7, 0x0, 0x16); - PCI_INT(bus_pci, 0x7, 0x1, 0x17); - PCI_INT(bus_pci, 0x7, 0x2, 0x14); - PCI_INT(bus_pci, 0x7, 0x3, 0x15); - } - - /* PCIe Lan*/ - PCI_INT(0x0, 0x06, 0x0, 0x13); - - /* FCH PCIe PortA */ - PCI_INT(0x0, 0x15, 0x0, 0x10); - /* FCH PCIe PortB */ - PCI_INT(0x0, 0x15, 0x1, 0x11); - /* FCH PCIe PortC */ - PCI_INT(0x0, 0x15, 0x2, 0x12); - /* FCH PCIe PortD */ - PCI_INT(0x0, 0x15, 0x3, 0x13); - - /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ - IO_LOCAL_INT(mp_ExtINT, 0, MP_APIC_ALL, 0x0); - IO_LOCAL_INT(mp_NMI, 0, MP_APIC_ALL, 0x1); - /* There is no extension information... */ - - /* Compute the checksums */ - return mptable_finalize(mc); -} - -unsigned long write_smp_table(unsigned long addr) -{ - void *v; - v = smp_write_floating_table(addr, 0); - return (unsigned long)smp_write_config_table(v); -} diff --git a/src/mainboard/amd/torpedo/platform_cfg.h b/src/mainboard/amd/torpedo/platform_cfg.h deleted file mode 100644 index 557abecb43..0000000000 --- a/src/mainboard/amd/torpedo/platform_cfg.h +++ /dev/null @@ -1,1220 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - - -#ifndef _PLATFORM_CFG_H_ -#define _PLATFORM_CFG_H_ - -#include - - -/** - * @def BIOS_SIZE - * BIOS_SIZE_{1,2,4,8,16}M - * - * In Hudson-2, default ROM size is 1M Bytes, if your platform ROM - * bigger than 1M you have to set the ROM size outside CIMx module and - * before AGESA module get call. - */ -#ifndef BIOS_SIZE -#define BIOS_SIZE ((CONFIG_COREBOOT_ROMSIZE_KB >> 10) - 1) -#endif /* BIOS_SIZE */ - -/** - * @section SBCIMx_LEGACY_FREE SBCIMx_LEGACY_FREE - * @li 1 - Legacy free enable - * @li 0 - Legacy free disable - */ -#ifndef SBCIMx_LEGACY_FREE - #define SBCIMx_LEGACY_FREE 0 -#endif - -/** - * @section SpiSpeed - * @li 0 - Disable - * @li 1 - Enable - */ -#ifndef SBCIMX_SPI_SPEED - #define SBCIMX_SPI_SPEED 0 -#endif - -/** - * @section SpiFastSpeed - * @li 0 - Disable - * @li 1 - Enable - */ -#ifndef SBCIMX_SPI_FASTSPEED - #define SBCIMX_SPI_FASTSPEED 0 -#endif - -/** - * @section SpiMode - * @li 0 - Disable - * @li 1 - Enable - */ -#ifndef SBCIMX_SPI_MODE - #define SBCIMX_SPI_MODE 0 -#endif - -/** - * @section SpiBurstWrite - * @li 0 - Disable - * @li 1 - Enable - */ -#ifndef SBCIMX_SPI_BURST_WRITE - #define SBCIMX_SPI_BURST_WRITE 0 -#endif - -/** - * @section INCHIP_EC_KBD INCHIP_EC_KBD - * @li 0 - Use SIO PS/2 function. - * @li 1 - Use EC PS/2 function. - */ -#ifndef INCHIP_EC_KBD - #define INCHIP_EC_KBD 0 -#endif - -/** - * @section INCHIP_EC_CHANNEL10 INCHIP_EC_CHANNEL10 - * @li 0 - EC controller NOT support Channel10 - * @li 1 - EC controller support Channel10. - */ -#ifndef INCHIP_EC_CHANNEL10 - #define INCHIP_EC_CHANNEL10 1 -#endif - -/** - * @section Smbus0BaseAddress - */ -// #ifndef SMBUS0_BASE_ADDRESS -// #define SMBUS0_BASE_ADDRESS 0xB00 -// #endif - -/** - * @section Smbus1BaseAddress - */ -// #ifndef SMBUS1_BASE_ADDRESS -// #define SMBUS1_BASE_ADDRESS 0xB21 -// #endif - -/** - * @section SioPmeBaseAddress - */ -// #ifndef SIO_PME_BASE_ADDRESS -// #define SIO_PME_BASE_ADDRESS 0xE00 -// #endif - -/** - * @section WatchDogTimerBase - */ -// #ifndef WATCHDOG_TIMER_BASE_ADDRESS -// #define WATCHDOG_TIMER_BASE_ADDRESS IO_APIC_ADDR -// #endif - -/** - * @section GecShadowRomAddress - */ -#ifndef GEC_ROM_SHADOW_ADDRESS - #define GEC_ROM_SHADOW_ADDRESS 0xFED61000 -#endif - -/** - * @section SpiRomBaseAddress - */ -// #ifndef SPI_BASE_ADDRESS -// #define SPI_BASE_ADDRESS 0xFEC10000 -// #endif - -/** - * @section AcpiPm1EvtBlkAddr - */ -// #ifndef PM1_EVT_BLK_ADDRESS -// #define PM1_EVT_BLK_ADDRESS 0x400 -// #endif - -/** - * @section AcpiPm1CntBlkAddr - */ -// #ifndef PM1_CNT_BLK_ADDRESS -// #define PM1_CNT_BLK_ADDRESS 0x404 -// #endif - -/** - * @section AcpiPmTmrBlkAddr - */ -// #ifndef PM1_TMR_BLK_ADDRESS -// #define PM1_TMR_BLK_ADDRESS 0x408 -// #endif - -/** - * @section CpuControlBlkAddr - */ -// #ifndef CPU_CNT_BLK_ADDRESS -// #define CPU_CNT_BLK_ADDRESS 0x410 -// #endif - -/** - * @section AcpiGpe0BlkAddr - */ -// #ifndef GPE0_BLK_ADDRESS -// #define GPE0_BLK_ADDRESS 0x420 -// #endif - -/** - * @section SmiCmdPortAddr - */ -// #ifndef SMI_CMD_PORT -// #define SMI_CMD_PORT 0xB0 -// #endif - -/** - * @section AcpiPmaCntBlkAddr - */ -// #ifndef ACPI_PMA_CNT_BLK_ADDRESS -// #define ACPI_PMA_CNT_BLK_ADDRESS 0xFE00 -// #endif - -/** - * @section InChipSataController - * @li 0 - Disable - * @li 1 - Enable - */ -#ifndef INCHIP_SATA_CONTROLLER - #define INCHIP_SATA_CONTROLLER 1 -#endif - -/** - * @section SataIdeCombModeChannel - * @li 0 - Primary - * @li 1 - Secondary - * Sata Controller set as primary or - * secondary while Combined Mode is enabled - */ -#ifndef SATA_COMBINE_MODE_CHANNEL - #define SATA_COMBINE_MODE_CHANNEL 0 -#endif - -/** - * @section SataSetMaxGen2 - * @li 0 - Disable - * @li 1 - Enable - * SataController Set to Max Gen2 mode - */ -#ifndef SATA_MAX_GEN2_MODE - #define SATA_MAX_GEN2_MODE 0 -#endif - -/** - * @section SataCombineMode - * @li 0 - Disable - * @li 1 - Enable - * Sata IDE Controller set to Combined Mode - */ -#ifndef SATA_COMBINE_MODE - #define SATA_COMBINE_MODE 0 -#endif - -#define SATA_CLK_RESERVED 9 - -/** - * @section NbSbGen2 - * @li 0 - Disable - * @li 1 - Enable - */ -#ifndef NB_SB_GEN2 - #define NB_SB_GEN2 1 -#endif - -/** - * @section SataInternal100Spread - * @li 0 - Disable - * @li 1 - Enable - */ -#ifndef INCHIP_SATA_INTERNAL_100_SPREAD - #define INCHIP_SATA_INTERNAL_100_SPREAD 0 -#endif - -/** - * @section Cg2Pll - * @li 0 - Disable - * @li 1 - Enable - */ -#ifndef INCHIP_CG2_PLL - #define INCHIP_CG2_PLL 0 -#endif - - - - -/** - * @section SpreadSpectrum - * @li 0 - Disable - * @li 1 - Enable - * Spread Spectrum function - */ -#define INCHIP_SPREAD_SPECTRUM 1 - -/** - * @section INCHIP_USB_CINFIG INCHIP_USB_CINFIG - * - * - Usb Ohci1 Controller is define at BIT0 - * 0:Disable 1:Enable - * (Bus 0 Dev 18 Func0) - * - Usb Ehci1 Controller is define at BIT1 - * 0:Disable 1:Enable - * (Bus 0 Dev 18 Func2) - * - Usb Ohci2 Controller is define at BIT2 - * 0:Disable 1:Enable - * (Bus 0 Dev 19 Func0) - * - Usb Ehci2 Controller is define at BIT3 - * 0:Disable 1:Enable - * (Bus 0 Dev 19 Func2) - * - Usb Ohci3 Controller is define at BIT4 - * 0:Disable 1:Enable - * (Bus 0 Dev 22 Func0) - * - Usb Ehci3 Controller is define at BIT5 - * 0:Disable 1:Enable - * (Bus 0 Dev 22 Func2) - * - Usb Ohci4 Controller is define at BIT6 - * 0:Disable 1:Enable - * (Bus 0 Dev 20 Func5) - */ -#define INCHIP_USB_CINFIG 0x7F -#define INCHIP_USB_OHCI1_CINFIG 0x01 -#define INCHIP_USB_OHCI2_CINFIG 0x01 -#if CONFIG(ONBOARD_USB30) -#define INCHIP_USB_OHCI3_CINFIG 0x00 -#else -#define INCHIP_USB_OHCI3_CINFIG 0x01 -#endif -#define INCHIP_USB_OHCI4_CINFIG 0x01 -#define INCHIP_USB_EHCI1_CINFIG 0x01 -#define INCHIP_USB_EHCI2_CINFIG 0x01 -#define INCHIP_USB_EHCI3_CINFIG 0x01 - -/** - * @section INCHIP_SATA_MODE INCHIP_SATA_MODE - * @li 000 - Native IDE mode - * @li 001 - RAID mode - * @li 010 - AHCI mode - * @li 011 - Legacy IDE mode - * @li 100 - IDE->AHCI mode - * @li 101 - AHCI mode as 7804 ID (AMD driver) - * @li 110 - IDE->AHCI mode as 7804 ID (AMD driver) - */ -#define INCHIP_SATA_MODE 0 - -/** - * @section INCHIP_IDE_MODE INCHIP_IDE_MODE - * @li 0 - Legacy IDE mode - * @li 1 - Native IDE mode - * ** DO NOT ALLOW SATA & IDE use same mode ** - */ -#define INCHIP_IDE_MODE 1 - -#define SATA_PORT_MULT_CAP_RESERVED 1 - -/** - * @section INCHIP_AZALIA_CONTROLLER INCHIP_AZALIA_CONTROLLER - * @li 0 - Auto : Detect Azalia controller automatically. - * @li 1 - Disable : Disable Azalia controller. - * @li 2 - Enable : Enable Azalia controller. - */ -#define INCHIP_AZALIA_CONTROLLER 2 -#define AZALIA_AUTO 0 -#define AZALIA_DISABLE 1 -#define AZALIA_ENABLE 2 - -/** - * @section INCHIP_AZALIA_PIN_CONFIG INCHIP_AZALIA_PIN_CONFIG - * @li 0 - disable - * @li 1 - enable - */ -#define INCHIP_AZALIA_PIN_CONFIG 1 - -/** - * @section AZALIA_PIN_CONFIG AZALIA_PIN_CONFIG - * - * SDIN0 is define at BIT0 & BIT1 - * - 00: GPIO PIN - * - 01: Reserved - * - 10: As a Azalia SDIN pin - * SDIN1 is define at BIT2 & BIT3 - * - 00: GPIO PIN - * - 01: Reserved - * - 10: As a Azalia SDIN pin - * SDIN2 is define at BIT4 & BIT5 - * - 00: GPIO PIN - * - 01: Reserved - * - 10: As a Azalia SDIN pin - * SDIN3 is define at BIT6 & BIT7 - * - 00: GPIO PIN - * - 01: Reserved - * - 10: As a Azalia SDIN pin - */ -#define AZALIA_PIN_CONFIG 0x2A - -/** - * @section AzaliaSnoop - * @li 0 - disable - * @li 1 - enable * - */ -#define INCHIP_AZALIA_SNOOP 0x01 - -/** - * @section NCHIP_GEC_CONTROLLER - * @li 0 - Enable * - * @li 1 - Disable - */ -#define INCHIP_GEC_CONTROLLER 0x00 - -/** - * @section SB_HPET_TIMER SB_HPET_TIMER - * @li 0 - Disable - * @li 1 - Enable - */ -#define SB_HPET_TIMER 1 - -/** - * @section SB_GPP_CONTROLLER SB_GPP_CONTROLLER - * @li 0 - Disable - * @li 1 - Enable - */ -#define SB_GPP_CONTROLLER 1 - -/** - * @section GPP_LINK_CONFIG GPP_LINK_CONFIG - * @li 0000 - Port ABCD -> 4:0:0:0 - * @li 0001 - N/A - * @li 0010 - Port ABCD -> 2:2:0:0 - * @li 0011 - Port ABCD -> 2:1:1:0 - * @li 0100 - Port ABCD -> 1:1:1:1 - */ -#define GPP_LINK_CONFIG 4 - -/** - * @section SB_GPP_PORT0 SB_GPP_PORT0 - * @li 0 - Disable - * @li 1 - Enable - */ -#define SB_GPP_PORT0 1 - -/** - * @section SB_GPP_PORT1 SB_GPP_PORT1 - * @li 0 - Disable - * @li 1 - Enable - */ -#define SB_GPP_PORT1 1 - -/** - * @section SB_GPP_PORT2 SB_GPP_PORT2 - * @li 0 - Disable - * @li 1 - Enable - */ -#define SB_GPP_PORT2 1 - -/** - * @section SB_GPP_PORT3 SB_GPP_PORT3 - * @li 0 - Disable - * @li 1 - Enable - */ -#define SB_GPP_PORT3 1 - -/** - * @section SB_IR_CONTROLLER - * @li 00 - disable - * @li 01 - Rx and Tx0 - * @li 10 - Rx and Tx1 - * @li 11 - Rx and both Tx0,Tx1 - */ -#define SB_IR_CONTROLLER 3 - -/** - * @section INCHIP_USB_PHY_POWER_DOWN - * @li 0 - Disable - * @li 1 - Enable - */ -#define INCHIP_USB_PHY_POWER_DOWN 0 - -/** - * @section INCHIP_NATIVE_PCIE_SUPPOORT - * @li 0 - Disable - * @li 1 - Enable - */ -#define INCHIP_NATIVE_PCIE_SUPPOORT 1 - -/** - * @section INCHIP_NB_SB_GEN2 - * @li 0 - Disable - * @li 1 - Enable - */ -#define INCHIP_NB_SB_GEN2 1 - -/** - * @section INCHIP_GPP_GEN2 - * @li 0 - Disable - * @li 1 - Enable - */ -#define INCHIP_GPP_GEN2 1 - -/** - * @section INCHIP_GPP_MEMORY_WRITE_IMPROVE - * @li 0 - Disable - * @li 1 - Enable - */ -#define INCHIP_GPP_MEMORY_WRITE_IMPROVE 1 - -/** - * @section INCHIP_GEC_PHY_STATUS - * @li 0 - Gb PHY Mode * - * @li 1 - 100/10 PHY Mode - */ -#define INCHIP_GEC_PHY_STATUS 0 - -/** - * @section INCHIP_GEC_POWER_POLICY - * @li 0 - S3/S5 - * @li 1 - S5 - * @li 2 - S3 - * @li 3 - Never power down * - */ -#define INCHIP_GEC_POWER_POLICY 3 - -/** - * @section INCHIP_GEC_DEBUGBUS - * @li 0 - Disable * - * @li 1 - Enable - */ -#define INCHIP_GEC_DEBUGBUS 0 - -/** - * @section SATA_MAX_GEN2_MODE SATA_MAX_GEN2_MODE - * @li 0 - Disable * - * @li 1 - Enable - * SataController Set to Max Gen2 mode - */ -#define SATA_MAX_GEN2_MODE 0 - -/** - * @section INCHIP_SATA_AGGR_LINK_PM_CAP - * @li 0 - Disable - * @li 1 - Enable * - * SataController Set to aggressive link PM capability - */ -#define INCHIP_SATA_AGGR_LINK_PM_CAP 0 - -/** - * @section INCHIP_SATA_PORT_MULT_CAP - * @li 0 - Disable - * @li 1 - Enable * - * SataController Set to Port Multiple capability - */ -#define INCHIP_SATA_PORT_MULT_CAP 1 - -/** - * @section INCHIP_SATA_PSC_CAP - * @li 0 - Disable - * @li 1 - Enable * -*/ -#define INCHIP_SATA_PSC_CAP 0 - -/** - * @section INCHIP_SATA_SSC_CAP - * @li 0 - Disable - * @li 1 - Enable * - */ -#define INCHIP_SATA_SSC_CAP 0 - -/** - * @section INCHIP_SATA_CLK_AUTO_OFF - * @li 0 - Disable - * @li 1 - Enable * - */ -#define INCHIP_SATA_CLK_AUTO_OFF 1 - -/** - * @section INCHIP_SATA_FIS_BASE_SW - * @li 0 - Disable - * @li 1 - Enable * - */ -#define INCHIP_SATA_FIS_BASE_SW 1 - -/** - * @section INCHIP_SATA_CCC_SUPPORT - * @li 0 - Disable - * @li 1 - Enable * - */ -#define INCHIP_SATA_CCC_SUPPORT 1 - -/** - * @section INCHIP_SATA_MSI_CAP - * @li 0 - Disable - * @li 1 - Enable * - */ -#define INCHIP_SATA_MSI_CAP 1 - -/** - * @section CIMXSB_SATA_TARGET_8DEVICE_CAP - * @li 0 - Disable * - * @li 1 - Enable - */ -#define CIMXSB_SATA_TARGET_8DEVICE_CAP 0 - -/** - * @section SATA_DISABLE_GENERIC_MODE - * @li 0 - Disable * - * @li 1 - Enable - */ -#define SATA_DISABLE_GENERIC_MODE_CAP 0 - -/** - * @section SATA_AHCI_ENCLOSURE_CAP - * @li 0 - Disable * - * @li 1 - Enable - */ -#define SATA_AHCI_ENCLOSURE_CAP 0 - -/** - * @section SataForceRaid (RISD5 mode) - * @li 0 - Disable * - * @li 1 - Enable - */ -#define INCHIP_SATA_FORCE_RAID5 0 - -/** - * @section SATA_GPIO_0_CAP - * @li 0 - Disable * - * @li 1 - Enable - */ -#define SATA_GPIO_0_CAP 0 - -/** - * @section SATA_GPIO_1_CAP - * @li 0 - Disable * - * @li 1 - Enable - */ -#define SATA_GPIO_1_CAP 0 - -/** - * @section SataPhyPllShutDown - * @li 0 - Disable - * @li 1 - Enable * - */ -#define SATA_PHY_PLL_SHUTDOWN 1 - -/** - * @section ImcEnableOverWrite - * @li 0 - Disable - * @li 1 - Enable - */ -#define IMC_ENABLE_OVER_WRITE 0 - -/** - * @section UsbMsi - * @li 0 - Disable - * @li 1 - Enable - */ -#define USB_MSI 0 - -/** - * @section HdAudioMsi - * @li 0 - Disable - * @li 1 - Enable - */ -#define HDAUDIO_MSI 0 - -/** - * @section LpcMsi - * @li 0 - Disable - * @li 1 - Enable - */ -#define LPC_MSI 0 - -/** - * @section PcibMsi - * @li 0 - Disable - * @li 1 - Enable - */ -#define PCIB_MSI 0 - -/** - * @section AbMsi - * @li 0 - Disable - * @li 1 - Enable - */ -#define AB_MSI 0 - -/** - * @section GecShadowRomBase - * @li 0 - Disable - * @li 1 - Enable * - */ -#define GEC_SHADOWROM_BASE 0xFED61000 - -/** - * @section SataController - * @li 0 - Disable - * @li 1 - Enable * - */ -#define SATA_CONTROLLER 1 - -/** - * @section SataIdeCombMdPriSecOpt - * @li 0 - Disable - * @li 1 - Enable - */ -#define SATA_IDE_COMBMD_PRISEC_OPT 0 - -/** - * @section SataIdeCombinedMode - * @li 0 - Disable - * @li 1 - Enable - */ -#define SATA_IDECOMBINED_MODE 0 - -/** - * @section sdConfig - * @li 0 - Disable - * @li 1 - Enable * - */ -#define SB_SD_CONFIG 1 - -/** - * @section sdSpeed - * @li 0 - Disable - * @li 1 - Enable * - */ -#define SB_SD_SPEED 1 - -/** - * @section sdBitwidth - * @li 0 - Disable - * @li 1 - Enable * - */ -#define SB_SD_BITWIDTH 1 - -/** - * @section SataDisUnusedIdePChannel - * @li 0 - Disable - * @li 1 - Enable - */ -#define SATA_DISUNUSED_IDE_P_CHANNEL 0 - -/** - * @section SataDisUnusedIdeSChannel - * @li 0 - Disable - * @li 1 - Enable - */ -#define SATA_DISUNUSED_IDE_S_CHANNEL 0 - -/** - * @section IdeDisUnusedIdePChannel - * @li 0 - Disable - * @li 1 - Enable - */ -#define IDE_DISUNUSED_IDE_P_CHANNEL 0 - -/** - * @section IdeDisUnusedIdeSChannel - * @li 0 - Disable - * @li 1 - Enable - */ -#define IDE_DISUNUSED_IDE_S_CHANNEL 0 - -/** - * @section SataEspPort0 - * @li 0 - Disable - * @li 1 - Enable - */ -#define SATA_ESP_PORT0 0 - -/** - * @section SataEspPort1 - * @li 0 - Disable - * @li 1 - Enable - */ -#define SATA_ESP_PORT1 0 - -/** - * @section SataEspPort2 - * @li 0 - Disable - * @li 1 - Enable - */ -#define SATA_ESP_PORT2 0 - -/** - * @section SataEspPort3 - * @li 0 - Disable - * @li 1 - Enable - */ -#define SATA_ESP_PORT3 0 - -/** - * @section SataEspPort4 - * @li 0 - Disable - * @li 1 - Enable - */ -#define SATA_ESP_PORT4 0 - -/** - * @section SataEspPort5 - * @li 0 - Disable - * @li 1 - Enable - */ -#define SATA_ESP_PORT5 0 - -/** - * @section SataEspPort6 - * @li 0 - Disable - * @li 1 - Enable - */ -#define SATA_ESP_PORT6 0 - -/** - * @section SataEspPort7 - * @li 0 - Disable - * @li 1 - Enable - */ -#define SATA_ESP_PORT7 0 - -/** - * @section SataPortPower0 - * @li 0 - Disable - * @li 1 - Enable - */ -#define SATA_PORT_POWER_PORT0 0 - -/** - * @section SataPortPower1 - * @li 0 - Disable - * @li 1 - Enable - */ -#define SATA_PORT_POWER_PORT1 0 - -/** - * @section SataPortPower2 - * @li 0 - Disable - * @li 1 - Enable - */ -#define SATA_PORT_POWER_PORT2 0 - -/** - * @section SataPortPower3 - * @li 0 - Disable - * @li 1 - Enable - */ -#define SATA_PORT_POWER_PORT3 0 - -/** - * @section SataPortPower4 - * @li 0 - Disable - * @li 1 - Enable - */ -#define SATA_PORT_POWER_PORT4 0 - -/** - * @section SataPortPower5 - * @li 0 - Disable - * @li 1 - Enable - */ -#define SATA_PORT_POWER_PORT5 0 - -/** - * @section SataPortPower6 - * @li 0 - Disable - * @li 1 - Enable - */ -#define SATA_PORT_POWER_PORT6 0 - -/** - * @section SataPortPower7 - * @li 0 - Disable - * @li 1 - Enable - */ -#define SATA_PORT_POWER_PORT7 0 - -/** - * @section SataPortMd0 - * @li 0 - Disable - * @li 1 - Enable - */ -#define SATA_PORTMODE_PORT0 3 - -/** - * @section SataPortMd1 - * @li 0 - Disable - * @li 1 - Enable - */ -#define SATA_PORTMODE_PORT1 3 - -/** - * @section SataPortMd2 - * @li 0 - Disable - * @li 1 - Enable - */ -#define SATA_PORTMODE_PORT2 3 - -/** - * @section SataPortMd3 - * @li 0 - Disable - * @li 1 - Enable - */ -#define SATA_PORTMODE_PORT3 3 - -/** - * @section SataPortMd4 - * @li 0 - Disable - * @li 1 - Enable - */ -#define SATA_PORTMODE_PORT4 0 - -/** - * @section SataPortMd5 - * @li 0 - Disable - * @li 1 - Enable - */ -#define SATA_PORTMODE_PORT5 0 - -/** - * @section SataPortMd6 - * @li 0 - Disable - * @li 1 - Enable - */ -#define SATA_PORTMODE_PORT6 0 - -/** - * @section SataPortMd7 - * @li 0 - Disable - * @li 1 - Enable - */ -#define SATA_PORTMODE_PORT7 0 - -/** - * @section SataHotRemovelEnh0 - * @li 0 - Disable - * @li 1 - Enable - */ -#define SATA_HOTREMOVEL_ENH_PORT0 0 - -/** - * @section SataHotRemovelEnh1 - * @li 0 - Disable - * @li 1 - Enable - */ -#define SATA_HOTREMOVEL_ENH_PORT1 0 - -/** - * @section SataHotRemovelEnh2 - * @li 0 - Disable - * @li 1 - Enable - */ -#define SATA_HOTREMOVEL_ENH_PORT2 0 - -/** - * @section SataHotRemovelEnh3 - * @li 0 - Disable - * @li 1 - Enable - */ -#define SATA_HOTREMOVEL_ENH_PORT3 0 - -/** - * @section SataHotRemovelEnh4 - * @li 0 - Disable - * @li 1 - Enable - */ -#define SATA_HOTREMOVEL_ENH_PORT4 0 - -/** - * @section SataHotRemovelEnh5 - * @li 0 - Disable - * @li 1 - Enable - */ -#define SATA_HOTREMOVEL_ENH_PORT5 0 - -/** - * @section SataHotRemovelEnh6 - * @li 0 - Disable - * @li 1 - Enable - */ -#define SATA_HOTREMOVEL_ENH_PORT6 0 - -/** - * @section SataHotRemovelEnh7 - * @li 0 - Disable - * @li 1 - Enable - */ -#define SATA_HOTREMOVEL_ENH_PORT7 0 - -/** - * @section XhciSwitch - * @li 0 - Disable - * @li 1 - Enable - */ -#if CONFIG(ONBOARD_USB30) - #define SB_XHCI_SWITCH 0 -#else -#define SB_XHCI_SWITCH 1 -#endif - -/** - * @section FrontPanelDetected - * @li 0 - Disable - * @li 1 - Enable - */ -#define INCHIP_FRONT_PANEL_DETECTED 0 - -/** - * @section AnyHT200MhzLink - * @li 0 - Disable - * @li 1 - Enable - */ -#define INCHIP_ANY_HT_200MHZ_LINK 0 - -/** - * @section PcibClkStopOverride - * @li 0 - Disable - * @li 1 - Enable - */ -#define INCHIP_PCIB_CLK_STOP_OVERRIDE 0 - -/** - * @section GppLinkConfig - * @li 0000 - Port ABCD -> 4:0:0:0 - * @li 0001 - N/A - * @li 0010 - Port ABCD -> 2:2:0:0 - * @li 0011 - Port ABCD -> 2:1:1:0 - * @li 0100 - Port ABCD -> 1:1:1:1 - */ -#define INCHIP_GPP_LINK_CONFIG 4 - -/** - * @section GppUnhidePorts - * @li 0 - Disable - * @li 1 - Enable - */ -#define INCHIP_GPP_UNHIDE_PORTS 0 - -/** - * @section GppPortAspm - * @li 01 - Disabled - * @li 01 - L0s - * @li 10 - L1 - * @li 11 - L0s + L1 - */ -#define INCHIP_GPP_PORT_ASPM 3 - -/** - * @section GppLaneReversal - * @li 0 - Disable - * @li 1 - Enable - */ -#define INCHIP_GPP_LANEREVERSAL 0 - -/** - * @section AlinkPhyPllPowerDown - * @li 0 - Disable - * @li 1 - Enable - */ -#define INCHIP_ALINK_PHY_PLL_POWER_DOWN 1 - -/** - * @section GppPhyPllPowerDown - * @li 0 - Disable - * @li 1 - Enable - */ -#define INCHIP_GPP_PHY_PLL_POWER_DOWN 1 - -/** - * @section GppDynamicPowerSaving - * @li 0 - Disable - * @li 1 - Enable - */ -#define INCHIP_GPP_DYNAMIC_POWER_SAVING 1 - -/** - * @section PcieAER - * @li 0 - Disable - * @li 1 - Enable - */ -#define INCHIP_PCIE_AER 0 - -/** - * @section PcieRAS - * @li 0 - Disable - * @li 1 - Enable - */ -#define INCHIP_PCIE_RAS 0 - -/** - * @section GppHardwareDowngrade - * @li 0 - Disable - * @li 1 - Enable - */ -#define INCHIP_GPP_HARDWARE_DOWNGRADE 0 - -/** - * @section GppToggleReset - * @li 0 - Disable - * @li 1 - Enable - */ -#define INCHIP_GPP_TOGGLE_RESET 0 - -/** - * @section SbPcieOrderRule - * @li 00 - Disable - * @li 01 - Rule 1 - * @li 10 - Rule 2 - */ -#define INCHIP_SB_PCIE_ORDER_RULE 2 - -/** - * @section AcDcMsg - * @li 0 - Disable - * @li 1 - Enable - */ -#define INCHIP_ACDC_MSG 0 - -/** - * @section TimerTickTrack - * @li 0 - Disable - * @li 1 - Enable - */ -#define INCHIP_TIMER_TICK_TRACK 1 - -/** - * @section ClockInterruptTag - * @li 0 - Disable - * @li 1 - Enable - */ -#define INCHIP_CLOCK_INTERRUPT_TAG 1 - -/** - * @section OhciTrafficHanding - * @li 0 - Disable - * @li 1 - Enable - */ -#define INCHIP_OHCI_TRAFFIC_HANDING 0 - -/** - * @section EhciTrafficHanding - * @li 0 - Disable - * @li 1 - Enable - */ -#define INCHIP_EHCI_TRAFFIC_HANDING 0 - -/** - * @section FusionMsgCMultiCore - * @li 0 - Disable - * @li 1 - Enable - */ -#define INCHIP_FUSION_MSGC_MULTICORE 0 - -/** - * @section FusionMsgCStage - * @li 0 - Disable - * @li 1 - Enable - */ -#define INCHIP_FUSION_MSGC_STAGE 0 - -/** - * @section ALinkClkGateOff - * @li 0 - Disable - * @li 1 - Enable - */ -#define INCHIP_ALINK_CLK_GATE_OFF 0 - -/** - * @section BLinkClkGateOff - * @li 0 - Disable - * @li 1 - Enable - */ -#define INCHIP_BLINK_CLK_GATE_OFF 0 - -/** - * @section SlowSpeedABlinkClock - * @li 0 - Disable - * @li 1 - Enable - */ -#define INCHIP_SLOW_SPEED_ABLINK_CLOCK 0 - -/** - * @section AbClockGating - * @li 0 - Disable - * @li 1 - Enable - */ -#define INCHIP_AB_CLOCK_GATING 1 - -/** - * @section GppClockGating - * @li 0 - Disable - * @li 1 - Enable - */ -#define INCHIP_GPP_CLOCK_GATING 1 - -/** - * @section L1TimerOverwrite - * @li 0 - Disable - * @li 1 - Enable - */ -#define INCHIP_L1_TIMER_OVERWRITE 0 - -/** - * @section UmiDynamicSpeedChange - * @li 0 - Disable - * @li 1 - Enable - */ -#define INCHIP_UMI_DYNAMIC_SPEED_CHANGE 0 - -/** - * @section SbAlinkGppTxDriverStrength - * @li 0 - Disable - * @li 1 - Enable - */ -#define INCHIP_ALINK_GPP_TX_DRV_STRENGTH 0 - -/** - * @section StressResetMode - * @li 0 - Disable - * @li 1 - Enable - */ -#define INCHIP_STRESS_RESET_MODE 0 - -#ifndef SB_PCI_CLOCK_RESERVED - #define SB_PCI_CLOCK_RESERVED 0x0 //according to CIMx change 0x1F -#endif - -/** - * @brief South Bridge CIMx configuration - * - */ -void sb900_cimx_config(AMDSBCFG *sb_cfg); -void SbPowerOnInit_Config(AMDSBCFG *sb_cfg); - -/** - * @brief Entry point of Southbridge CIMx callout - * - * prototype UINT32 (*SBCIM_HOOK_ENTRY)(UINT32 Param1, UINT32 Param2, void* pConfig) - * - * @param[in] func Southbridge CIMx Function ID. - * @param[in] data Southbridge Input Data. - * @param[in] config Southbridge configuration structure pointer. - * - */ -u32 sb900_callout_entry(u32 func, u32 data, void* config); - -// definition for function in gpio.c -void gpioEarlyInit (void); - -#endif diff --git a/src/mainboard/amd/torpedo/pmio.h b/src/mainboard/amd/torpedo/pmio.h deleted file mode 100644 index ed38eed569..0000000000 --- a/src/mainboard/amd/torpedo/pmio.h +++ /dev/null @@ -1,30 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - - -#ifndef _PMIO_H_ -#define _PMIO_H_ - -#define PM_INDEX 0xCD6 -#define PM_DATA 0xCD7 -#define PM2_INDEX 0xCD0 -#define PM2_DATA 0xCD1 - -void pm_iowrite(u8 reg, u8 value); -u8 pm_ioread(u8 reg); -void pm2_iowrite(u8 reg, u8 value); -u8 pm2_ioread(u8 reg); - -#endif diff --git a/src/mainboard/amd/torpedo/romstage.c b/src/mainboard/amd/torpedo/romstage.c deleted file mode 100644 index 3454ef8744..0000000000 --- a/src/mainboard/amd/torpedo/romstage.c +++ /dev/null @@ -1,25 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include - -#define SERIAL_DEV PNP_DEV(0x2e, SMSCSUPERIO_SP1) - -void board_BeforeAgesa(struct sysinfo *cb) -{ - kbc1100_early_init(0x2e); - kbc1100_early_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); -} From 2c08ea7cfcb24240e41ad0f75be35f9e2967b3d1 Mon Sep 17 00:00:00 2001 From: Joe Moore Date: Mon, 21 Oct 2019 01:03:08 -0600 Subject: [PATCH 0265/1242] cpu/nb/sb: Remove fam12 With removal of Torpedo mainboard, this code is no longer necessary. This also removes fam12 support from northbridge and SB900 from southbridge. Change-Id: I8a30461278844d0d9ad4320f0e952774c4fd644f Signed-off-by: Joe Moore Reviewed-on: https://review.coreboot.org/c/coreboot/+/36188 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth --- src/cpu/amd/agesa/Kconfig | 2 - src/cpu/amd/agesa/Makefile.inc | 1 - src/cpu/amd/agesa/family12/Kconfig | 24 - src/cpu/amd/agesa/family12/Makefile.inc | 43 - src/cpu/amd/agesa/family12/chip_name.c | 18 - src/cpu/amd/agesa/family12/fixme.c | 103 --- src/cpu/amd/agesa/family12/model_12_init.c | 106 --- src/cpu/amd/agesa/family12/romstage.c | 27 - src/northbridge/amd/agesa/Makefile.inc | 1 - src/northbridge/amd/agesa/family12/Kconfig | 35 - .../amd/agesa/family12/Makefile.inc | 21 - src/northbridge/amd/agesa/family12/dimmSpd.c | 80 -- .../amd/agesa/family12/northbridge.c | 834 ------------------ .../amd/agesa/family12/state_machine.c | 87 -- src/southbridge/amd/cimx/Kconfig | 1 - src/southbridge/amd/cimx/Makefile.inc | 3 - src/southbridge/amd/cimx/sb900/Amd.h | 377 -------- src/southbridge/amd/cimx/sb900/AmdSbLib.h | 160 ---- src/southbridge/amd/cimx/sb900/Kconfig | 54 -- src/southbridge/amd/cimx/sb900/Makefile.inc | 34 - src/southbridge/amd/cimx/sb900/SbPlatform.h | 148 ---- .../amd/cimx/sb900/amd_pci_int_defs.h | 70 -- .../amd/cimx/sb900/amd_pci_int_types.h | 29 - src/southbridge/amd/cimx/sb900/bootblock.c | 58 -- src/southbridge/amd/cimx/sb900/cfg.c | 298 ------- src/southbridge/amd/cimx/sb900/chip.h | 36 - src/southbridge/amd/cimx/sb900/early.c | 138 --- src/southbridge/amd/cimx/sb900/gpio_oem.h | 66 -- src/southbridge/amd/cimx/sb900/late.c | 457 ---------- src/southbridge/amd/cimx/sb900/lpc.c | 182 ---- src/southbridge/amd/cimx/sb900/lpc.h | 27 - src/southbridge/amd/cimx/sb900/ramtop.c | 43 - src/southbridge/amd/cimx/sb900/reset.c | 48 - src/southbridge/amd/cimx/sb900/sb_cimx.h | 45 - src/southbridge/amd/cimx/sb900/smbus.c | 260 ------ src/southbridge/amd/cimx/sb900/smbus.h | 71 -- src/southbridge/amd/cimx/sb900/smbus_spd.c | 177 ---- 37 files changed, 4164 deletions(-) delete mode 100644 src/cpu/amd/agesa/family12/Kconfig delete mode 100644 src/cpu/amd/agesa/family12/Makefile.inc delete mode 100644 src/cpu/amd/agesa/family12/chip_name.c delete mode 100644 src/cpu/amd/agesa/family12/fixme.c delete mode 100644 src/cpu/amd/agesa/family12/model_12_init.c delete mode 100644 src/cpu/amd/agesa/family12/romstage.c delete mode 100644 src/northbridge/amd/agesa/family12/Kconfig delete mode 100644 src/northbridge/amd/agesa/family12/Makefile.inc delete mode 100644 src/northbridge/amd/agesa/family12/dimmSpd.c delete mode 100644 src/northbridge/amd/agesa/family12/northbridge.c delete mode 100644 src/northbridge/amd/agesa/family12/state_machine.c delete mode 100644 src/southbridge/amd/cimx/sb900/Amd.h delete mode 100644 src/southbridge/amd/cimx/sb900/AmdSbLib.h delete mode 100644 src/southbridge/amd/cimx/sb900/Kconfig delete mode 100644 src/southbridge/amd/cimx/sb900/Makefile.inc delete mode 100644 src/southbridge/amd/cimx/sb900/SbPlatform.h delete mode 100644 src/southbridge/amd/cimx/sb900/amd_pci_int_defs.h delete mode 100644 src/southbridge/amd/cimx/sb900/amd_pci_int_types.h delete mode 100644 src/southbridge/amd/cimx/sb900/bootblock.c delete mode 100644 src/southbridge/amd/cimx/sb900/cfg.c delete mode 100644 src/southbridge/amd/cimx/sb900/chip.h delete mode 100644 src/southbridge/amd/cimx/sb900/early.c delete mode 100644 src/southbridge/amd/cimx/sb900/gpio_oem.h delete mode 100644 src/southbridge/amd/cimx/sb900/late.c delete mode 100644 src/southbridge/amd/cimx/sb900/lpc.c delete mode 100644 src/southbridge/amd/cimx/sb900/lpc.h delete mode 100644 src/southbridge/amd/cimx/sb900/ramtop.c delete mode 100644 src/southbridge/amd/cimx/sb900/reset.c delete mode 100644 src/southbridge/amd/cimx/sb900/sb_cimx.h delete mode 100644 src/southbridge/amd/cimx/sb900/smbus.c delete mode 100644 src/southbridge/amd/cimx/sb900/smbus.h delete mode 100644 src/southbridge/amd/cimx/sb900/smbus_spd.c diff --git a/src/cpu/amd/agesa/Kconfig b/src/cpu/amd/agesa/Kconfig index d14eb4054f..b6b757f6ae 100644 --- a/src/cpu/amd/agesa/Kconfig +++ b/src/cpu/amd/agesa/Kconfig @@ -13,7 +13,6 @@ config CPU_AMD_AGESA bool - default y if CPU_AMD_AGESA_FAMILY12 default y if CPU_AMD_AGESA_FAMILY14 default y if CPU_AMD_AGESA_FAMILY15_TN default y if CPU_AMD_AGESA_FAMILY16_KB @@ -67,7 +66,6 @@ config S3_DATA_SIZE endif # CPU_AMD_AGESA -source src/cpu/amd/agesa/family12/Kconfig source src/cpu/amd/agesa/family14/Kconfig source src/cpu/amd/agesa/family15tn/Kconfig source src/cpu/amd/agesa/family16kb/Kconfig diff --git a/src/cpu/amd/agesa/Makefile.inc b/src/cpu/amd/agesa/Makefile.inc index d99f2b051f..4a23ac4838 100644 --- a/src/cpu/amd/agesa/Makefile.inc +++ b/src/cpu/amd/agesa/Makefile.inc @@ -10,7 +10,6 @@ # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the # GNU General Public License for more details. # -subdirs-$(CONFIG_CPU_AMD_AGESA_FAMILY12) += family12 subdirs-$(CONFIG_CPU_AMD_AGESA_FAMILY14) += family14 subdirs-$(CONFIG_CPU_AMD_AGESA_FAMILY15_TN) += family15tn subdirs-$(CONFIG_CPU_AMD_AGESA_FAMILY16_KB) += family16kb diff --git a/src/cpu/amd/agesa/family12/Kconfig b/src/cpu/amd/agesa/family12/Kconfig deleted file mode 100644 index 0324d129a3..0000000000 --- a/src/cpu/amd/agesa/family12/Kconfig +++ /dev/null @@ -1,24 +0,0 @@ -# -# This file is part of the coreboot project. -# -# This program is free software; you can redistribute it and/or modify -# it under the terms of the GNU General Public License as published by -# the Free Software Foundation; version 2 of the License. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# - -config CPU_AMD_AGESA_FAMILY12 - bool - select X86_AMD_FIXED_MTRRS - -if CPU_AMD_AGESA_FAMILY12 - -config CPU_ADDR_BITS - int - default 48 - -endif diff --git a/src/cpu/amd/agesa/family12/Makefile.inc b/src/cpu/amd/agesa/family12/Makefile.inc deleted file mode 100644 index 1a7465d81f..0000000000 --- a/src/cpu/amd/agesa/family12/Makefile.inc +++ /dev/null @@ -1,43 +0,0 @@ -#***************************************************************************** -# -# Copyright (c) 2011, Advanced Micro Devices, Inc. -# All rights reserved. -# -# Redistribution and use in source and binary forms, with or without -# modification, are permitted provided that the following conditions are met: -# * Redistributions of source code must retain the above copyright -# notice, this list of conditions and the following disclaimer. -# * Redistributions in binary form must reproduce the above copyright -# notice, this list of conditions and the following disclaimer in the -# documentation and/or other materials provided with the distribution. -# * Neither the name of Advanced Micro Devices, Inc. nor the names of -# its contributors may be used to endorse or promote products derived -# from this software without specific prior written permission. -# -# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -# ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -# WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -# DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY -# DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -# (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -# LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -# ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -# SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -# -#***************************************************************************** - -romstage-y += fixme.c -romstage-y += romstage.c - -ramstage-y += fixme.c -ramstage-y += chip_name.c -ramstage-y += model_12_init.c - -subdirs-y += ../../mtrr -subdirs-y += ../../../x86/tsc -subdirs-y += ../../../x86/lapic -subdirs-y += ../../../x86/cache -subdirs-y += ../../../x86/mtrr -subdirs-y += ../../../x86/pae -subdirs-y += ../../../x86/smm diff --git a/src/cpu/amd/agesa/family12/chip_name.c b/src/cpu/amd/agesa/family12/chip_name.c deleted file mode 100644 index ca3c39e0ab..0000000000 --- a/src/cpu/amd/agesa/family12/chip_name.c +++ /dev/null @@ -1,18 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include - -struct chip_operations cpu_amd_agesa_family12_ops = { - CHIP_NAME("AMD CPU Family 12h") -}; diff --git a/src/cpu/amd/agesa/family12/fixme.c b/src/cpu/amd/agesa/family12/fixme.c deleted file mode 100644 index c1d4c7d1a6..0000000000 --- a/src/cpu/amd/agesa/family12/fixme.c +++ /dev/null @@ -1,103 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include -#include -#include -#include - -void amd_initcpuio(void) -{ - UINT64 MsrReg; - UINT32 PciData; - PCI_ADDR PciAddress; - AMD_CONFIG_PARAMS StdHeader; - - /* Enable MMIO on AMD CPU Address Map Controller */ - - /* Start to set MMIO 0000A0000-0000BFFFF to Node0 Link0 */ - PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18, 1, 0x84); - PciData = 0x00000B00; - LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); - PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18, 1, 0x80); - PciData = 0x00000A03; - LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); - - /* Set TOM-DFFFFFFF to Node0 Link0. */ - PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18, 1, 0x8C); - PciData = 0x00DFFF00; - LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); - LibAmdMsrRead(TOP_MEM, &MsrReg, &StdHeader); - MsrReg = (MsrReg >> 8) | 3; - PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18, 1, 0x88); - PciData = (UINT32) MsrReg; - LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); - - /* Set E0000000-FFFFFFFF to Node0 Link0 with NP set. */ - PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18, 1, 0xBC); - PciData = 0x00FFFF00 | 0x80; - LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); - PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18, 1, 0xB8); - PciData = (CONFIG_MMCONF_BASE_ADDRESS >> 8) | 03; - LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); - - /* Start to set PCIIO 0000-FFFF to Node0 Link0 with ISA&VGA set. */ - PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18, 1, 0xC4); -//- PciData = 0x0000F000; - PciData = 0x00FFF000; - LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); - PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18, 1, 0xC0); - PciData = 0x00000013; - LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); -} - -void amd_initmmio(void) -{ - UINT64 MsrReg; - UINT32 PciData; - PCI_ADDR PciAddress; - AMD_CONFIG_PARAMS StdHeader; - - /* - Set the MMIO Configuration Base Address and Bus Range onto MMIO configuration base - Address MSR register. - */ - MsrReg = CONFIG_MMCONF_BASE_ADDRESS | (LibAmdBitScanReverse(CONFIG_MMCONF_BUS_NUMBER) << 2) | 1; - LibAmdMsrWrite(MMIO_CONF_BASE, &MsrReg, &StdHeader); - - /* Enable Non-Post Memory in CPU */ - PciData = CONFIG_MMCONF_BASE_ADDRESS + (CONFIG_MMCONF_BUS_NUMBER * 0x100000) - 1; - PciData = (PciData >> 8) & ~0xff; - PciData |= 0x80; - PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x018, 0x01, 0xA4); - LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); - - PciData = ((CONFIG_MMCONF_BASE_ADDRESS >> 8) | 0x03); - PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x018, 0x01, 0xA0); - LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); - - /* Enable memory access */ - PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0, 0, 0x04); - LibAmdPciRead(AccessWidth8, PciAddress, &PciData, &StdHeader); - PciData |= BIT1; - PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0, 0, 0x04); - LibAmdPciWrite(AccessWidth8, PciAddress, &PciData, &StdHeader); - - /* Set ROM cache onto WP to decrease post time */ - MsrReg = (0x0100000000ull - CACHE_ROM_SIZE) | 5ull; - LibAmdMsrWrite(MTRR_PHYS_BASE(6), &MsrReg, &StdHeader); - MsrReg = ((1ULL << CONFIG_CPU_ADDR_BITS) - CACHE_ROM_SIZE) | 0x800ull; - LibAmdMsrWrite(MTRR_PHYS_MASK(6), &MsrReg, &StdHeader); -} diff --git a/src/cpu/amd/agesa/family12/model_12_init.c b/src/cpu/amd/agesa/family12/model_12_init.c deleted file mode 100644 index c0669a857d..0000000000 --- a/src/cpu/amd/agesa/family12/model_12_init.c +++ /dev/null @@ -1,106 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -static void model_12_init(struct device *dev) -{ - printk(BIOS_DEBUG, "Model 12 Init.\n"); - - u8 i; - msr_t msr; - int num_banks; - -#if CONFIG(LOGICAL_CPUS) - u32 siblings; -#endif - -// struct node_core_id id; -// id = get_node_core_id(read_nb_cfg_54()); /* nb_cfg_54 can not be set */ -// printk(BIOS_DEBUG, "nodeid = %02d, coreid = %02d\n", id.nodeid, id.coreid); - - /* Turn on caching if we haven't already */ - x86_enable_cache(); - amd_setup_mtrrs(); - x86_mtrr_check(); - - disable_cache(); - - /* zero the machine check error status registers */ - msr = rdmsr(IA32_MCG_CAP); - num_banks = msr.lo & MCA_BANKS_MASK; - msr.lo = 0; - msr.hi = 0; - for (i = 0; i < num_banks; i++) - wrmsr(IA32_MC0_STATUS + (i * 4), msr); - - enable_cache(); - - /* Enable the local CPU APICs */ - setup_lapic(); - - /* Set the processor name string */ - // init_processor_name(); - -#if CONFIG(LOGICAL_CPUS) - siblings = cpuid_ecx(0x80000008) & 0xff; - - if (siblings > 0) { - msr = rdmsr_amd(CPU_ID_FEATURES_MSR); - msr.lo |= 1 << 28; - wrmsr_amd(CPU_ID_FEATURES_MSR, msr); - - msr = rdmsr_amd(CPU_ID_EXT_FEATURES_MSR); - msr.hi |= 1 << (33 - 32); - wrmsr_amd(CPU_ID_EXT_FEATURES_MSR, msr); - } - printk(BIOS_DEBUG, "siblings = %02d, ", siblings); -#endif - - /* DisableCf8ExtCfg */ - msr = rdmsr(NB_CFG_MSR); - msr.hi &= ~(1 << (46 - 32)); - wrmsr(NB_CFG_MSR, msr); - - /* Write protect SMM space with SMMLOCK. */ - msr = rdmsr(HWCR_MSR); - msr.lo |= (1 << 0); - wrmsr(HWCR_MSR, msr); -} - -static struct device_operations cpu_dev_ops = { - .init = model_12_init, -}; - -static const struct cpu_device_id cpu_table[] = { - { X86_VENDOR_AMD, 0x300f00 }, /* LN1_A0x */ - { X86_VENDOR_AMD, 0x300f01 }, /* LN1_A1x */ - { X86_VENDOR_AMD, 0x300f10 }, /* LN1_B0x */ - { X86_VENDOR_AMD, 0x300f20 }, /* LN2_B0x */ - { 0, 0 }, -}; - -static const struct cpu_driver model_12 __cpu_driver = { - .ops = &cpu_dev_ops, - .id_table = cpu_table, -}; diff --git a/src/cpu/amd/agesa/family12/romstage.c b/src/cpu/amd/agesa/family12/romstage.c deleted file mode 100644 index bca2baf483..0000000000 --- a/src/cpu/amd/agesa/family12/romstage.c +++ /dev/null @@ -1,27 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include - -#include "sb_cimx.h" -#include "SbPlatform.h" -#include "platform_cfg.h" - -void platform_once(struct sysinfo *cb) -{ - gpioEarlyInit(); - - sb_poweron_init(); - - board_BeforeAgesa(cb); -} diff --git a/src/northbridge/amd/agesa/Makefile.inc b/src/northbridge/amd/agesa/Makefile.inc index 338f99a637..54418a9649 100644 --- a/src/northbridge/amd/agesa/Makefile.inc +++ b/src/northbridge/amd/agesa/Makefile.inc @@ -15,7 +15,6 @@ ifeq ($(CONFIG_NORTHBRIDGE_AMD_AGESA),y) -subdirs-$(CONFIG_NORTHBRIDGE_AMD_AGESA_FAMILY12) += family12 subdirs-$(CONFIG_NORTHBRIDGE_AMD_AGESA_FAMILY14) += family14 subdirs-$(CONFIG_NORTHBRIDGE_AMD_AGESA_FAMILY15_TN) += family15tn subdirs-$(CONFIG_NORTHBRIDGE_AMD_AGESA_FAMILY16_KB) += family16kb diff --git a/src/northbridge/amd/agesa/family12/Kconfig b/src/northbridge/amd/agesa/family12/Kconfig deleted file mode 100644 index 74bc6fcfb8..0000000000 --- a/src/northbridge/amd/agesa/family12/Kconfig +++ /dev/null @@ -1,35 +0,0 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2007-2009 coresystems GmbH -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; version 2 of the License. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## -config NORTHBRIDGE_AMD_AGESA_FAMILY12 - bool - select HAVE_DEBUG_RAM_SETUP - select HAVE_DEBUG_SMBUS - select HYPERTRANSPORT_PLUGIN_SUPPORT - -if NORTHBRIDGE_AMD_AGESA_FAMILY12 - -config HW_MEM_HOLE_SIZEK - hex - default 0x100000 - -config MMCONF_BASE_ADDRESS - hex - default 0xe0000000 - -config MMCONF_BUS_NUMBER - int - default 256 - -endif # NORTHBRIDGE_AMD_AGESA_FAMILY_12 diff --git a/src/northbridge/amd/agesa/family12/Makefile.inc b/src/northbridge/amd/agesa/family12/Makefile.inc deleted file mode 100644 index ad39325247..0000000000 --- a/src/northbridge/amd/agesa/family12/Makefile.inc +++ /dev/null @@ -1,21 +0,0 @@ -# -# This file is part of the coreboot project. -# -# Copyright (C) 2011 Advanced Micro Devices, Inc. -# -# This program is free software; you can redistribute it and/or modify -# it under the terms of the GNU General Public License as published by -# the Free Software Foundation; version 2 of the License. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# - -romstage-y += dimmSpd.c - -ramstage-y += northbridge.c - -romstage-y += state_machine.c -ramstage-y += state_machine.c diff --git a/src/northbridge/amd/agesa/family12/dimmSpd.c b/src/northbridge/amd/agesa/family12/dimmSpd.c deleted file mode 100644 index 822c577a74..0000000000 --- a/src/northbridge/amd/agesa/family12/dimmSpd.c +++ /dev/null @@ -1,80 +0,0 @@ -/* - * - * Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - */ - -#include -#include -#include - -#include - -typedef struct _DIMM_INFO_SMBUS { - UINT8 SocketId; - UINT8 MemChannelId; - UINT8 DimmId; - UINT8 SmbusAddress; -} DIMM_INFO_SMBUS; - -/* -* SPD address table - porting required -*/ -STATIC CONST DIMM_INFO_SMBUS SpdAddrLookup [] = -{ - /* Socket, Channel, Dimm, Smbus */ - {0, 0, 0, 0xA0}, - {0, 1, 0, 0xA2} -}; - -AGESA_STATUS -AmdMemoryReadSPD ( - IN UINT32 Func, - IN UINTN Data, - IN OUT AGESA_READ_SPD_PARAMS *SpdData - ) -{ - UINT8 SmBusAddress = 0; - UINTN Index; - UINTN MaxSocket = ARRAY_SIZE(SpdAddrLookup); - - for (Index = 0; Index < MaxSocket; Index ++) { - if ((SpdData->SocketId == SpdAddrLookup[Index].SocketId) && - (SpdData->MemChannelId == SpdAddrLookup[Index].MemChannelId) && - (SpdData->DimmId == SpdAddrLookup[Index].DimmId)) { - SmBusAddress = SpdAddrLookup[Index].SmbusAddress; - break; - } - } - - if (SmBusAddress == 0) - return AGESA_ERROR; - - int err = smbus_readSpd(SmBusAddress, (char *) SpdData->Buffer, 128); - if (err) - return AGESA_ERROR; - return AGESA_SUCCESS; -} diff --git a/src/northbridge/amd/agesa/family12/northbridge.c b/src/northbridge/amd/agesa/family12/northbridge.c deleted file mode 100644 index ab17d893bb..0000000000 --- a/src/northbridge/amd/agesa/family12/northbridge.c +++ /dev/null @@ -1,834 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include - -#include "sb_cimx.h" - -#include -#include -#include - -#define FX_DEVS 1 - -static struct device *__f0_dev[FX_DEVS]; -static struct device *__f1_dev[FX_DEVS]; -static struct device *__f2_dev[FX_DEVS]; -static struct device *__f4_dev[FX_DEVS]; -static unsigned int fx_devs = 0; - -struct dram_base_mask_t { - u32 base; //[47:27] at [28:8] - u32 mask; //[47:27] at [28:8] and enable at bit 0 -}; - -static struct dram_base_mask_t get_dram_base_mask(u32 nodeid) -{ - struct device *dev; - struct dram_base_mask_t d; - dev = __f1_dev[0]; - - u32 temp; - temp = pci_read_config32(dev, 0x44); //[39:24] at [31:16] - d.mask = (temp & 0xffff0000); // mask out DramMask [26:24] too - - temp = pci_read_config32(dev, 0x40); //[35:24] at [27:16] - d.mask |= (temp & 1); // read enable bit - - d.base = (temp & 0x0fff0000); // mask out DramBase [26:24) too - - return d; -} - -static u32 get_io_addr_index(u32 nodeid, u32 linkn) -{ - return 0; -} - -static u32 get_mmio_addr_index(u32 nodeid, u32 linkn) -{ - return 0; -} - -static void set_io_addr_reg(struct device *dev, u32 nodeid, u32 linkn, u32 reg, - u32 io_min, u32 io_max) -{ - - u32 tempreg; - /* io range allocation */ - tempreg = (nodeid & 0xf) | ((nodeid & 0x30) << (8 - 4)) | (linkn << 4) | - ((io_max & 0xf0) << (12 - 4)); //limit - pci_write_config32(__f1_dev[0], reg+4, tempreg); - - tempreg = 3 | ((io_min & 0xf0) << (12 - 4)); //base :ISA and VGA ? - pci_write_config32(__f1_dev[0], reg, tempreg); -} - -static void set_mmio_addr_reg(u32 nodeid, u32 linkn, u32 reg, u32 index, - u32 mmio_min, u32 mmio_max, u32 nodes) -{ - - u32 tempreg; - /* io range allocation */ - tempreg = (nodeid & 0xf) | (linkn << 4) | (mmio_max & 0xffffff00); - pci_write_config32(__f1_dev[0], reg+4, tempreg); - tempreg = 3 | (nodeid & 0x30) | (mmio_min&0xffffff00); - pci_write_config32(__f1_dev[0], reg, tempreg); -} - -static struct device *get_node_pci(u32 nodeid, u32 fn) -{ - return pcidev_on_root(DEV_CDB + nodeid, fn); -} - -static void get_fx_devs(void) -{ - int i; - for (i = 0; i < FX_DEVS; i++) { - __f0_dev[i] = get_node_pci(i, 0); - __f1_dev[i] = get_node_pci(i, 1); - __f2_dev[i] = get_node_pci(i, 2); - __f4_dev[i] = get_node_pci(i, 4); - if (__f0_dev[i] != NULL && __f1_dev[i] != NULL) - fx_devs = i+1; - } - - if (__f1_dev[0] == NULL || __f0_dev[0] == NULL || fx_devs == 0) - die("Cannot find 0:0x18.[0|1]\n"); -} - -static u32 f1_read_config32(unsigned int reg) -{ - if (fx_devs == 0) - get_fx_devs(); - - return pci_read_config32(__f1_dev[0], reg); -} - -static void f1_write_config32(unsigned int reg, u32 value) -{ - int i; - if (fx_devs == 0) - get_fx_devs(); - for (i = 0; i < fx_devs; i++) { - struct device *dev = __f1_dev[i]; - if (dev && dev->enabled) { - pci_write_config32(dev, reg, value); - } - } -} - -static u32 amdfam12_nodeid(struct device *dev) -{ - printk(BIOS_DEBUG, "Fam12h - northbridge.c - %s\n",__func__); - return (dev->path.pci.devfn >> 3) - DEV_CDB; -} - -static void northbridge_init(struct device *dev) -{ - printk(BIOS_DEBUG, "Northbridge init\n"); -} - - -static void set_vga_enable_reg(u32 nodeid, u32 linkn) -{ - u32 val; - - printk(BIOS_DEBUG, "\nFam12h - northbridge.c - %s - Start.\n",__func__); - val = 1 | (nodeid << 4) | (linkn << 12); - /* it will routing (1)mmio 0xa0000:0xbffff (2) io 0x3b0:0x3bb, - 0x3c0:0x3df */ - f1_write_config32(0xf4, val); - - printk(BIOS_DEBUG, "Fam12h - northbridge.c - %s - End.\n",__func__); -} - - -static int reg_useable(unsigned int reg, struct device *goal_dev, - unsigned int goal_nodeid, unsigned int goal_link) -{ - struct resource *res; - unsigned int nodeid, link = 0; - int result; - printk(BIOS_DEBUG, "\nFam12h - northbridge.c - %s - Start.\n",__func__); - res = 0; - for (nodeid = 0; !res && (nodeid < fx_devs); nodeid++) { - struct device *dev = __f0_dev[nodeid]; - if (!dev) - continue; - for (link = 0; !res && (link < 8); link++) { - res = probe_resource(dev, IOINDEX(0x1000 + reg, link)); - } - } - result = 2; - if (res) { - result = 0; - if ((goal_link == (link - 1)) && - (goal_nodeid == (nodeid - 1)) && - (res->flags <= 1)) { - result = 1; - } - } - printk(BIOS_DEBUG, "Fam12h - northbridge.c - %s - End.\n",__func__); - return result; -} - -static struct resource *amdfam12_find_iopair(struct device *dev, - unsigned int nodeid, unsigned int link) -{ - struct resource *resource; - u32 result, reg; - resource = 0; - reg = 0; - result = reg_useable(0xc0, dev, nodeid, link); - if (result >= 1) { - /* I have been allocated this one */ - reg = 0xc0; - } - - //Ext conf space - if (!reg) { - //because of Extend conf space, we will never run out of reg, but we need one index to differ them. so same node and same link can have multi range - u32 index = get_io_addr_index(nodeid, link); - reg = 0x110+ (index << 24) + (4 << 20); // index could be 0, 255 - } - - resource = new_resource(dev, IOINDEX(0x1000 + reg, link)); - - return resource; -} - -static struct resource *amdfam12_find_mempair(struct device *dev, u32 nodeid, - u32 link) -{ - struct resource *resource; - u32 free_reg, reg; - resource = 0; - free_reg = 0; - for (reg = 0x80; reg <= 0xb8; reg += 0x8) { - int result; - result = reg_useable(reg, dev, nodeid, link); - if (result == 1) { - /* I have been allocated this one */ - break; - } - else if (result > 1) { - /* I have a free register pair */ - free_reg = reg; - } - } - if (reg > 0xb8) { - reg = free_reg; - } - - //Ext conf space - if (!reg) { - //because of Extend conf space, we will never run out of reg, - // but we need one index to differ them. so same node and - // same link can have multi range - u32 index = get_mmio_addr_index(nodeid, link); - reg = 0x110+ (index << 24) + (6 << 20); // index could be 0, 63 - } - - resource = new_resource(dev, IOINDEX(0x1000 + reg, link)); - return resource; -} - - -static void amdfam12_link_read_bases(struct device *dev, u32 nodeid, u32 link) -{ - struct resource *resource; - - printk(BIOS_DEBUG, "\nFam12h - northbridge.c - %s - Start.\n",__func__); - /* Initialize the io space constraints on the current bus */ - resource = amdfam12_find_iopair(dev, nodeid, link); - if (resource) { - u32 align; - align = log2(HT_IO_HOST_ALIGN); - resource->base = 0; - resource->size = 0; - resource->align = align; - resource->gran = align; - resource->limit = 0xffffUL; - resource->flags = IORESOURCE_IO | IORESOURCE_BRIDGE; - } - - /* Initialize the prefetchable memory constraints on the current bus */ - resource = amdfam12_find_mempair(dev, nodeid, link); - if (resource) { - resource->base = 0; - resource->size = 0; - resource->align = log2(HT_MEM_HOST_ALIGN); - resource->gran = log2(HT_MEM_HOST_ALIGN); - resource->limit = 0xffffffffffULL; - resource->flags = IORESOURCE_MEM | IORESOURCE_PREFETCH; - resource->flags |= IORESOURCE_BRIDGE; - } - - /* Initialize the memory constraints on the current bus */ - resource = amdfam12_find_mempair(dev, nodeid, link); - if (resource) { - resource->base = 0; - resource->size = 0; - resource->align = log2(HT_MEM_HOST_ALIGN); - resource->gran = log2(HT_MEM_HOST_ALIGN); - resource->limit = 0xffffffffffULL; - resource->flags = IORESOURCE_MEM | IORESOURCE_BRIDGE; - } - printk(BIOS_DEBUG, "Fam12h - northbridge.c - %s - End.\n",__func__); -} - -static u32 my_find_pci_tolm(struct bus *bus, u32 tolm) -{ - struct resource *min; - min = 0; - search_bus_resources(bus, IORESOURCE_MEM, IORESOURCE_MEM, tolm_test, &min); - if (min && tolm > min->base) { - tolm = min->base; - } - return tolm; -} - -#if CONFIG_HW_MEM_HOLE_SIZEK != 0 - -struct hw_mem_hole_info { - unsigned int hole_startk; - int node_id; -}; - -static struct hw_mem_hole_info get_hw_mem_hole_info(void) -{ - struct hw_mem_hole_info mem_hole; - - mem_hole.hole_startk = CONFIG_HW_MEM_HOLE_SIZEK; - mem_hole.node_id = -1; - - struct dram_base_mask_t d; - u32 hole; - d = get_dram_base_mask(0); - if (d.mask & 1) { - hole = pci_read_config32(__f1_dev[0], 0xf0); - if (hole & 1) { // we find the hole - mem_hole.hole_startk = (hole & (0xff << 24)) >> 10; - mem_hole.node_id = 0; // record the node No with hole - } - } - return mem_hole; -} -#endif - -static void read_resources(struct device *dev) -{ - u32 nodeid; - struct bus *link; - - printk(BIOS_DEBUG, "\nFam12h - northbridge.c - %s - Start.\n",__func__); - - nodeid = amdfam12_nodeid(dev); - for (link = dev->link_list; link; link = link->next) { - if (link->children) { - amdfam12_link_read_bases(dev, nodeid, link->link_num); - } - } - - /* - * This MMCONF resource must be reserved in the PCI domain. - * It is not honored by the coreboot resource allocator if it is in - * the CPU_CLUSTER. - */ - mmconf_resource(dev, MMIO_CONF_BASE); - - printk(BIOS_DEBUG, "Fam12h - northbridge.c - %s - End.\n",__func__); -} - - -static void set_resource(struct device *dev, struct resource *resource, - u32 nodeid) -{ - resource_t rbase, rend; - unsigned int reg, link_num; - char buf[50]; - - printk(BIOS_DEBUG, "\nFam12h - northbridge.c - %s - Start.\n",__func__); - - /* Make certain the resource has actually been set */ - if (!(resource->flags & IORESOURCE_ASSIGNED)) { - return; - } - - /* If I have already stored this resource don't worry about it */ - if (resource->flags & IORESOURCE_STORED) { - return; - } - - /* Only handle PCI memory and IO resources */ - if (!(resource->flags & (IORESOURCE_MEM | IORESOURCE_IO))) - return; - - /* Ensure I am actually looking at a resource of function 1 */ - if ((resource->index & 0xffff) < 0x1000) { - return; - } - /* Get the base address */ - rbase = resource->base; - - /* Get the limit (rounded up) */ - rend = resource_end(resource); - - /* Get the register and link */ - reg = resource->index & 0xfff; // 4k - link_num = IOINDEX_LINK(resource->index); - - if (resource->flags & IORESOURCE_IO) { - set_io_addr_reg(dev, nodeid, link_num, reg, rbase>>8, rend>>8); - } - else if (resource->flags & IORESOURCE_MEM) { - set_mmio_addr_reg(nodeid, link_num, reg, (resource->index >>24), rbase>>8, rend>>8, 1); // [39:8] - } - resource->flags |= IORESOURCE_STORED; - snprintf(buf, sizeof(buf), " ", nodeid, link_num); - report_resource_stored(dev, resource, buf); - printk(BIOS_DEBUG, "Fam12h - northbridge.c - %s - End.\n",__func__); -} - - -#if CONFIG(CONSOLE_VGA_MULTI) -extern struct device *vga_pri; // the primary vga device, defined in device.c -#endif - -static void create_vga_resource(struct device *dev, unsigned int nodeid) -{ -struct bus *link; - -printk(BIOS_DEBUG, "\nFam12h - northbridge.c - %s - Start.\n",__func__); - - /* find out which link the VGA card is connected, - * we only deal with the 'first' vga card */ - for (link = dev->link_list; link; link = link->next) { - if (link->bridge_ctrl & PCI_BRIDGE_CTL_VGA) { -#if CONFIG(CONSOLE_VGA_MULTI) - printk(BIOS_DEBUG, "VGA: vga_pri bus num = %d bus range [%d,%d]\n", vga_pri->bus->secondary, - link->secondary,link->subordinate); - /* We need to make sure the vga_pri is under the link */ - if ((vga_pri->bus->secondary >= link->secondary) && - (vga_pri->bus->secondary <= link->subordinate)) -#endif - break; // XXX this break looks questionable - } - } - - /* no VGA card installed */ - if (link == NULL) - return; - - printk(BIOS_DEBUG, "VGA: %s (aka node %d) link %d has VGA device\n", dev_path(dev), nodeid, link->link_num); - set_vga_enable_reg(nodeid, link->link_num); - printk(BIOS_DEBUG, "Fam12h - northbridge.c - %s - End.\n",__func__); -} - - -static void set_resources(struct device *dev) -{ - unsigned int nodeid; - struct bus *bus; - struct resource *res; - - printk(BIOS_DEBUG, "\nFam12h - northbridge.c - %s - Start.\n",__func__); - - /* Find the nodeid */ - nodeid = amdfam12_nodeid(dev); - - create_vga_resource(dev, nodeid); - - /* Set each resource we have found */ - for (res = dev->resource_list; res; res = res->next) { - set_resource(dev, res, nodeid); - } - - for (bus = dev->link_list; bus; bus = bus->next) { - if (bus->children) - assign_resources(bus); - } - printk(BIOS_DEBUG, "Fam12h - northbridge.c - %s - End.\n",__func__); -} - -/* Domain/Root Complex related code */ - -static void domain_read_resources(struct device *dev) -{ - unsigned int reg; - - printk(BIOS_DEBUG, "\nFam12h - northbridge.c - %s - Start.\n",__func__); - - /* Find the already assigned resource pairs */ - get_fx_devs(); - for (reg = 0x80; reg <= 0xc0; reg+= 0x08) { - u32 base, limit; - base = f1_read_config32(reg); - limit = f1_read_config32(reg + 0x04); - /* Is this register allocated? */ - if ((base & 3) != 0) { - unsigned int nodeid, reg_link; - struct device *reg_dev; - if (reg < 0xc0) { // mmio - nodeid = (limit & 0xf) + (base&0x30); - } else { // io - nodeid = (limit & 0xf) + ((base>>4)&0x30); - } - reg_link = (limit >> 4) & 7; - reg_dev = __f0_dev[nodeid]; - if (reg_dev) { - /* Reserve the resource */ - struct resource *res; - res = new_resource(reg_dev, IOINDEX(0x1000 + reg, reg_link)); - if (res) { - res->flags = 1; - } - } - } - } - /* FIXME: do we need to check extend conf space? - I don't believe that much preset value */ - - struct resource *resource; - /* Initialize the system-wide I/O space constraints. */ - resource = new_resource(dev, IOINDEX_SUBTRACTIVE(0, 0)); - resource->base = 0x1000; - resource->limit = 0xffffUL; - resource->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE | - IORESOURCE_ASSIGNED; - - /* Initialize the system-wide memory resources constraints. */ - resource = new_resource(dev, IOINDEX_SUBTRACTIVE(1, 0)); - resource->base = 0xc0000000ULL; - resource->limit = 0xdfffffffULL; - resource->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE | - IORESOURCE_ASSIGNED; - - printk(BIOS_DEBUG, "Fam12h - northbridge.c - %s - End.\n",__func__); -} - - -static void domain_set_resources(struct device *dev) -{ - printk(BIOS_DEBUG, "\nFam12h - northbridge.c - %s - Start.\n",__func__); - printk(BIOS_DEBUG, " amsr - incoming dev = %p\n", dev); - - unsigned long mmio_basek; - u32 pci_tolm; - int idx; - struct bus *link; -#if CONFIG_HW_MEM_HOLE_SIZEK != 0 - struct hw_mem_hole_info mem_hole; - u32 reset_memhole = 1; -#endif - - pci_tolm = 0xffffffffUL; - for (link = dev->link_list; link; link = link->next) { - pci_tolm = my_find_pci_tolm(link, pci_tolm); - } - - // FIXME handle interleaved nodes. If you fix this here, please fix - // amdk8, too. - mmio_basek = pci_tolm >> 10; - /* Round mmio_basek to something the processor can support */ - mmio_basek &= ~((1 << 6) -1); - - // FIXME improve mtrr.c so we don't use up all of the mtrrs with a 64M - // MMIO hole. If you fix this here, please fix amdk8, too. - /* Round the mmio hole to 64M */ - mmio_basek &= ~((64*1024) - 1); - -#if CONFIG_HW_MEM_HOLE_SIZEK != 0 -/* if the hw mem hole is already set in raminit stage, here we will compare - * mmio_basek and hole_basek. if mmio_basek is bigger that hole_basek and will - * use hole_basek as mmio_basek and we don't need to reset hole. - * otherwise We reset the hole to the mmio_basek - */ - - mem_hole = get_hw_mem_hole_info(); - - // Use hole_basek as mmio_basek, and we don't need to reset hole anymore - if ((mem_hole.node_id != -1) && (mmio_basek > mem_hole.hole_startk)) { - mmio_basek = mem_hole.hole_startk; - reset_memhole = 0; - } -#endif - - idx = 0x10; - - struct dram_base_mask_t d; - resource_t basek, limitk, sizek; // 4 1T - - d = get_dram_base_mask(0); - - if (d.mask & 1) { - basek = ((resource_t)(d.base)) << 8; - limitk = (resource_t)((d.mask << 8) | 0xFFFFFF); - printk(BIOS_DEBUG, "adsr: (before) basek = %llx, limitk = %llx.\n",basek,limitk); - - /* Convert these values to multiples of 1K for ease of math. */ - basek >>= 10; - limitk >>= 10; - sizek = limitk - basek + 1; - - printk(BIOS_DEBUG, "adsr: (after) basek = %llx, limitk = %llx, sizek = %llx.\n",basek,limitk,sizek); - - /* see if we need a hole from 0xa0000 to 0xbffff */ - if ((basek < 640) && (sizek > 768)) { - printk(BIOS_DEBUG, "adsr - 0xa0000 to 0xbffff resource.\n"); - ram_resource(dev, (idx | 0), basek, 640 - basek); - idx += 0x10; - basek = 768; - sizek = limitk - 768; - } - - printk(BIOS_DEBUG, - "adsr: mmio_basek=%08lx, basek=%08llx, limitk=%08llx\n", - mmio_basek, basek, limitk); - - /* split the region to accommodate pci memory space */ - if ((basek < 4*1024*1024) && (limitk > mmio_basek)) { - if (basek <= mmio_basek) { - unsigned int pre_sizek; - pre_sizek = mmio_basek - basek; - if (pre_sizek > 0) { - ram_resource(dev, idx, basek, pre_sizek); - idx += 0x10; - sizek -= pre_sizek; - } - basek = mmio_basek; - } - if ((basek + sizek) <= 4*1024*1024) { - sizek = 0; - } else { - basek = 4*1024*1024; - sizek -= (4*1024*1024 - mmio_basek); - } - } - - ram_resource(dev, (idx | 0), basek, sizek); - idx += 0x10; - printk(BIOS_DEBUG, "%d: mmio_basek=%08lx, basek=%08llx, limitk=%08llx\n", - 0, mmio_basek, basek, limitk); - } - printk(BIOS_DEBUG, " adsr - mmio_basek = %lx.\n", mmio_basek); - - add_uma_resource_below_tolm(dev, 7); - - for (link = dev->link_list; link; link = link->next) { - if (link->children) - assign_resources(link); - } - printk(BIOS_DEBUG, " adsr - leaving this lovely routine.\n"); - printk(BIOS_DEBUG, "Fam12h - northbridge.c - %s - End.\n",__func__); -} - - -/* Bus related code */ - -static void cpu_bus_init(struct device *dev) -{ - printk(BIOS_DEBUG, "\nFam12h - northbridge.c - %s - Start.\n",__func__); - initialize_cpus(dev->link_list); - printk(BIOS_DEBUG, "Fam12h - northbridge.c - %s - End.\n",__func__); -} - - -/* North Bridge Structures */ - - -static unsigned long acpi_fill_hest(acpi_hest_t *hest) -{ - void *addr, *current; - - /* Skip the HEST header. */ - current = (void *)(hest + 1); - - addr = agesawrapper_getlateinitptr(PICK_WHEA_MCE); - if (addr != NULL) - current += acpi_create_hest_error_source(hest, current, 0, - addr + 2, *(UINT16 *)addr - 2); - - addr = agesawrapper_getlateinitptr(PICK_WHEA_CMC); - if (addr != NULL) - current += acpi_create_hest_error_source(hest, current, 1, - addr + 2, *(UINT16 *)addr - 2); - - return (unsigned long)current; -} - -static void northbridge_fill_ssdt_generator(struct device *device) -{ - msr_t msr; - char pscope[] = "\\_SB.PCI0"; - - acpigen_write_scope(pscope); - msr = rdmsr(TOP_MEM); - acpigen_write_name_dword("TOM1", msr.lo); - msr = rdmsr(TOP_MEM2); - /* - * Since XP only implements parts of ACPI 2.0, we can't use a qword - * here. - * See http://www.acpi.info/presentations/S01USMOBS169_OS%2520new.ppt - * slide 22ff. - * Shift value right by 20 bit to make it fit into 32bit, - * giving us 1MB granularity and a limit of almost 4Exabyte of memory. - */ - acpigen_write_name_dword("TOM2", (msr.hi << 12) | msr.lo >> 20); - acpigen_pop_len(); -} - -static unsigned long agesa_write_acpi_tables(struct device *device, - unsigned long current, - acpi_rsdp_t *rsdp) -{ - acpi_srat_t *srat; - acpi_slit_t *slit; - acpi_header_t *ssdt; - acpi_hest_t *hest; - - /* HEST */ - current = ALIGN(current, 8); - hest = (acpi_hest_t *)current; - acpi_write_hest((void *)current, acpi_fill_hest); - acpi_add_table(rsdp, (void *)current); - current += ((acpi_header_t *)current)->length; - - /* SRAT */ - current = ALIGN(current, 8); - printk(BIOS_DEBUG, "ACPI: * SRAT at %lx\n", current); - srat = (acpi_srat_t *) agesawrapper_getlateinitptr (PICK_SRAT); - if (srat != NULL) { - memcpy((void *)current, srat, srat->header.length); - srat = (acpi_srat_t *) current; - current += srat->header.length; - acpi_add_table(rsdp, srat); - } - - /* SLIT */ - current = ALIGN(current, 8); - printk(BIOS_DEBUG, "ACPI: * SLIT at %lx\n", current); - slit = (acpi_slit_t *) agesawrapper_getlateinitptr (PICK_SLIT); - if (slit != NULL) { - memcpy((void *)current, slit, slit->header.length); - slit = (acpi_slit_t *) current; - current += slit->header.length; - acpi_add_table(rsdp, slit); - } - - /* SSDT */ - current = ALIGN(current, 16); - printk(BIOS_DEBUG, "ACPI: * SSDT at %lx\n", current); - ssdt = (acpi_header_t *)agesawrapper_getlateinitptr (PICK_PSTATE); - if (ssdt != NULL) { - memcpy((void *)current, ssdt, ssdt->length); - ssdt = (acpi_header_t *) current; - current += ssdt->length; - acpi_add_table(rsdp,ssdt); - } - - printk(BIOS_DEBUG, "ACPI: * SSDT for PState at %lx\n", current); - - return current; -} - - -static struct device_operations northbridge_operations = { - .read_resources = read_resources, - .set_resources = set_resources, - .acpi_fill_ssdt_generator = northbridge_fill_ssdt_generator, - .write_acpi_tables = agesa_write_acpi_tables, - .enable_resources = pci_dev_enable_resources, - .init = northbridge_init, - .enable = 0, - .ops_pci = 0, -}; - - -static const struct pci_driver northbridge_driver __pci_driver = { - .ops = &northbridge_operations, - .vendor = PCI_VENDOR_ID_AMD, - .device = 0x1705, -}; - - -struct chip_operations northbridge_amd_agesa_family12_ops = { - CHIP_NAME("AMD Family 12h Northbridge") - .enable_dev = 0, -}; - - -/* Root Complex Structures */ - - -static struct device_operations pci_domain_ops = { - .read_resources = domain_read_resources, - .set_resources = domain_set_resources, - .init = DEVICE_NOOP, - .scan_bus = pci_domain_scan_bus, -}; - - -static struct device_operations cpu_bus_ops = { - .read_resources = DEVICE_NOOP, - .set_resources = DEVICE_NOOP, - .enable_resources = DEVICE_NOOP, - .init = cpu_bus_init, - .scan_bus = 0, -}; - - -static void root_complex_enable_dev(struct device *dev) -{ - printk(BIOS_DEBUG, "\nFam12h - northbridge.c - %s - Start.\n",__func__); - static int done = 0; - - if (!done) { - setup_bsp_ramtop(); - done = 1; - } - - /* Set the operations if it is a special bus type */ - if (dev->path.type == DEVICE_PATH_DOMAIN) { - dev->ops = &pci_domain_ops; - } - else if (dev->path.type == DEVICE_PATH_CPU_CLUSTER) { - dev->ops = &cpu_bus_ops; - } - printk(BIOS_DEBUG, "Fam12h - northbridge.c - %s - End.\n",__func__); -} - - -struct chip_operations northbridge_amd_agesa_family12_root_complex_ops = { - CHIP_NAME("AMD Family 12h Root Complex") - .enable_dev = root_complex_enable_dev, -}; diff --git a/src/northbridge/amd/agesa/family12/state_machine.c b/src/northbridge/amd/agesa/family12/state_machine.c deleted file mode 100644 index 077bf6a293..0000000000 --- a/src/northbridge/amd/agesa/family12/state_machine.c +++ /dev/null @@ -1,87 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2016 Kyösti Mälkki - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include - -#include -#include -#include - -#include - -void platform_BeforeInitReset(struct sysinfo *cb, AMD_RESET_PARAMS *Reset) -{ -} - -void platform_BeforeInitEarly(struct sysinfo *cb, AMD_EARLY_PARAMS *Early) -{ -} - -void platform_BeforeInitPost(struct sysinfo *cb, AMD_POST_PARAMS *Post) -{ -} - -void platform_AfterInitPost(struct sysinfo *cb, AMD_POST_PARAMS *Post) -{ - backup_top_of_low_cacheable(Post->MemConfig.Sub4GCacheTop); - - sb_before_pci_init(); -} - -void platform_BeforeInitResume(struct sysinfo *cb, AMD_RESUME_PARAMS *Resume) -{ - OemInitResume(&Resume->S3DataBlock); -} - -void platform_AfterInitResume(struct sysinfo *cb, AMD_RESUME_PARAMS *Resume) -{ -} - -void platform_BeforeInitEnv(struct sysinfo *cb, AMD_ENV_PARAMS *Env) -{ - EmptyHeap(); -} - -void platform_AfterInitEnv(struct sysinfo *cb, AMD_ENV_PARAMS *Env) -{ - sb_After_Pci_Init(); -} - -void platform_BeforeS3LateRestore(struct sysinfo *cb, AMD_S3LATE_PARAMS *S3Late) -{ - OemS3LateRestore(&S3Late->S3DataBlock); -} - -void platform_AfterS3LateRestore(struct sysinfo *cb, AMD_S3LATE_PARAMS *S3Late) -{ -} - -void platform_BeforeInitMid(struct sysinfo *cb, AMD_MID_PARAMS *Mid) -{ - sb_Mid_Post_Init(); - - amd_initcpuio(); -} - -void platform_AfterInitLate(struct sysinfo *cb, AMD_LATE_PARAMS *Late) -{ - sb_Late_Post(); -} - -void platform_AfterS3Save(struct sysinfo *cb, AMD_S3SAVE_PARAMS *S3Save) -{ - OemS3Save(&S3Save->S3DataBlock); -} diff --git a/src/southbridge/amd/cimx/Kconfig b/src/southbridge/amd/cimx/Kconfig index 06544938a7..62a717be54 100644 --- a/src/southbridge/amd/cimx/Kconfig +++ b/src/southbridge/amd/cimx/Kconfig @@ -18,4 +18,3 @@ config AMD_SB_CIMX default n source src/southbridge/amd/cimx/sb800/Kconfig -source src/southbridge/amd/cimx/sb900/Kconfig diff --git a/src/southbridge/amd/cimx/Makefile.inc b/src/southbridge/amd/cimx/Makefile.inc index b70d2feb7f..5d1d3f683b 100644 --- a/src/southbridge/amd/cimx/Makefile.inc +++ b/src/southbridge/amd/cimx/Makefile.inc @@ -14,10 +14,7 @@ # subdirs-$(CONFIG_SOUTHBRIDGE_AMD_CIMX_SB800) += sb800 -subdirs-$(CONFIG_SOUTHBRIDGE_AMD_CIMX_SB900) += sb900 romstage-$(CONFIG_SOUTHBRIDGE_AMD_CIMX_SB800) += cimx_util.c -romstage-$(CONFIG_SOUTHBRIDGE_AMD_CIMX_SB900) += cimx_util.c ramstage-$(CONFIG_SOUTHBRIDGE_AMD_CIMX_SB800) += cimx_util.c -ramstage-$(CONFIG_SOUTHBRIDGE_AMD_CIMX_SB900) += cimx_util.c diff --git a/src/southbridge/amd/cimx/sb900/Amd.h b/src/southbridge/amd/cimx/sb900/Amd.h deleted file mode 100644 index c765b3371b..0000000000 --- a/src/southbridge/amd/cimx/sb900/Amd.h +++ /dev/null @@ -1,377 +0,0 @@ -/***************************************************************************** - * AMD Generic Encapsulated Software Architecture */ -/** - * @file - * - * Agesa structures and definitions - * - * Contains AMD AGESA/CIMx core interface - * - */ -/* - ***************************************************************************** - * - * This file is part of the coreboot project. - * - * Copyright (C) 2011 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * *************************************************************************** - * - */ - - -#ifndef _AMD_H_ -#define _AMD_H_ - -// AGESA Types and Definitions -#ifndef NULL - #define NULL 0 -#endif - -#define LAST_ENTRY 0xFFFFFFFF -#define IOCF8 0xCF8 -#define IOCFC 0xCFC -#define IN -#define OUT - -#ifndef Int16FromChar -#define Int16FromChar(a,b) ((a) << 0 | (b) << 8) -#endif -#ifndef Int32FromChar -#define Int32FromChar(a,b,c,d) ((a) << 0 | (b) << 8 | (c) << 16 | (d) << 24) -#endif - -#define IMAGE_SIGNATURE Int32FromChar ('$', 'A', 'M', 'D') - -typedef unsigned int AGESA_STATUS; - -#define AGESA_SUCCESS ((AGESA_STATUS) 0x0) -#define AGESA_ALERT ((AGESA_STATUS) 0x40000000) -#define AGESA_WARNING ((AGESA_STATUS) 0x40000001) -#define AGESA_UNSUPPORTED ((AGESA_STATUS) 0x80000003) -#define AGESA_ERROR ((AGESA_STATUS) 0xC0000001) -#define AGESA_CRITICAL ((AGESA_STATUS) 0xC0000002) -#define AGESA_FATAL ((AGESA_STATUS) 0xC0000003) - -typedef AGESA_STATUS(*CALLOUT_ENTRY) (unsigned int Param1, unsigned int Param2, - void *ConfigPtr); -typedef AGESA_STATUS(*IMAGE_ENTRY) (IN OUT void *ConfigPtr); -typedef AGESA_STATUS(*MODULE_ENTRY) (IN OUT void *ConfigPtr); - -///This allocation type is used by the AmdCreateStruct entry point -typedef enum { - PreMemHeap = 0, ///< Create heap in cache. - PostMemDram, ///< Create heap in memory. - ByHost ///< Create heap by Host. -} ALLOCATION_METHOD; - -/// These width descriptors are used by the library function, and others, to specify the data size -typedef enum ACCESS_WIDTH { - AccessWidth8 = 1, ///< Access width is 8 bits. - AccessWidth16, ///< Access width is 16 bits. - AccessWidth32, ///< Access width is 32 bits. - AccessWidth64, ///< Access width is 64 bits. - - AccessS3SaveWidth8 = 0x81, ///< Save 8 bits data. - AccessS3SaveWidth16, ///< Save 16 bits data. - AccessS3SaveWidth32, ///< Save 32 bits data. - AccessS3SaveWidth64, ///< Save 64 bits data. -} ACCESS_WIDTH; - -// AGESA Structures - -/// The standard header for all AGESA services. -typedef struct _AMD_CONFIG_PARAMS { - IN unsigned int ImageBasePtr; ///< The AGESA Image base address. - IN unsigned int Func; ///< The service desired, @sa dispatch.h. - IN unsigned int AltImageBasePtr; ///< Alternate Image location - IN unsigned int PcieBasePtr; ///< PCIe MMIO Base address, if configured. - union { ///< Callback pointer - IN unsigned long long PlaceHolder; ///< Place holder - IN CALLOUT_ENTRY CalloutPtr; ///< For Callout from AGESA - } CALLBACK; - IN OUT unsigned int Reserved[2]; ///< This space is reserved for future use. -} AMD_CONFIG_PARAMS; - - -/// AGESA Binary module header structure -typedef struct _AMD_IMAGE_HEADER { - IN unsigned int Signature; ///< Binary Signature - IN signed char CreatorID[8]; ///< 8 characters ID - IN signed char Version[12]; ///< 12 characters version - IN unsigned int ModuleInfoOffset; ///< Offset of module - IN unsigned int EntryPointAddress; ///< Entry address - IN unsigned int ImageBase; ///< Image base - IN unsigned int RelocTableOffset; ///< Relocate Table offset - IN unsigned int ImageSize; ///< Size - IN unsigned short Checksum; ///< Checksum - IN unsigned char ImageType; ///< Type - IN unsigned char V_Reserved; ///< Reserved -} AMD_IMAGE_HEADER; - -/// AGESA Binary module header structure -typedef struct _AMD_MODULE_HEADER { - IN unsigned int ModuleHeaderSignature; ///< Module signature - IN signed char ModuleIdentifier[8]; ///< 8 characters ID - IN signed char ModuleVersion[12]; ///< 12 characters version - IN MODULE_ENTRY ModuleDispatcherPtr; ///< A pointer point to dispatcher - IN struct _AMD_MODULE_HEADER *NextBlockPtr; ///< Next module header link -} AMD_MODULE_HEADER; - -#define FUNC_0 0 // bit-placed for PCI address creation -#define FUNC_1 1 -#define FUNC_2 2 -#define FUNC_3 3 -#define FUNC_4 4 -#define FUNC_5 5 -#define FUNC_6 6 -#define FUNC_7 7 - -// SBDFO - Segment Bus Device Function Offset -// 31:28 Segment (4-bits) -// 27:20 Bus (8-bits) -// 19:15 Device (5-bits) -// 14:12 Function (3-bits) -// 11:00 Offset (12-bits) - -#if 0 -#define MAKE_SBDFO(Seg, Bus, Dev, Fun, Off) ((((unsigned int) (Seg)) << 28) | (((unsigned int) (Bus)) << 20) | \ - (((unsigned int) (Dev)) << 15) | (((unsigned int) (Fun)) << 12) | ((unsigned int) (Off))) -#endif -#define ILLEGAL_SBDFO 0xFFFFFFFF - -/* -/// CPUID data received registers format -typedef struct _SB_CPUID_DATA { - IN OUT unsigned int EAX_Reg; ///< CPUID instruction result in EAX - IN OUT unsigned int EBX_Reg; ///< CPUID instruction result in EBX - IN OUT unsigned int ECX_Reg; ///< CPUID instruction result in ECX - IN OUT unsigned int EDX_Reg; ///< CPUID instruction result in EDX -} SB_CPUID_DATA; -*/ - -#define WARM_RESET 1 -#define COLD_RESET 2 // Cold reset -#define RESET_CPU 4 // Triggers a CPU reset - -/// HT frequency for external callbacks -typedef enum { - HT_FREQUENCY_200M = 0, ///< HT speed 200 for external callbacks - HT_FREQUENCY_400M = 2, ///< HT speed 400 for external callbacks - HT_FREQUENCY_600M = 4, ///< HT speed 600 for external callbacks - HT_FREQUENCY_800M = 5, ///< HT speed 800 for external callbacks - HT_FREQUENCY_1000M = 6, ///< HT speed 1000 for external callbacks - HT_FREQUENCY_1200M = 7, ///< HT speed 1200 for external callbacks - HT_FREQUENCY_1400M = 8, ///< HT speed 1400 for external callbacks - HT_FREQUENCY_1600M = 9, ///< HT speed 1600 for external callbacks - HT_FREQUENCY_1800M = 10, ///< HT speed 1800 for external callbacks - HT_FREQUENCY_2000M = 11, ///< HT speed 2000 for external callbacks - HT_FREQUENCY_2200M = 12, ///< HT speed 2200 for external callbacks - HT_FREQUENCY_2400M = 13, ///< HT speed 2400 for external callbacks - HT_FREQUENCY_2600M = 14, ///< HT speed 2600 for external callbacks - HT_FREQUENCY_2800M = 17, ///< HT speed 2800 for external callbacks - HT_FREQUENCY_3000M = 18, ///< HT speed 3000 for external callbacks - HT_FREQUENCY_3200M = 19 ///< HT speed 3200 for external callbacks -} HT_FREQUENCIES; - -#ifndef BIT0 - #define BIT0 0x0000000000000001ull -#endif -#ifndef BIT1 - #define BIT1 0x0000000000000002ull -#endif -#ifndef BIT2 - #define BIT2 0x0000000000000004ull -#endif -#ifndef BIT3 - #define BIT3 0x0000000000000008ull -#endif -#ifndef BIT4 - #define BIT4 0x0000000000000010ull -#endif -#ifndef BIT5 - #define BIT5 0x0000000000000020ull -#endif -#ifndef BIT6 - #define BIT6 0x0000000000000040ull -#endif -#ifndef BIT7 - #define BIT7 0x0000000000000080ull -#endif -#ifndef BIT8 - #define BIT8 0x0000000000000100ull -#endif -#ifndef BIT9 - #define BIT9 0x0000000000000200ull -#endif -#ifndef BIT10 - #define BIT10 0x0000000000000400ull -#endif -#ifndef BIT11 - #define BIT11 0x0000000000000800ull -#endif -#ifndef BIT12 - #define BIT12 0x0000000000001000ull -#endif -#ifndef BIT13 - #define BIT13 0x0000000000002000ull -#endif -#ifndef BIT14 - #define BIT14 0x0000000000004000ull -#endif -#ifndef BIT15 - #define BIT15 0x0000000000008000ull -#endif -#ifndef BIT16 - #define BIT16 0x0000000000010000ull -#endif -#ifndef BIT17 - #define BIT17 0x0000000000020000ull -#endif -#ifndef BIT18 - #define BIT18 0x0000000000040000ull -#endif -#ifndef BIT19 - #define BIT19 0x0000000000080000ull -#endif -#ifndef BIT20 - #define BIT20 0x0000000000100000ull -#endif -#ifndef BIT21 - #define BIT21 0x0000000000200000ull -#endif -#ifndef BIT22 - #define BIT22 0x0000000000400000ull -#endif -#ifndef BIT23 - #define BIT23 0x0000000000800000ull -#endif -#ifndef BIT24 - #define BIT24 0x0000000001000000ull -#endif -#ifndef BIT25 - #define BIT25 0x0000000002000000ull -#endif -#ifndef BIT26 - #define BIT26 0x0000000004000000ull -#endif -#ifndef BIT27 - #define BIT27 0x0000000008000000ull -#endif -#ifndef BIT28 - #define BIT28 0x0000000010000000ull -#endif -#ifndef BIT29 - #define BIT29 0x0000000020000000ull -#endif -#ifndef BIT30 - #define BIT30 0x0000000040000000ull -#endif -#ifndef BIT31 - #define BIT31 0x0000000080000000ull -#endif -#ifndef BIT32 - #define BIT32 0x0000000100000000ull -#endif -#ifndef BIT33 - #define BIT33 0x0000000200000000ull -#endif -#ifndef BIT34 - #define BIT34 0x0000000400000000ull -#endif -#ifndef BIT35 - #define BIT35 0x0000000800000000ull -#endif -#ifndef BIT36 - #define BIT36 0x0000001000000000ull -#endif -#ifndef BIT37 - #define BIT37 0x0000002000000000ull -#endif -#ifndef BIT38 - #define BIT38 0x0000004000000000ull -#endif -#ifndef BIT39 - #define BIT39 0x0000008000000000ull -#endif -#ifndef BIT40 - #define BIT40 0x0000010000000000ull -#endif -#ifndef BIT41 - #define BIT41 0x0000020000000000ull -#endif -#ifndef BIT42 - #define BIT42 0x0000040000000000ull -#endif -#ifndef BIT43 - #define BIT43 0x0000080000000000ull -#endif -#ifndef BIT44 - #define BIT44 0x0000100000000000ull -#endif -#ifndef BIT45 - #define BIT45 0x0000200000000000ull -#endif -#ifndef BIT46 - #define BIT46 0x0000400000000000ull -#endif -#ifndef BIT47 - #define BIT47 0x0000800000000000ull -#endif -#ifndef BIT48 - #define BIT48 0x0001000000000000ull -#endif -#ifndef BIT49 - #define BIT49 0x0002000000000000ull -#endif -#ifndef BIT50 - #define BIT50 0x0004000000000000ull -#endif -#ifndef BIT51 - #define BIT51 0x0008000000000000ull -#endif -#ifndef BIT52 - #define BIT52 0x0010000000000000ull -#endif -#ifndef BIT53 - #define BIT53 0x0020000000000000ull -#endif -#ifndef BIT54 - #define BIT54 0x0040000000000000ull -#endif -#ifndef BIT55 - #define BIT55 0x0080000000000000ull -#endif -#ifndef BIT56 - #define BIT56 0x0100000000000000ull -#endif -#ifndef BIT57 - #define BIT57 0x0200000000000000ull -#endif -#ifndef BIT58 - #define BIT58 0x0400000000000000ull -#endif -#ifndef BIT59 - #define BIT59 0x0800000000000000ull -#endif -#ifndef BIT60 - #define BIT60 0x1000000000000000ull -#endif -#ifndef BIT61 - #define BIT61 0x2000000000000000ull -#endif -#ifndef BIT62 - #define BIT62 0x4000000000000000ull -#endif -#ifndef BIT63 - #define BIT63 0x8000000000000000ull -#endif -#endif diff --git a/src/southbridge/amd/cimx/sb900/AmdSbLib.h b/src/southbridge/amd/cimx/sb900/AmdSbLib.h deleted file mode 100644 index 10a88f2a47..0000000000 --- a/src/southbridge/amd/cimx/sb900/AmdSbLib.h +++ /dev/null @@ -1,160 +0,0 @@ -/* - ***************************************************************************** - * - * This file is part of the coreboot project. - * - * Copyright (C) 2011 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * *************************************************************************** - * - */ - -#ifndef _AMD_SB_LIB_H_ -#define _AMD_SB_LIB_H_ - -#include - -#pragma pack (push, 1) - -#define IMAGE_ALIGN 32*1024 -#define NUM_IMAGE_LOCATION 32 - -//Entry Point Call -typedef void (*CIM_IMAGE_ENTRY) (void *pConfig); - -//Hook Call - -typedef struct _CIMFILEHEADER -{ - unsigned int AMDLogo; - unsigned long long CreatorID; - unsigned int Version1; - unsigned int Version2; - unsigned int Version3; - unsigned int ModuleInfoOffset; - unsigned int EntryPoint; - unsigned int ImageBase; - unsigned int RelocTableOffset; - unsigned int ImageSize; - unsigned short CheckSum; - unsigned char ImageType; - unsigned char Reserved2; -} CIMFILEHEADER; - -#ifndef BIT0 - #define BIT0 (1 << 0) -#endif -#ifndef BIT1 - #define BIT1 (1 << 1) -#endif -#ifndef BIT2 - #define BIT2 (1 << 2) -#endif -#ifndef BIT3 - #define BIT3 (1 << 3) -#endif -#ifndef BIT4 - #define BIT4 (1 << 4) -#endif -#ifndef BIT5 - #define BIT5 (1 << 5) -#endif -#ifndef BIT6 - #define BIT6 (1 << 6) -#endif -#ifndef BIT7 - #define BIT7 (1 << 7) -#endif -#ifndef BIT8 - #define BIT8 (1 << 8) -#endif -#ifndef BIT9 - #define BIT9 (1 << 9) -#endif -#ifndef BIT10 - #define BIT10 (1 << 10) -#endif -#ifndef BIT11 - #define BIT11 (1 << 11) -#endif -#ifndef BIT12 - #define BIT12 (1 << 12) -#endif -#ifndef BIT13 - #define BIT13 (1 << 13) -#endif -#ifndef BIT14 - #define BIT14 (1 << 14) -#endif -#ifndef BIT15 - #define BIT15 (1 << 15) -#endif -#ifndef BIT16 - #define BIT16 (1 << 16) -#endif -#ifndef BIT17 - #define BIT17 (1 << 17) -#endif -#ifndef BIT18 - #define BIT18 (1 << 18) -#endif -#ifndef BIT19 - #define BIT19 (1 << 19) -#endif -#ifndef BIT20 - #define BIT20 (1 << 20) -#endif -#ifndef BIT21 - #define BIT21 (1 << 21) -#endif -#ifndef BIT22 - #define BIT22 (1 << 22) -#endif -#ifndef BIT23 - #define BIT23 (1 << 23) -#endif -#ifndef BIT24 - #define BIT24 (1 << 24) -#endif -#ifndef BIT25 - #define BIT25 (1 << 25) -#endif -#ifndef BIT26 - #define BIT26 (1 << 26) -#endif -#ifndef BIT27 - #define BIT27 (1 << 27) -#endif -#ifndef BIT28 - #define BIT28 (1 << 28) -#endif -#ifndef BIT29 - #define BIT29 (1 << 29) -#endif -#ifndef BIT30 - #define BIT30 (1 << 30) -#endif -#ifndef BIT31 - #define BIT31 (1 << 31) -#endif - -#pragma pack (pop) - -typedef enum -{ - AccWidthUint8 = 0, - AccWidthUint16, - AccWidthUint32, -} ACC_WIDTH; - -#define S3_SAVE 0x80 - -#endif diff --git a/src/southbridge/amd/cimx/sb900/Kconfig b/src/southbridge/amd/cimx/sb900/Kconfig deleted file mode 100644 index be3b16dd58..0000000000 --- a/src/southbridge/amd/cimx/sb900/Kconfig +++ /dev/null @@ -1,54 +0,0 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2011 Advanced Micro Devices, Inc. -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; version 2 of the License. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## - -config SOUTHBRIDGE_AMD_CIMX_SB900 - bool - default n - select IOAPIC - select AMD_SB_CIMX - select HAVE_CF9_RESET - select HAVE_CF9_RESET_PREPARE - -if SOUTHBRIDGE_AMD_CIMX_SB900 -config SATA_CONTROLLER_MODE - hex - default 0x0 - help - 0x0 = Native IDE mode. - 0x1 = RAID mode. - 0x2 = AHCI mode. - 0x3 = Legacy IDE mode. - 0x4 = IDE->AHCI mode. - 0x5 = AHCI mode as 7804 ID (AMD driver). - 0x6 = IDE->AHCI mode as 7804 ID (AMD driver). - -config PCIB_ENABLE - bool - default n - help - n = Disable PCI Bridge Device 14 Function 4. - y = Enable PCI Bridge Device 14 Function 4. - -config ACPI_SCI_IRQ - hex - default 0x9 - help - Set SCI IRQ to 9. - -config BOOTBLOCK_SOUTHBRIDGE_INIT - string - default "southbridge/amd/cimx/sb900/bootblock.c" - -endif #SOUTHBRIDGE_AMD_CIMX_SB900 diff --git a/src/southbridge/amd/cimx/sb900/Makefile.inc b/src/southbridge/amd/cimx/sb900/Makefile.inc deleted file mode 100644 index ff9ada66fb..0000000000 --- a/src/southbridge/amd/cimx/sb900/Makefile.inc +++ /dev/null @@ -1,34 +0,0 @@ -# -# This file is part of the coreboot project. -# -# Copyright (C) 2011 Advanced Micro Devices, Inc. -# -# This program is free software; you can redistribute it and/or modify -# it under the terms of the GNU General Public License as published by -# the Free Software Foundation; version 2 of the License. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# - - -# SB900 Platform Files - -romstage-y += cfg.c -romstage-y += early.c -romstage-y += smbus.c smbus_spd.c -romstage-y += reset.c -romstage-y += ramtop.c - -postcar-y += ramtop.c - -ramstage-y += cfg.c -ramstage-y += early.c -ramstage-y += late.c -ramstage-y += reset.c -ramstage-y += ramtop.c - -ramstage-y += smbus.c -ramstage-y += lpc.c diff --git a/src/southbridge/amd/cimx/sb900/SbPlatform.h b/src/southbridge/amd/cimx/sb900/SbPlatform.h deleted file mode 100644 index f5c11d4ce0..0000000000 --- a/src/southbridge/amd/cimx/sb900/SbPlatform.h +++ /dev/null @@ -1,148 +0,0 @@ -/* - ***************************************************************************** - * - * This file is part of the coreboot project. - * - * Copyright (C) 2011 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * *************************************************************************** - * - */ - -#ifndef _AMD_SBPLATFORM_H_ -#define _AMD_SBPLATFORM_H_ - -#include - -typedef unsigned long long PLACEHOLDER; - -#ifndef SBOEM_ACPI_RESTORE_SWSMI - #define SBOEM_BEFORE_PCI_RESTORE_SWSMI 0xD3 - #define SBOEM_AFTER_PCI_RESTORE_SWSMI 0xD4 -#endif - -#ifndef _AMD_NB_CIM_X_PROTOCOL_H_ - -/* -/// Extended PCI Address -typedef struct _EXT_PCI_ADDR { - UINT32 Reg :16; ///< / PCI Register - UINT32 Func:3; ///< / PCI Function - UINT32 Dev :5; ///< / PCI Device - UINT32 Bus :8; ///< / PCI Address -} EXT_PCI_ADDR; - -/// PCI Address -typedef union _PCI_ADDR { - UINT32 ADDR; ///< / 32 bit Address - EXT_PCI_ADDR Addr; ///< / Extended PCI Address -} PCI_ADDR; -*/ -#endif -#define FIXUP_PTR(ptr) ptr - -#include "AmdSbLib.h" -#include "Amd.h" -#include "Hudson-2.h" -#include "SbType.h" -#include "AcpiLib.h" -#include "SbDef.h" -#include "SbSubFun.h" -#include "platform_cfg.h" /* mainboard specific configuration */ -#include /* platform default configuration */ -#include -#include "SbBiosRamUsage.h" -#include "EcFan.h" - -//------------------------------------------------------------------------------------------------------------------------// -/** - * SB_CIMx_PARAMETER 0 1 2 Default Value When CIMx Take over - * SpreadSpectrum CIMx take over User (Setup Option) User (Setup Option) Enable - * SpreadSpectrumType CIMx take over User (Setup Option) User (Setup Option) Normal - * HpetTimer CIMx take over User (Setup Option) User (Setup Option) Enable - * HpetMsiDis CIMx take over User (Setup Option) User (Setup Option) Enable (0x00) - * IrConfig CIMx take over User (Setup Option) User (Setup Option) Disable (0x00) - * SpiFastReadEnable CIMx take over User (Setup Option) User (Setup Option) Disable - * SpiFastReadSpeed CIMx take over User (Setup Option) User (Setup Option) Disable (NULL) - * NbSbGen2 CIMx take over User (Setup Option) User (Setup Option) Enable - * AlinkPhyPllPowerDown CIMx take over User (Setup Option) User (Setup Option) Enable - * ResetCpuOnSyncFlood CIMx take over User (Setup Option) User (Setup Option) Enable - * GppGen2 CIMx take over User (Setup Option) User (Setup Option) Disable - * GppMemWrImprove CIMx take over User (Setup Option) User (Setup Option) Enable - * GppPortAspm CIMx take over User (Setup Option) User (Setup Option) Disable - * GppLaneReversal CIMx take over User (Setup Option) User (Setup Option) Disable - * GppPhyPllPowerDown CIMx take over User (Setup Option) User (Setup Option) Enable - * UsbPhyPowerDown CIMx take over User (Setup Option) User (Setup Option) Disable - * SBGecDebugBus CIMx take over User (Setup Option) User (Setup Option) Disable - * SBGecPwr CIMx take over User (Setup Option) User (Setup Option) Never Power down (0x11) - * SataSetMaxGen2 CIMx take over User (Setup Option) User (Setup Option) Max Gen3 (0x00) - * SataClkMode CIMx take over User (Setup Option) User (Setup Option) 0x90 int. 100Mhz - * SataAggrLinkPmCap CIMx take over User (Setup Option) User (Setup Option) Enable - * SataPortMultCap CIMx take over User (Setup Option) User (Setup Option) Enable - * SataPscCap CIMx take over User (Setup Option) User (Setup Option) Enable (0x00) - * SataSscCap CIMx take over User (Setup Option) User (Setup Option) Enable (0x00) - * SataFisBasedSwitching CIMx take over User (Setup Option) User (Setup Option) Disable - * SataCccSupport CIMx take over User (Setup Option) User (Setup Option) Disable - * SataMsiCapability CIMx take over User (Setup Option) User (Setup Option) Enable - * SataClkAutoOff CIMx take over User (Setup Option) User (Setup Option) Disable - * AcDcMsg CIMx take over User (Setup Option) User (Setup Option) Disable - * TimerTickTrack CIMx take over User (Setup Option) User (Setup Option) Disable - * ClockInterruptTag CIMx take over User (Setup Option) User (Setup Option) Disable - * OhciTrafficHanding CIMx take over User (Setup Option) User (Setup Option) Disable - * EhciTrafficHanding CIMx take over User (Setup Option) User (Setup Option) Disable - * FusionMsgCMultiCore CIMx take over User (Setup Option) User (Setup Option) Disable - * FusionMsgCStage CIMx take over User (Setup Option) User (Setup Option) Disable - */ -#define SB_CIMx_PARAMETER 0x02 - -// Generic -#define cimSpreadSpectrumDefault TRUE -#define cimSpreadSpectrumTypeDefault 0x00 // Normal -#define cimHpetTimerDefault TRUE -#define cimHpetMsiDisDefault FALSE // Enable -#define cimIrConfigDefault 0x00 // Disable -#define cimSpiFastReadEnableDefault 0x00 // Disable -#define cimSpiFastReadSpeedDefault 0x00 // NULL -// GPP/AB Controller -#define cimNbSbGen2Default TRUE -#define cimAlinkPhyPllPowerDownDefault TRUE -#define cimResetCpuOnSyncFloodDefault TRUE -#define cimGppGen2Default FALSE -#define cimGppMemWrImproveDefault TRUE -#define cimGppPortAspmDefault FALSE -#define cimGppLaneReversalDefault FALSE -#define cimGppPhyPllPowerDownDefault TRUE -// USB Controller -#define cimUsbPhyPowerDownDefault FALSE -// GEC Controller -#define cimSBGecDebugBusDefault FALSE -#define cimSBGecPwrDefault 0x03 -// Sata Controller -#define cimSataSetMaxGen2Default 0x00 -#define cimSATARefClkSelDefault 0x10 -#define cimSATARefDivSelDefault 0x80 -#define cimSataAggrLinkPmCapDefault TRUE -#define cimSataPortMultCapDefault TRUE -#define cimSataPscCapDefault 0x00 // Enable -#define cimSataSscCapDefault 0x00 // Enable -#define cimSataFisBasedSwitchingDefault FALSE -#define cimSataCccSupportDefault FALSE -#define cimSataClkAutoOffDefault FALSE -#define cimNativepciesupportDefault FALSE -// Fusion Related -#define cimAcDcMsgDefault FALSE -#define cimTimerTickTrackDefault FALSE -#define cimClockInterruptTagDefault FALSE -#define cimOhciTrafficHandingDefault FALSE -#define cimEhciTrafficHandingDefault FALSE -#define cimFusionMsgCMultiCoreDefault FALSE -#define cimFusionMsgCStageDefault FALSE -#endif // _AMD_SBPLATFORM_H_ diff --git a/src/southbridge/amd/cimx/sb900/amd_pci_int_defs.h b/src/southbridge/amd/cimx/sb900/amd_pci_int_defs.h deleted file mode 100644 index 161fa521b5..0000000000 --- a/src/southbridge/amd/cimx/sb900/amd_pci_int_defs.h +++ /dev/null @@ -1,70 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2014 Sage Electronic Engineering, LLC. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef AMD_PCI_INT_DEFS_H -#define AMD_PCI_INT_DEFS_H - -/* - * PIRQ and device routing - these define the index - * into the FCH PCI_INTR 0xC00/0xC01 interrupt - * routing table - */ -#define FCH_INT_TABLE_SIZE 0x54 - -#define PIRQ_NC 0x1F /* Not Used */ -#define PIRQ_A 0x00 /* INT A */ -#define PIRQ_B 0x01 /* INT B */ -#define PIRQ_C 0x02 /* INT C */ -#define PIRQ_D 0x03 /* INT D */ -#define PIRQ_E 0x04 /* INT E */ -#define PIRQ_F 0x05 /* INT F */ -#define PIRQ_G 0x06 /* INT G */ -#define PIRQ_H 0x07 /* INT H */ -#define PIRQ_MISC 0x08 /* Miscellaneous IRQ Settings - See FCH Spec */ -#define PIRQ_MISC0 0x09 /* Miscellaneous0 IRQ Settings */ -#define PIRQ_MISC1 0x0A /* Miscellaneous1 IRQ Settings */ -#define PIRQ_MISC2 0x0B /* Miscellaneous2 IRQ Settings */ -#define PIRQ_SIRQA 0x0C /* Serial IRQ INTA */ -#define PIRQ_SIRQB 0x0D /* Serial IRQ INTA */ -#define PIRQ_SIRQC 0x0E /* Serial IRQ INTA */ -#define PIRQ_SIRQD 0x0F /* Serial IRQ INTA */ -#define PIRQ_SCI 0x10 /* SCI IRQ */ -#define PIRQ_SMBUS 0x11 /* SMBUS 14h.0 */ -#define PIRQ_ASF 0x12 /* ASF */ -#define PIRQ_HDA 0x13 /* HDA 14h.2 */ -#define PIRQ_FC 0x14 /* FC */ -#define PIRQ_GEC 0x15 /* GEC */ -#define PIRQ_PMON 0x16 /* Performance Monitor */ -#define PIRQ_IMC0 0x20 /* IMC INT0 */ -#define PIRQ_IMC1 0x21 /* IMC INT1 */ -#define PIRQ_IMC2 0x22 /* IMC INT2 */ -#define PIRQ_IMC3 0x23 /* IMC INT3 */ -#define PIRQ_IMC4 0x24 /* IMC INT4 */ -#define PIRQ_IMC5 0x25 /* IMC INT5 */ -#define PIRQ_OHCI1 0x30 /* USB OHCI 12h.0 */ -#define PIRQ_EHCI1 0x31 /* USB EHCI 12h.2 */ -#define PIRQ_OHCI2 0x32 /* USB OHCI 13h.0 */ -#define PIRQ_EHCI2 0x33 /* USB EHCI 13h.2 */ -#define PIRQ_OHCI3 0x34 /* USB OHCI 16h.0 */ -#define PIRQ_EHCI3 0x35 /* USB EHCI 16h.2 */ -#define PIRQ_OHCI4 0x36 /* USB OHCI 14h.5 */ -#define PIRQ_IDE 0x40 /* IDE 14h.1 */ -#define PIRQ_SATA 0x41 /* SATA 11h.0 */ -#define PIRQ_GPP0 0x50 /* GPP INT 0 */ -#define PIRQ_GPP1 0x51 /* GPP INT 1 */ -#define PIRQ_GPP2 0x52 /* GPP INT 2 */ -#define PIRQ_GPP3 0x53 /* GPP INT 3 */ - -#endif /* AMD_PCI_INT_DEFS_H */ diff --git a/src/southbridge/amd/cimx/sb900/amd_pci_int_types.h b/src/southbridge/amd/cimx/sb900/amd_pci_int_types.h deleted file mode 100644 index 300969ddde..0000000000 --- a/src/southbridge/amd/cimx/sb900/amd_pci_int_types.h +++ /dev/null @@ -1,29 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2014 Sage Electronic Engineering, LLC. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef AMD_PCI_INT_TYPES_H -#define AMD_PCI_INT_TYPES_H - -const char *intr_types[] = { - [0x00] = "INTA#\t", "INTB#\t", "INTC#\t", "INTD#\t", "INTE#\t", "INTF#\t", "INTG#\t", "INTH#\t", - [0x08] = "Misc\t", "Misc0\t", "Misc1\t", "Misc2\t", "Ser IRQ INTA", "Ser IRQ INTB", "Ser IRQ INTC", "Ser IRQ INTD", - [0x10] = "SCI\t", "SMBUS0\t", "ASF\t", "HDA\t", "FC\t\t", "GEC\t", "PerMon\t", - [0x20] = "IMC INT0\t", "IMC INT1\t", "IMC INT2\t", "IMC INT3\t", "IMC INT4\t", "IMC INT5\t", - [0x30] = "Dev18.0 INTA", "Dev18.2 INTB", "Dev19.0 INTA", "Dev19.2 INTB", "Dev22.0 INTA", "Dev22.2 INTB", "Dev20.5 INTC", - [0x40] = "IDE\t", "SATA\t", - [0x50] = "GPPInt0\t", "GPPInt1\t", "GPPInt2\t", "GPPInt3\t" -}; - -#endif /* AMD_PCI_INT_TYPES_H */ diff --git a/src/southbridge/amd/cimx/sb900/bootblock.c b/src/southbridge/amd/cimx/sb900/bootblock.c deleted file mode 100644 index 11faeab3d7..0000000000 --- a/src/southbridge/amd/cimx/sb900/bootblock.c +++ /dev/null @@ -1,58 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include - -static void sb900_enable_rom(void) -{ - u32 word; - u32 dword; - pci_devfn_t dev; - - dev = PCI_DEV(0, 0x14, 0x03); - /* SB900 LPC Bridge 0:20:3:44h. - * BIT6: Port Enable for serial port 0x3f8-0x3ff - * BIT29: Port Enable for KBC port 0x60 and 0x64 - * BIT30: Port Enable for ACPI Micro-Controller port 0x66 and 0x62 - */ - dword = pci_io_read_config32(dev, 0x44); - //dword |= (1<<6) | (1<<29) | (1<<30); - /*Turn on all of LPC IO Port decode enable */ - dword = 0xffffffff; - pci_io_write_config32(dev, 0x44, dword); - - /* SB900 LPC Bridge 0:20:3:48h. - * BIT0: Port Enable for SuperIO 0x2E-0x2F - * BIT1: Port Enable for SuperIO 0x4E-0x4F - * BIT4: Port Enable for LPC ROM Address Arrage2 (0x68-0x6C) - * BIT6: Port Enable for RTC IO 0x70-0x73 - * BIT21: Port Enable for Port 0x80 - */ - dword = pci_io_read_config32(dev, 0x48); - dword |= (1<<0) | (1<<1) | (1<<4) | (1<<6) | (1<<21); - pci_io_write_config32(dev, 0x48, dword); - - /* Enable 4MB ROM access at 0xFFE00000 - 0xFFFFFFFF */ - /* Set the 4MB enable bits */ - word = pci_io_read_config16(dev, 0x6c); - word = 0xFFC0; - pci_io_write_config16(dev, 0x6c, word); -} - -static void bootblock_southbridge_init(void) -{ - /* Setup the ROM access for 2M */ - sb900_enable_rom(); -} diff --git a/src/southbridge/amd/cimx/sb900/cfg.c b/src/southbridge/amd/cimx/sb900/cfg.c deleted file mode 100644 index 2e4173fb92..0000000000 --- a/src/southbridge/amd/cimx/sb900/cfg.c +++ /dev/null @@ -1,298 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include - -#include "SbPlatform.h" -#include "platform_cfg.h" - -/** - * @brief South Bridge CIMx configuration - * - * should be called before execute CIMx function. - * this function will be called in romstage and ramstage. - */ -void sb900_cimx_config(AMDSBCFG *sb_config) -{ - if (!sb_config) { - printk(BIOS_INFO, "SB900 - Cfg.c - sb900_cimx_config - No sb_config.\n"); - return; - } - printk(BIOS_INFO, "SB900 - Cfg.c - sb900_cimx_config - Start.\n"); - memset(sb_config, 0, sizeof(AMDSBCFG)); - - /* static Build Parameters */ - sb_config->BuildParameters.BiosSize = BIOS_SIZE; - sb_config->BuildParameters.LegacyFree = LEGACY_FREE; - sb_config->BuildParameters.WatchDogTimerBase = WATCHDOG_TIMER_BASE_ADDRESS; // Board Level - sb_config->BuildParameters.AcpiGpe0BlkAddr = GPE0_BLK_ADDRESS; // Board Level - sb_config->BuildParameters.CpuControlBlkAddr = CPU_CNT_BLK_ADDRESS; // Board Level - sb_config->BuildParameters.AcpiPmTmrBlkAddr = PM1_TMR_BLK_ADDRESS; // Board Level - sb_config->BuildParameters.AcpiPm1CntBlkAddr = PM1_CNT_BLK_ADDRESS; // Board Level - sb_config->BuildParameters.AcpiPm1EvtBlkAddr = PM1_EVT_BLK_ADDRESS; // Board Level - sb_config->BuildParameters.SioPmeBaseAddress = SIO_PME_BASE_ADDRESS; // Board Level - sb_config->BuildParameters.SpiRomBaseAddress = SPI_BASE_ADDRESS; // Board Level - sb_config->BuildParameters.Smbus0BaseAddress = SMBUS0_BASE_ADDRESS; // Board Level - sb_config->BuildParameters.Smbus1BaseAddress = SMBUS1_BASE_ADDRESS; // Board Level - - /* Turn on CDROM and HDD Power */ - sb_config->SATAMODE.SataMode.SataClkMode = SATA_CLK_RESERVED; - - // header - sb_config->StdHeader.PcieBasePtr = PCIEX_BASE_ADDRESS; - - // Build Parameters - sb_config->BuildParameters.ImcEnableOverWrite = IMC_ENABLE_OVER_WRITE; // Internal Option - sb_config->BuildParameters.UsbMsi = USB_MSI; // Internal Option - sb_config->BuildParameters.HdAudioMsi = HDAUDIO_MSI; // Internal Option - sb_config->BuildParameters.LpcMsi = LPC_MSI; // Internal Option - sb_config->BuildParameters.PcibMsi = PCIB_MSI; // Internal Option - sb_config->BuildParameters.AbMsi = AB_MSI; // Internal Option - sb_config->BuildParameters.GecShadowRomBase = GEC_SHADOWROM_BASE; // Board Level - sb_config->BuildParameters.HpetBase = HPET_BASE_ADDRESS; // Board Level - sb_config->BuildParameters.SataIDESsid = SATA_IDE_MODE_SSID; // Board Level - sb_config->BuildParameters.SataRAIDSsid = SATA_RAID_MODE_SSID; // Board Level - sb_config->BuildParameters.SataRAID5Ssid = SATA_RAID5_MODE_SSID; // Board Level - sb_config->BuildParameters.SataAHCISsid = SATA_AHCI_SSID; // Board Level - sb_config->BuildParameters.OhciSsid = OHCI_SSID; // Board Level - sb_config->BuildParameters.EhciSsid = EHCI_SSID; // Board Level - sb_config->BuildParameters.Ohci4Ssid = OHCI4_SSID; // Board Level - sb_config->BuildParameters.SmbusSsid = SMBUS_SSID; // Board Level - sb_config->BuildParameters.IdeSsid = IDE_SSID; // Board Level - sb_config->BuildParameters.AzaliaSsid = AZALIA_SSID; // Board Level - sb_config->BuildParameters.LpcSsid = LPC_SSID; // Board Level - // sb_config->BuildParameters.PCIBSsid = PCIB_SSID; // Field Retired - - // - // Common Function - // - sb_config->SATAMODE.SataMode.SataController = SATA_CONTROLLER; // External Option - sb_config->SATAMODE.SataMode.SataIdeCombMdPriSecOpt = SATA_IDE_COMBMD_PRISEC_OPT; // External Option - sb_config->SATAMODE.SataMode.SataIdeCombinedMode = SATA_IDECOMBINED_MODE; // External Option - sb_config->S3Resume = 0; // CIMx Internal Used - sb_config->SpreadSpectrum = INCHIP_SPREAD_SPECTRUM; // Board Level - sb_config->NbSbGen2 = INCHIP_NB_SB_GEN2; // External Option - sb_config->GppGen2 = INCHIP_GPP_GEN2; // External Option - sb_config->GppMemWrImprove = INCHIP_GPP_MEMORY_WRITE_IMPROVE; // Internal Option - sb_config->S4Resume = 0; // CIMx Internal Used - sb_config->SataClass = CONFIG_SATA_CONTROLLER_MODE; // INCHIP_SATA_MODE // External Option - sb_config->SataIdeMode = INCHIP_IDE_MODE; // External Option - sb_config->sdConfig = SB_SD_CONFIG; // External Option - sb_config->sdSpeed = SB_SD_SPEED; // Internal Option - sb_config->sdBitwidth = SB_SD_BITWIDTH; // Internal Option - sb_config->SataDisUnusedIdePChannel = SATA_DISUNUSED_IDE_P_CHANNEL; // External Option - sb_config->SataDisUnusedIdeSChannel = SATA_DISUNUSED_IDE_S_CHANNEL; // External Option - sb_config->IdeDisUnusedIdePChannel = IDE_DISUNUSED_IDE_P_CHANNEL; // External Option - sb_config->IdeDisUnusedIdeSChannel = IDE_DISUNUSED_IDE_S_CHANNEL; // External Option - sb_config->SATAESPPORT.SataEspPort.PORT0 = SATA_ESP_PORT0; // Board Level - sb_config->SATAESPPORT.SataEspPort.PORT1 = SATA_ESP_PORT1; // Board Level - sb_config->SATAESPPORT.SataEspPort.PORT2 = SATA_ESP_PORT2; // Board Level - sb_config->SATAESPPORT.SataEspPort.PORT3 = SATA_ESP_PORT3; // Board Level - sb_config->SATAESPPORT.SataEspPort.PORT4 = SATA_ESP_PORT4; // Board Level - sb_config->SATAESPPORT.SataEspPort.PORT5 = SATA_ESP_PORT5; // Board Level - sb_config->SATAESPPORT.SataEspPort.PORT6 = SATA_ESP_PORT6; // Board Level - sb_config->SATAESPPORT.SataEspPort.PORT7 = SATA_ESP_PORT7; // Board Level - sb_config->SATAPORTPOWER.SataPortPower.PORT0 = SATA_PORT_POWER_PORT0; // Board Level - sb_config->SATAPORTPOWER.SataPortPower.PORT1 = SATA_PORT_POWER_PORT1; // Board Level - sb_config->SATAPORTPOWER.SataPortPower.PORT2 = SATA_PORT_POWER_PORT2; // Board Level - sb_config->SATAPORTPOWER.SataPortPower.PORT3 = SATA_PORT_POWER_PORT3; // Board Level - sb_config->SATAPORTPOWER.SataPortPower.PORT4 = SATA_PORT_POWER_PORT4; // Board Level - sb_config->SATAPORTPOWER.SataPortPower.PORT5 = SATA_PORT_POWER_PORT5; // Board Level - sb_config->SATAPORTPOWER.SataPortPower.PORT6 = SATA_PORT_POWER_PORT6; // Board Level - sb_config->SATAPORTPOWER.SataPortPower.PORT7 = SATA_PORT_POWER_PORT7; // Board Level - sb_config->SATAPORTMODE.SataPortMd.PORT0 = SATA_PORTMODE_PORT0; // Board Level - sb_config->SATAPORTMODE.SataPortMd.PORT1 = SATA_PORTMODE_PORT1; // Board Level - sb_config->SATAPORTMODE.SataPortMd.PORT2 = SATA_PORTMODE_PORT2; // Board Level - sb_config->SATAPORTMODE.SataPortMd.PORT3 = SATA_PORTMODE_PORT3; // Board Level - sb_config->SATAPORTMODE.SataPortMd.PORT4 = SATA_PORTMODE_PORT4; // Board Level - sb_config->SATAPORTMODE.SataPortMd.PORT5 = SATA_PORTMODE_PORT5; // Board Level - sb_config->SATAPORTMODE.SataPortMd.PORT6 = SATA_PORTMODE_PORT6; // Board Level - sb_config->SATAPORTMODE.SataPortMd.PORT7 = SATA_PORTMODE_PORT7; // Board Level - sb_config->SataAggrLinkPmCap = INCHIP_SATA_AGGR_LINK_PM_CAP; // Internal Option - sb_config->SataPortMultCap = INCHIP_SATA_PORT_MULT_CAP; // Internal Option - sb_config->SataClkAutoOff = INCHIP_SATA_CLK_AUTO_OFF; // External Option - sb_config->SataPscCap = INCHIP_SATA_PSC_CAP; // External Option - sb_config->SataFisBasedSwitching = INCHIP_SATA_FIS_BASE_SW; // External Option - sb_config->SataCccSupport = INCHIP_SATA_CCC_SUPPORT; // External Option - sb_config->SataSscCap = INCHIP_SATA_SSC_CAP; // External Option - sb_config->SataMsiCapability = INCHIP_SATA_MSI_CAP; // Internal Option - sb_config->SataForceRaid = INCHIP_SATA_FORCE_RAID5; // Internal Option - sb_config->SataTargetSupport8Device = CIMXSB_SATA_TARGET_8DEVICE_CAP; // External Option - sb_config->SataDisableGenericMode = SATA_DISABLE_GENERIC_MODE_CAP;// External Option - sb_config->SataAhciEnclosureManagement = SATA_AHCI_ENCLOSURE_CAP; // Internal Option - sb_config->SataSgpio0 = SATA_GPIO_0_CAP; // External Option - sb_config->SataSgpio1 = SATA_GPIO_1_CAP; // External Option - sb_config->SataPhyPllShutDown = SATA_PHY_PLL_SHUTDOWN; // External Option - sb_config->SATAHOTREMOVALENH.SataHotRemoveEnhPort.PORT0 = SATA_HOTREMOVEL_ENH_PORT0; // Board Level - sb_config->SATAHOTREMOVALENH.SataHotRemoveEnhPort.PORT1 = SATA_HOTREMOVEL_ENH_PORT1; // Board Level - sb_config->SATAHOTREMOVALENH.SataHotRemoveEnhPort.PORT2 = SATA_HOTREMOVEL_ENH_PORT2; // Board Level - sb_config->SATAHOTREMOVALENH.SataHotRemoveEnhPort.PORT3 = SATA_HOTREMOVEL_ENH_PORT3; // Board Level - sb_config->SATAHOTREMOVALENH.SataHotRemoveEnhPort.PORT4 = SATA_HOTREMOVEL_ENH_PORT4; // Board Level - sb_config->SATAHOTREMOVALENH.SataHotRemoveEnhPort.PORT5 = SATA_HOTREMOVEL_ENH_PORT5; // Board Level - sb_config->SATAHOTREMOVALENH.SataHotRemoveEnhPort.PORT6 = SATA_HOTREMOVEL_ENH_PORT6; // Board Level - sb_config->SATAHOTREMOVALENH.SataHotRemoveEnhPort.PORT7 = SATA_HOTREMOVEL_ENH_PORT7; // Board Level - // USB - sb_config->USBMODE.UsbMode.Ohci1 = INCHIP_USB_OHCI1_CINFIG; // External Option - sb_config->USBMODE.UsbMode.Ehci1 = INCHIP_USB_EHCI1_CINFIG; // Internal Option* - sb_config->USBMODE.UsbMode.Ohci2 = INCHIP_USB_OHCI2_CINFIG; // External Option - sb_config->USBMODE.UsbMode.Ehci2 = INCHIP_USB_EHCI2_CINFIG; // Internal Option* - sb_config->USBMODE.UsbMode.Ohci3 = INCHIP_USB_OHCI3_CINFIG; // External Option - sb_config->USBMODE.UsbMode.Ehci3 = INCHIP_USB_EHCI3_CINFIG; // Internal Option* - sb_config->USBMODE.UsbMode.Ohci4 = INCHIP_USB_OHCI4_CINFIG; // External Option - // GEC - sb_config->GecConfig = INCHIP_GEC_CONTROLLER; // External Option - sb_config->IrConfig = SB_IR_CONTROLLER; // External Option - sb_config->XhciSwitch = SB_XHCI_SWITCH; // External Option - // Azalia - sb_config->AzaliaController = INCHIP_AZALIA_CONTROLLER; // External Option - sb_config->AzaliaPinCfg = INCHIP_AZALIA_PIN_CONFIG; // Board Level - sb_config->FrontPanelDetected = INCHIP_FRONT_PANEL_DETECTED; // Board Level - sb_config->AZALIACONFIG.AzaliaSdinPin = AZALIA_PIN_CONFIG; // Board Level - sb_config->AZOEMTBL.pAzaliaOemCodecTablePtr = NULL; // Board Level - sb_config->AZOEMFPTBL.pAzaliaOemFpCodecTablePtr = NULL; // Board Level - sb_config->AnyHT200MhzLink = INCHIP_ANY_HT_200MHZ_LINK; // Internal Option - sb_config->HpetTimer = SB_HPET_TIMER; // External Option - sb_config->AzaliaSnoop = INCHIP_AZALIA_SNOOP; // Internal Option* - // Generic - sb_config->NativePcieSupport = INCHIP_NATIVE_PCIE_SUPPOORT; // External Option - // USB - sb_config->UsbPhyPowerDown = INCHIP_USB_PHY_POWER_DOWN; // External Option - sb_config->PcibClkStopOverride = INCHIP_PCIB_CLK_STOP_OVERRIDE;// Internal Option - // sb_config->HpetMsiDis = 0; // Field Retired - // sb_config->ResetCpuOnSyncFlood = 0; // Field Retired - // sb_config->PcibAutoClkCtr = 0; // Field Retired - sb_config->OEMPROGTBL.OemProgrammingTablePtr = (uintptr_t)NULL; // Board Level - sb_config->PORTCONFIG[0].PortCfg.PortPresent = SB_GPP_PORT0; // Board Level - sb_config->PORTCONFIG[0].PortCfg.PortDetected = 0; // CIMx Internal Used - sb_config->PORTCONFIG[0].PortCfg.PortIsGen2 = 0; // CIMx Internal Used - sb_config->PORTCONFIG[0].PortCfg.PortHotPlug = 0; // CIMx Internal Used - // sb_config->PORTCONFIG[0].PortCfg.PortIntxMap = 0; // Field Retired - sb_config->PORTCONFIG[1].PortCfg.PortPresent = SB_GPP_PORT1; // Board Level - sb_config->PORTCONFIG[1].PortCfg.PortDetected = 0; // CIMx Internal Used - sb_config->PORTCONFIG[1].PortCfg.PortIsGen2 = 0; // CIMx Internal Used - sb_config->PORTCONFIG[1].PortCfg.PortHotPlug = 0; // CIMx Internal Used - // sb_config->PORTCONFIG[0].PortCfg.PortIntxMap = 0; // Field Retired - sb_config->PORTCONFIG[2].PortCfg.PortPresent = SB_GPP_PORT2; // Board Level - sb_config->PORTCONFIG[2].PortCfg.PortDetected = 0; // CIMx Internal Used - sb_config->PORTCONFIG[2].PortCfg.PortIsGen2 = 0; // CIMx Internal Used - sb_config->PORTCONFIG[2].PortCfg.PortHotPlug = 0; // CIMx Internal Used - // sb_config->PORTCONFIG[0].PortCfg.PortIntxMap = 0; // Field Retired - sb_config->PORTCONFIG[3].PortCfg.PortPresent = SB_GPP_PORT3; // Board Level - sb_config->PORTCONFIG[3].PortCfg.PortDetected = 0; // CIMx Internal Used - sb_config->PORTCONFIG[3].PortCfg.PortIsGen2 = 0; // CIMx Internal Used - sb_config->PORTCONFIG[3].PortCfg.PortHotPlug = 0; // CIMx Internal Used - // sb_config->PORTCONFIG[0].PortCfg.PortIntxMap = 0; // Field Retired - sb_config->GppLinkConfig = INCHIP_GPP_LINK_CONFIG; // External Option - sb_config->GppFoundGfxDev = 0; // CIMx Internal Used - sb_config->GppFunctionEnable = SB_GPP_CONTROLLER; // External Option - sb_config->GppUnhidePorts = INCHIP_GPP_UNHIDE_PORTS; // Internal Option - sb_config->GppPortAspm = INCHIP_GPP_PORT_ASPM; // Internal Option - sb_config->GppLaneReversal = INCHIP_GPP_LANEREVERSAL; // External Option - sb_config->AlinkPhyPllPowerDown = INCHIP_ALINK_PHY_PLL_POWER_DOWN; // External Option - sb_config->GppPhyPllPowerDown = INCHIP_GPP_PHY_PLL_POWER_DOWN;// External Option - sb_config->GppDynamicPowerSaving = INCHIP_GPP_DYNAMIC_POWER_SAVING; // External Option - sb_config->PcieAER = INCHIP_PCIE_AER; // External Option - sb_config->PcieRAS = INCHIP_PCIE_RAS; // External Option - sb_config->GppHardwareDowngrade = INCHIP_GPP_HARDWARE_DOWNGRADE;// Internal Option - sb_config->GppToggleReset = INCHIP_GPP_TOGGLE_RESET; // External Option - sb_config->sdbEnable = 0; // CIMx Internal Used - sb_config->TempMMIO = (UINTN)NULL; // CIMx Internal Used - // sb_config->GecPhyStatus = INCHIP_GEC_PHY_STATUS; // Field Retired - sb_config->SBGecPwr = INCHIP_GEC_POWER_POLICY; // Internal Option - sb_config->SBGecDebugBus = INCHIP_GEC_DEBUGBUS; // Internal Option - sb_config->SbPcieOrderRule = INCHIP_SB_PCIE_ORDER_RULE; // External Option - sb_config->AcDcMsg = INCHIP_ACDC_MSG; // Internal Option - sb_config->TimerTickTrack = INCHIP_TIMER_TICK_TRACK; // Internal Option - sb_config->ClockInterruptTag = INCHIP_CLOCK_INTERRUPT_TAG; // Internal Option - sb_config->OhciTrafficHanding = INCHIP_OHCI_TRAFFIC_HANDING; // Internal Option - sb_config->EhciTrafficHanding = INCHIP_EHCI_TRAFFIC_HANDING; // Internal Option - sb_config->FusionMsgCMultiCore = INCHIP_FUSION_MSGC_MULTICORE; // Internal Option - sb_config->FusionMsgCStage = INCHIP_FUSION_MSGC_STAGE; // Internal Option - sb_config->ALinkClkGateOff = INCHIP_ALINK_CLK_GATE_OFF; // External Option - sb_config->BLinkClkGateOff = INCHIP_BLINK_CLK_GATE_OFF; // External Option - // sb_config->sdb = 0; // Field Retired - sb_config->GppGen2Strap = 0; // CIMx Internal Used - sb_config->SlowSpeedABlinkClock = INCHIP_SLOW_SPEED_ABLINK_CLOCK; // Internal Option - sb_config->DYNAMICGECROM.DynamicGecRomAddress_Ptr = NULL; // Board Level - sb_config->AbClockGating = INCHIP_AB_CLOCK_GATING; // External Option - sb_config->GppClockGating = INCHIP_GPP_CLOCK_GATING; // External Option - sb_config->L1TimerOverwrite = INCHIP_L1_TIMER_OVERWRITE; // Internal Option - // sb_config->UmiLinkWidth = 0; // Field Retired - sb_config->UmiDynamicSpeedChange = INCHIP_UMI_DYNAMIC_SPEED_CHANGE; // Internal Option - // sb_config->PcieRefClockOverclocking = 0; // Field Retired - sb_config->SbAlinkGppTxDriverStrength = INCHIP_ALINK_GPP_TX_DRV_STRENGTH; // Internal Option - sb_config->PwrFailShadow = 0x02; // Board Level - sb_config->StressResetMode = INCHIP_STRESS_RESET_MODE; // Internal Option - sb_config->hwm.fanSampleFreqDiv = 0x03; // Board Level - sb_config->hwm.hwmSbtsiAutoPoll = 1; // Board Level - - /* General */ - sb_config->PciClks = SB_PCI_CLOCK_RESERVED; - sb_config->hwm.hwmEnable = 0x0; - - /* ramstage cimx config here */ - if (ENV_RAMSTAGE && !sb_config->StdHeader.CALLBACK.CalloutPtr) { - sb_config->StdHeader.CALLBACK.CalloutPtr = sb900_callout_entry; - } - - //sb_config-> - printk(BIOS_INFO, "SB900 - Cfg.c - sb900_cimx_config - End.\n"); -} - -void SbPowerOnInit_Config(AMDSBCFG *sb_config) -{ - if (!sb_config) { - printk(BIOS_INFO, "SB900 - Cfg.c - SbPowerOnInit_Config - No sb_config.\n"); - return; - } - printk(BIOS_INFO, "SB900 - Cfg.c - SbPowerOnInit_Config - Start.\n"); - memset(sb_config, 0, sizeof(AMDSBCFG)); - - // Set the build parameters - sb_config->BuildParameters.BiosSize = BIOS_SIZE; // Field Retired - sb_config->BuildParameters.LegacyFree = SBCIMx_LEGACY_FREE; // Board Level - sb_config->BuildParameters.SpiSpeed = SBCIMX_SPI_SPEED; // Internal Option - sb_config->BuildParameters.SpiFastSpeed = SBCIMX_SPI_FASTSPEED; // Internal Option - // sb_config->BuildParameters.SpiWriteSpeed = 0; // Field Retired - sb_config->BuildParameters.SpiMode = SBCIMX_SPI_MODE; // Internal Option - sb_config->BuildParameters.SpiBurstWrite = SBCIMX_SPI_BURST_WRITE; // Internal Option - sb_config->BuildParameters.EcKbd = INCHIP_EC_KBD; // Board Level - sb_config->BuildParameters.Smbus0BaseAddress = SMBUS0_BASE_ADDRESS; // Board Level - sb_config->BuildParameters.Smbus1BaseAddress = SMBUS1_BASE_ADDRESS; // Board Level - sb_config->BuildParameters.SioPmeBaseAddress = SIO_PME_BASE_ADDRESS; // Board Level - sb_config->BuildParameters.WatchDogTimerBase = WATCHDOG_TIMER_BASE_ADDRESS; // Board Level - sb_config->BuildParameters.GecShadowRomBase = GEC_ROM_SHADOW_ADDRESS; // Board Level - sb_config->BuildParameters.SpiRomBaseAddress = SPI_BASE_ADDRESS; // Board Level - sb_config->BuildParameters.AcpiPm1EvtBlkAddr = PM1_EVT_BLK_ADDRESS; // Board Level - sb_config->BuildParameters.AcpiPm1CntBlkAddr = PM1_CNT_BLK_ADDRESS; // Board Level - sb_config->BuildParameters.AcpiPmTmrBlkAddr = PM1_TMR_BLK_ADDRESS; // Board Level - sb_config->BuildParameters.CpuControlBlkAddr = CPU_CNT_BLK_ADDRESS; // Board Level - sb_config->BuildParameters.AcpiGpe0BlkAddr = GPE0_BLK_ADDRESS; // Board Level - sb_config->BuildParameters.SmiCmdPortAddr = SMI_CMD_PORT; // Board Level - sb_config->BuildParameters.AcpiPmaCntBlkAddr = ACPI_PMA_CNT_BLK_ADDRESS; // Board Level - sb_config->SATAMODE.SataMode.SataController = INCHIP_SATA_CONTROLLER; // External Option - sb_config->SATAMODE.SataMode.SataIdeCombMdPriSecOpt = SATA_COMBINE_MODE_CHANNEL;// External Option - sb_config->SATAMODE.SataMode.SataSetMaxGen2 = SATA_MAX_GEN2_MODE; // External Option - sb_config->SATAMODE.SataMode.SataIdeCombinedMode= SATA_COMBINE_MODE; // External Option - sb_config->SATAMODE.SataMode.SataClkMode = SATA_CLK_RESERVED; // Internal Option - sb_config->NbSbGen2 = NB_SB_GEN2; // External Option - sb_config->SataInternal100Spread = INCHIP_SATA_INTERNAL_100_SPREAD; // External Option - sb_config->OEMPROGTBL.OemProgrammingTablePtr = (uintptr_t)NULL; // Board Level - sb_config->sdbEnable = 0; // CIMx Internal Used - sb_config->Cg2Pll = INCHIP_CG2_PLL; // Internal Option - - printk(BIOS_INFO, "SB900 - Cfg.c - SbPowerOnInit_Config - End.\n"); -} diff --git a/src/southbridge/amd/cimx/sb900/chip.h b/src/southbridge/amd/cimx/sb900/chip.h deleted file mode 100644 index 73561c0699..0000000000 --- a/src/southbridge/amd/cimx/sb900/chip.h +++ /dev/null @@ -1,36 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef _CIMX_SB900_CHIP_H_ -#define _CIMX_SB900_CHIP_H_ - -/* - * configuration set in mainboard/devicetree.cb - * boot_switch_sata_ide: - * 0 -set SATA as primary, PATA(IDE) as secondary. - * 1 -set PATA(IDE) as primary, SATA as secondary. if you want to boot from IDE, - * gpp_configuration - The configuration of General Purpose Port A/B/C/D - * 0(GPP_CFGMODE_X4000) -PortA Lanes[3:0] - * 2(GPP_CFGMODE_X2200) -PortA Lanes[1:0], PortB Lanes[3:2] - * 3(GPP_CFGMODE_X2110) -PortA Lanes[1:0], PortB Lane2, PortC Lane3 - * 4(GPP_CFGMODE_X1111) -PortA Lanes0, PortB Lane1, PortC Lane2, PortD Lane3 - */ -struct southbridge_amd_cimx_sb900_config -{ - u32 boot_switch_sata_ide : 1; - u8 gpp_configuration; -}; - -#endif /* _CIMX_SB900_CHIP_H_ */ diff --git a/src/southbridge/amd/cimx/sb900/early.c b/src/southbridge/amd/cimx/sb900/early.c deleted file mode 100644 index ccada12dc3..0000000000 --- a/src/southbridge/amd/cimx/sb900/early.c +++ /dev/null @@ -1,138 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -// Use simple device model for this file even in ramstage -#define __SIMPLE_DEVICE__ - -#include -#include -#include "SbPlatform.h" -#include "sb_cimx.h" -#include -#include "smbus.h" - - -/** - * @brief South Bridge CIMx romstage entry, - * wrapper of sbPowerOnInit entry point. - */ -void sb_poweron_init(void) -{ - AMDSBCFG sb_early_cfg; - u8 data; - - printk(BIOS_SPEW, "SB900 - Early.c - sb_poweron_init - Start.\n"); - - //Enable/Disable PCI Bridge Device 14 Function 4. - outb(0xEA, 0xCD6); - data = inb(0xCD7); - data &= ~BIT0; - if (!CONFIG(PCIB_ENABLE)) { - data |= BIT0; - } - outb(data, 0xCD7); - - SbPowerOnInit_Config(&sb_early_cfg); - //sb_early_cfg.StdHeader.Func = SB_POWERON_INIT; - //AmdSbDispatcher(&sb_early_cfg); - //TODO - //AMD_IMAGE_HEADER was missing, when using AmdSbDispatcher, - // VerifyImage() will fail, LocateImage() takes minutes to find the image. - sbPowerOnInit(&sb_early_cfg); - printk(BIOS_SPEW, "SB900 - Early.c - sb_poweron_init - End.\n"); -} - -/** - * @brief South Bridge CIMx romstage entry, - * wrapper of sbPowerOnInit entry point. - */ -void sb_before_pci_init(void) -{ - AMDSBCFG sb_early_cfg; - - printk(BIOS_SPEW, "SB900 - Early.c - sb_before_pci_init - Start.\n"); - sb900_cimx_config(&sb_early_cfg); - //sb_early_cfg.StdHeader.Func = SB_POWERON_INIT; - //AmdSbDispatcher(&sb_early_cfg); - //TODO - //AMD_IMAGE_HEADER was missing, when using AmdSbDispatcher, - // VerifyImage() will fail, LocateImage() takes minutes to find the image. - sbBeforePciInit(&sb_early_cfg); - printk(BIOS_SPEW, "SB900 - Early.c - sb_before_pci_init - End.\n"); -} - -void sb_After_Pci_Init(void) -{ - AMDSBCFG sb_early_cfg; - - printk(BIOS_SPEW, "SB900 - Early.c - sb_After_Pci_Init - Start.\n"); - sb900_cimx_config(&sb_early_cfg); - //sb_early_cfg.StdHeader.Func = SB_POWERON_INIT; - //AmdSbDispatcher(&sb_early_cfg); - //TODO - //AMD_IMAGE_HEADER was missing, when using AmdSbDispatcher, - // VerifyImage() will fail, LocateImage() takes minutes to find the image. - sbAfterPciInit(&sb_early_cfg); - printk(BIOS_SPEW, "SB900 - Early.c - sb_After_Pci_Init - End.\n"); -} - -void sb_Mid_Post_Init(void) -{ - AMDSBCFG sb_early_cfg; - - printk(BIOS_SPEW, "SB900 - Early.c - sb_Mid_Post_Init - Start.\n"); - sb900_cimx_config(&sb_early_cfg); - //sb_early_cfg.StdHeader.Func = SB_POWERON_INIT; - //AmdSbDispatcher(&sb_early_cfg); - //TODO - //AMD_IMAGE_HEADER was missing, when using AmdSbDispatcher, - // VerifyImage() will fail, LocateImage() takes minutes to find the image. - sbMidPostInit(&sb_early_cfg); - printk(BIOS_SPEW, "SB900 - Early.c - sb_Mid_Post_Init - End.\n"); -} - -void sb_Late_Post(void) -{ - AMDSBCFG sb_early_cfg; - u8 data; - - printk(BIOS_SPEW, "SB900 - Early.c - sb_Late_Post - Start.\n"); - sb900_cimx_config(&sb_early_cfg); - //sb_early_cfg.StdHeader.Func = SB_POWERON_INIT; - //AmdSbDispatcher(&sb_early_cfg); - //TODO - //AMD_IMAGE_HEADER was missing, when using AmdSbDispatcher, - // VerifyImage() will fail, LocateImage() takes minutes to find the image. - sbLatePost(&sb_early_cfg); - - //Set ACPI SCI IRQ to 0x9. - data = CONFIG_ACPI_SCI_IRQ; - outb(0x10, 0xC00); - outb(data, 0xC01); - outb(0x90, 0xC00); - outb(data, 0xC01); - - if (data > 0x7) { - data = inb(0x4D1); - data |= (1 << (CONFIG_ACPI_SCI_IRQ - 8)); - outb(data, 0x4D1); - } else { - data = inb(0x4D0); - data |= (1 << (CONFIG_ACPI_SCI_IRQ)); - outb(data, 0x4D0); - } - - printk(BIOS_SPEW, "SB900 - Early.c - sb_Late_Post - End.\n"); -} diff --git a/src/southbridge/amd/cimx/sb900/gpio_oem.h b/src/southbridge/amd/cimx/sb900/gpio_oem.h deleted file mode 100644 index d406887bdc..0000000000 --- a/src/southbridge/amd/cimx/sb900/gpio_oem.h +++ /dev/null @@ -1,66 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef _GPIO_OEM_H_ -#define _GPIO_OEM_H_ - -/* Hudson-2 ACPI PmIO Space Define */ -#define SB_ACPI_BASE_ADDRESS 0x0400 -#define VACPI_MMIO_BASE ((u8 *)0xFED80000) -#define SB_CFG_BASE 0x000 // DWORD -#define GPIO_BASE 0x100 // BYTE -#define SMI_BASE 0x200 // DWORD -#define PMIO_BASE 0x300 // DWORD -#define PMIO2_BASE 0x400 // BYTE -#define BIOS_RAM_BASE 0x500 // BYTE -#define CMOS_RAM_BASE 0x600 // BYTE -#define CMOS_BASE 0x700 // BYTE -#define ASF_BASE 0x900 // DWORD -#define SMBUS_BASE 0xA00 // DWORD -#define WATCHDOG_BASE 0xB00 // ?? -#define HPET_BASE 0xC00 // DWORD -#define IOMUX_BASE 0xD00 // BYTE -#define MISC_BASE 0xE00 -#define SERIAL_DEBUG_BASE 0x1000 -#define GFX_DAC_BASE 0x1400 -#define CEC_BASE 0x1800 -#define XHCI_BASE 0x1C00 -#define ACPI_SMI_DATA_PORT 0xB1 -#define R_SB_ACPI_PM1_STATUS 0x00 -#define R_SB_ACPI_PM1_ENABLE 0x02 -#define R_SB_ACPI_PM_CONTROL 0x04 -#define R_SB_ACPI_EVENT_STATUS 0x20 -#define R_SB_ACPI_EVENT_ENABLE 0x24 -#define B_PWR_BTN_STATUS BIT8 -#define B_WAKEUP_STATUS BIT15 -#define B_SCI_EN BIT0 -#define SB_PM_INDEX_PORT 0xCD6 -#define SB_PM_DATA_PORT 0xCD7 -#define SB_PMIOA_REG24 0x24 // AcpiMmioEn -#define MmioAddress( BaseAddr, Register ) \ - ( (UINTN)BaseAddr + \ - (UINTN)(Register) \ - ) -#define Mmio32Ptr( BaseAddr, Register ) \ - ( (volatile UINT32 *)MmioAddress( BaseAddr, Register ) ) -#define Mmio32( BaseAddr, Register ) \ - *Mmio32Ptr( BaseAddr, Register ) - -#define SB_GPIO_REG01 1 -#define SB_GPIO_REG02 2 -#define SB_GPIO_REG15 15 -#define SB_GPIO_REG24 24 -#define SB_GPIO_REG25 25 -#define SB_GPIO_REG27 27 - -#endif diff --git a/src/southbridge/amd/cimx/sb900/late.c b/src/southbridge/amd/cimx/sb900/late.c deleted file mode 100644 index 3a65e33804..0000000000 --- a/src/southbridge/amd/cimx/sb900/late.c +++ /dev/null @@ -1,457 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - - -#include -#include /* device_operations */ -#include -#include /* smbus_bus_operations */ -#include -#include -#include -#include /* printk */ -#include -#include -#include "lpc.h" /* lpc_read_resources */ -#include "SbPlatform.h" /* Platform Specific Definitions */ -#include "chip.h" /* struct southbridge_amd_cimx_sb900_config */ - -#ifndef _RAMSTAGE_ -#define _RAMSTAGE_ -#endif -static AMDSBCFG sb_late_cfg; //global, init in sb900_cimx_config -static AMDSBCFG *sb_config = &sb_late_cfg; - - -/** - * @brief Entry point of Southbridge CIMx callout - * - * prototype UINT32 (*SBCIM_HOOK_ENTRY)(UINT32 Param1, UINT32 Param2, void* pConfig) - * - * @param[in] func Southbridge CIMx Function ID. - * @param[in] data Southbridge Input Data. - * @param[in] config Southbridge configuration structure pointer. - * - */ -u32 sb900_callout_entry(u32 func, u32 data, void *config) -{ - u32 ret = 0; - - printk(BIOS_DEBUG, "SB900 - Late.c - sb900_callout_entry - Start.\n"); - switch (func) { - case CB_SBGPP_RESET_ASSERT: - break; - - case CB_SBGPP_RESET_DEASSERT: - break; - -//- case IMC_FIRMWARE_FAIL: -//- break; - - default: - break; - } - - printk(BIOS_DEBUG, "SB900 - Late.c - sb900_callout_entry - End.\n"); - return ret; -} - - -static struct pci_operations lops_pci = { - .set_subsystem = 0, -}; - -static void lpc_enable_resources(struct device *dev) -{ - - printk(BIOS_DEBUG, "SB900 - Late.c - lpc_enable_resources - Start.\n"); - pci_dev_enable_resources(dev); - //lpc_enable_childrens_resources(dev); - printk(BIOS_DEBUG, "SB900 - Late.c - lpc_enable_resources - End.\n"); -} - -static void lpc_init(struct device *dev) -{ - printk(BIOS_DEBUG, "SB900 - Late.c - lpc_init - Start.\n"); - /* SB Configure HPET base and enable bit */ -//- hpetInit(sb_config, &(sb_config->BuildParameters)); - cmos_check_update_date(); - - /* Initialize the real time clock. - * The 0 argument tells cmos_init not to - * update CMOS unless it is invalid. - * 1 tells cmos_init to always initialize the CMOS. - */ - cmos_init(0); - - setup_i8259(); /* Initialize i8259 pic */ - setup_i8254(); /* Initialize i8254 timers */ - - printk(BIOS_DEBUG, "SB900 - Late.c - lpc_init - End.\n"); -} - -unsigned long acpi_fill_mcfg(unsigned long current) -{ - /* Just a dummy */ - return current; -} - -static struct device_operations lpc_ops = { - .read_resources = lpc_read_resources, - .set_resources = lpc_set_resources, - .enable_resources = lpc_enable_resources, - .init = lpc_init, -#if CONFIG(HAVE_ACPI_TABLES) - .write_acpi_tables = acpi_write_hpet, -#endif - .scan_bus = scan_static_bus, - .ops_pci = &lops_pci, -}; - -static const struct pci_driver lpc_driver __pci_driver = { - .ops = &lpc_ops, - .vendor = PCI_VENDOR_ID_AMD, - .device = PCI_DEVICE_ID_AMD_SB900_LPC, -}; - - -static void sata_enable_resources(struct device *dev) -{ - printk(BIOS_DEBUG, "SB900 - Late.c - sata_enable_resources - Start.\n"); -//- sataInitAfterPciEnum(sb_config); - pci_dev_enable_resources(dev); - printk(BIOS_DEBUG, "SB900 - Late.c - sata_enable_resources - End.\n"); -} - -static void sata_init(struct device *dev) -{ - printk(BIOS_DEBUG, "SB900 - Late.c - sata_init - Start.\n"); - sb_config->StdHeader.Func = SB_MID_POST_INIT; -//- AmdSbDispatcher(sb_config); //sataInitMidPost only -//- commonInitLateBoot(sb_config); -//- sataInitLatePost(sb_config); - printk(BIOS_DEBUG, "SB900 - Late.c - sata_init - End.\n"); -} - -static struct device_operations sata_ops = { - .read_resources = pci_dev_read_resources, - .set_resources = pci_dev_set_resources, - .enable_resources = sata_enable_resources, //pci_dev_enable_resources, - .init = sata_init, - .scan_bus = 0, - .ops_pci = &lops_pci, -}; - -static const struct pci_driver sata_driver __pci_driver = { - .ops = &sata_ops, - .vendor = PCI_VENDOR_ID_AMD, -#if (CONFIG_SATA_CONTROLLER_MODE == 0x0 || CONFIG_SATA_CONTROLLER_MODE == 0x3) - .device = PCI_DEVICE_ID_AMD_SB900_SATA, //SATA IDE Mode -#endif -#if (CONFIG_SATA_CONTROLLER_MODE == 0x2 || CONFIG_SATA_CONTROLLER_MODE == 0x4) - .device = PCI_DEVICE_ID_AMD_SB900_SATA_AHCI, //SATA AHCI Mode -#endif -#if (CONFIG_SATA_CONTROLLER_MODE == 0x5 || CONFIG_SATA_CONTROLLER_MODE == 0x6) - .device = PCI_DEVICE_ID_AMD_SB900_SATA_AMDAHCI, //SATA AMDAHCI Mode -#endif -#if (CONFIG_SATA_CONTROLLER_MODE == 0x1 && INCHIP_SATA_FORCE_RAID5 == 0x0) - .device = PCI_DEVICE_ID_AMD_SB900_SATA_RAID5, //SATA RAID5 Mode -#endif -#if (CONFIG_SATA_CONTROLLER_MODE == 0x1 && INCHIP_SATA_FORCE_RAID5 == 0x1) - .device = PCI_DEVICE_ID_AMD_SB900_SATA_RAID, //SATA RAID Mode -#endif -}; - -static void usb_init(struct device *dev) -{ - printk(BIOS_DEBUG, "SB900 - Late.c - usb_init - Start.\n"); -//- usbInitAfterPciInit(sb_config); -//- commonInitLateBoot(sb_config); - printk(BIOS_DEBUG, "SB900 - Late.c - usb_init - End.\n"); -} - -static struct device_operations usb_ops = { - .read_resources = pci_ehci_read_resources, - .set_resources = pci_dev_set_resources, - .enable_resources = pci_dev_enable_resources, - .init = usb_init, - .scan_bus = 0, - .ops_pci = &lops_pci, -}; - -/* - * The pci id of usb ctrl 0 and 1 are the same. - */ -static const struct pci_driver usb_xhci123_driver __pci_driver = { - .ops = &usb_ops, - .vendor = PCI_VENDOR_ID_AMD, - .device = PCI_DEVICE_ID_AMD_SB900_USB_16_0, /* XHCI-USB1, XHCI-USB2 */ -}; - -static const struct pci_driver usb_ohci123_driver __pci_driver = { - .ops = &usb_ops, - .vendor = PCI_VENDOR_ID_AMD, - .device = PCI_DEVICE_ID_AMD_SB900_USB_18_0, /* OHCI-USB1, OHCI-USB2, OHCI-USB3 */ -}; - -static const struct pci_driver usb_ehci123_driver __pci_driver = { - .ops = &usb_ops, - .vendor = PCI_VENDOR_ID_AMD, - .device = PCI_DEVICE_ID_AMD_SB900_USB_18_2, /* EHCI-USB1, EHCI-USB2, EHCI-USB3 */ -}; - -static const struct pci_driver usb_ohci4_driver __pci_driver = { - .ops = &usb_ops, - .vendor = PCI_VENDOR_ID_AMD, - .device = PCI_DEVICE_ID_AMD_SB900_USB_20_5, /* OHCI-USB4 */ -}; - - -static void azalia_init(struct device *dev) -{ - printk(BIOS_DEBUG, "SB900 - Late.c - azalia_init - Start.\n"); -//- azaliaInitAfterPciEnum(sb_config); //Detect and configure High Definition Audio - printk(BIOS_DEBUG, "SB900 - Late.c - azalia_init - End.\n"); -} - -static struct device_operations azalia_ops = { - .read_resources = pci_dev_read_resources, - .set_resources = pci_dev_set_resources, - .enable_resources = pci_dev_enable_resources, - .init = azalia_init, - .scan_bus = 0, - .ops_pci = &lops_pci, -}; - -static const struct pci_driver azalia_driver __pci_driver = { - .ops = &azalia_ops, - .vendor = PCI_VENDOR_ID_AMD, - .device = PCI_DEVICE_ID_AMD_SB900_HDA, -}; - - -static void gec_init(struct device *dev) -{ - printk(BIOS_DEBUG, "SB900 - Late.c - gec_init - Start.\n"); -//- gecInitAfterPciEnum(sb_config); -//- gecInitLatePost(sb_config); - printk(BIOS_DEBUG, "SB900 - Late.c - gec_init - End.\n"); -} - -static struct device_operations gec_ops = { - .read_resources = pci_dev_read_resources, - .set_resources = pci_dev_set_resources, - .enable_resources = pci_dev_enable_resources, - .init = gec_init, - .scan_bus = 0, - .ops_pci = &lops_pci, -}; - -static const struct pci_driver gec_driver __pci_driver = { - .ops = &gec_ops, - .vendor = PCI_VENDOR_ID_AMD, - .device = PCI_DEVICE_ID_AMD_SB900_GEC, -}; - - -static void pcie_init(struct device *dev) -{ - printk(BIOS_DEBUG, "SB900 - Late.c - pcie_init - Start.\n"); -//- sbPcieGppLateInit(sb_config); - printk(BIOS_DEBUG, "SB900 - Late.c - pcie_init - End.\n"); -} - -static struct device_operations pci_ops = { - .read_resources = pci_bus_read_resources, - .set_resources = pci_dev_set_resources, - .enable_resources = pci_bus_enable_resources, - .init = pcie_init, - .scan_bus = pci_scan_bridge, - .reset_bus = pci_bus_reset, - .ops_pci = &lops_pci, -}; - -static const struct pci_driver pci_driver __pci_driver = { - .ops = &pci_ops, - .vendor = PCI_VENDOR_ID_AMD, - .device = PCI_DEVICE_ID_AMD_SB900_PCI, -}; - - -struct device_operations bridge_ops = { - .read_resources = pci_bus_read_resources, - .set_resources = pci_dev_set_resources, - .enable_resources = pci_bus_enable_resources, - .init = pcie_init, - .scan_bus = pci_scan_bridge, - .enable = 0, - .reset_bus = pci_bus_reset, - .ops_pci = &lops_pci, -}; - -/* 0:15:0 PCIe PortA */ -static const struct pci_driver PORTA_driver __pci_driver = { - .ops = &bridge_ops, - .vendor = PCI_VENDOR_ID_AMD, - .device = PCI_DEVICE_ID_AMD_SB900_PCIEA, -}; - -/* 0:15:1 PCIe PortB */ -static const struct pci_driver PORTB_driver __pci_driver = { - .ops = &bridge_ops, - .vendor = PCI_VENDOR_ID_AMD, - .device = PCI_DEVICE_ID_AMD_SB900_PCIEB, -}; - -/* 0:15:2 PCIe PortC */ -static const struct pci_driver PORTC_driver __pci_driver = { - .ops = &bridge_ops, - .vendor = PCI_VENDOR_ID_AMD, - .device = PCI_DEVICE_ID_AMD_SB900_PCIEC, -}; - -/* 0:15:3 PCIe PortD */ -static const struct pci_driver PORTD_driver __pci_driver = { - .ops = &bridge_ops, - .vendor = PCI_VENDOR_ID_AMD, - .device = PCI_DEVICE_ID_AMD_SB900_PCIED, -}; - - -/** - * @brief SB Cimx entry point sbBeforePciInit wrapper - */ -static void sb900_enable(struct device *dev) -{ - u8 gpp_port = 0; - struct southbridge_amd_cimx_sb900_config *sb_chip = - (struct southbridge_amd_cimx_sb900_config *)(dev->chip_info); - - sb900_cimx_config(sb_config); - printk(BIOS_DEBUG, "sb900_enable() "); - - /* Config SouthBridge SMBUS/ACPI/IDE/LPC/PCIB.*/ -//- commonInitEarlyBoot(sb_config); -//- commonInitEarlyPost(sb_config); - - switch (dev->path.pci.devfn) { - case PCI_DEVFN(0x10, 0): /* XHCI-USB */ -//- usbInitBeforePciEnum(sb_config); // USB POST TIME Only - break; - - case PCI_DEVFN(0x11, 0): /* SATA */ - if (dev->enabled) { - sb_config->SATAMODE.SataMode.SataController = ENABLED; - if (sb_chip->boot_switch_sata_ide == 1) - sb_config->SATAMODE.SataMode.SataIdeCombMdPriSecOpt = 0; //0 -IDE as primary. - else if (sb_chip->boot_switch_sata_ide == 0) - sb_config->SATAMODE.SataMode.SataIdeCombMdPriSecOpt = 1; //1 -IDE as secondary. - } else { - sb_config->SATAMODE.SataMode.SataController = DISABLED; - } - -//- sataInitBeforePciEnum(sb_config); // Init SATA class code and PHY - break; - - case PCI_DEVFN(0x12, 0): /* OHCI-USB1 */ - case PCI_DEVFN(0x12, 2): /* EHCI-USB1 */ - case PCI_DEVFN(0x13, 0): /* OHCI-USB2 */ - case PCI_DEVFN(0x13, 2): /* EHCI-USB2 */ - case PCI_DEVFN(0x14, 5): /* OHCI-USB4 */ -//- usbInitBeforePciEnum(sb_config); // USB POST TIME Only - break; - - case PCI_DEVFN(0x14, 0): /* SMBUS */ - break; - - case PCI_DEVFN(0x14, 1): /* IDE */ - if (dev->enabled) { - sb_config->SATAMODE.SataMode.SataIdeCombinedMode = ENABLED; - } else { - sb_config->SATAMODE.SataMode.SataIdeCombinedMode = DISABLED; - } -//- sataInitBeforePciEnum(sb_config); // Init SATA class code and PHY - break; - - case PCI_DEVFN(0x14, 2): /* HDA */ - if (dev->enabled) { - if (sb_config->AzaliaController == AZALIA_DISABLE) { - sb_config->AzaliaController = AZALIA_AUTO; - } - printk(BIOS_DEBUG, "hda enabled\n"); - } else { - sb_config->AzaliaController = AZALIA_DISABLE; - printk(BIOS_DEBUG, "hda disabled\n"); - } -//- azaliaInitBeforePciEnum(sb_config); // Detect and configure High Definition Audio - break; - - - case PCI_DEVFN(0x14, 3): /* LPC */ - break; - - case PCI_DEVFN(0x14, 4): /* PCI */ - break; - - case PCI_DEVFN(0x14, 6): /* GEC */ - if (dev->enabled) { - sb_config->GecConfig = 0; - printk(BIOS_DEBUG, "gec enabled\n"); - } else { - sb_config->GecConfig = 1; - printk(BIOS_DEBUG, "gec disabled\n"); - } -//- gecInitBeforePciEnum(sb_config); // Init GEC - break; - - case PCI_DEVFN(0x15, 0): /* PCIe PortA */ - case PCI_DEVFN(0x15, 1): /* PCIe PortB */ - case PCI_DEVFN(0x15, 2): /* PCIe PortC */ - case PCI_DEVFN(0x15, 3): /* PCIe PortD */ - gpp_port = (dev->path.pci.devfn) & 0x03; - if (dev->enabled) { - sb_config->PORTCONFIG[gpp_port].PortCfg.PortPresent = ENABLED; - } else { - sb_config->PORTCONFIG[gpp_port].PortCfg.PortPresent = DISABLED; - } - - /* - * GPP_CFGMODE_X4000: PortA Lanes[3:0] - * GPP_CFGMODE_X2200: PortA Lanes[1:0], PortB Lanes[3:2] - * GPP_CFGMODE_X2110: PortA Lanes[1:0], PortB Lane2, PortC Lane3 - * GPP_CFGMODE_X1111: PortA Lanes0, PortB Lane1, PortC Lane2, PortD Lane3 - */ - if (sb_config->GppLinkConfig != sb_chip->gpp_configuration) { - sb_config->GppLinkConfig = sb_chip->gpp_configuration; - } - -//- sbPcieGppEarlyInit(sb_config); - break; - - default: - break; - } - - /* Special setting ABCFG registers before PCI emulation. */ -//- abSpecialSetBeforePciEnum(sb_config); -//- usbDesertPll(sb_config); - //sb_config->StdHeader.Func = SB_BEFORE_PCI_INIT; - //AmdSbDispatcher(sb_config); -} - -struct chip_operations southbridge_amd_cimx_sb900_ops = { - CHIP_NAME("ATI SB900") - .enable_dev = sb900_enable, -}; diff --git a/src/southbridge/amd/cimx/sb900/lpc.c b/src/southbridge/amd/cimx/sb900/lpc.c deleted file mode 100644 index 8e7c1cc67f..0000000000 --- a/src/southbridge/amd/cimx/sb900/lpc.c +++ /dev/null @@ -1,182 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include "lpc.h" -#include /* printk */ -#include - - -void lpc_read_resources(struct device *dev) -{ - struct resource *res; - - printk(BIOS_DEBUG, "SB900 - Lpc.c - lpc_read_resources - Start.\n"); - /* Get the normal pci resources of this device */ - pci_dev_read_resources(dev); /* We got one for APIC, or one more for TRAP */ - - /* Add an extra subtractive resource for both memory and I/O. */ - res = new_resource(dev, IOINDEX_SUBTRACTIVE(0, 0)); - res->base = 0; - res->size = 0x1000; - res->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE | - IORESOURCE_ASSIGNED | IORESOURCE_FIXED; - - res = new_resource(dev, IOINDEX_SUBTRACTIVE(1, 0)); - res->base = 0xff800000; - res->size = 0x00800000; /* 8 MB for flash */ - res->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE | - IORESOURCE_ASSIGNED | IORESOURCE_FIXED; - - /* Add a memory resource for the SPI BAR. */ - fixed_mem_resource(dev, 2, SPI_BASE_ADDRESS / 1024, 1, IORESOURCE_SUBTRACTIVE); - - res = new_resource(dev, 3); - res->base = IO_APIC_ADDR; - res->size = 0x00001000; - res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; - - compact_resources(dev); - printk(BIOS_DEBUG, "SB900 - Lpc.c - lpc_read_resources - End.\n"); -} - -void lpc_set_resources(struct device *dev) -{ - struct resource *res; - - printk(BIOS_DEBUG, "SB900 - Lpc.c - lpc_set_resources - Start.\n"); - - /* Special case. SPI Base Address. The SpiRomEnable should STAY set. */ - res = find_resource(dev, 2); - pci_write_config32(dev, SPIROM_BASE_ADDRESS_REGISTER, res->base | SPI_ROM_ENABLE); - - pci_dev_set_resources(dev); - - printk(BIOS_DEBUG, "SB900 - Lpc.c - lpc_set_resources - End.\n"); -} - -/** - * @brief Enable resources for children devices - * - * @param dev the device whose children's resources are to be enabled - * - */ -void lpc_enable_childrens_resources(struct device *dev) -{ - struct bus *link; - u32 reg, reg_x; - int var_num = 0; - u16 reg_var[3]; - - printk(BIOS_DEBUG, "SB900 - Lpc.c - lpc_enable_childrens_resources - Start.\n"); - reg = pci_read_config32(dev, 0x44); - reg_x = pci_read_config32(dev, 0x48); - - for (link = dev->link_list; link; link = link->next) { - struct device *child; - for (child = link->children; child; - child = child->sibling) { - if (child->enabled - && (child->path.type == DEVICE_PATH_PNP)) { - struct resource *res; - for (res = child->resource_list; res; res = res->next) { - u32 base, end; /* don't need long long */ - if (!(res->flags & IORESOURCE_IO)) - continue; - base = res->base; - end = resource_end(res); -/* - printk(BIOS_DEBUG, "sb900 lpc decode:%s, base=0x%08x, end=0x%08x\n", - dev_path(child), base, end); -*/ - switch (base) { - case 0x60: /* KB */ - case 0x64: /* MS */ - reg |= (1 << 29); - break; - case 0x3f8: /* COM1 */ - reg |= (1 << 6); - break; - case 0x2f8: /* COM2 */ - reg |= (1 << 7); - break; - case 0x378: /* Parallel 1 */ - reg |= (1 << 0); - break; - case 0x3f0: /* FD0 */ - reg |= (1 << 26); - break; - case 0x220: /* Audio 0 */ - reg |= (1 << 8); - break; - case 0x300: /* Midi 0 */ - reg |= (1 << 18); - break; - case 0x400: - reg_x |= (1 << 16); - break; - case 0x480: - reg_x |= (1 << 17); - break; - case 0x500: - reg_x |= (1 << 18); - break; - case 0x580: - reg_x |= (1 << 19); - break; - case 0x4700: - reg_x |= (1 << 22); - break; - case 0xfd60: - reg_x |= (1 << 23); - break; - default: - if (var_num >= 3) - continue; /* only 3 var ; compact them ? */ - switch (var_num) { - case 0: - reg_x |= (1 << 2); - break; - case 1: - reg_x |= (1 << 24); - break; - case 2: - reg_x |= (1 << 25); - break; - } - reg_var[var_num++] = - base & 0xffff; - } - } - } - } - } - pci_write_config32(dev, 0x44, reg); - pci_write_config32(dev, 0x48, reg_x); - /* Set WideIO for as many IOs found (fall through is on purpose) */ - switch (var_num) { - case 3: - pci_write_config16(dev, 0x90, reg_var[2]); - /* fall through */ - case 2: - pci_write_config16(dev, 0x66, reg_var[1]); - /* fall through */ - case 1: - //pci_write_config16(dev, 0x64, reg_var[0]); //cause filo can not find sata - break; - } - printk(BIOS_DEBUG, "SB900 - Lpc.c - lpc_enable_childrens_resources - End.\n"); -} diff --git a/src/southbridge/amd/cimx/sb900/lpc.h b/src/southbridge/amd/cimx/sb900/lpc.h deleted file mode 100644 index 3fc5404a9f..0000000000 --- a/src/southbridge/amd/cimx/sb900/lpc.h +++ /dev/null @@ -1,27 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef _SB900_LPC_H_ -#define _SB900_LPC_H_ - -#define SPIROM_BASE_ADDRESS_REGISTER 0xA0 -#define SPI_ROM_ENABLE 0x02 -#define SPI_BASE_ADDRESS 0xFEC10000 - -void lpc_read_resources(struct device *dev); -void lpc_set_resources(struct device *dev); -void lpc_enable_childrens_resources(struct device *dev); - -#endif diff --git a/src/southbridge/amd/cimx/sb900/ramtop.c b/src/southbridge/amd/cimx/sb900/ramtop.c deleted file mode 100644 index 26e930bb7e..0000000000 --- a/src/southbridge/amd/cimx/sb900/ramtop.c +++ /dev/null @@ -1,43 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2010 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include -#include - -void backup_top_of_low_cacheable(uintptr_t ramtop) -{ - u32 dword = ramtop; - int nvram_pos = 0xf8, i; /* temp */ - for (i = 0; i < 4; i++) { - outb(nvram_pos, BIOSRAM_INDEX); - outb((dword >> (8 * i)) & 0xff, BIOSRAM_DATA); - nvram_pos++; - } -} - -uintptr_t restore_top_of_low_cacheable(void) -{ - u32 xdata = 0; - int xnvram_pos = 0xf8, xi; - for (xi = 0; xi < 4; xi++) { - outb(xnvram_pos, BIOSRAM_INDEX); - xdata &= ~(0xff << (xi * 8)); - xdata |= inb(BIOSRAM_DATA) << (xi *8); - xnvram_pos++; - } - return xdata; -} diff --git a/src/southbridge/amd/cimx/sb900/reset.c b/src/southbridge/amd/cimx/sb900/reset.c deleted file mode 100644 index 787f7426ce..0000000000 --- a/src/southbridge/amd/cimx/sb900/reset.c +++ /dev/null @@ -1,48 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 - 2012 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -// Use simple device model for this file even in ramstage -#define __SIMPLE_DEVICE__ - -#include -#include -#include - -#define HT_INIT_CONTROL 0x6C -#define HTIC_BIOSR_Detect (1<<5) - -#define DEV_CDB 0x18 -#define NODE_PCI(x, fn) (((DEV_CDB+x)<32)?(PCI_DEV(0,(DEV_CDB+x),fn)):(PCI_DEV((0-1),(DEV_CDB+x-32),fn))) - -void cf9_reset_prepare(void) -{ - u32 nodes; - u32 htic; - pci_devfn_t dev; - int i; - - nodes = ((pci_read_config32(PCI_DEV(0, DEV_CDB, 0), 0x60) >> 4) & 7) + 1; - for (i = 0; i < nodes; i++) { - dev = NODE_PCI(i, 0); - htic = pci_read_config32(dev, HT_INIT_CONTROL); - htic &= ~HTIC_BIOSR_Detect; - pci_write_config32(dev, HT_INIT_CONTROL, htic); - } -} - -void do_board_reset(void) -{ - system_reset(); -} diff --git a/src/southbridge/amd/cimx/sb900/sb_cimx.h b/src/southbridge/amd/cimx/sb900/sb_cimx.h deleted file mode 100644 index d13c79dc80..0000000000 --- a/src/southbridge/amd/cimx/sb900/sb_cimx.h +++ /dev/null @@ -1,45 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - - -#ifndef _CIMX_SB_EARLY_H_ -#define _CIMX_SB_EARLY_H_ - -#define PM_INDEX 0xcd6 -#define PM_DATA 0xcd7 - -#define SB900_ACPI_IO_BASE 0x800 - -#define ACPI_PM_EVT_BLK (SB900_ACPI_IO_BASE + 0x00) /* 4 bytes */ -#define ACPI_PM1_CNT_BLK (SB900_ACPI_IO_BASE + 0x04) /* 2 bytes */ -#define ACPI_PMA_CNT_BLK (SB900_ACPI_IO_BASE + 0x0F) /* 1 byte */ -#define ACPI_PM_TMR_BLK (SB900_ACPI_IO_BASE + 0x08) /* 4 bytes */ -#define ACPI_GPE0_BLK (SB900_ACPI_IO_BASE + 0x20) /* 8 bytes */ -#define ACPI_CPU_CONTROL (SB900_ACPI_IO_BASE + 0x10) /* 6 bytes */ - -#define REV_SB900_A11 0x11 -#define REV_SB900_A12 0x12 - -/** - * South Bridge CIMx romstage entry, sbPowerOnInit entry point wrapper. - */ -void sb_poweron_init(void); -void sb_before_pci_init(void); - -void sb_After_Pci_Init (void); -void sb_Mid_Post_Init (void); -void sb_Late_Post (void); - -#endif diff --git a/src/southbridge/amd/cimx/sb900/smbus.c b/src/southbridge/amd/cimx/sb900/smbus.c deleted file mode 100644 index 389aa8e12d..0000000000 --- a/src/southbridge/amd/cimx/sb900/smbus.c +++ /dev/null @@ -1,260 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - - -#include -#include "smbus.h" -#include /* printk */ - -static int smbus_wait_until_ready(u32 smbus_io_base) -{ - u32 loops; - - loops = SMBUS_TIMEOUT; - do { - u8 val; - val = inb(smbus_io_base + SMBHSTSTAT); - val &= 0x1f; - if (val == 0) { /* ready now */ - return 0; - } - outb(val, smbus_io_base + SMBHSTSTAT); - } while (--loops); - - return -2; /* time out */ -} - -static int smbus_wait_until_done(u32 smbus_io_base) -{ - u32 loops; - - loops = SMBUS_TIMEOUT; - do { - u8 val; - - val = inb(smbus_io_base + SMBHSTSTAT); - val &= 0x1f; /* mask off reserved bits */ - if (val & 0x1c) { - return -5; /* error */ - } - if (val == 0x02) { - outb(val, smbus_io_base + SMBHSTSTAT); /* clear status */ - return 0; - } - } while (--loops); - - return -3; /* timeout */ -} - -int do_smbus_recv_byte(u32 smbus_io_base, u32 device) -{ - u8 byte; - - if (smbus_wait_until_ready(smbus_io_base) < 0) { - printk(BIOS_INFO, "SB900 - Smbus.c - do_smbus_recv_byte - smbus no ready.\n"); - return -2; /* not ready */ - } - - printk(BIOS_INFO, "SB900 - Smbus.c - do_smbus_recv_byte - Start.\n"); - /* set the device I'm talking to */ - outb(((device & 0x7f) << 1) | 1, smbus_io_base + SMBHSTADDR); - - byte = inb(smbus_io_base + SMBHSTCTRL); - byte &= 0xe3; /* Clear [4:2] */ - byte |= (1 << 2) | (1 << 6); /* Byte data read/write command, start the command */ - outb(byte, smbus_io_base + SMBHSTCTRL); - - /* poll for transaction completion */ - if (smbus_wait_until_done(smbus_io_base) < 0) { - return -3; /* timeout or error */ - } - - /* read results of transaction */ - byte = inb(smbus_io_base + SMBHSTCMD); - - printk(BIOS_INFO, "SB900 - Smbus.c - do_smbus_recv_byte - End.\n"); - return byte; -} - -int do_smbus_send_byte(u32 smbus_io_base, u32 device, u8 val) -{ - u8 byte; - - if (smbus_wait_until_ready(smbus_io_base) < 0) { - printk(BIOS_INFO, "SB900 - Smbus.c - do_smbus_send_byte - smbus no ready.\n"); - return -2; /* not ready */ - } - - printk(BIOS_INFO, "SB900 - Smbus.c - do_smbus_send_byte - Start.\n"); - /* set the command... */ - outb(val, smbus_io_base + SMBHSTCMD); - - /* set the device I'm talking to */ - outb(((device & 0x7f) << 1) | 0, smbus_io_base + SMBHSTADDR); - - byte = inb(smbus_io_base + SMBHSTCTRL); - byte &= 0xe3; /* Clear [4:2] */ - byte |= (1 << 2) | (1 << 6); /* Byte data read/write command, start the command */ - outb(byte, smbus_io_base + SMBHSTCTRL); - - /* poll for transaction completion */ - if (smbus_wait_until_done(smbus_io_base) < 0) { - return -3; /* timeout or error */ - } - - printk(BIOS_INFO, "SB900 - Smbus.c - do_smbus_send_byte - End.\n"); - return 0; -} - -int do_smbus_read_byte(u32 smbus_io_base, u32 device, u32 address) -{ - u8 byte; - - if (smbus_wait_until_ready(smbus_io_base) < 0) { - printk(BIOS_INFO, "SB900 - Smbus.c - do_smbus_read_byte - smbus no ready.\n"); - return -2; /* not ready */ - } - - printk(BIOS_INFO, "SB900 - Smbus.c - do_smbus_read_byte - Start.\n"); - /* set the command/address... */ - outb(address & 0xff, smbus_io_base + SMBHSTCMD); - - /* set the device I'm talking to */ - outb(((device & 0x7f) << 1) | 1, smbus_io_base + SMBHSTADDR); - - byte = inb(smbus_io_base + SMBHSTCTRL); - byte &= 0xe3; /* Clear [4:2] */ - byte |= (1 << 3) | (1 << 6); /* Byte data read/write command, start the command */ - outb(byte, smbus_io_base + SMBHSTCTRL); - - /* poll for transaction completion */ - if (smbus_wait_until_done(smbus_io_base) < 0) { - return -3; /* timeout or error */ - } - - /* read results of transaction */ - byte = inb(smbus_io_base + SMBHSTDAT0); - - printk(BIOS_INFO, "SB900 - Smbus.c - do_smbus_read_byte - End.\n"); - return byte; -} - -int do_smbus_write_byte(u32 smbus_io_base, u32 device, u32 address, u8 val) -{ - u8 byte; - - if (smbus_wait_until_ready(smbus_io_base) < 0) { - printk(BIOS_INFO, "SB900 - Smbus.c - do_smbus_write_byte - smbus no ready.\n"); - return -2; /* not ready */ - } - - printk(BIOS_INFO, "SB900 - Smbus.c - do_smbus_write_byte - Start.\n"); - /* set the command/address... */ - outb(address & 0xff, smbus_io_base + SMBHSTCMD); - - /* set the device I'm talking to */ - outb(((device & 0x7f) << 1) | 0, smbus_io_base + SMBHSTADDR); - - /* output value */ - outb(val, smbus_io_base + SMBHSTDAT0); - - byte = inb(smbus_io_base + SMBHSTCTRL); - byte &= 0xe3; /* Clear [4:2] */ - byte |= (1 << 3) | (1 << 6); /* Byte data read/write command, start the command */ - outb(byte, smbus_io_base + SMBHSTCTRL); - - /* poll for transaction completion */ - if (smbus_wait_until_done(smbus_io_base) < 0) { - return -3; /* timeout or error */ - } - - printk(BIOS_INFO, "SB900 - Smbus.c - do_smbus_write_byte - End.\n"); - return 0; -} - -void alink_ab_indx(u32 reg_space, u32 reg_addr, u32 mask, u32 val) -{ - u32 tmp; - - printk(BIOS_INFO, "SB900 - Smbus.c - alink_ab_indx - Start.\n"); - outl((reg_space & 0x7) << 29 | reg_addr, AB_INDX); - tmp = inl(AB_DATA); - /* rpr 4.2 - * For certain revisions of the chip, the ABCFG registers, - * with an address of 0x100NN (where 'N' is any hexadecimal - * number), require an extra programming step.*/ - outl(0, AB_INDX); - - tmp &= ~mask; - tmp |= val; - - /* printk(BIOS_DEBUG, "about write %x, index=%x", tmp, (reg_space&0x3)<<29 | reg_addr); */ - outl((reg_space & 0x7) << 29 | reg_addr, AB_INDX); /* probably we don't have to do it again. */ - outl(tmp, AB_DATA); - outl(0, AB_INDX); - printk(BIOS_INFO, "SB900 - Smbus.c - alink_ab_indx - End.\n"); -} - -void alink_rc_indx(u32 reg_space, u32 reg_addr, u32 port, u32 mask, u32 val) -{ - u32 tmp; - - printk(BIOS_INFO, "SB900 - Smbus.c - alink_rc_indx - Start.\n"); - outl((reg_space & 0x7) << 29 | (port & 3) << 24 | reg_addr, AB_INDX); - tmp = inl(AB_DATA); - /* rpr 4.2 - * For certain revisions of the chip, the ABCFG registers, - * with an address of 0x100NN (where 'N' is any hexadecimal - * number), require an extra programming step.*/ - outl(0, AB_INDX); - - tmp &= ~mask; - tmp |= val; - - //printk(BIOS_DEBUG, "about write %x, index=%x", tmp, (reg_space&0x3)<<29 | (port&3) << 24 | reg_addr); - outl((reg_space & 0x7) << 29 | (port & 3) << 24 | reg_addr, AB_INDX); /* probably we don't have to do it again. */ - outl(tmp, AB_DATA); - outl(0, AB_INDX); - printk(BIOS_INFO, "SB900 - Smbus.c - alink_rc_indx - End.\n"); -} - -/* space = 0: AX_INDXC, AX_DATAC - * space = 1: AX_INDXP, AX_DATAP - */ -void alink_ax_indx(u32 space /*c or p? */, u32 axindc, u32 mask, u32 val) -{ - u32 tmp; - - printk(BIOS_INFO, "SB900 - Smbus.c - alink_ax_indx - Start.\n"); - /* read axindc to tmp */ - outl(space << 29 | space << 3 | 0x30, AB_INDX); - outl(axindc, AB_DATA); - outl(0, AB_INDX); - outl(space << 29 | space << 3 | 0x34, AB_INDX); - tmp = inl(AB_DATA); - outl(0, AB_INDX); - - tmp &= ~mask; - tmp |= val; - - /* write tmp */ - outl(space << 29 | space << 3 | 0x30, AB_INDX); - outl(axindc, AB_DATA); - outl(0, AB_INDX); - outl(space << 29 | space << 3 | 0x34, AB_INDX); - outl(tmp, AB_DATA); - outl(0, AB_INDX); - printk(BIOS_INFO, "SB900 - Smbus.c - alink_ax_indx - End.\n"); -} diff --git a/src/southbridge/amd/cimx/sb900/smbus.h b/src/southbridge/amd/cimx/sb900/smbus.h deleted file mode 100644 index 9fc698e90c..0000000000 --- a/src/southbridge/amd/cimx/sb900/smbus.h +++ /dev/null @@ -1,71 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef _SB900_SMBUS_H_ -#define _SB900_SMBUS_H_ - -#define SMBUS_IO_BASE SMBUS0_BASE_ADDRESS - -#define SMBHSTSTAT 0x0 -#define SMBSLVSTAT 0x1 -#define SMBHSTCTRL 0x2 -#define SMBHSTCMD 0x3 -#define SMBHSTADDR 0x4 -#define SMBHSTDAT0 0x5 -#define SMBHSTDAT1 0x6 -#define SMBHSTBLKDAT 0x7 - -#define SMBSLVCTRL 0x8 -#define SMBSLVCMD_SHADOW 0x9 -#define SMBSLVEVT 0xa -#define SMBSLVDAT 0xc - -#define AX_INDXC 0 -#define AX_INDXP 2 -#define AXCFG 4 -#define ABCFG 6 -#define RC_INDXC 1 -#define RC_INDXP 3 - -#define AB_INDX 0xCD8 -#define AB_DATA (AB_INDX+4) - -/* Between 1-10 seconds, We should never timeout normally - * Longer than this is just painful when a timeout condition occurs. - */ -#define SMBUS_TIMEOUT (100*1000*10) - -#define abcfg_reg(reg, mask, val) \ - alink_ab_indx((ABCFG), (reg), (mask), (val)) -#define axcfg_reg(reg, mask, val) \ - alink_ab_indx((AXCFG), (reg), (mask), (val)) -#define axindxc_reg(reg, mask, val) \ - alink_ax_indx((AX_INDXC), (reg), (mask), (val)) -#define axindxp_reg(reg, mask, val) \ - alink_ax_indx((AX_INDXP), (reg), (mask), (val)) -#define rcindxc_reg(reg, port, mask, val) \ - alink_rc_indx((RC_INDXC), (reg), (port), (mask), (val)) -#define rcindxp_reg(reg, port, mask, val) \ - alink_rc_indx((RC_INDXP), (reg), (port), (mask), (val)) - -int do_smbus_read_byte(u32 smbus_io_base, u32 device, u32 address); -int do_smbus_write_byte(u32 smbus_io_base, u32 device, u32 address, u8 val); -int do_smbus_recv_byte(u32 smbus_io_base, u32 device); -int do_smbus_send_byte(u32 smbus_io_base, u32 device, u8 val); -void alink_rc_indx(u32 reg_space, u32 reg_addr, u32 port, u32 mask, u32 val); -void alink_ab_indx(u32 reg_space, u32 reg_addr, u32 mask, u32 val); -void alink_ax_indx(u32 space /*c or p? */ , u32 axindc, u32 mask, u32 val); - -#endif diff --git a/src/southbridge/amd/cimx/sb900/smbus_spd.c b/src/southbridge/amd/cimx/sb900/smbus_spd.c deleted file mode 100644 index bd8b2f86c5..0000000000 --- a/src/southbridge/amd/cimx/sb900/smbus_spd.c +++ /dev/null @@ -1,177 +0,0 @@ -/***************************************************************************** - * - * Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ***************************************************************************/ - -#include -#include -#include - -#include - -#define SMBUS_BASE_ADDR 0xB00 - -STATIC -VOID -WritePmReg ( - IN UINT8 Reg, - IN UINT8 Data - ) -{ - __outbyte (0xCD6, Reg); - __outbyte (0xCD7, Data); -} -STATIC -VOID -SetupFch ( - IN UINT16 - IN IoBase - ) -{ - WritePmReg (0x2D, IoBase >> 8); - WritePmReg (0x2C, IoBase | 1); - WritePmReg (0x29, 0x80); - WritePmReg (0x28, 0x61); - /* set SMBus clock to 400 KHz */ - __outbyte (IoBase + 0x0E, 66000000 / 400000 / 4); -} - -/* - * - * ReadSmbusByteData - read a single SPD byte from any offset - * - */ - -STATIC -AGESA_STATUS -ReadSmbusByteData ( - IN UINT16 Iobase, - IN UINT8 Address, - OUT UINT8 *Buffer, - IN UINTN Offset - ) -{ - UINTN Status; - UINT64 Limit; - - Address |= 1; // set read bit - - __outbyte (Iobase + 0, 0xFF); // clear error status - __outbyte (Iobase + 1, 0x1F); // clear error status - __outbyte (Iobase + 3, Offset); // offset in eeprom - __outbyte (Iobase + 4, Address); // slave address and read bit - __outbyte (Iobase + 2, 0x48); // read byte command - - /* time limit to avoid hanging for unexpected error status (should never happen) */ - Limit = __rdtsc () + 2000000000 / 10; - for (;;) { - Status = __inbyte (Iobase); - if (__rdtsc () > Limit) break; - if ((Status & 2) == 0) continue; // SMBusInterrupt not set, keep waiting - if ((Status & 1) == 1) continue; // HostBusy set, keep waiting - break; - } - - Buffer [0] = __inbyte (Iobase + 5); - if (Status == 2) Status = 0; // check for done with no errors - return Status; - } - -/* - * - * ReadSmbusByte - read a single SPD byte from the default offset - * this function is faster function readSmbusByteData - * - */ - -STATIC -AGESA_STATUS -ReadSmbusByte ( - IN UINT16 Iobase, - IN UINT8 Address, - OUT UINT8 *Buffer - ) -{ - UINTN Status; - UINT64 Limit; - - __outbyte (Iobase + 0, 0xFF); // clear error status - __outbyte (Iobase + 2, 0x44); // read command - - // time limit to avoid hanging for unexpected error status - Limit = __rdtsc () + 2000000000 / 10; - for (;;) { - Status = __inbyte (Iobase); - if (__rdtsc () > Limit) break; - if ((Status & 2) == 0) continue; // SMBusInterrupt not set, keep waiting - if ((Status & 1) == 1) continue; // HostBusy set, keep waiting - break; - } - - Buffer [0] = __inbyte (Iobase + 5); - if (Status == 2) Status = 0; // check for done with no errors - return Status; -} - -/* - * - * ReadSpd - Read one or more SPD bytes from a DIMM. - * Start with offset zero and read sequentially. - * Optimization relies on autoincrement to avoid - * sending offset for every byte. - * Reads 128 bytes in 7-8 ms at 400 KHz. - * - */ - -STATIC -AGESA_STATUS -ReadSpd ( - IN UINT16 IoBase, - IN UINT8 SmbusSlaveAddress, - OUT UINT8 *Buffer, - IN UINTN Count - ) -{ - UINTN Index, Status; - - /* read the first byte using offset zero */ - Status = ReadSmbusByteData (IoBase, SmbusSlaveAddress, Buffer, 0); - if (Status) return Status; - - /* read the remaining bytes using auto-increment for speed */ - for (Index = 1; Index < Count; Index++){ - Status = ReadSmbusByte (IoBase, SmbusSlaveAddress, &Buffer [Index]); - if (Status) return Status; - } - return 0; -} - -int smbus_readSpd(int spdAddress, char *buf, size_t len) -{ - SetupFch (SMBUS_BASE_ADDR); - return ReadSpd (SMBUS_BASE_ADDR, spdAddress, (UINT8 *) buf, len); -} From a0e1e596f894416c9db9eefe5b742cb4fad23a00 Mon Sep 17 00:00:00 2001 From: Joe Moore Date: Mon, 21 Oct 2019 00:32:00 -0600 Subject: [PATCH 0266/1242] vc/amd/agesa: Remove fam12 With removal of Torpedo mainboard, this code is no longer necessary. Will resolve some unique Coverity issues. Change-Id: I2927245c426566a8f80863a109d015ebf6176803 Signed-off-by: Joe Moore Reviewed-on: https://review.coreboot.org/c/coreboot/+/36187 Tested-by: build bot (Jenkins) Reviewed-by: HAOUAS Elyes --- src/vendorcode/amd/agesa/Makefile.inc | 1 - src/vendorcode/amd/agesa/f12/AGESA.h | 3295 -- src/vendorcode/amd/agesa/f12/AMD.h | 486 - .../amd/agesa/f12/Config/OptionC6Install.h | 140 - .../amd/agesa/f12/Config/OptionCpbInstall.h | 144 - .../Config/OptionCpuCacheFlushOnHaltInstall.h | 117 - .../f12/Config/OptionCpuCoreLevelingInstall.h | 109 - .../f12/Config/OptionCpuFamiliesInstall.h | 357 - .../f12/Config/OptionCpuFeaturesInstall.h | 75 - .../amd/agesa/f12/Config/OptionDmiInstall.h | 206 - .../agesa/f12/Config/OptionFamily12hInstall.h | 694 - .../amd/agesa/f12/Config/OptionFchInstall.h | 928 - .../f12/Config/OptionGfxRecoveryInstall.h | 53 - .../amd/agesa/f12/Config/OptionGnbInstall.h | 592 - .../amd/agesa/f12/Config/OptionHtInstall.h | 304 - .../amd/agesa/f12/Config/OptionHwC1eInstall.h | 80 - .../amd/agesa/f12/Config/OptionIdsInstall.h | 407 - .../agesa/f12/Config/OptionIoCstateInstall.h | 132 - .../f12/Config/OptionL3FeaturesInstall.h | 104 - .../f12/Config/OptionLowPwrPstateInstall.h | 86 - .../agesa/f12/Config/OptionMemoryInstall.h | 4202 --- .../f12/Config/OptionMsgBasedC1eInstall.h | 116 - .../f12/Config/OptionMultiSocketInstall.h | 94 - .../f12/Config/OptionPreserveMailboxInstall.h | 122 - .../agesa/f12/Config/OptionPstateInstall.h | 254 - .../agesa/f12/Config/OptionS3ScriptInstall.h | 91 - .../amd/agesa/f12/Config/OptionSlitInstall.h | 79 - .../amd/agesa/f12/Config/OptionSratInstall.h | 73 - .../amd/agesa/f12/Config/OptionSwC1eInstall.h | 80 - .../amd/agesa/f12/Config/OptionWheaInstall.h | 74 - .../amd/agesa/f12/Config/PlatformInstall.h | 2586 -- src/vendorcode/amd/agesa/f12/Dispatcher.h | 51 - .../amd/agesa/f12/Include/AdvancedApi.h | 166 - .../amd/agesa/f12/Include/CommonReturns.h | 124 - .../amd/agesa/f12/Include/Filecode.h | 1076 - .../amd/agesa/f12/Include/GeneralServices.h | 201 - .../amd/agesa/f12/Include/GnbInterface.h | 99 - .../amd/agesa/f12/Include/GnbInterfaceStub.h | 249 - src/vendorcode/amd/agesa/f12/Include/Ids.h | 960 - src/vendorcode/amd/agesa/f12/Include/IdsHt.h | 123 - .../amd/agesa/f12/Include/OptionDmi.h | 89 - .../f12/Include/OptionFamily12hEarlySample.h | 138 - .../amd/agesa/f12/Include/OptionGfxRecovery.h | 81 - .../amd/agesa/f12/Include/OptionGnb.h | 105 - .../amd/agesa/f12/Include/OptionMemory.h | 351 - .../amd/agesa/f12/Include/OptionMultiSocket.h | 184 - .../amd/agesa/f12/Include/OptionPstate.h | 115 - .../amd/agesa/f12/Include/OptionSlit.h | 96 - .../amd/agesa/f12/Include/OptionSrat.h | 82 - .../amd/agesa/f12/Include/OptionWhea.h | 83 - .../amd/agesa/f12/Include/Options.h | 67 - .../amd/agesa/f12/Include/OptionsHt.h | 109 - .../amd/agesa/f12/Include/OptionsPage.h | 373 - .../f12/Include/PlatformMemoryConfiguration.h | 320 - .../amd/agesa/f12/Include/Topology.h | 162 - .../amd/agesa/f12/Legacy/Proc/Dispatcher.c | 135 - .../amd/agesa/f12/Legacy/Proc/Makefile.inc | 3 - .../amd/agesa/f12/Legacy/Proc/agesaCallouts.c | 420 - .../amd/agesa/f12/Legacy/Proc/hobTransfer.c | 392 - src/vendorcode/amd/agesa/f12/MainPage.h | 119 - src/vendorcode/amd/agesa/f12/Makefile.inc | 49 - .../f12/Proc/CPU/Family/0x12/F12C6State.c | 193 - .../agesa/f12/Proc/CPU/Family/0x12/F12Cpb.c | 171 - .../f12/Proc/CPU/Family/0x12/F12IoCstate.c | 278 - .../Family/0x12/F12MicrocodePatch03000002.c | 195 - .../Family/0x12/F12MicrocodePatch0300000e.c | 195 - .../Family/0x12/F12MicrocodePatch03000027.c | 195 - .../f12/Proc/CPU/Family/0x12/F12PackageType.h | 75 - .../Family/0x12/LN/F12LnEquivalenceTable.c | 113 - .../CPU/Family/0x12/LN/F12LnLogicalIdTables.c | 110 - .../0x12/LN/F12LnMicrocodePatchTables.c | 111 - .../f12/Proc/CPU/Family/0x12/LN/Makefile.inc | 3 - .../f12/Proc/CPU/Family/0x12/Makefile.inc | 23 - .../CPU/Family/0x12/cpuCommonF12Utilities.c | 572 - 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a/src/vendorcode/amd/agesa/Makefile.inc b/src/vendorcode/amd/agesa/Makefile.inc index da5900498c..b96af84d8c 100644 --- a/src/vendorcode/amd/agesa/Makefile.inc +++ b/src/vendorcode/amd/agesa/Makefile.inc @@ -1,4 +1,3 @@ -subdirs-$(CONFIG_CPU_AMD_AGESA_FAMILY12) += f12 subdirs-$(CONFIG_CPU_AMD_AGESA_FAMILY14) += f14 subdirs-$(CONFIG_CPU_AMD_AGESA_FAMILY15_TN) += f15tn subdirs-$(CONFIG_CPU_AMD_AGESA_FAMILY16_KB) += f16kb diff --git a/src/vendorcode/amd/agesa/f12/AGESA.h b/src/vendorcode/amd/agesa/f12/AGESA.h deleted file mode 100644 index 01a9c3f32c..0000000000 --- a/src/vendorcode/amd/agesa/f12/AGESA.h +++ /dev/null @@ -1,3295 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * Agesa structures and definitions - * - * Contains AMD AGESA core interface - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: Include - * @e \$Revision: 49979 $ @e \$Date: 2011-03-31 12:08:42 +0800 (Thu, 31 Mar 2011) $ - */ -/***************************************************************************** - * - * Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ***************************************************************************/ - - -#ifndef _AGESA_H_ -#define _AGESA_H_ - -#include "Porting.h" -#include "AMD.h" - -// -// -// AGESA Types and Definitions -// -// - -// AGESA BASIC CALLOUTS -#define AGESA_MEM_RELEASE 0x00028000 - -// AGESA ADVANCED CALLOUTS, Processor -#define AGESA_CHECK_UMA 0x00028100 -#define AGESA_DO_RESET 0x00028101 -#define AGESA_ALLOCATE_BUFFER 0x00028102 -#define AGESA_DEALLOCATE_BUFFER 0x00028103 -#define AGESA_LOCATE_BUFFER 0x00028104 -#define AGESA_RUNFUNC_ONAP 0x00028105 - -// AGESA ADVANCED CALLOUTS, HyperTransport - -// AGESA ADVANCED CALLOUTS, Memory -#define AGESA_READ_SPD 0x00028140 -#define AGESA_HOOKBEFORE_DRAM_INIT 0x00028141 -#define AGESA_HOOKBEFORE_DQS_TRAINING 0x00028142 -#define AGESA_READ_SPD_RECOVERY 0x00028143 -#define AGESA_HOOKBEFORE_EXIT_SELF_REF 0x00028144 -#define AGESA_HOOKBEFORE_DRAM_INIT_RECOVERY 0x00028145 - -// AGESA IDS CALLOUTS -#define AGESA_GET_IDS_INIT_DATA 0x00028200 - -// AGESA GNB CALLOUTS -#define AGESA_GNB_PCIE_SLOT_RESET 0x00028301 - -// AGESA FCH CALLOUTS -#define AGESA_FCH_OEM_CALLOUT 0x00028401 - -//------------------------------------------------------------------------ -// -// HyperTransport Interface - - - -//----------------------------------------------------------------------------- -// HT DEFINITIONS AND MACROS -// -//----------------------------------------------------------------------------- - - -// Width equates for call backs -#define HT_WIDTH_8_BITS 8 ///< Specifies 8 bit, or up to 8 bit widths. -#define HT_WIDTH_16_BITS 16 ///< Specifies 16 bit, or up to 16 bit widths. -#define HT_WIDTH_4_BITS 4 -#define HT_WIDTH_2_BITS 2 -#define HT_WIDTH_NO_LIMIT HT_WIDTH_16_BITS - -// Frequency Limit equates for call backs which take a frequency supported mask. -#define HT_FREQUENCY_LIMIT_200M 1 ///< Specifies a limit of no more than 200 MHz HT frequency. -#define HT_FREQUENCY_LIMIT_400M 7 ///< Specifies a limit of no more than 400 MHz HT frequency. -#define HT_FREQUENCY_LIMIT_600M 0x1F ///< Specifies a limit of no more than 600 MHz HT frequency. -#define HT_FREQUENCY_LIMIT_800M 0x3F ///< Specifies a limit of no more than 800 MHz HT frequency. -#define HT_FREQUENCY_LIMIT_1000M 0x7F ///< Specifies a limit of no more than 1000 MHz HT frequency. -#define HT_FREQUENCY_LIMIT_HT1_ONLY 0x7F ///< Specifies a limit of no more than 1000 MHz HT frequency. -#define HT_FREQUENCY_LIMIT_1200M 0xFF ///< Specifies a limit of no more than 1200 MHz HT frequency. -#define HT_FREQUENCY_LIMIT_1400M 0x1FF ///< Specifies a limit of no more than 1400 MHz HT frequency. -#define HT_FREQUENCY_LIMIT_1600M 0x3FF ///< Specifies a limit of no more than 1600 MHz HT frequency. -#define HT_FREQUENCY_LIMIT_1800M 0x7FF ///< Specifies a limit of no more than 1800 MHz HT frequency. -#define HT_FREQUENCY_LIMIT_2000M 0xFFF ///< Specifies a limit of no more than 2000 MHz HT frequency. -#define HT_FREQUENCY_LIMIT_2200M 0x1FFF ///< Specifies a limit of no more than 2200 MHz HT frequency. -#define HT_FREQUENCY_LIMIT_2400M 0x3FFF ///< Specifies a limit of no more than 2400 MHz HT frequency. -#define HT_FREQUENCY_LIMIT_2600M 0x7FFF ///< Specifies a limit of no more than 2600 MHz HT frequency. -#define HT_FREQUENCY_LIMIT_2800M 0x27FFF ///< Specifies a limit of no more than 2800 MHz HT frequency. -#define HT_FREQUENCY_LIMIT_3000M 0x67FFF ///< Specifies a limit of no more than 3000 MHz HT frequency. -#define HT_FREQUENCY_LIMIT_3200M 0xE7FFF ///< Specifies a limit of no more than 3200 MHz HT frequency. -#define HT_FREQUENCY_LIMIT_3600M 0x1E7FFF -#define HT_FREQUENCY_LIMIT_MAX HT_FREQUENCY_LIMIT_3600M -#define HT_FREQUENCY_NO_LIMIT 0xFFFFFFFF ///< Specifies a no limit of HT frequency. - -// Unit ID Clumping special values -#define HT_CLUMPING_DISABLE 0x00000000 -#define HT_CLUMPING_NO_LIMIT 0xFFFFFFFF - -#define HT_LIST_TERMINAL 0xFF ///< End of list. -#define HT_LIST_MATCH_ANY 0xFE ///< Match Any value, used for Sockets, Links, IO Chain Depth. -#define HT_LIST_MATCH_INTERNAL_LINK 0xFD ///< Match all of the internal links. - -// Event Notify definitions - -// Event definitions. - -// Coherent subfunction events -#define HT_EVENT_COH_EVENTS 0x10001000 -#define HT_EVENT_COH_NO_TOPOLOGY 0x10011000 ///< See ::HT_EVENT_DATA_COH_NO_TOPOLOGY. -#define HT_EVENT_COH_OBSOLETE000 0x10021000 // No longer used. -#define HT_EVENT_COH_PROCESSOR_TYPE_MIX 0x10031000 ///< See ::HT_EVENT_DATA_COH_PROCESSOR_TYPE_MIX. -#define HT_EVENT_COH_NODE_DISCOVERED 0x10041000 ///< See ::HT_EVENT_COH_NODE_DISCOVERED. -#define HT_EVENT_COH_MPCAP_MISMATCH 0x10051000 ///< See ::HT_EVENT_COH_MPCAP_MISMATCH. - -// Non-coherent subfunction events -#define HT_EVENT_NCOH_EVENTS 0x10002000 -#define HT_EVENT_NCOH_BUID_EXCEED 0x10012000 ///< See ::HT_EVENT_DATA_NCOH_BUID_EXCEED -#define HT_EVENT_NCOH_OBSOLETE000 0x10022000 // No longer used. -#define HT_EVENT_NCOH_BUS_MAX_EXCEED 0x10032000 ///< See ::HT_EVENT_DATA_NCOH_BUS_MAX_EXCEED. -#define HT_EVENT_NCOH_CFG_MAP_EXCEED 0x10042000 ///< See ::HT_EVENT_DATA_NCOH_CFG_MAP_EXCEED. -#define HT_EVENT_NCOH_DEVICE_FAILED 0x10052000 ///< See ::HT_EVENT_DATA_NCOH_DEVICE_FAILED -#define HT_EVENT_NCOH_AUTO_DEPTH 0x10062000 ///< See ::HT_EVENT_NCOH_AUTO_DEPTH - -// Optimization subfunction events -#define HT_EVENT_OPT_EVENTS 0x10003000 -#define HT_EVENT_OPT_REQUIRED_CAP_RETRY 0x10013000 ///< See ::HT_EVENT_DATA_OPT_REQUIRED_CAP. -#define HT_EVENT_OPT_REQUIRED_CAP_GEN3 0x10023000 ///< See ::HT_EVENT_DATA_OPT_REQUIRED_CAP. -#define HT_EVENT_OPT_UNUSED_LINKS 0x10033000 ///< See ::HT_EVENT_DATA_OPT_UNUSED_LINKS. -#define HT_EVENT_OPT_LINK_PAIR_EXCEED 0x10043000 ///< See ::HT_EVENT_DATA_OPT_LINK_PAIR_EXCEED. - -// HW Fault events -#define HT_EVENT_HW_EVENTS 0x10004000 -#define HT_EVENT_HW_SYNCFLOOD 0x10014000 ///< See ::HT_EVENT_DATA_HW_SYNCFLOOD. -#define HT_EVENT_HW_HTCRC 0x10024000 ///< See ::HT_EVENT_DATA_HW_HT_CRC. - -// The Recovery HT component uses 0x10005000 for events. -// For consistency, we avoid that range here. - -#define HT_MAX_NC_BUIDS 32 -//---------------------------------------------------------------------------- -// HT TYPEDEFS, STRUCTURES, ENUMS -// -//---------------------------------------------------------------------------- - -/// Specify the state redundant links are to be left in after match. -/// -/// After matching a link for IGNORE_LINK or SKIP_REGANG, the link may be left alone, -/// or powered off. - -typedef enum { - MATCHED, ///< The link matches the requested customization. - ///< When used with IGNORE_LINK, - ///< this will generally require other software to initialize the link. - ///< When used with SKIP_REGANG, - ///< the two unganged links will be available for distribution. - - POWERED_OFF, ///< Power the link off. Support may vary based on processor model. - ///< Power Off is only supported for coherent links. - ///< Link power off may occur at a warm reset rather than immediately. - ///< When used with SKIP_REGANG, the paired sublink is powered off, not the matching link. - - UNMATCHED, ///< The link should be processed according to normal defaults. - ///< Effectively, the link does not match the requested customization. - ///< This can be used to exclude links from a following match any. - - MaxFinalLinkState ///< Not a final link state, use for limit checking. -} FINAL_LINK_STATE; - -/// Swap a device from its current id to a new one. - -typedef struct { - IN UINT8 FromId; ///< The device responding to FromId, - IN UINT8 ToId; ///< will be moved to ToId. -} BUID_SWAP_ITEM; - - -/// Each Non-coherent chain may have a list of device swaps. After performing the swaps, -/// the final in order list of device ids is provided. (There can be more swaps than devices.) -/// The unused entries in both are filled with 0xFF. - -typedef struct { - IN BUID_SWAP_ITEM Swaps[HT_MAX_NC_BUIDS]; ///< The BUID Swaps to perform - IN UINT8 FinalIds[HT_MAX_NC_BUIDS]; ///< The ordered final BUIDs, resulting from the swaps -} BUID_SWAP_LIST; - - -/// Control Manual Initialization of Non-Coherent Chains -/// -/// This interface is checked every time a non-coherent chain is -/// processed. BUID assignment may be controlled explicitly on a -/// non-coherent chain. Provide a swap list. Swaps controls the -/// BUID assignment and FinalIds provides the device to device -/// Linking. Device orientation can be detected automatically, or -/// explicitly. See interface documentation for more details. -/// -/// If a manual swap list is not supplied, -/// automatic non-coherent init assigns BUIDs starting at 1 and incrementing sequentially -/// based on each device's unit count. - -typedef struct { - // Match fields - IN UINT8 Socket; ///< The Socket on which this chain is located - IN UINT8 Link; ///< The Link on the host for this chain - // Override fields - IN BUID_SWAP_LIST SwapList; ///< The swap list -} MANUAL_BUID_SWAP_LIST; - - -/// Override options for DEVICE_CAP_OVERRIDE. -/// -/// Specify which override actions should be performed. For Checks, 1 means to check the item -/// and 0 means to skip the check. For the override options, 1 means to apply the override and -/// 0 means to ignore the override. - -typedef struct { - IN UINT32 IsCheckDevVenId:1; ///< Check Match on Device/Vendor id - IN UINT32 IsCheckRevision:1; ///< Check Match on device Revision - IN UINT32 IsOverrideWidthIn:1; ///< Override Width In - IN UINT32 IsOverrideWidthOut:1; ///< Override Width Out - IN UINT32 IsOverrideFreq:1; ///< Override Frequency - IN UINT32 IsOverrideClumping:1; ///< Override Clumping - IN UINT32 IsDoCallout:1; ///< Make the optional callout -} DEVICE_CAP_OVERRIDE_OPTIONS; - -/// Override capabilities of a device. -/// -/// This interface is checked once for every Link on every IO device. -/// Provide the width and frequency capability if needed for this device. -/// This is used along with device capabilities, the limit interfaces, and northbridge -/// limits to compute the default settings. The components of the device's PCI config -/// address are provided, so its settings can be consulted if need be. -/// The optional callout is a catch all. - -typedef struct { - // Match fields - IN UINT8 HostSocket; ///< The Socket on which this chain is located. - IN UINT8 HostLink; ///< The Link on the host for this chain. - IN UINT8 Depth; ///< The Depth in the I/O chain from the Host. - IN UINT32 DevVenId; ///< The Device's PCI Vendor + Device ID (offset 0x00). - IN UINT8 Revision; ///< The Device's PCI Revision field (offset 0x08). - IN UINT8 Link; ///< The Device's Link number (0 or 1). - IN DEVICE_CAP_OVERRIDE_OPTIONS Options; ///< The options for this device override. - // Override fields - IN UINT8 LinkWidthIn; ///< modify to change the Link Width In. - IN UINT8 LinkWidthOut; ///< modify to change the Link Width Out. - IN UINT32 FreqCap; ///< modify to change the Link's frequency capability. - IN UINT32 Clumping; ///< modify to change Unit ID clumping support. - IN CALLOUT_ENTRY Callout; ///< optional call for really complex cases, or NULL. -} DEVICE_CAP_OVERRIDE; - -/// Callout param struct for override capabilities of a device. -/// -/// If the optional callout is implemented this param struct is passed to it. - -typedef struct { - IN AMD_CONFIG_PARAMS StdHeader; ///< Standard configuration header - // Match fields - IN UINT8 HostSocket; ///< The Socket on which this chain is located. - IN UINT8 HostLink; ///< The Link on the host for this chain. - IN UINT8 Depth; ///< The Depth in the I/O chain from the Host. - IN UINT32 DevVenId; ///< The Device's PCI Vendor + Device ID (offset 0x00). - IN UINT8 Revision; ///< The Device's PCI Revision field (offset 0x08). - IN UINT8 Link; ///< The Device's Link number (0 or 1). - IN PCI_ADDR PciAddress; ///< The Device's PCI Address. - // Override fields - OUT UINT8 *LinkWidthIn; ///< modify to change the Link Width In. - OUT UINT8 *LinkWidthOut; ///< modify to change the Link Width Out. - OUT UINT32 *FreqCap; ///< modify to change the Link's frequency capability. - OUT UINT32 *Clumping; ///< modify to change Unit ID clumping support. -} DEVICE_CAP_CALLOUT_PARAMS; - -/// Limits for CPU to CPU Links. -/// -/// For each coherent connection this interface is checked once. -/// Provide the frequency and width if needed for this Link (usually based on board -/// restriction). This is used with CPU device capabilities and northbridge limits -/// to compute the default settings. - -typedef struct { - // Match fields - IN UINT8 SocketA; ///< One Socket on which this Link is located - IN UINT8 LinkA; ///< The Link on this Node - IN UINT8 SocketB; ///< The other Socket on which this Link is located - IN UINT8 LinkB; ///< The Link on that Node - // Limit fields - IN UINT8 ABLinkWidthLimit; ///< modify to change the Link Width A->B - IN UINT8 BALinkWidthLimit; ///< modify to change the Link Width B-AHCI mode - SataAhci7804, ///< AHCI mode as 7804 ID (AMD driver) - SataIde2Ahci7804 ///< IDE->AHCI mode as 7804 ID (AMD driver) -} SATA_CLASS; - -/// Configuration values for BLDCFG_FCH_GPP_LINK_CONFIG -typedef enum { - PortA4 = 0, ///< 4:0:0:0 - PortA2B2 = 2, ///< 2:2:0:0 - PortA2B1C1 = 3, ///< 2:1:1:0 - PortA1B1C1D1 = 4 ///< 1:1:1:1 -} GPP_LINKMODE; - -/// Configuration values for FchPowerFail -typedef enum { - AlwaysOff = 0, ///< Always power off after power resumes - AlwaysOn = 1, ///< Always power on after power resumes - UsePrevious = 3, ///< Resume to same setting when power fails -} POWER_FAIL; - - -/// -/// FCH Component Data Structure in InitReset stage -/// -typedef struct { - IN BOOLEAN UmiGen2; ///< Enable Gen2 data rate of UMI - ///< @li FALSE - Disable Gen2 - ///< @li TRUE - Enable Gen2 - - IN BOOLEAN SataEnable; ///< SATA controller function - ///< @li FALSE - SATA controller is disabled - ///< @li TRUE - SATA controller is enabled - - IN BOOLEAN IdeEnable; ///< SATA IDE controller mode enabled/disabled - ///< @li FALSE - IDE controller is disabled - ///< @li TRUE - IDE controller is enabled - - IN BOOLEAN GppEnable; ///< Master switch of GPP function -} FCH_RESET_INTERFACE; - - -/// -/// FCH Component Data Structure from InitEnv stage -/// -typedef struct { - IN SD_MODE SdConfig; ///< Secure Digital (SD) controller mode - IN HDA_CONFIG AzaliaController; ///< Azalia HD Audio Controller - - IN IR_CONFIG IrConfig; ///< Infrared (IR) Configuration - IN BOOLEAN UmiGen2; ///< Enable Gen2 data rate of UMI - ///< @li FALSE - Disable Gen2 - ///< @li TRUE - Enable Gen2 - - IN SATA_CLASS SataClass; ///< SATA controller mode - IN BOOLEAN SataEnable; ///< SATA controller function - ///< @li FALSE - SATA controller is disabled - ///< @li TRUE - SATA controller is enabled - - IN BOOLEAN IdeEnable; ///< SATA IDE controller mode enabled/disabled - ///< @li FALSE - IDE controller is disabled - ///< @li TRUE - IDE controller is enabled - - IN BOOLEAN SataIdeMode; ///< Native mode of SATA IDE controller - ///< @li FALSE - Legacy IDE mode - ///< @li TRUE - Native IDE mode - - IN BOOLEAN Ohci1Enable; ///< OHCI controller #1 Function - ///< @li FALSE - OHCI1 is disabled - ///< @li TRUE - OHCI1 is enabled - - IN BOOLEAN Ohci2Enable; ///< OHCI controller #2 Function - ///< @li FALSE - OHCI2 is disabled - ///< @li TRUE - OHCI2 is enabled - - IN BOOLEAN Ohci3Enable; ///< OHCI controller #3 Function - ///< @li FALSE - OHCI3 is disabled - ///< @li TRUE - OHCI3 is enabled - - IN BOOLEAN Ohci4Enable; ///< OHCI controller #4 Function - ///< @li FALSE - OHCI4 is disabled - ///< @li TRUE - OHCI4 is enabled - - IN BOOLEAN XhciSwitch; ///< XHCI controller Function - ///< @li FALSE - XHCI is disabled - ///< @li TRUE - XHCI is enabled - - IN BOOLEAN GppEnable; ///< Master switch of GPP function - IN POWER_FAIL FchPowerFail; ///< FCH power failure option -} FCH_INTERFACE; - - -/*---------------------------------------------------------------------------- - * CPU Feature related info - *---------------------------------------------------------------------------- - */ - -/// Build Configuration values for BLDCFG_PLATFORM_C1E_MODE -typedef enum { - C1eModeDisabled = 0, ///< Disabled - C1eModeAuto = 1, ///< Auto mode enables the best C1e method for the - ///< currently installed processor - C1eModeHardware = 2, ///< Hardware method - C1eModeMsgBased = 3, ///< Message-based method - C1eModeSoftwareDeprecated = 4, ///< Deprecated software SMI method. - ///< Refer to "Addendum\Examples\C1eSMMHandler.asm" for - ///< example host BIOS SMM Handler implementation - C1eModeHardwareSoftwareDeprecated = 5, ///< Hardware or deprecated software SMI method - MaxC1eMode = 6 ///< Not a valid value, used for verifying input -} PLATFORM_C1E_MODES; - -/// Build Configuration values for BLDCFG_PLATFORM_CSTATE_MODE -typedef enum { - CStateModeDisabled = 0, ///< Disabled - CStateModeC6 = 1, ///< C6 State - MaxCStateMode = 2 ///< Not a valid value, used for verifying input -} PLATFORM_CSTATE_MODES; - -/// Build Configuration values for BLDCFG_PLATFORM_CPB_MODE -typedef enum { - CpbModeAuto = 0, ///< Auto - CpbModeDisabled = 1, ///< Disabled - MaxCpbMode = 2 ///< Not a valid value, used for verifying input -} PLATFORM_CPB_MODES; - -/*---------------------------------------------------------------------------- - * GNB PCIe configuration info - *---------------------------------------------------------------------------- - */ - -// Event definitions - - -#define GNB_EVENT_INVALID_CONFIGURATION 0x20010000 // User configuration invalid -#define GNB_EVENT_INVALID_PCIE_TOPOLOGY_CONFIGURATION 0x20010001 // Requested lane allocation for PCIe port can not be supported -#define GNB_EVENT_INVALID_PCIE_PORT_CONFIGURATION 0x20010002 // Requested incorrect PCIe port device address -#define GNB_EVENT_INVALID_DDI_LINK_CONFIGURATION 0x20010003 // Incorrect parameter in DDI link configuration -#define GNB_EVENT_INVALID_LINK_WIDTH_CONFIGURATION 0x20010004 // Invalid with for PCIe port or DDI link -#define GNB_EVENT_INVALID_LANES_CONFIGURATION 0x20010005 // Lane double subscribe lanes -#define GNB_EVENT_INVALID_DDI_TOPOLOGY_CONFIGURATION 0x20010006 // Requested lane allocation for DDI link(s) can not be supported -#define GNB_EVENT_LINK_TRAINING_FAIL 0x20020000 // PCIe Link training fail -#define GNB_EVENT_BROKEN_LANE_RECOVERY 0x20030000 // Broken lane workaround applied to recover link training -#define GNB_EVENT_GEN2_SUPPORT_RECOVERY 0x20040000 // Scale back to GEN1 to recover link training - - -#define DESCRIPTOR_TERMINATE_LIST 0x80000000ull - -/// PCIe port misc extended controls -typedef struct { - IN UINT8 LinkComplianceMode :1; ///< Force port into compliance mode (device will not be trained, port output compliance pattern) - IN UINT8 LinkSafeMode :2; /**< Safe mode PCIe capability. (Parameter may limit PCIe speed requested through PCIe_PORT_DATA::LinkSpeedCapability) - * @li @b 0 - port can advertize muximum supported capability - * @li @b 1 - port limit advertized capability and speed to PCIe Gen1 - */ - IN UINT8 SbLink :1; /**< PCIe link type - * @li @b 0 - General purpose port - * @li @b 1 - Port connected to SB - */ -} PCIe_PORT_MISC_CONTROL; - - -/// PCIe port configuration data -typedef struct { - IN UINT8 PortPresent; ///< Enable PCIe port for initialization. - IN UINT8 ChannelType; /**< Channel type. - * @li @b 0 - "lowLoss", - * @li @b 1 - "highLoss", - * @li @b 2 - "mob0db", - * @li @b 3 - "mob3db", - * @li @b 4 - "extnd6db" - * @li @b 5 - "extnd8db" - */ - IN UINT8 DeviceNumber; /**< PCI Device number for port. - * @li @b 0 - Native port device number - * @li @b N - Port device number (See available configurations @ref F12LaneConfigurations "Family 0x12", @ref F14LaneConfigurations "Family 0x14") - */ - IN UINT8 FunctionNumber; ///< Reserved for future use - IN UINT8 LinkSpeedCapability; /**< PCIe link speed/ - * @li @b 0 - Maximum supported by silicon - * @li @b 1 - Gen1 - * @li @b 2 - Gen2 - * @li @b 3 - Gen3 - */ - IN UINT8 LinkAspm; /**< ASPM control. (see AgesaPcieLinkAspm for additional option to control ASPM) - * @li @b 0 - Disabled - * @li @b 1 - L0s only - * @li @b 2 - L1 only - * @li @b 3 - L0s and L1 - */ - IN UINT8 LinkHotplug; /**< Hotplug control. - * @li @b 0 - Disabled - * @li @b 1 - Basic - * @li @b 2 - Server - * @li @b 3 - Enhanced - */ - IN UINT8 ResetId; /**< Arbitrary number greater than 0 assigned by platform firmware for GPIO - * identification which control reset for given port. - * Each port with unique GPIO should have unique ResetId assigned. - * All ports use same GPIO to control reset should have same ResetId assigned. - * see AgesaPcieSlotResetContol. - */ - IN PCIe_PORT_MISC_CONTROL MiscControls; ///< Misc extended controls -} PCIe_PORT_DATA; - -/// DDI channel lane mapping -typedef struct { ///< Structure that discribe lane mapping - IN UINT8 Lane0 :2; /**< Lane 0 mapping - * @li @b 0 - Map to lane 0 - * @li @b 1 - Map to lane 1 - * @li @b 2 - Map to lane 2 - * @li @b 2 - Map to lane 3 - */ - IN UINT8 Lane1 :2; ///< Lane 1 mapping (see "Lane 0 mapping") - IN UINT8 Lane2 :2; ///< Lane 2 mapping (see "Lane 0 mapping") - IN UINT8 Lane3 :2; ///< Lane 3 mapping (see "Lane 0 mapping") -} CHANNEL_MAPPING; ///< Lane mapping - -/// Common Channel Mapping -typedef union { - IN UINT8 ChannelMappingValue; ///< Raw lane mapping - IN CHANNEL_MAPPING ChannelMapping; ///< Channel mapping -} CONN_CHANNEL_MAPPING; - -/// DDI Configuration data -typedef struct { - IN UINT8 ConnectorType; /**< Display Connector Type - * @li @b 0 - DP - * @li @b 1 - eDP - * @li @b 2 - Single Link DVI-D - * @li @b 3 - Dual Link DVI-D (see @ref F12DualLinkDviDescription "Family 0x12 Dual Link DVI connector description") - * @li @b 4 - HDMI - * @li @b 5 - Travis DP-to-VGA - * @li @b 6 - Travis DP-to-LVDS - * @li @b 7 - Hudson-2 NutMeg DP-to-VGA - * @li @b 8 - Single Link DVI-I - * @li @b 9 - Native CRT (Family 0x14) - * @li @b 10 - Native LVDS (Family 0x14) - * @li @b 11 - Auto detect LCD panel connector type. VBIOS is able to auto detect the LVDS connector type: native LVDS, eDP or Travis-LVDS - * The auto detection method only support panel with EDID. - */ - IN UINT8 AuxIndex; /**< Indicates which AUX or DDC Line is used - * @li @b 0 - AUX1 - * @li @b 1 - AUX2 - * @li @b 2 - AUX3 - * @li @b 3 - AUX4 - * @li @b 4 - AUX5 - * @li @b 5 - AUX6 - */ - IN UINT8 HdpIndex; /**< Indicates which HDP pin is used - * @li @b 0 - HDP1 - * @li @b 1 - HDP2 - * @li @b 2 - HDP3 - * @li @b 3 - HDP4 - * @li @b 4 - HDP5 - * @li @b 5 - HDP6 - */ - IN CONN_CHANNEL_MAPPING Mapping[2]; /**< Set specific mapping of lanes to connector pins - * @li Mapping[0] define mapping for group of 4 lanes starting at PCIe_ENGINE_DATA.StartLane - * @li Mapping[1] define mapping for group of 4 lanes ending at PCIe_ENGINE_DATA.EndLane (only applicable for Dual DDI link) - * if Mapping[x] set to 0 than default mapping assumed - */ - IN UINT8 LanePnInversionMask; /**< Specifies whether to invert the state of P and N for each lane. Each bit represents a PCIe lane on the DDI port. - * @li 0 - Do not invert (default) - * @li 1 - Invert P and N on this lane - */ -} PCIe_DDI_DATA; - -/// Engine Configuration -typedef struct { - IN UINT8 EngineType; /**< Engine type - * @li @b 0 - Ignore engine configuration - * @li @b 1 - PCIe port - * @li @b 2 - DDI - */ - IN UINT16 StartLane; /**< Start Lane ID (in reversed configuration StartLane > EndLane) - * See lane description for @ref F12PcieLaneDescription "Family 0x12" - * @ref F14PcieLaneDescription "Family 0x14". - * See lane configurations for @ref F12LaneConfigurations "Family 0x12" - * @ref F14LaneConfigurations "Family 0x14". - */ - IN UINT16 EndLane; /**< End lane ID (in reversed configuration StartLane > EndLane) - * See lane description for @ref F12PcieLaneDescription "Family 0x12", - * @ref F14PcieLaneDescription "Family 0x14". - * See lane configurations for @ref F12LaneConfigurations "Family 0x12" - * @ref F14LaneConfigurations "Family 0x14". - */ - -} PCIe_ENGINE_DATA; - -/// PCIe port descriptor -typedef struct { - IN UINT32 Flags; /**< Descriptor flags - * @li @b Bit31 - last descriptor in complex - */ - IN PCIe_ENGINE_DATA EngineData; ///< Engine data - IN PCIe_PORT_DATA Port; ///< PCIe port specific configuration info -} PCIe_PORT_DESCRIPTOR; - -/// DDI descriptor -typedef struct { - IN UINT32 Flags; /**< Descriptor flags - * @li @b Bit31 - last descriptor in complex - */ - IN PCIe_ENGINE_DATA EngineData; ///< Engine data - IN PCIe_DDI_DATA Ddi; ///< DDI port specific configuration info -} PCIe_DDI_DESCRIPTOR; - -/// PCIe Complex descriptor -typedef struct { - IN UINT32 Flags; /**< Descriptor flags - * @li @b Bit31 - last descriptor in topology - */ - IN UINT32 SocketId; ///< Socket Id - IN CONST PCIe_PORT_DESCRIPTOR *PciePortList; ///< Pointer to array of PCIe port descriptors or NULL (Last element of array must be terminated with DESCRIPTOR_TERMINATE_LIST). - IN CONST PCIe_DDI_DESCRIPTOR *DdiLinkList; ///< Pointer to array DDI link descriptors (Last element of array must be terminated with DESCRIPTOR_TERMINATE_LIST). - IN VOID *Reserved; ///< Reserved for future use -} PCIe_COMPLEX_DESCRIPTOR; - -/// Action to control PCIe slot reset -typedef enum { - AssertSlotReset, ///< Assert slot reset - DeassertSlotReset ///< Deassert slot reset -} PCIE_RESET_CONTROL; - -///Slot Reset Info -typedef struct { - IN AMD_CONFIG_PARAMS StdHeader; ///< Standard configuration header - IN UINT8 ResetId; ///< Slot reset ID as specified in PCIe_PORT_DESCRIPTOR - IN UINT8 ResetControl; ///< Reset control as in PCIE_RESET_CONTROL -} PCIe_SLOT_RESET_INFO; - -/// Engine descriptor type -typedef enum { - PcieUnusedEngine = 0, ///< Unused descriptor - PciePortEngine = 1, ///< PCIe port - PcieDdiEngine = 2, ///< DDI - MaxPcieEngine ///< Max engine type for boundary check. -} PCIE_ENGINE_TYPE; - -/// PCIe link capability/speed -typedef enum { - PcieGenMaxSupported, ///< Maximum supported - PcieGen1 = 1, ///< Gen1 - PcieGen2, ///< Gen2 - MaxPcieGen ///< Max Gen for boundary check -} PCIE_LINK_SPEED_CAP; - -/// PCIe PSPP Power policy -typedef enum { - PsppDisabled, ///< PSPP disabled - PsppPerformance = 1, ///< Performance - PsppBalanceHigh, ///< Balance-High - PsppBalanceLow, ///< Balance-Low - PsppPowerSaving, ///< Power Saving - MaxPspp ///< Max Pspp for boundary check -} PCIE_PSPP_POLICY; - -/// DDI display connector type -typedef enum { - ConnectorTypeDP, ///< DP - ConnectorTypeEDP, ///< eDP - ConnectorTypeSingleLinkDVI, ///< Single Link DVI-D - ConnectorTypeDualLinkDVI, ///< Dual Link DVI-D - ConnectorTypeHDMI, ///< HDMI - ConnectorTypeTravisDpToVga, ///< Travis DP-to-VGA - ConnectorTypeTravisDpToLvds, ///< Travis DP-to-LVDS - ConnectorTypeNutmegDpToVga, ///< Hudson-2 NutMeg DP-to-VGA - ConnectorTypeSingleLinkDviI, ///< Single Link DVI-I - ConnectorTypeCrt, ///< CRT (VGA) - ConnectorTypeLvds, ///< LVDS - ConnectorTypeAutoDetect, ///< VBIOS auto detect connector type (native LVDS, eDP or Travis-LVDS) - MaxConnectorType ///< Not valid value, used to verify input -} PCIE_CONNECTOR_TYPE; - -/// PCIe link channel type -typedef enum { - ChannelTypeLowLoss, ///< Low Loss - ChannelTypeHighLoss, ///< High Loss - ChannelTypeMob0db, ///< Mobile 0dB - ChannelTypeMob3db, ///< Mobile 3dB - ChannelTypeExt6db, ///< Extended 6dB - ChannelTypeExt8db, ///< Extended 8dB - MaxChannelType ///< Not valid value, used to verify input -} PCIE_CHANNEL_TYPE; - -/// PCIe link ASPM -typedef enum { - AspmDisabled, ///< Disabled - AspmL0s, ///< PCIe L0s link state - AspmL1, ///< PCIe L1 link state - AspmL0sL1, ///< PCIe L0s & L1 link state - MaxAspm ///< Not valid value, used to verify input -} PCIE_ASPM_TYPE; - -/// PCIe link hotplug support -typedef enum { - HotplugDisabled, ///< Hotplug disable - HotplugBasic, ///< Basic Hotplug - HotplugServer, ///< Server Hotplug - HotplugEnhanced, ///< Enhanced - HotplugInboard, ///< Inboard - MaxHotplug ///< Not valid value, used to verify input -} PCIE_HOTPLUG_TYPE; - -/// PCIe link initialization -typedef enum { - PortDisabled, ///< Disable - PortEnabled ///< Enable -} PCIE_PORT_ENABLE; - -/// DDI Aux channel -typedef enum { - Aux1, ///< Aux1 - Aux2, ///< Aux2 - Aux3, ///< Aux3 - Aux4, ///< Aux4 - Aux5, ///< Aux5 - Aux6, ///< Aux6 - MaxAux ///< Not valid value, used to verify input -} PCIE_AUX_TYPE; - -/// DDI Hdp Index -typedef enum { - Hdp1, ///< Hdp1 - Hdp2, ///< Hdp2 - Hdp3, ///< Hdp3 - Hdp4, ///< Hdp4 - Hdp5, ///< Hdp5 - Hdp6, ///< Hdp6 - MaxHdp ///< Not valid value, used to verify input -} PCIE_HDP_TYPE; - -// Macro for statically initialization of various structures -#define PCIE_ENGINE_DATA_INITIALIZER(mType, mStartLane, mEndLane) {mType, mStartLane, mEndLane} -#define PCIE_PORT_DATA_INITIALIZER(mPortPresent, mChannelType, mDevAddress, mHotplug, mMaxLinkSpeed, mMaxLinkCap, mAspm, mResetId) \ -{mPortPresent, mChannelType, mDevAddress, 0, mMaxLinkSpeed, mAspm, mHotplug, mResetId, {0, mMaxLinkCap} } -#define PCIE_DDI_DATA_INITIALIZER(mConnectorType, mAuxIndex, mHpdIndex ) \ -{mConnectorType, mAuxIndex, mHpdIndex, {{0}, {0}}, 0} -#define PCIE_DDI_DATA_INITIALIZER_V1(mConnectorType, mAuxIndex, mHpdIndex, mMapping0, mMapping1, mPNInversion) \ -{mConnectorType, mAuxIndex, mHpdIndex, {mMapping0, mMapping1}, mPNInversion} - -///IOMMU requestor ID -typedef struct { - IN UINT16 Bus :8; ///< Bus - IN UINT16 Device :5; ///< Device - IN UINT16 Function :3; ///< Function -} IOMMU_REQUESTOR_ID; - -/// IVMD exclusion range descriptor -typedef struct { - IN UINT32 Flags; /**< Descriptor flags - * @li @b Flags[31] - Terminate descriptor array. - * @li @b Flags[30] - Ignore descriptor. - * @li @b Flags[0] - Range applies for all requestor IDs. - */ - IN IOMMU_REQUESTOR_ID RequestorId; ///< Requestor ID - IN UINT64 RangeBaseAddress; ///< Phisical base address of exclusion range - IN UINT64 RangeLength; ///< Length of exclusion range in bytes -} IOMMU_EXCLUSION_RANGE_DESCRIPTOR; - -/*---------------------------------------------------------------------------- - * GNB configuration info - *---------------------------------------------------------------------------- - */ -/// Configuration settings for GNB. -typedef struct { - IN UINT8 Gnb3dStereoPinIndex; ///< 3D Stereo Pin ID. - ///< @li 0 = Stereo 3D is disabled (default). - ///< @li 1 = Use processor pin HPD1. - ///< @li 2 = Use processor pin HPD2 - ///< @li 3 = Use processor pin HPD3 - ///< @li 4 = Use processor pin HPD4 - ///< @li 5 = Use processor pin HPD5 - ///< @li 6 = Use processor pin HPD6 - ///< @BldCfgItem{BLDCFG_STEREO_3D_PINOUT} - IN BOOLEAN IommuSupport; ///< IOMMU support. - ///< @li FALSE = Disabled. Disable and hide IOMMU device. - ///< @li TRUE = Initialize IOMMU subsystem. Generate ACPI IVRS table. - ///< BldCfgItem{BLDCFG_IOMMU_SUPPORT} - IN UINT16 LvdsSpreadSpectrum; ///< Spread spectrum value in 0.01 % - ///< BldCfgItem{BLDCFG_GFX_LVDS_SPREAD_SPECTRUM} - IN UINT16 LvdsSpreadSpectrumRate; ///< Spread spectrum frequency used by SS hardware logic in unit of 10Hz, 0 - default frequency 40kHz - ///< BldCfgItem{BLDCFG_GFX_LVDS_SPREAD_SPECTRUM_RATE} - IN UINT8 LvdsPowerOnSeqDigonToDe; ///< This item configures panel initialization timing. - ///< @BldCfgItem{BLDCFG_LVDS_POWER_ON_SEQ_DIGON_TO_DE} - IN UINT8 LvdsPowerOnSeqDeToVaryBl; ///< This item configures panel initialization timing. - ///< @BldCfgItem{BLDCFG_LVDS_POWER_ON_SEQ_DE_TO_VARY_BL} - IN UINT8 LvdsPowerOnSeqDeToDigon; ///< This item configures panel initialization timing. - ///< @BldCfgItem{BLDCFG_LVDS_POWER_ON_SEQ_DE_TO_DIGON} - IN UINT8 LvdsPowerOnSeqVaryBlToDe; ///< This item configures panel initialization timing. - ///< @BldCfgItem{BLDCFG_LVDS_POWERS_ON_SEQ_VARY_BL_TO_DE} - IN UINT8 LvdsPowerOnSeqOnToOffDelay; ///< This item configures panel initialization timing. - ///< @BldCfgItem{BLDCFG_LVDS_POWER_ON_SEQ_ON_TO_OFF_DELAY} - IN UINT8 LvdsPowerOnSeqVaryBlToBlon; ///< This item configures panel initialization timing. - ///< @BldCfgItem{BLDCFG_LVDS_POWER_ON_SEQ_VARY_BL_TO_BLON} - IN UINT8 LvdsPowerOnSeqBlonToVaryBl; ///< This item configures panel initialization timing. - ///< @BldCfgItem{BLDCFG_LVDS_POWER_ON_SEQ_BLON_TO_VARY_BL} - IN UINT16 LvdsMaxPixelClockFreq; ///< This item configures the maximum pixel clock frequency supported. - ///< @BldCfgItem{BLDCFG_LVDS_MAX_PIXEL_CLOCK_FREQ} - IN UINT32 LcdBitDepthControlValue; ///< This item configures the LCD bit depth control settings. - ///< @BldCfgItem{BLDCFG_LCD_BIT_DEPTH_CONTROL_VALUE} - IN UINT8 Lvds24bbpPanelMode; ///< This item configures the LVDS 24 BBP mode. - ///< @BldCfgItem{BLDCFG_LVDS_24BBP_PANEL_MODE} - IN UINT16 PcieRefClkSpreadSpectrum; ///< Spread spectrum value in 0.01 % - ///< @BldCfgItem{BLDCFG_PCIE_REFCLK_SPREAD_SPECTRUM} -} GNB_ENV_CONFIGURATION; - -/// GNB configuration info -typedef struct { - IN const PCIe_COMPLEX_DESCRIPTOR *PcieComplexList; /**< Pointer to array of structures describe PCIe topology on each processor package or NULL. - * Last element of array must be terminated with DESCRIPTOR_TERMINATE_LIST - * Example of topology definition for single socket system: - * @code - * PCIe_PORT_DESCRIPTOR PortList [] = { - * // Initialize Port descriptor (PCIe port, Lanes 8:15, PCI Device Number 2, ...) - * { - * 0, //Descriptor flags - * PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 8, 15), - * PCIE_PORT_DATA_INITIALIZER (PortEnabled, ChannelTypeExt6db, 2, HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, AspmDisabled, 0) - * }, - * // Initialize Port descriptor (PCIe port, Lanes 16:19, PCI Device Number 3, ...) - * { - * 0, //Descriptor flags - * PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 16, 19), - * PCIE_PORT_DATA_INITIALIZER (PortEnabled, ChannelTypeExt6db, 3, HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, AspmDisabled, 0) - * }, - * // Initialize Port descriptor (PCIe port, Lanes 4, PCI Device Number 4, ...) - * { - * DESCRIPTOR_TERMINATE_LIST, //Descriptor flags !!!IMPORTANT!!! Terminate last element of array - * PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 4, 4), - * PCIE_PORT_DATA_INITIALIZER (PortEnabled, ChannelTypeExt6db, 4, HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, AspmDisabled, 0) - * } - * }; - * PCIe_PORT_DESCRIPTOR DdiList [] = { - * // Initialize Ddi descriptor (DDI interface Lanes 24:27, Display Port Connector, ...) - * { - * 0, //Descriptor flags - * PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 24, 27), - * PCIE_DDI_DATA_INITIALIZER (ConnectorTypeDP, Aux1, Hdp1, 0) - * }, - * // Initialize Ddi descriptor (DDI interface Lanes 28:31, HDMI, ...) - * { - * DESCRIPTOR_TERMINATE_LIST, //Descriptor flags !!!IMPORTANT!!! Terminate last element of array - * PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 28, 31), - * PCIE_DDI_DATA_INITIALIZER (ConnectorTypeHDMI, Aux2, Hdp2, 0) - * } - * }; - * PCIe_COMPLEX_DESCRIPTOR PlatformTopology = { - * DESCRIPTOR_TERMINATE_LIST, //Descriptor flags !!!IMPORTANT!!! Terminate complexes list - * 0, //Socket ID - * &PortList[0], - * &DdiList[0], - * } - * @endcode - */ - IN UINT8 PsppPolicy; /**< PSPP (PCIe Speed Power Policy) - * @li @b 0 - Disabled - * @li @b 1 - Performance - * @li @b 2 - Balance-High - * @li @b 3 - Balance-Low - * @li @b 4 - Power Saving - */ - -} GNB_CONFIGURATION; -// -// MEMORY-SPECIFIC DATA STRUCTURES -// -// -// -// -// AGESA MAXIMIUM VALUES -// -// These Max values are used to define array sizes and associated loop -// counts in the code. They reflect the maximum values that AGESA -// currently supports and does not necessarily reflect the hardware -// capabilities of configuration. -// - -#define MAX_SOCKETS_SUPPORTED 8 ///< Max number of sockets in system -#define MAX_CHANNELS_PER_SOCKET 4 ///< Max Channels per sockets -#define MAX_DIMMS_PER_CHANNEL 4 ///< Max DIMMs on a memory channel (independent of platform) -#define NUMBER_OF_DELAY_TABLES 9 ///< Number of tables defined in CH_DEF_STRUCT. - ///< Eg: UINT16 *RcvEnDlys; - ///< UINT8 *WrDqsDlys; - ///< UINT8 *RdDqsDlys; - ///< UINT8 *WrDatDlys; - ///< UINT8 *RdDqsMinDlys; - ///< UINT8 *RdDqsMaxDlys; - ///< UINT8 *WrDatMinDlys; - ///< UINT8 *WrDatMaxDlys; -#define NUMBER_OF_FAILURE_MASK_TABLES 1 ///< Number of failure mask tables - -#define MAX_PLATFORM_TYPES 16 ///< Platform types per system - -#define MCT_TRNG_KEEPOUT_START 0x00004000 ///< base [39:8] -#define MCT_TRNG_KEEPOUT_END 0x00007FFF ///< base [39:8] - -#define UMA_ATTRIBUTE_INTERLEAVE 0x80000000 ///< Uma Region is interleaved -#define UMA_ATTRIBUTE_ON_DCT0 0x40000000 ///< UMA resides on memory that belongs to DCT0 -#define UMA_ATTRIBUTE_ON_DCT1 0x20000000 ///< UMA resides on memory that belongs to DCT1 - -typedef UINT8 PSO_TABLE; ///< Platform Configuration Table - -// AGESA DEFINITIONS -// -// Many of these are derived from the platform and hardware specific definitions - -/// EccSymbolSize override value -#define ECCSYMBOLSIZE_USE_BKDG 0 ///< Use BKDG Recommended Value -#define ECCSYMBOLSIZE_FORCE_X4 4 ///< Force to x4 -#define ECCSYMBOLSIZE_FORCE_X8 8 ///< Force to x8 -/// CPU Package Type -#define PT_L1 0 ///< L1 Package type -#define PT_M2 1 ///< AM Package type -#define PT_S1 2 ///< S1 Package type - -/// Structures use to pass system Logical CPU-ID -typedef struct { - IN OUT UINT64 Family; ///< Indicates logical ID Family - IN OUT UINT64 Revision; ///< Indicates logical ID Family -} CPU_LOGICAL_ID; - -/// Build Configuration values for BLDCFG_AMD_PLATFORM_TYPE -typedef enum { - AMD_PLATFORM_SERVER = 0x8000, ///< Server - AMD_PLATFORM_DESKTOP = 0x10000, ///< Desktop - AMD_PLATFORM_MOBILE = 0x20000, ///< Mobile -} AMD_PLATFORM_TYPE; - -/// Dram technology type -typedef enum { - DDR2_TECHNOLOGY, ///< DDR2 technology - DDR3_TECHNOLOGY ///< DDR3 technology -} TECHNOLOGY_TYPE; - -/// Build Configuration values for BLDCFG_MEMORY_BUS_FREQUENCY_LIMIT & BLDCFG_MEMORY_CLOCK_SELECT -typedef enum { - DDR400_FREQUENCY = 200, ///< DDR 400 - DDR533_FREQUENCY = 266, ///< DDR 533 - DDR667_FREQUENCY = 333, ///< DDR 667 - DDR800_FREQUENCY = 400, ///< DDR 800 - DDR1066_FREQUENCY = 533, ///< DDR 1066 - DDR1333_FREQUENCY = 667, ///< DDR 1333 - DDR1600_FREQUENCY = 800, ///< DDR 1600 - DDR1866_FREQUENCY = 933, ///< DDR 1866 - DDR2100_FREQUENCY = 1050, ///< DDR 2100 - DDR2133_FREQUENCY = 1066, ///< DDR 2133 - DDR2400_FREQUENCY = 1200, ///< DDR 2400 - UNSUPPORTED_DDR_FREQUENCY ///< Highest limit of DDR frequency -} MEMORY_BUS_SPEED; - -/// Build Configuration values for BLDCFG_MEMORY_QUADRANK_TYPE -typedef enum { - QUADRANK_REGISTERED, ///< Quadrank registered DIMM - QUADRANK_UNBUFFERED ///< Quadrank unbuffered DIMM -} QUANDRANK_TYPE; - -/// Build Configuration values for BLDCFG_TIMING_MODE_SELECT -typedef enum { - TIMING_MODE_AUTO, ///< Use best rate possible - TIMING_MODE_LIMITED, ///< Set user top limit - TIMING_MODE_SPECIFIC ///< Set user specified speed -} USER_MEMORY_TIMING_MODE; - -/// Build Configuration values for BLDCFG_POWER_DOWN_MODE -typedef enum { - POWER_DOWN_BY_CHANNEL, ///< Channel power down mode - POWER_DOWN_BY_CHIP_SELECT, ///< Chip select power down mode - POWER_DOWN_MODE_AUTO ///< AGESA to select power down mode -} POWER_DOWN_MODE; - -/// Low voltage support -typedef enum { - VOLT_INITIAL, ///< Initial value for VDDIO - VOLT1_5, ///< 1.5 Volt - VOLT1_35, ///< 1.35 Volt - VOLT1_25, ///< 1.25 Volt - VOLT_UNSUPPORTED = 0xFF ///< No common voltage found -} DIMM_VOLTAGE; - -/// UMA Mode -typedef enum { - UMA_NONE = 0, ///< UMA None - UMA_SPECIFIED = 1, ///< UMA Specified - UMA_AUTO = 2 ///< UMA Auto -} UMA_MODE; - -/// Build Configuration values for BLDCFG_UMA_ALIGNMENT -typedef enum { - NO_UMA_ALIGNED = 0x00FFFFFF, ///< NO UMA aligned - UMA_4MB_ALIGNED = 0x00FFFFC0, ///< UMA 4MB aligned - UMA_128MB_ALIGNED = 0x00FFF800, ///< UMA 128MB aligned - UMA_256MB_ALIGNED = 0x00FFF000, ///< UMA 256MB aligned - UMA_512MB_ALIGNED = 0x00FFE000, ///< UMA 512MB aligned -} UMA_ALIGNMENT; - -/// -/// Global MCT Configuration Status Word (GStatus) -/// -typedef enum { - GsbMTRRshort, ///< Ran out of MTRRs while mapping memory - GsbAllECCDimms, ///< All banks of all Nodes are ECC capable - GsbDramECCDis, ///< Dram ECC requested but not enabled. - GsbSoftHole, ///< A Node Base gap was created - GsbHWHole, ///< A HW dram remap was created - GsbNodeIntlv, ///< Node Memory interleaving was enabled - GsbSpIntRemapHole, ///< Special condition for Node Interleave and HW remapping - GsbEnDIMMSpareNW, ///< Indicates that DIMM Spare can be used without a warm reset - - GsbEOL ///< End of list -} GLOBAL_STATUS_FIELD; - -/// -/// Local Error Status (DIE_STRUCT.ErrStatus[31:0]) -/// -typedef enum { - EsbNoDimms, ///< No DIMMs - EsbSpdChkSum, ///< SPD Checksum fail - EsbDimmMismatchM, ///< dimm module type(buffer) mismatch - EsbDimmMismatchT, ///< dimm CL/T mismatch - EsbDimmMismatchO, ///< dimm organization mismatch (128-bit) - EsbNoTrcTrfc, ///< SPD missing Trc or Trfc info - EsbNoCycTime, ///< SPD missing byte 23 or 25 - EsbBkIntDis, ///< Bank interleave requested but not enabled - EsbDramECCDis, ///< Dram ECC requested but not enabled - EsbSpareDis, ///< Online spare requested but not enabled - EsbMinimumMode, ///< Running in Minimum Mode - EsbNoRcvrEn, ///< No DQS Receiver Enable pass window found - EsbSmallRcvr, ///< DQS Rcvr En pass window too small (far right of dynamic range) - EsbNoDqsPos, ///< No DQS-DQ passing positions - EsbSmallDqs, ///< DQS-DQ passing window too small - EsbDCBKScrubDis, ///< DCache scrub requested but not enabled - - EsbEMPNotSupported, ///< Processor is not capable for EMP. - EsbEMPConflict, ///< EMP requested but cannot be enabled since - ///< channel interleaving, bank interleaving, or bank swizzle is enabled. - EsbEMPDis, ///< EMP requested but cannot be enabled since - ///< memory size of each DCT is not a power of two. - - EsbEOL ///< End of list -} ERROR_STATUS_FIELD; - -/// -/// Local Configuration Status (DIE_STRUCT.Status[31:0]) -/// -typedef enum { - SbRegistered, ///< All DIMMs are Registered - SbEccDimms, ///< All banks ECC capable - SbParDimms, ///< All banks Addr/CMD Parity capable - SbDiagClks, ///< Jedec ALL slots clock enable diag mode - Sb128bitmode, ///< DCT in 128-bit mode operation - Sb64MuxedMode, ///< DCT in 64-bit mux'ed mode. - Sb2TMode, ///< 2T CMD timing mode is enabled. - SbSWNodeHole, ///< Remapping of Node Base on this Node to create a gap. - SbHWHole, ///< Memory Hole created on this Node using HW remapping. - SbOver400Mhz, ///< DCT freq greater than or equal to 400MHz flag - SbDQSPosPass2, ///< Used for TrainDQSPos DIMM0/1, when freq greater than or equal to 400MHz - SbDQSRcvLimit, ///< Used for DQSRcvEnTrain to know we have reached the upper bound. - SbExtConfig, ///< Indicate the default setting for extended PCI configuration support - SbLrdimms, ///< All DIMMs are LRDIMMs - - SbEOL ///< End of list -} LOCAL_STATUS_FIELD; - - -///< CPU MSR Register definitions ------------------------------------------ -#define SYS_CFG 0xC0010010 -#define TOP_MEM 0xC001001Aul -#define TOP_MEM2 0xC001001Dul -#define HWCR 0xC0010015 -#define NB_CFG 0xC001001F - -#define FS_BASE 0xC0000100 -#define IORR0_BASE 0xC0010016 -#define IORR0_MASK 0xC0010017 -#define BU_CFG 0xC0011023 -#define BU_CFG2 0xC001102A -#define COFVID_STAT 0xC0010071 -#define TSC 0x10 - -//----------------------------------------------------------------------------- -/// -/// SPD Data for each DIMM. -/// -typedef struct _SPD_DEF_STRUCT { - IN BOOLEAN DimmPresent; ///< Indicates that the DIMM is present and Data is valid - IN UINT8 Data[256]; ///< Buffer for 256 Bytes of SPD data from DIMM -} SPD_DEF_STRUCT; - -/// -/// Channel Definition Structure. -/// This data structure defines entries that are specific to the channel initialization -/// -typedef struct _CH_DEF_STRUCT { - OUT UINT8 ChannelID; ///< Physical channel ID of a socket(0 = CH A, 1 = CH B, 2 = CH C, 3 = CH D) - OUT TECHNOLOGY_TYPE TechType; ///< Technology type of this channel - OUT UINT8 ChDimmPresent; ///< For each bit n 0..7, 1 = DIMM n is present. - ///< DIMM# Select Signal - ///< 0 MA0_CS_L[0, 1] - ///< 1 MB0_CS_L[0, 1] - ///< 2 MA1_CS_L[0, 1] - ///< 3 MB1_CS_L[0, 1] - ///< 4 MA2_CS_L[0, 1] - ///< 5 MB2_CS_L[0, 1] - ///< 6 MA3_CS_L[0, 1] - ///< 7 MB3_CS_L[0, 1] - - OUT struct _DCT_STRUCT *DCTPtr; ///< Pointer to the DCT data of this channel. - OUT struct _DIE_STRUCT *MCTPtr; ///< Pointer to the node data of this channel. - OUT SPD_DEF_STRUCT *SpdPtr; ///< Pointer to the SPD data for this channel. (Setup by NB Constructor) - OUT SPD_DEF_STRUCT *DimmSpdPtr[MAX_DIMMS_PER_CHANNEL]; ///< Array of pointers to - ///< SPD Data for each Dimm. (Setup by Tech Block Constructor) - OUT UINT8 ChDimmValid; ///< For each bit n 0..3, 1 = DIMM n is valid and is/will be configured where 4..7 are reserved. - ///< - OUT UINT8 RegDimmPresent; ///< For each bit n 0..3, 1 = DIMM n is a registered DIMM where 4..7 are reserved. - OUT UINT8 LrDimmPresent; ///< For each bit n 0..3, 1 = DIMM n is Load Reduced DIMM where 4..7 are reserved. - OUT UINT8 SODimmPresent; ///< For each bit n 0..3, 1 = DIMM n is a SO-DIMM, where 4..7 are reserved. - OUT UINT8 Loads; ///< Number of devices loading bus - OUT UINT8 Dimms; ///< Number of DIMMs loading Channel - OUT UINT8 Ranks; ///< Number of ranks loading Channel DATA - OUT BOOLEAN SlowMode; ///< 1T or 2T CMD mode (slow access mode) - ///< FALSE = 1T - ///< TRUE = 2T - ///< The following pointers will be pointed to dynamically allocated buffers. - ///< Each buffer is two dimensional (RowCount x ColumnCount) and is lay-outed as in below. - ///< Example: If DIMM and Byte based training, then - ///< XX is a value in Hex - ///< BYTE 0, BYTE 1, BYTE 2, BYTE 3, BYTE 4, BYTE 5, BYTE 6, BYTE 7, ECC BYTE - ///< Row1 - Logical DIMM0 XX XX XX XX XX XX XX XX XX - ///< Row2 - Logical DIMM1 XX XX XX XX XX XX XX XX XX - OUT UINT16 *RcvEnDlys; ///< DQS Receiver Enable Delays - OUT UINT8 *WrDqsDlys; ///< Write DQS delays (only valid for DDR3) - OUT UINT8 *RdDqsDlys; ///< Read Dqs delays - OUT UINT8 *WrDatDlys; ///< Write Data delays - OUT UINT8 *RdDqsMinDlys; ///< Minimum Window for Read DQS - OUT UINT8 *RdDqsMaxDlys; ///< Maximum Window for Read DQS - OUT UINT8 *WrDatMinDlys; ///< Minimum Window for Write data - OUT UINT8 *WrDatMaxDlys; ///< Maximum Window for Write data - OUT UINT8 RowCount; ///< Number of rows of the allocated buffer. - OUT UINT8 ColumnCount; ///< Number of columns of the allocated buffer. - OUT UINT8 *FailingBitMask; ///< Table of masks to Track Failing bits - OUT UINT32 DctOdcCtl; ///< Output Driver Strength (see BKDG FN2:Offset 9Ch, index 00h) - OUT UINT32 DctAddrTmg; ///< Address Bus Timing (see BKDG FN2:Offset 9Ch, index 04h) - OUT UINT32 PhyRODTCSLow; ///< Phy Read ODT Pattern Chip Select low (see BKDG FN2:Offset 9Ch, index 180h) - OUT UINT32 PhyRODTCSHigh; ///< Phy Read ODT Pattern Chip Select high (see BKDG FN2:Offset 9Ch, index 181h) - OUT UINT32 PhyWODTCSLow; ///< Phy Write ODT Pattern Chip Select low (see BKDG FN2:Offset 9Ch, index 182h) - OUT UINT32 PhyWODTCSHigh; ///< Phy Write ODT Pattern Chip Select high (see BKDG FN2:Offset 9Ch, index 183) - OUT UINT8 PhyWLODT[4]; ///< Write Levelization ODT Pattern for Dimm 0-3 (see BKDG FN2:Offset 9Ch, index 0x8[11:8]) - OUT UINT16 DctEccDqsLike; ///< DCT DQS ECC UINT8 like... - OUT UINT8 DctEccDqsScale; ///< DCT DQS ECC UINT8 scale - OUT UINT16 PtrPatternBufA; ///< Ptr on stack to aligned DQS testing pattern - OUT UINT16 PtrPatternBufB; ///< Ptr on stack to aligned DQS testing pattern - OUT UINT8 ByteLane; ///< Current UINT8 Lane (0..7) - OUT UINT8 Direction; ///< Current DQS-DQ training write direction (0=read, 1=write) - OUT UINT8 Pattern; ///< Current pattern - OUT UINT8 DqsDelay; ///< Current DQS delay value - OUT UINT16 HostBiosSrvc1; ///< UINT16 sized general purpose field for use by host BIOS. Scratch space. - OUT UINT32 HostBiosSrvc2; ///< UINT32 sized general purpose field for use by host BIOS. Scratch space. - OUT UINT16 DctMaxRdLat; ///< Max Read Latency (ns) for the DCT - OUT UINT8 DIMMValidCh; ///< DIMM# in CH - OUT UINT8 MaxCh; ///< Max number of CH in system - OUT UINT8 Dct; ///< Dct pointer - OUT UINT8 WrDatGrossH; ///< Write Data Gross delay high value - OUT UINT8 DqsRcvEnGrossL; ///< DQS Receive Enable Gross Delay low - - OUT UINT8 TrwtWB; ///< Non-SPD timing value for TrwtWB - OUT UINT8 CurrRcvrDctADelay; ///< for keep current RcvrEnDly - OUT UINT16 T1000; ///< get the T1000 figure (cycle time (ns) * 1K) - OUT UINT8 DqsRcvEnPass; ///< for TrainRcvrEn UINT8 lane pass flag - OUT UINT8 DqsRcvEnSaved; ///< for TrainRcvrEn UINT8 lane saved flag - OUT UINT8 SeedPass1Remainder; ///< for Phy assisted DQS receiver enable training - - OUT UINT8 ClToNbFlag; ///< is used to restore ClLinesToNbDis bit after memory - OUT UINT32 NodeSysBase; ///< for channel interleave usage - OUT UINT8 RefRawCard[MAX_DIMMS_PER_CHANNEL]; ///< Array of rawcards detected - OUT UINT8 CtrlWrd02[MAX_DIMMS_PER_CHANNEL]; ///< Control Word 2 values per DIMM - OUT UINT8 CtrlWrd03[MAX_DIMMS_PER_CHANNEL]; ///< Control Word 3 values per DIMM - OUT UINT8 CtrlWrd04[MAX_DIMMS_PER_CHANNEL]; ///< Control Word 4 values per DIMM - OUT UINT8 CtrlWrd05[MAX_DIMMS_PER_CHANNEL]; ///< Control Word 5 values per DIMM - OUT UINT8 CtrlWrd08[MAX_DIMMS_PER_CHANNEL]; ///< Control Word 8 values per DIMM - - OUT UINT16 CsPresentDCT; ///< For each bit n 0..7, 1 = Chip-select n is present - OUT UINT8 DimmMirrorPresent; ///< For each bit n 0..3, 1 = DIMM n is OnDimmMirror capable where 4..7 are reserved. - OUT UINT8 DimmSpdCse; ///< For each bit n 0..3, 1 = DIMM n SPD checksum error where 4..7 are reserved. - OUT UINT8 DimmExclude; ///< For each bit n 0..3, 1 = DIMM n gets excluded where 4..7 are reserved. - OUT UINT8 DimmYr06; ///< Bitmap indicating which Dimms have a manufacturer's year code <= 2006 - OUT UINT8 DimmWk2406; ///< Bitmap indicating which Dimms have a manufacturer's week code <= 24 of 2006 (June) - OUT UINT8 DimmPlPresent; ///< Bitmap indicating that Planar (1) or Stacked (0) Dimms are present. - OUT UINT8 DimmQrPresent; ///< QuadRank DIMM present? - OUT UINT8 DimmDrPresent; ///< Bitmap indicating that Dual Rank Dimms are present - OUT UINT8 DimmSRPresent; ///< Bitmap indicating that Single Rank Dimms are present - OUT UINT8 Dimmx4Present; ///< For each bit n 0..3, 1 = DIMM n contains x4 data devices. where 4..7 are reserved. - OUT UINT8 Dimmx8Present; ///< For each bit n 0..3, 1 = DIMM n contains x8 data devices. where 4..7 are reserved. - OUT UINT8 Dimmx16Present; ///< For each bit n 0..3, 1 = DIMM n contains x16 data devices. where 4..7 are reserved. - OUT UINT8 LrdimmPhysicalRanks[MAX_DIMMS_PER_CHANNEL];///< Number of Physical Ranks for LRDIMMs - OUT UINT8 LrDimmLogicalRanks[MAX_DIMMS_PER_CHANNEL];///< Number of LRDIMM Logical ranks in this configuration - OUT UINT8 LrDimmRankMult[MAX_DIMMS_PER_CHANNEL];///< Rank Multipication factor per dimm. - - OUT UINT8 *MemClkDisMap; ///< This pointer will be set to point to an array that describes - ///< the routing of M[B,A]_CLK pins to the DIMMs' ranks. AGESA will - ///< base on this array to disable unused MemClk to save power. - ///< - ///< The array must have 8 entries. Each entry, which associates with - ///< one MemClkDis bit, is a bitmap of 8 CS that that MemClk is routed to. - ///< Example: - ///< BKDG definition of Fn2x88[MemClkDis] bitmap for AM3 package - ///< is like below: - ///< Bit AM3/S1g3 pin name - ///< 0 M[B,A]_CLK_H/L[0] - ///< 1 M[B,A]_CLK_H/L[1] - ///< 2 M[B,A]_CLK_H/L[2] - ///< 3 M[B,A]_CLK_H/L[3] - ///< 4 M[B,A]_CLK_H/L[4] - ///< 5 M[B,A]_CLK_H/L[5] - ///< 6 M[B,A]_CLK_H/L[6] - ///< 7 M[B,A]_CLK_H/L[7] - ///< And platform has the following routing: - ///< CS0 M[B,A]_CLK_H/L[4] - ///< CS1 M[B,A]_CLK_H/L[2] - ///< CS2 M[B,A]_CLK_H/L[3] - ///< CS3 M[B,A]_CLK_H/L[5] - ///< Then MemClkDisMap should be pointed to the following array: - ///< CLK_2 CLK_3 CLK_4 CLK_5 - ///< 0x00, 0x00, 0x02, 0x04, 0x01, 0x08, 0x00, 0x00 - ///< Each entry of the array is the bitmask of 8 chip selects. - - OUT UINT8 *CKETriMap; ///< This pointer will be set to point to an array that describes - ///< the routing of CKE pins to the DIMMs' ranks. - ///< The array must have 2 entries. Each entry, which associates with - ///< one CKE pin, is a bitmap of 8 CS that that CKE is routed to. - ///< AGESA will base on this array to disable unused CKE pins to save power. - - OUT UINT8 *ODTTriMap; ///< This pointer will be set to point to an array that describes - ///< the routing of ODT pins to the DIMMs' ranks. - ///< The array must have 4 entries. Each entry, which associates with - ///< one ODT pin, is a bitmap of 8 CS that that ODT is routed to. - ///< AGESA will base on this array to disable unused ODT pins to save power. - - OUT UINT8 *ChipSelTriMap; ///< This pointer will be set to point to an array that describes - ///< the routing of chip select pins to the DIMMs' ranks. - ///< The array must have 8 entries. Each entry is a bitmap of 8 CS. - ///< AGESA will base on this array to disable unused Chip select pins to save power. - - OUT BOOLEAN ExtendTmp; ///< If extended temperature is supported on all dimms on a channel. - - OUT UINT8 Reserved[100]; ///< Reserved -} CH_DEF_STRUCT; - -/// -/// DCT Channel Timing Parameters. -/// This data structure sets timings that are specific to the channel. -/// -typedef struct _CH_TIMING_STRUCT { - OUT UINT16 DctDimmValid; ///< For each bit n 0..3, 1=DIMM n is valid and is/will be configured where 4..7 are reserved. - OUT UINT16 DimmMirrorPresent; ///< For each bit n 0..3, 1=DIMM n is OnDimmMirror capable where 4..7 are reserved. - OUT UINT16 DimmSpdCse; ///< For each bit n 0..3, 1=DIMM n SPD checksum error where 4..7 are reserved. - OUT UINT16 DimmExclude; ///< For each bit n 0..3, 1 = DIMM n gets excluded where 4..7 are reserved. - OUT UINT16 CsPresent; ///< For each bit n 0..7, 1=Chip-select n is present - OUT UINT16 CsEnabled; ///< For each bit n 0..7, 1=Chip-select n is enabled - OUT UINT16 CsTestFail; ///< For each bit n 0..7, 1=Chip-select n is present but disabled - OUT UINT16 CsTrainFail; ///< Bitmap showing which chipselects failed training - OUT UINT16 DIMM1KPage; ///< For each bit n 0..3, 1=DIMM n contains 1K page devices. where 4..7 are reserved - OUT UINT16 DimmQrPresent; ///< QuadRank DIMM present? - OUT UINT16 DimmDrPresent; ///< Bitmap indicating that Dual Rank Dimms are present , where 4..7 are reserved - OUT UINT8 DimmSRPresent; ///< Bitmap indicating that Single Rank Dimms are present, where 4..7 are reserved - OUT UINT16 Dimmx4Present; ///< For each bit n 0..3, 1=DIMM n contains x4 data devices. where 4..7 are reserved - OUT UINT16 Dimmx8Present; ///< For each bit n 0..3, 1=DIMM n contains x8 data devices. where 4..7 are reserved - OUT UINT16 Dimmx16Present; ///< For each bit n 0..3, 1=DIMM n contains x16 data devices. where 4..7 are reserved - - OUT UINT16 DIMMTrcd; ///< Minimax Trcd*40 (ns) of DIMMs - OUT UINT16 DIMMTrp; ///< Minimax Trp*40 (ns) of DIMMs - OUT UINT16 DIMMTrtp; ///< Minimax Trtp*40 (ns) of DIMMs - OUT UINT16 DIMMTras; ///< Minimax Tras*40 (ns) of DIMMs - OUT UINT16 DIMMTrc; ///< Minimax Trc*40 (ns) of DIMMs - OUT UINT16 DIMMTwr; ///< Minimax Twr*40 (ns) of DIMMs - OUT UINT16 DIMMTrrd; ///< Minimax Trrd*40 (ns) of DIMMs - OUT UINT16 DIMMTwtr; ///< Minimax Twtr*40 (ns) of DIMMs - OUT UINT16 DIMMTfaw; ///< Minimax Tfaw*40 (ns) of DIMMs - OUT UINT16 TargetSpeed; ///< Target DRAM bus speed in MHz - OUT UINT16 Speed; ///< DRAM bus speed in MHz - ///< 400 (MHz) - ///< 533 (MHz) - ///< 667 (MHz) - ///< 800 (MHz) - ///< and so on... - OUT UINT8 CasL; ///< CAS latency DCT setting (busclocks) - OUT UINT8 Trcd; ///< DCT Trcd (busclocks) - OUT UINT8 Trp; ///< DCT Trp (busclocks) - OUT UINT8 Trtp; ///< DCT Trtp (busclocks) - OUT UINT8 Tras; ///< DCT Tras (busclocks) - OUT UINT8 Trc; ///< DCT Trc (busclocks) - OUT UINT8 Twr; ///< DCT Twr (busclocks) - OUT UINT8 Trrd; ///< DCT Trrd (busclocks) - OUT UINT8 Twtr; ///< DCT Twtr (busclocks) - OUT UINT8 Tfaw; ///< DCT Tfaw (busclocks) - OUT UINT8 Trfc0; ///< DCT Logical DIMM0 Trfc - ///< 0 = 75ns (for 256Mb devs) - ///< 1 = 105ns (for 512Mb devs) - ///< 2 = 127.5ns (for 1Gb devs) - ///< 3 = 195ns (for 2Gb devs) - ///< 4 = 327.5ns (for 4Gb devs) - OUT UINT8 Trfc1; ///< DCT Logical DIMM1 Trfc (see Trfc0 for format) - OUT UINT8 Trfc2; ///< DCT Logical DIMM2 Trfc (see Trfc0 for format) - OUT UINT8 Trfc3; ///< DCT Logical DIMM3 Trfc (see Trfc0 for format) - OUT UINT32 DctMemSize; ///< Base[47:16], total DRAM size controlled by this DCT. - ///< - OUT BOOLEAN SlowMode; ///< 1T or 2T CMD mode (slow access mode) - ///< FALSE = 1T - ///< TRUE = 2T - OUT UINT8 TrwtTO; ///< DCT TrwtTO (busclocks) - OUT UINT8 Twrrd; ///< DCT Twrrd (busclocks) - OUT UINT8 Twrwr; ///< DCT Twrwr (busclocks) - OUT UINT8 Trdrd; ///< DCT Trdrd (busclocks) - OUT UINT8 TrwtWB; ///< DCT TrwtWB (busclocks) - OUT UINT8 TrdrdSD; ///< DCT TrdrdSD (busclocks) - OUT UINT8 TwrwrSD; ///< DCT TwrwrSD (busclocks) - OUT UINT8 TwrrdSD; ///< DCT TwrrdSD (busclocks) - OUT UINT16 MaxRdLat; ///< Max Read Latency - OUT UINT8 WrDatGrossH; ///< Temporary variables must be removed - OUT UINT8 DqsRcvEnGrossL; ///< Temporary variables must be removed -} CH_TIMING_STRUCT; - -/// -/// Data for each DCT. -/// This data structure defines data used to configure each DRAM controller. -/// -typedef struct _DCT_STRUCT { - OUT UINT8 Dct; ///< Current Dct - OUT CH_TIMING_STRUCT Timings; ///< Channel Timing structure - OUT CH_DEF_STRUCT *ChData; ///< Pointed to a dynamically allocated array of Channel structures - OUT UINT8 ChannelCount; ///< Number of channel per this DCT - OUT BOOLEAN BkIntDis; ///< Bank interleave requested but not enabled on current DCT -} DCT_STRUCT; - - -/// -/// Data Structure defining each Die. -/// This data structure contains information that is used to configure each Die. -/// -typedef struct _DIE_STRUCT { - - /// Advanced: - - OUT UINT8 NodeId; ///< Node ID of current controller - OUT UINT8 SocketId; ///< Socket ID of this Die - OUT UINT8 DieId; ///< ID of this die relative to the socket - OUT PCI_ADDR PciAddr; ///< Pci bus and device number of this controller. - OUT AGESA_STATUS ErrCode; ///< Current error condition of Node - ///< 0x0 = AGESA_SUCCESS - ///< 0x1 = AGESA_UNSUPPORTED - ///< 0x2 = AGESA_BOUNDS_CHK - ///< 0x3 = AGESA_ALERT - ///< 0x4 = AGESA_WARNING - ///< 0x5 = AGESA_ERROR - ///< 0x6 = AGESA_CRITICAL - ///< 0x7 = AGESA_FATAL - ///< - OUT BOOLEAN ErrStatus[EsbEOL]; ///< Error Status bit Field - ///< - OUT BOOLEAN Status[SbEOL]; ///< Status bit Field - ///< - OUT UINT32 NodeMemSize; ///< Base[47:16], total DRAM size controlled by both DCT0 and DCT1 of this Node. - ///< - OUT UINT32 NodeSysBase; ///< Base[47:16] (system address) DRAM base address of this Node. - ///< - OUT UINT32 NodeHoleBase; ///< If not zero, Base[47:16] (system address) of dram hole for HW remapping. Dram hole exists on this Node - ///< - OUT UINT32 NodeSysLimit; ///< Base[47:16] (system address) DRAM limit address of this Node. - ///< - OUT UINT32 DimmPresent; ///< For each bit n 0..7, 1 = DIMM n is present. - ///< DIMM# Select Signal - ///< 0 MA0_CS_L[0, 1] - ///< 1 MB0_CS_L[0, 1] - ///< 2 MA1_CS_L[0, 1] - ///< 3 MB1_CS_L[0, 1] - ///< 4 MA2_CS_L[0, 1] - ///< 5 MB2_CS_L[0, 1] - ///< 6 MA3_CS_L[0, 1] - ///< 7 MB3_CS_L[0, 1] - ///< - OUT UINT32 DimmValid; ///< For each bit n 0..7, 1 = DIMM n is valid and is / will be configured - OUT UINT32 RegDimmPresent; ///< For each bit n 0..7, 1 = DIMM n is registered DIMM - OUT UINT32 LrDimmPresent; ///< For each bit n 0..7, 1 = DIMM n is Load Reduced DIMM - OUT UINT32 DimmEccPresent; ///< For each bit n 0..7, 1 = DIMM n is ECC capable. - OUT UINT32 DimmParPresent; ///< For each bit n 0..7, 1 = DIMM n is ADR/CMD Parity capable. - ///< - OUT UINT16 DimmTrainFail; ///< Bitmap showing which dimms failed training - OUT UINT16 ChannelTrainFail; ///< Bitmap showing the channel information about failed Chip Selects - ///< 0 in any bit field indicates Channel 0 - ///< 1 in any bit field indicates Channel 1 - OUT UINT8 Dct; ///< Need to be removed - ///< DCT pointer - OUT BOOLEAN GangedMode; ///< Ganged mode - ///< 0 = disabled - ///< 1 = enabled - OUT CPU_LOGICAL_ID LogicalCpuid; ///< The logical CPUID of the node - ///< - OUT UINT16 HostBiosSrvc1; ///< UINT16 sized general purpose field for use by host BIOS. Scratch space. - ///< - OUT UINT32 HostBiosSrvc2; ///< UINT32 sized general purpose field for use by host BIOS. Scratch space. - ///< - OUT UINT8 MLoad; ///< Need to be removed - ///< Number of devices loading MAA bus - ///< - OUT UINT8 MaxAsyncLat; ///< Legacy wrapper - ///< - OUT UINT8 ChbD3Rcvrdly; ///< Legacy wrapper - ///< - OUT UINT16 ChaMaxRdLat; ///< Max Read Latency (ns) for DCT 0 - ///< - OUT UINT8 ChbD3BcRcvrdly; ///< CHB DIMM 3 Check UINT8 Receiver Enable Delay - - OUT DCT_STRUCT *DctData; ///< Pointed to a dynamically allocated array of DCT_STRUCTs - OUT UINT8 DctCount; ///< Number of DCTs per this Die - OUT UINT8 Reserved[16]; ///< Reserved -} DIE_STRUCT; - -/********************************************************************** - * S3 Support structure - **********************************************************************/ -/// AmdInitResume, AmdS3LateRestore, and AmdS3Save param structure -typedef struct { - OUT UINT32 Signature; ///< "ASTR" for AMD Suspend-To-RAM - OUT UINT16 Version; ///< S3 Params version number - IN OUT UINT32 Flags; ///< Indicates operation - IN OUT VOID *NvStorage; ///< Pointer to memory critical save state data - IN OUT UINT32 NvStorageSize; ///< Size in bytes of the NvStorage region - IN OUT VOID *VolatileStorage; ///< Pointer to remaining AMD save state data - IN OUT UINT32 VolatileStorageSize; ///< Size in bytes of the VolatileStorage region -} AMD_S3_PARAMS; - -///=============================================================================== -/// MEM_PARAMETER_STRUCT -/// This data structure is used to pass wrapper parameters to the memory configuration code -/// -typedef struct _MEM_PARAMETER_STRUCT { - - // Basic (Return parameters) - // (This section contains the outbound parameters from the memory init code) - - OUT BOOLEAN GStatus[GsbEOL]; ///< Global Status bitfield. - ///< - OUT UINT32 HoleBase; ///< If not zero Base[47:16] (system address) of sub 4GB dram hole for HW remapping. - ///< - OUT UINT32 Sub4GCacheTop; ///< If not zero, the 32-bit top of cacheable memory. - ///< - OUT UINT32 Sub1THoleBase; ///< If not zero Base[47:16] (system address) of sub 1TB dram hole. - ///< - OUT UINT32 SysLimit; ///< Limit[47:16] (system address). - ///< - OUT DIMM_VOLTAGE DDR3Voltage; ///< Find support voltage and send back to platform BIOS. - ///< - - OUT struct _MEM_DATA_STRUCT *MemData; ///< Access to global memory init data. - - // Advanced (Optional parameters) - // Optional (all defaults values will be initialized by the - // 'AmdMemInitDataStructDef' based on AMD defaults. It is up - // to the IBV/OEM to change the defaults after initialization - // but prior to the main entry to the memory code): - - // Memory Map/Mgt. - - IN UINT16 BottomIo; ///< Bottom of 32-bit IO space (8-bits). - ///< NV_BOTTOM_IO[7:0]=Addr[31:24] - ///< - IN BOOLEAN MemHoleRemapping; ///< Memory Hole Remapping (1-bit). - ///< FALSE = disable - ///< TRUE = enable - ///< - IN BOOLEAN LimitMemoryToBelow1Tb;///< Limit memory address space to below 1 TB - ///< FALSE = disable - ///< TRUE = enable - ///< - ///< @BldCfgItem{BLDCFG_LIMIT_MEMORY_TO_BELOW_1TB} - - - // Dram Timing - - IN USER_MEMORY_TIMING_MODE UserTimingMode; ///< User Memclock Mode. - ///< @BldCfgItem{BLDCFG_TIMING_MODE_SELECT} - - IN MEMORY_BUS_SPEED MemClockValue; ///< Memory Clock Value. - ///< @BldCfgItem{BLDCFG_MEMORY_CLOCK_SELECT} - - - // Dram Configuration - - IN BOOLEAN EnableBankIntlv; ///< Dram Bank (chip-select) Interleaving (1-bit). - ///< - FALSE =disable (default) - ///< - TRUE = enable - ///< - ///< @BldCfgItem{BLDCFG_MEMORY_ENABLE_BANK_INTERLEAVING} - - IN BOOLEAN EnableNodeIntlv; ///< Node Memory Interleaving (1-bit). - ///< - FALSE = disable (default) - ///< - TRUE = enable - ///< - ///< @BldCfgItem{BLDCFG_MEMORY_ENABLE_NODE_INTERLEAVING} - - IN BOOLEAN EnableChannelIntlv; ///< Channel Interleaving (1-bit). - ///< - FALSE = disable (default) - ///< - TRUE = enable - ///< - ///< @BldCfgItem{BLDCFG_MEMORY_CHANNEL_INTERLEAVING} - // ECC - - IN BOOLEAN EnableEccFeature; ///< enable ECC error to go into MCE. - ///< - FALSE = disable (default) - ///< - TRUE = enable - ///< - ///< @BldCfgItem{BLDCFG_ENABLE_ECC_FEATURE} - // Dram Power - - IN BOOLEAN EnablePowerDown; ///< CKE based power down mode (1-bit). - ///< - FALSE =disable (default) - ///< - TRUE =enable - ///< - ///< @BldCfgItem{BLDCFG_MEMORY_POWER_DOWN} - - // Online Spare - - IN BOOLEAN EnableOnLineSpareCtl; ///< Chip Select Spare Control bit 0. - ///< - FALSE = disable Spare (default) - ///< - TRUE = enable Spare - ///< - ///< @BldCfgItem{BLDCFG_ONLINE_SPARE} - - IN UINT8 *TableBasedAlterations; ///< Desired modifications to register settings. - - IN PSO_TABLE *PlatformMemoryConfiguration; - ///< A table that contains platform specific settings. - ///< For example, MemClk routing, the number of DIMM slots per channel, .... - ///< AGESA initializes this pointer with DefaultPlatformMemoryConfiguration that - ///< contains default conservative settings. Platform BIOS can either tweak - ///< DefaultPlatformMemoryConfiguration or reassign this pointer to its own table. - ///< - IN BOOLEAN EnableParity; ///< Parity control. - ///< - TRUE = enable - ///< - FALSE = disable (default) - ///< - ///< @BldCfgItem{BLDCFG_MEMORY_PARITY_ENABLE} - - IN BOOLEAN EnableBankSwizzle; ///< BankSwizzle control. - ///< - FALSE = disable - ///< - TRUE = enable (default) - ///< - ///< @BldCfgItem{BLDCFG_BANK_SWIZZLE} - - ///< - - IN BOOLEAN EnableMemClr; ///< Memory Clear functionality control. - ///< - FALSE = disable - ///< - TRUE = enable (default) - ///< - - // Uma Configuration - - IN UMA_MODE UmaMode; ///< Uma Mode - ///< 0 = None - ///< 1 = Specified - ///< 2 = Auto - IN OUT UINT32 UmaSize; ///< The size of shared graphics dram (16-bits) - ///< NV_UMA_Size[31:0]=Addr[47:16] - ///< - OUT UINT32 UmaBase; ///< The allocated Uma base address (32-bits) - ///< NV_UMA_Base[31:0]=Addr[47:16] - ///< - - /// Memory Restore Feature - - IN BOOLEAN MemRestoreCtl; ///< Memory context restore control - ///< FALSE = perform memory init as normal (AMD default) - ///< TRUE = restore memory context and skip training. This requires - ///< MemContext is valid before AmdInitPost - ///< - IN BOOLEAN SaveMemContextCtl; ///< Control switch to save memory context at the end of MemAuto - ///< TRUE = AGESA will setup MemContext block before exit AmdInitPost - ///< FALSE = AGESA will not setup MemContext block. Platform is - ///< expected to call S3Save later in POST if it wants to - ///< use memory context restore feature. - ///< - IN OUT AMD_S3_PARAMS MemContext; ///< Memory context block describes the data that platform needs to - ///< save and restore for memory context restore feature to work. - ///< It uses the subset of S3Save block to save/restore. Hence platform - ///< may save only S3 block and uses it for both S3 resume and - ///< memory context restore. - ///< - If MemRestoreCtl is TRUE, platform needs to pass in MemContext - ///< before AmdInitPost. - ///< - If SaveMemContextCtl is TRUE, platform needs to save MemContext - ///< right after AmdInitPost. - ///< -} MEM_PARAMETER_STRUCT; - - -/// -/// Function definition. -/// This data structure passes function pointers to the memory configuration code. -/// The wrapper can use this structure with customized versions. -/// -typedef struct _MEM_FUNCTION_STRUCT { - - // PUBLIC required Internal functions - - IN OUT BOOLEAN (*amdMemGetPsCfgU) ( VOID *pMemData); ///< Proc for Unbuffered DIMMs, platform specific - IN OUT BOOLEAN (*amdMemGetPsCfgR) (VOID *pMemData); ///< Proc for Registered DIMMs, platform specific - - // PUBLIC optional functions - - IN OUT VOID (*amdMemEccInit) (VOID *pMemData); ///< NB proc for ECC feature - IN OUT VOID (*amdMemChipSelectInterleaveInit) (VOID *pMemData); ///< NB proc for CS interleave feature - IN OUT VOID (*amdMemDctInterleavingInit) (VOID *pMemData); ///< NB proc for Channel interleave feature - IN OUT VOID (*amdMemMctInterleavingInit) (VOID *pMemData); ///< NB proc for Node interleave feature - IN OUT VOID (*amdMemParallelTraining) (VOID *pMemData); ///< NB proc for parallel training feature - IN OUT VOID (*amdMemEarlySampleSupport) (VOID *pMemData); ///< NB code for early sample support feature - IN OUT VOID (*amdMemMultiPartInitSupport) (VOID *pMemData); ///< NB code for 'multi-part' - IN OUT VOID (*amdMemOnlineSpareSupport) (VOID *pMemData); ///< NB code for On-Line Spare feature - IN OUT VOID (*amdMemUDimmInit) (VOID *pMemData); ///< NB code for UDIMMs - IN OUT VOID (*amdMemRDimmInit) (VOID *pMemData); ///< NB code for RDIMMs - IN OUT VOID (*amdMemLrDimmInit) (VOID *pMemData); ///< NB code for LRDIMMs - - IN OUT UINT32 Reserved[100]; ///< Reserved for later function definition -} MEM_FUNCTION_STRUCT; - -/// -/// Socket Structure -/// -/// -typedef struct _MEM_SOCKET_STRUCT { - OUT VOID *ChannelPtr[MAX_CHANNELS_PER_SOCKET]; ///< Pointers to each channels training data - - OUT VOID *TimingsPtr[MAX_CHANNELS_PER_SOCKET]; ///< Pointers to each channels timing data -} MEM_SOCKET_STRUCT; - -/// -/// Contains all data relevant to Memory Initialization. -/// -typedef struct _MEM_DATA_STRUCT { - IN AMD_CONFIG_PARAMS StdHeader; ///< Standard configuration header - - IN MEM_PARAMETER_STRUCT *ParameterListPtr; ///< List of input Parameters - - OUT MEM_FUNCTION_STRUCT FunctionList; ///< List of function Pointers - - IN OUT AGESA_STATUS (*GetPlatformCfg[MAX_PLATFORM_TYPES]) (struct _MEM_DATA_STRUCT *MemData, UINT8 SocketID, CH_DEF_STRUCT *CurrentChannel); ///< look-up platform info - - IN OUT BOOLEAN (*ErrorHandling)(struct _DIE_STRUCT *MCTPtr, UINT8 DCT, UINT16 ChipSelMask, AMD_CONFIG_PARAMS *StdHeader); ///< Error Handling - - - OUT MEM_SOCKET_STRUCT SocketList[MAX_SOCKETS_SUPPORTED]; ///< Socket list for memory code. - ///< SocketList is a shortcut for IBVs to retrieve training - ///< and timing data for each channel indexed by socket/channel, - ///< eliminating their need to parse die/dct/channel etc. - ///< It contains pointers to the populated data structures for - ///< each channel and skips the channel structures that are - ///< unpopulated. In the case of channels sharing the same DCT, - ///< the pTimings pointers will point to the same DCT Timing data. - - OUT DIE_STRUCT *DiesPerSystem; ///< Pointed to an array of DIE_STRUCTs - OUT UINT8 DieCount; ///< Number of MCTs in the system. - - IN SPD_DEF_STRUCT *SpdDataStructure; ///< Pointer to SPD Data structure - - IN OUT struct _PLATFORM_CONFIGURATION *PlatFormConfig; ///< Platform profile/build option config structure - - IN OUT BOOLEAN IsFlowControlSupported; ///< Indicates if flow control is supported - - OUT UINT32 TscRate; ///< The rate at which the TSC increments in megahertz. - -} MEM_DATA_STRUCT; - -/// -/// Uma Structure -/// -/// -typedef struct _UMA_INFO { - OUT UINT64 UmaBase; ///< UmaBase[63:0] = Addr[63:0] - OUT UINT32 UmaSize; ///< UmaSize[31:0] = Addr[31:0] - OUT UINT32 UmaAttributes; ///< Indicate the attribute of Uma - OUT UINT8 UmaMode; ///< Indicate the mode of Uma - OUT UINT16 MemClock; ///< Indicate memory running speed in MHz - OUT UINT8 Reserved[3]; ///< Reserved for future usage -} UMA_INFO; - -/// Bitfield for ID -typedef struct { - OUT UINT16 SocketId:8; ///< Socket ID - OUT UINT16 ModuleId:8; ///< Module ID -} ID_FIELD; -/// -/// Union for ID of socket and module that will be passed out in call out -/// -typedef union { - OUT ID_FIELD IdField; ///< Bitfield for ID - OUT UINT16 IdInformation; ///< ID information for call out -} ID_INFO; - -// AGESA MEMORY ERRORS - -// AGESA_ALERT Memory Errors -#define MEM_ALERT_USER_TMG_MODE_OVERRULED 0x04010000 ///< TIMING_MODE_SPECIFIC is requested but - ///< cannot be applied to current configurations. -#define MEM_ALERT_ORG_MISMATCH_DIMM 0x04010100 ///< DIMM organization miss-match -#define MEM_ALERT_BK_INT_DIS 0x04010200 ///< Bank interleaving disable for internal issue - -// AGESA_ERROR Memory Errors -#define MEM_ERROR_NO_DQS_POS_RD_WINDOW 0x04010300 ///< No DQS Position window for RD DQS -#define MEM_ERROR_SMALL_DQS_POS_RD_WINDOW 0x04020300 ///< Small DQS Position window for RD DQS -#define MEM_ERROR_NO_DQS_POS_WR_WINDOW 0x04030300 ///< No DQS Position window for WR DQS -#define MEM_ERROR_SMALL_DQS_POS_WR_WINDOW 0x04040300 ///< Small DQS Position window for WR DQS -#define MEM_ERROR_ECC_DIS 0x04010400 ///< ECC has been disabled as a result of an internal issue -#define MEM_ERROR_DIMM_SPARING_NOT_ENABLED 0x04010500 ///< DIMM sparing has not been enabled for an internal issues -#define MEM_ERROR_RCVR_EN_VALUE_TOO_LARGE 0x04050300 ///< Receive Enable value is too large -#define MEM_ERROR_RCVR_EN_NO_PASSING_WINDOW 0x04060300 ///< There is no DQS receiver enable window -#define MEM_ERROR_DRAM_ENABLED_TIME_OUT 0x04010600 ///< Time out when polling DramEnabled bit -#define MEM_ERROR_DCT_ACCESS_DONE_TIME_OUT 0x04010700 ///< Time out when polling DctAccessDone bit -#define MEM_ERROR_SEND_CTRL_WORD_TIME_OUT 0x04010800 ///< Time out when polling SendCtrlWord bit -#define MEM_ERROR_PREF_DRAM_TRAIN_MODE_TIME_OUT 0x04010900 ///< Time out when polling PrefDramTrainMode bit -#define MEM_ERROR_ENTER_SELF_REF_TIME_OUT 0x04010A00 ///< Time out when polling EnterSelfRef bit -#define MEM_ERROR_FREQ_CHG_IN_PROG_TIME_OUT 0x04010B00 ///< Time out when polling FreqChgInProg bit -#define MEM_ERROR_EXIT_SELF_REF_TIME_OUT 0x04020A00 ///< Time out when polling ExitSelfRef bit -#define MEM_ERROR_SEND_MRS_CMD_TIME_OUT 0x04010C00 ///< Time out when polling SendMrsCmd bit -#define MEM_ERROR_SEND_ZQ_CMD_TIME_OUT 0x04010D00 ///< Time out when polling SendZQCmd bit -#define MEM_ERROR_DCT_EXTRA_ACCESS_DONE_TIME_OUT 0x04010E00 ///< Time out when polling DctExtraAccessDone bit -#define MEM_ERROR_MEM_CLR_BUSY_TIME_OUT 0x04010F00 ///< Time out when polling MemClrBusy bit -#define MEM_ERROR_MEM_CLEARED_TIME_OUT 0x04020F00 ///< Time out when polling MemCleared bit -#define MEM_ERROR_FLUSH_WR_TIME_OUT 0x04011000 ///< Time out when polling FlushWr bit -#define MEM_ERROR_MAX_LAT_NO_WINDOW 0x04070300 ///< Fail to find pass during Max Rd Latency training -#define MEM_ERROR_PARALLEL_TRAINING_LAUNCH_FAIL 0x04080300 ///< Fail to launch training code on an AP -#define MEM_ERROR_PARALLEL_TRAINING_TIME_OUT 0x04090300 ///< Fail to finish parallel training -#define MEM_ERROR_NO_ADDRESS_MAPPING 0x04011100 ///< No address mapping found for a dimm -#define MEM_ERROR_RCVR_EN_NO_PASSING_WINDOW_EQUAL_LIMIT 0x040A0300 ///< There is no DQS receiver enable window and the value is equal to the largest value -#define MEM_ERROR_RCVR_EN_VALUE_TOO_LARGE_LIMIT_LESS_ONE 0x040B0300 ///< Receive Enable value is too large and is 1 less than limit -#define MEM_ERROR_CHECKSUM_NV_SPDCHK_RESTRT_ERROR 0x04011200 ///< SPD Checksum error for NV_SPDCHK_RESTRT -#define MEM_ERROR_NO_CHIPSELECT 0x04011300 ///< No chipselects found -#define MEM_ERROR_UNSUPPORTED_333MHZ_UDIMM 0x04011500 ///< Unbuffered dimm is not supported at 333MHz -#define MEM_ERROR_WL_PRE_OUT_OF_RANGE 0x040C0300 ///< Returned PRE value during write levelizzation was out of range - -// AGESA_WARNING Memory Errors -#define MEM_WARNING_UNSUPPORTED_QRDIMM 0x04011600 ///< QR DIMMs detected but not supported -#define MEM_WARNING_UNSUPPORTED_UDIMM 0x04021600 ///< U DIMMs detected but not supported -#define MEM_WARNING_UNSUPPORTED_SODIMM 0x04031600 ///< SO-DIMMs detected but not supported -#define MEM_WARNING_UNSUPPORTED_X4DIMM 0x04041600 ///< x4 DIMMs detected but not supported -#define MEM_WARNING_UNSUPPORTED_RDIMM 0x04051600 ///< R DIMMs detected but not supported -#define MEM_WARNING_UNSUPPORTED_LRDIMM 0x04061600 ///< LR DIMMs detected but not supported -#define MEM_WARNING_EMP_NOT_SUPPORTED 0x04011700 ///< Processor is not capable for EMP -#define MEM_WARNING_EMP_CONFLICT 0x04021700 ///< EMP cannot be enabled if channel interleaving, -#define MEM_WARNING_EMP_NOT_ENABLED 0x04031700 ///< Memory size is not power of two. -#define MEM_WARNING_PERFORMANCE_ENABLED_BATTERY_LIFE_PREFERRED 0x04011800 ///< Performance has been enabled, but battery life is preferred. - ///< bank interleaving, or bank swizzle is enabled. -#define MEM_WARNING_NO_SPDTRC_FOUND 0x04011900 ///< No Trc timing value found in SPD of a dimm. -#define MEM_WARNING_NODE_INTERLEAVING_NOT_ENABLED 0x04012000 ///< Node Interleaveing Requested, but could not be enabled -#define MEM_WARNING_CHANNEL_INTERLEAVING_NOT_ENABLED 0x04012100 ///< Channel Interleaveing Requested, but could not be enabled -#define MEM_WARNING_BANK_INTERLEAVING_NOT_ENABLED 0x04012200 ///< Bank Interleaveing Requested, but could not be enabled -#define MEM_WARNING_VOLTAGE_1_35_NOT_SUPPORTED 0x04012300 ///< Voltage 1.35 determined, but could not be supported -#define MEM_WARNING_INITIAL_DDR3VOLT_NONZERO 0x04012400 ///< DDR3 voltage initial value is not 0 -#define MEM_WARNING_NO_COMMONLY_SUPPORTED_VDDIO 0x04012500 ///< Cannot find a commonly supported VDDIO - -// AGESA_FATAL Memory Errors -#define MEM_ERROR_MINIMUM_MODE 0x04011A00 ///< Running in minimum mode -#define MEM_ERROR_MODULE_TYPE_MISMATCH_DIMM 0x04011B00 ///< DIMM modules are miss-matched -#define MEM_ERROR_NO_DIMM_FOUND_ON_SYSTEM 0x04011C00 ///< No DIMMs have been found -#define MEM_ERROR_MISMATCH_DIMM_CLOCKS 0x04011D00 ///< DIMM clocks miss-matched -#define MEM_ERROR_NO_CYC_TIME 0x04011E00 ///< No cycle time found -#define MEM_ERROR_HEAP_ALLOCATE_DYN_STORING_OF_TRAINED_TIMINGS 0x04011F00 ///< Heap allocation error with dynamic storing of trained timings -#define MEM_ERROR_HEAP_ALLOCATE_FOR_DCT_STRUCT_AND_CH_DEF_STRUCTs 0x04021F00 ///< Heap allocation error for DCT_STRUCT and CH_DEF_STRUCT -#define MEM_ERROR_HEAP_ALLOCATE_FOR_REMOTE_TRAINING_ENV 0x04031F00 ///< Heap allocation error with REMOTE_TRAINING_ENV -#define MEM_ERROR_HEAP_ALLOCATE_FOR_SPD 0x04041F00 ///< Heap allocation error for SPD data -#define MEM_ERROR_HEAP_ALLOCATE_FOR_RECEIVED_DATA 0x04051F00 ///< Heap allocation error for RECEIVED_DATA during parallel training -#define MEM_ERROR_HEAP_ALLOCATE_FOR_S3_SPECIAL_CASE_REGISTERS 0x04061F00 ///< Heap allocation error for S3 "SPECIAL_CASE_REGISTER" -#define MEM_ERROR_HEAP_ALLOCATE_FOR_TRAINING_DATA 0x04071F00 ///< Heap allocation error for Training Data -#define MEM_ERROR_HEAP_ALLOCATE_FOR_IDENTIFY_DIMM_MEM_NB_BLOCK 0x04081F00 ///< Heap allocation error for DIMM Identify "MEM_NB_BLOCK -#define MEM_ERROR_NO_CONSTRUCTOR_FOR_IDENTIFY_DIMM 0x04022300 ///< No Constructor for DIMM Identify -#define MEM_ERROR_VDDIO_UNSUPPORTED 0x04022500 ///< VDDIO of the dimms on the board is not supported - -// AGESA_CRITICAL Memory Errors -#define MEM_ERROR_HEAP_ALLOCATE_FOR_DMI_TABLE_DDR3 0x04091F00 ///< Heap allocation error for DMI table for DDR3 -#define MEM_ERROR_HEAP_ALLOCATE_FOR_DMI_TABLE_DDR2 0x040A1F00 ///< Heap allocation error for DMI table for DDR2 -#define MEM_ERROR_UNSUPPORTED_DIMM_CONFIG 0x04011400 ///< Dimm population is not supported - - - -/*---------------------------------------------------------------------------- - * - * END OF MEMORY-SPECIFIC DATA STRUCTURES - * - *---------------------------------------------------------------------------- - */ - - - - -/*---------------------------------------------------------------------------- - * - * CPU RELATED DEFINITIONS - * - *---------------------------------------------------------------------------- - */ - -// CPU Event definitions. - -// Defines used to filter CPU events based on functional blocks -#define CPU_EVENT_PM_EVENT_MASK 0xFF00FF00 -#define CPU_EVENT_PM_EVENT_CLASS 0x08000400 - -//================================================================ -// CPU General events -// Heap allocation (AppFunction = 01h) -#define CPU_ERROR_HEAP_BUFFER_IS_NOT_PRESENT 0x08000100 -#define CPU_ERROR_HEAP_IS_ALREADY_INITIALIZED 0x08010100 -#define CPU_ERROR_HEAP_IS_FULL 0x08020100 -#define CPU_ERROR_HEAP_BUFFER_HANDLE_IS_ALREADY_USED 0x08030100 -#define CPU_ERROR_HEAP_BUFFER_HANDLE_IS_NOT_PRESENT 0x08040100 -// BrandId (AppFunction = 02h) -#define CPU_ERROR_BRANDID_HEAP_NOT_AVAILABLE 0x08000200 -// Micro code patch (AppFunction = 03h) -#define CPU_ERROR_MICRO_CODE_PATCH_IS_NOT_LOADED 0x08000300 -// Power management (AppFunction = 04h) -#define CPU_EVENT_PM_PSTATE_OVERCURRENT 0x08000400 -#define CPU_EVENT_PM_ALL_PSTATE_OVERCURRENT 0x08010400 -#define CPU_ERROR_PSTATE_HEAP_NOT_AVAILABLE 0x08020400 -#define CPU_ERROR_PM_NB_PSTATE_MISMATCH 0x08030400 -// Other CPU events (AppFunction = 05h) -#define CPU_EVENT_BIST_ERROR 0x08000500 -#define CPU_EVENT_UNKNOWN_PROCESSOR_FAMILY 0x08010500 -#define CPU_EVENT_STACK_REENTRY 0x08020500 -#define CPU_EVENT_CORE_NOT_IDENTIFIED 0x08030500 - -//================================================================= -// CPU Feature events -// Execution cache (AppFunction = 21h) -// AGESA_CACHE_SIZE_REDUCED 2101 -// AGESA_CACHE_REGIONS_ACROSS_1MB 2102 -// AGESA_CACHE_REGIONS_ACROSS_4GB 2103 -// AGESA_REGION_NOT_ALIGNED_ON_BOUNDARY 2104 -// AGESA_CACHE_START_ADDRESS_LESS_D0000 2105 -// AGESA_THREE_CACHE_REGIONS_ABOVE_1MB 2106 -// AGESA_DEALLOCATE_CACHE_REGIONS 2107 -#define CPU_EVENT_EXECUTION_CACHE_ALLOCATION_ERROR 0x08002100 -// Core Leveling (AppFunction = 22h) -#define CPU_WARNING_ADJUSTED_LEVELING_MODE 0x08002200 -// HT Assist (AppFunction = 23h) -#define CPU_WARNING_NONOPTIMAL_HT_ASSIST_CFG 0x08002300 - -// CPU Build Configuration structures and definitions - -/// Build Configuration structure for BLDCFG_AP_MTRR_SETTINGS -typedef struct { - IN UINT32 MsrAddr; ///< Fixed-Sized MTRR address - IN UINT64 MsrData; ///< MTRR Settings -} AP_MTRR_SETTINGS; - -#define AMD_AP_MTRR_FIX64k_00000 0x00000250 -#define AMD_AP_MTRR_FIX16k_80000 0x00000258 -#define AMD_AP_MTRR_FIX16k_A0000 0x00000259 -#define AMD_AP_MTRR_FIX4k_C0000 0x00000268 -#define AMD_AP_MTRR_FIX4k_C8000 0x00000269 -#define AMD_AP_MTRR_FIX4k_D0000 0x0000026A -#define AMD_AP_MTRR_FIX4k_D8000 0x0000026B -#define AMD_AP_MTRR_FIX4k_E0000 0x0000026C -#define AMD_AP_MTRR_FIX4k_E8000 0x0000026D -#define AMD_AP_MTRR_FIX4k_F0000 0x0000026E -#define AMD_AP_MTRR_FIX4k_F8000 0x0000026F -#define CPU_LIST_TERMINAL 0xFFFFFFFF - -/************************************************************************ - * - * AGESA interface Call-Out function parameter structures - * - ***********************************************************************/ - -/// Parameters structure for interface call-out AgesaAllocateBuffer -typedef struct { - IN OUT AMD_CONFIG_PARAMS StdHeader; ///< Standard configuration header - IN OUT UINT32 BufferLength; ///< Size of buffer to allocate - IN UINT32 BufferHandle; ///< Identifier or name for the buffer - OUT VOID *BufferPointer; ///< location of the created buffer -} AGESA_BUFFER_PARAMS; - -/// Parameters structure for interface call-out AgesaRunCodeOnAp -typedef struct { - IN OUT AMD_CONFIG_PARAMS StdHeader; ///< Standard configuration header - IN UINT32 FunctionNumber; ///< Index of the procedure to execute - IN VOID *RelatedDataBlock; ///< Location of data structure the procedure will use - IN UINT32 RelatedBlockLength; ///< Size of the related data block -} AP_EXE_PARAMS; - -/// Parameters structure for the interface call-out AgesaReadSpd & AgesaReadSpdRecovery -typedef struct { - IN OUT AMD_CONFIG_PARAMS StdHeader; ///< Standard configuration header - IN UINT8 SocketId; ///< Address of SPD - socket ID - IN UINT8 MemChannelId; ///< Address of SPD - memory channel ID - IN UINT8 DimmId; ///< Address of SPD - DIMM ID - IN OUT UINT8 *Buffer; ///< Location where to place the SPD content - IN OUT MEM_DATA_STRUCT *MemData; ///< Location of the MemData structure, for reference -} AGESA_READ_SPD_PARAMS; - -/// Buffer Handles -typedef enum { - AMD_DMI_INFO_BUFFER_HANDLE = 0x000D000, ///< Assign 0x000D000 buffer handle to DMI function - AMD_PSTATE_DATA_BUFFER_HANDLE, ///< Assign 0x000D001 buffer handle to Pstate data - AMD_PSTATE_ACPI_BUFFER_HANDLE, ///< Assign 0x000D002 buffer handle to Pstate table - AMD_BRAND_ID_BUFFER_HANDLE, ///< Assign 0x000D003 buffer handle to Brand ID - AMD_ACPI_SLIT_BUFFER_HANDLE, ///< Assign 0x000D004 buffer handle to SLIT function - AMD_SRAT_INFO_BUFFER_HANDLE, ///< Assign 0x000D005 buffer handle to SRAT function - AMD_WHEA_BUFFER_HANDLE, ///< Assign 0x000D006 buffer handle to WHEA function - AMD_S3_INFO_BUFFER_HANDLE, ///< Assign 0x000D007 buffer handle to S3 function - AMD_S3_NB_INFO_BUFFER_HANDLE, ///< Assign 0x000D008 buffer handle to S3 NB device info - AMD_ACPI_ALIB_BUFFER_HANDLE, ///< Assign 0x000D009 buffer handle to ALIB SSDT table - AMD_ACPI_IVRS_BUFFER_HANDLE ///< Assign 0x000D00A buffer handle to IOMMU IVRS table -} AMD_BUFFER_HANDLE; -/************************************************************************ - * - * AGESA interface Call-Out function prototypes - * - ***********************************************************************/ - -VOID -AgesaDoReset ( - IN UINTN ResetType, - IN OUT AMD_CONFIG_PARAMS *StdHeader - ); - -AGESA_STATUS -AgesaAllocateBuffer ( - IN UINTN FcnData, - IN OUT AGESA_BUFFER_PARAMS *AllocParams - ); - -AGESA_STATUS -AgesaDeallocateBuffer ( - IN UINTN FcnData, - IN OUT AGESA_BUFFER_PARAMS *DeallocParams - ); - -AGESA_STATUS -AgesaLocateBuffer ( - IN UINTN FcnData, - IN OUT AGESA_BUFFER_PARAMS *LocateParams - ); - -AGESA_STATUS -AgesaReadSpd ( - IN UINTN FcnData, - IN OUT AGESA_READ_SPD_PARAMS *ReadSpd - ); - -AGESA_STATUS -AgesaReadSpdRecovery ( - IN UINTN FcnData, - IN OUT AGESA_READ_SPD_PARAMS *ReadSpd - ); - -AGESA_STATUS -AgesaHookBeforeDramInitRecovery ( - IN UINTN FcnData, - IN OUT MEM_DATA_STRUCT *MemData - ); - -AGESA_STATUS -AgesaRunFcnOnAp ( - IN UINTN ApicIdOfCore, - IN AP_EXE_PARAMS *LaunchApParams - ); - -AGESA_STATUS -AgesaHookBeforeDramInit ( - IN UINTN SocketIdModuleId, - IN OUT MEM_DATA_STRUCT *MemData - ); - -AGESA_STATUS -AgesaHookBeforeDQSTraining ( - IN UINTN SocketIdModuleId, - IN OUT MEM_DATA_STRUCT *MemData - ); - -AGESA_STATUS -AgesaHookBeforeExitSelfRefresh ( - IN UINTN FcnData, - IN OUT MEM_DATA_STRUCT *MemData - ); - -AGESA_STATUS -AgesaPcieSlotResetControl ( - IN UINTN FcnData, - IN PCIe_SLOT_RESET_INFO *ResetInfo - ); - -AGESA_STATUS -AgesaFchOemCallout ( - IN VOID *FchData - ); - -/************************************************************************ - * - * AGESA interface structure definition and function prototypes - * - ***********************************************************************/ - -/********************************************************************** - * Platform Configuration: The parameters in boot branch function - **********************************************************************/ - -/// The possible platform control flow settings. -typedef enum { - Nfcm, ///< Normal Flow Control Mode. - UmaDr, ///< UMA using Display Refresh flow control. - UmaIfcm, ///< UMA using Isochronous Flow Control. - Ifcm, ///< Isochronous Flow Control Mode (other than for UMA). - Iommu, ///< An IOMMU is in use in the system. - MaxControlFlow ///< Not a control flow mode, use for limit checking. -} PLATFORM_CONTROL_FLOW; - -/// Platform Deemphasis Levels. -/// -/// The deemphasis level is set for the receiver, based on link characterization. The DCV level is -/// set based on the level of the far transmitter. -typedef enum { - DeemphasisLevelNone, ///< No Deemphasis. - DeemphasisLevelMinus3, ///< Minus 3 db deemphasis. - DeemphasisLevelMinus6, ///< Minus 6 db deemphasis. - DeemphasisLevelMinus8, ///< Minus 8 db deemphasis. - DeemphasisLevelMinus11, ///< Minus 11 db deemphasis. - DeemphasisLevelMinus11pre8, ///< Minus 11, Minus 8 precursor db deemphasis. - DcvLevelNone = 16, ///< No DCV Deemphasis. - DcvLevelMinus2, ///< Minus 2 db DCV deemphasis. - DcvLevelMinus3, ///< Minus 3 db DCV deemphasis. - DcvLevelMinus5, ///< Minus 5 db DCV deemphasis. - DcvLevelMinus6, ///< Minus 6 db DCV deemphasis. - DcvLevelMinus7, ///< Minus 7 db DCV deemphasis. - DcvLevelMinus8, ///< Minus 8 db DCV deemphasis. - DcvLevelMinus9, ///< Minus 9 db DCV deemphasis. - DcvLevelMinus11, ///< Minus 11 db DCV deemphasis. - MaxPlatformDeemphasisLevel ///< Not a deemphasis level, use for limit checking. -} PLATFORM_DEEMPHASIS_LEVEL; - -/// Provide Deemphasis Levels for HT Links. -/// -/// For each CPU to CPU or CPU to IO device HT link, the list of Deemphasis Levels will -/// be checked for a match. The item matches for a Socket, Link if the link frequency is -/// is in the inclusive range HighFreq:LoFreq. -/// AGESA does not set deemphasis in IO devices, only in processors. - -typedef struct { - // Match fields - IN UINT8 Socket; ///< One Socket on which this Link is located - IN UINT8 Link; ///< The Link on this Processor. - IN UINT8 LoFreq; ///< If the link is set to this frequency or greater, apply these levels, and - IN UINT8 HighFreq; ///< If the link is set to this frequency or less, apply these levels. - // Value fields - IN PLATFORM_DEEMPHASIS_LEVEL ReceiverDeemphasis; ///< The deemphasis level for this link - IN PLATFORM_DEEMPHASIS_LEVEL DcvDeemphasis; ///< The DCV, or far transmitter deemphasis level. -} CPU_HT_DEEMPHASIS_LEVEL; - -/// The possible platform power policy settings. -typedef enum { - Performance, ///< Optimize for performance. - BatteryLife, ///< Optimize for battery life. - MaxPowerPolicy ///< Not a power policy mode, use for limit checking. -} PLATFORM_POWER_POLICY; - -/// Platform performance settings for optimized settings. -/// Several configuration settings for the processor depend upon other parts and -/// general designer choices for the system. The determination of these data points -/// is not standard for all platforms, so the host environment needs to provide these -/// to specify how the system is to be configured. -typedef struct { - IN PLATFORM_CONTROL_FLOW PlatformControlFlowMode; ///< The platform's control flow mode for optimum platform performance. - ///< @BldCfgItem{BLDCFG_PLATFORM_CONTROL_FLOW_MODE} - IN BOOLEAN UseHtAssist; ///< HyperTransport link traffic optimization. - ///< @BldCfgItem{BLDCFG_USE_HT_ASSIST} - IN BOOLEAN UseAtmMode; ///< HyperTransport link traffic optimization. - ///< @BldCfgItem{BLDCFG_USE_ATM_MODE} - IN BOOLEAN Use32ByteRefresh; ///< Display Refresh traffic generates 32 byte requests. - ///< @BldCfgItem{BLDCFG_USE_32_BYTE_REFRESH} - IN BOOLEAN UseVariableMctIsocPriority; ///< The Memory controller will be set to Variable Isoc Priority. - ///< @BldCfgItem{BLDCFG_USE_VARIABLE_MCT_ISOC_PRIORITY} - IN PLATFORM_POWER_POLICY PlatformPowerPolicy; ///< The platform's desired power policy - ///< @BldCfgItem{BLDCFG_PLATFORM_POWER_POLICY_MODE} -} PERFORMANCE_PROFILE; - -/// Platform settings that describe the voltage regulator modules of the system. -/// Many power management settings are dependent upon the characteristics of the -/// on-board voltage regulator module (VRM). The host environment needs to provide -/// these to specify how the system is to be configured. -typedef struct { - IN UINT32 CurrentLimit; ///< Vrm Current Limit. - ///< @BldCfgItem{BLDCFG_VRM_CURRENT_LIMIT} - ///< @BldCfgItem{BLDCFG_VRM_NB_CURRENT_LIMIT} - IN UINT32 LowPowerThreshold; ///< Vrm Low Power Threshold. - ///< @BldCfgItem{BLDCFG_VRM_LOW_POWER_THRESHOLD} - ///< @BldCfgItem{BLDCFG_VRM_NB_LOW_POWER_THRESHOLD} - IN UINT32 SlewRate; ///< Vrm Slew Rate. - ///< @BldCfgItem{BLDCFG_VRM_SLEW_RATE} - ///< @BldCfgItem{BLDCFG_VRM_NB_SLEW_RATE} - IN UINT32 AdditionalDelay; ///< Vrm Additional Delay. - ///< @BldCfgItem{BLDCFG_VRM_ADDITIONAL_DELAY} - ///< @BldCfgItem{BLDCFG_VRM_NB_ADDITIONAL_DELAY} - IN BOOLEAN HiSpeedEnable; ///< Select high speed VRM. - ///< @BldCfgItem{BLDCFG_VRM_HIGH_SPEED_ENABLE} - ///< @BldCfgItem{BLDCFG_VRM_NB_HIGH_SPEED_ENABLE} - IN UINT32 InrushCurrentLimit; ///< Vrm Inrush Current Limit. - ///< @BldCfgItem{BLDCFG_VRM_INRUSH_CURRENT_LIMIT} - ///< @BldCfgItem{BLDCFG_VRM_NB_INRUSH_CURRENT_LIMIT} -} PLATFORM_VRM_CONFIGURATION; - -/// The VRM types to characterize. -typedef enum { - CoreVrm, ///< VDD plane. - NbVrm, ///< VDDNB plane. - MaxVrmType ///< Not a valid VRM type, use for limit checking. -} PLATFORM_VRM_TYPE; - - -/// Build Option/Configuration Boolean Structure. -typedef struct { - IN AMD_CODE_HEADER VersionString; ///< AMD embedded code version string - - //Build Option Area - IN BOOLEAN OptionUDimms; ///< @ref BLDOPT_REMOVE_UDIMMS_SUPPORT "BLDOPT_REMOVE_UDIMMS_SUPPORT" - IN BOOLEAN OptionRDimms; ///< @ref BLDOPT_REMOVE_RDIMMS_SUPPORT "BLDOPT_REMOVE_RDIMMS_SUPPORT" - IN BOOLEAN OptionLrDimms; ///< @ref BLDOPT_REMOVE_LRDIMMS_SUPPORT "BLDOPT_REMOVE_LRDIMMS_SUPPORT" - IN BOOLEAN OptionEcc; ///< @ref BLDOPT_REMOVE_ECC_SUPPORT "BLDOPT_REMOVE_ECC_SUPPORT" - IN BOOLEAN OptionBankInterleave; ///< @ref BLDOPT_REMOVE_BANK_INTERLEAVE "BLDOPT_REMOVE_BANK_INTERLEAVE" - IN BOOLEAN OptionDctInterleave; ///< @ref BLDOPT_REMOVE_DCT_INTERLEAVE "BLDOPT_REMOVE_DCT_INTERLEAVE" - IN BOOLEAN OptionNodeInterleave; ///< @ref BLDOPT_REMOVE_NODE_INTERLEAVE "BLDOPT_REMOVE_NODE_INTERLEAVE" - IN BOOLEAN OptionParallelTraining; ///< @ref BLDOPT_REMOVE_PARALLEL_TRAINING "BLDOPT_REMOVE_PARALLEL_TRAINING" - IN BOOLEAN OptionOnlineSpare; ///< @ref BLDOPT_REMOVE_ONLINE_SPARE_SUPPORT "BLDOPT_REMOVE_ONLINE_SPARE_SUPPORT" - IN BOOLEAN OptionMemRestore; ///< @ref BLDOPT_REMOVE_MEM_RESTORE_SUPPORT "BLDOPT_REMOVE_MEM_RESTORE_SUPPORT" - IN BOOLEAN OptionMultisocket; ///< @ref BLDOPT_REMOVE_MULTISOCKET_SUPPORT "BLDOPT_REMOVE_MULTISOCKET_SUPPORT" - IN BOOLEAN OptionAcpiPstates; ///< @ref BLDOPT_REMOVE_ACPI_PSTATES "BLDOPT_REMOVE_ACPI_PSTATES" - IN BOOLEAN OptionSrat; ///< @ref BLDOPT_REMOVE_SRAT "BLDOPT_REMOVE_SRAT" - IN BOOLEAN OptionSlit; ///< @ref BLDOPT_REMOVE_SLIT "BLDOPT_REMOVE_SLIT" - IN BOOLEAN OptionWhea; ///< @ref BLDOPT_REMOVE_WHEA "BLDOPT_REMOVE_WHEA" - IN BOOLEAN OptionDmi; ///< @ref BLDOPT_REMOVE_DMI "BLDOPT_REMOVE_DMI" - IN BOOLEAN OptionEarlySamples; ///< @ref BLDOPT_REMOVE_EARLY_SAMPLES "BLDOPT_REMOVE_EARLY_SAMPLES" - IN BOOLEAN OptionAddrToCsTranslator; ///< ADDR_TO_CS_TRANSLATOR - - //Build Configuration Area - IN UINT64 CfgPciMmioAddress; ///< Pci Mmio Base Address to use for PCI Config accesses. - ///< Build-time customizable only - @BldCfgItem{BLDCFG_PCI_MMIO_BASE} - IN UINT32 CfgPciMmioSize; ///< Pci Mmio region Size. - ///< Build-time customizable only - @BldCfgItem{BLDCFG_PCI_MMIO_SIZE} - IN PLATFORM_VRM_CONFIGURATION CfgPlatVrmCfg[MaxVrmType]; ///< Several configuration settings for the voltage regulator modules. - IN UINT32 CfgPlatNumIoApics; ///< The number of IO APICS for the platform. - IN UINT32 CfgMemInitPstate; ///< Memory Init Pstate. - IN PLATFORM_C1E_MODES CfgPlatformC1eMode; ///< Select the C1e Mode that will used. - IN UINT32 CfgPlatformC1eOpData; ///< An IO port or additional C1e setup data, depends on C1e mode. - IN UINT32 CfgPlatformC1eOpData1; ///< An IO port or additional C1e setup data, depends on C1e mode. - IN UINT32 CfgPlatformC1eOpData2; ///< An IO port or additional C1e setup data, depends on C1e mode. - IN UINT32 CfgPlatformC1eOpData3; ///< An IO port or additional C1e setup data, depends on C1e mode. - IN PLATFORM_CSTATE_MODES CfgPlatformCStateMode; ///< Select the C-State Mode that will used. - IN UINT32 CfgPlatformCStateOpData; ///< An IO port or additional C-State setup data, depends on C-State mode. - IN UINT16 CfgPlatformCStateIoBaseAddress; ///< Specifies I/O ports that can be used to allow CPU to enter CStates - IN PLATFORM_CPB_MODES CfgPlatformCpbMode; ///< Enable or disable core performance boost - IN UINT32 CfgCoreLevelingMode; ///< Apply any downcoring or core count leveling as specified. - IN PERFORMANCE_PROFILE CfgPerformanceProfile; ///< The platform's control flow mode and platform performance settings. - IN CPU_HT_DEEMPHASIS_LEVEL *CfgPlatformDeemphasisList; ///< Deemphasis levels for the platform's HT links. - - IN UINT32 CfgAmdPlatformType; ///< Designate the platform as a Server, Desktop, or Mobile. - IN UINT32 CfgAmdPstateCapValue; ///< Amd pstate ceiling enabling deck - - IN MEMORY_BUS_SPEED CfgMemoryBusFrequencyLimit; ///< Memory Bus Frequency Limit. - ///< Build-time customizable only - @BldCfgItem{BLDCFG_MEMORY_BUS_FREQUENCY_LIMIT} - IN BOOLEAN CfgMemoryModeUnganged; ///< Memory Mode Unganged. - ///< Build-time customizable only - @BldCfgItem{BLDCFG_MEMORY_MODE_UNGANGED} - IN BOOLEAN CfgMemoryQuadRankCapable; ///< Memory Quad Rank Capable. - ///< Build-time customizable only - @BldCfgItem{BLDCFG_MEMORY_QUAD_RANK_CAPABLE} - IN QUANDRANK_TYPE CfgMemoryQuadrankType; ///< Memory Quadrank Type. - ///< Build-time customizable only - @BldCfgItem{BLDCFG_MEMORY_QUADRANK_TYPE} - IN BOOLEAN CfgMemoryRDimmCapable; ///< Memory RDIMM Capable. - IN BOOLEAN CfgMemoryLRDimmCapable; ///< Memory LRDIMM Capable. - IN BOOLEAN CfgMemoryUDimmCapable; ///< Memory UDIMM Capable. - IN BOOLEAN CfgMemorySODimmCapable; ///< Memory SODimm Capable. - ///< Build-time customizable only - @BldCfgItem{BLDCFG_MEMORY_SODIMM_CAPABLE} - IN BOOLEAN CfgLimitMemoryToBelow1Tb; ///< Limit memory address space to below 1TB - IN BOOLEAN CfgMemoryEnableBankInterleaving; ///< Memory Enable Bank Interleaving. - IN BOOLEAN CfgMemoryEnableNodeInterleaving; ///< Memory Enable Node Interleaving. - IN BOOLEAN CfgMemoryChannelInterleaving; ///< Memory Channel Interleaving. - IN BOOLEAN CfgMemoryPowerDown; ///< Memory Power Down. - IN POWER_DOWN_MODE CfgPowerDownMode; ///< Power Down Mode. - IN BOOLEAN CfgOnlineSpare; ///< Online Spare. - IN BOOLEAN CfgMemoryParityEnable; ///< Memory Parity Enable. - IN BOOLEAN CfgBankSwizzle; ///< Bank Swizzle. - IN USER_MEMORY_TIMING_MODE CfgTimingModeSelect; ///< Timing Mode Select. - IN MEMORY_BUS_SPEED CfgMemoryClockSelect; ///< Memory Clock Select. - IN BOOLEAN CfgDqsTrainingControl; ///< Dqs Training Control. - ///< Build-time customizable only - @BldCfgItem{BLDCFG_DQS_TRAINING_CONTROL} - IN BOOLEAN CfgIgnoreSpdChecksum; ///< Ignore Spd Checksum. - ///< Build-time customizable only - @BldCfgItem{BLDCFG_IGNORE_SPD_CHECKSUM} - IN BOOLEAN CfgUseBurstMode; ///< Use Burst Mode. - ///< Build-time customizable only - @BldCfgItem{BLDCFG_USE_BURST_MODE} - IN BOOLEAN CfgMemoryAllClocksOn; ///< Memory All Clocks On. - ///< Build-time customizable only - @BldCfgItem{BLDCFG_MEMORY_ALL_CLOCKS_ON} - IN BOOLEAN CfgEnableEccFeature; ///< Enable ECC Feature. - IN BOOLEAN CfgEccRedirection; ///< ECC Redirection. - ///< Build-time customizable only - @BldCfgItem{BLDCFG_ECC_REDIRECTION} - IN UINT16 CfgScrubDramRate; ///< Scrub Dram Rate. - ///< Build-time customizable only - @BldCfgItem{BLDCFG_SCRUB_DRAM_RATE} - IN UINT16 CfgScrubL2Rate; ///< Scrub L2Rate. - ///< Build-time customizable only - @BldCfgItem{BLDCFG_SCRUB_L2_RATE} - IN UINT16 CfgScrubL3Rate; ///< Scrub L3Rate. - ///< Build-time customizable only - @BldCfgItem{BLDCFG_SCRUB_L3_RATE} - IN UINT16 CfgScrubIcRate; ///< Scrub Ic Rate. - ///< Build-time customizable only - @BldCfgItem{BLDCFG_SCRUB_IC_RATE} - IN UINT16 CfgScrubDcRate; ///< Scrub Dc Rate. - ///< Build-time customizable only - @BldCfgItem{BLDCFG_SCRUB_DC_RATE} - IN BOOLEAN CfgEccSyncFlood; ///< ECC Sync Flood. - ///< Build-time customizable only - @BldCfgItem{BLDCFG_ECC_SYNC_FLOOD} - IN UINT16 CfgEccSymbolSize; ///< ECC Symbol Size. - ///< Build-time customizable only - @BldCfgItem{BLDCFG_ECC_SYMBOL_SIZE} - IN UINT64 CfgHeapDramAddress; ///< Heap contents will be temporarily stored in this address during the transition. - ///< Build-time customizable only - @BldCfgItem{BLDCFG_HEAP_DRAM_ADDRESS} - IN BOOLEAN CfgNodeMem1GBAlign; ///< Node Mem 1GB boundary Alignment - IN BOOLEAN CfgS3LateRestore; ///< S3 Late Restore - IN BOOLEAN CfgAcpiPstateIndependent; ///< PSD method dependent/Independent - IN AP_MTRR_SETTINGS *CfgApMtrrSettingsList; ///< The AP's MTRR settings before final halt - ///< Build-time customizable only - @BldCfgItem{BLDCFG_AP_MTRR_SETTINGS_LIST} - IN UMA_MODE CfgUmaMode; ///< Uma Mode - IN UINT32 CfgUmaSize; ///< Uma Size [31:0]=Addr[47:16] - IN BOOLEAN CfgUmaAbove4G; ///< Uma Above 4G Support - IN UMA_ALIGNMENT CfgUmaAlignment; ///< Uma alignment - IN BOOLEAN CfgProcessorScopeInSb; ///< ACPI Processor Object in \\_SB scope - IN CHAR8 CfgProcessorScopeName0; ///< OEM specific 1st character of processor scope name. - IN CHAR8 CfgProcessorScopeName1; ///< OEM specific 2nd character of processor scope name. - IN UINT8 CfgGnbHdAudio; ///< GNB HD Audio - IN UINT8 CfgAbmSupport; ///< Abm Support - IN UINT8 CfgDynamicRefreshRate; ///< DRR Dynamic Refresh Rate - IN UINT16 CfgLcdBackLightControl; ///< LCD Backlight Control - IN UINT8 CfgGnb3dStereoPinIndex; ///< 3D Stereo Pin ID. - IN UINT32 CfgTempPcieMmioBaseAddress; ///< Temp pcie MMIO base Address - ///< Build-time customizable only - @BldCfgItem{BLDCFG_TEMP_PCIE_MMIO_BASE_ADDRESS} - IN UINT32 CfgGnbIGPUSSID; ///< Gnb internal GPU SSID - ///< Build-time customizable only - @BldCfgItem{BLDCFG_IGPU_SUBSYSTEM_ID} - IN UINT32 CfgGnbHDAudioSSID; ///< Gnb HD Audio SSID - ///< Build-time customizable only - @BldCfgItem{BLDCFG_IGPU_HD_AUDIO_SUBSYSTEM_ID} - IN UINT32 CfgGnbPcieSSID; ///< Gnb PCIe SSID - ///< Build-time customizable only - @BldCfgItem{BLFCFG_APU_PCIE_PORTS_SUBSYSTEM_ID} - IN UINT16 CfgLvdsSpreadSpectrum; ///< Lvds Spread Spectrum - ///< Build-time customizable only - @BldCfgItem{BLDCFG_GFX_LVDS_SPREAD_SPECTRUM} - IN UINT16 CfgLvdsSpreadSpectrumRate; ///< Lvds Spread Spectrum Rate - ///< Build-time customizable only - @BldCfgItem{BLDCFG_GFX_LVDS_SPREAD_SPECTRUM_RATE} - - IN UINT16 CfgSmbus0BaseAddress; ///< SMBUS0 Controller Base Address - IN UINT16 CfgSmbus1BaseAddress; ///< SMBUS1 Controller Base Address - IN UINT16 CfgSioPmeBaseAddress; ///< I/O base address for LPC I/O target range - IN UINT16 CfgAcpiPm1EvtBlkAddr; ///< I/O base address of ACPI power management Event Block - IN UINT16 CfgAcpiPm1CntBlkAddr; ///< I/O base address of ACPI power management Control Block - IN UINT16 CfgAcpiPmTmrBlkAddr; ///< I/O base address of ACPI power management Timer Block - IN UINT16 CfgCpuControlBlkAddr; ///< I/O base address of ACPI power management CPU Control Block - IN UINT16 CfgAcpiGpe0BlkAddr; ///< I/O base address of ACPI power management General Purpose Event Block - IN UINT16 CfgSmiCmdPortAddr; ///< I/O base address of ACPI SMI Command Block - IN UINT16 CfgAcpiPmaCntBlkAddr; ///< I/O base address of ACPI power management additional control block - IN UINT32 CfgGecShadowRomBase; ///< 32-bit base address to the GEC shadow ROM - IN UINT32 CfgWatchDogTimerBase; ///< Watchdog Timer base address - IN UINT32 CfgSpiRomBaseAddress; ///< Base address for the SPI ROM controller - IN UINT32 CfgHpetBaseAddress; ///< HPET MMIO base address - IN UINT32 CfgAzaliaSsid; ///< Subsystem ID of HD Audio controller - IN UINT32 CfgSmbusSsid; ///< Subsystem ID of SMBUS controller - IN UINT32 CfgIdeSsid; ///< Subsystem ID of IDE controller - IN UINT32 CfgSataAhciSsid; ///< Subsystem ID of SATA controller in AHCI mode - IN UINT32 CfgSataIdeSsid; ///< Subsystem ID of SATA controller in IDE mode - IN UINT32 CfgSataRaid5Ssid; ///< Subsystem ID of SATA controller in RAID5 mode - IN UINT32 CfgSataRaidSsid; ///< Subsystem ID of SATA controller in RAID mode - IN UINT32 CfgEhciSsid; ///< Subsystem ID of EHCI - IN UINT32 CfgOhciSsid; ///< Subsystem ID of OHCI - IN UINT32 CfgLpcSsid; ///< Subsystem ID of LPC ISA Bridge - IN GPP_LINKMODE CfgFchGppLinkConfig; ///< GPP link configuration - IN BOOLEAN CfgFchGppPort0Present; ///< Is FCH GPP port 0 present - IN BOOLEAN CfgFchGppPort1Present; ///< Is FCH GPP port 1 present - IN BOOLEAN CfgFchGppPort2Present; ///< Is FCH GPP port 2 present - IN BOOLEAN CfgFchGppPort3Present; ///< Is FCH GPP port 3 present - IN BOOLEAN CfgFchGppPort0HotPlug; ///< Is FCH GPP port 0 hotplug capable - IN BOOLEAN CfgFchGppPort1HotPlug; ///< Is FCH GPP port 1 hotplug capable - IN BOOLEAN CfgFchGppPort2HotPlug; ///< Is FCH GPP port 2 hotplug capable - IN BOOLEAN CfgFchGppPort3HotPlug; ///< Is FCH GPP port 3 hotplug capable - - IN BOOLEAN CfgIommuSupport; ///< IOMMU support - IN UINT8 CfgLvdsPowerOnSeqDigonToDe; ///< Panel initialization timing - IN UINT8 CfgLvdsPowerOnSeqDeToVaryBl; ///< Panel initialization timing - IN UINT8 CfgLvdsPowerOnSeqDeToDigon; ///< Panel initialization timing - IN UINT8 CfgLvdsPowerOnSeqVaryBlToDe; ///< Panel initialization timing - IN UINT8 CfgLvdsPowerOnSeqOnToOffDelay; ///< Panel initialization timing - IN UINT8 CfgLvdsPowerOnSeqVaryBlToBlon; ///< Panel initialization timing - IN UINT8 CfgLvdsPowerOnSeqBlonToVaryBl; ///< Panel initialization timing - IN UINT16 CfgLvdsMaxPixelClockFreq; ///< The maximum pixel clock frequency supported - IN UINT32 CfgLcdBitDepthControlValue; ///< The LCD bit depth control settings - IN UINT8 CfgLvds24bbpPanelMode; ///< The LVDS 24 BBP mode - IN UINT16 CfgPcieRefClkSpreadSpectrum; ///< PCIe Reference Clock Spread Spectrum - ///< Build-time customizable only - @BldCfgItem{BLDCFG_PCIE_REFCLK_SPREAD_SPECTRUM} - IN BOOLEAN Reserved; ///< reserved... -} BUILD_OPT_CFG; - -/// A structure containing platform specific operational characteristics. This -/// structure is initially populated by the initializer with a copy of the same -/// structure that was created at build time using the build configuration controls. -typedef struct _PLATFORM_CONFIGURATION { - IN PERFORMANCE_PROFILE PlatformProfile; ///< Several configuration settings for the processor. - IN CPU_HT_DEEMPHASIS_LEVEL *PlatformDeemphasisList; ///< Deemphasis levels for the platform's HT links. - ///< @BldCfgItem{BLDCFG_PLATFORM_DEEMPHASIS_LIST}. - ///< @n @e Examples: See @ref DeemphasisExamples "Deemphasis List Examples". - IN UINT8 CoreLevelingMode; ///< Indicates how to balance the number of cores per processor. - ///< @BldCfgItem{BLDCFG_CORE_LEVELING_MODE} - IN PLATFORM_C1E_MODES C1eMode; ///< Specifies the method of C1e enablement - Disabled, HW, or message based. - ///< @BldCfgItem{BLDCFG_PLATFORM_C1E_MODE} - IN UINT32 C1ePlatformData; ///< If C1eMode is HW, specifies the P_LVL3 I/O port of the platform. - ///< @BldCfgItem{BLDCFG_PLATFORM_C1E_OPDATA} - IN UINT32 C1ePlatformData1; ///< If C1eMode is SW, specifies the address of chipset's SMI command port. - ///< @BldCfgItem{BLDCFG_PLATFORM_C1E_OPDATA1} - IN UINT32 C1ePlatformData2; ///< If C1eMode is SW, specifies the unique number used by the SMI handler to identify SMI source. - ///< @BldCfgItem{BLDCFG_PLATFORM_C1E_OPDATA2} - IN UINT32 C1ePlatformData3; ///< If C1eMode is Auto, specifies the P_LVL3 I/O port of the platform for HW C1e - ///< @BldCfgItem{BLDCFG_PLATFORM_C1E_OPDATA3} - IN PLATFORM_CSTATE_MODES CStateMode; ///< Specifies the method of C-State enablement - Disabled, or C6. - ///< @BldCfgItem{BLDCFG_PLATFORM_CSTATE_MODE} - IN UINT32 CStatePlatformData; ///< This element specifies some pertinent data needed for the operation of the Cstate feature - ///< If CStateMode is CStateModeC6, this item is reserved - ///< @BldCfgItem{BLDCFG_PLATFORM_CSTATE_OPDATA} - IN UINT16 CStateIoBaseAddress; ///< This item specifies a free block of 8 consecutive bytes of I/O ports that - ///< can be used to allow the CPU to enter Cstates. - ///< @BldCfgItem{BLDCFG_PLATFORM_CSTATE_IO_BASE_ADDRESS} - IN PLATFORM_CPB_MODES CpbMode; ///< Specifies the method of core performance boost enablement - Disabled, or Auto. - ///< @BldCfgItem{BLDCFG_PLATFORM_CPB_MODE} - IN BOOLEAN UserOptionDmi; ///< When set to TRUE, the DMI data table is generated. - IN BOOLEAN UserOptionPState; ///< When set to TRUE, the PState data tables are generated. - IN BOOLEAN UserOptionSrat; ///< When set to TRUE, the SRAT data table is generated. - IN BOOLEAN UserOptionSlit; ///< When set to TRUE, the SLIT data table is generated. - IN BOOLEAN UserOptionWhea; ///< When set to TRUE, the WHEA data table is generated. - IN UINT32 PowerCeiling; ///< P-State Ceiling Enabling Deck - Max power milli-watts. - IN BOOLEAN ForcePstateIndependent; ///< P-State _PSD independence or dependence. - ///< @BldCfgItem{BLDCFG_FORCE_INDEPENDENT_PSD_OBJECT} - IN UINT32 NumberOfIoApics; ///< Number of I/O APICs in the system - ///< @BldCfgItem{BLDCFG_PLATFORM_NUM_IO_APICS} - IN PLATFORM_VRM_CONFIGURATION VrmProperties[MaxVrmType]; ///< Several configuration settings for the voltage regulator modules. - IN BOOLEAN ProcessorScopeInSb; ///< ACPI Processor Object in \\_SB scope - ///< @BldCfgItem{BLDCFG_PROCESSOR_SCOPE_IN_SB} - IN CHAR8 ProcessorScopeName0; ///< OEM specific 1st character of processor scope name. - ///< @BldCfgItem{BLDCFG_PROCESSOR_SCOPE_NAME0} - IN CHAR8 ProcessorScopeName1; ///< OEM specific 2nd character of processor scope name. - ///< @BldCfgItem{BLDCFG_PROCESSOR_SCOPE_NAME1} - IN UINT8 GnbHdAudio; ///< Control GFX HD Audio controller(Used for HDMI and DP display output), - ///< essentially it enables function 1 of graphics device. - ///< @li 0 = HD Audio disable - ///< @li 1 = HD Audio enable - ///< @BldCfgItem{BLDCFG_CFG_GNB_HD_AUDIO} - IN UINT8 AbmSupport; ///< Automatic adjust LVDS/eDP Back light level support.It is - ///< characteristic specific to display panel which used by platform design. - ///< @li 0 = ABM support disabled - ///< @li 1 = ABM support enabled - ///< @BldCfgItem{BLDCFG_CFG_ABM_SUPPORT} - IN UINT8 DynamicRefreshRate; ///< Adjust refresh rate on LVDS/eDP. - ///< @BldCfgItem{BLDCFG_CFG_DYNAMIC_REFRESH_RATE} - IN UINT16 LcdBackLightControl; ///< The PWM frequency to LCD backlight control. - ///< If equal to 0 backlight not controlled by iGPU - ///< @BldCfgItem{BLDCFG_CFG_LCD_BACK_LIGHT_CONTROL} -} PLATFORM_CONFIGURATION; - - -/********************************************************************** - * Structures for: AmdInitLate - **********************************************************************/ -#define PROC_VERSION_LENGTH 48 -#define MAX_DIMMS_PER_SOCKET 16 - -/* Interface Parameter Structures */ -/// DMI Type4 - Processor ID -typedef struct { - OUT UINT32 ProcIdLsd; ///< Lower half of 64b ID - OUT UINT32 ProcIdMsd; ///< Upper half of 64b ID -} TYPE4_PROC_ID; - -/// DMI Type 4 - Processor information -typedef struct { - OUT UINT8 T4ProcType; ///< CPU Type - OUT UINT8 T4ProcFamily; ///< Family 1 - OUT TYPE4_PROC_ID T4ProcId; ///< Id - OUT UINT8 T4Voltage; ///< Voltage - OUT UINT16 T4ExternalClock; ///< External clock - OUT UINT16 T4MaxSpeed; ///< Max speed - OUT UINT16 T4CurrentSpeed; ///< Current speed - OUT UINT8 T4Status; ///< Status - OUT UINT8 T4ProcUpgrade; ///< Up grade - OUT UINT8 T4CoreCount; ///< Core count - OUT UINT8 T4CoreEnabled; ///< Core Enable - OUT UINT8 T4ThreadCount; ///< Thread count - OUT UINT16 T4ProcCharacteristics; ///< Characteristics - OUT UINT16 T4ProcFamily2; ///< Family 2 - OUT CHAR8 T4ProcVersion[PROC_VERSION_LENGTH]; ///< Cpu version -} TYPE4_DMI_INFO; - -/// DMI Type 7 - Cache information -typedef struct _TYPE7_DMI_INFO { - OUT UINT16 T7CacheCfg; ///< Cache cfg - OUT UINT16 T7MaxCacheSize; ///< Max size - OUT UINT16 T7InstallSize; ///< Install size - OUT UINT16 T7SupportedSramType; ///< Supported Sram Type - OUT UINT16 T7CurrentSramType; ///< Current type - OUT UINT8 T7CacheSpeed; ///< Speed - OUT UINT8 T7ErrorCorrectionType; ///< ECC type - OUT UINT8 T7SystemCacheType; ///< Cache type - OUT UINT8 T7Associativity; ///< Associativity -} TYPE7_DMI_INFO; - -/// DMI Type 16 offset 04h - Location -typedef enum { - OtherLocation = 0x01, ///< Assign 01 to Other - UnknownLocation, ///< Assign 02 to Unknown - SystemboardOrMotherboard, ///< Assign 03 to systemboard or motherboard - IsaAddonCard, ///< Assign 04 to ISA add-on card - EisaAddonCard, ///< Assign 05 to EISA add-on card - PciAddonCard, ///< Assign 06 to PCI add-on card - McaAddonCard, ///< Assign 07 to MCA add-on card - PcmciaAddonCard, ///< Assign 08 to PCMCIA add-on card - ProprietaryAddonCard, ///< Assign 09 to proprietary add-on card - NuBus, ///< Assign 0A to NuBus - Pc98C20AddonCard, ///< Assign 0A0 to PC-98/C20 add-on card - Pc98C24AddonCard, ///< Assign 0A1 to PC-98/C24 add-on card - Pc98EAddoncard, ///< Assign 0A2 to PC-98/E add-on card - Pc98LocalBusAddonCard ///< Assign 0A3 to PC-98/Local bus add-on card -} DMI_T16_LOCATION; - -/// DMI Type 16 offset 05h - Memory Error Correction -typedef enum { - OtherUse = 0x01, ///< Assign 01 to Other - UnknownUse, ///< Assign 02 to Unknown - SystemMemory, ///< Assign 03 to system memory - VideoMemory, ///< Assign 04 to video memory - FlashMemory, ///< Assign 05 to flash memory - NonvolatileRam, ///< Assign 06 to non-volatile RAM - CacheMemory ///< Assign 07 to cache memory -} DMI_T16_USE; - -/// DMI Type 16 offset 07h - Maximum Capacity -typedef enum { - Dmi16OtherErrCorrection = 0x01, ///< Assign 01 to Other - Dmi16UnknownErrCorrection, ///< Assign 02 to Unknown - Dmi16NoneErrCorrection, ///< Assign 03 to None - Dmi16Parity, ///< Assign 04 to parity - Dmi16SingleBitEcc, ///< Assign 05 to Single-bit ECC - Dmi16MultiBitEcc, ///< Assign 06 to Multi-bit ECC - Dmi16Crc ///< Assign 07 to CRC -} DMI_T16_ERROR_CORRECTION; - -/// DMI Type 16 - Physical Memory Array -typedef struct { - OUT DMI_T16_LOCATION Location; ///< The physical location of the Memory Array, - ///< whether on the system board or an add-in board. - OUT DMI_T16_USE Use; ///< Identifies the function for which the array - ///< is used. - OUT DMI_T16_ERROR_CORRECTION MemoryErrorCorrection; ///< The primary hardware error correction or - ///< detection method supported by this memory array. - OUT UINT32 MaximumCapacity; ///< The maximum memory capacity, in kilobytes, - ///< for the array. - OUT UINT16 NumberOfMemoryDevices; ///< The number of slots or sockets available - ///< for memory devices in this array. -} TYPE16_DMI_INFO; - -/// DMI Type 17 offset 0Eh - Form Factor -typedef enum { - OtherFormFactor = 0x01, ///< Assign 01 to Other - UnknowFormFactor, ///< Assign 02 to Unknown - SimmFormFactor, ///< Assign 03 to SIMM - SipFormFactor, ///< Assign 04 to SIP - ChipFormFactor, ///< Assign 05 to Chip - DipFormFactor, ///< Assign 06 to DIP - ZipFormFactor, ///< Assign 07 to ZIP - ProprietaryCardFormFactor, ///< Assign 08 to Proprietary Card - DimmFormFactorFormFactor, ///< Assign 09 to DIMM - TsopFormFactor, ///< Assign 10 to TSOP - RowOfChipsFormFactor, ///< Assign 11 to Row of chips - RimmFormFactor, ///< Assign 12 to RIMM - SodimmFormFactor, ///< Assign 13 to SODIMM - SrimmFormFactor, ///< Assign 14 to SRIMM - FbDimmFormFactor ///< Assign 15 to FB-DIMM -} DMI_T17_FORM_FACTOR; - -/// DMI Type 17 offset 12h - Memory Type -typedef enum { - OtherMemType = 0x01, ///< Assign 01 to Other - UnknownMemType, ///< Assign 02 to Unknown - DramMemType, ///< Assign 03 to DRAM - EdramMemType, ///< Assign 04 to EDRAM - VramMemType, ///< Assign 05 to VRAM - SramMemType, ///< Assign 06 to SRAM - RamMemType, ///< Assign 07 to RAM - RomMemType, ///< Assign 08 to ROM - FlashMemType, ///< Assign 09 to Flash - EepromMemType, ///< Assign 10 to EEPROM - FepromMemType, ///< Assign 11 to FEPROM - EpromMemType, ///< Assign 12 to EPROM - CdramMemType, ///< Assign 13 to CDRAM - ThreeDramMemType, ///< Assign 14 to 3DRAM - SdramMemType, ///< Assign 15 to SDRAM - SgramMemType, ///< Assign 16 to SGRAM - RdramMemType, ///< Assign 17 to RDRAM - DdrMemType, ///< Assign 18 to DDR - Ddr2MemType, ///< Assign 19 to DDR2 - Ddr2FbdimmMemType, ///< Assign 20 to DDR2 FB-DIMM - Ddr3MemType = 0x18, ///< Assign 24 to DDR3 - Fbd2MemType ///< Assign 25 to FBD2 -} DMI_T17_MEMORY_TYPE; - -/// DMI Type 17 offset 13h - Type Detail -typedef struct { - OUT UINT16 Reserved1:1; ///< Reserved - OUT UINT16 Other:1; ///< Other - OUT UINT16 Unknown:1; ///< Unknown - OUT UINT16 FastPaged:1; ///< Fast-Paged - OUT UINT16 StaticColumn:1; ///< Static column - OUT UINT16 PseudoStatic:1; ///< Pseudo-static - OUT UINT16 Rambus:1; ///< RAMBUS - OUT UINT16 Synchronous:1; ///< Synchronous - OUT UINT16 Cmos:1; ///< CMOS - OUT UINT16 Edo:1; ///< EDO - OUT UINT16 WindowDram:1; ///< Window DRAM - OUT UINT16 CacheDram:1; ///< Cache Dram - OUT UINT16 NonVolatile:1; ///< Non-volatile - OUT UINT16 Reserved2:3; ///< Reserved -} DMI_T17_TYPE_DETAIL; - -/// DMI Type 17 - Memory Device -typedef struct { - OUT UINT16 TotalWidth; ///< Total Width, in bits, of this memory device, including any check or error-correction bits. - OUT UINT16 DataWidth; ///< Data Width, in bits, of this memory device. - OUT UINT16 MemorySize; ///< The size of the memory device. - OUT DMI_T17_FORM_FACTOR FormFactor; ///< The implementation form factor for this memory device. - OUT UINT8 DeviceSet; ///< Identifies when the Memory Device is one of a set of - ///< Memory Devices that must be populated with all devices of - ///< the same type and size, and the set to which this device belongs. - OUT CHAR8 DeviceLocator[8]; ///< The string number of the string that identifies the physically labeled socket or board position where the memory device is located. - OUT CHAR8 BankLocator[10]; ///< The string number of the string that identifies the physically labeled bank where the memory device is located. - OUT DMI_T17_MEMORY_TYPE MemoryType; ///< The type of memory used in this device. - OUT DMI_T17_TYPE_DETAIL TypeDetail; ///< Additional detail on the memory device type - OUT UINT16 Speed; ///< Identifies the speed of the device, in megahertz (MHz). - OUT UINT64 ManufacturerIdCode; ///< Manufacturer ID code. - OUT CHAR8 SerialNumber[9]; ///< Serial Number. - OUT CHAR8 PartNumber[19]; ///< Part Number. - OUT UINT8 Attributes; ///< Bits 7-4: Reserved, Bits 3-0: rank. - OUT UINT32 ExtSize; ///< Extended Size. - OUT UINT16 ConfigSpeed; ///< Configured memory clock speed -} TYPE17_DMI_INFO; - -/// Memory DMI Type 17 and 20 - for memory use -typedef struct { - OUT UINT16 TotalWidth; ///< Total Width, in bits, of this memory device, including any check or error-correction bits. - OUT UINT16 DataWidth; ///< Data Width, in bits, of this memory device. - OUT UINT16 MemorySize; ///< The size of the memory device. - OUT DMI_T17_FORM_FACTOR FormFactor; ///< The implementation form factor for this memory device. - OUT UINT8 DeviceLocator; ///< The string number of the string that identifies the physically labeled socket or board position where the memory device is located. - OUT UINT8 BankLocator; ///< The string number of the string that identifies the physically labeled bank where the memory device is located. - OUT UINT16 Speed; ///< Identifies the speed of the device, in megahertz (MHz). - OUT UINT64 ManufacturerIdCode; ///< Manufacturer ID code. - OUT UINT8 SerialNumber[4]; ///< Serial Number. - OUT UINT8 PartNumber[18]; ///< Part Number. - OUT UINT8 Attributes; ///< Bits 7-4: Reserved, Bits 3-0: rank. - OUT UINT32 ExtSize; ///< Extended Size. - OUT UINT8 Socket:3; ///< Socket ID - OUT UINT8 Channel:2; ///< Channel ID - OUT UINT8 Dimm:2; ///< DIMM ID - OUT UINT8 DimmPresent:1; ///< Dimm Present - OUT UINT32 StartingAddr; ///< The physical address, in kilobytes, of a range - ///< of memory mapped to the referenced Memory Device. - OUT UINT32 EndingAddr; ///< The handle, or instance number, associated with - ///< the Memory Device structure to which this address - ///< range is mapped. - OUT UINT16 ConfigSpeed; ///< Configured memory clock speed -} MEM_DMI_INFO; - -/// DMI Type 19 - Memory Array Mapped Address -typedef struct { - OUT UINT32 StartingAddr; ///< The physical address, in kilobytes, - ///< of a range of memory mapped to the - ///< specified physical memory array. - OUT UINT32 EndingAddr; ///< The physical ending address of the - ///< last kilobyte of a range of addresses - ///< mapped to the specified physical memory array. - OUT UINT16 MemoryArrayHandle; ///< The handle, or instance number, associated - ///< with the physical memory array to which this - ///< address range is mapped. - OUT UINT8 PartitionWidth; ///< Identifies the number of memory devices that - ///< form a single row of memory for the address - ///< partition defined by this structure. -} TYPE19_DMI_INFO; - -///DMI Type 20 - Memory Device Mapped Address -typedef struct { - OUT UINT32 StartingAddr; ///< The physical address, in kilobytes, of a range - ///< of memory mapped to the referenced Memory Device. - OUT UINT32 EndingAddr; ///< The handle, or instance number, associated with - ///< the Memory Device structure to which this address - ///< range is mapped. - OUT UINT16 MemoryDeviceHandle; ///< The handle, or instance number, associated with - ///< the Memory Device structure to which this address - ///< range is mapped. - OUT UINT16 MemoryArrayMappedAddressHandle; ///< The handle, or instance number, associated - ///< with the Memory Array Mapped Address structure to - ///< which this device address range is mapped. - OUT UINT8 PartitionRowPosition; ///< Identifies the position of the referenced Memory - ///< Device in a row of the address partition. - OUT UINT8 InterleavePosition; ///< The position of the referenced Memory Device in - ///< an interleave. - OUT UINT8 InterleavedDataDepth; ///< The maximum number of consecutive rows from the - ///< referenced Memory Device that are accessed in a - ///< single interleaved transfer. -} TYPE20_DMI_INFO; - -/// Collection of pointers to the DMI records -typedef struct { - OUT TYPE4_DMI_INFO T4[MAX_SOCKETS_SUPPORTED]; ///< Type 4 struc - OUT TYPE7_DMI_INFO T7L1[MAX_SOCKETS_SUPPORTED]; ///< Type 7 struc 1 - OUT TYPE7_DMI_INFO T7L2[MAX_SOCKETS_SUPPORTED]; ///< Type 7 struc 2 - OUT TYPE7_DMI_INFO T7L3[MAX_SOCKETS_SUPPORTED]; ///< Type 7 struc 3 - OUT TYPE16_DMI_INFO T16; ///< Type 16 struc - OUT TYPE17_DMI_INFO T17[MAX_SOCKETS_SUPPORTED][MAX_CHANNELS_PER_SOCKET][MAX_DIMMS_PER_CHANNEL]; ///< Type 17 struc - OUT TYPE19_DMI_INFO T19; ///< Type 19 struc - OUT TYPE20_DMI_INFO T20[MAX_SOCKETS_SUPPORTED][MAX_CHANNELS_PER_SOCKET][MAX_DIMMS_PER_CHANNEL]; ///< Type 20 struc -} DMI_INFO; - -/********************************************************************** - * Interface call: AllocateExecutionCache - **********************************************************************/ -#define MAX_CACHE_REGIONS 3 - -/// AllocateExecutionCache sub param structure for cached memory region -typedef struct { - IN OUT UINT32 ExeCacheStartAddr; ///< Start address - IN OUT UINT32 ExeCacheSize; ///< Size -} EXECUTION_CACHE_REGION; - -/********************************************************************** - * Interface call: AmdGetAvailableExeCacheSize - **********************************************************************/ -/// Get available Cache remain -typedef struct { - IN OUT AMD_CONFIG_PARAMS StdHeader; ///< Standard configuration header - OUT UINT32 AvailableExeCacheSize; ///< Remain size -} AMD_GET_EXE_SIZE_PARAMS; - -AGESA_STATUS -AmdGetAvailableExeCacheSize ( - IN OUT AMD_GET_EXE_SIZE_PARAMS *AmdGetExeSizeParams - ); - -/// Selection type for core leveling -typedef enum { - CORE_LEVEL_LOWEST, ///< Level to lowest common denominator - CORE_LEVEL_TWO, ///< Level to 2 cores - CORE_LEVEL_POWER_OF_TWO, ///< Level to 1,2,4 or 8 - CORE_LEVEL_NONE, ///< Do no leveling - CORE_LEVEL_COMPUTE_UNIT, ///< Level cores to one core per compute unit - CORE_LEVEL_ONE, ///< Level to 1 core - CORE_LEVEL_THREE, ///< Level to 3 cores - CORE_LEVEL_FOUR, ///< Level to 4 cores - CORE_LEVEL_FIVE, ///< Level to 5 cores - CORE_LEVEL_SIX, ///< Level to 6 cores - CORE_LEVEL_SEVEN, ///< Level to 7 cores - CORE_LEVEL_EIGHT, ///< Level to 8 cores - CORE_LEVEL_NINE, ///< Level to 9 cores - CORE_LEVEL_TEN, ///< Level to 10 cores - CORE_LEVEL_ELEVEN, ///< Level to 11 cores - CORE_LEVEL_TWELVE, ///< Level to 12 cores - CORE_LEVEL_THIRTEEN, ///< Level to 13 cores - CORE_LEVEL_FOURTEEN, ///< Level to 14 cores - CORE_LEVEL_FIFTEEN, ///< Level to 15 cores - CoreLevelModeMax ///< Used for bounds checking -} CORE_LEVELING_TYPE; - - - - - -/************************************************************************ - * - * AGESA Basic Level interface structure definition and function prototypes - * - ***********************************************************************/ - -/********************************************************************** - * Interface call: AmdCreateStruct - **********************************************************************/ -AGESA_STATUS -AmdCreateStruct ( - IN OUT AMD_INTERFACE_PARAMS *InterfaceParams - ); - -/********************************************************************** - * Interface call: AmdReleaseStruct - **********************************************************************/ -AGESA_STATUS -AmdReleaseStruct ( - IN OUT AMD_INTERFACE_PARAMS *InterfaceParams - ); - -/********************************************************************** - * Interface call: AmdInitReset - **********************************************************************/ -/// AmdInitReset param structure -typedef struct { - IN AMD_CONFIG_PARAMS StdHeader; ///< Standard configuration header - IN EXECUTION_CACHE_REGION CacheRegion[3]; ///< The cached memory region - IN AMD_HT_RESET_INTERFACE HtConfig; ///< The interface for Ht Recovery - IN FCH_RESET_INTERFACE FchInterface; ///< Interface for FCH configuration -} AMD_RESET_PARAMS; - -AGESA_STATUS -AmdInitReset ( - IN OUT AMD_RESET_PARAMS *ResetParams - ); - - -/********************************************************************** - * Interface call: AmdInitEarly - **********************************************************************/ -/// InitEarly param structure -/// -/// Provide defaults or customizations to each service performed in AmdInitEarly. -/// -typedef struct { - IN OUT AMD_CONFIG_PARAMS StdHeader; ///< Standard configuration header - IN EXECUTION_CACHE_REGION CacheRegion[3]; ///< Execution Map Interface - IN PLATFORM_CONFIGURATION PlatformConfig; ///< platform operational characteristics. - IN AMD_HT_INTERFACE HtConfig; ///< HyperTransport Interface - IN GNB_CONFIGURATION GnbConfig; ///< GNB configuration -} AMD_EARLY_PARAMS; - -AGESA_STATUS -AmdInitEarly ( - IN OUT AMD_EARLY_PARAMS *EarlyParams - ); - - -/********************************************************************** - * Interface call: AmdInitPost - **********************************************************************/ -/// AmdInitPost param structure -typedef struct { - IN OUT AMD_CONFIG_PARAMS StdHeader; ///< Standard configuration header - IN PLATFORM_CONFIGURATION PlatformConfig; ///< platform operational characteristics. - IN MEM_PARAMETER_STRUCT MemConfig; ///< Memory post param -} AMD_POST_PARAMS; - -AGESA_STATUS -AmdInitPost ( - IN OUT AMD_POST_PARAMS *PostParams ///< Amd Cpu init param - ); - - -/********************************************************************** - * Interface call: AmdInitEnv - **********************************************************************/ -/// AmdInitEnv param structure -typedef struct { - IN OUT AMD_CONFIG_PARAMS StdHeader; ///< Standard configuration header - IN PLATFORM_CONFIGURATION PlatformConfig; ///< platform operational characteristics. - IN GNB_ENV_CONFIGURATION GnbEnvConfiguration; ///< platform operational characteristics. - IN FCH_INTERFACE FchInterface; ///< FCH configuration -} AMD_ENV_PARAMS; - -AGESA_STATUS -AmdInitEnv ( - IN OUT AMD_ENV_PARAMS *EnvParams - ); - - -/********************************************************************** - * Interface call: AmdInitMid - **********************************************************************/ -/// AmdInitMid param structure -typedef struct { - IN OUT AMD_CONFIG_PARAMS StdHeader; ///< Standard configuration header - IN PLATFORM_CONFIGURATION PlatformConfig; ///< platform operational characteristics. - IN FCH_INTERFACE FchInterface; ///< FCH configuration -} AMD_MID_PARAMS; - -AGESA_STATUS -AmdInitMid ( - IN OUT AMD_MID_PARAMS *MidParams - ); - - -/********************************************************************** - * Interface call: AmdInitLate - **********************************************************************/ -/// AmdInitLate param structure -typedef struct { - IN OUT AMD_CONFIG_PARAMS StdHeader; ///< Standard configuration header - IN PLATFORM_CONFIGURATION PlatformConfig; ///< platform operational characteristics. - IN IOMMU_EXCLUSION_RANGE_DESCRIPTOR *IvrsExclusionRangeList; ///< Pointer to array of exclusion ranges - OUT DMI_INFO *DmiTable; ///< DMI Interface - OUT VOID *AcpiPState; ///< Acpi Pstate SSDT Table - OUT VOID *AcpiSrat; ///< SRAT Table - OUT VOID *AcpiSlit; ///< SLIT Table - OUT VOID *AcpiWheaMce; ///< WHEA MCE Table - OUT VOID *AcpiWheaCmc; ///< WHEA CMC Table - OUT VOID *AcpiAlib; ///< ACPI SSDT table with ALIB implementation - OUT VOID *AcpiIvrs; ///< IOMMU ACPI IVRS(I/O Virtualization Reporting Structure) table - OUT VOID *AcpiCrat; ///< Component Resource Affinity Table table - OUT VOID *AcpiCdit; ///< Component Locality Distance Information table -} AMD_LATE_PARAMS; - -AGESA_STATUS -AmdInitLate ( - IN OUT AMD_LATE_PARAMS *LateParams - ); - -/********************************************************************** - * Interface call: AmdInitRecovery - **********************************************************************/ -/// CPU Recovery Parameters -typedef struct { - IN OUT AMD_CONFIG_PARAMS StdHeader; ///< Standard configuration header - IN PLATFORM_CONFIGURATION PlatformConfig; ///< platform operational characteristics. -} AMD_CPU_RECOVERY_PARAMS; - -/// AmdInitRecovery param structure -typedef struct { - IN OUT AMD_CONFIG_PARAMS StdHeader; ///< Standard configuration header - IN MEM_PARAMETER_STRUCT MemConfig; ///< Memory post param - IN EXECUTION_CACHE_REGION CacheRegion[3]; ///< The cached memory region. And the max cache region is 3 - IN AMD_CPU_RECOVERY_PARAMS CpuRecoveryParams; ///< Params for CPU related recovery init. -} AMD_RECOVERY_PARAMS; - -AGESA_STATUS -AmdInitRecovery ( - IN OUT AMD_RECOVERY_PARAMS *RecoveryParams - ); - -/********************************************************************** - * Interface call: AmdInitResume - **********************************************************************/ -/// AmdInitResume param structure -typedef struct { - IN OUT AMD_CONFIG_PARAMS StdHeader; ///< Standard configuration header - IN PLATFORM_CONFIGURATION PlatformConfig; ///< Platform operational characteristics - IN AMD_S3_PARAMS S3DataBlock; ///< Save state data -} AMD_RESUME_PARAMS; - -AGESA_STATUS -AmdInitResume ( - IN AMD_RESUME_PARAMS *ResumeParams - ); - - -/********************************************************************** - * Interface call: AmdS3LateRestore - **********************************************************************/ -/// AmdS3LateRestore param structure -typedef struct { - IN OUT AMD_CONFIG_PARAMS StdHeader; ///< Standard configuration header - IN PLATFORM_CONFIGURATION PlatformConfig; ///< platform operational characteristics. - IN AMD_S3_PARAMS S3DataBlock; ///< Save state data -} AMD_S3LATE_PARAMS; - -AGESA_STATUS -AmdS3LateRestore ( - IN OUT AMD_S3LATE_PARAMS *S3LateParams - ); - - -/********************************************************************** - * Interface call: AmdS3Save - **********************************************************************/ -/// AmdS3Save param structure -typedef struct { - IN OUT AMD_CONFIG_PARAMS StdHeader; ///< Standard configuration header - IN PLATFORM_CONFIGURATION PlatformConfig; ///< platform operational characteristics. - OUT AMD_S3_PARAMS S3DataBlock; ///< Standard header - IN FCH_INTERFACE FchInterface; ///< FCH configuration -} AMD_S3SAVE_PARAMS; - -AGESA_STATUS -AmdS3Save ( - IN OUT AMD_S3SAVE_PARAMS *AmdS3SaveParams - ); - - -/********************************************************************** - * Interface call: AmdLateRunApTask - **********************************************************************/ -/** - * Entry point for AP tasking. - */ -AGESA_STATUS -AmdLateRunApTask ( - IN AP_EXE_PARAMS *AmdApExeParams -); - -// -// General Services API -// - -/********************************************************************** - * Interface service call: AmdGetApicId - **********************************************************************/ -/// Request the APIC ID of a particular core. - -typedef struct { - IN AMD_CONFIG_PARAMS StdHeader; ///< Standard configuration header - IN UINT8 Socket; ///< The Core's Socket. - IN UINT8 Core; ///< The Core id. - OUT BOOLEAN IsPresent; ///< The Core is present, and ApicAddress is valid. - OUT UINT8 ApicAddress; ///< The Core's APIC ID. -} AMD_APIC_PARAMS; - -/** - * Get a specified Core's APIC ID. - */ -AGESA_STATUS -AmdGetApicId ( - IN OUT AMD_APIC_PARAMS *AmdParamApic -); - -/********************************************************************** - * Interface service call: AmdGetPciAddress - **********************************************************************/ -/// Request the PCI Address of a Processor Module (that is, its Northbridge) - -typedef struct { - IN AMD_CONFIG_PARAMS StdHeader; ///< Standard configuration header - IN UINT8 Socket; ///< The Processor's socket - IN UINT8 Module; ///< The Module in that Processor - OUT BOOLEAN IsPresent; ///< The Core is present, and PciAddress is valid. - OUT PCI_ADDR PciAddress; ///< The Processor's PCI Config Space address (Function 0, Register 0) -} AMD_GET_PCI_PARAMS; - -/** - * Get Processor Module's PCI Config Space address. - */ -AGESA_STATUS -AmdGetPciAddress ( - IN OUT AMD_GET_PCI_PARAMS *AmdParamGetPci -); - -/********************************************************************** - * Interface service call: AmdIdentifyCore - **********************************************************************/ -/// Request the identity (Socket, Module, Core) of the current Processor Core - -typedef struct { - IN AMD_CONFIG_PARAMS StdHeader; ///< Standard configuration header - OUT UINT8 Socket; ///< The current Core's Socket - OUT UINT8 Module; ///< The current Core's Processor Module - OUT UINT8 Core; ///< The current Core's core id. -} AMD_IDENTIFY_PARAMS; - -/** - * "Who am I" for the current running core. - */ -AGESA_STATUS -AmdIdentifyCore ( - IN OUT AMD_IDENTIFY_PARAMS *AmdParamIdentify -); - -/********************************************************************** - * Interface service call: AmdReadEventLog - **********************************************************************/ -/// An Event Log Entry. -typedef struct { - IN AMD_CONFIG_PARAMS StdHeader; ///< Standard configuration header - OUT UINT32 EventClass; ///< The severity of this event, matches AGESA_STATUS. - OUT UINT32 EventInfo; ///< The unique event identifier, zero means "no event". - OUT UINT32 DataParam1; ///< Data specific to the Event. - OUT UINT32 DataParam2; ///< Data specific to the Event. - OUT UINT32 DataParam3; ///< Data specific to the Event. - OUT UINT32 DataParam4; ///< Data specific to the Event. -} EVENT_PARAMS; - -/** - * Read an Event from the Event Log. - */ -AGESA_STATUS -AmdReadEventLog ( - IN EVENT_PARAMS *Event -); - -/********************************************************************** - * Interface service call: AmdIdentifyDimm - **********************************************************************/ -/// Request the identity of dimm from system address - -typedef struct { - IN OUT AMD_CONFIG_PARAMS StdHeader; ///< Standard configuration header - IN UINT64 MemoryAddress; ///< System Address that needs to be translated to dimm identification. - OUT UINT8 SocketId; ///< The socket on which the targeted address locates. - OUT UINT8 MemChannelId; ///< The channel on which the targeted address locates. - OUT UINT8 DimmId; ///< The dimm on which the targeted address locates. -} AMD_IDENTIFY_DIMM; - -/** - * Get the dimm identification for the address. - */ -AGESA_STATUS -AmdIdentifyDimm ( - IN OUT AMD_IDENTIFY_DIMM *AmdDimmIdentify -); - -/// Data structure for the Mapping Item between Unified ID for IDS Setup Option -/// and the option value. -/// -typedef struct { - IN UINT16 IdsNvId; ///< Unified ID for IDS Setup Option. - OUT UINT16 IdsNvValue; ///< The value of IDS Setup Option. -} IDS_NV_ITEM; - -/// Data Structure for IDS CallOut Function -typedef struct { - IN AMD_CONFIG_PARAMS StdHeader; ///< Standard configuration header - IN IDS_NV_ITEM *IdsNvPtr; ///< Memory Pointer of IDS NV Table - IN OUT UINTN Reserved; ///< reserved -} IDS_CALLOUT_STRUCT; - -AGESA_STATUS -AmdIdsRunApTaskLate ( - IN AP_EXE_PARAMS *AmdApExeParams - ); - - -#define AGESA_IDS_DFT_VAL 0xFFFF ///< Default value of every uninitlized NV item, the action for it will be ignored -#define AGESA_IDS_NV_END 0xFFFF ///< Flag specify end of option structure -/// WARNING: Don't change the comment below, it used as signature for script -/// AGESA IDS NV ID Definitions -typedef enum { - AGESA_IDS_EXT_ID_START = 0x0000,///< 0x0000 specify the start of external NV id - - AGESA_IDS_NV_UCODE, ///< 0x0001 Enable or disable microcode patching - - AGESA_IDS_NV_TARGET_PSTATE, ///< 0x0002 Set the P-state required to be activated - AGESA_IDS_NV_POSTPSTATE, ///< 0x0003 Set the P-state required to be activated through POST - - AGESA_IDS_NV_BANK_INTERLEAVE, ///< 0x0004 Enable or disable Bank Interleave - AGESA_IDS_NV_CHANNEL_INTERLEAVE, ///< 0x0005 Enable or disable Channel Interleave - AGESA_IDS_NV_NODE_INTERLEAVE, ///< 0x0006 Enable or disable Node Interleave - AGESA_IDS_NV_MEMHOLE, ///< 0x0007 Enables or disable memory hole - - AGESA_IDS_NV_SCRUB_REDIRECTION, ///< 0x0008 Enable or disable a write to dram with corrected data - AGESA_IDS_NV_DRAM_SCRUB, ///< 0x0009 Set the rate of background scrubbing for DRAM - AGESA_IDS_NV_DCACHE_SCRUB, ///< 0x000A Set the rate of background scrubbing for the DCache. - AGESA_IDS_NV_L2_SCRUB, ///< 0x000B Set the rate of background scrubbing for the L2 cache - AGESA_IDS_NV_L3_SCRUB, ///< 0x000C Set the rate of background scrubbing for the L3 cache - AGESA_IDS_NV_ICACHE_SCRUB, ///< 0x000D Set the rate of background scrubbing for the Icache - AGESA_IDS_NV_SYNC_ON_ECC_ERROR, ///< 0x000E Enable or disable the sync flood on un-correctable ECC error - AGESA_IDS_NV_ECC_SYMBOL_SIZE, ///< 0x000F Set ECC symbol size - - AGESA_IDS_NV_ALL_MEMCLKS, ///< 0x0010 Enable or disable all memory clocks enable - AGESA_IDS_NV_DCT_GANGING_MODE, ///< 0x0011 Set the Ganged mode - AGESA_IDS_NV_DRAM_BURST_LENGTH32, ///< 0x0012 Set the DRAM Burst Length 32 - AGESA_IDS_NV_MEMORY_POWER_DOWN, ///< 0x0013 Enable or disable Memory power down mode - AGESA_IDS_NV_MEMORY_POWER_DOWN_MODE, ///< 0x0014 Set the Memory power down mode - AGESA_IDS_NV_DLL_SHUT_DOWN, ///< 0x0015 Enable or disable DLLShutdown - AGESA_IDS_NV_ONLINE_SPARE, ///< 0x0016 Enable or disable the Dram controller to designate a DIMM bank as a spare for logical swap - - AGESA_IDS_NV_HT_ASSIST, ///< 0x0017 Enable or Disable HT Assist - AGESA_IDS_NV_ATMMODE, ///< 0x0018 Enable or Disable ATM mode - - AGESA_IDS_NV_HDTOUT, ///< 0x0019 Enable or disable HDTOUT feature - - AGESA_IDS_NV_HTLINKSOCKET, ///< 0x001A HT Link Socket - AGESA_IDS_NV_HTLINKPORT, ///< 0x001B HT Link Port - AGESA_IDS_NV_HTLINKFREQ, ///< 0x001C HT Link Frequency - AGESA_IDS_NV_HTLINKWIDTHIN, ///< 0x001D HT Link In Width - AGESA_IDS_NV_HTLINKWIDTHOUT, ///< 0x001E HT Link Out Width - - AGESA_IDS_NV_GNBHDAUDIOEN, ///< 0x001F Enable or disable GNB HD Audio - - AGESA_IDS_NV_CPB_EN, ///< 0x0020 Core Performance Boost - - AGESA_IDS_NV_HTC_EN, ///< 0x0021 HTC Enable - AGESA_IDS_NV_HTC_OVERRIDE, ///< 0x0022 HTC Override - AGESA_IDS_NV_HTC_PSTATE_LIMIT, ///< 0x0023 HTC P-state limit select - AGESA_IDS_NV_HTC_TEMP_HYS, ///< 0x0024 HTC Temperature Hysteresis - AGESA_IDS_NV_HTC_ACT_TEMP, ///< 0x0025 HTC Activation Temp - - AGESA_IDS_NV_POWER_POLICY, ///< 0x0026 Select Platform Power Policy - AGESA_IDS_EXT_ID_END, ///< 0x0027 specify the end of external NV ID -} IDS_EX_NV_ID; - - -#define IDS_NUM_EXT_NV_ITEM (AGESA_IDS_EXT_ID_END - AGESA_IDS_EXT_ID_START + 1) - -#endif // _AGESA_H_ diff --git a/src/vendorcode/amd/agesa/f12/AMD.h b/src/vendorcode/amd/agesa/f12/AMD.h deleted file mode 100644 index 31c0b347a0..0000000000 --- a/src/vendorcode/amd/agesa/f12/AMD.h +++ /dev/null @@ -1,486 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * Agesa structures and definitions - * - * Contains AMD AGESA core interface - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: Include - * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $ - */ -/*****************************************************************************/ -/* - ***************************************************************************** - * - * Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * *************************************************************************** - * - */ - - -#ifndef _AMD_H_ -#define _AMD_H_ - -#define AGESA_REVISION "Arch2008" -#define AGESA_ID "AGESA" - -#define Int16FromChar(a,b) ((a) << 0 | (b) << 8) -#define Int32FromChar(a,b,c,d) ((a) << 0 | (b) << 8 | (c) << 16 | (d) << 24) -// -// -// AGESA Types and Definitions -// -// -#define LAST_ENTRY 0xFFFFFFFF -#define IMAGE_SIGNATURE Int32FromChar ('$', 'A', 'M', 'D') -#define IOCF8 0xCF8 -#define IOCFC 0xCFC - -/// The return status for all AGESA public services. -/// -/// Services return the most severe status of any logged event. Status other than SUCCESS, UNSUPPORTED, and BOUNDS_CHK -/// will have log entries with more detail. -/// -typedef enum { - AGESA_SUCCESS = 0, ///< The service completed normally. Info may be logged. - AGESA_UNSUPPORTED, ///< The dispatcher or create struct had an unimplemented function requested. - ///< Not logged. - AGESA_BOUNDS_CHK, ///< A dynamic parameter was out of range and the service was not provided. - ///< Example, memory address not installed, heap buffer handle not found. - ///< Not Logged. - // AGESA_STATUS of greater severity (the ones below this line), always have a log entry available. - AGESA_ALERT, ///< An observed condition, but no loss of function. - ///< See log. Example, HT CRC. - AGESA_WARNING, ///< Possible or minor loss of function. See Log. - AGESA_ERROR, ///< Significant loss of function, boot may be possible. See Log. - AGESA_CRITICAL, ///< Continue boot only to notify user. See Log. - AGESA_FATAL, ///< Halt booting. See Log, however Fatal errors pertaining to heap problems - ///< may not be able to reliably produce log events. - AgesaStatusMax ///< Not a status, for limit checking. -} AGESA_STATUS; - -/// For checking whether a status is at or above the mandatory log level. -#define AGESA_STATUS_LOG_LEVEL AGESA_ALERT - -/** - * Callout method to the host environment. - * - * Callout using a dispatch with appropriate thunk layer, which is determined by the host environment. - * - * @param[in] Function The specific callout function being invoked. - * @param[in] FcnData Function specific data item. - * @param[in,out] ConfigPtr Reference to Callout params. - */ -typedef AGESA_STATUS (*CALLOUT_ENTRY) ( - IN UINT32 Function, - IN UINTN FcnData, - IN OUT VOID *ConfigPtr - ); - -typedef AGESA_STATUS (*IMAGE_ENTRY) (VOID *ConfigPtr); -typedef AGESA_STATUS (*MODULE_ENTRY) (VOID *ConfigPtr); - -///This allocation type is used by the AmdCreateStruct entry point -typedef enum { - PreMemHeap = 0, ///< Create heap in cache. - PostMemDram, ///< Create heap in memory. - ByHost ///< Create heap by Host. -} ALLOCATION_METHOD; - -/// These width descriptors are used by the library function, and others, to specify the data size -typedef enum ACCESS_WIDTH { - AccessWidth8 = 1, ///< Access width is 8 bits. - AccessWidth16, ///< Access width is 16 bits. - AccessWidth32, ///< Access width is 32 bits. - AccessWidth64, ///< Access width is 64 bits. - - AccessS3SaveWidth8 = 0x81, ///< Save 8 bits data. - AccessS3SaveWidth16, ///< Save 16 bits data. - AccessS3SaveWidth32, ///< Save 32 bits data. - AccessS3SaveWidth64, ///< Save 64 bits data. -} ACCESS_WIDTH; - -/// AGESA struct name -typedef enum { - // AGESA BASIC FUNCTIONS - AMD_INIT_RECOVERY = 0x00020000, ///< AmdInitRecovery entry point handle - AMD_CREATE_STRUCT, ///< AmdCreateStruct handle - AMD_INIT_EARLY, ///< AmdInitEarly entry point handle - AMD_INIT_ENV, ///< AmdInitEnv entry point handle - AMD_INIT_LATE, ///< AmdInitLate entry point handle - AMD_INIT_MID, ///< AmdInitMid entry point handle - AMD_INIT_POST, ///< AmdInitPost entry point handle - AMD_INIT_RESET, ///< AmdInitReset entry point handle - AMD_INIT_RESUME, ///< AmdInitResume entry point handle - AMD_RELEASE_STRUCT, ///< AmdReleaseStruct handle - AMD_S3LATE_RESTORE, ///< AmdS3LateRestore entry point handle - AMD_S3_SAVE, ///< AmdS3Save entry point handle - AMD_GET_APIC_ID, ///< AmdGetApicId entry point handle - AMD_GET_PCI_ADDRESS, ///< AmdGetPciAddress entry point handle - AMD_IDENTIFY_CORE, ///< AmdIdentifyCore general service handle - AMD_READ_EVENT_LOG, ///< AmdReadEventLog general service handle - AMD_GET_EXECACHE_SIZE, ///< AmdGetAvailableExeCacheSize general service handle - AMD_LATE_RUN_AP_TASK, ///< AmdLateRunApTask entry point handle - AMD_IDENTIFY_DIMMS, ///< AmdIdentifyDimm general service handle - AMD_GET_2D_DATA_EYE, ///< AmdGet2DDataEye general service handle - AMD_S3FINAL_RESTORE, ///< AmdS3FinalRestore entry point handle - AMD_INIT_RTB ///< AmdInitRtb entry point handle -} AGESA_STRUCT_NAME; - - /* ResetType constant values */ -#define WARM_RESET_WHENEVER 1 -#define COLD_RESET_WHENEVER 2 -#define WARM_RESET_IMMEDIATELY 3 -#define COLD_RESET_IMMEDIATELY 4 - - -// AGESA Structures - -/// The standard header for all AGESA services. -/// For internal AGESA naming conventions, see @ref amdconfigparamname . -typedef struct { - IN UINT32 ImageBasePtr; ///< The AGESA Image base address. - IN UINT32 Func; ///< The service desired - IN UINT32 AltImageBasePtr; ///< Alternate Image location - IN CALLOUT_ENTRY CalloutPtr; ///< For Callout from AGESA - IN UINT8 HeapStatus; ///< For heap status from boot time slide. - IN UINT64 HeapBasePtr; ///< Location of the heap - IN OUT UINT8 Reserved[7]; ///< This space is reserved for future use. -} AMD_CONFIG_PARAMS; - - -/// Create Struct Interface. -typedef struct { - IN AMD_CONFIG_PARAMS StdHeader; ///< Standard configuration header - IN AGESA_STRUCT_NAME AgesaFunctionName; ///< The service to init - IN ALLOCATION_METHOD AllocationMethod; ///< How to handle buffer allocation - IN OUT UINT32 NewStructSize; ///< The size of the allocated data, in for ByHost, else out only. - IN OUT VOID *NewStructPtr; ///< The struct for the service. - ///< The struct to init for ByHost allocation, - ///< the initialized struct on return. -} AMD_INTERFACE_PARAMS; - -#define FUNC_0 0 // bit-placed for PCI address creation -#define FUNC_1 1 -#define FUNC_2 2 -#define FUNC_3 3 -#define FUNC_4 4 -#define FUNC_5 5 -#define FUNC_6 6 -#define FUNC_7 7 - -/// AGESA Binary module header structure -typedef struct { - IN UINT32 Signature; ///< Binary Signature - IN CHAR8 CreatorID[8]; ///< 8 characters ID - IN CHAR8 Version[12]; ///< 12 characters version - IN UINT32 ModuleInfoOffset; ///< Offset of module - IN UINT32 EntryPointAddress; ///< Entry address - IN UINT32 ImageBase; ///< Image base - IN UINT32 RelocTableOffset; ///< Relocate Table offset - IN UINT32 ImageSize; ///< Size - IN UINT16 Checksum; ///< Checksum - IN UINT8 ImageType; ///< Type - IN UINT8 V_Reserved; ///< Reserved -} AMD_IMAGE_HEADER; -/// AGESA Binary module header structure -typedef struct _AMD_MODULE_HEADER { - IN UINT32 ModuleHeaderSignature; ///< Module signature - IN CHAR8 ModuleIdentifier[8]; ///< 8 characters ID - IN CHAR8 ModuleVersion[12]; ///< 12 characters version - IN VOID *ModuleDispatcher; ///< A pointer point to dispatcher - IN struct _AMD_MODULE_HEADER *NextBlock; ///< Next module header link -} AMD_MODULE_HEADER; - -// AMD_CODE_HEADER Signatures. -#define AGESA_CODE_SIGNATURE {'!', '!', 'A', 'G', 'E', 'S', 'A', ' '} -#define CIMXNB_CODE_SIGNATURE {'!', '!', 'C', 'I', 'M', 'X', 'N', 'B'} -#define CIMXSB_CODE_SIGNATURE {'!', '!', 'C', 'I', 'M', 'X', 'S', 'B'} - -/// AGESA_CODE_SIGNATURE -typedef struct { - IN CHAR8 Signature[8]; ///< code header Signature - IN CHAR8 ComponentName[8]; ///< 8 character name of the code module - IN CHAR8 Version[12]; ///< 12 character version string - IN CHAR8 TerminatorNull; ///< null terminated string - IN CHAR8 VerReserved[7]; ///< reserved space -} AMD_CODE_HEADER; - -/// Extended PCI address format -typedef struct { - IN OUT UINT32 Register:12; ///< Register offset - IN OUT UINT32 Function:3; ///< Function number - IN OUT UINT32 Device:5; ///< Device number - IN OUT UINT32 Bus:8; ///< Bus number - IN OUT UINT32 Segment:4; ///< Segment -} EXT_PCI_ADDR; - -/// Union type for PCI address -typedef union _PCI_ADDR { - IN UINT32 AddressValue; ///< Formal address - IN EXT_PCI_ADDR Address; ///< Extended address -} PCI_ADDR; - -// SBDFO - Segment Bus Device Function Offset -// 31:28 Segment (4-bits) -// 27:20 Bus (8-bits) -// 19:15 Device (5-bits) -// 14:12 Function(3-bits) -// 11:00 Offset (12-bits) - -#define MAKE_SBDFO(Seg, Bus, Dev, Fun, Off) ((((UINT32) (Seg)) << 28) | (((UINT32) (Bus)) << 20) | \ - (((UINT32)(Dev)) << 15) | (((UINT32)(Fun)) << 12) | ((UINT32)(Off))) -#define ILLEGAL_SBDFO 0xFFFFFFFF - -/// CPUID data received registers format -typedef struct { - OUT UINT32 EAX_Reg; ///< CPUID instruction result in EAX - OUT UINT32 EBX_Reg; ///< CPUID instruction result in EBX - OUT UINT32 ECX_Reg; ///< CPUID instruction result in ECX - OUT UINT32 EDX_Reg; ///< CPUID instruction result in EDX -} CPUID_DATA; - -/// HT frequency for external callbacks -typedef enum { - HT_FREQUENCY_200M = 0, ///< HT speed 200 for external callbacks - HT_FREQUENCY_400M = 2, ///< HT speed 400 for external callbacks - HT_FREQUENCY_600M = 4, ///< HT speed 600 for external callbacks - HT_FREQUENCY_800M = 5, ///< HT speed 800 for external callbacks - HT_FREQUENCY_1000M = 6, ///< HT speed 1000 for external callbacks - HT_FREQUENCY_1200M = 7, ///< HT speed 1200 for external callbacks - HT_FREQUENCY_1400M = 8, ///< HT speed 1400 for external callbacks - HT_FREQUENCY_1600M = 9, ///< HT speed 1600 for external callbacks - HT_FREQUENCY_1800M = 10, ///< HT speed 1800 for external callbacks - HT_FREQUENCY_2000M = 11, ///< HT speed 2000 for external callbacks - HT_FREQUENCY_2200M = 12, ///< HT speed 2200 for external callbacks - HT_FREQUENCY_2400M = 13, ///< HT speed 2400 for external callbacks - HT_FREQUENCY_2600M = 14, ///< HT speed 2600 for external callbacks - HT_FREQUENCY_2800M = 17, ///< HT speed 2800 for external callbacks - HT_FREQUENCY_3000M = 18, ///< HT speed 3000 for external callbacks - HT_FREQUENCY_3200M = 19, ///< HT speed 3200 for external callbacks - HT_FREQUENCY_MAX ///< Limit check. -} HT_FREQUENCIES; -// The minimum HT3 frequency -#define HT3_FREQUENCY_MIN HT_FREQUENCY_1200M - -#ifndef BIT0 - #define BIT0 0x0000000000000001ull -#endif -#ifndef BIT1 - #define BIT1 0x0000000000000002ull -#endif -#ifndef BIT2 - #define BIT2 0x0000000000000004ull -#endif -#ifndef BIT3 - #define BIT3 0x0000000000000008ull -#endif -#ifndef BIT4 - #define BIT4 0x0000000000000010ull -#endif -#ifndef BIT5 - #define BIT5 0x0000000000000020ull -#endif -#ifndef BIT6 - #define BIT6 0x0000000000000040ull -#endif -#ifndef BIT7 - #define BIT7 0x0000000000000080ull -#endif -#ifndef BIT8 - #define BIT8 0x0000000000000100ull -#endif -#ifndef BIT9 - #define BIT9 0x0000000000000200ull -#endif -#ifndef BIT10 - #define BIT10 0x0000000000000400ull -#endif -#ifndef BIT11 - #define BIT11 0x0000000000000800ull -#endif -#ifndef BIT12 - #define BIT12 0x0000000000001000ull -#endif -#ifndef BIT13 - #define BIT13 0x0000000000002000ull -#endif -#ifndef BIT14 - #define BIT14 0x0000000000004000ull -#endif -#ifndef BIT15 - #define BIT15 0x0000000000008000ull -#endif -#ifndef BIT16 - #define BIT16 0x0000000000010000ull -#endif -#ifndef BIT17 - #define BIT17 0x0000000000020000ull -#endif -#ifndef BIT18 - #define BIT18 0x0000000000040000ull -#endif -#ifndef BIT19 - #define BIT19 0x0000000000080000ull -#endif -#ifndef BIT20 - #define BIT20 0x0000000000100000ull -#endif -#ifndef BIT21 - #define BIT21 0x0000000000200000ull -#endif -#ifndef BIT22 - #define BIT22 0x0000000000400000ull -#endif -#ifndef BIT23 - #define BIT23 0x0000000000800000ull -#endif -#ifndef BIT24 - #define BIT24 0x0000000001000000ull -#endif -#ifndef BIT25 - #define BIT25 0x0000000002000000ull -#endif -#ifndef BIT26 - #define BIT26 0x0000000004000000ull -#endif -#ifndef BIT27 - #define BIT27 0x0000000008000000ull -#endif -#ifndef BIT28 - #define BIT28 0x0000000010000000ull -#endif -#ifndef BIT29 - #define BIT29 0x0000000020000000ull -#endif -#ifndef BIT30 - #define BIT30 0x0000000040000000ull -#endif -#ifndef BIT31 - #define BIT31 0x0000000080000000ull -#endif -#ifndef BIT32 - #define BIT32 0x0000000100000000ull -#endif -#ifndef BIT33 - #define BIT33 0x0000000200000000ull -#endif -#ifndef BIT34 - #define BIT34 0x0000000400000000ull -#endif -#ifndef BIT35 - #define BIT35 0x0000000800000000ull -#endif -#ifndef BIT36 - #define BIT36 0x0000001000000000ull -#endif -#ifndef BIT37 - #define BIT37 0x0000002000000000ull -#endif -#ifndef BIT38 - #define BIT38 0x0000004000000000ull -#endif -#ifndef BIT39 - #define BIT39 0x0000008000000000ull -#endif -#ifndef BIT40 - #define BIT40 0x0000010000000000ull -#endif -#ifndef BIT41 - #define BIT41 0x0000020000000000ull -#endif -#ifndef BIT42 - #define BIT42 0x0000040000000000ull -#endif -#ifndef BIT43 - #define BIT43 0x0000080000000000ull -#endif -#ifndef BIT44 - #define BIT44 0x0000100000000000ull -#endif -#ifndef BIT45 - #define BIT45 0x0000200000000000ull -#endif -#ifndef BIT46 - #define BIT46 0x0000400000000000ull -#endif -#ifndef BIT47 - #define BIT47 0x0000800000000000ull -#endif -#ifndef BIT48 - #define BIT48 0x0001000000000000ull -#endif -#ifndef BIT49 - #define BIT49 0x0002000000000000ull -#endif -#ifndef BIT50 - #define BIT50 0x0004000000000000ull -#endif -#ifndef BIT51 - #define BIT51 0x0008000000000000ull -#endif -#ifndef BIT52 - #define BIT52 0x0010000000000000ull -#endif -#ifndef BIT53 - #define BIT53 0x0020000000000000ull -#endif -#ifndef BIT54 - #define BIT54 0x0040000000000000ull -#endif -#ifndef BIT55 - #define BIT55 0x0080000000000000ull -#endif -#ifndef BIT56 - #define BIT56 0x0100000000000000ull -#endif -#ifndef BIT57 - #define BIT57 0x0200000000000000ull -#endif -#ifndef BIT58 - #define BIT58 0x0400000000000000ull -#endif -#ifndef BIT59 - #define BIT59 0x0800000000000000ull -#endif -#ifndef BIT60 - #define BIT60 0x1000000000000000ull -#endif -#ifndef BIT61 - #define BIT61 0x2000000000000000ull -#endif -#ifndef BIT62 - #define BIT62 0x4000000000000000ull -#endif -#ifndef BIT63 - #define BIT63 0x8000000000000000ull -#endif - -#endif // _AMD_H_ diff --git a/src/vendorcode/amd/agesa/f12/Config/OptionC6Install.h b/src/vendorcode/amd/agesa/f12/Config/OptionC6Install.h deleted file mode 100644 index e5c2c8e2ee..0000000000 --- a/src/vendorcode/amd/agesa/f12/Config/OptionC6Install.h +++ /dev/null @@ -1,140 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * Install of build option: C6 C-state - * - * Contains AMD AGESA install macros and test conditions. Output is the - * defaults tables reflecting the User's build options selection. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: Options - * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $ - */ -/***************************************************************************** - * - * Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ***************************************************************************/ - -#ifndef _OPTION_C6_STATE_INSTALL_H_ -#define _OPTION_C6_STATE_INSTALL_H_ - -#include "cpuC6State.h" - -/* This option is designed to be included into the platform solution install - * file. The platform solution install file will define the options status. - * Check to validate the definition - */ -#define OPTION_C6_STATE_FEAT -#define F12_C6_STATE_SUPPORT -#define F14_ON_C6_STATE_SUPPORT -#define F15_OR_C6_STATE_SUPPORT - -#if OPTION_C6_STATE == TRUE - #if (AGESA_ENTRY_INIT_EARLY == TRUE) || (AGESA_ENTRY_INIT_POST == TRUE) || (AGESA_ENTRY_INIT_RESUME == TRUE) || (AGESA_ENTRY_INIT_LATE == TRUE) - #ifdef OPTION_FAMILY12H - #if OPTION_FAMILY12H == TRUE - #if OPTION_FAMILY12H_LN == TRUE - extern CONST CPU_FEATURE_DESCRIPTOR ROMDATA CpuFeatureC6State; - #undef OPTION_C6_STATE_FEAT - #define OPTION_C6_STATE_FEAT &CpuFeatureC6State, - extern CONST C6_FAMILY_SERVICES ROMDATA F12C6Support; - #undef F12_C6_STATE_SUPPORT - #define F12_C6_STATE_SUPPORT {AMD_FAMILY_12_LN, &F12C6Support}, - - #if OPTION_EARLY_SAMPLES == TRUE - extern F_F12_ES_C6_INIT F12C6A0Workaround; - - CONST F12_ES_C6_SUPPORT ROMDATA F12EarlySampleC6Support = - { - F12C6A0Workaround - }; - #else - CONST F12_ES_C6_SUPPORT ROMDATA F12EarlySampleC6Support = - { - (PF_F12_ES_C6_INIT) CommonVoid - }; - #endif - - #endif - #endif - #endif - - #ifdef OPTION_FAMILY14H - #if OPTION_FAMILY14H == TRUE - #if (OPTION_FAMILY14H_ON == TRUE) - extern CONST CPU_FEATURE_DESCRIPTOR ROMDATA CpuFeatureC6State; - #undef OPTION_C6_STATE_FEAT - #define OPTION_C6_STATE_FEAT &CpuFeatureC6State, - extern CONST C6_FAMILY_SERVICES ROMDATA F14OnC6Support; - #undef F14_ON_C6_STATE_SUPPORT - #define F14_ON_C6_STATE_SUPPORT {AMD_FAMILY_14_ON, &F14OnC6Support}, - - CONST F14_ON_ES_C6_SUPPORT ROMDATA F14OnEarlySampleC6Support = - { - (PF_F14_ON_ES_IS_C6_SUPPORTED) CommonVoid, - (PF_F14_ON_ES_C6_INIT) CommonVoid - }; - #endif - #endif - #endif - - #ifdef OPTION_FAMILY15H - #if OPTION_FAMILY15H == TRUE - #if (OPTION_FAMILY15H_OR == TRUE) - extern CONST CPU_FEATURE_DESCRIPTOR ROMDATA CpuFeatureC6State; - #undef OPTION_C6_STATE_FEAT - #define OPTION_C6_STATE_FEAT &CpuFeatureC6State, - extern CONST C6_FAMILY_SERVICES ROMDATA F15OrC6Support; - #undef F15_OR_C6_STATE_SUPPORT - #define F15_OR_C6_STATE_SUPPORT {AMD_FAMILY_15_OR, &F15OrC6Support}, - CONST F15_OR_ES_C6_SUPPORT ROMDATA F15OrEarlySampleC6Support = - { - (PF_F15_OR_ES_IS_C6_SUPPORTED) CommonVoid - }; - #endif - #endif - #endif - #endif -#endif - -CONST CPU_SPECIFIC_SERVICES_XLAT ROMDATA C6FamilyServiceArray[] = -{ - F12_C6_STATE_SUPPORT - F14_ON_C6_STATE_SUPPORT - F15_OR_C6_STATE_SUPPORT - {0, NULL} -}; - -CONST CPU_FAMILY_SUPPORT_TABLE ROMDATA C6FamilyServiceTable = -{ - (sizeof (C6FamilyServiceArray) / sizeof (CPU_SPECIFIC_SERVICES_XLAT)), - &C6FamilyServiceArray[0] -}; - -#endif // _OPTION_C6_STATE_INSTALL_H_ diff --git a/src/vendorcode/amd/agesa/f12/Config/OptionCpbInstall.h b/src/vendorcode/amd/agesa/f12/Config/OptionCpbInstall.h deleted file mode 100644 index 72720063c7..0000000000 --- a/src/vendorcode/amd/agesa/f12/Config/OptionCpbInstall.h +++ /dev/null @@ -1,144 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * Install of build option: Core Performance Boost - * - * Contains AMD AGESA install macros and test conditions. Output is the - * defaults tables reflecting the User's build options selection. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: Options - * @e \$Revision: 46389 $ @e \$Date: 2011-02-01 11:22:49 +0800 (Tue, 01 Feb 2011) $ - */ -/***************************************************************************** - * - * Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ***************************************************************************/ - -#ifndef _OPTION_CPB_INSTALL_H_ -#define _OPTION_CPB_INSTALL_H_ - -#include "cpuCpb.h" - -/* This option is designed to be included into the platform solution install - * file. The platform solution install file will define the options status. - * Check to validate the definition - */ -#define OPTION_CPB_FEAT -#define F10_CPB_SUPPORT -#define F12_CPB_SUPPORT -#define F14_ON_CPB_SUPPORT -#define F15_OR_CPB_SUPPORT - -#if OPTION_CPB == TRUE - #if (AGESA_ENTRY_INIT_EARLY == TRUE) || (AGESA_ENTRY_INIT_LATE == TRUE) || (AGESA_ENTRY_INIT_LATE_RESTORE == TRUE) - // Family 10h - #ifdef OPTION_FAMILY10H - #if OPTION_FAMILY10H == TRUE - #if OPTION_FAMILY10H_PH == TRUE - extern CONST CPU_FEATURE_DESCRIPTOR ROMDATA CpuFeatureCpb; - #undef OPTION_CPB_FEAT - #define OPTION_CPB_FEAT &CpuFeatureCpb, - extern CONST CPB_FAMILY_SERVICES ROMDATA F10CpbSupport; - #undef F10_CPB_SUPPORT - #define F10_CPB_SUPPORT {AMD_FAMILY_10_PH, &F10CpbSupport}, - #endif - #endif - #endif - - // Family 12h - #ifdef OPTION_FAMILY12H - #if OPTION_FAMILY12H == TRUE - #if OPTION_FAMILY12H_LN == TRUE - extern CONST CPU_FEATURE_DESCRIPTOR ROMDATA CpuFeatureCpb; - #undef OPTION_CPB_FEAT - #define OPTION_CPB_FEAT &CpuFeatureCpb, - extern CONST CPB_FAMILY_SERVICES ROMDATA F12CpbSupport; - #undef F12_CPB_SUPPORT - #define F12_CPB_SUPPORT {AMD_FAMILY_12_LN, &F12CpbSupport}, -// CONST F12_ES_CPB_SUPPORT ROMDATA F12EarlySampleCpbSupport = -// { -// (PF_F12_ES_CPB_INIT) CommonVoid -// }; - #endif - #endif - #endif - - // Family 14h - #ifdef OPTION_FAMILY14H - #if OPTION_FAMILY14H == TRUE - #if OPTION_FAMILY14H_ON == TRUE - extern CONST CPU_FEATURE_DESCRIPTOR ROMDATA CpuFeatureCpb; - #undef OPTION_CPB_FEAT - #define OPTION_CPB_FEAT &CpuFeatureCpb, - extern CONST CPB_FAMILY_SERVICES ROMDATA F14OnCpbSupport; - #undef F14_ON_CPB_SUPPORT - #define F14_ON_CPB_SUPPORT {AMD_FAMILY_14_ON, &F14OnCpbSupport}, - #endif - #endif - #endif - - // Family 15h - #ifdef OPTION_FAMILY15H - #if OPTION_FAMILY15H == TRUE - #if (OPTION_FAMILY15H_OR == TRUE) - extern CONST CPU_FEATURE_DESCRIPTOR ROMDATA CpuFeatureCpb; - #undef OPTION_CPB_FEAT - #define OPTION_CPB_FEAT &CpuFeatureCpb, - extern CONST CPB_FAMILY_SERVICES ROMDATA F15OrCpbSupport; - #undef F15_OR_CPB_SUPPORT - #define F15_OR_CPB_SUPPORT {AMD_FAMILY_15_OR, &F15OrCpbSupport}, - - CONST F15_OR_ES_CPB_SUPPORT ROMDATA F15OrEarlySampleCpbSupport = - { - (PF_F15_OR_ES_IS_CPB_SUPPORTED) CommonVoid - }; - #endif - #endif - #endif - - #endif -#endif - -CONST CPU_SPECIFIC_SERVICES_XLAT ROMDATA CpbFamilyServiceArray[] = -{ - F10_CPB_SUPPORT - F12_CPB_SUPPORT - F14_ON_CPB_SUPPORT - F15_OR_CPB_SUPPORT - {0, NULL} -}; - -CONST CPU_FAMILY_SUPPORT_TABLE ROMDATA CpbFamilyServiceTable = -{ - (sizeof (CpbFamilyServiceArray) / sizeof (CPU_SPECIFIC_SERVICES_XLAT)), - &CpbFamilyServiceArray[0] -}; - -#endif // _OPTION_CPB_INSTALL_H_ diff --git a/src/vendorcode/amd/agesa/f12/Config/OptionCpuCacheFlushOnHaltInstall.h b/src/vendorcode/amd/agesa/f12/Config/OptionCpuCacheFlushOnHaltInstall.h deleted file mode 100644 index 15949d0e34..0000000000 --- a/src/vendorcode/amd/agesa/f12/Config/OptionCpuCacheFlushOnHaltInstall.h +++ /dev/null @@ -1,117 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * Install of build option: CPU Cache Flush On Halt - * - * Contains AMD AGESA install macros and test conditions. Output is the - * defaults tables reflecting the User's build options selection. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: Options - * @e \$Revision: 44737 $ @e \$Date: 2011-01-05 15:59:55 +0800 (Wed, 05 Jan 2011) $ - */ -/***************************************************************************** - * - * Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ***************************************************************************/ - -#ifndef _OPTION_CPU_CACHEFLUSHONHALT_INSTALL_H_ -#define _OPTION_CPU_CACHEFLUSHONHALT_INSTALL_H_ - -#include "cpuPostInit.h" - -/* This option is designed to be included into the platform solution install - * file. The platform solution install file will define the options status. - * Check to validate the definition - */ -#define OPTION_CPU_CACHE_FLUSH_ON_HALT_FEAT -#define F10_BL_CPU_CFOH_SUPPORT -#define F10_DA_CPU_CFOH_SUPPORT -#define F10_CPU_CFOH_SUPPORT -#define F15_OR_CPU_CFOH_SUPPORT - -#if OPTION_CPU_CFOH == TRUE - #if (AGESA_ENTRY_INIT_POST == TRUE) || (AGESA_ENTRY_INIT_RESUME == TRUE) - #ifdef OPTION_FAMILY10H - #if OPTION_FAMILY10H == TRUE - extern CONST CPU_FEATURE_DESCRIPTOR ROMDATA CpuFeatureCacheFlushOnHalt; - #undef OPTION_CPU_CACHE_FLUSH_ON_HALT_FEAT - #define OPTION_CPU_CACHE_FLUSH_ON_HALT_FEAT &CpuFeatureCacheFlushOnHalt, - - #if OPTION_FAMILY10H_BL == TRUE - extern CONST CPU_CFOH_FAMILY_SERVICES ROMDATA F10BlCacheFlushOnHalt; - #undef F10_BL_CPU_CFOH_SUPPORT - #define F10_BL_CPU_CFOH_SUPPORT {AMD_FAMILY_10_BL, &F10BlCacheFlushOnHalt}, - #endif - - #if OPTION_FAMILY10H_DA == TRUE - extern CONST CPU_CFOH_FAMILY_SERVICES ROMDATA F10DaCacheFlushOnHalt; - #undef F10_DA_CPU_CFOH_SUPPORT - #define F10_DA_CPU_CFOH_SUPPORT {AMD_FAMILY_10_DA, &F10DaCacheFlushOnHalt}, - #endif - - #if (OPTION_FAMILY10H_RB == TRUE) || (OPTION_FAMILY10H_HY == TRUE) || (OPTION_FAMILY10H_PH == TRUE) - extern CONST CPU_CFOH_FAMILY_SERVICES ROMDATA F10CacheFlushOnHalt; - #undef F10_CPU_CFOH_SUPPORT - #define F10_CPU_CFOH_SUPPORT {AMD_FAMILY_10_RB | AMD_FAMILY_10_HY | AMD_FAMILY_10_PH, &F10CacheFlushOnHalt}, - #endif - #endif - #endif - - #ifdef OPTION_FAMILY15H - #if OPTION_FAMILY15H == TRUE - extern CONST CPU_FEATURE_DESCRIPTOR ROMDATA CpuFeatureCacheFlushOnHalt; - #undef OPTION_CPU_CACHE_FLUSH_ON_HALT_FEAT - #define OPTION_CPU_CACHE_FLUSH_ON_HALT_FEAT &CpuFeatureCacheFlushOnHalt, - - #if OPTION_FAMILY15H_OR == TRUE - extern CONST CPU_CFOH_FAMILY_SERVICES ROMDATA F15OrCacheFlushOnHalt; - #undef F15_OR_CPU_CFOH_SUPPORT - #define F15_OR_CPU_CFOH_SUPPORT {AMD_FAMILY_15_OR, &F15OrCacheFlushOnHalt}, - #endif - #endif - #endif - #endif -#endif - -CONST CPU_SPECIFIC_SERVICES_XLAT ROMDATA CacheFlushOnHaltFamilyServiceArray[] = -{ - F10_BL_CPU_CFOH_SUPPORT - F10_DA_CPU_CFOH_SUPPORT - F10_CPU_CFOH_SUPPORT - F15_OR_CPU_CFOH_SUPPORT - {0, NULL} -}; -CONST CPU_FAMILY_SUPPORT_TABLE ROMDATA CacheFlushOnHaltFamilyServiceTable = -{ - (sizeof (CacheFlushOnHaltFamilyServiceArray) / sizeof (CPU_SPECIFIC_SERVICES_XLAT)), - &CacheFlushOnHaltFamilyServiceArray[0] -}; - -#endif // _OPTION_CPU_CACHEFLUSHONHALT_INSTALL_H_ diff --git a/src/vendorcode/amd/agesa/f12/Config/OptionCpuCoreLevelingInstall.h b/src/vendorcode/amd/agesa/f12/Config/OptionCpuCoreLevelingInstall.h deleted file mode 100644 index c598283b6b..0000000000 --- a/src/vendorcode/amd/agesa/f12/Config/OptionCpuCoreLevelingInstall.h +++ /dev/null @@ -1,109 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * Install of build option: CPU Core Leveling - * - * Contains AMD AGESA install macros and test conditions. Output is the - * defaults tables reflecting the User's build options selection. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: Options - * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $ - */ -/***************************************************************************** - * - * Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ***************************************************************************/ - -#ifndef _OPTION_CPU_CORELEVELING_INSTALL_H_ -#define _OPTION_CPU_CORELEVELING_INSTALL_H_ - - -/* This option is designed to be included into the platform solution install - * file. The platform solution install file will define the options status. - * Check to validate the definition - */ -#define OPTION_CPU_CORE_LEVELING_FEAT -#define F10_REVE_CPU_CORELEVELING_SUPPORT -#define F10_REVD_CPU_CORELEVELING_SUPPORT -#define F10_REVC_CPU_CORELEVELING_SUPPORT -#define F15_OR_CPU_CORELEVELING_SUPPORT - -#if OPTION_CPU_CORELEVLING == TRUE - #if (AGESA_ENTRY_INIT_EARLY == TRUE) - // Family 10h - #if OPTION_FAMILY10H == TRUE - extern CONST CPU_FEATURE_DESCRIPTOR ROMDATA CpuFeatureCoreLeveling; - #undef OPTION_CPU_CORE_LEVELING_FEAT - #define OPTION_CPU_CORE_LEVELING_FEAT &CpuFeatureCoreLeveling, - #if OPTION_FAMILY10H_HY == TRUE - extern CONST CPU_CORE_LEVELING_FAMILY_SERVICES ROMDATA F10RevDCoreLeveling; - #undef F10_REVD_CPU_CORELEVELING_SUPPORT - #define F10_REVD_CPU_CORELEVELING_SUPPORT {AMD_FAMILY_10_HY, &F10RevDCoreLeveling}, - #endif - - #if (OPTION_FAMILY10H_RB == TRUE) || (OPTION_FAMILY10H_BL == TRUE) || (OPTION_FAMILY10H_DA == TRUE) - extern CONST CPU_CORE_LEVELING_FAMILY_SERVICES ROMDATA F10RevCCoreLeveling; - #undef F10_REVC_CPU_CORELEVELING_SUPPORT - #define F10_REVC_CPU_CORELEVELING_SUPPORT {AMD_FAMILY_10_RB | AMD_FAMILY_10_BL | AMD_FAMILY_10_DA, &F10RevCCoreLeveling}, - #endif - - #if (OPTION_FAMILY10H_PH == TRUE) - extern CONST CPU_CORE_LEVELING_FAMILY_SERVICES ROMDATA F10RevECoreLeveling; - #undef F10_REVE_CPU_CORELEVELING_SUPPORT - #define F10_REVE_CPU_CORELEVELING_SUPPORT {AMD_FAMILY_10_PH, &F10RevECoreLeveling}, - #endif - #endif - // Family 15h - #if OPTION_FAMILY15H == TRUE - extern CONST CPU_FEATURE_DESCRIPTOR ROMDATA CpuFeatureCoreLeveling; - #undef OPTION_CPU_CORE_LEVELING_FEAT - #define OPTION_CPU_CORE_LEVELING_FEAT &CpuFeatureCoreLeveling, - - extern CONST CPU_CORE_LEVELING_FAMILY_SERVICES ROMDATA F15OrCoreLeveling; - #undef F15_OR_CPU_CORELEVELING_SUPPORT - #define F15_OR_CPU_CORELEVELING_SUPPORT {AMD_FAMILY_15_OR, &F15OrCoreLeveling}, - #endif - #endif -#endif - -CONST CPU_SPECIFIC_SERVICES_XLAT ROMDATA CoreLevelingFamilyServiceArray[] = -{ - F10_REVE_CPU_CORELEVELING_SUPPORT - F10_REVD_CPU_CORELEVELING_SUPPORT - F10_REVC_CPU_CORELEVELING_SUPPORT - {0, NULL} -}; -CONST CPU_FAMILY_SUPPORT_TABLE ROMDATA CoreLevelingFamilyServiceTable = -{ - (sizeof (CoreLevelingFamilyServiceArray) / sizeof (CPU_SPECIFIC_SERVICES_XLAT)), - &CoreLevelingFamilyServiceArray[0] -}; - -#endif // _OPTION_CPU_CORELEVELING_INSTALL_H_ diff --git a/src/vendorcode/amd/agesa/f12/Config/OptionCpuFamiliesInstall.h b/src/vendorcode/amd/agesa/f12/Config/OptionCpuFamiliesInstall.h deleted file mode 100644 index 6074aee3a3..0000000000 --- a/src/vendorcode/amd/agesa/f12/Config/OptionCpuFamiliesInstall.h +++ /dev/null @@ -1,357 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * Install of all appropriate CPU family specific support. - * - * This file generates the defaults tables for all family specific - * combinations. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: Core - * @e \$Revision: 49967 $ @e \$Date: 2011-03-31 11:15:12 +0800 (Thu, 31 Mar 2011) $ - */ -/***************************************************************************** - * - * Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ***************************************************************************/ - -/* Default all CPU Specific Service members to off. They - will be enabled as needed by cross referencing families - with entry points in the family / model install files. */ -#define GET_PSTATE_POWER FALSE -#define GET_PSTATE_FREQ FALSE -#define DISABLE_PSTATE FALSE -#define TRANSITION_PSTATE FALSE -#define PROC_IDD_MAX FALSE -#define GET_TSC_RATE FALSE -#define PSTATE_TRANSITION_LATENCY FALSE -#define GET_PSTATE_REGISTER_INFO FALSE -#define GET_PSTATE_MAX_STATE FALSE -#define SET_PSTATE_LEVELING_REG FALSE -#define GET_NB_FREQ FALSE -#define GET_NB_IDD_MAX FALSE -#define IS_NBCOF_INIT_NEEDED FALSE -#define AP_INITIAL_LAUNCH FALSE -#define GET_AP_MAILBOX_FROM_HW FALSE -#define SET_AP_CORE_NUMBER FALSE -#define GET_AP_CORE_NUMBER FALSE -#define TRANSFER_AP_CORE_NUMBER FALSE -#define ID_POSITION_INITIAL_APICID FALSE -#define SAVE_FEATURES FALSE -#define WRITE_FEATURES FALSE -#define SET_DOWN_CORE_REG FALSE -#define SET_WARM_RESET_FLAG FALSE -#define GET_WARM_RESET_FLAG FALSE -#define USES_REGISTER_TABLES FALSE -#define BASE_FAMILY_PCI FALSE -#define MODEL_SPECIFIC_PCI FALSE -#define BASE_FAMILY_MSR FALSE -#define MODEL_SPECIFIC_MSR FALSE -#define BRAND_STRING1 FALSE -#define BRAND_STRING2 FALSE -#define BASE_FAMILY_HT_PCI FALSE -#define MODEL_SPECIFIC_HT_PCI FALSE -#define BASE_FAMILY_WORKAROUNDS FALSE -#define GET_PATCHES FALSE -#define GET_PATCHES_EQUIVALENCE_TABLE FALSE -#define GET_CACHE_INFO FALSE -#define GET_SYSTEM_PM_TABLE FALSE -#define GET_WHEA_INIT FALSE -#define GET_CFOH_REG FALSE -#define GET_PLATFORM_TYPE_SPECIFIC_INFO FALSE -#define IS_NB_PSTATE_ENABLED FALSE - -/* - * Pull in family specific services based on entry point - */ -#if AGESA_ENTRY_INIT_RESET == TRUE - #undef ID_POSITION_INITIAL_APICID - #define ID_POSITION_INITIAL_APICID TRUE - #undef GET_AP_MAILBOX_FROM_HW - #define GET_AP_MAILBOX_FROM_HW TRUE - #undef SET_WARM_RESET_FLAG - #define SET_WARM_RESET_FLAG TRUE - #undef GET_WARM_RESET_FLAG - #define GET_WARM_RESET_FLAG TRUE - #undef GET_CACHE_INFO - #define GET_CACHE_INFO TRUE - #undef GET_AP_CORE_NUMBER - #define GET_AP_CORE_NUMBER TRUE - #undef TRANSFER_AP_CORE_NUMBER - #define TRANSFER_AP_CORE_NUMBER TRUE -#endif - -#if AGESA_ENTRY_INIT_EARLY == TRUE - #undef TRANSITION_PSTATE - #define TRANSITION_PSTATE TRUE - #undef DISABLE_PSTATE - #define DISABLE_PSTATE TRUE - #undef PROC_IDD_MAX - #define PROC_IDD_MAX TRUE - #undef GET_TSC_RATE - #define GET_TSC_RATE TRUE - #undef GET_NB_FREQ - #define GET_NB_FREQ TRUE - #undef GET_NB_IDD_MAX - #define GET_NB_IDD_MAX TRUE - #undef IS_NBCOF_INIT_NEEDED - #define IS_NBCOF_INIT_NEEDED TRUE - #undef AP_INITIAL_LAUNCH - #define AP_INITIAL_LAUNCH TRUE - #undef GET_AP_MAILBOX_FROM_HW - #define GET_AP_MAILBOX_FROM_HW TRUE - #undef SET_AP_CORE_NUMBER - #define SET_AP_CORE_NUMBER TRUE - #undef GET_AP_CORE_NUMBER - #define GET_AP_CORE_NUMBER TRUE - #undef TRANSFER_AP_CORE_NUMBER - #define TRANSFER_AP_CORE_NUMBER TRUE - #undef ID_POSITION_INITIAL_APICID - #define ID_POSITION_INITIAL_APICID TRUE - #undef SET_DOWN_CORE_REG - #define SET_DOWN_CORE_REG TRUE - #undef SET_WARM_RESET_FLAG - #define SET_WARM_RESET_FLAG TRUE - #undef GET_WARM_RESET_FLAG - #define GET_WARM_RESET_FLAG TRUE - #undef USES_REGISTER_TABLES - #define USES_REGISTER_TABLES TRUE - #undef BASE_FAMILY_PCI - #define BASE_FAMILY_PCI TRUE - #undef MODEL_SPECIFIC_PCI - #define MODEL_SPECIFIC_PCI TRUE - #undef BASE_FAMILY_MSR - #define BASE_FAMILY_MSR TRUE - #undef MODEL_SPECIFIC_MSR - #define MODEL_SPECIFIC_MSR TRUE - #undef BRAND_STRING1 - #define BRAND_STRING1 TRUE - #undef BRAND_STRING2 - #define BRAND_STRING2 TRUE - #undef BASE_FAMILY_HT_PCI - #define BASE_FAMILY_HT_PCI TRUE - #undef MODEL_SPECIFIC_HT_PCI - #define MODEL_SPECIFIC_HT_PCI TRUE - #undef BASE_FAMILY_WORKAROUNDS - #define BASE_FAMILY_WORKAROUNDS TRUE - #undef GET_PATCHES - #define GET_PATCHES TRUE - #undef GET_PATCHES_EQUIVALENCE_TABLE - #define GET_PATCHES_EQUIVALENCE_TABLE TRUE - #undef GET_SYSTEM_PM_TABLE - #define GET_SYSTEM_PM_TABLE TRUE - #undef GET_CACHE_INFO - #define GET_CACHE_INFO TRUE - #undef GET_PLATFORM_TYPE_SPECIFIC_INFO - #define GET_PLATFORM_TYPE_SPECIFIC_INFO TRUE - #undef IS_NB_PSTATE_ENABLED - #define IS_NB_PSTATE_ENABLED TRUE -#endif - -#if AGESA_ENTRY_INIT_POST == TRUE - #undef ID_POSITION_INITIAL_APICID - #define ID_POSITION_INITIAL_APICID TRUE - #undef GET_PSTATE_POWER - #define GET_PSTATE_POWER TRUE - #undef GET_PSTATE_FREQ - #define GET_PSTATE_FREQ TRUE - #undef TRANSITION_PSTATE - #define TRANSITION_PSTATE TRUE - #undef PROC_IDD_MAX - #define PROC_IDD_MAX TRUE - #undef GET_AP_CORE_NUMBER - #define GET_AP_CORE_NUMBER TRUE - #undef GET_PSTATE_REGISTER_INFO - #define GET_PSTATE_REGISTER_INFO TRUE - #undef GET_PSTATE_MAX_STATE - #define GET_PSTATE_MAX_STATE TRUE - #undef SET_PSTATE_LEVELING_REG - #define SET_PSTATE_LEVELING_REG TRUE - #undef SET_WARM_RESET_FLAG - #define SET_WARM_RESET_FLAG TRUE - #undef GET_WARM_RESET_FLAG - #define GET_WARM_RESET_FLAG TRUE - #undef SAVE_FEATURES - #define SAVE_FEATURES TRUE - #undef WRITE_FEATURES - #define WRITE_FEATURES TRUE - #undef GET_CFOH_REG - #define GET_CFOH_REG TRUE - #undef IS_NB_PSTATE_ENABLED - #define IS_NB_PSTATE_ENABLED TRUE -#endif - -#if AGESA_ENTRY_INIT_ENV == TRUE -#endif - -#if AGESA_ENTRY_INIT_MID == TRUE -#endif - -#if AGESA_ENTRY_INIT_LATE == TRUE - #undef GET_AP_CORE_NUMBER - #define GET_AP_CORE_NUMBER TRUE - #undef GET_PSTATE_FREQ - #define GET_PSTATE_FREQ TRUE - #undef TRANSITION_PSTATE - #define TRANSITION_PSTATE TRUE - #undef PSTATE_TRANSITION_LATENCY - #define PSTATE_TRANSITION_LATENCY TRUE - #undef GET_WHEA_INIT - #define GET_WHEA_INIT TRUE - #undef GET_PLATFORM_TYPE_SPECIFIC_INFO - #define GET_PLATFORM_TYPE_SPECIFIC_INFO TRUE - #undef GET_TSC_RATE - #define GET_TSC_RATE TRUE - #undef BRAND_STRING1 - #define BRAND_STRING1 TRUE - #undef BRAND_STRING2 - #define BRAND_STRING2 TRUE -#endif - -#if AGESA_ENTRY_INIT_S3SAVE == TRUE -#endif - -#if AGESA_ENTRY_INIT_RESUME == TRUE - #undef GET_CFOH_REG - #define GET_CFOH_REG TRUE -#endif - -#if AGESA_ENTRY_INIT_LATE_RESTORE == TRUE -#endif - -#if AGESA_ENTRY_INIT_GENERAL_SERVICES == TRUE - #undef ID_POSITION_INITIAL_APICID - #define ID_POSITION_INITIAL_APICID TRUE -#endif - -/* - * Initialize PCI MMIO mask to 0 - */ -#define FAMILY_MMIO_BASE_MASK (0ull) - - -/* - * Initialize all families to disabled - */ -#define OPT_F12_TABLE - -#define OPT_F12_ID_TABLE - - -/* - * Install family specific support - */ - -#if (OPTION_FAMILY12H == TRUE) - #include "OptionFamily12hInstall.h" -#endif - -/* - * Process PCI MMIO mask - */ - -// If size is 0, but base is not, break the build. -#if (CFG_PCI_MMIO_BASE != 0) && (CFG_PCI_MMIO_SIZE == 0) - #error BLDCFG: Invalid PCI MMIO size -- acceptable values are 1, 2, 4, 8, 16, 32, 64, 128, and 256 -#endif - -// If base is 0, but size is not, break the build. -#if (CFG_PCI_MMIO_BASE == 0) && (CFG_PCI_MMIO_SIZE != 0) - #error BLDCFG: Invalid PCI MMIO base -- must be 8MB or greater -#endif - -#if (CFG_PCI_MMIO_BASE != 0) && (CFG_PCI_MMIO_SIZE != 0) - // Both are non-zero, begin further processing. - - // Heap runs from 4MB to 8MB. Disallow any addresses below 8MB. - #if (CFG_PCI_MMIO_BASE < 0x800000) - #error BLDCFG: Invalid PCI MMIO base -- must be 8MB or greater - #endif - - // Break the build if the address is too high for the enabled families. - #if ((CFG_PCI_MMIO_BASE & FAMILY_MMIO_BASE_MASK) != 0) - #error BLDCFG: Invalid PCI MMIO base address for the installed CPU families - #endif - - // If the size parameter is not valid, break the build. - #if (CFG_PCI_MMIO_SIZE != 1) && (CFG_PCI_MMIO_SIZE != 2) && (CFG_PCI_MMIO_SIZE != 4) && (CFG_PCI_MMIO_SIZE != 8) && (CFG_PCI_MMIO_SIZE != 16) - #if (CFG_PCI_MMIO_SIZE != 32) && (CFG_PCI_MMIO_SIZE != 64) && (CFG_PCI_MMIO_SIZE != 128) && (CFG_PCI_MMIO_SIZE != 256) - #error BLDCFG: Invalid PCI MMIO size -- acceptable values are 1, 2, 4, 8, 16, 32, 64, 128, and 256 - #endif - #endif - - #define PCI_MMIO_ALIGNMENT ((0x100000 * CFG_PCI_MMIO_SIZE) - 1) - // If the base is not aligned according to size, break the build. - #if ((CFG_PCI_MMIO_BASE & PCI_MMIO_ALIGNMENT) != 0) - #error BLDCFG: Invalid PCI MMIO base -- must be properly aligned according to MMIO size - #endif - #undef PCI_MMIO_ALIGNMENT -#endif - -/* - * Process sockets / modules - */ -#ifndef ADVCFG_PLATFORM_SOCKETS - #error BLDOPT Set Family supported sockets. -#endif -#ifndef ADVCFG_PLATFORM_MODULES - #error BLDOPT Set Family supported modules. -#endif - -CONST OPTIONS_CONFIG_TOPOLOGY ROMDATA TopologyConfiguration = -{ - ADVCFG_PLATFORM_SOCKETS, - ADVCFG_PLATFORM_MODULES -}; - -/* - * Instantiate global data needed for processor identification - */ -CONST CPU_SPECIFIC_SERVICES_XLAT ROMDATA CpuSupportedFamiliesArray[] = -{ - OPT_F12_TABLE -}; - -CONST CPU_FAMILY_SUPPORT_TABLE ROMDATA CpuSupportedFamiliesTable = -{ - (sizeof (CpuSupportedFamiliesArray) / sizeof (CPU_SPECIFIC_SERVICES_XLAT)), - &CpuSupportedFamiliesArray[0] -}; - - -CONST CPU_LOGICAL_ID_FAMILY_XLAT ROMDATA CpuSupportedFamilyIdArray[] = -{ - OPT_F12_ID_TABLE -}; - -CONST CPU_FAMILY_ID_XLAT_TABLE ROMDATA CpuSupportedFamilyIdTable = -{ - (sizeof (CpuSupportedFamilyIdArray) / sizeof (CPU_LOGICAL_ID_FAMILY_XLAT)), - CpuSupportedFamilyIdArray -}; diff --git a/src/vendorcode/amd/agesa/f12/Config/OptionCpuFeaturesInstall.h b/src/vendorcode/amd/agesa/f12/Config/OptionCpuFeaturesInstall.h deleted file mode 100644 index ba4b42b8fb..0000000000 --- a/src/vendorcode/amd/agesa/f12/Config/OptionCpuFeaturesInstall.h +++ /dev/null @@ -1,75 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * Install of multiple CPU features. - * - * Aggregates enabled CPU features into a list for the dispatcher to process. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: Options - * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $ - */ -/***************************************************************************** - * - * Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ***************************************************************************/ - -#ifndef _OPTION_CPU_FEATURES_INSTALL_H_ -#define _OPTION_CPU_FEATURES_INSTALL_H_ - -#include "OptionHwC1eInstall.h" -#include "OptionMsgBasedC1eInstall.h" -#include "OptionSwC1eInstall.h" -#include "OptionL3FeaturesInstall.h" -#include "OptionCpuCoreLevelingInstall.h" -#include "OptionIoCstateInstall.h" -#include "OptionC6Install.h" -#include "OptionCpbInstall.h" -#include "OptionCpuCacheFlushOnHaltInstall.h" -#include "OptionLowPwrPstateInstall.h" -#include "OptionPreserveMailboxInstall.h" - -CONST CPU_FEATURE_DESCRIPTOR* ROMDATA SupportedCpuFeatureList[] = -{ - OPTION_HW_C1E_FEAT - OPTION_MSG_BASED_C1E_FEAT - OPTION_SW_C1E_FEAT - OPTION_L3_FEAT - OPTION_CPU_CORE_LEVELING_FEAT - OPTION_IO_CSTATE_FEAT - OPTION_C6_STATE_FEAT - OPTION_CPB_FEAT - OPTION_CPU_CACHE_FLUSH_ON_HALT_FEAT - OPTION_CPU_LOW_PWR_PSTATE_FOR_PROCHOT_FEAT // this function should be run before creating ACPI objects and after Pstate initialization - OPTION_PRESERVE_MAILBOX_FEAT - NULL -}; - - -#endif // _OPTION_CPU_FEATURES_INSTALL_H_ diff --git a/src/vendorcode/amd/agesa/f12/Config/OptionDmiInstall.h b/src/vendorcode/amd/agesa/f12/Config/OptionDmiInstall.h deleted file mode 100644 index ead4fcec6a..0000000000 --- a/src/vendorcode/amd/agesa/f12/Config/OptionDmiInstall.h +++ /dev/null @@ -1,206 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * Install of build option: DMI - * - * Contains AMD AGESA install macros and test conditions. Output is the - * defaults tables reflecting the User's build options selection. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: Options - * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $ - */ -/***************************************************************************** - * - * Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ***************************************************************************/ - -#ifndef _OPTION_DMI_INSTALL_H_ -#define _OPTION_DMI_INSTALL_H_ - -#include "cpuLateInit.h" - -/* This option is designed to be included into the platform solution install - * file. The platform solution install file will define the options status. - * Check to validate the definition - */ -#if AGESA_ENTRY_INIT_LATE == TRUE - #ifndef OPTION_DMI - #error BLDOPT: Option not defined: "OPTION_DMI" - #endif - #if OPTION_DMI == TRUE - OPTION_DMI_FEATURE GetDmiInfoMain; - OPTION_DMI_RELEASE_BUFFER ReleaseDmiBuffer; - #define USER_DMI_OPTION &GetDmiInfoMain - #define USER_DMI_RELEASE_BUFFER &ReleaseDmiBuffer - - // This additional check keeps AP launch routines from being unnecessarily included - // in single socket systems. - #if OPTION_MULTISOCKET == TRUE - #define CPU_DMI_AP_GET_TYPE4_TYPE7 {AP_LATE_TASK_GET_TYPE4_TYPE7, (IMAGE_ENTRY) GetType4Type7Info}, - #else - #define CPU_DMI_AP_GET_TYPE4_TYPE7 - #endif - - // Family 10 - #ifdef OPTION_FAMILY10H - #if OPTION_FAMILY10H == TRUE - extern PROC_FAMILY_TABLE ProcFamily10DmiTable; - #define FAM10_DMI_SUPPORT FAM10_ENABLED, - #define FAM10_DMI_TABLE &ProcFamily10DmiTable, - #else - #define FAM10_DMI_SUPPORT - #define FAM10_DMI_TABLE - #endif - #else - #define FAM10_DMI_SUPPORT - #define FAM10_DMI_TABLE - #endif - - // Family 12 - #ifdef OPTION_FAMILY12H - #if OPTION_FAMILY12H == TRUE - extern PROC_FAMILY_TABLE ProcFamily12DmiTable; - #define FAM12_DMI_SUPPORT FAM12_ENABLED, - #define FAM12_DMI_TABLE &ProcFamily12DmiTable, - #else - #define FAM12_DMI_SUPPORT - #define FAM12_DMI_TABLE - #endif - #else - #define FAM12_DMI_SUPPORT - #define FAM12_DMI_TABLE - #endif - - // Family 14 - #ifdef OPTION_FAMILY14H - #if OPTION_FAMILY14H == TRUE - extern PROC_FAMILY_TABLE ProcFamily14DmiTable; - #define FAM14_DMI_SUPPORT FAM14_ENABLED, - #define FAM14_DMI_TABLE &ProcFamily14DmiTable, - #else - #define FAM14_DMI_SUPPORT - #define FAM14_DMI_TABLE - #endif - #else - #define FAM14_DMI_SUPPORT - #define FAM14_DMI_TABLE - #endif - - // Family 15 - #ifdef OPTION_FAMILY15H - #if OPTION_FAMILY15H == TRUE - #if OPTION_FAMILY15H_OR == TRUE - extern PROC_FAMILY_TABLE ProcFamily15OrDmiTable; - #define FAM15_OR_DMI_SUPPORT FAM15_OR_ENABLED, - #define FAM15_OR_DMI_TABLE &ProcFamily15OrDmiTable, - #else - #define FAM15_OR_DMI_SUPPORT - #define FAM15_OR_DMI_TABLE - #endif - #define FAM15_TN_DMI_SUPPORT - #define FAM15_TN_DMI_TABLE - #else - #define FAM15_OR_DMI_SUPPORT - #define FAM15_OR_DMI_TABLE - #define FAM15_TN_DMI_SUPPORT - #define FAM15_TN_DMI_TABLE - #endif - #else - #define FAM15_OR_DMI_SUPPORT - #define FAM15_OR_DMI_TABLE - #define FAM15_TN_DMI_SUPPORT - #define FAM15_TN_DMI_TABLE - #endif - - #else - OPTION_DMI_FEATURE GetDmiInfoStub; - OPTION_DMI_RELEASE_BUFFER ReleaseDmiBufferStub; - #define USER_DMI_OPTION GetDmiInfoStub - #define USER_DMI_RELEASE_BUFFER ReleaseDmiBufferStub - #define FAM10_DMI_SUPPORT - #define FAM10_DMI_TABLE - #define FAM12_DMI_SUPPORT - #define FAM12_DMI_TABLE - #define FAM14_DMI_SUPPORT - #define FAM14_DMI_TABLE - #define FAM15_OR_DMI_SUPPORT - #define FAM15_OR_DMI_TABLE - #define FAM15_TN_DMI_SUPPORT - #define FAM15_TN_DMI_TABLE - #define CPU_DMI_AP_GET_TYPE4_TYPE7 - #endif -#else - OPTION_DMI_FEATURE GetDmiInfoStub; - OPTION_DMI_RELEASE_BUFFER ReleaseDmiBufferStub; - #define USER_DMI_OPTION GetDmiInfoStub - #define USER_DMI_RELEASE_BUFFER ReleaseDmiBufferStub - #define FAM10_DMI_SUPPORT - #define FAM10_DMI_TABLE - #define FAM12_DMI_SUPPORT - #define FAM12_DMI_TABLE - #define FAM14_DMI_SUPPORT - #define FAM14_DMI_TABLE - #define FAM15_OR_DMI_SUPPORT - #define FAM15_OR_DMI_TABLE - #define FAM15_TN_DMI_SUPPORT - #define FAM15_TN_DMI_TABLE - #define CPU_DMI_AP_GET_TYPE4_TYPE7 -#endif - -/// DMI supported families enum -typedef enum { - FAM10_DMI_SUPPORT ///< Conditionally define F10 support - FAM12_DMI_SUPPORT ///< Conditionally define F12 support - FAM14_DMI_SUPPORT ///< Conditionally define F14 support - FAM15_OR_DMI_SUPPORT ///< Conditionally define F15 OR support - FAM15_TN_DMI_SUPPORT ///< Conditionally define F15 TN support - NUM_DMI_FAMILIES ///< Number of installed families -} AGESA_DMI_SUPPORTED_FAM; - -/* Declare the Family List. An array of pointers to tables that each describe a family */ -CONST PROC_FAMILY_TABLE ROMDATA *ProcTables[] = { - FAM10_DMI_TABLE - FAM12_DMI_TABLE - FAM14_DMI_TABLE - FAM15_OR_DMI_TABLE - FAM15_TN_DMI_TABLE - NULL -}; - -/* Declare the instance of the DMI option configuration structure */ -CONST OPTION_DMI_CONFIGURATION ROMDATA OptionDmiConfiguration = { - DMI_STRUCT_VERSION, - USER_DMI_OPTION, - USER_DMI_RELEASE_BUFFER, - NUM_DMI_FAMILIES, - (VOID *((*)[])) &ProcTables // Compiler says array size must match struct decl -}; - -#endif // _OPTION_DMI_INSTALL_H_ diff --git a/src/vendorcode/amd/agesa/f12/Config/OptionFamily12hInstall.h b/src/vendorcode/amd/agesa/f12/Config/OptionFamily12hInstall.h deleted file mode 100644 index 215342d301..0000000000 --- a/src/vendorcode/amd/agesa/f12/Config/OptionFamily12hInstall.h +++ /dev/null @@ -1,694 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * Install of family 12h support - * - * This file generates the defaults tables for family 12h processors. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: Core - * @e \$Revision: 49967 $ @e \$Date: 2011-03-31 11:15:12 +0800 (Thu, 31 Mar 2011) $ - */ -/***************************************************************************** - * - * Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ***************************************************************************/ - -#ifndef _OPTION_FAMILY_12H_INSTALL_H_ -#define _OPTION_FAMILY_12H_INSTALL_H_ - - -#include "OptionFamily12hEarlySample.h" - -/* - * Common Family 12h routines - */ -extern F_CPU_DISABLE_PSTATE F12DisablePstate; -extern F_CPU_TRANSITION_PSTATE F12TransitionPstate; -extern F_CPU_GET_TSC_RATE F12GetTscRate; -extern F_CPU_GET_NB_FREQ F12GetCurrentNbFrequency; -extern F_CPU_GET_NB_PSTATE_INFO F12GetNbPstateInfo; -extern F_CPU_IS_NBCOF_INIT_NEEDED F12GetNbCofVidUpdate; -extern F_CPU_AP_INITIAL_LAUNCH F12LaunchApCore; -extern F_CPU_GET_IDD_MAX F12GetProcIddMax; -extern F_CPU_AMD_GET_AP_MAILBOX_FROM_HARDWARE F12GetApMailboxFromHardware; -extern F_CPU_GET_AP_CORE_NUMBER F12GetApCoreNumber; -extern F_CORE_ID_POSITION_IN_INITIAL_APIC_ID F12CpuAmdCoreIdPositionInInitialApicId; -extern F_CPU_SET_DOWN_CORE_REGISTER F12SetDownCoreRegister; -extern F_CPU_SET_WARM_RESET_FLAG F12SetAgesaWarmResetFlag; -extern F_CPU_GET_WARM_RESET_FLAG F12GetAgesaWarmResetFlag; -extern F_CPU_GET_FAMILY_SPECIFIC_ARRAY GetF12BrandIdString1; -extern F_CPU_GET_FAMILY_SPECIFIC_ARRAY GetF12BrandIdString2; -extern F_CPU_GET_FAMILY_SPECIFIC_ARRAY GetF12CacheInfo; -extern F_CPU_GET_FAMILY_SPECIFIC_ARRAY GetF12SysPmTable; -extern F_CPU_GET_FAMILY_SPECIFIC_ARRAY GetF12WheaInitData; -//extern F_CPU_GET_FAMILY_SPECIFIC_ARRAY GetEmptyArray; -extern F_CPU_GET_PLATFORM_TYPE_SPECIFIC_INFO F12GetPlatformTypeSpecificInfo; -extern CONST REGISTER_TABLE ROMDATA F12PciRegisterTable; -extern CONST REGISTER_TABLE ROMDATA F12PerCorePciRegisterTable; -extern CONST REGISTER_TABLE ROMDATA F12MsrRegisterTable; -extern F_CPU_NUMBER_OF_PHYSICAL_CORES F12GetNumberOfPhysicalCores; -extern F_GET_EARLY_INIT_TABLE GetCommonEarlyInitOnCoreTable; -extern F_IS_NB_PSTATE_ENABLED F12IsNbPstateEnabled; -#if OPTION_EARLY_SAMPLES == TRUE - extern CONST REGISTER_TABLE ROMDATA F12EarlySampleMsrRegisterTable; -#endif - -/* - * Install family 12h model 0 support - */ - -#ifdef OPTION_FAMILY12H_LN - #if OPTION_FAMILY12H_LN == TRUE - extern F_CPU_GET_FAMILY_SPECIFIC_ARRAY GetF12LnMicroCodePatchesStruct; - extern F_CPU_GET_FAMILY_SPECIFIC_ARRAY GetF12LnMicrocodeEquivalenceTable; - - #if USES_REGISTER_TABLES == TRUE - CONST REGISTER_TABLE ROMDATA *F12LnRegisterTables[] = - { - #if BASE_FAMILY_PCI == TRUE - &F12PciRegisterTable, - #endif - #if BASE_FAMILY_PCI == TRUE - &F12PerCorePciRegisterTable, - #endif - #if BASE_FAMILY_MSR == TRUE - &F12MsrRegisterTable, - #if OPTION_EARLY_SAMPLES == TRUE - &F12EarlySampleMsrRegisterTable, - #endif - #endif - // the end. - NULL - }; - #endif - - #if USES_REGISTER_TABLES == TRUE - CONST TABLE_ENTRY_TYPE_DESCRIPTOR ROMDATA F12LnTableEntryTypeDescriptors[] = - { - {MsrRegister, SetRegisterForMsrEntry}, - {PciRegister, SetRegisterForPciEntry}, - {FamSpecificWorkaround, SetRegisterForFamSpecificWorkaroundEntry}, - {ProfileFixup, (PF_DO_TABLE_ENTRY)CommonVoid}, - // End - {TableEntryTypeMax, (PF_DO_TABLE_ENTRY)CommonVoid} - }; - #endif - - CONST CPU_SPECIFIC_SERVICES ROMDATA cpuF12LnServices = - { - 0, - #if DISABLE_PSTATE == TRUE - F12DisablePstate, - #else - (PF_CPU_DISABLE_PSTATE) CommonAssert, - #endif - #if TRANSITION_PSTATE == TRUE - F12TransitionPstate, - #else - (PF_CPU_TRANSITION_PSTATE) CommonAssert, - #endif - #if PROC_IDD_MAX == TRUE - F12GetProcIddMax, - #else - (PF_CPU_GET_IDD_MAX) CommonAssert, - #endif - #if GET_TSC_RATE == TRUE - F12GetTscRate, - #else - (PF_CPU_GET_TSC_RATE) CommonAssert, - #endif - #if GET_NB_FREQ == TRUE - F12GetCurrentNbFrequency, - #else - (PF_CPU_GET_NB_FREQ) CommonAssert, - #endif - #if GET_NB_FREQ == TRUE - (PF_CPU_GET_MIN_MAX_NB_FREQ) CommonAssert, - #else - (PF_CPU_GET_MIN_MAX_NB_FREQ) CommonAssert, - #endif - #if GET_NB_FREQ == TRUE - F12GetNbPstateInfo, - #else - (PF_CPU_GET_NB_PSTATE_INFO) CommonAssert, - #endif - #if IS_NBCOF_INIT_NEEDED == TRUE - F12GetNbCofVidUpdate, - #else - (PF_CPU_IS_NBCOF_INIT_NEEDED) CommonAssert, - #endif - #if GET_NB_IDD_MAX == TRUE - (PF_CPU_GET_NB_IDD_MAX) CommonAssert, - #else - (PF_CPU_GET_NB_IDD_MAX) CommonAssert, - #endif - #if AP_INITIAL_LAUNCH == TRUE - F12LaunchApCore, - #else - (PF_CPU_AP_INITIAL_LAUNCH) CommonAssert, - #endif - #if (BRAND_STRING1 == TRUE) || (BRAND_STRING2 == TRUE) - F12GetNumberOfPhysicalCores, - #else - (PF_CPU_NUMBER_OF_PHYSICAL_CORES) CommonAssert, - #endif - #if GET_AP_MAILBOX_FROM_HW == TRUE - F12GetApMailboxFromHardware, - #else - (PF_CPU_AMD_GET_AP_MAILBOX_FROM_HARDWARE) CommonAssert, - #endif - #if SET_AP_CORE_NUMBER == TRUE - (PF_CPU_SET_AP_CORE_NUMBER) CommonVoid, - #else - (PF_CPU_SET_AP_CORE_NUMBER) CommonAssert, - #endif - #if GET_AP_CORE_NUMBER == TRUE - F12GetApCoreNumber, - #else - (PF_CPU_GET_AP_CORE_NUMBER) CommonAssert, - #endif - #if TRANSFER_AP_CORE_NUMBER == TRUE - (PF_CPU_TRANSFER_AP_CORE_NUMBER) CommonVoid, - #else - (PF_CPU_TRANSFER_AP_CORE_NUMBER) CommonAssert, - #endif - #if ID_POSITION_INITIAL_APICID == TRUE - F12CpuAmdCoreIdPositionInInitialApicId, - #else - (PF_CORE_ID_POSITION_IN_INITIAL_APIC_ID) CommonAssert, - #endif - #if SAVE_FEATURES == TRUE - (PF_CPU_SAVE_FEATURES) CommonVoid, - #else - (PF_CPU_SAVE_FEATURES) CommonAssert, - #endif - #if WRITE_FEATURES == TRUE - (PF_CPU_WRITE_FEATURES) CommonVoid, - #else - (PF_CPU_WRITE_FEATURES) CommonAssert, - #endif - #if SET_WARM_RESET_FLAG == TRUE - F12SetAgesaWarmResetFlag, - #else - (PF_CPU_SET_WARM_RESET_FLAG) CommonAssert, - #endif - #if GET_WARM_RESET_FLAG == TRUE - F12GetAgesaWarmResetFlag, - #else - (PF_CPU_GET_WARM_RESET_FLAG) CommonAssert, - #endif - #if BRAND_STRING1 == TRUE - GetF12BrandIdString1, - #else - (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert, - #endif - #if BRAND_STRING2 == TRUE - GetF12BrandIdString2, - #else - (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert, - #endif - #if GET_PATCHES == TRUE - GetF12LnMicroCodePatchesStruct, - #else - (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert, - #endif - #if GET_PATCHES_EQUIVALENCE_TABLE == TRUE - GetF12LnMicrocodeEquivalenceTable, - #else - (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert, - #endif - #if GET_CACHE_INFO == TRUE - GetF12CacheInfo, - #else - (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert, - #endif - #if GET_SYSTEM_PM_TABLE == TRUE - GetF12SysPmTable, - #else - (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert, - #endif - #if GET_WHEA_INIT == TRUE - GetF12WheaInitData, - #else - (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert, - #endif - #if GET_PLATFORM_TYPE_SPECIFIC_INFO == TRUE - F12GetPlatformTypeSpecificInfo, - #else - (PF_CPU_GET_PLATFORM_TYPE_SPECIFIC_INFO) CommonAssert, - #endif - #if IS_NB_PSTATE_ENABLED == TRUE - F12IsNbPstateEnabled, - #else - (PF_IS_NB_PSTATE_ENABLED) CommonAssert, - #endif - #if (BASE_FAMILY_HT_PCI == TRUE) - (PF_NEXT_LINK_HAS_HTFPY_FEATS) CommonReturnFalse, - #else - (PF_NEXT_LINK_HAS_HTFPY_FEATS) CommonReturnFalse, - #endif - #if (BASE_FAMILY_HT_PCI == TRUE) - (PF_SET_HT_PHY_REGISTER) CommonVoid, - #else - (PF_SET_HT_PHY_REGISTER) CommonAssert, - #endif - #if BASE_FAMILY_PCI == TRUE - (PF_GET_NEXT_HT_LINK_FEATURES) CommonReturnFalse, - #else - (PF_GET_NEXT_HT_LINK_FEATURES) CommonReturnFalse, - #endif - #if USES_REGISTER_TABLES == TRUE - (REGISTER_TABLE **) F12LnRegisterTables, - #else - NULL, - #endif - #if USES_REGISTER_TABLES == TRUE - (TABLE_ENTRY_TYPE_DESCRIPTOR *) F12LnTableEntryTypeDescriptors, - #else - NULL, - #endif - #if MODEL_SPECIFIC_HT_PCI == TRUE - NULL, - #else - NULL, - #endif - NULL, - InitCacheDisabled, - #if AGESA_ENTRY_INIT_EARLY == TRUE - GetCommonEarlyInitOnCoreTable - #else - (PF_GET_EARLY_INIT_TABLE) CommonVoid - #endif - }; - - #define LN_SOCKETS 1 - #define LN_MODULES 1 - #define LN_RECOVERY_SOCKETS 1 - #define LN_RECOVERY_MODULES 1 - extern F_CPU_GET_SUBFAMILY_ID_ARRAY GetF12LnLogicalIdAndRev; - #define OPT_F12_LN_ID (PF_CPU_GET_SUBFAMILY_ID_ARRAY) GetF12LnLogicalIdAndRev, - #ifndef ADVCFG_PLATFORM_SOCKETS - #define ADVCFG_PLATFORM_SOCKETS LN_SOCKETS - #else - #if ADVCFG_PLATFORM_SOCKETS < LN_SOCKETS - #undef ADVCFG_PLATFORM_SOCKETS - #define ADVCFG_PLATFORM_SOCKETS LN_SOCKETS - #endif - #endif - #ifndef ADVCFG_PLATFORM_MODULES - #define ADVCFG_PLATFORM_MODULES LN_MODULES - #else - #if ADVCFG_PLATFORM_MODULES < LN_MODULES - #undef ADVCFG_PLATFORM_MODULES - #define ADVCFG_PLATFORM_MODULES LN_MODULES - #endif - #endif - - #if GET_PATCHES == TRUE - #define F12_LN_UCODE_02 - #define F12_LN_UCODE_0E - #define F12_LN_UCODE_0F - - #if AGESA_ENTRY_INIT_EARLY == TRUE - extern CONST MICROCODE_PATCHES ROMDATA CpuF12MicrocodePatch03000027; - #undef F12_LN_UCODE_0F - #define F12_LN_UCODE_0F &CpuF12MicrocodePatch03000027, - #if OPTION_EARLY_SAMPLES == TRUE - extern CONST MICROCODE_PATCHES ROMDATA CpuF12MicrocodePatch03000002; - extern CONST MICROCODE_PATCHES ROMDATA CpuF12MicrocodePatch0300000e; - #undef F12_LN_UCODE_02 - #define F12_LN_UCODE_02 &CpuF12MicrocodePatch03000002, - #undef F12_LN_UCODE_0E - #define F12_LN_UCODE_0E &CpuF12MicrocodePatch0300000e, - #endif - #endif - - CONST MICROCODE_PATCHES ROMDATA *CpuF12LnMicroCodePatchArray[] = - { - F12_LN_UCODE_0F - F12_LN_UCODE_0E - F12_LN_UCODE_02 - NULL - }; - - CONST UINT8 ROMDATA CpuF12LnNumberOfMicrocodePatches = (UINT8) ((sizeof (CpuF12LnMicroCodePatchArray) / sizeof (CpuF12LnMicroCodePatchArray[0])) - 1); - #endif - - #if OPTION_EARLY_SAMPLES == TRUE - extern F_F12_ES_NB_PSTATE_INIT F12NbPstateInitEarlySampleHook; - extern F_F12_ES_POWER_PLANE_INIT F12PowerPlaneInitEarlySampleHook; - - CONST F12_ES_CORE_SUPPORT ROMDATA F12EarlySampleCoreSupport = - { - #if AGESA_ENTRY_INIT_EARLY == TRUE - F12PowerPlaneInitEarlySampleHook, - #else - (PF_F12_ES_POWER_PLANE_INIT) CommonAssert, - #endif - #if (AGESA_ENTRY_INIT_POST == TRUE) || (AGESA_ENTRY_INIT_RESUME == TRUE) - F12NbPstateInitEarlySampleHook - #else - (PF_F12_ES_NB_PSTATE_INIT) CommonAssert - #endif - }; - #else - CONST F12_ES_CORE_SUPPORT ROMDATA F12EarlySampleCoreSupport = - { - #if AGESA_ENTRY_INIT_EARLY == TRUE - (PF_F12_ES_POWER_PLANE_INIT) CommonVoid, - #else - (PF_F12_ES_POWER_PLANE_INIT) CommonAssert, - #endif - #if (AGESA_ENTRY_INIT_POST == TRUE) || (AGESA_ENTRY_INIT_RESUME == TRUE) - (PF_F12_ES_NB_PSTATE_INIT) CommonVoid - #else - (PF_F12_ES_NB_PSTATE_INIT) CommonAssert - #endif - }; - #endif - - #define OPT_F12_LN_CPU {AMD_FAMILY_12_LN, &cpuF12LnServices}, - #else // OPTION_FAMILY12H_LN == TRUE - #define OPT_F12_LN_CPU - #define OPT_F12_LN_ID - #endif // OPTION_FAMILY12H_LN == TRUE -#else // defined (OPTION_FAMILY12H_LN) - #define OPT_F12_LN_CPU - #define OPT_F12_LN_ID -#endif // defined (OPTION_FAMILY12H_LN) - - -/* - * Install unknown family 12h support - */ - -#if USES_REGISTER_TABLES == TRUE - CONST REGISTER_TABLE ROMDATA *F12UnknownRegisterTables[] = - { - #if BASE_FAMILY_PCI == TRUE - &F12PciRegisterTable, - #endif - #if BASE_FAMILY_PCI == TRUE - &F12PerCorePciRegisterTable, - #endif - #if BASE_FAMILY_MSR == TRUE - &F12MsrRegisterTable, - #endif - // the end. - NULL - }; -#endif - -#if USES_REGISTER_TABLES == TRUE - CONST TABLE_ENTRY_TYPE_DESCRIPTOR ROMDATA F12UnknownTableEntryTypeDescriptors[] = - { - {MsrRegister, SetRegisterForMsrEntry}, - {PciRegister, SetRegisterForPciEntry}, - {FamSpecificWorkaround, SetRegisterForFamSpecificWorkaroundEntry}, - {ProfileFixup, (PF_DO_TABLE_ENTRY)CommonVoid}, - // End - {TableEntryTypeMax, (PF_DO_TABLE_ENTRY)CommonVoid} - }; -#endif - -CONST CPU_SPECIFIC_SERVICES ROMDATA cpuF12UnknownServices = -{ - 0, - #if DISABLE_PSTATE == TRUE - F12DisablePstate, - #else - (PF_CPU_DISABLE_PSTATE) CommonAssert, - #endif - #if TRANSITION_PSTATE == TRUE - F12TransitionPstate, - #else - (PF_CPU_TRANSITION_PSTATE) CommonAssert, - #endif - #if PROC_IDD_MAX == TRUE - F12GetProcIddMax, - #else - (PF_CPU_GET_IDD_MAX) CommonAssert, - #endif - #if GET_TSC_RATE == TRUE - F12GetTscRate, - #else - (PF_CPU_GET_TSC_RATE) CommonAssert, - #endif - #if GET_NB_FREQ == TRUE - F12GetCurrentNbFrequency, - #else - (PF_CPU_GET_NB_FREQ) CommonAssert, - #endif - #if GET_NB_FREQ == TRUE - (PF_CPU_GET_MIN_MAX_NB_FREQ) CommonAssert, - #else - (PF_CPU_GET_MIN_MAX_NB_FREQ) CommonAssert, - #endif - #if GET_NB_FREQ == TRUE - F12GetNbPstateInfo, - #else - (PF_CPU_GET_NB_PSTATE_INFO) CommonAssert, - #endif - #if IS_NBCOF_INIT_NEEDED == TRUE - F12GetNbCofVidUpdate, - #else - (PF_CPU_IS_NBCOF_INIT_NEEDED) CommonAssert, - #endif - #if GET_NB_IDD_MAX == TRUE - (PF_CPU_GET_NB_IDD_MAX) CommonAssert, - #else - (PF_CPU_GET_NB_IDD_MAX) CommonAssert, - #endif - #if AP_INITIAL_LAUNCH == TRUE - F12LaunchApCore, - #else - (PF_CPU_AP_INITIAL_LAUNCH) CommonAssert, - #endif - #if (BRAND_STRING1 == TRUE) || (BRAND_STRING2 == TRUE) - F12GetNumberOfPhysicalCores, - #else - (PF_CPU_NUMBER_OF_PHYSICAL_CORES) CommonAssert, - #endif - #if GET_AP_MAILBOX_FROM_HW == TRUE - F12GetApMailboxFromHardware, - #else - (PF_CPU_AMD_GET_AP_MAILBOX_FROM_HARDWARE) CommonAssert, - #endif - #if SET_AP_CORE_NUMBER == TRUE - (PF_CPU_SET_AP_CORE_NUMBER) CommonVoid, - #else - (PF_CPU_SET_AP_CORE_NUMBER) CommonAssert, - #endif - #if GET_AP_CORE_NUMBER == TRUE - F12GetApCoreNumber, - #else - (PF_CPU_GET_AP_CORE_NUMBER) CommonAssert, - #endif - #if TRANSFER_AP_CORE_NUMBER == TRUE - (PF_CPU_TRANSFER_AP_CORE_NUMBER) CommonVoid, - #else - (PF_CPU_TRANSFER_AP_CORE_NUMBER) CommonAssert, - #endif - #if ID_POSITION_INITIAL_APICID == TRUE - F12CpuAmdCoreIdPositionInInitialApicId, - #else - (PF_CORE_ID_POSITION_IN_INITIAL_APIC_ID) CommonAssert, - #endif - #if SAVE_FEATURES == TRUE - (PF_CPU_SAVE_FEATURES) CommonVoid, - #else - (PF_CPU_SAVE_FEATURES) CommonAssert, - #endif - #if WRITE_FEATURES == TRUE - (PF_CPU_WRITE_FEATURES) CommonVoid, - #else - (PF_CPU_WRITE_FEATURES) CommonAssert, - #endif - #if SET_WARM_RESET_FLAG == TRUE - F12SetAgesaWarmResetFlag, - #else - (PF_CPU_SET_WARM_RESET_FLAG) CommonAssert, - #endif - #if GET_WARM_RESET_FLAG == TRUE - F12GetAgesaWarmResetFlag, - #else - (PF_CPU_GET_WARM_RESET_FLAG) CommonAssert, - #endif - #if BRAND_STRING1 == TRUE - GetF12BrandIdString1, - #else - (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert, - #endif - #if BRAND_STRING2 == TRUE - GetF12BrandIdString2, - #else - (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert, - #endif - #if GET_PATCHES == TRUE - GetEmptyArray, - #else - (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert, - #endif - #if GET_PATCHES_EQUIVALENCE_TABLE == TRUE - GetEmptyArray, - #else - (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert, - #endif - #if GET_CACHE_INFO == TRUE - GetF12CacheInfo, - #else - (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert, - #endif - #if GET_SYSTEM_PM_TABLE == TRUE - GetF12SysPmTable, - #else - (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert, - #endif - #if GET_WHEA_INIT == TRUE - GetF12WheaInitData, - #else - (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert, - #endif - #if GET_PLATFORM_TYPE_SPECIFIC_INFO == TRUE - F12GetPlatformTypeSpecificInfo, - #else - (PF_CPU_GET_PLATFORM_TYPE_SPECIFIC_INFO) CommonAssert, - #endif - #if IS_NB_PSTATE_ENABLED == TRUE - F12IsNbPstateEnabled, - #else - (PF_IS_NB_PSTATE_ENABLED) CommonAssert, - #endif - #if (BASE_FAMILY_HT_PCI == TRUE) - (PF_NEXT_LINK_HAS_HTFPY_FEATS) CommonReturnFalse, - #else - (PF_NEXT_LINK_HAS_HTFPY_FEATS) CommonAssert, - #endif - #if (BASE_FAMILY_HT_PCI == TRUE) - (PF_SET_HT_PHY_REGISTER) CommonVoid, - #else - (PF_SET_HT_PHY_REGISTER) CommonAssert, - #endif - #if BASE_FAMILY_PCI == TRUE - (PF_GET_NEXT_HT_LINK_FEATURES) CommonReturnFalse, - #else - (PF_GET_NEXT_HT_LINK_FEATURES) CommonAssert, - #endif - #if USES_REGISTER_TABLES == TRUE - (REGISTER_TABLE **) F12UnknownRegisterTables, - #else - NULL, - #endif - #if USES_REGISTER_TABLES == TRUE - (TABLE_ENTRY_TYPE_DESCRIPTOR *) F12UnknownTableEntryTypeDescriptors, - #else - NULL, - #endif - #if MODEL_SPECIFIC_HT_PCI == TRUE - NULL, - #else - NULL, - #endif - NULL, - InitCacheDisabled, - #if AGESA_ENTRY_INIT_EARLY == TRUE - GetCommonEarlyInitOnCoreTable - #else - (PF_GET_EARLY_INIT_TABLE) CommonVoid - #endif -}; - - // Family 12h maximum base address is 40 bits. Limit BLDCFG to 40 bits, if appropriate. -#if (FAMILY_MMIO_BASE_MASK < 0xFFFFFF0000000000ull) - #undef FAMILY_MMIO_BASE_MASK - #define FAMILY_MMIO_BASE_MASK (0xFFFFFF0000000000ull) -#endif - -#undef OPT_F12_ID_TABLE -#define OPT_F12_ID_TABLE {0x12ul, {AMD_FAMILY_12, AMD_F12_UNKNOWN}, F12LogicalIdTable, (sizeof (F12LogicalIdTable) / sizeof (F12LogicalIdTable[0]))}, -#define OPT_F12_UNKNOWN_CPU {AMD_FAMILY_12, &cpuF12UnknownServices}, - -#undef OPT_F12_TABLE -#define OPT_F12_TABLE OPT_F12_LN_CPU OPT_F12_UNKNOWN_CPU - -#if OPTION_FS1_SOCKET_SUPPORT == TRUE - extern CONST CPU_BRAND_TABLE ROMDATA F12LnBrandIdString1ArrayFs1; - extern CONST CPU_BRAND_TABLE ROMDATA F12LnBrandIdString2ArrayFs1; - #define F12_FS1_BRANDSTRING1 &F12LnBrandIdString1ArrayFs1, - #define F12_FS1_BRANDSTRING2 &F12LnBrandIdString2ArrayFs1, -#else - #define F12_FS1_BRANDSTRING1 - #define F12_FS1_BRANDSTRING2 -#endif -#if OPTION_FM1_SOCKET_SUPPORT == TRUE - extern CONST CPU_BRAND_TABLE ROMDATA F12LnBrandIdString1ArrayFm1; - extern CONST CPU_BRAND_TABLE ROMDATA F12LnBrandIdString2ArrayFm1; - #define F12_FM1_BRANDSTRING1 &F12LnBrandIdString1ArrayFm1, - #define F12_FM1_BRANDSTRING2 &F12LnBrandIdString2ArrayFm1, -#else - #define F12_FM1_BRANDSTRING1 - #define F12_FM1_BRANDSTRING2 -#endif -#if OPTION_FP1_SOCKET_SUPPORT == TRUE - #define F12_FP1_BRANDSTRING1 NULL, - #define F12_FP1_BRANDSTRING2 NULL, -#else - #define F12_FP1_BRANDSTRING1 - #define F12_FP1_BRANDSTRING2 -#endif - -#if BRAND_STRING1 == TRUE - CONST CPU_BRAND_TABLE ROMDATA *F12BrandIdString1Tables[] = - { - F12_FS1_BRANDSTRING1 - F12_FM1_BRANDSTRING1 - F12_FP1_BRANDSTRING1 - }; - - CONST UINT8 F12BrandIdString1TableCount = (sizeof (F12BrandIdString1Tables) / sizeof (F12BrandIdString1Tables[0])); -#endif - -#if BRAND_STRING2 == TRUE - CONST CPU_BRAND_TABLE ROMDATA *F12BrandIdString2Tables[] = - { - F12_FS1_BRANDSTRING2 - F12_FM1_BRANDSTRING2 - F12_FP1_BRANDSTRING2 - }; - - CONST UINT8 F12BrandIdString2TableCount = (sizeof (F12BrandIdString2Tables) / sizeof (F12BrandIdString2Tables[0])); -#endif - -CONST PF_CPU_GET_SUBFAMILY_ID_ARRAY ROMDATA F12LogicalIdTable[] = -{ - OPT_F12_LN_ID -}; - -#endif // _OPTION_FAMILY_12H_INSTALL_H_ diff --git a/src/vendorcode/amd/agesa/f12/Config/OptionFchInstall.h b/src/vendorcode/amd/agesa/f12/Config/OptionFchInstall.h deleted file mode 100644 index f1799f6507..0000000000 --- a/src/vendorcode/amd/agesa/f12/Config/OptionFchInstall.h +++ /dev/null @@ -1,928 +0,0 @@ -/********************************************************************************* -; -* Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -;*********************************************************************************/ - -#ifndef _OPTION_FCH_INSTALL_H_ -#define _OPTION_FCH_INSTALL_H_ - -#include "AmdFch.h" - -#ifndef FCH_SUPPORT - #define FCH_SUPPORT FALSE -#endif - - -/* ACPI block register offset definitions */ -#define PM1_STATUS_OFFSET 0x00 -#define PM1_ENABLE_OFFSET 0x02 -#define PM_CONTROL_OFFSET 0x04 -#define PM_TIMER_OFFSET 0x08 -#define CPU_CONTROL_OFFSET 0x10 -#define EVENT_STATUS_OFFSET 0x20 -#define EVENT_ENABLE_OFFSET 0x24 - - -#if FCH_SUPPORT == TRUE - /* - * FCH subfunctions - */ - #ifdef AGESA_ENTRY_INIT_RESET - #if AGESA_ENTRY_INIT_RESET == TRUE - extern FCH_TASK_ENTRY FchInitResetHwAcpiP; - extern FCH_TASK_ENTRY FchInitResetHwAcpi; - extern FCH_TASK_ENTRY FchInitResetAb; - extern FCH_TASK_ENTRY FchInitResetSpi; - extern FCH_TASK_ENTRY FchInitResetGec; - extern FCH_TASK_ENTRY FchInitResetSata; - extern FCH_TASK_ENTRY FchInitResetLpc; - extern FCH_TASK_ENTRY FchInitResetPcib; - extern FCH_TASK_ENTRY FchInitResetPcie; - extern FCH_TASK_ENTRY FchInitResetGpp; - extern FCH_TASK_ENTRY FchInitResetUsb; - extern FCH_TASK_ENTRY FchInitResetEhci; - extern FCH_TASK_ENTRY FchInitResetOhci; - extern FCH_TASK_ENTRY FchInitResetXhci; - extern FCH_TASK_ENTRY FchInitResetImc; - #endif - #endif - - #ifdef AGESA_ENTRY_INIT_ENV - #if AGESA_ENTRY_INIT_ENV == TRUE - extern FCH_TASK_ENTRY FchInitEnvUsbXhci; - extern FCH_TASK_ENTRY FchInitEnvUsbOhci; - extern FCH_TASK_ENTRY FchInitEnvUsbEhci; - extern FCH_TASK_ENTRY FchInitEnvUsb; - extern FCH_TASK_ENTRY FchInitEnvAb; - extern FCH_TASK_ENTRY FchInitEnvGpp; - extern FCH_TASK_ENTRY FchInitEnvPcie; - extern FCH_TASK_ENTRY FchInitEnvPcib; - extern FCH_TASK_ENTRY FchInitEnvHwAcpiP; - extern FCH_TASK_ENTRY FchInitEnvHwAcpi; - extern FCH_TASK_ENTRY FchInitEnvAbSpecial; - extern FCH_TASK_ENTRY FchInitEnvSpi; - extern FCH_TASK_ENTRY FchInitEnvGec; - extern FCH_TASK_ENTRY FchInitEnvSata; - extern FCH_TASK_ENTRY FchInitEnvIde; - extern FCH_TASK_ENTRY FchInitEnvSd; - extern FCH_TASK_ENTRY FchInitEnvIr; - extern FCH_TASK_ENTRY FchInitEnvAzalia; - extern FCH_TASK_ENTRY FchInitEnvHwm; - extern FCH_TASK_ENTRY FchInitEnvImc; - #endif - #endif - - #ifdef AGESA_ENTRY_INIT_MID - #if AGESA_ENTRY_INIT_MID == TRUE - extern FCH_TASK_ENTRY FchInitMidHwm; - extern FCH_TASK_ENTRY FchInitMidAzalia; - extern FCH_TASK_ENTRY FchInitMidGec; - extern FCH_TASK_ENTRY FchInitMidSata; - extern FCH_TASK_ENTRY FchInitMidIde; - extern FCH_TASK_ENTRY FchInitMidAb; - extern FCH_TASK_ENTRY FchInitMidUsb; - extern FCH_TASK_ENTRY FchInitMidUsbEhci; - extern FCH_TASK_ENTRY FchInitMidUsbOhci; - extern FCH_TASK_ENTRY FchInitMidUsbXhci; - extern FCH_TASK_ENTRY FchInitMidImc; - #endif - #endif - - #ifdef AGESA_ENTRY_INIT_LATE - #if AGESA_ENTRY_INIT_LATE == TRUE - extern FCH_TASK_ENTRY FchInitLateHwAcpi; - extern FCH_TASK_ENTRY FchInitLateSpi; - extern FCH_TASK_ENTRY FchInitLateGec; - extern FCH_TASK_ENTRY FchInitLateSata; - extern FCH_TASK_ENTRY FchInitLateIde; - extern FCH_TASK_ENTRY FchInitLatePcib; - extern FCH_TASK_ENTRY FchInitLateAb; - extern FCH_TASK_ENTRY FchInitLatePcie; - extern FCH_TASK_ENTRY FchInitLateGpp; - extern FCH_TASK_ENTRY FchInitLateUsb; - extern FCH_TASK_ENTRY FchInitLateUsbEhci; - extern FCH_TASK_ENTRY FchInitLateUsbOhci; - extern FCH_TASK_ENTRY FchInitLateUsbXhci; - extern FCH_TASK_ENTRY FchInitLateImc; - extern FCH_TASK_ENTRY FchInitLateAzalia; - extern FCH_TASK_ENTRY FchInitLateHwm; - #endif - #endif - - extern FCH_TASK_ENTRY FchTaskDummy; - /* FCH Interface entries */ - extern FCH_INIT CommonFchInitStub; - - /* FCH Interface entries */ - #ifdef AGESA_ENTRY_INIT_RESET - #if AGESA_ENTRY_INIT_RESET == TRUE - extern FCH_INIT FchInitReset; - extern FCH_INIT FchResetConstructor; - - #define FP_FCH_INIT_RESET &FchInitReset - #define FP_FCH_INIT_RESET_CONSTRUCT &FchResetConstructor - #else - #define FP_FCH_INIT_RESET &CommonFchInitStub - #define FP_FCH_INIT_RESET_CONSTRUCT &CommonFchInitStub - #endif - #endif - - #ifdef AGESA_ENTRY_INIT_ENV - #if AGESA_ENTRY_INIT_ENV == TRUE - extern FCH_INIT FchInitEnv; - extern FCH_INIT FchEnvConstructor; - - #define FP_FCH_INIT_ENV &FchInitEnv - #define FP_FCH_INIT_ENV_CONSTRUCT &FchEnvConstructor - #else - #define FP_FCH_INIT_ENV &CommonFchInitStub - #define FP_FCH_INIT_ENV_CONSTRUCT &CommonFchInitStub - #endif - #endif - - #ifdef AGESA_ENTRY_INIT_MID - #if AGESA_ENTRY_INIT_MID == TRUE - extern FCH_INIT FchInitMid; - extern FCH_INIT FchMidConstructor; - - #define FP_FCH_INIT_MID &FchInitMid - #define FP_FCH_INIT_MID_CONSTRUCT &FchMidConstructor - #else - #define FP_FCH_INIT_MID &CommonFchInitStub - #define FP_FCH_INIT_MID_CONSTRUCT &CommonFchInitStub - #endif - #endif - - #ifdef AGESA_ENTRY_INIT_LATE - #if AGESA_ENTRY_INIT_LATE == TRUE - extern FCH_INIT FchInitLate; - extern FCH_INIT FchLateConstructor; - - #define FP_FCH_INIT_LATE &FchInitLate - #define FP_FCH_INIT_LATE_CONSTRUCT &FchLateConstructor - #else - #define FP_FCH_INIT_LATE &CommonFchInitStub - #define FP_FCH_INIT_LATE_CONSTRUCT &CommonFchInitStub - #endif - #endif - - /* FCH subcomponent build options */ - #undef FCH_NO_HWACPI_SUPPORT - #undef FCH_NO_AB_SUPPORT - #undef FCH_NO_SPI_SUPPORT - #undef FCH_NO_GEC_SUPPORT - #undef FCH_NO_SATA_SUPPORT - #undef FCH_NO_IDE_SUPPORT - #undef FCH_NO_LPC_SUPPORT - #undef FCH_NO_PCIB_SUPPORT - #undef FCH_NO_PCIE_SUPPORT - #undef FCH_NO_GPP_SUPPORT - #undef FCH_NO_USB_SUPPORT - #undef FCH_NO_EHCI_SUPPORT - #undef FCH_NO_OHCI_SUPPORT - #undef FCH_NO_XHCI_SUPPORT - #undef FCH_NO_IMC_SUPPORT - #undef FCH_NO_SD_SUPPORT - #undef FCH_NO_IR_SUPPORT - #undef FCH_NO_AZALIA_SUPPORT - #undef FCH_NO_HWM_SUPPORT - - // Following are determined by silicon characteristics - #if (OPTION_FAMILY14H_KR == TRUE) - #define FCH_NO_GPP_SUPPORT TRUE - #define FCH_NO_PCIB_SUPPORT TRUE - #define FCH_NO_PCIE_SUPPORT TRUE - - #else - #if (OPTION_FAMILY15H_TN == TRUE) - //#define FCH_NO_GEC_SUPPORT TRUE - #else - #error FCH_SUPPORT: No chip type selected. - #endif - #endif - - - // - // Installable blocks depending on build switches - // - #ifndef FCH_NO_HWACPI_SUPPORT - #define BLOCK_HWACPI_SIZE sizeof (FCH_ACPI) - #define InstallFchInitResetHwAcpiP &FchInitResetHwAcpiP - #define InstallFchInitResetHwAcpi &FchInitResetHwAcpi - #define InstallFchInitEnvHwAcpiP &FchInitEnvHwAcpiP - #define InstallFchInitEnvHwAcpi &FchInitEnvHwAcpi - #define InstallFchInitMidHwAcpi &FchTaskDummy - #define InstallFchInitLateHwAcpi &FchInitLateHwAcpi - #else - #define BLOCK_HWACPI_SIZE 0 - #define InstallFchInitResetHwAcpiP &FchTaskDummy - #define InstallFchInitResetHwAcpi &FchTaskDummy - #define InstallFchInitEnvHwAcpi &FchTaskDummy - #define InstallFchInitMidHwAcpi &FchTaskDummy - #define InstallFchInitLateHwAcpi &FchTaskDummy - #endif - - #ifndef FCH_NO_AB_SUPPORT - #define BLOCK_AB_SIZE sizeof (FCH_AB) - #define InstallFchInitResetAb &FchInitResetAb - #define InstallFchInitEnvAb &FchInitEnvAb - #define InstallFchInitEnvAbS &FchInitEnvAbSpecial - #define InstallFchInitMidAb &FchInitMidAb - #define InstallFchInitLateAb &FchInitLateAb - #else - #define BLOCK_AB_SIZE 0 - #define InstallFchInitResetAb &FchTaskDummy - #define InstallFchInitEnvAb &FchTaskDummy - #define InstallFchInitEnvAbS &FchTaskDummy - #define InstallFchInitMidAb &FchTaskDummy - #define InstallFchInitLateAb &FchTaskDummy - #endif - - #ifndef FCH_NO_SPI_SUPPORT - #define BLOCK_SPI_SIZE sizeof (FCH_SPI) - #define InstallFchInitResetSpi &FchInitResetSpi - #define InstallFchInitEnvSpi &FchInitEnvSpi - #define InstallFchInitMidSpi &FchTaskDummy - #define InstallFchInitLateSpi &FchInitLateSpi - #else - #define BLOCK_SPI_SIZE 0 - #define InstallFchInitResetSpi &FchTaskDummy - #define InstallFchInitEnvSpi &FchTaskDummy - #define InstallFchInitMidSpi &FchTaskDummy - #define InstallFchInitLateSpi &FchTaskDummy - #endif - - #ifndef FCH_NO_GEC_SUPPORT - #define BLOCK_GEC_SIZE sizeof (FCH_GEC) - #define InstallFchInitResetGec &FchInitResetGec - #define InstallFchInitEnvGec &FchInitEnvGec - #define InstallFchInitMidGec &FchInitMidGec - #define InstallFchInitLateGec &FchInitLateGec - #else - #define BLOCK_GEC_SIZE 0 - #define InstallFchInitResetGec &FchTaskDummy - #define InstallFchInitEnvGec &FchTaskDummy - #define InstallFchInitMidGec &FchTaskDummy - #define InstallFchInitLateGec &FchTaskDummy - #endif - - #ifndef FCH_NO_SATA_SUPPORT - #define BLOCK_SATA_SIZE sizeof (FCH_SATA) - #define InstallFchInitResetSata &FchInitResetSata - #define InstallFchInitEnvSata &FchInitEnvSata - #define InstallFchInitMidSata &FchInitMidSata - #define InstallFchInitLateSata &FchInitLateSata - #else - #define BLOCK_SATA_SIZE 0 - #define InstallFchInitResetSata &FchTaskDummy - #define InstallFchInitEnvSata &FchTaskDummy - #define InstallFchInitMidSata &FchTaskDummy - #define InstallFchInitLateSata &FchTaskDummy - #endif - - #ifndef FCH_NO_IDE_SUPPORT - #define BLOCK_IDE_SIZE sizeof (FCH_IDE) - #define InstallFchInitResetIde &FchTaskDummy - #define InstallFchInitEnvIde &FchInitEnvIde - #define InstallFchInitMidIde &FchInitMidIde - #define InstallFchInitLateIde &FchInitLateIde - #else - #define BLOCK_IDE_SIZE 0 - #define InstallFchInitResetIde &FchTaskDummy - #define InstallFchInitEnvIde &FchTaskDummy - #define InstallFchInitMidIde &FchTaskDummy - #define InstallFchInitLateIde &FchTaskDummy - #endif - - #ifndef FCH_NO_LPC_SUPPORT - #define BLOCK_LPC_SIZE sizeof (FCH_LPC) - #define InstallFchInitResetLpc &FchInitResetLpc - #define InstallFchInitEnvLpc &FchTaskDummy - #define InstallFchInitMidLpc &FchTaskDummy - #define InstallFchInitLateLpc &FchTaskDummy - #else - #define BLOCK_LPC_SIZE 0 - #define InstallFchInitResetLpc &FchTaskDummy - #define InstallFchInitEnvLpc &FchTaskDummy - #define InstallFchInitMidLpc &FchTaskDummy - #define InstallFchInitLateLpc &FchTaskDummy - #endif - - #ifndef FCH_NO_PCIB_SUPPORT - #define BLOCK_PCIB_SIZE sizeof (FCH_PCIB) - #define InstallFchInitResetPcib &FchInitResetPcib - #define InstallFchInitEnvPcib &FchInitEnvPcib - #define InstallFchInitMidPcib &FchTaskDummy - #define InstallFchInitLatePcib &FchInitLatePcib - #else - #define BLOCK_PCIB_SIZE 0 - #define InstallFchInitResetPcib &FchTaskDummy - #define InstallFchInitEnvPcib &FchTaskDummy - #define InstallFchInitMidPcib &FchTaskDummy - #define InstallFchInitLatePcib &FchTaskDummy - #endif - - #ifndef FCH_NO_PCIE_SUPPORT - #define InstallFchInitResetPcie &FchInitResetPcie - #define InstallFchInitEnvPcie &FchInitEnvPcie - #define InstallFchInitMidPcie &FchTaskDummy - #define InstallFchInitLatePcie &FchInitLatePcie - #else - #define InstallFchInitResetPcie &FchTaskDummy - #define InstallFchInitEnvPcie &FchTaskDummy - #define InstallFchInitMidPcie &FchTaskDummy - #define InstallFchInitLatePcie &FchTaskDummy - #endif - - #ifndef FCH_NO_GPP_SUPPORT - #define BLOCK_GPP_SIZE sizeof (FCH_GPP) - #define InstallFchInitResetGpp &FchInitResetGpp - #define InstallFchInitEnvGpp &FchInitEnvGpp - #define InstallFchInitMidGpp &FchTaskDummy - #define InstallFchInitLateGpp &FchInitLateGpp - #else - #define BLOCK_GPP_SIZE 0 - #define InstallFchInitResetGpp &FchTaskDummy - #define InstallFchInitEnvGpp &FchTaskDummy - #define InstallFchInitMidGpp &FchTaskDummy - #define InstallFchInitLateGpp &FchTaskDummy - #endif - - #ifndef FCH_NO_USB_SUPPORT - #define BLOCK_USB_SIZE sizeof (FCH_USB) - #define InstallFchInitResetUsb &FchInitResetUsb - #define InstallFchInitEnvUsb &FchInitEnvUsb - #define InstallFchInitMidUsb &FchInitMidUsb - #define InstallFchInitLateUsb &FchInitLateUsb - #else - #define BLOCK_USB_SIZE 0 - #define InstallFchInitResetUsb &FchTaskDummy - #define InstallFchInitEnvUsb &FchTaskDummy - #define InstallFchInitMidUsb &FchTaskDummy - #define InstallFchInitLateUsb &FchTaskDummy - #endif - - #ifndef FCH_NO_EHCI_SUPPORT - #define InstallFchInitResetUsbEhci &FchInitResetEhci - #define InstallFchInitEnvUsbEhci &FchInitEnvUsbEhci - #define InstallFchInitMidUsbEhci &FchInitMidUsbEhci - #define InstallFchInitLateUsbEhci &FchInitLateUsbEhci - #else - #define InstallFchInitResetUsbEhci &FchTaskDummy - #define InstallFchInitEnvUsbEhci &FchTaskDummy - #define InstallFchInitMidUsbEhci &FchTaskDummy - #define InstallFchInitLateUsbEhci &FchTaskDummy - #endif - - #ifndef FCH_NO_OHCI_SUPPORT - #define InstallFchInitResetUsbOhci &FchInitResetOhci - #define InstallFchInitEnvUsbOhci &FchInitEnvUsbOhci - #define InstallFchInitMidUsbOhci &FchInitMidUsbOhci - #define InstallFchInitLateUsbOhci &FchInitLateUsbOhci - #else - #define InstallFchInitResetUsbOhci &FchTaskDummy - #define InstallFchInitEnvUsbOhci &FchTaskDummy - #define InstallFchInitMidUsbOhci &FchTaskDummy - #define InstallFchInitLateUsbOhci &FchTaskDummy - #endif - - #ifndef FCH_NO_XHCI_SUPPORT - #define InstallFchInitResetUsbXhci &FchInitResetXhci - #define InstallFchInitEnvUsbXhci &FchInitEnvUsbXhci - #define InstallFchInitMidUsbXhci &FchInitMidUsbXhci - #define InstallFchInitLateUsbXhci &FchInitLateUsbXhci - #else - #define InstallFchInitResetUsbXhci &FchTaskDummy - #define InstallFchInitEnvUsbXhci &FchTaskDummy - #define InstallFchInitMidUsbXhci &FchTaskDummy - #define InstallFchInitLateUsbXhci &FchTaskDummy - #endif - - #ifndef FCH_NO_IMC_SUPPORT - #define BLOCK_IMC_SIZE sizeof (FCH_IMC) - #define InstallFchInitResetImc &FchInitResetImc - #define InstallFchInitEnvImc &FchInitEnvImc - #define InstallFchInitMidImc &FchInitMidImc - #define InstallFchInitLateImc &FchInitLateImc - #else - #define BLOCK_IMC_SIZE 0 - #define InstallFchInitResetImc &FchTaskDummy - #define InstallFchInitEnvImc &FchTaskDummy - #define InstallFchInitMidImc &FchTaskDummy - #define InstallFchInitLateImc &FchTaskDummy - #endif - - - #ifndef FCH_NO_SD_SUPPORT - #define BLOCK_SD_SIZE sizeof (FCH_SD) - #define InstallFchInitResetSd &FchTaskDummy - #define InstallFchInitEnvSd &FchInitEnvSd - #define InstallFchInitMidSd &FchTaskDummy - #define InstallFchInitLateSd &FchTaskDummy - #else - #define BLOCK_SD_SIZE 0 - #define InstallFchInitResetSd &FchTaskDummy - #define InstallFchInitEnvSd &FchTaskDummy - #define InstallFchInitMidSd &FchTaskDummy - #define InstallFchInitLateSd &FchTaskDummy - #endif - - #ifndef FCH_NO_IR_SUPPORT - #define BLOCK_IR_SIZE sizeof (FCH_IR) - #define InstallFchInitResetIr &FchTaskDummy - #define InstallFchInitEnvIr &FchInitEnvIr - #define InstallFchInitMidIr &FchTaskDummy - #define InstallFchInitLateIr &FchTaskDummy - #else - #define BLOCK_IR_SIZE 0 - #define InstallFchInitResetIr &FchTaskDummy - #define InstallFchInitEnvIr &FchTaskDummy - #define InstallFchInitMidIr &FchTaskDummy - #define InstallFchInitLateIr &FchTaskDummy - #endif - - #ifndef FCH_NO_AZALIA_SUPPORT - #define BLOCK_AZALIA_SIZE sizeof (FCH_AZALIA) - #define InstallFchInitResetAzalia &FchTaskDummy - #define InstallFchInitEnvAzalia &FchInitEnvAzalia - #define InstallFchInitMidAzalia &FchInitMidAzalia - #define InstallFchInitLateAzalia &FchInitLateAzalia - #else - #define BLOCK_AZALIA_SIZE 0 - #define InstallFchInitResetAzalia &FchTaskDummy - #define InstallFchInitEnvAzalia &FchTaskDummy - #define InstallFchInitMidAzalia &FchTaskDummy - #define InstallFchInitLateAzalia &FchTaskDummy - #endif - - #ifndef FCH_NO_HWM_SUPPORT - #define BLOCK_HWM_SIZE sizeof (FCH_HWM) - #define InstallFchInitResetHwm &FchTaskDummy - #define InstallFchInitEnvHwm &FchInitEnvHwm - #define InstallFchInitMidHwm &FchInitMidHwm - #define InstallFchInitLateHwm &FchInitLateHwm - #else - #define InstallFchInitResetHwm &FchTaskDummy - #define InstallFchInitEnvHwm &FchTaskDummy - #define InstallFchInitMidHwm &FchTaskDummy - #define InstallFchInitLateHwm &FchTaskDummy - #endif - - - #define BLOCK_SMBUS_SIZE sizeof (FCH_SMBUS) - #define BLOCK_HPET_SIZE sizeof (FCH_HPET) - #define BLOCK_GCPU_SIZE sizeof (FCH_GCPU) - #define BLOCK_SDB_SIZE sizeof (FCH_SERIALDB) - #define BLOCK_MISC_SIZE sizeof (FCH_MISC) - - - // Optionally declare OEM hooks after each phase - #ifndef FCH_INIT_RESET_HOOK - #define InstallFchInitResetHook FchTaskDummy - #else - #define InstallFchInitResetHook OemFchInitResetHook - #endif - - - // - // Define FCH build time options and configurations - // - #ifdef BLDCFG_SMBUS0_BASE_ADDRESS - #define CFG_SMBUS0_BASE_ADDRESS BLDCFG_SMBUS0_BASE_ADDRESS - #else - #define CFG_SMBUS0_BASE_ADDRESS DFLT_SMBUS0_BASE_ADDRESS - #endif - - #ifdef BLDCFG_SMBUS1_BASE_ADDRESS - #define CFG_SMBUS1_BASE_ADDRESS BLDCFG_SMBUS1_BASE_ADDRESS - #else - #define CFG_SMBUS1_BASE_ADDRESS DFLT_SMBUS1_BASE_ADDRESS - #endif - - #ifdef BLDCFG_SIO_PME_BASE_ADDRESS - #define CFG_SIO_PME_BASE_ADDRESS BLDCFG_SIO_PME_BASE_ADDRESS - #else - #define CFG_SIO_PME_BASE_ADDRESS DFLT_SIO_PME_BASE_ADDRESS - #endif - - #ifdef BLDCFG_ACPI_PM1_EVT_BLOCK_ADDRESS - #define CFG_ACPI_PM1_EVT_BLOCK_ADDRESS BLDCFG_ACPI_PM1_EVT_BLOCK_ADDRESS - #else - #define CFG_ACPI_PM1_EVT_BLOCK_ADDRESS DFLT_ACPI_PM1_EVT_BLOCK_ADDRESS - #endif - #ifdef BLDCFG_ACPI_PM1_CNT_BLOCK_ADDRESS - #define CFG_ACPI_PM1_CNT_BLOCK_ADDRESS BLDCFG_ACPI_PM1_CNT_BLOCK_ADDRESS - #else - #define CFG_ACPI_PM1_CNT_BLOCK_ADDRESS DFLT_ACPI_PM1_CNT_BLOCK_ADDRESS - #endif - #ifdef BLDCFG_ACPI_PM_TMR_BLOCK_ADDRESS - #define CFG_ACPI_PM_TMR_BLOCK_ADDRESS BLDCFG_ACPI_PM_TMR_BLOCK_ADDRESS - #else - #define CFG_ACPI_PM_TMR_BLOCK_ADDRESS DFLT_ACPI_PM_TMR_BLOCK_ADDRESS - #endif - #ifdef BLDCFG_ACPI_CPU_CNT_BLOCK_ADDRESS - #define CFG_ACPI_CPU_CNT_BLOCK_ADDRESS BLDCFG_ACPI_CPU_CNT_BLOCK_ADDRESS - #else - #define CFG_ACPI_CPU_CNT_BLOCK_ADDRESS DFLT_ACPI_CPU_CNT_BLOCK_ADDRESS - #endif - #ifdef BLDCFG_ACPI_GPE0_BLOCK_ADDRESS - #define CFG_ACPI_GPE0_BLOCK_ADDRESS BLDCFG_ACPI_GPE0_BLOCK_ADDRESS - #else - #define CFG_ACPI_GPE0_BLOCK_ADDRESS DFLT_ACPI_GPE0_BLOCK_ADDRESS - #endif - - - #ifdef BLDCFG_WATCHDOG_TIMER_BASE - #define CFG_WATCHDOG_TIMER_BASE BLDCFG_WATCHDOG_TIMER_BASE - #else - #define CFG_WATCHDOG_TIMER_BASE DFLT_WATCHDOG_TIMER_BASE_ADDRESS - #endif - - #ifdef BLDCFG_ACPI_PMA_BLK_ADDRESS - #define CFG_ACPI_PMA_CNTBLK_ADDRESS BLDCFG_ACPI_PMA_BLK_ADDRESS - #else - #define CFG_ACPI_PMA_CNTBLK_ADDRESS DFLT_ACPI_PMA_CNT_BLK_ADDRESS - #endif - - #ifdef BLDCFG_SMI_CMD_PORT_ADDRESS - #define CFG_SMI_CMD_PORT_ADDRESS BLDCFG_SMI_CMD_PORT_ADDRESS - #else - #define CFG_SMI_CMD_PORT_ADDRESS DFLT_SMI_CMD_PORT - #endif - - #ifdef BLDCFG_ROM_BASE_ADDRESS - #define CFG_SPI_ROM_BASE_ADDRESS BLDCFG_ROM_BASE_ADDRESS - #else - #define CFG_SPI_ROM_BASE_ADDRESS DFLT_SPI_BASE_ADDRESS - #endif - - #ifdef BLDCFG_GEC_SHADOW_ROM_BASE - #define CFG_GEC_SHADOW_ROM_BASE BLDCFG_GEC_SHADOW_ROM_BASE - #else - #define CFG_GEC_SHADOW_ROM_BASE DFLT_GEC_BASE_ADDRESS - #endif - - #ifdef BLDCFG_HPET_BASE_ADDRESS - #define CFG_HPET_BASE_ADDRESS BLDCFG_HPET_BASE_ADDRESS - #else - #define CFG_HPET_BASE_ADDRESS DFLT_HPET_BASE_ADDRESS - #endif - - #ifdef BLDCFG_AZALIA_SSID - #define CFG_AZALIA_SSID BLDCFG_AZALIA_SSID - #else - #define CFG_AZALIA_SSID DFLT_AZALIA_SSID - #endif - - #ifdef BLDCFG_SMBUS_SSID - #define CFG_SMBUS_SSID BLDCFG_SMBUS_SSID - #else - #define CFG_SMBUS_SSID DFLT_SMBUS_SSID - #endif - - #ifdef BLDCFG_IDE_SSID - #define CFG_IDE_SSID BLDCFG_IDE_SSID - #else - #define CFG_IDE_SSID DFLT_IDE_SSID - #endif - - #ifdef BLDCFG_SATA_AHCI_SSID - #define CFG_SATA_AHCI_SSID BLDCFG_SATA_AHCI_SSID - #else - #define CFG_SATA_AHCI_SSID DFLT_SATA_AHCI_SSID - #endif - - #ifdef BLDCFG_SATA_IDE_SSID - #define CFG_SATA_IDE_SSID BLDCFG_SATA_IDE_SSID - #else - #define CFG_SATA_IDE_SSID DFLT_SATA_IDE_SSID - #endif - - #ifdef BLDCFG_SATA_RAID5_SSID - #define CFG_SATA_RAID5_SSID BLDCFG_SATA_RAID5_SSID - #else - #define CFG_SATA_RAID5_SSID DFLT_SATA_RAID5_SSID - #endif - - #ifdef BLDCFG_SATA_RAID_SSID - #define CFG_SATA_RAID_SSID BLDCFG_SATA_RAID_SSID - #else - #define CFG_SATA_RAID_SSID DFLT_SATA_RAID_SSID - #endif - - #ifdef BLDCFG_EHCI_SSID - #define CFG_EHCI_SSID BLDCFG_EHCI_SSID - #else - #define CFG_EHCI_SSID DFLT_EHCI_SSID - #endif - - #ifdef BLDCFG_OHCI_SSID - #define CFG_OHCI_SSID BLDCFG_OHCI_SSID - #else - #define CFG_OHCI_SSID DFLT_OHCI_SSID - #endif - - #ifdef BLDCFG_LPC_SSID - #define CFG_LPC_SSID BLDCFG_LPC_SSID - #else - #define CFG_LPC_SSID DFLT_LPC_SSID - #endif - - #ifdef BLDCFG_FCH_GPP_LINK_CONFIG - #define CFG_FCH_GPP_LINK_CONFIG BLDCFG_FCH_GPP_LINK_CONFIG - #else - #define CFG_FCH_GPP_LINK_CONFIG DFLT_FCH_GPP_LINK_CONFIG - #endif - - #ifdef BLDCFG_FCH_GPP_PORT0_PRESENT - #define CFG_FCH_GPP_PORT0_PRESENT BLDCFG_FCH_GPP_PORT0_PRESENT - #else - #define CFG_FCH_GPP_PORT0_PRESENT DFLT_FCH_GPP_PORT0_PRESENT - #endif - - #ifdef BLDCFG_FCH_GPP_PORT1_PRESENT - #define CFG_FCH_GPP_PORT1_PRESENT BLDCFG_FCH_GPP_PORT1_PRESENT - #else - #define CFG_FCH_GPP_PORT1_PRESENT DFLT_FCH_GPP_PORT1_PRESENT - #endif - - #ifdef BLDCFG_FCH_GPP_PORT2_PRESENT - #define CFG_FCH_GPP_PORT2_PRESENT BLDCFG_FCH_GPP_PORT2_PRESENT - #else - #define CFG_FCH_GPP_PORT2_PRESENT DFLT_FCH_GPP_PORT2_PRESENT - #endif - - #ifdef BLDCFG_FCH_GPP_PORT3_PRESENT - #define CFG_FCH_GPP_PORT3_PRESENT BLDCFG_FCH_GPP_PORT3_PRESENT - #else - #define CFG_FCH_GPP_PORT3_PRESENT DFLT_FCH_GPP_PORT3_PRESENT - #endif - - #ifdef BLDCFG_FCH_GPP_PORT0_HOTPLUG - #define CFG_FCH_GPP_PORT0_HOTPLUG BLDCFG_FCH_GPP_PORT0_HOTPLUG - #else - #define CFG_FCH_GPP_PORT0_HOTPLUG DFLT_FCH_GPP_PORT0_HOTPLUG - #endif - - #ifdef BLDCFG_FCH_GPP_PORT1_HOTPLUG - #define CFG_FCH_GPP_PORT1_HOTPLUG BLDCFG_FCH_GPP_PORT1_HOTPLUG - #else - #define CFG_FCH_GPP_PORT1_HOTPLUG DFLT_FCH_GPP_PORT1_HOTPLUG - #endif - - #ifdef BLDCFG_FCH_GPP_PORT2_HOTPLUG - #define CFG_FCH_GPP_PORT2_HOTPLUG BLDCFG_FCH_GPP_PORT2_HOTPLUG - #else - #define CFG_FCH_GPP_PORT2_HOTPLUG DFLT_FCH_GPP_PORT2_HOTPLUG - #endif - - #ifdef BLDCFG_FCH_GPP_PORT3_HOTPLUG - #define CFG_FCH_GPP_PORT3_HOTPLUG BLDCFG_FCH_GPP_PORT3_HOTPLUG - #else - #define CFG_FCH_GPP_PORT3_HOTPLUG DFLT_FCH_GPP_PORT3_HOTPLUG - #endif - - - #ifdef AGESA_ENTRY_INIT_RESET - #if AGESA_ENTRY_INIT_RESET == TRUE - // - // Define task list for InitReset phase - // - FCH_TASK_ENTRY ROMDATA *FchInitResetTaskTable[] = { - InstallFchInitResetHwAcpiP, - InstallFchInitResetAb, - InstallFchInitResetSpi, - InstallFchInitResetGec, - InstallFchInitResetHwAcpi, - InstallFchInitResetSata, - InstallFchInitResetLpc, - InstallFchInitResetPcib, - InstallFchInitResetPcie, - InstallFchInitResetGpp, - InstallFchInitResetUsb, - InstallFchInitResetUsbEhci, - InstallFchInitResetUsbOhci, - InstallFchInitResetUsbXhci, - InstallFchInitResetImc, - NULL - }; - #endif - #endif - - #ifdef AGESA_ENTRY_INIT_ENV - #if AGESA_ENTRY_INIT_ENV == TRUE - // - // Define task list for InitEnv phase - // - FCH_TASK_ENTRY ROMDATA *FchInitEnvTaskTable[] = { - InstallFchInitEnvHwAcpiP, - InstallFchInitEnvPcib, - InstallFchInitEnvPcie, - InstallFchInitEnvIr, - InstallFchInitEnvHwAcpi, - InstallFchInitEnvSpi, - InstallFchInitEnvSd, - InstallFchInitEnvImc, - InstallFchInitEnvUsb, - InstallFchInitEnvUsbEhci, - InstallFchInitEnvUsbOhci, - InstallFchInitEnvUsbXhci, - InstallFchInitEnvSata, - InstallFchInitEnvIde, - InstallFchInitEnvGec, - InstallFchInitEnvAzalia, - InstallFchInitEnvAb, - InstallFchInitEnvGpp, - InstallFchInitEnvAbS, - InstallFchInitEnvHwm, - NULL - }; - #endif - #endif - - - #ifdef AGESA_ENTRY_INIT_MID - #if AGESA_ENTRY_INIT_MID == TRUE - // - // Define task list for InitMid phase - // - FCH_TASK_ENTRY ROMDATA *FchInitMidTaskTable[] = { - InstallFchInitMidImc, - InstallFchInitMidUsb, - InstallFchInitMidUsbEhci, - InstallFchInitMidUsbOhci, - InstallFchInitMidUsbXhci, - InstallFchInitMidSata, - InstallFchInitMidIde, - InstallFchInitMidGec, - InstallFchInitMidAzalia, - InstallFchInitMidHwm, - NULL - }; - #endif - #endif - - #ifdef AGESA_ENTRY_INIT_LATE - #if AGESA_ENTRY_INIT_LATE == TRUE - // - // Define task list for InitLate phase - // - FCH_TASK_ENTRY ROMDATA *FchInitLateTaskTable[] = { - InstallFchInitLatePcie, - InstallFchInitLatePcib, - InstallFchInitLateSpi, - InstallFchInitLateUsb, - InstallFchInitLateUsbEhci, - InstallFchInitLateUsbOhci, - InstallFchInitLateUsbXhci, - InstallFchInitLateSata, - InstallFchInitLateIde, - InstallFchInitLateGec, - InstallFchInitLateAzalia, - InstallFchInitLateImc, - InstallFchInitLateHwm, - InstallFchInitLateGpp, - InstallFchInitLateHwAcpi, - NULL - }; - #endif - #endif - - - #ifdef AGESA_ENTRY_INIT_ENV - #if AGESA_ENTRY_INIT_ENV == TRUE - // - // Define task list for S3 resume before PCI phase - // - FCH_TASK_ENTRY ROMDATA *FchInitS3EarlyTaskTable[] = { - InstallFchInitEnvPcie, - InstallFchInitEnvPcib, - InstallFchInitEnvIr, - InstallFchInitEnvHwAcpi, - InstallFchInitEnvSpi, - InstallFchInitEnvSd, - InstallFchInitEnvUsb, - InstallFchInitEnvSata, - InstallFchInitEnvIde, - InstallFchInitEnvGec, - InstallFchInitEnvAzalia, - InstallFchInitEnvAb, - InstallFchInitEnvGpp, - InstallFchInitEnvAbS, - NULL - }; - #endif - #endif - - #ifdef AGESA_ENTRY_INIT_LATE - #if AGESA_ENTRY_INIT_LATE == TRUE - // - // Define task list for S3 resume after PCI phase - // - FCH_TASK_ENTRY ROMDATA *FchInitS3LateTaskTable[] = { - InstallFchInitLatePcie, - InstallFchInitLatePcib, - InstallFchInitLateSpi, - InstallFchInitLateUsb, - InstallFchInitLateUsbEhci, - InstallFchInitLateUsbOhci, - InstallFchInitLateUsbXhci, - InstallFchInitMidSata, - InstallFchInitMidIde, - InstallFchInitMidGec, - InstallFchInitMidAzalia, - InstallFchInitLateSata, - InstallFchInitLateIde, - InstallFchInitLateHwAcpi, - InstallFchInitEnvHwm, - InstallFchInitLateHwm, - NULL - }; - #endif - #endif - -#else // FCH_SUPPORT == FALSE - /* FCH Interface entries */ - extern FCH_INIT CommonFchInitStub; - - #define FP_FCH_INIT_RESET &CommonFchInitStub - #define FP_FCH_INIT_RESET_CONSTRUCT &CommonFchInitStub - #define FP_FCH_INIT_ENV &CommonFchInitStub - #define FP_FCH_INIT_ENV_CONSTRUCT &CommonFchInitStub - #define FP_FCH_INIT_MID &CommonFchInitStub - #define FP_FCH_INIT_MID_CONSTRUCT &CommonFchInitStub - #define FP_FCH_INIT_LATE &CommonFchInitStub - #define FP_FCH_INIT_LATE_CONSTRUCT &CommonFchInitStub - - #define CFG_SMBUS0_BASE_ADDRESS 0 - #define CFG_SMBUS1_BASE_ADDRESS 0 - #define CFG_SIO_PME_BASE_ADDRESS 0 - #define CFG_ACPI_PM1_EVT_BLOCK_ADDRESS 0 - #define CFG_ACPI_PM1_CNT_BLOCK_ADDRESS 0 - #define CFG_ACPI_PM_TMR_BLOCK_ADDRESS 0 - #define CFG_ACPI_CPU_CNT_BLOCK_ADDRESS 0 - #define CFG_ACPI_GPE0_BLOCK_ADDRESS 0 - #define CFG_SPI_ROM_BASE_ADDRESS 0 - #define CFG_WATCHDOG_TIMER_BASE 0 - #define CFG_HPET_BASE_ADDRESS 0 - #define CFG_SMI_CMD_PORT_ADDRESS 0 - #define CFG_ACPI_PMA_CNTBLK_ADDRESS 0 - #define CFG_GEC_SHADOW_ROM_BASE 0 - #define CFG_AZALIA_SSID 0 - #define CFG_SMBUS_SSID 0 - #define CFG_IDE_SSID 0 - #define CFG_SATA_AHCI_SSID 0 - #define CFG_SATA_IDE_SSID 0 - #define CFG_SATA_RAID5_SSID 0 - #define CFG_SATA_RAID_SSID 0 - #define CFG_EHCI_SSID 0 - #define CFG_OHCI_SSID 0 - #define CFG_LPC_SSID 0 - #define CFG_FCH_GPP_LINK_CONFIG 0 - #define CFG_FCH_GPP_PORT0_PRESENT 0 - #define CFG_FCH_GPP_PORT1_PRESENT 0 - #define CFG_FCH_GPP_PORT2_PRESENT 0 - #define CFG_FCH_GPP_PORT3_PRESENT 0 - #define CFG_FCH_GPP_PORT0_HOTPLUG 0 - #define CFG_FCH_GPP_PORT1_HOTPLUG 0 - #define CFG_FCH_GPP_PORT2_HOTPLUG 0 - #define CFG_FCH_GPP_PORT3_HOTPLUG 0 - -#endif - - -CONST BLDOPT_FCH_FUNCTION ROMDATA BldoptFchFunction = { - FP_FCH_INIT_RESET, - FP_FCH_INIT_RESET_CONSTRUCT, - FP_FCH_INIT_ENV, - FP_FCH_INIT_ENV_CONSTRUCT, - FP_FCH_INIT_MID, - FP_FCH_INIT_MID_CONSTRUCT, - FP_FCH_INIT_LATE, - FP_FCH_INIT_LATE_CONSTRUCT, -}; - -#endif // _OPTION_FCH_INSTALL_H_ diff --git a/src/vendorcode/amd/agesa/f12/Config/OptionGfxRecoveryInstall.h b/src/vendorcode/amd/agesa/f12/Config/OptionGfxRecoveryInstall.h deleted file mode 100644 index c031f326c1..0000000000 --- a/src/vendorcode/amd/agesa/f12/Config/OptionGfxRecoveryInstall.h +++ /dev/null @@ -1,53 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * Install of build option: GfxRecovery - * - * Contains AMD AGESA install macros and test conditions. Output is the - * defaults tables reflecting the User's build options selection. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: Options - * @e \$Revision: 63425 $ @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ - */ -/***************************************************************************** - * - * Copyright (c) 2008 - 2012, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ***************************************************************************/ - -#ifndef _OPTION_GFX_RECOVERY_INSTALL_H_ -#define _OPTION_GFX_RECOVERY_INSTALL_H_ - -/* This option is designed to be included into the platform solution install - * file. The platform solution install file will define the options status. - * Check to validate the definition - */ - - -#endif // _OPTION_GFX_RECOVERY_INSTALL_H_ diff --git a/src/vendorcode/amd/agesa/f12/Config/OptionGnbInstall.h b/src/vendorcode/amd/agesa/f12/Config/OptionGnbInstall.h deleted file mode 100644 index bcd9700293..0000000000 --- a/src/vendorcode/amd/agesa/f12/Config/OptionGnbInstall.h +++ /dev/null @@ -1,592 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * Install of build option: GNB - * - * Contains AMD AGESA install macros and test conditions. Output is the - * defaults tables reflecting the User's build options selection. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: Options - * @e \$Revision: 49877 $ @e \$Date: 2011-03-30 13:15:18 +0800 (Wed, 30 Mar 2011) $ - */ -/***************************************************************************** - * - * Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ***************************************************************************/ - -#ifndef _OPTION_GNB_INSTALL_H_ -#define _OPTION_GNB_INSTALL_H_ - -#include "S3SaveState.h" -/* This option is designed to be included into the platform solution install - * file. The platform solution install file will define the options status. - * Check to validate the definition - */ - -//--------------------------------------------------------------------------------------------------- -// Family installation -//--------------------------------------------------------------------------------------------------- - - -#define GNB_TYPE_KR FALSE -#define GNB_TYPE_TN FALSE -#define GNB_TYPE_LN FALSE -#define GNB_TYPE_ON FALSE - -#if (OPTION_FAMILY14H_ON == TRUE) - #undef GNB_TYPE_ON - #define GNB_TYPE_ON TRUE -#endif - -#if (OPTION_FAMILY12H_LN == TRUE) - #undef GNB_TYPE_LN - #define GNB_TYPE_LN TRUE -#endif - -#if (GNB_TYPE_LN == TRUE || GNB_TYPE_ON == TRUE) -//--------------------------------------------------------------------------------------------------- -// Service installation -//--------------------------------------------------------------------------------------------------- - - #include "Gnb.h" - #include "GnbPcie.h" - - #define SERVICES_POINTER NULL - GNB_SERVICE *ServiceTable = SERVICES_POINTER; - -//--------------------------------------------------------------------------------------------------- -// BUILD options -//--------------------------------------------------------------------------------------------------- - - #ifndef CFG_IGFX_AS_PCIE_EP - #define CFG_IGFX_AS_PCIE_EP TRUE - #endif - - #ifndef CFG_LCLK_DEEP_SLEEP_EN - #define CFG_LCLK_DEEP_SLEEP_EN TRUE - #endif - - #ifndef CFG_LCLK_DPM_EN - #define CFG_LCLK_DPM_EN TRUE - #endif - - #ifndef CFG_GMC_POWER_GATE_STUTTER_ONLY - #define CFG_GMC_POWER_GATE_STUTTER_ONLY FALSE - #endif - - #ifndef CFG_SMU_SCLK_CLOCK_GATING_ENABLE - #if (GNB_TYPE_ON == TRUE) - #define CFG_SMU_SCLK_CLOCK_GATING_ENABLE TRUE - #else - #define CFG_SMU_SCLK_CLOCK_GATING_ENABLE FALSE - #endif - #endif - - #ifndef CFG_PCIE_ASPM_BLACK_LIST_ENABLE - #define CFG_PCIE_ASPM_BLACK_LIST_ENABLE TRUE - #endif - - #ifndef CFG_GNB_IVRS_RELATIVE_ADDR_NAMES_SUPPORT - #define CFG_GNB_IVRS_RELATIVE_ADDR_NAMES_SUPPORT FALSE - #endif - - #ifndef CFG_GNB_LOAD_REAL_FUSE - #define CFG_GNB_LOAD_REAL_FUSE TRUE - #endif - - #ifndef CFG_GNB_PCIE_LINK_RECEIVER_DETECTION_POOLING - #define CFG_GNB_PCIE_LINK_RECEIVER_DETECTION_POOLING (60 * 1000) - #endif - - #ifndef CFG_GNB_PCIE_LINK_L0_POOLING - #define CFG_GNB_PCIE_LINK_L0_POOLING (60 * 1000) - #endif - - #ifndef CFG_GNB_PCIE_LINK_GPIO_RESET_ASSERT_TIME - #define CFG_GNB_PCIE_LINK_GPIO_RESET_ASSERT_TIME (2 * 1000) - #endif - - #ifndef CFG_GNB_PCIE_LINK_RESET_TO_TRAINING_TIME - #define CFG_GNB_PCIE_LINK_RESET_TO_TRAINING_TIME (2 * 1000) - #endif - - #ifdef BLDCFG_PCIE_TRAINING_ALGORITHM - #define CFG_GNB_PCIE_TRAINING_ALGORITHM BLDCFG_PCIE_TRAINING_ALGORITHM - #else - #define CFG_GNB_PCIE_TRAINING_ALGORITHM PcieTrainingStandard - #endif - - #ifndef CFG_GNB_FORCE_CABLESAFE_OFF - #define CFG_GNB_FORCE_CABLESAFE_OFF FALSE - #endif - - #ifndef CFG_ORB_CLOCK_GATING_ENABLE - #define CFG_ORB_CLOCK_GATING_ENABLE TRUE - #endif - - #ifndef CFG_GNB_PCIE_POWERGATING_FLAGS - #define CFG_GNB_PCIE_POWERGATING_FLAGS 0x0 - #endif - - #ifndef CFG_IOC_LCLK_CLOCK_GATING_ENABLE - #define CFG_IOC_LCLK_CLOCK_GATING_ENABLE FALSE - #endif - - #ifndef CFG_IOC_SCLK_CLOCK_GATING_ENABLE - #define CFG_IOC_SCLK_CLOCK_GATING_ENABLE FALSE - #endif - - #ifndef CFG_IOMMU_L1_CLOCK_GATING_ENABLE - #define CFG_IOMMU_L1_CLOCK_GATING_ENABLE FALSE - #endif - - #ifndef CFG_IOMMU_L2_CLOCK_GATING_ENABLE - #define CFG_IOMMU_L2_CLOCK_GATING_ENABLE FALSE - #endif - - #ifndef CFG_GNB_ALTVDDNB_SUPPORT - #define CFG_GNB_ALTVDDNB_SUPPORT TRUE - #endif - - GNB_BUILD_OPTIONS ROMDATA GnbBuildOptions = { - CFG_IGFX_AS_PCIE_EP, - CFG_LCLK_DEEP_SLEEP_EN, - CFG_LCLK_DPM_EN, - CFG_GMC_POWER_GATE_STUTTER_ONLY, - CFG_SMU_SCLK_CLOCK_GATING_ENABLE, - CFG_PCIE_ASPM_BLACK_LIST_ENABLE, - CFG_GNB_IVRS_RELATIVE_ADDR_NAMES_SUPPORT, - CFG_GNB_LOAD_REAL_FUSE, - CFG_GNB_PCIE_LINK_RECEIVER_DETECTION_POOLING, - CFG_GNB_PCIE_LINK_L0_POOLING, - CFG_GNB_PCIE_LINK_GPIO_RESET_ASSERT_TIME, - CFG_GNB_PCIE_LINK_RESET_TO_TRAINING_TIME, - CFG_GNB_PCIE_TRAINING_ALGORITHM, - CFG_GNB_FORCE_CABLESAFE_OFF, - CFG_ORB_CLOCK_GATING_ENABLE, - CFG_GNB_PCIE_POWERGATING_FLAGS, - CFG_IOC_LCLK_CLOCK_GATING_ENABLE, - CFG_IOC_SCLK_CLOCK_GATING_ENABLE, - CFG_IOMMU_L1_CLOCK_GATING_ENABLE, - CFG_IOMMU_L2_CLOCK_GATING_ENABLE, - CFG_GNB_ALTVDDNB_SUPPORT - }; - - //--------------------------------------------------------------------------------------------------- - // Module entries - //--------------------------------------------------------------------------------------------------- - - #if (AGESA_ENTRY_INIT_EARLY == TRUE) - //--------------------------------------------------------------------------------------------------- - #ifndef OPTION_NB_EARLY_INIT - #define OPTION_NB_EARLY_INIT TRUE - #endif - #if (OPTION_NB_EARLY_INIT == TRUE) && (GNB_TYPE_LN == TRUE || GNB_TYPE_ON == TRUE) - OPTION_GNB_FEATURE NbInitAtEarly; - #define OPTION_NBINITATEARLY_ENTRY {AMD_FAMILY_LN | AMD_FAMILY_ON, NbInitAtEarly}, - #else - #define OPTION_NBINITATEARLY_ENTRY - #endif - #define OPTION_GNBEARLYINTERFACETN_ENTRY - //--------------------------------------------------------------------------------------------------- - // SMU init - #ifndef OPTION_SMU - #define OPTION_SMU TRUE - #endif - #if (OPTION_SMU == TRUE) && (GNB_TYPE_LN == TRUE) - OPTION_GNB_FEATURE F12NbSmuInitFeature; - #define OPTION_F12NBSMUINITFEATURE_ENTRY {AMD_FAMILY_LN, F12NbSmuInitFeature}, - #else - #define OPTION_F12NBSMUINITFEATURE_ENTRY - #endif - #if (OPTION_SMU == TRUE) && (GNB_TYPE_ON == TRUE) - OPTION_GNB_FEATURE F14NbSmuInitFeature; - #define OPTION_F14NBSMUINITFEATURE_ENTRY {AMD_FAMILY_ON, F14NbSmuInitFeature}, - #else - #define OPTION_F14NBSMUINITFEATURE_ENTRY - #endif - #define OPTION_KRNBSMUINITFEATURE_ENTRY - //--------------------------------------------------------------------------------------------------- - #ifndef OPTION_PCIE_CONFIG_INIT - #define OPTION_PCIE_CONFIG_INIT TRUE - #endif - #if (OPTION_PCIE_CONFIG_INIT == TRUE) && (GNB_TYPE_LN == TRUE || GNB_TYPE_ON == TRUE) - OPTION_GNB_FEATURE PcieConfigurationInit; - #define OPTION_PCIECONFIGURATIONINIT_ENTRY {AMD_FAMILY_LN | AMD_FAMILY_ON, PcieConfigurationInit}, - #else - #define OPTION_PCIECONFIGURATIONINIT_ENTRY - #endif - //--------------------------------------------------------------------------------------------------- - #ifndef OPTION_PCIE_EARLY_INIT - #define OPTION_PCIE_EARLY_INIT TRUE - #endif - #if (OPTION_PCIE_EARLY_INIT == TRUE) && (GNB_TYPE_LN == TRUE || GNB_TYPE_ON == TRUE) - OPTION_GNB_FEATURE PcieInitAtEarly; - #define OPTION_PCIEINITATEARLY_ENTRY {AMD_FAMILY_LN | AMD_FAMILY_ON, PcieInitAtEarly}, - #else - #define OPTION_PCIEINITATEARLY_ENTRY - #endif - #define OPTION_PCIEEARLYINTERFACETN_ENTRY - //--------------------------------------------------------------------------------------------------- - OPTION_GNB_CONFIGURATION GnbEarlyFeatureTable[] = { - OPTION_NBINITATEARLY_ENTRY - OPTION_GNBEARLYINTERFACETN_ENTRY - OPTION_F12NBSMUINITFEATURE_ENTRY - OPTION_F14NBSMUINITFEATURE_ENTRY - OPTION_KRNBSMUINITFEATURE_ENTRY - OPTION_PCIECONFIGURATIONINIT_ENTRY - OPTION_PCIEINITATEARLY_ENTRY - OPTION_PCIEEARLYINTERFACETN_ENTRY - {0, NULL} - }; - - //--------------------------------------------------------------------------------------------------- - #ifndef OPTION_NB_EARLIER_INIT - #define OPTION_NB_EARLIER_INIT TRUE - #endif - #define OPTION_GNBEARLIERINTERFACETN_ENTRY - - OPTION_GNB_CONFIGURATION GnbEarlierFeatureTable[] = { - OPTION_GNBEARLIERINTERFACETN_ENTRY - {0, NULL} - }; - #endif - - #if (AGESA_ENTRY_INIT_POST == TRUE) - //--------------------------------------------------------------------------------------------------- - #ifndef OPTION_GFX_CONFIG_POST_INIT - #define OPTION_GFX_CONFIG_POST_INIT TRUE - #endif - #if (OPTION_GFX_CONFIG_POST_INIT == TRUE) && (GNB_TYPE_LN == TRUE || GNB_TYPE_ON == TRUE) - OPTION_GNB_FEATURE GfxConfigPostInterface; - #define OPTION_GFXCONFIGPOSTINTERFACE_ENTRY {AMD_FAMILY_LN | AMD_FAMILY_ON, GfxConfigPostInterface}, - #else - #define OPTION_GFXCONFIGPOSTINTERFACE_ENTRY - #endif - //--------------------------------------------------------------------------------------------------- - #ifndef OPTION_GFX_POST_INIT - #define OPTION_GFX_POST_INIT TRUE - #endif - #if (OPTION_GFX_POST_INIT == TRUE) && (GNB_TYPE_LN == TRUE || GNB_TYPE_ON == TRUE) - OPTION_GNB_FEATURE GfxInitAtPost; - #define OPTION_GFXINITATPOST_ENTRY {AMD_FAMILY_LN | AMD_FAMILY_ON, GfxInitAtPost}, - #else - #define OPTION_GFXINITATPOST_ENTRY - #endif - #define OPTION_GFXPOSTINTERFACETN_ENTRY - //--------------------------------------------------------------------------------------------------- - #ifndef OPTION_NB_POST_INIT - #define OPTION_NB_POST_INIT TRUE - #endif - #if (OPTION_NB_POST_INIT == TRUE) && (GNB_TYPE_LN == TRUE || GNB_TYPE_ON == TRUE) - OPTION_GNB_FEATURE NbInitAtPost; - #define OPTION_NBINITATPOST_ENTRY {AMD_FAMILY_LN | AMD_FAMILY_ON, NbInitAtPost}, - #else - #define OPTION_NBINITATPOST_ENTRY - #endif - #define OPTION_GNBPOSTINTERFACETN_ENTRY - //--------------------------------------------------------------------------------------------------- - #ifndef OPTION_PCIE_POST_EALRY_INIT - #define OPTION_PCIE_POST_EALRY_INIT TRUE - #endif - #if (OPTION_PCIE_POST_EALRY_INIT == TRUE) && (GNB_TYPE_LN == TRUE || GNB_TYPE_ON == TRUE) - OPTION_GNB_FEATURE PcieInitAtPostEarly; - #define OPTION_PCIEINITATPOSTEARLY_ENTRY {AMD_FAMILY_LN | AMD_FAMILY_ON, PcieInitAtPostEarly}, - #else - #define OPTION_PCIEINITATPOSTEARLY_ENTRY - #endif - #define OPTION_PCIEPOSTEARLYINTERFACETN_ENTRY - //--------------------------------------------------------------------------------------------------- - #ifndef OPTION_PCIE_POST_INIT - #define OPTION_PCIE_POST_INIT TRUE - #endif - #if (OPTION_PCIE_POST_INIT == TRUE) && (GNB_TYPE_LN == TRUE || GNB_TYPE_ON == TRUE) - OPTION_GNB_FEATURE PcieInitAtPost; - #define OPTION_PCIEINITATPOST_ENTRY {AMD_FAMILY_LN | AMD_FAMILY_ON, PcieInitAtPost}, - #else - #define OPTION_PCIEINITATPOST_ENTRY - #endif - #define OPTION_PCIEPOSTINTERFACETN_ENTRY - - //--------------------------------------------------------------------------------------------------- - OPTION_GNB_CONFIGURATION GnbPostFeatureTable[] = { - OPTION_PCIEINITATPOSTEARLY_ENTRY - OPTION_PCIEPOSTEARLYINTERFACETN_ENTRY - OPTION_GFXCONFIGPOSTINTERFACE_ENTRY - OPTION_GFXINITATPOST_ENTRY - OPTION_GFXPOSTINTERFACETN_ENTRY - {0, NULL} - }; - - OPTION_GNB_CONFIGURATION GnbPostAfterDramFeatureTable[] = { - OPTION_NBINITATPOST_ENTRY - OPTION_GNBPOSTINTERFACETN_ENTRY - OPTION_PCIEINITATPOST_ENTRY - OPTION_PCIEPOSTINTERFACETN_ENTRY - {0, NULL} - }; - #endif - - #if (AGESA_ENTRY_INIT_ENV == TRUE) - //--------------------------------------------------------------------------------------------------- - #ifndef OPTION_FUSE_TABLE_INIT - #define OPTION_FUSE_TABLE_INIT TRUE - #endif - #if (OPTION_FUSE_TABLE_INIT == TRUE) && (GNB_TYPE_LN == TRUE || GNB_TYPE_ON == TRUE) - OPTION_GNB_FEATURE NbFuseTableFeature; - #define OPTION_NBFUSETABLEFEATURE_ENTRY {AMD_FAMILY_LN | AMD_FAMILY_ON, NbFuseTableFeature}, - #else - #define OPTION_NBFUSETABLEFEATURE_ENTRY - #endif - //--------------------------------------------------------------------------------------------------- - #ifndef OPTION_NB_ENV_INIT - #define OPTION_NB_ENV_INIT TRUE - #endif - #if (OPTION_NB_ENV_INIT == TRUE) && (GNB_TYPE_LN == TRUE || GNB_TYPE_ON == TRUE) - OPTION_GNB_FEATURE NbInitAtEnv; - #define OPTION_NBINITATENVT_ENTRY {AMD_FAMILY_LN | AMD_FAMILY_ON, NbInitAtEnv}, - #else - #define OPTION_NBINITATENVT_ENTRY - #endif - #define OPTION_GNBENVINTERFACETN_ENTRY - //--------------------------------------------------------------------------------------------------- - #ifndef OPTION_GFX_CONFIG_ENV_INIT - #define OPTION_GFX_CONFIG_ENV_INIT TRUE - #endif - #if (OPTION_GFX_CONFIG_ENV_INIT == TRUE) && (GNB_TYPE_LN == TRUE || GNB_TYPE_ON == TRUE) - OPTION_GNB_FEATURE GfxConfigEnvInterface; - #define OPTION_GFXCONFIGENVINTERFACE_ENTRY {AMD_FAMILY_LN | AMD_FAMILY_ON, GfxConfigEnvInterface}, - #else - #define OPTION_GFXCONFIGENVINTERFACE_ENTRY - #endif - - //--------------------------------------------------------------------------------------------------- - #ifndef OPTION_GFX_ENV_INIT - #define OPTION_GFX_ENV_INIT TRUE - #endif - #if (OPTION_GFX_ENV_INIT == TRUE) && (GNB_TYPE_LN == TRUE || GNB_TYPE_ON == TRUE) - OPTION_GNB_FEATURE GfxInitAtEnvPost; - #define OPTION_GFXINITATENVPOST_ENTRY {AMD_FAMILY_LN | AMD_FAMILY_ON, GfxInitAtEnvPost}, - #else - #define OPTION_GFXINITATENVPOST_ENTRY - #endif - #define OPTION_GFXENVINTERFACETN_ENTRY - - //--------------------------------------------------------------------------------------------------- - #ifndef OPTION_POWER_GATE - #define OPTION_POWER_GATE TRUE - #endif - #if (OPTION_POWER_GATE == TRUE) && (GNB_TYPE_LN == TRUE) - OPTION_GNB_FEATURE F12NbPowerGateFeature; - #define OPTION_F12NBPOWERGATEFEATURE_ENTRY {AMD_FAMILY_LN, F12NbPowerGateFeature}, - #else - #define OPTION_F12NBPOWERGATEFEATURE_ENTRY - #endif - #if (OPTION_POWER_GATE == TRUE) && (GNB_TYPE_ON == TRUE) - OPTION_GNB_FEATURE F14NbPowerGateFeature; - #define OPTION_F14NBPOWERGATEFEATURE_ENTRY {AMD_FAMILY_ON, F14NbPowerGateFeature}, - #else - #define OPTION_F14NBPOWERGATEFEATURE_ENTRY - #endif - #define OPTION_KRNBPOWERGATEFEATURE_ENTRY - //--------------------------------------------------------------------------------------------------- - #ifndef OPTION_PCIE_ENV_INIT - #define OPTION_PCIE_ENV_INIT TRUE - #endif - #if (OPTION_PCIE_ENV_INIT == TRUE) && (GNB_TYPE_LN == TRUE || GNB_TYPE_ON == TRUE) - OPTION_GNB_FEATURE PcieInitAtEnv; - #define OPTION_PCIEINITATENV_ENTRY {AMD_FAMILY_LN | AMD_FAMILY_ON, PcieInitAtEnv}, - #else - #define OPTION_PCIEINITATENV_ENTRY - #endif - #define OPTION_PCIEENVINTERFACETN_ENTRY - - //--------------------------------------------------------------------------------------------------- - - OPTION_GNB_CONFIGURATION GnbEnvFeatureTable[] = { - OPTION_NBFUSETABLEFEATURE_ENTRY - OPTION_NBINITATENVT_ENTRY - OPTION_GNBENVINTERFACETN_ENTRY - OPTION_PCIEINITATENV_ENTRY - OPTION_PCIEENVINTERFACETN_ENTRY - OPTION_GFXCONFIGENVINTERFACE_ENTRY - OPTION_GFXINITATENVPOST_ENTRY - OPTION_GFXENVINTERFACETN_ENTRY - OPTION_F12NBPOWERGATEFEATURE_ENTRY - OPTION_F14NBPOWERGATEFEATURE_ENTRY - OPTION_KRNBPOWERGATEFEATURE_ENTRY - {0, NULL} - }; - #endif - - #if (AGESA_ENTRY_INIT_MID == TRUE) - //--------------------------------------------------------------------------------------------------- - #ifndef OPTOIN_GNB_CABLESAFE - #define OPTOIN_GNB_CABLESAFE TRUE - #endif - #if (OPTOIN_GNB_CABLESAFE == TRUE) && (GNB_TYPE_LN == TRUE) - OPTION_GNB_FEATURE GnbCableSafeEntry; - #define OPTION_GNBCABLESAFEENTRY_ENTRY {AMD_FAMILY_LN, GnbCableSafeEntry}, - #else - #define OPTION_GNBCABLESAFEENTRY_ENTRY - #endif - //--------------------------------------------------------------------------------------------------- - #ifndef OPTOIN_NB_LCLK_NCLK_RATIO - #define OPTOIN_NB_LCLK_NCLK_RATIO TRUE - #endif - #if (OPTOIN_NB_LCLK_NCLK_RATIO == TRUE) && (GNB_TYPE_ON == TRUE) - OPTION_GNB_FEATURE F14NbLclkNclkRatioFeature; - #define OPTION_F14NBLCLKNCLKRATIOFEATURE_ENTRY {AMD_FAMILY_ON, F14NbLclkNclkRatioFeature}, - #else - #define OPTION_F14NBLCLKNCLKRATIOFEATURE_ENTRY - #endif - #define OPTION_KRNBLCLKNCLKRATIOFEATURE_ENTRY - //--------------------------------------------------------------------------------------------------- - #ifndef OPTION_NB_LCLK_DPM_INIT - #define OPTION_NB_LCLK_DPM_INIT TRUE - #endif - #if (OPTION_NB_LCLK_DPM_INIT == TRUE) && (GNB_TYPE_LN == TRUE || GNB_TYPE_ON == TRUE) - OPTION_GNB_FEATURE NbLclkDpmFeature; - #define OPTION_NBLCLKDPMFEATURE_ENTRY {AMD_FAMILY_LN | AMD_FAMILY_ON, NbLclkDpmFeature}, - #else - #define OPTION_NBLCLKDPMFEATURE_ENTRY - #endif - //--------------------------------------------------------------------------------------------------- - #ifndef OPTION_PCIE_POWER_GATE - #define OPTION_PCIE_POWER_GATE TRUE - #endif - #if (OPTION_PCIE_POWER_GATE == TRUE) && (GNB_TYPE_LN == TRUE) - OPTION_GNB_FEATURE PciePowerGateFeature; - #define OPTION_PCIEPOWERGATEFEATURE_ENTRY {AMD_FAMILY_LN, PciePowerGateFeature}, - #else - #define OPTION_PCIEPOWERGATEFEATURE_ENTRY - #endif - //--------------------------------------------------------------------------------------------------- - #ifndef OPTION_GFX_MID_INIT - #define OPTION_GFX_MID_INIT TRUE - #endif - #if (OPTION_GFX_MID_INIT == TRUE) && (GNB_TYPE_LN == TRUE || GNB_TYPE_ON == TRUE) - OPTION_GNB_FEATURE GfxInitAtMidPost; - #define OPTION_GFXINITATMIDPOST_ENTRY {AMD_FAMILY_LN | AMD_FAMILY_ON, GfxInitAtMidPost}, - #else - #define OPTION_GFXINITATMIDPOST_ENTRY - #endif - #define OPTION_GFXMIDINTERFACETN_ENTRY - //--------------------------------------------------------------------------------------------------- - #ifndef OPTION_GFX_INTEGRATED_TABLE_INIT - #define OPTION_GFX_INTEGRATED_TABLE_INIT TRUE - #endif - #if (OPTION_GFX_INTEGRATED_TABLE_INIT == TRUE) && (GNB_TYPE_LN == TRUE || GNB_TYPE_ON == TRUE) - OPTION_GNB_FEATURE GfxIntegratedInfoTableEntry; - #define OPTION_GFXINTEGRATEDINFOTABLE_ENTRY {AMD_FAMILY_LN | AMD_FAMILY_ON, GfxIntegratedInfoTableEntry}, - #else - #define OPTION_GFXINTEGRATEDINFOTABLE_ENTRY - #endif - #define OPTION_GFXINTINFOTABLEINTERFACETN_ENTRY - //--------------------------------------------------------------------------------------------------- - #ifndef OPTION_PCIe_MID_INIT - #define OPTION_PCIe_MID_INIT TRUE - #endif - #if (OPTION_PCIe_MID_INIT == TRUE) && (GNB_TYPE_LN == TRUE || GNB_TYPE_ON == TRUE) - OPTION_GNB_FEATURE PcieInitAtMid; - #define OPTION_PCIEINITATMID_ENTRY {AMD_FAMILY_LN | AMD_FAMILY_ON, PcieInitAtMid}, - #else - #define OPTION_PCIEINITATMID_ENTRY - #endif - #define OPTION_PCIEMIDINTERFACETN_ENTRY - - //--------------------------------------------------------------------------------------------------- - #ifndef OPTION_NB_MID_INIT - #define OPTION_NB_MID_INIT TRUE - #endif - #if (OPTION_NB_MID_INIT == TRUE) && (GNB_TYPE_LN == TRUE || GNB_TYPE_ON == TRUE) - OPTION_GNB_FEATURE NbInitAtLatePost; - #define OPTION_NBINITATLATEPOST_ENTRY {AMD_FAMILY_LN | AMD_FAMILY_ON, NbInitAtLatePost}, - #else - #define OPTION_NBINITATLATEPOST_ENTRY - #endif - #define OPTION_GNBMIDINTERFACETN_ENTRY - - //--------------------------------------------------------------------------------------------------- - OPTION_GNB_CONFIGURATION GnbMidFeatureTable[] = { - OPTION_GFXINITATMIDPOST_ENTRY - OPTION_GFXMIDINTERFACETN_ENTRY - OPTION_GFXINTEGRATEDINFOTABLE_ENTRY - OPTION_GFXINTINFOTABLEINTERFACETN_ENTRY - OPTION_GNBCABLESAFEENTRY_ENTRY - OPTION_PCIEINITATMID_ENTRY - OPTION_PCIEMIDINTERFACETN_ENTRY - OPTION_NBINITATLATEPOST_ENTRY - OPTION_GNBMIDINTERFACETN_ENTRY - OPTION_F14NBLCLKNCLKRATIOFEATURE_ENTRY - OPTION_KRNBLCLKNCLKRATIOFEATURE_ENTRY - OPTION_NBLCLKDPMFEATURE_ENTRY - OPTION_PCIEPOWERGATEFEATURE_ENTRY - {0, NULL} - }; - #endif - - #if (AGESA_ENTRY_INIT_LATE == TRUE) - //--------------------------------------------------------------------------------------------------- - #ifndef OPTION_ALIB - #define OPTION_ALIB FALSE - #endif - #if (OPTION_ALIB == TRUE) && (GNB_TYPE_LN == TRUE || GNB_TYPE_ON == TRUE) - OPTION_GNB_FEATURE PcieAlibFeature; - #define OPTION_PCIEALIBFEATURE_ENTRY {AMD_FAMILY_LN | AMD_FAMILY_ON, PcieAlibFeature}, - #else - #define OPTION_PCIEALIBFEATURE_ENTRY - #endif - //--------------------------------------------------------------------------------------------------- - #ifndef OPTION_IOMMU_ACPI_IVRS - #define OPTION_IOMMU_ACPI_IVRS TRUE - #endif - #define OPTIONIOMMUACPIIVRSLATE_ENTRY - //--------------------------------------------------------------------------------------------------- - OPTION_GNB_CONFIGURATION GnbLateFeatureTable[] = { - OPTION_PCIEALIBFEATURE_ENTRY - OPTIONIOMMUACPIIVRSLATE_ENTRY - {0, NULL} - }; - #endif - - #if (GNB_TYPE_LN == TRUE || GNB_TYPE_ON == TRUE) - S3_DISPATCH_FUNCTION NbSmuServiceRequestS3Script; - S3_DISPATCH_FUNCTION PcieLateRestoreS3Script; - S3_DISPATCH_FUNCTION NbSmuIndirectWriteS3Script; - #define GNB_S3_DISPATCH_FUNCTION_TABLE \ - {NbSmuIndirectWriteS3Script_ID, NbSmuIndirectWriteS3Script}, \ - {NbSmuServiceRequestS3Script_ID, NbSmuServiceRequestS3Script}, \ - {PcieLateRestoreS3Script_ID, PcieLateRestoreS3Script}, - #endif - - -#endif -#endif // _OPTION_GNB_INSTALL_H_ diff --git a/src/vendorcode/amd/agesa/f12/Config/OptionHtInstall.h b/src/vendorcode/amd/agesa/f12/Config/OptionHtInstall.h deleted file mode 100644 index eb4e44b5af..0000000000 --- a/src/vendorcode/amd/agesa/f12/Config/OptionHtInstall.h +++ /dev/null @@ -1,304 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * Install of build option: Ht - * - * Contains AMD AGESA install macros and test conditions. Output is the - * defaults tables reflecting the User's build options selection. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: Options - * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $ - */ -/***************************************************************************** - * - * Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ***************************************************************************/ - -#ifndef _OPTION_HT_INSTALL_H_ -#define _OPTION_HT_INSTALL_H_ - -#include "Topology.h" -#include "htFeat.h" -#include "htInterface.h" -#include "htNb.h" -#include "htTopologies.h" -/* - * Advanced Option only, hardware socket naming is the preferred method. - */ -#ifdef BLDCFG_SYSTEM_PHYSICAL_SOCKET_MAP - #define CFG_SYSTEM_PHYSICAL_SOCKET_MAP (BLDCFG_SYSTEM_PHYSICAL_SOCKET_MAP) -#else - #define CFG_SYSTEM_PHYSICAL_SOCKET_MAP (NULL) -#endif - -/* - * OPTION_IS_RECOVERY_HT is true if Basic API is being used. - */ -#ifndef OPTION_IS_RECOVERY_HT - #define OPTION_IS_RECOVERY_HT TRUE -#endif - -/* This option is designed to be included into the platform solution install - * file. The platform solution install file will define the options status. - * Check to validate the definition. - */ - -#ifndef OPTION_MULTISOCKET - #error BLDOPT: Option not defined: "OPTION_MULTISOCKET" -#endif - -/* - * Based on user level options, set Ht internal options. - * For now, Family 10h support will assume single module. For multi module, - * this will have to be changed to not set non-coherent only. - */ -#define OPTION_HT_NON_COHERENT_ONLY FALSE - -#if ((OPTION_FAMILY12H == TRUE) || (OPTION_FAMILY14H == TRUE) || (OPTION_FAMILY16H == TRUE)) -/* Fusion Families do not need a non-coherent only option. */ -#else - // Process Family 10h and 15h by socket, applying the MultiSocket option where it is allowable. - #if OPTION_G34_SOCKET_SUPPORT == FALSE - // Hydra has coherent support, other Family 10h should follow MultiSocket support. - #if OPTION_MULTISOCKET == FALSE - #undef OPTION_HT_NON_COHERENT_ONLY - #define OPTION_HT_NON_COHERENT_ONLY TRUE - #endif - #endif -#endif - -/* - * Macros will generate the correct item reference based on options - */ -#if AGESA_ENTRY_INIT_EARLY == TRUE - // Select the interface and features - #if ((OPTION_FAMILY12H == TRUE) || (OPTION_FAMILY14H == TRUE) || (OPTION_FAMILY16H == TRUE)) - #define INTERNAL_HT_OPTION_BUILTIN_TOPOLOGIES NULL - #define INTERNAL_HT_OPTION_FEATURES &HtFeaturesNone - #define INTERNAL_HT_OPTION_INTERFACE &HtInterfaceMapsOnly - #else - // Family 10h and 15h Models 00h-0Fh - #if OPTION_HT_NON_COHERENT_ONLY == FALSE - #define INTERNAL_HT_OPTION_FEATURES &HtFeaturesDefault - #define INTERNAL_HT_OPTION_INTERFACE &HtInterfaceDefault - #else - #define INTERNAL_HT_OPTION_BUILTIN_TOPOLOGIES NULL - #define INTERNAL_HT_OPTION_FEATURES &HtFeaturesNonCoherentOnly - #define INTERNAL_HT_OPTION_INTERFACE &HtInterfaceNonCoherentOnly - #endif - #endif - // Select Northbridge components - #if OPTION_FAMILY10H == TRUE - #if OPTION_HT_NON_COHERENT_ONLY == TRUE - #define INTERNAL_HT_OPTION_FAM10_NB &HtFam10NbNonCoherentOnly, &HtFam10RevDNbNonCoherentOnly, - #else - #define INTERNAL_HT_OPTION_FAM10_NB &HtFam10NbDefault, &HtFam10RevDNbDefault, - #endif - #else - #define INTERNAL_HT_OPTION_FAM10_NB - #endif - #if OPTION_FAMILY12H == TRUE - #define INTERNAL_HT_OPTION_FAM12_NB &HtFam12Nb, - #else - #define INTERNAL_HT_OPTION_FAM12_NB - #endif - #if OPTION_FAMILY14H == TRUE - #define INTERNAL_HT_OPTION_FAM14_NB &HtFam14Nb, - #else - #define INTERNAL_HT_OPTION_FAM14_NB - #endif - #if OPTION_FAMILY15H == TRUE - #if OPTION_HT_NON_COHERENT_ONLY == TRUE - #define INTERNAL_HT_OPTION_FAM15_NB &HtFam15NbNonCoherentOnly, - #else - #define INTERNAL_HT_OPTION_FAM15_NB &HtFam15NbDefault, - #endif - #else - #define INTERNAL_HT_OPTION_FAM15_NB - #endif - - #define INTERNAL_ONLY_NB_LIST_ITEM INTERNAL_ONLY_HT_OPTION_SUPPORTED_NBS, - #ifndef INTERNAL_ONLY_HT_OPTION_SUPPORTED_NBS - #undef INTERNAL_ONLY_NB_LIST_ITEM - #define INTERNAL_ONLY_NB_LIST_ITEM - #endif - - /* Install the correct set of northbridge implementations. Each item provides its own comma, the last item - * is ok to have a comma because the final item (NULL) is added below. - */ - #define INTERNAL_HT_OPTION_SUPPORTED_NBS \ - INTERNAL_ONLY_NB_LIST_ITEM \ - INTERNAL_HT_OPTION_FAM10_NB \ - INTERNAL_HT_OPTION_FAM15_NB \ - INTERNAL_HT_OPTION_FAM12_NB \ - INTERNAL_HT_OPTION_FAM14_NB - -#else - // Not Init Early - #define INTERNAL_HT_OPTION_FEATURES NULL - #define INTERNAL_HT_OPTION_INTERFACE NULL - #define INTERNAL_HT_OPTION_SUPPORTED_NBS NULL - #define HT_OPTIONS_PLATFORM NULL - #define INTERNAL_HT_OPTION_BUILTIN_TOPOLOGIES NULL -#endif - -#ifdef AGESA_ENTRY_INIT_EARLY - #if AGESA_ENTRY_INIT_EARLY == TRUE - - extern HT_FEATURES HtFeaturesDefault; - extern HT_FEATURES HtFeaturesNonCoherentOnly; - extern HT_FEATURES HtFeaturesNone; - extern HT_INTERFACE HtInterfaceDefault; - extern HT_INTERFACE HtInterfaceNonCoherentOnly; - extern HT_INTERFACE HtInterfaceMapsOnly; - extern HT_INTERFACE HtInterfaceNone; - extern NORTHBRIDGE HtFam10NbDefault; - extern NORTHBRIDGE HtFam10RevDNbDefault; - extern NORTHBRIDGE HtFam10NbNonCoherentOnly; - extern NORTHBRIDGE HtFam10RevDNbNonCoherentOnly; - extern NORTHBRIDGE HtFam12Nb; - extern NORTHBRIDGE HtFam14Nb; - extern NORTHBRIDGE HtFam10NbNone; - extern NORTHBRIDGE HtFam15NbDefault; - extern NORTHBRIDGE HtFam15NbNonCoherentOnly; - - CONST VOID * CONST ROMDATA HtInstalledFamilyNorthbridgeList[] = { - INTERNAL_HT_OPTION_SUPPORTED_NBS - NULL - }; - - STATIC CONST AMD_HT_INTERFACE ROMDATA HtOptionsPlatform = - { - CFG_STARTING_BUSNUM, CFG_MAXIMUM_BUSNUM, CFG_ALLOCATED_BUSNUM, - (MANUAL_BUID_SWAP_LIST *)CFG_BUID_SWAP_LIST, - (DEVICE_CAP_OVERRIDE *)CFG_HTDEVICE_CAPABILITIES_OVERRIDE_LIST, - (CPU_TO_CPU_PCB_LIMITS *)CFG_HTFABRIC_LIMITS_LIST, - (IO_PCB_LIMITS *)CFG_HTCHAIN_LIMITS_LIST, - (OVERRIDE_BUS_NUMBERS *)CFG_BUS_NUMBERS_LIST, - (IGNORE_LINK *)CFG_IGNORE_LINK_LIST, - (SKIP_REGANG *)CFG_LINK_SKIP_REGANG_LIST, - (UINT8 **)CFG_ADDITIONAL_TOPOLOGIES_LIST, - (SYSTEM_PHYSICAL_SOCKET_MAP *)CFG_SYSTEM_PHYSICAL_SOCKET_MAP - }; - #ifndef HT_OPTIONS_PLATFORM - #define HT_OPTIONS_PLATFORM &HtOptionsPlatform - #endif - - /** - * A list of all the supported topologies. - * - */ - #ifndef INTERNAL_HT_OPTION_BUILTIN_TOPOLOGIES - CONST UINT8 *CONST ROMDATA AmdTopolist[] = - { - amdHtTopologySingleNode, - amdHtTopologyDualNode, - amdHtTopologyThreeLine, - amdHtTopologyTriangle, - amdHtTopologyFourLine, - amdHtTopologyFourStar, - amdHtTopologyFourDegenerate, - amdHtTopologyFourSquare, - amdHtTopologyFourKite, - amdHtTopologyFourFully, - amdHtTopologyFiveFully, - amdHtTopologyFiveTwistedLadder, - amdHtTopologySixFully, - amdHtTopologySixDoubloonLower, - amdHtTopologySixDoubloonUpper, - amdHtTopologySixTwistedLadder, - amdHtTopologySevenFully, - amdHtTopologySevenTwistedLadder, - amdHtTopologyEightFully, - amdHtTopologyEightDoubloon, - amdHtTopologyEightTwistedLadder, - amdHtTopologyEightStraightLadder, - amdHtTopologySixTwinTriangles, - amdHtTopologyEightTwinFullyFourWays, - NULL - }; - #define INTERNAL_HT_OPTION_BUILTIN_TOPOLOGIES AmdTopolist - #endif - - /** - * Declare the instance of the Ht option configuration structure - */ - CONST OPTION_HT_CONFIGURATION ROMDATA OptionHtConfiguration = { - OPTION_IS_RECOVERY_HT, - CFG_SET_HTCRC_SYNC_FLOOD, - CFG_USE_UNIT_ID_CLUMPING, - HT_OPTIONS_PLATFORM, - INTERNAL_HT_OPTION_INTERFACE, - INTERNAL_HT_OPTION_FEATURES, - &HtInstalledFamilyNorthbridgeList, - INTERNAL_HT_OPTION_BUILTIN_TOPOLOGIES - }; - - #endif -#endif - -#ifndef OPTION_HT_INIIT_RESET_ENTRY - - #define OPTION_HT_INIIT_RESET_ENTRY AmdHtInitReset - #define OPTION_HT_INIIT_RESET_CONSTRUCTOR_ENTRY AmdHtResetConstructor - - #if (OPTION_FAMILY12H == TRUE) || (OPTION_FAMILY14H == TRUE) - #undef OPTION_HT_INIIT_RESET_ENTRY - #undef OPTION_HT_INIIT_RESET_CONSTRUCTOR_ENTRY - #define OPTION_HT_INIIT_RESET_ENTRY NULL - #define OPTION_HT_INIIT_RESET_CONSTRUCTOR_ENTRY NULL - #endif - - #if ((OPTION_FAMILY10H == TRUE) || (OPTION_FAMILY15H_OR == TRUE)) - #undef OPTION_HT_INIIT_RESET_ENTRY - #undef OPTION_HT_INIIT_RESET_CONSTRUCTOR_ENTRY - #define OPTION_HT_INIIT_RESET_ENTRY AmdHtInitReset - #define OPTION_HT_INIIT_RESET_CONSTRUCTOR_ENTRY AmdHtResetConstructor - #endif - -#endif - -#ifdef AGESA_ENTRY_INIT_RESET - #if AGESA_ENTRY_INIT_RESET == TRUE - - CONST AMD_HT_RESET_INTERFACE ROMDATA HtOptionResetDefaults = { - (MANUAL_BUID_SWAP_LIST *)CFG_BUID_SWAP_LIST, - 0 // Unused by options - }; - - CONST OPTION_HT_INIT_RESET ROMDATA HtOptionInitReset = { - OPTION_HT_INIIT_RESET_ENTRY, - OPTION_HT_INIIT_RESET_CONSTRUCTOR_ENTRY - }; - #endif - -#endif - -#endif // _OPTION_HT_INSTALL_H_ diff --git a/src/vendorcode/amd/agesa/f12/Config/OptionHwC1eInstall.h b/src/vendorcode/amd/agesa/f12/Config/OptionHwC1eInstall.h deleted file mode 100644 index e30f0488ff..0000000000 --- a/src/vendorcode/amd/agesa/f12/Config/OptionHwC1eInstall.h +++ /dev/null @@ -1,80 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * Install of build option: HW C1e - * - * Contains AMD AGESA install macros and test conditions. Output is the - * defaults tables reflecting the User's build options selection. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: Options - * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $ - */ -/***************************************************************************** - * - * Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ***************************************************************************/ - -#ifndef _OPTION_HW_C1E_INSTALL_H_ -#define _OPTION_HW_C1E_INSTALL_H_ - -#include "cpuHwC1e.h" - -/* This option is designed to be included into the platform solution install - * file. The platform solution install file will define the options status. - * Check to validate the definition - */ -#define OPTION_HW_C1E_FEAT -#define F10_HW_C1E_SUPPORT -#if AGESA_ENTRY_INIT_EARLY == TRUE - #ifdef OPTION_FAMILY10H - #if OPTION_FAMILY10H == TRUE - #if (OPTION_FAMILY10H_BL == TRUE) || (OPTION_FAMILY10H_DA == TRUE) || (OPTION_FAMILY10H_RB == TRUE) || (OPTION_FAMILY10H_PH == TRUE) - extern CONST CPU_FEATURE_DESCRIPTOR ROMDATA CpuFeatureHwC1e; - #undef OPTION_HW_C1E_FEAT - #define OPTION_HW_C1E_FEAT &CpuFeatureHwC1e, - extern CONST HW_C1E_FAMILY_SERVICES ROMDATA F10HwC1e; - #undef F10_HW_C1E_SUPPORT - #define F10_HW_C1E_SUPPORT {(AMD_FAMILY_10_BL | AMD_FAMILY_10_DA | AMD_FAMILY_10_RB | AMD_FAMILY_10_PH), &F10HwC1e}, - #endif - #endif - #endif - CONST CPU_SPECIFIC_SERVICES_XLAT ROMDATA HwC1eFamilyServiceArray[] = - { - F10_HW_C1E_SUPPORT - {0, NULL} - }; - CONST CPU_FAMILY_SUPPORT_TABLE ROMDATA HwC1eFamilyServiceTable = - { - (sizeof (HwC1eFamilyServiceArray) / sizeof (CPU_SPECIFIC_SERVICES_XLAT)), - &HwC1eFamilyServiceArray[0] - }; -#endif - -#endif // _OPTION_HW_C1E_INSTALL_H_ diff --git a/src/vendorcode/amd/agesa/f12/Config/OptionIdsInstall.h b/src/vendorcode/amd/agesa/f12/Config/OptionIdsInstall.h deleted file mode 100644 index d1c6c740f2..0000000000 --- a/src/vendorcode/amd/agesa/f12/Config/OptionIdsInstall.h +++ /dev/null @@ -1,407 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * IDS Option Install File - * - * This file generates the defaults tables for family 10h model 5 processors. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: Core - * @e \$Revision: 47940 $ @e \$Date: 2011-03-02 14:25:35 +0800 (Wed, 02 Mar 2011) $ - */ -/***************************************************************************** - * - * Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ***************************************************************************/ -#ifndef _OPTION_IDS_INSTALL_H_ -#define _OPTION_IDS_INSTALL_H_ -#include "Ids.h" -#include "IdsHt.h" -#include "IdsLib.h" -#ifdef __IDS_EXTENDED__ - #include OPTION_IDS_EXT_INSTALL_FILE -#endif - -#define IDS_LATE_RUN_AP_TASK - -#define M_HTIDS_PORT_OVERRIDE_HOOK (PF_HtIdsGetPortOverride)CommonVoid -#if (IDSOPT_IDS_ENABLED == TRUE) - #if (IDSOPT_CONTROL_ENABLED == TRUE) - // Check for all families which include HT Features. - #if (OPTION_FAMILY10H == TRUE) && (AGESA_ENTRY_INIT_POST == TRUE) - #undef M_HTIDS_PORT_OVERRIDE_HOOK - #define M_HTIDS_PORT_OVERRIDE_HOOK HtIdsGetPortOverride - #endif - #endif -#endif // OPTION_IDS_LEVEL -CONST PF_HtIdsGetPortOverride ROMDATA pf_HtIdsGetPortOverride = M_HTIDS_PORT_OVERRIDE_HOOK; - -#if (IDSOPT_IDS_ENABLED == TRUE) - #if (AGESA_ENTRY_INIT_LATE == TRUE) - #undef IDS_LATE_RUN_AP_TASK - #define IDS_LATE_RUN_AP_TASK - #endif -#endif // OPTION_IDS_LEVEL - -#if (IDSOPT_TRACING_ENABLED == TRUE) - #if (AGESA_ENTRY_INIT_POST == TRUE) - #include - CONST SCRIPT_FUNCTION ROMDATA ScriptFuncList[] = { - { (UINTN) MemUWriteCachelines, "WriteCl(PhyAddrLo,BufferAddr,ClCnt)"}, - { (UINTN) MemUReadCachelines, "ReadCl(BufferAddr,PhyAddrLo,ClCnt)"}, - { (UINTN) MemUFlushPattern, "FlushCl(PhyAddrLo,ClCnt)"} - }; - #else - CONST SCRIPT_FUNCTION ROMDATA ScriptFuncList[] = { - { (UINTN) CommonReturnFalse, "DefRet()"}, - { (UINTN) CommonReturnFalse, "DefRet()"}, - { (UINTN) CommonReturnFalse, "DefRet()"} - }; - #endif -#endif - - -///Ids Feat Options -#if (IDSOPT_IDS_ENABLED == TRUE) - #if (IDSOPT_CONTROL_ENABLED == TRUE) - - #ifndef OPTION_IDS_EXTEND_FEATS - #define OPTION_IDS_EXTEND_FEATS - #endif - - #define OPTION_IDS_FEAT_ECCCTRL\ - OPTION_IDS_FEAT_ECCCTRL_F10 \ - OPTION_IDS_FEAT_ECCCTRL_F12 \ - OPTION_IDS_FEAT_ECCCTRL_F15_OR - - #define OPTION_IDS_FEAT_GNB_PLATFORMCFG\ - OPTION_IDS_FEAT_GNB_PLATFORMCFGF12 \ - OPTION_IDS_FEAT_GNB_PLATFORMCFGF14 - - #define OPTION_IDS_FEAT_CPB_CTRL\ - OPTION_IDS_FEAT_CPB_CTRL_F12 - - #define OPTION_IDS_FEAT_HTC_CTRL\ - OPTION_IDS_FEAT_HTC_CTRL_F15 - - #define OPTION_IDS_FEAT_MEMORY_MAPPING\ - OPTION_IDS_FEAT_MEMORY_MAPPING_F12 \ - OPTION_IDS_FEAT_MEMORY_MAPPING_F15_OR - #define OPTION_IDS_FEAT_HT_ASSIST\ - OPTION_IDS_FEAT_HT_ASSIST_F10HY \ - OPTION_IDS_FEAT_HT_ASSIST_F15_OR - - #define OPTION_IDS_FEAT_ECCSYMBOLSIZE\ - OPTION_IDS_FEAT_ECCSYMBOLSIZE_F10 \ - OPTION_IDS_FEAT_ECCSYMBOLSIZE_F15_OR - -/*---------------------------------------------------------------------------- - * Family 10 feat blocks - * - *---------------------------------------------------------------------------- - */ - #define OPTION_IDS_FEAT_ECCSYMBOLSIZE_F10 - #define OPTION_IDS_FEAT_ECCCTRL_F10 - #ifdef OPTION_FAMILY10H - #if OPTION_FAMILY10H == TRUE -//Ecc symbol size - extern CONST IDS_FEAT_STRUCT ROMDATA IdsFeatEccSymbolSizeBlockF10; - #undef OPTION_IDS_FEAT_ECCSYMBOLSIZE_F10 - #define OPTION_IDS_FEAT_ECCSYMBOLSIZE_F10 &IdsFeatEccSymbolSizeBlockF10, - -//ECC scrub control - extern CONST IDS_FEAT_STRUCT ROMDATA IdsFeatEccCtrlBlockF10; - #undef OPTION_IDS_FEAT_ECCCTRL_F10 - #define OPTION_IDS_FEAT_ECCCTRL_F10 &IdsFeatEccCtrlBlockF10, - #endif - #endif - - //Misc Features - #define OPTION_IDS_FEAT_HT_ASSIST_F10HY - #ifdef OPTION_FAMILY10H_HY - #if OPTION_FAMILY10H_HY == TRUE - #undef OPTION_IDS_FEAT_HT_ASSIST_F10HY - extern CONST IDS_FEAT_STRUCT ROMDATA IdsFeatHtAssistBlockPlatformCfgF10Hy; - - #define OPTION_IDS_FEAT_HT_ASSIST_F10HY \ - &IdsFeatHtAssistBlockPlatformCfgF10Hy, - #endif - #endif -/*---------------------------------------------------------------------------- - * Family 12 feat blocks - * - *---------------------------------------------------------------------------- - */ - #define OPTION_IDS_FEAT_GNB_PLATFORMCFGF12 - #define OPTION_IDS_FEAT_ECCCTRL_F12 - #define OPTION_IDS_FEAT_CPB_CTRL_F12 - #ifdef OPTION_FAMILY12H - #if OPTION_FAMILY12H == TRUE - extern CONST IDS_FEAT_STRUCT ROMDATA IdsFeatGnbPlatformCfgBlockF12; - #undef OPTION_IDS_FEAT_GNB_PLATFORMCFGF12 - #define OPTION_IDS_FEAT_GNB_PLATFORMCFGF12 &IdsFeatGnbPlatformCfgBlockF12, - - //ECC scrub control - extern CONST IDS_FEAT_STRUCT ROMDATA IdsFeatEccCtrlBlockF12; - #undef OPTION_IDS_FEAT_ECCCTRL_F12 - #define OPTION_IDS_FEAT_ECCCTRL_F12 &IdsFeatEccCtrlBlockF12, - - #undef OPTION_IDS_FEAT_CPB_CTRL_F12 - extern CONST IDS_FEAT_STRUCT ROMDATA IdsFeatCpbCtrlBlockF12; - #define OPTION_IDS_FEAT_CPB_CTRL_F12 &IdsFeatCpbCtrlBlockF12, - - #endif - #endif - -/*---------------------------------------------------------------------------- - * Family 14 feat blocks - * - *---------------------------------------------------------------------------- - */ - #define OPTION_IDS_FEAT_GNB_PLATFORMCFGF14 - #ifdef OPTION_FAMILY14H - #if OPTION_FAMILY14H == TRUE - extern CONST IDS_FEAT_STRUCT ROMDATA IdsFeatGnbPlatformCfgBlockF14; - #undef OPTION_IDS_FEAT_GNB_PLATFORMCFGF14 - #define OPTION_IDS_FEAT_GNB_PLATFORMCFGF14 &IdsFeatGnbPlatformCfgBlockF14, - #endif - #endif - -/*---------------------------------------------------------------------------- - * Family 15 OR feat blocks - * - *---------------------------------------------------------------------------- - */ - #define OPTION_IDS_FEAT_HTC_CTRL_F15_OR - #define OPTION_IDS_FEAT_MEMORY_MAPPING_F15_OR - #define OPTION_IDS_FEAT_HT_ASSIST_F15_OR - #define OPTION_IDS_FEAT_ECCCTRL_F15_OR - #define OPTION_IDS_FEAT_ECCSYMBOLSIZE_F15_OR - #ifdef OPTION_FAMILY15H_OR - #if OPTION_FAMILY15H_OR == TRUE - extern CONST IDS_FEAT_STRUCT ROMDATA IdsFeatHtcControlBlockF15Or; - extern CONST IDS_FEAT_STRUCT ROMDATA IdsFeatHtcControlLateBlockF15Or; - #undef OPTION_IDS_FEAT_HTC_CTRL_F15_OR - #define OPTION_IDS_FEAT_HTC_CTRL_F15_OR\ - &IdsFeatHtcControlBlockF15Or,\ - &IdsFeatHtcControlLateBlockF15Or, - - extern CONST IDS_FEAT_STRUCT ROMDATA IdsFeatMemoryMappingPostBeforeBlockF15Or; - extern CONST IDS_FEAT_STRUCT ROMDATA IdsFeatMemoryMappingChIntlvBlockF15Or; - #undef OPTION_IDS_FEAT_MEMORY_MAPPING_F15_OR - #define OPTION_IDS_FEAT_MEMORY_MAPPING_F15_OR\ - &IdsFeatMemoryMappingPostBeforeBlockF15Or,\ - &IdsFeatMemoryMappingChIntlvBlockF15Or, - - extern CONST IDS_FEAT_STRUCT ROMDATA IdsFeatHtAssistBlockPlatformCfgF15Or; - #undef OPTION_IDS_FEAT_HT_ASSIST_F15_OR - #define OPTION_IDS_FEAT_HT_ASSIST_F15_OR\ - &IdsFeatHtAssistBlockPlatformCfgF15Or, - - extern CONST IDS_FEAT_STRUCT ROMDATA IdsFeatEccCtrlBlockF15Or; - #undef OPTION_IDS_FEAT_ECCCTRL_F15_OR - #define OPTION_IDS_FEAT_ECCCTRL_F15_OR &IdsFeatEccCtrlBlockF15Or, - - extern CONST IDS_FEAT_STRUCT ROMDATA IdsFeatEccSymbolSizeBlockF15Or; - #undef OPTION_IDS_FEAT_ECCSYMBOLSIZE_F15_OR - #define OPTION_IDS_FEAT_ECCSYMBOLSIZE_F15_OR &IdsFeatEccSymbolSizeBlockF15Or, - - #endif - #endif - - - - CONST IDS_FEAT_STRUCT ROMDATA IdsFeatUcodeBlock = - { - IDS_FEAT_UCODE_UPDATE, - IDS_ALL_CORES, - IDS_UCODE, - IDS_FAMILY_ALL, - IdsSubUCode - }; - - CONST IDS_FEAT_STRUCT ROMDATA IdsFeatPowerPolicyBlock = - { - IDS_FEAT_POWER_POLICY, - IDS_ALL_CORES, - IDS_PLATFORMCFG_OVERRIDE, - IDS_FAMILY_ALL, - IdsSubPowerPolicyOverride - }; - - CONST IDS_FEAT_STRUCT ROMDATA IdsFeatTargetPstateBlock = - { - IDS_FEAT_TARGET_PSTATE, - IDS_BSP_ONLY, - IDS_INIT_LATE_AFTER, - IDS_FAMILY_ALL, - IdsSubTargetPstate - }; - - CONST IDS_FEAT_STRUCT ROMDATA IdsFeatPostPstateBlock = - { - IDS_FEAT_POSTPSTATE, - IDS_ALL_CORES, - IDS_CPU_Early_Override, - IDS_FAMILY_ALL, - IdsSubPostPState - }; - - //Dram controller Features - CONST IDS_FEAT_STRUCT ROMDATA IdsFeatDctAllMemClkBlock = - { - IDS_FEAT_DCT_ALLMEMCLK, - IDS_BSP_ONLY, - IDS_ALL_MEMORY_CLOCK, - IDS_FAMILY_ALL, - IdsSubAllMemClkEn - }; - - CONST IDS_FEAT_STRUCT ROMDATA IdsFeatDctGangModeBlock = - { - IDS_FEAT_DCT_GANGMODE, - IDS_BSP_ONLY, - IDS_GANGING_MODE, - IDS_FAMILY_ALL, - IdsSubGangingMode - }; - - CONST IDS_FEAT_STRUCT ROMDATA IdsFeatDctBurstLengthBlock = - { - IDS_FEAT_DCT_BURSTLENGTH, - IDS_BSP_ONLY, - IDS_BURST_LENGTH32, - AMD_FAMILY_10, - IdsSubBurstLength32 - }; - - CONST IDS_FEAT_STRUCT ROMDATA IdsFeatDctPowerDownCtrlBlock = - { - IDS_FEAT_DCT_POWERDOWN, - IDS_BSP_ONLY, - IDS_INIT_POST_BEFORE, - IDS_FAMILY_ALL, - IdsSubPowerDownCtrl - }; - - CONST IDS_FEAT_STRUCT ROMDATA IdsFeatDctDllShutDownBlock = - { - IDS_FEAT_DCT_DLLSHUTDOWN, - IDS_BSP_ONLY, - IDS_DLL_SHUT_DOWN, - IDS_FAMILY_ALL, - IdsSubDllShutDownSR - }; - - - CONST IDS_FEAT_STRUCT ROMDATA IdsFeatDctPowerDownModeBlock = - { - IDS_FEAT_DCT_POWERDOWN, - IDS_BSP_ONLY, - IDS_POWERDOWN_MODE, - IDS_FAMILY_ALL, - IdsSubPowerDownMode - }; - - CONST IDS_FEAT_STRUCT ROMDATA IdsFeatHdtOutBlock = - { - IDS_FEAT_HDTOUT, - IDS_BSP_ONLY, - IDS_INIT_EARLY_BEFORE, - IDS_FAMILY_ALL, - IdsSubHdtOut - }; - - CONST IDS_FEAT_STRUCT ROMDATA IdsFeatHtSettingBlock = - { - IDS_FEAT_HT_SETTING, - IDS_BSP_ONLY, - IDS_HT_CONTROL, - IDS_FAMILY_ALL, - IdsSubHtLinkControl - }; - - CONST IDS_FEAT_STRUCT* ROMDATA IdsCommonFeats[] = - { - &IdsFeatUcodeBlock, - &IdsFeatPowerPolicyBlock, - - &IdsFeatTargetPstateBlock, - - &IdsFeatPostPstateBlock, - - OPTION_IDS_FEAT_ECCSYMBOLSIZE - - OPTION_IDS_FEAT_ECCCTRL - - &IdsFeatDctAllMemClkBlock, - - &IdsFeatDctGangModeBlock, - - &IdsFeatDctBurstLengthBlock, - - &IdsFeatDctPowerDownCtrlBlock, - - &IdsFeatDctPowerDownModeBlock, - - &IdsFeatDctPowerDownModeBlock, - - OPTION_IDS_FEAT_HT_ASSIST - - &IdsFeatHdtOutBlock, - - &IdsFeatHtSettingBlock, - - OPTION_IDS_FEAT_GNB_PLATFORMCFG - - OPTION_IDS_FEAT_CPB_CTRL - - OPTION_IDS_FEAT_HTC_CTRL - - OPTION_IDS_FEAT_MEMORY_MAPPING - - OPTION_IDS_EXTEND_FEATS - - NULL - }; - #else - CONST IDS_FEAT_STRUCT* ROMDATA IdsCommonFeats[] = - { - NULL - }; - #endif//IDSOPT_CONTROL_ENABLED -#else - CONST IDS_FEAT_STRUCT* ROMDATA IdsCommonFeats[] = - { - NULL - }; -#endif// IDSOPT_IDS_ENABLED - - -#endif diff --git a/src/vendorcode/amd/agesa/f12/Config/OptionIoCstateInstall.h b/src/vendorcode/amd/agesa/f12/Config/OptionIoCstateInstall.h deleted file mode 100644 index 3402809b3f..0000000000 --- a/src/vendorcode/amd/agesa/f12/Config/OptionIoCstateInstall.h +++ /dev/null @@ -1,132 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * Install of build option: IO C-state - * - * Contains AMD AGESA install macros and test conditions. Output is the - * defaults tables reflecting the User's build options selection. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: Options - * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $ - */ -/***************************************************************************** - * - * Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ***************************************************************************/ - -#ifndef _OPTION_IO_CSTATE_INSTALL_H_ -#define _OPTION_IO_CSTATE_INSTALL_H_ - -#include "cpuIoCstate.h" - -/* This option is designed to be included into the platform solution install - * file. The platform solution install file will define the options status. - * Check to validate the definition - */ - -#define OPTION_IO_CSTATE_FEAT -#define F10_IO_CSTATE_SUPPORT -#define F12_IO_CSTATE_SUPPORT -#define F14_IO_CSTATE_SUPPORT -#define F15_OR_IO_CSTATE_SUPPORT - -#if OPTION_IO_CSTATE == TRUE - #if (AGESA_ENTRY_INIT_EARLY == TRUE) || (AGESA_ENTRY_INIT_POST == TRUE) || (AGESA_ENTRY_INIT_RESUME == TRUE) || (AGESA_ENTRY_INIT_LATE == TRUE) - #ifdef OPTION_FAMILY10H - #if OPTION_FAMILY10H == TRUE - #if OPTION_FAMILY10H_PH == TRUE - extern CONST CPU_FEATURE_DESCRIPTOR ROMDATA CpuFeatureIoCstate; - #undef OPTION_IO_CSTATE_FEAT - #define OPTION_IO_CSTATE_FEAT &CpuFeatureIoCstate, - extern CONST IO_CSTATE_FAMILY_SERVICES ROMDATA F10IoCstateSupport; - #undef F10_IO_CSTATE_SUPPORT - #define F10_IO_CSTATE_SUPPORT {AMD_FAMILY_10_PH, &F10IoCstateSupport}, - #endif - #endif - #endif - - #ifdef OPTION_FAMILY12H - #if OPTION_FAMILY12H == TRUE - #if OPTION_FAMILY12H_LN == TRUE - extern CONST CPU_FEATURE_DESCRIPTOR ROMDATA CpuFeatureIoCstate; - #undef OPTION_IO_CSTATE_FEAT - #define OPTION_IO_CSTATE_FEAT &CpuFeatureIoCstate, - extern CONST IO_CSTATE_FAMILY_SERVICES ROMDATA F12IoCstateSupport; - #undef F12_IO_CSTATE_SUPPORT - #define F12_IO_CSTATE_SUPPORT {AMD_FAMILY_12_LN, &F12IoCstateSupport}, - #endif - #endif - #endif - - #ifdef OPTION_FAMILY14H - #if OPTION_FAMILY14H == TRUE - #if OPTION_FAMILY14H_ON == TRUE - extern CONST CPU_FEATURE_DESCRIPTOR ROMDATA CpuFeatureIoCstate; - #undef OPTION_IO_CSTATE_FEAT - #define OPTION_IO_CSTATE_FEAT &CpuFeatureIoCstate, - extern CONST IO_CSTATE_FAMILY_SERVICES ROMDATA F14IoCstateSupport; - #undef F14_IO_CSTATE_SUPPORT - #define F14_IO_CSTATE_SUPPORT {AMD_FAMILY_14, &F14IoCstateSupport}, - #endif - #endif - #endif - - #ifdef OPTION_FAMILY15H - #if OPTION_FAMILY15H == TRUE - #if OPTION_FAMILY15H_OR == TRUE - extern CONST CPU_FEATURE_DESCRIPTOR ROMDATA CpuFeatureIoCstate; - #undef OPTION_IO_CSTATE_FEAT - #define OPTION_IO_CSTATE_FEAT &CpuFeatureIoCstate, - extern CONST IO_CSTATE_FAMILY_SERVICES ROMDATA F15OrIoCstateSupport; - #undef F15_OR_IO_CSTATE_SUPPORT - #define F15_OR_IO_CSTATE_SUPPORT {AMD_FAMILY_15_OR, &F15OrIoCstateSupport}, - #endif - #endif - #endif - - #endif -#endif - -CONST CPU_SPECIFIC_SERVICES_XLAT ROMDATA IoCstateFamilyServiceArray[] = -{ - F10_IO_CSTATE_SUPPORT - F12_IO_CSTATE_SUPPORT - F14_IO_CSTATE_SUPPORT - F15_OR_IO_CSTATE_SUPPORT - {0, NULL} -}; - -CONST CPU_FAMILY_SUPPORT_TABLE ROMDATA IoCstateFamilyServiceTable = -{ - (sizeof (IoCstateFamilyServiceArray) / sizeof (CPU_SPECIFIC_SERVICES_XLAT)), - &IoCstateFamilyServiceArray[0] -}; - -#endif // _OPTION_IO_CSTATE_INSTALL_H_ diff --git a/src/vendorcode/amd/agesa/f12/Config/OptionL3FeaturesInstall.h b/src/vendorcode/amd/agesa/f12/Config/OptionL3FeaturesInstall.h deleted file mode 100644 index 7f3ac0769f..0000000000 --- a/src/vendorcode/amd/agesa/f12/Config/OptionL3FeaturesInstall.h +++ /dev/null @@ -1,104 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * Install of build option: L3 Dependent Features - * - * Contains AMD AGESA install macros and test conditions. Output is the - * defaults tables reflecting the User's build options selection. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: Options - * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $ - */ -/***************************************************************************** - * - * Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ***************************************************************************/ - -#ifndef _OPTION_L3_FEATURES_INSTALL_H_ -#define _OPTION_L3_FEATURES_INSTALL_H_ - -#include "cpuL3Features.h" - -/* This option is designed to be included into the platform solution install - * file. The platform solution install file will define the options status. - * Check to validate the definition - */ -#define OPTION_L3_FEAT -#define F10_L3_FEAT_SUPPORT -#define F15_L3_FEAT_SUPPORT -#define L3_FEAT_AP_DISABLE_CACHE -#define L3_FEAT_AP_ENABLE_CACHE - -#if (OPTION_HT_ASSIST == TRUE || OPTION_ATM_MODE == TRUE) - #if (AGESA_ENTRY_INIT_EARLY == TRUE) || (AGESA_ENTRY_INIT_POST == TRUE) || (AGESA_ENTRY_INIT_MID == TRUE) || (AGESA_ENTRY_INIT_LATE_RESTORE == TRUE) - #ifdef OPTION_FAMILY10H - #if OPTION_FAMILY10H == TRUE - #if OPTION_FAMILY10H_HY == TRUE - extern CONST CPU_FEATURE_DESCRIPTOR ROMDATA CpuL3Features; - #undef OPTION_L3_FEAT - #define OPTION_L3_FEAT &CpuL3Features, - extern CONST L3_FEATURE_FAMILY_SERVICES ROMDATA F10L3Features; - #undef F10_L3_FEAT_SUPPORT - #define F10_L3_FEAT_SUPPORT {AMD_FAMILY_10_HY, &F10L3Features}, - #endif - #endif - #endif - - #ifdef OPTION_FAMILY15H - #if OPTION_FAMILY15H == TRUE - extern CONST CPU_FEATURE_DESCRIPTOR ROMDATA CpuL3Features; - #undef OPTION_L3_FEAT - #define OPTION_L3_FEAT &CpuL3Features, - extern CONST L3_FEATURE_FAMILY_SERVICES ROMDATA F15OrL3Features; - #undef F15_L3_FEAT_SUPPORT - #define F15_L3_FEAT_SUPPORT {AMD_FAMILY_15, &F15OrL3Features}, - #endif - #endif - - #undef L3_FEAT_AP_DISABLE_CACHE - #define L3_FEAT_AP_DISABLE_CACHE {AP_LATE_TASK_DISABLE_CACHE, (IMAGE_ENTRY) DisableAllCaches}, - #undef L3_FEAT_AP_ENABLE_CACHE - #define L3_FEAT_AP_ENABLE_CACHE {AP_LATE_TASK_ENABLE_CACHE, (IMAGE_ENTRY) EnableAllCaches}, - #endif -#endif - -CONST CPU_SPECIFIC_SERVICES_XLAT ROMDATA L3FeatureFamilyServiceArray[] = -{ - F10_L3_FEAT_SUPPORT - F15_L3_FEAT_SUPPORT - {0, NULL} -}; -CONST CPU_FAMILY_SUPPORT_TABLE ROMDATA L3FeatureFamilyServiceTable = -{ - (sizeof (L3FeatureFamilyServiceArray) / sizeof (CPU_SPECIFIC_SERVICES_XLAT)), - &L3FeatureFamilyServiceArray[0] -}; - -#endif // _OPTION_L3_FEATURES_INSTALL_H_ diff --git a/src/vendorcode/amd/agesa/f12/Config/OptionLowPwrPstateInstall.h b/src/vendorcode/amd/agesa/f12/Config/OptionLowPwrPstateInstall.h deleted file mode 100644 index 3f9a3def52..0000000000 --- a/src/vendorcode/amd/agesa/f12/Config/OptionLowPwrPstateInstall.h +++ /dev/null @@ -1,86 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * Install of build option: Low Power Pstate for PROCHOT_L Throttling. - * - * Contains AMD AGESA install macros and test conditions. Output is the - * defaults tables reflecting the User's build options selection. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: Options - * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $ - */ -/***************************************************************************** - * - * Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ***************************************************************************/ - -#ifndef _OPTION_LOW_PWR_PSTATE_INSTALL_H_ -#define _OPTION_LOW_PWR_PSTATE_INSTALL_H_ - -#include "cpuLowPwrPstate.h" - -/* This option is designed to be included into the platform solution install - * file. The platform solution install file will define the options status. - * Check to validate the definition - */ -#define OPTION_CPU_LOW_PWR_PSTATE_FOR_PROCHOT_FEAT -#define F15_LOW_PWR_PSTATE_SUPPORT - -#if OPTION_CPU_LOW_PWR_PSTATE_FOR_PROCHOT == TRUE - #if (AGESA_ENTRY_INIT_EARLY == TRUE) || (AGESA_ENTRY_INIT_POST == TRUE) || (AGESA_ENTRY_INIT_RESUME == TRUE) || (AGESA_ENTRY_INIT_LATE == TRUE) - // Family 15h - #ifdef OPTION_FAMILY15H - #if OPTION_FAMILY15H == TRUE - #if OPTION_FAMILY15H_OR == TRUE - extern CONST CPU_FEATURE_DESCRIPTOR ROMDATA CpuFeatureLowPwrPstate; - #undef OPTION_CPU_LOW_PWR_PSTATE_FOR_PROCHOT_FEAT - #define OPTION_CPU_LOW_PWR_PSTATE_FOR_PROCHOT_FEAT &CpuFeatureLowPwrPstate, - extern CONST LOW_PWR_PSTATE_FAMILY_SERVICES ROMDATA F15OrLowPwrPstateSupport; - #undef F15_LOW_PWR_PSTATE_SUPPORT - #define F15_LOW_PWR_PSTATE_SUPPORT {AMD_FAMILY_15_OR, &F15OrLowPwrPstateSupport}, - #endif - #endif - #endif - #endif -#endif - -CONST CPU_SPECIFIC_SERVICES_XLAT ROMDATA LowPwrPstateFamilyServiceArray[] = -{ - F15_LOW_PWR_PSTATE_SUPPORT - {0, NULL} -}; - -CONST CPU_FAMILY_SUPPORT_TABLE ROMDATA LowPwrPstateFamilyServiceTable = -{ - (sizeof (LowPwrPstateFamilyServiceArray) / sizeof (CPU_SPECIFIC_SERVICES_XLAT)), - &LowPwrPstateFamilyServiceArray[0] -}; - -#endif // _OPTION_LOW_PWR_PSTATE_INSTALL_H_ diff --git a/src/vendorcode/amd/agesa/f12/Config/OptionMemoryInstall.h b/src/vendorcode/amd/agesa/f12/Config/OptionMemoryInstall.h deleted file mode 100644 index 0fd8232ead..0000000000 --- a/src/vendorcode/amd/agesa/f12/Config/OptionMemoryInstall.h +++ /dev/null @@ -1,4202 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * Install of build option: Memory - * - * Contains AMD AGESA install macros and test conditions. Output is the - * defaults tables reflecting the User's build options selection. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: Options - * @e \$Revision: 49545 $ @e \$Date: 2011-03-25 05:58:58 +0800 (Fri, 25 Mar 2011) $ - */ -/***************************************************************************** - * - * Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ***************************************************************************/ - -#ifndef _OPTION_MEMORY_INSTALL_H_ -#define _OPTION_MEMORY_INSTALL_H_ - -#ifndef RUN_BROKEN_AGESA_TESTS - #define RUN_BROKEN_AGESA_TESTS 0 -#endif - -/*------------------------------------------------------------------------------- - * This option file is designed to be included into the platform solution install - * file. The platform solution install file will define the options status. - * Check to validate the definition - */ - -/*---------------------------------------------------------------------------------- - * FEATURE BLOCK FUNCTIONS - * - * This section defines function names that depend upon options that are selected - * in the platform solution install file. - */ -BOOLEAN MemFDefRet ( - IN OUT MEM_NB_BLOCK *NBPtr - ) -{ - return FALSE; -} - -BOOLEAN MemMDefRet ( - IN MEM_MAIN_DATA_BLOCK *MMPtr - ) -{ - return TRUE; -} - -BOOLEAN MemMDefRetFalse ( - IN MEM_MAIN_DATA_BLOCK *MMPtr - ) -{ - return FALSE; -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * - * This function initializes the northbridge block for dimm identification translator - * - * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK - * @param[in,out] *MemPtr - Pointer to the MEM_DATA_STRUCT - * @param[in,out] NodeID - ID of current node to construct - * @return TRUE - This is the correct constructor for the targeted node. - * @return FALSE - This isn't the correct constructor for the targeted node. - */ -BOOLEAN MemNIdentifyDimmConstructorRetDef ( - IN OUT MEM_NB_BLOCK *NBPtr, - IN OUT MEM_DATA_STRUCT *MemPtr, - IN UINT8 NodeID - ) -{ - return FALSE; -} -/*---------------------------------------------------------------------------------- - * TABLE FEATURE BLOCK FUNCTIONS - * - * This section defines function names that depend upon options that are selected - * in the platform solution install file. - */ -UINT8 MemFTableDefRet ( - IN OUT MEM_TABLE_ALIAS **MTPtr - ) -{ - return 0; -} -/*---------------------------------------------------------------------------------- - * FEATURE S3 BLOCK FUNCTIONS - * - * This section defines function names that depend upon options that are selected - * in the platform solution install file. - */ -BOOLEAN MemFS3DefConstructorRet ( - IN OUT VOID *S3NBPtr, - IN OUT MEM_DATA_STRUCT *MemPtr, - IN UINT8 NodeID - ) -{ - return TRUE; -} - -#if (OPTION_MEMCTLR_DR == TRUE) - #if ((AGESA_ENTRY_INIT_RESUME == TRUE) || (AGESA_ENTRY_INIT_S3SAVE == TRUE) || (AGESA_ENTRY_INIT_LATE_RESTORE == TRUE)) - #if (OPTION_S3_MEM_SUPPORT == TRUE) - extern MEM_RESUME_CONSTRUCTOR MemS3ResumeConstructNBBlockDr; - #define MEM_FEATURE_S3_RESUME_CONSTRUCTOR_DR MemS3ResumeConstructNBBlockDr - #else - #define MEM_FEATURE_S3_RESUME_CONSTRUCTOR_DR MemFS3DefConstructorRet - #endif - #else - #define MEM_FEATURE_S3_RESUME_CONSTRUCTOR_DR MemFS3DefConstructorRet - #endif - #if (AGESA_ENTRY_INIT_GENERAL_SERVICES == TRUE) - extern MEM_IDENDIMM_CONSTRUCTOR MemNIdentifyDimmConstructorDr; - #define MEM_IDENDIMM_DR MemNIdentifyDimmConstructorDr - #else - #define MEM_IDENDIMM_DR MemNIdentifyDimmConstructorRetDef - #endif -#endif - -#if (OPTION_MEMCTLR_DA == TRUE || OPTION_MEMCTLR_Ni == TRUE || OPTION_MEMCTLR_RB == TRUE || OPTION_MEMCTLR_PH == TRUE) - #if ((AGESA_ENTRY_INIT_RESUME == TRUE) || (AGESA_ENTRY_INIT_S3SAVE == TRUE) || (AGESA_ENTRY_INIT_LATE_RESTORE == TRUE)) - #if (OPTION_S3_MEM_SUPPORT == TRUE) - #if (OPTION_MEMCTLR_Ni == TRUE) - extern MEM_RESUME_CONSTRUCTOR MemS3ResumeConstructNBBlockNi; - #define MEM_FEATURE_S3_RESUME_CONSTRUCTOR_Ni MemS3ResumeConstructNBBlockNi - #else - #define MEM_FEATURE_S3_RESUME_CONSTRUCTOR_Ni MemFS3DefConstructorRet - #endif - #if (OPTION_MEMCTLR_DA == TRUE) - extern MEM_RESUME_CONSTRUCTOR MemS3ResumeConstructNBBlockDA; - #define MEM_FEATURE_S3_RESUME_CONSTRUCTOR_DA MemS3ResumeConstructNBBlockDA - #else - #define MEM_FEATURE_S3_RESUME_CONSTRUCTOR_DA MemFS3DefConstructorRet - #endif - #if (OPTION_MEMCTLR_PH == TRUE) - extern MEM_RESUME_CONSTRUCTOR MemS3ResumeConstructNBBlockPh; - #define MEM_FEATURE_S3_RESUME_CONSTRUCTOR_PH MemS3ResumeConstructNBBlockPh - #else - #define MEM_FEATURE_S3_RESUME_CONSTRUCTOR_PH MemFS3DefConstructorRet - #endif - #if (OPTION_MEMCTLR_RB == TRUE) - extern MEM_RESUME_CONSTRUCTOR MemS3ResumeConstructNBBlockRb; - #define MEM_FEATURE_S3_RESUME_CONSTRUCTOR_RB MemS3ResumeConstructNBBlockRb - #else - #define MEM_FEATURE_S3_RESUME_CONSTRUCTOR_RB MemFS3DefConstructorRet - #endif - #endif - #else - #define MEM_FEATURE_S3_RESUME_CONSTRUCTOR_DA MemFS3DefConstructorRet - #define MEM_FEATURE_S3_RESUME_CONSTRUCTOR_Ni MemFS3DefConstructorRet - #define MEM_FEATURE_S3_RESUME_CONSTRUCTOR_RB MemFS3DefConstructorRet - #define MEM_FEATURE_S3_RESUME_CONSTRUCTOR_PH MemFS3DefConstructorRet - #endif - #if (AGESA_ENTRY_INIT_GENERAL_SERVICES == TRUE) - extern MEM_IDENDIMM_CONSTRUCTOR MemNIdentifyDimmConstructorDA; - #define MEM_IDENDIMM_DA MemNIdentifyDimmConstructorDA - extern MEM_IDENDIMM_CONSTRUCTOR MemNIdentifyDimmConstructorRb; - #define MEM_IDENDIMM_RB MemNIdentifyDimmConstructorRb - extern MEM_IDENDIMM_CONSTRUCTOR MemNIdentifyDimmConstructorPh; - #define MEM_IDENDIMM_PH MemNIdentifyDimmConstructorPh - #else - #define MEM_IDENDIMM_DA MemNIdentifyDimmConstructorRetDef - #define MEM_IDENDIMM_RB MemNIdentifyDimmConstructorRetDef - #define MEM_IDENDIMM_PH MemNIdentifyDimmConstructorRetDef - #endif -#endif - -#if (OPTION_MEMCTLR_OR == TRUE) - #if ((AGESA_ENTRY_INIT_RESUME == TRUE) || (AGESA_ENTRY_INIT_S3SAVE == TRUE) || (AGESA_ENTRY_INIT_LATE_RESTORE == TRUE)) - #if (OPTION_S3_MEM_SUPPORT == TRUE) - extern MEM_RESUME_CONSTRUCTOR MemS3ResumeConstructNBBlockOr; - #define MEM_FEATURE_S3_RESUME_CONSTRUCTOR_OR MemS3ResumeConstructNBBlockOr - #else - #define MEM_FEATURE_S3_RESUME_CONSTRUCTOR_OR MemFS3DefConstructorRet - #endif - #else - #define MEM_FEATURE_S3_RESUME_CONSTRUCTOR_OR MemFS3DefConstructorRet - #endif - #if (AGESA_ENTRY_INIT_GENERAL_SERVICES == TRUE) - extern MEM_IDENDIMM_CONSTRUCTOR MemNIdentifyDimmConstructorOr; - #define MEM_IDENDIMM_OR MemNIdentifyDimmConstructorOr - #else - #define MEM_IDENDIMM_OR MemNIdentifyDimmConstructorRetDef - #endif -#endif - -#if (OPTION_MEMCTLR_HY == TRUE) - #if ((AGESA_ENTRY_INIT_RESUME == TRUE) || (AGESA_ENTRY_INIT_S3SAVE == TRUE) || (AGESA_ENTRY_INIT_LATE_RESTORE == TRUE)) - #if (OPTION_S3_MEM_SUPPORT == TRUE) - extern MEM_RESUME_CONSTRUCTOR MemS3ResumeConstructNBBlockHy; - #define MEM_FEATURE_S3_RESUME_CONSTRUCTOR_HY MemS3ResumeConstructNBBlockHy - #else - #define MEM_FEATURE_S3_RESUME_CONSTRUCTOR_HY MemFS3DefConstructorRet - #endif - #else - #define MEM_FEATURE_S3_RESUME_CONSTRUCTOR_HY MemFS3DefConstructorRet - #endif - #if (AGESA_ENTRY_INIT_GENERAL_SERVICES == TRUE) - extern MEM_IDENDIMM_CONSTRUCTOR MemNIdentifyDimmConstructorHy; - #define MEM_IDENDIMM_HY MemNIdentifyDimmConstructorHy - #else - #define MEM_IDENDIMM_HY MemNIdentifyDimmConstructorRetDef - #endif -#endif - -#if (OPTION_MEMCTLR_C32 == TRUE) - #if ((AGESA_ENTRY_INIT_RESUME == TRUE) || (AGESA_ENTRY_INIT_S3SAVE == TRUE) || (AGESA_ENTRY_INIT_LATE_RESTORE == TRUE)) - #if (OPTION_S3_MEM_SUPPORT == TRUE) - extern MEM_RESUME_CONSTRUCTOR MemS3ResumeConstructNBBlockC32; - #define MEM_FEATURE_S3_RESUME_CONSTRUCTOR_C32 MemS3ResumeConstructNBBlockC32 - #else - #define MEM_FEATURE_S3_RESUME_CONSTRUCTOR_C32 MemFS3DefConstructorRet - #endif - #else - #define MEM_FEATURE_S3_RESUME_CONSTRUCTOR_C32 MemFS3DefConstructorRet - #endif - #if (AGESA_ENTRY_INIT_GENERAL_SERVICES == TRUE) - extern MEM_IDENDIMM_CONSTRUCTOR MemNIdentifyDimmConstructorC32; - #define MEM_IDENDIMM_C32 MemNIdentifyDimmConstructorC32 - #else - #define MEM_IDENDIMM_C32 MemNIdentifyDimmConstructorRetDef - #endif -#endif - -#if (OPTION_MEMCTLR_LN == TRUE) - #if ((AGESA_ENTRY_INIT_RESUME == TRUE) || (AGESA_ENTRY_INIT_S3SAVE == TRUE) || (AGESA_ENTRY_INIT_LATE_RESTORE == TRUE)) - #if (OPTION_S3_MEM_SUPPORT == TRUE) - extern MEM_RESUME_CONSTRUCTOR MemS3ResumeConstructNBBlockLN; - #define MEM_FEATURE_S3_RESUME_CONSTRUCTOR_LN MemS3ResumeConstructNBBlockLN - #else - #define MEM_FEATURE_S3_RESUME_CONSTRUCTOR_LN MemFS3DefConstructorRet - #endif - #else - #define MEM_FEATURE_S3_RESUME_CONSTRUCTOR_LN MemFS3DefConstructorRet - #endif - #if (AGESA_ENTRY_INIT_GENERAL_SERVICES == TRUE) - extern MEM_IDENDIMM_CONSTRUCTOR MemNIdentifyDimmConstructorLN; - #define MEM_IDENDIMM_LN MemNIdentifyDimmConstructorLN - #else - #define MEM_IDENDIMM_LN MemNIdentifyDimmConstructorRetDef - #endif -#endif - -#if (OPTION_MEMCTLR_ON == TRUE) - #if ((AGESA_ENTRY_INIT_RESUME == TRUE) || (AGESA_ENTRY_INIT_S3SAVE == TRUE) || (AGESA_ENTRY_INIT_LATE_RESTORE == TRUE)) - #if (OPTION_S3_MEM_SUPPORT == TRUE) - extern MEM_RESUME_CONSTRUCTOR MemS3ResumeConstructNBBlockON; - #define MEM_FEATURE_S3_RESUME_CONSTRUCTOR_ON MemS3ResumeConstructNBBlockON - #else - #define MEM_FEATURE_S3_RESUME_CONSTRUCTOR_ON MemFS3DefConstructorRet - #endif - #else - #define MEM_FEATURE_S3_RESUME_CONSTRUCTOR_ON MemFS3DefConstructorRet - #endif - #if (AGESA_ENTRY_INIT_GENERAL_SERVICES == TRUE) - extern MEM_IDENDIMM_CONSTRUCTOR MemNIdentifyDimmConstructorON; - #define MEM_IDENDIMM_ON MemNIdentifyDimmConstructorON - #else - #define MEM_IDENDIMM_ON MemNIdentifyDimmConstructorRetDef - #endif -#endif - -/*---------------------------------------------------------------------------------- - * NORTHBRIDGE BLOCK CONSTRUCTOR AND INITIALIZER FUNCTION DEFAULT ASSIGNMENTS - * - *---------------------------------------------------------------------------------- -*/ -#define MEM_NB_SUPPORT_DR -#define MEM_NB_SUPPORT_RB -#define MEM_NB_SUPPORT_DA -#define MEM_NB_SUPPORT_Ni -#define MEM_NB_SUPPORT_PH -#define MEM_NB_SUPPORT_HY -#define MEM_NB_SUPPORT_LN -#define MEM_NB_SUPPORT_OR -#define MEM_NB_SUPPORT_C32 -#define MEM_NB_SUPPORT_ON -#define MEM_NB_SUPPORT_END { MEM_NB_SUPPORT_STRUCT_VERSION, 0, 0, 0, 0, 0 } - -#if (AGESA_ENTRY_INIT_POST == TRUE) - /*---------------------------------------------------------------------------------- - * FLOW CONTROL FUNCTION - * - * This section selects the function that controls the memory initialization sequence - * based upon the number of processor families that the BIOS will support. - */ - - extern MEM_FLOW_CFG MemMFlowDef; - #if (OPTION_MEMCTLR_DR == TRUE) - extern MEM_FLOW_CFG MemMFlowDr; - #define MEM_MAIN_FLOW_CONTROL_PTR_Dr MemMFlowDr, - #else - #define MEM_MAIN_FLOW_CONTROL_PTR_Dr MemMFlowDef, - #endif - #if (OPTION_MEMCTLR_DA == TRUE) - extern MEM_FLOW_CFG MemMFlowDA; - #define MEM_MAIN_FLOW_CONTROL_PTR_DA MemMFlowDA, - #else - #define MEM_MAIN_FLOW_CONTROL_PTR_DA MemMFlowDef, - #endif - #if (OPTION_MEMCTLR_HY == TRUE) - extern MEM_FLOW_CFG MemMFlowHy; - #define MEM_MAIN_FLOW_CONTROL_PTR_Hy MemMFlowHy, - #else - #define MEM_MAIN_FLOW_CONTROL_PTR_Hy MemMFlowDef, - #endif - #if (OPTION_MEMCTLR_OR == TRUE) - extern MEM_FLOW_CFG MemMFlowOr; - #define MEM_MAIN_FLOW_CONTROL_PTR_OR MemMFlowOr, - #else - #define MEM_MAIN_FLOW_CONTROL_PTR_OR MemMFlowDef, - #endif - #if (OPTION_MEMCTLR_LN == TRUE) - extern MEM_FLOW_CFG MemMFlowLN; - #define MEM_MAIN_FLOW_CONTROL_PTR_LN MemMFlowLN, - #else - #define MEM_MAIN_FLOW_CONTROL_PTR_LN MemMFlowDef, - #endif - #if (OPTION_MEMCTLR_C32 == TRUE) - extern MEM_FLOW_CFG MemMFlowC32; - #define MEM_MAIN_FLOW_CONTROL_PTR_C32 MemMFlowC32, - #else - #define MEM_MAIN_FLOW_CONTROL_PTR_C32 MemMFlowDef, - #endif - #if (OPTION_MEMCTLR_ON == TRUE) - extern MEM_FLOW_CFG MemMFlowON; - #define MEM_MAIN_FLOW_CONTROL_PTR_ON MemMFlowON, - #else - #define MEM_MAIN_FLOW_CONTROL_PTR_ON MemMFlowDef, - #endif - #if (OPTION_MEMCTLR_Ni == TRUE) - extern MEM_FLOW_CFG MemMFlowDA; - #define MEM_MAIN_FLOW_CONTROL_PTR_Ni MemMFlowDA, - #else - #define MEM_MAIN_FLOW_CONTROL_PTR_Ni MemMFlowDef, - #endif - #if (OPTION_MEMCTLR_RB == TRUE) - extern MEM_FLOW_CFG MemMFlowRb; - #define MEM_MAIN_FLOW_CONTROL_PTR_RB MemMFlowRb, - #else - #define MEM_MAIN_FLOW_CONTROL_PTR_RB MemMFlowDef, - #endif - #if (OPTION_MEMCTLR_PH == TRUE) - extern MEM_FLOW_CFG MemMFlowPh; - #define MEM_MAIN_FLOW_CONTROL_PTR_PH MemMFlowPh, - #else - #define MEM_MAIN_FLOW_CONTROL_PTR_PH MemMFlowDef, - #endif - - MEM_FLOW_CFG* memFlowControlInstalled[] = { - MEM_MAIN_FLOW_CONTROL_PTR_Dr - MEM_MAIN_FLOW_CONTROL_PTR_DA - MEM_MAIN_FLOW_CONTROL_PTR_RB - MEM_MAIN_FLOW_CONTROL_PTR_PH - MEM_MAIN_FLOW_CONTROL_PTR_Hy - MEM_MAIN_FLOW_CONTROL_PTR_OR - MEM_MAIN_FLOW_CONTROL_PTR_LN - MEM_MAIN_FLOW_CONTROL_PTR_C32 - MEM_MAIN_FLOW_CONTROL_PTR_ON - MEM_MAIN_FLOW_CONTROL_PTR_Ni - NULL - }; - - #if (OPTION_ONLINE_SPARE == TRUE) - extern OPTION_MEM_FEATURE_MAIN MemMOnlineSpare; - #define MEM_MAIN_FEATURE_ONLINE_SPARE MemMOnlineSpare - extern OPTION_MEM_FEATURE_NB MemFOnlineSpare; - #define MEM_FEATURE_ONLINE_SPARE MemFOnlineSpare - #else - #define MEM_MAIN_FEATURE_ONLINE_SPARE MemMDefRet - #define MEM_FEATURE_ONLINE_SPARE MemFDefRet - #endif - - #if (OPTION_MEM_RESTORE == TRUE) - extern OPTION_MEM_FEATURE_MAIN MemMContextSave; - extern OPTION_MEM_FEATURE_MAIN MemMContextRestore; - #define MEM_MAIN_FEATURE_MEM_SAVE MemMContextSave - #define MEM_MAIN_FEATURE_MEM_RESTORE MemMContextRestore - #else - #define MEM_MAIN_FEATURE_MEM_SAVE MemMDefRet - #define MEM_MAIN_FEATURE_MEM_RESTORE MemMDefRetFalse - #endif - - #if (OPTION_BANK_INTERLEAVE == TRUE) - extern OPTION_MEM_FEATURE_NB MemFInterleaveBanks; - #define MEM_FEATURE_BANK_INTERLEAVE MemFInterleaveBanks - extern OPTION_MEM_FEATURE_NB MemFUndoInterleaveBanks; - #define MEM_FEATURE_UNDO_BANK_INTERLEAVE MemFUndoInterleaveBanks - #else - #define MEM_FEATURE_BANK_INTERLEAVE MemFDefRet - #define MEM_FEATURE_UNDO_BANK_INTERLEAVE MemFDefRet - #endif - - #if (OPTION_NODE_INTERLEAVE == TRUE) - extern OPTION_MEM_FEATURE_MAIN MemMInterleaveNodes; - #define MEM_MAIN_FEATURE_NODE_INTERLEAVE MemMInterleaveNodes - extern OPTION_MEM_FEATURE_NB MemFCheckInterleaveNodes; - extern OPTION_MEM_FEATURE_NB MemFInterleaveNodes; - #define MEM_FEATURE_NODE_INTERLEAVE_CHECK MemFCheckInterleaveNodes - #define MEM_FEATURE_NODE_INTERLEAVE MemFInterleaveNodes - #else - #define MEM_FEATURE_NODE_INTERLEAVE_CHECK MemFDefRet - #define MEM_FEATURE_NODE_INTERLEAVE MemFDefRet - #define MEM_MAIN_FEATURE_NODE_INTERLEAVE MemMDefRet - #endif - - #if (OPTION_DCT_INTERLEAVE == TRUE) - extern OPTION_MEM_FEATURE_NB MemFInterleaveChannels; - #define MEM_FEATURE_CHANNEL_INTERLEAVE MemFInterleaveChannels - #else - #define MEM_FEATURE_CHANNEL_INTERLEAVE MemFDefRet - #endif - - #if (OPTION_ECC == TRUE) - extern OPTION_MEM_FEATURE_MAIN MemMEcc; - #define MEM_MAIN_FEATURE_ECC MemMEcc - extern OPTION_MEM_FEATURE_NB MemFCheckECC; - extern OPTION_MEM_FEATURE_NB MemFInitECC; - #define MEM_FEATURE_CK_ECC MemFCheckECC - #define MEM_FEATURE_ECC MemFInitECC - #define MEM_FEATURE_ECCX8 MemMDefRet - #else - #define MEM_MAIN_FEATURE_ECC MemMDefRet - #define MEM_FEATURE_CK_ECC MemFDefRet - #define MEM_FEATURE_ECC MemFDefRet - #define MEM_FEATURE_ECCX8 MemMDefRet - #endif - - extern OPTION_MEM_FEATURE_MAIN MemMMctMemClr; - #define MEM_MAIN_FEATURE_MEM_CLEAR MemMMctMemClr - - #if (OPTION_DMI == TRUE) - #if (OPTION_DDR3 == TRUE) - extern OPTION_MEM_FEATURE_MAIN MemFDMISupport3; - #define MEM_MAIN_FEATURE_MEM_DMI MemFDMISupport3 - #else - extern OPTION_MEM_FEATURE_MAIN MemFDMISupport2; - #define MEM_MAIN_FEATURE_MEM_DMI MemFDMISupport2 - #endif - #else - #define MEM_MAIN_FEATURE_MEM_DMI MemMDefRet - #endif - - #if (OPTION_DDR3 == TRUE) - extern OPTION_MEM_FEATURE_NB MemFOnDimmThermal; - extern OPTION_MEM_FEATURE_MAIN MemMLvDdr3; - extern OPTION_MEM_FEATURE_NB MemFLvDdr3; - #define MEM_FEATURE_ONDIMMTHERMAL MemFOnDimmThermal - #define MEM_MAIN_FEATURE_LVDDR3 MemMLvDdr3 - #define MEM_FEATURE_LVDDR3 MemFLvDdr3 - #else - #define MEM_FEATURE_ONDIMMTHERMAL MemFDefRet - #define MEM_MAIN_FEATURE_LVDDR3 MemMDefRet - #define MEM_FEATURE_LVDDR3 MemFDefRet - #endif - - extern OPTION_MEM_FEATURE_NB MemFInterleaveRegion; - #define MEM_FEATURE_REGION_INTERLEAVE MemFInterleaveRegion - - extern OPTION_MEM_FEATURE_MAIN MemMUmaAlloc; - #define MEM_MAIN_FEATURE_UMAALLOC MemMUmaAlloc - - extern OPTION_MEM_FEATURE_MAIN MemMStandardTraining; - #if (OPTION_PARALLEL_TRAINING == TRUE) - extern OPTION_MEM_FEATURE_MAIN MemMParallelTraining; - #define MEM_MAIN_FEATURE_TRAINING MemMParallelTraining - #else - #define MEM_MAIN_FEATURE_TRAINING MemMStandardTraining - #endif - - #if (OPTION_DIMM_EXCLUDE == TRUE) - extern OPTION_MEM_FEATURE_MAIN MemMRASExcludeDIMM; - #define MEM_MAIN_FEATURE_DIMM_EXCLUDE MemMRASExcludeDIMM - extern OPTION_MEM_FEATURE_NB MemFRASExcludeDIMM; - #define MEM_FEATURE_DIMM_EXCLUDE MemFRASExcludeDIMM - #else - #define MEM_FEATURE_DIMM_EXCLUDE MemFDefRet - #define MEM_MAIN_FEATURE_DIMM_EXCLUDE MemMDefRet - #endif - - /*---------------------------------------------------------------------------------- - * TECHNOLOGY BLOCK CONSTRUCTOR FUNCTION ASSIGNMENTS - * - *---------------------------------------------------------------------------------- - */ - #if OPTION_DDR2 == TRUE - extern MEM_TECH_CONSTRUCTOR MemConstructTechBlock2; - #define MEM_TECH_CONSTRUCTOR_DDR2 MemConstructTechBlock2, - #if (OPTION_HW_DRAM_INIT == TRUE) - extern MEM_TECH_FEAT MemTDramInitHw; - #define MEM_TECH_FEATURE_HW_DRAMINIT MemTDramInitHw - #else - #define MEM_TECH_FEATURE_HW_DRAMINIT MemTFeatDef - #endif - #if (OPTION_SW_DRAM_INIT == TRUE) - #define MEM_TECH_FEATURE_SW_DRAMINIT MemTFeatDef - #else - #define MEM_TECH_FEATURE_SW_DRAMINIT MemTFeatDef - #endif - #else - #define MEM_TECH_CONSTRUCTOR_DDR2 - #endif - #if OPTION_DDR3 == TRUE - extern MEM_TECH_CONSTRUCTOR MemConstructTechBlock3; - #define MEM_TECH_CONSTRUCTOR_DDR3 MemConstructTechBlock3, - #if (OPTION_HW_DRAM_INIT == TRUE) - extern MEM_TECH_FEAT MemTDramInitHw; - #define MEM_TECH_FEATURE_HW_DRAMINIT MemTDramInitHw - #else - #define MEM_TECH_FEATURE_HW_DRAMINIT MemTFeatDef - #endif - #if (OPTION_SW_DRAM_INIT == TRUE) - #define MEM_TECH_FEATURE_SW_DRAMINIT MemTDramInitSw3 - #else - #define MEM_TECH_FEATURE_SW_DRAMINIT MemTFeatDef - #endif - #else - #define MEM_TECH_CONSTRUCTOR_DDR3 - #endif - - /*--------------------------------------------------------------------------------------------------- - * FEATURE BLOCKS - * - * This section instantiates a feature block structure for each memory controller installed - * by the platform solution install file. - *--------------------------------------------------------------------------------------------------- - */ - - /*--------------------------------------------------------------------------------------------------- - * DEERHOUND FEATURE BLOCK - *--------------------------------------------------------------------------------------------------- - */ - #if (OPTION_MEMCTLR_DR == TRUE) - #if OPTION_DDR2 - #undef MEM_TECH_FEATURE_DRAMINIT - #define MEM_TECH_FEATURE_DRAMINIT MEM_TECH_FEATURE_HW_DRAMINIT - #endif - #if OPTION_DDR3 - #undef MEM_TECH_FEATURE_DRAMINIT - #define MEM_TECH_FEATURE_DRAMINIT MEM_TECH_FEATURE_SW_DRAMINIT - #endif - - #undef MEM_TECH_FEATURE_CPG - #define MEM_TECH_FEATURE_CPG MemFDefRet - - #if (OPTION_HW_DQS_REC_EN_TRAINING == TRUE) - extern OPTION_MEM_FEATURE_NB MemNInitDqsTrainRcvrEnHwNb; - #undef MEM_TECH_FEATURE_HWRXEN - #define MEM_TECH_FEATURE_HWRXEN MemNInitDqsTrainRcvrEnHwNb - #else - extern OPTION_MEM_FEATURE_NB MemNDisableDqsTrainRcvrEnHwNb; - #undef MEM_TECH_FEATURE_HWRXEN - #define MEM_TECH_FEATURE_HWRXEN MemNDisableDqsTrainRcvrEnHwNb - #endif - - #undef MEM_MAIN_FEATURE_TRAINING - #undef MEM_FEATURE_TRAINING -// extern OPTION_MEM_FEATURE_MAIN MemMStandardTraining; - #define MEM_MAIN_FEATURE_TRAINING MemMStandardTraining - extern OPTION_MEM_FEATURE_NB MemFStandardTraining; - #define MEM_FEATURE_TRAINING MemFStandardTraining - - MEM_FEAT_BLOCK_NB MemFeatBlockDr = { - MEM_FEAT_BLOCK_NB_STRUCT_VERSION, - MEM_FEATURE_ONLINE_SPARE, - MEM_FEATURE_BANK_INTERLEAVE, - MEM_FEATURE_UNDO_BANK_INTERLEAVE, - MEM_FEATURE_NODE_INTERLEAVE_CHECK, - MEM_FEATURE_NODE_INTERLEAVE, - MEM_FEATURE_CHANNEL_INTERLEAVE, - MemFDefRet, - MEM_FEATURE_CK_ECC, - MEM_FEATURE_ECC, - MEM_FEATURE_TRAINING, - MEM_FEATURE_LVDDR3, - MemFDefRet, - MEM_TECH_FEATURE_DRAMINIT, - MEM_FEATURE_DIMM_EXCLUDE, - MemFDefRet, - MEM_TECH_FEATURE_CPG, - MEM_TECH_FEATURE_HWRXEN - }; - - #undef MEM_NB_SUPPORT_DR - extern MEM_NB_CONSTRUCTOR MemConstructNBBlockDR; - extern MEM_INITIALIZER MemNInitDefaultsDR; - - - #define MEM_NB_SUPPORT_DR { MEM_NB_SUPPORT_STRUCT_VERSION, MemConstructNBBlockDR, MemNInitDefaultsDR, &MemFeatBlockDr, MEM_FEATURE_S3_RESUME_CONSTRUCTOR_DR, MEM_IDENDIMM_DR }, - #endif // OPTION_MEMCTRL_DR - - /*--------------------------------------------------------------------------------------------------- - * DASHOUND FEATURE BLOCK - *--------------------------------------------------------------------------------------------------- - */ - #if (OPTION_MEMCTLR_DA == TRUE || OPTION_MEMCTLR_Ni == TRUE || OPTION_MEMCTLR_RB == TRUE || OPTION_MEMCTLR_PH == TRUE) - #if OPTION_DDR2 - #undef MEM_TECH_FEATURE_DRAMINIT - #define MEM_TECH_FEATURE_DRAMINIT MEM_TECH_FEATURE_HW_DRAMINIT - #endif - #if OPTION_DDR3 - #undef MEM_TECH_FEATURE_DRAMINIT - #define MEM_TECH_FEATURE_DRAMINIT MEM_TECH_FEATURE_SW_DRAMINIT - #endif - - #undef MEM_TECH_FEATURE_CPG - #define MEM_TECH_FEATURE_CPG MemFDefRet - - #if (OPTION_HW_DQS_REC_EN_TRAINING == TRUE) - extern OPTION_MEM_FEATURE_NB MemNInitDqsTrainRcvrEnHwNb; - #undef MEM_TECH_FEATURE_HWRXEN - #define MEM_TECH_FEATURE_HWRXEN MemNInitDqsTrainRcvrEnHwNb - #else - extern OPTION_MEM_FEATURE_NB MemNDisableDqsTrainRcvrEnHwNb; - #undef MEM_TECH_FEATURE_HWRXEN - #define MEM_TECH_FEATURE_HWRXEN MemNDisableDqsTrainRcvrEnHwNb - #endif - - #undef MEM_MAIN_FEATURE_TRAINING - #undef MEM_FEATURE_TRAINING -// extern OPTION_MEM_FEATURE_MAIN MemMStandardTraining; - #define MEM_MAIN_FEATURE_TRAINING MemMStandardTraining - extern OPTION_MEM_FEATURE_NB MemFStandardTraining; - #define MEM_FEATURE_TRAINING MemFStandardTraining - - #if (OPTION_MEMCTLR_Ni == TRUE) - MEM_FEAT_BLOCK_NB MemFeatBlockNi = { - MEM_FEAT_BLOCK_NB_STRUCT_VERSION, - MemFDefRet, - MEM_FEATURE_BANK_INTERLEAVE, - MEM_FEATURE_UNDO_BANK_INTERLEAVE, - MemFDefRet, - MemFDefRet, - MEM_FEATURE_CHANNEL_INTERLEAVE, - MEM_FEATURE_REGION_INTERLEAVE, - MEM_FEATURE_CK_ECC, - MEM_FEATURE_ECC, - MEM_FEATURE_TRAINING, - MEM_FEATURE_LVDDR3, - MemFDefRet, - MEM_TECH_FEATURE_DRAMINIT, - MEM_FEATURE_DIMM_EXCLUDE, - MemFDefRet, - MEM_TECH_FEATURE_CPG, - MEM_TECH_FEATURE_HWRXEN - }; - - #undef MEM_NB_SUPPORT_Ni - extern MEM_NB_CONSTRUCTOR MemConstructNBBlockNi; - extern MEM_INITIALIZER MemNInitDefaultsNi; - - #define MEM_NB_SUPPORT_Ni { MEM_NB_SUPPORT_STRUCT_VERSION, MemConstructNBBlockNi, MemNInitDefaultsNi, &MemFeatBlockNi, MEM_FEATURE_S3_RESUME_CONSTRUCTOR_Ni, MEM_IDENDIMM_DA }, - #endif - - #if (OPTION_MEMCTLR_PH == TRUE) - MEM_FEAT_BLOCK_NB MemFeatBlockPh = { - MEM_FEAT_BLOCK_NB_STRUCT_VERSION, - MemFDefRet, - MEM_FEATURE_BANK_INTERLEAVE, - MEM_FEATURE_UNDO_BANK_INTERLEAVE, - MemFDefRet, - MemFDefRet, - MEM_FEATURE_CHANNEL_INTERLEAVE, - MEM_FEATURE_REGION_INTERLEAVE, - MEM_FEATURE_CK_ECC, - MEM_FEATURE_ECC, - MEM_FEATURE_TRAINING, - MEM_FEATURE_LVDDR3, - MemFDefRet, - MEM_TECH_FEATURE_DRAMINIT, - MEM_FEATURE_DIMM_EXCLUDE, - MemFDefRet, - MEM_TECH_FEATURE_CPG, - MEM_TECH_FEATURE_HWRXEN - }; - - #undef MEM_NB_SUPPORT_PH - extern MEM_NB_CONSTRUCTOR MemConstructNBBlockPh; - extern MEM_INITIALIZER MemNInitDefaultsPh; - - #define MEM_NB_SUPPORT_PH { MEM_NB_SUPPORT_STRUCT_VERSION, MemConstructNBBlockPh, MemNInitDefaultsPh, &MemFeatBlockPh, MEM_FEATURE_S3_RESUME_CONSTRUCTOR_PH, MEM_IDENDIMM_PH }, - #endif - - #if (OPTION_MEMCTLR_RB == TRUE) - MEM_FEAT_BLOCK_NB MemFeatBlockRb = { - MEM_FEAT_BLOCK_NB_STRUCT_VERSION, - MemFDefRet, - MEM_FEATURE_BANK_INTERLEAVE, - MEM_FEATURE_UNDO_BANK_INTERLEAVE, - MemFDefRet, - MemFDefRet, - MEM_FEATURE_CHANNEL_INTERLEAVE, - MEM_FEATURE_REGION_INTERLEAVE, - MEM_FEATURE_CK_ECC, - MEM_FEATURE_ECC, - MEM_FEATURE_TRAINING, - MEM_FEATURE_LVDDR3, - MemFDefRet, - MEM_TECH_FEATURE_DRAMINIT, - MEM_FEATURE_DIMM_EXCLUDE, - MemFDefRet, - MEM_TECH_FEATURE_CPG, - MEM_TECH_FEATURE_HWRXEN - }; - - #undef MEM_NB_SUPPORT_RB - extern MEM_NB_CONSTRUCTOR MemConstructNBBlockRb; - extern MEM_INITIALIZER MemNInitDefaultsRb; - - #define MEM_NB_SUPPORT_RB { MEM_NB_SUPPORT_STRUCT_VERSION, MemConstructNBBlockRb, MemNInitDefaultsRb, &MemFeatBlockRb, MEM_FEATURE_S3_RESUME_CONSTRUCTOR_RB, MEM_IDENDIMM_RB }, - #endif - - #if (OPTION_MEMCTLR_DA == TRUE) - MEM_FEAT_BLOCK_NB MemFeatBlockDA = { - MEM_FEAT_BLOCK_NB_STRUCT_VERSION, - MemFDefRet, - MEM_FEATURE_BANK_INTERLEAVE, - MEM_FEATURE_UNDO_BANK_INTERLEAVE, - MemFDefRet, - MemFDefRet, - MEM_FEATURE_CHANNEL_INTERLEAVE, - MEM_FEATURE_REGION_INTERLEAVE, - MEM_FEATURE_CK_ECC, - MEM_FEATURE_ECC, - MEM_FEATURE_TRAINING, - MEM_FEATURE_LVDDR3, - MemFDefRet, - MEM_TECH_FEATURE_DRAMINIT, - MEM_FEATURE_DIMM_EXCLUDE, - MemFDefRet, - MEM_TECH_FEATURE_CPG, - MEM_TECH_FEATURE_HWRXEN - }; - - #undef MEM_NB_SUPPORT_DA - extern MEM_NB_CONSTRUCTOR MemConstructNBBlockDA; - extern MEM_INITIALIZER MemNInitDefaultsDA; - - #define MEM_NB_SUPPORT_DA { MEM_NB_SUPPORT_STRUCT_VERSION, MemConstructNBBlockDA, MemNInitDefaultsDA, &MemFeatBlockDA, MEM_FEATURE_S3_RESUME_CONSTRUCTOR_DA, MEM_IDENDIMM_DA }, - #endif - #endif // OPTION_MEMCTRL_DA - - /*--------------------------------------------------------------------------------------------------- - * HYDRA FEATURE BLOCK - *--------------------------------------------------------------------------------------------------- - */ - #if (OPTION_MEMCTLR_HY == TRUE) - #if OPTION_DDR2 - #undef MEM_TECH_FEATURE_DRAMINIT - #define MEM_TECH_FEATURE_DRAMINIT MEM_TECH_FEATURE_HW_DRAMINIT - #endif - #if OPTION_DDR3 - #undef MEM_TECH_FEATURE_DRAMINIT - #define MEM_TECH_FEATURE_DRAMINIT MEM_TECH_FEATURE_SW_DRAMINIT - #endif - - #undef MEM_TECH_FEATURE_CPG - #define MEM_TECH_FEATURE_CPG MemFDefRet - - #if (OPTION_HW_DQS_REC_EN_TRAINING == TRUE) - extern OPTION_MEM_FEATURE_NB MemNInitDqsTrainRcvrEnHwNb; - #undef MEM_TECH_FEATURE_HWRXEN - #define MEM_TECH_FEATURE_HWRXEN MemNInitDqsTrainRcvrEnHwNb - #else - extern OPTION_MEM_FEATURE_NB MemNDisableDqsTrainRcvrEnHwNb; - #undef MEM_TECH_FEATURE_HWRXEN - #define MEM_TECH_FEATURE_HWRXEN MemNDisableDqsTrainRcvrEnHwNb - #endif - - - #undef MEM_MAIN_FEATURE_TRAINING - #undef MEM_FEATURE_TRAINING -// extern OPTION_MEM_FEATURE_MAIN MemMStandardTraining; - #define MEM_MAIN_FEATURE_TRAINING MemMStandardTraining - extern OPTION_MEM_FEATURE_NB MemFStandardTraining; - #define MEM_FEATURE_TRAINING MemFStandardTraining - - MEM_FEAT_BLOCK_NB MemFeatBlockHy = { - MEM_FEAT_BLOCK_NB_STRUCT_VERSION, - MEM_FEATURE_ONLINE_SPARE, - MEM_FEATURE_BANK_INTERLEAVE, - MEM_FEATURE_UNDO_BANK_INTERLEAVE, - MEM_FEATURE_NODE_INTERLEAVE_CHECK, - MEM_FEATURE_NODE_INTERLEAVE, - MEM_FEATURE_CHANNEL_INTERLEAVE, - MemFDefRet, - MEM_FEATURE_CK_ECC, - MEM_FEATURE_ECC, - MEM_FEATURE_TRAINING, - MEM_FEATURE_LVDDR3, - MEM_FEATURE_ONDIMMTHERMAL, - MEM_TECH_FEATURE_DRAMINIT, - MEM_FEATURE_DIMM_EXCLUDE, - MemFDefRet, - MEM_TECH_FEATURE_CPG, - MEM_TECH_FEATURE_HWRXEN - }; - - #undef MEM_NB_SUPPORT_HY - extern MEM_NB_CONSTRUCTOR MemConstructNBBlockHY; - extern MEM_INITIALIZER MemNInitDefaultsHY; - #define MEM_NB_SUPPORT_HY { MEM_NB_SUPPORT_STRUCT_VERSION, MemConstructNBBlockHY, MemNInitDefaultsHY, &MemFeatBlockHy, MEM_FEATURE_S3_RESUME_CONSTRUCTOR_HY, MEM_IDENDIMM_HY }, - #endif // OPTION_MEMCTRL_HY - /*--------------------------------------------------------------------------------------------------- - * LLANO FEATURE BLOCK - *--------------------------------------------------------------------------------------------------- - */ - #if (OPTION_MEMCTLR_LN == TRUE) - #if OPTION_DDR2 - #undef MEM_TECH_FEATURE_DRAMINIT - #define MEM_TECH_FEATURE_DRAMINIT MEM_TECH_FEATURE_HW_DRAMINIT - #endif - #if OPTION_DDR3 - #undef MEM_TECH_FEATURE_DRAMINIT - #define MEM_TECH_FEATURE_DRAMINIT MEM_TECH_FEATURE_SW_DRAMINIT - #endif - - #if (OPTION_EARLY_SAMPLES == TRUE) - extern OPTION_MEM_FEATURE_NB MemNInitEarlySampleSupportLN; - #define MEM_EARLY_SAMPLE_SUPPORT MemNInitEarlySampleSupportLN - #else - #define MEM_EARLY_SAMPLE_SUPPORT MemFDefRet - #endif - - #if (OPTION_CONTINOUS_PATTERN_GENERATION == TRUE) - extern OPTION_MEM_FEATURE_NB MemNInitCPGClientNb; - #undef MEM_TECH_FEATURE_CPG - #define MEM_TECH_FEATURE_CPG MemNInitCPGClientNb - #else - #undef MEM_TECH_FEATURE_CPG - #define MEM_TECH_FEATURE_CPG MemFDefRet - #endif - - #if (OPTION_HW_DQS_REC_EN_TRAINING == TRUE) - extern OPTION_MEM_FEATURE_NB MemNInitDqsTrainRcvrEnHwNb; - #undef MEM_TECH_FEATURE_HWRXEN - #define MEM_TECH_FEATURE_HWRXEN MemNInitDqsTrainRcvrEnHwNb - #else - extern OPTION_MEM_FEATURE_NB MemNDisableDqsTrainRcvrEnHwNb; - #undef MEM_TECH_FEATURE_HWRXEN - #define MEM_TECH_FEATURE_HWRXEN MemNDisableDqsTrainRcvrEnHwNb - #endif - - #undef MEM_MAIN_FEATURE_TRAINING - #undef MEM_FEATURE_TRAINING -// extern OPTION_MEM_FEATURE_MAIN MemMStandardTraining; - #define MEM_MAIN_FEATURE_TRAINING MemMStandardTraining - extern OPTION_MEM_FEATURE_NB MemFStandardTraining; - #define MEM_FEATURE_TRAINING MemFStandardTraining - - MEM_FEAT_BLOCK_NB MemFeatBlockLn = { - MEM_FEAT_BLOCK_NB_STRUCT_VERSION, - MemFDefRet, - MEM_FEATURE_BANK_INTERLEAVE, - MEM_FEATURE_UNDO_BANK_INTERLEAVE, - MemFDefRet, - MemFDefRet, - MEM_FEATURE_CHANNEL_INTERLEAVE, - MEM_FEATURE_REGION_INTERLEAVE, - MEM_FEATURE_CK_ECC, - MemFDefRet, - MEM_FEATURE_TRAINING, - MEM_FEATURE_LVDDR3, - MEM_FEATURE_ONDIMMTHERMAL, - MEM_TECH_FEATURE_DRAMINIT, - MEM_FEATURE_DIMM_EXCLUDE, - MEM_EARLY_SAMPLE_SUPPORT, - MEM_TECH_FEATURE_CPG, - MEM_TECH_FEATURE_HWRXEN - }; - #undef MEM_NB_SUPPORT_LN - extern MEM_NB_CONSTRUCTOR MemConstructNBBlockLN; - extern MEM_INITIALIZER MemNInitDefaultsLN; - #define MEM_NB_SUPPORT_LN { MEM_NB_SUPPORT_STRUCT_VERSION, MemConstructNBBlockLN, MemNInitDefaultsLN, &MemFeatBlockLn, MEM_FEATURE_S3_RESUME_CONSTRUCTOR_LN, MEM_IDENDIMM_LN }, - - #endif // OPTION_MEMCTRL_LN - - /*--------------------------------------------------------------------------------------------------- - * ONTARIO FEATURE BLOCK - *--------------------------------------------------------------------------------------------------- - */ - #if (OPTION_MEMCTLR_ON == TRUE) - #if OPTION_DDR2 - #undef MEM_TECH_FEATURE_DRAMINIT - #define MEM_TECH_FEATURE_DRAMINIT MEM_TECH_FEATURE_HW_DRAMINIT - #endif - #if OPTION_DDR3 - #undef MEM_TECH_FEATURE_DRAMINIT - #define MEM_TECH_FEATURE_DRAMINIT MEM_TECH_FEATURE_SW_DRAMINIT - #endif - - #if (OPTION_CONTINOUS_PATTERN_GENERATION == TRUE) - extern OPTION_MEM_FEATURE_NB MemNInitCPGClientNb; - #undef MEM_TECH_FEATURE_CPG - #define MEM_TECH_FEATURE_CPG MemNInitCPGClientNb - #else - #undef MEM_TECH_FEATURE_CPG - #define MEM_TECH_FEATURE_CPG MemFDefRet - #endif - - #if (OPTION_HW_DQS_REC_EN_TRAINING == TRUE) - extern OPTION_MEM_FEATURE_NB MemNInitDqsTrainRcvrEnHwNb; - #undef MEM_TECH_FEATURE_HWRXEN - #define MEM_TECH_FEATURE_HWRXEN MemNInitDqsTrainRcvrEnHwNb - #else - extern OPTION_MEM_FEATURE_NB MemNDisableDqsTrainRcvrEnHwNb; - #undef MEM_TECH_FEATURE_HWRXEN - #define MEM_TECH_FEATURE_HWRXEN MemNDisableDqsTrainRcvrEnHwNb - #endif - - #undef MEM_MAIN_FEATURE_TRAINING - #undef MEM_FEATURE_TRAINING - #define MEM_MAIN_FEATURE_TRAINING MemMStandardTraining - extern OPTION_MEM_FEATURE_NB MemFStandardTraining; - #define MEM_FEATURE_TRAINING MemFStandardTraining - - #if (OPTION_EARLY_SAMPLES == TRUE) - extern OPTION_MEM_FEATURE_NB MemNInitEarlySampleSupportON; - #define MEM_EARLY_SAMPLE_SUPPORT MemNInitEarlySampleSupportON - #else - #define MEM_EARLY_SAMPLE_SUPPORT MemFDefRet - #endif - - MEM_FEAT_BLOCK_NB MemFeatBlockOn = { - MEM_FEAT_BLOCK_NB_STRUCT_VERSION, - MemFDefRet, - MEM_FEATURE_BANK_INTERLEAVE, - MEM_FEATURE_UNDO_BANK_INTERLEAVE, - MemFDefRet, - MemFDefRet, - MemFDefRet, - MemFDefRet, - MemFDefRet, - MemFDefRet, - MEM_FEATURE_TRAINING, - MEM_FEATURE_LVDDR3, - MEM_FEATURE_ONDIMMTHERMAL, - MEM_TECH_FEATURE_DRAMINIT, - MEM_FEATURE_DIMM_EXCLUDE, - MEM_EARLY_SAMPLE_SUPPORT, - MEM_TECH_FEATURE_CPG, - MEM_TECH_FEATURE_HWRXEN - }; - - #undef MEM_NB_SUPPORT_ON - extern MEM_NB_CONSTRUCTOR MemConstructNBBlockON; - extern MEM_INITIALIZER MemNInitDefaultsON; - #define MEM_NB_SUPPORT_ON { MEM_NB_SUPPORT_STRUCT_VERSION, MemConstructNBBlockON, MemNInitDefaultsON, &MemFeatBlockOn, MEM_FEATURE_S3_RESUME_CONSTRUCTOR_ON, MEM_IDENDIMM_ON }, - - #endif // OPTION_MEMCTRL_ON - - /*--------------------------------------------------------------------------------------------------- - * OROCHI FEATURE BLOCK - *--------------------------------------------------------------------------------------------------- - */ - #if (OPTION_MEMCTLR_OR == TRUE) - #if OPTION_DDR2 - #undef MEM_TECH_FEATURE_DRAMINIT - #define MEM_TECH_FEATURE_DRAMINIT MEM_TECH_FEATURE_HW_DRAMINIT - #endif - #if OPTION_DDR3 - #undef MEM_MAIN_FEATURE_LVDDR3 - extern OPTION_MEM_FEATURE_MAIN MemMLvDdr3PerformanceEnhPre; - #define MEM_MAIN_FEATURE_LVDDR3 MemMLvDdr3PerformanceEnhPre - #undef MEM_TECH_FEATURE_DRAMINIT - #define MEM_TECH_FEATURE_DRAMINIT MEM_TECH_FEATURE_SW_DRAMINIT - #endif - - #if (OPTION_G34_SOCKET_SUPPORT || OPTION_C32_SOCKET_SUPPORT) - #undef MEM_FEATURE_REGION_INTERLEAVE - #define MEM_FEATURE_REGION_INTERLEAVE MemFDefRet - #endif - - #if (OPTION_EARLY_SAMPLES == TRUE) - extern OPTION_MEM_FEATURE_NB MemNInitEarlySampleSupportOr; - #define MEM_EARLY_SAMPLE_SUPPORT MemNInitEarlySampleSupportOr - #else - #define MEM_EARLY_SAMPLE_SUPPORT MemFDefRet - #endif - - #if (OPTION_CONTINOUS_PATTERN_GENERATION == TRUE) - extern OPTION_MEM_FEATURE_NB MemNInitCPGUnb; - #undef MEM_TECH_FEATURE_CPG - #define MEM_TECH_FEATURE_CPG MemNInitCPGUnb - #else - #undef MEM_TECH_FEATURE_CPG - #define MEM_TECH_FEATURE_CPG MemFDefRet - #endif - - #if (OPTION_HW_DQS_REC_EN_TRAINING == TRUE) - extern OPTION_MEM_FEATURE_NB MemNInitDqsTrainRcvrEnHwNb; - #undef MEM_TECH_FEATURE_HWRXEN - #define MEM_TECH_FEATURE_HWRXEN MemNInitDqsTrainRcvrEnHwNb - #else - extern OPTION_MEM_FEATURE_NB MemNDisableDqsTrainRcvrEnHwNb; - #undef MEM_TECH_FEATURE_HWRXEN - #define MEM_TECH_FEATURE_HWRXEN MemNDisableDqsTrainRcvrEnHwNb - #endif - - - #undef MEM_MAIN_FEATURE_TRAINING - #undef MEM_FEATURE_TRAINING -// extern OPTION_MEM_FEATURE_MAIN MemMStandardTraining; - #define MEM_MAIN_FEATURE_TRAINING MemMStandardTraining - extern OPTION_MEM_FEATURE_NB MemFStandardTraining; - #define MEM_FEATURE_TRAINING MemFStandardTraining - - MEM_FEAT_BLOCK_NB MemFeatBlockOr = { - MEM_FEAT_BLOCK_NB_STRUCT_VERSION, - MEM_FEATURE_ONLINE_SPARE, - MEM_FEATURE_BANK_INTERLEAVE, - MEM_FEATURE_UNDO_BANK_INTERLEAVE, - MEM_FEATURE_NODE_INTERLEAVE_CHECK, - MEM_FEATURE_NODE_INTERLEAVE, - MEM_FEATURE_CHANNEL_INTERLEAVE, - MEM_FEATURE_REGION_INTERLEAVE, - MEM_FEATURE_CK_ECC, - MEM_FEATURE_ECC, - MEM_FEATURE_TRAINING, - MEM_FEATURE_LVDDR3, - MEM_FEATURE_ONDIMMTHERMAL, - MEM_TECH_FEATURE_DRAMINIT, - MEM_FEATURE_DIMM_EXCLUDE, - MEM_EARLY_SAMPLE_SUPPORT, - MEM_TECH_FEATURE_CPG, - MEM_TECH_FEATURE_HWRXEN - }; - - #undef MEM_NB_SUPPORT_OR - extern MEM_NB_CONSTRUCTOR MemConstructNBBlockOR; - extern MEM_INITIALIZER MemNInitDefaultsOR; - #define MEM_NB_SUPPORT_OR { MEM_NB_SUPPORT_STRUCT_VERSION, MemConstructNBBlockOR, MemNInitDefaultsOR, &MemFeatBlockOr, MEM_FEATURE_S3_RESUME_CONSTRUCTOR_OR, MEM_IDENDIMM_OR }, - #endif // OPTION_MEMCTRL_OR - - /*--------------------------------------------------------------------------------------------------- - * C32 FEATURE BLOCK - *--------------------------------------------------------------------------------------------------- - */ - #if (OPTION_MEMCTLR_C32 == TRUE) - #if OPTION_DDR2 - #undef MEM_TECH_FEATURE_DRAMINIT - #define MEM_TECH_FEATURE_DRAMINIT MEM_TECH_FEATURE_HW_DRAMINIT - #endif - #if OPTION_DDR3 - #undef MEM_TECH_FEATURE_DRAMINIT - #define MEM_TECH_FEATURE_DRAMINIT MEM_TECH_FEATURE_SW_DRAMINIT - #endif - - #undef MEM_TECH_FEATURE_CPG - #define MEM_TECH_FEATURE_CPG MemFDefRet - - #if (OPTION_HW_DQS_REC_EN_TRAINING == TRUE) - extern OPTION_MEM_FEATURE_NB MemNInitDqsTrainRcvrEnHwNb; - #undef MEM_TECH_FEATURE_HWRXEN - #define MEM_TECH_FEATURE_HWRXEN MemNInitDqsTrainRcvrEnHwNb - #else - extern OPTION_MEM_FEATURE_NB MemNDisableDqsTrainRcvrEnHwNb; - #define MEM_TECH_FEATURE_HWRXEN MemNDisableDqsTrainRcvrEnHwNb - #endif - - #undef MEM_MAIN_FEATURE_TRAINING - #undef MEM_FEATURE_TRAINING -// extern OPTION_MEM_FEATURE_MAIN MemMStandardTraining; - #define MEM_MAIN_FEATURE_TRAINING MemMStandardTraining - extern OPTION_MEM_FEATURE_NB MemFStandardTraining; - #define MEM_FEATURE_TRAINING MemFStandardTraining - - MEM_FEAT_BLOCK_NB MemFeatBlockC32 = { - MEM_FEAT_BLOCK_NB_STRUCT_VERSION, - MEM_FEATURE_ONLINE_SPARE, - MEM_FEATURE_BANK_INTERLEAVE, - MEM_FEATURE_UNDO_BANK_INTERLEAVE, - MEM_FEATURE_NODE_INTERLEAVE_CHECK, - MEM_FEATURE_NODE_INTERLEAVE, - MEM_FEATURE_CHANNEL_INTERLEAVE, - MemFDefRet, - MEM_FEATURE_CK_ECC, - MEM_FEATURE_ECC, - MEM_FEATURE_TRAINING, - MEM_FEATURE_LVDDR3, - MEM_FEATURE_ONDIMMTHERMAL, - MEM_TECH_FEATURE_DRAMINIT, - MEM_FEATURE_DIMM_EXCLUDE, - MemFDefRet, - MEM_TECH_FEATURE_CPG, - MEM_TECH_FEATURE_HWRXEN - }; - - #undef MEM_NB_SUPPORT_C32 - extern MEM_NB_CONSTRUCTOR MemConstructNBBlockC32; - extern MEM_INITIALIZER MemNInitDefaultsC32; - #define MEM_NB_SUPPORT_C32 { MEM_NB_SUPPORT_STRUCT_VERSION, MemConstructNBBlockC32, MemNInitDefaultsC32, &MemFeatBlockC32, MEM_FEATURE_S3_RESUME_CONSTRUCTOR_C32, MEM_IDENDIMM_C32 }, - #endif // OPTION_MEMCTRL_C32 - - /*--------------------------------------------------------------------------------------------------- - * MAIN FEATURE BLOCK - *--------------------------------------------------------------------------------------------------- - */ - MEM_FEAT_BLOCK_MAIN MemFeatMain = { - MEM_FEAT_BLOCK_MAIN_STRUCT_VERSION, - MEM_MAIN_FEATURE_TRAINING, - MEM_MAIN_FEATURE_DIMM_EXCLUDE, - MEM_MAIN_FEATURE_ONLINE_SPARE, - MEM_MAIN_FEATURE_NODE_INTERLEAVE, - MEM_MAIN_FEATURE_ECC, - MEM_MAIN_FEATURE_MEM_CLEAR, - MEM_MAIN_FEATURE_MEM_DMI, - MEM_MAIN_FEATURE_LVDDR3, - MEM_MAIN_FEATURE_UMAALLOC, - MEM_MAIN_FEATURE_MEM_SAVE, - MEM_MAIN_FEATURE_MEM_RESTORE - }; - - - /*--------------------------------------------------------------------------------------------------- - * Technology Training SPECIFIC CONFIGURATION - * - * - *--------------------------------------------------------------------------------------------------- - */ - #define MEM_TECH_TRAINING_FEAT_NULL_TERNMIATOR 0 - #if OPTION_MEMCTLR_DR - extern OPTION_MEM_FEATURE_NB memNEnableTrainSequenceDr; - #if OPTION_DDR2 - #define TECH_TRAIN_ENTER_HW_TRN_DDR2 MemTFeatDef - #define TECH_TRAIN_EXIT_HW_TRN_DDR2 MemTFeatDef - #define TECH_TRAIN_HW_WL_P1_DDR2 MemTFeatDef - #define TECH_TRAIN_HW_WL_P2_DDR2 MemTFeatDef - #define TECH_TRAIN_SW_WL_DDR2 MemTFeatDef - #if (OPTION_HW_DQS_REC_EN_TRAINING == TRUE) - #define TECH_TRAIN_HW_DQS_REC_EN_P1_DDR2 MemTDqsTrainRcvrEnHwPass1 - #define TECH_TRAIN_HW_DQS_REC_EN_P2_DDR2 MemTDqsTrainRcvrEnHwPass2 - #define TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR2 MemTTrainDQSEdgeDetect - #else - #define TECH_TRAIN_HW_DQS_REC_EN_P1_DDR2 MemTFeatDef - #define TECH_TRAIN_HW_DQS_REC_EN_P2_DDR2 MemTFeatDef - #if (OPTION_NON_OPT_SW_RD_WR_POS_TRAINING == TRUE) - #define TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR2 MemTTrainDQSEdgeDetect - #else - #define TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR2 MemTFeatDef - #endif - #endif - #if (OPTION_NON_OPT_SW_DQS_REC_EN_TRAINING == TRUE) - #define TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR2 MemTTrainRcvrEnSwPass1 - #else - #define TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR2 MemTFeatDef - #endif - #if (OPTION_OPT_SW_DQS_REC_EN_TRAINING == TRUE) - #define TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR2 MemTFeatDef - #else - #define TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR2 MemTFeatDef - #endif - #if (OPTION_NON_OPT_SW_RD_WR_POS_TRAINING == TRUE) - #define TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR2 MemTTrainDQSEdgeDetectSw - #else - #define TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR2 MemTFeatDef - #endif - #if (OPTION_OPT_SW_RD_WR_POS_TRAINING == TRUE) - #define TECH_TRAIN_OPT_SW_RD_WR_POS_DDR2 MemTFeatDef - #else - #define TECH_TRAIN_OPT_SW_RD_WR_POS_DDR2 MemTFeatDef - #endif - #if (OPTION_MAX_RD_LAT_TRAINING == TRUE) - #define TECH_TRAIN_MAX_RD_LAT_DDR2 MemTTrainMaxLatency - #else - #define TECH_TRAIN_MAX_RD_LAT_DDR2 MemTFeatDef - #endif - MEM_TECH_FEAT_BLOCK memTechTrainingFeatSequenceDDR2Dr = { - MEM_TECH_FEAT_BLOCK_STRUCT_VERSION, - TECH_TRAIN_ENTER_HW_TRN_DDR2, - TECH_TRAIN_SW_WL_DDR2, - TECH_TRAIN_HW_WL_P1_DDR2, - TECH_TRAIN_HW_DQS_REC_EN_P1_DDR2, - TECH_TRAIN_HW_WL_P2_DDR2, - TECH_TRAIN_HW_DQS_REC_EN_P2_DDR2, - TECH_TRAIN_EXIT_HW_TRN_DDR2, - TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR2, - TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR2, - TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR2, - TECH_TRAIN_OPT_SW_RD_WR_POS_DDR2, - TECH_TRAIN_MAX_RD_LAT_DDR2, - TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR2 - }; - extern OPTION_MEM_FEATURE_NB MemNDQSTiming2Nb; - #define NB_TRAIN_FLOW_DDR2 MemNDQSTiming2Nb - extern OPTION_MEM_FEATURE_NB memNSequenceDDR2ServerNb; - #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR2_DR { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, memNSequenceDDR2ServerNb, memNEnableTrainSequenceDr, &memTechTrainingFeatSequenceDDR2Dr }, - #else - #define TECH_TRAIN_ENTER_HW_TRN_DDR2 MemTFeatDef - #define TECH_TRAIN_EXIT_HW_TRN_DDR2 MemTFeatDef - #define TECH_TRAIN_HW_WL_P1_DDR2 MemTFeatDef - #define TECH_TRAIN_HW_WL_P2_DDR2 MemTFeatDef - #define TECH_TRAIN_SW_WL_DDR2 MemTFeatDef - #define TECH_TRAIN_HW_DQS_REC_EN_P1_DDR2 MemTFeatDef - #define TECH_TRAIN_HW_DQS_REC_EN_P2_DDR2 MemTFeatDef - #define TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR2 MemTFeatDef - #define TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR2 MemTFeatDef - #define TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR2 MemTFeatDef - #define TECH_TRAIN_OPT_SW_RD_WR_POS_DDR2 MemTFeatDef - #define TECH_TRAIN_MAX_RD_LAT_DDR2 MemTFeatDef - #define NB_TRAIN_FLOW_DDR2 (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue - #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR2_DR { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 }, - #endif - #if OPTION_DDR3 - #undef TECH_TRAIN_ENTER_HW_TRN_DDR3 - #define TECH_TRAIN_ENTER_HW_TRN_DDR3 MemTPreparePhyAssistedTraining - #undef TECH_TRAIN_EXIT_HW_TRN_DDR3 - #define TECH_TRAIN_EXIT_HW_TRN_DDR3 MemTExitPhyAssistedTraining - #if (OPTION_HW_WRITE_LEV_TRAINING == TRUE) - #define TECH_TRAIN_HW_WL_P1_DDR3 MemTWriteLevelizationHw3Pass1 - #define TECH_TRAIN_HW_WL_P2_DDR3 MemTWriteLevelizationHw3Pass2 - #else - #define TECH_TRAIN_HW_WL_P1_DDR3 MemTFeatDef - #define TECH_TRAIN_HW_WL_P2_DDR3 MemTFeatDef - #endif - #if (OPTION_SW_WRITE_LEV_TRAINING == TRUE) - #define TECH_TRAIN_SW_WL_DDR3 MemTFeatDef - #else - #define TECH_TRAIN_SW_WL_DDR3 MemTFeatDef - #endif - #if (OPTION_HW_DQS_REC_EN_TRAINING == TRUE) - #define TECH_TRAIN_HW_DQS_REC_EN_P1_DDR3 MemTDqsTrainRcvrEnHwPass1 - #define TECH_TRAIN_HW_DQS_REC_EN_P2_DDR3 MemTDqsTrainRcvrEnHwPass2 - #if (OPTION_HW_DQS_REC_EN_SEED_TRAINING == TRUE) - #undef TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR3 - #define TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR3 MemTRdPosWithRxEnDlySeeds3 - #else - #if (OPTION_OPT_SW_RD_WR_POS_TRAINING == TRUE || OPTION_NON_OPT_SW_RD_WR_POS_TRAINING == TRUE) - #define TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR3 MemTTrainDQSEdgeDetect - #else - #define TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR3 MemTFeatDef - #endif - #endif - #else - #define TECH_TRAIN_HW_DQS_REC_EN_P1_DDR3 MemTFeatDef - #define TECH_TRAIN_HW_DQS_REC_EN_P2_DDR3 MemTFeatDef - #if (OPTION_OPT_SW_RD_WR_POS_TRAINING == TRUE || OPTION_NON_OPT_SW_RD_WR_POS_TRAINING == TRUE) - #define TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR3 MemTTrainDQSEdgeDetect - #else - #define TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR3 MemTFeatDef - #endif - #endif - #if (OPTION_NON_OPT_SW_DQS_REC_EN_TRAINING == TRUE) - #define TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR3 MemTTrainRcvrEnSwPass1 - #else - #define TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR3 MemTFeatDef - #endif - #if (OPTION_OPT_SW_DQS_REC_EN_TRAINING == TRUE) - #define TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR3 MemTTrainOptRcvrEnSwPass1 - #else - #define TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR3 MemTFeatDef - #endif - #if (OPTION_NON_OPT_SW_RD_WR_POS_TRAINING == TRUE) - #define TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR3 MemTTrainDQSEdgeDetectSw - #else - #define TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR3 MemTFeatDef - #endif - #if (OPTION_OPT_SW_RD_WR_POS_TRAINING == TRUE) - #define TECH_TRAIN_OPT_SW_RD_WR_POS_DDR3 MemTTrainDQSEdgeDetectSw - #else - #define TECH_TRAIN_OPT_SW_RD_WR_POS_DDR3 MemTFeatDef - #endif - #if (OPTION_MAX_RD_LAT_TRAINING == TRUE) - #define TECH_TRAIN_MAX_RD_LAT_DDR3 MemTTrainMaxLatency - #else - #define TECH_TRAIN_MAX_RD_LAT_DDR3 MemTFeatDef - #endif -// extern OPTION_MEM_FEATURE_NB MemNDQSTiming3Nb; - #define NB_TRAIN_FLOW_DDR3 MemNDQSTiming3Nb -// extern OPTION_MEM_FEATURE_NB memNSequenceDDR3Nb; - extern OPTION_MEM_FEATURE_NB memNEnableTrainSequenceDr; - MEM_TECH_FEAT_BLOCK memTechTrainingFeatSequenceDDR3Dr = { - MEM_TECH_FEAT_BLOCK_STRUCT_VERSION, - TECH_TRAIN_ENTER_HW_TRN_DDR3, - TECH_TRAIN_SW_WL_DDR3, - TECH_TRAIN_HW_WL_P1_DDR3, - TECH_TRAIN_HW_DQS_REC_EN_P1_DDR3, - TECH_TRAIN_HW_WL_P2_DDR3, - TECH_TRAIN_HW_DQS_REC_EN_P2_DDR3, - TECH_TRAIN_EXIT_HW_TRN_DDR3, - TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR3, - TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR3, - TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR3, - TECH_TRAIN_OPT_SW_RD_WR_POS_DDR3, - TECH_TRAIN_MAX_RD_LAT_DDR3, - TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR3 - }; - #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR3_DR { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, memNSequenceDDR3Nb, memNEnableTrainSequenceDr, &memTechTrainingFeatSequenceDDR3Dr }, - #else - #undef TECH_TRAIN_ENTER_HW_TRN_DDR3 - #define TECH_TRAIN_ENTER_HW_TRN_DDR3 MemTFeatDef - #undef TECH_TRAIN_EXIT_HW_TRN_DDR3 - #define TECH_TRAIN_EXIT_HW_TRN_DDR3 MemTFeatDef - #define TECH_TRAIN_HW_WL_P1_DDR3 MemTFeatDef - #define TECH_TRAIN_HW_WL_P2_DDR3 MemTFeatDef - #define TECH_TRAIN_SW_WL_DDR3 MemTFeatDef - #define TECH_TRAIN_HW_DQS_REC_EN_P1_DDR3 MemTFeatDef - #define TECH_TRAIN_HW_DQS_REC_EN_P2_DDR3 MemTFeatDef - #define TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR3 MemTFeatDef - #define TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR3 MemTFeatDef - #define TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR3 MemTFeatDef - #define TECH_TRAIN_OPT_SW_RD_WR_POS_DDR3 MemTFeatDef - #define TECH_TRAIN_MAX_RD_LAT_DDR3 MemTFeatDef - #define NB_TRAIN_FLOW_DDR3 (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue - #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR3_DR { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 }, - #endif - #else - #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR2_DR { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 }, - #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR3_DR { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 }, - #endif - - #if (OPTION_MEMCTLR_DA || OPTION_MEMCTLR_Ni || OPTION_MEMCTLR_PH || OPTION_MEMCTLR_RB) - #if OPTION_DDR2 - #define TECH_TRAIN_ENTER_HW_TRN_DDR2 MemTFeatDef - #define TECH_TRAIN_EXIT_HW_TRN_DDR2 MemTFeatDef - #define TECH_TRAIN_HW_WL_P1_DDR2 MemTFeatDef - #define TECH_TRAIN_HW_WL_P2_DDR2 MemTFeatDef - #define TECH_TRAIN_SW_WL_DDR2 MemTFeatDef - #if (OPTION_HW_DQS_REC_EN_TRAINING == TRUE) - #define TECH_TRAIN_HW_DQS_REC_EN_P1_DDR2 MemTDqsTrainRcvrEnHwPass1 - #define TECH_TRAIN_HW_DQS_REC_EN_P2_DDR2 MemTDqsTrainRcvrEnHwPass2 - #define TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR2 MemTTrainDQSEdgeDetect - #else - #define TECH_TRAIN_HW_DQS_REC_EN_P1_DDR2 MemTFeatDef - #define TECH_TRAIN_HW_DQS_REC_EN_P2_DDR2 MemTFeatDef - #if (OPTION_NON_OPT_SW_RD_WR_POS_TRAINING == TRUE) - #define TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR2 MemTTrainDQSEdgeDetect - #else - #define TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR2 MemTFeatDef - #endif - #endif - #if (OPTION_NON_OPT_SW_DQS_REC_EN_TRAINING == TRUE) - #define TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR2 MemTTrainRcvrEnSwPass1 - #else - #define TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR2 MemTFeatDef - #endif - #if (OPTION_OPT_SW_DQS_REC_EN_TRAINING == TRUE) - #define TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR2 MemTFeatDef - #else - #define TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR2 MemTFeatDef - #endif - #if (OPTION_NON_OPT_SW_RD_WR_POS_TRAINING == TRUE) - #define TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR2 MemTTrainDQSEdgeDetectSw - #else - #define TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR2 MemTFeatDef - #endif - #if (OPTION_OPT_SW_RD_WR_POS_TRAINING == TRUE) - #define TECH_TRAIN_OPT_SW_RD_WR_POS_DDR2 MemTFeatDef - #else - #define TECH_TRAIN_OPT_SW_RD_WR_POS_DDR2 MemTFeatDef - #endif - #if (OPTION_MAX_RD_LAT_TRAINING == TRUE) - #define TECH_TRAIN_MAX_RD_LAT_DDR2 MemTTrainMaxLatency - #else - #define TECH_TRAIN_MAX_RD_LAT_DDR2 MemTFeatDef - #endif - MEM_TECH_FEAT_BLOCK memTechTrainingFeatSequenceDDR2DA = { - MEM_TECH_FEAT_BLOCK_STRUCT_VERSION, - TECH_TRAIN_ENTER_HW_TRN_DDR2, - TECH_TRAIN_SW_WL_DDR2, - TECH_TRAIN_HW_WL_P1_DDR2, - TECH_TRAIN_HW_DQS_REC_EN_P1_DDR2, - TECH_TRAIN_HW_WL_P2_DDR2, - TECH_TRAIN_HW_DQS_REC_EN_P2_DDR2, - TECH_TRAIN_EXIT_HW_TRN_DDR2, - TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR2, - TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR2, - TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR2, - TECH_TRAIN_OPT_SW_RD_WR_POS_DDR2, - TECH_TRAIN_MAX_RD_LAT_DDR2, - TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR2 - }; - MEM_TECH_FEAT_BLOCK memTechTrainingFeatSequenceDDR2PH = { - MEM_TECH_FEAT_BLOCK_STRUCT_VERSION, - TECH_TRAIN_ENTER_HW_TRN_DDR2, - TECH_TRAIN_SW_WL_DDR2, - TECH_TRAIN_HW_WL_P1_DDR2, - TECH_TRAIN_HW_DQS_REC_EN_P1_DDR2, - TECH_TRAIN_HW_WL_P2_DDR2, - TECH_TRAIN_HW_DQS_REC_EN_P2_DDR2, - TECH_TRAIN_EXIT_HW_TRN_DDR2, - TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR2, - TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR2, - TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR2, - TECH_TRAIN_OPT_SW_RD_WR_POS_DDR2, - TECH_TRAIN_MAX_RD_LAT_DDR2, - TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR2 - }; - MEM_TECH_FEAT_BLOCK memTechTrainingFeatSequenceDDR2Rb = { - MEM_TECH_FEAT_BLOCK_STRUCT_VERSION, - TECH_TRAIN_ENTER_HW_TRN_DDR2, - TECH_TRAIN_SW_WL_DDR2, - TECH_TRAIN_HW_WL_P1_DDR2, - TECH_TRAIN_HW_DQS_REC_EN_P1_DDR2, - TECH_TRAIN_HW_WL_P2_DDR2, - TECH_TRAIN_HW_DQS_REC_EN_P2_DDR2, - TECH_TRAIN_EXIT_HW_TRN_DDR2, - TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR2, - TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR2, - TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR2, - TECH_TRAIN_OPT_SW_RD_WR_POS_DDR2, - TECH_TRAIN_MAX_RD_LAT_DDR2, - TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR2 - }; - MEM_TECH_FEAT_BLOCK memTechTrainingFeatSequenceDDR2Ni = { - MEM_TECH_FEAT_BLOCK_STRUCT_VERSION, - TECH_TRAIN_ENTER_HW_TRN_DDR2, - TECH_TRAIN_SW_WL_DDR2, - TECH_TRAIN_HW_WL_P1_DDR2, - TECH_TRAIN_HW_DQS_REC_EN_P1_DDR2, - TECH_TRAIN_HW_WL_P2_DDR2, - TECH_TRAIN_HW_DQS_REC_EN_P2_DDR2, - TECH_TRAIN_EXIT_HW_TRN_DDR2, - TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR2, - TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR2, - TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR2, - TECH_TRAIN_OPT_SW_RD_WR_POS_DDR2, - TECH_TRAIN_MAX_RD_LAT_DDR2, - TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR2 - }; - extern OPTION_MEM_FEATURE_NB MemNDQSTiming2Nb; - #define NB_TRAIN_FLOW_DDR2 MemNDQSTiming2Nb - extern OPTION_MEM_FEATURE_NB memNSequenceDDR2ServerNb; - #if (OPTION_MEMCTLR_DA) - extern OPTION_MEM_FEATURE_NB memNEnableTrainSequenceDA - #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR2_DA { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, memNSequenceDDR2ServerNb, memNEnableTrainSequenceDA, &memTechTrainingFeatSequenceDDR2DA }, - #else - #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR2_DA { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 }, - #endif - #if (OPTION_MEMCTLR_PH) - extern OPTION_MEM_FEATURE_NB memNEnableTrainSequencePh - #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR2_PH { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, memNSequenceDDR2ServerNb, memNEnableTrainSequencePh, &memTechTrainingFeatSequenceDDR2PH }, - #else - #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR2_PH { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 }, - #endif - #if (OPTION_MEMCTLR_RB) - extern OPTION_MEM_FEATURE_NB memNEnableTrainSequenceRb - #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR2_RB { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, memNSequenceDDR2ServerNb, memNEnableTrainSequenceRb, &memTechTrainingFeatSequenceDDR2Rb }, - #else - #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR2_RB { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 }, - #endif - - #if (OPTION_MEMCTLR_Ni) - extern OPTION_MEM_FEATURE_NB memNEnableTrainSequenceNi - #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR2_Ni { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION,memNSequenceDDR2ServerNb, memNEnableTrainSequenceNi, &memTechTrainingFeatSequenceDDR2Ni }, - #else - #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR2_DA { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 }, - #endif - #else - #define TECH_TRAIN_ENTER_HW_TRN_DDR2 MemTFeatDef - #define TECH_TRAIN_EXIT_HW_TRN_DDR2 MemTFeatDef - #define TECH_TRAIN_HW_WL_P1_DDR2 MemTFeatDef - #define TECH_TRAIN_HW_WL_P2_DDR2 MemTFeatDef - #define TECH_TRAIN_SW_WL_DDR2 MemTFeatDef - #define TECH_TRAIN_HW_DQS_REC_EN_P1_DDR2 MemTFeatDef - #define TECH_TRAIN_HW_DQS_REC_EN_P2_DDR2 MemTFeatDef - #define TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR2 MemTFeatDef - #define TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR2 MemTFeatDef - #define TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR2 MemTFeatDef - #define TECH_TRAIN_OPT_SW_RD_WR_POS_DDR2 MemTFeatDef - #define TECH_TRAIN_MAX_RD_LAT_DDR2 MemTFeatDef - #define NB_TRAIN_FLOW_DDR2 (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue - #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR2_DA { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 }, - #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR2_Ni { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 }, - #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR2_PH { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 }, - #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR2_RB { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 }, - #endif - #if OPTION_DDR3 - #undef TECH_TRAIN_ENTER_HW_TRN_DDR3 - #define TECH_TRAIN_ENTER_HW_TRN_DDR3 MemTPreparePhyAssistedTraining - #undef TECH_TRAIN_EXIT_HW_TRN_DDR3 - #define TECH_TRAIN_EXIT_HW_TRN_DDR3 MemTExitPhyAssistedTraining - #if (OPTION_HW_WRITE_LEV_TRAINING == TRUE) - #define TECH_TRAIN_HW_WL_P1_DDR3 MemTWriteLevelizationHw3Pass1 - #define TECH_TRAIN_HW_WL_P2_DDR3 MemTWriteLevelizationHw3Pass2 - #else - #define TECH_TRAIN_HW_WL_P1_DDR3 MemTFeatDef - #define TECH_TRAIN_HW_WL_P2_DDR3 MemTFeatDef - #endif - #if (OPTION_SW_WRITE_LEV_TRAINING == TRUE) - #define TECH_TRAIN_SW_WL_DDR3 MemTFeatDef - #else - #define TECH_TRAIN_SW_WL_DDR3 MemTFeatDef - #endif - #if (OPTION_HW_DQS_REC_EN_TRAINING == TRUE) - #ifdef TECH_TRAIN_HW_DQS_REC_EN_P1_DDR3 - #undef TECH_TRAIN_HW_DQS_REC_EN_P1_DDR3 - #endif - #define TECH_TRAIN_HW_DQS_REC_EN_P1_DDR3 MemTFeatDef - #ifdef TECH_TRAIN_HW_DQS_REC_EN_P2_DDR3 - #undef TECH_TRAIN_HW_DQS_REC_EN_P2_DDR3 - #endif - #define TECH_TRAIN_HW_DQS_REC_EN_P2_DDR3 MemTFeatDef - #if (OPTION_HW_DQS_REC_EN_SEED_TRAINING == TRUE) - #undef TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR3 - #define TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR3 MemTTrainDQSEdgeDetect - #else - #if (OPTION_OPT_SW_RD_WR_POS_TRAINING == TRUE || OPTION_NON_OPT_SW_RD_WR_POS_TRAINING == TRUE) - #define TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR3 MemTTrainDQSEdgeDetect - #else - #define TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR3 MemTFeatDef - #endif - #endif - #else - #define TECH_TRAIN_HW_DQS_REC_EN_P1_DDR3 MemTFeatDef - #define TECH_TRAIN_HW_DQS_REC_EN_P2_DDR3 MemTFeatDef - #if (OPTION_OPT_SW_RD_WR_POS_TRAINING == TRUE || OPTION_NON_OPT_SW_RD_WR_POS_TRAINING == TRUE) - #undef TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR3 - #define TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR3 MemTTrainDQSEdgeDetect - #else - #define TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR3 MemTFeatDef - #endif - #endif - #if (OPTION_NON_OPT_SW_DQS_REC_EN_TRAINING == TRUE) - #define TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR3 MemTTrainRcvrEnSwPass1 - #else - #define TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR3 MemTFeatDef - #endif - #if (OPTION_OPT_SW_DQS_REC_EN_TRAINING == TRUE) - #define TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR3 MemTTrainOptRcvrEnSwPass1 - #else - #define TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR3 MemTFeatDef - #endif - #if (OPTION_NON_OPT_SW_RD_WR_POS_TRAINING == TRUE) - #define TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR3 MemTTrainDQSEdgeDetectSw - #else - #define TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR3 MemTFeatDef - #endif - #if (OPTION_OPT_SW_RD_WR_POS_TRAINING == TRUE) - #define TECH_TRAIN_OPT_SW_RD_WR_POS_DDR3 MemTTrainDQSEdgeDetectSw - #else - #define TECH_TRAIN_OPT_SW_RD_WR_POS_DDR3 MemTFeatDef - #endif - #if (OPTION_MAX_RD_LAT_TRAINING == TRUE) - #define TECH_TRAIN_MAX_RD_LAT_DDR3 MemTTrainMaxLatency - #else - #define TECH_TRAIN_MAX_RD_LAT_DDR3 MemTFeatDef - #endif - MEM_TECH_FEAT_BLOCK memTechTrainingFeatSequenceDDR3DA = { - MEM_TECH_FEAT_BLOCK_STRUCT_VERSION, - TECH_TRAIN_ENTER_HW_TRN_DDR3, - TECH_TRAIN_SW_WL_DDR3, - TECH_TRAIN_HW_WL_P1_DDR3, - TECH_TRAIN_HW_DQS_REC_EN_P1_DDR3, - TECH_TRAIN_HW_WL_P2_DDR3, - TECH_TRAIN_HW_DQS_REC_EN_P2_DDR3, - TECH_TRAIN_EXIT_HW_TRN_DDR3, - TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR3, - TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR3, - TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR3, - TECH_TRAIN_OPT_SW_RD_WR_POS_DDR3, - TECH_TRAIN_MAX_RD_LAT_DDR3, - TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR3 - }; - MEM_TECH_FEAT_BLOCK memTechTrainingFeatSequenceDDR3Ph = { - MEM_TECH_FEAT_BLOCK_STRUCT_VERSION, - TECH_TRAIN_ENTER_HW_TRN_DDR3, - TECH_TRAIN_SW_WL_DDR3, - TECH_TRAIN_HW_WL_P1_DDR3, - TECH_TRAIN_HW_DQS_REC_EN_P1_DDR3, - TECH_TRAIN_HW_WL_P2_DDR3, - TECH_TRAIN_HW_DQS_REC_EN_P2_DDR3, - TECH_TRAIN_EXIT_HW_TRN_DDR3, - TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR3, - TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR3, - TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR3, - TECH_TRAIN_OPT_SW_RD_WR_POS_DDR3, - TECH_TRAIN_MAX_RD_LAT_DDR3, - TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR3 - }; - MEM_TECH_FEAT_BLOCK memTechTrainingFeatSequenceDDR3Rb = { - MEM_TECH_FEAT_BLOCK_STRUCT_VERSION, - TECH_TRAIN_ENTER_HW_TRN_DDR3, - TECH_TRAIN_SW_WL_DDR3, - TECH_TRAIN_HW_WL_P1_DDR3, - TECH_TRAIN_HW_DQS_REC_EN_P1_DDR3, - TECH_TRAIN_HW_WL_P2_DDR3, - TECH_TRAIN_HW_DQS_REC_EN_P2_DDR3, - TECH_TRAIN_EXIT_HW_TRN_DDR3, - TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR3, - TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR3, - TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR3, - TECH_TRAIN_OPT_SW_RD_WR_POS_DDR3, - TECH_TRAIN_MAX_RD_LAT_DDR3, - TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR3 - }; - MEM_TECH_FEAT_BLOCK memTechTrainingFeatSequenceDDR3Ni = { - MEM_TECH_FEAT_BLOCK_STRUCT_VERSION, - TECH_TRAIN_ENTER_HW_TRN_DDR3, - TECH_TRAIN_SW_WL_DDR3, - TECH_TRAIN_HW_WL_P1_DDR3, - TECH_TRAIN_HW_DQS_REC_EN_P1_DDR3, - TECH_TRAIN_HW_WL_P2_DDR3, - TECH_TRAIN_HW_DQS_REC_EN_P2_DDR3, - TECH_TRAIN_EXIT_HW_TRN_DDR3, - TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR3, - TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR3, - TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR3, - TECH_TRAIN_OPT_SW_RD_WR_POS_DDR3, - TECH_TRAIN_MAX_RD_LAT_DDR3, - TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR3 - }; -// extern OPTION_MEM_FEATURE_NB MemNDQSTiming3Nb; - #define NB_TRAIN_FLOW_DDR3 MemNDQSTiming3Nb -// extern OPTION_MEM_FEATURE_NB memNSequenceDDR3Nb; - #if (OPTION_MEMCTLR_DA) - extern OPTION_MEM_FEATURE_NB memNEnableTrainSequenceDA; - #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR3_DA { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, memNSequenceDDR3Nb, memNEnableTrainSequenceDA, &memTechTrainingFeatSequenceDDR3DA }, - #else - #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR3_DA { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 }, - #endif - #if (OPTION_MEMCTLR_PH) - extern OPTION_MEM_FEATURE_NB memNEnableTrainSequencePh; - #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR3_PH { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, memNSequenceDDR3Nb, memNEnableTrainSequencePh, &memTechTrainingFeatSequenceDDR3Ph }, - #else - #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR3_PH { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 }, - #endif - #if (OPTION_MEMCTLR_RB) - extern OPTION_MEM_FEATURE_NB memNEnableTrainSequenceRb; - #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR3_RB { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, memNSequenceDDR3Nb, memNEnableTrainSequenceRb, &memTechTrainingFeatSequenceDDR3Rb }, - #else - #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR3_RB { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 }, - #endif - #if (OPTION_MEMCTLR_Ni) - extern OPTION_MEM_FEATURE_NB memNEnableTrainSequenceNi; - #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR3_Ni {MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION,memNSequenceDDR3Nb, memNEnableTrainSequenceNi, &memTechTrainingFeatSequenceDDR3Ni }, - #else - #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR3_Ni { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 }, - #endif - #else - #undef TECH_TRAIN_ENTER_HW_TRN_DDR3 - #define TECH_TRAIN_ENTER_HW_TRN_DDR3 MemTFeatDef - #define TECH_TRAIN_EXIT_HW_TRN_DDR3 MemTFeatDef - #undef TECH_TRAIN_EXIT_HW_TRN_DDR3 - #define TECH_TRAIN_HW_WL_P1_DDR3 MemTFeatDef - #define TECH_TRAIN_HW_WL_P2_DDR3 MemTFeatDef - #define TECH_TRAIN_SW_WL_DDR3 MemTFeatDef - #define TECH_TRAIN_HW_DQS_REC_EN_P1_DDR3 MemTFeatDef - #define TECH_TRAIN_HW_DQS_REC_EN_P2_DDR3 MemTFeatDef - #define TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR3 MemTFeatDef - #define TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR3 MemTFeatDef - #define TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR3 MemTFeatDef - #define TECH_TRAIN_OPT_SW_RD_WR_POS_DDR3 MemTFeatDef - #define TECH_TRAIN_MAX_RD_LAT_DDR3 MemTFeatDef - #define NB_TRAIN_FLOW_DDR3 (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue - #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR3_Ni { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 }, - #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR3_DA { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 }, - #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR3_PH { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 }, - #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR3_RB { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 }, - #endif - #else - #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR2_Ni { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 }, - #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR3_Ni { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 }, - #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR2_DA { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 }, - #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR3_DA { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 }, - #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR2_PH { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 }, - #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR3_PH { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 }, - #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR2_RB { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 }, - #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR3_RB { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 }, - #endif - - #if OPTION_MEMCTLR_HY - extern OPTION_MEM_FEATURE_NB memNEnableTrainSequenceHy; - #if OPTION_DDR2 - #define TECH_TRAIN_ENTER_HW_TRN_DDR2 MemTFeatDef - #define TECH_TRAIN_EXIT_HW_TRN_DDR2 MemTFeatDef - #define TECH_TRAIN_HW_WL_P1_DDR2 MemTFeatDef - #define TECH_TRAIN_HW_WL_P2_DDR2 MemTFeatDef - #define TECH_TRAIN_SW_WL_DDR2 MemTFeatDef - #if (OPTION_HW_DQS_REC_EN_TRAINING == TRUE) - #define TECH_TRAIN_HW_DQS_REC_EN_P1_DDR2 MemTDqsTrainRcvrEnHwPass1 - #define TECH_TRAIN_HW_DQS_REC_EN_P2_DDR2 MemTDqsTrainRcvrEnHwPass2 - #define TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR2 MemTTrainDQSEdgeDetect - #else - #define TECH_TRAIN_HW_DQS_REC_EN_P1_DDR2 MemTFeatDef - #define TECH_TRAIN_HW_DQS_REC_EN_P2_DDR2 MemTFeatDef - #if (OPTION_NON_OPT_SW_RD_WR_POS_TRAINING == TRUE) - #define TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR2 MemTTrainDQSEdgeDetect - #else - #define TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR2 MemTFeatDef - #endif - #endif - #if (OPTION_NON_OPT_SW_DQS_REC_EN_TRAINING == TRUE) - #define TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR2 MemTTrainRcvrEnSwPass1 - #else - #define TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR2 MemTFeatDef - #endif - #if (OPTION_OPT_SW_DQS_REC_EN_TRAINING == TRUE) - #define TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR2 MemTFeatDef - #else - #define TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR2 MemTFeatDef - #endif - #if (OPTION_NON_OPT_SW_RD_WR_POS_TRAINING == TRUE) - #define TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR2 MemTTrainDQSEdgeDetectSw - #else - #define TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR2 MemTFeatDef - #endif - #if (OPTION_OPT_SW_RD_WR_POS_TRAINING == TRUE) - #define TECH_TRAIN_OPT_SW_RD_WR_POS_DDR2 MemTFeatDef - #else - #define TECH_TRAIN_OPT_SW_RD_WR_POS_DDR2 MemTFeatDef - #endif - #if (OPTION_MAX_RD_LAT_TRAINING == TRUE) - #define TECH_TRAIN_MAX_RD_LAT_DDR2 MemTTrainMaxLatency - #else - #define TECH_TRAIN_MAX_RD_LAT_DDR2 MemTFeatDef - #endif - MEM_TECH_FEAT_BLOCK memTechTrainingFeatSequenceDDR2Hy = { - MEM_TECH_FEAT_BLOCK_STRUCT_VERSION, - TECH_TRAIN_ENTER_HW_TRN_DDR2, - TECH_TRAIN_SW_WL_DDR2, - TECH_TRAIN_HW_WL_P1_DDR2, - TECH_TRAIN_HW_DQS_REC_EN_P1_DDR2, - TECH_TRAIN_HW_WL_P2_DDR2, - TECH_TRAIN_HW_DQS_REC_EN_P2_DDR2, - TECH_TRAIN_EXIT_HW_TRN_DDR2, - TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR2, - TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR2, - TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR2, - TECH_TRAIN_OPT_SW_RD_WR_POS_DDR2, - TECH_TRAIN_MAX_RD_LAT_DDR2, - TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR2 - }; - extern OPTION_MEM_FEATURE_NB MemNDQSTiming2Nb; - #define NB_TRAIN_FLOW_DDR2 MemNDQSTiming2Nb - extern OPTION_MEM_FEATURE_NB memNSequenceDDR2ServerNb; - #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR2_HY {MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION,memNSequenceDDR2ServerNb, memNEnableTrainSequenceHy, &memTechTrainingFeatSequenceDDR2Hy }, - #else - #define TECH_TRAIN_ENTER_HW_TRN_DDR2 MemTFeatDef - #define TECH_TRAIN_EXIT_HW_TRN_DDR2 MemTFeatDef - #define TECH_TRAIN_HW_WL_P1_DDR2 MemTFeatDef - #define TECH_TRAIN_HW_WL_P2_DDR2 MemTFeatDef - #define TECH_TRAIN_SW_WL_DDR2 MemTFeatDef - #define TECH_TRAIN_HW_DQS_REC_EN_P1_DDR2 MemTFeatDef - #define TECH_TRAIN_HW_DQS_REC_EN_P2_DDR2 MemTFeatDef - #define TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR2 MemTFeatDef - #define TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR2 MemTFeatDef - #define TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR2 MemTFeatDef - #define TECH_TRAIN_OPT_SW_RD_WR_POS_DDR2 MemTFeatDef - #define TECH_TRAIN_MAX_RD_LAT_DDR2 MemTFeatDef - #define NB_TRAIN_FLOW_DDR2 (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue - #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR2_HY { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 }, - #endif - #if OPTION_DDR3 - #undef TECH_TRAIN_ENTER_HW_TRN_DDR3 - #define TECH_TRAIN_ENTER_HW_TRN_DDR3 MemTPreparePhyAssistedTraining - #undef TECH_TRAIN_EXIT_HW_TRN_DDR3 - #define TECH_TRAIN_EXIT_HW_TRN_DDR3 MemTExitPhyAssistedTraining - #if (OPTION_HW_WRITE_LEV_TRAINING == TRUE) - #define TECH_TRAIN_HW_WL_P1_DDR3 MemTWriteLevelizationHw3Pass1 - #define TECH_TRAIN_HW_WL_P2_DDR3 MemTWriteLevelizationHw3Pass2 - #else - #define TECH_TRAIN_HW_WL_P1_DDR3 MemTFeatDef - #define TECH_TRAIN_HW_WL_P2_DDR3 MemTFeatDef - #endif - #if (OPTION_SW_WRITE_LEV_TRAINING == TRUE) - #define TECH_TRAIN_SW_WL_DDR3 MemTFeatDef - #else - #define TECH_TRAIN_SW_WL_DDR3 MemTFeatDef - #endif - #if (OPTION_HW_DQS_REC_EN_TRAINING == TRUE) - #ifdef TECH_TRAIN_HW_DQS_REC_EN_P1_DDR3 - #undef TECH_TRAIN_HW_DQS_REC_EN_P1_DDR3 - #endif - #define TECH_TRAIN_HW_DQS_REC_EN_P1_DDR3 MemTFeatDef - #ifdef TECH_TRAIN_HW_DQS_REC_EN_P2_DDR3 - #undef TECH_TRAIN_HW_DQS_REC_EN_P2_DDR3 - #endif - #define TECH_TRAIN_HW_DQS_REC_EN_P2_DDR3 MemTFeatDef - #if (OPTION_HW_DQS_REC_EN_SEED_TRAINING == TRUE) - #undef TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR3 - #define TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR3 MemTTrainDQSEdgeDetect - #else - #if (OPTION_OPT_SW_RD_WR_POS_TRAINING == TRUE || OPTION_NON_OPT_SW_RD_WR_POS_TRAINING == TRUE) - #define TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR3 MemTTrainDQSEdgeDetect - #else - #define TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR3 MemTFeatDef - #endif - #endif - #else - #define TECH_TRAIN_HW_DQS_REC_EN_P1_DDR3 MemTFeatDef - #define TECH_TRAIN_HW_DQS_REC_EN_P2_DDR3 MemTFeatDef - #if (OPTION_OPT_SW_RD_WR_POS_TRAINING == TRUE || OPTION_NON_OPT_SW_RD_WR_POS_TRAINING == TRUE) - #define TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR3 MemTTrainDQSEdgeDetect - #else - #define TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR3 MemTFeatDef - #endif - #endif - #if (OPTION_NON_OPT_SW_DQS_REC_EN_TRAINING == TRUE) - #define TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR3 MemTTrainRcvrEnSwPass1 - #else - #define TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR3 MemTFeatDef - #endif - #if (OPTION_OPT_SW_DQS_REC_EN_TRAINING == TRUE) - #define TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR3 MemTTrainOptRcvrEnSwPass1 - #else - #define TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR3 MemTFeatDef - #endif - #if (OPTION_NON_OPT_SW_RD_WR_POS_TRAINING == TRUE) - #define TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR3 MemTTrainDQSEdgeDetectSw - #else - #define TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR3 MemTFeatDef - #endif - #if (OPTION_OPT_SW_RD_WR_POS_TRAINING == TRUE) - #define TECH_TRAIN_OPT_SW_RD_WR_POS_DDR3 MemTTrainDQSEdgeDetectSw - #else - #define TECH_TRAIN_OPT_SW_RD_WR_POS_DDR3 MemTFeatDef - #endif - #if (OPTION_MAX_RD_LAT_TRAINING == TRUE) - #define TECH_TRAIN_MAX_RD_LAT_DDR3 MemTTrainMaxLatency - #else - #define TECH_TRAIN_MAX_RD_LAT_DDR3 MemTFeatDef - #endif - MEM_TECH_FEAT_BLOCK memTechTrainingFeatSequenceDDR3Hy = { - MEM_TECH_FEAT_BLOCK_STRUCT_VERSION, - TECH_TRAIN_ENTER_HW_TRN_DDR3, - TECH_TRAIN_SW_WL_DDR3, - TECH_TRAIN_HW_WL_P1_DDR3, - TECH_TRAIN_HW_DQS_REC_EN_P1_DDR3, - TECH_TRAIN_HW_WL_P2_DDR3, - TECH_TRAIN_HW_DQS_REC_EN_P2_DDR3, - TECH_TRAIN_EXIT_HW_TRN_DDR3, - TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR3, - TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR3, - TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR3, - TECH_TRAIN_OPT_SW_RD_WR_POS_DDR3, - TECH_TRAIN_MAX_RD_LAT_DDR3, - TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR3 - }; -// extern OPTION_MEM_FEATURE_NB MemNDQSTiming3Nb; - #define NB_TRAIN_FLOW_DDR3 MemNDQSTiming3Nb -// extern OPTION_MEM_FEATURE_NB memNSequenceDDR3Nb; - #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR3_HY {MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION,memNSequenceDDR3Nb, memNEnableTrainSequenceHy, &memTechTrainingFeatSequenceDDR3Hy }, - #else - #undef TECH_TRAIN_ENTER_HW_TRN_DDR3 - #define TECH_TRAIN_ENTER_HW_TRN_DDR3 MemTFeatDef - #undef TECH_TRAIN_EXIT_HW_TRN_DDR3 - #define TECH_TRAIN_EXIT_HW_TRN_DDR3 MemTFeatDef - #define TECH_TRAIN_HW_WL_P1_DDR3 MemTFeatDef - #define TECH_TRAIN_HW_WL_P2_DDR3 MemTFeatDef - #define TECH_TRAIN_SW_WL_DDR3 MemTFeatDef - #define TECH_TRAIN_HW_DQS_REC_EN_P1_DDR3 MemTFeatDef - #define TECH_TRAIN_HW_DQS_REC_EN_P2_DDR3 MemTFeatDef - #define TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR3 MemTFeatDef - #define TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR3 MemTFeatDef - #define TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR3 MemTFeatDef - #define TECH_TRAIN_OPT_SW_RD_WR_POS_DDR3 MemTFeatDef - #define TECH_TRAIN_MAX_RD_LAT_DDR3 MemTFeatDef - #define NB_TRAIN_FLOW_DDR3 (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue - #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR3_HY { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 }, - #endif - #else - #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR2_HY { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 }, - #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR3_HY { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 }, - #endif - - #if OPTION_MEMCTLR_C32 - extern OPTION_MEM_FEATURE_NB memNEnableTrainSequenceC32; - #if OPTION_DDR2 - #define TECH_TRAIN_ENTER_HW_TRN_DDR2 MemTFeatDef - #define TECH_TRAIN_EXIT_HW_TRN_DDR2 MemTFeatDef - #define TECH_TRAIN_HW_WL_P1_DDR2 MemTFeatDef - #define TECH_TRAIN_HW_WL_P2_DDR2 MemTFeatDef - #define TECH_TRAIN_SW_WL_DDR2 MemTFeatDef - #if (OPTION_HW_DQS_REC_EN_TRAINING == TRUE) - #define TECH_TRAIN_HW_DQS_REC_EN_P1_DDR2 MemTDqsTrainRcvrEnHwPass1 - #define TECH_TRAIN_HW_DQS_REC_EN_P2_DDR2 MemTDqsTrainRcvrEnHwPass2 - #define TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR2 MemTTrainDQSEdgeDetect - #else - #define TECH_TRAIN_HW_DQS_REC_EN_P1_DDR2 MemTFeatDef - #define TECH_TRAIN_HW_DQS_REC_EN_P2_DDR2 MemTFeatDef - #if (OPTION_NON_OPT_SW_RD_WR_POS_TRAINING == TRUE) - #define TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR3 MemTTrainDQSEdgeDetect - #else - #define TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR3 MemTFeatDef - #endif - #endif - #if (OPTION_NON_OPT_SW_DQS_REC_EN_TRAINING == TRUE) - #define TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR2 MemTTrainRcvrEnSwPass1 - #else - #define TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR2 MemTFeatDef - #endif - #if (OPTION_OPT_SW_DQS_REC_EN_TRAINING == TRUE) - #define TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR2 MemTFeatDef - #else - #define TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR2 MemTFeatDef - #endif - #if (OPTION_NON_OPT_SW_RD_WR_POS_TRAINING == TRUE) - #define TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR2 MemTTrainDQSEdgeDetectSw - #else - #define TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR2 MemTFeatDef - #endif - #if (OPTION_OPT_SW_RD_WR_POS_TRAINING == TRUE) - #define TECH_TRAIN_OPT_SW_RD_WR_POS_DDR2 MemTFeatDef - #else - #define TECH_TRAIN_OPT_SW_RD_WR_POS_DDR2 MemTFeatDef - #endif - #if (OPTION_MAX_RD_LAT_TRAINING == TRUE) - #define TECH_TRAIN_MAX_RD_LAT_DDR2 MemTTrainMaxLatency - #else - #define TECH_TRAIN_MAX_RD_LAT_DDR2 MemTFeatDef - #endif - MEM_TECH_FEAT_BLOCK memTechTrainingFeatSequenceDDR2C32 = { - MEM_TECH_FEAT_BLOCK_STRUCT_VERSION, - TECH_TRAIN_ENTER_HW_TRN_DDR2, - TECH_TRAIN_SW_WL_DDR2, - TECH_TRAIN_HW_WL_P1_DDR2, - TECH_TRAIN_HW_DQS_REC_EN_P1_DDR2, - TECH_TRAIN_HW_WL_P2_DDR2, - TECH_TRAIN_HW_DQS_REC_EN_P2_DDR2, - TECH_TRAIN_EXIT_HW_TRN_DDR2, - TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR2, - TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR2, - TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR2, - TECH_TRAIN_OPT_SW_RD_WR_POS_DDR2, - TECH_TRAIN_MAX_RD_LAT_DDR2, - TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR2 - }; - extern OPTION_MEM_FEATURE_NB MemNDQSTiming2Nb; - #define NB_TRAIN_FLOW_DDR2 MemNDQSTiming2Nb - extern OPTION_MEM_FEATURE_NB memNSequenceDDR2ServerNb; - #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR2_C32 {MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION,memNSequenceDDR2ServerNb, memNEnableTrainSequenceC32, &memTechTrainingFeatSequenceDDR2C32 }, - #else - #define TECH_TRAIN_ENTER_HW_TRN_DDR2 MemTFeatDef - #define TECH_TRAIN_EXIT_HW_TRN_DDR2 MemTFeatDef - #define TECH_TRAIN_HW_WL_P1_DDR2 MemTFeatDef - #define TECH_TRAIN_HW_WL_P2_DDR2 MemTFeatDef - #define TECH_TRAIN_SW_WL_DDR2 MemTFeatDef - #define TECH_TRAIN_HW_DQS_REC_EN_P1_DDR2 MemTFeatDef - #define TECH_TRAIN_HW_DQS_REC_EN_P2_DDR2 MemTFeatDef - #define TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR2 MemTFeatDef - #define TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR2 MemTFeatDef - #define TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR2 MemTFeatDef - #define TECH_TRAIN_OPT_SW_RD_WR_POS_DDR2 MemTFeatDef - #define TECH_TRAIN_MAX_RD_LAT_DDR2 MemTFeatDef - #define NB_TRAIN_FLOW_DDR2 (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue - #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR2_C32 { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 }, - #endif - #if OPTION_DDR3 - #undef TECH_TRAIN_ENTER_HW_TRN_DDR3 - #define TECH_TRAIN_ENTER_HW_TRN_DDR3 MemTPreparePhyAssistedTraining - #undef TECH_TRAIN_EXIT_HW_TRN_DDR3 - #define TECH_TRAIN_EXIT_HW_TRN_DDR3 MemTExitPhyAssistedTraining - #if (OPTION_HW_WRITE_LEV_TRAINING == TRUE) - #define TECH_TRAIN_HW_WL_P1_DDR3 MemTWriteLevelizationHw3Pass1 - #define TECH_TRAIN_HW_WL_P2_DDR3 MemTWriteLevelizationHw3Pass2 - #else - #define TECH_TRAIN_HW_WL_P1_DDR3 MemTFeatDef - #define TECH_TRAIN_HW_WL_P2_DDR3 MemTFeatDef - #endif - #if (OPTION_SW_WRITE_LEV_TRAINING == TRUE) - #define TECH_TRAIN_SW_WL_DDR3 MemTFeatDef - #else - #define TECH_TRAIN_SW_WL_DDR3 MemTFeatDef - #endif - #if (OPTION_HW_DQS_REC_EN_TRAINING == TRUE) - #ifdef TECH_TRAIN_HW_DQS_REC_EN_P1_DDR3 - #undef TECH_TRAIN_HW_DQS_REC_EN_P1_DDR3 - #endif - #define TECH_TRAIN_HW_DQS_REC_EN_P1_DDR3 MemTFeatDef - #ifdef TECH_TRAIN_HW_DQS_REC_EN_P2_DDR3 - #undef TECH_TRAIN_HW_DQS_REC_EN_P2_DDR3 - #endif - #define TECH_TRAIN_HW_DQS_REC_EN_P2_DDR3 MemTFeatDef - #if (OPTION_HW_DQS_REC_EN_SEED_TRAINING == TRUE) - #define TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR3 MemTTrainDQSEdgeDetect - #else - #if (OPTION_OPT_SW_RD_WR_POS_TRAINING == TRUE || OPTION_NON_OPT_SW_RD_WR_POS_TRAINING == TRUE) - #define TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR3 MemTTrainDQSEdgeDetect - #else - #define TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR3 MemTFeatDef - #endif - #endif - #else - #define TECH_TRAIN_HW_DQS_REC_EN_P1_DDR3 MemTFeatDef - #define TECH_TRAIN_HW_DQS_REC_EN_P2_DDR3 MemTFeatDef - #if (OPTION_OPT_SW_RD_WR_POS_TRAINING == TRUE || OPTION_NON_OPT_SW_RD_WR_POS_TRAINING == TRUE) - #define TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR3 MemTTrainDQSEdgeDetect - #else - #define TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR3 MemTFeatDef - #endif - #endif - #if (OPTION_NON_OPT_SW_DQS_REC_EN_TRAINING == TRUE) - #define TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR3 MemTTrainRcvrEnSwPass1 - #else - #define TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR3 MemTFeatDef - #endif - #if (OPTION_OPT_SW_DQS_REC_EN_TRAINING == TRUE) - #define TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR3 MemTTrainOptRcvrEnSwPass1 - #else - #define TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR3 MemTFeatDef - #endif - #if (OPTION_NON_OPT_SW_RD_WR_POS_TRAINING == TRUE) - #define TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR3 MemTTrainDQSEdgeDetectSw - #else - #define TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR3 MemTFeatDef - #endif - #if (OPTION_OPT_SW_RD_WR_POS_TRAINING == TRUE) - #define TECH_TRAIN_OPT_SW_RD_WR_POS_DDR3 MemTTrainDQSEdgeDetectSw - #else - #define TECH_TRAIN_OPT_SW_RD_WR_POS_DDR3 MemTFeatDef - #endif - #if (OPTION_MAX_RD_LAT_TRAINING == TRUE) - #define TECH_TRAIN_MAX_RD_LAT_DDR3 MemTTrainMaxLatency - #else - #define TECH_TRAIN_MAX_RD_LAT_DDR3 MemTFeatDef - #endif - MEM_TECH_FEAT_BLOCK memTechTrainingFeatSequenceDDR3C32 = { - MEM_TECH_FEAT_BLOCK_STRUCT_VERSION, - TECH_TRAIN_ENTER_HW_TRN_DDR3, - TECH_TRAIN_SW_WL_DDR3, - TECH_TRAIN_HW_WL_P1_DDR3, - TECH_TRAIN_HW_DQS_REC_EN_P1_DDR3, - TECH_TRAIN_HW_WL_P2_DDR3, - TECH_TRAIN_HW_DQS_REC_EN_P2_DDR3, - TECH_TRAIN_EXIT_HW_TRN_DDR3, - TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR3, - TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR3, - TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR3, - TECH_TRAIN_OPT_SW_RD_WR_POS_DDR3, - TECH_TRAIN_MAX_RD_LAT_DDR3, - TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR3 - }; -// extern OPTION_MEM_FEATURE_NB MemNDQSTiming3Nb; - #define NB_TRAIN_FLOW_DDR3 MemNDQSTiming3Nb -// extern OPTION_MEM_FEATURE_NB memNSequenceDDR3Nb; - #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR3_C32 {MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION,memNSequenceDDR3Nb, memNEnableTrainSequenceC32, &memTechTrainingFeatSequenceDDR3C32 }, - #else - #undef TECH_TRAIN_ENTER_HW_TRN_DDR3 - #define TECH_TRAIN_ENTER_HW_TRN_DDR3 MemTFeatDef - #undef TECH_TRAIN_EXIT_HW_TRN_DDR3 - #define TECH_TRAIN_EXIT_HW_TRN_DDR3 MemTFeatDef - #define TECH_TRAIN_HW_WL_P1_DDR3 MemTFeatDef - #define TECH_TRAIN_HW_WL_P2_DDR3 MemTFeatDef - #define TECH_TRAIN_SW_WL_DDR3 MemTFeatDef - #define TECH_TRAIN_HW_DQS_REC_EN_P1_DDR3 MemTFeatDef - #define TECH_TRAIN_HW_DQS_REC_EN_P2_DDR3 MemTFeatDef - #define TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR3 MemTFeatDef - #define TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR3 MemTFeatDef - #define TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR3 MemTFeatDef - #define TECH_TRAIN_OPT_SW_RD_WR_POS_DDR3 MemTFeatDef - #define TECH_TRAIN_MAX_RD_LAT_DDR3 MemTFeatDef - #define NB_TRAIN_FLOW_DDR3 (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue - #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR3_C32 { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 }, - #endif - #else - #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR2_C32 { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 }, - #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR3_C32 { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 }, - #endif - - - #if OPTION_MEMCTLR_LN - #define TECH_TRAIN_ENTER_HW_TRN_DDR2 MemTFeatDef - #define TECH_TRAIN_EXIT_HW_TRN_DDR2 MemTFeatDef - #define TECH_TRAIN_HW_WL_P1_DDR2 MemTFeatDef - #define TECH_TRAIN_HW_WL_P2_DDR2 MemTFeatDef - #define TECH_TRAIN_SW_WL_DDR2 MemTFeatDef - #define TECH_TRAIN_HW_DQS_REC_EN_P1_DDR2 MemTFeatDef - #define TECH_TRAIN_HW_DQS_REC_EN_P2_DDR2 MemTFeatDef - #define TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR2 MemTFeatDef - #define TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR2 MemTFeatDef - #define TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR2 MemTFeatDef - #define TECH_TRAIN_OPT_SW_RD_WR_POS_DDR2 MemTFeatDef - #define TECH_TRAIN_MAX_RD_LAT_DDR2 MemTFeatDef - #define NB_TRAIN_FLOW_DDR2 (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue - #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR2_LN { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 }, - extern OPTION_MEM_FEATURE_NB memNEnableTrainSequenceLN; - #if OPTION_DDR3 - #undef TECH_TRAIN_ENTER_HW_TRN_DDR3 - #define TECH_TRAIN_ENTER_HW_TRN_DDR3 MemTFeatDef - #undef TECH_TRAIN_EXIT_HW_TRN_DDR3 - #define TECH_TRAIN_EXIT_HW_TRN_DDR3 MemTExitPhyAssistedTrainingClient3 - #if (OPTION_HW_WRITE_LEV_TRAINING == TRUE) - #define TECH_TRAIN_HW_WL_P1_DDR3 MemTWriteLevelizationHw3Pass1 - #define TECH_TRAIN_HW_WL_P2_DDR3 MemTWriteLevelizationHw3Pass2 - #else - #define TECH_TRAIN_HW_WL_P1_DDR3 MemTFeatDef - #define TECH_TRAIN_HW_WL_P2_DDR3 MemTFeatDef - #endif - #define TECH_TRAIN_SW_WL_DDR3 MemTFeatDef - #if (OPTION_HW_DQS_REC_EN_TRAINING == TRUE) - #ifdef TECH_TRAIN_HW_DQS_REC_EN_P1_DDR3 - #undef TECH_TRAIN_HW_DQS_REC_EN_P1_DDR3 - #endif - #define TECH_TRAIN_HW_DQS_REC_EN_P1_DDR3 MemTDqsTrainRcvrEnHwPass1 - #ifdef TECH_TRAIN_HW_DQS_REC_EN_P2_DDR3 - #undef TECH_TRAIN_HW_DQS_REC_EN_P2_DDR3 - #endif - #define TECH_TRAIN_HW_DQS_REC_EN_P2_DDR3 MemTDqsTrainRcvrEnHwPass2 - #if (OPTION_HW_DQS_REC_EN_SEED_TRAINING == TRUE) - #undef TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR3 - #define TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR3 MemTRdPosWithRxEnDlySeeds3 - #else - #if (OPTION_OPT_SW_RD_WR_POS_TRAINING == TRUE || OPTION_NON_OPT_SW_RD_WR_POS_TRAINING == TRUE) - #define TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR3 MemTTrainDQSEdgeDetect - #else - #define TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR3 MemTFeatDef - #endif - #endif - #else - #define TECH_TRAIN_HW_DQS_REC_EN_P1_DDR3 MemTFeatDef - #define TECH_TRAIN_HW_DQS_REC_EN_P2_DDR3 MemTFeatDef - #if (OPTION_OPT_SW_RD_WR_POS_TRAINING == TRUE || OPTION_NON_OPT_SW_RD_WR_POS_TRAINING == TRUE) - #define TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR3 MemTTrainDQSEdgeDetect - #else - #define TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR3 MemTFeatDef - #endif - #endif - #if (OPTION_NON_OPT_SW_DQS_REC_EN_TRAINING == TRUE) - #define TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR3 MemTTrainRcvrEnSwPass1 - #else - #define TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR3 MemTFeatDef - #endif - #if (OPTION_OPT_SW_DQS_REC_EN_TRAINING == TRUE) - #define TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR3 MemTTrainOptRcvrEnSwPass1 - #else - #define TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR3 MemTFeatDef - #endif - #if (OPTION_NON_OPT_SW_RD_WR_POS_TRAINING == TRUE) - #define TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR3 MemTTrainDQSEdgeDetectSw - #else - #define TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR3 MemTFeatDef - #endif - #if (OPTION_OPT_SW_RD_WR_POS_TRAINING == TRUE) - #define TECH_TRAIN_OPT_SW_RD_WR_POS_DDR3 MemTTrainDQSEdgeDetectSw - #else - #define TECH_TRAIN_OPT_SW_RD_WR_POS_DDR3 MemTFeatDef - #endif - #if (OPTION_MAX_RD_LAT_TRAINING == TRUE) - #define TECH_TRAIN_MAX_RD_LAT_DDR3 MemTTrainMaxLatency - #else - #define TECH_TRAIN_MAX_RD_LAT_DDR3 MemTFeatDef - #endif - MEM_TECH_FEAT_BLOCK memTechTrainingFeatSequenceDDR3LN = { - MEM_TECH_FEAT_BLOCK_STRUCT_VERSION, - TECH_TRAIN_ENTER_HW_TRN_DDR3, - TECH_TRAIN_SW_WL_DDR3, - TECH_TRAIN_HW_WL_P1_DDR3, - TECH_TRAIN_HW_DQS_REC_EN_P1_DDR3, - TECH_TRAIN_HW_WL_P2_DDR3, - TECH_TRAIN_HW_DQS_REC_EN_P2_DDR3, - TECH_TRAIN_EXIT_HW_TRN_DDR3, - TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR3, - TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR3, - TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR3, - TECH_TRAIN_OPT_SW_RD_WR_POS_DDR3, - TECH_TRAIN_MAX_RD_LAT_DDR3, - TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR3 - }; -// extern OPTION_MEM_FEATURE_NB MemNDQSTiming3Nb; - #define NB_TRAIN_FLOW_DDR3 MemNDQSTiming3Nb -// extern OPTION_MEM_FEATURE_NB memNSequenceDDR3Nb; - #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR3_LN {MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, memNSequenceDDR3Nb, memNEnableTrainSequenceLN, &memTechTrainingFeatSequenceDDR3LN }, - #else - #undef TECH_TRAIN_ENTER_HW_TRN_DDR3 - #define TECH_TRAIN_ENTER_HW_TRN_DDR3 MemTFeatDef - #undef TECH_TRAIN_EXIT_HW_TRN_DDR3 - #define TECH_TRAIN_EXIT_HW_TRN_DDR3 MemTFeatDef - #define TECH_TRAIN_HW_WL_P1_DDR3 MemTFeatDef - #define TECH_TRAIN_HW_WL_P2_DDR3 MemTFeatDef - #define TECH_TRAIN_SW_WL_DDR3 MemTFeatDef - #define TECH_TRAIN_HW_DQS_REC_EN_P1_DDR3 MemTFeatDef - #define TECH_TRAIN_HW_DQS_REC_EN_P2_DDR3 MemTFeatDef - #define TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR3 MemTFeatDef - #define TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR3 MemTFeatDef - #define TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR3 MemTFeatDef - #define TECH_TRAIN_OPT_SW_RD_WR_POS_DDR3 MemTFeatDef - #define TECH_TRAIN_MAX_RD_LAT_DDR3 MemTFeatDef - #define NB_TRAIN_FLOW_DDR3 (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue - #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR3_LN { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 }, - #endif - #else - #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR2_LN { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 }, - #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR3_LN { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 }, - #endif - - - #if OPTION_MEMCTLR_OR - extern OPTION_MEM_FEATURE_NB memNEnableTrainSequenceOr; - #define TECH_TRAIN_ENTER_HW_TRN_DDR2 MemTFeatDef - #define TECH_TRAIN_EXIT_HW_TRN_DDR2 MemTFeatDef - #define TECH_TRAIN_HW_WL_P1_DDR2 MemTFeatDef - #define TECH_TRAIN_HW_WL_P2_DDR2 MemTFeatDef - #define TECH_TRAIN_SW_WL_DDR2 MemTFeatDef - #define TECH_TRAIN_HW_DQS_REC_EN_P1_DDR2 MemTFeatDef - #define TECH_TRAIN_HW_DQS_REC_EN_P2_DDR2 MemTFeatDef - #define TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR2 MemTFeatDef - #define TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR2 MemTFeatDef - #define TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR2 MemTFeatDef - #define TECH_TRAIN_OPT_SW_RD_WR_POS_DDR2 MemTFeatDef - #define TECH_TRAIN_MAX_RD_LAT_DDR2 MemTFeatDef - #define NB_TRAIN_FLOW_DDR2 (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue - #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR2_OR { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 }, - #if OPTION_DDR3 - #undef TECH_TRAIN_ENTER_HW_TRN_DDR3 - #define TECH_TRAIN_ENTER_HW_TRN_DDR3 MemTPreparePhyAssistedTraining - #undef TECH_TRAIN_EXIT_HW_TRN_DDR3 - #define TECH_TRAIN_EXIT_HW_TRN_DDR3 MemTExitPhyAssistedTraining - #if (OPTION_HW_WRITE_LEV_TRAINING == TRUE) - #define TECH_TRAIN_HW_WL_P1_DDR3 MemTWriteLevelizationHw3Pass1 - #define TECH_TRAIN_HW_WL_P2_DDR3 MemTWriteLevelizationHw3Pass2 - #else - #define TECH_TRAIN_HW_WL_P1_DDR3 MemTFeatDef - #define TECH_TRAIN_HW_WL_P2_DDR3 MemTFeatDef - #endif - #if (OPTION_SW_WRITE_LEV_TRAINING == TRUE) - #define TECH_TRAIN_SW_WL_DDR3 MemTFeatDef - #else - #define TECH_TRAIN_SW_WL_DDR3 MemTFeatDef - #endif - #if (OPTION_HW_DQS_REC_EN_TRAINING == TRUE) - #ifdef TECH_TRAIN_HW_DQS_REC_EN_P1_DDR3 - #undef TECH_TRAIN_HW_DQS_REC_EN_P1_DDR3 - #endif - #define TECH_TRAIN_HW_DQS_REC_EN_P1_DDR3 MemTDqsTrainRcvrEnHwPass1 - #ifdef TECH_TRAIN_HW_DQS_REC_EN_P2_DDR3 - #undef TECH_TRAIN_HW_DQS_REC_EN_P2_DDR3 - #endif - #define TECH_TRAIN_HW_DQS_REC_EN_P2_DDR3 MemTDqsTrainRcvrEnHwPass2 - #if (OPTION_HW_DQS_REC_EN_SEED_TRAINING == TRUE) - #undef TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR3 - #define TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR3 MemTRdPosWithRxEnDlySeeds3 - #else - #if (OPTION_OPT_SW_RD_WR_POS_TRAINING == TRUE || OPTION_NON_OPT_SW_RD_WR_POS_TRAINING == TRUE) - #define TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR3 MemTTrainDQSEdgeDetect - #else - #define TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR3 MemTFeatDef - #endif - #endif - #else - #define TECH_TRAIN_HW_DQS_REC_EN_P1_DDR3 MemTFeatDef - #define TECH_TRAIN_HW_DQS_REC_EN_P2_DDR3 MemTFeatDef - #if (OPTION_OPT_SW_RD_WR_POS_TRAINING == TRUE || OPTION_NON_OPT_SW_RD_WR_POS_TRAINING == TRUE) - #define TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR3 MemTTrainDQSEdgeDetect - #else - #define TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR3 MemTFeatDef - #endif - #endif - #if (OPTION_NON_OPT_SW_DQS_REC_EN_TRAINING == TRUE) - #define TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR3 MemTFeatDef - #else - #define TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR3 MemTFeatDef - #endif - #undef TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR3 - #if (OPTION_OPT_SW_DQS_REC_EN_TRAINING == TRUE) - #define TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR3 MemTFeatDef - #else - #define TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR3 MemTFeatDef - #endif - #if (OPTION_NON_OPT_SW_RD_WR_POS_TRAINING == TRUE) - #define TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR3 MemTTrainDQSEdgeDetectSw - #else - #define TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR3 MemTFeatDef - #endif - #undef TECH_TRAIN_OPT_SW_RD_WR_POS_DDR3 - #if (OPTION_OPT_SW_RD_WR_POS_TRAINING == TRUE) - #define TECH_TRAIN_OPT_SW_RD_WR_POS_DDR3 MemTTrainDQSEdgeDetectSw - #else - #define TECH_TRAIN_OPT_SW_RD_WR_POS_DDR3 MemTFeatDef - #endif - #if (OPTION_MAX_RD_LAT_TRAINING == TRUE) - #define TECH_TRAIN_MAX_RD_LAT_DDR3 MemTTrainMaxLatency - #else - #define TECH_TRAIN_MAX_RD_LAT_DDR3 MemTFeatDef - #endif - MEM_TECH_FEAT_BLOCK memTechTrainingFeatSequenceDDR3OR = { - MEM_TECH_FEAT_BLOCK_STRUCT_VERSION, - TECH_TRAIN_ENTER_HW_TRN_DDR3, - TECH_TRAIN_SW_WL_DDR3, - TECH_TRAIN_HW_WL_P1_DDR3, - TECH_TRAIN_HW_DQS_REC_EN_P1_DDR3, - TECH_TRAIN_HW_WL_P2_DDR3, - TECH_TRAIN_HW_DQS_REC_EN_P2_DDR3, - TECH_TRAIN_EXIT_HW_TRN_DDR3, - TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR3, - TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR3, - TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR3, - TECH_TRAIN_OPT_SW_RD_WR_POS_DDR3, - TECH_TRAIN_MAX_RD_LAT_DDR3, - TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR3 - }; -// extern OPTION_MEM_FEATURE_NB MemNDQSTiming3Nb; - #define NB_TRAIN_FLOW_DDR3 MemNDQSTiming3Nb -// extern OPTION_MEM_FEATURE_NB memNSequenceDDR3Nb; - #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR3_OR {MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION,memNSequenceDDR3Nb, memNEnableTrainSequenceOr, &memTechTrainingFeatSequenceDDR3OR }, - #else - #undef TECH_TRAIN_ENTER_HW_TRN_DDR3 - #define TECH_TRAIN_ENTER_HW_TRN_DDR3 MemTFeatDef - #undef TECH_TRAIN_EXIT_HW_TRN_DDR3 - #define TECH_TRAIN_EXIT_HW_TRN_DDR3 MemTFeatDef - #define TECH_TRAIN_HW_WL_P1_DDR3 MemTFeatDef - #define TECH_TRAIN_HW_WL_P2_DDR3 MemTFeatDef - #define TECH_TRAIN_SW_WL_DDR3 MemTFeatDef - #define TECH_TRAIN_HW_DQS_REC_EN_P1_DDR3 MemTFeatDef - #define TECH_TRAIN_HW_DQS_REC_EN_P2_DDR3 MemTFeatDef - #define TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR3 MemTFeatDef - #define TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR3 MemTFeatDef - #define TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR3 MemTFeatDef - #define TECH_TRAIN_OPT_SW_RD_WR_POS_DDR3 MemTFeatDef - #define TECH_TRAIN_MAX_RD_LAT_DDR3 MemTFeatDef - #define NB_TRAIN_FLOW_DDR3 (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue - #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR3_OR { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 }, - #endif - #else - #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR2_OR { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 }, - #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR3_OR { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 }, - #endif - - - #if OPTION_MEMCTLR_ON - extern OPTION_MEM_FEATURE_NB memNEnableTrainSequenceON; - #define TECH_TRAIN_ENTER_HW_TRN_DDR2 MemTFeatDef - #define TECH_TRAIN_EXIT_HW_TRN_DDR2 MemTFeatDef - #define TECH_TRAIN_HW_WL_P1_DDR2 MemTFeatDef - #define TECH_TRAIN_HW_WL_P2_DDR2 MemTFeatDef - #define TECH_TRAIN_SW_WL_DDR2 MemTFeatDef - #define TECH_TRAIN_HW_DQS_REC_EN_P1_DDR2 MemTFeatDef - #define TECH_TRAIN_HW_DQS_REC_EN_P2_DDR2 MemTFeatDef - #define TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR2 MemTFeatDef - #define TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR2 MemTFeatDef - #define TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR2 MemTFeatDef - #define TECH_TRAIN_OPT_SW_RD_WR_POS_DDR2 MemTFeatDef - #define TECH_TRAIN_MAX_RD_LAT_DDR2 MemTFeatDef - #define NB_TRAIN_FLOW_DDR2 (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue - #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR2_ON { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 }, - #if OPTION_DDR3 - #undef TECH_TRAIN_ENTER_HW_TRN_DDR3 - #define TECH_TRAIN_ENTER_HW_TRN_DDR3 MemTFeatDef - #undef TECH_TRAIN_EXIT_HW_TRN_DDR3 - #define TECH_TRAIN_EXIT_HW_TRN_DDR3 MemTExitPhyAssistedTrainingClient3 - #if (OPTION_HW_WRITE_LEV_TRAINING == TRUE) - #define TECH_TRAIN_HW_WL_P1_DDR3 MemTWriteLevelizationHw3Pass1 - #define TECH_TRAIN_HW_WL_P2_DDR3 MemTWriteLevelizationHw3Pass2 - #else - #define TECH_TRAIN_HW_WL_P1_DDR3 MemTFeatDef - #define TECH_TRAIN_HW_WL_P2_DDR3 MemTFeatDef - #endif - #define TECH_TRAIN_SW_WL_DDR3 MemTFeatDef - #if (OPTION_HW_DQS_REC_EN_TRAINING == TRUE) - #define TECH_TRAIN_HW_DQS_REC_EN_P1_DDR3 MemTDqsTrainRcvrEnHwPass1 - #define TECH_TRAIN_HW_DQS_REC_EN_P2_DDR3 MemTDqsTrainRcvrEnHwPass2 - #if (OPTION_HW_DQS_REC_EN_SEED_TRAINING == TRUE) - #undef TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR3 - #define TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR3 MemTRdPosWithRxEnDlySeeds3 - #else - #if (OPTION_OPT_SW_RD_WR_POS_TRAINING == TRUE || OPTION_NON_OPT_SW_RD_WR_POS_TRAINING == TRUE) - #define TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR3 MemTTrainDQSEdgeDetect - #else - #define TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR3 MemTFeatDef - #endif - #endif - #else - #define TECH_TRAIN_HW_DQS_REC_EN_P1_DDR3 MemTFeatDef - #define TECH_TRAIN_HW_DQS_REC_EN_P2_DDR3 MemTFeatDef - #if (OPTION_OPT_SW_RD_WR_POS_TRAINING == TRUE || OPTION_NON_OPT_SW_RD_WR_POS_TRAINING == TRUE) - #define TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR3 MemTTrainDQSEdgeDetect - #else - #define TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR3 MemTFeatDef - #endif - #endif - #if (OPTION_NON_OPT_SW_DQS_REC_EN_TRAINING == TRUE) - #define TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR3 MemTTrainRcvrEnSwPass1 - #else - #define TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR3 MemTFeatDef - #endif - #undef TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR3 - #if (OPTION_OPT_SW_DQS_REC_EN_TRAINING == TRUE) - #define TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR3 MemTTrainOptRcvrEnSwPass1 - #else - #define TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR3 MemTFeatDef - #endif - #if (OPTION_NON_OPT_SW_RD_WR_POS_TRAINING == TRUE) - #define TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR3 MemTTrainDQSEdgeDetectSw - #else - #define TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR3 MemTFeatDef - #endif - #if (OPTION_OPT_SW_RD_WR_POS_TRAINING == TRUE) - #define TECH_TRAIN_OPT_SW_RD_WR_POS_DDR3 MemTTrainDQSEdgeDetectSw - #else - #define TECH_TRAIN_OPT_SW_RD_WR_POS_DDR3 MemTFeatDef - #endif - #if (OPTION_MAX_RD_LAT_TRAINING == TRUE) - #define TECH_TRAIN_MAX_RD_LAT_DDR3 MemTTrainMaxLatency - #else - #define TECH_TRAIN_MAX_RD_LAT_DDR3 MemTFeatDef - #endif - MEM_TECH_FEAT_BLOCK memTechTrainingFeatSequenceDDR3ON = { - MEM_TECH_FEAT_BLOCK_STRUCT_VERSION, - TECH_TRAIN_ENTER_HW_TRN_DDR3, - TECH_TRAIN_SW_WL_DDR3, - TECH_TRAIN_HW_WL_P1_DDR3, - TECH_TRAIN_HW_DQS_REC_EN_P1_DDR3, - TECH_TRAIN_HW_WL_P2_DDR3, - TECH_TRAIN_HW_DQS_REC_EN_P2_DDR3, - TECH_TRAIN_EXIT_HW_TRN_DDR3, - TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR3, - TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR3, - TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR3, - TECH_TRAIN_OPT_SW_RD_WR_POS_DDR3, - TECH_TRAIN_MAX_RD_LAT_DDR3, - TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR3 - }; -// extern OPTION_MEM_FEATURE_NB MemNDQSTiming3Nb; - #define NB_TRAIN_FLOW_DDR3 MemNDQSTiming3Nb -// extern OPTION_MEM_FEATURE_NB memNSequenceDDR3Nb; - #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR3_ON {MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION,memNSequenceDDR3Nb, memNEnableTrainSequenceON, &memTechTrainingFeatSequenceDDR3ON }, - #else - #undef TECH_TRAIN_ENTER_HW_TRN_DDR3 - #define TECH_TRAIN_ENTER_HW_TRN_DDR3 MemTFeatDef - #undef TECH_TRAIN_EXIT_HW_TRN_DDR3 - #define TECH_TRAIN_EXIT_HW_TRN_DDR3 MemTFeatDef - #define TECH_TRAIN_HW_WL_P1_DDR3 MemTFeatDef - #define TECH_TRAIN_HW_WL_P2_DDR3 MemTFeatDef - #define TECH_TRAIN_SW_WL_DDR3 MemTFeatDef - #define TECH_TRAIN_HW_DQS_REC_EN_P1_DDR3 MemTFeatDef - #define TECH_TRAIN_HW_DQS_REC_EN_P2_DDR3 MemTFeatDef - #define TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR3 MemTFeatDef - #define TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR3 MemTFeatDef - #define TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR3 MemTFeatDef - #define TECH_TRAIN_OPT_SW_RD_WR_POS_DDR3 MemTFeatDef - #define TECH_TRAIN_MAX_RD_LAT_DDR3 MemTFeatDef - #define NB_TRAIN_FLOW_DDR3 (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue - #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR3_ON { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 }, - #endif - #else - #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR2_ON { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 }, - #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR3_ON { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 }, - #endif - - #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_END { MEM_NB_SUPPORT_STRUCT_VERSION, 0, 0, 0 } - MEM_FEAT_TRAIN_SEQ memTrainSequenceDDR2[] = { - MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR2_DR - MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR2_DA - MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR2_HY - MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR2_LN - MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR2_C32 - MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR2_ON - MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR2_Ni - MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR2_OR - MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR2_PH - MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR2_RB - MEM_TECH_ENABLE_TRAINING_SEQUENCE_END - }; - - MEM_FEAT_TRAIN_SEQ memTrainSequenceDDR3[] = { - MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR3_DR - MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR3_DA - MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR3_HY - MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR3_LN - MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR3_C32 - MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR3_ON - MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR3_Ni - MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR3_OR - MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR3_PH - MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR3_RB - MEM_TECH_ENABLE_TRAINING_SEQUENCE_END - }; - /*--------------------------------------------------------------------------------------------------- - * NB TRAINING FLOW CONTROL - * - * - *--------------------------------------------------------------------------------------------------- - */ - OPTION_MEM_FEATURE_NB* memNTrainFlowControl[] = { // Training flow control - NB_TRAIN_FLOW_DDR2, - NB_TRAIN_FLOW_DDR3, - }; - /*--------------------------------------------------------------------------------------------------- - * TECHNOLOGY BLOCK - * - * - *--------------------------------------------------------------------------------------------------- - */ - MEM_TECH_CONSTRUCTOR* memTechInstalled[] = { // Types of technology installed - MEM_TECH_CONSTRUCTOR_DDR2 - MEM_TECH_CONSTRUCTOR_DDR3 - NULL - }; - /*--------------------------------------------------------------------------------------------------- - * PLATFORM SPECIFIC BLOCK FORM FACTOR DEFINITION - * - * - *--------------------------------------------------------------------------------------------------- - */ - #if OPTION_MEMCTLR_HY - #if OPTION_UDIMMS - #if OPTION_DDR2 - #define PLAT_SP_HY_FF_UDIMM2 MemPConstructPsUDef, - #else - #define PLAT_SP_HY_FF_UDIMM2 MemPConstructPsUDef, - #endif - #if OPTION_DDR3 - #define PLAT_SP_HY_FF_UDIMM3 MemPConstructPsUHy3, - #else - #define PLAT_SP_HY_FF_UDIMM3 MemPConstructPsUDef, - #endif - #else - #define PLAT_SP_HY_FF_UDIMM2 MemPConstructPsUDef, - #define PLAT_SP_HY_FF_UDIMM3 MemPConstructPsUDef, - #endif - #if OPTION_RDIMMS - #if OPTION_DDR2 - #define PLAT_SP_HY_FF_RDIMM2 MemPConstructPsUDef, - #else - #define PLAT_SP_HY_FF_RDIMM2 MemPConstructPsUDef, - #endif - #if OPTION_DDR3 - #define PLAT_SP_HY_FF_RDIMM3 MemPConstructPsRHy3, - #else - #define PLAT_SP_HY_FF_RDIMM3 MemPConstructPsUDef, - #endif - #else - #define PLAT_SP_HY_FF_RDIMM2 MemPConstructPsUDef, - #define PLAT_SP_HY_FF_RDIMM3 MemPConstructPsUDef, - #endif - #if OPTION_SODIMMS - #if OPTION_DDR2 - #define PLAT_SP_HY_FF_SDIMM2 MemPConstructPsUDef, - #else - #define PLAT_SP_HY_FF_SDIMM2 MemPConstructPsUDef, - #endif - #if OPTION_DDR3 - #define PLAT_SP_HY_FF_SDIMM3 MemPConstructPsSHy3, - #else - #define PLAT_SP_HY_FF_SDIMM3 MemPConstructPsUDef, - #endif - #else - #define PLAT_SP_HY_FF_SDIMM2 MemPConstructPsUDef, - #define PLAT_SP_HY_FF_SDIMM3 MemPConstructPsUDef, - #endif - #else - #define PLAT_SP_HY_FF_SDIMM2 MemPConstructPsUDef, - #define PLAT_SP_HY_FF_RDIMM2 MemPConstructPsUDef, - #define PLAT_SP_HY_FF_UDIMM2 MemPConstructPsUDef, - #define PLAT_SP_HY_FF_SDIMM3 MemPConstructPsUDef, - #define PLAT_SP_HY_FF_RDIMM3 MemPConstructPsUDef, - #define PLAT_SP_HY_FF_UDIMM3 MemPConstructPsUDef, - #endif - MEM_PLAT_SPEC_CFG* memPlatSpecFFInstalledHy[MAX_FF_TYPES] = { - PLAT_SP_HY_FF_UDIMM2 - PLAT_SP_HY_FF_RDIMM2 - PLAT_SP_HY_FF_SDIMM2 - PLAT_SP_HY_FF_UDIMM3 - PLAT_SP_HY_FF_RDIMM3 - PLAT_SP_HY_FF_SDIMM3 - }; - - #if OPTION_MEMCTLR_DR - #if OPTION_UDIMMS - #if OPTION_DDR2 - extern MEM_PLAT_SPEC_CFG MemPConstructPsUDr2; - #define PLAT_SP_DR_FF_UDIMM2 MemPConstructPsUDr2, - #else - #define PLAT_SP_DR_FF_UDIMM2 MemPConstructPsUDef, - #endif - #if OPTION_DDR3 - #define PLAT_SP_DR_FF_UDIMM3 MemPConstructPsUDr3, - #else - #define PLAT_SP_DR_FF_UDIMM3 MemPConstructPsUDef, - #endif - #else - #define PLAT_SP_DR_FF_UDIMM2 MemPConstructPsUDef, - #define PLAT_SP_DR_FF_UDIMM3 MemPConstructPsUDef, - #endif - #if OPTION_RDIMMS - #if OPTION_DDR2 - extern MEM_PLAT_SPEC_CFG MemPConstructPsRDr2; - #define PLAT_SP_DR_FF_RDIMM2 MemPConstructPsRDr2, - #else - #define PLAT_SP_DR_FF_RDIMM2 MemPConstructPsUDef, - #endif - #if OPTION_DDR3 - #define PLAT_SP_DR_FF_RDIMM3 MemPConstructPsRDr3, - #else - #define PLAT_SP_DR_FF_RDIMM3 MemPConstructPsUDef, - #endif - #else - #define PLAT_SP_DR_FF_RDIMM2 MemPConstructPsUDef, - #define PLAT_SP_DR_FF_RDIMM3 MemPConstructPsUDef, - #endif - #if OPTION_SODIMMS - #if OPTION_DDR2 - #define PLAT_SP_DR_FF_SDIMM2 MemPConstructPsUDef, - #else - #define PLAT_SP_DR_FF_SDIMM2 MemPConstructPsUDef, - #endif - #if OPTION_DDR3 - #define PLAT_SP_DR_FF_SDIMM3 MemPConstructPsSDr3, - #else - #define PLAT_SP_DR_FF_SDIMM3 MemPConstructPsUDef, - #endif - #else - #define PLAT_SP_DR_FF_SDIMM2 MemPConstructPsUDef, - #define PLAT_SP_DR_FF_SDIMM3 MemPConstructPsUDef, - #endif - #else - #define PLAT_SP_DR_FF_SDIMM2 MemPConstructPsUDef, - #define PLAT_SP_DR_FF_RDIMM2 MemPConstructPsUDef, - #define PLAT_SP_DR_FF_UDIMM2 MemPConstructPsUDef, - #define PLAT_SP_DR_FF_SDIMM3 MemPConstructPsUDef, - #define PLAT_SP_DR_FF_RDIMM3 MemPConstructPsUDef, - #define PLAT_SP_DR_FF_UDIMM3 MemPConstructPsUDef, - #endif - MEM_PLAT_SPEC_CFG* memPlatSpecFFInstalledDR[MAX_FF_TYPES] = { - PLAT_SP_DR_FF_UDIMM2 - PLAT_SP_DR_FF_RDIMM2 - PLAT_SP_DR_FF_SDIMM2 - PLAT_SP_DR_FF_UDIMM3 - PLAT_SP_DR_FF_RDIMM3 - PLAT_SP_DR_FF_SDIMM3 - }; - - #if (OPTION_MEMCTLR_DA == TRUE) - #if OPTION_UDIMMS - #if OPTION_DDR2 - #define PLAT_SP_DA_FF_UDIMM2 MemPConstructPsUDef, - #else - #define PLAT_SP_DA_FF_UDIMM2 MemPConstructPsUDef, - #endif - #if OPTION_DDR3 - #define PLAT_SP_DA_FF_UDIMM3 MemPConstructPsUDA3, - #else - #define PLAT_SP_DA_FF_UDIMM3 MemPConstructPsUDef, - #endif - #else - #define PLAT_SP_DA_FF_UDIMM2 MemPConstructPsUDef, - #define PLAT_SP_DA_FF_UDIMM3 MemPConstructPsUDef, - #endif - #if OPTION_RDIMMS - #if OPTION_DDR2 - #define PLAT_SP_DA_FF_RDIMM2 MemPConstructPsUDef, - #else - #define PLAT_SP_DA_FF_RDIMM2 MemPConstructPsUDef, - #endif - #if OPTION_DDR3 - #define PLAT_SP_DA_FF_RDIMM3 MemPConstructPsUDef, - #else - #define PLAT_SP_DA_FF_RDIMM3 MemPConstructPsUDef, - #endif - #else - #define PLAT_SP_DA_FF_RDIMM2 MemPConstructPsUDef, - #define PLAT_SP_DA_FF_RDIMM3 MemPConstructPsUDef, - #endif - #if OPTION_SODIMMS - #if OPTION_DDR2 - #define PLAT_SP_DA_FF_SDIMM2 MemPConstructPsSDA2, - #else - #define PLAT_SP_DA_FF_SDIMM2 MemPConstructPsUDef, - #endif - #if OPTION_DDR3 - #define PLAT_SP_DA_FF_SDIMM3 MemPConstructPsSDA3, - #else - #define PLAT_SP_DA_FF_SDIMM3 MemPConstructPsUDef, - #endif - #else - #define PLAT_SP_DA_FF_SDIMM2 MemPConstructPsUDef, - #define PLAT_SP_DA_FF_SDIMM3 MemPConstructPsUDef, - #endif - #else - #define PLAT_SP_DA_FF_SDIMM2 MemPConstructPsUDef, - #define PLAT_SP_DA_FF_RDIMM2 MemPConstructPsUDef, - #define PLAT_SP_DA_FF_UDIMM2 MemPConstructPsUDef, - #define PLAT_SP_DA_FF_SDIMM3 MemPConstructPsUDef, - #define PLAT_SP_DA_FF_RDIMM3 MemPConstructPsUDef, - #define PLAT_SP_DA_FF_UDIMM3 MemPConstructPsUDef, - #endif - MEM_PLAT_SPEC_CFG* memPlatSpecFFInstalledDA[MAX_FF_TYPES] = { - PLAT_SP_DA_FF_UDIMM2 - PLAT_SP_DA_FF_RDIMM2 - PLAT_SP_DA_FF_SDIMM2 - PLAT_SP_DA_FF_UDIMM3 - PLAT_SP_DA_FF_RDIMM3 - PLAT_SP_DA_FF_SDIMM3 - }; - - #if (OPTION_MEMCTLR_Ni == TRUE) - #define PLAT_SP_NI_FF_SDIMM2 MemPConstructPsUDef, - #define PLAT_SP_NI_FF_RDIMM2 MemPConstructPsUDef, - #define PLAT_SP_NI_FF_UDIMM2 MemPConstructPsUDef, - #define PLAT_SP_NI_FF_SDIMM3 MemPConstructPsSNi3, - #define PLAT_SP_NI_FF_RDIMM3 MemPConstructPsUDef, - #define PLAT_SP_NI_FF_UDIMM3 MemPConstructPsUNi3, - #else - #define PLAT_SP_NI_FF_SDIMM2 MemPConstructPsUDef, - #define PLAT_SP_NI_FF_RDIMM2 MemPConstructPsUDef, - #define PLAT_SP_NI_FF_UDIMM2 MemPConstructPsUDef, - #define PLAT_SP_NI_FF_SDIMM3 MemPConstructPsUDef, - #define PLAT_SP_NI_FF_RDIMM3 MemPConstructPsUDef, - #define PLAT_SP_NI_FF_UDIMM3 MemPConstructPsUDef, - #endif - MEM_PLAT_SPEC_CFG* memPlatSpecFFInstalledNi[MAX_FF_TYPES] = { - PLAT_SP_NI_FF_UDIMM2 - PLAT_SP_NI_FF_RDIMM2 - PLAT_SP_NI_FF_SDIMM2 - PLAT_SP_NI_FF_UDIMM3 - PLAT_SP_NI_FF_RDIMM3 - PLAT_SP_NI_FF_SDIMM3 - }; - - #if (OPTION_MEMCTLR_PH == TRUE) - #define PLAT_SP_PH_FF_SDIMM2 MemPConstructPsUDef, - #define PLAT_SP_PH_FF_RDIMM2 MemPConstructPsUDef, - #define PLAT_SP_PH_FF_UDIMM2 MemPConstructPsUDef, - #define PLAT_SP_PH_FF_SDIMM3 MemPConstructPsSPh3, - #define PLAT_SP_PH_FF_RDIMM3 MemPConstructPsUDef, - #define PLAT_SP_PH_FF_UDIMM3 MemPConstructPsUPh3, - #else - #define PLAT_SP_PH_FF_SDIMM2 MemPConstructPsUDef, - #define PLAT_SP_PH_FF_RDIMM2 MemPConstructPsUDef, - #define PLAT_SP_PH_FF_UDIMM2 MemPConstructPsUDef, - #define PLAT_SP_PH_FF_SDIMM3 MemPConstructPsUDef, - #define PLAT_SP_PH_FF_RDIMM3 MemPConstructPsUDef, - #define PLAT_SP_PH_FF_UDIMM3 MemPConstructPsUDef, - #endif - MEM_PLAT_SPEC_CFG* memPlatSpecFFInstalledPh[MAX_FF_TYPES] = { - PLAT_SP_PH_FF_UDIMM2 - PLAT_SP_PH_FF_RDIMM2 - PLAT_SP_PH_FF_SDIMM2 - PLAT_SP_PH_FF_UDIMM3 - PLAT_SP_PH_FF_RDIMM3 - PLAT_SP_PH_FF_SDIMM3 - }; - - #if (OPTION_MEMCTLR_RB == TRUE) - #define PLAT_SP_RB_FF_SDIMM2 MemPConstructPsUDef, - #define PLAT_SP_RB_FF_RDIMM2 MemPConstructPsUDef, - #define PLAT_SP_RB_FF_UDIMM2 MemPConstructPsUDef, - #define PLAT_SP_RB_FF_SDIMM3 MemPConstructPsSRb3, - #define PLAT_SP_RB_FF_RDIMM3 MemPConstructPsUDef, - #define PLAT_SP_RB_FF_UDIMM3 MemPConstructPsURb3, - #else - #define PLAT_SP_RB_FF_SDIMM2 MemPConstructPsUDef, - #define PLAT_SP_RB_FF_RDIMM2 MemPConstructPsUDef, - #define PLAT_SP_RB_FF_UDIMM2 MemPConstructPsUDef, - #define PLAT_SP_RB_FF_SDIMM3 MemPConstructPsUDef, - #define PLAT_SP_RB_FF_RDIMM3 MemPConstructPsUDef, - #define PLAT_SP_RB_FF_UDIMM3 MemPConstructPsUDef, - #endif - MEM_PLAT_SPEC_CFG* memPlatSpecFFInstalledRb[MAX_FF_TYPES] = { - PLAT_SP_RB_FF_UDIMM2 - PLAT_SP_RB_FF_RDIMM2 - PLAT_SP_RB_FF_SDIMM2 - PLAT_SP_RB_FF_UDIMM3 - PLAT_SP_RB_FF_RDIMM3 - PLAT_SP_RB_FF_SDIMM3 - }; - - #if OPTION_MEMCTLR_LN - #if OPTION_UDIMMS - #if OPTION_DDR3 - #define PLAT_SP_LN_FF_UDIMM3 MemPConstructPsULN3, - #else - #define PLAT_SP_LN_FF_UDIMM3 MemPConstructPsUDef, - #endif - #else - #define PLAT_SP_LN_FF_UDIMM3 MemPConstructPsUDef, - #endif - #if OPTION_SODIMMS - #if OPTION_DDR3 - #define PLAT_SP_LN_FF_SDIMM3 MemPConstructPsSLN3, - #else - #define PLAT_SP_LN_FF_SDIMM3 MemPConstructPsUDef, - #endif - #else - #define PLAT_SP_LN_FF_SDIMM3 MemPConstructPsUDef, - #endif - #else - #define PLAT_SP_LN_FF_SDIMM3 MemPConstructPsUDef, - #define PLAT_SP_LN_FF_UDIMM3 MemPConstructPsUDef, - #endif - MEM_PLAT_SPEC_CFG* memPlatSpecFFInstalledLN[] = { - PLAT_SP_LN_FF_SDIMM3 - PLAT_SP_LN_FF_UDIMM3 - NULL - }; - - #if OPTION_MEMCTLR_C32 - #if OPTION_UDIMMS - #if OPTION_DDR2 - #define PLAT_SP_C32_FF_UDIMM2 MemPConstructPsUDef, - #else - #define PLAT_SP_C32_FF_UDIMM2 MemPConstructPsUDef, - #endif - #if OPTION_DDR3 - #define PLAT_SP_C32_FF_UDIMM3 MemPConstructPsUC32_3, - #else - #define PLAT_SP_C32_FF_UDIMM3 MemPConstructPsUDef, - #endif - #else - #define PLAT_SP_C32_FF_UDIMM2 MemPConstructPsUDef, - #define PLAT_SP_C32_FF_UDIMM3 MemPConstructPsUDef, - #endif - #if OPTION_RDIMMS - #if OPTION_DDR2 - #define PLAT_SP_C32_FF_RDIMM2 MemPConstructPsUDef, - #else - #define PLAT_SP_C32_FF_RDIMM2 MemPConstructPsUDef, - #endif - #if OPTION_DDR3 - #define PLAT_SP_C32_FF_RDIMM3 MemPConstructPsRC32_3, - #else - #define PLAT_SP_C32_FF_RDIMM3 MemPConstructPsUDef, - #endif - #else - #define PLAT_SP_C32_FF_RDIMM2 MemPConstructPsUDef, - #define PLAT_SP_C32_FF_RDIMM3 MemPConstructPsUDef, - #endif - #if OPTION_SODIMMS - #define PLAT_SP_C32_FF_SDIMM2 MemPConstructPsUDef, - #define PLAT_SP_C32_FF_SDIMM3 MemPConstructPsUDef, - #endif - #else - #define PLAT_SP_C32_FF_SDIMM2 MemPConstructPsUDef, - #define PLAT_SP_C32_FF_RDIMM2 MemPConstructPsUDef, - #define PLAT_SP_C32_FF_UDIMM2 MemPConstructPsUDef, - #define PLAT_SP_C32_FF_SDIMM3 MemPConstructPsUDef, - #define PLAT_SP_C32_FF_RDIMM3 MemPConstructPsUDef, - #define PLAT_SP_C32_FF_UDIMM3 MemPConstructPsUDef, - #endif - MEM_PLAT_SPEC_CFG* memPlatSpecFFInstalledC32[MAX_FF_TYPES] = { - PLAT_SP_C32_FF_UDIMM2 - PLAT_SP_C32_FF_RDIMM2 - PLAT_SP_C32_FF_SDIMM2 - PLAT_SP_C32_FF_UDIMM3 - PLAT_SP_C32_FF_RDIMM3 - PLAT_SP_C32_FF_SDIMM3 - }; - - #if OPTION_MEMCTLR_ON - #if OPTION_UDIMMS - #if OPTION_DDR3 - #define PLAT_SP_ON_FF_UDIMM3 MemPConstructPsUON3, - #else - #define PLAT_SP_ON_FF_UDIMM3 MemPConstructPsUDef, - #endif - #else - #define PLAT_SP_ON_FF_UDIMM3 MemPConstructPsUDef, - #endif - #if OPTION_SODIMMS - #if OPTION_DDR3 - #define PLAT_SP_ON_FF_SDIMM3 MemPConstructPsSON3, - #else - #define PLAT_SP_ON_FF_SDIMM3 MemPConstructPsUDef, - #endif - #else - #define PLAT_SP_ON_FF_SDIMM3 MemPConstructPsUDef, - #endif - #else - #define PLAT_SP_ON_FF_SDIMM3 MemPConstructPsUDef, - #define PLAT_SP_ON_FF_UDIMM3 MemPConstructPsUDef, - #endif - MEM_PLAT_SPEC_CFG* memPlatSpecFFInstalledON[] = { - PLAT_SP_ON_FF_SDIMM3 - PLAT_SP_ON_FF_UDIMM3 - NULL - }; - - /*--------------------------------------------------------------------------------------------------- - * PLATFORM-SPECIFIC CONFIGURATION - * - * - *--------------------------------------------------------------------------------------------------- - */ - - #if OPTION_MEMCTLR_DR - #if OPTION_UDIMMS - #if OPTION_DDR2 - #define PSC_DR_UDIMM_DDR2 //MemAGetPsCfgUDr2 - #else - #define PSC_DR_UDIMM_DDR2 - #endif - #if OPTION_DDR3 - #define PSC_DR_UDIMM_DDR3 MemAGetPsCfgUDr3, - #else - #define PSC_DR_UDIMM_DDR3 - #endif - #endif - #if OPTION_RDIMMS - #if OPTION_DDR2 - #define PSC_DR_RDIMM_DDR2 MemAGetPsCfgRDr2, - #else - #define PSC_DR_RDIMM_DDR2 - #endif - #if OPTION_DDR3 - #define PSC_DR_RDIMM_DDR3 MemAGetPsCfgRDr3, - #else - #define PSC_DR_RDIMM_DDR3 - #endif - #endif - #if OPTION_SODIMMS - #if OPTION_DDR2 - #define PSC_DR_SODIMM_DDR2 //MemAGetPsCfgSDr2 - #else - #define PSC_DR_SODIMM_DDR2 - #endif - #if OPTION_DDR3 - #define PSC_DR_SODIMM_DDR3 //MemAGetPsCfgSDr3 - #else - #define PSC_DR_SODIMM_DDR3 - #endif - #endif - #endif - - #if (OPTION_MEMCTLR_DA == TRUE || OPTION_MEMCTLR_Ni == TRUE || OPTION_MEMCTLR_RB == TRUE || OPTION_MEMCTLR_PH == TRUE) - #if OPTION_MEMCTLR_Ni - #define PSC_NI_UDIMM_DDR2 - #define PSC_NI_UDIMM_DDR3 MemAGetPsCfgUNi3, - #define PSC_NI_RDIMM_DDR2 - #define PSC_NI_RDIMM_DDR3 - #define PSC_NI_SODIMM_DDR2 - #define PSC_NI_SODIMM_DDR3 MemAGetPsCfgSNi3, - #endif - #if OPTION_MEMCTLR_PH - #define PSC_PH_UDIMM_DDR2 - #define PSC_PH_UDIMM_DDR3 MemAGetPsCfgUPh3, - #define PSC_PH_RDIMM_DDR2 - #define PSC_PH_RDIMM_DDR3 - #define PSC_PH_SODIMM_DDR2 - #define PSC_PH_SODIMM_DDR3 MemAGetPsCfgSPh3, - #endif - #if OPTION_MEMCTLR_RB - #define PSC_RB_UDIMM_DDR2 - #define PSC_RB_UDIMM_DDR3 MemAGetPsCfgURb3, - #define PSC_RB_RDIMM_DDR2 - #define PSC_RB_RDIMM_DDR3 - #define PSC_RB_SODIMM_DDR2 - #define PSC_RB_SODIMM_DDR3 MemAGetPsCfgSRb3, - #endif - #if OPTION_MEMCTLR_DA - #if OPTION_UDIMMS - #if OPTION_DDR2 - #define PSC_DA_UDIMM_DDR2 //MemAGetPsCfgUDr2 - #else - #define PSC_DA_UDIMM_DDR2 - #endif - #if OPTION_DDR3 - #define PSC_DA_UDIMM_DDR3 MemAGetPsCfgUDA3, - #else - #define PSC_DA_UDIMM_DDR3 - #endif - #endif - #if OPTION_RDIMMS - #if OPTION_DDR2 - #define PSC_DA_RDIMM_DDR2 - #else - #define PSC_DA_RDIMM_DDR2 - #endif - #if OPTION_DDR3 - #define PSC_DA_RDIMM_DDR3 - #else - #define PSC_DA_RDIMM_DDR3 - #endif - #endif - #if OPTION_SODIMMS - #if OPTION_DDR2 - #define PSC_DA_SODIMM_DDR2 MemAGetPsCfgSDA2, - #else - #define PSC_DA_SODIMM_DDR2 - #endif - #if OPTION_DDR3 - #define PSC_DA_SODIMM_DDR3 MemAGetPsCfgSDA3, - #else - #define PSC_DA_SODIMM_DDR3 - #endif - #endif - #endif - #endif - - #if OPTION_MEMCTLR_HY - #if OPTION_UDIMMS - #if OPTION_DDR2 - #define PSC_HY_UDIMM_DDR2 //MemAGetPsCfgUDr2, - #else - #define PSC_HY_UDIMM_DDR2 - #endif - #if OPTION_DDR3 - #define PSC_HY_UDIMM_DDR3 MemAGetPsCfgUHy3, - #else - #define PSC_HY_UDIMM_DDR3 - #endif - #endif - #if OPTION_RDIMMS - #if OPTION_DDR2 - #define PSC_HY_RDIMM_DDR2 - #else - #define PSC_HY_RDIMM_DDR2 - #endif - #if OPTION_DDR3 - #define PSC_HY_RDIMM_DDR3 MemAGetPsCfgRHy3, - #else - #define PSC_HY_RDIMM_DDR3 - #endif - #endif - #if OPTION_SODIMMS - #if OPTION_DDR2 - #define PSC_HY_SODIMM_DDR2 //MemAGetPsCfgSHy2, - #else - #define PSC_HY_SODIMM_DDR2 - #endif - #if OPTION_DDR3 - #define PSC_HY_SODIMM_DDR3 //MemAGetPsCfgSHy3, - #else - #define PSC_HY_SODIMM_DDR3 - #endif - #endif - #endif - - #if OPTION_MEMCTLR_C32 - #if OPTION_UDIMMS - #if OPTION_DDR2 - #define PSC_C32_UDIMM_DDR2 //MemAGetPsCfgUDr2, - #else - #define PSC_C32_UDIMM_DDR2 - #endif - #if OPTION_DDR3 - #define PSC_C32_UDIMM_DDR3 MemAGetPsCfgUC32_3, - #else - #define PSC_C32_UDIMM_DDR3 - #endif - #endif - #if OPTION_RDIMMS - #if OPTION_DDR2 - #define PSC_C32_RDIMM_DDR2 - #else - #define PSC_C32_RDIMM_DDR2 - #endif - #if OPTION_DDR3 - #define PSC_C32_RDIMM_DDR3 MemAGetPsCfgRC32_3, - #else - #define PSC_C32_RDIMM_DDR3 - #endif - #endif - #if OPTION_SODIMMS - #if OPTION_DDR2 - #define PSC_C32_SODIMM_DDR2 //MemAGetPsCfgSC32_2, - #else - #define PSC_C32_SODIMM_DDR2 - #endif - #if OPTION_DDR3 - #define PSC_C32_SODIMM_DDR3 //MemAGetPsCfgSC32_3, - #else - #define PSC_C32_SODIMM_DDR3 - #endif - #endif - #endif - - #if OPTION_MEMCTLR_LN - #if OPTION_UDIMMS - #if OPTION_DDR2 - #define PSC_LN_UDIMM_DDR2 //MemAGetPsCfgULN2, - #else - #define PSC_LN_UDIMM_DDR2 - #endif - #if OPTION_DDR3 - #define PSC_LN_UDIMM_DDR3 MemAGetPsCfgULN3, - #else - #define PSC_LN_UDIMM_DDR3 - #endif - #endif - #if OPTION_RDIMMS - #if OPTION_DDR2 - #define PSC_LN_RDIMM_DDR2 - #else - #define PSC_LN_RDIMM_DDR2 - #endif - #if OPTION_DDR3 - #define PSC_LN_RDIMM_DDR3 //MemAGetPsCfgRLN3, - #else - #define PSC_LN_RDIMM_DDR3 - #endif - #endif - #if OPTION_SODIMMS - #if OPTION_DDR2 - #define PSC_LN_SODIMM_DDR2 //MemAGetPsCfgSLN2, - #else - #define PSC_LN_SODIMM_DDR2 - #endif - #if OPTION_DDR3 - #define PSC_LN_SODIMM_DDR3 MemAGetPsCfgSLN3, - #else - #define PSC_LN_SODIMM_DDR3 - #endif - #endif - #endif - - #if OPTION_MEMCTLR_OR - #if OPTION_UDIMMS - #if OPTION_DDR2 - #define PSC_OR_UDIMM_DDR2 //MemAGetPsCfgUOr2, - #else - #define PSC_OR_UDIMM_DDR2 - #endif - #if OPTION_DDR3 - #define PSC_OR_UDIMM_DDR3 //MemAGetPsCfgUOr3, - #else - #define PSC_OR_UDIMM_DDR3 - #endif - #endif - #if OPTION_RDIMMS - #if OPTION_DDR2 - #define PSC_OR_RDIMM_DDR2 - #else - #define PSC_OR_RDIMM_DDR2 - #endif - #if OPTION_DDR3 - #define PSC_OR_RDIMM_DDR3 //MemAGetPsCfgROr3, - #else - #define PSC_OR_RDIMM_DDR3 - #endif - #endif - #if OPTION_SODIMMS - #if OPTION_DDR2 - #define PSC_OR_SODIMM_DDR2 //MemAGetPsCfgSOr2, - #else - #define PSC_OR_SODIMM_DDR2 - #endif - #if OPTION_DDR3 - #define PSC_OR_SODIMM_DDR3 //MemAGetPsCfgSOr3, - #else - #define PSC_OR_SODIMM_DDR3 - #endif - #endif - #endif - - #if OPTION_MEMCTLR_ON - #if OPTION_UDIMMS - #if OPTION_DDR2 - #define PSC_ON_UDIMM_DDR2 //MemAGetPsCfgUON2, - #else - #define PSC_ON_UDIMM_DDR2 - #endif - #if OPTION_DDR3 - #define PSC_ON_UDIMM_DDR3 MemAGetPsCfgUON3, - #else - #define PSC_ON_UDIMM_DDR3 - #endif - #endif - #if OPTION_RDIMMS - #if OPTION_DDR2 - #define PSC_ON_RDIMM_DDR2 - #else - #define PSC_ON_RDIMM_DDR2 - #endif - #if OPTION_DDR3 - #define PSC_ON_RDIMM_DDR3 //MemAGetPsCfgRON3, - #else - #define PSC_ON_RDIMM_DDR3 - #endif - #endif - #if OPTION_SODIMMS - #if OPTION_DDR2 - #define PSC_ON_SODIMM_DDR2 //MemAGetPsCfgSON2, - #else - #define PSC_ON_SODIMM_DDR2 - #endif - #if OPTION_DDR3 - #define PSC_ON_SODIMM_DDR3 MemAGetPsCfgSON3, - #else - #define PSC_ON_SODIMM_DDR3 - #endif - #endif - #endif - - /*---------------------------------------------------------------------- - * DEFAULT PSCFG DEFINITIONS - * - *---------------------------------------------------------------------- - */ - - #ifndef PSC_DR_UDIMM_DDR2 - #define PSC_DR_UDIMM_DDR2 - #endif - #ifndef PSC_DR_RDIMM_DDR2 - #define PSC_DR_RDIMM_DDR2 - #endif - #ifndef PSC_DR_SODIMM_DDR2 - #define PSC_DR_SODIMM_DDR2 - #endif - #ifndef PSC_DR_UDIMM_DDR3 - #define PSC_DR_UDIMM_DDR3 - #endif - #ifndef PSC_DR_RDIMM_DDR3 - #define PSC_DR_RDIMM_DDR3 - #endif - #ifndef PSC_DR_SODIMM_DDR3 - #define PSC_DR_SODIMM_DDR3 - #endif - #ifndef PSC_RB_UDIMM_DDR2 - #define PSC_RB_UDIMM_DDR2 - #endif - #ifndef PSC_RB_RDIMM_DDR2 - #define PSC_RB_RDIMM_DDR2 - #endif - #ifndef PSC_RB_SODIMM_DDR2 - #define PSC_RB_SODIMM_DDR2 - #endif - #ifndef PSC_RB_UDIMM_DDR3 - #define PSC_RB_UDIMM_DDR3 - #endif - #ifndef PSC_RB_RDIMM_DDR3 - #define PSC_RB_RDIMM_DDR3 - #endif - #ifndef PSC_RB_SODIMM_DDR3 - #define PSC_RB_SODIMM_DDR3 - #endif - #ifndef PSC_DA_UDIMM_DDR2 - #define PSC_DA_UDIMM_DDR2 - #endif - #ifndef PSC_DA_RDIMM_DDR2 - #define PSC_DA_RDIMM_DDR2 - #endif - #ifndef PSC_DA_SODIMM_DDR2 - #define PSC_DA_SODIMM_DDR2 - #endif - #ifndef PSC_DA_UDIMM_DDR3 - #define PSC_DA_UDIMM_DDR3 - #endif - #ifndef PSC_DA_RDIMM_DDR3 - #define PSC_DA_RDIMM_DDR3 - #endif - #ifndef PSC_DA_SODIMM_DDR3 - #define PSC_DA_SODIMM_DDR3 - #endif - #ifndef PSC_NI_UDIMM_DDR2 - #define PSC_NI_UDIMM_DDR2 - #endif - #ifndef PSC_NI_RDIMM_DDR2 - #define PSC_NI_RDIMM_DDR2 - #endif - #ifndef PSC_NI_SODIMM_DDR2 - #define PSC_NI_SODIMM_DDR2 - #endif - #ifndef PSC_NI_UDIMM_DDR3 - #define PSC_NI_UDIMM_DDR3 - #endif - #ifndef PSC_NI_RDIMM_DDR3 - #define PSC_NI_RDIMM_DDR3 - #endif - #ifndef PSC_NI_SODIMM_DDR3 - #define PSC_NI_SODIMM_DDR3 - #endif - #ifndef PSC_PH_UDIMM_DDR2 - #define PSC_PH_UDIMM_DDR2 - #endif - #ifndef PSC_PH_RDIMM_DDR2 - #define PSC_PH_RDIMM_DDR2 - #endif - #ifndef PSC_PH_SODIMM_DDR2 - #define PSC_PH_SODIMM_DDR2 - #endif - #ifndef PSC_PH_UDIMM_DDR3 - #define PSC_PH_UDIMM_DDR3 - #endif - #ifndef PSC_PH_RDIMM_DDR3 - #define PSC_PH_RDIMM_DDR3 - #endif - #ifndef PSC_PH_SODIMM_DDR3 - #define PSC_PH_SODIMM_DDR3 - #endif - #ifndef PSC_HY_UDIMM_DDR2 - #define PSC_HY_UDIMM_DDR2 - #endif - #ifndef PSC_HY_RDIMM_DDR2 - #define PSC_HY_RDIMM_DDR2 - #endif - #ifndef PSC_HY_SODIMM_DDR2 - #define PSC_HY_SODIMM_DDR2 - #endif - #ifndef PSC_HY_UDIMM_DDR3 - #define PSC_HY_UDIMM_DDR3 - #endif - #ifndef PSC_HY_RDIMM_DDR3 - #define PSC_HY_RDIMM_DDR3 - #endif - #ifndef PSC_HY_SODIMM_DDR3 - #define PSC_HY_SODIMM_DDR3 - #endif - #ifndef PSC_LN_UDIMM_DDR2 - #define PSC_LN_UDIMM_DDR2 - #endif - #ifndef PSC_LN_RDIMM_DDR2 - #define PSC_LN_RDIMM_DDR2 - #endif - #ifndef PSC_LN_SODIMM_DDR2 - #define PSC_LN_SODIMM_DDR2 - #endif - #ifndef PSC_LN_UDIMM_DDR3 - #define PSC_LN_UDIMM_DDR3 - #endif - #ifndef PSC_LN_RDIMM_DDR3 - #define PSC_LN_RDIMM_DDR3 - #endif - #ifndef PSC_LN_SODIMM_DDR3 - #define PSC_LN_SODIMM_DDR3 - #endif - #ifndef PSC_OR_UDIMM_DDR2 - #define PSC_OR_UDIMM_DDR2 - #endif - #ifndef PSC_OR_RDIMM_DDR2 - #define PSC_OR_RDIMM_DDR2 - #endif - #ifndef PSC_OR_SODIMM_DDR2 - #define PSC_OR_SODIMM_DDR2 - #endif - #ifndef PSC_OR_UDIMM_DDR3 - #define PSC_OR_UDIMM_DDR3 - #endif - #ifndef PSC_OR_RDIMM_DDR3 - #define PSC_OR_RDIMM_DDR3 - #endif - #ifndef PSC_OR_SODIMM_DDR3 - #define PSC_OR_SODIMM_DDR3 - #endif - #ifndef PSC_C32_UDIMM_DDR3 - #define PSC_C32_UDIMM_DDR3 - #endif - #ifndef PSC_C32_RDIMM_DDR3 - #define PSC_C32_RDIMM_DDR3 - #endif - #ifndef PSC_ON_UDIMM_DDR2 - #define PSC_ON_UDIMM_DDR2 - #endif - #ifndef PSC_ON_RDIMM_DDR2 - #define PSC_ON_RDIMM_DDR2 - #endif - #ifndef PSC_ON_SODIMM_DDR2 - #define PSC_ON_SODIMM_DDR2 - #endif - #ifndef PSC_ON_UDIMM_DDR3 - #define PSC_ON_UDIMM_DDR3 - #endif - #ifndef PSC_ON_RDIMM_DDR3 - #define PSC_ON_RDIMM_DDR3 - #endif - #ifndef PSC_ON_SODIMM_DDR3 - #define PSC_ON_SODIMM_DDR3 - #endif - - MEM_PLATFORM_CFG* memPlatformTypeInstalled[] = { - PSC_DR_UDIMM_DDR2 - PSC_DR_RDIMM_DDR2 - PSC_DR_SODIMM_DDR2 - PSC_DR_UDIMM_DDR3 - PSC_DR_RDIMM_DDR3 - PSC_DR_SODIMM_DDR3 - PSC_RB_UDIMM_DDR3 - PSC_RB_SODIMM_DDR3 - PSC_DA_SODIMM_DDR2 - PSC_DA_UDIMM_DDR3 - PSC_DA_SODIMM_DDR3 - PSC_NI_UDIMM_DDR3 - PSC_NI_SODIMM_DDR3 - PSC_PH_UDIMM_DDR3 - PSC_PH_SODIMM_DDR3 - PSC_HY_UDIMM_DDR3 - PSC_HY_RDIMM_DDR3 - PSC_HY_SODIMM_DDR3 - PSC_LN_UDIMM_DDR3 - PSC_LN_RDIMM_DDR3 - PSC_LN_SODIMM_DDR3 - PSC_OR_UDIMM_DDR3 - PSC_OR_RDIMM_DDR3 - PSC_OR_SODIMM_DDR3 - PSC_C32_UDIMM_DDR3 - PSC_C32_RDIMM_DDR3 - PSC_ON_UDIMM_DDR3 - PSC_ON_RDIMM_DDR3 - PSC_ON_SODIMM_DDR3 - NULL - }; - CONST UINTN SIZE_OF_PLATFORM = (sizeof (memPlatformTypeInstalled) / sizeof (MEM_PLATFORM_CFG*)); -/* SIZE_OF_PLATFORM is not defined when the preprocessor runs - * Removing this test for coreboot. - */ -#if RUN_BROKEN_AGESA_TESTS - #if SIZE_OF_PLATFORM > MAX_PLATFORM_TYPES - #error Size of memPlatformTypeInstalled array larger than MAX_PLATFORM_TYPES - #endif -#endif - - /*--------------------------------------------------------------------------------------------------- - * EXTRACTABLE PLATFORM SPECIFIC CONFIGURATION - * - * - *--------------------------------------------------------------------------------------------------- - */ - #define MEM_PSC_FLOW_BLOCK_END NULL - #define PSC_TBL_END NULL - #define MEM_PSC_FLOW_DEFTRUE (BOOLEAN (*) (MEM_NB_BLOCK*, MEM_PSC_TABLE_BLOCK *)) memDefTrue - - #if OPTION_MEMCTLR_OR - #if OPTION_UDIMMS - #if OPTION_AM3_SOCKET_SUPPORT - extern PSC_TBL_ENTRY MaxFreqTblEntUAM3; - #define PSC_TBL_OR_UDIMM3_MAX_FREQ_AM3 &MaxFreqTblEntUAM3, - extern PSC_TBL_ENTRY DramTermTblEntUAM3; - #define PSC_TBL_OR_UDIMM3_DRAM_TERM_AM3 &DramTermTblEntUAM3, - extern PSC_TBL_ENTRY OdtPat1DTblEntUAM3; - #define PSC_TBL_OR_UDIMM3_ODT_PAT_1D_AM3 &OdtPat1DTblEntUAM3, - extern PSC_TBL_ENTRY OdtPat2DTblEntUAM3; - #define PSC_TBL_OR_UDIMM3_ODT_PAT_2D_AM3 &OdtPat2DTblEntUAM3, - extern PSC_TBL_ENTRY OdtPat3DTblEntUAM3; - #define PSC_TBL_OR_UDIMM3_ODT_PAT_3D_AM3 &OdtPat3DTblEntUAM3, - extern PSC_TBL_ENTRY SAOTblEntUAM3; - #define PSC_TBL_OR_UDIMM3_SAO_AM3 &SAOTblEntUAM3, - extern PSC_TBL_ENTRY ClkDisMapEntUAM3; - #define PSC_TBL_OR_UDIMM3_CLK_DIS_AM3 &ClkDisMapEntUAM3, - #endif - #if OPTION_C32_SOCKET_SUPPORT - extern PSC_TBL_ENTRY MaxFreqTblEntUC32; - #define PSC_TBL_OR_UDIMM3_MAX_FREQ_C32 &MaxFreqTblEntUC32, - extern PSC_TBL_ENTRY DramTermTblEntUC32; - #define PSC_TBL_OR_UDIMM3_DRAM_TERM_C32 &DramTermTblEntUC32, - extern PSC_TBL_ENTRY OdtPat1DTblEntUC32; - #define PSC_TBL_OR_UDIMM3_ODT_PAT_1D_C32 &OdtPat1DTblEntUC32, - extern PSC_TBL_ENTRY OdtPat2DTblEntUC32; - #define PSC_TBL_OR_UDIMM3_ODT_PAT_2D_C32 &OdtPat2DTblEntUC32, - extern PSC_TBL_ENTRY OdtPat3DTblEntUC32; - #define PSC_TBL_OR_UDIMM3_ODT_PAT_3D_C32 &OdtPat3DTblEntUC32, - extern PSC_TBL_ENTRY SAOTblEntUC32; - #define PSC_TBL_OR_UDIMM3_SAO_C32 &SAOTblEntUC32, - extern PSC_TBL_ENTRY ClkDisMapEntUC32; - #define PSC_TBL_OR_UDIMM3_CLK_DIS_C32 &ClkDisMapEntUC32, - extern PSC_TBL_ENTRY ClkDisMap3DEntUC32; - #define PSC_TBL_OR_UDIMM3_CLK_DIS_3D_C32 &ClkDisMap3DEntUC32, - #endif - #if OPTION_G34_SOCKET_SUPPORT - extern PSC_TBL_ENTRY MaxFreqTblEntUG34; - #define PSC_TBL_OR_UDIMM3_MAX_FREQ_G34 &MaxFreqTblEntUG34, - extern PSC_TBL_ENTRY DramTermTblEntUG34; - #define PSC_TBL_OR_UDIMM3_DRAM_TERM_G34 &DramTermTblEntUG34, - extern PSC_TBL_ENTRY OdtPat1DTblEntUG34; - #define PSC_TBL_OR_UDIMM3_ODT_PAT_1D_G34 &OdtPat1DTblEntUG34, - extern PSC_TBL_ENTRY OdtPat2DTblEntUG34; - #define PSC_TBL_OR_UDIMM3_ODT_PAT_2D_G34 &OdtPat2DTblEntUG34, - extern PSC_TBL_ENTRY OdtPat3DTblEntUG34; - #define PSC_TBL_OR_UDIMM3_ODT_PAT_3D_G34 &OdtPat3DTblEntUG34, - extern PSC_TBL_ENTRY SAOTblEntUG34; - #define PSC_TBL_OR_UDIMM3_SAO_G34 &SAOTblEntUG34, - extern PSC_TBL_ENTRY ClkDisMapEntUG34; - #define PSC_TBL_OR_UDIMM3_CLK_DIS_G34 &ClkDisMapEntUG34, - #endif - #endif - #if OPTION_RDIMMS - #if OPTION_C32_SOCKET_SUPPORT - extern PSC_TBL_ENTRY MaxFreqTblEntRC32; - #define PSC_TBL_OR_RDIMM3_MAX_FREQ_C32 &MaxFreqTblEntRC32, - extern PSC_TBL_ENTRY DramTermTblEntRC32; - #define PSC_TBL_OR_RDIMM3_DRAM_TERM_C32 &DramTermTblEntRC32, - extern PSC_TBL_ENTRY OdtPat1DTblEntRC32; - #define PSC_TBL_OR_RDIMM3_ODT_PAT_1D_C32 &OdtPat1DTblEntRC32, - extern PSC_TBL_ENTRY OdtPat2DTblEntRC32; - #define PSC_TBL_OR_RDIMM3_ODT_PAT_2D_C32 &OdtPat2DTblEntRC32, - extern PSC_TBL_ENTRY OdtPat3DTblEntRC32; - #define PSC_TBL_OR_RDIMM3_ODT_PAT_3D_C32 &OdtPat3DTblEntRC32, - extern PSC_TBL_ENTRY SAOTblEntRC32; - #define PSC_TBL_OR_RDIMM3_SAO_C32 &SAOTblEntRC32, - extern PSC_TBL_ENTRY RC2IBTTblEntRC32; - #define PSC_TBL_OR_RDIMM3_RC2IBT_C32 &RC2IBTTblEntRC32, - extern PSC_TBL_ENTRY RC10OpSpdTblEntRC32; - #define PSC_TBL_OR_RDIMM3_RC10OPSPD_C32 &RC10OpSpdTblEntRC32, - extern PSC_TBL_ENTRY ClkDisMapEntRC32; - #define PSC_TBL_OR_RDIMM3_CLK_DIS_C32 &ClkDisMapEntRC32, - #endif - #if OPTION_G34_SOCKET_SUPPORT - extern PSC_TBL_ENTRY MaxFreqTblEntRG34; - #define PSC_TBL_OR_RDIMM3_MAX_FREQ_G34 &MaxFreqTblEntRG34, - extern PSC_TBL_ENTRY DramTermTblEntRG34; - #define PSC_TBL_OR_RDIMM3_DRAM_TERM_G34 &DramTermTblEntRG34, - extern PSC_TBL_ENTRY OdtPat1DTblEntRG34; - #define PSC_TBL_OR_RDIMM3_ODT_PAT_1D_G34 &OdtPat1DTblEntRG34, - extern PSC_TBL_ENTRY OdtPat2DTblEntRG34; - #define PSC_TBL_OR_RDIMM3_ODT_PAT_2D_G34 &OdtPat2DTblEntRG34, - extern PSC_TBL_ENTRY OdtPat3DTblEntRG34; - #define PSC_TBL_OR_RDIMM3_ODT_PAT_3D_G34 &OdtPat3DTblEntRG34, - extern PSC_TBL_ENTRY SAOTblEntRG34; - #define PSC_TBL_OR_RDIMM3_SAO_G34 &SAOTblEntRG34, - extern PSC_TBL_ENTRY RC2IBTTblEntRG34; - #define PSC_TBL_OR_RDIMM3_RC2IBT_G34 &RC2IBTTblEntRG34, - extern PSC_TBL_ENTRY RC10OpSpdTblEntRG34; - #define PSC_TBL_OR_RDIMM3_RC10OPSPD_G34 &RC10OpSpdTblEntRG34, - extern PSC_TBL_ENTRY ClkDisMapEntRG34; - #define PSC_TBL_OR_RDIMM3_CLK_DIS_G34 &ClkDisMapEntRG34, - #endif - #endif - //#if OPTION_SODIMMS - //#endif - //#if OPTION_LRDIMMS - // #if OPTION_C32_SOCKET_SUPPORT - // extern PSC_TBL_ENTRY MaxFreqTblEntLRC32; - // #define PSC_TBL_OR_LRDIMM3_MAX_FREQ_C32 &MaxFreqTblEntLRC32, - // extern PSC_TBL_ENTRY DramTermTblEntLRC32; - // #define PSC_TBL_OR_LRDIMM3_DRAM_TERM_C32 &DramTermTblEntLRC32, - // extern PSC_TBL_ENTRY OdtPat1DTblEntRC32; - // #define PSC_TBL_OR_LRDIMM3_ODT_PAT_1D_C32 &OdtPat1DTblEntLRC32, - // extern PSC_TBL_ENTRY OdtPat2DTblEntRC32; - // #define PSC_TBL_OR_LRDIMM3_ODT_PAT_2D_C32 &OdtPat2DTblEntLRC32, - // extern PSC_TBL_ENTRY OdtPat3DTblEntRC32; - // #define PSC_TBL_OR_LRDIMM3_ODT_PAT_3D_C32 &OdtPat3DTblEntLRC32, - // extern PSC_TBL_ENTRY SAOTblEntRC32; - // #define PSC_TBL_OR_LRDIMM3_SAO_C32 &SAOTblEntLRC32, - // extern PSC_TBL_ENTRY IBTTblEntLRC32; - // #define PSC_TBL_OR_LRDIMM3_IBT_C32 &IBTTblEntLRC32, - // extern PSC_TBL_ENTRY ClkDisMapEntLRC32; - // #define PSC_TBL_OR_LRDIMM3_CLK_DIS_C32 &ClkDisMapEntLRC32, - // #endif - // #if OPTION_G34_SOCKET_SUPPORT - // extern PSC_TBL_ENTRY MaxFreqTblEntLRG34; - // #define PSC_TBL_OR_LRDIMM3_MAX_FREQ_G34 &MaxFreqTblEntLRG34, - // extern PSC_TBL_ENTRY DramTermTblEntLRG34; - // #define PSC_TBL_OR_LRDIMM3_DRAM_TERM_G34 &DramTermTblEntLRG34, - // extern PSC_TBL_ENTRY OdtPat1DTblEntRG34; - // #define PSC_TBL_OR_LRDIMM3_ODT_PAT_1D_G34 &OdtPat1DTblEntLRG34, - // extern PSC_TBL_ENTRY OdtPat2DTblEntRG34; - // #define PSC_TBL_OR_LRDIMM3_ODT_PAT_2D_G34 &OdtPat2DTblEntLRG34, - // extern PSC_TBL_ENTRY OdtPat3DTblEntRG34; - // #define PSC_TBL_OR_LRDIMM3_ODT_PAT_3D_G34 &OdtPat3DTblEntLRG34, - // extern PSC_TBL_ENTRY SAOTblEntRG34; - // #define PSC_TBL_OR_LRDIMM3_SAO_G34 &SAOTblEntLRG34, - // extern PSC_TBL_ENTRY IBTTblEntLRG34; - // #define PSC_TBL_OR_LRDIMM3_IBT_G34 &IBTTblEntLRG34, - // extern PSC_TBL_ENTRY ClkDisMapEntLRG34; - // #define PSC_TBL_OR_LRDIMM3_CLK_DIS_G34 &ClkDisMapEntLRG34, - // #endif - //#endif - extern PSC_TBL_ENTRY MR0WrTblEntry; - #define PSC_TBL_OR_MR0_WR &MR0WrTblEntry, - extern PSC_TBL_ENTRY MR0CLTblEntry; - #define PSC_TBL_OR_MR0_CL &MR0CLTblEntry, - extern PSC_TBL_ENTRY OrDdr3CKETriEnt; - #define PSC_TBL_OR_CKE_TRI &OrDdr3CKETriEnt, - extern PSC_TBL_ENTRY OrDdr3ODTTri3DEnt; - #define PSC_TBL_OR_ODT_TRI_3D &OrDdr3ODTTri3DEnt, - extern PSC_TBL_ENTRY OrDdr3ODTTriEnt; - #define PSC_TBL_OR_ODT_TRI &OrDdr3ODTTriEnt, - extern PSC_TBL_ENTRY OrUDdr3CSTriEnt; - #define PSC_TBL_OR_UDIMM3_CS_TRI &OrUDdr3CSTriEnt, - extern PSC_TBL_ENTRY OrDdr3CSTriEnt; - #define PSC_TBL_OR_CS_TRI &OrDdr3CSTriEnt, - extern PSC_TBL_ENTRY OrLRDdr3ODTTri3DEnt; - #define PSC_TBL_OR_LRDIMM3_ODT_TRI_3D &OrLRDdr3ODTTri3DEnt, - extern PSC_TBL_ENTRY OrLRDdr3ODTTriEnt; - #define PSC_TBL_OR_LRDIMM3_ODT_TRI &OrLRDdr3ODTTriEnt, - - #ifndef PSC_TBL_OR_UDIMM3_MAX_FREQ_AM3 - #define PSC_TBL_OR_UDIMM3_MAX_FREQ_AM3 - #endif - #ifndef PSC_TBL_OR_UDIMM3_MAX_FREQ_C32 - #define PSC_TBL_OR_UDIMM3_MAX_FREQ_C32 - #endif - #ifndef PSC_TBL_OR_UDIMM3_MAX_FREQ_G34 - #define PSC_TBL_OR_UDIMM3_MAX_FREQ_G34 - #endif - #ifndef PSC_TBL_OR_UDIMM3_DRAM_TERM_AM3 - #define PSC_TBL_OR_UDIMM3_DRAM_TERM_AM3 - #endif - #ifndef PSC_TBL_OR_UDIMM3_DRAM_TERM_C32 - #define PSC_TBL_OR_UDIMM3_DRAM_TERM_C32 - #endif - #ifndef PSC_TBL_OR_UDIMM3_DRAM_TERM_G34 - #define PSC_TBL_OR_UDIMM3_DRAM_TERM_G34 - #endif - #ifndef PSC_TBL_OR_UDIMM3_ODT_PAT_1D_AM3 - #define PSC_TBL_OR_UDIMM3_ODT_PAT_1D_AM3 - #endif - #ifndef PSC_TBL_OR_UDIMM3_ODT_PAT_1D_C32 - #define PSC_TBL_OR_UDIMM3_ODT_PAT_1D_C32 - #endif - #ifndef PSC_TBL_OR_UDIMM3_ODT_PAT_1D_G34 - #define PSC_TBL_OR_UDIMM3_ODT_PAT_1D_G34 - #endif - #ifndef PSC_TBL_OR_UDIMM3_ODT_PAT_2D_AM3 - #define PSC_TBL_OR_UDIMM3_ODT_PAT_2D_AM3 - #endif - #ifndef PSC_TBL_OR_UDIMM3_ODT_PAT_2D_C32 - #define PSC_TBL_OR_UDIMM3_ODT_PAT_2D_C32 - #endif - #ifndef PSC_TBL_OR_UDIMM3_ODT_PAT_2D_G34 - #define PSC_TBL_OR_UDIMM3_ODT_PAT_2D_G34 - #endif - #ifndef PSC_TBL_OR_UDIMM3_ODT_PAT_3D_AM3 - #define PSC_TBL_OR_UDIMM3_ODT_PAT_3D_AM3 - #endif - #ifndef PSC_TBL_OR_UDIMM3_ODT_PAT_3D_C32 - #define PSC_TBL_OR_UDIMM3_ODT_PAT_3D_C32 - #endif - #ifndef PSC_TBL_OR_UDIMM3_ODT_PAT_3D_G34 - #define PSC_TBL_OR_UDIMM3_ODT_PAT_3D_G34 - #endif - #ifndef PSC_TBL_OR_UDIMM3_SAO_AM3 - #define PSC_TBL_OR_UDIMM3_SAO_AM3 - #endif - #ifndef PSC_TBL_OR_UDIMM3_SAO_C32 - #define PSC_TBL_OR_UDIMM3_SAO_C32 - #endif - #ifndef PSC_TBL_OR_UDIMM3_SAO_G34 - #define PSC_TBL_OR_UDIMM3_SAO_G34 - #endif - #ifndef PSC_TBL_OR_RDIMM3_MAX_FREQ_AM3 - #define PSC_TBL_OR_RDIMM3_MAX_FREQ_AM3 - #endif - #ifndef PSC_TBL_OR_RDIMM3_MAX_FREQ_C32 - #define PSC_TBL_OR_RDIMM3_MAX_FREQ_C32 - #endif - #ifndef PSC_TBL_OR_RDIMM3_MAX_FREQ_G34 - #define PSC_TBL_OR_RDIMM3_MAX_FREQ_G34 - #endif - #ifndef PSC_TBL_OR_RDIMM3_DRAM_TERM_AM3 - #define PSC_TBL_OR_RDIMM3_DRAM_TERM_AM3 - #endif - #ifndef PSC_TBL_OR_RDIMM3_DRAM_TERM_C32 - #define PSC_TBL_OR_RDIMM3_DRAM_TERM_C32 - #endif - #ifndef PSC_TBL_OR_RDIMM3_DRAM_TERM_G34 - #define PSC_TBL_OR_RDIMM3_DRAM_TERM_G34 - #endif - #ifndef PSC_TBL_OR_RDIMM3_ODT_PAT_1D_AM3 - #define PSC_TBL_OR_RDIMM3_ODT_PAT_1D_AM3 - #endif - #ifndef PSC_TBL_OR_RDIMM3_ODT_PAT_1D_C32 - #define PSC_TBL_OR_RDIMM3_ODT_PAT_1D_C32 - #endif - #ifndef PSC_TBL_OR_RDIMM3_ODT_PAT_1D_G34 - #define PSC_TBL_OR_RDIMM3_ODT_PAT_1D_G34 - #endif - #ifndef PSC_TBL_OR_RDIMM3_ODT_PAT_2D_AM3 - #define PSC_TBL_OR_RDIMM3_ODT_PAT_2D_AM3 - #endif - #ifndef PSC_TBL_OR_RDIMM3_ODT_PAT_2D_C32 - #define PSC_TBL_OR_RDIMM3_ODT_PAT_2D_C32 - #endif - #ifndef PSC_TBL_OR_RDIMM3_ODT_PAT_2D_G34 - #define PSC_TBL_OR_RDIMM3_ODT_PAT_2D_G34 - #endif - #ifndef PSC_TBL_OR_RDIMM3_ODT_PAT_3D_AM3 - #define PSC_TBL_OR_RDIMM3_ODT_PAT_3D_AM3 - #endif - #ifndef PSC_TBL_OR_RDIMM3_ODT_PAT_3D_C32 - #define PSC_TBL_OR_RDIMM3_ODT_PAT_3D_C32 - #endif - #ifndef PSC_TBL_OR_RDIMM3_ODT_PAT_3D_G34 - #define PSC_TBL_OR_RDIMM3_ODT_PAT_3D_G34 - #endif - #ifndef PSC_TBL_OR_RDIMM3_SAO_AM3 - #define PSC_TBL_OR_RDIMM3_SAO_AM3 - #endif - #ifndef PSC_TBL_OR_RDIMM3_SAO_C32 - #define PSC_TBL_OR_RDIMM3_SAO_C32 - #endif - #ifndef PSC_TBL_OR_RDIMM3_SAO_G34 - #define PSC_TBL_OR_RDIMM3_SAO_G34 - #endif - #ifndef PSC_TBL_OR_RDIMM3_RC2IBT_AM3 - #define PSC_TBL_OR_RDIMM3_RC2IBT_AM3 - #endif - #ifndef PSC_TBL_OR_RDIMM3_RC2IBT_C32 - #define PSC_TBL_OR_RDIMM3_RC2IBT_C32 - #endif - #ifndef PSC_TBL_OR_RDIMM3_RC2IBT_G34 - #define PSC_TBL_OR_RDIMM3_RC2IBT_G34 - #endif - #ifndef PSC_TBL_OR_RDIMM3_RC10OPSPD_AM3 - #define PSC_TBL_OR_RDIMM3_RC10OPSPD_AM3 - #endif - #ifndef PSC_TBL_OR_RDIMM3_RC10OPSPD_C32 - #define PSC_TBL_OR_RDIMM3_RC10OPSPD_C32 - #endif - #ifndef PSC_TBL_OR_RDIMM3_RC10OPSPD_G34 - #define PSC_TBL_OR_RDIMM3_RC10OPSPD_G34 - #endif - #ifndef PSC_TBL_OR_LRDIMM3_MAX_FREQ_C32 - #define PSC_TBL_OR_LRDIMM3_MAX_FREQ_C32 - #endif - #ifndef PSC_TBL_OR_LRDIMM3_MAX_FREQ_G34 - #define PSC_TBL_OR_LRDIMM3_MAX_FREQ_G34 - #endif - #ifndef PSC_TBL_OR_LRDIMM3_DRAM_TERM_C32 - #define PSC_TBL_OR_LRDIMM3_DRAM_TERM_C32 - #endif - #ifndef PSC_TBL_OR_LRDIMM3_DRAM_TERM_G34 - #define PSC_TBL_OR_LRDIMM3_DRAM_TERM_G34 - #endif - #ifndef PSC_TBL_OR_LRDIMM3_ODT_PAT_1D_C32 - #define PSC_TBL_OR_LRDIMM3_ODT_PAT_1D_C32 - #endif - #ifndef PSC_TBL_OR_LRDIMM3_ODT_PAT_1D_G34 - #define PSC_TBL_OR_LRDIMM3_ODT_PAT_1D_G34 - #endif - #ifndef PSC_TBL_OR_LRDIMM3_ODT_PAT_2D_C32 - #define PSC_TBL_OR_LRDIMM3_ODT_PAT_2D_C32 - #endif - #ifndef PSC_TBL_OR_LRDIMM3_ODT_PAT_2D_G34 - #define PSC_TBL_OR_LRDIMM3_ODT_PAT_2D_G34 - #endif - #ifndef PSC_TBL_OR_LRDIMM3_ODT_PAT_3D_C32 - #define PSC_TBL_OR_LRDIMM3_ODT_PAT_3D_C32 - #endif - #ifndef PSC_TBL_OR_LRDIMM3_ODT_PAT_3D_G34 - #define PSC_TBL_OR_LRDIMM3_ODT_PAT_3D_G34 - #endif - #ifndef PSC_TBL_OR_LRDIMM3_SAO_C32 - #define PSC_TBL_OR_LRDIMM3_SAO_C32 - #endif - #ifndef PSC_TBL_OR_LRDIMM3_SAO_G34 - #define PSC_TBL_OR_LRDIMM3_SAO_G34 - #endif - #ifndef PSC_TBL_OR_LRDIMM3_IBT_C32 - #define PSC_TBL_OR_LRDIMM3_IBT_C32 - #endif - #ifndef PSC_TBL_OR_LRDIMM3_IBT_G34 - #define PSC_TBL_OR_LRDIMM3_IBT_G34 - #endif - #ifndef PSC_TBL_OR_UDIMM3_CLK_DIS_AM3 - #define PSC_TBL_OR_UDIMM3_CLK_DIS_AM3 - #endif - #ifndef PSC_TBL_OR_UDIMM3_CLK_DIS_C32 - #define PSC_TBL_OR_UDIMM3_CLK_DIS_C32 - #endif - #ifndef PSC_TBL_OR_UDIMM3_CLK_DIS_3D_C32 - #define PSC_TBL_OR_UDIMM3_CLK_DIS_3D_C32 - #endif - #ifndef PSC_TBL_OR_UDIMM3_CLK_DIS_G34 - #define PSC_TBL_OR_UDIMM3_CLK_DIS_G34 - #endif - #ifndef PSC_TBL_OR_RDIMM3_CLK_DIS_C32 - #define PSC_TBL_OR_RDIMM3_CLK_DIS_C32 - #endif - #ifndef PSC_TBL_OR_RDIMM3_CLK_DIS_G34 - #define PSC_TBL_OR_RDIMM3_CLK_DIS_G34 - #endif - #ifndef PSC_TBL_OR_LRDIMM3_CLK_DIS_C32 - #define PSC_TBL_OR_LRDIMM3_CLK_DIS_C32 - #endif - #ifndef PSC_TBL_OR_LRDIMM3_CLK_DIS_G34 - #define PSC_TBL_OR_LRDIMM3_CLK_DIS_G34 - #endif - - PSC_TBL_ENTRY* memPSCTblMaxFreqArrayOR[] = { - PSC_TBL_OR_UDIMM3_MAX_FREQ_AM3 - PSC_TBL_OR_UDIMM3_MAX_FREQ_C32 - PSC_TBL_OR_UDIMM3_MAX_FREQ_G34 - PSC_TBL_OR_RDIMM3_MAX_FREQ_AM3 - PSC_TBL_OR_RDIMM3_MAX_FREQ_C32 - PSC_TBL_OR_RDIMM3_MAX_FREQ_G34 - PSC_TBL_OR_LRDIMM3_MAX_FREQ_C32 - PSC_TBL_OR_LRDIMM3_MAX_FREQ_G34 - PSC_TBL_END - }; - - PSC_TBL_ENTRY* memPSCTblDramTermArrayOR[] = { - PSC_TBL_OR_UDIMM3_DRAM_TERM_AM3 - PSC_TBL_OR_UDIMM3_DRAM_TERM_C32 - PSC_TBL_OR_UDIMM3_DRAM_TERM_G34 - PSC_TBL_OR_RDIMM3_DRAM_TERM_AM3 - PSC_TBL_OR_RDIMM3_DRAM_TERM_C32 - PSC_TBL_OR_RDIMM3_DRAM_TERM_G34 - PSC_TBL_OR_LRDIMM3_DRAM_TERM_C32 - PSC_TBL_OR_LRDIMM3_DRAM_TERM_G34 - PSC_TBL_END - }; - - PSC_TBL_ENTRY* memPSCTblODTPatArrayOR[] = { - PSC_TBL_OR_UDIMM3_ODT_PAT_1D_AM3 - PSC_TBL_OR_UDIMM3_ODT_PAT_2D_AM3 - PSC_TBL_OR_UDIMM3_ODT_PAT_3D_AM3 - PSC_TBL_OR_RDIMM3_ODT_PAT_1D_AM3 - PSC_TBL_OR_RDIMM3_ODT_PAT_2D_AM3 - PSC_TBL_OR_RDIMM3_ODT_PAT_3D_AM3 - PSC_TBL_OR_UDIMM3_ODT_PAT_1D_C32 - PSC_TBL_OR_UDIMM3_ODT_PAT_2D_C32 - PSC_TBL_OR_UDIMM3_ODT_PAT_3D_C32 - PSC_TBL_OR_RDIMM3_ODT_PAT_1D_C32 - PSC_TBL_OR_RDIMM3_ODT_PAT_2D_C32 - PSC_TBL_OR_RDIMM3_ODT_PAT_3D_C32 - PSC_TBL_OR_LRDIMM3_ODT_PAT_1D_C32 - PSC_TBL_OR_LRDIMM3_ODT_PAT_2D_C32 - PSC_TBL_OR_LRDIMM3_ODT_PAT_3D_C32 - PSC_TBL_OR_UDIMM3_ODT_PAT_1D_G34 - PSC_TBL_OR_UDIMM3_ODT_PAT_2D_G34 - PSC_TBL_OR_UDIMM3_ODT_PAT_3D_G34 - PSC_TBL_OR_RDIMM3_ODT_PAT_1D_G34 - PSC_TBL_OR_RDIMM3_ODT_PAT_2D_G34 - PSC_TBL_OR_RDIMM3_ODT_PAT_3D_G34 - PSC_TBL_OR_LRDIMM3_ODT_PAT_1D_G34 - PSC_TBL_OR_LRDIMM3_ODT_PAT_2D_G34 - PSC_TBL_OR_LRDIMM3_ODT_PAT_3D_G34 - PSC_TBL_END - }; - - PSC_TBL_ENTRY* memPSCTblSAOArrayOR[] = { - PSC_TBL_OR_UDIMM3_SAO_AM3 - PSC_TBL_OR_UDIMM3_SAO_C32 - PSC_TBL_OR_UDIMM3_SAO_G34 - PSC_TBL_OR_RDIMM3_SAO_AM3 - PSC_TBL_OR_RDIMM3_SAO_C32 - PSC_TBL_OR_RDIMM3_SAO_G34 - PSC_TBL_OR_LRDIMM3_SAO_C32 - PSC_TBL_OR_LRDIMM3_SAO_G34 - PSC_TBL_END - }; - - PSC_TBL_ENTRY* memPSCTblMR0WRArrayOR[] = { - PSC_TBL_OR_MR0_WR - PSC_TBL_END - }; - - PSC_TBL_ENTRY* memPSCTblMR0CLArrayOR[] = { - PSC_TBL_OR_MR0_CL - PSC_TBL_END - }; - - PSC_TBL_ENTRY* memPSCTblRC2IBTArrayOR[] = { - PSC_TBL_OR_RDIMM3_RC2IBT_AM3 - PSC_TBL_OR_RDIMM3_RC2IBT_C32 - PSC_TBL_OR_RDIMM3_RC2IBT_G34 - PSC_TBL_END - }; - - PSC_TBL_ENTRY* memPSCTblRC10OPSPDArrayOR[] = { - PSC_TBL_OR_RDIMM3_RC10OPSPD_AM3 - PSC_TBL_OR_RDIMM3_RC10OPSPD_C32 - PSC_TBL_OR_RDIMM3_RC10OPSPD_G34 - PSC_TBL_END - }; - - PSC_TBL_ENTRY* memPSCTblLRIBTArrayOR[] = { - PSC_TBL_OR_LRDIMM3_IBT_C32 - PSC_TBL_OR_LRDIMM3_IBT_G34 - PSC_TBL_END - }; - - PSC_TBL_ENTRY* memPSCTblGenArrayOR[] = { - PSC_TBL_OR_UDIMM3_CLK_DIS_AM3 - PSC_TBL_OR_UDIMM3_CLK_DIS_C32 - PSC_TBL_OR_UDIMM3_CLK_DIS_3D_C32 - PSC_TBL_OR_UDIMM3_CLK_DIS_G34 - PSC_TBL_OR_RDIMM3_CLK_DIS_C32 - PSC_TBL_OR_RDIMM3_CLK_DIS_G34 - PSC_TBL_OR_LRDIMM3_CLK_DIS_C32 - PSC_TBL_OR_LRDIMM3_CLK_DIS_G34 - PSC_TBL_OR_CKE_TRI - PSC_TBL_OR_ODT_TRI_3D - PSC_TBL_OR_ODT_TRI - PSC_TBL_OR_LRDIMM3_ODT_TRI_3D - PSC_TBL_OR_LRDIMM3_ODT_TRI - PSC_TBL_OR_UDIMM3_CS_TRI - PSC_TBL_OR_CS_TRI - PSC_TBL_END - }; - - MEM_PSC_TABLE_BLOCK memPSCTblBlockOr = { - (PSC_TBL_ENTRY **)&memPSCTblMaxFreqArrayOR, - (PSC_TBL_ENTRY **)&memPSCTblDramTermArrayOR, - (PSC_TBL_ENTRY **)&memPSCTblODTPatArrayOR, - (PSC_TBL_ENTRY **)&memPSCTblSAOArrayOR, - (PSC_TBL_ENTRY **)&memPSCTblMR0WRArrayOR, - (PSC_TBL_ENTRY **)&memPSCTblMR0CLArrayOR, - (PSC_TBL_ENTRY **)&memPSCTblRC2IBTArrayOR, - (PSC_TBL_ENTRY **)&memPSCTblRC10OPSPDArrayOR, - (PSC_TBL_ENTRY **)&memPSCTblLRIBTArrayOR, - NULL, - NULL, - (PSC_TBL_ENTRY **)&memPSCTblGenArrayOR - }; - - extern MEM_PSC_FLOW MemPGetMaxFreqSupported; - #define PSC_FLOW_OR_MAX_FREQ MemPGetMaxFreqSupported - extern MEM_PSC_FLOW MemPGetRttNomWr; - #define PSC_FLOW_OR_DRAM_TERM MemPGetRttNomWr - extern MEM_PSC_FLOW MemPGetODTPattern; - #define PSC_FLOW_OR_ODT_PATTERN MemPGetODTPattern - extern MEM_PSC_FLOW MemPGetSAO; - #define PSC_FLOW_OR_SAO MemPGetSAO - extern MEM_PSC_FLOW MemPGetMR0WrCL; - #define PSC_FLOW_OR_MR0_WRCL MemPGetMR0WrCL - #if OPTION_RDIMMS - extern MEM_PSC_FLOW MemPGetRC2IBT; - #define PSC_FLOW_OR_RC2_IBT MemPGetRC2IBT - extern MEM_PSC_FLOW MemPGetRC10OpSpd; - #define PSC_FLOW_OR_RC10_OPSPD MemPGetRC10OpSpd - #endif - //#if OPTION_LRDIMMS - //extern MEM_PSC_FLOW MemPGetLRIBT; - //#define PSC_FLOW_OR_LR_IBT MemPGetLRIBT - //extern MEM_PSC_FLOW MemPGetLRNPR; - //#define PSC_FLOW_OR_LR_NPR MemPGetLRNPR - //extern MEM_PSC_FLOW MemPGetLRNLR; - //#define PSC_FLOW_OR_LR_NLR MemPGetLRNLR - //#endif - #ifndef PSC_FLOW_OR_MAX_FREQ - #define PSC_FLOW_OR_MAX_FREQ MEM_PSC_FLOW_DEFTRUE - #endif - #ifndef PSC_FLOW_OR_DRAM_TERM - #define PSC_FLOW_OR_DRAM_TERM MEM_PSC_FLOW_DEFTRUE - #endif - #ifndef PSC_FLOW_OR_ODT_PATTERN - #define PSC_FLOW_OR_ODT_PATTERN MEM_PSC_FLOW_DEFTRUE - #endif - #ifndef PSC_FLOW_OR_SAO - #define PSC_FLOW_OR_SAO MEM_PSC_FLOW_DEFTRUE - #endif - #ifndef PSC_FLOW_OR_MR0_WRCL - #define PSC_FLOW_OR_MR0_WRCL MEM_PSC_FLOW_DEFTRUE - #endif - #ifndef PSC_FLOW_OR_RC2_IBT - #define PSC_FLOW_OR_RC2_IBT MEM_PSC_FLOW_DEFTRUE - #endif - #ifndef PSC_FLOW_OR_RC10_OPSPD - #define PSC_FLOW_OR_RC10_OPSPD MEM_PSC_FLOW_DEFTRUE - #endif - #ifndef PSC_FLOW_OR_LR_IBT - #define PSC_FLOW_OR_LR_IBT MEM_PSC_FLOW_DEFTRUE - #endif - #ifndef PSC_FLOW_OR_LR_NPR - #define PSC_FLOW_OR_LR_NPR MEM_PSC_FLOW_DEFTRUE - #endif - #ifndef PSC_FLOW_OR_LR_NLR - #define PSC_FLOW_OR_LR_NLR MEM_PSC_FLOW_DEFTRUE - #endif - MEM_PSC_FLOW_BLOCK memPlatSpecFlowOR = { - &memPSCTblBlockOr, - PSC_FLOW_OR_MAX_FREQ, - PSC_FLOW_OR_DRAM_TERM, - PSC_FLOW_OR_ODT_PATTERN, - PSC_FLOW_OR_SAO, - PSC_FLOW_OR_MR0_WRCL, - PSC_FLOW_OR_RC2_IBT, - PSC_FLOW_OR_RC10_OPSPD, - PSC_FLOW_OR_LR_IBT, - PSC_FLOW_OR_LR_NPR, - PSC_FLOW_OR_LR_NLR - }; - #define MEM_PSC_FLOW_BLOCK_OR &memPlatSpecFlowOR, - #else - #define MEM_PSC_FLOW_BLOCK_OR - #endif - - - MEM_PSC_FLOW_BLOCK* memPlatSpecFlowArray[] = { - MEM_PSC_FLOW_BLOCK_OR - MEM_PSC_FLOW_BLOCK_END - }; - - /*--------------------------------------------------------------------------------------------------- - * - * LRDIMM CONTROL - * - *--------------------------------------------------------------------------------------------------- - */ - #if (OPTION_LRDIMMS == TRUE) - #if (OPTION_MEMCTLR_OR == TRUE) - extern MEM_TECH_FEAT MemTLrdimmConstructor3; - #define MEM_TECH_FEATURE_LRDIMM_INIT &MemTLrdimmConstructor3 - #else //#if (OPTION_MEMCTLR_OR == FALSE) - #define MEM_TECH_FEATURE_LRDIMM_INIT MemTFeatDef - #endif - #else //#if (OPTION_LRDIMMS == FALSE) - #define MEM_TECH_FEATURE_LRDIMM_INIT MemTFeatDef - #endif - MEM_TECH_LRDIMM memLrdimmSupported = { - MEM_TECH_LRDIMM_STRUCT_VERSION, - MEM_TECH_FEATURE_LRDIMM_INIT - }; -#else - /*--------------------------------------------------------------------------------------------------- - * MAIN FLOW CONTROL - * - * - *--------------------------------------------------------------------------------------------------- - */ - MEM_FLOW_CFG* memFlowControlInstalled[] = { - NULL - }; - /*--------------------------------------------------------------------------------------------------- - * NB TRAINING FLOW CONTROL - * - * - *--------------------------------------------------------------------------------------------------- - */ - OPTION_MEM_FEATURE_NB* memNTrainFlowControl[] = { // Training flow control - NULL - }; - /*--------------------------------------------------------------------------------------------------- - * DEFAULT TECHNOLOGY BLOCK - * - * - *--------------------------------------------------------------------------------------------------- - */ - MEM_TECH_CONSTRUCTOR* memTechInstalled[] = { // Types of technology installed - NULL - }; - - /*--------------------------------------------------------------------------------------------------- - * DEFAULT TECHNOLOGY MAP - * - * - *--------------------------------------------------------------------------------------------------- - */ - UINT8 MemoryTechnologyMap[MAX_SOCKETS_SUPPORTED] = {0, 0, 0, 0, 0, 0, 0, 0}; - - /*--------------------------------------------------------------------------------------------------- - * DEFAULT MAIN FEATURE BLOCK - *--------------------------------------------------------------------------------------------------- - */ - MEM_FEAT_BLOCK_MAIN MemFeatMain = { - 0 - }; - - /*--------------------------------------------------------------------------------------------------- - * DEFAULT NORTHBRIDGE SUPPORT LIST - * - * - *--------------------------------------------------------------------------------------------------- - */ - #if (OPTION_MEMCTLR_DR == TRUE) - #undef MEM_NB_SUPPORT_DR - #define MEM_NB_SUPPORT_DR { MEM_NB_SUPPORT_STRUCT_VERSION, NULL, NULL, NULL, MEM_FEATURE_S3_RESUME_CONSTRUCTOR_DR, MEM_IDENDIMM_DR }, - #endif - #if (OPTION_MEMCTLR_RB == TRUE) - #undef MEM_NB_SUPPORT_RB - #define MEM_NB_SUPPORT_RB { MEM_NB_SUPPORT_STRUCT_VERSION, NULL, NULL, NULL, MEM_FEATURE_S3_RESUME_CONSTRUCTOR_RB, MEM_IDENDIMM_RB }, - #endif - #if (OPTION_MEMCTLR_DA == TRUE) - #undef MEM_NB_SUPPORT_DA - #define MEM_NB_SUPPORT_DA { MEM_NB_SUPPORT_STRUCT_VERSION, NULL, NULL, NULL, MEM_FEATURE_S3_RESUME_CONSTRUCTOR_DA, MEM_IDENDIMM_DA }, - #endif - #if (OPTION_MEMCTLR_PH == TRUE) - #undef MEM_NB_SUPPORT_PH - #define MEM_NB_SUPPORT_PH { MEM_NB_SUPPORT_STRUCT_VERSION, NULL, NULL, NULL, MEM_FEATURE_S3_RESUME_CONSTRUCTOR_PH, MEM_IDENDIMM_PH }, - #endif - #if (OPTION_MEMCTLR_HY == TRUE) - #undef MEM_NB_SUPPORT_HY - #define MEM_NB_SUPPORT_HY { MEM_NB_SUPPORT_STRUCT_VERSION, NULL, NULL, NULL, MEM_FEATURE_S3_RESUME_CONSTRUCTOR_HY, MEM_IDENDIMM_HY }, - #endif - #if (OPTION_MEMCTLR_C32 == TRUE) - #undef MEM_NB_SUPPORT_C32 - #define MEM_NB_SUPPORT_C32 { MEM_NB_SUPPORT_STRUCT_VERSION, NULL, NULL, NULL, MEM_FEATURE_S3_RESUME_CONSTRUCTOR_C32, MEM_IDENDIMM_C32 }, - #endif - #if (OPTION_MEMCTLR_LN == TRUE) - #undef MEM_NB_SUPPORT_LN - #define MEM_NB_SUPPORT_LN { MEM_NB_SUPPORT_STRUCT_VERSION, NULL, NULL, NULL, MEM_FEATURE_S3_RESUME_CONSTRUCTOR_LN, MEM_IDENDIMM_LN }, - #endif - #if (OPTION_MEMCTLR_ON == TRUE) - #undef MEM_NB_SUPPORT_ON - #define MEM_NB_SUPPORT_ON { MEM_NB_SUPPORT_STRUCT_VERSION, NULL, NULL, NULL, MEM_FEATURE_S3_RESUME_CONSTRUCTOR_ON, MEM_IDENDIMM_ON }, - #endif - #if (OPTION_MEMCTLR_OR == TRUE) - #undef MEM_NB_SUPPORT_OR - #define MEM_NB_SUPPORT_OR { MEM_NB_SUPPORT_STRUCT_VERSION, NULL, NULL, NULL, MEM_FEATURE_S3_RESUME_CONSTRUCTOR_OR, MEM_IDENDIMM_OR }, - #endif - /*--------------------------------------------------------------------------------------------------- - * DEFAULT Technology Training - * - * - *--------------------------------------------------------------------------------------------------- - */ - #if OPTION_DDR2 - MEM_TECH_FEAT_BLOCK memTechTrainingFeatDDR2 = { - 0 - }; - MEM_FEAT_TRAIN_SEQ memTrainSequenceDDR2[] = { - { 0 } - }; - #endif - #if OPTION_DDR3 - MEM_TECH_FEAT_BLOCK memTechTrainingFeatDDR3 = { - 0 - }; - MEM_FEAT_TRAIN_SEQ memTrainSequenceDDR3[] = { - { 0 } - }; - #endif - /*--------------------------------------------------------------------------------------------------- - * DEFAULT Platform Specific list - * - * - *--------------------------------------------------------------------------------------------------- - */ - #if (OPTION_MEMCTLR_DR == TRUE) - MEM_PLAT_SPEC_CFG* memPlatSpecFFInstalledDr[MAX_FF_TYPES] = { - NULL - }; - #endif - #if (OPTION_MEMCTLR_RB == TRUE) - MEM_PLAT_SPEC_CFG* memPlatSpecFFInstalledRb[MAX_FF_TYPES] = { - NULL - }; - #endif - #if (OPTION_MEMCTLR_DA == TRUE) - MEM_PLAT_SPEC_CFG* memPlatSpecFFInstalledDA[MAX_FF_TYPES] = { - NULL - }; - #endif - #if (OPTION_MEMCTLR_Ni == TRUE) - MEM_PLAT_SPEC_CFG* memPlatSpecFFInstalledNi[MAX_FF_TYPES] = { - NULL - }; - #endif - #if (OPTION_MEMCTLR_PH == TRUE) - MEM_PLAT_SPEC_CFG* memPlatSpecFFInstalledPh[MAX_FF_TYPES] = { - NULL - }; - #endif - #if (OPTION_MEMCTLR_LN == TRUE) - MEM_PLAT_SPEC_CFG* memPlatSpecFFInstalledLN[MAX_FF_TYPES] = { - NULL - }; - #endif - #if (OPTION_MEMCTLR_HY == TRUE) - MEM_PLAT_SPEC_CFG* memPlatSpecFFInstalledHy[MAX_FF_TYPES] = { - NULL - }; - #endif - #if (OPTION_MEMCTLR_OR == TRUE) - MEM_PLAT_SPEC_CFG* memPlatSpecFFInstalledOr[MAX_FF_TYPES] = { - NULL - }; - #endif - #if (OPTION_MEMCTLR_C32 == TRUE) - MEM_PLAT_SPEC_CFG* memPlatSpecFFInstalledC32[MAX_FF_TYPES] = { - NULL - }; - #endif - #if (OPTION_MEMCTLR_ON == TRUE) - MEM_PLAT_SPEC_CFG* memPlatSpecFFInstalledON[MAX_FF_TYPES] = { - NULL - }; - #endif - /*---------------------------------------------------------------------- - * DEFAULT PSCFG DEFINITIONS - * - *---------------------------------------------------------------------- - */ - MEM_PLATFORM_CFG* memPlatformTypeInstalled[] = { - NULL - }; - - /*---------------------------------------------------------------------- - * EXTRACTABLE PLATFORM SPECIFIC CONFIGURATION - * - *---------------------------------------------------------------------- - */ - MEM_PSC_FLOW_BLOCK* memPlatSpecFlowArray[] = { - NULL - }; - - MEM_TECH_LRDIMM memLrdimmSupported = { - MEM_TECH_LRDIMM_STRUCT_VERSION, - NULL - }; -#endif - -/*--------------------------------------------------------------------------------------------------- - * NORTHBRIDGE SUPPORT LIST - * - * - *--------------------------------------------------------------------------------------------------- - */ -MEM_NB_SUPPORT memNBInstalled[] = { - MEM_NB_SUPPORT_RB - MEM_NB_SUPPORT_DA - MEM_NB_SUPPORT_Ni - MEM_NB_SUPPORT_PH - MEM_NB_SUPPORT_HY - MEM_NB_SUPPORT_LN - MEM_NB_SUPPORT_OR - MEM_NB_SUPPORT_C32 - MEM_NB_SUPPORT_ON - MEM_NB_SUPPORT_END -}; - -#endif // _OPTION_MEMORY_INSTALL_H_ diff --git a/src/vendorcode/amd/agesa/f12/Config/OptionMsgBasedC1eInstall.h b/src/vendorcode/amd/agesa/f12/Config/OptionMsgBasedC1eInstall.h deleted file mode 100644 index 7476e16358..0000000000 --- a/src/vendorcode/amd/agesa/f12/Config/OptionMsgBasedC1eInstall.h +++ /dev/null @@ -1,116 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * Install of build option: Message-Based C1e - * - * Contains AMD AGESA install macros and test conditions. Output is the - * defaults tables reflecting the User's build options selection. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: Options - * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $ - */ -/***************************************************************************** - * - * Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ***************************************************************************/ - -#ifndef _OPTION_MSG_BASED_C1E_INSTALL_H_ -#define _OPTION_MSG_BASED_C1E_INSTALL_H_ - -#include "cpuMsgBasedC1e.h" - -/* This option is designed to be included into the platform solution install - * file. The platform solution install file will define the options status. - * Check to validate the definition - */ -#define OPTION_MSG_BASED_C1E_FEAT -#define F10_MSG_BASED_C1E_SUPPORT -#define F15_MSG_BASED_C1E_SUPPORT -#if OPTION_MSG_BASED_C1E == TRUE - #if (AGESA_ENTRY_INIT_EARLY == TRUE) || (AGESA_ENTRY_INIT_POST == TRUE) || (AGESA_ENTRY_INIT_RESUME == TRUE) - - #ifdef OPTION_FAMILY10H - #if OPTION_FAMILY10H == TRUE - #if OPTION_FAMILY10H_HY == TRUE - #if (OPTION_G34_SOCKET_SUPPORT == TRUE) || (OPTION_C32_SOCKET_SUPPORT == TRUE) - extern CONST CPU_FEATURE_DESCRIPTOR ROMDATA CpuFeatureMsgBasedC1e; - #undef OPTION_MSG_BASED_C1E_FEAT - #define OPTION_MSG_BASED_C1E_FEAT &CpuFeatureMsgBasedC1e, - #endif - #endif - #endif - #endif - - #ifdef OPTION_FAMILY15H - #if OPTION_FAMILY15H == TRUE - #if (OPTION_G34_SOCKET_SUPPORT == TRUE) || (OPTION_C32_SOCKET_SUPPORT == TRUE || OPTION_AM3_SOCKET_SUPPORT == TRUE) - extern CONST CPU_FEATURE_DESCRIPTOR ROMDATA CpuFeatureMsgBasedC1e; - #undef OPTION_MSG_BASED_C1E_FEAT - #define OPTION_MSG_BASED_C1E_FEAT &CpuFeatureMsgBasedC1e, - #endif - #endif - #endif - - #ifdef OPTION_FAMILY10H - #if OPTION_FAMILY10H == TRUE - #if OPTION_FAMILY10H_HY == TRUE - #if (OPTION_G34_SOCKET_SUPPORT == TRUE) || (OPTION_C32_SOCKET_SUPPORT == TRUE) - extern CONST MSG_BASED_C1E_FAMILY_SERVICES ROMDATA F10MsgBasedC1e; - #undef F10_MSG_BASED_C1E_SUPPORT - #define F10_MSG_BASED_C1E_SUPPORT {AMD_FAMILY_10_HY, &F10MsgBasedC1e}, - #endif - #endif - #endif - #endif - - #ifdef OPTION_FAMILY15H - #if OPTION_FAMILY15H == TRUE - #if (OPTION_G34_SOCKET_SUPPORT == TRUE) || (OPTION_C32_SOCKET_SUPPORT == TRUE || OPTION_AM3_SOCKET_SUPPORT == TRUE) - extern CONST MSG_BASED_C1E_FAMILY_SERVICES ROMDATA F15OrMsgBasedC1e; - #undef F15_MSG_BASED_C1E_SUPPORT - #define F15_MSG_BASED_C1E_SUPPORT {AMD_FAMILY_15, &F15OrMsgBasedC1e}, - #endif - #endif - #endif - - CONST CPU_SPECIFIC_SERVICES_XLAT ROMDATA MsgBasedC1eFamilyServiceArray[] = - { - F10_MSG_BASED_C1E_SUPPORT - F15_MSG_BASED_C1E_SUPPORT - {0, NULL} - }; - CONST CPU_FAMILY_SUPPORT_TABLE ROMDATA MsgBasedC1eFamilyServiceTable = - { - (sizeof (MsgBasedC1eFamilyServiceArray) / sizeof (CPU_SPECIFIC_SERVICES_XLAT)), - &MsgBasedC1eFamilyServiceArray[0] - }; - #endif -#endif -#endif // _OPTION_MSG_BASED_C1E_INSTALL_H_ diff --git a/src/vendorcode/amd/agesa/f12/Config/OptionMultiSocketInstall.h b/src/vendorcode/amd/agesa/f12/Config/OptionMultiSocketInstall.h deleted file mode 100644 index 3c87677fe9..0000000000 --- a/src/vendorcode/amd/agesa/f12/Config/OptionMultiSocketInstall.h +++ /dev/null @@ -1,94 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * Install of build option: Multiple Socket Support - * - * Contains AMD AGESA install macros and test conditions. Output is the - * defaults tables reflecting the User's build options selection. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: Options - * @e \$Revision: 48937 $ @e \$Date: 2011-03-15 03:37:15 +0800 (Tue, 15 Mar 2011) $ - */ -/***************************************************************************** - * - * Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ***************************************************************************/ - -#ifndef _OPTION_MULTISOCKET_INSTALL_H_ -#define _OPTION_MULTISOCKET_INSTALL_H_ - -/* This option is designed to be included into the platform solution install - * file. The platform solution install file will define the options status. - * Check to validate the definition - */ -#ifndef OPTION_MULTISOCKET - #error BLDOPT: Option not defined: "OPTION_MULTISOCKET" -#endif - -#if OPTION_MULTISOCKET == TRUE - OPTION_MULTISOCKET_PM_STEPS GetNumberOfSystemPmStepsPtrMulti; - #define GET_NUM_PM_STEPS GetNumberOfSystemPmStepsPtrMulti - OPTION_MULTISOCKET_PM_CORE0_TASK RunCodeOnAllSystemCore0sMulti; - #define CORE0_PM_TASK RunCodeOnAllSystemCore0sMulti - OPTION_MULTISOCKET_PM_NB_COF GetSystemNbCofMulti; - #define GET_SYS_NB_COF GetSystemNbCofMulti - OPTION_MULTISOCKET_PM_NB_COF_UPDATE GetSystemNbCofVidUpdateMulti; - #define GET_SYS_NB_COF_UPDATE GetSystemNbCofVidUpdateMulti - OPTION_MULTISOCKET_PM_GET_EVENTS GetEarlyPmErrorsMulti; - #define GET_EARLY_PM_ERRORS GetEarlyPmErrorsMulti - OPTION_MULTISOCKET_PM_NB_MIN_COF GetMinNbCofMulti; - #define GET_MIN_NB_COF GetMinNbCofMulti -#else - OPTION_MULTISOCKET_PM_STEPS GetNumberOfSystemPmStepsPtrSingle; - #define GET_NUM_PM_STEPS GetNumberOfSystemPmStepsPtrSingle - OPTION_MULTISOCKET_PM_CORE0_TASK RunCodeOnAllSystemCore0sSingle; - #define CORE0_PM_TASK RunCodeOnAllSystemCore0sSingle - OPTION_MULTISOCKET_PM_NB_COF GetSystemNbCofSingle; - #define GET_SYS_NB_COF GetSystemNbCofSingle - OPTION_MULTISOCKET_PM_NB_COF_UPDATE GetSystemNbCofVidUpdateSingle; - #define GET_SYS_NB_COF_UPDATE GetSystemNbCofVidUpdateSingle - OPTION_MULTISOCKET_PM_GET_EVENTS GetEarlyPmErrorsSingle; - #define GET_EARLY_PM_ERRORS GetEarlyPmErrorsSingle - OPTION_MULTISOCKET_PM_NB_MIN_COF GetMinNbCofSingle; - #define GET_MIN_NB_COF GetMinNbCofSingle -#endif - -/* Declare the instance of the DMI option configuration structure */ -OPTION_MULTISOCKET_CONFIGURATION OptionMultiSocketConfiguration = { - MULTISOCKET_STRUCT_VERSION, - GET_NUM_PM_STEPS, - CORE0_PM_TASK, - GET_SYS_NB_COF, - GET_SYS_NB_COF_UPDATE, - GET_EARLY_PM_ERRORS, - GET_MIN_NB_COF -}; - -#endif // _OPTION_MULTISOCKET_INSTALL_H_ diff --git a/src/vendorcode/amd/agesa/f12/Config/OptionPreserveMailboxInstall.h b/src/vendorcode/amd/agesa/f12/Config/OptionPreserveMailboxInstall.h deleted file mode 100644 index 10ea6a74b1..0000000000 --- a/src/vendorcode/amd/agesa/f12/Config/OptionPreserveMailboxInstall.h +++ /dev/null @@ -1,122 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * Install of build option: Preserve Mailbox - * - * Contains AMD AGESA install macros and test conditions. Output is the - * defaults tables reflecting the User's build options selection. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: Options - * @e \$Revision: 50096 $ @e \$Date: 2011-04-02 06:17:10 +0800 (Sat, 02 Apr 2011) $ - */ -/***************************************************************************** - * - * Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ***************************************************************************/ - -#ifndef _OPTION_PRESERVE_MAILBOX_INSTALL_H_ -#define _OPTION_PRESERVE_MAILBOX_INSTALL_H_ - -#include "PreserveMailbox.h" - -/* This option is designed to be included into the platform solution install - * file. The platform solution install file will define the options status. - * Check to validate the definition - */ -#define OPTION_PRESERVE_MAILBOX_FEAT -#define F10_PRESERVE_MAILBOX_SUPPORT -#define F15_PRESERVE_MAILBOX_SUPPORT - -#if ((AGESA_ENTRY_INIT_EARLY == TRUE) || (AGESA_ENTRY_INIT_POST == TRUE)) - #if ((OPTION_FAMILY10H == TRUE) || (OPTION_FAMILY15H == TRUE)) - extern CONST CPU_FEATURE_DESCRIPTOR ROMDATA CpuFeaturePreserveAroundMailbox; - #undef OPTION_PRESERVE_MAILBOX_FEAT - #define OPTION_PRESERVE_MAILBOX_FEAT &CpuFeaturePreserveAroundMailbox, - #endif - #if OPTION_FAMILY10H == TRUE - CONST PRESERVE_MAILBOX_FAMILY_REGISTER ROMDATA F10PreserveMailboxRegisters [] = { - { - MAKE_SBDFO (0, 0, 0, 3, 0x168), - 0x00000FFF - }, - { - MAKE_SBDFO (0, 0, 0, 3, 0x170), - 0x00000FFF - }, - { - ILLEGAL_SBDFO, - 0 - } - }; - CONST PRESERVE_MAILBOX_FAMILY_SERVICES ROMDATA F10PreserveMailboxServices = { - 0, - TRUE, - (PRESERVE_MAILBOX_FAMILY_REGISTER *)&F10PreserveMailboxRegisters - }; - #undef F10_PRESERVE_MAILBOX_SUPPORT - #define F10_PRESERVE_MAILBOX_SUPPORT {AMD_FAMILY_10, &F10PreserveMailboxServices}, - #endif - #if OPTION_FAMILY15H == TRUE - CONST PRESERVE_MAILBOX_FAMILY_REGISTER ROMDATA F15PreserveMailboxRegisters [] = { - { - MAKE_SBDFO (0, 0, 0, 3, 0x168), - 0x00000FFF - }, - { - MAKE_SBDFO (0, 0, 0, 3, 0x170), - 0x00000FFF - }, - { - ILLEGAL_SBDFO, - 0 - } - }; - CONST PRESERVE_MAILBOX_FAMILY_SERVICES ROMDATA F15PreserveMailboxServices = { - 0, - TRUE, - (PRESERVE_MAILBOX_FAMILY_REGISTER *)&F15PreserveMailboxRegisters - }; - #undef F15_PRESERVE_MAILBOX_SUPPORT - #define F15_PRESERVE_MAILBOX_SUPPORT {AMD_FAMILY_15, &F15PreserveMailboxServices}, - #endif - CONST CPU_SPECIFIC_SERVICES_XLAT ROMDATA PreserveMailboxFamilyServiceArray[] = - { - F10_PRESERVE_MAILBOX_SUPPORT - F15_PRESERVE_MAILBOX_SUPPORT - {0, NULL} - }; - CONST CPU_FAMILY_SUPPORT_TABLE ROMDATA PreserveMailboxFamilyServiceTable = - { - (sizeof (PreserveMailboxFamilyServiceArray) / sizeof (CPU_SPECIFIC_SERVICES_XLAT)), - &PreserveMailboxFamilyServiceArray[0] - }; -#endif - -#endif // _OPTION_PRESERVE_MAILBOX_INSTALL_H_ diff --git a/src/vendorcode/amd/agesa/f12/Config/OptionPstateInstall.h b/src/vendorcode/amd/agesa/f12/Config/OptionPstateInstall.h deleted file mode 100644 index 7d6433db31..0000000000 --- a/src/vendorcode/amd/agesa/f12/Config/OptionPstateInstall.h +++ /dev/null @@ -1,254 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * Install of build option: PState - * - * Contains AMD AGESA install macros and test conditions. Output is the - * defaults tables reflecting the User's build options selection. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: Options - * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $ - */ -/***************************************************************************** - * - * Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ***************************************************************************/ - -#ifndef _OPTION_PSTATE_INSTALL_H_ -#define _OPTION_PSTATE_INSTALL_H_ - -#include "cpuPstateTables.h" - -/* This option is designed to be included into the platform solution install - * file. The platform solution install file will define the options status. - * Check to validate the definition - */ - -#define F10_PSTATE_SERVICE_SUPPORT -#define F12_PSTATE_SERVICE_SUPPORT -#define F14_PSTATE_SERVICE_SUPPORT -#define F15_OR_PSTATE_SERVICE_SUPPORT -#define F15_TN_PSTATE_SERVICE_SUPPORT - - -#if ((AGESA_ENTRY_INIT_LATE == TRUE) || (AGESA_ENTRY_INIT_POST == TRUE)) - // - //Define Pstate CPU Family service - // - #ifdef OPTION_FAMILY10H - #if OPTION_FAMILY10H == TRUE - extern CONST PSTATE_CPU_FAMILY_SERVICES ROMDATA F10PstateServices; - #undef F10_PSTATE_SERVICE_SUPPORT - #define F10_PSTATE_SERVICE_SUPPORT {AMD_FAMILY_10, &F10PstateServices}, - #endif - #endif - - #ifdef OPTION_FAMILY12H - #if OPTION_FAMILY12H == TRUE - extern CONST PSTATE_CPU_FAMILY_SERVICES ROMDATA F12PstateServices; - #undef F12_PSTATE_SERVICE_SUPPORT - #define F12_PSTATE_SERVICE_SUPPORT {AMD_FAMILY_12, &F12PstateServices}, - #endif - #endif - - #ifdef OPTION_FAMILY14H - #if OPTION_FAMILY14H == TRUE - extern CONST PSTATE_CPU_FAMILY_SERVICES ROMDATA F14PstateServices; - #undef F14_PSTATE_SERVICE_SUPPORT - #define F14_PSTATE_SERVICE_SUPPORT {AMD_FAMILY_14, &F14PstateServices}, - #endif - #endif - - #ifdef OPTION_FAMILY15H - #if OPTION_FAMILY15H == TRUE - #ifdef OPTION_FAMILY15H_OR - #if OPTION_FAMILY15H_OR == TRUE - extern CONST PSTATE_CPU_FAMILY_SERVICES ROMDATA F15OrPstateServices; - #undef F15_OR_PSTATE_SERVICE_SUPPORT - #define F15_OR_PSTATE_SERVICE_SUPPORT {AMD_FAMILY_15_OR, &F15OrPstateServices}, - #endif - #endif - #ifdef OPTION_FAMILY15H_TN - #if OPTION_FAMILY15H_TN == TRUE - extern CONST PSTATE_CPU_FAMILY_SERVICES ROMDATA F15TnPstateServices; - #undef F15_TN_PSTATE_SERVICE_SUPPORT - #define F15_TN_PSTATE_SERVICE_SUPPORT {AMD_FAMILY_15_TN, &F15TnPstateServices}, - #endif - #endif - #endif - #endif - // - //Define ACPI Pstate objects. - // - #ifndef OPTION_ACPI_PSTATES - #error BLDOPT: Option not defined: "OPTION_ACPI_PSTATES" - #endif - #if (OPTION_ACPI_PSTATES == TRUE) -// OPTION_SSDT_FEATURE GenerateSsdt; - #define USER_SSDT_MAIN GenerateSsdt - #ifndef OPTION_MULTISOCKET - #error BLDOPT: Option not defined: "OPTION_MULTISOCKET" - #endif - -// OPTION_ACPI_FEATURE CreatePStateAcpiTables; - OPTION_PSTATE_GATHER PStateGatherMain; - #if ((OPTION_MULTISOCKET == TRUE) && (AGESA_ENTRY_INIT_POST == TRUE)) - OPTION_PSTATE_LEVELING PStateLevelingMain; - #define USER_PSTATE_OPTION_LEVEL PStateLevelingMain - #else - OPTION_PSTATE_LEVELING PStateLevelingStub; - #define USER_PSTATE_OPTION_LEVEL PStateLevelingStub - #endif - #if AGESA_ENTRY_INIT_LATE == TRUE - #define USER_PSTATE_OPTION_MAIN CreatePStateAcpiTables - #else -// OPTION_ACPI_FEATURE CreateAcpiTablesStub; - #define USER_PSTATE_OPTION_MAIN CreateAcpiTablesStub - #endif - #if AGESA_ENTRY_INIT_POST == TRUE - #define USER_PSTATE_OPTION_GATHER PStateGatherMain - #else - OPTION_PSTATE_GATHER PStateGatherStub; - #define USER_PSTATE_OPTION_GATHER PStateGatherStub - #endif - #if CFG_ACPI_PSTATES_PPC == TRUE - #define USER_PSTATE_CFG_PPC TRUE - #else - #define USER_PSTATE_CFG_PPC FALSE - #endif - #if CFG_ACPI_PSTATES_PCT == TRUE - #define USER_PSTATE_CFG_PCT TRUE - #else - #define USER_PSTATE_CFG_PCT FALSE - #endif - #if CFG_ACPI_PSTATES_PSD == TRUE - #define USER_PSTATE_CFG_PSD TRUE - #else - #define USER_PSTATE_CFG_PSD FALSE - #endif - #if CFG_ACPI_PSTATES_PSS == TRUE - #define USER_PSTATE_CFG_PSS TRUE - #else - #define USER_PSTATE_CFG_PSS FALSE - #endif - #if CFG_ACPI_PSTATES_XPSS == TRUE - #define USER_PSTATE_CFG_XPSS TRUE - #else - #define USER_PSTATE_CFG_XPSS FALSE - #endif - - #if OPTION_IO_CSTATE == TRUE -// OPTION_ACPI_FEATURE CreateCStateAcpiTables; - #define USER_CSTATE_OPTION_MAIN CreateCStateAcpiTables - #else - OPTION_ACPI_FEATURE CreateAcpiTablesStub; - #define USER_CSTATE_OPTION_MAIN CreateAcpiTablesStub - #endif - #else - OPTION_SSDT_FEATURE GenerateSsdtStub; - OPTION_ACPI_FEATURE CreateAcpiTablesStub; - OPTION_PSTATE_GATHER PStateGatherStub; - OPTION_PSTATE_LEVELING PStateLevelingStub; - #define USER_SSDT_MAIN GenerateSsdtStub - #define USER_PSTATE_OPTION_MAIN CreateAcpiTablesStub - #define USER_CSTATE_OPTION_MAIN CreateAcpiTablesStub - #define USER_PSTATE_OPTION_GATHER PStateGatherStub - #define USER_PSTATE_OPTION_LEVEL PStateLevelingStub - #define USER_PSTATE_CFG_PPC FALSE - #define USER_PSTATE_CFG_PCT FALSE - #define USER_PSTATE_CFG_PSD FALSE - #define USER_PSTATE_CFG_PSS FALSE - #define USER_PSTATE_CFG_XPSS FALSE - - // If ACPI Objects are disabled for PStates, we still need to check - // whether ACPI Objects are enabled for CStates - #if OPTION_IO_CSTATE == TRUE - OPTION_SSDT_FEATURE GenerateSsdt; - OPTION_PSTATE_GATHER PStateGatherMain; - OPTION_ACPI_FEATURE CreateCStateAcpiTables; - #undef USER_SSDT_MAIN - #define USER_SSDT_MAIN GenerateSsdt - #undef USER_PSTATE_OPTION_GATHER - #define USER_PSTATE_OPTION_GATHER PStateGatherMain - #undef USER_CSTATE_OPTION_MAIN - #define USER_CSTATE_OPTION_MAIN CreateCStateAcpiTables - #endif - #endif -#else - OPTION_SSDT_FEATURE GenerateSsdtStub; - OPTION_ACPI_FEATURE CreateAcpiTablesStub; - OPTION_PSTATE_GATHER PStateGatherStub; - OPTION_PSTATE_LEVELING PStateLevelingStub; - #define USER_SSDT_MAIN GenerateSsdtStub - #define USER_PSTATE_OPTION_MAIN CreateAcpiTablesStub - #define USER_CSTATE_OPTION_MAIN CreateAcpiTablesStub - #define USER_PSTATE_OPTION_GATHER PStateGatherStub - #define USER_PSTATE_OPTION_LEVEL PStateLevelingStub - #define USER_PSTATE_CFG_PPC FALSE - #define USER_PSTATE_CFG_PCT FALSE - #define USER_PSTATE_CFG_PSD FALSE - #define USER_PSTATE_CFG_PSS FALSE - #define USER_PSTATE_CFG_XPSS FALSE -#endif - -/* Declare the instance of the PSTATE option configuration structure */ -OPTION_PSTATE_POST_CONFIGURATION OptionPstatePostConfiguration = { - PSTATE_STRUCT_VERSION, - USER_PSTATE_OPTION_GATHER, - USER_PSTATE_OPTION_LEVEL -}; - -OPTION_PSTATE_LATE_CONFIGURATION OptionPstateLateConfiguration = { - PSTATE_STRUCT_VERSION, - USER_SSDT_MAIN, - USER_PSTATE_OPTION_MAIN, - USER_CSTATE_OPTION_MAIN, - USER_PSTATE_CFG_PPC, - USER_PSTATE_CFG_PCT, - USER_PSTATE_CFG_PSD, - USER_PSTATE_CFG_PSS, - USER_PSTATE_CFG_XPSS -}; - -CONST CPU_SPECIFIC_SERVICES_XLAT ROMDATA PstateCpuFamilyServiceArray[] = -{ - F10_PSTATE_SERVICE_SUPPORT - F12_PSTATE_SERVICE_SUPPORT - F14_PSTATE_SERVICE_SUPPORT - F15_OR_PSTATE_SERVICE_SUPPORT - F15_TN_PSTATE_SERVICE_SUPPORT - {0, NULL} -}; -CONST CPU_FAMILY_SUPPORT_TABLE ROMDATA PstateFamilyServiceTable = -{ - (sizeof (PstateCpuFamilyServiceArray) / sizeof (CPU_SPECIFIC_SERVICES_XLAT)), - &PstateCpuFamilyServiceArray[0] -}; -#endif // _OPTION_PSTATE_INSTALL_H_ diff --git a/src/vendorcode/amd/agesa/f12/Config/OptionS3ScriptInstall.h b/src/vendorcode/amd/agesa/f12/Config/OptionS3ScriptInstall.h deleted file mode 100644 index 5b62bdf6dc..0000000000 --- a/src/vendorcode/amd/agesa/f12/Config/OptionS3ScriptInstall.h +++ /dev/null @@ -1,91 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * Install of build option: S3SCRIPT - * - * Contains AMD AGESA install macros and test conditions. Output is the - * defaults tables reflecting the User's build options selection. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: Options - * @e \$Revision: 63425 $ @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ - */ -/***************************************************************************** - * - * Copyright (c) 2008 - 2012, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ***************************************************************************/ - -#ifndef _OPTION_S3SCRIPT_INSTALL_H_ -#define _OPTION_S3SCRIPT_INSTALL_H_ - -#include "S3SaveState.h" -/* This option is designed to be included into the platform solution install - * file. The platform solution install file will define the options status. - * Check to validate the definition - */ -#ifndef OPTION_S3SCRIPT - #define OPTION_S3SCRIPT FALSE //if not define assume PI not use script -#endif - -#if (AGESA_ENTRY_INIT_LATE == TRUE) || (AGESA_ENTRY_INIT_ENV == TRUE) || (AGESA_ENTRY_INIT_MID == TRUE) - #if OPTION_S3SCRIPT == TRUE - #define P_S3_SCRIPT_INIT S3ScriptInitState - #endif -#endif - -#if AGESA_ENTRY_INIT_LATE_RESTORE == TRUE - #if OPTION_S3SCRIPT == TRUE - #define P_S3_SCRIPT_RESTORE S3ScriptRestoreState - #endif -#endif - -#ifndef P_S3_SCRIPT_INIT - #define P_S3_SCRIPT_INIT S3ScriptInitStateStub -#endif - -#ifndef P_S3_SCRIPT_RESTORE - #define P_S3_SCRIPT_RESTORE S3ScriptInitStateStub - #undef GNB_S3_DISPATCH_FUNCTION_TABLE -#endif - -#ifndef GNB_S3_DISPATCH_FUNCTION_TABLE - #define GNB_S3_DISPATCH_FUNCTION_TABLE -#endif - -/* Declare the instance of the S3SCRIPT option configuration structure */ -S3_SCRIPT_CONFIGURATION OptionS3ScriptConfiguration = { - P_S3_SCRIPT_INIT, - P_S3_SCRIPT_RESTORE -}; - -S3_DISPATCH_FUNCTION_ENTRY S3DispatchFunctionTable [] = { - GNB_S3_DISPATCH_FUNCTION_TABLE - {0, NULL} -}; -#endif // _OPTION_S3SCRIPT_INSTALL_H_ diff --git a/src/vendorcode/amd/agesa/f12/Config/OptionSlitInstall.h b/src/vendorcode/amd/agesa/f12/Config/OptionSlitInstall.h deleted file mode 100644 index 915e5302c4..0000000000 --- a/src/vendorcode/amd/agesa/f12/Config/OptionSlitInstall.h +++ /dev/null @@ -1,79 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * Install of build option: SLIT - * - * Contains AMD AGESA install macros and test conditions. Output is the - * defaults tables reflecting the User's build options selection. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: Options - * @e \$Revision: 63425 $ @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ - */ -/***************************************************************************** - * - * Copyright (c) 2008 - 2012, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ***************************************************************************/ - -#ifndef _OPTION_SLIT_INSTALL_H_ -#define _OPTION_SLIT_INSTALL_H_ - -/* This option is designed to be included into the platform solution install - * file. The platform solution install file will define the options status. - * Check to validate the definition - */ -#if AGESA_ENTRY_INIT_LATE == TRUE - #ifndef OPTION_SLIT - #error BLDOPT: Option not defined: "OPTION_SLIT" - #endif - #if OPTION_SLIT == TRUE - OPTION_SLIT_FEATURE GetAcpiSlitMain; - OPTION_SLIT_RELEASE_BUFFER ReleaseSlitBuffer; - #define USER_SLIT_OPTION GetAcpiSlitMain - #define USER_SLIT_RELEASE_BUFFER ReleaseSlitBuffer - #else - OPTION_SLIT_FEATURE GetAcpiSlitStub; - OPTION_SLIT_RELEASE_BUFFER ReleaseSlitBufferStub; - #define USER_SLIT_OPTION GetAcpiSlitStub - #define USER_SLIT_RELEASE_BUFFER ReleaseSlitBufferStub - #endif -#else - OPTION_SLIT_FEATURE GetAcpiSlitStub; - OPTION_SLIT_RELEASE_BUFFER ReleaseSlitBufferStub; - #define USER_SLIT_OPTION GetAcpiSlitStub - #define USER_SLIT_RELEASE_BUFFER ReleaseSlitBufferStub -#endif -/* Declare the instance of the SLIT option configuration structure */ -OPTION_SLIT_CONFIGURATION OptionSlitConfiguration = { - SLIT_STRUCT_VERSION, - USER_SLIT_OPTION, - USER_SLIT_RELEASE_BUFFER -}; - -#endif // _OPTION_SLIT_INSTALL_H_ diff --git a/src/vendorcode/amd/agesa/f12/Config/OptionSratInstall.h b/src/vendorcode/amd/agesa/f12/Config/OptionSratInstall.h deleted file mode 100644 index 273874753f..0000000000 --- a/src/vendorcode/amd/agesa/f12/Config/OptionSratInstall.h +++ /dev/null @@ -1,73 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * Install of build option: SRAT - * - * Contains AMD AGESA install macros and test conditions. Output is the - * defaults tables reflecting the User's build options selection. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: Options - * @e \$Revision: 63425 $ @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ - */ -/***************************************************************************** - * - * Copyright (c) 2008 - 2012, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ***************************************************************************/ - -#ifndef _OPTION_SRAT_INSTALL_H_ -#define _OPTION_SRAT_INSTALL_H_ - -/* This option is designed to be included into the platform solution install - * file. The platform solution install file will define the options status. - * Check to validate the definition - */ -#if AGESA_ENTRY_INIT_LATE == TRUE - #ifndef OPTION_SRAT - #error BLDOPT: Option not defined: "OPTION_SRAT" - #endif - #if OPTION_SRAT == TRUE - OPTION_SRAT_FEATURE GetAcpiSratMain; - #define USER_SRAT_OPTION GetAcpiSratMain - #else - OPTION_SRAT_FEATURE GetAcpiSratStub; - #define USER_SRAT_OPTION GetAcpiSratStub - #endif -#else - OPTION_SRAT_FEATURE GetAcpiSratStub; - #define USER_SRAT_OPTION GetAcpiSratStub -#endif - -/* Declare the instance of the WHEA option configuration structure */ -OPTION_SRAT_CONFIGURATION OptionSratConfiguration = { - SRAT_STRUCT_VERSION, - USER_SRAT_OPTION -}; - -#endif // _OPTION_WHEA_INSTALL_H_ diff --git a/src/vendorcode/amd/agesa/f12/Config/OptionSwC1eInstall.h b/src/vendorcode/amd/agesa/f12/Config/OptionSwC1eInstall.h deleted file mode 100644 index 34886eee14..0000000000 --- a/src/vendorcode/amd/agesa/f12/Config/OptionSwC1eInstall.h +++ /dev/null @@ -1,80 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * Install of build option: SW C1e - * - * Contains AMD AGESA install macros and test conditions. Output is the - * defaults tables reflecting the User's build options selection. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: Options - * @e \$Revision: 63425 $ @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ - */ -/***************************************************************************** - * - * Copyright (c) 2008 - 2012, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ***************************************************************************/ - -#ifndef _OPTION_SW_C1E_INSTALL_H_ -#define _OPTION_SW_C1E_INSTALL_H_ - -#include "cpuSwC1e.h" - -/* This option is designed to be included into the platform solution install - * file. The platform solution install file will define the options status. - * Check to validate the definition - */ -#define OPTION_SW_C1E_FEAT -#define F10_SW_C1E_SUPPORT -#if AGESA_ENTRY_INIT_EARLY == TRUE - #ifdef OPTION_FAMILY10H - #if OPTION_FAMILY10H == TRUE - #if (OPTION_FAMILY10H_BL == TRUE) || (OPTION_FAMILY10H_DA == TRUE) || (OPTION_FAMILY10H_RB == TRUE) || (OPTION_FAMILY10H_PH == TRUE) - extern CONST CPU_FEATURE_DESCRIPTOR ROMDATA CpuFeatureSwC1e; - #undef OPTION_SW_C1E_FEAT - #define OPTION_SW_C1E_FEAT &CpuFeatureSwC1e, - extern CONST SW_C1E_FAMILY_SERVICES ROMDATA F10SwC1e; - #undef F10_SW_C1E_SUPPORT - #define F10_SW_C1E_SUPPORT {(AMD_FAMILY_10_BL | AMD_FAMILY_10_DA | AMD_FAMILY_10_RB | AMD_FAMILY_10_PH), &F10SwC1e}, - #endif - #endif - #endif - CONST CPU_SPECIFIC_SERVICES_XLAT ROMDATA SwC1eFamilyServiceArray[] = - { - F10_SW_C1E_SUPPORT - {0, NULL} - }; - CONST CPU_FAMILY_SUPPORT_TABLE ROMDATA SwC1eFamilyServiceTable = - { - (sizeof (SwC1eFamilyServiceArray) / sizeof (CPU_SPECIFIC_SERVICES_XLAT)), - &SwC1eFamilyServiceArray[0] - }; -#endif - -#endif // _OPTION_SW_C1E_INSTALL_H_ diff --git a/src/vendorcode/amd/agesa/f12/Config/OptionWheaInstall.h b/src/vendorcode/amd/agesa/f12/Config/OptionWheaInstall.h deleted file mode 100644 index 5facece353..0000000000 --- a/src/vendorcode/amd/agesa/f12/Config/OptionWheaInstall.h +++ /dev/null @@ -1,74 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * Install of build option: WHEA - * - * Contains AMD AGESA install macros and test conditions. Output is the - * defaults tables reflecting the User's build options selection. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: Options - * @e \$Revision: 63425 $ @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ - */ -/***************************************************************************** - * - * Copyright (c) 2008 - 2012, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ***************************************************************************/ - -#ifndef _OPTION_WHEA_INSTALL_H_ -#define _OPTION_WHEA_INSTALL_H_ - -/* This option is designed to be included into the platform solution install - * file. The platform solution install file will define the options status. - * Check to validate the definition - */ -#if AGESA_ENTRY_INIT_LATE == TRUE - #ifndef OPTION_WHEA - #error BLDOPT: Option not defined: "OPTION_WHEA" - #endif - #if OPTION_WHEA == TRUE - OPTION_WHEA_FEATURE GetAcpiWheaMain; - #define USER_WHEA_OPTION GetAcpiWheaMain - #else - OPTION_WHEA_FEATURE GetAcpiWheaStub; - #define USER_WHEA_OPTION GetAcpiWheaStub - #endif - -#else - OPTION_WHEA_FEATURE GetAcpiWheaStub; - #define USER_WHEA_OPTION GetAcpiWheaStub -#endif - -/* Declare the instance of the WHEA option configuration structure */ -OPTION_WHEA_CONFIGURATION OptionWheaConfiguration = { - WHEA_STRUCT_VERSION, - USER_WHEA_OPTION -}; - -#endif // _OPTION_WHEA_INSTALL_H_ diff --git a/src/vendorcode/amd/agesa/f12/Config/PlatformInstall.h b/src/vendorcode/amd/agesa/f12/Config/PlatformInstall.h deleted file mode 100644 index 2153fe7c5e..0000000000 --- a/src/vendorcode/amd/agesa/f12/Config/PlatformInstall.h +++ /dev/null @@ -1,2586 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * Install of build options for a combination of package type, processor, and features. - * - * This file generates the defaults tables for the all platform solution - * combinations. The documented build options are imported from a user - * controlled file for processing. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: Core - * @e \$Revision: 49633 $ @e \$Date: 2011-03-26 06:52:29 +0800 (Sat, 26 Mar 2011) $ - */ -/***************************************************************************** - * - * Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ***************************************************************************/ - -#ifndef RUN_BROKEN_AGESA_TESTS - #define RUN_BROKEN_AGESA_TESTS 0 -#endif - -/***************************************************************************** - * - * Start processing the user options: First, set default settings - * - ****************************************************************************/ - - -VOLATILE AMD_MODULE_HEADER mCpuModuleID = { - //ModuleHeaderSignature - // Remove 'DOM$' as temp solution before update BinUtil.exe , - Int32FromChar ('0', '0', '0', '0'), - //ModuleIdentifier[8] - AGESA_ID, - //ModuleVersion[12] - AGESA_VERSION_STRING, - //ModuleDispatcher - NULL,//(VOID *)(UINT64)((MODULE_ENTRY)AmdAgesaDispatcher), - //NextBlock - NULL -}; - - -/* Process solution defined socket / family installations - * - * As part of the release package for each image, define the options below to select the - * AGESA processor support included in that image. - */ - -/* Default sockets to off */ -#define OPTION_G34_SOCKET_SUPPORT FALSE -#define OPTION_C32_SOCKET_SUPPORT FALSE -#define OPTION_S1G3_SOCKET_SUPPORT FALSE -#define OPTION_S1G4_SOCKET_SUPPORT FALSE -#define OPTION_ASB2_SOCKET_SUPPORT FALSE -#define OPTION_FS1_SOCKET_SUPPORT FALSE -#define OPTION_FM1_SOCKET_SUPPORT FALSE -#define OPTION_FP1_SOCKET_SUPPORT FALSE -#define OPTION_FT1_SOCKET_SUPPORT FALSE -#define OPTION_AM3_SOCKET_SUPPORT FALSE - -/* Default families to off */ -#define OPTION_FAMILY10H FALSE -#define OPTION_FAMILY12H FALSE -#define OPTION_FAMILY14H FALSE -#define OPTION_FAMILY15H FALSE - - -/* Enable the appropriate socket support */ -#ifdef INSTALL_G34_SOCKET_SUPPORT - #if INSTALL_G34_SOCKET_SUPPORT == TRUE - #undef OPTION_G34_SOCKET_SUPPORT - #define OPTION_G34_SOCKET_SUPPORT TRUE - #endif -#endif - -#ifdef INSTALL_C32_SOCKET_SUPPORT - #if INSTALL_C32_SOCKET_SUPPORT == TRUE - #undef OPTION_C32_SOCKET_SUPPORT - #define OPTION_C32_SOCKET_SUPPORT TRUE - #endif -#endif - -#ifdef INSTALL_S1G3_SOCKET_SUPPORT - #if INSTALL_S1G3_SOCKET_SUPPORT == TRUE - #undef OPTION_S1G3_SOCKET_SUPPORT - #define OPTION_S1G3_SOCKET_SUPPORT TRUE - #endif -#endif - -#ifdef INSTALL_S1G4_SOCKET_SUPPORT - #if INSTALL_S1G4_SOCKET_SUPPORT == TRUE - #undef OPTION_S1G4_SOCKET_SUPPORT - #define OPTION_S1G4_SOCKET_SUPPORT TRUE - #endif -#endif - -#ifdef INSTALL_ASB2_SOCKET_SUPPORT - #if INSTALL_ASB2_SOCKET_SUPPORT == TRUE - #undef OPTION_ASB2_SOCKET_SUPPORT - #define OPTION_ASB2_SOCKET_SUPPORT TRUE - #endif -#endif - -#ifdef INSTALL_FS1_SOCKET_SUPPORT - #if INSTALL_FS1_SOCKET_SUPPORT == TRUE - #undef OPTION_FS1_SOCKET_SUPPORT - #define OPTION_FS1_SOCKET_SUPPORT TRUE - #endif -#endif - -#ifdef INSTALL_FM1_SOCKET_SUPPORT - #if INSTALL_FM1_SOCKET_SUPPORT == TRUE - #undef OPTION_FM1_SOCKET_SUPPORT - #define OPTION_FM1_SOCKET_SUPPORT TRUE - #endif -#endif - -#ifdef INSTALL_FP1_SOCKET_SUPPORT - #if INSTALL_FP1_SOCKET_SUPPORT == TRUE - #undef OPTION_FP1_SOCKET_SUPPORT - #define OPTION_FP1_SOCKET_SUPPORT TRUE - #endif -#endif - -#ifdef INSTALL_FT1_SOCKET_SUPPORT - #if INSTALL_FT1_SOCKET_SUPPORT == TRUE - #undef OPTION_FT1_SOCKET_SUPPORT - #define OPTION_FT1_SOCKET_SUPPORT TRUE - #endif -#endif - -#ifdef INSTALL_AM3_SOCKET_SUPPORT - #if INSTALL_AM3_SOCKET_SUPPORT == TRUE - #undef OPTION_AM3_SOCKET_SUPPORT - #define OPTION_AM3_SOCKET_SUPPORT TRUE - #endif -#endif - - -/* Enable the appropriate family support */ -// F10 is supported in G34, C32, S1g4, ASB2, S1g3, & AM3 -#ifdef INSTALL_FAMILY_10_SUPPORT - #if INSTALL_FAMILY_10_SUPPORT == TRUE - #undef OPTION_FAMILY10H - #define OPTION_FAMILY10H TRUE - #endif -#endif - -// F12 is supported in FP1, FS1, & FM1 -#ifdef INSTALL_FAMILY_12_SUPPORT - #if INSTALL_FAMILY_12_SUPPORT == TRUE - #undef OPTION_FAMILY12H - #define OPTION_FAMILY12H TRUE - #endif -#endif - -// F14 is supported in FT1 -#ifdef INSTALL_FAMILY_14_SUPPORT - #if INSTALL_FAMILY_14_SUPPORT == TRUE - #undef OPTION_FAMILY14H - #define OPTION_FAMILY14H TRUE - #endif -#endif - -// F15 is supported in G34, C32, & AM3 -#ifdef INSTALL_FAMILY_15_SUPPORT - #if INSTALL_FAMILY_15_SUPPORT == TRUE - #undef OPTION_FAMILY15H - #define OPTION_FAMILY15H TRUE - #endif -#endif - - -/* Turn off families not required by socket designations */ -#if (OPTION_FAMILY10H == TRUE) - #if (OPTION_G34_SOCKET_SUPPORT == FALSE) && (OPTION_C32_SOCKET_SUPPORT == FALSE) && (OPTION_S1G3_SOCKET_SUPPORT == FALSE) && (OPTION_S1G4_SOCKET_SUPPORT == FALSE) && (OPTION_ASB2_SOCKET_SUPPORT == FALSE) && (OPTION_AM3_SOCKET_SUPPORT == FALSE) - #undef OPTION_FAMILY10H - #define OPTION_FAMILY10H FALSE - #endif -#endif - -#if (OPTION_FAMILY12H == TRUE) - #if (OPTION_FS1_SOCKET_SUPPORT == FALSE) && (OPTION_FM1_SOCKET_SUPPORT == FALSE) && (OPTION_FP1_SOCKET_SUPPORT == FALSE) - #undef OPTION_FAMILY12H - #define OPTION_FAMILY12H FALSE - #endif -#endif - -#if (OPTION_FAMILY14H == TRUE) - #if (OPTION_FT1_SOCKET_SUPPORT == FALSE) - #undef OPTION_FAMILY14H - #define OPTION_FAMILY14H FALSE - #endif -#endif - -#if (OPTION_FAMILY15H == TRUE) - #if (OPTION_G34_SOCKET_SUPPORT == FALSE) && (OPTION_C32_SOCKET_SUPPORT == FALSE) && (OPTION_AM3_SOCKET_SUPPORT == FALSE) - #undef OPTION_FAMILY15H - #define OPTION_FAMILY15H FALSE - #endif -#endif - - -/* Check for invalid combinations of socket/family */ -#if (OPTION_G34_SOCKET_SUPPORT == TRUE) - #if (OPTION_FAMILY10H == FALSE) && (OPTION_FAMILY15H == FALSE) - #error No G34 supported families included in the build - #endif -#endif - -#if (OPTION_C32_SOCKET_SUPPORT == TRUE) - #if (OPTION_FAMILY10H == FALSE) && (OPTION_FAMILY15H == FALSE) - #error No C32 supported families included in the build - #endif -#endif - -#if (OPTION_S1G3_SOCKET_SUPPORT == TRUE) - #if (OPTION_FAMILY10H == FALSE) - #error No S1G3 supported families included in the build - #endif -#endif - -#if (OPTION_S1G4_SOCKET_SUPPORT == TRUE) - #if (OPTION_FAMILY10H == FALSE) - #error No S1G4 supported families included in the build - #endif -#endif - -#if (OPTION_ASB2_SOCKET_SUPPORT == TRUE) - #if (OPTION_FAMILY10H == FALSE) - #error No ASB2 supported families included in the build - #endif -#endif - -#if (OPTION_FS1_SOCKET_SUPPORT == TRUE) - #if (OPTION_FAMILY12H == FALSE) - #error No FS1 supported families included in the build - #endif -#endif - -#if (OPTION_FM1_SOCKET_SUPPORT == TRUE) - #if (OPTION_FAMILY12H == FALSE) - #error No FM1 supported families included in the build - #endif -#endif - -#if (OPTION_FP1_SOCKET_SUPPORT == TRUE) - #if (OPTION_FAMILY12H == FALSE) - #error No FP1 supported families included in the build - #endif -#endif - -#if (OPTION_FT1_SOCKET_SUPPORT == TRUE) - #if (OPTION_FAMILY14H == FALSE) - #error No FT1 supported families included in the build - #endif -#endif - -#if (OPTION_AM3_SOCKET_SUPPORT == TRUE) - #if (OPTION_FAMILY10H == FALSE) && (OPTION_FAMILY15H == FALSE) - #error No AM3 supported families included in the build - #endif -#endif - - -/* Process AGESA private data - * - * Turn on appropriate CPU models and memory controllers, - * as well as some other memory controls. - */ - -/* Default all models to off */ -#define OPTION_FAMILY10H_BL FALSE -#define OPTION_FAMILY10H_DA FALSE -#define OPTION_FAMILY10H_HY FALSE -#define OPTION_FAMILY10H_PH FALSE -#define OPTION_FAMILY10H_RB FALSE -#define OPTION_FAMILY12H_LN FALSE -#define OPTION_FAMILY14H_ON FALSE -#define OPTION_FAMILY15H_OR FALSE - -/* Default all memory controllers to off */ -#define OPTION_MEMCTLR_DR FALSE -#define OPTION_MEMCTLR_HY FALSE -#define OPTION_MEMCTLR_OR FALSE -#define OPTION_MEMCTLR_C32 FALSE -#define OPTION_MEMCTLR_DA FALSE -#define OPTION_MEMCTLR_LN FALSE -#define OPTION_MEMCTLR_ON FALSE -#define OPTION_MEMCTLR_Ni FALSE -#define OPTION_MEMCTLR_PH FALSE -#define OPTION_MEMCTLR_RB FALSE - -/* Default all memory controls to off */ -#define OPTION_HW_WRITE_LEV_TRAINING FALSE -#define OPTION_SW_WRITE_LEV_TRAINING FALSE -#define OPTION_CONTINOUS_PATTERN_GENERATION FALSE -#define OPTION_HW_DQS_REC_EN_TRAINING FALSE -#define OPTION_NON_OPT_SW_DQS_REC_EN_TRAINING FALSE -#define OPTION_OPT_SW_DQS_REC_EN_TRAINING FALSE -#define OPTION_NON_OPT_SW_RD_WR_POS_TRAINING FALSE -#define OPTION_OPT_SW_RD_WR_POS_TRAINING FALSE -#define OPTION_MAX_RD_LAT_TRAINING FALSE -#define OPTION_HW_DRAM_INIT FALSE -#define OPTION_SW_DRAM_INIT FALSE -#define OPTION_S3_MEM_SUPPORT FALSE -#define OPTION_ADDR_TO_CS_TRANSLATOR FALSE -#define OPTION_HW_DQS_REC_EN_SEED_TRAINING FALSE - -/* Defaults for public user options */ -#define OPTION_UDIMMS FALSE -#define OPTION_RDIMMS FALSE -#define OPTION_SODIMMS FALSE -#define OPTION_LRDIMMS FALSE -#define OPTION_DDR2 FALSE -#define OPTION_DDR3 FALSE -#define OPTION_ECC FALSE -#define OPTION_BANK_INTERLEAVE FALSE -#define OPTION_DCT_INTERLEAVE FALSE -#define OPTION_NODE_INTERLEAVE FALSE -#define OPTION_PARALLEL_TRAINING FALSE -#define OPTION_ONLINE_SPARE FALSE -#define OPTION_MEM_RESTORE FALSE -#define OPTION_DIMM_EXCLUDE FALSE - -/* Default all CPU controls to off */ -#define OPTION_MULTISOCKET FALSE -#define OPTION_SRAT FALSE -#define OPTION_SLIT FALSE -#define OPTION_HT_ASSIST FALSE -#define OPTION_ATM_MODE FALSE -#define OPTION_CPU_CORELEVLING FALSE -#define OPTION_MSG_BASED_C1E FALSE -#define OPTION_CPU_CFOH FALSE -#define OPTION_C6_STATE FALSE -#define OPTION_IO_CSTATE FALSE -#define OPTION_CPB FALSE -#define OPTION_CPU_LOW_PWR_PSTATE_FOR_PROCHOT FALSE -#define OPTION_S3SCRIPT FALSE -#define OPTION_GFX_RECOVERY FALSE - -/* Default FCH controls to off */ -#define FCH_SUPPORT FALSE - -/* Enable all private controls based on socket/family enables */ -#if (OPTION_G34_SOCKET_SUPPORT == TRUE) - #if (OPTION_FAMILY10H == TRUE) - #undef OPTION_FAMILY10H_HY - #define OPTION_FAMILY10H_HY TRUE - #undef OPTION_MEMCTLR_HY - #define OPTION_MEMCTLR_HY TRUE - #undef OPTION_HW_WRITE_LEV_TRAINING - #define OPTION_HW_WRITE_LEV_TRAINING TRUE - #undef OPTION_OPT_SW_DQS_REC_EN_TRAINING - #define OPTION_OPT_SW_DQS_REC_EN_TRAINING TRUE - #undef OPTION_OPT_SW_RD_WR_POS_TRAINING - #define OPTION_OPT_SW_RD_WR_POS_TRAINING TRUE - #undef OPTION_MAX_RD_LAT_TRAINING - #define OPTION_MAX_RD_LAT_TRAINING TRUE - #undef OPTION_SW_DRAM_INIT - #define OPTION_SW_DRAM_INIT TRUE - #undef OPTION_S3_MEM_SUPPORT - #define OPTION_S3_MEM_SUPPORT TRUE - #undef OPTION_MULTISOCKET - #define OPTION_MULTISOCKET TRUE - #undef OPTION_SRAT - #define OPTION_SRAT TRUE - #undef OPTION_SLIT - #define OPTION_SLIT TRUE - #undef OPTION_HT_ASSIST - #define OPTION_HT_ASSIST TRUE - #undef OPTION_CPU_CORELEVLING - #define OPTION_CPU_CORELEVLING TRUE - #undef OPTION_MSG_BASED_C1E - #define OPTION_MSG_BASED_C1E TRUE - #undef OPTION_CPU_CFOH - #define OPTION_CPU_CFOH TRUE - #undef OPTION_UDIMMS - #define OPTION_UDIMMS TRUE - #undef OPTION_RDIMMS - #define OPTION_RDIMMS TRUE - #undef OPTION_SODIMMS - #define OPTION_SODIMMS TRUE - #undef OPTION_DDR3 - #define OPTION_DDR3 TRUE - #undef OPTION_ECC - #define OPTION_ECC TRUE - #undef OPTION_BANK_INTERLEAVE - #define OPTION_BANK_INTERLEAVE TRUE - #undef OPTION_DCT_INTERLEAVE - #define OPTION_DCT_INTERLEAVE TRUE - #undef OPTION_NODE_INTERLEAVE - #define OPTION_NODE_INTERLEAVE TRUE - #undef OPTION_PARALLEL_TRAINING - #define OPTION_PARALLEL_TRAINING TRUE - #undef OPTION_MEM_RESTORE - #define OPTION_MEM_RESTORE TRUE - #undef OPTION_ONLINE_SPARE - #define OPTION_ONLINE_SPARE TRUE - #undef OPTION_DIMM_EXCLUDE - #define OPTION_DIMM_EXCLUDE TRUE - #endif - #if (OPTION_FAMILY15H == TRUE) - #undef OPTION_FAMILY15H_OR - #define OPTION_FAMILY15H_OR TRUE - #undef OPTION_MEMCTLR_OR - #define OPTION_MEMCTLR_OR TRUE - #undef OPTION_HW_WRITE_LEV_TRAINING - #define OPTION_HW_WRITE_LEV_TRAINING TRUE - #undef OPTION_CONTINOUS_PATTERN_GENERATION - #define OPTION_CONTINOUS_PATTERN_GENERATION TRUE - #undef OPTION_HW_DQS_REC_EN_TRAINING - #define OPTION_HW_DQS_REC_EN_TRAINING TRUE - #undef OPTION_HW_DQS_REC_EN_SEED_TRAINING - #define OPTION_HW_DQS_REC_EN_SEED_TRAINING TRUE - #undef OPTION_OPT_SW_DQS_REC_EN_TRAINING - #define OPTION_OPT_SW_DQS_REC_EN_TRAINING TRUE - #undef OPTION_OPT_SW_RD_WR_POS_TRAINING - #define OPTION_OPT_SW_RD_WR_POS_TRAINING TRUE - #undef OPTION_MAX_RD_LAT_TRAINING - #define OPTION_MAX_RD_LAT_TRAINING TRUE - #undef OPTION_SW_DRAM_INIT - #define OPTION_SW_DRAM_INIT TRUE - #undef OPTION_S3_MEM_SUPPORT - #define OPTION_S3_MEM_SUPPORT TRUE - #undef OPTION_MULTISOCKET - #define OPTION_MULTISOCKET TRUE - #undef OPTION_C6_STATE - #define OPTION_C6_STATE TRUE - #undef OPTION_IO_CSTATE - #define OPTION_IO_CSTATE TRUE - #undef OPTION_CPB - #define OPTION_CPB TRUE - #undef OPTION_CPU_LOW_PWR_PSTATE_FOR_PROCHOT - #define OPTION_CPU_LOW_PWR_PSTATE_FOR_PROCHOT TRUE - #undef OPTION_SRAT - #define OPTION_SRAT TRUE - #undef OPTION_SLIT - #define OPTION_SLIT TRUE - #undef OPTION_HT_ASSIST - #define OPTION_HT_ASSIST TRUE - #undef OPTION_ATM_MODE - #define OPTION_ATM_MODE TRUE - #undef OPTION_CPU_CORELEVLING - #define OPTION_CPU_CORELEVLING TRUE - #undef OPTION_MSG_BASED_C1E - #define OPTION_MSG_BASED_C1E TRUE - #undef OPTION_CPU_CFOH - #define OPTION_CPU_CFOH TRUE - #undef OPTION_UDIMMS - #define OPTION_UDIMMS TRUE - #undef OPTION_RDIMMS - #define OPTION_RDIMMS TRUE - #undef OPTION_SODIMMS - #define OPTION_SODIMMS TRUE - #undef OPTION_LRDIMMS - #define OPTION_LRDIMMS TRUE - #undef OPTION_DDR3 - #define OPTION_DDR3 TRUE - #undef OPTION_ECC - #define OPTION_ECC TRUE - #undef OPTION_BANK_INTERLEAVE - #define OPTION_BANK_INTERLEAVE TRUE - #undef OPTION_DCT_INTERLEAVE - #define OPTION_DCT_INTERLEAVE TRUE - #undef OPTION_NODE_INTERLEAVE - #define OPTION_NODE_INTERLEAVE TRUE - #undef OPTION_MEM_RESTORE - #define OPTION_MEM_RESTORE TRUE - #undef OPTION_ONLINE_SPARE - #define OPTION_ONLINE_SPARE TRUE - #undef OPTION_DIMM_EXCLUDE - #define OPTION_DIMM_EXCLUDE TRUE - #endif -#endif - -#if (OPTION_C32_SOCKET_SUPPORT == TRUE) - #if (OPTION_FAMILY10H == TRUE) - #undef OPTION_FAMILY10H_HY - #define OPTION_FAMILY10H_HY TRUE - #undef OPTION_MEMCTLR_C32 - #define OPTION_MEMCTLR_C32 TRUE - #undef OPTION_HW_WRITE_LEV_TRAINING - #define OPTION_HW_WRITE_LEV_TRAINING TRUE - #undef OPTION_OPT_SW_DQS_REC_EN_TRAINING - #define OPTION_OPT_SW_DQS_REC_EN_TRAINING TRUE - #undef OPTION_OPT_SW_RD_WR_POS_TRAINING - #define OPTION_OPT_SW_RD_WR_POS_TRAINING TRUE - #undef OPTION_MAX_RD_LAT_TRAINING - #define OPTION_MAX_RD_LAT_TRAINING TRUE - #undef OPTION_SW_DRAM_INIT - #define OPTION_SW_DRAM_INIT TRUE - #undef OPTION_S3_MEM_SUPPORT - #define OPTION_S3_MEM_SUPPORT TRUE - #undef OPTION_ADDR_TO_CS_TRANSLATOR - #define OPTION_ADDR_TO_CS_TRANSLATOR FALSE - #undef OPTION_MULTISOCKET - #define OPTION_MULTISOCKET TRUE - #undef OPTION_SRAT - #define OPTION_SRAT TRUE - #undef OPTION_SLIT - #define OPTION_SLIT TRUE - #undef OPTION_HT_ASSIST - #define OPTION_HT_ASSIST TRUE - #undef OPTION_CPU_CORELEVLING - #define OPTION_CPU_CORELEVLING TRUE - #undef OPTION_MSG_BASED_C1E - #define OPTION_MSG_BASED_C1E TRUE - #undef OPTION_CPU_CFOH - #define OPTION_CPU_CFOH TRUE - #undef OPTION_UDIMMS - #define OPTION_UDIMMS TRUE - #undef OPTION_RDIMMS - #define OPTION_RDIMMS TRUE - #undef OPTION_SODIMMS - #define OPTION_SODIMMS TRUE - #undef OPTION_DDR3 - #define OPTION_DDR3 TRUE - #undef OPTION_ECC - #define OPTION_ECC TRUE - #undef OPTION_BANK_INTERLEAVE - #define OPTION_BANK_INTERLEAVE TRUE - #undef OPTION_DCT_INTERLEAVE - #define OPTION_DCT_INTERLEAVE TRUE - #undef OPTION_NODE_INTERLEAVE - #define OPTION_NODE_INTERLEAVE TRUE - #undef OPTION_PARALLEL_TRAINING - #define OPTION_PARALLEL_TRAINING TRUE - #undef OPTION_MEM_RESTORE - #define OPTION_MEM_RESTORE TRUE - #undef OPTION_ONLINE_SPARE - #define OPTION_ONLINE_SPARE TRUE - #undef OPTION_DIMM_EXCLUDE - #define OPTION_DIMM_EXCLUDE TRUE - #endif - #if (OPTION_FAMILY15H == TRUE) - #undef OPTION_FAMILY15H_OR - #define OPTION_FAMILY15H_OR TRUE - #undef OPTION_MEMCTLR_OR - #define OPTION_MEMCTLR_OR TRUE - #undef OPTION_HW_WRITE_LEV_TRAINING - #define OPTION_HW_WRITE_LEV_TRAINING TRUE - #undef OPTION_CONTINOUS_PATTERN_GENERATION - #define OPTION_CONTINOUS_PATTERN_GENERATION TRUE - #undef OPTION_HW_DQS_REC_EN_TRAINING - #define OPTION_HW_DQS_REC_EN_TRAINING TRUE - #undef OPTION_HW_DQS_REC_EN_SEED_TRAINING - #define OPTION_HW_DQS_REC_EN_SEED_TRAINING TRUE - #undef OPTION_OPT_SW_DQS_REC_EN_TRAINING - #define OPTION_OPT_SW_DQS_REC_EN_TRAINING TRUE - #undef OPTION_OPT_SW_RD_WR_POS_TRAINING - #define OPTION_OPT_SW_RD_WR_POS_TRAINING TRUE - #undef OPTION_MAX_RD_LAT_TRAINING - #define OPTION_MAX_RD_LAT_TRAINING TRUE - #undef OPTION_SW_DRAM_INIT - #define OPTION_SW_DRAM_INIT TRUE - #undef OPTION_S3_MEM_SUPPORT - #define OPTION_S3_MEM_SUPPORT TRUE - #undef OPTION_ADDR_TO_CS_TRANSLATOR - #define OPTION_ADDR_TO_CS_TRANSLATOR TRUE - #undef OPTION_MULTISOCKET - #define OPTION_MULTISOCKET TRUE - #undef OPTION_C6_STATE - #define OPTION_C6_STATE TRUE - #undef OPTION_IO_CSTATE - #define OPTION_IO_CSTATE TRUE - #undef OPTION_CPB - #define OPTION_CPB TRUE - #undef OPTION_CPU_LOW_PWR_PSTATE_FOR_PROCHOT - #define OPTION_CPU_LOW_PWR_PSTATE_FOR_PROCHOT TRUE - #undef OPTION_SRAT - #define OPTION_SRAT TRUE - #undef OPTION_SLIT - #define OPTION_SLIT TRUE - #undef OPTION_HT_ASSIST - #define OPTION_HT_ASSIST TRUE - #undef OPTION_ATM_MODE - #define OPTION_ATM_MODE TRUE - #undef OPTION_CPU_CORELEVLING - #define OPTION_CPU_CORELEVLING TRUE - #undef OPTION_MSG_BASED_C1E - #define OPTION_MSG_BASED_C1E TRUE - #undef OPTION_CPU_CFOH - #define OPTION_CPU_CFOH TRUE - #undef OPTION_UDIMMS - #define OPTION_UDIMMS TRUE - #undef OPTION_RDIMMS - #define OPTION_RDIMMS TRUE - #undef OPTION_SODIMMS - #define OPTION_SODIMMS TRUE - #undef OPTION_LRDIMMS - #define OPTION_LRDIMMS TRUE - #undef OPTION_DDR3 - #define OPTION_DDR3 TRUE - #undef OPTION_ECC - #define OPTION_ECC TRUE - #undef OPTION_BANK_INTERLEAVE - #define OPTION_BANK_INTERLEAVE TRUE - #undef OPTION_DCT_INTERLEAVE - #define OPTION_DCT_INTERLEAVE TRUE - #undef OPTION_NODE_INTERLEAVE - #define OPTION_NODE_INTERLEAVE TRUE - #undef OPTION_MEM_RESTORE - #define OPTION_MEM_RESTORE TRUE - #undef OPTION_ONLINE_SPARE - #define OPTION_ONLINE_SPARE TRUE - #undef OPTION_DIMM_EXCLUDE - #define OPTION_DIMM_EXCLUDE TRUE - #endif -#endif - -#if (OPTION_S1G3_SOCKET_SUPPORT == TRUE) - #if (OPTION_FAMILY10H == TRUE) - #undef OPTION_FAMILY10H_BL - #define OPTION_FAMILY10H_BL TRUE - #undef OPTION_FAMILY10H_DA - #define OPTION_FAMILY10H_DA TRUE - #undef OPTION_MEMCTLR_DA - #define OPTION_MEMCTLR_DA TRUE - #undef OPTION_HW_WRITE_LEV_TRAINING - #define OPTION_HW_WRITE_LEV_TRAINING TRUE - #undef OPTION_OPT_SW_DQS_REC_EN_TRAINING - #define OPTION_OPT_SW_DQS_REC_EN_TRAINING TRUE - #undef OPTION_OPT_SW_RD_WR_POS_TRAINING - #define OPTION_OPT_SW_RD_WR_POS_TRAINING TRUE - #undef OPTION_MAX_RD_LAT_TRAINING - #define OPTION_MAX_RD_LAT_TRAINING TRUE - #undef OPTION_SW_DRAM_INIT - #define OPTION_SW_DRAM_INIT TRUE - #undef OPTION_S3_MEM_SUPPORT - #define OPTION_S3_MEM_SUPPORT TRUE - #undef OPTION_CPU_CORELEVLING - #define OPTION_CPU_CORELEVLING TRUE - #undef OPTION_CPU_CFOH - #define OPTION_CPU_CFOH TRUE - #undef OPTION_UDIMMS - #define OPTION_UDIMMS TRUE - #undef OPTION_SODIMMS - #define OPTION_SODIMMS TRUE - #undef OPTION_DDR3 - #define OPTION_DDR3 TRUE - #undef OPTION_ECC - #define OPTION_ECC TRUE - #undef OPTION_BANK_INTERLEAVE - #define OPTION_BANK_INTERLEAVE TRUE - #undef OPTION_DCT_INTERLEAVE - #define OPTION_DCT_INTERLEAVE TRUE - #undef OPTION_NODE_INTERLEAVE - #define OPTION_NODE_INTERLEAVE TRUE - #undef OPTION_PARALLEL_TRAINING - #define OPTION_PARALLEL_TRAINING TRUE - #undef OPTION_MEM_RESTORE - #define OPTION_MEM_RESTORE TRUE - #undef OPTION_ONLINE_SPARE - #define OPTION_ONLINE_SPARE TRUE - #undef OPTION_DIMM_EXCLUDE - #define OPTION_DIMM_EXCLUDE TRUE - #endif -#endif - -#if (OPTION_S1G4_SOCKET_SUPPORT == TRUE) - #if (OPTION_FAMILY10H == TRUE) - #undef OPTION_FAMILY10H_BL - #define OPTION_FAMILY10H_BL TRUE - #undef OPTION_FAMILY10H_DA - #define OPTION_FAMILY10H_DA TRUE - #undef OPTION_MEMCTLR_DA - #define OPTION_MEMCTLR_DA TRUE - #undef OPTION_HW_WRITE_LEV_TRAINING - #define OPTION_HW_WRITE_LEV_TRAINING TRUE - #undef OPTION_OPT_SW_DQS_REC_EN_TRAINING - #define OPTION_OPT_SW_DQS_REC_EN_TRAINING TRUE - #undef OPTION_OPT_SW_RD_WR_POS_TRAINING - #define OPTION_OPT_SW_RD_WR_POS_TRAINING TRUE - #undef OPTION_MAX_RD_LAT_TRAINING - #define OPTION_MAX_RD_LAT_TRAINING TRUE - #undef OPTION_SW_DRAM_INIT - #define OPTION_SW_DRAM_INIT TRUE - #undef OPTION_S3_MEM_SUPPORT - #define OPTION_S3_MEM_SUPPORT TRUE - #undef OPTION_CPU_CORELEVLING - #define OPTION_CPU_CORELEVLING TRUE - #undef OPTION_CPU_CFOH - #define OPTION_CPU_CFOH TRUE - #undef OPTION_UDIMMS - #define OPTION_UDIMMS TRUE - #undef OPTION_SODIMMS - #define OPTION_SODIMMS TRUE - #undef OPTION_DDR3 - #define OPTION_DDR3 TRUE - #undef OPTION_ECC - #define OPTION_ECC TRUE - #undef OPTION_BANK_INTERLEAVE - #define OPTION_BANK_INTERLEAVE TRUE - #undef OPTION_DCT_INTERLEAVE - #define OPTION_DCT_INTERLEAVE TRUE - #undef OPTION_NODE_INTERLEAVE - #define OPTION_NODE_INTERLEAVE TRUE - #undef OPTION_MEM_RESTORE - #define OPTION_MEM_RESTORE TRUE - #undef OPTION_DIMM_EXCLUDE - #define OPTION_DIMM_EXCLUDE TRUE - #endif -#endif - -#if (OPTION_ASB2_SOCKET_SUPPORT == TRUE) - #if (OPTION_FAMILY10H == TRUE) - #undef OPTION_FAMILY10H_BL - #define OPTION_FAMILY10H_BL TRUE - #undef OPTION_FAMILY10H_DA - #define OPTION_FAMILY10H_DA TRUE - #undef OPTION_MEMCTLR_Ni - #define OPTION_MEMCTLR_Ni TRUE - #undef OPTION_HW_WRITE_LEV_TRAINING - #define OPTION_HW_WRITE_LEV_TRAINING TRUE - #undef OPTION_OPT_SW_DQS_REC_EN_TRAINING - #define OPTION_OPT_SW_DQS_REC_EN_TRAINING TRUE - #undef OPTION_OPT_SW_RD_WR_POS_TRAINING - #define OPTION_OPT_SW_RD_WR_POS_TRAINING TRUE - #undef OPTION_MAX_RD_LAT_TRAINING - #define OPTION_MAX_RD_LAT_TRAINING TRUE - #undef OPTION_SW_DRAM_INIT - #define OPTION_SW_DRAM_INIT TRUE - #undef OPTION_S3_MEM_SUPPORT - #define OPTION_S3_MEM_SUPPORT TRUE - #undef OPTION_CPU_CORELEVLING - #define OPTION_CPU_CORELEVLING TRUE - #undef OPTION_CPU_CFOH - #define OPTION_CPU_CFOH TRUE - #undef OPTION_UDIMMS - #define OPTION_UDIMMS TRUE - #undef OPTION_SODIMMS - #define OPTION_SODIMMS TRUE - #undef OPTION_DDR3 - #define OPTION_DDR3 TRUE - #undef OPTION_ECC - #define OPTION_ECC TRUE - #undef OPTION_BANK_INTERLEAVE - #define OPTION_BANK_INTERLEAVE TRUE - #undef OPTION_DCT_INTERLEAVE - #define OPTION_DCT_INTERLEAVE TRUE - #undef OPTION_NODE_INTERLEAVE - #define OPTION_NODE_INTERLEAVE TRUE - #undef OPTION_MEM_RESTORE - #define OPTION_MEM_RESTORE TRUE - #undef OPTION_DIMM_EXCLUDE - #define OPTION_DIMM_EXCLUDE TRUE - #endif -#endif - -#if (OPTION_FS1_SOCKET_SUPPORT == TRUE) - #if (OPTION_FAMILY12H == TRUE) - #undef OPTION_FAMILY12H_LN - #define OPTION_FAMILY12H_LN TRUE - #undef OPTION_MEMCTLR_LN - #define OPTION_MEMCTLR_LN TRUE - #undef OPTION_HW_WRITE_LEV_TRAINING - #define OPTION_HW_WRITE_LEV_TRAINING TRUE - #undef OPTION_CONTINOUS_PATTERN_GENERATION - #define OPTION_CONTINOUS_PATTERN_GENERATION TRUE - #undef OPTION_HW_DQS_REC_EN_TRAINING - #define OPTION_HW_DQS_REC_EN_TRAINING TRUE - #undef OPTION_HW_DQS_REC_EN_SEED_TRAINING - #define OPTION_HW_DQS_REC_EN_SEED_TRAINING TRUE - #undef OPTION_OPT_SW_RD_WR_POS_TRAINING - #define OPTION_OPT_SW_RD_WR_POS_TRAINING TRUE - #undef OPTION_MAX_RD_LAT_TRAINING - #define OPTION_MAX_RD_LAT_TRAINING TRUE - #undef OPTION_SW_DRAM_INIT - #define OPTION_SW_DRAM_INIT TRUE - #undef OPTION_S3_MEM_SUPPORT - #define OPTION_S3_MEM_SUPPORT TRUE - #undef OPTION_GFX_RECOVERY - #define OPTION_GFX_RECOVERY TRUE - #undef OPTION_C6_STATE - #define OPTION_C6_STATE TRUE - #undef OPTION_IO_CSTATE - #define OPTION_IO_CSTATE TRUE - #undef OPTION_CPB - #define OPTION_CPB TRUE - #undef OPTION_S3SCRIPT - #define OPTION_S3SCRIPT TRUE - #undef OPTION_UDIMMS - #define OPTION_UDIMMS TRUE - #undef OPTION_SODIMMS - #define OPTION_SODIMMS TRUE - #undef OPTION_DDR3 - #define OPTION_DDR3 TRUE - #undef OPTION_BANK_INTERLEAVE - #define OPTION_BANK_INTERLEAVE TRUE - #undef OPTION_DCT_INTERLEAVE - #define OPTION_DCT_INTERLEAVE TRUE - #undef OPTION_MEM_RESTORE - #define OPTION_MEM_RESTORE TRUE - #undef OPTION_DIMM_EXCLUDE - #define OPTION_DIMM_EXCLUDE TRUE - #endif -#endif - -#if (OPTION_FM1_SOCKET_SUPPORT == TRUE) - #if (OPTION_FAMILY12H == TRUE) - #undef OPTION_FAMILY12H_LN - #define OPTION_FAMILY12H_LN TRUE - #undef OPTION_MEMCTLR_LN - #define OPTION_MEMCTLR_LN TRUE - #undef OPTION_HW_WRITE_LEV_TRAINING - #define OPTION_HW_WRITE_LEV_TRAINING TRUE - #undef OPTION_CONTINOUS_PATTERN_GENERATION - #define OPTION_CONTINOUS_PATTERN_GENERATION TRUE - #undef OPTION_HW_DQS_REC_EN_TRAINING - #define OPTION_HW_DQS_REC_EN_TRAINING TRUE - #undef OPTION_HW_DQS_REC_EN_SEED_TRAINING - #define OPTION_HW_DQS_REC_EN_SEED_TRAINING TRUE - #undef OPTION_OPT_SW_RD_WR_POS_TRAINING - #define OPTION_OPT_SW_RD_WR_POS_TRAINING TRUE - #undef OPTION_MAX_RD_LAT_TRAINING - #define OPTION_MAX_RD_LAT_TRAINING TRUE - #undef OPTION_SW_DRAM_INIT - #define OPTION_SW_DRAM_INIT TRUE - #undef OPTION_S3_MEM_SUPPORT - #define OPTION_S3_MEM_SUPPORT TRUE - #undef OPTION_GFX_RECOVERY - #define OPTION_GFX_RECOVERY TRUE - #undef OPTION_C6_STATE - #define OPTION_C6_STATE TRUE - #undef OPTION_IO_CSTATE - #define OPTION_IO_CSTATE TRUE - #undef OPTION_CPB - #define OPTION_CPB TRUE - #undef OPTION_S3SCRIPT - #define OPTION_S3SCRIPT TRUE - #undef OPTION_UDIMMS - #define OPTION_UDIMMS TRUE - #undef OPTION_SODIMMS - #define OPTION_SODIMMS TRUE - #undef OPTION_DDR3 - #define OPTION_DDR3 TRUE - #undef OPTION_BANK_INTERLEAVE - #define OPTION_BANK_INTERLEAVE TRUE - #undef OPTION_DCT_INTERLEAVE - #define OPTION_DCT_INTERLEAVE TRUE - #undef OPTION_MEM_RESTORE - #define OPTION_MEM_RESTORE TRUE - #undef OPTION_DIMM_EXCLUDE - #define OPTION_DIMM_EXCLUDE TRUE - #endif -#endif - -#if (OPTION_FP1_SOCKET_SUPPORT == TRUE) - #if (OPTION_FAMILY12H == TRUE) - #undef OPTION_FAMILY12H_LN - #define OPTION_FAMILY12H_LN TRUE - #undef OPTION_MEMCTLR_LN - #define OPTION_MEMCTLR_LN TRUE - #undef OPTION_HW_WRITE_LEV_TRAINING - #define OPTION_HW_WRITE_LEV_TRAINING TRUE - #undef OPTION_CONTINOUS_PATTERN_GENERATION - #define OPTION_CONTINOUS_PATTERN_GENERATION TRUE - #undef OPTION_HW_DQS_REC_EN_TRAINING - #define OPTION_HW_DQS_REC_EN_TRAINING TRUE - #undef OPTION_HW_DQS_REC_EN_SEED_TRAINING - #define OPTION_HW_DQS_REC_EN_SEED_TRAINING TRUE - #undef OPTION_OPT_SW_RD_WR_POS_TRAINING - #define OPTION_OPT_SW_RD_WR_POS_TRAINING TRUE - #undef OPTION_MAX_RD_LAT_TRAINING - #define OPTION_MAX_RD_LAT_TRAINING TRUE - #undef OPTION_SW_DRAM_INIT - #define OPTION_SW_DRAM_INIT TRUE - #undef OPTION_S3_MEM_SUPPORT - #define OPTION_S3_MEM_SUPPORT TRUE - #undef OPTION_ADDR_TO_CS_TRANSLATOR - #define OPTION_ADDR_TO_CS_TRANSLATOR TRUE - #undef OPTION_GFX_RECOVERY - #define OPTION_GFX_RECOVERY TRUE - #undef OPTION_C6_STATE - #define OPTION_C6_STATE TRUE - #undef OPTION_IO_CSTATE - #define OPTION_IO_CSTATE TRUE - #undef OPTION_CPB - #define OPTION_CPB TRUE - #undef OPTION_S3SCRIPT - #define OPTION_S3SCRIPT TRUE - #undef OPTION_UDIMMS - #define OPTION_UDIMMS TRUE - #undef OPTION_SODIMMS - #define OPTION_SODIMMS TRUE - #undef OPTION_DDR3 - #define OPTION_DDR3 TRUE - #undef OPTION_BANK_INTERLEAVE - #define OPTION_BANK_INTERLEAVE TRUE - #undef OPTION_DCT_INTERLEAVE - #define OPTION_DCT_INTERLEAVE TRUE - #undef OPTION_MEM_RESTORE - #define OPTION_MEM_RESTORE TRUE - #undef OPTION_ONLINE_SPARE - #define OPTION_ONLINE_SPARE TRUE - #undef OPTION_DIMM_EXCLUDE - #define OPTION_DIMM_EXCLUDE TRUE - #endif -#endif - -#if (OPTION_FT1_SOCKET_SUPPORT == TRUE) - #if (OPTION_FAMILY14H == TRUE) - #undef OPTION_FAMILY14H_ON - #define OPTION_FAMILY14H_ON TRUE - #undef OPTION_MEMCTLR_ON - #define OPTION_MEMCTLR_ON TRUE - #undef OPTION_HW_WRITE_LEV_TRAINING - #define OPTION_HW_WRITE_LEV_TRAINING TRUE - #undef OPTION_CONTINOUS_PATTERN_GENERATION - #define OPTION_CONTINOUS_PATTERN_GENERATION TRUE - #undef OPTION_MAX_RD_LAT_TRAINING - #define OPTION_MAX_RD_LAT_TRAINING TRUE - #undef OPTION_HW_DQS_REC_EN_TRAINING - #define OPTION_HW_DQS_REC_EN_TRAINING TRUE - #undef OPTION_HW_DQS_REC_EN_SEED_TRAINING - #define OPTION_HW_DQS_REC_EN_SEED_TRAINING FALSE - #undef OPTION_OPT_SW_RD_WR_POS_TRAINING - #define OPTION_OPT_SW_RD_WR_POS_TRAINING TRUE - #undef OPTION_SW_DRAM_INIT - #define OPTION_SW_DRAM_INIT TRUE - #undef OPTION_S3_MEM_SUPPORT - #define OPTION_S3_MEM_SUPPORT TRUE - #undef OPTION_GFX_RECOVERY - #define OPTION_GFX_RECOVERY TRUE - #undef OPTION_C6_STATE - #define OPTION_C6_STATE TRUE - #undef OPTION_IO_CSTATE - #define OPTION_IO_CSTATE TRUE - #undef OPTION_CPB - #define OPTION_CPB TRUE - #undef OPTION_S3SCRIPT - #define OPTION_S3SCRIPT TRUE - #undef OPTION_UDIMMS - #define OPTION_UDIMMS TRUE - #undef OPTION_SODIMMS - #define OPTION_SODIMMS TRUE - #undef OPTION_DDR3 - #define OPTION_DDR3 TRUE - #undef OPTION_BANK_INTERLEAVE - #define OPTION_BANK_INTERLEAVE TRUE - #undef OPTION_MEM_RESTORE - #define OPTION_MEM_RESTORE TRUE - #undef OPTION_DIMM_EXCLUDE - #define OPTION_DIMM_EXCLUDE TRUE - #endif -#endif - -#if (OPTION_AM3_SOCKET_SUPPORT == TRUE) - #if (OPTION_FAMILY10H == TRUE) - #undef OPTION_FAMILY10H_BL - #define OPTION_FAMILY10H_BL TRUE - #undef OPTION_FAMILY10H_DA - #define OPTION_FAMILY10H_DA TRUE - #undef OPTION_FAMILY10H_PH - #define OPTION_FAMILY10H_PH TRUE - #undef OPTION_FAMILY10H_RB - #define OPTION_FAMILY10H_RB TRUE - #undef OPTION_MEMCTLR_RB - #define OPTION_MEMCTLR_RB TRUE - #undef OPTION_MEMCTLR_DA - #define OPTION_MEMCTLR_DA TRUE - #undef OPTION_MEMCTLR_PH - #define OPTION_MEMCTLR_PH TRUE - #undef OPTION_HW_WRITE_LEV_TRAINING - #define OPTION_HW_WRITE_LEV_TRAINING TRUE - #undef OPTION_OPT_SW_DQS_REC_EN_TRAINING - #define OPTION_OPT_SW_DQS_REC_EN_TRAINING TRUE - #undef OPTION_OPT_SW_RD_WR_POS_TRAINING - #define OPTION_OPT_SW_RD_WR_POS_TRAINING TRUE - #undef OPTION_MAX_RD_LAT_TRAINING - #define OPTION_MAX_RD_LAT_TRAINING TRUE - #undef OPTION_SW_DRAM_INIT - #define OPTION_SW_DRAM_INIT TRUE - #undef OPTION_S3_MEM_SUPPORT - #define OPTION_S3_MEM_SUPPORT TRUE - #undef OPTION_CPU_CORELEVLING - #define OPTION_CPU_CORELEVLING TRUE - #undef OPTION_CPU_CFOH - #define OPTION_CPU_CFOH TRUE - #undef OPTION_IO_CSTATE - #define OPTION_IO_CSTATE TRUE - #undef OPTION_CPB - #define OPTION_CPB TRUE - #undef OPTION_UDIMMS - #define OPTION_UDIMMS TRUE - #undef OPTION_SODIMMS - #define OPTION_SODIMMS TRUE - #undef OPTION_DDR3 - #define OPTION_DDR3 TRUE - #undef OPTION_ECC - #define OPTION_ECC TRUE - #undef OPTION_BANK_INTERLEAVE - #define OPTION_BANK_INTERLEAVE TRUE - #undef OPTION_DCT_INTERLEAVE - #define OPTION_DCT_INTERLEAVE TRUE - #undef OPTION_NODE_INTERLEAVE - #define OPTION_NODE_INTERLEAVE TRUE - #undef OPTION_PARALLEL_TRAINING - #define OPTION_PARALLEL_TRAINING TRUE - #undef OPTION_MEM_RESTORE - #define OPTION_MEM_RESTORE TRUE - #undef OPTION_ONLINE_SPARE - #define OPTION_ONLINE_SPARE TRUE - #undef OPTION_DIMM_EXCLUDE - #define OPTION_DIMM_EXCLUDE TRUE - #endif - #if (OPTION_FAMILY15H == TRUE) - #undef OPTION_FAMILY15H_OR - #define OPTION_FAMILY15H_OR TRUE - #undef OPTION_MEMCTLR_OR - #define OPTION_MEMCTLR_OR TRUE - #undef OPTION_HW_WRITE_LEV_TRAINING - #define OPTION_HW_WRITE_LEV_TRAINING TRUE - #undef OPTION_CONTINOUS_PATTERN_GENERATION - #define OPTION_CONTINOUS_PATTERN_GENERATION TRUE - #undef OPTION_HW_DQS_REC_EN_TRAINING - #define OPTION_HW_DQS_REC_EN_TRAINING TRUE - #undef OPTION_HW_DQS_REC_EN_SEED_TRAINING - #define OPTION_HW_DQS_REC_EN_SEED_TRAINING TRUE - #undef OPTION_OPT_SW_RD_WR_POS_TRAINING - #define OPTION_OPT_SW_RD_WR_POS_TRAINING TRUE - #undef OPTION_MAX_RD_LAT_TRAINING - #define OPTION_MAX_RD_LAT_TRAINING TRUE - #undef OPTION_SW_DRAM_INIT - #define OPTION_SW_DRAM_INIT TRUE - #undef OPTION_C6_STATE - #define OPTION_C6_STATE TRUE - #undef OPTION_IO_CSTATE - #define OPTION_IO_CSTATE TRUE - #undef OPTION_CPB - #define OPTION_CPB TRUE - #undef OPTION_CPU_LOW_PWR_PSTATE_FOR_PROCHOT - #define OPTION_CPU_LOW_PWR_PSTATE_FOR_PROCHOT TRUE - #undef OPTION_S3_MEM_SUPPORT - #define OPTION_S3_MEM_SUPPORT TRUE - #undef OPTION_ADDR_TO_CS_TRANSLATOR - #define OPTION_ADDR_TO_CS_TRANSLATOR TRUE - #undef OPTION_ATM_MODE - #define OPTION_ATM_MODE TRUE - #undef OPTION_CPU_CORELEVLING - #define OPTION_CPU_CORELEVLING TRUE - #undef OPTION_CPU_CFOH - #define OPTION_CPU_CFOH TRUE - #undef OPTION_MSG_BASED_C1E - #define OPTION_MSG_BASED_C1E TRUE - #undef OPTION_UDIMMS - #define OPTION_UDIMMS TRUE - #undef OPTION_RDIMMS - #define OPTION_RDIMMS TRUE - #undef OPTION_LRDIMMS - #define OPTION_LRDIMMS TRUE - #undef OPTION_SODIMMS - #define OPTION_SODIMMS TRUE - #undef OPTION_DDR3 - #define OPTION_DDR3 TRUE - #undef OPTION_ECC - #define OPTION_ECC TRUE - #undef OPTION_BANK_INTERLEAVE - #define OPTION_BANK_INTERLEAVE TRUE - #undef OPTION_DCT_INTERLEAVE - #define OPTION_DCT_INTERLEAVE TRUE - #undef OPTION_NODE_INTERLEAVE - #define OPTION_NODE_INTERLEAVE TRUE - #undef OPTION_MEM_RESTORE - #define OPTION_MEM_RESTORE TRUE - #undef OPTION_ONLINE_SPARE - #define OPTION_ONLINE_SPARE TRUE - #undef OPTION_DIMM_EXCLUDE - #define OPTION_DIMM_EXCLUDE TRUE - #endif -#endif - -#if (OPTION_FAMILY12H == TRUE) || (OPTION_FAMILY14H == TRUE) - #undef GNB_SUPPORT - #define GNB_SUPPORT TRUE -#endif - -#define OPTION_ACPI_PSTATES TRUE -#define OPTION_WHEA TRUE -#define OPTION_DMI TRUE -#define OPTION_EARLY_SAMPLES FALSE -#define CFG_ACPI_PSTATES_PPC TRUE -#define CFG_ACPI_PSTATES_PCT TRUE -#define CFG_ACPI_PSTATES_PSD TRUE -#define CFG_ACPI_PSTATES_PSS TRUE -#define CFG_ACPI_PSTATES_XPSS TRUE -#define CFG_ACPI_PSTATE_PSD_INDPX FALSE -#define CFG_VRM_HIGH_SPEED_ENABLE FALSE -#define CFG_VRM_NB_HIGH_SPEED_ENABLE FALSE -#define OPTION_ALIB TRUE -/*--------------------------------------------------------------------------- - * Processing the options: Second, process the user's selections - *--------------------------------------------------------------------------*/ -#ifdef BLDOPT_REMOVE_MULTISOCKET_SUPPORT - #if BLDOPT_REMOVE_MULTISOCKET_SUPPORT == TRUE - #undef OPTION_MULTISOCKET - #define OPTION_MULTISOCKET FALSE - #endif -#endif -#ifdef BLDOPT_REMOVE_ECC_SUPPORT - #if BLDOPT_REMOVE_ECC_SUPPORT == TRUE - #undef OPTION_ECC - #define OPTION_ECC FALSE - #endif -#endif -#ifdef BLDOPT_REMOVE_UDIMMS_SUPPORT - #if BLDOPT_REMOVE_UDIMMS_SUPPORT == TRUE - #undef OPTION_UDIMMS - #define OPTION_UDIMMS FALSE - #endif -#endif -#ifdef BLDOPT_REMOVE_RDIMMS_SUPPORT - #if BLDOPT_REMOVE_RDIMMS_SUPPORT == TRUE - #undef OPTION_RDIMMS - #define OPTION_RDIMMS FALSE - #endif -#endif -#ifdef BLDOPT_REMOVE_SODIMMS_SUPPORT - #if BLDOPT_REMOVE_SODIMMS_SUPPORT == TRUE - #undef OPTION_SODIMMS - #define OPTION_SODIMMS FALSE - #endif -#endif -#ifdef BLDOPT_REMOVE_LRDIMMS_SUPPORT - #if BLDOPT_REMOVE_LRDIMMS_SUPPORT == TRUE - #undef OPTION_LRDIMMS - #define OPTION_LRDIMMS FALSE - #endif -#endif -#ifdef BLDOPT_REMOVE_BANK_INTERLEAVE - #if BLDOPT_REMOVE_BANK_INTERLEAVE == TRUE - #undef OPTION_BANK_INTERLEAVE - #define OPTION_BANK_INTERLEAVE FALSE - #endif -#endif -#ifdef BLDOPT_REMOVE_DCT_INTERLEAVE - #if BLDOPT_REMOVE_DCT_INTERLEAVE == TRUE - #undef OPTION_DCT_INTERLEAVE - #define OPTION_DCT_INTERLEAVE FALSE - #endif -#endif -#ifdef BLDOPT_REMOVE_NODE_INTERLEAVE - #if BLDOPT_REMOVE_NODE_INTERLEAVE == TRUE - #undef OPTION_NODE_INTERLEAVE - #define OPTION_NODE_INTERLEAVE FALSE - #endif -#endif -#ifdef BLDOPT_REMOVE_PARALLEL_TRAINING - #if BLDOPT_REMOVE_PARALLEL_TRAINING == TRUE - #undef OPTION_PARALLEL_TRAINING - #define OPTION_PARALLEL_TRAINING FALSE - #endif -#endif -#ifdef BLDOPT_REMOVE_ONLINE_SPARE_SUPPORT - #if BLDOPT_REMOVE_ONLINE_SPARE_SUPPORT == TRUE - #undef OPTION_ONLINE_SPARE - #define OPTION_ONLINE_SPARE FALSE - #endif -#endif -#ifdef BLDOPT_REMOVE_MEM_RESTORE_SUPPORT - #if BLDOPT_REMOVE_MEM_RESTORE_SUPPORT == TRUE - #undef OPTION_MEM_RESTORE - #define OPTION_MEM_RESTORE FALSE - #endif -#endif -#ifdef BLDOPT_REMOVE_HW_DQS_REC_EN_SEED_TRAINING - #if BLDOPT_REMOVE_HW_DQS_REC_EN_SEED_TRAINING == TRUE - #undef OPTION_HW_DQS_REC_EN_SEED_TRAINING - #define OPTION_HW_DQS_REC_EN_SEED_TRAINING FALSE - #endif -#endif -#ifdef BLDOPT_REMOVE_ACPI_PSTATES - #if BLDOPT_REMOVE_ACPI_PSTATES == TRUE - #undef OPTION_ACPI_PSTATES - #define OPTION_ACPI_PSTATES FALSE - #endif -#endif -#ifdef BLDOPT_REMOVE_SRAT - #if BLDOPT_REMOVE_SRAT == TRUE - #undef OPTION_SRAT - #define OPTION_SRAT FALSE - #endif -#endif -#ifdef BLDOPT_REMOVE_SLIT - #if BLDOPT_REMOVE_SLIT == TRUE - #undef OPTION_SLIT - #define OPTION_SLIT FALSE - #endif -#endif -#ifdef BLDOPT_REMOVE_WHEA - #if BLDOPT_REMOVE_WHEA == TRUE - #undef OPTION_WHEA - #define OPTION_WHEA FALSE - #endif -#endif -#ifdef BLDOPT_REMOVE_DMI - #if BLDOPT_REMOVE_DMI == TRUE - #undef OPTION_DMI - #define OPTION_DMI FALSE - #endif -#endif -#ifdef BLDOPT_REMOVE_ADDR_TO_CS_TRANSLATOR - #if BLDOPT_REMOVE_ADDR_TO_CS_TRANSLATOR == TRUE - #undef OPTION_ADDR_TO_CS_TRANSLATOR - #define OPTION_ADDR_TO_CS_TRANSLATOR FALSE - #endif -#endif - -#ifdef BLDOPT_REMOVE_HT_ASSIST - #if BLDOPT_REMOVE_HT_ASSIST == TRUE - #undef OPTION_HT_ASSIST - #define OPTION_HT_ASSIST FALSE - #endif -#endif - -#ifdef BLDOPT_REMOVE_ATM_MODE - #if BLDOPT_REMOVE_ATM_MODE == TRUE - #undef OPTION_ATM_MODE - #define OPTION_ATM_MODE FALSE - #endif -#endif - -#ifdef BLDOPT_REMOVE_MSG_BASED_C1E - #if BLDOPT_REMOVE_MSG_BASED_C1E == TRUE - #undef OPTION_MSG_BASED_C1E - #define OPTION_MSG_BASED_C1E FALSE - #endif -#endif - -#ifdef BLDOPT_REMOVE_C6_STATE - #if BLDOPT_REMOVE_C6_STATE == TRUE - #undef OPTION_C6_STATE - #define OPTION_C6_STATE FALSE - #endif -#endif - -#ifdef BLDOPT_REMOVE_GFX_RECOVERY - #if BLDOPT_REMOVE_GFX_RECOVERY == TRUE - #undef OPTION_GFX_RECOVERY - #define OPTION_GFX_RECOVERY FALSE - #endif -#endif - -#ifdef BLDCFG_REMOVE_ACPI_PSTATES_PPC - #if BLDCFG_REMOVE_ACPI_PSTATES_PPC == TRUE - #undef CFG_ACPI_PSTATES_PPC - #define CFG_ACPI_PSTATES_PPC FALSE - #endif -#endif - -#ifdef BLDCFG_REMOVE_ACPI_PSTATES_PCT - #if BLDCFG_REMOVE_ACPI_PSTATES_PCT == TRUE - #undef CFG_ACPI_PSTATES_PCT - #define CFG_ACPI_PSTATES_PCT FALSE - #endif -#endif - -#ifdef BLDCFG_REMOVE_ACPI_PSTATES_PSD - #if BLDCFG_REMOVE_ACPI_PSTATES_PSD == TRUE - #undef CFG_ACPI_PSTATES_PSD - #define CFG_ACPI_PSTATES_PSD FALSE - #endif -#endif - -#ifdef BLDCFG_REMOVE_ACPI_PSTATES_PSS - #if BLDCFG_REMOVE_ACPI_PSTATES_PSS == TRUE - #undef CFG_ACPI_PSTATES_PSS - #define CFG_ACPI_PSTATES_PSS FALSE - #endif -#endif - -#ifdef BLDCFG_REMOVE_ACPI_PSTATES_XPSS - #if BLDCFG_REMOVE_ACPI_PSTATES_XPSS == TRUE - #undef CFG_ACPI_PSTATES_XPSS - #define CFG_ACPI_PSTATES_XPSS FALSE - #endif -#endif - -#ifdef BLDOPT_REMOVE_LOW_PWR_PSTATE_FOR_PROCHOT - #if BLDOPT_REMOVE_LOW_PWR_PSTATE_FOR_PROCHOT == TRUE - #undef OPTION_CPU_LOW_PWR_PSTATE_FOR_PROCHOT - #define OPTION_CPU_LOW_PWR_PSTATE_FOR_PROCHOT FALSE - #endif -#endif - -#ifdef BLDCFG_FORCE_INDEPENDENT_PSD_OBJECT - #if BLDCFG_FORCE_INDEPENDENT_PSD_OBJECT == TRUE - #undef CFG_ACPI_PSTATE_PSD_INDPX - #define CFG_ACPI_PSTATE_PSD_INDPX TRUE - #endif -#endif - -#ifdef BLDCFG_VRM_HIGH_SPEED_ENABLE - #if BLDCFG_VRM_HIGH_SPEED_ENABLE == TRUE - #undef CFG_VRM_HIGH_SPEED_ENABLE - #define CFG_VRM_HIGH_SPEED_ENABLE TRUE - #endif -#endif - -#ifdef BLDCFG_VRM_NB_HIGH_SPEED_ENABLE - #if BLDCFG_VRM_NB_HIGH_SPEED_ENABLE == TRUE - #undef CFG_VRM_NB_HIGH_SPEED_ENABLE - #define CFG_VRM_NB_HIGH_SPEED_ENABLE TRUE - #endif -#endif - -#ifdef BLDCFG_STARTING_BUSNUM - #define CFG_STARTING_BUSNUM (BLDCFG_STARTING_BUSNUM) -#else - #define CFG_STARTING_BUSNUM (0) -#endif - -#ifdef BLDCFG_AMD_PLATFORM_TYPE - #define CFG_AMD_PLATFORM_TYPE BLDCFG_AMD_PLATFORM_TYPE -#else - #define CFG_AMD_PLATFORM_TYPE 0 -#endif - -CONST UINT32 ROMDATA AmdPlatformTypeCgf = CFG_AMD_PLATFORM_TYPE; - -#ifdef BLDCFG_MAXIMUM_BUSNUM - #define CFG_MAXIMUM_BUSNUM (BLDCFG_MAXIMUM_BUSNUM) -#else - #define CFG_MAXIMUM_BUSNUM (0xF8) -#endif - -#ifdef BLDCFG_ALLOCATED_BUSNUM - #define CFG_ALLOCATED_BUSNUM (BLDCFG_ALLOCATED_BUSNUM) -#else - #define CFG_ALLOCATED_BUSNUM (0x20) -#endif - -#ifdef BLDCFG_BUID_SWAP_LIST - #define CFG_BUID_SWAP_LIST (BLDCFG_BUID_SWAP_LIST) -#else - #define CFG_BUID_SWAP_LIST (NULL) -#endif - -#ifdef BLDCFG_HTDEVICE_CAPABILITIES_OVERRIDE_LIST - #define CFG_HTDEVICE_CAPABILITIES_OVERRIDE_LIST (BLDCFG_HTDEVICE_CAPABILITIES_OVERRIDE_LIST) -#else - #define CFG_HTDEVICE_CAPABILITIES_OVERRIDE_LIST (NULL) -#endif - -#ifdef BLDCFG_HTFABRIC_LIMITS_LIST - #define CFG_HTFABRIC_LIMITS_LIST (BLDCFG_HTFABRIC_LIMITS_LIST) -#else - #define CFG_HTFABRIC_LIMITS_LIST (NULL) -#endif - -#ifdef BLDCFG_HTCHAIN_LIMITS_LIST - #define CFG_HTCHAIN_LIMITS_LIST (BLDCFG_HTCHAIN_LIMITS_LIST) -#else - #define CFG_HTCHAIN_LIMITS_LIST (NULL) -#endif - -#ifdef BLDCFG_BUS_NUMBERS_LIST - #define CFG_BUS_NUMBERS_LIST (BLDCFG_BUS_NUMBERS_LIST) -#else - #define CFG_BUS_NUMBERS_LIST (NULL) -#endif - -#ifdef BLDCFG_IGNORE_LINK_LIST - #define CFG_IGNORE_LINK_LIST (BLDCFG_IGNORE_LINK_LIST) -#else - #define CFG_IGNORE_LINK_LIST (NULL) -#endif - -#ifdef BLDCFG_LINK_SKIP_REGANG_LIST - #define CFG_LINK_SKIP_REGANG_LIST (BLDCFG_LINK_SKIP_REGANG_LIST) -#else - #define CFG_LINK_SKIP_REGANG_LIST (NULL) -#endif - -#ifdef BLDCFG_SET_HTCRC_SYNC_FLOOD - #define CFG_SET_HTCRC_SYNC_FLOOD (BLDCFG_SET_HTCRC_SYNC_FLOOD) -#else - #define CFG_SET_HTCRC_SYNC_FLOOD (FALSE) -#endif - -#ifdef BLDCFG_USE_UNIT_ID_CLUMPING - #define CFG_USE_UNIT_ID_CLUMPING (BLDCFG_USE_UNIT_ID_CLUMPING) -#else - #define CFG_USE_UNIT_ID_CLUMPING (FALSE) -#endif - -#ifdef BLDCFG_ADDITIONAL_TOPOLOGIES_LIST - #define CFG_ADDITIONAL_TOPOLOGIES_LIST (BLDCFG_ADDITIONAL_TOPOLOGIES_LIST) -#else - #define CFG_ADDITIONAL_TOPOLOGIES_LIST (NULL) -#endif - -#ifdef BLDCFG_USE_HT_ASSIST - #define CFG_USE_HT_ASSIST (BLDCFG_USE_HT_ASSIST) -#else - #define CFG_USE_HT_ASSIST (TRUE) -#endif - -#ifdef BLDCFG_USE_ATM_MODE - #define CFG_USE_ATM_MODE (BLDCFG_USE_ATM_MODE) -#else - #define CFG_USE_ATM_MODE (TRUE) -#endif - -#ifdef BLDCFG_PLATFORM_CONTROL_FLOW_MODE - #define CFG_PLATFORM_CONTROL_FLOW_MODE (BLDCFG_PLATFORM_CONTROL_FLOW_MODE) -#else - #define CFG_PLATFORM_CONTROL_FLOW_MODE (Nfcm) -#endif - -#ifdef BLDCFG_PLATFORM_DEEMPHASIS_LIST - #define CFG_PLATFORM_DEEMPHASIS_LIST (BLDCFG_PLATFORM_DEEMPHASIS_LIST) -#else - #define CFG_PLATFORM_DEEMPHASIS_LIST (NULL) -#endif - -#ifdef BLDCFG_VRM_ADDITIONAL_DELAY - #define CFG_VRM_ADDITIONAL_DELAY (BLDCFG_VRM_ADDITIONAL_DELAY) -#else - #define CFG_VRM_ADDITIONAL_DELAY (0) -#endif - -#ifdef BLDCFG_VRM_CURRENT_LIMIT - #define CFG_VRM_CURRENT_LIMIT BLDCFG_VRM_CURRENT_LIMIT -#else - #define CFG_VRM_CURRENT_LIMIT 0 -#endif - -#ifdef BLDCFG_VRM_LOW_POWER_THRESHOLD - #define CFG_VRM_LOW_POWER_THRESHOLD BLDCFG_VRM_LOW_POWER_THRESHOLD -#else - #define CFG_VRM_LOW_POWER_THRESHOLD 0 -#endif - -#ifdef BLDCFG_VRM_SLEW_RATE - #define CFG_VRM_SLEW_RATE BLDCFG_VRM_SLEW_RATE -#else - #define CFG_VRM_SLEW_RATE DFLT_VRM_SLEW_RATE -#endif - -#ifdef BLDCFG_VRM_INRUSH_CURRENT_LIMIT - #define CFG_VRM_INRUSH_CURRENT_LIMIT BLDCFG_VRM_INRUSH_CURRENT_LIMIT -#else - #define CFG_VRM_INRUSH_CURRENT_LIMIT 0 -#endif - -#ifdef BLDCFG_VRM_NB_ADDITIONAL_DELAY - #define CFG_VRM_NB_ADDITIONAL_DELAY (BLDCFG_VRM_NB_ADDITIONAL_DELAY) -#else - #define CFG_VRM_NB_ADDITIONAL_DELAY (0) -#endif - -#ifdef BLDCFG_VRM_NB_CURRENT_LIMIT - #define CFG_VRM_NB_CURRENT_LIMIT BLDCFG_VRM_NB_CURRENT_LIMIT -#else - #define CFG_VRM_NB_CURRENT_LIMIT (0) -#endif - -#ifdef BLDCFG_VRM_NB_LOW_POWER_THRESHOLD - #define CFG_VRM_NB_LOW_POWER_THRESHOLD BLDCFG_VRM_NB_LOW_POWER_THRESHOLD -#else - #define CFG_VRM_NB_LOW_POWER_THRESHOLD (0) -#endif - -#ifdef BLDCFG_VRM_NB_SLEW_RATE - #define CFG_VRM_NB_SLEW_RATE BLDCFG_VRM_NB_SLEW_RATE -#else - #define CFG_VRM_NB_SLEW_RATE DFLT_VRM_SLEW_RATE -#endif - -#ifdef BLDCFG_VRM_NB_INRUSH_CURRENT_LIMIT - #define CFG_VRM_NB_INRUSH_CURRENT_LIMIT BLDCFG_VRM_NB_INRUSH_CURRENT_LIMIT -#else - #define CFG_VRM_NB_INRUSH_CURRENT_LIMIT (0) -#endif - - -#ifdef BLDCFG_PLAT_NUM_IO_APICS - #define CFG_PLAT_NUM_IO_APICS BLDCFG_PLAT_NUM_IO_APICS -#else - #define CFG_PLAT_NUM_IO_APICS 0 -#endif - -#ifdef BLDCFG_MEM_INIT_PSTATE - #define CFG_MEM_INIT_PSTATE BLDCFG_MEM_INIT_PSTATE -#else - #define CFG_MEM_INIT_PSTATE 0 -#endif - -#ifdef BLDCFG_PLATFORM_C1E_MODE - #define CFG_C1E_MODE BLDCFG_PLATFORM_C1E_MODE -#else - #define CFG_C1E_MODE C1eModeDisabled -#endif - -#ifdef BLDCFG_PLATFORM_C1E_OPDATA - #define CFG_C1E_OPDATA BLDCFG_PLATFORM_C1E_OPDATA -#else - #define CFG_C1E_OPDATA 0 -#endif - -#ifdef BLDCFG_PLATFORM_C1E_OPDATA1 - #define CFG_C1E_OPDATA1 BLDCFG_PLATFORM_C1E_OPDATA1 -#else - #define CFG_C1E_OPDATA1 0 -#endif - -#ifdef BLDCFG_PLATFORM_C1E_OPDATA2 - #define CFG_C1E_OPDATA2 BLDCFG_PLATFORM_C1E_OPDATA2 -#else - #define CFG_C1E_OPDATA2 0 -#endif - -#ifdef BLDCFG_PLATFORM_C1E_OPDATA3 - #define CFG_C1E_OPDATA3 BLDCFG_PLATFORM_C1E_OPDATA3 -#else - #define CFG_C1E_OPDATA3 0 -#endif - -#ifdef BLDCFG_PLATFORM_CSTATE_MODE - #define CFG_CSTATE_MODE BLDCFG_PLATFORM_CSTATE_MODE -#else - #define CFG_CSTATE_MODE CStateModeDisabled -#endif - -#ifdef BLDCFG_PLATFORM_CSTATE_OPDATA - #define CFG_CSTATE_OPDATA BLDCFG_PLATFORM_CSTATE_OPDATA -#else - #define CFG_CSTATE_OPDATA 0 -#endif - -#ifdef BLDCFG_PLATFORM_CSTATE_IO_BASE_ADDRESS - #define CFG_CSTATE_IO_BASE_ADDRESS BLDCFG_PLATFORM_CSTATE_IO_BASE_ADDRESS -#else - #define CFG_CSTATE_IO_BASE_ADDRESS 0 -#endif - -#ifdef BLDCFG_PLATFORM_CPB_MODE - #define CFG_CPB_MODE BLDCFG_PLATFORM_CPB_MODE -#else - #define CFG_CPB_MODE CpbModeAuto -#endif - -#ifdef BLDCFG_CORE_LEVELING_MODE - #define CFG_CORE_LEVELING_MODE BLDCFG_CORE_LEVELING_MODE -#else - #define CFG_CORE_LEVELING_MODE 0 -#endif - -#ifdef BLDCFG_AMD_PSTATE_CAP_VALUE - #define CFG_AMD_PSTATE_CAP_VALUE BLDCFG_AMD_PSTATE_CAP_VALUE -#else - #define CFG_AMD_PSTATE_CAP_VALUE 0 -#endif - -#ifdef BLDCFG_HEAP_DRAM_ADDRESS - #define CFG_HEAP_DRAM_ADDRESS BLDCFG_HEAP_DRAM_ADDRESS -#else - #define CFG_HEAP_DRAM_ADDRESS AMD_HEAP_RAM_ADDRESS -#endif - -#ifdef BLDCFG_MEMORY_BUS_FREQUENCY_LIMIT - #define CFG_MEMORY_BUS_FREQUENCY_LIMIT BLDCFG_MEMORY_BUS_FREQUENCY_LIMIT -#else - #define CFG_MEMORY_BUS_FREQUENCY_LIMIT DDR800_FREQUENCY -#endif - -#ifdef BLDCFG_MEMORY_MODE_UNGANGED - #define CFG_MEMORY_MODE_UNGANGED BLDCFG_MEMORY_MODE_UNGANGED -#else - #define CFG_MEMORY_MODE_UNGANGED TRUE -#endif - -#ifdef BLDCFG_MEMORY_QUAD_RANK_CAPABLE - #define CFG_MEMORY_QUAD_RANK_CAPABLE BLDCFG_MEMORY_QUAD_RANK_CAPABLE -#else - #define CFG_MEMORY_QUAD_RANK_CAPABLE TRUE -#endif - -#ifdef BLDCFG_MEMORY_QUADRANK_TYPE - #define CFG_MEMORY_QUADRANK_TYPE BLDCFG_MEMORY_QUADRANK_TYPE -#else - #define CFG_MEMORY_QUADRANK_TYPE DFLT_MEMORY_QUADRANK_TYPE -#endif - -#ifdef BLDCFG_MEMORY_RDIMM_CAPABLE - #define CFG_MEMORY_RDIMM_CAPABLE BLDCFG_MEMORY_RDIMM_CAPABLE -#else - #define CFG_MEMORY_RDIMM_CAPABLE TRUE -#endif - -#ifdef BLDCFG_MEMORY_LRDIMM_CAPABLE - #define CFG_MEMORY_LRDIMM_CAPABLE BLDCFG_MEMORY_LRDIMM_CAPABLE -#else - #define CFG_MEMORY_LRDIMM_CAPABLE TRUE -#endif - -#ifdef BLDCFG_MEMORY_UDIMM_CAPABLE - #define CFG_MEMORY_UDIMM_CAPABLE BLDCFG_MEMORY_UDIMM_CAPABLE -#else - #define CFG_MEMORY_UDIMM_CAPABLE TRUE -#endif - -#ifdef BLDCFG_MEMORY_SODIMM_CAPABLE - #define CFG_MEMORY_SODIMM_CAPABLE BLDCFG_MEMORY_SODIMM_CAPABLE -#else - #define CFG_MEMORY_SODIMM_CAPABLE FALSE -#endif - -#ifdef BLDCFG_LIMIT_MEMORY_TO_BELOW_1TB - #define CFG_LIMIT_MEMORY_TO_BELOW_1TB BLDCFG_LIMIT_MEMORY_TO_BELOW_1TB -#else - #define CFG_LIMIT_MEMORY_TO_BELOW_1TB TRUE -#endif - -#ifdef BLDCFG_MEMORY_ENABLE_BANK_INTERLEAVING - #define CFG_MEMORY_ENABLE_BANK_INTERLEAVING BLDCFG_MEMORY_ENABLE_BANK_INTERLEAVING -#else - #define CFG_MEMORY_ENABLE_BANK_INTERLEAVING TRUE -#endif - -#ifdef BLDCFG_MEMORY_ENABLE_NODE_INTERLEAVING - #define CFG_MEMORY_ENABLE_NODE_INTERLEAVING BLDCFG_MEMORY_ENABLE_NODE_INTERLEAVING -#else - #define CFG_MEMORY_ENABLE_NODE_INTERLEAVING FALSE -#endif - -#ifdef BLDCFG_MEMORY_CHANNEL_INTERLEAVING - #define CFG_MEMORY_CHANNEL_INTERLEAVING BLDCFG_MEMORY_CHANNEL_INTERLEAVING -#else - #define CFG_MEMORY_CHANNEL_INTERLEAVING TRUE -#endif - -#ifdef BLDCFG_MEMORY_POWER_DOWN - #define CFG_MEMORY_POWER_DOWN BLDCFG_MEMORY_POWER_DOWN -#else - #define CFG_MEMORY_POWER_DOWN FALSE -#endif - -#ifdef BLDCFG_POWER_DOWN_MODE - #define CFG_POWER_DOWN_MODE BLDCFG_POWER_DOWN_MODE -#else - #define CFG_POWER_DOWN_MODE POWER_DOWN_MODE_AUTO -#endif - -#ifdef BLDCFG_ONLINE_SPARE - #define CFG_ONLINE_SPARE BLDCFG_ONLINE_SPARE -#else - #define CFG_ONLINE_SPARE FALSE -#endif - -#ifdef BLDCFG_MEMORY_PARITY_ENABLE - #define CFG_MEMORY_PARITY_ENABLE BLDCFG_MEMORY_PARITY_ENABLE -#else - #define CFG_MEMORY_PARITY_ENABLE FALSE -#endif - -#ifdef BLDCFG_BANK_SWIZZLE - #define CFG_BANK_SWIZZLE BLDCFG_BANK_SWIZZLE -#else - #define CFG_BANK_SWIZZLE TRUE -#endif - -#ifdef BLDCFG_TIMING_MODE_SELECT - #define CFG_TIMING_MODE_SELECT BLDCFG_TIMING_MODE_SELECT -#else - #define CFG_TIMING_MODE_SELECT TIMING_MODE_AUTO -#endif - -#ifdef BLDCFG_MEMORY_CLOCK_SELECT - #define CFG_MEMORY_CLOCK_SELECT BLDCFG_MEMORY_CLOCK_SELECT -#else - #define CFG_MEMORY_CLOCK_SELECT DDR800_FREQUENCY -#endif - -#ifdef BLDCFG_DQS_TRAINING_CONTROL - #define CFG_DQS_TRAINING_CONTROL BLDCFG_DQS_TRAINING_CONTROL -#else - #define CFG_DQS_TRAINING_CONTROL TRUE -#endif - -#ifdef BLDCFG_IGNORE_SPD_CHECKSUM - #define CFG_IGNORE_SPD_CHECKSUM BLDCFG_IGNORE_SPD_CHECKSUM -#else - #define CFG_IGNORE_SPD_CHECKSUM FALSE -#endif - -#ifdef BLDCFG_USE_BURST_MODE - #define CFG_USE_BURST_MODE BLDCFG_USE_BURST_MODE -#else - #define CFG_USE_BURST_MODE FALSE -#endif - -#ifdef BLDCFG_MEMORY_ALL_CLOCKS_ON - #define CFG_MEMORY_ALL_CLOCKS_ON BLDCFG_MEMORY_ALL_CLOCKS_ON -#else - #define CFG_MEMORY_ALL_CLOCKS_ON FALSE -#endif - -#ifdef BLDCFG_ENABLE_ECC_FEATURE - #define CFG_ENABLE_ECC_FEATURE BLDCFG_ENABLE_ECC_FEATURE -#else - #define CFG_ENABLE_ECC_FEATURE TRUE -#endif - -#ifdef BLDCFG_ECC_REDIRECTION - #define CFG_ECC_REDIRECTION BLDCFG_ECC_REDIRECTION -#else - #define CFG_ECC_REDIRECTION FALSE -#endif - -#ifdef BLDCFG_SCRUB_DRAM_RATE - #define CFG_SCRUB_DRAM_RATE BLDCFG_SCRUB_DRAM_RATE -#else - #define CFG_SCRUB_DRAM_RATE DFLT_SCRUB_DRAM_RATE -#endif - -#ifdef BLDCFG_SCRUB_L2_RATE - #define CFG_SCRUB_L2_RATE BLDCFG_SCRUB_L2_RATE -#else - #define CFG_SCRUB_L2_RATE DFLT_SCRUB_L2_RATE -#endif - -#ifdef BLDCFG_SCRUB_L3_RATE - #define CFG_SCRUB_L3_RATE BLDCFG_SCRUB_L3_RATE -#else - #define CFG_SCRUB_L3_RATE DFLT_SCRUB_L3_RATE -#endif - -#ifdef BLDCFG_SCRUB_IC_RATE - #define CFG_SCRUB_IC_RATE BLDCFG_SCRUB_IC_RATE -#else - #define CFG_SCRUB_IC_RATE DFLT_SCRUB_IC_RATE -#endif - -#ifdef BLDCFG_SCRUB_DC_RATE - #define CFG_SCRUB_DC_RATE BLDCFG_SCRUB_DC_RATE -#else - #define CFG_SCRUB_DC_RATE DFLT_SCRUB_DC_RATE -#endif - -#ifdef BLDCFG_ECC_SYNC_FLOOD - #define CFG_ECC_SYNC_FLOOD BLDCFG_ECC_SYNC_FLOOD -#else - #define CFG_ECC_SYNC_FLOOD TRUE -#endif - -#ifdef BLDCFG_ECC_SYMBOL_SIZE - #define CFG_ECC_SYMBOL_SIZE BLDCFG_ECC_SYMBOL_SIZE -#else - #define CFG_ECC_SYMBOL_SIZE 0 -#endif - -#ifdef BLDCFG_1GB_ALIGN - #define CFG_1GB_ALIGN BLDCFG_1GB_ALIGN -#else - #define CFG_1GB_ALIGN FALSE -#endif - -#ifdef BLDCFG_UMA_ALLOCATION_MODE - #define CFG_UMA_MODE BLDCFG_UMA_ALLOCATION_MODE -#else - #define CFG_UMA_MODE UMA_AUTO -#endif - -#ifdef BLDCFG_UMA_ALLOCATION_SIZE - #define CFG_UMA_SIZE BLDCFG_UMA_ALLOCATION_SIZE -#else - #define CFG_UMA_SIZE 0 -#endif - -#ifdef BLDCFG_UMA_ABOVE4G_SUPPORT - #define CFG_UMA_ABOVE4G BLDCFG_UMA_ABOVE4G_SUPPORT -#else - #define CFG_UMA_ABOVE4G FALSE -#endif - -#ifdef BLDCFG_UMA_ALIGNMENT - #define CFG_UMA_ALIGNMENT BLDCFG_UMA_ALIGNMENT -#else - #define CFG_UMA_ALIGNMENT NO_UMA_ALIGNED -#endif - -#ifdef BLDCFG_PROCESSOR_SCOPE_IN_SB - #define CFG_PROCESSOR_SCOPE_IN_SB BLDCFG_PROCESSOR_SCOPE_IN_SB -#else - #define CFG_PROCESSOR_SCOPE_IN_SB FALSE -#endif - -#ifdef BLDCFG_S3_LATE_RESTORE - #define CFG_S3_LATE_RESTORE BLDCFG_S3_LATE_RESTORE -#else - #define CFG_S3_LATE_RESTORE TRUE -#endif - -#ifdef BLDCFG_USE_32_BYTE_REFRESH - #define CFG_USE_32_BYTE_REFRESH (BLDCFG_USE_32_BYTE_REFRESH) -#else - #define CFG_USE_32_BYTE_REFRESH (FALSE) -#endif - -#ifdef BLDCFG_USE_VARIABLE_MCT_ISOC_PRIORITY - #define CFG_USE_VARIABLE_MCT_ISOC_PRIORITY (BLDCFG_USE_VARIABLE_MCT_ISOC_PRIORITY) -#else - #define CFG_USE_VARIABLE_MCT_ISOC_PRIORITY (FALSE) -#endif - -#ifdef BLDCFG_PROCESSOR_SCOPE_NAME0 - #define CFG_PROCESSOR_SCOPE_NAME0 BLDCFG_PROCESSOR_SCOPE_NAME0 -#else - #define CFG_PROCESSOR_SCOPE_NAME0 SCOPE_NAME_VALUE -#endif - -#ifdef BLDCFG_PROCESSOR_SCOPE_NAME1 - #define CFG_PROCESSOR_SCOPE_NAME1 BLDCFG_PROCESSOR_SCOPE_NAME1 -#else - #define CFG_PROCESSOR_SCOPE_NAME1 SCOPE_NAME_VALUE1 -#endif - -#ifdef BLDCFG_CFG_GNB_HD_AUDIO - #define CFG_GNB_HD_AUDIO BLDCFG_CFG_GNB_HD_AUDIO -#else - #define CFG_GNB_HD_AUDIO TRUE -#endif - -#ifdef BLDCFG_CFG_ABM_SUPPORT - #define CFG_ABM_SUPPORT BLDCFG_CFG_ABM_SUPPORT -#else - #define CFG_ABM_SUPPORT FALSE -#endif - -#ifdef BLDCFG_CFG_DYNAMIC_REFRESH_RATE - #define CFG_DINAMIC_REFRESH_RATE BLDCFG_CFG_DYNAMIC_REFRESH_RATE -#else - #define CFG_DYNAMIC_REFRESH_RATE 0 -#endif - -#ifdef BLDCFG_CFG_LCD_BACK_LIGHT_CONTROL - #define CFG_LCD_BACK_LIGHT_CONTROL BLDCFG_CFG_LCD_BACK_LIGHT_CONTROL -#else - #define CFG_LCD_BACK_LIGHT_CONTROL 0 -#endif - -#ifdef BLDCFG_STEREO_3D_PINOUT - #define CFG_GNB_STEREO_3D_PINOUT BLDCFG_STEREO_3D_PINOUT -#else - #define CFG_GNB_STEREO_3D_PINOUT 0 -#endif - -#ifdef BLDCFG_IGPU_SUBSYSTEM_ID - #define CFG_GNB_IGPU_SSID BLDCFG_IGPU_SUBSYSTEM_ID -#else - #define CFG_GNB_IGPU_SSID 0 -#endif - -#ifdef BLDCFG_IGPU_HD_AUDIO_SUBSYSTEM_ID - #define CFG_GNB_HDAUDIO_SSID BLDCFG_IGPU_HD_AUDIO_SUBSYSTEM_ID -#else - #define CFG_GNB_HDAUDIO_SSID 0 -#endif - -#ifdef BLFCFG_APU_PCIE_PORTS_SUBSYSTEM_ID - #define CFG_GNB_PCIE_SSID BLFCFG_APU_PCIE_PORTS_SUBSYSTEM_ID -#else - #define CFG_GNB_PCIE_SSID 0x12341022 -#endif - -#ifdef BLDCFG_GFX_LVDS_SPREAD_SPECTRUM - #define CFG_GFX_LVDS_SPREAD_SPECTRUM BLDCFG_GFX_LVDS_SPREAD_SPECTRUM -#else - #define CFG_GFX_LVDS_SPREAD_SPECTRUM 0 -#endif - -#ifdef BLDCFG_GFX_LVDS_SPREAD_SPECTRUM_RATE - #define CFG_GFX_LVDS_SPREAD_SPECTRUM_RATE BLDCFG_GFX_LVDS_SPREAD_SPECTRUM_RATE -#else - #define CFG_GFX_LVDS_SPREAD_SPECTRUM_RATE 0 -#endif - -#ifdef BLDCFG_PCIE_REFCLK_SPREAD_SPECTRUM - #define CFG_PCIE_REFCLK_SPREAD_SPECTRUM BLDCFG_PCIE_REFCLK_SPREAD_SPECTRUM -#else - #define CFG_PCIE_REFCLK_SPREAD_SPECTRUM 0 -#endif - -#ifdef BLDCFG_CFG_TEMP_PCIE_MMIO_BASE_ADDRESS - #define CFG_TEMP_PCIE_MMIO_BASE_ADDRESS BLDCFG_CFG_TEMP_PCIE_MMIO_BASE_ADDRESS -#else - #define CFG_TEMP_PCIE_MMIO_BASE_ADDRESS 0xD0000000 -#endif - -#ifdef BLDOPT_REMOVE_EARLY_SAMPLES - #if BLDOPT_REMOVE_EARLY_SAMPLES == TRUE - #undef OPTION_EARLY_SAMPLES - #define OPTION_EARLY_SAMPLES FALSE - #else - #undef OPTION_EARLY_SAMPLES - #define OPTION_EARLY_SAMPLES TRUE - #endif -#endif - -#ifdef BLDOPT_REMOVE_ALIB - #if BLDOPT_REMOVE_ALIB == TRUE - #undef OPTION_ALIB - #define OPTION_ALIB FALSE - #else - #undef OPTION_ALIB - #define OPTION_ALIB TRUE - #endif -#endif - -#ifdef BLDCFG_IOMMU_SUPPORT - #define CFG_IOMMU_SUPPORT BLDCFG_IOMMU_SUPPORT -#else - #define CFG_IOMMU_SUPPORT TRUE -#endif - -#ifdef BLDCFG_LVDS_POWER_ON_SEQ_DIGON_TO_DE - #define CFG_LVDS_POWER_ON_SEQ_DIGON_TO_DE BLDCFG_LVDS_POWER_ON_SEQ_DIGON_TO_DE -#else - #define CFG_LVDS_POWER_ON_SEQ_DIGON_TO_DE 0 -#endif - -#ifdef BLDCFG_LVDS_POWER_ON_SEQ_DE_TO_VARY_BL - #define CFG_LVDS_POWER_ON_SEQ_DE_TO_VARY_BL BLDCFG_LVDS_POWER_ON_SEQ_DE_TO_VARY_BL -#else - #define CFG_LVDS_POWER_ON_SEQ_DE_TO_VARY_BL 0 -#endif - -#ifdef BLDCFG_LVDS_POWER_ON_SEQ_DE_TO_DIGON - #define CFG_LVDS_POWER_ON_SEQ_DE_TO_DIGON BLDCFG_LVDS_POWER_ON_SEQ_DE_TO_DIGON -#else - #define CFG_LVDS_POWER_ON_SEQ_DE_TO_DIGON 0 -#endif - -#ifdef BLDCFG_LVDS_POWERS_ON_SEQ_VARY_BL_TO_DE - #define CFG_LVDS_POWERS_ON_SEQ_VARY_BL_TO_DE BLDCFG_LVDS_POWERS_ON_SEQ_VARY_BL_TO_DE -#else - #define CFG_LVDS_POWERS_ON_SEQ_VARY_BL_TO_DE 0 -#endif - -#ifdef BLDCFG_LVDS_POWER_ON_SEQ_ON_TO_OFF_DELAY - #define CFG_LVDS_POWER_ON_SEQ_ON_TO_OFF_DELAY BLDCFG_LVDS_POWER_ON_SEQ_ON_TO_OFF_DELAY -#else - #define CFG_LVDS_POWER_ON_SEQ_ON_TO_OFF_DELAY 0 -#endif - -#ifdef BLDCFG_LVDS_POWER_ON_SEQ_VARY_BL_TO_BLON - #define CFG_LVDS_POWER_ON_SEQ_VARY_BL_TO_BLON BLDCFG_LVDS_POWER_ON_SEQ_VARY_BL_TO_BLON -#else - #define CFG_LVDS_POWER_ON_SEQ_VARY_BL_TO_BLON 0 -#endif - -#ifdef BLDCFG_LVDS_POWER_ON_SEQ_BLON_TO_VARY_BL - #define CFG_LVDS_POWER_ON_SEQ_BLON_TO_VARY_BL BLDCFG_LVDS_POWER_ON_SEQ_BLON_TO_VARY_BL -#else - #define CFG_LVDS_POWER_ON_SEQ_BLON_TO_VARY_BL 0 -#endif - -#ifdef BLDCFG_LVDS_MAX_PIXEL_CLOCK_FREQ - #define CFG_LVDS_MAX_PIXEL_CLOCK_FREQ BLDCFG_LVDS_MAX_PIXEL_CLOCK_FREQ -#else - #define CFG_LVDS_MAX_PIXEL_CLOCK_FREQ 0 -#endif - -#ifdef BLDCFG_LCD_BIT_DEPTH_CONTROL_VALUE - #define CFG_LCD_BIT_DEPTH_CONTROL_VALUE BLDCFG_LCD_BIT_DEPTH_CONTROL_VALUE -#else - #define CFG_LCD_BIT_DEPTH_CONTROL_VALUE 0 -#endif - - -// BLDCFG_LVDS_24BBP_PANEL_MODE -// This specifies the LVDS 24 BBP mode. -// 0 - Use LDI mode (default). -// 1 - Use FPDI mode. -#ifdef BLDCFG_LVDS_24BBP_PANEL_MODE - #define CFG_LVDS_24BBP_PANEL_MODE BLDCFG_LVDS_24BBP_PANEL_MODE -#else - #define CFG_LVDS_24BBP_PANEL_MODE 0 -#endif - -#ifdef BLDCFG_PLATFORM_POWER_POLICY_MODE - #define CFG_PLATFORM_POWER_POLICY_MODE (BLDCFG_PLATFORM_POWER_POLICY_MODE) -#else - #define CFG_PLATFORM_POWER_POLICY_MODE (Performance) -#endif - -#ifdef BLDCFG_PCI_MMIO_BASE - #define CFG_PCI_MMIO_BASE (BLDCFG_PCI_MMIO_BASE) -#else - #define CFG_PCI_MMIO_BASE (0) -#endif - -#ifdef BLDCFG_PCI_MMIO_SIZE - #define CFG_PCI_MMIO_SIZE (BLDCFG_PCI_MMIO_SIZE) -#else - #define CFG_PCI_MMIO_SIZE (0) -#endif - -#ifdef BLDCFG_AP_MTRR_SETTINGS_LIST - #define CFG_AP_MTRR_SETTINGS_LIST (BLDCFG_AP_MTRR_SETTINGS_LIST) -#else - #define CFG_AP_MTRR_SETTINGS_LIST (NULL) -#endif - -/*--------------------------------------------------------------------------- - * Processing the options: Third, perform the option cross checks - *--------------------------------------------------------------------------*/ -// Assure that at least one type of memory support is included -#if OPTION_UDIMMS == FALSE - #if OPTION_RDIMMS == FALSE - #if OPTION_SODIMMS == FALSE - #if OPTION_LRDIMMS == FALSE - #error BLDOPT: No DIMM support selected. Either BLDOPT_REMOVE_UDIMMS_SUPPORT or BLDOPT_REMOVE_RDIMMS_SUPPORT or BLDOPT_REMOVE_SODIMMS_SUPPORT or BLDOPT_REMOVE_LRDIMMS_SUPPORT must be FALSE. - #endif - #endif - #endif -#endif -// Ensure at least one dimm type is capable -#if CFG_MEMORY_RDIMM_CAPABLE == FALSE - #if CFG_MEMORY_UDIMM_CAPABLE == FALSE - #if CFG_MEMORY_SODIMM_CAPABLE == FALSE - #if CFG_MEMORY_LRDIMM_CAPABLE == FALSE - #error BLDCFG: No dimm type is capable - #endif - #endif - #endif -#endif -// Turn off multi-socket based features if only one node... -#if OPTION_MULTISOCKET == FALSE - #undef OPTION_PARALLEL_TRAINING - #define OPTION_PARALLEL_TRAINING FALSE - #undef OPTION_NODE_INTERLEAVE - #define OPTION_NODE_INTERLEAVE FALSE -#endif -// Ensure that at least one write leveling option is selected -#if OPTION_DDR3 == TRUE - #if OPTION_HW_WRITE_LEV_TRAINING == FALSE - #if OPTION_SW_WRITE_LEV_TRAINING == FALSE - #error No Write leveling option selected for DDR3 - #endif - #endif - #if OPTION_SW_DRAM_INIT == FALSE - #error Software dram init must be enabled for DDR3 dimms - #endif -#endif -// Ensure at least one DQS receiver training option is selected -#if OPTION_HW_DQS_REC_EN_TRAINING == FALSE - #if OPTION_NON_OPT_SW_DQS_REC_EN_TRAINING == FALSE - #if OPTION_OPT_SW_DQS_REC_EN_TRAINING == FALSE - #error No DQS receiver training option has been slected - #endif - #endif -#endif -// Ensure at least one Rd Wr position training option has been selected -#if OPTION_NON_OPT_SW_RD_WR_POS_TRAINING == FALSE - #if OPTION_OPT_SW_RD_WR_POS_TRAINING == FALSE - #error No Rd Wr position training option has been selected - #endif -#endif -// Ensure at least one dram init option has been selected -#if OPTION_HW_DRAM_INIT == FALSE - #if OPTION_SW_DRAM_INIT == FALSE - #error No Dram init option has been selected - #endif -#endif -/* As an ENUM, DDRXXX_FREQUENCY is not defined when the c preprocessor runs. - * Removing this test for coreboot. - */ -#if RUN_BROKEN_AGESA_TESTS -// Ensure the frequency limit is valid -#if (CFG_MEMORY_BUS_FREQUENCY_LIMIT != DDR1866_FREQUENCY) && (CFG_MEMORY_BUS_FREQUENCY_LIMIT != 933) - #if (CFG_MEMORY_BUS_FREQUENCY_LIMIT != DDR1600_FREQUENCY) && (CFG_MEMORY_BUS_FREQUENCY_LIMIT != 800) - #if (CFG_MEMORY_BUS_FREQUENCY_LIMIT != DDR1333_FREQUENCY) && (CFG_MEMORY_BUS_FREQUENCY_LIMIT != 667) - #if (CFG_MEMORY_BUS_FREQUENCY_LIMIT != DDR1066_FREQUENCY) && (CFG_MEMORY_BUS_FREQUENCY_LIMIT != 533) - #if (CFG_MEMORY_BUS_FREQUENCY_LIMIT != DDR800_FREQUENCY) && (CFG_MEMORY_BUS_FREQUENCY_LIMIT != 400) - #if (CFG_MEMORY_BUS_FREQUENCY_LIMIT != DDR667_FREQUENCY) && (CFG_MEMORY_BUS_FREQUENCY_LIMIT != 333) - #if (CFG_MEMORY_BUS_FREQUENCY_LIMIT != DDR533_FREQUENCY) && (CFG_MEMORY_BUS_FREQUENCY_LIMIT != 266) - #if (CFG_MEMORY_BUS_FREQUENCY_LIMIT != DDR400_FREQUENCY) && (CFG_MEMORY_BUS_FREQUENCY_LIMIT != 200) - #error BLDCFG: Unsupported memory bus frequency - #endif - #endif - #endif - #endif - #endif - #endif - #endif -#endif - -#endif -/* As an ENUM, TIMING_MODE_XXX is not defined when the c preprocessor runs. - * Removing this test for coreboot. - */ -#if RUN_BROKEN_AGESA_TESTS - -// Ensure timing mode is valid -#if CFG_TIMING_MODE_SELECT != TIMING_MODE_SPECIFIC - #if CFG_TIMING_MODE_SELECT != TIMING_MODE_LIMITED - #if CFG_TIMING_MODE_SELECT != TIMING_MODE_AUTO - #error BLDCFG: Invalid timing mode is set - #endif - #endif -#endif - -#endif -// Ensure the scrub rate is valid -#if ((CFG_SCRUB_DRAM_RATE > 0x16) && (CFG_SCRUB_DRAM_RATE != 0xFF)) - #error BLDCFG: Unsupported dram scrub rate set -#endif -#if CFG_SCRUB_L2_RATE > 0x16 - #error BLDCFG: Unsupported L2 scrubber rate set -#endif -#if CFG_SCRUB_L3_RATE > 0x16 - #error BLDCFG: unsupported L3 scrubber rate set -#endif -#if CFG_SCRUB_IC_RATE > 0x16 - #error BLDCFG: Unsupported Instruction cache scrub rate set -#endif -#if CFG_SCRUB_DC_RATE > 0x16 - #error BLDCFG: Unsupported Dcache scrub rate set -#endif -/* As an ENUM, QUADRANK_XXX is not defined when the c preprocessor runs. - * Removing this test for coreboot. - */ -#if RUN_BROKEN_AGESA_TESTS - -// Ensure Quad rank dimm type is valid -#if CFG_MEMORY_QUADRANK_TYPE != QUADRANK_UNBUFFERED - #if CFG_MEMORY_QUADRANK_TYPE != QUADRANK_REGISTERED - #error BLDCFG: Invalid quad rank dimm type set - #endif -#endif - -#endif -// Ensure ECC symbol size is valid -#if CFG_ECC_SYMBOL_SIZE != ECCSYMBOLSIZE_USE_BKDG - #if CFG_ECC_SYMBOL_SIZE != ECCSYMBOLSIZE_FORCE_X4 - #if CFG_ECC_SYMBOL_SIZE != ECCSYMBOLSIZE_FORCE_X8 - #error BLDCFG: Invalid Ecc symbol size set - #endif - #endif -#endif -/* As an ENUM, POWER_DOWN_BY_XXX is not defined when the c preprocessor runs. - * Removing this test for coreboot. - */ -#if RUN_BROKEN_AGESA_TESTS - -// Ensure power down mode is valid -#if CFG_POWER_DOWN_MODE != POWER_DOWN_BY_CHIP_SELECT - #if CFG_POWER_DOWN_MODE != POWER_DOWN_BY_CHANNEL - #error BLDCFG: Invalid power down mode set - #endif -#endif - -#endif -/***************************************************************************** - * - * Process the option logic, setting local control variables - * - ****************************************************************************/ -#if OPTION_ACPI_PSTATES == TRUE - #define OPTFCN_ACPI_TABLES CreateAcpiTablesMain - #define OPTFCN_GATHER_DATA PStateGatherData - #if OPTION_MULTISOCKET == TRUE - #define OPTFCN_PSTATE_LEVELING PStateLeveling - #else - #define OPTFCN_PSTATE_LEVELING CommonReturnAgesaSuccess - #endif -#else - #define OPTFCN_ACPI_TABLES CommonReturnAgesaSuccess - #define OPTFCN_GATHER_DATA CommonReturnAgesaSuccess - #define OPTFCN_PSTATE_LEVELING CommonReturnAgesaSuccess -#endif - - -/***************************************************************************** - * - * Include the structure definitions for the defaults table structures - * - ****************************************************************************/ -#include -#include -#include "Options.h" -#include "OptionCpuFamiliesInstall.h" -#include "OptionsHt.h" -#include "OptionHtInstall.h" -#include "OptionMemory.h" -#include "OptionMemoryInstall.h" -#include "OptionCpuFeaturesInstall.h" -#include "OptionDmi.h" -#include "OptionDmiInstall.h" -#include "OptionPstate.h" -#include "OptionPstateInstall.h" -#include "OptionWhea.h" -#include "OptionWheaInstall.h" -#include "OptionSrat.h" -#include "OptionSratInstall.h" -#include "OptionSlit.h" -#include "OptionSlitInstall.h" -#include "OptionMultiSocket.h" -#include "OptionMultiSocketInstall.h" -#include "OptionIdsInstall.h" -#include "OptionGfxRecovery.h" -#include "OptionGfxRecoveryInstall.h" -#include "OptionGnb.h" -#include "OptionGnbInstall.h" -#include "OptionS3ScriptInstall.h" -#include "OptionFchInstall.h" - - -/***************************************************************************** - * - * Generate the output structures (defaults tables) - * - ****************************************************************************/ -BUILD_OPT_CFG UserOptions = { - { // AGESA version string - AGESA_CODE_SIGNATURE, // code header Signature - AGESA_PACKAGE_STRING, // 8 character ID - AGESA_VERSION_STRING, // 12 character version string - 0 // null string terminator - }, - //Build Option Area - OPTION_UDIMMS, //UDIMMS - OPTION_RDIMMS, //RDIMMS - OPTION_LRDIMMS, //LRDIMMS - OPTION_ECC, //ECC - OPTION_BANK_INTERLEAVE, //BANK_INTERLEAVE - OPTION_DCT_INTERLEAVE, //DCT_INTERLEAVE - OPTION_NODE_INTERLEAVE, //NODE_INTERLEAVE - OPTION_PARALLEL_TRAINING, //PARALLEL_TRAINING - OPTION_ONLINE_SPARE, //ONLINE_SPARE - OPTION_MEM_RESTORE, //MEM CONTEXT RESTORE - OPTION_MULTISOCKET, //MULTISOCKET - OPTION_ACPI_PSTATES, //ACPI_PSTATES - OPTION_SRAT, //SRAT - OPTION_SLIT, //SLIT - OPTION_WHEA, //WHEA - OPTION_DMI, //DMI - OPTION_EARLY_SAMPLES, //EARLY_SAMPLES - OPTION_ADDR_TO_CS_TRANSLATOR, //ADDR_TO_CS_TRANSLATOR - - //Build Configuration Area - CFG_PCI_MMIO_BASE, - CFG_PCI_MMIO_SIZE, - { - // CoreVrm - { - CFG_VRM_CURRENT_LIMIT, // VrmCurrentLimit - CFG_VRM_LOW_POWER_THRESHOLD, // VrmLowPowerThershold - CFG_VRM_SLEW_RATE, // VrmSlewRate - CFG_VRM_ADDITIONAL_DELAY, // VrmAdditionalDelay - CFG_VRM_HIGH_SPEED_ENABLE, // VrmHiSpeedEnable - CFG_VRM_INRUSH_CURRENT_LIMIT // VrmInrushCurrentLimit - }, - // NbVrm - { - CFG_VRM_NB_CURRENT_LIMIT, // VrmNbCurrentLimit - CFG_VRM_NB_LOW_POWER_THRESHOLD, // VrmNbLowPowerThershold - CFG_VRM_NB_SLEW_RATE, // VrmNbSlewRate - CFG_VRM_NB_ADDITIONAL_DELAY, // VrmNbAdditionalDelay - CFG_VRM_NB_HIGH_SPEED_ENABLE, // VrmNbHiSpeedEnable - CFG_VRM_NB_INRUSH_CURRENT_LIMIT // VrmNbInrushCurrentLimit - } - }, - CFG_PLAT_NUM_IO_APICS, //PlatformApicIoNumber - CFG_MEM_INIT_PSTATE, //MemoryInitPstate - CFG_C1E_MODE, //C1eMode - CFG_C1E_OPDATA, //C1ePlatformData - CFG_C1E_OPDATA1, //C1ePlatformData1 - CFG_C1E_OPDATA2, //C1ePlatformData2 - CFG_C1E_OPDATA3, //C1ePlatformData3 - CFG_CSTATE_MODE, //CStateMode - CFG_CSTATE_OPDATA, //CStatePlatformData - CFG_CSTATE_IO_BASE_ADDRESS, //CStateIoBaseAddress - CFG_CPB_MODE, //CpbMode - CFG_CORE_LEVELING_MODE, //CoreLevelingCofig - { - CFG_PLATFORM_CONTROL_FLOW_MODE, // The platform's control flow mode. - CFG_USE_HT_ASSIST, // CfgUseHtAssist - CFG_USE_ATM_MODE, // CfgUseAtmMode - CFG_USE_32_BYTE_REFRESH, // Display Refresh uses 32 byte packets. - CFG_USE_VARIABLE_MCT_ISOC_PRIORITY, // The Memory controller will be set to Variable Isoc Priority. - CFG_PLATFORM_POWER_POLICY_MODE // The platform's power policy mode. - }, - (CPU_HT_DEEMPHASIS_LEVEL *)CFG_PLATFORM_DEEMPHASIS_LIST, // Deemphasis settings - CFG_AMD_PLATFORM_TYPE, //AmdPlatformType - CFG_AMD_PSTATE_CAP_VALUE, // Amd pstate ceiling enabling deck - - CFG_MEMORY_BUS_FREQUENCY_LIMIT, // CfgMemoryBusFrequencyLimit - CFG_MEMORY_MODE_UNGANGED, // CfgMemoryModeUnganged - CFG_MEMORY_QUAD_RANK_CAPABLE, // CfgMemoryQuadRankCapable - CFG_MEMORY_QUADRANK_TYPE, // CfgMemoryQuadrankType - CFG_MEMORY_RDIMM_CAPABLE, // CfgMemoryRDimmCapable - CFG_MEMORY_LRDIMM_CAPABLE, // CfgMemoryLRDimmCapable - CFG_MEMORY_UDIMM_CAPABLE, // CfgMemoryUDimmCapable - CFG_MEMORY_SODIMM_CAPABLE, // CfgMemorySodimmCapable - CFG_LIMIT_MEMORY_TO_BELOW_1TB, // CfgLimitMemoryToBelow1Tb - CFG_MEMORY_ENABLE_BANK_INTERLEAVING, // CfgMemoryEnableBankInterleaving - CFG_MEMORY_ENABLE_NODE_INTERLEAVING, // CfgMemoryEnableNodeInterleaving - CFG_MEMORY_CHANNEL_INTERLEAVING, // CfgMemoryChannelInterleaving - CFG_MEMORY_POWER_DOWN, // CfgMemoryPowerDown - CFG_POWER_DOWN_MODE, // CfgPowerDownMode - CFG_ONLINE_SPARE, // CfgOnlineSpare - CFG_MEMORY_PARITY_ENABLE, // CfgMemoryParityEnable - CFG_BANK_SWIZZLE, // CfgBankSwizzle - CFG_TIMING_MODE_SELECT, // CfgTimingModeSelect - CFG_MEMORY_CLOCK_SELECT, // CfgMemoryClockSelect - CFG_DQS_TRAINING_CONTROL, // CfgDqsTrainingControl - CFG_IGNORE_SPD_CHECKSUM, // CfgIgnoreSpdChecksum - CFG_USE_BURST_MODE, // CfgUseBurstMode - CFG_MEMORY_ALL_CLOCKS_ON, // CfgMemoryAllClocksOn - CFG_ENABLE_ECC_FEATURE, // CfgEnableEccFeature - CFG_ECC_REDIRECTION, // CfgEccRedirection - CFG_SCRUB_DRAM_RATE, // CfgScrubDramRate - CFG_SCRUB_L2_RATE, // CfgScrubL2Rate - CFG_SCRUB_L3_RATE, // CfgScrubL3Rate - CFG_SCRUB_IC_RATE, // CfgScrubIcRate - CFG_SCRUB_DC_RATE, // CfgScrubDcRate - CFG_ECC_SYNC_FLOOD, // CfgEccSyncFlood - CFG_ECC_SYMBOL_SIZE, // CfgEccSymbolSize - CFG_HEAP_DRAM_ADDRESS, // CfgHeapDramAddress - CFG_1GB_ALIGN, // CfgNodeMem1GBAlign - CFG_S3_LATE_RESTORE, // CfgS3LateRestore - CFG_ACPI_PSTATE_PSD_INDPX, // CfgAcpiPstateIndependent - (AP_MTRR_SETTINGS *) CFG_AP_MTRR_SETTINGS_LIST, // CfgApMtrrSettingsList - CFG_UMA_MODE, // CfgUmaMode - CFG_UMA_SIZE, // CfgUmaSize - CFG_UMA_ABOVE4G, // CfgUmaAbove4G - CFG_UMA_ALIGNMENT, // CfgUmaAlignment - CFG_PROCESSOR_SCOPE_IN_SB, // CfgProcessorScopeInSb - CFG_PROCESSOR_SCOPE_NAME0, // CfgProcessorScopeName0 - CFG_PROCESSOR_SCOPE_NAME1, // CfgProcessorScopeName1 - CFG_GNB_HD_AUDIO, // CfgGnbHdAudio - CFG_ABM_SUPPORT, // CfgAbmSupport - CFG_DYNAMIC_REFRESH_RATE, // CfgDynamicRefreshRate - CFG_LCD_BACK_LIGHT_CONTROL, // CfgLcdBackLightControl - CFG_GNB_STEREO_3D_PINOUT, // CfgGnb3dStereoPinIndex - CFG_TEMP_PCIE_MMIO_BASE_ADDRESS, // CfgTempPcieMmioBaseAddress - CFG_GNB_IGPU_SSID, // CfgGnbIGPUSSID - CFG_GNB_HDAUDIO_SSID, // CfgGnbHDAudioSSID - CFG_GNB_PCIE_SSID, // CfgGnbPcieSSID - CFG_GFX_LVDS_SPREAD_SPECTRUM, // CfgLvdsSpreadSpectrum - CFG_GFX_LVDS_SPREAD_SPECTRUM_RATE, // CfgLvdsSpreadSpectrumRate - - CFG_SMBUS0_BASE_ADDRESS, // CfgSmbus0BaseAddress - CFG_SMBUS1_BASE_ADDRESS, // CfgSmbus1BaseAddress - CFG_SIO_PME_BASE_ADDRESS, // CfgSioPmeBaseAddress - CFG_ACPI_PM1_EVT_BLOCK_ADDRESS, // CfgAcpiPm1EvtBlkAddr - CFG_ACPI_PM1_CNT_BLOCK_ADDRESS, // CfgAcpiPm1CntBlkAddr - CFG_ACPI_PM_TMR_BLOCK_ADDRESS, // CfgAcpiPmTmrBlkAddr - CFG_ACPI_CPU_CNT_BLOCK_ADDRESS, // CfgCpuControlBlkAddr - CFG_ACPI_GPE0_BLOCK_ADDRESS, // CfgAcpiGpe0BlkAddr - CFG_SMI_CMD_PORT_ADDRESS, // CfgSmiCmdPortAddr - CFG_ACPI_PMA_CNTBLK_ADDRESS, // CfgAcpiPmaCntBlkAddr - CFG_GEC_SHADOW_ROM_BASE, // CfgGecShadowRomBase - CFG_WATCHDOG_TIMER_BASE, // CfgWatchDogTimerBase - CFG_SPI_ROM_BASE_ADDRESS, // CfgSpiRomBaseAddress - CFG_HPET_BASE_ADDRESS, // CfgHpetBaseAddress - CFG_AZALIA_SSID, // CfgAzaliaSsid - CFG_SMBUS_SSID, // CfgSmbusSsid - CFG_IDE_SSID, // CfgIdeSsid - CFG_SATA_AHCI_SSID, // CfgSataAhciSsid - CFG_SATA_IDE_SSID, // CfgSataIdeSsid - CFG_SATA_RAID5_SSID, // CfgSataRaid5Ssid - CFG_SATA_RAID_SSID, // CfgSataRaidSsid - CFG_EHCI_SSID, // CfgEhcidSsid - CFG_OHCI_SSID, // CfgOhcidSsid - CFG_LPC_SSID, // CfgLpcSsid - CFG_FCH_GPP_LINK_CONFIG, // CfgFchGppLinkConfig - CFG_FCH_GPP_PORT0_PRESENT, // CfgFchGppPort0Present - CFG_FCH_GPP_PORT1_PRESENT, // CfgFchGppPort1Present - CFG_FCH_GPP_PORT2_PRESENT, // CfgFchGppPort2Present - CFG_FCH_GPP_PORT3_PRESENT, // CfgFchGppPort3Present - CFG_FCH_GPP_PORT0_HOTPLUG, // CfgFchGppPort0HotPlug - CFG_FCH_GPP_PORT1_HOTPLUG, // CfgFchGppPort1HotPlug - CFG_FCH_GPP_PORT2_HOTPLUG, // CfgFchGppPort2HotPlug - CFG_FCH_GPP_PORT3_HOTPLUG, // CfgFchGppPort3HotPlug - - - CFG_IOMMU_SUPPORT, // CfgIommuSupport - CFG_LVDS_POWER_ON_SEQ_DIGON_TO_DE, // CfgLvdsPowerOnSeqDigonToDe - CFG_LVDS_POWER_ON_SEQ_DE_TO_VARY_BL, // CfgLvdsPowerOnSeqDeToVaryBl - CFG_LVDS_POWER_ON_SEQ_DE_TO_DIGON, // CfgLvdsPowerOnSeqDeToDigon - CFG_LVDS_POWERS_ON_SEQ_VARY_BL_TO_DE, // CfgLvdsPowerOnSeqVaryBlToDe - CFG_LVDS_POWER_ON_SEQ_ON_TO_OFF_DELAY,// CfgLvdsPowerOnSeqOnToOffDelay - CFG_LVDS_POWER_ON_SEQ_VARY_BL_TO_BLON,// CfgLvdsPowerOnSeqVaryBlToBlon - CFG_LVDS_POWER_ON_SEQ_BLON_TO_VARY_BL,// CfgLvdsPowerOnSeqBlonToVaryBl - CFG_LVDS_MAX_PIXEL_CLOCK_FREQ, // CfgLvdsMaxPixelClockFreq - CFG_LCD_BIT_DEPTH_CONTROL_VALUE, // CfgLcdBitDepthControlValue - CFG_LVDS_24BBP_PANEL_MODE, // CfgLvds24bbpPanelMode - CFG_PCIE_REFCLK_SPREAD_SPECTRUM, // CfgPcieRefClkSpreadSpectrum - 0, //reserved... -}; - -CONST DISPATCH_TABLE ROMDATA ApDispatchTable[] = -{ - IDS_LATE_RUN_AP_TASK - // Get DMI info - CPU_DMI_AP_GET_TYPE4_TYPE7 - // Probe filter enable - L3_FEAT_AP_DISABLE_CACHE - L3_FEAT_AP_ENABLE_CACHE - - { 0, NULL } -}; - -#if AGESA_ENTRY_INIT_EARLY == TRUE - #if IDSOPT_IDS_ENABLED == TRUE - #if IDSOPT_TRACING_ENABLED == TRUE - #define MAKE_DBG_STR(x, y) MAKE_AS_A_STRING(x : y) - CONST CHAR8 *BldOptDebugOutput[] = { - #if IDS_TRACE_SHOW_BLD_OPT_CFG == TRUE - //Build Option Area - MAKE_DBG_STR (\nOptUDIMM, OPTION_UDIMMS) - MAKE_DBG_STR (\nOptRDIMM, OPTION_RDIMMS) - MAKE_DBG_STR (\nOptLRDIMM, OPTION_LRDIMMS) - MAKE_DBG_STR (\nOptECC, OPTION_ECC) - MAKE_DBG_STR (\nOptCsIntlv, OPTION_BANK_INTERLEAVE) - MAKE_DBG_STR (\nOptDctIntlv, OPTION_DCT_INTERLEAVE) - MAKE_DBG_STR (\nOptNodeIntlv, OPTION_NODE_INTERLEAVE) - //MAKE_DBG_STR (\nOptParallelTraining, OPTION_PARALLEL_TRAINING) - MAKE_DBG_STR (\nOptOnlineSpare, OPTION_ONLINE_SPARE) - MAKE_DBG_STR (\nOptAddr2CsTranslator, OPTION_ADDR_TO_CS_TRANSLATOR) - MAKE_DBG_STR (\nOptMemRestore, OPTION_MEM_RESTORE) - MAKE_DBG_STR (\nOptMultiSocket, OPTION_MULTISOCKET) - MAKE_DBG_STR (\nOptPstates, OPTION_ACPI_PSTATES) - MAKE_DBG_STR (\nOptSRAT, OPTION_SRAT) - MAKE_DBG_STR (\nOptSLIT, OPTION_SLIT) - MAKE_DBG_STR (\nOptWHEA, OPTION_WHEA) - MAKE_DBG_STR (\nOptDMI, OPTION_DMI) - MAKE_DBG_STR (\nOptEarlySamples, OPTION_EARLY_SAMPLES), - - //Build Configuration Area - // CoreVrm - MAKE_DBG_STR (\nVrmCurrentLimit , CFG_VRM_CURRENT_LIMIT) - MAKE_DBG_STR (\nVrmLowPowerThreshold , CFG_VRM_LOW_POWER_THRESHOLD) - MAKE_DBG_STR (\nVrmSlewRate , CFG_VRM_SLEW_RATE) - MAKE_DBG_STR (\nVrmAdditionalDelay , CFG_VRM_ADDITIONAL_DELAY) - MAKE_DBG_STR (\nVrmHiSpeedEnable , CFG_VRM_HIGH_SPEED_ENABLE) - MAKE_DBG_STR (\nVrmInrushCurrentLimit, CFG_VRM_INRUSH_CURRENT_LIMIT) - // NbVrm - MAKE_DBG_STR (\nNbVrmCurrentLimit , CFG_VRM_NB_CURRENT_LIMIT) - MAKE_DBG_STR (\nNbVrmLowPowerThreshold , CFG_VRM_NB_LOW_POWER_THRESHOLD) - MAKE_DBG_STR (\nNbVrmSlewRate , CFG_VRM_NB_SLEW_RATE) - MAKE_DBG_STR (\nNbVrmAdditionalDelay , CFG_VRM_NB_ADDITIONAL_DELAY) - MAKE_DBG_STR (\nNbVrmHiSpeedEnable , CFG_VRM_NB_HIGH_SPEED_ENABLE) - MAKE_DBG_STR (\nNbVrmInrushCurrentLimit, CFG_VRM_NB_INRUSH_CURRENT_LIMIT), - - MAKE_DBG_STR (\nNumIoApics , CFG_PLAT_NUM_IO_APICS) - MAKE_DBG_STR (\nMemInitPstate , CFG_MEM_INIT_PSTATE) - MAKE_DBG_STR (\nC1eMode , CFG_C1E_MODE) - MAKE_DBG_STR (\nC1eOpData , CFG_C1E_OPDATA) - MAKE_DBG_STR (\nC1eOpdata1 , CFG_C1E_OPDATA1) - MAKE_DBG_STR (\nC1eOpdata2 , CFG_C1E_OPDATA2) - MAKE_DBG_STR (\nC1eOpdata3 , CFG_C1E_OPDATA3) - MAKE_DBG_STR (\nCStateMode , CFG_CSTATE_MODE) - MAKE_DBG_STR (\nCStateOpData , CFG_CSTATE_OPDATA) - MAKE_DBG_STR (\nCStateIoBaseAddr , CFG_CSTATE_IO_BASE_ADDRESS) - MAKE_DBG_STR (\nCpbMode , CFG_CPB_MODE) - MAKE_DBG_STR (\nCoreLevelingMode , CFG_CORE_LEVELING_MODE), - - MAKE_DBG_STR (\nControlFlowMode , CFG_PLATFORM_CONTROL_FLOW_MODE) - MAKE_DBG_STR (\nUseHtAssist , CFG_USE_HT_ASSIST) - MAKE_DBG_STR (\nUseAtmMode , CFG_USE_ATM_MODE) - MAKE_DBG_STR (\nUse32ByteRefresh , CFG_USE_32_BYTE_REFRESH) - MAKE_DBG_STR (\nUseVarMctIsocPriority , CFG_USE_VARIABLE_MCT_ISOC_PRIORITY) - MAKE_DBG_STR (\nPowerPolicy , CFG_PLATFORM_POWER_POLICY_MOD) - - MAKE_DBG_STR (\nDeemphasisList , CFG_PLATFORM_DEEMPHASIS_LIST) - - MAKE_DBG_STR (\nPciMmioAddr , CFG_PCI_MMIO_BASE) - MAKE_DBG_STR (\nPciMmioSize , CFG_PCI_MMIO_SIZE) - MAKE_DBG_STR (\nPlatformType , CFG_AMD_PLATFORM_TYPE) - MAKE_DBG_STR (\nPstateCapValue , CFG_AMD_PSTATE_CAP_VALUE), - - MAKE_DBG_STR (\nMemBusFreqLimit , CFG_MEMORY_BUS_FREQUENCY_LIMIT) - MAKE_DBG_STR (\nTimingModeSelect , CFG_TIMING_MODE_SELECT) - MAKE_DBG_STR (\nMemoryClockSelect , CFG_MEMORY_CLOCK_SELECT) - - MAKE_DBG_STR (\nMemUnganged , CFG_MEMORY_MODE_UNGANGED) - MAKE_DBG_STR (\nQRCap , CFG_MEMORY_QUAD_RANK_CAPABLE) - MAKE_DBG_STR (\nQRType , CFG_MEMORY_QUADRANK_TYPE) - MAKE_DBG_STR (\nRDimmCap , CFG_MEMORY_RDIMM_CAPABLE) - MAKE_DBG_STR (\nLRDimmCap , CFG_MEMORY_LRDIMM_CAPABLE) - MAKE_DBG_STR (\nUDimmCap , CFG_MEMORY_UDIMM_CAPABLE) - MAKE_DBG_STR (\nSODimmCap , CFG_MEMORY_SODIMM_CAPABLE) - MAKE_DBG_STR (\nDqsTrainingControl , CFG_DQS_TRAINING_CONTROL) - MAKE_DBG_STR (\nIgnoreSpdChecksum , CFG_IGNORE_SPD_CHECKSUM) - MAKE_DBG_STR (\nUseBurstMode , CFG_USE_BURST_MODE) - MAKE_DBG_STR (\nAllMemClkOn , CFG_MEMORY_ALL_CLOCKS_ON), - - MAKE_DBG_STR (\nPowerDownEn , CFG_MEMORY_POWER_DOWN) - MAKE_DBG_STR (\nPowerDownMode , CFG_POWER_DOWN_MODE) - MAKE_DBG_STR (\nOnlineSpare , CFG_ONLINE_SPARE) - MAKE_DBG_STR (\nAddrParityEn , CFG_MEMORY_PARITY_ENABLE) - MAKE_DBG_STR (\nBankSwizzle , CFG_BANK_SWIZZLE) - MAKE_DBG_STR (\nLimitBelow1TB , CFG_LIMIT_MEMORY_TO_BELOW_1TB) - MAKE_DBG_STR (\nCsIntlvEn , CFG_MEMORY_ENABLE_BANK_INTERLEAVING) - MAKE_DBG_STR (\nNodeIntlvEn , CFG_MEMORY_ENABLE_NODE_INTERLEAVING) - MAKE_DBG_STR (\nDctIntlvEn , CFG_MEMORY_CHANNEL_INTERLEAVING), - - MAKE_DBG_STR (\nUmaMode , CFG_UMA_MODE) - MAKE_DBG_STR (\nUmaSize , CFG_UMA_SIZE) - MAKE_DBG_STR (\nUmaAbove4G , CFG_UMA_ABOVE4G) - MAKE_DBG_STR (\nUmaAlignment , CFG_UMA_ALIGNMENT) - - MAKE_DBG_STR (\nEccEn , CFG_ENABLE_ECC_FEATURE) - MAKE_DBG_STR (\nEccRedirect , CFG_ECC_REDIRECTION) - MAKE_DBG_STR (\nScrubDramRate , CFG_SCRUB_DRAM_RATE) - MAKE_DBG_STR (\nScrubL2Rate , CFG_SCRUB_L2_RATE) - MAKE_DBG_STR (\nScrubL3Rate , CFG_SCRUB_L3_RATE) - MAKE_DBG_STR (\nScrubIcRate , CFG_SCRUB_IC_RATE) - MAKE_DBG_STR (\nScrubDcRate , CFG_SCRUB_DC_RATE) - MAKE_DBG_STR (\nEccSyncFlood , CFG_ECC_SYNC_FLOOD) - MAKE_DBG_STR (\nEccSymbolSize , CFG_ECC_SYMBOL_SIZE) - MAKE_DBG_STR (\nHeapDramAddress , CFG_HEAP_DRAM_ADDRESS) - MAKE_DBG_STR (\nNodeMem1GBAlign , CFG_1GB_ALIGN), - - MAKE_DBG_STR (\nS3LateRestore , CFG_S3_LATE_RESTORE) - MAKE_DBG_STR (\nAcpiPstateIndependent , CFG_ACPI_PSTATE_PSD_INDPX) - - MAKE_DBG_STR (\nApMtrrSettingsList , CFG_AP_MTRR_SETTINGS_LIST) - - MAKE_DBG_STR (\nProcessorScopeInSb , CFG_PROCESSOR_SCOPE_IN_SB) - MAKE_DBG_STR (\nProcessorScopeName0 , CFG_PROCESSOR_SCOPE_NAME0) - MAKE_DBG_STR (\nProcessorScopeName1 , CFG_PROCESSOR_SCOPE_NAME1) - MAKE_DBG_STR (\nGnbHdAudio , CFG_GNB_HD_AUDIO) - MAKE_DBG_STR (\nAbmSupport , CFG_ABM_SUPPORT) - MAKE_DBG_STR (\nDynamicRefreshRate , CFG_DYNAMIC_REFRESH_RATE) - MAKE_DBG_STR (\nLcdBackLightControl , CFG_LCD_BACK_LIGHT_CONTROL) - MAKE_DBG_STR (\nGnb3dStereoPinIndex , CFG_GNB_STEREO_3D_PINOUT) - MAKE_DBG_STR (\nTempPcieMmioBaseAddress, CFG_TEMP_PCIE_MMIO_BASE_ADDRESS), - MAKE_DBG_STR (\nCfgGnbIGPUSSID , CFG_GNB_IGPU_SSID) - MAKE_DBG_STR (\nCfgGnbHDAudioSSID , CFG_GNB_HDAUDIO_SSID) - MAKE_DBG_STR (\nCfgGnbPcieSSID , CFG_GNB_PCIE_SSID) - MAKE_DBG_STR (\nCfgIommuSupport , CFG_IOMMU_SUPPORT) - MAKE_DBG_STR (\nCfgLvdsSpreadSpectrum , CFG_GFX_LVDS_SPREAD_SPECTRUM) - MAKE_DBG_STR (\nCfgLvdsSpreadSpectrumRate , CFG_GFX_LVDS_SPREAD_SPECTRUM_RATE) - MAKE_DBG_STR (\nCfgLvdsPowerOnSeqDigonToDe , CFG_LVDS_POWER_ON_SEQ_DIGON_TO_DE) - MAKE_DBG_STR (\nCfgLvdsPowerOnSeqDeToVaryBl , CFG_LVDS_POWER_ON_SEQ_DE_TO_VARY_BL) - MAKE_DBG_STR (\nCfgLvdsPowerOnSeqDeToDigon , CFG_LVDS_POWER_ON_SEQ_DE_TO_DIGON) - MAKE_DBG_STR (\nCfgLvdsPowerOnSeqVaryBlToDe , CFG_LVDS_POWERS_ON_SEQ_VARY_BL_TO_DE) - MAKE_DBG_STR (\nCfgLvdsPowerOnSeqOnToOffDelay , CFG_LVDS_POWER_ON_SEQ_ON_TO_OFF_DELAY) - MAKE_DBG_STR (\nCfgLvdsPowerOnSeqVaryBlToBlon , CFG_LVDS_POWER_ON_SEQ_VARY_BL_TO_BLON) - MAKE_DBG_STR (\nCfgLvdsPowerOnSeqBlonToVaryBl , CFG_LVDS_POWER_ON_SEQ_BLON_TO_VARY_BL) - MAKE_DBG_STR (\nCfgLvdsMaxPixelClockFreq , CFG_LVDS_MAX_PIXEL_CLOCK_FREQ) - MAKE_DBG_STR (\nCfgLcdBitDepthControlValue , CFG_LCD_BIT_DEPTH_CONTROL_VALUE) - MAKE_DBG_STR (\nCfgLvds24bbpPanelMode , CFG_LVDS_24BBP_PANEL_MODE), - MAKE_DBG_STR (\nCfgPcieRefClkSpreadSpectrum , CFG_PCIE_REFCLK_SPREAD_SPECTRUM), - #endif - NULL - }; - #endif - #endif -#endif diff --git a/src/vendorcode/amd/agesa/f12/Dispatcher.h b/src/vendorcode/amd/agesa/f12/Dispatcher.h deleted file mode 100644 index baa69cde26..0000000000 --- a/src/vendorcode/amd/agesa/f12/Dispatcher.h +++ /dev/null @@ -1,51 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * AMD Pushhigh Interface - * - * Contains interface to Pushhigh entry - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: Legacy - * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $ - * - */ -/***************************************************************************** - * - * Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * *************************************************************************** - */ - -#ifndef _DISPATCHER_H_ -#define _DISPATCHER_H_ - -// AGESA function prototypes -AGESA_STATUS CALLCONV AmdAgesaDispatcher ( IN OUT VOID *ConfigPtr ); -AGESA_STATUS CALLCONV AmdAgesaCallout ( IN UINT32 Func, IN UINTN Data, IN OUT VOID *ConfigPtr ); - -#endif // _DISPATCHER_H_ diff --git a/src/vendorcode/amd/agesa/f12/Include/AdvancedApi.h b/src/vendorcode/amd/agesa/f12/Include/AdvancedApi.h deleted file mode 100644 index 53b57d8bbd..0000000000 --- a/src/vendorcode/amd/agesa/f12/Include/AdvancedApi.h +++ /dev/null @@ -1,166 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * Advanced API Interface for HT, Memory and CPU - * - * Contains additional declarations need to use HT, Memory and CPU Advanced interface, such as - * would be required by the basic interface implementations. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: Include - * @e \$Revision: 63425 $ @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ - */ -/***************************************************************************** - * - * Copyright (c) 2008 - 2012, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ***************************************************************************/ - - -#ifndef _ADVANCED_API_H_ -#define _ADVANCED_API_H_ - -/*---------------------------------------------------------------------------- - * HT FUNCTIONS PROTOTYPE - * - *---------------------------------------------------------------------------- - */ - -/** - * A constructor for the HyperTransport input structure. - * - * Sets inputs to valid, basic level, defaults. - * - * @param[in] StdHeader Opaque handle to standard config header - * @param[in] AmdHtInterface HT Interface structure to initialize. - * - * @retval AGESA_SUCCESS Constructors are not allowed to fail -*/ -AGESA_STATUS -AmdHtInterfaceConstructor ( - IN AMD_CONFIG_PARAMS *StdHeader, - IN AMD_HT_INTERFACE *AmdHtInterface - ); - -/** - * The top level external interface for Hypertransport Initialization. - * - * Create our initial internal state, initialize the coherent fabric, - * initialize the non-coherent chains, and perform any required fabric tuning or - * optimization. - * - * @param[in] StdHeader Opaque handle to standard config header - * @param[in] PlatformConfiguration The platform configuration options. - * @param[in] AmdHtInterface HT Interface structure. - * - * @retval AGESA_SUCCESS Only information events logged. - * @retval AGESA_ALERT Sync Flood or CRC error logged. - * @retval AGESA_WARNING Example: expected capability not found - * @retval AGESA_ERROR logged events indicating some devices may not be available - * @retval AGESA_FATAL Mixed Family or MP capability mismatch - * - */ -AGESA_STATUS -AmdHtInitialize ( - IN AMD_CONFIG_PARAMS *StdHeader, - IN PLATFORM_CONFIGURATION *PlatformConfiguration, - IN AMD_HT_INTERFACE *AmdHtInterface - ); - -/*---------------------------------------------------------------------------- - * HT Recovery FUNCTIONS PROTOTYPE - * - *---------------------------------------------------------------------------- - */ - -/** - * A constructor for the HyperTransport input structure. - * - */ -AGESA_STATUS -AmdHtResetConstructor ( - IN AMD_CONFIG_PARAMS *StdHeader, - IN AMD_HT_RESET_INTERFACE *AmdHtResetInterface - ); - -/** - * Initialize HT at Reset for both Normal and Recovery. - * - */ -AGESA_STATUS -AmdHtInitReset ( - IN AMD_CONFIG_PARAMS *StdHeader, - IN AMD_HT_RESET_INTERFACE *AmdHtResetInterface - ); - -/** - * Initialize the Node and Socket maps for an AP Core. - * - */ -AGESA_STATUS -AmdHtInitRecovery ( - IN AMD_CONFIG_PARAMS *StdHeader - ); - -///---------------------------------------------------------------------------- -/// MEMORY FUNCTIONS PROTOTYPE -/// -///---------------------------------------------------------------------------- - -AGESA_STATUS -AmdMemRecovery ( - IN OUT MEM_DATA_STRUCT *MemPtr - ); - -AGESA_STATUS -AmdMemAuto ( - IN OUT MEM_DATA_STRUCT *MemPtr - ); - -VOID -AmdMemInitDataStructDef ( - IN OUT MEM_DATA_STRUCT *MemPtr, - IN OUT PLATFORM_CONFIGURATION *PlatFormConfig - ); - -VOID -memDefRet ( VOID ); - -BOOLEAN -memDefTrue ( VOID ); - -BOOLEAN -memDefFalse ( VOID ); - -VOID -MemRecDefRet ( VOID ); - -BOOLEAN -MemRecDefTrue ( VOID ); - -#endif // _ADVANCED_API_H_ diff --git a/src/vendorcode/amd/agesa/f12/Include/CommonReturns.h b/src/vendorcode/amd/agesa/f12/Include/CommonReturns.h deleted file mode 100644 index 1bf9f85779..0000000000 --- a/src/vendorcode/amd/agesa/f12/Include/CommonReturns.h +++ /dev/null @@ -1,124 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * Common Return routines. - * - * Routines which do nothing, returning a result (preferably some version of zero) which - * is consistent with "do nothing" or "default". Useful for function pointer tables. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: Common - * @e \$Revision: 63425 $ @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ - * - */ -/* -***************************************************************************** -* - * Copyright (c) 2008 - 2012, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* *************************************************************************** -* -*/ - -#ifndef _COMMON_RETURNS_H_ -#define _COMMON_RETURNS_H_ - - -/** -* Return True -* -* @retval True Default case, no special action -*/ -BOOLEAN -CommonReturnTrue ( VOID ); - -/** -* Return False. -* -* @retval FALSE Default case, no special action -*/ -BOOLEAN -CommonReturnFalse ( VOID ); - -/** - * Return (UINT8)zero. - * - * - * @retval zero None, or only case zero. - */ -UINT8 -CommonReturnZero8 ( VOID ); - -/** - * Return (UINT32)zero. - * - * - * @retval zero None, or only case zero. - */ -UINT32 -CommonReturnZero32 ( VOID ); - -/** - * Return (UINT64)zero. - * - * - * @retval zero None, or only case zero. - */ -UINT64 -CommonReturnZero64 ( VOID ); - -/** - * Return NULL - * - * @retval NULL pointer to nothing - */ -VOID * -CommonReturnNULL ( VOID ); - -/** -* Return AGESA_SUCCESS. -* -* @retval AGESA_SUCCESS Success. -*/ -AGESA_STATUS -CommonReturnAgesaSuccess ( VOID ); - -/** - * Do Nothing. - * - */ -VOID -CommonVoid ( VOID ); - -/** - * ASSERT if this routine is called. - * - */ -VOID -CommonAssert ( VOID ); - -#endif // _COMMON_RETURNS_H_ diff --git a/src/vendorcode/amd/agesa/f12/Include/Filecode.h b/src/vendorcode/amd/agesa/f12/Include/Filecode.h deleted file mode 100644 index e811ace90e..0000000000 --- a/src/vendorcode/amd/agesa/f12/Include/Filecode.h +++ /dev/null @@ -1,1076 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * Collectively assign unique filecodes for assert and debug to each source file. - * - * Publish values for decorated filenames, which can be used for - * ASSERT and debug support using a preprocessor define like: - * @n \#define FILECODE MY_C_FILENAME_FILECODE @n - * This file serves as a reference for debugging to associate the code and filename. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: Include - * @e \$Revision: 50060 $ @e \$Date: 2011-04-01 14:56:44 +0800 (Fri, 01 Apr 2011) $ - */ -/***************************************************************************** - * - * Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ***************************************************************************/ - -#ifndef _FILECODE_H_ -#define _FILECODE_H_ - -#define UNASSIGNED_FILE_FILECODE (0xFFFF) - -/// For debug use in any Platform's options C file. -/// Can be reused for platforms and image builds, since only one options file can be built. -#define PLATFORM_SPECIFIC_OPTIONS_FILECODE (0xBBBB) - - -#define PROC_GNB_COMMON_GNBLIBFEATURES_FILECODE (0xA001) -#define PROC_GNB_GFX_FAMILY_LN_F12GFXSERVICES_FILECODE (0xA002) -#define PROC_GNB_GFX_FAMILY_ON_F14GFXSERVICES_FILECODE (0xA003) -#define PROC_GNB_GFX_GFXCONFIGDATA_FILECODE (0xA004) -#define PROC_GNB_GFX_GFXGMCINIT_FILECODE (0xA006) -#define PROC_GNB_GFX_GFXINITATENVPOST_FILECODE (0xA010) -#define PROC_GNB_GFX_GFXINITATMIDPOST_FILECODE (0xA011) -#define PROC_GNB_GFX_GFXINITATPOST_FILECODE (0xA012) -#define PROC_GNB_GFX_GFXINTEGRATEDINFOTABLEINIT_FILECODE (0xA013) -#define PROC_GNB_GFX_GFXLIB_FILECODE (0xA014) -#define PROC_GNB_GFX_GFXREGISTERACC_FILECODE (0xA015) -#define PROC_GNB_GFX_GFXSTRAPSINIT_FILECODE (0xA016) -#define PROC_GNB_GNBINITATEARLY_FILECODE (0xA017) -#define PROC_GNB_GNBINITATENV_FILECODE (0xA020) -#define PROC_GNB_GNBINITATLATE_FILECODE (0xA021) -#define PROC_GNB_GNBINITATMID_FILECODE (0xA022) -#define PROC_GNB_GNBINITATPOST_FILECODE (0xA023) -#define PROC_GNB_GNBINITATRESET_FILECODE (0xA024) -#define PROC_GNB_MODULES_GNBCOMMONLIB_GNBLIB_FILECODE (0xA025) -#define PROC_GNB_MODULES_GNBCOMMONLIB_GNBLIBCPUACC_FILECODE (0xA026) -#define PROC_GNB_MODULES_GNBCOMMONLIB_GNBLIBHEAP_FILECODE (0xA027) -#define PROC_GNB_MODULES_GNBCOMMONLIB_GNBLIBIOACC_FILECODE (0xA028) -#define PROC_GNB_MODULES_GNBCOMMONLIB_GNBLIBMEMACC_FILECODE (0xA029) -#define PROC_GNB_MODULES_GNBCOMMONLIB_GNBLIBPCI_FILECODE (0xA02A) -#define PROC_GNB_MODULES_GNBCOMMONLIB_GNBLIBPCIACC_FILECODE (0xA030) -#define PROC_GNB_MODULES_GNBGFXINITLIBV1_GFXCARDINFO_FILECODE (0xA031) -#define PROC_GNB_MODULES_GNBGFXINITLIBV1_GFXENUMCONNECTORS_FILECODE (0xA032) -#define PROC_GNB_MODULES_GNBGFXINITLIBV1_GFXPOWERPLAYTABLE_FILECODE (0xA033) -#define PROC_GNB_MODULES_GNBNBINITLIBV1_GNBNBINITLIBV1_FILECODE (0xA034) -#define PROC_GNB_MODULES_GNBPCIEALIBV1_PCIEALIB_FILECODE (0xA035) -#define PROC_GNB_MODULES_GNBPCIECONFIG_PCIECONFIGDATA_FILECODE (0xA036) -#define PROC_GNB_MODULES_GNBPCIECONFIG_PCIECONFIGLIB_FILECODE (0xA037) -#define PROC_GNB_MODULES_GNBPCIECONFIG_PCIEINPUTPARSER_FILECODE (0xA038) -#define PROC_GNB_MODULES_GNBPCIECONFIG_PCIEMAPTOPOLOGY_FILECODE (0xA039) -#define PROC_GNB_MODULES_GNBPCIEINITLIBV1_PCIEASPM_FILECODE (0xA03A) -#define PROC_GNB_MODULES_GNBPCIEINITLIBV1_PCIEASPMBLACKLIST_FILECODE (0xA03B) -#define PROC_GNB_MODULES_GNBPCIEINITLIBV1_PCIEASPMEXITLATENCY_FILECODE (0xA03C) -#define PROC_GNB_MODULES_GNBPCIEINITLIBV1_PCIEPHYSERVICES_FILECODE (0xA03D) -#define PROC_GNB_MODULES_GNBPCIEINITLIBV1_PCIEPIFSERVICES_FILECODE (0xA03E) -#define PROC_GNB_MODULES_GNBPCIEINITLIBV1_PCIEPORTREGACC_FILECODE (0xA03F) -#define PROC_GNB_MODULES_GNBPCIEINITLIBV1_PCIEPORTSERVICES_FILECODE (0xA041) -#define PROC_GNB_MODULES_GNBPCIEINITLIBV1_PCIEPOWERMGMT_FILECODE (0xA043) -#define PROC_GNB_MODULES_GNBPCIEINITLIBV1_PCIESILICONSERVICES_FILECODE (0xA045) -#define PROC_GNB_MODULES_GNBPCIEINITLIBV1_PCIETIMER_FILECODE (0xA046) -#define PROC_GNB_MODULES_GNBPCIEINITLIBV1_PCIETOPOLOGYSERVICES_FILECODE (0xA047) -#define PROC_GNB_MODULES_GNBPCIEINITLIBV1_PCIEUTILITYLIB_FILECODE (0xA048) -#define PROC_GNB_MODULES_GNBPCIEINITLIBV1_PCIEWRAPPERREGACC_FILECODE (0xA049) -#define PROC_GNB_MODULES_GNBPCIETRAININGV1_PCIETRAINING_FILECODE (0xA04A) -#define PROC_GNB_MODULES_GNBPCIETRAININGV1_PCIEWORKAROUNDS_FILECODE (0xA04B) -#define PROC_GNB_NB_FAMILY_LN_F12NBPOWERGATE_FILECODE (0xA04C) -#define PROC_GNB_NB_FAMILY_LN_F12NBSERVICES_FILECODE (0xA04D) -#define PROC_GNB_NB_FAMILY_LN_F12NBSMU_FILECODE (0xA04E) -#define PROC_GNB_NB_FAMILY_ON_F14NBLCLKNCLKRATIO_FILECODE (0xA04F) -#define PROC_GNB_NB_FAMILY_ON_F14NBPOWERGATE_FILECODE (0xA050) -#define PROC_GNB_NB_FAMILY_ON_F14NBSERVICES_FILECODE (0xA051) -#define PROC_GNB_NB_FAMILY_ON_F14NBSMU_FILECODE (0xA052) -#define PROC_GNB_NB_FEATURE_NBFUSETABLE_FILECODE (0xA053) -#define PROC_GNB_NB_FEATURE_NBLCLKDPM_FILECODE (0xA054) -#define PROC_GNB_NB_FAMILY_LN_F12NBLCLKDPM_FILECODE (0xA055) -#define PROC_GNB_NB_FAMILY_ON_F14NBLCLKDPM_FILECODE (0xA056) -#define PROC_GNB_NB_NBCONFIGDATA_FILECODE (0xA060) -#define PROC_GNB_NB_NBINIT_FILECODE (0xA061) -#define PROC_GNB_NB_NBINITATEARLY_FILECODE (0xA062) -#define PROC_GNB_NB_NBINITATENV_FILECODE (0xA063) -#define PROC_GNB_NB_NBINITATLATEPOST_FILECODE (0xA070) -#define PROC_GNB_NB_NBINITATPOST_FILECODE (0xA071) -#define PROC_GNB_NB_NBINITATRESET_FILECODE (0xA072) -#define PROC_GNB_NB_NBPOWERMGMT_FILECODE (0xA073) -#define PROC_GNB_NB_NBSMULIB_FILECODE (0xA074) -#define PROC_GNB_PCIE_FAMILY_LN_F12PCIEALIB_FILECODE (0xA075) -#define PROC_GNB_PCIE_FAMILY_LN_F12PCIECOMPLEXCONFIG_FILECODE (0xA076) -#define PROC_GNB_PCIE_FAMILY_LN_F12PCIECOMPLEXSERVICES_FILECODE (0xA077) -#define PROC_GNB_PCIE_FAMILY_LN_F12PCIEPHYSERVICES_FILECODE (0xA078) -#define PROC_GNB_PCIE_FAMILY_LN_F12PCIEPIFSERVICES_FILECODE (0xA079) -#define PROC_GNB_PCIE_FAMILY_LN_F12PCIEWRAPPERSERVICES_FILECODE (0xA07A) -#define PROC_GNB_PCIE_FAMILY_ON_F14PCIEALIB_FILECODE (0xA07D) -#define PROC_GNB_PCIE_FAMILY_ON_F14PCIECOMPLEXCONFIG_FILECODE (0xA07E) -#define PROC_GNB_PCIE_FAMILY_ON_F14PCIECOMPLEXSERVICES_FILECODE (0xA07F) -#define PROC_GNB_PCIE_FAMILY_ON_F14PCIEPHYSERVICES_FILECODE (0xA080) -#define PROC_GNB_PCIE_FAMILY_ON_F14PCIEPIFSERVICES_FILECODE (0xA081) -#define PROC_GNB_PCIE_FAMILY_ON_F14PCIEWRAPPERSERVICES_FILECODE (0xA082) -#define PROC_GNB_PCIE_FEATURE_PCIEPOWERGATE_FILECODE (0xA083) -#define PROC_GNB_PCIE_PCIEINIT_FILECODE (0xA084) -#define PROC_GNB_PCIE_PCIEINITATEARLYPOST_FILECODE (0xA085) -#define PROC_GNB_PCIE_PCIEINITATENV_FILECODE (0xA086) -#define PROC_GNB_PCIE_PCIEINITATLATEPOST_FILECODE (0xA087) -#define PROC_GNB_PCIE_PCIEINITATPOST_FILECODE (0xA088) -#define PROC_GNB_PCIE_PCIELATEINIT_FILECODE (0xA089) -#define PROC_GNB_PCIE_PCIEPORTINIT_FILECODE (0xA08B) -#define PROC_GNB_PCIE_PCIEPORTLATEINIT_FILECODE (0xA08C) -#define PROC_GNB_MODULES_GNBCABLESAFE_GNBCABLESAFE_FILECODE (0xA08D) -#define PROC_GNB_MODULES_GNBGFXCONFIG_GFXCONFIGENV_FILECODE (0xA08E) -#define PROC_GNB_MODULES_GNBGFXCONFIG_GFXCONFIGPOST_FILECODE (0xA08F) -#define PROC_GNB_MODULES_GNBCOMMONLIB_GNBTABLE_FILECODE (0xA090) -#define PROC_GNB_MODULES_GNBGFXINITLIBV1_GNBGFXINITLIBV1_FILECODE (0xA091) -#define PROC_GNB_MODULES_GNBINITTN_GFXENVINITTN_FILECODE (0xA092) -#define PROC_GNB_MODULES_GNBINITTN_GFXCONFIGDATATN_FILECODE (0xA093) -#define PROC_GNB_MODULES_GNBINITTN_GFXGMCINITTN_FILECODE (0xA094) -#define PROC_GNB_MODULES_GNBINITTN_GFXINTEGRATEDINFOTABLETN_FILECODE (0xA095) -#define PROC_GNB_MODULES_GNBINITTN_GFXLIBTN_FILECODE (0xA096) -#define PROC_GNB_MODULES_GNBINITTN_GFXMIDINITTN_FILECODE (0xA097) -#define PROC_GNB_MODULES_GNBINITTN_GNBPOSTINITTN_FILECODE (0xA098) -#define PROC_GNB_MODULES_GNBINITTN_GNBEARLYINITTN_FILECODE (0xA09A) -#define PROC_GNB_MODULES_GNBINITTN_GNBENVINITTN_FILECODE (0xA09B) -#define PROC_GNB_MODULES_GNBINITTN_GNBFUSETABLETN_FILECODE (0xA09C) -#define PROC_GNB_MODULES_GNBINITTN_GNBMIDINITTN_FILECODE (0xA09D) -#define PROC_GNB_MODULES_GNBINITTN_GFXPOSTINITTN_FILECODE (0xA09E) -#define PROC_GNB_MODULES_GNBINITTN_GNBREGISTERACCTN_FILECODE (0xA09F) -#define PROC_GNB_MODULES_GNBINITTN_PCIECONFIGTN_FILECODE (0xA0A0) -#define PROC_GNB_MODULES_GNBINITTN_PCIEEARLYINITTN_FILECODE (0xA0A1) -#define PROC_GNB_MODULES_GNBINITTN_PCIEENVINITTN_FILECODE (0xA0A2) -#define PROC_GNB_MODULES_GNBINITTN_PCIELIBTN_FILECODE (0xA0A3) -#define PROC_GNB_MODULES_GNBINITTN_PCIEMIDINITTN_FILECODE (0xA0A4) -#define PROC_GNB_MODULES_GNBINITTN_PCIEPOSTINITTN_FILECODE (0xA0A5) -#define PROC_GNB_MODULES_GNBPCIEINITLIBV4_PCIEWRAPPERSERVICESV4_FILECODE (0xA0A6) -#define PROC_GNB_MODULES_GNBIOMMUIVRS_GNBIOMMUIVRS_FILECODE (0xA0A7) -#define PROC_GNB_MODULES_GNBIVRSLIB_GNBIVRSLIB_FILECODE (0xA0A8) -#define PROC_GNB_MODULES_GNBNBINITLIBV4_GNBNBINITLIBV4_FILECODE (0xA0A9) -#define PROC_GNB_MODULES_GNBFAMTRANSLATION_GNBPCIETRANSLATION_FILECODE (0xA0AA) -#define PROC_GNB_MODULES_GNBINITTN_GNBIOMMUIVRSTN_FILECODE (0xA0AB) -#define PROC_GNB_GFX_FAMILY_KR_KRGFXSERVICES_FILECODE (0xA0AC) -#define PROC_GNB_NB_FAMILY_KR_KRNBSMU_FILECODE (0xA0AD) -#define PROC_GNB_NB_FAMILY_KR_KRNBPOWERGATE_FILECODE (0xA0AE) -#define PROC_GNB_NB_FAMILY_KR_KRNBSERVICES_FILECODE (0xA0AF) -#define PROC_GNB_NB_FAMILY_KR_KRNBLCLKNCLKRATIO_FILECODE (0xA0B0) -#define PROC_GNB_NB_FAMILY_KR_KRNBLCLKDPM_FILECODE (0xA0B1) -#define PROC_GNB_PCIE_FAMILY_KR_KRPCIEALIB_FILECODE (0xA0B2) -#define PROC_GNB_PCIE_FAMILY_KR_KRPCIECOMPLEXCONFIG_FILECODE (0xA0B3) -#define PROC_GNB_PCIE_FAMILY_KR_KRPCIECOMPLEXSERVICES_FILECODE (0xA0B4) -#define PROC_GNB_PCIE_FAMILY_KR_KRPCIEPHYSERVICES_FILECODE (0xA0B5) -#define PROC_GNB_PCIE_FAMILY_KR_KRPCIEWRAPPERSERVICES_FILECODE (0xA0B6) -#define PROC_GNB_PCIE_FAMILY_KR_KRPCIEPIFSERVICES_FILECODE (0xA0B7) -#define PROC_GNB_MODULES_GNBINITTN_PCIEPOWERGATETN_FILECODE (0xA0B8) -#define PROC_GNB_MODULES_GNBINITTN_PCIEALIBTN_FILECODE (0xA0B9) -#define PROC_GNB_MODULES_GNBSBLIB_GNBSBPCIE_FILECODE (0xA0BA) -#define PROC_GNB_MODULES_GNBSBLIB_GNBSBLIB_FILECODE (0xA0BB) -#define PROC_GNB_MODULES_GNBSBIOMMULIB_GNBSBIOMMULIB_FILECODE (0xA0BC) - -#define PROC_RECOVERY_GNB_GNBRECOVERY_FILECODE (0xAE01) -#define PROC_RECOVERY_GNB_NBINITRECOVERY_FILECODE (0xAE02) - -// FCH -#define PROC_FCH_AZALIA_AZALIARESET_FILECODE (0xB001) -#define PROC_FCH_AZALIA_AZALIAENV_FILECODE (0xB002) -#define PROC_FCH_AZALIA_AZALIAMID_FILECODE (0xB003) -#define PROC_FCH_AZALIA_AZALIALATE_FILECODE (0xB004) -#define PROC_FCH_COMMON_ACPILIB_FILECODE (0xB010) -#define PROC_FCH_COMMON_FCHLIB_FILECODE (0xB011) -#define PROC_FCH_COMMON_FCHCOMMON_FILECODE (0xB012) -#define PROC_FCH_COMMON_FCHCOMMONSMM_FILECODE (0xB013) -#define PROC_FCH_COMMON_MEMLIB_FILECODE (0xB014) -#define PROC_FCH_COMMON_PCILIB_FILECODE (0xB015) -#define PROC_FCH_COMMON_FCHPELIB_FILECODE (0xB016) -#define PROC_FCH_GEC_GECRESET_FILECODE (0xB020) -#define PROC_FCH_GEC_GECENV_FILECODE (0xB021) -#define PROC_FCH_GEC_GECMID_FILECODE (0xB022) -#define PROC_FCH_GEC_GECLATE_FILECODE (0xB023) -#define PROC_FCH_GEC_FAMILY_HUDSON2_HUDSON2GECSERVICE_FILECODE (0xB024) -#define PROC_FCH_GEC_FAMILY_HUDSON2_HUDSON2GECENVSERVICE_FILECODE (0xB025) -#define PROC_FCH_GEC_FAMILY_YUBA_YUBAGECSERVICE_FILECODE (0xB026) -#define PROC_FCH_GEC_FAMILY_YUBA_YUBAGECENVSERVICE_FILECODE (0xB027) -#define PROC_FCH_HWACPI_HWACPIRESET_FILECODE (0xB030) -#define PROC_FCH_HWACPI_HWACPIENV_FILECODE (0xB031) -#define PROC_FCH_HWACPI_HWACPIMID_FILECODE (0xB032) -#define PROC_FCH_HWACPI_HWACPILATE_FILECODE (0xB033) -#define PROC_FCH_HWACPI_FAMILY_HUDSON2_HUDSON2HWACPIENVSERVICE_FILECODE (0xB034) -#define PROC_FCH_HWACPI_FAMILY_HUDSON2_HUDSON2HWACPIMIDSERVICE_FILECODE (0xB035) -#define PROC_FCH_HWACPI_FAMILY_HUDSON2_HUDSON2HWACPILATESERVICE_FILECODE (0xB036) -#define PROC_FCH_HWACPI_FAMILY_HUDSON2_HUDSON2SSSERVICE_FILECODE (0xB037) -#define PROC_FCH_HWACPI_FAMILY_YUBA_YUBAHWACPIENVSERVICE_FILECODE (0xB038) -#define PROC_FCH_HWACPI_FAMILY_YUBA_YUBAHWACPIMIDSERVICE_FILECODE (0xB039) -#define PROC_FCH_HWACPI_FAMILY_YUBA_YUBAHWACPILATESERVICE_FILECODE (0xB03A) -#define PROC_FCH_HWACPI_FAMILY_YUBA_YUBASSSERVICE_FILECODE (0xB03B) -#define PROC_FCH_HWM_HWMRESET_FILECODE (0xB040) -#define PROC_FCH_HWM_HWMENV_FILECODE (0xB041) -#define PROC_FCH_HWM_HWMMID_FILECODE (0xB042) -#define PROC_FCH_HWM_HWMLATE_FILECODE (0xB043) -#define PROC_FCH_HWM_FAMILY_HUDSON2_HUDSON2HWMENVSERVICE_FILECODE (0xB044) -#define PROC_FCH_HWM_FAMILY_HUDSON2_HUDSON2HWMMIDSERVICE_FILECODE (0xB045) -#define PROC_FCH_HWM_FAMILY_HUDSON2_HUDSON2HWMLATESERVICE_FILECODE (0xB046) -#define PROC_FCH_HWM_FAMILY_YUBA_YUBAHWMENVSERVICE_FILECODE (0xB047) -#define PROC_FCH_HWM_FAMILY_YUBA_YUBAHWMMIDSERVICE_FILECODE (0xB048) -#define PROC_FCH_HWM_FAMILY_YUBA_YUBAHWMLATESERVICE_FILECODE (0xB049) -#define PROC_FCH_IDE_IDEENV_FILECODE (0xB050) -#define PROC_FCH_IDE_IDEMID_FILECODE (0xB051) -#define PROC_FCH_IDE_IDELATE_FILECODE (0xB052) -#define PROC_FCH_IMC_IMCENV_FILECODE (0xB060) -#define PROC_FCH_IMC_IMCMID_FILECODE (0xB061) -#define PROC_FCH_IMC_IMCLATE_FILECODE (0xB062) -#define PROC_FCH_IMC_IMCLIB_FILECODE (0xB063) -#define PROC_FCH_IMC_IMCRESET_FILECODE (0xB064) -#define PROC_FCH_IMC_FCHECENV_FILECODE (0xB065) -#define PROC_FCH_IMC_FCHECMID_FILECODE (0xB066) -#define PROC_FCH_IMC_FCHECLATE_FILECODE (0xB067) -#define PROC_FCH_IMC_FCHECRESET_FILECODE (0xB068) -#define PROC_FCH_IMC_FAMILY_HUDSON2_HUDSON2IMCSERVICE_FILECODE (0xB069) -#define PROC_FCH_IMC_FAMILY_YUBA_YUBAIMCSERVICE_FILECODE (0xB06A) -#define PROC_FCH_INTERFACE_INITRESETDEF_FILECODE (0xB070) -#define PROC_FCH_INTERFACE_INITENVDEF_FILECODE (0xB071) -#define PROC_FCH_INTERFACE_FCHINITRESET_FILECODE (0xB072) -#define PROC_FCH_INTERFACE_FCHINITENV_FILECODE (0xB073) -#define PROC_FCH_INTERFACE_FCHINITLATE_FILECODE (0xB074) -#define PROC_FCH_INTERFACE_FCHINITMID_FILECODE (0xB075) -#define PROC_FCH_INTERFACE_FCHINITS3_FILECODE (0xB076) -#define PROC_FCH_INTERFACE_FCHTASKLAUNCHER_FILECODE (0xB077) -#define PROC_FCH_IR_IRENV_FILECODE (0xB080) -#define PROC_FCH_IR_IRMID_FILECODE (0xB081) -#define PROC_FCH_IR_IRLATE_FILECODE (0xB082) -#define PROC_FCH_PCIB_PCIBRESET_FILECODE (0xB090) -#define PROC_FCH_PCIB_PCIBENV_FILECODE (0xB091) -#define PROC_FCH_PCIB_PCIBMID_FILECODE (0xB092) -#define PROC_FCH_PCIB_PCIBLATE_FILECODE (0xB093) -#define PROC_FCH_PCIE_ABRESET_FILECODE (0xB0A0) -#define PROC_FCH_PCIE_ABENV_FILECODE (0xB0A1) -#define PROC_FCH_PCIE_ABMID_FILECODE (0xB0A2) -#define PROC_FCH_PCIE_ABLATE_FILECODE (0xB0A3) -#define PROC_FCH_PCIE_GPPHP_FILECODE (0xB0A4) -#define PROC_FCH_PCIE_GPPLIB_FILECODE (0xB0A5) -#define PROC_FCH_PCIE_GPPRESET_FILECODE (0xB0A6) -#define PROC_FCH_PCIE_GPPENV_FILECODE (0xB0A7) -#define PROC_FCH_PCIE_GPPMID_FILECODE (0xB0A8) -#define PROC_FCH_PCIE_GPPLATE_FILECODE (0xB0A9) -#define PROC_FCH_PCIE_PCIERESET_FILECODE (0xB0AA) -#define PROC_FCH_PCIE_PCIEENV_FILECODE (0xB0AB) -#define PROC_FCH_PCIE_PCIEMID_FILECODE (0xB0AC) -#define PROC_FCH_PCIE_PCIELATE_FILECODE (0xB0AD) -#define PROC_FCH_PCIE_FAMILY_HUDSON2_HUDSON2ABRESETSERVICE_FILECODE (0xB0AE) -#define PROC_FCH_PCIE_FAMILY_HUDSON2_HUDSON2ABENVSERVICE_FILECODE (0xB0AF) -#define PROC_FCH_PCIE_FAMILY_HUDSON2_HUDSON2ABSERVICE_FILECODE (0xB0B0) -#define PROC_FCH_PCIE_FAMILY_HUDSON2_HUDSON2GPPRESETSERVICE_FILECODE (0xB0B1) -#define PROC_FCH_PCIE_FAMILY_HUDSON2_HUDSON2GPPSERVICE_FILECODE (0xB0B2) -#define PROC_FCH_PCIE_FAMILY_HUDSON2_HUDSON2PCIEENVSERVICE_FILECODE (0xB0B3) -#define PROC_FCH_PCIE_FAMILY_HUDSON2_HUDSON2PCIESERVICE_FILECODE (0xB0B4) -#define PROC_FCH_PCIE_FAMILY_YUBA_YUBAABRESETSERVICE_FILECODE (0xB0B5) -#define PROC_FCH_PCIE_FAMILY_YUBA_YUBAABENVSERVICE_FILECODE (0xB0B6) -#define PROC_FCH_PCIE_FAMILY_YUBA_YUBAABSERVICE_FILECODE (0xB0B7) -#define PROC_FCH_SATA_AHCIENV_FILECODE (0xB0C0) -#define PROC_FCH_SATA_AHCIMID_FILECODE (0xB0C1) -#define PROC_FCH_SATA_AHCILATE_FILECODE (0xB0C2) -#define PROC_FCH_SATA_AHCILIB_FILECODE (0xB0C3) -#define PROC_FCH_SATA_IDE2AHCIENV_FILECODE (0xB0C4) -#define PROC_FCH_SATA_IDE2AHCIMID_FILECODE (0xB0C5) -#define PROC_FCH_SATA_IDE2AHCILATE_FILECODE (0xB0C6) -#define PROC_FCH_SATA_IDE2AHCILIB_FILECODE (0xB0C7) -#define PROC_FCH_SATA_RAIDENV_FILECODE (0xB0C8) -#define PROC_FCH_SATA_RAIDMID_FILECODE (0xB0C9) -#define PROC_FCH_SATA_RAIDLATE_FILECODE (0xB0CA) -#define PROC_FCH_SATA_RAIDLIB_FILECODE (0xB0CB) -#define PROC_FCH_SATA_SATAENV_FILECODE (0xB0CC) -#define PROC_FCH_SATA_SATAENVLIB_FILECODE (0xB0CD) -#define PROC_FCH_SATA_SATAIDEENV_FILECODE (0xB0CE) -#define PROC_FCH_SATA_SATAIDEMID_FILECODE (0xB0CF) -#define PROC_FCH_SATA_SATAIDELATE_FILECODE (0xB0D0) -#define PROC_FCH_SATA_SATAIDELIB_FILECODE (0xB0D1) -#define PROC_FCH_SATA_SATAMID_FILECODE (0xB0D2) -#define PROC_FCH_SATA_SATALATE_FILECODE (0xB0D3) -#define PROC_FCH_SATA_SATALIB_FILECODE (0xB0D4) -#define PROC_FCH_SATA_SATARESET_FILECODE (0xB0D5) -#define PROC_FCH_SATA_FAMILY_HUDSON2_HUDSON2SATARESETSERVICE_FILECODE (0xB0D6) -#define PROC_FCH_SATA_FAMILY_HUDSON2_HUDSON2SATAENVSERVICE_FILECODE (0xB0D7) -#define PROC_FCH_SATA_FAMILY_HUDSON2_HUDSON2SATASERVICE_FILECODE (0xB0D8) -#define PROC_FCH_SATA_FAMILY_YUBA_YUBASATARESETSERVICE_FILECODE (0xB0D9) -#define PROC_FCH_SATA_FAMILY_YUBA_YUBASATAENVSERVICE_FILECODE (0xB0DA) -#define PROC_FCH_SATA_FAMILY_YUBA_YUBASATASERVICE_FILECODE (0xB0DB) -#define PROC_FCH_SD_SDENV_FILECODE (0xB0E0) -#define PROC_FCH_SD_SDMID_FILECODE (0xB0E1) -#define PROC_FCH_SD_SDLATE_FILECODE (0xB0E2) -#define PROC_FCH_SPI_LPCRESET_FILECODE (0xB0F0) -#define PROC_FCH_SPI_LPCENV_FILECODE (0xB0F1) -#define PROC_FCH_SPI_LPCMID_FILECODE (0xB0F2) -#define PROC_FCH_SPI_LPCLATE_FILECODE (0xB0F3) -#define PROC_FCH_SPI_SPIRESET_FILECODE (0xB0F4) -#define PROC_FCH_SPI_SPIENV_FILECODE (0xB0F5) -#define PROC_FCH_SPI_SPIMID_FILECODE (0xB0F6) -#define PROC_FCH_SPI_SPILATE_FILECODE (0xB0F7) -#define PROC_FCH_USB_EHCIRESET_FILECODE (0xB100) -#define PROC_FCH_USB_EHCIENV_FILECODE (0xB101) -#define PROC_FCH_USB_EHCIMID_FILECODE (0xB102) -#define PROC_FCH_USB_EHCILATE_FILECODE (0xB103) -#define PROC_FCH_USB_OHCIRESET_FILECODE (0xB104) -#define PROC_FCH_USB_OHCIENV_FILECODE (0xB105) -#define PROC_FCH_USB_OHCIMID_FILECODE (0xB106) -#define PROC_FCH_USB_OHCILATE_FILECODE (0xB107) -#define PROC_FCH_USB_USBRESET_FILECODE (0xB108) -#define PROC_FCH_USB_USBENV_FILECODE (0xB109) -#define PROC_FCH_USB_USBMID_FILECODE (0xB10A) -#define PROC_FCH_USB_USBLATE_FILECODE (0xB10B) -#define PROC_FCH_USB_XHCIRESET_FILECODE (0xB10C) -#define PROC_FCH_USB_XHCIENV_FILECODE (0xB10D) -#define PROC_FCH_USB_XHCIMID_FILECODE (0xB10E) -#define PROC_FCH_USB_XHCILATE_FILECODE (0xB10F) -#define PROC_FCH_USB_FAMILY_HUDSON2_HUDSON2EHCIENVSERVICE_FILECODE (0xB110) -#define PROC_FCH_USB_FAMILY_HUDSON2_HUDSON2EHCIMIDSERVICE_FILECODE (0xB111) -#define PROC_FCH_USB_FAMILY_HUDSON2_HUDSON2EHCILATESERVICE_FILECODE (0xB112) -#define PROC_FCH_USB_FAMILY_HUDSON2_HUDSON2OHCIENVSERVICE_FILECODE (0xB113) -#define PROC_FCH_USB_FAMILY_HUDSON2_HUDSON2OHCIMIDSERVICE_FILECODE (0xB114) -#define PROC_FCH_USB_FAMILY_HUDSON2_HUDSON2OHCILATESERVICE_FILECODE (0xB115) -#define PROC_FCH_USB_FAMILY_HUDSON2_HUDSON2XHCIRESETSERVICE_FILECODE (0xB116) -#define PROC_FCH_USB_FAMILY_HUDSON2_HUDSON2XHCIENVSERVICE_FILECODE (0xB117) -#define PROC_FCH_USB_FAMILY_HUDSON2_HUDSON2XHCIMIDSERVICE_FILECODE (0xB118) -#define PROC_FCH_USB_FAMILY_HUDSON2_HUDSON2XHCILATESERVICE_FILECODE (0xB119) -#define PROC_FCH_USB_FAMILY_YUBA_YUBAEHCIENVSERVICE_FILECODE (0xB11A) -#define PROC_FCH_USB_FAMILY_YUBA_YUBAEHCIMIDSERVICE_FILECODE (0xB11B) -#define PROC_FCH_USB_FAMILY_YUBA_YUBAEHCILATESERVICE_FILECODE (0xB11C) -#define PROC_FCH_USB_FAMILY_YUBA_YUBAOHCIENVSERVICE_FILECODE (0xB11D) -#define PROC_FCH_USB_FAMILY_YUBA_YUBAOHCIMIDSERVICE_FILECODE (0xB11E) -#define PROC_FCH_USB_FAMILY_YUBA_YUBAOHCILATESERVICE_FILECODE (0xB11F) -#define PROC_FCH_USB_FAMILY_YUBA_YUBAXHCIRESETSERVICE_FILECODE (0xB120) -#define PROC_FCH_USB_FAMILY_YUBA_YUBAXHCIENVSERVICE_FILECODE (0xB121) -#define PROC_FCH_USB_FAMILY_YUBA_YUBAXHCIMIDSERVICE_FILECODE (0xB122) -#define PROC_FCH_USB_FAMILY_YUBA_YUBAXHCILATESERVICE_FILECODE (0xB123) -#define PROC_FCH_USB_XHCIRECOVERY_FILECODE (0xB124) - -#define UEFI_DXE_FCHDXE_FCHDXE_FILECODE (0xB200) -#define UEFI_DXE_CF9RESET_CF9RESET_FILECODE (0xB220) -#define UEFI_DXE_CF9RESET_IA32_IA32CF9RESET_FILECODE (0xB221) -#define UEFI_DXE_CF9RESET_X64_X64CF9RESET_FILECODE (0xB222) -#define UEFI_DXE_LEGACYINTERRUPT_LEGACYINTERRUPT_FILECODE (0xB230) -#define UEFI_DXE_SMMCONTROL_SMMCONTROL_FILECODE (0xB240) -#define UEFI_SMM_FCHSMMLIB_FCHDXECOMMON_FILECODE (0xB250) -#define UEFI_SMM_FCHSMMLIB_FCHSMMLIB_FILECODE (0xB251) -#define UEFI_DXE_FCHDXELIB_FCHDXELIB_FILECODE (0xB252) -#define UEFI_PEI_FCHPEI_FCHPEI_FILECODE (0xB260) -#define UEFI_PEI_FCHPEI_FCHRESET_FILECODE (0xB261) -#define UEFI_PEI_FCHPEI_FCHSTALL_FILECODE (0xB262) -#define UEFI_PEI_FCHPEI_LIBAMDPEI_FILECODE (0xB263) -#define UEFI_PEI_SMBUS_SMBUS_FILECODE (0xB270) -#define UEFI_SMM_FCHSMM_FCHSMM_FILECODE (0xB280) -#define UEFI_SMM_FCHSMM_GPESMI_FILECODE (0xB282) -#define UEFI_SMM_FCHSMM_IOTRAPSMI_FILECODE (0xB283) -#define UEFI_SMM_FCHSMM_MISCSMI_FILECODE (0xB284) -#define UEFI_SMM_FCHSMM_PERIODICTIMERSMI_FILECODE (0xB285) -#define UEFI_SMM_FCHSMM_POWERBUTTONSMI_FILECODE (0xB286) -#define UEFI_SMM_FCHSMM_SWSMI_FILECODE (0xB287) -#define UEFI_SMM_FCHSMM_SXSMI_FILECODE (0xB288) -#define UEFI_DXE_SMBUS_SMBUSLIGHT_FILECODE (0xB2A0) -#define UEFI_SMM_FCHSMMDISPATCHER_FCHSMMDISPATCHER_FILECODE (0xB290) -#define UEFI_SMM_FCHSMMDISPATCHER_FCHSMMGPEDISPATCHER_FCHSMMGPEDISPATCHER_FILECODE (0xB292) -#define UEFI_SMM_FCHSMMDISPATCHER_FCHSMMIOTRAPDISPATCHER_FCHSMMIOTRAPDISPATCHER_FILECODE (0xB293) -#define UEFI_SMM_FCHSMMDISPATCHER_FCHSMMMISCDISPATCHER_FCHSMMMISCDISPATCHER_FILECODE (0xB294) -#define UEFI_SMM_FCHSMMDISPATCHER_FCHSMMPERIODICALDISPATCHER_FCHSMMPERIODICALDISPATCHER_FILECODE (0xB295) -#define UEFI_SMM_FCHSMMDISPATCHER_FCHSMMPWRBTNDISPATCHER_FCHSMMPWRBTNDISPATCHER_FILECODE (0xB296) -#define UEFI_SMM_FCHSMMDISPATCHER_FCHSMMSWDISPATCHER_FCHSMMSWDISPATCHER_FILECODE (0xB297) -#define UEFI_SMM_FCHSMMDISPATCHER_FCHSMMSXDISPATCHER_FCHSMMSXDISPATCHER_FILECODE (0xB298) -#define UEFI_SMM_FCHSMMDISPATCHER_FCHSMMUSBDISPATCHER_FCHSMMUSBDISPATCHER_FILECODE (0xB299) - -#define LIB_AMDLIB_FILECODE (0xC001) - -#define LEGACY_PROC_AGESACALLOUTS_FILECODE (0xC010) -#define LEGACY_PROC_HOBTRANSFER_FILECODE (0xC011) -#define LEGACY_PROC_DISPATCHER_FILECODE (0xC012) - -#define UEFI_DXE_AMDAGESADXEDRIVER_AMDAGESADXEDRIVER_FILECODE (0xC120) - -#define UEFI_PEI_AMDINITPOSTPEIM_AMDINITPOSTPEIM_FILECODE (0xC140) -#define UEFI_PEI_AMDPROCESSORINITPEIM_AMDPROCESSORINITPEIM_FILECODE (0xC141) -#define UEFI_PEI_AMDRESETMANAGER_AMDRESETMANAGER_FILECODE (0xC142) -#define UEFI_PROC_HOBTRANSFERUEFI_FILECODE (0xC162) - -#define PROC_COMMON_AMDINITEARLY_FILECODE (0xC020) -#define PROC_COMMON_AMDINITENV_FILECODE (0xC021) -#define PROC_COMMON_AMDINITLATE_FILECODE (0xC022) -#define PROC_COMMON_AMDINITMID_FILECODE (0xC023) -#define PROC_COMMON_AMDINITPOST_FILECODE (0xC024) -#define PROC_COMMON_AMDINITRECOVERY_FILECODE (0xC025) -#define PROC_COMMON_AMDINITRESET_FILECODE (0xC026) -#define PROC_COMMON_AMDINITRESUME_FILECODE (0xC027) -#define PROC_COMMON_AMDS3LATERESTORE_FILECODE (0xC028) -#define PROC_COMMON_AMDS3SAVE_FILECODE (0xC029) -#define PROC_COMMON_AMDLATERUNAPTASK_FILECODE (0xC02A) - -#define PROC_COMMON_COMMONRETURNS_FILECODE (0xC0C0) -#define PROC_COMMON_CREATESTRUCT_FILECODE (0xC0D0) -#define PROC_COMMON_COMMONINITS_FILECODE (0xC0F0) -#define PROC_COMMON_S3RESTORESTATE_FILECODE (0xC0F8) -#define PROC_COMMON_S3SAVESTATE_FILECODE (0xC0F9) - -#define PROC_CPU_CPUAPICUTILITIES_FILECODE (0xC401) -#define PROC_CPU_CPUBRANDID_FILECODE (0xC402) -#define PROC_CPU_TABLE_FILECODE (0xC403) -#define PROC_CPU_CPUEARLYINIT_FILECODE (0xC405) -#define PROC_CPU_CPUEVENTLOG_FILECODE (0xC406) -#define PROC_CPU_CPUFAMILYTRANSLATION_FILECODE (0xC407) -#define PROC_CPU_CPUGENERALSERVICES_FILECODE (0xC408) -#define PROC_CPU_CPUINITEARLYTABLE_FILECODE (0xC409) -#define PROC_CPU_CPULATEINIT_FILECODE (0xC40A) -#define PROC_CPU_CPUMICROCODEPATCH_FILECODE (0xC40B) -#define PROC_CPU_CPUWARMRESET_FILECODE (0xC40C) -#define PROC_CPU_HEAPMANAGER_FILECODE (0xC40D) -#define PROC_CPU_CPUBIST_FILECODE (0xC40E) - -#define PROC_CPU_CPUPOSTINIT_FILECODE (0xC420) -#define PROC_CPU_CPUPOWERMGMT_FILECODE (0xC430) -#define PROC_CPU_CPUPOWERMGMTMULTISOCKET_FILECODE (0xC431) -#define PROC_CPU_CPUPOWERMGMTSINGLESOCKET_FILECODE (0xC432) -#define PROC_CPU_S3_FILECODE (0xC460) - -// Family 10h -#define PROC_CPU_FAMILY_0X10_CPUCOMMONF10UTILITIES_FILECODE (0xC801) -#define PROC_CPU_FAMILY_0X10_CPUF10BRANDID_FILECODE (0xC802) -#define PROC_CPU_FAMILY_0X10_CPUF10CACHEDEFAULTS_FILECODE (0xC803) -#define PROC_CPU_FAMILY_0X10_CPUF10CACHEFLUSHONHALT_FILECODE (0xC804) -#define PROC_CPU_FAMILY_0X10_CPUF10DMI_FILECODE (0xC805) -#define PROC_CPU_FAMILY_0X10_CPUF10EARLYINIT_FILECODE (0xC806) -#define PROC_CPU_FAMILY_0X10_CPUF10FEATURELEVELING_FILECODE (0xC807) -#define PROC_CPU_FAMILY_0X10_CPUF10HTPHYTABLES_FILECODE (0xC808) -#define PROC_CPU_FAMILY_0X10_CPUF10MSRTABLES_FILECODE (0xC809) -#define PROC_CPU_FAMILY_0X10_CPUF10PCITABLES_FILECODE (0xC80A) -#define PROC_CPU_FAMILY_0X10_CPUF10POWERCHECK_FILECODE (0xC80B) -#define PROC_CPU_FAMILY_0X10_CPUF10POWERMGMTSYSTEMTABLES_FILECODE (0xC80C) -#define PROC_CPU_FAMILY_0X10_CPUF10POWERPLANE_FILECODE (0xC80D) -#define PROC_CPU_FAMILY_0X10_CPUF10SOFTWARETHERMAL_FILECODE (0xC80E) -#define PROC_CPU_FAMILY_0X10_CPUF10UTILITIES_FILECODE (0xC80F) -#define PROC_CPU_FAMILY_0X10_CPUF10WHEAINITDATATABLES_FILECODE (0xC810) -#define PROC_CPU_FAMILY_0X10_CPUF10PSTATE_FILECODE (0xC811) -#define PROC_CPU_FAMILY_0X10_CPUF10CPB_FILECODE (0xC812) -#define PROC_CPU_FAMILY_0X10_CPUF10WORKAROUNDSTABLE_FILECODE (0xC813) -#define PROC_CPU_FAMILY_0X10_F10PMNBCOFVIDINIT_FILECODE (0xC820) -#define PROC_CPU_FAMILY_0X10_F10SINGLELINKPCITABLES_FILECODE (0xC821) -#define PROC_CPU_FAMILY_0X10_F10MULTILINKPCITABLES_FILECODE (0xC822) -#define PROC_CPU_FAMILY_0X10_F10PMNBPSTATEINIT_FILECODE (0xC823) -#define PROC_CPU_FAMILY_0X10_F10PMASYMBOOSTINIT_FILECODE (0xC824) -#define PROC_CPU_FAMILY_0X10_F10INITEARLYTABLE_FILECODE (0xC825) -#define PROC_CPU_FAMILY_0X10_F10PMDUALPLANEONLYSUPPORT_FILECODE (0xC826) -#define PROC_CPU_FAMILY_0X10_F10IOCSTATE_FILECODE (0xC827) -#define PROC_CPU_FAMILY_0X10_REVC_F10REVCUTILITIES_FILECODE (0xC830) -#define PROC_CPU_FAMILY_0X10_REVC_F10REVCHWC1E_FILECODE (0xC831) -#define PROC_CPU_FAMILY_0X10_REVC_F10REVCSWC1E_FILECODE (0xC832) -#define PROC_CPU_FAMILY_0X10_REVC_F10REVCPCITABLES_FILECODE (0xC833) -#define PROC_CPU_FAMILY_0X10_REVC_F10REVCMSRTABLES_FILECODE (0xC834) -#define PROC_CPU_FAMILY_0X10_REVC_F10REVCHTPHYTABLES_FILECODE (0xC835) -#define PROC_CPU_FAMILY_0X10_REVC_BL_F10BLHTPHYTABLES_FILECODE (0xC836) -#define PROC_CPU_FAMILY_0X10_REVC_BL_F10BLLOGICALIDTABLES_FILECODE (0xC837) -#define PROC_CPU_FAMILY_0X10_REVC_BL_F10BLMICROCODEPATCHTABLES_FILECODE (0xC838) -#define PROC_CPU_FAMILY_0X10_REVC_BL_F10BLMSRTABLES_FILECODE (0xC839) -#define PROC_CPU_FAMILY_0X10_REVC_BL_F10BLEQUIVALENCETABLE_FILECODE (0xC83A) -#define PROC_CPU_FAMILY_0X10_REVC_BL_F10BLPCITABLES_FILECODE (0xC83B) -#define PROC_CPU_FAMILY_0X10_REVC_BL_F10BLCACHEFLUSHONHALT_FILECODE (0xC83C) -#define PROC_CPU_FAMILY_0X10_REVC_DA_F10DAHTPHYTABLES_FILECODE (0xC83D) -#define PROC_CPU_FAMILY_0X10_REVC_DA_F10DALOGICALIDTABLES_FILECODE (0xC83E) -#define PROC_CPU_FAMILY_0X10_REVC_DA_F10DAMICROCODEPATCHTABLES_FILECODE (0xC83F) -#define PROC_CPU_FAMILY_0X10_REVC_DA_F10DAMSRTABLES_FILECODE (0xC840) -#define PROC_CPU_FAMILY_0X10_REVC_DA_F10DAEQUIVALENCETABLE_FILECODE (0xC841) -#define PROC_CPU_FAMILY_0X10_REVC_DA_F10DAPCITABLES_FILECODE (0xC842) -#define PROC_CPU_FAMILY_0X10_REVC_DA_F10DACACHEFLUSHONHALT_FILECODE (0xC843) -#define PROC_CPU_FAMILY_0X10_REVC_RB_F10RBHTPHYTABLES_FILECODE (0xC844) -#define PROC_CPU_FAMILY_0X10_REVC_RB_F10RBLOGICALIDTABLES_FILECODE (0xC845) -#define PROC_CPU_FAMILY_0X10_REVC_RB_F10RBMICROCODEPATCHTABLES_FILECODE (0xC846) -#define PROC_CPU_FAMILY_0X10_REVC_RB_F10RBMSRTABLES_FILECODE (0xC847) -#define PROC_CPU_FAMILY_0X10_REVC_RB_F10RBEQUIVALENCETABLE_FILECODE (0xC848) -#define PROC_CPU_FAMILY_0X10_REVC_RB_F10RBPCITABLES_FILECODE (0xC849) -#define PROC_CPU_FAMILY_0X10_REVD_F10REVDUTILITIES_FILECODE (0xC850) -#define PROC_CPU_FAMILY_0X10_REVD_F10REVDMSGBASEDC1E_FILECODE (0xC851) -#define PROC_CPU_FAMILY_0X10_REVD_F10REVDL3FEATURES_FILECODE (0xC852) -#define PROC_CPU_FAMILY_0X10_REVD_HY_F10HYHTPHYTABLES_FILECODE (0xC853) -#define PROC_CPU_FAMILY_0X10_REVD_HY_F10HYINITEARLYTABLE_FILECODE (0xC854) -#define PROC_CPU_FAMILY_0X10_REVD_HY_F10HYLOGICALIDTABLES_FILECODE (0xC855) -#define PROC_CPU_FAMILY_0X10_REVD_HY_F10HYMICROCODEPATCHTABLES_FILECODE (0xC856) -#define PROC_CPU_FAMILY_0X10_REVD_HY_F10HYMSRTABLES_FILECODE (0xC857) -#define PROC_CPU_FAMILY_0X10_REVD_HY_F10HYEQUIVALENCETABLE_FILECODE (0xC858) -#define PROC_CPU_FAMILY_0X10_REVD_HY_F10HYPCITABLES_FILECODE (0xC859) -#define PROC_CPU_FAMILY_0X10_REVE_F10REVEUTILITIES_FILECODE (0xC860) -#define PROC_CPU_FAMILY_0X10_REVE_F10REVEMSRTABLES_FILECODE (0xC861) -#define PROC_CPU_FAMILY_0X10_REVE_F10REVEPCITABLES_FILECODE (0xC862) -#define PROC_CPU_FAMILY_0X10_REVE_F10REVEHTPHYTABLES_FILECODE (0xC863) -#define PROC_CPU_FAMILY_0X10_REVE_PH_F10PHEQUIVALENCETABLE_FILECODE (0xC864) -#define PROC_CPU_FAMILY_0X10_REVE_PH_F10PHHTPHYTABLES_FILECODE (0xC865) -#define PROC_CPU_FAMILY_0X10_REVE_PH_F10PHLOGICALIDTABLES_FILECODE (0xC866) -#define PROC_CPU_FAMILY_0X10_REVE_PH_F10PHMICROCODEPATCHTABLES_FILECODE (0xC867) - -// Family 12h -#define PROC_CPU_FAMILY_0X12_CPUCOMMONF12UTILITIES_FILECODE (0xC901) -#define PROC_CPU_FAMILY_0X12_CPUF12BRANDID_FILECODE (0xC902) -#define PROC_CPU_FAMILY_0X12_CPUF12CACHEDEFAULTS_FILECODE (0xC903) -#define PROC_CPU_FAMILY_0X12_CPUF12DMI_FILECODE (0xC904) -#define PROC_CPU_FAMILY_0X12_CPUF12MSRTABLES_FILECODE (0xC905) -#define PROC_CPU_FAMILY_0X12_CPUF12EARLYNBPSTATEINIT_FILECODE (0xC906) -#define PROC_CPU_FAMILY_0X12_CPUF12PCITABLES_FILECODE (0xC907) -#define PROC_CPU_FAMILY_0X12_CPUF12POWERCHECK_FILECODE (0xC908) -#define PROC_CPU_FAMILY_0X12_CPUF12POWERMGMTSYSTEMTABLES_FILECODE (0xC909) -#define PROC_CPU_FAMILY_0X12_CPUF12POWERPLANE_FILECODE (0xC90A) -#define PROC_CPU_FAMILY_0X12_CPUF12SOFTWARETHERMAL_FILECODE (0xC90B) -#define PROC_CPU_FAMILY_0X12_CPUF12UTILITIES_FILECODE (0xC90C) -#define PROC_CPU_FAMILY_0X12_CPUF12WHEAINITDATATABLES_FILECODE (0xC90D) -#define PROC_CPU_FAMILY_0X12_CPUF12PSTATE_FILECODE (0xC90E) -#define PROC_CPU_FAMILY_0X12_F12C6STATE_FILECODE (0xC90F) -#define PROC_CPU_FAMILY_0X12_F12CPB_FILECODE (0xC910) -#define PROC_CPU_FAMILY_0X12_F12IOCSTATE_FILECODE (0xC911) -#define PROC_CPU_FAMILY_0X12_LN_F12LNLOGICALIDTABLES_FILECODE (0xC921) -#define PROC_CPU_FAMILY_0X12_LN_F12LNMICROCODEPATCHTABLES_FILECODE (0xC922) -#define PROC_CPU_FAMILY_0X12_LN_F12LNEQUIVALENCETABLE_FILECODE (0xC923) -#define PROC_CPU_FAMILY_0X12_CPUF12PERCOREPCITABLES_FILECODE (0xC924) -#define PROC_CPU_FAMILY_0X12_LN_F12LNEARLYSAMPLES_FILECODE (0xC925) - -// Family 14h -#define PROC_CPU_FAMILY_0X14_CPUCOMMONF14UTILITIES_FILECODE (0xCA01) -#define PROC_CPU_FAMILY_0X14_CPUF14BRANDID_FILECODE (0xCA02) -#define PROC_CPU_FAMILY_0X14_CPUF14CACHEDEFAULTS_FILECODE (0xCA03) -#define PROC_CPU_FAMILY_0X14_CPUF14DMI_FILECODE (0xCA04) -#define PROC_CPU_FAMILY_0X14_CPUF14MSRTABLES_FILECODE (0xCA05) -#define PROC_CPU_FAMILY_0X14_CPUF14PCITABLES_FILECODE (0xCA06) -#define PROC_CPU_FAMILY_0X14_CPUF14UTILITIES_FILECODE (0xCA07) -#define PROC_CPU_FAMILY_0X14_CPUF14WHEAINITDATATABLES_FILECODE (0xCA08) -#define PROC_CPU_FAMILY_0X14_CPUF14PSTATE_FILECODE (0xCA09) -#define PROC_CPU_FAMILY_0X14_F14IOCSTATE_FILECODE (0xCA0A) -#define PROC_CPU_FAMILY_0X14_CPUF14PERCOREPCITABLES_FILECODE (0xCA0B) - -#define PROC_CPU_FAMILY_0X14_ON_F14ONPOWERPLANE_FILECODE (0xCA21) -#define PROC_CPU_FAMILY_0X14_ON_F14ONC6STATE_FILECODE (0xCA22) -#define PROC_CPU_FAMILY_0X14_ON_F14ONLOGICALIDTABLES_FILECODE (0xCA23) -#define PROC_CPU_FAMILY_0X14_ON_F14ONMICROCODEPATCHTABLES_FILECODE (0xCA24) -#define PROC_CPU_FAMILY_0X14_ON_F14ONEQUIVALENCETABLE_FILECODE (0xCA25) -#define PROC_CPU_FAMILY_0X14_ON_F14ONINITEARLYTABLE_FILECODE (0xCA26) -#define PROC_CPU_FAMILY_0X14_ON_F14ONEARLYSAMPLES_FILECODE (0xCA27) -#define PROC_CPU_FAMILY_0X14_ON_F14ONMSRTABLES_FILECODE (0xCA28) -#define PROC_CPU_FAMILY_0X14_ON_F14ONUTILITIES_FILECODE (0xCA29) -#define PROC_CPU_FAMILY_0X14_ON_F14ONPOWERMGMTSYSTEMTABLES_FILECODE (0xCA2A) -#define PROC_CPU_FAMILY_0X14_ON_F14ONLOWPOWERINIT_FILECODE (0xCA2B) -#define PROC_CPU_FAMILY_0X14_ON_F14ONCPB_FILECODE (0xCA2C) -#define PROC_CPU_FAMILY_0X14_ON_F14ONSOFTWARETHERMAL_FILECODE (0xCA2D) -#define PROC_CPU_FAMILY_0X14_ON_F14ONPOWERCHECK_FILECODE (0xCA2E) - -#define PROC_CPU_FAMILY_0X14_KR_F14KREQUIVALENCETABLE_FILECODE (0xCA41) -#define PROC_CPU_FAMILY_0X14_KR_F14KRINITEARLYTABLE_FILECODE (0xCA42) -#define PROC_CPU_FAMILY_0X14_KR_F14KRLOGICALIDTABLES_FILECODE (0xCA43) -#define PROC_CPU_FAMILY_0X14_KR_F14KRMICROCODEPATCHTABLES_FILECODE (0xCA44) -#define PROC_CPU_FAMILY_0X14_KR_F14KRCPB_FILECODE (0xCA45) -#define PROC_CPU_FAMILY_0X14_KR_F14KRC6STATE_FILECODE (0xCA46) -#define PROC_CPU_FAMILY_0X14_KR_F14KRUTILITIES_FILECODE (0xCA47) -#define PROC_CPU_FAMILY_0X14_KR_F14KRPOWERPLANE_FILECODE (0xCA48) -#define PROC_CPU_FAMILY_0X14_KR_F14KRPOWERMGMTSYSTEMTABLES_FILECODE (0xCA49) -#define PROC_CPU_FAMILY_0X14_KR_F14KREARLYNBPSTATEINIT_FILECODE (0xCA4A) -#define PROC_CPU_FAMILY_0X14_KR_F14KRMSRTABLES_FILECODE (0xCA4B) -#define PROC_CPU_FAMILY_0X14_KR_F14KRPCITABLES_FILECODE (0xCA4C) -#define PROC_CPU_FAMILY_0X14_KR_F14KRSOFTWARETHERMAL_FILECODE (0xCA4D) -#define PROC_CPU_FAMILY_0X14_KR_F14KRPOWERCHECK_FILECODE (0xCA4E) - -// Family 15h -#define PROC_CPU_FAMILY_0X15_CPUCOMMONF15UTILITIES_FILECODE (0xCB01) -#define PROC_CPU_FAMILY_0X15_CPUF15BRANDID_FILECODE (0xCB02) -#define PROC_CPU_FAMILY_0X15_CPUF15CACHEDEFAULTS_FILECODE (0xCB03) -#define PROC_CPU_FAMILY_0X15_CPUF15DMI_FILECODE (0xCB04) -#define PROC_CPU_FAMILY_0X15_CPUF15MSRTABLES_FILECODE (0xCB05) -#define PROC_CPU_FAMILY_0X15_CPUF15PCITABLES_FILECODE (0xCB06) -#define PROC_CPU_FAMILY_0X15_CPUF15POWERCHECK_FILECODE (0xCB07) -#define PROC_CPU_FAMILY_0X15_CPUF15UTILITIES_FILECODE (0xCB08) -#define PROC_CPU_FAMILY_0X15_CPUF15WHEAINITDATATABLES_FILECODE (0xCB09) - -#define PROC_CPU_FAMILY_0X15_OR_CPUF15ORCOREAFTERRESET_FILECODE (0xCB20) -#define PROC_CPU_FAMILY_0X15_OR_CPUF15ORDMI_FILECODE (0xCB21) -#define PROC_CPU_FAMILY_0X15_OR_CPUF15ORNBAFTERRESET_FILECODE (0xCB22) -#define PROC_CPU_FAMILY_0X15_OR_CPUF15ORPSTATE_FILECODE (0xCB23) -#define PROC_CPU_FAMILY_0X15_OR_F15ORL3FEATURES_FILECODE (0xCB24) -#define PROC_CPU_FAMILY_0X15_OR_F15ORMSGBASEDC1E_FILECODE (0xCB25) -#define PROC_CPU_FAMILY_0X15_OR_F15ORLOGICALIDTABLES_FILECODE (0xCB26) -#define PROC_CPU_FAMILY_0X15_OR_F15ORMICROCODEPATCHTABLES_FILECODE (0xCB27) -#define PROC_CPU_FAMILY_0X15_OR_F15ORMSRTABLES_FILECODE (0xCB28) -#define PROC_CPU_FAMILY_0X15_OR_F15ORSHAREDMSRTABLE_FILECODE (0xCB29) -#define PROC_CPU_FAMILY_0X15_OR_F15OREQUIVALENCETABLE_FILECODE (0xCB2A) -#define PROC_CPU_FAMILY_0X15_OR_F15ORPCITABLES_FILECODE (0xCB2B) -#define PROC_CPU_FAMILY_0X15_OR_F15ORPOWERMGMTSYSTEMTABLES_FILECODE (0xCB2C) -#define PROC_CPU_FAMILY_0X15_OR_F15ORPOWERPLANE_FILECODE (0xCB2D) -#define PROC_CPU_FAMILY_0X15_OR_F15ORUTILITIES_FILECODE (0xCB2E) -#define PROC_CPU_FAMILY_0X15_OR_F15ORWORKAROUNDSTABLE_FILECODE (0xCB2F) -#define PROC_CPU_FAMILY_0X15_OR_F15ORPMNBCOFVIDINIT_FILECODE (0xCB30) -#define PROC_CPU_FAMILY_0X15_OR_F15ORLOWPWRPSTATE_FILECODE (0xCB31) -#define PROC_CPU_FAMILY_0X15_OR_F15ORSINGLELINKPCITABLES_FILECODE (0xCB32) -#define PROC_CPU_FAMILY_0X15_OR_F15ORMULTILINKPCITABLES_FILECODE (0xCB33) -#define PROC_CPU_FAMILY_0X15_OR_F15ORC6STATE_FILECODE (0xCB34) -#define PROC_CPU_FAMILY_0X15_OR_F15OREARLYSAMPLES_FILECODE (0xCB35) -#define PROC_CPU_FAMILY_0X15_OR_F15ORCPB_FILECODE (0xCB36) -#define PROC_CPU_FAMILY_0X15_OR_F15ORIOCSTATE_FILECODE (0xCB37) -#define PROC_CPU_FAMILY_0X15_OR_CPUF15ORCACHEFLUSHONHALT_FILECODE (0xCB38) -#define PROC_CPU_FAMILY_0X15_OR_CPUF15ORFEATURELEVELING_FILECODE (0xCB39) -#define PROC_CPU_FAMILY_0X15_OR_CPUF15ORSOFTWARETHERMAL_FILECODE (0xCB3A) -#define PROC_CPU_FAMILY_0X15_OR_F15ORINITEARLYTABLE_FILECODE (0xCB3B) - -#define PROC_CPU_FAMILY_0X15_TN_CPUF15TNCOREAFTERRESET_FILECODE (0xCB50) -#define PROC_CPU_FAMILY_0X15_TN_CPUF15TNDMI_FILECODE (0xCB51) -#define PROC_CPU_FAMILY_0X15_TN_CPUF15TNNBAFTERRESET_FILECODE (0xCB52) -#define PROC_CPU_FAMILY_0X15_TN_CPUF15TNPSTATE_FILECODE (0xCB53) -#define PROC_CPU_FAMILY_0X15_TN_F15TNLOGICALIDTABLES_FILECODE (0xCB54) -#define PROC_CPU_FAMILY_0X15_TN_F15TNMICROCODEPATCHTABLES_FILECODE (0xCB55) -#define PROC_CPU_FAMILY_0X15_TN_F15TNMSRTABLES_FILECODE (0xCB56) -#define PROC_CPU_FAMILY_0X15_TN_F15TNSHAREDMSRTABLE_FILECODE (0xCB57) -#define PROC_CPU_FAMILY_0X15_TN_F15TNEQUIVALENCETABLE_FILECODE (0xCB58) -#define PROC_CPU_FAMILY_0X15_TN_F15TNPCITABLES_FILECODE (0xCB59) -#define PROC_CPU_FAMILY_0X15_TN_F15TNPOWERMGMTSYSTEMTABLES_FILECODE (0xCB5A) -#define PROC_CPU_FAMILY_0X15_TN_F15TNPOWERPLANE_FILECODE (0xCB5B) -#define PROC_CPU_FAMILY_0X15_TN_F15TNUTILITIES_FILECODE (0xCB5C) -#define PROC_CPU_FAMILY_0X15_TN_F15TNC6STATE_FILECODE (0xCB5D) -#define PROC_CPU_FAMILY_0X15_TN_F15TNCPB_FILECODE (0xCB5E) -#define PROC_CPU_FAMILY_0X15_TN_F15TNIOCSTATE_FILECODE (0xCB5F) -#define PROC_CPU_FAMILY_0X15_TN_CPUF15TNCACHEFLUSHONHALT_FILECODE (0xCB60) -#define PROC_CPU_FAMILY_0X15_TN_CPUF15TNSOFTWARETHERMAL_FILECODE (0xCB61) -#define PROC_CPU_FAMILY_0X15_TN_F15TNINITEARLYTABLE_FILECODE (0xCB62) - -#define PROC_CPU_FEATURE_CPUCACHEFLUSHONHALT_FILECODE (0xDC01) -#define PROC_CPU_FEATURE_CPUCACHEINIT_FILECODE (0xDC02) -#define PROC_CPU_FEATURE_CPUDMI_FILECODE (0xDC10) -#define PROC_CPU_FEATURE_CPUFEATURELEVELING_FILECODE (0xDC20) -#define PROC_CPU_FEATURE_CPUL3FEATURES_FILECODE (0xDC30) -#define PROC_CPU_FEATURE_CPUPSTATEGATHER_FILECODE (0xDC41) -#define PROC_CPU_FEATURE_CPUPSTATELEVELING_FILECODE (0xDC42) -#define PROC_CPU_FEATURE_CPUPSTATETABLES_FILECODE (0xDC43) -#define PROC_CPU_FEATURE_CPUSLIT_FILECODE (0xDC50) -#define PROC_CPU_FEATURE_CPUSRAT_FILECODE (0xDC60) -#define PROC_CPU_FEATURE_CPUWHEA_FILECODE (0xDC70) -#define PROC_CPU_FEATURE_CPUHWC1E_FILECODE (0xDC80) -#define PROC_CPU_FEATURE_CPUSWC1E_FILECODE (0xDC81) -#define PROC_CPU_FEATURE_CPUC6STATE_FILECODE (0xDC82) -#define PROC_CPU_FEATURE_CPUCPB_FILECODE (0xDC83) -#define PROC_CPU_FEATURE_CPULOWPWRPSTATE_FILECODE (0xDC84) -#define PROC_CPU_FEATURE_CPUIOCSTATE_FILECODE (0xDC85) -#define PROC_CPU_FEATURE_CPUFEATURES_FILECODE (0xDC90) -#define PROC_CPU_FEATURE_CPUMSGBASEDC1E_FILECODE (0xDCA0) -#define PROC_CPU_FEATURE_CPUCORELEVELING_FILECODE (0xDCB0) -#define PROC_CPU_FEATURE_PRESERVEMAILBOX_FILECODE (0xDCC0) - -#define PROC_RECOVERY_CPU_CPURECOVERY_FILECODE (0xDE01) - -#define PROC_HT_FEATURES_HTFEATSETS_FILECODE (0xE001) -#define PROC_HT_FEATURES_HTFEATDYNAMICDISCOVERY_FILECODE (0xE002) -#define PROC_HT_FEATURES_HTFEATGANGING_FILECODE (0xE003) -#define PROC_HT_FEATURES_HTFEATNONCOHERENT_FILECODE (0xE004) -#define PROC_HT_FEATURES_HTFEATOPTIMIZATION_FILECODE (0xE005) -#define PROC_HT_FEATURES_HTFEATROUTING_FILECODE (0xE006) -#define PROC_HT_FEATURES_HTFEATSUBLINKS_FILECODE (0xE007) -#define PROC_HT_FEATURES_HTFEATTRAFFICDISTRIBUTION_FILECODE (0xE008) -#define PROC_HT_FEATURES_HTIDS_FILECODE (0xE009) -#define PROC_HT_HTFEAT_FILECODE (0xE021) -#define PROC_HT_HTINTERFACE_FILECODE (0xE022) -#define PROC_HT_HTINTERFACECOHERENT_FILECODE (0xE023) -#define PROC_HT_HTINTERFACEGENERAL_FILECODE (0xE024) -#define PROC_HT_HTINTERFACENONCOHERENT_FILECODE (0xE025) -#define PROC_HT_HTMAIN_FILECODE (0xE026) -#define PROC_HT_HTNOTIFY_FILECODE (0xE027) -#define PROC_HT_HTGRAPH_HTGRAPH_FILECODE (0xE028) -#define PROC_HT_HTNB_FILECODE (0xE081) -#define PROC_HT_NBCOMMON_HTNBCOHERENT_FILECODE (0xE082) -#define PROC_HT_NBCOMMON_HTNBNONCOHERENT_FILECODE (0xE083) -#define PROC_HT_NBCOMMON_HTNBOPTIMIZATION_FILECODE (0xE084) -#define PROC_HT_NBCOMMON_HTNBUTILITIES_FILECODE (0xE085) -#define PROC_HT_FAM10_HTNBFAM10_FILECODE (0xE0C1) -#define PROC_HT_FAM10_HTNBCOHERENTFAM10_FILECODE (0xE0C2) -#define PROC_HT_FAM10_HTNBNONCOHERENTFAM10_FILECODE (0xE0C3) -#define PROC_HT_FAM10_HTNBOPTIMIZATIONFAM10_FILECODE (0xE0C4) -#define PROC_HT_FAM10_HTNBSYSTEMFAM10_FILECODE (0xE0C5) -#define PROC_HT_FAM10_HTNBUTILITIESFAM10_FILECODE (0xE0C6) -#define PROC_HT_FAM12_HTNBFAM12_FILECODE (0xE101) -#define PROC_HT_FAM12_HTNBUTILITIESFAM12_FILECODE (0xE102) -#define PROC_HT_FAM14_HTNBFAM14_FILECODE (0xE141) -#define PROC_HT_FAM14_HTNBUTILITIESFAM14_FILECODE (0xE142) -#define PROC_HT_FAM15_HTNBFAM15_FILECODE (0xE181) -#define PROC_HT_FAM15_HTNBCOHERENTFAM15_FILECODE (0xE182) -#define PROC_HT_FAM15_HTNBNONCOHERENTFAM15_FILECODE (0xE183) -#define PROC_HT_FAM15_HTNBOPTIMIZATIONFAM15_FILECODE (0xE184) -#define PROC_HT_FAM15_HTNBSYSTEMFAM15_FILECODE (0xE185) -#define PROC_HT_FAM15_HTNBUTILITIESFAM15_FILECODE (0xE186) -#define PROC_HT_FAM15MOD1X_HTNBFAM15MOD1X_FILECODE (0xE187) -#define PROC_HT_FAM15MOD1X_HTNBUTILITIESFAM15MOD1X_FILECODE (0xE188) -#define PROC_HT_FAM14MOD1X_HTNBFAM14MOD1X_FILECODE (0xE189) -#define PROC_HT_FAM14MOD1X_HTNBUTILITIESFAM14MOD1X_FILECODE (0xE18A) - -#define PROC_RECOVERY_HT_HTINITRECOVERY_FILECODE (0xE302) -#define PROC_RECOVERY_HT_HTINITRESET_FILECODE (0xE301) - -#define PROC_IDS_CONTROL_IDSCTRL_FILECODE (0xE801) -#define PROC_IDS_CONTROL_IDSLIB_FILECODE (0xE802) -#define PROC_IDS_DEBUG_IDSDEBUG_FILECODE (0xE803) -#define PROC_IDS_PERF_IDSPERF_FILECODE (0xE804) -#define PROC_IDS_FAMILY_0X10_IDSF10ALLSERVICE_FILECODE (0xE805) -#define PROC_IDS_FAMILY_0X10_BL_IDSF10BLSERVICE_FILECODE (0xE806) -#define PROC_IDS_FAMILY_0X10_DA_IDSF10DASERVICE_FILECODE (0xE807) -#define PROC_IDS_FAMILY_0X10_HY_IDSF10HYSERVICE_FILECODE (0xE808) -#define PROC_IDS_FAMILY_0X10_RB_IDSF10RBSERVICE_FILECODE (0xE809) -#define PROC_IDS_FAMILY_0X12_IDSF12ALLSERVICE_FILECODE (0xE80A) -#define PROC_IDS_FAMILY_0X14_IDSF14ALLSERVICE_FILECODE (0xE80B) -#define PROC_IDS_FAMILY_0X15_IDSF15ALLSERVICE_FILECODE (0xE80C) -#define PROC_IDS_FAMILY_0X15_OR_IDSF15ORALLSERVICE_FILECODE (0xE80D) -#define PROC_IDS_FAMILY_0X15_TN_IDSF15TNALLSERVICE_FILECODE (0xE80E) - -#define PROC_IDS_DEBUG_IDSIDTTABLE_FILECODE (0xE81E) -#define PROC_IDS_CONTROL_IDSNVTOCMOS_FILECODE (0xE81F) - -///0xE820 ~ 0xE840 is reserved for ids extend module - -#define PROC_MEM_ARDK_MA_FILECODE (0xF001) -#define PROC_MEM_ARDK_DR_MARDR2_FILECODE (0xF002) -#define PROC_MEM_ARDK_DR_MARDR3_FILECODE (0xF003) -#define PROC_MEM_ARDK_HY_MARHY3_FILECODE (0xF004) -#define PROC_MEM_ARDK_LN_MASLN3_FILECODE (0xF005) -#define PROC_MEM_ARDK_DR_MAUDR3_FILECODE (0xF006) -#define PROC_MEM_ARDK_HY_MAUHY3_FILECODE (0xF007) -#define PROC_MEM_ARDK_LN_MAULN3_FILECODE (0xF008) -#define PROC_MEM_ARDK_DA_MAUDA3_FILECODE (0xF009) -#define PROC_MEM_ARDK_DA_MASDA2_FILECODE (0xF00A) -#define PROC_MEM_ARDK_DA_MASDA3_FILECODE (0xF00B) -#define PROC_MEM_ARDK_NI_MASNI3_FILECODE (0xF00C) -#define PROC_MEM_ARDK_C32_MARC32_3_FILECODE (0xF00D) -#define PROC_MEM_ARDK_C32_MAUC32_3_FILECODE (0xF00E) -#define PROC_MEM_ARDK_NI_MAUNI3_FILECODE (0xF00F) -#define PROC_MEM_ARDK_ON_MASON3_FILECODE (0xF010) -#define PROC_MEM_ARDK_ON_MAUON3_FILECODE (0xF011) -#define PROC_MEM_ARDK_PH_MASPH3_FILECODE (0xF012) -#define PROC_MEM_ARDK_PH_MAUPH3_FILECODE (0xF013) -#define PROC_MEM_ARDK_OR_MAROR3_FILECODE (0xF014) -#define PROC_MEM_ARDK_OR_MAUOR3_FILECODE (0xF017) -#define PROC_MEM_ARDK_RB_MASRB3_FILECODE (0xF018) -#define PROC_MEM_ARDK_RB_MAURB3_FILECODE (0xF019) - -#define PROC_MEM_FEAT_CHINTLV_MFCHI_FILECODE (0xF081) -#define PROC_MEM_FEAT_CSINTLV_MFCSI_FILECODE (0xF082) -#define PROC_MEM_FEAT_ECC_MFECC_FILECODE (0xF083) -#define PROC_MEM_FEAT_ECC_MFEMP_FILECODE (0xF085) -#define PROC_MEM_FEAT_EXCLUDIMM_MFDIMMEXCLUD_FILECODE (0xF086) -#define PROC_MEM_FEAT_IDENDIMM_MFIDENDIMM_FILECODE (0xF088) -#define PROC_MEM_FEAT_INTLVRN_MFINTLVRN_FILECODE (0xF089) -#define PROC_MEM_FEAT_LVDDR3_MFLVDDR3_FILECODE (0xF08A) -#define PROC_MEM_FEAT_MEMCLR_MFMEMCLR_FILECODE (0xF08B) -#define PROC_MEM_FEAT_NDINTLV_MFNDI_FILECODE (0xF08C) -#define PROC_MEM_FEAT_ODTHERMAL_MFODTHERMAL_FILECODE (0xF08D) -#define PROC_MEM_FEAT_OLSPARE_MFSPR_FILECODE (0xF08E) -#define PROC_MEM_FEAT_PARTRN_MFPARALLELTRAINING_FILECODE (0xF08F) -#define PROC_MEM_FEAT_PARTRN_MFSTANDARDTRAINING_FILECODE (0xF091) -#define PROC_MEM_FEAT_S3_MFS3_FILECODE (0xF092) -#define PROC_MEM_FEAT_TABLE_MFTDS_FILECODE (0xF093) - -#define PROC_MEM_MAIN_MDEF_FILECODE (0xF101) -#define PROC_MEM_MAIN_MINIT_FILECODE (0xF102) -#define PROC_MEM_MAIN_MM_FILECODE (0xF103) -#define PROC_MEM_FEAT_DMI_MFDMI_FILECODE (0xF104) -#define PROC_MEM_MAIN_MMECC_FILECODE (0xF105) -#define PROC_MEM_MAIN_MMEXCLUDEDIMM_FILECODE (0xF106) -#define PROC_MEM_MAIN_DR_MMFLOWDR_FILECODE (0xF107) -#define PROC_MEM_MAIN_HY_MMFLOWHY_FILECODE (0xF108) -#define PROC_MEM_MAIN_LN_MMFLOWLN_FILECODE (0xF109) -#define PROC_MEM_MAIN_ON_MMFLOWON_FILECODE (0xF10A) -#define PROC_MEM_MAIN_MMNODEINTERLEAVE_FILECODE (0xF10B) -#define PROC_MEM_MAIN_MMONLINESPARE_FILECODE (0xF10C) -#define PROC_MEM_MAIN_MMPARALLELTRAINING_FILECODE (0xF10D) -#define PROC_MEM_MAIN_MMSTANDARDTRAINING_FILECODE (0xF10E) -#define PROC_MEM_MAIN_MUC_FILECODE (0xF10F) -#define PROC_MEM_MAIN_MMMEMCLR_FILECODE (0xF110) -#define PROC_MEM_MAIN_DA_MMFLOWDA_FILECODE (0xF111) -#define PROC_MEM_MAIN_MMFLOW_FILECODE (0xF112) -#define PROC_MEM_MAIN_MERRHDL_FILECODE (0xF113) -#define PROC_MEM_MAIN_C32_MMFLOWC32_FILECODE (0xF114) -#define PROC_MEM_MAIN_MMLVDDR3_FILECODE (0xF115) -#define PROC_MEM_MAIN_MMUMAALLOC_FILECODE (0xF116) -#define PROC_MEM_MAIN_MMMEMRESTORE_FILECODE (0xF117) -#define PROC_MEM_MAIN_MMCONDITIONALPSO_FILECODE (0xF118) -#define PROC_MEM_MAIN_OR_MMFLOWOR_FILECODE (0xF119) -#define PROC_MEM_MAIN_RB_MMFLOWRB_FILECODE (0xF11A) -#define PROC_MEM_MAIN_PH_MMFLOWPH_FILECODE (0xF11B) -#define PROC_MEM_MAIN_TN_MMFLOWTN_FILECODE (0xF11C) -#define PROC_MEM_MAIN_KR_MMFLOWKR_FILECODE (0xF11D) - -#define PROC_MEM_NB_DR_MNDR_FILECODE (0XF213) -#define PROC_MEM_NB_DR_MNFLOWDR_FILECODE (0XF214) -#define PROC_MEM_NB_DR_MNIDENDIMMDR_FILECODE (0XF216) -#define PROC_MEM_NB_DR_MNMCTDR_FILECODE (0XF217) -#define PROC_MEM_NB_DR_MNDCTDR_FILECODE (0XF218) -#define PROC_MEM_NB_DR_MNOTDR_FILECODE (0XF219) -#define PROC_MEM_NB_DR_MNPARTRAINDR_FILECODE (0XF21A) -#define PROC_MEM_NB_DR_MNPROTODR_FILECODE (0XF21C) -#define PROC_MEM_NB_DR_MNS3DR_FILECODE (0XF21D) -#define PROC_MEM_NB_DR_MNREGDR_FILECODE (0XF21E) -#define PROC_MEM_NB_RB_MNRB_FILECODE (0XF220) -#define PROC_MEM_NB_RB_MNFLOWRB_FILECODE (0XF221) -#define PROC_MEM_NB_RB_MNS3RB_FILECODE (0XF222) -#define PROC_MEM_NB_RB_MNIDENDIMMRB_FILECODE (0XF223) -#define PROC_MEM_NB_HY_MNFLOWHY_FILECODE (0XF233) -#define PROC_MEM_NB_HY_MNHY_FILECODE (0XF235) -#define PROC_MEM_NB_HY_MNIDENDIMMHY_FILECODE (0XF236) -#define PROC_MEM_NB_HY_MNMCTHY_FILECODE (0XF237) -#define PROC_MEM_NB_HY_MNDCTHY_FILECODE (0XF238) -#define PROC_MEM_NB_HY_MNOTHY_FILECODE (0XF239) -#define PROC_MEM_NB_HY_MNPARTRAINHY_FILECODE (0XF23A) -#define PROC_MEM_NB_HY_MNPHYHY_FILECODE (0XF23B) -#define PROC_MEM_NB_HY_MNPROTOHY_FILECODE (0XF23C) -#define PROC_MEM_NB_HY_MNS3HY_FILECODE (0XF23D) -#define PROC_MEM_NB_HY_MNREGHY_FILECODE (0XF23E) -#define PROC_MEM_NB_ON_MNON_FILECODE (0xF240) -#define PROC_MEM_NB_ON_MNREGON_FILECODE (0xF241) -#define PROC_MEM_NB_ON_MNDCTON_FILECODE (0xF242) -#define PROC_MEM_NB_ON_MNIDENDIMMON_FILECODE (0xF244) -#define PROC_MEM_NB_ON_MNMCTON_FILECODE (0xF245) -#define PROC_MEM_NB_ON_MNOTON_FILECODE (0xF246) -#define PROC_MEM_NB_ON_MNPHYON_FILECODE (0xF247) -#define PROC_MEM_NB_ON_MNS3ON_FILECODE (0xF248) -#define PROC_MEM_NB_ON_MNFLOWON_FILECODE (0xF249) -#define PROC_MEM_NB_ON_MNPROTOON_FILECODE (0xF24A) -#define PROC_MEM_NB_LN_MNDCTLN_FILECODE (0XF252) -#define PROC_MEM_NB_LN_MNFLOWLN_FILECODE (0XF253) -#define PROC_MEM_NB_LN_MNIDENDIMMLN_FILECODE (0XF254) -#define PROC_MEM_NB_LN_MNMCTLN_FILECODE (0XF255) -#define PROC_MEM_NB_LN_MNOTLN_FILECODE (0XF256) -#define PROC_MEM_NB_LN_MNPHYLN_FILECODE (0XF257) -#define PROC_MEM_NB_LN_MNPROTOLN_FILECODE (0XF258) -#define PROC_MEM_NB_LN_MNLN_FILECODE (0XF259) -#define PROC_MEM_NB_LN_MNS3LN_FILECODE (0XF25A) -#define PROC_MEM_NB_LN_MNREGLN_FILECODE (0XF25B) -#define PROC_MEM_NB_DA_MNDA_FILECODE (0XF260) -#define PROC_MEM_NB_DA_MNFLOWDA_FILECODE (0XF261) -#define PROC_MEM_NB_DA_MNIDENDIMMDA_FILECODE (0XF263) -#define PROC_MEM_NB_DA_MNMCTDA_FILECODE (0XF264) -#define PROC_MEM_NB_DA_MNDCTDA_FILECODE (0XF265) -#define PROC_MEM_NB_DA_MNOTDA_FILECODE (0XF266) -#define PROC_MEM_NB_DA_MNPARTRAINDA_FILECODE (0XF267) -#define PROC_MEM_NB_DA_MNPROTODA_FILECODE (0XF269) -#define PROC_MEM_NB_DA_MNS3DA_FILECODE (0XF26A) -#define PROC_MEM_NB_DA_MNREGDA_FILECODE (0XF26B) -#define PROC_MEM_NB_C32_MNC32_FILECODE (0XF26C) -#define PROC_MEM_NB_C32_MNDCTC32_FILECODE (0XF26D) -#define PROC_MEM_NB_C32_MNFLOWC32_FILECODE (0XF26E) -#define PROC_MEM_NB_C32_MNIDENDIMMC32_FILECODE (0XF26F) -#define PROC_MEM_NB_C32_MNMCTC32_FILECODE (0XF270) -#define PROC_MEM_NB_C32_MNOTC32_FILECODE (0XF271) -#define PROC_MEM_NB_C32_MNPARTRAINC32_FILECODE (0XF272) -#define PROC_MEM_NB_C32_MNPHYC32_FILECODE (0XF273) -#define PROC_MEM_NB_C32_MNPROTOC32_FILECODE (0XF274) -#define PROC_MEM_NB_C32_MNS3C32_FILECODE (0XF275) -#define PROC_MEM_NB_C32_MNREGC32_FILECODE (0XF277) -#define PROC_MEM_NB_MN_FILECODE (0XF27C) -#define PROC_MEM_NB_MNDCT_FILECODE (0XF27D) -#define PROC_MEM_NB_MNPHY_FILECODE (0XF27E) -#define PROC_MEM_NB_MNMCT_FILECODE (0XF27F) -#define PROC_MEM_NB_MNS3_FILECODE (0XF280) -#define PROC_MEM_NB_MNFLOW_FILECODE (0XF281) -#define PROC_MEM_NB_MNFEAT_FILECODE (0XF282) -#define PROC_MEM_NB_MNTRAIN2_FILECODE (0XF283) -#define PROC_MEM_NB_MNTRAIN3_FILECODE (0XF284) -#define PROC_MEM_NB_MNREG_FILECODE (0XF285) -#define PROC_MEM_NB_NI_MNNI_FILECODE (0XF286) -#define PROC_MEM_NB_NI_MNS3NI_FILECODE (0XF287) -#define PROC_MEM_NB_NI_MNFLOWNI_FILECODE (0XF288) -#define PROC_MEM_NB_PH_MNFLOWPH_FILECODE (0XF289) -#define PROC_MEM_NB_PH_MNPH_FILECODE (0XF28A) -#define PROC_MEM_NB_PH_MNS3PH_FILECODE (0XF28B) -#define PROC_MEM_NB_PH_MNIDENDIMMPH_FILECODE (0XF28C) -#define PROC_MEM_NB_OR_MNFLOWOR_FILECODE (0XF290) -#define PROC_MEM_NB_OR_MNOR_FILECODE (0XF291) -#define PROC_MEM_NB_OR_MNIDENDIMMOR_FILECODE (0XF292) -#define PROC_MEM_NB_OR_MNMCTOR_FILECODE (0XF293) -#define PROC_MEM_NB_OR_MNDCTOR_FILECODE (0XF294) -#define PROC_MEM_NB_OR_MNOTOR_FILECODE (0XF295) -#define PROC_MEM_NB_OR_MNPARTRAINOR_FILECODE (0XF296) -#define PROC_MEM_NB_OR_MNPHYOR_FILECODE (0XF297) -#define PROC_MEM_NB_OR_MNPROTOOR_FILECODE (0XF298) -#define PROC_MEM_NB_OR_MNS3OR_FILECODE (0XF299) -#define PROC_MEM_NB_OR_MNREGOR_FILECODE (0XF29A) -#define PROC_MEM_NB_TN_MNREGTN_FILECODE (0XF29B) -#define PROC_MEM_NB_TN_MNTN_FILECODE (0XF29C) -#define PROC_MEM_NB_TN_MNMCTTN_FILECODE (0XF29D) -#define PROC_MEM_NB_TN_MNOTTN_FILECODE (0XF29E) -#define PROC_MEM_NB_TN_MNDCTTN_FILECODE (0XF29F) -#define PROC_MEM_NB_TN_MNPHYTN_FILECODE (0XF2A0) -#define PROC_MEM_NB_TN_MNS3TN_FILECODE (0XF2A1) -#define PROC_MEM_NB_TN_MNIDENDIMMTN_FILECODE (0XF2A2) -#define PROC_MEM_NB_TN_MNFLOWTN_FILECODE (0XF2A3) -#define PROC_MEM_NB_TN_MNPROTOTN_FILECODE (0XF2A4) -#define PROC_MEM_NB_KR_MNREGKR_FILECODE (0xF2A5) -#define PROC_MEM_NB_KR_MNDCTKR_FILECODE (0xF2A6) -#define PROC_MEM_NB_KR_MNIDENDIMMKR_FILECODE (0xF2A7) -#define PROC_MEM_NB_KR_MNMCTKR_FILECODE (0xF2A8) -#define PROC_MEM_NB_KR_MNOTKR_FILECODE (0xF2A9) -#define PROC_MEM_NB_KR_MNPHYKR_FILECODE (0xF2AA) -#define PROC_MEM_NB_KR_MNS3KR_FILECODE (0xF2AB) -#define PROC_MEM_NB_KR_MNFLOWKR_FILECODE (0xF2AC) -#define PROC_MEM_NB_KR_MNPROTOKR_FILECODE (0xF2AD) -#define PROC_MEM_NB_KR_MNKR_FILECODE (0xF2AE) - -#define PROC_MEM_PS_MP_FILECODE (0XF401) -#define PROC_MEM_PS_DR_MPRDR3_FILECODE (0XF402) -#define PROC_MEM_PS_HY_MPRHY3_FILECODE (0XF403) -#define PROC_MEM_PS_LN_MPRLN3_FILECODE (0XF404) -#define PROC_MEM_PS_DR_MPSDR3_FILECODE (0XF405) -#define PROC_MEM_PS_HY_MPSHY3_FILECODE (0XF406) -#define PROC_MEM_PS_LN_MPSLN3_FILECODE (0XF407) -#define PROC_MEM_PS_DR_MPUDR3_FILECODE (0XF408) -#define PROC_MEM_PS_HY_MPUHY3_FILECODE (0XF409) -#define PROC_MEM_PS_LN_MPULN3_FILECODE (0XF40A) -#define PROC_MEM_PS_DA_MPUDA3_FILECODE (0XF40B) -#define PROC_MEM_PS_DA_MPSDA2_FILECODE (0XF40C) -#define PROC_MEM_PS_DA_MPSDA3_FILECODE (0XF40D) -#define PROC_MEM_PS_DR_MPRDR2_FILECODE (0XF40E) -#define PROC_MEM_PS_DR_MPUDR2_FILECODE (0XF40F) -#define PROC_MEM_PS_C32_MPRC32_3_FILECODE (0XF410) -#define PROC_MEM_PS_C32_MPUC32_3_FILECODE (0XF411) -#define PROC_MEM_PS_NI_MPSNI3_FILECODE (0XF412) -#define PROC_MEM_PS_NI_MPUNI3_FILECODE (0XF413) -#define PROC_MEM_PS_ON_MPSON3_FILECODE (0XF414) -#define PROC_MEM_PS_ON_MPUON3_FILECODE (0XF415) -#define PROC_MEM_PS_PH_MPSPH3_FILECODE (0XF416) -#define PROC_MEM_PS_PH_MPUPH3_FILECODE (0XF417) -#define PROC_MEM_PS_RB_MPSRB3_FILECODE (0XF418) -#define PROC_MEM_PS_RB_MPURB3_FILECODE (0XF419) -#define PROC_MEM_PS_OR_AM3_MPUORA3_FILECODE (0XF41A) -#define PROC_MEM_PS_OR_AM3_MPSORA3_FILECODE (0XF41B) -#define PROC_MEM_PS_OR_C32_MPRORC3_FILECODE (0XF41C) -#define PROC_MEM_PS_OR_C32_MPUORC3_FILECODE (0XF41D) -#define PROC_MEM_PS_OR_C32_MPLORC3_FILECODE (0XF41E) -#define PROC_MEM_PS_OR_G34_MPRORG3_FILECODE (0XF41F) -#define PROC_MEM_PS_OR_G34_MPUORG3_FILECODE (0XF420) -#define PROC_MEM_PS_OR_G34_MPLORG3_FILECODE (0XF421) -#define PROC_MEM_PS_MPRTT_FILECODE (0XF422) -#define PROC_MEM_PS_MPMAXFREQ_FILECODE (0XF423) -#define PROC_MEM_PS_MPODTPAT_FILECODE (0XF424) -#define PROC_MEM_PS_MPSAO_FILECODE (0XF425) -#define PROC_MEM_PS_MPMR0_FILECODE (0XF426) -#define PROC_MEM_PS_MPRC2IBT_FILECODE (0XF427) -#define PROC_MEM_PS_MPRC10OPSPD_FILECODE (0XF428) -#define PROC_MEM_PS_MPLRIBT_FILECODE (0XF429) -#define PROC_MEM_PS_MPLRNPR_FILECODE (0XF42A) -#define PROC_MEM_PS_MPLRNLR_FILECODE (0XF42B) -#define PROC_MEM_PS_OR_MPOR3_FILECODE (0XF42C) -#define PROC_MEM_PS_TN_MPSTN3_FILECODE (0XF42D) -#define PROC_MEM_PS_TN_MPTN3_FILECODE (0XF42E) -#define PROC_MEM_PS_TN_MPUTN3_FILECODE (0XF42F) -#define PROC_MEM_PS_TN_FM2_MPUTNFM2_FILECODE (0XF430) -#define PROC_MEM_PS_TN_FP2_MPSTNFP2_FILECODE (0XF431) -#define PROC_MEM_PS_TN_FS1_MPSTNFS1_FILECODE (0XF432) -#define PROC_MEM_PS_KR_MPKR3_FILECODE (0XF433) -#define PROC_MEM_PS_KR_MPUKR3_FILECODE (0XF434) -#define PROC_MEM_PS_KR_MPSKR3_FILECODE (0XF435) - -#define PROC_MEM_TECH_MT_FILECODE (0XF501) -#define PROC_MEM_TECH_MTHDI_FILECODE (0XF502) -#define PROC_MEM_TECH_MTTDIMBT_FILECODE (0XF504) -#define PROC_MEM_TECH_MTTECC_FILECODE (0XF505) -#define PROC_MEM_TECH_MTTHRC_FILECODE (0XF506) -#define PROC_MEM_TECH_MTTML_FILECODE (0XF507) -#define PROC_MEM_TECH_MTTOPTSRC_FILECODE (0XF509) -#define PROC_MEM_TECH_MTTSRC_FILECODE (0XF50B) -#define PROC_MEM_TECH_MTTEDGEDETECT_FILECODE (0XF50C) -#define PROC_MEM_TECH_DDR2_MT2_FILECODE (0XF541) -#define PROC_MEM_TECH_DDR2_MTOT2_FILECODE (0XF543) -#define PROC_MEM_TECH_DDR2_MTSPD2_FILECODE (0XF544) -#define PROC_MEM_TECH_DDR3_MT3_FILECODE (0XF581) -#define PROC_MEM_TECH_DDR3_MTOT3_FILECODE (0XF583) -#define PROC_MEM_TECH_DDR3_MTRCI3_FILECODE (0XF584) -#define PROC_MEM_TECH_DDR3_MTSDI3_FILECODE (0XF585) -#define PROC_MEM_TECH_DDR3_MTSPD3_FILECODE (0XF586) -#define PROC_MEM_TECH_DDR3_MTTWL3_FILECODE (0XF587) -#define PROC_MEM_TECH_DDR3_MTTECC3_FILECODE (0XF588) -#define PROC_MEM_TECH_DDR3_MTLRDIMM3_FILECODE (0XF589) -#define PROC_MEM_TECH_MTTHRCSEEDTRAIN_FILECODE (0XF58A) - -#define PROC_RECOVERY_MEM_MRDEF_FILECODE (0XF801) -#define PROC_RECOVERY_MEM_MRINIT_FILECODE (0XF802) -#define PROC_RECOVERY_MEM_MRM_FILECODE (0XF803) -#define PROC_RECOVERY_MEM_MRUC_FILECODE (0XF804) -#define PROC_RECOVERY_MEM_NB_DR_MRNDR_FILECODE (0XF812) -#define PROC_RECOVERY_MEM_NB_DR_MRNMCTDR_FILECODE (0XF813) -#define PROC_RECOVERY_MEM_NB_HY_MRNDCTHY_FILECODE (0XF821) -#define PROC_RECOVERY_MEM_NB_HY_MRNHY_FILECODE (0XF822) -#define PROC_RECOVERY_MEM_NB_HY_MRNMCTHY_FILECODE (0XF823) -#define PROC_RECOVERY_MEM_NB_HY_MRNPROTOHY_FILECODE (0XF825) -#define PROC_RECOVERY_MEM_NB_LN_MRNDCTLN_FILECODE (0XF831) -#define PROC_RECOVERY_MEM_NB_LN_MRNMCTLN_FILECODE (0XF832) -#define PROC_RECOVERY_MEM_NB_LN_MRNLN_FILECODE (0XF833) -#define PROC_RECOVERY_MEM_NB_DA_MRNDA_FILECODE (0XF842) -#define PROC_RECOVERY_MEM_NB_DA_MRNMCTDA_FILECODE (0XF843) -#define PROC_RECOVERY_MEM_NB_NI_MRNNI_FILECODE (0XF845) -#define PROC_RECOVERY_MEM_NB_C32_MRNC32_FILECODE (0XF851) -#define PROC_RECOVERY_MEM_NB_C32_MRNMCTC32_FILECODE (0XF852) -#define PROC_RECOVERY_MEM_NB_C32_MRNPROTOC32_FILECODE (0XF853) -#define PROC_RECOVERY_MEM_NB_ON_MRNDCTON_FILECODE (0xF861) -#define PROC_RECOVERY_MEM_NB_ON_MRNMCTON_FILECODE (0xF862) -#define PROC_RECOVERY_MEM_NB_ON_MRNON_FILECODE (0xF863) -#define PROC_RECOVERY_MEM_NB_PH_MRNPH_FILECODE (0xF871) -#define PROC_RECOVERY_MEM_NB_RB_MRNRB_FILECODE (0xF881) -#define PROC_RECOVERY_MEM_NB_KR_MRNDCTKR_FILECODE (0xF891) -#define PROC_RECOVERY_MEM_NB_KR_MRNMCTKR_FILECODE (0xF892) -#define PROC_RECOVERY_MEM_NB_KR_MRNKR_FILECODE (0xF893) -#define PROC_RECOVERY_MEM_TECH_MRTTPOS_FILECODE (0XF8C1) -#define PROC_RECOVERY_MEM_TECH_MRTTSRC_FILECODE (0XF8C2) -#define PROC_RECOVERY_MEM_TECH_DDR3_MRT3_FILECODE (0XF8C3) -#define PROC_RECOVERY_MEM_TECH_DDR3_MRTRCI3_FILECODE (0XF8C4) -#define PROC_RECOVERY_MEM_TECH_DDR3_MRTSDI3_FILECODE (0XF8C5) -#define PROC_RECOVERY_MEM_TECH_DDR3_MRTSPD3_FILECODE (0XF8C6) -#define PROC_RECOVERY_MEM_TECH_DDR3_MRTTWL3_FILECODE (0XF8C7) -#define PROC_RECOVERY_MEM_NB_MRN_FILECODE (0XF8C8) -#define PROC_RECOVERY_MEM_NB_MRNDCT_FILECODE (0XF8C9) -#define PROC_RECOVERY_MEM_NB_MRNMCT_FILECODE (0XF8CA) -#define PROC_RECOVERY_MEM_NB_MRNTRAIN3_FILECODE (0XF8CB) -#define PROC_RECOVERY_MEM_TECH_MRTTHRC_FILECODE (0XF8CC) -#define PROC_RECOVERY_MEM_NB_OR_MRNDCTOR_FILECODE (0XF8CD) -#define PROC_RECOVERY_MEM_NB_OR_MRNOR_FILECODE (0XF8CE) -#define PROC_RECOVERY_MEM_NB_OR_MRNMCTOR_FILECODE (0XF8CF) -#define PROC_RECOVERY_MEM_NB_OR_MRNPROTOOR_FILECODE (0XF8D0) -#define PROC_RECOVERY_MEM_PS_MRP_FILECODE (0XF8E0) -#define PROC_RECOVERY_MEM_PS_MRPRTT_FILECODE (0XF8E1) -#define PROC_RECOVERY_MEM_PS_MRPODTPAT_FILECODE (0XF8E2) -#define PROC_RECOVERY_MEM_PS_MRPSAO_FILECODE (0XF8E3) -#define PROC_RECOVERY_MEM_PS_MRPMR0_FILECODE (0XF8E4) -#define PROC_RECOVERY_MEM_PS_MRPRC2IBT_FILECODE (0XF8E5) -#define PROC_RECOVERY_MEM_PS_MRPRC10OPSPD_FILECODE (0XF8E6) -#define PROC_RECOVERY_MEM_PS_MRPLRIBT_FILECODE (0XF8E7) -#define PROC_RECOVERY_MEM_PS_MRPLRNPR_FILECODE (0XF8E8) -#define PROC_RECOVERY_MEM_PS_MRPLRNLR_FILECODE (0XF8E9) -#define PROC_RECOVERY_MEM_PS_OR_MRPOR3_FILECODE (0XF8EA) -#define PROC_RECOVERY_MEM_PS_OR_AM3_MRPSORA3_FILECODE (0XF8EB) -#define PROC_RECOVERY_MEM_PS_OR_AM3_MRPUORA3_FILECODE (0XF8EC) -#define PROC_RECOVERY_MEM_PS_OR_C32_MRPUORC3_FILECODE (0XF8ED) -#define PROC_RECOVERY_MEM_PS_OR_C32_MRPRORC3_FILECODE (0XF8EE) -#define PROC_RECOVERY_MEM_PS_OR_C32_MRPLORC3_FILECODE (0XF8EF) -#define PROC_RECOVERY_MEM_PS_OR_G34_MRPUORG3_FILECODE (0XF8F0) -#define PROC_RECOVERY_MEM_PS_OR_G34_MRPRORG3_FILECODE (0XF8F1) -#define PROC_RECOVERY_MEM_PS_OR_G34_MRPLORG3_FILECODE (0XF8F2) -#define PROC_RECOVERY_MEM_NB_TN_MRNDCTTN_FILECODE (0XF8F3) -#define PROC_RECOVERY_MEM_NB_TN_MRNTN_FILECODE (0XF8F4) -#define PROC_RECOVERY_MEM_NB_TN_MRNMCTTN_FILECODE (0XF8F5) -#define PROC_RECOVERY_MEM_NB_TN_MRNPROTOTN_FILECODE (0XF8F6) -#define PROC_RECOVERY_MEM_PS_TN_MRPSTN3_FILECODE (0XF8F7) -#define PROC_RECOVERY_MEM_PS_TN_MRPTN3_FILECODE (0XF8F8) -#define PROC_RECOVERY_MEM_PS_TN_MRPUTN3_FILECODE (0XF8F9) -#define PROC_RECOVERY_MEM_TECH_MRTTHRCSEEDTRAIN_FILECODE (0XF8FA) - -#endif // _FILECODE_H_ diff --git a/src/vendorcode/amd/agesa/f12/Include/GeneralServices.h b/src/vendorcode/amd/agesa/f12/Include/GeneralServices.h deleted file mode 100644 index da0ecf5474..0000000000 --- a/src/vendorcode/amd/agesa/f12/Include/GeneralServices.h +++ /dev/null @@ -1,201 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * General Services - * - * Provides Services similar to the external General Services API, except - * suited to use within AGESA components. Socket, Core and PCI identification. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: Common - * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $ - * - */ -/* - ****************************************************************************** - * - * Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - ****************************************************************************** - */ - -#ifndef _GENERAL_SERVICES_H_ -#define _GENERAL_SERVICES_H_ - -/*---------------------------------------------------------------------------------------- - * M I X E D (Definitions And Macros / Typedefs, Structures, Enums) - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------- - * D E F I N I T I O N S A N D M A C R O S - *---------------------------------------------------------------------------------------- - */ -#define NUMBER_OF_EVENT_DATA_PARAMS 4 - -/** - * AMD Device id for MMIO check. - */ -#define AMD_DEV_VEN_ID 0x1022 -#define AMD_DEV_VEN_ID_ADDRESS 0 - -/*---------------------------------------------------------------------------------------- - * T Y P E D E F S, S T R U C T U R E S, E N U M S - *---------------------------------------------------------------------------------------- - */ - -/** - * An AGESA Event Log entry. - */ -typedef struct { - AGESA_STATUS EventClass; ///< The severity of the event, its associated AGESA_STATUS. - UINT32 EventInfo; ///< Uniquely identifies the event. - UINT32 DataParam1; ///< Event specific additional data - UINT32 DataParam2; ///< Event specific additional data - UINT32 DataParam3; ///< Event specific additional data - UINT32 DataParam4; ///< Event specific additional data -} AGESA_EVENT; - -/*---------------------------------------------------------------------------------------- - * F U N C T I O N P R O T O T Y P E - *---------------------------------------------------------------------------------------- - */ - -/** - * Get a specified Core's APIC ID. - * - * @param[in] StdHeader Header for library and services. - * @param[in] Socket The Core's Socket. - * @param[in] Core The Core id. - * @param[out] ApicAddress The Core's APIC ID. - * @param[out] AgesaStatus Aggregates AGESA_STATUS for external interface, Always Succeeds. - * - * @retval TRUE The core is present, APIC Id valid - * @retval FALSE The core is not present, APIC Id not valid. - */ -BOOLEAN -GetApicId ( - IN AMD_CONFIG_PARAMS *StdHeader, - IN UINT32 Socket, - IN UINT32 Core, - OUT UINT8 *ApicAddress, - OUT AGESA_STATUS *AgesaStatus -); - -/** - * Get Processor Module's PCI Config Space address. - * - * @param[in] StdHeader Header for library and services. - * @param[in] Socket The Core's Socket. - * @param[in] Module The Module in that Processor - * @param[out] PciAddress The Processor's PCI Config Space address (Function 0, Register 0) - * @param[out] AgesaStatus Aggregates AGESA_STATUS for external interface, Always Succeeds. - * - * @retval TRUE The core is present, PCI Address valid - * @retval FALSE The core is not present, PCI Address not valid. - */ -BOOLEAN -GetPciAddress ( - IN AMD_CONFIG_PARAMS *StdHeader, - IN UINT32 Socket, - IN UINT32 Module, - OUT PCI_ADDR *PciAddress, - OUT AGESA_STATUS *AgesaStatus -); - -/** - * "Who am I" for the current running core. - * - * @param[in] StdHeader Header for library and services. - * @param[out] Socket The current Core's Socket - * @param[out] Module The current Core's Processor Module - * @param[out] Core The current Core's core id. - * @param[out] AgesaStatus Aggregates AGESA_STATUS for external interface, Always Succeeds. - * - */ -VOID -IdentifyCore ( - IN AMD_CONFIG_PARAMS *StdHeader, - OUT UINT32 *Socket, - OUT UINT32 *Module, - OUT UINT32 *Core, - OUT AGESA_STATUS *AgesaStatus -); - -/** - * A boolean function determine executed CPU is BSP core. - */ -BOOLEAN -IsBsp ( - IN OUT AMD_CONFIG_PARAMS *StdHeader, - OUT AGESA_STATUS *AgesaStatus - ); - -/** - * This function logs AGESA events into the event log. - */ -VOID -PutEventLog ( - IN AGESA_STATUS EventClass, - IN UINT32 EventInfo, - IN UINT32 DataParam1, - IN UINT32 DataParam2, - IN UINT32 DataParam3, - IN UINT32 DataParam4, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -/** - * This function gets event logs from the circular buffer. - */ -AGESA_STATUS -GetEventLog ( - OUT AGESA_EVENT *EventRecord, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -/** - * This function gets event logs from the circular buffer without flushing the entry. - */ -BOOLEAN -PeekEventLog ( - OUT AGESA_EVENT *EventRecord, - IN UINT16 Index, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -/*---------------------------------------------------------------------------------------*/ -/** - * This routine programs the registers necessary to get the PCI MMIO mechanism - * up and functioning. - */ -VOID -InitializePciMmio ( - IN AMD_CONFIG_PARAMS *StdHeader - ); - -#endif // _GENERAL_SERVICES_H_ diff --git a/src/vendorcode/amd/agesa/f12/Include/GnbInterface.h b/src/vendorcode/amd/agesa/f12/Include/GnbInterface.h deleted file mode 100644 index bde490ab96..0000000000 --- a/src/vendorcode/amd/agesa/f12/Include/GnbInterface.h +++ /dev/null @@ -1,99 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * GNB API definition. - * - * - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: GNB - * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $ - * - */ -/* -***************************************************************************** -* -* Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* *************************************************************************** -* -*/ - -#ifndef _GNBINTERFACE_H_ -#define _GNBINTERFACE_H_ - -AGESA_STATUS -GnbInitAtReset ( - IN AMD_CONFIG_PARAMS *StdHeader - ); - -AGESA_STATUS -GnbInitAtEarly ( - IN OUT AMD_EARLY_PARAMS *EarlyParamsPtr - ); - -AGESA_STATUS -GnbInitAtPost ( - IN OUT AMD_POST_PARAMS *PostParamsPtr - ); - -VOID -GnbInitDataStructAtEnvDef ( - IN OUT GNB_ENV_CONFIGURATION *GnbEnvConfigPtr, - IN AMD_ENV_PARAMS *EnvParamsPtr - ); - -AGESA_STATUS -GnbInitAtEnv ( - IN AMD_ENV_PARAMS *EnvParamsPtr - ); - -AGESA_STATUS -GnbInitAtMid ( - IN OUT AMD_MID_PARAMS *MidParamsPtr - ); - -AGESA_STATUS -GnbInitAtLate ( - IN OUT AMD_LATE_PARAMS *LateParamsPtr - ); - -AGESA_STATUS -GnbInitAtPostAfterDram ( - IN OUT AMD_POST_PARAMS *PostParamsPtr - ); - -AGESA_STATUS -AmdGnbRecovery ( - IN AMD_CONFIG_PARAMS *StdHeader - ); - -AGESA_STATUS -GnbInitAtEarlier ( - IN OUT AMD_EARLY_PARAMS *EarlyParamsPtr - ); -#endif diff --git a/src/vendorcode/amd/agesa/f12/Include/GnbInterfaceStub.h b/src/vendorcode/amd/agesa/f12/Include/GnbInterfaceStub.h deleted file mode 100644 index 46dc7b6cce..0000000000 --- a/src/vendorcode/amd/agesa/f12/Include/GnbInterfaceStub.h +++ /dev/null @@ -1,249 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * - * - * - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: GNB - * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $ - * - */ -/* -***************************************************************************** -* -* Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* *************************************************************************** -* -*/ - -/*---------------------------------------------------------------------------------------- - * M O D U L E S U S E D - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------- - * D E F I N I T I O N S A N D M A C R O S - *---------------------------------------------------------------------------------------- - */ - - -/*---------------------------------------------------------------------------------------- - * T Y P E D E F S A N D S T R U C T U R E S - *---------------------------------------------------------------------------------------- - */ - - -/*---------------------------------------------------------------------------------------- - * P R O T O T Y P E S O F L O C A L F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ -/*----------------------------------------------------------------------------------------*/ -/** - * Init GNB at Reset Stub - * - * - * - * @param[in] StdHeader Standard configuration header - * @retval AGESA_SUCCESS Always succeeds - */ - -AGESA_STATUS -GnbInitAtReset ( - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - - return AGESA_SUCCESS; -} - -/*----------------------------------------------------------------------------------------*/ -/** - * Init GNB at Early Stub - * - * - * - * @param[in,out] EarlyParamsPtr Pointer to early configuration params. - * @retval AGESA_SUCCESS Always succeeds - */ - -AGESA_STATUS -GnbInitAtEarly ( - IN OUT AMD_EARLY_PARAMS *EarlyParamsPtr - ) -{ - return AGESA_SUCCESS; -} - -/*----------------------------------------------------------------------------------------*/ -/** - * Default constructor of GNB configuration at Env - * - * - * - * @param[in] GnbEnvConfigPtr Pointer to gnb env configuration params. - * @param[in] EnvParamsPtr Pointer to env configuration params. - */ -VOID -GnbInitDataStructAtEnvDef ( - IN OUT GNB_ENV_CONFIGURATION *GnbEnvConfigPtr, - IN AMD_ENV_PARAMS *EnvParamsPtr - ) -{ - -} - -/*----------------------------------------------------------------------------------------*/ -/** - * Init GNB at Env - * - * - * - * @param[in] EnvParamsPtr Pointer to env configuration params. -* @retval AGESA_SUCCESS Always succeeds - */ - -AGESA_STATUS -GnbInitAtEnv ( - IN AMD_ENV_PARAMS *EnvParamsPtr - ) -{ - - return AGESA_SUCCESS; -} - -/*----------------------------------------------------------------------------------------*/ -/** - * Init GNB at Post - * - * - * - * @param[in,out] PostParamsPtr Pointer to Post configuration params. - * @retval AGESA_SUCCESS Always succeeds - */ - -AGESA_STATUS -GnbInitAtPost ( - IN OUT AMD_POST_PARAMS *PostParamsPtr - ) -{ - - return AGESA_SUCCESS; -} - -/*----------------------------------------------------------------------------------------*/ -/** - * Init GNB at Mid post - * - * - * - * @param[in,out] MidParamsPtr Pointer to mid configuration params. - * @retval AGESA_SUCCESS Always succeeds - */ - -AGESA_STATUS -GnbInitAtMid ( - IN OUT AMD_MID_PARAMS *MidParamsPtr - ) -{ - - return AGESA_SUCCESS; -} - -/*----------------------------------------------------------------------------------------*/ -/** - * Init GNB at Late post - * - * - * - * @param[in,out] LateParamsPtr Pointer to late configuration params. - * @retval AGESA_SUCCESS Always succeeds - */ - -AGESA_STATUS -GnbInitAtLate ( - IN OUT AMD_LATE_PARAMS *LateParamsPtr - ) -{ - - return AGESA_SUCCESS; -} - -/*----------------------------------------------------------------------------------------*/ -/** - * AmdGnbRecovery - * - * - * - * @param[in] StdHeader Standard configuration header - * @retval AGESA_SUCCESS Always succeeds - */ -AGESA_STATUS -AmdGnbRecovery ( - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - return AGESA_SUCCESS; -} - -/*----------------------------------------------------------------------------------------*/ -/** - * Init GNB at Post after DRAM init - * - * - * - * @param[in] PostParamsPtr Pointer to post configuration parameters - * @retval AGESA_SUCCESS Always succeeds - */ - -AGESA_STATUS -GnbInitAtPostAfterDram ( - IN OUT AMD_POST_PARAMS *PostParamsPtr - ) -{ - return AGESA_SUCCESS; -} - -/*----------------------------------------------------------------------------------------*/ -/** - * Init GNB at Early Before CPU Stub - * - * - * - * @param[in,out] EarlyParamsPtr Pointer to early configuration params. - * @retval AGESA_SUCCESS Always succeeds - */ - -AGESA_STATUS -GnbInitAtEarlier ( - IN OUT AMD_EARLY_PARAMS *EarlyParamsPtr - ) -{ - return AGESA_SUCCESS; -} diff --git a/src/vendorcode/amd/agesa/f12/Include/Ids.h b/src/vendorcode/amd/agesa/f12/Include/Ids.h deleted file mode 100644 index 3f1f37b72d..0000000000 --- a/src/vendorcode/amd/agesa/f12/Include/Ids.h +++ /dev/null @@ -1,960 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * AMD IDS Routines - * - * Contains AMD AGESA Integrated Debug Macros - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: IDS - * @e \$Revision: 49994 $ @e \$Date: 2011-03-31 15:44:04 +0800 (Thu, 31 Mar 2011) $ - */ -/***************************************************************************** - * - * Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ***************************************************************************/ - - /* Macros to aid debugging */ - /* These definitions expand to zero (0) bytes of code when disabled */ - -#ifndef _IDS_H_ -#define _IDS_H_ - -#undef FALSE -#undef TRUE -#define FALSE 0 -#define TRUE 1 -// Proto type for optionsids.h -typedef UINT32 IDS_STATUS; ///< Status of IDS function. -#define IDS_SUCCESS ((IDS_STATUS) 0x00000000) ///< IDS Function is Successful. -#define IDS_UNSUPPORTED ((IDS_STATUS) 0xFFFFFFFF) ///< IDS Function is not existed. - -#define IDS_STRINGIZE(a) #a ///< for define stringize macro -/** - * IDS Option Hook Points - * - * These are the values to indicate hook point in AGESA for IDS Options. - * - */ -typedef enum { //vv- for debug reference only - IDS_INIT_EARLY_BEFORE, ///< 00 Option Hook Point before AGESA function AMD_INIT_EARLY. - ///< IDS Object is initialized. - ///< Override CPU Core Leveling Mode. - ///< Set P-State in Post - IDS_INIT_EARLY_AFTER, ///< 01 Option Hook Point after AGESA function AMD_INIT_EARLY. - IDS_INIT_LATE_BEFORE, ///< 02 Option Hook Point before AGESA function AMD_INIT_LATE. - ///< It will be used to control the following tables. - ///< ACPI P-State Table (_PSS, XPSS, _PCT, _PSD, _PPC) - ///< ACPI SRAT Table - ///< ACPI SLIT Table - ///< ACPI WHEA Table - ///< DMI Table - IDS_INIT_LATE_AFTER, ///< 03 Option Hook Point after AGESA function AMD_INIT_LATE. - IDS_INIT_MID_BEFORE, ///< 04 Option Hook Point before AGESA function AMD_INIT_MID. - IDS_INIT_MID_AFTER, ///< 05 Option Hook Point after AGESA function AMD_INIT_MID. - IDS_INIT_POST_BEFORE, ///< 06 Option Hook Point before AGESA function AMD_INIT_POST. - ///< Control Interleaving and DRAM memory hole - ///< Override the setting of ECC Control - ///< Override the setting of Online Spare Rank - IDS_INIT_POST_AFTER, ///< 07 Option Hook Point after AGESA function AMD_INIT_POST. - IDS_INIT_RESET_BEFORE, ///< 08 Option Hook Point before AGESA function AMD_INIT_RESET. - IDS_INIT_RESET_AFTER, ///< 09 Option Hook Point after AGESA function AMD_INIT_RESET. - IDS_INIT_POST_MID, ///< 0a Option Hook Point after AGESA function AMD_INIT_POST. - IDS_BEFORE_S3_SAVE, ///< 0b override any settings before S3 save. - IDS_BEFORE_S3_RESTORE, ///< 0c override any settings before S3 restore - IDS_AFTER_S3_SAVE, ///< 0d Override any settings after S3 save - IDS_AFTER_S3_RESTORE, ///< 0e Override any settings after S3 restore - IDS_BEFORE_DQS_TRAINING, ///< 0f override any settings before DQS training - IDS_BEFORE_DRAM_INIT, ///< 10 override any settings before Dram initialization - IDS_BEFORE_MEM_FREQ_CHG, ///< 11 override settings before MemClk frequency change - IDS_BEFORE_WARM_RESET , ///< 12 Override PCI or MSR Registers Before Warm Reset - IDS_BEFORE_MEM_INIT, ///< 13 Override PCI or MSR Registers Before Memory Init - IDS_BEFORE_PCI_INIT, ///< 14 Override PCI or MSR Registers Before PCI Init - IDS_BEFORE_OS, ///< 15 Override PCI or MSR Registers Before booting to OS - IDS_UCODE, ///< 16 Enable or Disable microcode patching - IDS_BEFORE_AP_EARLY_HALT, ///< 17 Option Hook Point before AP early halt - IDS_BEFORE_S3_RESUME, ///< 18 Option Hook Point before s3 resume - IDS_AFTER_S3_RESUME, ///< 19 Option Hook Point after s3 resume - IDS_BEFORE_PM_INIT, ///< 20 Option Hook Point Before Pm Init - - IDS_PLATFORM_RSVD1 = 0x38, ///< from 0x38 to 0x3f will reserved for platform used - IDS_PLATFORM_RSVD2 = 0x39, ///< from 0x38 to 0x3f will reserved for platform used - IDS_PLATFORM_RSVD3 = 0x3a, ///< from 0x38 to 0x3f will reserved for platform used - IDS_PLATFORM_RSVD4 = 0x3b, ///< from 0x38 to 0x3f will reserved for platform used - IDS_PLATFORM_RSVD5 = 0x3c, ///< from 0x38 to 0x3f will reserved for platform used - IDS_PLATFORM_RSVD6 = 0x3d, ///< from 0x38 to 0x3f will reserved for platform used - IDS_PLATFORM_RSVD7 = 0x3e, ///< from 0x38 to 0x3f will reserved for platform used - IDS_PLATFORM_RSVD8 = 0x3f, ///< from 0x38 to 0x3f will reserved for platform used - - // All the above timing point is used by BVM, their value should never be changed - IDS_HT_CONTROL, ///< 40 Override the setting of HT Link Control - IDS_HT_TRISTATE, ///< 41 Enable or Disable HT Tri-state during an LDTSTP# - IDS_INIT_DRAM_TABLE, ///< 42 Generate override table for Dram Timing - ///< Dram Controller, Drive Strength and DQS Timing - IDS_GET_DRAM_TABLE, ///< 43 Generate override table for Dram Timing - IDS_GANGING_MODE, ///< 44 override Memory Mode Unganged - IDS_POWERDOWN_MODE, ///< 45 override Power Down Mode - IDS_BURST_LENGTH32, ///< 46 override Burst Length32 - IDS_ALL_MEMORY_CLOCK, ///< 47 override All Memory Clks Enable - IDS_ECC, ///< 48 override ECC parameter - IDS_ECCSYMBOLSIZE, ///< 49 override ECC symbol size - IDS_CPU_Early_Override, ///< 4a override CPU early parameter - IDS_CACHE_FLUSH_HLT, ///< 4b override Cache Flush Hlt - IDS_CHANNEL_INTERLEAVE, ///< 4c override Channel Interleave - IDS_MEM_ERROR_RECOVERY, ///< 4d override memory error recovery - IDS_MEM_RETRAIN_TIMES, ///< 4e override memory retrain times - IDS_MEM_SIZE_OVERLAY, ///< 4f Override the syslimit - IDS_HT_ASSIST, ///< 50 Override Probe Filter - IDS_CHECK_NEGATIVE_WL, ///< 51 Check for negative write leveling result - IDS_DLL_SHUT_DOWN, ///< 52 Check for Dll Shut Down - IDS_POR_MEM_FREQ, ///< 53 Entry to enable/disable MemClk frequency enforcement - IDS_PHY_DLL_STANDBY_CTRL, ///< 54 Enable/Disable Phy DLL standby feature - IDS_PLATFORMCFG_OVERRIDE, ///< 55 Hook for Override PlatformConfig structure - IDS_LOADCARD_ERROR_RECOVERY, ///< 56 Special error handling for load card support - IDS_MEM_IGNORE_ERROR, ///< 57 Ignore error and do not do fatal exit in memory - IDS_GNB_SMU_SERVICE_CONFIG, ///< 58 Config GNB SMU service - IDS_GNB_ORBDYNAMIC_WAKE, ///< 59 config GNB dynamic wake - IDS_GNB_PLATFORMCFG_OVERRIDE, ///< 5a override ids gnb platform config - IDS_GNB_LCLK_DPM_EN, ///< 5b override GNB LCLK DPM configuration - IDS_GNB_LCLK_DEEP_SLEEP, ///< 5c override GNB LCLK DPM deep sleep - IDS_GNB_CLOCK_GATING, ///< 5d Override GNB Clock gating config - IDS_NB_PSTATE_DIDVID, ///< 5e Override NB P-state settings - IDS_CPB_CTRL, ///< 5f Config the Core peformance boost feature - IDS_HTC_CTRL, ///< 60 Hook for Hardware Thermal Control - IDS_CC6_WORKAROUND, ///< 61 Hook for skip CC6 work around - IDS_MEM_MR0, ///< 62 Hook for override Memory Mr0 register - IDS_REG_TABLE, ///< 63 Hook for add IDS register table to the loop - IDS_NBBUFFERALLOCATIONATEARLY, ///< 64 Hook for override North bridge bufer allocation - IDS_BEFORE_S3_SPECIAL, ///< 65 Hook to bypass S3 special functions - IDS_SET_PCI_REGISTER_ENTRY, ///< 66 Hook to SetRegisterForPciEntry - IDS_ERRATUM463_WORKAROUND, ///< 67 Hook to Erratum 463 workaround - IDS_BEFORE_MEMCLR, ///< 68 Hook before set Memclr bit - IDS_OVERRIDE_IO_CSTATE, ///< 69 Hook for override io C-state setting - IDS_NBPSDIS_OVERRIDE, ///< 6a Hook for override NB pstate disable setting - IDS_NBPS_REG_OVERRIDE, ///< 6b Hook for override Memory NBps reg - IDS_LOW_POWER_PSTATE, ///< 6c Hook for disalbe Low power_Pstates feature - IDS_CST_CREATE, ///< 6d Hook for create _CST - IDS_CST_SIZE, ///< 6e Hook for get _CST size - IDS_ENFORCE_VDDIO, ///< 6f Hook to override VDDIO - IDS_SKIP_PERFORMANCE_OPT, ///< 70 Hook to skip performance optimization - IDS_INIT_MEM_REG_TABLE, ///< 71 Hook for init memory register table - IDS_SKIP_FUSED_MAX_RATE, ///< 72 Hook to skip fused max rate cap - IDS_FCH_INIT_AT_RESET, ///< 73 Hook for FCH reset parameter - IDS_FCH_INIT_AT_ENV, ///< 74 Hook for FCH ENV parameter - IDS_ENFORCE_PLAT_TABLES, ///< 75 Hook to enforce platform specific tables - IDS_NBPS_MIN_FREQ, ///< 76 Hook for override MIN nb ps freq - IDS_GNB_FORCE_CABLESAFE, ///< 77 Hook for override Force Cable Safe - IDS_SKIP_PM_TRANSITION_STEP, ///< 78 Hook for provide IDS ability to skip this PM step - IDS_GNB_PROPERTY, ///< 79 Hook for GNB Property - IDS_GNB_PCIE_POWER_GATING, ///< 7A Hook for GNB PCIe Power Gating - IDS_MEM_DYN_DRAM_TERM, ///< 7B Hook for Override Dynamic Dram Term - IDS_MEM_DRAM_TERM, ///< 7C Hook for Override Dram Term - IDS_TRACE_MODE, ///< 7D Trace Mode - IDS_GNB_ALTVDDNB, ///< 7E Hook for Override AltVddNB -} AGESA_IDS_OPTION; - -#include "OptionsIds.h" -#include "Filecode.h" - -/* Initialize IDS controls */ -#ifndef IDSOPT_IDS_ENABLED - #define IDSOPT_IDS_ENABLED FALSE -#endif - -#ifndef IDSOPT_CONTROL_ENABLED - #define IDSOPT_CONTROL_ENABLED FALSE -#endif - -#ifndef IDSOPT_CONTROL_NV_TO_CMOS - #define IDSOPT_CONTROL_NV_TO_CMOS FALSE -#endif - -#ifndef IDSOPT_TRACING_ENABLED - #define IDSOPT_TRACING_ENABLED FALSE -#endif - -#ifndef IDSOPT_TRACE_USER_OPTIONS - #define IDSOPT_TRACE_USER_OPTIONS TRUE -#endif - -#ifndef IDSOPT_PERF_ANALYSIS - #define IDSOPT_PERF_ANALYSIS FALSE -#endif - -#ifndef IDSOPT_HEAP_CHECKING - #define IDSOPT_HEAP_CHECKING FALSE -#endif - -#ifndef IDSOPT_ASSERT_ENABLED - #define IDSOPT_ASSERT_ENABLED FALSE -#endif - -#ifndef IDSOPT_ERROR_TRAP_ENABLED - #define IDSOPT_ERROR_TRAP_ENABLED FALSE -#endif - -#ifndef IDSOPT_CAR_CORRUPTION_CHECK_ENABLED - #define IDSOPT_CAR_CORRUPTION_CHECK_ENABLED FALSE -#endif - -#ifndef IDSOPT_DEBUG_CODE_ENABLED - #define IDSOPT_DEBUG_CODE_ENABLED FALSE -#endif - -#ifndef IDSOPT_IDT_EXCEPTION_TRAP - #define IDSOPT_IDT_EXCEPTION_TRAP FALSE -#endif - -#ifndef IDSOPT_C_OPTIMIZATION_DISABLED - #define IDSOPT_C_OPTIMIZATION_DISABLED FALSE -#endif - -#if IDSOPT_IDS_ENABLED == FALSE - #undef IDSOPT_CONTROL_ENABLED - #undef IDSOPT_TRACING_ENABLED - #undef IDSOPT_PERF_ANALYSIS - #undef IDSOPT_HEAP_CHECKING - #undef IDSOPT_ASSERT_ENABLED - #undef IDSOPT_ERROR_TRAP_ENABLED - #undef IDSOPT_CAR_CORRUPTION_CHECK_ENABLED - #undef IDSOPT_DEBUG_CODE_ENABLED - #undef IDSOPT_TRACE_USER_OPTIONS - - #define IDSOPT_CONTROL_ENABLED FALSE - #define IDSOPT_TRACING_ENABLED FALSE - #define IDSOPT_PERF_ANALYSIS FALSE - #define IDSOPT_HEAP_CHECKING FALSE - #define IDSOPT_ASSERT_ENABLED FALSE - #define IDSOPT_ERROR_TRAP_ENABLED FALSE - #define IDSOPT_CAR_CORRUPTION_CHECK_ENABLED FALSE - #define IDSOPT_DEBUG_CODE_ENABLED FALSE - #define IDSOPT_TRACE_USER_OPTIONS FALSE -#endif - -/** - * Make a Progress Report to the User. - * - * This Macro is always enabled. The default action is to write the TestPoint value - * to an I/O port. The I/O port is 8 bits in size and the default address is 0x80. - * IBVs can change AGESA's default port by defining IDS_DEBUG_PORT to desired port - * in OptionsIds.h in their build tip. - * - * @param[in] TestPoint The value for display indicating progress - * @param[in,out] StdHeader Pointer of AMD_CONFIG_PARAMS - * - **/ - -#define AGESA_TESTPOINT(TestPoint, StdHeader) - -#ifndef IDS_DEBUG_PORT - #define IDS_DEBUG_PORT 0x80 -#endif - -/** - * @def STOP_HERE - * (macro) - Causes program to halt. This is @b only for use during active debugging . - * - * Causes the program to halt and display the file number of the source of the - * halt (displayed in decimal). - * - **/ -#if IDSOPT_IDS_ENABLED == TRUE - #ifdef STOP_CODE - #undef STOP_CODE - #endif - #define STOP_CODE (((UINT32)FILECODE)*0x10000 + \ - ((__LINE__) % 10) + (((__LINE__ / 10) % 10)*0x10) + \ - (((__LINE__ / 100) % 10)*0x100) + (((__LINE__ / 1000) % 10)*0x1000)) - #define STOP_HERE -#else - #define STOP_HERE -#endif - -/** - * @def ASSERT - * Test an assertion that the given statement is True. - * - * The statement is evaluated to a boolean value. If the statement is True, - * then no action is taken (no error). If the statement is False, a error stop - * is generated to halt the program. Used for testing for fatal errors that - * must be resolved before production. This is used to do parameter checks, - * bounds checking, range checks and 'sanity' checks. - * - * @param[in] conditional Assert that evaluating this conditional results in TRUE. - * - **/ -#ifndef ASSERT - #if IDSOPT_ASSERT_ENABLED == TRUE - #ifdef STOP_CODE - #undef STOP_CODE - #endif - #define STOP_CODE (((UINT32)FILECODE)*0x10000 + \ - ((__LINE__) % 10) + (((__LINE__ / 10) % 10)*0x10) + \ - (((__LINE__ / 100) % 10)*0x100) + (((__LINE__ / 1000) % 10)*0x1000)) - - #define ASSERT(conditional) - #else - #define ASSERT(conditional) - #endif -#endif - -#if IDSOPT_CAR_CORRUPTION_CHECK_ENABLED == TRUE - #undef IDSOPT_ERROR_TRAP_ENABLED - #define IDSOPT_ERROR_TRAP_ENABLED TRUE - #define IDS_CAR_CORRUPTION_CHECK(StdHeader) -#else - #define IDS_CAR_CORRUPTION_CHECK(StdHeader) -#endif -/** - * @def DEBUG_CODE - * Make the code active when IDSOPT_DEBUG_CODE_ENABLED enable - * - */ -#ifndef DEBUG_CODE - #if IDSOPT_DEBUG_CODE_ENABLED == TRUE - #define DEBUG_CODE(Code) - #else - #define DEBUG_CODE(Code) - #endif -#endif - -/** - * @def IDS_ERROR_TRAP - * Trap AGESA Error events with stop code display. - * - * Works similarly to use of "ASSERT (FALSE);" - * - */ -#if IDSOPT_ERROR_TRAP_ENABLED == TRUE - #ifdef STOP_CODE - #undef STOP_CODE - #endif - #define STOP_CODE (((UINT32)FILECODE)*0x10000 + \ - ((__LINE__) % 10) + (((__LINE__ / 10) % 10)*0x10) + \ - (((__LINE__ / 100) % 10)*0x100) + (((__LINE__ / 1000) % 10)*0x1000)) - - #define IDS_ERROR_TRAP -#else - #define IDS_ERROR_TRAP -#endif - -///give the extended Macro default value -#ifndef __IDS_EXTENDED__ - #define IDS_EXTENDED_HOOK(idsoption, dataptr, idsnvptr, stdheader) IDS_SUCCESS - #define IDS_INITIAL_F10_PM_STEP - #define IDS_INITIAL_F12_PM_STEP - #define IDS_INITIAL_F14_PM_STEP - #define IDS_INITIAL_F15_PM_STEP - #define IDS_EXTENDED_GET_DATA_EARLY(data, StdHeader) - #define IDS_EXTENDED_GET_DATA_LATE(data, StdHeader) - #define IDS_EXTENDED_HEAP_SIZE 0 - #define IDS_EXT_INCLUDE_F10(file) - #define IDS_EXT_INCLUDE_F12(file) - #define IDS_EXT_INCLUDE_F14(file) - #define IDS_EXT_INCLUDE_F15(file) - #define IDS_EXT_INCLUDE(file) -#endif - -#ifndef IDS_NUM_NV_ITEM - #define IDS_NUM_NV_ITEM (IDS_NUM_EXT_NV_ITEM) -#endif - -#if IDSOPT_CONTROL_ENABLED == TRUE - #define IDS_OPTION_HOOK(IdsOption, DataPtr, StdHeader) - - #define IDS_OPTION_CALLOUT(CallOutId, DataPtr, StdHeader) -#else - #define IDS_OPTION_HOOK(IdsOption, DataPtr, StdHeader) - - #define IDS_OPTION_CALLOUT(CallOutId, DataPtr, StdHeader) -#endif - -/** - * Macro to add a *skip* hook for IDS options - * - * The default minimal action is to do nothing and there is no any code to increase. - * For debug environments, IDS dispatcher function will be called to perform - * the detailed action and to skip AGESA code if necessary. - * - * @param[in] IdsOption IDS Option ID for this hook point - * @param[in, out] DataPtr Data Pointer to override - * @param[in, out] StdHeader Pointer of AMD_CONFIG_PARAMS - * - * - **/ - -#if IDSOPT_CONTROL_ENABLED == TRUE - #define IDS_SKIP_HOOK(IdsOption, DataPtr, StdHeader) -#else - #define IDS_SKIP_HOOK(IdsOption, DataPtr, StdHeader) -#endif - -/** - * Macro to add a heap manager routine - * - * when memory is allocated the heap manager actually allocates two extra dwords of data, - * one dword buffer before the actual memory, and one dword afterwards. - * a complete heap walk and check to be performed at any time. - * it would ASSERT if the heap is corrupt - * - * @param[in] StdHeader Pointer of AMD_CONFIG_PARAMS - * - * - **/ - -// Heap debug feature -#define SENTINEL_BEFORE_VALUE 0x64616548 // "Head" -#define SENTINEL_AFTER_VALUE 0x6C696154 // "Tail" -#if IDSOPT_IDS_ENABLED == TRUE - #if IDSOPT_HEAP_CHECKING == TRUE - #define SIZE_OF_SENTINEL 0 - #define NUM_OF_SENTINEL 0 - #define SET_SENTINEL_BEFORE(NodePtr, AlignTo16Byte) - #define SET_SENTINEL_AFTER(NodePtr) - #define Heap_Check(stdheader) -#else - #define SIZE_OF_SENTINEL 0 - #define NUM_OF_SENTINEL 0 - #define SET_SENTINEL_BEFORE(NodePtr, AlignTo16Byte) - #define SET_SENTINEL_AFTER(NodePtr) - #define Heap_Check(stdheader) -#endif - #else - #define SIZE_OF_SENTINEL 0 - #define NUM_OF_SENTINEL 0 - #define SET_SENTINEL_BEFORE(NodePtr, AlignTo16Byte) - #define SET_SENTINEL_AFTER(NodePtr) - #define Heap_Check(stdheader) -#endif - - - //Note a is from 0 to 63 -#define DEBUG_PRINT_SHIFT(a) ((UINT64)1 << a) -//If you change the Bitmap definition below, please change the Hash in ParseFilter of hdtout2008.pl accordingly -//Memory Masks -#define MEM_SETREG DEBUG_PRINT_SHIFT (0) -#define MEM_GETREG DEBUG_PRINT_SHIFT (1) -#define MEM_FLOW DEBUG_PRINT_SHIFT (2) -#define MEM_STATUS DEBUG_PRINT_SHIFT (3) -#define MEMORY_TRACE_RSV1 DEBUG_PRINT_SHIFT (4) -#define MEMORY_TRACE_RSV2 DEBUG_PRINT_SHIFT (5) -#define MEMORY_TRACE_RSV3 DEBUG_PRINT_SHIFT (6) -#define MEMORY_TRACE_RSV4 DEBUG_PRINT_SHIFT (7) -#define MEMORY_TRACE_RSV5 DEBUG_PRINT_SHIFT (8) -#define MEMORY_TRACE_RSV6 DEBUG_PRINT_SHIFT (9) - - - -//CPU Masks -#define CPU_TRACE DEBUG_PRINT_SHIFT (10) -#define CPU_TRACE_RSV1 DEBUG_PRINT_SHIFT (11) -#define CPU_TRACE_RSV2 DEBUG_PRINT_SHIFT (12) -#define CPU_TRACE_RSV3 DEBUG_PRINT_SHIFT (13) -#define CPU_TRACE_RSV4 DEBUG_PRINT_SHIFT (14) -#define CPU_TRACE_RSV5 DEBUG_PRINT_SHIFT (15) -#define CPU_TRACE_RSV6 DEBUG_PRINT_SHIFT (16) -#define CPU_TRACE_RSV7 DEBUG_PRINT_SHIFT (17) -#define CPU_TRACE_RSV8 DEBUG_PRINT_SHIFT (18) -#define CPU_TRACE_RSV9 DEBUG_PRINT_SHIFT (19) - -//GNB Masks -#define GNB_TRACE DEBUG_PRINT_SHIFT (20) -#define PCIE_MISC DEBUG_PRINT_SHIFT (21) -#define PCIE_PORTREG_TRACE DEBUG_PRINT_SHIFT (22) -#define PCIE_HOSTREG_TRACE DEBUG_PRINT_SHIFT (23) -#define GNB_TRACE_RSV2 DEBUG_PRINT_SHIFT (24) -#define NB_MISC DEBUG_PRINT_SHIFT (25) -#define GNB_TRACE_RSV3 DEBUG_PRINT_SHIFT (26) -#define GFX_MISC DEBUG_PRINT_SHIFT (27) -#define NB_SMUREG_TRACE DEBUG_PRINT_SHIFT (28) -#define GNB_TRACE_RSV1 DEBUG_PRINT_SHIFT (29) - -//HT Masks -#define HT_TRACE DEBUG_PRINT_SHIFT (30) -#define HT_TRACE_RSV1 DEBUG_PRINT_SHIFT (31) -#define HT_TRACE_RSV2 DEBUG_PRINT_SHIFT (32) -#define HT_TRACE_RSV3 DEBUG_PRINT_SHIFT (33) -#define HT_TRACE_RSV4 DEBUG_PRINT_SHIFT (34) -#define HT_TRACE_RSV5 DEBUG_PRINT_SHIFT (35) -#define HT_TRACE_RSV6 DEBUG_PRINT_SHIFT (36) -#define HT_TRACE_RSV7 DEBUG_PRINT_SHIFT (37) -#define HT_TRACE_RSV8 DEBUG_PRINT_SHIFT (38) -#define HT_TRACE_RSV9 DEBUG_PRINT_SHIFT (39) - -//FCH Masks -#define FCH_TRACE DEBUG_PRINT_SHIFT (40) -#define FCH_TRACE_RSV1 DEBUG_PRINT_SHIFT (41) -#define FCH_TRACE_RSV2 DEBUG_PRINT_SHIFT (42) -#define FCH_TRACE_RSV3 DEBUG_PRINT_SHIFT (43) -#define FCH_TRACE_RSV4 DEBUG_PRINT_SHIFT (44) -#define FCH_TRACE_RSV5 DEBUG_PRINT_SHIFT (45) -#define FCH_TRACE_RSV6 DEBUG_PRINT_SHIFT (46) -#define FCH_TRACE_RSV7 DEBUG_PRINT_SHIFT (47) -#define FCH_TRACE_RSV8 DEBUG_PRINT_SHIFT (48) -#define FCH_TRACE_RSV9 DEBUG_PRINT_SHIFT (49) - -//Other Masks -#define MAIN_FLOW DEBUG_PRINT_SHIFT (50) -#define EVENT_LOG DEBUG_PRINT_SHIFT (51) -#define PERFORMANCE_ANALYSE DEBUG_PRINT_SHIFT (52) - -//Ids Masks -#define IDS_TRACE DEBUG_PRINT_SHIFT (53) -#define IDS_REG DEBUG_PRINT_SHIFT (54) -#define IDS_TRACE_RSV2 DEBUG_PRINT_SHIFT (55) -#define IDS_TRACE_RSV3 DEBUG_PRINT_SHIFT (56) - -//S3 -#define S3_TRACE DEBUG_PRINT_SHIFT (57) - -//Library function to read/write PCI/MSR registers -#define LIB_PCI_RD DEBUG_PRINT_SHIFT (58) -#define LIB_PCI_WR DEBUG_PRINT_SHIFT (59) - -//Reserved -#define TRACE_RSV3 DEBUG_PRINT_SHIFT (60) -#define TRACE_RSV4 DEBUG_PRINT_SHIFT (61) -#define TRACE_RSV5 DEBUG_PRINT_SHIFT (62) -#define TRACE_RSV6 DEBUG_PRINT_SHIFT (63) - -#define GNB_TRACE_DEFAULT 0 - -#define GNB_TRACE_REG 0 - -#define GNB_TRACE_ALL 0 - -#define CPU_TRACE_ALL 0 - -#define MEMORY_TRACE_ALL 0 - -#define HT_TRACE_ALL 0 - -#define FCH_TRACE_ALL 0 - -#define IDS_TRACE_ALL 0 - -#define OTHER_TRACE_ALL 0 - -#define TRACE_MASK_ALL (0ull) -#ifndef IDS_DEBUG_PRINT_MASK - #define IDS_DEBUG_PRINT_MASK 0 -#endif - - -/** - * Macro to add HDT OUT - * - * The default minimal action is to do nothing and there is no any code to increase. - * For debug environments, the debug information can be displayed in HDT or other - * devices. - * - **/ -#if IDSOPT_IDS_ENABLED == TRUE - #if IDSOPT_TRACING_ENABLED == TRUE - #define IDS_HDT_CONSOLE_INIT(x) - #define IDS_HDT_CONSOLE_EXIT(x) - #define IDS_HDT_CONSOLE_S3_EXIT(x) - #define IDS_HDT_CONSOLE_S3_AP_EXIT(x) - - #if IDSOPT_C_OPTIMIZATION_DISABLED == TRUE - #ifdef __GNUC__ - #define IDS_HDT_CONSOLE(f, s, ...) - #else - #define IDS_HDT_CONSOLE(f, s, ...) - #endif - #else - #pragma warning(disable: 4127) - #ifdef __GNUC__ - #define IDS_HDT_CONSOLE(f, s, ...) - #else - #define IDS_HDT_CONSOLE(f, s, ...) - #endif - #endif - - #define IDS_HDT_CONSOLE_FLUSH_BUFFER(x) - #define IDS_HDT_CONSOLE_ASSERT(x) - #define IDS_FUNCLIST_ADDR NULL - #define IDS_FUNCLIST_EXTERN() - #define IDS_TIMEOUT_CTL(t) - #define IDS_HDT_CONSOLE_DEBUG_CODE(Code) - #define CONSOLE(s, ...) - #else - #define IDS_HDT_CONSOLE_INIT(x) - #define IDS_HDT_CONSOLE_EXIT(x) - #define IDS_HDT_CONSOLE_S3_EXIT(x) - #define IDS_HDT_CONSOLE_S3_AP_EXIT(x) - #define IDS_HDT_CONSOLE(f, s, ...) - #define IDS_HDT_CONSOLE_FLUSH_BUFFER(x) - #define IDS_HDT_CONSOLE_ASSERT(x) - #define IDS_FUNCLIST_ADDR NULL - #define IDS_FUNCLIST_EXTERN() - #define IDS_TIMEOUT_CTL(t) - #define IDS_HDT_CONSOLE_DEBUG_CODE(Code) - #define CONSOLE(s, ...) - #endif -#else - #define IDS_HDT_CONSOLE_INIT(x) - #define IDS_HDT_CONSOLE_EXIT(x) - #define IDS_HDT_CONSOLE_S3_EXIT(x) - #define IDS_HDT_CONSOLE_S3_AP_EXIT(x) - #define IDS_HDT_CONSOLE(f, s, ...) - #define IDS_HDT_CONSOLE_FLUSH_BUFFER(x) - #define IDS_HDT_CONSOLE_ASSERT(x) - #define IDS_FUNCLIST_ADDR NULL - #define IDS_FUNCLIST_EXTERN() - #define IDS_TIMEOUT_CTL(t) - #define IDS_HDT_CONSOLE_DEBUG_CODE(Code) - #define CONSOLE(s, ...) -#endif - -#define IDS_TRACE_SHOW_BLD_OPT_CFG IDSOPT_TRACE_USER_OPTIONS - -#if IDSOPT_PERF_ANALYSIS == TRUE - #define IDS_PERF_TIMESTAMP(StdHeader, TestPoint) - #define IDS_PERF_ANALYSE(StdHeader) - #define IDS_PERF_TIME_MEASURE(StdHeader) -#else - #define IDS_PERF_TIMESTAMP(StdHeader, TestPoint) - #define IDS_PERF_ANALYSE(StdHeader) - #define IDS_PERF_TIME_MEASURE(StdHeader) -#endif - -///For IDS feat use -#define IDS_FAMILY_ALL 0x0ull -#define IDS_BSP_ONLY TRUE -#define IDS_ALL_CORES FALSE - -#define IDS_LATE_RUN_AP_TASK_ID PROC_IDS_CONTROL_IDSLIB_FILECODE - -#define IDS_CALLOUT_INIT 0x00 ///< The function data of IDS callout function of initialization. - -#define IDS_CALLOUT_GNB_PPFUSE_OVERRIDE 0x00 ///< The function data of IDS callout function of GNB pp fuse table. -#define IDS_CALLOUT_GNB_INTEGRATED_TABLE_CONFIG 0x00 ///< The function data of IDS callout function of GNB integrated table. -#define IDS_CALLOUT_GNB_NB_POWERGATE_CONFIG 0x00 ///< The function data of IDS callout function of GNB NB power gate config. -#define IDS_CALLOUT_GNB_PCIE_POWERGATE_CONFIG 0x00 ///< The function data of IDS callout function of GNB PCIE power gateconfig. -#define IDS_CALLOUT_GNB_PCIE_PLATFORM_CONFIG 0x00 ///< The function data of IDS callout function of GNB pcie platform config. -#define IDS_CALLOUT_GNB_PCIE_PHY_CONFIG 0x00 ///< The function data of IDS callout function of GNB pcie PHY config. -#define IDS_CALLOUT_GNB_GMM_REGISTER_OVERRIDE 0x00 ///< The function data of IDS callout function of GNB GMM register override -#define IDS_CALLOUT_MTC1E_PLATFORM_CONFIG 0x00 ///< The function data of IDS callout function of Message Triggered C1e platform config. -#define IDS_CALLOUT_FCH_INIT_RESET 0x00 ///< The function data of IDS callout function of FchInitReset -#define IDS_CALLOUT_FCH_INIT_ENV 0x00 ///< The function data of IDS callout function of FchInitEnv. -/// Function entry for HDT script to call -typedef struct _SCRIPT_FUNCTION { - UINTN FuncAddr; ///< Function address in ROM - CHAR8 FuncName[40]; ///< Function name -} SCRIPT_FUNCTION; - -/// Data Structure for Mem ECC parameter override -typedef struct { - IN BOOLEAN CfgEccRedirection; ///< ECC Redirection - IN UINT16 CfgScrubDramRate; ///< Scrub Dram Rate - IN UINT16 CfgScrubL2Rate; ///< Scrub L2Rate - IN UINT16 CfgScrubL3Rate; ///< Scrub L3Rate - IN UINT16 CfgScrubIcRate; ///< Scrub Ic Rate - IN UINT16 CfgScrubDcRate; ///< Scrub Dc Rate - IN BOOLEAN CfgEccSyncFlood; ///< ECC Sync Flood -} ECC_OVERRIDE_STRUCT; - - - - -/** - * AGESA Test Points - * - * These are the values displayed to the user to indicate progress through boot. - * These can be used in a debug environment to stop the debugger at a specific - * test point: - * For SimNow!, this command - * bi 81 w vb 49 - * will stop the debugger on one of the TracePoints (49 is the TP value in this example). - * - */ -typedef enum { - StartProcessorTestPoints, ///< 00 Entry used for range testing for @b Processor related TPs - - // Memory test points - TpProcMemBeforeMemDataInit, ///< 01 .. Memory structure initialization (Public interface) - TpProcMemBeforeSpdProcessing, ///< 02 .. SPD Data processing (Public interface) - TpProcMemAmdMemAuto, ///< 03 .. Memory configuration (Public interface) - TpProcMemDramInit, ///< 04 .. DRAM initialization - TpProcMemSPDChecking, ///< 05 .. - TpProcMemModeChecking, ///< 06 .. - TpProcMemSpeedTclConfig, ///< 07 .. Speed and TCL configuration - TpProcMemSpdTiming, ///< 08 .. - TpProcMemDramMapping, ///< 09 .. - TpProcMemPlatformSpecificConfig, ///< 0A .. - TPProcMemPhyCompensation, ///< 0B .. - TpProcMemStartDcts, ///< 0C .. - TpProcMemBeforeDramInit, ///< 0D .. (Public interface) - TpProcMemPhyFenceTraining, ///< 0E .. - TpProcMemSynchronizeDcts, ///< 0F .. - TpProcMemSystemMemoryMapping, ///< 10 .. - TpProcMemMtrrConfiguration, ///< 11 .. - TpProcMemDramTraining, ///< 12 .. - TpProcMemBeforeAnyTraining, ///< 13 .. (Public interface) - TpProcMemWriteLevelizationTraining, ///< 14 .. - TpProcMemWlFirstPass, ///< 15 .. Below 800Mhz first pass start - TpProcMemWlSecondPass, ///< 16 .. Above 800Mhz second pass start - TpProcMemWlTrainTargetDimm, ///< 17 .. Target DIMM configured - TpProcMemWlPrepDimms, ///< 18 .. Prepare DIMMS for WL - TpProcMemWlConfigDimms, ///< 19 .. Configure DIMMS for WL - TpProcMemReceiverEnableTraining, ///< 1A .. - TpProcMemRcvrStartSweep, ///< 1B .. Start sweep loop - TpProcMemRcvrSetDelay, ///< 1C .. Set receiver Delay - TpProcMemRcvrWritePattern, ///< 1D .. Write test pattern - TpProcMemRcvrReadPattern, ///< 1E .. Read test pattern - TpProcMemRcvrTestPattern, ///< 1F .. Compare test pattern - TpProcMemRcvrCalcLatency, ///< 20 .. Calculate MaxRdLatency per channel - TpProcMemReceiveDqsTraining, ///< 21 .. - TpProcMemRcvDqsSetDelay, ///< 22 .. Set Write Data delay - TpProcMemRcvDqsWritePattern, ///< 23 .. Write test pattern - TpProcMemRcvDqsStartSweep, ///< 24 .. Start read sweep - TpProcMemRcvDqsSetRcvDelay, ///< 25 .. Set Receive DQS delay - TpProcMemRcvDqsReadPattern, ///< 26 .. Read Test pattern - TpProcMemRcvDqsTstPattern, ///< 27 .. Compare Test pattern - TpProcMemRcvDqsResults, ///< 28 .. Update results - TpProcMemRcvDqsFindWindow, ///< 29 .. Start Find passing window - TpProcMemTransmitDqsTraining, ///< 2A .. - TpProcMemTxDqStartSweep, ///< 2B .. Start write sweep - TpProcMemTxDqSetDelay, ///< 2C .. Set Transmit DQ delay - TpProcMemTxDqWritePattern, ///< 2D .. Write test pattern - TpProcMemTxDqReadPattern, ///< 2E .. Read Test pattern - TpProcMemTxDqTestPattern, ///< 2F .. Compare Test pattern - TpProcMemTxDqResults, ///< 30 .. Update results - TpProcMemTxDqFindWindow, ///< 31 .. Start Find passing window - TpProcMemMaxRdLatencyTraining, ///< 32 .. - TpProcMemMaxRdLatStartSweep, ///< 33 .. Start sweep - TpProcMemMaxRdLatSetDelay, ///< 34 .. Set delay - TpProcMemMaxRdLatWritePattern, ///< 35 .. Write test pattern - TpProcMemMaxRdLatReadPattern, ///< 36 .. Read Test pattern - TpProcMemMaxRdLatTestPattern, ///< 37 .. Compare Test pattern - TpProcMemOnlineSpareInit, ///< 38 .. Online Spare init - TpProcMemBankInterleaveInit, ///< 39 .. Bank Interleave Init - TpProcMemNodeInterleaveInit, ///< 3A .. Node Interleave Init - TpProcMemChannelInterleaveInit, ///< 3B .. Channel Interleave Init - TpProcMemEccInitialization, ///< 3C .. ECC initialization - TpProcMemPlatformSpecificInit, ///< 3D .. Platform Specific Init - TpProcMemBeforeAgesaReadSpd, ///< 3E .. Before callout for "AgesaReadSpd" - TpProcMemAfterAgesaReadSpd, ///< 3F .. After callout for "AgesaReadSpd" - TpProcMemBeforeAgesaHookBeforeDramInit, ///< 40 .. Before optional callout "AgesaHookBeforeDramInit" - TpProcMemAfterAgesaHookBeforeDramInit, ///< 41 .. After optional callout "AgesaHookBeforeDramInit" - TpProcMemBeforeAgesaHookBeforeDQSTraining, ///< 42 .. Before optional callout "AgesaHookBeforeDQSTraining" - TpProcMemAfterAgesaHookBeforeDQSTraining, ///< 43 .. After optional callout "AgesaHookBeforeDQSTraining" - TpProcMemBeforeAgesaHookBeforeExitSelfRef, ///< 44 .. Before optional callout "AgesaHookBeforeDramInit" - TpProcMemAfterAgesaHookBeforeExitSelfRef, ///< 45 .. After optional callout "AgesaHookBeforeDramInit" - TpProcMemAfterMemDataInit, ///< 46 .. After MemDataInit - TpProcMemInitializeMCT, ///< 47 .. Before InitializeMCT - TpProcMemLvDdr3, ///< 48 .. Before LV DDR3 - TpProcMemInitMCT, ///< 49 .. Before InitMCT - TpProcMemOtherTiming, ///< 4A.. Before OtherTiming - TpProcMemUMAMemTyping, ///< 4B .. Before UMAMemTyping - TpProcMemSetDqsEccTmgs, ///< 4C .. Before SetDqsEccTmgs - TpProcMemMemClr, ///< 4D .. Before MemClr - TpProcMemOnDimmThermal, ///< 4E .. Before On DIMM Thermal - TpProcMemDmi, ///< 4F .. Before DMI - TpProcMemEnd, ///< 50 .. End of memory code - - // CPU test points - TpProcCpuEntryDmi, ///< 51 .. Entry point CreateDmiRecords - TpProcCpuEntryPstate, ///< 52 .. Entry point GenerateSsdt - TpProcCpuEntryPstateLeveling, ///< 53 .. Entry point PStateLeveling - TpProcCpuEntryPstateGather, ///< 54 .. Entry point PStateGatherData - TpProcCpuEntryWhea, ///< 55 .. Entry point CreateAcpiWhea - TpProcCpuEntrySrat, ///< 56 .. Entry point CreateAcpiSrat - TpProcCpuEntrySlit, ///< 57 .. Entry point CreateAcpiSlit - TpProcCpuProcessRegisterTables, ///< 58 .. Register table processing - TpProcCpuSetBrandID, ///< 59 .. Set brand ID - TpProcCpuLocalApicInit, ///< 5A .. Initialize local APIC - TpProcCpuLoadUcode, ///< 5B .. Load microcode patch - TpProcCpuBeforePMFeatureInit, ///< 5C .. BeforePM feature dispatch point - TpProcCpuPowerMgmtInit, ///< 5D .. Power Management table processing - TpProcCpuEarlyFeatureInit, ///< 5E .. Early feature dispatch point - TpProcCpuCoreLeveling, ///< 5F .. Core Leveling - TpProcCpuApMtrrSync, ///< 60 .. AP MTRR sync up - TpProcCpuPostFeatureInit, ///< 61 .. POST feature dispatch point - TpProcCpuFeatureLeveling, ///< 62 .. CPU Feature Leveling - TpProcCpuBeforeRelinquishAPsFeatureInit, ///< 63 .. Before Relinquishing control of APs feature dispatch point - TpProcCpuBeforeAllocateWheaBuffer, ///< 64 .. Before the WHEA init code calls out to allocate a buffer - TpProcCpuAfterAllocateWheaBuffer, ///< 65 .. After the WHEA init code calls out to allocate a buffer - TpProcCpuBeforeAllocateSratBuffer, ///< 66 .. Before the SRAT init code calls out to allocate a buffer - TpProcCpuAfterAllocateSratBuffer, ///< 67 .. After the SRAT init code calls out to allocate a buffer - TpProcCpuBeforeLocateSsdtBuffer, ///< 68 .. Before the P-state init code calls out to locate a buffer - TpProcCpuAfterLocateSsdtBuffer, ///< 69 .. After the P-state init code calls out to locate a buffer - TpProcCpuBeforeAllocateSsdtBuffer, ///< 6A .. Before the P-state init code calls out to allocate a buffer - TpProcCpuAfterAllocateSsdtBuffer, ///< 6B .. After the P-state init code calls out to allocate a buffer - - // HT test points - TpProcHtEntry = 0x71, ///< 71 .. Coherent Discovery begin (Public interface) - TpProcHtTopology, ///< 72 .. Topology match, routing, begin - TpProcHtManualNc, ///< 73 .. Manual Non-coherent Init begin - TpProcHtAutoNc, ///< 74 .. Automatic Non-coherent init begin - TpProcHtOptGather, ///< 75 .. Optimization: Gather begin - TpProcHtOptRegang, ///< 76 .. Optimization: Regang begin - TpProcHtOptLinks, ///< 77 .. Optimization: Link Begin - TpProcHtOptSubLinks, ///< 78 .. Optimization: Sublinks begin - TpProcHtOptFinish, ///< 79 .. Optimization: Set begin - TpProcHtTrafficDist, ///< 7A .. Traffic Distribution begin - TpProcHtTuning, ///< 7B .. Misc Tuning Begin - TpProcHtDone, ///< 7C .. HT Init complete - TpProcHtApMapEntry, ///< 7D .. AP HT: Init Maps begin - TpProcHtApMapDone, ///< 7E .. AP HT: Complete - - // Extended memory test point - TpProcMemSendMRS2 = 0x80, ///< 80 .. Sending MRS2 - TpProcMemSendMRS3, ///< 81 .. Sedding MRS3 - TpProcMemSendMRS1, ///< 82 .. Sending MRS1 - TpProcMemSendMRS0, ///< 83 .. Sending MRS0 - TpProcMemContinPatternGenRead, ///< 84 .. Continuous Pattern Read - TpProcMemContinPatternGenWrite, ///< 85 .. Continuous Pattern Write - - StartNbTestPoints = 0x90, ///< 90 Entry used for range testing for @b NorthBridge related TPs - TpNbxxx, ///< 91 . - EndNbTestPoints, ///< 92 End of TP range for NB - - StartSbTestPoints = 0xB0, ///< B0 Entry used for range testing for @b SouthBridge related TPs - TpSbxxx, ///< B1 . - EndSbTestPoints, ///< B2 End of TP range for SB - - // Interface test points - TpIfAmdInitResetEntry = 0xC0, ///< C0 .. Entry to AmdInitReset - TpIfAmdInitResetExit, ///< C1 .. Exiting from AmdInitReset - TpIfAmdInitRecoveryEntry, ///< C2 .. Entry to AmdInitRecovery - TpIfAmdInitRecoveryExit, ///< C3 .. Exiting from AmdInitRecovery - TpIfAmdInitEarlyEntry, ///< C4 .. Entry to AmdInitEarly - TpIfAmdInitEarlyExit, ///< C5 .. Exiting from AmdInitEarly - TpIfAmdInitPostEntry, ///< C6 .. Entry to AmdInitPost - TpIfAmdInitPostExit, ///< C7 .. Exiting from AmdInitPost - TpIfAmdInitEnvEntry, ///< C8 .. Entry to AmdInitEnv - TpIfAmdInitEnvExit, ///< C9 .. Exiting from AmdInitEnv - TpIfAmdInitMidEntry, ///< CA .. Entry to AmdInitMid - TpIfAmdInitMidExit, ///< CB .. Exiting from AmdInitMid - TpIfAmdInitLateEntry, ///< CC .. Entry to AmdInitLate - TpIfAmdInitLateExit, ///< CD .. Exiting from AmdInitLate - TpIfAmdS3SaveEntry, ///< CE .. Entry to AmdS3Save - TpIfAmdS3SaveExit, ///< CF .. Exiting from AmdS3Save - TpIfAmdInitResumeEntry, ///< D0 .. Entry to AmdInitResume - TpIfAmdInitResumeExit, ///< D1 .. Exiting from AmdInitResume - TpIfAmdS3LateRestoreEntry, ///< D2 .. Entry to AmdS3LateRestore - TpIfAmdS3LateRestoreExit, ///< D3 .. Exiting from AmdS3LateRestore - TpIfAmdLateRunApTaskEntry, ///< D4 .. Entry to AmdS3LateRestore - TpIfAmdLateRunApTaskExit, ///< D5 .. Exiting from AmdS3LateRestore - TpIfAmdReadEventLogEntry, ///< D6 .. Entry to AmdReadEventLog - TpIfAmdReadEventLogExit, ///< D7 .. Exiting from AmdReadEventLog - TpIfAmdGetApicIdEntry, ///< D8 .. Entry to AmdGetApicId - TpIfAmdGetApicIdExit, ///< D9 .. Exiting from AmdGetApicId - TpIfAmdGetPciAddressEntry, ///< DA .. Entry to AmdGetPciAddress - TpIfAmdGetPciAddressExit, ///< DB .. Exiting from AmdGetPciAddress - TpIfAmdIdentifyCoreEntry, ///< DC .. Entry to AmdIdentifyCore - TpIfAmdIdentifyCoreExit, ///< DD .. Exiting from AmdIdentifyCore - TpIfBeforeRunApFromIds, ///< DE .. After IDS calls out to run code on an AP - TpIfAfterRunApFromIds, ///< DF .. After IDS calls out to run code on an AP - TpIfBeforeGetIdsData, ///< E0 .. Before IDS calls out to get IDS data - TpIfAfterGetIdsData, ///< E1 .. After IDS calls out to get IDS data - TpIfBeforeAllocateHeapBuffer, ///< E2 .. Before the heap manager calls out to allocate a buffer - TpIfAfterAllocateHeapBuffer, ///< E3 .. After the heap manager calls out to allocate a buffer - TpIfBeforeDeallocateHeapBuffer, ///< E4 .. Before the heap manager calls out to deallocate a buffer - TpIfAfterDeallocateHeapBuffer, ///< E5 .. After the heap manager calls out to deallocate a buffer - TpIfBeforeLocateHeapBuffer, ///< E6 .. Before the heap manager calls out to locate a buffer - TpIfAfterLocateHeapBuffer, ///< E7 .. After the heap manager calls out to locate a buffer - TpIfBeforeRunApFromAllAps, ///< E8 .. Before the BSP calls out to run code on an AP - TpIfAfterRunApFromAllAps, ///< E9 .. After the BSP calls out to run code on an AP - TpIfBeforeRunApFromAllCore0s, ///< EA .. Before the BSP calls out to run code on an AP - TpIfAfterRunApFromAllCore0s, ///< EB .. After the BSP calls out to run code on an AP - TpIfBeforeAllocateS3SaveBuffer, ///< EC .. Before the S3 save code calls out to allocate a buffer - TpIfAfterAllocateS3SaveBuffer, ///< ED .. After the S3 save code calls out to allocate a buffer - TpIfBeforeAllocateMemoryS3SaveBuffer, ///< EE .. Before the memory S3 save code calls out to allocate a buffer - TpIfAfterAllocateMemoryS3SaveBuffer, ///< EF .. After the memory S3 save code calls out to allocate a buffer - TpIfBeforeLocateS3PciBuffer, ///< F0 .. Before the memory code calls out to locate a buffer - TpIfAfterLocateS3PciBuffer, ///< F1 .. After the memory code calls out to locate a buffer - TpIfBeforeLocateS3CPciBuffer, ///< F2 .. Before the memory code calls out to locate a buffer - TpIfAfterLocateS3CPciBuffer, ///< F3 .. After the memory code calls out to locate a buffer - TpIfBeforeLocateS3MsrBuffer, ///< F4 .. Before the memory code calls out to locate a buffer - TpIfAfterLocateS3MsrBuffer, ///< F5 .. After the memory code calls out to locate a buffer - TpIfBeforeLocateS3CMsrBuffer, ///< F6 .. Before the memory code calls out to locate a buffer - TpIfAfterLocateS3CMsrBuffer, ///< F7 .. After the memory code calls out to locate a buffer - TpPerfUnit, ///< F8 .. The Unit of performance measure. - EndAgesaTps = 0xFF, ///< Last defined AGESA TP -} AGESA_TP; - -///Ids Feat description -typedef enum { - IDS_FEAT_UCODE_UPDATE = 0x0000, ///< Feat for Ucode Update - IDS_FEAT_TARGET_PSTATE, ///< Feat for Target Pstate - IDS_FEAT_POSTPSTATE, ///< Feat for Post Pstate - IDS_FEAT_ECC_CTRL, ///< Feat for Ecc Control - IDS_FEAT_ECC_SYMBOL_SIZE, ///< Feat for Ecc symbol size - IDS_FEAT_DCT_ALLMEMCLK, ///< Feat for all memory clock - IDS_FEAT_DCT_GANGMODE, ///< Feat for Dct gang mode - IDS_FEAT_DCT_BURSTLENGTH, ///< Feat for dct burst length - IDS_FEAT_DCT_POWERDOWN, ///< Feat for dct power down - IDS_FEAT_DCT_DLLSHUTDOWN, ///< Feat for dct dll shut down - IDS_FEAT_PROBE_FILTER, ///< Feat for probe filter - IDS_FEAT_HDTOUT, ///< Feat for hdt out - IDS_FEAT_HT_SETTING, ///< Feat for Ht setting - IDS_FEAT_GNB_PLATFORMCFG, ///< Feat for override GNB platform config - IDS_FEAT_CPB_CTRL, ///< Feat for Config the Core peformance boost feature - IDS_FEAT_HTC_CTRL, ///< Feat for Hardware Thermal Control - IDS_FEAT_MEMORY_MAPPING, ///< Feat for Memory Mapping - IDS_FEAT_POWER_POLICY, ///< Feat for Power Policy - IDS_FEAT_NV_TO_CMOS, ///< Feat for Save BSP Nv to CMOS - IDS_FEAT_END = 0xFF ///< End of Common feat -} IDS_FEAT; - -typedef IDS_STATUS IDS_COMMON_FUNC ( - IN OUT VOID *DataPtr, - IN OUT AMD_CONFIG_PARAMS *StdHeader, - IN IDS_NV_ITEM *IdsNvPtr - ); - -typedef IDS_COMMON_FUNC *PIDS_COMMON_FUNC; - -/// Data Structure of IDS Feature block -typedef struct _IDS_FEAT_STRUCT { - IDS_FEAT IdsFeat; ///< Ids Feat ID - BOOLEAN IsBsp; ///< swith for Bsp check - AGESA_IDS_OPTION IdsOption; ///< IDS option - UINT64 CpuFamily; ///< - PIDS_COMMON_FUNC pf_idsoption; /// /P /EP /C /FAs @n - * PreProcessor output is produced in an .i file in the directory where the project - * file is located. - * - Design Guides: - * - add here >>> - * - */ - -/** - * @page platforminstall Platform Build Options. - * - * Build options are boolean constants. The purpose of build options is to remove code - * from the build to reduce the overall code size present in the ROM image. Unless - * otherwise specified, the default action is to include all options. If a build option is - * not specifically listed as disabled, then it is included into the build. - * - * The documented build options are imported from a user controlled file for - * processing. The build options for all platform solutions are listed below: - * - * @anchor BLDOPT_REMOVE_UDIMMS_SUPPORT - * @li @e BLDOPT_REMOVE_UDIMMS_SUPPORT @n - * If unbuffered DIMMs are NOT expected to be required in the system, the code that - * handles unbuffered DIMMs can be removed from the build. - * - * @anchor BLDOPT_REMOVE_RDIMMS_SUPPORT - * @li @e BLDOPT_REMOVE_RDIMMS_SUPPORT @n - * If registered DIMMs are NOT expected to be required in the system, the code - * that handles registered DIMMs can be removed from the build. - * - * @anchor BLDOPT_REMOVE_LRDIMMS_SUPPORT - * @li @e BLDOPT_REMOVE_LRDIMMS_SUPPORT @n - * If Load Reduced DIMMs are NOT expected to be required in the system, the code - * that handles Load Reduced DIMMs can be removed from the build. - * - * @note The above three options operate independently from each other; however, at - * least one of the unbuffered , registered or load reduced DIMM options must be present in the build. - * - * @anchor BLDOPT_REMOVE_ECC_SUPPORT - * @li @e BLDOPT_REMOVE_ECC_SUPPORT @n - * Use this option to remove the code for Error Checking & Correction. - * - * @anchor BLDOPT_REMOVE_BANK_INTERLEAVE - * @li @e BLDOPT_REMOVE_BANK_INTERLEAVE @n - * Interleaving is a mechanism to do performance fine tuning. This option - * interleaves memory between banks on a DIMM. - * - * @anchor BLDOPT_REMOVE_DCT_INTERLEAVE - * @li @e BLDOPT_REMOVE_DCT_INTERLEAVE @n - * Interleaving is a mechanism to do performance fine tuning. This option - * interleaves memory from two DRAM controllers. - * - * @anchor BLDOPT_REMOVE_NODE_INTERLEAVE - * @li @e BLDOPT_REMOVE_NODE_INTERLEAVE @n - * Interleaving is a mechanism to do performance fine tuning. This option - * interleaves memory from two HyperTransport nodes. - * - * @anchor BLDOPT_REMOVE_PARALLEL_TRAINING - * @li @e BLDOPT_REMOVE_PARALLEL_TRAINING @n - * For multi-socket systems, training memory in parallel can reduce the time - * needed to boot. - * - * @anchor BLDOPT_REMOVE_ONLINE_SPARE_SUPPORT - * @li @e BLDOPT_REMOVE_ONLINE_SPARE_SUPPORT @n - * Online Spare support is removed by this option. - * - * @anchor BLDOPT_REMOVE_MULTISOCKET_SUPPORT - * @li @e BLDOPT_REMOVE_MULTISOCKET_SUPPORT @n - * Many systems use only a single socket and may benefit in code space to remove - * this code. However, certain processors have multiple HyperTransport nodes - * within a single socket. For these processors, the multi-node support is - * required and this option has no effect. - * - * @anchor BLDOPT_REMOVE_ACPI_PSTATES - * @li @e BLDOPT_REMOVE_ACPI_PSTATES @n - * This option removes the code that generates the ACPI tables used in power - * management. - * - * @anchor BLDOPT_REMOVE_SRAT - * @li @e BLDOPT_REMOVE_SRAT @n - * This option removes the code that generates the SRAT tables used in performance - * tuning. - * - * @anchor BLDOPT_REMOVE_SLIT - * @li @e BLDOPT_REMOVE_SLIT @n - * This option removes the code that generates the SLIT tables used in performance - * tuning. - * - * @anchor BLDOPT_REMOVE_WHEA - * @li @e BLDOPT_REMOVE_WHEA @n - * This option removes the code that generates the WHEA tables used in error - * handling and reporting. - * - * @anchor BLDOPT_REMOVE_DMI - * @li @e BLDOPT_REMOVE_DMI @n - * This option removes the code that generates the DMI tables used in system - * management. - * - * @anchor BLDOPT_REMOVE_DQS_TRAINING - * @li @e BLDOPT_REMOVE_DQS_TRAINING @n - * This option removes the code used in memory performance tuning. - * - * @anchor BLDOPT_REMOVE_EARLY_SAMPLES - * @li @e BLDOPT_REMOVE_EARLY_SAMPLES @n - * Special support for Early Samples is included. Default setting is FALSE. - * - * @anchor BLDOPT_REMOVE_HT_ASSIST - * @li @e BLDOPT_REMOVE_HT_ASSIST @n - * This option removes the code which implements the HT Assist feature. - * - * @anchor BLDOPT_REMOVE_ATM_MODE - * @li @e BLDOPT_REMOVE_ATM_MODE @n - * This option removes the code which implements the ATM feature. - * - * @anchor BLDOPT_REMOVE_MSG_BASED_C1E - * @li @e BLDOPT_REMOVE_MSG_BASED_C1E @n - * This option removes the code which implements the Message Based C1e feature. - * - * @anchor BLDOPT_REMOVE_C6_STATE - * @li @e BLDOPT_REMOVE_C6_STATE @n - * This option removes the code which implements the C6 C-state feature. - * - * @anchor BLDOPT_REMOVE_MEM_RESTORE_SUPPORT - * @li @e BLDOPT_REMOVE_MEM_RESTORE_SUPPORT @n - * This option removes the memory context restore feature. - * - * @anchor BLDOPT_REMOVE_FAMILY_10_SUPPORT - * @li @e BLDOPT_REMOVE_FAMILY_10_SUPPORT @n - * If the package contains support for family 10h processors, remove that support. - * - * @anchor BLDOPT_REMOVE_FAMILY_12_SUPPORT - * @li @e BLDOPT_REMOVE_FAMILY_12_SUPPORT @n - * If the package contains support for family 10h processors, remove that support. - * - * @anchor BLDOPT_REMOVE_FAMILY_14_SUPPORT - * @li @e BLDOPT_REMOVE_FAMILY_14_SUPPORT @n - * If the package contains support for family 14h processors, remove that support. - * - * @anchor BLDOPT_REMOVE_FAMILY_15_SUPPORT - * @li @e BLDOPT_REMOVE_FAMILY_15_SUPPORT @n - * If the package contains support for family 15h processors, remove that support. - * - * @anchor BLDOPT_REMOVE_AM3_SOCKET_SUPPORT - * @li @e BLDOPT_REMOVE_AM3_SOCKET_SUPPORT @n - * This option removes the code which implements support for processors packaged for AM3 sockets. - * - * @anchor BLDOPT_REMOVE_ASB2_SOCKET_SUPPORT - * @li @e BLDOPT_REMOVE_ASB2_SOCKET_SUPPORT @n - * This option removes the code which implements support for processors packaged for ASB2 sockets. - * - * @anchor BLDOPT_REMOVE_C32_SOCKET_SUPPORT - * @li @e BLDOPT_REMOVE_C32_SOCKET_SUPPORT @n - * This option removes the code which implements support for processors packaged for C32 sockets. - * - * @anchor BLDOPT_REMOVE_FM1_SOCKET_SUPPORT - * @li @e BLDOPT_REMOVE_FM1_SOCKET_SUPPORT @n - * This option removes the code which implements support for processors packaged for FM1 sockets. - * - * @anchor BLDOPT_REMOVE_FP1_SOCKET_SUPPORT - * @li @e BLDOPT_REMOVE_FP1_SOCKET_SUPPORT @n - * This option removes the code which implements support for processors packaged for FP1 sockets. - * - * @anchor BLDOPT_REMOVE_FS1_SOCKET_SUPPORT - * @li @e BLDOPT_REMOVE_FS1_SOCKET_SUPPORT @n - * This option removes the code which implements support for processors packaged for FS1 sockets. - * - * @anchor BLDOPT_REMOVE_FT1_SOCKET_SUPPORT - * @li @e BLDOPT_REMOVE_FT1_SOCKET_SUPPORT @n - * This option removes the code which implements support for processors packaged for FT1 sockets. - * - * @anchor BLDOPT_REMOVE_G34_SOCKET_SUPPORT - * @li @e BLDOPT_REMOVE_G34_SOCKET_SUPPORT @n - * This option removes the code which implements support for processors packaged for G34 sockets. - * - * @anchor BLDOPT_REMOVE_S1G3_SOCKET_SUPPORT - * @li @e BLDOPT_REMOVE_S1G3_SOCKET_SUPPORT @n - * This option removes the code which implements support for processors packaged for S1G3 sockets. - * - * @anchor BLDOPT_REMOVE_S1G4_SOCKET_SUPPORT - * @li @e BLDOPT_REMOVE_S1G4_SOCKET_SUPPORT @n - * This option removes the code which implements support for processors packaged for S1G4 sockets. - */ - -/** - * @page examplecustomizations Customization Examples - * - * The Addendum \Options.c file for each platform contains the minimum required - * customizations for that platform. That is, it contains settings which would be needed - * to boot a SimNow! bsd for that platform. - * However, each individual product based on that platform will have customizations necessary for - * that hardware. Since the actual customizations needed vary so much, they are not included in - * the \Options.c. This section provides examples of useful customizations that you can use or - * modify to suit your needs. - * - * @par - * - * Source for the examples shown can be found at Addendum\\Examples. @n - * - * - @ref DeemphasisExamples "Deemphasis List Examples" - * - @ref FrequencyLimitExamples "Frequency Limit Examples" - * - @ref PerfPerWattHt "A performance-per-watt optimization Example" - * - * @anchor DeemphasisExamples - * @par Deemphasis List Examples - * - * These examples customize PLATFORM_CONFIGURATION.PlatformDeemphasisList. - * Source for the deemphasis list examples can be found in DeemphasisExamples.c. @n - * @dontinclude DeemphasisExamples.c - *
    - *
  • - * The following deemphasis list provides an example for a 2P MCM Max Performance configuration. - * High Speed HT frequencies are supported. There is only one non-coherent chain. Note the technique of - * putting specified link matches before all uses of match any. It often works well to specify the non-coherent links - * and use match any for the coherent links. - * @skip DinarDeemphasisList - * @until { - * The non-coherent chain can run up to 2600 MHz. The chain is located on Socket 0, package Link 2. - * @until { - * @line } - * @line { - * @line } - * The coherent links can run up to 3200 MHz. - * @until HT_FREQUENCY_MAX - * @line } - * end of list: - * @until } - * Make this list the build time customized deemphasis list. - * @line define - * - *
  • - * - * The following deemphasis list provides an example for a 4P MCM Max Performance configuration. - * This system has a backplane with connectors for CPU cards and an IO board. So trace lengths are long. - * There can be one to four IO Chains, depending on the IO board. - * @skipline DoubloonDeemphasisList - * @until DoubloonDeemphasisList - * - *
  • - * - * The following deemphasis list further illustrates complex coherent system deemphasis. This is the same - * Dinar system as in an earlier example, but this time all the coherent links are explicitly customized (as - * might be needed if each link has unique characterization). For this example, we skip the non-coherent chains. - * (A real system would have to include them, see example above.) - * @skip DinarPerLinkDeemphasisList - * @until { - * Provide deemphasis settings for the 16 bit, ganged, links, Socket 0 links 0, 1 and Socket 1 links 1 and 2. - * Provide entries to customize all HT3 frequencies at which the links may run. This example covers all HT3 speeds. - * @until { - * @until DcvLevelMinus6 - * @until DcvLevelMinus6 - * @until DcvLevelMinus6 - * @until DcvLevelMinus6 - * Link 3 on both sockets connects different internal die: sublink 0 connects the internal node zeroes, and - * sublink 1 connects the internal node ones. So the link is unganged and both sublinks must be specifically - * customized. - * @until { - * @until DcvLevelMinus6 - * @until DcvLevelMinus6 - * @until DcvLevelMinus6 - * @until DcvLevelMinus6 - * end of list: - * @until define - * - *
- * - * @anchor FrequencyLimitExamples - * @par Frequency Limit Examples - * - * These examples customize AMD_HT_INTERFACE.CpuToCpuPcbLimitsList and AMD_HT_INTERFACE.IoPcbLimitsList. - * Source for the frequency limit examples can be found in FrequencyLimitExamples.c. @n - * @dontinclude FrequencyLimitExamples.c - *
    - *
  • - * The following list provides an example for limiting all coherent links to non-extended frequencies, - * that is, to 2600 MHz or less. - * @skipline NonExtendedCpuToCpuLimitList - * @until { - * Provide the limit customization. Match links from any socket, any package link, to any socket, any package link. Width is not limited. - * @until HT_FREQUENCY_LIMIT_2600M - * End of list: - * @until ; - * Customize the build to use this cpu to cpu frequency limit. - * @until NonExtendedCpuToCpuLimitList - * @n
    • - *
  • - * The following list provides an example for limiting all coherent links to HT 1 frequencies, - * that is, to 1000 MHz or less. This is sometimes useful for test and debug. - * @skipline Ht1CpuToCpuLimitList - * @until Ht1CpuToCpuLimitList - * @n
    • - *
  • - * The following list provides an example for limiting all non-coherent links to 2400 MHz or less. - * The chain is matched by host processor Socket and package Link. The depth can be used to select a particular device - * to device link on the chain. In this example, the chain consists of a single cave device and depth can be set to match any. - * @skipline No2600MhzIoLimitList - * @until No2600MhzIoLimitList - * @n
    • - *
  • - * The following list provides an example for limiting all non-coherent links to the minimum HT 3 frequency, - * that is, to 1200 MHz or less. This can be useful for test and debug. - * @skipline MinHt3IoLimitList - * @until MinHt3IoLimitList - * @n
    • - * - *
- * - * @anchor PerfPerWattHt - * @par Performance-per-Watt Optimization Example - * - * This example customizes AMD_HT_INTERFACE.SkipRegangList. - * Source for the Performance-per-watt Optimization example can be found in PerfPerWatt.c. @n - * @dontinclude PerfPerWatt.c - * To implement a performance-per-watt optimization for MCM processors, use the skip regang structure shown. @n - * @skipline PerfPerWatt - * @until PerfPerWatt - * - */ diff --git a/src/vendorcode/amd/agesa/f12/Include/PlatformMemoryConfiguration.h b/src/vendorcode/amd/agesa/f12/Include/PlatformMemoryConfiguration.h deleted file mode 100644 index 04407652d0..0000000000 --- a/src/vendorcode/amd/agesa/f12/Include/PlatformMemoryConfiguration.h +++ /dev/null @@ -1,320 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * AMD Platform Specific Memory Configuration - * - * Contains Definitions and Macros for control of AGESA Memory code on a per platform basis - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: OPTION - * @e \$Revision: 47408 $ @e \$Date: 2011-02-19 00:56:31 +0800 (Sat, 19 Feb 2011) $ - * - */ -/***************************************************************************** - * - * Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - ****************************************************************************** - */ - -#ifndef _PLATFORM_MEMORY_CONFIGURATION_H_ -#define _PLATFORM_MEMORY_CONFIGURATION_H_ - -/*---------------------------------------------------------------------------------------- - * M I X E D (Definitions And Macros / Typedefs, Structures, Enums) - *---------------------------------------------------------------------------------------- - */ -#ifndef PSO_ENTRY - #define PSO_ENTRY UINT8 -#endif - -/*---------------------------------------------------------------------------------------- - * D E F I N I T I O N S A N D M A C R O S - *---------------------------------------------------------------------------------------- - */ -/*---------------------------------------------------------------------------------------- - * T Y P E D E F S, S T R U C T U R E S, E N U M S - *---------------------------------------------------------------------------------------- - */ -/*---------------------------------------------------------------------------------------- - * PLATFORM SPECIFIC MEMORY DEFINITIONS - *---------------------------------------------------------------------------------------- - */ -/// -/// Memory Speed and DIMM Population Masks -/// -///< DDR Speed Masks -///< Specifies the DDR Speed on a memory channel -/// -#define ANY_SPEED 0xFFFFFFFF -#define DDR400 ((UINT32) 1 << (DDR400_FREQUENCY / 66)) -#define DDR533 ((UINT32) 1 << (DDR533_FREQUENCY / 66)) -#define DDR667 ((UINT32) 1 << (DDR667_FREQUENCY / 66)) -#define DDR800 ((UINT32) 1 << (DDR800_FREQUENCY / 66)) -#define DDR1066 ((UINT32) 1 << (DDR1066_FREQUENCY / 66)) -#define DDR1333 ((UINT32) 1 << (DDR1333_FREQUENCY / 66)) -#define DDR1600 ((UINT32) 1 << (DDR1600_FREQUENCY / 66)) -#define DDR1866 ((UINT32) 1 << (DDR1866_FREQUENCY / 66)) -#define DDR2133 ((UINT32) 1 << (DDR2133_FREQUENCY / 66)) -#define DDR2400 ((UINT32) 1 << (DDR2400_FREQUENCY / 66)) -/// -///< DIMM POPULATION MASKS -///< Specifies the DIMM Population on a channel (can be added together to specify configuration). -///< ex. SR_DIMM0 + SR_DIMM1 : Single Rank Dimm in slot 0 AND Slot 1 -///< SR_DIMM0 + DR_DIMM0 + SR_DIMM1 +DR_DIMM1 : Single OR Dual rank in Slot 0 AND Single OR Dual rank in Slot 1 -/// -#define ANY_ 0xFF ///< Any dimm configuration the current channel -#define SR_DIMM0 0x0001 ///< Single rank dimm in slot 0 on the current channel -#define SR_DIMM1 0x0010 ///< Single rank dimm in slot 1 on the current channel -#define SR_DIMM2 0x0100 ///< Single rank dimm in slot 2 on the current channel -#define SR_DIMM3 0x1000 ///< Single rank dimm in slot 3 on the current channel -#define DR_DIMM0 0x0002 ///< Dual rank dimm in slot 0 on the current channel -#define DR_DIMM1 0x0020 ///< Dual rank dimm in slot 1 on the current channel -#define DR_DIMM2 0x0200 ///< Dual rank dimm in slot 2 on the current channel -#define DR_DIMM3 0x2000 ///< Dual rank dimm in slot 3 on the current channel -#define QR_DIMM0 0x0004 ///< Quad rank dimm in slot 0 on the current channel -#define QR_DIMM1 0x0040 ///< Quad rank dimm in slot 1 on the current channel -#define QR_DIMM2 0x0400 ///< Quad rank dimm in slot 2 on the current channel -#define QR_DIMM3 0x4000 ///< Quad rank dimm in slot 3 on the current channel -#define ANY_DIMM0 0x000F ///< Any Dimm combination in slot 0 on the current channel -#define ANY_DIMM1 0x00F0 ///< Any Dimm combination in slot 1 on the current channel -#define ANY_DIMM2 0x0F00 ///< Any Dimm combination in slot 2 on the current channel -#define ANY_DIMM3 0xF000 ///< Any Dimm combination in slot 3 on the current channel -/// -///< Number of Dimms on the current channel -///< This is a mask used to indicate the number of dimms in a channel -///< They can be added to indicate multiple conditions (i.e 1 OR 2 Dimms) -/// -#define ANY_NUM 0xFF ///< Any number of Dimms -#define NO_DIMM 0x00 ///< No Dimms present -#define ONE_DIMM 0x01 ///< One dimm Poulated on the current channel -#define TWO_DIMM 0x02 ///< Two dimms Poulated on the current channel -#define THREE_DIMM 0x04 ///< Three dimms Poulated on the current channel -#define FOUR_DIMM 0x08 ///< Four dimms Poulated on the current channel - -/*---------------------------------------------------------------------------------------- - * - * Platform Specific Override Definitions for Socket, Channel and Dimm - * This indicates where a platform override will be applied. - * - *---------------------------------------------------------------------------------------- - */ -/// -///< SOCKET MASKS -///< Indicates associated processor sockets to apply override settings -/// -#define ANY_SOCKET 0xFF ///< Apply to all sockets -#define SOCKET0 0x01 ///< Apply to socket 0 -#define SOCKET1 0x02 ///< Apply to socket 1 -#define SOCKET2 0x04 ///< Apply to socket 2 -#define SOCKET3 0x08 ///< Apply to socket 3 -#define SOCKET4 0x10 ///< Apply to socket 4 -#define SOCKET5 0x20 ///< Apply to socket 5 -#define SOCKET6 0x40 ///< Apply to socket 6 -#define SOCKET7 0x80 ///< Apply to socket 7 -/// -///< CHANNEL MASKS -///< Indicates Memory channels where override should be applied -/// -#define ANY_CHANNEL 0xFF ///< Apply to all Memory channels -#define CHANNEL_A 0x01 ///< Apply to Channel A -#define CHANNEL_B 0x02 ///< Apply to Channel B -#define CHANNEL_C 0x04 ///< Apply to Channel C -#define CHANNEL_D 0x08 ///< Apply to Channel D -/// -/// DIMM MASKS -/// Indicates Dimm Slots where override should be applied -/// -#define ALL_DIMMS 0xFF ///< Apply to all dimm slots -#define DIMM0 0x01 ///< Apply to Dimm Slot 0 -#define DIMM1 0x02 ///< Apply to Dimm Slot 1 -#define DIMM2 0x04 ///< Apply to Dimm Slot 2 -#define DIMM3 0x08 ///< Apply to Dimm Slot 3 -/// -/// REGISTER ACCESS MASKS -/// Not supported as an at this time -/// -#define ACCESS_NB0 0x0 -#define ACCESS_NB1 0x1 -#define ACCESS_NB2 0x2 -#define ACCESS_NB3 0x3 -#define ACCESS_NB4 0x4 -#define ACCESS_PHY 0x5 -#define ACCESS_DCT_XT 0x6 - -/*---------------------------------------------------------------------------------------- - * - * Platform Specific Overriding Table Definitions - * - *---------------------------------------------------------------------------------------- - */ - -#define PSO_END 0 ///< Table End -#define PSO_CKE_TRI 1 ///< CKE Tristate Map -#define PSO_ODT_TRI 2 ///< ODT Tristate Map -#define PSO_CS_TRI 3 ///< CS Tristate Map -#define PSO_MAX_DIMMS 4 ///< Max Dimms per channel -#define PSO_CLK_SPEED 5 ///< Clock Speed -#define PSO_DIMM_TYPE 6 ///< Dimm Type -#define PSO_MEMCLK_DIS 7 ///< MEMCLK Disable Map -#define PSO_MAX_CHNLS 8 ///< Max Channels per Socket -#define PSO_BUS_SPEED 9 ///< Max Memory Bus Speed -#define PSO_MAX_CHIPSELS 10 ///< Max Chipsel per Channel -#define PSO_MEM_TECH 11 ///< Channel Memory Type -#define PSO_WL_SEED 12 ///< DDR3 Write Levelization Seed delay -#define PSO_RXEN_SEED 13 ///< Hardwared based RxEn seed -#define PSO_NO_LRDIMM_CS67_ROUTING 14 ///< CS6 and CS7 are not Routed to all Memoy slots on a channel for LRDIMMs -#define PSO_SOLDERED_DOWN_SODIMM_TYPE 15 ///< Soldered down SODIMM type -#define PSO_LVDIMM_VOLT1_5_SUPPORT 16 ///< Force LvDimm voltage to 1.5V - -/*---------------------------------- - * CONDITIONAL PSO SPECIFIC ENTRIES - *---------------------------------*/ -// Condition Types -#define CONDITIONAL_PSO_MIN 100 ///< Start of Conditional Entry Types -#define PSO_CONDITION_AND 100 ///< And Block - Start of Conditional block -#define PSO_CONDITION_LOC 101 ///< Location - Specify Socket, Channel, Dimms to be affected -#define PSO_CONDITION_SPD 102 ///< SPD - Specify a specific SPD value on a Dimm on the channel -#define PSO_CONDITION_REG 103 // Reserved -#define PSO_CONDITION_MAX 103 ///< End Of Condition Entry Types -// Action Types -#define PSO_ACTION_MIN 120 ///< Start of Action Entry Types -#define PSO_ACTION_ODT 120 ///< ODT values to override -#define PSO_ACTION_ADDRTMG 121 ///< Address/Timing values to override -#define PSO_ACTION_ODCCONTROL 122 ///< ODC Control values to override -#define PSO_ACTION_SLEWRATE 123 ///< Slew Rate value to override -#define PSO_ACTION_REG 124 // Reserved -#define PSO_ACTION_SPEEDLIMIT 125 ///< Memory Bus speed Limit based on configuration -#define PSO_ACTION_MAX 125 ///< End of Action Entry Types -#define CONDITIONAL_PSO_MAX 139 ///< End of Conditional Entry Types - -/*---------------------------------------------------------------------------------------- - * CONDITIONAL OVERRIDE TABLE MACROS - *---------------------------------------------------------------------------------------- - */ -#define MEMCLK_DIS_MAP(SocketID, ChannelID, Bit0Map, Bit1Map, Bit2Map, Bit3Map, Bit4Map, Bit5Map, Bit6Map, Bit7Map) \ - PSO_MEMCLK_DIS, 10, SocketID, ChannelID, Bit0Map, Bit1Map, Bit2Map, Bit3Map, Bit4Map, Bit5Map, Bit6Map, Bit7Map - -#define CKE_TRI_MAP(SocketID, ChannelID, Bit0Map, Bit1Map) \ - PSO_CKE_TRI, 4, SocketID, ChannelID, Bit0Map, Bit1Map - -#define ODT_TRI_MAP(SocketID, ChannelID, Bit0Map, Bit1Map, Bit2Map, Bit3Map) \ - PSO_ODT_TRI, 6, SocketID, ChannelID, Bit0Map, Bit1Map, Bit2Map, Bit3Map - -#define CS_TRI_MAP(SocketID, ChannelID, Bit0Map, Bit1Map, Bit2Map, Bit3Map, Bit4Map, Bit5Map, Bit6Map, Bit7Map) \ - PSO_CS_TRI, 10, SocketID, ChannelID, Bit0Map, Bit1Map, Bit2Map, Bit3Map, Bit4Map, Bit5Map, Bit6Map, Bit7Map - -#define NUMBER_OF_DIMMS_SUPPORTED(SocketID, ChannelID, NumberOfDimmSlotsPerChannel) \ - PSO_MAX_DIMMS, 3, SocketID, ChannelID, NumberOfDimmSlotsPerChannel - -#define NUMBER_OF_CHIP_SELECTS_SUPPORTED(SocketID, ChannelID, NumberOfChipSelectsPerChannel) \ - PSO_MAX_CHIPSELS, 3, SocketID, ChannelID, NumberOfChipSelectsPerChannel - -#define NUMBER_OF_CHANNELS_SUPPORTED(SocketID, NumberOfChannelsPerSocket) \ - PSO_MAX_CHNLS, 3, SocketID, ANY_CHANNEL, NumberOfChannelsPerSocket - -#define OVERRIDE_DDR_BUS_SPEED(SocketID, ChannelID, TimingMode, BusSpeed) \ - PSO_BUS_SPEED, 10, SocketID, ChannelID, TimingMode, (TimingMode >> 8), (TimingMode >> 16), (TimingMode >> 24), \ - BusSpeed, (BusSpeed >> 8), (BusSpeed >> 16), (BusSpeed >> 24) - -#define DRAM_TECHNOLOGY(SocketID, MemTechType) \ - PSO_MEM_TECH, 6, SocketID, ANY_CHANNEL, MemTechType, (MemTechType >> 8), (MemTechType >> 16), (MemTechType >> 24) - -#define WRITE_LEVELING_SEED(SocketID, ChannelID, Byte0Seed, Byte1Seed, Byte2Seed, Byte3Seed, Byte4Seed, Byte5Seed, \ - Byte6Seed, Byte7Seed, ByteEccSeed) \ - PSO_WL_SEED, 11, SocketID, ChannelID, Byte0Seed, Byte1Seed, Byte2Seed, Byte3Seed, Byte4Seed, Byte5Seed, \ - Byte6Seed, Byte7Seed, ByteEccSeed - -#define HW_RXEN_SEED(SocketID, ChannelID, Byte0Seed, Byte1Seed, Byte2Seed, Byte3Seed, Byte4Seed, Byte5Seed, \ - Byte6Seed, Byte7Seed, ByteEccSeed) \ - PSO_RXEN_SEED, 20, SocketID, ChannelID, Byte0Seed, (Byte0Seed >> 8), Byte1Seed, (Byte1Seed >> 8), Byte2Seed, (Byte2Seed >> 8), \ - Byte3Seed, (Byte3Seed >> 8), Byte4Seed, (Byte4Seed >> 8), Byte5Seed, (Byte5Seed >> 8), Byte6Seed, (Byte6Seed >> 8), \ - Byte7Seed, (Byte7Seed >> 8), ByteEccSeed, (ByteEccSeed >> 8) - -#define NO_LRDIMM_CS67_ROUTING(SocketID, ChannelID) \ - PSO_NO_LRDIMM_CS67_ROUTING, 3, SocketID, ChannelID, TRUE - -#define SOLDERED_DOWN_SODIMM_TYPE(SocketID, ChannelID) \ - PSO_SOLDERED_DOWN_SODIMM_TYPE, 3, SocketID, ChannelID, TRUE - -#define LVDIMM_FORCE_VOLT1_5_FOR_D0 \ - PSO_LVDIMM_VOLT1_5_SUPPORT, 3, ANY_SOCKET, ANY_CHANNEL, TRUE - -/*---------------------------------------------------------------------------------------- - * CONDITIONAL OVERRIDE TABLE MACROS - *---------------------------------------------------------------------------------------- - */ -#define CONDITION_AND \ - PSO_CONDITION_AND, 0 - -#define COND_LOC(SocketMsk, ChannelMsk, DimmMsk) \ - PSO_CONDITION_LOC, 3, SocketMsk, ChannelMsk, DimmMsk - -#define COND_SPD(Byte, Mask, Value) \ - PSO_CONDITION_SPD, 3, Byte, Mask, Value - -#define COND_REG(Access, Offset, Mask, Value) \ - PSO_CONDITION_REG, 11, Access, (Offset & 0x0FF), (Offset >> 8), \ - ((Mask) & 0x0FF), (((Mask) >> 8) & 0x0FF), (((Mask) >> 16) & 0x0FF), (((Mask) >> 24) & 0x0FF), \ - ((Value) & 0x0FF), (((Value) >> 8) & 0x0FF), (((Value) >> 16) & 0x0FF), (((Value) >> 24) & 0x0FF) - -#define ACTION_ODT(Frequency, Dimms, QrDimms, DramOdt, QrDramOdt, DramDynOdt) \ - PSO_ACTION_ODT, 9, \ - ((Frequency) & 0x0FF), (((Frequency) >> 8)& 0x0FF), (((Frequency) >> 16)& 0x0FF), ((Frequency >> 24)& 0x0FF), \ - Dimms, QrDimms, DramOdt, QrDramOdt, DramDynOdt - -#define ACTION_ADDRTMG(Frequency, DimmConfig, AddrTmg) \ - PSO_ACTION_ADDRTMG, 10, \ - ((Frequency) & 0x0FF), (((Frequency) >> 8)& 0x0FF), (((Frequency) >> 16)& 0x0FF), (((Frequency) >> 24)& 0x0FF), \ - ((DimmConfig) & 0x0FF), (((DimmConfig) >> 8) & 0x0FF), \ - (AddrTmg & 0x0FF), ((AddrTmg >> 8)& 0x0FF), ((AddrTmg >> 16)& 0x0FF), ((AddrTmg >> 24)& 0x0FF) - -#define ACTION_ODCCTRL(Frequency, DimmConfig, OdcCtrl) \ - PSO_ACTION_ODCCONTROL, 10, \ - ((Frequency) & 0x0FF), (((Frequency) >> 8)& 0x0FF), (((Frequency) >> 16)& 0x0FF), (((Frequency) >> 24)& 0x0FF), \ - ((DimmConfig) & 0x0FF), (((DimmConfig) >> 8) & 0x0FF), \ - (OdcCtrl & 0x0FF), ((OdcCtrl >> 8)& 0x0FF), ((OdcCtrl >> 16)& 0x0FF), ((OdcCtrl >> 24)& 0x0FF) - -#define ACTION_SLEWRATE(Frequency, DimmConfig, SlewRate) \ - PSO_ACTION_SLEWRATE, 10, \ - ((Frequency) & 0x0FF), (((Frequency) >> 8)& 0x0FF), (((Frequency) >> 16)& 0x0FF), (((Frequency) >> 24)& 0x0FF), \ - ((DimmConfig) & 0x0FF), (((DimmConfig) >> 8) & 0x0FF), \ - (SlewRate & 0x0FF), ((SlewRate >> 8)& 0x0FF), ((SlewRate >> 16)& 0x0FF), ((SlewRate >> 24)& 0x0FF) - -#define ACTION_SPEEDLIMIT(DimmConfig, Dimms, SpeedLimit15, SpeedLimit135, SpeedLimit125) \ - PSO_ACTION_SPEEDLIMIT, 9, \ - ((DimmConfig) & 0x0FF), (((DimmConfig) >> 8) & 0x0FF), Dimms, \ - (SpeedLimit15 & 0x0FF), ((SpeedLimit15 >> 8)& 0x0FF), \ - (SpeedLimit135 & 0x0FF), ((SpeedLimit135 >> 8)& 0x0FF), \ - (SpeedLimit125 & 0x0FF), ((SpeedLimit125 >> 8)& 0x0FF) - -/*---------------------------------------------------------------------------------------- - * END OF CONDITIONAL OVERRIDE TABLE MACROS - *---------------------------------------------------------------------------------------- - */ - -#endif // _PLATFORM_MEMORY_CONFIGURATION_H_ diff --git a/src/vendorcode/amd/agesa/f12/Include/Topology.h b/src/vendorcode/amd/agesa/f12/Include/Topology.h deleted file mode 100644 index 340c5c3139..0000000000 --- a/src/vendorcode/amd/agesa/f12/Include/Topology.h +++ /dev/null @@ -1,162 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * Topology interface definitions. - * - * Contains AMD AGESA internal interface for topology related data which - * is consumed by code other than HyperTransport init (and produced by - * HyperTransport init.) - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: Core - * @e \$Revision: 63425 $ @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ - */ -/***************************************************************************** - * - * Copyright (c) 2008 - 2012, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ***************************************************************************/ - -#ifndef _TOPOLOGY_H_ -#define _TOPOLOGY_H_ - -// Defines for limiting data structure maximum allocation and limit checking. -#define MAX_NODES 8 -#define MAX_SOCKETS MAX_NODES -#define MAX_DIES 2 - -// Defines useful with package link -#define HT_LIST_MATCH_INTERNAL_LINK_0 0xFA -#define HT_LIST_MATCH_INTERNAL_LINK_1 0xFB -#define HT_LIST_MATCH_INTERNAL_LINK_2 0xFC - -/** - * Hop Count Table. - * This is a heap data structure. The Hops array is filled as a size x size matrix. - * The unused space, if any, is all at the end. - */ -typedef struct { - UINT8 Size; ///< The row and column size of actual hop count data */ - UINT8 Hops[MAX_NODES * MAX_NODES]; ///< Room for a dynamic two dimensional array of [size][size] */ -} HOP_COUNT_TABLE; - -/** - * Socket and Module to Node Map Item. - * Provide the Node Id and core id range for each module in each processor. - */ -typedef struct { - UINT8 Node; ///< The module's Node id. - UINT8 LowCore; ///< The lowest processor core id for this module. - UINT8 HighCore; ///< The highest processor core id for this module. - UINT8 EnabledComputeUnits; ///< The value of Enabled for this processor module. - UINT8 DualCoreComputeUnits; ///< The value of DualCore for this processor module. -} SOCKET_DIE_TO_NODE_ITEM; - -/** - * Socket and Module to Node Map. - * This type is a pointer to the actual map, it can be used for a struct item or - * for typecasting a heap buffer pointer. - */ -typedef SOCKET_DIE_TO_NODE_ITEM (*SOCKET_DIE_TO_NODE_MAP)[MAX_SOCKETS][MAX_DIES]; - -/** - * Node id to Socket Die Map Item. - */ -typedef struct { - UINT8 Socket; ///< socket of the processor containing the Node. - UINT8 Die; ///< the module in the processor which is Node. -} NODE_TO_SOCKET_DIE_ITEM; - -/** - * Node id to Socket Die Map. - */ -typedef NODE_TO_SOCKET_DIE_ITEM (*NODE_TO_SOCKET_DIE_MAP)[MAX_NODES]; - -/** - * Provide AP core with socket and node context at start up. - * This information is posted to the AP cores using a register as a mailbox. - */ -typedef struct { - UINT32 Node:4; ///< The node id of Core's node. - UINT32 Socket:4; ///< The socket of this Core's node. - UINT32 Module:2; ///< The internal module number for Core's node. - UINT32 ModuleType:2; ///< Single Module = 0, Multi-module = 1. - UINT32 :20; ///< Reserved -} AP_MAIL_INFO_FIELDS; - -/** - * AP info fields can be written and read to a register. - */ -typedef union { - UINT32 Info; ///< Just a number for register access, or opaque passing. - AP_MAIL_INFO_FIELDS Fields; ///< access to the info fields. -} AP_MAIL_INFO; - -/** - * Provide AP core with system degree and system core number at start up. - * This information is posted to the AP cores using a register as a mailbox. - */ -typedef struct { - UINT32 SystemDegree:3; ///< The number of connected links - UINT32 :3; ///< Reserved - UINT32 HeapIndex:6; ///< The zero-based system core number - UINT32 :20; ///< Reserved -} AP_MAIL_EXT_INFO_FIELDS; - -/** - * AP info fields can be written and read to a register. - */ -typedef union { - UINT32 Info; ///< Just a number for register access, or opaque passing. - AP_MAIL_EXT_INFO_FIELDS Fields; ///< access to the info fields. -} AP_MAIL_EXT_INFO; - -/** - * AP Info mailbox set. - */ -typedef struct { - AP_MAIL_INFO ApMailInfo; ///< The AP mail info - AP_MAIL_EXT_INFO ApMailExtInfo; ///< The extended AP mail info -} AP_MAILBOXES; - -/** - * Provide a northbridge to package mapping for link assignments. - * - */ -typedef struct { - UINT8 Link; ///< The Node's link - UINT8 Module; ///< The internal module position of Node - UINT8 PackageLink; ///< The corresponding package link -} PACKAGE_HTLINK_MAP_ITEM; - -/** - * A Processor's complete set of link assignments - */ -typedef PACKAGE_HTLINK_MAP_ITEM (*PACKAGE_HTLINK_MAP)[]; - -#endif // _TOPOLOGY_H_ diff --git a/src/vendorcode/amd/agesa/f12/Legacy/Proc/Dispatcher.c b/src/vendorcode/amd/agesa/f12/Legacy/Proc/Dispatcher.c deleted file mode 100644 index b507570e48..0000000000 --- a/src/vendorcode/amd/agesa/f12/Legacy/Proc/Dispatcher.c +++ /dev/null @@ -1,135 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * AMD binary block interface - * - * Contains the block entry function dispatcher - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: Legacy - * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $ - * - */ -/***************************************************************************** - * - * Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * *************************************************************************** - */ - -/*---------------------------------------------------------------------------------------- - * M O D U L E S U S E D - *---------------------------------------------------------------------------------------- - */ -#include "AGESA.h" -#include "amdlib.h" -#include "Dispatcher.h" -#include "Options.h" -#include "Filecode.h" -CODE_GROUP (G1_PEICC) -RDATA_GROUP (G1_PEICC) - -#define FILECODE LEGACY_PROC_DISPATCHER_FILECODE - -/*---------------------------------------------------------------------------------------- - * D E F I N I T I O N S A N D M A C R O S - *---------------------------------------------------------------------------------------- - */ -extern CONST DISPATCH_TABLE DispatchTable[]; -extern AMD_MODULE_HEADER mCpuModuleID; - -/*---------------------------------------------------------------------------------------*/ -/** - * The Dispatcher is the entry point into the AGESA software. It takes a function - * number as entry parameter in order to invoke the published function - * - * @param[in,out] ConfigPtr - * - * @return AGESA Status. - * - */ -AGESA_STATUS -CALLCONV -AmdAgesaDispatcher ( - IN OUT VOID *ConfigPtr - ) -{ - AGESA_STATUS Status; - MODULE_ENTRY ModuleEntry; - DISPATCH_TABLE *Entry; - - Status = AGESA_UNSUPPORTED; - ModuleEntry = NULL; - - Entry = (DISPATCH_TABLE *) DispatchTable; - while (Entry->FunctionId != 0) { - if ((((AMD_CONFIG_PARAMS *) ConfigPtr)->Func) == Entry->FunctionId) { - Status = Entry->EntryPoint (ConfigPtr); - break; - } - Entry++; - } - - // 2. Try next dispatcher if possible, and we have not already got status back - if ((mCpuModuleID.NextBlock != NULL) && (Status == AGESA_UNSUPPORTED)) { - ModuleEntry = (MODULE_ENTRY) (intptr_t) mCpuModuleID.NextBlock->ModuleDispatcher; - if (ModuleEntry != NULL) { - Status = (*ModuleEntry) (ConfigPtr); - } - } - - return (Status); -} - -/*---------------------------------------------------------------------------------------*/ -/** - * The host environment interface of callout. - * - * @param[in] Func - * @param[in] Data - * @param[in,out] ConfigPtr - * - * @return The AGESA Status returned from the callout. - * - */ -AGESA_STATUS -CALLCONV -AmdAgesaCallout ( - IN UINT32 Func, - IN UINTN Data, - IN OUT VOID *ConfigPtr - ) -{ - UINT32 Result; - Result = AGESA_UNSUPPORTED; - if (((AMD_CONFIG_PARAMS *) ConfigPtr)->CalloutPtr == NULL) { - return Result; - } - - Result = (((AMD_CONFIG_PARAMS *) ConfigPtr)->CalloutPtr) (Func, Data, ConfigPtr); - return (Result); -} diff --git a/src/vendorcode/amd/agesa/f12/Legacy/Proc/Makefile.inc b/src/vendorcode/amd/agesa/f12/Legacy/Proc/Makefile.inc deleted file mode 100644 index 80cdf12a7d..0000000000 --- a/src/vendorcode/amd/agesa/f12/Legacy/Proc/Makefile.inc +++ /dev/null @@ -1,3 +0,0 @@ -libagesa-y += Dispatcher.c -libagesa-y += agesaCallouts.c -libagesa-y += hobTransfer.c diff --git a/src/vendorcode/amd/agesa/f12/Legacy/Proc/agesaCallouts.c b/src/vendorcode/amd/agesa/f12/Legacy/Proc/agesaCallouts.c deleted file mode 100644 index 2241ed77c5..0000000000 --- a/src/vendorcode/amd/agesa/f12/Legacy/Proc/agesaCallouts.c +++ /dev/null @@ -1,420 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * AMD CPU AGESA Callout Functions - * - * Contains code to set / get useful platform information. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: Common - * @e \$Revision: 49633 $ @e \$Date: 2011-03-26 06:52:29 +0800 (Sat, 26 Mar 2011) $ - * - */ -/***************************************************************************** - * AMD Generic Encapsulated Software Architecture - * - * Description: agesaCallouts.c - AGESA Call out functions - * - ****************************************************************************** - * - * Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - ****************************************************************************** - */ - -/*---------------------------------------------------------------------------------------- - * M O D U L E S U S E D - *---------------------------------------------------------------------------------------- - */ -#include "AGESA.h" -#include "cpuRegisters.h" -#include "Dispatcher.h" -#include "cpuServices.h" -#include "Ids.h" -#include "Filecode.h" - -#define FILECODE LEGACY_PROC_AGESACALLOUTS_FILECODE -/*---------------------------------------------------------------------------------------- - * D E F I N I T I O N S A N D M A C R O S - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------- - * T Y P E D E F S A N D S T R U C T U R E S - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------- - * P R O T O T Y P E S O F L O C A L F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------- - * E X P O R T E D F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ - - -/*---------------------------------------------------------------------------------------- - * E X P O R T E D F U N C T I O N S - (AGESA ONLY) - *---------------------------------------------------------------------------------------- - */ - - -/*---------------------------------------------------------------------------------------*/ -/** - * - * Call the host environment interface to do the warm or cold reset. - * - * @param[in] ResetType Warm or Cold Reset is requested - * @param[in,out] StdHeader Config header - * - */ -VOID -AgesaDoReset ( - IN UINTN ResetType, - IN OUT AMD_CONFIG_PARAMS *StdHeader - ) -{ - AGESA_STATUS Status; - WARM_RESET_REQUEST Request; - - // Clear warm request bit and set state bits to the current post stage - GetWarmResetFlag (StdHeader, &Request); - Request.RequestBit = FALSE; - Request.StateBits = Request.PostStage; - SetWarmResetFlag (StdHeader, &Request); - - Status = AmdAgesaCallout (AGESA_DO_RESET, (UINT32)ResetType, (VOID *) StdHeader); -} - -/*---------------------------------------------------------------------------------------*/ -/** - * - * Call the host environment interface to allocate buffer in main system memory. - * - * @param[in] FcnData - * @param[in,out] AllocParams Heap manager parameters - * - * @return The AGESA Status returned from the callout. - * - */ -AGESA_STATUS -AgesaAllocateBuffer ( - IN UINTN FcnData, - IN OUT AGESA_BUFFER_PARAMS *AllocParams - ) -{ - AGESA_STATUS Status; - - Status = AmdAgesaCallout (AGESA_ALLOCATE_BUFFER, (UINT32)FcnData, (VOID *) AllocParams); - - return Status; -} - - -/*---------------------------------------------------------------------------------------*/ -/** - * Call the host environment interface to deallocate buffer in main system memory. - * - * @param[in] FcnData - * @param[in,out] DeallocParams Heap Manager parameters - * - * @return The AGESA Status returned from the callout. - */ -AGESA_STATUS -AgesaDeallocateBuffer ( - IN UINTN FcnData, - IN OUT AGESA_BUFFER_PARAMS *DeallocParams - ) -{ - AGESA_STATUS Status; - - Status = AmdAgesaCallout (AGESA_DEALLOCATE_BUFFER, (UINT32)FcnData, (VOID *) DeallocParams); - - return Status; -} - - -/*---------------------------------------------------------------------------------------*/ -/** - * - * Call the host environment interface to Locate buffer Pointer in main system memory - * - * @param[in] FcnData - * @param[in,out] LocateParams Heap manager parameters - * - * @return The AGESA Status returned from the callout. - * - */ -AGESA_STATUS -AgesaLocateBuffer ( - IN UINTN FcnData, - IN OUT AGESA_BUFFER_PARAMS *LocateParams - ) -{ - AGESA_STATUS Status; - - Status = AmdAgesaCallout (AGESA_LOCATE_BUFFER, (UINT32)FcnData, (VOID *) LocateParams); - - return Status; -} - - -/*---------------------------------------------------------------------------------------*/ -/** - * Call the host environment interface to launch APs - * - * @param[in] ApicIdOfCore - * @param[in,out] LaunchApParams - * - * @return The AGESA Status returned from the callout. - * - */ -AGESA_STATUS -AgesaRunFcnOnAp ( - IN UINTN ApicIdOfCore, - IN AP_EXE_PARAMS *LaunchApParams - ) -{ - AGESA_STATUS Status; - - Status = AmdAgesaCallout (AGESA_RUNFUNC_ONAP, (UINT32)ApicIdOfCore, (VOID *) LaunchApParams); - - return Status; -} - - -/*---------------------------------------------------------------------------------------*/ -/** - * Call the host environment interface to read an SPD's content. - * - * @param[in] FcnData - * @param[in,out] ReadSpd - * - * @return The AGESA Status returned from the callout. - * - */ -AGESA_STATUS -AgesaReadSpd ( - IN UINTN FcnData, - IN OUT AGESA_READ_SPD_PARAMS *ReadSpd - ) -{ - AGESA_STATUS Status; - - Status = AmdAgesaCallout (AGESA_READ_SPD, (UINT32)FcnData, ReadSpd); - - return Status; -} - - -/*---------------------------------------------------------------------------------------*/ -/** - * Call the host environment interface to read an SPD's content. - * - * @param[in] FcnData - * @param[in,out] ReadSpd - * - * @return The AGESA Status returned from the callout. - * - */ -AGESA_STATUS -AgesaReadSpdRecovery ( - IN UINTN FcnData, - IN OUT AGESA_READ_SPD_PARAMS *ReadSpd - ) -{ - AGESA_STATUS Status; - - Status = AmdAgesaCallout (AGESA_READ_SPD_RECOVERY, (UINT32)FcnData, ReadSpd); - - return Status; -} - - -/*---------------------------------------------------------------------------------------*/ -/** - * Call the host environment interface to provide a user hook opportunity. - * - * @param[in] FcnData - * @param[in,out] MemData - * - * @return The AGESA Status returned from the callout. - * - */ -AGESA_STATUS -AgesaHookBeforeDramInitRecovery ( - IN UINTN FcnData, - IN OUT MEM_DATA_STRUCT *MemData - ) -{ - AGESA_STATUS Status; - - Status = AmdAgesaCallout (AGESA_HOOKBEFORE_DRAM_INIT_RECOVERY, (UINT32)FcnData, MemData); - - return Status; -} - - -/*---------------------------------------------------------------------------------------*/ -/** - * Call the host environment interface to provide a user hook opportunity. - * - * @param[in] SocketIdModuleId - (SocketID << 8) | ModuleId - * @param[in,out] MemData - * - * @return The AGESA Status returned from the callout. - * - */ -AGESA_STATUS -AgesaHookBeforeDramInit ( - IN UINTN SocketIdModuleId, - IN OUT MEM_DATA_STRUCT *MemData - ) -{ - AGESA_STATUS Status; - - Status = AmdAgesaCallout (AGESA_HOOKBEFORE_DRAM_INIT, (UINT32)SocketIdModuleId, MemData); - - return Status; -} - -/*---------------------------------------------------------------------------------------*/ -/** - * Call the host environment interface to provide a user hook opportunity. - * - * @param[in] SocketIdModuleId - (SocketID << 8) | ModuleId - * @param[in,out] MemData - * - * @return The AGESA Status returned from the callout. - * - */ -AGESA_STATUS -AgesaHookBeforeDQSTraining ( - IN UINTN SocketIdModuleId, - IN OUT MEM_DATA_STRUCT *MemData - ) -{ - AGESA_STATUS Status; - - Status = AmdAgesaCallout (AGESA_HOOKBEFORE_DQS_TRAINING, (UINT32)SocketIdModuleId, MemData); - - return Status; -} - -/*---------------------------------------------------------------------------------------*/ -/** - * Call the host environment interface to provide a user hook opportunity. - * - * @param[in] FcnData - * @param[in,out] MemData - * - * @return The AGESA Status returned from the callout. - * - */ -AGESA_STATUS -AgesaHookBeforeExitSelfRefresh ( - IN UINTN FcnData, - IN OUT MEM_DATA_STRUCT *MemData - ) -{ - AGESA_STATUS Status; - - Status = AmdAgesaCallout (AGESA_HOOKBEFORE_EXIT_SELF_REF, (UINT32)FcnData, MemData); - - return Status; -} - -/*---------------------------------------------------------------------------------------*/ -/** - * Call the host environment interface to provide a user hook opportunity. - * - * @param[in] Data - * @param[in,out] IdsCalloutData - * - * @return The AGESA Status returned from the callout. - * - */ - -/* -AGESA_STATUS -AgesaGetIdsData ( - IN UINTN Data, - IN OUT IDS_CALLOUT_STRUCT *IdsCalloutData - ) -{ - AGESA_STATUS Status; - - Status = AmdAgesaCallout (AGESA_GET_IDS_INIT_DATA, (UINT32)Data, IdsCalloutData); - - return Status; -} -*/ - -/*----------------------------------------------------------------------------------------*/ -/** - * PCIE slot reset control - * - * - * - * @param[in] FcnData Function data - * @param[in] ResetInfo Reset information - * @retval Status Agesa status - */ - -AGESA_STATUS -AgesaPcieSlotResetControl ( - IN UINTN FcnData, - IN PCIe_SLOT_RESET_INFO *ResetInfo - ) -{ - AGESA_STATUS Status; - Status = AmdAgesaCallout (AGESA_GNB_PCIE_SLOT_RESET, (UINT32) FcnData, ResetInfo); - return Status; -} - - -/*----------------------------------------------------------------------------------------*/ -/** - * OEM callout function for FCH data override - * - * - * @param[in] FchData FCH data pointer - * @retval Status This feature is not supported - */ - -AGESA_STATUS -AgesaFchOemCallout ( - IN VOID *FchData - ) -{ - AGESA_STATUS Status; - Status = AmdAgesaCallout (AGESA_FCH_OEM_CALLOUT, (UINT32) 0, FchData); - return Status; -} - diff --git a/src/vendorcode/amd/agesa/f12/Legacy/Proc/hobTransfer.c b/src/vendorcode/amd/agesa/f12/Legacy/Proc/hobTransfer.c deleted file mode 100644 index eac7c2a723..0000000000 --- a/src/vendorcode/amd/agesa/f12/Legacy/Proc/hobTransfer.c +++ /dev/null @@ -1,392 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * AMD Hob Transfer functions. - * - * Contains code that copy Heap to temp memory or main memory. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: CPU - * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $ - * - */ -/* - ****************************************************************************** - * - * Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - ****************************************************************************** - */ - -/*---------------------------------------------------------------------------------------- - * M O D U L E S U S E D - *---------------------------------------------------------------------------------------- - */ - -#include "AGESA.h" -#include "amdlib.h" -#include "Ids.h" -#include "cpuRegisters.h" -#include "GeneralServices.h" -#include "cpuServices.h" -#include "cpuCacheInit.h" -#include "cpuFamilyTranslation.h" -#include "heapManager.h" -#include "cpuLateInit.h" -#include "Filecode.h" -CODE_GROUP (G1_PEICC) -RDATA_GROUP (G1_PEICC) - -#define FILECODE LEGACY_PROC_HOBTRANSFER_FILECODE -/*---------------------------------------------------------------------------------------- - * D E F I N I T I O N S A N D M A C R O S - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------- - * T Y P E D E F S A N D S T R U C T U R E S - *---------------------------------------------------------------------------------------- - */ - - -/*---------------------------------------------------------------------------------------- - * P R O T O T Y P E S O F L O C A L F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------- - * P U B L I C F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------- - * E X P O R T E D F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ -extern BUILD_OPT_CFG UserOptions; - -/* -----------------------------------------------------------------------------*/ -/** - * - * CopyHeapToTempRamAtPost - * - * This function copies BSP heap content to RAM - * - * @param[in,out] StdHeader - Pointer to AMD_CONFIG_PARAMS struct. - * - * @retval AGESA_STATUS - * - */ -AGESA_STATUS -CopyHeapToTempRamAtPost ( - IN OUT AMD_CONFIG_PARAMS *StdHeader - ) -{ - UINT8 *BaseAddressInCache; - UINT8 *BaseAddressInTempMem; - UINT8 *Source; - UINT8 *Destination; - UINT8 AlignTo16ByteInCache; - UINT8 AlignTo16ByteInTempMem; - UINT8 Ignored; - UINT32 SizeOfNodeData; - UINT32 TotalSize; - UINT32 HeapRamFixMtrr; - UINT32 HeapRamVariableMtrr; - UINT32 HeapInCacheOffset; - UINT64 MsrData; - UINT64 VariableMtrrBase; - UINT64 VariableMtrrMask; - UINTN AmdHeapRamAddress; - AGESA_STATUS IgnoredStatus; - BUFFER_NODE *HeapInCache; - BUFFER_NODE *HeapInTempMem; - HEAP_MANAGER *HeapManagerInCache; - HEAP_MANAGER *HeapManagerInTempMem; - CACHE_INFO *CacheInfoPtr; - CPU_SPECIFIC_SERVICES *FamilySpecificServices; - - AmdHeapRamAddress = (UINTN) UserOptions.CfgHeapDramAddress; - // - //If the user define address above 1M, Mem Init has already set - //whole available memory as WB cacheable. - // - if (AmdHeapRamAddress < 0x100000) { - // Region below 1MB - // Fixed MTRR region - // turn on modification bit - LibAmdMsrRead (MSR_SYS_CFG, &MsrData, StdHeader); - MsrData |= 0x80000; - LibAmdMsrWrite (MSR_SYS_CFG, &MsrData, StdHeader); - - if (AmdHeapRamAddress >= 0xC0000) { - // - // 0xC0000 ~ 0xFFFFF - // - HeapRamFixMtrr = (UINT32) (AMD_MTRR_FIX4k_C0000 + (((AmdHeapRamAddress >> 16) & 0x3) * 2)); - MsrData = (UINT64)AMD_MTRR_FIX4K_UC_DRAM; - LibAmdMsrWrite (HeapRamFixMtrr, &MsrData, StdHeader); - LibAmdMsrWrite ((HeapRamFixMtrr + 1), &MsrData, StdHeader); - } else if (AmdHeapRamAddress >= 0x80000) { - // - // 0x80000~0xBFFFF - // - HeapRamFixMtrr = (UINT32) (AMD_MTRR_FIX16k_80000 + ((AmdHeapRamAddress >> 17) & 0x1)); - MsrData = (UINT64)AMD_MTRR_FIX16K_UC_DRAM; - LibAmdMsrWrite (HeapRamFixMtrr, &MsrData, StdHeader); - } else { - // - // 0x0 ~ 0x7FFFF - // - LibAmdMsrRead (AMD_MTRR_FIX64k_00000, &MsrData, StdHeader); - MsrData = MsrData & (~(0xFF << (8 * ((AmdHeapRamAddress >> 16) & 0x7)))); - MsrData = MsrData | (AMD_MTRR_FIX64K_UC_DRAM << (8 * ((AmdHeapRamAddress >> 16) & 0x7))); - LibAmdMsrWrite (AMD_MTRR_FIX64k_00000, &MsrData, StdHeader); - } - - // Turn on MTRR enable bit and turn off modification bit - LibAmdMsrRead (MSR_SYS_CFG, &MsrData, StdHeader); - MsrData |= 0x40000; - MsrData &= 0xFFFFFFFFFFF7FFFFull; - LibAmdMsrWrite (MSR_SYS_CFG, &MsrData, StdHeader); - } else { - // Region above 1MB - // Variable MTRR region - // Get family specific cache Info - GetCpuServicesOfCurrentCore ((const CPU_SPECIFIC_SERVICES **)&FamilySpecificServices, StdHeader); - FamilySpecificServices->GetCacheInfo (FamilySpecificServices, (const VOID **) &CacheInfoPtr, &Ignored, StdHeader); - - // Find an empty MTRRphysBase/MTRRphysMask - for (HeapRamVariableMtrr = AMD_MTRR_VARIABLE_HEAP_BASE; - HeapRamVariableMtrr >= AMD_MTRR_VARIABLE_BASE0; - HeapRamVariableMtrr--) { - LibAmdMsrRead (HeapRamVariableMtrr, &VariableMtrrBase, StdHeader); - LibAmdMsrRead ((HeapRamVariableMtrr + 1), &VariableMtrrMask, StdHeader); - if ((VariableMtrrBase == 0) && (VariableMtrrMask == 0)) { - break; - } - } - if (HeapRamVariableMtrr < AMD_MTRR_VARIABLE_BASE0) { - // All variable MTRR is used. - ASSERT (FALSE); - } - - // Set variable MTRR base and mask - // If the address ranges of two or more MTRRs overlap - // and if at least one of the memory types is UC, the UC memory type is used. - VariableMtrrBase = (UINT64) (AmdHeapRamAddress & CacheInfoPtr->HeapBaseMask); - VariableMtrrMask = CacheInfoPtr->VariableMtrrHeapMask & (UINT64)AMD_HEAP_MTRR_MASK; - LibAmdMsrWrite (HeapRamVariableMtrr, &VariableMtrrBase, StdHeader); - LibAmdMsrWrite ((HeapRamVariableMtrr + 1), &VariableMtrrMask, StdHeader); - } - // Copying Heap content - if (IsBsp (StdHeader, &IgnoredStatus)) { - TotalSize = sizeof (HEAP_MANAGER); - SizeOfNodeData = 0; - AlignTo16ByteInTempMem = 0; - BaseAddressInCache = (UINT8 *) (intptr_t) StdHeader->HeapBasePtr; - HeapManagerInCache = (HEAP_MANAGER *) BaseAddressInCache; - HeapInCacheOffset = HeapManagerInCache->FirstActiveBufferOffset; - HeapInCache = (BUFFER_NODE *) (BaseAddressInCache + HeapInCacheOffset); - - BaseAddressInTempMem = (UINT8 *) (intptr_t) UserOptions.CfgHeapDramAddress; - HeapManagerInTempMem = (HEAP_MANAGER *) BaseAddressInTempMem; - HeapInTempMem = (BUFFER_NODE *) (BaseAddressInTempMem + TotalSize); - - // copy heap from cache to temp memory. - // only heap with persist great than HEAP_LOCAL_CACHE will be copied. - // Note: Only copy heap with persist greater than HEAP_LOCAL_CACHE. - while (HeapInCacheOffset != AMD_HEAP_INVALID_HEAP_OFFSET) { - if (HeapInCache->Persist > HEAP_LOCAL_CACHE) { - AlignTo16ByteInCache = HeapInCache->PadSize; - AlignTo16ByteInTempMem = (UINT8) ((0x10 - (((UINTN) (VOID *) HeapInTempMem + sizeof (BUFFER_NODE) + SIZE_OF_SENTINEL) & 0xF)) & 0xF); - SizeOfNodeData = HeapInCache->BufferSize - AlignTo16ByteInCache; - TotalSize = (UINT32) (TotalSize + sizeof (BUFFER_NODE) + SizeOfNodeData + AlignTo16ByteInTempMem); - Source = (UINT8 *) HeapInCache + sizeof (BUFFER_NODE) + AlignTo16ByteInCache; - Destination = (UINT8 *) HeapInTempMem + sizeof (BUFFER_NODE) + AlignTo16ByteInTempMem; - LibAmdMemCopy (HeapInTempMem, HeapInCache, sizeof (BUFFER_NODE), StdHeader); - LibAmdMemCopy (Destination, Source, SizeOfNodeData, StdHeader); - HeapInTempMem->OffsetOfNextNode = TotalSize; - HeapInTempMem->BufferSize = SizeOfNodeData + AlignTo16ByteInTempMem; - HeapInTempMem->PadSize = AlignTo16ByteInTempMem; - HeapInTempMem = (BUFFER_NODE *) (BaseAddressInTempMem + TotalSize); - } - HeapInCacheOffset = HeapInCache->OffsetOfNextNode; - HeapInCache = (BUFFER_NODE *) (BaseAddressInCache + HeapInCacheOffset); - } - // initialize heap manager - if (TotalSize == sizeof (HEAP_MANAGER)) { - // heap is empty - HeapManagerInTempMem->UsedSize = sizeof (HEAP_MANAGER); - HeapManagerInTempMem->FirstActiveBufferOffset = AMD_HEAP_INVALID_HEAP_OFFSET; - HeapManagerInTempMem->FirstFreeSpaceOffset = sizeof (HEAP_MANAGER); - } else { - // heap is NOT empty - HeapManagerInTempMem->UsedSize = TotalSize; - HeapManagerInTempMem->FirstActiveBufferOffset = sizeof (HEAP_MANAGER); - HeapManagerInTempMem->FirstFreeSpaceOffset = TotalSize; - HeapInTempMem = (BUFFER_NODE *) (BaseAddressInTempMem + TotalSize - SizeOfNodeData - AlignTo16ByteInTempMem - sizeof (BUFFER_NODE)); - HeapInTempMem->OffsetOfNextNode = AMD_HEAP_INVALID_HEAP_OFFSET; - HeapInTempMem = (BUFFER_NODE *) (BaseAddressInTempMem + TotalSize); - } - // heap signature - HeapManagerInCache->Signature = 0x00000000; - HeapManagerInTempMem->Signature = HEAP_SIGNATURE_VALID; - // Free space node - HeapInTempMem->BufferSize = (UINT32) (AMD_HEAP_SIZE_PER_CORE - TotalSize); - HeapInTempMem->OffsetOfNextNode = AMD_HEAP_INVALID_HEAP_OFFSET; - } - return AGESA_SUCCESS; -} - - -/* -----------------------------------------------------------------------------*/ -/** - * - * CopyHeapToMainRamAtPost - * - * This function copies Temp Ram heap content to Main Ram - * - * @param[in,out] StdHeader - Pointer to AMD_CONFIG_PARAMS struct. - * - * @retval AGESA_STATUS - * - */ -AGESA_STATUS -CopyHeapToMainRamAtPost ( - IN OUT AMD_CONFIG_PARAMS *StdHeader - ) -{ - UINT8 *BaseAddressInTempMem; - UINT8 *BaseAddressInMainMem; - UINT8 *Source; - UINT8 *Destination; - UINT8 AlignTo16ByteInTempMem; - UINT8 AlignTo16ByteInMainMem; - UINT8 Ignored; - UINT32 SizeOfNodeData; - UINT32 TotalSize; - UINT32 HeapInTempMemOffset; - UINT32 HeapRamVariableMtrr; - UINT64 VariableMtrrBase; - UINT64 VariableMtrrMask; - AGESA_STATUS IgnoredStatus; - BUFFER_NODE *HeapInTempMem; - BUFFER_NODE *HeapInMainMem; - HEAP_MANAGER *HeapManagerInTempMem; - HEAP_MANAGER *HeapManagerInMainMem; - AGESA_BUFFER_PARAMS AgesaBuffer; - CACHE_INFO *CacheInfoPtr; - CPU_SPECIFIC_SERVICES *FamilySpecificServices; - - if (IsBsp (StdHeader, &IgnoredStatus)) { - TotalSize = sizeof (HEAP_MANAGER); - SizeOfNodeData = 0; - AlignTo16ByteInMainMem = 0; - BaseAddressInTempMem = (UINT8 *) (intptr_t) StdHeader->HeapBasePtr; - HeapManagerInTempMem = (HEAP_MANAGER *) (intptr_t) StdHeader->HeapBasePtr; - HeapInTempMemOffset = HeapManagerInTempMem->FirstActiveBufferOffset; - HeapInTempMem = (BUFFER_NODE *) (BaseAddressInTempMem + HeapInTempMemOffset); - - AgesaBuffer.StdHeader = *StdHeader; - AgesaBuffer.BufferHandle = AMD_HEAP_IN_MAIN_MEMORY_HANDLE; - AgesaBuffer.BufferLength = AMD_HEAP_SIZE_PER_CORE; - if (AgesaAllocateBuffer (0, &AgesaBuffer) != AGESA_SUCCESS) { - return AGESA_ERROR; - } - BaseAddressInMainMem = (UINT8 *) AgesaBuffer.BufferPointer; - HeapManagerInMainMem = (HEAP_MANAGER *) BaseAddressInMainMem; - HeapInMainMem = (BUFFER_NODE *) (BaseAddressInMainMem + TotalSize); - LibAmdMemFill (BaseAddressInMainMem, 0x00, AMD_HEAP_SIZE_PER_CORE, StdHeader); - // copy heap from temp memory to main memory. - // only heap with persist great than HEAP_TEMP_MEM will be copied. - // Note: Only copy heap buffers with persist greater than HEAP_TEMP_MEM. - while (HeapInTempMemOffset != AMD_HEAP_INVALID_HEAP_OFFSET) { - if (HeapInTempMem->Persist > HEAP_TEMP_MEM) { - AlignTo16ByteInTempMem = HeapInTempMem->PadSize; - AlignTo16ByteInMainMem = (UINT8) ((0x10 - (((UINTN) (VOID *) HeapInMainMem + sizeof (BUFFER_NODE) + SIZE_OF_SENTINEL) & 0xF)) & 0xF); - SizeOfNodeData = HeapInTempMem->BufferSize - AlignTo16ByteInTempMem; - TotalSize = (UINT32) (TotalSize + sizeof (BUFFER_NODE) + SizeOfNodeData + AlignTo16ByteInMainMem); - Source = (UINT8 *) HeapInTempMem + sizeof (BUFFER_NODE) + AlignTo16ByteInTempMem; - Destination = (UINT8 *) HeapInMainMem + sizeof (BUFFER_NODE) + AlignTo16ByteInMainMem; - LibAmdMemCopy (HeapInMainMem, HeapInTempMem, sizeof (BUFFER_NODE), StdHeader); - LibAmdMemCopy (Destination, Source, SizeOfNodeData, StdHeader); - HeapInMainMem->OffsetOfNextNode = TotalSize; - HeapInMainMem->BufferSize = SizeOfNodeData + AlignTo16ByteInMainMem; - HeapInMainMem->PadSize = AlignTo16ByteInMainMem; - HeapInMainMem = (BUFFER_NODE *) (BaseAddressInMainMem + TotalSize); - } - HeapInTempMemOffset = HeapInTempMem->OffsetOfNextNode; - HeapInTempMem = (BUFFER_NODE *) (BaseAddressInTempMem + HeapInTempMemOffset); - } - // initialize heap manager - if (TotalSize == sizeof (HEAP_MANAGER)) { - // heap is empty - HeapManagerInMainMem->UsedSize = sizeof (HEAP_MANAGER); - HeapManagerInMainMem->FirstActiveBufferOffset = AMD_HEAP_INVALID_HEAP_OFFSET; - HeapManagerInMainMem->FirstFreeSpaceOffset = sizeof (HEAP_MANAGER); - } else { - // heap is NOT empty - HeapManagerInMainMem->UsedSize = TotalSize; - HeapManagerInMainMem->FirstActiveBufferOffset = sizeof (HEAP_MANAGER); - HeapManagerInMainMem->FirstFreeSpaceOffset = TotalSize; - HeapInMainMem = (BUFFER_NODE *) (BaseAddressInMainMem + TotalSize - SizeOfNodeData - AlignTo16ByteInMainMem - sizeof (BUFFER_NODE)); - HeapInMainMem->OffsetOfNextNode = AMD_HEAP_INVALID_HEAP_OFFSET; - HeapInMainMem = (BUFFER_NODE *) (BaseAddressInMainMem + TotalSize); - } - // heap signature - HeapManagerInTempMem->Signature = 0x00000000; - HeapManagerInMainMem->Signature = HEAP_SIGNATURE_VALID; - // Free space node - HeapInMainMem->BufferSize = AMD_HEAP_SIZE_PER_CORE - TotalSize; - HeapInMainMem->OffsetOfNextNode = AMD_HEAP_INVALID_HEAP_OFFSET; - } - // if address of heap in temp memory is above 1M, then we must used one variable MTRR. - if (StdHeader->HeapBasePtr >= 0x100000) { - // Find out which variable MTRR was used in CopyHeapToTempRamAtPost. - GetCpuServicesOfCurrentCore ((const CPU_SPECIFIC_SERVICES **) &FamilySpecificServices, StdHeader); - FamilySpecificServices->GetCacheInfo (FamilySpecificServices, (const VOID **) &CacheInfoPtr, &Ignored, StdHeader); - for (HeapRamVariableMtrr = AMD_MTRR_VARIABLE_HEAP_BASE; - HeapRamVariableMtrr >= AMD_MTRR_VARIABLE_BASE0; - HeapRamVariableMtrr--) { - LibAmdMsrRead (HeapRamVariableMtrr, &VariableMtrrBase, StdHeader); - LibAmdMsrRead ((HeapRamVariableMtrr + 1), &VariableMtrrMask, StdHeader); - if ((VariableMtrrBase == (UINT64) (StdHeader->HeapBasePtr & CacheInfoPtr->HeapBaseMask)) && - (VariableMtrrMask == (UINT64) (CacheInfoPtr->VariableMtrrHeapMask & (UINT64) AMD_HEAP_MTRR_MASK))) { - break; - } - } - if (HeapRamVariableMtrr >= AMD_MTRR_VARIABLE_BASE0) { - // Clear variable MTRR which set in CopyHeapToTempRamAtPost. - VariableMtrrBase = 0; - VariableMtrrMask = 0; - LibAmdMsrWrite (HeapRamVariableMtrr, &VariableMtrrBase, StdHeader); - LibAmdMsrWrite ((HeapRamVariableMtrr + 1), &VariableMtrrMask, StdHeader); - } - } - return AGESA_SUCCESS; -} diff --git a/src/vendorcode/amd/agesa/f12/MainPage.h b/src/vendorcode/amd/agesa/f12/MainPage.h deleted file mode 100644 index a9871dc545..0000000000 --- a/src/vendorcode/amd/agesa/f12/MainPage.h +++ /dev/null @@ -1,119 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * Create outline and references for mainpage documentation. - * - * Design guides, maintenance guides, and general documentation, are - * collected using this file onto the documentation mainpage. - * This file contains doxygen comment blocks, only. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: Documentation - * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $ - * - */ -/* - ****************************************************************************** - * - * Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - ****************************************************************************** - */ - -/** - * @mainpage - * - * The design and maintenance documentation for AGESA Sample Code is organized as - * follows. On this page, you can reference design guides, maintenance guides, and - * general documentation. Detailed Data Structure, Function, and Interface documentation - * may be found using the Data Structures or Files tabs. See Related Pages for a - * Release content summary, and, if this is not a production release, lists of To Do's, - * Deprecated items, etc. - * - * @subpage starthere "Start Here - Initial Porting and Integration." - * - * @subpage optionmain "Build Configuration and Options Guides and Documentation." - * - * @subpage commonmain "Processor Common Component Guides and Documentation." - * - * @subpage cpumain "CPU Component Guides and Documentation." - * - * @subpage htmain "HT Component Guides and Documentation." - * - * @subpage memmain "MEM Component Guides and Documentation." - * - * @subpage gnbmain "GNB Component Documentation." - * - * @subpage idsmain "IDS Component Guides and Documentation." - * - * @subpage recoverymain "Recovery Component Guides and Documentation." - * - */ - -/** - * @page starthere Initial Porting and Integration - * - * @par Basic Check List - * - *
    - *
  • Copy the \Options.c file from the Addendum directory to the platform tip build directory. - * AMD recommends the use of a sub-directory named AGESA to contain these files and the build output files. - *
  • Copy the OptionsIds.h content in the spec to OptionsIds.h in the platform build tip directory - * and make changes to enable the IDS support desired. It is highly recommended to set the following for - * initial integration and development:@n - * @code - * #define IDSOPT_IDS_ENABLED TRUE - * #define IDSOPT_ERROR_TRAP_ENABLED TRUE - * #define IDSOPT_ASSERT_ENABLED TRUE - * @endcode - *
  • Edit and modify the option selections in those two files to meet the needs of the specific platform. - *
  • Set the environment variable AGESA_ROOT to the root folder of the AGESA code. - *
  • Set the environment variable AGESA_OptsDir the platform build tip AGESA directory. - *
  • Generate the doxygen documentation or locate the file arch2008.chm within your AGESA release package. - *
- * - * @par Debugging Using ASSERT and IDS_ERROR_TRAP - * - * While AGESA code uses ::ASSERT and ::IDS_ERROR_TRAP to check for internal errors, these macros can also - * catch and assist debug of wrapper and platform BIOS issues. - * - * When an ::ASSERT fails or an ::IDS_ERROR_TRAP is executed, the AGESA code will enter a halt loop and display a - * Stop Code. A Stop Code is eight hex digits. The first (most significant) four are the FILECODE. - * FILECODEs can be looked up in Filecode.h to determine which file contains the stop macro. Each file has a - * unique code value. - * The least significant digits are the line number in that file. - * For example, 0210 means the macro is on line two hundred ten. - * (see ::IdsErrorStop for more details on stop code display.) - * - * Enabling ::ASSERT and ::IDS_ERROR_TRAP ensure errors are caught and also provide a useful debug assist. - * Comments near each macro use will describe the nature of the error and typical wrapper errors or other - * root causes. - * - * After your wrapper consistently executes ::ASSERT and ::IDS_ERROR_TRAP stop free, you can disable them in - * OptionsIds.h, except for regression testing. IDS is not expected to be enabled in production BIOS builds. - * - */ diff --git a/src/vendorcode/amd/agesa/f12/Makefile.inc b/src/vendorcode/amd/agesa/f12/Makefile.inc deleted file mode 100644 index d53b3a3dc5..0000000000 --- a/src/vendorcode/amd/agesa/f12/Makefile.inc +++ /dev/null @@ -1,49 +0,0 @@ -#***************************************************************************** -# -# Copyright (c) 2011, Advanced Micro Devices, Inc. -# All rights reserved. -# -# Redistribution and use in source and binary forms, with or without -# modification, are permitted provided that the following conditions are met: -# * Redistributions of source code must retain the above copyright -# notice, this list of conditions and the following disclaimer. -# * Redistributions in binary form must reproduce the above copyright -# notice, this list of conditions and the following disclaimer in the -# documentation and/or other materials provided with the distribution. -# * Neither the name of Advanced Micro Devices, Inc. nor the names of -# its contributors may be used to endorse or promote products derived -# from this software without specific prior written permission. -# -# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -# ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -# WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -# DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY -# DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -# (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -# LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -# ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -# SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -# -#***************************************************************************** - -# AGESA V5 Files -AGESA_ROOT = src/vendorcode/amd/agesa/f12 - -AGESA_AUTOINCLUDES := $(shell find $(AGESA_ROOT)/Proc -type d -exec echo -n "-I"{}" " \;) - -AGESA_INC = -I$(src)/vendorcode/amd/include -AGESA_INC += -I$(AGESA_ROOT) -AGESA_INC += -I$(AGESA_ROOT)/../common -AGESA_INC += -I$(AGESA_ROOT)/Include -AGESA_INC += -I$(src)/mainboard/$(MAINBOARDDIR) # OptionsIds.h - -BUILDOPTS_INCLUDES = -I$(AGESA_ROOT)/Config $(AGESA_INC) $(AGESA_AUTOINCLUDES) - -CPPFLAGS_x86_32 += $(AGESA_INC) -CPPFLAGS_x86_64 += $(AGESA_INC) - -####################################################################### - -subdirs-y += Legacy/Proc -subdirs-y += $(dir $(shell cd $(dir); find Proc -name Makefile.inc)) diff --git a/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x12/F12C6State.c b/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x12/F12C6State.c deleted file mode 100644 index b7c7f76be4..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x12/F12C6State.c +++ /dev/null @@ -1,193 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * AMD Family_12 C6 C-state feature support functions. - * - * Provides the functions necessary to initialize the C6 feature. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: CPU/F12 - * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $ - * - */ -/* - ****************************************************************************** - * - * Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - ****************************************************************************** - */ - -/*---------------------------------------------------------------------------------------- - * M O D U L E S U S E D - *---------------------------------------------------------------------------------------- - */ -#include "AGESA.h" -#include "amdlib.h" -#include "Ids.h" -#include "cpuRegisters.h" -#include "cpuFeatures.h" -#include "cpuC6State.h" -#include "cpuF12PowerMgmt.h" -#include "OptionFamily12hEarlySample.h" -#include "Filecode.h" -CODE_GROUP (G1_PEICC) -RDATA_GROUP (G1_PEICC) - -#define FILECODE PROC_CPU_FAMILY_0X12_F12C6STATE_FILECODE - -/*---------------------------------------------------------------------------------------- - * D E F I N I T I O N S A N D M A C R O S - *---------------------------------------------------------------------------------------- - */ -extern F12_ES_C6_SUPPORT F12EarlySampleC6Support; - -/*---------------------------------------------------------------------------------------- - * T Y P E D E F S A N D S T R U C T U R E S - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------- - * P R O T O T Y P E S O F L O C A L F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------- - * E X P O R T E D F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ - - -/*---------------------------------------------------------------------------------------*/ -/** - * Is C6 supported on this CPU - * - * @param[in] C6Services Pointer to this CPU's C6 family services. - * @param[in] Socket This core's zero-based socket number. - * @param[in] PlatformConfig Contains the runtime modifiable feature input data. - * @param[in] StdHeader Config Handle for library, services. - * - * @retval TRUE C6 state is supported. - * @retval FALSE C6 state is not supported. - * - */ -BOOLEAN -STATIC -F12IsC6Supported ( - IN C6_FAMILY_SERVICES *C6Services, - IN UINT32 Socket, - IN PLATFORM_CONFIGURATION *PlatformConfig, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - UINT32 LocalPciRegister; - BOOLEAN IsEnabled; - PCI_ADDR PciAddress; - - IsEnabled = TRUE; - PciAddress.AddressValue = CPU_STATE_PM_CTRL1_PCI_ADDR; - LibAmdPciRead (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader); - if ((((CPU_STATE_PM_CTRL1_REGISTER *) &LocalPciRegister)->CoreC6Cap == 0) && - (((CPU_STATE_PM_CTRL1_REGISTER *) &LocalPciRegister)->PkgC6Cap == 0)) { - IsEnabled = FALSE; - } - return IsEnabled; -} - -/*---------------------------------------------------------------------------------------*/ -/** - * Enable C6 on a family 12h CPU. - * - * @param[in] C6Services Pointer to this CPU's C6 family services. - * @param[in] EntryPoint Timepoint designator. - * @param[in] PlatformConfig Contains the runtime modifiable feature input data. - * @param[in] StdHeader Config Handle for library, services. - * - * @return AGESA_SUCCESS Always succeeds. - * - */ -AGESA_STATUS -STATIC -F12InitializeC6 ( - IN C6_FAMILY_SERVICES *C6Services, - IN UINT64 EntryPoint, - IN PLATFORM_CONFIGURATION *PlatformConfig, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - UINT32 i; - UINT32 MaxEnabledPstate; - UINT32 LocalPciRegister; - UINT64 LocalMsrRegister; - PCI_ADDR PciAddress; - - for (i = MSR_PSTATE_7; i > MSR_PSTATE_0; i--) { - LibAmdMsrRead (i, &LocalMsrRegister, StdHeader); - if (((PSTATE_MSR *) &LocalMsrRegister)->PsEnable == 1) { - break; - } - } - MaxEnabledPstate = i - MSR_PSTATE_0; - - if ((EntryPoint & CPU_FEAT_AFTER_PM_INIT) != 0) { - F12EarlySampleC6Support.F12InitializeC6 (StdHeader); - } else { - // Ensure D18F2x118[C6DramLock] and D18F4x12C[C6Base] are programmed. - PciAddress.AddressValue = MEM_CFG_LOW_PCI_ADDR; - LibAmdPciRead (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader); - ASSERT (((MEM_CFG_LOW_REGISTER *) &LocalPciRegister)->C6DramLock == 1); - - PciAddress.AddressValue = C6_BASE_PCI_ADDR; - LibAmdPciRead (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader); - ASSERT (((C6_BASE_REGISTER *) &LocalPciRegister)->C6Base != 0); - - // If PC6 is supported, program D18F4x1AC[PstateIdCoreOffExit] to - // the index of lowest-performance Pstate with MSRC001_00[6B:64] - // [PstateEn] == 1 on core 0. - PciAddress.AddressValue = CPU_STATE_PM_CTRL1_PCI_ADDR; - LibAmdPciRead (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader); - if (((CPU_STATE_PM_CTRL1_REGISTER *) &LocalPciRegister)->PkgC6Cap == 1) { - ((CPU_STATE_PM_CTRL1_REGISTER *) &LocalPciRegister)->PstateIdCoreOffExit = MaxEnabledPstate; - LibAmdPciWrite (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader); - } - - // Program D18F4x118 to 0000_0101h. - PciAddress.AddressValue = CSTATE_CTRL1_PCI_ADDR; - LocalPciRegister = 0x00000101; - LibAmdPciWrite (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader); - } - - return AGESA_SUCCESS; -} - -CONST C6_FAMILY_SERVICES ROMDATA F12C6Support = -{ - 0, - F12IsC6Supported, - F12InitializeC6, - ReloadMicrocodePatchAfterMemInit -}; diff --git a/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x12/F12Cpb.c b/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x12/F12Cpb.c deleted file mode 100644 index 2f4e0989b2..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x12/F12Cpb.c +++ /dev/null @@ -1,171 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * AMD Family_12 CPB Initialization - * - * Enables core performance boost. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: CPU/F12 - * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $ - * - */ -/* - ****************************************************************************** - * - * Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - ****************************************************************************** - */ - -/*---------------------------------------------------------------------------------------- - * M O D U L E S U S E D - *---------------------------------------------------------------------------------------- - */ -#include "AGESA.h" -#include "amdlib.h" -#include "cpuFamilyTranslation.h" -#include "cpuF12PowerMgmt.h" -#include "GnbRegistersLN.h" -#include "NbSmuLib.h" -#include "cpuFeatures.h" -#include "cpuCpb.h" -#include "OptionFamily12hEarlySample.h" -#include "Filecode.h" -CODE_GROUP (G1_PEICC) -RDATA_GROUP (G1_PEICC) - -#define FILECODE PROC_CPU_FAMILY_0X12_F12CPB_FILECODE - -/*---------------------------------------------------------------------------------------- - * D E F I N I T I O N S A N D M A C R O S - *---------------------------------------------------------------------------------------- - */ -//extern F12_ES_CPB_SUPPORT F12EarlySampleCpbSupport; - -/*---------------------------------------------------------------------------------------- - * T Y P E D E F S A N D S T R U C T U R E S - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------- - * P R O T O T Y P E S O F L O C A L F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------- - * E X P O R T E D F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------*/ -/** - * BSC entry point for checking whether or not CPB is supported. - * - * @param[in] CpbServices The current CPU's family services. - * @param[in] PlatformConfig Contains the runtime modifiable feature input data. - * @param[in] Socket Zero based socket number to check. - * @param[in] StdHeader Config handle for library and services. - * - * @retval TRUE CPB is supported. - * @retval FALSE CPB is not supported. - * - */ -BOOLEAN -STATIC -F12IsCpbSupported ( - IN CPB_FAMILY_SERVICES *CpbServices, - IN PLATFORM_CONFIGURATION *PlatformConfig, - IN UINT32 Socket, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - PCI_ADDR PciAddress; - D18F4x15C_STRUCT CpbControl; - - PciAddress.AddressValue = CPB_CTRL_PCI_ADDR; - LibAmdPciRead (AccessWidth32, PciAddress, &CpbControl.Value, StdHeader); - return (BOOLEAN) (CpbControl.Field.NumBoostStates != 0); -} - - -/*---------------------------------------------------------------------------------------*/ -/** - * BSC entry point for enabling Core Performance Boost. - * - * Set up D18F4x15C[BoostSrc] and start the PDMs according to the BKDG. - * - * @param[in] CpbServices The current CPU's family services. - * @param[in] PlatformConfig Contains the runtime modifiable feature input data. - * @param[in] EntryPoint Current CPU feature dispatch point. - * @param[in] Socket Zero based socket number to check. - * @param[in] StdHeader Config handle for library and services. - * - * @retval AGESA_SUCCESS Always succeeds. - * - */ -AGESA_STATUS -STATIC -F12InitializeCpb ( - IN CPB_FAMILY_SERVICES *CpbServices, - IN PLATFORM_CONFIGURATION *PlatformConfig, - IN UINT64 EntryPoint, - IN UINT32 Socket, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - PCI_ADDR PciAddress; - D18F4x15C_STRUCT CpbControl; - SMUx0B_x8580_STRUCT SMUx0Bx8580; - - if ((EntryPoint & CPU_FEAT_BEFORE_PM_INIT) != 0) { -// F12EarlySampleCpbSupport.F12CpbInitHook (StdHeader); - PciAddress.AddressValue = CPB_CTRL_PCI_ADDR; - LibAmdPciRead (AccessWidth32, PciAddress, &CpbControl.Value, StdHeader); - CpbControl.Field.BoostSrc = 1; - IDS_OPTION_HOOK (IDS_CPB_CTRL, &CpbControl.Value, StdHeader); - LibAmdPciWrite (AccessWidth32, PciAddress, &CpbControl.Value, StdHeader); - } else if ((EntryPoint & CPU_FEAT_INIT_LATE_END) != 0) { - // Ensure that the recommended settings have been programmed into SMUx0B_x8580, then - // interrupt the SMU with service index 12h. - SMUx0Bx8580.Value = 0; - SMUx0Bx8580.Field.PdmPeriod = 0x1388; - SMUx0Bx8580.Field.PdmUnit = 1; - SMUx0Bx8580.Field.PdmCacEn = 1; - SMUx0Bx8580.Field.PdmEn = 1; - NbSmuRcuRegisterWrite (SMUx0B_x8580_ADDRESS, &SMUx0Bx8580.Value, 1, TRUE, StdHeader); - NbSmuServiceRequest (0x12, TRUE, StdHeader); - } - return AGESA_SUCCESS; -} - -CONST CPB_FAMILY_SERVICES ROMDATA F12CpbSupport = -{ - 0, - F12IsCpbSupported, - F12InitializeCpb -}; diff --git a/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x12/F12IoCstate.c b/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x12/F12IoCstate.c deleted file mode 100644 index 7e7b089f29..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x12/F12IoCstate.c +++ /dev/null @@ -1,278 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * AMD Family_12 IO C-state feature support functions. - * - * Provides the functions necessary to initialize the IO C-state feature. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: CPU/F12 - * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $ - * - */ -/* - ****************************************************************************** - * - * Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - ****************************************************************************** - */ - -/*---------------------------------------------------------------------------------------- - * M O D U L E S U S E D - *---------------------------------------------------------------------------------------- - */ - -#include "AGESA.h" -#include "amdlib.h" -#include "Ids.h" -#include "cpuRegisters.h" -#include "cpuFamilyTranslation.h" -#include "cpuFeatures.h" -#include "cpuIoCstate.h" -#include "cpuF12PowerMgmt.h" -#include "cpuLateInit.h" -#include "cpuApicUtilities.h" -#include "cpuServices.h" -#include "CommonReturns.h" -#include "Filecode.h" -CODE_GROUP (G1_PEICC) -RDATA_GROUP (G1_PEICC) - -#define FILECODE PROC_CPU_FAMILY_0X12_F12IOCSTATE_FILECODE - -/*---------------------------------------------------------------------------------------- - * P R O T O T Y P E S O F L O C A L F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ -VOID -STATIC -F12InitializeIoCstateOnCore ( - IN VOID *CstateBaseMsr, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -/*---------------------------------------------------------------------------------------- - * E X P O R T E D F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------*/ -/** - * Enable IO Cstate on a family 12h CPU. - * Implement steps 1 to 3 of BKDG section 2.5.3.2.9 BIOS Requirements for Initialization - * - * @param[in] IoCstateServices Pointer to this CPU's IO Cstate family services. - * @param[in] EntryPoint Timepoint designator. - * @param[in] PlatformConfig Contains the runtime modifiable feature input data. - * @param[in] StdHeader Config Handle for library, services. - * - * @return AGESA_SUCCESS Always succeeds. - * - */ -AGESA_STATUS -STATIC -F12InitializeIoCstate ( - IN IO_CSTATE_FAMILY_SERVICES *IoCstateServices, - IN UINT64 EntryPoint, - IN PLATFORM_CONFIGURATION *PlatformConfig, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - UINT32 i; - UINT32 MaxEnabledPstate; - UINT32 LocalPciRegister; - UINT64 LocalMsrRegister; - AP_TASK TaskPtr; - PCI_ADDR PciAddress; - - if ((EntryPoint & CPU_FEAT_AFTER_PM_INIT) != 0) { - for (i = MSR_PSTATE_7; i > MSR_PSTATE_0; i--) { - LibAmdMsrRead (i, &LocalMsrRegister, StdHeader); - if (((PSTATE_MSR *) &LocalMsrRegister)->PsEnable == 1) { - break; - } - } - MaxEnabledPstate = i - MSR_PSTATE_0; - // Initialize MSRC001_0073[CstateAddr] on each core to a region of - // the IO address map with 8 consecutive available addresses. - LocalMsrRegister = 0; - ((CSTATE_ADDRESS_MSR *) &LocalMsrRegister)->CstateAddr = PlatformConfig->CStateIoBaseAddress; - ASSERT ((((CSTATE_ADDRESS_MSR *) &LocalMsrRegister)->CstateAddr != 0) && - (((CSTATE_ADDRESS_MSR *) &LocalMsrRegister)->CstateAddr <= 0xFFF8)); - - TaskPtr.FuncAddress.PfApTaskI = F12InitializeIoCstateOnCore; - TaskPtr.DataTransfer.DataSizeInDwords = 2; - TaskPtr.DataTransfer.DataPtr = &LocalMsrRegister; - TaskPtr.DataTransfer.DataTransferFlags = 0; - TaskPtr.ExeFlags = WAIT_FOR_CORE; - ApUtilRunCodeOnAllLocalCoresAtEarly (&TaskPtr, StdHeader, NULL); - - // Program D18F4x1A8[PService] to the index of lowest-performance - // P-state with MSRC001_00[6B:64][PstateEn]==1 on core 0. - PciAddress.AddressValue = CPU_STATE_PM_CTRL0_PCI_ADDR; - LibAmdPciRead (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader); - ((CPU_STATE_PM_CTRL0_REGISTER *) &LocalPciRegister)->PService = MaxEnabledPstate; - LibAmdPciWrite (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader); - - // Program D18F4x1AC[CstPminEn] to 1. - PciAddress.AddressValue = CPU_STATE_PM_CTRL1_PCI_ADDR; - LibAmdPciRead (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader); - ((CPU_STATE_PM_CTRL1_REGISTER *) &LocalPciRegister)->CstPminEn = 1; - LibAmdPciWrite (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader); - } - return AGESA_SUCCESS; -} - -/*---------------------------------------------------------------------------------------*/ -/** - * Enable C-State on a family 12h core. - * - * @param[in] CstateBaseMsr MSR value to write to C001_0073 as determined by core 0. - * @param[in] StdHeader Config Handle for library, services. - * - */ -VOID -STATIC -F12InitializeIoCstateOnCore ( - IN VOID *CstateBaseMsr, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - // Initialize MSRC001_0073[CstateAddr] on each core - LibAmdMsrWrite (MSR_CSTATE_ADDRESS, (UINT64 *) CstateBaseMsr, StdHeader); -} - - -/*---------------------------------------------------------------------------------------*/ -/** - * Returns the size of CST object - * - * @param[in] IoCstateServices IoCstate services. - * @param[in] PlatformConfig Contains the runtime modifiable feature input data - * @param[in] StdHeader Config Handle for library, services. - * - * @retval CstObjSize Size of CST Object - * - */ -UINT32 -STATIC -F12GetAcpiCstObj ( - IN IO_CSTATE_FAMILY_SERVICES *IoCstateServices, - IN PLATFORM_CONFIGURATION *PlatformConfig, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - return (CST_HEADER_SIZE + CST_BODY_SIZE); -} - -/*---------------------------------------------------------------------------------------*/ -/** - * Routine to generate the ACPI C-State objects - * - * @param[in] IoCstateServices IO Cstate services. - * @param[in] LocalApicId Local Apic Id - * @param[in, out] PstateAcpiBufferPtr Pointer to Pstate data buffer. - * @param[in] StdHeader Config Handle for library, services. - * - */ -VOID -STATIC -F12CreateAcpiCstObj ( - IN IO_CSTATE_FAMILY_SERVICES *IoCstateServices, - IN UINT8 LocalApicId, - IN OUT VOID **PstateAcpiBufferPtr, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - UINT64 MsrData; - CST_HEADER_STRUCT *CstHeaderPtr; - CST_BODY_STRUCT *CstBodyPtr; - - // Read from MSR C0010073 to obtain CstateAddr - LibAmdMsrRead (MSR_CSTATE_ADDRESS, &MsrData, StdHeader); - ASSERT ((((CSTATE_ADDRESS_MSR *) &MsrData)->CstateAddr != 0) && - (((CSTATE_ADDRESS_MSR *) &MsrData)->CstateAddr <= 0xFFF8)); - - // Typecast the pointer - CstHeaderPtr = (CST_HEADER_STRUCT *) *PstateAcpiBufferPtr; - - // Set CST Header - CstHeaderPtr->NameOpcode = NAME_OPCODE; - CstHeaderPtr->CstName_a__ = CST_NAME__; - CstHeaderPtr->CstName_a_C = CST_NAME_C; - CstHeaderPtr->CstName_a_S = CST_NAME_S; - CstHeaderPtr->CstName_a_T = CST_NAME_T; - - // Typecast the pointer - CstHeaderPtr++; - CstBodyPtr = (CST_BODY_STRUCT *) CstHeaderPtr; - - // Set CST Body - CstBodyPtr->PkgOpcode = PACKAGE_OPCODE; - CstBodyPtr->PkgLength = CST_LENGTH; - CstBodyPtr->PkgElements = CST_NUM_OF_ELEMENTS; - CstBodyPtr->BytePrefix = BYTE_PREFIX_OPCODE; - CstBodyPtr->Count = CST_COUNT; - CstBodyPtr->PkgOpcode2 = PACKAGE_OPCODE; - CstBodyPtr->PkgLength2 = CST_PKG_LENGTH; - CstBodyPtr->PkgElements2 = CST_PKG_ELEMENTS; - CstBodyPtr->BufferOpcode = BUFFER_OPCODE; - CstBodyPtr->BufferLength = CST_SUBPKG_LENGTH; - CstBodyPtr->BufferElements = CST_SUBPKG_ELEMENTS; - CstBodyPtr->BufferOpcode2 = BUFFER_OPCODE; - CstBodyPtr->GdrOpcode = GENERIC_REG_DESCRIPTION; - CstBodyPtr->GdrLength = CST_GDR_LENGTH; - CstBodyPtr->AddrSpaceId = GDR_ASI_SYSTEM_IO; - CstBodyPtr->RegBitWidth = 0x08; - CstBodyPtr->RegBitOffset = 0x00; - CstBodyPtr->AddressSize = GDR_ASZ_BYTE_ACCESS; - CstBodyPtr->RegisterAddr = ((CSTATE_ADDRESS_MSR *) &MsrData)->CstateAddr + 1; - CstBodyPtr->EndTag = 0x0079; - CstBodyPtr->BytePrefix2 = BYTE_PREFIX_OPCODE; - CstBodyPtr->Type = CST_C2_TYPE; - CstBodyPtr->WordPrefix = WORD_PREFIX_OPCODE; - CstBodyPtr->Latency = 0x64; - CstBodyPtr->DWordPrefix = DWORD_PREFIX_OPCODE; - CstBodyPtr->Power = 0; - - CstBodyPtr++; - - //Update the pointer - *PstateAcpiBufferPtr = CstBodyPtr; -} - -CONST IO_CSTATE_FAMILY_SERVICES ROMDATA F12IoCstateSupport = -{ - 0, - (PF_IO_CSTATE_IS_SUPPORTED) CommonReturnTrue, - F12InitializeIoCstate, - F12GetAcpiCstObj, - F12CreateAcpiCstObj, - (PF_IO_CSTATE_IS_CSD_GENERATED) CommonReturnFalse -}; - diff --git a/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x12/F12MicrocodePatch03000002.c b/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x12/F12MicrocodePatch03000002.c deleted file mode 100644 index 3c72d59d34..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x12/F12MicrocodePatch03000002.c +++ /dev/null @@ -1,195 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * AMD Family_12 Microcode patch. - * - * Fam12 Microcode Patch rev 03000002 for 1200 or equivalent. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: CPU/FAMILY/0x12 - * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $ - * - */ -/* - ****************************************************************************** - * - * Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - ****************************************************************************** - */ -/*---------------------------------------------------------------------------------------- - * M O D U L E S U S E D - *---------------------------------------------------------------------------------------- - */ -#include "AGESA.h" -#include "cpuRegisters.h" -#include "cpuEarlyInit.h" - -/*---------------------------------------------------------------------------------------- - * D E F I N I T I O N S A N D M A C R O S - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------- - * T Y P E D E F S A N D S T R U C T U R E S - *---------------------------------------------------------------------------------------- - */ - -// Patch code 03000002 for 1200 and equivalent -CONST MICROCODE_PATCHES ROMDATA CpuF12MicrocodePatch03000002 = -{{ - 0x10, 0x20, 0x24, 0x03, 0x02, 0x00, 0x00, 0x03, - 0x03, 0x80, 0x20, 0x00, 0x49, 0xb8, 0x03, 0x43, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x12, 0x00, 0x00, 0x00, 0xaa, 0xaa, 0xaa, - 0x6d, 0x10, 0xd8, 0x0b, 0x51, 0x0a, 0x38, 0x29, - 0xff, 0xff, 0x72, 0x0a, 0xfc, 0x03, 0xa7, 0x7c, - 0xff, 0xff, 0xb8, 0x1c, 0xff, 0xff, 0x59, 0x6b, - 0xff, 0xff, 0xf9, 0xa9, 0xff, 0xff, 0xc8, 0x1a, - 0x6f, 0x58, 0x39, 0x00, 0x81, 0x3f, 0xa0, 0xd7, - 0xfc, 0xff, 0xff, 0x03, 0x0f, 0xef, 0x58, 0xc8, - 0xf0, 0xfe, 0xff, 0x4f, 0x3a, 0xfc, 0x31, 0xe8, - 0xc0, 0x87, 0x93, 0x01, 0x80, 0xff, 0xc0, 0x3f, - 0xbf, 0xe1, 0x1f, 0xc0, 0x00, 0xfe, 0x03, 0xff, - 0xff, 0x86, 0x7f, 0x00, 0x03, 0xf8, 0x0f, 0xfc, - 0xfc, 0x1b, 0xfe, 0x01, 0x00, 0xe0, 0xff, 0xf7, - 0xbf, 0x4b, 0xff, 0xff, 0xf0, 0xf3, 0xf0, 0x0f, - 0x38, 0x00, 0x4f, 0xdb, 0xa0, 0xd7, 0x81, 0x3f, - 0xeb, 0x01, 0xfc, 0x77, 0x5a, 0x3e, 0x0f, 0xfd, - 0x69, 0x00, 0x70, 0x41, 0xfd, 0xdf, 0x03, 0xdc, - 0x07, 0xf8, 0x79, 0xf8, 0xfa, 0x7f, 0x14, 0xd6, - 0x1f, 0xe0, 0xe7, 0xe1, 0xeb, 0xff, 0x4f, 0x56, - 0x7f, 0x80, 0x9f, 0x87, 0xff, 0x3d, 0x00, 0xe8, - 0x20, 0xf0, 0x6f, 0x82, 0xfc, 0x03, 0xfc, 0x1c, - 0xf9, 0xff, 0xbf, 0xc9, 0xf0, 0xcf, 0x74, 0x7d, - 0xff, 0x3f, 0xff, 0x25, 0xc3, 0xbf, 0xd2, 0xfd, - 0xac, 0x56, 0x19, 0x00, 0xf8, 0x0f, 0xfc, 0x03, - 0x1b, 0xfe, 0x01, 0xfc, 0xe0, 0x3f, 0xf0, 0x0f, - 0x6f, 0xf8, 0x07, 0xf0, 0x80, 0xff, 0xc0, 0x3f, - 0xbf, 0xe1, 0x1f, 0xc0, 0x00, 0xfe, 0x7f, 0x0f, - 0x00, 0x18, 0x60, 0xe5, 0x3e, 0x07, 0xfd, 0x00, - 0xff, 0xf2, 0xfd, 0xff, 0xfc, 0x3c, 0xfc, 0x03, - 0x0e, 0xc0, 0x81, 0x57, 0xe0, 0x73, 0xd0, 0x0f, - 0x06, 0x00, 0xb2, 0x5d, 0xff, 0x00, 0xfe, 0x03, - 0x00, 0xff, 0x86, 0x7f, 0xfc, 0x03, 0xf8, 0x0f, - 0x01, 0xfc, 0x1b, 0xfe, 0xf0, 0x0f, 0xe0, 0x3f, - 0x07, 0xf0, 0x6f, 0xf8, 0xdf, 0x03, 0x80, 0xff, - 0x81, 0x7f, 0x00, 0xff, 0x3f, 0x80, 0x7f, 0xc3, - 0x07, 0xfe, 0x01, 0xfc, 0xff, 0x00, 0xfe, 0x0d, - 0x1f, 0xf8, 0x07, 0xf0, 0xfc, 0x03, 0xf8, 0x37, - 0xff, 0xef, 0x01, 0xc0, 0xff, 0xc0, 0x3f, 0x80, - 0xe1, 0x1f, 0xc0, 0xbf, 0xfe, 0x03, 0xff, 0x00, - 0x86, 0x7f, 0x00, 0xff, 0xf8, 0x0f, 0xfc, 0x03, - 0x1b, 0xfe, 0x01, 0xfc, 0xe0, 0xff, 0xf7, 0x00, - 0xc0, 0x7f, 0xe0, 0x1f, 0xdf, 0xf0, 0x0f, 0xe0, - 0x00, 0xff, 0x81, 0x7f, 0x7f, 0xc3, 0x3f, 0x80, - 0x01, 0xfc, 0x07, 0xfe, 0xfe, 0x0d, 0xff, 0x00, - 0x00, 0xf0, 0xff, 0x7b, 0x0f, 0xe0, 0x3f, 0xf0, - 0xf0, 0x6f, 0xf8, 0x07, 0x3f, 0x80, 0xff, 0xc0, - 0xc0, 0xbf, 0xe1, 0x1f, 0xff, 0x00, 0xfe, 0x03, - 0x00, 0xff, 0x86, 0x7f, 0x3d, 0x00, 0xf8, 0xff, - 0xf8, 0x07, 0xf0, 0x1f, 0x03, 0xf8, 0x37, 0xfc, - 0xe0, 0x1f, 0xc0, 0x7f, 0x0f, 0xe0, 0xdf, 0xf0, - 0x81, 0x7f, 0x00, 0xff, 0x3f, 0x80, 0x7f, 0xc3, - 0xff, 0x1e, 0x00, 0xfc, 0x0f, 0xfc, 0x03, 0xf8, - 0xfe, 0x01, 0xfc, 0x1b, 0x3f, 0xf0, 0x0f, 0xe0, - 0xf8, 0x07, 0xf0, 0x6f, 0xff, 0xc0, 0x3f, 0x80, - 0xe1, 0x1f, 0xc0, 0xbf, 0xfe, 0x7f, 0x0f, 0x00, - 0xfc, 0x07, 0xfe, 0x01, 0x0d, 0xff, 0x00, 0xfe, - 0xf0, 0x1f, 0xf8, 0x07, 0x37, 0xfc, 0x03, 0xf8, - 0xc0, 0x7f, 0xe0, 0x1f, 0xdf, 0xf0, 0x0f, 0xe0, - 0x00, 0xff, 0xbf, 0x07, 0x00, 0xfe, 0x03, 0xff, - 0xff, 0x86, 0x7f, 0x00, 0x03, 0xf8, 0x0f, 0xfc, - 0xfc, 0x1b, 0xfe, 0x01, 0x0f, 0xe0, 0x3f, 0xf0, - 0xf0, 0x6f, 0xf8, 0x07, 0x03, 0x80, 0xff, 0xdf, - 0x7f, 0x00, 0xff, 0x81, 0x80, 0x7f, 0xc3, 0x3f, - 0xfe, 0x01, 0xfc, 0x07, 0x00, 0xfe, 0x0d, 0xff, - 0xf8, 0x07, 0xf0, 0x1f, 0x03, 0xf8, 0x37, 0xfc, - 0xef, 0x01, 0xc0, 0xff, 0xff, 0x7f, 0x16, 0xff, - 0x9f, 0x6b, 0xf1, 0xe0, 0xff, 0xff, 0x5b, 0x98, - 0x7f, 0x80, 0xb3, 0x86, 0xdf, 0xfe, 0x63, 0xf9, - 0xfe, 0xb1, 0x16, 0x0f, 0x98, 0xd6, 0x00, 0x80, - 0x01, 0x56, 0x0e, 0x80, 0xd0, 0x0f, 0xe0, 0x73, - 0xdf, 0xff, 0xff, 0x2c, 0xc3, 0x3f, 0xc0, 0xcf, - 0x1c, 0x60, 0xe5, 0x00, 0x07, 0xfd, 0x00, 0x3e, - 0xc0, 0x3d, 0x6b, 0x00, 0xe0, 0x3f, 0xf0, 0x0f, - 0x6f, 0xf8, 0x07, 0xf0, 0x80, 0xff, 0xc0, 0x3f, - 0xbf, 0xe1, 0x1f, 0xc0, 0x00, 0xfe, 0x03, 0xff, - 0xff, 0x86, 0x7f, 0x00, 0x00, 0xf8, 0xff, 0x3d, - 0x07, 0xf0, 0x1f, 0xf8, 0xf8, 0x37, 0xfc, 0x03, - 0x1f, 0xc0, 0x7f, 0xe0, 0xe0, 0xdf, 0xf0, 0x0f, - 0x7f, 0x00, 0xff, 0x81, 0x80, 0x7f, 0xc3, 0x3f, - 0x1e, 0x00, 0xfc, 0xff, 0xfc, 0x03, 0xf8, 0x0f, - 0x01, 0xfc, 0x1b, 0xfe, 0xf0, 0x0f, 0xe0, 0x3f, - 0x07, 0xf0, 0x6f, 0xf8, 0xc0, 0x3f, 0x80, 0xff, - 0x1f, 0xc0, 0xbf, 0xe1, 0x7f, 0x0f, 0x00, 0xfe, - 0x07, 0xfe, 0x01, 0xfc, 0xff, 0x00, 0xfe, 0x0d, - 0x1f, 0xf8, 0x07, 0xf0, 0xfc, 0x03, 0xf8, 0x37, - 0x7f, 0xe0, 0x1f, 0xc0, 0xf0, 0x0f, 0xe0, 0xdf, - 0xff, 0xbf, 0x07, 0x00, 0xfe, 0x03, 0xff, 0x00, - 0x86, 0x7f, 0x00, 0xff, 0xf8, 0x0f, 0xfc, 0x03, - 0x1b, 0xfe, 0x01, 0xfc, 0xe0, 0x3f, 0xf0, 0x0f, - 0x6f, 0xf8, 0x07, 0xf0, 0x80, 0xff, 0xdf, 0x03, - 0x00, 0xff, 0x81, 0x7f, 0x7f, 0xc3, 0x3f, 0x80, - 0x01, 0xfc, 0x07, 0xfe, 0xfe, 0x0d, 0xff, 0x00, - 0x07, 0xf0, 0x1f, 0xf8, 0xf8, 0x37, 0xfc, 0x03, - 0x01, 0xc0, 0xff, 0xef, 0x3f, 0x80, 0xff, 0xc0, - 0xc0, 0xbf, 0xe1, 0x1f, 0xff, 0x00, 0xfe, 0x03, - 0x00, 0xff, 0x86, 0x7f, 0xfc, 0x03, 0xf8, 0x0f, - 0x01, 0xfc, 0x1b, 0xfe, 0xf7, 0x00, 0xe0, 0xff, - 0xe0, 0x1f, 0xc0, 0x7f, 0x0f, 0xe0, 0xdf, 0xf0, - 0x81, 0x7f, 0x00, 0xff, 0x3f, 0x80, 0x7f, 0xc3, - 0x07, 0xfe, 0x01, 0xfc, 0xff, 0x00, 0xfe, 0x0d, - 0xff, 0x7b, 0x00, 0xf0, 0x3f, 0xf0, 0x0f, 0xe0, - 0xf8, 0x07, 0xf0, 0x6f, 0xff, 0xc0, 0x3f, 0x80, - 0xe1, 0x1f, 0xc0, 0xbf, 0xfe, 0x03, 0xff, 0x00, - 0x86, 0x7f, 0x00, 0xff, 0xf8, 0xff, 0x3d, 0x00, - 0xf0, 0x1f, 0xf8, 0x07, 0x37, 0xfc, 0x03, 0xf8, - 0xc0, 0x7f, 0xe0, 0x1f, 0xdf, 0xf0, 0x0f, 0xe0, - 0x00, 0xff, 0x81, 0x7f, 0x7f, 0xc3, 0x3f, 0x80, - 0x00, 0xfc, 0xff, 0x1e, 0x03, 0xf8, 0x0f, 0xfc, - 0xfc, 0x1b, 0xfe, 0x01, 0x0f, 0xe0, 0x3f, 0xf0, - 0xf0, 0x6f, 0xf8, 0x07, 0x3f, 0x80, 0xff, 0xc0, - 0xc0, 0xbf, 0xe1, 0x1f, 0x0f, 0x00, 0xfe, 0x7f, - 0xfe, 0x01, 0xfc, 0x07, 0x00, 0xfe, 0x0d, 0xff, - 0xf8, 0x07, 0xf0, 0x1f, 0x03, 0xf8, 0x37, 0xfc, - 0xe0, 0x1f, 0xc0, 0x7f, 0x0f, 0xe0, 0xdf, 0xf0, - 0xbf, 0x07, 0x00, 0xff, 0x03, 0xff, 0x00, 0xfe, - 0x7f, 0x00, 0xff, 0x86, 0x0f, 0xfc, 0x03, 0xf8, - 0xfe, 0x01, 0xfc, 0x1b, 0x3f, 0xf0, 0x0f, 0xe0, - 0xf8, 0x07, 0xf0, 0x6f, 0xff, 0xdf, 0x03, 0x80 -}}; - -/*---------------------------------------------------------------------------------------- - * P R O T O T Y P E S O F L O C A L F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------- - * E X P O R T E D F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ diff --git a/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x12/F12MicrocodePatch0300000e.c b/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x12/F12MicrocodePatch0300000e.c deleted file mode 100644 index 3488f856d3..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x12/F12MicrocodePatch0300000e.c +++ /dev/null @@ -1,195 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * AMD Family_12 Microcode patch. - * - * Fam12 Microcode Patch rev 0300000E for 3001 or equivalent. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: CPU/FAMILY/0x12 - * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $ - * - */ -/* - ****************************************************************************** - * - * Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - ****************************************************************************** - */ -/*---------------------------------------------------------------------------------------- - * M O D U L E S U S E D - *---------------------------------------------------------------------------------------- - */ -#include "AGESA.h" -#include "cpuRegisters.h" -#include "cpuEarlyInit.h" - -/*---------------------------------------------------------------------------------------- - * D E F I N I T I O N S A N D M A C R O S - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------- - * T Y P E D E F S A N D S T R U C T U R E S - *---------------------------------------------------------------------------------------- - */ - -// Patch code 0300000E for 3001 and equivalent -CONST MICROCODE_PATCHES ROMDATA CpuF12MicrocodePatch0300000e = -{{ - 0x10, 0x20, 0x04, 0x10, 0x0e, 0x00, 0x00, 0x03, - 0x03, 0x80, 0x20, 0x00, 0xbc, 0x7c, 0x68, 0xfe, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x01, 0x30, 0x00, 0x00, 0x00, 0xaa, 0xaa, 0xaa, - 0x96, 0x0c, 0xc1, 0x47, 0xbd, 0x02, 0x2a, 0x19, - 0xff, 0xff, 0xcd, 0x73, 0xff, 0xff, 0x17, 0xa0, - 0xff, 0xff, 0xb9, 0x5e, 0xff, 0xff, 0x81, 0x4a, - 0xff, 0xff, 0xd0, 0x2a, 0xff, 0xff, 0xfd, 0xa8, - 0xef, 0x98, 0x38, 0x00, 0x03, 0x3e, 0x80, 0xa1, - 0xfc, 0x57, 0xfe, 0x39, 0x0f, 0xfb, 0x1c, 0x2e, - 0xf0, 0xbf, 0xf9, 0xa7, 0x3c, 0xec, 0x73, 0xb8, - 0x40, 0x83, 0xab, 0x01, 0x87, 0xff, 0xca, 0xbf, - 0xe5, 0x61, 0xdf, 0xc3, 0x16, 0xfe, 0x37, 0xff, - 0x97, 0x87, 0x7d, 0x0b, 0x5b, 0xf8, 0xcf, 0xfc, - 0x5c, 0x1e, 0xf6, 0x2d, 0x00, 0xe0, 0xff, 0xf7, - 0x3f, 0xc0, 0x81, 0xff, 0x45, 0xff, 0xf0, 0x2d, - 0xff, 0x28, 0xbb, 0xfc, 0x54, 0x95, 0xc3, 0x2f, - 0xff, 0x03, 0xfc, 0xfd, 0x58, 0xf6, 0x0f, 0xdf, - 0x6a, 0x00, 0xb0, 0xe0, 0xc1, 0x9f, 0x00, 0x3c, - 0x65, 0xa0, 0x75, 0xf8, 0xff, 0x7f, 0x80, 0x7f, - 0xdb, 0xcb, 0xfe, 0xe1, 0x23, 0xfc, 0x09, 0x62, - 0x5f, 0x06, 0x5a, 0x87, 0xbb, 0x35, 0x00, 0x50, - 0x1f, 0xf8, 0x07, 0xf0, 0xfc, 0x03, 0xf8, 0x37, - 0x7f, 0xe0, 0x1f, 0xc0, 0xf0, 0x0f, 0xe0, 0xdf, - 0xff, 0x81, 0x7f, 0x00, 0xc3, 0x3f, 0x80, 0x7f, - 0xfc, 0xff, 0x1e, 0x00, 0xf8, 0x0f, 0xfc, 0x03, - 0x1b, 0xfe, 0x01, 0xfc, 0xe0, 0x3f, 0xf0, 0x0f, - 0x6f, 0xf8, 0x07, 0xf0, 0x80, 0xff, 0xc0, 0x3f, - 0xbf, 0xe1, 0x1f, 0xc0, 0x00, 0xfe, 0x7f, 0x0f, - 0x01, 0xfc, 0x07, 0xfe, 0xfe, 0x0d, 0xff, 0x00, - 0x07, 0xf0, 0x1f, 0xf8, 0xf8, 0x37, 0xfc, 0x03, - 0x1f, 0xc0, 0x7f, 0xe0, 0xe0, 0xdf, 0xf0, 0x0f, - 0x07, 0x00, 0xff, 0xbf, 0xff, 0x00, 0xfe, 0x03, - 0x00, 0xff, 0x86, 0x7f, 0xfc, 0x03, 0xf8, 0x0f, - 0x01, 0xfc, 0x1b, 0xfe, 0xf0, 0x0f, 0xe0, 0x3f, - 0x07, 0xf0, 0x6f, 0xf8, 0xdf, 0x03, 0x80, 0xff, - 0x81, 0x7f, 0x00, 0xff, 0x3f, 0x80, 0x7f, 0xc3, - 0x07, 0xfe, 0x01, 0xfc, 0xff, 0x00, 0xfe, 0x0d, - 0x1f, 0xf8, 0x07, 0xf0, 0xfc, 0x03, 0xf8, 0x37, - 0xff, 0xef, 0x01, 0xc0, 0xff, 0xc0, 0x3f, 0x80, - 0xe1, 0x1f, 0xc0, 0xbf, 0xfe, 0x03, 0xff, 0x00, - 0x86, 0x7f, 0x00, 0xff, 0xf8, 0x0f, 0xfc, 0x03, - 0x1b, 0xfe, 0x01, 0xfc, 0xe0, 0xff, 0xf7, 0x00, - 0xc0, 0x7f, 0xe0, 0x1f, 0xdf, 0xf0, 0x0f, 0xe0, - 0x00, 0xff, 0x81, 0x7f, 0x7f, 0xc3, 0x3f, 0x80, - 0x01, 0xfc, 0x07, 0xfe, 0xfe, 0x0d, 0xff, 0x00, - 0x00, 0xf0, 0xff, 0x7b, 0x0f, 0xe0, 0x3f, 0xf0, - 0xf0, 0x6f, 0xf8, 0x07, 0x3f, 0x80, 0xff, 0xc0, - 0xc0, 0xbf, 0xe1, 0x1f, 0xff, 0x00, 0xfe, 0x03, - 0x00, 0xff, 0x86, 0x7f, 0x3d, 0x00, 0xf8, 0xff, - 0xf8, 0x07, 0xf0, 0x1f, 0x03, 0xf8, 0x37, 0xfc, - 0xe0, 0x1f, 0xc0, 0x7f, 0x0f, 0xe0, 0xdf, 0xf0, - 0x81, 0x7f, 0x00, 0xff, 0x3f, 0x80, 0x7f, 0xc3, - 0xff, 0x1e, 0x00, 0xfc, 0x0f, 0xfc, 0x03, 0xf8, - 0xfe, 0x01, 0xfc, 0x1b, 0x3f, 0xf0, 0x0f, 0xe0, - 0xf8, 0x07, 0xf0, 0x6f, 0xff, 0xc0, 0x3f, 0x80, - 0xe1, 0x1f, 0xc0, 0xbf, 0xfe, 0x7f, 0x0f, 0x00, - 0xfc, 0x07, 0xfe, 0x01, 0x0d, 0xff, 0x00, 0xfe, - 0xf0, 0x1f, 0xf8, 0x07, 0x37, 0xfc, 0x03, 0xf8, - 0xc0, 0x7f, 0xe0, 0x1f, 0xdf, 0xf0, 0x0f, 0xe0, - 0x00, 0xff, 0xbf, 0x07, 0x00, 0xfe, 0x03, 0xff, - 0xff, 0x86, 0x7f, 0x00, 0x03, 0xf8, 0x0f, 0xfc, - 0xfc, 0x1b, 0xfe, 0x01, 0x0f, 0xe0, 0x3f, 0xf0, - 0xf0, 0x6f, 0xf8, 0x07, 0x03, 0x80, 0xff, 0xdf, - 0x7f, 0x00, 0xff, 0x81, 0x80, 0x7f, 0xc3, 0x3f, - 0xfe, 0x01, 0xfc, 0x07, 0x00, 0xfe, 0x0d, 0xff, - 0xf8, 0x07, 0xf0, 0x1f, 0x03, 0xf8, 0x37, 0xfc, - 0xaf, 0x01, 0xc0, 0x3f, 0xc0, 0x3f, 0x80, 0xff, - 0x1f, 0xc0, 0xbf, 0xe1, 0x03, 0xff, 0x00, 0xfe, - 0x7f, 0x00, 0xff, 0x86, 0x0f, 0xfc, 0x03, 0xf8, - 0xfe, 0x01, 0xfc, 0x1b, 0x9f, 0xd7, 0x00, 0xc0, - 0x42, 0x80, 0x3f, 0x41, 0xf0, 0xcb, 0x40, 0xeb, - 0xff, 0x9d, 0x7f, 0x3f, 0xc3, 0xbe, 0x87, 0xdd, - 0xfc, 0x67, 0xfe, 0xf9, 0x0f, 0xfb, 0x16, 0x76, - 0xf0, 0xff, 0x77, 0x00, 0xe0, 0x3f, 0xf0, 0x0f, - 0x6f, 0xf8, 0x07, 0xf0, 0x80, 0xff, 0xc0, 0x3f, - 0xbf, 0xe1, 0x1f, 0xc0, 0x00, 0xfe, 0x17, 0xdf, - 0xb6, 0x83, 0x7f, 0x2f, 0x00, 0xf8, 0xff, 0x3d, - 0x0f, 0xf0, 0xfd, 0xff, 0xd9, 0x3f, 0x7c, 0x7b, - 0x3f, 0xc1, 0xff, 0xff, 0x40, 0xeb, 0xf0, 0xcb, - 0x7f, 0x00, 0xff, 0x81, 0x80, 0x7f, 0xc3, 0x3f, - 0x1e, 0x00, 0xfc, 0xff, 0xff, 0x07, 0x80, 0xf0, - 0xa5, 0xe8, 0x1f, 0xbe, 0xff, 0xdf, 0xc5, 0xff, - 0x05, 0xb8, 0x72, 0xf8, 0x6e, 0x1c, 0xc0, 0xb0, - 0x1f, 0xc0, 0xe7, 0xa1, 0xbe, 0x0c, 0x00, 0xca, - 0x07, 0xfe, 0x01, 0xfc, 0xff, 0x00, 0xfe, 0x0d, - 0x1f, 0xf8, 0x07, 0xf0, 0xfc, 0x03, 0xf8, 0x37, - 0x7f, 0xe0, 0x1f, 0xc0, 0xf0, 0x0f, 0xe0, 0xdf, - 0xff, 0xbf, 0x07, 0x00, 0xfe, 0x03, 0xff, 0x00, - 0x86, 0x7f, 0x00, 0xff, 0xf8, 0x0f, 0xfc, 0x03, - 0x1b, 0xfe, 0x01, 0xfc, 0xe0, 0x3f, 0xf0, 0x0f, - 0x6f, 0xf8, 0x07, 0xf0, 0x80, 0xff, 0xdf, 0x03, - 0x00, 0xff, 0x81, 0x7f, 0x7f, 0xc3, 0x3f, 0x80, - 0x01, 0xfc, 0x07, 0xfe, 0xfe, 0x0d, 0xff, 0x00, - 0x07, 0xf0, 0x1f, 0xf8, 0xf8, 0x37, 0xfc, 0x03, - 0x01, 0xc0, 0xff, 0xef, 0x3f, 0x80, 0xff, 0xc0, - 0xc0, 0xbf, 0xe1, 0x1f, 0xff, 0x00, 0xfe, 0x03, - 0x00, 0xff, 0x86, 0x7f, 0xfc, 0x03, 0xf8, 0x0f, - 0x01, 0xfc, 0x1b, 0xfe, 0xf7, 0x00, 0xe0, 0xff, - 0xe0, 0x1f, 0xc0, 0x7f, 0x0f, 0xe0, 0xdf, 0xf0, - 0x81, 0x7f, 0x00, 0xff, 0x3f, 0x80, 0x7f, 0xc3, - 0x07, 0xfe, 0x01, 0xfc, 0xff, 0x00, 0xfe, 0x0d, - 0xff, 0x7b, 0x00, 0xf0, 0x3f, 0xf0, 0x0f, 0xe0, - 0xf8, 0x07, 0xf0, 0x6f, 0xff, 0xc0, 0x3f, 0x80, - 0xe1, 0x1f, 0xc0, 0xbf, 0xfe, 0x03, 0xff, 0x00, - 0x86, 0x7f, 0x00, 0xff, 0xf8, 0xff, 0x3d, 0x00, - 0xf0, 0x1f, 0xf8, 0x07, 0x37, 0xfc, 0x03, 0xf8, - 0xc0, 0x7f, 0xe0, 0x1f, 0xdf, 0xf0, 0x0f, 0xe0, - 0x00, 0xff, 0x81, 0x7f, 0x7f, 0xc3, 0x3f, 0x80, - 0x00, 0xfc, 0xff, 0x1e, 0x03, 0xf8, 0x0f, 0xfc, - 0xfc, 0x1b, 0xfe, 0x01, 0x0f, 0xe0, 0x3f, 0xf0, - 0xf0, 0x6f, 0xf8, 0x07, 0x3f, 0x80, 0xff, 0xc0, - 0xc0, 0xbf, 0xe1, 0x1f, 0x0f, 0x00, 0xfe, 0x7f, - 0xfe, 0x01, 0xfc, 0x07, 0x00, 0xfe, 0x0d, 0xff, - 0xf8, 0x07, 0xf0, 0x1f, 0x03, 0xf8, 0x37, 0xfc, - 0xe0, 0x1f, 0xc0, 0x7f, 0x0f, 0xe0, 0xdf, 0xf0, - 0xbf, 0x07, 0x00, 0xff, 0x03, 0xff, 0x00, 0xfe, - 0x7f, 0x00, 0xff, 0x86, 0x0f, 0xfc, 0x03, 0xf8, - 0xfe, 0x01, 0xfc, 0x1b, 0x3f, 0xf0, 0x0f, 0xe0, - 0xf8, 0x07, 0xf0, 0x6f, 0xff, 0xdf, 0x03, 0x80 -}}; - -/*---------------------------------------------------------------------------------------- - * P R O T O T Y P E S O F L O C A L F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------- - * E X P O R T E D F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ diff --git a/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x12/F12MicrocodePatch03000027.c b/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x12/F12MicrocodePatch03000027.c deleted file mode 100644 index 456c51a537..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x12/F12MicrocodePatch03000027.c +++ /dev/null @@ -1,195 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * AMD Family_12 Microcode patch. - * - * Fam12 Microcode Patch rev 03000027 for 3010 or equivalent. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: CPU/FAMILY/0x12 - * @e \$Revision: 58717 $ @e \$Date: 2011-09-13 23:20:11 +0800 (Tue, 13 Sep 2011) $ - * - */ -/* - ****************************************************************************** - * - * Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - ****************************************************************************** - */ -/*---------------------------------------------------------------------------------------- - * M O D U L E S U S E D - *---------------------------------------------------------------------------------------- - */ -#include "AGESA.h" -#include "cpuRegisters.h" -#include "cpuEarlyInit.h" - -/*---------------------------------------------------------------------------------------- - * D E F I N I T I O N S A N D M A C R O S - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------- - * T Y P E D E F S A N D S T R U C T U R E S - *---------------------------------------------------------------------------------------- - */ - -// Patch code 03000027 for 3010 and equivalent -CONST MICROCODE_PATCHES ROMDATA CpuF12MicrocodePatch03000027 = -{{ - 0x11, 0x20, 0x09, 0x13, 0x27, 0x00, 0x00, 0x03, - 0x03, 0x80, 0x20, 0x00, 0x40, 0x00, 0x4f, 0x10, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x10, 0x30, 0x00, 0x00, 0x00, 0xaa, 0xaa, 0xaa, - 0xbd, 0x02, 0x19, 0xe3, 0x99, 0x0c, 0x06, 0x98, - 0x8a, 0x0f, 0x7b, 0x68, 0xc6, 0x11, 0x45, 0xd0, - 0x8c, 0x0e, 0x45, 0x3c, 0xff, 0xff, 0x29, 0xee, - 0xff, 0xff, 0x66, 0xdd, 0xff, 0xff, 0x53, 0x89, - 0x04, 0xfe, 0xff, 0x00, 0xc3, 0xb7, 0x14, 0xfd, - 0xec, 0xf2, 0xff, 0xa3, 0x0e, 0xbf, 0x50, 0x55, - 0xf0, 0xf7, 0xff, 0x0f, 0x3f, 0x7c, 0x63, 0xd9, - 0x80, 0x83, 0xab, 0x01, 0x02, 0x87, 0x04, 0x7f, - 0xd6, 0xe1, 0x97, 0x81, 0x01, 0xfe, 0xfd, 0xff, - 0xfb, 0x87, 0x6f, 0x2f, 0x27, 0x78, 0x8d, 0xf0, - 0x68, 0x1d, 0x7e, 0x19, 0x00, 0x40, 0xed, 0xd6, - 0x0e, 0xc0, 0x3b, 0x26, 0x60, 0xe8, 0x80, 0x0f, - 0x7f, 0x0e, 0xff, 0x95, 0x87, 0xcb, 0xc3, 0x3e, - 0xfe, 0x29, 0xfc, 0x6f, 0x1c, 0x2e, 0x0f, 0xfb, - 0x6a, 0x00, 0xc0, 0xe0, 0xf2, 0xef, 0xe1, 0xbf, - 0xf7, 0x70, 0x79, 0xd8, 0xcd, 0xbf, 0x85, 0xff, - 0xdf, 0xc2, 0xe5, 0x61, 0x33, 0xff, 0x16, 0xfe, - 0x7d, 0x0b, 0x97, 0x87, 0xff, 0x3d, 0x00, 0xf8, - 0xb4, 0x8d, 0x03, 0xf0, 0xf8, 0x03, 0x02, 0x1c, - 0xfa, 0xb4, 0x0e, 0xc0, 0xe0, 0xaf, 0x0d, 0xf0, - 0xff, 0x81, 0x7f, 0x00, 0xc3, 0x3f, 0x80, 0x7f, - 0x28, 0xb8, 0x1a, 0x00, 0xa0, 0xcf, 0xca, 0x01, - 0x0e, 0xfc, 0x01, 0xbd, 0xe0, 0x3f, 0xf0, 0x0f, - 0x6f, 0xf8, 0x07, 0xf0, 0x80, 0xff, 0xc0, 0x3f, - 0xbf, 0xe1, 0x1f, 0xc0, 0x00, 0xfe, 0x7f, 0x07, - 0xb7, 0x3c, 0xf8, 0xff, 0x3f, 0x0f, 0xff, 0x00, - 0x0f, 0x90, 0xfa, 0xff, 0xd1, 0x3f, 0x1c, 0x73, - 0x3f, 0xcb, 0xea, 0xff, 0x55, 0xff, 0xf0, 0xcf, - 0x06, 0x00, 0x36, 0xae, 0xfc, 0x09, 0xae, 0x23, - 0x06, 0x59, 0x87, 0x3f, 0xff, 0x07, 0x38, 0xfd, - 0xb9, 0xe8, 0x1f, 0x8e, 0xf0, 0x0f, 0xe0, 0x3f, - 0x07, 0xf0, 0x6f, 0xf8, 0x57, 0x03, 0x80, 0x1a, - 0x02, 0xff, 0x29, 0x03, 0x3f, 0xc0, 0xcf, 0xc3, - 0xff, 0xff, 0xa7, 0x9c, 0xff, 0x52, 0xd7, 0x07, - 0xff, 0xdf, 0x97, 0xfa, 0xf8, 0x7b, 0x7b, 0x1d, - 0x84, 0xab, 0x01, 0x40, 0x05, 0x6e, 0x1c, 0x80, - 0xc1, 0x1f, 0x10, 0xe0, 0xfe, 0x03, 0xff, 0x4a, - 0x87, 0x7f, 0x80, 0xcf, 0x09, 0xff, 0xff, 0x6f, - 0x1a, 0xfe, 0x01, 0xce, 0xe0, 0xff, 0xf7, 0x00, - 0xc0, 0x7f, 0xe0, 0x1f, 0xdf, 0xf0, 0x0f, 0xe0, - 0x00, 0xff, 0x81, 0x7f, 0x7f, 0xc3, 0x3f, 0x80, - 0x01, 0xfc, 0x07, 0xfe, 0xfe, 0x0d, 0xff, 0x00, - 0x00, 0xf0, 0xff, 0x7b, 0x0f, 0xe0, 0x3f, 0xf0, - 0xf0, 0x6f, 0xf8, 0x07, 0x3f, 0x80, 0xff, 0xc0, - 0xc0, 0xbf, 0xe1, 0x1f, 0xff, 0x00, 0xfe, 0x03, - 0x00, 0xff, 0x86, 0x7f, 0x3d, 0x00, 0xf8, 0xff, - 0xf8, 0x07, 0xf0, 0x1f, 0x03, 0xf8, 0x37, 0xfc, - 0xe0, 0x1f, 0xc0, 0x7f, 0x0f, 0xe0, 0xdf, 0xf0, - 0x81, 0x7f, 0x00, 0xff, 0x3f, 0x80, 0x7f, 0xc3, - 0xff, 0x1e, 0x00, 0xfc, 0x0f, 0xfc, 0x03, 0xf8, - 0xfe, 0x01, 0xfc, 0x1b, 0x3f, 0xf0, 0x0f, 0xe0, - 0xf8, 0x07, 0xf0, 0x6f, 0xff, 0xc0, 0x3f, 0x80, - 0xe1, 0x1f, 0xc0, 0xbf, 0xfe, 0x7f, 0x0f, 0x00, - 0xfe, 0x7f, 0xff, 0xad, 0x0f, 0xff, 0x5a, 0x3f, - 0xfa, 0xbf, 0xfc, 0xd7, 0x3c, 0xfc, 0x6b, 0xfd, - 0xcb, 0xff, 0xf6, 0x9f, 0xff, 0xf0, 0xcf, 0x75, - 0x00, 0xff, 0xbf, 0x07, 0x00, 0xfe, 0xbb, 0xff, - 0xfa, 0x87, 0x63, 0x2b, 0x63, 0xfd, 0xff, 0xff, - 0x7e, 0x0e, 0xfe, 0x01, 0x7f, 0xe5, 0xdf, 0xff, - 0xf8, 0x79, 0xf8, 0x07, 0x03, 0x80, 0xdc, 0x5a, - 0xff, 0x04, 0xf5, 0xff, 0x83, 0xad, 0xc3, 0x2f, - 0xfe, 0x01, 0xfc, 0x07, 0x00, 0xfe, 0x0d, 0xff, - 0xf8, 0x07, 0xf0, 0x1f, 0x03, 0xf8, 0x37, 0xfc, - 0xef, 0x01, 0xc0, 0xff, 0xff, 0x7f, 0x80, 0xef, - 0xdb, 0xcb, 0xfe, 0xe1, 0xff, 0xff, 0x09, 0xfe, - 0x5f, 0x06, 0x5a, 0x87, 0x0f, 0xfc, 0x03, 0xf8, - 0xfe, 0x01, 0xfc, 0x1b, 0xff, 0xf7, 0x00, 0xe0, - 0x83, 0xff, 0x3f, 0x40, 0xf0, 0x2d, 0x45, 0xff, - 0xfe, 0xff, 0xff, 0x2e, 0xc3, 0x2f, 0xc0, 0x95, - 0x86, 0x75, 0xe3, 0x00, 0x0f, 0xfd, 0x00, 0x3e, - 0x50, 0xf6, 0x65, 0x00, 0x20, 0x21, 0xc0, 0x9f, - 0x75, 0xf8, 0x65, 0xa0, 0x9f, 0xff, 0xce, 0xbf, - 0xee, 0x61, 0xdf, 0xc3, 0x7c, 0xfe, 0x33, 0xff, - 0xbb, 0x87, 0x7d, 0x0b, 0x00, 0xf8, 0xff, 0x3b, - 0x07, 0xf0, 0x1f, 0xf8, 0xf8, 0x37, 0xfc, 0x03, - 0x1f, 0xc0, 0x7f, 0xe0, 0xe0, 0xdf, 0xf0, 0x0f, - 0x6f, 0x00, 0xff, 0x8b, 0x17, 0xdb, 0xc1, 0xbf, - 0x1e, 0x00, 0xfc, 0xff, 0xca, 0x01, 0xa0, 0xaf, - 0x01, 0xbd, 0x0e, 0xfc, 0xfb, 0x4f, 0xe5, 0x3f, - 0xa7, 0xaa, 0x3f, 0xf8, 0xff, 0x7f, 0x00, 0xc0, - 0x9b, 0x4a, 0xf1, 0xe0, 0x5c, 0x0d, 0x00, 0x14, - 0x57, 0xeb, 0x00, 0xac, 0xfe, 0xda, 0x00, 0x0f, - 0xff, 0xff, 0x4f, 0xf0, 0xfc, 0x32, 0xd0, 0x3a, - 0x7f, 0xe0, 0x1f, 0xc0, 0xf0, 0x0f, 0xe0, 0xdf, - 0xff, 0xbf, 0x03, 0x00, 0xfe, 0xa7, 0xdf, 0x54, - 0x87, 0x7f, 0xaa, 0xfe, 0x58, 0xff, 0xff, 0x07, - 0x1f, 0xde, 0xa9, 0x90, 0x60, 0x02, 0xc0, 0x9f, - 0x75, 0xf8, 0x63, 0xd0, 0x80, 0xff, 0xdf, 0x03, - 0x25, 0xff, 0xdf, 0x7f, 0xe2, 0xc3, 0xbf, 0xd2, - 0x97, 0xfc, 0xdf, 0xff, 0xfd, 0x0f, 0xff, 0x4a, - 0x07, 0xf0, 0xbf, 0xac, 0xf9, 0x3c, 0xf4, 0x5b, - 0x01, 0xc0, 0x1c, 0xac, 0x1c, 0x00, 0x7a, 0xac, - 0xd0, 0xeb, 0xc0, 0x1f, 0xff, 0x5f, 0xfe, 0xfd, - 0xac, 0xc5, 0x83, 0x7f, 0xca, 0x01, 0xa0, 0xf7, - 0x01, 0x7c, 0x0e, 0xfa, 0xf7, 0x00, 0xa0, 0xff, - 0xf6, 0x5f, 0xcb, 0x7f, 0xaf, 0xf4, 0x7b, 0xf0, - 0xdd, 0x7f, 0x00, 0xff, 0xb1, 0x16, 0xfd, 0xc1, - 0xff, 0xff, 0x13, 0xfc, 0x7f, 0x0c, 0xb0, 0x0e, - 0x5b, 0x65, 0x00, 0x90, 0x3f, 0xf0, 0x6f, 0xe5, - 0x38, 0xb6, 0xfa, 0x7c, 0xda, 0x03, 0x7f, 0x82, - 0xe1, 0x97, 0xc1, 0xd6, 0xfe, 0x03, 0xff, 0x00, - 0x86, 0x7f, 0x00, 0xff, 0xf8, 0xff, 0x3d, 0x00, - 0xf2, 0x9f, 0xfd, 0xd7, 0x3c, 0xfc, 0x03, 0xfc, - 0xcb, 0xef, 0xff, 0xbf, 0x7f, 0xf0, 0x8f, 0xf5, - 0x29, 0xff, 0xd9, 0x7d, 0xd7, 0x83, 0xbf, 0xb7, - 0x00, 0xfc, 0xff, 0x1e, 0xfb, 0xfd, 0xcf, 0xfe, - 0x7e, 0x0e, 0xfe, 0xfd, 0x0f, 0xe0, 0x7f, 0xfb, - 0xa2, 0x3f, 0x38, 0xc6, 0x7f, 0x82, 0x01, 0x00, - 0x41, 0xd7, 0xe1, 0x8f, 0x0d, 0x00, 0x72, 0x6b, - 0xf8, 0x13, 0x0c, 0x00, 0x0c, 0xb6, 0x0e, 0xbf, - 0xfd, 0x07, 0xf0, 0xdf, 0x63, 0xd1, 0x1f, 0x1c, - 0x80, 0x3f, 0xc1, 0x00, 0xc7, 0x00, 0xeb, 0xf0, - 0xbf, 0x07, 0x00, 0xff, 0x03, 0xff, 0x00, 0xfe, - 0x7f, 0x00, 0xff, 0x86, 0x0f, 0xfc, 0x03, 0xf8, - 0xfe, 0x01, 0xfc, 0x1b, 0x3f, 0xf0, 0x0f, 0xe0, - 0xf8, 0x07, 0xf0, 0x6f, 0xff, 0xdf, 0x03, 0x80 -}}; - -/*---------------------------------------------------------------------------------------- - * P R O T O T Y P E S O F L O C A L F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------- - * E X P O R T E D F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ diff --git a/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x12/F12PackageType.h b/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x12/F12PackageType.h deleted file mode 100644 index 098bbe0b4b..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x12/F12PackageType.h +++ /dev/null @@ -1,75 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * AMD Family_12 Package Type Definitions - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: CPU/F12 - * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $ - * - */ -/* - ****************************************************************************** - * - * Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - ****************************************************************************** - */ - -#ifndef _F12_PACKAGE_TYPE_H_ -#define _F12_PACKAGE_TYPE_H_ - - -/*--------------------------------------------------------------------------------------- - * M I X E D (Definitions And Macros / Typedefs, Structures, Enums) - *--------------------------------------------------------------------------------------- - */ - - -/*--------------------------------------------------------------------------------------- - * D E F I N I T I O N S A N D M A C R O S - *--------------------------------------------------------------------------------------- - */ - -// Below equates are defined to cooperate with LibAmdGetPackageType. -#define PACKAGE_TYPE_FP1 (1 << 0) -#define PACKAGE_TYPE_FS1 (1 << 1) -#define PACKAGE_TYPE_FM1 (1 << 2) - - -/*--------------------------------------------------------------------------------------- - * T Y P E D E F S, S T R U C T U R E S, E N U M S - *--------------------------------------------------------------------------------------- - */ - - -/*--------------------------------------------------------------------------------------- - * F U N C T I O N P R O T O T Y P E - *--------------------------------------------------------------------------------------- - */ - -#endif // _F12_PACKAGE_TYPE_H_ diff --git a/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x12/LN/F12LnEquivalenceTable.c b/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x12/LN/F12LnEquivalenceTable.c deleted file mode 100644 index 84edcac571..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x12/LN/F12LnEquivalenceTable.c +++ /dev/null @@ -1,113 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * AMD Family_12 Llano Equivalence Table related data - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: CPU/Family/0x12 - * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $ - * - */ -/* - ****************************************************************************** - * - * Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - ****************************************************************************** - */ - -/*---------------------------------------------------------------------------------------- - * M O D U L E S U S E D - *---------------------------------------------------------------------------------------- - */ -#include "AGESA.h" -#include "cpuFamilyTranslation.h" -#include "Filecode.h" -CODE_GROUP (G1_PEICC) -RDATA_GROUP (G1_PEICC) - -#define FILECODE PROC_CPU_FAMILY_0X12_LN_F12LNEQUIVALENCETABLE_FILECODE - -/*---------------------------------------------------------------------------------------- - * D E F I N I T I O N S A N D M A C R O S - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------- - * T Y P E D E F S A N D S T R U C T U R E S - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------- - * P R O T O T Y P E S O F L O C A L F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ -VOID -GetF12LnMicrocodeEquivalenceTable ( - IN CPU_SPECIFIC_SERVICES *FamilySpecificServices, - OUT CONST VOID **LnEquivalenceTablePtr, - OUT UINT8 *NumberOfElements, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -/*---------------------------------------------------------------------------------------- - * E X P O R T E D F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ - -STATIC CONST UINT16 ROMDATA CpuF12LnMicrocodeEquivalenceTable[] = -{ - 0x3010, 0x3010, - 0x3001, 0x3001, - 0x3000, 0x1200 -}; - - -/*---------------------------------------------------------------------------------------*/ -/** - * Returns the appropriate microcode patch equivalent ID table. - * - * @CpuServiceMethod{::F_CPU_GET_FAMILY_SPECIFIC_ARRAY}. - * - * @param[in] FamilySpecificServices The current Family Specific Services. - * @param[out] LnEquivalenceTablePtr Points to the first entry in the table. - * @param[out] NumberOfElements Number of valid entries in the table. - * @param[in] StdHeader Header for library and services. - * - */ -VOID -GetF12LnMicrocodeEquivalenceTable ( - IN CPU_SPECIFIC_SERVICES *FamilySpecificServices, - OUT CONST VOID **LnEquivalenceTablePtr, - OUT UINT8 *NumberOfElements, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - *NumberOfElements = ((sizeof (CpuF12LnMicrocodeEquivalenceTable) / sizeof (UINT16)) / 2); - *LnEquivalenceTablePtr = CpuF12LnMicrocodeEquivalenceTable; -} - diff --git a/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x12/LN/F12LnLogicalIdTables.c b/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x12/LN/F12LnLogicalIdTables.c deleted file mode 100644 index 4e88e59ead..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x12/LN/F12LnLogicalIdTables.c +++ /dev/null @@ -1,110 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * AMD Family_12 Llano Logical ID Table - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: CPU/FAMILY/0x12 - * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $ - * - */ -/* - ****************************************************************************** - * - * Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - ****************************************************************************** - */ - -/*---------------------------------------------------------------------------------------- - * M O D U L E S U S E D - *---------------------------------------------------------------------------------------- - */ -#include "AGESA.h" -#include "cpuRegisters.h" -#include "Filecode.h" -CODE_GROUP (G1_PEICC) -RDATA_GROUP (G1_PEICC) - -#define FILECODE PROC_CPU_FAMILY_0X12_LN_F12LNLOGICALIDTABLES_FILECODE - -/*---------------------------------------------------------------------------------------- - * D E F I N I T I O N S A N D M A C R O S - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------- - * T Y P E D E F S A N D S T R U C T U R E S - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------- - * P R O T O T Y P E S O F L O C A L F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ -VOID -GetF12LnLogicalIdAndRev ( - OUT CONST CPU_LOGICAL_ID_XLAT **LnIdPtr, - OUT UINT8 *NumberOfElements, - OUT UINT64 *LogicalFamily, - IN OUT AMD_CONFIG_PARAMS *StdHeader - ); - -/*---------------------------------------------------------------------------------------- - * E X P O R T E D F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ - -STATIC CONST CPU_LOGICAL_ID_XLAT ROMDATA CpuF12LnLogicalIdAndRevArray[] = -{ - { - 0x3010, - AMD_F12_LN_B0 - }, - { - 0x3000, - AMD_F12_LN_A0 - }, - { - 0x3001, - AMD_F12_LN_A1 - } -}; - -VOID -GetF12LnLogicalIdAndRev ( - OUT CONST CPU_LOGICAL_ID_XLAT **LnIdPtr, - OUT UINT8 *NumberOfElements, - OUT UINT64 *LogicalFamily, - IN OUT AMD_CONFIG_PARAMS *StdHeader - ) -{ - *NumberOfElements = (sizeof (CpuF12LnLogicalIdAndRevArray) / sizeof (CPU_LOGICAL_ID_XLAT)); - *LnIdPtr = CpuF12LnLogicalIdAndRevArray; - *LogicalFamily = AMD_FAMILY_12_LN; -} - diff --git a/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x12/LN/F12LnMicrocodePatchTables.c b/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x12/LN/F12LnMicrocodePatchTables.c deleted file mode 100644 index 8dc724499b..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x12/LN/F12LnMicrocodePatchTables.c +++ /dev/null @@ -1,111 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * AMD Family_12 Llano PCI tables with values as defined in BKDG - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: CPU/Family/0x10 - * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $ - * - */ -/* - ****************************************************************************** - * - * Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - ****************************************************************************** - */ - -/*---------------------------------------------------------------------------------------- - * M O D U L E S U S E D - *---------------------------------------------------------------------------------------- - */ -#include "AGESA.h" -#include "cpuRegisters.h" -#include "cpuEarlyInit.h" -#include "cpuFamilyTranslation.h" -#include "Filecode.h" -CODE_GROUP (G1_PEICC) -RDATA_GROUP (G1_PEICC) - -#define FILECODE PROC_CPU_FAMILY_0X12_LN_F12LNMICROCODEPATCHTABLES_FILECODE - -/*---------------------------------------------------------------------------------------- - * D E F I N I T I O N S A N D M A C R O S - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------- - * T Y P E D E F S A N D S T R U C T U R E S - *---------------------------------------------------------------------------------------- - */ -extern CONST MICROCODE_PATCHES ROMDATA *CpuF12LnMicroCodePatchArray[]; -extern CONST UINT8 ROMDATA CpuF12LnNumberOfMicrocodePatches; - - -/*---------------------------------------------------------------------------------------- - * P R O T O T Y P E S O F L O C A L F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ -VOID -GetF12LnMicroCodePatchesStruct ( - IN CPU_SPECIFIC_SERVICES *FamilySpecificServices, - OUT CONST VOID **LnUcodePtr, - OUT UINT8 *NumberOfElements, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -/*---------------------------------------------------------------------------------------- - * E X P O R T E D F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ - - -/*---------------------------------------------------------------------------------------*/ -/** - * Returns a table containing the appropriate microcode patches. - * - * @CpuServiceMethod{::F_CPU_GET_FAMILY_SPECIFIC_ARRAY}. - * - * @param[in] FamilySpecificServices The current Family Specific Services. - * @param[out] LnUcodePtr Points to the first entry in the table. - * @param[out] NumberOfElements Number of valid entries in the table. - * @param[in] StdHeader Header for library and services. - * - */ -VOID -GetF12LnMicroCodePatchesStruct ( - IN CPU_SPECIFIC_SERVICES *FamilySpecificServices, - OUT CONST VOID **LnUcodePtr, - OUT UINT8 *NumberOfElements, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - *NumberOfElements = CpuF12LnNumberOfMicrocodePatches; - *LnUcodePtr = &CpuF12LnMicroCodePatchArray[0]; -} - diff --git a/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x12/LN/Makefile.inc b/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x12/LN/Makefile.inc deleted file mode 100644 index b08f0a4499..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x12/LN/Makefile.inc +++ /dev/null @@ -1,3 +0,0 @@ -libagesa-y += F12LnEquivalenceTable.c -libagesa-y += F12LnLogicalIdTables.c -libagesa-y += F12LnMicrocodePatchTables.c diff --git a/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x12/Makefile.inc b/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x12/Makefile.inc deleted file mode 100644 index 72e42f82f8..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x12/Makefile.inc +++ /dev/null @@ -1,23 +0,0 @@ -libagesa-y += F12C6State.c -libagesa-y += F12Cpb.c -libagesa-y += F12IoCstate.c -libagesa-y += F12MicrocodePatch03000002.c -libagesa-y += F12MicrocodePatch0300000e.c -libagesa-y += F12MicrocodePatch03000027.c -libagesa-y += cpuCommonF12Utilities.c -libagesa-y += cpuF12BrandId.c -libagesa-y += cpuF12BrandIdFm1.c -libagesa-y += cpuF12BrandIdFs1.c -libagesa-y += cpuF12CacheDefaults.c -libagesa-y += cpuF12Dmi.c -libagesa-y += cpuF12EarlyNbPstateInit.c -libagesa-y += cpuF12MsrTables.c -libagesa-y += cpuF12PciTables.c -libagesa-y += cpuF12PerCorePciTables.c -libagesa-y += cpuF12PowerCheck.c -libagesa-y += cpuF12PowerMgmtSystemTables.c -libagesa-y += cpuF12PowerPlane.c -libagesa-y += cpuF12Pstate.c -libagesa-y += cpuF12SoftwareThermal.c -libagesa-y += cpuF12Utilities.c -libagesa-y += cpuF12WheaInitDataTables.c diff --git a/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x12/cpuCommonF12Utilities.c b/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x12/cpuCommonF12Utilities.c deleted file mode 100644 index 59fb1d94f4..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x12/cpuCommonF12Utilities.c +++ /dev/null @@ -1,572 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * AMD Family_12 specific utility functions. - * - * Provides numerous utility functions specific to family 12h. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: CPU/FAMILY/0x12 - * @e \$Revision: 49553 $ @e \$Date: 2011-03-25 08:55:17 +0800 (Fri, 25 Mar 2011) $ - * - */ -/* - ***************************************************************************** - * - * Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - ****************************************************************************** - */ - -/*---------------------------------------------------------------------------------------- - * M O D U L E S U S E D - *---------------------------------------------------------------------------------------- - */ -#include "AGESA.h" -#include "amdlib.h" -#include "Ids.h" -#include "cpuRegisters.h" -#include "cpuServices.h" -#include "cpuFamilyTranslation.h" -#include "cpuCommonF12Utilities.h" -#include "cpuF12PowerMgmt.h" -#include "OptionFamily12hEarlySample.h" -#include "NbSmuLib.h" -#include "GnbRegistersLN.h" -#include "F12PackageType.h" -#include "Filecode.h" -CODE_GROUP (G1_PEICC) -RDATA_GROUP (G1_PEICC) - -#define FILECODE PROC_CPU_FAMILY_0X12_CPUCOMMONF12UTILITIES_FILECODE - -/*---------------------------------------------------------------------------------------- - * D E F I N I T I O N S A N D M A C R O S - *---------------------------------------------------------------------------------------- - */ -extern F12_ES_CORE_SUPPORT F12EarlySampleCoreSupport; -#define F12_DDR1333_ENCODED_MEMCLK (0xE) - -/*---------------------------------------------------------------------------------------- - * T Y P E D E F S A N D S T R U C T U R E S - *---------------------------------------------------------------------------------------- - */ -CONST UINT16 ROMDATA F12MaxNbFreqAtMinVidFreqTable[] = -{ - 25, // 00000b - 50, // 00001b - 100, // 00010b - 150, // 00011b - 167, // 00100b - 183, // 00101b - 200, // 00110b - 217, // 00111b - 233, // 01000b - 250, // 01001b - 267, // 01010b - 283, // 01011b - 300, // 01100b - 317, // 01101b - 333, // 01110b - 350, // 01111b - 366, // 10000b - 383, // 10001b - 400, // 10010b - 417, // 10011b - 433, // 10100b - 450, // 10101b - 467, // 10110b - 483, // 10111b - 500, // 11000b - 517, // 11001b - 533, // 11010b - 550, // 11011b - 563, // 11100b - 575, // 11101b - 588, // 11110b - 600 // 11111b -}; - -/*---------------------------------------------------------------------------------------- - * P R O T O T Y P E S O F L O C A L F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ -UINT32 -STATIC -RoundedDivision ( - IN UINT32 Dividend, - IN UINT32 Divisor - ); - -UINT32 -F12GetApCoreNumber ( - IN CPU_SPECIFIC_SERVICES *FamilySpecificServices, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -CORE_ID_POSITION -F12CpuAmdCoreIdPositionInInitialApicId ( - IN CPU_SPECIFIC_SERVICES *FamilySpecificServices, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -/*---------------------------------------------------------------------------------------- - * E X P O R T E D F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------*/ -/** - * Set warm reset status and count - * - * @CpuServiceMethod{::F_CPU_SET_WARM_RESET_FLAG}. - * - * This function will use bit9, and bit 10 of register F0x6C as a warm reset status and count. - * - * @param[in] FamilySpecificServices The current Family Specific Services. - * @param[in] StdHeader Handle of Header for calling lib functions and services. - * @param[in] Request Indicate warm reset status - * - */ -VOID -F12SetAgesaWarmResetFlag ( - IN CPU_SPECIFIC_SERVICES *FamilySpecificServices, - IN AMD_CONFIG_PARAMS *StdHeader, - IN WARM_RESET_REQUEST *Request - ) -{ - PCI_ADDR PciAddress; - UINT32 PciData; - - PciAddress.AddressValue = MAKE_SBDFO (0, 0 , PCI_DEV_BASE, FUNC_0, HT_INIT_CTRL); - LibAmdPciRead (AccessWidth32, PciAddress, &PciData, StdHeader); - - // bit[5] - indicate a warm reset is or is not required - PciData &= ~(HT_INIT_BIOS_RST_DET_0); - PciData = PciData | (Request->RequestBit << 5); - - // bit[10,9] - indicate warm reset status and count - PciData &= ~(HT_INIT_BIOS_RST_DET_1 | HT_INIT_BIOS_RST_DET_2); - PciData |= Request->StateBits << 9; - - LibAmdPciWrite (AccessWidth32, PciAddress, &PciData, StdHeader); -} - -/*---------------------------------------------------------------------------------------*/ -/** - * Get warm reset status and count - * - * @CpuServiceMethod{::F_CPU_GET_WARM_RESET_FLAG}. - * - * This function will bit9, and bit 10 of register F0x6C as a warm reset status and count. - * - * @param[in] FamilySpecificServices The current Family Specific Services. - * @param[in] StdHeader Config handle for library and services - * @param[out] Request Indicate warm reset status - * - */ -VOID -F12GetAgesaWarmResetFlag ( - IN CPU_SPECIFIC_SERVICES *FamilySpecificServices, - IN AMD_CONFIG_PARAMS *StdHeader, - OUT WARM_RESET_REQUEST *Request - ) -{ - PCI_ADDR PciAddress; - UINT32 PciData; - - PciAddress.AddressValue = MAKE_SBDFO (0, 0 , PCI_DEV_BASE, FUNC_0, HT_INIT_CTRL); - LibAmdPciRead (AccessWidth32, PciAddress, &PciData, StdHeader); - - // bit[5] - indicate a warm reset is or is not required - Request->RequestBit = (UINT8) ((PciData & HT_INIT_BIOS_RST_DET_0) >> 5); - // bit[10,9] - indicate warm reset status and count - Request->StateBits = (UINT8) ((PciData & (HT_INIT_BIOS_RST_DET_1 | HT_INIT_BIOS_RST_DET_2)) >> 9); -} - -/*---------------------------------------------------------------------------------------*/ -/** - * Use the Mailbox Register to get the Ap Mailbox info for the current core. - * - * @CpuServiceMethod{::F_CPU_AMD_GET_AP_MAILBOX_FROM_HARDWARE}. - * - * Access the mailbox register used with this NB family. This is valid until the - * point that some init code initializes the mailbox register for its normal use. - * - * @param[in] FamilySpecificServices The current Family Specific Services. - * @param[out] ApMailboxInfo The AP Mailbox info - * @param[in] StdHeader Handle of Header for calling lib functions and services. - * - */ -VOID -F12GetApMailboxFromHardware ( - IN CPU_SPECIFIC_SERVICES *FamilySpecificServices, - OUT AP_MAILBOXES *ApMailboxInfo, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - // For Family 12h, we will return socket 0, node 0, module 0, module type 0, and 0 for - // the system degree - ApMailboxInfo->ApMailInfo.Info = (UINT32) 0x00000000; - ApMailboxInfo->ApMailExtInfo.Info = (UINT32) 0x00000000; -} - - -/*---------------------------------------------------------------------------------------*/ -/** - * Get this AP's system core number from hardware. - * - * @CpuServiceMethod{::F_CPU_GET_AP_CORE_NUMBER}. - * - * Returns the system core number. For family 12h, this is simply the - * initial APIC ID. - * - * @param[in] FamilySpecificServices The current Family Specific Services. - * @param[in] StdHeader Handle of Header for calling lib functions and services. - * - * @return The AP's unique core number - */ -UINT32 -F12GetApCoreNumber ( - IN CPU_SPECIFIC_SERVICES *FamilySpecificServices, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - CPUID_DATA Cpuid; - - LibAmdCpuidRead (0x1, &Cpuid, StdHeader); - return ((Cpuid.EBX_Reg >> 24) & 0xFF); -} - - -/*---------------------------------------------------------------------------------------*/ -/** - * Return a number zero or one, based on the Core ID position in the initial APIC Id. - * - * @CpuServiceMethod{::F_CORE_ID_POSITION_IN_INITIAL_APIC_ID}. - * - * @param[in] FamilySpecificServices The current Family Specific Services. - * @param[in] StdHeader Handle of Header for calling lib functions and services. - * - * @retval CoreIdPositionZero Core Id is not low - * @retval CoreIdPositionOne Core Id is low - */ -CORE_ID_POSITION -F12CpuAmdCoreIdPositionInInitialApicId ( - IN CPU_SPECIFIC_SERVICES *FamilySpecificServices, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - return (CoreIdPositionOne); -} - -/*---------------------------------------------------------------------------------------*/ -/** - * Sets up a valid set of NB P-states based on the value of MEMCLK, transitions - * to the desired NB P-state, and returns the current NB frequency in megahertz. - * - * @param[in] TargetMemclk The target MEMCLK in megahertz, or zero to - * indicate NB P-state change only. - * @param[in] TargetMemclkEncoded The target MEMCLK's register encoding. - * @param[in] TargetNbPstate The NB P-state to exit in. - * @param[out] CurrentNbFreq Current NB operating frequency in megahertz. - * @param[in] StdHeader Handle of Header for calling lib functions and services. - * - * @retval TRUE Transition to TargetNbPstate was successful. - * @retval FALSE Transition to TargetNbPstate was unsuccessful. - */ -BOOLEAN -F12NbPstateInit ( - IN UINT32 TargetMemclk, - IN UINT32 TargetMemclkEncoded, - IN UINT32 TargetNbPstate, - OUT UINT32 *CurrentNbFreq, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - UINT32 EncodedNbPs1Vid; - UINT32 EncodedNbPs0NclkDiv; - UINT32 EncodedNbPs1NclkDiv; - UINT32 NbP0Cof; - UINT32 NbP1Cof; - UINT32 NbPstateNumerator; - UINT32 TargetNumerator; - UINT32 TargetDenominator; - UINT32 PkgType; - BOOLEAN ReturnStatus; - BOOLEAN WaitForTransition; - BOOLEAN EnableAltVddNb; - PCI_ADDR PciAddress; - D18F3xD4_STRUCT Cptc0; - D18F3xDC_STRUCT Cptc2; - D18F6x90_STRUCT NbPsCfgLow; - D18F6x98_STRUCT NbPsCtrlSts; - FCRxFE00_6000_STRUCT FCRxFE00_6000; - FCRxFE00_6002_STRUCT FCRxFE00_6002; - FCRxFE00_7006_STRUCT FCRxFE00_7006; - FCRxFE00_7009_STRUCT FCRxFE00_7009; - FCRxFE00_705F_STRUCT FCRxFE00_705F; - - // F12 only supports NB P0 and NB P1 - ASSERT (TargetNbPstate < 2); - - WaitForTransition = FALSE; - ReturnStatus = TRUE; - EnableAltVddNb = FALSE; - - // Get D18F3xD4[MainPllOpFreqId] frequency - PciAddress.AddressValue = CPTC0_PCI_ADDR; - LibAmdPciRead (AccessWidth32, PciAddress, &Cptc0.Value, StdHeader); - - // Calculate the numerator to be used for NB P-state calculations - NbPstateNumerator = (UINT32) (4 * ((Cptc0.Field.MainPllOpFreqId + 0x10) * 100)); - - if (TargetMemclk != 0) { - // Determine the appropriate numerator / denominator of the target memclk - switch (TargetMemclk) { - case DDR800_FREQUENCY: - TargetNumerator = 400; - TargetDenominator = 1; - break; - case DDR1066_FREQUENCY: - TargetNumerator = 1600; - TargetDenominator = 3; - break; - case DDR1333_FREQUENCY: - TargetNumerator = 2000; - TargetDenominator = 3; - break; - case DDR1600_FREQUENCY: - TargetNumerator = 800; - TargetDenominator = 1; - break; - case DDR1866_FREQUENCY: - TargetNumerator = 2800; - TargetDenominator = 3; - break; - default: - // An invalid memclk has been passed in. - ASSERT (FALSE); - TargetNumerator = TargetMemclk; - TargetDenominator = 1; - break; - } - - FCRxFE00_6000.Value = NbSmuReadEfuse (FCRxFE00_6000_ADDRESS, StdHeader); - FCRxFE00_6002.Value = NbSmuReadEfuse (FCRxFE00_6002_ADDRESS, StdHeader); - FCRxFE00_7006.Value = NbSmuReadEfuse (FCRxFE00_7006_ADDRESS, StdHeader); - FCRxFE00_7009.Value = NbSmuReadEfuse (FCRxFE00_7009_ADDRESS, StdHeader); - - F12EarlySampleCoreSupport.F12NbPstateInitHook (&FCRxFE00_6000, - &FCRxFE00_6002, - &FCRxFE00_7006, - &FCRxFE00_7009, - NbPstateNumerator, - StdHeader); - - // Determine NB P0 settings - if ((TargetNumerator * FCRxFE00_7009.Field.NbPs0NclkDiv) < (NbPstateNumerator * TargetDenominator)) { - // Program D18F3xDC[NbPs0NclkDiv] to the minimum divisor where - // (target memclk frequency >= (D18F3xD4[MainPllOpFreqId] freq) / divisor) - EncodedNbPs0NclkDiv = ((NbPstateNumerator * TargetDenominator) / TargetNumerator); - if (((NbPstateNumerator * TargetDenominator) % TargetNumerator) != 0) { - EncodedNbPs0NclkDiv++; - } - // Ensure that the encoded divisor is even to give 50% duty cycle - EncodedNbPs0NclkDiv = ((EncodedNbPs0NclkDiv + 1) & 0xFFFFFFFE); - - ASSERT (EncodedNbPs0NclkDiv >= 8); - ASSERT (EncodedNbPs0NclkDiv <= 0x3F); - } else { - EncodedNbPs0NclkDiv = FCRxFE00_7009.Field.NbPs0NclkDiv; - } - - // Check to see if the DIMMs are too fast for the CPU (NB P0 COF < (Memclk / 2)) - if ((TargetNumerator * EncodedNbPs0NclkDiv) > (NbPstateNumerator * TargetDenominator * 2)) { - // Indicate the error to the memory code so the DIMMs can be derated. - ReturnStatus = FALSE; - } - - // Apply the appropriate P0 frequency - PciAddress.AddressValue = CPTC2_PCI_ADDR; - LibAmdPciRead (AccessWidth32, PciAddress, &Cptc2.Value, StdHeader); - if (Cptc2.Field.NbPs0NclkDiv != EncodedNbPs0NclkDiv) { - WaitForTransition = TRUE; - Cptc2.Field.NbPs0NclkDiv = EncodedNbPs0NclkDiv; - LibAmdPciWrite (AccessWidth32, PciAddress, &Cptc2.Value, StdHeader); - } - NbP0Cof = RoundedDivision (NbPstateNumerator, EncodedNbPs0NclkDiv); - - // Determine NB P1 settings if necessary - PciAddress.AddressValue = NB_PSTATE_CFG_LOW_PCI_ADDR; - LibAmdPciRead (AccessWidth32, PciAddress, &NbPsCfgLow.Value, StdHeader); - if (NbPsCfgLow.Field.NbPsCap == 1) { - if ((TargetNumerator * FCRxFE00_7006.Field.NbPs1NclkDiv) > (NbPstateNumerator * TargetDenominator * 2)) { - // Program D18F6x90[NbPs1NclkDiv] to the maximum divisor where - // (target memclk frequency / 2 <= (D18F3xD4[MainPllOpFreqId] freq) / divisor) - EncodedNbPs1NclkDiv = ((NbPstateNumerator * TargetDenominator * 2) / TargetNumerator); - - // Ensure that the encoded divisor is even to give 50% duty cycle - EncodedNbPs1NclkDiv &= 0xFFFFFFFE; - ASSERT (EncodedNbPs1NclkDiv >= 8); - ASSERT (EncodedNbPs1NclkDiv <= 0x3F); - - // Calculate the new effective P1 frequency to determine the voltage - NbP1Cof = RoundedDivision (NbPstateNumerator, EncodedNbPs1NclkDiv); - - if (NbP1Cof <= F12MaxNbFreqAtMinVidFreqTable[FCRxFE00_7006.Field.MaxNbFreqAtMinVid]) { - // Program D18F6x90[NbPs1Vid] = FCRxFE00_6002[NbPs1VidAddl] - EncodedNbPs1Vid = FCRxFE00_6002.Field.NbPs1VidAddl; - } else { - // Program D18F6x90[NbPs1Vid] = FCRxFE00_6002[NbPs1VidHigh] - EncodedNbPs1Vid = FCRxFE00_6002.Field.NbPs1VidHigh; - } - } else { - // Fused frequency and voltage are legal - EncodedNbPs1Vid = FCRxFE00_6000.Field.NbPs1Vid; - EncodedNbPs1NclkDiv = FCRxFE00_7006.Field.NbPs1NclkDiv; - NbP1Cof = RoundedDivision (NbPstateNumerator, EncodedNbPs1NclkDiv); - } - - if (NbP0Cof < NbP1Cof) { - // NB P1 frequency is faster than NB P0. Fix it up by slowing - // P1 to match P0. - EncodedNbPs1NclkDiv = EncodedNbPs0NclkDiv; - NbP1Cof = NbP0Cof; - } - - // Program the new NB P1 settings - NbPsCfgLow.Field.NbPs1NclkDiv = EncodedNbPs1NclkDiv; - NbPsCfgLow.Field.NbPs1Vid = EncodedNbPs1Vid; - LibAmdPciWrite (AccessWidth32, PciAddress, &NbPsCfgLow.Value, StdHeader); - } else { - // NB P-states are not enabled - NbP1Cof = 0; - } - *CurrentNbFreq = NbP0Cof; - if (WaitForTransition) { - // Ensure that the frequency has settled before returning to memory code. - PciAddress.AddressValue = CPTC2_PCI_ADDR; - do { - LibAmdPciRead (AccessWidth32, PciAddress, &Cptc2.Value, StdHeader); - } while (Cptc2.Field.NclkFreqDone != 1); - } - } else { - // Get NB P0 COF - PciAddress.AddressValue = CPTC2_PCI_ADDR; - LibAmdPciRead (AccessWidth32, PciAddress, &Cptc2.Value, StdHeader); - NbP0Cof = RoundedDivision (NbPstateNumerator, Cptc2.Field.NbPs0NclkDiv); - - // Read NB P-state status - PciAddress.AddressValue = NB_PSTATE_CTRL_STS_PCI_ADDR; - LibAmdPciRead (AccessWidth32, PciAddress, &NbPsCtrlSts.Value, StdHeader); - - FCRxFE00_705F.Value = NbSmuReadEfuse (FCRxFE00_705F_ADDRESS, StdHeader); - if (FCRxFE00_705F.Field.GnbIdleAdjustVid != 0) { - PkgType = LibAmdGetPackageType (StdHeader); - if ((PkgType == PACKAGE_TYPE_FP1) || ((PkgType == PACKAGE_TYPE_FS1) && (TargetMemclkEncoded <= F12_DDR1333_ENCODED_MEMCLK))) { - EnableAltVddNb = TRUE; - } - } - - // Read low config register - PciAddress.AddressValue = NB_PSTATE_CFG_LOW_PCI_ADDR; - LibAmdPciRead (AccessWidth32, PciAddress, &NbPsCfgLow.Value, StdHeader); - if (TargetNbPstate == 1) { - // If target is P1, the CPU MUST be in P0, otherwise the P1 settings - // cannot be realized. This is a programming error. - ASSERT (NbPsCtrlSts.Field.NbPs1Act == 0); - - if (NbPsCfgLow.Field.NbPsCap == 1) { - // The part is capable of NB P-states. Transition to P1. - if (EnableAltVddNb) { - NbPsCfgLow.Field.NbPs1Vid += FCRxFE00_705F.Field.GnbIdleAdjustVid; - LibAmdPciWrite (AccessWidth32, PciAddress, &NbPsCfgLow.Value, StdHeader); - } - - NbPsCfgLow.Field.NbPsForceSel = 1; - LibAmdPciWrite (AccessWidth32, PciAddress, &NbPsCfgLow.Value, StdHeader); - - WaitForTransition = TRUE; - *CurrentNbFreq = RoundedDivision (NbPstateNumerator, NbPsCfgLow.Field.NbPs1NclkDiv); - } else { - // No NB P-states. Return FALSE, and set current frequency to P0. - *CurrentNbFreq = NbP0Cof; - ReturnStatus = FALSE; - } - } else { - // Target P0 - *CurrentNbFreq = NbP0Cof; - if (NbPsCtrlSts.Field.NbPs1Act != 0) { - // Request transition to P0 - if (EnableAltVddNb) { - NbPsCfgLow.Field.NbPs1Vid -= FCRxFE00_705F.Field.GnbIdleAdjustVid; - } - NbPsCfgLow.Field.NbPsForceSel = 0; - LibAmdPciWrite (AccessWidth32, PciAddress, &NbPsCfgLow.Value, StdHeader); - WaitForTransition = TRUE; - } - } - if (WaitForTransition) { - // Ensure that the frequency has settled before returning to memory code. - PciAddress.AddressValue = NB_PSTATE_CTRL_STS_PCI_ADDR; - do { - LibAmdPciRead (AccessWidth32, PciAddress, &NbPsCtrlSts.Value, StdHeader); - } while (NbPsCtrlSts.Field.NbPs1Act != TargetNbPstate); - } - } - - return ReturnStatus; -} - -/*---------------------------------------------------------------------------------------*/ -/** - * Performs integer division, and rounds the quotient up if the remainder is greater - * than or equal to 50% of the divisor. - * - * @param[in] Dividend The target MEMCLK in megahertz. - * @param[in] Divisor The target MEMCLK's register encoding. - * - * @return The rounded quotient - */ -UINT32 -STATIC -RoundedDivision ( - IN UINT32 Dividend, - IN UINT32 Divisor - ) -{ - UINT32 Quotient; - - ASSERT (Divisor != 0); - - Quotient = Dividend / Divisor; - if (((Dividend % Divisor) * 2) >= Divisor) { - Quotient++; - } - return Quotient; -} diff --git a/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x12/cpuCommonF12Utilities.h b/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x12/cpuCommonF12Utilities.h deleted file mode 100644 index 8f8f32d289..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x12/cpuCommonF12Utilities.h +++ /dev/null @@ -1,102 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * AMD Family_12 specific utility functions. - * - * Provides numerous utility functions specific to family 12h. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: CPU/FAMILY/0x12 - * @e \$Revision: 49553 $ @e \$Date: 2011-03-25 08:55:17 +0800 (Fri, 25 Mar 2011) $ - * - */ -/* - ****************************************************************************** - * - * Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - ****************************************************************************** - */ - -#ifndef _CPU_COMMON_F12_UTILITES_H_ -#define _CPU_COMMON_F12_UTILITES_H_ - - -/*--------------------------------------------------------------------------------------- - * M I X E D (Definitions And Macros / Typedefs, Structures, Enums) - *--------------------------------------------------------------------------------------- - */ - - -/*--------------------------------------------------------------------------------------- - * D E F I N I T I O N S A N D M A C R O S - *--------------------------------------------------------------------------------------- - */ - - -/*--------------------------------------------------------------------------------------- - * T Y P E D E F S, S T R U C T U R E S, E N U M S - *--------------------------------------------------------------------------------------- - */ - - -/*--------------------------------------------------------------------------------------- - * F U N C T I O N P R O T O T Y P E - *--------------------------------------------------------------------------------------- - */ - -VOID -F12SetAgesaWarmResetFlag ( - IN CPU_SPECIFIC_SERVICES *FamilySpecificServices, - IN AMD_CONFIG_PARAMS *StdHeader, - IN WARM_RESET_REQUEST *Request - ); - -VOID -F12GetAgesaWarmResetFlag ( - IN CPU_SPECIFIC_SERVICES *FamilySpecificServices, - IN AMD_CONFIG_PARAMS *StdHeader, - OUT WARM_RESET_REQUEST *Request - ); - -VOID -F12GetApMailboxFromHardware ( - IN CPU_SPECIFIC_SERVICES *FamilySpecificServices, - OUT AP_MAILBOXES *ApMailboxInfo, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -BOOLEAN -F12NbPstateInit ( - IN UINT32 TargetMemclk, - IN UINT32 TargetMemclkEncoded, - IN UINT32 TargetNbPstate, - OUT UINT32 *CurrentNbFreq, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -#endif // _CPU_COMMON_F12_UTILITES_H_ diff --git a/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x12/cpuF12BrandId.c b/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x12/cpuF12BrandId.c deleted file mode 100644 index 5184d2383c..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x12/cpuF12BrandId.c +++ /dev/null @@ -1,157 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * AMD CPU BrandId related functions and structures. - * - * Contains code that provides CPU BrandId information - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: CPU - * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $ - * - */ -/* - ****************************************************************************** - * - * Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - ****************************************************************************** - */ - -/*---------------------------------------------------------------------------------------- - * M O D U L E S U S E D - *---------------------------------------------------------------------------------------- - */ -#include "AGESA.h" -#include "cpuRegisters.h" -#include "cpuEarlyInit.h" -#include "cpuFamilyTranslation.h" -#include "Filecode.h" -CODE_GROUP (G1_PEICC) -RDATA_GROUP (G1_PEICC) - -#define FILECODE PROC_CPU_FAMILY_0X12_CPUF12BRANDID_FILECODE - -/*---------------------------------------------------------------------------------------- - * D E F I N I T I O N S A N D M A C R O S - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------- - * T Y P E D E F S A N D S T R U C T U R E S - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------- - * P R O T O T Y P E S O F L O C A L F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------- - * E X P O R T E D F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ -extern CPU_BRAND_TABLE *F12BrandIdString1Tables[]; -extern CPU_BRAND_TABLE *F12BrandIdString2Tables[]; -extern CONST UINT8 F12BrandIdString1TableCount; -extern CONST UINT8 F12BrandIdString2TableCount; - -/*--------------------------------------------------------------------------------------- - * T Y P E D E F S, S T R U C T U R E S, E N U M S - *--------------------------------------------------------------------------------------- - */ -VOID -GetF12BrandIdString1 ( - IN CPU_SPECIFIC_SERVICES *FamilySpecificServices, - OUT CONST VOID **BrandString1Ptr, - OUT UINT8 *NumberOfElements, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -VOID -GetF12BrandIdString2 ( - IN CPU_SPECIFIC_SERVICES *FamilySpecificServices, - OUT CONST VOID **BrandString2Ptr, - OUT UINT8 *NumberOfElements, - IN AMD_CONFIG_PARAMS *StdHeader - ); - - - -/*---------------------------------------------------------------------------------------*/ -/** - * Returns a table containing the appropriate beginnings of the CPU brandstring. - * - * @CpuServiceMethod{::F_CPU_GET_FAMILY_SPECIFIC_ARRAY}. - * - * @param[in] FamilySpecificServices The current Family Specific Services. - * @param[out] BrandString1Ptr Points to the first entry in the table. - * @param[out] NumberOfElements Number of valid entries in the table. - * @param[in] StdHeader Header for library and services. - * - */ -VOID -GetF12BrandIdString1 ( - IN CPU_SPECIFIC_SERVICES *FamilySpecificServices, - OUT CONST VOID **BrandString1Ptr, - OUT UINT8 *NumberOfElements, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - CPU_BRAND_TABLE **TableEntryPtr; - - TableEntryPtr = &F12BrandIdString1Tables[0]; - *BrandString1Ptr = TableEntryPtr; - *NumberOfElements = F12BrandIdString1TableCount; -} - -/*---------------------------------------------------------------------------------------*/ -/** - * Returns a table containing the appropriate endings of the CPU brandstring. - * - * @CpuServiceMethod{::F_CPU_GET_FAMILY_SPECIFIC_ARRAY}. - * - * @param[in] FamilySpecificServices The current Family Specific Services. - * @param[out] BrandString2Ptr Points to the first entry in the table. - * @param[out] NumberOfElements Number of valid entries in the table. - * @param[in] StdHeader Header for library and services. - * - */ -VOID -GetF12BrandIdString2 ( - IN CPU_SPECIFIC_SERVICES *FamilySpecificServices, - OUT CONST VOID **BrandString2Ptr, - OUT UINT8 *NumberOfElements, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - CPU_BRAND_TABLE **TableEntryPtr; - - TableEntryPtr = &F12BrandIdString2Tables[0]; - *BrandString2Ptr = TableEntryPtr; - *NumberOfElements = F12BrandIdString2TableCount; -} diff --git a/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x12/cpuF12BrandIdFm1.c b/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x12/cpuF12BrandIdFm1.c deleted file mode 100644 index 8711d68f4b..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x12/cpuF12BrandIdFm1.c +++ /dev/null @@ -1,232 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * AMD CPU BrandId related functions and structures. - * - * Contains code that provides CPU BrandId information - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: CPU/Family/0x12 - * @e \$Revision: 52412 $ @e \$Date: 2011-05-06 08:13:56 +0800 (Fri, 06 May 2011) $ - * - */ -/* - ****************************************************************************** - * - * Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - ****************************************************************************** - */ - -/*---------------------------------------------------------------------------------------- - * M O D U L E S U S E D - *---------------------------------------------------------------------------------------- - */ -#include "AGESA.h" -#include "cpuRegisters.h" -#include "cpuEarlyInit.h" -#include "F12PackageType.h" - -/*---------------------------------------------------------------------------------------- - * D E F I N I T I O N S A N D M A C R O S - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------- - * T Y P E D E F S A N D S T R U C T U R E S - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------- - * P R O T O T Y P E S O F L O C A L F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------- - * E X P O R T E D F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ - -// String1 -CONST CHAR8 ROMDATA str_F12_Fm1_AMD_A4_3[] = "AMD A4-3"; -CONST CHAR8 ROMDATA str_F12_Fm1_AMD_A4_33[] = "AMD A4-33"; -CONST CHAR8 ROMDATA str_F12_Fm1_AMD_A4_34[] = "AMD A4-34"; -CONST CHAR8 ROMDATA str_F12_Fm1_AMD_A6_3[] = "AMD A6-3"; -CONST CHAR8 ROMDATA str_F12_Fm1_AMD_A6_34[] = "AMD A6-34"; -CONST CHAR8 ROMDATA str_F12_Fm1_AMD_A6_35[] = "AMD A6-35"; -CONST CHAR8 ROMDATA str_F12_Fm1_AMD_A6_36[] = "AMD A6-36"; -CONST CHAR8 ROMDATA str_F12_Fm1_AMD_A8_3[] = "AMD A8-3"; -CONST CHAR8 ROMDATA str_F12_Fm1_AMD_A8_35[] = "AMD A8-35"; -CONST CHAR8 ROMDATA str_F12_Fm1_AMD_A8_38[] = "AMD A8-38"; -CONST CHAR8 ROMDATA str_F12_Fm1_AMD_E2_1[] = "AMD E2-1"; -CONST CHAR8 ROMDATA str_F12_Fm1_AMD_E2_12[] = "AMD E2-12"; -CONST CHAR8 ROMDATA str_F12_Fm1_AMD_E2_3[] = "AMD E2-3"; -CONST CHAR8 ROMDATA str_F12_Fm1_AMD_E2_32[] = "AMD E2-32"; -CONST CHAR8 ROMDATA str_F12_Fm1_AMD_Athlon_II[] = "AMD Athlon(tm) II "; -CONST CHAR8 ROMDATA str_F12_Fm1_AMD_Athlon_II_1[] = "AMD Athlon(tm) II 1"; -CONST CHAR8 ROMDATA str_F12_Fm1_AMD_Athlon_II_X2[] = "AMD Athlon(tm) II X2 "; -CONST CHAR8 ROMDATA str_F12_Fm1_AMD_Athlon_II_X2_2[] = "AMD Athlon(tm) II X2 2"; -CONST CHAR8 ROMDATA str_F12_Fm1_AMD_Athlon_II_X3[] = "AMD Athlon(tm) II X3 "; -CONST CHAR8 ROMDATA str_F12_Fm1_AMD_Athlon_II_X3_3[] = "AMD Athlon(tm) II X3 3"; -CONST CHAR8 ROMDATA str_F12_Fm1_AMD_Athlon_II_X3_4[] = "AMD Athlon(tm) II X3 4"; -CONST CHAR8 ROMDATA str_F12_Fm1_AMD_Athlon_II_X4_4[] = "AMD Athlon(tm) II X4 4"; -CONST CHAR8 ROMDATA str_F12_Fm1_AMD_Athlon_II_X4_6[] = "AMD Athlon(tm) II X4 6"; -CONST CHAR8 ROMDATA str_F12_Fm1_AMD_Athlon_II_X4[] = "AMD Athlon(tm) II X4 "; -CONST CHAR8 ROMDATA str_F12_Fm1_AMD_Athlon_FM1[] = "AMD Athlon(tm) FM1 "; -CONST CHAR8 ROMDATA str_F12_Fm1_AMD_Athlon_FM1_X2[] = "AMD Athlon(tm) FM1 X2 "; -CONST CHAR8 ROMDATA str_F12_Fm1_AMD_Athlon_FM1_X3[] = "AMD Athlon(tm) FM1 X3 "; -CONST CHAR8 ROMDATA str_F12_Fm1_AMD_Athlon_FM1_X4[] = "AMD Athlon(tm) FM1 X4 "; -CONST CHAR8 ROMDATA str_F12_Fm1_AMD_Sempron_1[] = "AMD Sempron(tm) 1"; -CONST CHAR8 ROMDATA str_F12_Fm1_AMD_Sempron_X2_1[] = "AMD Sempron(tm) X2 1"; -CONST CHAR8 ROMDATA str_F12_Fm1_AMD_Sempron_X2_2[] = "AMD Sempron(tm) X2 2"; -CONST CHAR8 ROMDATA str_F12_Fm1_AMD_Sempron_II[] = "AMD Sempron(tm) II "; -CONST CHAR8 ROMDATA str_F12_Fm1_AMD_Sempron_II_1[] = "AMD Sempron(tm) II 1"; -CONST CHAR8 ROMDATA str_F12_Fm1_AMD_Sempron_II_X2[] = "AMD Sempron(tm) II X2 "; -CONST CHAR8 ROMDATA str_F12_Fm1_AMD_Sempron_II_X2_2[] = "AMD Sempron(tm) II X2 2"; -CONST CHAR8 ROMDATA str_F12_Fm1_AMD_Sempron_II_X3[] = "AMD Sempron(tm) II X3 "; -CONST CHAR8 ROMDATA str_F12_Fm1_AMD_Sempron_II_X3_3[] = "AMD Sempron(tm) II X3 3"; -CONST CHAR8 ROMDATA str_F12_Fm1_AMD_Sempron_II_X4_4[] = "AMD Sempron(tm) II X4 4"; -CONST CHAR8 ROMDATA str_F12_Fm1_AMD_Sempron_II_X4[] = "AMD Sempron(tm) II X4 "; -CONST CHAR8 ROMDATA str_F12_Fm1_AMD_Sempron_FM1[] = "AMD Sempron(tm) FM1 "; -CONST CHAR8 ROMDATA str_F12_Fm1_AMD_Sempron_FM1_X2[] = "AMD Sempron(tm) FM1 X2 "; -CONST CHAR8 ROMDATA str_F12_Fm1_AMD_Sempron_FM1_X3[] = "AMD Sempron(tm) FM1 X3 "; -CONST CHAR8 ROMDATA str_F12_Fm1_AMD_Sempron_FM1_X4[] = "AMD Sempron(tm) FM1 X4 "; - -// String2 -CONST CHAR8 ROMDATA str_F12_Fm1_APU[] = " APU with Radeon(tm) HD Graphics"; -CONST CHAR8 ROMDATA str_F12_Fm1_0_APU[] = "0 APU with Radeon(tm) HD Graphics"; -CONST CHAR8 ROMDATA str_F12_Fm1_P_APU[] = "P APU with Radeon(tm) HD Graphics"; -CONST CHAR8 ROMDATA str_F12_Fm1_0P_APU[] = "0P APU with Radeon(tm) HD Graphics"; -CONST CHAR8 ROMDATA str_F12_Fm1_Processor[] = " Processor"; -CONST CHAR8 ROMDATA str_F12_Fm1_0_Processor[] = "0 Processor"; -CONST CHAR8 ROMDATA str_F12_Fm1_DC_Processor[] = " Dual-Core Processor"; -CONST CHAR8 ROMDATA str_F12_Fm1_0_DC_Processor[] = "0 Dual-Core Processor"; -CONST CHAR8 ROMDATA str_F12_Fm1_TC_Processor[] = " Triple-Core Processor"; -CONST CHAR8 ROMDATA str_F12_Fm1_0_TC_Processor[] = "0 Triple-Core Processor"; -CONST CHAR8 ROMDATA str_F12_Fm1_QC_Processor[] = " Quad-Core Processor"; -CONST CHAR8 ROMDATA str_F12_Fm1_0_QC_Processor[] = "0 Quad-Core Processor"; - - -/*--------------------------------------------------------------------------------------- - * T Y P E D E F S, S T R U C T U R E S, E N U M S - *--------------------------------------------------------------------------------------- - */ - -CONST AMD_CPU_BRAND ROMDATA CpuF12LnBrandIdString1ArrayFm1[] = -{ - // FM1 - {1, 0, 1, LN_SOCKET_FM1, str_F12_Fm1_AMD_E2_12, sizeof (str_F12_Fm1_AMD_E2_12)}, - {1, 0, 2, LN_SOCKET_FM1, str_F12_Fm1_AMD_Sempron_II_1, sizeof (str_F12_Fm1_AMD_Sempron_II_1)}, - {1, 0, 3, LN_SOCKET_FM1, str_F12_Fm1_AMD_Athlon_II_1, sizeof (str_F12_Fm1_AMD_Athlon_II_1)}, - {1, 0, 4, LN_SOCKET_FM1, str_F12_Fm1_AMD_E2_1, sizeof (str_F12_Fm1_AMD_E2_1)}, - {1, 0, 5, LN_SOCKET_FM1, str_F12_Fm1_AMD_Sempron_II, sizeof (str_F12_Fm1_AMD_Sempron_II)}, - {1, 0, 6, LN_SOCKET_FM1, str_F12_Fm1_AMD_Athlon_II, sizeof (str_F12_Fm1_AMD_Athlon_II)}, - {1, 0, 7, LN_SOCKET_FM1, str_F12_Fm1_AMD_Sempron_FM1, sizeof (str_F12_Fm1_AMD_Sempron_FM1)}, - {1, 0, 8, LN_SOCKET_FM1, str_F12_Fm1_AMD_Athlon_FM1, sizeof (str_F12_Fm1_AMD_Athlon_FM1)}, - {1, 0, 9, LN_SOCKET_FM1, str_F12_Fm1_AMD_Sempron_1, sizeof (str_F12_Fm1_AMD_Sempron_1)}, - {2, 0, 1, LN_SOCKET_FM1, str_F12_Fm1_AMD_A4_33, sizeof (str_F12_Fm1_AMD_A4_33)}, - {2, 0, 2, LN_SOCKET_FM1, str_F12_Fm1_AMD_E2_32, sizeof (str_F12_Fm1_AMD_E2_32)}, - {2, 0, 3, LN_SOCKET_FM1, str_F12_Fm1_AMD_Sempron_II_X2_2, sizeof (str_F12_Fm1_AMD_Sempron_II_X2_2)}, - {2, 0, 4, LN_SOCKET_FM1, str_F12_Fm1_AMD_Athlon_II_X2_2, sizeof (str_F12_Fm1_AMD_Athlon_II_X2_2)}, - {2, 0, 5, LN_SOCKET_FM1, str_F12_Fm1_AMD_A4_34, sizeof (str_F12_Fm1_AMD_A4_34)}, - {2, 0, 6, LN_SOCKET_FM1, str_F12_Fm1_AMD_A4_3, sizeof (str_F12_Fm1_AMD_A4_3)}, - {2, 0, 7, LN_SOCKET_FM1, str_F12_Fm1_AMD_E2_3, sizeof (str_F12_Fm1_AMD_E2_3)}, - {2, 0, 8, LN_SOCKET_FM1, str_F12_Fm1_AMD_Sempron_II_X2, sizeof (str_F12_Fm1_AMD_Sempron_II_X2)}, - {2, 0, 9, LN_SOCKET_FM1, str_F12_Fm1_AMD_Athlon_II_X2, sizeof (str_F12_Fm1_AMD_Athlon_II_X2)}, - {2, 0, 0xA, LN_SOCKET_FM1, str_F12_Fm1_AMD_Sempron_FM1_X2, sizeof (str_F12_Fm1_AMD_Sempron_FM1_X2)}, - {2, 0, 0xB, LN_SOCKET_FM1, str_F12_Fm1_AMD_Athlon_FM1_X2, sizeof (str_F12_Fm1_AMD_Athlon_FM1_X2)}, - {2, 0, 0xC, LN_SOCKET_FM1, str_F12_Fm1_AMD_Sempron_X2_1, sizeof (str_F12_Fm1_AMD_Sempron_X2_1)}, - {2, 0, 0xD, LN_SOCKET_FM1, str_F12_Fm1_AMD_Sempron_X2_2, sizeof (str_F12_Fm1_AMD_Sempron_X2_2)}, - {3, 0, 1, LN_SOCKET_FM1, str_F12_Fm1_AMD_A6_34, sizeof (str_F12_Fm1_AMD_A6_34)}, - {3, 0, 2, LN_SOCKET_FM1, str_F12_Fm1_AMD_Sempron_II_X3_3, sizeof (str_F12_Fm1_AMD_Sempron_II_X3_3)}, - {3, 0, 3, LN_SOCKET_FM1, str_F12_Fm1_AMD_Athlon_II_X3_3, sizeof (str_F12_Fm1_AMD_Athlon_II_X3_3)}, - {3, 0, 4, LN_SOCKET_FM1, str_F12_Fm1_AMD_A6_36, sizeof (str_F12_Fm1_AMD_A6_36)}, - {3, 0, 5, LN_SOCKET_FM1, str_F12_Fm1_AMD_A6_35, sizeof (str_F12_Fm1_AMD_A6_35)}, - {3, 0, 6, LN_SOCKET_FM1, str_F12_Fm1_AMD_A6_3, sizeof (str_F12_Fm1_AMD_A6_3)}, - {3, 0, 7, LN_SOCKET_FM1, str_F12_Fm1_AMD_Sempron_II_X3, sizeof (str_F12_Fm1_AMD_Sempron_II_X3)}, - {3, 0, 8, LN_SOCKET_FM1, str_F12_Fm1_AMD_Athlon_II_X3, sizeof (str_F12_Fm1_AMD_Athlon_II_X3)}, - {3, 0, 9, LN_SOCKET_FM1, str_F12_Fm1_AMD_Sempron_FM1_X3, sizeof (str_F12_Fm1_AMD_Sempron_FM1_X3)}, - {3, 0, 0xA, LN_SOCKET_FM1, str_F12_Fm1_AMD_Athlon_FM1_X3, sizeof (str_F12_Fm1_AMD_Athlon_FM1_X3)}, - {3, 0, 0xB, LN_SOCKET_FM1, str_F12_Fm1_AMD_Athlon_II_X3_4, sizeof (str_F12_Fm1_AMD_Athlon_II_X3_4)}, - {4, 0, 1, LN_SOCKET_FM1, str_F12_Fm1_AMD_A8_35, sizeof (str_F12_Fm1_AMD_A8_35)}, - {4, 0, 2, LN_SOCKET_FM1, str_F12_Fm1_AMD_A6_34, sizeof (str_F12_Fm1_AMD_A6_34)}, - {4, 0, 3, LN_SOCKET_FM1, str_F12_Fm1_AMD_Sempron_II_X4_4, sizeof (str_F12_Fm1_AMD_Sempron_II_X4_4)}, - {4, 0, 4, LN_SOCKET_FM1, str_F12_Fm1_AMD_Athlon_II_X4_4, sizeof (str_F12_Fm1_AMD_Athlon_II_X4_4)}, - {4, 0, 5, LN_SOCKET_FM1, str_F12_Fm1_AMD_A8_38, sizeof (str_F12_Fm1_AMD_A8_38)}, - {4, 0, 6, LN_SOCKET_FM1, str_F12_Fm1_AMD_A6_36, sizeof (str_F12_Fm1_AMD_A6_36)}, - {4, 0, 7, LN_SOCKET_FM1, str_F12_Fm1_AMD_A8_3, sizeof (str_F12_Fm1_AMD_A8_3)}, - {4, 0, 8, LN_SOCKET_FM1, str_F12_Fm1_AMD_A6_3, sizeof (str_F12_Fm1_AMD_A6_3)}, - {4, 0, 9, LN_SOCKET_FM1, str_F12_Fm1_AMD_Sempron_II_X4, sizeof (str_F12_Fm1_AMD_Sempron_II_X4)}, - {4, 0, 0xA, LN_SOCKET_FM1, str_F12_Fm1_AMD_Athlon_II_X4, sizeof (str_F12_Fm1_AMD_Athlon_II_X4)}, - {4, 0, 0xB, LN_SOCKET_FM1, str_F12_Fm1_AMD_Sempron_FM1_X4, sizeof (str_F12_Fm1_AMD_Sempron_FM1_X4)}, - {4, 0, 0xC, LN_SOCKET_FM1, str_F12_Fm1_AMD_Athlon_FM1_X4, sizeof (str_F12_Fm1_AMD_Athlon_FM1_X4)}, - {4, 0, 0xD, LN_SOCKET_FM1, str_F12_Fm1_AMD_Athlon_II_X4_6, sizeof (str_F12_Fm1_AMD_Athlon_II_X4_6)}, -}; //Cores, page, index, socket, stringstart, stringlength - - -CONST AMD_CPU_BRAND ROMDATA CpuF12LnBrandIdString2ArrayFm1[] = -{ - // FM1 - {1, 0, 1, LN_SOCKET_FM1, str_F12_Fm1_APU, sizeof (str_F12_Fm1_APU)}, - {1, 0, 2, LN_SOCKET_FM1, str_F12_Fm1_Processor, sizeof (str_F12_Fm1_Processor)}, - {1, 0, 3, LN_SOCKET_FM1, str_F12_Fm1_P_APU, sizeof (str_F12_Fm1_P_APU)}, - {1, 0, 4, LN_SOCKET_FM1, str_F12_Fm1_0_APU, sizeof (str_F12_Fm1_0_APU)}, - {1, 0, 5, LN_SOCKET_FM1, str_F12_Fm1_0P_APU, sizeof (str_F12_Fm1_0P_APU)}, - {1, 0, 6, LN_SOCKET_FM1, str_F12_Fm1_0_Processor, sizeof (str_F12_Fm1_0_Processor)}, - {2, 0, 1, LN_SOCKET_FM1, str_F12_Fm1_APU, sizeof (str_F12_Fm1_APU)}, - {2, 0, 2, LN_SOCKET_FM1, str_F12_Fm1_DC_Processor, sizeof (str_F12_Fm1_DC_Processor)}, - {2, 0, 3, LN_SOCKET_FM1, str_F12_Fm1_P_APU, sizeof (str_F12_Fm1_P_APU)}, - {2, 0, 4, LN_SOCKET_FM1, str_F12_Fm1_0_APU, sizeof (str_F12_Fm1_0_APU)}, - {2, 0, 5, LN_SOCKET_FM1, str_F12_Fm1_0P_APU, sizeof (str_F12_Fm1_0P_APU)}, - {2, 0, 6, LN_SOCKET_FM1, str_F12_Fm1_0_DC_Processor, sizeof (str_F12_Fm1_0_DC_Processor)}, - {3, 0, 1, LN_SOCKET_FM1, str_F12_Fm1_APU, sizeof (str_F12_Fm1_APU)}, - {3, 0, 2, LN_SOCKET_FM1, str_F12_Fm1_P_APU, sizeof (str_F12_Fm1_P_APU)}, - {3, 0, 3, LN_SOCKET_FM1, str_F12_Fm1_TC_Processor, sizeof (str_F12_Fm1_TC_Processor)}, - {3, 0, 4, LN_SOCKET_FM1, str_F12_Fm1_0_APU, sizeof (str_F12_Fm1_0_APU)}, - {3, 0, 5, LN_SOCKET_FM1, str_F12_Fm1_0P_APU, sizeof (str_F12_Fm1_0P_APU)}, - {3, 0, 6, LN_SOCKET_FM1, str_F12_Fm1_0_TC_Processor, sizeof (str_F12_Fm1_0_TC_Processor)}, - {4, 0, 1, LN_SOCKET_FM1, str_F12_Fm1_APU, sizeof (str_F12_Fm1_APU)}, - {4, 0, 2, LN_SOCKET_FM1, str_F12_Fm1_P_APU, sizeof (str_F12_Fm1_P_APU)}, - {4, 0, 3, LN_SOCKET_FM1, str_F12_Fm1_QC_Processor, sizeof (str_F12_Fm1_QC_Processor)}, - {4, 0, 4, LN_SOCKET_FM1, str_F12_Fm1_0_APU, sizeof (str_F12_Fm1_0_APU)}, - {4, 0, 5, LN_SOCKET_FM1, str_F12_Fm1_0P_APU, sizeof (str_F12_Fm1_0P_APU)}, - {4, 0, 6, LN_SOCKET_FM1, str_F12_Fm1_0_QC_Processor, sizeof (str_F12_Fm1_0_QC_Processor)}, - }; //Cores, page, index, socket, stringstart, stringlength - - -CONST CPU_BRAND_TABLE ROMDATA F12LnBrandIdString1ArrayFm1 = { - (sizeof (CpuF12LnBrandIdString1ArrayFm1) / sizeof (AMD_CPU_BRAND)), - CpuF12LnBrandIdString1ArrayFm1 -}; - - -CONST CPU_BRAND_TABLE ROMDATA F12LnBrandIdString2ArrayFm1 = { - (sizeof (CpuF12LnBrandIdString2ArrayFm1) / sizeof (AMD_CPU_BRAND)), - CpuF12LnBrandIdString2ArrayFm1 -}; - - diff --git a/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x12/cpuF12BrandIdFs1.c b/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x12/cpuF12BrandIdFs1.c deleted file mode 100644 index 372ae4c921..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x12/cpuF12BrandIdFs1.c +++ /dev/null @@ -1,181 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * AMD CPU BrandId related functions and structures. - * - * Contains code that provides CPU BrandId information - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: CPU/Family/0x12 - * @e \$Revision: 46474 $ @e \$Date: 2011-02-03 05:46:17 +0800 (Thu, 03 Feb 2011) $ - * - */ -/* - ****************************************************************************** - * - * Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - ****************************************************************************** - */ - -/*---------------------------------------------------------------------------------------- - * M O D U L E S U S E D - *---------------------------------------------------------------------------------------- - */ -#include "AGESA.h" -#include "cpuRegisters.h" -#include "cpuEarlyInit.h" -#include "F12PackageType.h" - -/*---------------------------------------------------------------------------------------- - * D E F I N I T I O N S A N D M A C R O S - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------- - * T Y P E D E F S A N D S T R U C T U R E S - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------- - * P R O T O T Y P E S O F L O C A L F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------- - * E X P O R T E D F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ - -// String1 -CONST CHAR8 ROMDATA str_F12_Fs1_AMD_A4_35[] = "AMD A4-35"; -CONST CHAR8 ROMDATA str_F12_Fs1_AMD_A4_34[] = "AMD A4-34"; -CONST CHAR8 ROMDATA str_F12_Fs1_AMD_A4_33[] = "AMD A4-33"; -CONST CHAR8 ROMDATA str_F12_Fs1_AMD_A4_32[] = "AMD A4-32"; -CONST CHAR8 ROMDATA str_F12_Fs1_AMD_E2_30[] = "AMD E2-30"; -CONST CHAR8 ROMDATA str_F12_Fs1_AMD_E2_20[] = "AMD E2-20"; -CONST CHAR8 ROMDATA str_F12_Fs1_AMD_E2_10[] = "AMD E2-10"; -CONST CHAR8 ROMDATA str_F12_Fs1_AMD_A8_35[] = "AMD A8-35"; -CONST CHAR8 ROMDATA str_F12_Fs1_AMD_A8_34[] = "AMD A8-34"; -CONST CHAR8 ROMDATA str_F12_Fs1_AMD_A6_34[] = "AMD A6-34"; -CONST CHAR8 ROMDATA str_F12_Fs1_AMD_A6_33[] = "AMD A6-33"; - -// String2 -CONST CHAR8 ROMDATA str_F12_Fs1_M_APU[] = "M APU with Radeon(tm) HD Graphics"; -CONST CHAR8 ROMDATA str_F12_Fs1_MX_APU[] = "MX APU with Radeon(tm) HD Graphics"; -CONST CHAR8 ROMDATA str_F12_Fs1_ML_APU[] = "ML APU with Radeon(tm) HD Graphics"; -CONST CHAR8 ROMDATA str_F12_Fs1_MZ_APU[] = "MZ APU with Radeon(tm) HD Graphics"; -CONST CHAR8 ROMDATA str_F12_Fs1_MC_APU[] = "MC APU with Radeon(tm) HD Graphics"; -CONST CHAR8 ROMDATA str_F12_Fs1_MF_Processor[] = "MF Processor"; -CONST CHAR8 ROMDATA str_F12_Fs1_MG_Processor[] = "MG Processor"; -CONST CHAR8 ROMDATA str_F12_Fs1_MF_DC_Processor[] = "MF Dual-Core Processor"; -CONST CHAR8 ROMDATA str_F12_Fs1_MG_DC_Processor[] = "MG Dual-Core Processor"; -CONST CHAR8 ROMDATA str_F12_Fs1_MF_TC_Processor[] = "MF Triple-Core Processor"; -CONST CHAR8 ROMDATA str_F12_Fs1_MG_TC_Processor[] = "MG Triple-Core Processor"; -CONST CHAR8 ROMDATA str_F12_Fs1_MF_QC_Processor[] = "MF Quad-Core Processor"; -CONST CHAR8 ROMDATA str_F12_Fs1_MG_QC_Processor[] = "MG Quad-Core Processor"; - - -/*--------------------------------------------------------------------------------------- - * T Y P E D E F S, S T R U C T U R E S, E N U M S - *--------------------------------------------------------------------------------------- - */ - -CONST AMD_CPU_BRAND ROMDATA CpuF12LnBrandIdString1ArrayFs1[] = -{ - // FS1 - {1, 0, 1, LN_SOCKET_FS1, str_F12_Fs1_AMD_A4_35, sizeof (str_F12_Fs1_AMD_A4_35)}, - {2, 0, 1, LN_SOCKET_FS1, str_F12_Fs1_AMD_A4_35, sizeof (str_F12_Fs1_AMD_A4_35)}, - {1, 0, 2, LN_SOCKET_FS1, str_F12_Fs1_AMD_A4_34, sizeof (str_F12_Fs1_AMD_A4_34)}, - {2, 0, 2, LN_SOCKET_FS1, str_F12_Fs1_AMD_A4_34, sizeof (str_F12_Fs1_AMD_A4_34)}, - {1, 0, 3, LN_SOCKET_FS1, str_F12_Fs1_AMD_A4_33, sizeof (str_F12_Fs1_AMD_A4_33)}, - {2, 0, 3, LN_SOCKET_FS1, str_F12_Fs1_AMD_A4_33, sizeof (str_F12_Fs1_AMD_A4_33)}, - {1, 0, 4, LN_SOCKET_FS1, str_F12_Fs1_AMD_A4_32, sizeof (str_F12_Fs1_AMD_A4_32)}, - {2, 0, 4, LN_SOCKET_FS1, str_F12_Fs1_AMD_A4_32, sizeof (str_F12_Fs1_AMD_A4_32)}, - {1, 0, 5, LN_SOCKET_FS1, str_F12_Fs1_AMD_E2_30, sizeof (str_F12_Fs1_AMD_E2_30)}, - {2, 0, 5, LN_SOCKET_FS1, str_F12_Fs1_AMD_E2_30, sizeof (str_F12_Fs1_AMD_E2_30)}, - {1, 0, 6, LN_SOCKET_FS1, str_F12_Fs1_AMD_E2_20, sizeof (str_F12_Fs1_AMD_E2_20)}, - {2, 0, 6, LN_SOCKET_FS1, str_F12_Fs1_AMD_E2_20, sizeof (str_F12_Fs1_AMD_E2_20)}, - {1, 0, 7, LN_SOCKET_FS1, str_F12_Fs1_AMD_E2_10, sizeof (str_F12_Fs1_AMD_E2_10)}, - {2, 0, 7, LN_SOCKET_FS1, str_F12_Fs1_AMD_E2_10, sizeof (str_F12_Fs1_AMD_E2_10)}, - {3, 0, 1, LN_SOCKET_FS1, str_F12_Fs1_AMD_A8_35, sizeof (str_F12_Fs1_AMD_A8_35)}, - {4, 0, 1, LN_SOCKET_FS1, str_F12_Fs1_AMD_A8_35, sizeof (str_F12_Fs1_AMD_A8_35)}, - {3, 0, 2, LN_SOCKET_FS1, str_F12_Fs1_AMD_A8_34, sizeof (str_F12_Fs1_AMD_A8_34)}, - {4, 0, 2, LN_SOCKET_FS1, str_F12_Fs1_AMD_A8_34, sizeof (str_F12_Fs1_AMD_A8_34)}, - {3, 0, 3, LN_SOCKET_FS1, str_F12_Fs1_AMD_A6_34, sizeof (str_F12_Fs1_AMD_A6_34)}, - {4, 0, 3, LN_SOCKET_FS1, str_F12_Fs1_AMD_A6_34, sizeof (str_F12_Fs1_AMD_A6_34)}, - {3, 0, 4, LN_SOCKET_FS1, str_F12_Fs1_AMD_A6_33, sizeof (str_F12_Fs1_AMD_A6_33)}, - {4, 0, 4, LN_SOCKET_FS1, str_F12_Fs1_AMD_A6_33, sizeof (str_F12_Fs1_AMD_A6_33)}, -}; //Cores, page, index, socket, stringstart, stringlength - - -CONST AMD_CPU_BRAND ROMDATA CpuF12LnBrandIdString2ArrayFs1[] = -{ - // FS1 - {1, 0, 1, LN_SOCKET_FS1, str_F12_Fs1_M_APU, sizeof (str_F12_Fs1_M_APU)}, - {2, 0, 1, LN_SOCKET_FS1, str_F12_Fs1_M_APU, sizeof (str_F12_Fs1_M_APU)}, - {3, 0, 1, LN_SOCKET_FS1, str_F12_Fs1_M_APU, sizeof (str_F12_Fs1_M_APU)}, - {4, 0, 1, LN_SOCKET_FS1, str_F12_Fs1_M_APU, sizeof (str_F12_Fs1_M_APU)}, - {1, 0, 2, LN_SOCKET_FS1, str_F12_Fs1_MX_APU, sizeof (str_F12_Fs1_MX_APU)}, - {2, 0, 2, LN_SOCKET_FS1, str_F12_Fs1_MX_APU, sizeof (str_F12_Fs1_MX_APU)}, - {3, 0, 2, LN_SOCKET_FS1, str_F12_Fs1_MX_APU, sizeof (str_F12_Fs1_MX_APU)}, - {4, 0, 2, LN_SOCKET_FS1, str_F12_Fs1_MX_APU, sizeof (str_F12_Fs1_MX_APU)}, - {1, 0, 3, LN_SOCKET_FS1, str_F12_Fs1_ML_APU, sizeof (str_F12_Fs1_ML_APU)}, - {2, 0, 3, LN_SOCKET_FS1, str_F12_Fs1_ML_APU, sizeof (str_F12_Fs1_ML_APU)}, - {3, 0, 3, LN_SOCKET_FS1, str_F12_Fs1_ML_APU, sizeof (str_F12_Fs1_ML_APU)}, - {4, 0, 3, LN_SOCKET_FS1, str_F12_Fs1_ML_APU, sizeof (str_F12_Fs1_ML_APU)}, - {1, 0, 4, LN_SOCKET_FS1, str_F12_Fs1_MZ_APU, sizeof (str_F12_Fs1_MZ_APU)}, - {2, 0, 4, LN_SOCKET_FS1, str_F12_Fs1_MZ_APU, sizeof (str_F12_Fs1_MZ_APU)}, - {3, 0, 4, LN_SOCKET_FS1, str_F12_Fs1_MZ_APU, sizeof (str_F12_Fs1_MZ_APU)}, - {4, 0, 4, LN_SOCKET_FS1, str_F12_Fs1_MZ_APU, sizeof (str_F12_Fs1_MZ_APU)}, - {1, 0, 5, LN_SOCKET_FS1, str_F12_Fs1_MC_APU, sizeof (str_F12_Fs1_MC_APU)}, - {2, 0, 5, LN_SOCKET_FS1, str_F12_Fs1_MC_APU, sizeof (str_F12_Fs1_MC_APU)}, - {3, 0, 5, LN_SOCKET_FS1, str_F12_Fs1_MC_APU, sizeof (str_F12_Fs1_MC_APU)}, - {4, 0, 5, LN_SOCKET_FS1, str_F12_Fs1_MC_APU, sizeof (str_F12_Fs1_MC_APU)}, - {1, 0, 6, LN_SOCKET_FS1, str_F12_Fs1_MF_Processor, sizeof (str_F12_Fs1_MF_Processor)}, - {1, 0, 7, LN_SOCKET_FS1, str_F12_Fs1_MG_Processor, sizeof (str_F12_Fs1_MG_Processor)}, - {2, 0, 6, LN_SOCKET_FS1, str_F12_Fs1_MF_DC_Processor, sizeof (str_F12_Fs1_MF_DC_Processor)}, - {2, 0, 7, LN_SOCKET_FS1, str_F12_Fs1_MG_DC_Processor, sizeof (str_F12_Fs1_MG_DC_Processor)}, - {3, 0, 6, LN_SOCKET_FS1, str_F12_Fs1_MF_TC_Processor, sizeof (str_F12_Fs1_MF_TC_Processor)}, - {3, 0, 7, LN_SOCKET_FS1, str_F12_Fs1_MG_TC_Processor, sizeof (str_F12_Fs1_MG_TC_Processor)}, - {4, 0, 6, LN_SOCKET_FS1, str_F12_Fs1_MF_QC_Processor, sizeof (str_F12_Fs1_MF_QC_Processor)}, - {4, 0, 7, LN_SOCKET_FS1, str_F12_Fs1_MG_QC_Processor, sizeof (str_F12_Fs1_MG_QC_Processor)}, - }; //Cores, page, index, socket, stringstart, stringlength - - -CONST CPU_BRAND_TABLE ROMDATA F12LnBrandIdString1ArrayFs1 = { - (sizeof (CpuF12LnBrandIdString1ArrayFs1) / sizeof (AMD_CPU_BRAND)), - CpuF12LnBrandIdString1ArrayFs1 -}; - - -CONST CPU_BRAND_TABLE ROMDATA F12LnBrandIdString2ArrayFs1 = { - (sizeof (CpuF12LnBrandIdString2ArrayFs1) / sizeof (AMD_CPU_BRAND)), - CpuF12LnBrandIdString2ArrayFs1 -}; - - diff --git a/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x12/cpuF12CacheDefaults.c b/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x12/cpuF12CacheDefaults.c deleted file mode 100644 index 900c82b10d..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x12/cpuF12CacheDefaults.c +++ /dev/null @@ -1,130 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * AMD Family_12 ROM Execution Cache Defaults - * - * Contains default values for ROM execution cache setup - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: CPU/Family/0x12 - * @e \$Revision: 50761 $ @e \$Date: 2011-04-14 06:16:02 +0800 (Thu, 14 Apr 2011) $ - * - */ -/* - ****************************************************************************** - * - * Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - ****************************************************************************** - */ - -/*---------------------------------------------------------------------------------------- - * M O D U L E S U S E D - *---------------------------------------------------------------------------------------- - */ -#include "AGESA.h" -#include "cpuCacheInit.h" -#include "cpuFamilyTranslation.h" -#include "Filecode.h" -CODE_GROUP (G1_PEICC) -RDATA_GROUP (G1_PEICC) -#define FILECODE PROC_CPU_FAMILY_0X12_CPUF12CACHEDEFAULTS_FILECODE - -/*---------------------------------------------------------------------------------------- - * D E F I N I T I O N S A N D M A C R O S - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------- - * T Y P E D E F S A N D S T R U C T U R E S - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------- - * P R O T O T Y P E S O F L O C A L F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ -VOID -GetF12CacheInfo ( - IN CPU_SPECIFIC_SERVICES *FamilySpecificServices, - OUT CONST VOID **CacheInfoPtr, - OUT UINT8 *NumberOfElements, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -/*---------------------------------------------------------------------------------------- - * E X P O R T E D F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ -#define BSP_STACK_SIZE 16384 -#define CORE0_STACK_SIZE 16384 -#define CORE1_STACK_SIZE 4096 -#define MEM_TRAINING_BUFFER_SIZE 16384 -#define VAR_MTRR_MASK 0x000000FFFFFFFFFFull - -#define HEAP_BASE_MASK 0x000000FFFFFFFFFFull - -#define SHARED_MEM_SIZE 0 - -CONST CACHE_INFO ROMDATA CpuF12CacheInfo = -{ - BSP_STACK_SIZE, - CORE0_STACK_SIZE, - CORE1_STACK_SIZE, - MEM_TRAINING_BUFFER_SIZE, - SHARED_MEM_SIZE, - (UINT64) VAR_MTRR_MASK, - (UINT64) VAR_MTRR_MASK, - (UINT64) HEAP_BASE_MASK, - LimitedByL2Size -}; - - -/*---------------------------------------------------------------------------------------*/ -/** - * Returns the family specific properties of the cache, and its usage. - * - * @CpuServiceMethod{::F_CPU_GET_FAMILY_SPECIFIC_ARRAY}. - * - * @param[in] FamilySpecificServices The current Family Specific Services. - * @param[out] CacheInfoPtr Points to the cache info properties on exit. - * @param[out] NumberOfElements Will be one to indicate one entry. - * @param[in] StdHeader Header for library and services. - * - */ -VOID -GetF12CacheInfo ( - IN CPU_SPECIFIC_SERVICES *FamilySpecificServices, - OUT CONST VOID **CacheInfoPtr, - OUT UINT8 *NumberOfElements, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - *NumberOfElements = 1; - *CacheInfoPtr = &CpuF12CacheInfo; -} - diff --git a/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x12/cpuF12Dmi.c b/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x12/cpuF12Dmi.c deleted file mode 100644 index 227cecaefc..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x12/cpuF12Dmi.c +++ /dev/null @@ -1,352 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * AMD DMI Record Creation API, and related functions. - * - * Contains code that produce the DMI related information. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: CPU - * @e \$Revision: 49028 $ @e \$Date: 2011-03-16 09:20:07 +0800 (Wed, 16 Mar 2011) $ - * - */ -/***************************************************************************** - * - * Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - ****************************************************************************** - */ - -/*---------------------------------------------------------------------------------------- - * M O D U L E S U S E D - *---------------------------------------------------------------------------------------- - */ -#include "AGESA.h" -#include "amdlib.h" -#include "cpuRegisters.h" -#include "cpuLateInit.h" -#include "cpuF12PowerMgmt.h" -#include "cpuFamilyTranslation.h" -#include "cpuPstateTables.h" -#include "Filecode.h" -CODE_GROUP (G3_DXE) -RDATA_GROUP (G3_DXE) - -#define FILECODE PROC_CPU_FAMILY_0X12_CPUF12DMI_FILECODE - -/*---------------------------------------------------------------------------------------- - * D E F I N I T I O N S A N D M A C R O S - *---------------------------------------------------------------------------------------- - */ -extern CPU_FAMILY_SUPPORT_TABLE PstateFamilyServiceTable; - -/*---------------------------------------------------------------------------------------- - * T Y P E D E F S A N D S T R U C T U R E S - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------- - * P R O T O T Y P E S O F L O C A L F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ -VOID -DmiF12GetInfo ( - IN OUT CPU_TYPE_INFO *CpuInfoPtr, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -UINT8 -DmiF12GetVoltage ( - IN AMD_CONFIG_PARAMS *StdHeader - ); - -UINT16 -DmiF12GetMaxSpeed ( - IN AMD_CONFIG_PARAMS *StdHeader - ); - -UINT16 -DmiF12GetExtClock ( - IN AMD_CONFIG_PARAMS *StdHeader - ); - -VOID -DmiF12GetMemInfo ( - IN OUT CPU_GET_MEM_INFO *CpuGetMemInfoPtr, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -/*---------------------------------------------------------------------------------------- - * E X P O R T E D F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ - -/* -----------------------------------------------------------------------------*/ -/** - * - * DmiF12GetInfo - * - * Get CPU type information - * - * @param[in,out] CpuInfoPtr Pointer to CPU_TYPE_INFO struct. - * @param[in] StdHeader Standard Head Pointer - * - */ -VOID -DmiF12GetInfo ( - IN OUT CPU_TYPE_INFO *CpuInfoPtr, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - CPUID_DATA CpuId; - - LibAmdCpuidRead (AMD_CPUID_FMF, &CpuId, StdHeader); - CpuInfoPtr->ExtendedFamily = (UINT8) (CpuId.EAX_Reg >> 20) & 0xFF; // bit 27:20 - CpuInfoPtr->ExtendedModel = (UINT8) (CpuId.EAX_Reg >> 16) & 0xF; // bit 19:16 - CpuInfoPtr->BaseFamily = (UINT8) (CpuId.EAX_Reg >> 8) & 0xF; // bit 11:8 - CpuInfoPtr->BaseModel = (UINT8) (CpuId.EAX_Reg >> 4) & 0xF; // bit 7:4 - CpuInfoPtr->Stepping = (UINT8) (CpuId.EAX_Reg & 0xF); // bit 3:0 - - CpuInfoPtr->PackageType = (UINT8) (CpuId.EBX_Reg >> 28) & 0xF; // bit 31:28 - CpuInfoPtr->BrandId.Pg = (UINT8) (CpuId.EBX_Reg >> 15) & 0x1; // bit 15 - CpuInfoPtr->BrandId.String1 = (UINT8) (CpuId.EBX_Reg >> 11) & 0xF; // bit 14:11 - CpuInfoPtr->BrandId.Model = (UINT8) (CpuId.EBX_Reg >> 4) & 0x7F; // bit 10:4 - CpuInfoPtr->BrandId.String2 = (UINT8) (CpuId.EBX_Reg & 0xF); // bit 3:0 - - LibAmdCpuidRead (AMD_CPUID_ASIZE_PCCOUNT, &CpuId, StdHeader); - CpuInfoPtr->TotalCoreNumber = (UINT8) (CpuId.ECX_Reg & 0xFF); // bit 7:0 - CpuInfoPtr->EnabledCoreNumber = (UINT8) (CpuId.ECX_Reg & 0xFF); // bit 7:0 - - switch (CpuInfoPtr->PackageType) { - case LN_SOCKET_FP1: - CpuInfoPtr->ProcUpgrade = P_UPGRADE_NONE; - break; - case LN_SOCKET_FS1: - CpuInfoPtr->ProcUpgrade = P_UPGRADE_FS1; - break; - case LN_SOCKET_FM1: - CpuInfoPtr->ProcUpgrade = P_UPGRADE_FM1; - break; - default: - CpuInfoPtr->ProcUpgrade = P_UPGRADE_UNKNOWN; - break; - } - -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * DmiF12GetVoltage - * - * Get the voltage value according to SMBIOS SPEC's requirement. - * - * @param[in] StdHeader Standard Head Pointer - * - * @retval Voltage - CPU Voltage. - * - */ -UINT8 -DmiF12GetVoltage ( - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - UINT8 MaxVid; - UINT8 Voltage; - UINT8 NumberBoostStates; - UINT64 MsrData; - PCI_ADDR TempAddr; - CPB_CTRL_REGISTER CpbCtrl; - - // Voltage = 0x80 + (voltage at boot time * 10) - TempAddr.AddressValue = CPB_CTRL_PCI_ADDR; - LibAmdPciRead (AccessWidth32, TempAddr, &CpbCtrl, StdHeader); // F4x15C - NumberBoostStates = (UINT8) CpbCtrl.NumBoostStates; - - LibAmdMsrRead ((MSR_PSTATE_0 + NumberBoostStates), &MsrData, StdHeader); - MaxVid = (UINT8) (((PSTATE_MSR *)&MsrData)->CpuVid); - - if ((MaxVid >= 0x7C) && (MaxVid <= 0x7F)) { - Voltage = 0; - } else { - Voltage = (UINT8) ((15500 - (125 * MaxVid) + 500) / 1000); - } - - Voltage += 0x80; - return (Voltage); -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * DmiF12GetMaxSpeed - * - * Get the Max Speed - * - * @param[in] StdHeader Standard Head Pointer - * - * @retval MaxSpeed - CPU Max Speed. - * - */ -UINT16 -DmiF12GetMaxSpeed ( - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - UINT8 NumBoostStates; - UINT32 P0Frequency; - UINT32 PciData; - PCI_ADDR PciAddress; - PSTATE_CPU_FAMILY_SERVICES *FamilyServices; - - FamilyServices = NULL; - GetFeatureServicesOfCurrentCore (&PstateFamilyServiceTable, (const VOID **) &FamilyServices, StdHeader); - ASSERT (FamilyServices != NULL); - - PciAddress.AddressValue = MAKE_SBDFO (0, 0 , PCI_DEV_BASE, FUNC_4, 0x15C); - LibAmdPciRead (AccessWidth32, PciAddress, &PciData, StdHeader); - NumBoostStates = (UINT8) ((PciData >> 2) & 7); - - FamilyServices->GetPstateFrequency (FamilyServices, NumBoostStates, &P0Frequency, StdHeader); - return ((UINT16) P0Frequency); -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * DmiF12GetExtClock - * - * Get the external clock Speed - * - * @param[in] StdHeader Standard Head Pointer - * - * @retval ExtClock - CPU external clock Speed. - * - */ -UINT16 -DmiF12GetExtClock ( - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - return (EXTERNAL_CLOCK_100MHZ); -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * DmiF12GetMemInfo - * - * Get memory information. - * - * @param[in,out] CpuGetMemInfoPtr Pointer to CPU_GET_MEM_INFO struct. - * @param[in] StdHeader Standard Head Pointer - * - */ -VOID -DmiF12GetMemInfo ( - IN OUT CPU_GET_MEM_INFO *CpuGetMemInfoPtr, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - // Llano does NOT support ECC DIMM - CpuGetMemInfoPtr->EccCapable = FALSE; - // Partition Row Position - 0 is for dual channel memory - CpuGetMemInfoPtr->PartitionRowPosition = 0; -} - -/*--------------------------------------------------------------------------------------- - * Processor Family Table - * - * Note: 'x' means we don't care this field - * 047h = "E-Series" - * 048h = "A-Series" - * 002h = "Unknown" - *-------------------------------------------------------------------------------------*/ -CONST DMI_BRAND_ENTRY ROMDATA Family12BrandList[] = -{ - // Brand --> DMI ID translation table - // PackageType, PgOfBrandId, NumberOfCores, String1ofBrandId, ValueSetToDmiTable - {1, 0, 0, 1, 0x48}, - {1, 0, 1, 1, 0x48}, - {1, 0, 0, 2, 0x48}, - {1, 0, 1, 2, 0x48}, - {1, 0, 0, 3, 0x48}, - {1, 0, 1, 3, 0x48}, - {1, 0, 0, 4, 0x48}, - {1, 0, 1, 4, 0x48}, - {1, 0, 0, 5, 0x47}, - {1, 0, 1, 5, 0x47}, - {1, 0, 0, 6, 0x47}, - {1, 0, 1, 6, 0x47}, - {1, 0, 0, 7, 0x47}, - {1, 0, 1, 7, 0x47}, - {1, 0, 2, 1, 0x48}, - {1, 0, 3, 1, 0x48}, - {1, 0, 2, 2, 0x48}, - {1, 0, 3, 2, 0x48}, - {1, 0, 2, 3, 0x48}, - {1, 0, 3, 3, 0x48}, - {1, 0, 2, 4, 0x48}, - {1, 0, 3, 4, 0x48}, - {2, 0, 0, 1, 0x47}, - {2, 0, 0, 4, 0x47}, - {2, 0, 1, 1, 0x48}, - {2, 0, 1, 2, 0x47}, - {2, 0, 1, 5, 0x48}, - {2, 0, 1, 6, 0x48}, - {2, 0, 1, 7, 0x47}, - {2, 0, 2, 1, 0x48}, - {2, 0, 2, 4, 0x48}, - {2, 0, 2, 5, 0x48}, - {2, 0, 2, 6, 0x48}, - {2, 0, 3, 1, 0x48}, - {2, 0, 3, 2, 0x48}, - {2, 0, 3, 5, 0x48}, - {2, 0, 3, 6, 0x48}, - {2, 0, 3, 7, 0x48}, - {2, 0, 3, 8, 0x48}, - {'x', 'x', 'x', 'x', P_FAMILY_UNKNOWN} -}; - -CONST PROC_FAMILY_TABLE ROMDATA ProcFamily12DmiTable = -{ - AMD_FAMILY_12, // ID for Family 12h - &DmiF12GetInfo, // Transfer vectors for family - &DmiGetT4ProcFamilyFromBrandId, // Get type 4 processor family information from CPUID_8000_0001_EBX[BrandId] - &DmiF12GetVoltage, // specific routines (above) - &DmiF12GetMaxSpeed, - &DmiF12GetExtClock, - &DmiF12GetMemInfo, // Get memory information - (sizeof (Family12BrandList) / sizeof (Family12BrandList[0])), // Number of entries in following table - &Family12BrandList[0] -}; - - -/*--------------------------------------------------------------------------------------- - * L O C A L F U N C T I O N S - *--------------------------------------------------------------------------------------- - */ diff --git a/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x12/cpuF12EarlyNbPstateInit.c b/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x12/cpuF12EarlyNbPstateInit.c deleted file mode 100644 index 0bf4c69da1..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x12/cpuF12EarlyNbPstateInit.c +++ /dev/null @@ -1,115 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * AMD Family_12 Early NB P-state Initialization - * - * Sets some NB P-state related fields at AmdInitEarly. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: CPU/F12 - * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $ - * - */ -/* - ****************************************************************************** - * - * Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - ****************************************************************************** - */ - -/*---------------------------------------------------------------------------------------- - * M O D U L E S U S E D - *---------------------------------------------------------------------------------------- - */ -#include "AGESA.h" -#include "amdlib.h" -#include "cpuFamilyTranslation.h" -#include "cpuF12PowerMgmt.h" -#include "cpuF12EarlyNbPstateInit.h" -#include "Filecode.h" -CODE_GROUP (G1_PEICC) -RDATA_GROUP (G1_PEICC) - -#define FILECODE PROC_CPU_FAMILY_0X12_CPUF12EARLYNBPSTATEINIT_FILECODE - -/*---------------------------------------------------------------------------------------- - * D E F I N I T I O N S A N D M A C R O S - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------- - * T Y P E D E F S A N D S T R U C T U R E S - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------- - * P R O T O T Y P E S O F L O C A L F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------- - * E X P O R T E D F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------*/ -/** - * Family 12h core 0 entry point for performing early NB P-state initialization. - * - * Set up D18F6x94[CpuPstateThrEn, CpuPstateThr] according to the BKDG. - * - * @param[in] FamilySpecificServices The current Family Specific Services. - * @param[in] CpuEarlyParams Service parameters - * @param[in] StdHeader Config handle for library and services. - * - */ -VOID -F12NbPstateEarlyInit ( - IN CPU_SPECIFIC_SERVICES *FamilySpecificServices, - IN AMD_CPU_EARLY_PARAMS *CpuEarlyParams, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - UINT32 CpbControl; - UINT32 LocalPciRegister; - PCI_ADDR PciAddress; - - PciAddress.AddressValue = CPB_CTRL_PCI_ADDR; - LibAmdPciRead (AccessWidth32, PciAddress, &CpbControl, StdHeader); - - PciAddress.AddressValue = NB_PSTATE_CFG_HIGH_PCI_ADDR; - LibAmdPciRead (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader); - - if (((CPB_CTRL_REGISTER *) &CpbControl)->NumBoostStates == 0) { - ((NB_PSTATE_CFG_HIGH_REGISTER *) &LocalPciRegister)->CpuPstateThr = 1; - } else { - ((NB_PSTATE_CFG_HIGH_REGISTER *) &LocalPciRegister)->CpuPstateThr = 2; - } - ((NB_PSTATE_CFG_HIGH_REGISTER *) &LocalPciRegister)->CpuPstateThrEn = 1; - LibAmdPciWrite (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader); -} diff --git a/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x12/cpuF12EarlyNbPstateInit.h b/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x12/cpuF12EarlyNbPstateInit.h deleted file mode 100644 index 2691231ba1..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x12/cpuF12EarlyNbPstateInit.h +++ /dev/null @@ -1,76 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * AMD Family_12 Early NB P-state Initialization related functions and structures - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: CPU/F12 - * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $ - * - */ -/* - ****************************************************************************** - * - * Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - ****************************************************************************** - */ - -#ifndef _CPU_F12_EARLY_NB_PSTATE_INIT_H_ -#define _CPU_F12_EARLY_NB_PSTATE_INIT_H_ - - -/*--------------------------------------------------------------------------------------- - * M I X E D (Definitions And Macros / Typedefs, Structures, Enums) - *--------------------------------------------------------------------------------------- - */ - - -/*--------------------------------------------------------------------------------------- - * D E F I N I T I O N S A N D M A C R O S - *--------------------------------------------------------------------------------------- - */ - - -/*--------------------------------------------------------------------------------------- - * T Y P E D E F S, S T R U C T U R E S, E N U M S - *--------------------------------------------------------------------------------------- - */ - - -/*--------------------------------------------------------------------------------------- - * F U N C T I O N P R O T O T Y P E - *--------------------------------------------------------------------------------------- - */ -VOID -F12NbPstateEarlyInit ( - IN CPU_SPECIFIC_SERVICES *FamilySpecificServices, - IN AMD_CPU_EARLY_PARAMS *CpuEarlyParams, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -#endif // _CPU_F12_EARLY_NB_PSTATE_INIT_H_ diff --git a/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x12/cpuF12MsrTables.c b/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x12/cpuF12MsrTables.c deleted file mode 100644 index 7d47641332..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x12/cpuF12MsrTables.c +++ /dev/null @@ -1,214 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * AMD Family_12 MSR tables with values as defined in BKDG - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: CPU - * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $ - * - */ -/* - ****************************************************************************** - * - * Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - ****************************************************************************** - */ - -/*---------------------------------------------------------------------------------------- - * M O D U L E S U S E D - *---------------------------------------------------------------------------------------- - */ -#include "AGESA.h" -#include "cpuRegisters.h" -#include "cpuF12PowerMgmt.h" -#include "Table.h" -#include "Filecode.h" -CODE_GROUP (G1_PEICC) -RDATA_GROUP (G1_PEICC) - -#define FILECODE PROC_CPU_FAMILY_0X12_CPUF12MSRTABLES_FILECODE - -/*---------------------------------------------------------------------------------------- - * D E F I N I T I O N S A N D M A C R O S - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------- - * T Y P E D E F S A N D S T R U C T U R E S - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------- - * P R O T O T Y P E S O F L O C A L F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------- - * E X P O R T E D F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ -CONST MSR_TYPE_ENTRY_INITIALIZER ROMDATA F12MsrRegisters[] = -{ - -// M S R T a b l e s -// ---------------------- - -// MSR_TOM2 (0xC001001D) -// bits[63:0] - TOP_MEM2 = 0 - { - MsrRegister, - { - AMD_FAMILY_12, // CpuFamily - AMD_F12_ALL // CpuRevision - }, - {AMD_PF_ALL}, // platformFeatures - {{ - MSR_TOM2, // MSR Address - 0x0000000000000000ull, // OR Mask - 0xFFFFFFFFFFFFFFFFull, // NAND Mask - }} - }, -// MSR_SYS_CFG (0xC0010010) -// bit[21] - MtrrTom2En = 1 - { - MsrRegister, - { - AMD_FAMILY_12, // CpuFamily - AMD_F12_ALL // CpuRevision - }, - {AMD_PF_ALL}, // platformFeatures - {{ - MSR_SYS_CFG, // MSR Address - (UINT64) (1 << 21), // OR Mask - (UINT64) (1 << 21), // NAND Mask - }} - }, -// MSR_HWCR (0xC0010015) -// bit[4] - INVD_WBINVD = 1 - { - MsrRegister, - { - AMD_FAMILY_12, // CpuFamily - AMD_F12_ALL // CpuRevision - }, - {AMD_PF_ALL}, // platformFeatures - {{ - MSR_HWCR, // MSR Address - 0x0000000000000010ull, // OR Mask - 0x0000000000000010ull, // NAND Mask - }} - }, -// MSR_CSTATE_ADDRESS (0xC0010073) -// bit[15:0] - CstateAddr = 0 - { - MsrRegister, - { - AMD_FAMILY_12, // CpuFamily - AMD_F12_ALL // CpuRevision - }, - {AMD_PF_ALL}, // platformFeatures - {{ - MSR_CSTATE_ADDRESS, // MSR Address - 0x0000000000000000ull, // OR Mask - 0x000000000000FFFFull, // NAND Mask - }} - }, -// MSR_BU_CFG2 (0xC001102A) -// bit[50] - RdMmExtCfgDwDis = 1 -// bit[56] - L2ClkGatingEn = 1 -// bits[58:57] - L2HystCnt = 3 - { - MsrRegister, - { - AMD_FAMILY_12, // CpuFamily - AMD_F12_ALL // CpuRevision - }, - {AMD_PF_ALL}, // platformFeatures - {{ - MSR_BU_CFG2, // MSR Address - 0x0704000000000000ull, // OR Mask - 0x0704000000000000ull, // NAND Mask - }} - }, -// MSR_OSVW_ID_Length (0xC0010140) -// bit[15:0] = 4 - { - MsrRegister, - { - AMD_FAMILY_12, // CpuFamily - AMD_F12_ALL // CpuRevision - }, - {AMD_PF_ALL}, // platformFeatures - {{ - MSR_OSVW_ID_Length, // MSR Address - 0x0000000000000004ull, // OR Mask - 0x000000000000FFFFull, // NAND Mask - }} - }, -// MSR_OSVW_Status (0xC0010141) -// bits[2:0] = 0 reserved, must be zero -// bit[3] = 1 for Erratum #383 - { - MsrRegister, - { - AMD_FAMILY_12, // CpuFamily - AMD_F12_LN_Ax // CpuRevision - }, - {AMD_PF_ALL}, // platformFeatures - {{ - MSR_OSVW_Status, // MSR Address - 0x0000000000000008ull, // OR Mask - 0x000000000000000Full, // NAND Mask - }} - }, -// This MSR should be set after the code that most errata would be applied in -// MSR_MC0_CTL (0x00000400) -// bits[63:0] = 0xFFFFFFFFFFFFFFFF - { - MsrRegister, - { - AMD_FAMILY_12, // CpuFamily - AMD_F12_ALL // CpuRevision - }, - {AMD_PF_ALL}, // platformFeatures - {{ - MSR_MC0_CTL, // MSR Address - 0xFFFFFFFFFFFFFFFFull, // OR Mask - 0xFFFFFFFFFFFFFFFFull, // NAND Mask - }} - } -}; - -CONST REGISTER_TABLE ROMDATA F12MsrRegisterTable = { - AllCores, - (sizeof (F12MsrRegisters) / sizeof (TABLE_ENTRY_FIELDS)), - (TABLE_ENTRY_FIELDS *) &F12MsrRegisters, -}; - - diff --git a/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x12/cpuF12PciTables.c b/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x12/cpuF12PciTables.c deleted file mode 100644 index d6ebb89c34..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x12/cpuF12PciTables.c +++ /dev/null @@ -1,959 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * AMD Family_12 PCI tables with values as defined in BKDG - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: CPU/FAMILY/0x12 - * @e \$Revision: 45812 $ @e \$Date: 2011-01-22 07:45:25 +0800 (Sat, 22 Jan 2011) $ - * - */ -/* - ****************************************************************************** - * - * Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - ****************************************************************************** - */ - -/*---------------------------------------------------------------------------------------- - * M O D U L E S U S E D - *---------------------------------------------------------------------------------------- - */ -#include "AGESA.h" -#include "cpuRegisters.h" -#include "Table.h" -#include "Filecode.h" -CODE_GROUP (G1_PEICC) -RDATA_GROUP (G1_PEICC) - -#define FILECODE PROC_CPU_FAMILY_0X12_CPUF12PCITABLES_FILECODE - -/*---------------------------------------------------------------------------------------- - * D E F I N I T I O N S A N D M A C R O S - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------- - * T Y P E D E F S A N D S T R U C T U R E S - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------- - * P R O T O T Y P E S O F L O C A L F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------- - * E X P O R T E D F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ - -// P C I T a b l e s -// ---------------------- - -STATIC CONST TABLE_ENTRY_FIELDS ROMDATA F12PciRegisters[] = -{ -// Function 0 - Link Config - -// D18F0x68 - Link Transaction Control -// bit[11] RespPassPW = 1 -// bits[19:17] for 8bit APIC config -// bits[22:21] DsNpReqLmt = 1 - { - PciRegister, - { - AMD_FAMILY_12, // CpuFamily - AMD_F12_ALL // CpuRevision - }, - {AMD_PF_ALL}, // platformFeatures - {{ - MAKE_SBDFO (0, 0, 24, FUNC_0, 0x68), // Address - 0x002E0800ull, // regData - 0x006E0800ull, // regMask - }} - }, - -// Function 3 - Misc. Control - -// D18F3x40 - MCA NB Control -// bit[8] MstrAbortEn = 1 - { - PciRegister, - { - AMD_FAMILY_12, // CpuFamily - AMD_F12_ALL // CpuRevision - }, - {AMD_PF_ALL}, // platformFeatures - {{ - MAKE_SBDFO (0, 0, 24, FUNC_3, 0x40), // Address - 0x00000100ull, // regData - 0x00000100ull, // regMask - }} - }, -// D18F3x44 - MCA NB Configuration -// bit[27] NbMcaToMstCpuEn = 1 -// bit[25] DisPciCfgCpuErrRsp = 1 -// bit[21] SyncOnAnyErrEn = 1 -// bit[20] SyncOnWDTEn = 1 -// bits[13:12] WDTBaseSel = 0 -// bits[11:9] WDTCntSel[2:0] = 0 -// bit[6] CpuErrDis = 1 - { - PciRegister, - { - AMD_FAMILY_12, // CpuFamily - AMD_F12_ALL // CpuRevision - }, - {AMD_PF_ALL}, // platformFeatures - {{ - MAKE_SBDFO (0, 0, 24, FUNC_3, 0x44), // Address - 0x0A300040ull, // regData - 0x0A303E40ull, // regMask - }} - }, -// D18F3x6C - Upstream Data Buffer Count -// bits[3:0] UpLoPreqDBC = 0x0E -// bits[7:4] UpLoNpreqDBC = 1 -// bits[11:8] UpLoRespDBC = 1 -// bits[19:16] UpHiPreqDBC = 0 -// bits[23:20] UpHiNpreqDBC = 0 - { - PciRegister, - { - AMD_FAMILY_12, // CpuFamily - AMD_F12_ALL // CpuRevision - }, - {AMD_PF_ALL}, // platformFeatures - {{ - MAKE_SBDFO(0, 0, 24, FUNC_3, 0x6C), // Address - 0x0000011Eull, // regData - 0x00FF0FFFull, // regMask - }} - }, -// D18F3x74 - Upstream Command Buffer Count -// bits[3:0] UpLoPreqCBC = 7 -// bits[7:4] UpLoNpreqCBC = 9 -// bits[11:8] UpLoRespCBC = 8 -// bits[19:16] UpHiPreqCBC = 0 -// bits[23:20] UpHiNpreqCBC = 0 - { - PciRegister, - { - AMD_FAMILY_12, // CpuFamily - AMD_F12_ALL // CpuRevision - }, - {AMD_PF_ALL}, // platformFeatures - {{ - MAKE_SBDFO(0, 0, 24, FUNC_3, 0x74), // Address - 0x00000897ull, // regData - 0x00FF0FFFull, // regMask - }} - }, -// D18F3x7C - In-Flight Queue Buffer Allocation -// bits[5:0] CpuBC = 1 -// bits[13:8] LoPriPBC = 1 -// bits[21:16] LoPriNPBC = 1 -// bits[29:24] FreePoolBC = 0x19 - { - PciRegister, - { - AMD_FAMILY_12, // CpuFamily - AMD_F12_ALL // CpuRevision - }, - {AMD_PF_ALL}, // platformFeatures - {{ - MAKE_SBDFO (0, 0, 24, FUNC_3, 0x7C), // Address - 0x19010101ull, // regData - 0x3F3F3F3Full, // regMask - }} - }, -// D18F3x84 - ACPI Power State Control High -// bit[18] Smaf6DramMemClkTri = 1 -// bit[17] Smaf6DramSr = 1 -// bit[2] Smaf4DramMemClkTri = 1 -// bit[1] Smaf4DramSr = 1 - { - PciRegister, - { - AMD_FAMILY_12, // CpuFamily - AMD_F12_ALL // CpuRevision - }, - {AMD_PF_ALL}, // platformFeatures - {{ - MAKE_SBDFO (0, 0, 24, FUNC_3, 0x84), // Address - 0x00060006ull, // regData - 0x00060006ull, // regMask - }} - }, -// D18F3x8C - NB Configuration High -// bit[26] EnConvertToNonIsoc = 1 - { - PciRegister, - { - AMD_FAMILY_12, // CpuFamily - AMD_F12_ALL // CpuRevision - }, - {AMD_PF_ALL}, // platformFeatures - {{ - MAKE_SBDFO (0, 0, 24, FUNC_3, 0x8C), // Address - 0x04000000ull, // regData - 0x04000000ull, // regMask - }} - }, -// D18F3xA0 - Power Control Miscellaneous -// bit[9] SviHighFreqSel = 1 - { - PciRegister, - { - AMD_FAMILY_12, // CpuFamily - AMD_F12_ALL // CpuRevision - }, - {AMD_PF_ALL}, // platformFeatures - {{ - MAKE_SBDFO (0, 0, 24, FUNC_3, 0xA0), // Address - 0x00000200ull, // regData - 0x00000200ull, // regMask - }} - }, -// D18F3xA4 - Reported Temperature Control -// bits[12:8] PerStepTimeDn = 0xF -// bit [7] TmpSlewDnEn = 1 -// bits[6:5] TmpMaxDiffUp = 0x3 -// bits[4:0] PerStepTimeUp = 0xF - { - PciRegister, - { - AMD_FAMILY_12, // CpuFamily - AMD_F12_ALL // CpuRevision - }, - {AMD_PF_ALL}, // platformFeatures - {{ - MAKE_SBDFO (0, 0, 24, FUNC_3, 0xA4), // Address - 0x00000FEFull, // regData - 0x00001FFFull, // regMask - }} - }, -// D18F3xD4 - Clock Power Timing Control 0 -// bits[11:8] ClkRampHystSel = 0xF -// bits[15:12] OnionOutHyst = 0x4 -// bit[17] ClockGatingEnDram = 1 - { - PciRegister, - { - AMD_FAMILY_12, // CpuFamily - AMD_F12_ALL // CpuRevision - }, - {AMD_PF_ALL}, // platformFeatures - {{ - MAKE_SBDFO (0, 0, 24, FUNC_3, 0xD4), // Address - 0x00024F00ull, // regData - 0x0002FF00ull, // regMask - }} - }, -// D18F3xD4 - Clock Power Timing Control 0 -// bit[7] ShallowHaltDidAllow = 1 - { - PciRegister, - { - AMD_FAMILY_12, // CpuFamily - AMD_F12_LN_Bx // CpuRevision - }, - {AMD_PF_ALL}, // platformFeatures - {{ - MAKE_SBDFO (0, 0, 24, FUNC_3, 0xD4), // Address - 0x00000080ull, // regData - 0x00000080ull, // regMask - }} - }, -// D18F3xDC - Clock Power Timing Control 2 -// bits[29:27] NbClockGateHyst = 3 -// bit[30] NbClockGateEn = 0 - erratum #596 -// bit[31] CnbCifClockGateEn = 1 - { - PciRegister, - { - AMD_FAMILY_12, // CpuFamily - AMD_F12_ALL // CpuRevision - }, - {AMD_PF_ALL}, // platformFeatures - {{ - MAKE_SBDFO (0, 0, 24, FUNC_3, 0xDC), // Address - 0x98000000ull, // regData - 0xF8000000ull, // regMask - }} - }, -// D18F3x17C - In-Flight Queue Extended Buffer Allocation -// bits[5:0] HiPriPBC = 0 -// bits[13:8] HiPriNPBC = 0 - { - PciRegister, - { - AMD_FAMILY_12, // CpuFamily - AMD_F12_ALL // CpuRevision - }, - {AMD_PF_ALL}, // platformFeatures - {{ - MAKE_SBDFO (0, 0, 24, FUNC_3, 0x17C), // Address - 0x00000000ull, // regData - 0x00003F3Full, // regMask - }} - }, -// D18F3x180 - Extended NB MCA Configuration -// bit[2] WDTCntSel[3] = 0 -// bit[5] DisPciCfgCpuMstAbtRsp = 1 -// bit[21] SyncFloodOnCpuLeakErr = 1 - { - PciRegister, - { - AMD_FAMILY_12, // CpuFamily - AMD_F12_ALL // CpuRevision - }, - {AMD_PF_ALL}, // platformFeatures - {{ - MAKE_SBDFO (0, 0, 24, FUNC_3, 0x180), // Address - 0x00200020ull, // regData - 0x00200024ull, // regMask - }} - }, -// D18F3x188 - NB Extended Configuration -// bit[21] EnCpuSerWrBehindIoRd = 0 -// bit[23] EnCpuSerRdBehindIoRd = 0 -// bits[27:24] FeArbCpuWeightOverLoPrio = 0x0B -// bits[31:28] FeArbCpuWeightOverHiPrio = 1 - { - PciRegister, - { - AMD_FAMILY_12, // CpuFamily - AMD_F12_ALL // CpuRevision - }, - {AMD_PF_ALL}, // platformFeatures - {{ - MAKE_SBDFO (0, 0, 24, FUNC_3, 0x188), // Address - 0x1B000000ull, // regData - 0xFFA00000ull, // regMask - }} - }, - -// Function 4 - Extended Misc. Control - -// D18F4x104 - TDP Lock Accumulator -// bits[1:0] TdpLockDivVal = 1 -// bits[13:2] TdpLockDivRate = 0x190 -// bits[16:15] TdpLockDivValCpu = 1 -// bits[28:17] TdpLockDivRateCpu = 0x190 - { - PciRegister, - { - AMD_FAMILY_12, // CpuFamily - AMD_F12_ALL // CpuRevision - }, - {AMD_PF_ALL}, // platformFeatures - {{ - MAKE_SBDFO (0, 0, 24, FUNC_4, 0x104), // Address - 0x03208641ull, // regData - 0x1FFFBFFFull, // regMask - }} - }, -// D18F4x118 - C-state Control 1 -// bits[10:8] CstAct1 = 0 -// bits[2:0] CstAct0 = 0 - { - PciRegister, - { - AMD_FAMILY_12, // CpuFamily - AMD_F12_ALL // CpuRevision - }, - {AMD_PF_ALL}, // platformFeatures - {{ - MAKE_SBDFO (0, 0, 24, FUNC_4, 0x118), // Address - 0x00000000ull, // regData - 0x00000707ull, // regMask - }} - }, -// D18F4x120 - C-state Policy Control 1 -// bit[31] CstateMsgDis = 1 - { - PciRegister, - { - AMD_FAMILY_12, // CpuFamily - AMD_F12_ALL // CpuRevision - }, - {AMD_PF_ALL}, // platformFeatures - {{ - MAKE_SBDFO (0, 0, 24, FUNC_4, 0x120), // Address - 0x80000000ull, // regData - 0x80000000ull, // regMask - }} - }, -// D18F4x124 - C-state Monitor Control 1 -// bit[15] TimerTickIntvlScale = 1 -// bit[16] TrackTimerTickInterEn = 1 -// bit[17] IntMonCC6En = 1 -// bits[21:18] IntMonCC6Lmt = 4 -// bit[22] IntMonPkgC6En = 0 -// bits[26:23] IntMonPkgC6Lmt = 0xA - { - PciRegister, - { - AMD_FAMILY_12, // CpuFamily - AMD_F12_ALL // CpuRevision - }, - {AMD_PF_ALL}, // platformFeatures - {{ - MAKE_SBDFO (0, 0, 24, FUNC_4, 0x124), // Address - 0x05138000ull, // regData - 0x07FF8000ull, // regMask - }} - }, -// D18F4x134 - C-state Monitor Control 3 -// bits[3:0] IntRatePkgC6MaxDepth = 0 -// bits[7:4] IntRatePkgC6Threshold = 0 -// bits[10:8] IntRatePkgC6BurstLen = 1 -// bits[15:11] IntRatePkgC6DecrRate = 0x0A -// bits[19:16] IntRateCC6MaxDepth = 5 -// bits[23:20] IntRateCC6Threshold = 4 -// bits[26:24] IntRateCC6BurstLen = 5 -// bits[31:27] IntRateCC6DecrRate = 0x18 - { - PciRegister, - { - AMD_FAMILY_12, // CpuFamily - AMD_F12_ALL // CpuRevision - }, - {AMD_PF_ALL}, // platformFeatures - {{ - MAKE_SBDFO (0, 0, 24, FUNC_4, 0x134), // Address - 0xC5455100ull, // regData - 0xFFFFFFFFull, // regMask - }} - }, -// D18F4x13C - SMAF Code DID 1 -// bits[4:0] Smaf4Did = 0x0F -// bits[20:16] Smaf6Did = 0x0F - { - PciRegister, - { - AMD_FAMILY_12, // CpuFamily - AMD_F12_ALL // CpuRevision - }, - {AMD_PF_ALL}, // platformFeatures - {{ - MAKE_SBDFO (0, 0, 24, FUNC_4, 0x13C), // Address - 0x000F000Full, // regData - 0x001F001Full, // regMask - }} - }, -// D18F4x14C - LPMV Scalar 2 -// bits[25:24] ApmCstExtPol = 1 - { - PciRegister, - { - AMD_FAMILY_12, // CpuFamily - AMD_F12_ALL // CpuRevision - }, - {AMD_PF_ALL}, // platformFeatures - {{ - MAKE_SBDFO (0, 0, 24, FUNC_4, 0x14C), // Address - 0x01000000ull, // regData - 0x03000000ull, // regMask - }} - }, -// D18F4x14C - LPMV Scalar 2 -// bit[26] CstatePowerSel = 1 - { - PciRegister, - { - AMD_FAMILY_12, // CpuFamily - AMD_F12_LN_Bx // CpuRevision - }, - {AMD_PF_ALL}, // platformFeatures - {{ - MAKE_SBDFO (0, 0, 24, FUNC_4, 0x14C), // Address - 0x04000000ull, // regData - 0x04000000ull, // regMask - }} - }, -// D18F4x15C - Core Performance Boost Control -// bits[1:0] BoostSrc = 0 -// bit[29] BoostEnAllCores = 1 - { - PciRegister, - { - AMD_FAMILY_12, // CpuFamily - AMD_F12_ALL // CpuRevision - }, - {AMD_PF_ALL}, // platformFeatures - {{ - MAKE_SBDFO (0, 0, 24, FUNC_4, 0x15C), // Address - 0x20000000ull, // regData - 0x20000003ull, // regMask - }} - }, -// D18F4x15C - Core Performance Boost Control -// bit[28] IgnoreBoostThresh = 1 - { - PciRegister, - { - AMD_FAMILY_12, // CpuFamily - AMD_F12_LN_Bx // CpuRevision - }, - {AMD_PF_ALL}, // platformFeatures - {{ - MAKE_SBDFO (0, 0, 24, FUNC_4, 0x15C), // Address - 0x10000000ull, // regData - 0x10000000ull, // regMask - }} - }, -// D18F4x1A4 - C-state Monitor Mask -// bits[7:0] IntRateMonMask = 0xFC -// bits[15:8] TimerTickMonMask = 0xFF -// bits[23:16] NonC0MonMask = 0xFF -// bits[31:24] C0MonMask = 0xFF - { - PciRegister, - { - AMD_FAMILY_12, // CpuFamily - AMD_F12_ALL // CpuRevision - }, - {AMD_PF_ALL}, // platformFeatures - {{ - MAKE_SBDFO (0, 0, 24, FUNC_4, 0x1A4), // Address - 0xFFFFFFFCull, // regData - 0xFFFFFFFFull, // regMask - }} - }, -// D18F4x1A8 - CPU State Power Management Dynamic Control 0 -// bits[4:0] SingleHaltCpuDid = 8 -// bits[9:5] AllHaltCpuDid = 0x0F -// bit[15] CpuProbEn = 0 -// bits[22:20] PServiceTmr = 1 -// bit[23] PServiceTmrEn = 1 - { - PciRegister, - { - AMD_FAMILY_12, // CpuFamily - AMD_F12_ALL // CpuRevision - }, - {AMD_PF_ALL}, // platformFeatures - {{ - MAKE_SBDFO (0, 0, 24, FUNC_4, 0x1A8), // Address - 0x009001E8ull, // regData - 0x00F083FFull, // regMask - }} - }, -// D18F4x1AC - CPU State Power Management Dynamic Control 1 -// bits[9:5] C6Did = 0x0F - { - PciRegister, - { - AMD_FAMILY_12, // CpuFamily - AMD_F12_ALL // CpuRevision - }, - {AMD_PF_ALL}, // platformFeatures - {{ - MAKE_SBDFO (0, 0, 24, FUNC_4, 0x1AC), // Address - 0x000001E0ull, // regData - 0x000003E0ull, // regMask - }} - }, -// D18F6x50 - Configuration Register Access Control -// bit[1] CfgAccAddrMode = 0 - { - PciRegister, - { - AMD_FAMILY_12, // CpuFamily - AMD_F12_ALL // CpuRevision - }, - {AMD_PF_ALL}, // platformFeatures - {{ - MAKE_SBDFO (0, 0, 24, FUNC_6, 0x50), // Address - 0x00000000ull, // regData - 0x00000002ull, // regMask - }} - }, -// D18F6x54 - Dram Arbitration Control FEQ Collision -// bits[7:0] FeqLoPrio = 0x20 -// bits[15:8] FeqMedPrio = 0x10 -// bits[23:16] FeqHiPrio = 8 -// bit[31] PpMode = 0 - { - PciRegister, - { - AMD_FAMILY_12, // CpuFamily - AMD_F12_ALL // CpuRevision - }, - {AMD_PF_ALL}, // platformFeatures - {{ - MAKE_SBDFO (0, 0, 24, FUNC_6, 0x54), // Address - 0x00081020ull, // regData - 0x80FFFFFFull, // regMask - }} - }, -// D18F6x154 - Dram Arbitration Control FEQ Collision -// bits[7:0] FeqLoPrio = 0x20 -// bits[15:8] FeqMedPrio = 0x10 -// bits[23:16] FeqHiPrio = 8 -// bit[31] PpMode = 0 - { - PciRegister, - { - AMD_FAMILY_12, // CpuFamily - AMD_F12_ALL // CpuRevision - }, - {AMD_PF_ALL}, // platformFeatures - {{ - MAKE_SBDFO (0, 0, 24, FUNC_6, 0x154), // Address - 0x00081020ull, // regData - 0x80FFFFFFull, // regMask - }} - }, -// D18F6x58 - Dram Arbitration Control Display Collision -// bits[7:0] DispLoPrio = 0x40 -// bits[15:8] DispMedPrio = 0x20 -// bits[23:16] DispHiPrio = 0x10 -// bits[31:24] DispUrgPrio = 0 - { - PciRegister, - { - AMD_FAMILY_12, // CpuFamily - AMD_F12_ALL // CpuRevision - }, - {AMD_PF_ALL}, // platformFeatures - {{ - MAKE_SBDFO (0, 0, 24, FUNC_6, 0x58), // Address - 0x00102040ull, // regData - 0xFFFFFFFFull, // regMask - }} - }, -// D18F6x158 - Dram Arbitration Control Display Collision -// bits[7:0] DispLoPrio = 0x40 -// bits[15:8] DispMedPrio = 0x20 -// bits[23:16] DispHiPrio = 0x10 -// bits[31:24] DispUrgPrio = 0 - { - PciRegister, - { - AMD_FAMILY_12, // CpuFamily - AMD_F12_ALL // CpuRevision - }, - {AMD_PF_ALL}, // platformFeatures - {{ - MAKE_SBDFO (0, 0, 24, FUNC_6, 0x158), // Address - 0x00102040ull, // regData - 0xFFFFFFFFull, // regMask - }} - }, -// D18F6x5C - Dram Arbitration Control FEQ Write Protect -// bits[7:0] FeqLoPrio = 0x20 -// bits[15:8] FeqMedPrio = 0x10 -// bits[23:16] FeqHiPrio = 8 -// bit[31] PpMode = 0 - { - PciRegister, - { - AMD_FAMILY_12, // CpuFamily - AMD_F12_ALL // CpuRevision - }, - {AMD_PF_ALL}, // platformFeatures - {{ - MAKE_SBDFO (0, 0, 24, FUNC_6, 0x5C), // Address - 0x00081020ull, // regData - 0x80FFFFFFull, // regMask - }} - }, -// D18F6x15C - Dram Arbitration Control FEQ Write Protect -// bits[7:0] FeqLoPrio = 0x20 -// bits[15:8] FeqMedPrio = 0x10 -// bits[23:16] FeqHiPrio = 8 -// bit[31] PpMode = 0 - { - PciRegister, - { - AMD_FAMILY_12, // CpuFamily - AMD_F12_ALL // CpuRevision - }, - {AMD_PF_ALL}, // platformFeatures - {{ - MAKE_SBDFO (0, 0, 24, FUNC_6, 0x15C), // Address - 0x00081020ull, // regData - 0x80FFFFFFull, // regMask - }} - }, -// D18F6x60 - Dram Arbitration Control Diplay Write Protect -// bits[7:0] DispLoPri = 0x20 -// bits[15:8] DispMedPrio = 0x10 -// bits[23:16] DispHiPrio = 8 -// bits[31:24] DispUrgPrio = 0 - { - PciRegister, - { - AMD_FAMILY_12, // CpuFamily - AMD_F12_ALL // CpuRevision - }, - {AMD_PF_ALL}, // platformFeatures - {{ - MAKE_SBDFO (0, 0, 24, FUNC_6, 0x60), // Address - 0x00081020ull, // regData - 0xFFFFFFFFull, // regMask - }} - }, -// D18F6x160 - Dram Arbitration Control Diplay Write Protect -// bits[7:0] DispLoPri = 0x20 -// bits[15:8] DispMedPrio = 0x10 -// bits[23:16] DispHiPrio = 8 -// bits[31:24] DispUrgPrio = 0 - { - PciRegister, - { - AMD_FAMILY_12, // CpuFamily - AMD_F12_ALL // CpuRevision - }, - {AMD_PF_ALL}, // platformFeatures - {{ - MAKE_SBDFO (0, 0, 24, FUNC_6, 0x160), // Address - 0x00081020ull, // regData - 0xFFFFFFFFull, // regMask - }} - }, -// D18F6x64 - Dram Arbitration Control FEQ Read Protect -// bits[7:0] FeqLoPrio = 0x10 -// bits[15:8] FeqMedPrio = 8 -// bits[23:16] FeqHiPrio = 4 -// bit[31] PpMode = 0 - { - PciRegister, - { - AMD_FAMILY_12, // CpuFamily - AMD_F12_ALL // CpuRevision - }, - {AMD_PF_ALL}, // platformFeatures - {{ - MAKE_SBDFO (0, 0, 24, FUNC_6, 0x64), // Address - 0x00040810ull, // regData - 0x80FFFFFFull, // regMask - }} - }, -// D18F6x164 - Dram Arbitration Control FEQ Read Protect -// bits[7:0] FeqLoPrio = 0x10 -// bits[15:8] FeqMedPrio = 8 -// bits[23:16] FeqHiPrio = 4 -// bit[31] PpMode = 0 - { - PciRegister, - { - AMD_FAMILY_12, // CpuFamily - AMD_F12_ALL // CpuRevision - }, - {AMD_PF_ALL}, // platformFeatures - {{ - MAKE_SBDFO (0, 0, 24, FUNC_6, 0x164), // Address - 0x00040810ull, // regData - 0x80FFFFFFull, // regMask - }} - }, -// D18F6x68 - Dram Arbitration Control Display Read Protect -// bits[7:0] DispLoPrio = 0x10 -// bits[15:8] DispMedPrio = 8 -// bits[23:16] DispHiPrio = 4 -// bits[31:24] DispUrgPrio = 0 - { - PciRegister, - { - AMD_FAMILY_12, // CpuFamily - AMD_F12_ALL // CpuRevision - }, - {AMD_PF_ALL}, // platformFeatures - {{ - MAKE_SBDFO (0, 0, 24, FUNC_6, 0x68), // Address - 0x00040810ull, // regData - 0xFFFFFFFFull, // regMask - }} - }, -// D18F6x168 - Dram Arbitration Control Display Read Protect -// bits[7:0] DispLoPrio = 0x10 -// bits[15:8] DispMedPrio = 8 -// bits[23:16] DispHiPrio = 4 -// bits[31:24] DispUrgPrio = 0 - { - PciRegister, - { - AMD_FAMILY_12, // CpuFamily - AMD_F12_ALL // CpuRevision - }, - {AMD_PF_ALL}, // platformFeatures - {{ - MAKE_SBDFO (0, 0, 24, FUNC_6, 0x168), // Address - 0x00040810ull, // regData - 0xFFFFFFFFull, // regMask - }} - }, -// D18F6x6C - Dram Arbitration Control FEQ Fairness Timer -// bits[7:0] FeqLoPrio = 0x80 -// bits[15:8] FeqMedPrio = 0x40 -// bits[23:16] FeqHiPrio = 0x20 - { - PciRegister, - { - AMD_FAMILY_12, // CpuFamily - AMD_F12_ALL // CpuRevision - }, - {AMD_PF_ALL}, // platformFeatures - {{ - MAKE_SBDFO (0, 0, 24, FUNC_6, 0x6C), // Address - 0x00204080ull, // regData - 0x00FFFFFFull, // regMask - }} - }, -// D18F6x16C - Dram Arbitration Control FEQ Fairness Timer -// bits[7:0] FeqLoPrio = 0x80 -// bits[15:8] FeqMedPrio = 0x40 -// bits[23:16] FeqHiPrio = 0x20 - { - PciRegister, - { - AMD_FAMILY_12, // CpuFamily - AMD_F12_ALL // CpuRevision - }, - {AMD_PF_ALL}, // platformFeatures - {{ - MAKE_SBDFO (0, 0, 24, FUNC_6, 0x16C), // Address - 0x00204080ull, // regData - 0x00FFFFFFull, // regMask - }} - }, -// D18F6x70 - Dram Arbitration Control Display Fairness Timer -// bits[7:0] DispLoPrio = 0x80 -// bits[15:8] DispMedPrio = 0x40 -// bits[23:16] DispHiPrio = 0x20 -// bits[31:24] DispUrPrio = 0 - { - PciRegister, - { - AMD_FAMILY_12, // CpuFamily - AMD_F12_ALL // CpuRevision - }, - {AMD_PF_ALL}, // platformFeatures - {{ - MAKE_SBDFO (0, 0, 24, FUNC_6, 0x70), // Address - 0x00204080ull, // regData - 0xFFFFFFFFull, // regMask - }} - }, -// D18F6x170 - Dram Arbitration Control Display Fairness Timer -// bits[7:0] DispLoPrio = 0x80 -// bits[15:8] DispMedPrio = 0x40 -// bits[23:16] DispHiPrio = 0x20 -// bits[31:24] DispUrPrio = 0 - { - PciRegister, - { - AMD_FAMILY_12, // CpuFamily - AMD_F12_ALL // CpuRevision - }, - {AMD_PF_ALL}, // platformFeatures - {{ - MAKE_SBDFO (0, 0, 24, FUNC_6, 0x170), // Address - 0x00204080ull, // regData - 0xFFFFFFFFull, // regMask - }} - }, -// D18F6x78 - Dram Prioritization and Arbitration Control -// bits[1:0] DispDbePrioEn = 3 -// bit[2] FeqDbePrioEn = 1 -// bit[3] DispArbCtrl = 0 -// bits[5:4] GlcEosDet = 3 -// bit[6] GlcEosDetDis = 0 - { - PciRegister, - { - AMD_FAMILY_12, // CpuFamily - AMD_F12_ALL // CpuRevision - }, - {AMD_PF_ALL}, // platformFeatures - {{ - MAKE_SBDFO (0, 0, 24, FUNC_6, 0x78), // Address - 0x00000037ull, // regData - 0x0000007Full, // regMask - }} - }, -// D18F6x90 - NB P-state Config Low -// bit[30] NbPsCtrlDis = 1 -// bit[29] NbPsForceSel = 0 -// bit[28] NbPsForceReq = 1 - { - PciRegister, - { - AMD_FAMILY_12, // CpuFamily - AMD_F12_ALL // CpuRevision - }, - {AMD_PF_ALL}, // platformFeatures - {{ - MAKE_SBDFO (0, 0, 24, FUNC_6, 0x90), // Address - 0x50000000ull, // regData - 0x70000000ull, // regMask - }} - }, -// D18F6x94 - NB P-state Config High -// bit[4] NbPs1NoTransOnDma = 0 -// bits[25:23] NbPsC0Timer = 4 - { - PciRegister, - { - AMD_FAMILY_12, // CpuFamily - AMD_F12_ALL // CpuRevision - }, - {AMD_PF_ALL}, // platformFeatures - {{ - MAKE_SBDFO (0, 0, 24, FUNC_6, 0x94), // Address - 0x02000000ull, // regData - 0x03800010ull, // regMask - }} - }, -// D18F6x9C - NCLK Reduction Control -// bits[6:0] NclkRedDiv = 0x78 -// bit[7] NclkRedSelfRefrAlways = 1 - { - PciRegister, - { - AMD_FAMILY_12, // CpuFamily - AMD_F12_ALL // CpuRevision - }, - {AMD_PF_ALL}, // platformFeatures - {{ - MAKE_SBDFO (0, 0, 24, FUNC_6, 0x9C), // Address - 0x000000F8ull, // regData - 0x000000FFull, // regMask - }} - } -}; - -CONST REGISTER_TABLE ROMDATA F12PciRegisterTable = { - PrimaryCores, - (sizeof (F12PciRegisters) / sizeof (TABLE_ENTRY_FIELDS)), - F12PciRegisters, -}; diff --git a/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x12/cpuF12PerCorePciTables.c b/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x12/cpuF12PerCorePciTables.c deleted file mode 100644 index 56ab0324a7..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x12/cpuF12PerCorePciTables.c +++ /dev/null @@ -1,104 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * AMD Family_12 Per Core PCI tables with values as defined in BKDG - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: CPU/FAMILY/0x12 - * @e \$Revision: 36764 $ @e \$Date: 2010-08-25 22:51:27 +0800 (Wed, 25 Aug 2010) $ - * - */ -/* - ****************************************************************************** - * - * Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - ****************************************************************************** - */ - -/*---------------------------------------------------------------------------------------- - * M O D U L E S U S E D - *---------------------------------------------------------------------------------------- - */ -#include "AGESA.h" -#include "cpuRegisters.h" -#include "Table.h" -#include "Filecode.h" -CODE_GROUP (G1_PEICC) -RDATA_GROUP (G1_PEICC) - -#define FILECODE PROC_CPU_FAMILY_0X12_CPUF12PERCOREPCITABLES_FILECODE - -/*---------------------------------------------------------------------------------------- - * D E F I N I T I O N S A N D M A C R O S - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------- - * T Y P E D E F S A N D S T R U C T U R E S - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------- - * P R O T O T Y P E S O F L O C A L F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------- - * E X P O R T E D F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ - -// Per Core P C I T a b l e s -// ---------------------- - -STATIC CONST TABLE_ENTRY_FIELDS ROMDATA F12PerCorePciRegisters[] = -{ -// D18F3x1CC - IBS Control -// bits[3:0] LvtOffset = 0 -// bit[8] LvtOffsetVal = 1 - { - PciRegister, - { - (UINT64) AMD_FAMILY_12, // CpuFamily - (UINT64) AMD_F12_ALL // CpuRevision - }, - {AMD_PF_ALL}, // platformFeatures - {{ - MAKE_SBDFO (0, 0, 24, FUNC_3, 0x1CC), // Address - 0x00000100ull, // regData - 0x0000010Full, // regMask - }} - } -}; - -CONST REGISTER_TABLE ROMDATA F12PerCorePciRegisterTable = { - AllCores, - (sizeof (F12PerCorePciRegisters) / sizeof (TABLE_ENTRY_FIELDS)), - F12PerCorePciRegisters, -}; - diff --git a/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x12/cpuF12PowerCheck.c b/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x12/cpuF12PowerCheck.c deleted file mode 100644 index d96f6ecae2..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x12/cpuF12PowerCheck.c +++ /dev/null @@ -1,364 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * AMD Family_12 P-State power check - * - * Performs the "Processor-Systemboard Power Delivery Compatibility Check" as - * described in the BKDG. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: CPU/F12 - * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $ - * - */ -/* - ****************************************************************************** - * - * Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - ****************************************************************************** - */ - -/*---------------------------------------------------------------------------------------- - * M O D U L E S U S E D - *---------------------------------------------------------------------------------------- - */ -#include "AGESA.h" -#include "amdlib.h" -#include "cpuF12PowerMgmt.h" -#include "cpuRegisters.h" -#include "cpuApicUtilities.h" -#include "cpuServices.h" -#include "GeneralServices.h" -#include "cpuEarlyInit.h" -#include "cpuFamilyTranslation.h" -#include "cpuF12PowerCheck.h" -#include "Filecode.h" -CODE_GROUP (G1_PEICC) -RDATA_GROUP (G1_PEICC) - -#define FILECODE PROC_CPU_FAMILY_0X12_CPUF12POWERCHECK_FILECODE - -/*---------------------------------------------------------------------------------------- - * D E F I N I T I O N S A N D M A C R O S - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------- - * T Y P E D E F S A N D S T R U C T U R E S - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------- - * P R O T O T Y P E S O F L O C A L F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ -VOID -STATIC -F12PmPwrCheckCore ( - IN VOID *ErrorData, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -VOID -STATIC -F12PmPwrChkCopyPstate ( - IN UINT8 Dest, - IN UINT8 Src, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -/*---------------------------------------------------------------------------------------- - * E X P O R T E D F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------*/ -/** - * Family 12h core 0 entry point for performing the family 12h Processor- - * Systemboard Power Delivery Check. - * - * The steps are as follows: - * 1. Starting with P0, loop through all P-states until a passing state is - * found. A passing state is one in which the current required by the - * CPU is less than the maximum amount of current that the system can - * provide to the CPU. If P0 is under the limit, no further action is - * necessary. - * 2. If at least one P-State is under the limit & at least one P-State is - * over the limit, the BIOS must: - * a. Clear both D18F4x15C[BoostSrc] and D18F4x15C[NumBoostStates] to 0. - * b. If the processor's current P-State is disabled by the power check, - * then the BIOS must request a transition to an enabled P-state - * using MSRC001_0062[PstateCmd] and wait for MSRC001_0063[CurPstate] - * to reflect the new value. - * c. Copy the contents of the enabled P-state MSRs to the highest - * performance P-state locations. - * d. Request a P-state transition to the P-state MSR containing the - * COF/VID values currently applied. - * e. Adjust the following P-state parameters affected by the P-state - * MSR copy by subtracting the number of P-states that are disabled - * by the power check. - * 1. D18F3x64[HtcPstateLimit] - * 2. D18F3xDC[PstateMaxVal] - * 3. If all P-States are over the limit, the BIOS must: - * a. Clear both D18F4x15C[BoostSrc] and D18F4x15C[NumBoostStates] to 0. - * b. If the processor's current P-State is != D18F3xDC[PstateMaxVal], then - * write D18F3xDC[PstateMaxVal] to MSRC001_0062[PstateCmd] and wait for - * MSRC001_0063[CurPstate] to reflect the new value. - * c. If D18F3xDC[PstateMaxVal]!= 000b, copy the contents of the P-state - * MSR pointed to by D18F3xDC[PstateMaxVal] to MSRC001_0064 and set - * MSRC001_0064[PstateEn] - * d. Write 000b to MSRC001_0062[PstateCmd] and wait for MSRC001_0063 - * [CurPstate] to reflect the new value. - * e. Adjust the following P-state parameters to zero: - * 1. D18F3x64[HtcPstateLimit] - * 2. D18F3xDC[PstateMaxVal] - * - * @param[in] FamilySpecificServices The current Family Specific Services. - * @param[in] CpuEarlyParams Service parameters. - * @param[in] StdHeader Config handle for library and services. - * - */ -VOID -F12PmPwrCheck ( - IN CPU_SPECIFIC_SERVICES *FamilySpecificServices, - IN AMD_CPU_EARLY_PARAMS *CpuEarlyParams, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - UINT8 DisPsNum; - UINT8 PsMaxVal; - UINT8 Pstate; - UINT32 ProcIddMax; - UINT32 LocalPciRegister; - UINT32 Socket; - UINT32 Module; - UINT32 Core; - UINT32 PstateLimit; - PCI_ADDR PciAddress; - UINT64 LocalMsrRegister; - AP_TASK TaskPtr; - AGESA_STATUS IgnoredSts; - PWRCHK_ERROR_DATA ErrorData; - - // get the socket number - IdentifyCore (StdHeader, &Socket, &Module, &Core, &IgnoredSts); - ErrorData.SocketNumber = (UINT8) Socket; - - ASSERT (Core == 0); - - // get the Max P-state value - for (PsMaxVal = NM_PS_REG - 1; PsMaxVal != 0; --PsMaxVal) { - LibAmdMsrRead (PS_REG_BASE + PsMaxVal, &LocalMsrRegister, StdHeader); - if (((PSTATE_MSR *) &LocalMsrRegister)->PsEnable == 1) { - break; - } - } - - ErrorData.HwPstateNumber = (UINT8) (PsMaxVal + 1); - - DisPsNum = 0; - for (Pstate = 0; Pstate < ErrorData.HwPstateNumber; Pstate++) { - if (FamilySpecificServices->GetProcIddMax (FamilySpecificServices, Pstate, &ProcIddMax, StdHeader)) { - if (ProcIddMax > CpuEarlyParams->PlatformConfig.VrmProperties[CoreVrm].CurrentLimit) { - // Add to event log the Pstate that exceeded the current limit - PutEventLog (AGESA_WARNING, - CPU_EVENT_PM_PSTATE_OVERCURRENT, - Socket, Pstate, 0, 0, StdHeader); - DisPsNum++; - } else { - break; - } - } - } - - // If all P-state registers are disabled, move P[PsMaxVal] to P0 - // and transition to P0, then wait for CurPstate = 0 - - ErrorData.AllowablePstateNumber = ((PsMaxVal + 1) - DisPsNum); - - // We only need to log this event on the BSC - if (ErrorData.AllowablePstateNumber == 0) { - PutEventLog (AGESA_FATAL, - CPU_EVENT_PM_ALL_PSTATE_OVERCURRENT, - Socket, 0, 0, 0, StdHeader); - } - - if (DisPsNum != 0) { - // Clear both D18F4x15C[BoostSrc] and D18F4x15C[NumBoostStates] to 0 - PciAddress.AddressValue = CPB_CTRL_PCI_ADDR; - LibAmdPciRead (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader); - ((CPB_CTRL_REGISTER *) &LocalPciRegister)->BoostSrc = 0; - ((CPB_CTRL_REGISTER *) &LocalPciRegister)->NumBoostStates = 0; - LibAmdPciWrite (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader); - - TaskPtr.FuncAddress.PfApTaskI = F12PmPwrCheckCore; - TaskPtr.DataTransfer.DataSizeInDwords = SIZE_IN_DWORDS (PWRCHK_ERROR_DATA); - TaskPtr.DataTransfer.DataPtr = &ErrorData; - TaskPtr.DataTransfer.DataTransferFlags = 0; - TaskPtr.ExeFlags = WAIT_FOR_CORE; - ApUtilRunCodeOnAllLocalCoresAtEarly (&TaskPtr, StdHeader, CpuEarlyParams); - - // Final Step - // D18F3x64[HtPstatelimit] -= disPsNum - // D18F3xDC[PstateMaxVal]-= disPsNum - - PciAddress.AddressValue = HTC_PCI_ADDR; - LibAmdPciRead (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader); // D18F3x64 - PstateLimit = ((HTC_REGISTER *) &LocalPciRegister)->HtcPstateLimit; - if (PstateLimit > DisPsNum) { - PstateLimit -= DisPsNum; - } else { - PstateLimit = 0; - } - ((HTC_REGISTER *) &LocalPciRegister)->HtcPstateLimit = PstateLimit; - LibAmdPciWrite (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader); // D18F3x64 - - PciAddress.AddressValue = CPTC2_PCI_ADDR; - LibAmdPciRead (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader); // D18F3xDC - PstateLimit = ((CLK_PWR_TIMING_CTRL2_REGISTER *) &LocalPciRegister)->PstateMaxVal; - if (PstateLimit > DisPsNum) { - PstateLimit -= DisPsNum; - } else { - PstateLimit = 0; - } - ((CLK_PWR_TIMING_CTRL2_REGISTER *) &LocalPciRegister)->PstateMaxVal = PstateLimit; - LibAmdPciWrite (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader); // D18F3xDC - } -} - - -/*---------------------------------------------------------------------------------------*/ -/** - * Core-level error handler called if any p-states were determined to be out - * of range for the mother board. - * - * This function implements steps 2b-d and 3b-d on each core. - * - * @param[in] ErrorData Details about the error condition. - * @param[in] StdHeader Config handle for library and services. - * - */ -VOID -STATIC -F12PmPwrCheckCore ( - IN VOID *ErrorData, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - UINT8 i; - UINT8 PsMaxVal; - UINT8 DisPsNum; - UINT8 CurrentPs; - UINT64 LocalMsrRegister; - CPU_SPECIFIC_SERVICES *FamilySpecificServices; - - GetCpuServicesOfCurrentCore ((const CPU_SPECIFIC_SERVICES **) &FamilySpecificServices, StdHeader); - - PsMaxVal = (((PWRCHK_ERROR_DATA *) ErrorData)->HwPstateNumber - 1); - DisPsNum = (((PWRCHK_ERROR_DATA *) ErrorData)->HwPstateNumber - - ((PWRCHK_ERROR_DATA *) ErrorData)->AllowablePstateNumber); - - LibAmdMsrRead (MSR_PSTATE_STS, &LocalMsrRegister, StdHeader); - CurrentPs = (UINT8) (((PSTATE_STS_MSR *) &LocalMsrRegister)->CurPstate); - - if (((PWRCHK_ERROR_DATA *) ErrorData)->AllowablePstateNumber == 0) { - - // Step 1 - // Transition to Pstate Max if not there already - - if (CurrentPs != PsMaxVal) { - FamilySpecificServices->TransitionPstate (FamilySpecificServices, PsMaxVal, (BOOLEAN) TRUE, StdHeader); - } - - - // Step 2 - // If Pstate Max is not P0, copy Pstate max contents to P0 and switch - // to P0. - - if (PsMaxVal != 0) { - F12PmPwrChkCopyPstate (0, PsMaxVal, StdHeader); - FamilySpecificServices->TransitionPstate (FamilySpecificServices, (UINT8) 0, (BOOLEAN) TRUE, StdHeader); - } - } else { - - // move remaining P-state register(s) up - // Step 1 - // Transition to a valid Pstate if current Pstate has been disabled - - if (CurrentPs < DisPsNum) { - FamilySpecificServices->TransitionPstate (FamilySpecificServices, DisPsNum, (BOOLEAN) TRUE, StdHeader); - CurrentPs = DisPsNum; - } - - // Step 2 - // Move enabled Pstates up and disable the remainder - - for (i = 0; (i + DisPsNum) <= PsMaxVal; ++i) { - F12PmPwrChkCopyPstate (i, (i + DisPsNum), StdHeader); - } - - // Step 3 - // Transition to current COF/VID at shifted location - - CurrentPs = (CurrentPs - DisPsNum); - FamilySpecificServices->TransitionPstate (FamilySpecificServices, CurrentPs, (BOOLEAN) TRUE, StdHeader); - } - i = ((PWRCHK_ERROR_DATA *) ErrorData)->AllowablePstateNumber; - if (i == 0) { - i++; - } - while (i <= PsMaxVal) { - FamilySpecificServices->DisablePstate (FamilySpecificServices, i, StdHeader); - i++; - } -} - - -/*---------------------------------------------------------------------------------------*/ -/** - * Copies the contents of one P-State MSR to another. - * - * @param[in] Dest Destination p-state number - * @param[in] Src Source p-state number - * @param[in] StdHeader Config handle for library and services - * - */ -VOID -STATIC -F12PmPwrChkCopyPstate ( - IN UINT8 Dest, - IN UINT8 Src, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - UINT64 LocalMsrRegister; - - LibAmdMsrRead ((UINT32) (PS_REG_BASE + Src), &LocalMsrRegister, StdHeader); - LibAmdMsrWrite ((UINT32) (PS_REG_BASE + Dest), &LocalMsrRegister, StdHeader); -} - diff --git a/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x12/cpuF12PowerCheck.h b/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x12/cpuF12PowerCheck.h deleted file mode 100644 index f044217007..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x12/cpuF12PowerCheck.h +++ /dev/null @@ -1,81 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * AMD Family_12 Power related functions and structures - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: CPU/F12 - * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $ - * - */ -/* - ****************************************************************************** - * - * Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - ****************************************************************************** - */ - -#ifndef _CPU_F12_POWER_CHECK_H_ -#define _CPU_F12_POWER_CHECK_H_ - - -/*--------------------------------------------------------------------------------------- - * M I X E D (Definitions And Macros / Typedefs, Structures, Enums) - *--------------------------------------------------------------------------------------- - */ - - -/*--------------------------------------------------------------------------------------- - * D E F I N I T I O N S A N D M A C R O S - *--------------------------------------------------------------------------------------- - */ - - -/*--------------------------------------------------------------------------------------- - * T Y P E D E F S, S T R U C T U R E S, E N U M S - *--------------------------------------------------------------------------------------- - */ -/// Power Check Error Data -typedef struct { - UINT8 SocketNumber; ///< Socket Number - UINT8 HwPstateNumber; ///< Hardware P-state Number - UINT8 AllowablePstateNumber; ///< Allowable P-state Number -} PWRCHK_ERROR_DATA; - -/*--------------------------------------------------------------------------------------- - * F U N C T I O N P R O T O T Y P E - *--------------------------------------------------------------------------------------- - */ -VOID -F12PmPwrCheck ( - IN CPU_SPECIFIC_SERVICES *FamilySpecificServices, - IN AMD_CPU_EARLY_PARAMS *CpuEarlyParams, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -#endif // _CPU_F12_POWER_CHECK_H_ diff --git a/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x12/cpuF12PowerMgmt.h b/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x12/cpuF12PowerMgmt.h deleted file mode 100644 index 9701304953..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x12/cpuF12PowerMgmt.h +++ /dev/null @@ -1,511 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * AMD Family_12 Power Management related stuff - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: CPU/F12 - * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $ - * - */ -/* - ****************************************************************************** - * - * Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - ****************************************************************************** - */ - -#ifndef _CPUF12POWERMGMT_H_ -#define _CPUF12POWERMGMT_H_ - -/* - * Family 12h CPU Power Management MSR definitions - * - */ - -/* P-state Current Limit Register 0xC0010061 */ -#define MSR_PSTATE_CURRENT_LIMIT 0xC0010061 - -/// Pstate Current Limit MSR Register -typedef struct { - UINT64 CurPstateLimit:3; ///< Current Pstate Limit - UINT64 :1; ///< Reserved - UINT64 PstateMaxVal:3; ///< Pstate Max Value - UINT64 :57; ///< Reserved -} PSTATE_CURLIM_MSR; - - -/* P-state Control Register 0xC0010062 */ -#define MSR_PSTATE_CTL 0xC0010062 - -/// Pstate Control MSR Register -typedef struct { - UINT64 PstateCmd:3; ///< Pstate change command - UINT64 :61; ///< Reserved -} PSTATE_CTRL_MSR; - - -/* P-state Status Register 0xC0010063 */ -#define MSR_PSTATE_STS 0xC0010063 - -/// Pstate Status MSR Register -typedef struct { - UINT64 CurPstate:3; ///< Current Pstate - UINT64 :61; ///< Reserved -} PSTATE_STS_MSR; - - -/* P-state Registers 0xC001006[B:4] */ -#define MSR_PSTATE_0 0xC0010064 -#define MSR_PSTATE_1 0xC0010065 -#define MSR_PSTATE_2 0xC0010066 -#define MSR_PSTATE_3 0xC0010067 -#define MSR_PSTATE_4 0xC0010068 -#define MSR_PSTATE_5 0xC0010069 -#define MSR_PSTATE_6 0xC001006A -#define MSR_PSTATE_7 0xC001006B - -#define PS_REG_BASE MSR_PSTATE_0 /* P-state Register base */ -#define PS_MAX_REG MSR_PSTATE_7 /* Maximum P-State Register */ -#define PS_MIN_REG MSR_PSTATE_0 /* Minimum P-State Register */ -#define NM_PS_REG 8 /* number of P-state MSR registers */ - -/// Pstate MSR -typedef struct { - UINT64 CpuDid:4; ///< CPU core divisor identifier - UINT64 CpuFid:5; ///< CPU core frequency identifier - UINT64 CpuVid:7; ///< CPU core VID - UINT64 :16; ///< Reserved - UINT64 IddValue:8; ///< Current value field - UINT64 IddDiv:2; ///< Current divisor field - UINT64 :21; ///< Reserved - UINT64 PsEnable:1; ///< P-state Enable -} PSTATE_MSR; - - -/* COFVID Control Register 0xC0010070 */ -#define MSR_COFVID_CTL 0xC0010070 - -/// COFVID Control MSR Register -typedef struct { - UINT64 CpuDid:4; ///< CPU core divisor identifier - UINT64 CpuDidMSD:5; ///< CPU core frequency identifier - UINT64 CpuVid:7; ///< CPU core VID - UINT64 PstateId:3; ///< P-state identifier - UINT64 IgnoreFidVidDid:1; ///< Ignore FID, VID, and DID - UINT64 :44; ///< Reserved -} COFVID_CTRL_MSR; - - -/* COFVID Status Register 0xC0010071 */ -#define MSR_COFVID_STS 0xC0010071 - -/// COFVID Status MSR Register -typedef struct { - UINT64 CurCpuDid:4; ///< Current CPU core divisor ID - UINT64 CurCpuDidMSD:5; ///< Current CPU core frequency ID - UINT64 CurCpuVid:7; ///< Current CPU core VID - UINT64 CurPstate:3; ///< Current P-state - UINT64 :1; ///< Reserved - UINT64 PstateInProgress:1; ///< P-state change in progress - UINT64 :4; ///< Reserved - UINT64 CurNbVid:7; ///< Current northbridge VID - UINT64 StartupPstate:3; ///< Startup P-state number - UINT64 MaxVid:7; ///< Maximum voltage - UINT64 MinVid:7; ///< Minimum voltage - UINT64 MainPllOpFreqIdMax:6; ///< Main PLL operating frequency ID maximum - UINT64 :1; ///< Reserved - UINT64 CurPstateLimit:3; ///< Current P-state Limit - UINT64 :5; ///< Reserved -} COFVID_STS_MSR; - - -/* C-state Address Register 0xC0010073 */ -#define MSR_CSTATE_ADDRESS 0xC0010073 - -/// C-state Address MSR Register -typedef struct { - UINT64 CstateAddr:16; ///< C-state address - UINT64 :48; ///< Reserved -} CSTATE_ADDRESS_MSR; - - -/* CPU Watchdog Timer Register 0xC0010074 */ -#define MSR_CPU_WDT 0xC0010074 - -/// CPU Watchdog Timer Register -typedef struct { - UINT64 CpuWdtEn:1; ///< CPU watchdog timer enable - UINT64 CpuWdtTimeBase:2; ///< CPU watchdog timer time base - UINT64 CpuWdtCountSel:4; ///< CPU watchdog timer count select - UINT64 :57; ///< Reserved -} CPU_WDT_MSR; - - -/* - * Family 12h CPU Power Management PCI definitions - * - */ - -/* Memory controller configuration low register D18F2x118 */ -#define MEM_CFG_LOW_REG 0x118 -#define MEM_CFG_LOW_PCI_ADDR (MAKE_SBDFO (0, 0, 0x18, FUNC_2, MEM_CFG_LOW_REG)) - -/// Memory Controller Configuration Low -typedef struct { - UINT32 MctPriCpuRd:2; ///< CPU read priority - UINT32 MctPriCpuWr:2; ///< CPU write priority - UINT32 MctPriHiRd:2; ///< High-priority VC set read priority - UINT32 MctPriHiWr:2; ///< High-priority VC set write priority - UINT32 MctPriDefault:2; ///< Default non-write priority - UINT32 MctPriWr:2; ///< Default write priority - UINT32 :7; ///< Reserved - UINT32 C6DramLock:1; ///< C6 DRAM lock - UINT32 :8; ///< Reserved - UINT32 MctVarPriCntLmt:4; ///< Variable priority time limit -} MEM_CFG_LOW_REGISTER; - - -/* Hardware thermal control register D18F3x64 */ -#define HTC_REG 0x64 -#define HTC_PCI_ADDR (MAKE_SBDFO (0, 0, 0x18, FUNC_3, HTC_REG)) - -/// Hardware Thermal Control PCI Register -typedef struct { - UINT32 HtcEn:1; ///< HTC Enable - UINT32 :3; ///< Reserved - UINT32 HtcAct:1; ///< HTC Active State - UINT32 HtcActSts:1; ///< HTC Active Status - UINT32 PslApicHiEn:1; ///< P-state limit higher APIC int enable - UINT32 PslApicLoEn:1; ///< P-state limit lower APIC int enable - UINT32 :8; ///< Reserved - UINT32 HtcTmpLmt:7; ///< HTC temperature limit - UINT32 HtcSlewSel:1; ///< HTC slew-controlled temp select - UINT32 HtcHystLmt:4; ///< HTC hysteresis - UINT32 HtcPstateLimit:3; ///< HTC P-state limit select - UINT32 HtcLock:1; ///< HTC lock -} HTC_REGISTER; - -/* Power Control Miscellaneous Register D18F3xA0 */ -#define PW_CTL_MISC_REG 0xA0 -#define PW_CTL_MISC_PCI_ADDR (MAKE_SBDFO (0, 0, 0x18, FUNC_3, PW_CTL_MISC_REG)) - -/// Power Control Miscellaneous PCI Register -typedef struct { - UINT32 PsiVid:7; ///< PSI_L VID threshold - UINT32 PsiVidEn:1; ///< PSI_L VID enable - UINT32 :1; ///< Reserved - UINT32 SviHighFreqSel:1; ///< SVI high frequency select - UINT32 :6; ///< Reserved - UINT32 ConfigId:12; ///< Configuration Identifier - UINT32 :3; ///< Reserved - UINT32 CofVidProg:1; ///< COF and VID of P-states programmed -} POWER_CTRL_MISC_REGISTER; - - -/* Clock Power/Timing Control 0 Register D18F3xD4 */ -#define CPTC0_REG 0xD4 -#define CPTC0_PCI_ADDR (MAKE_SBDFO (0, 0, 0x18, FUNC_3, CPTC0_REG)) - -/// Clock Power Timing Control PCI Register -typedef struct { - UINT32 MainPllOpFreqId:6; ///< Main PLL Fid - UINT32 :1; ///< Main PLL Fid Enable - UINT32 ShallowHaltDidAllow:1; ///< Allow Shallow Halt Did - UINT32 ClkRampHystSel:4; ///< Clock Ramp Hysteresis Select - UINT32 OnionOutHyst:4; ///< ONION outbound hysteresis - UINT32 DisNclkGatingIdle:1; ///< Disable NCLK gating when idle - UINT32 ClkGatingEnDram:1; ///< Clock gating enable DRAM - UINT32 :1; ///< Reserved - UINT32 PstateSpecFuseSel:8; ///< P-State Specification Fuse Select - UINT32 :5; ///< Reserved -} CLK_PWR_TIMING_CTRL_REGISTER; - - -/* Clock Power/Timing Control 1 Register D18F3xD8 */ -#define CPTC1_REG 0xD8 -#define CPTC1_PCI_ADDR (MAKE_SBDFO (0, 0, 0x18, FUNC_3, CPTC1_REG)) - -/// Clock Power Timing Control 1 PCI Register -typedef struct { - UINT32 :4; ///< Reserved - UINT32 VSRampSlamTime:3; ///< Voltage stabilization slam time - UINT32 ExtndTriDly:5; ///< Extend tri-state delay - UINT32 :20; ///< Reserved -} CLK_PWR_TIMING_CTRL1_REGISTER; - -#define CPTC1_VSRAMPSLAMTIME_START (4) -#define CPTC1_VSRAMPSLAMTIME_END (6) - - -/* Clock Power/Timing Control 2 Register D18F3xDC */ -#define CPTC2_REG 0xDC -#define CPTC2_PCI_ADDR (MAKE_SBDFO (0, 0, 0x18, FUNC_3, CPTC2_REG)) - -/// Clock Power Timing Control 2 PCI Register -typedef struct { - UINT32 :8; ///< Reserved - UINT32 PstateMaxVal:3; ///< P-state maximum value - UINT32 :1; ///< Reserved - UINT32 NbPs0Vid:7; ///< NB VID - UINT32 NclkFreqDone:1; ///< NCLK frequency change done - UINT32 NbPs0NclkDiv:7; ///< NCLK divisor - UINT32 NbClockGateHyst:3; ///< Northbridge clock gating hysteresis - UINT32 NbClockGateEn:1; ///< Northbridge clock gating enable - UINT32 CnbCifClockGateEn:1; ///< CNB CIF clock gating enable -} CLK_PWR_TIMING_CTRL2_REGISTER; - - -/* Northbridge Capabilities Register D18F3xE8 */ -#define NB_CAPS_REG 0xE8 -#define NB_CAPS_PCI_ADDR (MAKE_SBDFO (0, 0, 0x18, FUNC_3, NB_CAPS_REG)) - -/// Northbridge Capabilities PCI Register -typedef struct { - UINT32 DctDualCap:1; ///< Two-channel DRAM capable - UINT32 :4; ///< Reserved - UINT32 DdrMaxRate:3; ///< Maximum DRAM data rate - UINT32 MctCap:1; ///< Memory controller capable - UINT32 SvmCapable:1; ///< SVM capable - UINT32 HtcCapable:1; ///< HTC capable - UINT32 :1; ///< Reserved - UINT32 CmpCap:2; ///< CMP capable - UINT32 :14; ///< Reserved - UINT32 LHtcCapable:1; ///< LHTC capable - UINT32 :3; ///< Reserved -} NB_CAPS_REGISTER; - - -/* Clock Power/Timing Control 3 Register D18F3x128 */ -#define CPTC3_REG 0x128 -#define CPTC3_PCI_ADDR (MAKE_SBDFO (0, 0, 0x18, FUNC_3, CPTC3_REG)) - -/// Clock Power Timing Control 3 PCI Register -typedef struct { - UINT32 C6Vid:7; ///< C6 VID - UINT32 :1; ///< Reserved - UINT32 NbPsiVid:7; ///< NB PSI_L VID threshold - UINT32 NbPsiVidEn:1; ///< NB PSI_L enable - UINT32 :16; ///< Reserved -} CLK_PWR_TIMING_CTRL3_REGISTER; - - -/* Local hardware thermal control register D18F3x138 */ -#define LHTC_REG 0x138 -#define LHTC_PCI_ADDR (MAKE_SBDFO (0, 0, 0x18, FUNC_3, LHTC_REG)) - -/// Local Hardware Thermal Control PCI Register -typedef struct { - UINT32 LHtcEn:1; ///< Local HTC Enable - UINT32 :7; ///< Reserved - UINT32 LHtcAct:1; ///< Local HTC Active State - UINT32 :3; ///< Reserved - UINT32 LHtcActSts:1; ///< Local HTC Active Status - UINT32 :3; ///< Reserved - UINT32 LHtcTmpLmt:7; ///< Local HTC temperature limit - UINT32 LHtcSlewSel:1; ///< Local HTC slew-controlled temp select - UINT32 LHtcHystLmt:4; ///< Local HTC hysteresis - UINT32 LHtcPstateLimit:3; ///< Local HTC P-state limit select - UINT32 LHtcLock:1; ///< HTC lock -} LHTC_REGISTER; - - -/* C-state Control 1 Register D18F4x118 */ -#define CSTATE_CTRL1_REG 0x118 -#define CSTATE_CTRL1_PCI_ADDR (MAKE_SBDFO (0, 0, 0x18, FUNC_4, CSTATE_CTRL1_REG)) - -/// C-state Control 1 Register -typedef struct { - UINT32 CstAct0:3; ///< C-state action field 0 - UINT32 :5; ///< Reserved - UINT32 CstAct1:3; ///< C-state action field 1 - UINT32 :5; ///< Reserved - UINT32 CstAct2:3; ///< C-state action field 2 - UINT32 :5; ///< Reserved - UINT32 CstAct3:3; ///< C-state action field 3 - UINT32 :5; ///< Reserved -} CSTATE_CTRL1_REGISTER; - - -/* C-state Control 2 Register D18F4x11C */ -#define CSTATE_CTRL2_REG 0x11C -#define CSTATE_CTRL2_PCI_ADDR (MAKE_SBDFO (0, 0, 0x18, FUNC_4, CSTATE_CTRL2_REG)) - -/// C-state Control 2 Register -typedef struct { - UINT32 CstAct4:3; ///< C-state action field 4 - UINT32 :5; ///< Reserved - UINT32 CstAct5:3; ///< C-state action field 5 - UINT32 :5; ///< Reserved - UINT32 CstAct6:3; ///< C-state action field 6 - UINT32 :5; ///< Reserved - UINT32 CstAct7:3; ///< C-state action field 7 - UINT32 :5; ///< Reserved -} CSTATE_CTRL2_REGISTER; - - -/* Core Performance Boost Control Register D18F4x15C */ -#define CPB_CTRL_REG 0x15C -#define CPB_CTRL_PCI_ADDR (MAKE_SBDFO (0, 0, 0x18, FUNC_4, CPB_CTRL_REG)) - -/// Core Performance Boost Control Register -typedef struct { - UINT32 BoostSrc:2; ///< Boost source - UINT32 NumBoostStates:3; ///< Number of boosted states - UINT32 :23; ///< Reserved - UINT32 IgnoreBoostThresh:1; ///< Ignore boost threshold - UINT32 BoostEnAllCores:1; ///< Boost enable all cores - UINT32 :2; ///< Reserved -} CPB_CTRL_REGISTER; - - -/* CPU State Power Management Dynamic Control 0 Register D18F4x1A8 */ -#define CPU_STATE_PM_CTRL0_REG 0x1A8 -#define CPU_STATE_PM_CTRL0_PCI_ADDR (MAKE_SBDFO (0, 0, 0x18, FUNC_4, CPU_STATE_PM_CTRL0_REG)) - -/// CPU State Power Management Dynamic Control 0 Register -typedef struct { - UINT32 SingleHaltCpuDid:5; ///< Single hlt CPU DID - UINT32 AllHaltCpuDid:5; ///< All hlt CPU DID - UINT32 :5; ///< Reserved - UINT32 CpuProbEn:1; ///< CPU probe enable - UINT32 :1; ///< Reserved - UINT32 PService:3; ///< Service P-state - UINT32 PServiceTmr:3; ///< Service P-state timer - UINT32 PServiceTmrEn:1; ///< Service P-state timer enable - UINT32 DramSrEn:1; ///< DRAM self-refresh enable - UINT32 MemTriStateEn:1; ///< Memory clock tri-state enable - UINT32 DramSrHyst:3; ///< DRAM self-refresh hysteresis time - UINT32 DramSrHystEnable:1; ///< DRAM self-refresh hysteresis enable - UINT32 :2; ///< Reserved -} CPU_STATE_PM_CTRL0_REGISTER; - - -/* CPU State Power Management Dynamic Control 1 Register D18F4x1AC */ -#define CPU_STATE_PM_CTRL1_REG 0x1AC -#define CPU_STATE_PM_CTRL1_PCI_ADDR (MAKE_SBDFO (0, 0, 0x18, FUNC_4, CPU_STATE_PM_CTRL1_REG)) - -/// CPU State Power Management Dynamic Control 1 Register -typedef struct { - UINT32 :5; ///< Reserved - UINT32 C6Did:5; ///< CC6 divisor - UINT32 :6; ///< Reserved - UINT32 PstateIdCoreOffExit:3; ///< P-state ID core-off exit - UINT32 :7; ///< Reserved - UINT32 PkgC6Cap:1; ///< Package C6 capable - UINT32 CoreC6Cap:1; ///< Core C6 capable - UINT32 PkgC6Dis:1; ///< Package C6 disable - UINT32 CoreC6Dis:1; ///< Core C6 disable - UINT32 CstPminEn:1; ///< C-state Pmin enable - UINT32 :1; ///< Reserved -} CPU_STATE_PM_CTRL1_REGISTER; - - -/* C6 Base Register D18F4x1AC */ -#define C6_BASE_REG 0x12C -#define C6_BASE_PCI_ADDR (MAKE_SBDFO (0, 0, 0x18, FUNC_4, C6_BASE_REG)) - -/// C6 Base Register -typedef struct { - UINT32 C6Base:16; ///< C6 base[39:24] - UINT32 :16; ///< Reserved -} C6_BASE_REGISTER; - - -/* NB P-state Config Low Register D18F6x90 */ -#define NB_PSTATE_CFG_LOW_REG 0x90 -#define NB_PSTATE_CFG_LOW_PCI_ADDR (MAKE_SBDFO (0, 0, 0x18, FUNC_6, NB_PSTATE_CFG_LOW_REG)) - -/// NB P-state Config Low Register -typedef struct { - UINT32 NbPs1NclkDiv:7; ///< NBP1 NCLK divisor - UINT32 :1; ///< Reserved - UINT32 NbPs1Vid:7; ///< NBP1 NCLK VID - UINT32 :1; ///< Reserved - UINT32 NbPs1GnbSlowIgn:1; ///< NB P-state ignore GNB slow signal - UINT32 :3; ///< Reserved - UINT32 NbPsLock:1; ///< NB P-state lock - UINT32 :7; ///< Reserved - UINT32 NbPsForceReq:1; ///< NB P-state force request - UINT32 NbPsForceSel:1; ///< NB P-state force selection - UINT32 NbPsCtrlDis:1; ///< NB P-state control disable - UINT32 NbPsCap:1; ///< NB P-state capable -} NB_PSTATE_CFG_LOW_REGISTER; - - -/* NB P-state Config High Register D18F6x94 */ -#define NB_PSTATE_CFG_HIGH_REG 0x94 -#define NB_PSTATE_CFG_HIGH_PCI_ADDR (MAKE_SBDFO (0, 0, 0x18, FUNC_6, NB_PSTATE_CFG_HIGH_REG)) - -/// NB P-state Config High Register -typedef struct { - UINT32 CpuPstateThr:3; ///< CPU P-state threshold - UINT32 CpuPstateThrEn:1; ///< CPU P-state threshold enable - UINT32 NbPs1NoTransOnDma:1; ///< NB P-state no transitions on DMA - UINT32 :15; ///< Reserved - UINT32 NbPsNonC0Timer:3; ///< NB P-state non-C0 timer - UINT32 NbPsC0Timer:3; ///< NB P-state C0 timer - UINT32 NbPs1ResTmrMin:3; ///< NBP1 minimum residency timer - UINT32 NbPs0ResTmrMin:3; ///< NBP0 minimum residency timer -} NB_PSTATE_CFG_HIGH_REGISTER; - - -/* NB P-state Control and Status Register D18F6x98 */ -#define NB_PSTATE_CTRL_STS_REG 0x98 -#define NB_PSTATE_CTRL_STS_PCI_ADDR (MAKE_SBDFO (0, 0, 0x18, FUNC_6, NB_PSTATE_CTRL_STS_REG)) - -/// NB P-state Control and Status Register -typedef struct { - UINT32 NbPsTransInFlight:1; ///< NB P-state transition in flight - UINT32 NbPs1ActSts:1; ///< NB P-state 1 active status - UINT32 NbPs1Act:1; ///< NB P-state 1 active - UINT32 :27; ///< Reserved - UINT32 NbPsCsrAccSel:1; ///< NB P-state register accessibility select - UINT32 NbPsDbgEn:1; ///< NB P-state debug enable -} NB_PSTATE_CTRL_STS_REGISTER; - -/* NCLK Reduction Control D18F6x9C */ -#define NCLK_REDUCTION_CTRL_REG 0x9C -#define NCLK_REDUCTION_CTRL_PCI_ADDR (MAKE_SBDFO (0, 0, 0x18, FUNC_6, NCLK_REDUCTION_CTRL_REG)) - -/// NCLK Reduction Control -typedef struct { - UINT32 NclkRedDiv:7; ///< NCLK reduction divisor - UINT32 NclkRedSelfRefrAlways:1; ///< NCLK reduction always self refresh - UINT32 NclkRampWithDllRelock:1; ///< NCLK ramp mode - UINT32 :23; ///< Reserved -} NCLK_REDUCTION_CTRL_REGISTER; - -/// enum for DSM workaround control -typedef enum { - CC6_DSM_WORK_AROUND_DISABLE = 0, ///< work around disable - CC6_DSM_WORK_AROUND_NORMAL_TRAFFIC, ///< work around With Normal Traffic - CC6_DSM_WORK_AROUND_HIGH_PRIORITY_CHANNEL, ///< work around With High Priority Channel -} CC6_DSM_WORK_AROUND; - -#endif /* _CPUF12POWERMGMT_H */ diff --git a/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x12/cpuF12PowerMgmtSystemTables.c b/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x12/cpuF12PowerMgmtSystemTables.c deleted file mode 100644 index 3ca62c2d62..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x12/cpuF12PowerMgmtSystemTables.c +++ /dev/null @@ -1,150 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * AMD Family_12 Power Management Initialization Steps - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: CPU/F12 - * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $ - * - */ -/* - ****************************************************************************** - * - * Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - ****************************************************************************** - */ - -/*---------------------------------------------------------------------------------------- - * M O D U L E S U S E D - *---------------------------------------------------------------------------------------- - */ -#include "AGESA.h" -#include "Ids.h" -#include "cpuRegisters.h" -#include "cpuApicUtilities.h" -#include "cpuFamilyTranslation.h" -//#include "IdsF12AllService.h" -#include "cpuPowerMgmtSystemTables.h" -#include "cpuF12SoftwareThermal.h" -#include "cpuF12PowerPlane.h" -#include "cpuF12PowerCheck.h" -#include "cpuF12EarlyNbPstateInit.h" -#include "Filecode.h" -CODE_GROUP (G1_PEICC) -RDATA_GROUP (G1_PEICC) - -#define FILECODE PROC_CPU_FAMILY_0X12_CPUF12POWERMGMTSYSTEMTABLES_FILECODE - -/*---------------------------------------------------------------------------------------- - * D E F I N I T I O N S A N D M A C R O S - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------- - * T Y P E D E F S A N D S T R U C T U R E S - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------- - * P R O T O T Y P E S O F L O C A L F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ -VOID -GetF12SysPmTable ( - IN CPU_SPECIFIC_SERVICES *FamilySpecificServices, - OUT CONST VOID **SysPmTblPtr, - OUT UINT8 *NumberOfElements, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -/*---------------------------------------------------------------------------------------- - * E X P O R T E D F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ - -/* Family 12h Table */ -/* ---------------------- */ -CONST SYS_PM_TBL_STEP ROMDATA CpuF12SysPmTableArray[] = -{ - IDS_INITIAL_F12_PM_STEP - - // Step 1 - Power Plane Initialization - // Execute both cold & warm - { - 0, // ExeFlags - F12PmPwrPlaneInit // Function Pointer - }, - - // Step 2 - Current Delivery Check - // Execute both cold & warm - { - 0, // ExeFlags - F12PmPwrCheck // Function Pointer - }, - - // Step x - Nb P-state init - // Execute both cold & warm - { - 0, // ExeFlags - F12NbPstateEarlyInit // Function Pointer - }, - - // Step x - Software Thermal Control Init - // Execute both cold & warm - { - 0, // ExeFlags - F12PmThermalInit // Function Pointer - }, -}; - - -/*---------------------------------------------------------------------------------------*/ -/** - * Returns the appropriate table of steps to perform to initialize the power management - * subsystem. - * - * @CpuServiceMethod{::F_CPU_GET_FAMILY_SPECIFIC_ARRAY}. - * - * @param[in] FamilySpecificServices The current Family Specific Services. - * @param[out] SysPmTblPtr Points to the first entry in the table. - * @param[out] NumberOfElements Number of valid entries in the table. - * @param[in] StdHeader Header for library and services. - * - */ -VOID -GetF12SysPmTable ( - IN CPU_SPECIFIC_SERVICES *FamilySpecificServices, - OUT CONST VOID **SysPmTblPtr, - OUT UINT8 *NumberOfElements, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - *NumberOfElements = (sizeof (CpuF12SysPmTableArray) / sizeof (SYS_PM_TBL_STEP)); - *SysPmTblPtr = CpuF12SysPmTableArray; -} diff --git a/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x12/cpuF12PowerPlane.c b/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x12/cpuF12PowerPlane.c deleted file mode 100644 index a14cb1b61a..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x12/cpuF12PowerPlane.c +++ /dev/null @@ -1,312 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * AMD Family_12 Power Plane Initialization - * - * Performs the "BIOS Requirements for Power Plane Initialization" as described - * in the BKDG. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: CPU/F12 - * @e \$Revision: 47330 $ @e \$Date: 2011-02-18 10:39:06 +0800 (Fri, 18 Feb 2011) $ - * - */ -/* - ****************************************************************************** - * - * Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - ****************************************************************************** - */ - -/*---------------------------------------------------------------------------------------- - * M O D U L E S U S E D - *---------------------------------------------------------------------------------------- - */ -#include "AGESA.h" -#include "amdlib.h" -#include "Ids.h" -#include "cpuRegisters.h" -#include "cpuFamilyTranslation.h" -#include "cpuServices.h" -#include "cpuF12PowerMgmt.h" -#include "cpuF12PowerPlane.h" -#include "OptionFamily12hEarlySample.h" -#include "GnbRegistersLN.h" -#include "NbSmuLib.h" -#include "Filecode.h" -CODE_GROUP (G1_PEICC) -RDATA_GROUP (G1_PEICC) - -#define FILECODE PROC_CPU_FAMILY_0X12_CPUF12POWERPLANE_FILECODE - -/*---------------------------------------------------------------------------------------- - * D E F I N I T I O N S A N D M A C R O S - *---------------------------------------------------------------------------------------- - */ -extern F12_ES_CORE_SUPPORT F12EarlySampleCoreSupport; - -// Register encodings for D18F3xD8[VSRampSlamTime] -STATIC CONST UINT32 ROMDATA F12VSRampSlamWaitTimes[8] = -{ - 625, // 000b: 6.25us - 500, // 001b: 5.00us - 417, // 010b: 4.17us - 313, // 011b: 3.13us - 250, // 100b: 2.50us - 167, // 101b: 1.67us - 125, // 110b: 1.25us - 100 // 111b: 1.00us -}; - -/*---------------------------------------------------------------------------------------- - * T Y P E D E F S A N D S T R U C T U R E S - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------- - * P R O T O T Y P E S O F L O C A L F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ -VOID -STATIC -F12PmVrmLowPowerModeEnable ( - IN CPU_SPECIFIC_SERVICES *FamilySpecificServices, - IN AMD_CPU_EARLY_PARAMS *CpuEarlyParams, - IN PCI_ADDR PciAddress, - IN AMD_CONFIG_PARAMS *StdHeader - ); - - -/*---------------------------------------------------------------------------------------- - * E X P O R T E D F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------*/ -/** - * Family 12h core 0 entry point for performing power plane initialization. - * - * The steps are as follows: - * 1. BIOS must initialize D18F3xD8[VSRampSlamTime]. - * 2. BIOS must configure D18F3xA0[PsiVidEn & PsiVid] and - * D18F3x128[NbPsiVidEn & NbPsiVid]. - * 3. BIOS must program D18F3xDC[NbPs0Vid] = FCRxFE00_6000[NbPs0Vid] - 1. - * BIOS must program D18F3xDC[NbPs0Vid] = FCRxFE00_6000[NbPs0Vid]. - * - * @param[in] FamilySpecificServices The current Family Specific Services. - * @param[in] CpuEarlyParams Service parameters - * @param[in] StdHeader Config handle for library and services. - * - */ -VOID -F12PmPwrPlaneInit ( - IN CPU_SPECIFIC_SERVICES *FamilySpecificServices, - IN AMD_CPU_EARLY_PARAMS *CpuEarlyParams, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - UINT32 SystemSlewRate; - UINT32 WaitTime; - UINT32 VSRampSlamTime; - UINT32 LocalPciRegister; - UINT32 VoltageDifference; - UINT32 SingleVidStepTransitionTime; - UINT32 TransitionTime; - PCI_ADDR PciAddress; - FCRxFE00_6000_STRUCT FCRxFE00_6000; - - // Step 1 - Configure D18F3xD8[VSRampSlamTime] based on platform requirements. - // Voltage Ramp Time = maximum time to change voltage by 12.5mV rounded to the next higher encoding. - SystemSlewRate = (CpuEarlyParams->PlatformConfig.VrmProperties[CoreVrm].SlewRate <= - CpuEarlyParams->PlatformConfig.VrmProperties[NbVrm].SlewRate) ? - CpuEarlyParams->PlatformConfig.VrmProperties[CoreVrm].SlewRate : - CpuEarlyParams->PlatformConfig.VrmProperties[NbVrm].SlewRate; - - ASSERT (SystemSlewRate != 0); - - // First, calculate the time it takes to change 12.5mV using the VRM slew rate. - WaitTime = (12500 * 100) / SystemSlewRate; - if (((12500 * 100) % SystemSlewRate) != 0) { - WaitTime++; - } - - // Next, round it to the appropriate encoded value. We will start from encoding 111b which corresponds - // to the fastest slew rate, and work our way down to 000b, which represents the slowest an acceptable - // VRM can be. - for (VSRampSlamTime = ((sizeof (F12VSRampSlamWaitTimes) / sizeof (F12VSRampSlamWaitTimes[0])) - 1); VSRampSlamTime > 0; VSRampSlamTime--) { - if (WaitTime <= F12VSRampSlamWaitTimes[VSRampSlamTime]) { - break; - } - } - - if (WaitTime > F12VSRampSlamWaitTimes[0]) { - // The VRMs on this motherboard are too slow for this CPU. - IDS_ERROR_TRAP; - } - - // Lastly, program D18F3xD8[VSRampSlamTime] with the appropriate encoded value. - PciAddress.AddressValue = CPTC1_PCI_ADDR; - LibAmdPciWriteBits (PciAddress, CPTC1_VSRAMPSLAMTIME_END, CPTC1_VSRAMPSLAMTIME_START, &VSRampSlamTime, StdHeader); - - // Step 2 - Configure D18F3xA0[PsiVidEn & PsiVid] and D18F3x128[NbPsiVidEn & NbPsiVid]. - F12PmVrmLowPowerModeEnable (FamilySpecificServices, CpuEarlyParams, PciAddress, StdHeader); - - // Step 3 - Program D18F3xDC[NbPs0Vid] = FCRxFE00_6000[NbPs0Vid] - 1. - // Wait out the appropriate voltage stabilization time. - // Program D18F3xDC[NbPs0Vid] = FCRxFE00_6000[NbPs0Vid]. - // Wait out the appropriate voltage stabilization time. - FCRxFE00_6000.Value = NbSmuReadEfuse (FCRxFE00_6000_ADDRESS, StdHeader); - - F12EarlySampleCoreSupport.F12PowerPlaneInitHook (&FCRxFE00_6000, StdHeader); - - PciAddress.AddressValue = CPTC2_PCI_ADDR; - LibAmdPciRead (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader); - if (((CLK_PWR_TIMING_CTRL2_REGISTER *) &LocalPciRegister)->NbPs0Vid >= FCRxFE00_6000.Field.NbPs0Vid) { - VoltageDifference = ((((CLK_PWR_TIMING_CTRL2_REGISTER *) &LocalPciRegister)->NbPs0Vid - FCRxFE00_6000.Field.NbPs0Vid) + 1); - } else { - VoltageDifference = ((FCRxFE00_6000.Field.NbPs0Vid - ((CLK_PWR_TIMING_CTRL2_REGISTER *) &LocalPciRegister)->NbPs0Vid) - 1); - } - SingleVidStepTransitionTime = WaitTime / 100; - if ((WaitTime % 100) != 0) { - SingleVidStepTransitionTime++; - } - TransitionTime = SingleVidStepTransitionTime * VoltageDifference; - - ((CLK_PWR_TIMING_CTRL2_REGISTER *) &LocalPciRegister)->NbPs0Vid = FCRxFE00_6000.Field.NbPs0Vid - 1; - LibAmdPciWrite (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader); - - WaitMicroseconds (TransitionTime, StdHeader); - - ((CLK_PWR_TIMING_CTRL2_REGISTER *) &LocalPciRegister)->NbPs0Vid = FCRxFE00_6000.Field.NbPs0Vid; - LibAmdPciWrite (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader); - - WaitMicroseconds (SingleVidStepTransitionTime, StdHeader); -} - -/*---------------------------------------------------------------------------------------*/ -/** - * Sets up PSI_L operation. - * - * This function implements the AMD_CPU_EARLY_PARAMS.VrmLowPowerThreshold parameter. - * - * @param[in] FamilySpecificServices The current Family Specific Services. - * @param[in] CpuEarlyParams Contains VrmLowPowerThreshold parameter. - * @param[in] PciAddress PCI address of the executing core's config space. - * @param[in] StdHeader Config handle for library and services. - * - */ -VOID -STATIC -F12PmVrmLowPowerModeEnable ( - IN CPU_SPECIFIC_SERVICES *FamilySpecificServices, - IN AMD_CPU_EARLY_PARAMS *CpuEarlyParams, - IN PCI_ADDR PciAddress, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - UINT32 Pstate; - UINT32 PstateMaxVal; - UINT32 PstateCurrent; - UINT32 NextPstateCurrent; - UINT32 NextPstateCurrentRaw; - UINT32 LocalPciRegister; - UINT32 PreviousVid; - UINT32 CurrentVid; - UINT32 C6Vid; - UINT32 HwPsMaxVal; - UINT64 PstateMsr; - BOOLEAN IsPsiEnabled; - - // Set up PSI_L for VDD - IsPsiEnabled = FALSE; - PreviousVid = 0x7F; - CurrentVid = 0x7F; - PciAddress.Address.Function = FUNC_3; - PciAddress.Address.Register = CPTC2_REG; - LibAmdPciRead (AccessWidth32, PciAddress, &HwPsMaxVal, StdHeader); - - if (CpuEarlyParams->PlatformConfig.VrmProperties[CoreVrm].LowPowerThreshold != 0) { - PstateMaxVal = (UINT32) ((CLK_PWR_TIMING_CTRL2_REGISTER *) &HwPsMaxVal)->PstateMaxVal; - FamilySpecificServices->GetProcIddMax (FamilySpecificServices, (UINT8) 0, &PstateCurrent, StdHeader); - for (Pstate = 0; Pstate <= PstateMaxVal; Pstate++) { - LibAmdMsrRead ((UINT32) (Pstate + PS_REG_BASE), &PstateMsr, StdHeader); - CurrentVid = (UINT32) ((PSTATE_MSR *) &PstateMsr)->CpuVid; - if (Pstate == PstateMaxVal) { - NextPstateCurrentRaw = 0; - NextPstateCurrent = 0; - } else { - FamilySpecificServices->GetProcIddMax (FamilySpecificServices, (UINT8) (Pstate + 1), &NextPstateCurrentRaw, StdHeader); - NextPstateCurrent = NextPstateCurrentRaw + CpuEarlyParams->PlatformConfig.VrmProperties[CoreVrm].InrushCurrentLimit; - } - if ((PstateCurrent <= CpuEarlyParams->PlatformConfig.VrmProperties[CoreVrm].LowPowerThreshold) && - (NextPstateCurrent <= CpuEarlyParams->PlatformConfig.VrmProperties[CoreVrm].LowPowerThreshold) && - (CurrentVid != PreviousVid)) { - IsPsiEnabled = TRUE; - break; - } else { - PstateCurrent = NextPstateCurrentRaw; - PreviousVid = CurrentVid; - } - } - - // At this point, if IsPsiEnabled is still FALSE, then a suitable threshold - // is not found. - if (!IsPsiEnabled) { - PciAddress.AddressValue = CPTC3_PCI_ADDR; - LibAmdPciRead (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader); - C6Vid = ((CLK_PWR_TIMING_CTRL3_REGISTER *) &LocalPciRegister)->C6Vid; - // Set threshold to C6Vid and set IsPsiEnabled to TRUE only if C6Vid value - // is larger than the last seen VID code. - if (C6Vid > PreviousVid) { - CurrentVid = C6Vid; - IsPsiEnabled = TRUE; - } - } - } - PciAddress.AddressValue = PW_CTL_MISC_PCI_ADDR; - LibAmdPciRead (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader); - if (IsPsiEnabled) { - ((POWER_CTRL_MISC_REGISTER *) &LocalPciRegister)->PsiVid = CurrentVid; - ((POWER_CTRL_MISC_REGISTER *) &LocalPciRegister)->PsiVidEn = 1; - } else { - ((POWER_CTRL_MISC_REGISTER *) &LocalPciRegister)->PsiVidEn = 0; - } - LibAmdPciWrite (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader); - - - // Set up NBPSI_L for VDDNB - PciAddress.AddressValue = CPTC3_PCI_ADDR; - LibAmdPciRead (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader); - if (CpuEarlyParams->PlatformConfig.VrmProperties[NbVrm].LowPowerThreshold != 0) { - ((CLK_PWR_TIMING_CTRL3_REGISTER *) &LocalPciRegister)->NbPsiVid = 0; - ((CLK_PWR_TIMING_CTRL3_REGISTER *) &LocalPciRegister)->NbPsiVidEn = 1; - } else { - ((CLK_PWR_TIMING_CTRL3_REGISTER *) &LocalPciRegister)->NbPsiVidEn = 0; - } - LibAmdPciWrite (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader); -} diff --git a/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x12/cpuF12PowerPlane.h b/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x12/cpuF12PowerPlane.h deleted file mode 100644 index d071c73999..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x12/cpuF12PowerPlane.h +++ /dev/null @@ -1,76 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * AMD Family_12 Power Plane related functions and structures - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: CPU/F12 - * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $ - * - */ -/* - ****************************************************************************** - * - * Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - ****************************************************************************** - */ - -#ifndef _CPU_F12_POWER_PLANE_H_ -#define _CPU_F12_POWER_PLANE_H_ - - -/*--------------------------------------------------------------------------------------- - * M I X E D (Definitions And Macros / Typedefs, Structures, Enums) - *--------------------------------------------------------------------------------------- - */ - - -/*--------------------------------------------------------------------------------------- - * D E F I N I T I O N S A N D M A C R O S - *--------------------------------------------------------------------------------------- - */ - - -/*--------------------------------------------------------------------------------------- - * T Y P E D E F S, S T R U C T U R E S, E N U M S - *--------------------------------------------------------------------------------------- - */ - - -/*--------------------------------------------------------------------------------------- - * F U N C T I O N P R O T O T Y P E - *--------------------------------------------------------------------------------------- - */ -VOID -F12PmPwrPlaneInit ( - IN CPU_SPECIFIC_SERVICES *FamilySpecificServices, - IN AMD_CPU_EARLY_PARAMS *CpuEarlyParams, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -#endif // _CPU_F12_POWER_PLANE_H_ diff --git a/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x12/cpuF12Pstate.c b/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x12/cpuF12Pstate.c deleted file mode 100644 index 8b4fbd5350..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x12/cpuF12Pstate.c +++ /dev/null @@ -1,481 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * AMD Family_12 Pstate feature support functions. - * - * Provides the functions necessary to initialize the Pstate feature. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: CPU/F12 - * @e \$Revision: 44702 $ @e \$Date: 2011-01-05 06:54:00 +0800 (Wed, 05 Jan 2011) $ - * - */ -/* - ****************************************************************************** - * - * Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - ****************************************************************************** - */ - -/*---------------------------------------------------------------------------------------- - * M O D U L E S U S E D - *---------------------------------------------------------------------------------------- - */ -#include "AGESA.h" -#include "amdlib.h" -#include "Ids.h" -#include "cpuPstateTables.h" -#include "cpuFamilyTranslation.h" -#include "cpuRegisters.h" -#include "cpuF12Utilities.h" -#include "cpuF12PowerMgmt.h" -#include "CommonReturns.h" -#include "Filecode.h" -CODE_GROUP (G1_PEICC) -RDATA_GROUP (G1_PEICC) - -#define FILECODE PROC_CPU_FAMILY_0X12_CPUF12PSTATE_FILECODE - -/*---------------------------------------------------------------------------------------- - * D E F I N I T I O N S A N D M A C R O S - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------- - * T Y P E D E F S A N D S T R U C T U R E S - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------- - * P R O T O T Y P E S O F L O C A L F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ -AGESA_STATUS -F12GetPstateTransLatency ( - IN PSTATE_CPU_FAMILY_SERVICES *PstateCpuServices, - IN PSTATE_LEVELING *PStateLevelingBufferStructPtr, - IN PCI_ADDR *PciAddress, - OUT UINT32 *TransitionLatency, - IN AMD_CONFIG_PARAMS *StdHeader - ); - - AGESA_STATUS -F12GetPstateFrequency ( - IN PSTATE_CPU_FAMILY_SERVICES *PstateCpuServices, - IN UINT8 StateNumber, - OUT UINT32 *FrequencyInMHz, - IN AMD_CONFIG_PARAMS *StdHeader - ); - - AGESA_STATUS -F12GetPstatePower ( - IN PSTATE_CPU_FAMILY_SERVICES *PstateCpuServices, - IN UINT8 StateNumber, - OUT UINT32 *PowerInMw, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -AGESA_STATUS -F12GetPstateMaxState ( - IN PSTATE_CPU_FAMILY_SERVICES *PstateCpuServices, - OUT UINT32 *MaxPStateNumber, - OUT UINT8 *NumberOfBoostStates, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -AGESA_STATUS -F12GetPstateRegisterInfo ( - IN PSTATE_CPU_FAMILY_SERVICES *PstateCpuServices, - IN UINT32 PState, - OUT BOOLEAN *PStateEnabled, - IN OUT UINT32 *IddVal, - IN OUT UINT32 *IddDiv, - OUT UINT32 *SwPstateNumber, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -/*---------------------------------------------------------------------------------------- - * E X P O R T E D F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------*/ -/** - * Family specific call to check if Pstate PSD is dependent. - * - * @param[in] PstateCpuServices Pstate CPU services. - * @param[in,out] PlatformConfig Contains the runtime modifiable feature input data. - * @param[in] StdHeader Config Handle for library, services. - * - * @retval TRUE PSD is dependent. - * @retval FALSE PSD is independent. - * - */ -BOOLEAN -STATIC -F12IsPstatePsdDependent ( - IN PSTATE_CPU_FAMILY_SERVICES *PstateCpuServices, - IN OUT PLATFORM_CONFIGURATION *PlatformConfig, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - // F12h defaults to dependent PSD; allow Platform Configuration to - // overwrite the default setting. - if (PlatformConfig->ForcePstateIndependent) { - return FALSE; - } - return TRUE; -} - -/** - * Family specific call to set core TscFreqSel. - * - * @param[in] PstateCpuServices Pstate CPU services. - * @param[in] StdHeader Config Handle for library, services. - * - */ -VOID -STATIC -F12SetTscFreqSel ( - IN PSTATE_CPU_FAMILY_SERVICES *PstateCpuServices, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - UINT64 MsrValue; - - LibAmdMsrRead (MSR_HWCR, &MsrValue, StdHeader); - MsrValue = MsrValue | BIT24; - LibAmdMsrWrite (MSR_HWCR, &MsrValue, StdHeader); -} - -/*---------------------------------------------------------------------------------------*/ -/** - * Family specific call to get Pstate Transition Latency. - * - * Follow BKDG, return zero currently. - * - * @param[in] PstateCpuServices Pstate CPU services. - * @param[in] PStateLevelingBufferStructPtr Pstate row data buffer pointer - * @param[in] PciAddress Pci address - * @param[out] TransitionLatency The transition latency. - * @param[in] StdHeader Header for library and services - * - * @retval AGESA_SUCCESS Always succeeds. - */ -AGESA_STATUS -F12GetPstateTransLatency ( - IN PSTATE_CPU_FAMILY_SERVICES *PstateCpuServices, - IN PSTATE_LEVELING *PStateLevelingBufferStructPtr, - IN PCI_ADDR *PciAddress, - OUT UINT32 *TransitionLatency, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - // - // TransitionLatency (us) = BusMasterLatency (us) = 0 us, calculation may - // change due to a potential new encoding. - // - *TransitionLatency = 0; - return (AGESA_SUCCESS); -} - -/*---------------------------------------------------------------------------------------*/ -/** - * Family specific call to calculates the frequency in megahertz of the desired P-state. - * - * @param[in] PstateCpuServices Pstate CPU services. - * @param[in] StateNumber The P-State to analyze. - * @param[out] FrequencyInMHz The P-State's frequency in MegaHertz - * @param[in] StdHeader Header for library and services - * - * @retval AGESA_SUCCESS Always Succeeds. - */ -AGESA_STATUS -F12GetPstateFrequency ( - IN PSTATE_CPU_FAMILY_SERVICES *PstateCpuServices, - IN UINT8 StateNumber, - OUT UINT32 *FrequencyInMHz, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - UINT32 CpuDid; - UINT32 CpuFid; - UINT32 LocalPciRegister; - UINT64 LocalMsrRegister; - BOOLEAN FrequencyCalculated; - PCI_ADDR PciAddress; - - ASSERT (StateNumber < NM_PS_REG); - - LibAmdMsrRead (PS_REG_BASE + (UINT32) StateNumber, &LocalMsrRegister, StdHeader); - ASSERT (((PSTATE_MSR *) &LocalMsrRegister)->PsEnable == 1); - - CpuDid = (UINT32) (((PSTATE_MSR *) &LocalMsrRegister)->CpuDid); - CpuFid = (UINT32) (((PSTATE_MSR *) &LocalMsrRegister)->CpuFid); - - FrequencyCalculated = FALSE; - - switch (CpuDid) { - case 0: - CpuDid = 10; - break; - case 1: - CpuDid = 15; - break; - case 2: - CpuDid = 20; - break; - case 3: - CpuDid = 30; - break; - case 4: - CpuDid = 40; - break; - case 5: - CpuDid = 60; - break; - case 6: - CpuDid = 80; - break; - case 7: - CpuDid = 120; - break; - case 8: - CpuDid = 160; - break; - case 14: - if (CpuFid != 0) { - CpuDid = 160; - } else { - FrequencyCalculated = TRUE; - *FrequencyInMHz = 100; - } - break; - default: - // CpuDid is set to an undefined value. This is due to either a misfused CPU, or - // an invalid P-state MSR write. - ASSERT (FALSE); - CpuDid = 1; - break; - } - - if (!FrequencyCalculated) { - PciAddress.AddressValue = MAKE_SBDFO (0, 0, PCI_DEV_BASE, 4, 0x15C); - LibAmdPciRead (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader); - - if ((LocalPciRegister & BIT30) != 0) { - CpuFid += 0x20; - } else { - CpuFid += 0x10; - } - *FrequencyInMHz = (((100 * 10) * CpuFid) / CpuDid); - } - - return (AGESA_SUCCESS); -} - -/*--------------------------------------------------------------------------------------*/ -/** - * - * Family specific call to calculates the power in milliWatts of the desired P-state. - * - * @param[in] PstateCpuServices Pstate CPU services. - * @param[in] StateNumber Which P-state to analyze - * @param[out] PowerInMw The Power in milliWatts of that P-State - * @param[in] StdHeader Header for library and services - * - * @retval AGESA_SUCCESS Always succeeds. - */ -AGESA_STATUS -F12GetPstatePower ( - IN PSTATE_CPU_FAMILY_SERVICES *PstateCpuServices, - IN UINT8 StateNumber, - OUT UINT32 *PowerInMw, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - UINT32 CpuVid; - UINT32 IddValue; - UINT32 IddDiv; - UINT32 V_x10000; - UINT32 Power; - UINT64 LocalMsrRegister; - - ASSERT (StateNumber < NM_PS_REG); - LibAmdMsrRead (PS_REG_BASE + (UINT32) StateNumber, &LocalMsrRegister, StdHeader); - ASSERT (((PSTATE_MSR *) &LocalMsrRegister)->PsEnable == 1); - CpuVid = (UINT32) (((PSTATE_MSR *) &LocalMsrRegister)->CpuVid); - IddValue = (UINT32) (((PSTATE_MSR *) &LocalMsrRegister)->IddValue); - IddDiv = (UINT32) (((PSTATE_MSR *) &LocalMsrRegister)->IddDiv); - - if (CpuVid >= 0x7C) { - V_x10000 = 0; - } else { - V_x10000 = 15500L - (125L * CpuVid); - } - - Power = V_x10000 * IddValue; - - switch (IddDiv) { - case 0: - *PowerInMw = Power / 10L; - break; - case 1: - *PowerInMw = Power / 100L; - break; - case 2: - *PowerInMw = Power / 1000L; - break; - default: - // IddDiv is set to an undefined value. This is due to either a misfused CPU, or - // an invalid P-state MSR write. - ASSERT (FALSE); - *PowerInMw = 0; - break; - } - return (AGESA_SUCCESS); -} - -/*---------------------------------------------------------------------------------------*/ -/** - * Family specific call to get CPU pstate max state. - * - * @param[in] PstateCpuServices Pstate CPU services. - * @param[out] MaxPStateNumber The max hw pstate value on the current socket. - * @param[out] NumberOfBoostStates The number of boosted P-states on the current socket. - * @param[in] StdHeader Handle of Header for calling lib functions and services. - * - * @retval AGESA_SUCCESS Always succeeds. - */ -AGESA_STATUS -F12GetPstateMaxState ( - IN PSTATE_CPU_FAMILY_SERVICES *PstateCpuServices, - OUT UINT32 *MaxPStateNumber, - OUT UINT8 *NumberOfBoostStates, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - UINT32 NumBoostStates; - UINT64 MsrValue; - UINT32 LocalPciRegister; - PCI_ADDR PciAddress; - - // For F12 CPU, skip boosted p-state. The boosted p-state number = D18F4x15C[NumBoostStates]. - PciAddress.AddressValue = CPB_CTRL_PCI_ADDR; - LibAmdPciRead (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader); // D18F4x15C - - NumBoostStates = ((CPB_CTRL_REGISTER *) &LocalPciRegister)->NumBoostStates; - *NumberOfBoostStates = (UINT8) NumBoostStates; - // - // Read PstateMaxVal [6:4] from MSR C001_0061 - // So, we will know the max pstate state in this socket. - // - LibAmdMsrRead (MSR_PSTATE_CURRENT_LIMIT, &MsrValue, StdHeader); - *MaxPStateNumber = (UINT32) (((PSTATE_CURLIM_MSR *) &MsrValue)->PstateMaxVal) + NumBoostStates; - - return (AGESA_SUCCESS); -} - -/*---------------------------------------------------------------------------------------*/ -/** - * Family specific call to get CPU pstate register information. - * - * @param[in] PstateCpuServices Pstate CPU services. - * @param[in] PState Input Pstate number for query. - * @param[out] PStateEnabled Boolean flag return pstate enable. - * @param[in,out] IddVal Pstate current value. - * @param[in,out] IddDiv Pstate current divisor. - * @param[out] SwPstateNumber Software P-state number. - * @param[in] StdHeader Handle of Header for calling lib functions and services. - * - * @retval AGESA_SUCCESS Always succeeds. - */ -AGESA_STATUS -F12GetPstateRegisterInfo ( - IN PSTATE_CPU_FAMILY_SERVICES *PstateCpuServices, - IN UINT32 PState, - OUT BOOLEAN *PStateEnabled, - IN OUT UINT32 *IddVal, - IN OUT UINT32 *IddDiv, - OUT UINT32 *SwPstateNumber, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - UINT64 LocalMsrRegister; - UINT32 LocalPciRegister; - PCI_ADDR PciAddress; - - ASSERT (PState < NM_PS_REG); - - // For F12 CPU, skip boosted p-state. The boosted p-state number = D18F4x15C[NumBoostStates]. - PciAddress.AddressValue = CPB_CTRL_PCI_ADDR; - LibAmdPciRead (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader); // D18F4x15C - - // Read PSTATE MSRs - LibAmdMsrRead (PS_REG_BASE + (UINT32) PState, &LocalMsrRegister, StdHeader); - - *SwPstateNumber = PState; - - if (((PSTATE_MSR *) &LocalMsrRegister)->PsEnable == 1) { - // PState enable = bit 63 - *PStateEnabled = TRUE; - // - // Check input pstate belongs to Boosted-Pstate, if yes, return *PStateEnabled = FALSE. - // - if (PState < ((CPB_CTRL_REGISTER *) &LocalPciRegister)->NumBoostStates) { - *PStateEnabled = FALSE; - } else { - *SwPstateNumber = PState - ((CPB_CTRL_REGISTER *) &LocalPciRegister)->NumBoostStates; - } - } else { - *PStateEnabled = FALSE; - } - - // Bits 39:32 (high 32 bits [7:0]) - *IddVal = (UINT32) ((PSTATE_MSR *) &LocalMsrRegister)->IddValue; - // Bits 41:40 (high 32 bits [9:8]) - *IddDiv = (UINT32) ((PSTATE_MSR *) &LocalMsrRegister)->IddDiv; - - return (AGESA_SUCCESS); -} - - -CONST PSTATE_CPU_FAMILY_SERVICES ROMDATA F12PstateServices = -{ - 0, - (PF_PSTATE_PSD_IS_NEEDED) CommonReturnTrue, - F12IsPstatePsdDependent, - F12SetTscFreqSel, - F12GetPstateTransLatency, - F12GetPstateFrequency, - (PF_CPU_SET_PSTATE_LEVELING_REG) CommonReturnAgesaSuccess, - F12GetPstatePower, - F12GetPstateMaxState, - F12GetPstateRegisterInfo -}; - diff --git a/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x12/cpuF12SoftwareThermal.c b/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x12/cpuF12SoftwareThermal.c deleted file mode 100644 index 08be5d157b..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x12/cpuF12SoftwareThermal.c +++ /dev/null @@ -1,128 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * AMD Family_12 thermal initialization - * - * Performs processor thermal initialization. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: CPU/F12 - * @e \$Revision: 48183 $ @e \$Date: 2011-03-04 15:53:58 +0800 (Fri, 04 Mar 2011) $ - * - */ -/* - ****************************************************************************** - * - * Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - ****************************************************************************** - */ - -/*---------------------------------------------------------------------------------------- - * M O D U L E S U S E D - *---------------------------------------------------------------------------------------- - */ -#include "AGESA.h" -#include "amdlib.h" -#include "cpuRegisters.h" -#include "cpuFamilyTranslation.h" -#include "cpuF12PowerMgmt.h" -#include "Filecode.h" -CODE_GROUP (G1_PEICC) -RDATA_GROUP (G1_PEICC) - -#define FILECODE PROC_CPU_FAMILY_0X12_CPUF12SOFTWARETHERMAL_FILECODE - -/*---------------------------------------------------------------------------------------- - * D E F I N I T I O N S A N D M A C R O S - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------- - * T Y P E D E F S A N D S T R U C T U R E S - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------- - * P R O T O T Y P E S O F L O C A L F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ -VOID -F12PmThermalInit ( - IN CPU_SPECIFIC_SERVICES *FamilySpecificServices, - IN AMD_CPU_EARLY_PARAMS *CpuEarlyParamsPtr, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -/*---------------------------------------------------------------------------------------- - * E X P O R T E D F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ - -/*----------------------------------------------------------------------------------------*/ -/** - * Main entry point for initializing the SW Thermal Control - * safety net feature. - * - * This must be run by all Family 12h core 0s in the system. - * - * @param[in] FamilySpecificServices The current Family Specific Services. - * @param[in] CpuEarlyParamsPtr Service parameters. - * @param[in] StdHeader Config handle for library and services. - */ -VOID -F12PmThermalInit ( - IN CPU_SPECIFIC_SERVICES *FamilySpecificServices, - IN AMD_CPU_EARLY_PARAMS *CpuEarlyParamsPtr, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - UINT32 NbCaps; - UINT32 LocalPciRegister; - PCI_ADDR PciAddress; - - PciAddress.AddressValue = NB_CAPS_PCI_ADDR; - LibAmdPciRead (AccessWidth32, PciAddress, &NbCaps, StdHeader); - if (((NB_CAPS_REGISTER *) &NbCaps)->HtcCapable == 1) { - PciAddress.AddressValue = HTC_PCI_ADDR; - LibAmdPciRead (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader); - if (((HTC_REGISTER *) &LocalPciRegister)->HtcTmpLmt != 0) { - // Enable HTC - ((HTC_REGISTER *) &LocalPciRegister)->HtcEn = 1; - LibAmdPciWrite (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader); - } - } - if (((NB_CAPS_REGISTER *) &NbCaps)->LHtcCapable == 1) { - PciAddress.AddressValue = LHTC_PCI_ADDR; - LibAmdPciRead (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader); - if (((LHTC_REGISTER *) &LocalPciRegister)->LHtcTmpLmt != 0) { - // Enable local HTC - ((LHTC_REGISTER *) &LocalPciRegister)->LHtcEn = 1; - LibAmdPciWrite (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader); - } - } -} diff --git a/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x12/cpuF12SoftwareThermal.h b/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x12/cpuF12SoftwareThermal.h deleted file mode 100644 index 1945c01f2d..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x12/cpuF12SoftwareThermal.h +++ /dev/null @@ -1,78 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * AMD Family_12 thermal initialization related functions and structures - * - * Performs processor thermal initialization. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: CPU/F12 - * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $ - * - */ -/* - ****************************************************************************** - * - * Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - ****************************************************************************** - */ - -#ifndef _CPU_F12_SOFTWARE_THERMAL_H_ -#define _CPU_F12_SOFTWARE_THERMAL_H_ - - -/*--------------------------------------------------------------------------------------- - * M I X E D (Definitions And Macros / Typedefs, Structures, Enums) - *--------------------------------------------------------------------------------------- - */ - - -/*--------------------------------------------------------------------------------------- - * D E F I N I T I O N S A N D M A C R O S - *--------------------------------------------------------------------------------------- - */ - - -/*--------------------------------------------------------------------------------------- - * T Y P E D E F S, S T R U C T U R E S, E N U M S - *--------------------------------------------------------------------------------------- - */ - - -/*--------------------------------------------------------------------------------------- - * F U N C T I O N P R O T O T Y P E - *--------------------------------------------------------------------------------------- - */ -VOID -F12PmThermalInit ( - IN CPU_SPECIFIC_SERVICES *FamilySpecificServices, - IN AMD_CPU_EARLY_PARAMS *CpuEarlyParamsPtr, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -#endif // _CPU_F12_SOFTWARE_THERMAL_H_ diff --git a/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x12/cpuF12Utilities.c b/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x12/cpuF12Utilities.c deleted file mode 100644 index 8fe929844f..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x12/cpuF12Utilities.c +++ /dev/null @@ -1,594 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * AMD Family_12 specific utility functions. - * - * Provides numerous utility functions specific to family 12h. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: CPU/F12 - * @e \$Revision: 44870 $ @e \$Date: 2011-01-08 14:23:12 +0800 (Sat, 08 Jan 2011) $ - * - */ -/* - ****************************************************************************** - * - * Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - ****************************************************************************** - */ - -/*---------------------------------------------------------------------------------------- - * M O D U L E S U S E D - *---------------------------------------------------------------------------------------- - */ -#include "AGESA.h" -#include "amdlib.h" -#include "Ids.h" -#include "cpuRegisters.h" -#include "cpuFamilyTranslation.h" -#include "cpuPstateTables.h" -#include "cpuF12PowerMgmt.h" -#include "cpuServices.h" -#include "cpuF12Utilities.h" -#include "cpuPostInit.h" -#include "Filecode.h" -CODE_GROUP (G1_PEICC) -RDATA_GROUP (G1_PEICC) - -#define FILECODE PROC_CPU_FAMILY_0X12_CPUF12UTILITIES_FILECODE - -/*---------------------------------------------------------------------------------------- - * D E F I N I T I O N S A N D M A C R O S - *---------------------------------------------------------------------------------------- - */ -extern CPU_FAMILY_SUPPORT_TABLE PstateFamilyServiceTable; - -/*---------------------------------------------------------------------------------------- - * T Y P E D E F S A N D S T R U C T U R E S - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------- - * P R O T O T Y P E S O F L O C A L F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ -VOID -F12ConvertEnabledBitsIntoCount ( - OUT UINT8 *EnabledCoreCountPtr, - IN UINT8 FusedCoreCount, - IN UINT8 EnabledCores - ); - -BOOLEAN -F12GetNbPstateInfo ( - IN CPU_SPECIFIC_SERVICES *FamilySpecificServices, - IN PLATFORM_CONFIGURATION *PlatformConfig, - IN PCI_ADDR *PciAddress, - IN UINT32 NbPstate, - OUT UINT32 *FreqNumeratorInMHz, - OUT UINT32 *FreqDivisor, - OUT UINT32 *VoltageInuV, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -BOOLEAN -F12IsNbPstateEnabled ( - IN CPU_SPECIFIC_SERVICES *FamilySpecificServices, - IN PLATFORM_CONFIGURATION *PlatformConfig, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -BOOLEAN -F12GetProcIddMax ( - IN CPU_SPECIFIC_SERVICES *FamilySpecificServices, - IN UINT8 Pstate, - OUT UINT32 *ProcIddMax, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -UINT8 -F12GetNumberOfPhysicalCores ( - IN CPU_SPECIFIC_SERVICES *FamilySpecificServices, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -/*---------------------------------------------------------------------------------------- - * E X P O R T E D F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ - -VOID -F12ConvertEnabledBitsIntoCount ( - OUT UINT8 *EnabledCoreCountPtr, - IN UINT8 FusedCoreCount, - IN UINT8 EnabledCores - ) -{ - UINT8 i; - UINT8 j; - UINT8 EnabledCoreCount; - - EnabledCoreCount = 0; - - for (i = 0; i < FusedCoreCount+1; i++) { - j = 1; - if (!((BOOLEAN) (EnabledCores) & (j << i))) { - EnabledCoreCount++; - } - } - - *EnabledCoreCountPtr = EnabledCoreCount; -} - -/*---------------------------------------------------------------------------------------*/ -/** - * Disables the desired P-state. - * - * @CpuServiceMethod{::F_CPU_DISABLE_PSTATE}. - * - * @param[in] FamilySpecificServices The current Family Specific Services. - * @param[in] StateNumber The P-State to disable. - * @param[in] StdHeader Header for library and services - * - * @retval AGESA_SUCCESS Always succeeds. - */ -AGESA_STATUS -F12DisablePstate ( - IN CPU_SPECIFIC_SERVICES *FamilySpecificServices, - IN UINT8 StateNumber, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - UINT64 LocalMsrRegister; - - ASSERT (StateNumber < NM_PS_REG); - LibAmdMsrRead (PS_REG_BASE + (UINT32) StateNumber, &LocalMsrRegister, StdHeader); - ((PSTATE_MSR *) &LocalMsrRegister)->PsEnable = 0; - LibAmdMsrWrite (PS_REG_BASE + (UINT32) StateNumber, &LocalMsrRegister, StdHeader); - return (AGESA_SUCCESS); -} - -/*---------------------------------------------------------------------------------------*/ -/** - * Transitions the executing core to the desired P-state. - * - * @CpuServiceMethod{::F_CPU_TRANSITION_PSTATE}. - * - * @param[in] FamilySpecificServices The current Family Specific Services. - * @param[in] StateNumber The new P-State to make effective. - * @param[in] WaitForTransition True if the caller wants the transition completed upon return. - * @param[in] StdHeader Header for library and services - * - * @retval AGESA_SUCCESS Always Succeeds - */ -AGESA_STATUS -F12TransitionPstate ( - IN CPU_SPECIFIC_SERVICES *FamilySpecificServices, - IN UINT8 StateNumber, - IN BOOLEAN WaitForTransition, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - UINT64 LocalMsrRegister; - - LibAmdMsrRead (MSR_PSTATE_CURRENT_LIMIT, &LocalMsrRegister, StdHeader); - ASSERT (((PSTATE_CURLIM_MSR *) &LocalMsrRegister)->PstateMaxVal >= StateNumber); - LibAmdMsrRead (MSR_PSTATE_CTL, &LocalMsrRegister, StdHeader); - ((PSTATE_CTRL_MSR *) &LocalMsrRegister)->PstateCmd = (UINT64) StateNumber; - LibAmdMsrWrite (MSR_PSTATE_CTL, &LocalMsrRegister, StdHeader); - if (WaitForTransition) { - do { - LibAmdMsrRead (MSR_PSTATE_STS, &LocalMsrRegister, StdHeader); - } while (((PSTATE_STS_MSR *) &LocalMsrRegister)->CurPstate != (UINT64) StateNumber); - } - return (AGESA_SUCCESS); -} - -/*---------------------------------------------------------------------------------------*/ -/** - * Determines the rate at which the executing core's time stamp counter is - * incrementing. - * - * @CpuServiceMethod{::F_CPU_GET_TSC_RATE}. - * - * @param[in] FamilySpecificServices The current Family Specific Services. - * @param[out] FrequencyInMHz TSC actual frequency. - * @param[in] StdHeader Header for library and services. - * - * @return The most severe status of all called services - */ -AGESA_STATUS -F12GetTscRate ( - IN CPU_SPECIFIC_SERVICES *FamilySpecificServices, - OUT UINT32 *FrequencyInMHz, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - UINT8 NumBoostStates; - UINT32 LocalPciRegister; - UINT64 LocalMsrRegister; - PCI_ADDR PciAddress; - PSTATE_CPU_FAMILY_SERVICES *FamilyServices; - - LibAmdMsrRead (0xC0010015, &LocalMsrRegister, StdHeader); - if ((LocalMsrRegister & 0x01000000) != 0) { - FamilyServices = NULL; - GetFeatureServicesOfCurrentCore (&PstateFamilyServiceTable, (const VOID **) &FamilyServices, StdHeader); - ASSERT (FamilyServices != NULL); - - PciAddress.AddressValue = CPB_CTRL_PCI_ADDR; - LibAmdPciRead (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader); - NumBoostStates = (UINT8) ((CPB_CTRL_REGISTER *) &LocalPciRegister)->NumBoostStates; - return (FamilyServices->GetPstateFrequency (FamilyServices, NumBoostStates, FrequencyInMHz, StdHeader)); - } else { - return (FamilySpecificServices->GetCurrentNbFrequency (FamilySpecificServices, FrequencyInMHz, StdHeader)); - } -} - -/*---------------------------------------------------------------------------------------*/ -/** - * Determines the NB clock on the desired node. - * - * @CpuServiceMethod{::F_CPU_GET_NB_FREQ}. - * - * @param[in] FamilySpecificServices The current Family Specific Services. - * @param[out] FrequencyInMHz Northbridge clock frequency in MHz. - * @param[in] StdHeader Header for library and services - * - * @retval AGESA_SUCCESS Always succeeds. - */ -AGESA_STATUS -F12GetCurrentNbFrequency ( - IN CPU_SPECIFIC_SERVICES *FamilySpecificServices, - OUT UINT32 *FrequencyInMHz, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - UINT32 LocalPciRegister; - UINT32 MainPllFid; - PCI_ADDR PciAddress; - - PciAddress.AddressValue = CPTC0_PCI_ADDR; - LibAmdPciRead (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader); - - MainPllFid = ((CLK_PWR_TIMING_CTRL_REGISTER *) &LocalPciRegister)->MainPllOpFreqId; - - *FrequencyInMHz = ((MainPllFid + 0x10) * 100); - return (AGESA_SUCCESS); -} - -/*---------------------------------------------------------------------------------------*/ -/** - * Determines the NB clock on the desired node. - * - * @CpuServiceMethod{::F_CPU_GET_NB_PSTATE_INFO}. - * - * @param[in] FamilySpecificServices The current Family Specific Services. - * @param[in] PlatformConfig Platform profile/build option config structure. - * @param[in] PciAddress The segment, bus, and device numbers of the CPU in question. - * @param[in] NbPstate The NB P-state number to check. - * @param[out] FreqNumeratorInMHz The desired node's frequency numerator in megahertz. - * @param[out] FreqDivisor The desired node's frequency divisor. - * @param[out] VoltageInuV The desired node's voltage in microvolts. - * @param[in] StdHeader Handle of Header for calling lib functions and services. - * - * @retval TRUE NbPstate is valid - * @retval FALSE NbPstate is disabled or invalid - */ -BOOLEAN -F12GetNbPstateInfo ( - IN CPU_SPECIFIC_SERVICES *FamilySpecificServices, - IN PLATFORM_CONFIGURATION *PlatformConfig, - IN PCI_ADDR *PciAddress, - IN UINT32 NbPstate, - OUT UINT32 *FreqNumeratorInMHz, - OUT UINT32 *FreqDivisor, - OUT UINT32 *VoltageInuV, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - UINT32 NbVid; - UINT32 LocalPciRegister; - UINT32 MainPllFreq; - BOOLEAN PstateIsValid; - - PstateIsValid = FALSE; - if ((NbPstate == 0) || ((NbPstate == 1) && FamilySpecificServices->IsNbPstateEnabled (FamilySpecificServices, PlatformConfig, StdHeader))) { - FamilySpecificServices->GetCurrentNbFrequency (FamilySpecificServices, &MainPllFreq, StdHeader); - *FreqNumeratorInMHz = (MainPllFreq * 4); - if (NbPstate == 0) { - PciAddress->Address.Function = FUNC_3; - PciAddress->Address.Register = CPTC2_REG; - LibAmdPciRead (AccessWidth32, *PciAddress, &LocalPciRegister, StdHeader); - *FreqDivisor = ((CLK_PWR_TIMING_CTRL2_REGISTER *) &LocalPciRegister)->NbPs0NclkDiv; - NbVid = ((CLK_PWR_TIMING_CTRL2_REGISTER *) &LocalPciRegister)->NbPs0Vid; - } else { - PciAddress->Address.Function = FUNC_6; - PciAddress->Address.Register = NB_PSTATE_CFG_LOW_REG; - LibAmdPciRead (AccessWidth32, *PciAddress, &LocalPciRegister, StdHeader); - *FreqDivisor = ((NB_PSTATE_CFG_LOW_REGISTER *) &LocalPciRegister)->NbPs1NclkDiv; - NbVid = ((NB_PSTATE_CFG_LOW_REGISTER *) &LocalPciRegister)->NbPs1Vid; - } - *VoltageInuV = (1550000 - (12500 * NbVid)); - PstateIsValid = TRUE; - } - return PstateIsValid; -} - -/*---------------------------------------------------------------------------------------*/ -/** - * Is the Northbridge PState feature enabled? - * - * @CpuServiceMethod{::F_IS_NB_PSTATE_ENABLED}. - * - * @param[in] FamilySpecificServices The current Family Specific Services. - * @param[in] PlatformConfig Platform profile/build option config structure. - * @param[in] StdHeader Handle of Header for calling lib functions and services. - * - * @retval TRUE The NB PState feature is enabled. - * @retval FALSE The NB PState feature is not enabled. - */ -BOOLEAN -F12IsNbPstateEnabled ( - IN CPU_SPECIFIC_SERVICES *FamilySpecificServices, - IN PLATFORM_CONFIGURATION *PlatformConfig, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - UINT32 LocalPciRegister; - PCI_ADDR PciAddress; - - PciAddress.AddressValue = NB_PSTATE_CFG_LOW_PCI_ADDR; - LibAmdPciRead (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader); - return ((BOOLEAN) (((NB_PSTATE_CFG_LOW_REGISTER *) &LocalPciRegister)->NbPsCap == 1)); -} - -/*---------------------------------------------------------------------------------------*/ -/** - * Returns whether or not BIOS is responsible for configuring the NB COFVID. - * - * @CpuServiceMethod{::F_CPU_IS_NBCOF_INIT_NEEDED}. - * - * @param[in] FamilySpecificServices The current Family Specific Services. - * @param[in] PciAddress The northbridge to query by pci base address. - * @param[out] NbCofVidUpdateRequired TRUE, perform northbridge frequency and voltage config, - * FALSE, do not configure them. - * @param[in] StdHeader Header for library and services - * - * @retval AGESA_SUCCESS Always succeeds. - */ -AGESA_STATUS -F12GetNbCofVidUpdate ( - IN CPU_SPECIFIC_SERVICES *FamilySpecificServices, - IN PCI_ADDR *PciAddress, - OUT BOOLEAN *NbCofVidUpdateRequired, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - *NbCofVidUpdateRequired = FALSE; - return (AGESA_SUCCESS); -} - -/*---------------------------------------------------------------------------------------*/ -/** - * Initially launches the desired core to run from the reset vector. - * - * @CpuServiceMethod{::F_CPU_AP_INITIAL_LAUNCH}. - * - * @param[in] FamilySpecificServices The current Family Specific Services. - * @param[in] SocketNum The Processor on which the core is to be launched - * @param[in] ModuleNum The Module in that processor containing that core - * @param[in] CoreNum The Core to launch - * @param[in] PrimaryCoreNum The id of the module's primary core. - * @param[in] StdHeader Header for library and services - * - * @retval TRUE The core was launched - * @retval FALSE The core was previously launched - */ -BOOLEAN -F12LaunchApCore ( - IN CPU_SPECIFIC_SERVICES *FamilySpecificServices, - IN UINT32 SocketNum, - IN UINT32 ModuleNum, - IN UINT32 CoreNum, - IN UINT32 PrimaryCoreNum, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - UINT32 NodeRelativeCoreNum; - UINT32 LocalPciRegister; - PCI_ADDR PciAddress; - BOOLEAN LaunchFlag; - - // Code Start - LaunchFlag = FALSE; - NodeRelativeCoreNum = CoreNum - PrimaryCoreNum; - PciAddress.AddressValue = MAKE_SBDFO (0, 0, PCI_DEV_BASE, FUNC_0, 0); - - switch (NodeRelativeCoreNum) { - case 1: - PciAddress.Address.Register = HT_TRANS_CTRL; - LibAmdPciRead (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader); - if ((LocalPciRegister & HT_TRANS_CTRL_CPU1_EN) == 0) { - LocalPciRegister |= HT_TRANS_CTRL_CPU1_EN; - LibAmdPciWrite (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader); - LaunchFlag = TRUE; - } else { - LaunchFlag = FALSE; - } - break; - case 2: - PciAddress.Address.Register = ECS_HT_TRANS_CTRL; - LibAmdPciRead (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader); - - if ((LocalPciRegister & ECS_HT_TRANS_CTRL_CPU2_EN) == 0) { - LocalPciRegister |= ECS_HT_TRANS_CTRL_CPU2_EN; - LibAmdPciWrite (AccessWidth32, PciAddress, &LocalPciRegister, - StdHeader); - LaunchFlag = TRUE; - } else { - LaunchFlag = FALSE; - } - break; - - case 3: - PciAddress.Address.Register = ECS_HT_TRANS_CTRL; - LibAmdPciRead (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader); - if ((LocalPciRegister & ECS_HT_TRANS_CTRL_CPU3_EN) == 0) { - LocalPciRegister |= ECS_HT_TRANS_CTRL_CPU3_EN; - LibAmdPciWrite (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader); - LaunchFlag = TRUE; - } else { - LaunchFlag = FALSE; - } - break; - default: - break; - } - - return (LaunchFlag); -} - - -/*---------------------------------------------------------------------------------------*/ -/** - * Get CPU Specific Platform Type Info. - * - * @CpuServiceMethod{::F_CPU_GET_PLATFORM_TYPE_SPECIFIC_INFO}. - * - * This function returns Returns the platform features. - * - * @param[in] FamilySpecificServices The current Family Specific Services. - * @param[in,out] Features The Features supported by this platform. - * @param[in] StdHeader Handle of Header for calling lib functions and services. - * - * @retval AGESA_SUCCESS Always succeeds. - */ -AGESA_STATUS -F12GetPlatformTypeSpecificInfo ( - IN CPU_SPECIFIC_SERVICES *FamilySpecificServices, - IN OUT PLATFORM_FEATS *Features, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - return (AGESA_SUCCESS); -} - - -/*---------------------------------------------------------------------------------------*/ -/** - * Get CPU pstate current. - * - * @CpuServiceMethod{::F_CPU_GET_IDD_MAX}. - * - * This function returns the ProcIddMax. - * - * @param[in] FamilySpecificServices The current Family Specific Services. - * @param[in] Pstate The P-state to check. - * @param[out] ProcIddMax P-state current in mA. - * @param[in] StdHeader Handle of Header for calling lib functions and services. - * - * @retval TRUE P-state is enabled - * @retval FALSE P-state is disabled - */ -BOOLEAN -F12GetProcIddMax ( - IN CPU_SPECIFIC_SERVICES *FamilySpecificServices, - IN UINT8 Pstate, - OUT UINT32 *ProcIddMax, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - UINT32 IddDiv; - UINT32 CmpCap; - UINT32 LocalPciRegister; - UINT32 MsrAddress; - UINT64 PstateMsr; - BOOLEAN IsPstateEnabled; - PCI_ADDR PciAddress; - - IsPstateEnabled = FALSE; - - MsrAddress = (UINT32) (Pstate + PS_REG_BASE); - - ASSERT (MsrAddress <= PS_MAX_REG); - - LibAmdMsrRead (MsrAddress, &PstateMsr, StdHeader); - if (((PSTATE_MSR *) &PstateMsr)->PsEnable == 1) { - PciAddress.AddressValue = NB_CAPS_PCI_ADDR; - LibAmdPciRead (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader); // F3xE8 - CmpCap = (UINT32) (((NB_CAPS_REGISTER *) &LocalPciRegister)->CmpCap); - CmpCap++; - - switch (((PSTATE_MSR *) &PstateMsr)->IddDiv) { - case 0: - IddDiv = 1000; - break; - case 1: - IddDiv = 100; - break; - case 2: - IddDiv = 10; - break; - default: // IddDiv = 3 is reserved. Use 10 - ASSERT (FALSE); - IddDiv = 10; - break; - } - - *ProcIddMax = (UINT32) ((PSTATE_MSR *) &PstateMsr)->IddValue * IddDiv * CmpCap; - IsPstateEnabled = TRUE; - } - return IsPstateEnabled; -} - -/*---------------------------------------------------------------------------------------*/ -/** - * Get the number of physical cores of current processor. - * - * @CpuServiceMethod{::F_CPU_NUMBER_OF_PHYSICAL_CORES}. - * - * @param[in] FamilySpecificServices The current Family Specific Services. - * @param[in] StdHeader Handle of Header for calling lib functions and services. - * - * @return The number of physical cores. - */ -UINT8 -F12GetNumberOfPhysicalCores ( - IN CPU_SPECIFIC_SERVICES *FamilySpecificServices, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - CPUID_DATA CpuId; - - // - //CPUID.80000008h.ECX.NC + 1, 000b = 1, 001b = 2, etc. - // - LibAmdCpuidRead (CPUID_LONG_MODE_ADDR, &CpuId, StdHeader); - return ((UINT8) ((CpuId.ECX_Reg & 0xff) + 1)); -} diff --git a/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x12/cpuF12Utilities.h b/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x12/cpuF12Utilities.h deleted file mode 100644 index 3daf79017a..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x12/cpuF12Utilities.h +++ /dev/null @@ -1,130 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * AMD Family_12 specific utility functions. - * - * Provides numerous utility functions specific to family 12h. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: CPU - * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $ - * - */ -/* - ****************************************************************************** - * - * Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - ****************************************************************************** - */ - -#ifndef _CPU_F12_UTILITES_H_ -#define _CPU_F12_UTILITES_H_ - - -/*--------------------------------------------------------------------------------------- - * M I X E D (Definitions And Macros / Typedefs, Structures, Enums) - *--------------------------------------------------------------------------------------- - */ - - -/*--------------------------------------------------------------------------------------- - * D E F I N I T I O N S A N D M A C R O S - *--------------------------------------------------------------------------------------- - */ - - -/*--------------------------------------------------------------------------------------- - * T Y P E D E F S, S T R U C T U R E S, E N U M S - *--------------------------------------------------------------------------------------- - */ - -/*--------------------------------------------------------------------------------------- - * F U N C T I O N P R O T O T Y P E - *--------------------------------------------------------------------------------------- - */ - -AGESA_STATUS -F12DisablePstate ( - IN CPU_SPECIFIC_SERVICES *FamilySpecificServices, - IN UINT8 StateNumber, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -AGESA_STATUS -F12TransitionPstate ( - IN CPU_SPECIFIC_SERVICES *FamilySpecificServices, - IN UINT8 StateNumber, - IN BOOLEAN WaitForTransition, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -AGESA_STATUS -F12GetTscRate ( - IN CPU_SPECIFIC_SERVICES *FamilySpecificServices, - OUT UINT32 *FrequencyInMHz, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -AGESA_STATUS -F12GetCurrentNbFrequency ( - IN CPU_SPECIFIC_SERVICES *FamilySpecificServices, - OUT UINT32 *FrequencyInMHz, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -AGESA_STATUS -F12GetNbCofVidUpdate ( - IN CPU_SPECIFIC_SERVICES *FamilySpecificServices, - IN PCI_ADDR *PciAddress, - OUT BOOLEAN *NbCofVidUpdateRequired, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -BOOLEAN -F12LaunchApCore ( - IN CPU_SPECIFIC_SERVICES *FamilySpecificServices, - IN UINT32 SocketNum, - IN UINT32 ModuleNum, - IN UINT32 CoreNum, - IN UINT32 PrimaryCoreNum, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -CORE_ID_POSITION -F12CpuAmdCoreIdPositionInInitialApicId ( - IN CPU_SPECIFIC_SERVICES *FamilySpecificServices, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -AGESA_STATUS -F12GetPlatformTypeSpecificInfo ( - IN CPU_SPECIFIC_SERVICES *FamilySpecificServices, - IN OUT PLATFORM_FEATS *Features, - IN AMD_CONFIG_PARAMS *StdHeader - ); -#endif // _CPU_F12_UTILITES_H_ diff --git a/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x12/cpuF12WheaInitDataTables.c b/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x12/cpuF12WheaInitDataTables.c deleted file mode 100644 index b4c22dc84d..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x12/cpuF12WheaInitDataTables.c +++ /dev/null @@ -1,126 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * AMD Family_12 WHEA initial Data - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: CPU - * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $ - * - */ -/* - ****************************************************************************** - * - * Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - ****************************************************************************** - */ - -/*---------------------------------------------------------------------------------------- - * M O D U L E S U S E D - *---------------------------------------------------------------------------------------- - */ -#include "AGESA.h" -#include "cpuLateInit.h" -#include "cpuFamilyTranslation.h" -#include "Filecode.h" -CODE_GROUP (G3_DXE) -RDATA_GROUP (G3_DXE) - -#define FILECODE PROC_CPU_FAMILY_0X12_CPUF12WHEAINITDATATABLES_FILECODE - -/*---------------------------------------------------------------------------------------- - * D E F I N I T I O N S A N D M A C R O S - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------- - * T Y P E D E F S A N D S T R U C T U R E S - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------- - * P R O T O T Y P E S O F L O C A L F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ -VOID -GetF12WheaInitData ( - IN CPU_SPECIFIC_SERVICES *FamilySpecificServices, - OUT CONST VOID **F12WheaInitDataPtr, - OUT UINT8 *NumberOfElements, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -/*---------------------------------------------------------------------------------------- - * E X P O R T E D F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ -AMD_HEST_BANK_INIT_DATA F12HestBankInitData[] = { - {0xFFFFFFFF,0xFFFFFFFF,0x400,0x401,0x402,0x403}, - {0xFFFFFFFF,0xFFFFFFFF,0x404,0x405,0x406,0x407}, - {0xFFFFFFFF,0xFFFFFFFF,0x408,0x409,0x40A,0x40B}, - {0xFFFFFFFF,0xFFFFFFFF,0x40C,0x40D,0x40E,0x40F}, - {0xFFFFFFFF,0xFFFFFFFF,0x410,0x411,0x412,0x413}, - {0xFFFFFFFF,0xFFFFFFFF,0x414,0x415,0x416,0x417}, -}; - -AMD_WHEA_INIT_DATA F12WheaInitData = { - 0x000000000, // AmdGlobCapInitDataLsd - 0x000000000, // AmdGlobCapInitDataMsd - 0x00000003F, // AmdGlobCtrlInitDataLsd - 0x000000000, // AmdGlobCtrlInitDataMsd - 0x00, // AmdMcbClrStatusOnInit - 0x02, // AmdMcbStatusDataFormat - 0x00, // AmdMcbConfWriteEn - (sizeof (F12HestBankInitData) / sizeof (F12HestBankInitData[0])), // HestBankNum - &F12HestBankInitData[0] // Pointer to Initial data of HEST Bank -}; - - -/*---------------------------------------------------------------------------------------*/ -/** - * Returns the family specific WHEA table properties. - * - * @CpuServiceMethod{::F_CPU_GET_FAMILY_SPECIFIC_ARRAY}. - * - * @param[in] FamilySpecificServices The current Family Specific Services. - * @param[out] F12WheaInitDataPtr Points to the family 12h WHEA properties. - * @param[out] NumberOfElements Will be one to indicate one structure. - * @param[in] StdHeader Header for library and services. - * - */ -VOID -GetF12WheaInitData ( - IN CPU_SPECIFIC_SERVICES *FamilySpecificServices, - OUT CONST VOID **F12WheaInitDataPtr, - OUT UINT8 *NumberOfElements, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - *NumberOfElements = 1; - *F12WheaInitDataPtr = &F12WheaInitData; -} diff --git a/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/cpuFamRegisters.h b/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/cpuFamRegisters.h deleted file mode 100644 index db4e7ad7ce..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/cpuFamRegisters.h +++ /dev/null @@ -1,226 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * AMD CPU Register Table Related Functions - * - * Contains the definition of the CPU CPUID MSRs and PCI registers with BKDG recommended values - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: CPU - * @e \$Revision: 45026 $ @e \$Date: 2011-01-12 05:00:20 +0800 (Wed, 12 Jan 2011) $ - * - */ -/* - ****************************************************************************** - * - * Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - ****************************************************************************** - */ - -#ifndef _CPU_FAM_REGISTERS_H_ -#define _CPU_FAM_REGISTERS_H_ - -/* - *-------------------------------------------------------------- - * - * M O D U L E S U S E D - * - *--------------------------------------------------------------- - */ - -/* - *-------------------------------------------------------------- - * - * D E F I N I T I O N S / M A C R O S - * - *--------------------------------------------------------------- - */ - -// This define should be equal to the total number of families -// in the cpuFamily enum. -#define MAX_CPU_FAMILIES 64 -#define MAX_CPU_REVISIONS 63 // Max Cpu Revisions Per Family - -// CPU_LOGICAL_ID.Family equates -// Family 10h equates -#define AMD_FAMILY_10_RB 0x0000000000000001ull -#define AMD_FAMILY_10_BL 0x0000000000000002ull -#define AMD_FAMILY_10_DA 0x0000000000000004ull -#define AMD_FAMILY_10_HY 0x0000000000000008ull -#define AMD_FAMILY_10_PH 0x0000000000000010ull -#define AMD_FAMILY_10_C32 AMD_FAMILY_10_HY - -#define AMD_FAMILY_10 (AMD_FAMILY_10_RB | AMD_FAMILY_10_BL | AMD_FAMILY_10_DA | AMD_FAMILY_10_HY | AMD_FAMILY_10_PH) -#define AMD_FAMILY_GH (AMD_FAMILY_10) - -// Family 12h equates -#define AMD_FAMILY_12_LN 0x0000000000000020ull -#define AMD_FAMILY_12 (AMD_FAMILY_12_LN) -#define AMD_FAMILY_LN (AMD_FAMILY_12_LN) - -// Family 14h equates -#define AMD_FAMILY_14_ON 0x0000000000000040ull -#define AMD_FAMILY_14 (AMD_FAMILY_14_ON) -#define AMD_FAMILY_ON (AMD_FAMILY_14_ON) - -// Family 15h equates -#define AMD_FAMILY_15_OR 0x0000000000000100ull -#define AMD_FAMILY_OR (AMD_FAMILY_15_OR) -#define AMD_FAMILY_15 (AMD_FAMILY_15_OR) - -// Family 16h equates -#define AMD_FAMILY_16 0x0000000000000800ull -#define AMD_FAMILY_WF (AMD_FAMILY_16) - -// Family Unknown -#define AMD_FAMILY_UNKNOWN 0x8000000000000000ull - -// Family Group equates -#define AMD_FAMILY_GE_12 (AMD_FAMILY_12 | AMD_FAMILY_14 | AMD_FAMILY_15 | AMD_FAMILY_16) - -// Family 10h CPU_LOGICAL_ID.Revision equates -// ------------------------------------- - // Family 10h RB steppings -#define AMD_F10_RB_C0 0x0000000000000001ull -#define AMD_F10_RB_C1 0x0000000000000002ull -#define AMD_F10_RB_C2 0x0000000000000004ull -#define AMD_F10_RB_C3 0x0000000000000008ull - // Family 10h BL steppings -#define AMD_F10_BL_C2 0x0000000000000010ull -#define AMD_F10_BL_C3 0x0000000000000020ull - // Family 10h DA steppings -#define AMD_F10_DA_C2 0x0000000000000040ull -#define AMD_F10_DA_C3 0x0000000000000080ull - // Family 10h HY SCM steppings -#define AMD_F10_HY_SCM_D0 0x0000000000000100ull -#define AMD_F10_HY_SCM_D1 0x0000000000000400ull - // Family 10h HY MCM steppings -#define AMD_F10_HY_MCM_D0 0x0000000000000200ull -#define AMD_F10_HY_MCM_D1 0x0000000000000800ull - // Family 10h PH steppings -#define AMD_F10_PH_E0 0x0000000000001000ull - - // Family 10h Unknown stepping -#define AMD_F10_UNKNOWN 0x8000000000000000ull - - // Family 10h Miscellaneous equates -#define AMD_F10_C0 (AMD_F10_RB_C0) -#define AMD_F10_C1 (AMD_F10_RB_C1) -#define AMD_F10_C2 (AMD_F10_RB_C2 | AMD_F10_DA_C2 | AMD_F10_BL_C2) -#define AMD_F10_C3 (AMD_F10_RB_C3 | AMD_F10_DA_C3 | AMD_F10_BL_C3) -#define AMD_F10_Cx (AMD_F10_C0 | AMD_F10_C1 | AMD_F10_C2 | AMD_F10_C3) - -#define AMD_F10_RB_ALL (AMD_F10_RB_C0 | AMD_F10_RB_C1 | AMD_F10_RB_C2 | AMD_F10_RB_C3) - -#define AMD_F10_BL_ALL (AMD_F10_BL_C2 | AMD_F10_BL_C3) -#define AMD_F10_BL_Cx (AMD_F10_BL_C2 | AMD_F10_BL_C3) - -#define AMD_F10_DA_ALL (AMD_F10_DA_C2 | AMD_F10_DA_C3) -#define AMD_F10_DA_Cx (AMD_F10_DA_C2 | AMD_F10_DA_C3) - -#define AMD_F10_D0 (AMD_F10_HY_SCM_D0 | AMD_F10_HY_MCM_D0) -#define AMD_F10_D1 (AMD_F10_HY_SCM_D1 | AMD_F10_HY_MCM_D1) -#define AMD_F10_Dx (AMD_F10_D0 | AMD_F10_D1) - -#define AMD_F10_PH_ALL (AMD_F10_PH_E0) -#define AMD_F10_Ex (AMD_F10_PH_E0) - -#define AMD_F10_HY_ALL (AMD_F10_Dx) -#define AMD_F10_C32_ALL (AMD_F10_HY_SCM_D0 | AMD_F10_HY_SCM_D1) - -#define AMD_F10_GT_B0 (AMD_F10_Cx | AMD_F10_Dx | AMD_F10_Ex) -#define AMD_F10_GT_Bx (AMD_F10_Cx | AMD_F10_Dx | AMD_F10_Ex) -#define AMD_F10_GT_A2 (AMD_F10_Cx | AMD_F10_Dx | AMD_F10_Ex) -#define AMD_F10_GT_Ax (AMD_F10_Cx | AMD_F10_Dx | AMD_F10_Ex) -#define AMD_F10_GT_C0 ((AMD_F10_Cx & ~AMD_F10_C0) | AMD_F10_Dx | AMD_F10_Ex) -#define AMD_F10_GT_D0 (AMD_F10_Dx & ~AMD_F10_D0 | AMD_F10_Ex) - -#define AMD_F10_ALL (AMD_F10_Cx | AMD_F10_Dx | AMD_F10_Ex | AMD_F10_UNKNOWN) - -// Family 12h CPU_LOGICAL_ID.Revision equates -// ------------------------------------- - - // Family 12h LN steppings -#define AMD_F12_LN_A0 0x0000000000000001ull -#define AMD_F12_LN_A1 0x0000000000000002ull -#define AMD_F12_LN_B0 0x0000000000000004ull - // Family 12h Unknown stepping -#define AMD_F12_UNKNOWN 0x8000000000000000ull - -#define AMD_F12_LN_Ax (AMD_F12_LN_A0 | AMD_F12_LN_A1) -#define AMD_F12_LN_Bx (AMD_F12_LN_B0) - -#define AMD_F12_ALL (AMD_F12_LN_Ax | AMD_F12_LN_Bx | AMD_F12_UNKNOWN) - -// Family 14h CPU_LOGICAL_ID.Revision equates -// ------------------------------------- - - // Family 14h ON steppings -#define AMD_F14_ON_A0 0x0000000000000001ull -#define AMD_F14_ON_A1 0x0000000000000002ull -#define AMD_F14_ON_B0 0x0000000000000004ull -#define AMD_F14_ON_C0 0x0000000000000008ull - // Family 14h KR steppings -#define AMD_F14_KR_A0 0x0000000000000100ull -#define AMD_F14_KR_A1 0x0000000000000200ull -#define AMD_F14_KR_B0 0x0000000000000400ull - // Family 14h Unknown stepping -#define AMD_F14_UNKNOWN 0x8000000000000000ull - -#define AMD_F14_ON_Ax (AMD_F14_ON_A0 | AMD_F14_ON_A1) -#define AMD_F14_ON_Bx (AMD_F14_ON_B0) -#define AMD_F14_ON_Cx (AMD_F14_ON_C0) -#define AMD_F14_ON_ALL (AMD_F14_ON_Ax | AMD_F14_ON_Bx | AMD_F14_ON_Cx) - -#define AMD_F14_ALL (AMD_F14_ON_ALL | AMD_F14_UNKNOWN) - -// Family 15h CPU_LOGICAL_ID.Revision equates -// ------------------------------------- - - // Family 15h OROCHI steppings -#define AMD_F15_OR_A0 0x0000000000000001ull -#define AMD_F15_OR_A1 0x0000000000000002ull -#define AMD_F15_OR_B0 0x0000000000000004ull - // Family 15h TN steppings -#define AMD_F15_TN_A0 0x0000000000000100ull - // Family 15h Unknown stepping -#define AMD_F15_UNKNOWN 0x8000000000000000ull - -#define AMD_F15_OR_Ax (AMD_F15_OR_A0 | AMD_F15_OR_A1) -#define AMD_F15_OR_Bx AMD_F15_OR_B0 -#define AMD_F15_OR_GT_Ax (AMD_F15_OR_Bx) -#define AMD_F15_OR_LT_B1 (AMD_F15_OR_Ax | AMD_F15_OR_B0) -#define AMD_F15_OR_ALL (AMD_F15_OR_Ax | AMD_F15_OR_Bx) - -#define AMD_F15_ALL (AMD_F15_OR_ALL | AMD_F15_UNKNOWN) - -// Family 16h CPU_LOGICAL_ID.Revision equates -// TBD - -#endif // _CPU_FAM_REGISTERS_H_ - diff --git a/src/vendorcode/amd/agesa/f12/Proc/CPU/Feature/Makefile.inc b/src/vendorcode/amd/agesa/f12/Proc/CPU/Feature/Makefile.inc deleted file mode 100644 index 56d9f3c5bb..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/CPU/Feature/Makefile.inc +++ /dev/null @@ -1,20 +0,0 @@ -libagesa-y += PreserveMailbox.c -libagesa-y += cpuC6State.c -libagesa-y += cpuCacheFlushOnHalt.c -libagesa-y += cpuCacheInit.c -libagesa-y += cpuCoreLeveling.c -libagesa-y += cpuCpb.c -libagesa-y += cpuDmi.c -libagesa-y += cpuFeatureLeveling.c -libagesa-y += cpuFeatures.c -libagesa-y += cpuHwC1e.c -libagesa-y += cpuIoCstate.c -libagesa-y += cpuL3Features.c -libagesa-y += cpuLowPwrPstate.c -libagesa-y += cpuPstateGather.c -libagesa-y += cpuPstateLeveling.c -libagesa-y += cpuPstateTables.c -libagesa-y += cpuSlit.c -libagesa-y += cpuSrat.c -libagesa-y += cpuSwC1e.c -libagesa-y += cpuWhea.c diff --git a/src/vendorcode/amd/agesa/f12/Proc/CPU/Feature/PreserveMailbox.c b/src/vendorcode/amd/agesa/f12/Proc/CPU/Feature/PreserveMailbox.c deleted file mode 100644 index 35705b2e40..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/CPU/Feature/PreserveMailbox.c +++ /dev/null @@ -1,218 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * AMD AGESA CPU Preserve Registers used for AP Mailbox. - * - * Save and Restore the normal feature content of the registers being used for - * the AP Mailbox. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: CPU/Feature - * @e \$Revision: 50096 $ @e \$Date: 2011-04-02 06:17:10 +0800 (Sat, 02 Apr 2011) $ - * - */ -/* - ****************************************************************************** - * - * Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - ****************************************************************************** - */ - -/*---------------------------------------------------------------------------------------- - * M O D U L E S U S E D - *---------------------------------------------------------------------------------------- - */ -#include "AGESA.h" -#include "amdlib.h" -#include "Ids.h" -#include "Topology.h" -#include "GeneralServices.h" -#include "OptionMultiSocket.h" -#include "cpuRegisters.h" -#include "cpuApicUtilities.h" -#include "cpuServices.h" -#include "cpuFamilyTranslation.h" -#include "cpuFeatures.h" -#include "PreserveMailbox.h" -#include "heapManager.h" -#include "Filecode.h" -CODE_GROUP (G1_PEICC) -RDATA_GROUP (G1_PEICC) - -#define FILECODE PROC_CPU_FEATURE_PRESERVEMAILBOX_FILECODE -/*---------------------------------------------------------------------------------------- - * D E F I N I T I O N S A N D M A C R O S - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------- - * T Y P E D E F S A N D S T R U C T U R E S - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------- - * P R O T O T Y P E S O F L O C A L F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------- - * E X P O R T E D F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ -extern CPU_FAMILY_SUPPORT_TABLE PreserveMailboxFamilyServiceTable; - -/*---------------------------------------------------------------------------------------*/ -/** - * The contents of the mailbox registers should always be preserved. - * - * @param[in] PlatformConfig Contains the runtime modifiable feature input data. - * @param[in] StdHeader Config Handle for library, services. - * - * @retval TRUE Always TRUE - * - */ -BOOLEAN -STATIC -IsPreserveAroundMailboxEnabled ( - IN PLATFORM_CONFIGURATION *PlatformConfig, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - return TRUE; -} - -/*---------------------------------------------------------------------------------------*/ -/** - * Save and Restore or Initialize the content of the mailbox registers. - * - * The registers used for AP mailbox should have the content related to their function - * preserved. - * - * @param[in] EntryPoint Timepoint designator. - * @param[in] PlatformConfig Contains the runtime modifiable feature input data. - * @param[in] StdHeader Config Handle for library, services. - * - * @return AGESA_SUCCESS Always succeeds. - * - */ -AGESA_STATUS -STATIC -PreserveMailboxes ( - IN UINT64 EntryPoint, - IN PLATFORM_CONFIGURATION *PlatformConfig, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - PRESERVE_MAILBOX_FAMILY_SERVICES *FamilySpecificServices; - UINT32 Socket; - UINT32 Module; - PCI_ADDR BaseAddress; - PCI_ADDR MailboxRegister; - PRESERVE_MAILBOX_FAMILY_REGISTER *NextRegister; - AGESA_STATUS IgnoredStatus; - AGESA_STATUS HeapStatus; - UINT32 Value; - ALLOCATE_HEAP_PARAMS AllocateParams; - LOCATE_HEAP_PTR LocateParams; - UINT32 RegisterEntryIndex; - - BaseAddress.AddressValue = ILLEGAL_SBDFO; - - if (EntryPoint == CPU_FEAT_AFTER_COHERENT_DISCOVERY) { - // The save step. Save either the register content or zero (for cold boot, if family specifies that). - AllocateParams.BufferHandle = PRESERVE_MAIL_BOX_HANDLE; - AllocateParams.RequestedBufferSize = (sizeof (UINT32) * (MAX_PRESERVE_REGISTER_ENTRIES * (MAX_SOCKETS * MAX_DIES))); - AllocateParams.Persist = HEAP_SYSTEM_MEM; - HeapStatus = HeapAllocateBuffer (&AllocateParams, StdHeader); - ASSERT ((HeapStatus == AGESA_SUCCESS) && (AllocateParams.BufferPtr != NULL)); - LibAmdMemFill (AllocateParams.BufferPtr, 0xFF, AllocateParams.RequestedBufferSize, StdHeader); - RegisterEntryIndex = 0; - for (Socket = 0; Socket < GetPlatformNumberOfSockets (); Socket++) { - for (Module = 0; Module < GetPlatformNumberOfModules (); Module++) { - if (GetPciAddress (StdHeader, Socket, Module, &BaseAddress, &IgnoredStatus)) { - GetFeatureServicesOfSocket (&PreserveMailboxFamilyServiceTable, Socket, (const VOID **)&FamilySpecificServices, StdHeader); - ASSERT (FamilySpecificServices != NULL); - NextRegister = FamilySpecificServices->RegisterList; - while (NextRegister->Register.AddressValue != ILLEGAL_SBDFO) { - ASSERT (RegisterEntryIndex < - (MAX_PRESERVE_REGISTER_ENTRIES * GetPlatformNumberOfSockets () * GetPlatformNumberOfModules ())); - if (FamilySpecificServices->IsZeroOnCold && (!IsWarmReset (StdHeader))) { - Value = 0; - } else { - MailboxRegister = BaseAddress; - MailboxRegister.Address.Function = NextRegister->Register.Address.Function; - MailboxRegister.Address.Register = NextRegister->Register.Address.Register; - LibAmdPciRead (AccessWidth32, MailboxRegister, &Value, StdHeader); - Value &= NextRegister->Mask; - } - (* (MAILBOX_REGISTER_SAVE_ENTRY) AllocateParams.BufferPtr) [RegisterEntryIndex] = Value; - RegisterEntryIndex++; - NextRegister++; - } - } - } - } - } else if ((EntryPoint == CPU_FEAT_INIT_LATE_END) || (EntryPoint == CPU_FEAT_AFTER_RESUME_MTRR_SYNC)) { - // The restore step. Just write out the saved content in the buffer. - LocateParams.BufferHandle = PRESERVE_MAIL_BOX_HANDLE; - HeapStatus = HeapLocateBuffer (&LocateParams, StdHeader); - ASSERT ((HeapStatus == AGESA_SUCCESS) && (LocateParams.BufferPtr != NULL)); - RegisterEntryIndex = 0; - for (Socket = 0; Socket < GetPlatformNumberOfSockets (); Socket++) { - for (Module = 0; Module < GetPlatformNumberOfModules (); Module++) { - if (GetPciAddress (StdHeader, Socket, Module, &BaseAddress, &IgnoredStatus)) { - GetFeatureServicesOfSocket (&PreserveMailboxFamilyServiceTable, Socket, (const VOID **)&FamilySpecificServices, StdHeader); - NextRegister = FamilySpecificServices->RegisterList; - while (NextRegister->Register.AddressValue != ILLEGAL_SBDFO) { - ASSERT (RegisterEntryIndex < - (MAX_PRESERVE_REGISTER_ENTRIES * GetPlatformNumberOfSockets () * GetPlatformNumberOfModules ())); - MailboxRegister = BaseAddress; - MailboxRegister.Address.Function = NextRegister->Register.Address.Function; - MailboxRegister.Address.Register = NextRegister->Register.Address.Register; - LibAmdPciRead (AccessWidth32, MailboxRegister, &Value, StdHeader); - Value = ((Value & ~NextRegister->Mask) | (* (MAILBOX_REGISTER_SAVE_ENTRY) LocateParams.BufferPtr) [RegisterEntryIndex]); - LibAmdPciWrite (AccessWidth32, MailboxRegister, &Value, StdHeader); - RegisterEntryIndex++; - NextRegister++; - } - } - } - } - HeapStatus = HeapDeallocateBuffer (PRESERVE_MAIL_BOX_HANDLE, StdHeader); - } - return AGESA_SUCCESS; -} - - -CONST CPU_FEATURE_DESCRIPTOR ROMDATA CpuFeaturePreserveAroundMailbox = -{ - PreserveAroundMailbox, - (CPU_FEAT_AFTER_COHERENT_DISCOVERY | CPU_FEAT_INIT_LATE_END | CPU_FEAT_AFTER_RESUME_MTRR_SYNC), - IsPreserveAroundMailboxEnabled, - PreserveMailboxes -}; diff --git a/src/vendorcode/amd/agesa/f12/Proc/CPU/Feature/PreserveMailbox.h b/src/vendorcode/amd/agesa/f12/Proc/CPU/Feature/PreserveMailbox.h deleted file mode 100644 index 987bd9da6a..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/CPU/Feature/PreserveMailbox.h +++ /dev/null @@ -1,97 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * AMD AGESA CPU Preserve Registers used for AP Mailbox. - * - * Save and Restore the normal feature content of the registers being used for - * the AP Mailbox. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: CPU/Feature - * @e \$Revision: 50096 $ @e \$Date: 2011-04-02 06:17:10 +0800 (Sat, 02 Apr 2011) $ - * - */ -/* - ****************************************************************************** - * - * Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - ****************************************************************************** - */ - -#ifndef _PRESERVE_MAILBOX_H_ -#define _PRESERVE_MAILBOX_H_ - -/*---------------------------------------------------------------------------------------- - * M I X E D (Definitions And Macros / Typedefs, Structures, Enums) - *---------------------------------------------------------------------------------------- - */ -#define MAX_PRESERVE_REGISTER_ENTRIES 2 ///< There is room on the heap for up to this per node. - -/// Reference to a save buffer. -typedef UINT32 (*MAILBOX_REGISTER_SAVE_ENTRY) [MAX_PRESERVE_REGISTER_ENTRIES]; - -/*---------------------------------------------------------------------------------------- - * D E F I N I T I O N S A N D M A C R O S - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------- - * T Y P E D E F S A N D S T R U C T U R E S - *---------------------------------------------------------------------------------------- - */ - -/** - * Family specific mailbox register descriptor. - * - * Describes a register and bits within the register used as the mailbox. - */ -typedef struct { - PCI_ADDR Register; ///< The PCI address of a mailbox register. - UINT32 Mask; ///< The mask of bits used in Register as the mailbox. -} PRESERVE_MAILBOX_FAMILY_REGISTER; - -/** - * Descriptor for family specific save-restore. - * - * Provide a list of the register offsets to save-restore on each node. Optionally, zero the - * register instead of restoring it. - */ -typedef struct { - UINT16 Revision; ///< Interface version - // Public Data. - BOOLEAN IsZeroOnCold; ///< On a cold boot, zero the register instead of restore. - PRESERVE_MAILBOX_FAMILY_REGISTER *RegisterList; ///< The list of registers, terminated by ILLEGAL_SBDFO. -} PRESERVE_MAILBOX_FAMILY_SERVICES; - - -/*---------------------------------------------------------------------------------------- - * F U N C T I O N S P R O T O T Y P E - *---------------------------------------------------------------------------------------- - */ - -#endif // _PRESERVE_MAILBOX_H_ diff --git a/src/vendorcode/amd/agesa/f12/Proc/CPU/Feature/cpuC6State.c b/src/vendorcode/amd/agesa/f12/Proc/CPU/Feature/cpuC6State.c deleted file mode 100644 index 262867c187..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/CPU/Feature/cpuC6State.c +++ /dev/null @@ -1,260 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * AMD AGESA CPU C6 feature support code. - * - * Contains code that declares the AGESA CPU C6 related APIs - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: CPU/Feature - * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $ - * - */ -/* - ****************************************************************************** - * - * Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - ****************************************************************************** - */ - -/*---------------------------------------------------------------------------------------- - * M O D U L E S U S E D - *---------------------------------------------------------------------------------------- - */ -#include "AGESA.h" -#include "amdlib.h" -#include "Ids.h" -#include "cpuRegisters.h" -#include "cpuEarlyInit.h" -#include "GeneralServices.h" -#include "cpuFamilyTranslation.h" -#include "OptionMultiSocket.h" -#include "cpuApicUtilities.h" -#include "cpuServices.h" -#include "cpuFeatures.h" -#include "cpuC6State.h" -#include "Filecode.h" -CODE_GROUP (G1_PEICC) -RDATA_GROUP (G1_PEICC) - -#define FILECODE PROC_CPU_FEATURE_CPUC6STATE_FILECODE - -/*---------------------------------------------------------------------------------------- - * D E F I N I T I O N S A N D M A C R O S - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------- - * T Y P E D E F S A N D S T R U C T U R E S - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------- - * P R O T O T Y P E S O F L O C A L F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ -VOID -STATIC -EnableC6OnSocket ( - IN VOID *EntryPoint, - IN AMD_CONFIG_PARAMS *StdHeader, - IN AMD_CPU_EARLY_PARAMS *CpuEarlyParams - ); - -/*---------------------------------------------------------------------------------------- - * E X P O R T E D F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ -extern CPU_FAMILY_SUPPORT_TABLE C6FamilyServiceTable; -extern OPTION_MULTISOCKET_CONFIGURATION OptionMultiSocketConfiguration; - -/*---------------------------------------------------------------------------------------*/ -/** - * Should C6 be enabled - * - * @param[in] PlatformConfig Contains the runtime modifiable feature input data. - * @param[in] StdHeader Config Handle for library, services. - * - * @retval TRUE C6 is supported. - * @retval FALSE C6 cannot be enabled. - * - */ -BOOLEAN -STATIC -IsC6FeatureEnabled ( - IN PLATFORM_CONFIGURATION *PlatformConfig, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - UINT32 Socket; - BOOLEAN IsEnabled; - C6_FAMILY_SERVICES *FamilyServices; - - IsEnabled = FALSE; - if (PlatformConfig->CStateMode == CStateModeC6) { - IsEnabled = TRUE; - for (Socket = 0; Socket < GetPlatformNumberOfSockets (); Socket++) { - if (IsProcessorPresent (Socket, StdHeader)) { - GetFeatureServicesOfSocket (&C6FamilyServiceTable, Socket, (const VOID **)&FamilyServices, StdHeader); - if ((FamilyServices == NULL) || !FamilyServices->IsC6Supported (FamilyServices, Socket, PlatformConfig, StdHeader)) { - IsEnabled = FALSE; - break; - } - } - } - } - return IsEnabled; -} - -/*---------------------------------------------------------------------------------------*/ -/** - * Enable the C6 C-state - * - * @param[in] EntryPoint Timepoint designator. - * @param[in] PlatformConfig Contains the runtime modifiable feature input data. - * @param[in] StdHeader Config Handle for library, services. - * - * @retval AGESA_SUCCESS Always succeeds. - * - */ -AGESA_STATUS -STATIC -InitializeC6Feature ( - IN UINT64 EntryPoint, - IN PLATFORM_CONFIGURATION *PlatformConfig, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - UINT32 BscSocket; - UINT32 Ignored; - UINT32 BscCoreNum; - UINT32 Core; - UINT32 Socket; - UINT32 NumberOfSockets; - UINT32 NumberOfCores; - AP_TASK TaskPtr; - AMD_CPU_EARLY_PARAMS CpuEarlyParams; - C6_FAMILY_SERVICES *C6FamilyServices; - AGESA_STATUS IgnoredSts; - - CpuEarlyParams.PlatformConfig = *PlatformConfig; - - TaskPtr.FuncAddress.PfApTaskIC = EnableC6OnSocket; - TaskPtr.DataTransfer.DataSizeInDwords = 2; - TaskPtr.DataTransfer.DataPtr = &EntryPoint; - TaskPtr.DataTransfer.DataTransferFlags = 0; - TaskPtr.ExeFlags = PASS_EARLY_PARAMS; - OptionMultiSocketConfiguration.BscRunCodeOnAllSystemCore0s (&TaskPtr, StdHeader, &CpuEarlyParams); - - if ((EntryPoint & (CPU_FEAT_AFTER_POST_MTRR_SYNC | CPU_FEAT_AFTER_RESUME_MTRR_SYNC)) != 0) { - // Load any required microcode patches on both normal boot and resume from S3. - IdentifyCore (StdHeader, &BscSocket, &Ignored, &BscCoreNum, &IgnoredSts); - GetFeatureServicesOfSocket (&C6FamilyServiceTable, BscSocket, (const VOID **)&C6FamilyServices, StdHeader); - if (C6FamilyServices != NULL) { - C6FamilyServices->ReloadMicrocodePatchAfterMemInit (StdHeader); - } - - // run code on all APs - TaskPtr.DataTransfer.DataSizeInDwords = 0; - TaskPtr.ExeFlags = 0; - - NumberOfSockets = GetPlatformNumberOfSockets (); - - for (Socket = 0; Socket < NumberOfSockets; Socket++) { - if (IsProcessorPresent (Socket, StdHeader)) { - GetFeatureServicesOfSocket (&C6FamilyServiceTable, Socket, (const VOID **)&C6FamilyServices, StdHeader); - if (C6FamilyServices != NULL) { - // run code on all APs - TaskPtr.FuncAddress.PfApTask = C6FamilyServices->ReloadMicrocodePatchAfterMemInit; - if (GetActiveCoresInGivenSocket (Socket, &NumberOfCores, StdHeader)) { - for (Core = 0; Core < NumberOfCores; Core++) { - if ((Socket != BscSocket) || (Core != BscCoreNum)) { - ApUtilRunCodeOnSocketCore ((UINT8) Socket, (UINT8) Core, &TaskPtr, StdHeader); - } - } - } - } - } - } - } - return AGESA_SUCCESS; -} - - -/*---------------------------------------------------------------------------------------*/ -/** - * 'Local' core 0 task to enable C6 on it's socket. - * - * @param[in] EntryPoint Timepoint designator. - * @param[in] StdHeader Config Handle for library, services. - * @param[in] CpuEarlyParams Service parameters. - * - */ -VOID -STATIC -EnableC6OnSocket ( - IN VOID *EntryPoint, - IN AMD_CONFIG_PARAMS *StdHeader, - IN AMD_CPU_EARLY_PARAMS *CpuEarlyParams - ) -{ - - C6_FAMILY_SERVICES *FamilyServices; - - IDS_HDT_CONSOLE (CPU_TRACE, " C6 is enabled\n"); - - GetFeatureServicesOfCurrentCore (&C6FamilyServiceTable, (const VOID **)&FamilyServices, StdHeader); - FamilyServices->InitializeC6 (FamilyServices, - *((UINT64 *) EntryPoint), - &CpuEarlyParams->PlatformConfig, - StdHeader); -} - -/*---------------------------------------------------------------------------------------*/ -/** - * Reload microcode patch after memory is initialized. - * - * @param[in] StdHeader Config Handle for library, services. - * - */ -VOID -ReloadMicrocodePatchAfterMemInit ( - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - LoadMicrocodePatch (StdHeader); -} - - -CONST CPU_FEATURE_DESCRIPTOR ROMDATA CpuFeatureC6State = -{ - C6Cstate, - (CPU_FEAT_AFTER_PM_INIT | CPU_FEAT_AFTER_POST_MTRR_SYNC | CPU_FEAT_AFTER_RESUME_MTRR_SYNC), - IsC6FeatureEnabled, - InitializeC6Feature -}; diff --git a/src/vendorcode/amd/agesa/f12/Proc/CPU/Feature/cpuC6State.h b/src/vendorcode/amd/agesa/f12/Proc/CPU/Feature/cpuC6State.h deleted file mode 100644 index 7a163b1d3d..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/CPU/Feature/cpuC6State.h +++ /dev/null @@ -1,156 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * AMD AGESA CPU C6 Functions declarations. - * - * Contains code that declares the AGESA CPU C6 related APIs - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: CPU/Feature - * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $ - * - */ -/* - ****************************************************************************** - * - * Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - ****************************************************************************** - */ - -#ifndef _CPU_C6_STATE_H_ -#define _CPU_C6_STATE_H_ - -/*---------------------------------------------------------------------------------------- - * M I X E D (Definitions And Macros / Typedefs, Structures, Enums) - *---------------------------------------------------------------------------------------- - */ -// Forward declaration needed for multi-structure mutual references -AGESA_FORWARD_DECLARATION (C6_FAMILY_SERVICES); - -/*---------------------------------------------------------------------------------------- - * D E F I N I T I O N S A N D M A C R O S - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------- - * T Y P E D E F S A N D S T R U C T U R E S - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------*/ -/** - * Family specific call to check if C6 is supported. - * - * @param[in] C6Services C6 C-state services. - * @param[in] Socket Zero-based socket number. - * @param[in] PlatformConfig Contains the runtime modifiable feature input data. - * @param[in] StdHeader Config Handle for library, services. - * - * @retval TRUE C6 is supported. - * @retval FALSE C6 is not supported. - * - */ -typedef BOOLEAN F_C6_IS_SUPPORTED ( - IN C6_FAMILY_SERVICES *C6Services, - IN UINT32 Socket, - IN PLATFORM_CONFIGURATION *PlatformConfig, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -/// Reference to a Method. -typedef F_C6_IS_SUPPORTED *PF_C6_IS_SUPPORTED; - -/*---------------------------------------------------------------------------------------*/ -/** - * Family specific call to enable C6. - * - * @param[in] C6Services C6 services. - * @param[in] EntryPoint Timepoint designator. - * @param[in] PlatformConfig Contains the runtime modifiable feature input data. - * @param[in] StdHeader Config Handle for library, services. - * - * @return Family specific error value. - * - */ -typedef AGESA_STATUS F_C6_INIT ( - IN C6_FAMILY_SERVICES *C6Services, - IN UINT64 EntryPoint, - IN PLATFORM_CONFIGURATION *PlatformConfig, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -/// Reference to a Method. -typedef F_C6_INIT *PF_C6_INIT; - -/*---------------------------------------------------------------------------------------*/ -/** - * Family specific call to reload microcode patch after memory is initialized. - * - * @param[in] StdHeader Config Handle for library, services. - * - */ -typedef VOID F_C6_RELOAD_MICORCODE_PATCH_AFTER_MEM_INIT ( - IN AMD_CONFIG_PARAMS *StdHeader - ); - -/// Reference to a Method. -typedef F_C6_RELOAD_MICORCODE_PATCH_AFTER_MEM_INIT *PF_C6_RELOAD_MICORCODE_PATCH_AFTER_MEM_INIT; - -/** - * Provide the interface to the C6 Family Specific Services. - * - * Use the methods or data in this struct to adapt the feature code to a specific cpu family or model (or stepping!). - * Each supported Family must provide an implementation for all methods in this interface, even if the - * implementation is a CommonReturn(). - */ -struct _C6_FAMILY_SERVICES { - UINT16 Revision; ///< Interface version - // Public Methods. - PF_C6_IS_SUPPORTED IsC6Supported; ///< Method: Family specific call to check if C6 is supported. - PF_C6_INIT InitializeC6; ///< Method: Family specific call to enable C6. - PF_C6_RELOAD_MICORCODE_PATCH_AFTER_MEM_INIT ReloadMicrocodePatchAfterMemInit; ///< Method: Family specific call to reload microcode patch after memory is initialized. -}; - -/*---------------------------------------------------------------------------------------*/ -/** - * Reload microcode patch after memory is initialized. - * - * @param[in] StdHeader Config Handle for library, services. - * - */ -VOID -ReloadMicrocodePatchAfterMemInit ( - IN AMD_CONFIG_PARAMS *StdHeader - ); - -/*---------------------------------------------------------------------------------------- - * F U N C T I O N S P R O T O T Y P E - *---------------------------------------------------------------------------------------- - */ - -#endif // _CPU_C6_STATE_H_ diff --git a/src/vendorcode/amd/agesa/f12/Proc/CPU/Feature/cpuCacheFlushOnHalt.c b/src/vendorcode/amd/agesa/f12/Proc/CPU/Feature/cpuCacheFlushOnHalt.c deleted file mode 100644 index 6a0bb527f5..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/CPU/Feature/cpuCacheFlushOnHalt.c +++ /dev/null @@ -1,200 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * AMD CPU Cache Flush On Halt Function. - * - * Contains code to initialize Cache Flush On Halt feature. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: CPU - * @e \$Revision: 44737 $ @e \$Date: 2011-01-05 15:59:55 +0800 (Wed, 05 Jan 2011) $ - * - */ -/* - ****************************************************************************** - * - * Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - ****************************************************************************** - *---------------------------------------------------------------------------- - */ - - -/* - *---------------------------------------------------------------------------- - * MODULES USED - * - *---------------------------------------------------------------------------- - */ -#include "AGESA.h" -#include "Ids.h" -#include "amdlib.h" -#include "cpuRegisters.h" -#include "GeneralServices.h" -#include "cpuServices.h" -#include "cpuFamilyTranslation.h" -#include "cpuFeatures.h" -#include "cpuApicUtilities.h" -#include "OptionMultiSocket.h" -#include "Filecode.h" -CODE_GROUP (G2_PEI) -RDATA_GROUP (G2_PEI) -#define FILECODE PROC_CPU_FEATURE_CPUCACHEFLUSHONHALT_FILECODE -/*---------------------------------------------------------------------------- - * DEFINITIONS AND MACROS - * - *---------------------------------------------------------------------------- - */ - - -/*---------------------------------------------------------------------------- - * TYPEDEFS AND STRUCTURES - * - *---------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------- - * E X P O R T E D F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ -extern CPU_FAMILY_SUPPORT_TABLE CacheFlushOnHaltFamilyServiceTable; -extern OPTION_MULTISOCKET_CONFIGURATION OptionMultiSocketConfiguration; - -/*---------------------------------------------------------------------------- - * PROTOTYPES OF LOCAL FUNCTIONS - * - *---------------------------------------------------------------------------- - */ -VOID -STATIC -EnableCacheFlushOnHaltOnSocket ( - IN VOID *EntryPoint, - IN AMD_CONFIG_PARAMS *StdHeader, - IN AMD_CPU_EARLY_PARAMS *CpuEarlyParams - ); - -AGESA_STATUS -InitializeCacheFlushOnHaltFeature ( - IN UINT64 EntryPoint, - IN PLATFORM_CONFIGURATION *PlatformConfig, - IN OUT AMD_CONFIG_PARAMS *StdHeader - ); - -/*---------------------------------------------------------------------------------------- - * P U B L I C F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------*/ -/** - * Should cache flush on halt be enabled - * - * @param[in] PlatformConfig Contains the runtime modifiable feature input data. - * @param[in] StdHeader Config Handle for library, services. - * - * @retval TRUE core leveling is supported. - * @retval FALSE core leveling cannot be enabled. - * - */ -BOOLEAN -STATIC -IsCFOHEnabled ( - IN PLATFORM_CONFIGURATION *PlatformConfig, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - return (TRUE); -} -/* -----------------------------------------------------------------------------*/ -/** - * - * InitializeCacheFlushOnHaltFeature - * - * CPU feature leveling. Enable Cpu Cache Flush On Halt Function - * - * @param[in] EntryPoint Timepoint designator. - * @param[in] PlatformConfig Contains the runtime modifiable feature input data. - * @param[in,out] StdHeader Pointer to AMD_CONFIG_PARAMS struct. - * - * @return The most severe status of any family specific service. - */ -AGESA_STATUS -InitializeCacheFlushOnHaltFeature ( - IN UINT64 EntryPoint, - IN PLATFORM_CONFIGURATION *PlatformConfig, - IN OUT AMD_CONFIG_PARAMS *StdHeader - ) -{ - - AP_TASK TaskPtr; - AMD_CPU_EARLY_PARAMS CpuEarlyParams; - - CpuEarlyParams.PlatformConfig = *PlatformConfig; - - IDS_HDT_CONSOLE (CPU_TRACE, " Cache flush on hlt feature is enabled\n"); - TaskPtr.FuncAddress.PfApTaskIC = EnableCacheFlushOnHaltOnSocket; - TaskPtr.DataTransfer.DataSizeInDwords = 2; - TaskPtr.DataTransfer.DataPtr = &EntryPoint; - TaskPtr.DataTransfer.DataTransferFlags = 0; - TaskPtr.ExeFlags = PASS_EARLY_PARAMS; - OptionMultiSocketConfiguration.BscRunCodeOnAllSystemCore0s (&TaskPtr, StdHeader, &CpuEarlyParams); - - return AGESA_SUCCESS; -} - -/*---------------------------------------------------------------------------------------*/ -/** - * 'Local' core 0 task to enable Cache Flush On Halt on it's socket. - * - * @param[in] EntryPoint Timepoint designator. - * @param[in] StdHeader Config Handle for library, services. - * @param[in] CpuEarlyParams Service parameters. - * - */ -VOID -STATIC -EnableCacheFlushOnHaltOnSocket ( - IN VOID *EntryPoint, - IN AMD_CONFIG_PARAMS *StdHeader, - IN AMD_CPU_EARLY_PARAMS *CpuEarlyParams - ) -{ - CPU_CFOH_FAMILY_SERVICES *FamilyServices; - - GetFeatureServicesOfCurrentCore (&CacheFlushOnHaltFamilyServiceTable, (const VOID **)&FamilyServices, StdHeader); - if (FamilyServices != NULL) { - FamilyServices->SetCacheFlushOnHaltRegister (FamilyServices, *((UINT64 *) EntryPoint), &CpuEarlyParams->PlatformConfig, StdHeader); - } -} - -CONST CPU_FEATURE_DESCRIPTOR ROMDATA CpuFeatureCacheFlushOnHalt = -{ - CacheFlushOnHalt, - (CPU_FEAT_AFTER_POST_MTRR_SYNC | CPU_FEAT_AFTER_RESUME_MTRR_SYNC), - IsCFOHEnabled, - InitializeCacheFlushOnHaltFeature -}; diff --git a/src/vendorcode/amd/agesa/f12/Proc/CPU/Feature/cpuCacheInit.c b/src/vendorcode/amd/agesa/f12/Proc/CPU/Feature/cpuCacheInit.c deleted file mode 100644 index d84e6891ff..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/CPU/Feature/cpuCacheInit.c +++ /dev/null @@ -1,751 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * AMD CPU Execution Cache Allocation functions. - * - * Contains code for doing Execution Cache Allocation for ROM space - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: CPU - * @e \$Revision: 46142 $ @e \$Date: 2011-01-29 05:35:36 +0800 (Sat, 29 Jan 2011) $ - * - */ -/* - ****************************************************************************** - * - * Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - ****************************************************************************** - */ - - -/* - *---------------------------------------------------------------------------- - * MODULES USED - * - *---------------------------------------------------------------------------- - */ -#include "AGESA.h" -#include "amdlib.h" -#include "Ids.h" -#include "cpuRegisters.h" -#include "Topology.h" -#include "cpuServices.h" -#include "GeneralServices.h" -#include "cpuFamilyTranslation.h" -#include "cpuCacheInit.h" -#include "heapManager.h" -#include "Filecode.h" -CODE_GROUP (G1_PEICC) -RDATA_GROUP (G1_PEICC) - -#define FILECODE PROC_CPU_FEATURE_CPUCACHEINIT_FILECODE -/*---------------------------------------------------------------------------- - * DEFINITIONS AND MACROS - * - *---------------------------------------------------------------------------- - */ -// 4G - 1, ~max ROM space -#define SIZE_INFINITE_EXE_CACHE 0xFFFFFFFF - -/*---------------------------------------------------------------------------- - * TYPEDEFS AND STRUCTURES - * - *---------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------- - * L2 cache Association to Way translation table - *---------------------------------------------------------------------------- - */ -CONST UINT8 ROMDATA L2AssocToL2WayTranslationTable[] = -{ - 0, - 1, - 2, - 0xFF, - 4, - 0xFF, - 8, - 0xFF, - 16, - 0xFF, - 32, - 48, - 64, - 96, - 128, - 0xFF, -}; - - -/*---------------------------------------------------------------------------- - * PROTOTYPES OF LOCAL FUNCTIONS - * - *---------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------- - * EXPORTED FUNCTIONS - * - *---------------------------------------------------------------------------- - */ -UINT8 -STATIC -Ceiling ( - IN UINT32 Divisor, - IN UINT32 Dividend - ); - -UINT32 -STATIC -CalculateOccupiedExeCache ( - IN AMD_CONFIG_PARAMS *StdHeader - ); - -VOID -STATIC -CompareRegions ( - IN EXECUTION_CACHE_REGION ARegion, - IN EXECUTION_CACHE_REGION BRegion, - IN OUT MERGED_CACHE_REGION *CRegion, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -BOOLEAN -STATIC -IsPowerOfTwo ( - IN UINT32 TestNumber - ); - -/*---------------------------------------------------------------------------------------*/ -/** - * This function will setup ROM execution cache. - * - * The execution cache regions are passed in, the max number of execution cache regions - * is three. Several rules are checked for compliance. If a rule test fails then one of - * these error suffixes will be added to the general CPU_EVENT_EXECUTION_CACHE_ALLOCATION_ERROR - * in the SubReason field - * -1 available cache size is less than requested, the ROM execution cache - * region has been reduced or eliminated. - * -2 at least one execution cache region crosses the 1MB line, the ROM execution - * cache size has been reduced. - * -3 at least one execution cache region crosses the 4GB line, the ROM execution - * cache size has been reduced. - * -4 the start address of a region is not at the boundary of cache size, - * the starting address has been adjusted downward - * -5 execution cache start address less than D0000, request is ignored - * -6 more than 2 execution cache regions are above 1MB, request is ignored - * If the start address of all three regions are zero, then no execution cache is allocated. - * - * @param[in] StdHeader Handle to config for library and services - * @param[in] AmdExeAddrMapPtr Pointer to the start of EXECUTION_CACHE_REGION array - * - * @retval AGESA_SUCCESS No error - * @retval AGESA_WARNING AGESA_CACHE_SIZE_REDUCED; AGESA_CACHE_REGIONS_ACROSS_1MB; - * AGESA_CACHE_REGIONS_ACROSS_4GB; - * @retval AGESA_ERROR AGESA_REGION_NOT_ALIGNED_ON_BOUNDARY; - * AGESA_CACHE_START_ADDRESS_LESS_D0000; - * AGESA_THREE_CACHE_REGIONS_ABOVE_1MB; - * - */ -AGESA_STATUS -AllocateExecutionCache ( - IN AMD_CONFIG_PARAMS *StdHeader, - IN EXECUTION_CACHE_REGION *AmdExeAddrMapPtr - ) -{ - AGESA_STATUS AgesaStatus; - AMD_GET_EXE_SIZE_PARAMS AmdGetExeSize; - UINT32 CurrentAllocatedExeCacheSize; - UINT32 RemainingExecutionCacheSize; - UINT64 MsrData; - UINT64 SecondMsrData; - UINT32 RequestStartAddr; - UINT32 RequestSize; - UINT32 StartFixMtrr; - UINT32 CurrentMtrr; - UINT32 EndFixMtrr; - UINT8 i; - UINT8 Ignored; - CACHE_INFO *CacheInfoPtr; - CPU_SPECIFIC_SERVICES *FamilySpecificServices; - EXECUTION_CACHE_REGION MtrrV6; - EXECUTION_CACHE_REGION MtrrV7; - MERGED_CACHE_REGION Result; - - // - // If start addresses of all three regions are zero, then return early - // - if (AmdExeAddrMapPtr[0].ExeCacheStartAddr == 0) { - if (AmdExeAddrMapPtr[1].ExeCacheStartAddr == 0) { - if (AmdExeAddrMapPtr[2].ExeCacheStartAddr == 0) { - // No regions defined by the caller - return AGESA_SUCCESS; - } - } - } - - // Get available cache size for ROM execution - AmdGetExeSize.StdHeader = *StdHeader; - AgesaStatus = AmdGetAvailableExeCacheSize (&AmdGetExeSize); - CurrentAllocatedExeCacheSize = CalculateOccupiedExeCache (StdHeader); - ASSERT (CurrentAllocatedExeCacheSize <= AmdGetExeSize.AvailableExeCacheSize); - IDS_HDT_CONSOLE (CPU_TRACE, " Cache size available for execution cache: 0x%x\n", AmdGetExeSize.AvailableExeCacheSize); - RemainingExecutionCacheSize = AmdGetExeSize.AvailableExeCacheSize - CurrentAllocatedExeCacheSize; - - GetCpuServicesOfCurrentCore ((const CPU_SPECIFIC_SERVICES **)&FamilySpecificServices, StdHeader); - FamilySpecificServices->GetCacheInfo (FamilySpecificServices, (const VOID **)&CacheInfoPtr, &Ignored, StdHeader); - - // Process each request entry 0 to 2 - for (i = 0; i < 3; i++) { - // Exit if no more cache available - if (RemainingExecutionCacheSize == 0) { - break; - } - - // Skip the region if ExeCacheSize = 0 - if (AmdExeAddrMapPtr[i].ExeCacheSize == 0) { - continue; - } - - // Align starting addresses on 32K boundary - AmdExeAddrMapPtr[i].ExeCacheStartAddr = - AmdExeAddrMapPtr[i].ExeCacheStartAddr & 0xFFFF8000; - - // Adjust size to multiple of 32K (rounding up) - if ((AmdExeAddrMapPtr[i].ExeCacheSize % 0x8000) != 0) { - AmdExeAddrMapPtr[i].ExeCacheSize = ((AmdExeAddrMapPtr[i].ExeCacheSize + 0x8000) & 0xFFFF8000); - } - - // Boundary alignment check and confirm size is an even power of two - if ( !IsPowerOfTwo (AmdExeAddrMapPtr[i].ExeCacheSize) || - ((AmdExeAddrMapPtr[i].ExeCacheStartAddr % AmdExeAddrMapPtr[i].ExeCacheSize) != 0) ) { - AgesaStatus = AGESA_ERROR; - PutEventLog (AgesaStatus, - (CPU_EVENT_EXECUTION_CACHE_ALLOCATION_ERROR + AGESA_REGION_NOT_ALIGNED_ON_BOUNDARY), - i, AmdExeAddrMapPtr[i].ExeCacheStartAddr, AmdExeAddrMapPtr[i].ExeCacheSize, 0, StdHeader); - break; - } - - // Check start address boundary - if (AmdExeAddrMapPtr[i].ExeCacheStartAddr < 0xD0000) { - AgesaStatus = AGESA_ERROR; - PutEventLog (AgesaStatus, - (CPU_EVENT_EXECUTION_CACHE_ALLOCATION_ERROR + AGESA_CACHE_START_ADDRESS_LESS_D0000), - i, AmdExeAddrMapPtr[i].ExeCacheStartAddr, AmdExeAddrMapPtr[i].ExeCacheSize, 0, StdHeader); - break; - } - - if (CacheInfoPtr->CarExeType == LimitedByL2Size) { - // Verify available execution cache size for region 0 to 2 request - if (RemainingExecutionCacheSize < AmdExeAddrMapPtr[i].ExeCacheSize) { - // Request is larger than available, reduce the allocation & report the change - AmdExeAddrMapPtr[i].ExeCacheSize = RemainingExecutionCacheSize; - RemainingExecutionCacheSize = 0; - AgesaStatus = AGESA_WARNING; - PutEventLog (AgesaStatus, - (CPU_EVENT_EXECUTION_CACHE_ALLOCATION_ERROR + AGESA_CACHE_SIZE_REDUCED), - i, AmdExeAddrMapPtr[i].ExeCacheStartAddr, AmdExeAddrMapPtr[i].ExeCacheSize, 0, StdHeader); - } else { - RemainingExecutionCacheSize = RemainingExecutionCacheSize - AmdExeAddrMapPtr[i].ExeCacheSize; - } - } - IDS_HDT_CONSOLE (CPU_TRACE, " Exe cache allocated: Base 0x%x, Size 0x%x\n", AmdExeAddrMapPtr[i].ExeCacheStartAddr, AmdExeAddrMapPtr[i].ExeCacheSize); - - RequestStartAddr = AmdExeAddrMapPtr[i].ExeCacheStartAddr; - RequestSize = AmdExeAddrMapPtr[i].ExeCacheSize; - - if (RequestStartAddr < 0x100000) { - // Region starts below 1MB - Fixed MTRR region, - // turn on modification bit: MtrrFixDramModEn - LibAmdMsrRead (MSR_SYS_CFG, &MsrData, StdHeader); - MsrData |= 0x80000; - LibAmdMsrWrite (MSR_SYS_CFG, &MsrData, StdHeader); - - - // Check for 1M boundary crossing - if ((RequestStartAddr + RequestSize) > 0x100000) { - // Request spans the 1M boundary, reduce the size & report the change - RequestSize = 0x100000 - RequestStartAddr; - AmdExeAddrMapPtr[i].ExeCacheSize = RequestSize; - AgesaStatus = AGESA_WARNING; - PutEventLog (AgesaStatus, - (CPU_EVENT_EXECUTION_CACHE_ALLOCATION_ERROR + AGESA_CACHE_REGIONS_ACROSS_1MB), - i, RequestStartAddr, RequestSize, 0, StdHeader); - } - - // Find start MTRR and end MTRR for the requested region - StartFixMtrr = AMD_MTRR_FIX4K_BASE + ((RequestStartAddr >> 15) & 0x7); - EndFixMtrr = AMD_MTRR_FIX4K_BASE + ((((RequestStartAddr + RequestSize) - 1) >> 15) & 0x7); - - // - //Check Mtrr before we use it, - // if Mtrr has been used, we need to recover the previously allocated size. - // (only work in blocks of 32K size - no splitting of ways) - for (CurrentMtrr = StartFixMtrr; CurrentMtrr <= EndFixMtrr; CurrentMtrr++) { - LibAmdMsrRead (CurrentMtrr, &MsrData, StdHeader); - if ((CacheInfoPtr->CarExeType == LimitedByL2Size) && (MsrData != 0)) { - // MTRR previously allocated, recover size - RemainingExecutionCacheSize = RemainingExecutionCacheSize + 0x8000; - } else { - // Allocate this MTRR - MsrData = (UINT64) WP_IO; - LibAmdMsrWrite (CurrentMtrr, &MsrData, StdHeader); - } - } - // Turn off modification bit: MtrrFixDramModEn - LibAmdMsrRead (MSR_SYS_CFG, &MsrData, StdHeader); - MsrData &= 0xFFFFFFFFFFF7FFFFULL; - LibAmdMsrWrite (MSR_SYS_CFG, &MsrData, StdHeader); - - - } else { - // Region above 1MB - Variable MTRR region - // Need to check both VarMTRRs for each requested region for match or overlap - // - - // Check for 4G boundary crossing (using size-1 to keep in 32bit math range) - if ((0xFFFFFFFFUL - RequestStartAddr) < (RequestSize - 1)) { - RequestSize = (0xFFFFFFFFUL - RequestStartAddr) + 1; - AgesaStatus = AGESA_WARNING; - AmdExeAddrMapPtr[i].ExeCacheSize = RequestSize; - PutEventLog (AgesaStatus, - (CPU_EVENT_EXECUTION_CACHE_ALLOCATION_ERROR + AGESA_CACHE_REGIONS_ACROSS_4GB), - i, RequestStartAddr, RequestSize, 0, StdHeader); - } - LibAmdMsrRead (AMD_MTRR_VARIABLE_BASE6, &MsrData, StdHeader); - MtrrV6.ExeCacheStartAddr = ((UINT32) MsrData) & 0xFFFFF000UL; - LibAmdMsrRead (AMD_MTRR_VARIABLE_BASE6 + 1, &MsrData, StdHeader); - MtrrV6.ExeCacheSize = (0xFFFFFFFFUL - (((UINT32) MsrData) & 0xFFFFF000UL)) + 1; - - LibAmdMsrRead (AMD_MTRR_VARIABLE_BASE7, &MsrData, StdHeader); - MtrrV7.ExeCacheStartAddr = ((UINT32) MsrData) & 0xFFFFF000UL; - LibAmdMsrRead (AMD_MTRR_VARIABLE_BASE7 + 1, &MsrData, StdHeader); - MtrrV7.ExeCacheSize = (0xFFFFFFFFUL - (((UINT32) MsrData) & 0xFFFFF000UL)) + 1; - - CompareRegions (AmdExeAddrMapPtr[i], MtrrV6, &Result, StdHeader); - if (Result.OverlapType == EmptySet) { - // MTRR6 is empty. Allocate request into MTRR6. - // Note: since all merges are moved down to MTRR6, if MTRR6 is empty so should MTRR7 also be empty - MtrrV6.ExeCacheStartAddr = AmdExeAddrMapPtr[i].ExeCacheStartAddr; - MtrrV6.ExeCacheSize = AmdExeAddrMapPtr[i].ExeCacheSize; - } else if ((Result.OverlapType == Disjoint) || - (Result.OverlapType == NotCombinable)) { - // MTRR6 is in use, and request does not overlap with MTRR6, check MTRR7 - CompareRegions (AmdExeAddrMapPtr[i], MtrrV7, &Result, StdHeader); - if (Result.OverlapType == EmptySet) { - // MTRR7 is empty. Allocate request into MTRR7. - MtrrV7.ExeCacheStartAddr = AmdExeAddrMapPtr[i].ExeCacheStartAddr; - MtrrV7.ExeCacheSize = AmdExeAddrMapPtr[i].ExeCacheSize; - } else if ((Result.OverlapType == Disjoint) || - (Result.OverlapType == NotCombinable)) { - // MTRR7 is also in use and request does not overlap - error: 3rd region above 1M - AgesaStatus = AGESA_ERROR; - PutEventLog (AgesaStatus, - (CPU_EVENT_EXECUTION_CACHE_ALLOCATION_ERROR + AGESA_THREE_CACHE_REGIONS_ABOVE_1MB), - i, AmdExeAddrMapPtr[i].ExeCacheStartAddr, AmdExeAddrMapPtr[i].ExeCacheSize, 0, StdHeader); - break; - } else { - // Merge request with MTRR7 - MtrrV7.ExeCacheStartAddr = Result.MergedStartAddr; - MtrrV7.ExeCacheSize = Result.MergedSize; - if (CacheInfoPtr->CarExeType == LimitedByL2Size) { - RemainingExecutionCacheSize += Result.OverlapAmount; - } - } - } else { - // Request overlaps with MTRR6, Merge request with MTRR6 - MtrrV6.ExeCacheStartAddr = Result.MergedStartAddr; - MtrrV6.ExeCacheSize = Result.MergedSize; - if (CacheInfoPtr->CarExeType == LimitedByL2Size) { - RemainingExecutionCacheSize += Result.OverlapAmount; - } - CompareRegions (MtrrV6, MtrrV7, &Result, StdHeader); - if ((Result.OverlapType != Disjoint) && - (Result.OverlapType != EmptySet) && - (Result.OverlapType != NotCombinable)) { - // MTRR6 and MTRR7 now overlap, merge them into MTRR6 - MtrrV6.ExeCacheStartAddr = Result.MergedStartAddr; - MtrrV6.ExeCacheSize = Result.MergedSize; - MtrrV7.ExeCacheStartAddr = 0; - MtrrV7.ExeCacheSize = 0; - if (CacheInfoPtr->CarExeType == LimitedByL2Size) { - RemainingExecutionCacheSize += Result.OverlapAmount; - } - } - } - - // Set the VarMTRRs. Base first, then size/mask; this allows for expanding the region safely. - if (MtrrV6.ExeCacheSize != 0) { - MsrData = (UINT64) ( 0xFFFFFFFF00000000ULL | ((0xFFFFFFFFUL - (MtrrV6.ExeCacheSize - 1)) | 0x0800UL)); - MsrData &= CacheInfoPtr->VariableMtrrMask; - SecondMsrData = (UINT64) ( MtrrV6.ExeCacheStartAddr | (UINT64) (WP_IO & 0xFULL)); - } else { - MsrData = 0; - SecondMsrData = 0; - } - LibAmdMsrWrite (AMD_MTRR_VARIABLE_BASE6, &SecondMsrData, StdHeader); - LibAmdMsrWrite ((AMD_MTRR_VARIABLE_BASE6 + 1), &MsrData, StdHeader); - - if (MtrrV7.ExeCacheSize != 0) { - MsrData = (UINT64) ( 0xFFFFFFFF00000000ULL | ((0xFFFFFFFFUL - (MtrrV7.ExeCacheSize - 1)) | 0x0800UL)); - MsrData &= CacheInfoPtr->VariableMtrrMask; - SecondMsrData = (UINT64) ( MtrrV7.ExeCacheStartAddr | (UINT64) (WP_IO & 0xFULL)); - } else { - MsrData = 0; - SecondMsrData = 0; - } - LibAmdMsrWrite (AMD_MTRR_VARIABLE_BASE7, &SecondMsrData, StdHeader); - LibAmdMsrWrite ((AMD_MTRR_VARIABLE_BASE7 + 1), &MsrData, StdHeader); - } // endif of MTRR region check - } // end of requests For loop - - return AgesaStatus; -} - -/*---------------------------------------------------------------------------------------*/ -/** - * This function calculates available L2 cache space for ROM execution. - * - * @param[in] AmdGetExeSizeParams Pointer to the start of AmdGetExeSizeParamsPtr structure - * - * @retval AGESA_SUCCESS No error - * @retval AGESA_ALERT No cache available for execution cache. - * - */ -AGESA_STATUS -AmdGetAvailableExeCacheSize ( - IN OUT AMD_GET_EXE_SIZE_PARAMS *AmdGetExeSizeParams - ) -{ - UINT8 WayUsedForCar; - UINT8 L2Assoc; - UINT32 L2Size; - UINT32 L2WaySize; - UINT32 CurrentCoreNum; - UINT8 L2Ways; - UINT8 Ignored; - UINT32 DieNumber; - UINT32 TotalCores; - CPUID_DATA CpuIdDataStruct; - CACHE_INFO *CacheInfoPtr; - AP_MAIL_INFO ApMailboxInfo; - AGESA_STATUS IgnoredStatus; - CPU_SPECIFIC_SERVICES *FamilySpecificServices; - - GetCpuServicesOfCurrentCore ((const CPU_SPECIFIC_SERVICES **)&FamilySpecificServices, &AmdGetExeSizeParams->StdHeader); - FamilySpecificServices->GetCacheInfo (FamilySpecificServices, (const VOID **)&CacheInfoPtr, &Ignored, &AmdGetExeSizeParams->StdHeader); - // CAR_EXE mode is either "Limited by L2 size" or "Infinite Execution space" - ASSERT (CacheInfoPtr->CarExeType < MaxCarExeMode); - if (CacheInfoPtr->CarExeType == InfiniteExe) { - AmdGetExeSizeParams->AvailableExeCacheSize = SIZE_INFINITE_EXE_CACHE; - return AGESA_SUCCESS; - } - - // EXE cache size is limited by size of the L2, minus previous allocations for stack, heap, etc. - // Check for L2 cache size and way size - LibAmdCpuidRead (AMD_CPUID_L2L3Cache_L2TLB, &CpuIdDataStruct, &AmdGetExeSizeParams->StdHeader); - L2Assoc = (UINT8) ((CpuIdDataStruct.ECX_Reg >> 12) & 0x0F); - - // get L2Ways from L2 Association to Way translation table - L2Ways = L2AssocToL2WayTranslationTable[L2Assoc]; - ASSERT (L2Ways != 0xFF); - - // get L2Size - L2Size = 1024 * ((CpuIdDataStruct.ECX_Reg >> 16) & 0xFFFF); - - // get each L2WaySize - L2WaySize = L2Size / L2Ways; - - // Determine the size for execution cache - if (IsBsp (&AmdGetExeSizeParams->StdHeader, &IgnoredStatus)) { - // BSC (Boot Strap Core) - WayUsedForCar = Ceiling (CacheInfoPtr->BspStackSize, L2WaySize) + - Ceiling (CacheInfoPtr->MemTrainingBufferSize, L2WaySize) + - Ceiling (AMD_HEAP_SIZE_PER_CORE , L2WaySize) + - Ceiling (CacheInfoPtr->SharedMemSize, L2WaySize); - } else { - // AP (Application Processor) - GetCurrentCore (&CurrentCoreNum, &AmdGetExeSizeParams->StdHeader); - - GetApMailbox (&ApMailboxInfo.Info, &AmdGetExeSizeParams->StdHeader); - DieNumber = (1 << ApMailboxInfo.Fields.ModuleType); - GetActiveCoresInCurrentSocket (&TotalCores, &AmdGetExeSizeParams->StdHeader); - ASSERT ((TotalCores % DieNumber) == 0); - if ((CurrentCoreNum % (TotalCores / DieNumber)) == 0) { - WayUsedForCar = Ceiling (CacheInfoPtr->Core0StackSize , L2WaySize) + - Ceiling (CacheInfoPtr->MemTrainingBufferSize, L2WaySize) + - Ceiling (AMD_HEAP_SIZE_PER_CORE , L2WaySize) + - Ceiling (CacheInfoPtr->SharedMemSize, L2WaySize); - } else { - WayUsedForCar = Ceiling (CacheInfoPtr->Core1StackSize , L2WaySize) + - Ceiling (AMD_HEAP_SIZE_PER_CORE , L2WaySize) + - Ceiling (CacheInfoPtr->SharedMemSize, L2WaySize); - } - } - - ASSERT (WayUsedForCar < L2Ways); - - if (WayUsedForCar < L2Ways) { - AmdGetExeSizeParams->AvailableExeCacheSize = L2WaySize * (L2Ways - WayUsedForCar); - return AGESA_SUCCESS; - } else { - AmdGetExeSizeParams->AvailableExeCacheSize = 0; - return AGESA_ALERT; - } -} - - -/*---------------------------------------------------------------------------------------*/ -/** - * This function rounds a quotient up if the remainder is not zero. - * - * @param[in] Divisor The divisor - * @param[in] Dividend The dividend - * - * @retval Value Rounded quotient - * - */ -UINT8 -STATIC -Ceiling ( - IN UINT32 Divisor, - IN UINT32 Dividend - ) -{ - if ((Divisor % Dividend) == 0) { - return (UINT8) (Divisor / Dividend); - } else { - return (UINT8) ((Divisor / Dividend) + 1); - } -} - - -/*---------------------------------------------------------------------------------------*/ -/** - * This function calculates the amount of cache that has already been allocated on the - * executing core. - * - * @param[in] StdHeader Handle to config for library and services - * - * @returns Allocated size in bytes - * - */ -UINT32 -STATIC -CalculateOccupiedExeCache ( - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - UINT64 OccupExeCacheSize; - UINT64 MsrData; - UINT8 i; - - MsrData = 0; - OccupExeCacheSize = 0; - - // - //Calculate Variable MTRR base 6~7 - // - for (i = 0; i < 2; i++) { - LibAmdMsrRead ((AMD_MTRR_VARIABLE_BASE6 + (2*i)), &MsrData, StdHeader); - if (MsrData != 0) { - LibAmdMsrRead ((AMD_MTRR_VARIABLE_BASE6 + (2*i + 1)), &MsrData, StdHeader); - OccupExeCacheSize = OccupExeCacheSize + ((~((MsrData & (0xFFFF8000)) - 1))&0xFFFF8000); - } - } - - // - //Calculate Fixed MTRR base D0000~F8000 - // - for (i = 0; i < 6; i++) { - LibAmdMsrRead ((AMD_MTRR_FIX4K_BASE + 2 + i), &MsrData, StdHeader); - if (MsrData!= 0) { - OccupExeCacheSize = OccupExeCacheSize + 0x8000; - } - } - - return (UINT32)OccupExeCacheSize; -} - - -/*---------------------------------------------------------------------------------------*/ -/** - * This function compares two memory regions for overlap and returns the combined - * Base,Size to describe the new combined region. - * - * There are 13 cases for how two regions may overlap: key: [] region A, ** region B - * 1- [ ] *** 9- *** [ ] disjoint regions - * 2- [ ]*** 10- ***[ ] adjacent regions - * 3- [ ***] 11- **[**] common ending - * 4- [ *]** 12- *[** ] extending - * 5- [ ** ] 13- *[*]* contained - * 6- [*** ] common start, contained - * 7- [***] identity - * 8- [**]** common start, extending - * 0- one of the regions is empty (has base=0) - * - * @param[in] ARegion pointer to the base,size pair that describes region A - * @param[in] BRegion pointer to the base,size pair that describes region B - * @param[in,out] CRegion pointer to the base,size pair that describes region C This struct also has the - * overlap type and the amount of overlap between the regions. - * @param[in] StdHeader Handle to config for library and services - * - * @returns void, nothing - */ - -VOID -STATIC -CompareRegions ( - IN EXECUTION_CACHE_REGION ARegion, - IN EXECUTION_CACHE_REGION BRegion, - IN OUT MERGED_CACHE_REGION *CRegion, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - // Use Int64 to handle regions ending at or above the 4G boundary. - UINT64 EndOfA; - UINT64 EndOfB; - - - if ((BRegion.ExeCacheStartAddr == 0) || - (ARegion.ExeCacheStartAddr == 0)) { - CRegion->MergedStartAddr = - CRegion->MergedSize = - CRegion->OverlapAmount = 0; - CRegion->OverlapType = EmptySet; - return; - } - if (BRegion.ExeCacheStartAddr < ARegion.ExeCacheStartAddr) { - //swap regions A & B. this collapses types 9-13 onto 1-5 and reduces the number of tests - CRegion->MergedStartAddr = ARegion.ExeCacheStartAddr; - CRegion->MergedSize = ARegion.ExeCacheSize; - ARegion = BRegion; - BRegion.ExeCacheStartAddr = CRegion->MergedStartAddr; - BRegion.ExeCacheSize = CRegion->MergedSize; - } - CRegion->MergedStartAddr = - CRegion->MergedSize = - CRegion->OverlapType = - CRegion->OverlapAmount = 0; - - if (ARegion.ExeCacheStartAddr == BRegion.ExeCacheStartAddr) { - // Common start, cases 6,7, or 8 - if (ARegion.ExeCacheSize == BRegion.ExeCacheSize) { - // case 7, identity. Need to recover the overlap size - CRegion->MergedStartAddr = ARegion.ExeCacheStartAddr; - CRegion->MergedSize = ARegion.ExeCacheSize; - CRegion->OverlapAmount = ARegion.ExeCacheSize; - CRegion->OverlapType = Identity; - } else if (ARegion.ExeCacheSize < BRegion.ExeCacheSize) { - // case 8, common start extending - CRegion->MergedStartAddr = ARegion.ExeCacheStartAddr; - CRegion->MergedSize = BRegion.ExeCacheSize; - CRegion->OverlapType = CommonStartExtending; - CRegion->OverlapAmount = ARegion.ExeCacheSize; - } else { - // case 6, common start contained - CRegion->MergedStartAddr = ARegion.ExeCacheStartAddr; - CRegion->MergedSize = ARegion.ExeCacheSize; - CRegion->OverlapType = CommonStartContained; - CRegion->OverlapAmount = BRegion.ExeCacheSize; - } - } else { - // A_Base is less than B_Base. check for cases 1-5 - EndOfA = ((UINT64) ARegion.ExeCacheStartAddr) + ((UINT64) ARegion.ExeCacheSize); - - if (EndOfA < ((UINT64) BRegion.ExeCacheStartAddr)) { - // case 1, disjoint - CRegion->MergedStartAddr = - CRegion->MergedSize = - CRegion->OverlapAmount = 0; - CRegion->OverlapType = Disjoint; - - } else if (EndOfA == ((UINT64) BRegion.ExeCacheStartAddr)) { - // case 2, adjacent - CRegion->OverlapType = Adjacent; - CRegion->MergedStartAddr = ARegion.ExeCacheStartAddr; - CRegion->MergedSize = ARegion.ExeCacheSize + BRegion.ExeCacheSize; - CRegion->OverlapAmount = 0; - } else { - // EndOfA is > B_Base. check for cases 3,4,5 - EndOfB = ((UINT64) BRegion.ExeCacheStartAddr) + ((UINT64) BRegion.ExeCacheSize); - - if ( EndOfA < EndOfB) { - // case 4, extending - CRegion->OverlapType = Extending; - CRegion->MergedStartAddr = ARegion.ExeCacheStartAddr; - CRegion->MergedSize = (UINT32) (EndOfB - ((UINT64) ARegion.ExeCacheStartAddr)); - CRegion->OverlapAmount = (UINT32) (EndOfA - ((UINT64) BRegion.ExeCacheStartAddr)); - } else { - // case 3, same end; or case 5, contained - CRegion->OverlapType = Contained; - CRegion->MergedStartAddr = ARegion.ExeCacheStartAddr; - CRegion->MergedSize = ARegion.ExeCacheSize; - CRegion->OverlapAmount = BRegion.ExeCacheSize; - } - } - } // endif - // Once we have combined the regions, they must still obey the MTRR size and boundary rules - if ( CRegion->OverlapType != Disjoint ) { - if ((!(IsPowerOfTwo (CRegion->MergedSize))) || - ((CRegion->MergedStartAddr % CRegion->MergedSize) != 0) ) { - CRegion->OverlapType = NotCombinable; - } - } - -} - - -/*---------------------------------------------------------------------------------------*/ -/** - * This local function tests the parameter for being an even power of two - * - * @param[in] TestNumber Number to check - * - * @retval TRUE - TestNumber is a power of two, - * @retval FALSE - TestNumber is not a power of two - * - */ -BOOLEAN -STATIC -IsPowerOfTwo ( - IN UINT32 TestNumber - ) -{ - UINT32 PowerTwo; - - ASSERT (TestNumber >= 0x8000UL); - PowerTwo = 0x8000UL; // Start at 32K - while ( TestNumber > PowerTwo ) { - PowerTwo = PowerTwo * 2; - } - return (((TestNumber % PowerTwo) == 0) ? TRUE: FALSE); -} - - diff --git a/src/vendorcode/amd/agesa/f12/Proc/CPU/Feature/cpuCacheInit.h b/src/vendorcode/amd/agesa/f12/Proc/CPU/Feature/cpuCacheInit.h deleted file mode 100644 index a327d54317..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/CPU/Feature/cpuCacheInit.h +++ /dev/null @@ -1,132 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * AMD CPU Execution Cache Allocation functions. - * - * Contains code for doing Execution Cache Allocation for ROM space - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: CPU - * @e \$Revision: 50761 $ @e \$Date: 2011-04-14 06:16:02 +0800 (Thu, 14 Apr 2011) $ - * - */ -/* - ****************************************************************************** - * - * Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - ****************************************************************************** - */ - -#ifndef _CPU_CACHE_INIT_H_ -#define _CPU_CACHE_INIT_H_ - -/*---------------------------------------------------------------------------- - * Mixed (DEFINITIONS AND MACROS / TYPEDEFS, STRUCTURES, ENUMS) - * - *---------------------------------------------------------------------------- - */ - -/*----------------------------------------------------------------------------- - * DEFINITIONS AND MACROS - * - *----------------------------------------------------------------------------- - */ -#define AMD_MTRR_FIX4K_BASE 0x268 -#define AMD_MTRR_VARIABLE_BASE6 0x20C -#define AMD_MTRR_VARIABLE_BASE7 0x20E - -#define WP_IO 0x0505050505050505ull - -#define AGESA_CACHE_SIZE_REDUCED 1 -#define AGESA_CACHE_REGIONS_ACROSS_1MB 2 -#define AGESA_CACHE_REGIONS_ACROSS_4GB 3 -#define AGESA_REGION_NOT_ALIGNED_ON_BOUNDARY 4 -#define AGESA_CACHE_START_ADDRESS_LESS_D0000 5 -#define AGESA_THREE_CACHE_REGIONS_ABOVE_1MB 6 -#define AGESA_DEALLOCATE_CACHE_REGIONS 7 - -/*---------------------------------------------------------------------------- - * TYPEDEFS, STRUCTURES, ENUMS - * - *---------------------------------------------------------------------------- - */ -/// Cache-As-Ram Executable region allocation modes -typedef enum { - LimitedByL2Size, ///< Execution space must be allocated from L2 - InfiniteExe, ///< Family can support unlimited Execution space - MaxCarExeMode ///< Used as limit or bounds check -} CAR_EXE_MODE; - -/// Cache Information -typedef struct { - IN UINT32 BspStackSize; ///< Stack size of BSP - IN UINT32 Core0StackSize; ///< Stack size of primary cores - IN UINT32 Core1StackSize; ///< Stack size of all non primary cores - IN UINT32 MemTrainingBufferSize; ///< Memory training buffer size - IN UINT32 SharedMemSize; ///< Shared memory size - IN UINT64 VariableMtrrMask; ///< Mask to apply before variable MTRR writes - IN UINT64 VariableMtrrHeapMask; ///< Mask to apply before variable MTRR writes for use in heap init. - IN UINT64 HeapBaseMask; ///< Mask used for the heap MTRR settings - IN CAR_EXE_MODE CarExeType; ///< Indicates which algorithm to use when allocating EXE space -} CACHE_INFO; - -/// Merged memory region overlap type -typedef enum { - EmptySet, ///< One of the regions is zero length - Disjoint, ///< The two regions do not touch - Adjacent, ///< one region is next to the other, no gap - CommonEnd, ///< regions overlap with a common end point - Extending, ///< the 2nd region is extending the size of the 1st - Contained, ///< the 2nd region is wholely contained inside the 1st - CommonStartContained, ///< the 2nd region is contained in the 1st with a common start - Identity, ///< the two regions are the same - CommonStartExtending, ///< the 2nd region has same start as 1st, but is larger size - NotCombinable ///< the combined regions do not follow the cache block rules -} OVERLAP_TYPE; - -/// Result of merging two memory regions for cache coverage -typedef struct { - IN OUT UINT32 MergedStartAddr; ///< Start address of the merged regions - IN OUT UINT32 MergedSize; ///< Size of the merged regions - OUT UINT32 OverlapAmount; ///< the size of the overlapping section - OUT OVERLAP_TYPE OverlapType; ///< indicates how the two regions overlap -} MERGED_CACHE_REGION; - -/*---------------------------------------------------------------------------- - * FUNCTIONS PROTOTYPE - * - *---------------------------------------------------------------------------- - */ -AGESA_STATUS -AllocateExecutionCache ( - IN AMD_CONFIG_PARAMS *StdHeader, - IN EXECUTION_CACHE_REGION *AmdExeAddrMapPtr - ); - -#endif // _CPU_CACHE_INIT_H_ - diff --git a/src/vendorcode/amd/agesa/f12/Proc/CPU/Feature/cpuCoreLeveling.c b/src/vendorcode/amd/agesa/f12/Proc/CPU/Feature/cpuCoreLeveling.c deleted file mode 100644 index 27537d6753..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/CPU/Feature/cpuCoreLeveling.c +++ /dev/null @@ -1,364 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * AMD CPU Core Leveling Function. - * - * Contains code to Level the number of core in a multi-socket system - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: CPU - * @e \$Revision: 45951 $ @e \$Date: 2011-01-26 02:29:04 +0800 (Wed, 26 Jan 2011) $ - * - */ -/* - ****************************************************************************** - * - * Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - ****************************************************************************** - *---------------------------------------------------------------------------- - */ - - -/* - *---------------------------------------------------------------------------- - * MODULES USED - * - *---------------------------------------------------------------------------- - */ -#include "AGESA.h" -#include "AMD.h" -#include "amdlib.h" -#include "Topology.h" -#include "cpuRegisters.h" -#include "GeneralServices.h" -#include "cpuServices.h" -#include "cpuFamilyTranslation.h" -#include "cpuFeatures.h" -#include "cpuEarlyInit.h" -#include "heapManager.h" -#include "Filecode.h" -CODE_GROUP (G1_PEICC) -RDATA_GROUP (G1_PEICC) -#define FILECODE PROC_CPU_FEATURE_CPUCORELEVELING_FILECODE -/*---------------------------------------------------------------------------- - * DEFINITIONS AND MACROS - * - *---------------------------------------------------------------------------- - */ - - -/*---------------------------------------------------------------------------- - * TYPEDEFS AND STRUCTURES - * - *---------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------- - * E X P O R T E D F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ -extern CPU_FAMILY_SUPPORT_TABLE CoreLevelingFamilyServiceTable; - -/*---------------------------------------------------------------------------- - * PROTOTYPES OF LOCAL FUNCTIONS - * - *---------------------------------------------------------------------------- - */ -AGESA_STATUS -CoreLevelingAtEarly ( - IN UINT64 EntryPoint, - IN PLATFORM_CONFIGURATION *PlatformConfig, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -/*---------------------------------------------------------------------------------------- - * P U B L I C F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------*/ -/** - * Should core leveling be enabled - * - * @param[in] PlatformConfig Contains the runtime modifiable feature input data. - * @param[in] StdHeader Config Handle for library, services. - * - * @retval TRUE core leveling is supported. - * @retval FALSE core leveling cannot be enabled. - * - */ -BOOLEAN -STATIC -IsCoreLevelingEnabled ( - IN PLATFORM_CONFIGURATION *PlatformConfig, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - CORE_LEVELING_TYPE CoreLevelMode; - - CoreLevelMode = (CORE_LEVELING_TYPE) PlatformConfig->CoreLevelingMode; - if (CoreLevelMode != CORE_LEVEL_NONE) { - return (TRUE); - } else { - return (FALSE); - } -} - -/*---------------------------------------------------------------------------------------*/ -/** - * Performs core leveling for the system. - * - * This function implements the AMD_CPU_EARLY_PARAMS.CoreLevelingMode parameter. - * The possible modes are: - * -0 CORE_LEVEL_LOWEST Level to lowest common denominator - * -1 CORE_LEVEL_TWO Level to 2 cores - * -2 CORE_LEVEL_POWER_OF_TWO Level to 1,2,4 or 8 - * -3 CORE_LEVEL_NONE Do no leveling - * -4 CORE_LEVEL_COMPUTE_UNIT Level cores to one core per compute unit - * - * @param[in] EntryPoint Timepoint designator. - * @param[in] PlatformConfig Contains the leveling mode parameter - * @param[in] StdHeader Config handle for library and services - * - * @return The most severe status of any family specific service. - * - */ -AGESA_STATUS -CoreLevelingAtEarly ( - IN UINT64 EntryPoint, - IN PLATFORM_CONFIGURATION *PlatformConfig, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - UINT32 CoreNumPerComputeUnit; - UINT32 MinNumOfComputeUnit; - UINT32 EnabledComputeUnit; - UINT32 Socket; - UINT32 Module; - UINT32 NumberOfSockets; - UINT32 NumberOfModules; - UINT32 MinCoreCountOnNode; - UINT32 MaxCoreCountOnNode; - UINT32 LowCore; - UINT32 HighCore; - UINT32 LeveledCores; - UINT32 RequestedCores; - UINT32 TotalEnabledCoresOnNode; - BOOLEAN RegUpdated; - AP_MAIL_INFO ApMailboxInfo; - CORE_LEVELING_TYPE CoreLevelMode; - CPU_CORE_LEVELING_FAMILY_SERVICES *FamilySpecificServices; - WARM_RESET_REQUEST Request; - - IDS_HDT_CONSOLE (CPU_TRACE, "CoreLevelingAtEarly\n CoreLevelMode: %d\n", PlatformConfig->CoreLevelingMode); - - MaxCoreCountOnNode = 0; - MinCoreCountOnNode = 0xFFFFFFFF; - LeveledCores = 0; - CoreNumPerComputeUnit = 1; - MinNumOfComputeUnit = 0xFF; - - ASSERT (PlatformConfig->CoreLevelingMode < CoreLevelModeMax); - - // Get OEM IO core level mode - CoreLevelMode = (CORE_LEVELING_TYPE) PlatformConfig->CoreLevelingMode; - - // Get socket count - NumberOfSockets = GetPlatformNumberOfSockets (); - GetApMailbox (&ApMailboxInfo.Info, StdHeader); - NumberOfModules = ApMailboxInfo.Fields.ModuleType + 1; - - // Collect cpu core info - for (Socket = 0; Socket < NumberOfSockets; Socket++) { - if (IsProcessorPresent (Socket, StdHeader)) { - for (Module = 0; Module < NumberOfModules; Module++) { - if (GetGivenModuleCoreRange (Socket, Module, &LowCore, &HighCore, StdHeader)) { - // Get the highest and lowest core count in all nodes - TotalEnabledCoresOnNode = HighCore - LowCore + 1; - if (TotalEnabledCoresOnNode < MinCoreCountOnNode) { - MinCoreCountOnNode = TotalEnabledCoresOnNode; - } - if (TotalEnabledCoresOnNode > MaxCoreCountOnNode) { - MaxCoreCountOnNode = TotalEnabledCoresOnNode; - } - EnabledComputeUnit = TotalEnabledCoresOnNode; - switch (GetComputeUnitMapping (StdHeader)) { - case AllCoresMapping: - // All cores are in their own compute unit. - break; - case EvenCoresMapping: - // Cores are paired in compute units. - CoreNumPerComputeUnit = 2; - EnabledComputeUnit = (TotalEnabledCoresOnNode / 2); - break; - default: - ASSERT (FALSE); - } - // Get minimum of compute unit. This will either be the minimum number of cores (AllCoresMapping), - // or less (EvenCoresMapping). - if (EnabledComputeUnit < MinNumOfComputeUnit) { - MinNumOfComputeUnit = EnabledComputeUnit; - } - IDS_HDT_CONSOLE (CPU_TRACE, " Socket %d Module %d MaxCoreCountOnNode %d MinCoreCountOnNode %d TotalEnabledCoresOnNode %d EnabledComputeUnit %d MinNumOfComputeUnit %d\n", \ - Socket, Module, MaxCoreCountOnNode, MinCoreCountOnNode, TotalEnabledCoresOnNode, EnabledComputeUnit, MinNumOfComputeUnit); - } - } - } - } - - // Get LeveledCores - switch (CoreLevelMode) { - case CORE_LEVEL_LOWEST: - if (MinCoreCountOnNode == MaxCoreCountOnNode) { - return (AGESA_SUCCESS); - } - LeveledCores = (MinCoreCountOnNode / CoreNumPerComputeUnit) * CoreNumPerComputeUnit; - break; - case CORE_LEVEL_TWO: - LeveledCores = 2 / NumberOfModules; - if (LeveledCores != 0) { - LeveledCores = (LeveledCores <= MinCoreCountOnNode) ? LeveledCores : MinCoreCountOnNode; - } else { - return (AGESA_WARNING); - } - if ((LeveledCores * NumberOfModules) != 2) { - PutEventLog ( - AGESA_WARNING, - CPU_WARNING_ADJUSTED_LEVELING_MODE, - 2, (LeveledCores * NumberOfModules), 0, 0, StdHeader - ); - } - break; - case CORE_LEVEL_POWER_OF_TWO: - // Level to power of 2 (1, 2, 4, 8...) - LeveledCores = 1; - while (MinCoreCountOnNode >= (LeveledCores * 2)) { - LeveledCores = LeveledCores * 2; - } - break; - case CORE_LEVEL_COMPUTE_UNIT: - // Level cores to one core per compute unit, with additional reduction to level - // all processors to match the processor with the minimum number of cores. - if (CoreNumPerComputeUnit == 1) { - // If there is one core per compute unit, this is the same as CORE_LEVEL_LOWEST. - if (MinCoreCountOnNode == MaxCoreCountOnNode) { - return (AGESA_SUCCESS); - } - LeveledCores = MinCoreCountOnNode; - } else { - // If there are more than one core per compute unit, level to the number of compute units. - LeveledCores = MinNumOfComputeUnit; - } - break; - case CORE_LEVEL_ONE: - LeveledCores = 1; - if (NumberOfModules > 1) { - PutEventLog ( - AGESA_WARNING, - CPU_WARNING_ADJUSTED_LEVELING_MODE, - 1, NumberOfModules, 0, 0, StdHeader - ); - } - break; - case CORE_LEVEL_THREE: - case CORE_LEVEL_FOUR: - case CORE_LEVEL_FIVE: - case CORE_LEVEL_SIX: - case CORE_LEVEL_SEVEN: - case CORE_LEVEL_EIGHT: - case CORE_LEVEL_NINE: - case CORE_LEVEL_TEN: - case CORE_LEVEL_ELEVEN: - case CORE_LEVEL_TWELVE: - case CORE_LEVEL_THIRTEEN: - case CORE_LEVEL_FOURTEEN: - case CORE_LEVEL_FIFTEEN: - // MCM processors can not have an odd number of cores. For an odd CORE_LEVEL_N, MCM processors will be - // leveled as though CORE_LEVEL_N+1 was chosen. - // Processors with compute units disable all cores in an entire compute unit at a time, or on an MCM processor, - // two compute units at a time. For example, on an SCM processor with two cores per compute unit, the effective - // explicit levels are CORE_LEVEL_ONE, CORE_LEVEL_TWO, CORE_LEVEL_FOUR, CORE_LEVEL_SIX, and - // CORE_LEVEL_EIGHT. The same example for an MCM processor with two cores per compute unit has effective - // explicit levels of CORE_LEVEL_TWO, CORE_LEVEL_FOUR, CORE_LEVEL_EIGHT, and CORE_LEVEL_TWELVE. - RequestedCores = CoreLevelMode - CORE_LEVEL_THREE + 3; - LeveledCores = (RequestedCores + NumberOfModules - 1) / NumberOfModules; - LeveledCores = (LeveledCores / CoreNumPerComputeUnit) * CoreNumPerComputeUnit; - LeveledCores = (LeveledCores <= MinCoreCountOnNode) ? LeveledCores : MinCoreCountOnNode; - if (LeveledCores != 1) { - LeveledCores = (LeveledCores / CoreNumPerComputeUnit) * CoreNumPerComputeUnit; - } - if ((LeveledCores * NumberOfModules * CoreNumPerComputeUnit) != RequestedCores) { - PutEventLog ( - AGESA_WARNING, - CPU_WARNING_ADJUSTED_LEVELING_MODE, - RequestedCores, (LeveledCores * NumberOfModules * CoreNumPerComputeUnit), 0, 0, StdHeader - ); - } - break; - default: - ASSERT (FALSE); - } - - // Set down core register - for (Socket = 0; Socket < NumberOfSockets; Socket++) { - if (IsProcessorPresent (Socket, StdHeader)) { - GetFeatureServicesOfSocket (&CoreLevelingFamilyServiceTable, Socket, (const VOID **)&FamilySpecificServices, StdHeader); - if (FamilySpecificServices != NULL) { - for (Module = 0; Module < NumberOfModules; Module++) { - IDS_HDT_CONSOLE (CPU_TRACE, " SetDownCoreRegister: Socket %d Module %d LeveledCores %d CoreLevelMode %d\n", Socket, Module, LeveledCores, CoreLevelMode); - RegUpdated = FamilySpecificServices->SetDownCoreRegister (FamilySpecificServices, &Socket, &Module, &LeveledCores, CoreLevelMode, StdHeader); - // If the down core register is updated, trigger a warm reset. - if (RegUpdated) { - GetWarmResetFlag (StdHeader, &Request); - Request.RequestBit = TRUE; - Request.StateBits = Request.PostStage - 1; - IDS_HDT_CONSOLE (CPU_TRACE, " Request a warm reset.\n"); - SetWarmResetFlag (StdHeader, &Request); - } - } - } - } - } - - return (AGESA_SUCCESS); -} - - -CONST CPU_FEATURE_DESCRIPTOR ROMDATA CpuFeatureCoreLeveling = -{ - CoreLeveling, - (CPU_FEAT_AFTER_PM_INIT), - IsCoreLevelingEnabled, - CoreLevelingAtEarly -}; - -/*---------------------------------------------------------------------------------------- - * L O C A L F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ - diff --git a/src/vendorcode/amd/agesa/f12/Proc/CPU/Feature/cpuCpb.c b/src/vendorcode/amd/agesa/f12/Proc/CPU/Feature/cpuCpb.c deleted file mode 100644 index fdad8cc293..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/CPU/Feature/cpuCpb.c +++ /dev/null @@ -1,175 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * AMD AGESA CPU Core performance boost feature support code. - * - * Contains code that declares the AGESA CPU CPB related APIs - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: CPU/Feature - * @e \$Revision: 47856 $ @e \$Date: 2011-03-01 13:52:52 +0800 (Tue, 01 Mar 2011) $ - * - */ -/* - ****************************************************************************** - * - * Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - ****************************************************************************** - */ - -/*---------------------------------------------------------------------------------------- - * M O D U L E S U S E D - *---------------------------------------------------------------------------------------- - */ -#include "AGESA.h" -#include "cpuFamilyTranslation.h" -#include "cpuFeatures.h" -#include "cpuCpb.h" -#include "Filecode.h" -CODE_GROUP (G1_PEICC) -RDATA_GROUP (G1_PEICC) - -#define FILECODE PROC_CPU_FEATURE_CPUCPB_FILECODE - -/*---------------------------------------------------------------------------------------- - * D E F I N I T I O N S A N D M A C R O S - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------- - * T Y P E D E F S A N D S T R U C T U R E S - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------- - * P R O T O T Y P E S O F L O C A L F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------- - * E X P O R T E D F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ -extern CPU_FAMILY_SUPPORT_TABLE CpbFamilyServiceTable; - -/*---------------------------------------------------------------------------------------*/ -/** - * Should CPB be enabled - * - * @param[in] PlatformConfig Contains the runtime modifiable feature input data. - * @param[in] StdHeader Config Handle for library, services. - * - * @retval TRUE CPB is supported. - * @retval FALSE CPB cannot be enabled. - * - */ -BOOLEAN -STATIC -IsCpbFeatureEnabled ( - IN PLATFORM_CONFIGURATION *PlatformConfig, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - UINT32 Socket; - BOOLEAN IsEnabled; - CPB_FAMILY_SERVICES *FamilyServices; - - IsEnabled = FALSE; - - ASSERT (PlatformConfig->CpbMode < MaxCpbMode); - - if (PlatformConfig->CpbMode == CpbModeAuto) { - for (Socket = 0; Socket < GetPlatformNumberOfSockets (); Socket++) { - if (IsProcessorPresent (Socket, StdHeader)) { - GetFeatureServicesOfSocket (&CpbFamilyServiceTable, Socket, (const VOID **)&FamilyServices, StdHeader); - if (FamilyServices != NULL) { - if (FamilyServices->IsCpbSupported (FamilyServices, PlatformConfig, Socket, StdHeader)) { - IsEnabled = TRUE; - break; - } - } - } - } - } - return IsEnabled; -} - -/*---------------------------------------------------------------------------------------*/ -/** - * Enable core performance boost - * - * @param[in] EntryPoint Timepoint designator. - * @param[in] PlatformConfig Contains the runtime modifiable feature input data. - * @param[in] StdHeader Config Handle for library, services. - * - * @retval AGESA_SUCCESS Always succeeds. - * - */ -AGESA_STATUS -STATIC -InitializeCpbFeature ( - IN UINT64 EntryPoint, - IN PLATFORM_CONFIGURATION *PlatformConfig, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - UINT32 Socket; - AGESA_STATUS AgesaStatus; - AGESA_STATUS CalledStatus; - CPB_FAMILY_SERVICES *FamilyServices; - - AgesaStatus = AGESA_SUCCESS; - CalledStatus = AGESA_SUCCESS; - - IDS_HDT_CONSOLE (CPU_TRACE, " Boost is enabled\n"); - - for (Socket = 0; Socket < GetPlatformNumberOfSockets (); Socket++) { - if (IsProcessorPresent (Socket, StdHeader)) { - GetFeatureServicesOfSocket (&CpbFamilyServiceTable, Socket, (const VOID **)&FamilyServices, StdHeader); - if (FamilyServices != NULL) { - if (FamilyServices->IsCpbSupported (FamilyServices, PlatformConfig, Socket, StdHeader)) { - CalledStatus = FamilyServices->EnableCpbOnSocket (FamilyServices, PlatformConfig, EntryPoint, Socket, StdHeader); - if (CalledStatus > AgesaStatus) { - AgesaStatus = CalledStatus; - } - } - } - } - } - - return AgesaStatus; -} - - -CONST CPU_FEATURE_DESCRIPTOR ROMDATA CpuFeatureCpb = -{ - CoreBoost, - (CPU_FEAT_BEFORE_PM_INIT | CPU_FEAT_INIT_LATE_END | CPU_FEAT_S3_LATE_RESTORE_END), - IsCpbFeatureEnabled, - InitializeCpbFeature -}; diff --git a/src/vendorcode/amd/agesa/f12/Proc/CPU/Feature/cpuCpb.h b/src/vendorcode/amd/agesa/f12/Proc/CPU/Feature/cpuCpb.h deleted file mode 100644 index 2dde5d82fd..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/CPU/Feature/cpuCpb.h +++ /dev/null @@ -1,133 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * AMD AGESA CPU Core Performance Boost Functions declarations. - * - * Contains code that declares the AGESA CPU CPB related APIs - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: CPU/Feature - * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $ - * - */ -/* - ****************************************************************************** - * - * Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - ****************************************************************************** - */ - -#ifndef _CPU_CPB_H_ -#define _CPU_CPB_H_ - -/*---------------------------------------------------------------------------------------- - * M I X E D (Definitions And Macros / Typedefs, Structures, Enums) - *---------------------------------------------------------------------------------------- - */ -// Forward declaration needed for multi-structure mutual references -AGESA_FORWARD_DECLARATION (CPB_FAMILY_SERVICES); - -/*---------------------------------------------------------------------------------------- - * D E F I N I T I O N S A N D M A C R O S - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------- - * T Y P E D E F S A N D S T R U C T U R E S - *---------------------------------------------------------------------------------------- - */ - - -/*---------------------------------------------------------------------------------------*/ -/** - * Family specific call to check if CPB is supported. - * - * @param[in] CpbServices Core Performance Boost services. - * @param[in] PlatformConfig Contains the runtime modifiable feature input data. - * @param[in] Socket Zero-based socket number. - * @param[in] StdHeader Config Handle for library, services. - * - * @retval TRUE CPB is supported. - * @retval FALSE CPB is not supported. - * - */ -typedef BOOLEAN F_CPB_IS_SUPPORTED ( - IN CPB_FAMILY_SERVICES *CpbServices, - IN PLATFORM_CONFIGURATION *PlatformConfig, - IN UINT32 Socket, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -/// Reference to a Method. -typedef F_CPB_IS_SUPPORTED *PF_CPB_IS_SUPPORTED; - -/*---------------------------------------------------------------------------------------*/ -/** - * Family specific call to enable CPB. - * - * @param[in] CpbServices Core Performance Boost services. - * @param[in] PlatformConfig Contains the runtime modifiable feature input data. - * @param[in] EntryPoint Timepoint designator. - * @param[in] Socket Zero-based socket number. - * @param[in] StdHeader Config Handle for library, services. - * - * @return Family specific error value. - * - */ -typedef AGESA_STATUS F_CPB_INIT ( - IN CPB_FAMILY_SERVICES *CpbServices, - IN PLATFORM_CONFIGURATION *PlatformConfig, - IN UINT64 EntryPoint, - IN UINT32 Socket, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -/// Reference to a Method. -typedef F_CPB_INIT *PF_CPB_INIT; - -/** - * Provide the interface to the CPB Family Specific Services. - * - * Use the methods or data in this struct to adapt the feature code to a specific cpu family or model (or stepping!). - * Each supported Family must provide an implementation for all methods in this interface, even if the - * implementation is a CommonReturn(). - */ -struct _CPB_FAMILY_SERVICES { - UINT16 Revision; ///< Interface version - // Public Methods. - PF_CPB_IS_SUPPORTED IsCpbSupported; ///< Method: Family specific call to check if CPB is supported. - PF_CPB_INIT EnableCpbOnSocket; ///< Method: Family specific call to enable CPB. -}; - - -/*---------------------------------------------------------------------------------------- - * F U N C T I O N S P R O T O T Y P E - *---------------------------------------------------------------------------------------- - */ - -#endif // _CPU_CPB_H_ diff --git a/src/vendorcode/amd/agesa/f12/Proc/CPU/Feature/cpuDmi.c b/src/vendorcode/amd/agesa/f12/Proc/CPU/Feature/cpuDmi.c deleted file mode 100644 index 56612916db..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/CPU/Feature/cpuDmi.c +++ /dev/null @@ -1,798 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * AMD DMI Record Creation API, and related functions. - * - * Contains code that produce the DMI related information. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: CPU - * @e \$Revision: 49990 $ @e \$Date: 2011-03-31 13:48:41 +0800 (Thu, 31 Mar 2011) $ - * - */ -/***************************************************************************** - * - * Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - ****************************************************************************** - */ - -/*---------------------------------------------------------------------------------------- - * M O D U L E S U S E D - *---------------------------------------------------------------------------------------- - */ -#include "AGESA.h" -#include "amdlib.h" -#include "OptionDmi.h" -#include "cpuLateInit.h" -#include "cpuRegisters.h" -#include "cpuServices.h" -#include "GeneralServices.h" -#include "heapManager.h" -#include "Ids.h" -#include "cpuFamilyTranslation.h" -#include "Filecode.h" -CODE_GROUP (G3_DXE) -RDATA_GROUP (G3_DXE) - -#define FILECODE PROC_CPU_FEATURE_CPUDMI_FILECODE -/*---------------------------------------------------------------------------------------- - * D E F I N I T I O N S A N D M A C R O S - *---------------------------------------------------------------------------------------- - */ -extern OPTION_DMI_CONFIGURATION OptionDmiConfiguration; // global user config record - -/*---------------------------------------------------------------------------------------- - * T Y P E D E F S A N D S T R U C T U R E S - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------- - * P R O T O T Y P E S O F L O C A L F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ -UINT16 -STATIC -AdjustGranularity ( - IN UINT32 *CacheSizePtr - ); - -VOID -STATIC -IntToString ( - IN OUT CHAR8 *String, - IN UINT8 *Integer, - IN UINT8 SizeInByte -); - -/*---------------------------------------------------------------------------------------- - * E X P O R T E D F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ -AGESA_STATUS -GetDmiInfoStub ( - IN OUT AMD_CONFIG_PARAMS *StdHeader, - IN OUT DMI_INFO **DmiTable - ); - -AGESA_STATUS -GetDmiInfoMain ( - IN OUT AMD_CONFIG_PARAMS *StdHeader, - IN OUT DMI_INFO **DmiTable - ); - -AGESA_STATUS -ReleaseDmiBufferStub ( - IN OUT AMD_CONFIG_PARAMS *StdHeader - ); - -AGESA_STATUS -ReleaseDmiBuffer ( - IN OUT AMD_CONFIG_PARAMS *StdHeader - ); - -/*--------------------------------------------------------------------------------------- - * L O C A L F U N C T I O N S - *--------------------------------------------------------------------------------------- - */ - -/* -----------------------------------------------------------------------------*/ -/** - * - * CreateDmiRecords - * - * Description: - * This function creates DMI/SMBios records pertinent to the processor - * SMBIOS type 4, type 7, and type 40. - * - * Parameters: - * @param[in, out] *StdHeader - * @param[in, out] **DmiTable - * - * @retval AGESA_STATUS - * - */ - -AGESA_STATUS -CreateDmiRecords ( - IN OUT AMD_CONFIG_PARAMS *StdHeader, - IN OUT DMI_INFO **DmiTable - ) -{ - AGESA_TESTPOINT (TpProcCpuEntryDmi, StdHeader); - return ((*(OptionDmiConfiguration.DmiFeature)) (StdHeader, DmiTable)); -} - -/* -----------------------------------------------------------------------------*/ -/** - * GetDmiInfoStub - * - * Description: - * This is the default routine for use when the DMI option is NOT requested. - * The option install process will create and fill the transfer vector with - * the address of the proper routine (Main or Stub). The link optimizer will - * strip out of the .DLL the routine that is not used. - * - * Parameters: - * @param[in, out] *StdHeader - * @param[in, out] **DmiTable - * - * @retval AGESA_STATUS - * - */ -AGESA_STATUS -GetDmiInfoStub ( - IN OUT AMD_CONFIG_PARAMS *StdHeader, - IN OUT DMI_INFO **DmiTable - ) -{ - return AGESA_UNSUPPORTED; -} - -/* -----------------------------------------------------------------------------*/ -/** - * GetDmiInfoMain - * - * Description: - * This is the common routine for getting Dmi type4 and type7 CPU related information. - * - * Parameters: - * @param[in, out] *StdHeader - * @param[in, out] **DmiTable - * - * @retval AGESA_STATUS - * - */ -AGESA_STATUS -GetDmiInfoMain ( - IN OUT AMD_CONFIG_PARAMS *StdHeader, - IN OUT DMI_INFO **DmiTable - ) -{ - UINT8 Socket; - UINT8 Channel; - UINT8 Dimm; - UINT16 Index; - UINT16 DimmIndex; - UINT16 NumberOfDimm; - UINT32 MaxCapacity; - UINT64 MsrData; - UINT64 LocalMsrRegister; - BOOLEAN FamilyNotFound; - AGESA_STATUS Flag; - AGESA_STATUS CalledStatus; - AP_EXE_PARAMS ApParams; - MEM_DMI_INFO *MemInfo; - DMI_T17_MEMORY_TYPE MemType; - DMI_INFO *DmiBufferPtr; - ALLOCATE_HEAP_PARAMS AllocateHeapParams; - LOCATE_HEAP_PTR LocateHeapParams; - CPU_LOGICAL_ID LogicalId; - PROC_FAMILY_TABLE *ProcData; - CPU_GET_MEM_INFO CpuGetMemInfo; - - MsrData = 0; - Flag = AGESA_SUCCESS; - ProcData = NULL; - MemInfo = NULL; - DmiBufferPtr = *DmiTable; - FamilyNotFound = TRUE; - - GetLogicalIdOfCurrentCore (&LogicalId, StdHeader); - for (Index = 0; Index < OptionDmiConfiguration.NumEntries; Index++) { - ProcData = (PROC_FAMILY_TABLE *) ((*OptionDmiConfiguration.FamilyList)[Index]); - if ((ProcData->ProcessorFamily & LogicalId.Family) != 0) { - FamilyNotFound = FALSE; - break; - } - } - - if (FamilyNotFound) { - return AGESA_ERROR; - } - - if (DmiBufferPtr == NULL) { - // - // Allocate a buffer by heap function - // - AllocateHeapParams.BufferHandle = AMD_DMI_INFO_BUFFER_HANDLE; - AllocateHeapParams.RequestedBufferSize = sizeof (DMI_INFO); - AllocateHeapParams.Persist = HEAP_SYSTEM_MEM; - - if (HeapAllocateBuffer (&AllocateHeapParams, StdHeader) != AGESA_SUCCESS) { - return AGESA_ERROR; - } - - DmiBufferPtr = (DMI_INFO *) AllocateHeapParams.BufferPtr; - *DmiTable = DmiBufferPtr; - } - - IDS_HDT_CONSOLE (CPU_TRACE, " DMI is enabled\n"); - - // Fill with 0x00 - LibAmdMemFill (DmiBufferPtr, 0x00, sizeof (DMI_INFO), StdHeader); - - // - // Get CPU information - // - - // Run GetType4Type7Info on all core0s. - ApParams.StdHeader = *StdHeader; - ApParams.FunctionNumber = AP_LATE_TASK_GET_TYPE4_TYPE7; - ApParams.RelatedDataBlock = (VOID *) DmiBufferPtr; - ApParams.RelatedBlockLength = sizeof (DMI_INFO); - CalledStatus = RunLateApTaskOnAllCore0s (&ApParams, StdHeader); - if (CalledStatus > Flag) { - Flag = CalledStatus; - } - CalledStatus = GetType4Type7Info (&ApParams); - if (CalledStatus > Flag) { - Flag = CalledStatus; - } - - //------------------------------ - // T Y P E 16 17 19 20 - //------------------------------ - - LocateHeapParams.BufferHandle = AMD_DMI_MEM_DEV_INFO_HANDLE; - if (HeapLocateBuffer (&LocateHeapParams, StdHeader) != AGESA_SUCCESS) { - if (Flag < AGESA_ERROR) { - Flag = AGESA_ERROR; - } - } else { - NumberOfDimm = *((UINT16 *) (LocateHeapParams.BufferPtr)); - MemType = *((DMI_T17_MEMORY_TYPE *) ((UINT8 *) (LocateHeapParams.BufferPtr) + 6)); - MemInfo = (MEM_DMI_INFO *) ((UINT8 *) (LocateHeapParams.BufferPtr) + 6 + sizeof (DMI_T17_MEMORY_TYPE)); - // TYPE 16 - DmiBufferPtr->T16.Location = 0x03; - DmiBufferPtr->T16.Use = 0x03; - - // Gather memory information - ProcData->DmiGetMemInfo (&CpuGetMemInfo, StdHeader); - - if (CpuGetMemInfo.EccCapable) { - DmiBufferPtr->T16.MemoryErrorCorrection = Dmi16MultiBitEcc; - } else { - DmiBufferPtr->T16.MemoryErrorCorrection = Dmi16NoneErrCorrection; - } - - MaxCapacity = *((UINT32 *) ((UINT8 *) (LocateHeapParams.BufferPtr) + 2)); - DmiBufferPtr->T16.MaximumCapacity = MaxCapacity << 10; - - DmiBufferPtr->T16.NumberOfMemoryDevices = NumberOfDimm; - - // TYPE 17 - for (DimmIndex = 0; DimmIndex < NumberOfDimm; DimmIndex++) { - Socket = (MemInfo + DimmIndex)->Socket; - Channel = (MemInfo + DimmIndex)->Channel; - Dimm = (MemInfo + DimmIndex)->Dimm; - - DmiBufferPtr->T17[Socket][Channel][Dimm].TotalWidth = (MemInfo + DimmIndex)->TotalWidth; - DmiBufferPtr->T17[Socket][Channel][Dimm].DataWidth = (MemInfo + DimmIndex)->DataWidth; - DmiBufferPtr->T17[Socket][Channel][Dimm].MemorySize = (MemInfo + DimmIndex)->MemorySize; - DmiBufferPtr->T17[Socket][Channel][Dimm].FormFactor = (MemInfo + DimmIndex)->FormFactor; - DmiBufferPtr->T17[Socket][Channel][Dimm].DeviceSet = 0; - - DmiBufferPtr->T17[Socket][Channel][Dimm].DeviceLocator[0] = 'D'; - DmiBufferPtr->T17[Socket][Channel][Dimm].DeviceLocator[1] = 'I'; - DmiBufferPtr->T17[Socket][Channel][Dimm].DeviceLocator[2] = 'M'; - DmiBufferPtr->T17[Socket][Channel][Dimm].DeviceLocator[3] = 'M'; - DmiBufferPtr->T17[Socket][Channel][Dimm].DeviceLocator[4] = ' '; - DmiBufferPtr->T17[Socket][Channel][Dimm].DeviceLocator[5] = Dimm + 0x30; - DmiBufferPtr->T17[Socket][Channel][Dimm].DeviceLocator[6] = '\0'; - DmiBufferPtr->T17[Socket][Channel][Dimm].DeviceLocator[7] = '\0'; - - DmiBufferPtr->T17[Socket][Channel][Dimm].BankLocator[0] = 'C'; - DmiBufferPtr->T17[Socket][Channel][Dimm].BankLocator[1] = 'H'; - DmiBufferPtr->T17[Socket][Channel][Dimm].BankLocator[2] = 'A'; - DmiBufferPtr->T17[Socket][Channel][Dimm].BankLocator[3] = 'N'; - DmiBufferPtr->T17[Socket][Channel][Dimm].BankLocator[4] = 'N'; - DmiBufferPtr->T17[Socket][Channel][Dimm].BankLocator[5] = 'E'; - DmiBufferPtr->T17[Socket][Channel][Dimm].BankLocator[6] = 'L'; - DmiBufferPtr->T17[Socket][Channel][Dimm].BankLocator[7] = ' '; - DmiBufferPtr->T17[Socket][Channel][Dimm].BankLocator[8] = Channel + 0x41; - DmiBufferPtr->T17[Socket][Channel][Dimm].BankLocator[9] = '\0'; - - DmiBufferPtr->T17[Socket][Channel][Dimm].MemoryType = MemType; - DmiBufferPtr->T17[Socket][Channel][Dimm].TypeDetail.Synchronous = 1; - DmiBufferPtr->T17[Socket][Channel][Dimm].Speed = (MemInfo + DimmIndex)->Speed; - - DmiBufferPtr->T17[Socket][Channel][Dimm].ManufacturerIdCode = (MemInfo + DimmIndex)->ManufacturerIdCode; - - IntToString (DmiBufferPtr->T17[Socket][Channel][Dimm].SerialNumber, (MemInfo + DimmIndex)->SerialNumber, (sizeof DmiBufferPtr->T17[Socket][Channel][Dimm].SerialNumber - 1) / 2); - - LibAmdMemCopy (&DmiBufferPtr->T17[Socket][Channel][Dimm].PartNumber, &(MemInfo + DimmIndex)->PartNumber, sizeof (DmiBufferPtr->T17[Socket][Channel][Dimm].PartNumber), StdHeader); - DmiBufferPtr->T17[Socket][Channel][Dimm].PartNumber[18] = 0; - - DmiBufferPtr->T17[Socket][Channel][Dimm].Attributes = (MemInfo + DimmIndex)->Attributes; - DmiBufferPtr->T17[Socket][Channel][Dimm].ExtSize = (MemInfo + DimmIndex)->ExtSize; - DmiBufferPtr->T17[Socket][Channel][Dimm].ConfigSpeed = (MemInfo + DimmIndex)->ConfigSpeed; - - //TYPE 20 - DmiBufferPtr->T20[Socket][Channel][Dimm].StartingAddr = (MemInfo + DimmIndex)->StartingAddr; - DmiBufferPtr->T20[Socket][Channel][Dimm].EndingAddr = (MemInfo + DimmIndex)->EndingAddr; - // Partition Row Position - 2 for single channel memory - // 0 for dual channel memory - DmiBufferPtr->T20[Socket][Channel][Dimm].PartitionRowPosition = CpuGetMemInfo.PartitionRowPosition; - DmiBufferPtr->T20[Socket][Channel][Dimm].InterleavePosition = 0xFF; - DmiBufferPtr->T20[Socket][Channel][Dimm].InterleavedDataDepth = 0xFF; - } - - // TYPE 19 - DmiBufferPtr->T19.StartingAddr = 0; - - LibAmdMsrRead (TOP_MEM2, &LocalMsrRegister, StdHeader); - if (LocalMsrRegister == 0) { - LibAmdMsrRead (TOP_MEM, &LocalMsrRegister, StdHeader); - DmiBufferPtr->T19.EndingAddr = (UINT32) (LocalMsrRegister >> 10); - } else if (LocalMsrRegister != 0) { - DmiBufferPtr->T19.EndingAddr = (UINT32) (LocalMsrRegister >> 10); - } - - DmiBufferPtr->T19.PartitionWidth = 0xFF; - } - return (Flag); -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * GetType4Type7Info - * - * Description: - * This routine should be run on core 0 of every socket. It creates DMI type 4 and type 7 tables. - * - * Parameters: - * @param[in] ApExeParams Handle to config for library and services. - * - * @retval AGESA_STATUS - * - * Processing: - * - */ -AGESA_STATUS -GetType4Type7Info ( - IN AP_EXE_PARAMS *ApExeParams - ) -{ - UINT8 ByteIndexInUint64; - UINT16 Index; - UINT32 SocketNum; - UINT32 CacheSize; - UINT32 IgnoredModule; - UINT32 IgnoredCore; - UINT64 MsrData; - DMI_INFO *DmiBufferPtr; - AGESA_STATUS IgnoredSts; - AGESA_STATUS Flag; - BOOLEAN FamilyNotFound; - CPUID_DATA CpuId; - CPU_TYPE_INFO CpuInfo; - PROC_FAMILY_TABLE *ProcData; - CPU_LOGICAL_ID LogicalID; - - Flag = AGESA_SUCCESS; - DmiBufferPtr = (DMI_INFO *) ApExeParams->RelatedDataBlock; - GetLogicalIdOfCurrentCore (&LogicalID, &ApExeParams->StdHeader); - - ProcData = NULL; - FamilyNotFound = TRUE; - for (Index = 0; Index < OptionDmiConfiguration.NumEntries; Index++) { - ProcData = (PROC_FAMILY_TABLE *) ((*OptionDmiConfiguration.FamilyList)[Index]); - if ((ProcData->ProcessorFamily & LogicalID.Family) != 0) { - FamilyNotFound = FALSE; - break; - } - } - - if (FamilyNotFound) { - return AGESA_ERROR; - } - - ProcData->DmiGetCpuInfo (&CpuInfo, &ApExeParams->StdHeader); - - // ------------------------------ - // T Y P E 4 - // ------------------------------ - - IdentifyCore (&ApExeParams->StdHeader, &SocketNum, &IgnoredModule, &IgnoredCore, &IgnoredSts); - - // Type 4 Offset 0x05, Processor Type - DmiBufferPtr->T4[SocketNum].T4ProcType = CENTRAL_PROCESSOR; - - // Type 4 Offset 0x06, Processor Family - ProcData->DmiGetT4ProcFamily (&DmiBufferPtr->T4[SocketNum].T4ProcFamily, ProcData, &CpuInfo, &ApExeParams->StdHeader); - - if (DmiBufferPtr->T4[SocketNum].T4ProcFamily == P_UPGRADE_UNKNOWN) { - Flag = AGESA_ERROR; - } - - // Type4 Offset 0x08, Processor ID - LibAmdCpuidRead (AMD_CPUID_APICID_LPC_BID, &CpuId, &ApExeParams->StdHeader); - DmiBufferPtr->T4[SocketNum].T4ProcId.ProcIdLsd = CpuId.EAX_Reg; - DmiBufferPtr->T4[SocketNum].T4ProcId.ProcIdMsd = CpuId.EDX_Reg; - - // Type4 Offset 0x11, Voltage - DmiBufferPtr->T4[SocketNum].T4Voltage = ProcData->DmiGetVoltage (&ApExeParams->StdHeader); - - // Type4 Offset 0x12, External Clock - DmiBufferPtr->T4[SocketNum].T4ExternalClock = ProcData->DmiGetExtClock (&ApExeParams->StdHeader); - - // Type4 Offset 0x14, Max Speed - DmiBufferPtr->T4[SocketNum].T4MaxSpeed = ProcData->DmiGetMaxSpeed (&ApExeParams->StdHeader); - - // Type4 Offset 0x16, Current Speed - DmiBufferPtr->T4[SocketNum].T4CurrentSpeed = DmiBufferPtr->T4[SocketNum].T4MaxSpeed; - - // Type4 Offset 0x18, Status - DmiBufferPtr->T4[SocketNum].T4Status = SOCKET_POPULATED | CPU_STATUS_ENABLED; - - // Type4 Offset 0x19, Processor Upgrade - DmiBufferPtr->T4[SocketNum].T4ProcUpgrade = CpuInfo.ProcUpgrade; - - // Type4 Offset 0x23, 0x24 and 0x25, Core Count, Core Enabled and Thread Count - DmiBufferPtr->T4[SocketNum].T4CoreCount = CpuInfo.TotalCoreNumber + 1; - DmiBufferPtr->T4[SocketNum].T4CoreEnabled = CpuInfo.EnabledCoreNumber + 1; - DmiBufferPtr->T4[SocketNum].T4ThreadCount = CpuInfo.EnabledCoreNumber + 1; - - // Type4 Offset 0x26, Processor Characteristics - DmiBufferPtr->T4[SocketNum].T4ProcCharacteristics = P_CHARACTERISTICS; - - // Type4 Offset 0x28, Processor Family 2 - DmiBufferPtr->T4[SocketNum].T4ProcFamily2 = DmiBufferPtr->T4[SocketNum].T4ProcFamily; - - // Type4 ProcVersion - for (Index = 0; Index <= 5; Index++) { - LibAmdMsrRead ((MSR_CPUID_NAME_STRING0 + Index), &MsrData, &ApExeParams->StdHeader); - for (ByteIndexInUint64 = 0; ByteIndexInUint64 <= 7; ByteIndexInUint64++) { - DmiBufferPtr->T4[SocketNum].T4ProcVersion[Index * 8 + ByteIndexInUint64] = (UINT8) (MsrData >> (8 * ByteIndexInUint64)); - } - } - - //------------------------------ - // T Y P E 7 - //------------------------------ - - // Type7 Offset 0x05, Cache Configuration - DmiBufferPtr->T7L1[SocketNum].T7CacheCfg = CACHE_CFG_L1; - DmiBufferPtr->T7L2[SocketNum].T7CacheCfg = CACHE_CFG_L2; - DmiBufferPtr->T7L3[SocketNum].T7CacheCfg = CACHE_CFG_L3; - - // Type7 Offset 0x07 and 09, Maximum Cache Size and Installed Size - LibAmdCpuidRead (AMD_CPUID_TLB_L1Cache, &CpuId, &ApExeParams->StdHeader); - - // Maximum L1 cache size - CacheSize = (UINT32) (((UINT8) (CpuId.ECX_Reg >> 24) + (UINT8) (CpuId.EDX_Reg >> 24)) * (CpuInfo.EnabledCoreNumber + 1)); - DmiBufferPtr->T7L1[SocketNum].T7MaxCacheSize = AdjustGranularity (&CacheSize); - - // Installed L1 cache size - DmiBufferPtr->T7L1[SocketNum].T7InstallSize = DmiBufferPtr->T7L1[SocketNum].T7MaxCacheSize; - - // Maximum L2 cache size - LibAmdCpuidRead (AMD_CPUID_L2L3Cache_L2TLB, &CpuId, &ApExeParams->StdHeader); - CacheSize = (UINT32) ((UINT16) (CpuId.ECX_Reg >> 16) * (CpuInfo.EnabledCoreNumber + 1)); - DmiBufferPtr->T7L2[SocketNum].T7MaxCacheSize = AdjustGranularity (&CacheSize); - - // Installed L2 cache size - DmiBufferPtr->T7L2[SocketNum].T7InstallSize = DmiBufferPtr->T7L2[SocketNum].T7MaxCacheSize; - - // Maximum L3 cache size - CacheSize = ((CpuId.EDX_Reg >> 18) & 0x3FFF) * 512; - DmiBufferPtr->T7L3[SocketNum].T7MaxCacheSize = AdjustGranularity (&CacheSize); - - // Installed L3 cache size - DmiBufferPtr->T7L3[SocketNum].T7InstallSize = DmiBufferPtr->T7L3[SocketNum].T7MaxCacheSize; - - // Type7 Offset 0x0B and 0D, Supported SRAM Type and Current SRAM Type - DmiBufferPtr->T7L1[SocketNum].T7SupportedSramType = SRAM_TYPE; - DmiBufferPtr->T7L1[SocketNum].T7CurrentSramType = SRAM_TYPE; - DmiBufferPtr->T7L2[SocketNum].T7SupportedSramType = SRAM_TYPE; - DmiBufferPtr->T7L2[SocketNum].T7CurrentSramType = SRAM_TYPE; - DmiBufferPtr->T7L3[SocketNum].T7SupportedSramType = SRAM_TYPE; - DmiBufferPtr->T7L3[SocketNum].T7CurrentSramType = SRAM_TYPE; - - // Type7 Offset 0x0F, Cache Speed - DmiBufferPtr->T7L1[SocketNum].T7CacheSpeed = 1; - DmiBufferPtr->T7L2[SocketNum].T7CacheSpeed = 1; - DmiBufferPtr->T7L3[SocketNum].T7CacheSpeed = 1; - - // Type7 Offset 0x10, Error Correction Type - DmiBufferPtr->T7L1[SocketNum].T7ErrorCorrectionType = ERR_CORRECT_TYPE; - DmiBufferPtr->T7L2[SocketNum].T7ErrorCorrectionType = ERR_CORRECT_TYPE; - DmiBufferPtr->T7L3[SocketNum].T7ErrorCorrectionType = ERR_CORRECT_TYPE; - - // Type7 Offset 0x11, System Cache Type - DmiBufferPtr->T7L1[SocketNum].T7SystemCacheType = CACHE_TYPE; - DmiBufferPtr->T7L2[SocketNum].T7SystemCacheType = CACHE_TYPE; - DmiBufferPtr->T7L3[SocketNum].T7SystemCacheType = CACHE_TYPE; - - // Type7 Offset 0x12, Associativity - DmiBufferPtr->T7L1[SocketNum].T7Associativity = ASSOCIATIVE_2_WAY; - DmiBufferPtr->T7L2[SocketNum].T7Associativity = ASSOCIATIVE_16_WAY; - if (((CpuId.EDX_Reg >> 12) & 0x0F) == ASSOCIATIVE_16_WAY) { - DmiBufferPtr->T7L3[SocketNum].T7Associativity = ASSOCIATIVE_16_WAY; - } else { - DmiBufferPtr->T7L3[SocketNum].T7Associativity = ASSOCIATIVE_OTHER; - } - return (Flag); -} - -/* -----------------------------------------------------------------------------*/ -/** - * DmiGetT4ProcFamilyFromBrandId - * - * Description: - * This is the common routine for getting Type 4 processor family information from brand ID - * - * Parameters: - * @param[in, out] *T4ProcFamily Pointer to type 4 processor family information - * @param[in] *CpuDmiProcFamilyTable Pointer to DMI family special service - * @param[in] *CpuInfo Pointer to CPU_TYPE_INFO struct - * @param[in, out] *StdHeader Standard Head Pointer - * - * @retval AGESA_STATUS - * - */ -VOID -DmiGetT4ProcFamilyFromBrandId ( - IN OUT UINT8 *T4ProcFamily, - IN PROC_FAMILY_TABLE *CpuDmiProcFamilyTable, - IN CPU_TYPE_INFO *CpuInfo, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - UINT16 Index; - - for (Index = 0; Index < CpuDmiProcFamilyTable->LenBrandList; Index++) { - if ((CpuDmiProcFamilyTable->DmiBrandList[Index].PackageType == 'x' || CpuDmiProcFamilyTable->DmiBrandList[Index].PackageType == CpuInfo->PackageType) && - (CpuDmiProcFamilyTable->DmiBrandList[Index].PgOfBrandId == 'x' || CpuDmiProcFamilyTable->DmiBrandList[Index].PgOfBrandId == CpuInfo->BrandId.Pg) && - (CpuDmiProcFamilyTable->DmiBrandList[Index].NumberOfCores == 'x' || CpuDmiProcFamilyTable->DmiBrandList[Index].NumberOfCores == CpuInfo->TotalCoreNumber) && - (CpuDmiProcFamilyTable->DmiBrandList[Index].String1ofBrandId == 'x' || CpuDmiProcFamilyTable->DmiBrandList[Index].String1ofBrandId == CpuInfo->BrandId.String1)) { - *T4ProcFamily = CpuDmiProcFamilyTable->DmiBrandList[Index].ValueSetToDmiTable; - break; - } - } -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * GetNameString - * - * Description: - * Get name string from MSR_C001_00[35:30] - * - * Parameters: - * @param[in, out] *String Pointer to name string - * @param[in, out] *StdHeader - * - */ -VOID -GetNameString ( - IN OUT CHAR8 *String, - IN OUT AMD_CONFIG_PARAMS *StdHeader - ) -{ - UINT8 i; - UINT8 StringIndex; - UINT8 MsrIndex; - UINT64 MsrData; - - StringIndex = 0; - for (MsrIndex = 0; MsrIndex <= 5; MsrIndex++) { - LibAmdMsrRead ((MSR_CPUID_NAME_STRING0 + MsrIndex), &MsrData, StdHeader); - for (i = 0; i < 8; i++) { - String[StringIndex] = (CHAR8) (MsrData >> (8 * i)); - StringIndex++; - } - } - String[StringIndex] = '\0'; -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * IsSourceStrContainTargetStr - * - * Description: - * check if source string contains target string. - * - * Parameters: - * @param[in, out] *SourceStr Pointer to source CHAR array - * @param[in, out] *TargetStr Pointer to target CHAR array - * @param[in, out] *StdHeader - * - * @retval TRUE Target string is contained in the source string - * @retval FALSE Target string is not contained in the source string - */ -BOOLEAN -IsSourceStrContainTargetStr ( - IN OUT CHAR8 *SourceStr, - IN OUT CONST CHAR8 *TargetStr, - IN OUT AMD_CONFIG_PARAMS *StdHeader - ) -{ - BOOLEAN IsContained; - UINT32 SourceStrIndex; - UINT32 TargetStrIndex; - - IsContained = FALSE; - if ((TargetStr != NULL) && (SourceStr != NULL)) { - for (SourceStrIndex = 0; SourceStr[SourceStrIndex] != '\0'; SourceStrIndex++) { - TargetStrIndex = 0; - // Compare TrgString with SrcString from frist charactor to the '\0' - while ((TargetStr[TargetStrIndex] != '\0') && (TargetStr[TargetStrIndex] == SourceStr[SourceStrIndex + TargetStrIndex])) { - TargetStrIndex++; - } - if ((TargetStr[TargetStrIndex] == '\0') && (TargetStrIndex != 0)) { - IsContained = TRUE; - break; - } - } - } - return IsContained; -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * AdjustGranularity - * - * Description: - * If cache size is greater than or equal to 32M, then set granularity - * to 64K. otherwise, set granularity to 1K - * - * Parameters: - * @param[in] *CacheSizePtr - * - * @retval CacheSize - * - * Processing: - * - */ -UINT16 -STATIC -AdjustGranularity ( - IN UINT32 *CacheSizePtr - ) -{ - UINT16 CacheSize; - - if (*CacheSizePtr >= 0x8000) { - CacheSize = (UINT16) (*CacheSizePtr / 64); - CacheSize |= 0x8000; - } else { - CacheSize = (UINT16) *CacheSizePtr; - } - - return (CacheSize); -} - -/* -----------------------------------------------------------------------------*/ -/** - * ReleaseDmiBufferStub - * - * Description: - * This is the default routine for use when the DMI option is NOT requested. - * - * Parameters: - * @param[in, out] *StdHeader - * - * @retval AGESA_STATUS - * - */ -AGESA_STATUS -ReleaseDmiBufferStub ( - IN OUT AMD_CONFIG_PARAMS *StdHeader - ) -{ - return AGESA_UNSUPPORTED; -} - -/* -----------------------------------------------------------------------------*/ -/** - * ReleaseDmiBuffer - * - * Description: - * Deallocate DMI buffer - * - * Parameters: - * @param[in, out] *StdHeader - * - * @retval AGESA_STATUS - * - */ -AGESA_STATUS -ReleaseDmiBuffer ( - IN OUT AMD_CONFIG_PARAMS *StdHeader - ) -{ - HeapDeallocateBuffer ((UINT32) AMD_DMI_MEM_DEV_INFO_HANDLE, StdHeader); - - return AGESA_SUCCESS; -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * IntToString - * - * Description: - * Translate UINT array to CHAR array. - * - * Parameters: - * @param[in, out] *String Pointer to CHAR array - * @param[in] *Integer Pointer to UINT array - * @param[in] SizeInByte The size of UINT array - * - * Processing: - * - */ -VOID -STATIC -IntToString ( - IN OUT CHAR8 *String, - IN UINT8 *Integer, - IN UINT8 SizeInByte - ) -{ - UINT8 Index; - - for (Index = 0; Index < SizeInByte; Index++) { - *(String + Index * 2) = (*(Integer + Index) >> 4) & 0x0F; - *(String + Index * 2 + 1) = *(Integer + Index) & 0x0F; - } - for (Index = 0; Index < (SizeInByte * 2); Index++) { - if (*(String + Index) >= 0x0A) { - *(String + Index) += 0x37; - } else { - *(String + Index) += 0x30; - } - } - *(String + SizeInByte * 2) = 0x0; -} - diff --git a/src/vendorcode/amd/agesa/f12/Proc/CPU/Feature/cpuFeatureLeveling.c b/src/vendorcode/amd/agesa/f12/Proc/CPU/Feature/cpuFeatureLeveling.c deleted file mode 100644 index 47afc5d245..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/CPU/Feature/cpuFeatureLeveling.c +++ /dev/null @@ -1,265 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * AMD CPU Feature Leveling Function. - * - * Contains code to Level the Feature in a multi-socket system - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: CPU - * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $ - * - */ -/* - ****************************************************************************** - * - * Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - ****************************************************************************** - *---------------------------------------------------------------------------- - */ - - -/* - *---------------------------------------------------------------------------- - * MODULES USED - * - *---------------------------------------------------------------------------- - */ -#include "AGESA.h" -#include "amdlib.h" -#include "cpuRegisters.h" -#include "GeneralServices.h" -#include "cpuServices.h" -#include "cpuPostInit.h" -#include "cpuApicUtilities.h" -#include "cpuFamilyTranslation.h" -#include "Filecode.h" -CODE_GROUP (G1_PEICC) -RDATA_GROUP (G1_PEICC) - -#define FILECODE PROC_CPU_FEATURE_CPUFEATURELEVELING_FILECODE -/*---------------------------------------------------------------------------- - * DEFINITIONS AND MACROS - * - *---------------------------------------------------------------------------- - */ - - -/*---------------------------------------------------------------------------- - * TYPEDEFS AND STRUCTURES - * - *---------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------- - * E X P O R T E D F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------- - * PROTOTYPES OF LOCAL FUNCTIONS - * - *---------------------------------------------------------------------------- - */ -VOID -STATIC -SaveFeatures ( - IN OUT VOID *cpuFeatureListPtr, - IN OUT AMD_CONFIG_PARAMS *StdHeader - ); - -VOID -STATIC -WriteFeatures ( - IN OUT VOID *cpuFeatureListPtr, - IN OUT AMD_CONFIG_PARAMS *StdHeader - ); - -VOID -STATIC -GetGlobalCpuFeatureListAddress ( - OUT UINT64 **Address, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -/*---------------------------------------------------------------------------------------- - * P U B L I C F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ - -/* -----------------------------------------------------------------------------*/ -/** - * - * FeatureLeveling - * - * CPU feature leveling. Set least common features set of all CPUs - * - * @param[in,out] StdHeader - Pointer to AMD_CONFIG_PARAMS struct. - * - */ -VOID -FeatureLeveling ( - IN OUT AMD_CONFIG_PARAMS *StdHeader - ) -{ - UINT32 BscSocket; - UINT32 Ignored; - UINT32 BscCoreNum; - UINT32 Socket; - UINT32 Core; - UINT32 NumberOfSockets; - UINT32 NumberOfCores; - BOOLEAN *FirstTime; - BOOLEAN *NeedLeveling; - AGESA_STATUS IgnoredSts; - CPU_FEATURES_LIST *globalCpuFeatureList; - AP_TASK TaskPtr; - - ASSERT (IsBsp (StdHeader, &IgnoredSts)); - - GetGlobalCpuFeatureListAddress ((UINT64 **) &globalCpuFeatureList, StdHeader); - FirstTime = (BOOLEAN *) ((UINT8 *) globalCpuFeatureList + sizeof (CPU_FEATURES_LIST)); - NeedLeveling = (BOOLEAN *) ((UINT8 *) globalCpuFeatureList + sizeof (CPU_FEATURES_LIST) + sizeof (BOOLEAN)); - - *FirstTime = TRUE; - *NeedLeveling = FALSE; - - LibAmdMemFill (globalCpuFeatureList, 0xFF, sizeof (CPU_FEATURES_LIST), StdHeader); - IdentifyCore (StdHeader, &BscSocket, &Ignored, &BscCoreNum, &IgnoredSts); - NumberOfSockets = GetPlatformNumberOfSockets (); - - TaskPtr.FuncAddress.PfApTaskI = SaveFeatures; - TaskPtr.DataTransfer.DataSizeInDwords = SIZE_IN_DWORDS (CPU_FEATURES_LIST); - TaskPtr.ExeFlags = WAIT_FOR_CORE; - TaskPtr.DataTransfer.DataPtr = globalCpuFeatureList; - TaskPtr.DataTransfer.DataTransferFlags = DATA_IN_MEMORY; - - for (Socket = 0; Socket < NumberOfSockets; Socket++) { - if (IsProcessorPresent (Socket, StdHeader)) { - if (Socket != BscSocket) { - ApUtilRunCodeOnSocketCore ((UINT8)Socket, 0, &TaskPtr, StdHeader); - } - } - } - ApUtilTaskOnExecutingCore (&TaskPtr, StdHeader, NULL); - - if (*NeedLeveling) { - TaskPtr.FuncAddress.PfApTaskI = WriteFeatures; - for (Socket = 0; Socket < NumberOfSockets; Socket++) { - if (GetActiveCoresInGivenSocket (Socket, &NumberOfCores, StdHeader)) { - for (Core = 0; Core < NumberOfCores; Core++) { - if ((Socket != BscSocket) || (Core != BscCoreNum)) { - ApUtilRunCodeOnSocketCore ((UINT8)Socket, (UINT8)Core, &TaskPtr, StdHeader); - } - } - } - } - ApUtilTaskOnExecutingCore (&TaskPtr, StdHeader, NULL); - } -} - -/*---------------------------------------------------------------------------------------- - * L O C A L F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ - -/* -----------------------------------------------------------------------------*/ -/** - * - * SaveFeatures - * - * save least common features set of all CPUs - * - * @param[in,out] cpuFeatureListPtr - Pointer to CPU Feature List. - * @param[in,out] StdHeader - Pointer to AMD_CONFIG_PARAMS struct. - * - */ -VOID -STATIC -SaveFeatures ( - IN OUT VOID *cpuFeatureListPtr, - IN OUT AMD_CONFIG_PARAMS *StdHeader - ) -{ - CPU_SPECIFIC_SERVICES *FamilySpecificServices; - FamilySpecificServices = NULL; - - GetCpuServicesOfCurrentCore ((const CPU_SPECIFIC_SERVICES **)&FamilySpecificServices, StdHeader); - FamilySpecificServices->SaveFeatures (FamilySpecificServices, cpuFeatureListPtr, StdHeader); -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * WriteFeatures - * - * Write out least common features set of all CPUs - * - * @param[in,out] cpuFeatureListPtr - Pointer to CPU Feature List. - * @param[in,out] StdHeader - Pointer to AMD_CONFIG_PARAMS struct. - * - */ -VOID -STATIC -WriteFeatures ( - IN OUT VOID *cpuFeatureListPtr, - IN OUT AMD_CONFIG_PARAMS *StdHeader - ) -{ - CPU_SPECIFIC_SERVICES *FamilySpecificServices; - FamilySpecificServices = NULL; - - GetCpuServicesOfCurrentCore ((const CPU_SPECIFIC_SERVICES **)&FamilySpecificServices, StdHeader); - FamilySpecificServices->WriteFeatures (FamilySpecificServices, cpuFeatureListPtr, StdHeader); -} - -/*---------------------------------------------------------------------------------------*/ -/** - * - * GetGlobalCpuFeatureListAddress - * - * Determines the address in system DRAM that should be used for CPU feature leveling. - * - * @param[out] Address Address to utilize - * @param[in] StdHeader Config handle for library and services - * - * - */ -VOID -STATIC -GetGlobalCpuFeatureListAddress ( - OUT UINT64 **Address, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - UINT64 *AddressValue; - - AddressValue = (UINT64 *)GLOBAL_CPU_FEATURE_LIST_TEMP_ADDR; - - *Address = AddressValue; -} diff --git a/src/vendorcode/amd/agesa/f12/Proc/CPU/Feature/cpuFeatures.c b/src/vendorcode/amd/agesa/f12/Proc/CPU/Feature/cpuFeatures.c deleted file mode 100644 index 7f80562011..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/CPU/Feature/cpuFeatures.c +++ /dev/null @@ -1,196 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * Implement general feature dispatcher. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: CPU - * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $ - * - */ -/* - ****************************************************************************** - * - * Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - ****************************************************************************** - */ - -/*---------------------------------------------------------------------------------------- - * M O D U L E S U S E D - *---------------------------------------------------------------------------------------- - */ -#include "AGESA.h" -#include "Ids.h" -#include "GeneralServices.h" -#include "cpuFeatures.h" -#include "cpuFamilyTranslation.h" -#include "Filecode.h" -CODE_GROUP (G1_PEICC) -RDATA_GROUP (G1_PEICC) -#define FILECODE PROC_CPU_FEATURE_CPUFEATURES_FILECODE -/*---------------------------------------------------------------------------------------- - * D E F I N I T I O N S A N D M A C R O S - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------- - * T Y P E D E F S A N D S T R U C T U R E S - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------- - * P R O T O T Y P E S O F L O C A L F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------- - * E X P O R T E D F U N C T I O N S - External General Services API - *---------------------------------------------------------------------------------------- - */ -extern CONST CPU_FEATURE_DESCRIPTOR* ROMDATA SupportedCpuFeatureList[]; - -/** - * Determines if a specific feature is or will be enabled. - * - * This code traverses the feature list until a match is - * found, then invokes the 'IsEnabled' function of the - * feature. - * - * @param[in] Feature Indicates the desired feature. - * @param[in] PlatformConfig Contains the runtime modifiable feature input data. - * @param[in] StdHeader Standard AMD configuration parameters. - * - * @retval TRUE Feature is or will be enabled - * @retval FALSE Feature is not enabled - */ -BOOLEAN -IsFeatureEnabled ( - IN DISPATCHABLE_CPU_FEATURES Feature, - IN PLATFORM_CONFIGURATION *PlatformConfig, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - UINTN i; - - ASSERT (Feature < MaxCpuFeature); - - for (i = 0; SupportedCpuFeatureList[i] != NULL; i++) { - if (SupportedCpuFeatureList[i]->Feature == Feature) { - return (SupportedCpuFeatureList[i]->IsEnabled (PlatformConfig, StdHeader)); - } - } - return FALSE; -} - -/** - * Dispatches all features needing to perform some initialization at - * this time point. - * - * This routine searches the feature table for features needing to - * run at this time point, and invokes them. - * - * @param[in] EntryPoint Timepoint designator - * @param[in] PlatformConfig Contains the runtime modifiable feature input data. - * @param[in] StdHeader Standard AMD configuration parameters. - * - * @return The most severe status of any called service. - */ -AGESA_STATUS -DispatchCpuFeatures ( - IN UINT64 EntryPoint, - IN PLATFORM_CONFIGURATION *PlatformConfig, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - UINTN i; - AGESA_STATUS AgesaStatus; - AGESA_STATUS CalledStatus; - AGESA_STATUS IgnoredStatus; - - AgesaStatus = AGESA_SUCCESS; - - if (IsBsp (StdHeader, &IgnoredStatus)) { - for (i = 0; SupportedCpuFeatureList[i] != NULL; i++) { - if ((SupportedCpuFeatureList[i]->EntryPoint & EntryPoint) != 0) { - if (SupportedCpuFeatureList[i]->IsEnabled (PlatformConfig, StdHeader)) { - CalledStatus = SupportedCpuFeatureList[i]->InitializeFeature (EntryPoint, PlatformConfig, StdHeader); - if (CalledStatus > AgesaStatus) { - AgesaStatus = CalledStatus; - } - } - } - } - } - return AgesaStatus; -} - -/** - * This routine checks whether any non-coherent links in the system - * runs in HT1 mode; used to determine whether certain features - * should be disabled when this routine returns TRUE. - * - * @param[in] StdHeader Standard AMD configuration parameters. - * - * @retval TRUE One of the non-coherent links in the - * system runs in HT1 mode - * @retval FALSE None of the non-coherent links in the - * system is running in HT1 mode - */ -BOOLEAN -IsNonCoherentHt1 ( - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - UINTN Link; - UINT32 Socket; - UINT32 Module; - PCI_ADDR PciAddress; - AGESA_STATUS AgesaStatus; - HT_HOST_FEATS HtHostFeats; - CPU_SPECIFIC_SERVICES *CpuServices; - - for (Socket = 0; Socket < GetPlatformNumberOfSockets (); Socket++) { - if (IsProcessorPresent (Socket, StdHeader)) { - GetCpuServicesOfSocket (Socket, (const CPU_SPECIFIC_SERVICES **) &CpuServices, StdHeader); - for (Module = 0; Module < GetPlatformNumberOfModules (); Module++) { - if (GetPciAddress (StdHeader, Socket, Module, &PciAddress, &AgesaStatus)) { - HtHostFeats.HtHostValue = 0; - Link = 0; - while (CpuServices->GetNextHtLinkFeatures (CpuServices, &Link, &PciAddress, &HtHostFeats, StdHeader)) { - // Return TRUE and exit routine once we find a non-coherent link in HT1 - if ((HtHostFeats.HtHostFeatures.NonCoherent == 1) && (HtHostFeats.HtHostFeatures.Ht1 == 1)) { - return TRUE; - } - } - } - } - } - } - - return FALSE; -} diff --git a/src/vendorcode/amd/agesa/f12/Proc/CPU/Feature/cpuFeatures.h b/src/vendorcode/amd/agesa/f12/Proc/CPU/Feature/cpuFeatures.h deleted file mode 100644 index 79be036551..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/CPU/Feature/cpuFeatures.h +++ /dev/null @@ -1,266 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * Generic CPU feature dispatcher and related services. - * - * Provides a feature processing engine to handle feature in a - * more generic way. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: Common - * @e \$Revision: 49029 $ @e \$Date: 2011-03-16 09:55:06 +0800 (Wed, 16 Mar 2011) $ - * - */ -/* - ****************************************************************************** - * - * Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - ****************************************************************************** - */ - -#ifndef _CPU_FEATURES_H_ -#define _CPU_FEATURES_H_ - -/** - * @page cpufeatimpl CPU Generic Feature Implementation Guide - * - * The CPU generic feature dispatcher provides services which can be used to implement a - * wide range of features in a manner that isolates calling code from knowledge about which - * families or features are supported in the current build. - * - * @par Determine if a New Feature is a Suitable Candidate - * - * A feature must meet the following requirements: - *
    - *
  • Any core in the system must be able to determine if the feature should be enabled or not. - * - *
      - *
    • MSRs cannot be read in multisocket systems in the 'IsEnabled' function. - * - *
    • Cores cannot be launched in the 'IsEnabled' function. - *
    - *
- * - * @par Determine the Time Point at which the Feature Should be Enabled - * - * Factors to consider in making this determination: - * - *
    - *
  • Determine if there are any dependencies on other settings that require strict ordering. - * - *
  • Consider the state of the APs that you will need. - * - *
  • Remember that features enabled during AmdInitEarly will automatically be restored on S3 resume. - *
- * - * @par Implementing a new feature - * - * Perform the following steps to implement a new feature: - * - *
    - *
  • Create a unique equate for your time point, @b if you cannot use an existing time point. - * - *
  • Create a new value in the DISPATCHABLE_CPU_FEATURES enum for your feature. - * - *
  • Add a new 'C' file to the Features folder for your feature. - * - *
      - *
    • The 'C' file must implement 2 functions -- 'IsEnabled' and 'Initialize' - * - *
    • The 'C' file must instantiate a CPU_FEATURE_DESCRIPTOR structure. - *
    - * - *
  • Add a new 'H' file to the Features folder for your feature. - * - *
      - *
    • The 'H' file declares whatever family specific functions required by the feature. - * - *
    • The 'H' file declares a structure containing all family specific functions. For a reference - * example, your feature API should have a set of conventions similar to cpu specific services, - * @ref cpuimplfss. - *
    - * - *
  • Create 'C' files in all applicable family folders. - * - *
      - *
    • Implement the required family specific functions. - * - *
    • Instantiate a family specific services structure. - *
    - * - *
  • Create \Install.h in the include folder. - * - *
      - *
    • Add logic to determine when your feature should be included in the build. - * - *
    • If the feature should be included, define OPTION_\ to the address of your - * CPU_FEATURE_DESCRIPTOR instantiation. If not, define OPTION_\ to be blank. - * - *
    • Create a family translation table pointing to all applicable instantiations of - * family specific function structures. - *
    - * - *
  • Modify OptionCpuFeaturesInstall.h in the include folder. - * - *
      - *
    • Include \Install.h. - * - *
    • Add OPTION_\ to the SupportedCpuFeatureList array. - *
    - * - *
  • If a new time point was created, add a call to DispatchCpuFeatures at the desired location, - * passing your new time point equate. - *
- * - */ - - -/*---------------------------------------------------------------------------------------- - * M I X E D (Definitions And Macros / Typedefs, Structures, Enums) - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------- - * D E F I N I T I O N S A N D M A C R O S - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------- - * T Y P E D E F S, S T R U C T U R E S, E N U M S - *---------------------------------------------------------------------------------------- - */ -#define CPU_FEAT_BEFORE_PM_INIT (0x0000000000000001ull) -#define CPU_FEAT_AFTER_PM_INIT (0x0000000000000002ull) -#define CPU_FEAT_AFTER_POST_MTRR_SYNC (0x0000000000000004ull) -#define CPU_FEAT_INIT_MID_END (0x0000000000000008ull) -#define CPU_FEAT_INIT_LATE_END (0x0000000000000010ull) -#define CPU_FEAT_S3_LATE_RESTORE_END (0x0000000000000020ull) -#define CPU_FEAT_AFTER_RESUME_MTRR_SYNC (0x0000000000000040ull) -#define CPU_FEAT_AFTER_COHERENT_DISCOVERY (0x0000000000000080ull) -#define CPU_FEAT_BEFORE_RELINQUISH_AP (0x0000000000000100ull) -/** - * Enumerated list of supported features. - */ -typedef enum { - HardwareC1e, ///< Hardware C1e - L3Features, ///< L3 dependent features - MsgBasedC1e, ///< Message-based C1e - SoftwareC1e, ///< Software C1e - CoreLeveling, ///< Core Leveling - C6Cstate, ///< C6 C-state - IoCstate, ///< IO C-state - CacheFlushOnHalt, ///< Cache Flush On Halt - PreserveAroundMailbox, ///< Save-Restore the registers used for AP mailbox, to preserve their normal function. - CoreBoost, ///< Core Performance Boost (CPB) - LowPwrPstate, ///< 500 MHz Low Power P-state - MaxCpuFeature ///< Not a valid value, used for verifying input -} DISPATCHABLE_CPU_FEATURES; - -/*---------------------------------------------------------------------------------------*/ -/** - * Feature specific call to check if it is supported by the system. - * - * @param[in] PlatformConfig Contains the runtime modifiable feature input data. - * @param[in] StdHeader Config Handle for library, services. - * - * @retval TRUE Feature is supported. - * @retval FALSE Feature is not supported. - * - */ -typedef BOOLEAN F_CPU_FEATURE_IS_ENABLED ( - IN PLATFORM_CONFIGURATION *PlatformConfig, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -/// Reference to a Method. -typedef F_CPU_FEATURE_IS_ENABLED *PF_CPU_FEATURE_IS_ENABLED; - -/*---------------------------------------------------------------------------------------*/ -/** - * The feature's main entry point for enablement. - * - * @param[in] EntryPoint Timepoint designator. - * @param[in] PlatformConfig Contains the runtime modifiable feature input data. - * @param[in] StdHeader Config Handle for library, services. - * - * @return Family specific error value. - * - */ -typedef AGESA_STATUS F_CPU_FEATURE_INITIALIZE ( - IN UINT64 EntryPoint, - IN PLATFORM_CONFIGURATION *PlatformConfig, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -/// Reference to a Method. -typedef F_CPU_FEATURE_INITIALIZE *PF_CPU_FEATURE_INITIALIZE; - - -/** - * Generic feature descriptor - */ -typedef struct { - DISPATCHABLE_CPU_FEATURES Feature; ///< Enumerated feature ID - UINT64 EntryPoint; ///< Timepoint designator - PF_CPU_FEATURE_IS_ENABLED IsEnabled; ///< Pointer to the function that checks if the feature is supported - PF_CPU_FEATURE_INITIALIZE InitializeFeature; ///< Pointer to the function that enables the feature -} CPU_FEATURE_DESCRIPTOR; - -/** - * Table descriptor for the installed features. - */ -typedef struct { - UINT8 NumberOfFeats; ///< Number of valid entries in the table. - CPU_FEATURE_DESCRIPTOR *FeatureList; ///< Pointer to the first element in the array. -} CPU_FEATURE_TABLE; - -/*---------------------------------------------------------------------------------------- - * F U N C T I O N P R O T O T Y P E - *---------------------------------------------------------------------------------------- - */ - -BOOLEAN -IsFeatureEnabled ( - IN DISPATCHABLE_CPU_FEATURES Feature, - IN PLATFORM_CONFIGURATION *PlatformConfig, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -AGESA_STATUS -DispatchCpuFeatures ( - IN UINT64 EntryPoint, - IN PLATFORM_CONFIGURATION *PlatformConfig, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -BOOLEAN -IsNonCoherentHt1 ( - IN AMD_CONFIG_PARAMS *StdHeader - ); - -#endif // _CPU_FEATURES_H_ diff --git a/src/vendorcode/amd/agesa/f12/Proc/CPU/Feature/cpuHwC1e.c b/src/vendorcode/amd/agesa/f12/Proc/CPU/Feature/cpuHwC1e.c deleted file mode 100644 index 6106d14987..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/CPU/Feature/cpuHwC1e.c +++ /dev/null @@ -1,180 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * AMD AGESA CPU HW C1e feature support code. - * - * Contains code that declares the AGESA CPU C1e related APIs - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: CPU/Feature - * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $ - * - */ -/* - ****************************************************************************** - * - * Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - ****************************************************************************** - */ - -/*---------------------------------------------------------------------------------------- - * M O D U L E S U S E D - *---------------------------------------------------------------------------------------- - */ -#include "AGESA.h" -#include "amdlib.h" -#include "Ids.h" -#include "cpuRegisters.h" -#include "cpuApicUtilities.h" -#include "cpuServices.h" -#include "GeneralServices.h" -#include "cpuFamilyTranslation.h" -#include "Topology.h" -#include "cpuFeatures.h" -#include "cpuHwC1e.h" -#include "Filecode.h" -CODE_GROUP (G1_PEICC) -RDATA_GROUP (G1_PEICC) - -#define FILECODE PROC_CPU_FEATURE_CPUHWC1E_FILECODE -/*---------------------------------------------------------------------------------------- - * D E F I N I T I O N S A N D M A C R O S - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------- - * T Y P E D E F S A N D S T R U C T U R E S - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------- - * P R O T O T Y P E S O F L O C A L F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------- - * E X P O R T E D F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ -extern CPU_FAMILY_SUPPORT_TABLE HwC1eFamilyServiceTable; - -/*---------------------------------------------------------------------------------------*/ -/** - * Should hardware C1e be enabled - * - * @param[in] PlatformConfig Contains the runtime modifiable feature input data. - * @param[in] StdHeader Config Handle for library, services. - * - * @retval TRUE HW C1e is supported. - * @retval FALSE HW C1e cannot be enabled. - * - */ -BOOLEAN -STATIC -IsHwC1eFeatureEnabled ( - IN PLATFORM_CONFIGURATION *PlatformConfig, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - UINT32 C1eData; - BOOLEAN IsEnabled; - AP_MAILBOXES ApMailboxes; - HW_C1E_FAMILY_SERVICES *FamilyServices; - - ASSERT (PlatformConfig->C1eMode < MaxC1eMode); - IsEnabled = FALSE; - C1eData = PlatformConfig->C1ePlatformData; - if ((PlatformConfig->C1eMode == C1eModeHardware) || (PlatformConfig->C1eMode == C1eModeHardwareSoftwareDeprecated) || - (PlatformConfig->C1eMode == C1eModeAuto)) { - // If C1eMode is Auto, C1ePlatformData3 specifies the P_LVL3 I/O port of the platform for HW C1e - if (PlatformConfig->C1eMode == C1eModeAuto) { - C1eData = PlatformConfig->C1ePlatformData3; - } - ASSERT (C1eData < 0x10000); - ASSERT (C1eData != 0); - if ((C1eData != 0) && (C1eData < 0xFFFE)) { - if (!IsNonCoherentHt1 (StdHeader)) { - if (GetNumberOfProcessors (StdHeader) == 1) { - GetApMailbox (&ApMailboxes.ApMailInfo.Info, StdHeader); - if (ApMailboxes.ApMailInfo.Fields.ModuleType == 0) { - GetFeatureServicesOfCurrentCore (&HwC1eFamilyServiceTable, (const VOID **)&FamilyServices, StdHeader); - if (FamilyServices != NULL) { - IsEnabled = FamilyServices->IsHwC1eSupported (FamilyServices, StdHeader); - } - } - } - } - } - } - return IsEnabled; -} - -/*---------------------------------------------------------------------------------------*/ -/** - * Enable Hardware C1e - * - * @param[in] EntryPoint Timepoint designator. - * @param[in] PlatformConfig Contains the runtime modifiable feature input data. - * @param[in] StdHeader Config Handle for library, services. - * - * @return The most severe status of any family specific service. - * - */ -AGESA_STATUS -STATIC -InitializeHwC1eFeature ( - IN UINT64 EntryPoint, - IN PLATFORM_CONFIGURATION *PlatformConfig, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - AGESA_STATUS CalledStatus; - AGESA_STATUS AgesaStatus; - HW_C1E_FAMILY_SERVICES *FamilyServices; - - AgesaStatus = AGESA_SUCCESS; - - IDS_HDT_CONSOLE (CPU_TRACE, " HW C1e is enabled\n"); - - if (IsWarmReset (StdHeader)) { - GetFeatureServicesOfCurrentCore (&HwC1eFamilyServiceTable, (const VOID **)&FamilyServices, StdHeader); - CalledStatus = FamilyServices->InitializeHwC1e (FamilyServices, EntryPoint, PlatformConfig, StdHeader); - if (CalledStatus > AgesaStatus) { - AgesaStatus = CalledStatus; - } - } - return AgesaStatus; -} - -CONST CPU_FEATURE_DESCRIPTOR ROMDATA CpuFeatureHwC1e = -{ - HardwareC1e, - CPU_FEAT_AFTER_PM_INIT, - IsHwC1eFeatureEnabled, - InitializeHwC1eFeature -}; diff --git a/src/vendorcode/amd/agesa/f12/Proc/CPU/Feature/cpuHwC1e.h b/src/vendorcode/amd/agesa/f12/Proc/CPU/Feature/cpuHwC1e.h deleted file mode 100644 index f6bfafe730..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/CPU/Feature/cpuHwC1e.h +++ /dev/null @@ -1,125 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * AMD AGESA CPU HW C1e Functions declarations. - * - * Contains code that declares the AGESA CPU C1e related APIs - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: CPU/Feature - * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $ - * - */ -/* - ****************************************************************************** - * - * Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - ****************************************************************************** - */ - -#ifndef _CPU_HW_C1E_H_ -#define _CPU_HW_C1E_H_ - -/*---------------------------------------------------------------------------------------- - * M I X E D (Definitions And Macros / Typedefs, Structures, Enums) - *---------------------------------------------------------------------------------------- - */ -// Forward declaration needed for multi-structure mutual references -AGESA_FORWARD_DECLARATION (HW_C1E_FAMILY_SERVICES); - -/*---------------------------------------------------------------------------------------- - * D E F I N I T I O N S A N D M A C R O S - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------- - * T Y P E D E F S A N D S T R U C T U R E S - *---------------------------------------------------------------------------------------- - */ -/*---------------------------------------------------------------------------------------*/ -/** - * Family specific call to check if hardware C1e is supported. - * - * @param[in] HwC1eServices Hardware C1e services. - * @param[in] StdHeader Config Handle for library, services. - * - * @retval TRUE HW C1e is supported. - * @retval FALSE HW C1e is not supported. - * - */ -typedef BOOLEAN F_HW_C1E_IS_SUPPORTED ( - IN HW_C1E_FAMILY_SERVICES *HwC1eServices, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -/// Reference to a Method. -typedef F_HW_C1E_IS_SUPPORTED *PF_HW_C1E_IS_SUPPORTED; - -/*---------------------------------------------------------------------------------------*/ -/** - * Family specific call to enable hardware C1e. - * - * @param[in] HwC1eServices Hardware C1e services. - * @param[in] EntryPoint Timepoint designator. - * @param[in] PlatformConfig Contains the runtime modifiable feature input data. - * @param[in] StdHeader Config Handle for library, services. - * - * @return Family specific error value. - * - */ -typedef AGESA_STATUS F_HW_C1E_INIT ( - IN HW_C1E_FAMILY_SERVICES *HwC1eServices, - IN UINT64 EntryPoint, - IN PLATFORM_CONFIGURATION *PlatformConfig, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -/// Reference to a Method. -typedef F_HW_C1E_INIT *PF_HW_C1E_INIT; - -/** - * Provide the interface to the hardware C1e Family Specific Services. - * - * Use the methods or data in this struct to adapt the feature code to a specific cpu family or model (or stepping!). - * Each supported Family must provide an implementation for all methods in this interface, even if the - * implementation is a CommonReturn(). - */ -struct _HW_C1E_FAMILY_SERVICES { - UINT16 Revision; ///< Interface version - // Public Methods. - PF_HW_C1E_IS_SUPPORTED IsHwC1eSupported; ///< Method: Family specific call to check if hardware C1e is supported. - PF_HW_C1E_INIT InitializeHwC1e; ///< Method: Family specific call to enable hardware C1e. -}; - - -/*---------------------------------------------------------------------------------------- - * F U N C T I O N S P R O T O T Y P E - *---------------------------------------------------------------------------------------- - */ - -#endif // _CPU_HW_C1E_H_ diff --git a/src/vendorcode/amd/agesa/f12/Proc/CPU/Feature/cpuIoCstate.c b/src/vendorcode/amd/agesa/f12/Proc/CPU/Feature/cpuIoCstate.c deleted file mode 100644 index c9a42ce57f..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/CPU/Feature/cpuIoCstate.c +++ /dev/null @@ -1,208 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * AMD AGESA CPU IO Cstate function declarations. - * - * Contains code that declares the AGESA CPU IO Cstate related APIs - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: CPU/Feature - * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $ - */ -/* - ****************************************************************************** - * - * Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - ****************************************************************************** - */ - -/*---------------------------------------------------------------------------------------- - * M O D U L E S U S E D - *---------------------------------------------------------------------------------------- - */ - -#include "AGESA.h" -#include "amdlib.h" -#include "cpuRegisters.h" -#include "cpuFeatures.h" -#include "cpuIoCstate.h" -#include "cpuServices.h" -#include "cpuFamilyTranslation.h" -#include "cpuApicUtilities.h" -#include "OptionMultiSocket.h" -#include "Filecode.h" -CODE_GROUP (G1_PEICC) -RDATA_GROUP (G1_PEICC) - -#define FILECODE PROC_CPU_FEATURE_CPUIOCSTATE_FILECODE - -/*---------------------------------------------------------------------------------------- - * D E F I N I T I O N S A N D M A C R O S - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------- - * T Y P E D E F S A N D S T R U C T U R E S - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------- - * P R O T O T Y P E S O F L O C A L F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ - -VOID -STATIC -EnableIoCstateOnSocket ( - IN VOID *EntryPoint, - IN AMD_CONFIG_PARAMS *StdHeader, - IN AMD_CPU_EARLY_PARAMS *CpuEarlyParams - ); -/*---------------------------------------------------------------------------------------- - * E X P O R T E D F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ -extern CPU_FAMILY_SUPPORT_TABLE IoCstateFamilyServiceTable; -extern OPTION_MULTISOCKET_CONFIGURATION OptionMultiSocketConfiguration; - -/*---------------------------------------------------------------------------------------*/ -/** - * Should IO Cstate be enabled - * If all processors support IO Cstate, return TRUE. Otherwise, return FALSE - * - * @param[in] PlatformConfig Contains the runtime modifiable feature input data. - * @param[in] StdHeader Config Handle for library, services. - * - * @retval TRUE IO Cstate is supported. - * @retval FALSE IO Cstate cannot be enabled. - * - */ -BOOLEAN -STATIC -IsIoCstateFeatureSupported ( - IN PLATFORM_CONFIGURATION *PlatformConfig, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - UINT32 Socket; - BOOLEAN IsSupported; - IO_CSTATE_FAMILY_SERVICES *IoCstateServices; - - IsSupported = FALSE; - if ((PlatformConfig->CStateIoBaseAddress != 0) && (PlatformConfig->CStateIoBaseAddress <= 0xFFF8)) { - for (Socket = 0; Socket < GetPlatformNumberOfSockets (); Socket++) { - if (IsProcessorPresent (Socket, StdHeader)) { - GetFeatureServicesOfSocket (&IoCstateFamilyServiceTable, Socket, (const VOID **)&IoCstateServices, StdHeader); - if (IoCstateServices != NULL) { - if (IoCstateServices->IsIoCstateSupported (IoCstateServices, Socket, StdHeader)) { - IsSupported = TRUE; - } else { - // Stop checking remaining socket(s) once we find one that does not support IO Cstates - IsSupported = FALSE; - break; - } - } else { - // Exit the for loop if we found a socket that does not have the IO Cstates feature installed - IsSupported = FALSE; - break; - } - } - } - } - return IsSupported; -} - -/*---------------------------------------------------------------------------------------*/ -/** - * Enable IO Cstate feature - * - * @param[in] EntryPoint Timepoint designator. - * @param[in] PlatformConfig Contains the runtime modifiable feature input data. - * @param[in] StdHeader Config Handle for library, services. - * - * @retval AGESA_SUCCESS Always succeeds. - * - */ -AGESA_STATUS -STATIC -InitializeIoCstateFeature ( - IN UINT64 EntryPoint, - IN PLATFORM_CONFIGURATION *PlatformConfig, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - AP_TASK TaskPtr; - AMD_CPU_EARLY_PARAMS CpuEarlyParams; - - IDS_HDT_CONSOLE (CPU_TRACE, " IO C-state is enabled\n"); - - CpuEarlyParams.PlatformConfig = *PlatformConfig; - - TaskPtr.FuncAddress.PfApTaskIC = EnableIoCstateOnSocket; - TaskPtr.DataTransfer.DataSizeInDwords = 2; - TaskPtr.DataTransfer.DataPtr = &EntryPoint; - TaskPtr.DataTransfer.DataTransferFlags = 0; - TaskPtr.ExeFlags = PASS_EARLY_PARAMS; - OptionMultiSocketConfiguration.BscRunCodeOnAllSystemCore0s (&TaskPtr, StdHeader, &CpuEarlyParams); - - return AGESA_SUCCESS; -} - -/*---------------------------------------------------------------------------------------*/ -/** - * 'Local' core 0 task to enable IO Cstate on it's socket. - * - * @param[in] EntryPoint Timepoint designator. - * @param[in] StdHeader Config Handle for library, services. - * @param[in] CpuEarlyParams Service parameters. - * - */ -VOID -STATIC -EnableIoCstateOnSocket ( - IN VOID *EntryPoint, - IN AMD_CONFIG_PARAMS *StdHeader, - IN AMD_CPU_EARLY_PARAMS *CpuEarlyParams - ) -{ - IO_CSTATE_FAMILY_SERVICES *FamilyServices; - - GetFeatureServicesOfCurrentCore (&IoCstateFamilyServiceTable, (const VOID **)&FamilyServices, StdHeader); - FamilyServices->InitializeIoCstate (FamilyServices, - *((UINT64 *) EntryPoint), - &CpuEarlyParams->PlatformConfig, - StdHeader); -} - -CONST CPU_FEATURE_DESCRIPTOR ROMDATA CpuFeatureIoCstate = -{ - IoCstate, - (CPU_FEAT_AFTER_PM_INIT), - IsIoCstateFeatureSupported, - InitializeIoCstateFeature -}; diff --git a/src/vendorcode/amd/agesa/f12/Proc/CPU/Feature/cpuIoCstate.h b/src/vendorcode/amd/agesa/f12/Proc/CPU/Feature/cpuIoCstate.h deleted file mode 100644 index 27e1a1b1a9..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/CPU/Feature/cpuIoCstate.h +++ /dev/null @@ -1,283 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * AMD AGESA CPU IO Cstate feature support code. - * - * Contains code that declares the AGESA CPU IO Cstate related APIs - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: CPU/Feature - * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $ - */ -/* - ****************************************************************************** - * - * Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - ****************************************************************************** - */ - -#ifndef _CPU_IO_CSTATE_H_ -#define _CPU_IO_CSTATE_H_ - -/*---------------------------------------------------------------------------------------- - * M I X E D (Definitions And Macros / Typedefs, Structures, Enums) - *---------------------------------------------------------------------------------------- - */ -// Forward declaration needed for multi-structure mutual references -AGESA_FORWARD_DECLARATION (IO_CSTATE_FAMILY_SERVICES); - -/*---------------------------------------------------------------------------------------- - * D E F I N I T I O N S A N D M A C R O S - *---------------------------------------------------------------------------------------- - */ -// Defines for ACPI C-State Objects -#define CST_NAME__ '_' -#define CST_NAME_C 'C' -#define CST_NAME_S 'S' -#define CST_NAME_T 'T' -#define CST_LENGTH (CST_BODY_SIZE - 1) -#define CST_NUM_OF_ELEMENTS 0x02 -#define CST_COUNT 0x01 -#define CST_PKG_LENGTH (CST_BODY_SIZE - 6) // CST_BODY_SIZE - PkgHeader - Count Buffer -#define CST_PKG_ELEMENTS 0x04 -#define CST_SUBPKG_LENGTH 0x14 -#define CST_SUBPKG_ELEMENTS 0x0A -#define CST_GDR_LENGTH 0x000C -#define CST_C1_TYPE 0x01 -#define CST_C2_TYPE 0x02 - -#define CSD_NAME_D 'D' -#define CSD_COORD_TYPE_HW_ALL 0xFE - -/*---------------------------------------------------------------------------------------- - * T Y P E D E F S A N D S T R U C T U R E S - *---------------------------------------------------------------------------------------- - */ -/* AML code definition */ - -/// CST Header -typedef struct _CST_HEADER_STRUCT { - UINT8 NameOpcode; ///< Name Opcode - UINT8 CstName_a__; ///< String "_" - UINT8 CstName_a_C; ///< String "C" - UINT8 CstName_a_S; ///< String "S" - UINT8 CstName_a_T; ///< String "T" -} CST_HEADER_STRUCT; -#define CST_HEADER_SIZE 5 - -/// CST Body -typedef struct _CST_BODY_STRUCT { - UINT8 PkgOpcode; ///< Package Opcode - UINT8 PkgLength; ///< Package Length - UINT8 PkgElements; ///< Number of Elements - UINT8 BytePrefix; ///< Byte Prefix Opcode - UINT8 Count; ///< Number of Cstate info packages - UINT8 PkgOpcode2; ///< Package Opcode - UINT8 PkgLength2; ///< Package Length - UINT8 PkgElements2; ///< Number of Elements - UINT8 BufferOpcode; ///< Buffer Opcode - UINT8 BufferLength; ///< Buffer Length - UINT8 BufferElements; ///< Number of Elements - UINT8 BufferOpcode2; ///< Buffer Opcode - UINT8 GdrOpcode; ///< Generic Register Descriptor Opcode - UINT16 GdrLength; ///< Descriptor Length - UINT8 AddrSpaceId; ///< Address Space ID - UINT8 RegBitWidth; ///< Register Bit Width - UINT8 RegBitOffset; ///< Register Bit Offset - UINT8 AddressSize; ///< Address Size - UINT64 RegisterAddr; ///< Register Address - UINT16 EndTag; ///< End Tag Descriptor - UINT8 BytePrefix2; ///< Byte Prefix Opcode - UINT8 Type; ///< Type - UINT8 WordPrefix; ///< Word Prefix Opcode - UINT16 Latency; ///< Latency - UINT8 DWordPrefix; ///< Dword Prefix Opcode - UINT32 Power; ///< Power -} CST_BODY_STRUCT; -#define CST_BODY_SIZE 39 - -/// CSD Header -typedef struct _CSD_HEADER_STRUCT { - UINT8 NameOpcode; ///< Name Opcode - UINT8 CsdName_a__; ///< String "_" - UINT8 CsdName_a_C; ///< String "C" - UINT8 CsdName_a_S; ///< String "S" - UINT8 CsdName_a_D; ///< String "D" -} CSD_HEADER_STRUCT; -#define CSD_HEADER_SIZE 5 - -/// CSD Body -typedef struct _CSD_BODY_STRUCT { - UINT8 PkgOpcode; ///< Package Opcode - UINT8 PkgLength; ///< Package Length - UINT8 PkgElements; ///< Number of Elements - UINT8 PkgOpcode2; ///< Package Opcode - UINT8 PkgLength2; ///< Package Length - UINT8 PkgElements2; ///< Number of Elements - UINT8 BytePrefix; ///< Byte Prefix Opcode - UINT8 NumEntries; ///< Number of Entries - UINT8 BytePrefix2; ///< Byte Prefix Opcode - UINT8 Revision; ///< Revision - UINT8 DWordPrefix; ///< DWord Prefix Opcode - UINT32 Domain; ///< Dependency Domain Number - UINT8 DWordPrefix2; ///< DWord Prefix Opcode - UINT32 CoordType; ///< Coordination Type - UINT8 DWordPrefix3; ///< Dword Prefix Opcode - UINT32 NumProcessors; ///< Number of Processors in the Domain - UINT8 DWordPrefix4; ///< Dword Prefix Opcode - UINT32 Index; ///< Index of C-State entry for which dependency applies -} CSD_BODY_STRUCT; -#define CSD_BODY_SIZE 30 - -/// input for create _CST -typedef struct _ACPI_CST_CREATE_INPUT { - IO_CSTATE_FAMILY_SERVICES *IoCstateServices; ///< Family service of IoCstate - UINT8 LocalApicId; ///< Local Apic for create _CST - VOID **PstateAcpiBufferPtr; ///< buffer for fill _CST -} ACPI_CST_CREATE_INPUT ; - -/// input for get _CST -typedef struct _ACPI_CST_GET_INPUT { - IO_CSTATE_FAMILY_SERVICES *IoCstateServices; ///< Family service of IoCstate - PLATFORM_CONFIGURATION *PlatformConfig; ///< platform config - UINT32 *CStateAcpiObjSizePtr; ///< Point to size of _CST -} ACPI_CST_GET_INPUT ; - - -/*---------------------------------------------------------------------------------------*/ -/** - * Family specific call to check if IO Cstate is supported. - * - * @param[in] IoCstateServices IO Cstate services. - * @param[in] Socket Zero-based socket number. - * @param[in] StdHeader Config Handle for library, services. - * - * @retval TRUE IO Cstate is supported. - * @retval FALSE IO Cstate is not supported. - * - */ -typedef BOOLEAN F_IO_CSTATE_IS_SUPPORTED ( - IN IO_CSTATE_FAMILY_SERVICES *IoCstateServices, - IN UINT32 Socket, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -/*---------------------------------------------------------------------------------------*/ -/** - * Family specific call to enable IO Cstate. - * - * @param[in] IoCstateServices IO Cstate services. - * @param[in] EntryPoint Timepoint designator. - * @param[in] PlatformConfig Contains the runtime modifiable feature input data. - * @param[in] StdHeader Config Handle for library, services. - * - * @return Family specific error value. - * - */ -typedef AGESA_STATUS F_IO_CSTATE_INIT ( - IN IO_CSTATE_FAMILY_SERVICES *IoCstateServices, - IN UINT64 EntryPoint, - IN PLATFORM_CONFIGURATION *PlatformConfig, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -/*---------------------------------------------------------------------------------------*/ -/** - * Family specific call to return the size of ACPI C-State Objects - * - * @param[in] IoCstateServices IO Cstate services. - * @param[in] PlatformConfig Contains the runtime modifiable feature input data - * @param[in] StdHeader Config Handle for library, services. - * - * @retval Size of ACPI C-State Objects - * - */ -typedef UINT32 F_IO_CSTATE_GET_CST_SIZE ( - IN IO_CSTATE_FAMILY_SERVICES *IoCstateServices, - IN PLATFORM_CONFIGURATION *PlatformConfig, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -/*---------------------------------------------------------------------------------------*/ -/** - * Family specific call to create ACPI C-State Objects - * - * @param[in] IoCstateServices IO Cstate services. - * @param[in] LocalApicId Local Apic Id - * @param[in, out] PstateAcpiBufferPtr Pointer to Pstate data buffer - * @param[in] StdHeader Config Handle for library, services. - * - */ -typedef VOID F_IO_CSTATE_CREATE_CST ( - IN IO_CSTATE_FAMILY_SERVICES *IoCstateServices, - IN UINT8 LocalApicId, - IN OUT VOID **PstateAcpiBufferPtr, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -/*---------------------------------------------------------------------------------------*/ -/** - * Family specific call to check whether CSD object should be created. - * - * @param[in] IoCstateServices IO Cstate services. - * @param[in] StdHeader Config Handle for library, services. - * - * @retval TRUE CSD Object should be created. - * @retval FALSE CSD Object should not be created. - * - */ -typedef BOOLEAN F_IO_CSTATE_IS_CSD_GENERATED ( - IN IO_CSTATE_FAMILY_SERVICES *IoCstateServices, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -/// Reference to a Method -typedef F_IO_CSTATE_IS_SUPPORTED *PF_IO_CSTATE_IS_SUPPORTED; -typedef F_IO_CSTATE_INIT *PF_IO_CSTATE_INIT; -typedef F_IO_CSTATE_GET_CST_SIZE *PF_IO_CSTATE_GET_CST_SIZE; -typedef F_IO_CSTATE_CREATE_CST *PF_IO_CSTATE_CREATE_CST; -typedef F_IO_CSTATE_IS_CSD_GENERATED *PF_IO_CSTATE_IS_CSD_GENERATED; - -/** - * Provide the interface to the IO Cstate Family Specific Services. - * - * Use the methods or data in this struct to adapt the feature code to a specific cpu family or model (or stepping!). - * Each supported Family must provide an implementation for all methods in this interface, even if the - * implementation is a CommonReturn(). - */ -struct _IO_CSTATE_FAMILY_SERVICES { - UINT16 Revision; ///< Interface version - // Public Methods. - PF_IO_CSTATE_IS_SUPPORTED IsIoCstateSupported; ///< Method: Family specific call to check if IO Cstate is supported. - PF_IO_CSTATE_INIT InitializeIoCstate; ///< Method: Family specific call to enable IO Cstate - PF_IO_CSTATE_GET_CST_SIZE GetAcpiCstObj; ///< Method: Family specific call to return the size of ACPI CST objects. - PF_IO_CSTATE_CREATE_CST CreateAcpiCstObj; ///< Method: Family specific call to create ACPI CST object - PF_IO_CSTATE_IS_CSD_GENERATED IsCsdObjGenerated; ///< Method: Family specific call to check whether CSD Object should be created. -}; - -#endif // _CPU_IO_CSTATE_H_ diff --git a/src/vendorcode/amd/agesa/f12/Proc/CPU/Feature/cpuL3Features.c b/src/vendorcode/amd/agesa/f12/Proc/CPU/Feature/cpuL3Features.c deleted file mode 100644 index 5ccda88a83..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/CPU/Feature/cpuL3Features.c +++ /dev/null @@ -1,349 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * AMD CPU L3 Features Initialization functions. - * - * Contains code for initializing L3 features. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: CPU - * @e \$Revision: 49463 $ @e \$Date: 2011-03-24 05:33:12 +0800 (Thu, 24 Mar 2011) $ - * - */ -/* - ****************************************************************************** - * - * Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - ****************************************************************************** - */ - - -/* - *---------------------------------------------------------------------------- - * MODULES USED - * - *---------------------------------------------------------------------------- - */ - -#include "AGESA.h" -#include "amdlib.h" -#include "Ids.h" -#include "cpuRegisters.h" -#include "cpuLateInit.h" -#include "cpuFamilyTranslation.h" -#include "cpuServices.h" -#include "GeneralServices.h" -#include "cpuFeatures.h" -#include "cpuL3Features.h" -#include "Filecode.h" -CODE_GROUP (G2_PEI) -RDATA_GROUP (G2_PEI) - -#define FILECODE PROC_CPU_FEATURE_CPUL3FEATURES_FILECODE -/*---------------------------------------------------------------------------- - * DEFINITIONS AND MACROS - * - *---------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------- - * TYPEDEFS AND STRUCTURES - * - *---------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------- - * PROTOTYPES OF LOCAL FUNCTIONS - * - *---------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------- - * EXPORTED FUNCTIONS - * - *---------------------------------------------------------------------------- - */ -extern CPU_FAMILY_SUPPORT_TABLE L3FeatureFamilyServiceTable; - -/*---------------------------------------------------------------------------------------*/ -/** - * Should L3 features be enabled - * - * @param[in] PlatformConfig Contains the runtime modifiable feature input data. - * @param[in] StdHeader Config Handle for library, services. - * - * @retval TRUE L3 Features are supported - * @retval FALSE L3 Features are not supported - * - */ -BOOLEAN -STATIC -IsL3FeatureEnabled ( - IN PLATFORM_CONFIGURATION *PlatformConfig, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - BOOLEAN IsEnabled; - UINT32 Socket; - L3_FEATURE_FAMILY_SERVICES *FamilyServices; - - IsEnabled = FALSE; - if (PlatformConfig->PlatformProfile.UseHtAssist || - PlatformConfig->PlatformProfile.UseAtmMode) { - IsEnabled = TRUE; - for (Socket = 0; Socket < GetPlatformNumberOfSockets (); Socket++) { - if (IsProcessorPresent (Socket, StdHeader)) { - GetFeatureServicesOfSocket (&L3FeatureFamilyServiceTable, Socket, (const VOID **) &FamilyServices, StdHeader); - if ((FamilyServices == NULL) || !FamilyServices->IsL3FeatureSupported (FamilyServices, Socket, StdHeader)) { - IsEnabled = FALSE; - break; - } - } - } - } - return IsEnabled; -} - -/*---------------------------------------------------------------------------------------*/ -/** - * Enable L3 dependent features. - * - * L3 features initialization requires the following series of steps. - * 1. Disable L3 and DRAM scrubbers on all nodes - * 2. Wait 40us for outstanding scrub results to complete - * 3. Disable all cache activity in the system - * 4. Issue WBINVD on all active cores - * 5. Initialize Probe Filter, if supported - * 6. Initialize ATM Mode, if supported - * 7. Enable all cache activity in the system - * 8. Restore L3 and DRAM scrubber register values - * - * @param[in] EntryPoint Timepoint designator. - * @param[in] PlatformConfig Contains the runtime modifiable feature input data. - * @param[in] StdHeader Config Handle for library, services. - * - * @retval AGESA_SUCCESS Always succeeds. - * - */ -AGESA_STATUS -STATIC -InitializeL3Feature ( - IN UINT64 EntryPoint, - IN PLATFORM_CONFIGURATION *PlatformConfig, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - UINT32 CpuCount; - UINT32 Socket; - BOOLEAN HtAssistEnabled; - BOOLEAN AtmModeEnabled; - AGESA_STATUS AgesaStatus; - AP_MAILBOXES ApMailboxes; - AP_EXE_PARAMS ApParams; - UINT32 Scrubbers[MAX_SOCKETS_SUPPORTED][L3_SCRUBBER_CONTEXT_ARRAY_SIZE]; - L3_FEATURE_FAMILY_SERVICES *FamilyServices[MAX_SOCKETS_SUPPORTED]; - - AgesaStatus = AGESA_SUCCESS; - HtAssistEnabled = TRUE; - AtmModeEnabled = TRUE; - - IDS_HDT_CONSOLE (CPU_TRACE, " Enabling L3 dependent features\n"); - - // There are many family service call outs. Initialize the family service array while - // cache is still enabled. - for (Socket = 0; Socket < MAX_SOCKETS_SUPPORTED; Socket++) { - if (IsProcessorPresent (Socket, StdHeader)) { - GetFeatureServicesOfSocket (&L3FeatureFamilyServiceTable, Socket, (const VOID **) &FamilyServices[Socket], StdHeader); - } else { - FamilyServices[Socket] = NULL; - } - } - - if (EntryPoint == CPU_FEAT_AFTER_POST_MTRR_SYNC) { - // Check for optimal settings - GetApMailbox (&ApMailboxes.ApMailInfo.Info, StdHeader); - CpuCount = GetNumberOfProcessors (StdHeader); - if (((CpuCount == 1) && (ApMailboxes.ApMailInfo.Fields.ModuleType == 1)) || - ((CpuCount == 2) && (ApMailboxes.ApMailInfo.Fields.ModuleType == 0))) { - for (Socket = 0; Socket < GetPlatformNumberOfSockets (); Socket++) { - // Only check for non-optimal HT Assist setting is if's supported. - if ((FamilyServices[Socket] != NULL) && - (FamilyServices[Socket]->IsHtAssistSupported (FamilyServices[Socket], PlatformConfig, StdHeader))) { - if (FamilyServices[Socket]->IsNonOptimalConfig (FamilyServices[Socket], Socket, StdHeader)) { - // Non-optimal settings. Log an event. - AgesaStatus = AGESA_WARNING; - PutEventLog (AgesaStatus, CPU_WARNING_NONOPTIMAL_HT_ASSIST_CFG, 0, 0, 0, 0, StdHeader); - break; - } - } - } - } - } else { - // Disable the scrubbers. - for (Socket = 0; Socket < GetPlatformNumberOfSockets (); Socket++) { - if (FamilyServices[Socket] != NULL) { - FamilyServices[Socket]->GetL3ScrubCtrl (FamilyServices[Socket], Socket, &Scrubbers[Socket][0], StdHeader); - - // If any node in the system does not support Probe Filter, disable it on the system - if (!FamilyServices[Socket]->IsHtAssistSupported (FamilyServices[Socket], PlatformConfig, StdHeader)) { - HtAssistEnabled = FALSE; - } - // If any node in the system does not support ATM mode, disable it on the system - if (!FamilyServices[Socket]->IsAtmModeSupported (FamilyServices[Socket], PlatformConfig, StdHeader)) { - AtmModeEnabled = FALSE; - } - } - } - - // Wait for 40us - WaitMicroseconds ((UINT32) 40, StdHeader); - - // Run DisableAllCaches on AP cores. - ApParams.StdHeader = *StdHeader; - ApParams.FunctionNumber = AP_LATE_TASK_DISABLE_CACHE; - ApParams.RelatedDataBlock = (VOID *) &HtAssistEnabled; - ApParams.RelatedBlockLength = sizeof (BOOLEAN); - RunLateApTaskOnAllAPs (&ApParams, StdHeader); - - // Run DisableAllCaches on core 0. - DisableAllCaches (&ApParams); - - // Family hook before initialization. - for (Socket = 0; Socket < GetPlatformNumberOfSockets (); Socket++) { - if (FamilyServices[Socket] != NULL) { - FamilyServices[Socket]->HookBeforeInit (FamilyServices[Socket], Socket, StdHeader); - } - } - - // Activate Probe Filter & ATM mode. - for (Socket = 0; Socket < GetPlatformNumberOfSockets (); Socket++) { - if (FamilyServices[Socket] != NULL) { - if (HtAssistEnabled) { - FamilyServices[Socket]->HtAssistInit (FamilyServices[Socket], Socket, StdHeader); - } - if (AtmModeEnabled) { - FamilyServices[Socket]->AtmModeInit (FamilyServices[Socket], Socket, StdHeader); - } - } - } - - // Family hook after initialization. - for (Socket = 0; Socket < GetPlatformNumberOfSockets (); Socket++) { - if (FamilyServices[Socket] != NULL) { - FamilyServices[Socket]->HookAfterInit (FamilyServices[Socket], Socket, StdHeader); - } - } - - // Run EnableAllCaches on core 0. - EnableAllCaches (&ApParams); - - // Run EnableAllCaches on every core. - ApParams.FunctionNumber = AP_LATE_TASK_ENABLE_CACHE; - RunLateApTaskOnAllAPs (&ApParams, StdHeader); - - // Restore the scrubbers. - for (Socket = 0; Socket < GetPlatformNumberOfSockets (); Socket++) { - if (FamilyServices[Socket] != NULL) { - FamilyServices[Socket]->SetL3ScrubCtrl (FamilyServices[Socket], Socket, &Scrubbers[Socket][0], StdHeader); - } - } - } - - return AgesaStatus; -} - -/*---------------------------------------------------------------------------------------*/ -/** - * - * Disable all the caches on current core. - * - * @param[in] ApExeParams Handle to config for library and services. - * - * @retval AGESA_SUCCESS Always succeeds. - * - */ -AGESA_STATUS -DisableAllCaches ( - IN AP_EXE_PARAMS *ApExeParams - ) -{ - UINT32 CR0Data; - L3_FEATURE_FAMILY_SERVICES *FamilyServices; - - // Disable cache through CR0. - LibAmdReadCpuReg (0, &CR0Data); - CR0Data |= (0x60000000); - LibAmdWriteCpuReg (0, CR0Data); - - // Execute wbinvd - LibAmdWriteBackInvalidateCache (); - - GetFeatureServicesOfCurrentCore (&L3FeatureFamilyServiceTable, (const VOID **) &FamilyServices, &ApExeParams->StdHeader); - - FamilyServices->HookDisableCache (FamilyServices, *(BOOLEAN *) ApExeParams->RelatedDataBlock, &ApExeParams->StdHeader); - - return AGESA_SUCCESS; -} - -/*---------------------------------------------------------------------------------------*/ -/** - * - * Enable all the caches on current core. - * - * @param[in] ApExeParams Handle to config for library and services. - * - * @retval AGESA_SUCCESS Always succeeds. - * - */ -AGESA_STATUS -EnableAllCaches ( - IN AP_EXE_PARAMS *ApExeParams - ) -{ - UINT32 CR0Data; - L3_FEATURE_FAMILY_SERVICES *FamilyServices; - - // Enable cache through CR0. - LibAmdReadCpuReg (0, &CR0Data); - CR0Data &= ~(0x60000000); - LibAmdWriteCpuReg (0, CR0Data); - - GetFeatureServicesOfCurrentCore (&L3FeatureFamilyServiceTable, (const VOID **) &FamilyServices, &ApExeParams->StdHeader); - - FamilyServices->HookEnableCache (FamilyServices, &ApExeParams->StdHeader); - - return AGESA_SUCCESS; -} - -CONST CPU_FEATURE_DESCRIPTOR ROMDATA CpuL3Features = -{ - L3Features, - (CPU_FEAT_AFTER_POST_MTRR_SYNC | CPU_FEAT_INIT_MID_END | CPU_FEAT_S3_LATE_RESTORE_END), - IsL3FeatureEnabled, - InitializeL3Feature -}; diff --git a/src/vendorcode/amd/agesa/f12/Proc/CPU/Feature/cpuL3Features.h b/src/vendorcode/amd/agesa/f12/Proc/CPU/Feature/cpuL3Features.h deleted file mode 100644 index f6f8d7d1a4..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/CPU/Feature/cpuL3Features.h +++ /dev/null @@ -1,358 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * AMD CPU L3 Features Initialization functions. - * - * Contains code that declares the AGESA CPU L3 dependent feature related APIs - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: CPU/Feature - * @e \$Revision: 49216 $ @e \$Date: 2011-03-19 11:34:39 +0800 (Sat, 19 Mar 2011) $ - * - */ -/* - ****************************************************************************** - * - * Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - ****************************************************************************** - */ - -#ifndef _CPU_L3_FEATURES_H_ -#define _CPU_L3_FEATURES_H_ - -#include "Filecode.h" -/*---------------------------------------------------------------------------------------- - * M I X E D (Definitions And Macros / Typedefs, Structures, Enums) - *---------------------------------------------------------------------------------------- - */ -// Forward declaration needed for multi-structure mutual references -AGESA_FORWARD_DECLARATION (L3_FEATURE_FAMILY_SERVICES); - -/*---------------------------------------------------------------------------------------- - * D E F I N I T I O N S A N D M A C R O S - *---------------------------------------------------------------------------------------- - */ -#define AP_LATE_TASK_DISABLE_CACHE (0x00000000 | PROC_CPU_FEATURE_CPUL3FEATURES_FILECODE) -#define AP_LATE_TASK_ENABLE_CACHE (0x00010000 | PROC_CPU_FEATURE_CPUL3FEATURES_FILECODE) - -/*---------------------------------------------------------------------------------------- - * T Y P E D E F S A N D S T R U C T U R E S - *---------------------------------------------------------------------------------------- - */ -#define L3_SCRUBBER_CONTEXT_ARRAY_SIZE 4 - -/*---------------------------------------------------------------------------------------*/ -/** - * Family specific call to check if L3 Features are supported. - * - * @param[in] L3FeatureServices L3 Feature family services. - * @param[in] Socket Processor socket to check. - * @param[in] StdHeader Config Handle for library, services. - * - * @retval TRUE L3 dependent features are supported - * @retval FALSE L3 dependent features are not supported - * - */ -typedef BOOLEAN F_L3_FEATURE_IS_SUPPORTED ( - IN L3_FEATURE_FAMILY_SERVICES *L3FeatureServices, - IN UINT32 Socket, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -/// Reference to a Method. -typedef F_L3_FEATURE_IS_SUPPORTED *PF_L3_FEATURE_IS_SUPPORTED; - -/*---------------------------------------------------------------------------------------*/ -/** - * Family specific hook before L3 features are initialized. - * - * @param[in] L3FeatureServices L3 Feature family services. - * @param[in] Socket Processor socket to check. - * @param[in] StdHeader Config Handle for library, services. - * - */ -typedef VOID F_L3_FEATURE_BEFORE_INIT ( - IN L3_FEATURE_FAMILY_SERVICES *L3FeatureServices, - IN UINT32 Socket, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -/// Reference to a Method. -typedef F_L3_FEATURE_BEFORE_INIT *PF_L3_FEATURE_BEFORE_INIT; - -/*---------------------------------------------------------------------------------------*/ -/** - * Family specific call to disable cache. - * - * @param[in] L3FeatureServices L3 Feature family services. - * @param[in] HtAssistEnabled Indicates whether Ht Assist is enabled. - * @param[in] StdHeader Config Handle for library, services. - * - */ -typedef VOID F_L3_FEATURE_DISABLE_CACHE ( - IN L3_FEATURE_FAMILY_SERVICES *L3FeatureServices, - IN BOOLEAN HtAssistEnabled, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -/// Reference to a Method. -typedef F_L3_FEATURE_DISABLE_CACHE *PF_L3_FEATURE_DISABLE_CACHE; - -/*---------------------------------------------------------------------------------------*/ -/** - * Family specific call to disable cache. - * - * @param[in] L3FeatureServices L3 Feature family services. - * @param[in] StdHeader Config Handle for library, services. - * - * @return Family specific error value. - * - */ -typedef VOID F_L3_FEATURE_ENABLE_CACHE ( - IN L3_FEATURE_FAMILY_SERVICES *L3FeatureServices, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -/// Reference to a Method. -typedef F_L3_FEATURE_ENABLE_CACHE *PF_L3_FEATURE_ENABLE_CACHE; - -/*---------------------------------------------------------------------------------------*/ -/** - * Family specific call to Initialize L3 Features - * - * @param[in] L3FeatureServices L3 Feature family services. - * @param[in] Socket Processor socket to enable. - * @param[in] StdHeader Config Handle for library, services. - * - */ -typedef VOID F_L3_FEATURE_INIT ( - IN L3_FEATURE_FAMILY_SERVICES *L3FeatureServices, - IN UINT32 Socket, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -/// Reference to a Method. -typedef F_L3_FEATURE_INIT *PF_L3_FEATURE_INIT; - -/*---------------------------------------------------------------------------------------*/ -/** - * Family specific hook after L3 Features are initialized. - * - * @param[in] L3FeatureServices L3 Features family services. - * @param[in] Socket Processor socket to check. - * @param[in] StdHeader Config Handle for library, services. - * - */ -typedef VOID F_L3_FEATURE_AFTER_INIT ( - IN L3_FEATURE_FAMILY_SERVICES *L3FeatureServices, - IN UINT32 Socket, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -/// Reference to a Method. -typedef F_L3_FEATURE_AFTER_INIT *PF_L3_FEATURE_AFTER_INIT; - -/*---------------------------------------------------------------------------------------*/ -/** - * Family specific call to save the L3 scrubber. - * - * @param[in] L3FeatureServices L3 Feature family services. - * @param[in] Socket Processor socket to check. - * @param[in] ScrubSettings Location to store current L3 scrubber settings. - * @param[in] StdHeader Config Handle for library, services. - * - */ -typedef VOID F_L3_FEATURE_GET_L3_SCRUB_CTRL ( - IN L3_FEATURE_FAMILY_SERVICES *L3FeatureServices, - IN UINT32 Socket, - IN UINT32 ScrubSettings[L3_SCRUBBER_CONTEXT_ARRAY_SIZE], - IN AMD_CONFIG_PARAMS *StdHeader - ); - -/// Reference to a Method. -typedef F_L3_FEATURE_GET_L3_SCRUB_CTRL *PF_L3_FEATURE_GET_L3_SCRUB_CTRL; - -/*---------------------------------------------------------------------------------------*/ -/** - * Family specific call to restore the L3 scrubber. - * - * @param[in] L3FeatureServices L3 Feature family services. - * @param[in] Socket Processor socket to check. - * @param[in] ScrubSettings Contains L3 scrubber settings to restore. - * @param[in] StdHeader Config Handle for library, services. - * - */ -typedef VOID F_L3_FEATURE_SET_L3_SCRUB_CTRL ( - IN L3_FEATURE_FAMILY_SERVICES *L3FeatureServices, - IN UINT32 Socket, - IN UINT32 ScrubSettings[L3_SCRUBBER_CONTEXT_ARRAY_SIZE], - IN AMD_CONFIG_PARAMS *StdHeader - ); - -/// Reference to a Method. -typedef F_L3_FEATURE_SET_L3_SCRUB_CTRL *PF_L3_FEATURE_SET_L3_SCRUB_CTRL; - -/*---------------------------------------------------------------------------------------*/ -/** - * Family specific call to check if HT Assist is supported. - * - * @param[in] L3FeatureServices L3 Feature family services. - * @param[in] PlatformConfig Contains the runtime modifiable feature input data - * @param[in] StdHeader Config Handle for library, services. - * - * @retval TRUE HT Assist is supported. - * @retval FALSE HT Assist is not supported. - * - */ -typedef BOOLEAN F_HT_ASSIST_IS_SUPPORTED ( - IN L3_FEATURE_FAMILY_SERVICES *L3FeatureServices, - IN PLATFORM_CONFIGURATION *PlatformConfig, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -/// Reference to a Method. -typedef F_HT_ASSIST_IS_SUPPORTED *PF_HT_ASSIST_IS_SUPPORTED; - -/*---------------------------------------------------------------------------------------*/ -/** - * Family specific call to Initialize HT Assist - * - * @param[in] L3FeatureServices L3 Features family services. - * @param[in] Socket Processor socket to enable. - * @param[in] StdHeader Config Handle for library, services. - * - */ -typedef VOID F_HT_ASSIST_INIT ( - IN L3_FEATURE_FAMILY_SERVICES *L3FeatureServices, - IN UINT32 Socket, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -/// Reference to a Method. -typedef F_HT_ASSIST_INIT *PF_HT_ASSIST_INIT; - -/*---------------------------------------------------------------------------------------*/ -/** - * Family specific call to provide non_optimal HT Assist support - * - * @param[in] L3FeatureServices L3 Feature family services. - * @param[in] Socket Processor socket to check. - * @param[in] StdHeader Config Handle for library, services. - * - * @return TRUE The system may be running with non-optimal settings. - * @return FALSE The system may is running optimally. - * - */ -typedef BOOLEAN F_HT_ASSIST_IS_NONOPTIMAL ( - IN L3_FEATURE_FAMILY_SERVICES *L3FeatureServices, - IN UINT32 Socket, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -/// Reference to a Method. -typedef F_HT_ASSIST_IS_NONOPTIMAL *PF_HT_ASSIST_IS_NONOPTIMAL; - -/*---------------------------------------------------------------------------------------*/ -/** - * Family specific call to check if ATM Mode is supported. - * - * @param[in] L3FeatureServices L3 Features family services. - * @param[in] PlatformConfig Contains the runtime modifiable feature input data. - * @param[in] StdHeader Config Handle for library, services. - * - * @retval TRUE ATM Mode is supported. - * @retval FALSE ATM Mode is not supported. - * - */ -typedef BOOLEAN F_ATM_MODE_IS_SUPPORTED ( - IN L3_FEATURE_FAMILY_SERVICES *L3FeatureServices, - IN PLATFORM_CONFIGURATION *PlatformConfig, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -/// Reference to a Method. -typedef F_ATM_MODE_IS_SUPPORTED *PF_ATM_MODE_IS_SUPPORTED; - -/*---------------------------------------------------------------------------------------*/ -/** - * Family specific call to Initialize ATM mode - * - * @param[in] L3FeatureServices L3 Features family services. - * @param[in] Socket Processor socket to enable. - * @param[in] StdHeader Config Handle for library, services. - * - */ -typedef VOID F_ATM_MODE_INIT ( - IN L3_FEATURE_FAMILY_SERVICES *L3FeatureServices, - IN UINT32 Socket, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -/// Reference to a Method. -typedef F_ATM_MODE_INIT *PF_ATM_MODE_INIT; - -/** - * Provide the interface to the L3 dependent features Family Specific Services. - * - * Use the methods or data in this struct to adapt the feature code to a specific cpu family or model (or stepping!). - * Each supported Family must provide an implementation for all methods in this interface, even if the - * implementation is a CommonReturn(). - */ -struct _L3_FEATURE_FAMILY_SERVICES { - UINT16 Revision; ///< Interface version - // Public Methods. - PF_L3_FEATURE_IS_SUPPORTED IsL3FeatureSupported; ///< Method: Check if L3 dependent features are supported. - PF_L3_FEATURE_GET_L3_SCRUB_CTRL GetL3ScrubCtrl; ///< Method: Save/disable the L3 scrubber. - PF_L3_FEATURE_SET_L3_SCRUB_CTRL SetL3ScrubCtrl; ///< Method: Restore the L3 scrubber. - PF_L3_FEATURE_BEFORE_INIT HookBeforeInit; ///< Method: Hook before enabling L3 dependent features. - PF_L3_FEATURE_AFTER_INIT HookAfterInit; ///< Method: Hook after enabling L3 dependent features. - PF_L3_FEATURE_DISABLE_CACHE HookDisableCache; ///< Method: Core hook just before disabling cache. - PF_L3_FEATURE_ENABLE_CACHE HookEnableCache; ///< Method: Core hook just after enabling cache. - PF_HT_ASSIST_IS_SUPPORTED IsHtAssistSupported; ///< Method: Check if HT Assist is supported. - PF_HT_ASSIST_INIT HtAssistInit; ///< Method: Enable HT Assist. - PF_HT_ASSIST_IS_NONOPTIMAL IsNonOptimalConfig; ///< Method: Check if HT Assist is running optimally. - PF_ATM_MODE_IS_SUPPORTED IsAtmModeSupported; ///< Method: Check if ATM Mode is supported. - PF_ATM_MODE_INIT AtmModeInit; ///< Method: Enable ATM Mode. -}; - - -/*---------------------------------------------------------------------------------------- - * F U N C T I O N S P R O T O T Y P E - *---------------------------------------------------------------------------------------- - */ -AGESA_STATUS -DisableAllCaches ( - IN AP_EXE_PARAMS *ApExeParams - ); - -AGESA_STATUS -EnableAllCaches ( - IN AP_EXE_PARAMS *ApExeParams - ); - -#endif // _CPU_L3_FEATURES_H_ diff --git a/src/vendorcode/amd/agesa/f12/Proc/CPU/Feature/cpuLowPwrPstate.c b/src/vendorcode/amd/agesa/f12/Proc/CPU/Feature/cpuLowPwrPstate.c deleted file mode 100644 index 310d152372..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/CPU/Feature/cpuLowPwrPstate.c +++ /dev/null @@ -1,220 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * AMD AGESA CPU create low power P-state for PROCHOT_L throttling support code. - * - * Contains code that declares the AGESA CPU low power P-state related APIs - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: CPU/Feature - * @e \$Revision: 49029 $ @e \$Date: 2011-03-16 09:55:06 +0800 (Wed, 16 Mar 2011) $ - * - */ -/* - ****************************************************************************** - * - * Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - ****************************************************************************** - */ - -/*---------------------------------------------------------------------------------------- - * M O D U L E S U S E D - *---------------------------------------------------------------------------------------- - */ -#include "AGESA.h" -#include "GeneralServices.h" -#include "cpuFamilyTranslation.h" -#include "cpuApicUtilities.h" -#include "OptionMultiSocket.h" -#include "cpuRegisters.h" -#include "cpuApicUtilities.h" -#include "cpuFeatures.h" -#include "cpuLowPwrPstate.h" -#include "Filecode.h" -CODE_GROUP (G1_PEICC) -RDATA_GROUP (G1_PEICC) - -#define FILECODE PROC_CPU_FEATURE_CPULOWPWRPSTATE_FILECODE - -/*---------------------------------------------------------------------------------------- - * D E F I N I T I O N S A N D M A C R O S - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------- - * T Y P E D E F S A N D S T R U C T U R E S - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------- - * P R O T O T Y P E S O F L O C A L F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ -VOID -STATIC -EnableLowPwrPstateOnSocket ( - IN VOID *PlatformConfig, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -/*---------------------------------------------------------------------------------------- - * E X P O R T E D F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ -extern CPU_FAMILY_SUPPORT_TABLE LowPwrPstateFamilyServiceTable; -//extern OPTION_MULTISOCKET_CONFIGURATION OptionMultiSocketConfiguration; - -/*---------------------------------------------------------------------------------------*/ -/** - * Should Low Power P-state be enabled - * If all processors support Low Power P-state, reture TRUE, otherwise reture FALSE - * - * @param[in] PlatformConfig Contains the runtime modifiable feature input data. - * @param[in] StdHeader Config Handle for library, services. - * - * @retval TRUE Low Power P-state is supported. - * @retval FALSE Low Power P-state cannot be enabled. - * - */ -BOOLEAN -STATIC -IsLowPwrPstateFeatureSupported ( - IN PLATFORM_CONFIGURATION *PlatformConfig, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - UINT32 Socket; - BOOLEAN IsSupported; - LOW_PWR_PSTATE_FAMILY_SERVICES *FamilyServices; - - IsSupported = FALSE; - for (Socket = 0; Socket < GetPlatformNumberOfSockets (); Socket++) { - if (IsProcessorPresent (Socket, StdHeader)) { - GetFeatureServicesOfSocket (&LowPwrPstateFamilyServiceTable, Socket, (const VOID **)&FamilyServices, StdHeader); - if (FamilyServices != NULL) { - if (FamilyServices->IsLowPwrPstateSupported (FamilyServices, PlatformConfig, Socket, StdHeader)) { - IsSupported = TRUE; - } else { - IsSupported = FALSE; - break; - } - } else { - IsSupported = FALSE; - break; - } - } - } - IDS_OPTION_HOOK (IDS_LOW_POWER_PSTATE, &IsSupported, StdHeader); - return IsSupported; -} - -/*---------------------------------------------------------------------------------------*/ -/** - * Enable low power P-state - * - * @param[in] EntryPoint Timepoint designator. - * @param[in] PlatformConfig Contains the runtime modifiable feature input data. - * @param[in] StdHeader Config Handle for library, services. - * - * @retval AGESA_SUCCESS Always succeeds. - * - */ -AGESA_STATUS -STATIC -InitializeLowPwrPstateFeature ( - IN UINT64 EntryPoint, - IN PLATFORM_CONFIGURATION *PlatformConfig, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - UINT32 BscSocket; - UINT32 Ignored; - UINT32 BscCoreNum; - UINT32 Core; - UINT32 Socket; - UINT32 NumberOfSockets; - UINT32 NumberOfCores; - AP_TASK TaskPtr; - AGESA_STATUS IgnoredSts; - - IDS_HDT_CONSOLE (CPU_TRACE, " Low pwr P-state is enabled\n"); - - IdentifyCore (StdHeader, &BscSocket, &Ignored, &BscCoreNum, &IgnoredSts); - NumberOfSockets = GetPlatformNumberOfSockets (); - - TaskPtr.FuncAddress.PfApTaskI = EnableLowPwrPstateOnSocket; - TaskPtr.DataTransfer.DataSizeInDwords = 2; - TaskPtr.DataTransfer.DataPtr = PlatformConfig; - TaskPtr.DataTransfer.DataTransferFlags = 0; - TaskPtr.ExeFlags = WAIT_FOR_CORE; - - for (Socket = 0; Socket < NumberOfSockets; Socket++) { - if (GetActiveCoresInGivenSocket (Socket, &NumberOfCores, StdHeader)) { - for (Core = 0; Core < NumberOfCores; Core++) { - if ((Socket != BscSocket) || (Core != BscCoreNum)) { - ApUtilRunCodeOnSocketCore ((UINT8) Socket, (UINT8) Core, &TaskPtr, StdHeader); - } - } - } - } - - EnableLowPwrPstateOnSocket (PlatformConfig, StdHeader); - return AGESA_SUCCESS; -} - -/*---------------------------------------------------------------------------------------*/ -/** - * 'Local' core 0 task to enable low power P-state - * - * @param[in] PlatformConfig Contains the runtime modifiable feature input data. - * @param[in] StdHeader Config Handle for library, services. - * - */ -VOID -STATIC -EnableLowPwrPstateOnSocket ( - IN VOID *PlatformConfig, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - LOW_PWR_PSTATE_FAMILY_SERVICES *FamilyServices; - - GetFeatureServicesOfCurrentCore (&LowPwrPstateFamilyServiceTable, (const VOID **)&FamilyServices, StdHeader); - FamilyServices->EnableLowPwrPstate (FamilyServices, - PlatformConfig, - StdHeader); -} - - -CONST CPU_FEATURE_DESCRIPTOR ROMDATA CpuFeatureLowPwrPstate = -{ - LowPwrPstate, - CPU_FEAT_BEFORE_RELINQUISH_AP, - IsLowPwrPstateFeatureSupported, - InitializeLowPwrPstateFeature -}; diff --git a/src/vendorcode/amd/agesa/f12/Proc/CPU/Feature/cpuLowPwrPstate.h b/src/vendorcode/amd/agesa/f12/Proc/CPU/Feature/cpuLowPwrPstate.h deleted file mode 100644 index c06e169789..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/CPU/Feature/cpuLowPwrPstate.h +++ /dev/null @@ -1,129 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * AMD AGESA CPU create low power P-state for PROCHOT_L throttling Functions declarations. - * - * Contains code that declares the AGESA CPU low power P-state related APIs - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: CPU/Feature - * @e \$Revision: 49029 $ @e \$Date: 2011-03-16 09:55:06 +0800 (Wed, 16 Mar 2011) $ - * - */ -/* - ****************************************************************************** - * - * Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - ****************************************************************************** - */ - -#ifndef _CPU_LOW_PWR_PSTATE_H_ -#define _CPU_LOW_PWR_PSTATE_H_ - -/*---------------------------------------------------------------------------------------- - * M I X E D (Definitions And Macros / Typedefs, Structures, Enums) - *---------------------------------------------------------------------------------------- - */ -// Forward declaration needed for multi-structure mutual references -AGESA_FORWARD_DECLARATION (LOW_PWR_PSTATE_FAMILY_SERVICES); - -/*---------------------------------------------------------------------------------------- - * D E F I N I T I O N S A N D M A C R O S - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------- - * T Y P E D E F S A N D S T R U C T U R E S - *---------------------------------------------------------------------------------------- - */ - - -/*---------------------------------------------------------------------------------------*/ -/** - * Family specific call to check if Low Power P-state is supported. - * - * @param[in] LowPwrPstateService Low Power P-state services. - * @param[in] PlatformConfig Contains the runtime modifiable feature input data. - * @param[in] Socket Zero-based socket number. - * @param[in] StdHeader Config Handle for library, services. - * - * @retval TRUE Low Power P-state is supported. - * @retval FALSE Low Power P-state is not supported. - * - */ -typedef BOOLEAN F_LOW_PWR_PSTATE_IS_SUPPORTED ( - IN LOW_PWR_PSTATE_FAMILY_SERVICES *LowPwrPstateService, - IN PLATFORM_CONFIGURATION *PlatformConfig, - IN UINT32 Socket, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -/// Reference to a Method. -typedef F_LOW_PWR_PSTATE_IS_SUPPORTED *PF_LOW_PWR_PSTATE_IS_SUPPORTED; - -/*---------------------------------------------------------------------------------------*/ -/** - * Family specific call to enable Low Power P-state - * - * @param[in] LowPwrPstateService Low Power P-state services. - * @param[in] PlatformConfig Contains the runtime modifiable feature input data. - * @param[in] StdHeader Config Handle for library, services. - * - * @return Family specific error value. - * - */ -typedef AGESA_STATUS F_LOW_PWR_PSTATE_INIT ( - IN LOW_PWR_PSTATE_FAMILY_SERVICES *LowPwrPstateService, - IN PLATFORM_CONFIGURATION *PlatformConfig, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -/// Reference to a Method. -typedef F_LOW_PWR_PSTATE_INIT *PF_LOW_PWR_PSTATE_INIT; - -/** - * Provide the interface to the Low Power P-state Family Specific Services. - * - * Use the methods or data in this struct to adapt the feature code to a specific cpu family or model (or stepping!). - * Each supported Family must provide an implementation for all methods in this interface, even if the - * implementation is a CommonReturn(). - */ -struct _LOW_PWR_PSTATE_FAMILY_SERVICES { - UINT16 Revision; ///< Interface version - // Public Methods. - PF_LOW_PWR_PSTATE_IS_SUPPORTED IsLowPwrPstateSupported; ///< Method: Family specific call to check if Low Power P-state is supported. - PF_LOW_PWR_PSTATE_INIT EnableLowPwrPstate; ///< Method: Family specific call to enable Low Power P-state. -}; - - -/*---------------------------------------------------------------------------------------- - * F U N C T I O N S P R O T O T Y P E - *---------------------------------------------------------------------------------------- - */ - -#endif // _CPU_LOW_PWR_PSTATE_H_ diff --git a/src/vendorcode/amd/agesa/f12/Proc/CPU/Feature/cpuMsgBasedC1e.c b/src/vendorcode/amd/agesa/f12/Proc/CPU/Feature/cpuMsgBasedC1e.c deleted file mode 100644 index ab1a5ae265..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/CPU/Feature/cpuMsgBasedC1e.c +++ /dev/null @@ -1,211 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * AMD AGESA CPU Message-based C1e feature support code. - * - * Contains code that declares the AGESA CPU C1e related APIs - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: CPU/Feature - * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $ - * - */ -/* - ****************************************************************************** - * - * Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - ****************************************************************************** - */ - -/*---------------------------------------------------------------------------------------- - * M O D U L E S U S E D - *---------------------------------------------------------------------------------------- - */ -#include "AGESA.h" -#include "amdlib.h" -#include "Ids.h" -#include "OptionMultiSocket.h" -#include "cpuRegisters.h" -#include "cpuApicUtilities.h" -#include "cpuServices.h" -#include "cpuFamilyTranslation.h" -#include "cpuFeatures.h" -#include "cpuMsgBasedC1e.h" -#include "Filecode.h" -CODE_GROUP (G1_PEICC) -RDATA_GROUP (G1_PEICC) - -#define FILECODE PROC_CPU_FEATURE_CPUMSGBASEDC1E_FILECODE -/*---------------------------------------------------------------------------------------- - * D E F I N I T I O N S A N D M A C R O S - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------- - * T Y P E D E F S A N D S T R U C T U R E S - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------- - * P R O T O T Y P E S O F L O C A L F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ -VOID -STATIC -EnableMsgC1eOnSocket ( - IN VOID *EntryPoint, - IN AMD_CONFIG_PARAMS *StdHeader, - IN AMD_CPU_EARLY_PARAMS *CpuEarlyParams - ); - -/*---------------------------------------------------------------------------------------- - * E X P O R T E D F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ -extern CPU_FAMILY_SUPPORT_TABLE MsgBasedC1eFamilyServiceTable; -extern OPTION_MULTISOCKET_CONFIGURATION OptionMultiSocketConfiguration; - -/*---------------------------------------------------------------------------------------*/ -/** - * Should message-based C1e be enabled - * - * @param[in] PlatformConfig Contains the runtime modifiable feature input data. - * @param[in] StdHeader Config Handle for library, services. - * - * @retval TRUE Message-based C1e is supported. - * @retval FALSE Message-based C1e cannot be enabled. - * - */ -BOOLEAN -STATIC -IsMsgBasedC1eFeatureEnabled ( - IN PLATFORM_CONFIGURATION *PlatformConfig, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - BOOLEAN IsEnabled; - UINT32 Socket; - MSG_BASED_C1E_FAMILY_SERVICES *FamilyServices; - - ASSERT (PlatformConfig->C1eMode < MaxC1eMode); - - IsEnabled = FALSE; - if ((PlatformConfig->C1eMode == C1eModeMsgBased) || (PlatformConfig->C1eMode == C1eModeAuto)) { - ASSERT (PlatformConfig->C1ePlatformData < 0x10000); - ASSERT (PlatformConfig->C1ePlatformData != 0); - if ((PlatformConfig->C1ePlatformData != 0) && (PlatformConfig->C1ePlatformData < 0xFFFE)) { - IsEnabled = TRUE; - if (IsNonCoherentHt1 (StdHeader)) { - IsEnabled = FALSE; - } else { - for (Socket = 0; Socket < GetPlatformNumberOfSockets (); Socket++) { - if (IsProcessorPresent (Socket, StdHeader)) { - GetFeatureServicesOfSocket (&MsgBasedC1eFamilyServiceTable, Socket, (const VOID **)&FamilyServices, StdHeader); - if ((FamilyServices == NULL) || !FamilyServices->IsMsgBasedC1eSupported (FamilyServices, Socket, StdHeader)) { - IsEnabled = FALSE; - break; - } - } - } - } - } - } - return IsEnabled; -} - -/*---------------------------------------------------------------------------------------*/ -/** - * Enable Message-based C1e - * - * @param[in] EntryPoint Timepoint designator. - * @param[in] PlatformConfig Contains the runtime modifiable feature input data. - * @param[in] StdHeader Config Handle for library, services. - * - * @return AGESA_SUCCESS Always succeeds. - * - */ -AGESA_STATUS -STATIC -InitializeMsgBasedC1eFeature ( - IN UINT64 EntryPoint, - IN PLATFORM_CONFIGURATION *PlatformConfig, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - AP_TASK TaskPtr; - AMD_CPU_EARLY_PARAMS CpuEarlyParams; - - IDS_HDT_CONSOLE (CPU_TRACE, " MT C1e is enabled\n"); - - if ((EntryPoint != CPU_FEAT_AFTER_PM_INIT) || (IsWarmReset (StdHeader))) { - CpuEarlyParams.PlatformConfig = *PlatformConfig; - - TaskPtr.FuncAddress.PfApTaskIC = EnableMsgC1eOnSocket; - TaskPtr.DataTransfer.DataSizeInDwords = 2; - TaskPtr.DataTransfer.DataPtr = &EntryPoint; - TaskPtr.DataTransfer.DataTransferFlags = 0; - TaskPtr.ExeFlags = PASS_EARLY_PARAMS; - OptionMultiSocketConfiguration.BscRunCodeOnAllSystemCore0s (&TaskPtr, StdHeader, &CpuEarlyParams); - } - return AGESA_SUCCESS; -} - - -/*---------------------------------------------------------------------------------------*/ -/** - * 'Local' core 0 task to enable message-based C1e on it's socket. - * - * @param[in] EntryPoint Timepoint designator. - * @param[in] StdHeader Config Handle for library, services. - * @param[in] CpuEarlyParams Service parameters. - * - */ -VOID -STATIC -EnableMsgC1eOnSocket ( - IN VOID *EntryPoint, - IN AMD_CONFIG_PARAMS *StdHeader, - IN AMD_CPU_EARLY_PARAMS *CpuEarlyParams - ) -{ - MSG_BASED_C1E_FAMILY_SERVICES *FamilyServices; - - GetFeatureServicesOfCurrentCore (&MsgBasedC1eFamilyServiceTable, (const VOID **)&FamilyServices, StdHeader); - FamilyServices->InitializeMsgBasedC1e (FamilyServices, - *((UINT64 *) EntryPoint), - &CpuEarlyParams->PlatformConfig, - StdHeader); -} - -CONST CPU_FEATURE_DESCRIPTOR ROMDATA CpuFeatureMsgBasedC1e = -{ - MsgBasedC1e, - (CPU_FEAT_AFTER_PM_INIT | CPU_FEAT_AFTER_POST_MTRR_SYNC | CPU_FEAT_AFTER_RESUME_MTRR_SYNC), - IsMsgBasedC1eFeatureEnabled, - InitializeMsgBasedC1eFeature -}; diff --git a/src/vendorcode/amd/agesa/f12/Proc/CPU/Feature/cpuMsgBasedC1e.h b/src/vendorcode/amd/agesa/f12/Proc/CPU/Feature/cpuMsgBasedC1e.h deleted file mode 100644 index 76457a907f..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/CPU/Feature/cpuMsgBasedC1e.h +++ /dev/null @@ -1,127 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * AMD AGESA CPU Message-based C1e Functions declarations. - * - * Contains code that declares the AGESA CPU C1e related APIs - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: CPU/Feature - * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $ - * - */ -/* - ****************************************************************************** - * - * Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - ****************************************************************************** - */ - -#ifndef _CPU_MSG_BASED_C1E_H_ -#define _CPU_MSG_BASED_C1E_H_ - -/*---------------------------------------------------------------------------------------- - * M I X E D (Definitions And Macros / Typedefs, Structures, Enums) - *---------------------------------------------------------------------------------------- - */ -// Forward declaration needed for multi-structure mutual references -AGESA_FORWARD_DECLARATION (MSG_BASED_C1E_FAMILY_SERVICES); - -/*---------------------------------------------------------------------------------------- - * D E F I N I T I O N S A N D M A C R O S - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------- - * T Y P E D E F S A N D S T R U C T U R E S - *---------------------------------------------------------------------------------------- - */ -/*---------------------------------------------------------------------------------------*/ -/** - * Family specific call to check if message-based C1e is supported. - * - * @param[in] MsgBasedC1eServices Contains the runtime modifiable feature input data. - * @param[in] Socket Processor socket to check. - * @param[in] StdHeader Config Handle for library, services. - * - * @retval TRUE Message-based C1e is supported. - * @retval FALSE Message-based C1e is not supported. - * - */ -typedef BOOLEAN F_MSG_BASED_C1E_IS_SUPPORTED ( - IN MSG_BASED_C1E_FAMILY_SERVICES *MsgBasedC1eServices, - IN UINT32 Socket, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -/// Reference to a Method. -typedef F_MSG_BASED_C1E_IS_SUPPORTED *PF_MSG_BASED_C1E_IS_SUPPORTED; - -/*---------------------------------------------------------------------------------------*/ -/** - * Family specific call to enable hardware C1e. - * - * @param[in] MsgBasedC1eServices Hardware C1e services. - * @param[in] EntryPoint Timepoint designator. - * @param[in] PlatformConfig Contains the runtime modifiable feature input data. - * @param[in] StdHeader Config Handle for library, services. - * - * @return Family specific error value. - * - */ -typedef AGESA_STATUS F_MSG_BASED_C1E_INIT ( - IN MSG_BASED_C1E_FAMILY_SERVICES *MsgBasedC1eServices, - IN UINT64 EntryPoint, - IN PLATFORM_CONFIGURATION *PlatformConfig, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -/// Reference to a Method. -typedef F_MSG_BASED_C1E_INIT *PF_MSG_BASED_C1E_INIT; - -/** - * Provide the interface to the hardware C1e Family Specific Services. - * - * Use the methods or data in this struct to adapt the feature code to a specific cpu family or model (or stepping!). - * Each supported Family must provide an implementation for all methods in this interface, even if the - * implementation is a CommonReturn(). - */ -struct _MSG_BASED_C1E_FAMILY_SERVICES { - UINT16 Revision; ///< Interface version - // Public Methods. - PF_MSG_BASED_C1E_IS_SUPPORTED IsMsgBasedC1eSupported; ///< Method: Family specific call to check if hardware C1e is supported. - PF_MSG_BASED_C1E_INIT InitializeMsgBasedC1e; ///< Method: Family specific call to enable hardware C1e. -}; - - -/*---------------------------------------------------------------------------------------- - * F U N C T I O N S P R O T O T Y P E - *---------------------------------------------------------------------------------------- - */ - -#endif // _CPU_MSG_BASED_C1E_H_ diff --git a/src/vendorcode/amd/agesa/f12/Proc/CPU/Feature/cpuPstateGather.c b/src/vendorcode/amd/agesa/f12/Proc/CPU/Feature/cpuPstateGather.c deleted file mode 100644 index 5476eace9b..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/CPU/Feature/cpuPstateGather.c +++ /dev/null @@ -1,412 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * AMD CPU Pstate Data Gather Function. - * - * Contains code to collect all the Pstate related information from MSRs, and PCI registers. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: CPU - * @e \$Revision: 45227 $ @e \$Date: 2011-01-14 10:47:29 +0800 (Fri, 14 Jan 2011) $ - * - */ -/***************************************************************************** - * - * Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - ****************************************************************************** - */ - - -/* - *---------------------------------------------------------------------------- - * MODULES USED - * - *---------------------------------------------------------------------------- - */ -#include "AGESA.h" -#include "amdlib.h" -#include "OptionPstate.h" -#include "cpuRegisters.h" -#include "cpuServices.h" -#include "GeneralServices.h" -#include "cpuPostInit.h" -#include "Ids.h" -#include "cpuFamilyTranslation.h" -#include "cpuPstateTables.h" -#include "cpuApicUtilities.h" -#include "cpuFeatures.h" -#include "Filecode.h" -CODE_GROUP (G1_PEICC) -RDATA_GROUP (G1_PEICC) - -#define FILECODE PROC_CPU_FEATURE_CPUPSTATEGATHER_FILECODE - -/*---------------------------------------------------------------------------- - * DEFINITIONS AND MACROS - * - *---------------------------------------------------------------------------- - */ -extern OPTION_PSTATE_POST_CONFIGURATION OptionPstatePostConfiguration; // global user config record -extern CPU_FAMILY_SUPPORT_TABLE PstateFamilyServiceTable; - -/*---------------------------------------------------------------------------- - * TYPEDEFS AND STRUCTURES - * - *---------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------- - * PROTOTYPES OF LOCAL FUNCTIONS - * - *---------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------- - * EXPORTED FUNCTIONS - * - *---------------------------------------------------------------------------- - */ -AGESA_STATUS -PStateGatherStub ( - IN AMD_CONFIG_PARAMS *StdHeader, - IN OUT S_CPU_AMD_PSTATE *PStateStrucPtr - ); - -AGESA_STATUS -PStateGatherMain ( - IN AMD_CONFIG_PARAMS *StdHeader, - IN OUT S_CPU_AMD_PSTATE *PStateStrucPtr - ); - -VOID -PStateGather ( - IN OUT VOID *PStateBuffer, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -/** - *--------------------------------------------------------------------------------------- - * - * PStateGatherData - * - * Description: - * This function will gather PState information from the MSRs and fill up the - * pStateBuf. This buffer will be used by the PState Leveling, and PState Table - * generation code later. - * - * Parameters: - * @param[in] *PlatformConfig - * @param[in, out] *PStateStrucPtr - * @param[in] *StdHeader - * - * @retval AGESA_STATUS - * - *--------------------------------------------------------------------------------------- - **/ -AGESA_STATUS -PStateGatherData ( - IN PLATFORM_CONFIGURATION *PlatformConfig, - IN OUT S_CPU_AMD_PSTATE *PStateStrucPtr, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - - - AGESA_STATUS AgesaStatus; - - AGESA_TESTPOINT (TpProcCpuEntryPstateGather, StdHeader); - AgesaStatus = AGESA_SUCCESS; - - // Gather data for ACPI Tables if ACPI P-States/C-States object generation is enabled. - if ((PlatformConfig->UserOptionPState) || (IsFeatureEnabled (IoCstate, PlatformConfig, StdHeader))) { - AgesaStatus = (*(OptionPstatePostConfiguration.PstateGather)) (StdHeader, PStateStrucPtr); - // Note: Split config struct into PEI/DXE halves. This one is PEI. - } - - return AgesaStatus; -} - -/**-------------------------------------------------------------------------------------- - * - * PStateGatherStub - * - * Description: - * This is the default routine for use when the PState option is NOT requested. - * The option install process will create and fill the transfer vector with - * the address of the proper routine (Main or Stub). The link optimizer will - * strip out of the .DLL the routine that is not used. - * - * Parameters: - * @param[in] *StdHeader - * @param[in, out] *PStateStrucPtr - * - * @retval AGESA_STATUS - * - *--------------------------------------------------------------------------------------- - **/ -AGESA_STATUS -PStateGatherStub ( - IN AMD_CONFIG_PARAMS *StdHeader, - IN OUT S_CPU_AMD_PSTATE *PStateStrucPtr - ) -{ - return AGESA_UNSUPPORTED; -} - -/**-------------------------------------------------------------------------------------- - * - * PStateGatherMain - * - * Description: - * This is the common routine for BSP gathering the Pstate data. - * - * Parameters: - * @param[in] *StdHeader - * @param[in, out] *PStateStrucPtr - * - * @retval AGESA_STATUS - * - *--------------------------------------------------------------------------------------- - **/ -AGESA_STATUS -PStateGatherMain ( - IN AMD_CONFIG_PARAMS *StdHeader, - IN OUT S_CPU_AMD_PSTATE *PStateStrucPtr - ) -{ - AP_TASK TaskPtr; - UINT32 BscSocket; - UINT32 Ignored; - UINT32 PopulatedSockets; - UINT32 NumberOfSockets; - UINT32 Socket; - AGESA_STATUS IgnoredSts; - PSTATE_LEVELING *PStateBufferPtr; - PSTATE_CPU_FAMILY_SERVICES *FamilyServices; - UINT32 MaxState; - UINT8 IgnoredByte; - - ASSERT (IsBsp (StdHeader, &IgnoredSts)); - - FamilyServices = NULL; - GetFeatureServicesOfCurrentCore (&PstateFamilyServiceTable, (const VOID **)&FamilyServices, StdHeader); - ASSERT (FamilyServices != NULL); - - PopulatedSockets = 1; - PStateBufferPtr = PStateStrucPtr->PStateLevelingStruc; - - NumberOfSockets = GetPlatformNumberOfSockets (); - IdentifyCore (StdHeader, &BscSocket, &Ignored, &Ignored, &IgnoredSts); - - PStateStrucPtr->SizeOfBytes = sizeof (S_CPU_AMD_PSTATE); - - MaxState = 0; - FamilyServices->GetPstateMaxState (FamilyServices, &MaxState, &IgnoredByte, StdHeader); - - TaskPtr.FuncAddress.PfApTaskI = PStateGather; - // - // Calculate max buffer size in dwords that need to pass to ap task. - // - TaskPtr.DataTransfer.DataSizeInDwords = (UINT16) ((MaxState + 1) * (SIZE_IN_DWORDS (S_PSTATE_VALUES))); - TaskPtr.ExeFlags = WAIT_FOR_CORE; - TaskPtr.DataTransfer.DataPtr = PStateBufferPtr; - TaskPtr.DataTransfer.DataTransferFlags = DATA_IN_MEMORY; - - // - //Get P-States and fill the PStateBufferPtr for BSP - // - ApUtilTaskOnExecutingCore (&TaskPtr, StdHeader, NULL); - - // - //Calculate next node buffer address - // - PStateBufferPtr->SocketNumber = (UINT8) BscSocket; - MaxState = PStateBufferPtr->PStateCoreStruct[0].PStateMaxValue; - PStateBufferPtr->PStateLevelingSizeOfBytes = (UINT16) (sizeof (PSTATE_LEVELING) + (MaxState + 1) * sizeof (S_PSTATE_VALUES)); - PStateStrucPtr->SizeOfBytes += (MaxState + 1) * sizeof (S_PSTATE_VALUES); - PStateBufferPtr = (PSTATE_LEVELING *) ((UINT8 *) PStateBufferPtr + PStateBufferPtr->PStateLevelingSizeOfBytes); - CpuGetPStateLevelStructure (&PStateBufferPtr, PStateStrucPtr, 1, StdHeader); - // - //Get CPU P-States and fill the PStateBufferPtr for each node(BSC) - // - for (Socket = 0; Socket < NumberOfSockets; Socket++) { - if (Socket != BscSocket) { - if (IsProcessorPresent (Socket, StdHeader)) { - PopulatedSockets++; - LibAmdMemFill (PStateBufferPtr, 0, sizeof (PSTATE_LEVELING), StdHeader); - TaskPtr.DataTransfer.DataPtr = PStateBufferPtr; - ApUtilRunCodeOnSocketCore ((UINT8)Socket, 0, &TaskPtr, StdHeader); - PStateBufferPtr->SocketNumber = (UINT8) Socket; - // - //Calculate next node buffer address - // - MaxState = PStateBufferPtr->PStateCoreStruct[0].PStateMaxValue; - PStateBufferPtr->PStateLevelingSizeOfBytes = (UINT16) (sizeof (PSTATE_LEVELING) + (MaxState + 1) * sizeof (S_PSTATE_VALUES)); - PStateStrucPtr->SizeOfBytes += PStateBufferPtr->PStateLevelingSizeOfBytes; - PStateBufferPtr = (PSTATE_LEVELING *) ((UINT8 *) PStateBufferPtr + PStateBufferPtr->PStateLevelingSizeOfBytes); - } - } - } - PStateStrucPtr->TotalSocketInSystem = PopulatedSockets; - - return AGESA_SUCCESS; -} -/**-------------------------------------------------------------------------------------- - * - * PStateGather - * - * Description: - * This is the common routine run on each BSC for gathering Pstate data. - * - * Parameters: - * @param[in,out] *PStateBuffer - * @param[in] *StdHeader - * - * @retval VOID - * - *--------------------------------------------------------------------------------------- - **/ -VOID -PStateGather ( - IN OUT VOID *PStateBuffer, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - UINT32 k; - UINT32 IddVal; - UINT32 IddDiv; - UINT32 NodeNum; - UINT32 CoreNum; - UINT32 TempVar_c; - UINT32 TotalEnabledPStates; - UINT32 SwPstate; - UINT8 BoostStates; - PCI_ADDR PciAddress; - PSTATE_LEVELING *PStateBufferPtr; - BOOLEAN PStateEnabled; - PSTATE_CPU_FAMILY_SERVICES *FamilyServices; - UINT32 Socket; - AGESA_STATUS IgnoredSts; - CPUID_DATA CpuId; - - PStateBufferPtr = (PSTATE_LEVELING *) PStateBuffer; - TotalEnabledPStates = 0; - FamilyServices = NULL; - PStateEnabled = FALSE; - - GetFeatureServicesOfCurrentCore (&PstateFamilyServiceTable, (const VOID **)&FamilyServices, StdHeader); - ASSERT (FamilyServices != NULL); - - // - /// Sockets number: code looking at PStateBufferPtr->TotalCoresInNode - /// needs to know it is Processor (or socket) core count and NOT a Node Core count. - GetActiveCoresInCurrentSocket (&CoreNum, StdHeader); - PStateBufferPtr->TotalCoresInNode = (UINT8) CoreNum; - - // - // Assume current CoreNum always zero.(BSC) - // - GetCurrentNodeAndCore (&NodeNum, &CoreNum, StdHeader); - - PStateBufferPtr->CreateAcpiTables = 1; - - // - // We need to know the max pstate state in this socket. - // - FamilyServices->GetPstateMaxState (FamilyServices, &TempVar_c, &BoostStates, StdHeader); - PStateBufferPtr->PStateCoreStruct[0].PStateMaxValue = (UINT8) TempVar_c; - PStateBufferPtr->PStateCoreStruct[0].NumberOfBoostedStates = BoostStates; - - for (k = 0; k <= TempVar_c; k++) { - // Check if PState is enabled - FamilyServices->GetPstateRegisterInfo ( FamilyServices, - k, - &PStateEnabled, - &IddVal, - &IddDiv, - &SwPstate, - StdHeader); - - LibAmdMemFill (&(PStateBufferPtr->PStateCoreStruct[0].PStateStruct[k]), 0, sizeof (S_PSTATE_VALUES), StdHeader); - - if (PStateEnabled) { - FamilyServices->GetPstateFrequency ( - FamilyServices, - (UINT8) k, - &(PStateBufferPtr->PStateCoreStruct[0].PStateStruct[k].CoreFreq), - StdHeader); - - FamilyServices->GetPstatePower ( - FamilyServices, - (UINT8) k, - &(PStateBufferPtr->PStateCoreStruct[0].PStateStruct[k].Power), - StdHeader); - - PStateBufferPtr->PStateCoreStruct[0].PStateStruct[k].IddValue = IddVal; - PStateBufferPtr->PStateCoreStruct[0].PStateStruct[k].IddDiv = IddDiv; - PStateBufferPtr->PStateCoreStruct[0].PStateStruct[k].SwPstateNumber = SwPstate; - - PStateBufferPtr->PStateCoreStruct[0].PStateStruct[k].PStateEnable = 1; - TotalEnabledPStates++; - } - } // for (k = 0; k < MPPSTATE_MAXIMUM_STATES; k++) - - // Don't create ACPI Tables if there is one or less than one PState is enabled - if (TotalEnabledPStates <= 1) { - PStateBufferPtr[0].CreateAcpiTables = 0; - } - - //--------------------Check Again-------------------------------- - - IdentifyCore (StdHeader, &Socket, &NodeNum, &CoreNum, &IgnoredSts); - // Get the PCI address of internal die 0 as it is the only die programmed. - GetPciAddress (StdHeader, Socket, 0, &PciAddress, &IgnoredSts); - PciAddress.Address.Function = FUNC_3; - PciAddress.Address.Register = NORTH_BRIDGE_CAPABILITIES_REG; - TempVar_c = 0; - LibAmdPciRead (AccessWidth32, PciAddress, &TempVar_c, StdHeader); - PStateBufferPtr->PStateCoreStruct[0].HtcCapable = - (UINT8) ((TempVar_c & 0x00000400) >> 10); // Bit 10 - - TempVar_c = 0; - PciAddress.Address.Register = HARDWARE_THERMAL_CTRL_REG; - LibAmdPciRead (AccessWidth32, PciAddress, &TempVar_c, StdHeader); - PStateBufferPtr->PStateCoreStruct[0].HtcPstateLimit = - (UINT8) ((TempVar_c & 0x70000000) >> 28); // Bits 30:28 - - // Get LocalApicId from CPUID Fn0000_0001_EBX - LibAmdCpuidRead (AMD_CPUID_APICID_LPC_BID, &CpuId, StdHeader); - PStateBufferPtr->PStateCoreStruct[0].LocalApicId = (UINT8) ((CpuId.EBX_Reg & 0xFF000000) >> 24); -} - - -/*---------------------------------------------------------------------------- - * LOCAL FUNCTIONS - * - *---------------------------------------------------------------------------- - */ diff --git a/src/vendorcode/amd/agesa/f12/Proc/CPU/Feature/cpuPstateLeveling.c b/src/vendorcode/amd/agesa/f12/Proc/CPU/Feature/cpuPstateLeveling.c deleted file mode 100644 index c036deefb7..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/CPU/Feature/cpuPstateLeveling.c +++ /dev/null @@ -1,1096 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * AMD CPU Pstate Leveling Function. - * - * Contains code to level the Pstates in a multi-socket system - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: CPU - * @e \$Revision: 44702 $ @e \$Date: 2011-01-05 06:54:00 +0800 (Wed, 05 Jan 2011) $ - * - */ -/***************************************************************************** - * - * Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - ****************************************************************************** - *---------------------------------------------------------------------------- - */ - - -/* - *---------------------------------------------------------------------------- - * MODULES USED - * - *---------------------------------------------------------------------------- - */ -#include "AGESA.h" -#include "amdlib.h" -#include "OptionPstate.h" -#include "cpuLateInit.h" -#include "cpuRegisters.h" -#include "cpuPostInit.h" -#include "Ids.h" -#include "cpuFamilyTranslation.h" -#include "cpuPstateTables.h" -#include "cpuApicUtilities.h" -#include "cpuServices.h" -#include "GeneralServices.h" -#include "Filecode.h" -CODE_GROUP (G1_PEICC) -RDATA_GROUP (G1_PEICC) - -#define FILECODE PROC_CPU_FEATURE_CPUPSTATELEVELING_FILECODE - -/*---------------------------------------------------------------------------- - * DEFINITIONS AND MACROS - * - *---------------------------------------------------------------------------- - */ -extern OPTION_PSTATE_POST_CONFIGURATION OptionPstatePostConfiguration; // global user config record -extern CPU_FAMILY_SUPPORT_TABLE PstateFamilyServiceTable; - -/*---------------------------------------------------------------------------- - * TYPEDEFS AND STRUCTURES - * - *---------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------- - * PROTOTYPES OF LOCAL FUNCTIONS - * - *---------------------------------------------------------------------------- - */ -AGESA_STATUS -PutAllCoreInPState0 ( - IN OUT PSTATE_LEVELING *PStateBufferPtr, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -AGESA_STATUS -StartPstateMsrModify ( - IN S_CPU_AMD_PSTATE *CpuAmdPState, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -VOID -STATIC -PutCoreInPState0 ( - IN VOID *PStateBuffer, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -AGESA_STATUS -PStateLevelingStub ( - IN OUT S_CPU_AMD_PSTATE *PStateStrucPtr, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -AGESA_STATUS -PStateLevelingMain ( - IN OUT S_CPU_AMD_PSTATE *PStateStrucPtr, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -VOID -CorePstateRegModify ( - IN VOID *CpuAmdPState, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -/** - *--------------------------------------------------------------------------------------- - * - * PStateLeveling - * - * Description: - * This function will populate the PStateBuffer, after doing the PState Leveling - * Note: This function should be called for every core in the system. - * - * Parameters: - * @param[in,out] *PStateStrucPtr - * @param[in] *StdHeader - * - * @retval AGESA_STATUS - * - *--------------------------------------------------------------------------------------- - **/ -AGESA_STATUS -PStateLeveling ( - IN OUT S_CPU_AMD_PSTATE *PStateStrucPtr, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - AGESA_TESTPOINT (TpProcCpuEntryPstateLeveling, StdHeader); - return ((*(OptionPstatePostConfiguration.PstateLeveling)) (PStateStrucPtr, StdHeader)); - // Note: Split config struct into PEI/DXE halves. This one is PEI. -} - -/**-------------------------------------------------------------------------------------- - * - * PStateLevelingStub - * - * Description: - * This is the default routine for use when the PState option is NOT requested. - * The option install process will create and fill the transfer vector with - * the address of the proper routine (Main or Stub). The link optimizer will - * strip out of the .DLL the routine that is not used. - * - * Parameters: - * @param[in,out] *PStateStrucPtr - * @param[in] *StdHeader - * - * @retval AGESA_STATUS - * - *--------------------------------------------------------------------------------------- - **/ -AGESA_STATUS -PStateLevelingStub ( - IN OUT S_CPU_AMD_PSTATE *PStateStrucPtr, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - return AGESA_UNSUPPORTED; -} - -/**-------------------------------------------------------------------------------------- - * - * PStateLevelingMain - * - * Description: - * This is the common routine for creating the ACPI information tables. - * - * Parameters: - * @param[in,out] *PStateStrucPtr - * @param[in] *StdHeader - * - * @retval AGESA_STATUS - * - *--------------------------------------------------------------------------------------- - **/ -AGESA_STATUS -PStateLevelingMain ( - IN OUT S_CPU_AMD_PSTATE *PStateStrucPtr, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - UINT32 i; - UINT32 k; - UINT32 m; - UINT32 TotalIterations; - UINT32 LogicalSocketCount; - UINT32 TempVar_a; - UINT32 TempVar_b; - UINT32 TempVar_c; - UINT32 TempVar_d; - UINT32 TempVar_e; - UINT32 TempVar_f; - PCI_ADDR PciAddress; - - UINT32 TempFreqArray[20]; - UINT32 TempPowerArray[20]; - UINT32 TempIddValueArray[20]; - UINT32 TempIddDivArray[20]; - UINT32 TempSocketPiArray[20]; - UINT32 TempSwP0Array[MAX_SOCKETS_SUPPORTED]; - - BOOLEAN TempFlag1; - BOOLEAN TempFlag2; - BOOLEAN TempFlag3; - BOOLEAN TempFlag4; - BOOLEAN AllCoresHaveHtcCapEquToZeroFlag; - BOOLEAN AllCoreHaveMaxOnePStateFlag; - BOOLEAN PstateMaxValEquToPstateHtcLimitFlag; - BOOLEAN AtLeastOneCoreHasPstateHtcLimitEquToOneFlag; - BOOLEAN PstateMaxValMinusHtcPstateLimitLessThan2Flag; - PSTATE_LEVELING *PStateBufferPtr; - PSTATE_LEVELING *PStateBufferPtrTmp = NULL; - UINT32 MaxPstateInNode; - AGESA_STATUS Status; - - TempFlag1 = FALSE; - TempFlag2 = FALSE; - TempFlag3 = FALSE; - TempFlag4 = FALSE; - AllCoresHaveHtcCapEquToZeroFlag = FALSE; - AllCoreHaveMaxOnePStateFlag = FALSE; - PstateMaxValEquToPstateHtcLimitFlag = FALSE; - AtLeastOneCoreHasPstateHtcLimitEquToOneFlag = FALSE; - PstateMaxValMinusHtcPstateLimitLessThan2Flag = FALSE; - PStateBufferPtr = PStateStrucPtr->PStateLevelingStruc; - Status = AGESA_SUCCESS; - - if (PStateBufferPtr[0].SetPState0 == PSTATE_FLAG_1) { - PStateBufferPtr[0].AllCpusHaveIdenticalPStates = TRUE; - PStateBufferPtr[0].InitStruct = 1; - return AGESA_UNSUPPORTED; - } - - LogicalSocketCount = PStateStrucPtr->TotalSocketInSystem; - ASSERT (LogicalSocketCount <= MAX_SOCKETS_SUPPORTED); - - // This section of code will execute only for "core 0" i.e. BSP - // Read P-States of all the cores. - if (PStateBufferPtr[0].InitStruct == 0) { - // Determine 'software' P0 indices for each socket - for (i = 0; i < LogicalSocketCount; i++) { - CpuGetPStateLevelStructure (&PStateBufferPtrTmp, PStateStrucPtr, i, StdHeader); - TempSwP0Array[i] = (UINT32) (PStateBufferPtrTmp->PStateCoreStruct[0].NumberOfBoostedStates); - } - - // Check if core frequency and power are same across all sockets. - TempFlag1 = FALSE; - for (i = 1; i < LogicalSocketCount; i++) { - CpuGetPStateLevelStructure (&PStateBufferPtrTmp, PStateStrucPtr, i, StdHeader); - if ((PStateBufferPtrTmp->PStateCoreStruct[0].PStateMaxValue != PStateBufferPtr[0].PStateCoreStruct[0].PStateMaxValue)) { - TempFlag1 = TRUE; - break; - } - MaxPstateInNode = PStateBufferPtrTmp->PStateCoreStruct[0].PStateMaxValue; - for (k = TempSwP0Array[i]; k <= MaxPstateInNode; k++) { - if ((PStateBufferPtr[0].PStateCoreStruct[0].PStateStruct[k].CoreFreq != - PStateBufferPtrTmp->PStateCoreStruct[0].PStateStruct[k].CoreFreq) || - (PStateBufferPtr[0].PStateCoreStruct[0].PStateStruct[k].Power != - PStateBufferPtrTmp->PStateCoreStruct[0].PStateStruct[k].Power)) { - TempFlag1 = TRUE; - break; // Come out of the inner FOR loop - } - } - if (TempFlag1) { - break; // Come out of the outer FOR loop - } - } - - if (!TempFlag1) { - // No need to do pStateLeveling, or writing to pState MSR registers - // if all CPUs have Identical PStates - PStateBufferPtr[0].AllCpusHaveIdenticalPStates = TRUE; - PStateBufferPtr[0].InitStruct = 1; - PutAllCoreInPState0 (PStateBufferPtr, StdHeader); - return AGESA_UNSUPPORTED; - } else { - PStateBufferPtr[0].AllCpusHaveIdenticalPStates = FALSE; - } - - // 1_b) & 1_c) - TempFlag1 = FALSE; - TempFlag2 = FALSE; - for (i = 0; i < LogicalSocketCount; i++) { - CpuGetPStateLevelStructure (&PStateBufferPtrTmp, PStateStrucPtr, i, StdHeader); - if (PStateBufferPtrTmp->PStateCoreStruct[0].PStateMaxValue == TempSwP0Array[i]) { - TempFlag1 = TRUE; - } else { - TempFlag2 = TRUE; - } - if (PStateBufferPtrTmp->PStateCoreStruct[0].HtcCapable == 0) { - TempFlag3 = TRUE; - } else { - TempFlag4 = TRUE; - } - - if ((PStateBufferPtrTmp->PStateCoreStruct[0].PStateMaxValue - - PStateBufferPtrTmp->PStateCoreStruct[0].HtcPstateLimit) < 2) { - PstateMaxValMinusHtcPstateLimitLessThan2Flag = TRUE; - } - - if (PStateBufferPtrTmp->PStateCoreStruct[0].PStateMaxValue == - PStateBufferPtrTmp->PStateCoreStruct[0].HtcPstateLimit) { - PstateMaxValEquToPstateHtcLimitFlag = TRUE; - } - - if (PStateBufferPtrTmp->PStateCoreStruct[0].HtcPstateLimit == 1) { - AtLeastOneCoreHasPstateHtcLimitEquToOneFlag = TRUE; - } - } - - // Do general setup of flags, that we may use later - // Implementation of (1_b) - if (TempFlag1 && TempFlag2) { - // - //Processors with only one enabled P-state (F3xDC[PstateMaxVal]=000b) cannot be mixed in a system with - //processors with more than one enabled P-state (F3xDC[PstateMaxVal]!=000b). - // - PStateBufferPtr[0].InitStruct = 1; - PStateBufferPtr[0].CreateAcpiTables = 0; - PutAllCoreInPState0 (PStateBufferPtr, StdHeader); - return AGESA_UNSUPPORTED; - } else if (TempFlag1 && !TempFlag2) { - // - //all processors have only 1 enabled P-state - // - AllCoreHaveMaxOnePStateFlag = TRUE; - PStateBufferPtr[0].OnlyOneEnabledPState = TRUE; - } - - // Processors with F3xE8[HTC_CAPABLE] = 1 can not be - // mixed in system with processors with F3xE8[HTC_CAPABLE] = 0. - if (TempFlag3 && TempFlag4) { - PStateBufferPtr[0].InitStruct = 1; - PStateBufferPtr[0].CreateAcpiTables = 0; - PutAllCoreInPState0 (PStateBufferPtr, StdHeader); - return AGESA_UNSUPPORTED; - } - - if (TempFlag3) { - // - //If code run to here means that all processors do not have HTC_CAPABLE. - // - AllCoresHaveHtcCapEquToZeroFlag = TRUE; - } - - //-------------------------------------------------------------------------------- - // S T E P - 2 - //-------------------------------------------------------------------------------- - // Now run the PState Leveling Algorithm which will create mixed CPU P-State - // Tables. - // Follow the algorithm in the latest BKDG - // ------------------------------------------------------------------------------- - // Match P0 CPU COF for all CPU cores to the lowest P0 CPU COF value in the - // coherent fabric, and match P0 power for all CPU cores to the highest P0 power - // value in the coherent fabric. - // 2_a) If all processors have only 1 enabled P-State BIOS must write the - // appropriate CpuFid value resulting from the matched CPU COF to all - // copies of MSRC001_0070[CpuFid], and exit the sequence (No further - // steps are executed) - //-------------------------------------------------------------------------------- - // Identify the lowest P0 Frequency and maximum P0 Power - TempVar_d = PStateBufferPtr[0].PStateCoreStruct[0].PStateStruct[TempSwP0Array[0]].CoreFreq; - TempVar_e = PStateBufferPtr[0].PStateCoreStruct[0].PStateStruct[TempSwP0Array[0]].Power; - TempVar_a = PStateBufferPtr[0].PStateCoreStruct[0].PStateStruct[TempSwP0Array[0]].IddValue; - TempVar_b = PStateBufferPtr[0].PStateCoreStruct[0].PStateStruct[TempSwP0Array[0]].IddDiv; - - for (i = 0; i < LogicalSocketCount; i++) { - CpuGetPStateLevelStructure (&PStateBufferPtrTmp, PStateStrucPtr, i, StdHeader); - if (TempVar_d > PStateBufferPtrTmp->PStateCoreStruct[0].PStateStruct[TempSwP0Array[i]].CoreFreq) { - TempVar_d = PStateBufferPtrTmp->PStateCoreStruct[0].PStateStruct[TempSwP0Array[i]].CoreFreq; - } - - if (TempVar_e < PStateBufferPtrTmp->PStateCoreStruct[0].PStateStruct[TempSwP0Array[i]].Power) { - TempVar_e = PStateBufferPtrTmp->PStateCoreStruct[0].PStateStruct[TempSwP0Array[i]].Power; - TempVar_a = PStateBufferPtrTmp->PStateCoreStruct[0].PStateStruct[TempSwP0Array[i]].IddValue; - TempVar_b = PStateBufferPtrTmp->PStateCoreStruct[0].PStateStruct[TempSwP0Array[i]].IddDiv; - } - } - - // Set P0 Frequency and Power for all CPUs - for (i = 0; i < LogicalSocketCount; i++) { - CpuGetPStateLevelStructure (&PStateBufferPtrTmp, PStateStrucPtr, i, StdHeader); - PStateBufferPtrTmp->PStateCoreStruct[0].PStateStruct[TempSwP0Array[i]].CoreFreq = TempVar_d; - PStateBufferPtrTmp->PStateCoreStruct[0].PStateStruct[TempSwP0Array[i]].Power = TempVar_e; - PStateBufferPtrTmp->PStateCoreStruct[0].PStateStruct[TempSwP0Array[i]].IddValue = TempVar_a; - PStateBufferPtrTmp->PStateCoreStruct[0].PStateStruct[TempSwP0Array[i]].IddDiv = TempVar_b; - } - - // 2_a) - if (!AllCoreHaveMaxOnePStateFlag) { - //-------------------------------------------------------------------------- - // STEP - 3 - //-------------------------------------------------------------------------- - // Match the CPU COF and power for P-states used by HTC. Skip to step 4 - // is any processor reports F3xE8[HTC_Capable] = 0; - // 3_a) Set F3x64[HtcPstateLimit] = 001b and F3x68[StcPstateLimit] = 001b for - // processors with F3x64[HtcPstateLimit] = 000b. - // 3_b) Identify the lowest CPU COF for all processors in the P-state - // pointed to by [The Hardware Thermal Control (HTC) Register] - // F3x64[HtcPstateLimit] - // 3_c) Modify the CPU COF pointed to by [The Hardware Thermal Control - // (HTC) Register] F3x64[HtcPstateLimit] for all processors to the - // previously identified lowest CPU COF value. - // 3_d) Identify the highest power for all processors in the P-state - // pointed to by [The Hardware Thermal Control (HTC) Register] - // F3x64[HtcPstateLimit]. - // 3_e) Modify the power pointed to by [The Hardware Thermal Control (HTC) - // Register] F3x64[HtcPstateLimit] to the previously identified - // highest power value. - if (!AllCoresHaveHtcCapEquToZeroFlag) { - // 3_a) - for (i = 0; i < LogicalSocketCount; i++) { - CpuGetPStateLevelStructure (&PStateBufferPtrTmp, PStateStrucPtr, i, StdHeader); - if (PStateBufferPtrTmp->PStateCoreStruct[0].HtcPstateLimit == 0) { - // To Be Done (Set Htc and Stc PstateLimit values) - // for this CPU (using PCI address space) - for (k = 0; k < (UINT8)GetPlatformNumberOfModules (); k++) { - if (GetPciAddress (StdHeader, PStateBufferPtrTmp->SocketNumber, k, &PciAddress, &Status)) { - // Set F3x64[HtcPstateLimit] = 001b - PciAddress.Address.Function = FUNC_3; - PciAddress.Address.Register = HARDWARE_THERMAL_CTRL_REG; - LibAmdPciRead (AccessWidth32, PciAddress, &TempVar_d, StdHeader); - // Bits 30:28 - TempVar_d = (TempVar_d & 0x8FFFFFFF) | 0x10000000; - LibAmdPciWrite (AccessWidth32, PciAddress, &TempVar_d, StdHeader); - - // Set F3x68[StcPstateLimit] = 001b - PciAddress.Address.Register = SOFTWARE_THERMAL_CTRL_REG; - LibAmdPciRead (AccessWidth32, PciAddress, &TempVar_d, StdHeader); - // Bits 28:30 - TempVar_d = (TempVar_d & 0x8FFFFFFF) | 0x10000000; - LibAmdPciWrite (AccessWidth32, PciAddress, &TempVar_d, StdHeader); - } - } - // Set LocalBuffer - PStateBufferPtrTmp->PStateCoreStruct[0].HtcPstateLimit = 1; - if ((PStateBufferPtrTmp->PStateCoreStruct[0].PStateMaxValue - 1) < 2) { - PstateMaxValMinusHtcPstateLimitLessThan2Flag = TRUE; - } - - if (PStateBufferPtrTmp->PStateCoreStruct[0].PStateMaxValue == 1) { - PstateMaxValEquToPstateHtcLimitFlag = TRUE; - } - } - - if (PStateBufferPtrTmp->PStateCoreStruct[0].HtcPstateLimit == 1) { - AtLeastOneCoreHasPstateHtcLimitEquToOneFlag = TRUE; - } - } - - // 3_b) and 3_d) - TempVar_a = PStateBufferPtr[0].PStateCoreStruct[0].HtcPstateLimit; - TempVar_d = PStateBufferPtr[0].PStateCoreStruct[0].PStateStruct[TempVar_a].CoreFreq; - TempVar_e = PStateBufferPtr[0].PStateCoreStruct[0].PStateStruct[TempVar_a].Power; - TempVar_f = PStateBufferPtr[0].PStateCoreStruct[0].PStateStruct[TempVar_a].IddValue; - TempVar_c = PStateBufferPtr[0].PStateCoreStruct[0].PStateStruct[TempVar_a].IddDiv; - for (i = 0; i < LogicalSocketCount; i++) { - CpuGetPStateLevelStructure (&PStateBufferPtrTmp, PStateStrucPtr, i, StdHeader); - for (k = 0; k < 1; k++) { - TempVar_b = PStateBufferPtrTmp->PStateCoreStruct[0].HtcPstateLimit; - if (TempVar_d > PStateBufferPtrTmp->PStateCoreStruct[0].PStateStruct[TempVar_b].CoreFreq) { - TempVar_d = PStateBufferPtrTmp->PStateCoreStruct[0].PStateStruct[TempVar_b].CoreFreq; - } - - if (TempVar_e < PStateBufferPtrTmp->PStateCoreStruct[0].PStateStruct[TempVar_b].Power) { - TempVar_e = PStateBufferPtrTmp->PStateCoreStruct[0].PStateStruct[TempVar_b].Power; - TempVar_f = PStateBufferPtrTmp->PStateCoreStruct[0].PStateStruct[TempVar_b].IddValue; - TempVar_c = PStateBufferPtrTmp->PStateCoreStruct[0].PStateStruct[TempVar_b].IddDiv; - } - } - } - - // 3_c) and 3_e) - for (i = 0; i < LogicalSocketCount; i++) { - CpuGetPStateLevelStructure (&PStateBufferPtrTmp, PStateStrucPtr, i, StdHeader); - TempVar_a = PStateBufferPtrTmp->PStateCoreStruct[0].HtcPstateLimit; - PStateBufferPtrTmp->PStateCoreStruct[0].PStateStruct[TempVar_a].CoreFreq = TempVar_d; - PStateBufferPtrTmp->PStateCoreStruct[0].PStateStruct[TempVar_a].Power = TempVar_e; - PStateBufferPtrTmp->PStateCoreStruct[0].PStateStruct[TempVar_a].IddValue = TempVar_f; - PStateBufferPtrTmp->PStateCoreStruct[0].PStateStruct[TempVar_a].IddDiv = TempVar_c; - } - } // if(AllCoresHaveHtcCapEquToZeroFlag) - - - //-------------------------------------------------------------------------- - // STEP - 4 - //-------------------------------------------------------------------------- - // Match the CPU COF and power for the lowest performance P-state: - // 4_a) If F3xDC[PstateMaxVal] = F3x64[HtcPstateLimit] for any processor, - // set PstateEn = 0 for all the P-states greater than - // F3x64[HtcPstateLimit] for all processors. - // 4_b) Identify the lowest CPU COF for all processors in the P-state - // pointed to by F3xDC[PstateMaxVal]. - // 4_c) Modify the CPU COF for all processors in the P-state pointed to by - // F3xDC[PstateMaxVal] to the previously identified lowest CPU COF - // value. - // 4_d) Identify the highest power for all processors in the P-state - // pointed to by F3xDC[PstateMaxVal]. - // 4_e) Modify the power for all processors in the P-state pointed to by - // F3xDC[PstateMaxVal] to the previously identified highest power - // value. - - // 4_a) - if (PstateMaxValEquToPstateHtcLimitFlag) { - for (i = 0; i < LogicalSocketCount; i++) { - CpuGetPStateLevelStructure (&PStateBufferPtrTmp, PStateStrucPtr, i, StdHeader); - TempVar_b = PStateBufferPtrTmp->PStateCoreStruct[0].HtcPstateLimit + 1; - for (k = TempVar_b; k <= PStateBufferPtrTmp->PStateCoreStruct[0].PStateMaxValue; k++) { - PStateBufferPtrTmp->PStateCoreStruct[0].PStateStruct[k].PStateEnable = 0; - } - //-------------------------------------------------------------------------- - // STEP - 5 - //-------------------------------------------------------------------------- - // 5_a) Modify F3xDC[PstateMaxVal] to indicate the lowest performance - // P-state with PstateEn set for each processor (Step 4 can disable - // P-states pointed to by F3xDC[PstateMaxVal]) - - // Use this value of HtcPstateLimit to program the - // F3xDC[pStateMaxValue] - TempVar_e = PStateBufferPtrTmp->PStateCoreStruct[0].HtcPstateLimit; - TempVar_e <<= 8; - // Bits 10:8 - - for (m = 0; m < (UINT8)GetPlatformNumberOfModules (); m++) { - if (GetPciAddress (StdHeader, PStateBufferPtrTmp->SocketNumber, m, &PciAddress, &Status)) { - PciAddress.Address.Function = FUNC_3; - PciAddress.Address.Register = CLOCK_POWER_TIMING_CTRL2_REG; - LibAmdPciRead (AccessWidth32, PciAddress, &TempVar_d, StdHeader); - TempVar_d = (TempVar_d & 0xFFFFF8FF) | TempVar_e; - LibAmdPciWrite (AccessWidth32, PciAddress, &TempVar_d, StdHeader); - } - }//End of step 5 - } - }// End of 4_a) - - // 4_b) and 4_d) - TempVar_a = PStateBufferPtr[0].PStateCoreStruct[0].PStateMaxValue; - TempVar_d = PStateBufferPtr[0].PStateCoreStruct[0].PStateStruct[TempVar_a].CoreFreq; - TempVar_e = PStateBufferPtr[0].PStateCoreStruct[0].PStateStruct[TempVar_a].Power; - TempVar_f = PStateBufferPtr[0].PStateCoreStruct[0].PStateStruct[TempVar_a].IddValue; - TempVar_c = PStateBufferPtr[0].PStateCoreStruct[0].PStateStruct[TempVar_a].IddDiv; - - for (i = 0; i < LogicalSocketCount; i++) { - CpuGetPStateLevelStructure (&PStateBufferPtrTmp, PStateStrucPtr, i, StdHeader); - TempVar_b = PStateBufferPtrTmp->PStateCoreStruct[0].PStateMaxValue; - if (TempVar_d > - PStateBufferPtrTmp->PStateCoreStruct[0].PStateStruct[TempVar_b].CoreFreq) { - TempVar_d = - PStateBufferPtrTmp->PStateCoreStruct[0].PStateStruct[TempVar_b].CoreFreq; - } - - if (TempVar_e < PStateBufferPtrTmp->PStateCoreStruct[0].PStateStruct[TempVar_b].Power) { - TempVar_e = PStateBufferPtrTmp->PStateCoreStruct[0].PStateStruct[TempVar_b].Power; - TempVar_f = PStateBufferPtrTmp->PStateCoreStruct[0].PStateStruct[TempVar_b].IddValue; - TempVar_c = PStateBufferPtrTmp->PStateCoreStruct[0].PStateStruct[TempVar_b].IddDiv; - } - } - - // 4_c) and 4_e) - for (i = 0; i < LogicalSocketCount; i++) { - CpuGetPStateLevelStructure (&PStateBufferPtrTmp, PStateStrucPtr, i, StdHeader); - TempVar_a = PStateBufferPtrTmp->PStateCoreStruct[0].PStateMaxValue; - PStateBufferPtrTmp->PStateCoreStruct[0].PStateStruct[TempVar_a].CoreFreq = TempVar_d; - PStateBufferPtrTmp->PStateCoreStruct[0].PStateStruct[TempVar_a].Power = TempVar_e; - PStateBufferPtrTmp->PStateCoreStruct[0].PStateStruct[TempVar_a].IddValue = TempVar_f; - PStateBufferPtrTmp->PStateCoreStruct[0].PStateStruct[TempVar_a].IddDiv = TempVar_c; - } - - - //-------------------------------------------------------------------------- - // STEP - 6 - //-------------------------------------------------------------------------- - // Match the CPU COF and power for upper intermediate performance - // P-state(s): - // Upper intermediate PStates = PStates between (Not including) P0 and - // F3x64[HtcPstateLimit] - // 6_a) If F3x64[HtcPstateLimit] = 001b for any processor, set PstateEn = 0 - // for enabled upper intermediate P-states for all processors with - // F3x64[HtcPstateLimit] > 001b and skip the remaining actions for - // this numbered step. - // 6_b) Define each of the available upper intermediate P-states; for each - // processor concurrently evaluate the following loop; when any - // processor falls out of the loop (runs out of available upper - // intermediate Pstates) all other processors have their remaining - // upper intermediate P-states invalidated (PstateEn = 0); - // for (i = F3x64[HtcPstateLimit] - 1; i > 0; i--) - // - Identify the lowest CPU COF for P(i). - // - Identify the highest power for P(i). - // - Modify P(i) CPU COF for all processors to the previously - // identified lowest CPU COF value. - // - Modify P(i) power for all processors to the previously - // identified highest power value. - - // 6_a) - if (AtLeastOneCoreHasPstateHtcLimitEquToOneFlag) { - for (i = 0; i < LogicalSocketCount; i++) { - CpuGetPStateLevelStructure (&PStateBufferPtrTmp, PStateStrucPtr, i, StdHeader); - for (k = TempSwP0Array[i] + 1; k < (PStateBufferPtrTmp->PStateCoreStruct[0].HtcPstateLimit); k++) { - if (PStateBufferPtrTmp->PStateCoreStruct[0].HtcPstateLimit > 1) { - // Make a function call to clear the - // structure values - PStateBufferPtrTmp->PStateCoreStruct[0].PStateStruct[k].PStateEnable = 0; - } - } - } - } - // 6_b) - else { - // Identify Lowest Frequency and Highest Power - TotalIterations = 0; - TempFlag1 = TRUE; - - for (i = 0; i < LogicalSocketCount; i++) { - CpuGetPStateLevelStructure (&PStateBufferPtrTmp, PStateStrucPtr, i, StdHeader); - TempSocketPiArray[i] = PStateBufferPtrTmp->PStateCoreStruct[0].HtcPstateLimit - 1; - } - - do { - //For first socket, try to find a candidate - if (TempSocketPiArray[0] != TempSwP0Array[0]) { - while (PStateBufferPtr[0].PStateCoreStruct[0].PStateStruct[TempSocketPiArray[0]].PStateEnable == 0) { - TempSocketPiArray[0] = TempSocketPiArray[0] - 1; - if (TempSocketPiArray[0] == TempSwP0Array[0]) { - TempFlag1 = FALSE; - break; - } - } - } else { - TempFlag1 = FALSE; - } - if (TempFlag1) { - TempFreqArray[TotalIterations] = PStateBufferPtr[0].PStateCoreStruct[0].PStateStruct[TempSocketPiArray[0]].CoreFreq; - TempPowerArray[TotalIterations] = PStateBufferPtr[0].PStateCoreStruct[0].PStateStruct[TempSocketPiArray[0]].Power; - TempIddValueArray[TotalIterations] = PStateBufferPtr[0].PStateCoreStruct[0].PStateStruct[TempSocketPiArray[0]].IddValue; - TempIddDivArray[TotalIterations] = PStateBufferPtr[0].PStateCoreStruct[0].PStateStruct[TempSocketPiArray[0]].IddDiv; - - //Try to find next candidate - for (i = 1; i < LogicalSocketCount; i++) { - CpuGetPStateLevelStructure (&PStateBufferPtrTmp, PStateStrucPtr, i, StdHeader); - if (TempSocketPiArray[i] != TempSwP0Array[i]) { - while (PStateBufferPtrTmp->PStateCoreStruct[0].PStateStruct[TempSocketPiArray[i]].PStateEnable == 0) { - TempSocketPiArray[i]--; - if (TempSocketPiArray[i] == TempSwP0Array[i]) { - TempFlag1 = FALSE; - break; - } - }//end while - } else { - TempFlag1 = FALSE; - } - - } //end for LogicalSocketCount - } - - if (TempFlag1) { - for (i = 0; i < LogicalSocketCount; i++) { - // - //Compare - // - CpuGetPStateLevelStructure (&PStateBufferPtrTmp, PStateStrucPtr, i, StdHeader); - if (TempFreqArray[TotalIterations] > PStateBufferPtrTmp->PStateCoreStruct[0].PStateStruct[TempSocketPiArray[i]].CoreFreq) { - TempFreqArray[TotalIterations] = PStateBufferPtrTmp->PStateCoreStruct[0].PStateStruct[TempSocketPiArray[i]].CoreFreq; - } - - if (TempPowerArray[TotalIterations] < PStateBufferPtrTmp->PStateCoreStruct[0].PStateStruct[TempSocketPiArray[i]].Power) { - TempPowerArray[TotalIterations] = PStateBufferPtrTmp->PStateCoreStruct[0].PStateStruct[TempSocketPiArray[i]].Power; - TempIddValueArray[TotalIterations] = PStateBufferPtrTmp->PStateCoreStruct[0].PStateStruct[TempSocketPiArray[i]].IddValue; - TempIddDivArray[TotalIterations] = PStateBufferPtrTmp->PStateCoreStruct[0].PStateStruct[TempSocketPiArray[i]].IddDiv; - } - } - // Modify (Pi) CPU COF and Power for all the CPUs - for (i = 0; i < LogicalSocketCount; i++) { - CpuGetPStateLevelStructure (&PStateBufferPtrTmp, PStateStrucPtr, i, StdHeader); - PStateBufferPtrTmp->PStateCoreStruct[0].PStateStruct[TempSocketPiArray[i]].CoreFreq = TempFreqArray[TotalIterations]; - PStateBufferPtrTmp->PStateCoreStruct[0].PStateStruct[TempSocketPiArray[i]].Power = TempPowerArray[TotalIterations]; - PStateBufferPtrTmp->PStateCoreStruct[0].PStateStruct[TempSocketPiArray[i]].IddValue = TempIddValueArray[TotalIterations]; - PStateBufferPtrTmp->PStateCoreStruct[0].PStateStruct[TempSocketPiArray[i]].IddDiv = TempIddDivArray[TotalIterations]; - TempSocketPiArray[i] = TempSocketPiArray[i] - 1; - } - } else { - for (i = 0; i < LogicalSocketCount; i++) { - CpuGetPStateLevelStructure (&PStateBufferPtrTmp, PStateStrucPtr, i, StdHeader); - for (m = TempSocketPiArray[i]; m > TempSwP0Array[i]; m--) { - PStateBufferPtrTmp->PStateCoreStruct[0].PStateStruct[m].PStateEnable = 0; - } - } - } - - TotalIterations++; - } while (TempFlag1); - - } // else - - //-------------------------------------------------------------------------- - // STEP - 7 - //-------------------------------------------------------------------------- - // Match the CPU COF and power for lower intermediate performance P - state(s) - // Lower Intermediate Pstates = Pstates between (not including) - // F3x64[HtcPstateLimit] and F3xDC[PstateMaxVal] - // 7_a) If F3xDC[PstateMaxVal] - F3x64[HtcPstateLimit] < 2 for any - // processor, set PstateEn = 0 for enabled lower intermediate P - states - // for all processors with (F3xDC[PstateMaxVal] - - // F3x64[HtcPstateLimit] > 1) and skip the remaining actions for this - // numbered step. - // 7_b) Define each of the available lower intermediate P-states; for each - // processor concurrently evaluate the following loop; when any - // processor falls out of the loop (runs out of available lower - // intermediate Pstates) all other processors have their remaining - // lower intermediate P-states invalidated (PstateEn = 0); - // for (i = F3xDC[PstateMaxVal]-1; i > F3x64[HtcPstateLimit]; i--) - // - Identify the lowest CPU COF for P-states between - // (not including) F3x64[HtcPstateLimit] and P(i). - // - Identify the highest power for P-states between - // (not including) F3x64[HtcPstateLimit] and P(i). - // - Modify P(i) CPU COF for all processors to the previously - // identified lowest CPU COF value. - // - Modify P(i) power for all processors to the previously - // identified highest power value. - - - // 7_a) - if (PstateMaxValMinusHtcPstateLimitLessThan2Flag) { - for (i = 0; i < LogicalSocketCount; i++) { - CpuGetPStateLevelStructure (&PStateBufferPtrTmp, PStateStrucPtr, i, StdHeader); - - for (k = PStateBufferPtrTmp->PStateCoreStruct[0].PStateMaxValue - 1; - k > PStateBufferPtrTmp->PStateCoreStruct[0].HtcPstateLimit; - k--) { - if ((PStateBufferPtrTmp->PStateCoreStruct[0].PStateMaxValue - - PStateBufferPtrTmp->PStateCoreStruct[0].HtcPstateLimit) > 1) { - PStateBufferPtrTmp->PStateCoreStruct[0].PStateStruct[k].PStateEnable = 0; - } - } - } - } - - // 7_b) - else { - // Identify Lowest Frequency and Highest Power - - TotalIterations = 0; - TempFlag1 = TRUE; - - for (i = 0; i < LogicalSocketCount; i++) { - CpuGetPStateLevelStructure (&PStateBufferPtrTmp, PStateStrucPtr, i, StdHeader); - TempSocketPiArray[i] = PStateBufferPtrTmp->PStateCoreStruct[0].PStateMaxValue - 1; - } - - do { - //For first socket, try to find a candidate - if (TempSocketPiArray[0] != PStateBufferPtr[0].PStateCoreStruct[0].HtcPstateLimit) { - while (PStateBufferPtr[0].PStateCoreStruct[0].PStateStruct[TempSocketPiArray[0]].PStateEnable == 0) { - TempSocketPiArray[0] = TempSocketPiArray[0] - 1; - if (TempSocketPiArray[0] == PStateBufferPtr[0].PStateCoreStruct[0].HtcPstateLimit) { - TempFlag1 = FALSE; - break; - } - } - } else { - TempFlag1 = FALSE; - } - if (TempFlag1) { - TempFreqArray[TotalIterations] = PStateBufferPtr[0].PStateCoreStruct[0].PStateStruct[TempSocketPiArray[0]].CoreFreq; - TempPowerArray[TotalIterations] = PStateBufferPtr[0].PStateCoreStruct[0].PStateStruct[TempSocketPiArray[0]].Power; - TempIddValueArray[TotalIterations] = PStateBufferPtr[0].PStateCoreStruct[0].PStateStruct[TempSocketPiArray[0]].IddValue; - TempIddDivArray[TotalIterations] = PStateBufferPtr[0].PStateCoreStruct[0].PStateStruct[TempSocketPiArray[0]].IddDiv; - - //Try to find next candidate - for (i = 1; i < LogicalSocketCount; i++) { - CpuGetPStateLevelStructure (&PStateBufferPtrTmp, PStateStrucPtr, i, StdHeader); - if (TempSocketPiArray[i] != PStateBufferPtrTmp->PStateCoreStruct[0].HtcPstateLimit) { - while (PStateBufferPtrTmp->PStateCoreStruct[0].PStateStruct[TempSocketPiArray[i]].PStateEnable == 0) { - TempSocketPiArray[i]--; - if (TempSocketPiArray[i] == PStateBufferPtrTmp->PStateCoreStruct[0].HtcPstateLimit) { - TempFlag1 = FALSE; - break; - } - }//end while - } else { - TempFlag1 = FALSE; - } - } //end for LogicalSocketCount - } - - if (TempFlag1) { - for (i = 0; i < LogicalSocketCount; i++) { - // - //Compare - // - CpuGetPStateLevelStructure (&PStateBufferPtrTmp, PStateStrucPtr, i, StdHeader); - if (TempFreqArray[TotalIterations] > PStateBufferPtrTmp->PStateCoreStruct[0].PStateStruct[TempSocketPiArray[i]].CoreFreq) { - TempFreqArray[TotalIterations] = PStateBufferPtrTmp->PStateCoreStruct[0].PStateStruct[TempSocketPiArray[i]].CoreFreq; - } - if (TempPowerArray[TotalIterations] < PStateBufferPtrTmp->PStateCoreStruct[0].PStateStruct[TempSocketPiArray[i]].Power) { - TempPowerArray[TotalIterations] = PStateBufferPtrTmp->PStateCoreStruct[0].PStateStruct[TempSocketPiArray[i]].Power; - TempIddValueArray[TotalIterations] = PStateBufferPtrTmp->PStateCoreStruct[0].PStateStruct[TempSocketPiArray[i]].IddValue; - TempIddDivArray[TotalIterations] = PStateBufferPtrTmp->PStateCoreStruct[0].PStateStruct[TempSocketPiArray[i]].IddDiv; - } - } - // Modify (Pi) CPU COF and Power for all the CPUs - for (i = 0; i < LogicalSocketCount; i++) { - CpuGetPStateLevelStructure (&PStateBufferPtrTmp, PStateStrucPtr, i, StdHeader); - PStateBufferPtrTmp->PStateCoreStruct[0].PStateStruct[TempSocketPiArray[i]].CoreFreq = TempFreqArray[TotalIterations]; - PStateBufferPtrTmp->PStateCoreStruct[0].PStateStruct[TempSocketPiArray[i]].Power = TempPowerArray[TotalIterations]; - PStateBufferPtrTmp->PStateCoreStruct[0].PStateStruct[TempSocketPiArray[i]].IddValue = TempIddValueArray[TotalIterations]; - PStateBufferPtrTmp->PStateCoreStruct[0].PStateStruct[TempSocketPiArray[i]].IddDiv = TempIddDivArray[TotalIterations]; - TempSocketPiArray[i] = TempSocketPiArray[i] - 1; - } - } else { - for (i = 0; i < LogicalSocketCount; i++) { - CpuGetPStateLevelStructure (&PStateBufferPtrTmp, PStateStrucPtr, i, StdHeader); - for (m = TempSocketPiArray[i]; m > PStateBufferPtrTmp->PStateCoreStruct[0].HtcPstateLimit; m--) { - PStateBufferPtrTmp->PStateCoreStruct[0].PStateStruct[m].PStateEnable = 0; - } - } - } - TotalIterations++; - } while (TempFlag1); - } // else - } // if(!AllCoreHaveMaxOnePStateFlag) - - PStateBufferPtr[0].InitStruct = 1; - } // CurrentCore - - - // Update the pState MSRs - // This can be done only by individual core - StartPstateMsrModify (PStateStrucPtr, StdHeader); - - //---------------------------------------------------------------------------------- - // STEP - 8 - //---------------------------------------------------------------------------------- - // Place all cores into a valid COF and VID configuration corresponding to an - // enabled P-state: - // 8_a) Select an enabled P-state != to the P-state pointed to by - // MSRC001_0063[CurPstate] for each core. - // 8_b) Transition all cores to the selected P-states by writing the Control value - // from the_PSS object corresponding to the selected P-state to - // MSRC001_0062[PstateCmd]. - // 8_c) Wait for all cores to report the Status value from the _PSS object - // corresponding to the selected P-state in MSRC001_0063[CurPstate]. - // - PutAllCoreInPState0 (PStateBufferPtr, StdHeader); - - return AGESA_SUCCESS; -} - - -/*---------------------------------------------------------------------------- - * LOCAL FUNCTIONS - * - *---------------------------------------------------------------------------- - */ - -/** - *--------------------------------------------------------------------------------------- - * - * PutAllCoreInPState0 - * - * Description: - * This function will put core pstate to p0. - * - * Parameters: - * @param[in,out] *PStateBufferPtr - * @param[in] *StdHeader - * - * @retval AGESA_STATUS - * - *--------------------------------------------------------------------------------------- - **/ -AGESA_STATUS -PutAllCoreInPState0 ( - IN OUT PSTATE_LEVELING *PStateBufferPtr, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - AP_TASK TaskPtr; - UINT32 BscSocket; - UINT32 Ignored; - UINT32 BscCoreNum; - UINT32 Core; - UINT32 Socket; - UINT32 NumberOfSockets; - UINT32 NumberOfCores; - AGESA_STATUS IgnoredSts; - - TaskPtr.FuncAddress.PfApTaskI = PutCoreInPState0; - TaskPtr.DataTransfer.DataSizeInDwords = SIZE_IN_DWORDS (PSTATE_LEVELING); - TaskPtr.ExeFlags = WAIT_FOR_CORE; - TaskPtr.DataTransfer.DataPtr = PStateBufferPtr; - TaskPtr.DataTransfer.DataTransferFlags = DATA_IN_MEMORY; - - IdentifyCore (StdHeader, &BscSocket, &Ignored, &BscCoreNum, &IgnoredSts); - NumberOfSockets = GetPlatformNumberOfSockets (); - - PutCoreInPState0 (PStateBufferPtr, StdHeader); - - for (Socket = 0; Socket < NumberOfSockets; Socket++) { - if (GetActiveCoresInGivenSocket (Socket, &NumberOfCores, StdHeader)) { - for (Core = 0; Core < NumberOfCores; Core++) { - if ((Socket != (UINT32) BscSocket) || (Core != (UINT32) BscCoreNum)) { - ApUtilRunCodeOnSocketCore ((UINT8) Socket, (UINT8) Core, &TaskPtr, StdHeader); - } - } - } - } - - return AGESA_SUCCESS; -} - -/** - *--------------------------------------------------------------------------------------- - * - * CorePstateRegModify - * - * Description: - * This function will setting the Pstate MSR to each APs base on Pstate Buffer. - * Note: This function should be called for every core in the system. - * - * Parameters: - * @param[in,out] *CpuAmdPState - * @param[in] *StdHeader - * - * @retval VOID - * - *--------------------------------------------------------------------------------------- - **/ -VOID -CorePstateRegModify ( - IN VOID *CpuAmdPState, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - PSTATE_CPU_FAMILY_SERVICES *FamilySpecificServices; - FamilySpecificServices = NULL; - - GetFeatureServicesOfCurrentCore (&PstateFamilyServiceTable, (const VOID **) &FamilySpecificServices, StdHeader); - ASSERT (FamilySpecificServices != NULL) - FamilySpecificServices->SetPStateLevelReg (FamilySpecificServices, (S_CPU_AMD_PSTATE *) CpuAmdPState, StdHeader); -} - - -/*---------------------------------------------------------------------------------------*/ -/** - * This function will set msr on all cores of all nodes. - * - * @param[in] CpuAmdPState Pointer to S_CPU_AMD_PSTATE. - * @param[in] StdHeader Header for library and services. - * - * @retval AGESA_SUCCESS Always succeeds - * - */ -AGESA_STATUS -StartPstateMsrModify ( - IN S_CPU_AMD_PSTATE *CpuAmdPState, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - AP_TASK TaskPtr; - UINT32 BscSocket; - UINT32 Ignored; - UINT32 BscCoreNum; - UINT32 Core; - UINT32 Socket; - UINT32 NumberOfSockets; - UINT32 NumberOfCores; - AGESA_STATUS IgnoredSts; - - TaskPtr.FuncAddress.PfApTaskI = CorePstateRegModify; - TaskPtr.DataTransfer.DataSizeInDwords = (UINT16) (CpuAmdPState->SizeOfBytes / 4 + 1); - TaskPtr.ExeFlags = WAIT_FOR_CORE; - TaskPtr.DataTransfer.DataPtr = CpuAmdPState; - TaskPtr.DataTransfer.DataTransferFlags = DATA_IN_MEMORY; - - IdentifyCore (StdHeader, &BscSocket, &Ignored, &BscCoreNum, &IgnoredSts); - NumberOfSockets = GetPlatformNumberOfSockets (); - - CorePstateRegModify (CpuAmdPState, StdHeader); - - for (Socket = 0; Socket < NumberOfSockets; Socket++) { - if (GetActiveCoresInGivenSocket (Socket, &NumberOfCores, StdHeader)) { - for (Core = 0; Core < NumberOfCores; Core++) { - if ((Socket != (UINT32) BscSocket) || (Core != (UINT32) BscCoreNum)) { - ApUtilRunCodeOnSocketCore ((UINT8) Socket, (UINT8) Core, &TaskPtr, StdHeader); - } - } - } - } - - return AGESA_SUCCESS; -} - - -/** - *--------------------------------------------------------------------------------------- - * - * CpuGetPStateLevelStructure - * - * Description: - * Based on the LogicalSocketNumber, this function will return a pointer - * point to the accurate offset of the PSTATE_LEVELING structure. - * - * Parameters: - * @param[in,out] *PStateBufferPtr - * @param[in] *CpuAmdPState - * @param[in] LogicalSocketNumber - * @param[in] *StdHeader - * - * @retval VOID - * - *--------------------------------------------------------------------------------------- - **/ -AGESA_STATUS -CpuGetPStateLevelStructure ( - OUT PSTATE_LEVELING **PStateBufferPtr, - IN S_CPU_AMD_PSTATE *CpuAmdPState, - IN UINT32 LogicalSocketNumber, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - PSTATE_LEVELING *PStateBufferPtrTmp; - UINT32 i; - - if (LogicalSocketNumber > CpuAmdPState->TotalSocketInSystem) { - return AGESA_UNSUPPORTED; - } - - PStateBufferPtrTmp = CpuAmdPState->PStateLevelingStruc; - - for (i = 1; i <= LogicalSocketNumber; i++) { - PStateBufferPtrTmp = (PSTATE_LEVELING *) ((UINT8 *) PStateBufferPtrTmp + ((UINTN) PStateBufferPtrTmp->PStateLevelingSizeOfBytes)); - } - - *PStateBufferPtr = PStateBufferPtrTmp; - - return AGESA_SUCCESS; -} - - -/** - *--------------------------------------------------------------------------------------- - * - * PutCoreInPState0 - * - * Description: - * This function will take the CPU core into P0 - * - * Parameters: - * @param[in] *PStateBuffer - * @param[in] *StdHeader - * - * @retval VOID - * - *--------------------------------------------------------------------------------------- - **/ -VOID -STATIC -PutCoreInPState0 ( - IN VOID *PStateBuffer, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - CPU_SPECIFIC_SERVICES *FamilySpecificServices; - PSTATE_LEVELING *PStateBufferPtr; - - PStateBufferPtr = (PSTATE_LEVELING *) PStateBuffer; - - if ((PStateBufferPtr[0].SetPState0 == PSTATE_FLAG_1 ) || - (PStateBufferPtr[0].SetPState0 == PSTATE_FLAG_2)) { - return; - } - - GetCpuServicesOfCurrentCore ((const CPU_SPECIFIC_SERVICES **)&FamilySpecificServices, StdHeader); - - FamilySpecificServices->TransitionPstate (FamilySpecificServices, (UINT8) 0, (BOOLEAN) FALSE, StdHeader); -} diff --git a/src/vendorcode/amd/agesa/f12/Proc/CPU/Feature/cpuPstateTables.c b/src/vendorcode/amd/agesa/f12/Proc/CPU/Feature/cpuPstateTables.c deleted file mode 100644 index 8db205249e..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/CPU/Feature/cpuPstateTables.c +++ /dev/null @@ -1,836 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * AMD PSTATE, ACPI table related API functions. - * - * Contains code that generates the _PSS, _PCT, and other ACPI tables. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: CPU - * @e \$Revision: 44571 $ @e \$Date: 2010-12-31 12:35:36 +0800 (Fri, 31 Dec 2010) $ - * - */ -/***************************************************************************** - * - * Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - ****************************************************************************** - */ - - -/* - *---------------------------------------------------------------------------- - * MODULES USED - * - *---------------------------------------------------------------------------- - */ -#include "AGESA.h" -#include "amdlib.h" -#include "OptionPstate.h" -#include "cpuLateInit.h" -#include "cpuRegisters.h" -#include "cpuFamilyTranslation.h" -#include "GeneralServices.h" -#include "cpuServices.h" -#include "heapManager.h" -#include "Ids.h" -#include "Filecode.h" -#include "GeneralServices.h" -#include "cpuPstateTables.h" -#include "cpuFeatures.h" -#include "cpuIoCstate.h" -CODE_GROUP (G3_DXE) -RDATA_GROUP (G3_DXE) - -#define FILECODE PROC_CPU_FEATURE_CPUPSTATETABLES_FILECODE -/*---------------------------------------------------------------------------- - * DEFINITIONS AND MACROS - * - *---------------------------------------------------------------------------- - */ -extern OPTION_PSTATE_LATE_CONFIGURATION OptionPstateLateConfiguration; // global user config record -extern CPU_FAMILY_SUPPORT_TABLE PstateFamilyServiceTable; -extern CPU_FAMILY_SUPPORT_TABLE IoCstateFamilyServiceTable; - -STATIC ACPI_TABLE_HEADER ROMDATA CpuSsdtHdrStruct = -{ - {'S','S','D','T'}, - 0, - 1, - 0, - {'A','M','D',' ',' ',' '}, - {'P','O','W','E','R','N','O','W'}, - 1, - {'A','M','D',' '}, - 1 -}; - - -/*---------------------------------------------------------------------------- - * TYPEDEFS AND STRUCTURES - * - *---------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------- - * PROTOTYPES OF LOCAL FUNCTIONS - * - *---------------------------------------------------------------------------- - */ -UINT32 -CalAcpiTablesSize ( - IN S_CPU_AMD_PSTATE *AmdPstatePtr, - IN PLATFORM_CONFIGURATION *PlatformConfig, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -/** - *--------------------------------------------------------------------------------------- - * - * CalAcpiTablesSize - * - * Description: - * This function will calculate the size of ACPI PState tables - * - * Parameters: - * @param[in] *AmdPstatePtr - * @param[in] *PlatformConfig - * @param[in] *StdHeader - * - * @retval UINT32 - * - *--------------------------------------------------------------------------------------- - */ -UINT32 -CalAcpiTablesSize ( - IN S_CPU_AMD_PSTATE *AmdPstatePtr, - IN PLATFORM_CONFIGURATION *PlatformConfig, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - UINT32 ScopeSize; - UINT32 CoreCount; - UINT32 SocketCount; - UINT32 MaxCoreNumberInCurrentSocket; - UINT32 MaxSocketNumberInSystem; - UINT32 MaxPstateNumberInCurrentCore; - UINT32 CstateAcpiObjSize; - PSTATE_LEVELING *PStateLevelingBufferStructPtr; - IO_CSTATE_FAMILY_SERVICES *IoCstateFamilyServices; - - ScopeSize = sizeof (ACPI_TABLE_HEADER); - CstateAcpiObjSize = 0; - IoCstateFamilyServices = NULL; - - PStateLevelingBufferStructPtr = AmdPstatePtr->PStateLevelingStruc; - MaxSocketNumberInSystem = AmdPstatePtr->TotalSocketInSystem; - - if (IsFeatureEnabled (IoCstate, PlatformConfig, StdHeader)) { - GetFeatureServicesOfCurrentCore (&IoCstateFamilyServiceTable, (const VOID **)&IoCstateFamilyServices, StdHeader); - // If we're supporting multiple families, only proceed when IO Cstate family services are available - if (IoCstateFamilyServices != NULL) { - CstateAcpiObjSize = IoCstateFamilyServices->GetAcpiCstObj (IoCstateFamilyServices, PlatformConfig, StdHeader); - } - } - - for (SocketCount = 0; SocketCount < MaxSocketNumberInSystem; SocketCount++) { - MaxCoreNumberInCurrentSocket = PStateLevelingBufferStructPtr->TotalCoresInNode; - for (CoreCount = 0; CoreCount < MaxCoreNumberInCurrentSocket; CoreCount++) { - MaxPstateNumberInCurrentCore = PStateLevelingBufferStructPtr->PStateCoreStruct[0].PStateMaxValue + 1; - - ScopeSize += (SCOPE_STRUCT_SIZE - 1); // Scope size per core - ScopeSize += CstateAcpiObjSize; // C-State ACPI objects size per core - - // Add P-State ACPI Objects size per core - if ((PStateLevelingBufferStructPtr[0].CreateAcpiTables != 0) && (PlatformConfig->UserOptionPState)) { - ScopeSize += (PCT_STRUCT_SIZE + - PSS_HEADER_STRUCT_SIZE + - (MaxPstateNumberInCurrentCore * PSS_BODY_STRUCT_SIZE) + - XPSS_HEADER_STRUCT_SIZE + - (MaxPstateNumberInCurrentCore * XPSS_BODY_STRUCT_SIZE) + - PSD_HEADER_STRUCT_SIZE + - PSD_BODY_STRUCT_SIZE + - PPC_HEADER_BODY_STRUCT_SIZE); - } - } - ScopeSize += MaxCoreNumberInCurrentSocket; - PStateLevelingBufferStructPtr = (PSTATE_LEVELING *) ((UINT8 *) PStateLevelingBufferStructPtr + (UINTN) sizeof (PSTATE_LEVELING) + (UINTN) (PStateLevelingBufferStructPtr->PStateCoreStruct[0].PStateMaxValue * sizeof (S_PSTATE_VALUES))); - } - AmdPstatePtr->SizeOfBytes = ScopeSize; - - return ScopeSize; -} - -/**-------------------------------------------------------------------------------------- - * - * GenerateSsdtStub - * - * Description: - * This is the default routine for use when both PState and CState option is NOT - * requested. The option install process will create and fill the transfer vector - * with the address of the proper routine (Main or Stub). The link optimizer will - * strip out of the .DLL the routine that is not used. - * - * Parameters: - * @param[in] StdHeader Handle to config for library and services - * @param[in] PlatformConfig Contains the power cap parameter - * @param[in,out] SsdtPtr ACPI SSDT table pointer - * - * @retval AGESA_STATUS - * - *--------------------------------------------------------------------------------------- - **/ -AGESA_STATUS -GenerateSsdtStub ( - IN AMD_CONFIG_PARAMS *StdHeader, - IN PLATFORM_CONFIGURATION *PlatformConfig, - IN OUT VOID **SsdtPtr - ) -{ - return AGESA_UNSUPPORTED; -} - -/** - *--------------------------------------------------------------------------------------- - * - * GenerateSsdt - * - * Description: - * This function will populate the SSDT with ACPI P-States and C-States Objects, whenever - * necessary - * This function should be called only from BSP - * - * Parameters: - * @param[in] StdHeader Handle to config for library and services - * @param[in] PlatformConfig Contains the power cap parameter - * @param[in,out] SsdtPtr ACPI SSDT pointer - * - * @retval AGESA_STATUS - * - *--------------------------------------------------------------------------------------- - */ -AGESA_STATUS -GenerateSsdt ( - IN AMD_CONFIG_PARAMS *StdHeader, - IN PLATFORM_CONFIGURATION *PlatformConfig, - IN OUT VOID **SsdtPtr - ) -{ - UINT32 i; - UINT32 j; - UINT32 TempVar8_a; - UINT32 CurrSize; - UINT32 TempVar_a; - UINT32 TempVar_b; - UINT32 ScopeSize; - UINT32 CoreCount; - UINT32 SocketCount; - UINT32 MaxCorePerNode; - UINT8 LocalApicId; - UINT8 *IntermediatePtr; - AGESA_STATUS AgesaStatus; - LOCATE_HEAP_PTR LocateHeapParams; - ALLOCATE_HEAP_PARAMS AllocateHeapParams; - S_CPU_AMD_PSTATE *AmdPstatePtr; - PSTATE_LEVELING *PStateLevelingBufferStructPtr; - SCOPE *ScopeAcpiTablesStructPtr; - SCOPE *ScopeAcpiTablesStructPtrTemp; - - AGESA_TESTPOINT (TpProcCpuEntryPstate, StdHeader); - - ASSERT (IsBsp (StdHeader, &AgesaStatus)); - - // If P-State and C-State ACPI tables do not need to be generated, exit this routine - if ((!PlatformConfig->UserOptionPState) && (!IsFeatureEnabled (IoCstate, PlatformConfig, StdHeader))) { - AgesaStatus = AGESA_UNSUPPORTED; - return AgesaStatus; - } - - // Initialize data variables - ScopeSize = 0; - CoreCount = 0; - LocalApicId = 0; - CurrSize = 0; - - // Locate P-State data buffer - LocateHeapParams.BufferHandle = AMD_PSTATE_DATA_BUFFER_HANDLE; - AGESA_TESTPOINT (TpProcCpuBeforeLocateSsdtBuffer, StdHeader); - if (HeapLocateBuffer (&LocateHeapParams, StdHeader) != AGESA_SUCCESS) { - return AGESA_ERROR; - } - AGESA_TESTPOINT (TpProcCpuAfterLocateSsdtBuffer, StdHeader); - - AmdPstatePtr = (S_CPU_AMD_PSTATE *) LocateHeapParams.BufferPtr; - PStateLevelingBufferStructPtr = AmdPstatePtr->PStateLevelingStruc; - - // Allocate rough buffer for AcpiTable, if SsdtPtr is NULL - if (*SsdtPtr == NULL) { - //Do not know the actual size.. pre-calculate it. - AllocateHeapParams.RequestedBufferSize = CalAcpiTablesSize (AmdPstatePtr, PlatformConfig, StdHeader); - AllocateHeapParams.BufferHandle = AMD_PSTATE_ACPI_BUFFER_HANDLE; - AllocateHeapParams.Persist = HEAP_SYSTEM_MEM; - - AGESA_TESTPOINT (TpProcCpuBeforeAllocateSsdtBuffer, StdHeader); - if (HeapAllocateBuffer (&AllocateHeapParams, StdHeader) != AGESA_SUCCESS) { - return AGESA_ERROR; - } - AGESA_TESTPOINT (TpProcCpuAfterAllocateSsdtBuffer, StdHeader); - *SsdtPtr = AllocateHeapParams.BufferPtr; - } - - IDS_HDT_CONSOLE (CPU_TRACE, " SSDT is created\n"); - - // Copy SSDT header into allocated buffer - LibAmdMemCopy (*SsdtPtr, (VOID *) &CpuSsdtHdrStruct, (UINTN) (sizeof (ACPI_TABLE_HEADER)), StdHeader); - IntermediatePtr = (UINT8 *) *SsdtPtr; - ScopeAcpiTablesStructPtr = (SCOPE *) &IntermediatePtr[sizeof (ACPI_TABLE_HEADER)]; - - SocketCount = AmdPstatePtr->TotalSocketInSystem; - - // Generate name scope and ACPI objects for every core in the system - for (i = 0; i < SocketCount; i++) { - MaxCorePerNode = PStateLevelingBufferStructPtr->TotalCoresInNode; - for (j = 0; j < MaxCorePerNode; j++) { - CoreCount++; - // Set Name Scope for CPU0, 1, 2, ..... n - // CPU0 to CPUn will name as C000 to Cnnn - // ----------------------------------------- - ScopeAcpiTablesStructPtr->ScopeOpcode = SCOPE_OPCODE; - // This value will be filled at the end of this function - // Since at this time, we don't know how many Pstates we - // would have - ScopeAcpiTablesStructPtr->ScopeLength = 0; - ScopeAcpiTablesStructPtr->ScopeValue1 = SCOPE_VALUE1; - ScopeAcpiTablesStructPtr->ScopeValue2 = SCOPE_VALUE2; - ScopeAcpiTablesStructPtr->ScopeNamePt1a__ = SCOPE_NAME__; - if (PlatformConfig->ProcessorScopeInSb) { - ScopeAcpiTablesStructPtr->ScopeNamePt1a_P = SCOPE_NAME_S; - ScopeAcpiTablesStructPtr->ScopeNamePt1a_R = SCOPE_NAME_B; - } else { - ScopeAcpiTablesStructPtr->ScopeNamePt1a_P = SCOPE_NAME_P; - ScopeAcpiTablesStructPtr->ScopeNamePt1a_R = SCOPE_NAME_R; - } - ScopeAcpiTablesStructPtr->ScopeNamePt1b__ = SCOPE_NAME__; - ASSERT ((PlatformConfig->ProcessorScopeName0 >= 'A') && (PlatformConfig->ProcessorScopeName0 <= 'Z')) - ASSERT (((PlatformConfig->ProcessorScopeName1 >= 'A') && (PlatformConfig->ProcessorScopeName1 <= 'Z')) || \ - ((PlatformConfig->ProcessorScopeName1 >= '0') && (PlatformConfig->ProcessorScopeName1 <= '9')) || \ - (PlatformConfig->ProcessorScopeName1 == '_')) - - ScopeAcpiTablesStructPtr->ScopeNamePt2a_C = PlatformConfig->ProcessorScopeName0; - ScopeAcpiTablesStructPtr->ScopeNamePt2a_P = PlatformConfig->ProcessorScopeName1; - - TempVar8_a = ((CoreCount - 1) >> 4) & 0x0F; - ScopeAcpiTablesStructPtr->ScopeNamePt2a_U = (UINT8) (SCOPE_NAME_0 + TempVar8_a); - - TempVar8_a = (CoreCount - 1) & 0x0F; - if (TempVar8_a < 0xA) { - ScopeAcpiTablesStructPtr->ScopeNamePt2a_0 = (UINT8) (SCOPE_NAME_0 + TempVar8_a); - } else { - ScopeAcpiTablesStructPtr->ScopeNamePt2a_0 = (UINT8) (SCOPE_NAME_A + TempVar8_a - 0xA); - } - // Increment and typecast the pointer - ScopeAcpiTablesStructPtrTemp = ScopeAcpiTablesStructPtr; - ScopeAcpiTablesStructPtrTemp++; - - // Get the Local Apic Id for each core - LocalApicId = PStateLevelingBufferStructPtr->PStateCoreStruct[0].LocalApicId + (UINT8) j; - - // Create P-State ACPI Objects - CurrSize += ((*(OptionPstateLateConfiguration.PstateFeature)) (PlatformConfig, PStateLevelingBufferStructPtr, (VOID *) &ScopeAcpiTablesStructPtrTemp, LocalApicId, StdHeader)); - - // Create C-State ACPI Objects - CurrSize += ((*(OptionPstateLateConfiguration.CstateFeature)) (PlatformConfig, PStateLevelingBufferStructPtr, (VOID *) &ScopeAcpiTablesStructPtrTemp, LocalApicId, StdHeader)); - - // Now update the SCOPE Length field - { - CurrSize += (SCOPE_STRUCT_SIZE - 1); - ScopeSize += CurrSize; - - TempVar_b = ((CurrSize << 4) & 0x0000FF00); - TempVar_b |= ((CurrSize & 0x0000000F) | 0x00000040); - TempVar_a = TempVar_b; - ScopeAcpiTablesStructPtr->ScopeLength = (UINT16) TempVar_a; - CurrSize = 0; - } - - ScopeAcpiTablesStructPtr = ScopeAcpiTablesStructPtrTemp; - } - //Calculate next node buffer address - PStateLevelingBufferStructPtr = (PSTATE_LEVELING *) ((UINT8 *) PStateLevelingBufferStructPtr + (UINTN) sizeof (PSTATE_LEVELING) + (UINTN) (PStateLevelingBufferStructPtr->PStateCoreStruct[0].PStateMaxValue * sizeof (S_PSTATE_VALUES))); - } - //Update SSDT header Checksum - ((ACPI_TABLE_HEADER *) *SsdtPtr)->TableLength = (ScopeSize + CoreCount + sizeof (ACPI_TABLE_HEADER)); - ChecksumAcpiTable ((ACPI_TABLE_HEADER *) *SsdtPtr, StdHeader); - - return AGESA_SUCCESS; -} - -/**-------------------------------------------------------------------------------------- - * - * CreateAcpiTablesStub - * - * Description: - * This is the default routine for use when the P-State or C-State option is NOT - * requested. The option install process will create and fill the transfer vector - * with the address of the proper routine (Main or Stub). The link optimizer will - * strip out of the .DLL the routine that is not used. - * - * Parameters: - * @param[in] PlatformConfig Platform operational characteristics; power cap - * @param[in] PStateLevelingBuffer Buffer that contains P-State Leveling information - * @param[in,out] SsdtPtr ACPI SSDT table pointer - * @param[in] LocalApicId Local Apic Id - * @param[in] StdHeader Handle to config for library and services - * - * @retval Size of generated ACPI objects - * - *--------------------------------------------------------------------------------------- - **/ -UINT32 -CreateAcpiTablesStub ( - IN PLATFORM_CONFIGURATION *PlatformConfig, - IN PSTATE_LEVELING *PStateLevelingBuffer, - IN OUT VOID **SsdtPtr, - IN UINT8 LocalApicId, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - return 0; -} - - -/**-------------------------------------------------------------------------------------- - * - * CreatePStateAcpiTables - * - * Description: - * This is the common routine for creating ACPI P-State objects - * - * Parameters: - * @param[in] PlatformConfig Platform operational characteristics; power cap - * @param[in] PStateLevelingBuffer Buffer that contains P-State Leveling information - * @param[in,out] SsdtPtr ACPI SSDT table pointer - * @param[in] LocalApicId Local Apic Id - * @param[in] StdHeader Handle to config for library and services - * - * @retval Size of generated ACPI P-States objects - * - *--------------------------------------------------------------------------------------- - **/ -UINT32 -CreatePStateAcpiTables ( - IN PLATFORM_CONFIGURATION *PlatformConfig, - IN PSTATE_LEVELING *PStateLevelingBuffer, - IN OUT VOID **SsdtPtr, - IN UINT8 LocalApicId, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - UINT8 PstateCapLevelSupport; - UINT8 PStateMaxValueOnCurrentCore; - BOOLEAN PstateCapEnable; - BOOLEAN PstateCapLevelSupportDetermined; - BOOLEAN IsPsdDependent; - UINT32 k; - UINT32 TempVar_a; - UINT32 TempVar_b; - UINT32 TempVar_c; - UINT32 PstateCapInputMilliWatts; - UINT32 CurrSize; - UINT32 PstateCount; - UINT32 CoreCount1; - UINT32 TransAndBusMastLatency; - AGESA_STATUS IgnoredStatus; - PCI_ADDR PciAddress; - PCT_HEADER_BODY *pPctAcpiTables; - PSS_HEADER *pPssHeaderAcpiTables; - PSS_BODY *pPssBodyAcpiTables; - XPSS_HEADER *pXpssHeaderAcpiTables; - XPSS_BODY *pXpssBodyAcpiTables; - PSD_HEADER *pPsdHeaderAcpiTables; - PSD_BODY *pPsdBodyAcpiTables; - PPC_HEADER_BODY *pPpcAcpiTables; - PSTATE_CPU_FAMILY_SERVICES *FamilyServices; - - CurrSize = 0; - PstateCount = 0; - PstateCapEnable = FALSE; - PstateCapLevelSupport = DEFAULT_PERF_PRESENT_CAP; - PstateCapLevelSupportDetermined = TRUE; - PstateCapInputMilliWatts = PlatformConfig->PowerCeiling; - IsPsdDependent = !(PlatformConfig->ForcePstateIndependent); - TransAndBusMastLatency = 0; - - if ((PStateLevelingBuffer[0].CreateAcpiTables != 0) && (PlatformConfig->UserOptionPState)) { - pPctAcpiTables = (PCT_HEADER_BODY *) *SsdtPtr; - - //Check Pstate Capability - if (PstateCapInputMilliWatts != 0) { - PstateCapEnable = TRUE; - PstateCapLevelSupportDetermined = FALSE; - } - - PStateMaxValueOnCurrentCore = PStateLevelingBuffer->PStateCoreStruct[0].PStateMaxValue; - if (OptionPstateLateConfiguration.CfgPstatePct) { - // Set _PCT Table - // -------------- - pPctAcpiTables->NameOpcode = NAME_OPCODE; - pPctAcpiTables->PctName_a__ = PCT_NAME__; - pPctAcpiTables->PctName_a_P = PCT_NAME_P; - pPctAcpiTables->PctName_a_C = PCT_NAME_C; - pPctAcpiTables->PctName_a_T = PCT_NAME_T; - pPctAcpiTables->Value1 = PCT_VALUE1; - pPctAcpiTables->Value2 = PCT_VALUE2; - pPctAcpiTables->Value3 = PCT_VALUE3; - pPctAcpiTables->GenericRegDescription1 = GENERIC_REG_DESCRIPTION; - pPctAcpiTables->Length1 = PCT_LENGTH; - pPctAcpiTables->AddressSpaceId1 = PCT_ADDRESS_SPACE_ID; - pPctAcpiTables->RegisterBitWidth1 = PCT_REGISTER_BIT_WIDTH; - pPctAcpiTables->RegisterBitOffset1 = PCT_REGISTER_BIT_OFFSET; - pPctAcpiTables->Reserved1 = PCT_RESERVED; - pPctAcpiTables->ControlRegAddressLo = PCT_CONTROL_REG_LO; - pPctAcpiTables->ControlRegAddressHi = PCT_CONTROL_REG_HI; - pPctAcpiTables->Value4 = PCT_VALUE4; - pPctAcpiTables->Value5 = PCT_VALUE5; - pPctAcpiTables->GenericRegDescription2 = GENERIC_REG_DESCRIPTION; - pPctAcpiTables->Length2 = PCT_LENGTH; - pPctAcpiTables->AddressSpaceId2 = PCT_ADDRESS_SPACE_ID; - pPctAcpiTables->RegisterBitWidth2 = PCT_REGISTER_BIT_WIDTH; - pPctAcpiTables->RegisterBitOffset2 = PCT_REGISTER_BIT_OFFSET; - pPctAcpiTables->Reserved2 = PCT_RESERVED; - pPctAcpiTables->StatusRegAddressLo = PCT_STATUS_REG_LO; - pPctAcpiTables->StatusRegAddressHi = PCT_STATUS_REG_HI; - pPctAcpiTables->Value6 = PCT_VALUE6; - - // Increment and then typecast the pointer - pPctAcpiTables++; - CurrSize += PCT_STRUCT_SIZE; - - *SsdtPtr = pPctAcpiTables; - } // end of OptionPstateLateConfiguration.CfgPstatePct - - pPssHeaderAcpiTables = (PSS_HEADER *) pPctAcpiTables; - pPssBodyAcpiTables = (PSS_BODY *) pPctAcpiTables; - if (OptionPstateLateConfiguration.CfgPstatePss) { - // Set _PSS Header - // Note: Set pssLength and numOfItemsInPss later - //--------------------------------------------------- - pPssHeaderAcpiTables->NameOpcode = NAME_OPCODE; - pPssHeaderAcpiTables->PssName_a__ = PSS_NAME__; - pPssHeaderAcpiTables->PssName_a_P = PSS_NAME_P; - pPssHeaderAcpiTables->PssName_a_S = PSS_NAME_S; - pPssHeaderAcpiTables->PssName_b_S = PSS_NAME_S; - pPssHeaderAcpiTables->PkgOpcode = PACKAGE_OPCODE; - - pPssHeaderAcpiTables++; - pPssBodyAcpiTables = (PSS_BODY *) pPssHeaderAcpiTables; - // Restore the pPssHeaderAcpiTables - pPssHeaderAcpiTables--; - - // Set _PSS Body - //--------------- - PstateCount = 0; - - // Calculate PCI address for socket only - GetPciAddress (StdHeader, (UINT32) PStateLevelingBuffer->SocketNumber, 0, &PciAddress, &IgnoredStatus); - TransAndBusMastLatency = 0; - GetFeatureServicesOfSocket (&PstateFamilyServiceTable, (UINT32) PStateLevelingBuffer->SocketNumber, (const VOID **)&FamilyServices, StdHeader); - ASSERT (FamilyServices != NULL) - FamilyServices->GetPstateLatency ( FamilyServices, - PStateLevelingBuffer, - &PciAddress, - &TransAndBusMastLatency, - StdHeader); - - for (k = 0; k <= PStateMaxValueOnCurrentCore; k++) { - if (PStateLevelingBuffer->PStateCoreStruct[0].PStateStruct[k].PStateEnable != 0) { - pPssBodyAcpiTables->PkgOpcode = PACKAGE_OPCODE; - pPssBodyAcpiTables->PkgLength = PSS_PKG_LENGTH; - pPssBodyAcpiTables->NumOfElements = PSS_NUM_OF_ELEMENTS; - pPssBodyAcpiTables->DwordPrefixOpcode1 = DWORD_PREFIX_OPCODE; - pPssBodyAcpiTables->Frequency = - PStateLevelingBuffer->PStateCoreStruct[0].PStateStruct[k].CoreFreq; - pPssBodyAcpiTables->DwordPrefixOpcode2 = DWORD_PREFIX_OPCODE; - pPssBodyAcpiTables->Power = - PStateLevelingBuffer->PStateCoreStruct[0].PStateStruct[k].Power; - - if (PstateCapEnable && (!PstateCapLevelSupportDetermined) && (PstateCapInputMilliWatts >= pPssBodyAcpiTables->Power)) { - PstateCapLevelSupport = (UINT8) PStateLevelingBuffer->PStateCoreStruct[0].PStateStruct[k].SwPstateNumber; - PstateCapLevelSupportDetermined = TRUE; - } - - pPssBodyAcpiTables->DwordPrefixOpcode3 = DWORD_PREFIX_OPCODE; - pPssBodyAcpiTables->TransitionLatency = TransAndBusMastLatency; - pPssBodyAcpiTables->DwordPrefixOpcode4 = DWORD_PREFIX_OPCODE; - pPssBodyAcpiTables->BusMasterLatency = TransAndBusMastLatency; - pPssBodyAcpiTables->DwordPrefixOpcode5 = DWORD_PREFIX_OPCODE; - pPssBodyAcpiTables->Control = - PStateLevelingBuffer->PStateCoreStruct[0].PStateStruct[k].SwPstateNumber; - pPssBodyAcpiTables->DwordPrefixOpcode6 = DWORD_PREFIX_OPCODE; - pPssBodyAcpiTables->Status = - PStateLevelingBuffer->PStateCoreStruct[0].PStateStruct[k].SwPstateNumber; - - pPssBodyAcpiTables++; - PstateCount++; - } - } // for (k = 0; k < MPPSTATE_MAXIMUM_STATES; k++) - - if (PstateCapEnable && (!PstateCapLevelSupportDetermined)) { - PstateCapLevelSupport = PStateMaxValueOnCurrentCore; - } - - // Set _PSS Header again - // Now Set pssLength and numOfItemsInPss - //--------------------------------------- - TempVar_a = (PstateCount * PSS_BODY_STRUCT_SIZE) + 3; - TempVar_b = TempVar_a; - TempVar_c = ((TempVar_b << 4) & 0x0000FF00); - TempVar_c = TempVar_c | ((TempVar_b & 0x0000000F) | 0x00000040); - TempVar_a = (UINT16) TempVar_c; - - pPssHeaderAcpiTables->PssLength = (UINT16) TempVar_a; - pPssHeaderAcpiTables->NumOfItemsInPss = (UINT8) PstateCount; - CurrSize += (PSS_HEADER_STRUCT_SIZE + (PstateCount * PSS_BODY_STRUCT_SIZE)); - - *SsdtPtr = pPssBodyAcpiTables; - } // end of PSS Body if OptionPstateLateConfiguration.CfgPstatePss - - // Set XPSS Table - //--------------- - // Typecast the pointer - pXpssHeaderAcpiTables = (XPSS_HEADER *) pPssBodyAcpiTables; - pXpssBodyAcpiTables = (XPSS_BODY *) pPssBodyAcpiTables; - if (OptionPstateLateConfiguration.CfgPstateXpss) { - // Set XPSS Header - // Note: Set the pssLength and numOfItemsInPss later - //--------------------------------------------------- - pXpssHeaderAcpiTables->NameOpcode = NAME_OPCODE; - pXpssHeaderAcpiTables->XpssName_a_X = PSS_NAME_X; - pXpssHeaderAcpiTables->XpssName_a_P = PSS_NAME_P; - pXpssHeaderAcpiTables->XpssName_a_S = PSS_NAME_S; - pXpssHeaderAcpiTables->XpssName_b_S = PSS_NAME_S; - pXpssHeaderAcpiTables->PkgOpcode = PACKAGE_OPCODE; - - // Increment and then typecast the pointer - pXpssHeaderAcpiTables++; - pXpssBodyAcpiTables = (XPSS_BODY *) pXpssHeaderAcpiTables; - // Restore the pXpssHeaderAcpiTables - pXpssHeaderAcpiTables--; - - // Set XPSS Body - //--------------- - for (k = 0; k <= PStateMaxValueOnCurrentCore; k++) { - if (PStateLevelingBuffer->PStateCoreStruct[0].PStateStruct[k].PStateEnable != 0) { - pXpssBodyAcpiTables->PkgOpcode = PACKAGE_OPCODE; - pXpssBodyAcpiTables->PkgLength = XPSS_PKG_LENGTH; - pXpssBodyAcpiTables->NumOfElements = XPSS_NUM_OF_ELEMENTS; - pXpssBodyAcpiTables->XpssValueTbd = 04; - pXpssBodyAcpiTables->DwordPrefixOpcode1 = DWORD_PREFIX_OPCODE; - pXpssBodyAcpiTables->Frequency = - PStateLevelingBuffer->PStateCoreStruct[0].PStateStruct[k].CoreFreq; - pXpssBodyAcpiTables->DwordPrefixOpcode2 = DWORD_PREFIX_OPCODE; - pXpssBodyAcpiTables->Power = - PStateLevelingBuffer->PStateCoreStruct[0].PStateStruct[k].Power; - pXpssBodyAcpiTables->DwordPrefixOpcode3 = DWORD_PREFIX_OPCODE; - pXpssBodyAcpiTables->TransitionLatency = TransAndBusMastLatency; - pXpssBodyAcpiTables->DwordPrefixOpcode4 = DWORD_PREFIX_OPCODE; - pXpssBodyAcpiTables->BusMasterLatency = TransAndBusMastLatency; - pXpssBodyAcpiTables->ControlBuffer = XPSS_ACPI_BUFFER; - pXpssBodyAcpiTables->ControlLo = - PStateLevelingBuffer->PStateCoreStruct[0].PStateStruct[k].SwPstateNumber; - pXpssBodyAcpiTables->ControlHi = 0; - pXpssBodyAcpiTables->StatusBuffer = XPSS_ACPI_BUFFER; - pXpssBodyAcpiTables->StatusLo = - PStateLevelingBuffer->PStateCoreStruct[0].PStateStruct[k].SwPstateNumber; - pXpssBodyAcpiTables->StatusHi = 0; - pXpssBodyAcpiTables->ControlMaskBuffer = XPSS_ACPI_BUFFER; - pXpssBodyAcpiTables->ControlMaskLo = 0; - pXpssBodyAcpiTables->ControlMaskHi = 0; - pXpssBodyAcpiTables->StatusMaskBuffer = XPSS_ACPI_BUFFER; - pXpssBodyAcpiTables->StatusMaskLo = 0; - pXpssBodyAcpiTables->StatusMaskHi = 0; - - pXpssBodyAcpiTables++; - } - } // for (k = 0; k < MPPSTATE_MAXIMUM_STATES; k++) - - // Set XPSS Header again - // Now set pssLength and numOfItemsInPss - //--------------------------------------- - TempVar_a = (PstateCount * XPSS_BODY_STRUCT_SIZE) + 3; - TempVar_b = TempVar_a; - TempVar_c = ((TempVar_b << 4) & 0x0000FF00); - TempVar_c = TempVar_c | ((TempVar_b & 0x0000000F) | 0x00000040); - TempVar_a = (UINT16) TempVar_c; - - pXpssHeaderAcpiTables->XpssLength = (UINT16) TempVar_a; - pXpssHeaderAcpiTables->NumOfItemsInXpss = (UINT8) PstateCount; - CurrSize += (XPSS_HEADER_STRUCT_SIZE + (PstateCount * XPSS_BODY_STRUCT_SIZE)); - - *SsdtPtr = pXpssBodyAcpiTables; - } //end of XPSS Body OptionPstateLateConfiguration.CfgPstateXpss - - // Set _PSD Table - //--------------- - // Typecast the pointer - pPsdHeaderAcpiTables = (PSD_HEADER *) pXpssBodyAcpiTables; - pPsdBodyAcpiTables = (PSD_BODY *) pXpssBodyAcpiTables; - // Get Total Cores Per Node - if (GetActiveCoresInGivenSocket ((UINT32) PStateLevelingBuffer->SocketNumber, &CoreCount1, StdHeader)) { - GetFeatureServicesOfSocket (&PstateFamilyServiceTable, (UINT32) PStateLevelingBuffer->SocketNumber, (const VOID **)&FamilyServices, StdHeader); - ASSERT (FamilyServices != NULL) - if ((CoreCount1 != 1) && (OptionPstateLateConfiguration.CfgPstatePsd) && - FamilyServices->IsPstatePsdNeeded (FamilyServices, PlatformConfig, StdHeader)) { - // Set _PSD Header - //---------------- - pPsdHeaderAcpiTables->NameOpcode = NAME_OPCODE; - pPsdHeaderAcpiTables->PkgOpcode = PACKAGE_OPCODE; - pPsdHeaderAcpiTables->PsdLength = PSD_HEADER_LENGTH; - pPsdHeaderAcpiTables->Value1 = PSD_VALUE1; - pPsdHeaderAcpiTables->PsdName_a__ = PSD_NAME__; - pPsdHeaderAcpiTables->PsdName_a_P = PSD_NAME_P; - pPsdHeaderAcpiTables->PsdName_a_S = PSD_NAME_S; - pPsdHeaderAcpiTables->PsdName_a_D = PSD_NAME_D; - - // Typecast the pointer - pPsdHeaderAcpiTables++; - CurrSize += PSD_HEADER_STRUCT_SIZE; - pPsdBodyAcpiTables = (PSD_BODY *) pPsdHeaderAcpiTables; - - pPsdHeaderAcpiTables--; - // Set _PSD Body - //-------------- - pPsdBodyAcpiTables->PkgOpcode = PACKAGE_OPCODE; - pPsdBodyAcpiTables->PkgLength = PSD_PKG_LENGTH; - pPsdBodyAcpiTables->NumOfEntries = NUM_OF_ENTRIES; - pPsdBodyAcpiTables->BytePrefixOpcode1 = BYTE_PREFIX_OPCODE; - pPsdBodyAcpiTables->PsdNumOfEntries = PSD_NUM_OF_ENTRIES; - pPsdBodyAcpiTables->BytePrefixOpcode2 = BYTE_PREFIX_OPCODE; - pPsdBodyAcpiTables->PsdRevision = PSD_REVISION; - pPsdBodyAcpiTables->DwordPrefixOpcode1 = DWORD_PREFIX_OPCODE; - - IsPsdDependent = FamilyServices->IsPstatePsdDependent (FamilyServices, PlatformConfig, StdHeader); - - if (IsPsdDependent) { - pPsdBodyAcpiTables->DependencyDomain = PSD_DEPENDENCY_DOMAIN; - pPsdBodyAcpiTables->CoordinationType = PSD_COORDINATION_TYPE_SW_ALL; - pPsdBodyAcpiTables->NumOfProcessors = CoreCount1; - } else { - switch (GetComputeUnitMapping (StdHeader)) { - case AllCoresMapping: - // All cores are in their own compute unit. - pPsdBodyAcpiTables->DependencyDomain = LocalApicId; - pPsdBodyAcpiTables->CoordinationType = PSD_COORDINATION_TYPE_SW_ANY; - pPsdBodyAcpiTables->NumOfProcessors = PSD_NUM_OF_PROCESSORS; - break; - case EvenCoresMapping: - // Cores are paired in compute units. - pPsdBodyAcpiTables->DependencyDomain = (LocalApicId >> 1) & PSD_DOMAIN_COMPUTE_UNIT_MASK; - pPsdBodyAcpiTables->CoordinationType = PSD_COORDINATION_TYPE_HW_ALL; - pPsdBodyAcpiTables->NumOfProcessors = PSD_CORE_NUM_PER_COMPUTE_UNIT; - break; - default: - ASSERT (FALSE); - } - } - pPsdBodyAcpiTables->DwordPrefixOpcode2 = DWORD_PREFIX_OPCODE; - pPsdBodyAcpiTables->DwordPrefixOpcode3 = DWORD_PREFIX_OPCODE; - - pPsdBodyAcpiTables++; - *SsdtPtr = pPsdBodyAcpiTables; - CurrSize += PSD_BODY_STRUCT_SIZE; - } - }// end of PSD Body if (CoreCount1 != 1) || (OptionPstateLateConfiguration.CfgPstatePsd) - // Typecast the pointer - - pPpcAcpiTables = (PPC_HEADER_BODY *) pPsdBodyAcpiTables; - - // Set _PPC Table - //--------------- - if (OptionPstateLateConfiguration.CfgPstatePpc) { - pPpcAcpiTables->MethodOpcode = METHOD_OPCODE; - pPpcAcpiTables->PpcLength = PPC_HEADER_BODY_STRUCT_SIZE -1; - pPpcAcpiTables->PpcName_a__ = PPC_NAME__; - pPpcAcpiTables->PpcName_a_P = PPC_NAME_P; - pPpcAcpiTables->PpcName_b_P = PPC_NAME_P; - pPpcAcpiTables->PpcName_a_C = PPC_NAME_C; - pPpcAcpiTables->MethodFlags = PPC_METHOD_FLAGS; - pPpcAcpiTables->ReturnOpcode = RETURN_OPCODE; - pPpcAcpiTables->Value1 = PPC_VALUE1; - - pPpcAcpiTables->DefaultPerfPresentCap = PstateCapLevelSupport; - CurrSize += PPC_HEADER_BODY_STRUCT_SIZE; - // Increment and typecast the pointer - pPpcAcpiTables++; - *SsdtPtr = pPpcAcpiTables; - }// end of OptionPstateLateConfiguration.CfgPstatePpc - } - return CurrSize; -} - -/**-------------------------------------------------------------------------------------- - * - * CreateCStateAcpiTables - * - * Description: - * This is the common routine for creating ACPI C-State objects - * - * Parameters: - * @param[in] PlatformConfig Platform operational characteristics; power cap - * @param[in] PStateLevelingBuffer Buffer that contains P-State Leveling information - * @param[in,out] SsdtPtr ACPI SSDT table pointer - * @param[in] LocalApicId Local Apic Id - * @param[in] StdHeader Handle to config for library and services - * - * @retval Size of ACPI C-States objects generated - * - *--------------------------------------------------------------------------------------- - **/ -UINT32 -CreateCStateAcpiTables ( - IN PLATFORM_CONFIGURATION *PlatformConfig, - IN PSTATE_LEVELING *PStateLevelingBuffer, - IN OUT VOID **SsdtPtr, - IN UINT8 LocalApicId, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - UINT32 ObjSize; - IO_CSTATE_FAMILY_SERVICES *IoCstateFamilyServices; - - ObjSize = 0; - - if (IsFeatureEnabled (IoCstate, PlatformConfig, StdHeader)) { - GetFeatureServicesOfCurrentCore (&IoCstateFamilyServiceTable, (const VOID **)&IoCstateFamilyServices, StdHeader); - // If we're supporting multiple families, only proceed when IO Cstate family services are available - if (IoCstateFamilyServices != NULL) { - IoCstateFamilyServices->CreateAcpiCstObj (IoCstateFamilyServices, LocalApicId, SsdtPtr, StdHeader); - ObjSize = IoCstateFamilyServices->GetAcpiCstObj (IoCstateFamilyServices, PlatformConfig, StdHeader); - } - } - return ObjSize; -} diff --git a/src/vendorcode/amd/agesa/f12/Proc/CPU/Feature/cpuPstateTables.h b/src/vendorcode/amd/agesa/f12/Proc/CPU/Feature/cpuPstateTables.h deleted file mode 100644 index 1944b32168..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/CPU/Feature/cpuPstateTables.h +++ /dev/null @@ -1,371 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * AMD AGESA CPU Pstate Table Functions declarations. - * - * Contains code that declares the AGESA CPU _PSS related APIs - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: CPU/Feature - * @e \$Revision: 44702 $ @e \$Date: 2011-01-05 06:54:00 +0800 (Wed, 05 Jan 2011) $ - * - */ -/* - ****************************************************************************** - * - * Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - ****************************************************************************** - */ - -#ifndef _CPU_PSTATE_TABLES_H_ -#define _CPU_PSTATE_TABLES_H_ - -/*---------------------------------------------------------------------------------------- - * M I X E D (Definitions And Macros / Typedefs, Structures, Enums) - *---------------------------------------------------------------------------------------- - */ -// Forward declaration needed for multi-structure mutual references -AGESA_FORWARD_DECLARATION (PSTATE_CPU_FAMILY_SERVICES); - -/*---------------------------------------------------------------------------------------- - * D E F I N I T I O N S A N D M A C R O S - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------- - * T Y P E D E F S A N D S T R U C T U R E S - *---------------------------------------------------------------------------------------- - */ -/// P-state structure for each state -typedef struct { - IN OUT UINT32 PStateEnable; ///< Pstate enable - IN OUT UINT32 CoreFreq; ///< MHz - IN OUT UINT32 Power; ///< milliWatts - IN OUT UINT32 IddValue; ///< Current value field - IN OUT UINT32 IddDiv; ///< Current divisor field - IN OUT UINT32 SwPstateNumber; ///< Software P-state number -} S_PSTATE_VALUES; - -/// P-state structure for each core -typedef struct { - IN OUT UINT8 PStateMaxValue; ///< Max p-state number in this core - IN OUT UINT8 HtcPstateLimit; ///< Htc limit - IN OUT UINT8 HtcCapable; ///< Htc capable - IN OUT UINT8 LocalApicId; ///< Local Apic Id - IN OUT UINT8 NumberOfBoostedStates; ///< Number of boost P-states - IN OUT S_PSTATE_VALUES PStateStruct[]; ///< P state struc -} S_PSTATE; - -/// P-state structure for each node -typedef struct { - IN UINT8 SetPState0; ///< If value = 0x55 (Don't set PState0) - IN UINT8 TotalCoresInNode; ///< core number per node - IN UINT16 PStateLevelingSizeOfBytes; ///< Size - IN BOOLEAN OnlyOneEnabledPState; ///< Only P0 - IN UINT8 InitStruct; ///< Init struc - IN BOOLEAN AllCpusHaveIdenticalPStates; ///< Have Identical p state - IN UINT8 CreateAcpiTables; ///< Create table flag - IN UINT8 SocketNumber; ///< Physical socket number of this socket - IN UINT8 Reserved[2]; ///< Reserved. - IN OUT S_PSTATE PStateCoreStruct[1]; ///< P state core struc -} PSTATE_LEVELING; - -/// P-state structure for whole system -typedef struct { - IN OUT UINT32 TotalSocketInSystem; ///< Total node number in system - IN OUT UINT32 SizeOfBytes; ///< Structure size - IN OUT PSTATE_LEVELING PStateLevelingStruc[1]; ///< P state level structure -} S_CPU_AMD_PSTATE; - -/*---------------------------------------------------------------------------------------*/ -/** - * Family specific call to check if PSD need to be generated. - * - * @param[in] PstateCpuFamilyServices Pstate CPU services. - * @param[in,out] PlatformConfig Contains the runtime modifiable feature input data. - * @param[in] StdHeader Config Handle for library, services. - * - * @retval TRUE PSD need to be generated - * @retval FALSE PSD does NOT need to be generated - * - */ -typedef BOOLEAN F_PSTATE_PSD_IS_NEEDED ( - IN PSTATE_CPU_FAMILY_SERVICES *PstateCpuServices, - IN OUT PLATFORM_CONFIGURATION *PlatformConfig, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -/// Reference to a Method. -typedef F_PSTATE_PSD_IS_NEEDED *PF_PSTATE_PSD_IS_NEEDED; - - -/*---------------------------------------------------------------------------------------*/ -/** - * Family specific call to check if Pstate PSD is dependent. - * - * @param[in] PstateCpuFamilyServices Pstate CPU services. - * @param[in,out] PlatformConfig Contains the runtime modifiable feature input data. - * @param[in] StdHeader Config Handle for library, services. - * - * @retval TRUE PSD is dependent. - * @retval FALSE PSD is independent. - * - */ -typedef BOOLEAN F_PSTATE_PSD_IS_DEPENDENT ( - IN PSTATE_CPU_FAMILY_SERVICES *PstateCpuServices, - IN OUT PLATFORM_CONFIGURATION *PlatformConfig, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -/// Reference to a Method. -typedef F_PSTATE_PSD_IS_DEPENDENT *PF_PSTATE_PSD_IS_DEPENDENT; - -/** - * Family specific call to set core TscFreqSel. - * - * @param[in] PstateCpuFamilyServices Pstate CPU services. - * @param[in] StdHeader Config Handle for library, services. - * - */ -typedef VOID F_PSTATE_SET_TSC_FREQ_SEL ( - IN PSTATE_CPU_FAMILY_SERVICES *PstateCpuServices, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -/// Reference to a Method. -typedef F_PSTATE_SET_TSC_FREQ_SEL *PF_PSTATE_SET_TSC_FREQ_SEL; - -/** - * Family specific call to get CPU pstate transition latency for current socket. - * - * @param[in] PstateCpuFamilyServices Pstate CPU services. - * @param[in] PStateLevelingBufferStructPtr Pstate row data buffer pointer. - * @param[in] PciAddress Pci address struct. - * @param[out] TransitionLatency Pstate Transition latency result. - * @param[in] StdHeader Handle of Header for calling lib functions and services. - * - */ -typedef AGESA_STATUS F_CPU_PSTATE_TRANSITION_LATENCY ( - IN PSTATE_CPU_FAMILY_SERVICES *PstateCpuServices, - IN PSTATE_LEVELING *PStateLevelingBufferStructPtr, - IN PCI_ADDR *PciAddress, - OUT UINT32 *TransitionLatency, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -/// Reference to a Method. -typedef F_CPU_PSTATE_TRANSITION_LATENCY *PF_CPU_PSTATE_TRANSITION_LATENCY; - -/** - * Family specific call to get the desired P-state's frequency in megahertz. - * - * @param[in] PstateCpuFamilyServices Pstate CPU services. - * @param[in] StateNumber P-state number. - * @param[out] PowerInMw P-state frequency in megahertz. - * @param[in] StdHeader Handle of Header for calling lib functions and services. - * - */ -typedef AGESA_STATUS F_CPU_GET_PSTATE_FREQ ( - IN PSTATE_CPU_FAMILY_SERVICES *PstateCpuServices, - IN UINT8 StateNumber, - OUT UINT32 *FreqInMHz, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -/// Reference to a Method. -typedef F_CPU_GET_PSTATE_FREQ *PF_CPU_GET_PSTATE_FREQ; - -/** - * Family specific call to set the system wide P-state settings on the current core. - * - * @param[in] PstateCpuFamilyServices Pstate CPU services. - * @param[in] CpuAmdPState The current core's P-state data. - * @param[in] StdHeader Handle of Header for calling lib functions and services. - * - */ -typedef AGESA_STATUS F_CPU_SET_PSTATE_LEVELING_REG ( - IN PSTATE_CPU_FAMILY_SERVICES *PstateCpuServices, - IN S_CPU_AMD_PSTATE *CpuAmdPState, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -/// Reference to a Method. -typedef F_CPU_SET_PSTATE_LEVELING_REG *PF_CPU_SET_PSTATE_LEVELING_REG; - -/** - * Family specific call to get the desired P-state's rated power in milliwatts. - * - * @param[in] PstateCpuFamilyServices Pstate CPU services. - * @param[in] StateNumber P-state number. - * @param[out] PowerInMw P-state power in milliwatts. - * @param[in] StdHeader Handle of Header for calling lib functions and services. - * - */ -typedef AGESA_STATUS F_CPU_GET_PSTATE_POWER ( - IN PSTATE_CPU_FAMILY_SERVICES *PstateCpuServices, - IN UINT8 StateNumber, - OUT UINT32 *PowerInMw, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -/// Reference to a Method. -typedef F_CPU_GET_PSTATE_POWER *PF_CPU_GET_PSTATE_POWER; - -/** - * Family specific call to get CPU Pstate Max State. - * - * @param[in] PstateCpuFamilyServices Pstate CPU services. - * @param[out] MaxPStateNumber The max hw pstate value on the current socket. - * @param[out] NumberOfBoostStates The number of boosted P-states on the current socket. - * @param[in] StdHeader Handle of Header for calling lib functions and services. - * - */ -typedef AGESA_STATUS F_CPU_GET_PSTATE_MAX_STATE ( - IN PSTATE_CPU_FAMILY_SERVICES *PstateCpuServices, - OUT UINT32 *MaxPStateNumber, - OUT UINT8 *NumberOfBoostStates, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -/// Reference to a Method. -typedef F_CPU_GET_PSTATE_MAX_STATE *PF_CPU_GET_PSTATE_MAX_STATE; - -/** - * Family specific call to get CPU pstate register information. - * - * @param[in] PstateCpuFamilyServices Pstate CPU services. - * @param[in] PState Input hardware Pstate number for query. - * @param[out] PStateEnabled Boolean flag return pstate enable. - * @param[in,out] IddVal Pstate current value. - * @param[in,out] IddDiv Pstate current divisor. - * @param[out] SwPstateNumber Software P-state number. - * @param[in] StdHeader Handle of Header for calling lib functions and services. - * - */ -typedef AGESA_STATUS F_CPU_GET_PSTATE_REGISTER_INFO ( - IN PSTATE_CPU_FAMILY_SERVICES *PstateCpuServices, - IN UINT32 PState, - OUT BOOLEAN *PStateEnabled, - IN OUT UINT32 *IddVal, - IN OUT UINT32 *IddDiv, - OUT UINT32 *SwPstateNumber, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -/// Reference to a Method. -typedef F_CPU_GET_PSTATE_REGISTER_INFO *PF_CPU_GET_PSTATE_REGISTER_INFO; - -/** - * Provide the interface to the Pstate dependent Family Specific Services. - * - * Use the methods or data in this struct to adapt the feature code to a specific cpu family or model (or stepping!). - * Each supported Family must provide an implementation for all methods in this interface, even if the - * implementation is a CommonReturn(). - */ -struct _PSTATE_CPU_FAMILY_SERVICES { - UINT16 Revision; ///< Interface version - // Public Methods. - PF_PSTATE_PSD_IS_NEEDED IsPstatePsdNeeded; ///< Method: Family specific call to check if PSD need to be generated. - PF_PSTATE_PSD_IS_DEPENDENT IsPstatePsdDependent; ///< Method: Family specific call to check if PSD is dependent. - PF_PSTATE_SET_TSC_FREQ_SEL CpuSetTscFreqSel; ///< Method: Family specific call to set core TscFreqSel. - PF_CPU_PSTATE_TRANSITION_LATENCY GetPstateLatency; ///< Method: Family specific call to get pstate transition latency. - PF_CPU_GET_PSTATE_FREQ GetPstateFrequency; ///< Method: Family specific call to get the desired P-state's frequency in megahertz. - PF_CPU_SET_PSTATE_LEVELING_REG SetPStateLevelReg; ///< Method: Family specific call to set the system wide P-state settings on the current core. - PF_CPU_GET_PSTATE_POWER GetPstatePower; ///< Method: Family specific call to get the desired P-state's rated power in milliwatts. - PF_CPU_GET_PSTATE_MAX_STATE GetPstateMaxState; ///< Method: Family specific call to get pstate max state number. - PF_CPU_GET_PSTATE_REGISTER_INFO GetPstateRegisterInfo; ///< Method: Family specific call to get pstate register information. -}; - - -/*---------------------------------------------------------------------------------------- - * F U N C T I O N S P R O T O T Y P E - *---------------------------------------------------------------------------------------- - */ -AGESA_STATUS -PStateGatherData ( - IN PLATFORM_CONFIGURATION *PlatformConfig, - IN OUT S_CPU_AMD_PSTATE *PStateStrucPtr, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -AGESA_STATUS -PStateLeveling ( - IN OUT S_CPU_AMD_PSTATE *PStateStrucPtr, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -AGESA_STATUS -CpuGetPStateLevelStructure ( - OUT PSTATE_LEVELING **PStateBufferPtr, - IN S_CPU_AMD_PSTATE *CpuAmdPState, - IN UINT32 LogicalSocketNumber, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -AGESA_STATUS -GenerateSsdtStub ( - IN AMD_CONFIG_PARAMS *StdHeader, - IN PLATFORM_CONFIGURATION *PlatformConfig, - IN OUT VOID **SsdtPtr - ); - -AGESA_STATUS -GenerateSsdt ( - IN AMD_CONFIG_PARAMS *StdHeader, - IN PLATFORM_CONFIGURATION *PlatformConfig, - IN OUT VOID **SsdtPtr - ); - -UINT32 -CreateAcpiTablesStub ( - IN PLATFORM_CONFIGURATION *PlatformConfig, - IN PSTATE_LEVELING *PStateLevelingBuffer, - IN OUT VOID **SsdtPtr, - IN UINT8 LocalApicId, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -UINT32 -CreatePStateAcpiTables ( - IN PLATFORM_CONFIGURATION *PlatformConfig, - IN PSTATE_LEVELING *PStateLevelingBuffer, - IN OUT VOID **SsdtPtr, - IN UINT8 LocalApicId, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -UINT32 -CreateCStateAcpiTables ( - IN PLATFORM_CONFIGURATION *PlatformConfig, - IN PSTATE_LEVELING *PStateLevelingBuffer, - IN OUT VOID **SsdtPtr, - IN UINT8 LocalApicId, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -#endif // _CPU_PSTATE_TABLES_H_ diff --git a/src/vendorcode/amd/agesa/f12/Proc/CPU/Feature/cpuSlit.c b/src/vendorcode/amd/agesa/f12/Proc/CPU/Feature/cpuSlit.c deleted file mode 100644 index dd414f1a8b..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/CPU/Feature/cpuSlit.c +++ /dev/null @@ -1,398 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * AMD SLIT, ACPI table related API functions. - * - * Contains code that generates the SLIT table - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: CPU - * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $ - * - */ -/* - ****************************************************************************** - * - * Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - ****************************************************************************** - */ - -/*---------------------------------------------------------------------------- - * This file provides functions, that will generate SLIT tables - *---------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------- - * M O D U L E S U S E D - *---------------------------------------------------------------------------------------- - */ - -#include "AGESA.h" -#include "amdlib.h" -#include "OptionSlit.h" -#include "heapManager.h" -#include "cpuLateInit.h" -#include "cpuRegisters.h" -#include "Topology.h" -#include "Ids.h" -#include "cpuFeatures.h" -#include "cpuFamilyTranslation.h" -#include "cpuL3Features.h" -#include "Filecode.h" -CODE_GROUP (G3_DXE) -RDATA_GROUP (G3_DXE) - -#define FILECODE PROC_CPU_FEATURE_CPUSLIT_FILECODE -/*---------------------------------------------------------------------------------------- - * D E F I N I T I O N S A N D M A C R O S - *---------------------------------------------------------------------------------------- - */ - -extern OPTION_SLIT_CONFIGURATION OptionSlitConfiguration; // global user config record - -STATIC ACPI_TABLE_HEADER ROMDATA CpuSlitHdrStruct = -{ - {'S','L','I','T'}, - 0, - 1, - 0, - {'A','M','D',' ',' ',' '}, - {'A','G','E','S','A',' ',' ',' '}, - 1, - {'A','M','D',' '}, - 1 -}; - -/*---------------------------------------------------------------------------------------- - * T Y P E D E F S A N D S T R U C T U R E S - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------- - * P R O T O T Y P E S O F L O C A L F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ -VOID -STATIC -AcpiSlitHBufferFind ( - IN OUT AMD_CONFIG_PARAMS *StdHeader, - IN UINT8 **SocketTopologyPtr - ); - -/*---------------------------------------------------------------------------------------- - * P R O T O T Y P E S O F E X P O R T E D F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ - - -/*---------------------------------------------------------------------------------------- - * E X P O R T E D F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ -AGESA_STATUS -GetAcpiSlitStub ( - IN OUT AMD_CONFIG_PARAMS *StdHeader, - IN PLATFORM_CONFIGURATION *PlatformConfig, - IN OUT VOID **SlitPtr - ); - -AGESA_STATUS -GetAcpiSlitMain ( - IN OUT AMD_CONFIG_PARAMS *StdHeader, - IN PLATFORM_CONFIGURATION *PlatformConfig, - IN OUT VOID **SlitPtr - ); - -AGESA_STATUS -ReleaseSlitBufferStub ( - IN OUT AMD_CONFIG_PARAMS *StdHeader - ); - -AGESA_STATUS -ReleaseSlitBuffer ( - IN OUT AMD_CONFIG_PARAMS *StdHeader - ); - -extern CPU_FAMILY_SUPPORT_TABLE L3FeatureFamilyServiceTable; - -/*---------------------------------------------------------------------------------------*/ -/** - * - * This function generates a complete SLIT table into a memory buffer. - * After completion, this table must be set by the system BIOS into its - * internal ACPI namespace, and linked into the RSDT/XSDT - * - * @param[in, out] StdHeader Standard Head Pointer - * @param[in] PlatformConfig Config handle for platform specific information - * @param[in, out] SlitPtr Point to Slit Struct including buffer address and length - * - * @retval UINT32 AGESA_STATUS - */ -AGESA_STATUS -CreateAcpiSlit ( - IN OUT AMD_CONFIG_PARAMS *StdHeader, - IN PLATFORM_CONFIGURATION *PlatformConfig, - IN OUT VOID **SlitPtr - ) -{ - AGESA_TESTPOINT (TpProcCpuEntrySlit, StdHeader); - return ((*(OptionSlitConfiguration.SlitFeature)) (StdHeader, PlatformConfig, SlitPtr)); -} - -/*---------------------------------------------------------------------------------------*/ -/** - * - * This is the default routine for use when the SLIT option is NOT requested. - * - * The option install process will create and fill the transfer vector with - * the address of the proper routine (Main or Stub). The link optimizer will - * strip out of the .DLL the routine that is not used. - * - * @param[in, out] StdHeader Standard Head Pointer - * @param[in] PlatformConfig Config handle for platform specific information - * @param[in, out] SlitPtr Point to Slit Struct including buffer address and length - * - * @retval AGESA_STATUS - */ - -AGESA_STATUS -GetAcpiSlitStub ( - IN OUT AMD_CONFIG_PARAMS *StdHeader, - IN PLATFORM_CONFIGURATION *PlatformConfig, - IN OUT VOID **SlitPtr - ) -{ - return AGESA_UNSUPPORTED; -} -/*---------------------------------------------------------------------------------------*/ -/** - * - * This function generates a complete SLIT table into a memory buffer. - * After completion, this table must be set by the system BIOS into its - * internal ACPI namespace, and linked into the RSDT/XSDT - * - * @param[in, out] StdHeader Standard Head Pointer - * @param[in] PlatformConfig Config handle for platform specific information - * @param[in, out] SlitPtr Point to Slit Struct including buffer address and length - * - * @retval UINT32 AGESA_STATUS - */ -AGESA_STATUS -GetAcpiSlitMain ( - IN OUT AMD_CONFIG_PARAMS *StdHeader, - IN PLATFORM_CONFIGURATION *PlatformConfig, - IN OUT VOID **SlitPtr - ) -{ - UINT8 MaxHops; - UINT8 SocketNum; - UINT8 i; - UINT8 j; - UINT8 *BufferPtr; - UINT8 *SocketTopologyDataPtr; - UINT8 *SocketTopologyPtr; - UINT32 Socket; - BOOLEAN IsProbeFilterEnabled; - ACPI_TABLE_HEADER *CpuSlitHeaderStructPtr; - AGESA_STATUS Flag; - ALLOCATE_HEAP_PARAMS AllocStruct; - L3_FEATURE_FAMILY_SERVICES *FamilyServices; - - MaxHops = 0; - SocketTopologyPtr = NULL; - Flag = AGESA_ERROR; - IsProbeFilterEnabled = FALSE; - - // find out the pointer to the BufferHandle which contains - // Node Topology information - AcpiSlitHBufferFind (StdHeader, &SocketTopologyPtr); - if (SocketTopologyPtr == 0) { - return (Flag); - } - - SocketNum = *SocketTopologyPtr; - - IDS_HDT_CONSOLE (CPU_TRACE, " SLIT is created\n"); - - // create a buffer by calling IBV callout routine - AllocStruct.RequestedBufferSize = (SocketNum * SocketNum) + AMD_ACPI_SLIT_SOCKET_NUM_LENGTH + sizeof (ACPI_TABLE_HEADER); - AllocStruct.BufferHandle = AMD_ACPI_SLIT_BUFFER_HANDLE; - AllocStruct.Persist = HEAP_SYSTEM_MEM; - if (HeapAllocateBuffer (&AllocStruct, StdHeader) != AGESA_SUCCESS) { - return (Flag); - } - *SlitPtr = AllocStruct.BufferPtr; - - //SLIT header - LibAmdMemCopy (*SlitPtr, (VOID *) &CpuSlitHdrStruct, (UINTN) (sizeof (ACPI_TABLE_HEADER)), StdHeader); - CpuSlitHeaderStructPtr = (ACPI_TABLE_HEADER *) *SlitPtr; - CpuSlitHeaderStructPtr->TableLength = (UINT32) AllocStruct.RequestedBufferSize; - BufferPtr = *SlitPtr; - - Flag = AGESA_SUCCESS; - // SLIT body - // Check if Probe Filter is enabled - if (IsFeatureEnabled (L3Features, PlatformConfig, StdHeader)) { - IsProbeFilterEnabled = TRUE; - for (Socket = 0; Socket < GetPlatformNumberOfSockets (); Socket++) { - if (IsProcessorPresent (Socket, StdHeader)) { - GetFeatureServicesOfSocket (&L3FeatureFamilyServiceTable, Socket, (const VOID **) &FamilyServices, StdHeader); - if ((FamilyServices == NULL) || (!FamilyServices->IsHtAssistSupported (FamilyServices, PlatformConfig, StdHeader))) { - IsProbeFilterEnabled = FALSE; - break; - } - } - } - } - - - if (!IsProbeFilterEnabled) { - // probe filter is disabled - // get MaxHops - SocketTopologyDataPtr = SocketTopologyPtr + sizeof (SocketNum); - for (i = 0; i < SocketNum; i++) { - for (j = 0; j < SocketNum; j++) { - if (*SocketTopologyDataPtr > MaxHops) { - MaxHops = *SocketTopologyDataPtr; - } - SocketTopologyDataPtr++; - } - } - - // the Max hop entries have a value of 13 - // and all other entries have 10. - SocketTopologyDataPtr = SocketTopologyPtr + sizeof (SocketNum); - for (i = 0; i < SocketNum; i++) { - for (j = 0; j < SocketNum; j++) { - if (*SocketTopologyDataPtr++ == MaxHops) { - *(BufferPtr + sizeof (ACPI_TABLE_HEADER) + - AMD_ACPI_SLIT_SOCKET_NUM_LENGTH + (i * SocketNum) + j) = 13; - } else { - *(BufferPtr + sizeof (ACPI_TABLE_HEADER) + - AMD_ACPI_SLIT_SOCKET_NUM_LENGTH + (i * SocketNum) + j) = 10; - } - } - } - } else { - // probe filter is enabled - // formula : num_hops * 6 + 10 - SocketTopologyDataPtr = SocketTopologyPtr + sizeof (SocketNum); - for (i = 0; i < SocketNum; i++) { - for (j = 0; j < SocketNum; j++) { - *(BufferPtr + sizeof (ACPI_TABLE_HEADER) + - AMD_ACPI_SLIT_SOCKET_NUM_LENGTH + (i * SocketNum) + j) = - ((*SocketTopologyDataPtr++) * 6) + 10; - } - } - } - - BufferPtr += sizeof (ACPI_TABLE_HEADER); - *((UINT64 *) BufferPtr) = (UINT64) SocketNum; - - //Update SLIT header Checksum - ChecksumAcpiTable ((ACPI_TABLE_HEADER *) *SlitPtr, StdHeader); - - return (Flag); -} - -/*--------------------------------------------------------------------------------------- - * L O C A L F U N C T I O N S - *--------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------*/ -/** - * - * Find out the pointer to the BufferHandle which contains - * Node Topology information - * - * @param[in, out] StdHeader Standard Head Pointer - * @param[in] SocketTopologyPtr Point to the address of Socket Topology - * - */ -VOID -STATIC -AcpiSlitHBufferFind ( - IN OUT AMD_CONFIG_PARAMS *StdHeader, - IN UINT8 **SocketTopologyPtr - ) -{ - LOCATE_HEAP_PTR LocateBuffer; - - LocateBuffer.BufferHandle = HOP_COUNT_TABLE_HANDLE; - if (HeapLocateBuffer (&LocateBuffer, StdHeader) == AGESA_SUCCESS) { - *SocketTopologyPtr = (UINT8 *) LocateBuffer.BufferPtr; - } - - return; -} - - -/* -----------------------------------------------------------------------------*/ -/** - * ReleaseSlitBufferStub - * - * Description: - * This is the default routine for use when the SLIT option is NOT requested. - * - * Parameters: - * @param[in, out] *StdHeader - * - * @retval AGESA_STATUS - * - */ -AGESA_STATUS -ReleaseSlitBufferStub ( - IN OUT AMD_CONFIG_PARAMS *StdHeader - ) -{ - return AGESA_UNSUPPORTED; -} - -/* -----------------------------------------------------------------------------*/ -/** - * ReleaseSlitBuffer - * - * Description: - * Deallocate SLIT buffer - * - * Parameters: - * @param[in, out] *StdHeader - * - * @retval AGESA_STATUS - * - */ -AGESA_STATUS -ReleaseSlitBuffer ( - IN OUT AMD_CONFIG_PARAMS *StdHeader - ) -{ - HeapDeallocateBuffer ((UINT32) HOP_COUNT_TABLE_HANDLE, StdHeader); - - return AGESA_SUCCESS; -} diff --git a/src/vendorcode/amd/agesa/f12/Proc/CPU/Feature/cpuSrat.c b/src/vendorcode/amd/agesa/f12/Proc/CPU/Feature/cpuSrat.c deleted file mode 100644 index 8a59886b89..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/CPU/Feature/cpuSrat.c +++ /dev/null @@ -1,617 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * AMD SRAT, ACPI table related API functions. - * - * Contains code that Create the APCI SRAT Table after early reset. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: CPU - * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $ - * - */ -/* - ****************************************************************************** - * - * Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - ***************************************************************************/ - - -/*---------------------------------------------------------------------------- - * This file provides functions, that will generate SRAT tables - *---------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------- - * M O D U L E S U S E D - *---------------------------------------------------------------------------------------- - */ -#include "AGESA.h" -#include "amdlib.h" -#include "OptionSrat.h" -#include "heapManager.h" -#include "cpuRegisters.h" -#include "cpuServices.h" -#include "cpuLateInit.h" -#include "Ids.h" -#include "Filecode.h" -CODE_GROUP (G3_DXE) -RDATA_GROUP (G3_DXE) - -#define FILECODE PROC_CPU_FEATURE_CPUSRAT_FILECODE -/*---------------------------------------------------------------------------------------- - * D E F I N I T I O N S A N D M A C R O S - *---------------------------------------------------------------------------------------- - */ -extern OPTION_SRAT_CONFIGURATION OptionSratConfiguration; // global user config record - -#define NodeID 0x60 -#define FOURGB 0x010000 - -/*---------------------------------------------------------------------------------------- - * T Y P E D E F S A N D S T R U C T U R E S - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------- - * All of the DATA should be defined in _CODE segment. - * Use ROMDATA to specify that it belongs to _CODE. - *---------------------------------------------------------------------------- - */ -STATIC CPU_SRAT_HEADER ROMDATA CpuSratHdrStruct = -{ - {'S','R','A','T'}, - 0, - 2, - 0, - {'A','M','D',' ',' ',' '}, - {'A','G','E','S','A',' ',' ',' '}, - 1, - {'A','M','D',' '}, - 1, - 1, - {0, 0, 0, 0, 0, 0, 0, 0} -}; - -/*---------------------------------------------------------------------------------------- - * P R O T O T Y P E S O F L O C A L F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ -UINT8 -STATIC -*MakeApicEntry ( - IN UINT8 ApicId, - IN UINT8 Domain, - IN UINT8 *BufferLocPtr - ); - -UINT8 -STATIC -*FillMemoryForCurrentNode ( - IN UINT8 *PDomain, - IN OUT UINT8 *PDomainForBase640K, - IN UINT8 Node, - IN OUT UINT8 *BufferLocPtr, - IN OUT AMD_CONFIG_PARAMS *StdHeader - ); - -UINT8 -STATIC -*MakeMemEntry ( - IN UINT8 PDomain, - IN UINT8 Node, - IN UINT32 Base, - IN UINT32 Size, - IN UINT8 *BufferLocPtr - ); - -/*---------------------------------------------------------------------------------------- - * E X P O R T E D F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ -AGESA_STATUS -GetAcpiSratStub ( - IN OUT AMD_CONFIG_PARAMS *StdHeader, - IN OUT VOID **SratPtr - ); - -AGESA_STATUS -GetAcpiSratMain ( - IN OUT AMD_CONFIG_PARAMS *StdHeader, - IN OUT VOID **SratPtr - ); - -/*---------------------------------------------------------------------------------------*/ -/** - * - * This function will generate a complete Static Resource Affinity Table - * i.e. SRAT into a memory buffer. After completion, this table must be set - * by the system BIOS into its internal ACPI name space. - * - * @param[in, out] StdHeader Standard Head Pointer - * @param[in, out] SratPtr Point to Srat Struct including buffer address and length - * - * @retval AGESA_STATUS - */ - -AGESA_STATUS -CreateAcpiSrat ( - IN OUT AMD_CONFIG_PARAMS *StdHeader, - IN OUT VOID **SratPtr - ) -{ - AGESA_TESTPOINT (TpProcCpuEntrySrat, StdHeader); - return ((*(OptionSratConfiguration.SratFeature)) (StdHeader, SratPtr)); -} - -/*---------------------------------------------------------------------------------------*/ -/** - * - * This is the default routine for use when the SRAT option is NOT requested. - * - * The option install process will create and fill the transfer vector with - * the address of the proper routine (Main or Stub). The link optimizer will - * strip out of the .DLL the routine that is not used. - * - * @param[in, out] StdHeader Standard Head Pointer - * @param[in, out] SratPtr Point to Srat Struct including buffer address and length - * - * @retval AGESA_STATUS - */ - -AGESA_STATUS -GetAcpiSratStub ( - IN OUT AMD_CONFIG_PARAMS *StdHeader, - IN OUT VOID **SratPtr - ) -{ - return AGESA_UNSUPPORTED; -} -/*---------------------------------------------------------------------------------------*/ -/** - * - * This function will generate a complete Static Resource Affinity Table - * i.e. SRAT into a memory buffer. After completion, this table must be set - * by the system BIOS into its internal ACPI name space. - * - * @param[in, out] StdHeader Standard Head Pointer - * @param[in, out] SratPtr Point to Srat Struct including buffer address and length - * - * @retval AGESA_STATUS - */ -AGESA_STATUS -GetAcpiSratMain ( - IN OUT AMD_CONFIG_PARAMS *StdHeader, - IN OUT VOID **SratPtr - ) -{ - UINT8 *BufferPtr; - UINT8 NodeNum; - UINT8 NodeCount; - UINT8 PDomain; - UINT8 PDomainForBase640K; - UINT32 Socket; - UINT32 Module; - UINT32 LowCore; - UINT32 HighCore; - UINT32 CoreNum; - UINT32 RegVal; - UINT32 tempVar_32; - AMD_APIC_PARAMS ApicParams; - PCI_ADDR PciAddress; - CPU_SRAT_HEADER *CpuSratHeaderStructPtr; - ALLOCATE_HEAP_PARAMS AllocParams; - - // Get Node count - PciAddress.AddressValue = MAKE_SBDFO (0, 0, LOW_NODE_DEVICEID, FUNC_0, NodeID); - LibAmdPciRead (AccessWidth32 , PciAddress, &RegVal, StdHeader); - NodeCount = (UINT8) (((RegVal >> 4) & 0x7) + 1); - - // The worst-case buffer size to request is for the SRAT table header, one - // entree for special region (base 640k block), two memory - // regions per node, and APIC entries for each core in the system. - tempVar_32 = (sizeof (CPU_SRAT_HEADER)) + (sizeof (CPU_SRAT_MEMORY_ENTRY)) - + ((UINT32) NodeCount * (2 * (sizeof (CPU_SRAT_MEMORY_ENTRY)) - + ((UINT32) GetActiveCoresInCurrentModule (StdHeader) * sizeof (CPU_SRAT_APIC_ENTRY)))); - - if (*SratPtr == NULL) { - // - // Allocate a buffer - // - AllocParams.RequestedBufferSize = tempVar_32; - AllocParams.BufferHandle = AMD_SRAT_INFO_BUFFER_HANDLE; - AllocParams.Persist = HEAP_SYSTEM_MEM; - - AGESA_TESTPOINT (TpProcCpuBeforeAllocateSratBuffer, StdHeader); - if (HeapAllocateBuffer (&AllocParams, StdHeader) != AGESA_SUCCESS) { - return AGESA_ERROR; - } - AGESA_TESTPOINT (TpProcCpuAfterAllocateSratBuffer, StdHeader); - - *SratPtr = AllocParams.BufferPtr; - } - - IDS_HDT_CONSOLE (CPU_TRACE, " SRAT is created\n"); - - CpuSratHeaderStructPtr = (CPU_SRAT_HEADER *) *SratPtr; - BufferPtr = (UINT8 *) *SratPtr; - - // Copy acpiSRATHeader -> data buffer - LibAmdMemCopy (*SratPtr, (VOID *) &CpuSratHdrStruct, (UINTN) (sizeof (CPU_SRAT_HEADER)), StdHeader); - - BufferPtr += sizeof (CPU_SRAT_HEADER); - - // Place all memory and IO affinity entries - NodeNum = 0; - PDomain = 0; - PDomainForBase640K = 0xFF; - ApicParams.StdHeader = *StdHeader; - while (NodeNum < NodeCount) { - GetSocketModuleOfNode ((UINT32) NodeNum, &Socket, &Module, StdHeader); - GetGivenModuleCoreRange (Socket, Module, &LowCore, &HighCore, StdHeader); - BufferPtr = FillMemoryForCurrentNode (&PDomain, &PDomainForBase640K, NodeNum, BufferPtr, StdHeader); - for (CoreNum = LowCore; CoreNum <= HighCore; CoreNum++) { - ApicParams.Socket = (UINT8) Socket; - ApicParams.Core = (UINT8) CoreNum; - AmdGetApicId (&ApicParams); - if (ApicParams.IsPresent) { - BufferPtr = MakeApicEntry (ApicParams.ApicAddress, PDomain, BufferPtr); - } - } - - NodeNum++; - PDomain = NodeNum; - } - - // Store size in table (current buffer offset - buffer start offset) - CpuSratHeaderStructPtr->TableLength = (UINT32) (BufferPtr - (UINT8 *) CpuSratHeaderStructPtr); - - //Update SSDT header Checksum - ChecksumAcpiTable ((ACPI_TABLE_HEADER *) CpuSratHeaderStructPtr, StdHeader); - - return AGESA_SUCCESS; -} - - -/*---------------------------------------------------------------------------------------- - * L O C A L F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------*/ -/** - * - * This function will build Memory entry for current node. - * Note that we only create a memory affinity entry if we find one - * that matches the current node. This makes an easier to read table - * though it is not necessary. - * - * @param[in] PDomain Proximity Domain - * @param[in, out] PDomainForBase640K The PDomain for Base 640K - * @param[in] Node The number of Node - * @param[in, out] BufferLocPtr Point to the address of buffer - * @param[in, out] StdHeader Standard Head Pointer - * - * @retval UINT8 *(New buffer location ptr) - */ -UINT8 -STATIC -*FillMemoryForCurrentNode ( - IN UINT8 *PDomain, - IN OUT UINT8 *PDomainForBase640K, - IN UINT8 Node, - IN OUT UINT8 *BufferLocPtr, - IN OUT AMD_CONFIG_PARAMS *StdHeader - ) -{ - UINT32 ValueLimit; - UINT32 ValueTOM; - BOOLEAN isModified; - UINT8 Domain; - UINT32 RegVal; - UINT32 DramLeng; - UINT32 DramBase; - UINT32 DramLimit; - UINT32 OffsetRegs; - PCI_ADDR PciAddress; - UINT64 MsrValue; - UINT32 TopOfMemoryAbove4Gb; - - Domain = *PDomain; - - PciAddress.Address.Segment = 0; - PciAddress.Address.Bus = 0; - PciAddress.Address.Device = LOW_NODE_DEVICEID; - PciAddress.Address.Function = FUNC_1; - - for (OffsetRegs = DRAMBase0; OffsetRegs < MMIOBase0; OffsetRegs += 8) { - isModified = FALSE; // FALSE means normal update procedure - // Get DRAM Base Address - PciAddress.Address.Register = OffsetRegs; - LibAmdPciRead (AccessWidth32, PciAddress, &DramBase, StdHeader); - if ((DramBase & 3) != 3) { - // 0:1 set if memory range enabled - // Not set, so we don't have an enabled range - continue; // Proceed to next Base register - } - - // Get DRAM Limit - PciAddress.Address.Register = OffsetRegs + 4; - LibAmdPciRead (AccessWidth32, PciAddress, &DramLimit, StdHeader); - if (DramLimit == 0xFFFFFFFF) { - // Node not installed(all FF's)? - continue; // Proceed to next Base register - } - - if ((DramLimit & 0xFF) != Node) { - // Check if Destination Node ID is current node - continue; // Proceed to next Base register - } - - // We only add an entry now if detected range belongs to current node/PDomain - PciAddress.Address.Register = OffsetRegs + 0x104; - LibAmdPciRead (AccessWidth32, PciAddress, &RegVal, StdHeader); - - DramLimit = (((RegVal & 0xFF) << 16) | (DramLimit >> 16)); // Get DRAM Limit addr [47:24] - DramLimit++; // Add 1 for potential length - DramLimit <<= 8; - - // Get DRAM Base Address - PciAddress.Address.Register = OffsetRegs + 0x100; - LibAmdPciRead (AccessWidth32, PciAddress, &RegVal, StdHeader); - DramBase = ((((RegVal & 0xFF) << 24) | (DramBase >> 8)) & 0xFFFFFF00); // Get DRAM Base Base value [47:24] - DramLeng = DramLimit - DramBase; // Subtract base from limit to get length - - // Leave hole for conventional memory (Less than 640K). It must be on CPU 0. - if (DramBase == 0) { - if (*PDomainForBase640K == 0xFF) { - // It is the first time that the range start at 0. - // If Yes, then Place 1MB memory gap and save Domain to PDomainForBase640K - BufferLocPtr = MakeMemEntry ( - Domain, - Node, - 0, // Base = 0 - 0xA0000 >> 16, // Put it into format used in DRAM regs.. - BufferLocPtr - ); - DramBase += 0x10; // Add 1MB, so range = 1MB to Top of Region - DramLeng -= 0x10; // Also subtract 1MB from the length - *PDomainForBase640K = Domain; // Save Domain number for memory Less than 640K - } else { - // If No, there are more than one memory range less than 640K, it should that - // node interleaving is enabled. All nodes have the same memory ranges - // and all cores in these nodes belong to the same domain. - *PDomain = *PDomainForBase640K; - return (BufferLocPtr); - } - } - LibAmdMsrRead (TOP_MEM, &MsrValue, StdHeader); - ValueTOM = (UINT32) MsrValue >> 16; // Save it in 39:24 format - ValueLimit = DramBase + DramLeng; // We need to know how large region is - - LibAmdMsrRead (SYS_CFG, &MsrValue, StdHeader); - if ((MsrValue & BIT21) != 0) { - LibAmdMsrRead (TOP_MEM2, &MsrValue, StdHeader); - TopOfMemoryAbove4Gb = (UINT32) (MsrValue >> 16); // Save it in 47:16 format - } else { - TopOfMemoryAbove4Gb = 0xFFFFFFFF; - } - - // SPECIAL CASES: - // - // Several conditions require that we process the values of the memory range differently. - // Here are descriptions of the corner cases. - // - // 1. TRUNCATE LOW - Memory range starts below TOM, ends in TOM (memory hole). For this case, - // the range must be truncated to end at TOM. - // ******************************* ******************************* - // * * * -> * * - // ******************************* ******************************* - // 2 TOM 4 2 TOM - // - // 2. TRUNCATE HIGH - Memory range starts below 4GB, ends above 4GB. This is handled by changing the - // start base to 4GB. - // **************** ********** - // * * * -> * * - // **************** ********** - // TOM 3.8 4 6 TOM 3.8 4 6 - // - // 3. Memory range starts below TOM, ends above 4GB. For this case, the range must be truncated - // to end at TOM. Note that this scenario creates two ranges, as the second comparison below - // will find that it ends above 4GB since base and limit have been restored after first truncation, - // and a second range will be written based at 4GB ending at original end address. - // ******************************* **************** ********** - // * * * * -> * * * * - // ******************************* **************** ********** - // 2 TOM 4 6 2 TOM 4 6 - // - // 4. Memory range starts above TOM, ends below or equal to 4GB. This invalid range should simply - // be ignored. - // ******* - // * * -> < NULL > - // ******* - // TOM 3.8 4 - // - // 5. Memory range starts below TOM2, and ends beyond TOM2. This range must be truncated to TOM2. - // ************************ ******************************* - // * * * -> * * - // ************************ ******************************* - // 768 TOM2 1024 768 TOM2 - // - // 6. Memory range starts above TOM2. This invalid range should simply be ignored. - // ******************** - // * * -> < NULL > - // ******************** - // TOM2 1024 1280 - - if (((DramBase < ValueTOM) && (ValueLimit <= FOURGB) && (ValueLimit > ValueTOM)) - || ((DramBase < ValueTOM) && (ValueLimit > FOURGB))) { - // TRUNCATE LOW!!! Shrink entry below TOM... - // Base = DramBase, Size = TOM - DramBase - BufferLocPtr = MakeMemEntry (Domain, Node, DramBase, (ValueTOM - DramBase), BufferLocPtr); - isModified = TRUE; - } - - if ((ValueLimit > FOURGB) && (DramBase < FOURGB)) { - // TRUNCATE HIGH!!! Shrink entry above 4GB... - // Size = Base + Size - 4GB, Base = 4GB - BufferLocPtr = MakeMemEntry (Domain, Node, FOURGB, (DramLeng + DramBase - FOURGB), BufferLocPtr); - isModified = TRUE; - } - - if ((DramBase >= ValueTOM) && (ValueLimit <= FOURGB)) { - // IGNORE!!! Entry located entirely within memory hole - isModified = TRUE; - } - - if ((DramBase < TopOfMemoryAbove4Gb) && (ValueLimit > TopOfMemoryAbove4Gb)) { - // Truncate to TOM2 - // Base = DramBase, Size = TOM2 - DramBase - BufferLocPtr = MakeMemEntry (Domain, Node, DramBase, (TopOfMemoryAbove4Gb - DramBase), BufferLocPtr); - isModified = TRUE; - } - - if (DramBase >= TopOfMemoryAbove4Gb) { - // IGNORE!!! Entry located entirely above TOM2 - isModified = TRUE; - } - - // If special range(isModified), we are done. - // If not, finally write the memory entry. - if (isModified == FALSE) { - // Finally write the memory entry. - BufferLocPtr = MakeMemEntry (Domain, Node, DramBase, DramLeng, BufferLocPtr); - } - - } // for ( OffsetRegs = DRAMBase0; ... ) - - return (BufferLocPtr); -} // FillMemoryForCurrentNode() - - -/*---------------------------------------------------------------------------------------*/ -/** - * This function will add APIC entry. - * - * @param[in] ApicId APIC ID number - * @param[in] Domain Domain number - * @param[in] BufferLocPtr Point to the address of buffer - * - * @retval UINT8 *(New buffer location ptr) - */ -UINT8 -STATIC -*MakeApicEntry ( - IN UINT8 ApicId, - IN UINT8 Domain, - IN UINT8 *BufferLocPtr - ) -{ - CPU_SRAT_APIC_ENTRY *psSratApicEntry; - UINT8 ReservedBytes; - - psSratApicEntry = (CPU_SRAT_APIC_ENTRY *)BufferLocPtr; - - psSratApicEntry->Type = AE_APIC; - psSratApicEntry->Length = (UINT8)sizeof (CPU_SRAT_APIC_ENTRY); - psSratApicEntry->Domain = Domain; - psSratApicEntry->ApicId = ApicId; - psSratApicEntry->Flags = ENABLED; - psSratApicEntry->LSApicEid = 0; - for (ReservedBytes = 0; ReservedBytes < (UINT8)sizeof (psSratApicEntry->Reserved); ReservedBytes++) { - psSratApicEntry->Reserved[ReservedBytes] = 0; - } - return (BufferLocPtr + (UINT8)sizeof (CPU_SRAT_APIC_ENTRY)); -} // MakeApicEntry - - -/*---------------------------------------------------------------------------------------*/ -/** - * - * This function will add Memory entry. - * - * Parameters: - * @param[in] PDomain Proximity Domain - * @param[in] Node The number of Node - * @param[in] Base Memory Base - * @param[in] Size Memory Size - * @param[in] BufferLocPtr Point to the address of buffer - * - * @retval UINT8 * (new buffer location ptr) - */ -UINT8 -STATIC -*MakeMemEntry ( - IN UINT8 PDomain, - IN UINT8 Node, - IN UINT32 Base, - IN UINT32 Size, - IN UINT8 *BufferLocPtr - ) -{ - CPU_SRAT_MEMORY_ENTRY *psSratMemEntry; - UINT8 ReservedBytes; - - psSratMemEntry = (CPU_SRAT_MEMORY_ENTRY *)BufferLocPtr; - - psSratMemEntry->Type = AE_MEMORY; // [0] = Memory Entry - psSratMemEntry->Length = (UINT8)sizeof (CPU_SRAT_MEMORY_ENTRY); // [1] = 40 - psSratMemEntry->Domain = PDomain; // [2] = Proximity Domain - - // [6-7] = Reserved - for (ReservedBytes = 0; ReservedBytes < (UINT8)sizeof (psSratMemEntry->Reserved1); ReservedBytes++) { - psSratMemEntry->Reserved1[ReservedBytes] = 0; - } - - // [8-11] = Keep 31:0 of address only -> Base Addr Low - psSratMemEntry->BaseAddrLow = Base << 16; - - // [12-15] = Keep 39:32 of address only -> Base Addr High - psSratMemEntry->BaseAddrHigh = Base >> 16; - - // [16-19] = Keep 31:0 of address only -> Length Low - psSratMemEntry->LengthAddrLow = Size << 16; - - // [20-23] = Keep 39:32 of address only -> Length High - psSratMemEntry->LengthAddrHigh = Size >> 16; - - // [24-27] = Reserved - for (ReservedBytes = 0; ReservedBytes < (UINT8)sizeof (psSratMemEntry->Reserved2); ReservedBytes++) { - psSratMemEntry->Reserved2[ReservedBytes] = 0; - } - - // [28-31] = Flags - psSratMemEntry->Flags = ENABLED; - - // [32-40] = Reserved - for (ReservedBytes = 0; ReservedBytes < (UINT8)sizeof (psSratMemEntry->Reserved3); ReservedBytes++) { - psSratMemEntry->Reserved3[ReservedBytes] = 0; - } - return (BufferLocPtr + (UINT8)sizeof (CPU_SRAT_MEMORY_ENTRY)); -} // MakeMemEntry() - diff --git a/src/vendorcode/amd/agesa/f12/Proc/CPU/Feature/cpuSwC1e.c b/src/vendorcode/amd/agesa/f12/Proc/CPU/Feature/cpuSwC1e.c deleted file mode 100644 index 7282832831..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/CPU/Feature/cpuSwC1e.c +++ /dev/null @@ -1,178 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * AMD AGESA CPU SW C1e feature support code. - * - * Contains code that declares the AGESA CPU C1e related APIs - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: CPU/Feature - * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $ - * - */ -/* - ****************************************************************************** - * - * Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - ****************************************************************************** - */ - -/*---------------------------------------------------------------------------------------- - * M O D U L E S U S E D - *---------------------------------------------------------------------------------------- - */ -#include "AGESA.h" -#include "amdlib.h" -#include "Ids.h" -#include "cpuRegisters.h" -#include "cpuApicUtilities.h" -#include "cpuServices.h" -#include "GeneralServices.h" -#include "cpuFamilyTranslation.h" -#include "Topology.h" -#include "cpuFeatures.h" -#include "cpuSwC1e.h" -#include "cpuHwC1e.h" -#include "Filecode.h" -CODE_GROUP (G1_PEICC) -RDATA_GROUP (G1_PEICC) - -#define FILECODE PROC_CPU_FEATURE_CPUSWC1E_FILECODE -/*---------------------------------------------------------------------------------------- - * D E F I N I T I O N S A N D M A C R O S - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------- - * T Y P E D E F S A N D S T R U C T U R E S - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------- - * P R O T O T Y P E S O F L O C A L F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------- - * E X P O R T E D F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ -extern CPU_FAMILY_SUPPORT_TABLE SwC1eFamilyServiceTable; - -/*---------------------------------------------------------------------------------------*/ -/** - * Should software C1e be enabled - * - * @param[in] PlatformConfig Contains the runtime modifiable feature input data. - * @param[in] StdHeader Config Handle for library, services. - * - * @retval TRUE SW C1e is supported. - * @retval FALSE SW C1e not supported. - * - */ -BOOLEAN -STATIC -IsSwC1eFeatureEnabled ( - IN PLATFORM_CONFIGURATION *PlatformConfig, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - BOOLEAN IsEnabled; - BOOLEAN IsOtherC1eEnabled; - AP_MAILBOXES ApMailboxes; - SW_C1E_FAMILY_SERVICES *SwFamilyServices; - - ASSERT (PlatformConfig->C1eMode < MaxC1eMode); - IsEnabled = FALSE; - - // Check whether software C1e is enabled only if other C1e methods is/are not supported - // or if the platform specifically uses C1eModeSoftwareDeprecated. - IsOtherC1eEnabled = (IsFeatureEnabled (HardwareC1e, PlatformConfig, StdHeader) || - IsFeatureEnabled (MsgBasedC1e, PlatformConfig, StdHeader)); - if ((PlatformConfig->C1eMode == C1eModeSoftwareDeprecated) || - ((!IsOtherC1eEnabled) && ((PlatformConfig->C1eMode == C1eModeHardwareSoftwareDeprecated) || (PlatformConfig->C1eMode == C1eModeAuto)))) { - ASSERT ((PlatformConfig->C1ePlatformData1 < 0x10000) && (PlatformConfig->C1ePlatformData1 != 0)); - ASSERT (PlatformConfig->C1ePlatformData2 < 0x100); - if ((PlatformConfig->C1ePlatformData1 != 0) && (PlatformConfig->C1ePlatformData1 < 0xFFFE) && (PlatformConfig->C1ePlatformData2 < 0xFF)) { - if (!IsNonCoherentHt1 (StdHeader)) { - if (GetNumberOfProcessors (StdHeader) == 1) { - GetApMailbox (&ApMailboxes.ApMailInfo.Info, StdHeader); - if (ApMailboxes.ApMailInfo.Fields.ModuleType == 0) { - GetFeatureServicesOfCurrentCore (&SwC1eFamilyServiceTable, (const VOID **)&SwFamilyServices, StdHeader); - if (SwFamilyServices != NULL) { - IsEnabled = SwFamilyServices->IsSwC1eSupported (SwFamilyServices, StdHeader); - } - } - } - } - } - } - return IsEnabled; -} - -/*---------------------------------------------------------------------------------------*/ -/** - * Enable Software C1e - * - * @param[in] EntryPoint Timepoint designator. - * @param[in] PlatformConfig Contains the runtime modifiable feature input data. - * @param[in] StdHeader Config Handle for library, services. - * - * @return The most severe status of any family specific service. - * - */ -AGESA_STATUS -STATIC -InitializeSwC1eFeature ( - IN UINT64 EntryPoint, - IN PLATFORM_CONFIGURATION *PlatformConfig, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - AGESA_STATUS AgesaStatus; - SW_C1E_FAMILY_SERVICES *FamilyServices; - - AgesaStatus = AGESA_SUCCESS; - - IDS_HDT_CONSOLE (CPU_TRACE, " SW C1e is enabled\n"); - - if (IsWarmReset (StdHeader)) { - GetFeatureServicesOfCurrentCore (&SwC1eFamilyServiceTable, (const VOID **)&FamilyServices, StdHeader); - AgesaStatus = FamilyServices->InitializeSwC1e (FamilyServices, EntryPoint, PlatformConfig, StdHeader); - } - - return AgesaStatus; -} - -CONST CPU_FEATURE_DESCRIPTOR ROMDATA CpuFeatureSwC1e = -{ - SoftwareC1e, - CPU_FEAT_AFTER_PM_INIT, - IsSwC1eFeatureEnabled, - InitializeSwC1eFeature -}; \ No newline at end of file diff --git a/src/vendorcode/amd/agesa/f12/Proc/CPU/Feature/cpuSwC1e.h b/src/vendorcode/amd/agesa/f12/Proc/CPU/Feature/cpuSwC1e.h deleted file mode 100644 index 1810eb5e2e..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/CPU/Feature/cpuSwC1e.h +++ /dev/null @@ -1,119 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * AMD AGESA CPU SW C1e Functions declarations. - * - * Contains code that declares the AGESA CPU C1e related APIs - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: CPU/Feature - * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $ - * - */ -/* - ****************************************************************************** - * - * Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - ****************************************************************************** - */ - -#ifndef _CPU_SW_C1E_H_ -#define _CPU_SW_C1E_H_ - -/*---------------------------------------------------------------------------------------- - * M I X E D (Definitions And Macros / Typedefs, Structures, Enums) - *---------------------------------------------------------------------------------------- - */ -// Forward declaration needed for multi-structure mutual references -AGESA_FORWARD_DECLARATION (SW_C1E_FAMILY_SERVICES); - -/*---------------------------------------------------------------------------------------- - * D E F I N I T I O N S A N D M A C R O S - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------- - * T Y P E D E F S A N D S T R U C T U R E S - *---------------------------------------------------------------------------------------- - */ -/*---------------------------------------------------------------------------------------*/ -/** - * Family specific call to check if software C1e is supported. - * - * @param[in] SwC1eServices Software C1e services. - * @param[in] StdHeader Config Handle for library, services. - * - * @retval TRUE SW C1e is supported. - * @retval FALSE SW C1e is not supported. - * - */ -typedef BOOLEAN F_SW_C1E_IS_SUPPORTED ( - IN SW_C1E_FAMILY_SERVICES *SwC1eServices, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -/// Reference to a Method -typedef F_SW_C1E_IS_SUPPORTED *PF_SW_C1E_IS_SUPPORTED; - -/*---------------------------------------------------------------------------------------*/ -/** - * Family specific call to enable software C1e. - * - * @param[in] SwC1eServices Software C1e services. - * @param[in] EntryPoint Timepoint designator. - * @param[in] PlatformConfig Contains the runtime modifiable feature input data. - * @param[in] StdHeader Config Handle for library, services. - * - * @return Family specific error value. - * - */ -typedef AGESA_STATUS F_SW_C1E_INIT ( - IN SW_C1E_FAMILY_SERVICES *SwC1eServices, - IN UINT64 EntryPoint, - IN PLATFORM_CONFIGURATION *PlatformConfig, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -/// Reference to a Method -typedef F_SW_C1E_INIT *PF_SW_C1E_INIT; - -/** - * Provide the interface to the software C1e Family Specific Services. - * - * Use the methods or data in this struct to adapt the feature code to a specific cpu family or model (or stepping!). - * Each supported Family must provide an implementation for all methods in this interface, even if the - * implementation is a CommonReturn(). - */ -struct _SW_C1E_FAMILY_SERVICES { - UINT16 Revision; ///< Interface version - // Public Methods. - PF_SW_C1E_IS_SUPPORTED IsSwC1eSupported; ///< Method: Family specific call to check if software C1e is supported. - PF_SW_C1E_INIT InitializeSwC1e; ///< Method: Family specific call to enable software C1e. -}; - -#endif // _CPU_SW_C1E_H_ diff --git a/src/vendorcode/amd/agesa/f12/Proc/CPU/Feature/cpuWhea.c b/src/vendorcode/amd/agesa/f12/Proc/CPU/Feature/cpuWhea.c deleted file mode 100644 index bdef5ba6d1..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/CPU/Feature/cpuWhea.c +++ /dev/null @@ -1,283 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * AMD WHEA Table Creation API, and related functions. - * - * Contains code that produce the ACPI WHEA related information. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: CPU - * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $ - * - */ -/* - ****************************************************************************** - * - * Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - ****************************************************************************** - */ - -/*---------------------------------------------------------------------------------------- - * M O D U L E S U S E D - *---------------------------------------------------------------------------------------- - */ -#include "AGESA.h" -#include "amdlib.h" -#include "OptionWhea.h" -#include "cpuLateInit.h" -#include "heapManager.h" -#include "cpuRegisters.h" -#include "cpuFamilyTranslation.h" -#include "Ids.h" -#include "Filecode.h" -CODE_GROUP (G3_DXE) -RDATA_GROUP (G3_DXE) - -#define FILECODE PROC_CPU_FEATURE_CPUWHEA_FILECODE -/*---------------------------------------------------------------------------------------- - * D E F I N I T I O N S A N D M A C R O S - *--------------------------------------------------------------------------------------- - */ - -extern OPTION_WHEA_CONFIGURATION OptionWheaConfiguration; // global user config record - -/*---------------------------------------------------------------------------------------- - * T Y P E D E F S A N D S T R U C T U R E S - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------- - * P R O T O T Y P E S O F L O C A L F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ -VOID -STATIC -CreateHestBank ( - IN AMD_HEST_BANK *HestBankPtr, - IN UINT8 BankNum, - IN AMD_WHEA_INIT_DATA *WheaInitDataPtr - ); - -/*---------------------------------------------------------------------------------------- - * E X P O R T E D F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ -AGESA_STATUS -GetAcpiWheaStub ( - IN OUT AMD_CONFIG_PARAMS *StdHeader, - IN OUT VOID **WheaMcePtr, - IN OUT VOID **WheaCmcPtr - ); - -AGESA_STATUS -GetAcpiWheaMain ( - IN OUT AMD_CONFIG_PARAMS *StdHeader, - IN OUT VOID **WheaMcePtr, - IN OUT VOID **WheaCmcPtr - ); - -/*---------------------------------------------------------------------------------------*/ -/** - * - * It will create the ACPI table of WHEA and return the pointer to the table. - * - * @param[in, out] StdHeader Standard Head Pointer - * @param[in, out] WheaMcePtr Point to Whea Hest Mce table - * @param[in, out] WheaCmcPtr Point to Whea Hest Cmc table - * - * @retval AGESA_STATUS - */ -AGESA_STATUS -CreateAcpiWhea ( - IN OUT AMD_CONFIG_PARAMS *StdHeader, - IN OUT VOID **WheaMcePtr, - IN OUT VOID **WheaCmcPtr - ) -{ - AGESA_TESTPOINT (TpProcCpuEntryWhea, StdHeader); - return ((*(OptionWheaConfiguration.WheaFeature)) (StdHeader, WheaMcePtr, WheaCmcPtr)); -} - -/*---------------------------------------------------------------------------------------*/ -/** - * - * This is the default routine for use when the WHEA option is NOT requested. - * - * The option install process will create and fill the transfer vector with - * the address of the proper routine (Main or Stub). The link optimizer will - * strip out of the .DLL the routine that is not used. - * - * @param[in, out] StdHeader Standard Head Pointer - * @param[in, out] WheaMcePtr Point to Whea Hest Mce table - * @param[in, out] WheaCmcPtr Point to Whea Hest Cmc table - * - * @retval AGESA_STATUS - */ - -AGESA_STATUS -GetAcpiWheaStub ( - IN OUT AMD_CONFIG_PARAMS *StdHeader, - IN OUT VOID **WheaMcePtr, - IN OUT VOID **WheaCmcPtr - ) -{ - return AGESA_UNSUPPORTED; -} - -/*---------------------------------------------------------------------------------------*/ -/** - * - * It will create the ACPI tale of WHEA and return the pointer to the table. - * - * @param[in, out] StdHeader Standard Head Pointer - * @param[in, out] WheaMcePtr Point to Whea Hest Mce table - * @param[in, out] WheaCmcPtr Point to Whea Hest Cmc table - * - * @retval UINT32 AGESA_STATUS - */ -AGESA_STATUS -GetAcpiWheaMain ( - IN OUT AMD_CONFIG_PARAMS *StdHeader, - IN OUT VOID **WheaMcePtr, - IN OUT VOID **WheaCmcPtr - ) -{ - UINT8 BankNum; - UINT8 Entries; - UINT16 HestMceTableSize; - UINT16 HestCmcTableSize; - UINT64 MsrData; - AMD_HEST_MCE_TABLE *HestMceTablePtr; - AMD_HEST_CMC_TABLE *HestCmcTablePtr; - AMD_HEST_BANK *HestBankPtr; - AMD_WHEA_INIT_DATA *WheaInitDataPtr; - ALLOCATE_HEAP_PARAMS AllocParams; - CPU_SPECIFIC_SERVICES *FamilySpecificServices; - - FamilySpecificServices = NULL; - - IDS_HDT_CONSOLE (CPU_TRACE, " WHEA is created\n"); - - // step 1: calculate Hest table size - LibAmdMsrRead (MSR_MCG_CAP, &MsrData, StdHeader); - BankNum = (UINT8) (((MSR_MCG_CAP_STRUCT *) (&MsrData))->Count); - if (BankNum == 0) { - return AGESA_ERROR; - } - - GetCpuServicesOfCurrentCore ((const CPU_SPECIFIC_SERVICES **)&FamilySpecificServices, StdHeader); - FamilySpecificServices->GetWheaInitData (FamilySpecificServices, (const VOID **)&WheaInitDataPtr, &Entries, StdHeader); - - ASSERT (WheaInitDataPtr->HestBankNum <= BankNum); - - HestMceTableSize = sizeof (AMD_HEST_MCE_TABLE) + WheaInitDataPtr->HestBankNum * sizeof (AMD_HEST_BANK); - HestCmcTableSize = sizeof (AMD_HEST_CMC_TABLE) + WheaInitDataPtr->HestBankNum * sizeof (AMD_HEST_BANK); - - HestMceTablePtr = (AMD_HEST_MCE_TABLE *) *WheaMcePtr; - HestCmcTablePtr = (AMD_HEST_CMC_TABLE *) *WheaCmcPtr; - - // step 2: allocate a buffer by callback function - if ((HestMceTablePtr == NULL) || (HestCmcTablePtr == NULL)) { - AllocParams.RequestedBufferSize = (UINT32) (HestMceTableSize + HestCmcTableSize); - AllocParams.BufferHandle = AMD_WHEA_BUFFER_HANDLE; - AllocParams.Persist = HEAP_SYSTEM_MEM; - - AGESA_TESTPOINT (TpProcCpuBeforeAllocateWheaBuffer, StdHeader); - if (HeapAllocateBuffer (&AllocParams, StdHeader) != AGESA_SUCCESS) { - return AGESA_ERROR; - } - AGESA_TESTPOINT (TpProcCpuAfterAllocateWheaBuffer, StdHeader); - - HestMceTablePtr = (AMD_HEST_MCE_TABLE *) AllocParams.BufferPtr; - HestCmcTablePtr = (AMD_HEST_CMC_TABLE *) ((UINT8 *) (HestMceTablePtr + 1) + (WheaInitDataPtr->HestBankNum * sizeof (AMD_HEST_BANK))); - } - - // step 3: fill in Hest MCE table - HestMceTablePtr->TblLength = HestMceTableSize; - HestMceTablePtr->GlobCapInitDataLSD = WheaInitDataPtr->GlobCapInitDataLSD; - HestMceTablePtr->GlobCapInitDataMSD = WheaInitDataPtr->GlobCapInitDataMSD; - HestMceTablePtr->GlobCtrlInitDataLSD = WheaInitDataPtr->GlobCtrlInitDataLSD; - HestMceTablePtr->GlobCtrlInitDataMSD = WheaInitDataPtr->GlobCtrlInitDataMSD; - HestMceTablePtr->NumHWBanks = WheaInitDataPtr->HestBankNum; - - HestBankPtr = (AMD_HEST_BANK *) (HestMceTablePtr + 1); - CreateHestBank (HestBankPtr, WheaInitDataPtr->HestBankNum, WheaInitDataPtr); - - // step 4: fill in Hest CMC table - HestCmcTablePtr->NumHWBanks = WheaInitDataPtr->HestBankNum; - HestCmcTablePtr->TblLength = HestCmcTableSize; - - HestBankPtr = (AMD_HEST_BANK *) (HestCmcTablePtr + 1); - CreateHestBank (HestBankPtr, WheaInitDataPtr->HestBankNum, WheaInitDataPtr); - - // step 5: fill in the incoming structure - *WheaMcePtr = HestMceTablePtr; - *WheaCmcPtr = HestCmcTablePtr; - - return (AGESA_SUCCESS); -} - -/*--------------------------------------------------------------------------------------- - * L O C A L F U N C T I O N S - *--------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------*/ -/** - * - * It will create Bank structure for Hest table - * - * @param[in] HestBankPtr Pointer to the Hest Back structure - * @param[in] BankNum The number of Bank - * @param[in] WheaInitDataPtr Pointer to the AMD_WHEA_INIT_DATA structure - * - */ -VOID -STATIC -CreateHestBank ( - IN AMD_HEST_BANK *HestBankPtr, - IN UINT8 BankNum, - IN AMD_WHEA_INIT_DATA *WheaInitDataPtr - ) -{ - UINT8 BankIndex; - for (BankIndex = 0; BankIndex < BankNum; BankIndex++) { - HestBankPtr->BankNum = BankIndex; - HestBankPtr->ClrStatusOnInit = WheaInitDataPtr->ClrStatusOnInit; - HestBankPtr->StatusDataFormat = WheaInitDataPtr->StatusDataFormat; - HestBankPtr->ConfWriteEn = WheaInitDataPtr->ConfWriteEn; - HestBankPtr->CtrlRegMSRAddr = WheaInitDataPtr->HestBankInitData[BankIndex].CtrlRegMSRAddr; - HestBankPtr->CtrlInitDataLSD = WheaInitDataPtr->HestBankInitData[BankIndex].CtrlInitDataLSD; - HestBankPtr->CtrlInitDataMSD = WheaInitDataPtr->HestBankInitData[BankIndex].CtrlInitDataMSD; - HestBankPtr->StatRegMSRAddr = WheaInitDataPtr->HestBankInitData[BankIndex].StatRegMSRAddr; - HestBankPtr->AddrRegMSRAddr = WheaInitDataPtr->HestBankInitData[BankIndex].AddrRegMSRAddr; - HestBankPtr->MiscRegMSRAddr = WheaInitDataPtr->HestBankInitData[BankIndex].MiscRegMSRAddr; - HestBankPtr++; - } -} - diff --git a/src/vendorcode/amd/agesa/f12/Proc/CPU/Makefile.inc b/src/vendorcode/amd/agesa/f12/Proc/CPU/Makefile.inc deleted file mode 100644 index 6e270a2fb7..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/CPU/Makefile.inc +++ /dev/null @@ -1,19 +0,0 @@ -libagesa-y += S3.c -libagesa-y += Table.c -libagesa-y += cahalt.c -libagesa-y += cpuApicUtilities.c -libagesa-y += cpuBist.c -libagesa-y += cpuBrandId.c -libagesa-y += cpuEarlyInit.c -libagesa-y += cpuEventLog.c -libagesa-y += cpuFamilyTranslation.c -libagesa-y += cpuGeneralServices.c -libagesa-y += cpuInitEarlyTable.c -libagesa-y += cpuLateInit.c -libagesa-y += cpuMicrocodePatch.c -libagesa-y += cpuPostInit.c -libagesa-y += cpuPowerMgmt.c -libagesa-y += cpuPowerMgmtMultiSocket.c -libagesa-y += cpuPowerMgmtSingleSocket.c -libagesa-y += cpuWarmReset.c -libagesa-y += heapManager.c diff --git a/src/vendorcode/amd/agesa/f12/Proc/CPU/S3.c b/src/vendorcode/amd/agesa/f12/Proc/CPU/S3.c deleted file mode 100644 index 0897123aa2..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/CPU/S3.c +++ /dev/null @@ -1,1233 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * ACPI S3 Support routines - * - * Contains routines needed for supporting resume from the ACPI S3 sleep state. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: Interface - * @e \$Revision: 49927 $ @e \$Date: 2011-03-31 01:27:42 +0800 (Thu, 31 Mar 2011) $ - * - */ -/***************************************************************************** - * - * Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - ****************************************************************************** - */ - - -/*---------------------------------------------------------------------------------------- - * M O D U L E S U S E D - *---------------------------------------------------------------------------------------- - */ -#include "AGESA.h" -#include "amdlib.h" -#include "Ids.h" -#include "mm.h" -#include "mn.h" -#include "S3.h" -#include "mfs3.h" -#include "GeneralServices.h" -#include "cpuRegisters.h" -#include "cpuServices.h" -#include "Filecode.h" -CODE_GROUP (G1_PEICC) -RDATA_GROUP (G1_PEICC) - -#define FILECODE PROC_CPU_S3_FILECODE -/*---------------------------------------------------------------------------------------- - * D E F I N I T I O N S A N D M A C R O S - *---------------------------------------------------------------------------------------- - */ - - -/*---------------------------------------------------------------------------------------- - * T Y P E D E F S A N D S T R U C T U R E S - *---------------------------------------------------------------------------------------- - */ - - -/*---------------------------------------------------------------------------------------- - * P R O T O T Y P E S O F L O C A L F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ -VOID -SaveDeviceContext ( - IN DEVICE_BLOCK_HEADER *DeviceList, - IN CALL_POINTS CallPoint, - OUT UINT32 *ActualBufferSize, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -VOID -SavePciDevice ( - IN AMD_CONFIG_PARAMS *StdHeader, - IN PCI_DEVICE_DESCRIPTOR *Device, - IN CALL_POINTS CallPoint, - IN OUT VOID **OrMask - ); - -VOID -SaveConditionalPciDevice ( - IN AMD_CONFIG_PARAMS *StdHeader, - IN CONDITIONAL_PCI_DEVICE_DESCRIPTOR *Device, - IN CALL_POINTS CallPoint, - IN OUT VOID **OrMask - ); - -VOID -SaveMsrDevice ( - IN AMD_CONFIG_PARAMS *StdHeader, - IN MSR_DEVICE_DESCRIPTOR *Device, - IN CALL_POINTS CallPoint, - IN OUT UINT64 **OrMask - ); - -VOID -SaveConditionalMsrDevice ( - IN AMD_CONFIG_PARAMS *StdHeader, - IN CONDITIONAL_MSR_DEVICE_DESCRIPTOR *Device, - IN CALL_POINTS CallPoint, - IN OUT UINT64 **OrMask - ); - -VOID -RestorePciDevice ( - IN AMD_CONFIG_PARAMS *StdHeader, - IN PCI_DEVICE_DESCRIPTOR *Device, - IN CALL_POINTS CallPoint, - IN OUT VOID **OrMask - ); - -VOID -RestoreConditionalPciDevice ( - IN AMD_CONFIG_PARAMS *StdHeader, - IN CONDITIONAL_PCI_DEVICE_DESCRIPTOR *Device, - IN CALL_POINTS CallPoint, - IN OUT VOID **OrMask - ); - -VOID -RestoreMsrDevice ( - IN AMD_CONFIG_PARAMS *StdHeader, - IN MSR_DEVICE_DESCRIPTOR *Device, - IN CALL_POINTS CallPoint, - IN OUT UINT64 **OrMask - ); - -VOID -RestoreConditionalMsrDevice ( - IN AMD_CONFIG_PARAMS *StdHeader, - IN CONDITIONAL_MSR_DEVICE_DESCRIPTOR *Device, - IN CALL_POINTS CallPoint, - IN OUT UINT64 **OrMask - ); - -/*---------------------------------------------------------------------------------------- - * E X P O R T E D F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------*/ -/** - * Saves all devices in the given device list. - * - * This traverses the entire device list twice. In the first pass, we save - * all devices identified as Pre ESR. In the second pass, we save devices - * marked as post ESR. - * - * @param[in] DeviceList Beginning of the device list to save. - * @param[in] Storage Beginning of the context buffer. - * @param[in] CallPoint Indicates whether this is AMD_INIT_RESUME or - * AMD_S3LATE_RESTORE. - * @param[out] ActualBufferSize Actual size used in saving the device list. - * @param[in] StdHeader AMD standard header config param. - * - */ -VOID -SaveDeviceListContext ( - IN DEVICE_BLOCK_HEADER *DeviceList, - IN VOID *Storage, - IN CALL_POINTS CallPoint, - OUT UINT32 *ActualBufferSize, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - // Copy device list over - LibAmdMemCopy (Storage, - DeviceList, - (UINTN) DeviceList->RelativeOrMaskOffset, - StdHeader); - SaveDeviceContext (Storage, CallPoint, ActualBufferSize, StdHeader); -} - -/*---------------------------------------------------------------------------------------*/ -/** - * Saves all devices in the given device list. - * - * This traverses the entire device list twice. In the first pass, we save - * all devices identified as Pre ESR. In the second pass, we save devices - * marked as post ESR. - * - * @param[in,out] DeviceList Beginning of the device list to save. - * @param[in] CallPoint Indicates whether this is AMD_INIT_RESUME or - * AMD_S3LATE_RESTORE. - * @param[out] ActualBufferSize Actual size used in saving the device list. - * @param[in] StdHeader AMD standard header config param. - * - */ -VOID -SaveDeviceContext ( - IN DEVICE_BLOCK_HEADER *DeviceList, - IN CALL_POINTS CallPoint, - OUT UINT32 *ActualBufferSize, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - DEVICE_DESCRIPTORS Device; - UINT16 i; - UINT64 StartAddress; - UINT64 EndAddress; - VOID *OrMask; - - StartAddress = (UINT64) (intptr_t) DeviceList; - Device.CommonDeviceHeader = (DEVICE_DESCRIPTOR *) &DeviceList[1]; - OrMask = (UINT8 *) DeviceList + DeviceList->RelativeOrMaskOffset; - - // Process Pre ESR List - for (i = 0; i < DeviceList->NumDevices; i++) { - switch (Device.CommonDeviceHeader->Type) { - case DEV_TYPE_PCI_PRE_ESR: - SavePciDevice (StdHeader, Device.PciDevice, CallPoint, &OrMask); - // fall through - advance the pointer after saving context - case DEV_TYPE_PCI: - Device.PciDevice++; - break; - case DEV_TYPE_CPCI_PRE_ESR: - SaveConditionalPciDevice (StdHeader, Device.CPciDevice, CallPoint, &OrMask); - // fall through - advance the pointer after saving context - case DEV_TYPE_CPCI: - Device.CPciDevice++; - break; - case DEV_TYPE_MSR_PRE_ESR: - SaveMsrDevice (StdHeader, Device.MsrDevice, CallPoint, (UINT64 **) &OrMask); - // fall through - advance the pointer after saving context - case DEV_TYPE_MSR: - Device.MsrDevice++; - break; - case DEV_TYPE_CMSR_PRE_ESR: - SaveConditionalMsrDevice (StdHeader, Device.CMsrDevice, CallPoint, (UINT64 **) &OrMask); - // fall through - advance the pointer after saving context - case DEV_TYPE_CMSR: - Device.CMsrDevice++; - break; - } - } - - Device.CommonDeviceHeader = (DEVICE_DESCRIPTOR *) &DeviceList[1]; - // Process Post ESR List - for (i = 0; i < DeviceList->NumDevices; i++) { - switch (Device.CommonDeviceHeader->Type) { - case DEV_TYPE_PCI: - SavePciDevice (StdHeader, Device.PciDevice, CallPoint, &OrMask); - // fall through - advance the pointer after saving context - case DEV_TYPE_PCI_PRE_ESR: - Device.PciDevice++; - break; - case DEV_TYPE_CPCI: - SaveConditionalPciDevice (StdHeader, Device.CPciDevice, CallPoint, &OrMask); - // fall through - advance the pointer after saving context - case DEV_TYPE_CPCI_PRE_ESR: - Device.CPciDevice++; - break; - case DEV_TYPE_MSR: - SaveMsrDevice (StdHeader, Device.MsrDevice, CallPoint, (UINT64 **) &OrMask); - // fall through - advance the pointer after saving context - case DEV_TYPE_MSR_PRE_ESR: - Device.MsrDevice++; - break; - case DEV_TYPE_CMSR: - SaveConditionalMsrDevice (StdHeader, Device.CMsrDevice, CallPoint, (UINT64 **) &OrMask); - // fall through - advance the pointer after saving context - case DEV_TYPE_CMSR_PRE_ESR: - Device.CMsrDevice++; - break; - } - } - EndAddress = (UINT64) (intptr_t) OrMask; - *ActualBufferSize = (UINT32) (EndAddress - StartAddress); -} - -/*---------------------------------------------------------------------------------------*/ -/** - * Saves the context of a PCI device. - * - * This traverses the provided register list saving PCI registers. - * - * @param[in] StdHeader AMD standard header config param. - * @param[in] Device PCI device to restore. - * @param[in] CallPoint Indicates whether this is AMD_INIT_RESUME or - * AMD_S3LATE_RESTORE. - * @param[in,out] OrMask Current buffer pointer of raw register values. - * - */ -VOID -SavePciDevice ( - IN AMD_CONFIG_PARAMS *StdHeader, - IN PCI_DEVICE_DESCRIPTOR *Device, - IN CALL_POINTS CallPoint, - IN OUT VOID **OrMask - ) -{ - UINT8 RegSizeInBytes; - UINT8 SpecialCaseIndex; - UINT8 *IntermediatePtr; - UINT16 i; - UINT32 Socket; - UINT32 Module; - UINT32 AndMask; - ACCESS_WIDTH AccessWidth; - AGESA_STATUS IgnoredSts; - PCI_ADDR PciAddress; - PCI_REGISTER_BLOCK_HEADER *RegisterHdr; - - GetSocketModuleOfNode ((UINT32) Device->Node, - &Socket, - &Module, - StdHeader); - GetPciAddress (StdHeader, Socket, Module, &PciAddress, &IgnoredSts); - - if (CallPoint == INIT_RESUME) { - MemFS3GetPciDeviceRegisterList (Device, &RegisterHdr, StdHeader); - } else { - S3GetPciDeviceRegisterList (Device, &RegisterHdr, StdHeader); - } - - for (i = 0; i < RegisterHdr->NumRegisters; i++) { - PciAddress.Address.Function = RegisterHdr->RegisterList[i].Function; - PciAddress.Address.Register = RegisterHdr->RegisterList[i].Offset; - RegSizeInBytes = RegisterHdr->RegisterList[i].Type.RegisterSize; - switch (RegSizeInBytes) { - case 1: - AndMask = 0xFFFFFFFF & ((UINT8) RegisterHdr->RegisterList[i].AndMask); - AccessWidth = AccessS3SaveWidth8; - break; - case 2: - AndMask = 0xFFFFFFFF & ((UINT16) RegisterHdr->RegisterList[i].AndMask); - AccessWidth = AccessS3SaveWidth16; - break; - case 3: - // In this case, we don't need to save a register. We just need to call a special - // function to do certain things in the save and resume sequence. - // This should not be used in a non-special case. - AndMask = 0; - RegSizeInBytes = 0; - AccessWidth = 0; - break; - default: - AndMask = RegisterHdr->RegisterList[i].AndMask; - RegSizeInBytes = 4; - AccessWidth = AccessS3SaveWidth32; - break; - } - if (RegisterHdr->RegisterList[i].Type.SpecialCaseFlag == 0) { - ASSERT ((AndMask != 0) && (RegSizeInBytes != 0) && (AccessWidth != 0)); - LibAmdPciRead (AccessWidth, PciAddress, *OrMask, StdHeader); - } else { - SpecialCaseIndex = RegisterHdr->RegisterList[i].Type.SpecialCaseIndex; - RegisterHdr->SpecialCases[SpecialCaseIndex].Save (AccessWidth, PciAddress, *OrMask, StdHeader); - } - if (AndMask != 0) { - // If AndMask is 0, then it is a not-care. Don't need to apply it to the OrMask - **((UINT32 **) OrMask) &= AndMask; - } - if ((RegSizeInBytes == 0) && (**((UINT32 **) OrMask) == RESTART_FROM_BEGINNING_LIST)) { - // Restart from the beginning of the register list - i = 0xFFFF; - } - IntermediatePtr = (UINT8 *) *OrMask; - *OrMask = &IntermediatePtr[RegSizeInBytes]; // += RegSizeInBytes; - } -} - -/*---------------------------------------------------------------------------------------*/ -/** - * Saves the context of a 'conditional' PCI device. - * - * This traverses the provided register list saving PCI registers when appropriate. - * - * @param[in] StdHeader AMD standard header config param. - * @param[in] Device 'conditional' PCI device to restore. - * @param[in] CallPoint Indicates whether this is AMD_INIT_RESUME or - * AMD_S3LATE_RESTORE. - * @param[in,out] OrMask Current buffer pointer of raw register values. - * - */ -VOID -SaveConditionalPciDevice ( - IN AMD_CONFIG_PARAMS *StdHeader, - IN CONDITIONAL_PCI_DEVICE_DESCRIPTOR *Device, - IN CALL_POINTS CallPoint, - IN OUT VOID **OrMask - ) -{ - UINT8 RegSizeInBytes; - UINT8 SpecialCaseIndex; - UINT8 *IntermediatePtr; - UINT16 i; - UINT32 Socket; - UINT32 Module; - UINT32 AndMask; - ACCESS_WIDTH AccessWidth; - AGESA_STATUS IgnoredSts; - PCI_ADDR PciAddress; - CPCI_REGISTER_BLOCK_HEADER *RegisterHdr; - - GetSocketModuleOfNode ((UINT32) Device->Node, - &Socket, - &Module, - StdHeader); - GetPciAddress (StdHeader, Socket, Module, &PciAddress, &IgnoredSts); - - if (CallPoint == INIT_RESUME) { - MemFS3GetCPciDeviceRegisterList (Device, &RegisterHdr, StdHeader); - } else { - S3GetCPciDeviceRegisterList (Device, &RegisterHdr, StdHeader); - } - - for (i = 0; i < RegisterHdr->NumRegisters; i++) { - if (((Device->Mask1 & RegisterHdr->RegisterList[i].Mask1) != 0) && - ((Device->Mask2 & RegisterHdr->RegisterList[i].Mask2) != 0)) { - PciAddress.Address.Function = RegisterHdr->RegisterList[i].Function; - PciAddress.Address.Register = RegisterHdr->RegisterList[i].Offset; - RegSizeInBytes = RegisterHdr->RegisterList[i].Type.RegisterSize; - switch (RegSizeInBytes) { - case 1: - AndMask = 0xFFFFFFFF & ((UINT8) RegisterHdr->RegisterList[i].AndMask); - AccessWidth = AccessS3SaveWidth8; - break; - case 2: - AndMask = 0xFFFFFFFF & ((UINT16) RegisterHdr->RegisterList[i].AndMask); - AccessWidth = AccessS3SaveWidth16; - break; - case 3: - // In this case, we don't need to save a register. We just need to call a special - // function to do certain things in the save and resume sequence. - // This should not be used in a non-special case. - AndMask = 0; - RegSizeInBytes = 0; - AccessWidth = 0; - break; - default: - AndMask = RegisterHdr->RegisterList[i].AndMask; - RegSizeInBytes = 4; - AccessWidth = AccessS3SaveWidth32; - break; - } - if (RegisterHdr->RegisterList[i].Type.SpecialCaseFlag == 0) { - ASSERT ((AndMask != 0) && (RegSizeInBytes != 0) && (AccessWidth != 0)); - LibAmdPciRead (AccessWidth, PciAddress, *OrMask, StdHeader); - } else { - SpecialCaseIndex = RegisterHdr->RegisterList[i].Type.SpecialCaseIndex; - RegisterHdr->SpecialCases[SpecialCaseIndex].Save (AccessWidth, PciAddress, *OrMask, StdHeader); - } - if (AndMask != 0) { - // If AndMask is 0, then it is a not-care. Don't need to apply it to the OrMask - **((UINT32 **) OrMask) &= AndMask; - } - if ((RegSizeInBytes == 0) && (**((UINT32 **) OrMask) == RESTART_FROM_BEGINNING_LIST)) { - // Restart from the beginning of the register list - i = 0xFFFF; - } - IntermediatePtr = (UINT8 *) *OrMask; - *OrMask = &IntermediatePtr[RegSizeInBytes]; // += RegSizeInBytes; - } - } -} - -/*---------------------------------------------------------------------------------------*/ -/** - * Saves the context of an MSR device. - * - * This traverses the provided register list saving MSRs. - * - * @param[in] StdHeader AMD standard header config param. - * @param[in] Device MSR device to restore. - * @param[in] CallPoint Indicates whether this is AMD_INIT_RESUME or - * AMD_S3LATE_RESTORE. - * @param[in,out] OrMask Current buffer pointer of raw register values. - * - */ -VOID -SaveMsrDevice ( - IN AMD_CONFIG_PARAMS *StdHeader, - IN MSR_DEVICE_DESCRIPTOR *Device, - IN CALL_POINTS CallPoint, - IN OUT UINT64 **OrMask - ) -{ - UINT8 SpecialCaseIndex; - UINT16 i; - MSR_REGISTER_BLOCK_HEADER *RegisterHdr; - - if (CallPoint == INIT_RESUME) { - MemFS3GetMsrDeviceRegisterList (Device, &RegisterHdr, StdHeader); - } else { - S3GetMsrDeviceRegisterList (Device, &RegisterHdr, StdHeader); - } - - for (i = 0; i < RegisterHdr->NumRegisters; i++) { - if (RegisterHdr->RegisterList[i].Type.SpecialCaseFlag == 0) { - LibAmdMsrRead (RegisterHdr->RegisterList[i].Address, *OrMask, StdHeader); - } else { - SpecialCaseIndex = RegisterHdr->RegisterList[i].Type.SpecialCaseIndex; - RegisterHdr->SpecialCases[SpecialCaseIndex].Save (RegisterHdr->RegisterList[i].Address, *OrMask, StdHeader); - } - **OrMask &= RegisterHdr->RegisterList[i].AndMask; - (*OrMask)++; - } -} - -/*---------------------------------------------------------------------------------------*/ -/** - * Saves the context of a 'conditional' MSR device. - * - * This traverses the provided register list saving MSRs when appropriate. - * - * @param[in] StdHeader AMD standard header config param. - * @param[in] Device 'conditional' MSR device to restore. - * @param[in] CallPoint Indicates whether this is AMD_INIT_RESUME or - * AMD_S3LATE_RESTORE. - * @param[in,out] OrMask Current buffer pointer of raw register values. - * - */ -VOID -SaveConditionalMsrDevice ( - IN AMD_CONFIG_PARAMS *StdHeader, - IN CONDITIONAL_MSR_DEVICE_DESCRIPTOR *Device, - IN CALL_POINTS CallPoint, - IN OUT UINT64 **OrMask - ) -{ - UINT8 SpecialCaseIndex; - UINT16 i; - CMSR_REGISTER_BLOCK_HEADER *RegisterHdr; - - if (CallPoint == INIT_RESUME) { - MemFS3GetCMsrDeviceRegisterList (Device, &RegisterHdr, StdHeader); - } else { - S3GetCMsrDeviceRegisterList (Device, &RegisterHdr, StdHeader); - } - - for (i = 0; i < RegisterHdr->NumRegisters; i++) { - if (((Device->Mask1 & RegisterHdr->RegisterList[i].Mask1) != 0) && - ((Device->Mask2 & RegisterHdr->RegisterList[i].Mask2) != 0)) { - if (RegisterHdr->RegisterList[i].Type.SpecialCaseFlag == 0) { - LibAmdMsrRead (RegisterHdr->RegisterList[i].Address, (UINT64 *) *OrMask, StdHeader); - } else { - SpecialCaseIndex = RegisterHdr->RegisterList[i].Type.SpecialCaseIndex; - RegisterHdr->SpecialCases[SpecialCaseIndex].Save (RegisterHdr->RegisterList[i].Address, (UINT64 *) *OrMask, StdHeader); - } - **OrMask &= RegisterHdr->RegisterList[i].AndMask; - (*OrMask)++; - } - } -} - -/*---------------------------------------------------------------------------------------*/ -/** - * Determines the maximum amount of space required to store all raw register - * values for the given device list. - * - * This traverses the entire device list, and calculates the worst case size - * of each device in the device list. - * - * @param[in] DeviceList Beginning of the device list. - * @param[in] CallPoint Indicates whether this is AMD_INIT_RESUME or - * AMD_S3LATE_RESTORE. - * @param[in] StdHeader AMD standard header config param. - * - * @retval Size in bytes required for storing all registers. - */ -UINT32 -GetWorstCaseContextSize ( - IN DEVICE_BLOCK_HEADER *DeviceList, - IN CALL_POINTS CallPoint, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - UINT32 WorstCaseSize; - DEVICE_DESCRIPTORS Device; - UINT16 i; - REGISTER_BLOCK_HEADERS RegisterHdr; - - WorstCaseSize = DeviceList->RelativeOrMaskOffset; - Device.CommonDeviceHeader = (DEVICE_DESCRIPTOR *) &DeviceList[1]; - - // Process Device List - for (i = 0; i < DeviceList->NumDevices; i++) { - switch (Device.CommonDeviceHeader->Type) { - case DEV_TYPE_PCI_PRE_ESR: - // PRE_ESR and post ESR take the same amount of space - case DEV_TYPE_PCI: - if (CallPoint == INIT_RESUME) { - MemFS3GetPciDeviceRegisterList (Device.PciDevice, &RegisterHdr.PciRegisters, StdHeader); - } else { - S3GetPciDeviceRegisterList (Device.PciDevice, &RegisterHdr.PciRegisters, StdHeader); - } - WorstCaseSize += (RegisterHdr.PciRegisters->NumRegisters * 4); - Device.PciDevice++; - break; - case DEV_TYPE_CPCI_PRE_ESR: - // PRE_ESR and post ESR take the same amount of space - case DEV_TYPE_CPCI: - if (CallPoint == INIT_RESUME) { - MemFS3GetCPciDeviceRegisterList (Device.CPciDevice, &RegisterHdr.CPciRegisters, StdHeader); - } else { - S3GetCPciDeviceRegisterList (Device.CPciDevice, &RegisterHdr.CPciRegisters, StdHeader); - } - WorstCaseSize += (RegisterHdr.CPciRegisters->NumRegisters * 4); - Device.CPciDevice++; - break; - case DEV_TYPE_MSR_PRE_ESR: - // PRE_ESR and post ESR take the same amount of space - case DEV_TYPE_MSR: - if (CallPoint == INIT_RESUME) { - MemFS3GetMsrDeviceRegisterList (Device.MsrDevice, &RegisterHdr.MsrRegisters, StdHeader); - } else { - S3GetMsrDeviceRegisterList (Device.MsrDevice, &RegisterHdr.MsrRegisters, StdHeader); - } - WorstCaseSize += (RegisterHdr.MsrRegisters->NumRegisters * 8); - Device.MsrDevice++; - break; - case DEV_TYPE_CMSR_PRE_ESR: - // PRE_ESR and post ESR take the same amount of space - case DEV_TYPE_CMSR: - if (CallPoint == INIT_RESUME) { - MemFS3GetCMsrDeviceRegisterList (Device.CMsrDevice, &RegisterHdr.CMsrRegisters, StdHeader); - } else { - S3GetCMsrDeviceRegisterList (Device.CMsrDevice, &RegisterHdr.CMsrRegisters, StdHeader); - } - WorstCaseSize += (RegisterHdr.CMsrRegisters->NumRegisters * 8); - Device.CMsrDevice++; - break; - default: - ASSERT (FALSE); - } - } - return (WorstCaseSize); -} - -/*---------------------------------------------------------------------------------------*/ -/** - * Restores all devices marked as 'before exiting self-refresh.' - * - * This traverses the entire device list, restoring all devices identified - * as Pre ESR. - * - * @param[in,out] OrMaskPtr Current buffer pointer of raw register values. - * @param[in] Storage Beginning of the device list. - * @param[in] CallPoint Indicates whether this is AMD_INIT_RESUME or - * AMD_S3LATE_RESTORE. - * @param[in] StdHeader AMD standard header config param. - * - */ -VOID -RestorePreESRContext ( - OUT VOID **OrMaskPtr, - IN VOID *Storage, - IN CALL_POINTS CallPoint, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - DEVICE_DESCRIPTORS Device; - UINT16 i; - DEVICE_BLOCK_HEADER *DeviceList; - - DeviceList = (DEVICE_BLOCK_HEADER *) Storage; - Device.CommonDeviceHeader = (DEVICE_DESCRIPTOR *) &DeviceList[1]; - *OrMaskPtr = (UINT8 *) DeviceList + DeviceList->RelativeOrMaskOffset; - - // Process Pre ESR List - for (i = 0; i < DeviceList->NumDevices; i++) { - switch (Device.CommonDeviceHeader->Type) { - case DEV_TYPE_PCI_PRE_ESR: - RestorePciDevice (StdHeader, Device.PciDevice, CallPoint, OrMaskPtr); - // fall through - advance the pointer after restoring context - case DEV_TYPE_PCI: - Device.PciDevice++; - break; - case DEV_TYPE_CPCI_PRE_ESR: - RestoreConditionalPciDevice (StdHeader, Device.CPciDevice, CallPoint, OrMaskPtr); - // fall through - advance the pointer after restoring context - case DEV_TYPE_CPCI: - Device.CPciDevice++; - break; - case DEV_TYPE_MSR_PRE_ESR: - RestoreMsrDevice (StdHeader, Device.MsrDevice, CallPoint, (UINT64 **) OrMaskPtr); - // fall through - advance the pointer after restoring context - case DEV_TYPE_MSR: - Device.MsrDevice++; - break; - case DEV_TYPE_CMSR_PRE_ESR: - RestoreConditionalMsrDevice (StdHeader, Device.CMsrDevice, CallPoint, (UINT64 **) OrMaskPtr); - // fall through - advance the pointer after restoring context - case DEV_TYPE_CMSR: - Device.CMsrDevice++; - break; - } - } -} - -/*---------------------------------------------------------------------------------------*/ -/** - * Restores all devices marked as 'after exiting self-refresh.' - * - * This traverses the entire device list, restoring all devices identified - * as Post ESR. - * - * @param[in] OrMaskPtr Current buffer pointer of raw register values. - * @param[in] Storage Beginning of the device list. - * @param[in] CallPoint Indicates whether this is AMD_INIT_RESUME or - * AMD_S3LATE_RESTORE. - * @param[in] StdHeader AMD standard header config param. - * - */ -VOID -RestorePostESRContext ( - IN VOID *OrMaskPtr, - IN VOID *Storage, - IN CALL_POINTS CallPoint, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - DEVICE_DESCRIPTORS Device; - UINT16 i; - DEVICE_BLOCK_HEADER *DeviceList; - - DeviceList = (DEVICE_BLOCK_HEADER *) Storage; - Device.CommonDeviceHeader = (DEVICE_DESCRIPTOR *) &DeviceList[1]; - - // Process Pre ESR List - for (i = 0; i < DeviceList->NumDevices; i++) { - switch (Device.CommonDeviceHeader->Type) { - case DEV_TYPE_PCI: - RestorePciDevice (StdHeader, Device.PciDevice, CallPoint, &OrMaskPtr); - // fall through - advance the pointer after restoring context - case DEV_TYPE_PCI_PRE_ESR: - Device.PciDevice++; - break; - case DEV_TYPE_CPCI: - RestoreConditionalPciDevice (StdHeader, Device.CPciDevice, CallPoint, &OrMaskPtr); - // fall through - advance the pointer after restoring context - case DEV_TYPE_CPCI_PRE_ESR: - Device.CPciDevice++; - break; - case DEV_TYPE_MSR: - RestoreMsrDevice (StdHeader, Device.MsrDevice, CallPoint, (UINT64 **) &OrMaskPtr); - // fall through - advance the pointer after restoring context - case DEV_TYPE_MSR_PRE_ESR: - Device.MsrDevice++; - break; - case DEV_TYPE_CMSR: - RestoreConditionalMsrDevice (StdHeader, Device.CMsrDevice, CallPoint, (UINT64 **) &OrMaskPtr); - // fall through - advance the pointer after restoring context - case DEV_TYPE_CMSR_PRE_ESR: - Device.CMsrDevice++; - break; - } - } -} - -/*---------------------------------------------------------------------------------------*/ -/** - * Restores the context of a PCI device. - * - * This traverses the provided register list restoring PCI registers. - * - * @param[in] StdHeader AMD standard header config param. - * @param[in] Device 'conditional' PCI device to restore. - * @param[in] CallPoint Indicates whether this is AMD_INIT_RESUME or - * AMD_S3LATE_RESTORE. - * @param[in,out] OrMask Current buffer pointer of raw register values. - * - */ -VOID -RestorePciDevice ( - IN AMD_CONFIG_PARAMS *StdHeader, - IN PCI_DEVICE_DESCRIPTOR *Device, - IN CALL_POINTS CallPoint, - IN OUT VOID **OrMask - ) -{ - UINT8 RegSizeInBytes; - UINT8 SpecialCaseIndex; - UINT8 *IntermediatePtr; - UINT16 i; - UINT32 Socket; - UINT32 Module; - UINT32 AndMask; - UINT32 RegValueRead; - UINT32 RegValueWrite; - ACCESS_WIDTH AccessWidth; - AGESA_STATUS IgnoredSts; - PCI_ADDR PciAddress; - PCI_REGISTER_BLOCK_HEADER *RegisterHdr; - - GetSocketModuleOfNode ((UINT32) Device->Node, - &Socket, - &Module, - StdHeader); - GetPciAddress (StdHeader, Socket, Module, &PciAddress, &IgnoredSts); - - if (CallPoint == INIT_RESUME) { - MemFS3GetPciDeviceRegisterList (Device, &RegisterHdr, StdHeader); - } else { - S3GetPciDeviceRegisterList (Device, &RegisterHdr, StdHeader); - } - - for (i = 0; i < RegisterHdr->NumRegisters; i++) { - PciAddress.Address.Function = RegisterHdr->RegisterList[i].Function; - PciAddress.Address.Register = RegisterHdr->RegisterList[i].Offset; - RegSizeInBytes = RegisterHdr->RegisterList[i].Type.RegisterSize; - switch (RegSizeInBytes) { - case 1: - AndMask = 0xFFFFFFFF & ((UINT8) RegisterHdr->RegisterList[i].AndMask); - RegValueWrite = **(UINT8 **)OrMask; - AccessWidth = AccessS3SaveWidth8; - break; - case 2: - AndMask = 0xFFFFFFFF & ((UINT16) RegisterHdr->RegisterList[i].AndMask); - RegValueWrite = **(UINT16 **)OrMask; - AccessWidth = AccessS3SaveWidth16; - break; - case 3: - // In this case, we don't need to restore a register. We just need to call a special - // function to do certain things in the save and resume sequence. - // This should not be used in a non-special case. - AndMask = 0; - RegValueWrite = 0; - RegSizeInBytes = 0; - AccessWidth = 0; - break; - default: - AndMask = RegisterHdr->RegisterList[i].AndMask; - RegSizeInBytes = 4; - RegValueWrite = **(UINT32 **)OrMask; - AccessWidth = AccessS3SaveWidth32; - break; - } - if (RegisterHdr->RegisterList[i].Type.SpecialCaseFlag == 0) { - ASSERT ((AndMask != 0) && (RegSizeInBytes != 0) && (AccessWidth != 0)); - LibAmdPciRead (AccessWidth, PciAddress, &RegValueRead, StdHeader); - RegValueWrite |= RegValueRead & (~AndMask); - LibAmdPciWrite (AccessWidth, PciAddress, &RegValueWrite, StdHeader); - } else { - SpecialCaseIndex = RegisterHdr->RegisterList[i].Type.SpecialCaseIndex; - if (AndMask != 0) { - RegisterHdr->SpecialCases[SpecialCaseIndex].Save (AccessWidth, - PciAddress, - &RegValueRead, - StdHeader); - RegValueWrite |= RegValueRead & (~AndMask); - } - RegisterHdr->SpecialCases[SpecialCaseIndex].Restore (AccessWidth, - PciAddress, - &RegValueWrite, - StdHeader); - } - IntermediatePtr = (UINT8 *) *OrMask; - *OrMask = &IntermediatePtr[RegSizeInBytes]; // += RegSizeInBytes; - if ((RegSizeInBytes == 0) && (RegValueWrite == RESTART_FROM_BEGINNING_LIST)) { - // Restart from the beginning of the register list - i = 0xFFFF; - } - } -} - -/*---------------------------------------------------------------------------------------*/ -/** - * Restores the context of a 'conditional' PCI device. - * - * This traverses the provided register list restoring PCI registers when appropriate. - * - * @param[in] StdHeader AMD standard header config param. - * @param[in] Device 'conditional' PCI device to restore. - * @param[in] CallPoint Indicates whether this is AMD_INIT_RESUME or - * AMD_S3LATE_RESTORE. - * @param[in,out] OrMask Current buffer pointer of raw register values. - * - */ -VOID -RestoreConditionalPciDevice ( - IN AMD_CONFIG_PARAMS *StdHeader, - IN CONDITIONAL_PCI_DEVICE_DESCRIPTOR *Device, - IN CALL_POINTS CallPoint, - IN OUT VOID **OrMask - ) -{ - UINT8 RegSizeInBytes; - UINT8 SpecialCaseIndex; - UINT8 *IntermediatePtr; - UINT16 i; - UINT32 Socket; - UINT32 Module; - UINT32 RegValueRead; - UINT32 RegValueWrite; - UINT32 AndMask; - ACCESS_WIDTH AccessWidth; - AGESA_STATUS IgnoredSts; - PCI_ADDR PciAddress; - CPCI_REGISTER_BLOCK_HEADER *RegisterHdr; - - GetSocketModuleOfNode ((UINT32) Device->Node, - &Socket, - &Module, - StdHeader); - GetPciAddress (StdHeader, Socket, Module, &PciAddress, &IgnoredSts); - - if (CallPoint == INIT_RESUME) { - MemFS3GetCPciDeviceRegisterList (Device, &RegisterHdr, StdHeader); - } else { - S3GetCPciDeviceRegisterList (Device, &RegisterHdr, StdHeader); - } - - for (i = 0; i < RegisterHdr->NumRegisters; i++) { - if (((Device->Mask1 & RegisterHdr->RegisterList[i].Mask1) != 0) && - ((Device->Mask2 & RegisterHdr->RegisterList[i].Mask2) != 0)) { - PciAddress.Address.Function = RegisterHdr->RegisterList[i].Function; - PciAddress.Address.Register = RegisterHdr->RegisterList[i].Offset; - RegSizeInBytes = RegisterHdr->RegisterList[i].Type.RegisterSize; - switch (RegSizeInBytes) { - case 1: - AndMask = 0xFFFFFFFF & ((UINT8) RegisterHdr->RegisterList[i].AndMask); - RegValueWrite = **(UINT8 **)OrMask; - AccessWidth = AccessS3SaveWidth8; - break; - case 2: - AndMask = 0xFFFFFFFF & ((UINT16) RegisterHdr->RegisterList[i].AndMask); - RegValueWrite = **(UINT16 **)OrMask; - AccessWidth = AccessS3SaveWidth16; - break; - case 3: - // In this case, we don't need to restore a register. We just need to call a special - // function to do certain things in the save and resume sequence. - // This should not be used in a non-special case. - AndMask = 0; - RegValueWrite = 0; - RegSizeInBytes = 0; - AccessWidth = 0; - break; - default: - AndMask = RegisterHdr->RegisterList[i].AndMask; - RegSizeInBytes = 4; - RegValueWrite = **(UINT32 **)OrMask; - AccessWidth = AccessS3SaveWidth32; - break; - } - if (RegisterHdr->RegisterList[i].Type.SpecialCaseFlag == 0) { - LibAmdPciRead (AccessWidth, PciAddress, &RegValueRead, StdHeader); - RegValueWrite |= RegValueRead & (~AndMask); - LibAmdPciWrite (AccessWidth, PciAddress, &RegValueWrite, StdHeader); - } else { - SpecialCaseIndex = RegisterHdr->RegisterList[i].Type.SpecialCaseIndex; - if (AndMask != 0) { - RegisterHdr->SpecialCases[SpecialCaseIndex].Save (AccessWidth, - PciAddress, - &RegValueRead, - StdHeader); - RegValueWrite |= RegValueRead & (~AndMask); - } - RegisterHdr->SpecialCases[SpecialCaseIndex].Restore (AccessWidth, - PciAddress, - &RegValueWrite, - StdHeader); - } - IntermediatePtr = (UINT8 *) *OrMask; - *OrMask = &IntermediatePtr[RegSizeInBytes]; - if ((RegSizeInBytes == 0) && (RegValueWrite == RESTART_FROM_BEGINNING_LIST)) { - // Restart from the beginning of the register list - i = 0xFFFF; - } - } - } -} - -/*---------------------------------------------------------------------------------------*/ -/** - * Restores the context of an MSR device. - * - * This traverses the provided register list restoring MSRs. - * - * @param[in] StdHeader AMD standard header config param. - * @param[in] Device MSR device to restore. - * @param[in] CallPoint Indicates whether this is AMD_INIT_RESUME or - * AMD_S3LATE_RESTORE. - * @param[in,out] OrMask Current buffer pointer of raw register values. - * - */ -VOID -RestoreMsrDevice ( - IN AMD_CONFIG_PARAMS *StdHeader, - IN MSR_DEVICE_DESCRIPTOR *Device, - IN CALL_POINTS CallPoint, - IN OUT UINT64 **OrMask - ) -{ - UINT8 SpecialCaseIndex; - UINT16 i; - UINT64 RegValueRead; - UINT64 RegValueWrite; - MSR_REGISTER_BLOCK_HEADER *RegisterHdr; - - if (CallPoint == INIT_RESUME) { - MemFS3GetMsrDeviceRegisterList (Device, &RegisterHdr, StdHeader); - } else { - S3GetMsrDeviceRegisterList (Device, &RegisterHdr, StdHeader); - } - - for (i = 0; i < RegisterHdr->NumRegisters; i++) { - RegValueWrite = **OrMask; - if (RegisterHdr->RegisterList[i].Type.SpecialCaseFlag == 0) { - LibAmdMsrRead (RegisterHdr->RegisterList[i].Address, &RegValueRead, StdHeader); - RegValueWrite |= RegValueRead & (~RegisterHdr->RegisterList[i].AndMask); - LibAmdMsrWrite (RegisterHdr->RegisterList[i].Address, &RegValueWrite, StdHeader); - } else { - SpecialCaseIndex = RegisterHdr->RegisterList[i].Type.SpecialCaseIndex; - RegisterHdr->SpecialCases[SpecialCaseIndex].Save (RegisterHdr->RegisterList[i].Address, - &RegValueRead, - StdHeader); - RegValueWrite |= RegValueRead & (~RegisterHdr->RegisterList[i].AndMask); - RegisterHdr->SpecialCases[SpecialCaseIndex].Restore (RegisterHdr->RegisterList[i].Address, - &RegValueWrite, - StdHeader); - } - (*OrMask)++; - } -} - -/*---------------------------------------------------------------------------------------*/ -/** - * Restores the context of a 'conditional' MSR device. - * - * This traverses the provided register list restoring MSRs when appropriate. - * - * @param[in] StdHeader AMD standard header config param. - * @param[in] Device 'conditional' MSR device to restore. - * @param[in] CallPoint Indicates whether this is AMD_INIT_RESUME or - * AMD_S3LATE_RESTORE. - * @param[in,out] OrMask Current buffer pointer of raw register values. - * - */ -VOID -RestoreConditionalMsrDevice ( - IN AMD_CONFIG_PARAMS *StdHeader, - IN CONDITIONAL_MSR_DEVICE_DESCRIPTOR *Device, - IN CALL_POINTS CallPoint, - IN OUT UINT64 **OrMask - ) -{ - UINT8 SpecialCaseIndex; - UINT16 i; - UINT64 RegValueRead; - UINT64 RegValueWrite; - CMSR_REGISTER_BLOCK_HEADER *RegisterHdr; - - if (CallPoint == INIT_RESUME) { - MemFS3GetCMsrDeviceRegisterList (Device, &RegisterHdr, StdHeader); - } else { - S3GetCMsrDeviceRegisterList (Device, &RegisterHdr, StdHeader); - } - - for (i = 0; i < RegisterHdr->NumRegisters; i++) { - if (((Device->Mask1 & RegisterHdr->RegisterList[i].Mask1) != 0) && - ((Device->Mask2 & RegisterHdr->RegisterList[i].Mask2) != 0)) { - RegValueWrite = **OrMask; - if (RegisterHdr->RegisterList[i].Type.SpecialCaseFlag == 0) { - LibAmdMsrRead (RegisterHdr->RegisterList[i].Address, &RegValueRead, StdHeader); - RegValueWrite |= RegValueRead & (~RegisterHdr->RegisterList[i].AndMask); - LibAmdMsrWrite (RegisterHdr->RegisterList[i].Address, &RegValueWrite, StdHeader); - } else { - SpecialCaseIndex = RegisterHdr->RegisterList[i].Type.SpecialCaseIndex; - RegisterHdr->SpecialCases[SpecialCaseIndex].Save (RegisterHdr->RegisterList[i].Address, - &RegValueRead, - StdHeader); - RegValueWrite |= RegValueRead & (~RegisterHdr->RegisterList[i].AndMask); - RegisterHdr->SpecialCases[SpecialCaseIndex].Restore (RegisterHdr->RegisterList[i].Address, - &RegValueWrite, - StdHeader); - } - (*OrMask)++; - } - } -} - -/*---------------------------------------------------------------------------------------*/ -/** - * Unique device ID to PCI register list translator. - * - * This translates the given device header in storage to the appropriate list - * of registers in the AGESA image. - * - * @param[out] NonMemoryRelatedDeviceList List of devices to save and restore - * during S3LateRestore. - * @param[in] StdHeader AMD standard header config param. - * - */ -VOID -GetNonMemoryRelatedDeviceList ( - OUT DEVICE_BLOCK_HEADER **NonMemoryRelatedDeviceList, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - *NonMemoryRelatedDeviceList = NULL; -} - -/*---------------------------------------------------------------------------------------*/ -/** - * Unique device ID to PCI register list translator. - * - * This translates the given device header in storage to the appropriate list - * of registers in the AGESA image. - * - * @param[in] Device Device header containing the unique ID. - * @param[out] RegisterHdr Output PCI register list pointer. - * @param[in] StdHeader AMD standard header config param. - * - * @retval AGESA_SUCCESS Always succeeds. - */ -AGESA_STATUS -S3GetPciDeviceRegisterList ( - IN PCI_DEVICE_DESCRIPTOR *Device, - OUT PCI_REGISTER_BLOCK_HEADER **RegisterHdr, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - *RegisterHdr = NULL; - return AGESA_SUCCESS; -} - -/*---------------------------------------------------------------------------------------*/ -/** - * Unique device ID to 'conditional' PCI register list translator. - * - * This translates the given device header in storage to the appropriate list - * of registers in the AGESA image. - * - * @param[in] Device Device header containing the unique ID. - * @param[out] RegisterHdr Output 'conditional' PCI register list pointer. - * @param[in] StdHeader AMD standard header config param. - * - * @retval AGESA_SUCCESS Always succeeds. - */ -AGESA_STATUS -S3GetCPciDeviceRegisterList ( - IN CONDITIONAL_PCI_DEVICE_DESCRIPTOR *Device, - OUT CPCI_REGISTER_BLOCK_HEADER **RegisterHdr, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - *RegisterHdr = NULL; - return AGESA_SUCCESS; -} - - -/*---------------------------------------------------------------------------------------*/ -/** - * Unique device ID to MSR register list translator. - * - * This translates the given device header in storage to the appropriate list - * of registers in the AGESA image. - * - * @param[in] Device Device header containing the unique ID. - * @param[out] RegisterHdr Output MSR register list pointer. - * @param[in] StdHeader AMD standard header config param. - * - * @retval AGESA_SUCCESS Always succeeds. - */ -AGESA_STATUS -S3GetMsrDeviceRegisterList ( - IN MSR_DEVICE_DESCRIPTOR *Device, - OUT MSR_REGISTER_BLOCK_HEADER **RegisterHdr, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - *RegisterHdr = NULL; - return AGESA_SUCCESS; -} - -/*---------------------------------------------------------------------------------------*/ -/** - * Unique device ID to 'conditional' MSR register list translator. - * - * This translates the given device header in storage to the appropriate list - * of registers in the AGESA image. - * - * @param[in] Device Device header containing the unique ID. - * @param[out] RegisterHdr Output 'conditional' MSR register list pointer. - * @param[in] StdHeader AMD standard header config param. - * - * @retval AGESA_SUCCESS Always succeeds. - */ -AGESA_STATUS -S3GetCMsrDeviceRegisterList ( - IN CONDITIONAL_MSR_DEVICE_DESCRIPTOR *Device, - OUT CMSR_REGISTER_BLOCK_HEADER **RegisterHdr, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - *RegisterHdr = NULL; - return AGESA_SUCCESS; -} - -/*---------------------------------------------------------------------------------------*/ -/** - * Constructor for the AMD_S3_PARAMS structure. - * - * This routine initializes failsafe values for the AMD_S3_PARAMS structure - * to be used by the AMD_INIT_RESUME, AMD_S3_SAVE, and AMD_S3LATE_RESTORE - * entry points. - * - * @param[in,out] S3Params Required input parameter for the AMD_S3_SAVE, - * AMD_INIT_RESUME, and AMD_S3_SAVE entry points. - * - */ -VOID -AmdS3ParamsInitializer ( - OUT AMD_S3_PARAMS *S3Params - ) -{ - S3Params->Signature = 0x52545341; - S3Params->Version = 0x0000; - S3Params->VolatileStorage = NULL; - S3Params->VolatileStorageSize = 0x00000000; - S3Params->Flags = 0x00000000; - S3Params->NvStorage = NULL; - S3Params->NvStorageSize = 0x00000000; -} diff --git a/src/vendorcode/amd/agesa/f12/Proc/CPU/S3.h b/src/vendorcode/amd/agesa/f12/Proc/CPU/S3.h deleted file mode 100644 index f3171aea14..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/CPU/S3.h +++ /dev/null @@ -1,394 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * ACPI S3 support definitions. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: CPU - * @e \$Revision: 49927 $ @e \$Date: 2011-03-31 01:27:42 +0800 (Thu, 31 Mar 2011) $ - * - */ -/* -***************************************************************************** -* -* Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* *************************************************************************** -* -*/ - -#ifndef _S3_H_ -#define _S3_H_ - - -/*--------------------------------------------------------------------------------------- - * M I X E D (Definitions And Macros / Typedefs, Structures, Enums) - *--------------------------------------------------------------------------------------- - */ - - -/*--------------------------------------------------------------------------------------- - * D E F I N I T I O N S A N D M A C R O S - *--------------------------------------------------------------------------------------- - */ -#define RESTART_FROM_BEGINNING_LIST 0xFFFFFFFF - -/*--------------------------------------------------------------------------------------- - * T Y P E D E F S, S T R U C T U R E S, E N U M S - *--------------------------------------------------------------------------------------- - */ - -/* Device related definitions */ - -/// Header at the beginning of a context save buffer. -typedef struct { - UINT16 Version; ///< Version of header - UINT16 NumDevices; ///< Number of devices in the list - UINT16 RelativeOrMaskOffset; ///< Size of device list + header -} DEVICE_BLOCK_HEADER; - -/// S3 device types -typedef enum { - DEV_TYPE_PCI_PRE_ESR, ///< PCI device before exiting self-refresh - DEV_TYPE_PCI, ///< PCI device after exiting self-refresh - DEV_TYPE_CPCI_PRE_ESR, ///< 'conditional' PCI device before exiting self-refresh - DEV_TYPE_CPCI, ///< 'conditional' PCI device after exiting self-refresh - DEV_TYPE_MSR_PRE_ESR, ///< MSR device before exiting self-refresh - DEV_TYPE_MSR, ///< MSR device after exiting self-refresh - DEV_TYPE_CMSR_PRE_ESR, ///< 'conditional' MSR device before exiting self-refresh - DEV_TYPE_CMSR ///< 'conditional' MSR device after exiting self-refresh -} S3_DEVICE_TYPES; - -/// S3 restoration call points -typedef enum { - INIT_RESUME, ///< AMD_INIT_RESUME - S3_LATE_RESTORE ///< AMD_S3LATE_RESTORE -} CALL_POINTS; - -/// S3 device common header -typedef struct { - UINT32 RegisterListID; ///< Unique ID of this device - UINT8 Type; ///< Appropriate S3_DEVICE_TYPES type -} DEVICE_DESCRIPTOR; - -/// S3 PCI device header -typedef struct { - UINT32 RegisterListID; ///< Unique ID of this device - UINT8 Type; ///< DEV_TYPE_PCI / DEV_TYPE_PCI_PRE_ESR - UINT8 Node; ///< Zero-based node number -} PCI_DEVICE_DESCRIPTOR; - -/// S3 'conditional' PCI device header -typedef struct { - UINT32 RegisterListID; ///< Unique ID of this device - UINT8 Type; ///< DEV_TYPE_CPCI / DEV_TYPE_CPCI_PRE_ESR - UINT8 Node; ///< Zero-based node number - UINT8 Mask1; ///< Conditional mask 1 - UINT8 Mask2; ///< Conditional mask 2 -} CONDITIONAL_PCI_DEVICE_DESCRIPTOR; - -/// S3 MSR device header -typedef struct { - UINT32 RegisterListID; ///< Unique ID of this device - UINT8 Type; ///< DEV_TYPE_MSR / DEV_TYPE_MSR_PRE_ESR -} MSR_DEVICE_DESCRIPTOR; - -/// S3 'conditional' MSR device header -typedef struct { - UINT32 RegisterListID; ///< Unique ID of this device - UINT8 Type; ///< DEV_TYPE_CMSR / DEV_TYPE_CMSR_PRE_ESR - UINT8 Mask1; ///< Conditional mask 1 - UINT8 Mask2; ///< Conditional mask 2 -} CONDITIONAL_MSR_DEVICE_DESCRIPTOR; - -/* Special case related definitions */ - -/** - * PCI special case save handler - * - * @param[in] AccessWidth 8, 16, or 32 bit wide access - * @param[in] Address full PCI address of the register to save - * @param[out] Value Value read from the register - * @param[in] ConfigPtr AMD standard header config parameter - * - */ -typedef VOID (*PF_S3_SPECIAL_PCI_SAVE) ( - IN ACCESS_WIDTH AccessWidth, - IN PCI_ADDR Address, - OUT VOID *Value, - IN VOID *ConfigPtr - ); - -/** - * PCI special case restore handler - * - * @param[in] AccessWidth 8, 16, or 32 bit wide access - * @param[in] Address full PCI address of the register to save - * @param[in] Value Value to write to the register - * @param[in] ConfigPtr AMD standard header config parameter - * - */ -typedef VOID (*PF_S3_SPECIAL_PCI_RESTORE) ( - IN ACCESS_WIDTH AccessWidth, - IN PCI_ADDR PciAddress, - IN VOID *Value, - IN VOID *StdHeader - ); - -/** - * MSR special case save handler - * - * @param[in] MsrAddress Address of model specific register to save - * @param[out] Value Value read from the register - * @param[in] ConfigPtr AMD standard header config parameter - * - */ -typedef VOID (*PF_S3_SPECIAL_MSR_SAVE) ( - IN UINT32 MsrAddress, - OUT UINT64 *Value, - IN VOID *StdHeader - ); - -/** - * MSR special case restore handler - * - * @param[in] MsrAddress Address of model specific register to restore - * @param[in] Value Value to write to the register - * @param[in] ConfigPtr AMD standard header config parameter - * - */ -typedef VOID (*PF_S3_SPECIAL_MSR_RESTORE) ( - IN UINT32 MsrAddress, - IN UINT64 *Value, - IN VOID *StdHeader - ); - -/// PCI special case save/restore structure. -typedef struct { - PF_S3_SPECIAL_PCI_SAVE Save; ///< Save routine - PF_S3_SPECIAL_PCI_RESTORE Restore; ///< Restore routine -} PCI_SPECIAL_CASE; - -/// MSR special case save/restore structure. -typedef struct { - PF_S3_SPECIAL_MSR_SAVE Save; ///< Save routine - PF_S3_SPECIAL_MSR_RESTORE Restore; ///< Restore routine -} MSR_SPECIAL_CASE; - -/* Register related definitions */ -/// S3 register type bit fields -typedef struct { - UINT8 SpecialCaseIndex:4; ///< Special Case array index - UINT8 RegisterSize:3; ///< For PCI, 1 = byte, 2 = word, else = dword. - ///< For MSR, don't care - UINT8 SpecialCaseFlag:1; ///< Indicates special case -} S3_REGISTER_TYPE; - -/// S3 PCI register descriptor. -typedef struct { - S3_REGISTER_TYPE Type; ///< Type[7] = special case flag, - ///< Type[6:3] = register size in bytes, - ///< Type[2:0] = special case index - UINT8 Function; ///< PCI function of the register - UINT16 Offset; ///< PCI offset of the register - UINT32 AndMask; ///< AND mask to be applied to the value before saving -} PCI_REG_DESCRIPTOR; - -/// S3 'conditional' PCI register descriptor. -typedef struct { - S3_REGISTER_TYPE Type; ///< Type[7] = special case flag, - ///< Type[6:3] = register size in bytes, - ///< Type[2:0] = special case index - UINT8 Function; ///< PCI function of the register - UINT16 Offset; ///< PCI offset of the register - UINT32 AndMask; ///< AND mask to be applied to the value before saving - UINT8 Mask1; ///< conditional mask 1 - UINT8 Mask2; ///< conditional mask 2 -} CONDITIONAL_PCI_REG_DESCRIPTOR; - -/// S3 MSR register descriptor. -typedef struct { - S3_REGISTER_TYPE Type; ///< Type[7] = special case flag, - ///< Type[6:3] = reserved, - ///< Type[2:0] = special case index - UINT32 Address; ///< MSR address - UINT64 AndMask; ///< AND mask to be applied to the value before saving -} MSR_REG_DESCRIPTOR; - -/// S3 'conditional' MSR register descriptor. -typedef struct { - S3_REGISTER_TYPE Type; ///< Type[7] = special case flag, - ///< Type[6:3] = reserved, - ///< Type[2:0] = special case index - UINT32 Address; ///< MSR address - UINT64 AndMask; ///< AND mask to be applied to the value before saving - UINT8 Mask1; ///< conditional mask 1 - UINT8 Mask2; ///< conditional mask 2 -} CONDITIONAL_MSR_REG_DESCRIPTOR; - -/// Common header at the beginning of an S3 register list. -typedef struct { - UINT16 Version; ///< Version of header - UINT16 NumRegisters; ///< Number of registers in the list -} REGISTER_BLOCK_HEADER; - -/// S3 PCI register list header. -typedef struct { - UINT16 Version; ///< Version of header - UINT16 NumRegisters; ///< Number of registers in the list - PCI_REG_DESCRIPTOR *RegisterList; ///< Pointer to the first register descriptor - PCI_SPECIAL_CASE *SpecialCases; ///< Pointer to array of special case handlers -} PCI_REGISTER_BLOCK_HEADER; - -/// S3 'conditional' PCI register list header. -typedef struct { - UINT16 Version; ///< Version of header - UINT16 NumRegisters; ///< Number of registers in the list - CONDITIONAL_PCI_REG_DESCRIPTOR *RegisterList; ///< Pointer to the first register descriptor - PCI_SPECIAL_CASE *SpecialCases; ///< Pointer to array of special case handlers -} CPCI_REGISTER_BLOCK_HEADER; - -/// S3 MSR register list header. -typedef struct { - UINT16 Version; ///< Version of header - UINT16 NumRegisters; ///< Number of registers in the list - MSR_REG_DESCRIPTOR *RegisterList; ///< Pointer to the first register descriptor - MSR_SPECIAL_CASE *SpecialCases; ///< Pointer to array of special case handlers -} MSR_REGISTER_BLOCK_HEADER; - -/// S3 'conditional' MSR register list header. -typedef struct { - UINT16 Version; ///< Version of header - UINT16 NumRegisters; ///< Number of registers in the list - CONDITIONAL_MSR_REG_DESCRIPTOR *RegisterList; ///< Pointer to the first register descriptor - MSR_SPECIAL_CASE *SpecialCases; ///< Pointer to array of special case handlers -} CMSR_REGISTER_BLOCK_HEADER; - -/// S3 device descriptor pointers for ease of proper pointer advancement. -typedef union { - DEVICE_DESCRIPTOR *CommonDeviceHeader; ///< Common header - PCI_DEVICE_DESCRIPTOR *PciDevice; ///< PCI header - CONDITIONAL_PCI_DEVICE_DESCRIPTOR *CPciDevice; ///< 'conditional' PCI header - MSR_DEVICE_DESCRIPTOR *MsrDevice; ///< MSR header - CONDITIONAL_MSR_DEVICE_DESCRIPTOR *CMsrDevice; ///< 'conditional' MSR header -} DEVICE_DESCRIPTORS; - -/// S3 register list header pointers for ease of proper pointer advancement. -typedef union { - DEVICE_DESCRIPTOR *CommonDeviceHeader; ///< Common header - PCI_REGISTER_BLOCK_HEADER *PciRegisters; ///< PCI header - CPCI_REGISTER_BLOCK_HEADER *CPciRegisters; ///< 'conditional' PCI header - MSR_REGISTER_BLOCK_HEADER *MsrRegisters; ///< MSR header - CMSR_REGISTER_BLOCK_HEADER *CMsrRegisters; ///< 'conditional' MSR header -} REGISTER_BLOCK_HEADERS; - -/// S3 Volatile Storage Header -typedef struct { - UINT32 HeapOffset; ///< Offset to beginning of heap data - UINT32 HeapSize; ///< Size of the heap data - UINT32 RegisterDataOffset; ///< Offset to beginning of raw save data - UINT32 RegisterDataSize; ///< Size of raw save data -} S3_VOLATILE_STORAGE_HEADER; - - -/*--------------------------------------------------------------------------------------- - * F U N C T I O N P R O T O T Y P E - *--------------------------------------------------------------------------------------- - */ -UINT32 -GetWorstCaseContextSize ( - IN DEVICE_BLOCK_HEADER *DeviceList, - IN CALL_POINTS CallPoint, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -VOID -SaveDeviceListContext ( - IN DEVICE_BLOCK_HEADER *DeviceList, - IN VOID *Storage, - IN CALL_POINTS CallPoint, - OUT UINT32 *ActualBufferSize, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -VOID -RestorePreESRContext ( - OUT VOID **OrMaskPtr, - IN VOID *Storage, - IN CALL_POINTS CallPoint, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -VOID -RestorePostESRContext ( - IN VOID *OrMaskPtr, - IN VOID *Storage, - IN CALL_POINTS CallPoint, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -VOID -AmdS3ParamsInitializer ( - OUT AMD_S3_PARAMS *S3Params - ); - -VOID -GetNonMemoryRelatedDeviceList ( - OUT DEVICE_BLOCK_HEADER **NonMemoryRelatedDeviceList, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -AGESA_STATUS -S3GetPciDeviceRegisterList ( - IN PCI_DEVICE_DESCRIPTOR *Device, - OUT PCI_REGISTER_BLOCK_HEADER **RegisterHdr, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -AGESA_STATUS -S3GetCPciDeviceRegisterList ( - IN CONDITIONAL_PCI_DEVICE_DESCRIPTOR *Device, - OUT CPCI_REGISTER_BLOCK_HEADER **RegisterHdr, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -AGESA_STATUS -S3GetMsrDeviceRegisterList ( - IN MSR_DEVICE_DESCRIPTOR *Device, - OUT MSR_REGISTER_BLOCK_HEADER **RegisterHdr, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -AGESA_STATUS -S3GetCMsrDeviceRegisterList ( - IN CONDITIONAL_MSR_DEVICE_DESCRIPTOR *Device, - OUT CMSR_REGISTER_BLOCK_HEADER **RegisterHdr, - IN AMD_CONFIG_PARAMS *StdHeader - ); - - -#endif // _S3_H_ diff --git a/src/vendorcode/amd/agesa/f12/Proc/CPU/Table.c b/src/vendorcode/amd/agesa/f12/Proc/CPU/Table.c deleted file mode 100644 index b6c69470c0..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/CPU/Table.c +++ /dev/null @@ -1,1730 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * AMD CPU Register Table Related Functions - * - * Set registers according to a set of register tables - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: CPU - * @e \$Revision: 50057 $ @e \$Date: 2011-04-01 13:30:57 +0800 (Fri, 01 Apr 2011) $ - * - */ -/* - ****************************************************************************** - * - * Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - ****************************************************************************** - */ - -/*---------------------------------------------------------------------------------------- - * M O D U L E S U S E D - *---------------------------------------------------------------------------------------- - */ -#include "AGESA.h" -#include "amdlib.h" -#include "Ids.h" -#include "Topology.h" -#include "OptionMultiSocket.h" -#include "cpuRegisters.h" -#include "cpuFamilyTranslation.h" -#include "Table.h" -#include "GeneralServices.h" -#include "cpuServices.h" -#include "cpuFeatures.h" -#include "CommonReturns.h" -#include "cpuL3Features.h" -#include "cpuEarlyInit.h" -#include "Filecode.h" -CODE_GROUP (G1_PEICC) -RDATA_GROUP (G1_PEICC) - -#define FILECODE PROC_CPU_TABLE_FILECODE - -extern OPTION_MULTISOCKET_CONFIGURATION OptionMultiSocketConfiguration; - -/*---------------------------------------------------------------------------------------- - * D E F I N I T I O N S A N D M A C R O S - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------- - * T Y P E D E F S A N D S T R U C T U R E S - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------- - * P R O T O T Y P E S O F L O C A L F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------- - * E X P O R T E D F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ -VOID -SetRegistersFromTablesAtEarly ( - IN CPU_SPECIFIC_SERVICES *FamilyServices, - IN AMD_CPU_EARLY_PARAMS *EarlyParams, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -extern BUILD_OPT_CFG UserOptions; -extern CPU_FAMILY_SUPPORT_TABLE L3FeatureFamilyServiceTable; - -/*---------------------------------------------------------------------------------------*/ -/** - * An iterator for all the Family and Model Register Tables. - * - * RegisterTableHandle should be set to NULL to begin iteration, the first time the method is - * invoked. Register tables can be processed, until this method returns NULL. RegisterTableHandle - * should simply be passed back to the method without modification or use by the caller. - * The table selector allows the relevant tables for different cores to be iterated, if the family separates - * tables. For example, MSRs can be in a table processed by all cores and PCI registers in a table processed by - * primary cores. - * - * @param[in] FamilySpecificServices The current Family Specific Services. - * @param[in] Selector Select whether to iterate over tables for either all cores, primary cores, bsp, .... - * @param[in,out] RegisterTableHandle IN: The handle of the current register table, or NULL if Begin. - * OUT: The handle of the next register table, if not End. - * @param[out] NumberOfEntries The number of entries in the table returned, if not End. - * @param[in] StdHeader Handle of Header for calling lib functions and services. - * - * @return The pointer to the next Register Table, or NULL if End. - */ -TABLE_ENTRY_FIELDS -STATIC -*GetNextRegisterTable ( - IN CPU_SPECIFIC_SERVICES *FamilySpecificServices, - IN TABLE_CORE_SELECTOR Selector, - IN OUT REGISTER_TABLE ***RegisterTableHandle, - OUT UINTN *NumberOfEntries, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - REGISTER_TABLE **NextTable; - TABLE_ENTRY_FIELDS *Entries; - - ASSERT ((FamilySpecificServices != NULL) && (StdHeader != NULL)); - ASSERT (Selector < TableCoreSelectorMax); - - NextTable = *RegisterTableHandle; - if (NextTable == NULL) { - // Begin - NextTable = FamilySpecificServices->RegisterTableList; - IDS_OPTION_HOOK (IDS_REG_TABLE, &NextTable, StdHeader); - } else { - NextTable++; - } - // skip if not selected - while ((*NextTable != NULL) && (*NextTable)->Selector != Selector) { - NextTable++; - } - if (*NextTable == NULL) { - // End - *RegisterTableHandle = NULL; - Entries = NULL; - } else { - // Iterate next table - *RegisterTableHandle = NextTable; - *NumberOfEntries = (*NextTable)->NumberOfEntries; - Entries = (TABLE_ENTRY_FIELDS *) (*NextTable)->Table; - } - return Entries; -} - -/*---------------------------------------------------------------------------------------*/ -/** - * Compare counts to a pair of ranges. - * - * @param[in] FirstCount The actual count to be compared to the first range. - * @param[in] SecondCount The actual count to be compared to the second range. - * @param[in] Ranges The ranges which the counts are compared to. - * - * @retval TRUE Either one, or both, of the counts is in the range given. - * @retval FALSE Neither count is in the range given. - */ -BOOLEAN -IsEitherCountInRange ( - IN UINTN FirstCount, - IN UINTN SecondCount, - IN COUNT_RANGE_FEATURE Ranges - ) -{ - // Errors: Entire Range value is zero, Min and Max reversed or not <=, ranges overlap (OK if first range is all), - // the real counts are too big. - ASSERT ((Ranges.Range0Min <= Ranges.Range0Max) && - (Ranges.Range1Min <= Ranges.Range1Max) && - (Ranges.Range0Max != 0) && - (Ranges.Range1Max != 0) && - ((Ranges.Range0Max == COUNT_RANGE_HIGH) || (Ranges.Range0Max < Ranges.Range1Min)) && - ((FirstCount < COUNT_RANGE_HIGH) && (SecondCount < COUNT_RANGE_HIGH))); - - return (BOOLEAN) (((FirstCount <= Ranges.Range0Max) && (FirstCount >= Ranges.Range0Min)) || - ((SecondCount <= Ranges.Range1Max) && (SecondCount >= Ranges.Range1Min))); -} - -/*-------------------------------------------------------------------------------------*/ -/** - * Returns the performance profile features list of the currently running processor core. - * - * @param[out] Features The performance profile features supported by this platform - * @param[in] PlatformConfig Config handle for platform specific information - * @param[in] StdHeader Header for library and services - * - */ -VOID -GetPerformanceFeatures ( - OUT PERFORMANCE_PROFILE_FEATS *Features, - IN PLATFORM_CONFIGURATION *PlatformConfig, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - CPUID_DATA CpuidDataStruct; - CPU_SPECIFIC_SERVICES *FamilySpecificServices; - L3_FEATURE_FAMILY_SERVICES *FeatureFamilyServices; - - Features->PerformanceProfileValue = 0; - // Reflect Probe Filter Configuration. - Features->PerformanceProfileFeatures.ProbeFilter = 0; - if (IsFeatureEnabled (L3Features, PlatformConfig, StdHeader)) { - GetFeatureServicesOfCurrentCore (&L3FeatureFamilyServiceTable, (const VOID **) &FeatureFamilyServices, StdHeader); - if ((FeatureFamilyServices != NULL) && - (FeatureFamilyServices->IsHtAssistSupported (FeatureFamilyServices, PlatformConfig, StdHeader))) { - Features->PerformanceProfileFeatures.ProbeFilter = 1; - } - } - - // Reflect Display Refresh Requests use 32 bytes Configuration. - Features->PerformanceProfileFeatures.RefreshRequest32Byte = 0; - if (PlatformConfig->PlatformProfile.Use32ByteRefresh) { - Features->PerformanceProfileFeatures.RefreshRequest32Byte = 1; - } - // Reflect Mct Isoc Read Priority set to variable Configuration. - Features->PerformanceProfileFeatures.MctIsocVariable = 0; - if (PlatformConfig->PlatformProfile.UseVariableMctIsocPriority) { - Features->PerformanceProfileFeatures.MctIsocVariable = 1; - } - // Indicate if this boot is a warm reset. - Features->PerformanceProfileFeatures.IsWarmReset = 0; - if (IsWarmReset (StdHeader)) { - Features->PerformanceProfileFeatures.IsWarmReset = 1; - } - - // Get L3 Cache present as indicated by CPUID - Features->PerformanceProfileFeatures.L3Cache = 0; - Features->PerformanceProfileFeatures.NoL3Cache = 1; - LibAmdCpuidRead (AMD_CPUID_L2L3Cache_L2TLB, &CpuidDataStruct, StdHeader); - if (((CpuidDataStruct.EDX_Reg & 0xFFFC0000) >> 18) != 0) { - Features->PerformanceProfileFeatures.L3Cache = 1; - Features->PerformanceProfileFeatures.NoL3Cache = 0; - } - - // Get VRM select high speed from build option. - Features->PerformanceProfileFeatures.VrmHighSpeed = 0; - if (PlatformConfig->VrmProperties[CoreVrm].HiSpeedEnable) { - Features->PerformanceProfileFeatures.VrmHighSpeed = 1; - } - - // Get some family, model specific performance type info. - GetCpuServicesOfCurrentCore ((const CPU_SPECIFIC_SERVICES **)&FamilySpecificServices, StdHeader); - ASSERT (FamilySpecificServices != NULL); - - // Is the Northbridge P-State feature enabled - Features->PerformanceProfileFeatures.NbPstates = 0; - if (FamilySpecificServices->IsNbPstateEnabled (FamilySpecificServices, PlatformConfig, StdHeader)) { - Features->PerformanceProfileFeatures.NbPstates = 1; - } -} - -/*---------------------------------------------------------------------------------------*/ -/** - * Perform the MSR Register Entry. - * - * @TableEntryTypeMethod{::MsrRegister}. - * - * Read - Modify - Write the MSR, clearing masked bits, and setting the data bits. - * - * @param[in] Entry The MSR register entry to perform - * @param[in] PlatformConfig Config handle for platform specific information - * @param[in] StdHeader Config handle for library and services. - * - */ -VOID -SetRegisterForMsrEntry ( - IN TABLE_ENTRY_DATA *Entry, - IN PLATFORM_CONFIGURATION *PlatformConfig, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - UINT64 MsrData; - - // Even for only single bit fields, use those in the mask. "Mask nothing" is a bug, even if just by policy. - ASSERT (Entry->MsrEntry.Mask != 0); - - LibAmdMsrRead (Entry->MsrEntry.Address, &MsrData, StdHeader); - MsrData = MsrData & (~(Entry->MsrEntry.Mask)); - MsrData = MsrData | Entry->MsrEntry.Data; - LibAmdMsrWrite (Entry->MsrEntry.Address, &MsrData, StdHeader); -} - -/*---------------------------------------------------------------------------------------*/ -/** - * Perform the PCI Register Entry. - * - * @TableEntryTypeMethod{::PciRegister}. - * - * Make the current core's PCI address with the function and register for the entry. - * Read - Modify - Write the PCI register, clearing masked bits, and setting the data bits. - * - * @param[in] Entry The PCI register entry to perform - * @param[in] PlatformConfig Config handle for platform specific information - * @param[in] StdHeader Config handle for library and services. - * - */ -VOID -SetRegisterForPciEntry ( - IN TABLE_ENTRY_DATA *Entry, - IN PLATFORM_CONFIGURATION *PlatformConfig, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - UINT32 TempVar32_a; - UINT32 MySocket; - UINT32 MyModule; - UINT32 Ignored; - PCI_ADDR MyPciAddress; - AGESA_STATUS IgnoredSts; - TABLE_ENTRY_DATA PciEntry; - - // Errors: Possible values in unused entry space, extra type features, value range checks. - // Check that the entry type is correct and the actual supplied entry data is appropriate for that entry. - // Even for only single bit fields, use those in the mask. "Mask nothing" is a bug, even if just by policy. - ASSERT ((Entry->InitialValues[4] == 0) && - (Entry->InitialValues[3] == 0) && - (Entry->PciEntry.Mask != 0)); - - LibAmdMemFill (&PciEntry, 0, sizeof (TABLE_ENTRY_DATA), StdHeader); - PciEntry.PciEntry = Entry->PciEntry; - - IDS_OPTION_HOOK (IDS_SET_PCI_REGISTER_ENTRY, &PciEntry, StdHeader); - - IdentifyCore (StdHeader, &MySocket, &MyModule, &Ignored, &IgnoredSts); - GetPciAddress (StdHeader, MySocket, MyModule, &MyPciAddress, &IgnoredSts); - MyPciAddress.Address.Function = PciEntry.PciEntry.Address.Address.Function; - MyPciAddress.Address.Register = PciEntry.PciEntry.Address.Address.Register; - LibAmdPciRead (AccessWidth32, MyPciAddress, &TempVar32_a, StdHeader); - TempVar32_a = TempVar32_a & (~(PciEntry.PciEntry.Mask)); - TempVar32_a = TempVar32_a | PciEntry.PciEntry.Data; - LibAmdPciWrite (AccessWidth32, MyPciAddress, &TempVar32_a, StdHeader); -} - -/*---------------------------------------------------------------------------------------*/ -/** - * Perform the Family Specific Workaround Register Entry. - * - * @TableEntryTypeMethod{::FamSpecificWorkaround}. - * - * Call the function, passing the data. - * - * See if you can use the other entries or make an entry that covers the fix. - * After all, the purpose of having a table entry is to @b NOT have code which - * isn't generic feature code, but is family/model code specific to one case. - * - * @param[in] Entry The Family Specific Workaround register entry to perform - * @param[in] PlatformConfig Config handle for platform specific information - * @param[in] StdHeader Config handle for library and services. - * - */ -VOID -SetRegisterForFamSpecificWorkaroundEntry ( - IN TABLE_ENTRY_DATA *Entry, - IN PLATFORM_CONFIGURATION *PlatformConfig, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - ASSERT (Entry->FamSpecificEntry.DoAction != NULL); - - Entry->FamSpecificEntry.DoAction (Entry->FamSpecificEntry.Data, StdHeader); -} - -/*---------------------------------------------------------------------------------------*/ -/** - * Program HT Phy PCI registers using BKDG values. - * - * @TableEntryTypeMethod{::HtPhyRegister}. - * - * - * @param[in] Entry The type specific entry data to be implemented (that is written). - * @param[in] PlatformConfig Config handle for platform specific information - * @param[in] StdHeader Config params for library, services. - * - */ -VOID -SetRegisterForHtPhyEntry ( - IN TABLE_ENTRY_DATA *Entry, - IN PLATFORM_CONFIGURATION *PlatformConfig, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - UINT32 Link; - UINT32 MySocket; - UINT32 MyModule; - AGESA_STATUS IgnoredStatus; - UINT32 Ignored; - CPU_LOGICAL_ID CpuFamilyRevision; - PCI_ADDR CapabilitySet; - CPU_SPECIFIC_SERVICES *FamilySpecificServices; - BOOLEAN MatchedSublink1; - HT_FREQUENCIES Freq0; - HT_FREQUENCIES Freq1; - - // Errors: Possible values in unused entry space, extra type features, value range checks. - // Check that the entry type is correct and the actual supplied entry data is appropriate for that entry. - ASSERT ((Entry->InitialValues[4] == 0) && - ((Entry->HtPhyEntry.TypeFeats.HtPhyLinkValue & ~(HTPHY_LINKTYPE_ALL | HTPHY_LINKTYPE_SL0_AND | HTPHY_LINKTYPE_SL1_AND)) == 0) && - (Entry->HtPhyEntry.Address < HTPHY_REGISTER_MAX)); - - IdentifyCore (StdHeader, &MySocket, &MyModule, &Ignored, &IgnoredStatus); - GetPciAddress (StdHeader, MySocket, MyModule, &CapabilitySet, &IgnoredStatus); - GetLogicalIdOfCurrentCore (&CpuFamilyRevision, StdHeader); - GetCpuServicesFromLogicalId (&CpuFamilyRevision, (const CPU_SPECIFIC_SERVICES **)&FamilySpecificServices, StdHeader); - Link = 0; - while (FamilySpecificServices->NextLinkHasHtPhyFeats ( - FamilySpecificServices, - &CapabilitySet, - &Link, - &Entry->HtPhyEntry.TypeFeats, - &MatchedSublink1, - &Freq0, - &Freq1, - StdHeader)) { - FamilySpecificServices->SetHtPhyRegister (FamilySpecificServices, &Entry->HtPhyEntry, CapabilitySet, Link, StdHeader); - } -} - -/*---------------------------------------------------------------------------------------*/ -/** - * Program a range of HT Phy PCI registers using BKDG values. - * - * @TableEntryTypeMethod{::HtPhyRangeRegister}. - * - * - * @param[in] Entry The type specific entry data to be implemented (that is written). - * @param[in] PlatformConfig Config handle for platform specific information - * @param[in] StdHeader Config params for library, services. - * - */ -VOID -SetRegisterForHtPhyRangeEntry ( - IN TABLE_ENTRY_DATA *Entry, - IN PLATFORM_CONFIGURATION *PlatformConfig, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - UINT32 Link; - UINT32 MySocket; - UINT32 MyModule; - AGESA_STATUS IgnoredStatus; - UINT32 Ignored; - CPU_LOGICAL_ID CpuFamilyRevision; - PCI_ADDR CapabilitySet; - CPU_SPECIFIC_SERVICES *FamilySpecificServices; - HT_PHY_TYPE_ENTRY_DATA CurrentHtPhyRegister; - BOOLEAN MatchedSublink1; - HT_FREQUENCIES Freq0; - HT_FREQUENCIES Freq1; - - // Errors: Possible values in unused entry space, extra type features, value range checks. - // Check that the entry type is correct and the actual supplied entry data is appropriate for that entry. - ASSERT (((Entry->HtPhyRangeEntry.TypeFeats.HtPhyLinkValue & ~(HTPHY_LINKTYPE_ALL)) == 0) && - (Entry->HtPhyRangeEntry.LowAddress <= Entry->HtPhyRangeEntry.HighAddress) && - (Entry->HtPhyRangeEntry.HighAddress < HTPHY_REGISTER_MAX) && - (Entry->HtPhyRangeEntry.HighAddress != 0)); - - CurrentHtPhyRegister.Mask = Entry->HtPhyRangeEntry.Mask; - CurrentHtPhyRegister.Data = Entry->HtPhyRangeEntry.Data; - CurrentHtPhyRegister.TypeFeats = Entry->HtPhyRangeEntry.TypeFeats; - - IdentifyCore (StdHeader, &MySocket, &MyModule, &Ignored, &IgnoredStatus); - GetPciAddress (StdHeader, MySocket, MyModule, &CapabilitySet, &IgnoredStatus); - GetLogicalIdOfCurrentCore (&CpuFamilyRevision, StdHeader); - GetCpuServicesFromLogicalId (&CpuFamilyRevision, (const CPU_SPECIFIC_SERVICES **)&FamilySpecificServices, StdHeader); - Link = 0; - while (FamilySpecificServices->NextLinkHasHtPhyFeats ( - FamilySpecificServices, - &CapabilitySet, - &Link, - &Entry->HtPhyRangeEntry.TypeFeats, - &MatchedSublink1, - &Freq0, - &Freq1, - StdHeader)) { - for (CurrentHtPhyRegister.Address = Entry->HtPhyRangeEntry.LowAddress; - CurrentHtPhyRegister.Address <= Entry->HtPhyRangeEntry.HighAddress; - CurrentHtPhyRegister.Address++) { - FamilySpecificServices->SetHtPhyRegister (FamilySpecificServices, &CurrentHtPhyRegister, CapabilitySet, Link, StdHeader); - } - } -} - -/*----------------------------------------------------------------------------------------*/ -/** - * Is PackageLink an Internal Link? - * - * This is a test for the logical link match codes in the user interface, not a test for - * the actual northbridge links. - * - * @param[in] PackageLink The link - * - * @retval TRUE This is an internal link - * @retval FALSE This is not an internal link - */ -BOOLEAN -STATIC -IsDeemphasisLinkInternal ( - IN UINT32 PackageLink - ) -{ - return (BOOLEAN) ((PackageLink <= HT_LIST_MATCH_INTERNAL_LINK_2) && (PackageLink >= HT_LIST_MATCH_INTERNAL_LINK_0)); -} - -/*----------------------------------------------------------------------------------------*/ -/** - * Get the Package Link number, for the current node and real link number. - * - * Based on the link to package link mapping from BKDG, look up package link for - * the input link on the internal node number corresponding to the current core's node. - * For single module processors, the northbridge link and package link are the same. - * - * @param[in] Link the link on the current node. - * @param[in] FamilySpecificServices CPU specific support interface. - * @param[in] StdHeader Config params for library, services. - * - * @return the Package Link, HT_LIST_TERMINAL Not connected in package, HT_LIST_MATCH_INTERNAL_LINK package internal link. - * - */ -UINT32 -STATIC -LookupPackageLink ( - IN UINT32 Link, - IN CPU_SPECIFIC_SERVICES *FamilySpecificServices, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - UINT32 PackageLinkMapItem; - UINT32 PackageLink; - AP_MAIL_INFO ApMailbox; - - PackageLink = HT_LIST_TERMINAL; - - GetApMailbox (&ApMailbox.Info, StdHeader); - - if (ApMailbox.Fields.ModuleType != 0) { - ASSERT (FamilySpecificServices->PackageLinkMap != NULL); - // Use table to find this module's package link - PackageLinkMapItem = 0; - while ((*FamilySpecificServices->PackageLinkMap)[PackageLinkMapItem].Link != HT_LIST_TERMINAL) { - if (((*FamilySpecificServices->PackageLinkMap)[PackageLinkMapItem].Module == ApMailbox.Fields.Module) && - ((*FamilySpecificServices->PackageLinkMap)[PackageLinkMapItem].Link == Link)) { - PackageLink = (*FamilySpecificServices->PackageLinkMap)[PackageLinkMapItem].PackageLink; - break; - } - PackageLinkMapItem++; - } - } else { - PackageLink = Link; - } - return PackageLink; -} - -/*---------------------------------------------------------------------------------------*/ -/** - * Get the platform's specified deemphasis levels for the current link. - * - * Search the platform's list for a match to the current link and also matching frequency. - * If a match is found, use the specified deemphasis levels. - * - * @param[in] Socket The current Socket. - * @param[in] Link The link on that socket. - * @param[in] Frequency The frequency the link is set to. - * @param[in] PlatformConfig Config handle for platform specific information - * @param[in] FamilySpecificServices CPU specific support interface. - * @param[in] StdHeader Config params for library, services. - * - * @return The Deemphasis values for the link. - */ -UINT32 -STATIC -GetLinkDeemphasis ( - IN UINT32 Socket, - IN UINT32 Link, - IN HT_FREQUENCIES Frequency, - IN PLATFORM_CONFIGURATION *PlatformConfig, - IN CPU_SPECIFIC_SERVICES *FamilySpecificServices, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - UINT32 Result; - CPU_HT_DEEMPHASIS_LEVEL *Match; - UINT32 PackageLink; - - PackageLink = LookupPackageLink (Link, FamilySpecificServices, StdHeader); - // All External and Internal links have deemphasis level none as the default. - // However, it is expected that the platform BIOS will provide deemphasis levels for the external links. - Result = ((DCV_LEVEL_NONE) | (DEEMPHASIS_LEVEL_NONE)); - - if (PlatformConfig->PlatformDeemphasisList != NULL) { - Match = PlatformConfig->PlatformDeemphasisList; - while (Match->Socket != HT_LIST_TERMINAL) { - if (((Match->Socket == Socket) || (Match->Socket == HT_LIST_MATCH_ANY)) && - ((Match->Link == PackageLink) || - ((Match->Link == HT_LIST_MATCH_ANY) && (!IsDeemphasisLinkInternal (PackageLink))) || - ((Match->Link == HT_LIST_MATCH_INTERNAL_LINK) && (IsDeemphasisLinkInternal (PackageLink)))) && - ((Match->LoFreq <= Frequency) && (Match->HighFreq >= Frequency))) { - // Found a match, get the deemphasis value. - ASSERT ((MaxPlatformDeemphasisLevel > Match->DcvDeemphasis) | (MaxPlatformDeemphasisLevel > Match->ReceiverDeemphasis)); - Result = ((1 << Match->DcvDeemphasis) | (1 << Match->ReceiverDeemphasis)); - break; - } else { - Match++; - } - } - } - return Result; -} - -/*---------------------------------------------------------------------------------------*/ -/** - * Program Deemphasis registers using BKDG values, for the platform specified levels. - * - * @TableEntryTypeMethod{::DeemphasisRegister}. - * - * - * @param[in] Entry The type specific entry data to be implemented (that is written). - * @param[in] PlatformConfig Config handle for platform specific information - * @param[in] StdHeader Config params for library, services. - * - */ -VOID -SetRegisterForDeemphasisEntry ( - IN TABLE_ENTRY_DATA *Entry, - IN PLATFORM_CONFIGURATION *PlatformConfig, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - UINT32 Link; - UINT32 MySocket; - UINT32 MyModule; - AGESA_STATUS IgnoredStatus; - UINT32 Ignored; - CPU_LOGICAL_ID CpuFamilyRevision; - PCI_ADDR CapabilitySet; - CPU_SPECIFIC_SERVICES *FamilySpecificServices; - BOOLEAN MatchedSublink1; - HT_FREQUENCIES Freq0; - HT_FREQUENCIES Freq1; - - // Errors: Possible values in unused entry space, extra type features, value range checks. - // Check that the entry type is correct and the actual supplied entry data is appropriate for that entry. - ASSERT (((Entry->DeemphasisEntry.Levels.DeemphasisValues & ~(VALID_DEEMPHASIS_LEVELS)) == 0) && - ((Entry->DeemphasisEntry.HtPhyEntry.TypeFeats.HtPhyLinkValue & ~(HTPHY_LINKTYPE_ALL)) == 0) && - (Entry->DeemphasisEntry.HtPhyEntry.Address < HTPHY_REGISTER_MAX)); - - IdentifyCore (StdHeader, &MySocket, &MyModule, &Ignored, &IgnoredStatus); - GetPciAddress (StdHeader, MySocket, MyModule, &CapabilitySet, &IgnoredStatus); - GetLogicalIdOfCurrentCore (&CpuFamilyRevision, StdHeader); - GetCpuServicesFromLogicalId (&CpuFamilyRevision, (const CPU_SPECIFIC_SERVICES **)&FamilySpecificServices, StdHeader); - Link = 0; - while (FamilySpecificServices->NextLinkHasHtPhyFeats ( - FamilySpecificServices, - &CapabilitySet, - &Link, - &Entry->DeemphasisEntry.HtPhyEntry.TypeFeats, - &MatchedSublink1, - &Freq0, - &Freq1, - StdHeader)) { - if (DoesEntryTypeSpecificInfoMatch ( - GetLinkDeemphasis ( - MySocket, - (MatchedSublink1 ? (Link + 4) : Link), - (MatchedSublink1 ? Freq1 : Freq0), - PlatformConfig, - FamilySpecificServices, - StdHeader), - Entry->DeemphasisEntry.Levels.DeemphasisValues)) { - FamilySpecificServices->SetHtPhyRegister ( - FamilySpecificServices, - &Entry->DeemphasisEntry.HtPhyEntry, - CapabilitySet, - Link, - StdHeader - ); - IDS_HDT_CONSOLE (HT_TRACE, "Socket %d Module %d Sub-link %1d :\n ----> running on HT3, %s Level is %s\n", - MySocket, MyModule, - ((Entry->DeemphasisEntry.HtPhyEntry.TypeFeats.HtPhyLinkValue & HTPHY_LINKTYPE_SL0_ALL) != 0) ? Link : (Link + 4), - ((Entry->DeemphasisEntry.Levels.DeemphasisValues & DCV_LEVELS_ALL) != 0) ? "DCV" : "Deemphasis", - (Entry->DeemphasisEntry.Levels.DeemphasisValues == DEEMPHASIS_LEVEL_NONE) ? " 0 dB" : - (Entry->DeemphasisEntry.Levels.DeemphasisValues == DEEMPHASIS_LEVEL__3) ? " - 3 dB" : - (Entry->DeemphasisEntry.Levels.DeemphasisValues == DEEMPHASIS_LEVEL__6) ? " - 6 dB" : - (Entry->DeemphasisEntry.Levels.DeemphasisValues == DEEMPHASIS_LEVEL__6) ? " - 6 dB" : - (Entry->DeemphasisEntry.Levels.DeemphasisValues == DEEMPHASIS_LEVEL__8) ? " - 8 dB" : - (Entry->DeemphasisEntry.Levels.DeemphasisValues == DEEMPHASIS_LEVEL__11) ? " - 11 dB" : - (Entry->DeemphasisEntry.Levels.DeemphasisValues == DEEMPHASIS_LEVEL__11_8) ? " - 11 dB postcursor with - 8 dB precursor" : - (Entry->DeemphasisEntry.Levels.DeemphasisValues == DCV_LEVEL_NONE) ? " 0 dB" : - (Entry->DeemphasisEntry.Levels.DeemphasisValues == DCV_LEVEL__2) ? " - 2 dB" : - (Entry->DeemphasisEntry.Levels.DeemphasisValues == DCV_LEVEL__3) ? " - 3 dB" : - (Entry->DeemphasisEntry.Levels.DeemphasisValues == DCV_LEVEL__5) ? " - 5 dB" : - (Entry->DeemphasisEntry.Levels.DeemphasisValues == DCV_LEVEL__6) ? " - 6 dB" : - (Entry->DeemphasisEntry.Levels.DeemphasisValues == DCV_LEVEL__7) ? " - 7 dB" : - (Entry->DeemphasisEntry.Levels.DeemphasisValues == DCV_LEVEL__8) ? " - 8 dB" : - (Entry->DeemphasisEntry.Levels.DeemphasisValues == DCV_LEVEL__9) ? " - 9 dB" : - (Entry->DeemphasisEntry.Levels.DeemphasisValues == DCV_LEVEL__11) ? " - 11 dB" : "Undefined"); - } - } -} - -/*---------------------------------------------------------------------------------------*/ -/** - * Program HT Phy PCI registers which have complex frequency dependencies. - * - * @TableEntryTypeMethod{::HtPhyFreqRegister}. - * - * After matching a link for HT Features, check if the HT frequency matches the given range. - * If it does, get the northbridge frequency limits for implemented NB P-states and check if - * each matches the given range - range 0 and range 1 for each NB frequency, respectively. - * If all matches, apply the entry. - * - * @param[in] Entry The type specific entry data to be implemented (that is written). - * @param[in] PlatformConfig Config handle for platform specific information - * @param[in] StdHeader Config params for library, services. - * - */ -VOID -SetRegisterForHtPhyFreqEntry ( - IN TABLE_ENTRY_DATA *Entry, - IN PLATFORM_CONFIGURATION *PlatformConfig, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - UINT32 Link; - UINT32 MySocket; - UINT32 MyModule; - AGESA_STATUS IgnoredStatus; - UINT32 Ignored; - CPU_LOGICAL_ID CpuFamilyRevision; - PCI_ADDR CapabilitySet; - CPU_SPECIFIC_SERVICES *FamilySpecificServices; - BOOLEAN MatchedSublink1; - HT_FREQUENCIES Freq0; - HT_FREQUENCIES Freq1; - BOOLEAN Temp1; - BOOLEAN Temp2; - UINT32 NbFreq0; - UINT32 NbFreq1; - UINT32 NbDivisor0; - UINT32 NbDivisor1; - - // Errors: extra type features, value range checks. - // Check that the entry type is correct and the actual supplied entry data is appropriate for that entry. - ASSERT (((Entry->HtPhyFreqEntry.HtPhyEntry.TypeFeats.HtPhyLinkValue & ~(HTPHY_LINKTYPE_ALL)) == 0) && - (Entry->HtPhyFreqEntry.HtPhyEntry.Address < HTPHY_REGISTER_MAX)); - - IdentifyCore (StdHeader, &MySocket, &MyModule, &Ignored, &IgnoredStatus); - GetPciAddress (StdHeader, MySocket, MyModule, &CapabilitySet, &IgnoredStatus); - GetLogicalIdOfCurrentCore (&CpuFamilyRevision, StdHeader); - GetCpuServicesFromLogicalId (&CpuFamilyRevision, (const CPU_SPECIFIC_SERVICES **)&FamilySpecificServices, StdHeader); - Link = 0; - while (FamilySpecificServices->NextLinkHasHtPhyFeats ( - FamilySpecificServices, - &CapabilitySet, - &Link, - &Entry->HtPhyFreqEntry.HtPhyEntry.TypeFeats, - &MatchedSublink1, - &Freq0, - &Freq1, - StdHeader)) { - // Check the HT Frequency for match to the range. - if (IsEitherCountInRange ( - (MatchedSublink1 ? Freq1 : Freq0), - (MatchedSublink1 ? Freq1 : Freq0), - Entry->HtPhyFreqEntry.HtFreqCounts.HtFreqCountRanges)) { - // Get the NB Frequency, convert to 100's of MHz, then convert to equivalent HT encoding. This supports - // NB frequencies from 800 MHz to 2600 MHz, which is currently greater than any processor supports. - OptionMultiSocketConfiguration.GetSystemNbPstateSettings ( - (UINT32) 0, - PlatformConfig, - &NbFreq0, - &NbDivisor0, - &Temp1, - &Temp2, - StdHeader); - - if (OptionMultiSocketConfiguration.GetSystemNbPstateSettings ( - (UINT32) 1, - PlatformConfig, - &NbFreq1, - &NbDivisor1, - &Temp1, - &Temp2, - StdHeader)) { - ASSERT (NbDivisor1 != 0); - NbFreq1 = (NbFreq1 / NbDivisor1); - NbFreq1 = (NbFreq1 / 100); - NbFreq1 = (NbFreq1 / 2) + 1; - } else { - NbFreq1 = 0; - } - - ASSERT (NbDivisor0 != 0); - NbFreq0 = (NbFreq0 / NbDivisor0); - NbFreq0 = (NbFreq0 / 100); - NbFreq0 = (NbFreq0 / 2) + 1; - if (IsEitherCountInRange (NbFreq0, NbFreq1, Entry->HtPhyFreqEntry.NbFreqCounts.HtFreqCountRanges)) { - FamilySpecificServices->SetHtPhyRegister ( - FamilySpecificServices, - &Entry->HtPhyFreqEntry.HtPhyEntry, - CapabilitySet, - Link, - StdHeader); - } - } - } -} - -/*---------------------------------------------------------------------------------------*/ -/** - * Perform the Performance Profile PCI Register Entry. - * - * @TableEntryTypeMethod{::ProfileFixup}. - * - * Check the entry's performance profile features to the platform's and do the - * PCI register entry if they match. - * - * @param[in] Entry The Performance Profile register entry to perform - * @param[in] PlatformConfig Config handle for platform specific information - * @param[in] StdHeader Config handle for library and services. - * - */ -VOID -SetRegisterForPerformanceProfileEntry ( - IN TABLE_ENTRY_DATA *Entry, - IN PLATFORM_CONFIGURATION *PlatformConfig, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - PERFORMANCE_PROFILE_FEATS PlatformProfile; - TABLE_ENTRY_DATA PciEntry; - - // Errors: Possible values in unused entry space, extra type features, value range checks. - // Check that the entry type is correct and the actual supplied entry data is appropriate for that entry. - ASSERT (((Entry->TokenPciEntry.TypeFeats.PerformanceProfileValue & ~((PERFORMANCE_PROFILE_ALL) | (PERFORMANCE_AND))) == 0) && - (Entry->InitialValues[4] == 0)); - - GetPerformanceFeatures (&PlatformProfile, PlatformConfig, StdHeader); - if (DoesEntryTypeSpecificInfoMatch (PlatformProfile.PerformanceProfileValue, - Entry->FixupEntry.TypeFeats.PerformanceProfileValue)) { - LibAmdMemFill (&PciEntry, 0, sizeof (TABLE_ENTRY_DATA), StdHeader); - PciEntry.PciEntry = Entry->FixupEntry.PciEntry; - SetRegisterForPciEntry (&PciEntry, PlatformConfig, StdHeader); - } -} - -/*---------------------------------------------------------------------------------------*/ -/** - * Perform the HT Phy Performance Profile Register Entry. - * - * @TableEntryTypeMethod{::HtPhyProfileRegister}. - * - * @param[in] Entry The HT Phy register entry to perform - * @param[in] PlatformConfig Config handle for platform specific information - * @param[in] StdHeader Config handle for library and services. - * - */ -VOID -SetRegisterForHtPhyProfileEntry ( - IN TABLE_ENTRY_DATA *Entry, - IN PLATFORM_CONFIGURATION *PlatformConfig, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - PERFORMANCE_PROFILE_FEATS PlatformProfile; - TABLE_ENTRY_DATA HtPhyEntry; - - // Errors: Possible values in unused entry space, extra type features, value range checks. - // Check that the entry type is correct and the actual supplied entry data is appropriate for that entry. - ASSERT (((Entry->HtPhyProfileEntry.TypeFeats.PerformanceProfileValue & ~((PERFORMANCE_PROFILE_ALL) | (PERFORMANCE_AND))) == 0) && - (Entry->InitialValues[5] == 0)); - - GetPerformanceFeatures (&PlatformProfile, PlatformConfig, StdHeader); - if (DoesEntryTypeSpecificInfoMatch ( - PlatformProfile.PerformanceProfileValue, - Entry->HtPhyProfileEntry.TypeFeats.PerformanceProfileValue)) { - LibAmdMemFill (&HtPhyEntry, 0, sizeof (TABLE_ENTRY_DATA), StdHeader); - HtPhyEntry.HtPhyEntry = Entry->HtPhyProfileEntry.HtPhyEntry; - SetRegisterForHtPhyEntry (&HtPhyEntry, PlatformConfig, StdHeader); - } -} - -/*---------------------------------------------------------------------------------------*/ -/** - * Perform the HT Host PCI Register Entry. - * - * @TableEntryTypeMethod{::HtHostPciRegister}. - * - * Make the current core's PCI address with the function and register for the entry. - * For all HT links, check the link's feature set for a match to the entry. - * Read - Modify - Write the PCI register, clearing masked bits, and setting the data bits. - * - * @param[in] Entry The PCI register entry to perform - * @param[in] PlatformConfig Config handle for platform specific information - * @param[in] StdHeader Config handle for library and services. - * - */ -VOID -SetRegisterForHtHostEntry ( - IN TABLE_ENTRY_DATA *Entry, - IN PLATFORM_CONFIGURATION *PlatformConfig, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - UINTN Link; - UINT32 MySocket; - UINT32 MyModule; - AGESA_STATUS IgnoredStatus; - UINT32 Ignored; - CPU_LOGICAL_ID CpuFamilyRevision; - CPU_SPECIFIC_SERVICES *FamilySpecificServices; - PCI_ADDR CapabilitySet; - PCI_ADDR PciAddress; - HT_HOST_FEATS HtHostFeats; - UINT32 RegisterData; - - // Errors: Possible values in unused entry space, extra type features, value range checks. - // Check that the entry type is correct and the actual supplied entry data is appropriate for that entry. - ASSERT ((Entry->InitialValues[4] == 0) && - ((Entry->HtHostEntry.TypeFeats.HtHostValue & ~((HT_HOST_FEATURES_ALL) | (HT_HOST_AND))) == 0) && - (Entry->HtHostEntry.Address.Address.Register < HT_LINK_HOST_CAP_MAX)); - - HtHostFeats.HtHostValue = 0; - IdentifyCore (StdHeader, &MySocket, &MyModule, &Ignored, &IgnoredStatus); - GetPciAddress (StdHeader, MySocket, MyModule, &CapabilitySet, &IgnoredStatus); - GetLogicalIdOfCurrentCore (&CpuFamilyRevision, StdHeader); - GetCpuServicesFromLogicalId (&CpuFamilyRevision, (const CPU_SPECIFIC_SERVICES **)&FamilySpecificServices, StdHeader); - Link = 0; - while (FamilySpecificServices->GetNextHtLinkFeatures (FamilySpecificServices, &Link, &CapabilitySet, &HtHostFeats, StdHeader)) { - if (DoesEntryTypeSpecificInfoMatch (HtHostFeats.HtHostValue, Entry->HtHostEntry.TypeFeats.HtHostValue)) { - // Do the HT Host PCI register update. - PciAddress = CapabilitySet; - PciAddress.Address.Register += Entry->HtHostEntry.Address.Address.Register; - LibAmdPciRead (AccessWidth32, PciAddress, &RegisterData, StdHeader); - RegisterData = RegisterData & (~(Entry->HtHostEntry.Mask)); - RegisterData = RegisterData | Entry->HtHostEntry.Data; - LibAmdPciWrite (AccessWidth32, PciAddress, &RegisterData, StdHeader); - } - } -} - -/*---------------------------------------------------------------------------------------*/ -/** - * Perform the HT Host Performance PCI Register Entry. - * - * @TableEntryTypeMethod{::HtHostPerfPciRegister}. - * - * Make the current core's PCI address with the function and register for the entry. - * For all HT links, check the link's feature set for a match to the entry. - * Read - Modify - Write the PCI register, clearing masked bits, and setting the data bits. - * - * @param[in] Entry The PCI register entry to perform - * @param[in] PlatformConfig Config handle for platform specific information - * @param[in] StdHeader Config handle for library and services. - * - */ -VOID -SetRegisterForHtHostPerfEntry ( - IN TABLE_ENTRY_DATA *Entry, - IN PLATFORM_CONFIGURATION *PlatformConfig, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - PERFORMANCE_PROFILE_FEATS PlatformProfile; - TABLE_ENTRY_DATA HtHostPciTypeEntryData; - - // Errors: Possible values in unused entry space, extra type features, value range checks. - // Check that the entry type is correct and the actual supplied entry data is appropriate for that entry. - ASSERT ((Entry->InitialValues[5] == 0) && - ((Entry->HtHostEntry.TypeFeats.HtHostValue & ~((HT_HOST_FEATURES_ALL) | (HT_HOST_AND))) == 0) && - (Entry->HtHostEntry.Address.Address.Register < HT_LINK_HOST_CAP_MAX)); - - // Check for any performance profile features. - GetPerformanceFeatures (&PlatformProfile, PlatformConfig, StdHeader); - if (DoesEntryTypeSpecificInfoMatch (PlatformProfile.PerformanceProfileValue, - Entry->HtHostPerfEntry.PerformanceFeats.PerformanceProfileValue)) { - // Perform HT Host entry process. - LibAmdMemFill (&HtHostPciTypeEntryData, 0, sizeof (TABLE_ENTRY_DATA), StdHeader); - HtHostPciTypeEntryData.HtHostEntry = Entry->HtHostPerfEntry.HtHostEntry; - SetRegisterForHtHostEntry (&HtHostPciTypeEntryData, PlatformConfig, StdHeader); - } -} - -/*---------------------------------------------------------------------------------------*/ -/** - * Set the HT Link Token Count registers. - * - * @TableEntryTypeMethod{::HtTokenPciRegister}. - * - * Make the current core's PCI address with the function and register for the entry. - * Check the performance profile features. - * For all HT links, check the link's feature set for a match to the entry. - * Read - Modify - Write the PCI register, clearing masked bits, and setting the data bits. - * - * @param[in] Entry The Link Token register entry to perform - * @param[in] PlatformConfig Config handle for platform specific information - * @param[in] StdHeader Config handle for library and services. - * - */ -VOID -SetRegisterForHtLinkTokenEntry ( - IN TABLE_ENTRY_DATA *Entry, - IN PLATFORM_CONFIGURATION *PlatformConfig, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - UINTN Link; - UINT32 MySocket; - UINT32 MyModule; - AGESA_STATUS IgnoredStatus; - UINT32 Ignored; - CPU_LOGICAL_ID CpuFamilyRevision; - CPU_SPECIFIC_SERVICES *FamilySpecificServices; - PCI_ADDR CapabilitySet; - HT_HOST_FEATS HtHostFeats; - PERFORMANCE_PROFILE_FEATS PlatformProfile; - UINTN ProcessorCount; - UINTN SystemDegree; - UINT32 RegisterData; - PCI_ADDR PciAddress; - - // Errors: Possible values in unused entry space, extra type features, value range checks. - // Check that the entry type is correct and the actual supplied entry data is appropriate for that entry. - ASSERT (((Entry->HtTokenEntry.LinkFeats.HtHostValue & ~((HT_HOST_FEATURES_ALL) | (HT_HOST_AND))) == 0) && - ((Entry->HtTokenEntry.PerformanceFeats.PerformanceProfileValue & ~((PERFORMANCE_PROFILE_ALL) | (PERFORMANCE_AND))) == 0) && - (Entry->HtTokenEntry.Mask != 0)); - - HtHostFeats.HtHostValue = 0; - IdentifyCore (StdHeader, &MySocket, &MyModule, &Ignored, &IgnoredStatus); - GetPciAddress (StdHeader, MySocket, MyModule, &CapabilitySet, &IgnoredStatus); - GetLogicalIdOfCurrentCore (&CpuFamilyRevision, StdHeader); - GetCpuServicesFromLogicalId (&CpuFamilyRevision, (const CPU_SPECIFIC_SERVICES **)&FamilySpecificServices, StdHeader); - - // Check if the actual processor count and SystemDegree are in either range. - ProcessorCount = GetNumberOfProcessors (StdHeader); - SystemDegree = GetSystemDegree (StdHeader); - if (IsEitherCountInRange (ProcessorCount, SystemDegree, Entry->HtTokenEntry.ConnectivityCount.ConnectivityCountRanges)) { - // Check for any performance profile features. - GetPerformanceFeatures (&PlatformProfile, PlatformConfig, StdHeader); - if (DoesEntryTypeSpecificInfoMatch (PlatformProfile.PerformanceProfileValue, - Entry->HtTokenEntry.PerformanceFeats.PerformanceProfileValue)) { - // Check the link features. - Link = 0; - while (FamilySpecificServices->GetNextHtLinkFeatures (FamilySpecificServices, &Link, &CapabilitySet, &HtHostFeats, StdHeader)) { - if (DoesEntryTypeSpecificInfoMatch (HtHostFeats.HtHostValue, Entry->HtTokenEntry.LinkFeats.HtHostValue)) { - // Do the HT Host PCI register update. Token register are four registers, sublink 0 and 1 share fields. - // If sublink 0 is unconnected, we should let sublink 1 match. If the links are ganged, of course only sublink 0 matches. - // If the links are unganged and both connected, the BKDG settings are for both coherent. - PciAddress = CapabilitySet; - PciAddress.Address.Register = Entry->HtTokenEntry.Address.Address.Register + - ((Link > 3) ? (((UINT32)Link - 4) * 4) : ((UINT32)Link * 4)); - PciAddress.Address.Function = Entry->HtTokenEntry.Address.Address.Function; - LibAmdPciRead (AccessWidth32, PciAddress, &RegisterData, StdHeader); - RegisterData = RegisterData & (~(Entry->HtTokenEntry.Mask)); - RegisterData = RegisterData | Entry->HtTokenEntry.Data; - LibAmdPciWrite (AccessWidth32, PciAddress, &RegisterData, StdHeader); - } - } - } - } -} - -/*---------------------------------------------------------------------------------------*/ -/** - * Perform the Core Counts Performance PCI Register Entry. - * - * @TableEntryTypeMethod{::CoreCountsPciRegister}. - * - * Check the performance profile. - * Check the actual core count to the range pair given, and apply if matched. - * - * @param[in] Entry The PCI register entry to perform - * @param[in] PlatformConfig Config handle for platform specific information - * @param[in] StdHeader Config handle for library and services. - * - */ -VOID -SetRegisterForCoreCountsPerformanceEntry ( - IN TABLE_ENTRY_DATA *Entry, - IN PLATFORM_CONFIGURATION *PlatformConfig, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - PERFORMANCE_PROFILE_FEATS PlatformProfile; - UINTN ActualCoreCount; - TABLE_ENTRY_DATA PciEntry; - - // Errors: Possible values in unused entry space, extra type features, value range checks. - // Check that the entry type is correct and the actual supplied entry data is appropriate for that entry. - ASSERT (((Entry->CoreCountEntry.TypeFeats.PerformanceProfileValue & ~((PERFORMANCE_PROFILE_ALL) | (PERFORMANCE_AND))) == 0)); - - GetPerformanceFeatures (&PlatformProfile, PlatformConfig, StdHeader); - if (DoesEntryTypeSpecificInfoMatch (PlatformProfile.PerformanceProfileValue, Entry->CoreCountEntry.TypeFeats.PerformanceProfileValue)) { - ActualCoreCount = GetActiveCoresInCurrentModule (StdHeader); - // Check if the actual core count is in either range. - if (IsEitherCountInRange (ActualCoreCount, ActualCoreCount, Entry->CoreCountEntry.CoreCounts.CoreRanges)) { - LibAmdMemFill (&PciEntry, 0, sizeof (TABLE_ENTRY_DATA), StdHeader); - PciEntry.PciEntry = Entry->CoreCountEntry.PciEntry; - SetRegisterForPciEntry (&PciEntry, PlatformConfig, StdHeader); - } - } -} - -/*---------------------------------------------------------------------------------------*/ -/** - * Perform the Processor Counts PCI Register Entry. - * - * @TableEntryTypeMethod{::ProcCountsPciRegister}. - * - * Check the performance profile. - * Check the actual processor count (not node count!) to the range pair given, and apply if matched. - * - * @param[in] Entry The PCI register entry to perform - * @param[in] PlatformConfig Config handle for platform specific information - * @param[in] StdHeader Config handle for library and services. - * - */ -VOID -SetRegisterForProcessorCountsEntry ( - IN TABLE_ENTRY_DATA *Entry, - IN PLATFORM_CONFIGURATION *PlatformConfig, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - PERFORMANCE_PROFILE_FEATS PlatformProfile; - UINTN ProcessorCount; - TABLE_ENTRY_DATA PciEntry; - - // Errors: Possible values in unused entry space, extra type features, value range checks. - // Check that the entry type is correct and the actual supplied entry data is appropriate for that entry. - ASSERT (((Entry->ProcCountEntry.TypeFeats.PerformanceProfileValue & ~((PERFORMANCE_PROFILE_ALL) | (PERFORMANCE_AND))) == 0)); - - GetPerformanceFeatures (&PlatformProfile, PlatformConfig, StdHeader); - if (DoesEntryTypeSpecificInfoMatch (PlatformProfile.PerformanceProfileValue, Entry->ProcCountEntry.TypeFeats.PerformanceProfileValue)) { - ProcessorCount = GetNumberOfProcessors (StdHeader); - // Check if the actual processor count is in either range. - if (IsEitherCountInRange (ProcessorCount, ProcessorCount, Entry->ProcCountEntry.ProcessorCounts.ProcessorCountRanges)) { - LibAmdMemFill (&PciEntry, 0, sizeof (TABLE_ENTRY_DATA), StdHeader); - PciEntry.PciEntry = Entry->ProcCountEntry.PciEntry; - SetRegisterForPciEntry (&PciEntry, PlatformConfig, StdHeader); - } - } -} - -/*---------------------------------------------------------------------------------------*/ -/** - * Perform the Compute Unit Counts PCI Register Entry. - * - * @TableEntryTypeMethod{::CompUnitCountsPciRegister}. - * - * Check the entry's performance profile features and the compute unit count - * to the platform's and do the PCI register entry if they match. - * - * @param[in] Entry The PCI register entry to perform - * @param[in] PlatformConfig Config handle for platform specific information - * @param[in] StdHeader Config handle for library and services. - * - */ -VOID -SetRegisterForComputeUnitCountsEntry ( - IN TABLE_ENTRY_DATA *Entry, - IN PLATFORM_CONFIGURATION *PlatformConfig, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - PERFORMANCE_PROFILE_FEATS PlatformProfile; - UINTN ComputeUnitCount; - TABLE_ENTRY_DATA PciEntry; - - // Errors: Possible values in unused entry space, extra type features, value range checks. - // Check that the entry type is correct and the actual supplied entry data is appropriate for that entry. - ASSERT (((Entry->CompUnitCountEntry.TypeFeats.PerformanceProfileValue & ~((PERFORMANCE_PROFILE_ALL) | (PERFORMANCE_AND))) == 0)); - - GetPerformanceFeatures (&PlatformProfile, PlatformConfig, StdHeader); - if (DoesEntryTypeSpecificInfoMatch (PlatformProfile.PerformanceProfileValue, Entry->CompUnitCountEntry.TypeFeats.PerformanceProfileValue)) { - ComputeUnitCount = GetNumberOfCompUnitsInCurrentModule (StdHeader); - // Check if the actual compute unit count is in either range. - if (IsEitherCountInRange (ComputeUnitCount, ComputeUnitCount, Entry->CompUnitCountEntry.ComputeUnitCounts.ComputeUnitRanges)) { - LibAmdMemFill (&PciEntry, 0, sizeof (TABLE_ENTRY_DATA), StdHeader); - PciEntry.PciEntry = Entry->CompUnitCountEntry.PciEntry; - SetRegisterForPciEntry (&PciEntry, PlatformConfig, StdHeader); - } - } -} - -/*---------------------------------------------------------------------------------------*/ -/** - * Perform the Compute Unit Counts MSR Register Entry. - * - * @TableEntryTypeMethod{::CompUnitCountsMsr}. - * - * Check the entry's compute unit count to the platform's and do the - * MSR entry if they match. - * - * @param[in] Entry The PCI register entry to perform - * @param[in] PlatformConfig Config handle for platform specific information - * @param[in] StdHeader Config handle for library and services. - * - */ -VOID -SetMsrForComputeUnitCountsEntry ( - IN TABLE_ENTRY_DATA *Entry, - IN PLATFORM_CONFIGURATION *PlatformConfig, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - UINTN ComputeUnitCount; - TABLE_ENTRY_DATA MsrEntry; - - ComputeUnitCount = GetNumberOfCompUnitsInCurrentModule (StdHeader); - // Check if the actual compute unit count is in either range. - if (IsEitherCountInRange (ComputeUnitCount, ComputeUnitCount, Entry->CompUnitCountMsrEntry.ComputeUnitCounts.ComputeUnitRanges)) { - LibAmdMemFill (&MsrEntry, 0, sizeof (TABLE_ENTRY_DATA), StdHeader); - MsrEntry.MsrEntry = Entry->CompUnitCountMsrEntry.MsrEntry; - SetRegisterForMsrEntry (&MsrEntry, PlatformConfig, StdHeader); - } -} - -/*---------------------------------------------------------------------------------------*/ -/** - * Perform the Processor Token Counts PCI Register Entry. - * - * @TableEntryTypeMethod{::TokenPciRegister}. - * - * The table criteria then translate as: - * - 2 Socket, half populated == Degree 1 - * - 4 Socket, half populated == Degree 2 - * - 2 Socket, fully populated == Degree 3 - * - 4 Socket, fully populated == Degree > 3. (4 or 5 if 3P, 6 if 4P) - * - * @param[in] Entry The PCI register entry to perform - * @param[in] PlatformConfig Config handle for platform specific information - * @param[in] StdHeader Config handle for library and services. - * - */ -VOID -SetRegisterForTokenPciEntry ( - IN TABLE_ENTRY_DATA *Entry, - IN PLATFORM_CONFIGURATION *PlatformConfig, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - PERFORMANCE_PROFILE_FEATS PlatformProfile; - UINTN SystemDegree; - TABLE_ENTRY_DATA PciEntry; - - // Errors: Possible values in unused entry space, extra type features, value range checks. - // Check that the entry type is correct and the actual supplied entry data is appropriate for that entry. - ASSERT (((Entry->TokenPciEntry.TypeFeats.PerformanceProfileValue & ~((PERFORMANCE_PROFILE_ALL) | (PERFORMANCE_AND))) == 0)); - - GetPerformanceFeatures (&PlatformProfile, PlatformConfig, StdHeader); - if (DoesEntryTypeSpecificInfoMatch (PlatformProfile.PerformanceProfileValue, Entry->TokenPciEntry.TypeFeats.PerformanceProfileValue)) { - SystemDegree = GetSystemDegree (StdHeader); - // Check if the system degree is in the range. - if (IsEitherCountInRange (SystemDegree, SystemDegree, Entry->TokenPciEntry.ConnectivityCount.ConnectivityCountRanges)) { - LibAmdMemFill (&PciEntry, 0, sizeof (TABLE_ENTRY_DATA), StdHeader); - PciEntry.PciEntry = Entry->TokenPciEntry.PciEntry; - SetRegisterForPciEntry (&PciEntry, PlatformConfig, StdHeader); - } - } -} - -/*---------------------------------------------------------------------------------------*/ -/** - * Perform the HT Link Feature PCI Register Entry. - * - * @TableEntryTypeMethod{::HtFeatPciRegister}. - * - * Set a single field (that is, the register field is not in HT Host capability or a - * set of per link registers) in PCI config, based on HT link features and package type. - * This code is used for two cases: single link processors and multilink processors. - * For single link cases, the link will be tested for a match to the HT Features for the link. - * For multilink processors, the entry will match if @b any link is found which matches. - * For example, a setting can be applied based on coherent HT3 by matching coherent AND HT3. - * - * Make the core's PCI address. Check the package type (currently more important to the single link case), - * and if matching, iterate through all links checking for an HT feature match until found or exhausted. - * If a match was found, pass the PCI entry data to the implementer for writing for the current core. - * - * @param[in] Entry The PCI register entry to perform - * @param[in] PlatformConfig Config handle for platform specific information - * @param[in] StdHeader Config handle for library and services. - * - */ -VOID -SetRegisterForHtFeaturePciEntry ( - IN TABLE_ENTRY_DATA *Entry, - IN PLATFORM_CONFIGURATION *PlatformConfig, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - UINTN Link; - UINT32 MySocket; - UINT32 MyModule; - AGESA_STATUS IgnoredStatus; - UINT32 Ignored; - CPU_LOGICAL_ID CpuFamilyRevision; - CPU_SPECIFIC_SERVICES *FamilySpecificServices; - PCI_ADDR CapabilitySet; - HT_HOST_FEATS HtHostFeats; - UINT32 ProcessorPackageType; - BOOLEAN IsMatch; - TABLE_ENTRY_DATA PciEntry; - - // Errors: Possible values in unused entry space, extra type features, value range checks. - // Check that the entry type is correct and the actual supplied entry data is appropriate for that entry. - ASSERT ((Entry->HtFeatPciEntry.PciEntry.Mask != 0) && - ((Entry->HtFeatPciEntry.LinkFeats.HtHostValue & ~((HT_HOST_FEATURES_ALL) | (HT_HOST_AND))) == 0)); - - HtHostFeats.HtHostValue = 0; - LibAmdMemFill (&PciEntry, 0, sizeof (TABLE_ENTRY_DATA), StdHeader); - PciEntry.PciEntry = Entry->HtFeatPciEntry.PciEntry; - IdentifyCore (StdHeader, &MySocket, &MyModule, &Ignored, &IgnoredStatus); - GetPciAddress (StdHeader, MySocket, MyModule, &CapabilitySet, &IgnoredStatus); - GetLogicalIdOfCurrentCore (&CpuFamilyRevision, StdHeader); - GetCpuServicesFromLogicalId (&CpuFamilyRevision, (const CPU_SPECIFIC_SERVICES **)&FamilySpecificServices, StdHeader); - - ASSERT ((Entry->HtFeatPciEntry.PackageType.PackageTypeValue & ~(PACKAGE_TYPE_ALL)) == 0); - - ProcessorPackageType = LibAmdGetPackageType (StdHeader); - if (DoesEntryTypeSpecificInfoMatch (ProcessorPackageType, Entry->HtFeatPciEntry.PackageType.PackageTypeValue)) { - IsMatch = FALSE; - while (FamilySpecificServices->GetNextHtLinkFeatures (FamilySpecificServices, &Link, &CapabilitySet, &HtHostFeats, StdHeader)) { - if (DoesEntryTypeSpecificInfoMatch (HtHostFeats.HtHostValue, Entry->HtFeatPciEntry.LinkFeats.HtHostValue)) { - IsMatch = TRUE; - break; - } - } - if (IsMatch) { - // Do the PCI register update. - SetRegisterForPciEntry (&PciEntry, PlatformConfig, StdHeader); - } - } -} - -/*---------------------------------------------------------------------------------------*/ -/** - * Perform the HT Link PCI Register Entry. - * - * @TableEntryTypeMethod{::HtLinkPciRegister}. - * - * Make the current core's PCI address with the function and register for the entry. - * Registers are processed for match per link, assuming sequential PCI address per link. - * Read - Modify - Write each matching link's PCI register, clearing masked bits, and setting the data bits. - * - * @param[in] Entry The PCI register entry to perform - * @param[in] PlatformConfig Config handle for platform specific information - * @param[in] StdHeader Config handle for library and services. - * - */ -VOID -SetRegisterForHtLinkPciEntry ( - IN TABLE_ENTRY_DATA *Entry, - IN PLATFORM_CONFIGURATION *PlatformConfig, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - UINTN Link; - UINT32 MySocket; - UINT32 MyModule; - AGESA_STATUS IgnoredStatus; - UINT32 Ignored; - CPU_LOGICAL_ID CpuFamilyRevision; - CPU_SPECIFIC_SERVICES *FamilySpecificServices; - PCI_ADDR CapabilitySet; - HT_HOST_FEATS HtHostFeats; - TABLE_ENTRY_DATA PciEntry; - - // Errors: Possible values in unused entry space, extra type features, value range checks. - // Check that the entry type is correct and the actual supplied entry data is appropriate for that entry. - ASSERT ((Entry->HtLinkPciEntry.PciEntry.Mask != 0) && - ((Entry->HtLinkPciEntry.LinkFeats.HtHostValue & ~((HT_HOST_FEATURES_ALL) | (HT_HOST_AND))) == 0)); - - HtHostFeats.HtHostValue = 0; - LibAmdMemFill (&PciEntry, 0, sizeof (TABLE_ENTRY_DATA), StdHeader); - PciEntry.PciEntry = Entry->HtLinkPciEntry.PciEntry; - IdentifyCore (StdHeader, &MySocket, &MyModule, &Ignored, &IgnoredStatus); - GetPciAddress (StdHeader, MySocket, MyModule, &CapabilitySet, &IgnoredStatus); - GetLogicalIdOfCurrentCore (&CpuFamilyRevision, StdHeader); - GetCpuServicesFromLogicalId (&CpuFamilyRevision, (const CPU_SPECIFIC_SERVICES **)&FamilySpecificServices, StdHeader); - - Link = 0; - while (FamilySpecificServices->GetNextHtLinkFeatures (FamilySpecificServices, &Link, &CapabilitySet, &HtHostFeats, StdHeader)) { - if (DoesEntryTypeSpecificInfoMatch (HtHostFeats.HtHostValue, Entry->HtLinkPciEntry.LinkFeats.HtHostValue)) { - // Do the update to the link's non-Host PCI register, based on the entry address. - PciEntry.PciEntry.Address = Entry->HtLinkPciEntry.PciEntry.Address; - PciEntry.PciEntry.Address.Address.Register = PciEntry.PciEntry.Address.Address.Register + ((UINT32)Link * 4); - SetRegisterForPciEntry (&PciEntry, PlatformConfig, StdHeader); - } - } -} - -/* -----------------------------------------------------------------------------*/ -/** - * Returns the platform features list of the currently running processor core. - * - * @param[out] Features The Features supported by this platform - * @param[in] PlatformConfig Config handle for platform specific information - * @param[in] StdHeader Header for library and services - * - */ -VOID -GetPlatformFeatures ( - OUT PLATFORM_FEATS *Features, - IN PLATFORM_CONFIGURATION *PlatformConfig, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - PCI_ADDR PciAddress; - UINT32 CapabilityReg; - UINT32 Link; - CPU_SPECIFIC_SERVICES *FamilySpecificServices; - UINT32 CoreCount; - - // Start with none. - Features->PlatformValue = 0; - - switch (PlatformConfig->PlatformProfile.PlatformControlFlowMode) { - case Nfcm: - Features->PlatformFeatures.PlatformNfcm = 1; - break; - case UmaDr: - Features->PlatformFeatures.PlatformUma = 1; - break; - case UmaIfcm: - Features->PlatformFeatures.PlatformUmaIfcm = 1; - break; - case Ifcm: - Features->PlatformFeatures.PlatformIfcm = 1; - break; - case Iommu: - Features->PlatformFeatures.PlatformIommu = 1; - break; - default: - ASSERT (FALSE); - } - // Check - Single Link? - // This is based on the implemented links on the package regardless of their - // connection status. All processors must match the BSP, so we only check it and - // not the current node. We don't care exactly how many links there are, as soon - // as we find more than one we are done. - Link = 0; - PciAddress.AddressValue = MAKE_SBDFO (0, 0, PCI_DEV_BASE, FUNC_0, 0); - // Until either all capabilities are done or until the desired link is found, - // keep looking for HT Host Capabilities. - while (Link < 2) { - LibAmdPciFindNextCap (&PciAddress, StdHeader); - if (PciAddress.AddressValue != ILLEGAL_SBDFO) { - LibAmdPciRead (AccessWidth32, PciAddress, &CapabilityReg, StdHeader); - if ((CapabilityReg & 0xE00000FF) == 0x20000008) { - Link++; - } - // A capability other than an HT capability, keep looking. - } else { - // end of capabilities - break; - } - } - if (Link < 2) { - Features->PlatformFeatures.PlatformSingleLink = 1; - } else { - Features->PlatformFeatures.PlatformMultiLink = 1; - } - - // Set the legacy core count bits. - GetActiveCoresInCurrentSocket (&CoreCount, StdHeader); - switch (CoreCount) { - case 1: - Features->PlatformFeatures.PlatformSingleCore = 1; - break; - case 2: - Features->PlatformFeatures.PlatformDualCore = 1; - break; - default: - Features->PlatformFeatures.PlatformMultiCore = 1; - } - - // - // Get some specific platform type info, VC...etc. - // - GetCpuServicesOfCurrentCore ((const CPU_SPECIFIC_SERVICES **)&FamilySpecificServices, StdHeader); - ASSERT (FamilySpecificServices != NULL); - FamilySpecificServices->GetPlatformTypeSpecificInfo (FamilySpecificServices, Features, StdHeader); - -} - -/*---------------------------------------------------------------------------------------*/ -/** - * Checks if a register table entry applies to the executing core. - * - * This function uses a combination of logical ID and platform features to - * determine whether or not a register table entry applies to the executing core. - * - * @param[in] CoreCpuRevision The current core's logical ID - * @param[in] EntryCpuRevision The entry's desired logical IDs - * @param[in] PlatformFeatures The platform features - * @param[in] EntryFeatures The entry's desired platform features - * - * @retval TRUE This entry should be applied - * @retval FALSE This entry does not apply - * - */ -BOOLEAN -STATIC -DoesEntryMatchPlatform ( - IN CPU_LOGICAL_ID CoreCpuRevision, - IN CPU_LOGICAL_ID EntryCpuRevision, - IN PLATFORM_FEATS PlatformFeatures, - IN PLATFORM_FEATS EntryFeatures - ) -{ - BOOLEAN Result; - - Result = FALSE; - - if (((CoreCpuRevision.Family & EntryCpuRevision.Family) != 0) && - ((CoreCpuRevision.Revision & EntryCpuRevision.Revision) != 0)) { - if (EntryFeatures.PlatformFeatures.AndPlatformFeats == 0) { - // Match if ANY entry feats match a platform feat (an OR test) - if ((EntryFeatures.PlatformValue & PlatformFeatures.PlatformValue) != 0) { - Result = TRUE; - } - } else { - // Match if ALL entry feats match a platform feat (an AND test) - if ((EntryFeatures.PlatformValue & ~(AMD_PF_AND)) == - (EntryFeatures.PlatformValue & PlatformFeatures.PlatformValue)) { - Result = TRUE; - } - } - } - - return Result; -} - -/*---------------------------------------------------------------------------------------*/ -/** - * Checks register table entry type specific criteria to the platform. - * - * Entry Data Type implementer methods can use this generically to check their own - * specific criteria. The method collects the actual platform characteristics and - * provides them along with the table entry's criteria to this service. - * - * There are a couple considerations for any implementer method using this service. - * The criteria value has to be representable as a UINT32. The MSB, Bit 31, has to - * be used as a AND test request if set in the entry. (The platform value should never - * have that bit set.) - * - * @param[in] PlatformTypeSpecificFeatures The platform features - * @param[in] EntryTypeFeatures The entry's desired platform features - * - * @retval TRUE This entry should be applied - * @retval FALSE This entry does not apply - * - */ -BOOLEAN -DoesEntryTypeSpecificInfoMatch ( - IN UINT32 PlatformTypeSpecificFeatures, - IN UINT32 EntryTypeFeatures - ) -{ - BOOLEAN Result; - - Result = FALSE; - - if ((EntryTypeFeatures & BIT31) == 0) { - // Match if ANY entry feats match a platform feat (an OR test) - if ((EntryTypeFeatures & PlatformTypeSpecificFeatures) != 0) { - Result = TRUE; - } - } else { - // Match if ALL entry feats match a platform feat (an AND test) - if ((EntryTypeFeatures & ~(BIT31)) == (EntryTypeFeatures & PlatformTypeSpecificFeatures)) { - Result = TRUE; - } - } - return Result; -} - -/*---------------------------------------------------------------------------------------*/ -/** - * Determine this core's Selector matches. - * - * @param[in] Selector Is the current core this selector type? - * @param[in] StdHeader Config handle for library and services. - * - * @retval TRUE Yes, it is. - * @retval FALSE No, it is not. - */ -BOOLEAN -STATIC -IsCoreSelector ( - IN TABLE_CORE_SELECTOR Selector, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - BOOLEAN Result; - AGESA_STATUS CalledStatus; - - Result = TRUE; - ASSERT (Selector < TableCoreSelectorMax); - - if ((Selector == PrimaryCores) && !IsCurrentCorePrimary (StdHeader)) { - Result = FALSE; - } - if ((Selector == CorePairPrimary) && !IsCorePairPrimary (FirstCoreIsComputeUnitPrimary, StdHeader)) { - Result = FALSE; - } - if ((Selector == BscCore) && (!IsBsp (StdHeader, &CalledStatus))) { - Result = FALSE; - } - return Result; -} - -/*---------------------------------------------------------------------------------------*/ -/** - * Set the registers for this core based on entries in a list of Register Tables. - * - * Determine the platform features and this core's logical id. Get the specific table - * entry type implementations for the logical model, which may be either generic (the ones - * in this file) or specific. - * - * Scan the tables starting the with ones for all cores and progressively narrowing the selection - * based on this core's role (ex. primary core). For a selected table, check for each entry - * matching the current core and platform, and call the implementer method to perform the - * register set operation if it matches. - * - * @param[in] PlatformConfig Config handle for platform specific information - * @param[in] StdHeader Config handle for library and services. - * - */ -VOID -SetRegistersFromTables ( - IN PLATFORM_CONFIGURATION *PlatformConfig, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - CPU_LOGICAL_ID CpuLogicalId; - PLATFORM_FEATS PlatformFeatures; - CPU_SPECIFIC_SERVICES *FamilySpecificServices; - TABLE_ENTRY_FIELDS *Entries; - TABLE_CORE_SELECTOR Selector; - TABLE_ENTRY_TYPE EntryType; - REGISTER_TABLE **TableHandle; - UINTN NumberOfEntries; - UINTN CurrentEntryCount; - TABLE_ENTRY_TYPE_DESCRIPTOR *TypeImplementer; - PF_DO_TABLE_ENTRY DoTableEntry[TableEntryTypeMax]; - - // Did you really mean to increase the size of ALL table entries??!! - // While it is not necessarily a bug to increase the size of table entries: - // - Is this warning a surprise? Please fix it. - // - If expected, is this really a feature which is worth the increase? Then let other entries also use the space. - ASSERT (sizeof (TABLE_ENTRY_DATA) == (MAX_ENTRY_TYPE_ITEMS32 * sizeof (UINT32))); - - PlatformFeatures.PlatformValue = 0; - GetLogicalIdOfCurrentCore (&CpuLogicalId, StdHeader); - GetPlatformFeatures (&PlatformFeatures, PlatformConfig, StdHeader); - GetCpuServicesFromLogicalId (&CpuLogicalId, (const CPU_SPECIFIC_SERVICES **)&FamilySpecificServices, StdHeader); - - // Build a non-sparse table of implementer methods, so we don't have to keep searching. - // It is a bug to not include a descriptor for a type that is in the table (but the - // descriptor can point to a non-assert stub). - // Also, it is not a bug to have no register table implementations, but it is a bug to have none and call this routine. - for (EntryType = MsrRegister; EntryType < TableEntryTypeMax; EntryType++) { - DoTableEntry[EntryType] = (PF_DO_TABLE_ENTRY)CommonAssert; - } - TypeImplementer = FamilySpecificServices->TableEntryTypeDescriptors; - ASSERT (TypeImplementer != NULL); - while (TypeImplementer->EntryType < TableEntryTypeMax) { - DoTableEntry[TypeImplementer->EntryType] = TypeImplementer->DoTableEntry; - TypeImplementer++; - } - - for (Selector = AllCores; Selector < TableCoreSelectorMax; Selector++) { - if (IsCoreSelector (Selector, StdHeader)) { - // If the current core is the selected type of core, work the table list for tables for that type of core. - TableHandle = NULL; - Entries = GetNextRegisterTable (FamilySpecificServices, Selector, &TableHandle, &NumberOfEntries, StdHeader); - while (Entries != NULL) { - for (CurrentEntryCount = 0; CurrentEntryCount < NumberOfEntries; CurrentEntryCount++, Entries++) { - if (DoesEntryMatchPlatform (CpuLogicalId, Entries->CpuRevision, PlatformFeatures, Entries->Features)) { - // The entry matches this config, Do It! - // Find the implementer for this entry type and pass the entry data to it. - ASSERT (Entries->EntryType < TableEntryTypeMax); - DoTableEntry[Entries->EntryType] (&Entries->Entry, PlatformConfig, StdHeader); - } - } - Entries = GetNextRegisterTable (FamilySpecificServices, Selector, &TableHandle, &NumberOfEntries, StdHeader); - } - } else { - // Once a selector does not match the current core, quit looking. - break; - } - } -} - -/*---------------------------------------------------------------------------------------*/ -/** - * Set the registers for this core based on entries in a list of Register Tables. - * - * This function acts as a wrapper for calling the SetRegistersFromTables - * routine at AmdInitEarly. - * - * @param[in] FamilyServices The current Family Specific Services. - * @param[in] EarlyParams Service parameters. - * @param[in] StdHeader Config handle for library and services. - * - */ -VOID -SetRegistersFromTablesAtEarly ( - IN CPU_SPECIFIC_SERVICES *FamilyServices, - IN AMD_CPU_EARLY_PARAMS *EarlyParams, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - AGESA_TESTPOINT (TpProcCpuProcessRegisterTables, StdHeader); - SetRegistersFromTables (&EarlyParams->PlatformConfig, StdHeader); -} diff --git a/src/vendorcode/amd/agesa/f12/Proc/CPU/Table.h b/src/vendorcode/amd/agesa/f12/Proc/CPU/Table.h deleted file mode 100644 index e2c7e14900..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/CPU/Table.h +++ /dev/null @@ -1,1294 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * AMD CPU Register Table Related Functions - * - * Contains code to initialize the CPU MSRs and PCI registers with BKDG recommended values - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: CPU - * @e \$Revision: 50057 $ @e \$Date: 2011-04-01 13:30:57 +0800 (Fri, 01 Apr 2011) $ - * - */ -/* - ****************************************************************************** - * - * Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - ****************************************************************************** - */ - -#ifndef _CPU_TABLE_H_ -#define _CPU_TABLE_H_ - -#define MAX_ENTRY_TYPE_ITEMS32 6 // The maximum number of initializer items for UINT32 entry data types. - -/** - * @page regtableimpl Register Table Implementation Guide - * - * This register table implementation is modular and extensible, so that support code as - * well as table data can be family specific or built out if not needed, and new types - * of table entries can be added with low overhead. Because many aspects are now generic, - * there can be common implementations for CPU revision and platform feature matching and for - * finding and iterating tables. - * - * @par Adding a new table entry type. - * - * To add a new table entry type follow these steps. - *
    - *
  • Add a member to the enum TABLE_ENTRY_TYPE which is a descriptive name of the entry's purpose - * or distinct characteristics. - * - *
  • Create an entry data struct with the customized data needed. For example, custom register designations, - * data and mask sizes, or feature comparisons. Name your struct by adding "_" and upper-casing the enum name - * and adding "_TYPE_ENTRY_DATA" at the end. - * - *
  • Add the entry data type as a member of the TABLE_ENTRY_DATA union. Be aware of the size of your - * entry data struct; all table entries in all tables will share any size increase you introduce! - * - *
  • If your data entry contains any member types except for UINT32, you can't use the generic first union member - * for the initializers that make up the actual tables (it's just UINT32's). The generic MSR entry is - * an example. Follow the steps below: - * - *
      - *
    • Make a union which has your entry data type as the first member. Use TABLE_ENTRY_DATA as the - * second member. Name this with your register followed by "_DATA_INITIALIZER". - * - *
    • Make a copy of TABLE_ENTRY_FIELDS, and rename it your register "_TYPE_ENTRY_INITIALIZER". Rename - * the TABLE_ENTRY_DATA member of that struct to have the type you created in the previous step. - * This type can be used to declare an array of entries and make a register table in some family specific - * file. - *
    - * - *
  • Add the descriptor that will link table entries of your data type to an implementation for it. - *
      - *
    • Find the options file which instantiates the CPU_SPECIFIC_SERVICES for each logical model that will - * support the new entry type. - * - *
    • From there find the instantiation of its TABLE_ENTRY_TYPE_DESCRIPTOR. Add a descriptor to the - * to the list for your new type. Provide the name of a function which will implement the - * entry data. The function name should reflect that it implements the action for the entry type. - * The function must be an instance of F_DO_TABLE_ENTRY. - *
    - * - *
  • Implement the function for your entry type data. (If parts of it are family specific add methods to - * CPU_SPECIFIC_SERVICES for that and implement them for each family or model required.) @n - * The definition of the function must conform to F_DO_TABLE_ENTRY. - * In the function preamble, include a cross reference to the entry enum: - * @code - * * - * * @TableEntryTypeMethod{::MyRegister} - * * - * @endcode - * - *
- * - * @par Adding a new Register Table - * - * To add a new register table for a logical CPU model follow the steps below. - * - *
    - *
  • Find the options file which instantiates the CPU_SPECIFIC_SERVICES for the logical model that - * should include the table. - * - *
  • From there find the instantiation of its REGISTER_TABLE list. Add the name of the new register table. - *
- * - */ - -/*------------------------------------------------------------------------------------------*/ -/* - * Define the supported table entries. - */ -/*------------------------------------------------------------------------------------------*/ - -/** - * These are the available types of table entries. - * - * Each type corresponds to: - * - a semantics for the type specific data, for example semantics for a Register value, - * Data value, and Mask value. - * - optionally, including a method for type specific matching criteria - * - a method for writing the desired update to the hardware. - * - * All types share in common a method to match CPU Family and Model and a method to match - * platform feature set. - * - */ -typedef enum { - MsrRegister, ///< Processor MSR registers. - PciRegister, ///< Processor Config Space registers. - FamSpecificWorkaround, ///< Processor Family Specific Workarounds which are @b not practical using the other types. - HtPhyRegister, ///< Processor HT Phy registers. - HtPhyRangeRegister, ///< Processor HT Phy range of contiguous registers (ex. 40h:48h). - DeemphasisRegister, ///< Processor Deemphasis register (HT Phy special case). - HtPhyFreqRegister, ///< Processor Frequency dependent HT Phy settings. - ProfileFixup, ///< Processor Performance Profile fixups to PCI Config Registers. - HtHostPciRegister, ///< Processor Ht Host capability registers (PCI Config). - HtHostPerfPciRegister, ///< Processor Ht Host capability registers which depend on performance features. - HtTokenPciRegister, ///< Processor Ht Link Token count registers. - CoreCountsPciRegister, ///< Processor PCI Config Registers which depend on core counts. - ProcCountsPciRegister, ///< Processor PCI Config Registers which depend on processor counts. - CompUnitCountsPciRegister, ///< Processor PCI Config Registers which depend on compute unit counts. - TokenPciRegister, ///< Processor northbridge Token Count register which may be dependent on connectivity. - HtFeatPciRegister, ///< Processor HT Link feature dependant PCI Config Registers. - HtPhyProfileRegister, ///< Processor HT Phy registers which depend on performance features. - HtLinkPciRegister, ///< Processor HT Link registers (one per link) not part of HT Host capability. - CompUnitCountsMsr, ///< Processor MSRs which depend on compute unit counts. - TableEntryTypeMax ///< Not a valid entry type, use for limit checking. -} TABLE_ENTRY_TYPE; - -/*------------------------------------------------------------------------------------------*/ -/* - * Useful types and defines: Selectors, Platform Features, and type specific features. - */ -/*------------------------------------------------------------------------------------------*/ - -/** - * Select tables for the current core. - * - * This allows more efficient register table processing, by allowing cores to skip - * redundantly setting PCI registers, for example. This feature is not intended to - * be relied on for function: it is valid to have a single register table with all settings - * processed by every core; it's just slower. - * - */ -typedef enum { - AllCores, ///< Select only tables which apply to all cores. - CorePairPrimary, ///< Select tables which apply to the primary core of a compute unit (SharedC, SharedNc). - PrimaryCores, ///< Select tables which apply to primary cores. - BscCore, ///< Select tables which apply to the boot core. - TableCoreSelectorMax ///< Not a valid selector, use for limit checking. -} TABLE_CORE_SELECTOR; - -// Initializer bit pattern values for platform features. -// Keep in synch with the PLATFORM_FEATURES struct! - -// The 5 control flow modes. -#define AMD_PF_NFCM BIT0 -#define AMD_PF_UMA BIT1 // UMA_DR -#define AMD_PF_UMA_IFCM BIT2 -#define AMD_PF_IFCM BIT3 -#define AMD_PF_IOMMU BIT4 -// Degree of HT connectivity possible. -#define AMD_PF_SINGLE_LINK BIT5 -#define AMD_PF_MULTI_LINK BIT6 -// For some legacy MSRs, define a couple core count bits. Do not continue adding -// core counts to the platform feats, if you need more than this design a table entry type. -// Here, provide exactly 1, exactly 2, or anything else. -#define AMD_PF_SINGLE_CORE BIT7 -#define AMD_PF_DUAL_CORE BIT8 -#define AMD_PF_MULTI_CORE BIT9 - -// Not a platform type, but treat all others as AND -#define AMD_PF_AND BIT31 - -#define AMD_PF_ALL (AMD_PF_NFCM | \ - AMD_PF_UMA | \ - AMD_PF_UMA_IFCM | \ - AMD_PF_IFCM | \ - AMD_PF_IOMMU | \ - AMD_PF_SINGLE_LINK | \ - AMD_PF_MULTI_LINK | \ - AMD_PF_SINGLE_CORE | \ - AMD_PF_DUAL_CORE | \ - AMD_PF_MULTI_CORE) -// Do not include AMD_PF_AND in AMD_PF_ALL ! - -/** - * The current platform features. - * - * Keep this in sync with defines above that are used in the initializers! - * - * The comments with the bit number are useful for the computing the reserved member size, but - * do not write code that assumes you know what bit number one of these members is. - * - * These platform features are standard for all logical families and models. - */ -typedef struct { - UINT32 PlatformNfcm:1; ///< BIT_0 Normal Flow Control Mode. - UINT32 PlatformUma:1; ///< BIT_1 UMA (Display Refresh) Flow Control. - UINT32 PlatformUmaIfcm:1; ///< BIT_2 UMA using Isochronous Flow Control. - UINT32 PlatformIfcm:1; ///< BIT_3 Isochronous Flow Control Mode (not UMA). - UINT32 PlatformIommu:1; ///< BIT_4 IOMMU (a special case Isochronous mode). - UINT32 PlatformSingleLink:1; ///< BIT_5 The processor is in a package which implements only a single HT Link. - UINT32 PlatformMultiLink:1; ///< BIT_6 The processor is in a package which implements more than one HT Link. - UINT32 PlatformSingleCore:1; ///< BIT_7 Single Core processor, for legacy entries. - UINT32 PlatformDualCore:1; ///< BIT_8 Dual Core processor, for legacy entries. - UINT32 PlatformMultiCore:1; ///< BIT_9 More than dual Core processor, for legacy entries. - UINT32 :(30 - 9); ///< The possibilities are (not quite) endless. - UINT32 AndPlatformFeats:1; ///< BIT_31 -} PLATFORM_FEATURES; - -/** - * Platform Features - */ -typedef union { - UINT32 PlatformValue; ///< Describe Platform Features in UINT32. - ///< This one goes first, because then initializers use it automatically for the union. - PLATFORM_FEATURES PlatformFeatures; ///< Describe Platform Features in structure -} PLATFORM_FEATS; - -// Sublink Types are defined so they can match each attribute against either -// sublink zero or one. The table entry must contain the correct matching -// values based on the register. This is available in the BKDG, for each register -// which sublink it controls. If the register is independent of sublink, OR values -// together or use HT_LINKTYPE_ALL to match if either sublink matches (ex. E0 - E5). -// Sublink 0 types, bits 0 thru 14 -#define HTPHY_LINKTYPE_SL0_HT3 BIT0 -#define HTPHY_LINKTYPE_SL0_HT1 BIT1 -#define HTPHY_LINKTYPE_SL0_COHERENT BIT2 -#define HTPHY_LINKTYPE_SL0_NONCOHERENT BIT3 -#define HTPHY_LINKTYPE_SL0_LINK0 BIT4 -#define HTPHY_LINKTYPE_SL0_LINK1 BIT5 -#define HTPHY_LINKTYPE_SL0_LINK2 BIT6 -#define HTPHY_LINKTYPE_SL0_LINK3 BIT7 -#define HTPHY_LINKTYPE_SL0_INTERNAL BIT8 -#define HTPHY_LINKTYPE_SL0_EXTERNAL BIT9 -#define HTPHY_LINKTYPE_SL0_AND BIT15 - -// SubLink 1 types, bits 16 thru 30 -#define HTPHY_LINKTYPE_SL1_HT3 BIT16 -#define HTPHY_LINKTYPE_SL1_HT1 BIT17 -#define HTPHY_LINKTYPE_SL1_COHERENT BIT18 -#define HTPHY_LINKTYPE_SL1_NONCOHERENT BIT19 -#define HTPHY_LINKTYPE_SL1_LINK4 BIT20 -#define HTPHY_LINKTYPE_SL1_LINK5 BIT21 -#define HTPHY_LINKTYPE_SL1_LINK6 BIT22 -#define HTPHY_LINKTYPE_SL1_LINK7 BIT23 -#define HTPHY_LINKTYPE_SL1_INTERNAL BIT24 -#define HTPHY_LINKTYPE_SL1_EXTERNAL BIT25 -#define HTPHY_LINKTYPE_SL1_AND BIT31 - -#define HTPHY_LINKTYPE_SL0_ALL (HTPHY_LINKTYPE_SL0_HT3 | \ - HTPHY_LINKTYPE_SL0_HT1 | \ - HTPHY_LINKTYPE_SL0_COHERENT | \ - HTPHY_LINKTYPE_SL0_NONCOHERENT | \ - HTPHY_LINKTYPE_SL0_LINK0 | \ - HTPHY_LINKTYPE_SL0_LINK1 | \ - HTPHY_LINKTYPE_SL0_LINK2 | \ - HTPHY_LINKTYPE_SL0_LINK3 | \ - HTPHY_LINKTYPE_SL0_INTERNAL | \ - HTPHY_LINKTYPE_SL0_EXTERNAL) -#define HTPHY_LINKTYPE_SL1_ALL (HTPHY_LINKTYPE_SL1_HT3 | \ - HTPHY_LINKTYPE_SL1_HT1 | \ - HTPHY_LINKTYPE_SL1_COHERENT | \ - HTPHY_LINKTYPE_SL1_NONCOHERENT | \ - HTPHY_LINKTYPE_SL1_LINK4 | \ - HTPHY_LINKTYPE_SL1_LINK5 | \ - HTPHY_LINKTYPE_SL1_LINK6 | \ - HTPHY_LINKTYPE_SL1_LINK7 | \ - HTPHY_LINKTYPE_SL1_INTERNAL | \ - HTPHY_LINKTYPE_SL1_EXTERNAL) -#define HTPHY_LINKTYPE_ALL (HTPHY_LINKTYPE_SL0_ALL | HTPHY_LINKTYPE_SL1_ALL) - -#define HTPHY_REGISTER_MAX 0x0000FFFFul -/** - * HT PHY Link Features - */ -typedef struct { - UINT32 HtPhySL0Ht3:1; ///< Ht Phy Sub-link 0 Ht3 - UINT32 HtPhySL0Ht1:1; ///< Ht Phy Sub-link 0 Ht1 - UINT32 HtPhySL0Coh:1; ///< Ht Phy Sub-link 0 Coherent - UINT32 HtPhySL0NonCoh:1; ///< Ht Phy Sub-link 0 NonCoherent - UINT32 HtPhySL0Link0:1; ///< Ht Phy Sub-link 0 specifically for node link 0. - UINT32 HtPhySL0Link1:1; ///< Ht Phy Sub-link 0 specifically for node link 1. - UINT32 HtPhySL0Link2:1; ///< Ht Phy Sub-link 0 specifically for node link 2. - UINT32 HtPhySL0Link3:1; ///< Ht Phy Sub-link 0 specifically for node link 3. - UINT32 HtPhySL0Internal:1; ///< Ht Phy Sub-link 0 is internal link. Intended for IDS support. - UINT32 HtPhySL0External:1; ///< Ht Phy Sub-link 0 is external link. Intended for IDS support. - UINT32 :(14 - 9); ///< Ht Phy Sub-link 0 Pad - UINT32 HtPhySL0And:1; ///< Ht Phy feature match should match all selected features, for sub-link 0. - UINT32 HtPhySL1Ht3:1; ///< Ht Phy Sub-link 1 Ht3 - UINT32 HtPhySL1Ht1:1; ///< Ht Phy Sub-link 1 Ht1 - UINT32 HtPhySL1Coh:1; ///< Ht Phy Sub-link 1 Coherent - UINT32 HtPhySL1NonCoh:1; ///< Ht Phy Sub-link 1 NonCoherent - UINT32 HtPhySL1Link4:1; ///< Ht Phy Sub-link 1 specifically for node link 4. - UINT32 HtPhySL1Link5:1; ///< Ht Phy Sub-link 1 specifically for node link 5. - UINT32 HtPhySL1Link6:1; ///< Ht Phy Sub-link 1 specifically for node link 6. - UINT32 HtPhySL1Link7:1; ///< Ht Phy Sub-link 1 specifically for node link 7. - UINT32 HtPhySL1Internal:1; ///< Ht Phy Sub-link 1 is internal link. Intended for IDS support. - UINT32 HtPhySL1External:1; ///< Ht Phy Sub-link 1 is external link. Intended for IDS support. - UINT32 :(30 - 25); ///< Ht Phy Sub-link 1 Pad - UINT32 HtPhySL1And:1; ///< Ht Phy feature match should match all selected features, for sub-link 1. -} HT_PHY_LINK_FEATURES; - -/** - * Ht Phy Link Features - */ -typedef union { - UINT32 HtPhyLinkValue; ///< Describe HY Phy Features in UINT32. - ///< This one goes first, because then initializers use it automatically for the union. - HT_PHY_LINK_FEATURES HtPhyLinkFeatures; ///< Describe HT Phy Features in structure. -} HT_PHY_LINK_FEATS; - -// DB Level for initializing Deemphasis -// This must be in sync with DEEMPHASIS_FEATURES and PLATFORM_DEEMPHASIS_LEVEL (agesa.h) -#define DEEMPHASIS_LEVEL_NONE BIT0 -#define DEEMPHASIS_LEVEL__3 BIT1 -#define DEEMPHASIS_LEVEL__6 BIT2 -#define DEEMPHASIS_LEVEL__8 BIT3 -#define DEEMPHASIS_LEVEL__11 BIT4 -#define DEEMPHASIS_LEVEL__11_8 BIT5 -#define DCV_LEVEL_NONE BIT16 -#define DCV_LEVEL__2 BIT17 -#define DCV_LEVEL__3 BIT18 -#define DCV_LEVEL__5 BIT19 -#define DCV_LEVEL__6 BIT20 -#define DCV_LEVEL__7 BIT21 -#define DCV_LEVEL__8 BIT22 -#define DCV_LEVEL__9 BIT23 -#define DCV_LEVEL__11 BIT24 -// Note that an "AND" feature doesn't make any sense, levels are mutually exclusive. - -// An error check value. -#define DEEMPHASIS_LEVELS_ALL (DEEMPHASIS_LEVEL_NONE | \ - DEEMPHASIS_LEVEL__3 | \ - DEEMPHASIS_LEVEL__6 | \ - DEEMPHASIS_LEVEL__8 | \ - DEEMPHASIS_LEVEL__11 | \ - DEEMPHASIS_LEVEL__11_8) - -#define DCV_LEVELS_ALL (DCV_LEVEL_NONE | \ - DCV_LEVEL__2 | \ - DCV_LEVEL__3 | \ - DCV_LEVEL__5 | \ - DCV_LEVEL__6 | \ - DCV_LEVEL__7 | \ - DCV_LEVEL__8 | \ - DCV_LEVEL__9 | \ - DCV_LEVEL__11) - -#define VALID_DEEMPHASIS_LEVELS (DEEMPHASIS_LEVELS_ALL | DCV_LEVELS_ALL) - -/** - * Deemphasis Ht Phy Link Deemphasis. - * - * This must be in sync with defines above and ::PLATFORM_DEEMPHASIS_LEVEL (agesa.h) - */ -typedef struct { - UINT32 DeemphasisLevelNone:1; ///< The deemphasis level None. - UINT32 DeemphasisLevelMinus3:1; ///< The deemphasis level minus 3 db. - UINT32 DeemphasisLevelMinus6:1; ///< The deemphasis level minus 6 db. - UINT32 DeemphasisLevelMinus8:1; ///< The deemphasis level minus 8 db. - UINT32 DeemphasisLevelMinus11:1; ///< The deemphasis level minus 11 db. - UINT32 DeemphasisLevelMinus11w8:1; ///< The deemphasis level minus 11 db, minus 8 precursor. - UINT32 :(15 - 5); ///< reserved. - UINT32 DcvLevelNone:1; ///< The level for DCV None. - UINT32 DcvLevelMinus2:1; ///< The level for DCV minus 2 db. - UINT32 DcvLevelMinus3:1; ///< The level for DCV minus 3 db. - UINT32 DcvLevelMinus5:1; ///< The level for DCV minus 5 db. - UINT32 DcvLevelMinus6:1; ///< The level for DCV minus 6 db. - UINT32 DcvLevelMinus7:1; ///< The level for DCV minus 7 db. - UINT32 DcvLevelMinus8:1; ///< The level for DCV minus 8 db. - UINT32 DcvLevelMinus9:1; ///< The level for DCV minus 9 db. - UINT32 DcvLevelMinus11:1; ///< The level for DCV minus 11 db. - UINT32 :(15 - 8); ///< reserved. -} DEEMPHASIS_FEATURES; - -/** - * Deemphasis Ht Phy Link Features. - */ -typedef union { - UINT32 DeemphasisValues; ///< Initialize HT Deemphasis in UINT32. - DEEMPHASIS_FEATURES DeemphasisLevels; ///< HT Deemphasis levels. -} DEEMPHASIS_FEATS; - -// Initializer bit patterns for PERFORMANCE_PROFILE_FEATS. -#define PERFORMANCE_REFRESH_REQUEST_32B BIT0 -#define PERFORMANCE_PROBEFILTER BIT1 -#define PERFORMANCE_L3_CACHE BIT2 -#define PERFORMANCE_NO_L3_CACHE BIT3 -#define PERFORMANCE_MCT_ISOC_VARIABLE BIT4 -#define PERFORMANCE_IS_WARM_RESET BIT5 -#define PERFORMANCE_VRM_HIGH_SPEED_ENABLE BIT6 -#define PERFORMANCE_NB_PSTATES_ENABLE BIT7 -#define PERFORMANCE_AND BIT31 - -#define PERFORMANCE_PROFILE_ALL (PERFORMANCE_REFRESH_REQUEST_32B | \ - PERFORMANCE_PROBEFILTER | \ - PERFORMANCE_L3_CACHE | \ - PERFORMANCE_NO_L3_CACHE | \ - PERFORMANCE_MCT_ISOC_VARIABLE | \ - PERFORMANCE_IS_WARM_RESET | \ - PERFORMANCE_VRM_HIGH_SPEED_ENABLE | \ - PERFORMANCE_NB_PSTATES_ENABLE) - -/** - * Performance Profile specific Type Features. - * - * Register settings for the different control flow modes can have additional dependencies - */ -typedef struct { - UINT32 RefreshRequest32Byte:1; ///< BIT_0. Display Refresh Requests use 32 bytes (32BE). - UINT32 ProbeFilter:1; ///< BIT_1 Probe Filter will be enabled. - UINT32 L3Cache:1; ///< BIT_2 L3 Cache is present. - UINT32 NoL3Cache:1; ///< BIT_3 L3 Cache is NOT present. - UINT32 MctIsocVariable:1; ///< BIT_4 Mct Isoc Read Priority set to variable. - UINT32 IsWarmReset:1; ///< BIT_5 This boot is on a warm reset, cold reset pass is already completed. - UINT32 VrmHighSpeed:1; ///< BIT_6 Select high speed VRM. - UINT32 NbPstates:1; ///< BIT_7 Northbridge PStates are enabled - UINT32 :(30 - 7); ///< available for future expansion. - UINT32 AndPerformanceFeats:1; ///< BIT_31. AND other selected features. -} PERFORMANCE_PROFILE_FEATURES; - -/** - * Performance Profile features. - */ -typedef union { - UINT32 PerformanceProfileValue; ///< Initializer value. - PERFORMANCE_PROFILE_FEATURES PerformanceProfileFeatures; ///< The performance profile features. -} PERFORMANCE_PROFILE_FEATS; - -/** - * Package Type Features - * - */ -typedef struct { - UINT32 PkgType0:1; ///< Package Type 0 - UINT32 PkgType1:1; ///< Package Type 1 - UINT32 PkgType2:1; ///< Package Type 2 - UINT32 PkgType3:1; ///< Package Type 3 - UINT32 PkgType4:1; ///< Package Type 4 - UINT32 PkgType5:1; ///< Package Type 5 - UINT32 PkgType6:1; ///< Package Type 6 - UINT32 PkgType7:1; ///< Package Type 7 - UINT32 PkgType8:1; ///< Package Type 8 - UINT32 PkgType9:1; ///< Package Type 9 - UINT32 PkgType10:1; ///< Package Type 10 - UINT32 PkgType11:1; ///< Package Type 11 - UINT32 PkgType12:1; ///< Package Type 12 - UINT32 PkgType13:1; ///< Package Type 13 - UINT32 PkgType14:1; ///< Package Type 14 - UINT32 PkgType15:1; ///< Package Type 15 - UINT32 Reserved:15; ///< Package Type Reserved - UINT32 ReservedAndFeats:1; ///< BIT_31. AND other selected features. Always zero here. -} PACKAGE_TYPE_FEATURES; - -// Initializer Values for Package Type -#define PACKAGE_TYPE_ALL 0XFFFF ///< Package Type apply all packages - -// Initializer Values for Ht Host Pci Config Registers -#define HT_HOST_FEAT_COHERENT BIT0 -#define HT_HOST_FEAT_NONCOHERENT BIT1 -#define HT_HOST_FEAT_GANGED BIT2 -#define HT_HOST_FEAT_UNGANGED BIT3 -#define HT_HOST_FEAT_HT3 BIT4 -#define HT_HOST_FEAT_HT1 BIT5 -#define HT_HOST_AND BIT31 - -#define HT_HOST_FEATURES_ALL (HT_HOST_FEAT_COHERENT | \ - HT_HOST_FEAT_NONCOHERENT | \ - HT_HOST_FEAT_GANGED | \ - HT_HOST_FEAT_UNGANGED | \ - HT_HOST_FEAT_HT3 | \ - HT_HOST_FEAT_HT1) - -/** - * HT Host PCI register features. - * - * Links which are not connected do not match any of these features. - */ -typedef struct { - UINT32 Coherent:1; ///< BIT_0 Apply to links with a coherent connection. - UINT32 NonCoherent:1; ///< BIT_1 Apply to links with a non-coherent connection. - UINT32 Ganged:1; ///< BIT_2 Apply to links with a ganged connection. - UINT32 UnGanged:1; ///< BIT_3 Apply to links with a unganged connection. - UINT32 Ht3:1; ///< BIT_4 Apply to links with HT3 frequency (> 1000 MHz) - UINT32 Ht1:1; ///< BIT_5 Apply to links with HT1 frequency (< 1200 MHz) - UINT32 :(30 - 5); ///< Future expansion. - UINT32 AndHtHostFeats:1; ///< BIT_31. AND other selected features. -} HT_HOST_FEATURES; - -/** - * HT Host features for table data. - */ -typedef union { - UINT32 HtHostValue; ///< Initializer value. - HT_HOST_FEATURES HtHostFeatures; ///< The HT Host Features. -} HT_HOST_FEATS; - -// Core Range Initializer values. -#define COUNT_RANGE_LOW 0ul -#define COUNT_RANGE_HIGH 0xFFul - -// A count range matching none is often useful as the second range, matching will then be -// based on the first range. A count range all is provided as a first range for default settings. -#define COUNT_RANGE_NONE ((((COUNT_RANGE_HIGH) << 8) | (COUNT_RANGE_HIGH)) << 16) -#define COUNT_RANGE_ALL (((COUNT_RANGE_HIGH) << 8) | (COUNT_RANGE_LOW)) -#define IGNORE_FREQ_0 (((COUNT_RANGE_HIGH) << 8) | (COUNT_RANGE_HIGH)) -#define IGNORE_PROCESSOR_0 (((COUNT_RANGE_HIGH) << 8) | (COUNT_RANGE_HIGH)) - -#define CORE_RANGE_0(min, max) ((((UINT32)(max)) << 8) | (UINT32)(min)) -#define CORE_RANGE_1(min, max) (((((UINT32)(max)) << 8) | (UINT32)(min)) << 16) -#define PROCESSOR_RANGE_0(min, max) ((((UINT32)(max)) << 8) | (UINT32)(min)) -#define PROCESSOR_RANGE_1(min, max) (((((UINT32)(max)) << 8) | (UINT32)(min)) << 16) -#define DEGREE_RANGE_0(min, max) ((((UINT32)(max)) << 8) | (UINT32)(min)) -#define DEGREE_RANGE_1(min, max) (((((UINT32)(max)) << 8) | (UINT32)(min)) << 16) -#define FREQ_RANGE_0(min, max) ((((UINT32)(max)) << 8) | (UINT32)(min)) -#define FREQ_RANGE_1(min, max) (((((UINT32)(max)) << 8) | (UINT32)(min)) << 16) -#define COMPUTE_UNIT_RANGE_0(min, max) ((((UINT32)(max)) << 8) | (UINT32)(min)) -#define COMPUTE_UNIT_RANGE_1(min, max) (((((UINT32)(max)) << 8) | (UINT32)(min)) << 16) - -/** - * Count Range Feature, two count ranges for core counts, processor counts, or node counts. - */ -typedef struct { - UINT32 Range0Min:8; ///< The minimum of the first count range. - UINT32 Range0Max:8; ///< The maximum of the first count range. - UINT32 Range1Min:8; ///< The minimum of the second count range. - UINT32 Range1Max:8; ///< The maximum of the second count range. -} COUNT_RANGE_FEATURE; - -/** - * Core Count Ranges for table data. - * - * Provide a pair of core count ranges. If the actual core count is included in either range (OR), - * the feature should be considered a match. - */ -typedef union { - UINT32 CoreRangeValue; ///< Initializer value. - COUNT_RANGE_FEATURE CoreRanges; ///< The Core Counts. -} CORE_COUNT_RANGES; - -/** - * Processor count ranges for table data. - * - * Provide a pair of processor count ranges. If the actual counts are included in either range (OR), - * the feature should be considered a match. - */ -typedef union { - UINT32 ProcessorCountRangeValue; ///< Initializer value. - COUNT_RANGE_FEATURE ProcessorCountRanges; ///< The Processor and Node Counts. -} PROCESSOR_COUNTS; - -/** - * Compute unit count ranges for table data. - * - * Provide a pair of compute unit count ranges. If the actual counts are included in either ranges (OR), - * the feature should be considered a match. - */ -typedef union { - UINT32 ComputeUnitRangeValue; ///< Initializer value. - COUNT_RANGE_FEATURE ComputeUnitRanges; ///< The Processor and Node Counts. -} COMPUTE_UNIT_COUNTS; - -/** - * Connectivity count ranges for table data. - * - * Provide a processor count range and a system degree range. The degree of a system is - * the maximum degree of any node. The degree of a node is the number of nodes to which - * it is directly connected (not considering width or redundant links). If both the actual - * counts are included in each range (AND), the feature should be considered a match. - */ -typedef union { - UINT32 ConnectivityCountRangeValue; ///< Initializer value. - COUNT_RANGE_FEATURE ConnectivityCountRanges; ///< The Processor and Degree Counts. -} CONNECTIVITY_COUNT; - -/** - * HT Frequency Count Range. - * - * Provide a pair of Frequency count ranges, with the frequency encoded as an HT Frequency value - * (such as would be programmed into the HT Host Link Frequency register). By converting a NB freq, - * the same count can be applied for it. If the actual value is included in either range - */ -typedef union { - UINT32 HtFreqCountRangeValue; ///< Initializer value. - COUNT_RANGE_FEATURE HtFreqCountRanges; ///< The HT Freq counts. -} HT_FREQ_COUNTS; - -/*------------------------------------------------------------------------------------------*/ -/* - * The specific data for each table entry. - */ -/*------------------------------------------------------------------------------------------*/ - -/** - * Make an extra type so we can use compilers that don't support designated initializers. - * - * All the entry type unions are no more than 5 UINT32's in size. For entry types which are a struct of UINT32's, - * this type can be used so that initializers can be declared TABLE_ENTRY_FIELDS, instead of a special non-union type. - * A non-union type then has to be cast back to TABLE_ENTRY_FIELDS in order to process the table, and you can't mix - * entry types with non-union initializers in the same table with any other type. - * - * If the entry type contains anything but UINT32's, then it must have a non-union initializer type for creating the - * actual tables. For example, MSR entry has UINT64 and workaround entry has a function pointer. - */ -typedef UINT32 GENERIC_TYPE_ENTRY_INITIALIZER[MAX_ENTRY_TYPE_ITEMS32]; - -/** - * Table Entry Data for MSR Registers. - * - * Apply data to register after mask, for MSRs. - */ -typedef struct { - UINT32 Address; ///< MSR address - UINT64 Data; ///< Data to set in the MSR - UINT64 Mask; ///< Mask to be applied to the MSR. Set every bit of all updated fields. -} MSR_TYPE_ENTRY_DATA; - -/** - * Table Entry Data for PCI Registers. - * - * Apply data to register after mask, for PCI Config registers. - */ -typedef struct { - PCI_ADDR Address; ///< Address should contain Function, Offset only. It will apply to all CPUs - UINT32 Data; ///< Data to be written into PCI device - UINT32 Mask; ///< Mask to be used before data write. Set every bit of all updated fields. -} PCI_TYPE_ENTRY_DATA; - -/** - * Table Entry Data for HT Phy Registers. - * - * Apply data to register after mask, for HT Phy registers, repeated for all active links. - */ -typedef struct { - HT_PHY_LINK_FEATS TypeFeats; ///< HT Phy Link Features - UINT32 Address; ///< Address of Ht Phy Register - UINT32 Data; ///< Data to be written into PCI device - UINT32 Mask; ///< Mask to be used before data write. Set every bit of all updated fields. -} HT_PHY_TYPE_ENTRY_DATA; - -/** - * Table Entry Data for HT Phy Register Ranges. - * - * Apply data to register after mask, for a range of HT Phy registers, repeated for all active links. - */ -typedef struct { - HT_PHY_LINK_FEATS TypeFeats; ///< HT Phy Link Features - UINT32 LowAddress; ///< Low address of Ht Phy Register range. - UINT32 HighAddress; ///< High address of register range. - UINT32 Data; ///< Data to be written into PCI device. - UINT32 Mask; ///< Mask to be used before data write. Set every bit of all updated fields. -} HT_PHY_RANGE_TYPE_ENTRY_DATA; - -/** - * Table Entry Data for HT Phy Deemphasis Registers. - * - * Apply data to register after mask, for HT Phy registers, repeated for all active links. - */ -typedef struct { - DEEMPHASIS_FEATS Levels; ///< The DCV and Deemphasis levels to match - HT_PHY_TYPE_ENTRY_DATA HtPhyEntry; ///< The HT Phy Entry to set the deemphasis values -} DEEMPHASIS_HT_PHY_TYPE_ENTRY_DATA; - -/** - * Table Entry Date for HT Phy Frequency Count Register updates. - * - * Compare the NB freq to a range, the HT freq to a range, the link features. - * Apply data to register after mask, if all three matched. - */ -typedef struct { - HT_FREQ_COUNTS HtFreqCounts; ///< Specify the HT Frequency range. - HT_FREQ_COUNTS NbFreqCounts; ///< Specify the NB Frequency range. - HT_PHY_TYPE_ENTRY_DATA HtPhyEntry; ///< The HT Phy register update to perform. -} HT_PHY_FREQ_TYPE_ENTRY_DATA; - -/** - * Table Entry Data for Profile Fixup Registers. - * - * If TypeFeats matches current config, apply data to register after mask for PCI Config registers. - */ -typedef struct { - PERFORMANCE_PROFILE_FEATS TypeFeats; ///< Profile Fixup Features. - PCI_TYPE_ENTRY_DATA PciEntry; ///< The PCI Register entry data. -} PROFILE_FIXUP_TYPE_ENTRY_DATA; - -/** - * A variation of PCI register for the HT Host registers. - * - * A setting to the HT Host buffer counts needs to be made to all the registers for - * all the links. There are also link specific criteria to check. - */ -typedef struct { - HT_HOST_FEATS TypeFeats; ///< Link Features. - PCI_ADDR Address; ///< Address of PCI Register to Fixed Up. - UINT32 Data; ///< Data to be written into PCI device - UINT32 Mask; ///< Mask to be used before data write. Set every bit of all updated fields. -} HT_HOST_PCI_TYPE_ENTRY_DATA; - -/** - * A variation of PCI register for the HT Host performance registers. - * - * A setting to the HT Host buffer counts needs to be made to all the registers for - * all the links. There are also link specific criteria to check. - */ -typedef struct { - PERFORMANCE_PROFILE_FEATS PerformanceFeats; ///< Performance Profile features. - HT_HOST_PCI_TYPE_ENTRY_DATA HtHostEntry; ///< Link Features. -} HT_HOST_PERFORMANCE_PCI_TYPE_ENTRY_DATA; - -/** - * A variation of HT Host PCI register for the Link Token registers. - * - * Use Link Features, Performance Fixup features, and processor counts to match entries. - * Link Features are iterated through the connected links. All the matching Link Token count - * registers are updated. - */ -typedef struct { - CONNECTIVITY_COUNT ConnectivityCount; ///< Specify Processor count and Degree count range. - PERFORMANCE_PROFILE_FEATS PerformanceFeats; ///< Performance Profile features. - HT_HOST_FEATS LinkFeats; ///< Link Features. - PCI_ADDR Address; ///< Address of PCI Register to Fixed Up. - UINT32 Data; ///< Data to be written into PCI device - UINT32 Mask; ///< Mask to be used before data write. Set every bit of all updated fields. -} HT_TOKEN_PCI_REGISTER; - -/** - * Core Count dependent PCI registers. - * - */ -typedef struct { - PERFORMANCE_PROFILE_FEATS TypeFeats; ///< Profile Fixup Features. - CORE_COUNT_RANGES CoreCounts; ///< Specify up to two core count ranges to match. - PCI_TYPE_ENTRY_DATA PciEntry; ///< The PCI Register entry data. -} CORE_COUNTS_PCI_TYPE_ENTRY_DATA; - -/** - * Processor Count dependent PCI registers. - * - */ -typedef struct { - PERFORMANCE_PROFILE_FEATS TypeFeats; ///< Profile Fixup Features. - PROCESSOR_COUNTS ProcessorCounts; ///< Specify a processor count range. - PCI_TYPE_ENTRY_DATA PciEntry; ///< The PCI Register entry data. -} PROCESSOR_COUNTS_PCI_TYPE_ENTRY_DATA; - -/** - * Compute Unit Count dependent PCI registers. - * - */ -typedef struct { - PERFORMANCE_PROFILE_FEATS TypeFeats; ///< Profile Fixup Features. - COMPUTE_UNIT_COUNTS ComputeUnitCounts; ///< Specify a compute unit count range. - PCI_TYPE_ENTRY_DATA PciEntry; ///< The PCI Register entry data. -} COMPUTE_UNIT_COUNTS_PCI_TYPE_ENTRY_DATA; - -/** - * Compute Unit Count dependent MSR registers. - * - */ -typedef struct { - COMPUTE_UNIT_COUNTS ComputeUnitCounts; ///< Specify a compute unit count range. - MSR_TYPE_ENTRY_DATA MsrEntry; ///< The MSR Register entry data. -} COMPUTE_UNIT_COUNTS_MSR_TYPE_ENTRY_DATA; - -/** - * System connectivity dependent PCI registers. - * - * The topology specific recommended settings are based on the different connectivity of nodes - * in each configuration: the more connections, the fewer resources each connection gets. - * The connectivity criteria translate as: - * - 2 Socket, half populated == Degree 1 - * - 4 Socket, half populated == Degree 2 - * - 2 Socket, fully populated == Degree 3 - * - 4 Socket, fully populated == Degree > 3. (4 or 5 if 3P, 6 if 4P) - * - */ -typedef struct { - PERFORMANCE_PROFILE_FEATS TypeFeats; ///< Profile Fixup Features. - CONNECTIVITY_COUNT ConnectivityCount; ///< Specify a system degree range. - PCI_TYPE_ENTRY_DATA PciEntry; ///< The PCI Register entry data. -} CONNECTIVITY_COUNTS_PCI_TYPE_ENTRY_DATA; - -/** - * A Family Specific Workaround method. - * - * \@TableTypeFamSpecificInstances. - * - * When called, the entry's CPU Logical ID and Platform Features matched the current config. - * The method must implement any specific criteria checking for the workaround. - * - * See if you can use the other entries or make an entry specifically for the fix. - * After all, the purpose of having a table entry is to @b NOT have code which - * isn't generic feature code, but is family/model specific. - * - * @param[in] Data The table data value, for example to indicate which CPU and Platform types matched. - * @param[in] StdHeader Config params for library, services. - */ -typedef VOID F_FAM_SPECIFIC_WORKAROUND ( - IN UINT32 Data, - IN AMD_CONFIG_PARAMS *StdHeader - ); -/// Reference to a method. -typedef F_FAM_SPECIFIC_WORKAROUND *PF_FAM_SPECIFIC_WORKAROUND; - -/** - * Table Entry Data for Family Specific Workarounds. - * - * See if you can use the other entries or make an entry specifically for the fix. - * After all, the purpose of having a table entry is to @b NOT have code which - * isn't generic feature code, but is family/model specific. - * - * Call DoAction passing Data. - */ -typedef struct { - PF_FAM_SPECIFIC_WORKAROUND DoAction; ///< A function implementing the workaround. - UINT32 Data; ///< This data is passed to DoAction(). -} FAM_SPECIFIC_WORKAROUND_TYPE_ENTRY_DATA; - -/** - * Package Type Features - * - * FamilyPackageType are various among CPU families. - * - */ -typedef union { - UINT32 PackageTypeValue; ///< Package Type - PACKAGE_TYPE_FEATURES FamilyPackageType; ///< Package Type of CPU family -} PACKAGE_TYPE_FEATS; - -/** - * HT Features dependent Global PCI registers. - * - */ -typedef struct { - HT_HOST_FEATS LinkFeats; ///< Link Features. - PACKAGE_TYPE_FEATS PackageType; ///< Package Type - PCI_TYPE_ENTRY_DATA PciEntry; ///< The PCI Register entry data. -} HT_FEATURES_PCI_TYPE_ENTRY_DATA; - -/** - * Table Entry Data for HT Phy Registers which depend on performance profile features. - * - * Match performance profile features and link features. - * Apply data to register after mask, for HT Phy registers, repeated for all active links. - */ -typedef struct { - PERFORMANCE_PROFILE_FEATS TypeFeats; ///< Profile Fixup Features. - HT_PHY_TYPE_ENTRY_DATA HtPhyEntry; ///< The HT Phy Entry to set the deemphasis values -} PROFILE_HT_PHY_TYPE_ENTRY_DATA; - -/** - * HT Link PCI registers that are not in the HT Host capability. - * - * Some HT Link registers have an instance per link, but are just sequential. Specify the base register - * in the table register address (link 0 sublink 0). - */ -typedef struct { - HT_HOST_FEATS LinkFeats; ///< Link Features. - PCI_TYPE_ENTRY_DATA PciEntry; ///< The PCI Register entry data. -} HT_LINK_PCI_TYPE_ENTRY_DATA; - -/*------------------------------------------------------------------------------------------*/ -/* - * A complete register table and table entries. - */ -/*------------------------------------------------------------------------------------------*/ - -/** - * All the available entry data types. - */ -typedef union { - GENERIC_TYPE_ENTRY_INITIALIZER InitialValues; ///< Not a valid entry type; as the first union item, - ///< it can be used with initializers. - MSR_TYPE_ENTRY_DATA MsrEntry; ///< Msr entry. - PCI_TYPE_ENTRY_DATA PciEntry; ///< PCI entry. - FAM_SPECIFIC_WORKAROUND_TYPE_ENTRY_DATA FamSpecificEntry; ///< Family Specific Workaround entry. - HT_PHY_TYPE_ENTRY_DATA HtPhyEntry; ///< HT Phy entry. - HT_PHY_RANGE_TYPE_ENTRY_DATA HtPhyRangeEntry; ///< A range of Ht Phy Registers - DEEMPHASIS_HT_PHY_TYPE_ENTRY_DATA DeemphasisEntry; ///< A HT Deemphasis level's settings. - HT_PHY_FREQ_TYPE_ENTRY_DATA HtPhyFreqEntry; ///< A frequency dependent Ht Phy Register setting. - PROFILE_FIXUP_TYPE_ENTRY_DATA FixupEntry; ///< Profile Fixup entry. - HT_HOST_PCI_TYPE_ENTRY_DATA HtHostEntry; ///< HT Host PCI entry. - HT_HOST_PERFORMANCE_PCI_TYPE_ENTRY_DATA HtHostPerfEntry; ///< HT Host Performance PCI entry - HT_TOKEN_PCI_REGISTER HtTokenEntry; ///< HT Link Token Count entry. - CORE_COUNTS_PCI_TYPE_ENTRY_DATA CoreCountEntry; ///< Core count dependent settings. - PROCESSOR_COUNTS_PCI_TYPE_ENTRY_DATA ProcCountEntry; ///< Processor count entry. - COMPUTE_UNIT_COUNTS_PCI_TYPE_ENTRY_DATA CompUnitCountEntry; ///< Compute unit count dependent entry. - CONNECTIVITY_COUNTS_PCI_TYPE_ENTRY_DATA TokenPciEntry; ///< System connectivity dependent Token register. - HT_FEATURES_PCI_TYPE_ENTRY_DATA HtFeatPciEntry; ///< HT Features PCI entry. - PROFILE_HT_PHY_TYPE_ENTRY_DATA HtPhyProfileEntry; ///< Performance dependent HT Phy register. - HT_LINK_PCI_TYPE_ENTRY_DATA HtLinkPciEntry; ///< Per Link, non HT Host, PCI registers. - COMPUTE_UNIT_COUNTS_MSR_TYPE_ENTRY_DATA CompUnitCountMsrEntry; ///< Compute unit count dependent MSR entry. -} TABLE_ENTRY_DATA; - -/** - * Register Table Entry common fields. - * - * All the various types of register table entries are subclasses of this object. - */ -typedef struct { - TABLE_ENTRY_TYPE EntryType; ///< The type of table entry this is. - CPU_LOGICAL_ID CpuRevision; ///< Common CPU Logical ID match criteria. - PLATFORM_FEATS Features; ///< Common Platform Features match criteria. - TABLE_ENTRY_DATA Entry; ///< The type dependent entry data (ex. register, data, mask). -} TABLE_ENTRY_FIELDS; - -/** - * An entire register table. - */ -typedef struct { - TABLE_CORE_SELECTOR Selector; ///< For efficiency, these cores should process this table - UINTN NumberOfEntries; ///< The number of entries in the table. - CONST TABLE_ENTRY_FIELDS *Table; ///< The table entries. -} REGISTER_TABLE; - -/*------------------------------------------------------------------------------------------*/ -/* - * Describe implementers for table entries. - */ -/*------------------------------------------------------------------------------------------*/ - -/** - * Implement the semantics of a Table Entry Type. - * - * @TableEntryTypeInstances. - * - * @param[in] CurrentEntry The type specific entry data to be implemented (that is written). - * @param[in] PlatformConfig Config handle for platform specific information - * @param[in] StdHeader Config params for library, services. - */ -typedef VOID F_DO_TABLE_ENTRY ( - IN TABLE_ENTRY_DATA *CurrentEntry, - IN PLATFORM_CONFIGURATION *PlatformConfig, - IN AMD_CONFIG_PARAMS *StdHeader - ); -/// Reference to a method -typedef F_DO_TABLE_ENTRY *PF_DO_TABLE_ENTRY; - -/** - * Describe the attributes of a Table Entry Type. - */ -typedef struct { - TABLE_ENTRY_TYPE EntryType; ///< The type of table entry this describes. - PF_DO_TABLE_ENTRY DoTableEntry; ///< Provide all semantics associated with TABLE_ENTRY_DATA -} TABLE_ENTRY_TYPE_DESCRIPTOR; - -/*------------------------------------------------------------------------------------------*/ -/* - * Non-union initializers for entry data which is not just UINT32. - */ -/*------------------------------------------------------------------------------------------*/ - -/** - * A union of data types, that can be initialized with MSR data. - * - * This ensures the entry data is the same size as TABLE_ENTRY_DATA. - */ -typedef union { - MSR_TYPE_ENTRY_DATA MsrInitializer; ///< The data in the table initializer is assigned to this member. - TABLE_ENTRY_DATA Reserved; ///< Make sure the size is the same as the real union. -} MSR_DATA_INITIALIZER; - -/** - * A type suitable for an initializer for MSR Table entries. - */ -typedef struct { - TABLE_ENTRY_TYPE Type; ///< The type of table entry this is. - CPU_LOGICAL_ID CpuRevision; ///< Common CPU Logical ID match criteria. - PLATFORM_FEATS Features; ///< Common Platform Features match criteria. - MSR_DATA_INITIALIZER EntryData; ///< The special union which accepts msr data initializer. -} MSR_TYPE_ENTRY_INITIALIZER; - -/** - * A union of data types, that can be initialized with MSR CU data. - * - * This ensures the entry data is the same size as TABLE_ENTRY_DATA. - */ -typedef union { - COMPUTE_UNIT_COUNTS_MSR_TYPE_ENTRY_DATA MsrInitializer; ///< The data in the table initializer is assigned to this member. - TABLE_ENTRY_DATA Reserved; ///< Make sure the size is the same as the real union. -} MSR_CU_DATA_INITIALIZER; - -/** - * A type suitable for an initializer for MSR CU count Table entries. - */ -typedef struct { - TABLE_ENTRY_TYPE Type; ///< The type of table entry this is. - CPU_LOGICAL_ID CpuRevision; ///< Common CPU Logical ID match criteria. - PLATFORM_FEATS Features; ///< Common Platform Features match criteria. - MSR_CU_DATA_INITIALIZER EntryData; ///< The special union which accepts msr data initializer. -} MSR_CU_TYPE_ENTRY_INITIALIZER; - -/** - * A union of data types, that can be initialized with Family Specific Workaround data. - * - * This ensures the entry data is the same size as TABLE_ENTRY_DATA. - */ -typedef union { - FAM_SPECIFIC_WORKAROUND_TYPE_ENTRY_DATA FamSpecificInitializer; ///< The data in the table initializer is assigned to this member. - TABLE_ENTRY_DATA Reserved; ///< Make sure the size is the same as the real union. -} FAM_SPECIFIC_WORKAROUND_DATA_INITIALIZER; - -/** - * A type suitable for an initializer for Family Specific Workaround Table entries. - */ -typedef struct { - TABLE_ENTRY_TYPE Type; ///< The type of table entry this is. - CPU_LOGICAL_ID CpuRevision; ///< Common CPU Logical ID match criteria. - PLATFORM_FEATS Features; ///< Common Platform Features match criteria. - FAM_SPECIFIC_WORKAROUND_DATA_INITIALIZER EntryData; ///< Special union accepts family specific workaround data initializer. -} FAM_SPECIFIC_WORKAROUND_TYPE_ENTRY_INITIALIZER; - -/*------------------------------------------------------------------------------------------*/ -/* - * Table related function prototypes (many are instance of F_DO_TABLE_ENTRY method). - */ -/*------------------------------------------------------------------------------------------*/ - -/** - * Set the registers for this core based on entries in a list of Register Tables. - */ -VOID SetRegistersFromTables ( - IN PLATFORM_CONFIGURATION *PlatformConfig, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -/** - * Find the features of the running platform. - */ -VOID -GetPlatformFeatures ( - OUT PLATFORM_FEATS *Features, - IN PLATFORM_CONFIGURATION *PlatformConfig, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -/** - * Checks register table entry type specific criteria to the platform. - */ -BOOLEAN -DoesEntryTypeSpecificInfoMatch ( - IN UINT32 PlatformTypeSpecificFeatures, - IN UINT32 EntryTypeFeatures - ); - -/** - * Perform the MSR Register Entry. - */ -VOID -SetRegisterForMsrEntry ( - IN TABLE_ENTRY_DATA *Entry, - IN PLATFORM_CONFIGURATION *PlatformConfig, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -/** - * Perform the PCI Register Entry. - */ -VOID -SetRegisterForPciEntry ( - IN TABLE_ENTRY_DATA *Entry, - IN PLATFORM_CONFIGURATION *PlatformConfig, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -/** - * Perform the Performance Profile PCI Register Entry. - */ -VOID -SetRegisterForPerformanceProfileEntry ( - IN TABLE_ENTRY_DATA *Entry, - IN PLATFORM_CONFIGURATION *PlatformConfig, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -/** - * Perform the HT Host PCI Register Entry. - */ -VOID -SetRegisterForHtHostEntry ( - IN TABLE_ENTRY_DATA *Entry, - IN PLATFORM_CONFIGURATION *PlatformConfig, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -/** - * Perform the HT Host Performance PCI Register Entry. - */ -VOID -SetRegisterForHtHostPerfEntry ( - IN TABLE_ENTRY_DATA *Entry, - IN PLATFORM_CONFIGURATION *PlatformConfig, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -/** - * Set the HT Link Token Count registers. - */ -VOID -SetRegisterForHtLinkTokenEntry ( - IN TABLE_ENTRY_DATA *Entry, - IN PLATFORM_CONFIGURATION *PlatformConfig, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -/** - * Perform the Core Counts Performance PCI Register Entry. - */ -VOID -SetRegisterForCoreCountsPerformanceEntry ( - IN TABLE_ENTRY_DATA *Entry, - IN PLATFORM_CONFIGURATION *PlatformConfig, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -/** - * Perform the Processor Counts PCI Register Entry. - */ -VOID -SetRegisterForProcessorCountsEntry ( - IN TABLE_ENTRY_DATA *Entry, - IN PLATFORM_CONFIGURATION *PlatformConfig, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -/** - * Perform the Compute Unit Counts PCI Register Entry. - */ -VOID -SetRegisterForComputeUnitCountsEntry ( - IN TABLE_ENTRY_DATA *Entry, - IN PLATFORM_CONFIGURATION *PlatformConfig, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -/** - * Perform the Compute Unit Counts MSR Register Entry. - */ -VOID -SetMsrForComputeUnitCountsEntry ( - IN TABLE_ENTRY_DATA *Entry, - IN PLATFORM_CONFIGURATION *PlatformConfig, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -/** - * Perform the Family Specific Workaround Register Entry. - */ -VOID -SetRegisterForFamSpecificWorkaroundEntry ( - IN TABLE_ENTRY_DATA *Entry, - IN PLATFORM_CONFIGURATION *PlatformConfig, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -/** - * Program HT Phy PCI registers. - */ -VOID -SetRegisterForHtPhyEntry ( - IN TABLE_ENTRY_DATA *Entry, - IN PLATFORM_CONFIGURATION *PlatformConfig, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -/** - * Program a range of HT Phy PCI registers. - */ -VOID -SetRegisterForHtPhyRangeEntry ( - IN TABLE_ENTRY_DATA *Entry, - IN PLATFORM_CONFIGURATION *PlatformConfig, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -/** - * Program Deemphasis registers, for the platform specified levels. - */ -VOID -SetRegisterForDeemphasisEntry ( - IN TABLE_ENTRY_DATA *Entry, - IN PLATFORM_CONFIGURATION *PlatformConfig, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -/** - * Program HT Phy PCI registers which have complex frequency dependencies. - */ -VOID -SetRegisterForHtPhyFreqEntry ( - IN TABLE_ENTRY_DATA *Entry, - IN PLATFORM_CONFIGURATION *PlatformConfig, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -/** - * Perform the Processor Token Counts PCI Register Entry. - */ -VOID -SetRegisterForTokenPciEntry ( - IN TABLE_ENTRY_DATA *Entry, - IN PLATFORM_CONFIGURATION *PlatformConfig, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -/** - * Perform the HT Link Feature PCI Register Entry. - */ -VOID -SetRegisterForHtFeaturePciEntry ( - IN TABLE_ENTRY_DATA *Entry, - IN PLATFORM_CONFIGURATION *PlatformConfig, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -/** - * Perform the HT Phy Performance Profile Register Entry. - */ -VOID -SetRegisterForHtPhyProfileEntry ( - IN TABLE_ENTRY_DATA *Entry, - IN PLATFORM_CONFIGURATION *PlatformConfig, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -/** - * Perform the HT Link PCI Register Entry. - */ -VOID -SetRegisterForHtLinkPciEntry ( - IN TABLE_ENTRY_DATA *Entry, - IN PLATFORM_CONFIGURATION *PlatformConfig, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -/** - * Compare counts to a pair of ranges. - */ -BOOLEAN -IsEitherCountInRange ( - IN UINTN FirstCount, - IN UINTN SecondCount, - IN COUNT_RANGE_FEATURE Ranges - ); - -/** - * Returns the performance profile features list of the currently running processor core. - */ -VOID -GetPerformanceFeatures ( - OUT PERFORMANCE_PROFILE_FEATS *Features, - IN PLATFORM_CONFIGURATION *PlatformConfig, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -#endif // _CPU_TABLE_H_ - diff --git a/src/vendorcode/amd/agesa/f12/Proc/CPU/cahalt.c b/src/vendorcode/amd/agesa/f12/Proc/CPU/cahalt.c deleted file mode 100644 index 57483a9b15..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/CPU/cahalt.c +++ /dev/null @@ -1,306 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * HyperTransport features and sequence implementation. - * - * Implements the external AmdHtInitialize entry point. - * Contains routines for directing the sequence of available features. - * Mostly, but not exclusively, AGESA_TESTPOINT invocations should be - * contained in this file, and not in the feature code. - * - * From a build option perspective, it may be that a few lines could be removed - * from compilation in this file for certain options. It is considered that - * the code savings from this are too small to be of concern and this file - * should not have any explicit build option implementation. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: HyperTransport - * @e \$Revision: 35978 $ @e \$Date: 2010-08-07 02:18:50 +0800 (Sat, 07 Aug 2010) $ - * - */ -/* - ***************************************************************************** - * - * Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * *************************************************************************** - * - */ - -#include "AGESA.h" -#include "cpuRegisters.h" -#include "cpuApicUtilities.h" -#include "Filecode.h" - - /*---------------------------------------------------------------------------------------- - * D E F I N I T I O N S A N D M A C R O S - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------- - * T Y P E D E F S A N D S T R U C T U R E S - *---------------------------------------------------------------------------------------- - */ - -// typedef unsigned int uintptr_t; - -/*---------------------------------------------------------------------------------------- - * P R O T O T Y P E S O F L O C A L F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ - -VOID -ExecuteFinalHltInstruction ( - IN UINT32 SharedCore, - IN AP_MTRR_SETTINGS *ApMtrrSettingsList, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -VOID -NmiHandler ( - IN OUT AMD_CONFIG_PARAMS *StdHeaderPtr - ); - -VOID -ExecuteHltInstruction ( - IN OUT AMD_CONFIG_PARAMS *StdHeaderPtr - ); - -VOID -ExecuteWbinvdInstruction ( - IN AMD_CONFIG_PARAMS *StdHeader - ); - - /*---------------------------------------------------------------------------------------- - * E X P O R T E D F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ - - -//---------------------------------------------------------------------------- - -STATIC -VOID -PrimaryCoreFunctions (AP_MTRR_SETTINGS *ApMtrrSettingsList) - { - UINT64 data; - UINT32 msrno; - // Configure the MTRRs on the AP so - // when it runs remote code it will execute - // out of RAM instead of ROM. - // Disable MTRRs and turn on modification enable bit - - data = __readmsr (0xC0010010); // MTRR_SYS_CFG - data &= ~(1 << 18); // MtrrFixDramEn - data &= ~(1 << 20); // MtrrVarDramEn - data |= (1 << 19); // MtrrFixDramModEn - data |= (1 << 17); // SysUcLockEn - - - __writemsr (0xC0010010, data); - - // Set 7FFFh-00000h and 9FFFFh-80000h as WB DRAM - __writemsr (0x250, 0x1E1E1E1E1E1E1E1Eull); // AMD_MTRR_FIX64k_00000 - __writemsr (0x258, 0x1E1E1E1E1E1E1E1Eull); // AMD_MTRR_FIX16k_80000 - - // Set BFFFFh-A0000h, DFFFFh-C0000h as Uncacheable Memory-mapped IO - __writemsr (0x259, 0); // AMD_AP_MTRR_FIX16k_A0000 - __writemsr (0x268, 0); // AMD_MTRR_FIX4k_C0000 - __writemsr (0x269, 0); // AMD_MTRR_FIX4k_C8000 - __writemsr (0x26A, 0); // AMD_MTRR_FIX4k_D0000 - __writemsr (0x26B, 0); // AMD_MTRR_FIX4k_D8000 - - // Set FFFFFh-E0000h as Uncacheable Memory - for (msrno = 0x26C; msrno <= 0x26F; msrno++) - __writemsr (msrno, 0x1818181818181818ull); - - // If IBV provided settings for Fixed-Sized MTRRs, - // overwrite the default settings. - if ((uintptr_t) ApMtrrSettingsList != 0 && (uintptr_t) ApMtrrSettingsList != 0xFFFFFFFF) - { - int index; - for (index = 0; ApMtrrSettingsList [index].MsrAddr != CPU_LIST_TERMINAL; index++) - __writemsr (ApMtrrSettingsList [index].MsrAddr, ApMtrrSettingsList [index].MsrData); - } - - // restore variable MTRR6 and MTRR7 to default states - for (msrno = 0x20F; msrno <= 0x20C; msrno--) // decrement so that the pair is disable before the base is cleared - __writemsr (msrno, 0); - - // Enable fixed-range and variable-range MTRRs - // Set Fixed-Range Enable (FE) and MTRR Enable (E) bits - __writemsr (0x2FF, __readmsr (0x2FF) | 0xC00); - - // Enable Top-of-Memory setting - // Enable use of RdMem/WrMem bits attributes - data = __readmsr (0xC0010010); // MTRR_SYS_CFG - data |= (1 << 18); // MtrrFixDramEn - data |= (1 << 20); // MtrrVarDramEn - data &= ~(1 << 19); // MtrrFixDramModEn - __writemsr (0xC0010010, data); - } - -//---------------------------------------------------------------------------- - -VOID -ExecuteFinalHltInstruction ( - IN UINT32 SharedCore, - IN AP_MTRR_SETTINGS *ApMtrrSettingsList, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - int abcdRegs [4]; - UINT32 cr0val; - UINT64 data; - - cr0val = __readcr0 (); - if (SharedCore & 2) - { - // set CombineCr0Cd and enable cache in CR0 - __writemsr (MSR_CU_CFG3, __readmsr (MSR_CU_CFG3) | 1ULL << 49); - __writecr0 (cr0val & ~0x60000000); - } - else - __writecr0 (cr0val | 0x60000000); - - if (SharedCore & 1) PrimaryCoreFunctions (ApMtrrSettingsList); - - // Make sure not to touch any Shared MSR from this point on - - // Restore settings that were temporarily overridden for the cache as ram phase - data = __readmsr (0xC0011022); // MSR_DC_CFG - data &= ~(1 << 4); // DC_DIS_SPEC_TLB_RLD - data &= ~(1 << 8); // DIS_CLR_WBTOL2_SMC_HIT - data &= ~(1 << 13); // DIS_HW_PF - __writemsr (0xC0011022, data); - - data = __readmsr (0xC0011021); // MSR_IC_CFG - C001_1021 - data &= ~(1 << 9); // IC_DIS_SPEC_TLB_RLD - __writemsr (0xC0011021, data); - - // AMD_DISABLE_STACK_FAMILY_HOOK - __cpuid (abcdRegs, 1); - if ((abcdRegs [0] >> 20) == 1) //-----family 10h (Hydra) only----- - { - data = __readmsr (0xC0011022); - data &= ~(1 << 4); - data &= ~(1 << 8); - data &= ~(1 << 13); - __writemsr (0xC0011022, data); - - data = __readmsr (0xC0011021); - data &= ~(1 << 14); - data &= ~(1 << 9); - __writemsr (0xC0011021, data); - - data = __readmsr (0xC001102A); - data &= ~(1 << 15); - data &= ~(1ull << 35); - __writemsr (0xC001102A, data); - } - else if ((abcdRegs [0] >> 20) == 6) //-----family 15h (Orochi) only----- - { - data = __readmsr (0xC0011020); - data &= ~(1 << 28); - __writemsr (0xC0011020, data); - - data = __readmsr (0xC0011021); - data &= ~(1 << 9); - __writemsr (0xC0011021, data); - - data = __readmsr (0xC0011022); - data &= ~(1 << 4); - data &= ~(1l << 13); - __writemsr (0xC0011022, data); - } - - for (;;) - { - _disable (); - __halt (); - } - } - -//---------------------------------------------------------------------------- - -/// Structure needed to load the IDTR using the lidt instruction - -VOID -SetIdtr ( - IN IDT_BASE_LIMIT *IdtInfo, - IN OUT AMD_CONFIG_PARAMS *StdHeaderPtr - ) -{ - __lidt (IdtInfo); -} - -//---------------------------------------------------------------------------- - -VOID -GetCsSelector ( - IN UINT16 *Selector, - IN OUT AMD_CONFIG_PARAMS *StdHeaderPtr - ) -{ - static const UINT8 opcode [] = {0x8C, 0xC8, 0xC3}; // mov eax, cs; ret - *Selector = ((UINT16 (*)(void)) (size_t) opcode) (); -} - -//---------------------------------------------------------------------------- - -VOID -NmiHandler ( - IN OUT AMD_CONFIG_PARAMS *StdHeaderPtr - ) -{ - static const UINT8 opcode [] = {0xCF}; // iret - ((void (*)(void)) (size_t) opcode) (); -} - -//---------------------------------------------------------------------------- - -VOID -ExecuteHltInstruction ( - IN OUT AMD_CONFIG_PARAMS *StdHeaderPtr - ) -{ - _disable (); - __halt (); -} - -//--------------------------------------------------------------------------- - -VOID -ExecuteWbinvdInstruction ( - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - __wbinvd (); -} - -//---------------------------------------------------------------------------- diff --git a/src/vendorcode/amd/agesa/f12/Proc/CPU/cpuApicUtilities.c b/src/vendorcode/amd/agesa/f12/Proc/CPU/cpuApicUtilities.c deleted file mode 100644 index 06a1d7b085..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/CPU/cpuApicUtilities.c +++ /dev/null @@ -1,1437 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * AMD CPU APIC related utility functions. - * - * Contains code that provides mechanism to invoke and control APIC communication. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: CPU - * @e \$Revision: 44393 $ @e \$Date: 2010-12-24 07:38:46 +0800 (Fri, 24 Dec 2010) $ - * - */ -/* - ****************************************************************************** - * - * Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - ****************************************************************************** - */ - -/*---------------------------------------------------------------------------------------- - * M O D U L E S U S E D - *---------------------------------------------------------------------------------------- - */ -#include "AGESA.h" -#include "amdlib.h" -#include "Ids.h" -#include "cpuCacheInit.h" -#include "cpuRegisters.h" -#include "cpuApicUtilities.h" -#include "cpuFamilyTranslation.h" -#include "GeneralServices.h" -#include "cpuServices.h" -#include "heapManager.h" -#include "Filecode.h" -CODE_GROUP (G1_PEICC) -RDATA_GROUP (G1_PEICC) - -#define FILECODE PROC_CPU_CPUAPICUTILITIES_FILECODE - -/*---------------------------------------------------------------------------------------- - * D E F I N I T I O N S A N D M A C R O S - *---------------------------------------------------------------------------------------- - */ -/* ApFlags bits */ -#define AP_TASK_HAS_INPUT 0x00000001 -#define AP_TASK_HAS_OUTPUT 0x00000002 -#define AP_RETURN_PARAMS 0x00000004 -#define AP_END_AT_HLT 0x00000008 -#define AP_PASS_EARLY_PARAMS 0x00000010 - -#define XFER_ELEMENT_SIZE sizeof (UINT32) - -/*---------------------------------------------------------------------------------------- - * T Y P E D E F S A N D S T R U C T U R E S - *---------------------------------------------------------------------------------------- - */ - -typedef VOID F_CPU_AMD_NMI_HANDLER ( - IN AMD_CONFIG_PARAMS *StdHeader - ); -typedef F_CPU_AMD_NMI_HANDLER *PF_CPU_AMD_NMI_HANDLER; - -/*---------------------------------------------------------------------------------------- - * P R O T O T Y P E S O F L O C A L F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ -VOID -STATIC -ApUtilSetupIdtForHlt ( - IN IDT_DESCRIPTOR *NmiIdtDescPtr, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -UINT32 -STATIC -ApUtilRemoteRead ( - IN UINT32 TargetApicId, - IN UINT8 RegAddr, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -VOID -STATIC -ApUtilLocalWrite ( - IN UINT32 RegAddr, - IN UINT32 Value, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -UINT32 -STATIC -ApUtilLocalRead ( - IN UINT32 RegAddr, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -VOID -STATIC -ApUtilGetLocalApicBase ( - OUT UINT64 *ApicBase, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -UINT8 -STATIC -ApUtilCalculateUniqueId ( - IN UINT8 Socket, - IN UINT8 Core, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -VOID -STATIC -ApUtilFireDirectedNmi ( - IN UINT32 TargetApicId, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -VOID -STATIC -ApUtilReceivePointer ( - IN UINT32 TargetApicId, - OUT VOID **ReturnPointer, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -VOID -STATIC -ApUtilTransmitPointer ( - IN UINT32 TargetApicId, - IN VOID **Pointer, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -VOID -STATIC -PerformFinalHalt ( - IN AMD_CONFIG_PARAMS *StdHeader - ); - -VOID -LocalApicInitializationAtEarly ( - IN CPU_SPECIFIC_SERVICES *FamilyServices, - IN AMD_CPU_EARLY_PARAMS *EarlyParams, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -/*---------------------------------------------------------------------------------------- - * E X P O R T E D F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ -extern -VOID -ExecuteHltInstruction ( - IN AMD_CONFIG_PARAMS *StdHeader - ); - -extern -VOID -NmiHandler ( - IN AMD_CONFIG_PARAMS *StdHeader - ); - -extern -VOID -ExecuteFinalHltInstruction ( - IN UINT32 SharedCore, - IN AP_MTRR_SETTINGS *ApMtrrSettingsList, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -extern BUILD_OPT_CFG UserOptions; - -/*---------------------------------------------------------------------------------------*/ -/** - * Initialize the Local APIC. - * - * This function determines and programs the appropriate APIC ID value - * for the executing core. This code must be run after HT initialization - * is complete. - * - * @param[in] CpuEarlyParamsPtr Service parameters. - * @param[in] StdHeader Config handle for library and services. - * - */ -VOID -LocalApicInitialization ( - IN AMD_CPU_EARLY_PARAMS *CpuEarlyParamsPtr, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - UINT32 CurrentCore; - UINT32 CurrentNodeNum; - UINT32 CoreIdBits; - UINT32 Mnc; - UINT32 ProcessorCount; - UINT32 ProcessorApicIndex; - UINT32 IoApicNum; - UINT32 StartLocalApicId; - UINT64 LocalApicBase; - UINT32 TempVar_a; - UINT64 MsrData; - UINT64 Address; - CPUID_DATA CpuidData; - - // Local variables default values - IoApicNum = CpuEarlyParamsPtr->PlatformConfig.NumberOfIoApics; - - GetCurrentCore (&CurrentCore, StdHeader); - GetCurrentNodeNum (&CurrentNodeNum, StdHeader); - - // Get Mnc - LibAmdCpuidRead (AMD_CPUID_ASIZE_PCCOUNT, &CpuidData, StdHeader); - CoreIdBits = (CpuidData.ECX_Reg & 0x0000F000) >> 12; - Mnc = 1 << (CoreIdBits & 0x000F); - - // Get ProcessorCount in the system - ProcessorCount = GetNumberOfProcessors (StdHeader); - - // Get the APIC Index of this processor. - ProcessorApicIndex = GetProcessorApicIndex (CurrentNodeNum, StdHeader); - - TempVar_a = (Mnc * ProcessorCount) + IoApicNum; - ASSERT (TempVar_a < 255); - - // Apply apic enumeration rules - // For systems with >= 16 APICs, put the IO-APICs at 0..n and - // put the local-APICs at m..z - // For systems with < 16 APICs, put the Local-APICs at 0..n and - // put the IO-APICs at (n + 1)..z - // This is needed because many IO-APIC devices only have 4 bits - // for their APIC id and therefore must reside at 0..15 - StartLocalApicId = 0; - if (TempVar_a >= 16) { - if (IoApicNum >= 1) { - StartLocalApicId = (IoApicNum - 1) / Mnc; - StartLocalApicId = (StartLocalApicId + 1) * Mnc; - } - } - - // Set local apic id - TempVar_a = (ProcessorApicIndex * Mnc) + CurrentCore + StartLocalApicId; - IDS_HDT_CONSOLE (CPU_TRACE, " Node %d core %d APIC ID = 0x%x\n", CurrentNodeNum, CurrentCore, TempVar_a); - TempVar_a = TempVar_a << APIC20_ApicId; - - // Enable local apic id - LibAmdMsrRead (MSR_APIC_BAR, &MsrData, StdHeader); - MsrData |= APIC_ENABLE_BIT; - LibAmdMsrWrite (MSR_APIC_BAR, &MsrData, StdHeader); - - // Get local apic base Address - ApUtilGetLocalApicBase (&LocalApicBase, StdHeader); - - Address = LocalApicBase + APIC_ID_REG; - LibAmdMemWrite (AccessWidth32, Address, &TempVar_a, StdHeader); -} - -/*---------------------------------------------------------------------------------------*/ -/** - * Initialize the Local APIC at the AmdInitEarly entry point. - * - * This function acts as a wrapper for calling the LocalApicInitialization - * routine at AmdInitEarly. - * - * @param[in] FamilyServices The current Family Specific Services. - * @param[in] EarlyParams Service parameters. - * @param[in] StdHeader Config handle for library and services. - * - */ -VOID -LocalApicInitializationAtEarly ( - IN CPU_SPECIFIC_SERVICES *FamilyServices, - IN AMD_CPU_EARLY_PARAMS *EarlyParams, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - AGESA_TESTPOINT (TpProcCpuLocalApicInit, StdHeader); - LocalApicInitialization (EarlyParams, StdHeader); -} - - -/*---------------------------------------------------------------------------------------*/ -/** - * Main entry point for all APs in the system. - * - * This routine puts the AP cores in an infinite loop in which the cores - * will poll their masters, waiting to be told to perform a task. At early, - * all socket-relative core zeros will receive their tasks from the BSC. - * All others will receive their tasks from the core zero of their local - * processor. At the end of AmdInitEarly, all cores will switch to receiving - * their tasks from the BSC. - * - * @param[in] StdHeader Handle to config for library and services. - * @param[in] CpuEarlyParams AMD_CPU_EARLY_PARAMS pointer. - * - */ -VOID -ApEntry ( - IN AMD_CONFIG_PARAMS *StdHeader, - IN AMD_CPU_EARLY_PARAMS *CpuEarlyParams - ) -{ - UINT8 RemoteCmd; - UINT8 SourceSocket; - UINT8 CommandStart; - UINT32 ApFlags; - UINT32 FuncType; - UINT32 ReturnCode; - UINT32 CurrentSocket; - UINT32 CurrentCore; - UINT32 *InputDataPtr; - UINT32 BscSocket; - UINT32 Ignored; - UINT32 TargetApicId; - AP_FUNCTION_PTR FuncAddress; - IDT_DESCRIPTOR IdtDesc[32]; - AP_DATA_TRANSFER DataTransferInfo; - AGESA_STATUS IgnoredSts; - - ASSERT (!IsBsp (StdHeader, &IgnoredSts)); - - // Initialize local variables - ReturnCode = 0; - DataTransferInfo.DataTransferFlags = 0; - InputDataPtr = NULL; - - // Determine the executing core's socket and core numbers - IdentifyCore (StdHeader, &CurrentSocket, &Ignored, &CurrentCore, &IgnoredSts); - - IDS_HDT_CONSOLE (CPU_TRACE, " Socket %d core %d begin AP tasking engine\n", CurrentSocket, CurrentCore); - - // Determine the BSC's socket number - GetSocketModuleOfNode ((UINT32) 0x00000000, &BscSocket, &Ignored, StdHeader); - - // Setup Interrupt Descriptor Table for sleep mode - ApUtilSetupIdtForHlt (&IdtDesc[2], StdHeader); - - // Indicate to the BSC that we have reached the tasking engine - ApUtilWriteControlByte (CORE_IDLE, StdHeader); - - if (CurrentCore == 0) { - // Core 0s receive their tasks from the BSC - SourceSocket = (UINT8) BscSocket; - } else { - // All non-zero cores receive their tasks from the core 0 of their socket - SourceSocket = (UINT8) CurrentSocket; - } - - GetLocalApicIdForCore (SourceSocket, 0, &TargetApicId, StdHeader); - - // Determine the unique value that the master will write when it has a task - // for this core to perform. - CommandStart = ApUtilCalculateUniqueId ( - (UINT8)CurrentSocket, - (UINT8)CurrentCore, - StdHeader - ); - for (;;) { - RemoteCmd = ApUtilReadRemoteControlByte (TargetApicId, StdHeader); - if (RemoteCmd == CommandStart) { - ApFlags = ApUtilReadRemoteDataDword (TargetApicId, StdHeader); - - ApUtilReceivePointer (TargetApicId, (VOID **) &FuncAddress, StdHeader); - - FuncType = ApFlags & (UINT32) (AP_TASK_HAS_INPUT | AP_TASK_HAS_OUTPUT | AP_PASS_EARLY_PARAMS); - if ((ApFlags & AP_TASK_HAS_INPUT) != 0) { - DataTransferInfo.DataSizeInDwords = 0; - DataTransferInfo.DataPtr = NULL; - DataTransferInfo.DataTransferFlags = 0; - if (ApUtilReceiveBuffer (SourceSocket, 0, &DataTransferInfo, StdHeader) == AGESA_ERROR) { - // There is not enough space to put the input data on the heap. Undefined behavior is about - // to result. - IDS_ERROR_TRAP; - } - InputDataPtr = (UINT32 *) DataTransferInfo.DataPtr; - } - ApUtilWriteControlByte (CORE_ACTIVE, StdHeader); - switch (FuncType) { - case 0: - FuncAddress.PfApTask (StdHeader); - break; - case AP_TASK_HAS_INPUT: - FuncAddress.PfApTaskI (InputDataPtr, StdHeader); - break; - case AP_PASS_EARLY_PARAMS: - FuncAddress.PfApTaskC (StdHeader, CpuEarlyParams); - break; - case (AP_TASK_HAS_INPUT | AP_PASS_EARLY_PARAMS): - FuncAddress.PfApTaskIC (InputDataPtr, StdHeader, CpuEarlyParams); - break; - case AP_TASK_HAS_OUTPUT: - ReturnCode = FuncAddress.PfApTaskO (StdHeader); - break; - case (AP_TASK_HAS_INPUT | AP_TASK_HAS_OUTPUT): - ReturnCode = FuncAddress.PfApTaskIO (InputDataPtr, StdHeader); - break; - case (AP_TASK_HAS_OUTPUT | AP_PASS_EARLY_PARAMS): - ReturnCode = FuncAddress.PfApTaskOC (StdHeader, CpuEarlyParams); - break; - case (AP_TASK_HAS_INPUT | AP_TASK_HAS_OUTPUT | AP_PASS_EARLY_PARAMS): - ReturnCode = FuncAddress.PfApTaskIOC (InputDataPtr, StdHeader, CpuEarlyParams); - break; - default: - ReturnCode = 0; - break; - } - if (((ApFlags & AP_RETURN_PARAMS) != 0)) { - ApUtilTransmitBuffer (SourceSocket, 0, &DataTransferInfo, StdHeader); - } - if ((ApFlags & AP_TASK_HAS_OUTPUT) != 0) { - ApUtilWriteDataDword (ReturnCode, StdHeader); - } - if ((ApFlags & AP_END_AT_HLT) != 0) { - RemoteCmd = CORE_IDLE_HLT; - } else { - ApUtilWriteControlByte (CORE_IDLE, StdHeader); - } - } - if (RemoteCmd == CORE_IDLE_HLT) { - SourceSocket = (UINT8) BscSocket; - GetLocalApicIdForCore (SourceSocket, 0, &TargetApicId, StdHeader); - ApUtilWriteControlByte (CORE_IDLE_HLT, StdHeader); - ExecuteHltInstruction (StdHeader); - ApUtilWriteControlByte (CORE_IDLE, StdHeader); - } - } -} - - -/*---------------------------------------------------------------------------------------*/ -/** - * Reads the 'control byte' on the designated remote core. - * - * This function will read the current contents of the control byte - * on the designated core using the APIC remote read inter- - * processor interrupt sequence. - * - * @param[in] TargetApicId Local APIC ID of the desired core - * @param[in] StdHeader Configuration parameters pointer - * - * @return The current value of the remote cores control byte - * - */ -UINT8 -ApUtilReadRemoteControlByte ( - IN UINT32 TargetApicId, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - UINT8 ControlByte; - UINT32 ApicRegister; - - ApicRegister = ApUtilRemoteRead (TargetApicId, APIC_CTRL_DWORD, StdHeader); - ControlByte = (UINT8) ((ApicRegister & APIC_CTRL_MASK) >> APIC_CTRL_SHIFT); - return (ControlByte); -} - - -/*---------------------------------------------------------------------------------------*/ -/** - * Writes the 'control byte' on the executing core. - * - * This function writes data to a local APIC offset used in inter- - * processor communication. - * - * @param[in] Value - * @param[in] StdHeader - * - */ -VOID -ApUtilWriteControlByte ( - IN UINT8 Value, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - UINT32 ApicRegister; - - ApicRegister = ApUtilLocalRead (APIC_CTRL_REG, StdHeader); - ApicRegister = ((ApicRegister & ~APIC_CTRL_MASK) | (UINT32) (Value << APIC_CTRL_SHIFT)); - ApUtilLocalWrite (APIC_CTRL_REG, ApicRegister, StdHeader); -} - - -/*---------------------------------------------------------------------------------------*/ -/** - * Reads the 'data dword' on the designated remote core. - * - * This function will read the current contents of the data dword - * on the designated core using the APIC remote read inter- - * processor interrupt sequence. - * - * @param[in] TargetApicId Local APIC ID of the desired core - * @param[in] StdHeader Configuration parameters pointer - * - * @return The current value of the remote core's data dword - * - */ -UINT32 -ApUtilReadRemoteDataDword ( - IN UINT32 TargetApicId, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - return (ApUtilRemoteRead (TargetApicId, APIC_DATA_DWORD, StdHeader)); -} - - -/*---------------------------------------------------------------------------------------*/ -/** - * Writes the 'data dword' on the executing core. - * - * This function writes data to a local APIC offset used in inter- - * processor communication. - * - * @param[in] Value Value to write - * @param[in] StdHeader Configuration parameters pointer - * - */ -VOID -ApUtilWriteDataDword ( - IN UINT32 Value, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - ApUtilLocalWrite (APIC_DATA_REG, Value, StdHeader); -} - - -/*---------------------------------------------------------------------------------------*/ -/** - * Runs the given task on the specified local core. - * - * This function is used to invoke an AP to run a specified AGESA - * procedure. It can only be called by cores that have subordinate - * APs -- the BSC at POST, or any socket-relative core 0s at Early. - * - * @param[in] Socket Socket number of the target core - * @param[in] Core Core number of the target core - * @param[in] TaskPtr Function descriptor - * @param[in] StdHeader Configuration parameters pointer - * - * @return Return value of the task that the AP core ran, - * or zero if the task was VOID. - * - */ -UINT32 -ApUtilRunCodeOnSocketCore ( - IN UINT8 Socket, - IN UINT8 Core, - IN AP_TASK *TaskPtr, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - UINT8 CoreId; - UINT8 CurrentStatus; - UINT8 WaitStatus[3]; - UINT32 ApFlags; - UINT32 ReturnCode; - UINT32 TargetApicId; - AP_WAIT_FOR_STATUS WaitForStatus; - - ApFlags = 0; - ReturnCode = 0; - - CoreId = ApUtilCalculateUniqueId (Socket, Core, StdHeader); - - GetLocalApicIdForCore (Socket, Core, &TargetApicId, StdHeader); - - if (TaskPtr->DataTransfer.DataSizeInDwords != 0) { - ApFlags |= AP_TASK_HAS_INPUT; - if (((TaskPtr->ExeFlags & RETURN_PARAMS) != 0) && - ((TaskPtr->DataTransfer.DataTransferFlags & DATA_IN_MEMORY) == 0)) { - ApFlags |= AP_RETURN_PARAMS; - } - } - - if ((TaskPtr->ExeFlags & TASK_HAS_OUTPUT) != 0) { - ApFlags |= AP_TASK_HAS_OUTPUT; - } - - if ((TaskPtr->ExeFlags & END_AT_HLT) != 0) { - ApFlags |= AP_END_AT_HLT; - } - - if ((TaskPtr->ExeFlags & PASS_EARLY_PARAMS) != 0) { - ApFlags |= AP_PASS_EARLY_PARAMS; - } - - WaitStatus[0] = CORE_IDLE; - WaitStatus[1] = CORE_IDLE_HLT; - WaitStatus[2] = CORE_UNAVAILABLE; - WaitForStatus.Status = WaitStatus; - WaitForStatus.NumberOfElements = 3; - WaitForStatus.RetryCount = WAIT_INFINITELY; - WaitForStatus.WaitForStatusFlags = WAIT_STATUS_EQUALITY; - CurrentStatus = ApUtilWaitForCoreStatus (TargetApicId, &WaitForStatus, StdHeader); - - if (CurrentStatus != CORE_UNAVAILABLE) { - ApUtilWriteDataDword (ApFlags, StdHeader); - ApUtilWriteControlByte (CoreId, StdHeader); - - if (CurrentStatus == CORE_IDLE_HLT) { - ApUtilFireDirectedNmi (TargetApicId, StdHeader); - } - - ApUtilTransmitPointer (TargetApicId, (VOID **) &TaskPtr->FuncAddress, StdHeader); - - if ((ApFlags & AP_TASK_HAS_INPUT) != 0) { - ApUtilTransmitBuffer (Socket, Core, &TaskPtr->DataTransfer, StdHeader); - } - - if ((TaskPtr->ExeFlags & WAIT_FOR_CORE) != 0) { - if (((ApFlags & AP_TASK_HAS_INPUT) != 0) && - ((ApFlags & AP_RETURN_PARAMS) != 0) && - ((TaskPtr->DataTransfer.DataTransferFlags & DATA_IN_MEMORY) == 0)) { - if (ApUtilReceiveBuffer (Socket, Core, &TaskPtr->DataTransfer, StdHeader) == AGESA_ERROR) { - // There is not enough space to put the return data. This should never occur. If it - // does, this would point to strange heap corruption. - IDS_ERROR_TRAP; - } - } - - ApUtilWaitForCoreStatus (TargetApicId, &WaitForStatus, StdHeader); - if ((ApFlags & AP_TASK_HAS_OUTPUT) != 0) { - ReturnCode = ApUtilReadRemoteDataDword (TargetApicId, StdHeader); - } - } - } else { - ReturnCode = 0; - } - return (ReturnCode); -} - - -/*---------------------------------------------------------------------------------------*/ -/** - * Waits for a remote core's control byte value to either be equal or - * not equal to any number of specified values. - * - * This function will loop doing remote read IPIs until the remote core's - * control byte becomes one of the values in the input array if the input - * flags are set for equality. Otherwise, the loop will continue until - * the control byte value is not equal to one of the elements in the - * array. The caller can also specify an iteration count for timeout - * purposes. - * - * @param[in] TargetApicId Local APIC ID of the desired core - * @param[in] WaitParamsPtr Wait parameter structure - * @param[in] StdHeader Configuration parameteres pointer - * - * @return The current value of the remote core's control byte - * - */ -UINT8 -ApUtilWaitForCoreStatus ( - IN UINT32 TargetApicId, - IN AP_WAIT_FOR_STATUS *WaitParamsPtr, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - BOOLEAN IsEqual; - UINT8 CoreStatus; - UINT8 i; - UINT8 j; - - CoreStatus = 0; - for (i = 0; (WaitParamsPtr->RetryCount == WAIT_INFINITELY) || - (i < WaitParamsPtr->RetryCount); ++i) { - CoreStatus = ApUtilReadRemoteControlByte (TargetApicId, StdHeader); - // Determine whether or not the current remote status is equal - // to an element in the array. - IsEqual = FALSE; - for (j = 0; !IsEqual && j < WaitParamsPtr->NumberOfElements; ++j) { - if (CoreStatus == WaitParamsPtr->Status[j]) { - IsEqual = TRUE; - } - } - if ((((WaitParamsPtr->WaitForStatusFlags & WAIT_STATUS_EQUALITY) != 0) && IsEqual) || - (((WaitParamsPtr->WaitForStatusFlags & WAIT_STATUS_EQUALITY) == 0) && !IsEqual)) { - break; - } - } - return (CoreStatus); -} - - -/*---------------------------------------------------------------------------------------*/ -/** - * Runs the AP task on the executing core. - * - * @param[in] TaskPtr Function descriptor - * @param[in] StdHeader Configuration parameters pointer - * @param[in] ConfigParams Entry point CPU parameters pointer - * - * @return Return value of the task, or zero if the task - * was VOID. - * - */ -UINT32 -ApUtilTaskOnExecutingCore ( - IN AP_TASK *TaskPtr, - IN AMD_CONFIG_PARAMS *StdHeader, - IN VOID *ConfigParams - ) -{ - UINT32 InvocationOptions; - UINT32 ReturnCode; - - ReturnCode = 0; - InvocationOptions = 0; - - if (TaskPtr->DataTransfer.DataSizeInDwords != 0) { - InvocationOptions |= AP_TASK_HAS_INPUT; - } - if ((TaskPtr->ExeFlags & TASK_HAS_OUTPUT) != 0) { - InvocationOptions |= AP_TASK_HAS_OUTPUT; - } - if ((TaskPtr->ExeFlags & PASS_EARLY_PARAMS) != 0) { - InvocationOptions |= AP_PASS_EARLY_PARAMS; - } - - switch (InvocationOptions) { - case 0: - TaskPtr->FuncAddress.PfApTask (StdHeader); - break; - case AP_TASK_HAS_INPUT: - TaskPtr->FuncAddress.PfApTaskI (TaskPtr->DataTransfer.DataPtr, StdHeader); - break; - case AP_PASS_EARLY_PARAMS: - TaskPtr->FuncAddress.PfApTaskC (StdHeader, ConfigParams); - break; - case (AP_TASK_HAS_INPUT | AP_PASS_EARLY_PARAMS): - TaskPtr->FuncAddress.PfApTaskIC (TaskPtr->DataTransfer.DataPtr, StdHeader, ConfigParams); - break; - case AP_TASK_HAS_OUTPUT: - ReturnCode = TaskPtr->FuncAddress.PfApTaskO (StdHeader); - break; - case (AP_TASK_HAS_INPUT | AP_TASK_HAS_OUTPUT): - ReturnCode = TaskPtr->FuncAddress.PfApTaskIO (TaskPtr->DataTransfer.DataPtr, StdHeader); - break; - case (AP_TASK_HAS_OUTPUT | AP_PASS_EARLY_PARAMS): - ReturnCode = TaskPtr->FuncAddress.PfApTaskOC (StdHeader, ConfigParams); - break; - case (AP_TASK_HAS_INPUT | AP_TASK_HAS_OUTPUT | AP_PASS_EARLY_PARAMS): - ReturnCode = TaskPtr->FuncAddress.PfApTaskIOC (TaskPtr->DataTransfer.DataPtr, StdHeader, ConfigParams); - break; - default: - ReturnCode = 0; - break; - } - return (ReturnCode); -} - -/*---------------------------------------------------------------------------------------*/ -/** - * Sets up the AP's IDT with NMI (INT2) being the only valid descriptor - * - * This function prepares the executing AP core for recovering from a hlt - * instruction by initializing its IDTR. - * - * @param[in] NmiIdtDescPtr Pointer to a writable IDT entry to - * be used for NMIs - * @param[in] StdHeader Configuration parameters pointer - * - */ -VOID -STATIC -ApUtilSetupIdtForHlt ( - IN IDT_DESCRIPTOR *NmiIdtDescPtr, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - UINT8 DescSize; - UINT64 HandlerOffset; - UINT64 EferRegister; - IDT_BASE_LIMIT IdtInfo; - - LibAmdMsrRead (MSR_EXTENDED_FEATURE_EN, &EferRegister, StdHeader); - if ((EferRegister & 0x100) != 0) { - DescSize = 16; - } else { - DescSize = 8; - } - - HandlerOffset = (UINT64) (intptr_t) NmiHandler; - NmiIdtDescPtr->OffsetLo = (UINT16) HandlerOffset & 0xFFFF; - NmiIdtDescPtr->OffsetHi = (UINT16) (HandlerOffset >> 16); - GetCsSelector (&NmiIdtDescPtr->Selector, StdHeader); - NmiIdtDescPtr->Flags = IDT_DESC_PRESENT | IDT_DESC_TYPE_INT32; - NmiIdtDescPtr->Rsvd = 0; - NmiIdtDescPtr->Offset64 = (UINT32) (HandlerOffset >> 32); - NmiIdtDescPtr->Rsvd64 = 0; - IdtInfo.Limit = (UINT16) ((DescSize * 3) - 1); - IdtInfo.Base = (UINT64) (intptr_t) NmiIdtDescPtr - (DescSize * 2); -// IDS_EXCEPTION_TRAP (IDS_IDT_UPDATE_EXCEPTION_VECTOR_FOR_AP, &IdtInfo, StdHeader); - SetIdtr (&IdtInfo , StdHeader); -} - - -/*---------------------------------------------------------------------------------------*/ -/** - * Calculate the APIC ID for a given core. - * - * Get the current node's apic id and deconstruct it to the base id of local apic id space. - * Then construct the target's apic id using that base. - * @b Assumes: The target Socket and Core exist! - * Other Notes: - * - Must run after HT initialization is complete. - * - Code sync: This calculation MUST match the assignment - * calculation done above in LocalApicInitializationAtEarly function. - * - Assumes family homogeneous population of all sockets. - * - * @param[in] TargetSocket The socket in which the Core's Processor is installed. - * @param[in] TargetCore The Core on that Processor - * @param[out] LocalApicId Its APIC Id - * @param[in] StdHeader Handle to header for library and services. - * - */ -VOID -GetLocalApicIdForCore ( - IN UINT32 TargetSocket, - IN UINT32 TargetCore, - OUT UINT32 *LocalApicId, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - UINT32 CoreIdBits; - UINT32 CurrentNode; - UINT32 CurrentCore; - UINT32 TargetNode; - UINT32 MaxCoresInProcessor; - UINT32 TotalCores; - UINT32 CurrentLocalApicId; - UINT64 LocalApicBase; - UINT32 TempVar_a; - UINT64 Address; - UINT32 ProcessorApicIndex; - BOOLEAN ReturnResult; - CPUID_DATA CpuidData; - - TargetNode = 0; - - // Get local apic base Address - ApUtilGetLocalApicBase (&LocalApicBase, StdHeader); - Address = LocalApicBase + APIC_ID_REG; - - LibAmdMemRead (AccessWidth32, Address, &TempVar_a, StdHeader); - - // ApicId [7:0] - CurrentLocalApicId = (TempVar_a >> APIC20_ApicId) & 0x000000FF; - - GetCurrentNodeAndCore (&CurrentNode, &CurrentCore, StdHeader); - LibAmdCpuidRead (AMD_CPUID_ASIZE_PCCOUNT, &CpuidData, StdHeader); - CoreIdBits = (CpuidData.ECX_Reg & 0x0000F000) >> 12; - MaxCoresInProcessor = (1 << CoreIdBits); - - // Get the APIC Index of this processor. - ProcessorApicIndex = GetProcessorApicIndex (CurrentNode, StdHeader); - - TotalCores = (MaxCoresInProcessor * ProcessorApicIndex) + CurrentCore; - CurrentLocalApicId -= TotalCores; - - // Use the Node Id of TargetSocket, Module 0. No socket transitions are missed or added, - // even if the TargetCore is not on Module 0 in that processor and that's all that matters now. - ReturnResult = GetNodeId (TargetSocket, 0, (UINT8 *)&TargetNode, StdHeader); - ASSERT (ReturnResult); - - // Get the APIC Index of this processor. - ProcessorApicIndex = GetProcessorApicIndex (TargetNode, StdHeader); - - CurrentLocalApicId += ((MaxCoresInProcessor * ProcessorApicIndex) + TargetCore); - *LocalApicId = CurrentLocalApicId; -} - -/*---------------------------------------------------------------------------------------*/ -/** - * Securely passes a buffer to the designated remote core. - * - * This function uses a sequence of remote reads to transmit a data - * buffer, one UINT32 at a time. - * - * @param[in] Socket Socket number of the remote core - * @param[in] Core Core number of the remote core - * @param[in] BufferInfo Information about the buffer to pass, and - * how to pass it - * @param[in] StdHeader Configuration parameters pointer - * - */ -VOID -ApUtilTransmitBuffer ( - IN UINT8 Socket, - IN UINT8 Core, - IN AP_DATA_TRANSFER *BufferInfo, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - UINT8 TargetCore; - UINT8 MyUniqueId; - UINT8 CurrentStatus; - UINT32 *CurrentPtr; - UINT32 i; - UINT32 MyCore; - UINT32 MySocket; - UINT32 Ignored; - UINT32 TargetApicId; - AP_WAIT_FOR_STATUS WaitForStatus; - AGESA_STATUS IgnoredSts; - - GetLocalApicIdForCore ((UINT32) Socket, (UINT32) Core, &TargetApicId, StdHeader); - - if ((BufferInfo->DataTransferFlags & DATA_IN_MEMORY) != 0) { - ApUtilWriteDataDword ((UINT32) 0x00000000, StdHeader); - } else { - ApUtilWriteDataDword ((UINT32) BufferInfo->DataSizeInDwords, StdHeader); - } - TargetCore = ApUtilCalculateUniqueId (Socket, Core, StdHeader); - - ApUtilWriteControlByte (TargetCore, StdHeader); - - IdentifyCore (StdHeader, &MySocket, &Ignored, &MyCore, &IgnoredSts); - - MyUniqueId = ApUtilCalculateUniqueId ((UINT8)MySocket, (UINT8)MyCore, StdHeader); - - WaitForStatus.Status = &MyUniqueId; - WaitForStatus.NumberOfElements = 1; - WaitForStatus.RetryCount = WAIT_INFINITELY; - WaitForStatus.WaitForStatusFlags = WAIT_STATUS_EQUALITY; - - ApUtilWaitForCoreStatus (TargetApicId, &WaitForStatus, StdHeader); - ApUtilWriteDataDword (BufferInfo->DataTransferFlags, StdHeader); - - ApUtilWriteControlByte (CORE_DATA_FLAGS_READY, StdHeader); - WaitForStatus.WaitForStatusFlags = 0; - ApUtilWaitForCoreStatus (TargetApicId, &WaitForStatus, StdHeader); - if ((BufferInfo->DataTransferFlags & DATA_IN_MEMORY) != 0) { - ApUtilTransmitPointer (TargetApicId, (VOID **) &BufferInfo->DataPtr, StdHeader); - } else { - ApUtilWriteControlByte (CORE_STS_DATA_READY_1, StdHeader); - CurrentStatus = CORE_STS_DATA_READY_0; - WaitForStatus.Status = &CurrentStatus; - WaitForStatus.WaitForStatusFlags = WAIT_STATUS_EQUALITY; - ApUtilWaitForCoreStatus (TargetApicId, &WaitForStatus, StdHeader); - WaitForStatus.WaitForStatusFlags = 0; - CurrentPtr = (UINT32 *) BufferInfo->DataPtr; - for (i = 0; i < BufferInfo->DataSizeInDwords; ++i) { - ApUtilWriteDataDword (*CurrentPtr++, StdHeader); - ApUtilWriteControlByte (CurrentStatus, StdHeader); - ApUtilWaitForCoreStatus (TargetApicId, &WaitForStatus, StdHeader); - CurrentStatus ^= 0x01; - } - } - ApUtilWriteControlByte (CORE_ACTIVE, StdHeader); -} - - -/*---------------------------------------------------------------------------------------*/ -/** - * Securely receives a buffer from the designated remote core. - * - * This function uses a sequence of remote reads to receive a data - * buffer, one UINT32 at a time. - * - * @param[in] Socket Socket number of the remote core - * @param[in] Core Core number of the remote core - * @param[in] BufferInfo Information about where to place the buffer - * @param[in] StdHeader Configuration parameters pointer - * - * @retval AGESA_SUCCESS Transaction was successful - * @retval AGESA_ALERT The non-NULL desired location to place - * the buffer was not used as the buffer - * resides in a shared memory space. The - * input data pointer has changed. - * @retval AGESA_ERROR There is not enough room to receive the - * buffer. - * - */ -AGESA_STATUS -ApUtilReceiveBuffer ( - IN UINT8 Socket, - IN UINT8 Core, - IN OUT AP_DATA_TRANSFER *BufferInfo, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - UINT8 MyUniqueId; - UINT8 SourceUniqueId; - UINT8 CurrentStatus; - UINT32 i; - UINT32 MySocket; - UINT32 MyCore; - UINT32 Ignored; - UINT32 *CurrentPtr; - UINT32 TransactionSize; - UINT32 TargetApicId; - AGESA_STATUS ReturnStatus; - ALLOCATE_HEAP_PARAMS HeapMalloc; - AP_WAIT_FOR_STATUS WaitForStatus; - - ReturnStatus = AGESA_SUCCESS; - IdentifyCore (StdHeader, &MySocket, &Ignored, &MyCore, &ReturnStatus); - - MyUniqueId = ApUtilCalculateUniqueId ((UINT8)MySocket, (UINT8)MyCore, StdHeader); - - GetLocalApicIdForCore ((UINT32) Socket, (UINT32) Core, &TargetApicId, StdHeader); - - WaitForStatus.Status = &MyUniqueId; - WaitForStatus.NumberOfElements = 1; - WaitForStatus.RetryCount = WAIT_INFINITELY; - WaitForStatus.WaitForStatusFlags = WAIT_STATUS_EQUALITY; - - ApUtilWaitForCoreStatus (TargetApicId, &WaitForStatus, StdHeader); - TransactionSize = ApUtilReadRemoteDataDword (TargetApicId, StdHeader); - - if (BufferInfo->DataPtr == NULL && TransactionSize != 0) { - HeapMalloc.BufferHandle = AMD_CPU_AP_TASKING_HANDLE; - HeapMalloc.Persist = HEAP_LOCAL_CACHE; - // Deallocate the general purpose heap structure, if it exists. Ignore - // the status in case it does not exist. - HeapDeallocateBuffer (HeapMalloc.BufferHandle, StdHeader); - HeapMalloc.RequestedBufferSize = (TransactionSize * XFER_ELEMENT_SIZE); - if (HeapAllocateBuffer (&HeapMalloc, StdHeader) == AGESA_SUCCESS) { - BufferInfo->DataPtr = (UINT32 *) HeapMalloc.BufferPtr; - BufferInfo->DataSizeInDwords = (UINT16) (HeapMalloc.RequestedBufferSize / XFER_ELEMENT_SIZE); - } else { - BufferInfo->DataSizeInDwords = 0; - } - } - - if (TransactionSize <= BufferInfo->DataSizeInDwords) { - SourceUniqueId = ApUtilCalculateUniqueId (Socket, Core, StdHeader); - ApUtilWriteControlByte (SourceUniqueId, StdHeader); - CurrentStatus = CORE_DATA_FLAGS_READY; - WaitForStatus.Status = &CurrentStatus; - ApUtilWaitForCoreStatus (TargetApicId, &WaitForStatus, StdHeader); - BufferInfo->DataTransferFlags = ApUtilReadRemoteDataDword (TargetApicId, StdHeader); - ApUtilWriteControlByte (CORE_DATA_FLAGS_ACKNOWLEDGE, StdHeader); - if ((BufferInfo->DataTransferFlags & DATA_IN_MEMORY) != 0) { - if (BufferInfo->DataPtr != NULL) { - ReturnStatus = AGESA_ALERT; - } - ApUtilReceivePointer (TargetApicId, (VOID **) &BufferInfo->DataPtr, StdHeader); - } else { - CurrentStatus = CORE_STS_DATA_READY_1; - ApUtilWaitForCoreStatus (TargetApicId, &WaitForStatus, StdHeader); - CurrentStatus = CORE_STS_DATA_READY_0; - ApUtilWriteControlByte (CurrentStatus, StdHeader); - CurrentPtr = BufferInfo->DataPtr; - for (i = 0; i < TransactionSize; ++i) { - ApUtilWaitForCoreStatus (TargetApicId, &WaitForStatus, StdHeader); - *CurrentPtr++ = ApUtilReadRemoteDataDword (TargetApicId, StdHeader); - CurrentStatus ^= 0x01; - ApUtilWriteControlByte (CurrentStatus, StdHeader); - } - } - ApUtilWriteControlByte (CORE_ACTIVE, StdHeader); - } else { - BufferInfo->DataSizeInDwords = (UINT16) TransactionSize; - ReturnStatus = AGESA_ERROR; - } - return (ReturnStatus); -} - - -VOID -RelinquishControlOfAllAPs ( - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - UINT32 BscSocket; - UINT32 Ignored; - UINT32 BscCoreNum; - UINT32 Core; - UINT32 Socket; - UINT32 NumberOfSockets; - AP_TASK TaskPtr; - AGESA_STATUS IgnoredSts; - - ASSERT (IsBsp (StdHeader, &IgnoredSts)); - - TaskPtr.FuncAddress.PfApTask = PerformFinalHalt; - TaskPtr.DataTransfer.DataSizeInDwords = 0; - TaskPtr.ExeFlags = WAIT_FOR_CORE; - - IdentifyCore (StdHeader, &BscSocket, &Ignored, &BscCoreNum, &IgnoredSts); - NumberOfSockets = GetPlatformNumberOfSockets (); - - for (Socket = 0; Socket < NumberOfSockets; Socket++) { - if (GetActiveCoresInGivenSocket (Socket, &Core, StdHeader)) { - while (Core-- > 0) { - if ((Socket != BscSocket) || (Core != BscCoreNum)) { - ApUtilRunCodeOnSocketCore ((UINT8) Socket, (UINT8) Core, &TaskPtr, StdHeader); - } - } - } - } -} - -/*--------------------------------------------------------------------------------------- - * L O C A L F U N C T I O N S - *--------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------*/ -/** - * The last AGESA code that an AP performs - * - * This function, run only by APs, breaks down their cache subsystem, sets up - * for memory to be present upon wake (from IBV Init/Startup IPIs), and halts. - * - * @param[in] StdHeader Config handle for library and services - * - */ -VOID -STATIC -PerformFinalHalt ( - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - UINT32 PrimaryCore; - UINT32 HaltFlags; - UINT32 CacheEnDis; - CPU_SPECIFIC_SERVICES *FamilyServices; - - GetCpuServicesOfCurrentCore ((const CPU_SPECIFIC_SERVICES **)&FamilyServices, StdHeader); - ASSERT (FamilyServices != NULL); - // CacheEnDis is a family specific flag, that lets the code to decide whether to - // keep the cache control bits set or cleared. - CacheEnDis = FamilyServices->InitCacheDisabled; - - // Determine if the current core has the primary core role. The first core to execute - // in each compute unit has the primary role. - PrimaryCore = (UINT32) IsCorePairPrimary (FirstCoreIsComputeUnitPrimary, StdHeader); - - // Aggregate the flags for the halt service. - HaltFlags = PrimaryCore | (CacheEnDis << 1); - - ApUtilWriteControlByte (CORE_UNAVAILABLE, StdHeader); - ExecuteFinalHltInstruction (HaltFlags, UserOptions.CfgApMtrrSettingsList, StdHeader); -} - -/*---------------------------------------------------------------------------------------*/ -/** - * Reads the APIC register on the designated remote core. - * - * This function uses the remote read inter-processor interrupt protocol - * to read an APIC register from the remote core - * - * @param[in] TargetApicId Local APIC ID of the desired core - * @param[in] RegAddr APIC register to read - * @param[in] StdHeader Configuration parameters pointer - * - * @return The current value of the remote core's desired APIC register - * - */ -UINT32 -STATIC -ApUtilRemoteRead ( - IN UINT32 TargetApicId, - IN UINT8 RegAddr, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - UINT32 ApicRegister; - UINT64 ApicBase; - UINT64 ApicAddr; - - ApUtilGetLocalApicBase (&ApicBase, StdHeader); - TargetApicId <<= LOCAL_APIC_ID; - - do { - ApicAddr = ApicBase + APIC_CMD_HI_REG; - LibAmdMemWrite (AccessWidth32, ApicAddr, &TargetApicId, StdHeader); - ApicAddr = ApicBase + APIC_CMD_LO_REG; - ApicRegister = CMD_REG_TO_READ | (UINT32) RegAddr; - LibAmdMemWrite (AccessWidth32, ApicAddr, &ApicRegister, StdHeader); - do { - LibAmdMemRead (AccessWidth32, ApicAddr, &ApicRegister, StdHeader); - } while ((ApicRegister & CMD_REG_DELIVERY_STATUS) != 0); - while ((ApicRegister & CMD_REG_REMOTE_RD_STS_MSK) == CMD_REG_REMOTE_DELIVERY_PENDING) { - LibAmdMemRead (AccessWidth32, ApicAddr, &ApicRegister, StdHeader); - } - } while ((ApicRegister & CMD_REG_REMOTE_RD_STS_MSK) != CMD_REG_REMOTE_DELIVERY_DONE); - ApicAddr = ApicBase + APIC_REMOTE_READ_REG; - LibAmdMemRead (AccessWidth32, ApicAddr, &ApicRegister, StdHeader); - return (ApicRegister); -} - - -/*---------------------------------------------------------------------------------------*/ -/** - * Writes an APIC register on the executing core. - * - * This function gets the base address of the executing core's local APIC, - * and writes a UINT32 value to a specified offset. - * - * @param[in] RegAddr APIC register to write to - * @param[in] Value Data to be written to the desired APIC register - * @param[in] StdHeader Configuration parameters pointer - * - */ -VOID -STATIC -ApUtilLocalWrite ( - IN UINT32 RegAddr, - IN UINT32 Value, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - UINT64 ApicAddr; - - ApUtilGetLocalApicBase (&ApicAddr, StdHeader); - ApicAddr += RegAddr; - - LibAmdMemWrite (AccessWidth32, ApicAddr, &Value, StdHeader); -} - - -/*---------------------------------------------------------------------------------------*/ -/** - * Reads an APIC register on the executing core. - * - * This function gets the base address of the executing core's local APIC, - * and reads a UINT32 value from a specified offset. - * - * @param[in] RegAddr APIC register to read from - * @param[in] StdHeader Configuration parameters pointer - * - * @return The current value of the local APIC register - * - */ -UINT32 -STATIC -ApUtilLocalRead ( - IN UINT32 RegAddr, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - UINT32 ApicRegister; - UINT64 ApicAddr; - - ApUtilGetLocalApicBase (&ApicAddr, StdHeader); - ApicAddr += RegAddr; - LibAmdMemRead (AccessWidth32, ApicAddr, &ApicRegister, StdHeader); - - return (ApicRegister); -} - - -/*---------------------------------------------------------------------------------------*/ -/** - * Returns the 64-bit base address of the executing core's local APIC. - * - * This function reads the APICBASE MSR and isolates the programmed address. - * - * @param[out] ApicBase Base address - * @param[in] StdHeader Configuration parameters pointer - * - */ -VOID -STATIC -ApUtilGetLocalApicBase ( - OUT UINT64 *ApicBase, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - LibAmdMsrRead (MSR_APIC_BAR, ApicBase, StdHeader); - *ApicBase &= (UINT64) LAPIC_BASE_ADDR_MASK; -} - - -/*---------------------------------------------------------------------------------------*/ -/** - * Determines the unique ID of the input Socket/Core. - * - * This routine converts a socket-core combination to to a number - * that will be used to directly address a particular core. This - * unique value must be less than 128 because we only have a byte - * to use for status. APIC IDs are not guaranteed to be below - * 128. - * - * @param[in] Socket Socket number of the remote core - * @param[in] Core Core number of the remote core - * @param[in] StdHeader Configuration parameters pointer - * - * @return The unique ID of the desired core - * - */ -UINT8 -STATIC -ApUtilCalculateUniqueId ( - IN UINT8 Socket, - IN UINT8 Core, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - UINT8 UniqueId; - - UniqueId = ((Core << 3) | Socket); - ASSERT ((UniqueId & 0x80) == 0); - return (UniqueId); -} - - -/*---------------------------------------------------------------------------------------*/ -/** - * Wakes up a core from the halted state. - * - * This function sends a directed NMI inter-processor interrupt to - * the input Socket/Core. - * - * @param[in] TargetApicId Local APIC ID of the desired core - * @param[in] StdHeader Configuration parameters pointer - * - */ -VOID -STATIC -ApUtilFireDirectedNmi ( - IN UINT32 TargetApicId, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - TargetApicId <<= LOCAL_APIC_ID; - - ApUtilLocalWrite ((UINT32) APIC_CMD_HI_REG, TargetApicId, StdHeader); - ApUtilLocalWrite ((UINT32) APIC_CMD_LO_REG, (UINT32) CMD_REG_TO_NMI, StdHeader); -} - - -/*---------------------------------------------------------------------------------------*/ -/** - * Securely receives a pointer from the designated remote core. - * - * This function uses a sequence of remote reads to receive a pointer, - * one UINT32 at a time. - * - * @param[in] TargetApicId Local APIC ID of the desired core - * @param[out] ReturnPointer Pointer passed from remote core - * @param[in] StdHeader Configuration parameters pointer - * - */ -VOID -STATIC -ApUtilReceivePointer ( - IN UINT32 TargetApicId, - OUT VOID **ReturnPointer, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - UINT8 i; - UINT8 WaitStatus; - UINT32 *AddressScratchPtr; - AP_WAIT_FOR_STATUS WaitForStatus; - - WaitStatus = CORE_STS_DATA_READY_0; - WaitForStatus.Status = &WaitStatus; - WaitForStatus.NumberOfElements = 1; - WaitForStatus.RetryCount = WAIT_INFINITELY; - AddressScratchPtr = (UINT32 *) ReturnPointer; - for (i = 0; i < SIZE_IN_DWORDS (AddressScratchPtr); ++i) { - ApUtilWriteControlByte (CORE_NEEDS_PTR, StdHeader); - WaitForStatus.WaitForStatusFlags = WAIT_STATUS_EQUALITY; - ApUtilWaitForCoreStatus (TargetApicId, &WaitForStatus, StdHeader); - *AddressScratchPtr++ = ApUtilReadRemoteDataDword (TargetApicId, StdHeader); - ApUtilWriteControlByte (CORE_ACTIVE, StdHeader); - WaitForStatus.WaitForStatusFlags = 0; - ApUtilWaitForCoreStatus (TargetApicId, &WaitForStatus, StdHeader); - } -} - - -/*---------------------------------------------------------------------------------------*/ -/** - * Securely transmits a pointer to the designated remote core. - * - * This function uses a sequence of remote reads to transmit a pointer, - * one UINT32 at a time. - * - * @param[in] TargetApicId Local APIC ID of the desired core - * @param[out] Pointer Pointer passed from remote core - * @param[in] StdHeader Configuration parameters pointer - * - */ -VOID -STATIC -ApUtilTransmitPointer ( - IN UINT32 TargetApicId, - IN VOID **Pointer, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - UINT8 i; - UINT8 WaitStatus; - UINT32 *AddressScratchPtr; - AP_WAIT_FOR_STATUS WaitForStatus; - - WaitStatus = CORE_NEEDS_PTR; - WaitForStatus.Status = &WaitStatus; - WaitForStatus.NumberOfElements = 1; - WaitForStatus.RetryCount = WAIT_INFINITELY; - - AddressScratchPtr = (UINT32 *) Pointer; - - for (i = 0; i < SIZE_IN_DWORDS (AddressScratchPtr); i++) { - WaitForStatus.WaitForStatusFlags = WAIT_STATUS_EQUALITY; - ApUtilWaitForCoreStatus (TargetApicId, &WaitForStatus, StdHeader); - ApUtilWriteDataDword (*AddressScratchPtr++, StdHeader); - ApUtilWriteControlByte (CORE_STS_DATA_READY_0, StdHeader); - WaitForStatus.WaitForStatusFlags = 0; - ApUtilWaitForCoreStatus (TargetApicId, &WaitForStatus, StdHeader); - ApUtilWriteControlByte (CORE_ACTIVE, StdHeader); - } -} diff --git a/src/vendorcode/amd/agesa/f12/Proc/CPU/cpuApicUtilities.h b/src/vendorcode/amd/agesa/f12/Proc/CPU/cpuApicUtilities.h deleted file mode 100644 index 59b836a356..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/CPU/cpuApicUtilities.h +++ /dev/null @@ -1,303 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * AMD CPU APIC related utility functions and structures - * - * Contains code that provides mechanism to invoke and control APIC communication. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: CPU - * @e \$Revision: 44393 $ @e \$Date: 2010-12-24 07:38:46 +0800 (Fri, 24 Dec 2010) $ - * - */ -/* - ****************************************************************************** - * - * Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - ****************************************************************************** - */ - -#ifndef _CPU_APIC_UTILITIES_H_ -#define _CPU_APIC_UTILITIES_H_ - - -/*--------------------------------------------------------------------------------------- - * M I X E D (Definitions And Macros / Typedefs, Structures, Enums) - *--------------------------------------------------------------------------------------- - */ - - -/*--------------------------------------------------------------------------------------- - * D E F I N I T I O N S A N D M A C R O S - *--------------------------------------------------------------------------------------- - */ -#define APIC_CTRL_DWORD 0xF -#define APIC_CTRL_REG (APIC_CTRL_DWORD << 4) -#define APIC_CTRL_MASK 0xFF -#define APIC_CTRL_SHIFT 0 - -#define APIC_DATA_DWORD 0x38 -#define APIC_DATA_REG (APIC_DATA_DWORD << 4) - -#define APIC_REMOTE_READ_REG 0xC0 -#define APIC_CMD_LO_REG 0x300 -#define APIC_CMD_HI_REG 0x310 - -// APIC_CMD_LO_REG bits -#define CMD_REG_DELIVERY_STATUS 0x1000 -#define CMD_REG_TO_READ 0x300 -#define CMD_REG_REMOTE_RD_STS_MSK 0x30000 -#define CMD_REG_REMOTE_DELIVERY_PENDING 0x10000 -#define CMD_REG_REMOTE_DELIVERY_DONE 0x20000 -#define CMD_REG_TO_NMI 0x400 - -// ExeFlags bits -#define WAIT_FOR_CORE 0x00000001 -#define TASK_HAS_OUTPUT 0x00000002 -#define RETURN_PARAMS 0x00000004 -#define END_AT_HLT 0x00000008 -#define PASS_EARLY_PARAMS 0x00000010 - -// Control Byte Values -// bit 7 indicates the type of message -// 1 - control message -// 0 - launch + APIC ID = message to go -// -#define CORE_UNAVAILABLE 0xFF -#define CORE_IDLE 0xFE -#define CORE_IDLE_HLT 0xFD -#define CORE_ACTIVE 0xFC -#define CORE_NEEDS_PTR 0xFB -#define CORE_NEEDS_DATA_SIZE 0xFA -#define CORE_STS_DATA_READY_1 0xF9 -#define CORE_STS_DATA_READY_0 0xF8 -#define CORE_DATA_FLAGS_READY 0xF7 -#define CORE_DATA_FLAGS_ACKNOWLEDGE 0xF6 -#define CORE_DATA_PTR_READY 0xF5 - -// Macro used to determine the number of dwords to transmit to the AP as input -#define SIZE_IN_DWORDS(sInput) ((UINT32) (((sizeof (sInput)) + 3) >> 2)) - -// IDT table -#define IDT_DESC_PRESENT 0x80 - -#define IDT_DESC_TYPE_LDT 0x02 -#define IDT_DESC_TYPE_CALL16 0x04 -#define IDT_DESC_TYPE_TASK 0x05 -#define IDT_DESC_TYPE_INT16 0x06 -#define IDT_DESC_TYPE_TRAP16 0x07 -#define IDT_DESC_TYPE_CALL32 0x0C -#define IDT_DESC_TYPE_INT32 0x0E -#define IDT_DESC_TYPE_TRAP32 0x0F -/*--------------------------------------------------------------------------------------- - * T Y P E D E F S, S T R U C T U R E S, E N U M S - *--------------------------------------------------------------------------------------- - */ -typedef VOID (*PF_AP_TASK) (AMD_CONFIG_PARAMS *StdHeader); -typedef VOID (*PF_AP_TASK_I) (VOID *, AMD_CONFIG_PARAMS *StdHeader); -typedef VOID (*PF_AP_TASK_C) (AMD_CONFIG_PARAMS *StdHeader, AMD_CPU_EARLY_PARAMS *); -typedef VOID (*PF_AP_TASK_IC) (VOID *, AMD_CONFIG_PARAMS *StdHeader, AMD_CPU_EARLY_PARAMS *); -typedef UINT32 (*PF_AP_TASK_O) (AMD_CONFIG_PARAMS *StdHeader); -typedef UINT32 (*PF_AP_TASK_IO) (VOID *, AMD_CONFIG_PARAMS *StdHeader); -typedef UINT32 (*PF_AP_TASK_OC) (AMD_CONFIG_PARAMS *StdHeader, AMD_CPU_EARLY_PARAMS *); -typedef UINT32 (*PF_AP_TASK_IOC) (VOID *, AMD_CONFIG_PARAMS *StdHeader, AMD_CPU_EARLY_PARAMS *); - -/// Function pointer union representing the eight different -/// types of functions that an AP can be asked to perform. -typedef union { - PF_AP_TASK PfApTask; ///< AMD_CONFIG_PARAMS * input with no output - PF_AP_TASK_I PfApTaskI; ///< VOID * + AMD_CONFIG_PARAMS * input with no output - PF_AP_TASK_C PfApTaskC; ///< AMD_CONFIG_PARAMS * + AMD_CPU_EARLY_PARAMS * input with no output - PF_AP_TASK_IC PfApTaskIC; ///< VOID * + AMD_CONFIG_PARAMS * + AMD_CPU_EARLY_PARAMS * input with no output - PF_AP_TASK_O PfApTaskO; ///< AMD_CONFIG_PARAMS * input with UINT32 output - PF_AP_TASK_IO PfApTaskIO; ///< VOID * + AMD_CONFIG_PARAMS * input with UINT32 output - PF_AP_TASK_OC PfApTaskOC; ///< AMD_CONFIG_PARAMS * + AMD_CPU_EARLY_PARAMS * input with UINT32 output - PF_AP_TASK_IOC PfApTaskIOC; ///< VOID * + AMD_CONFIG_PARAMS * + AMD_CPU_EARLY_PARAMS * input with UINT32 output -} AP_FUNCTION_PTR; - -/// Input structure for ApUtilTransmitBuffer and ApUtilReceiveBuffer -/// containing information about the data transfer from one core -/// to another. -typedef struct { - IN OUT UINT16 DataSizeInDwords; ///< Size of the data to be transferred rounded up to the nearest dword - IN OUT VOID *DataPtr; ///< Pointer to the data - IN UINT32 DataTransferFlags; ///< Flags dictating certain aspects of the data transfer -} AP_DATA_TRANSFER; - -/// Input structure for ApUtilRunCodeOnSocketCore. -typedef struct _AP_TASK { - AP_FUNCTION_PTR FuncAddress; ///< Pointer to the function that the AP will run - AP_DATA_TRANSFER DataTransfer; ///< Data transfer struct for optionally passing data that the AP should use as input to the function - UINT32 ExeFlags; ///< Flags dictating certain aspects of the AP tasking sequence -} AP_TASK; - -/// Input structure for ApUtilWaitForCoreStatus. -typedef struct { - IN UINT8 *Status; ///< Pointer to the 1st element of an array of values to wait for - IN UINT8 NumberOfElements; ///< Number of elements in the array - IN UINT32 RetryCount; ///< Number of remote read cycles to complete before quitting - IN UINT32 WaitForStatusFlags; ///< Flags dictating certain aspects of ApUtilWaitForCoreStatus -} AP_WAIT_FOR_STATUS; - -/// Interrupt Descriptor Table entry -typedef struct { - UINT16 OffsetLo; ///< Lower 16 bits of the interrupt handler routine's offset - UINT16 Selector; ///< Interrupt handler routine's selector - UINT8 Rsvd; ///< Reserved - UINT8 Flags; ///< Interrupt flags - UINT16 OffsetHi; ///< Upper 16 bits of the interrupt handler routine's offset - UINT32 Offset64; ///< High order 32 bits of the handler's offset needed when in 64 bit mode - UINT32 Rsvd64; ///< Reserved -} IDT_DESCRIPTOR; - -/// Structure needed to load the IDTR using the lidt instruction -typedef struct { - UINT16 Limit; ///< Interrupt Descriptor Table size - UINT64 Base; ///< Interrupt Descriptor Table base address -} IDT_BASE_LIMIT; - -#define WAIT_STATUS_EQUALITY 0x00000001 -#define WAIT_INFINITELY 0 - -// Data Transfer Flags -#define DATA_IN_MEMORY 0x00000001 - - -/*--------------------------------------------------------------------------------------- - * F U N C T I O N P R O T O T Y P E - *--------------------------------------------------------------------------------------- - */ -// These are P U B L I C functions, used by AGESA -UINT8 -ApUtilReadRemoteControlByte ( - IN UINT32 TargetApicId, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -VOID -ApUtilWriteControlByte ( - IN UINT8 Value, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -UINT32 -ApUtilReadRemoteDataDword ( - IN UINT32 TargetApicId, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -VOID -ApUtilWriteDataDword ( - IN UINT32 Value, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -UINT32 -ApUtilRunCodeOnSocketCore ( - IN UINT8 Socket, - IN UINT8 Core, - IN AP_TASK *TaskPtr, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -UINT8 -ApUtilWaitForCoreStatus ( - IN UINT32 TargetApicId, - IN AP_WAIT_FOR_STATUS *WaitParamsPtr, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -VOID -ApEntry ( - IN AMD_CONFIG_PARAMS *StdHeader, - IN AMD_CPU_EARLY_PARAMS *CpuEarlyParams - ); - -UINT32 -ApUtilTaskOnExecutingCore ( - IN AP_TASK *TaskPtr, - IN AMD_CONFIG_PARAMS *StdHeader, - IN VOID *ConfigParams - ); - -VOID -ApUtilTransmitBuffer ( - IN UINT8 Socket, - IN UINT8 Core, - IN AP_DATA_TRANSFER *BufferInfo, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -AGESA_STATUS -ApUtilReceiveBuffer ( - IN UINT8 Socket, - IN UINT8 Core, - IN OUT AP_DATA_TRANSFER *BufferInfo, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -VOID -GetLocalApicIdForCore ( - IN UINT32 TargetSocket, - IN UINT32 TargetCore, - OUT UINT32 *LocalApicId, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -VOID -ApUtilRunCodeOnAllLocalCoresAtEarly ( - IN AP_TASK *TaskPtr, - IN AMD_CONFIG_PARAMS *StdHeader, - IN AMD_CPU_EARLY_PARAMS *CpuEarlyParamsPtr - ); - -VOID -RelinquishControlOfAllAPs ( - IN AMD_CONFIG_PARAMS *StdHeader - ); - -VOID -GetCsSelector ( - IN UINT16 *Selector, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -VOID -SetIdtr ( - IN IDT_BASE_LIMIT *IdtInfo, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -VOID -GetIdtr ( - IN IDT_BASE_LIMIT *IdtInfo, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -#endif /* _CPU_APIC_UTILITIES_H_ */ - diff --git a/src/vendorcode/amd/agesa/f12/Proc/CPU/cpuBist.c b/src/vendorcode/amd/agesa/f12/Proc/CPU/cpuBist.c deleted file mode 100644 index a86aa2e01a..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/CPU/cpuBist.c +++ /dev/null @@ -1,171 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * AMD CPU BIST Status Check Implementation. - * - * Implement CPU BIST Status checking - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: CPU - * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $ - * - */ -/* - ****************************************************************************** - * - * Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - ****************************************************************************** - */ - -/*---------------------------------------------------------------------------------------- - * M O D U L E S U S E D - *---------------------------------------------------------------------------------------- - */ -#include "AGESA.h" -#include "amdlib.h" -#include "Ids.h" -#include "cpuRegisters.h" -#include "GeneralServices.h" -#include "cpuServices.h" -#include "cpuApicUtilities.h" -#include "Filecode.h" -CODE_GROUP (G1_PEICC) -RDATA_GROUP (G1_PEICC) -#define FILECODE PROC_CPU_CPUBIST_FILECODE - -/*---------------------------------------------------------------------------------------- - * P R O T O T Y P E S O F L O C A L F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ - -UINT32 -STATIC -GetBistResults ( - IN AMD_CONFIG_PARAMS *StdHeader - ); - - /*---------------------------------------------------------------------------------------- - * E X P O R T E D F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ - - /*---------------------------------------------------------------------------------------*/ - /** - * - * This function checks the status of BIST and places the error status in the event log - * if there are any errors - * - * @param[in] StdHeader Header for library and services - * - * @retval AGESA_SUCCESS No BIST errors have been logged. - * @retval AGESA_ALERT BIST errors have been detected and added to the - * event log. - */ -AGESA_STATUS -CheckBistStatus ( - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - UINT32 Socket; - UINT32 Core; - UINT32 BscSocket; - UINT32 BscCoreNum; - UINT32 NumberOfSockets; - UINT32 NumberOfCores; - UINT32 Ignored; - UINT32 ReturnCode; - AGESA_STATUS IgnoredSts; - AGESA_STATUS AgesaStatus; - AP_TASK TaskPtr; - - // Make sure that Standard Header is valid - ASSERT (StdHeader != NULL); - ASSERT (IsBsp (StdHeader, &IgnoredSts)); - - AgesaStatus = AGESA_SUCCESS; - - // Get the BscSocket, BscCoreNum and NumberOfSockets in the system - IdentifyCore (StdHeader, &BscSocket, &Ignored, &BscCoreNum, &IgnoredSts); - NumberOfSockets = GetPlatformNumberOfSockets (); - - // Setup TaskPtr struct to execute routine on APs - TaskPtr.FuncAddress.PfApTaskO = GetBistResults; - TaskPtr.DataTransfer.DataSizeInDwords = 0; - TaskPtr.ExeFlags = TASK_HAS_OUTPUT | WAIT_FOR_CORE; - - for (Socket = 0; Socket < NumberOfSockets; Socket++) { - if (GetActiveCoresInGivenSocket (Socket, &NumberOfCores, StdHeader)) { - for (Core = 0; Core < NumberOfCores; Core++) { - if ((Socket != BscSocket) || (Core != BscCoreNum)) { - ReturnCode = ApUtilRunCodeOnSocketCore ((UINT8)Socket, (UINT8)Core, &TaskPtr, StdHeader); - } else { - ReturnCode = TaskPtr.FuncAddress.PfApTaskO (StdHeader); - } - - // If BIST value is non-zero, add to BSP's event log - if (ReturnCode != 0) { - IDS_HDT_CONSOLE (CPU_TRACE, " BIST failure: socket %d core %d, status = 0x%x\n", Socket, Core, ReturnCode); - AgesaStatus = AGESA_ALERT; - PutEventLog (AGESA_ALERT, - CPU_EVENT_BIST_ERROR, - ReturnCode, Socket, Core, 0, StdHeader); - } - } - } - } - - return AgesaStatus; -} - -/*---------------------------------------------------------------------------------------- - * L O C A L F U N C T I O N S - *---------------------------------------------------------------------------------------- -*/ - -/*---------------------------------------------------------------------------------------*/ -/** - * - * Reads the lower 32 bits of the BIST register - * - * @param[in] StdHeader Header for library and services - * - * @retval Value of the BIST register -*/ -UINT32 -STATIC -GetBistResults ( - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - UINT64 BistResults; - - // Read MSRC001_0060 BIST Results Register - LibAmdMsrRead (MSR_BIST, &BistResults, StdHeader); - - return (UINT32) (BistResults & 0xFFFFFFFF); -} diff --git a/src/vendorcode/amd/agesa/f12/Proc/CPU/cpuBrandId.c b/src/vendorcode/amd/agesa/f12/Proc/CPU/cpuBrandId.c deleted file mode 100644 index a33513947b..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/CPU/cpuBrandId.c +++ /dev/null @@ -1,312 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * AMD CPU BrandId related functions. - * - * Contains code that provides CPU BrandId information - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: CPU - * @e \$Revision: 44870 $ @e \$Date: 2011-01-08 14:23:12 +0800 (Sat, 08 Jan 2011) $ - * - */ -/***************************************************************************** - * - * Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - ****************************************************************************** - */ - -/*---------------------------------------------------------------------------------------- - * M O D U L E S U S E D - *---------------------------------------------------------------------------------------- - */ -#include "AGESA.h" -#include "amdlib.h" -#include "OptionPstate.h" -#include "cpuRegisters.h" -#include "cpuFamilyTranslation.h" -#include "cpuEarlyInit.h" -#include "cpuRegisters.h" -#include "heapManager.h" -#include "GeneralServices.h" -#include "Filecode.h" -CODE_GROUP (G1_PEICC) -RDATA_GROUP (G1_PEICC) -#define FILECODE PROC_CPU_CPUBRANDID_FILECODE -/*---------------------------------------------------------------------------------------- - * D E F I N I T I O N S A N D M A C R O S - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------- - * T Y P E D E F S A N D S T R U C T U R E S - *---------------------------------------------------------------------------------------- - */ -CONST CHAR8 ROMDATA strEngSample[] = "AMD Engineering Sample"; -CONST CHAR8 ROMDATA strTtkSample[] = "AMD Thermal Test Kit"; -CONST CHAR8 ROMDATA strUnknown[] = "AMD Processor Model Unknown"; - -CONST AMD_CPU_BRAND ROMDATA EngSample_Str = {0, 0, 0, SOCKET_IGNORE, strEngSample, sizeof (strEngSample)}; -CONST AMD_CPU_BRAND ROMDATA TtkSample_Str = {0, 1, 0, SOCKET_IGNORE, strTtkSample, sizeof (strTtkSample)}; -CONST AMD_CPU_BRAND ROMDATA Dflt_Str1 = {0, 0, 0, SOCKET_IGNORE, strUnknown, sizeof (strUnknown)}; -CONST AMD_CPU_BRAND ROMDATA Dflt_Str2 = {0, 0, 0, SOCKET_IGNORE, DR_NO_STRING, DR_NO_STRING}; - - -/*---------------------------------------------------------------------------------------- - * P R O T O T Y P E S O F L O C A L F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------- - * E X P O R T E D F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ -VOID -SetBrandIdRegistersAtEarly ( - IN CPU_SPECIFIC_SERVICES *FamilyServices, - IN AMD_CPU_EARLY_PARAMS *EarlyParams, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -/*---------------------------------------------------------------------------------------*/ -/** - * Program BrandID registers (CPUIDNameStringPtr[0-5]) - * - * This function determines the appropriate brand string for the executing - * core, and programs the namestring MSRs. - * - * @param[in,out] StdHeader Config handle for library and services. - * - */ -VOID -SetBrandIdRegisters ( - IN OUT AMD_CONFIG_PARAMS *StdHeader - ) -{ - UINT8 SocketIndex; - UINT8 SuffixStatus; - UINT8 TableElements; - UINT8 TableEntryCount; - UINT8 TableEntryIndex; - CHAR8 TempChar; - CHAR8 *NameStringPtr; - CHAR8 *SuffixStringPtr; - CHAR8 *BrandStringPtr; - CHAR8 *TempNameCharPtr; - UINT32 MsrIndex; - UINT32 Quotient; - UINT32 Remainder; - UINT64 *MsrNameStringPtrPtr; - CPUID_DATA CpuId; - CPU_LOGICAL_ID CpuLogicalId; - CPU_BRAND_TABLE *SocketTableEntry; - CPU_BRAND_TABLE **SocketTableEntry1; - AMD_CPU_BRAND *SocketTablePtr; - AMD_CPU_BRAND_DATA Data; - ALLOCATE_HEAP_PARAMS AllocHeapParams; - CPU_SPECIFIC_SERVICES *FamilySpecificServices; - - SuffixStatus = 0; - FamilySpecificServices = NULL; - SocketTablePtr = NULL; - SocketTableEntry = NULL; - - GetCpuServicesOfCurrentCore ((const CPU_SPECIFIC_SERVICES **)&FamilySpecificServices, StdHeader); - // Step1: Allocate 48 bytes from Heap space - AllocHeapParams.RequestedBufferSize = CPU_BRAND_ID_LENGTH; - AllocHeapParams.BufferHandle = AMD_BRAND_ID_BUFFER_HANDLE; - AllocHeapParams.Persist = HEAP_LOCAL_CACHE; - if (HeapAllocateBuffer (&AllocHeapParams, StdHeader) == AGESA_SUCCESS) { - // Clear NameBuffer - BrandStringPtr = (CHAR8 *) AllocHeapParams.BufferPtr; - LibAmdMemFill (BrandStringPtr, 0, CPU_BRAND_ID_LENGTH, StdHeader); - } else { - PutEventLog ( - AGESA_ERROR, - CPU_ERROR_BRANDID_HEAP_NOT_AVAILABLE, - 0, 0, 0, 0, StdHeader - ); - return; - } - - // Step2: Get brandid from model number and model string - LibAmdCpuidRead (AMD_CPUID_FMF, &CpuId, StdHeader); - - // Step3: Figure out Socket/Page/Model/String1/String2/Core Number - Data.String2 = (UINT8) (CpuId.EBX_Reg & 0x0f); - Data.Model = (UINT8) ((CpuId.EBX_Reg >> 4) & 0x7f); - Data.String1 = (UINT8) ((CpuId.EBX_Reg >> 11) & 0x0f); - Data.Page = (UINT8) ((CpuId.EBX_Reg >> 15) & 0x01); - Data.Socket = (UINT8) ((CpuId.EBX_Reg >> 28) & 0x0f); - Data.Cores = FamilySpecificServices->GetNumberOfPhysicalCores (FamilySpecificServices, StdHeader); - - // Step4: If NN = 0, we have an engineering sample, no suffix; then jump to Step6 - if (Data.Model == 0) { - if (Data.Page == 0) { - SocketTablePtr = (AMD_CPU_BRAND *)&EngSample_Str; - } else { - SocketTablePtr = (AMD_CPU_BRAND *)&TtkSample_Str; - } - } else { - - // Model is not equal to zero, so decrement it - // For family 10 if PkgType[3:0] is greater than or equal to 2h and families >= 12h - GetLogicalIdOfCurrentCore (&CpuLogicalId, StdHeader); - if ((((CpuLogicalId.Family & AMD_FAMILY_10) != 0) && (Data.Socket >= DR_SOCKET_S1G3)) || - ((CpuLogicalId.Family & AMD_FAMILY_GE_12) != 0)) { - Data.Model--; - } - - // Step5: Search for String1 (there can be only 1) - FamilySpecificServices->GetBrandString1 (FamilySpecificServices, (const VOID **) &SocketTableEntry, &TableEntryCount, StdHeader); - SocketTableEntry1 = (CPU_BRAND_TABLE **) SocketTableEntry; - for (TableEntryIndex = 0; ((TableEntryIndex < TableEntryCount) - && (SuffixStatus == 0)); TableEntryIndex++, SocketTableEntry1++) { - if (*SocketTableEntry1 == NULL) { - break; - } - SocketTablePtr = (AMD_CPU_BRAND *) (*SocketTableEntry1)->Table; - TableElements = (*SocketTableEntry1)->NumberOfEntries; - for (SocketIndex = 0; (SocketIndex < TableElements) - && SuffixStatus == 0; SocketIndex++) { - if ((SocketTablePtr->Page == Data.Page) && - (SocketTablePtr->Index == Data.String1) && - (SocketTablePtr->Socket == Data.Socket) && - (SocketTablePtr->Cores == Data.Cores)) { - SuffixStatus = 1; - } else { - SocketTablePtr++; - } - } - } - if (SuffixStatus == 0) { - SocketTablePtr = (AMD_CPU_BRAND *)&Dflt_Str1; // We did not find one, make 'Unknown' - } - } - - // Step6: Copy String into NameBuffer - // We now have data structure pointing to correct type in (*SocketTablePtr) - LibAmdMemCopy (BrandStringPtr, - (CHAR8 *)SocketTablePtr->Stringstart, - SocketTablePtr->Stringlength, - StdHeader); - - // Step7: Get suffix, determine addition to BRANDSPEED - if (SuffixStatus != 0) { - // Turn our value into a decimal string - // We have a value like 37d which we need to turn into '3' '7' - // Divide by 10, store remainder as an ASCII char on stack, repeat until Quotient is 0 - NameStringPtr = BrandStringPtr + SocketTablePtr->Stringlength - 1; - TempNameCharPtr = NameStringPtr; - Quotient = Data.Model; - do { - Remainder = Quotient % 10; - Quotient = Quotient / 10; - *TempNameCharPtr++ = (CHAR8) (Remainder + '0'); // Put suffix into our NameBuffer - } while (Quotient != 0); - if (Data.Model < 10) { - *TempNameCharPtr++ = '0'; - } - - // Step8: Reverse the string sequence and copy into NameBuffer - SuffixStringPtr = TempNameCharPtr--; - while (NameStringPtr < TempNameCharPtr) { - TempChar = *NameStringPtr; - *NameStringPtr = *TempNameCharPtr; - *TempNameCharPtr = TempChar; - NameStringPtr++; - TempNameCharPtr--; - } - - // Step9: Search for String2 - SuffixStatus = 0; - FamilySpecificServices->GetBrandString2 (FamilySpecificServices, (const VOID **) &SocketTableEntry, &TableEntryCount, StdHeader); - SocketTableEntry1 = (CPU_BRAND_TABLE **) SocketTableEntry; - for (TableEntryIndex = 0; ((TableEntryIndex < TableEntryCount) - && (SuffixStatus == 0)); TableEntryIndex++, SocketTableEntry1++) { - if (*SocketTableEntry1 == NULL) { - break; - } - SocketTablePtr = (AMD_CPU_BRAND *) (*SocketTableEntry1)->Table; - TableElements = (*SocketTableEntry1)->NumberOfEntries; - for (SocketIndex = 0; (SocketIndex < TableElements) - && SuffixStatus == 0; SocketIndex++) { - if ((SocketTablePtr->Page == Data.Page) && - (SocketTablePtr->Index == Data.String2) && - (SocketTablePtr->Socket == Data.Socket) && - (SocketTablePtr->Cores == Data.Cores)) { - SuffixStatus = 1; - } else { - SocketTablePtr++; - } - } - } - if (SuffixStatus == 0) { - SocketTablePtr = (AMD_CPU_BRAND *)&Dflt_Str2; - } - - // Step10: Copy String2 into our NameBuffer - if (SocketTablePtr->Stringlength != 0) { - LibAmdMemCopy (SuffixStringPtr, - (CHAR8 *)SocketTablePtr->Stringstart, - SocketTablePtr->Stringlength, - StdHeader); - } - } - - // Step11: Put values into name MSRs, Always write the full 48 bytes - MsrNameStringPtrPtr = (UINT64 *) BrandStringPtr; - for (MsrIndex = MSR_CPUID_NAME_STRING0; MsrIndex <= MSR_CPUID_NAME_STRING5; MsrIndex++) { - LibAmdMsrWrite (MsrIndex, MsrNameStringPtrPtr, StdHeader); - MsrNameStringPtrPtr++; - } - HeapDeallocateBuffer (AMD_BRAND_ID_BUFFER_HANDLE, StdHeader); -} - -/*---------------------------------------------------------------------------------------*/ -/** - * Program BrandID registers (CPUIDNameStringPtr[0-5]) - * - * This function acts as a wrapper for calling the SetBrandIdRegisters - * routine at AmdInitEarly. - * - * @param[in] FamilyServices The current Family Specific Services. - * @param[in] EarlyParams Service parameters. - * @param[in] StdHeader Config handle for library and services. - * - */ -VOID -SetBrandIdRegistersAtEarly ( - IN CPU_SPECIFIC_SERVICES *FamilyServices, - IN AMD_CPU_EARLY_PARAMS *EarlyParams, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - AGESA_TESTPOINT (TpProcCpuSetBrandID, StdHeader); - SetBrandIdRegisters (StdHeader); -} diff --git a/src/vendorcode/amd/agesa/f12/Proc/CPU/cpuEarlyInit.c b/src/vendorcode/amd/agesa/f12/Proc/CPU/cpuEarlyInit.c deleted file mode 100644 index 5a3e4eb86e..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/CPU/cpuEarlyInit.c +++ /dev/null @@ -1,422 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * AMD CPU Reset API, and related functions. - * - * Contains code that initialized the CPU after early reset. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: CPU - * @e \$Revision: 49711 $ @e \$Date: 2011-03-28 20:19:38 +0800 (Mon, 28 Mar 2011) $ - * - */ -/* - ****************************************************************************** - * - * Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - ****************************************************************************** - */ - -/*---------------------------------------------------------------------------------------- - * M O D U L E S U S E D - *---------------------------------------------------------------------------------------- - */ -#include "AGESA.h" -#include "amdlib.h" -#include "Ids.h" -#include "cpuRegisters.h" -#include "cpuServices.h" -#include "GeneralServices.h" -#include "Table.h" -#include "cpuApicUtilities.h" -#include "cpuEarlyInit.h" -#include "Topology.h" -#include "cpuFamilyTranslation.h" -#include "cpuFeatures.h" -#include "Filecode.h" -CODE_GROUP (G1_PEICC) -RDATA_GROUP (G1_PEICC) - -#define FILECODE PROC_CPU_CPUEARLYINIT_FILECODE - - -/*---------------------------------------------------------------------------------------- - * D E F I N I T I O N S A N D M A C R O S - *---------------------------------------------------------------------------------------- - */ -extern BUILD_OPT_CFG UserOptions; -/*---------------------------------------------------------------------------------------- - * T Y P E D E F S A N D S T R U C T U R E S - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------- - * P R O T O T Y P E S O F L O C A L F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ -VOID -AmdCpuEarlyInitializer ( - IN AMD_CONFIG_PARAMS *StdHeader, - IN PLATFORM_CONFIGURATION *PlatformConfig, - IN OUT AMD_CPU_EARLY_PARAMS *CpuEarlyParamsPtr - ); - -VOID -McaInitialization ( - IN AMD_CONFIG_PARAMS *StdHeader - ); - -VOID -STATIC -GetPerformEarlyFlag ( - IN OUT UINT32 *PerformEarlyFlag, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -/*---------------------------------------------------------------------------------------- - * E X P O R T E D F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ -VOID -McaInitializationAtEarly ( - IN CPU_SPECIFIC_SERVICES *FamilyServices, - IN AMD_CPU_EARLY_PARAMS *EarlyParams, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -/*------------------------------------------------------------------------------------*/ -/** - * Initializer routine that will be invoked by AmdCpuEarly to initialize the input - * structure for the Cpu Init @ Early routine. - * - * @param[in] StdHeader Opaque handle to standard config header - * @param[in] PlatformConfig Config handle for platform specific information - * @param[in,out] CpuEarlyParamsPtr Service Interface structure to initialize. - * - * @retval AGESA_SUCCESS Always Succeeds - */ -VOID -AmdCpuEarlyInitializer ( - IN AMD_CONFIG_PARAMS *StdHeader, - IN PLATFORM_CONFIGURATION *PlatformConfig, - IN OUT AMD_CPU_EARLY_PARAMS *CpuEarlyParamsPtr - ) -{ - ASSERT (CpuEarlyParamsPtr != NULL); - - CpuEarlyParamsPtr->MemInitPState = (UINT8) UserOptions.CfgMemInitPstate; - CpuEarlyParamsPtr->PlatformConfig = *PlatformConfig; -} -/*---------------------------------------------------------------------------------------*/ -/** - * Performs CPU related initialization at the early entry point - * - * This function performs a large list of initialization items. These items - * include: - * - * -1 local APIC initialization - * -2 MSR table initialization - * -3 PCI table initialization - * -4 HT Phy PCI table initialization - * -5 microcode patch loading - * -6 namestring determination/programming - * -7 AP initialization - * -8 power management initialization - * -9 core leveling - * - * This routine must be run by all cores in the system. Please note that - * all APs that enter will never exit. - * - * @param[in] StdHeader Config handle for library and services - * @param[in] PlatformConfig Config handle for platform specific information - * - * @retval AGESA_SUCCESS - * - */ -AGESA_STATUS -AmdCpuEarly ( - IN AMD_CONFIG_PARAMS *StdHeader, - IN PLATFORM_CONFIGURATION *PlatformConfig - ) -{ - UINT8 WaitStatus; - UINT8 i; - UINT8 StartCore; - UINT8 EndCore; - UINT32 NodeNum; - UINT32 PrimaryCore; - UINT32 SocketNum; - UINT32 ModuleNum; - UINT32 HighCore; - UINT32 ApHeapIndex; - UINT32 CurrentPerformEarlyFlag; - UINT32 TargetApicId; - AP_WAIT_FOR_STATUS WaitForStatus; - AGESA_STATUS Status; - AGESA_STATUS CalledStatus; - CPU_SPECIFIC_SERVICES *FamilySpecificServices; - AMD_CPU_EARLY_PARAMS CpuEarlyParams; - S_PERFORM_EARLY_INIT_ON_CORE *EarlyTableOnCore; - - Status = AGESA_SUCCESS; - CalledStatus = AGESA_SUCCESS; - - AmdCpuEarlyInitializer (StdHeader, PlatformConfig, &CpuEarlyParams); - - IDS_OPTION_HOOK (IDS_CPU_Early_Override, &CpuEarlyParams, StdHeader); - - GetCpuServicesOfCurrentCore ((const CPU_SPECIFIC_SERVICES **)&FamilySpecificServices, StdHeader); - EarlyTableOnCore = NULL; - FamilySpecificServices->GetEarlyInitOnCoreTable (FamilySpecificServices, (const S_PERFORM_EARLY_INIT_ON_CORE **)&EarlyTableOnCore, &CpuEarlyParams, StdHeader); - if (EarlyTableOnCore != NULL) { - GetPerformEarlyFlag (&CurrentPerformEarlyFlag, StdHeader); - for (i = 0; EarlyTableOnCore[i].PerformEarlyInitOnCore != NULL; i++) { - if ((EarlyTableOnCore[i].PerformEarlyInitFlag & CurrentPerformEarlyFlag) != 0) { - IDS_HDT_CONSOLE (CPU_TRACE, " Perform core init step %d\n", i); - EarlyTableOnCore[i].PerformEarlyInitOnCore (FamilySpecificServices, &CpuEarlyParams, StdHeader); - } - } - } - - // B S P C O D E T O I N I T I A L I Z E A Ps - // ------------------------------------------------------- - // ------------------------------------------------------- - // IMPORTANT: Here we determine if we are BSP or AP - if (IsBsp (StdHeader, &CalledStatus)) { - - // Even though the bsc does not need to send itself a heap index, this sequence performs other important initialization. - // Use '0' as a dummy heap index value. - GetSocketModuleOfNode (0, &SocketNum, &ModuleNum, StdHeader); - GetCpuServicesOfSocket (SocketNum, (const CPU_SPECIFIC_SERVICES **)&FamilySpecificServices, StdHeader); - FamilySpecificServices->SetApCoreNumber (FamilySpecificServices, SocketNum, ModuleNum, 0, StdHeader); - FamilySpecificServices->TransferApCoreNumber (FamilySpecificServices, StdHeader); - - // Clear BSP's Status Byte - ApUtilWriteControlByte (CORE_ACTIVE, StdHeader); - - NodeNum = 0; - ApHeapIndex = 1; - while (NodeNum < MAX_NODES && - GetSocketModuleOfNode (NodeNum, &SocketNum, &ModuleNum, StdHeader)) { - GetCpuServicesOfSocket (SocketNum, (const CPU_SPECIFIC_SERVICES **)&FamilySpecificServices, StdHeader); - GetGivenModuleCoreRange (SocketNum, ModuleNum, &PrimaryCore, &HighCore, StdHeader); - if (NodeNum == 0) { - StartCore = (UINT8) PrimaryCore + 1; - } else { - StartCore = (UINT8) PrimaryCore; - } - - EndCore = (UINT8) HighCore; - for (i = StartCore; i <= EndCore; i++) { - FamilySpecificServices->SetApCoreNumber (FamilySpecificServices, SocketNum, ModuleNum, ApHeapIndex, StdHeader); - IDS_HDT_CONSOLE (CPU_TRACE, " Launch socket %d core %d\n", SocketNum, i); - if (FamilySpecificServices->LaunchApCore (FamilySpecificServices, SocketNum, ModuleNum, i, PrimaryCore, StdHeader)) { - IDS_HDT_CONSOLE (CPU_TRACE, " Waiting for socket %d core %d\n", SocketNum, i); - GetLocalApicIdForCore (SocketNum, i, &TargetApicId, StdHeader); - WaitStatus = CORE_IDLE; - WaitForStatus.Status = &WaitStatus; - WaitForStatus.NumberOfElements = 1; - WaitForStatus.RetryCount = WAIT_INFINITELY; - WaitForStatus.WaitForStatusFlags = WAIT_STATUS_EQUALITY; - ApUtilWaitForCoreStatus (TargetApicId, &WaitForStatus, StdHeader); - ApHeapIndex++; - } - } - NodeNum++; - } - - // B S P P h a s e - 1 E N D - - IDS_OPTION_HOOK (IDS_BEFORE_PM_INIT, &CpuEarlyParams, StdHeader); - - AGESA_TESTPOINT (TpProcCpuBeforePMFeatureInit, StdHeader); - IDS_HDT_CONSOLE (CPU_TRACE, " Dispatch CPU features before early power mgmt init\n"); - CalledStatus = DispatchCpuFeatures (CPU_FEAT_BEFORE_PM_INIT, PlatformConfig, StdHeader); - if (CalledStatus > Status) { - Status = CalledStatus; - } - - AGESA_TESTPOINT (TpProcCpuPowerMgmtInit, StdHeader); - CalledStatus = PmInitializationAtEarly (&CpuEarlyParams, StdHeader); - if (CalledStatus > Status) { - Status = CalledStatus; - } - - AGESA_TESTPOINT (TpProcCpuEarlyFeatureInit, StdHeader); - IDS_HDT_CONSOLE (CPU_TRACE, " Dispatch CPU features after early power mgmt init\n"); - CalledStatus = DispatchCpuFeatures (CPU_FEAT_AFTER_PM_INIT, PlatformConfig, StdHeader); - - IDS_OPTION_HOOK (IDS_BEFORE_AP_EARLY_HALT, &CpuEarlyParams, StdHeader); - - // Sleep all APs - IDS_HDT_CONSOLE (CPU_TRACE, " Halting all APs\n"); - ApUtilWriteControlByte (CORE_IDLE_HLT, StdHeader); - } // if (amdIsBsp()) - END - else { - ApEntry (StdHeader, &CpuEarlyParams); - } - - if (CalledStatus > Status) { - Status = CalledStatus; - } - - return (Status); -} - -/*--------------------------------------------------------------------------------------- - * L O C A L F U N C T I O N S - *--------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------*/ -/** - * Initialize Machine Check Architecture registers - * - * This function initializes the MCA MSRs. On cold reset, these registers - * have an invalid data that must be cleared on all cores. - * - * @param[in] StdHeader Config handle for library and services - * - *--------------------------------------------------------------------------------------- - */ -VOID -McaInitialization ( - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - UINT16 TempVar16_a; - UINT32 MsrAddress; - UINT64 MsrData; - CPUID_DATA CpuIdDataStruct; - - if (!(IsWarmReset (StdHeader))) { - // Run CPUID to verify that the processor supports MCE and MCA - // i.e. edx[7], and edx[14] - // CPUID_MODEL = 1 - LibAmdCpuidRead (1, &CpuIdDataStruct, StdHeader); - if ((CpuIdDataStruct.EDX_Reg & 0x4080) != 0) { - // Check to see if the MCG_CTL_P bit is set - // MCG = Global Machine Check Exception Reporting Control Register - LibAmdMsrRead (MSR_MCG_CAP, &MsrData, StdHeader); - if ((MsrData & MCG_CTL_P) != 0) { - TempVar16_a = (UINT16) ((MsrData & 0x000000FF) << 2); - TempVar16_a += MSR_MC0_CTL; - - // Initialize the data - MsrData = 0; - for (MsrAddress = MSR_MC0_CTL; MsrAddress < TempVar16_a; MsrAddress++) { - LibAmdMsrWrite (MsrAddress, &MsrData, StdHeader); - } - } - } - } -} - - -/*---------------------------------------------------------------------------------------*/ -/** - * Initialize Machine Check Architecture registers - * - * This function acts as a wrapper for calling the McaInitialization - * routine at AmdInitEarly. - * - * @param[in] FamilyServices The current Family Specific Services. - * @param[in] EarlyParams Service parameters. - * @param[in] StdHeader Config handle for library and services. - * - */ -VOID -McaInitializationAtEarly ( - IN CPU_SPECIFIC_SERVICES *FamilyServices, - IN AMD_CPU_EARLY_PARAMS *EarlyParams, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - McaInitialization (StdHeader); -} - -/*---------------------------------------------------------------------------------------*/ -/** - * Runs the given task on all cores (including self) on the socket of the executing - * core 0. - * - * This function is used to invoke all APs on the socket of the executing core 0 to - * run a specified AGESA procedure. - * - * @param[in] TaskPtr Function descriptor - * @param[in] StdHeader Config handle for library and services - * @param[in] CpuEarlyParamsPtr Required input parameters for early CPU initialization - * - */ -VOID -ApUtilRunCodeOnAllLocalCoresAtEarly ( - IN AP_TASK *TaskPtr, - IN AMD_CONFIG_PARAMS *StdHeader, - IN AMD_CPU_EARLY_PARAMS *CpuEarlyParamsPtr - ) -{ - UINT32 Core; - UINT32 Socket; - UINT32 IgnoredModule; - UINT32 IgnoredCore; - UINT32 ActiveCores; - AGESA_STATUS IgnoredSts; - - IdentifyCore (StdHeader, &Socket, &IgnoredModule, &IgnoredCore, &IgnoredSts); - GetActiveCoresInCurrentSocket (&ActiveCores, StdHeader); - - for (Core = 1; Core < (UINT8) ActiveCores; ++Core) { - ApUtilRunCodeOnSocketCore ((UINT8)Socket, (UINT8)Core, TaskPtr, StdHeader); - } - ApUtilTaskOnExecutingCore (TaskPtr, StdHeader, (VOID *) CpuEarlyParamsPtr); -} - -/*---------------------------------------------------------------------------------------*/ -/** - * Get current condition, such as warm/cold reset, to determine if related function - * need to be performed at early stage - * - * @param[in, out] PerformEarlyFlag Perform early flag. - * @param[in] StdHeader Config handle for library and services. - * - */ -VOID -STATIC -GetPerformEarlyFlag ( - IN OUT UINT32 *PerformEarlyFlag, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - *PerformEarlyFlag = 0; - if (IsWarmReset (StdHeader)) { - *PerformEarlyFlag |= PERFORM_EARLY_WARM_RESET; - } else { - *PerformEarlyFlag |= PERFORM_EARLY_COLD_BOOT; - } - return; -} diff --git a/src/vendorcode/amd/agesa/f12/Proc/CPU/cpuEarlyInit.h b/src/vendorcode/amd/agesa/f12/Proc/CPU/cpuEarlyInit.h deleted file mode 100644 index 0cda4ad48e..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/CPU/cpuEarlyInit.h +++ /dev/null @@ -1,248 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * AMD CPU Reset API, and related functions and structures. - * - * Contains code that initialized the CPU after early reset. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: CPU - * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $ - * - */ -/* - ****************************************************************************** - * - * Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - ****************************************************************************** - */ - -#ifndef _CPU_EARLY_INIT_H_ -#define _CPU_EARLY_INIT_H_ - - -/*--------------------------------------------------------------------------------------- - * M I X E D (Definitions And Macros / Typedefs, Structures, Enums) - *--------------------------------------------------------------------------------------- - */ -AGESA_FORWARD_DECLARATION (CPU_CORE_LEVELING_FAMILY_SERVICES); - -/*--------------------------------------------------------------------------------------- - * D E F I N I T I O N S A N D M A C R O S - *--------------------------------------------------------------------------------------- - */ -//---------------------------------------------------------------------------- -// CPU BRAND ID TYPEDEFS, STRUCTURES, ENUMS -// -//---------------------------------------------------------------------------- -#define CPU_BRAND_ID_LENGTH 48 // Total number of characters supported -#define LOW_NODE_DEVICEID 24 -#define NB_CAPABILITIES 0xE8 //Function 3 Registers -//---------------------------------------------------------------------------- -// CPU MICROCODE PATCH TYPEDEFS, STRUCTURES, ENUMS -// -//---------------------------------------------------------------------------- -/* All lengths are in bytes */ -#define MICROCODE_TRIADE_SIZE 28 -#define MICROCODE_HEADER_LENGTH 64 - -/* Offsets in UCODE PATCH Header */ -/* Note: Header is 64 bytes */ -#define DATE_CODE_OFFSET 0 // 4 bytes -#define PATCH_ID 4 // 4 bytes -#define MICROCODE_PATH_DATA_ID 8 // 2 bytes -#define MICROCODE_PATCH_DATA_LENGTH 10 // 1 byte -#define MICROCODE_PATCH_DATA_CHECKSUM 12 // 4 bytes -#define CHIPSET_1_DEVICE_ID 16 // 4 bytes -#define CHIPSET_2_DEVICE_ID 20 // 4 bytes -#define PROCESSOR_REV_ID 24 // 2 bytes -#define CHIPSET_1_REV_ID 26 // 1 byte -#define CHIPSET_2_REV_ID 27 // 1 byte - -#define MICROCODE_PATCH_2K_SIZE 2048 -#define MICROCODE_PATCH_4K_SIZE 4096 -/*--------------------------------------------------------------------------------------- - * T Y P E D E F S, S T R U C T U R E S, E N U M S - *--------------------------------------------------------------------------------------- - */ -//---------------------------------------------------------------------------- -// CPU BRAND ID TYPEDEFS, STRUCTURES, ENUMS -// -//---------------------------------------------------------------------------- -/// A structure representing BrandId[15:0] from -/// CPUID Fn8000_0001_EBX -typedef struct { - UINT8 String1:4; ///< An index to a string value used to create the name string - UINT8 String2:4; ///< An index to a string value used to create the name string - UINT8 Page:1; ///< An index to the appropriate page for the String1, String2, and Model values - UINT8 Model:7; ///< A field used to create the model number in the name string - UINT8 Socket:4; ///< Specifies the package type - UINT8 Cores:4; ///< Identifies how many physical cores are present -} AMD_CPU_BRAND_DATA; - -/// A structure containing string1 and string2 values -/// as well as information pertaining to their usage -typedef struct { - IN UINT8 Cores; ///< Appropriate number of physical cores - IN UINT8 Page; ///< This string's page number - IN UINT8 Index; ///< String index - IN UINT8 Socket; ///< Package type information - IN CONST CHAR8 *Stringstart; ///< The literal string - IN UINT8 Stringlength; ///< Number of characters in the string -} AMD_CPU_BRAND; - -/// An entire CPU brand table. -typedef struct { - UINT8 NumberOfEntries; ///< The number of entries in the table. - CONST AMD_CPU_BRAND *Table; ///< The table entries. -} CPU_BRAND_TABLE; - -//---------------------------------------------------------------------------- -// CPU MICROCODE PATCH TYPEDEFS, STRUCTURES, ENUMS -// -//---------------------------------------------------------------------------- -/// Microcode patch field definitions -typedef struct { - UINT32 DateCode; ///< Date of patch creation - UINT32 PatchID; ///< Patch level - UINT16 MicrocodePatchDataID; ///< Internal use only - UINT8 MicrocodePatchDataLength; ///< Internal use only - UINT8 InitializationFlag; ///< Internal use only - UINT32 MicrocodePatchDataChecksum; ///< Doubleword sum of data block - UINT32 Chipset1DeviceID; ///< Device ID of 1st HT device to match - UINT32 Chipset2DeviceID; ///< Device ID of 2nd HT device to match - UINT16 ProcessorRevisionID; ///< Equivalent ID - UINT8 Chipset1RevisionID; ///< Revision level of 1st HT device to match - UINT8 Chipset2RevisionID; ///< Revision level of 2nd HT device to match - UINT8 BiosApiRevision; ///< BIOS INT 15 API revision required - UINT8 Reserved1[3]; ///< Reserved - UINT32 MatchRegister0; ///< Internal use only - UINT32 MatchRegister1; ///< Internal use only - UINT32 MatchRegister2; ///< Internal use only - UINT32 MatchRegister3; ///< Internal use only - UINT32 MatchRegister4; ///< Internal use only - UINT32 MatchRegister5; ///< Internal use only - UINT32 MatchRegister6; ///< Internal use only - UINT32 MatchRegister7; ///< Internal use only - UINT8 PatchDataBlock[896]; ///< Raw patch data - UINT8 Reserved2[896]; ///< Reserved - UINT8 X86CodePresent; ///< Boolean to determine if executable code exists - UINT8 X86CodeEntry[191]; ///< Code to execute if X86CodePresent != 0 -} MICROCODE_PATCH; - -/// Two kilobyte array containing the raw -/// microcode patch binary data -typedef struct { - IN UINT8 MicrocodePatches[MICROCODE_PATCH_2K_SIZE]; ///< 2k UINT8 elements -} MICROCODE_PATCHES; - -/// Four kilobyte array containing the raw -/// microcode patch binary data -typedef struct { - IN UINT8 MicrocodePatches[MICROCODE_PATCH_4K_SIZE]; ///< 4k UINT8 elements -} MICROCODE_PATCHES_4K; - -/** - * Set down core register - * - * @CpuServiceInstances - * - * @param[in] FamilySpecificServices The current Family Specific Services. - * @param[in] Socket Socket ID. - * @param[in] Module Module ID in socket. - * @param[in] LeveledCores Number of core. - * @param[in] CoreLevelMode Core level mode. - * @param[in] StdHeader Header for library and services. - * - * @retval TRUE Down Core register is updated. - * @retval FALSE Down Core register is not updated. - */ -typedef BOOLEAN (F_CPU_SET_DOWN_CORE_REGISTER) ( - IN CPU_CORE_LEVELING_FAMILY_SERVICES *FamilySpecificServices, - IN UINT32 *Socket, - IN UINT32 *Module, - IN UINT32 *LeveledCores, - IN CORE_LEVELING_TYPE CoreLevelMode, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -/// Reference to a method -typedef F_CPU_SET_DOWN_CORE_REGISTER *PF_CPU_SET_DOWN_CORE_REGISTER; - -/** - * Provide the interface to the Core Leveling Family Specific Services. - * - * Use the methods or data in this struct to adapt the feature code to a specific cpu family or model (or stepping!). - * Each supported Family must provide an implementation for all methods in this interface, even if the - * implementation is a CommonReturn(). - */ -struct _CPU_CORE_LEVELING_FAMILY_SERVICES { // See Forward Declaration above - UINT16 Revision; ///< Interface version - // Public Methods. - PF_CPU_SET_DOWN_CORE_REGISTER SetDownCoreRegister; ///< Method: Set down core register. -}; - -//---------------------------------------------------------------------------- -// CPU PERFORM EARLY INIT ON CORE -// -//---------------------------------------------------------------------------- -/// Flag definition. -#define PERFORM_EARLY_WARM_RESET 0x1 // bit 0 --- the related function needs to be run if it's warm reset -#define PERFORM_EARLY_COLD_BOOT 0x2 // bit 1 --- the related function needs to be run if it's cold boot - -#define PERFORM_EARLY_ANY_CONDITION 0xFFFFFFFF // the related function always needs to be run -/*--------------------------------------------------------------------------------------- - * F U N C T I O N P R O T O T Y P E - *--------------------------------------------------------------------------------------- - */ - -// These are P U B L I C functions, used by IBVs -AGESA_STATUS -AmdCpuEarly ( - IN AMD_CONFIG_PARAMS *StdHeader, - IN PLATFORM_CONFIGURATION *PlatformConfig - ); - -// These are P U B L I C functions, used by AGESA -VOID -SetBrandIdRegisters ( - IN OUT AMD_CONFIG_PARAMS *StdHeader - ); - -AGESA_STATUS -PmInitializationAtEarly ( - IN AMD_CPU_EARLY_PARAMS *CpuEarlyParams, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -BOOLEAN -LoadMicrocodePatch ( - IN OUT AMD_CONFIG_PARAMS *StdHeader - ); -#endif // _CPU_EARLY_INIT_H_ - diff --git a/src/vendorcode/amd/agesa/f12/Proc/CPU/cpuEnvInit.h b/src/vendorcode/amd/agesa/f12/Proc/CPU/cpuEnvInit.h deleted file mode 100644 index 2d13b5df5b..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/CPU/cpuEnvInit.h +++ /dev/null @@ -1,73 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * AMD CPU Env Init API functions Prototypes. - * - * Contains code for doing any Env CPU initialization - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: CPU - * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $ - * - */ -/* - ****************************************************************************** - * - * Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - ****************************************************************************** - */ - -#ifndef _CPU_ENV_INIT_H_ -#define _CPU_ENV_INIT_H_ - -/*---------------------------------------------------------------------------------------- - * M I X E D (Definitions And Macros / Typedefs, Structures, Enums) - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------- - * D E F I N I T I O N S A N D M A C R O S - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------- - * T Y P E D E F S, S T R U C T U R E S, E N U M S - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------- - * F U N C T I O N P R O T O T Y P E - *---------------------------------------------------------------------------------------- - */ -// HobTransfer -AGESA_STATUS -CopyHeapToMainRamAtPost ( - IN OUT AMD_CONFIG_PARAMS *StdHeader - ); - -#endif // _CPU_ENV_INIT_H_ diff --git a/src/vendorcode/amd/agesa/f12/Proc/CPU/cpuEventLog.c b/src/vendorcode/amd/agesa/f12/Proc/CPU/cpuEventLog.c deleted file mode 100644 index 1beb48eb1d..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/CPU/cpuEventLog.c +++ /dev/null @@ -1,408 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * AMD Event (Error) Log APIs, and related functions. - * - * Contains code that records and returns the events and errors. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: CPU - * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $ - * - */ -/***************************************************************************** - * - * Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - ****************************************************************************** - */ - -/*---------------------------------------------------------------------------------------- - * M O D U L E S U S E D - *---------------------------------------------------------------------------------------- - */ - -#include "AGESA.h" -#include "amdlib.h" -#include "heapManager.h" -#include "GeneralServices.h" -#include "Ids.h" -#include "Filecode.h" -CODE_GROUP (G1_PEICC) -RDATA_GROUP (G1_PEICC) - -#define FILECODE PROC_CPU_CPUEVENTLOG_FILECODE -/*---------------------------------------------------------------------------------------- - * D E F I N I T I O N S A N D M A C R O S - *---------------------------------------------------------------------------------------- - */ -#define TOTAL_EVENT_LOG_BUFFERS 16 - -/*---------------------------------------------------------------------------------------- - * T Y P E D E F S A N D S T R U C T U R E S - *---------------------------------------------------------------------------------------- - */ - -/** - * A wrapper for each Event Log entry. - */ -typedef struct { - UINT16 Count; ///< Entry number - AGESA_EVENT AgesaEvent; ///< The entry itself. -} AGESA_EVENT_STRUCT; - -/** - * The Event Log. - */ -typedef struct { - UINT16 ReadWriteFlag; ///< Read Write flag. - UINT16 Count; ///< The total number of active entries. - UINT16 ReadRecordPtr; ///< The next entry to read. - UINT16 WriteRecordPtr; ///< The next entry to write. - AGESA_EVENT_STRUCT AgesaEventStruct[TOTAL_EVENT_LOG_BUFFERS]; ///< The entries. -} AGESA_STRUCT_BUFFER; - -/*---------------------------------------------------------------------------------------- - * P R O T O T Y P E S O F L O C A L F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ -VOID -STATIC -GetEventLogHeapPointer ( - OUT AGESA_STRUCT_BUFFER **EventLog, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -/*---------------------------------------------------------------------------------------*/ -/** - * External AGESA interface to read an Event from the Event Log. - * - * This is the implementation of the external AGESA interface entry, as a thin wrapper - * around the internal log services. - * - * @param[in] Event The event class, id, and any associated data. - * - * @retval AGESA_SUCCESS Always Succeeds. - */ -AGESA_STATUS -AmdReadEventLog ( - IN EVENT_PARAMS *Event - ) -{ - AGESA_EVENT LogEvent; - AGESA_STATUS Status; - - AGESA_TESTPOINT (TpIfAmdReadEventLogEntry, &Event->StdHeader); - - ASSERT (Event != NULL); - Event->StdHeader.HeapBasePtr = HeapGetBaseAddress (&Event->StdHeader); - Status = GetEventLog (&LogEvent, &Event->StdHeader); - if (Status != AGESA_SUCCESS) - return Status; - - Event->EventClass = LogEvent.EventClass; - Event->EventInfo = LogEvent.EventInfo; - Event->DataParam1 = LogEvent.DataParam1; - Event->DataParam2 = LogEvent.DataParam2; - Event->DataParam3 = LogEvent.DataParam3; - Event->DataParam4 = LogEvent.DataParam4; - - AGESA_TESTPOINT (TpIfAmdReadEventLogExit, &Event->StdHeader); - return Status; -} - - -/*---------------------------------------------------------------------------------------*/ -/** - * - * This function prepares the Event Log for use. - * - * Allocate the memory for an event log on the heap. Set the read pointer, write pointer, - * and count to reflect the log is empty. - * - * @param[in] StdHeader Our configuration, for passing to services. - * - * @retval AGESA_SUCCESS The event log is initialized. - * @retval AGESA_ERROR Allocate Heap Buffer returned an error. - * - */ -AGESA_STATUS -EventLogInitialization ( - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - ALLOCATE_HEAP_PARAMS AllocateHeapParams; - AGESA_STRUCT_BUFFER *AgesaEventAlloc; - AGESA_STATUS Status; - - AllocateHeapParams.BufferHandle = EVENT_LOG_BUFFER_HANDLE; - AllocateHeapParams.RequestedBufferSize = sizeof (AGESA_STRUCT_BUFFER); - AllocateHeapParams.Persist = HEAP_SYSTEM_MEM; - Status = HeapAllocateBuffer (&AllocateHeapParams, StdHeader); - AgesaEventAlloc = (AGESA_STRUCT_BUFFER *) AllocateHeapParams.BufferPtr; - AgesaEventAlloc->Count = 0; - AgesaEventAlloc->ReadRecordPtr = 0; - AgesaEventAlloc->WriteRecordPtr = 0; - AgesaEventAlloc->ReadWriteFlag = 1; - - return Status; -} - - -/*---------------------------------------------------------------------------------------*/ -/** - * - * This function logs AGESA events into the event log. - * - * It will put the information in a circular buffer consisting of 16 such log - * entries. If the buffer gets full, then the next event log entry will be written - * over the oldest event log entry. - * - * @param[in] EventClass The severity of the event, its associated AGESA_STATUS. - * @param[in] EventInfo Uniquely identifies the event. - * @param[in] DataParam1 Event specific additional data - * @param[in] DataParam2 Event specific additional data - * @param[in] DataParam3 Event specific additional data - * @param[in] DataParam4 Event specific additional data - * @param[in] StdHeader Header for library and services - * - */ -VOID -PutEventLog ( - IN AGESA_STATUS EventClass, - IN UINT32 EventInfo, - IN UINT32 DataParam1, - IN UINT32 DataParam2, - IN UINT32 DataParam3, - IN UINT32 DataParam4, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - UINT16 Index; - AGESA_STRUCT_BUFFER *AgesaEventAlloc; - - IDS_HDT_CONSOLE (MAIN_FLOW, "\n * %s Event: %08x Data: %x, %x, %x, %x\n\n", - (EventClass == AGESA_FATAL) ? "FATAL" : - (EventClass == AGESA_CRITICAL) ? "CRITICAL" : - (EventClass == AGESA_ERROR) ? "ERROR" : - (EventClass == AGESA_WARNING) ? "WARNING" : - (EventClass == AGESA_ALERT) ? "ALERT" : - (EventClass == AGESA_BOUNDS_CHK) ? "BOUNDS_CHK" : - (EventClass == AGESA_UNSUPPORTED) ? "UNSUPPORTED" : - "SUCCESS", EventInfo, DataParam1, DataParam2, DataParam3, DataParam4); - - if (EventClass < AGESA_STATUS_LOG_LEVEL) - return; - - AgesaEventAlloc = NULL; - GetEventLogHeapPointer (&AgesaEventAlloc, StdHeader); - ASSERT (AgesaEventAlloc != NULL); - if (AgesaEventAlloc == NULL) - return; - - Index = AgesaEventAlloc->WriteRecordPtr; - - // Add the new event log data into a circular buffer - AgesaEventAlloc->AgesaEventStruct[Index].AgesaEvent.EventClass = EventClass; - AgesaEventAlloc->AgesaEventStruct[Index].AgesaEvent.EventInfo = EventInfo; - AgesaEventAlloc->AgesaEventStruct[Index].AgesaEvent.DataParam1 = DataParam1; - AgesaEventAlloc->AgesaEventStruct[Index].AgesaEvent.DataParam2 = DataParam2; - AgesaEventAlloc->AgesaEventStruct[Index].AgesaEvent.DataParam3 = DataParam3; - AgesaEventAlloc->AgesaEventStruct[Index].AgesaEvent.DataParam4 = DataParam4; - - if ((AgesaEventAlloc->WriteRecordPtr == AgesaEventAlloc->ReadRecordPtr) && - (AgesaEventAlloc->ReadWriteFlag == 0)) { - AgesaEventAlloc->WriteRecordPtr += 1; - AgesaEventAlloc->ReadRecordPtr += 1; - if (AgesaEventAlloc->WriteRecordPtr == TOTAL_EVENT_LOG_BUFFERS) { - AgesaEventAlloc->WriteRecordPtr = 0; - AgesaEventAlloc->ReadRecordPtr = 0; - } - } else { - AgesaEventAlloc->WriteRecordPtr += 1; - if (AgesaEventAlloc->WriteRecordPtr == TOTAL_EVENT_LOG_BUFFERS) { - AgesaEventAlloc->WriteRecordPtr = 0; - } - AgesaEventAlloc->ReadWriteFlag = 0; - } - AgesaEventAlloc->Count = AgesaEventAlloc->Count + 1; - - if (AgesaEventAlloc->Count <= TOTAL_EVENT_LOG_BUFFERS) { - AgesaEventAlloc->AgesaEventStruct[Index].Count = Index; - } -} - - -/*---------------------------------------------------------------------------------------*/ -/** - * - * This function gets event logs from the circular buffer. - * - * It will read the oldest entry from the circular buffer and place that information to the structure - * pointed to by the parameter. The read pointers will be incremented to remove the entry from buffer - * so that a subsequent call will return the next entry from the buffer. If the buffer is empty the - * returned log event will have EventInfo zero, which is not a valid event id. - * - * @param[out] EventRecord The next log event. - * @param[in] StdHeader Header for library and services - * - * @retval AGESA_SUCCESS Always succeeds. - * - */ -AGESA_STATUS -GetEventLog ( - OUT AGESA_EVENT *EventRecord, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - UINT16 Index; - AGESA_STRUCT_BUFFER *AgesaEventAlloc; - - AgesaEventAlloc = NULL; - - GetEventLogHeapPointer (&AgesaEventAlloc, StdHeader); - ASSERT (AgesaEventAlloc != NULL); - if (AgesaEventAlloc == NULL) - return AGESA_BOUNDS_CHK; - - if ((AgesaEventAlloc->ReadRecordPtr == AgesaEventAlloc->WriteRecordPtr) && - (AgesaEventAlloc->ReadWriteFlag == 1)) { - // EventInfo == zero, means no more data. - LibAmdMemFill (EventRecord, 0, sizeof (AGESA_EVENT), StdHeader); - } else { - Index = AgesaEventAlloc->ReadRecordPtr; - EventRecord->EventClass = AgesaEventAlloc->AgesaEventStruct[Index].AgesaEvent.EventClass; - EventRecord->EventInfo = AgesaEventAlloc->AgesaEventStruct[Index].AgesaEvent.EventInfo; - EventRecord->DataParam1 = AgesaEventAlloc->AgesaEventStruct[Index].AgesaEvent.DataParam1; - EventRecord->DataParam2 = AgesaEventAlloc->AgesaEventStruct[Index].AgesaEvent.DataParam2; - EventRecord->DataParam3 = AgesaEventAlloc->AgesaEventStruct[Index].AgesaEvent.DataParam3; - EventRecord->DataParam4 = AgesaEventAlloc->AgesaEventStruct[Index].AgesaEvent.DataParam4; - if (AgesaEventAlloc->ReadRecordPtr == (TOTAL_EVENT_LOG_BUFFERS - 1)) { - AgesaEventAlloc->ReadRecordPtr = 0; - } else { - AgesaEventAlloc->ReadRecordPtr = AgesaEventAlloc->ReadRecordPtr + 1; - } - if (AgesaEventAlloc->ReadRecordPtr == AgesaEventAlloc->WriteRecordPtr) { - AgesaEventAlloc->ReadWriteFlag = 1; - } - } - return (AGESA_SUCCESS); -} - -/*---------------------------------------------------------------------------------------*/ -/** - * - * This function gets event logs from the circular buffer without flushing the entry. - * - * It will read the desired entry from the circular buffer and place that information to the structure - * pointed to by the parameter. The read pointers will not be incremented to remove the entry from the - * buffer. If the buffer is empty, or the desired entry does not exist, FALSE will be returned. - * - * @param[out] EventRecord The next log event. - * @param[in] Index Zero-based unread entry index - * @param[in] StdHeader Header for library and services - * - * @retval TRUE Entry exists - * @retval FALSE Entry does not exist - * - */ -BOOLEAN -PeekEventLog ( - OUT AGESA_EVENT *EventRecord, - IN UINT16 Index, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - UINT16 ActualIndex; - UINT16 UnreadEntries; - AGESA_STRUCT_BUFFER *AgesaEventAlloc; - - AgesaEventAlloc = NULL; - - GetEventLogHeapPointer (&AgesaEventAlloc, StdHeader); - ASSERT (AgesaEventAlloc != NULL); - if (AgesaEventAlloc == NULL) - return FALSE; - - if ((AgesaEventAlloc->ReadRecordPtr == AgesaEventAlloc->WriteRecordPtr) && - (AgesaEventAlloc->ReadWriteFlag == 1)) { - // EventInfo == zero, means no more data. - return FALSE; - } - if (AgesaEventAlloc->ReadRecordPtr < AgesaEventAlloc->WriteRecordPtr) { - UnreadEntries = AgesaEventAlloc->WriteRecordPtr - AgesaEventAlloc->ReadRecordPtr; - } else { - UnreadEntries = TOTAL_EVENT_LOG_BUFFERS - (AgesaEventAlloc->ReadRecordPtr - AgesaEventAlloc->WriteRecordPtr); - } - if (Index >= UnreadEntries) { - return FALSE; - } - ActualIndex = Index + AgesaEventAlloc->ReadRecordPtr; - if (ActualIndex >= TOTAL_EVENT_LOG_BUFFERS) { - ActualIndex -= TOTAL_EVENT_LOG_BUFFERS; - } - - EventRecord->EventClass = AgesaEventAlloc->AgesaEventStruct[ActualIndex].AgesaEvent.EventClass; - EventRecord->EventInfo = AgesaEventAlloc->AgesaEventStruct[ActualIndex].AgesaEvent.EventInfo; - EventRecord->DataParam1 = AgesaEventAlloc->AgesaEventStruct[ActualIndex].AgesaEvent.DataParam1; - EventRecord->DataParam2 = AgesaEventAlloc->AgesaEventStruct[ActualIndex].AgesaEvent.DataParam2; - EventRecord->DataParam3 = AgesaEventAlloc->AgesaEventStruct[ActualIndex].AgesaEvent.DataParam3; - EventRecord->DataParam4 = AgesaEventAlloc->AgesaEventStruct[ActualIndex].AgesaEvent.DataParam4; - - return TRUE; -} - - -/*---------------------------------------------------------------------------------------*/ -/** - * - * This function gets the Event Log pointer. - * - * It will locate the Event Log on the heap using the heap locate service. If the Event - * Log is not located, NULL is returned. - * - * @param[out] EventLog Pointer to the Event Log, or NULL. - * @param[in] StdHeader Our Configuration, for passing to services. - * - */ -VOID -STATIC -GetEventLogHeapPointer ( - OUT AGESA_STRUCT_BUFFER **EventLog, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - LOCATE_HEAP_PTR LocateHeapStruct; - - LocateHeapStruct.BufferHandle = EVENT_LOG_BUFFER_HANDLE; - LocateHeapStruct.BufferPtr = NULL; - if ((HeapLocateBuffer (&LocateHeapStruct, StdHeader)) == AGESA_SUCCESS) { - *EventLog = (AGESA_STRUCT_BUFFER *)LocateHeapStruct.BufferPtr; - } else { - *EventLog = NULL; - } -} diff --git a/src/vendorcode/amd/agesa/f12/Proc/CPU/cpuFamilyTranslation.c b/src/vendorcode/amd/agesa/f12/Proc/CPU/cpuFamilyTranslation.c deleted file mode 100644 index 3884cd758b..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/CPU/cpuFamilyTranslation.c +++ /dev/null @@ -1,483 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * AMD CPU Family Translation functions. - * - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: CPU/Interface - * @e \$Revision: 49967 $ @e \$Date: 2011-03-31 11:15:12 +0800 (Thu, 31 Mar 2011) $ - * - */ -/* - ****************************************************************************** - * - * Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - ****************************************************************************** - */ - -/*---------------------------------------------------------------------------------------- - * M O D U L E S U S E D - *---------------------------------------------------------------------------------------- - */ -#include "AGESA.h" -#include "amdlib.h" -#include "Ids.h" -#include "cpuRegisters.h" -#include "CommonReturns.h" -#include "GeneralServices.h" -#include "cpuFamilyTranslation.h" -#include "Filecode.h" -CODE_GROUP (G1_PEICC) -RDATA_GROUP (G1_PEICC) - -#define FILECODE PROC_CPU_CPUFAMILYTRANSLATION_FILECODE - -/*---------------------------------------------------------------------------------------- - * D E F I N I T I O N S A N D M A C R O S - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------- - * T Y P E D E F S A N D S T R U C T U R E S - *---------------------------------------------------------------------------------------- - */ - -CONST CPU_SPECIFIC_SERVICES ROMDATA cpuNullServices = -{ - 0, - (PF_CPU_DISABLE_PSTATE) CommonReturnAgesaSuccess, - (PF_CPU_TRANSITION_PSTATE) CommonReturnAgesaSuccess, - (PF_CPU_GET_IDD_MAX) CommonReturnFalse, - (PF_CPU_GET_TSC_RATE) CommonReturnAgesaSuccess, - (PF_CPU_GET_NB_FREQ) CommonReturnAgesaSuccess, - (PF_CPU_GET_MIN_MAX_NB_FREQ) CommonReturnAgesaSuccess, - (PF_CPU_GET_NB_PSTATE_INFO) CommonReturnFalse, - (PF_CPU_IS_NBCOF_INIT_NEEDED) CommonReturnAgesaSuccess, - (PF_CPU_GET_NB_IDD_MAX) CommonReturnFalse, - (PF_CPU_AP_INITIAL_LAUNCH) CommonReturnFalse, - (PF_CPU_NUMBER_OF_PHYSICAL_CORES) CommonReturnZero8, - (PF_CPU_AMD_GET_AP_MAILBOX_FROM_HARDWARE) CommonReturnAgesaSuccess, - (PF_CPU_SET_AP_CORE_NUMBER) CommonVoid, - (PF_CPU_GET_AP_CORE_NUMBER) CommonReturnZero32, - (PF_CPU_TRANSFER_AP_CORE_NUMBER) CommonVoid, - (PF_CORE_ID_POSITION_IN_INITIAL_APIC_ID) CommonReturnAgesaSuccess, - (PF_CPU_SAVE_FEATURES) CommonReturnAgesaSuccess, - (PF_CPU_WRITE_FEATURES) CommonReturnAgesaSuccess, - (PF_CPU_SET_WARM_RESET_FLAG) CommonReturnAgesaSuccess, - (PF_CPU_GET_WARM_RESET_FLAG) CommonReturnAgesaSuccess, - GetEmptyArray, - GetEmptyArray, - GetEmptyArray, - GetEmptyArray, - GetEmptyArray, - GetEmptyArray, - GetEmptyArray, - (PF_CPU_GET_PLATFORM_TYPE_SPECIFIC_INFO) CommonReturnAgesaSuccess, - (PF_IS_NB_PSTATE_ENABLED) CommonReturnFalse, - (PF_NEXT_LINK_HAS_HTFPY_FEATS) CommonReturnFalse, - (PF_SET_HT_PHY_REGISTER) CommonVoid, - (PF_GET_NEXT_HT_LINK_FEATURES) CommonVoid, - NULL, - NULL, - NULL, - NULL, - InitCacheDisabled, - (PF_GET_EARLY_INIT_TABLE) CommonVoid -}; - -/*---------------------------------------------------------------------------------------- - * P R O T O T Y P E S O F L O C A L F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ -VOID -STATIC -GetCpuServices ( - IN CPU_FAMILY_SUPPORT_TABLE *FamilyTable, - IN UINT64 *MatchData, - OUT CONST VOID **CpuServices, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -/*---------------------------------------------------------------------------------------- - * E X P O R T E D F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ -extern CPU_FAMILY_SUPPORT_TABLE CpuSupportedFamiliesTable; -extern CPU_FAMILY_ID_XLAT_TABLE CpuSupportedFamilyIdTable; - -/*---------------------------------------------------------------------------------------*/ -/** - * - * Returns the logical ID of the desired processor. This will be obtained by - * reading the CPUID and converting it into a "logical ID" which is not package - * dependent. - * - * @param[in] Socket Socket - * @param[out] LogicalId The Processor's Logical ID - * @param[in] StdHeader Handle of Header for calling lib functions and services. - * - */ -VOID -GetLogicalIdOfSocket ( - IN UINT32 Socket, - OUT CPU_LOGICAL_ID *LogicalId, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - UINT32 RawCpuid; - PCI_ADDR PciAddress; - AGESA_STATUS AssumedSuccess; - - RawCpuid = 0; - - if (GetPciAddress (StdHeader, (UINT8)Socket, 0, &PciAddress, &AssumedSuccess)) { - PciAddress.Address.Function = FUNC_3; - PciAddress.Address.Register = CPUID_FMR; - LibAmdPciRead (AccessWidth32, PciAddress, &RawCpuid, StdHeader); - GetLogicalIdFromCpuid (RawCpuid, LogicalId, StdHeader); - } else { - LogicalId->Family = 0; - LogicalId->Revision = 0; - // Logical ID was not found. - IDS_ERROR_TRAP; - } -} - - -/*---------------------------------------------------------------------------------------*/ -/** - * - * Returns the logical ID of the executing core. This will be obtained by reading - * the CPUID and converting it into a "logical ID" which is not package dependent. - * - * @param[out] LogicalId The Processor's Logical ID - * @param[in] StdHeader Handle of Header for calling lib functions and services. - * - */ -VOID -GetLogicalIdOfCurrentCore ( - OUT CPU_LOGICAL_ID *LogicalId, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - CPUID_DATA CpuidDataStruct; - - LibAmdCpuidRead (AMD_CPUID_APICID_LPC_BID, &CpuidDataStruct, StdHeader); - GetLogicalIdFromCpuid (CpuidDataStruct.EAX_Reg, LogicalId, StdHeader); -} - - -/*---------------------------------------------------------------------------------------*/ -/** - * - * Returns the logical ID of a processor with the given CPUID value. This - * will be obtained by converting it into a "logical ID" which is not package - * dependent. - * - * @param[in] RawCpuid The unprocessed CPUID value to be translated - * @param[out] LogicalId The Processor's Logical ID - * @param[in] StdHeader Handle of Header for calling lib functions and services - * - */ -VOID -GetLogicalIdFromCpuid ( - IN UINT32 RawCpuid, - OUT CPU_LOGICAL_ID *LogicalId, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - UINT8 i; - UINT8 k; - UINT8 NumberOfFamiliesSupported; - UINT8 NumberOfLogicalSubFamilies; - UINT8 LogicalIdEntries; - UINT32 j; - UINT32 RawFamily; - UINT32 CpuModelAndExtendedModel; - UINT64 LogicalFamily; - BOOLEAN IdNotFound; - BOOLEAN FamilyNotFound; - CONST PF_CPU_GET_SUBFAMILY_ID_ARRAY *SubFamilyIdPtr; - CPU_LOGICAL_ID_XLAT *CpuLogicalIdAndRevPtr; - CONST CPU_LOGICAL_ID_FAMILY_XLAT *ImageSupportedId; - - IdNotFound = TRUE; - FamilyNotFound = TRUE; - CpuLogicalIdAndRevPtr = NULL; - ImageSupportedId = CpuSupportedFamilyIdTable.FamilyIdTable; - NumberOfFamiliesSupported = CpuSupportedFamilyIdTable.Elements; - - RawFamily = ((RawCpuid & 0xF00) >> 8) + ((RawCpuid & 0xFF00000) >> 20); - RawCpuid &= (UINT32) CPU_FMS_MASK; - CpuModelAndExtendedModel = (UINT16) ((RawCpuid >> 8) | RawCpuid); - - LogicalId->Family = 0; - LogicalId->Revision = 0; - - for (i = 0; i < NumberOfFamiliesSupported && FamilyNotFound; i++) { - if (ImageSupportedId[i].Family == RawFamily) { - FamilyNotFound = FALSE; - LogicalId->Family = ImageSupportedId[i].UnknownRevision.Family; - LogicalId->Revision = ImageSupportedId[i].UnknownRevision.Revision; - - NumberOfLogicalSubFamilies = ImageSupportedId[i].Elements; - SubFamilyIdPtr = ImageSupportedId[i].SubFamilyIdTable; - for (j = 0; j < NumberOfLogicalSubFamilies && IdNotFound; j++) { - SubFamilyIdPtr[j] ((const CPU_LOGICAL_ID_XLAT **)&CpuLogicalIdAndRevPtr, &LogicalIdEntries, &LogicalFamily, StdHeader); - ASSERT (CpuLogicalIdAndRevPtr != NULL); - for (k = 0; k < LogicalIdEntries; k++) { - if (CpuLogicalIdAndRevPtr[k].RawId == CpuModelAndExtendedModel) { - IdNotFound = FALSE; - LogicalId->Family = LogicalFamily; - LogicalId->Revision = CpuLogicalIdAndRevPtr[k].LogicalId; - break; - } - } - } - } - } -} - - -/*---------------------------------------------------------------------------------------*/ -/** - * - * Retrieves a pointer to the desired processor's family specific services structure. - * - * @param[in] Socket The Processor in this Socket. - * @param[out] FunctionTable The Processor's Family Specific services. - * @param[in] StdHeader Handle of Header for calling lib functions and services. - * - */ -VOID -GetCpuServicesOfSocket ( - IN UINT32 Socket, - OUT CONST CPU_SPECIFIC_SERVICES **FunctionTable, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - GetFeatureServicesOfSocket (&CpuSupportedFamiliesTable, - Socket, - (const VOID **)FunctionTable, - StdHeader); - if (*FunctionTable == NULL) { - *FunctionTable = &cpuNullServices; - } -} - - -/*---------------------------------------------------------------------------------------*/ -/** - * - * Retrieves a pointer to the desired processor's family specific services structure. - * - * @param[in] FamilyTable The table to search in. - * @param[in] Socket The Processor in this Socket. - * @param[out] CpuServices The Processor's Family Specific services. - * @param[in] StdHeader Handle of Header for calling lib functions and services. - * - */ -VOID -GetFeatureServicesOfSocket ( - IN CPU_FAMILY_SUPPORT_TABLE *FamilyTable, - IN UINT32 Socket, - OUT CONST VOID **CpuServices, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - CPU_LOGICAL_ID CpuFamilyRevision; - - GetLogicalIdOfSocket (Socket, &CpuFamilyRevision, StdHeader); - GetFeatureServicesFromLogicalId (FamilyTable, &CpuFamilyRevision, CpuServices, StdHeader); -} - - -/*---------------------------------------------------------------------------------------*/ -/** - * - * Retrieves a pointer to the executing core's family specific services structure. - * - * @param[out] FunctionTable The Processor's Family Specific services. - * @param[in] StdHeader Handle of Header for calling lib functions and services. - * - */ -VOID -GetCpuServicesOfCurrentCore ( - OUT CONST CPU_SPECIFIC_SERVICES **FunctionTable, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - GetFeatureServicesOfCurrentCore (&CpuSupportedFamiliesTable, - (const VOID **)FunctionTable, - StdHeader); - if (*FunctionTable == NULL) { - *FunctionTable = &cpuNullServices; - } -} - -/*---------------------------------------------------------------------------------------*/ -/** - * - * Retrieves a pointer to the family specific services structure for a processor - * with the given logical ID. - * - * @param[in] FamilyTable The table to search in. - * @param[out] CpuServices The Processor's Family Specific services. - * @param[in] StdHeader Handle of Header for calling lib functions and services. - * - */ -VOID -GetFeatureServicesOfCurrentCore ( - IN CPU_FAMILY_SUPPORT_TABLE *FamilyTable, - OUT CONST VOID **CpuServices, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - CPU_LOGICAL_ID CpuFamilyRevision; - - GetLogicalIdOfCurrentCore (&CpuFamilyRevision, StdHeader); - GetFeatureServicesFromLogicalId (FamilyTable, &CpuFamilyRevision, CpuServices, StdHeader); -} - - -/*---------------------------------------------------------------------------------------*/ -/** - * - * Retrieves a pointer to the family specific services structure for a processor - * with the given logical ID. - * - * @param[in] LogicalId The Processor's logical ID. - * @param[out] FunctionTable The Processor's Family Specific services. - * @param[in] StdHeader Handle of Header for calling lib functions and services. - * - */ -VOID -GetCpuServicesFromLogicalId ( - IN CPU_LOGICAL_ID *LogicalId, - OUT CONST CPU_SPECIFIC_SERVICES **FunctionTable, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - GetFeatureServicesFromLogicalId (&CpuSupportedFamiliesTable, - LogicalId, - (const VOID **)FunctionTable, - StdHeader); - if (*FunctionTable == NULL) { - *FunctionTable = &cpuNullServices; - } -} - -/*---------------------------------------------------------------------------------------*/ -/** - * - * Retrieves a pointer to the family specific services structure for a processor - * with the given logical ID. - * - * @param[in] FamilyTable The table to search in. - * @param[in] LogicalId The Processor's logical ID. - * @param[out] CpuServices The Processor's Family Specific services. - * @param[in] StdHeader Handle of Header for calling lib functions and services. - * - */ -VOID -GetFeatureServicesFromLogicalId ( - IN CPU_FAMILY_SUPPORT_TABLE *FamilyTable, - IN CPU_LOGICAL_ID *LogicalId, - OUT CONST VOID **CpuServices, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - GetCpuServices (FamilyTable, &LogicalId->Family, CpuServices, StdHeader); -} - - -/*---------------------------------------------------------------------------------------*/ -/** - * - * Finds a family match in the given table, and returns the pointer to the - * appropriate table. If no match is found in the table, NULL will be returned. - * - * @param[in] FamilyTable The table to search in. - * @param[in] MatchData Family data that must match. - * @param[out] CpuServices The Processor's Family Specific services. - * @param[in] StdHeader Handle of Header for calling lib functions and services. - * - */ -VOID -STATIC -GetCpuServices ( - IN CPU_FAMILY_SUPPORT_TABLE *FamilyTable, - IN UINT64 *MatchData, - OUT CONST VOID **CpuServices, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - BOOLEAN IsFamily; - UINT8 i; - UINT8 NumberOfFamiliesSupported; - CONST CPU_SPECIFIC_SERVICES_XLAT *ImageSupportedFamiliesPtr; - - ImageSupportedFamiliesPtr = FamilyTable->FamilyTable; - NumberOfFamiliesSupported = FamilyTable->Elements; - IsFamily = FALSE; - for (i = 0; i < NumberOfFamiliesSupported; i++) { - if ((ImageSupportedFamiliesPtr[i].Family & *MatchData) != 0) { - IsFamily = TRUE; - break; - } - } - if (IsFamily) { - *CpuServices = ImageSupportedFamiliesPtr[i].TablePtr; - } else { - *CpuServices = NULL; - } -} - - -/*---------------------------------------------------------------------------------------*/ -/** - * Used to stub out various family specific tables of information. - * - * @param[in] FamilySpecificServices The current Family Specific Services. - * @param[in] Empty NULL, to indicate no data. - * @param[out] NumberOfElements Zero, to indicate no data. - * @param[in] StdHeader Handle of Header for calling lib functions and services. - * - */ -VOID -GetEmptyArray ( - IN CPU_SPECIFIC_SERVICES *FamilySpecificServices, - OUT CONST VOID **Empty, - OUT UINT8 *NumberOfElements, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - *NumberOfElements = 0; - *Empty = NULL; -} diff --git a/src/vendorcode/amd/agesa/f12/Proc/CPU/cpuFamilyTranslation.h b/src/vendorcode/amd/agesa/f12/Proc/CPU/cpuFamilyTranslation.h deleted file mode 100644 index a0f2609573..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/CPU/cpuFamilyTranslation.h +++ /dev/null @@ -1,1006 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * AMD CPU Family Translation functions. - * - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: CPU - * @e \$Revision: 49967 $ @e \$Date: 2011-03-31 11:15:12 +0800 (Thu, 31 Mar 2011) $ - * - */ -/* - ****************************************************************************** - * - * Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - ****************************************************************************** - */ - -#ifndef _CPU_FAMILY_TRANSLATION_H_ -#define _CPU_FAMILY_TRANSLATION_H_ - -/** - * @page cpuimplfss CPU Family Specific Services Implementation Guide - * - * CPU Family Specific Services provides access to supported family service functions and data, - * in a manner that isolates calling code from knowledge about particular families or which - * families are supported in the current build. - * - * @par Adding a Method to Family Specific Services - * - * To add a new method to Family Specific Services, follow these steps. - *
    - *
  • Create a typedef for the Method with the correct parameters and return type. - * - *
      - *
    • Name the method typedef (*PF_METHOD_NAME)(), where METHOD_NAME is the same name as the method table item, - * but with "_"'s and UPPERCASE, rather than mixed case. - * @n typedef VOID (*PF_METHOD_NAME)(); @n - * - *
    • [Optionally make the type F_ and provide a separate: - * @n typedef F_METHOD_NAME *PF_METHOD_NAME> @n - * and provide a single line "///" doxygen comment brief description on the PF_ type.] - *
    - * - *
  • The first parameter to @b all Family Specific Service Methods is @b required to be a reference to - * their Family Service struct. - * @n IN CPU_SPECIFIC_SERVICES *FamilySpecificServices @n - * - *
  • Provide a standard doxygen function preamble for the Method typedef. Begin the - * detailed description by provide a reference to the method instances page by including - * the lines below: - * @code - * * - * * @CpuServiceInstances - * * - * @endcode - * @note It is important to provide documentation for the method type, because the method may not - * have an implementation in any families supported by the current package. @n - * - *
  • Add to the CPU_SPECIFIC_SERVICES struct an item for the Method: - * @n PF_METHOD_NAME MethodName; ///< Method: description. @n - *
- * - * @par Implementing a Family Specific Instance of the method. - * - * To implement an instance of a method for a specific family follow these steps. - * - * - In appropriate files in the family specific directory, implement the method with the return type - * and parameters matching the method typedef. - * - * - Name the function FnnMethodName(), where nn is the family number. - * - * - Create a doxygen function preamble for the method instance. Begin the detailed description with - * an Implements command to reference the method type and add this instance to the Method Instances page. - * @code - * * - * * @CpuServiceMethod{::F_METHOD_NAME}. - * * - * @endcode - * - * - To access other family specific services as part of the method implementation, the function - * @b must use FamilySpecificServices->OtherMethod(). Do not directly call other family specific - * routines, because in the table there may be overrides or this routine may be shared by multiple families. - * - * - Do @b not call Family translation services from a family specific instance. Use the parameter. - * - * - Add the instance to the family specific CPU_SPECIFIC_SERVICES instance. - * - * - If a family does not need an instance of the method use one of the CommonReturns from - * CommonReturns.h with the same return type. - * - * @par Invoking Family Specific Services. - * - * The following example shows how to invoke a family specific method. - * @n @code - * CPU_SPECIFIC_SERVICES *FamilyServices; - * - * GetCpuServicesOfCurrentCore (&FamilyServices, StdHeader); - * ASSERT (FamilyServices != NULL); - * FamilyServices->MethodName (FamilyServices, StdHeader); - * @endcode - * - */ - - -/*--------------------------------------------------------------------------------------- - * M I X E D (Definitions And Macros / Typedefs, Structures, Enums) - *--------------------------------------------------------------------------------------- - */ -#include "cpuPostInit.h" -#include "cpuRegisters.h" -#include "cpuServices.h" -#include "Table.h" -#include "Ids.h" -#include "Topology.h" - -// Forward declaration needed for multi-structure mutual references. -AGESA_FORWARD_DECLARATION (CPU_SPECIFIC_SERVICES); -/*--------------------------------------------------------------------------------------- - * D E F I N I T I O N S A N D M A C R O S - *--------------------------------------------------------------------------------------- - */ - -/*--------------------------------------------------------------------------------------- - * T Y P E D E F S, S T R U C T U R E S, E N U M S - *--------------------------------------------------------------------------------------- - */ - -/** - * Disable the desired P-state. - * - * @CpuServiceInstances - * - * @param[in] FamilySpecificServices The current Family Specific Services. - * @param[in] StateNumber Hardware P-state number. - * @param[in] StdHeader Handle of Header for calling lib functions and services. - * - */ -typedef AGESA_STATUS F_CPU_DISABLE_PSTATE ( - IN CPU_SPECIFIC_SERVICES *FamilySpecificServices, - IN UINT8 StateNumber, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -/// Reference to a Method. -typedef F_CPU_DISABLE_PSTATE *PF_CPU_DISABLE_PSTATE; - -/** - * Transition the current core to the desired P-state. - * - * @CpuServiceInstances - * - * @param[in] FamilySpecificServices The current Family Specific Services. - * @param[in] StateNumber Software P-state number. - * @param[in] WaitForChange Wait/don't wait for P-state change to complete. - * @param[in] StdHeader Handle of Header for calling lib functions and services. - * - */ -typedef AGESA_STATUS F_CPU_TRANSITION_PSTATE ( - IN CPU_SPECIFIC_SERVICES *FamilySpecificServices, - IN UINT8 StateNumber, - IN BOOLEAN WaitForChange, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -/// Reference to a Method. -typedef F_CPU_TRANSITION_PSTATE *PF_CPU_TRANSITION_PSTATE; - -/** - * Get the desired P-state's maximum current required in milliamps. - * - * @CpuServiceInstances - * - * @param[in] FamilySpecificServices The current Family Specific Services. - * @param[in] StateNumber The desired hardware P-state number. - * @param[out] ProcIddMax The P-state's maximum current. - * @param[in] StdHeader Handle of Header for calling lib functions and services. - * - * @retval TRUE The P-state is enabled, and ProcIddMax is valid. - * @retval FALSE The P-state is disabled. - * - */ -typedef BOOLEAN F_CPU_GET_IDD_MAX ( - IN CPU_SPECIFIC_SERVICES *FamilySpecificServices, - IN UINT8 StateNumber, - OUT UINT32 *ProcIddMax, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -/// Reference to a Method. -typedef F_CPU_GET_IDD_MAX *PF_CPU_GET_IDD_MAX; - - -/** - * Returns the rate at which the current core's timestamp counter increments in megahertz. - * - * @CpuServiceInstances - * - * @param[in] FamilySpecificServices The current Family Specific Services. - * @param[out] FreqInMHz The rate at which the TSC increments in megahertz. - * @param[in] StdHeader Handle of Header for calling lib functions and services. - * - */ -typedef AGESA_STATUS F_CPU_GET_TSC_RATE ( - IN CPU_SPECIFIC_SERVICES *FamilySpecificServices, - OUT UINT32 *FreqInMHz, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -/// Reference to a Method. -typedef F_CPU_GET_TSC_RATE *PF_CPU_GET_TSC_RATE; - -/** - * Returns the processor north bridge's clock rate in megahertz. - * - * @CpuServiceInstances - * - * @param[in] FamilySpecificServices The current Family Specific Services. - * @param[out] FreqInMHz The desired node's frequency in megahertz. - * @param[in] StdHeader Handle of Header for calling lib functions and services. - * - * @retval AGESA_SUCCESS FreqInMHz is valid. - */ -typedef AGESA_STATUS F_CPU_GET_NB_FREQ ( - IN CPU_SPECIFIC_SERVICES *FamilySpecificServices, - OUT UINT32 *FreqInMHz, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -/// Reference to a Method. -typedef F_CPU_GET_NB_FREQ *PF_CPU_GET_NB_FREQ; - -/** - * Returns the node's minimum and maximum northbridge frequency. - * - * @CpuServiceInstances - * - * @param[in] FamilySpecificServices The current Family Specific Services. - * @param[in] PlatformConfig Platform profile/build option config structure. - * @param[in] PciAddress The segment, bus, and device numbers of the CPU in question. - * @param[out] MinFreqInMHz The minimum north bridge frequency. - * @param[out] MaxFreqInMHz The maximum north bridge frequency. - * @param[in] StdHeader Handle of Header for calling lib functions and services. - * - * @retval AGESA_STATUS Northbridge frequency is valid - */ -typedef AGESA_STATUS F_CPU_GET_MIN_MAX_NB_FREQ ( - IN CPU_SPECIFIC_SERVICES *FamilySpecificServices, - IN PLATFORM_CONFIGURATION *PlatformConfig, - IN PCI_ADDR *PciAddress, - OUT UINT32 *MinFreqInMHz, - OUT UINT32 *MaxFreqInMHz, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -/// Reference to a Method. -typedef F_CPU_GET_MIN_MAX_NB_FREQ *PF_CPU_GET_MIN_MAX_NB_FREQ; - -/** - * Returns the processor north bridge's P-state settings. - * - * @CpuServiceInstances - * - * @param[in] FamilySpecificServices The current Family Specific Services. - * @param[in] PlatformConfig Platform profile/build option config structure. - * @param[in] PciAddress The segment, bus, and device numbers of the CPU in question. - * @param[in] NbPstate The NB P-state number to check. - * @param[out] FreqNumeratorInMHz The desired node's frequency numerator in megahertz. - * @param[out] FreqDivisor The desired node's frequency divisor. - * @param[out] VoltageInuV The desired node's voltage in microvolts. - * @param[in] StdHeader Handle of Header for calling lib functions and services. - * - * @retval TRUE NbPstate is valid - * @retval FALSE NbPstate is disabled or invalid - */ -typedef BOOLEAN F_CPU_GET_NB_PSTATE_INFO ( - IN CPU_SPECIFIC_SERVICES *FamilySpecificServices, - IN PLATFORM_CONFIGURATION *PlatformConfig, - IN PCI_ADDR *PciAddress, - IN UINT32 NbPstate, - OUT UINT32 *FreqNumeratorInMHz, - OUT UINT32 *FreqDivisor, - OUT UINT32 *VoltageInuV, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -/// Reference to a Method. -typedef F_CPU_GET_NB_PSTATE_INFO *PF_CPU_GET_NB_PSTATE_INFO; - -/** - * Returns whether or not the NB frequency initialization sequence is required - * to be performed by the BIOS. - * - * @CpuServiceInstances - * - * @param[in] FamilySpecificServices The current Family Specific Services. - * @param[in] PciAddress The northbridge to query by pci base address. - * @param[out] NbVidUpdateAll Do all NbVids need to be updated as well. - * @param[in] StdHeader Handle of Header for calling lib functions and services. - * - */ -typedef BOOLEAN F_CPU_IS_NBCOF_INIT_NEEDED ( - IN CPU_SPECIFIC_SERVICES *FamilySpecificServices, - IN PCI_ADDR *PciAddress, - OUT BOOLEAN *NbVidUpdateAll, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -/// Reference to a Method. -typedef F_CPU_IS_NBCOF_INIT_NEEDED *PF_CPU_IS_NBCOF_INIT_NEEDED; - -/** - * Get the desired NB P-state's maximum current required in milliamps. - * - * @CpuServiceInstances - * - * @param[in] FamilySpecificServices The current Family Specific Services. - * @param[in] StateNumber The desired hardware P-state number. - * @param[out] NbIddMax The NB P-state's maximum current. - * @param[in] StdHeader Handle of Header for calling lib functions and services. - * - * @retval TRUE The NB P-state is enabled, and NbIddMax is valid. - * @retval FALSE The NB P-state is disabled. - * - */ -typedef BOOLEAN F_CPU_GET_NB_IDD_MAX ( - IN CPU_SPECIFIC_SERVICES *FamilySpecificServices, - IN UINT8 StateNumber, - OUT UINT32 *NbIddMax, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -/// Reference to a Method. -typedef F_CPU_GET_NB_IDD_MAX *PF_CPU_GET_NB_IDD_MAX; - -/** - * Launches the desired core from the reset vector. - * - * @CpuServiceInstances - * - * @param[in] FamilySpecificServices The current Family Specific Services. - * @param[in] SocketNumber The desired core's socket number. - * @param[in] ModuleNumber The desired core's die number. - * @param[in] CoreNumber The desired core's die relative core number. - * @param[in] PrimaryCoreNumber SocketNumber / ModuleNumber's primary core number. - * @param[in] StdHeader Handle of Header for calling lib functions and services. - * - * @retval TRUE The core was launched successfully. - * @retval FALSE The core was previously launched, or has a problem. - */ -typedef BOOLEAN F_CPU_AP_INITIAL_LAUNCH ( - IN CPU_SPECIFIC_SERVICES *FamilySpecificServices, - IN UINT32 SocketNumber, - IN UINT32 ModuleNumber, - IN UINT32 CoreNumber, - IN UINT32 PrimaryCoreNumber, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -/// Reference to a Method. -typedef F_CPU_AP_INITIAL_LAUNCH *PF_CPU_AP_INITIAL_LAUNCH; - -/** - * Returns the appropriate number of physical processor cores - * - * @CpuServiceInstances - * - * @param[in] FamilySpecificServices The current Family Specific Services. - * @param[in] StdHeader Handle of Header for calling lib functions and services. - * - * @return One-based number of physical cores on current processor - */ -typedef UINT8 F_CPU_NUMBER_OF_PHYSICAL_CORES ( - IN CPU_SPECIFIC_SERVICES *FamilySpecificServices, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -/// Reference to a Method. -typedef F_CPU_NUMBER_OF_PHYSICAL_CORES *PF_CPU_NUMBER_OF_PHYSICAL_CORES; - -/** - * Returns a family specific table of information pointer and size. - * - * @CpuServiceInstances - * - * @param[in] FamilySpecificServices The current Family Specific Services. - * @param[out] FamilySpecificArray Pointer to the appropriate list for the core. - * @param[out] NumberOfElements Number of valid entries FamilySpecificArray. - * @param[in] StdHeader Handle of Header for calling lib functions and services. - * - */ -typedef VOID F_CPU_GET_FAMILY_SPECIFIC_ARRAY ( - IN CPU_SPECIFIC_SERVICES *FamilySpecificServices, - OUT CONST VOID **FamilySpecificArray, - OUT UINT8 *NumberOfElements, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -/// Reference to a Method. -typedef F_CPU_GET_FAMILY_SPECIFIC_ARRAY *PF_CPU_GET_FAMILY_SPECIFIC_ARRAY; - -/** - * Returns a model specific list of logical IDs. - * - * @param[out] LogicalIdXlat Installed logical ID table. - * @param[out] NumberOfElements Number of entries in the Logical ID translate table. - * @param[out] LogicalFamily Base logical family bit mask. - * @param[in] StdHeader Handle of Header for calling lib functions and services. - * - */ -typedef VOID F_CPU_GET_SUBFAMILY_ID_ARRAY ( - OUT CONST CPU_LOGICAL_ID_XLAT **LogicalIdXlat, - OUT UINT8 *NumberOfElements, - OUT UINT64 *LogicalFamily, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -/// Reference to a method. -typedef F_CPU_GET_SUBFAMILY_ID_ARRAY *PF_CPU_GET_SUBFAMILY_ID_ARRAY; - -/** - * Use the Mailbox Register to get the Ap Mailbox info for the current core. - * - * @CpuServiceInstances - * - * @param[in] FamilySpecificServices The current Family Specific Services. - * @param[out] ApMailboxInfo The AP Mailbox info - * @param[in] StdHeader Handle of Header for calling lib functions and services. - * - */ -typedef VOID (F_CPU_AMD_GET_AP_MAILBOX_FROM_HARDWARE) ( - IN CPU_SPECIFIC_SERVICES *FamilySpecificServices, - OUT AP_MAILBOXES *ApMailboxInfo, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -/// Reference to a method -typedef F_CPU_AMD_GET_AP_MAILBOX_FROM_HARDWARE *PF_CPU_AMD_GET_AP_MAILBOX_FROM_HARDWARE; - -/** - * Set the AP core number in the AP's Mailbox. - * - * @CpuServiceInstances - * - * @param[in] FamilySpecificServices The current Family Specific Services. - * @param[in] Socket The AP's socket - * @param[in] Module The AP's module - * @param[in] ApCoreNumber The AP's unique core number - * @param[in] StdHeader Handle of Header for calling lib functions and services. - * - */ -typedef VOID (F_CPU_SET_AP_CORE_NUMBER) ( - IN CPU_SPECIFIC_SERVICES *FamilySpecificServices, - IN UINT32 Socket, - IN UINT32 Module, - IN UINT32 ApCoreNumber, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -/// Reference to a method -typedef F_CPU_SET_AP_CORE_NUMBER *PF_CPU_SET_AP_CORE_NUMBER; - -/** - * Get the AP core number from hardware. - * - * @CpuServiceInstances - * - * @param[in] FamilySpecificServices The current Family Specific Services. - * @param[in] StdHeader Handle of Header for calling lib functions and services. - * - * @return The AP's unique core number - */ -typedef UINT32 (F_CPU_GET_AP_CORE_NUMBER) ( - IN CPU_SPECIFIC_SERVICES *FamilySpecificServices, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -/// Reference to a method -typedef F_CPU_GET_AP_CORE_NUMBER *PF_CPU_GET_AP_CORE_NUMBER; - -/** - * Move the AP's core number from the mailbox to hardware. - * - * @CpuServiceInstances - * - * @param[in] FamilySpecificServices The current Family Specific Services. - * @param[in] StdHeader Handle of Header for calling lib functions and services. - * - * @return The AP's unique core number - */ -typedef VOID (F_CPU_TRANSFER_AP_CORE_NUMBER) ( - IN CPU_SPECIFIC_SERVICES *FamilySpecificServices, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -/// Reference to a method -typedef F_CPU_TRANSFER_AP_CORE_NUMBER *PF_CPU_TRANSFER_AP_CORE_NUMBER; - -/** - * Core ID position in the initial APIC ID, reflected as a number zero or one. - */ -typedef enum { - CoreIdPositionZero, ///< Zero, the Core Id bits are the Most Significant bits. - CoreIdPositionOne, ///< One, the Core Id bits are the Least Significant bits. - CoreIdPositionMax ///< Limit check. -} CORE_ID_POSITION; - -/** - * Return a number zero or one, based on the Core ID position in the initial APIC Id. - * - * @CpuServiceInstances - * - * @param[in] FamilySpecificServices The current Family Specific Services. - * @param[in] StdHeader Handle of Header for calling lib functions and services. - * - * @retval CoreIdPositionZero Core Id is not low - * @retval CoreIdPositionOne Core Id is low - */ -typedef CORE_ID_POSITION F_CORE_ID_POSITION_IN_INITIAL_APIC_ID ( - IN CPU_SPECIFIC_SERVICES *FamilySpecificServices, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -/// Reference to a method -typedef F_CORE_ID_POSITION_IN_INITIAL_APIC_ID *PF_CORE_ID_POSITION_IN_INITIAL_APIC_ID; - -/** - * Get least common features set of all CPUs and save them to CPU_FEATURES_LIST - * - * @CpuServiceInstances - * - * @param[in] FamilySpecificServices The current Family Specific Services. - * @param[in,out] cpuFeatureListPtr The CPU Features List - * @param[in] StdHeader Handle of Header for calling lib functions and services. - * - */ -typedef VOID (F_CPU_SAVE_FEATURES) ( - IN CPU_SPECIFIC_SERVICES *FamilySpecificServices, - IN OUT CPU_FEATURES_LIST *cpuFeatureListPtr, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -/// Reference to a method -typedef F_CPU_SAVE_FEATURES *PF_CPU_SAVE_FEATURES; - -/** - * Get least common features from CPU_FEATURES_LIST and write them to CPU - * - * @CpuServiceInstances - * - * @param[in] FamilySpecificServices The current Family Specific Services. - * @param[in,out] cpuFeatureListPtr The CPU Features List - * @param[in] StdHeader Handle of Header for calling lib functions and services. - * - */ -typedef VOID (F_CPU_WRITE_FEATURES) ( - IN CPU_SPECIFIC_SERVICES *FamilySpecificServices, - IN OUT CPU_FEATURES_LIST *cpuFeatureListPtr, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -/// Reference to a method -typedef F_CPU_WRITE_FEATURES *PF_CPU_WRITE_FEATURES; - -/** - * Set Warm Reset Flag - * - * @CpuServiceInstances - * - * @param[in] FamilySpecificServices The current Family Specific Services. - * @param[in] StdHeader Header for library and services. - * @param[in] Request Value to set the flags to. - * - */ -typedef VOID (F_CPU_SET_WARM_RESET_FLAG) ( - IN CPU_SPECIFIC_SERVICES *FamilySpecificServices, - IN AMD_CONFIG_PARAMS *StdHeader, - IN WARM_RESET_REQUEST *Request - ); - -/// Reference to a method -typedef F_CPU_SET_WARM_RESET_FLAG *PF_CPU_SET_WARM_RESET_FLAG; - -/** - * Get Warm Reset Flag - * - * @CpuServiceInstances - * - * @param[in] FamilySpecificServices The current Family Specific Services. - * @param[in] StdHeader Header for library and services. - * @param[out] BiosRstDet Indicate warm reset status. - * - */ -typedef VOID (F_CPU_GET_WARM_RESET_FLAG) ( - IN CPU_SPECIFIC_SERVICES *FamilySpecificServices, - IN AMD_CONFIG_PARAMS *StdHeader, - OUT WARM_RESET_REQUEST *Request - ); - -/// Reference to a method -typedef F_CPU_GET_WARM_RESET_FLAG *PF_CPU_GET_WARM_RESET_FLAG; - - -/** - * Get CPU Specific Platform Type Info. - * - * @CpuServiceInstances - * - * @param[in] FamilySpecificServices The current Family Specific Services. - * @param[in,out] FeaturesUnion The Features supported by this platform. - * @param[in] StdHeader Handle of Header for calling lib functions and services. - * - */ -typedef AGESA_STATUS F_CPU_GET_PLATFORM_TYPE_SPECIFIC_INFO ( - IN CPU_SPECIFIC_SERVICES *FamilySpecificServices, - IN OUT PLATFORM_FEATS *FeaturesUnion, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -/// Reference to a Method. -typedef F_CPU_GET_PLATFORM_TYPE_SPECIFIC_INFO *PF_CPU_GET_PLATFORM_TYPE_SPECIFIC_INFO; - -/** - * Is the Northbridge PState feature enabled? - * - * @CpuServiceInstances - * - * @param[in] FamilySpecificServices The current Family Specific Services. - * @param[in] PlatformConfig Platform profile/build option config structure. - * @param[in] StdHeader Handle of Header for calling lib functions and services. - * - * @retval TRUE The NB PState feature is enabled. - * @retval FALSE The NB PState feature is not enabled. - */ -typedef BOOLEAN F_IS_NB_PSTATE_ENABLED ( - IN CPU_SPECIFIC_SERVICES *FamilySpecificServices, - IN PLATFORM_CONFIGURATION *PlatformConfig, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -/// Reference to a method -typedef F_IS_NB_PSTATE_ENABLED *PF_IS_NB_PSTATE_ENABLED; - -/** - * Gets the next link with features matching the HT phy register table entry type features. - * - * @CpuServiceInstances - * - * @param[in] FamilySpecificServices The current Family Specific Services. - * @param[in,out] HtHostCapability Initially the PCI bus, device, function=0, offset=0; - * Each call returns the HT Host Capability function and offset; - * Caller may use it to access registers, but must @b not modify it; - * Each new call passes the previous value as input. - * @param[in,out] Link Initially zero, each call returns the link number; caller passes it back unmodified each call. - * @param[in] HtPhyLinkType Link type field from a register table entry to compare against - * @param[out] MatchedSublink1 TRUE: It is actually just sublink 1 that matches, FALSE: any other condition. - * @param[out] Frequency0 The frequency of sublink0 (200 MHz if not connected). - * @param[out] Frequency1 The frequency of sublink1 (200 MHz if not connected). - * @param[in] StdHeader Standard Head Pointer - * - * @retval TRUE Link matches - * @retval FALSE No more links - * - */ -typedef BOOLEAN F_NEXT_LINK_HAS_HTFPY_FEATS ( - IN CPU_SPECIFIC_SERVICES *FamilySpecificServices, - IN OUT PCI_ADDR *HtHostCapability, - IN OUT UINT32 *Link, - IN HT_PHY_LINK_FEATS *HtPhyLinkType, - OUT BOOLEAN *MatchedSublink1, - OUT HT_FREQUENCIES *Frequency0, - OUT HT_FREQUENCIES *Frequency1, - IN AMD_CONFIG_PARAMS *StdHeader - ); -/// Reference to a Method. -typedef F_NEXT_LINK_HAS_HTFPY_FEATS *PF_NEXT_LINK_HAS_HTFPY_FEATS; - -/** - * Applies an HT Phy read-modify-write based on an HT Phy register table entry. - * - * @CpuServiceInstances - * - * @param[in] FamilySpecificServices The current Family Specific Services. - * @param[in] HtPhyEntry HT Phy register table entry to apply - * @param[in] CapabilitySet The link's HT Host base address. - * @param[in] Link Zero based, node, link number (not package link), always a sublink0 link. - * @param[in] StdHeader Config handle for library and services - * - */ -typedef VOID F_SET_HT_PHY_REGISTER ( - IN CPU_SPECIFIC_SERVICES *FamilySpecificServices, - IN HT_PHY_TYPE_ENTRY_DATA *HtPhyEntry, - IN PCI_ADDR CapabilitySet, - IN UINT32 Link, - IN AMD_CONFIG_PARAMS *StdHeader - ); -/// Reference to a Method. -typedef F_SET_HT_PHY_REGISTER *PF_SET_HT_PHY_REGISTER; - -/** - * Performs an early initialization function on the executing core. - * - * @param[in] FamilyServices The current Family Specific Services. - * @param[in] EarlyParams CPU module early paramters. - * @param[in] StdHeader Config handle for library and services - * - */ -typedef VOID F_PERFORM_EARLY_INIT_ON_CORE ( - IN CPU_SPECIFIC_SERVICES *FamilyServices, - IN AMD_CPU_EARLY_PARAMS *EarlyParams, - IN AMD_CONFIG_PARAMS *StdHeader - ); -/// Reference to a Method. -typedef F_PERFORM_EARLY_INIT_ON_CORE *PF_PERFORM_EARLY_INIT_ON_CORE; - -/** - * A struct that contains function pointer and function flag - * - * the flag indicates if the function need to be run. - */ -typedef struct _S_PERFORM_EARLY_INIT_ON_CORE { - PF_PERFORM_EARLY_INIT_ON_CORE PerformEarlyInitOnCore; ///< Function Pointer, which points to the function need to be run at early stage - UINT32 PerformEarlyInitFlag; ///< Function Flag, which indicates if the function need to be run. -} S_PERFORM_EARLY_INIT_ON_CORE; - -/** - * Returns the initialization steps that the executing core should - * perform at AmdInitEarly. - * - * @CpuServiceInstances - * - * @param[in] FamilyServices The current Family Specific Services. - * @param[out] Table Table of appropriate init steps for the executing core. - * @param[in] EarlyParams CPU module early paramters. - * @param[in] StdHeader Config handle for library and services - * - */ -typedef VOID F_GET_EARLY_INIT_TABLE ( - IN CPU_SPECIFIC_SERVICES *FamilyServices, - OUT CONST S_PERFORM_EARLY_INIT_ON_CORE **Table, - IN AMD_CPU_EARLY_PARAMS *EarlyParams, - IN AMD_CONFIG_PARAMS *StdHeader - ); -/// Reference to a Method. -typedef F_GET_EARLY_INIT_TABLE *PF_GET_EARLY_INIT_TABLE; - -/** - * Provide the features of the next HT link. - * - * @CpuServiceInstances - * - * This method is different than the HT Phy Features method, because for the phy registers - * sublink 1 matches and should be programmed if the link is ganged but for PCI config - * registers sublink 1 is reserved if the link is ganged. - * - * @param[in] FamilySpecificServices The current Family Specific Services. - * @param[in,out] Link The link number, for accessing non-capability set registers. - * Zero on initial call, and passed back unmodified on each subsequent call. - * @param[in,out] LinkBase IN: initially the node's PCI config base address, passed back on each call. - * OUT: the base HT Host capability PCI address for the link. - * @param[out] HtHostFeats The link's features. - * @param[in] StdHeader Standard Head Pointer - * - * @retval TRUE Valid link and features found. - * @retval FALSE No more links. - */ -typedef BOOLEAN F_GET_NEXT_HT_LINK_FEATURES ( - IN CPU_SPECIFIC_SERVICES *FamilySpecificServices, - IN OUT UINTN *Link, - IN OUT PCI_ADDR *LinkBase, - OUT HT_HOST_FEATS *HtHostFeats, - IN AMD_CONFIG_PARAMS *StdHeader - ); -/// Reference to a Method. -typedef F_GET_NEXT_HT_LINK_FEATURES *PF_GET_NEXT_HT_LINK_FEATURES; - -/// Cache Enable / Disable policy before giving control back to OS. -typedef enum { - InitCacheDisabled, ///StdHeader); - AmdParamApic->StdHeader.HeapBasePtr = HeapGetBaseAddress (&AmdParamApic->StdHeader); - - AmdParamApic->IsPresent = GetApicId ( - &AmdParamApic->StdHeader, - AmdParamApic->Socket, - AmdParamApic->Core, - &AmdParamApic->ApicAddress, - &AgesaStatus - ); - - AGESA_TESTPOINT (TpIfAmdGetApicIdExit, &AmdParamApic->StdHeader); - return AgesaStatus; -} - -/** - * Get Processor Module's PCI Config Space address. - * - * Invoke corresponding Cpu Service for external user. - * - * @param[in,out] AmdParamGetPci Our interface struct - * - * @return The most severe status of any called service. - */ -AGESA_STATUS -AmdGetPciAddress ( - IN OUT AMD_GET_PCI_PARAMS *AmdParamGetPci - ) -{ - AGESA_STATUS AgesaStatus; - - AGESA_TESTPOINT (TpIfAmdGetPciAddressEntry, &AmdParamGetPci->StdHeader); - AmdParamGetPci->StdHeader.HeapBasePtr = HeapGetBaseAddress (&AmdParamGetPci->StdHeader); - - AmdParamGetPci->IsPresent = GetPciAddress ( - &AmdParamGetPci->StdHeader, - AmdParamGetPci->Socket, - AmdParamGetPci->Module, - &AmdParamGetPci->PciAddress, - &AgesaStatus - ); - - AGESA_TESTPOINT (TpIfAmdGetPciAddressExit, &AmdParamGetPci->StdHeader); - return AgesaStatus; -} - -/** - * "Who am I" for the current running core. - * - * Invoke corresponding Cpu Service for external user. - * - * @param[in,out] AmdParamIdentify Our interface struct - * - * @return The most severe status of any called service. - */ -AGESA_STATUS -AmdIdentifyCore ( - IN OUT AMD_IDENTIFY_PARAMS *AmdParamIdentify - ) -{ - AGESA_STATUS AgesaStatus; - UINT32 Socket; - UINT32 Module; - UINT32 Core; - - AGESA_TESTPOINT (TpIfAmdIdentifyCoreEntry, &AmdParamIdentify->StdHeader); - AmdParamIdentify->StdHeader.HeapBasePtr = HeapGetBaseAddress (&AmdParamIdentify->StdHeader); - - IdentifyCore ( - &AmdParamIdentify->StdHeader, - &Socket, - &Module, - &Core, - &AgesaStatus - ); - AmdParamIdentify->Socket = (UINT8)Socket; - AmdParamIdentify->Module = (UINT8)Module; - AmdParamIdentify->Core = (UINT8)Core; - - AGESA_TESTPOINT (TpIfAmdIdentifyCoreExit, &AmdParamIdentify->StdHeader); - return AgesaStatus; -} - -/*---------------------------------------------------------------------------------------- - * E X P O R T E D F U N C T I O N S - AGESA common General Services - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------*/ -/** - * Get a specified Core's APIC ID. - * - * Code sync: This calculation MUST match the assignment - * calculation done in LocalApicInitializationAtEarly function. - * - * @param[in] StdHeader Header for library and services. - * @param[in] Socket The socket in which the Core's Processor is installed. - * @param[in] Core The Core id. - * @param[out] ApicAddress The Core's APIC ID. - * @param[out] AgesaStatus Aggregates AGESA_STATUS for external interface, Always Succeeds. - * - * @retval TRUE The core is present, APIC Id valid - * @retval FALSE The core is not present, APIC Id not valid. -*/ -BOOLEAN -GetApicId ( - IN AMD_CONFIG_PARAMS *StdHeader, - IN UINT32 Socket, - IN UINT32 Core, - OUT UINT8 *ApicAddress, - OUT AGESA_STATUS *AgesaStatus - ) -{ - BOOLEAN ReturnValue; - UINT32 CoreCount; - UINT32 ApicID; - - ReturnValue = FALSE; - if (GetActiveCoresInGivenSocket (Socket, &CoreCount, StdHeader)) { - if (Core < CoreCount) { - ReturnValue = TRUE; - GetLocalApicIdForCore (Socket, Core, &ApicID, StdHeader); - *ApicAddress = (UINT8) ApicID; - } - } - - // Always Succeeds. - *AgesaStatus = AGESA_SUCCESS; - - return ReturnValue; -} - -/*---------------------------------------------------------------------------------------*/ -/** - * Get Processor Module's PCI Config Space address. - * - * @param[in] StdHeader Header for library and services. - * @param[in] Socket The Core's Socket. - * @param[in] Module The Module in that Processor - * @param[out] PciAddress The Processor's PCI Config Space address (Function 0, Register 0) - * @param[out] AgesaStatus Aggregates AGESA_STATUS for external interface, Always Succeeds. - * - * @retval TRUE The core is present, PCI Address valid - * @retval FALSE The core is not present, PCI Address not valid. - */ -BOOLEAN -GetPciAddress ( - IN AMD_CONFIG_PARAMS *StdHeader, - IN UINT32 Socket, - IN UINT32 Module, - OUT PCI_ADDR *PciAddress, - OUT AGESA_STATUS *AgesaStatus - ) -{ - UINT8 Node; - BOOLEAN Result; - - ASSERT (Socket < MAX_SOCKETS); - ASSERT (Module < MAX_DIES); - - Result = TRUE; - // Always Succeeds. - *AgesaStatus = AGESA_SUCCESS; - - if (GetNodeId (Socket, Module, &Node, StdHeader)) { - // socket is populated - PciAddress->AddressValue = MAKE_SBDFO (0, 0, 24, 0, 0); - PciAddress->Address.Device = PciAddress->Address.Device + Node; - } else { - // socket is not populated - PciAddress->AddressValue = ILLEGAL_SBDFO; - Result = FALSE; - } - return Result; -} - -/*---------------------------------------------------------------------------------------*/ -/** - * "Who am I" for the current running core. - * - * @param[in] StdHeader Header for library and services. - * @param[out] Socket The current Core's Socket - * @param[out] Module The current Core's Processor Module - * @param[out] Core The current Core's core id. - * @param[out] AgesaStatus Aggregates AGESA_STATUS for external interface, Always Succeeds. - * - */ -VOID -IdentifyCore ( - IN AMD_CONFIG_PARAMS *StdHeader, - OUT UINT32 *Socket, - OUT UINT32 *Module, - OUT UINT32 *Core, - OUT AGESA_STATUS *AgesaStatus - ) -{ - AP_MAIL_INFO ApMailboxInfo; - UINT32 CurrentCore; - - // Always Succeeds. - *AgesaStatus = AGESA_SUCCESS; - - GetApMailbox (&ApMailboxInfo.Info, StdHeader); - ASSERT (ApMailboxInfo.Fields.Socket < MAX_SOCKETS); - ASSERT (ApMailboxInfo.Fields.Module < MAX_DIES); - *Socket = (UINT8)ApMailboxInfo.Fields.Socket; - *Module = (UINT8)ApMailboxInfo.Fields.Module; - - // Get Core Id - GetCurrentCore (&CurrentCore, StdHeader); - *Core = (UINT8)CurrentCore; -} - - -/*---------------------------------------------------------------------------------------- - * E X P O R T E D F U N C T I O N S - cpu component General Services - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------*/ -/** - * Get the current Platform's number of Sockets, regardless of how many are populated. - * - * The Options component can provide how many sockets are available in system. - * This can be used to avoid testing presence of Processors in Sockets which don't exist. - * The result can be one socket to the maximum possible sockets of any supported processor family. - * You cannot assume that all sockets contain a processor or that the sockets have processors - * installed in any particular order. Do not convert this number to a number of nodes. - * - * @return The number of available sockets for the platform. - * - */ -UINT32 -GetPlatformNumberOfSockets () -{ - return TopologyConfiguration.PlatformNumberOfSockets; -} - -/*---------------------------------------------------------------------------------------*/ -/** - * Get the number of Modules to check presence in each Processor. - * - * The Options component can provide how many modules need to be check for presence in each - * processor, regardless whether all, or any, processor have that many modules present on this boot. - * The result can be one module to the maximum possible modules of any supported processor family. - * You cannot assume that Modules are in any particular order, especially with respect to node id. - * - * @return The maximum number of modules in each processor. - * - */ -UINT32 -GetPlatformNumberOfModules () -{ - return TopologyConfiguration.PlatformNumberOfModules; -} - -/*---------------------------------------------------------------------------------------*/ -/** - * Is a processor present in Socket? - * - * Check to see if any possible module of the processor is present. This provides - * support for a few cases where a PCI address isn't needed, but code still needs to - * iterate by Socket. - * - * @param[in] Socket The socket which is being tested - * @param[in] StdHeader Header for library and services. - * - * @retval TRUE The socket has a processor installed - * @retval FALSE The socket is empty (or the processor is dead). - * - */ -BOOLEAN -IsProcessorPresent ( - IN UINT32 Socket, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - SOCKET_DIE_TO_NODE_MAP pSocketDieMap; - LOCATE_HEAP_PTR SocketDieHeapDataBlock; - BOOLEAN Result; - UINT32 Module; - AGESA_STATUS Status; - - ASSERT (Socket < MAX_SOCKETS); - Result = FALSE; - SocketDieHeapDataBlock.BufferHandle = SOCKET_DIE_MAP_HANDLE; - - // Get data block from heap - Status = HeapLocateBuffer (&SocketDieHeapDataBlock, StdHeader); - pSocketDieMap = (SOCKET_DIE_TO_NODE_MAP)SocketDieHeapDataBlock.BufferPtr; - ASSERT ((pSocketDieMap != NULL) && (Status == AGESA_SUCCESS)); - for (Module = 0; Module < GetPlatformNumberOfModules (); Module++) { - if ((*pSocketDieMap)[Socket][Module].Node != 0xFF) { - Result = TRUE; - break; - } - } - return Result; -} - -/*---------------------------------------------------------------------------------------*/ -/** - * Provide the number of installed processors (not Nodes! and not Sockets!) - * - * Iterate over the Socket, Module to Node Map, counting the number of present nodes. - * Do not use this as a Node Count! Do not use this as the number of Sockets! (This - * is for APIC ID utilities.) - * - * @param[in] StdHeader Header for library and services. - * - * @return the number of processors installed - * - */ -UINT32 -GetNumberOfProcessors ( - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - SOCKET_DIE_TO_NODE_MAP pSocketDieMap; - LOCATE_HEAP_PTR SocketDieHeapDataBlock; - UINT32 Result; - UINT32 Socket; - UINT32 Module; - AGESA_STATUS Status; - - Result = 0; - SocketDieHeapDataBlock.BufferHandle = SOCKET_DIE_MAP_HANDLE; - - // Get data block from heap - Status = HeapLocateBuffer (&SocketDieHeapDataBlock, StdHeader); - pSocketDieMap = (SOCKET_DIE_TO_NODE_MAP)SocketDieHeapDataBlock.BufferPtr; - ASSERT ((pSocketDieMap != NULL) && (Status == AGESA_SUCCESS)); - for (Socket = 0; Socket < GetPlatformNumberOfSockets (); Socket++) { - for (Module = 0; Module < GetPlatformNumberOfModules (); Module++) { - if ((*pSocketDieMap)[Socket][Module].Node != 0xFF) { - Result++; - break; - } - } - } - return Result; -} - -/*---------------------------------------------------------------------------------------*/ -/** - * For a specific Node, get its Socket and Module ids. - * - * If asking for the current running Node, read the mailbox socket, module. Specific Node, - * locate the Node to Socket/Module Map in heap, and return the ids, if present. - * - * @param[in] Node What Socket and Module is this Node? - * @param[out] Socket The Socket containing that Node. - * @param[out] Module The Processor Module of that Node. - * @param[in] StdHeader Header for library and services. - * - * @retval TRUE Node is present, Socket, Module are valid. - * @retval FALSE Node is not present, why do you ask? - */ -BOOLEAN -GetSocketModuleOfNode ( - IN UINT32 Node, - OUT UINT32 *Socket, - OUT UINT32 *Module, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - NODE_TO_SOCKET_DIE_MAP pNodeMap; - LOCATE_HEAP_PTR SocketDieHeapDataBlock; - BOOLEAN Result; - AGESA_STATUS Status; - - Result = FALSE; - - ASSERT (Node < MAX_NODES); - - // Get Map from heap - SocketDieHeapDataBlock.BufferHandle = NODE_ID_MAP_HANDLE; - Status = HeapLocateBuffer (&SocketDieHeapDataBlock, StdHeader); - pNodeMap = (NODE_TO_SOCKET_DIE_MAP)SocketDieHeapDataBlock.BufferPtr; - ASSERT ((pNodeMap != NULL) && (Status == AGESA_SUCCESS)); - *Socket = (*pNodeMap)[Node].Socket; - *Module = (*pNodeMap)[Node].Die; - if ((*pNodeMap)[Node].Socket != 0xFF) { - Result = TRUE; - } - return Result; -} - -/*---------------------------------------------------------------------------------------*/ -/** - * Get the current core's Processor APIC Index. - * - * The Processor APIC Index is the position of the current processor in the APIC id - * assignment. Processors are ordered in node id order. This is not the same, however, - * as the node id of the current socket and module or the current socket id. - * - * @param[in] Node The current desired core's node id (usually the current core). - * @param[in] StdHeader Header for library and services. - * - * @return Processor APIC Index - * - */ -UINT32 -GetProcessorApicIndex ( - IN UINT32 Node, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - UINT32 ProcessorApicIndex; - UINT32 PreviousSocket; - UINT32 CurrentSocket; - UINT32 Ignored; - UINT32 i; - - ASSERT (Node < MAX_NODES); - - // Calculate total APIC devices up to Current Node, Core. - ProcessorApicIndex = 0; - PreviousSocket = 0xFF; - for (i = 0; i < (Node + 1); i++) { - GetSocketModuleOfNode (i, &CurrentSocket, &Ignored, StdHeader); - if (CurrentSocket != PreviousSocket) { - ProcessorApicIndex++; - PreviousSocket = CurrentSocket; - } - } - // Convert to Index (zero based) from count (one based). - ProcessorApicIndex--; - return ProcessorApicIndex; -} - -/*---------------------------------------------------------------------------------------*/ -/** - * Returns current node number - * - * @param[out] Node This Core's Node id - * @param[in] StdHeader Header for library and services. - * - */ -VOID -GetCurrentNodeNum ( - OUT UINT32 *Node, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - AP_MAIL_INFO ApMailboxInfo; - - // Get the Node Id from the Mailbox. - GetApMailbox (&ApMailboxInfo.Info, StdHeader); - ASSERT (ApMailboxInfo.Fields.Node < MAX_NODES); - *Node = ApMailboxInfo.Fields.Node; -} - -/*---------------------------------------------------------------------------------------*/ -/** - * Writes to all nodes on the executing core's socket. - * - * @param[in] PciAddress The Function and Register to update - * @param[in] Mask The bitwise AND mask to apply to the current register value - * @param[in] Data The bitwise OR mask to apply to the current register value - * @param[in] StdHeader Header for library and services. - * - */ -VOID -ModifyCurrentSocketPci ( - IN PCI_ADDR *PciAddress, - IN UINT32 Mask, - IN UINT32 Data, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - UINT32 Socket; - UINT32 Module; - UINT32 Core; - UINT32 LocalPciRegister; - AGESA_STATUS AgesaStatus; - PCI_ADDR Reg; - - IdentifyCore (StdHeader, &Socket, &Module, &Core, &AgesaStatus); - - for (Module = 0; Module < (UINT8)GetPlatformNumberOfModules (); Module++) { - if (GetPciAddress (StdHeader, Socket, Module, &Reg, &AgesaStatus)) { - Reg.Address.Function = PciAddress->Address.Function; - Reg.Address.Register = PciAddress->Address.Register; - LibAmdPciRead (AccessWidth32, Reg, &LocalPciRegister, StdHeader); - LocalPciRegister &= Mask; - LocalPciRegister |= Data; - LibAmdPciWrite (AccessWidth32, Reg, &LocalPciRegister, StdHeader); - } - } -} - -/*---------------------------------------------------------------------------------------*/ -/** - * Returns Total number of active cores in the current socket - * - * @param[out] CoreCount The cores in this processor. - * @param[in] StdHeader Header for library and services. - * - */ -VOID -GetActiveCoresInCurrentSocket ( - OUT UINT32 *CoreCount, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - CPUID_DATA CpuidDataStruct; - UINT32 TotalCoresCount; - - LibAmdCpuidRead (AMD_CPUID_ASIZE_PCCOUNT, &CpuidDataStruct, StdHeader); - TotalCoresCount = (CpuidDataStruct.ECX_Reg & 0x000000FF) + 1; - *CoreCount = TotalCoresCount; -} - -/*---------------------------------------------------------------------------------------*/ -/** - * Provides the Total number of active cores in the current core's node. - * - * @param[in] StdHeader Header for library and services. - * - * @return The current node core count - */ -UINTN -GetActiveCoresInCurrentModule ( - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - UINT32 Socket; - UINT32 Module; - UINT32 Core; - UINT32 LowCore; - UINT32 HighCore; - UINT32 ProcessorCoreCount; - AGESA_STATUS AgesaStatus; - - ProcessorCoreCount = 0; - - IdentifyCore (StdHeader, &Socket, &Module, &Core, &AgesaStatus); - if (GetGivenModuleCoreRange (Socket, Module, &LowCore, &HighCore, StdHeader)) { - ProcessorCoreCount = ((HighCore - LowCore) + 1); - } - return ProcessorCoreCount; -} - -/** - * Provide the number of compute units on current module. - * - * - * @param[in] StdHeader Header for library and services. - * - * @return The current compute unit counts. - * - */ -UINTN -GetNumberOfCompUnitsInCurrentModule ( - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - UINT32 Socket; - UINT32 Module; - UINT32 CurrentCore; - UINT32 ComputeUnitCount; - UINT32 Enabled; - AGESA_STATUS IgnoredSts; - LOCATE_HEAP_PTR SocketDieHeapDataBlock; - SOCKET_DIE_TO_NODE_MAP pSocketDieMap; - - ComputeUnitCount = 0; - - ASSERT ((GetComputeUnitMapping (StdHeader) == AllCoresMapping) || - (GetComputeUnitMapping (StdHeader) == EvenCoresMapping)); - - IdentifyCore (StdHeader, &Socket, &Module, &CurrentCore, &IgnoredSts); - // Get data block from heap - SocketDieHeapDataBlock.BufferHandle = SOCKET_DIE_MAP_HANDLE; - IgnoredSts = HeapLocateBuffer (&SocketDieHeapDataBlock, StdHeader); - pSocketDieMap = (SOCKET_DIE_TO_NODE_MAP)SocketDieHeapDataBlock.BufferPtr; - ASSERT ((pSocketDieMap != NULL) && (IgnoredSts == AGESA_SUCCESS)); - // Current Core's socket, module must be present. - ASSERT ((*pSocketDieMap)[Socket][Module].Node != 0xFF); - // Process compute unit info - Enabled = (*pSocketDieMap)[Socket][Module].EnabledComputeUnits; - - while (Enabled > 0) { - if ((Enabled & 0x1) != 0) { - ComputeUnitCount++; - } - Enabled >>= 1; - } - - return ComputeUnitCount; -} - -/*---------------------------------------------------------------------------------------*/ -/** - * Provides the Total number of active cores in the given socket. - * - * @param[in] Socket Get a core count for the processor in this socket. - * @param[out] CoreCount Its core count - * @param[in] StdHeader Header for library and services. - * - * @retval TRUE A processor is present in the Socket and the CoreCount is valid. - * @retval FALSE The Socket does not have a Processor - */ -BOOLEAN -GetActiveCoresInGivenSocket ( - IN UINT32 Socket, - OUT UINT32 *CoreCount, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - UINT32 Module; - UINT32 LowCore; - UINT32 HighCore; - UINT32 ProcessorCoreCount; - BOOLEAN Result; - - Result = FALSE; - ProcessorCoreCount = 0; - - for (Module = 0; Module < GetPlatformNumberOfModules (); Module++) { - if (GetGivenModuleCoreRange (Socket, Module, &LowCore, &HighCore, StdHeader)) { - ProcessorCoreCount = ProcessorCoreCount + ((HighCore - LowCore) + 1); - Result = TRUE; - } else { - break; - } - } - *CoreCount = ProcessorCoreCount; - return Result; -} - -/*---------------------------------------------------------------------------------------*/ -/** - * Provides the range of Cores in a Processor which are in a Module. - * - * Cores are named uniquely in a processor, 0 to TotalCores. Any module in the processor has - * a set of those cores, named from LowCore to HighCore. - * - * @param[in] Socket Get a core range for the processor in this socket. - * @param[in] Module Get a core range for this Module in the processor. - * @param[out] LowCore The lowest Processor Core in the Module. - * @param[out] HighCore The highest Processor Core in the Module. - * @param[in] StdHeader Header for library and services. - * - * @retval TRUE A processor is present in the Socket and the Core Range is valid. - * @retval FALSE The Socket does not have a Processor - */ -BOOLEAN -GetGivenModuleCoreRange ( - IN UINT32 Socket, - IN UINT32 Module, - OUT UINT32 *LowCore, - OUT UINT32 *HighCore, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - SOCKET_DIE_TO_NODE_MAP pSocketDieMap; - LOCATE_HEAP_PTR SocketDieHeapDataBlock; - BOOLEAN Result; - AGESA_STATUS Status; - - ASSERT (Socket < MAX_SOCKETS); - ASSERT (Module < MAX_DIES); - Result = FALSE; - SocketDieHeapDataBlock.BufferHandle = SOCKET_DIE_MAP_HANDLE; - - // Get data block from heap - Status = HeapLocateBuffer (&SocketDieHeapDataBlock, StdHeader); - pSocketDieMap = (SOCKET_DIE_TO_NODE_MAP)SocketDieHeapDataBlock.BufferPtr; - ASSERT ((pSocketDieMap != NULL) && (Status == AGESA_SUCCESS)); - *LowCore = (*pSocketDieMap)[Socket][Module].LowCore; - *HighCore = (*pSocketDieMap)[Socket][Module].HighCore; - if ((*pSocketDieMap)[Socket][Module].Node != 0xFF) { - Result = TRUE; - } - return Result; -} - -/*---------------------------------------------------------------------------------------*/ -/** - * Returns the current running core number. - * - * @param[out] Core The core id. - * @param[in] StdHeader Header for library and services. - * - */ -VOID -GetCurrentCore ( - OUT UINT32 *Core, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - CPUID_DATA CpuidDataStruct; - UINT32 LocalApicId; - UINT32 ApicIdCoreIdSize; - CORE_ID_POSITION InitApicIdCpuIdLo; - CPU_SPECIFIC_SERVICES *FamilyServices; - - GetCpuServicesOfCurrentCore ((const CPU_SPECIFIC_SERVICES **)&FamilyServices, StdHeader); - ASSERT (FamilyServices != NULL); - - // Read CPUID ebx[31:24] to get initial APICID - LibAmdCpuidRead (AMD_CPUID_APICID_LPC_BID, &CpuidDataStruct, StdHeader); - LocalApicId = (CpuidDataStruct.EBX_Reg & 0xFF000000) >> 24; - - // Find the core ID size. - LibAmdCpuidRead (AMD_CPUID_ASIZE_PCCOUNT, &CpuidDataStruct, StdHeader); - ApicIdCoreIdSize = (CpuidDataStruct.ECX_Reg & 0x0000F000) >> 12; - - InitApicIdCpuIdLo = FamilyServices->CoreIdPositionInInitialApicId (FamilyServices, StdHeader); - ASSERT (InitApicIdCpuIdLo < CoreIdPositionMax); - - // Now extract the core ID from the Apic ID by right justifying the id and masking off non-core Id bits. - *Core = ((LocalApicId >> ((1 - (UINT32)InitApicIdCpuIdLo) * (MAX_CORE_ID_SIZE - ApicIdCoreIdSize))) & - (MAX_CORE_ID_MASK >> (MAX_CORE_ID_SIZE - ApicIdCoreIdSize))); -} - -/*---------------------------------------------------------------------------------------*/ -/** - * Returns current node, and core number. - * - * @param[out] Node The node id of the current core's node. - * @param[out] Core The core id if the current core. - * @param[in] StdHeader Config handle for library and services. - * - */ -VOID -GetCurrentNodeAndCore ( - OUT UINT32 *Node, - OUT UINT32 *Core, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - // Get Node Id - GetCurrentNodeNum (Node, StdHeader); - - // Get Core Id - GetCurrentCore (Core, StdHeader); -} - -/*---------------------------------------------------------------------------------------*/ -/** - * Is the current core a primary core of it's node? - * - * @param[in] StdHeader Config handle for library and services. - * - * @retval TRUE Is Primary Core - * @retval FALSE Is not Primary Core - * - */ -BOOLEAN -IsCurrentCorePrimary ( - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - BOOLEAN Result; - UINT32 Core; - UINT32 Socket; - UINT32 Module; - UINT32 PrimaryCore; - UINT32 IgnoredCore; - AGESA_STATUS IgnoredSts; - - Result = FALSE; - - IdentifyCore (StdHeader, &Socket, &Module, &Core, &IgnoredSts); - GetGivenModuleCoreRange (Socket, Module, &PrimaryCore, &IgnoredCore, StdHeader); - if (Core == PrimaryCore) { - Result = TRUE; - } - return Result; -} - - -/*---------------------------------------------------------------------------------------*/ -/** - * Returns node id based on SocketId and ModuleId. - * - * @param[in] SocketId The socket to look up - * @param[in] ModuleId The module in that socket - * @param[out] NodeId Provide the corresponding Node Id. - * @param[in] StdHeader Handle of Header for calling lib functions and services. - * - * @retval TRUE The socket is populated - * @retval FALSE The socket is not populated - * - */ -BOOLEAN -GetNodeId ( - IN UINT32 SocketId, - IN UINT32 ModuleId, - OUT UINT8 *NodeId, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - SOCKET_DIE_TO_NODE_MAP pSocketDieMap; - LOCATE_HEAP_PTR SocketDieHeapDataBlock; - BOOLEAN Result; - AGESA_STATUS Status; - - Result = FALSE; - SocketDieHeapDataBlock.BufferHandle = SOCKET_DIE_MAP_HANDLE; - - // Get data block from heap - Status = HeapLocateBuffer (&SocketDieHeapDataBlock, StdHeader); - pSocketDieMap = (SOCKET_DIE_TO_NODE_MAP)SocketDieHeapDataBlock.BufferPtr; - ASSERT ((pSocketDieMap != NULL) && (Status == AGESA_SUCCESS)); - *NodeId = (*pSocketDieMap)[SocketId][ModuleId].Node; - if ((*pSocketDieMap)[SocketId][ModuleId].Node != 0xFF) { - Result = TRUE; - } - return Result; -} - -/*---------------------------------------------------------------------------------------*/ -/** - * Get the cached AP Mailbox Info if available, or read the info from the hardware. - * - * Locate the known AP Mailbox Info Cache buffer in this core's local heap. If it - * doesn't exist, read the hardware to get the info. - * This routine gets the main AP mailbox, not the system degree. - * - * @param[out] ApMailboxInfo Provide the info in this AP core's mailbox - * @param[in] StdHeader Config handle for library and services. - * - */ -VOID -GetApMailbox ( - OUT UINT32 *ApMailboxInfo, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - AGESA_STATUS Ignored; - LOCATE_HEAP_PTR LocalApMailboxCache; - CPU_SPECIFIC_SERVICES *FamilyServices; - AP_MAILBOXES ApMailboxes; - BOOLEAN IamBsp; - - IamBsp = IsBsp (StdHeader, &Ignored); - LocalApMailboxCache.BufferHandle = LOCAL_AP_MAIL_BOX_CACHE_HANDLE; - if (((StdHeader->HeapStatus == HEAP_LOCAL_CACHE) || IamBsp) && - (HeapLocateBuffer (&LocalApMailboxCache, StdHeader) == AGESA_SUCCESS)) { - // If during HEAP_LOCAL_CACHE stage, we always try to get ApMailbox from heap - // If we're not in HEAP_LOCAL_CACHE stage, only BSP can get ApMailbox from heap - *ApMailboxInfo = ((AP_MAILBOXES *) LocalApMailboxCache.BufferPtr)->ApMailInfo.Info; - } else if (!IamBsp) { - // If this is an AP, the hardware register should be good. - GetCpuServicesOfCurrentCore ((const CPU_SPECIFIC_SERVICES **)&FamilyServices, StdHeader); - ASSERT (FamilyServices != NULL); - FamilyServices->GetApMailboxFromHardware (FamilyServices, &ApMailboxes, StdHeader); - *ApMailboxInfo = ApMailboxes.ApMailInfo.Info; - } else { - // This is the BSC. The hardware mailbox has not been set up yet. - ASSERT (FALSE); - } -} - -/*---------------------------------------------------------------------------------------*/ -/** - * Cache the Ap Mailbox info in our local heap for later use. - * - * This enables us to use the info even after the mailbox register is initialized - * with operational values. Get all the AP mailboxes and keep them in one buffer. - * - * @param[in] StdHeader Config handle for library and services. - * - */ -VOID -CacheApMailbox ( - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - ALLOCATE_HEAP_PARAMS AllocHeapParams; - AP_MAILBOXES ApMailboxes; - CPU_SPECIFIC_SERVICES *FamilyServices; - - GetCpuServicesOfCurrentCore ((const CPU_SPECIFIC_SERVICES **)&FamilyServices, StdHeader); - ASSERT (FamilyServices != NULL); - - // Get mailbox from hardware. - FamilyServices->GetApMailboxFromHardware (FamilyServices, &ApMailboxes, StdHeader); - - // Allocate heap for the info - AllocHeapParams.RequestedBufferSize = sizeof (AP_MAILBOXES); - AllocHeapParams.BufferHandle = LOCAL_AP_MAIL_BOX_CACHE_HANDLE; - AllocHeapParams.Persist = HEAP_SYSTEM_MEM; - if (HeapAllocateBuffer (&AllocHeapParams, StdHeader) == AGESA_SUCCESS) { - *(AP_MAILBOXES *)AllocHeapParams.BufferPtr = ApMailboxes; - } -} - -/*---------------------------------------------------------------------------------------*/ -/** - * Compute the degree of the system. - * - * The degree of a system is the maximum degree of any node. The degree of a node is the - * number of nodes to which it is directly connected (not considering width or redundant - * links). - * - * @param[in] StdHeader Config handle for library and services. - * - */ -UINTN -GetSystemDegree ( - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - AP_MAILBOXES *ApMailboxes; - LOCATE_HEAP_PTR LocalApMailboxCache; - AGESA_STATUS Status; - - // Get data block from heap - LocalApMailboxCache.BufferHandle = LOCAL_AP_MAIL_BOX_CACHE_HANDLE; - Status = HeapLocateBuffer (&LocalApMailboxCache, StdHeader); - // non-Success handled by ASSERT not NULL below. - ApMailboxes = (AP_MAILBOXES *)LocalApMailboxCache.BufferPtr; - ASSERT ((ApMailboxes != NULL) && (Status == AGESA_SUCCESS)); - return ApMailboxes->ApMailExtInfo.Fields.SystemDegree; -} - -/*---------------------------------------------------------------------------------------*/ -/** - * Spins until the number of microseconds specified have - * expired regardless of CPU operational frequency. - * - * @param[in] Microseconds Wait time in microseconds - * @param[in] StdHeader Header for library and services - * - */ -VOID -WaitMicroseconds ( - IN UINT32 Microseconds, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - UINT32 TscRateInMhz; - UINT64 NumberOfTicks; - UINT64 InitialTsc; - UINT64 CurrentTsc; - CPU_SPECIFIC_SERVICES *FamilySpecificServices; - - LibAmdMsrRead (TSC, &InitialTsc, StdHeader); - GetCpuServicesOfCurrentCore ((const CPU_SPECIFIC_SERVICES **)&FamilySpecificServices, StdHeader); - FamilySpecificServices->GetTscRate (FamilySpecificServices, &TscRateInMhz, StdHeader); - NumberOfTicks = Microseconds * TscRateInMhz; - do { - LibAmdMsrRead (TSC, &CurrentTsc, StdHeader); - } while ((CurrentTsc - InitialTsc) < NumberOfTicks); -} - -/*---------------------------------------------------------------------------------------*/ -/** - * A boolean function determine executed CPU is BSP core. - * - * @param[in,out] StdHeader Header for library and services - * @param[out] AgesaStatus Aggregates AGESA_STATUS for external interface, Always Succeeds. - * - */ -BOOLEAN -IsBsp ( - IN OUT AMD_CONFIG_PARAMS *StdHeader, - OUT AGESA_STATUS *AgesaStatus - ) -{ - UINT64 MsrData; - - // Always Succeeds. - *AgesaStatus = AGESA_SUCCESS; - - // Read APIC_BASE register (0x1B), bit[8] returns 1 for BSP - LibAmdMsrRead (MSR_APIC_BAR, &MsrData, StdHeader); - if ((MsrData & BIT8) != 0 ) { - return TRUE; - } else { - return FALSE; - } - -} - -/*---------------------------------------------------------------------------------------*/ -/** - * Get the compute unit mapping algorithm. - * - * Look up the compute unit values for the current core's socket/module and find the matching - * core pair map item. This will tell us how to determine the core's status. - * - * @param[in] StdHeader Header for library and services - * - * @retval AllCoresMapping Each core is in a compute unit of its own. - * @retval EvenCoresMapping Even/Odd pairs of cores are in each compute unit. - */ -COMPUTE_UNIT_MAPPING -GetComputeUnitMapping ( - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - UINT32 CurrentCore; - UINT32 Module; - UINT32 Socket; - UINT8 Enabled; - UINT8 DualCore; - AGESA_STATUS IgnoredSts; - SOCKET_DIE_TO_NODE_MAP pSocketDieMap; - LOCATE_HEAP_PTR SocketDieHeapDataBlock; - CPU_SPECIFIC_SERVICES *FamilyServices; - CORE_PAIR_MAP *CorePairMap; - COMPUTE_UNIT_MAPPING Result; - - // Invalid mapping, unless we find one. - Result = MaxComputeUnitMapping; - - IdentifyCore (StdHeader, &Socket, &Module, &CurrentCore, &IgnoredSts); - GetCpuServicesOfCurrentCore ((const CPU_SPECIFIC_SERVICES **)&FamilyServices, StdHeader); - ASSERT (FamilyServices != NULL); - - // Get data block from heap - SocketDieHeapDataBlock.BufferHandle = SOCKET_DIE_MAP_HANDLE; - IgnoredSts = HeapLocateBuffer (&SocketDieHeapDataBlock, StdHeader); - pSocketDieMap = (SOCKET_DIE_TO_NODE_MAP)SocketDieHeapDataBlock.BufferPtr; - ASSERT ((pSocketDieMap != NULL) && (IgnoredSts == AGESA_SUCCESS)); - // Current Core's socket, module must be present. - ASSERT ((*pSocketDieMap)[Socket][Module].Node != 0xFF); - - // Process compute unit info - Enabled = (*pSocketDieMap)[Socket][Module].EnabledComputeUnits; - DualCore = (*pSocketDieMap)[Socket][Module].DualCoreComputeUnits; - CorePairMap = FamilyServices->CorePairMap; - if ((Enabled != 0) && (CorePairMap != NULL)) { - while (CorePairMap->Enabled != 0xFF) { - if ((Enabled == CorePairMap->Enabled) && (DualCore == CorePairMap->DualCore)) { - break; - } - CorePairMap++; - } - // The assert is for finding a processor configured in a way the core pair map doesn't support. - ASSERT (CorePairMap->Enabled != 0xFF); - Result = CorePairMap->Mapping; - } else { - // Families that don't have compute units act as though each core is in its own compute unit - // and all cores are primary - Result = AllCoresMapping; - } - return Result; -} - -/*---------------------------------------------------------------------------------------*/ -/** - * Is current core the primary core of its compute unit? - * - * Get the mapping algorithm and the current core number. Selecting First/Last ordering for - * primary @b ASSUMES cores are launched in ascending core number order. - * - * @param[in] Selector Select whether first or last core has the primary core role. - * @param[in] StdHeader Header for library and services - * - * @retval TRUE This is the primary core of a compute unit. - * @retval FALSE This is the second shared core of a compute unit. - * - */ -BOOLEAN -IsCorePairPrimary ( - IN COMPUTE_UNIT_PRIMARY_SELECTOR Selector, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - BOOLEAN Result; - UINT32 CurrentCore; - UINT32 Module; - UINT32 Socket; - AGESA_STATUS IgnoredSts; - - IdentifyCore (StdHeader, &Socket, &Module, &CurrentCore, &IgnoredSts); - - Result = FALSE; - switch (GetComputeUnitMapping (StdHeader)) { - case AllCoresMapping: - // All cores are primaries - Result = TRUE; - break; - case EvenCoresMapping: - // Even core numbers are first to execute, odd cores are last to execute - if (Selector == FirstCoreIsComputeUnitPrimary) { - Result = (BOOLEAN) ((CurrentCore & 1) == 0); - } else { - Result = (BOOLEAN) ((CurrentCore & 1) != 0); - } - break; - default: - ASSERT (FALSE); - } - return Result; -} - -/*---------------------------------------------------------------------------------------*/ -/** - * Are the two specified cores shared in a compute unit? - * - * Look up the compute unit values for the current core's socket/module and find the matching - * core pair map item. This will tell us how to determine the core's status. - * - * @param[in] Socket The processor in this socket is to be checked - * @param[in] Module The processor in this module is to be checked - * @param[in] CoreA One of the two cores to check - * @param[in] CoreB The other core to be checked - * @param[in] StdHeader Header for library and services - * - * @retval TRUE The cores are in the same compute unit. - * @retval FALSE The cores are not in the same compute unit, or the processor does - * not have compute units. - * - */ -BOOLEAN -AreCoresPaired ( - IN UINT32 Socket, - IN UINT32 Module, - IN UINT32 CoreA, - IN UINT32 CoreB, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - BOOLEAN Result; - - Result = FALSE; - switch (GetComputeUnitMapping (StdHeader)) { - case AllCoresMapping: - // No cores are sharing a compute unit - Result = FALSE; - break; - case EvenCoresMapping: - // Even core numbers are paired with odd core numbers, n with n + 1 - if ((CoreA & 1) == 0) { - Result = (BOOLEAN) (CoreA == (CoreB - 1)); - } else { - Result = (BOOLEAN) (CoreA == (CoreB + 1)); - } - break; - default: - ASSERT (FALSE); - } - return Result; -} - -/*---------------------------------------------------------------------------------------*/ -/** - * - * This routine programs the registers necessary to get the PCI MMIO mechanism - * up and functioning. - * - * @param[in] StdHeader Pointer to structure containing the function call - * whose parameter structure is to be created, the - * allocation method, and a pointer to the newly - * created structure. - * - */ -VOID -InitializePciMmio ( - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - UINT8 EncodedSize; - UINT64 LocalMsrRegister; - - // Make sure that Standard header is valid - ASSERT (StdHeader != NULL); - - if ((UserOptions.CfgPciMmioAddress != 0) && (UserOptions.CfgPciMmioSize != 0)) { - EncodedSize = LibAmdBitScanForward (UserOptions.CfgPciMmioSize); - LocalMsrRegister = ((UserOptions.CfgPciMmioAddress | BIT0) | (EncodedSize << 2)); - LibAmdMsrWrite (MSR_MMIO_Cfg_Base, &LocalMsrRegister, StdHeader); - } -} diff --git a/src/vendorcode/amd/agesa/f12/Proc/CPU/cpuInitEarlyTable.c b/src/vendorcode/amd/agesa/f12/Proc/CPU/cpuInitEarlyTable.c deleted file mode 100644 index 0883d201d9..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/CPU/cpuInitEarlyTable.c +++ /dev/null @@ -1,125 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * Initialize the 'common' way of running early initialization. - * - * Returns the table of initialization steps to perform at - * AmdInitEarly. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: CPU - * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $ - * - */ -/* - ****************************************************************************** - * - * Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - ****************************************************************************** - */ - -/*---------------------------------------------------------------------------------------- - * M O D U L E S U S E D - *---------------------------------------------------------------------------------------- - */ -#include "AGESA.h" -#include "cpuFamilyTranslation.h" -#include "Filecode.h" -#include "cpuEarlyInit.h" -CODE_GROUP (G1_PEICC) -RDATA_GROUP (G1_PEICC) - -#define FILECODE PROC_CPU_CPUINITEARLYTABLE_FILECODE - - -/*---------------------------------------------------------------------------------------- - * D E F I N I T I O N S A N D M A C R O S - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------- - * T Y P E D E F S A N D S T R U C T U R E S - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------- - * P R O T O T Y P E S O F L O C A L F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------- - * E X P O R T E D F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ -VOID -GetCommonEarlyInitOnCoreTable ( - IN CPU_SPECIFIC_SERVICES *FamilyServices, - OUT CONST S_PERFORM_EARLY_INIT_ON_CORE **Table, - IN AMD_CPU_EARLY_PARAMS *EarlyParams, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -extern F_PERFORM_EARLY_INIT_ON_CORE McaInitializationAtEarly; -extern F_PERFORM_EARLY_INIT_ON_CORE SetRegistersFromTablesAtEarly; -extern F_PERFORM_EARLY_INIT_ON_CORE SetBrandIdRegistersAtEarly; -extern F_PERFORM_EARLY_INIT_ON_CORE LocalApicInitializationAtEarly; -extern F_PERFORM_EARLY_INIT_ON_CORE LoadMicrocodePatchAtEarly; - -CONST S_PERFORM_EARLY_INIT_ON_CORE ROMDATA CommonEarlyInitOnCoreTable[] = -{ - {McaInitializationAtEarly, PERFORM_EARLY_ANY_CONDITION}, - {SetRegistersFromTablesAtEarly, PERFORM_EARLY_ANY_CONDITION}, - {SetBrandIdRegistersAtEarly, PERFORM_EARLY_ANY_CONDITION}, - {LocalApicInitializationAtEarly, PERFORM_EARLY_ANY_CONDITION}, - {LoadMicrocodePatchAtEarly, PERFORM_EARLY_ANY_CONDITION}, - {NULL, 0} -}; - -/*------------------------------------------------------------------------------------*/ -/** - * Initializer routine that may be invoked at AmdCpuEarly to return the steps that a - * processor that uses the standard initialization steps should take. - * - * @CpuServiceMethod{::F_GET_EARLY_INIT_TABLE}. - * - * @param[in] FamilyServices The current Family Specific Services. - * @param[out] Table Table of appropriate init steps for the executing core. - * @param[in] EarlyParams Service Interface structure to initialize. - * @param[in] StdHeader Opaque handle to standard config header. - * - */ -VOID -GetCommonEarlyInitOnCoreTable ( - IN CPU_SPECIFIC_SERVICES *FamilyServices, - OUT CONST S_PERFORM_EARLY_INIT_ON_CORE **Table, - IN AMD_CPU_EARLY_PARAMS *EarlyParams, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - *Table = CommonEarlyInitOnCoreTable; -} diff --git a/src/vendorcode/amd/agesa/f12/Proc/CPU/cpuLateInit.c b/src/vendorcode/amd/agesa/f12/Proc/CPU/cpuLateInit.c deleted file mode 100644 index 618a4a6538..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/CPU/cpuLateInit.c +++ /dev/null @@ -1,284 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * AMD CPU Late Init API - * - * Contains code for doing any late CPU initialization. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: CPU - * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $ - * - */ -/* - ****************************************************************************** - * - * Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - ****************************************************************************** - */ - -/*---------------------------------------------------------------------------------------- - * M O D U L E S U S E D - *---------------------------------------------------------------------------------------- - */ -#include "AGESA.h" -#include "amdlib.h" -#include "Ids.h" -#include "cpuLateInit.h" -#include "cpuRegisters.h" -#include "GeneralServices.h" -#include "cpuServices.h" -#include "Filecode.h" -CODE_GROUP (G3_DXE) -RDATA_GROUP (G3_DXE) - -#define FILECODE PROC_CPU_CPULATEINIT_FILECODE -/*---------------------------------------------------------------------------------------- - * D E F I N I T I O N S A N D M A C R O S - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------- - * T Y P E D E F S A N D S T R U C T U R E S - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------- - * P R O T O T Y P E S O F L O C A L F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ -VOID -DisableCf8ExtCfg ( - IN AMD_CONFIG_PARAMS *StdHeader - ); -/*---------------------------------------------------------------------------------------- - * E X P O R T E D F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ - - -/*---------------------------------------------------------------------------------------*/ -/** - * Performs CPU related initialization at the late entry point - * - * This function should be the last function run by the AGESA - * CPU module and prepares the processor for the operating system - * bootstrap load process. - * - * @param[in] StdHeader Config handle for library and services - * - * @retval AGESA_SUCCESS - * - */ -AGESA_STATUS -AmdCpuLate ( - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - DisableCf8ExtCfg (StdHeader); - return (AGESA_SUCCESS); -} - -/*---------------------------------------------------------------------------------------*/ -/** - * Clear EnableCf8ExtCfg on all socket - * - * Clear F3x8C bit 14 EnableCf8ExtCfg - * - * @param[in] StdHeader Config handle for library and services - * - * - */ -VOID -DisableCf8ExtCfg ( - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - AGESA_STATUS AgesaStatus; - PCI_ADDR PciAddress; - UINT32 Socket; - UINT32 Module; - UINT32 PciData; - UINT32 LegacyPciAccess; - - ASSERT (IsBsp (StdHeader, &AgesaStatus)); - - for (Socket = 0; Socket < GetPlatformNumberOfSockets (); Socket++) { - for (Module = 0; Module < GetPlatformNumberOfModules (); Module++) { - if (GetPciAddress (StdHeader, Socket, Module, &PciAddress, &AgesaStatus)) { - PciAddress.Address.Function = FUNC_3; - PciAddress.Address.Register = NB_CFG_HIGH_REG; - LegacyPciAccess = ((1 << 31) + (PciAddress.Address.Register & 0xFC) + (PciAddress.Address.Function << 8) + (PciAddress.Address.Device << 11) + (PciAddress.Address.Bus << 16) + ((PciAddress.Address.Register & 0xF00) << (24 - 8))); - // read from PCI register - LibAmdIoWrite (AccessWidth32, IOCF8, &LegacyPciAccess, StdHeader); - LibAmdIoRead (AccessWidth32, IOCFC, &PciData, StdHeader); - // Disable Cf8ExtCfg - PciData &= 0xFFFFBFFF; - // write to PCI register - LibAmdIoWrite (AccessWidth32, IOCF8, &LegacyPciAccess, StdHeader); - LibAmdIoWrite (AccessWidth32, IOCFC, &PciData, StdHeader); - } - } - } -} - -/*---------------------------------------------------------------------------------------*/ -/** - * Calculate an ACPI style checksum - * - * Computes the checksum and stores the value to the checksum - * field of the passed in ACPI table's header. - * - * @param[in] Table ACPI table to checksum - * @param[in] StdHeader Config handle for library and services - * - */ -VOID -ChecksumAcpiTable ( - IN OUT ACPI_TABLE_HEADER *Table, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - UINT8 *BuffTempPtr; - UINT8 Checksum; - UINT32 BufferOffset; - - Table->Checksum = 0; - Checksum = 0; - BuffTempPtr = (UINT8 *) Table; - for (BufferOffset = 0; BufferOffset < Table->TableLength; BufferOffset++) { - Checksum = Checksum - *(BuffTempPtr + BufferOffset); - } - - Table->Checksum = Checksum; -} - -/*---------------------------------------------------------------------------------------*/ -/** - * - * Run code on every AP in the system. - * - * @param[in] ApParams AP task pointer. - * @param[in] StdHeader Handle to config for library and services - * - * @return The most severe AGESA_STATUS returned by an AP. - * - */ -AGESA_STATUS -RunLateApTaskOnAllAPs ( - IN AP_EXE_PARAMS *ApParams, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - UINT32 NumberOfSockets; - UINT32 NumberOfCores; - UINT8 Socket; - UINT8 Core; - UINT8 ApicId; - UINT32 BscSocket; - UINT32 Ignored; - UINT32 BscCoreNum; - AGESA_STATUS CalledStatus; - AGESA_STATUS IgnoredStatus; - AGESA_STATUS AgesaStatus; - - ASSERT (IsBsp (StdHeader, &IgnoredStatus)); - - AgesaStatus = AGESA_SUCCESS; - - IdentifyCore (StdHeader, &BscSocket, &Ignored, &BscCoreNum, &IgnoredStatus); - NumberOfSockets = GetPlatformNumberOfSockets (); - - for (Socket = 0; Socket < NumberOfSockets; Socket++) { - if (GetActiveCoresInGivenSocket (Socket, &NumberOfCores, StdHeader)) { - for (Core = 0; Core < NumberOfCores; Core++) { - if ((Socket != BscSocket) || (Core != BscCoreNum)) { - GetApicId (StdHeader, Socket, Core, &ApicId, &IgnoredStatus); - AGESA_TESTPOINT (TpIfBeforeRunApFromAllAps, StdHeader); - CalledStatus = AgesaRunFcnOnAp ((UINTN) ApicId, ApParams); - AGESA_TESTPOINT (TpIfAfterRunApFromAllAps, StdHeader); - if (CalledStatus > AgesaStatus) { - AgesaStatus = CalledStatus; - } - } - } - } - } - return AgesaStatus; -} - - -/*---------------------------------------------------------------------------------------*/ -/** - * - * Run code on core 0 of every socket in the system. - * - * @param[in] ApParams AP task pointer. - * @param[in] StdHeader Handle to config for library and services - * - * @return The most severe AGESA_STATUS returned by an AP. - * - */ -AGESA_STATUS -RunLateApTaskOnAllCore0s ( - IN AP_EXE_PARAMS *ApParams, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - UINT32 NumberOfSockets; - UINT8 Socket; - UINT8 ApicId; - UINT32 BscSocket; - UINT32 IgnoredModule; - UINT32 IgnoredCore; - AGESA_STATUS CalledStatus; - AGESA_STATUS IgnoredStatus; - AGESA_STATUS AgesaStatus; - - ASSERT (IsBsp (StdHeader, &IgnoredStatus)); - - AgesaStatus = AGESA_SUCCESS; - - IdentifyCore (StdHeader, &BscSocket, &IgnoredModule, &IgnoredCore, &IgnoredStatus); - NumberOfSockets = GetPlatformNumberOfSockets (); - - for (Socket = 0; Socket < NumberOfSockets; Socket++) { - if (IsProcessorPresent (Socket, StdHeader)) { - if (Socket != BscSocket) { - GetApicId (StdHeader, Socket, 0, &ApicId, &IgnoredStatus); - AGESA_TESTPOINT (TpIfBeforeRunApFromAllCore0s, StdHeader); - CalledStatus = AgesaRunFcnOnAp ((UINTN) ApicId, ApParams); - AGESA_TESTPOINT (TpIfAfterRunApFromAllCore0s, StdHeader); - if (CalledStatus > AgesaStatus) { - AgesaStatus = CalledStatus; - } - } - } - } - return AgesaStatus; -} diff --git a/src/vendorcode/amd/agesa/f12/Proc/CPU/cpuLateInit.h b/src/vendorcode/amd/agesa/f12/Proc/CPU/cpuLateInit.h deleted file mode 100644 index b871845870..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/CPU/cpuLateInit.h +++ /dev/null @@ -1,858 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * AMD CPU Late Init API functions Prototypes. - * - * Contains code for doing any late CPU initialization - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: CPU - * @e \$Revision: 48773 $ @e \$Date: 2011-03-11 07:04:05 +0800 (Fri, 11 Mar 2011) $ - * - */ -/* - ****************************************************************************** - * - * Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - ****************************************************************************** - */ - -#ifndef _CPU_LATE_INIT_H_ -#define _CPU_LATE_INIT_H_ - -#include "Filecode.h" - -// Forward declaration needed for multi-structure mutual references. -AGESA_FORWARD_DECLARATION (PROC_FAMILY_TABLE); -/*---------------------------------------------------------------------------------------- - * M I X E D (Definitions And Macros / Typedefs, Structures, Enums) - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------- - * D E F I N I T I O N S A N D M A C R O S - *---------------------------------------------------------------------------------------- - */ -//---------------------------------------------------------------------------- -// DMI DEFINITIONS AND MACROS -// -//---------------------------------------------------------------------------- -#define AP_LATE_TASK_GET_TYPE4_TYPE7 (PROC_CPU_FEATURE_CPUDMI_FILECODE) -// SMBIOS constant definition -#define CENTRAL_PROCESSOR 0x03 -#define EXTERNAL_CLOCK_DFLT 200 -#define EXTERNAL_CLOCK_100MHZ 100 -#define P_FAMILY_UNKNOWN 0x02 -#define P_CHARACTERISTICS 0x4 -#define CACHE_CFG_L1 0x180 -#define CACHE_CFG_L2 0x181 -#define CACHE_CFG_L3 0x182 -#define SRAM_TYPE 0x10 -#define ERR_CORRECT_TYPE 0x06 -#define CACHE_TYPE 0x05 -#define ASSOCIATIVE_2_WAY 0x04 -#define ASSOCIATIVE_16_WAY 0x08 -#define ASSOCIATIVE_OTHER 0x01 -#define SOCKET_POPULATED 0x40 -#define CPU_STATUS_UNKNOWN 0x00 -#define CPU_STATUS_ENABLED 0x01 - -// Processor Upgrade Definition -#define P_UPGRADE_UNKNOWN 0x02 -#define P_UPGRADE_NONE 0x06 -#define P_UPGRADE_S1GX 0x16 -#define P_UPGRADE_AM2 0x17 -#define P_UPGRADE_F1207 0x18 -#define P_UPGRADE_G34 0x1A -#define P_UPGRADE_AM3 0x1B -#define P_UPGRADE_C32 0x1C -#define P_UPGRADE_FS1 0x27 -#define P_UPGRADE_FM1 0x29 - -//---------------------------------------------------------------------------- -// SRAT DEFINITIONS AND MACROS -// -//---------------------------------------------------------------------------- -#define NorthbridgeCapabilities 0xE8 -#define DRAMBase0 0x40 -#define MMIOBase0 0x80 -#define TOP_MEM 0xC001001Aul -#define LOW_NODE_DEVICEID 24 -#define LOW_APICID 0 - - -// Miscellaneous AMD related values -#define MAX_NUMBER_NODES 8 - -// Flags -#define ENABLED 1 // Bit 0 -#define DISABLED 0 // Bit 0 -#define HOTPLUGGABLE 2 // Bit 1 - -// Affinity Entry Structures -#define AE_APIC 0 -#define AE_MEMORY 1 - - -// Memory Types -#define TYPE_MEMORY 1 -#define TYPE_RESERVED 2 -#define TYPE_ACPI 3 -#define TYPE_NVS 4 - -//---------------------------------------------------------------------------- -// SLIT DEFINITIONS AND MACROS -// -//---------------------------------------------------------------------------- -#define PROBE_FILTER_CTRL_REG 0x1D4 -#define AMD_ACPI_SLIT_SOCKET_NUM_LENGTH 8 - -//---------------------------------------------------------------------------- -// P-STATE DEFINITIONS AND MACROS -// -//---------------------------------------------------------------------------- -//------------------------------------- -// ERROR Codes -//------------------------------------- -#define NO_ERROR 0x0 -#define USER_DISABLE_ERROR 0x01 // User disabled SSDT generation -#define CORES_MISSMATCH_PSS_ERROR 0x02 // No PSS match -#define PNOW_SUPPORT_ERROR 0x04 // One of the Cores do not support PNOW! -#define PWR_FREQ_MATCH_ERROR 0x08 // FREQ and PWR mismatch -#define NO_PSS_SIZE_ERROR 0x10 // Error in PSS Size -#define INVALID_PSTATE_ERROR 0x20 // Invalid Max or only 1 P-State available -#define NO_PSS_ENTRY 0x0FFFF -#define INVALID_FREQ 0x0FFFFFFFF - -//------------------------- -// Default definitions -// AMD BKDG default values -//------------------------- -#define DEFAULT_ISOCH_RELIEF_TIME IRT_80uS -#define DEFAULT_RAMP_VOLTAGE_OFFSET RVO_50mV -#define DEFAULT_MAX_VOLTAGE_STEP MVS_25mV -#define DEFAULT_PERF_PRESENT_CAP 0 // default for Desktop -#define DEFAULT_VOLTAGE_STABLE_TIME (100 / 20) // 100uS -#define DEFAULT_PLL_LOCK_TIME 2 // 2uS -#define DEFAULT_TRANSITION_LATENCY 100 // 100uS -#define DEFAULT_BUS_MASTER_LATENCY 9 // 9uS -#define DEFAULT_CPU_SCOPE_NUMBER "0UPC" - -// Defines for Common ACPI -// ----------------------------- -#define SCOPE_OPCODE 0x10 -#define NAME_OPCODE 0x08 -#define METHOD_OPCODE 0x14 -#define PACKAGE_OPCODE 0x12 -#define BUFFER_OPCODE 0x11 -#define BYTE_PREFIX_OPCODE 0x0A -#define WORD_PREFIX_OPCODE 0x0B -#define DWORD_PREFIX_OPCODE 0x0C -#define RETURN_OPCODE 0xA4 -#define ACPI_BUFFER 0x080A0B11 - -// Generic Register Descriptor (GDR) Fields -#define GDR_ASI_SYSTEM_IO 0x01 // Address Space ID -#define GDR_ASZ_BYTE_ACCESS 0x01 // Address Size - -// Defines for ACPI Scope Table -// ---------------------------- -#define SCOPE_LENGTH (SCOPE_STRUCT_SIZE + \ - PCT_STRUCT_SIZE + \ - PSS_HEADER_STRUCT_SIZE + \ - PSS_BODY_STRUCT_SIZE + \ - PPC_HEADER_BODY_STRUCT_SIZE) -#define SCOPE_VALUE1 0x5C -#define SCOPE_VALUE2 0x2E -#define SCOPE_NAME__ '_' -#define SCOPE_NAME_P 'P' -#define SCOPE_NAME_R 'R' -#define SCOPE_NAME_S 'S' -#define SCOPE_NAME_B 'B' -#define SCOPE_NAME_C 'C' -#define SCOPE_NAME_U 'U' -#define SCOPE_NAME_0 '0' -#define SCOPE_NAME_1 '1' -#define SCOPE_NAME_2 '2' -#define SCOPE_NAME_3 '3' -#define SCOPE_NAME_A 'A' - -#ifdef OEM_SCOPE_NAME - #if (OEM_SCOPE_NAME > 'Z') || (OEM_SCOPE_NAME < 'A') - #error "OEM_SCOPE_NAME: it should be only one char long AND a valid letter (A~Z)" - #endif - #define SCOPE_NAME_VALUE OEM_SCOPE_NAME -#else - #define SCOPE_NAME_VALUE SCOPE_NAME_C -#endif // OEM_SCOPE_NAME - -#ifdef OEM_SCOPE_NAME1 - #if (!(((OEM_SCOPE_NAME1 >= 'A') && (OEM_SCOPE_NAME1 <= 'Z')) || \ - ((OEM_SCOPE_NAME1 >= '0') && (OEM_SCOPE_NAME1 <= '9')) || \ - (OEM_SCOPE_NAME1 == '_'))) - #error "OEM_SCOPE_NAME1: it should be only one char long AND a valid letter (0~9, A~F)" - #endif - #define SCOPE_NAME_VALUE1 OEM_SCOPE_NAME1 -#else - #define SCOPE_NAME_VALUE1 SCOPE_NAME_0 -#endif // OEM_SCOPE_NAME - -// Defines for PCT Control and Status Table -// ---------------------------------------- -#define PCT_NAME__ '_' -#define PCT_NAME_P 'P' -#define PCT_NAME_C 'C' -#define PCT_NAME_T 'T' -#define PCT_VALUE1 0x11022C12 -#define PCT_VALUE2 0x0A14 -#define PCT_VALUE3 0x11 -#define GENERIC_REG_DESCRIPTION 0x82 -#define PCT_LENGTH 0x0C -#define PCT_ADDRESS_SPACE_ID 0x7F -#define PCT_REGISTER_BIT_WIDTH 0x40 -#define PCT_REGISTER_BIT_OFFSET 0x00 -#define PCT_RESERVED 0x00 -#define PCT_CONTROL_REG_LO 0xC0010062 -#define PCT_CONTROL_REG_HI 0x00 -#define PCT_VALUE4 0x14110079 -#define PCT_VALUE5 0x110A -#define PCT_STATUS_REG_LO 0x00 -#define PCT_STATUS_REG_HI 0x00 -#define PCT_VALUE6 0x0079 - - -// Defines for PSS Header Table -// ---------------------------- -#define PSS_NAME__ '_' -#define PSS_NAME_X 'X' -#define PSS_NAME_P 'P' -#define PSS_NAME_S 'S' -#define PSS_LENGTH (sizeof pssBodyStruct + 3) -#define NUM_OF_ITEMS_IN_PSS 0x00 - - -// Defines for PSS Header Table -// ---------------------------- -#define PSS_PKG_LENGTH 0x20 // PSS_BODY_STRUCT_SIZE - 1 -#define PSS_NUM_OF_ELEMENTS 0x06 -#define PSS_FREQUENCY 0x00 -#define PSS_POWER 0x00 -#define PSS_TRANSITION_LATENCY DEFAULT_TRANSITION_LATENCY -#define PSS_BUS_MASTER_LATENCY DEFAULT_BUS_MASTER_LATENCY -#define PSS_CONTROL ((DEFAULT_ISOCH_RELIEF_TIME << 30) + \ - (DEFAULT_RAMP_VOLTAGE_OFFSET << 28) + \ - (DEFAULT_EXT_TYPE << 27) + \ - (DEFAULT_PLL_LOCK_TIME << 20) + \ - (DEFAULT_MAX_VOLTAGE_STEP << 18) + \ - (DEFAULT_VOLTAGE_STABLE_TIME << 11) + \ - (PSS_VID << 6) + PSS_FID) -#define PSS_STATUS (DEFAULT_EXTENDED_TYPE << 11) + (PSS_VID << 6) + (PSS_FID) - -// Defines for XPSS Header Table -// ---------------------------- -#define XPSS_PKG_LENGTH 0x47 // XPSS_BODY_STRUCT_SIZE - 1 -#define XPSS_NUM_OF_ELEMENTS 0x08 -#define XPSS_ACPI_BUFFER 0x080A0B11 - - -// Defines for PPC Header Table -// ---------------------------- -#define PPC_NAME__ '_' -#define PPC_NAME_P 'P' -#define PPC_NAME_C 'C' -#define PPC_METHOD_FLAGS 0x00; -#define PPC_VALUE1 0x0A; - -// Defines for PSD Header Table -// ---------------------------- -#define PSD_NAME__ '_' -#define PSD_NAME_P 'P' -#define PSD_NAME_S 'S' -#define PSD_NAME_D 'D' -#define PSD_HEADER_LENGTH (PSD_BODY_STRUCT_SIZE + 2) -#define PSD_VALUE1 0x01 - - -// Defines for PSD Header Table -// ---------------------------- -#define PSD_PKG_LENGTH (PSD_BODY_STRUCT_SIZE - 1) -#define NUM_OF_ENTRIES 0x05 -#define PSD_NUM_OF_ENTRIES 0x05 -#define PSD_REVISION 0x00 -#define PSD_DEPENDENCY_DOMAIN 0x00 -#define PSD_COORDINATION_TYPE_HW_ALL 0xFE -#define PSD_COORDINATION_TYPE_SW_ANY 0xFD -#define PSD_COORDINATION_TYPE_SW_ALL 0xFC -#define PSD_NUM_OF_PROCESSORS 0x01 -#define PSD_CORE_NUM_PER_COMPUTE_UNIT 0x02 -#define PSD_DOMAIN_COMPUTE_UNIT_MASK 0x7F - - -#define CUSTOM_PSTATE_FLAG 0x55 -#define PSTATE_FLAG_1 0x55 -#define TARGET_PSTATE_FLAG 0xAA -#define PSTATE_FLAG_2 0xAA - -/*---------------------------------------------------------------------------------------- - * T Y P E D E F S, S T R U C T U R E S, E N U M S - *---------------------------------------------------------------------------------------- - */ -//---------------------------------------------------------------------------- -// ACPI P-States AML TYPEDEFS, STRUCTURES, ENUMS -// -//---------------------------------------------------------------------------- - -//-------------------------------------------- -// AML code definition -// (Scope) -//--------------------------------------------- -/// SCOPE -typedef struct _SCOPE { - UINT8 ScopeOpcode; ///< Opcode - UINT16 ScopeLength; ///< Scope Length - UINT8 ScopeValue1; ///< Value1 - UINT8 ScopeValue2; ///< Value2 - UINT8 ScopeNamePt1a__; ///< Name Pointer - UINT8 ScopeNamePt1a_P; ///< Name Pointer - UINT8 ScopeNamePt1a_R; ///< Name Pointer - UINT8 ScopeNamePt1b__; ///< Name Pointer - UINT8 ScopeNamePt2a_C; ///< Name Pointer - UINT8 ScopeNamePt2a_P; ///< Name Pointer - UINT8 ScopeNamePt2a_U; ///< Name Pointer - UINT8 ScopeNamePt2a_0; ///< Name Pointer -} SCOPE; -#define SCOPE_STRUCT_SIZE 13 // 13 Bytes - -//-------------------------------------------- -// AML code definition -// (PCT Header and Body) -//--------------------------------------------- - -///Performance Control Header -typedef struct _PCT_HEADER_BODY { - UINT8 NameOpcode; ///< Opcode - UINT8 PctName_a__; ///< String "_" - UINT8 PctName_a_P; ///< String "P" - UINT8 PctName_a_C; ///< String "C" - UINT8 PctName_a_T; ///< String "T" - UINT32 Value1; ///< Value1 - UINT16 Value2; ///< Value2 - UINT8 Value3; ///< Value3 - UINT8 GenericRegDescription1; ///< Generic Reg Description - UINT16 Length1; ///< Length1 - UINT8 AddressSpaceId1; ///< PCT Address Space ID - UINT8 RegisterBitWidth1; ///< PCT Register Bit Width - UINT8 RegisterBitOffset1; ///< PCT Register Bit Offset - UINT8 Reserved1; ///< Reserved - UINT32 ControlRegAddressLo; ///< Control Register Address Low - UINT32 ControlRegAddressHi; ///< Control Register Address High - UINT32 Value4; ///< Value4 - UINT16 Value5; ///< Value 5 - UINT8 GenericRegDescription2; ///< Generic Reg Description - UINT16 Length2; ///< Length2 - UINT8 AddressSpaceId2; ///< PCT Address Space ID - UINT8 RegisterBitWidth2; ///< PCT Register Bit Width - UINT8 RegisterBitOffset2; ///< PCT Register Bit Offset - UINT8 Reserved2; ///< Reserved - UINT32 StatusRegAddressLo; ///< Control Register Address Low - UINT32 StatusRegAddressHi; ///< Control Register Address High - UINT16 Value6; ///< Values -} PCT_HEADER_BODY; -#define PCT_STRUCT_SIZE 50 // 50 Bytes - - -//-------------------------------------------- -// AML code definition -// (PSS Header) -//-------------------------------------------- -///Performance Supported States Header -typedef struct _PSS_HEADER { - UINT8 NameOpcode; ///< Opcode - UINT8 PssName_a__; ///< String "_" - UINT8 PssName_a_P; ///< String "P" - UINT8 PssName_a_S; ///< String "S" - UINT8 PssName_b_S; ///< String "S" - UINT8 PkgOpcode; ///< Package Opcode - UINT16 PssLength; ///< PSS Length - UINT8 NumOfItemsInPss; ///< Number of Items in PSS -} PSS_HEADER; -#define PSS_HEADER_STRUCT_SIZE 9 // 9 Bytes - - -//-------------------------------------------- -// AML code definition -// (PSS Body) -//-------------------------------------------- -///Performance Supported States Body -typedef struct _PSS_BODY { - UINT8 PkgOpcode; ///< Package Opcode - UINT8 PkgLength; ///< Package Length - UINT8 NumOfElements; ///< Number of Elements - UINT8 DwordPrefixOpcode1; ///< Prefix Opcode1 - UINT32 Frequency; ///< Frequency - UINT8 DwordPrefixOpcode2; ///< Prefix Opcode2 - UINT32 Power; ///< Power - UINT8 DwordPrefixOpcode3; ///< Prefix Opcode3 - UINT32 TransitionLatency; ///< Transition Latency - UINT8 DwordPrefixOpcode4; ///< Prefix Opcode4 - UINT32 BusMasterLatency; ///< Bus Master Latency - UINT8 DwordPrefixOpcode5; ///< Prefix Opcode5 - UINT32 Control; ///< Control - UINT8 DwordPrefixOpcode6; ///< Prefix Opcode6 - UINT32 Status; ///< Status -} PSS_BODY; -#define PSS_BODY_STRUCT_SIZE 33 // 33 Bytes - - -/*-------------------------------------------- - * AML code definition - * (XPSS Header) - *-------------------------------------------- - */ -/// Extended PSS Header -typedef struct _XPSS_HEADER { - UINT8 NameOpcode; ///< 08h - UINT8 XpssName_a_X; ///< String "X" - UINT8 XpssName_a_P; ///< String "P" - UINT8 XpssName_a_S; ///< String "S" - UINT8 XpssName_b_S; ///< String "S" - UINT8 PkgOpcode; ///< 12h - UINT16 XpssLength; ///< XPSS Length - UINT8 NumOfItemsInXpss; ///< Number of Items in XPSS -} XPSS_HEADER; -#define XPSS_HEADER_STRUCT_SIZE 9 // 9 Bytes - -/*-------------------------------------------- - * AML code definition - * (XPSS Body) - *-------------------------------------------- - */ -/// Extended PSS Body -typedef struct _XPSS_BODY { - UINT8 PkgOpcode; ///< 12h - UINT8 PkgLength; ///< Package Length - UINT8 XpssValueTbd; ///< XPSS Value - UINT8 NumOfElements; ///< Number of Elements - UINT8 DwordPrefixOpcode1; ///< Prefix Opcode1 - UINT32 Frequency; ///< Frequency - UINT8 DwordPrefixOpcode2; ///< Prefix Opcode2 - UINT32 Power; ///< Power - UINT8 DwordPrefixOpcode3; ///< Prefix Opcode3 - UINT32 TransitionLatency; ///< Transition Latency - UINT8 DwordPrefixOpcode4; ///< Prefix Opcode4 - UINT32 BusMasterLatency; ///< Bus Master Latency - UINT32 ControlBuffer; ///< Control Buffer - UINT32 ControlLo; ///< Control Low - UINT32 ControlHi; ///< Control High - UINT32 StatusBuffer; ///< Status Buffer - UINT32 StatusLo; ///< Status Low - UINT32 StatusHi; ///< Status High - UINT32 ControlMaskBuffer; ///< Control Mask Buffer - UINT32 ControlMaskLo; ///< Control Mask Low - UINT32 ControlMaskHi; ///< Control Mask High - UINT32 StatusMaskBuffer; ///< Status Mask Buffer - UINT32 StatusMaskLo; ///< Status Mask Low - UINT32 StatusMaskHi; ///< Status Mask High -} XPSS_BODY; -#define XPSS_BODY_STRUCT_SIZE 72 // 72 Bytes - -/*-------------------------------------------- - * AML code definition - * (PPC Header and Body) - *-------------------------------------------- - */ -/// Performance Present Capabilities Header -typedef struct _PPC_HEADER_BODY { - UINT8 MethodOpcode; ///< Method Opcode - UINT8 PpcLength; ///< PPC Length - UINT8 PpcName_a__; ///< String "_" - UINT8 PpcName_a_P; ///< String "P" - UINT8 PpcName_b_P; ///< String "P" - UINT8 PpcName_a_C; ///< String "C" - UINT8 MethodFlags; ///< Method Flags - UINT8 ReturnOpcode; ///< Return Opcoce - UINT8 Value1; ///< Value - UINT8 DefaultPerfPresentCap; ///< Default Perf Present Cap -} PPC_HEADER_BODY; -#define PPC_HEADER_BODY_STRUCT_SIZE 10 // 10 Bytes - - -/*-------------------------------------------- - * AML code definition - * (PSD Header) - *-------------------------------------------- - */ -/// P-State Dependency Header -typedef struct _PSD_HEADER { - UINT8 NameOpcode; ///< Name Opcode - UINT8 PsdName_a__; ///< String "_" - UINT8 PsdName_a_P; ///< String "P" - UINT8 PsdName_a_S; ///< String "S" - UINT8 PsdName_a_D; ///< String "D" - UINT8 PkgOpcode; ///< Package Opcode - UINT8 PsdLength; ///< PSD Length - UINT8 Value1; ///< Value -} PSD_HEADER; -#define PSD_HEADER_STRUCT_SIZE 8 // 8 Bytes - -/*-------------------------------------------- - * AML code definition - * (PSD Body) - *-------------------------------------------- - */ -/// P-State Dependency Body -typedef struct _PSD_BODY { - UINT8 PkgOpcode; ///< Package Opcode - UINT8 PkgLength; ///< Package Length - UINT8 NumOfEntries; ///< Number of Entries - UINT8 BytePrefixOpcode1; ///< Prefix Opcode1 in Byte - UINT8 PsdNumOfEntries; ///< PSD Number of Entries - UINT8 BytePrefixOpcode2; ///< Prefix Opcode2 in Byte - UINT8 PsdRevision; ///< PSD Revision - UINT8 DwordPrefixOpcode1; ///< Prefix Opcode1 in DWord - UINT32 DependencyDomain; ///< Dependency Domain - UINT8 DwordPrefixOpcode2; ///< Prefix Opcode2 in DWord - UINT32 CoordinationType; ///< (0xFC = SW_ALL, 0xFD = SW_ANY, 0xFE = HW_ALL) - UINT8 DwordPrefixOpcode3; ///< Prefix Opcode3 in DWord - UINT32 NumOfProcessors; ///< Number of Processors -} PSD_BODY; -#define PSD_BODY_STRUCT_SIZE 22 // 22 Bytes - -//---------------------------------------------------------------------------- -// WHEA TYPEDEFS, STRUCTURES, ENUMS -// -//---------------------------------------------------------------------------- - -/// HEST MCE TABLE -typedef struct _AMD_HEST_MCE_TABLE { - UINT16 TblLength; ///< Length, in bytes, of entire AMD_HEST_MCE structure. - UINT32 GlobCapInitDataLSD; ///< Holds the value that the OS will program into - UINT32 GlobCapInitDataMSD; ///< the machine check global capability register(MCG_CAP). - UINT32 GlobCtrlInitDataLSD; ///< Holds the value that the OS will program into - UINT32 GlobCtrlInitDataMSD; ///< the machine check global control register(MCG_CTL). - UINT8 NumHWBanks; ///< The number of hardware error reporting banks. - UINT8 Rsvd[7]; ///< reserve 7 bytes as spec's required -} AMD_HEST_MCE_TABLE; - -/// HEST CMC TABLE -typedef struct _AMD_HEST_CMC_TABLE { - UINT16 TblLength; ///< Length, in bytes, of entire AMD_HEST_CMC structure. - UINT8 NumHWBanks; ///< The number of hardware error reporting banks. - UINT8 Rsvd[3]; ///< reserve 3 bytes as spec's required -} AMD_HEST_CMC_TABLE; - -/// HEST BANK -typedef struct _AMD_HEST_BANK { - UINT8 BankNum; ///< Zero-based index identifies the machine check error bank. - UINT8 ClrStatusOnInit; ///< Indicates if the status information in this machine check bank - ///< is to be cleared during system initialization. - UINT8 StatusDataFormat; ///< Indicates the format of the data in the status register - UINT8 ConfWriteEn; ///< This field indicates whether configuration parameters may be - ///< modified by the OS. If the bit for the associated parameter is - ///< set, the parameter is writable by the OS. - UINT32 CtrlRegMSRAddr; ///< Address of the hardware bank's control MSR. Ignored if zero. - - UINT32 CtrlInitDataLSD; ///< This is the value the OS will program into the machine check - UINT32 CtrlInitDataMSD; ///< bank's control register - UINT32 StatRegMSRAddr; ///< Address of the hardware bank's MCi_STAT MSR. Ignored if zero. - UINT32 AddrRegMSRAddr; ///< Address of the hardware bank's MCi_ADDR MSR. Ignored if zero. - UINT32 MiscRegMSRAddr; ///< Address of the hardware bank's MCi_MISC MSR. Ignored if zero. -} AMD_HEST_BANK; - -/// Initial data of AMD_HEST_BANK -typedef struct _AMD_HEST_BANK_INIT_DATA { - UINT32 CtrlInitDataLSD; ///< Initial data of CtrlInitDataLSD - UINT32 CtrlInitDataMSD; ///< Initial data of CtrlInitDataMSD - UINT32 CtrlRegMSRAddr; ///< Initial data of CtrlRegMSRAddr - UINT32 StatRegMSRAddr; ///< Initial data of StatRegMSRAddr - UINT32 AddrRegMSRAddr; ///< Initial data of AddrRegMSRAddr - UINT32 MiscRegMSRAddr; ///< Initial data of MiscRegMSRAddr -} AMD_HEST_BANK_INIT_DATA; - -/// MSR179 Global Machine Check Capabilities data struct -typedef struct _MSR_MCG_CAP_STRUCT { - UINT64 Count:8; ///< Indicates the number of - ///< error-reporting banks visible to each core - UINT64 McgCtlP:1; ///< 1=The machine check control registers - UINT64 Rsvd:55; ///< reserved -} MSR_MCG_CAP_STRUCT; - -/// Initial data of WHEA -typedef struct _AMD_WHEA_INIT_DATA { - UINT32 GlobCapInitDataLSD; ///< Holds the value that the OS will program into the machine - UINT32 GlobCapInitDataMSD; ///< Check global capability register - UINT32 GlobCtrlInitDataLSD; ///< Holds the value that the OS will grogram into the machine - UINT32 GlobCtrlInitDataMSD; ///< Check global control register - UINT8 ClrStatusOnInit; ///< Indicates if the status information in this machine check - ///< bank is to be cleared during system initialization - UINT8 StatusDataFormat; ///< Indicates the format of the data in the status register - UINT8 ConfWriteEn; ///< This field indicates whether configuration parameters may be - ///< modified by the OS. If the bit for the associated parameter is - ///< set, the parameter is writable by the OS. - UINT8 HestBankNum; ///< Number of HEST Bank - AMD_HEST_BANK_INIT_DATA *HestBankInitData; ///< Pointer to Initial data of HEST Bank -} AMD_WHEA_INIT_DATA; - -//---------------------------------------------------------------------------- -// DMI TYPEDEFS, STRUCTURES, ENUMS -// -//---------------------------------------------------------------------------- -/// DMI brand information -typedef struct { - UINT16 String1:4; ///< String1 - UINT16 String2:4; ///< String2 - UINT16 Model:7; ///< Model - UINT16 Pg:1; ///< Page -} BRAND_ID; - -/// DMI processor information -typedef struct { - UINT8 ExtendedFamily; ///< Extended Family - UINT8 ExtendedModel; ///< Extended Model - UINT8 BaseFamily; ///< Base Family - UINT8 BaseModel; ///< Base Model - UINT8 Stepping; ///< Stepping - UINT8 PackageType; ///< PackageType - BRAND_ID BrandId; ///< BrandId which contains information about String1, String2, Model and Page - UINT8 TotalCoreNumber; ///< Number of total cores - UINT8 EnabledCoreNumber; ///< Number of enabled cores - UINT8 ProcUpgrade; ///< ProcUpdrade -} CPU_TYPE_INFO; - -/// A structure containing processor name string and -/// the value that should be provide to DMI type 4 processor family -typedef struct { - IN CONST CHAR8 *Stringstart; ///< The literal string - IN UINT8 T4ProcFamilySetting; ///< The value set to DMI type 4 processor family -} CPU_T4_PROC_FAMILY; - -/// DMI ECC information -typedef struct { - BOOLEAN EccCapable; ///< ECC Capable - UINT8 PartitionRowPosition; ///< DMI Type 20 offset 10h: Partition Row Position - ///< 2 - single channel memory - ///< 0 - dual channel memory -} CPU_GET_MEM_INFO; - -/* Transfer vectors for DMI family specific routines */ -typedef VOID OPTION_DMI_GET_CPU_INFO ( - IN OUT CPU_TYPE_INFO *CpuInfoPtr, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -typedef VOID OPTION_DMI_GET_PROC_FAMILY ( - IN OUT UINT8 *T4ProcFamily, - IN PROC_FAMILY_TABLE *CpuDmiProcFamilyTable, - IN CPU_TYPE_INFO *CpuInfo, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -typedef UINT8 OPTION_DMI_GET_VOLTAGE ( - IN AMD_CONFIG_PARAMS *StdHeader - ); - -typedef UINT16 OPTION_DMI_GET_MAX_SPEED ( - IN AMD_CONFIG_PARAMS *StdHeader - ); - -typedef UINT16 OPTION_DMI_GET_EXT_CLOCK ( - IN AMD_CONFIG_PARAMS *StdHeader - ); - -typedef VOID OPTION_DMI_GET_MEM_INFO ( - IN OUT CPU_GET_MEM_INFO *CpuGetMemInfoPtr, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -/// Brand table entry format -typedef struct { - UINT8 PackageType; ///< Package type - UINT8 PgOfBrandId; ///< Page - UINT8 NumberOfCores; ///< Number of cores - UINT8 String1ofBrandId; ///< String1 - UINT8 ValueSetToDmiTable; ///< The value which will should be set to DMI table -} DMI_BRAND_ENTRY; - -/// Family specific data table structure -typedef struct _PROC_FAMILY_TABLE { - UINT64 ProcessorFamily; ///< processor - OPTION_DMI_GET_CPU_INFO *DmiGetCpuInfo; ///< transfer vectors - OPTION_DMI_GET_PROC_FAMILY *DmiGetT4ProcFamily; ///< Get DMI type 4 processor family information - OPTION_DMI_GET_VOLTAGE *DmiGetVoltage; ///< vector for reading voltage - OPTION_DMI_GET_MAX_SPEED *DmiGetMaxSpeed; ///< vector for reading speed - OPTION_DMI_GET_EXT_CLOCK *DmiGetExtClock; ///< vector for reading external clock speed - OPTION_DMI_GET_MEM_INFO *DmiGetMemInfo; ///< Get memory information - UINT8 LenBrandList; ///< size of brand table - CONST DMI_BRAND_ENTRY *DmiBrandList; ///< translate brand info to DMI identifier -} UnusedName1; - -//---------------------------------------------------------------------------- -// SLIT TYPEDEFS, STRUCTURES, ENUMS -// -//---------------------------------------------------------------------------- -/// Format for SRAT Header -typedef struct { - UINT8 Sign[4]; ///< Signature - UINT32 TableLength; ///< Table Length - UINT8 Revision; ///< Revision - UINT8 Checksum; ///< Checksum - UINT8 OemId[6]; ///< OEM ID - UINT8 OemTableId[8]; ///< OEM Tabled ID - UINT32 OemRev; ///< OEM Revision - UINT8 CreatorId[4]; ///< Creator ID - UINT32 CreatorRev; ///< Creator Revision -} ACPI_TABLE_HEADER; - -//---------------------------------------------------------------------------- -// SRAT TYPEDEFS, STRUCTURES, ENUMS -// -//---------------------------------------------------------------------------- -/// Format for SRAT Header -typedef struct _CPU_SRAT_HEADER { - UINT8 Sign[4]; ///< Signature - UINT32 TableLength; ///< Table Length - UINT8 Revision; ///< Revision - UINT8 Checksum; ///< Checksum - UINT8 OemId[6]; ///< OEM ID - UINT8 OemTableId[8]; ///< OEM Tabled ID - UINT32 OemRev; ///< OEM Revision - UINT8 CreatorId[4]; ///< Creator ID - UINT32 CreatorRev; ///< Creator Revision - UINT32 TableRev; ///< Table Revision - UINT8 Reserved[8]; ///< Reserved -} CPU_SRAT_HEADER; - - -/// Format for SRAT APIC Affinity Entry -typedef struct _CPU_SRAT_APIC_ENTRY { - UINT8 Type; ///< Type - UINT8 Length; ///< Length - UINT8 Domain; ///< Domain - UINT8 ApicId; ///< Apic ID - UINT32 Flags; ///< Flags - UINT8 LSApicEid; ///< Local SAPIC EID - UINT8 Reserved[7]; ///< Reserved -} CPU_SRAT_APIC_ENTRY; - - -/// Format for SRAT Memory Affinity Entry -typedef struct _CPU_SRAT_MEMORY_ENTRY { - UINT8 Type; ///< 0: Memory affinity = 1 - UINT8 Length; ///< 1: Length = 40 bytes - UINT32 Domain; ///< 2: Proximity domain - UINT8 Reserved1[2]; ///< 6: Reserved - UINT32 BaseAddrLow; ///< 8: Low 32bits address base - UINT32 BaseAddrHigh; ///< 12: High 32bits address base - UINT32 LengthAddrLow; ///< 16: Low 32bits address limit - UINT32 LengthAddrHigh; ///< 20: High 32bits address limit - UINT8 Reserved2[4]; ///< 24: Memory Type - UINT32 Flags; ///< 28: Flags - UINT8 Reserved3[8]; ///< 32: Reserved -} CPU_SRAT_MEMORY_ENTRY; - -/*---------------------------------------------------------------------------------------- - * F U N C T I O N P R O T O T Y P E - *---------------------------------------------------------------------------------------- - */ - -AGESA_STATUS -AmdCpuLate ( - IN AMD_CONFIG_PARAMS *StdHeader - ); - -AGESA_STATUS -CreateAcpiWhea ( - IN OUT AMD_CONFIG_PARAMS *StdHeader, - IN OUT VOID **WheaMcePtr, - IN OUT VOID **WheaCmcPtr - ); - -AGESA_STATUS -CreateDmiRecords ( - IN OUT AMD_CONFIG_PARAMS *StdHeader, - IN OUT DMI_INFO **DmiTable - ); - -AGESA_STATUS -GetType4Type7Info ( - IN AP_EXE_PARAMS *ApExeParams - ); - -VOID -DmiGetT4ProcFamilyFromBrandId ( - IN OUT UINT8 *T4ProcFamily, - IN PROC_FAMILY_TABLE *CpuDmiProcFamilyTable, - IN CPU_TYPE_INFO *CpuInfo, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -VOID -GetNameString ( - IN OUT CHAR8 *String, - IN OUT AMD_CONFIG_PARAMS *StdHeader - ); - -BOOLEAN -IsSourceStrContainTargetStr ( - IN OUT CHAR8 *SourceStr, - IN OUT CONST CHAR8 *TargetStr, - IN OUT AMD_CONFIG_PARAMS *StdHeader - ); - -AGESA_STATUS -CreateAcpiSrat ( - IN OUT AMD_CONFIG_PARAMS *StdHeader, - IN OUT VOID **SratPtr - ); - -AGESA_STATUS -CreateAcpiSlit ( - IN OUT AMD_CONFIG_PARAMS *StdHeader, - IN PLATFORM_CONFIGURATION *PlatformConfig, - IN OUT VOID **SlitPtr - ); - -VOID -ChecksumAcpiTable ( - IN OUT ACPI_TABLE_HEADER *Table, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -AGESA_STATUS -RunLateApTaskOnAllAPs ( - IN AP_EXE_PARAMS *ApParams, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -AGESA_STATUS -RunLateApTaskOnAllCore0s ( - IN AP_EXE_PARAMS *ApParams, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -#endif // _CPU_LATE_INIT_H_ diff --git a/src/vendorcode/amd/agesa/f12/Proc/CPU/cpuMicrocodePatch.c b/src/vendorcode/amd/agesa/f12/Proc/CPU/cpuMicrocodePatch.c deleted file mode 100644 index 5968c25891..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/CPU/cpuMicrocodePatch.c +++ /dev/null @@ -1,445 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * AMD CPU Microcode Patch Related Functions - * - * Contains code to program a microcode into the CPU - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: CPU - * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $ - * - */ -/* - ****************************************************************************** - * - * Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - ****************************************************************************** - */ - -/*--------------------------------------------------------------------------------------- - * M O D U L E S U S E D - *--------------------------------------------------------------------------------------- - */ -#include "AGESA.h" -#include "amdlib.h" -#include "Ids.h" -#include "cpuRegisters.h" -#include "cpuFamilyTranslation.h" -#include "cpuEarlyInit.h" -#include "GeneralServices.h" -#include "cpuServices.h" -#include "Filecode.h" -CODE_GROUP (G1_PEICC) -RDATA_GROUP (G1_PEICC) - -#define FILECODE PROC_CPU_CPUMICROCODEPATCH_FILECODE -/*---------------------------------------------------------------------------------------- - * D E F I N I T I O N S A N D M A C R O S - *---------------------------------------------------------------------------------------- - */ - - -/*---------------------------------------------------------------------------------------- - * T Y P E D E F S A N D S T R U C T U R E S - *---------------------------------------------------------------------------------------- - */ -typedef union { - UINT64 RawData; - PATCH_LOADER_MSR BitFields; -} PATCH_LOADER; - -/*---------------------------------------------------------------------------------------- - * P R O T O T Y P E S O F L O C A L F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ -BOOLEAN -STATIC -LoadMicrocode ( - IN MICROCODE_PATCH *MicrocodePatchPtr, - IN OUT AMD_CONFIG_PARAMS *StdHeader - ); - -BOOLEAN -STATIC -GetPatchEquivalentId ( - IN OUT UINT16 *ProcessorEquivalentId, - IN OUT AMD_CONFIG_PARAMS *StdHeader - ); - -BOOLEAN -STATIC -ValidateMicrocode ( - IN MICROCODE_PATCH *MicrocodePatchPtr, - IN UINT16 ProcessorEquivalentId, - IN OUT AMD_CONFIG_PARAMS *StdHeader - ); - -VOID -STATIC -GetMicrocodeVersion ( - OUT UINT32 *pMicrocodeVersion, - IN OUT AMD_CONFIG_PARAMS *StdHeader - ); - -/*---------------------------------------------------------------------------------------- - * E X P O R T E D F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ -VOID -LoadMicrocodePatchAtEarly ( - IN CPU_SPECIFIC_SERVICES *FamilyServices, - IN AMD_CPU_EARLY_PARAMS *EarlyParams, - IN AMD_CONFIG_PARAMS *StdHeader - ); - - -/* -----------------------------------------------------------------------------*/ -/** - * Update microcode patch in current processor. - * - * Then reads the patch id, and compare it to the expected, in the Microprocessor - * patch block. - * - * @param[in] StdHeader - Config handle for library and services. - * - * @retval TRUE - Patch Loaded Successfully. - * @retval FALSE - Patch Did Not Get Loaded. - * - */ -BOOLEAN -LoadMicrocodePatch ( - IN OUT AMD_CONFIG_PARAMS *StdHeader - ) -{ - UINT8 PatchNumber; - UINT8 TotalPatches; - UINT16 ProcessorEquivalentId; - BOOLEAN Status; - MICROCODE_PATCH **MicrocodePatchPtr; - CPU_SPECIFIC_SERVICES *FamilySpecificServices; - - Status = FALSE; - - if (IsCorePairPrimary (FirstCoreIsComputeUnitPrimary, StdHeader)) { - // Get the patch pointer - GetCpuServicesOfCurrentCore ((const CPU_SPECIFIC_SERVICES **)&FamilySpecificServices, StdHeader); - FamilySpecificServices->GetMicroCodePatchesStruct (FamilySpecificServices, (const VOID **) &MicrocodePatchPtr, &TotalPatches, StdHeader); - - IDS_OPTION_HOOK (IDS_UCODE, &TotalPatches, StdHeader); - - // Get the processor microcode path equivalent ID - if (GetPatchEquivalentId (&ProcessorEquivalentId, StdHeader)) { - // parse the patch table to see if we have one for the current cpu - for (PatchNumber = 0; PatchNumber < TotalPatches; PatchNumber++) { - if (ValidateMicrocode (MicrocodePatchPtr[PatchNumber], ProcessorEquivalentId, StdHeader)) { - if (LoadMicrocode (MicrocodePatchPtr[PatchNumber], StdHeader)) { - Status = TRUE; - } else { - PutEventLog (AGESA_ERROR, - CPU_ERROR_MICRO_CODE_PATCH_IS_NOT_LOADED, - 0, 0, 0, 0, StdHeader); - } - break; // Once we find a microcode patch that matches the processor, exit the for loop - } - } - } - } - return Status; -} - -/*--------------------------------------------------------------------------------------- - * L O C A L F U N C T I O N S - *--------------------------------------------------------------------------------------- - */ - -/* -----------------------------------------------------------------------------*/ -/** - * - * LoadMicrocode - * - * Update microcode patch in current processor, then reads the - * patch id, and compare it to the expected, in the Microprocessor - * patch block. - * - * @param[in] MicrocodePatchPtr - Pointer to Microcode Patch. - * @param[in,out] StdHeader - Pointer to AMD_CONFIG_PARAMS struct. - * - * @retval TRUE - Patch Loaded Successfully. - * @retval FALSE - Patch Did Not Get Loaded. - * - */ -BOOLEAN -STATIC -LoadMicrocode ( - IN MICROCODE_PATCH *MicrocodePatchPtr, - IN OUT AMD_CONFIG_PARAMS *StdHeader - ) -{ - UINT32 MicrocodeVersion; - PATCH_LOADER PatchLoaderMsr; - - // Load microcode patch into CPU - PatchLoaderMsr.RawData = (UINT64) (intptr_t) MicrocodePatchPtr; - PatchLoaderMsr.BitFields.SBZ = 0; - LibAmdMsrWrite (MSR_PATCH_LOADER, &PatchLoaderMsr.RawData, StdHeader); - - // Do ucode patch Authentication - // Read microcode version back from CPU, determine if - // it is the same patch level as contained in the source - // microprocessor patch block passed in - GetMicrocodeVersion (&MicrocodeVersion, StdHeader); - if (MicrocodeVersion == MicrocodePatchPtr->PatchID) { - return (TRUE); - } else { - return (FALSE); - } -} - - -/* -----------------------------------------------------------------------------*/ -/** - * - * GetPatchEquivalentId - * - * Return the equivalent ID for microcode patching - * - * @param[in,out] ProcessorEquivalentId - Pointer to Processor Equivalent ID table. - * @param[in,out] StdHeader - Pointer to AMD_CONFIG_PARAMS struct. - * - * @retval TRUE - ID Found. - * @retval FALSE - ID Not Found. - * - */ -BOOLEAN -STATIC -GetPatchEquivalentId ( - IN OUT UINT16 *ProcessorEquivalentId, - IN OUT AMD_CONFIG_PARAMS *StdHeader - ) -{ - UINT8 i; - UINT8 EquivalencyEntries; - UINT16 ProcessorRevisionId; - UINT16 *MicrocodeEquivalenceTable; - CPUID_DATA CpuIdData; - CPU_SPECIFIC_SERVICES *FamilySpecificServices; - - // - // compute the processor revision ID - // - LibAmdCpuidRead (AMD_CPUID_FMF, &CpuIdData, StdHeader); - // high byte contains extended model and extended family - ProcessorRevisionId = (UINT16) ((CpuIdData.EAX_Reg & (CPU_EMODEL | CPU_EFAMILY)) >> 8); - // low byte contains model and family - ProcessorRevisionId |= (CpuIdData.EAX_Reg & (CPU_STEPPING | CPU_MODEL)); - - // - // find the equivalent ID for microcode purpose using the equivalence table - // - GetCpuServicesOfCurrentCore ((const CPU_SPECIFIC_SERVICES **)&FamilySpecificServices, StdHeader); - - FamilySpecificServices->GetMicrocodeEquivalenceTable (FamilySpecificServices, - (const VOID **)&MicrocodeEquivalenceTable, - &EquivalencyEntries, - StdHeader); - - // parse the equivalence table - for (i = 0; i < (EquivalencyEntries * 2); i += 2) { - // check for equivalence - if (ProcessorRevisionId == MicrocodeEquivalenceTable[i]) { - *ProcessorEquivalentId = MicrocodeEquivalenceTable[i + 1]; - return (TRUE); - } - } - // end of table reach, this processor is not supported - *ProcessorEquivalentId = 0x0000; - return (FALSE); -} - -/*---------------------------------------------------------------------------------------*/ -/** - * - * ValidateMicrocode - * - * Determine if the microcode patch block, currently pointed to - * is valid, and is appropriate for the current processor - - * @param[in] MicrocodePatchPtr - Pointer to Microcode Patch. - * @param[in] ProcessorEquivalentId - Pointer to Processor Equivalent ID table. - * @param[in,out] StdHeader - Pointer to AMD_CONFIG_PARAMS struct. - * - * @retval TRUE - Patch Found. - * @retval FALSE - Patch Not Found. - * - */ -BOOLEAN -STATIC -ValidateMicrocode ( - IN MICROCODE_PATCH *MicrocodePatchPtr, - IN UINT16 ProcessorEquivalentId, - IN OUT AMD_CONFIG_PARAMS *StdHeader - ) -{ - BOOLEAN Chipset1Matched; - BOOLEAN Chipset2Matched; - PCI_ADDR PciAddress; - UINT32 PciDeviceVidDid; - UINT8 PciDeviceRevision; - UINT8 DevCount; - UINT8 FunCount; - UINT32 Chipset1DeviceID; - UINT32 Chipset2DeviceID; - UINT8 MulitFunction; - - Chipset1Matched = FALSE; - Chipset2Matched = FALSE; - PciDeviceVidDid = 0; - PciDeviceRevision = 0; - Chipset1DeviceID = MicrocodePatchPtr->Chipset1DeviceID; - Chipset2DeviceID = MicrocodePatchPtr->Chipset2DeviceID; - MulitFunction = 0; - - // - // parse the supplied microcode to see if it is compatible with the processor - // - if (MicrocodePatchPtr->ProcessorRevisionID != ProcessorEquivalentId) { - return (FALSE); - } - - if (Chipset1DeviceID == 0) { - Chipset1Matched = TRUE; - } - if (Chipset2DeviceID == 0) { - Chipset2Matched = TRUE; - } - - if ((!Chipset1Matched) || (!Chipset2Matched)) { - // - // Scan all PCI devices in Bus 0, try to find out matched case. - // - for (DevCount = 0; DevCount < 32; DevCount++) { - for (FunCount = 0; FunCount < 8; FunCount++) { - PciAddress.AddressValue = MAKE_SBDFO (0, 0, DevCount, FunCount, 0); - LibAmdPciRead (AccessWidth32, PciAddress, &PciDeviceVidDid, StdHeader); - if (PciDeviceVidDid == 0xFFFFFFFF) { - if (FunCount == 0) { - break; - } else { - continue; - } - } - PciAddress.Address.Register = 0x8; - LibAmdPciRead (AccessWidth8, PciAddress, &PciDeviceRevision, StdHeader); - if ((!Chipset1Matched) && (PciDeviceVidDid == Chipset1DeviceID)) { - if (PciDeviceRevision == MicrocodePatchPtr->Chipset1RevisionID) { - Chipset1Matched = TRUE; - } - } - if ((!Chipset2Matched) && (PciDeviceVidDid == Chipset2DeviceID)) { - if (PciDeviceRevision == MicrocodePatchPtr->Chipset2RevisionID) { - Chipset2Matched = TRUE; - } - } - if (Chipset1Matched && Chipset2Matched) { - break; - } - // - // Check multi-function. If it doesen't exist, we don't have to loop functions to 7. - // - if (FunCount == 0) { - MulitFunction = 0; - PciAddress.Address.Register = 0xE; - LibAmdPciRead (AccessWidth8, PciAddress, &MulitFunction, StdHeader); - if ((MulitFunction & 0x80) == 0) { - break; - } - } - } // end FunCount for loop. - - if (Chipset1Matched && Chipset2Matched) { - break; - } - } // end DevCount for loop. - } - - return (Chipset1Matched && Chipset2Matched); -} - - -/*---------------------------------------------------------------------------------------*/ -/** - * - * GetMicrocodeVersion - * - * Return the version of the currently loaded microcode patch, if any. - * Read from the patch level MSR, return the value in eax. If no patch - * has been loaded, 0 will be returned. - * - * @param[out] pMicrocodeVersion - Pointer to Microcode Version. - * @param[in,out] StdHeader - Pointer to AMD_CONFIG_PARAMS struct. - * - */ -VOID -STATIC -GetMicrocodeVersion ( - OUT UINT32 *pMicrocodeVersion, - IN OUT AMD_CONFIG_PARAMS *StdHeader - ) -{ - UINT64 MsrData; - - MsrData = 0; - LibAmdMsrRead (MSR_PATCH_LEVEL, &MsrData, StdHeader); - - *pMicrocodeVersion = (UINT32) MsrData; -} - - -/*---------------------------------------------------------------------------------------*/ -/** - * Update microcode patch in current processor. - * - * This function acts as a wrapper for calling the LoadMicrocodePatch - * routine at AmdInitEarly. - * - * @param[in] FamilyServices The current Family Specific Services. - * @param[in] EarlyParams Service parameters. - * @param[in] StdHeader Config handle for library and services. - * - */ -VOID -LoadMicrocodePatchAtEarly ( - IN CPU_SPECIFIC_SERVICES *FamilyServices, - IN AMD_CPU_EARLY_PARAMS *EarlyParams, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - AGESA_TESTPOINT (TpProcCpuLoadUcode, StdHeader); - LoadMicrocodePatch (StdHeader); -} diff --git a/src/vendorcode/amd/agesa/f12/Proc/CPU/cpuPage.h b/src/vendorcode/amd/agesa/f12/Proc/CPU/cpuPage.h deleted file mode 100644 index 3a4af879bf..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/CPU/cpuPage.h +++ /dev/null @@ -1,60 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * Create outline and references for CPU Component mainpage documentation. - * - * Design guides, maintenance guides, and general documentation, are - * collected using this file onto the documentation mainpage. - * This file contains doxygen comment blocks, only. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: Documentation - * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $ - * - */ -/* - ****************************************************************************** - * - * Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - ****************************************************************************** - */ - -/** - * @page cpumain CPU Component Documentation - * - * Additional documentation for the CPU component consists of - * - * - Maintenance Guides: - * - @subpage cpuimplfss "CPU Family Specific Services Implementation Guide" - * - @subpage regtableimpl "Register Table Implementation Guide" - * - @subpage cpufeatimpl "CPU Generic Feature Implementation Guide" - * - add here >>> - * - Design Guides: - * - add here >>> - * - */ diff --git a/src/vendorcode/amd/agesa/f12/Proc/CPU/cpuPostInit.c b/src/vendorcode/amd/agesa/f12/Proc/CPU/cpuPostInit.c deleted file mode 100644 index 59ff2659fd..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/CPU/cpuPostInit.c +++ /dev/null @@ -1,504 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * AMD CPU POST API, and related functions. - * - * Contains code that initialized the CPU after memory init. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: CPU - * @e \$Revision: 49029 $ @e \$Date: 2011-03-16 09:55:06 +0800 (Wed, 16 Mar 2011) $ - * - */ -/* - **************************************************************************** - * AMD Generic Encapsulated Software Architecture - * - * Description: cpuPostInit.c - Cpu POST Initialization Functions. - * - ****************************************************************************** - * - * Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - ****************************************************************************** - */ - -/*---------------------------------------------------------------------------------------- - * M O D U L E S U S E D - *---------------------------------------------------------------------------------------- - */ - -#include "AGESA.h" -#include "amdlib.h" -#include "Ids.h" -#include "Options.h" -#include "cpuRegisters.h" -#include "cpuApicUtilities.h" -#include "heapManager.h" -#include "cpuServices.h" -#include "cpuFeatures.h" -#include "GeneralServices.h" -#include "cpuPostInit.h" -#include "cpuPstateTables.h" -#include "cpuFamilyTranslation.h" -#include "Filecode.h" -CODE_GROUP (G1_PEICC) -RDATA_GROUP (G1_PEICC) -#define FILECODE PROC_CPU_CPUPOSTINIT_FILECODE -/*---------------------------------------------------------------------------------------- - * D E F I N I T I O N S A N D M A C R O S - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------- - * T Y P E D E F S A N D S T R U C T U R E S - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------- - * P R O T O T Y P E S O F L O C A L F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ -VOID -STATIC -SyncVariableMTRR ( - IN AMD_CONFIG_PARAMS *StdHeader - ); - -AGESA_STATUS -GetPstateGatherDataAddressAtPost ( - OUT UINT64 **Ptr, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -VOID -SyncAllApMtrrToBsc ( - IN VOID *MtrrTable, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -/*---------------------------------------------------------------------------------------- - * E X P O R T E D F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ -extern BUILD_OPT_CFG UserOptions; -extern CPU_FAMILY_SUPPORT_TABLE PstateFamilyServiceTable; - -extern -VOID -ExecuteWbinvdInstruction ( - IN OUT AMD_CONFIG_PARAMS *StdHeader - ); - -AGESA_STATUS -PstateCreateHeapInfo ( - IN PLATFORM_CONFIGURATION *PlatformConfig, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -/*---------------------------------------------------------------------------------------*/ -/** - * Performs CPU related initialization at the POST entry point - * - * This function performs a large list of initialization items. These items - * include: - * - * -1 AP MTRR sync - * -2 feature leveling - * -3 P-state data gather - * -4 P-state leveling - * -5 AP cache breakdown & release - * - * @param[in] StdHeader Config handle for library and services - * @param[in] PlatformConfig Config handle for platform specific information - * - * @retval AGESA_SUCCESS - * - */ -AGESA_STATUS -AmdCpuPost ( - IN AMD_CONFIG_PARAMS *StdHeader, - IN PLATFORM_CONFIGURATION *PlatformConfig - ) -{ - AGESA_STATUS AgesaStatus; - AGESA_STATUS CalledStatus; - - AgesaStatus = AGESA_SUCCESS; - // - // Sync variable MTRR - // - AGESA_TESTPOINT (TpProcCpuApMtrrSync, StdHeader); - SyncVariableMTRR (StdHeader); - - AGESA_TESTPOINT (TpProcCpuPostFeatureInit, StdHeader); - IDS_HDT_CONSOLE (CPU_TRACE, " Dispatch CPU features after AP MTRR sync\n"); - CalledStatus = DispatchCpuFeatures (CPU_FEAT_AFTER_POST_MTRR_SYNC, PlatformConfig, StdHeader); - if (CalledStatus > AgesaStatus) { - AgesaStatus = CalledStatus; - } - // - // Feature Leveling - // - AGESA_TESTPOINT (TpProcCpuFeatureLeveling, StdHeader); - IDS_HDT_CONSOLE (CPU_TRACE, " Perform feature leveling\n"); - FeatureLeveling (StdHeader); - // - // P-state Gathered and set heap info - // - IDS_HDT_CONSOLE (CPU_TRACE, " Create P-state info in the heap\n"); - PstateCreateHeapInfo (PlatformConfig, StdHeader); - - // Set TscFreqSel at the rate specified by the core P0 after core frequency leveling. - SetCoresTscFreqSel (StdHeader); - - // Dispatch CPU features before relinquishing control of APs - AGESA_TESTPOINT (TpProcCpuBeforeRelinquishAPsFeatureInit, StdHeader); - IDS_HDT_CONSOLE (CPU_TRACE, " Dispatch CPU features before Relinquishing control of APs\n"); - CalledStatus = DispatchCpuFeatures (CPU_FEAT_BEFORE_RELINQUISH_AP, PlatformConfig, StdHeader); - if (CalledStatus > AgesaStatus) { - AgesaStatus = CalledStatus; - } - - // Relinquish control of all APs to IBV. - IDS_HDT_CONSOLE (CPU_TRACE, " Relinquish control of APs\n"); - RelinquishControlOfAllAPs (StdHeader); - - return (AgesaStatus); -} - -/*--------------------------------------------------------------------------------------- - * L O C A L F U N C T I O N S - *--------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------*/ -/** - * Determines the address in system DRAM that should be used for p-state data - * gather and leveling. - * - * @param[out] Ptr Address to utilize - * @param[in] StdHeader Config handle for library and services - * - * @retval AGESA_SUCCESS - * - */ -AGESA_STATUS -GetPstateGatherDataAddressAtPost ( - OUT UINT64 **Ptr, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - UINT64 AddressValue; - - AddressValue = P_STATE_DATA_GATHER_TEMP_ADDR; - - *Ptr = (UINT64 *) (intptr_t) (AddressValue); - - return AGESA_SUCCESS; -} - - -/*---------------------------------------------------------------------------------------*/ -/** - * AP task to sync memory subsystem MSRs with the BSC - * - * This function processes a list of MSRs and the BSC's current values for those - * MSRs. This will allow the APs to see system RAM. - * - * @param[in] MtrrTable Memory related MSR table - * @param[in] StdHeader Config handle for library and services - * - */ -VOID -SyncAllApMtrrToBsc ( - IN VOID *MtrrTable, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - UINT8 i; - - for (i = 0; ((BSC_AP_MSR_SYNC *) MtrrTable)[i].RegisterAddress != 0; i++) { - LibAmdMsrWrite (((BSC_AP_MSR_SYNC *) MtrrTable)[i].RegisterAddress, - &((BSC_AP_MSR_SYNC *) MtrrTable)[i].RegisterValue, - StdHeader); - } -} - - -/*---------------------------------------------------------------------------------------*/ -/** - * Creates p-state information on the heap - * - * This function gathers p-state information from all processors in the system, - * determines a level set of p-states, and places that information into the - * heap. This heap data will be used by GenerateSsdt to generate the - * final _PSS and XPSS objects. - * - * @param[in] PlatformConfig Pointer to runtime configuration options - * @param[in] StdHeader Config handle for library and services - * - * @retval AGESA_SUCCESS No error - * @retval AGESA_ERROR CPU_ERROR_PSTATE_HEAP_NOT_AVAILABLE - */ -AGESA_STATUS -PstateCreateHeapInfo ( - IN PLATFORM_CONFIGURATION *PlatformConfig, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - AGESA_STATUS AgesaStatus; - S_CPU_AMD_PSTATE *PStateBufferPtr; - ALLOCATE_HEAP_PARAMS AllocHeapParams; - UINT8 *PStateBufferPtrInHeap; - - ASSERT (IsBsp (StdHeader, &AgesaStatus)); - - // - //Get proper address for gather data pool address - //Zero P-state gather data pool - // - GetPstateGatherDataAddressAtPost ((UINT64 **)&PStateBufferPtr, StdHeader); - LibAmdMemFill (PStateBufferPtr, 0, sizeof (S_CPU_AMD_PSTATE), StdHeader); - - // - //Get all the CPUs P-States and fill the PStateBufferPtr for each core - // - AgesaStatus = PStateGatherData (PlatformConfig, PStateBufferPtr, StdHeader); - if (AgesaStatus != AGESA_SUCCESS) { - return AgesaStatus; - } - - // - //Do Pstate Leveling for each core if needed. - // - AgesaStatus = PStateLeveling (PStateBufferPtr, StdHeader); - - // - //Create Heap and store p-state data for ACPI table in CpuLate - // - AllocHeapParams.RequestedBufferSize = PStateBufferPtr->SizeOfBytes; - AllocHeapParams.BufferHandle = AMD_PSTATE_DATA_BUFFER_HANDLE; - AllocHeapParams.Persist = HEAP_SYSTEM_MEM; - AgesaStatus = HeapAllocateBuffer (&AllocHeapParams, StdHeader); - if (AgesaStatus == AGESA_SUCCESS) { - // - // Zero Buffer - // - PStateBufferPtrInHeap = (UINT8 *) AllocHeapParams.BufferPtr; - LibAmdMemFill (PStateBufferPtrInHeap, 0, PStateBufferPtr->SizeOfBytes, StdHeader); - LibAmdMemCopy (PStateBufferPtrInHeap, PStateBufferPtr, PStateBufferPtr->SizeOfBytes, StdHeader); - - } else { - PutEventLog (AGESA_ERROR, - CPU_ERROR_PSTATE_HEAP_NOT_AVAILABLE, - 0, 0, 0, 0, StdHeader); - } - - return AgesaStatus; -} - -VOID -SyncApMsrsToBsc ( - IN OUT BSC_AP_MSR_SYNC *ApMsrSync, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - AP_TASK TaskPtr; - UINT16 i; - UINT32 BscSocket; - UINT32 Ignored; - UINT32 BscCoreNum; - UINT32 Core; - UINT32 Socket; - UINT32 NumberOfSockets; - UINT32 NumberOfCores; - AGESA_STATUS IgnoredSts; - - ASSERT (IsBsp (StdHeader, &IgnoredSts)); - - IdentifyCore (StdHeader, &BscSocket, &Ignored, &BscCoreNum, &IgnoredSts); - NumberOfSockets = GetPlatformNumberOfSockets (); - - // - //Sync all MTRR settings with BSP - // - for (i = 0; ApMsrSync[i].RegisterAddress != 0; i++) { - LibAmdMsrRead (ApMsrSync[i].RegisterAddress, &ApMsrSync[i].RegisterValue, StdHeader); - } - - TaskPtr.FuncAddress.PfApTaskI = SyncAllApMtrrToBsc; - TaskPtr.DataTransfer.DataSizeInDwords = (UINT16) ((((sizeof (BSC_AP_MSR_SYNC)) * i) + 4) >> 2); - TaskPtr.ExeFlags = WAIT_FOR_CORE; - TaskPtr.DataTransfer.DataPtr = ApMsrSync; - TaskPtr.DataTransfer.DataTransferFlags = 0; - - for (Socket = 0; Socket < NumberOfSockets; Socket++) { - if (GetActiveCoresInGivenSocket (Socket, &NumberOfCores, StdHeader)) { - for (Core = 0; Core < NumberOfCores; Core++) { - if ((Socket != BscSocket) || (Core != BscCoreNum)) { - ApUtilRunCodeOnSocketCore ((UINT8) Socket, (UINT8) Core, &TaskPtr, StdHeader); - } - } - } - } -} - -/*---------------------------------------------------------------------------------------*/ -/** - * SyncVariableMTRR - * - * Sync variable MTRR - * - * @param[in] StdHeader Config handle for library and services - * - */ -VOID -STATIC -SyncVariableMTRR ( - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - BSC_AP_MSR_SYNC ApMsrSync[20]; - - ApMsrSync[0].RegisterAddress = SYS_CFG; - ApMsrSync[1].RegisterAddress = TOP_MEM; - ApMsrSync[2].RegisterAddress = TOP_MEM2; - ApMsrSync[3].RegisterAddress = 0x200; - ApMsrSync[4].RegisterAddress = 0x201; - ApMsrSync[5].RegisterAddress = 0x202; - ApMsrSync[6].RegisterAddress = 0x203; - ApMsrSync[7].RegisterAddress = 0x204; - ApMsrSync[8].RegisterAddress = 0x205; - ApMsrSync[9].RegisterAddress = 0x206; - ApMsrSync[10].RegisterAddress = 0x207; - ApMsrSync[11].RegisterAddress = 0x208; - ApMsrSync[12].RegisterAddress = 0x209; - ApMsrSync[13].RegisterAddress = 0x20A; - ApMsrSync[14].RegisterAddress = 0x20B; - ApMsrSync[15].RegisterAddress = 0xC0010016; - ApMsrSync[16].RegisterAddress = 0xC0010017; - ApMsrSync[17].RegisterAddress = 0xC0010018; - ApMsrSync[18].RegisterAddress = 0xC0010019; - ApMsrSync[19].RegisterAddress = 0; - SyncApMsrsToBsc (ApMsrSync, StdHeader); -} - -/*---------------------------------------------------------------------------------------*/ -/** - * The function suppose to do any thing need to be done at the end of AmdInitPost. - * - * @param[in] StdHeader Config handle for library and services - * - * @retval AGESA_SUCCESS - * - */ -AGESA_STATUS -FinalizeAtPost ( - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - // - // Execute wbinvd to ensure heap data in cache write back to memory. - // - ExecuteWbinvdInstruction (StdHeader); - - return AGESA_SUCCESS; -} -/*---------------------------------------------------------------------------------------*/ -/** - * Set TSC Frequency Selection. - * - * This function set TSC Frequency Selection. - * - * @param[in] StdHeader Config handle for library and services - * - */ -VOID -STATIC -SetTscFreqSel ( - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - PSTATE_CPU_FAMILY_SERVICES *FamilyServices; - - FamilyServices = NULL; - - GetFeatureServicesOfCurrentCore (&PstateFamilyServiceTable, (const VOID **)&FamilyServices, StdHeader); - if (FamilyServices != NULL) { - FamilyServices->CpuSetTscFreqSel (FamilyServices, StdHeader); - } - -} - -/*---------------------------------------------------------------------------------------*/ -/** - * Set TSC Frequency Selection to all cores. - * - * This function set TscFreqSel to all cores in the system. - * - * @param[in] StdHeader Config handle for library and services - * - */ -VOID -SetCoresTscFreqSel ( - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - AP_TASK TaskPtr; - UINT32 BscSocket; - UINT32 Ignored; - UINT32 BscCoreNum; - UINT32 Core; - UINT32 Socket; - UINT32 NumberOfSockets; - UINT32 NumberOfCores; - AGESA_STATUS IgnoredSts; - - ASSERT (IsBsp (StdHeader, &IgnoredSts)); - - IdentifyCore (StdHeader, &BscSocket, &Ignored, &BscCoreNum, &IgnoredSts); - NumberOfSockets = GetPlatformNumberOfSockets (); - - SetTscFreqSel (StdHeader); - - TaskPtr.FuncAddress.PfApTask = SetTscFreqSel; - TaskPtr.ExeFlags = WAIT_FOR_CORE; - TaskPtr.DataTransfer.DataTransferFlags = 0; - TaskPtr.DataTransfer.DataSizeInDwords = 0; - TaskPtr.DataTransfer.DataPtr = NULL; - - for (Socket = 0; Socket < NumberOfSockets; Socket++) { - if (GetActiveCoresInGivenSocket (Socket, &NumberOfCores, StdHeader)) { - for (Core = 0; Core < NumberOfCores; Core++) { - if ((Socket != BscSocket) || (Core != BscCoreNum)) { - ApUtilRunCodeOnSocketCore ((UINT8) Socket, (UINT8) Core, &TaskPtr, StdHeader); - } - } - } - } -} diff --git a/src/vendorcode/amd/agesa/f12/Proc/CPU/cpuPostInit.h b/src/vendorcode/amd/agesa/f12/Proc/CPU/cpuPostInit.h deleted file mode 100644 index 4fd5781951..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/CPU/cpuPostInit.h +++ /dev/null @@ -1,231 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * AMD CPU Reset API, and related functions and structures. - * - * Contains code that initialized the CPU after early reset. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: CPU - * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $ - * - */ -/* - ****************************************************************************** - * - * Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - ****************************************************************************** - */ - -#ifndef _CPU_POST_INIT_H_ -#define _CPU_POST_INIT_H_ - - -/*--------------------------------------------------------------------------------------- - * M I X E D (Definitions And Macros / Typedefs, Structures, Enums) - *--------------------------------------------------------------------------------------- - */ -// Forward declaration needed for multi-structure mutual references -AGESA_FORWARD_DECLARATION (CPU_CFOH_FAMILY_SERVICES); - -/*--------------------------------------------------------------------------------------- - * D E F I N I T I O N S A N D M A C R O S - *--------------------------------------------------------------------------------------- - */ -#define P_STATE_DATA_GATHER_TEMP_ADDR 0x200000 ///< Fixed the row data at 2M memory address. -#define GLOBAL_CPU_FEATURE_LIST_TEMP_ADDR 0x200000 ///< Fixed the row data at 2M memory address. -/*--------------------------------------------------------------------------------------- - * T Y P E D E F S, S T R U C T U R E S, E N U M S - *--------------------------------------------------------------------------------------- - */ -//---------------------------------------------------------------------------- -// CPU FEATURE LEVELING TYPEDEFS, STRUCTURES, ENUMS -// -//---------------------------------------------------------------------------- -/// CPU FEATURE LIST -typedef struct { - UINT8 ABM:1; ///< byte 0 bit 0 - UINT8 AES:1; ///< byte 0 bit 1 - UINT8 AltMovCr8:1; ///< byte 0 bit 2 - UINT8 APIC:1; ///< byte 0 bit 3 - UINT8 AVX:1; ///< byte 0 bit 4 - UINT8 CLFSH:1; ///< byte 0 bit 5 - UINT8 CMOV:1; ///< byte 0 bit 6 - UINT8 CmpLegacy:1; ///< byte 0 bit 7 - UINT8 CMPXCHG8B:1; ///< byte 1 bit 0 - UINT8 CMPXCHG16B:1; ///< byte 1 bit 1 - UINT8 CVT16:1; ///< byte 1 bit 2 - UINT8 DE:1; ///< byte 1 bit 3 - UINT8 ExtApicSpace:1; ///< byte 1 bit 4 - UINT8 FFXSR:1; ///< byte 1 bit 5 - UINT8 FMA:1; ///< byte 1 bit 6 - UINT8 FMA4:1; ///< byte 1 bit 7 - UINT8 FPU:1; ///< byte 2 bit 0 - UINT8 FXSR:1; ///< byte 2 bit 1 - UINT8 HTT:1; ///< byte 2 bit 2 - UINT8 IBS:1; ///< byte 2 bit 3 - UINT8 LahfSahf:1; ///< byte 2 bit 4 - UINT8 LM:1; ///< byte 2 bit 5 - UINT8 LWP:1; ///< byte 2 bit 6 - UINT8 MCA:1; ///< byte 2 bit 7 - UINT8 MCE:1; ///< byte 3 bit 0 - UINT8 MisAlignSse:1; ///< byte 3 bit 1 - UINT8 MMX:1; ///< byte 3 bit 2 - UINT8 MmxExt:1; ///< byte 3 bit 3 - UINT8 Monitor:1; ///< byte 3 bit 4 - UINT8 MSR:1; ///< byte 3 bit 5 - UINT8 MTRR:1; ///< byte 3 bit 6 - UINT8 NodeId:1; ///< byte 3 bit 7 - UINT8 NX:1; ///< byte 4 bit 0 - UINT8 OSVW:1; ///< byte 4 bit 1 - UINT8 OSXSAVE:1; ///< byte 4 bit 2 - UINT8 PAE:1; ///< byte 4 bit 3 - UINT8 Page1GB:1; ///< byte 4 bit 4 - UINT8 PAT:1; ///< byte 4 bit 5 - UINT8 PCLMULQDQ:1; ///< byte 4 bit 6 - UINT8 PGE:1; ///< byte 4 bit 7 - UINT8 POPCNT:1; ///< byte 5 bit 0 - UINT8 PSE:1; ///< byte 5 bit 1 - UINT8 PSE36:1; ///< byte 5 bit 2 - UINT8 RDTSCP:1; ///< byte 5 bit 3 - UINT8 SKINIT:1; ///< byte 5 bit 4 - UINT8 SSE:1; ///< byte 5 bit 5 - UINT8 SSE2:1; ///< byte 5 bit 6 - UINT8 SSE3:1; ///< byte 5 bit 7 - UINT8 SSE4A:1; ///< byte 6 bit 0 - UINT8 SSE41:1; ///< byte 6 bit 1 - UINT8 SSE42:1; ///< byte 6 bit 2 - UINT8 SSE5:1; ///< byte 6 bit 3 - UINT8 SSSE3:1; ///< byte 6 bit 4 - UINT8 SVM:1; ///< byte 6 bit 5 - UINT8 SysCallSysRet:1; ///< byte 6 bit 6 - UINT8 SysEnterSysExit:1; ///< byte 6 bit 7 - UINT8 TBM0:1; ///< byte 7 bit 0 - UINT8 TCE:1; ///< byte 7 bit 1 - UINT8 ThreeDNow:1; ///< byte 7 bit 2 - UINT8 ThreeDNowExt:1; ///< byte 7 bit 3 - UINT8 ThreeDNowPrefetch:1; ///< byte 7 bit 4 - UINT8 TimeStampCounter:1; ///< byte 7 bit 5 - UINT8 VME:1; ///< byte 7 bit 6 - UINT8 WDT:1; ///< byte 7 bit 7 - UINT8 X2APIC:1; ///< byte 8 bit 0 - UINT8 XOP:1; ///< byte 8 bit 1 - UINT8 XSAVE:1; ///< byte 8 bit 2 - UINT8 Reserve:5; ///< Reserved -} CPU_FEATURES_LIST; - -//---------------------------------------------------------------------------- -// POST INIT TYPEDEFS, STRUCTURES, ENUMS -// -//---------------------------------------------------------------------------- -/// BSC to AP MSR sync up -typedef struct { - UINT32 RegisterAddress; ///< MSR Address - UINT64 RegisterValue; ///< BSC's MSR Value -} BSC_AP_MSR_SYNC; - -/** - * Set Cache Flush On Halt Register. - * - * @CpuServiceInstances - * - * @param[in] FamilySpecificServices The current Family Specific Services. - * @param[in] EntryPoint Timepoint designator. - * @param[in] PlatformConfig Contains the runtime modifiable feature input data. - * @param[in] StdHeader Handle of Header for calling lib functions and services. - * - */ -typedef VOID (F_CPU_SET_CFOH_REG) ( - IN CPU_CFOH_FAMILY_SERVICES *FamilySpecificServices, - IN UINT64 EntryPoint, - IN PLATFORM_CONFIGURATION *PlatformConfig, - IN AMD_CONFIG_PARAMS *StdHeader - ); - - /// Reference to a Method. -typedef F_CPU_SET_CFOH_REG *PF_CPU_SET_CFOH_REG; - -/** - * Provide the interface to the Cache Flush On Halt Family Specific Services. - * - * Use the methods or data in this struct to adapt the feature code to a specific cpu family or model (or stepping!). - * Each supported Family must provide an implementation for all methods in this interface, even if the - * implementation is a CommonReturn(). - */ -struct _CPU_CFOH_FAMILY_SERVICES { // See forward reference above - UINT16 Revision; ///< Interface version - // Public Methods. - PF_CPU_SET_CFOH_REG SetCacheFlushOnHaltRegister; ///< Method: Set Cache Flush On Halt register. -}; - -/*--------------------------------------------------------------------------------------- - * F U N C T I O N P R O T O T Y P E - *--------------------------------------------------------------------------------------- - */ - -// These are P U B L I C functions, used by IBVs -AGESA_STATUS -AmdCpuPost ( - IN AMD_CONFIG_PARAMS *StdHeader, - IN PLATFORM_CONFIGURATION *PlatformConfig - ); - -// These are P U B L I C functions, used by AGESA - -VOID -FeatureLeveling ( - IN OUT AMD_CONFIG_PARAMS *StdHeader - ); - -AGESA_STATUS -CopyHeapToTempRamAtPost ( - IN OUT AMD_CONFIG_PARAMS *StdHeader - ); - -AGESA_STATUS -CopyHeapToMainRamAtPost ( - IN OUT AMD_CONFIG_PARAMS *StdHeader - ); - -VOID -SyncApMsrsToBsc ( - IN OUT BSC_AP_MSR_SYNC *ApMsrSync, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -AGESA_STATUS -FinalizeAtPost ( - IN AMD_CONFIG_PARAMS *StdHeader - ); - -VOID -SetCoresTscFreqSel ( - IN AMD_CONFIG_PARAMS *StdHeader - ); -#endif // _CPU_POST_INIT_H_ - diff --git a/src/vendorcode/amd/agesa/f12/Proc/CPU/cpuPowerMgmt.c b/src/vendorcode/amd/agesa/f12/Proc/CPU/cpuPowerMgmt.c deleted file mode 100644 index db7a1d1cac..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/CPU/cpuPowerMgmt.c +++ /dev/null @@ -1,251 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * AMD CPU Power Management functions. - * - * Contains code for doing early power management - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: CPU - * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $ - * - */ -/* - **************************************************************************** - * - * Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - ****************************************************************************** - */ - -/*---------------------------------------------------------------------------------------- - * M O D U L E S U S E D - *---------------------------------------------------------------------------------------- - */ - -#include "AGESA.h" -#include "amdlib.h" -#include "cpuRegisters.h" -#include "cpuFamilyTranslation.h" -#include "OptionMultiSocket.h" -#include "cpuApicUtilities.h" -#include "cpuEarlyInit.h" -#include "cpuPowerMgmtSystemTables.h" -#include "cpuServices.h" -#include "Filecode.h" -CODE_GROUP (G1_PEICC) -RDATA_GROUP (G1_PEICC) - -#define FILECODE PROC_CPU_CPUPOWERMGMT_FILECODE -/*---------------------------------------------------------------------------------------- - * D E F I N I T I O N S A N D M A C R O S - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------- - * T Y P E D E F S A N D S T R U C T U R E S - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------- - * P R O T O T Y P E S O F L O C A L F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ -VOID -STATIC -PerformThisPmStep ( - IN VOID *Step, - IN AMD_CONFIG_PARAMS *StdHeader, - IN AMD_CPU_EARLY_PARAMS *CpuEarlyParamsPtr - ); - -VOID -STATIC -GoToMemInitPstateCore0 ( - IN AMD_CONFIG_PARAMS *StdHeader, - IN AMD_CPU_EARLY_PARAMS *CpuEarlyParamsPtr - ); - -VOID -STATIC -GoToMemInitPstateCore ( - IN AMD_CONFIG_PARAMS *StdHeader, - IN AMD_CPU_EARLY_PARAMS *CpuEarlyParamsPtr - ); - -/*---------------------------------------------------------------------------------------- - * E X P O R T E D F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ -extern OPTION_MULTISOCKET_CONFIGURATION OptionMultiSocketConfiguration; - -/*---------------------------------------------------------------------------------------*/ -/** - * Perform the "BIOS Requirements for P-State Initialization and Transitions." - * - * This is the generic arbiter code to be executed by the BSC. The system power - * management init tables will be traversed. This must be run by the system BSC - * only. - * - * @param[in] CpuEarlyParams Required input parameters for early CPU initialization - * @param[in] StdHeader Config handle for library and services - * - * @return Most severe AGESA_STATUS level that any system processor encountered - * - */ -AGESA_STATUS -PmInitializationAtEarly ( - IN AMD_CPU_EARLY_PARAMS *CpuEarlyParams, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - UINT8 i; - UINT8 NumberOfSystemWideSteps; - AP_TASK TaskPtr; - AGESA_STATUS ReturnCode; - WARM_RESET_REQUEST Request; - - // Determine the number of steps to perform - OptionMultiSocketConfiguration.GetNumberOfSystemPmSteps (&NumberOfSystemWideSteps, StdHeader); - - // Traverse the PM init table - TaskPtr.FuncAddress.PfApTaskIC = PerformThisPmStep; - TaskPtr.DataTransfer.DataSizeInDwords = 1; - TaskPtr.DataTransfer.DataPtr = &i; - TaskPtr.DataTransfer.DataTransferFlags = 0; - TaskPtr.ExeFlags = PASS_EARLY_PARAMS; - for (i = 0; i < NumberOfSystemWideSteps; ++i) { - IDS_HDT_CONSOLE (CPU_TRACE, " Perform PM init step %d\n", i); - OptionMultiSocketConfiguration.BscRunCodeOnAllSystemCore0s (&TaskPtr, StdHeader, CpuEarlyParams); - } - - // GoToMemInitPstateCore0 only if there is no pending warm reset. - GetWarmResetFlag (StdHeader, &Request); - if (Request.RequestBit == FALSE) { - TaskPtr.FuncAddress.PfApTaskC = GoToMemInitPstateCore0; - TaskPtr.DataTransfer.DataSizeInDwords = 0; - TaskPtr.ExeFlags = PASS_EARLY_PARAMS; - IDS_HDT_CONSOLE (CPU_TRACE, " Transition all cores to POST P-state\n"); - OptionMultiSocketConfiguration.BscRunCodeOnAllSystemCore0s (&TaskPtr, StdHeader, CpuEarlyParams); - } - - // Retrieve/Process any errors - ReturnCode = OptionMultiSocketConfiguration.BscRetrievePmEarlyInitErrors (StdHeader); - - return (ReturnCode); -} - - -/*---------------------------------------------------------------------------------------*/ -/** - * Performs the next step in the executing core 0's family specific power - * management table. - * - * This function determines if the input step is valid, and invokes the power - * management step if appropriate. This must be run by processor core 0s only. - * - * @param[in] Step Zero based step number - * @param[in] StdHeader Config handle for library and services - * @param[in] CpuEarlyParamsPtr Required input parameters for early CPU initialization - * - */ -VOID -STATIC -PerformThisPmStep ( - IN VOID *Step, - IN AMD_CONFIG_PARAMS *StdHeader, - IN AMD_CPU_EARLY_PARAMS *CpuEarlyParamsPtr - ) -{ - UINT8 MyNumberOfSteps; - SYS_PM_TBL_STEP *FamilyTablePtr; - CPU_SPECIFIC_SERVICES *FamilySpecificServices; - - GetCpuServicesOfCurrentCore ((const CPU_SPECIFIC_SERVICES **)&FamilySpecificServices, StdHeader); - FamilySpecificServices->GetSysPmTableStruct (FamilySpecificServices, (const VOID **)&FamilyTablePtr, &MyNumberOfSteps, StdHeader); - - if (*(UINT8 *)Step < MyNumberOfSteps) { - if (FamilyTablePtr[*(UINT8 *)Step].FuncPtr != NULL) { - if (!(BOOLEAN) (FamilyTablePtr[*(UINT8 *)Step].ExeFlags & PM_EXEFLAGS_WARM_ONLY) || - IsWarmReset (StdHeader)) { - FamilyTablePtr[*(UINT8 *)Step].FuncPtr (FamilySpecificServices, CpuEarlyParamsPtr, StdHeader); - } - } - } -} - - -/*---------------------------------------------------------------------------------------*/ -/** - * Transitions the executing processor to the desired P-state. - * - * This function implements the AMD_CPU_EARLY_PARAMS.MemInitPState parameter, and is - * run by all processor core 0s. - * - * @param[in] StdHeader Config handle for library and services - * @param[in] CpuEarlyParamsPtr Required input parameters for early CPU initialization - * - */ -VOID -STATIC -GoToMemInitPstateCore0 ( - IN AMD_CONFIG_PARAMS *StdHeader, - IN AMD_CPU_EARLY_PARAMS *CpuEarlyParamsPtr - ) -{ - AP_TASK TaskPtr; - - TaskPtr.FuncAddress.PfApTaskC = GoToMemInitPstateCore; - TaskPtr.DataTransfer.DataSizeInDwords = 0; - TaskPtr.ExeFlags = WAIT_FOR_CORE | PASS_EARLY_PARAMS; - ApUtilRunCodeOnAllLocalCoresAtEarly (&TaskPtr, StdHeader, CpuEarlyParamsPtr); -} - - -/*---------------------------------------------------------------------------------------*/ -/** - * Transitions the executing core to the desired P-state. - * - * This function implements the AMD_CPU_EARLY_PARAMS.MemInitPState parameter, and is - * run by all system cores. - * - * @param[in] StdHeader Config handle for library and services - * @param[in] CpuEarlyParamsPtr Required input parameters for early CPU initialization - * - */ -VOID -STATIC -GoToMemInitPstateCore ( - IN AMD_CONFIG_PARAMS *StdHeader, - IN AMD_CPU_EARLY_PARAMS *CpuEarlyParamsPtr - ) -{ - CPU_SPECIFIC_SERVICES *FamilySpecificServices; - - GetCpuServicesOfCurrentCore ((const CPU_SPECIFIC_SERVICES **)&FamilySpecificServices, StdHeader); - FamilySpecificServices->TransitionPstate (FamilySpecificServices, CpuEarlyParamsPtr->MemInitPState, (BOOLEAN) FALSE, StdHeader); -} diff --git a/src/vendorcode/amd/agesa/f12/Proc/CPU/cpuPowerMgmtMultiSocket.c b/src/vendorcode/amd/agesa/f12/Proc/CPU/cpuPowerMgmtMultiSocket.c deleted file mode 100644 index 330f46bf5f..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/CPU/cpuPowerMgmtMultiSocket.c +++ /dev/null @@ -1,487 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * AMD CPU Power Management Multisocket Functions. - * - * Contains code for doing power management for multisocket CPUs - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: CPU - * @e \$Revision: 48937 $ @e \$Date: 2011-03-15 03:37:15 +0800 (Tue, 15 Mar 2011) $ - * - */ -/* - ****************************************************************************** - * - * Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - ****************************************************************************** - */ - -/*---------------------------------------------------------------------------------------- - * M O D U L E S U S E D - *---------------------------------------------------------------------------------------- - */ - -#include "AGESA.h" -#include "amdlib.h" -#include "Ids.h" -#include "cpuRegisters.h" -#include "GeneralServices.h" -#include "cpuServices.h" -#include "cpuApicUtilities.h" -#include "cpuFamilyTranslation.h" -#include "cpuPowerMgmtSystemTables.h" -#include "cpuPowerMgmtMultiSocket.h" -#include "GeneralServices.h" -#include "Filecode.h" -CODE_GROUP (G1_PEICC) -RDATA_GROUP (G1_PEICC) - -#define FILECODE PROC_CPU_CPUPOWERMGMTMULTISOCKET_FILECODE -/*---------------------------------------------------------------------------------------- - * D E F I N I T I O N S A N D M A C R O S - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------- - * T Y P E D E F S A N D S T R U C T U R E S - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------- - * P R O T O T Y P E S O F L O C A L F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ -VOID -STATIC -GetNextEvent ( - IN OUT VOID *EventLogEntryPtr, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -/*---------------------------------------------------------------------------------------- - * E X P O R T E D F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------*/ -/** - * Multisocket BSC call to start all system core 0s to perform a standard AP_TASK. - * - * This function loops through all possible socket locations, starting core 0 of - * each populated socket to perform the passed in AP_TASK. After starting all - * other core 0s, the BSC will perform the AP_TASK as well. This must be run by - * the system BSC only. - * - * @param[in] TaskPtr Function descriptor - * @param[in] StdHeader Config handle for library and services - * @param[in] ConfigParams AMD entry point's CPU parameter structure - * - */ -VOID -RunCodeOnAllSystemCore0sMulti ( - IN AP_TASK *TaskPtr, - IN AMD_CONFIG_PARAMS *StdHeader, - IN VOID *ConfigParams - ) -{ - UINT32 BscSocket; - UINT32 BscModule; - UINT32 BscCoreNum; - UINT8 Socket; - UINT32 NumberOfSockets; - AGESA_STATUS DummyStatus; - - ASSERT (IsBsp (StdHeader, &DummyStatus)); - - NumberOfSockets = GetPlatformNumberOfSockets (); - - IdentifyCore (StdHeader, &BscSocket, &BscModule, &BscCoreNum, &DummyStatus); - - for (Socket = 0; Socket < NumberOfSockets; Socket++) { - if (Socket != BscSocket) { - if (IsProcessorPresent (Socket, StdHeader)) { - ApUtilRunCodeOnSocketCore (Socket, 0, TaskPtr, StdHeader); - } - } - } - ApUtilTaskOnExecutingCore (TaskPtr, StdHeader, ConfigParams); -} - - -/*---------------------------------------------------------------------------------------*/ -/** - * Multisocket BSC call to determine the maximum number of steps that any single - * processor needs to execute. - * - * This function loops through all possible socket locations, gathering the number - * of power management steps each populated socket requires, and returns the - * highest number. - * - * @param[out] NumSystemSteps Maximum number of system steps required - * @param[in] StdHeader Config handle for library and services - * - */ -VOID -GetNumberOfSystemPmStepsPtrMulti ( - OUT UINT8 *NumSystemSteps, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - UINT8 NumberOfSteps; - UINT32 NumberOfSockets; - UINT32 Socket; - SYS_PM_TBL_STEP *Ignored; - CPU_SPECIFIC_SERVICES *FamilySpecificServices; - - NumberOfSockets = GetPlatformNumberOfSockets (); - *NumSystemSteps = 0; - - for (Socket = 0; Socket < NumberOfSockets; Socket++) { - if (IsProcessorPresent (Socket, StdHeader)) { - GetCpuServicesOfSocket (Socket, (const CPU_SPECIFIC_SERVICES **)&FamilySpecificServices, StdHeader); - FamilySpecificServices->GetSysPmTableStruct (FamilySpecificServices, (const VOID **)&Ignored, &NumberOfSteps, StdHeader); - if (NumberOfSteps > *NumSystemSteps) { - *NumSystemSteps = NumberOfSteps; - } - } - } -} - - -/*---------------------------------------------------------------------------------------*/ -/** - * Multisocket call to determine the frequency that the northbridges must run. - * - * This function loops through all possible socket locations, comparing the - * maximum NB frequencies to determine the slowest. This function also - * determines if all coherent NB frequencies are equivalent. - * - * @param[in] NbPstate NB P-state number to check (0 = fastest) - * @param[in] PlatformConfig Platform profile/build option config structure. - * @param[out] SystemNbCofNumerator NB frequency numerator for the system in MHz - * @param[out] SystemNbCofDenominator NB frequency denominator for the system - * @param[out] SystemNbCofsMatch Whether or not all NB frequencies are equivalent - * @param[out] NbPstateIsEnabledOnAllCPUs Whether or not NbPstate is valid on all CPUs - * @param[in] StdHeader Config handle for library and services - * - * @retval TRUE At least one processor has NbPstate enabled. - * @retval FALSE NbPstate is disabled on all CPUs - * - */ -BOOLEAN -GetSystemNbCofMulti ( - IN UINT32 NbPstate, - IN PLATFORM_CONFIGURATION *PlatformConfig, - OUT UINT32 *SystemNbCofNumerator, - OUT UINT32 *SystemNbCofDenominator, - OUT BOOLEAN *SystemNbCofsMatch, - OUT BOOLEAN *NbPstateIsEnabledOnAllCPUs, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - UINT32 Socket; - UINT8 Module; - UINT32 CurrentNbCof; - UINT32 CurrentDivisor; - UINT32 CurrentFreq; - UINT32 LowFrequency; - UINT32 Ignored32; - BOOLEAN FirstCofNotFound; - BOOLEAN NbPstateDisabled; - BOOLEAN IsNbPstateEnabledOnAny; - PCI_ADDR PciAddress; - AGESA_STATUS Ignored; - CPU_SPECIFIC_SERVICES *FamilySpecificServices; - - // Find the slowest NB COF in the system & whether or not all are equivalent - LowFrequency = 0xFFFFFFFF; - *SystemNbCofsMatch = TRUE; - *NbPstateIsEnabledOnAllCPUs = FALSE; - IsNbPstateEnabledOnAny = FALSE; - FirstCofNotFound = TRUE; - NbPstateDisabled = FALSE; - for (Socket = 0; Socket < GetPlatformNumberOfSockets (); Socket++) { - if (IsProcessorPresent (Socket, StdHeader)) { - GetCpuServicesOfSocket (Socket, (const CPU_SPECIFIC_SERVICES **)&FamilySpecificServices, StdHeader); - for (Module = 0; Module < GetPlatformNumberOfModules (); Module++) { - if (GetPciAddress (StdHeader, Socket, Module, &PciAddress, &Ignored)) { - break; - } - } - if (FamilySpecificServices->GetNbPstateInfo (FamilySpecificServices, - PlatformConfig, - &PciAddress, - NbPstate, - &CurrentNbCof, - &CurrentDivisor, - &Ignored32, - StdHeader)) { - ASSERT (CurrentDivisor != 0); - CurrentFreq = (CurrentNbCof / CurrentDivisor); - if (FirstCofNotFound) { - *SystemNbCofNumerator = CurrentNbCof; - *SystemNbCofDenominator = CurrentDivisor; - LowFrequency = CurrentFreq; - IsNbPstateEnabledOnAny = TRUE; - if (!NbPstateDisabled) { - *NbPstateIsEnabledOnAllCPUs = TRUE; - } - FirstCofNotFound = FALSE; - } else { - if (CurrentFreq != LowFrequency) { - *SystemNbCofsMatch = FALSE; - if (CurrentFreq < LowFrequency) { - LowFrequency = CurrentFreq; - *SystemNbCofNumerator = CurrentNbCof; - *SystemNbCofDenominator = CurrentDivisor; - } - } - } - } else { - NbPstateDisabled = TRUE; - *NbPstateIsEnabledOnAllCPUs = FALSE; - } - } - } - return IsNbPstateEnabledOnAny; -} - - -/*---------------------------------------------------------------------------------------*/ -/** - * Multisocket call to determine if the BIOS is responsible for updating the - * northbridge operating frequency and voltage. - * - * This function loops through all possible socket locations, checking whether - * any populated sockets require NB COF VID programming. - * - * @param[in] StdHeader Config handle for library and services - * - * @retval TRUE BIOS needs to set up NB frequency and voltage - * @retval FALSE BIOS does not need to set up NB frequency and voltage - * - */ -BOOLEAN -GetSystemNbCofVidUpdateMulti ( - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - UINT8 Module; - UINT32 Socket; - UINT32 NumberOfSockets; - BOOLEAN IgnoredBool; - BOOLEAN AtLeast1RequiresUpdate; - PCI_ADDR PciAddress; - AGESA_STATUS Ignored; - CPU_SPECIFIC_SERVICES *FamilySpecificServices; - - NumberOfSockets = GetPlatformNumberOfSockets (); - - AtLeast1RequiresUpdate = FALSE; - for (Socket = 0; Socket < NumberOfSockets; Socket++) { - if (IsProcessorPresent (Socket, StdHeader)) { - GetCpuServicesOfSocket (Socket, (const CPU_SPECIFIC_SERVICES **)&FamilySpecificServices, StdHeader); - for (Module = 0; Module < GetPlatformNumberOfModules (); Module++) { - if (GetPciAddress (StdHeader, (UINT8) Socket, Module, &PciAddress, &Ignored)) { - break; - } - } - if (FamilySpecificServices->IsNbCofInitNeeded (FamilySpecificServices, &PciAddress, &IgnoredBool, StdHeader)) { - AtLeast1RequiresUpdate = TRUE; - break; - } - } - } - return AtLeast1RequiresUpdate; -} - - -/*---------------------------------------------------------------------------------------*/ -/** - * Multisocket call to determine the most severe AGESA_STATUS return value after - * processing the power management initialization tables. - * - * This function loops through all possible socket locations, collecting any - * power management initialization errors that may have occurred. These errors - * are transferred from the core 0s of the socket in which the errors occurred - * to the BSC's heap. The BSC's heap is then searched for the most severe error - * that occurred, and returns it. This function must be called by the BSC only. - * - * @param[in] StdHeader Config handle for library and services - * - * @return The most severe error code from power management init - * - */ -AGESA_STATUS -GetEarlyPmErrorsMulti ( - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - UINT16 i; - UINT32 BscSocket; - UINT32 BscModule; - UINT32 BscCoreNum; - UINT32 Socket; - UINT32 NumberOfSockets; - AP_TASK TaskPtr; - AGESA_EVENT EventLogEntry; - AGESA_STATUS ReturnCode; - AGESA_STATUS DummyStatus; - - ASSERT (IsBsp (StdHeader, &ReturnCode)); - - ReturnCode = AGESA_SUCCESS; - EventLogEntry.EventClass = AGESA_SUCCESS; - EventLogEntry.EventInfo = 0; - EventLogEntry.DataParam1 = 0; - EventLogEntry.DataParam2 = 0; - EventLogEntry.DataParam3 = 0; - EventLogEntry.DataParam4 = 0; - - NumberOfSockets = GetPlatformNumberOfSockets (); - IdentifyCore (StdHeader, &BscSocket, &BscModule, &BscCoreNum, &DummyStatus); - - TaskPtr.FuncAddress.PfApTaskI = GetNextEvent; - TaskPtr.DataTransfer.DataSizeInDwords = SIZE_IN_DWORDS (AGESA_EVENT); - TaskPtr.DataTransfer.DataPtr = &EventLogEntry; - TaskPtr.DataTransfer.DataTransferFlags = 0; - TaskPtr.ExeFlags = WAIT_FOR_CORE | RETURN_PARAMS; - for (Socket = 0; Socket < NumberOfSockets; Socket++) { - if (Socket != BscSocket) { - if (IsProcessorPresent (Socket, StdHeader)) { - do { - ApUtilRunCodeOnSocketCore ((UINT8)Socket, (UINT8) 0, &TaskPtr, StdHeader); - if ((EventLogEntry.EventInfo & CPU_EVENT_PM_EVENT_MASK) == CPU_EVENT_PM_EVENT_CLASS) { - PutEventLog ( - EventLogEntry.EventClass, - EventLogEntry.EventInfo, - EventLogEntry.DataParam1, - EventLogEntry.DataParam2, - EventLogEntry.DataParam3, - EventLogEntry.DataParam4, - StdHeader - ); - } - } while (EventLogEntry.EventInfo != 0); - } - } - } - - for (i = 0; PeekEventLog (&EventLogEntry, i, StdHeader); i++) { - if ((EventLogEntry.EventInfo & CPU_EVENT_PM_EVENT_MASK) == CPU_EVENT_PM_EVENT_CLASS) { - if (EventLogEntry.EventClass > ReturnCode) { - ReturnCode = EventLogEntry.EventClass; - } - } - } - return (ReturnCode); -} - -/** - * Multisocket call to loop through all possible socket locations and Nb Pstates, - * comparing the NB frequencies to determine the slowest system and P0 frequency - * - * @param[in] PlatformConfig Platform profile/build option config structure. - * @param[out] MinSysNbFreq NB frequency numerator for the system in MHz - * @param[out] MinP0NbFreq NB frequency numerator for P0 in MHz - * @param[in] StdHeader Config handle for library and services - */ -VOID -GetMinNbCofMulti ( - IN PLATFORM_CONFIGURATION *PlatformConfig, - OUT UINT32 *MinSysNbFreq, - OUT UINT32 *MinP0NbFreq, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - UINT32 Socket; - UINT32 Module; - UINT32 CurrMinFreq; - UINT32 CurrMaxFreq; - PCI_ADDR PciAddress; - AGESA_STATUS Ignored; - CPU_SPECIFIC_SERVICES *FamilySpecificServices; - - *MinSysNbFreq = 0xFFFFFFFF; - *MinP0NbFreq = 0xFFFFFFFF; - - for (Socket = 0; Socket < GetPlatformNumberOfSockets (); Socket++) { - if (IsProcessorPresent (Socket, StdHeader)) { - GetCpuServicesOfSocket (Socket, (const CPU_SPECIFIC_SERVICES **) &FamilySpecificServices, StdHeader); - for (Module = 0; Module < GetPlatformNumberOfModules (); Module++) { - if (GetPciAddress (StdHeader, Socket, Module, &PciAddress, &Ignored )) { - break; - } - } - - - FamilySpecificServices->GetMinMaxNbFrequency (FamilySpecificServices, - PlatformConfig, - &PciAddress, - &CurrMinFreq, - &CurrMaxFreq, - StdHeader); - // Determine the slowest NB Pmin frequency - if (CurrMinFreq < *MinSysNbFreq) { - *MinSysNbFreq = CurrMinFreq; - } - - // Determine the slowest NB P0 frequency - if (CurrMaxFreq < *MinP0NbFreq) { - *MinP0NbFreq = CurrMaxFreq; - } - } - } -} - -/*--------------------------------------------------------------------------------------- - * L O C A L F U N C T I O N S - *--------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------*/ -/** - * AP task to return the next event log entry to the BSC. - * - * This function calls to the event log manager to retrieve the next error out - * of the heap. - * - * @param[out] EventLogEntryPtr The AP's next event log entry - * @param[in] StdHeader Config handle for library and services - * - */ -VOID -STATIC -GetNextEvent ( - IN OUT VOID *EventLogEntryPtr, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - GetEventLog ((AGESA_EVENT *) EventLogEntryPtr, StdHeader); -} diff --git a/src/vendorcode/amd/agesa/f12/Proc/CPU/cpuPowerMgmtMultiSocket.h b/src/vendorcode/amd/agesa/f12/Proc/CPU/cpuPowerMgmtMultiSocket.h deleted file mode 100644 index caeb96f672..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/CPU/cpuPowerMgmtMultiSocket.h +++ /dev/null @@ -1,113 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * AMD CPU Power Management Multisocket Functions. - * - * Contains code for doing power management for multisocket CPUs - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: CPU - * @e \$Revision: 48937 $ @e \$Date: 2011-03-15 03:37:15 +0800 (Tue, 15 Mar 2011) $ - * - */ -/* - ****************************************************************************** - * - * Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - ****************************************************************************** - */ - -#ifndef _CPU_POWER_MGMT_MULTI_SOCKET_H_ -#define _CPU_POWER_MGMT_MULTI_SOCKET_H_ - - -/*--------------------------------------------------------------------------------------- - * M I X E D (Definitions And Macros / Typedefs, Structures, Enums) - *--------------------------------------------------------------------------------------- - */ - - -/*--------------------------------------------------------------------------------------- - * D E F I N I T I O N S A N D M A C R O S - *--------------------------------------------------------------------------------------- - */ - - -/*--------------------------------------------------------------------------------------- - * T Y P E D E F S, S T R U C T U R E S, E N U M S - *--------------------------------------------------------------------------------------- - */ - - -/*--------------------------------------------------------------------------------------- - * F U N C T I O N P R O T O T Y P E - *--------------------------------------------------------------------------------------- - */ -VOID -RunCodeOnAllSystemCore0sMulti ( - IN AP_TASK *TaskPtr, - IN AMD_CONFIG_PARAMS *StdHeader, - IN VOID *ConfigParams - ); - -VOID -GetNumberOfSystemPmStepsPtrMulti ( - OUT UINT8 *NumSystemSteps, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -BOOLEAN -GetSystemNbCofMulti ( - IN UINT32 NbPstate, - IN PLATFORM_CONFIGURATION *PlatformConfig, - OUT UINT32 *SystemNbCofNumerator, - OUT UINT32 *SystemNbCofDenominator, - OUT BOOLEAN *SystemNbCofsMatch, - OUT BOOLEAN *NbPstateIsEnabledOnAllCPUs, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -BOOLEAN -GetSystemNbCofVidUpdateMulti ( - IN AMD_CONFIG_PARAMS *StdHeader - ); - -VOID -GetMinNbCofMulti ( - IN PLATFORM_CONFIGURATION *PlatformConfig, - OUT UINT32 *MinSysNbFreq, - OUT UINT32 *MinP0NbFreq, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -AGESA_STATUS -GetEarlyPmErrorsMulti ( - IN AMD_CONFIG_PARAMS *StdHeader - ); - -#endif // _CPU_POWER_MGMT_MULTI_SOCKET_H_ diff --git a/src/vendorcode/amd/agesa/f12/Proc/CPU/cpuPowerMgmtSingleSocket.c b/src/vendorcode/amd/agesa/f12/Proc/CPU/cpuPowerMgmtSingleSocket.c deleted file mode 100644 index 38d7afabcf..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/CPU/cpuPowerMgmtSingleSocket.c +++ /dev/null @@ -1,273 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * AMD CPU Power Management Single Socket Functions. - * - * Contains code for doing power management for single socket CPU - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: CPU - * @e \$Revision: 48937 $ @e \$Date: 2011-03-15 03:37:15 +0800 (Tue, 15 Mar 2011) $ - * - */ -/* - ****************************************************************************** - * - * Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - ****************************************************************************** - */ - -/*---------------------------------------------------------------------------------------- - * M O D U L E S U S E D - *---------------------------------------------------------------------------------------- - */ - -#include "AGESA.h" -#include "amdlib.h" -#include "GeneralServices.h" -#include "cpuRegisters.h" -#include "cpuApicUtilities.h" -#include "cpuFamilyTranslation.h" -#include "cpuPowerMgmtSystemTables.h" -#include "cpuPowerMgmtSingleSocket.h" -#include "Filecode.h" -CODE_GROUP (G1_PEICC) -RDATA_GROUP (G1_PEICC) - -#define FILECODE PROC_CPU_CPUPOWERMGMTSINGLESOCKET_FILECODE -/*---------------------------------------------------------------------------------------- - * D E F I N I T I O N S A N D M A C R O S - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------- - * T Y P E D E F S A N D S T R U C T U R E S - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------- - * P R O T O T Y P E S O F L O C A L F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------- - * E X P O R T E D F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------*/ -/** - * Single socket BSC call to start all system core 0s to perform a standard AP_TASK. - * - * This function will simply invoke the task on the executing core. This must be - * run by the system BSC only. - * - * @param[in] TaskPtr Function descriptor - * @param[in] StdHeader Config handle for library and services - * @param[in] ConfigParams AMD entry point's CPU parameter structure - * - */ -VOID -RunCodeOnAllSystemCore0sSingle ( - IN AP_TASK *TaskPtr, - IN AMD_CONFIG_PARAMS *StdHeader, - IN VOID *ConfigParams - ) -{ - ApUtilTaskOnExecutingCore (TaskPtr, StdHeader, ConfigParams); -} - - -/*---------------------------------------------------------------------------------------*/ -/** - * Single socket BSC call to determine the maximum number of steps that any single - * processor needs to execute. - * - * This function simply returns the number of steps that the BSC needs. - * - * @param[out] NumSystemSteps Maximum number of system steps required - * @param[in] StdHeader Config handle for library and services - * - */ -VOID -GetNumberOfSystemPmStepsPtrSingle ( - OUT UINT8 *NumSystemSteps, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - SYS_PM_TBL_STEP *Ignored; - CPU_SPECIFIC_SERVICES *FamilySpecificServices; - - GetCpuServicesOfCurrentCore ((const CPU_SPECIFIC_SERVICES **)&FamilySpecificServices, StdHeader); - FamilySpecificServices->GetSysPmTableStruct (FamilySpecificServices, (const VOID **)&Ignored, NumSystemSteps, StdHeader); -} - - -/*---------------------------------------------------------------------------------------*/ -/** - * Single socket call to determine the frequency that the northbridges must run. - * - * This function simply returns the executing core's NB frequency, and that all - * NB frequencies are equivalent. - * - * @param[in] NbPstate NB P-state number to check (0 = fastest) - * @param[in] PlatformConfig Platform profile/build option config structure. - * @param[out] SystemNbCofNumerator NB frequency numerator for the system in MHz - * @param[out] SystemNbCofDenominator NB frequency denominator for the system - * @param[out] SystemNbCofsMatch Whether or not all NB frequencies are equivalent - * @param[out] NbPstateIsEnabledOnAllCPUs Whether or not NbPstate is valid on all CPUs - * @param[in] StdHeader Config handle for library and services - * - * @retval TRUE At least one processor has NbPstate enabled. - * @retval FALSE NbPstate is disabled on all CPUs - * - */ -BOOLEAN -GetSystemNbCofSingle ( - IN UINT32 NbPstate, - IN PLATFORM_CONFIGURATION *PlatformConfig, - OUT UINT32 *SystemNbCofNumerator, - OUT UINT32 *SystemNbCofDenominator, - OUT BOOLEAN *SystemNbCofsMatch, - OUT BOOLEAN *NbPstateIsEnabledOnAllCPUs, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - UINT32 Ignored; - PCI_ADDR PciAddress; - CPU_SPECIFIC_SERVICES *FamilySpecificServices; - - PciAddress.AddressValue = MAKE_SBDFO (0, 0, 24, 0, 0); - *SystemNbCofsMatch = TRUE; - GetCpuServicesOfCurrentCore ((const CPU_SPECIFIC_SERVICES **)&FamilySpecificServices, StdHeader); - *NbPstateIsEnabledOnAllCPUs = FamilySpecificServices->GetNbPstateInfo (FamilySpecificServices, - PlatformConfig, - &PciAddress, - NbPstate, - SystemNbCofNumerator, - SystemNbCofDenominator, - &Ignored, - StdHeader); - return *NbPstateIsEnabledOnAllCPUs; -} - - -/*---------------------------------------------------------------------------------------*/ -/** - * Single socket call to determine if the BIOS is responsible for updating the - * northbridge operating frequency and voltage. - * - * This function simply returns whether or not the executing core needs NB COF - * VID programming. - * - * @param[in] StdHeader Config handle for library and services - * - * @retval TRUE BIOS needs to set up NB frequency and voltage - * @retval FALSE BIOS does not need to set up NB frequency and voltage - * - */ -BOOLEAN -GetSystemNbCofVidUpdateSingle ( - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - BOOLEAN Ignored; - PCI_ADDR PciAddress; - CPU_SPECIFIC_SERVICES *FamilySpecificServices; - - PciAddress.AddressValue = MAKE_SBDFO (0, 0, 24, 0, 0); - GetCpuServicesOfCurrentCore ((const CPU_SPECIFIC_SERVICES **)&FamilySpecificServices, StdHeader); - return (FamilySpecificServices->IsNbCofInitNeeded (FamilySpecificServices, &PciAddress, &Ignored, StdHeader)); -} - - -/*---------------------------------------------------------------------------------------*/ -/** - * Single socket call to determine the most severe AGESA_STATUS return value after - * processing the power management initialization tables. - * - * This function searches the event log for the most severe error and returns - * the status code. This function must be called by the BSC only. - * - * @param[in] StdHeader Config handle for library and services - * - * @return The most severe error code from power management init - * - */ -AGESA_STATUS -GetEarlyPmErrorsSingle ( - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - UINT16 i; - AGESA_EVENT EventLogEntry; - AGESA_STATUS ReturnCode; - - ASSERT (IsBsp (StdHeader, &ReturnCode)); - - ReturnCode = AGESA_SUCCESS; - for (i = 0; PeekEventLog (&EventLogEntry, i, StdHeader); i++) { - if ((EventLogEntry.EventInfo & CPU_EVENT_PM_EVENT_MASK) == CPU_EVENT_PM_EVENT_CLASS) { - if (EventLogEntry.EventClass > ReturnCode) { - ReturnCode = EventLogEntry.EventClass; - } - } - } - - return (ReturnCode); -} - -/** - * Single socket call to loop through all Nb Pstates, comparing the NB frequencies - * to determine the slowest in the system. This routine also returns the NB P0 frequency. - * - * @param[in] PlatformConfig Platform profile/build option config structure. - * @param[out] MinSysNbFreq NB frequency numerator for the system in MHz - * @param[out] MinP0NbFreq NB frequency numerator for P0 in MHz - * @param[in] StdHeader Config handle for library and services - */ -VOID -GetMinNbCofSingle ( - IN PLATFORM_CONFIGURATION *PlatformConfig, - OUT UINT32 *MinSysNbFreq, - OUT UINT32 *MinP0NbFreq, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - PCI_ADDR PciAddress; - CPU_SPECIFIC_SERVICES *FamilySpecificServices; - - PciAddress.AddressValue = MAKE_SBDFO (0, 0, 24, 0, 0); - GetCpuServicesOfCurrentCore ((const CPU_SPECIFIC_SERVICES **) &FamilySpecificServices, StdHeader); - FamilySpecificServices->GetMinMaxNbFrequency (FamilySpecificServices, - PlatformConfig, - &PciAddress, - MinSysNbFreq, - MinP0NbFreq, - StdHeader); -} \ No newline at end of file diff --git a/src/vendorcode/amd/agesa/f12/Proc/CPU/cpuPowerMgmtSingleSocket.h b/src/vendorcode/amd/agesa/f12/Proc/CPU/cpuPowerMgmtSingleSocket.h deleted file mode 100644 index 6dd4c817a3..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/CPU/cpuPowerMgmtSingleSocket.h +++ /dev/null @@ -1,113 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * AMD CPU Power Management Single Socket Functions. - * - * Contains code for doing power management for single socket CPU - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: CPU - * @e \$Revision: 48937 $ @e \$Date: 2011-03-15 03:37:15 +0800 (Tue, 15 Mar 2011) $ - * - */ -/* - ****************************************************************************** - * - * Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - ****************************************************************************** - */ - -#ifndef _CPU_POWER_MGMT_SINGLE_SOCKET_H_ -#define _CPU_POWER_MGMT_SINGLE_SOCKET_H_ - - -/*--------------------------------------------------------------------------------------- - * M I X E D (Definitions And Macros / Typedefs, Structures, Enums) - *--------------------------------------------------------------------------------------- - */ - - -/*--------------------------------------------------------------------------------------- - * D E F I N I T I O N S A N D M A C R O S - *--------------------------------------------------------------------------------------- - */ - - -/*--------------------------------------------------------------------------------------- - * T Y P E D E F S, S T R U C T U R E S, E N U M S - *--------------------------------------------------------------------------------------- - */ - - -/*--------------------------------------------------------------------------------------- - * F U N C T I O N P R O T O T Y P E - *--------------------------------------------------------------------------------------- - */ -VOID -RunCodeOnAllSystemCore0sSingle ( - IN AP_TASK *TaskPtr, - IN AMD_CONFIG_PARAMS *StdHeader, - IN VOID *ConfigParams - ); - -VOID -GetNumberOfSystemPmStepsPtrSingle ( - OUT UINT8 *NumSystemSteps, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -BOOLEAN -GetSystemNbCofSingle ( - IN UINT32 NbPstate, - IN PLATFORM_CONFIGURATION *PlatformConfig, - OUT UINT32 *SystemNbCofNumerator, - OUT UINT32 *SystemNbCofDenominator, - OUT BOOLEAN *SystemNbCofsMatch, - OUT BOOLEAN *NbPstateIsEnabledOnAllCPUs, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -BOOLEAN -GetSystemNbCofVidUpdateSingle ( - IN AMD_CONFIG_PARAMS *StdHeader - ); - -VOID -GetMinNbCofSingle ( - IN PLATFORM_CONFIGURATION *PlatformConfig, - OUT UINT32 *MinSysNbFreq, - OUT UINT32 *MinP0NbFreq, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -AGESA_STATUS -GetEarlyPmErrorsSingle ( - IN AMD_CONFIG_PARAMS *StdHeader - ); - -#endif // _CPU_POWER_MGMT_SINGLE_SOCKET_H_ diff --git a/src/vendorcode/amd/agesa/f12/Proc/CPU/cpuPowerMgmtSystemTables.h b/src/vendorcode/amd/agesa/f12/Proc/CPU/cpuPowerMgmtSystemTables.h deleted file mode 100644 index 0adb2794a3..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/CPU/cpuPowerMgmtSystemTables.h +++ /dev/null @@ -1,92 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * Power Management Table declarations. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: CPU - * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $ - * - */ -/* - ****************************************************************************** - * - * Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - ****************************************************************************** - */ - -#ifndef _CPU_POWER_MGMT_SYSTEM_TABLES_H_ -#define _CPU_POWER_MGMT_SYSTEM_TABLES_H_ - - -/*--------------------------------------------------------------------------------------- - * M I X E D (Definitions And Macros / Typedefs, Structures, Enums) - *--------------------------------------------------------------------------------------- - */ - - -/*--------------------------------------------------------------------------------------- - * D E F I N I T I O N S A N D M A C R O S - *--------------------------------------------------------------------------------------- - */ -#define PM_EXEFLAGS_WARM_ONLY 0x00000001 /* Skip step if set && cold reset */ -#define PM_EXEFLAGS_NOT_ON_S3 0x00000002 /* Skip step if S3 resume */ -#define PM_EXEFLAGS_SYSTEM_TASK 0x00000004 /* Future use */ -#define PM_EXEFLAGS_SERIAL_EXE 0x00000008 /* BSC will wait for remote core 0 to complete the step*/ - - -/*--------------------------------------------------------------------------------------- - * T Y P E D E F S, S T R U C T U R E S, E N U M S - *--------------------------------------------------------------------------------------- - */ -typedef VOID F_PM_STEP_FUNCTION ( - IN CPU_SPECIFIC_SERVICES *FamilySpecificServices, - IN AMD_CPU_EARLY_PARAMS *CpuEarlyParamsPtr, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -/// Reference to a Method. -typedef F_PM_STEP_FUNCTION *PF_PM_STEP_FUNCTION; - - -/// A structure representing a step in a power management -/// initialization process to be invoked at AmdInitEarly -typedef struct { - UINT32 ExeFlags; ///< Execution flags - PF_PM_STEP_FUNCTION FuncPtr; ///< Function pointer -} SYS_PM_TBL_STEP; - - -/*--------------------------------------------------------------------------------------- - * F U N C T I O N P R O T O T Y P E - *--------------------------------------------------------------------------------------- - */ - - -#endif // _CPU_POWER_MGMT_SYSTEM_TABLES_H_/ - diff --git a/src/vendorcode/amd/agesa/f12/Proc/CPU/cpuRegisters.h b/src/vendorcode/amd/agesa/f12/Proc/CPU/cpuRegisters.h deleted file mode 100644 index 941f4b6948..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/CPU/cpuRegisters.h +++ /dev/null @@ -1,388 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * AMD CPU Register Table Related Functions - * - * Contains the definition of the CPU CPUID MSRs and PCI registers with BKDG recommended values - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: CPU - * @e \$Revision: 45621 $ @e \$Date: 2011-01-19 16:12:16 +0800 (Wed, 19 Jan 2011) $ - * - */ -/* - ****************************************************************************** - * - * Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - ****************************************************************************** - */ - -#ifndef _CPU_REGISTERS_H_ -#define _CPU_REGISTERS_H_ - -#include "cpuFamRegisters.h" -/* - *-------------------------------------------------------------- - * - * M O D U L E S U S E D - * - *--------------------------------------------------------------- - */ - -/* - *-------------------------------------------------------------- - * - * D E F I N I T I O N S / M A C R O S - * - *--------------------------------------------------------------- - */ - -#define BIT0 0x0000000000000001ull -#define BIT1 0x0000000000000002ull -#define BIT2 0x0000000000000004ull -#define BIT3 0x0000000000000008ull -#define BIT4 0x0000000000000010ull -#define BIT5 0x0000000000000020ull -#define BIT6 0x0000000000000040ull -#define BIT7 0x0000000000000080ull -#define BIT8 0x0000000000000100ull -#define BIT9 0x0000000000000200ull -#define BIT10 0x0000000000000400ull -#define BIT11 0x0000000000000800ull -#define BIT12 0x0000000000001000ull -#define BIT13 0x0000000000002000ull -#define BIT14 0x0000000000004000ull -#define BIT15 0x0000000000008000ull -#define BIT16 0x0000000000010000ull -#define BIT17 0x0000000000020000ull -#define BIT18 0x0000000000040000ull -#define BIT19 0x0000000000080000ull -#define BIT20 0x0000000000100000ull -#define BIT21 0x0000000000200000ull -#define BIT22 0x0000000000400000ull -#define BIT23 0x0000000000800000ull -#define BIT24 0x0000000001000000ull -#define BIT25 0x0000000002000000ull -#define BIT26 0x0000000004000000ull -#define BIT27 0x0000000008000000ull -#define BIT28 0x0000000010000000ull -#define BIT29 0x0000000020000000ull -#define BIT30 0x0000000040000000ull -#define BIT31 0x0000000080000000ull -#define BIT32 0x0000000100000000ull -#define BIT33 0x0000000200000000ull -#define BIT34 0x0000000400000000ull -#define BIT35 0x0000000800000000ull -#define BIT36 0x0000001000000000ull -#define BIT37 0x0000002000000000ull -#define BIT38 0x0000004000000000ull -#define BIT39 0x0000008000000000ull -#define BIT40 0x0000010000000000ull -#define BIT41 0x0000020000000000ull -#define BIT42 0x0000040000000000ull -#define BIT43 0x0000080000000000ull -#define BIT44 0x0000100000000000ull -#define BIT45 0x0000200000000000ull -#define BIT46 0x0000400000000000ull -#define BIT47 0x0000800000000000ull -#define BIT48 0x0001000000000000ull -#define BIT49 0x0002000000000000ull -#define BIT50 0x0004000000000000ull -#define BIT51 0x0008000000000000ull -#define BIT52 0x0010000000000000ull -#define BIT53 0x0020000000000000ull -#define BIT54 0x0040000000000000ull -#define BIT55 0x0080000000000000ull -#define BIT56 0x0100000000000000ull -#define BIT57 0x0200000000000000ull -#define BIT58 0x0400000000000000ull -#define BIT59 0x0800000000000000ull -#define BIT60 0x1000000000000000ull -#define BIT61 0x2000000000000000ull -#define BIT62 0x4000000000000000ull -#define BIT63 0x8000000000000000ull - -/// CPUID related registers -#define AMD_CPUID_FMF 0x80000001 // Family Model Features information -#define AMD_CPUID_APICID_LPC_BID 0x00000001 // Local APIC ID, Logical Processor Count, Brand ID -#define AMD_CPUID_L2L3Cache_L2TLB 0x80000006 -#define AMD_CPUID_TLB_L1Cache 0x80000005 -#define AMD_CPUID_APM 0x80000007 -#define LOCAL_APIC_ID 24 -#define LOGICAL_PROCESSOR_COUNT 16 -#define AMD_CPUID_ASIZE_PCCOUNT 0x80000008 // Address Size, Physical Core Count - -/// CPU Logical ID Transfer -typedef struct { - UINT32 RawId; ///< RawID - UINT64 LogicalId; ///< LogicalID -} CPU_LOGICAL_ID_XLAT; - -/// Logical CPU ID Table -typedef struct { - IN UINT32 Elements; ///< Number of Elements - IN CPU_LOGICAL_ID_XLAT *LogicalIdTable; ///< CPU Logical ID Transfer table Pointer -} LOGICAL_ID_TABLE; - -// MSRs -// ------------------------ -#define MCG_CTL_P 0x00000100 // bit 8 for MCG_CTL_P under MSRR -#define MSR_MCG_CAP 0x00000179 -#define MSR_MC0_CTL 0x00000400 - -#define MSR_APIC_BAR 0x0000001B -#define MSR_PATCH_LEVEL 0x0000008B - -#define CPUID_LONG_MODE_ADDR 0x80000008 -#define AMD_CPUID_FMF 0x80000001 - -#define MSR_EXTENDED_FEATURE_EN 0xC0000080 -#define MSR_MC_MISC_LINK_THRESHOLD 0xC0000408 -#define MSR_MC_MISC_L3_THRESHOLD 0xC0000409 -#define MSR_PATCH_LOADER 0xC0010020 - -/// Patch Loader Register -typedef struct { - UINT64 PatchBase:32; ///< Linear address of patch header address block - UINT64 SBZ:32; ///< Should be zero -} PATCH_LOADER_MSR; - -#define MSR_SYS_CFG 0xC0010010 // SYSCFG - F15 Shared -#define MSR_TOM2 0xC001001D // TOP_MEM2 - F15 Shared -#define MSR_MC0_CTL_MASK 0xC0010044 // MC0 Control Mask -#define MSR_MC1_CTL_MASK 0xC0010045 // MC1 Control Mask -#define MSR_MC2_CTL_MASK 0xC0010046 // MC2 Control Mask -#define MSR_MC4_CTL_MASK 0xC0010048 // MC4 Control Mask - -#define MSR_CPUID_FEATS 0xC0011004 // CPUID Features -#define MSR_CPUID_EXT_FEATS 0xC0011005 // CPUID Extended Features -#define MSR_HWCR 0xC0010015 -#define MSR_NB_CFG 0xC001001F // NB Config -#define ENABLE_CF8_EXT_CFG 0x00004000 // [46] -#define INIT_APIC_CPUID_LO 0x00400000 // [54] -#define MSR_LS_CFG 0xC0011020 -#define MSR_IC_CFG 0xC0011021 // ICache Config - F15 Shared -#define MSR_DC_CFG 0xC0011022 -#define MSR_ME_CFG 0xC0011029 -#define MSR_BU_CFG 0xC0011023 -#define MSR_CU_CFG 0xC0011023 // F15 Shared -#define MSR_DE_CFG 0xC0011029 // F15 Shared -#define MSR_BU_CFG2 0xC001102A -#define MSR_CU_CFG2 0xC001102A // F15 Shared -#define MSR_BU_CFG3 0xC001102B -#define MSR_CU_CFG3 0xC001102B // F15 Shared -#define MSR_LS_CFG2 0xC001102D -#define MSR_IBS_OP_DATA3 0xC0011037 -#define MSR_C001_1070 0xC0011070 // F15 Shared - - -#define MSR_CPUID_NAME_STRING0 0xC0010030 // First CPUID namestring register -#define MSR_CPUID_NAME_STRING1 0xC0010031 -#define MSR_CPUID_NAME_STRING2 0XC0010032 -#define MSR_CPUID_NAME_STRING3 0xC0010033 -#define MSR_CPUID_NAME_STRING4 0xC0010034 -#define MSR_CPUID_NAME_STRING5 0xC0010035 // Last CPUID namestring register -#define MSR_MMIO_Cfg_Base 0xC0010058 // MMIO Configuration Base Address Register -#define MSR_BIST 0xC0010060 // BIST Results register -#define MSR_OSVW_ID_Length 0xC0010140 -#define MSR_OSVW_Status 0xC0010141 -#define MSR_PERF_CONTROL3 0xC0010003 // Perfromance control register number 3 -#define MSR_PERF_COUNTER3 0xC0010007 // Performance counter register number 3 -#define PERF_RESERVE_BIT_MASK 0x030FFFDFFFFF // Mask of the Performance control Reserve bits -#define PERF_CAR_CORRUPTION_EVENT 0x040040F0E2 // Configure the controller to capture the - // CAR Corruption -// FUNC_0 registers -// ---------------- -#define HT_LINK_FREQ_OFFSET 8 // Link HT Frequency from capability base -#define HT_LINK_CONTROL_REG_OFFSET 4 -#define HT_LINK_TYPE_REG_OFFSET 0x18 -#define HT_LINK_EXTENDED_FREQ 0x1C -#define HT_LINK_HOST_CAP_MAX 0x20 // HT Host Capability offsets are less than its size. -#define HT_CAPABILITIES_POINTER 0x34 -#define NODE_ID 0x60 -#define HT_INIT_CTRL 0x6C -#define HT_INIT_CTRL_REQ_DIS 0x02 // [1] = ReqDis -#define HT_INIT_COLD_RST_DET BIT4 -#define HT_INIT_BIOS_RST_DET_0 BIT5 -#define HT_INIT_BIOS_RST_DET_1 BIT9 -#define HT_INIT_BIOS_RST_DET_2 BIT10 -#define HT_INIT_BIOS_RST_DET BIT9 | BIT10 -#define HT_TRANS_CTRL 0x68 -#define HT_TRANS_CTRL_CPU1_EN 0x00000020 // [5] = CPU1 Enable -#define HT_LINK_CONTROL_0 0x84 -#define HT_LINK_FREQ_0 0x88 // Link HT Frequency -#define EXTENDED_NODE_ID 0x160 -#define ECS_HT_TRANS_CTRL 0x168 -#define ECS_HT_TRANS_CTRL_CPU2_EN 0x00000001 // [0] = CPU2 Enable -#define ECS_HT_TRANS_CTRL_CPU3_EN 0x00000002 // [1] = CPU3 Enable -#define ECS_HT_TRANS_CTRL_CPU4_EN 0x00000004 // [2] = CPU4 Enable -#define ECS_HT_TRANS_CTRL_CPU5_EN 0x00000008 // [3] = CPU5 Enable - -#define CORE_CTRL 0x1DC -#define CORE_CTRL_CORE1_EN 0x00000002 -#define CORE_CTRL_CORE2_EN 0x00000004 -#define CORE_CTRL_CORE3_EN 0x00000008 -#define CORE_CTRL_CORE4_EN 0x00000010 -#define CORE_CTRL_CORE5_EN 0x00000020 -#define CORE_CTRL_CORE6_EN 0x00000040 -#define CORE_CTRL_CORE7_EN 0x00000080 - -// FUNC_3 registers -// ---------------- -#define HARDWARE_THERMAL_CTRL_REG 0x64 -#define SOFTWARE_THERMAL_CTRL_REG 0x68 - -#define ACPI_PSC_0_REG 0x80 // ACPI Power State Control Registers -#define ACPI_PSC_4_REG 0x84 - -#define NB_CFG_HIGH_REG 0x8C -#define POWER_CTRL_MISCELLANEOUS_REG 0xA0 -#define CLOCK_POWER_TIMING_CTRL2_REG 0xDC -#define NORTH_BRIDGE_CAPABILITIES_REG 0xE8 -#define MULTI_NODE_CPU 29 -#define CPUID_FMR 0xFC // Family / Model registers -#define DOWNCORE_CTRL 0x190 // Downcore Control Register - -#define LINK_TO_XCS_TOKEN_COUNT_REG_3X148 0x148 -#define REG_HT4_PHY_OFFSET_BASE_4X180 0x180 -#define REG_HT4_PHY_DATA_PORT_BASE_4X184 0x184 - -#define HTPHY_OFFSET_MASK 0xE00001FF -#define HTPHY_WRITE_CMD 0x40000000 -#define HTPHY_IS_COMPLETE_MASK 0x80000000 -#define HTPHY_DIRECT_MAP 0x20000000 -#define HTPHY_DIRECT_OFFSET_MASK 0xE000FFFF - -// FUNC_5 registers -// ---------------- -#define COMPUTE_UNIT_STATUS 0x80 -#define NORTH_BRIDGE_CAPABILITIES_2_REG 0x84 - - -// Misc. defines. -#define PCI_DEV_BASE 24 - -#define CPU_STEPPING 0x0000000F -#define CPU_MODEL 0x000000F0 -#define CPU_EMODEL 0x000F0000 -#define CPU_EFAMILY 0x00F00000 -#define CPU_FMS_MASK CPU_EFAMILY | CPU_EMODEL | CPU_MODEL | CPU_STEPPING - -#define HTPHY_SELECT 2 -#define PCI_SELECT 1 -#define MSR_SELECT 0 - -#define LOGICAL_ID 1 -#define F_SCHEME 0 -#define DR_SCHEME 1 -#define GR_SCHEME 2 - -#define DR_NO_STRING 0 -#define DR_SOCKET_C32 5 -#define DR_SOCKET_ASB2 4 -#define DR_SOCKET_G34 3 -#define DR_SOCKET_S1G3 2 -#define DR_SOCKET_S1G4 2 -#define DR_SOCKET_AM3 1 -#define DR_SOCKET_1207 0 -#define LN_SOCKET_FM1 2 -#define LN_SOCKET_FS1 1 -#define LN_SOCKET_FP1 0 -#define ON_SOCKET_FT1 0 -#define OR_SOCKET_AM3 1 -#define OR_SOCKET_G34 3 -#define OR_SOCKET_C32 5 -#define SOCKET_IGNORE 0xF - -#define LAPIC_BASE_ADDR_MASK 0x0000FFFFFFFFF000ull -#define APIC_EXT_BRDCST_MASK 0x000E0000 -#define APIC_ENABLE_BIT 0x00000800 -#define LOCAL_APIC_ADDR 0xFEE00000 -#define INT_CMD_REG_LO 0x300 -#define INT_CMD_REG_HI 0x310 -#define REMOTE_MSG_REG 0x380 -#define REMOTE_READ_REG 0xC0 -#define APIC_ID_REG 0x20 -#define APIC20_ApicId 24 -#define CMD_REG_TO_READ_DATA 0x338 - -#define MAX_CORE_ID_SIZE 8 -#define MAX_CORE_ID_MASK ((1 << MAX_CORE_ID_SIZE) - 1) - -/*------------------------- - * Default definitions - *------------------------- - */ -#define DOWNCORE_MASK_SINGLE 0xFFFFFFFE -#define DOWNCORE_MASK_DUAL 0xFFFFFFFC -#define DOWNCORE_MASK_TRI 0xFFFFFFF8 -#define DOWNCORE_MASK_FOUR 0xFFFFFFF0 -#define DOWNCORE_MASK_FIVE 0xFFFFFFE0 -#define DOWNCORE_MASK_SIX 0xFFFFFFC0 -#define DOWNCORE_MASK_DUAL_COMPUTE_UNIT 0xFFFFFFFA -#define DOWNCORE_MASK_TRI_COMPUTE_UNIT 0xFFFFFFEA -#define DOWNCORE_MASK_FOUR_COMPUTE_UNIT 0xFFFFFFAA - -#define DELIVERY_STATUS BIT13 -#define REMOTE_READ_STAT_MASK 0x00030000 -#define REMOTE_DELIVERY_PENDING 0x00010000 -#define REMOTE_DELIVERY_DONE 0x00020000 - -/* - * -------------------------------------------------------------------------------------- - * - * D E F I N E S / T Y P E D E F S / S T R U C T U R E S - * - * -------------------------------------------------------------------------------------- - */ - -/// CpuEarly param type -typedef struct { - IN UINT8 MemInitPState; ///< Pstate value during memory initial - IN PLATFORM_CONFIGURATION PlatformConfig; ///< Runtime configurable user options -} AMD_CPU_EARLY_PARAMS; - -/// Enum - Will be used to access each structure -/// related to each CPU family -typedef enum { - REVF, ///< NPT, RevF - REVG, ///< NPT, RevG - DEERHOUND, ///< Family 10h, Deerhound - GRIFFIN ///< Family 11h, Griffin -} CPU_FAMILY; - -/// CPUID -typedef enum { - REG_EAX, ///< EAX - REG_EBX, ///< EBX - REG_ECX, ///< ECX - REG_EDX ///< EDX -} CPUID_REG; - -#endif // _CPU_REGISTERS_H_ - diff --git a/src/vendorcode/amd/agesa/f12/Proc/CPU/cpuServices.h b/src/vendorcode/amd/agesa/f12/Proc/CPU/cpuServices.h deleted file mode 100644 index 0d5302ee15..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/CPU/cpuServices.h +++ /dev/null @@ -1,354 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * AMD CPU Services - * - * Related to the General Services API's, but for the CPU component. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: CPU - * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $ - * - */ -/* - ****************************************************************************** - * - * Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - ****************************************************************************** - */ - -#ifndef _CPU_SERVICES_H_ -#define _CPU_SERVICES_H_ - -/*---------------------------------------------------------------------------------------- - * M I X E D (Definitions And Macros / Typedefs, Structures, Enums) - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------- - * D E F I N I T I O N S A N D M A C R O S - *---------------------------------------------------------------------------------------- - */ - /// WARM RESET STATE_BITS -#define WR_STATE_COLD 00 -#define WR_STATE_RESET 01 -#define WR_STATE_EARLY 02 -#define WR_STATE_POST 03 - -/*---------------------------------------------------------------------------------------- - * T Y P E D E F S, S T R U C T U R E S, E N U M S - *---------------------------------------------------------------------------------------- - */ - -/** - * The role of primary core for each compute unit can be relative to the cores' launch order. - * - * One core of a compute unit is always given the role as primary. In different feature algorithms - * the core performing the primary core role can be designated relative to compute order. In most cases, - * the primary core is the first core of a compute unit to execute. However, in some cases the primary core - * role is associated with the last core to execute. - * - * If the launch order is strictly ascending, then first core is the lowest number and last core is highest. - * But if the launch order is not ascending, the first and last core follow the launch order, not the numbering order. - * - * Note that for compute units with only one core (AllCoresMapping), that core is primary for both orderings. - * (This includes processors without hardware compute units.) - * - */ -typedef enum { - FirstCoreIsComputeUnitPrimary, ///< the primary core role associates with the first core. - LastCoreIsComputeUnitPrimary, ///< the primary core role associates with the last core. - MaxComputeUnitPrimarySelector, ///< limit check. -} COMPUTE_UNIT_PRIMARY_SELECTOR; - -/** - * The supported Core to Compute unit mappings. - */ -typedef enum { - AllCoresMapping, ///< All Cores are primary cores - EvenCoresMapping, ///< Compute units are even/odd core pairs. - BitMapMapping, ///< Currently not supported by any family, arbitrary core - ///< to compute unit mapping. - MaxComputeUnitMapping ///< Not a mapping, use for limit check. -} COMPUTE_UNIT_MAPPING; - -/** - * Core Pair Map entry. - * Provide for interpreting the core pairing for the processor's compute units. - * - * HT_LIST_TERMINAL as an Enabled value means the end of a list of map structs. - * Zero as an Enabled value implies Compute Units are not supported by the processor - * and the mapping is assumed to be AllCoresMapping. - * - */ -typedef struct { - UINT8 Enabled; ///< The value of the Enabled Compute Units - UINT8 DualCore; ///< The value of the Dual Core Compute Units - COMPUTE_UNIT_MAPPING Mapping; ///< When the processor module matches these values, use this mapping method. -} CORE_PAIR_MAP; - -//---------------------------------------------------------------------------- -// CPU SYSTEM INFO TYPEDEFS, STRUCTURES, ENUMS -// -//---------------------------------------------------------------------------- -/// SYSTEM INFO -typedef struct _SYSTEM_INFO { - UINT32 TotalNumberOfSockets; ///< Total Number of Sockets - UINT32 TotalNumberOfCores; ///< Total Number Of Cores - UINT32 CurrentSocketNum; ///< Current Socket Number - UINT32 CurrentCoreNum; ///< Current Core Number - UINT32 CurrentCoreApicId; ///< Current Core Apic ID - UINT32 CurrentLogicalCpuId; ///< Current Logical CPU ID -} SYSTEM_INFO; - -/// WARM_RESET_REQUEST -typedef struct _WARM_RESET_REQUEST { - UINT8 RequestBit:1; ///< Request Bit - UINT8 StateBits:2; ///< State Bits - UINT8 PostStage:2; ///< Post Stage - UINT8 Reserved:(8-5); ///< Reserved -} WARM_RESET_REQUEST; -/*---------------------------------------------------------------------------------------- - * F U N C T I O N P R O T O T Y P E - *---------------------------------------------------------------------------------------- - */ - -VOID -GetCurrentNodeNum ( - OUT UINT32 *Node, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -/** - * Get the current Platform's number of Sockets, regardless of how many are populated. - * - */ -UINT32 -GetPlatformNumberOfSockets (VOID); - -/** - * Get the number of Modules to check presence in each Processor. - * - */ -UINT32 -GetPlatformNumberOfModules (VOID); - -BOOLEAN -IsProcessorPresent ( - IN UINT32 Socket, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -/** - * For a specific Node, get its Socket and Module ids. - * - */ -BOOLEAN -GetSocketModuleOfNode ( - IN UINT32 Node, - OUT UINT32 *Socket, - OUT UINT32 *Module, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -/** - * Get the current core's Processor APIC Index. - */ -UINT32 -GetProcessorApicIndex ( - IN UINT32 Node, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -/** - * Initialize the Local APIC. - */ -VOID -LocalApicInitialization ( - IN AMD_CPU_EARLY_PARAMS *CpuEarlyParamsPtr, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -/** - * Writes to all nodes on the executing core's socket. - * - */ -VOID -ModifyCurrentSocketPci ( - IN PCI_ADDR *PciAddress, - IN UINT32 Mask, - IN UINT32 Data, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -/** - * Provide the number of installed processors (not Nodes! and not Sockets!) - */ -UINT32 -GetNumberOfProcessors ( - IN AMD_CONFIG_PARAMS *StdHeader - ); - -VOID -GetActiveCoresInCurrentSocket ( - OUT UINT32 *CoreCount, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -BOOLEAN -GetActiveCoresInGivenSocket ( - IN UINT32 Socket, - OUT UINT32 *CoreCount, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -UINTN -GetActiveCoresInCurrentModule ( - IN AMD_CONFIG_PARAMS *StdHeader - ); - -UINTN -GetNumberOfCompUnitsInCurrentModule ( - IN AMD_CONFIG_PARAMS *StdHeader - ); - -BOOLEAN -GetGivenModuleCoreRange ( - IN UINT32 Socket, - IN UINT32 Module, - OUT UINT32 *LowCore, - OUT UINT32 *HighCore, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -VOID -GetCurrentCore ( - OUT UINT32 *Core, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -VOID -GetCurrentNodeAndCore ( - OUT UINT32 *Node, - OUT UINT32 *Core, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -BOOLEAN -IsCurrentCorePrimary ( - IN AMD_CONFIG_PARAMS *StdHeader - ); - -VOID -GetApMailbox ( - OUT UINT32 *ApMailboxInfo, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -VOID -CacheApMailbox ( - IN AMD_CONFIG_PARAMS *StdHeader - ); - -UINTN -GetSystemDegree ( - IN AMD_CONFIG_PARAMS *StdHeader - ); - -BOOLEAN -GetNodeId ( - IN UINT32 SocketId, - IN UINT32 ModuleId, - OUT UINT8 *NodeId, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -VOID -WaitMicroseconds ( - IN UINT32 Microseconds, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -/** - * Get the compute unit mapping algorithm. - */ -COMPUTE_UNIT_MAPPING -GetComputeUnitMapping ( - IN AMD_CONFIG_PARAMS *StdHeader - ); - -/** - * Does the current core have the role of primary core for the compute unit? - */ -BOOLEAN -IsCorePairPrimary ( - IN COMPUTE_UNIT_PRIMARY_SELECTOR Selector, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -/** - * Are the two specified cores shared in a compute unit? - */ -BOOLEAN -AreCoresPaired ( - IN UINT32 Socket, - IN UINT32 Module, - IN UINT32 CoreA, - IN UINT32 CoreB, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -VOID -SetWarmResetFlag ( - IN AMD_CONFIG_PARAMS *StdHeader, - IN WARM_RESET_REQUEST *Request - ); - -VOID -GetWarmResetFlag ( - IN AMD_CONFIG_PARAMS *StdHeader, - OUT WARM_RESET_REQUEST *Request - ); - -BOOLEAN -IsWarmReset ( - IN AMD_CONFIG_PARAMS *StdHeader - ); - -AGESA_STATUS -CheckBistStatus ( - IN AMD_CONFIG_PARAMS *StdHeader - ); - -VOID -SetWarmResetAtEarly ( - IN UINT32 Data, - IN AMD_CONFIG_PARAMS *StdHeader -); - -#endif // _CPU_SERVICES_H_ diff --git a/src/vendorcode/amd/agesa/f12/Proc/CPU/cpuWarmReset.c b/src/vendorcode/amd/agesa/f12/Proc/CPU/cpuWarmReset.c deleted file mode 100644 index e812dc4c0e..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/CPU/cpuWarmReset.c +++ /dev/null @@ -1,235 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * AMD CPU Warm Reset Implementation. - * - * Implement Warm Reset Interface. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: CPU - * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $ - * - */ -/* - ****************************************************************************** - * - * Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - ****************************************************************************** - */ - -/*---------------------------------------------------------------------------------------- - * M O D U L E S U S E D - *---------------------------------------------------------------------------------------- - */ - -#include "AGESA.h" -#include "cpuRegisters.h" -#include "cpuServices.h" -#include "cpuFamilyTranslation.h" -#include "amdlib.h" -#include "Filecode.h" -CODE_GROUP (G1_PEICC) -RDATA_GROUP (G1_PEICC) - -#define FILECODE PROC_CPU_CPUWARMRESET_FILECODE -/*---------------------------------------------------------------------------------------- - * D E F I N I T I O N S A N D M A C R O S - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------- - * T Y P E D E F S A N D S T R U C T U R E S - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------- - * P R O T O T Y P E S O F L O C A L F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------- - * E X P O R T E D F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------*/ -/** - * This function will set the CPU register warm reset bits. - * - * Note: This function will be called by UEFI BIOS's - * The UEFI wrapper code should register this function, to be called back later point - * in time, before the wrapper code does warm reset. - * - * @param[in] StdHeader Config handle for library and services - * @param[in] Request Indicate warm reset status - * - *--------------------------------------------------------------------------------------- - **/ -VOID -SetWarmResetFlag ( - IN AMD_CONFIG_PARAMS *StdHeader, - IN WARM_RESET_REQUEST *Request - ) -{ - CPU_SPECIFIC_SERVICES *FamilySpecificServices; - FamilySpecificServices = NULL; - - GetCpuServicesOfCurrentCore ((const CPU_SPECIFIC_SERVICES **)&FamilySpecificServices, StdHeader); - FamilySpecificServices->SetWarmResetFlag (FamilySpecificServices, StdHeader, Request); -} - -/*---------------------------------------------------------------------------------------*/ -/** - * This function will get the CPU register warm reset bits. - * - * Note: This function will be called by UEFI BIOS's - * The UEFI wrapper code should register this function, to be called back later point - * in time, before the wrapper code does warm reset. - * - * @param[in] StdHeader Config handle for library and services - * @param[out] Request Indicate warm reset status - * - *--------------------------------------------------------------------------------------- - **/ -VOID -GetWarmResetFlag ( - IN AMD_CONFIG_PARAMS *StdHeader, - OUT WARM_RESET_REQUEST *Request - ) -{ - CPU_SPECIFIC_SERVICES *FamilySpecificServices; - FamilySpecificServices = NULL; - - GetCpuServicesOfCurrentCore ((const CPU_SPECIFIC_SERVICES **)&FamilySpecificServices, StdHeader); - FamilySpecificServices->GetWarmResetFlag (FamilySpecificServices, StdHeader, Request); - - switch (StdHeader->Func) { - case AMD_INIT_RESET: - Request->PostStage = (UINT8) WR_STATE_RESET; - break; - case AMD_INIT_EARLY: - Request->PostStage = (UINT8) WR_STATE_EARLY; - break; - case AMD_INIT_POST: - // Fall through to default case - default: - Request->PostStage = (UINT8) WR_STATE_POST; - break; - } -} -/*---------------------------------------------------------------------------------------- - * E X P O R T E D F U N C T I O N S - (AGESA ONLY) - *---------------------------------------------------------------------------------------- - */ - - - -/*---------------------------------------------------------------------------------------*/ -/** - * Is this boot a warm reset? - * - * This function reads the CPU register warm reset bit that is preserved after a warm reset. - * Which in fact gets set before issuing warm reset. We just use the BSP's register always. - * - * @param[in] StdHeader Config handle for library and services - * - * @retval TRUE Warm Reset - * @retval FALSE Not Warm Reset - * - */ -BOOLEAN -IsWarmReset ( - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - UINT8 PostStage; - WARM_RESET_REQUEST Request; - BOOLEAN WarmReset; - CPU_SPECIFIC_SERVICES *FamilySpecificServices; - - FamilySpecificServices = NULL; - - switch (StdHeader->Func) { - case AMD_INIT_RESET: - PostStage = WR_STATE_RESET; - break; - case AMD_INIT_EARLY: - PostStage = WR_STATE_EARLY; - break; - case AMD_INIT_POST: - default: - PostStage = WR_STATE_POST; - break; - } - - GetCpuServicesOfCurrentCore ((const CPU_SPECIFIC_SERVICES **)&FamilySpecificServices, StdHeader); - FamilySpecificServices->GetWarmResetFlag (FamilySpecificServices, StdHeader, &Request); - - if (Request.StateBits >= PostStage) { - WarmReset = TRUE; - } else { - WarmReset = FALSE; - } - - return WarmReset; -} - -/*---------------------------------------------------------------------------------------*/ -/** - * This function will set the CPU register warm reset bits at AmdInitEarly if it is - * currently in cold boot. To request for a warm reset, set the RequestBit to TRUE - * and the StateBits to (current poststage - 1) - * - * @param[in] Data The table data value (unused in this routine) - * @param[in] StdHeader Config handle for library and services - * - *--------------------------------------------------------------------------------------- - **/ -VOID -SetWarmResetAtEarly ( - IN UINT32 Data, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - WARM_RESET_REQUEST Request; - - if (!IsWarmReset (StdHeader)) { - GetWarmResetFlag (StdHeader, &Request); - - Request.RequestBit = TRUE; - Request.StateBits = (Request.PostStage - 1); - - SetWarmResetFlag (StdHeader, &Request); - } -} - -/*---------------------------------------------------------------------------------------- - * L O C A L F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ - diff --git a/src/vendorcode/amd/agesa/f12/Proc/CPU/heapManager.c b/src/vendorcode/amd/agesa/f12/Proc/CPU/heapManager.c deleted file mode 100644 index e9e41cbb7e..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/CPU/heapManager.c +++ /dev/null @@ -1,871 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * AMD Heap Manager and Heap Allocation APIs, and related functions. - * - * Contains code that initialize, maintain, and allocate the heap space. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: CPU - * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $ - * - */ -/******************************************************************************* - * - * Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - ****************************************************************************** - */ - -/*---------------------------------------------------------------------------------------- - * M O D U L E S U S E D - *---------------------------------------------------------------------------------------- - */ - -#include "AGESA.h" -#include "amdlib.h" -#include "Ids.h" -#include "cpuRegisters.h" -#include "cpuServices.h" -#include "GeneralServices.h" -#include "heapManager.h" -#include "cpuCacheInit.h" -#include "cpuFamilyTranslation.h" -#include "Filecode.h" -CODE_GROUP (G1_PEICC) -RDATA_GROUP (G1_PEICC) - -#define FILECODE PROC_CPU_HEAPMANAGER_FILECODE -/*---------------------------------------------------------------------------------------- - * D E F I N I T I O N S A N D M A C R O S - *---------------------------------------------------------------------------------------- - */ - - -/*---------------------------------------------------------------------------------------- - * T Y P E D E F S A N D S T R U C T U R E S - *---------------------------------------------------------------------------------------- - */ - - -/*---------------------------------------------------------------------------------------- - * P R O T O T Y P E S O F L O C A L F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ -UINT64 -STATIC -HeapGetCurrentBase ( - IN AMD_CONFIG_PARAMS *StdHeader - ); - -VOID -STATIC -DeleteFreeSpaceNode ( - IN AMD_CONFIG_PARAMS *StdHeader, - IN UINT32 OffsetOfDeletedNode - ); - -VOID -STATIC -InsertFreeSpaceNode ( - IN AMD_CONFIG_PARAMS *StdHeader, - IN UINT32 OffsetOfInsertNode - ); - -/*---------------------------------------------------------------------------------------- - * P U B L I C F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------- - * E X P O R T E D F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ -extern BUILD_OPT_CFG UserOptions; - -/*---------------------------------------------------------------------------------------*/ -/** - * This function initializes the heap for each CPU core. - * - * Check for already initialized. If not, determine offset of local heap in CAS and - * setup initial heap markers and bookkeeping status. Initialize a couple heap items - * all cores need, for convenience. Currently these are caching the AP mailbox info and - * an initial event log. - * - * @param[in] StdHeader Handle of Header for calling lib functions and services. - * - * @retval AGESA_SUCCESS This core's heap is initialized - * @retval AGESA_FATAL This core's heap cannot be initialized due to any reasons below: - * - current processor family cannot be identified. - * - */ -AGESA_STATUS -HeapManagerInit ( - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - // First Time Initialization - // Note: First 16 bytes of buffer is reserved for Heap Manager use - UINT16 HeapAlreadyInitSizeDword; - UINT32 HeapAlreadyRead; - UINT8 L2LineSize; - UINT8 *HeapBufferPtr; - UINT8 *HeapInitPtr; - UINT32 *HeapDataPtr; - UINT64 MsrData; - UINT64 MsrMask; - UINT8 Ignored; - CPUID_DATA CpuId; - BUFFER_NODE *FreeSpaceNode; - CACHE_INFO *CacheInfoPtr; - AGESA_STATUS IgnoredSts; - CPU_SPECIFIC_SERVICES *FamilySpecificServices; - CPU_LOGICAL_ID CpuFamilyRevision; - - // Check whether this is a known processor family. - GetLogicalIdOfCurrentCore (&CpuFamilyRevision, StdHeader); - if ((CpuFamilyRevision.Family == 0) && (CpuFamilyRevision.Revision == 0)) { - IDS_ERROR_TRAP; - return AGESA_FATAL; - } - - GetCpuServicesOfCurrentCore ((const CPU_SPECIFIC_SERVICES **)&FamilySpecificServices, StdHeader); - FamilySpecificServices->GetCacheInfo (FamilySpecificServices, (const VOID **)&CacheInfoPtr, &Ignored, StdHeader); - HeapBufferPtr = (UINT8 *) (intptr_t) StdHeader->HeapBasePtr; - - // Check whether the heap manager is already initialized - LibAmdMsrRead (AMD_MTRR_VARIABLE_HEAP_MASK, &MsrData, StdHeader); - if (MsrData == (CacheInfoPtr->VariableMtrrMask & (UINT64) AMD_HEAP_MTRR_MASK)) { - LibAmdMsrRead (AMD_MTRR_VARIABLE_HEAP_BASE, &MsrData, StdHeader); - if ((MsrData & CacheInfoPtr->HeapBaseMask) == ((UINT64) (intptr_t) HeapBufferPtr & CacheInfoPtr->HeapBaseMask)) { - if (((HEAP_MANAGER *) HeapBufferPtr)->Signature == HEAP_SIGNATURE_VALID) { - // This is not a bug, there are multiple premem basic entry points, - // and each will call heap init to make sure create struct will succeed. - // If that is later deemed a problem, there needs to be a reasonable test - // for the calling code to make to determine if it needs to init heap or not. - // In the mean time, add this to the event log - PutEventLog (AGESA_SUCCESS, - CPU_ERROR_HEAP_IS_ALREADY_INITIALIZED, - 0, 0, 0, 0, StdHeader); - return AGESA_SUCCESS; - } - } - } - - // Set variable MTRR base and mask - MsrData = ((UINT64) (intptr_t) HeapBufferPtr & CacheInfoPtr->HeapBaseMask); - MsrMask = CacheInfoPtr->VariableMtrrHeapMask & (UINT64) AMD_HEAP_MTRR_MASK; - - MsrData |= 0x06; - LibAmdMsrWrite (AMD_MTRR_VARIABLE_HEAP_BASE, &MsrData, StdHeader); - LibAmdMsrWrite (AMD_MTRR_VARIABLE_HEAP_MASK, &MsrMask, StdHeader); - - // Set top of memory to a temp value - MsrData = (UINT64) (AMD_TEMP_TOM); - LibAmdMsrWrite (TOP_MEM, &MsrData, StdHeader); - - // Enable variable MTRRs - LibAmdMsrRead (SYS_CFG, &MsrData, StdHeader); - MsrData |= AMD_VAR_MTRR_ENABLE_BIT; - LibAmdMsrWrite (SYS_CFG, &MsrData, StdHeader); - - // Initialize Heap Space - // BIOS may store to a line only after it has been allocated by a load - LibAmdCpuidRead (AMD_CPUID_L2L3Cache_L2TLB, &CpuId, StdHeader); - L2LineSize = (UINT8) (CpuId.ECX_Reg); - HeapInitPtr = HeapBufferPtr ; - for (HeapAlreadyRead = 0; HeapAlreadyRead < AMD_HEAP_SIZE_PER_CORE; - (HeapAlreadyRead = HeapAlreadyRead + L2LineSize)) { - Ignored = *HeapInitPtr; - HeapInitPtr += L2LineSize; - } - - HeapDataPtr = (UINT32 *) HeapBufferPtr; - for (HeapAlreadyInitSizeDword = 0; HeapAlreadyInitSizeDword < AMD_HEAP_SIZE_DWORD_PER_CORE; HeapAlreadyInitSizeDword++) { - *HeapDataPtr = 0; - HeapDataPtr++; - } - - // Note: We are reserving the first 16 bytes for Heap Manager use - // UsedSize indicates the size of heap spaced is used for HEAP_MANAGER, BUFFER_NODE, - // Pad for 16-byte alignment, buffer data, and IDS SENTINEL. - // FirstActiveBufferOffset is initalized as invalid heap offset, AMD_HEAP_INVALID_HEAP_OFFSET. - // FirstFreeSpaceOffset is initalized as the byte right after HEAP_MANAGER header. - // Then we set Signature of HEAP_MANAGER header as valid, HEAP_SIGNATURE_VALID. - ((HEAP_MANAGER*) HeapBufferPtr)->UsedSize = sizeof (HEAP_MANAGER); - ((HEAP_MANAGER*) HeapBufferPtr)->FirstActiveBufferOffset = AMD_HEAP_INVALID_HEAP_OFFSET; - ((HEAP_MANAGER*) HeapBufferPtr)->FirstFreeSpaceOffset = sizeof (HEAP_MANAGER); - ((HEAP_MANAGER*) HeapBufferPtr)->Signature = HEAP_SIGNATURE_VALID; - // Create free space link - FreeSpaceNode = (BUFFER_NODE *) (HeapBufferPtr + sizeof (HEAP_MANAGER)); - FreeSpaceNode->BufferSize = AMD_HEAP_SIZE_PER_CORE - sizeof (HEAP_MANAGER) - sizeof (BUFFER_NODE); - FreeSpaceNode->OffsetOfNextNode = AMD_HEAP_INVALID_HEAP_OFFSET; - - StdHeader->HeapStatus = HEAP_LOCAL_CACHE; - if (!IsBsp (StdHeader, &IgnoredSts)) { - // The BSP's hardware mailbox has not been initialized, so only APs - // can do this at this point. - CacheApMailbox (StdHeader); - } - EventLogInitialization (StdHeader); - return AGESA_SUCCESS; -} - - -/*---------------------------------------------------------------------------------------*/ -/** - * Allocates space for a new buffer in the heap - * - * This function will allocate new buffer either by using internal 'AGESA' heapmanager - * or by using externa (IBV) heapmanager. This function will also determine if whether or not - * there is enough space for the new structure. If so, it will zero out the buffer, - * and return a pointer to the region. - * - * @param[in,out] AllocateHeapParams structure pointer containing the size of the - * desired new region, its handle, and the - * return pointer. - * @param[in,out] StdHeader Config handle for library and services. - * - * @retval AGESA_SUCCESS No error - * @retval AGESA_BOUNDS_CHK Handle already exists, or not enough - * free space - * @retval AGESA_ERROR Heap is invaild - * - */ -AGESA_STATUS -HeapAllocateBuffer ( - IN OUT ALLOCATE_HEAP_PARAMS *AllocateHeapParams, - IN OUT AMD_CONFIG_PARAMS *StdHeader - ) -{ - UINT8 *BaseAddress; - UINT8 AlignTo16Byte; - UINT32 RemainSize; - UINT32 OffsetOfSplitNode; - UINT32 OffsetOfNode; - HEAP_MANAGER *HeapManager; - BUFFER_NODE *FreeSpaceNode; - BUFFER_NODE *SplitFreeSpaceNode; - BUFFER_NODE *CurrentBufferNode; - BUFFER_NODE *NewBufferNode; - AGESA_BUFFER_PARAMS AgesaBuffer; - - ASSERT (StdHeader != NULL); - - // At this stage we will decide to either use external (IBV) heap manger - // or internal (AGESA) heap manager. - - // If (HeapStatus == HEAP_SYSTEM_MEM), then use the call function to call - // external heap manager - if (StdHeader->HeapStatus == HEAP_SYSTEM_MEM) { - AgesaBuffer.StdHeader = *StdHeader; - AgesaBuffer.BufferHandle = AllocateHeapParams->BufferHandle; - AgesaBuffer.BufferLength = AllocateHeapParams->RequestedBufferSize; - - AGESA_TESTPOINT (TpIfBeforeAllocateHeapBuffer, StdHeader); - if (AgesaAllocateBuffer (0, &AgesaBuffer) != AGESA_SUCCESS) { - AllocateHeapParams->BufferPtr = NULL; - return AGESA_ERROR; - } - AGESA_TESTPOINT (TpIfAfterAllocateHeapBuffer, StdHeader); - - AllocateHeapParams->BufferPtr = (UINT8 *) (AgesaBuffer.BufferPointer); - return AGESA_SUCCESS; - } - - // If (StdHeader->HeapStatus != HEAP_SYSTEM_MEM), then allocated buffer - // using following AGESA Heap Manager code. - - // Buffer pointer is NULL unless we return a buffer. - AlignTo16Byte = 0; - AllocateHeapParams->BufferPtr = NULL; - AllocateHeapParams->RequestedBufferSize += NUM_OF_SENTINEL * SIZE_OF_SENTINEL; - - // Get base address - BaseAddress = (UINT8 *) (intptr_t) StdHeader->HeapBasePtr; - HeapManager = (HEAP_MANAGER *) BaseAddress; - - // Check Heap database is valid - if ((BaseAddress == NULL) || (HeapManager->Signature != HEAP_SIGNATURE_VALID)) { - // The base address in StdHeader is incorrect, get base address by itself - BaseAddress = (UINT8 *) (intptr_t) HeapGetBaseAddress (StdHeader); - HeapManager = (HEAP_MANAGER *) BaseAddress; - if ((BaseAddress == NULL) || (HeapManager->Signature != HEAP_SIGNATURE_VALID)) { - // Heap is not available, ASSERT here - ASSERT (FALSE); - return AGESA_ERROR; - } - StdHeader->HeapBasePtr = (UINT64) (intptr_t) BaseAddress; - } - - // Allocate - CurrentBufferNode = (BUFFER_NODE *) (BaseAddress + sizeof (HEAP_MANAGER)); - // If there already has been a heap with the incoming BufferHandle, we return AGESA_BOUNDS_CHK. - if (HeapManager->FirstActiveBufferOffset != AMD_HEAP_INVALID_HEAP_OFFSET) { - CurrentBufferNode = (BUFFER_NODE *) (BaseAddress + HeapManager->FirstActiveBufferOffset); - while (CurrentBufferNode->OffsetOfNextNode != AMD_HEAP_INVALID_HEAP_OFFSET) { - if (CurrentBufferNode->BufferHandle == AllocateHeapParams->BufferHandle) { - PutEventLog (AGESA_BOUNDS_CHK, - CPU_ERROR_HEAP_BUFFER_HANDLE_IS_ALREADY_USED, - AllocateHeapParams->BufferHandle, 0, 0, 0, StdHeader); - return AGESA_BOUNDS_CHK; - } else { - CurrentBufferNode = (BUFFER_NODE *) (BaseAddress + CurrentBufferNode->OffsetOfNextNode); - } - } - if (CurrentBufferNode->BufferHandle == AllocateHeapParams->BufferHandle) { - PutEventLog (AGESA_BOUNDS_CHK, - CPU_ERROR_HEAP_BUFFER_HANDLE_IS_ALREADY_USED, - AllocateHeapParams->BufferHandle, 0, 0, 0, StdHeader); - return AGESA_BOUNDS_CHK; - } - } - - // Find the buffer size that first matches the requested buffer size (i.e. the first free buffer of greater size). - OffsetOfNode = HeapManager->FirstFreeSpaceOffset; - FreeSpaceNode = (BUFFER_NODE *) (BaseAddress + OffsetOfNode); - while (OffsetOfNode != AMD_HEAP_INVALID_HEAP_OFFSET) { - AlignTo16Byte = (UINT8) ((0x10 - (((UINTN) (VOID *) FreeSpaceNode + sizeof (BUFFER_NODE) + SIZE_OF_SENTINEL) & 0xF)) & 0xF); - AllocateHeapParams->RequestedBufferSize = (UINT32) (AllocateHeapParams->RequestedBufferSize + AlignTo16Byte); - if (FreeSpaceNode->BufferSize >= AllocateHeapParams->RequestedBufferSize) { - break; - } - AllocateHeapParams->RequestedBufferSize = (UINT32) (AllocateHeapParams->RequestedBufferSize - AlignTo16Byte); - OffsetOfNode = FreeSpaceNode->OffsetOfNextNode; - FreeSpaceNode = (BUFFER_NODE *) (BaseAddress + OffsetOfNode); - } - if (OffsetOfNode == AMD_HEAP_INVALID_HEAP_OFFSET) { - // We don't find any free space buffer that matches the requested buffer size. - PutEventLog (AGESA_BOUNDS_CHK, - CPU_ERROR_HEAP_IS_FULL, - AllocateHeapParams->BufferHandle, 0, 0, 0, StdHeader); - return AGESA_BOUNDS_CHK; - } else { - // We find one matched free space buffer. - DeleteFreeSpaceNode (StdHeader, OffsetOfNode); - NewBufferNode = FreeSpaceNode; - // Add new buffer node to the buffer chain - if (HeapManager->FirstActiveBufferOffset == AMD_HEAP_INVALID_HEAP_OFFSET) { - HeapManager->FirstActiveBufferOffset = sizeof (HEAP_MANAGER); - } else { - CurrentBufferNode->OffsetOfNextNode = OffsetOfNode; - } - // New buffer size - RemainSize = FreeSpaceNode->BufferSize - AllocateHeapParams->RequestedBufferSize; - if (RemainSize > sizeof (BUFFER_NODE)) { - NewBufferNode->BufferSize = AllocateHeapParams->RequestedBufferSize; - OffsetOfSplitNode = OffsetOfNode + sizeof (BUFFER_NODE) + NewBufferNode->BufferSize; - SplitFreeSpaceNode = (BUFFER_NODE *) (BaseAddress + OffsetOfSplitNode); - SplitFreeSpaceNode->BufferSize = RemainSize - sizeof (BUFFER_NODE); - InsertFreeSpaceNode (StdHeader, OffsetOfSplitNode); - } else { - // Remain size is less than BUFFER_NODE, we use whole size instead of requested size. - NewBufferNode->BufferSize = FreeSpaceNode->BufferSize; - } - } - - // Initialize BUFFER_NODE structure of NewBufferNode - NewBufferNode->BufferHandle = AllocateHeapParams->BufferHandle; - if ((AllocateHeapParams->Persist == HEAP_TEMP_MEM) || (AllocateHeapParams->Persist == HEAP_SYSTEM_MEM)) { - NewBufferNode->Persist = AllocateHeapParams->Persist; - } else { - NewBufferNode->Persist = HEAP_LOCAL_CACHE; - } - NewBufferNode->OffsetOfNextNode = AMD_HEAP_INVALID_HEAP_OFFSET; - NewBufferNode->PadSize = AlignTo16Byte; - - // Clear to 0x00 - LibAmdMemFill ((VOID *) ((UINT8 *) NewBufferNode + sizeof (BUFFER_NODE)), 0x00, NewBufferNode->BufferSize, StdHeader); - - // Debug feature - SET_SENTINEL_BEFORE (NewBufferNode, AlignTo16Byte); - SET_SENTINEL_AFTER (NewBufferNode); - - // Update global variables - HeapManager->UsedSize += NewBufferNode->BufferSize + sizeof (BUFFER_NODE); - - // Now fill in the incoming structure - AllocateHeapParams->BufferPtr = (UINT8 *) ((UINT8 *) NewBufferNode + sizeof (BUFFER_NODE) + SIZE_OF_SENTINEL + AlignTo16Byte); - AllocateHeapParams->RequestedBufferSize -= (NUM_OF_SENTINEL * SIZE_OF_SENTINEL + AlignTo16Byte); - - return AGESA_SUCCESS; -} - - -/*---------------------------------------------------------------------------------------*/ -/** - * Deallocates a previously allocated buffer in the heap - * - * This function will deallocate buffer either by using internal 'AGESA' heapmanager - * or by using externa (IBV) heapmanager. - * - * @param[in] BufferHandle Handle of the buffer to free. - * @param[in] StdHeader Config handle for library and services. - * - * @retval AGESA_SUCCESS No error - * @retval AGESA_BOUNDS_CHK Handle does not exist on the heap - * - */ -AGESA_STATUS -HeapDeallocateBuffer ( - IN UINT32 BufferHandle, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - UINT8 *BaseAddress; - UINT32 NodeSize; - UINT32 OffsetOfFreeSpaceNode; - UINT32 OffsetOfPreviousNode; - UINT32 OffsetOfCurrentNode; - BOOLEAN HeapLocateFlag; - HEAP_MANAGER *HeapManager; - BUFFER_NODE *CurrentNode; - BUFFER_NODE *PreviousNode; - BUFFER_NODE *FreeSpaceNode; - AGESA_BUFFER_PARAMS AgesaBuffer; - - ASSERT (StdHeader != NULL); - - HeapLocateFlag = TRUE; - BaseAddress = (UINT8 *) (intptr_t) StdHeader->HeapBasePtr; - HeapManager = (HEAP_MANAGER *) BaseAddress; - - // Check Heap database is valid - if ((BaseAddress == NULL) || (HeapManager->Signature != HEAP_SIGNATURE_VALID)) { - // The base address in StdHeader is incorrect, get base address by itself - BaseAddress = (UINT8 *) (intptr_t) HeapGetBaseAddress (StdHeader); - HeapManager = (HEAP_MANAGER *) BaseAddress; - if ((BaseAddress == NULL) || (HeapManager->Signature != HEAP_SIGNATURE_VALID)) { - // Heap is not available, ASSERT here - ASSERT (FALSE); - return AGESA_ERROR; - } - StdHeader->HeapBasePtr = (UINT64) (intptr_t) BaseAddress; - } - - OffsetOfPreviousNode = AMD_HEAP_INVALID_HEAP_OFFSET; - OffsetOfCurrentNode = HeapManager->FirstActiveBufferOffset; - CurrentNode = (BUFFER_NODE *) (BaseAddress + OffsetOfCurrentNode); - - // Locate heap - if ((BaseAddress != NULL) && (HeapManager->Signature == HEAP_SIGNATURE_VALID)) { - if (OffsetOfCurrentNode == AMD_HEAP_INVALID_HEAP_OFFSET) { - HeapLocateFlag = FALSE; - } else { - while (CurrentNode->BufferHandle != BufferHandle) { - if (CurrentNode->OffsetOfNextNode == AMD_HEAP_INVALID_HEAP_OFFSET) { - HeapLocateFlag = FALSE; - break; - } else { - OffsetOfPreviousNode = OffsetOfCurrentNode; - OffsetOfCurrentNode = CurrentNode->OffsetOfNextNode; - CurrentNode = (BUFFER_NODE *) (BaseAddress + OffsetOfCurrentNode); - } - } - } - } else { - HeapLocateFlag = FALSE; - } - - if (HeapLocateFlag == TRUE) { - // CurrentNode points to the buffer which wanted to be deallocated. - // Remove deallocated heap from active buffer chain. - if (OffsetOfPreviousNode == AMD_HEAP_INVALID_HEAP_OFFSET) { - HeapManager->FirstActiveBufferOffset = CurrentNode->OffsetOfNextNode; - } else { - PreviousNode = (BUFFER_NODE *) (BaseAddress + OffsetOfPreviousNode); - PreviousNode->OffsetOfNextNode = CurrentNode->OffsetOfNextNode; - } - // Now, CurrentNode become a free space node. - HeapManager->UsedSize -= CurrentNode->BufferSize + sizeof (BUFFER_NODE); - // Loop free space chain to see if any free space node is just before/after CurrentNode, then merge them. - OffsetOfFreeSpaceNode = HeapManager->FirstFreeSpaceOffset; - FreeSpaceNode = (BUFFER_NODE *) (BaseAddress + OffsetOfFreeSpaceNode); - while (OffsetOfFreeSpaceNode != AMD_HEAP_INVALID_HEAP_OFFSET) { - if ((OffsetOfFreeSpaceNode + sizeof (BUFFER_NODE) + FreeSpaceNode->BufferSize) == OffsetOfCurrentNode) { - DeleteFreeSpaceNode (StdHeader, OffsetOfFreeSpaceNode); - NodeSize = FreeSpaceNode->BufferSize + CurrentNode->BufferSize + sizeof (BUFFER_NODE); - OffsetOfCurrentNode = OffsetOfFreeSpaceNode; - CurrentNode = FreeSpaceNode; - CurrentNode->BufferSize = NodeSize; - } else if (OffsetOfFreeSpaceNode == (OffsetOfCurrentNode + sizeof (BUFFER_NODE) + CurrentNode->BufferSize)) { - DeleteFreeSpaceNode (StdHeader, OffsetOfFreeSpaceNode); - NodeSize = FreeSpaceNode->BufferSize + CurrentNode->BufferSize + sizeof (BUFFER_NODE); - CurrentNode->BufferSize = NodeSize; - } - OffsetOfFreeSpaceNode = FreeSpaceNode->OffsetOfNextNode; - FreeSpaceNode = (BUFFER_NODE *) (BaseAddress + OffsetOfFreeSpaceNode); - } - InsertFreeSpaceNode (StdHeader, OffsetOfCurrentNode); - return AGESA_SUCCESS; - } else { - // If HeapStatus == HEAP_SYSTEM_MEM, try callout function - if (StdHeader->HeapStatus == HEAP_SYSTEM_MEM) { - AgesaBuffer.StdHeader = *StdHeader; - AgesaBuffer.BufferHandle = BufferHandle; - - AGESA_TESTPOINT (TpIfBeforeDeallocateHeapBuffer, StdHeader); - if (AgesaDeallocateBuffer (0, &AgesaBuffer) != AGESA_SUCCESS) { - return AGESA_ERROR; - } - AGESA_TESTPOINT (TpIfAfterDeallocateHeapBuffer, StdHeader); - - return AGESA_SUCCESS; - } - // If we are still unable to locate the buffer handle, return AGESA_BOUNDS_CHK - if ((BaseAddress != NULL) && (HeapManager->Signature == HEAP_SIGNATURE_VALID)) { - PutEventLog (AGESA_BOUNDS_CHK, - CPU_ERROR_HEAP_BUFFER_HANDLE_IS_NOT_PRESENT, - BufferHandle, 0, 0, 0, StdHeader); - } else { - ASSERT (FALSE); - } - return AGESA_BOUNDS_CHK; - } -} - -/*---------------------------------------------------------------------------------------*/ -/** - * Locates a previously allocated buffer on the heap. - * - * This function searches the heap for a buffer with the desired handle, and - * returns a pointer to the buffer. - * - * @param[in,out] LocateHeap Structure containing the buffer's handle, - * and the return pointer. - * @param[in] StdHeader Config handle for library and services. - * - * @retval AGESA_SUCCESS No error - * @retval AGESA_BOUNDS_CHK Handle does not exist on the heap - * - */ -AGESA_STATUS -HeapLocateBuffer ( - IN OUT LOCATE_HEAP_PTR *LocateHeap, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - UINT8 *BaseAddress; - UINT8 AlignTo16Byte; - UINT32 OffsetOfCurrentNode; - BOOLEAN HeapLocateFlag; - HEAP_MANAGER *HeapManager; - BUFFER_NODE *CurrentNode; - AGESA_BUFFER_PARAMS AgesaBuffer; - - ASSERT (StdHeader != NULL); - - HeapLocateFlag = TRUE; - BaseAddress = (UINT8 *) (intptr_t) StdHeader->HeapBasePtr; - HeapManager = (HEAP_MANAGER *) BaseAddress; - - // Check Heap database is valid - if ((BaseAddress == NULL) || (HeapManager->Signature != HEAP_SIGNATURE_VALID)) { - // The base address in StdHeader is incorrect, get base address by itself - BaseAddress = (UINT8 *) (intptr_t) HeapGetBaseAddress (StdHeader); - HeapManager = (HEAP_MANAGER *) BaseAddress; - if ((BaseAddress == NULL) || (HeapManager->Signature != HEAP_SIGNATURE_VALID)) { - // Heap is not available, ASSERT here - ASSERT (FALSE); - return AGESA_ERROR; - } - StdHeader->HeapBasePtr = (UINT64) (intptr_t) BaseAddress; - } - OffsetOfCurrentNode = HeapManager->FirstActiveBufferOffset; - CurrentNode = (BUFFER_NODE *) (BaseAddress + OffsetOfCurrentNode); - - // Find buffer using internal heap manager - // Locate the heap using handle = LocateHeap-> BufferHandle - // If HeapStatus != HEAP_SYSTEM_ MEM - if ((BaseAddress != NULL) && (HeapManager->Signature == HEAP_SIGNATURE_VALID)) { - if (OffsetOfCurrentNode == AMD_HEAP_INVALID_HEAP_OFFSET) { - HeapLocateFlag = FALSE; - } else { - while (CurrentNode->BufferHandle != LocateHeap->BufferHandle) { - if (CurrentNode->OffsetOfNextNode == AMD_HEAP_INVALID_HEAP_OFFSET) { - HeapLocateFlag = FALSE; - break; - } else { - OffsetOfCurrentNode = CurrentNode->OffsetOfNextNode; - CurrentNode = (BUFFER_NODE *) (BaseAddress + OffsetOfCurrentNode); - } - } - } - } else { - HeapLocateFlag = FALSE; - } - - if (HeapLocateFlag) { - AlignTo16Byte = CurrentNode->PadSize; - LocateHeap->BufferPtr = (UINT8 *) ((UINT8 *) CurrentNode + sizeof (BUFFER_NODE) + SIZE_OF_SENTINEL + AlignTo16Byte); - LocateHeap->BufferSize = CurrentNode->BufferSize - NUM_OF_SENTINEL * SIZE_OF_SENTINEL - AlignTo16Byte; - return AGESA_SUCCESS; - } else { - // If HeapStatus == HEAP_SYSTEM_MEM, try callout function - if (StdHeader->HeapStatus == HEAP_SYSTEM_MEM) { - AgesaBuffer.StdHeader = *StdHeader; - AgesaBuffer.BufferHandle = LocateHeap->BufferHandle; - - AGESA_TESTPOINT (TpIfBeforeLocateHeapBuffer, StdHeader); - if (AgesaLocateBuffer (0, &AgesaBuffer) != AGESA_SUCCESS) { - LocateHeap->BufferPtr = NULL; - return AGESA_ERROR; - } - LocateHeap->BufferSize = AgesaBuffer.BufferLength; - AGESA_TESTPOINT (TpIfAfterLocateHeapBuffer, StdHeader); - - LocateHeap->BufferPtr = (UINT8 *) (AgesaBuffer.BufferPointer); - return AGESA_SUCCESS; - } - - // If we are still unable to deallocate the buffer handle, return AGESA_BOUNDS_CHK - LocateHeap->BufferPtr = NULL; - LocateHeap->BufferSize = 0; - if ((BaseAddress != NULL) && (HeapManager->Signature == HEAP_SIGNATURE_VALID)) { - PutEventLog (AGESA_BOUNDS_CHK, - CPU_ERROR_HEAP_BUFFER_HANDLE_IS_NOT_PRESENT, - LocateHeap->BufferHandle, 0, 0, 0, StdHeader); - } else { - ASSERT (FALSE); - } - return AGESA_BOUNDS_CHK; - } -} - -/*---------------------------------------------------------------------------------------*/ -/** - * Get the heap base address - * - * This function will try to locate heap from cache, temp memory, main memory. - * The heap signature will be checked for validity on each possible location. - * Firstly, try if heap base is in cache by calling the function HeapGetCurrentBase. - * Secondly, try if heap base is temp memory by UserOptoions.CfgHeapDramAddress. - * Thirdly, try if heap base is in main memory by doing a buffer locate with buffer handle - * AMD_HEAP_IN_MAIN_MEMORY_HANDLE. - * If no valid heap signature is found in each possible location above, a NULL pointer is returned. - * - * @param[in] StdHeader Config handle for library and services. - * - * @return Heap base address of the executing core's heap. - * - */ -UINT64 -HeapGetBaseAddress ( - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - UINT64 BaseAddress; - HEAP_MANAGER *HeapManager; - AGESA_BUFFER_PARAMS AgesaBuffer; - - // Firstly, we try to see if heap is in cache - BaseAddress = HeapGetCurrentBase (StdHeader); - HeapManager = (HEAP_MANAGER *) (intptr_t) BaseAddress; - - if ((HeapManager->Signature != HEAP_SIGNATURE_VALID) && - (StdHeader->HeapStatus != HEAP_DO_NOT_EXIST_YET) && - (StdHeader->HeapStatus != HEAP_LOCAL_CACHE)) { - // Secondly, we try to see if heap is in temp memory - BaseAddress = UserOptions.CfgHeapDramAddress; - HeapManager = (HEAP_MANAGER *) (intptr_t) BaseAddress; - if (HeapManager->Signature != HEAP_SIGNATURE_VALID) { - // Thirdly, we try to see if heap in main memory - // by locating with external buffer manager (IBV) - AgesaBuffer.StdHeader = *StdHeader; - AgesaBuffer.BufferHandle = AMD_HEAP_IN_MAIN_MEMORY_HANDLE; - if (AgesaLocateBuffer (0, &AgesaBuffer) == AGESA_SUCCESS) { - BaseAddress = (UINT64) (intptr_t) AgesaBuffer.BufferPointer; - HeapManager = (HEAP_MANAGER *) (intptr_t) BaseAddress; - if (HeapManager->Signature != HEAP_SIGNATURE_VALID) { - // No valid heap signature ever found, return a NULL pointer - BaseAddress = (UINT64) (intptr_t) NULL; - } - } else { - // No heap buffer is allocated by external manager (IBV), return a NULL pointer - BaseAddress = (UINT64) (intptr_t) NULL; - } - } - } - - return BaseAddress; -} - -/*--------------------------------------------------------------------------------------- - * L O C A L F U N C T I O N S - *--------------------------------------------------------------------------------------- - */ -/* -----------------------------------------------------------------------------*/ -/** - * - * DeleteFreeSpaceNode - * - * Description: - * Delete a free space node from free space chain - * - * Parameters: - * @param[in] StdHeader Config handle for library and services. - * @param[in] OffsetOfDeletedNode Offset of deleted node. - * - * Processing: - * - */ -VOID -STATIC -DeleteFreeSpaceNode ( - IN AMD_CONFIG_PARAMS *StdHeader, - IN UINT32 OffsetOfDeletedNode - ) -{ - UINT8 *BaseAddress; - UINT32 OffsetOfPreviousNode; - UINT32 OffsetOfCurrentNode; - HEAP_MANAGER *HeapManager; - BUFFER_NODE *CurrentFreeSpaceNode; - BUFFER_NODE *PreviousFreeSpaceNode; - - - BaseAddress = (UINT8 *) (intptr_t) StdHeader->HeapBasePtr; - HeapManager = (HEAP_MANAGER *) BaseAddress; - - OffsetOfPreviousNode = AMD_HEAP_INVALID_HEAP_OFFSET; - OffsetOfCurrentNode = HeapManager->FirstFreeSpaceOffset; - // - // After AmdInitEnv, there is no free space provided for HeapAllocateBuffer. - // Hence if the FirstFreeSpaceOffset is AMD_HEAP_INVALID_HEAP_OFFSET, then - // no need to do more on delete node. - // - if (OffsetOfCurrentNode != AMD_HEAP_INVALID_HEAP_OFFSET) { - CurrentFreeSpaceNode = (BUFFER_NODE *) (BaseAddress + OffsetOfCurrentNode); - while ((OffsetOfCurrentNode != AMD_HEAP_INVALID_HEAP_OFFSET) && (OffsetOfCurrentNode != OffsetOfDeletedNode)) { - OffsetOfPreviousNode = OffsetOfCurrentNode; - OffsetOfCurrentNode = CurrentFreeSpaceNode->OffsetOfNextNode; - CurrentFreeSpaceNode = (BUFFER_NODE *) (BaseAddress + OffsetOfCurrentNode); - } - if (OffsetOfCurrentNode != AMD_HEAP_INVALID_HEAP_OFFSET) { - if (OffsetOfPreviousNode == AMD_HEAP_INVALID_HEAP_OFFSET) { - HeapManager->FirstFreeSpaceOffset = CurrentFreeSpaceNode->OffsetOfNextNode; - } else { - PreviousFreeSpaceNode = (BUFFER_NODE *) (BaseAddress + OffsetOfPreviousNode); - PreviousFreeSpaceNode->OffsetOfNextNode = CurrentFreeSpaceNode->OffsetOfNextNode; - } - } - } - return; -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * InsertFreeSpaceNode - * - * Description: - * Insert a free space node to free space chain, size order - * - * Parameters: - * @param[in] StdHeader Config handle for library and services. - * @param[in] OffsetOfInsertNode Offset of inserted node. - * - * Processing: - * - */ -VOID -STATIC -InsertFreeSpaceNode ( - IN AMD_CONFIG_PARAMS *StdHeader, - IN UINT32 OffsetOfInsertNode - ) -{ - UINT8 *BaseAddress; - UINT32 OffsetOfPreviousNode; - UINT32 OffsetOfCurrentNode; - HEAP_MANAGER *HeapManager; - BUFFER_NODE *CurrentFreeSpaceNode; - BUFFER_NODE *PreviousFreeSpaceNode; - BUFFER_NODE *LocalInsertFreeSpaceNode; - - BaseAddress = (UINT8 *) (intptr_t) StdHeader->HeapBasePtr; - HeapManager = (HEAP_MANAGER *) BaseAddress; - - OffsetOfPreviousNode = AMD_HEAP_INVALID_HEAP_OFFSET; - OffsetOfCurrentNode = HeapManager->FirstFreeSpaceOffset; - CurrentFreeSpaceNode = (BUFFER_NODE *) (BaseAddress + OffsetOfCurrentNode); - LocalInsertFreeSpaceNode = (BUFFER_NODE *) (BaseAddress + OffsetOfInsertNode); - while ((OffsetOfCurrentNode != AMD_HEAP_INVALID_HEAP_OFFSET) && - (CurrentFreeSpaceNode->BufferSize < LocalInsertFreeSpaceNode->BufferSize)) { - OffsetOfPreviousNode = OffsetOfCurrentNode; - OffsetOfCurrentNode = CurrentFreeSpaceNode->OffsetOfNextNode; - CurrentFreeSpaceNode = (BUFFER_NODE *) (BaseAddress + OffsetOfCurrentNode); - } - LocalInsertFreeSpaceNode->OffsetOfNextNode = OffsetOfCurrentNode; - if (OffsetOfPreviousNode == AMD_HEAP_INVALID_HEAP_OFFSET) { - HeapManager->FirstFreeSpaceOffset = OffsetOfInsertNode; - } else { - PreviousFreeSpaceNode = (BUFFER_NODE *) (BaseAddress + OffsetOfPreviousNode); - PreviousFreeSpaceNode->OffsetOfNextNode = OffsetOfInsertNode; - } - return; -} - -/*---------------------------------------------------------------------------------------*/ -/** - * Determines the base address of the executing core's heap. - * - * This function uses the executing core's socket/core numbers to determine - * where it's heap should be located. - * - * @param[in] StdHeader Config handle for library and services. - * - * @return A pointer to the executing core's heap. - * - */ -UINT64 -STATIC -HeapGetCurrentBase ( - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - UINT32 SystemCoreNumber; - UINT64 ReturnPtr; - AGESA_STATUS IgnoredStatus; - CPU_SPECIFIC_SERVICES *FamilyServices; - - if (IsBsp (StdHeader, &IgnoredStatus)) { - ReturnPtr = AMD_HEAP_START_ADDRESS; - } else { - GetCpuServicesOfCurrentCore ((const CPU_SPECIFIC_SERVICES **)&FamilyServices, StdHeader); - ASSERT (FamilyServices != NULL); - - SystemCoreNumber = FamilyServices->GetApCoreNumber (FamilyServices, StdHeader); - ASSERT (SystemCoreNumber != 0); - ASSERT (SystemCoreNumber < 64); - ReturnPtr = ((SystemCoreNumber * AMD_HEAP_SIZE_PER_CORE) + AMD_HEAP_START_ADDRESS); - } - ASSERT (ReturnPtr <= ((AMD_HEAP_REGION_END_ADDRESS + 1) - AMD_HEAP_SIZE_PER_CORE)); - return ReturnPtr; -} - - diff --git a/src/vendorcode/amd/agesa/f12/Proc/CPU/heapManager.h b/src/vendorcode/amd/agesa/f12/Proc/CPU/heapManager.h deleted file mode 100644 index 3afc7989e8..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/CPU/heapManager.h +++ /dev/null @@ -1,234 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * AMD Heap Manager and Heap Allocation APIs, and related functions. - * - * Contains code that initialize, maintain, and allocate the heap space. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: CPU - * @e \$Revision: 49532 $ @e \$Date: 2011-03-25 02:54:43 +0800 (Fri, 25 Mar 2011) $ - * - */ -/* - ****************************************************************************** - * - * Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - ****************************************************************************** - */ - -#ifndef _HEAP_MANAGER_H_ -#define _HEAP_MANAGER_H_ - -/*--------------------------------------------------------------------------------------- - * M I X E D (Definitions And Macros / Typedefs, Structures, Enums) - *--------------------------------------------------------------------------------------- - */ - - -/*--------------------------------------------------------------------------------------- - * D E F I N I T I O N S A N D M A C R O S - *--------------------------------------------------------------------------------------- - */ -#define AMD_MTRR_VARIABLE_BASE0 0x200 -#define AMD_MTRR_VARIABLE_HEAP_BASE 0x20A -#define AMD_MTRR_VARIABLE_HEAP_MASK (AMD_MTRR_VARIABLE_HEAP_BASE + 1) - -#define AMD_HEAP_START_ADDRESS 0x400000 -#define AMD_HEAP_REGION_END_ADDRESS 0xBFFFFF -#define AMD_HEAP_SIZE_PER_CORE 0x010000 -#define AMD_HEAP_INVALID_HEAP_OFFSET 0xFFFFFFFF -#define AMD_HEAP_MTRR_MASK (0xFFFFFFFFFFFFF800ull & (((AMD_HEAP_SIZE_PER_CORE ^ (-1)) + 1) | 0x800)) -#define AMD_HEAP_SIZE_DWORD_PER_CORE (AMD_HEAP_SIZE_PER_CORE / 4) - -#define AMD_TEMP_TOM 0x20000000 // Set TOM to 512 MB (temporary value) -#define AMD_VAR_MTRR_ENABLE_BIT 0x100000 // bit 20 - -#define AMD_HEAP_RAM_ADDRESS 0xB0000 - -#define HEAP_SIGNATURE_VALID 0x50414548 // Signature: 'HEAP' -#define HEAP_SIGNATURE_INVALID 0x00000000 // Signature cleared - -///Heap Manager Life cycle -#define HEAP_DO_NOT_EXIST_YET 1 -#define HEAP_LOCAL_CACHE 2 -#define HEAP_TEMP_MEM 3 -#define HEAP_SYSTEM_MEM 4 -#define HEAP_DO_NOT_EXIST_ANYMORE 5 -#define HEAP_S3_RESUME 6 - - -#define AMD_MTRR_FIX64k_00000 0x250 -#define AMD_MTRR_FIX16k_80000 0x258 -#define AMD_MTRR_FIX16k_A0000 0x259 -#define AMD_MTRR_FIX4k_C0000 0x268 -#define AMD_MTRR_FIX4k_C8000 0x269 -#define AMD_MTRR_FIX4k_D0000 0x26A -#define AMD_MTRR_FIX4k_D8000 0x26B -#define AMD_MTRR_FIX4k_E0000 0x26C -#define AMD_MTRR_FIX4k_E8000 0x26D -#define AMD_MTRR_FIX4k_F0000 0x26E -#define AMD_MTRR_FIX4k_F8000 0x26F - -#define AMD_MTRR_FIX64K_WB_DRAM 0x1E -#define AMD_MTRR_FIX64K_WT_DRAM 0x1C -#define AMD_MTRR_FIX64K_UC_DRAM 0x18 -#define AMD_MTRR_FIX16K_WB_DRAM 0x1E1E1E1E1E1E1E1Eull -#define AMD_MTRR_FIX16K_WT_DRAM 0x1C1C1C1C1C1C1C1Cull -#define AMD_MTRR_FIX16K_UC_DRAM 0x1818181818181818ull -#define AMD_MTRR_FIX4K_WB_DRAM 0x1E1E1E1E1E1E1E1Eull -#define AMD_MTRR_FIX4K_WT_DRAM 0x1C1C1C1C1C1C1C1Cull -#define AMD_MTRR_FIX4K_UC_DRAM 0x1818181818181818ull - -/*--------------------------------------------------------------------------------------- - * T Y P E D E F S, S T R U C T U R E S, E N U M S - *--------------------------------------------------------------------------------------- - */ -/// Allocate Heap Parameters -typedef struct _ALLOCATE_HEAP_PARAMS { - UINT32 RequestedBufferSize; ///< Size of buffer. - UINT32 BufferHandle; ///< An unique ID of buffer. - UINT8 Persist; ///< A flag. If marked, to be stored and passed to AmdInitLate. - UINT8 *BufferPtr; ///< Pointer to buffer. -} ALLOCATE_HEAP_PARAMS; - -/// Locate Heap Parameters -typedef struct _LOCATE_HEAP_PTR { - UINT32 BufferHandle; ///< An unique ID of buffer. - UINT32 BufferSize; ///< Data buffer size. - UINT8 *BufferPtr; ///< Pointer to buffer. -} LOCATE_HEAP_PTR; - -/// Heap Node Header -typedef struct _BUFFER_NODE { - UINT32 BufferHandle; ///< An unique ID of buffer. - UINT32 BufferSize; ///< Size of buffer. - UINT8 Persist; ///< A flag. If marked, to be stored and passed to AmdInitLate. - UINT8 PadSize; ///< Size of pad. - UINT32 OffsetOfNextNode; ///< Offset of next node (relative to the base). -} BUFFER_NODE; - -/// Heap Manager -typedef struct _HEAP_MANAGER { - UINT32 Signature; ///< a signature to indicate if the heap is valid. - UINT32 UsedSize; ///< Used size of heap. - UINT32 FirstActiveBufferOffset; ///< Offset of the first active buffer. - UINT32 FirstFreeSpaceOffset; ///< Offset of the first free space. -} HEAP_MANAGER; - -/// AGESA Buffer Handles (These are reserved) -typedef enum { - AMD_INIT_RESET_HANDLE = 0x000A000, ///< Assign 0x000A000 buffer handle to AmdInitReset routine. - AMD_INIT_EARLY_HANDLE, ///< Assign 0x000A001 buffer handle to AmdInitEarly routine. - AMD_INIT_POST_HANDLE, ///< Assign 0x000A002 buffer handle to AmdInitPost routine. - AMD_INIT_ENV_HANDLE, ///< Assign 0x000A003 buffer handle to AmdInitEnv routine. - AMD_INIT_MID_HANDLE, ///< Assign 0x000A004 buffer handle to AmdInitMid routine. - AMD_INIT_LATE_HANDLE, ///< Assign 0x000A005 buffer handle to AmdInitLate routine. - AMD_INIT_RESUME_HANDLE, ///< Assign 0x000A006 buffer handle to AmdInitResume routine. - AMD_LATE_RUN_AP_TASK_HANDLE, ///< Assign 0x000A007 buffer handle to AmdLateRunApTask routine. - AMD_S3_SAVE_HANDLE, ///< Assign 0x000A008 buffer handle to AmdS3Save routine. - AMD_S3_LATE_RESTORE_HANDLE, ///< Assign 0x000A009 buffer handle to AmdS3LateRestore routine. - AMD_S3_SCRIPT_SAVE_TABLE_HANDLE, ///< Assign 0x000A00A buffer handle to be used for S3 save table - AMD_S3_SCRIPT_TEMP_BUFFER_HANDLE, ///< Assign 0x000A00B buffer handle to be used for S3 save table - AMD_CPU_AP_TASKING_HANDLE, ///< Assign 0x000A00C buffer handle to AP tasking input parameters. - AMD_REC_MEM_SOCKET_HANDLE, ///< Assign 0x000A00D buffer handle to save socket with memory in memory recovery mode. - AMD_MEM_AUTO_HANDLE, ///< Assign 0x000A00E buffer handle to AmdMemAuto routine. - AMD_MEM_SPD_HANDLE, ///< Assign 0x000A00F buffer handle to AmdMemSpd routine. - AMD_MEM_DATA_HANDLE, ///< Assign 0x000A010 buffer handle to MemData - AMD_MEM_TRAIN_BUFFER_HANDLE, ///< Assign 0x000A011 buffer handle to allocate buffer for training - AMD_MEM_S3_DATA_HANDLE, ///< Assign 0x000A012 buffer handle to special case register for S3 - AMD_MEM_S3_NB_HANDLE, ///< Assign 0x000A013 buffer handle to NB block for S3 - AMD_MEM_S3_MR0_DATA_HANDLE, ///< Assign 0x000A014 buffer handle to MR0 data block for S3 - AMD_UMA_INFO_HANDLE, ///< Assign 0x000A015 buffer handle to be used for Uma information - AMD_DMI_MEM_DEV_INFO_HANDLE, ///< Assign 0x000A016 buffer handle to DMI Type16 17 19 20 information - HT_STATE_DATA_HANDLE, ///< Assign 0x000A017 buffer handle to HT State Data - PRESERVE_MAIL_BOX_HANDLE, ///< Assign 0x000A018 buffer handle for Preserve Mailbox Feature. - EVENT_LOG_BUFFER_HANDLE, ///< Assign 0x000A019 buffer handle to Event Log - IDS_CONTROL_HANDLE, ///< Assign 0x000A01A buffer handle to AmdIds routine. - IDS_HT_DATA_HANDLE, ///< Assign 0x000A01B buffer handle to Ht IDS control - IDS_HDT_OUT_BUFFER_HANDLE, ///< Assign 0x000A01C buffer handle to be used for HDTOUT support. - IDS_CHECK_POINT_PERF_HANDLE, ///< Assign 0x000A01D buffer handle to Performance analysis - AMD_PCIE_COMPLEX_DATA_HANDLE, ///< Assign 0x000A01F buffer handle to be used for PCIe support - AMD_GNB_SMU_CONFIG_HANDLE, ///< Assign 0x000A020 buffer handle to be used for GNB SMU configuration - AMD_PP_FUSE_TABLE_HANDLE, ///< Assign 0x000A021 buffer handle to be used for TT fuse table - AMD_GFX_PLATFORM_CONFIG_HANDLE, ///< Assign 0x000A022 buffer handle to be used for Gfx platform configuration - AMD_FCH_DATA_BLOCK_HANDLE, ///< Assign 0x000A023 buffer handle for FCH internal data block - AMD_GNB_TEMP_DATA_HANDLE, ///< Assign 0x000A024 buffer handle for GNB general purpose data block - AMD_MEM_MISC_HANDLES_START = 0x1000000, ///< Reserve 0x1000000 to 0x1FFFFFF buffer handle - AMD_MEM_MISC_HANDLES_END = 0x1FFFFFF, ///< miscellaneous memory init tasks' buffers. - AMD_HEAP_IN_MAIN_MEMORY_HANDLE = 0x8000000, ///< Assign 0x8000000 to AMD_HEAP_IN_MAIN_MEMORY_HANDLE. - SOCKET_DIE_MAP_HANDLE = 0x534F4B54, ///< 'sokt' - NODE_ID_MAP_HANDLE = 0x4E4F4445, ///< 'node' - HOP_COUNT_TABLE_HANDLE = 0x484F5053, ///< 'hops' - LOCAL_AP_MAIL_BOX_CACHE_HANDLE = 0x414D4258, ///< 'ambx' - IDS_REG_TABLE_HANDLE = 0x49524547, ///< 'IREG' Handle for IDS register table - IDS_SAVE_IDTR_HANDLE = 0x49445452, ///< 'IDTR' - IDS_BSC_IDT_HANDLE = 0x42534349, ///< 'BSCI' BSC Idt table - IDS_NV_TO_CMOS_HANDLE = 0x534D4349, ///< 'ICMS' Handle for IDS CMOS save - IDS_EXTEND_HANDLE = 0x54584549 ///< 'IEXT' Handle for IDS extend module -} AGESA_BUFFER_HANDLE; - - -/*--------------------------------------------------------------------------------------- - * F U N C T I O N P R O T O T Y P E - *--------------------------------------------------------------------------------------- - */ - -AGESA_STATUS -HeapManagerInit ( - IN AMD_CONFIG_PARAMS *StdHeader - ); - -AGESA_STATUS -HeapAllocateBuffer ( - IN OUT ALLOCATE_HEAP_PARAMS *AllocateHeapParams, - IN OUT AMD_CONFIG_PARAMS *StdHeader - ); - -AGESA_STATUS -HeapDeallocateBuffer ( - IN UINT32 BufferHandle, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -AGESA_STATUS -HeapLocateBuffer ( - IN OUT LOCATE_HEAP_PTR *LocateHeap, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -UINT64 -HeapGetBaseAddress ( - IN AMD_CONFIG_PARAMS *StdHeader - ); - -AGESA_STATUS -EventLogInitialization ( - IN AMD_CONFIG_PARAMS *StdHeader - ); -#endif // _HEAP_MANAGER_H_ diff --git a/src/vendorcode/amd/agesa/f12/Proc/Common/AmdFch.h b/src/vendorcode/amd/agesa/f12/Proc/Common/AmdFch.h deleted file mode 100644 index f9bdddbbd6..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/Common/AmdFch.h +++ /dev/null @@ -1,65 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * AMD FCH Component - * - * - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: FCH - * @e \$Revision: 34897 $ @e \$Date: 2010-07-13 19:07:10 -0700 (Tue, 13 Jul 2010) $ - * - */ -/* -***************************************************************************** -* -* Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* *************************************************************************** -* -*/ - -#ifndef _AMD_FCH_H_ -#define _AMD_FCH_H_ - -typedef AGESA_STATUS FCH_INIT (IN VOID *DataPtr); -typedef VOID FCH_TASK_ENTRY (IN VOID *FchCfg); - - -/// FCH API build options -typedef struct { - FCH_INIT *InitReset; ///< InitReset - FCH_INIT *InitResetConstructor; ///< InitResetConstructor - FCH_INIT *InitEnv; ///< InitEnv - FCH_INIT *InitEnvConstructor; ///< InitEnvConstructor - FCH_INIT *InitMid; ///< InitMid - FCH_INIT *InitMidConstructor; ///< InitMidConstructor - FCH_INIT *InitLate; ///< InitLate - FCH_INIT *InitLateConstructor; ///< InitLateConstructor -} BLDOPT_FCH_FUNCTION; - -#endif diff --git a/src/vendorcode/amd/agesa/f12/Proc/Common/AmdInitEarly.c b/src/vendorcode/amd/agesa/f12/Proc/Common/AmdInitEarly.c deleted file mode 100644 index daedd9f478..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/Common/AmdInitEarly.c +++ /dev/null @@ -1,317 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * AMD AGESA Basic Level Public APIs - * - * Contains basic Level Initialization routines. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: Interface - * @e \$Revision: 48404 $ @e \$Date: 2011-03-09 00:21:32 +0800 (Wed, 09 Mar 2011) $ - * - */ -/***************************************************************************** - * - * Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - ****************************************************************************** - */ - - -/*---------------------------------------------------------------------------------------- - * M O D U L E S U S E D - *---------------------------------------------------------------------------------------- - */ -#include "AGESA.h" -#include "amdlib.h" -#include "Ids.h" -#include "cpuCacheInit.h" -#include "AmdFch.h" -#include "cpuRegisters.h" -#include "heapManager.h" -#include "cpuApicUtilities.h" -#include "cpuEarlyInit.h" -#include "AdvancedApi.h" -#include "cpuServices.h" -#include "CommonInits.h" -#include "GnbInterface.h" -#include "CreateStruct.h" -#include "Filecode.h" -CODE_GROUP (G1_PEICC) -RDATA_GROUP (G1_PEICC) - -#define FILECODE PROC_COMMON_AMDINITEARLY_FILECODE -/*---------------------------------------------------------------------------------------- - * D E F I N I T I O N S A N D M A C R O S - *---------------------------------------------------------------------------------------- - */ - - -/*---------------------------------------------------------------------------------------- - * T Y P E D E F S A N D S T R U C T U R E S - *---------------------------------------------------------------------------------------- - */ -EXECUTION_CACHE_REGION InitExeCacheMap[] = -{ - {0x00000000, 0x00000000}, - {0x00000000, 0x00000000}, - {0x00000000, 0x00000000} -}; - -/*---------------------------------------------------------------------------------------- - * P R O T O T Y P E S O F L O C A L F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ -AGESA_STATUS -AmdEarlyPlatformConfigInit ( - IN OUT PLATFORM_CONFIGURATION *PlatformConfig, - IN OUT AMD_CONFIG_PARAMS *StdHeader - ); - -AGESA_STATUS -AllocateExecutionCacheInitializer ( - IN AMD_CONFIG_PARAMS *StdHeader, - IN EXECUTION_CACHE_REGION *AmdExeAddrMapPtr - ); - -/*---------------------------------------------------------------------------------------- - * E X P O R T E D F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ -extern BUILD_OPT_CFG UserOptions; -/*------------------------------------------------------------------------------------*/ -/** - * Initialize AmdInitEarly stage platform profile and user option input. - * - * @param[in,out] PlatformConfig Platform profile/build option config structure - * @param[in,out] StdHeader AMD standard header config param - * - * @retval AGESA_SUCCESS Always Succeeds. - * - */ -AGESA_STATUS -AmdEarlyPlatformConfigInit ( - IN OUT PLATFORM_CONFIGURATION *PlatformConfig, - IN OUT AMD_CONFIG_PARAMS *StdHeader - ) -{ - CommonPlatformConfigInit (PlatformConfig, StdHeader); - - return AGESA_SUCCESS; -} -/*------------------------------------------------------------------------------------*/ -/** - * Initializer routine that will be invoked by the wrapper to initialize the input - * structure for the AllocateExecutionCache. - * - * @param[in] StdHeader Opaque handle to standard config header - * @param[in] AmdExeAddrMapPtr Our Service interface struct - * - * @retval AGESA_SUCCESS Always Succeeds. - * - */ -AGESA_STATUS -AllocateExecutionCacheInitializer ( - IN AMD_CONFIG_PARAMS *StdHeader, - IN EXECUTION_CACHE_REGION *AmdExeAddrMapPtr - ) -{ - UINT8 i; - ASSERT (AmdExeAddrMapPtr != NULL); - - for (i = 0; i < MAX_CACHE_REGIONS; ++i) { - AmdExeAddrMapPtr[i].ExeCacheStartAddr = InitExeCacheMap[i].ExeCacheStartAddr; - AmdExeAddrMapPtr[i].ExeCacheSize = InitExeCacheMap[i].ExeCacheSize; - } - - return AGESA_SUCCESS; -} - -/*---------------------------------------------------------------------------------------*/ -/** - * - * Initializer routine that will be invoked by the wrapper to initialize the input - * structure for the AmdInitEarly. - * - * @param[in] StdHeader AMD standard header config param. - * @param[in,out] EarlyParams The service interface struct to initialize. - * - * @retval AGESA_SUCCESS Always succeeds. - */ -AGESA_STATUS -AmdInitEarlyInitializer ( - IN AMD_CONFIG_PARAMS *StdHeader, - IN OUT AMD_EARLY_PARAMS *EarlyParams - ) -{ - ASSERT (StdHeader != NULL); - ASSERT (EarlyParams != NULL); - - EarlyParams->StdHeader = *StdHeader; - - // We don't check any AGESA_STATUS from the called constructors, since they MUST all SUCCEED. - // - - AllocateExecutionCacheInitializer (&EarlyParams->StdHeader, &EarlyParams->CacheRegion[0]); - - AmdHtInterfaceConstructor (&EarlyParams->StdHeader, &EarlyParams->HtConfig); - - AmdEarlyPlatformConfigInit (&EarlyParams->PlatformConfig, &EarlyParams->StdHeader); - - return AGESA_SUCCESS; -} - - -/*---------------------------------------------------------------------------------------*/ -/** - * Perform initialization services required at the Early Init POST time point. - * - * Execution Cache, HyperTransport, and AP Init advanced services are performed. - * - * @param[in] EarlyParams The interface struct for all early services - * - * @return The most severe AGESA_STATUS returned by any called service. - * - */ -AGESA_STATUS -AmdInitEarly ( - IN OUT AMD_EARLY_PARAMS *EarlyParams - ) -{ - AGESA_STATUS CalledAgesaStatus; - AGESA_STATUS EarlyInitStatus; - WARM_RESET_REQUEST Request; - UINT8 PrevRequestBit; - UINT8 PrevStateBits; - - AGESA_TESTPOINT (TpIfAmdInitEarlyEntry, &EarlyParams->StdHeader); - - EarlyInitStatus = AGESA_SUCCESS; - - // Setup ROM execution cache - IDS_HDT_CONSOLE (MAIN_FLOW, "AllocateExecutionCache: Start\n"); - CalledAgesaStatus = AllocateExecutionCache (&EarlyParams->StdHeader, &EarlyParams->CacheRegion[0]); - IDS_HDT_CONSOLE (MAIN_FLOW, "AllocateExecutionCache: End\n"); - if (CalledAgesaStatus > EarlyInitStatus) { - EarlyInitStatus = CalledAgesaStatus; - } - - IDS_HDT_CONSOLE_DEBUG_CODE ( - { - extern CHAR8 *BldOptDebugOutput[]; - - UINT8 i; - for (i = 0; BldOptDebugOutput[i] != NULL; i++) { - IDS_HDT_CONSOLE (MAIN_FLOW, "\t%s\n", BldOptDebugOutput[i]); - } - } - ) - - // - // WARNING: AGESA's own IDT is at heap which would be moved from one place to another - // so we MUST restore IDT every time before moving heap. - // -// IDS_EXCEPTION_TRAP (IDS_IDT_REPLACE_IDTR_FOR_BSC, NULL, &EarlyParams->StdHeader); - IDS_PERF_TIME_MEASURE (&EarlyParams->StdHeader); - ASSERT (EarlyParams != NULL); - PrevRequestBit = FALSE; - PrevStateBits = WR_STATE_COLD; - IDS_HDT_CONSOLE (MAIN_FLOW, "\nAmdInitEarly: Start %x \n\n", PrevStateBits); - // If a previously requested warm reset cannot be triggered in the - // current stage, store the previous state of request and reset the - // request struct to the current post stage - GetWarmResetFlag (&EarlyParams->StdHeader, &Request); - if (Request.RequestBit == TRUE) { - if (Request.StateBits >= Request.PostStage) { - PrevRequestBit = Request.RequestBit; - PrevStateBits = Request.StateBits; - Request.RequestBit = FALSE; - Request.StateBits = Request.PostStage - 1; - SetWarmResetFlag (&EarlyParams->StdHeader, &Request); - } - } - - IDS_OPTION_HOOK (IDS_INIT_EARLY_BEFORE, EarlyParams, &EarlyParams->StdHeader); - - // Full Hypertransport Initialization - // IMPORTANT: All AP cores call Ht Init. HT Init handles full init for the BSC, and map init for APs. - IDS_HDT_CONSOLE (MAIN_FLOW, "AmdHtInitialize: Start\n"); - CalledAgesaStatus = AmdHtInitialize (&EarlyParams->StdHeader, &EarlyParams->PlatformConfig, &EarlyParams->HtConfig); - IDS_HDT_CONSOLE (MAIN_FLOW, "AmdHtInitialize: End\n"); - if (CalledAgesaStatus > EarlyInitStatus) { - EarlyInitStatus = CalledAgesaStatus; - } - - CalledAgesaStatus = GnbInitAtEarlier (EarlyParams); - if (CalledAgesaStatus > EarlyInitStatus) { - EarlyInitStatus = CalledAgesaStatus; - } - - // AP launch - IDS_HDT_CONSOLE (MAIN_FLOW, "AmdCpuEarly: Start\n"); - CalledAgesaStatus = AmdCpuEarly (&EarlyParams->StdHeader, &EarlyParams->PlatformConfig); - IDS_HDT_CONSOLE (MAIN_FLOW, "AmdCpuEarly: End\n"); - if (CalledAgesaStatus > EarlyInitStatus) { - EarlyInitStatus = CalledAgesaStatus; - } - - // Warm Reset, should be at the end of AmdInitEarly - GetWarmResetFlag (&EarlyParams->StdHeader, &Request); - // If a warm reset is requested in the current post stage, trigger the - // warm reset and ignore the previous request - if (Request.RequestBit == TRUE) { - if (Request.StateBits < Request.PostStage) { - AgesaDoReset (WARM_RESET_WHENEVER, &EarlyParams->StdHeader); - } - } else { - // Otherwise, if there's a previous request, restore it - // so that the subsequent post stage can trigger the warm reset - if (PrevRequestBit == TRUE) { - Request.RequestBit = PrevRequestBit; - Request.StateBits = PrevStateBits; - SetWarmResetFlag (&EarlyParams->StdHeader, &Request); - } - } - - CalledAgesaStatus = GnbInitAtEarly (EarlyParams); - if (CalledAgesaStatus > EarlyInitStatus) { - EarlyInitStatus = CalledAgesaStatus; - } - // Check for Cache As Ram Corruption - IDS_CAR_CORRUPTION_CHECK (&EarlyParams->StdHeader); - - IDS_OPTION_HOOK (IDS_BEFORE_WARM_RESET, EarlyParams, &EarlyParams->StdHeader); - IDS_OPTION_HOOK (IDS_INIT_EARLY_AFTER, EarlyParams, &EarlyParams->StdHeader); - IDS_PERF_TIME_MEASURE (&EarlyParams->StdHeader); - AGESA_TESTPOINT (TpIfAmdInitEarlyExit, &EarlyParams->StdHeader); - IDS_HDT_CONSOLE (MAIN_FLOW, "\nAmdInitEarly: End\n\n"); - - // Flush out all debug contents in case warm reset is triggered after this point - IDS_HDT_CONSOLE_FLUSH_BUFFER (&EarlyParams->StdHeader); - - return EarlyInitStatus; -} diff --git a/src/vendorcode/amd/agesa/f12/Proc/Common/AmdInitEnv.c b/src/vendorcode/amd/agesa/f12/Proc/Common/AmdInitEnv.c deleted file mode 100644 index c49cd263ef..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/Common/AmdInitEnv.c +++ /dev/null @@ -1,181 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * AMD AGESA Basic Level Public APIs - * - * Contains basic Level Initialization routines. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: Interface - * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $ - * - */ -/***************************************************************************** - * - * Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - ****************************************************************************** - */ - - -/*---------------------------------------------------------------------------------------- - * M O D U L E S U S E D - *---------------------------------------------------------------------------------------- - */ -#include "AGESA.h" -#include "Ids.h" -#include "cpuEnvInit.h" -#include "heapManager.h" -#include "GnbInterface.h" -#include "CommonInits.h" -#include "AmdFch.h" -#include "S3SaveState.h" -#include "CreateStruct.h" -#include "Filecode.h" -CODE_GROUP (G1_PEICC) -RDATA_GROUP (G1_PEICC) - -#define FILECODE PROC_COMMON_AMDINITENV_FILECODE - -extern BLDOPT_FCH_FUNCTION BldoptFchFunction; - -/*---------------------------------------------------------------------------------------- - * D E F I N I T I O N S A N D M A C R O S - *---------------------------------------------------------------------------------------- - */ - - -/*---------------------------------------------------------------------------------------- - * T Y P E D E F S A N D S T R U C T U R E S - *---------------------------------------------------------------------------------------- - */ - - -/*---------------------------------------------------------------------------------------- - * P R O T O T Y P E S O F L O C A L F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ - - -/*---------------------------------------------------------------------------------------- - * E X P O R T E D F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ -/* - *--------------------------------------------------------------------------------------- - * - * Initializer routine that will be invoked by the wrapper - * to initialize the input structure for the AmdInitEnv - * - * @param[in,out] EnvParamsPtr Newly created interface parameters for AmdInitEnv - * - * @retval AGESA_SUCCESS Always succeeds - * - *--------------------------------------------------------------------------------------- - */ -AGESA_STATUS -AmdInitEnvInitializer ( - IN AMD_CONFIG_PARAMS *StdHeader, - IN OUT AMD_ENV_PARAMS *EnvParamsPtr - ) -{ - ASSERT (StdHeader != NULL); - ASSERT (EnvParamsPtr != NULL); - - EnvParamsPtr->StdHeader = *StdHeader; - - CommonPlatformConfigInit (&EnvParamsPtr->PlatformConfig, &EnvParamsPtr->StdHeader); - BldoptFchFunction.InitEnvConstructor (EnvParamsPtr); - GnbInitDataStructAtEnvDef (&EnvParamsPtr->GnbEnvConfiguration, EnvParamsPtr); - - return AGESA_SUCCESS; -} - - -/*---------------------------------------------------------------------------------------*/ -/** - * Main entry point for the AMD_INIT_ENV function. - * - * This entry point is responsible for copying the heap contents from the - * temp RAM area to main memory. - * - * @param[in,out] EnvParams Required input parameters for the AMD_INIT_ENV - * entry point. - * - * @return Aggregated status across all internal AMD env calls invoked. - * - */ -AGESA_STATUS -AmdInitEnv ( - IN OUT AMD_ENV_PARAMS *EnvParams - ) -{ - AGESA_STATUS AgesaStatus; - AGESA_STATUS AmdInitEnvStatus; - - AGESA_TESTPOINT (TpIfAmdInitEnvEntry, &EnvParams->StdHeader); - - ASSERT (EnvParams != NULL); - AmdInitEnvStatus = AGESA_SUCCESS; - - - //Copy Temp Ram heap content to Main Ram - AgesaStatus = CopyHeapToMainRamAtPost (&(EnvParams->StdHeader)); - if (AgesaStatus > AmdInitEnvStatus) { - AmdInitEnvStatus = AgesaStatus; - } - EnvParams->StdHeader.HeapStatus = HEAP_SYSTEM_MEM; - EnvParams->StdHeader.HeapBasePtr = HeapGetBaseAddress (&EnvParams->StdHeader); - // Any heap allocate/deallocat/locate buffer should be used after heap is rebuild from here. - // After persist heaps are tansfer and rebuild, HeapLocateBuffer can start to be used in IDS hook. - - //Heap have been relocated, so Debug Print need be init again to get new address - IDS_HDT_CONSOLE_INIT (&EnvParams->StdHeader); - IDS_HDT_CONSOLE (MAIN_FLOW, "Heap transfer End\n"); - IDS_HDT_CONSOLE (MAIN_FLOW, "AmdInitEnv: Start\n\n"); - IDS_OPTION_HOOK (IDS_PLATFORMCFG_OVERRIDE, &EnvParams->PlatformConfig, &(EnvParams->StdHeader)); - IDS_OPTION_HOOK (IDS_BEFORE_PCI_INIT, EnvParams, &(EnvParams->StdHeader)); - - AgesaStatus = S3ScriptInit (&EnvParams->StdHeader); - if (AgesaStatus > AmdInitEnvStatus) { - AmdInitEnvStatus = AgesaStatus; - } - AgesaStatus = BldoptFchFunction.InitEnv (EnvParams); - AmdInitEnvStatus = (AgesaStatus > AmdInitEnvStatus) ? AgesaStatus : AmdInitEnvStatus; - - AgesaStatus = GnbInitAtEnv (EnvParams); - if (AgesaStatus > AmdInitEnvStatus) { - AmdInitEnvStatus = AgesaStatus; - } - - AGESA_TESTPOINT (TpIfAmdInitEnvExit, &EnvParams->StdHeader); - IDS_HDT_CONSOLE (MAIN_FLOW, "\nAmdInitEnv: End\n"); - IDS_HDT_CONSOLE_FLUSH_BUFFER (&EnvParams->StdHeader); - return AmdInitEnvStatus; -} - - diff --git a/src/vendorcode/amd/agesa/f12/Proc/Common/AmdInitLate.c b/src/vendorcode/amd/agesa/f12/Proc/Common/AmdInitLate.c deleted file mode 100644 index fb63efb316..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/Common/AmdInitLate.c +++ /dev/null @@ -1,296 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * AMD AGESA Basic Level Public APIs - * - * Contains basic Level Initialization routines. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: Interface - * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $ - * - */ -/***************************************************************************** - * - * Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - ****************************************************************************** - */ - - -/*---------------------------------------------------------------------------------------- - * M O D U L E S U S E D - *---------------------------------------------------------------------------------------- - */ -#include "AGESA.h" -#include "amdlib.h" -#include "Ids.h" -#include "OptionDmi.h" -#include "OptionSlit.h" -#include "cpuLateInit.h" -#include "cpuFeatures.h" -#include "CommonInits.h" -#include "GnbInterface.h" -#include "OptionPstate.h" -#include "heapManager.h" -#include "CreateStruct.h" -#include "Filecode.h" -CODE_GROUP (G3_DXE) -RDATA_GROUP (G3_DXE) - -#define FILECODE PROC_COMMON_AMDINITLATE_FILECODE -/*---------------------------------------------------------------------------------------- - * D E F I N I T I O N S A N D M A C R O S - *---------------------------------------------------------------------------------------- - */ -extern OPTION_DMI_CONFIGURATION OptionDmiConfiguration; // global user config record -extern OPTION_SLIT_CONFIGURATION OptionSlitConfiguration; // global user config record -extern OPTION_PSTATE_LATE_CONFIGURATION OptionPstateLateConfiguration; - -/*---------------------------------------------------------------------------------------- - * T Y P E D E F S A N D S T R U C T U R E S - *---------------------------------------------------------------------------------------- - */ - - -/*---------------------------------------------------------------------------------------- - * P R O T O T Y P E S O F L O C A L F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ -AGESA_STATUS -AmdLatePlatformConfigInit ( - IN OUT PLATFORM_CONFIGURATION *PlatformConfig, - IN OUT AMD_CONFIG_PARAMS *StdHeader - ); - - -/*---------------------------------------------------------------------------------------- - * E X P O R T E D F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ -extern BUILD_OPT_CFG UserOptions; - -/*------------------------------------------------------------------------------------*/ -/** - * Initialize AmdInitLate stage platform profile and user option input. - * - * @param[in,out] PlatformConfig Platform profile/build option config structure - * @param[in,out] StdHeader AMD standard header config param - * - * @retval AGESA_SUCCESS Always Succeeds. - * - */ -AGESA_STATUS -AmdLatePlatformConfigInit ( - IN OUT PLATFORM_CONFIGURATION *PlatformConfig, - IN OUT AMD_CONFIG_PARAMS *StdHeader - ) -{ - CommonPlatformConfigInit (PlatformConfig, StdHeader); - - return AGESA_SUCCESS; -} - -/* - *--------------------------------------------------------------------------------------- - * - * AmdInitLateInitializer - * - * Initializer routine that will be invoked by the wrapper - * to initialize the input structure for the AmdInitLate - * - * @param[in, out] IN OUT AMD_LATE_PARAMS *LateParamsPtr - * - * @retval AGESA_STATUS - * - *--------------------------------------------------------------------------------------- - */ -AGESA_STATUS -AmdInitLateInitializer ( - IN AMD_CONFIG_PARAMS *StdHeader, - IN OUT AMD_LATE_PARAMS *LateParamsPtr - ) -{ - ASSERT (StdHeader != NULL); - ASSERT (LateParamsPtr != NULL); - - LateParamsPtr->StdHeader = *StdHeader; - - AmdLatePlatformConfigInit (&LateParamsPtr->PlatformConfig, &LateParamsPtr->StdHeader); - - LateParamsPtr->AcpiSlit = NULL; - - LateParamsPtr->AcpiSrat = NULL; - - LateParamsPtr->AcpiWheaMce = NULL; - LateParamsPtr->AcpiWheaCmc = NULL; - - LateParamsPtr->AcpiPState = NULL; - - LateParamsPtr->DmiTable = NULL; - - LateParamsPtr->AcpiAlib = NULL; - - return AGESA_SUCCESS; -} - -/* - *--------------------------------------------------------------------------------------- - * - * AmdInitLateDestructor - * - * Destruct routine that provide a chance if something need to be done - * before the end of AmdInitLate. - * - * @param[in] StdHeader The standard header. - * @param[in] LateParamsPtr AMD init late param. - * - * @retval AGESA_STATUS - * - *--------------------------------------------------------------------------------------- - */ -AGESA_STATUS -AmdInitLateDestructor ( - IN AMD_CONFIG_PARAMS *StdHeader, - IN AMD_LATE_PARAMS *LateParamsPtr - ) -{ - - ASSERT (LateParamsPtr != NULL); - - (*(OptionDmiConfiguration.DmiReleaseBuffer)) (StdHeader); - (*(OptionSlitConfiguration.SlitReleaseBuffer)) (StdHeader); - - return AGESA_SUCCESS; -} - -/*---------------------------------------------------------------------------------------*/ -/** - * Main entry point for the AMD_INIT_LATE function. - * - * This entry point is responsible for creating any desired ACPI tables, providing - * information for DMI, and to prepare the processors for the operating system - * bootstrap load process. - * - * @param[in,out] LateParams Required input parameters for the AMD_INIT_LATE - * entry point. - * - * @return Aggregated status across all internal AMD late calls invoked. - * - */ -AGESA_STATUS -AmdInitLate ( - IN OUT AMD_LATE_PARAMS *LateParams - ) -{ - AGESA_STATUS AgesaStatus; - AGESA_STATUS AmdInitLateStatus; - IDS_HDT_CONSOLE (MAIN_FLOW, "AmdInitLate: Start\n\n"); - AGESA_TESTPOINT (TpIfAmdInitLateEntry, &LateParams->StdHeader); - IDS_PERF_TIME_MEASURE (&LateParams->StdHeader); - - ASSERT (LateParams != NULL); - AmdInitLateStatus = AGESA_SUCCESS; - - IDS_OPTION_HOOK (IDS_INIT_LATE_BEFORE, LateParams, &LateParams->StdHeader); - - IDS_HDT_CONSOLE (MAIN_FLOW, "CreatSystemTable: Start\n"); - // _PSS, XPSS, _PCT, _PSD, _PPC, _CST, _CSD Tables - if ((LateParams->PlatformConfig.UserOptionPState) || (IsFeatureEnabled (IoCstate, &LateParams->PlatformConfig, &LateParams->StdHeader))) { - AgesaStatus = ((*(OptionPstateLateConfiguration.SsdtFeature)) (&LateParams->StdHeader, &LateParams->PlatformConfig, &LateParams->AcpiPState)); - if (AgesaStatus > AmdInitLateStatus) { - AmdInitLateStatus = AgesaStatus; - } - } - - // SRAT Table Generation - if (LateParams->PlatformConfig.UserOptionSrat) { - AgesaStatus = CreateAcpiSrat (&LateParams->StdHeader, &LateParams->AcpiSrat); - if (AgesaStatus > AmdInitLateStatus) { - AmdInitLateStatus = AgesaStatus; - } - } - - // SLIT Table Generation - if (LateParams->PlatformConfig.UserOptionSlit) { - AgesaStatus = CreateAcpiSlit (&LateParams->StdHeader, &LateParams->PlatformConfig, &LateParams->AcpiSlit); - if (AgesaStatus > AmdInitLateStatus) { - AmdInitLateStatus = AgesaStatus; - } - } - - // WHEA Table Generation - if (LateParams->PlatformConfig.UserOptionWhea) { - AgesaStatus = CreateAcpiWhea (&LateParams->StdHeader, &LateParams->AcpiWheaMce, &LateParams->AcpiWheaCmc); - if (AgesaStatus > AmdInitLateStatus) { - AmdInitLateStatus = AgesaStatus; - } - } - - // DMI Table Generation - if (LateParams->PlatformConfig.UserOptionDmi) { - AgesaStatus = CreateDmiRecords (&LateParams->StdHeader, &LateParams->DmiTable); - if (AgesaStatus > AmdInitLateStatus) { - AmdInitLateStatus = AgesaStatus; - } - } - IDS_HDT_CONSOLE (MAIN_FLOW, "CreatSystemTable: End\n"); - - // Cpu Features - IDS_HDT_CONSOLE (MAIN_FLOW, "DispatchCpuFeatures: LateStart\n"); - AgesaStatus = DispatchCpuFeatures (CPU_FEAT_INIT_LATE_END, &LateParams->PlatformConfig, &LateParams->StdHeader); - IDS_HDT_CONSOLE (MAIN_FLOW, "DispatchCpuFeatures: LateEnd\n"); - if (AgesaStatus > AmdInitLateStatus) { - AmdInitLateStatus = AgesaStatus; - } - - // It is the last function run by the AGESA CPU module and prepares the processor - // for the operating system bootstrap load process. - IDS_HDT_CONSOLE (MAIN_FLOW, "AmdCpuLate: Start\n"); - AgesaStatus = AmdCpuLate (&LateParams->StdHeader); - IDS_HDT_CONSOLE (MAIN_FLOW, "AmdCpuLate: End\n"); - if (AgesaStatus > AmdInitLateStatus) { - AmdInitLateStatus = AgesaStatus; - } - - AgesaStatus = GnbInitAtLate (LateParams); - if (AgesaStatus > AmdInitLateStatus) { - AmdInitLateStatus = AgesaStatus; - } - - IDS_OPTION_HOOK (IDS_INIT_LATE_AFTER, LateParams, &LateParams->StdHeader); - - IDS_OPTION_HOOK (IDS_BEFORE_OS, LateParams, &LateParams->StdHeader); - IDS_PERF_TIME_MEASURE (&LateParams->StdHeader); - AGESA_TESTPOINT (TpIfAmdInitLateExit, &LateParams->StdHeader); - IDS_HDT_CONSOLE (MAIN_FLOW, "\nAmdInitLate: End\n\n"); - AGESA_TESTPOINT (EndAgesaTps, &LateParams->StdHeader); -//End Debug Print Service - IDS_HDT_CONSOLE_EXIT (&LateParams->StdHeader); - return AmdInitLateStatus; -} - diff --git a/src/vendorcode/amd/agesa/f12/Proc/Common/AmdInitMid.c b/src/vendorcode/amd/agesa/f12/Proc/Common/AmdInitMid.c deleted file mode 100644 index 4ec3f7dd51..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/Common/AmdInitMid.c +++ /dev/null @@ -1,169 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * AMD AGESA Basic Level Public APIs - * - * Contains basic Level Initialization routines. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: Interface - * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $ - * - */ -/***************************************************************************** - * - * Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - ****************************************************************************** - */ - - -/*---------------------------------------------------------------------------------------- - * M O D U L E S U S E D - *---------------------------------------------------------------------------------------- - */ -#include "AGESA.h" -#include "Ids.h" -#include "cpuFeatures.h" -#include "CommonInits.h" -#include "GnbInterface.h" -#include "AmdFch.h" -#include "heapManager.h" -#include "CreateStruct.h" -#include "Filecode.h" -CODE_GROUP (G1_PEICC) -RDATA_GROUP (G1_PEICC) - -#define FILECODE PROC_COMMON_AMDINITMID_FILECODE - -extern BLDOPT_FCH_FUNCTION BldoptFchFunction; - -/*---------------------------------------------------------------------------------------- - * D E F I N I T I O N S A N D M A C R O S - *---------------------------------------------------------------------------------------- - */ - - -/*---------------------------------------------------------------------------------------- - * T Y P E D E F S A N D S T R U C T U R E S - *---------------------------------------------------------------------------------------- - */ - - -/*---------------------------------------------------------------------------------------- - * P R O T O T Y P E S O F L O C A L F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ - - -/*---------------------------------------------------------------------------------------- - * E X P O R T E D F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ -/* - *--------------------------------------------------------------------------------------- - * - * Initializer routine that will be invoked by the wrapper - * to initialize the input structure for the AmdInitMid - * - * @param[in,out] MidParamsPtr Newly created interface parameters for AmdInitMid - * - * @retval AGESA_SUCCESS Always succeeds - * - *--------------------------------------------------------------------------------------- - */ -AGESA_STATUS -AmdInitMidInitializer ( - IN AMD_CONFIG_PARAMS *StdHeader, - IN OUT AMD_MID_PARAMS *MidParamsPtr - ) -{ - ASSERT (StdHeader != NULL); - ASSERT (MidParamsPtr != NULL); - - MidParamsPtr->StdHeader = *StdHeader; - CommonPlatformConfigInit (&MidParamsPtr->PlatformConfig, &MidParamsPtr->StdHeader); - BldoptFchFunction.InitMidConstructor (MidParamsPtr); - - return AGESA_SUCCESS; -} - - -/*---------------------------------------------------------------------------------------*/ -/** - * Main entry point for the AMD_INIT_MID function. - * - * This entry point is responsible for performing any necessary functions needed - * after PCI bus enumeration and just before control is passed to the video option ROM. - * - * @param[in,out] MidParams Required input parameters for the AMD_INIT_MID - * entry point. - * - * @return Aggregated status across all internal AMD mid calls invoked. - * - */ -AGESA_STATUS -AmdInitMid ( - IN OUT AMD_MID_PARAMS *MidParams - ) -{ - AGESA_STATUS AgesaStatus; - AGESA_STATUS CalledStatus; - IDS_HDT_CONSOLE (MAIN_FLOW, "AmdInitMid: Start\n\n"); - AGESA_TESTPOINT (TpIfAmdInitMidEntry, &MidParams->StdHeader); - IDS_PERF_TIME_MEASURE (&MidParams->StdHeader); - - AgesaStatus = AGESA_SUCCESS; - - ASSERT (MidParams != NULL); - IDS_OPTION_HOOK (IDS_INIT_MID_BEFORE, MidParams, &MidParams->StdHeader); - - IDS_HDT_CONSOLE (MAIN_FLOW, "DispatchCpuFeatures: MidStart\n"); - CalledStatus = DispatchCpuFeatures (CPU_FEAT_INIT_MID_END, &MidParams->PlatformConfig, &MidParams->StdHeader); - IDS_HDT_CONSOLE (MAIN_FLOW, "DispatchCpuFeatures: MidEnd\n"); - if (CalledStatus > AgesaStatus) { - AgesaStatus = CalledStatus; - } - - CalledStatus = BldoptFchFunction.InitMid (MidParams); - AgesaStatus = (CalledStatus > AgesaStatus) ? CalledStatus : AgesaStatus; - - CalledStatus = GnbInitAtMid (MidParams); - if (CalledStatus > AgesaStatus) { - AgesaStatus = CalledStatus; - } - - IDS_OPTION_HOOK (IDS_INIT_MID_AFTER, MidParams, &MidParams->StdHeader); - - IDS_PERF_TIME_MEASURE (&MidParams->StdHeader); - AGESA_TESTPOINT (TpIfAmdInitMidExit, &MidParams->StdHeader); - IDS_HDT_CONSOLE (MAIN_FLOW, "\nAmdInitMid: End\n\n"); - IDS_HDT_CONSOLE_FLUSH_BUFFER (&MidParams->StdHeader); - return AgesaStatus; -} - - diff --git a/src/vendorcode/amd/agesa/f12/Proc/Common/AmdInitPost.c b/src/vendorcode/amd/agesa/f12/Proc/Common/AmdInitPost.c deleted file mode 100644 index 23fa60601d..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/Common/AmdInitPost.c +++ /dev/null @@ -1,343 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * AMD AGESA Basic Level Public APIs - * - * Contains basic Level Initialization routines. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: Interface - * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $ - * - */ -/***************************************************************************** - * - * Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - ****************************************************************************** - */ - - -/*---------------------------------------------------------------------------------------- - * M O D U L E S U S E D - *---------------------------------------------------------------------------------------- - */ -#include "AGESA.h" -#include "amdlib.h" -#include "mm.h" -#include "Ids.h" -#include "cpuRegisters.h" -#include "cpuPostInit.h" -#include "AdvancedApi.h" -#include "heapManager.h" -#include "CommonInits.h" -#include "cpuServices.h" -#include "GnbInterface.h" -#include "CreateStruct.h" -#include "Filecode.h" -CODE_GROUP (G1_PEICC) -RDATA_GROUP (G1_PEICC) - -#define FILECODE PROC_COMMON_AMDINITPOST_FILECODE -/*---------------------------------------------------------------------------------------- - * D E F I N I T I O N S A N D M A C R O S - *---------------------------------------------------------------------------------------- - */ - - -/*---------------------------------------------------------------------------------------- - * T Y P E D E F S A N D S T R U C T U R E S - *---------------------------------------------------------------------------------------- - */ - - -/*---------------------------------------------------------------------------------------- - * P R O T O T Y P E S O F L O C A L F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ -AGESA_STATUS -AmdPostPlatformConfigInit ( - IN OUT PLATFORM_CONFIGURATION *PlatformConfig, - IN OUT AMD_CONFIG_PARAMS *StdHeader - ); - - -/*---------------------------------------------------------------------------------------- - * E X P O R T E D F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ - -extern BUILD_OPT_CFG UserOptions; - -/*------------------------------------------------------------------------------------*/ -/** - * Initialize AmdInitPost stage platform profile and user option input. - * - * @param[in,out] PlatformConfig Platform profile/build option config structure - * @param[in,out] StdHeader AMD standard header config param - * - * @retval AGESA_SUCCESS Always Succeeds. - * - */ -AGESA_STATUS -AmdPostPlatformConfigInit ( - IN OUT PLATFORM_CONFIGURATION *PlatformConfig, - IN OUT AMD_CONFIG_PARAMS *StdHeader - ) -{ - CommonPlatformConfigInit (PlatformConfig, StdHeader); - - return AGESA_SUCCESS; -} - -/* - *--------------------------------------------------------------------------------------- - * - * AmdInitPostInitializer - * - * Initializer routine that will be invoked by the wrapper - * to initialize the input structure for the AmdInitPost - * - * @param[in, out] IN OUT AMD_POST_PARAMS *PostParamsPtr - * - * @retval AGESA_STATUS - * - *--------------------------------------------------------------------------------------- - */ -AGESA_STATUS -AmdInitPostInitializer ( - IN AMD_CONFIG_PARAMS *StdHeader, - IN OUT AMD_POST_PARAMS *PostParamsPtr - ) -{ - AGESA_STATUS AgesaStatus; - ALLOCATE_HEAP_PARAMS AllocHeapParams; - - ASSERT (StdHeader != NULL); - ASSERT (PostParamsPtr != NULL); - - PostParamsPtr->StdHeader = *StdHeader; - - AllocHeapParams.RequestedBufferSize = sizeof (MEM_DATA_STRUCT); - AllocHeapParams.BufferHandle = AMD_MEM_DATA_HANDLE; - AllocHeapParams.Persist = HEAP_LOCAL_CACHE; - AgesaStatus = HeapAllocateBuffer (&AllocHeapParams, &PostParamsPtr->StdHeader); - - if (AgesaStatus == AGESA_SUCCESS) { - PostParamsPtr->MemConfig.MemData = (MEM_DATA_STRUCT *) AllocHeapParams.BufferPtr; - PostParamsPtr->MemConfig.MemData->ParameterListPtr = &(PostParamsPtr->MemConfig); - PostParamsPtr->MemConfig.MemData->StdHeader = PostParamsPtr->StdHeader; - AmdPostPlatformConfigInit (&PostParamsPtr->PlatformConfig, &PostParamsPtr->StdHeader); - AmdMemInitDataStructDef (PostParamsPtr->MemConfig.MemData, &PostParamsPtr->PlatformConfig); - } - return AgesaStatus; -} - -/* - *--------------------------------------------------------------------------------------- - * - * AmdInitPostDestructor - * - * Destruct routine that provide a chance if something need to be done - * before the end of AmdInitPost. - * - * @param[in] StdHeader The standard header. - * @param[in] PostParamsPtr AMD init post param. - * - * @retval AGESA_STATUS - * - *--------------------------------------------------------------------------------------- - */ -AGESA_STATUS -AmdInitPostDestructor ( - IN AMD_CONFIG_PARAMS *StdHeader, - IN AMD_POST_PARAMS *PostParamsPtr - ) -{ - - ASSERT (PostParamsPtr != NULL); - - PostParamsPtr->StdHeader = *StdHeader; - PostParamsPtr->MemConfig.MemData->StdHeader = *StdHeader; - - // - // AmdMemAuto completed. Here, release heap space which is used for memory init. - // - MemAmdFinalize (PostParamsPtr->MemConfig.MemData); - HeapDeallocateBuffer (AMD_MEM_DATA_HANDLE, StdHeader); - - // - // AmdCpuPost completed. - // - if (PostParamsPtr->MemConfig.SysLimit != 0) { - // WBINVD can only be executed when memory is available - FinalizeAtPost (StdHeader); - } - - return AGESA_SUCCESS; -} - -/*---------------------------------------------------------------------------------------*/ -/** - * Main entry point for the AMD_INIT_POST function. - * - * This entry point is responsible for initializing all system memory, - * gathering important data out of the pre-memory cache storage into a - * temporary holding buffer in main memory. After that APs will be - * shutdown in preparation for the host environment to take control. - * Note: pre-memory stack will be disabled also. - * - * @param[in,out] PostParams Required input parameters for the AMD_INIT_POST - * entry point. - * - * @return Aggregated status across all internal AMD POST calls invoked. - * - */ -AGESA_STATUS -AmdInitPost ( - IN OUT AMD_POST_PARAMS *PostParams - ) -{ - AGESA_STATUS AgesaStatus; - AGESA_STATUS AmdInitPostStatus; - WARM_RESET_REQUEST Request; - UINT8 PrevRequestBit; - UINT8 PrevStateBits; - - AGESA_TESTPOINT (TpIfAmdInitPostEntry, &PostParams->StdHeader); - IDS_HDT_CONSOLE (MAIN_FLOW, "AmdInitPost: Start\n\n"); - IDS_PERF_TIME_MEASURE (&PostParams->StdHeader); - - ASSERT (PostParams != NULL); - AmdInitPostStatus = AGESA_SUCCESS; - PrevRequestBit = FALSE; - PrevStateBits = WR_STATE_COLD; - - IDS_OPTION_HOOK (IDS_INIT_POST_BEFORE, PostParams, &PostParams->StdHeader); - - IDS_OPTION_HOOK (IDS_BEFORE_MEM_INIT, PostParams, &PostParams->StdHeader); - - // If a previously requested warm reset cannot be triggered in the - // current stage, store the previous state of request and reset the - // request struct to the current post stage - GetWarmResetFlag (&PostParams->StdHeader, &Request); - if (Request.RequestBit == TRUE) { - if (Request.StateBits >= Request.PostStage) { - PrevRequestBit = Request.RequestBit; - PrevStateBits = Request.StateBits; - Request.RequestBit = FALSE; - Request.StateBits = Request.PostStage - 1; - SetWarmResetFlag (&PostParams->StdHeader, &Request); - } - } - - AgesaStatus = GnbInitAtPost (PostParams); - if (AgesaStatus > AmdInitPostStatus) { - AmdInitPostStatus = AgesaStatus; - } - - IDS_HDT_CONSOLE (MAIN_FLOW, "AmdMemAuto: Start\n"); - AgesaStatus = AmdMemAuto (PostParams->MemConfig.MemData); - IDS_HDT_CONSOLE (MAIN_FLOW, "AmdMemAuto: End\n"); - if (AgesaStatus > AmdInitPostStatus) { - AmdInitPostStatus = AgesaStatus; - } - - if (AgesaStatus != AGESA_FATAL) { - - IDS_OPTION_HOOK (IDS_INIT_POST_MID, PostParams, &PostParams->StdHeader); - - // Check BIST status - AgesaStatus = CheckBistStatus (&PostParams->StdHeader); - if (AgesaStatus > AmdInitPostStatus) { - AmdInitPostStatus = AgesaStatus; - } - - // - // P-State data gathered, then, Relinquish APs - // - IDS_HDT_CONSOLE (MAIN_FLOW, "AmdCpuPost: Start\n"); - AgesaStatus = AmdCpuPost (&PostParams->StdHeader, &PostParams->PlatformConfig); - IDS_HDT_CONSOLE (MAIN_FLOW, "AmdCpuPost: End\n"); - if (AgesaStatus > AmdInitPostStatus) { - AmdInitPostStatus = AgesaStatus; - } - - // Warm Reset - GetWarmResetFlag (&PostParams->StdHeader, &Request); - // If a warm reset is requested in the current post stage, trigger the - // warm reset and ignore the previous request - if (Request.RequestBit == TRUE) { - if (Request.StateBits < Request.PostStage) { - AgesaDoReset (WARM_RESET_WHENEVER, &PostParams->StdHeader); - } - } else { - // Otherwise, if there's a previous request, restore it - // so that the subsequent post stage can trigger the warm reset - if (PrevRequestBit == TRUE) { - Request.RequestBit = PrevRequestBit; - Request.StateBits = PrevStateBits; - SetWarmResetFlag (&PostParams->StdHeader, &Request); - } - } - - AgesaStatus = GnbInitAtPostAfterDram (PostParams); - if (AgesaStatus > AmdInitPostStatus) { - AmdInitPostStatus = AgesaStatus; - } - - IDS_OPTION_HOOK (IDS_INIT_POST_AFTER, PostParams, &PostParams->StdHeader); - - IDS_PERF_TIME_MEASURE (&PostParams->StdHeader); - AGESA_TESTPOINT (TpIfAmdInitPostExit, &PostParams->StdHeader); - IDS_HDT_CONSOLE (MAIN_FLOW, "\nAmdInitPost: End\n\n"); - IDS_HDT_CONSOLE (MAIN_FLOW, "Heap transfer Start ...\n\n"); - - //For Heap will be relocate to new address in next stage, flush out debug print buffer if needed - IDS_HDT_CONSOLE_FLUSH_BUFFER (&PostParams->StdHeader); - - // WARNING: IDT will be moved from local cache to temp memory, so restore IDTR for BSP here -// IDS_EXCEPTION_TRAP (IDS_IDT_RESTORE_IDTR_FOR_BSC, NULL, &PostParams->StdHeader); - // Copies BSP heap content to RAM, and it should be at the end of AmdInitPost - AgesaStatus = CopyHeapToTempRamAtPost (&(PostParams->StdHeader)); - if (AgesaStatus > AmdInitPostStatus) { - AmdInitPostStatus = AgesaStatus; - } - PostParams->StdHeader.HeapStatus = HEAP_TEMP_MEM; - } - // Check for Cache As Ram Corruption - IDS_CAR_CORRUPTION_CHECK (&PostParams->StdHeader); - - // At the end of AmdInitPost, set StateBits to POST to allow any warm reset that occurs outside - // of AGESA to be recognized by IsWarmReset() - GetWarmResetFlag (&PostParams->StdHeader, &Request); - Request.StateBits = Request.PostStage; - SetWarmResetFlag (&PostParams->StdHeader, &Request); - - return AmdInitPostStatus; -} - diff --git a/src/vendorcode/amd/agesa/f12/Proc/Common/AmdInitReset.c b/src/vendorcode/amd/agesa/f12/Proc/Common/AmdInitReset.c deleted file mode 100644 index 27eae0e2ba..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/Common/AmdInitReset.c +++ /dev/null @@ -1,255 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * AMD AGESA Basic Level Public APIs - * - * Contains basic Level Initialization routines. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: Interface - * @e \$Revision: 46017 $ @e \$Date: 2011-01-27 04:09:42 +0800 (Thu, 27 Jan 2011) $ - * - */ -/***************************************************************************** - * - * Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - ****************************************************************************** - */ - - -/*---------------------------------------------------------------------------------------- - * M O D U L E S U S E D - *---------------------------------------------------------------------------------------- - */ -#include "AGESA.h" -#include "amdlib.h" -#include "Ids.h" -#include "cpuCacheInit.h" -#include "cpuRegisters.h" -#include "cpuServices.h" -#include "AdvancedApi.h" -#include "GeneralServices.h" -#include "OptionsHt.h" -#include "AmdFch.h" -#include "Filecode.h" -#include "heapManager.h" -#include "CreateStruct.h" -CODE_GROUP (G1_PEICC) -RDATA_GROUP (G1_PEICC) - -#define FILECODE PROC_COMMON_AMDINITRESET_FILECODE - -extern BLDOPT_FCH_FUNCTION BldoptFchFunction; - -/*---------------------------------------------------------------------------------------- - * D E F I N I T I O N S A N D M A C R O S - *---------------------------------------------------------------------------------------- - */ -extern CONST OPTION_HT_INIT_RESET HtOptionInitReset; -extern BUILD_OPT_CFG UserOptions; - -/*---------------------------------------------------------------------------------------- - * T Y P E D E F S A N D S T R U C T U R E S - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------- - * P R O T O T Y P E S O F L O C A L F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ -AGESA_STATUS -AmdInitResetExecutionCacheAllocateInitializer ( - IN AMD_CONFIG_PARAMS *StdHeader, - IN EXECUTION_CACHE_REGION *AmdExeAddrMapPtr - ); - - -/*---------------------------------------------------------------------------------------- - * E X P O R T E D F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ - -/*------------------------------------------------------------------------------------*/ -/** - * Initializer routine that will be invoked by the wrapper to initialize the input - * structure for the AllocateExecutionCache. - * - * Parameters: - * @param[in] StdHeader Opaque handle to standard config header - * @param[in] AmdExeAddrMapPtr Our Service interface struct - * - * @retval AGESA_SUCCESS Always Succeeds. - * - */ -AGESA_STATUS -AmdInitResetExecutionCacheAllocateInitializer ( - IN AMD_CONFIG_PARAMS *StdHeader, - IN EXECUTION_CACHE_REGION *AmdExeAddrMapPtr - ) -{ - ASSERT (AmdExeAddrMapPtr != NULL); - - LibAmdMemFill (AmdExeAddrMapPtr, 0, sizeof (EXECUTION_CACHE_REGION) * MAX_CACHE_REGIONS, StdHeader); - - return AGESA_SUCCESS; -} -/*---------------------------------------------------------------------------------------*/ -/** - * Main entry point for the AMD_INIT_RESET function. - * - * This entry point is responsible for establishing the HT links to the program - * ROM and for performing basic processor initialization. - * - * @param[in,out] ResetParams Required input parameters for the AMD_INIT_RESET - * entry point. - * - * @return Aggregated status across all internal AMD reset calls invoked. - * - */ -AGESA_STATUS -AmdInitReset ( - IN OUT AMD_RESET_PARAMS *ResetParams - ) -{ - AGESA_STATUS AgesaStatus; - AGESA_STATUS CalledAgesaStatus; - WARM_RESET_REQUEST Request; - UINT8 PrevRequestBit; - UINT8 PrevStateBits; - - AgesaStatus = AGESA_SUCCESS; - - // Init Debug Print function - IDS_HDT_CONSOLE_INIT (&ResetParams->StdHeader); - - IDS_HDT_CONSOLE (MAIN_FLOW, "\nAmdInitReset: Start\n\n"); - - // Setup ROM execution cache - IDS_HDT_CONSOLE (MAIN_FLOW, "AllocateExecutionCache: Start\n"); - CalledAgesaStatus = AllocateExecutionCache (&ResetParams->StdHeader, &ResetParams->CacheRegion[0]); - IDS_HDT_CONSOLE (MAIN_FLOW, "AllocateExecutionCache: End\n"); - if (CalledAgesaStatus > AgesaStatus) { - AgesaStatus = CalledAgesaStatus; - } - -// IDS_EXTENDED_HOOK (IDS_INIT_RESET_BEFORE, NULL, NULL, &ResetParams->StdHeader); - - IDS_HDT_CONSOLE (MAIN_FLOW, "\n*** %s ***\n\n", &UserOptions.VersionString); - - AGESA_TESTPOINT (TpIfAmdInitResetEntry, &ResetParams->StdHeader); - ASSERT (ResetParams != NULL); - - PrevRequestBit = FALSE; - PrevStateBits = WR_STATE_COLD; - - if (IsBsp (&ResetParams->StdHeader, &AgesaStatus)) { - CalledAgesaStatus = BldoptFchFunction.InitReset (ResetParams); - AgesaStatus = (CalledAgesaStatus > AgesaStatus) ? CalledAgesaStatus : AgesaStatus; - } - - // If a previously requested warm reset cannot be triggered in the - // current stage, store the previous state of request and reset the - // request struct to the current post stage - GetWarmResetFlag (&ResetParams->StdHeader, &Request); - if (Request.RequestBit == TRUE) { - if (Request.StateBits >= Request.PostStage) { - PrevRequestBit = Request.RequestBit; - PrevStateBits = Request.StateBits; - Request.RequestBit = FALSE; - Request.StateBits = Request.PostStage - 1; - SetWarmResetFlag (&ResetParams->StdHeader, &Request); - } - } - - // Initialize the PCI MMIO access mechanism - InitializePciMmio (&ResetParams->StdHeader); - - // Initialize Hyper Transport Registers - if (HtOptionInitReset.HtInitReset != NULL) { - IDS_HDT_CONSOLE (MAIN_FLOW, "HtInitReset: Start\n"); - CalledAgesaStatus = HtOptionInitReset.HtInitReset (&ResetParams->StdHeader, &ResetParams->HtConfig); - IDS_HDT_CONSOLE (MAIN_FLOW, "HtInitReset: End\n"); - if (CalledAgesaStatus > AgesaStatus) { - AgesaStatus = CalledAgesaStatus; - } - } - - // Warm Reset, should be at the end of AmdInitReset - GetWarmResetFlag (&ResetParams->StdHeader, &Request); - // If a warm reset is requested in the current post stage, trigger the - // warm reset and ignore the previous request - if (Request.RequestBit == TRUE) { - if (Request.StateBits < Request.PostStage) { - AgesaDoReset (WARM_RESET_WHENEVER, &ResetParams->StdHeader); - } - } else { - // Otherwise, if there's a previous request, restore it - // so that the subsequent post stage can trigger the warm reset - if (PrevRequestBit == TRUE) { - Request.RequestBit = PrevRequestBit; - Request.StateBits = PrevStateBits; - SetWarmResetFlag (&ResetParams->StdHeader, &Request); - } - } - // Check for Cache As Ram Corruption - IDS_CAR_CORRUPTION_CHECK (&ResetParams->StdHeader); - IDS_HDT_CONSOLE (MAIN_FLOW, "\nAmdInitReset: End\n\n"); - - AGESA_TESTPOINT (TpIfAmdInitResetExit, &ResetParams->StdHeader); - return AgesaStatus; -} - -/*---------------------------------------------------------------------------------------*/ -/** - * Initialize defaults and options for Amd Init Reset. - * - * @param[in] StdHeader Header - * @param[in] AmdResetParams The Reset Init interface to initialize. - * - * @retval AGESA_SUCCESS Always Succeeds. - */ -AGESA_STATUS -AmdInitResetConstructor ( - IN AMD_CONFIG_PARAMS *StdHeader, - IN AMD_RESET_PARAMS *AmdResetParams - ) -{ - ASSERT (AmdResetParams != NULL); - - AmdResetParams->StdHeader = *StdHeader; - - AmdInitResetExecutionCacheAllocateInitializer (&AmdResetParams->StdHeader, &AmdResetParams->CacheRegion[0]); - // Initialize Hyper Transport input structure - if (HtOptionInitReset.HtResetConstructor != NULL) { - HtOptionInitReset.HtResetConstructor (&AmdResetParams->StdHeader, &AmdResetParams->HtConfig); - } - BldoptFchFunction.InitResetConstructor (AmdResetParams); - - return AGESA_SUCCESS; -} - diff --git a/src/vendorcode/amd/agesa/f12/Proc/Common/AmdInitResume.c b/src/vendorcode/amd/agesa/f12/Proc/Common/AmdInitResume.c deleted file mode 100644 index 663f07e7cc..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/Common/AmdInitResume.c +++ /dev/null @@ -1,238 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * AMD AGESA Basic Level Public APIs - * - * Contains basic Level Initialization routines. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: Interface - * @e \$Revision: 45707 $ @e \$Date: 2011-01-20 17:48:52 +0800 (Thu, 20 Jan 2011) $ - * - */ -/***************************************************************************** - * - * Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - ****************************************************************************** - */ - - -/*---------------------------------------------------------------------------------------- - * M O D U L E S U S E D - *---------------------------------------------------------------------------------------- - */ -#include "AGESA.h" -#include "amdlib.h" -#include "Ids.h" -#include "mm.h" -#include "mn.h" -#include "S3.h" -#include "mfs3.h" -#include "Filecode.h" -#include "cpuRegisters.h" -#include "cpuApicUtilities.h" -#include "cpuPostInit.h" -#include "CommonInits.h" -#include "heapManager.h" -#include "CreateStruct.h" -#include "cpuFeatures.h" -CODE_GROUP (G1_PEICC) -RDATA_GROUP (G1_PEICC) - -#define FILECODE PROC_COMMON_AMDINITRESUME_FILECODE -/*---------------------------------------------------------------------------------------- - * D E F I N I T I O N S A N D M A C R O S - *---------------------------------------------------------------------------------------- - */ - - -/*---------------------------------------------------------------------------------------- - * T Y P E D E F S A N D S T R U C T U R E S - *---------------------------------------------------------------------------------------- - */ - - -/*---------------------------------------------------------------------------------------- - * P R O T O T Y P E S O F L O C A L F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ - - -/*---------------------------------------------------------------------------------------- - * E X P O R T E D F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------*/ -/** - * Main entry point for the AMD_INIT_RESUME function. - * - * This entry point is responsible for performing silicon device and memory - * re-initialization for the resume boot path. - * - * @param[in] ResumeParams Required input parameters for the AMD_INIT_RESUME - * entry point. - * - * @return Aggregated status across all internal AMD resume calls invoked. - * - */ -AGESA_STATUS -AmdInitResume ( - IN AMD_RESUME_PARAMS *ResumeParams - ) -{ - VOID *OrMaskPtr; - AGESA_STATUS ReturnStatus; - AGESA_STATUS AmdInitResumeStatus; - BSC_AP_MSR_SYNC ApMsrSync[4]; - - AGESA_TESTPOINT (TpIfAmdInitResumeEntry, &ResumeParams->StdHeader); - IDS_HDT_CONSOLE (MAIN_FLOW, "AmdInitResume Start\n"); - - AmdInitResumeStatus = AGESA_SUCCESS; - - ASSERT (ResumeParams != NULL); - - if (ResumeParams->S3DataBlock.NvStorage != NULL) { - - MemS3ResumeInitNB (&ResumeParams->StdHeader); - - // Restore registers before exiting self refresh - RestorePreESRContext (&OrMaskPtr, - ResumeParams->S3DataBlock.NvStorage, - INIT_RESUME, - &ResumeParams->StdHeader); - // Exit self refresh - ReturnStatus = AmdMemS3Resume (&ResumeParams->StdHeader); - if (ReturnStatus > AmdInitResumeStatus) { - AmdInitResumeStatus = ReturnStatus; - } - if (ReturnStatus == AGESA_SUCCESS) { - - // Restore registers after exiting self refresh - RestorePostESRContext (OrMaskPtr, - ResumeParams->S3DataBlock.NvStorage, - INIT_RESUME, - &ResumeParams->StdHeader); - - ApMsrSync[0].RegisterAddress = SYS_CFG; - ApMsrSync[1].RegisterAddress = TOP_MEM; - ApMsrSync[2].RegisterAddress = TOP_MEM2; - ApMsrSync[3].RegisterAddress = 0; - SyncApMsrsToBsc (ApMsrSync, &ResumeParams->StdHeader); - - IDS_HDT_CONSOLE (CPU_TRACE, " Dispatch CPU features after S3 AP MTRR sync\n"); - ReturnStatus = DispatchCpuFeatures (CPU_FEAT_AFTER_RESUME_MTRR_SYNC, &ResumeParams->PlatformConfig, &ResumeParams->StdHeader); - if (ReturnStatus > AmdInitResumeStatus) { - AmdInitResumeStatus = ReturnStatus; - } - } - } - - // Set TscFreqSel at the rate specified by the core P0 - SetCoresTscFreqSel (&ResumeParams->StdHeader); - - IDS_HDT_CONSOLE (MAIN_FLOW, "AmdInitResume End\n"); - // HDT out of All Aps - IDS_HDT_CONSOLE_FLUSH_BUFFER (&ResumeParams->StdHeader); - // Relinquish control of all APs to IBV - RelinquishControlOfAllAPs (&ResumeParams->StdHeader); - - // Restore IDT -// IDS_EXCEPTION_TRAP (IDS_IDT_RESTORE_IDTR_FOR_BSC, NULL, &ResumeParams->StdHeader); - IDS_OPTION_HOOK (IDS_AFTER_S3_RESUME, NULL, &ResumeParams->StdHeader); - AGESA_TESTPOINT (TpIfAmdInitResumeExit, &ResumeParams->StdHeader); - return (AmdInitResumeStatus); -} - -/*---------------------------------------------------------------------------------------*/ -/** - * Constructor for the AMD_INIT_RESUME function. - * - * This routine is responsible for setting default values for the - * input parameters needed by the AMD_INIT_RESUME entry point. - * - * @param[in] StdHeader The standard header. - * @param[in,out] ResumeParams Required input parameters for the AMD_INIT_RESUME - * entry point. - * - * @retval AGESA_SUCCESS Always Succeeds. - * - */ -AGESA_STATUS -AmdInitResumeInitializer ( - IN AMD_CONFIG_PARAMS *StdHeader, - IN OUT AMD_RESUME_PARAMS *ResumeParams - ) -{ - ASSERT (StdHeader != NULL); - ASSERT (ResumeParams != NULL); - - ResumeParams->StdHeader = *StdHeader; - - AmdS3ParamsInitializer (&ResumeParams->S3DataBlock); - CommonPlatformConfigInit (&ResumeParams->PlatformConfig, &ResumeParams->StdHeader); - - return AGESA_SUCCESS; -} - -/*---------------------------------------------------------------------------------------*/ -/** - * Destructor for the AMD_INIT_RESUME function. - * - * This routine is responsible for deallocation of heap space allocated during - * AMD_INIT_RESUME entry point. - * - * @param[in] StdHeader The standard header. - * @param[in,out] ResumeParams Required input parameters for the AMD_INIT_RESUME - * entry point. - * - * @retval AGESA_STATUS - * - */ -AGESA_STATUS -AmdInitResumeDestructor ( - IN AMD_CONFIG_PARAMS *StdHeader, - IN OUT AMD_RESUME_PARAMS *ResumeParams - ) -{ - AGESA_STATUS ReturnStatus; - AGESA_STATUS RetVal; - - ASSERT (ResumeParams != NULL); - - ReturnStatus = AGESA_SUCCESS; - - // Deallocate heap space allocated during memory S3 resume - RetVal = MemS3Deallocate (&ResumeParams->StdHeader); - if (RetVal > ReturnStatus) { - ReturnStatus = RetVal; - } - - return ReturnStatus; -} diff --git a/src/vendorcode/amd/agesa/f12/Proc/Common/AmdLateRunApTask.c b/src/vendorcode/amd/agesa/f12/Proc/Common/AmdLateRunApTask.c deleted file mode 100644 index 0bedc9b69b..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/Common/AmdLateRunApTask.c +++ /dev/null @@ -1,159 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * AMD AGESA Basic Level Public APIs - * - * Contains basic Level Initialization routines. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: Interface - * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $ - * - */ -/***************************************************************************** - * - * Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - ****************************************************************************** - */ - - -/*---------------------------------------------------------------------------------------- - * M O D U L E S U S E D - *---------------------------------------------------------------------------------------- - */ -#include "AGESA.h" -#include "Ids.h" -#include "Options.h" -#include "heapManager.h" -#include "CreateStruct.h" -#include "Filecode.h" -CODE_GROUP (G3_DXE) -RDATA_GROUP (G3_DXE) - -#define FILECODE PROC_COMMON_AMDLATERUNAPTASK_FILECODE -/*---------------------------------------------------------------------------------------- - * D E F I N I T I O N S A N D M A C R O S - *---------------------------------------------------------------------------------------- - */ - - -/*---------------------------------------------------------------------------------------- - * T Y P E D E F S A N D S T R U C T U R E S - *---------------------------------------------------------------------------------------- - */ - - -/*---------------------------------------------------------------------------------------- - * P R O T O T Y P E S O F L O C A L F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ - - -/*---------------------------------------------------------------------------------------- - * E X P O R T E D F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ -extern CONST DISPATCH_TABLE ApDispatchTable[]; - -/*---------------------------------------------------------------------------------------*/ -/** - * Application Processor perform a function as directed by the BSC. - * - * This is needed for an AP task that must run after AGESA has relinquished control - * of the APs to the IBV. - * - * @param[in] AmdApExeParams The interface struct for any required routine. - * - * @return The most severe AGESA_STATUS returned by any called service. Note - * that this will be the return value passed back to the BSC as the - * return value for the call out. - * - */ -AGESA_STATUS -AmdLateRunApTask ( - IN AP_EXE_PARAMS *AmdApExeParams - ) -{ - AGESA_STATUS CalledAgesaStatus; - AGESA_STATUS ApLateTaskStatus; - DISPATCH_TABLE *Entry; - - AGESA_TESTPOINT (TpIfAmdLateRunApTaskEntry, &AmdApExeParams->StdHeader); - - ASSERT (AmdApExeParams != NULL); - ApLateTaskStatus = AGESA_SUCCESS; - CalledAgesaStatus = AGESA_UNSUPPORTED; - - // Dispatch, if valid - Entry = (DISPATCH_TABLE *) ApDispatchTable; - while (Entry->FunctionId != 0) { - if (AmdApExeParams->FunctionNumber == Entry->FunctionId) { - CalledAgesaStatus = Entry->EntryPoint (AmdApExeParams); - break; - } - Entry++; - } - - if (CalledAgesaStatus > ApLateTaskStatus) { - ApLateTaskStatus = CalledAgesaStatus; - } - - AGESA_TESTPOINT (TpIfAmdLateRunApTaskExit, &AmdApExeParams->StdHeader); - return ApLateTaskStatus; -} - -/*---------------------------------------------------------------------------------------*/ -/** - * Constructor for the AMD_LATE_RUN_AP_TASK function. - * - * This routine is responsible for setting default values for the - * input parameters needed by the AMD_S3_SAVE entry point. - * - * @param[in] StdHeader The standard header. - * @param[in,out] AmdApExeParams Required input parameters for the AMD_LATE_RUN_AP_TASK - * entry point. - * - * @retval AGESA_SUCCESS Always Succeeds. - * - */ -AGESA_STATUS -AmdLateRunApTaskInitializer ( - IN AMD_CONFIG_PARAMS *StdHeader, - IN OUT AP_EXE_PARAMS *AmdApExeParams - ) -{ - ASSERT (StdHeader != NULL); - ASSERT (AmdApExeParams != NULL); - - AmdApExeParams->StdHeader = *StdHeader; - AmdApExeParams->FunctionNumber = 0; - AmdApExeParams->RelatedDataBlock = NULL; - AmdApExeParams->RelatedBlockLength = 0; - return AGESA_SUCCESS; -} - diff --git a/src/vendorcode/amd/agesa/f12/Proc/Common/AmdS3LateRestore.c b/src/vendorcode/amd/agesa/f12/Proc/Common/AmdS3LateRestore.c deleted file mode 100644 index 419e26fd62..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/Common/AmdS3LateRestore.c +++ /dev/null @@ -1,217 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * AMD AGESA Basic Level Public APIs - * - * Contains basic Level Initialization routines. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: Interface - * @e \$Revision: 46395 $ @e \$Date: 2011-02-01 13:36:45 +0800 (Tue, 01 Feb 2011) $ - * - */ -/***************************************************************************** - * - * Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - ****************************************************************************** - */ - - -/*---------------------------------------------------------------------------------------- - * M O D U L E S U S E D - *---------------------------------------------------------------------------------------- - */ -#include "AGESA.h" -#include "amdlib.h" -#include "Ids.h" -#include "S3.h" -#include "cpuFeatures.h" -#include "heapManager.h" -#include "S3SaveState.h" -#include "CommonInits.h" -#include "CreateStruct.h" -#include "Filecode.h" -CODE_GROUP (G2_PEI) -RDATA_GROUP (G2_PEI) - -#define FILECODE PROC_COMMON_AMDS3LATERESTORE_FILECODE -/*---------------------------------------------------------------------------------------- - * D E F I N I T I O N S A N D M A C R O S - *---------------------------------------------------------------------------------------- - */ - - -/*---------------------------------------------------------------------------------------- - * T Y P E D E F S A N D S T R U C T U R E S - *---------------------------------------------------------------------------------------- - */ - - -/*---------------------------------------------------------------------------------------- - * P R O T O T Y P E S O F L O C A L F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ -AGESA_STATUS -AmdS3LateRestorePlatformConfigInit ( - IN OUT PLATFORM_CONFIGURATION *PlatformConfig, - IN OUT AMD_CONFIG_PARAMS *StdHeader - ); - -/*---------------------------------------------------------------------------------------- - * E X P O R T E D F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ -extern BUILD_OPT_CFG UserOptions; - -/*---------------------------------------------------------------------------------------*/ -/** - * Main entry point for the AMD_S3LATE_RESTORE function. - * - * This entry point is responsible for restoring saved registers and preparing the - * silicon components for OS restart. - * - * @param[in,out] S3LateParams Required input parameters for the AMD_S3LATE_RESTORE - * entry point. - * - * @return Aggregated status across all internal AMD S3 late restore calls invoked. - * - */ -AGESA_STATUS -AmdS3LateRestore ( - IN OUT AMD_S3LATE_PARAMS *S3LateParams - ) -{ - UINT8 *BufferPointer; - VOID *OrMaskPtr; - VOID *LateContextPtr; - AGESA_STATUS ReturnStatus; - AGESA_STATUS CalledStatus; - - AGESA_TESTPOINT (TpIfAmdS3LateRestoreEntry, &S3LateParams->StdHeader); - - ReturnStatus = AGESA_SUCCESS; - - ASSERT (S3LateParams != NULL); - - BufferPointer = (UINT8 *) S3LateParams->S3DataBlock.VolatileStorage; - S3LateParams->StdHeader.HeapBasePtr = (UINT64) (intptr_t) ((UINT8 *)(&BufferPointer[(((S3_VOLATILE_STORAGE_HEADER *) S3LateParams->S3DataBlock.VolatileStorage)->HeapOffset)])); - ASSERT (S3LateParams->StdHeader.HeapBasePtr != 0); - - IDS_HDT_CONSOLE_INIT (&S3LateParams->StdHeader); - IDS_HDT_CONSOLE (MAIN_FLOW, "AmdS3LateRestore: Start\n\n"); - - IDS_OPTION_HOOK (IDS_PLATFORMCFG_OVERRIDE, &S3LateParams->PlatformConfig, &S3LateParams->StdHeader); - IDS_OPTION_HOOK (IDS_BEFORE_S3_RESTORE, S3LateParams, &(S3LateParams->StdHeader)); - - if (((S3_VOLATILE_STORAGE_HEADER *) S3LateParams->S3DataBlock.VolatileStorage)->RegisterDataSize != 0) { - LateContextPtr = &BufferPointer[((S3_VOLATILE_STORAGE_HEADER *) S3LateParams->S3DataBlock.VolatileStorage)->RegisterDataOffset]; - // Restore registers before exiting self refresh - RestorePreESRContext (&OrMaskPtr, - LateContextPtr, - S3_LATE_RESTORE, - &S3LateParams->StdHeader); - // Restore registers after exiting self refresh - RestorePostESRContext (OrMaskPtr, - LateContextPtr, - S3_LATE_RESTORE, - &S3LateParams->StdHeader); - } - - // Dispatch any features needing to run at this time point - IDS_HDT_CONSOLE (CPU_TRACE, " Dispatch CPU features at S3 late restore end\n"); - CalledStatus = DispatchCpuFeatures (CPU_FEAT_S3_LATE_RESTORE_END, - &S3LateParams->PlatformConfig, - &S3LateParams->StdHeader); - if (CalledStatus > ReturnStatus) { - ReturnStatus = CalledStatus; - } - - CalledStatus = S3ScriptRestore (&S3LateParams->StdHeader); - if (CalledStatus > ReturnStatus) { - ReturnStatus = CalledStatus; - } - - IDS_OPTION_HOOK (IDS_AFTER_S3_RESTORE, S3LateParams, &S3LateParams->StdHeader); - AGESA_TESTPOINT (TpIfAmdS3LateRestoreExit, &S3LateParams->StdHeader); - IDS_HDT_CONSOLE (MAIN_FLOW, "\nAmdS3LateRestore: End\n\n"); - IDS_HDT_CONSOLE_S3_EXIT (&S3LateParams->StdHeader); - return ReturnStatus; -} - -/*---------------------------------------------------------------------------------------*/ -/** - * Constructor for the AMD_S3LATE_RESTORE function. - * - * This routine is responsible for setting default values for the - * input parameters needed by the AMD_S3LATE_RESTORE entry point. - * - * @param[in] StdHeader AMD standard header config param. - * @param[in,out] S3LateParams Required input parameters for the - * AMD_S3LATE_RESTORE entry point. - * - * @retval AGESA_SUCCESS Always Succeeds. - * - */ -AGESA_STATUS -AmdS3LateRestoreInitializer ( - IN AMD_CONFIG_PARAMS *StdHeader, - IN OUT AMD_S3LATE_PARAMS *S3LateParams - ) -{ - ASSERT (StdHeader != NULL); - ASSERT (S3LateParams != NULL); - - S3LateParams->StdHeader = *StdHeader; - - AmdS3ParamsInitializer (&S3LateParams->S3DataBlock); - - AmdS3LateRestorePlatformConfigInit (&S3LateParams->PlatformConfig, &S3LateParams->StdHeader); - - return AGESA_SUCCESS; -} - -/*------------------------------------------------------------------------------------*/ -/** - * Initialize AmdS3LateRestore stage platform profile and user option input. - * - * @param[in,out] PlatformConfig Platform profile/build option config structure - * @param[in,out] StdHeader AMD standard header config param - * - * @retval AGESA_SUCCESS Always Succeeds. - * - */ -AGESA_STATUS -AmdS3LateRestorePlatformConfigInit ( - IN OUT PLATFORM_CONFIGURATION *PlatformConfig, - IN OUT AMD_CONFIG_PARAMS *StdHeader - ) -{ - CommonPlatformConfigInit (PlatformConfig, StdHeader); - - return AGESA_SUCCESS; -} diff --git a/src/vendorcode/amd/agesa/f12/Proc/Common/AmdS3Save.c b/src/vendorcode/amd/agesa/f12/Proc/Common/AmdS3Save.c deleted file mode 100644 index 0770c1e5e9..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/Common/AmdS3Save.c +++ /dev/null @@ -1,387 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * AMD AGESA Basic Level Public APIs - * - * Contains basic Level Initialization routines. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: Interface - * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $ - * - */ -/***************************************************************************** - * - * Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - ****************************************************************************** - */ - - -/*---------------------------------------------------------------------------------------- - * M O D U L E S U S E D - *---------------------------------------------------------------------------------------- - */ -#include "AGESA.h" -#include "amdlib.h" -#include "Ids.h" -#include "mm.h" -#include "mn.h" -#include "S3.h" -#include "mfs3.h" -#include "CommonInits.h" -#include "AmdFch.h" -#include "Filecode.h" -#include "heapManager.h" -#include "Topology.h" -#include "CreateStruct.h" -CODE_GROUP (G3_DXE) -RDATA_GROUP (G3_DXE) - -#define FILECODE PROC_COMMON_AMDS3SAVE_FILECODE - -extern BLDOPT_FCH_FUNCTION BldoptFchFunction; - -/*---------------------------------------------------------------------------------------- - * D E F I N I T I O N S A N D M A C R O S - *---------------------------------------------------------------------------------------- - */ - - -/*---------------------------------------------------------------------------------------- - * T Y P E D E F S A N D S T R U C T U R E S - *---------------------------------------------------------------------------------------- - */ -CONST UINT32 ROMDATA S3LateHeapTable[] = -{ - EVENT_LOG_BUFFER_HANDLE, - SOCKET_DIE_MAP_HANDLE, - NODE_ID_MAP_HANDLE, - LOCAL_AP_MAIL_BOX_CACHE_HANDLE, - IDS_CONTROL_HANDLE, - AMD_S3_SCRIPT_SAVE_TABLE_HANDLE, - AMD_PCIE_COMPLEX_DATA_HANDLE -}; - -#define S3LATE_TABLE_SIZE (sizeof (S3LateHeapTable) / sizeof (UINT32)) //(sizeof (S3LateHeapTable) / sizeof (S3LATE_HEAP_ELEMENT)) - - -/*---------------------------------------------------------------------------------------- - * P R O T O T Y P E S O F L O C A L F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ -AGESA_STATUS -AmdS3SavePlatformConfigInit ( - IN OUT PLATFORM_CONFIGURATION *PlatformConfig, - IN OUT AMD_CONFIG_PARAMS *StdHeader - ); - -/*---------------------------------------------------------------------------------------- - * E X P O R T E D F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ -extern BUILD_OPT_CFG UserOptions; - -/*---------------------------------------------------------------------------------------*/ -/** - * Main entry point for the AMD_S3_SAVE function. - * - * This entry point is responsible for saving silicon component registers to the - * SMM save area in preparation of entering system suspend-to-RAM mode. - * - * @param[in,out] AmdS3SaveParams Required input parameters for the AMD_S3_SAVE - * entry point. - * - * @return Aggregated status across all internal AMD S3 save calls invoked. - * - */ -AGESA_STATUS -AmdS3Save ( - IN OUT AMD_S3SAVE_PARAMS *AmdS3SaveParams - ) -{ - UINTN i; - UINT32 EarlyBufferSize; - UINT32 LateBufferSize; - UINT32 LateContextSize; - UINT32 HeapSize; - UINT8 *BufferPointer; - UINT8 HeapStatus; - ALLOCATE_HEAP_PARAMS HeapParams; - LOCATE_HEAP_PTR LocateHeap; - BUFFER_NODE *FreeSpaceNode; - ALLOCATE_HEAP_PARAMS AllocParams; - DEVICE_BLOCK_HEADER *MemoryRelatedDeviceList; - DEVICE_BLOCK_HEADER *NonMemoryRelatedDeviceList; - AGESA_STATUS ReturnStatus; - VOID *HeapPtrs[S3LATE_TABLE_SIZE]; - UINT32 HeapSizes[S3LATE_TABLE_SIZE]; - UINT32 HeapBuffersPresent; - HEAP_MANAGER *HeapPtr; - - AGESA_TESTPOINT (TpIfAmdS3SaveEntry, &AmdS3SaveParams->StdHeader); - - ASSERT (AmdS3SaveParams != NULL); - - HeapBuffersPresent = 0; - EarlyBufferSize = 0; - LateBufferSize = 0; - LateContextSize = 0; - HeapSize = 0; - NonMemoryRelatedDeviceList = NULL; - MemoryRelatedDeviceList = NULL; - ReturnStatus = AGESA_SUCCESS; - - IDS_SKIP_HOOK (IDS_BEFORE_S3_SAVE, AmdS3SaveParams, &(AmdS3SaveParams->StdHeader)) { - - // Get memory device list - MemFS3GetDeviceList (&MemoryRelatedDeviceList, &AmdS3SaveParams->StdHeader); - if (MemoryRelatedDeviceList != NULL) { - // Determine size needed - EarlyBufferSize = GetWorstCaseContextSize (MemoryRelatedDeviceList, INIT_RESUME, &AmdS3SaveParams->StdHeader); - } - - if (UserOptions.CfgS3LateRestore) { - for (i = 0; i < S3LATE_TABLE_SIZE; i++) { - LocateHeap.BufferHandle = S3LateHeapTable[i]; - if (HeapLocateBuffer (&LocateHeap, &AmdS3SaveParams->StdHeader) == AGESA_SUCCESS) { - HeapBuffersPresent++; - HeapSize += LocateHeap.BufferSize; - HeapPtrs[i] = LocateHeap.BufferPtr; - HeapSizes[i] = LocateHeap.BufferSize; - } else { - HeapPtrs[i] = NULL; - HeapSizes[i] = 0; - } - } - - // Determine heap data size requirements - if (HeapBuffersPresent != 0) { - HeapSize += ((sizeof (HEAP_MANAGER)) + (HeapBuffersPresent * ((sizeof (BUFFER_NODE)) + (NUM_OF_SENTINEL * SIZE_OF_SENTINEL) + 0xF))); // reserve 0xF per buffer node for 16 byte alignment - } - - // Get non memory device list - GetNonMemoryRelatedDeviceList (&NonMemoryRelatedDeviceList, &AmdS3SaveParams->StdHeader); - - if (NonMemoryRelatedDeviceList != NULL) { - // Determine size needed - LateContextSize = GetWorstCaseContextSize (NonMemoryRelatedDeviceList, S3_LATE_RESTORE, &AmdS3SaveParams->StdHeader); - } - LateBufferSize = HeapSize + LateContextSize; - if (LateBufferSize != 0) { - LateBufferSize += sizeof (S3_VOLATILE_STORAGE_HEADER); - } - } - - if ((EarlyBufferSize != 0) || (LateBufferSize != 0)) { - // - // Allocate a buffer - // - AllocParams.RequestedBufferSize = EarlyBufferSize + LateBufferSize; - AllocParams.BufferHandle = AMD_S3_INFO_BUFFER_HANDLE; - - AGESA_TESTPOINT (TpIfBeforeAllocateS3SaveBuffer, &AmdS3SaveParams->StdHeader); - if (HeapAllocateBuffer (&AllocParams, &AmdS3SaveParams->StdHeader) != AGESA_SUCCESS) { - if (AGESA_ERROR > ReturnStatus) { - ReturnStatus = AGESA_ERROR; - } - } - AGESA_TESTPOINT (TpIfAfterAllocateS3SaveBuffer, &AmdS3SaveParams->StdHeader); - - if (EarlyBufferSize != 0) { - AmdS3SaveParams->S3DataBlock.NvStorage = AllocParams.BufferPtr; - SaveDeviceListContext (MemoryRelatedDeviceList, - AmdS3SaveParams->S3DataBlock.NvStorage, - INIT_RESUME, - &EarlyBufferSize, - &AmdS3SaveParams->StdHeader); - - AmdS3SaveParams->S3DataBlock.NvStorageSize = EarlyBufferSize; - } - - if (LateBufferSize != 0) { - BufferPointer = AllocParams.BufferPtr; - AmdS3SaveParams->S3DataBlock.VolatileStorage = &(BufferPointer[EarlyBufferSize]); - - ((S3_VOLATILE_STORAGE_HEADER *) AmdS3SaveParams->S3DataBlock.VolatileStorage)->HeapOffset = (intptr_t) NULL; - ((S3_VOLATILE_STORAGE_HEADER *) AmdS3SaveParams->S3DataBlock.VolatileStorage)->HeapSize = HeapSize; - ((S3_VOLATILE_STORAGE_HEADER *) AmdS3SaveParams->S3DataBlock.VolatileStorage)->RegisterDataOffset = (intptr_t) NULL; - ((S3_VOLATILE_STORAGE_HEADER *) AmdS3SaveParams->S3DataBlock.VolatileStorage)->RegisterDataSize = LateContextSize; - - if (HeapSize != 0) { - // Transfer heap contents - ((S3_VOLATILE_STORAGE_HEADER *) AmdS3SaveParams->S3DataBlock.VolatileStorage)->HeapOffset = sizeof (S3_VOLATILE_STORAGE_HEADER); - HeapPtr = (HEAP_MANAGER *) &BufferPointer[EarlyBufferSize + sizeof (S3_VOLATILE_STORAGE_HEADER)]; - HeapPtr->UsedSize = sizeof (HEAP_MANAGER); - HeapPtr->Signature = HEAP_SIGNATURE_VALID; - HeapPtr->FirstActiveBufferOffset = AMD_HEAP_INVALID_HEAP_OFFSET; - HeapPtr->FirstFreeSpaceOffset = sizeof (HEAP_MANAGER); - FreeSpaceNode = (BUFFER_NODE *) ((UINT8 *) HeapPtr + sizeof (HEAP_MANAGER)); - FreeSpaceNode->BufferSize = HeapSize - sizeof (HEAP_MANAGER) - sizeof (BUFFER_NODE); - FreeSpaceNode->OffsetOfNextNode = AMD_HEAP_INVALID_HEAP_OFFSET; - - HeapStatus = AmdS3SaveParams->StdHeader.HeapStatus; - AmdS3SaveParams->StdHeader.HeapStatus = HEAP_S3_RESUME; - AmdS3SaveParams->StdHeader.HeapBasePtr = (UINT64) (intptr_t) HeapPtr; - - for (i = 0; i < S3LATE_TABLE_SIZE; i++) { - if (HeapPtrs[i] != NULL) { - HeapParams.RequestedBufferSize = HeapSizes[i]; // S3LateHeapTable[i].BufferLength; - HeapParams.BufferHandle = S3LateHeapTable[i]; - HeapParams.Persist = HEAP_S3_RESUME; - if (HeapAllocateBuffer (&HeapParams, &AmdS3SaveParams->StdHeader) == AGESA_SUCCESS) { - LibAmdMemCopy ((VOID *) HeapParams.BufferPtr, HeapPtrs[i], HeapSizes[i], &AmdS3SaveParams->StdHeader); - } - } - } - - AmdS3SaveParams->StdHeader.HeapStatus = HeapStatus; - } - - - if (LateContextSize != 0) { - - ((S3_VOLATILE_STORAGE_HEADER *) AmdS3SaveParams->S3DataBlock.VolatileStorage)->RegisterDataOffset = HeapSize + sizeof (S3_VOLATILE_STORAGE_HEADER); - - SaveDeviceListContext (NonMemoryRelatedDeviceList, - &(BufferPointer[EarlyBufferSize + HeapSize + sizeof (S3_VOLATILE_STORAGE_HEADER)]), - S3_LATE_RESTORE, - &LateContextSize, - &AmdS3SaveParams->StdHeader); - } - - AmdS3SaveParams->S3DataBlock.VolatileStorageSize = HeapSize + LateContextSize + sizeof (S3_VOLATILE_STORAGE_HEADER); - } - } - } - - ReturnStatus = BldoptFchFunction.InitLate (AmdS3SaveParams); - - IDS_OPTION_HOOK (IDS_AFTER_S3_SAVE, AmdS3SaveParams, &AmdS3SaveParams->StdHeader); - AGESA_TESTPOINT (TpIfAmdS3SaveExit, &AmdS3SaveParams->StdHeader); - return ReturnStatus; -} - -/*---------------------------------------------------------------------------------------*/ -/** - * Constructor for the AMD_S3_SAVE function. - * - * This routine is responsible for setting default values for the - * input parameters needed by the AMD_S3_SAVE entry point. - * - * @param[in] StdHeader The standard header. - * @param[in,out] S3SaveParams Required input parameters for the AMD_S3_SAVE - * entry point. - * - * @retval AGESA_SUCCESS Always Succeeds. - * - */ -AGESA_STATUS -AmdS3SaveInitializer ( - IN OUT AMD_CONFIG_PARAMS *StdHeader, - IN OUT AMD_S3SAVE_PARAMS *S3SaveParams - ) -{ - ASSERT (StdHeader != NULL); - ASSERT (S3SaveParams != NULL); - - S3SaveParams->StdHeader = *StdHeader; - - AmdS3ParamsInitializer (&S3SaveParams->S3DataBlock); - - AmdS3SavePlatformConfigInit (&S3SaveParams->PlatformConfig, &S3SaveParams->StdHeader); - BldoptFchFunction.InitLateConstructor (S3SaveParams); - - return AGESA_SUCCESS; -} - -/*---------------------------------------------------------------------------------------*/ -/** - * Destructor for the AMD_S3_SAVE function. - * - * This routine is responsible for deallocation of heap space allocated during - * AMD_S3_SAVE entry point. - * - * @param[in] StdHeader The standard header. - * @param[in,out] S3SaveParams Required input parameters for the AMD_INIT_RESUME - * entry point. - * - * @retval AGESA_STATUS - * - */ -AGESA_STATUS -AmdS3SaveDestructor ( - IN AMD_CONFIG_PARAMS *StdHeader, - IN OUT AMD_S3SAVE_PARAMS *S3SaveParams - ) -{ - AGESA_STATUS ReturnStatus; - AGESA_STATUS RetVal; - - ASSERT (S3SaveParams != NULL); - - ReturnStatus = AGESA_SUCCESS; - - // Deallocate heap space allocated during memory S3 save - RetVal = MemS3Deallocate (&S3SaveParams->StdHeader); - if (RetVal > ReturnStatus) { - ReturnStatus = RetVal; - } - - RetVal = HeapDeallocateBuffer (AMD_S3_NB_INFO_BUFFER_HANDLE, StdHeader); - if (RetVal > ReturnStatus) { - ReturnStatus = RetVal; - } - - RetVal = HeapDeallocateBuffer (AMD_S3_INFO_BUFFER_HANDLE, StdHeader); - if (RetVal > ReturnStatus) { - ReturnStatus = RetVal; - } - - return ReturnStatus; -} - -/*------------------------------------------------------------------------------------*/ -/** - * Initialize AmdS3Save stage platform profile and user option input. - * - * @param[in,out] PlatformConfig Platform profile/build option config structure - * @param[in,out] StdHeader AMD standard header config param - * - * @retval AGESA_SUCCESS Always Succeeds. - * - */ -AGESA_STATUS -AmdS3SavePlatformConfigInit ( - IN OUT PLATFORM_CONFIGURATION *PlatformConfig, - IN OUT AMD_CONFIG_PARAMS *StdHeader - ) -{ - CommonPlatformConfigInit (PlatformConfig, StdHeader); - - return AGESA_SUCCESS; -} diff --git a/src/vendorcode/amd/agesa/f12/Proc/Common/CommonInits.c b/src/vendorcode/amd/agesa/f12/Proc/Common/CommonInits.c deleted file mode 100644 index c12ad55273..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/Common/CommonInits.c +++ /dev/null @@ -1,136 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * Common initialization routines. - * - * Contains common initialization routines across AGESA entries of phases. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: Common - * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $ - * - */ -/***************************************************************************** - * - * Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - ****************************************************************************** - */ - - -/*---------------------------------------------------------------------------------------- - * M O D U L E S U S E D - *---------------------------------------------------------------------------------------- - */ -#include "AGESA.h" -#include "Ids.h" -#include "Filecode.h" -#include "heapManager.h" -#include "CommonInits.h" -CODE_GROUP (G1_PEICC) -RDATA_GROUP (G1_PEICC) - -#define FILECODE PROC_COMMON_COMMONINITS_FILECODE -/*---------------------------------------------------------------------------------------- - * D E F I N I T I O N S A N D M A C R O S - *---------------------------------------------------------------------------------------- - */ -extern BUILD_OPT_CFG UserOptions; - -/*---------------------------------------------------------------------------------------- - * T Y P E D E F S A N D S T R U C T U R E S - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------- - * P R O T O T Y P E S O F L O C A L F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ - - -/*---------------------------------------------------------------------------------------- - * E X P O R T E D F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ - -/*------------------------------------------------------------------------------------*/ - -/** - * Common routine to initialize PLATFORM_CONFIGURATION. - * - * @param[in,out] PlatformConfig Platform profile/build option config structure - * @param[in,out] StdHeader AMD standard header config param - * - * @retval AGESA_SUCCESS Always Succeeds. - * - */ -AGESA_STATUS -CommonPlatformConfigInit ( - IN OUT PLATFORM_CONFIGURATION *PlatformConfig, - IN OUT AMD_CONFIG_PARAMS *StdHeader - ) -{ - UINTN i; - - PlatformConfig->PlatformProfile = UserOptions.CfgPerformanceProfile; - PlatformConfig->PlatformDeemphasisList = UserOptions.CfgPlatformDeemphasisList; - PlatformConfig->CoreLevelingMode = (UINT8) UserOptions.CfgCoreLevelingMode; - PlatformConfig->C1eMode = UserOptions.CfgPlatformC1eMode; - PlatformConfig->C1ePlatformData = UserOptions.CfgPlatformC1eOpData; - PlatformConfig->C1ePlatformData1 = UserOptions.CfgPlatformC1eOpData1; - PlatformConfig->C1ePlatformData2 = UserOptions.CfgPlatformC1eOpData2; - PlatformConfig->C1ePlatformData3 = UserOptions.CfgPlatformC1eOpData3; - PlatformConfig->CStateMode = UserOptions.CfgPlatformCStateMode; - PlatformConfig->CStatePlatformData = UserOptions.CfgPlatformCStateOpData; - PlatformConfig->CStateIoBaseAddress = UserOptions.CfgPlatformCStateIoBaseAddress; - PlatformConfig->CpbMode = UserOptions.CfgPlatformCpbMode; - PlatformConfig->UserOptionDmi = UserOptions.OptionDmi; - PlatformConfig->UserOptionPState = UserOptions.OptionAcpiPstates; - PlatformConfig->UserOptionSrat = UserOptions.OptionSrat; - PlatformConfig->UserOptionSlit = UserOptions.OptionSlit; - PlatformConfig->UserOptionWhea = UserOptions.OptionWhea; - PlatformConfig->PowerCeiling = UserOptions.CfgAmdPstateCapValue; - PlatformConfig->ForcePstateIndependent = UserOptions.CfgAcpiPstateIndependent; - PlatformConfig->NumberOfIoApics = UserOptions.CfgPlatNumIoApics; - for (i = 0; i < MaxVrmType; i++) { - PlatformConfig->VrmProperties[i] = UserOptions.CfgPlatVrmCfg[i]; - } - PlatformConfig->ProcessorScopeInSb = UserOptions.CfgProcessorScopeInSb; - PlatformConfig->ProcessorScopeName0 = UserOptions.CfgProcessorScopeName0; - PlatformConfig->ProcessorScopeName1 = UserOptions.CfgProcessorScopeName1; - PlatformConfig->GnbHdAudio = UserOptions.CfgGnbHdAudio; - PlatformConfig->AbmSupport = UserOptions.CfgAbmSupport; - PlatformConfig->DynamicRefreshRate = UserOptions.CfgDynamicRefreshRate; - PlatformConfig->LcdBackLightControl = UserOptions.CfgLcdBackLightControl; - if ((StdHeader->HeapStatus == HEAP_LOCAL_CACHE) || - (StdHeader->HeapStatus == HEAP_TEMP_MEM) || - (StdHeader->HeapStatus == HEAP_SYSTEM_MEM)) { - IDS_OPTION_HOOK (IDS_PLATFORMCFG_OVERRIDE, PlatformConfig, StdHeader); - } - return AGESA_SUCCESS; -} - diff --git a/src/vendorcode/amd/agesa/f12/Proc/Common/CommonInits.h b/src/vendorcode/amd/agesa/f12/Proc/Common/CommonInits.h deleted file mode 100644 index 1a736b6af0..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/Common/CommonInits.h +++ /dev/null @@ -1,65 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * Common initialization routines. - * - * Contains common initialization routines across AGESA entries of phases. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: Common - * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $ - * - */ -/* -***************************************************************************** -* -* Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* *************************************************************************** -* -*/ - -#ifndef _COMMON_INITS_H_ -#define _COMMON_INITS_H_ - -/** - * Common routine to initialize PLATFORM_CONFIGURATION. - * - * @param[in,out] PlatformConfig Platform profile/build option config structure - * @param[in,out] StdHeader AMD standard header config param - * - * @retval AGESA_SUCCESS Always Succeeds. - * - */ -AGESA_STATUS -CommonPlatformConfigInit ( - IN OUT PLATFORM_CONFIGURATION *PlatformConfig, - IN OUT AMD_CONFIG_PARAMS *StdHeader - ); - -#endif // _COMMON_INITS_H_ - diff --git a/src/vendorcode/amd/agesa/f12/Proc/Common/CommonPage.h b/src/vendorcode/amd/agesa/f12/Proc/Common/CommonPage.h deleted file mode 100644 index ec08ba8c3e..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/Common/CommonPage.h +++ /dev/null @@ -1,116 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * Create outline and references for Processor Common Component mainpage documentation. - * - * Design guides, maintenance guides, and general documentation, are - * collected using this file onto the documentation mainpage. - * This file contains doxygen comment blocks, only. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: Documentation - * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $ - * - */ -/* - ****************************************************************************** - * - * Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - ****************************************************************************** - */ - -/** - * @page commonmain Processor Common Component Documentation - * - * Additional documentation for the Common component consists of - * - * - Maintenance Guides: - * - @subpage amdconfigparamname "Naming Guidelines for type AMD_CONFIG_PARAMS" - * - Design Guides: - * - add here >>> - * - */ - -/** - * @page amdconfigparamname Naming Guidelines for type AMD_CONFIG_PARAMS - * @par - * These are the guidelines for naming objects of type AMD_CONFIG_PARAMS and AMD_CONFIG_PARAMS * in AGESA code. - *
    - * - *
  • - * Formal parameter names of type AMD_CONFIG_PARAMS and AMD_CONFIG_PARAMS * will always be named - * StdHeader. This covers all function prototypes, function definitions, and method typedefs (a - * typedef of a function prototype) in AGESA code. Examples: - * @n @code - * VOID - * LibAmdPciFindNextCap ( - * IN OUT PCI_ADDR *Address, - * IN AMD_CONFIG_PARAMS *StdHeader - * ) - * - * typedef VOID F_DO_TABLE_ENTRY ( - * IN TABLE_ENTRY_DATA *CurrentEntry, - * IN PLATFORM_CONFIGURATION *PlatformConfig, - * IN AMD_CONFIG_PARAMS *StdHeader - * ); - * - * @endcode - * - *
  • - * Structure members of type AMD_CONFIG_PARAMS or AMD_CONFIG_PARAMS * will always be named StdHeader. Examples: - * @n @code - /// Example of struct member naming. - * typedef struct { - * IN OUT AMD_CONFIG_PARAMS StdHeader; ///< Standard Header - * IN PLATFORM_CONFIGURATION PlatformConfig; ///< platform operational characteristics. - * } AMD_CPU_RECOVERY_PARAMS; - * - * @endcode - * - *
  • - * Routines which define local variables of type AMD_CONFIG_PARAMS or AMD_CONFIG_PARAMS * should - * name the local variable as closely as practical to StdHeader, but otherwise freedom is allowed. Example: - * @n @code - * AMD_CONFIG_PARAMS *NewStdHeader; - * [...] - * NewStdHeader = (AMD_CONFIG_PARAMS *)AllocHeapParams.BufferPtr; - * @endcode - * - *
  • - * Arguments to routines with AMD_CONFIG_PARAMS or AMD_CONFIG_PARAMS * formal parameters are not - * checked. Freedom is allowed in order to conform to these guidelines in a practical, readable - * way. This includes typecast arguments. Examples: - * @n @code - * Status = GetEventLog (&LogEvent, (AMD_CONFIG_PARAMS *)Event); - * - * MemS3ExitSelfRefRegDA (NBPtr, &MemPtr->StdHeader); - * @endcode - * - *
- * - */ diff --git a/src/vendorcode/amd/agesa/f12/Proc/Common/CommonReturns.c b/src/vendorcode/amd/agesa/f12/Proc/Common/CommonReturns.c deleted file mode 100644 index d27f8171ff..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/Common/CommonReturns.c +++ /dev/null @@ -1,207 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * Common Return routines. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: Common - * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $ - * - */ -/* -***************************************************************************** -* -* Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* *************************************************************************** -* -*/ - -/* - *---------------------------------------------------------------------------- - * MODULES USED - * - *---------------------------------------------------------------------------- - */ - - -#include "AGESA.h" -#include "Ids.h" -#include "CommonReturns.h" -#include "Filecode.h" -CODE_GROUP (G1_PEICC) -RDATA_GROUP (G1_PEICC) - -#define FILECODE PROC_COMMON_COMMONRETURNS_FILECODE -/*---------------------------------------------------------------------------- - * DEFINITIONS AND MACROS - * - *---------------------------------------------------------------------------- - */ -AGESA_STATUS -CommonFchInitStub ( - IN VOID *DataPtr - ); - -VOID -FchTaskDummy ( - IN VOID *DataPtr - ); - -/*----------------------------------------------------------------------------------------*/ -/** -* Return TRUE. -* -* @retval TRUE Default case, no special action -*/ -BOOLEAN -CommonReturnTrue (VOID) -{ - return TRUE; -} - - -/*----------------------------------------------------------------------------------------*/ -/** -* Return False. -* -* @retval FALSE Default case, no special action -*/ -BOOLEAN -CommonReturnFalse (VOID) -{ - return FALSE; -} - -/*----------------------------------------------------------------------------------------*/ -/** - * Return (UINT8)zero. - * - * - * @retval zero None, or only case zero. - */ -UINT8 -CommonReturnZero8 (VOID) -{ - return 0; -} - -/*----------------------------------------------------------------------------------------*/ -/** - * Return (UINT32)zero. - * - * - * @retval zero None, or only case zero. - */ -UINT32 -CommonReturnZero32 (VOID) -{ - return 0; -} - -/*----------------------------------------------------------------------------------------*/ -/** - * Return (UINT64)zero. - * - * - * @retval zero None, or only case zero. - */ -UINT64 -CommonReturnZero64 (VOID) -{ - return 0; -} - -/*----------------------------------------------------------------------------------------*/ -/** - * Return NULL - * - * @retval NULL pointer to nothing - */ -VOID * -CommonReturnNULL (VOID) -{ - return NULL; -} - -/*----------------------------------------------------------------------------------------*/ -/** -* Return AGESA_SUCCESS. -* -* @retval AGESA_SUCCESS Success. -*/ -AGESA_STATUS -CommonReturnAgesaSuccess (VOID) -{ - return AGESA_SUCCESS; -} - - -/*----------------------------------------------------------------------------------------*/ -/** - * Do Nothing. - * - */ -VOID -CommonVoid (VOID) -{ -} - -/*----------------------------------------------------------------------------------------*/ -/** - * ASSERT if this routine is called. - * - */ -VOID -CommonAssert (VOID) -{ - ASSERT (FALSE); -} - - -/*----------------------------------------------------------------------------------------*/ -/** -* Return AGESA_SUCCESS. -* -* @retval AGESA_SUCCESS Success. -*/ -AGESA_STATUS -CommonFchInitStub ( - IN VOID *DataPtr - ) -{ - return AGESA_SUCCESS; -} - - -VOID -FchTaskDummy ( - IN VOID *DataPtr - ) -{ -} - diff --git a/src/vendorcode/amd/agesa/f12/Proc/Common/CreateStruct.c b/src/vendorcode/amd/agesa/f12/Proc/Common/CreateStruct.c deleted file mode 100644 index 010536e5c6..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/Common/CreateStruct.c +++ /dev/null @@ -1,313 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * AMD AGESA Input Structure Creation - * - * Contains AGESA input structure creation support. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: Common - * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $ - * - */ -/* - ****************************************************************************** - * - * Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - ****************************************************************************** - */ - -/*---------------------------------------------------------------------------------------- - * M O D U L E S U S E D - *---------------------------------------------------------------------------------------- - */ -#include "AGESA.h" -#include "amdlib.h" -#include "Ids.h" -#include "GeneralServices.h" -#include "heapManager.h" -#include "CreateStruct.h" -#include "cpuFamilyTranslation.h" -#include "Filecode.h" -CODE_GROUP (G1_PEICC) -RDATA_GROUP (G1_PEICC) - -#define FILECODE PROC_COMMON_CREATESTRUCT_FILECODE -/*---------------------------------------------------------------------------------------- - * D E F I N I T I O N S A N D M A C R O S - *---------------------------------------------------------------------------------------- - */ -extern CONST FUNCTION_PARAMS_INFO FuncParamsInfo[]; -extern CONST UINTN InitializerCount; - -/*---------------------------------------------------------------------------------------- - * T Y P E D E F S A N D S T R U C T U R E S - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------- - * P R O T O T Y P E S O F L O C A L F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------- - * E X P O R T E D F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ -extern BUILD_OPT_CFG UserOptions; - -/*---------------------------------------------------------------------------------------*/ -/** - * Allocate and initialize Config headers and Service Interface structures. - * - * This function will be called for each AGESA public APIs. - * This function will do the following: - * -# Locate the AGESA API structure parameters initializer function information. - * -# Find the size of the structure that gets passed to each public APIs as - * the entry parameter. Allocate heap space using the size for PreMemHeap, callout for - * memory allocation for PostMemDram, and just set the config and service interface - * pointers for ByHost. - * -# If the allocation is not ByHost, copy the AmdConfigParams into the newly created AmdConfigParams. - * For ByHost, we're using the caller's existing config params. - * -# Call the initializer function, and pass a reference to the Config params and to - * the Service Interface struct. On return the constructor will have filled the - * remaining structure with default values. - * -# Fill the remaining info in the newly created structure on heap in AMD_CONFIG_PARAMS - * area (i.e. Fill *newStructPtr with the pointer to the newly created structure) - * -# Set the appropriate AGESA function number in the StdHeader member of the input - * parameter structure. - * - * @param[in,out] InterfaceParams Pointer to structure containing the function call - * whose parameter structure is to be created, the - * allocation method, and a pointer to the newly - * created structure. - * - * @retval AGESA_SUCCESS The interface struct is allocated and initialized. - * @retval AGESA_UNSUPPORTED The Service is not supported. - * - */ -AGESA_STATUS -AmdCreateStruct ( - IN OUT AMD_INTERFACE_PARAMS *InterfaceParams - ) -{ - UINTN ServiceIndex; - ALLOCATE_HEAP_PARAMS AllocHeapParams; - AMD_CONFIG_PARAMS *NewlyCreatedConfig; - VOID *NewlyCreatedServiceInterface; - AGESA_STATUS AgesaStatus; - AGESA_STATUS TempStatus; - AGESA_STATUS IgnoredSts; - CPU_SPECIFIC_SERVICES *FamilySpecificServices; - - AgesaStatus = AGESA_SUCCESS; - - ASSERT (InterfaceParams != NULL); - - switch (InterfaceParams->AgesaFunctionName) { - case AMD_INIT_RESET: - if (!IsBsp (&InterfaceParams->StdHeader, &IgnoredSts)) { - // APs must transfer their system core number from the mailbox to - // a local register while it is still valid. - GetCpuServicesOfCurrentCore ((const CPU_SPECIFIC_SERVICES **)&FamilySpecificServices, &InterfaceParams->StdHeader); - FamilySpecificServices->TransferApCoreNumber (FamilySpecificServices, &InterfaceParams->StdHeader); - } - InterfaceParams->StdHeader.HeapStatus = HEAP_DO_NOT_EXIST_YET; - break; - case AMD_INIT_EARLY: - case AMD_INIT_RECOVERY: - case AMD_INIT_RESUME: - case AMD_INIT_POST: - InterfaceParams->StdHeader.HeapStatus = HEAP_LOCAL_CACHE; - break; - case AMD_INIT_ENV: - InterfaceParams->StdHeader.HeapStatus = HEAP_TEMP_MEM; - break; - case AMD_INIT_LATE: - case AMD_INIT_MID: - case AMD_S3_SAVE: - case AMD_LATE_RUN_AP_TASK: - InterfaceParams->StdHeader.HeapStatus = HEAP_SYSTEM_MEM; - break; - case AMD_S3LATE_RESTORE: - InterfaceParams->StdHeader.HeapStatus = HEAP_S3_RESUME; - break; - default: - ASSERT (FALSE); - InterfaceParams->StdHeader.HeapStatus = HEAP_LOCAL_CACHE; - break; - } - - InterfaceParams->StdHeader.HeapBasePtr = HeapGetBaseAddress (&InterfaceParams->StdHeader); - - if (InterfaceParams->AgesaFunctionName == AMD_INIT_RESET) { - AgesaStatus = HeapManagerInit (&InterfaceParams->StdHeader); - } - - // Step 1 - for (ServiceIndex = 0; ServiceIndex < InitializerCount; ServiceIndex++) { - if (FuncParamsInfo[ServiceIndex].AgesaFunctionName == InterfaceParams->AgesaFunctionName) { - break; - } - } - if (ServiceIndex >= InitializerCount) { - // A call was made to AGESA with an invalid function number. This wrapper error may be due to the build target - // not containing the desired entry point. - return AGESA_UNSUPPORTED; - } - - // Step 2 - LibAmdMemFill (&AllocHeapParams, 0, (UINTN) (sizeof (ALLOCATE_HEAP_PARAMS)), &InterfaceParams->StdHeader); - - if (InterfaceParams->AllocationMethod < ByHost) { - // Allocate one buffer to contain the config params and the service struct. - // The service struct begins immediately after the config params. - AllocHeapParams.RequestedBufferSize = FuncParamsInfo[ServiceIndex].CreateStructSize + sizeof (AMD_CONFIG_PARAMS); - AllocHeapParams.BufferHandle = FuncParamsInfo[ServiceIndex].BufferHandle; - AllocHeapParams.Persist = HEAP_SYSTEM_MEM; - TempStatus = HeapAllocateBuffer (&AllocHeapParams, &(InterfaceParams->StdHeader)); - AgesaStatus = ((AgesaStatus > TempStatus) ? AgesaStatus : TempStatus); - NewlyCreatedConfig = (AMD_CONFIG_PARAMS *)AllocHeapParams.BufferPtr; - NewlyCreatedConfig++; - NewlyCreatedServiceInterface = NewlyCreatedConfig; - NewlyCreatedConfig = (AMD_CONFIG_PARAMS *)AllocHeapParams.BufferPtr; - } else { - // The caller (example, agesa basic interface implementation) already has a buffer to use. - NewlyCreatedConfig = (AMD_CONFIG_PARAMS *)InterfaceParams; - NewlyCreatedServiceInterface = InterfaceParams->NewStructPtr; - ASSERT (InterfaceParams->NewStructSize >= FuncParamsInfo[ServiceIndex].CreateStructSize); - } - ASSERT (NewlyCreatedConfig != NULL); - ASSERT (NewlyCreatedServiceInterface != NULL); - - // Step 3 - if (InterfaceParams->AllocationMethod != ByHost) { - *NewlyCreatedConfig = InterfaceParams->StdHeader; - } - - // Step 4 - TempStatus = FuncParamsInfo[ServiceIndex].AgesaFunction (NewlyCreatedConfig, NewlyCreatedServiceInterface); - AgesaStatus = ((AgesaStatus > TempStatus) ? AgesaStatus : TempStatus); - - // Step 5 - if (InterfaceParams->AllocationMethod != ByHost) { - InterfaceParams->NewStructPtr = (VOID *) NewlyCreatedServiceInterface; - InterfaceParams->NewStructSize = FuncParamsInfo[ServiceIndex].CreateStructSize; - } - - // Step 6 - ((AMD_CONFIG_PARAMS *) InterfaceParams->NewStructPtr)->Func = InterfaceParams->AgesaFunctionName; - return AgesaStatus; -} - - -/*---------------------------------------------------------------------------------------*/ -/** - * Clears storage space from allocation for a parameter block of an - * AGESA software call entry. - * - * @param[in,out] InterfaceParams Pointer to structure containing the function call - * whose parameter structure is to be deallocated. - * - * @retval AGESA_STATUS - * - *--------------------------------------------------------------------------------------- - **/ -AGESA_STATUS -AmdReleaseStruct ( - IN OUT AMD_INTERFACE_PARAMS *InterfaceParams - ) -{ - UINT8 i; - UINT8 *BufferPtr; - VOID *ServicePtr; - AGESA_STATUS AgesaStatus; - AGESA_STATUS TempStatus; - LOCATE_HEAP_PTR LocHeap; - - AgesaStatus = AGESA_SUCCESS; - - switch (InterfaceParams->AgesaFunctionName) { - case AMD_INIT_RESET: - case AMD_INIT_EARLY: - case AMD_INIT_RECOVERY: - case AMD_INIT_RESUME: - InterfaceParams->StdHeader.HeapStatus = HEAP_LOCAL_CACHE; - break; - case AMD_INIT_POST: - InterfaceParams->StdHeader.HeapStatus = HEAP_TEMP_MEM; - break; - case AMD_INIT_ENV: - case AMD_INIT_LATE: - case AMD_INIT_MID: - case AMD_S3_SAVE: - case AMD_LATE_RUN_AP_TASK: - InterfaceParams->StdHeader.HeapStatus = HEAP_SYSTEM_MEM; - break; - case AMD_S3LATE_RESTORE: - InterfaceParams->StdHeader.HeapStatus = HEAP_S3_RESUME; - break; - default: - ASSERT (FALSE); - InterfaceParams->StdHeader.HeapStatus = HEAP_LOCAL_CACHE; - break; - } - - InterfaceParams->StdHeader.HeapBasePtr = HeapGetBaseAddress (&InterfaceParams->StdHeader); - -// Step 1 - for (i = 0; i < InitializerCount; i++) { - if (FuncParamsInfo[i].AgesaFunctionName == InterfaceParams->AgesaFunctionName) { - break; - } - } - if (i >= InitializerCount) { - return AGESA_BOUNDS_CHK; - } - - // Step 2 - if (InterfaceParams->AllocationMethod < ByHost) { - LocHeap.BufferHandle = FuncParamsInfo[i].BufferHandle; - if (HeapLocateBuffer (&LocHeap, &(InterfaceParams->StdHeader)) == AGESA_SUCCESS) { - BufferPtr = (UINT8 *) LocHeap.BufferPtr; - ServicePtr = &BufferPtr[sizeof (AMD_CONFIG_PARAMS)]; - TempStatus = FuncParamsInfo[i].AgesaDestructor (&(InterfaceParams->StdHeader), ServicePtr); - AgesaStatus = ((AgesaStatus > TempStatus) ? AgesaStatus : TempStatus); - } - } - - // Step 3 - if (InterfaceParams->AllocationMethod < ByHost) { - TempStatus = HeapDeallocateBuffer (FuncParamsInfo[i].BufferHandle, &(InterfaceParams->StdHeader)); - AgesaStatus = ((AgesaStatus > TempStatus) ? AgesaStatus : TempStatus); - } else { - // Unless we define service specific destructors, nothing to do for ByHost. - return AGESA_SUCCESS; - } - return AgesaStatus; -} diff --git a/src/vendorcode/amd/agesa/f12/Proc/Common/CreateStruct.h b/src/vendorcode/amd/agesa/f12/Proc/Common/CreateStruct.h deleted file mode 100644 index 65a20409e1..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/Common/CreateStruct.h +++ /dev/null @@ -1,195 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * AMD AGESA Input Structure Creation - * - * Contains AGESA input creation structures. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: Common - * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $ - * - */ -/* - ****************************************************************************** - * - * Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - ****************************************************************************** - */ - -#ifndef _CREATE_STRUCT_H_ -#define _CREATE_STRUCT_H_ - -/** - * A constructor method. - * - * Sets inputs to valid, basic level, defaults for the specific service instance. - * Constructors should avoid using the header, since these routines should not - * do operations which may fail or require status back to the user. The constructor - * should always SUCCEED. - * - * @param[in] StdHeader Opaque handle to standard config header - * @param[in] ServiceInterface Service Interface structure to initialize. - * - * @retval AGESA_SUCCESS Constructors are not allowed to fail -*/ -typedef AGESA_STATUS -F_AGESA_FUNCTION ( - IN AMD_CONFIG_PARAMS *StdHeader, - IN VOID *ServiceInterface - ); - -/// Reference to a Method. -typedef F_AGESA_FUNCTION *PF_AGESA_FUNCTION; - -/** - * A Destructor method. - * - * Sets inputs to valid, basic level, defaults for the specific service instance. - * The constructor should always SUCCEED. - * - * @param[in] StdHeader Opaque handle to standard config header. - * @param[in] ServiceInterface Service Interface structure to initialize. - * - * @retval AGESA_SUCCESS Constructors are not allowed to fail -*/ -typedef AGESA_STATUS -F_AGESA_DESTRUCTOR ( - IN AMD_CONFIG_PARAMS *StdHeader, - IN VOID *ServiceInterface - ); - -/// Reference to a Method. -typedef F_AGESA_DESTRUCTOR *PF_AGESA_DESTRUCTOR; - -/** - * Provide the information needed to invoke each service constructor. - */ -typedef struct { - IN AGESA_STRUCT_NAME AgesaFunctionName; ///< Identifies the service - IN UINT16 CreateStructSize; ///< The service's input struct size. - /// Do NOT include a config params header! - OUT PF_AGESA_FUNCTION AgesaFunction; ///< The constructor function - OUT PF_AGESA_DESTRUCTOR AgesaDestructor; ///< The destructor function. - IN AGESA_BUFFER_HANDLE BufferHandle; ///< The buffer handle id for the service. -} FUNCTION_PARAMS_INFO; - -/** - * All available services have their constructor info here. - */ -AGESA_STATUS -AmdInitResetConstructor ( - IN AMD_CONFIG_PARAMS *StdHeader, - IN AMD_RESET_PARAMS *AmdResetParams - ); - -AGESA_STATUS -AmdInitRecoveryInitializer ( - IN AMD_CONFIG_PARAMS *StdHeader, - IN OUT AMD_RECOVERY_PARAMS *AmdRecoveryParamsPtr - ); - -AGESA_STATUS -AmdInitEarlyInitializer ( - IN AMD_CONFIG_PARAMS *StdHeader, - IN OUT AMD_EARLY_PARAMS *EarlyParams - ); - -AGESA_STATUS -AmdInitPostInitializer ( - IN AMD_CONFIG_PARAMS *StdHeader, - IN OUT AMD_POST_PARAMS *PostParamsPtr - ); - -AGESA_STATUS -AmdInitPostDestructor ( - IN AMD_CONFIG_PARAMS *StdHeader, - IN AMD_POST_PARAMS *PostParamsPtr - ); - -AGESA_STATUS -AmdInitEnvInitializer ( - IN AMD_CONFIG_PARAMS *StdHeader, - IN OUT AMD_ENV_PARAMS *EnvParamsPtr - ); - -AGESA_STATUS -AmdInitMidInitializer ( - IN AMD_CONFIG_PARAMS *StdHeader, - IN OUT AMD_MID_PARAMS *MidParamsPtr - ); - -AGESA_STATUS -AmdInitLateInitializer ( - IN AMD_CONFIG_PARAMS *StdHeader, - IN OUT AMD_LATE_PARAMS *LateParamsPtr - ); - -AGESA_STATUS -AmdInitLateDestructor ( - IN AMD_CONFIG_PARAMS *StdHeader, - IN AMD_LATE_PARAMS *LateParamsPtr - ); - -AGESA_STATUS -AmdInitResumeInitializer ( - IN AMD_CONFIG_PARAMS *StdHeader, - IN OUT AMD_RESUME_PARAMS *ResumeParams - ); - -AGESA_STATUS -AmdInitResumeDestructor ( - IN AMD_CONFIG_PARAMS *StdHeader, - IN OUT AMD_RESUME_PARAMS *ResumeParams - ); - -AGESA_STATUS -AmdS3SaveInitializer ( - IN OUT AMD_CONFIG_PARAMS *StdHeader, - IN OUT AMD_S3SAVE_PARAMS *S3SaveParams - ); - -AGESA_STATUS -AmdS3SaveDestructor ( - IN AMD_CONFIG_PARAMS *StdHeader, - IN OUT AMD_S3SAVE_PARAMS *S3SaveParams - ); - -AGESA_STATUS -AmdS3LateRestoreInitializer ( - IN AMD_CONFIG_PARAMS *StdHeader, - IN OUT AMD_S3LATE_PARAMS *S3LateParams - ); - -AGESA_STATUS -AmdLateRunApTaskInitializer ( - IN AMD_CONFIG_PARAMS *StdHeader, - IN OUT AP_EXE_PARAMS *AmdApExeParams - ); -#endif // _CREATE_STRUCT_H_ - diff --git a/src/vendorcode/amd/agesa/f12/Proc/Common/Makefile.inc b/src/vendorcode/amd/agesa/f12/Proc/Common/Makefile.inc deleted file mode 100644 index 957c98f639..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/Common/Makefile.inc +++ /dev/null @@ -1,15 +0,0 @@ -libagesa-y += AmdInitEarly.c -libagesa-y += AmdInitEnv.c -libagesa-y += AmdInitLate.c -libagesa-y += AmdInitMid.c -libagesa-y += AmdInitPost.c -libagesa-y += AmdInitReset.c -libagesa-y += AmdInitResume.c -libagesa-y += AmdLateRunApTask.c -libagesa-y += AmdS3LateRestore.c -libagesa-y += AmdS3Save.c -libagesa-y += CommonInits.c -libagesa-y += CommonReturns.c -libagesa-y += CreateStruct.c -libagesa-y += S3RestoreState.c -libagesa-y += S3SaveState.c diff --git a/src/vendorcode/amd/agesa/f12/Proc/Common/S3RestoreState.c b/src/vendorcode/amd/agesa/f12/Proc/Common/S3RestoreState.c deleted file mode 100644 index 7b2056b2e9..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/Common/S3RestoreState.c +++ /dev/null @@ -1,441 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * S3 save/restore script - * - * - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: GNB - * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $ - * - */ -/* -***************************************************************************** -* -* Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* *************************************************************************** -* -*/ - -/*---------------------------------------------------------------------------------------- - * M O D U L E S U S E D - *---------------------------------------------------------------------------------------- - */ -#include "Porting.h" -#include "AMD.h" -#include "AGESA.h" -#include "Ids.h" -#include "amdlib.h" -#include "S3SaveState.h" -#include "Filecode.h" -CODE_GROUP (G1_PEICC) -RDATA_GROUP (G1_PEICC) - -#define FILECODE PROC_COMMON_S3RESTORESTATE_FILECODE -/*---------------------------------------------------------------------------------------- - * D E F I N I T I O N S A N D M A C R O S - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------- - * T Y P E D E F S A N D S T R U C T U R E S - *---------------------------------------------------------------------------------------- - */ - -extern S3_SCRIPT_CONFIGURATION OptionS3ScriptConfiguration; -extern S3_DISPATCH_FUNCTION_ENTRY S3DispatchFunctionTable[]; -/*---------------------------------------------------------------------------------------- - * P R O T O T Y P E S O F L O C A L F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ - - -AGESA_STATUS -STATIC -S3RestoreStateFromTable ( - IN S3_SAVE_TABLE_HEADER *S3SaveTablePtr, - IN AMD_CONFIG_PARAMS *StdHeader - ); - - - -/*----------------------------------------------------------------------------------------*/ -/** - * Initialize S3 Script framework - * - * - * - * @param[in] StdHeader Pointer to standard header - */ -AGESA_STATUS -S3ScriptRestore ( - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - return OptionS3ScriptConfiguration.Restore (StdHeader); -} - - -/*----------------------------------------------------------------------------------------*/ -/** - * Initialize S3 Script framework - * - * - * - * @param[in] StdHeader Pointer to standard header - */ -AGESA_STATUS -S3ScriptRestoreStateStub ( - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - return AGESA_SUCCESS; -} - - -/*----------------------------------------------------------------------------------------*/ -/** - * Initialize S3 Script framework - * - * - * - * @param[in] StdHeader Pointer to standard header - */ -AGESA_STATUS -S3ScriptRestoreState ( - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - AGESA_STATUS Status; - S3_SAVE_TABLE_HEADER *S3SaveTablePtr; - Status = S3ScriptGetS3SaveTable (StdHeader, &S3SaveTablePtr); - if (Status != AGESA_SUCCESS) { - IDS_ERROR_TRAP; - return AGESA_FATAL; - } - S3SaveTablePtr->Locked = TRUE; - Status = S3RestoreStateFromTable (S3SaveTablePtr, StdHeader); - return Status; -} - - -/*----------------------------------------------------------------------------------------*/ -/** - * Initialize S3 Script framework - * - * - * - * @param[in] S3SaveTablePtr Pointer to S3 Save Table - * @param[in] StdHeader Pointer to standard header - */ -AGESA_STATUS -STATIC -S3RestoreStateFromTable ( - IN S3_SAVE_TABLE_HEADER *S3SaveTablePtr, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - VOID *S3SaveTableRecordPtr; - PCI_ADDR PciAddress; - UINTN Index; - S3SaveTableRecordPtr = (UINT8 *) S3SaveTablePtr + sizeof (S3_SAVE_TABLE_HEADER); - IDS_HDT_CONSOLE (S3_TRACE, "Start S3 restore\n", ((S3_WRITE_OP_HEADER *) S3SaveTableRecordPtr)->Address); - while ((UINT8 *) S3SaveTableRecordPtr < ((UINT8 *) S3SaveTablePtr + S3SaveTablePtr->SaveOffset)) { - switch (*(UINT16 *) S3SaveTableRecordPtr) { - case SAVE_STATE_IO_WRITE_OPCODE: - S3_SCRIPT_DEBUG_CODE ( - IDS_HDT_CONSOLE (S3_TRACE, " S3 Restore: %s Address: 0x%08x Data: ", S3SaveDebugOpcodeString (StdHeader, *(UINT16 *) S3SaveTableRecordPtr), (UINT16) ((S3_WRITE_OP_HEADER *) S3SaveTableRecordPtr)->Address); - S3SaveDebugPrintHexArray (StdHeader, (UINT8 *) S3SaveTableRecordPtr + sizeof (S3_WRITE_OP_HEADER), 1, ((S3_WRITE_OP_HEADER *) S3SaveTableRecordPtr)->Width); - IDS_HDT_CONSOLE (S3_TRACE, "\n"); - ); - LibAmdIoWrite ( - ((S3_WRITE_OP_HEADER *) S3SaveTableRecordPtr)->Width, - (UINT16) ((S3_WRITE_OP_HEADER *) S3SaveTableRecordPtr)->Address, - (UINT8 *) S3SaveTableRecordPtr + sizeof (S3_WRITE_OP_HEADER), - StdHeader - ); - S3SaveTableRecordPtr = (UINT8 *) S3SaveTableRecordPtr + - sizeof (S3_WRITE_OP_HEADER) + - LibAmdAccessWidth (((S3_WRITE_OP_HEADER *) S3SaveTableRecordPtr)->Width); - break; - case SAVE_STATE_IO_READ_WRITE_OPCODE: - S3_SCRIPT_DEBUG_CODE ( - IDS_HDT_CONSOLE (S3_TRACE, " S3 Restore: %s Address: 0x%08x Data: ", S3SaveDebugOpcodeString (StdHeader, *(UINT16 *) S3SaveTableRecordPtr), (UINT16) ((S3_READ_WRITE_OP_HEADER*) S3SaveTableRecordPtr)->Address); - S3SaveDebugPrintHexArray ( - StdHeader, - (UINT8 *) S3SaveTableRecordPtr + sizeof (S3_READ_WRITE_OP_HEADER), - 1, - ((S3_READ_WRITE_OP_HEADER *) S3SaveTableRecordPtr)->Width - ); - IDS_HDT_CONSOLE (S3_TRACE, " Mask: "); - S3SaveDebugPrintHexArray ( - StdHeader, - (UINT8 *) S3SaveTableRecordPtr + sizeof (S3_READ_WRITE_OP_HEADER) + LibAmdAccessWidth (((S3_READ_WRITE_OP_HEADER *) S3SaveTableRecordPtr)->Width), - 1, - ((S3_READ_WRITE_OP_HEADER *) S3SaveTableRecordPtr)->Width - ); - IDS_HDT_CONSOLE (S3_TRACE, "\n"); - ); - LibAmdIoRMW ( - ((S3_READ_WRITE_OP_HEADER *) S3SaveTableRecordPtr)->Width, - (UINT16) ((S3_READ_WRITE_OP_HEADER*) S3SaveTableRecordPtr)->Address, - (UINT8 *) S3SaveTableRecordPtr + sizeof (S3_READ_WRITE_OP_HEADER), - (UINT8 *) S3SaveTableRecordPtr + sizeof (S3_READ_WRITE_OP_HEADER) + LibAmdAccessWidth (((S3_READ_WRITE_OP_HEADER *) S3SaveTableRecordPtr)->Width), - StdHeader - ); - S3SaveTableRecordPtr = (UINT8 *) S3SaveTableRecordPtr + - sizeof (S3_READ_WRITE_OP_HEADER) + - 2 * LibAmdAccessWidth (((S3_READ_WRITE_OP_HEADER *) S3SaveTableRecordPtr)->Width); - break; - case SAVE_STATE_MEM_WRITE_OPCODE: - S3_SCRIPT_DEBUG_CODE ( - IDS_HDT_CONSOLE (S3_TRACE, " S3 Restore: %s Address: 0x%08x Data: ", S3SaveDebugOpcodeString (StdHeader, *(UINT16 *) S3SaveTableRecordPtr), (UINT16) ((S3_WRITE_OP_HEADER *) S3SaveTableRecordPtr)->Address); - S3SaveDebugPrintHexArray (StdHeader, (UINT8 *) S3SaveTableRecordPtr + sizeof (S3_WRITE_OP_HEADER), 1, ((S3_WRITE_OP_HEADER *) S3SaveTableRecordPtr)->Width); - IDS_HDT_CONSOLE (S3_TRACE, "\n"); - ); - LibAmdMemWrite ( - ((S3_WRITE_OP_HEADER *) S3SaveTableRecordPtr)->Width, - ((S3_WRITE_OP_HEADER *) S3SaveTableRecordPtr)->Address, - (UINT8 *) S3SaveTableRecordPtr + sizeof (S3_WRITE_OP_HEADER), - StdHeader - ); - S3SaveTableRecordPtr = (UINT8 *) S3SaveTableRecordPtr + - sizeof (S3_WRITE_OP_HEADER) + - LibAmdAccessWidth (((S3_WRITE_OP_HEADER *) S3SaveTableRecordPtr)->Width); - break; - case SAVE_STATE_MEM_READ_WRITE_OPCODE: - S3_SCRIPT_DEBUG_CODE ( - IDS_HDT_CONSOLE (S3_TRACE, " S3 Restore: %s Address: 0x%08x Data: ", S3SaveDebugOpcodeString (StdHeader, *(UINT16 *) S3SaveTableRecordPtr), (UINT16) ((S3_READ_WRITE_OP_HEADER*) S3SaveTableRecordPtr)->Address); - S3SaveDebugPrintHexArray ( - StdHeader, - (UINT8 *) S3SaveTableRecordPtr + sizeof (S3_READ_WRITE_OP_HEADER), - 1, - ((S3_READ_WRITE_OP_HEADER *) S3SaveTableRecordPtr)->Width - ); - IDS_HDT_CONSOLE (S3_TRACE, " Mask: "); - S3SaveDebugPrintHexArray ( - StdHeader, - (UINT8 *) S3SaveTableRecordPtr + sizeof (S3_READ_WRITE_OP_HEADER) + LibAmdAccessWidth (((S3_READ_WRITE_OP_HEADER *) S3SaveTableRecordPtr)->Width), - 1, - ((S3_READ_WRITE_OP_HEADER *) S3SaveTableRecordPtr)->Width - ); - IDS_HDT_CONSOLE (S3_TRACE, "\n"); - ); - LibAmdMemRMW ( - ((S3_READ_WRITE_OP_HEADER *) S3SaveTableRecordPtr)->Width, - ((S3_READ_WRITE_OP_HEADER *) S3SaveTableRecordPtr)->Address, - (UINT8 *) S3SaveTableRecordPtr + sizeof (S3_READ_WRITE_OP_HEADER), - (UINT8 *) S3SaveTableRecordPtr + sizeof (S3_READ_WRITE_OP_HEADER) + LibAmdAccessWidth (((S3_READ_WRITE_OP_HEADER*) S3SaveTableRecordPtr)->Width), - StdHeader - ); - S3SaveTableRecordPtr = (UINT8 *) S3SaveTableRecordPtr + - sizeof (S3_READ_WRITE_OP_HEADER) + - 2 * LibAmdAccessWidth (((S3_READ_WRITE_OP_HEADER *) S3SaveTableRecordPtr)->Width); - break; - case SAVE_STATE_PCI_CONFIG_WRITE_OPCODE: - PciAddress.AddressValue = (UINT32) ((S3_WRITE_OP_HEADER *) S3SaveTableRecordPtr)->Address; - S3_SCRIPT_DEBUG_CODE ( - IDS_HDT_CONSOLE (S3_TRACE, " S3 Restore: %s Address: 0x%08x Data: ", S3SaveDebugOpcodeString (StdHeader, *(UINT16 *) S3SaveTableRecordPtr), (UINT16) ((S3_WRITE_OP_HEADER *) S3SaveTableRecordPtr)->Address); - S3SaveDebugPrintHexArray (StdHeader, (UINT8 *) S3SaveTableRecordPtr + sizeof (S3_WRITE_OP_HEADER), 1, ((S3_WRITE_OP_HEADER *) S3SaveTableRecordPtr)->Width); - IDS_HDT_CONSOLE (S3_TRACE, "\n"); - ); - LibAmdPciWrite ( - ((S3_WRITE_OP_HEADER *) S3SaveTableRecordPtr)->Width, - PciAddress, - (UINT8 *) S3SaveTableRecordPtr + sizeof (S3_WRITE_OP_HEADER), - StdHeader - ); - S3SaveTableRecordPtr = (UINT8 *) S3SaveTableRecordPtr + - sizeof (S3_WRITE_OP_HEADER) + - LibAmdAccessWidth (((S3_WRITE_OP_HEADER *) S3SaveTableRecordPtr)->Width); - break; - case SAVE_STATE_PCI_CONFIG_READ_WRITE_OPCODE: - PciAddress.AddressValue = (UINT32) ((S3_READ_WRITE_OP_HEADER *) S3SaveTableRecordPtr)->Address; - S3_SCRIPT_DEBUG_CODE ( - IDS_HDT_CONSOLE (S3_TRACE, " S3 Restore: %s Address: 0x%08x Data: ", S3SaveDebugOpcodeString (StdHeader, *(UINT16 *) S3SaveTableRecordPtr), (UINT16) ((S3_READ_WRITE_OP_HEADER*) S3SaveTableRecordPtr)->Address); - S3SaveDebugPrintHexArray ( - StdHeader, - (UINT8 *) S3SaveTableRecordPtr + sizeof (S3_READ_WRITE_OP_HEADER), - 1, - ((S3_READ_WRITE_OP_HEADER *) S3SaveTableRecordPtr)->Width - ); - IDS_HDT_CONSOLE (S3_TRACE, " Mask: "); - S3SaveDebugPrintHexArray ( - StdHeader, - (UINT8 *) S3SaveTableRecordPtr + sizeof (S3_READ_WRITE_OP_HEADER) + LibAmdAccessWidth (((S3_READ_WRITE_OP_HEADER *) S3SaveTableRecordPtr)->Width), - 1, - ((S3_READ_WRITE_OP_HEADER *) S3SaveTableRecordPtr)->Width - ); - IDS_HDT_CONSOLE (S3_TRACE, "\n"); - ); - LibAmdPciRMW ( - ((S3_READ_WRITE_OP_HEADER *) S3SaveTableRecordPtr)->Width, - PciAddress, - (UINT8 *) S3SaveTableRecordPtr + sizeof (S3_READ_WRITE_OP_HEADER), - (UINT8 *) S3SaveTableRecordPtr + sizeof (S3_READ_WRITE_OP_HEADER) + LibAmdAccessWidth (((S3_READ_WRITE_OP_HEADER *) S3SaveTableRecordPtr)->Width), - StdHeader - ); - S3SaveTableRecordPtr = (UINT8 *) S3SaveTableRecordPtr + - sizeof (S3_READ_WRITE_OP_HEADER) + - 2 * LibAmdAccessWidth (((S3_READ_WRITE_OP_HEADER *) S3SaveTableRecordPtr)->Width); - break; - case SAVE_STATE_STALL_OPCODE: - break; - case SAVE_STATE_INFORMATION_OPCODE: - IDS_HDT_CONSOLE (S3_TRACE, " S3 Restore: Info: [%s]\n", (UINT8 *) S3SaveTableRecordPtr + sizeof (S3_INFO_OP_HEADER)); - S3SaveTableRecordPtr = (UINT8 *) S3SaveTableRecordPtr + - sizeof (S3_INFO_OP_HEADER) + - ((S3_INFO_OP_HEADER*) S3SaveTableRecordPtr)->Length; - break; - case SAVE_STATE_DISPATCH_OPCODE: - S3_SCRIPT_DEBUG_CODE ( - IDS_HDT_CONSOLE (S3_TRACE, " S3 Restore: %s Function Id: 0x%02x, Context: ", S3SaveDebugOpcodeString (StdHeader, *(UINT16 *) S3SaveTableRecordPtr), ((S3_DISPATCH_OP_HEADER*) S3SaveTableRecordPtr)->FunctionId); - S3SaveDebugPrintHexArray ( - StdHeader, - (VOID*)((UINT8*) S3SaveTableRecordPtr + sizeof (S3_DISPATCH_OP_HEADER)), - ((S3_DISPATCH_OP_HEADER*) S3SaveTableRecordPtr)->Length, - AccessWidth8); - IDS_HDT_CONSOLE (S3_TRACE, "\n"); - ); - Index = 0; - while (S3DispatchFunctionTable[Index].FunctionId != 0) { - if (S3DispatchFunctionTable[Index].FunctionId == ((S3_DISPATCH_OP_HEADER*) S3SaveTableRecordPtr)->FunctionId) { - (S3DispatchFunctionTable[Index].Function) ( - StdHeader, - ((S3_DISPATCH_OP_HEADER*) S3SaveTableRecordPtr)->Length, - (VOID*)((UINT8*) S3SaveTableRecordPtr + sizeof (S3_DISPATCH_OP_HEADER)) - ); - break; - } - Index++; - } - ASSERT (S3DispatchFunctionTable[Index].FunctionId != 0); - S3SaveTableRecordPtr = (UINT8 *) S3SaveTableRecordPtr + - sizeof (S3_DISPATCH_OP_HEADER) + - ((S3_DISPATCH_OP_HEADER*) S3SaveTableRecordPtr)->Length; - break; - - case SAVE_STATE_IO_POLL_OPCODE: - S3_SCRIPT_DEBUG_CODE ( - IDS_HDT_CONSOLE (S3_TRACE, " S3 Restore: %s Address: 0x%04x Data: ", S3SaveDebugOpcodeString (StdHeader, *(UINT16 *) S3SaveTableRecordPtr), (UINT16) ((S3_POLL_OP_HEADER*) S3SaveTableRecordPtr)->Address); - S3SaveDebugPrintHexArray ( - StdHeader, - (UINT8 *) S3SaveTableRecordPtr + sizeof (S3_POLL_OP_HEADER), - 1, - ((S3_READ_WRITE_OP_HEADER *) S3SaveTableRecordPtr)->Width - ); - IDS_HDT_CONSOLE (S3_TRACE, " Mask: "); - S3SaveDebugPrintHexArray ( - StdHeader, - (UINT8 *) S3SaveTableRecordPtr + sizeof (S3_POLL_OP_HEADER) + LibAmdAccessWidth (((S3_POLL_OP_HEADER *) S3SaveTableRecordPtr)->Width), - 1, - ((S3_POLL_OP_HEADER *) S3SaveTableRecordPtr)->Width - ); - ) - LibAmdIoPoll ( - ((S3_POLL_OP_HEADER *) S3SaveTableRecordPtr)->Width, - (UINT16) ((S3_POLL_OP_HEADER *) S3SaveTableRecordPtr)->Address, - (UINT8 *) S3SaveTableRecordPtr + sizeof (S3_POLL_OP_HEADER), - (UINT8 *) S3SaveTableRecordPtr + sizeof (S3_POLL_OP_HEADER) + LibAmdAccessWidth (((S3_POLL_OP_HEADER*) S3SaveTableRecordPtr)->Width), - ((S3_POLL_OP_HEADER*) S3SaveTableRecordPtr)->Delay, - StdHeader - ); - S3SaveTableRecordPtr = (UINT8 *) S3SaveTableRecordPtr + - sizeof (S3_POLL_OP_HEADER) + - 2 * LibAmdAccessWidth (((S3_POLL_OP_HEADER *) S3SaveTableRecordPtr)->Width); - break; - case SAVE_STATE_MEM_POLL_OPCODE: - S3_SCRIPT_DEBUG_CODE ( - IDS_HDT_CONSOLE (S3_TRACE, " S3 Restore: %s Address: 0x%08x Data: ", S3SaveDebugOpcodeString (StdHeader, *(UINT16 *) S3SaveTableRecordPtr), (UINT32) ((S3_POLL_OP_HEADER*) S3SaveTableRecordPtr)->Address); - S3SaveDebugPrintHexArray ( - StdHeader, - (UINT8 *) S3SaveTableRecordPtr + sizeof (S3_POLL_OP_HEADER), - 1, - ((S3_POLL_OP_HEADER *) S3SaveTableRecordPtr)->Width - ); - IDS_HDT_CONSOLE (S3_TRACE, " Mask: "); - S3SaveDebugPrintHexArray ( - StdHeader, - (UINT8 *) S3SaveTableRecordPtr + sizeof (S3_POLL_OP_HEADER) + LibAmdAccessWidth (((S3_POLL_OP_HEADER *) S3SaveTableRecordPtr)->Width), - 1, - ((S3_POLL_OP_HEADER *) S3SaveTableRecordPtr)->Width - ); - ) - LibAmdMemPoll ( - ((S3_POLL_OP_HEADER *) S3SaveTableRecordPtr)->Width, - ((S3_POLL_OP_HEADER *) S3SaveTableRecordPtr)->Address, - (UINT8 *) S3SaveTableRecordPtr + sizeof (S3_POLL_OP_HEADER), - (UINT8 *) S3SaveTableRecordPtr + sizeof (S3_POLL_OP_HEADER) + LibAmdAccessWidth (((S3_POLL_OP_HEADER *) S3SaveTableRecordPtr)->Width), - ((S3_POLL_OP_HEADER *) S3SaveTableRecordPtr)->Delay, - StdHeader - ); - S3SaveTableRecordPtr = (UINT8 *) S3SaveTableRecordPtr + - sizeof (S3_POLL_OP_HEADER) + - 2 * LibAmdAccessWidth (((S3_POLL_OP_HEADER *) S3SaveTableRecordPtr)->Width); - break; - case SAVE_STATE_PCI_CONFIG_POLL_OPCODE: - PciAddress.AddressValue = (UINT32) ((S3_POLL_OP_HEADER *) S3SaveTableRecordPtr)->Address; - S3_SCRIPT_DEBUG_CODE ( - IDS_HDT_CONSOLE (S3_TRACE, " S3 Restore: %s Address: 0x%08x Data: ", S3SaveDebugOpcodeString (StdHeader, *(UINT16 *) S3SaveTableRecordPtr), (UINT32) ((S3_POLL_OP_HEADER*) S3SaveTableRecordPtr)->Address); - S3SaveDebugPrintHexArray ( - StdHeader, - (UINT8 *) S3SaveTableRecordPtr + sizeof (S3_POLL_OP_HEADER), - 1, - ((S3_POLL_OP_HEADER *) S3SaveTableRecordPtr)->Width - ); - IDS_HDT_CONSOLE (S3_TRACE, " Mask: "); - S3SaveDebugPrintHexArray ( - StdHeader, - (UINT8 *) S3SaveTableRecordPtr + sizeof (S3_POLL_OP_HEADER) + LibAmdAccessWidth (((S3_POLL_OP_HEADER *) S3SaveTableRecordPtr)->Width), - 1, - ((S3_POLL_OP_HEADER *) S3SaveTableRecordPtr)->Width - ); - ) - LibAmdPciPoll ( - ((S3_POLL_OP_HEADER *) S3SaveTableRecordPtr)->Width, - PciAddress, - (UINT8 *) S3SaveTableRecordPtr + sizeof (S3_POLL_OP_HEADER), - (UINT8 *) S3SaveTableRecordPtr + sizeof (S3_POLL_OP_HEADER) + LibAmdAccessWidth (((S3_POLL_OP_HEADER *) S3SaveTableRecordPtr)->Width), - ((S3_POLL_OP_HEADER *) S3SaveTableRecordPtr)->Delay, - StdHeader - ); - S3SaveTableRecordPtr = (UINT8 *) S3SaveTableRecordPtr + - sizeof (S3_POLL_OP_HEADER) + - 2 * LibAmdAccessWidth (((S3_POLL_OP_HEADER *) S3SaveTableRecordPtr)->Width); - break; - default: - IDS_HDT_CONSOLE (S3_TRACE, " ERROR!!! Invalid S3 restore opcode\n"); - ASSERT (FALSE); - return AGESA_ERROR; - } - } - IDS_HDT_CONSOLE (S3_TRACE, " End S3 Restore \n"); - return AGESA_SUCCESS; -} - diff --git a/src/vendorcode/amd/agesa/f12/Proc/Common/S3SaveState.c b/src/vendorcode/amd/agesa/f12/Proc/Common/S3SaveState.c deleted file mode 100644 index e1946264cb..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/Common/S3SaveState.c +++ /dev/null @@ -1,651 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * S3 save/restore script - * - * - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: GNB - * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $ - * - */ -/* -***************************************************************************** -* -* Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* *************************************************************************** -* -*/ - -/*---------------------------------------------------------------------------------------- - * M O D U L E S U S E D - *---------------------------------------------------------------------------------------- - */ -#include "Porting.h" -#include "AMD.h" -#include "AGESA.h" -#include "Ids.h" -#include "amdlib.h" -#include "heapManager.h" -#include "S3SaveState.h" -#include "Filecode.h" -CODE_GROUP (G3_DXE) -RDATA_GROUP (G3_DXE) - -#define FILECODE PROC_COMMON_S3SAVESTATE_FILECODE -/*---------------------------------------------------------------------------------------- - * D E F I N I T I O N S A N D M A C R O S - *---------------------------------------------------------------------------------------- - */ - - -/*---------------------------------------------------------------------------------------- - * T Y P E D E F S A N D S T R U C T U R E S - *---------------------------------------------------------------------------------------- - */ -extern S3_SCRIPT_CONFIGURATION OptionS3ScriptConfiguration; - -/*---------------------------------------------------------------------------------------- - * P R O T O T Y P E S O F L O C A L F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ -AGESA_STATUS -S3SaveStateExtendTableLenth ( - IN AMD_CONFIG_PARAMS *StdHeader, - IN OUT S3_SAVE_TABLE_HEADER **S3SaveTable - ); - -/*----------------------------------------------------------------------------------------*/ -/** - * Initialize S3 Script framework - * - * - * - * @param[in] StdHeader Pointer to standard header - */ -AGESA_STATUS -S3ScriptInit ( - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - return OptionS3ScriptConfiguration.Init (StdHeader); -} - -/*----------------------------------------------------------------------------------------*/ -/** - * Initialize S3 Script framework - * - * - * - * @param[in] StdHeader Pointer to standard header - */ -AGESA_STATUS -S3ScriptInitStateStub ( - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - return AGESA_SUCCESS; -} - -/*----------------------------------------------------------------------------------------*/ -/** - * Initialize S3 Script framework - * - * - * - * @param[in] StdHeader Pointer to standard header - */ -AGESA_STATUS -S3ScriptInitState ( - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - AGESA_STATUS Status; - ALLOCATE_HEAP_PARAMS AllocHeapParams; - - AllocHeapParams.RequestedBufferSize = S3_TABLE_LENGTH; - AllocHeapParams.BufferHandle = AMD_S3_SCRIPT_SAVE_TABLE_HANDLE; - AllocHeapParams.Persist = HEAP_SYSTEM_MEM; - Status = HeapAllocateBuffer (&AllocHeapParams, StdHeader); - if (Status == AGESA_SUCCESS) { - ((S3_SAVE_TABLE_HEADER *) AllocHeapParams.BufferPtr)->TableLength = S3_TABLE_LENGTH; - ((S3_SAVE_TABLE_HEADER *) AllocHeapParams.BufferPtr)->SaveOffset = sizeof (S3_SAVE_TABLE_HEADER); - ((S3_SAVE_TABLE_HEADER *) AllocHeapParams.BufferPtr)->Locked = FALSE; - } - return Status; -} - -/*----------------------------------------------------------------------------------------*/ -/** - * Initialize S3 Script framework - * - * - * - * @param[in] StdHeader Pointer to standard header - * @param[in,out] S3SaveTable S3 save table header - */ -AGESA_STATUS -S3SaveStateExtendTableLenth ( - IN AMD_CONFIG_PARAMS *StdHeader, - IN OUT S3_SAVE_TABLE_HEADER **S3SaveTable - ) -{ - AGESA_STATUS Status; - ALLOCATE_HEAP_PARAMS AllocHeapParams; - VOID *TempBuffer; - UINT16 NewTableLength; - UINT16 CurrentTableLength; - //Allocate temporary buffer - NewTableLength = (*S3SaveTable)->TableLength + S3_TABLE_LENGTH_INCREMENT; - AllocHeapParams.RequestedBufferSize = NewTableLength; - AllocHeapParams.BufferHandle = AMD_S3_SCRIPT_TEMP_BUFFER_HANDLE; - AllocHeapParams.Persist = StdHeader->HeapStatus; - Status = HeapAllocateBuffer (&AllocHeapParams, StdHeader); - if (Status != AGESA_SUCCESS) { - return Status; - } - //Save current table length - CurrentTableLength = (*S3SaveTable)->TableLength; - //Update table length - (*S3SaveTable)->TableLength = NewTableLength; - //Copy S3 save toable to temporary location - LibAmdMemCopy (AllocHeapParams.BufferPtr, *S3SaveTable, CurrentTableLength, StdHeader); - //Save pointer to temp buffer - TempBuffer = AllocHeapParams.BufferPtr; - // Free original S3 save buffer - HeapDeallocateBuffer (AMD_S3_SCRIPT_SAVE_TABLE_HANDLE, StdHeader); - - AllocHeapParams.RequestedBufferSize = NewTableLength; - AllocHeapParams.BufferHandle = AMD_S3_SCRIPT_SAVE_TABLE_HANDLE; - AllocHeapParams.Persist = StdHeader->HeapStatus; - Status = HeapAllocateBuffer (&AllocHeapParams, StdHeader); - if (Status != AGESA_SUCCESS) { - return Status; - } - LibAmdMemCopy (AllocHeapParams.BufferPtr, TempBuffer, AllocHeapParams.RequestedBufferSize, StdHeader); - *S3SaveTable = (S3_SAVE_TABLE_HEADER*) AllocHeapParams.BufferPtr; - HeapDeallocateBuffer (AMD_S3_SCRIPT_TEMP_BUFFER_HANDLE, StdHeader); - return Status; -} - - -/*----------------------------------------------------------------------------------------*/ -/** - * Initialize S3 Script framework - * - * - * - * @param[in] StdHeader Pointer to standard header - * @param[out] S3SaveTable S3 save table header - */ -AGESA_STATUS -S3ScriptGetS3SaveTable ( - IN AMD_CONFIG_PARAMS *StdHeader, - OUT S3_SAVE_TABLE_HEADER **S3SaveTable - ) -{ - AGESA_STATUS Status; - LOCATE_HEAP_PTR LocHeapParams; - LocHeapParams.BufferHandle = AMD_S3_SCRIPT_SAVE_TABLE_HANDLE; - Status = HeapLocateBuffer (&LocHeapParams, StdHeader); - if (Status != AGESA_SUCCESS) { - *S3SaveTable = NULL; - return Status; - } - *S3SaveTable = (S3_SAVE_TABLE_HEADER *) LocHeapParams.BufferPtr; - return AGESA_SUCCESS; -} - - -/*----------------------------------------------------------------------------------------*/ -/** - * Save S3 write opcode - * - * - * - * @param[in] StdHeader Pointer to standard header - * @param[in] OpCode Operation opcode - * @param[in] Width Width - * @param[in] Address Register address - * @param[in] Count Number of register writes - * @param[in] Buffer Pointer to write buffer - */ -AGESA_STATUS -S3SaveStateSaveWriteOp ( - IN AMD_CONFIG_PARAMS *StdHeader, - IN UINT16 OpCode, - IN ACCESS_WIDTH Width, - IN UINT64 Address, - IN UINT32 Count, - IN VOID *Buffer - ) -{ - S3_SAVE_TABLE_HEADER *S3SaveTablePtr; - S3_WRITE_OP_HEADER *SaveOffsetPtr; - UINT32 OpCodeLength; - UINT32 WidthLength; - AGESA_STATUS Status; - - Status = S3ScriptGetS3SaveTable (StdHeader, &S3SaveTablePtr); - if (Status != AGESA_SUCCESS) { - return Status; - } - if (S3SaveTablePtr->Locked) { - return AGESA_UNSUPPORTED; - } - WidthLength = LibAmdAccessWidth (Width); - OpCodeLength = sizeof (S3_WRITE_OP_HEADER) + WidthLength * Count; - if ((S3SaveTablePtr->SaveOffset + OpCodeLength) > S3SaveTablePtr->TableLength) { - Status = S3SaveStateExtendTableLenth (StdHeader, &S3SaveTablePtr); - if (Status != AGESA_SUCCESS) { - return Status; - } - } - S3_SCRIPT_DEBUG_CODE ( - IDS_HDT_CONSOLE (S3_TRACE, " S3 Save: %s Address: 0x%08x Data: ", S3SaveDebugOpcodeString (StdHeader, OpCode), Address); - S3SaveDebugPrintHexArray (StdHeader, Buffer, Count, Width); - IDS_HDT_CONSOLE (S3_TRACE, "\n"); - ); - SaveOffsetPtr = (S3_WRITE_OP_HEADER *) ((UINT8 *) S3SaveTablePtr + S3SaveTablePtr->SaveOffset); - SaveOffsetPtr->OpCode = OpCode; - SaveOffsetPtr->Width = Width; - SaveOffsetPtr->Count = Count; - SaveOffsetPtr->Address = Address; - LibAmdMemCopy ( - (UINT8 *) SaveOffsetPtr + sizeof (S3_WRITE_OP_HEADER), - Buffer, - WidthLength * Count, - StdHeader - ); - S3SaveTablePtr->SaveOffset += OpCodeLength; - return AGESA_SUCCESS; -} - -/*----------------------------------------------------------------------------------------*/ -/** - * Save S3 write opcode - * - * - * - * @param[in] StdHeader Pointer to standard header - * @param[in] OpCode Operation opcode - * @param[in] Width Width - * @param[in] Address Register address - * @param[in] Data Pointer to data - * @param[in] DataMask Pointer data mask - */ -AGESA_STATUS -S3SaveStateSaveReadWriteOp ( - IN AMD_CONFIG_PARAMS *StdHeader, - IN UINT16 OpCode, - IN ACCESS_WIDTH Width, - IN UINT64 Address, - IN VOID *Data, - IN VOID *DataMask - ) -{ - - S3_SAVE_TABLE_HEADER *S3SaveTablePtr; - S3_READ_WRITE_OP_HEADER *SaveOffsetPtr; - UINT32 OpCodeLength; - UINT32 WidthLength; - AGESA_STATUS Status; - - Status = S3ScriptGetS3SaveTable (StdHeader, &S3SaveTablePtr); - if (Status != AGESA_SUCCESS) { - return Status; - } - if (S3SaveTablePtr->Locked) { - return AGESA_UNSUPPORTED; - } - WidthLength = LibAmdAccessWidth (Width); - OpCodeLength = sizeof (S3_READ_WRITE_OP_HEADER) + WidthLength * 2; - if ((S3SaveTablePtr->SaveOffset + OpCodeLength) > S3SaveTablePtr->TableLength) { - Status = S3SaveStateExtendTableLenth (StdHeader, &S3SaveTablePtr); - if (Status != AGESA_SUCCESS) { - return Status; - } - } - S3_SCRIPT_DEBUG_CODE ( - IDS_HDT_CONSOLE (S3_TRACE, " S3 Save: %s Address: 0x%08x Data: ", S3SaveDebugOpcodeString (StdHeader, OpCode), Address); - S3SaveDebugPrintHexArray (StdHeader, Data, 1, Width); - IDS_HDT_CONSOLE (S3_TRACE, " Mask: "); - S3SaveDebugPrintHexArray (StdHeader, DataMask, 1, Width); - IDS_HDT_CONSOLE (S3_TRACE, "\n"); - ); - SaveOffsetPtr = (S3_READ_WRITE_OP_HEADER *) ((UINT8 *) S3SaveTablePtr + S3SaveTablePtr->SaveOffset); - SaveOffsetPtr->OpCode = OpCode; - SaveOffsetPtr->Width = Width; - SaveOffsetPtr->Address = Address; - - LibAmdMemCopy ( - (UINT8 *) SaveOffsetPtr + sizeof (S3_READ_WRITE_OP_HEADER), - Data, - WidthLength, - StdHeader - ); - LibAmdMemCopy ( - (UINT8 *) SaveOffsetPtr + sizeof (S3_READ_WRITE_OP_HEADER) + WidthLength, - DataMask, - WidthLength, - StdHeader - ); - S3SaveTablePtr->SaveOffset += OpCodeLength; - return AGESA_SUCCESS; -} - - -/*----------------------------------------------------------------------------------------*/ -/** - * Save S3 poll opcode - * - * - * - * @param[in] StdHeader Pointer to standard header - * @param[in] OpCode Operation opcode - * @param[in] Width Width - * @param[in] Address Register address - * @param[in] Data Pointer to data - * @param[in] DataMask Pointer data mask - * @param[in] Delay Time delay for poll - */ -AGESA_STATUS -S3SaveStateSavePollOp ( - IN AMD_CONFIG_PARAMS *StdHeader, - IN UINT16 OpCode, - IN ACCESS_WIDTH Width, - IN UINT64 Address, - IN VOID *Data, - IN VOID *DataMask, - IN UINT64 Delay - ) -{ - - S3_SAVE_TABLE_HEADER *S3SaveTablePtr; - S3_POLL_OP_HEADER *SaveOffsetPtr; - UINT32 OpCodeLength; - UINT32 WidthLength; - AGESA_STATUS Status; - - Status = S3ScriptGetS3SaveTable (StdHeader, &S3SaveTablePtr); - if (Status != AGESA_SUCCESS) { - return Status; - } - if (S3SaveTablePtr->Locked) { - return AGESA_UNSUPPORTED; - } - WidthLength = LibAmdAccessWidth (Width); - OpCodeLength = sizeof (S3_POLL_OP_HEADER) + WidthLength * 2; - if ((S3SaveTablePtr->SaveOffset + OpCodeLength) > S3SaveTablePtr->TableLength) { - Status = S3SaveStateExtendTableLenth (StdHeader, &S3SaveTablePtr); - if (Status != AGESA_SUCCESS) { - return Status; - } - } - S3_SCRIPT_DEBUG_CODE ( - IDS_HDT_CONSOLE (S3_TRACE, " S3 Save: %s Address: 0x%08x Data: ", S3SaveDebugOpcodeString (StdHeader, OpCode), Address); - S3SaveDebugPrintHexArray (StdHeader, Data, 1, Width); - IDS_HDT_CONSOLE (S3_TRACE, " Mask: "); - S3SaveDebugPrintHexArray (StdHeader, DataMask, 1, Width); - IDS_HDT_CONSOLE (S3_TRACE, "\n"); - ); - SaveOffsetPtr = (S3_POLL_OP_HEADER *) ((UINT8 *) S3SaveTablePtr + S3SaveTablePtr->SaveOffset); - SaveOffsetPtr->OpCode = OpCode; - SaveOffsetPtr->Width = Width; - SaveOffsetPtr->Delay = Delay; - SaveOffsetPtr->Address = Address; - - LibAmdMemCopy ( - (UINT8 *) SaveOffsetPtr + sizeof (S3_POLL_OP_HEADER), - Data, - WidthLength, - StdHeader - ); - LibAmdMemCopy ( - (UINT8 *) SaveOffsetPtr + sizeof (S3_POLL_OP_HEADER) + WidthLength, - DataMask, - WidthLength, - StdHeader - ); - S3SaveTablePtr->SaveOffset += OpCodeLength; - return AGESA_SUCCESS; -} - -/*----------------------------------------------------------------------------------------*/ -/** - * Save S3 info opcode - * - * - * - * @param[in] StdHeader Pointer to standard header - * @param[in] OpCode Operation opcode - * @param[in] InformationLength Info length - * @param[in] Information Pointer to information - */ -AGESA_STATUS -S3SaveStateSaveInfoOp ( - IN AMD_CONFIG_PARAMS *StdHeader, - IN UINT16 OpCode, - IN UINT32 InformationLength, - IN VOID *Information - ) -{ - - S3_SAVE_TABLE_HEADER *S3SaveTablePtr; - S3_INFO_OP_HEADER *SaveOffsetPtr; - UINT32 OpCodeLength; - - AGESA_STATUS Status; - - Status = S3ScriptGetS3SaveTable (StdHeader, &S3SaveTablePtr); - if (Status != AGESA_SUCCESS) { - return Status; - } - if (S3SaveTablePtr->Locked) { - return AGESA_UNSUPPORTED; - } - OpCodeLength = sizeof (S3_INFO_OP_HEADER) + InformationLength; - if ((S3SaveTablePtr->SaveOffset + OpCodeLength) > S3SaveTablePtr->TableLength) { - Status = S3SaveStateExtendTableLenth (StdHeader, &S3SaveTablePtr); - if (Status != AGESA_SUCCESS) { - return Status; - } - } - SaveOffsetPtr = (S3_INFO_OP_HEADER *) ((UINT8 *) S3SaveTablePtr + S3SaveTablePtr->SaveOffset); - SaveOffsetPtr->OpCode = OpCode; - SaveOffsetPtr->Length = InformationLength; - S3_SCRIPT_DEBUG_CODE ( - IDS_HDT_CONSOLE (S3_TRACE, " S3 Save: Info: %s \n", Information); - ); - LibAmdMemCopy ( - (UINT8 *) SaveOffsetPtr + sizeof (S3_INFO_OP_HEADER), - Information, - InformationLength, - StdHeader - ); - S3SaveTablePtr->SaveOffset += OpCodeLength; - return AGESA_SUCCESS; -} - -/*----------------------------------------------------------------------------------------*/ -/** - * Save S3 dispatch opcode - * - * - * - * @param[in] StdHeader Pointer to standard header - * @param[in] OpCode Operation opcode - * @param[in] FunctionId Function ID - * @param[in] ContextLength Context length - * @param[in] Context Pointer to Context - */ -AGESA_STATUS -S3SaveStateSaveDispatchOp ( - IN AMD_CONFIG_PARAMS *StdHeader, - IN UINT16 OpCode, - IN UINT16 FunctionId, - IN UINT16 ContextLength, - IN VOID *Context - ) -{ - - S3_SAVE_TABLE_HEADER *S3SaveTablePtr; - S3_DISPATCH_OP_HEADER *SaveOffsetPtr; - UINT32 OpCodeLength; - AGESA_STATUS Status; - - Status = S3ScriptGetS3SaveTable (StdHeader, &S3SaveTablePtr); - if (Status != AGESA_SUCCESS) { - return Status; - } - if (S3SaveTablePtr->Locked) { - return AGESA_UNSUPPORTED; - } - OpCodeLength = sizeof (S3_DISPATCH_OP_HEADER) + ContextLength; - if ((S3SaveTablePtr->SaveOffset + OpCodeLength) > S3SaveTablePtr->TableLength) { - Status = S3SaveStateExtendTableLenth (StdHeader, &S3SaveTablePtr); - if (Status != AGESA_SUCCESS) { - return Status; - } - } - S3_SCRIPT_DEBUG_CODE ( - IDS_HDT_CONSOLE (S3_TRACE, " S3 Save: %s Function Id: 0x%02x, Context: ", S3SaveDebugOpcodeString (StdHeader, OpCode), FunctionId); - S3SaveDebugPrintHexArray (StdHeader, Context, ContextLength, AccessWidth8); - IDS_HDT_CONSOLE (S3_TRACE, "\n"); - ); - SaveOffsetPtr = (S3_DISPATCH_OP_HEADER *) ((UINT8 *) S3SaveTablePtr + S3SaveTablePtr->SaveOffset); - SaveOffsetPtr->OpCode = OpCode; - SaveOffsetPtr->Length = ContextLength; - SaveOffsetPtr->FunctionId = FunctionId; - LibAmdMemCopy ( - (UINT8 *) SaveOffsetPtr + sizeof (S3_DISPATCH_OP_HEADER), - Context, - ContextLength, - StdHeader - ); - - S3SaveTablePtr->SaveOffset += OpCodeLength; - return AGESA_SUCCESS; -} - - - - -/*----------------------------------------------------------------------------------------*/ -/** - * Save S3 debug support - * - * - * - * @param[in] StdHeader Pointer to standard header - * @param[in] Op Opcode - */ -CHAR8* -S3SaveDebugOpcodeString ( - IN AMD_CONFIG_PARAMS *StdHeader, - IN UINT16 Op - ) -{ - switch (Op) { - case SAVE_STATE_IO_WRITE_OPCODE: - return (CHAR8 *)"IO WR"; - case SAVE_STATE_IO_READ_WRITE_OPCODE: - return (CHAR8 *)"IO RD/WR"; - case SAVE_STATE_IO_POLL_OPCODE: - return (CHAR8 *)"IO POLL"; - case SAVE_STATE_MEM_WRITE_OPCODE: - return (CHAR8 *)"MEM WR"; - case SAVE_STATE_MEM_READ_WRITE_OPCODE: - return (CHAR8 *)"MEM RD/WR"; - case SAVE_STATE_MEM_POLL_OPCODE: - return (CHAR8 *)"MEM POLL"; - case SAVE_STATE_PCI_CONFIG_WRITE_OPCODE: - return (CHAR8 *)"PCI WR"; - case SAVE_STATE_PCI_CONFIG_READ_WRITE_OPCODE: - return (CHAR8 *)"PCI RD/WR"; - case SAVE_STATE_PCI_CONFIG_POLL_OPCODE: - return (CHAR8 *)"PCI POLL"; - case SAVE_STATE_STALL_OPCODE: - return (CHAR8 *)"STALL"; - case SAVE_STATE_DISPATCH_OPCODE: - return (CHAR8 *)"DISPATCH"; - default: - IDS_ERROR_TRAP; - } - return (CHAR8 *)"!!! Unrecognize opcode !!!"; -} - - -/*----------------------------------------------------------------------------------------*/ -/** - * Save S3 debug support - * - * - * - * @param[in] StdHeader Pointer to standard header - * @param[in] Array Array - * @param[in] Count Count of element in array - * @param[in] Width Array Element width - */ -VOID -S3SaveDebugPrintHexArray ( - IN AMD_CONFIG_PARAMS *StdHeader, - IN VOID *Array, - IN UINT32 Count, - IN ACCESS_WIDTH Width - ) -{ - UINTN Index; - - for (Index = 0; Index < Count; Index++) { - switch (Width) { - case AccessWidth8: - case AccessS3SaveWidth8: - IDS_HDT_CONSOLE (S3_TRACE, "0x%02x", *((UINT8*)Array + Index)); - break; - case AccessWidth16: - case AccessS3SaveWidth16: - IDS_HDT_CONSOLE (S3_TRACE, "0x%04x", *((UINT16*)Array + Index)); - break; - case AccessWidth32: - case AccessS3SaveWidth32: - IDS_HDT_CONSOLE (S3_TRACE, "0x%08x", *((UINT32*)Array + Index)); - break; - case AccessWidth64: - case AccessS3SaveWidth64: - IDS_HDT_CONSOLE (S3_TRACE, "0x%08x%08x", ((UINT32*) ((UINT64*)Array + Index)[1], ((UINT32*) ((UINT64*)Array + Index))[0])); - break; - default: - IDS_ERROR_TRAP; - } - if (Index < (Count - 1)) { - IDS_HDT_CONSOLE (S3_TRACE, ", "); - } - } -} diff --git a/src/vendorcode/amd/agesa/f12/Proc/Common/S3SaveState.h b/src/vendorcode/amd/agesa/f12/Proc/Common/S3SaveState.h deleted file mode 100644 index c28728659d..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/Common/S3SaveState.h +++ /dev/null @@ -1,358 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * Various PCI service routines. - * - * - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: GNB - * @e \$Revision: 49526 $ @e \$Date: 2011-03-25 00:52:37 +0800 (Fri, 25 Mar 2011) $ - * - */ -/* -***************************************************************************** -* -* Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* *************************************************************************** -* -*/ - -#ifndef _S3SAVESTATE_H_ -#define _S3SAVESTATE_H_ - -#pragma pack (push, 1) - -#ifndef S3_SCRIPT_DEBUG_CODE - #define S3_SCRIPT_DEBUG_CODE(Code) Code -#endif - -/// Dispatch function ID repository -typedef enum { - NbSmuIndirectWriteS3Script_ID = 1, ///< GNB SMU service request function ID. - NbSmuServiceRequestS3Script_ID, ///< GNB PCIe late restore function ID. - PcieLateRestoreS3Script_ID, ///< GNB SMU indirect write. - GnbSmuServiceRequestV4S3Script_ID, ///< SMU service request - GnbLibStallS3Script_ID ///< Stall request -} S3_DISPATCH_FUNCTION_ID; - -#define SAVE_STATE_IO_WRITE_OPCODE 0x00 -#define SAVE_STATE_IO_READ_WRITE_OPCODE 0x01 -#define SAVE_STATE_MEM_WRITE_OPCODE 0x02 -#define SAVE_STATE_MEM_READ_WRITE_OPCODE 0x03 -#define SAVE_STATE_PCI_CONFIG_WRITE_OPCODE 0x04 -#define SAVE_STATE_PCI_CONFIG_READ_WRITE_OPCODE 0x05 -#define SAVE_STATE_STALL_OPCODE 0x07 -#define SAVE_STATE_INFORMATION_OPCODE 0x0A -#define SAVE_STATE_IO_POLL_OPCODE 0x0D -#define SAVE_STATE_MEM_POLL_OPCODE 0x0E -#define SAVE_STATE_PCI_CONFIG_POLL_OPCODE 0x0F -#define SAVE_STATE_DISPATCH_OPCODE 0x20 -#define SAVE_STATE_BREAKPOINT_OPCODE 0x21 - - -#define S3_TABLE_LENGTH 8 * 1024 -#define S3_TABLE_LENGTH_INCREMENT 1 * 1024 - -/// S3 Save Table -typedef struct { - UINT16 TableLength; ///< Table Length - UINT32 SaveOffset; ///< Save Location - BOOLEAN Locked; ///< Locked -} S3_SAVE_TABLE_HEADER; - -/// S3 write operation header -typedef struct { - UINT16 OpCode; ///< Opcode - ACCESS_WIDTH Width; ///< Data width (byte, word, dword) - UINT64 Address; ///< Register address - UINT32 Count; ///< Write count -} S3_WRITE_OP_HEADER; - -/// S3 Read and Write Operation header -typedef struct { - UINT16 OpCode; ///< Opcode - ACCESS_WIDTH Width; ///< Data width (byte, word, dword) - UINT64 Address; ///< Register Address -} S3_READ_WRITE_OP_HEADER; - -/// S3 Poll operation header -typedef struct { - UINT16 OpCode; ///< Opcode - ACCESS_WIDTH Width; ///< Data width (byte, word, dword) - UINT64 Address; ///< Register address - UINT64 Delay; ///< Time delay -} S3_POLL_OP_HEADER; - -/// Information operation header -typedef struct { - UINT16 OpCode; ///< Opcode - UINT32 Length; ///< Length of info -} S3_INFO_OP_HEADER; - -/// Dispatch operation header -typedef struct { - UINT16 OpCode; ///< Opcode - UINT16 FunctionId; ///< Function ID - UINT16 Length; ///< Length in bytes of the context -} S3_DISPATCH_OP_HEADER; - - -typedef VOID S3_DISPATCH_FUNCTION ( - IN AMD_CONFIG_PARAMS *StdHeader, - IN UINT16 ContextLength, - IN VOID *Context - ); - -/// Dispatch function table entry -typedef struct { - UINT16 FunctionId; /// - -#pragma pack (push, 1) - -#define GNB_DEADLOOP() \ -{ \ - VOLATILE BOOLEAN k; \ - k = TRUE; \ - while (k) { \ - } \ -} -#ifdef IDSOPT_TRACING_ENABLED - #if (IDSOPT_TRACING_ENABLED == TRUE) - #define GNB_TRACE_ENABLE - #endif -#endif - - -#ifndef GNB_DEBUG_CODE - #ifdef GNB_TRACE_ENABLE - #define GNB_DEBUG_CODE(Code) Code - #else - #define GNB_DEBUG_CODE(Code) - #endif -#endif - -#define OFF 0 - -#define PVOID UINT64 - -#define GnbLibGetHeader(x) ((AMD_CONFIG_PARAMS*) (intptr_t) (x)->StdHeader) - -#define AGESA_STATUS_UPDATE(Current, Aggregated) \ -if (Current > Aggregated) { \ - Aggregated = Current; \ -} - -#ifndef offsetof - #define offsetof(s, m) (UINTN)&(((s *)0)->m) -#endif - - -//Table properties - -#define TABLE_PROPERTY_DEAFULT 0x00000000 -#define TABLE_PROPERTY_IGFX_DISABLED 0x00000001 -#define TABLE_PROPERTY_IOMMU_DISABLED 0x00000002 -#define TABLE_PROPERTY_LCLK_DEEP_SLEEP 0x00000004 -#define TABLE_PROPERTY_ORB_CLK_GATING 0x00000008 -#define TABLE_PROPERTY_IOC_LCLK_CLOCK_GATING 0x00000010 -#define TABLE_PROPERTY_IOC_SCLK_CLOCK_GATING 0x00000020 - -#define TABLE_PROPERTY_IOMMU_L1_CLOCK_GATING 0x00000040 -#define TABLE_PROPERTY_IOMMU_L2_CLOCK_GATING 0x00000080 - -//Register access flags Flags -#define GNB_REG_ACC_FLAG_S3SAVE 0x00000001 - -/// LCLK DPM enable control -typedef enum { - LclkDpmDisabled, ///GnbFeature != NULL) { - Status = ConfigTable->GnbFeature (StdHeader); - AGESA_STATUS_UPDATE (Status, AgesaStatus); - ConfigTable++; - } - return AgesaStatus; -} - - -/*----------------------------------------------------------------------------------------*/ -/** - * Feature stub function - * - * - */ - -AGESA_STATUS -GnbCommonFeatureStub ( - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - return AGESA_SUCCESS; -} \ No newline at end of file diff --git a/src/vendorcode/amd/agesa/f12/Proc/GNB/Common/GnbLibFeatures.h b/src/vendorcode/amd/agesa/f12/Proc/GNB/Common/GnbLibFeatures.h deleted file mode 100644 index 83a874c96e..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/GNB/Common/GnbLibFeatures.h +++ /dev/null @@ -1,55 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * GNB register access services. - * - * - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: GNB - * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $ - * - */ -/* -***************************************************************************** -* -* Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* *************************************************************************** -* -*/ -#ifndef _GNBLIBFEATURES_H_ -#define _GNBLIBFEATURES_H_ - - -AGESA_STATUS -GnbLibDispatchFeatures ( - IN OPTION_GNB_CONFIGURATION *ConfigTable, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -#endif diff --git a/src/vendorcode/amd/agesa/f12/Proc/GNB/Common/GnbPcie.h b/src/vendorcode/amd/agesa/f12/Proc/GNB/Common/GnbPcie.h deleted file mode 100644 index 4c83b53868..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/GNB/Common/GnbPcie.h +++ /dev/null @@ -1,370 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * PCIe component definitions. - * - * - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: GNB - * @e \$Revision: 38931 $ @e \$Date: 2010-10-01 15:50:05 -0700 (Fri, 01 Oct 2010) $ - * - */ -/* -***************************************************************************** -* -* Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* *************************************************************************** - -* -*/ - -#ifndef _GNBPCIE_H_ -#define _GNBPCIE_H_ - -#pragma pack (push, 1) - -#define MAX_NUMBER_OF_COMPLEXES 4 - -#define DESCRIPTOR_TERMINATE_GNB 0x40000000ull -#define DESCRIPTOR_TERMINATE_TOPOLOGY 0x20000000ull -#define DESCRIPTOR_ALLOCATED 0x10000000ull -#define DESCRIPTOR_VIRTUAL 0x08000000ull -#define DESCRIPTOR_PLATFORM 0x04000000ull -#define DESCRIPTOR_COMPLEX 0x02000000ull -#define DESCRIPTOR_SILICON 0x01000000ull -#define DESCRIPTOR_PCIE_WRAPPER 0x00800000ull -#define DESCRIPTOR_DDI_WRAPPER 0x00400000ull -#define DESCRIPTOR_PCIE_ENGINE 0x00200000ull -#define DESCRIPTOR_DDI_ENGINE 0x00100000ull - -#define DESCRIPTOR_ALL_WRAPPERS (DESCRIPTOR_DDI_WRAPPER | DESCRIPTOR_PCIE_WRAPPER) -#define DESCRIPTOR_ALL_ENGINES (DESCRIPTOR_DDI_ENGINE | DESCRIPTOR_PCIE_ENGINE) - -#define DESCRIPTOR_ALL_TYPES (DESCRIPTOR_ALL_WRAPPERS | DESCRIPTOR_ALL_ENGINES | DESCRIPTOR_SILICON | DESCRIPTOR_PLATFORM) - -#define UNUSED_LANE_ID 128 -//#define PCIE_LINK_RECEIVER_DETECTION_POOLING (60 * 1000) -//#define PCIE_LINK_L0_POOLING (60 * 1000) -//#define PCIE_LINK_GPIO_RESET_ASSERT_TIME (2 * 1000) -//#define PCIE_LINK_RESET_TO_TRAINING_TIME (2 * 1000) - -// Get lowest PHY lane on engine -#define PcieLibGetLoPhyLane(Engine) (Engine != NULL ? ((Engine->EngineData.StartLane > Engine->EngineData.EndLane) ? Engine->EngineData.EndLane : Engine->EngineData.StartLane) : 0xFF) -// Get highest PHY lane on engine -#define PcieLibGetHiPhyLane(Engine) (Engine != NULL ? ((Engine->EngineData.StartLane > Engine->EngineData.EndLane) ? Engine->EngineData.StartLane : Engine->EngineData.EndLane) : 0xFF) -// Get number of lanes on wrapper -#define PcieLibWrapperNumberOfLanes(Wrapper) (Wrapper != NULL ? ((UINT8)(Wrapper->EndPhyLane - Wrapper->StartPhyLane + 1)) : 0) -// Check if virtual descriptor -#define PcieLibIsVirtualDesciptor(Descriptor) (Descriptor != NULL ? ((Descriptor->Header.DescriptorFlags & DESCRIPTOR_VIRTUAL) != 0) : (1==0)) -// Check if it is allocated descriptor -#define PcieLibIsEngineAllocated(Descriptor) (Descriptor != NULL ? ((Descriptor->Header.DescriptorFlags & DESCRIPTOR_ALLOCATED) != 0) : (1==0)) -// Check if it is last descriptor in list -#define PcieLibIsLastDescriptor(Descriptor) (Descriptor != NULL ? ((Descriptor->Header.DescriptorFlags & DESCRIPTOR_TERMINATE_LIST) != 0) : (1==1)) -// Check if descriptor a PCIe engine -#define PcieLibIsPcieEngine(Descriptor) (Descriptor != NULL ? ((Descriptor->Header.DescriptorFlags & DESCRIPTOR_PCIE_ENGINE) != 0) : (1==0)) -// Check if descriptor a DDI engine -#define PcieLibIsDdiEngine(Descriptor) (Descriptor != NULL ? ((Descriptor->Header.DescriptorFlags & DESCRIPTOR_DDI_ENGINE) != 0) : (1==0)) -// Check if descriptor a DDI wrapper -#define PcieLibIsDdiWrapper(Descriptor) (Descriptor != NULL ? ((Descriptor->Header.DescriptorFlags & DESCRIPTOR_DDI_WRAPPER) != 0) : (1==0)) -// Check if descriptor a PCIe wrapper -#define PcieLibIsPcieWrapper(Descriptor) (Descriptor != NULL ? ((Descriptor->Header.DescriptorFlags & DESCRIPTOR_PCIE_WRAPPER) != 0) : (1==0)) -// Check if descriptor a PCIe wrapper -#define PcieLibGetNextDescriptor(Descriptor) (Descriptor != NULL ? (((Descriptor->Header.DescriptorFlags & DESCRIPTOR_TERMINATE_LIST) != 0) ? NULL : ((++Descriptor) != NULL ? Descriptor : NULL)) : NULL) - - -#define LANE_TYPE_PCIE_CORE_CONFIG 0x00000001 -#define LANE_TYPE_PCIE_CORE_ALLOC 0x00000002 -#define LANE_TYPE_PCIE_CORE_ACTIVE 0x00000004 -#define LANE_TYPE_PCIE_SB_CORE_CONFIG 0x00000008 -#define LANE_TYPE_PCIE_CORE_HOTPLUG 0x00000010 -#define LANE_TYPE_PCIE_CORE_ALLOC_ACTIVE 0x00000020 -#define LANE_TYPE_PCIE_PHY 0x00000100 -#define LANE_TYPE_PCIE_PHY_NATIVE 0x00000200 -#define LANE_TYPE_PCIE_PHY_NATIVE_ACTIVE 0x00000400 -#define LANE_TYPE_PCIE_PHY_NATIVE_HOTPLUG 0x00000800 -#define LANE_TYPE_PCIE_PHY_NATIVE_ALLOC_ACTIVE 0x00001000 -#define LANE_TYPE_DDI_PHY 0x00010000 -#define LANE_TYPE_DDI_PHY_NATIVE 0x00020000 -#define LANE_TYPE_DDI_PHY_NATIVE_ACTIVE 0x00040000 -#define LANE_TYPE_PHY_NATIVE_ALL 0x00100000 -#define LANE_TYPE_CORE_ALL LANE_TYPE_PHY_NATIVE_ALL -#define LANE_TYPE_ALL LANE_TYPE_PHY_NATIVE_ALL - -#define LANE_TYPE_PCIE_LANES (LANE_TYPE_PCIE_CORE_ACTIVE | LANE_TYPE_PCIE_SB_CORE_CONFIG | \ - LANE_TYPE_PCIE_CORE_HOTPLUG | LANE_TYPE_PCIE_CORE_ALLOC | \ - LANE_TYPE_PCIE_PHY | LANE_TYPE_PCIE_PHY_NATIVE | \ - LANE_TYPE_PCIE_PHY_NATIVE_ACTIVE | LANE_TYPE_PCIE_PHY_NATIVE_HOTPLUG | \ - LANE_TYPE_PCIE_CORE_CONFIG | LANE_TYPE_PCIE_PHY_NATIVE_ALLOC_ACTIVE | \ - LANE_TYPE_PCIE_CORE_ALLOC_ACTIVE) - -#define LANE_TYPE_DDI_LANES (LANE_TYPE_DDI_PHY | LANE_TYPE_DDI_PHY_NATIVE | LANE_TYPE_DDI_PHY_NATIVE_ACTIVE) - - -#define INIT_STATUS_PCIE_PORT_GEN2_RECOVERY 0x00000001ull -#define INIT_STATUS_PCIE_PORT_BROKEN_LANE_RECOVERY 0x00000002ull -#define INIT_STATUS_PCIE_PORT_TRAINING_FAIL 0x00000004ull -#define INIT_STATUS_PCIE_TRAINING_SUCCESS 0x00000008ull -#define INIT_STATUS_PCIE_EP_NOT_PRESENT 0x00000010ull -#define INIT_STATUS_PCIE_PORT_IN_COMPLIANCE 0x00000020ull -#define INIT_STATUS_DDI_ACTIVE 0x00000040ull -#define INIT_STATUS_ALLOCATED 0x00000080ull - -#define PCIE_PORT_GEN_CAP_BOOT 0x00000001 -#define PCIE_PORT_GEN_CAP_MAX 0x00000002 -#define PCIE_GLOBAL_GEN_CAP_ALL_PORTS 0x00000010 -#define PCIE_GLOBAL_GEN_CAP_TRAINED_PORTS 0x00000011 -#define PCIE_GLOBAL_GEN_CAP_HOTPLUG_PORTS 0x00000012 - -#define PCIE_POWERGATING_SKIP_CORE 0x00000001 -#define PCIE_POWERGATING_SKIP_PHY 0x00000002 - -/// PCIe Link Training State -typedef enum { - PcieTrainingStandard, ///< Standard training algorithm. Training contained to AmdEarlyInit. - ///< PCIe device accessible after AmdEarlyInit complete - PcieTrainingDistributed, ///< Distribute training algorithm. Training distributed across AmdEarlyInit/AmdPostInit/AmdS3LateRestore - ///< PCIe device accessible after AmdPostInit complete. - ///< Algorithm potentially save up to 60ms in S3 resume time by skipping training empty slots. -} PCIE_TRAINING_ALGORITHM; - -/// PCIe Link Training State -typedef enum { - LinkStateResetAssert, ///< Assert port GPIO reset - LinkStateResetDuration, ///< Timeout for reset duration - LinkStateResetExit, ///< Deassert port GPIO reset - LinkTrainingResetTimeout, ///< Port GPIO reset timeout - LinkStateReleaseTraining, ///< Release link training - LinkStateDetectPresence, ///< Detect device presence - LinkStateDetecting, ///< Detect link training. - LinkStateBrokenLane, ///< Check and handle broken lane - LinkStateGen2Fail, ///< Check and handle device that fail training if GEN2 capability advertised - LinkStateL0, ///< Device trained to L0 - LinkStateVcoNegotiation, ///< Check VCO negotiation complete - LinkStateRetrain, ///< Force retrain link. - LinkStateTrainingFail, ///< Link training fail - LinkStateTrainingSuccess, ///< Link training success - LinkStateGfxWorkaround, ///< GFX workaround - LinkStateCompliance, ///< Link in compliance mode - LinkStateDeviceNotPresent, ///< Link is not connected - LinkStateTrainingCompleted ///< Link training completed -} PCIE_LINK_TRAINING_STATE; - -/// PCIe Port Visibility -typedef enum { - UnhidePorts, ///< Command to unhide port - HidePorts, ///< Command to hide unused ports -} PCIE_PORT_VISIBILITY; - - -/// Table Register Entry -typedef struct { - UINT16 Reg; ///< Address - UINT32 Mask; ///< Mask - UINT32 Data; ///< Data -} PCIE_PORT_REGISTER_ENTRY; - -/// Table Register Entry -typedef struct { - PCIE_PORT_REGISTER_ENTRY *Table; ///< Table - UINT32 Length; ///< Length -} PCIE_PORT_REGISTER_TABLE_HEADER; - -/// Table Register Entry -typedef struct { - UINT32 Reg; ///< Address - UINT32 Mask; ///< Mask - UINT32 Data; ///< Data -} PCIE_HOST_REGISTER_ENTRY; - -/// Table Register Entry -typedef struct { - PCIE_HOST_REGISTER_ENTRY *Table; ///< Table - UINT32 Length; ///< Length -} PCIE_HOST_REGISTER_TABLE_HEADER; - -///Link ASPM info -typedef struct { - PCI_ADDR DownstreamPort; ///< PCI address of downstream port - PCIE_ASPM_TYPE DownstreamAspm; ///< Downstream Device Aspm - PCI_ADDR UpstreamPort; ///< PCI address of upstream port - PCIE_ASPM_TYPE UpstreamAspm; ///< Upstream Device Capability - PCIE_ASPM_TYPE RequestedAspm; ///< Requested ASPM -} PCIe_LINK_ASPM; - -///PCIe ASPM Latency Information -typedef struct { - UINT8 MaxL0sExitLatency; ///< Max L0s exit latency in us - UINT8 MaxL1ExitLatency; ///< Max L1 exit latency in us -} PCIe_ASPM_LATENCY_INFO; - -/// PCI address association -typedef struct { - UINT8 NewDeviceAddress; ///< New PCI address (Device,Fucntion) - UINT8 NativeDeviceAddress; ///< Native PCI address (Device,Fucntion) -} PCI_ADDR_LIST; - -/// The return status for GFX Card Workaround. -typedef enum { - GFX_WORKAROUND_DEVICE_NOT_READY, ///< GFX Workaround device is not ready. - GFX_WORKAROUND_RESET_DEVICE, ///< GFX Workaround device need reset. - GFX_WORKAROUND_SUCCESS ///< The service completed normally. -} GFX_WORKAROUND_STATUS; - -/// GFX workaround control -typedef enum { - GfxWorkaroundDisable, ///< GFX Workaround disabled - GfxWorkaroundEnable ///< GFX Workaround enabled -} GFX_WORKAROUND_CONTROL; - -/// PIF lane power state -typedef enum { - PifPowerStateL0, ///< - PifPowerStateLS1, ///< - PifPowerStateLS2, ///< - PifPowerStateOff = 0x7, ///< -} PCIE_PIF_POWER_STATE; - -/// PIF lane power control -typedef enum { - PowerDownPifs, ///< - PowerUpPifs ///< -} PCIE_PIF_POWER_CONTROL; - -///PLL rumup time -typedef enum { - NormalRampup, ///< - LongRampup, ///< -} PCIE_PLL_RAMPUP_TIME; - -/// PCIe port configuration info -typedef struct { - PCIe_PORT_DATA PortData; ///< Port data - UINT8 StartCoreLane; ///< Start Core Lane - UINT8 EndCoreLane; ///< End Core lane - UINT8 NativeDevNumber :5; ///< Native PCI device number of the port - UINT8 NativeFunNumber :3; ///< Native PCI function number of the port - UINT8 CoreId :4; ///< PCIe core ID - UINT8 PortId :4; ///< Port ID on wrapper - PCI_ADDR Address; ///< PCI address of the port - UINT8 State; ///< Training state - UINT32 TimeStamp; ///< Time stamp used to during training process - UINT8 GfxWrkRetryCount; ///< Number of retry for GFX workaround -} PCIe_PORT_CONFIG; - -///Descriptor header -typedef struct { - UINT32 DescriptorFlags; ///< Descriptor flags - UINT16 Parent; ///< Offset of parent descriptor - UINT16 Peer; ///< Offset of the peer descriptor - UINT16 Child; ///< Offset of the list of child descriptors -} PCIe_DESCRIPTOR_HEADER; - -/// DDI (Digital Display Interface) configuration info -typedef struct { - PCIe_DDI_DATA DdiData; ///< DDI Data - UINT8 DisplayPriorityIndex; ///< Display priority index - UINT8 ConnectorId; ///< Connector id determined by enumeration - UINT8 DisplayDeviceId; ///< Display device id determined by enumeration -} PCIe_DDI_CONFIG; - - -/// Engine configuration data -typedef struct { - PCIe_DESCRIPTOR_HEADER Header; ///< Descripto header - PCIe_ENGINE_DATA EngineData; ///< Engine Data - UINT32 InitStatus; ///< Initialization Status - UINT8 Scratch; ///< Scratch pad - union { - PCIe_PORT_CONFIG Port; ///< PCIe port configuration data - PCIe_DDI_CONFIG Ddi; ///< DDI configuration data - } Type; -} PCIe_ENGINE_CONFIG; - -/// Wrapper configuration data -typedef struct { - PCIe_DESCRIPTOR_HEADER Header; ///< Descrptor Header - UINT8 WrapId; ///< Wrapper ID - UINT8 NumberOfPIFs; ///< Number of PIFs on wrapper - UINT8 StartPhyLane; ///< Start PHY Lane - UINT8 EndPhyLane; ///< End PHY Lane - UINT8 StartPcieCoreId:4; ///< Start PCIe Core ID - UINT8 EndPcieCoreId:4; ///< End PCIe Core ID - UINT8 NumberOfLanes; ///< Number of lanes - struct { - UINT8 PowerOffUnusedLanes:1; ///< Power Off unused lanes - UINT8 PowerOffUnusedPlls:1; ///< Power Off unused Plls - UINT8 ClkGating:1; ///< TXCLK gating - UINT8 LclkGating:1; ///< LCLK gating - UINT8 TxclkGatingPllPowerDown:1; ///< TXCLK clock gating PLL power down - UINT8 PllOffInL1:1; ///< PLL off in L1 - } Features; -} PCIe_WRAPPER_CONFIG; - - -/// Silicon configuration data -typedef struct { - PCIe_DESCRIPTOR_HEADER Header; ///< Descrptor Header - UINT8 SiliconId; ///< Gnb silicon(module) ID - PCI_ADDR Address; ///< PCI address of GNB host bridge -} PCIe_SILICON_CONFIG; - -/// Complex configuration data -typedef struct { - PCIe_DESCRIPTOR_HEADER Header; ///< Descrptor Header - UINT8 SocketId; ///< Processor socket ID -} PCIe_COMPLEX_CONFIG; - -/// PCIe platform configuration info -typedef struct { - PCIe_DESCRIPTOR_HEADER Header; ///< Descrptor Header - PVOID StdHeader; ///< Standard configuration header - UINT32 LinkReceiverDetectionPooling; ///< Receiver pooling detection time in us. - UINT32 LinkL0Pooling; ///< Pooling for link to get to L0 in us - UINT32 LinkGpioResetAssertionTime; ///< Gpio reset assertion time in us - UINT32 LinkResetToTrainingTime; ///< Time duration between deassert GPIO reset and release training in us /// - UINT8 GfxCardWorkaround; ///< GFX Card Workaround - UINT8 PsppPolicy; ///< PSPP policy - UINT8 TrainingExitState; ///< State at which training should exit (see PCIE_LINK_TRAINING_STATE) - UINT8 TrainingAlgorithm; ///< Training algorithm (see PCIE_TRAINING_ALGORITHM) - PCIe_COMPLEX_CONFIG ComplexList[MAX_NUMBER_OF_COMPLEXES]; ///< Complex -} PCIe_PLATFORM_CONFIG; - -/// PCIe Engine Description -typedef struct { - UINT32 Flags; /**< Descriptor flags - * @li @b Bit31 - last descriptor on wrapper - * @li @b Bit30 - Descriptor allocated for PCIe port or DDI - */ - PCIe_ENGINE_DATA EngineData; ///< Engine Data -} PCIe_ENGINE_DESCRIPTOR; - - -#pragma pack (pop) - -#endif diff --git a/src/vendorcode/amd/agesa/f12/Proc/GNB/Common/GnbPcieFamServices.h b/src/vendorcode/amd/agesa/f12/Proc/GNB/Common/GnbPcieFamServices.h deleted file mode 100644 index fd31fa8e06..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/GNB/Common/GnbPcieFamServices.h +++ /dev/null @@ -1,231 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * PCIe family specific services. - * - * - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: GNB - * @e \$Revision: 34897 $ @e \$Date: 2010-07-13 19:07:10 -0700 (Tue, 13 Jul 2010) $ - * - */ -/* -***************************************************************************** -* -* Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* *************************************************************************** -* -*/ -#ifndef _GNBPCIEFAMSERVICES_H_ -#define _GNBPCIEFAMSERVICES_H_ - - -AGESA_STATUS -PcieFmGetComplexDataLength ( - IN UINT8 SocketId, - OUT UINTN *Length, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -typedef AGESA_STATUS F_PCIEFMGETCOMPLEXDATALENGTH ( - IN UINT8 SocketId, - OUT UINTN *Length, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -AGESA_STATUS -PcieFmBuildComplexConfiguration ( - IN UINT8 SocketId, - OUT VOID *Buffer, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -typedef AGESA_STATUS F_PCIEFMBUILDCOMPLEXCONFIGURATION ( - IN UINT8 SocketId, - OUT VOID *Buffer, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -AGESA_STATUS -PcieFmConfigureEnginesLaneAllocation ( - IN PCIe_WRAPPER_CONFIG *Wrapper, - IN PCIE_ENGINE_TYPE EngineType, - IN UINT8 ConfigurationId - ); - -typedef AGESA_STATUS F_PCIEFMCONFIGUREENGINESLANEALLOCATION ( - IN PCIe_WRAPPER_CONFIG *Wrapper, - IN PCIE_ENGINE_TYPE EngineType, - IN UINT8 ConfigurationId - ); - -AGESA_STATUS -PcieFmGetCoreConfigurationValue ( - IN PCIe_WRAPPER_CONFIG *Wrapper, - IN UINT8 CoreId, - IN UINT64 ConfigurationSignature, - IN UINT8 *ConfigurationValue - ); - -typedef AGESA_STATUS F_PCIEFMGETCORECONFIGURATIONVALUE ( - IN PCIe_WRAPPER_CONFIG *Wrapper, - IN UINT8 CoreId, - IN UINT64 ConfigurationSignature, - IN UINT8 *ConfigurationValue - ); - -BOOLEAN -PcieFmCheckPortPciDeviceMapping ( - IN PCIe_PORT_DESCRIPTOR *PortDescriptor, - IN PCIe_ENGINE_CONFIG *Engine - ); - -typedef BOOLEAN F_PCIEFMCHECKPORTPCIDEVICEMAPPING ( - IN PCIe_PORT_DESCRIPTOR *PortDescriptor, - IN PCIe_ENGINE_CONFIG *Engine - ); - -AGESA_STATUS -PcieFmMapPortPciAddress ( - IN PCIe_ENGINE_CONFIG *Engine - ); - -typedef AGESA_STATUS F_PCIEFMMAPPORTPCIADDRESS ( - IN PCIe_ENGINE_CONFIG *Engine - ); - -BOOLEAN -PcieFmCheckPortPcieLaneCanBeMuxed ( - IN PCIe_PORT_DESCRIPTOR *PortDescriptor, - IN PCIe_ENGINE_CONFIG *Engine - ); - -typedef BOOLEAN F_PCIEFMCHECKPORTPCIELANECANBEMUXED ( - IN PCIe_PORT_DESCRIPTOR *PortDescriptor, - IN PCIe_ENGINE_CONFIG *Engine - ); - -CONST CHAR8* -PcieFmDebugGetCoreConfigurationString ( - IN PCIe_WRAPPER_CONFIG *Wrapper, - IN UINT8 ConfigurationValue - ); - -typedef CONST CHAR8* F_PCIEFMDEBUGGETCORECONFIGURATIONSTRING ( - IN PCIe_WRAPPER_CONFIG *Wrapper, - IN UINT8 ConfigurationValue - ); - -CONST CHAR8* -PcieFmDebugGetWrapperNameString ( - IN PCIe_WRAPPER_CONFIG *Wrapper - ); - -typedef CONST CHAR8* F_PCIEFMDEBUGGETWRAPPERNAMESTRING ( - IN PCIe_WRAPPER_CONFIG *Wrapper - ); - -CONST CHAR8* -PcieFmDebugGetHostRegAddressSpaceString ( - IN PCIe_SILICON_CONFIG *Silicon, - IN UINT16 AddressFrame - ); - -typedef CONST CHAR8* F_PCIEFMDEBUGGETHOSTREGADDRESSSPACESTRING ( - IN PCIe_SILICON_CONFIG *Silicon, - IN UINT16 AddressFrame - ); - -PCIE_LINK_SPEED_CAP -PcieFmGetLinkSpeedCap ( - IN UINT32 Flags, - IN PCIe_ENGINE_CONFIG *Engine - ); - -typedef PCIE_LINK_SPEED_CAP F_PCIEFMGETLINKSPEEDCAP ( - IN UINT32 Flags, - IN PCIe_ENGINE_CONFIG *Engine - ); - -UINT32 -PcieFmGetNativePhyLaneBitmap ( - IN UINT32 PhyLaneBitmap, - IN PCIe_ENGINE_CONFIG *Engine - ); - -typedef UINT32 F_PCIEFMGETNATIVEPHYLANEBITMAP ( - IN UINT32 PhyLaneBitmap, - IN PCIe_ENGINE_CONFIG *Engine - ); - -AGESA_STATUS -PcieFmAlibBuildAcpiTable ( - IN VOID *AlibSsdtPtr, - IN AMD_CONFIG_PARAMS *StdHeader - ); -AGESA_STATUS -PcieFmGetSbConfigInfo ( - IN UINT8 SocketId, - OUT PCIe_PORT_DESCRIPTOR *SbPort, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -typedef AGESA_STATUS F_PCIEFMGETSBCONFIGINFO ( - IN UINT8 SocketId, - OUT PCIe_PORT_DESCRIPTOR *SbPort, - IN AMD_CONFIG_PARAMS *StdHeader - ); - - -/// PCIe config services -typedef struct { - F_PCIEFMGETCOMPLEXDATALENGTH *PcieFmGetComplexDataLength; ///< PcieFmGetComplexDataLength - F_PCIEFMBUILDCOMPLEXCONFIGURATION *PcieFmBuildComplexConfiguration; ///< PcieFmBuildComplexConfiguration - F_PCIEFMCONFIGUREENGINESLANEALLOCATION *PcieFmConfigureEnginesLaneAllocation; ///< PcieFmConfigureEnginesLaneAllocation - F_PCIEFMCHECKPORTPCIDEVICEMAPPING *PcieFmCheckPortPciDeviceMapping; ///< PcieFmCheckPortPciDeviceMapping - F_PCIEFMMAPPORTPCIADDRESS *PcieFmMapPortPciAddress; ///< PcieFmMapPortPciAddress - F_PCIEFMCHECKPORTPCIELANECANBEMUXED *PcieFmCheckPortPcieLaneCanBeMuxed; ///< PcieFmCheckPortPcieLaneCanBeMuxed - F_PCIEFMGETSBCONFIGINFO *PcieFmGetSbConfigInfo; ///< PcieFmGetSbConfigInfo -} PCIe_FAM_CONFIG_SERVICES; - -/// PCIe init services -typedef struct { - F_PCIEFMGETCORECONFIGURATIONVALUE *PcieFmGetCoreConfigurationValue; ///< PcieFmGetCoreConfigurationValue - F_PCIEFMGETLINKSPEEDCAP *PcieFmGetLinkSpeedCap; ///< PcieFmGetLinkSpeedCap - F_PCIEFMGETNATIVEPHYLANEBITMAP *PcieFmGetNativePhyLaneBitmap; ///< PcieFmGetNativePhyLaneBitmap -} PCIe_FAM_INIT_SERVICES; - -///PCIe debug services -typedef struct { - F_PCIEFMDEBUGGETHOSTREGADDRESSSPACESTRING *PcieFmDebugGetHostRegAddressSpaceString; ///< PcieFmGetCoreConfigurationValue - F_PCIEFMDEBUGGETWRAPPERNAMESTRING *PcieFmDebugGetWrapperNameString; ///< PcieFmDebugGetWrapperNameString - F_PCIEFMDEBUGGETCORECONFIGURATIONSTRING *PcieFmDebugGetCoreConfigurationString; ///< PcieFmDebugGetCoreConfigurationString -} PCIe_FAM_DEBUG_SERVICES; - -#endif diff --git a/src/vendorcode/amd/agesa/f12/Proc/GNB/Common/GnbRegistersLN.h b/src/vendorcode/amd/agesa/f12/Proc/GNB/Common/GnbRegistersLN.h deleted file mode 100644 index f59fd2eea5..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/GNB/Common/GnbRegistersLN.h +++ /dev/null @@ -1,24922 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * Register definitions - * - * - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: GNB - * @e \$Revision:$ @e \$Date:$ - * - */ -/* -***************************************************************************** -* -* Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* *************************************************************************** -* -*/ - -#ifndef _GNBREGISTERSLN_H_ -#define _GNBREGISTERSLN_H_ -#define TYPE_D0F0 0x1 -#define TYPE_D0F0x64 0x2 -#define TYPE_D0F0x98 0x3 -#define TYPE_D0F0xE4 0x5 -#define TYPE_DxF0 0x6 -#define TYPE_DxF0xE4 0x7 -#define TYPE_D18F1 0xb -#define TYPE_D18F2 0xc -#define TYPE_D18F3 0xd -#define TYPE_MSR 0x10 -#define TYPE_D1F0 0x11 -#define TYPE_GMM 0x12 -#define D18F2x9C 0xe -#define GMM 0x11 -#ifndef WRAP_SPACE - #define WRAP_SPACE(w, x) (0x01300000 | (w << 16) | (x)) -#endif -#ifndef CORE_SPACE - #define CORE_SPACE(c, x) (0x00010000 | (c << 24) | (x)) -#endif -#ifndef PHY_SPACE - #define PHY_SPACE(w, p, x) (0x00200000 | ((p + 1) << 24) | (w << 16) | (x)) -#endif -#ifndef PIF_SPACE - #define PIF_SPACE(w, p, x) (0x00100000 | ((p + 1) << 24) | (w << 16) | (x)) -#endif -// **** D0F0x00 Register Definition **** -// Address -#define D0F0x00_ADDRESS 0x0 - -// Type -#define D0F0x00_TYPE TYPE_D0F0 -// Field Data -#define D0F0x00_VendorID_OFFSET 0 -#define D0F0x00_VendorID_WIDTH 16 -#define D0F0x00_VendorID_MASK 0xffff -#define D0F0x00_DeviceID_OFFSET 16 -#define D0F0x00_DeviceID_WIDTH 16 -#define D0F0x00_DeviceID_MASK 0xffff0000 - -/// D0F0x00 -typedef union { - struct { ///< - UINT32 VendorID:16; ///< - UINT32 DeviceID:16; ///< - } Field; ///< - UINT32 Value; ///< -} D0F0x00_STRUCT; - -// **** D0F0x04 Register Definition **** -// Address -#define D0F0x04_ADDRESS 0x4 - -// Type -#define D0F0x04_TYPE TYPE_D0F0 -// Field Data -#define D0F0x04_IoAccessEn_OFFSET 0 -#define D0F0x04_IoAccessEn_WIDTH 1 -#define D0F0x04_IoAccessEn_MASK 0x1 -#define D0F0x04_MemAccessEn_OFFSET 1 -#define D0F0x04_MemAccessEn_WIDTH 1 -#define D0F0x04_MemAccessEn_MASK 0x2 -#define D0F0x04_BusMasterEn_OFFSET 2 -#define D0F0x04_BusMasterEn_WIDTH 1 -#define D0F0x04_BusMasterEn_MASK 0x4 -#define D0F0x04_SpecialCycleEn_OFFSET 3 -#define D0F0x04_SpecialCycleEn_WIDTH 1 -#define D0F0x04_SpecialCycleEn_MASK 0x8 -#define D0F0x04_MemWriteInvalidateEn_OFFSET 4 -#define D0F0x04_MemWriteInvalidateEn_WIDTH 1 -#define D0F0x04_MemWriteInvalidateEn_MASK 0x10 -#define D0F0x04_PalSnoopEn_OFFSET 5 -#define D0F0x04_PalSnoopEn_WIDTH 1 -#define D0F0x04_PalSnoopEn_MASK 0x20 -#define D0F0x04_ParityErrorEn_OFFSET 6 -#define D0F0x04_ParityErrorEn_WIDTH 1 -#define D0F0x04_ParityErrorEn_MASK 0x40 -#define D0F0x04_Reserved_7_7_OFFSET 7 -#define D0F0x04_Reserved_7_7_WIDTH 1 -#define D0F0x04_Reserved_7_7_MASK 0x80 -#define D0F0x04_SerrEn_OFFSET 8 -#define D0F0x04_SerrEn_WIDTH 1 -#define D0F0x04_SerrEn_MASK 0x100 -#define D0F0x04_FastB2BEn_OFFSET 9 -#define D0F0x04_FastB2BEn_WIDTH 1 -#define D0F0x04_FastB2BEn_MASK 0x200 -#define D0F0x04_Reserved_19_10_OFFSET 10 -#define D0F0x04_Reserved_19_10_WIDTH 10 -#define D0F0x04_Reserved_19_10_MASK 0xffc00 -#define D0F0x04_CapList_OFFSET 20 -#define D0F0x04_CapList_WIDTH 1 -#define D0F0x04_CapList_MASK 0x100000 -#define D0F0x04_PCI66En_OFFSET 21 -#define D0F0x04_PCI66En_WIDTH 1 -#define D0F0x04_PCI66En_MASK 0x200000 -#define D0F0x04_Reserved_22_22_OFFSET 22 -#define D0F0x04_Reserved_22_22_WIDTH 1 -#define D0F0x04_Reserved_22_22_MASK 0x400000 -#define D0F0x04_FastBackCapable_OFFSET 23 -#define D0F0x04_FastBackCapable_WIDTH 1 -#define D0F0x04_FastBackCapable_MASK 0x800000 -#define D0F0x04_Reserved_24_24_OFFSET 24 -#define D0F0x04_Reserved_24_24_WIDTH 1 -#define D0F0x04_Reserved_24_24_MASK 0x1000000 -#define D0F0x04_DevselTiming_OFFSET 25 -#define D0F0x04_DevselTiming_WIDTH 2 -#define D0F0x04_DevselTiming_MASK 0x6000000 -#define D0F0x04_SignalTargetAbort_OFFSET 27 -#define D0F0x04_SignalTargetAbort_WIDTH 1 -#define D0F0x04_SignalTargetAbort_MASK 0x8000000 -#define D0F0x04_ReceivedTargetAbort_OFFSET 28 -#define D0F0x04_ReceivedTargetAbort_WIDTH 1 -#define D0F0x04_ReceivedTargetAbort_MASK 0x10000000 -#define D0F0x04_ReceivedMasterAbort_OFFSET 29 -#define D0F0x04_ReceivedMasterAbort_WIDTH 1 -#define D0F0x04_ReceivedMasterAbort_MASK 0x20000000 -#define D0F0x04_SignaledSystemError_OFFSET 30 -#define D0F0x04_SignaledSystemError_WIDTH 1 -#define D0F0x04_SignaledSystemError_MASK 0x40000000 -#define D0F0x04_ParityErrorDetected_OFFSET 31 -#define D0F0x04_ParityErrorDetected_WIDTH 1 -#define D0F0x04_ParityErrorDetected_MASK 0x80000000 - -/// D0F0x04 -typedef union { - struct { ///< - UINT32 IoAccessEn:1 ; ///< - UINT32 MemAccessEn:1 ; ///< - UINT32 BusMasterEn:1 ; ///< - UINT32 SpecialCycleEn:1 ; ///< - UINT32 MemWriteInvalidateEn:1 ; ///< - UINT32 PalSnoopEn:1 ; ///< - UINT32 ParityErrorEn:1 ; ///< - UINT32 Reserved_7_7:1 ; ///< - UINT32 SerrEn:1 ; ///< - UINT32 FastB2BEn:1 ; ///< - UINT32 Reserved_19_10:10; ///< - UINT32 CapList:1 ; ///< - UINT32 PCI66En:1 ; ///< - UINT32 Reserved_22_22:1 ; ///< - UINT32 FastBackCapable:1 ; ///< - UINT32 Reserved_24_24:1 ; ///< - UINT32 DevselTiming:2 ; ///< - UINT32 SignalTargetAbort:1 ; ///< - UINT32 ReceivedTargetAbort:1 ; ///< - UINT32 ReceivedMasterAbort:1 ; ///< - UINT32 SignaledSystemError:1 ; ///< - UINT32 ParityErrorDetected:1 ; ///< - } Field; ///< - UINT32 Value; ///< -} D0F0x04_STRUCT; - -// **** D0F0x08 Register Definition **** -// Address -#define D0F0x08_ADDRESS 0x8 - -// Type -#define D0F0x08_TYPE TYPE_D0F0 -// Field Data -#define D0F0x08_RevID_OFFSET 0 -#define D0F0x08_RevID_WIDTH 8 -#define D0F0x08_RevID_MASK 0xff -#define D0F0x08_ClassCode_OFFSET 8 -#define D0F0x08_ClassCode_WIDTH 24 -#define D0F0x08_ClassCode_MASK 0xffffff00 - -/// D0F0x08 -typedef union { - struct { ///< - UINT32 RevID:8 ; ///< - UINT32 ClassCode:24; ///< - } Field; ///< - UINT32 Value; ///< -} D0F0x08_STRUCT; - -// **** D0F0x0C Register Definition **** -// Address -#define D0F0x0C_ADDRESS 0xc - -// Type -#define D0F0x0C_TYPE TYPE_D0F0 -// Field Data -#define D0F0x0C_CacheLineSize_OFFSET 0 -#define D0F0x0C_CacheLineSize_WIDTH 8 -#define D0F0x0C_CacheLineSize_MASK 0xff -#define D0F0x0C_LatencyTimer_OFFSET 8 -#define D0F0x0C_LatencyTimer_WIDTH 8 -#define D0F0x0C_LatencyTimer_MASK 0xff00 -#define D0F0x0C_HeaderTypeReg_OFFSET 16 -#define D0F0x0C_HeaderTypeReg_WIDTH 8 -#define D0F0x0C_HeaderTypeReg_MASK 0xff0000 -#define D0F0x0C_BIST_OFFSET 24 -#define D0F0x0C_BIST_WIDTH 8 -#define D0F0x0C_BIST_MASK 0xff000000 - -/// D0F0x0C -typedef union { - struct { ///< - UINT32 CacheLineSize:8 ; ///< - UINT32 LatencyTimer:8 ; ///< - UINT32 HeaderTypeReg:8 ; ///< - UINT32 BIST:8 ; ///< - } Field; ///< - UINT32 Value; ///< -} D0F0x0C_STRUCT; - -// **** D0F0x2C Register Definition **** -// Address -#define D0F0x2C_ADDRESS 0x2c - -// Type -#define D0F0x2C_TYPE TYPE_D0F0 -// Field Data -#define D0F0x2C_SubsystemVendorID_OFFSET 0 -#define D0F0x2C_SubsystemVendorID_WIDTH 16 -#define D0F0x2C_SubsystemVendorID_MASK 0xffff -#define D0F0x2C_SubsystemID_OFFSET 16 -#define D0F0x2C_SubsystemID_WIDTH 16 -#define D0F0x2C_SubsystemID_MASK 0xffff0000 - -/// D0F0x2C -typedef union { - struct { ///< - UINT32 SubsystemVendorID:16; ///< - UINT32 SubsystemID:16; ///< - } Field; ///< - UINT32 Value; ///< -} D0F0x2C_STRUCT; - -// **** D0F0x34 Register Definition **** -// Address -#define D0F0x34_ADDRESS 0x34 - -// Type -#define D0F0x34_TYPE TYPE_D0F0 -// Field Data -#define D0F0x34_CapPtr_OFFSET 0 -#define D0F0x34_CapPtr_WIDTH 8 -#define D0F0x34_CapPtr_MASK 0xff -#define D0F0x34_Reserved_31_8_OFFSET 8 -#define D0F0x34_Reserved_31_8_WIDTH 24 -#define D0F0x34_Reserved_31_8_MASK 0xffffff00 - -/// D0F0x34 -typedef union { - struct { ///< - UINT32 CapPtr:8 ; ///< - UINT32 Reserved_31_8:24; ///< - } Field; ///< - UINT32 Value; ///< -} D0F0x34_STRUCT; - -// **** D0F0x4C Register Definition **** -// Address -#define D0F0x4C_ADDRESS 0x4c - -// Type -#define D0F0x4C_TYPE TYPE_D0F0 -// Field Data -#define D0F0x4C_Function1Enable_OFFSET 0 -#define D0F0x4C_Function1Enable_WIDTH 1 -#define D0F0x4C_Function1Enable_MASK 0x1 -#define D0F0x4C_ApicEnable_OFFSET 1 -#define D0F0x4C_ApicEnable_WIDTH 1 -#define D0F0x4C_ApicEnable_MASK 0x2 -#define D0F0x4C_Reserved_2_2_OFFSET 2 -#define D0F0x4C_Reserved_2_2_WIDTH 1 -#define D0F0x4C_Reserved_2_2_MASK 0x4 -#define D0F0x4C_Cf8Dis_OFFSET 3 -#define D0F0x4C_Cf8Dis_WIDTH 1 -#define D0F0x4C_Cf8Dis_MASK 0x8 -#define D0F0x4C_PMEDis_OFFSET 4 -#define D0F0x4C_PMEDis_WIDTH 1 -#define D0F0x4C_PMEDis_MASK 0x10 -#define D0F0x4C_SerrDis_OFFSET 5 -#define D0F0x4C_SerrDis_WIDTH 1 -#define D0F0x4C_SerrDis_MASK 0x20 -#define D0F0x4C_Reserved_10_6_OFFSET 6 -#define D0F0x4C_Reserved_10_6_WIDTH 5 -#define D0F0x4C_Reserved_10_6_MASK 0x7c0 -#define D0F0x4C_CRS_OFFSET 11 -#define D0F0x4C_CRS_WIDTH 1 -#define D0F0x4C_CRS_MASK 0x800 -#define D0F0x4C_CfgRdTime_OFFSET 12 -#define D0F0x4C_CfgRdTime_WIDTH 3 -#define D0F0x4C_CfgRdTime_MASK 0x7000 -#define D0F0x4C_Reserved_22_15_OFFSET 15 -#define D0F0x4C_Reserved_22_15_WIDTH 8 -#define D0F0x4C_Reserved_22_15_MASK 0x7f8000 -#define D0F0x4C_MMIOEnable_OFFSET 23 -#define D0F0x4C_MMIOEnable_WIDTH 1 -#define D0F0x4C_MMIOEnable_MASK 0x800000 -#define D0F0x4C_Reserved_25_24_OFFSET 24 -#define D0F0x4C_Reserved_25_24_WIDTH 2 -#define D0F0x4C_Reserved_25_24_MASK 0x3000000 -#define D0F0x4C_HPDis_OFFSET 26 -#define D0F0x4C_HPDis_WIDTH 1 -#define D0F0x4C_HPDis_MASK 0x4000000 -#define D0F0x4C_Reserved_31_27_OFFSET 27 -#define D0F0x4C_Reserved_31_27_WIDTH 5 -#define D0F0x4C_Reserved_31_27_MASK 0xf8000000 - -/// D0F0x4C -typedef union { - struct { ///< - UINT32 Function1Enable:1 ; ///< - UINT32 ApicEnable:1 ; ///< - UINT32 Reserved_2_2:1 ; ///< - UINT32 Cf8Dis:1 ; ///< - UINT32 PMEDis:1 ; ///< - UINT32 SerrDis:1 ; ///< - UINT32 Reserved_10_6:5 ; ///< - UINT32 CRS:1 ; ///< - UINT32 CfgRdTime:3 ; ///< - UINT32 Reserved_22_15:8 ; ///< - UINT32 MMIOEnable:1 ; ///< - UINT32 Reserved_25_24:2 ; ///< - UINT32 HPDis:1 ; ///< - UINT32 Reserved_31_27:5 ; ///< - } Field; ///< - UINT32 Value; ///< -} D0F0x4C_STRUCT; - -// **** D0F0x60 Register Definition **** -// Address -#define D0F0x60_ADDRESS 0x60 - -// Type -#define D0F0x60_TYPE TYPE_D0F0 -// Field Data -#define D0F0x60_MiscIndAddr_OFFSET 0 -#define D0F0x60_MiscIndAddr_WIDTH 7 -#define D0F0x60_MiscIndAddr_MASK 0x7f -#define D0F0x60_MiscIndWrEn_OFFSET 7 -#define D0F0x60_MiscIndWrEn_WIDTH 1 -#define D0F0x60_MiscIndWrEn_MASK 0x80 -#define D0F0x60_Reserved_31_8_OFFSET 8 -#define D0F0x60_Reserved_31_8_WIDTH 24 -#define D0F0x60_Reserved_31_8_MASK 0xffffff00 - -/// D0F0x60 -typedef union { - struct { ///< - UINT32 MiscIndAddr:7 ; ///< - UINT32 MiscIndWrEn:1 ; ///< - UINT32 Reserved_31_8:24; ///< - } Field; ///< - UINT32 Value; ///< -} D0F0x60_STRUCT; - -// **** D0F0x64 Register Definition **** -// Address -#define D0F0x64_ADDRESS 0x64 - -// Type -#define D0F0x64_TYPE TYPE_D0F0 -// Field Data -#define D0F0x64_MiscIndData_OFFSET 0 -#define D0F0x64_MiscIndData_WIDTH 32 -#define D0F0x64_MiscIndData_MASK 0xffffffff - -/// D0F0x64 -typedef union { - struct { ///< - UINT32 MiscIndData:32; ///< - } Field; ///< - UINT32 Value; ///< -} D0F0x64_STRUCT; - -// **** D0F0x78 Register Definition **** -// Address -#define D0F0x78_ADDRESS 0x78 - -// Type -#define D0F0x78_TYPE TYPE_D0F0 -// Field Data -#define D0F0x78_Scratch_OFFSET 0 -#define D0F0x78_Scratch_WIDTH 32 -#define D0F0x78_Scratch_MASK 0xffffffff - -/// D0F0x78 -typedef union { - struct { ///< - UINT32 Scratch:32; ///< - } Field; ///< - UINT32 Value; ///< -} D0F0x78_STRUCT; - -// **** D0F0x7C Register Definition **** -// Address -#define D0F0x7C_ADDRESS 0x7c - -// Type -#define D0F0x7C_TYPE TYPE_D0F0 -// Field Data -#define D0F0x7C_ForceIntGFXDisable_OFFSET 0 -#define D0F0x7C_ForceIntGFXDisable_WIDTH 1 -#define D0F0x7C_ForceIntGFXDisable_MASK 0x1 -#define D0F0x7C_Reserved_31_1_OFFSET 1 -#define D0F0x7C_Reserved_31_1_WIDTH 31 -#define D0F0x7C_Reserved_31_1_MASK 0xfffffffe - -/// D0F0x7C -typedef union { - struct { ///< - UINT32 ForceIntGFXDisable:1 ; ///< - UINT32 Reserved_31_1:31; ///< - } Field; ///< - UINT32 Value; ///< -} D0F0x7C_STRUCT; - -// **** D0F0x84 Register Definition **** -// Address -#define D0F0x84_ADDRESS 0x84 - -// Type -#define D0F0x84_TYPE TYPE_D0F0 -// Field Data -#define D0F0x84_Reserved_3_0_OFFSET 0 -#define D0F0x84_Reserved_3_0_WIDTH 4 -#define D0F0x84_Reserved_3_0_MASK 0xf -#define D0F0x84_Ev6Mode_OFFSET 4 -#define D0F0x84_Ev6Mode_WIDTH 1 -#define D0F0x84_Ev6Mode_MASK 0x10 -#define D0F0x84_Reserved_7_5_OFFSET 5 -#define D0F0x84_Reserved_7_5_WIDTH 3 -#define D0F0x84_Reserved_7_5_MASK 0xe0 -#define D0F0x84_PmeMode_OFFSET 8 -#define D0F0x84_PmeMode_WIDTH 1 -#define D0F0x84_PmeMode_MASK 0x100 -#define D0F0x84_PmeTurnOff_OFFSET 9 -#define D0F0x84_PmeTurnOff_WIDTH 1 -#define D0F0x84_PmeTurnOff_MASK 0x200 -#define D0F0x84_Reserved_31_10_OFFSET 10 -#define D0F0x84_Reserved_31_10_WIDTH 22 -#define D0F0x84_Reserved_31_10_MASK 0xfffffc00 - -/// D0F0x84 -typedef union { - struct { ///< - UINT32 Reserved_3_0:4 ; ///< - UINT32 Ev6Mode:1 ; ///< - UINT32 Reserved_7_5:3 ; ///< - UINT32 PmeMode:1 ; ///< - UINT32 PmeTurnOff:1 ; ///< - UINT32 Reserved_31_10:22; ///< - } Field; ///< - UINT32 Value; ///< -} D0F0x84_STRUCT; - -// **** D0F0x90 Register Definition **** -// Address -#define D0F0x90_ADDRESS 0x90 - -// Type -#define D0F0x90_TYPE TYPE_D0F0 -// Field Data -#define D0F0x90_Reserved_22_0_OFFSET 0 -#define D0F0x90_Reserved_22_0_WIDTH 23 -#define D0F0x90_Reserved_22_0_MASK 0x7fffff -#define D0F0x90_TopOfDram_OFFSET 23 -#define D0F0x90_TopOfDram_WIDTH 9 -#define D0F0x90_TopOfDram_MASK 0xff800000 - -/// D0F0x90 -typedef union { - struct { ///< - UINT32 Reserved_22_0:23; ///< - UINT32 TopOfDram:9 ; ///< - } Field; ///< - UINT32 Value; ///< -} D0F0x90_STRUCT; - -// **** D0F0x94 Register Definition **** -// Address -#define D0F0x94_ADDRESS 0x94 - -// Type -#define D0F0x94_TYPE TYPE_D0F0 -// Field Data -#define D0F0x94_OrbIndAddr_OFFSET 0 -#define D0F0x94_OrbIndAddr_WIDTH 7 -#define D0F0x94_OrbIndAddr_MASK 0x7f -#define D0F0x94_Reserved_7_7_OFFSET 7 -#define D0F0x94_Reserved_7_7_WIDTH 1 -#define D0F0x94_Reserved_7_7_MASK 0x80 -#define D0F0x94_OrbIndWrEn_OFFSET 8 -#define D0F0x94_OrbIndWrEn_WIDTH 1 -#define D0F0x94_OrbIndWrEn_MASK 0x100 -#define D0F0x94_Reserved_31_9_OFFSET 9 -#define D0F0x94_Reserved_31_9_WIDTH 23 -#define D0F0x94_Reserved_31_9_MASK 0xfffffe00 - -/// D0F0x94 -typedef union { - struct { ///< - UINT32 OrbIndAddr:7 ; ///< - UINT32 Reserved_7_7:1 ; ///< - UINT32 OrbIndWrEn:1 ; ///< - UINT32 Reserved_31_9:23; ///< - } Field; ///< - UINT32 Value; ///< -} D0F0x94_STRUCT; - -// **** D0F0x98 Register Definition **** -// Address -#define D0F0x98_ADDRESS 0x98 - -// Type -#define D0F0x98_TYPE TYPE_D0F0 -// Field Data -#define D0F0x98_OrbIndData_OFFSET 0 -#define D0F0x98_OrbIndData_WIDTH 32 -#define D0F0x98_OrbIndData_MASK 0xffffffff - -/// D0F0x98 -typedef union { - struct { ///< - UINT32 OrbIndData:32; ///< - } Field; ///< - UINT32 Value; ///< -} D0F0x98_STRUCT; - -// **** D0F0xE0 Register Definition **** -// Address -#define D0F0xE0_ADDRESS 0xe0 - -// Type -#define D0F0xE0_TYPE TYPE_D0F0 -// Field Data -#define D0F0xE0_PcieIndxAddr_OFFSET 0 -#define D0F0xE0_PcieIndxAddr_WIDTH 16 -#define D0F0xE0_PcieIndxAddr_MASK 0xffff -#define D0F0xE0_FrameType_OFFSET 16 -#define D0F0xE0_FrameType_WIDTH 8 -#define D0F0xE0_FrameType_MASK 0xff0000 -#define D0F0xE0_BlockSelect_OFFSET 24 -#define D0F0xE0_BlockSelect_WIDTH 8 -#define D0F0xE0_BlockSelect_MASK 0xff000000 - -/// D0F0xE0 -typedef union { - struct { ///< - UINT32 PcieIndxAddr:16; ///< - UINT32 FrameType:8 ; ///< - UINT32 BlockSelect:8 ; ///< - } Field; ///< - UINT32 Value; ///< -} D0F0xE0_STRUCT; - -// **** D0F0xE4 Register Definition **** -// Address -#define D0F0xE4_ADDRESS 0xe4 - -// Type -#define D0F0xE4_TYPE TYPE_D0F0 -// Field Data -#define D0F0xE4_PcieIndxData_OFFSET 0 -#define D0F0xE4_PcieIndxData_WIDTH 32 -#define D0F0xE4_PcieIndxData_MASK 0xffffffff - -/// D0F0xE4 -typedef union { - struct { ///< - UINT32 PcieIndxData:32; ///< - } Field; ///< - UINT32 Value; ///< -} D0F0xE4_STRUCT; - -// **** D18F1xF0 Register Definition **** -// Address -#define D18F1xF0_ADDRESS 0xf0 - -// Type -#define D18F1xF0_TYPE TYPE_D18F1 -// Field Data -#define D18F1xF0_DramHoleValid_OFFSET 0 -#define D18F1xF0_DramHoleValid_WIDTH 1 -#define D18F1xF0_DramHoleValid_MASK 0x1 -#define D18F1xF0_Reserved_6_1_OFFSET 1 -#define D18F1xF0_Reserved_6_1_WIDTH 6 -#define D18F1xF0_Reserved_6_1_MASK 0x7e -#define D18F1xF0_DramHoleOffset_31_23__OFFSET 7 -#define D18F1xF0_DramHoleOffset_31_23__WIDTH 9 -#define D18F1xF0_DramHoleOffset_31_23__MASK 0xff80 -#define D18F1xF0_Reserved_23_16_OFFSET 16 -#define D18F1xF0_Reserved_23_16_WIDTH 8 -#define D18F1xF0_Reserved_23_16_MASK 0xff0000 -#define D18F1xF0_DramHoleBase_31_24__OFFSET 24 -#define D18F1xF0_DramHoleBase_31_24__WIDTH 8 -#define D18F1xF0_DramHoleBase_31_24__MASK 0xff000000 - -/// D18F1xF0 -typedef union { - struct { ///< - UINT32 DramHoleValid:1 ; ///< - UINT32 Reserved_6_1:6 ; ///< - UINT32 DramHoleOffset_31_23_:9 ; ///< - UINT32 Reserved_23_16:8 ; ///< - UINT32 DramHoleBase_31_24_:8 ; ///< - } Field; ///< - UINT32 Value; ///< -} D18F1xF0_STRUCT; - -// **** D18F2x00 Register Definition **** -// Address -#define D18F2x00_ADDRESS 0x0 - -// Type -#define D18F2x00_TYPE TYPE_D18F2 -// Field Data -#define D18F2x00_VendorID_OFFSET 0 -#define D18F2x00_VendorID_WIDTH 16 -#define D18F2x00_VendorID_MASK 0xffff -#define D18F2x00_DeviceID_OFFSET 16 -#define D18F2x00_DeviceID_WIDTH 16 -#define D18F2x00_DeviceID_MASK 0xffff0000 - -/// D18F2x00 -typedef union { - struct { ///< - UINT32 VendorID:16; ///< - UINT32 DeviceID:16; ///< - } Field; ///< - UINT32 Value; ///< -} D18F2x00_STRUCT; - -// **** D18F2x04 Register Definition **** -// Address -#define D18F2x04_ADDRESS 0x4 - -// Type -#define D18F2x04_TYPE TYPE_D18F2 -// Field Data -#define D18F2x04_Command_OFFSET 0 -#define D18F2x04_Command_WIDTH 16 -#define D18F2x04_Command_MASK 0xffff -#define D18F2x04_Status_OFFSET 16 -#define D18F2x04_Status_WIDTH 16 -#define D18F2x04_Status_MASK 0xffff0000 - -/// D18F2x04 -typedef union { - struct { ///< - UINT32 Command:16; ///< - UINT32 Status:16; ///< - } Field; ///< - UINT32 Value; ///< -} D18F2x04_STRUCT; - -// **** D18F2x08 Register Definition **** -// Address -#define D18F2x08_ADDRESS 0x8 - -// Type -#define D18F2x08_TYPE TYPE_D18F2 -// Field Data -#define D18F2x08_RevID_OFFSET 0 -#define D18F2x08_RevID_WIDTH 8 -#define D18F2x08_RevID_MASK 0xff -#define D18F2x08_ClassCode_OFFSET 8 -#define D18F2x08_ClassCode_WIDTH 24 -#define D18F2x08_ClassCode_MASK 0xffffff00 - -/// D18F2x08 -typedef union { - struct { ///< - UINT32 RevID:8 ; ///< - UINT32 ClassCode:24; ///< - } Field; ///< - UINT32 Value; ///< -} D18F2x08_STRUCT; - -// **** D18F2x0C Register Definition **** -// Address -#define D18F2x0C_ADDRESS 0xc - -// Type -#define D18F2x0C_TYPE TYPE_D18F2 -// Field Data -#define D18F2x0C_HeaderTypeReg_OFFSET 0 -#define D18F2x0C_HeaderTypeReg_WIDTH 32 -#define D18F2x0C_HeaderTypeReg_MASK 0xffffffff - -/// D18F2x0C -typedef union { - struct { ///< - UINT32 HeaderTypeReg:32; ///< - } Field; ///< - UINT32 Value; ///< -} D18F2x0C_STRUCT; - -// **** D18F2x34 Register Definition **** -// Address -#define D18F2x34_ADDRESS 0x34 - -// Type -#define D18F2x34_TYPE TYPE_D18F2 -// Field Data -#define D18F2x34_CapPtr_OFFSET 0 -#define D18F2x34_CapPtr_WIDTH 8 -#define D18F2x34_CapPtr_MASK 0xff -#define D18F2x34_Reserved_31_8_OFFSET 8 -#define D18F2x34_Reserved_31_8_WIDTH 24 -#define D18F2x34_Reserved_31_8_MASK 0xffffff00 - -/// D18F2x34 -typedef union { - struct { ///< - UINT32 CapPtr:8 ; ///< - UINT32 Reserved_31_8:24; ///< - } Field; ///< - UINT32 Value; ///< -} D18F2x34_STRUCT; - -// **** D18F2x040 Register Definition **** -// Address -#define D18F2x040_ADDRESS 0x40 - -// Type -#define D18F2x040_TYPE TYPE_D18F2 -// Field Data -#define D18F2x040_CSEnable_OFFSET 0 -#define D18F2x040_CSEnable_WIDTH 1 -#define D18F2x040_CSEnable_MASK 0x1 -#define D18F2x040_Reserved_1_1_OFFSET 1 -#define D18F2x040_Reserved_1_1_WIDTH 1 -#define D18F2x040_Reserved_1_1_MASK 0x2 -#define D18F2x040_TestFail_OFFSET 2 -#define D18F2x040_TestFail_WIDTH 1 -#define D18F2x040_TestFail_MASK 0x4 -#define D18F2x040_OnDimmMirror_OFFSET 3 -#define D18F2x040_OnDimmMirror_WIDTH 1 -#define D18F2x040_OnDimmMirror_MASK 0x8 -#define D18F2x040_Reserved_4_4_OFFSET 4 -#define D18F2x040_Reserved_4_4_WIDTH 1 -#define D18F2x040_Reserved_4_4_MASK 0x10 -#define D18F2x040_BaseAddr_21_13__OFFSET 5 -#define D18F2x040_BaseAddr_21_13__WIDTH 9 -#define D18F2x040_BaseAddr_21_13__MASK 0x3fe0 -#define D18F2x040_Reserved_18_14_OFFSET 14 -#define D18F2x040_Reserved_18_14_WIDTH 5 -#define D18F2x040_Reserved_18_14_MASK 0x7c000 -#define D18F2x040_BaseAddr_36_27__OFFSET 19 -#define D18F2x040_BaseAddr_36_27__WIDTH 10 -#define D18F2x040_BaseAddr_36_27__MASK 0x1ff80000 -#define D18F2x040_Reserved_31_29_OFFSET 29 -#define D18F2x040_Reserved_31_29_WIDTH 3 -#define D18F2x040_Reserved_31_29_MASK 0xe0000000 - -/// D18F2x040 -typedef union { - struct { ///< - UINT32 CSEnable:1 ; ///< - UINT32 Reserved_1_1:1 ; ///< - UINT32 TestFail:1 ; ///< - UINT32 OnDimmMirror:1 ; ///< - UINT32 Reserved_4_4:1 ; ///< - UINT32 BaseAddr_21_13_:9 ; ///< - UINT32 Reserved_18_14:5 ; ///< - UINT32 BaseAddr_36_27_:10; ///< - UINT32 Reserved_31_29:3 ; ///< - } Field; ///< - UINT32 Value; ///< -} D18F2x040_STRUCT; - -// **** D18F2x044 Register Definition **** -// Address -#define D18F2x044_ADDRESS 0x44 - -// Type -#define D18F2x044_TYPE TYPE_D18F2 -// Field Data -#define D18F2x044_CSEnable_OFFSET 0 -#define D18F2x044_CSEnable_WIDTH 1 -#define D18F2x044_CSEnable_MASK 0x1 -#define D18F2x044_Reserved_1_1_OFFSET 1 -#define D18F2x044_Reserved_1_1_WIDTH 1 -#define D18F2x044_Reserved_1_1_MASK 0x2 -#define D18F2x044_TestFail_OFFSET 2 -#define D18F2x044_TestFail_WIDTH 1 -#define D18F2x044_TestFail_MASK 0x4 -#define D18F2x044_OnDimmMirror_OFFSET 3 -#define D18F2x044_OnDimmMirror_WIDTH 1 -#define D18F2x044_OnDimmMirror_MASK 0x8 -#define D18F2x044_Reserved_4_4_OFFSET 4 -#define D18F2x044_Reserved_4_4_WIDTH 1 -#define D18F2x044_Reserved_4_4_MASK 0x10 -#define D18F2x044_BaseAddr_21_13__OFFSET 5 -#define D18F2x044_BaseAddr_21_13__WIDTH 9 -#define D18F2x044_BaseAddr_21_13__MASK 0x3fe0 -#define D18F2x044_Reserved_18_14_OFFSET 14 -#define D18F2x044_Reserved_18_14_WIDTH 5 -#define D18F2x044_Reserved_18_14_MASK 0x7c000 -#define D18F2x044_BaseAddr_36_27__OFFSET 19 -#define D18F2x044_BaseAddr_36_27__WIDTH 10 -#define D18F2x044_BaseAddr_36_27__MASK 0x1ff80000 -#define D18F2x044_Reserved_31_29_OFFSET 29 -#define D18F2x044_Reserved_31_29_WIDTH 3 -#define D18F2x044_Reserved_31_29_MASK 0xe0000000 - -/// D18F2x044 -typedef union { - struct { ///< - UINT32 CSEnable:1 ; ///< - UINT32 Reserved_1_1:1 ; ///< - UINT32 TestFail:1 ; ///< - UINT32 OnDimmMirror:1 ; ///< - UINT32 Reserved_4_4:1 ; ///< - UINT32 BaseAddr_21_13_:9 ; ///< - UINT32 Reserved_18_14:5 ; ///< - UINT32 BaseAddr_36_27_:10; ///< - UINT32 Reserved_31_29:3 ; ///< - } Field; ///< - UINT32 Value; ///< -} D18F2x044_STRUCT; - -// **** D18F2x048 Register Definition **** -// Address -#define D18F2x048_ADDRESS 0x48 - -// Type -#define D18F2x048_TYPE TYPE_D18F2 -// Field Data -#define D18F2x048_CSEnable_OFFSET 0 -#define D18F2x048_CSEnable_WIDTH 1 -#define D18F2x048_CSEnable_MASK 0x1 -#define D18F2x048_Reserved_1_1_OFFSET 1 -#define D18F2x048_Reserved_1_1_WIDTH 1 -#define D18F2x048_Reserved_1_1_MASK 0x2 -#define D18F2x048_TestFail_OFFSET 2 -#define D18F2x048_TestFail_WIDTH 1 -#define D18F2x048_TestFail_MASK 0x4 -#define D18F2x048_OnDimmMirror_OFFSET 3 -#define D18F2x048_OnDimmMirror_WIDTH 1 -#define D18F2x048_OnDimmMirror_MASK 0x8 -#define D18F2x048_Reserved_4_4_OFFSET 4 -#define D18F2x048_Reserved_4_4_WIDTH 1 -#define D18F2x048_Reserved_4_4_MASK 0x10 -#define D18F2x048_BaseAddr_21_13__OFFSET 5 -#define D18F2x048_BaseAddr_21_13__WIDTH 9 -#define D18F2x048_BaseAddr_21_13__MASK 0x3fe0 -#define D18F2x048_Reserved_18_14_OFFSET 14 -#define D18F2x048_Reserved_18_14_WIDTH 5 -#define D18F2x048_Reserved_18_14_MASK 0x7c000 -#define D18F2x048_BaseAddr_36_27__OFFSET 19 -#define D18F2x048_BaseAddr_36_27__WIDTH 10 -#define D18F2x048_BaseAddr_36_27__MASK 0x1ff80000 -#define D18F2x048_Reserved_31_29_OFFSET 29 -#define D18F2x048_Reserved_31_29_WIDTH 3 -#define D18F2x048_Reserved_31_29_MASK 0xe0000000 - -/// D18F2x048 -typedef union { - struct { ///< - UINT32 CSEnable:1 ; ///< - UINT32 Reserved_1_1:1 ; ///< - UINT32 TestFail:1 ; ///< - UINT32 OnDimmMirror:1 ; ///< - UINT32 Reserved_4_4:1 ; ///< - UINT32 BaseAddr_21_13_:9 ; ///< - UINT32 Reserved_18_14:5 ; ///< - UINT32 BaseAddr_36_27_:10; ///< - UINT32 Reserved_31_29:3 ; ///< - } Field; ///< - UINT32 Value; ///< -} D18F2x048_STRUCT; - -// **** D18F2x04C Register Definition **** -// Address -#define D18F2x04C_ADDRESS 0x4c - -// Type -#define D18F2x04C_TYPE TYPE_D18F2 -// Field Data -#define D18F2x04C_CSEnable_OFFSET 0 -#define D18F2x04C_CSEnable_WIDTH 1 -#define D18F2x04C_CSEnable_MASK 0x1 -#define D18F2x04C_Reserved_1_1_OFFSET 1 -#define D18F2x04C_Reserved_1_1_WIDTH 1 -#define D18F2x04C_Reserved_1_1_MASK 0x2 -#define D18F2x04C_TestFail_OFFSET 2 -#define D18F2x04C_TestFail_WIDTH 1 -#define D18F2x04C_TestFail_MASK 0x4 -#define D18F2x04C_OnDimmMirror_OFFSET 3 -#define D18F2x04C_OnDimmMirror_WIDTH 1 -#define D18F2x04C_OnDimmMirror_MASK 0x8 -#define D18F2x04C_Reserved_4_4_OFFSET 4 -#define D18F2x04C_Reserved_4_4_WIDTH 1 -#define D18F2x04C_Reserved_4_4_MASK 0x10 -#define D18F2x04C_BaseAddr_21_13__OFFSET 5 -#define D18F2x04C_BaseAddr_21_13__WIDTH 9 -#define D18F2x04C_BaseAddr_21_13__MASK 0x3fe0 -#define D18F2x04C_Reserved_18_14_OFFSET 14 -#define D18F2x04C_Reserved_18_14_WIDTH 5 -#define D18F2x04C_Reserved_18_14_MASK 0x7c000 -#define D18F2x04C_BaseAddr_36_27__OFFSET 19 -#define D18F2x04C_BaseAddr_36_27__WIDTH 10 -#define D18F2x04C_BaseAddr_36_27__MASK 0x1ff80000 -#define D18F2x04C_Reserved_31_29_OFFSET 29 -#define D18F2x04C_Reserved_31_29_WIDTH 3 -#define D18F2x04C_Reserved_31_29_MASK 0xe0000000 - -/// D18F2x04C -typedef union { - struct { ///< - UINT32 CSEnable:1 ; ///< - UINT32 Reserved_1_1:1 ; ///< - UINT32 TestFail:1 ; ///< - UINT32 OnDimmMirror:1 ; ///< - UINT32 Reserved_4_4:1 ; ///< - UINT32 BaseAddr_21_13_:9 ; ///< - UINT32 Reserved_18_14:5 ; ///< - UINT32 BaseAddr_36_27_:10; ///< - UINT32 Reserved_31_29:3 ; ///< - } Field; ///< - UINT32 Value; ///< -} D18F2x04C_STRUCT; - -// **** D18F2x060 Register Definition **** -// Address -#define D18F2x060_ADDRESS 0x60 - -// Type -#define D18F2x060_TYPE TYPE_D18F2 -// Field Data -#define D18F2x060_Reserved_4_0_OFFSET 0 -#define D18F2x060_Reserved_4_0_WIDTH 5 -#define D18F2x060_Reserved_4_0_MASK 0x1f -#define D18F2x060_AddrMask_21_13__OFFSET 5 -#define D18F2x060_AddrMask_21_13__WIDTH 9 -#define D18F2x060_AddrMask_21_13__MASK 0x3fe0 -#define D18F2x060_Reserved_18_14_OFFSET 14 -#define D18F2x060_Reserved_18_14_WIDTH 5 -#define D18F2x060_Reserved_18_14_MASK 0x7c000 -#define D18F2x060_AddrMask_36_27__OFFSET 19 -#define D18F2x060_AddrMask_36_27__WIDTH 10 -#define D18F2x060_AddrMask_36_27__MASK 0x1ff80000 -#define D18F2x060_Reserved_31_29_OFFSET 29 -#define D18F2x060_Reserved_31_29_WIDTH 3 -#define D18F2x060_Reserved_31_29_MASK 0xe0000000 - -/// D18F2x060 -typedef union { - struct { ///< - UINT32 Reserved_4_0:5 ; ///< - UINT32 AddrMask_21_13_:9 ; ///< - UINT32 Reserved_18_14:5 ; ///< - UINT32 AddrMask_36_27_:10; ///< - UINT32 Reserved_31_29:3 ; ///< - } Field; ///< - UINT32 Value; ///< -} D18F2x060_STRUCT; - -// **** D18F2x064 Register Definition **** -// Address -#define D18F2x064_ADDRESS 0x64 - -// Type -#define D18F2x064_TYPE TYPE_D18F2 -// Field Data -#define D18F2x064_Reserved_4_0_OFFSET 0 -#define D18F2x064_Reserved_4_0_WIDTH 5 -#define D18F2x064_Reserved_4_0_MASK 0x1f -#define D18F2x064_AddrMask_21_13__OFFSET 5 -#define D18F2x064_AddrMask_21_13__WIDTH 9 -#define D18F2x064_AddrMask_21_13__MASK 0x3fe0 -#define D18F2x064_Reserved_18_14_OFFSET 14 -#define D18F2x064_Reserved_18_14_WIDTH 5 -#define D18F2x064_Reserved_18_14_MASK 0x7c000 -#define D18F2x064_AddrMask_36_27__OFFSET 19 -#define D18F2x064_AddrMask_36_27__WIDTH 10 -#define D18F2x064_AddrMask_36_27__MASK 0x1ff80000 -#define D18F2x064_Reserved_31_29_OFFSET 29 -#define D18F2x064_Reserved_31_29_WIDTH 3 -#define D18F2x064_Reserved_31_29_MASK 0xe0000000 - -/// D18F2x064 -typedef union { - struct { ///< - UINT32 Reserved_4_0:5 ; ///< - UINT32 AddrMask_21_13_:9 ; ///< - UINT32 Reserved_18_14:5 ; ///< - UINT32 AddrMask_36_27_:10; ///< - UINT32 Reserved_31_29:3 ; ///< - } Field; ///< - UINT32 Value; ///< -} D18F2x064_STRUCT; - -// **** D18F2x078 Register Definition **** -// Address -#define D18F2x078_ADDRESS 0x78 - -// Type -#define D18F2x078_TYPE TYPE_D18F2 -// Field Data -#define D18F2x078_RdPtrInit_OFFSET 0 -#define D18F2x078_RdPtrInit_WIDTH 4 -#define D18F2x078_RdPtrInit_MASK 0xf -#define D18F2x078_Reserved_5_4_OFFSET 4 -#define D18F2x078_Reserved_5_4_WIDTH 2 -#define D18F2x078_Reserved_5_4_MASK 0x30 -#define D18F2x078_RxPtrInitReq_OFFSET 6 -#define D18F2x078_RxPtrInitReq_WIDTH 1 -#define D18F2x078_RxPtrInitReq_MASK 0x40 -#define D18F2x078_Reserved_7_7_OFFSET 7 -#define D18F2x078_Reserved_7_7_WIDTH 1 -#define D18F2x078_Reserved_7_7_MASK 0x80 -#define D18F2x078_Twrrd_3_2__OFFSET 8 -#define D18F2x078_Twrrd_3_2__WIDTH 2 -#define D18F2x078_Twrrd_3_2__MASK 0x300 -#define D18F2x078_Twrwr_3_2__OFFSET 10 -#define D18F2x078_Twrwr_3_2__WIDTH 2 -#define D18F2x078_Twrwr_3_2__MASK 0xc00 -#define D18F2x078_Trdrd_3_2__OFFSET 12 -#define D18F2x078_Trdrd_3_2__WIDTH 2 -#define D18F2x078_Trdrd_3_2__MASK 0x3000 -#define D18F2x078_Reserved_14_14_OFFSET 14 -#define D18F2x078_Reserved_14_14_WIDTH 1 -#define D18F2x078_Reserved_14_14_MASK 0x4000 -#define D18F2x078_Reserved_15_15_OFFSET 15 -#define D18F2x078_Reserved_15_15_WIDTH 1 -#define D18F2x078_Reserved_15_15_MASK 0x8000 -#define D18F2x078_Reserved_16_16_OFFSET 16 -#define D18F2x078_Reserved_16_16_WIDTH 1 -#define D18F2x078_Reserved_16_16_MASK 0x10000 -#define D18F2x078_AddrCmdTriEn_OFFSET 17 -#define D18F2x078_AddrCmdTriEn_WIDTH 1 -#define D18F2x078_AddrCmdTriEn_MASK 0x20000 -#define D18F2x078_Reserved_18_18_OFFSET 18 -#define D18F2x078_Reserved_18_18_WIDTH 1 -#define D18F2x078_Reserved_18_18_MASK 0x40000 -#define D18F2x078_Reserved_19_19_OFFSET 19 -#define D18F2x078_Reserved_19_19_WIDTH 1 -#define D18F2x078_Reserved_19_19_MASK 0x80000 -#define D18F2x078_ForceCasToSlot_OFFSET 20 -#define D18F2x078_ForceCasToSlot_WIDTH 1 -#define D18F2x078_ForceCasToSlot_MASK 0x100000 -#define D18F2x078_DisCutThroughMode_OFFSET 21 -#define D18F2x078_DisCutThroughMode_WIDTH 1 -#define D18F2x078_DisCutThroughMode_MASK 0x200000 -#define D18F2x078_MaxRdLatency_OFFSET 22 -#define D18F2x078_MaxRdLatency_WIDTH 10 -#define D18F2x078_MaxRdLatency_MASK 0xffc00000 - -/// D18F2x078 -typedef union { - struct { ///< - UINT32 RdPtrInit:4 ; ///< - UINT32 Reserved_5_4:2 ; ///< - UINT32 RxPtrInitReq:1 ; ///< - UINT32 Reserved_7_7:1 ; ///< - UINT32 Twrrd_3_2_:2 ; ///< - UINT32 Twrwr_3_2_:2 ; ///< - UINT32 Trdrd_3_2_:2 ; ///< - UINT32 Reserved_14_14:1 ; ///< - UINT32 Reserved_15_15:1 ; ///< - UINT32 Reserved_16_16:1 ; ///< - UINT32 AddrCmdTriEn:1 ; ///< - UINT32 Reserved_18_18:1 ; ///< - UINT32 Reserved_19_19:1 ; ///< - UINT32 ForceCasToSlot:1 ; ///< - UINT32 DisCutThroughMode:1 ; ///< - UINT32 MaxRdLatency:10; ///< - } Field; ///< - UINT32 Value; ///< -} D18F2x078_STRUCT; - -// **** D18F2x07C Register Definition **** -// Address -#define D18F2x07C_ADDRESS 0x7c - -// Type -#define D18F2x07C_TYPE TYPE_D18F2 -// Field Data -#define D18F2x07C_MrsAddress_OFFSET 0 -#define D18F2x07C_MrsAddress_WIDTH 16 -#define D18F2x07C_MrsAddress_MASK 0xffff -#define D18F2x07C_MrsBank_OFFSET 16 -#define D18F2x07C_MrsBank_WIDTH 3 -#define D18F2x07C_MrsBank_MASK 0x70000 -#define D18F2x07C_Reserved_19_19_OFFSET 19 -#define D18F2x07C_Reserved_19_19_WIDTH 1 -#define D18F2x07C_Reserved_19_19_MASK 0x80000 -#define D18F2x07C_MrsChipSel_OFFSET 20 -#define D18F2x07C_MrsChipSel_WIDTH 3 -#define D18F2x07C_MrsChipSel_MASK 0x700000 -#define D18F2x07C_Reserved_23_23_OFFSET 23 -#define D18F2x07C_Reserved_23_23_WIDTH 1 -#define D18F2x07C_Reserved_23_23_MASK 0x800000 -#define D18F2x07C_SendPchgAll_OFFSET 24 -#define D18F2x07C_SendPchgAll_WIDTH 1 -#define D18F2x07C_SendPchgAll_MASK 0x1000000 -#define D18F2x07C_SendAutoRefresh_OFFSET 25 -#define D18F2x07C_SendAutoRefresh_WIDTH 1 -#define D18F2x07C_SendAutoRefresh_MASK 0x2000000 -#define D18F2x07C_SendMrsCmd_OFFSET 26 -#define D18F2x07C_SendMrsCmd_WIDTH 1 -#define D18F2x07C_SendMrsCmd_MASK 0x4000000 -#define D18F2x07C_DeassertMemRstX_OFFSET 27 -#define D18F2x07C_DeassertMemRstX_WIDTH 1 -#define D18F2x07C_DeassertMemRstX_MASK 0x8000000 -#define D18F2x07C_AssertCke_OFFSET 28 -#define D18F2x07C_AssertCke_WIDTH 1 -#define D18F2x07C_AssertCke_MASK 0x10000000 -#define D18F2x07C_SendZQCmd_OFFSET 29 -#define D18F2x07C_SendZQCmd_WIDTH 1 -#define D18F2x07C_SendZQCmd_MASK 0x20000000 -#define D18F2x07C_Reserved_30_30_OFFSET 30 -#define D18F2x07C_Reserved_30_30_WIDTH 1 -#define D18F2x07C_Reserved_30_30_MASK 0x40000000 -#define D18F2x07C_EnDramInit_OFFSET 31 -#define D18F2x07C_EnDramInit_WIDTH 1 -#define D18F2x07C_EnDramInit_MASK 0x80000000 - -/// D18F2x07C -typedef union { - struct { ///< - UINT32 MrsAddress:16; ///< - UINT32 MrsBank:3 ; ///< - UINT32 Reserved_19_19:1 ; ///< - UINT32 MrsChipSel:3 ; ///< - UINT32 Reserved_23_23:1 ; ///< - UINT32 SendPchgAll:1 ; ///< - UINT32 SendAutoRefresh:1 ; ///< - UINT32 SendMrsCmd:1 ; ///< - UINT32 DeassertMemRstX:1 ; ///< - UINT32 AssertCke:1 ; ///< - UINT32 SendZQCmd:1 ; ///< - UINT32 Reserved_30_30:1 ; ///< - UINT32 EnDramInit:1 ; ///< - } Field; ///< - UINT32 Value; ///< -} D18F2x07C_STRUCT; - -// **** D18F2x080 Register Definition **** -// Address -#define D18F2x080_ADDRESS 0x80 - -// Type -#define D18F2x080_TYPE TYPE_D18F2 -// Field Data -#define D18F2x080_Dimm0AddrMap_OFFSET 0 -#define D18F2x080_Dimm0AddrMap_WIDTH 4 -#define D18F2x080_Dimm0AddrMap_MASK 0xf -#define D18F2x080_Dimm1AddrMap_OFFSET 4 -#define D18F2x080_Dimm1AddrMap_WIDTH 4 -#define D18F2x080_Dimm1AddrMap_MASK 0xf0 -#define D18F2x080_Reserved_31_8_OFFSET 8 -#define D18F2x080_Reserved_31_8_WIDTH 24 -#define D18F2x080_Reserved_31_8_MASK 0xffffff00 - -/// D18F2x080 -typedef union { - struct { ///< - UINT32 Dimm0AddrMap:4 ; ///< - UINT32 Dimm1AddrMap:4 ; ///< - UINT32 Reserved_31_8:24; ///< - } Field; ///< - UINT32 Value; ///< -} D18F2x080_STRUCT; - -// **** D18F2x084 Register Definition **** -// Address -#define D18F2x084_ADDRESS 0x84 - -// Type -#define D18F2x084_TYPE TYPE_D18F2 -// Field Data -#define D18F2x084_BurstCtrl_OFFSET 0 -#define D18F2x084_BurstCtrl_WIDTH 2 -#define D18F2x084_BurstCtrl_MASK 0x3 -#define D18F2x084_Reserved_3_2_OFFSET 2 -#define D18F2x084_Reserved_3_2_WIDTH 2 -#define D18F2x084_Reserved_3_2_MASK 0xc -#define D18F2x084_Twr_OFFSET 4 -#define D18F2x084_Twr_WIDTH 3 -#define D18F2x084_Twr_MASK 0x70 -#define D18F2x084_Reserved_19_7_OFFSET 7 -#define D18F2x084_Reserved_19_7_WIDTH 13 -#define D18F2x084_Reserved_19_7_MASK 0xfff80 -#define D18F2x084_Tcwl_OFFSET 20 -#define D18F2x084_Tcwl_WIDTH 3 -#define D18F2x084_Tcwl_MASK 0x700000 -#define D18F2x084_PchgPDModeSel_OFFSET 23 -#define D18F2x084_PchgPDModeSel_WIDTH 1 -#define D18F2x084_PchgPDModeSel_MASK 0x800000 -#define D18F2x084_Reserved_31_24_OFFSET 24 -#define D18F2x084_Reserved_31_24_WIDTH 8 -#define D18F2x084_Reserved_31_24_MASK 0xff000000 - -/// D18F2x084 -typedef union { - struct { ///< - UINT32 BurstCtrl:2 ; ///< - UINT32 Reserved_3_2:2 ; ///< - UINT32 Twr:3 ; ///< - UINT32 Reserved_19_7:13; ///< - UINT32 Tcwl:3 ; ///< - UINT32 PchgPDModeSel:1 ; ///< - UINT32 Reserved_31_24:8 ; ///< - } Field; ///< - UINT32 Value; ///< -} D18F2x084_STRUCT; - -// **** D18F2x088 Register Definition **** -// Address -#define D18F2x088_ADDRESS 0x88 - -// Type -#define D18F2x088_TYPE TYPE_D18F2 -// Field Data -#define D18F2x088_Tcl_OFFSET 0 -#define D18F2x088_Tcl_WIDTH 4 -#define D18F2x088_Tcl_MASK 0xf -#define D18F2x088_Reserved_23_4_OFFSET 4 -#define D18F2x088_Reserved_23_4_WIDTH 20 -#define D18F2x088_Reserved_23_4_MASK 0xfffff0 -#define D18F2x088_MemClkDis_OFFSET 24 -#define D18F2x088_MemClkDis_WIDTH 8 -#define D18F2x088_MemClkDis_MASK 0xff000000 - -/// D18F2x088 -typedef union { - struct { ///< - UINT32 Tcl:4 ; ///< - UINT32 Reserved_23_4:20; ///< - UINT32 MemClkDis:8 ; ///< - } Field; ///< - UINT32 Value; ///< -} D18F2x088_STRUCT; - -// **** D18F2x08C Register Definition **** -// Address -#define D18F2x08C_ADDRESS 0x8c - -// Type -#define D18F2x08C_TYPE TYPE_D18F2 -// Field Data -#define D18F2x08C_TrwtWB_OFFSET 0 -#define D18F2x08C_TrwtWB_WIDTH 4 -#define D18F2x08C_TrwtWB_MASK 0xf -#define D18F2x08C_TrwtTO_OFFSET 4 -#define D18F2x08C_TrwtTO_WIDTH 4 -#define D18F2x08C_TrwtTO_MASK 0xf0 -#define D18F2x08C_Reserved_9_8_OFFSET 8 -#define D18F2x08C_Reserved_9_8_WIDTH 2 -#define D18F2x08C_Reserved_9_8_MASK 0x300 -#define D18F2x08C_Twrrd_1_0__OFFSET 10 -#define D18F2x08C_Twrrd_1_0__WIDTH 2 -#define D18F2x08C_Twrrd_1_0__MASK 0xc00 -#define D18F2x08C_Twrwr_1_0__OFFSET 12 -#define D18F2x08C_Twrwr_1_0__WIDTH 2 -#define D18F2x08C_Twrwr_1_0__MASK 0x3000 -#define D18F2x08C_Trdrd_1_0__OFFSET 14 -#define D18F2x08C_Trdrd_1_0__WIDTH 2 -#define D18F2x08C_Trdrd_1_0__MASK 0xc000 -#define D18F2x08C_Tref_OFFSET 16 -#define D18F2x08C_Tref_WIDTH 2 -#define D18F2x08C_Tref_MASK 0x30000 -#define D18F2x08C_DisAutoRefresh_OFFSET 18 -#define D18F2x08C_DisAutoRefresh_WIDTH 1 -#define D18F2x08C_DisAutoRefresh_MASK 0x40000 -#define D18F2x08C_Reserved_19_19_OFFSET 19 -#define D18F2x08C_Reserved_19_19_WIDTH 1 -#define D18F2x08C_Reserved_19_19_MASK 0x80000 -#define D18F2x08C_Trfc0_OFFSET 20 -#define D18F2x08C_Trfc0_WIDTH 3 -#define D18F2x08C_Trfc0_MASK 0x700000 -#define D18F2x08C_Trfc1_OFFSET 23 -#define D18F2x08C_Trfc1_WIDTH 3 -#define D18F2x08C_Trfc1_MASK 0x3800000 -#define D18F2x08C_Reserved_31_26_OFFSET 26 -#define D18F2x08C_Reserved_31_26_WIDTH 6 -#define D18F2x08C_Reserved_31_26_MASK 0xfc000000 - -/// D18F2x08C -typedef union { - struct { ///< - UINT32 TrwtWB:4 ; ///< - UINT32 TrwtTO:4 ; ///< - UINT32 Reserved_9_8:2 ; ///< - UINT32 Twrrd_1_0_:2 ; ///< - UINT32 Twrwr_1_0_:2 ; ///< - UINT32 Trdrd_1_0_:2 ; ///< - UINT32 Tref:2 ; ///< - UINT32 DisAutoRefresh:1 ; ///< - UINT32 Reserved_19_19:1 ; ///< - UINT32 Trfc0:3 ; ///< - UINT32 Trfc1:3 ; ///< - UINT32 Reserved_31_26:6 ; ///< - } Field; ///< - UINT32 Value; ///< -} D18F2x08C_STRUCT; - -// **** D18F2x090 Register Definition **** -// Address -#define D18F2x090_ADDRESS 0x90 - -// Type -#define D18F2x090_TYPE TYPE_D18F2 -// Field Data -#define D18F2x090_Reserved_0_0_OFFSET 0 -#define D18F2x090_Reserved_0_0_WIDTH 1 -#define D18F2x090_Reserved_0_0_MASK 0x1 -#define D18F2x090_ExitSelfRef_OFFSET 1 -#define D18F2x090_ExitSelfRef_WIDTH 1 -#define D18F2x090_ExitSelfRef_MASK 0x2 -#define D18F2x090_Reserved_16_2_OFFSET 2 -#define D18F2x090_Reserved_16_2_WIDTH 15 -#define D18F2x090_Reserved_16_2_MASK 0x1fffc -#define D18F2x090_EnterSelfRef_OFFSET 17 -#define D18F2x090_EnterSelfRef_WIDTH 1 -#define D18F2x090_EnterSelfRef_MASK 0x20000 -#define D18F2x090_Reserved_19_18_OFFSET 18 -#define D18F2x090_Reserved_19_18_WIDTH 2 -#define D18F2x090_Reserved_19_18_MASK 0xc0000 -#define D18F2x090_DynPageCloseEn_OFFSET 20 -#define D18F2x090_DynPageCloseEn_WIDTH 1 -#define D18F2x090_DynPageCloseEn_MASK 0x100000 -#define D18F2x090_IdleCycInit_OFFSET 21 -#define D18F2x090_IdleCycInit_WIDTH 2 -#define D18F2x090_IdleCycInit_MASK 0x600000 -#define D18F2x090_ForceAutoPchg_OFFSET 23 -#define D18F2x090_ForceAutoPchg_WIDTH 1 -#define D18F2x090_ForceAutoPchg_MASK 0x800000 -#define D18F2x090_Reserved_24_24_OFFSET 24 -#define D18F2x090_Reserved_24_24_WIDTH 1 -#define D18F2x090_Reserved_24_24_MASK 0x1000000 -#define D18F2x090_EnDispAutoPrecharge_OFFSET 25 -#define D18F2x090_EnDispAutoPrecharge_WIDTH 1 -#define D18F2x090_EnDispAutoPrecharge_MASK 0x2000000 -#define D18F2x090_DbeSkidBufDis_OFFSET 26 -#define D18F2x090_DbeSkidBufDis_WIDTH 1 -#define D18F2x090_DbeSkidBufDis_MASK 0x4000000 -#define D18F2x090_DisDllShutdownSR_OFFSET 27 -#define D18F2x090_DisDllShutdownSR_WIDTH 1 -#define D18F2x090_DisDllShutdownSR_MASK 0x8000000 -#define D18F2x090_Reserved_28_28_OFFSET 28 -#define D18F2x090_Reserved_28_28_WIDTH 1 -#define D18F2x090_Reserved_28_28_MASK 0x10000000 -#define D18F2x090_Reserved_29_29_OFFSET 29 -#define D18F2x090_Reserved_29_29_WIDTH 1 -#define D18F2x090_Reserved_29_29_MASK 0x20000000 -#define D18F2x090_Reserved_31_30_OFFSET 30 -#define D18F2x090_Reserved_31_30_WIDTH 2 -#define D18F2x090_Reserved_31_30_MASK 0xc0000000 - -/// D18F2x090 -typedef union { - struct { ///< - UINT32 Reserved_0_0:1 ; ///< - UINT32 ExitSelfRef:1 ; ///< - UINT32 Reserved_16_2:15; ///< - UINT32 EnterSelfRef:1 ; ///< - UINT32 Reserved_19_18:2 ; ///< - UINT32 DynPageCloseEn:1 ; ///< - UINT32 IdleCycInit:2 ; ///< - UINT32 ForceAutoPchg:1 ; ///< - UINT32 Reserved_24_24:1 ; ///< - UINT32 EnDispAutoPrecharge:1 ; ///< - UINT32 DbeSkidBufDis:1 ; ///< - UINT32 DisDllShutdownSR:1 ; ///< - UINT32 Reserved_28_28:1 ; ///< - UINT32 Reserved_29_29:1 ; ///< - UINT32 Reserved_31_30:2 ; ///< - } Field; ///< - UINT32 Value; ///< -} D18F2x090_STRUCT; - -// **** D18F2x094 Register Definition **** -// Address -#define D18F2x094_ADDRESS 0x94 - -// Type -#define D18F2x094_TYPE TYPE_D18F2 -// Field Data -#define D18F2x094_MemClkFreq_OFFSET 0 -#define D18F2x094_MemClkFreq_WIDTH 5 -#define D18F2x094_MemClkFreq_MASK 0x1f -#define D18F2x094_Reserved_6_5_OFFSET 5 -#define D18F2x094_Reserved_6_5_WIDTH 2 -#define D18F2x094_Reserved_6_5_MASK 0x60 -#define D18F2x094_MemClkFreqVal_OFFSET 7 -#define D18F2x094_MemClkFreqVal_WIDTH 1 -#define D18F2x094_MemClkFreqVal_MASK 0x80 -#define D18F2x094_Reserved_9_8_OFFSET 8 -#define D18F2x094_Reserved_9_8_WIDTH 2 -#define D18F2x094_Reserved_9_8_MASK 0x300 -#define D18F2x094_ZqcsInterval_OFFSET 10 -#define D18F2x094_ZqcsInterval_WIDTH 2 -#define D18F2x094_ZqcsInterval_MASK 0xc00 -#define D18F2x094_Reserved_13_12_OFFSET 12 -#define D18F2x094_Reserved_13_12_WIDTH 2 -#define D18F2x094_Reserved_13_12_MASK 0x3000 -#define D18F2x094_DisDramInterface_OFFSET 14 -#define D18F2x094_DisDramInterface_WIDTH 1 -#define D18F2x094_DisDramInterface_MASK 0x4000 -#define D18F2x094_PowerDownEn_OFFSET 15 -#define D18F2x094_PowerDownEn_WIDTH 1 -#define D18F2x094_PowerDownEn_MASK 0x8000 -#define D18F2x094_PowerDownMode_OFFSET 16 -#define D18F2x094_PowerDownMode_WIDTH 1 -#define D18F2x094_PowerDownMode_MASK 0x10000 -#define D18F2x094_Reserved_19_17_OFFSET 17 -#define D18F2x094_Reserved_19_17_WIDTH 3 -#define D18F2x094_Reserved_19_17_MASK 0xe0000 -#define D18F2x094_SlowAccessMode_OFFSET 20 -#define D18F2x094_SlowAccessMode_WIDTH 1 -#define D18F2x094_SlowAccessMode_MASK 0x100000 -#define D18F2x094_Reserved_21_21_OFFSET 21 -#define D18F2x094_Reserved_21_21_WIDTH 1 -#define D18F2x094_Reserved_21_21_MASK 0x200000 -#define D18F2x094_BankSwizzleMode_OFFSET 22 -#define D18F2x094_BankSwizzleMode_WIDTH 1 -#define D18F2x094_BankSwizzleMode_MASK 0x400000 -#define D18F2x094_ProcOdtDis_OFFSET 23 -#define D18F2x094_ProcOdtDis_WIDTH 1 -#define D18F2x094_ProcOdtDis_MASK 0x800000 -#define D18F2x094_DcqBypassMax_OFFSET 24 -#define D18F2x094_DcqBypassMax_WIDTH 4 -#define D18F2x094_DcqBypassMax_MASK 0xf000000 -#define D18F2x094_FourActWindow_OFFSET 28 -#define D18F2x094_FourActWindow_WIDTH 4 -#define D18F2x094_FourActWindow_MASK 0xf0000000 - -/// D18F2x094 -typedef union { - struct { ///< - UINT32 MemClkFreq:5 ; ///< - UINT32 Reserved_6_5:2 ; ///< - UINT32 MemClkFreqVal:1 ; ///< - UINT32 Reserved_9_8:2 ; ///< - UINT32 ZqcsInterval:2 ; ///< - UINT32 Reserved_13_12:2 ; ///< - UINT32 DisDramInterface:1 ; ///< - UINT32 PowerDownEn:1 ; ///< - UINT32 PowerDownMode:1 ; ///< - UINT32 Reserved_19_17:3 ; ///< - UINT32 SlowAccessMode:1 ; ///< - UINT32 Reserved_21_21:1 ; ///< - UINT32 BankSwizzleMode:1 ; ///< - UINT32 ProcOdtDis:1 ; ///< - UINT32 DcqBypassMax:4 ; ///< - UINT32 FourActWindow:4 ; ///< - } Field; ///< - UINT32 Value; ///< -} D18F2x094_STRUCT; - -// **** D18F2x098 Register Definition **** -// Address -#define D18F2x098_ADDRESS 0x98 - -// Type -#define D18F2x098_TYPE TYPE_D18F2 -// Field Data -#define D18F2x098_DctOffset_OFFSET 0 -#define D18F2x098_DctOffset_WIDTH 30 -#define D18F2x098_DctOffset_MASK 0x3fffffff -#define D18F2x098_DctAccessWrite_OFFSET 30 -#define D18F2x098_DctAccessWrite_WIDTH 1 -#define D18F2x098_DctAccessWrite_MASK 0x40000000 -#define D18F2x098_Reserved_31_31_OFFSET 31 -#define D18F2x098_Reserved_31_31_WIDTH 1 -#define D18F2x098_Reserved_31_31_MASK 0x80000000 - -/// D18F2x098 -typedef union { - struct { ///< - UINT32 DctOffset:30; ///< - UINT32 DctAccessWrite:1 ; ///< - UINT32 Reserved_31_31:1 ; ///< - } Field; ///< - UINT32 Value; ///< -} D18F2x098_STRUCT; - -// **** D18F2x09C Register Definition **** -// Address -#define D18F2x09C_ADDRESS 0x9c - -// Type -#define D18F2x09C_TYPE TYPE_D18F2 -// Field Data -#define D18F2x09C_DctDataPort_OFFSET 0 -#define D18F2x09C_DctDataPort_WIDTH 32 -#define D18F2x09C_DctDataPort_MASK 0xffffffff - -/// D18F2x09C -typedef union { - struct { ///< - UINT32 DctDataPort:32; ///< - } Field; ///< - UINT32 Value; ///< -} D18F2x09C_STRUCT; - -// **** D18F2x0A0 Register Definition **** -// Address -#define D18F2x0A0_ADDRESS 0xa0 - -// Type -#define D18F2x0A0_TYPE TYPE_D18F2 -// Field Data -#define D18F2x0A0_Reserved_31_0_OFFSET 0 -#define D18F2x0A0_Reserved_31_0_WIDTH 32 -#define D18F2x0A0_Reserved_31_0_MASK 0xffffffff - -/// D18F2x0A0 -typedef union { - struct { ///< - UINT32 Reserved_31_0:32; ///< - } Field; ///< - UINT32 Value; ///< -} D18F2x0A0_STRUCT; - -// **** D18F2xA4 Register Definition **** -// Address -#define D18F2xA4_ADDRESS 0xa4 - -// Type -#define D18F2xA4_TYPE TYPE_D18F2 -// Field Data -#define D18F2xA4_DoubleTrefRateEn_OFFSET 0 -#define D18F2xA4_DoubleTrefRateEn_WIDTH 1 -#define D18F2xA4_DoubleTrefRateEn_MASK 0x1 -#define D18F2xA4_ThrottleEn_OFFSET 1 -#define D18F2xA4_ThrottleEn_WIDTH 2 -#define D18F2xA4_ThrottleEn_MASK 0x6 -#define D18F2xA4_Reserved_31_3_OFFSET 3 -#define D18F2xA4_Reserved_31_3_WIDTH 29 -#define D18F2xA4_Reserved_31_3_MASK 0xfffffff8 - -/// D18F2xA4 -typedef union { - struct { ///< - UINT32 DoubleTrefRateEn:1 ; ///< - UINT32 ThrottleEn:2 ; ///< - UINT32 Reserved_31_3:29; ///< - } Field; ///< - UINT32 Value; ///< -} D18F2xA4_STRUCT; - -// **** D18F2x0A8 Register Definition **** -// Address -#define D18F2x0A8_ADDRESS 0xa8 - -// Type -#define D18F2x0A8_TYPE TYPE_D18F2 -// Field Data -#define D18F2x0A8_Reserved_19_0_OFFSET 0 -#define D18F2x0A8_Reserved_19_0_WIDTH 20 -#define D18F2x0A8_Reserved_19_0_MASK 0xfffff -#define D18F2x0A8_BankSwap_OFFSET 20 -#define D18F2x0A8_BankSwap_WIDTH 1 -#define D18F2x0A8_BankSwap_MASK 0x100000 -#define D18F2x0A8_DbeGskMemClkAlignMode_OFFSET 21 -#define D18F2x0A8_DbeGskMemClkAlignMode_WIDTH 2 -#define D18F2x0A8_DbeGskMemClkAlignMode_MASK 0x600000 -#define D18F2x0A8_Reserved_31_23_OFFSET 23 -#define D18F2x0A8_Reserved_31_23_WIDTH 9 -#define D18F2x0A8_Reserved_31_23_MASK 0xff800000 - -/// D18F2x0A8 -typedef union { - struct { ///< - UINT32 Reserved_19_0:20; ///< - UINT32 BankSwap:1 ; ///< - UINT32 DbeGskMemClkAlignMode:2 ; ///< - UINT32 Reserved_31_23:9 ; ///< - } Field; ///< - UINT32 Value; ///< -} D18F2x0A8_STRUCT; - -// **** D18F2xAC Register Definition **** -// Address -#define D18F2xAC_ADDRESS 0xac - -// Type -#define D18F2xAC_TYPE TYPE_D18F2 -// Field Data -#define D18F2xAC_MemTempHot_OFFSET 0 -#define D18F2xAC_MemTempHot_WIDTH 1 -#define D18F2xAC_MemTempHot_MASK 0x1 -#define D18F2xAC_Reserved_31_1_OFFSET 1 -#define D18F2xAC_Reserved_31_1_WIDTH 31 -#define D18F2xAC_Reserved_31_1_MASK 0xfffffffe - -/// D18F2xAC -typedef union { - struct { ///< - UINT32 MemTempHot:1 ; ///< - UINT32 Reserved_31_1:31; ///< - } Field; ///< - UINT32 Value; ///< -} D18F2xAC_STRUCT; - -// **** D18F2x0F0 Register Definition **** -// Address -#define D18F2x0F0_ADDRESS 0xf0 - -// Type -#define D18F2x0F0_TYPE TYPE_D18F2 -// Field Data -#define D18F2x0F0_DctOffset_OFFSET 0 -#define D18F2x0F0_DctOffset_WIDTH 28 -#define D18F2x0F0_DctOffset_MASK 0xfffffff -#define D18F2x0F0_Reserved_29_28_OFFSET 28 -#define D18F2x0F0_Reserved_29_28_WIDTH 2 -#define D18F2x0F0_Reserved_29_28_MASK 0x30000000 -#define D18F2x0F0_DctAccessWrite_OFFSET 30 -#define D18F2x0F0_DctAccessWrite_WIDTH 1 -#define D18F2x0F0_DctAccessWrite_MASK 0x40000000 -#define D18F2x0F0_DctAccessDone_OFFSET 31 -#define D18F2x0F0_DctAccessDone_WIDTH 1 -#define D18F2x0F0_DctAccessDone_MASK 0x80000000 - -/// D18F2x0F0 -typedef union { - struct { ///< - UINT32 DctOffset:28; ///< - UINT32 Reserved_29_28:2 ; ///< - UINT32 DctAccessWrite:1 ; ///< - UINT32 DctAccessDone:1 ; ///< - } Field; ///< - UINT32 Value; ///< -} D18F2x0F0_STRUCT; - -// **** D18F2x0F4 Register Definition **** -// Address -#define D18F2x0F4_ADDRESS 0xf4 - -// Type -#define D18F2x0F4_TYPE TYPE_D18F2 -// Field Data -#define D18F2x0F4_DctExtDataPort_OFFSET 0 -#define D18F2x0F4_DctExtDataPort_WIDTH 32 -#define D18F2x0F4_DctExtDataPort_MASK 0xffffffff - -/// D18F2x0F4 -typedef union { - struct { ///< - UINT32 DctExtDataPort:32; ///< - } Field; ///< - UINT32 Value; ///< -} D18F2x0F4_STRUCT; - -// **** D18F2x10C Register Definition **** -// Address -#define D18F2x10C_ADDRESS 0x10c - -// Type -#define D18F2x10C_TYPE TYPE_D18F2 -// Field Data -#define D18F2x10C_IntLvRegionEn_OFFSET 0 -#define D18F2x10C_IntLvRegionEn_WIDTH 1 -#define D18F2x10C_IntLvRegionEn_MASK 0x1 -#define D18F2x10C_Reserved_2_1_OFFSET 1 -#define D18F2x10C_Reserved_2_1_WIDTH 2 -#define D18F2x10C_Reserved_2_1_MASK 0x6 -#define D18F2x10C_IntLvRegionBase_OFFSET 3 -#define D18F2x10C_IntLvRegionBase_WIDTH 5 -#define D18F2x10C_IntLvRegionBase_MASK 0xf8 -#define D18F2x10C_Reserved_10_8_OFFSET 8 -#define D18F2x10C_Reserved_10_8_WIDTH 3 -#define D18F2x10C_Reserved_10_8_MASK 0x700 -#define D18F2x10C_IntLvRegionLimit_OFFSET 11 -#define D18F2x10C_IntLvRegionLimit_WIDTH 5 -#define D18F2x10C_IntLvRegionLimit_MASK 0xf800 -#define D18F2x10C_Reserved_31_16_OFFSET 16 -#define D18F2x10C_Reserved_31_16_WIDTH 16 -#define D18F2x10C_Reserved_31_16_MASK 0xffff0000 - -/// D18F2x10C -typedef union { - struct { ///< - UINT32 IntLvRegionEn:1 ; ///< - UINT32 Reserved_2_1:2 ; ///< - UINT32 IntLvRegionBase:5 ; ///< - UINT32 Reserved_10_8:3 ; ///< - UINT32 IntLvRegionLimit:5 ; ///< - UINT32 Reserved_31_16:16; ///< - } Field; ///< - UINT32 Value; ///< -} D18F2x10C_STRUCT; - -// **** D18F2x110 Register Definition **** -// Address -#define D18F2x110_ADDRESS 0x110 - -// Type -#define D18F2x110_TYPE TYPE_D18F2 -// Field Data -#define D18F2x110_DctSelHiRngEn_OFFSET 0 -#define D18F2x110_DctSelHiRngEn_WIDTH 1 -#define D18F2x110_DctSelHiRngEn_MASK 0x1 -#define D18F2x110_DctSelHi_OFFSET 1 -#define D18F2x110_DctSelHi_WIDTH 1 -#define D18F2x110_DctSelHi_MASK 0x2 -#define D18F2x110_DctSelIntLvEn_OFFSET 2 -#define D18F2x110_DctSelIntLvEn_WIDTH 1 -#define D18F2x110_DctSelIntLvEn_MASK 0x4 -#define D18F2x110_MemClrInit_OFFSET 3 -#define D18F2x110_MemClrInit_WIDTH 1 -#define D18F2x110_MemClrInit_MASK 0x8 -#define D18F2x110_Reserved_5_4_OFFSET 4 -#define D18F2x110_Reserved_5_4_WIDTH 2 -#define D18F2x110_Reserved_5_4_MASK 0x30 -#define D18F2x110_DctSelIntLvAddr_1_0__OFFSET 6 -#define D18F2x110_DctSelIntLvAddr_1_0__WIDTH 2 -#define D18F2x110_DctSelIntLvAddr_1_0__MASK 0xc0 -#define D18F2x110_DramEnable_OFFSET 8 -#define D18F2x110_DramEnable_WIDTH 1 -#define D18F2x110_DramEnable_MASK 0x100 -#define D18F2x110_MemClrBusy_OFFSET 9 -#define D18F2x110_MemClrBusy_WIDTH 1 -#define D18F2x110_MemClrBusy_MASK 0x200 -#define D18F2x110_MemCleared_OFFSET 10 -#define D18F2x110_MemCleared_WIDTH 1 -#define D18F2x110_MemCleared_MASK 0x400 -#define D18F2x110_DctSelBaseAddr_39_27__OFFSET 11 -#define D18F2x110_DctSelBaseAddr_39_27__WIDTH 13 -#define D18F2x110_DctSelBaseAddr_39_27__MASK 0xfff800 -#define D18F2x110_Reserved_31_24_OFFSET 24 -#define D18F2x110_Reserved_31_24_WIDTH 8 -#define D18F2x110_Reserved_31_24_MASK 0xff000000 - -/// D18F2x110 -typedef union { - struct { ///< - UINT32 DctSelHiRngEn:1 ; ///< - UINT32 DctSelHi:1 ; ///< - UINT32 DctSelIntLvEn:1 ; ///< - UINT32 MemClrInit:1 ; ///< - UINT32 Reserved_5_4:2 ; ///< - UINT32 DctSelIntLvAddr_1_0_:2 ; ///< - UINT32 DramEnable:1 ; ///< - UINT32 MemClrBusy:1 ; ///< - UINT32 MemCleared:1 ; ///< - UINT32 DctSelBaseAddr_39_27_:13; ///< - UINT32 Reserved_31_24:8 ; ///< - } Field; ///< - UINT32 Value; ///< -} D18F2x110_STRUCT; - -// **** D18F2x114 Register Definition **** -// Address -#define D18F2x114_ADDRESS 0x114 - -// Type -#define D18F2x114_TYPE TYPE_D18F2 -// Field Data -#define D18F2x114_Reserved_8_0_OFFSET 0 -#define D18F2x114_Reserved_8_0_WIDTH 9 -#define D18F2x114_Reserved_8_0_MASK 0x1ff -#define D18F2x114_DctSelIntLvAddr_2__OFFSET 9 -#define D18F2x114_DctSelIntLvAddr_2__WIDTH 1 -#define D18F2x114_DctSelIntLvAddr_2__MASK 0x200 -#define D18F2x114_DctSelBaseOffset_39_26__OFFSET 10 -#define D18F2x114_DctSelBaseOffset_39_26__WIDTH 14 -#define D18F2x114_DctSelBaseOffset_39_26__MASK 0xfffc00 -#define D18F2x114_Reserved_31_24_OFFSET 24 -#define D18F2x114_Reserved_31_24_WIDTH 8 -#define D18F2x114_Reserved_31_24_MASK 0xff000000 - -/// D18F2x114 -typedef union { - struct { ///< - UINT32 Reserved_8_0:9 ; ///< - UINT32 DctSelIntLvAddr_2_:1 ; ///< - UINT32 DctSelBaseOffset_39_26_:14; ///< - UINT32 Reserved_31_24:8 ; ///< - } Field; ///< - UINT32 Value; ///< -} D18F2x114_STRUCT; - -// **** D18F2x118 Register Definition **** -// Address -#define D18F2x118_ADDRESS 0x118 - -// Type -#define D18F2x118_TYPE TYPE_D18F2 -// Field Data -#define D18F2x118_MctPriCpuRd_OFFSET 0 -#define D18F2x118_MctPriCpuRd_WIDTH 2 -#define D18F2x118_MctPriCpuRd_MASK 0x3 -#define D18F2x118_MctPriCpuWr_OFFSET 2 -#define D18F2x118_MctPriCpuWr_WIDTH 2 -#define D18F2x118_MctPriCpuWr_MASK 0xc -#define D18F2x118_MctPriHiRd_OFFSET 4 -#define D18F2x118_MctPriHiRd_WIDTH 2 -#define D18F2x118_MctPriHiRd_MASK 0x30 -#define D18F2x118_MctPriHiWr_OFFSET 6 -#define D18F2x118_MctPriHiWr_WIDTH 2 -#define D18F2x118_MctPriHiWr_MASK 0xc0 -#define D18F2x118_MctPriDefault_OFFSET 8 -#define D18F2x118_MctPriDefault_WIDTH 2 -#define D18F2x118_MctPriDefault_MASK 0x300 -#define D18F2x118_MctPriWr_OFFSET 10 -#define D18F2x118_MctPriWr_WIDTH 2 -#define D18F2x118_MctPriWr_MASK 0xc00 -#define D18F2x118_Reserved_18_12_OFFSET 12 -#define D18F2x118_Reserved_18_12_WIDTH 7 -#define D18F2x118_Reserved_18_12_MASK 0x7f000 -#define D18F2x118_C6DramLock_OFFSET 19 -#define D18F2x118_C6DramLock_WIDTH 1 -#define D18F2x118_C6DramLock_MASK 0x80000 -#define D18F2x118_Reserved_27_20_OFFSET 20 -#define D18F2x118_Reserved_27_20_WIDTH 8 -#define D18F2x118_Reserved_27_20_MASK 0xff00000 -#define D18F2x118_MctVarPriCntLmt_OFFSET 28 -#define D18F2x118_MctVarPriCntLmt_WIDTH 4 -#define D18F2x118_MctVarPriCntLmt_MASK 0xf0000000 - -/// D18F2x118 -typedef union { - struct { ///< - UINT32 MctPriCpuRd:2 ; ///< - UINT32 MctPriCpuWr:2 ; ///< - UINT32 MctPriHiRd:2 ; ///< - UINT32 MctPriHiWr:2 ; ///< - UINT32 MctPriDefault:2 ; ///< - UINT32 MctPriWr:2 ; ///< - UINT32 Reserved_18_12:7 ; ///< - UINT32 C6DramLock:1 ; ///< - UINT32 Reserved_27_20:8 ; ///< - UINT32 MctVarPriCntLmt:4 ; ///< - } Field; ///< - UINT32 Value; ///< -} D18F2x118_STRUCT; - -// **** D18F2x11C Register Definition **** -// Address -#define D18F2x11C_ADDRESS 0x11c - -// Type -#define D18F2x11C_TYPE TYPE_D18F2 -// Field Data -#define D18F2x11C_Reserved_1_0_OFFSET 0 -#define D18F2x11C_Reserved_1_0_WIDTH 2 -#define D18F2x11C_Reserved_1_0_MASK 0x3 -#define D18F2x11C_DctWrLimit_OFFSET 2 -#define D18F2x11C_DctWrLimit_WIDTH 5 -#define D18F2x11C_DctWrLimit_MASK 0x7c -#define D18F2x11C_Reserved_11_7_OFFSET 7 -#define D18F2x11C_Reserved_11_7_WIDTH 5 -#define D18F2x11C_Reserved_11_7_MASK 0xf80 -#define D18F2x11C_PrefCpuDis_OFFSET 12 -#define D18F2x11C_PrefCpuDis_WIDTH 1 -#define D18F2x11C_PrefCpuDis_MASK 0x1000 -#define D18F2x11C_Reserved_13_13_OFFSET 13 -#define D18F2x11C_Reserved_13_13_WIDTH 1 -#define D18F2x11C_Reserved_13_13_MASK 0x2000 -#define D18F2x11C_PrefCpuRdSzDis_OFFSET 14 -#define D18F2x11C_PrefCpuRdSzDis_WIDTH 1 -#define D18F2x11C_PrefCpuRdSzDis_MASK 0x4000 -#define D18F2x11C_Reserved_17_15_OFFSET 15 -#define D18F2x11C_Reserved_17_15_WIDTH 3 -#define D18F2x11C_Reserved_17_15_MASK 0x38000 -#define D18F2x11C_PrefConfSat_OFFSET 18 -#define D18F2x11C_PrefConfSat_WIDTH 2 -#define D18F2x11C_PrefConfSat_MASK 0xc0000 -#define D18F2x11C_Reserved_21_20_OFFSET 20 -#define D18F2x11C_Reserved_21_20_WIDTH 2 -#define D18F2x11C_Reserved_21_20_MASK 0x300000 -#define D18F2x11C_PrefConf_OFFSET 22 -#define D18F2x11C_PrefConf_WIDTH 3 -#define D18F2x11C_PrefConf_MASK 0x1c00000 -#define D18F2x11C_Reserved_28_25_OFFSET 25 -#define D18F2x11C_Reserved_28_25_WIDTH 4 -#define D18F2x11C_Reserved_28_25_MASK 0x1e000000 -#define D18F2x11C_FlushWrOnStpGnt_OFFSET 29 -#define D18F2x11C_FlushWrOnStpGnt_WIDTH 1 -#define D18F2x11C_FlushWrOnStpGnt_MASK 0x20000000 -#define D18F2x11C_FlushWr_OFFSET 30 -#define D18F2x11C_FlushWr_WIDTH 1 -#define D18F2x11C_FlushWr_MASK 0x40000000 -#define D18F2x11C_Reserved_31_31_OFFSET 31 -#define D18F2x11C_Reserved_31_31_WIDTH 1 -#define D18F2x11C_Reserved_31_31_MASK 0x80000000 - -/// D18F2x11C -typedef union { - struct { ///< - UINT32 Reserved_1_0:2 ; ///< - UINT32 DctWrLimit:5 ; ///< - UINT32 Reserved_11_7:5 ; ///< - UINT32 PrefCpuDis:1 ; ///< - UINT32 Reserved_13_13:1 ; ///< - UINT32 PrefCpuRdSzDis:1 ; ///< - UINT32 Reserved_17_15:3 ; ///< - UINT32 PrefConfSat:2 ; ///< - UINT32 Reserved_21_20:2 ; ///< - UINT32 PrefConf:3 ; ///< - UINT32 Reserved_28_25:4 ; ///< - UINT32 FlushWrOnStpGnt:1 ; ///< - UINT32 FlushWr:1 ; ///< - UINT32 Reserved_31_31:1 ; ///< - } Field; ///< - UINT32 Value; ///< -} D18F2x11C_STRUCT; - -// **** D18F2x140 Register Definition **** -// Address -#define D18F2x140_ADDRESS 0x140 - -// Type -#define D18F2x140_TYPE TYPE_D18F2 -// Field Data -#define D18F2x140_CSEnable_OFFSET 0 -#define D18F2x140_CSEnable_WIDTH 1 -#define D18F2x140_CSEnable_MASK 0x1 -#define D18F2x140_Reserved_1_1_OFFSET 1 -#define D18F2x140_Reserved_1_1_WIDTH 1 -#define D18F2x140_Reserved_1_1_MASK 0x2 -#define D18F2x140_TestFail_OFFSET 2 -#define D18F2x140_TestFail_WIDTH 1 -#define D18F2x140_TestFail_MASK 0x4 -#define D18F2x140_OnDimmMirror_OFFSET 3 -#define D18F2x140_OnDimmMirror_WIDTH 1 -#define D18F2x140_OnDimmMirror_MASK 0x8 -#define D18F2x140_Reserved_4_4_OFFSET 4 -#define D18F2x140_Reserved_4_4_WIDTH 1 -#define D18F2x140_Reserved_4_4_MASK 0x10 -#define D18F2x140_BaseAddr_21_13__OFFSET 5 -#define D18F2x140_BaseAddr_21_13__WIDTH 9 -#define D18F2x140_BaseAddr_21_13__MASK 0x3fe0 -#define D18F2x140_Reserved_18_14_OFFSET 14 -#define D18F2x140_Reserved_18_14_WIDTH 5 -#define D18F2x140_Reserved_18_14_MASK 0x7c000 -#define D18F2x140_BaseAddr_36_27__OFFSET 19 -#define D18F2x140_BaseAddr_36_27__WIDTH 10 -#define D18F2x140_BaseAddr_36_27__MASK 0x1ff80000 -#define D18F2x140_Reserved_31_29_OFFSET 29 -#define D18F2x140_Reserved_31_29_WIDTH 3 -#define D18F2x140_Reserved_31_29_MASK 0xe0000000 - -/// D18F2x140 -typedef union { - struct { ///< - UINT32 CSEnable:1 ; ///< - UINT32 Reserved_1_1:1 ; ///< - UINT32 TestFail:1 ; ///< - UINT32 OnDimmMirror:1 ; ///< - UINT32 Reserved_4_4:1 ; ///< - UINT32 BaseAddr_21_13_:9 ; ///< - UINT32 Reserved_18_14:5 ; ///< - UINT32 BaseAddr_36_27_:10; ///< - UINT32 Reserved_31_29:3 ; ///< - } Field; ///< - UINT32 Value; ///< -} D18F2x140_STRUCT; - -// **** D18F2x144 Register Definition **** -// Address -#define D18F2x144_ADDRESS 0x144 - -// Type -#define D18F2x144_TYPE TYPE_D18F2 -// Field Data -#define D18F2x144_CSEnable_OFFSET 0 -#define D18F2x144_CSEnable_WIDTH 1 -#define D18F2x144_CSEnable_MASK 0x1 -#define D18F2x144_Reserved_1_1_OFFSET 1 -#define D18F2x144_Reserved_1_1_WIDTH 1 -#define D18F2x144_Reserved_1_1_MASK 0x2 -#define D18F2x144_TestFail_OFFSET 2 -#define D18F2x144_TestFail_WIDTH 1 -#define D18F2x144_TestFail_MASK 0x4 -#define D18F2x144_OnDimmMirror_OFFSET 3 -#define D18F2x144_OnDimmMirror_WIDTH 1 -#define D18F2x144_OnDimmMirror_MASK 0x8 -#define D18F2x144_Reserved_4_4_OFFSET 4 -#define D18F2x144_Reserved_4_4_WIDTH 1 -#define D18F2x144_Reserved_4_4_MASK 0x10 -#define D18F2x144_BaseAddr_21_13__OFFSET 5 -#define D18F2x144_BaseAddr_21_13__WIDTH 9 -#define D18F2x144_BaseAddr_21_13__MASK 0x3fe0 -#define D18F2x144_Reserved_18_14_OFFSET 14 -#define D18F2x144_Reserved_18_14_WIDTH 5 -#define D18F2x144_Reserved_18_14_MASK 0x7c000 -#define D18F2x144_BaseAddr_36_27__OFFSET 19 -#define D18F2x144_BaseAddr_36_27__WIDTH 10 -#define D18F2x144_BaseAddr_36_27__MASK 0x1ff80000 -#define D18F2x144_Reserved_31_29_OFFSET 29 -#define D18F2x144_Reserved_31_29_WIDTH 3 -#define D18F2x144_Reserved_31_29_MASK 0xe0000000 - -/// D18F2x144 -typedef union { - struct { ///< - UINT32 CSEnable:1 ; ///< - UINT32 Reserved_1_1:1 ; ///< - UINT32 TestFail:1 ; ///< - UINT32 OnDimmMirror:1 ; ///< - UINT32 Reserved_4_4:1 ; ///< - UINT32 BaseAddr_21_13_:9 ; ///< - UINT32 Reserved_18_14:5 ; ///< - UINT32 BaseAddr_36_27_:10; ///< - UINT32 Reserved_31_29:3 ; ///< - } Field; ///< - UINT32 Value; ///< -} D18F2x144_STRUCT; - -// **** D18F2x148 Register Definition **** -// Address -#define D18F2x148_ADDRESS 0x148 - -// Type -#define D18F2x148_TYPE TYPE_D18F2 -// Field Data -#define D18F2x148_CSEnable_OFFSET 0 -#define D18F2x148_CSEnable_WIDTH 1 -#define D18F2x148_CSEnable_MASK 0x1 -#define D18F2x148_Reserved_1_1_OFFSET 1 -#define D18F2x148_Reserved_1_1_WIDTH 1 -#define D18F2x148_Reserved_1_1_MASK 0x2 -#define D18F2x148_TestFail_OFFSET 2 -#define D18F2x148_TestFail_WIDTH 1 -#define D18F2x148_TestFail_MASK 0x4 -#define D18F2x148_OnDimmMirror_OFFSET 3 -#define D18F2x148_OnDimmMirror_WIDTH 1 -#define D18F2x148_OnDimmMirror_MASK 0x8 -#define D18F2x148_Reserved_4_4_OFFSET 4 -#define D18F2x148_Reserved_4_4_WIDTH 1 -#define D18F2x148_Reserved_4_4_MASK 0x10 -#define D18F2x148_BaseAddr_21_13__OFFSET 5 -#define D18F2x148_BaseAddr_21_13__WIDTH 9 -#define D18F2x148_BaseAddr_21_13__MASK 0x3fe0 -#define D18F2x148_Reserved_18_14_OFFSET 14 -#define D18F2x148_Reserved_18_14_WIDTH 5 -#define D18F2x148_Reserved_18_14_MASK 0x7c000 -#define D18F2x148_BaseAddr_36_27__OFFSET 19 -#define D18F2x148_BaseAddr_36_27__WIDTH 10 -#define D18F2x148_BaseAddr_36_27__MASK 0x1ff80000 -#define D18F2x148_Reserved_31_29_OFFSET 29 -#define D18F2x148_Reserved_31_29_WIDTH 3 -#define D18F2x148_Reserved_31_29_MASK 0xe0000000 - -/// D18F2x148 -typedef union { - struct { ///< - UINT32 CSEnable:1 ; ///< - UINT32 Reserved_1_1:1 ; ///< - UINT32 TestFail:1 ; ///< - UINT32 OnDimmMirror:1 ; ///< - UINT32 Reserved_4_4:1 ; ///< - UINT32 BaseAddr_21_13_:9 ; ///< - UINT32 Reserved_18_14:5 ; ///< - UINT32 BaseAddr_36_27_:10; ///< - UINT32 Reserved_31_29:3 ; ///< - } Field; ///< - UINT32 Value; ///< -} D18F2x148_STRUCT; - -// **** D18F2x14C Register Definition **** -// Address -#define D18F2x14C_ADDRESS 0x14c - -// Type -#define D18F2x14C_TYPE TYPE_D18F2 -// Field Data -#define D18F2x14C_CSEnable_OFFSET 0 -#define D18F2x14C_CSEnable_WIDTH 1 -#define D18F2x14C_CSEnable_MASK 0x1 -#define D18F2x14C_Reserved_1_1_OFFSET 1 -#define D18F2x14C_Reserved_1_1_WIDTH 1 -#define D18F2x14C_Reserved_1_1_MASK 0x2 -#define D18F2x14C_TestFail_OFFSET 2 -#define D18F2x14C_TestFail_WIDTH 1 -#define D18F2x14C_TestFail_MASK 0x4 -#define D18F2x14C_OnDimmMirror_OFFSET 3 -#define D18F2x14C_OnDimmMirror_WIDTH 1 -#define D18F2x14C_OnDimmMirror_MASK 0x8 -#define D18F2x14C_Reserved_4_4_OFFSET 4 -#define D18F2x14C_Reserved_4_4_WIDTH 1 -#define D18F2x14C_Reserved_4_4_MASK 0x10 -#define D18F2x14C_BaseAddr_21_13__OFFSET 5 -#define D18F2x14C_BaseAddr_21_13__WIDTH 9 -#define D18F2x14C_BaseAddr_21_13__MASK 0x3fe0 -#define D18F2x14C_Reserved_18_14_OFFSET 14 -#define D18F2x14C_Reserved_18_14_WIDTH 5 -#define D18F2x14C_Reserved_18_14_MASK 0x7c000 -#define D18F2x14C_BaseAddr_36_27__OFFSET 19 -#define D18F2x14C_BaseAddr_36_27__WIDTH 10 -#define D18F2x14C_BaseAddr_36_27__MASK 0x1ff80000 -#define D18F2x14C_Reserved_31_29_OFFSET 29 -#define D18F2x14C_Reserved_31_29_WIDTH 3 -#define D18F2x14C_Reserved_31_29_MASK 0xe0000000 - -/// D18F2x14C -typedef union { - struct { ///< - UINT32 CSEnable:1 ; ///< - UINT32 Reserved_1_1:1 ; ///< - UINT32 TestFail:1 ; ///< - UINT32 OnDimmMirror:1 ; ///< - UINT32 Reserved_4_4:1 ; ///< - UINT32 BaseAddr_21_13_:9 ; ///< - UINT32 Reserved_18_14:5 ; ///< - UINT32 BaseAddr_36_27_:10; ///< - UINT32 Reserved_31_29:3 ; ///< - } Field; ///< - UINT32 Value; ///< -} D18F2x14C_STRUCT; - -// **** D18F2x160 Register Definition **** -// Address -#define D18F2x160_ADDRESS 0x160 - -// Type -#define D18F2x160_TYPE TYPE_D18F2 -// Field Data -#define D18F2x160_Reserved_4_0_OFFSET 0 -#define D18F2x160_Reserved_4_0_WIDTH 5 -#define D18F2x160_Reserved_4_0_MASK 0x1f -#define D18F2x160_AddrMask_21_13__OFFSET 5 -#define D18F2x160_AddrMask_21_13__WIDTH 9 -#define D18F2x160_AddrMask_21_13__MASK 0x3fe0 -#define D18F2x160_Reserved_18_14_OFFSET 14 -#define D18F2x160_Reserved_18_14_WIDTH 5 -#define D18F2x160_Reserved_18_14_MASK 0x7c000 -#define D18F2x160_AddrMask_36_27__OFFSET 19 -#define D18F2x160_AddrMask_36_27__WIDTH 10 -#define D18F2x160_AddrMask_36_27__MASK 0x1ff80000 -#define D18F2x160_Reserved_31_29_OFFSET 29 -#define D18F2x160_Reserved_31_29_WIDTH 3 -#define D18F2x160_Reserved_31_29_MASK 0xe0000000 - -/// D18F2x160 -typedef union { - struct { ///< - UINT32 Reserved_4_0:5 ; ///< - UINT32 AddrMask_21_13_:9 ; ///< - UINT32 Reserved_18_14:5 ; ///< - UINT32 AddrMask_36_27_:10; ///< - UINT32 Reserved_31_29:3 ; ///< - } Field; ///< - UINT32 Value; ///< -} D18F2x160_STRUCT; - -// **** D18F2x164 Register Definition **** -// Address -#define D18F2x164_ADDRESS 0x164 - -// Type -#define D18F2x164_TYPE TYPE_D18F2 -// Field Data -#define D18F2x164_Reserved_4_0_OFFSET 0 -#define D18F2x164_Reserved_4_0_WIDTH 5 -#define D18F2x164_Reserved_4_0_MASK 0x1f -#define D18F2x164_AddrMask_21_13__OFFSET 5 -#define D18F2x164_AddrMask_21_13__WIDTH 9 -#define D18F2x164_AddrMask_21_13__MASK 0x3fe0 -#define D18F2x164_Reserved_18_14_OFFSET 14 -#define D18F2x164_Reserved_18_14_WIDTH 5 -#define D18F2x164_Reserved_18_14_MASK 0x7c000 -#define D18F2x164_AddrMask_36_27__OFFSET 19 -#define D18F2x164_AddrMask_36_27__WIDTH 10 -#define D18F2x164_AddrMask_36_27__MASK 0x1ff80000 -#define D18F2x164_Reserved_31_29_OFFSET 29 -#define D18F2x164_Reserved_31_29_WIDTH 3 -#define D18F2x164_Reserved_31_29_MASK 0xe0000000 - -/// D18F2x164 -typedef union { - struct { ///< - UINT32 Reserved_4_0:5 ; ///< - UINT32 AddrMask_21_13_:9 ; ///< - UINT32 Reserved_18_14:5 ; ///< - UINT32 AddrMask_36_27_:10; ///< - UINT32 Reserved_31_29:3 ; ///< - } Field; ///< - UINT32 Value; ///< -} D18F2x164_STRUCT; - -// **** D18F2x178 Register Definition **** -// Address -#define D18F2x178_ADDRESS 0x178 - -// Type -#define D18F2x178_TYPE TYPE_D18F2 -// Field Data -#define D18F2x178_RdPtrInit_OFFSET 0 -#define D18F2x178_RdPtrInit_WIDTH 4 -#define D18F2x178_RdPtrInit_MASK 0xf -#define D18F2x178_Reserved_5_4_OFFSET 4 -#define D18F2x178_Reserved_5_4_WIDTH 2 -#define D18F2x178_Reserved_5_4_MASK 0x30 -#define D18F2x178_RxPtrInitReq_OFFSET 6 -#define D18F2x178_RxPtrInitReq_WIDTH 1 -#define D18F2x178_RxPtrInitReq_MASK 0x40 -#define D18F2x178_Reserved_7_7_OFFSET 7 -#define D18F2x178_Reserved_7_7_WIDTH 1 -#define D18F2x178_Reserved_7_7_MASK 0x80 -#define D18F2x178_Twrrd_3_2__OFFSET 8 -#define D18F2x178_Twrrd_3_2__WIDTH 2 -#define D18F2x178_Twrrd_3_2__MASK 0x300 -#define D18F2x178_Twrwr_3_2__OFFSET 10 -#define D18F2x178_Twrwr_3_2__WIDTH 2 -#define D18F2x178_Twrwr_3_2__MASK 0xc00 -#define D18F2x178_Trdrd_3_2__OFFSET 12 -#define D18F2x178_Trdrd_3_2__WIDTH 2 -#define D18F2x178_Trdrd_3_2__MASK 0x3000 -#define D18F2x178_Reserved_14_14_OFFSET 14 -#define D18F2x178_Reserved_14_14_WIDTH 1 -#define D18F2x178_Reserved_14_14_MASK 0x4000 -#define D18F2x178_Reserved_15_15_OFFSET 15 -#define D18F2x178_Reserved_15_15_WIDTH 1 -#define D18F2x178_Reserved_15_15_MASK 0x8000 -#define D18F2x178_Reserved_16_16_OFFSET 16 -#define D18F2x178_Reserved_16_16_WIDTH 1 -#define D18F2x178_Reserved_16_16_MASK 0x10000 -#define D18F2x178_AddrCmdTriEn_OFFSET 17 -#define D18F2x178_AddrCmdTriEn_WIDTH 1 -#define D18F2x178_AddrCmdTriEn_MASK 0x20000 -#define D18F2x178_Reserved_18_18_OFFSET 18 -#define D18F2x178_Reserved_18_18_WIDTH 1 -#define D18F2x178_Reserved_18_18_MASK 0x40000 -#define D18F2x178_Reserved_19_19_OFFSET 19 -#define D18F2x178_Reserved_19_19_WIDTH 1 -#define D18F2x178_Reserved_19_19_MASK 0x80000 -#define D18F2x178_ForceCasToSlot_OFFSET 20 -#define D18F2x178_ForceCasToSlot_WIDTH 1 -#define D18F2x178_ForceCasToSlot_MASK 0x100000 -#define D18F2x178_DisCutThroughMode_OFFSET 21 -#define D18F2x178_DisCutThroughMode_WIDTH 1 -#define D18F2x178_DisCutThroughMode_MASK 0x200000 -#define D18F2x178_MaxRdLatency_OFFSET 22 -#define D18F2x178_MaxRdLatency_WIDTH 10 -#define D18F2x178_MaxRdLatency_MASK 0xffc00000 - -/// D18F2x178 -typedef union { - struct { ///< - UINT32 RdPtrInit:4 ; ///< - UINT32 Reserved_5_4:2 ; ///< - UINT32 RxPtrInitReq:1 ; ///< - UINT32 Reserved_7_7:1 ; ///< - UINT32 Twrrd_3_2_:2 ; ///< - UINT32 Twrwr_3_2_:2 ; ///< - UINT32 Trdrd_3_2_:2 ; ///< - UINT32 Reserved_14_14:1 ; ///< - UINT32 Reserved_15_15:1 ; ///< - UINT32 Reserved_16_16:1 ; ///< - UINT32 AddrCmdTriEn:1 ; ///< - UINT32 Reserved_18_18:1 ; ///< - UINT32 Reserved_19_19:1 ; ///< - UINT32 ForceCasToSlot:1 ; ///< - UINT32 DisCutThroughMode:1 ; ///< - UINT32 MaxRdLatency:10; ///< - } Field; ///< - UINT32 Value; ///< -} D18F2x178_STRUCT; - -// **** D18F2x17C Register Definition **** -// Address -#define D18F2x17C_ADDRESS 0x17c - -// Type -#define D18F2x17C_TYPE TYPE_D18F2 -// Field Data -#define D18F2x17C_MrsAddress_OFFSET 0 -#define D18F2x17C_MrsAddress_WIDTH 16 -#define D18F2x17C_MrsAddress_MASK 0xffff -#define D18F2x17C_MrsBank_OFFSET 16 -#define D18F2x17C_MrsBank_WIDTH 3 -#define D18F2x17C_MrsBank_MASK 0x70000 -#define D18F2x17C_Reserved_19_19_OFFSET 19 -#define D18F2x17C_Reserved_19_19_WIDTH 1 -#define D18F2x17C_Reserved_19_19_MASK 0x80000 -#define D18F2x17C_MrsChipSel_OFFSET 20 -#define D18F2x17C_MrsChipSel_WIDTH 3 -#define D18F2x17C_MrsChipSel_MASK 0x700000 -#define D18F2x17C_Reserved_23_23_OFFSET 23 -#define D18F2x17C_Reserved_23_23_WIDTH 1 -#define D18F2x17C_Reserved_23_23_MASK 0x800000 -#define D18F2x17C_SendPchgAll_OFFSET 24 -#define D18F2x17C_SendPchgAll_WIDTH 1 -#define D18F2x17C_SendPchgAll_MASK 0x1000000 -#define D18F2x17C_SendAutoRefresh_OFFSET 25 -#define D18F2x17C_SendAutoRefresh_WIDTH 1 -#define D18F2x17C_SendAutoRefresh_MASK 0x2000000 -#define D18F2x17C_SendMrsCmd_OFFSET 26 -#define D18F2x17C_SendMrsCmd_WIDTH 1 -#define D18F2x17C_SendMrsCmd_MASK 0x4000000 -#define D18F2x17C_DeassertMemRstX_OFFSET 27 -#define D18F2x17C_DeassertMemRstX_WIDTH 1 -#define D18F2x17C_DeassertMemRstX_MASK 0x8000000 -#define D18F2x17C_AssertCke_OFFSET 28 -#define D18F2x17C_AssertCke_WIDTH 1 -#define D18F2x17C_AssertCke_MASK 0x10000000 -#define D18F2x17C_SendZQCmd_OFFSET 29 -#define D18F2x17C_SendZQCmd_WIDTH 1 -#define D18F2x17C_SendZQCmd_MASK 0x20000000 -#define D18F2x17C_Reserved_30_30_OFFSET 30 -#define D18F2x17C_Reserved_30_30_WIDTH 1 -#define D18F2x17C_Reserved_30_30_MASK 0x40000000 -#define D18F2x17C_EnDramInit_OFFSET 31 -#define D18F2x17C_EnDramInit_WIDTH 1 -#define D18F2x17C_EnDramInit_MASK 0x80000000 - -/// D18F2x17C -typedef union { - struct { ///< - UINT32 MrsAddress:16; ///< - UINT32 MrsBank:3 ; ///< - UINT32 Reserved_19_19:1 ; ///< - UINT32 MrsChipSel:3 ; ///< - UINT32 Reserved_23_23:1 ; ///< - UINT32 SendPchgAll:1 ; ///< - UINT32 SendAutoRefresh:1 ; ///< - UINT32 SendMrsCmd:1 ; ///< - UINT32 DeassertMemRstX:1 ; ///< - UINT32 AssertCke:1 ; ///< - UINT32 SendZQCmd:1 ; ///< - UINT32 Reserved_30_30:1 ; ///< - UINT32 EnDramInit:1 ; ///< - } Field; ///< - UINT32 Value; ///< -} D18F2x17C_STRUCT; - -// **** D18F2x180 Register Definition **** -// Address -#define D18F2x180_ADDRESS 0x180 - -// Type -#define D18F2x180_TYPE TYPE_D18F2 -// Field Data -#define D18F2x180_Dimm0AddrMap_OFFSET 0 -#define D18F2x180_Dimm0AddrMap_WIDTH 4 -#define D18F2x180_Dimm0AddrMap_MASK 0xf -#define D18F2x180_Dimm1AddrMap_OFFSET 4 -#define D18F2x180_Dimm1AddrMap_WIDTH 4 -#define D18F2x180_Dimm1AddrMap_MASK 0xf0 -#define D18F2x180_Reserved_31_8_OFFSET 8 -#define D18F2x180_Reserved_31_8_WIDTH 24 -#define D18F2x180_Reserved_31_8_MASK 0xffffff00 - -/// D18F2x180 -typedef union { - struct { ///< - UINT32 Dimm0AddrMap:4 ; ///< - UINT32 Dimm1AddrMap:4 ; ///< - UINT32 Reserved_31_8:24; ///< - } Field; ///< - UINT32 Value; ///< -} D18F2x180_STRUCT; - -// **** D18F2x184 Register Definition **** -// Address -#define D18F2x184_ADDRESS 0x184 - -// Type -#define D18F2x184_TYPE TYPE_D18F2 -// Field Data -#define D18F2x184_BurstCtrl_OFFSET 0 -#define D18F2x184_BurstCtrl_WIDTH 2 -#define D18F2x184_BurstCtrl_MASK 0x3 -#define D18F2x184_Reserved_3_2_OFFSET 2 -#define D18F2x184_Reserved_3_2_WIDTH 2 -#define D18F2x184_Reserved_3_2_MASK 0xc -#define D18F2x184_Twr_OFFSET 4 -#define D18F2x184_Twr_WIDTH 3 -#define D18F2x184_Twr_MASK 0x70 -#define D18F2x184_Reserved_19_7_OFFSET 7 -#define D18F2x184_Reserved_19_7_WIDTH 13 -#define D18F2x184_Reserved_19_7_MASK 0xfff80 -#define D18F2x184_Tcwl_OFFSET 20 -#define D18F2x184_Tcwl_WIDTH 3 -#define D18F2x184_Tcwl_MASK 0x700000 -#define D18F2x184_PchgPDModeSel_OFFSET 23 -#define D18F2x184_PchgPDModeSel_WIDTH 1 -#define D18F2x184_PchgPDModeSel_MASK 0x800000 -#define D18F2x184_Reserved_31_24_OFFSET 24 -#define D18F2x184_Reserved_31_24_WIDTH 8 -#define D18F2x184_Reserved_31_24_MASK 0xff000000 - -/// D18F2x184 -typedef union { - struct { ///< - UINT32 BurstCtrl:2 ; ///< - UINT32 Reserved_3_2:2 ; ///< - UINT32 Twr:3 ; ///< - UINT32 Reserved_19_7:13; ///< - UINT32 Tcwl:3 ; ///< - UINT32 PchgPDModeSel:1 ; ///< - UINT32 Reserved_31_24:8 ; ///< - } Field; ///< - UINT32 Value; ///< -} D18F2x184_STRUCT; - -// **** D18F2x188 Register Definition **** -// Address -#define D18F2x188_ADDRESS 0x188 - -// Type -#define D18F2x188_TYPE TYPE_D18F2 -// Field Data -#define D18F2x188_Tcl_OFFSET 0 -#define D18F2x188_Tcl_WIDTH 4 -#define D18F2x188_Tcl_MASK 0xf -#define D18F2x188_Reserved_23_4_OFFSET 4 -#define D18F2x188_Reserved_23_4_WIDTH 20 -#define D18F2x188_Reserved_23_4_MASK 0xfffff0 -#define D18F2x188_MemClkDis_OFFSET 24 -#define D18F2x188_MemClkDis_WIDTH 8 -#define D18F2x188_MemClkDis_MASK 0xff000000 - -/// D18F2x188 -typedef union { - struct { ///< - UINT32 Tcl:4 ; ///< - UINT32 Reserved_23_4:20; ///< - UINT32 MemClkDis:8 ; ///< - } Field; ///< - UINT32 Value; ///< -} D18F2x188_STRUCT; - -// **** D18F2x18C Register Definition **** -// Address -#define D18F2x18C_ADDRESS 0x18c - -// Type -#define D18F2x18C_TYPE TYPE_D18F2 -// Field Data -#define D18F2x18C_TrwtWB_OFFSET 0 -#define D18F2x18C_TrwtWB_WIDTH 4 -#define D18F2x18C_TrwtWB_MASK 0xf -#define D18F2x18C_TrwtTO_OFFSET 4 -#define D18F2x18C_TrwtTO_WIDTH 4 -#define D18F2x18C_TrwtTO_MASK 0xf0 -#define D18F2x18C_Reserved_9_8_OFFSET 8 -#define D18F2x18C_Reserved_9_8_WIDTH 2 -#define D18F2x18C_Reserved_9_8_MASK 0x300 -#define D18F2x18C_Twrrd_1_0__OFFSET 10 -#define D18F2x18C_Twrrd_1_0__WIDTH 2 -#define D18F2x18C_Twrrd_1_0__MASK 0xc00 -#define D18F2x18C_Twrwr_1_0__OFFSET 12 -#define D18F2x18C_Twrwr_1_0__WIDTH 2 -#define D18F2x18C_Twrwr_1_0__MASK 0x3000 -#define D18F2x18C_Trdrd_1_0__OFFSET 14 -#define D18F2x18C_Trdrd_1_0__WIDTH 2 -#define D18F2x18C_Trdrd_1_0__MASK 0xc000 -#define D18F2x18C_Tref_OFFSET 16 -#define D18F2x18C_Tref_WIDTH 2 -#define D18F2x18C_Tref_MASK 0x30000 -#define D18F2x18C_DisAutoRefresh_OFFSET 18 -#define D18F2x18C_DisAutoRefresh_WIDTH 1 -#define D18F2x18C_DisAutoRefresh_MASK 0x40000 -#define D18F2x18C_Reserved_19_19_OFFSET 19 -#define D18F2x18C_Reserved_19_19_WIDTH 1 -#define D18F2x18C_Reserved_19_19_MASK 0x80000 -#define D18F2x18C_Trfc0_OFFSET 20 -#define D18F2x18C_Trfc0_WIDTH 3 -#define D18F2x18C_Trfc0_MASK 0x700000 -#define D18F2x18C_Trfc1_OFFSET 23 -#define D18F2x18C_Trfc1_WIDTH 3 -#define D18F2x18C_Trfc1_MASK 0x3800000 -#define D18F2x18C_Reserved_31_26_OFFSET 26 -#define D18F2x18C_Reserved_31_26_WIDTH 6 -#define D18F2x18C_Reserved_31_26_MASK 0xfc000000 - -/// D18F2x18C -typedef union { - struct { ///< - UINT32 TrwtWB:4 ; ///< - UINT32 TrwtTO:4 ; ///< - UINT32 Reserved_9_8:2 ; ///< - UINT32 Twrrd_1_0_:2 ; ///< - UINT32 Twrwr_1_0_:2 ; ///< - UINT32 Trdrd_1_0_:2 ; ///< - UINT32 Tref:2 ; ///< - UINT32 DisAutoRefresh:1 ; ///< - UINT32 Reserved_19_19:1 ; ///< - UINT32 Trfc0:3 ; ///< - UINT32 Trfc1:3 ; ///< - UINT32 Reserved_31_26:6 ; ///< - } Field; ///< - UINT32 Value; ///< -} D18F2x18C_STRUCT; - -// **** D18F2x190 Register Definition **** -// Address -#define D18F2x190_ADDRESS 0x190 - -// Type -#define D18F2x190_TYPE TYPE_D18F2 -// Field Data -#define D18F2x190_Reserved_0_0_OFFSET 0 -#define D18F2x190_Reserved_0_0_WIDTH 1 -#define D18F2x190_Reserved_0_0_MASK 0x1 -#define D18F2x190_ExitSelfRef_OFFSET 1 -#define D18F2x190_ExitSelfRef_WIDTH 1 -#define D18F2x190_ExitSelfRef_MASK 0x2 -#define D18F2x190_Reserved_16_2_OFFSET 2 -#define D18F2x190_Reserved_16_2_WIDTH 15 -#define D18F2x190_Reserved_16_2_MASK 0x1fffc -#define D18F2x190_EnterSelfRef_OFFSET 17 -#define D18F2x190_EnterSelfRef_WIDTH 1 -#define D18F2x190_EnterSelfRef_MASK 0x20000 -#define D18F2x190_Reserved_19_18_OFFSET 18 -#define D18F2x190_Reserved_19_18_WIDTH 2 -#define D18F2x190_Reserved_19_18_MASK 0xc0000 -#define D18F2x190_DynPageCloseEn_OFFSET 20 -#define D18F2x190_DynPageCloseEn_WIDTH 1 -#define D18F2x190_DynPageCloseEn_MASK 0x100000 -#define D18F2x190_IdleCycInit_OFFSET 21 -#define D18F2x190_IdleCycInit_WIDTH 2 -#define D18F2x190_IdleCycInit_MASK 0x600000 -#define D18F2x190_ForceAutoPchg_OFFSET 23 -#define D18F2x190_ForceAutoPchg_WIDTH 1 -#define D18F2x190_ForceAutoPchg_MASK 0x800000 -#define D18F2x190_Reserved_24_24_OFFSET 24 -#define D18F2x190_Reserved_24_24_WIDTH 1 -#define D18F2x190_Reserved_24_24_MASK 0x1000000 -#define D18F2x190_EnDispAutoPrecharge_OFFSET 25 -#define D18F2x190_EnDispAutoPrecharge_WIDTH 1 -#define D18F2x190_EnDispAutoPrecharge_MASK 0x2000000 -#define D18F2x190_DbeSkidBufDis_OFFSET 26 -#define D18F2x190_DbeSkidBufDis_WIDTH 1 -#define D18F2x190_DbeSkidBufDis_MASK 0x4000000 -#define D18F2x190_DisDllShutdownSR_OFFSET 27 -#define D18F2x190_DisDllShutdownSR_WIDTH 1 -#define D18F2x190_DisDllShutdownSR_MASK 0x8000000 -#define D18F2x190_Reserved_28_28_OFFSET 28 -#define D18F2x190_Reserved_28_28_WIDTH 1 -#define D18F2x190_Reserved_28_28_MASK 0x10000000 -#define D18F2x190_Reserved_29_29_OFFSET 29 -#define D18F2x190_Reserved_29_29_WIDTH 1 -#define D18F2x190_Reserved_29_29_MASK 0x20000000 -#define D18F2x190_Reserved_31_30_OFFSET 30 -#define D18F2x190_Reserved_31_30_WIDTH 2 -#define D18F2x190_Reserved_31_30_MASK 0xc0000000 - -/// D18F2x190 -typedef union { - struct { ///< - UINT32 Reserved_0_0:1 ; ///< - UINT32 ExitSelfRef:1 ; ///< - UINT32 Reserved_16_2:15; ///< - UINT32 EnterSelfRef:1 ; ///< - UINT32 Reserved_19_18:2 ; ///< - UINT32 DynPageCloseEn:1 ; ///< - UINT32 IdleCycInit:2 ; ///< - UINT32 ForceAutoPchg:1 ; ///< - UINT32 Reserved_24_24:1 ; ///< - UINT32 EnDispAutoPrecharge:1 ; ///< - UINT32 DbeSkidBufDis:1 ; ///< - UINT32 DisDllShutdownSR:1 ; ///< - UINT32 Reserved_28_28:1 ; ///< - UINT32 Reserved_29_29:1 ; ///< - UINT32 Reserved_31_30:2 ; ///< - } Field; ///< - UINT32 Value; ///< -} D18F2x190_STRUCT; - -// **** D18F2x194 Register Definition **** -// Address -#define D18F2x194_ADDRESS 0x194 - -// Type -#define D18F2x194_TYPE TYPE_D18F2 -// Field Data -#define D18F2x194_MemClkFreq_OFFSET 0 -#define D18F2x194_MemClkFreq_WIDTH 5 -#define D18F2x194_MemClkFreq_MASK 0x1f -#define D18F2x194_Reserved_6_5_OFFSET 5 -#define D18F2x194_Reserved_6_5_WIDTH 2 -#define D18F2x194_Reserved_6_5_MASK 0x60 -#define D18F2x194_MemClkFreqVal_OFFSET 7 -#define D18F2x194_MemClkFreqVal_WIDTH 1 -#define D18F2x194_MemClkFreqVal_MASK 0x80 -#define D18F2x194_Reserved_9_8_OFFSET 8 -#define D18F2x194_Reserved_9_8_WIDTH 2 -#define D18F2x194_Reserved_9_8_MASK 0x300 -#define D18F2x194_ZqcsInterval_OFFSET 10 -#define D18F2x194_ZqcsInterval_WIDTH 2 -#define D18F2x194_ZqcsInterval_MASK 0xc00 -#define D18F2x194_Reserved_13_12_OFFSET 12 -#define D18F2x194_Reserved_13_12_WIDTH 2 -#define D18F2x194_Reserved_13_12_MASK 0x3000 -#define D18F2x194_DisDramInterface_OFFSET 14 -#define D18F2x194_DisDramInterface_WIDTH 1 -#define D18F2x194_DisDramInterface_MASK 0x4000 -#define D18F2x194_PowerDownEn_OFFSET 15 -#define D18F2x194_PowerDownEn_WIDTH 1 -#define D18F2x194_PowerDownEn_MASK 0x8000 -#define D18F2x194_PowerDownMode_OFFSET 16 -#define D18F2x194_PowerDownMode_WIDTH 1 -#define D18F2x194_PowerDownMode_MASK 0x10000 -#define D18F2x194_Reserved_19_17_OFFSET 17 -#define D18F2x194_Reserved_19_17_WIDTH 3 -#define D18F2x194_Reserved_19_17_MASK 0xe0000 -#define D18F2x194_SlowAccessMode_OFFSET 20 -#define D18F2x194_SlowAccessMode_WIDTH 1 -#define D18F2x194_SlowAccessMode_MASK 0x100000 -#define D18F2x194_Reserved_21_21_OFFSET 21 -#define D18F2x194_Reserved_21_21_WIDTH 1 -#define D18F2x194_Reserved_21_21_MASK 0x200000 -#define D18F2x194_BankSwizzleMode_OFFSET 22 -#define D18F2x194_BankSwizzleMode_WIDTH 1 -#define D18F2x194_BankSwizzleMode_MASK 0x400000 -#define D18F2x194_ProcOdtDis_OFFSET 23 -#define D18F2x194_ProcOdtDis_WIDTH 1 -#define D18F2x194_ProcOdtDis_MASK 0x800000 -#define D18F2x194_DcqBypassMax_OFFSET 24 -#define D18F2x194_DcqBypassMax_WIDTH 4 -#define D18F2x194_DcqBypassMax_MASK 0xf000000 -#define D18F2x194_FourActWindow_OFFSET 28 -#define D18F2x194_FourActWindow_WIDTH 4 -#define D18F2x194_FourActWindow_MASK 0xf0000000 - -/// D18F2x194 -typedef union { - struct { ///< - UINT32 MemClkFreq:5 ; ///< - UINT32 Reserved_6_5:2 ; ///< - UINT32 MemClkFreqVal:1 ; ///< - UINT32 Reserved_9_8:2 ; ///< - UINT32 ZqcsInterval:2 ; ///< - UINT32 Reserved_13_12:2 ; ///< - UINT32 DisDramInterface:1 ; ///< - UINT32 PowerDownEn:1 ; ///< - UINT32 PowerDownMode:1 ; ///< - UINT32 Reserved_19_17:3 ; ///< - UINT32 SlowAccessMode:1 ; ///< - UINT32 Reserved_21_21:1 ; ///< - UINT32 BankSwizzleMode:1 ; ///< - UINT32 ProcOdtDis:1 ; ///< - UINT32 DcqBypassMax:4 ; ///< - UINT32 FourActWindow:4 ; ///< - } Field; ///< - UINT32 Value; ///< -} D18F2x194_STRUCT; - -// **** D18F2x198 Register Definition **** -// Address -#define D18F2x198_ADDRESS 0x198 - -// Type -#define D18F2x198_TYPE TYPE_D18F2 -// Field Data -#define D18F2x198_DctOffset_OFFSET 0 -#define D18F2x198_DctOffset_WIDTH 30 -#define D18F2x198_DctOffset_MASK 0x3fffffff -#define D18F2x198_DctAccessWrite_OFFSET 30 -#define D18F2x198_DctAccessWrite_WIDTH 1 -#define D18F2x198_DctAccessWrite_MASK 0x40000000 -#define D18F2x198_Reserved_31_31_OFFSET 31 -#define D18F2x198_Reserved_31_31_WIDTH 1 -#define D18F2x198_Reserved_31_31_MASK 0x80000000 - -/// D18F2x198 -typedef union { - struct { ///< - UINT32 DctOffset:30; ///< - UINT32 DctAccessWrite:1 ; ///< - UINT32 Reserved_31_31:1 ; ///< - } Field; ///< - UINT32 Value; ///< -} D18F2x198_STRUCT; - -// **** D18F2x19C Register Definition **** -// Address -#define D18F2x19C_ADDRESS 0x19c - -// Type -#define D18F2x19C_TYPE TYPE_D18F2 -// Field Data -#define D18F2x19C_DctDataPort_OFFSET 0 -#define D18F2x19C_DctDataPort_WIDTH 32 -#define D18F2x19C_DctDataPort_MASK 0xffffffff - -/// D18F2x19C -typedef union { - struct { ///< - UINT32 DctDataPort:32; ///< - } Field; ///< - UINT32 Value; ///< -} D18F2x19C_STRUCT; - -// **** D18F2x1A0 Register Definition **** -// Address -#define D18F2x1A0_ADDRESS 0x1a0 - -// Type -#define D18F2x1A0_TYPE TYPE_D18F2 -// Field Data -#define D18F2x1A0_Reserved_31_0_OFFSET 0 -#define D18F2x1A0_Reserved_31_0_WIDTH 32 -#define D18F2x1A0_Reserved_31_0_MASK 0xffffffff - -/// D18F2x1A0 -typedef union { - struct { ///< - UINT32 Reserved_31_0:32; ///< - } Field; ///< - UINT32 Value; ///< -} D18F2x1A0_STRUCT; - -// **** D18F2x1A8 Register Definition **** -// Address -#define D18F2x1A8_ADDRESS 0x1a8 - -// Type -#define D18F2x1A8_TYPE TYPE_D18F2 -// Field Data -#define D18F2x1A8_Reserved_19_0_OFFSET 0 -#define D18F2x1A8_Reserved_19_0_WIDTH 20 -#define D18F2x1A8_Reserved_19_0_MASK 0xfffff -#define D18F2x1A8_BankSwap_OFFSET 20 -#define D18F2x1A8_BankSwap_WIDTH 1 -#define D18F2x1A8_BankSwap_MASK 0x100000 -#define D18F2x1A8_DbeGskMemClkAlignMode_OFFSET 21 -#define D18F2x1A8_DbeGskMemClkAlignMode_WIDTH 2 -#define D18F2x1A8_DbeGskMemClkAlignMode_MASK 0x600000 -#define D18F2x1A8_Reserved_31_23_OFFSET 23 -#define D18F2x1A8_Reserved_31_23_WIDTH 9 -#define D18F2x1A8_Reserved_31_23_MASK 0xff800000 - -/// D18F2x1A8 -typedef union { - struct { ///< - UINT32 Reserved_19_0:20; ///< - UINT32 BankSwap:1 ; ///< - UINT32 DbeGskMemClkAlignMode:2 ; ///< - UINT32 Reserved_31_23:9 ; ///< - } Field; ///< - UINT32 Value; ///< -} D18F2x1A8_STRUCT; - -// **** D18F2x1C0 Register Definition **** -// Address -#define D18F2x1C0_ADDRESS 0x1c0 - -// Type -#define D18F2x1C0_TYPE TYPE_D18F2 -// Field Data -#define D18F2x1C0_WrDramTrainMode_OFFSET 0 -#define D18F2x1C0_WrDramTrainMode_WIDTH 1 -#define D18F2x1C0_WrDramTrainMode_MASK 0x1 -#define D18F2x1C0_WrTrainGo_OFFSET 1 -#define D18F2x1C0_WrTrainGo_WIDTH 1 -#define D18F2x1C0_WrTrainGo_MASK 0x2 -#define D18F2x1C0_TrainLength_OFFSET 2 -#define D18F2x1C0_TrainLength_WIDTH 16 -#define D18F2x1C0_TrainLength_MASK 0x3fffc -#define D18F2x1C0_Reserved_19_18_OFFSET 18 -#define D18F2x1C0_Reserved_19_18_WIDTH 2 -#define D18F2x1C0_Reserved_19_18_MASK 0xc0000 -#define D18F2x1C0_DramTrainPdbDis_OFFSET 20 -#define D18F2x1C0_DramTrainPdbDis_WIDTH 1 -#define D18F2x1C0_DramTrainPdbDis_MASK 0x100000 -#define D18F2x1C0_AltAddrEn_OFFSET 21 -#define D18F2x1C0_AltAddrEn_WIDTH 1 -#define D18F2x1C0_AltAddrEn_MASK 0x200000 -#define D18F2x1C0_RdDramTrainMode_OFFSET 22 -#define D18F2x1C0_RdDramTrainMode_WIDTH 1 -#define D18F2x1C0_RdDramTrainMode_MASK 0x400000 -#define D18F2x1C0_RdTrainGo_OFFSET 23 -#define D18F2x1C0_RdTrainGo_WIDTH 1 -#define D18F2x1C0_RdTrainGo_MASK 0x800000 -#define D18F2x1C0_Reserved_31_24_OFFSET 24 -#define D18F2x1C0_Reserved_31_24_WIDTH 8 -#define D18F2x1C0_Reserved_31_24_MASK 0xff000000 - -/// D18F2x1C0 -typedef union { - struct { ///< - UINT32 WrDramTrainMode:1 ; ///< - UINT32 WrTrainGo:1 ; ///< - UINT32 TrainLength:16; ///< - UINT32 Reserved_19_18:2 ; ///< - UINT32 DramTrainPdbDis:1 ; ///< - UINT32 AltAddrEn:1 ; ///< - UINT32 RdDramTrainMode:1 ; ///< - UINT32 RdTrainGo:1 ; ///< - UINT32 Reserved_31_24:8 ; ///< - } Field; ///< - UINT32 Value; ///< -} D18F2x1C0_STRUCT; - -// **** D18F2x1C8 Register Definition **** -// Address -#define D18F2x1C8_ADDRESS 0x1c8 - -// Type -#define D18F2x1C8_TYPE TYPE_D18F2 -// Field Data -#define D18F2x1C8_TrainAddrPtr_37_6__OFFSET 0 -#define D18F2x1C8_TrainAddrPtr_37_6__WIDTH 32 -#define D18F2x1C8_TrainAddrPtr_37_6__MASK 0xffffffff - -/// D18F2x1C8 -typedef union { - struct { ///< - UINT32 TrainAddrPtr_37_6_:32; ///< - } Field; ///< - UINT32 Value; ///< -} D18F2x1C8_STRUCT; - -// **** D18F2x1CC Register Definition **** -// Address -#define D18F2x1CC_ADDRESS 0x1cc - -// Type -#define D18F2x1CC_TYPE TYPE_D18F2 -// Field Data -#define D18F2x1CC_AltAddr1Ptr_39_38__OFFSET 0 -#define D18F2x1CC_AltAddr1Ptr_39_38__WIDTH 2 -#define D18F2x1CC_AltAddr1Ptr_39_38__MASK 0x3 -#define D18F2x1CC_AltAddr1PtrIt_OFFSET 2 -#define D18F2x1CC_AltAddr1PtrIt_WIDTH 6 -#define D18F2x1CC_AltAddr1PtrIt_MASK 0xfc -#define D18F2x1CC_AltAddr2Ptr_39_38__OFFSET 8 -#define D18F2x1CC_AltAddr2Ptr_39_38__WIDTH 2 -#define D18F2x1CC_AltAddr2Ptr_39_38__MASK 0x300 -#define D18F2x1CC_AltAddr2PtrIt_OFFSET 10 -#define D18F2x1CC_AltAddr2PtrIt_WIDTH 6 -#define D18F2x1CC_AltAddr2PtrIt_MASK 0xfc00 -#define D18F2x1CC_TrainAddrPtr_39_38__OFFSET 16 -#define D18F2x1CC_TrainAddrPtr_39_38__WIDTH 2 -#define D18F2x1CC_TrainAddrPtr_39_38__MASK 0x30000 -#define D18F2x1CC_TrainAddrPtrIt_OFFSET 18 -#define D18F2x1CC_TrainAddrPtrIt_WIDTH 6 -#define D18F2x1CC_TrainAddrPtrIt_MASK 0xfc0000 -#define D18F2x1CC_AltAddr3Ptr_39_38__OFFSET 24 -#define D18F2x1CC_AltAddr3Ptr_39_38__WIDTH 2 -#define D18F2x1CC_AltAddr3Ptr_39_38__MASK 0x3000000 -#define D18F2x1CC_AltAddr3PtrIt_OFFSET 26 -#define D18F2x1CC_AltAddr3PtrIt_WIDTH 6 -#define D18F2x1CC_AltAddr3PtrIt_MASK 0xfc000000 - -/// D18F2x1CC -typedef union { - struct { ///< - UINT32 AltAddr1Ptr_39_38_:2 ; ///< - UINT32 AltAddr1PtrIt:6 ; ///< - UINT32 AltAddr2Ptr_39_38_:2 ; ///< - UINT32 AltAddr2PtrIt:6 ; ///< - UINT32 TrainAddrPtr_39_38_:2 ; ///< - UINT32 TrainAddrPtrIt:6 ; ///< - UINT32 AltAddr3Ptr_39_38_:2 ; ///< - UINT32 AltAddr3PtrIt:6 ; ///< - } Field; ///< - UINT32 Value; ///< -} D18F2x1CC_STRUCT; - -// **** D18F2x1D0 Register Definition **** -// Address -#define D18F2x1D0_ADDRESS 0x1d0 - -// Type -#define D18F2x1D0_TYPE TYPE_D18F2 -// Field Data -#define D18F2x1D0_WrTrainBufAddr_OFFSET 0 -#define D18F2x1D0_WrTrainBufAddr_WIDTH 10 -#define D18F2x1D0_WrTrainBufAddr_MASK 0x3ff -#define D18F2x1D0_Reserved_31_10_OFFSET 10 -#define D18F2x1D0_Reserved_31_10_WIDTH 22 -#define D18F2x1D0_Reserved_31_10_MASK 0xfffffc00 - -/// D18F2x1D0 -typedef union { - struct { ///< - UINT32 WrTrainBufAddr:10; ///< - UINT32 Reserved_31_10:22; ///< - } Field; ///< - UINT32 Value; ///< -} D18F2x1D0_STRUCT; - -// **** D18F2x1D4 Register Definition **** -// Address -#define D18F2x1D4_ADDRESS 0x1d4 - -// Type -#define D18F2x1D4_TYPE TYPE_D18F2 -// Field Data -#define D18F2x1D4_WrTrainBufDat_OFFSET 0 -#define D18F2x1D4_WrTrainBufDat_WIDTH 32 -#define D18F2x1D4_WrTrainBufDat_MASK 0xffffffff - -/// D18F2x1D4 -typedef union { - struct { ///< - UINT32 WrTrainBufDat:32; ///< - } Field; ///< - UINT32 Value; ///< -} D18F2x1D4_STRUCT; - -// **** D18F2x1D8 Register Definition **** -// Address -#define D18F2x1D8_ADDRESS 0x1d8 - -// Type -#define D18F2x1D8_TYPE TYPE_D18F2 -// Field Data -#define D18F2x1D8_AltAddrPtr_37_6__OFFSET 0 -#define D18F2x1D8_AltAddrPtr_37_6__WIDTH 32 -#define D18F2x1D8_AltAddrPtr_37_6__MASK 0xffffffff - -/// D18F2x1D8 -typedef union { - struct { ///< - UINT32 AltAddrPtr_37_6_:32; ///< - } Field; ///< - UINT32 Value; ///< -} D18F2x1D8_STRUCT; - -// **** D18F2x1DC Register Definition **** -// Address -#define D18F2x1DC_ADDRESS 0x1dc - -// Type -#define D18F2x1DC_TYPE TYPE_D18F2 -// Field Data -#define D18F2x1DC_AltAddrPtr_37_6__OFFSET 0 -#define D18F2x1DC_AltAddrPtr_37_6__WIDTH 32 -#define D18F2x1DC_AltAddrPtr_37_6__MASK 0xffffffff - -/// D18F2x1DC -typedef union { - struct { ///< - UINT32 AltAddrPtr_37_6_:32; ///< - } Field; ///< - UINT32 Value; ///< -} D18F2x1DC_STRUCT; - -// **** D18F2x1E0 Register Definition **** -// Address -#define D18F2x1E0_ADDRESS 0x1e0 - -// Type -#define D18F2x1E0_TYPE TYPE_D18F2 -// Field Data -#define D18F2x1E0_AltAddrPtr_37_6__OFFSET 0 -#define D18F2x1E0_AltAddrPtr_37_6__WIDTH 32 -#define D18F2x1E0_AltAddrPtr_37_6__MASK 0xffffffff - -/// D18F2x1E0 -typedef union { - struct { ///< - UINT32 AltAddrPtr_37_6_:32; ///< - } Field; ///< - UINT32 Value; ///< -} D18F2x1E0_STRUCT; - -// **** D18F2x1E8 Register Definition **** -// Address -#define D18F2x1E8_ADDRESS 0x1e8 - -// Type -#define D18F2x1E8_TYPE TYPE_D18F2 -// Field Data -#define D18F2x1E8_TrainCmpSts_OFFSET 0 -#define D18F2x1E8_TrainCmpSts_WIDTH 8 -#define D18F2x1E8_TrainCmpSts_MASK 0xff -#define D18F2x1E8_TrainCmpSts2_OFFSET 8 -#define D18F2x1E8_TrainCmpSts2_WIDTH 8 -#define D18F2x1E8_TrainCmpSts2_MASK 0xff00 -#define D18F2x1E8_Reserved_31_16_OFFSET 16 -#define D18F2x1E8_Reserved_31_16_WIDTH 16 -#define D18F2x1E8_Reserved_31_16_MASK 0xffff0000 - -/// D18F2x1E8 -typedef union { - struct { ///< - UINT32 TrainCmpSts:8 ; ///< - UINT32 TrainCmpSts2:8 ; ///< - UINT32 Reserved_31_16:16; ///< - } Field; ///< - UINT32 Value; ///< -} D18F2x1E8_STRUCT; - -// **** D18F2x1F0 Register Definition **** -// Address -#define D18F2x1F0_ADDRESS 0x1f0 - -// Type -#define D18F2x1F0_TYPE TYPE_D18F2 -// Field Data -#define D18F2x1F0_DctOffset_OFFSET 0 -#define D18F2x1F0_DctOffset_WIDTH 28 -#define D18F2x1F0_DctOffset_MASK 0xfffffff -#define D18F2x1F0_Reserved_29_28_OFFSET 28 -#define D18F2x1F0_Reserved_29_28_WIDTH 2 -#define D18F2x1F0_Reserved_29_28_MASK 0x30000000 -#define D18F2x1F0_DctAccessWrite_OFFSET 30 -#define D18F2x1F0_DctAccessWrite_WIDTH 1 -#define D18F2x1F0_DctAccessWrite_MASK 0x40000000 -#define D18F2x1F0_DctAccessDone_OFFSET 31 -#define D18F2x1F0_DctAccessDone_WIDTH 1 -#define D18F2x1F0_DctAccessDone_MASK 0x80000000 - -/// D18F2x1F0 -typedef union { - struct { ///< - UINT32 DctOffset:28; ///< - UINT32 Reserved_29_28:2 ; ///< - UINT32 DctAccessWrite:1 ; ///< - UINT32 DctAccessDone:1 ; ///< - } Field; ///< - UINT32 Value; ///< -} D18F2x1F0_STRUCT; - -// **** D18F2x1F4 Register Definition **** -// Address -#define D18F2x1F4_ADDRESS 0x1f4 - -// Type -#define D18F2x1F4_TYPE TYPE_D18F2 -// Field Data -#define D18F2x1F4_DctExtDataPort_OFFSET 0 -#define D18F2x1F4_DctExtDataPort_WIDTH 32 -#define D18F2x1F4_DctExtDataPort_MASK 0xffffffff - -/// D18F2x1F4 -typedef union { - struct { ///< - UINT32 DctExtDataPort:32; ///< - } Field; ///< - UINT32 Value; ///< -} D18F2x1F4_STRUCT; - -// **** D18F3x00 Register Definition **** -// Address -#define D18F3x00_ADDRESS 0x0 - -// Type -#define D18F3x00_TYPE TYPE_D18F3 -// Field Data -#define D18F3x00_VendorID_OFFSET 0 -#define D18F3x00_VendorID_WIDTH 16 -#define D18F3x00_VendorID_MASK 0xffff -#define D18F3x00_DeviceID_OFFSET 16 -#define D18F3x00_DeviceID_WIDTH 16 -#define D18F3x00_DeviceID_MASK 0xffff0000 - -/// D18F3x00 -typedef union { - struct { ///< - UINT32 VendorID:16; ///< - UINT32 DeviceID:16; ///< - } Field; ///< - UINT32 Value; ///< -} D18F3x00_STRUCT; - -// **** D18F3x04 Register Definition **** -// Address -#define D18F3x04_ADDRESS 0x4 - -// Type -#define D18F3x04_TYPE TYPE_D18F3 -// Field Data -#define D18F3x04_Command_OFFSET 0 -#define D18F3x04_Command_WIDTH 16 -#define D18F3x04_Command_MASK 0xffff -#define D18F3x04_Status_OFFSET 16 -#define D18F3x04_Status_WIDTH 16 -#define D18F3x04_Status_MASK 0xffff0000 - -/// D18F3x04 -typedef union { - struct { ///< - UINT32 Command:16; ///< - UINT32 Status:16; ///< - } Field; ///< - UINT32 Value; ///< -} D18F3x04_STRUCT; - -// **** D18F3x08 Register Definition **** -// Address -#define D18F3x08_ADDRESS 0x8 - -// Type -#define D18F3x08_TYPE TYPE_D18F3 -// Field Data -#define D18F3x08_RevID_OFFSET 0 -#define D18F3x08_RevID_WIDTH 8 -#define D18F3x08_RevID_MASK 0xff -#define D18F3x08_ClassCode_OFFSET 8 -#define D18F3x08_ClassCode_WIDTH 24 -#define D18F3x08_ClassCode_MASK 0xffffff00 - -/// D18F3x08 -typedef union { - struct { ///< - UINT32 RevID:8 ; ///< - UINT32 ClassCode:24; ///< - } Field; ///< - UINT32 Value; ///< -} D18F3x08_STRUCT; - -// **** D18F3x0C Register Definition **** -// Address -#define D18F3x0C_ADDRESS 0xc - -// Type -#define D18F3x0C_TYPE TYPE_D18F3 -// Field Data -#define D18F3x0C_HeaderTypeReg_OFFSET 0 -#define D18F3x0C_HeaderTypeReg_WIDTH 32 -#define D18F3x0C_HeaderTypeReg_MASK 0xffffffff - -/// D18F3x0C -typedef union { - struct { ///< - UINT32 HeaderTypeReg:32; ///< - } Field; ///< - UINT32 Value; ///< -} D18F3x0C_STRUCT; - -// **** D18F3x34 Register Definition **** -// Address -#define D18F3x34_ADDRESS 0x34 - -// Type -#define D18F3x34_TYPE TYPE_D18F3 -// Field Data -#define D18F3x34_CapPtr_OFFSET 0 -#define D18F3x34_CapPtr_WIDTH 8 -#define D18F3x34_CapPtr_MASK 0xff -#define D18F3x34_Reserved_31_8_OFFSET 8 -#define D18F3x34_Reserved_31_8_WIDTH 24 -#define D18F3x34_Reserved_31_8_MASK 0xffffff00 - -/// D18F3x34 -typedef union { - struct { ///< - UINT32 CapPtr:8 ; ///< - UINT32 Reserved_31_8:24; ///< - } Field; ///< - UINT32 Value; ///< -} D18F3x34_STRUCT; - -// **** D18F3x40 Register Definition **** -// Address -#define D18F3x40_ADDRESS 0x40 - -// Type -#define D18F3x40_TYPE TYPE_D18F3 -// Field Data -#define D18F3x40_Reserved_4_0_OFFSET 0 -#define D18F3x40_Reserved_4_0_WIDTH 5 -#define D18F3x40_Reserved_4_0_MASK 0x1f -#define D18F3x40_SyncFloodEn_OFFSET 5 -#define D18F3x40_SyncFloodEn_WIDTH 1 -#define D18F3x40_SyncFloodEn_MASK 0x20 -#define D18F3x40_Reserved_7_6_OFFSET 6 -#define D18F3x40_Reserved_7_6_WIDTH 2 -#define D18F3x40_Reserved_7_6_MASK 0xc0 -#define D18F3x40_MstrAbortEn_OFFSET 8 -#define D18F3x40_MstrAbortEn_WIDTH 1 -#define D18F3x40_MstrAbortEn_MASK 0x100 -#define D18F3x40_TgtAbortEn_OFFSET 9 -#define D18F3x40_TgtAbortEn_WIDTH 1 -#define D18F3x40_TgtAbortEn_MASK 0x200 -#define D18F3x40_Reserved_10_10_OFFSET 10 -#define D18F3x40_Reserved_10_10_WIDTH 1 -#define D18F3x40_Reserved_10_10_MASK 0x400 -#define D18F3x40_AtomicRMWEn_OFFSET 11 -#define D18F3x40_AtomicRMWEn_WIDTH 1 -#define D18F3x40_AtomicRMWEn_MASK 0x800 -#define D18F3x40_WDTRptEn_OFFSET 12 -#define D18F3x40_WDTRptEn_WIDTH 1 -#define D18F3x40_WDTRptEn_MASK 0x1000 -#define D18F3x40_DevErrEn_OFFSET 13 -#define D18F3x40_DevErrEn_WIDTH 1 -#define D18F3x40_DevErrEn_MASK 0x2000 -#define D18F3x40_Reserved_15_14_OFFSET 14 -#define D18F3x40_Reserved_15_14_WIDTH 2 -#define D18F3x40_Reserved_15_14_MASK 0xc000 -#define D18F3x40_ProtEn_OFFSET 16 -#define D18F3x40_ProtEn_WIDTH 1 -#define D18F3x40_ProtEn_MASK 0x10000 -#define D18F3x40_DataEn_OFFSET 17 -#define D18F3x40_DataEn_WIDTH 1 -#define D18F3x40_DataEn_MASK 0x20000 -#define D18F3x40_Reserved_24_18_OFFSET 18 -#define D18F3x40_Reserved_24_18_WIDTH 7 -#define D18F3x40_Reserved_24_18_MASK 0x1fc0000 -#define D18F3x40_McaUsPwDatErrEn_OFFSET 25 -#define D18F3x40_McaUsPwDatErrEn_WIDTH 1 -#define D18F3x40_McaUsPwDatErrEn_MASK 0x2000000 -#define D18F3x40_Reserved_31_26_OFFSET 26 -#define D18F3x40_Reserved_31_26_WIDTH 6 -#define D18F3x40_Reserved_31_26_MASK 0xfc000000 - -/// D18F3x40 -typedef union { - struct { ///< - UINT32 Reserved_4_0:5 ; ///< - UINT32 SyncFloodEn:1 ; ///< - UINT32 Reserved_7_6:2 ; ///< - UINT32 MstrAbortEn:1 ; ///< - UINT32 TgtAbortEn:1 ; ///< - UINT32 Reserved_10_10:1 ; ///< - UINT32 AtomicRMWEn:1 ; ///< - UINT32 WDTRptEn:1 ; ///< - UINT32 DevErrEn:1 ; ///< - UINT32 Reserved_15_14:2 ; ///< - UINT32 ProtEn:1 ; ///< - UINT32 DataEn:1 ; ///< - UINT32 Reserved_24_18:7 ; ///< - UINT32 McaUsPwDatErrEn:1 ; ///< - UINT32 Reserved_31_26:6 ; ///< - } Field; ///< - UINT32 Value; ///< -} D18F3x40_STRUCT; - -// **** D18F3x44 Register Definition **** -// Address -#define D18F3x44_ADDRESS 0x44 - -// Type -#define D18F3x44_TYPE TYPE_D18F3 -// Field Data -#define D18F3x44_Reserved_0_0_OFFSET 0 -#define D18F3x44_Reserved_0_0_WIDTH 1 -#define D18F3x44_Reserved_0_0_MASK 0x1 -#define D18F3x44_CpuRdDatErrEn_OFFSET 1 -#define D18F3x44_CpuRdDatErrEn_WIDTH 1 -#define D18F3x44_CpuRdDatErrEn_MASK 0x2 -#define D18F3x44_Reserved_2_2_OFFSET 2 -#define D18F3x44_Reserved_2_2_WIDTH 1 -#define D18F3x44_Reserved_2_2_MASK 0x4 -#define D18F3x44_Reserved_4_3_OFFSET 3 -#define D18F3x44_Reserved_4_3_WIDTH 2 -#define D18F3x44_Reserved_4_3_MASK 0x18 -#define D18F3x44_IoMstAbortDis_OFFSET 5 -#define D18F3x44_IoMstAbortDis_WIDTH 1 -#define D18F3x44_IoMstAbortDis_MASK 0x20 -#define D18F3x44_CpuErrDis_OFFSET 6 -#define D18F3x44_CpuErrDis_WIDTH 1 -#define D18F3x44_CpuErrDis_MASK 0x40 -#define D18F3x44_IoErrDis_OFFSET 7 -#define D18F3x44_IoErrDis_WIDTH 1 -#define D18F3x44_IoErrDis_MASK 0x80 -#define D18F3x44_WDTDis_OFFSET 8 -#define D18F3x44_WDTDis_WIDTH 1 -#define D18F3x44_WDTDis_MASK 0x100 -#define D18F3x44_WDTCntSel_2_0__OFFSET 9 -#define D18F3x44_WDTCntSel_2_0__WIDTH 3 -#define D18F3x44_WDTCntSel_2_0__MASK 0xe00 -#define D18F3x44_WDTBaseSel_OFFSET 12 -#define D18F3x44_WDTBaseSel_WIDTH 2 -#define D18F3x44_WDTBaseSel_MASK 0x3000 -#define D18F3x44_Reserved_19_14_OFFSET 14 -#define D18F3x44_Reserved_19_14_WIDTH 6 -#define D18F3x44_Reserved_19_14_MASK 0xfc000 -#define D18F3x44_SyncOnWDTEn_OFFSET 20 -#define D18F3x44_SyncOnWDTEn_WIDTH 1 -#define D18F3x44_SyncOnWDTEn_MASK 0x100000 -#define D18F3x44_SyncOnAnyErrEn_OFFSET 21 -#define D18F3x44_SyncOnAnyErrEn_WIDTH 1 -#define D18F3x44_SyncOnAnyErrEn_MASK 0x200000 -#define D18F3x44_Reserved_23_22_OFFSET 22 -#define D18F3x44_Reserved_23_22_WIDTH 2 -#define D18F3x44_Reserved_23_22_MASK 0xc00000 -#define D18F3x44_IoRdDatErrEn_OFFSET 24 -#define D18F3x44_IoRdDatErrEn_WIDTH 1 -#define D18F3x44_IoRdDatErrEn_MASK 0x1000000 -#define D18F3x44_DisPciCfgCpuErrRsp_OFFSET 25 -#define D18F3x44_DisPciCfgCpuErrRsp_WIDTH 1 -#define D18F3x44_DisPciCfgCpuErrRsp_MASK 0x2000000 -#define D18F3x44_CorrMcaExcEn_OFFSET 26 -#define D18F3x44_CorrMcaExcEn_WIDTH 1 -#define D18F3x44_CorrMcaExcEn_MASK 0x4000000 -#define D18F3x44_NbMcaToMstCpuEn_OFFSET 27 -#define D18F3x44_NbMcaToMstCpuEn_WIDTH 1 -#define D18F3x44_NbMcaToMstCpuEn_MASK 0x8000000 -#define D18F3x44_DisTgtAbtCpuErrRsp_OFFSET 28 -#define D18F3x44_DisTgtAbtCpuErrRsp_WIDTH 1 -#define D18F3x44_DisTgtAbtCpuErrRsp_MASK 0x10000000 -#define D18F3x44_DisMstAbtCpuErrRsp_OFFSET 29 -#define D18F3x44_DisMstAbtCpuErrRsp_WIDTH 1 -#define D18F3x44_DisMstAbtCpuErrRsp_MASK 0x20000000 -#define D18F3x44_Reserved_30_30_OFFSET 30 -#define D18F3x44_Reserved_30_30_WIDTH 1 -#define D18F3x44_Reserved_30_30_MASK 0x40000000 -#define D18F3x44_NbMcaLogEn_OFFSET 31 -#define D18F3x44_NbMcaLogEn_WIDTH 1 -#define D18F3x44_NbMcaLogEn_MASK 0x80000000 - -/// D18F3x44 -typedef union { - struct { ///< - UINT32 Reserved_0_0:1 ; ///< - UINT32 CpuRdDatErrEn:1 ; ///< - UINT32 Reserved_2_2:1 ; ///< - UINT32 Reserved_4_3:2 ; ///< - UINT32 IoMstAbortDis:1 ; ///< - UINT32 CpuErrDis:1 ; ///< - UINT32 IoErrDis:1 ; ///< - UINT32 WDTDis:1 ; ///< - UINT32 WDTCntSel_2_0_:3 ; ///< - UINT32 WDTBaseSel:2 ; ///< - UINT32 Reserved_19_14:6 ; ///< - UINT32 SyncOnWDTEn:1 ; ///< - UINT32 SyncOnAnyErrEn:1 ; ///< - UINT32 Reserved_23_22:2 ; ///< - UINT32 IoRdDatErrEn:1 ; ///< - UINT32 DisPciCfgCpuErrRsp:1 ; ///< - UINT32 CorrMcaExcEn:1 ; ///< - UINT32 NbMcaToMstCpuEn:1 ; ///< - UINT32 DisTgtAbtCpuErrRsp:1 ; ///< - UINT32 DisMstAbtCpuErrRsp:1 ; ///< - UINT32 Reserved_30_30:1 ; ///< - UINT32 NbMcaLogEn:1 ; ///< - } Field; ///< - UINT32 Value; ///< -} D18F3x44_STRUCT; - -// **** D18F3x48 Register Definition **** -// Address -#define D18F3x48_ADDRESS 0x48 - -// Type -#define D18F3x48_TYPE TYPE_D18F3 -// Field Data -#define D18F3x48_ErrorCode_OFFSET 0 -#define D18F3x48_ErrorCode_WIDTH 16 -#define D18F3x48_ErrorCode_MASK 0xffff -#define D18F3x48_ErrorCodeExt_OFFSET 16 -#define D18F3x48_ErrorCodeExt_WIDTH 5 -#define D18F3x48_ErrorCodeExt_MASK 0x1f0000 -#define D18F3x48_Reserved_31_21_OFFSET 21 -#define D18F3x48_Reserved_31_21_WIDTH 11 -#define D18F3x48_Reserved_31_21_MASK 0xffe00000 - -/// D18F3x48 -typedef union { - struct { ///< - UINT32 ErrorCode:16; ///< - UINT32 ErrorCodeExt:5 ; ///< - UINT32 Reserved_31_21:11; ///< - } Field; ///< - UINT32 Value; ///< -} D18F3x48_STRUCT; - -// **** D18F3x4C Register Definition **** -// Address -#define D18F3x4C_ADDRESS 0x4c - -// Type -#define D18F3x4C_TYPE TYPE_D18F3 -// Field Data -#define D18F3x4C_ErrCPU_OFFSET 0 -#define D18F3x4C_ErrCPU_WIDTH 4 -#define D18F3x4C_ErrCPU_MASK 0xf -#define D18F3x4C_BusErr_OFFSET 4 -#define D18F3x4C_BusErr_WIDTH 1 -#define D18F3x4C_BusErr_MASK 0x10 -#define D18F3x4C_Reserved_24_5_OFFSET 5 -#define D18F3x4C_Reserved_24_5_WIDTH 20 -#define D18F3x4C_Reserved_24_5_MASK 0x1ffffe0 -#define D18F3x4C_PCC_OFFSET 25 -#define D18F3x4C_PCC_WIDTH 1 -#define D18F3x4C_PCC_MASK 0x2000000 -#define D18F3x4C_AddrV_OFFSET 26 -#define D18F3x4C_AddrV_WIDTH 1 -#define D18F3x4C_AddrV_MASK 0x4000000 -#define D18F3x4C_Reserved_27_27_OFFSET 27 -#define D18F3x4C_Reserved_27_27_WIDTH 1 -#define D18F3x4C_Reserved_27_27_MASK 0x8000000 -#define D18F3x4C_En_OFFSET 28 -#define D18F3x4C_En_WIDTH 1 -#define D18F3x4C_En_MASK 0x10000000 -#define D18F3x4C_UC_OFFSET 29 -#define D18F3x4C_UC_WIDTH 1 -#define D18F3x4C_UC_MASK 0x20000000 -#define D18F3x4C_Over_OFFSET 30 -#define D18F3x4C_Over_WIDTH 1 -#define D18F3x4C_Over_MASK 0x40000000 -#define D18F3x4C_Val_OFFSET 31 -#define D18F3x4C_Val_WIDTH 1 -#define D18F3x4C_Val_MASK 0x80000000 - -/// D18F3x4C -typedef union { - struct { ///< - UINT32 ErrCPU:4 ; ///< - UINT32 BusErr:1 ; ///< - UINT32 Reserved_24_5:20; ///< - UINT32 PCC:1 ; ///< - UINT32 AddrV:1 ; ///< - UINT32 Reserved_27_27:1 ; ///< - UINT32 En:1 ; ///< - UINT32 UC:1 ; ///< - UINT32 Over:1 ; ///< - UINT32 Val:1 ; ///< - } Field; ///< - UINT32 Value; ///< -} D18F3x4C_STRUCT; - -// **** D18F3x50 Register Definition **** -// Address -#define D18F3x50_ADDRESS 0x50 - -// Type -#define D18F3x50_TYPE TYPE_D18F3 -// Field Data -#define D18F3x50_ErrorAddr_31_0__OFFSET 0 -#define D18F3x50_ErrorAddr_31_0__WIDTH 32 -#define D18F3x50_ErrorAddr_31_0__MASK 0xffffffff - -/// D18F3x50 -typedef union { - struct { ///< - UINT32 ErrorAddr_31_0_:32; ///< - } Field; ///< - UINT32 Value; ///< -} D18F3x50_STRUCT; - -// **** D18F3x54 Register Definition **** -// Address -#define D18F3x54_ADDRESS 0x54 - -// Type -#define D18F3x54_TYPE TYPE_D18F3 -// Field Data -#define D18F3x54_ErrorAddr_39_32__OFFSET 0 -#define D18F3x54_ErrorAddr_39_32__WIDTH 8 -#define D18F3x54_ErrorAddr_39_32__MASK 0xff -#define D18F3x54_Reserved_31_8_OFFSET 8 -#define D18F3x54_Reserved_31_8_WIDTH 24 -#define D18F3x54_Reserved_31_8_MASK 0xffffff00 - -/// D18F3x54 -typedef union { - struct { ///< - UINT32 ErrorAddr_39_32_:8 ; ///< - UINT32 Reserved_31_8:24; ///< - } Field; ///< - UINT32 Value; ///< -} D18F3x54_STRUCT; - -// **** D18F3x64 Register Definition **** -// Address -#define D18F3x64_ADDRESS 0x64 - -// Type -#define D18F3x64_TYPE TYPE_D18F3 -// Field Data -#define D18F3x64_HtcEn_OFFSET 0 -#define D18F3x64_HtcEn_WIDTH 1 -#define D18F3x64_HtcEn_MASK 0x1 -#define D18F3x64_Reserved_3_1_OFFSET 1 -#define D18F3x64_Reserved_3_1_WIDTH 3 -#define D18F3x64_Reserved_3_1_MASK 0xe -#define D18F3x64_HtcAct_OFFSET 4 -#define D18F3x64_HtcAct_WIDTH 1 -#define D18F3x64_HtcAct_MASK 0x10 -#define D18F3x64_HtcActSts_OFFSET 5 -#define D18F3x64_HtcActSts_WIDTH 1 -#define D18F3x64_HtcActSts_MASK 0x20 -#define D18F3x64_PslApicHiEn_OFFSET 6 -#define D18F3x64_PslApicHiEn_WIDTH 1 -#define D18F3x64_PslApicHiEn_MASK 0x40 -#define D18F3x64_PslApicLoEn_OFFSET 7 -#define D18F3x64_PslApicLoEn_WIDTH 1 -#define D18F3x64_PslApicLoEn_MASK 0x80 -#define D18F3x64_Reserved_15_8_OFFSET 8 -#define D18F3x64_Reserved_15_8_WIDTH 8 -#define D18F3x64_Reserved_15_8_MASK 0xff00 -#define D18F3x64_HtcTmpLmt_OFFSET 16 -#define D18F3x64_HtcTmpLmt_WIDTH 7 -#define D18F3x64_HtcTmpLmt_MASK 0x7f0000 -#define D18F3x64_HtcSlewSel_OFFSET 23 -#define D18F3x64_HtcSlewSel_WIDTH 1 -#define D18F3x64_HtcSlewSel_MASK 0x800000 -#define D18F3x64_HtcHystLmt_OFFSET 24 -#define D18F3x64_HtcHystLmt_WIDTH 4 -#define D18F3x64_HtcHystLmt_MASK 0xf000000 -#define D18F3x64_HtcPstateLimit_OFFSET 28 -#define D18F3x64_HtcPstateLimit_WIDTH 3 -#define D18F3x64_HtcPstateLimit_MASK 0x70000000 -#define D18F3x64_HtcLock_OFFSET 31 -#define D18F3x64_HtcLock_WIDTH 1 -#define D18F3x64_HtcLock_MASK 0x80000000 - -/// D18F3x64 -typedef union { - struct { ///< - UINT32 HtcEn:1 ; ///< - UINT32 Reserved_3_1:3 ; ///< - UINT32 HtcAct:1 ; ///< - UINT32 HtcActSts:1 ; ///< - UINT32 PslApicHiEn:1 ; ///< - UINT32 PslApicLoEn:1 ; ///< - UINT32 Reserved_15_8:8 ; ///< - UINT32 HtcTmpLmt:7 ; ///< - UINT32 HtcSlewSel:1 ; ///< - UINT32 HtcHystLmt:4 ; ///< - UINT32 HtcPstateLimit:3 ; ///< - UINT32 HtcLock:1 ; ///< - } Field; ///< - UINT32 Value; ///< -} D18F3x64_STRUCT; - -// **** D18F3x6C Register Definition **** -// Address -#define D18F3x6C_ADDRESS 0x6c - -// Type -#define D18F3x6C_TYPE TYPE_D18F3 -// Field Data -#define D18F3x6C_UpLoPreqDBC_OFFSET 0 -#define D18F3x6C_UpLoPreqDBC_WIDTH 4 -#define D18F3x6C_UpLoPreqDBC_MASK 0xf -#define D18F3x6C_UpLoNpreqDBC_OFFSET 4 -#define D18F3x6C_UpLoNpreqDBC_WIDTH 4 -#define D18F3x6C_UpLoNpreqDBC_MASK 0xf0 -#define D18F3x6C_UpLoRespDBC_OFFSET 8 -#define D18F3x6C_UpLoRespDBC_WIDTH 4 -#define D18F3x6C_UpLoRespDBC_MASK 0xf00 -#define D18F3x6C_Reserved_15_12_OFFSET 12 -#define D18F3x6C_Reserved_15_12_WIDTH 4 -#define D18F3x6C_Reserved_15_12_MASK 0xf000 -#define D18F3x6C_UpHiPreqDBC_OFFSET 16 -#define D18F3x6C_UpHiPreqDBC_WIDTH 4 -#define D18F3x6C_UpHiPreqDBC_MASK 0xf0000 -#define D18F3x6C_UpHiNpreqDBC_OFFSET 20 -#define D18F3x6C_UpHiNpreqDBC_WIDTH 4 -#define D18F3x6C_UpHiNpreqDBC_MASK 0xf00000 -#define D18F3x6C_UpHiRespDBC_OFFSET 24 -#define D18F3x6C_UpHiRespDBC_WIDTH 4 -#define D18F3x6C_UpHiRespDBC_MASK 0xf000000 -#define D18F3x6C_Reserved_31_28_OFFSET 28 -#define D18F3x6C_Reserved_31_28_WIDTH 4 -#define D18F3x6C_Reserved_31_28_MASK 0xf0000000 - -/// D18F3x6C -typedef union { - struct { ///< - UINT32 UpLoPreqDBC:4 ; ///< - UINT32 UpLoNpreqDBC:4 ; ///< - UINT32 UpLoRespDBC:4 ; ///< - UINT32 Reserved_15_12:4 ; ///< - UINT32 UpHiPreqDBC:4 ; ///< - UINT32 UpHiNpreqDBC:4 ; ///< - UINT32 UpHiRespDBC:4 ; ///< - UINT32 Reserved_31_28:4 ; ///< - } Field; ///< - UINT32 Value; ///< -} D18F3x6C_STRUCT; - -// **** D18F3x74 Register Definition **** -// Address -#define D18F3x74_ADDRESS 0x74 - -// Type -#define D18F3x74_TYPE TYPE_D18F3 -// Field Data -#define D18F3x74_UpLoPreqCBC_OFFSET 0 -#define D18F3x74_UpLoPreqCBC_WIDTH 4 -#define D18F3x74_UpLoPreqCBC_MASK 0xf -#define D18F3x74_UpLoNpreqCBC_OFFSET 4 -#define D18F3x74_UpLoNpreqCBC_WIDTH 4 -#define D18F3x74_UpLoNpreqCBC_MASK 0xf0 -#define D18F3x74_UpLoRespCBC_OFFSET 8 -#define D18F3x74_UpLoRespCBC_WIDTH 4 -#define D18F3x74_UpLoRespCBC_MASK 0xf00 -#define D18F3x74_Reserved_15_12_OFFSET 12 -#define D18F3x74_Reserved_15_12_WIDTH 4 -#define D18F3x74_Reserved_15_12_MASK 0xf000 -#define D18F3x74_UpHiPreqCBC_OFFSET 16 -#define D18F3x74_UpHiPreqCBC_WIDTH 4 -#define D18F3x74_UpHiPreqCBC_MASK 0xf0000 -#define D18F3x74_UpHiNpreqCBC_OFFSET 20 -#define D18F3x74_UpHiNpreqCBC_WIDTH 4 -#define D18F3x74_UpHiNpreqCBC_MASK 0xf00000 -#define D18F3x74_UpHiRespCBC_OFFSET 24 -#define D18F3x74_UpHiRespCBC_WIDTH 4 -#define D18F3x74_UpHiRespCBC_MASK 0xf000000 -#define D18F3x74_Reserved_31_28_OFFSET 28 -#define D18F3x74_Reserved_31_28_WIDTH 4 -#define D18F3x74_Reserved_31_28_MASK 0xf0000000 - -/// D18F3x74 -typedef union { - struct { ///< - UINT32 UpLoPreqCBC:4 ; ///< - UINT32 UpLoNpreqCBC:4 ; ///< - UINT32 UpLoRespCBC:4 ; ///< - UINT32 Reserved_15_12:4 ; ///< - UINT32 UpHiPreqCBC:4 ; ///< - UINT32 UpHiNpreqCBC:4 ; ///< - UINT32 UpHiRespCBC:4 ; ///< - UINT32 Reserved_31_28:4 ; ///< - } Field; ///< - UINT32 Value; ///< -} D18F3x74_STRUCT; - -// **** D18F3x7C Register Definition **** -// Address -#define D18F3x7C_ADDRESS 0x7c - -// Type -#define D18F3x7C_TYPE TYPE_D18F3 -// Field Data -#define D18F3x7C_CpuBC_OFFSET 0 -#define D18F3x7C_CpuBC_WIDTH 6 -#define D18F3x7C_CpuBC_MASK 0x3f -#define D18F3x7C_Reserved_7_6_OFFSET 6 -#define D18F3x7C_Reserved_7_6_WIDTH 2 -#define D18F3x7C_Reserved_7_6_MASK 0xc0 -#define D18F3x7C_LoPriPBC_OFFSET 8 -#define D18F3x7C_LoPriPBC_WIDTH 6 -#define D18F3x7C_LoPriPBC_MASK 0x3f00 -#define D18F3x7C_Reserved_15_14_OFFSET 14 -#define D18F3x7C_Reserved_15_14_WIDTH 2 -#define D18F3x7C_Reserved_15_14_MASK 0xc000 -#define D18F3x7C_LoPriNpBC_OFFSET 16 -#define D18F3x7C_LoPriNpBC_WIDTH 6 -#define D18F3x7C_LoPriNpBC_MASK 0x3f0000 -#define D18F3x7C_Reserved_23_22_OFFSET 22 -#define D18F3x7C_Reserved_23_22_WIDTH 2 -#define D18F3x7C_Reserved_23_22_MASK 0xc00000 -#define D18F3x7C_FreePoolBC_OFFSET 24 -#define D18F3x7C_FreePoolBC_WIDTH 6 -#define D18F3x7C_FreePoolBC_MASK 0x3f000000 -#define D18F3x7C_Reserved_31_30_OFFSET 30 -#define D18F3x7C_Reserved_31_30_WIDTH 2 -#define D18F3x7C_Reserved_31_30_MASK 0xc0000000 - -/// D18F3x7C -typedef union { - struct { ///< - UINT32 CpuBC:6 ; ///< - UINT32 Reserved_7_6:2 ; ///< - UINT32 LoPriPBC:6 ; ///< - UINT32 Reserved_15_14:2 ; ///< - UINT32 LoPriNpBC:6 ; ///< - UINT32 Reserved_23_22:2 ; ///< - UINT32 FreePoolBC:6 ; ///< - UINT32 Reserved_31_30:2 ; ///< - } Field; ///< - UINT32 Value; ///< -} D18F3x7C_STRUCT; - -// **** D18F3x80 Register Definition **** -// Address -#define D18F3x80_ADDRESS 0x80 - -// Type -#define D18F3x80_TYPE TYPE_D18F3 -// Field Data -#define D18F3x80_Reserved_31_0_OFFSET 0 -#define D18F3x80_Reserved_31_0_WIDTH 32 -#define D18F3x80_Reserved_31_0_MASK 0xffffffff - -/// D18F3x80 -typedef union { - struct { ///< - UINT32 Reserved_31_0:32; ///< - } Field; ///< - UINT32 Value; ///< -} D18F3x80_STRUCT; - -// **** D18F3x84 Register Definition **** -// Address -#define D18F3x84_ADDRESS 0x84 - -// Type -#define D18F3x84_TYPE TYPE_D18F3 -// Field Data -#define D18F3x84_Reserved_0_0_OFFSET 0 -#define D18F3x84_Reserved_0_0_WIDTH 1 -#define D18F3x84_Reserved_0_0_MASK 0x1 -#define D18F3x84_Smaf4DramSr_OFFSET 1 -#define D18F3x84_Smaf4DramSr_WIDTH 1 -#define D18F3x84_Smaf4DramSr_MASK 0x2 -#define D18F3x84_Smaf4DramMemClkTri_OFFSET 2 -#define D18F3x84_Smaf4DramMemClkTri_WIDTH 1 -#define D18F3x84_Smaf4DramMemClkTri_MASK 0x4 -#define D18F3x84_Reserved_16_3_OFFSET 3 -#define D18F3x84_Reserved_16_3_WIDTH 14 -#define D18F3x84_Reserved_16_3_MASK 0x1fff8 -#define D18F3x84_Smaf6DramSr_OFFSET 17 -#define D18F3x84_Smaf6DramSr_WIDTH 1 -#define D18F3x84_Smaf6DramSr_MASK 0x20000 -#define D18F3x84_Smaf6DramMemClkTri_OFFSET 18 -#define D18F3x84_Smaf6DramMemClkTri_WIDTH 1 -#define D18F3x84_Smaf6DramMemClkTri_MASK 0x40000 -#define D18F3x84_Reserved_31_19_OFFSET 19 -#define D18F3x84_Reserved_31_19_WIDTH 13 -#define D18F3x84_Reserved_31_19_MASK 0xfff80000 - -/// D18F3x84 -typedef union { - struct { ///< - UINT32 Reserved_0_0:1 ; ///< - UINT32 Smaf4DramSr:1 ; ///< - UINT32 Smaf4DramMemClkTri:1 ; ///< - UINT32 Reserved_16_3:14; ///< - UINT32 Smaf6DramSr:1 ; ///< - UINT32 Smaf6DramMemClkTri:1 ; ///< - UINT32 Reserved_31_19:13; ///< - } Field; ///< - UINT32 Value; ///< -} D18F3x84_STRUCT; - -// **** D18F3x88 Register Definition **** -// Address -#define D18F3x88_ADDRESS 0x88 - -// Type -#define D18F3x88_TYPE TYPE_D18F3 -// Field Data -#define D18F3x88_Reserved_31_0_OFFSET 0 -#define D18F3x88_Reserved_31_0_WIDTH 32 -#define D18F3x88_Reserved_31_0_MASK 0xffffffff - -/// D18F3x88 -typedef union { - struct { ///< - UINT32 Reserved_31_0:32; ///< - } Field; ///< - UINT32 Value; ///< -} D18F3x88_STRUCT; - -// **** D18F3x8C Register Definition **** -// Address -#define D18F3x8C_ADDRESS 0x8c - -// Type -#define D18F3x8C_TYPE TYPE_D18F3 -// Field Data -#define D18F3x8C_Reserved_12_0_OFFSET 0 -#define D18F3x8C_Reserved_12_0_WIDTH 13 -#define D18F3x8C_Reserved_12_0_MASK 0x1fff -#define D18F3x8C_DisUsSysMgtReqToNcHt_OFFSET 13 -#define D18F3x8C_DisUsSysMgtReqToNcHt_WIDTH 1 -#define D18F3x8C_DisUsSysMgtReqToNcHt_MASK 0x2000 -#define D18F3x8C_EnableCf8ExtCfg_OFFSET 14 -#define D18F3x8C_EnableCf8ExtCfg_WIDTH 1 -#define D18F3x8C_EnableCf8ExtCfg_MASK 0x4000 -#define D18F3x8C_Reserved_25_15_OFFSET 15 -#define D18F3x8C_Reserved_25_15_WIDTH 11 -#define D18F3x8C_Reserved_25_15_MASK 0x3ff8000 -#define D18F3x8C_EnConvertToNonIsoc_OFFSET 26 -#define D18F3x8C_EnConvertToNonIsoc_WIDTH 1 -#define D18F3x8C_EnConvertToNonIsoc_MASK 0x4000000 -#define D18F3x8C_Reserved_31_27_OFFSET 27 -#define D18F3x8C_Reserved_31_27_WIDTH 5 -#define D18F3x8C_Reserved_31_27_MASK 0xf8000000 - -/// D18F3x8C -typedef union { - struct { ///< - UINT32 Reserved_12_0:13; ///< - UINT32 DisUsSysMgtReqToNcHt:1 ; ///< - UINT32 EnableCf8ExtCfg:1 ; ///< - UINT32 Reserved_25_15:11; ///< - UINT32 EnConvertToNonIsoc:1 ; ///< - UINT32 Reserved_31_27:5 ; ///< - } Field; ///< - UINT32 Value; ///< -} D18F3x8C_STRUCT; - - -// **** D18F3xA4 Register Definition **** -// Address -#define D18F3xA4_ADDRESS 0xa4 - -// Type -#define D18F3xA4_TYPE TYPE_D18F3 -// Field Data -#define D18F3xA4_PerStepTimeUp_OFFSET 0 -#define D18F3xA4_PerStepTimeUp_WIDTH 5 -#define D18F3xA4_PerStepTimeUp_MASK 0x1f -#define D18F3xA4_TmpMaxDiffUp_OFFSET 5 -#define D18F3xA4_TmpMaxDiffUp_WIDTH 2 -#define D18F3xA4_TmpMaxDiffUp_MASK 0x60 -#define D18F3xA4_TmpSlewDnEn_OFFSET 7 -#define D18F3xA4_TmpSlewDnEn_WIDTH 1 -#define D18F3xA4_TmpSlewDnEn_MASK 0x80 -#define D18F3xA4_PerStepTimeDn_OFFSET 8 -#define D18F3xA4_PerStepTimeDn_WIDTH 5 -#define D18F3xA4_PerStepTimeDn_MASK 0x1f00 -#define D18F3xA4_Reserved_20_13_OFFSET 13 -#define D18F3xA4_Reserved_20_13_WIDTH 8 -#define D18F3xA4_Reserved_20_13_MASK 0x1fe000 -#define D18F3xA4_CurTmp_OFFSET 21 -#define D18F3xA4_CurTmp_WIDTH 11 -#define D18F3xA4_CurTmp_MASK 0xffe00000 - -/// D18F3xA4 -typedef union { - struct { ///< - UINT32 PerStepTimeUp:5 ; ///< - UINT32 TmpMaxDiffUp:2 ; ///< - UINT32 TmpSlewDnEn:1 ; ///< - UINT32 PerStepTimeDn:5 ; ///< - UINT32 Reserved_20_13:8 ; ///< - UINT32 CurTmp:11; ///< - } Field; ///< - UINT32 Value; ///< -} D18F3xA4_STRUCT; - - -// **** D18F3xD8 Register Definition **** -// Address -#define D18F3xD8_ADDRESS 0xd8 - -// Type -#define D18F3xD8_TYPE TYPE_D18F3 -// Field Data -#define D18F3xD8_Reserved_3_0_OFFSET 0 -#define D18F3xD8_Reserved_3_0_WIDTH 4 -#define D18F3xD8_Reserved_3_0_MASK 0xf -#define D18F3xD8_VSRampSlamTime_OFFSET 4 -#define D18F3xD8_VSRampSlamTime_WIDTH 3 -#define D18F3xD8_VSRampSlamTime_MASK 0x70 -#define D18F3xD8_ExtndTriDly_OFFSET 7 -#define D18F3xD8_ExtndTriDly_WIDTH 5 -#define D18F3xD8_ExtndTriDly_MASK 0xf80 -#define D18F3xD8_Reserved_28_12_OFFSET 12 -#define D18F3xD8_Reserved_28_12_WIDTH 17 -#define D18F3xD8_Reserved_28_12_MASK 0x1ffff000 -#define D18F3xD8_Reserved_31_29_OFFSET 29 -#define D18F3xD8_Reserved_31_29_WIDTH 3 -#define D18F3xD8_Reserved_31_29_MASK 0xe0000000 - -/// D18F3xD8 -typedef union { - struct { ///< - UINT32 Reserved_3_0:4 ; ///< - UINT32 VSRampSlamTime:3 ; ///< - UINT32 ExtndTriDly:5 ; ///< - UINT32 Reserved_28_12:17; ///< - UINT32 Reserved_31_29:3 ; ///< - } Field; ///< - UINT32 Value; ///< -} D18F3xD8_STRUCT; - -// **** D18F3xDC Register Definition **** -// Address -#define D18F3xDC_ADDRESS 0xdc - -// Type -#define D18F3xDC_TYPE TYPE_D18F3 -// Field Data -#define D18F3xDC_Reserved_7_0_OFFSET 0 -#define D18F3xDC_Reserved_7_0_WIDTH 8 -#define D18F3xDC_Reserved_7_0_MASK 0xff -#define D18F3xDC_PstateMaxVal_OFFSET 8 -#define D18F3xDC_PstateMaxVal_WIDTH 3 -#define D18F3xDC_PstateMaxVal_MASK 0x700 -#define D18F3xDC_Reserved_11_11_OFFSET 11 -#define D18F3xDC_Reserved_11_11_WIDTH 1 -#define D18F3xDC_Reserved_11_11_MASK 0x800 -#define D18F3xDC_NbPs0Vid_OFFSET 12 -#define D18F3xDC_NbPs0Vid_WIDTH 7 -#define D18F3xDC_NbPs0Vid_MASK 0x7f000 -#define D18F3xDC_NclkFreqDone_OFFSET 19 -#define D18F3xDC_NclkFreqDone_WIDTH 1 -#define D18F3xDC_NclkFreqDone_MASK 0x80000 -#define D18F3xDC_NbPs0NclkDiv_OFFSET 20 -#define D18F3xDC_NbPs0NclkDiv_WIDTH 7 -#define D18F3xDC_NbPs0NclkDiv_MASK 0x7f00000 -#define D18F3xDC_NbClockGateHyst_OFFSET 27 -#define D18F3xDC_NbClockGateHyst_WIDTH 3 -#define D18F3xDC_NbClockGateHyst_MASK 0x38000000 -#define D18F3xDC_NbClockGateEn_OFFSET 30 -#define D18F3xDC_NbClockGateEn_WIDTH 1 -#define D18F3xDC_NbClockGateEn_MASK 0x40000000 -#define D18F3xDC_CnbCifClockGateEn_OFFSET 31 -#define D18F3xDC_CnbCifClockGateEn_WIDTH 1 -#define D18F3xDC_CnbCifClockGateEn_MASK 0x80000000 - -/// D18F3xDC -typedef union { - struct { ///< - UINT32 Reserved_7_0:8 ; ///< - UINT32 PstateMaxVal:3 ; ///< - UINT32 Reserved_11_11:1 ; ///< - UINT32 NbPs0Vid:7 ; ///< - UINT32 NclkFreqDone:1 ; ///< - UINT32 NbPs0NclkDiv:7 ; ///< - UINT32 NbClockGateHyst:3 ; ///< - UINT32 NbClockGateEn:1 ; ///< - UINT32 CnbCifClockGateEn:1 ; ///< - } Field; ///< - UINT32 Value; ///< -} D18F3xDC_STRUCT; - -// **** D18F3xE4 Register Definition **** -// Address -#define D18F3xE4_ADDRESS 0xe4 - -// Type -#define D18F3xE4_TYPE TYPE_D18F3 -// Field Data -#define D18F3xE4_Reserved_0_0_OFFSET 0 -#define D18F3xE4_Reserved_0_0_WIDTH 1 -#define D18F3xE4_Reserved_0_0_MASK 0x1 -#define D18F3xE4_Thermtp_OFFSET 1 -#define D18F3xE4_Thermtp_WIDTH 1 -#define D18F3xE4_Thermtp_MASK 0x2 -#define D18F3xE4_Reserved_2_2_OFFSET 2 -#define D18F3xE4_Reserved_2_2_WIDTH 1 -#define D18F3xE4_Reserved_2_2_MASK 0x4 -#define D18F3xE4_ThermtpSense_OFFSET 3 -#define D18F3xE4_ThermtpSense_WIDTH 1 -#define D18F3xE4_ThermtpSense_MASK 0x8 -#define D18F3xE4_Reserved_4_4_OFFSET 4 -#define D18F3xE4_Reserved_4_4_WIDTH 1 -#define D18F3xE4_Reserved_4_4_MASK 0x10 -#define D18F3xE4_ThermtpEn_OFFSET 5 -#define D18F3xE4_ThermtpEn_WIDTH 1 -#define D18F3xE4_ThermtpEn_MASK 0x20 -#define D18F3xE4_Reserved_7_6_OFFSET 6 -#define D18F3xE4_Reserved_7_6_WIDTH 2 -#define D18F3xE4_Reserved_7_6_MASK 0xc0 -#define D18F3xE4_Reserved_30_8_OFFSET 8 -#define D18F3xE4_Reserved_30_8_WIDTH 23 -#define D18F3xE4_Reserved_30_8_MASK 0x7fffff00 -#define D18F3xE4_SwThermtp_OFFSET 31 -#define D18F3xE4_SwThermtp_WIDTH 1 -#define D18F3xE4_SwThermtp_MASK 0x80000000 - -/// D18F3xE4 -typedef union { - struct { ///< - UINT32 Reserved_0_0:1 ; ///< - UINT32 Thermtp:1 ; ///< - UINT32 Reserved_2_2:1 ; ///< - UINT32 ThermtpSense:1 ; ///< - UINT32 Reserved_4_4:1 ; ///< - UINT32 ThermtpEn:1 ; ///< - UINT32 Reserved_7_6:2 ; ///< - UINT32 Reserved_30_8:23; ///< - UINT32 SwThermtp:1 ; ///< - } Field; ///< - UINT32 Value; ///< -} D18F3xE4_STRUCT; - -// **** D18F3xE8 Register Definition **** -// Address -#define D18F3xE8_ADDRESS 0xe8 - -// Type -#define D18F3xE8_TYPE TYPE_D18F3 -// Field Data -#define D18F3xE8_DctDualCap_OFFSET 0 -#define D18F3xE8_DctDualCap_WIDTH 1 -#define D18F3xE8_DctDualCap_MASK 0x1 -#define D18F3xE8_Reserved_4_1_OFFSET 1 -#define D18F3xE8_Reserved_4_1_WIDTH 4 -#define D18F3xE8_Reserved_4_1_MASK 0x1e -#define D18F3xE8_DdrMaxRate_OFFSET 5 -#define D18F3xE8_DdrMaxRate_WIDTH 3 -#define D18F3xE8_DdrMaxRate_MASK 0xe0 -#define D18F3xE8_MctCap_OFFSET 8 -#define D18F3xE8_MctCap_WIDTH 1 -#define D18F3xE8_MctCap_MASK 0x100 -#define D18F3xE8_SvmCapable_OFFSET 9 -#define D18F3xE8_SvmCapable_WIDTH 1 -#define D18F3xE8_SvmCapable_MASK 0x200 -#define D18F3xE8_HtcCapable_OFFSET 10 -#define D18F3xE8_HtcCapable_WIDTH 1 -#define D18F3xE8_HtcCapable_MASK 0x400 -#define D18F3xE8_Reserved_11_11_OFFSET 11 -#define D18F3xE8_Reserved_11_11_WIDTH 1 -#define D18F3xE8_Reserved_11_11_MASK 0x800 -#define D18F3xE8_CmpCap_OFFSET 12 -#define D18F3xE8_CmpCap_WIDTH 2 -#define D18F3xE8_CmpCap_MASK 0x3000 -#define D18F3xE8_Reserved_27_14_OFFSET 14 -#define D18F3xE8_Reserved_27_14_WIDTH 14 -#define D18F3xE8_Reserved_27_14_MASK 0xfffc000 -#define D18F3xE8_LHtcCapable_OFFSET 28 -#define D18F3xE8_LHtcCapable_WIDTH 1 -#define D18F3xE8_LHtcCapable_MASK 0x10000000 -#define D18F3xE8_Reserved_31_29_OFFSET 29 -#define D18F3xE8_Reserved_31_29_WIDTH 3 -#define D18F3xE8_Reserved_31_29_MASK 0xe0000000 - -/// D18F3xE8 -typedef union { - struct { ///< - UINT32 DctDualCap:1 ; ///< - UINT32 Reserved_4_1:4 ; ///< - UINT32 DdrMaxRate:3 ; ///< - UINT32 MctCap:1 ; ///< - UINT32 SvmCapable:1 ; ///< - UINT32 HtcCapable:1 ; ///< - UINT32 Reserved_11_11:1 ; ///< - UINT32 CmpCap:2 ; ///< - UINT32 Reserved_27_14:14; ///< - UINT32 LHtcCapable:1 ; ///< - UINT32 Reserved_31_29:3 ; ///< - } Field; ///< - UINT32 Value; ///< -} D18F3xE8_STRUCT; - -// **** D18F3xF0 Register Definition **** -// Address -#define D18F3xF0_ADDRESS 0xf0 - -// Type -#define D18F3xF0_TYPE TYPE_D18F3 -// Field Data -#define D18F3xF0_Reserved_31_0_OFFSET 0 -#define D18F3xF0_Reserved_31_0_WIDTH 32 -#define D18F3xF0_Reserved_31_0_MASK 0xffffffff - -/// D18F3xF0 -typedef union { - struct { ///< - UINT32 Reserved_31_0:32; ///< - } Field; ///< - UINT32 Value; ///< -} D18F3xF0_STRUCT; - -// **** D18F3xF4 Register Definition **** -// Address -#define D18F3xF4_ADDRESS 0xf4 - -// Type -#define D18F3xF4_TYPE TYPE_D18F3 -// Field Data -#define D18F3xF4_Reserved_31_0_OFFSET 0 -#define D18F3xF4_Reserved_31_0_WIDTH 32 -#define D18F3xF4_Reserved_31_0_MASK 0xffffffff - -/// D18F3xF4 -typedef union { - struct { ///< - UINT32 Reserved_31_0:32; ///< - } Field; ///< - UINT32 Value; ///< -} D18F3xF4_STRUCT; - -// **** D18F3xF8 Register Definition **** -// Address -#define D18F3xF8_ADDRESS 0xf8 - -// Type -#define D18F3xF8_TYPE TYPE_D18F3 -// Field Data -#define D18F3xF8_Reserved_31_0_OFFSET 0 -#define D18F3xF8_Reserved_31_0_WIDTH 32 -#define D18F3xF8_Reserved_31_0_MASK 0xffffffff - -/// D18F3xF8 -typedef union { - struct { ///< - UINT32 Reserved_31_0:32; ///< - } Field; ///< - UINT32 Value; ///< -} D18F3xF8_STRUCT; - -// **** D18F3xFC Register Definition **** -// Address -#define D18F3xFC_ADDRESS 0xfc - -// Type -#define D18F3xFC_TYPE TYPE_D18F3 -// Field Data -#define D18F3xFC_Stepping_OFFSET 0 -#define D18F3xFC_Stepping_WIDTH 4 -#define D18F3xFC_Stepping_MASK 0xf -#define D18F3xFC_BaseModel_OFFSET 4 -#define D18F3xFC_BaseModel_WIDTH 4 -#define D18F3xFC_BaseModel_MASK 0xf0 -#define D18F3xFC_BaseFamily_OFFSET 8 -#define D18F3xFC_BaseFamily_WIDTH 4 -#define D18F3xFC_BaseFamily_MASK 0xf00 -#define D18F3xFC_Reserved_15_12_OFFSET 12 -#define D18F3xFC_Reserved_15_12_WIDTH 4 -#define D18F3xFC_Reserved_15_12_MASK 0xf000 -#define D18F3xFC_ExtModel_OFFSET 16 -#define D18F3xFC_ExtModel_WIDTH 4 -#define D18F3xFC_ExtModel_MASK 0xf0000 -#define D18F3xFC_ExtFamily_OFFSET 20 -#define D18F3xFC_ExtFamily_WIDTH 8 -#define D18F3xFC_ExtFamily_MASK 0xff00000 -#define D18F3xFC_Reserved_31_28_OFFSET 28 -#define D18F3xFC_Reserved_31_28_WIDTH 4 -#define D18F3xFC_Reserved_31_28_MASK 0xf0000000 - -/// D18F3xFC -typedef union { - struct { ///< - UINT32 Stepping:4 ; ///< - UINT32 BaseModel:4 ; ///< - UINT32 BaseFamily:4 ; ///< - UINT32 Reserved_15_12:4 ; ///< - UINT32 ExtModel:4 ; ///< - UINT32 ExtFamily:8 ; ///< - UINT32 Reserved_31_28:4 ; ///< - } Field; ///< - UINT32 Value; ///< -} D18F3xFC_STRUCT; - -// **** D18F3x128 Register Definition **** -// Address -#define D18F3x128_ADDRESS 0x128 - -// Type -#define D18F3x128_TYPE TYPE_D18F3 -// Field Data -#define D18F3x128_C6Vid_OFFSET 0 -#define D18F3x128_C6Vid_WIDTH 7 -#define D18F3x128_C6Vid_MASK 0x7f -#define D18F3x128_Reserved_7_7_OFFSET 7 -#define D18F3x128_Reserved_7_7_WIDTH 1 -#define D18F3x128_Reserved_7_7_MASK 0x80 -#define D18F3x128_NbPsiVid_OFFSET 8 -#define D18F3x128_NbPsiVid_WIDTH 7 -#define D18F3x128_NbPsiVid_MASK 0x7f00 -#define D18F3x128_NbPsiVidEn_OFFSET 15 -#define D18F3x128_NbPsiVidEn_WIDTH 1 -#define D18F3x128_NbPsiVidEn_MASK 0x8000 -#define D18F3x128_Reserved_31_16_OFFSET 16 -#define D18F3x128_Reserved_31_16_WIDTH 16 -#define D18F3x128_Reserved_31_16_MASK 0xffff0000 - -/// D18F3x128 -typedef union { - struct { ///< - UINT32 C6Vid:7 ; ///< - UINT32 Reserved_7_7:1 ; ///< - UINT32 NbPsiVid:7 ; ///< - UINT32 NbPsiVidEn:1 ; ///< - UINT32 Reserved_31_16:16; ///< - } Field; ///< - UINT32 Value; ///< -} D18F3x128_STRUCT; - -// **** D18F3x138 Register Definition **** -// Address -#define D18F3x138_ADDRESS 0x138 - -// Type -#define D18F3x138_TYPE TYPE_D18F3 -// Field Data -#define D18F3x138_LHtcEn_OFFSET 0 -#define D18F3x138_LHtcEn_WIDTH 1 -#define D18F3x138_LHtcEn_MASK 0x1 -#define D18F3x138_Reserved_7_1_OFFSET 1 -#define D18F3x138_Reserved_7_1_WIDTH 7 -#define D18F3x138_Reserved_7_1_MASK 0xfe -#define D18F3x138_LHtcAct_OFFSET 8 -#define D18F3x138_LHtcAct_WIDTH 1 -#define D18F3x138_LHtcAct_MASK 0x100 -#define D18F3x138_Reserved_11_9_OFFSET 9 -#define D18F3x138_Reserved_11_9_WIDTH 3 -#define D18F3x138_Reserved_11_9_MASK 0xe00 -#define D18F3x138_LHtcActSts_OFFSET 12 -#define D18F3x138_LHtcActSts_WIDTH 1 -#define D18F3x138_LHtcActSts_MASK 0x1000 -#define D18F3x138_Reserved_15_13_OFFSET 13 -#define D18F3x138_Reserved_15_13_WIDTH 3 -#define D18F3x138_Reserved_15_13_MASK 0xe000 -#define D18F3x138_LHtcTmpLmt_OFFSET 16 -#define D18F3x138_LHtcTmpLmt_WIDTH 7 -#define D18F3x138_LHtcTmpLmt_MASK 0x7f0000 -#define D18F3x138_LHtcSlewSel_OFFSET 23 -#define D18F3x138_LHtcSlewSel_WIDTH 1 -#define D18F3x138_LHtcSlewSel_MASK 0x800000 -#define D18F3x138_LHtcHystLmt_OFFSET 24 -#define D18F3x138_LHtcHystLmt_WIDTH 4 -#define D18F3x138_LHtcHystLmt_MASK 0xf000000 -#define D18F3x138_LHtcPstateLimit_OFFSET 28 -#define D18F3x138_LHtcPstateLimit_WIDTH 3 -#define D18F3x138_LHtcPstateLimit_MASK 0x70000000 -#define D18F3x138_LHtcLock_OFFSET 31 -#define D18F3x138_LHtcLock_WIDTH 1 -#define D18F3x138_LHtcLock_MASK 0x80000000 - -/// D18F3x138 -typedef union { - struct { ///< - UINT32 LHtcEn:1 ; ///< - UINT32 Reserved_7_1:7 ; ///< - UINT32 LHtcAct:1 ; ///< - UINT32 Reserved_11_9:3 ; ///< - UINT32 LHtcActSts:1 ; ///< - UINT32 Reserved_15_13:3 ; ///< - UINT32 LHtcTmpLmt:7 ; ///< - UINT32 LHtcSlewSel:1 ; ///< - UINT32 LHtcHystLmt:4 ; ///< - UINT32 LHtcPstateLimit:3 ; ///< - UINT32 LHtcLock:1 ; ///< - } Field; ///< - UINT32 Value; ///< -} D18F3x138_STRUCT; - -// **** D18F3x15C Register Definition **** -// Address -#define D18F3x15C_ADDRESS 0x15c - -// Type -#define D18F3x15C_TYPE TYPE_D18F3 -// Field Data -#define D18F3x15C_SclkVidLevel0_OFFSET 0 -#define D18F3x15C_SclkVidLevel0_WIDTH 7 -#define D18F3x15C_SclkVidLevel0_MASK 0x7f -#define D18F3x15C_Reserved_7_7_OFFSET 7 -#define D18F3x15C_Reserved_7_7_WIDTH 1 -#define D18F3x15C_Reserved_7_7_MASK 0x80 -#define D18F3x15C_SclkVidLevel1_OFFSET 8 -#define D18F3x15C_SclkVidLevel1_WIDTH 7 -#define D18F3x15C_SclkVidLevel1_MASK 0x7f00 -#define D18F3x15C_Reserved_15_15_OFFSET 15 -#define D18F3x15C_Reserved_15_15_WIDTH 1 -#define D18F3x15C_Reserved_15_15_MASK 0x8000 -#define D18F3x15C_SclkVidLevel2_OFFSET 16 -#define D18F3x15C_SclkVidLevel2_WIDTH 7 -#define D18F3x15C_SclkVidLevel2_MASK 0x7f0000 -#define D18F3x15C_Reserved_23_23_OFFSET 23 -#define D18F3x15C_Reserved_23_23_WIDTH 1 -#define D18F3x15C_Reserved_23_23_MASK 0x800000 -#define D18F3x15C_SclkVidLevel3_OFFSET 24 -#define D18F3x15C_SclkVidLevel3_WIDTH 7 -#define D18F3x15C_SclkVidLevel3_MASK 0x7f000000 -#define D18F3x15C_Reserved_31_31_OFFSET 31 -#define D18F3x15C_Reserved_31_31_WIDTH 1 -#define D18F3x15C_Reserved_31_31_MASK 0x80000000 - -/// D18F3x15C -typedef union { - struct { ///< - UINT32 SclkVidLevel0:7 ; ///< - UINT32 Reserved_7_7:1 ; ///< - UINT32 SclkVidLevel1:7 ; ///< - UINT32 Reserved_15_15:1 ; ///< - UINT32 SclkVidLevel2:7 ; ///< - UINT32 Reserved_23_23:1 ; ///< - UINT32 SclkVidLevel3:7 ; ///< - UINT32 Reserved_31_31:1 ; ///< - } Field; ///< - UINT32 Value; ///< -} D18F3x15C_STRUCT; - -// **** D18F3x17C Register Definition **** -// Address -#define D18F3x17C_ADDRESS 0x17c - -// Type -#define D18F3x17C_TYPE TYPE_D18F3 -// Field Data -#define D18F3x17C_HiPriPBC_OFFSET 0 -#define D18F3x17C_HiPriPBC_WIDTH 6 -#define D18F3x17C_HiPriPBC_MASK 0x3f -#define D18F3x17C_Reserved_7_6_OFFSET 6 -#define D18F3x17C_Reserved_7_6_WIDTH 2 -#define D18F3x17C_Reserved_7_6_MASK 0xc0 -#define D18F3x17C_HiPriNPBC_OFFSET 8 -#define D18F3x17C_HiPriNPBC_WIDTH 6 -#define D18F3x17C_HiPriNPBC_MASK 0x3f00 -#define D18F3x17C_Reserved_31_14_OFFSET 14 -#define D18F3x17C_Reserved_31_14_WIDTH 18 -#define D18F3x17C_Reserved_31_14_MASK 0xffffc000 - -/// D18F3x17C -typedef union { - struct { ///< - UINT32 HiPriPBC:6 ; ///< - UINT32 Reserved_7_6:2 ; ///< - UINT32 HiPriNPBC:6 ; ///< - UINT32 Reserved_31_14:18; ///< - } Field; ///< - UINT32 Value; ///< -} D18F3x17C_STRUCT; - -// **** D18F3x180 Register Definition **** -// Address -#define D18F3x180_ADDRESS 0x180 - -// Type -#define D18F3x180_TYPE TYPE_D18F3 -// Field Data -#define D18F3x180_Reserved_1_0_OFFSET 0 -#define D18F3x180_Reserved_1_0_WIDTH 2 -#define D18F3x180_Reserved_1_0_MASK 0x3 -#define D18F3x180_WDTCntSel_3__OFFSET 2 -#define D18F3x180_WDTCntSel_3__WIDTH 1 -#define D18F3x180_WDTCntSel_3__MASK 0x4 -#define D18F3x180_DatErrChgToTgtAbt_OFFSET 3 -#define D18F3x180_DatErrChgToTgtAbt_WIDTH 1 -#define D18F3x180_DatErrChgToTgtAbt_MASK 0x8 -#define D18F3x180_MstAbtChgToNoErrs_OFFSET 4 -#define D18F3x180_MstAbtChgToNoErrs_WIDTH 1 -#define D18F3x180_MstAbtChgToNoErrs_MASK 0x10 -#define D18F3x180_DisPciCfgCpuMstAbtRsp_OFFSET 5 -#define D18F3x180_DisPciCfgCpuMstAbtRsp_WIDTH 1 -#define D18F3x180_DisPciCfgCpuMstAbtRsp_MASK 0x20 -#define D18F3x180_Reserved_6_6_OFFSET 6 -#define D18F3x180_Reserved_6_6_WIDTH 1 -#define D18F3x180_Reserved_6_6_MASK 0x40 -#define D18F3x180_SyncFloodOnTgtAbtErr_OFFSET 7 -#define D18F3x180_SyncFloodOnTgtAbtErr_WIDTH 1 -#define D18F3x180_SyncFloodOnTgtAbtErr_MASK 0x80 -#define D18F3x180_Reserved_20_8_OFFSET 8 -#define D18F3x180_Reserved_20_8_WIDTH 13 -#define D18F3x180_Reserved_20_8_MASK 0x1fff00 -#define D18F3x180_SyncFloodOnCpuLeakErr_OFFSET 21 -#define D18F3x180_SyncFloodOnCpuLeakErr_WIDTH 1 -#define D18F3x180_SyncFloodOnCpuLeakErr_MASK 0x200000 -#define D18F3x180_Reserved_31_22_OFFSET 22 -#define D18F3x180_Reserved_31_22_WIDTH 10 -#define D18F3x180_Reserved_31_22_MASK 0xffc00000 - -/// D18F3x180 -typedef union { - struct { ///< - UINT32 Reserved_1_0:2 ; ///< - UINT32 WDTCntSel_3_:1 ; ///< - UINT32 DatErrChgToTgtAbt:1 ; ///< - UINT32 MstAbtChgToNoErrs:1 ; ///< - UINT32 DisPciCfgCpuMstAbtRsp:1 ; ///< - UINT32 Reserved_6_6:1 ; ///< - UINT32 SyncFloodOnTgtAbtErr:1 ; ///< - UINT32 Reserved_20_8:13; ///< - UINT32 SyncFloodOnCpuLeakErr:1 ; ///< - UINT32 Reserved_31_22:10; ///< - } Field; ///< - UINT32 Value; ///< -} D18F3x180_STRUCT; - -// **** D18F3x188 Register Definition **** -// Address -#define D18F3x188_ADDRESS 0x188 - -// Type -#define D18F3x188_TYPE TYPE_D18F3 -// Field Data -#define D18F3x188_Reserved_20_0_OFFSET 0 -#define D18F3x188_Reserved_20_0_WIDTH 21 -#define D18F3x188_Reserved_20_0_MASK 0x1fffff -#define D18F3x188_EnCpuSerWrBehindIoRd_OFFSET 21 -#define D18F3x188_EnCpuSerWrBehindIoRd_WIDTH 1 -#define D18F3x188_EnCpuSerWrBehindIoRd_MASK 0x200000 -#define D18F3x188_EnCpuSerRdBehindNpIoWr_OFFSET 22 -#define D18F3x188_EnCpuSerRdBehindNpIoWr_WIDTH 1 -#define D18F3x188_EnCpuSerRdBehindNpIoWr_MASK 0x400000 -#define D18F3x188_EnCpuSerRdBehindIoRd_OFFSET 23 -#define D18F3x188_EnCpuSerRdBehindIoRd_WIDTH 1 -#define D18F3x188_EnCpuSerRdBehindIoRd_MASK 0x800000 -#define D18F3x188_FeArbCpuWeightOverLoPrio_OFFSET 24 -#define D18F3x188_FeArbCpuWeightOverLoPrio_WIDTH 4 -#define D18F3x188_FeArbCpuWeightOverLoPrio_MASK 0xf000000 -#define D18F3x188_FeArbCpuWeightOverHiPrio_OFFSET 28 -#define D18F3x188_FeArbCpuWeightOverHiPrio_WIDTH 4 -#define D18F3x188_FeArbCpuWeightOverHiPrio_MASK 0xf0000000 - -/// D18F3x188 -typedef union { - struct { ///< - UINT32 Reserved_20_0:21; ///< - UINT32 EnCpuSerWrBehindIoRd:1 ; ///< - UINT32 EnCpuSerRdBehindNpIoWr:1 ; ///< - UINT32 EnCpuSerRdBehindIoRd:1 ; ///< - UINT32 FeArbCpuWeightOverLoPrio:4 ; ///< - UINT32 FeArbCpuWeightOverHiPrio:4 ; ///< - } Field; ///< - UINT32 Value; ///< -} D18F3x188_STRUCT; - -// **** D18F3x1CC Register Definition **** -// Address -#define D18F3x1CC_ADDRESS 0x1cc - -// Type -#define D18F3x1CC_TYPE TYPE_D18F3 -// Field Data -#define D18F3x1CC_LvtOffset_OFFSET 0 -#define D18F3x1CC_LvtOffset_WIDTH 4 -#define D18F3x1CC_LvtOffset_MASK 0xf -#define D18F3x1CC_Reserved_7_4_OFFSET 4 -#define D18F3x1CC_Reserved_7_4_WIDTH 4 -#define D18F3x1CC_Reserved_7_4_MASK 0xf0 -#define D18F3x1CC_LvtOffsetVal_OFFSET 8 -#define D18F3x1CC_LvtOffsetVal_WIDTH 1 -#define D18F3x1CC_LvtOffsetVal_MASK 0x100 -#define D18F3x1CC_Reserved_31_9_OFFSET 9 -#define D18F3x1CC_Reserved_31_9_WIDTH 23 -#define D18F3x1CC_Reserved_31_9_MASK 0xfffffe00 - -/// D18F3x1CC -typedef union { - struct { ///< - UINT32 LvtOffset:4 ; ///< - UINT32 Reserved_7_4:4 ; ///< - UINT32 LvtOffsetVal:1 ; ///< - UINT32 Reserved_31_9:23; ///< - } Field; ///< - UINT32 Value; ///< -} D18F3x1CC_STRUCT; - -// **** D18F3x1E4 Register Definition **** -// Address -#define D18F3x1E4_ADDRESS 0x1e4 - -// Type -#define D18F3x1E4_TYPE TYPE_D18F3 -// Field Data -#define D18F3x1E4_Reserved_0_0_OFFSET 0 -#define D18F3x1E4_Reserved_0_0_WIDTH 1 -#define D18F3x1E4_Reserved_0_0_MASK 0x1 -#define D18F3x1E4_SbTsiDis_OFFSET 1 -#define D18F3x1E4_SbTsiDis_WIDTH 1 -#define D18F3x1E4_SbTsiDis_MASK 0x2 -#define D18F3x1E4_Reserved_3_2_OFFSET 2 -#define D18F3x1E4_Reserved_3_2_WIDTH 2 -#define D18F3x1E4_Reserved_3_2_MASK 0xc -#define D18F3x1E4_SbiAddr_OFFSET 4 -#define D18F3x1E4_SbiAddr_WIDTH 3 -#define D18F3x1E4_SbiAddr_MASK 0x70 -#define D18F3x1E4_Reserved_30_7_OFFSET 7 -#define D18F3x1E4_Reserved_30_7_WIDTH 24 -#define D18F3x1E4_Reserved_30_7_MASK 0x7fffff80 -#define D18F3x1E4_SbiRegWrDn_OFFSET 31 -#define D18F3x1E4_SbiRegWrDn_WIDTH 1 -#define D18F3x1E4_SbiRegWrDn_MASK 0x80000000 - -/// D18F3x1E4 -typedef union { - struct { ///< - UINT32 Reserved_0_0:1 ; ///< - UINT32 SbTsiDis:1 ; ///< - UINT32 Reserved_3_2:2 ; ///< - UINT32 SbiAddr:3 ; ///< - UINT32 Reserved_30_7:24; ///< - UINT32 SbiRegWrDn:1 ; ///< - } Field; ///< - UINT32 Value; ///< -} D18F3x1E4_STRUCT; - -// **** D18F3x1E8 Register Definition **** -// Address -#define D18F3x1E8_ADDRESS 0x1e8 - -// Type -#define D18F3x1E8_TYPE TYPE_D18F3 -// Field Data -#define D18F3x1E8_SbiRegAddr_OFFSET 0 -#define D18F3x1E8_SbiRegAddr_WIDTH 8 -#define D18F3x1E8_SbiRegAddr_MASK 0xff -#define D18F3x1E8_Reserved_31_8_OFFSET 8 -#define D18F3x1E8_Reserved_31_8_WIDTH 24 -#define D18F3x1E8_Reserved_31_8_MASK 0xffffff00 - -/// D18F3x1E8 -typedef union { - struct { ///< - UINT32 SbiRegAddr:8 ; ///< - UINT32 Reserved_31_8:24; ///< - } Field; ///< - UINT32 Value; ///< -} D18F3x1E8_STRUCT; - -// **** D18F3x1EC Register Definition **** -// Address -#define D18F3x1EC_ADDRESS 0x1ec - -// Type -#define D18F3x1EC_TYPE TYPE_D18F3 -// Field Data -#define D18F3x1EC_SbiRegDat0_OFFSET 0 -#define D18F3x1EC_SbiRegDat0_WIDTH 8 -#define D18F3x1EC_SbiRegDat0_MASK 0xff -#define D18F3x1EC_Reserved_31_8_OFFSET 8 -#define D18F3x1EC_Reserved_31_8_WIDTH 24 -#define D18F3x1EC_Reserved_31_8_MASK 0xffffff00 - -/// D18F3x1EC -typedef union { - struct { ///< - UINT32 SbiRegDat0:8 ; ///< - UINT32 Reserved_31_8:24; ///< - } Field; ///< - UINT32 Value; ///< -} D18F3x1EC_STRUCT; - -// **** D18F3x1F0 Register Definition **** -// Address -#define D18F3x1F0_ADDRESS 0x1f0 - -// Type -#define D18F3x1F0_TYPE TYPE_D18F3 -// Field Data -#define D18F3x1F0_BrandId_OFFSET 0 -#define D18F3x1F0_BrandId_WIDTH 16 -#define D18F3x1F0_BrandId_MASK 0xffff -#define D18F3x1F0_Reserved_31_16_OFFSET 16 -#define D18F3x1F0_Reserved_31_16_WIDTH 16 -#define D18F3x1F0_Reserved_31_16_MASK 0xffff0000 - -/// D18F3x1F0 -typedef union { - struct { ///< - UINT32 BrandId:16; ///< - UINT32 Reserved_31_16:16; ///< - } Field; ///< - UINT32 Value; ///< -} D18F3x1F0_STRUCT; - -// **** D18F4x12C Register Definition **** -// Address -#define D18F4x12C_ADDRESS 0x12c - -// Type -#define D18F4x12C_TYPE TYPE_D18F4 -// Field Data -#define D18F4x12C_C6Base_39_24__OFFSET 0 -#define D18F4x12C_C6Base_39_24__WIDTH 16 -#define D18F4x12C_C6Base_39_24__MASK 0xffff -#define D18F4x12C_Reserved_31_16_OFFSET 16 -#define D18F4x12C_Reserved_31_16_WIDTH 16 -#define D18F4x12C_Reserved_31_16_MASK 0xffff0000 - -/// D18F4x12C -typedef union { - struct { ///< - UINT32 C6Base_39_24_:16; ///< - UINT32 Reserved_31_16:16; ///< - } Field; ///< - UINT32 Value; ///< -} D18F4x12C_STRUCT; - -// **** D18F4x15C Register Definition **** -// Address -#define D18F4x15C_ADDRESS 0x15c - -// Type -#define D18F4x15C_TYPE TYPE_D18F4 -// Field Data -#define D18F4x15C_BoostSrc_OFFSET 0 -#define D18F4x15C_BoostSrc_WIDTH 2 -#define D18F4x15C_BoostSrc_MASK 0x3 -#define D18F4x15C_NumBoostStates_OFFSET 2 -#define D18F4x15C_NumBoostStates_WIDTH 3 -#define D18F4x15C_NumBoostStates_MASK 0x1c -#define D18F4x15C_Reserved_27_5_OFFSET 5 -#define D18F4x15C_Reserved_27_5_WIDTH 23 -#define D18F4x15C_Reserved_27_5_MASK 0xfffffe0 -#define D18F4x15C_IgnoreBoostThresh_OFFSET 28 -#define D18F4x15C_IgnoreBoostThresh_WIDTH 1 -#define D18F4x15C_IgnoreBoostThresh_MASK 0x10000000 -#define D18F4x15C_BoostEnAllCores_OFFSET 29 -#define D18F4x15C_BoostEnAllCores_WIDTH 1 -#define D18F4x15C_BoostEnAllCores_MASK 0x20000000 -#define D18F4x15C_Reserved_31_30_OFFSET 30 -#define D18F4x15C_Reserved_31_30_WIDTH 2 -#define D18F4x15C_Reserved_31_30_MASK 0xc0000000 - -/// D18F4x15C -typedef union { - struct { ///< - UINT32 BoostSrc:2 ; ///< - UINT32 NumBoostStates:3 ; ///< - UINT32 Reserved_27_5:23; ///< - UINT32 IgnoreBoostThresh:1 ; ///< - UINT32 BoostEnAllCores:1 ; ///< - UINT32 Reserved_31_30:2 ; ///< - } Field; ///< - UINT32 Value; ///< -} D18F4x15C_STRUCT; - -// **** D18F6x90 Register Definition **** -// Address -#define D18F6x90_ADDRESS 0x90 - -// Type -#define D18F6x90_TYPE TYPE_D18F6 -// Field Data -#define D18F6x90_NbPs1NclkDiv_OFFSET 0 -#define D18F6x90_NbPs1NclkDiv_WIDTH 7 -#define D18F6x90_NbPs1NclkDiv_MASK 0x7f -#define D18F6x90_Reserved_7_7_OFFSET 7 -#define D18F6x90_Reserved_7_7_WIDTH 1 -#define D18F6x90_Reserved_7_7_MASK 0x80 -#define D18F6x90_NbPs1Vid_OFFSET 8 -#define D18F6x90_NbPs1Vid_WIDTH 7 -#define D18F6x90_NbPs1Vid_MASK 0x7f00 -#define D18F6x90_Reserved_15_15_OFFSET 15 -#define D18F6x90_Reserved_15_15_WIDTH 1 -#define D18F6x90_Reserved_15_15_MASK 0x8000 -#define D18F6x90_NbPs1GnbSlowIgn_OFFSET 16 -#define D18F6x90_NbPs1GnbSlowIgn_WIDTH 1 -#define D18F6x90_NbPs1GnbSlowIgn_MASK 0x10000 -#define D18F6x90_Reserved_19_17_OFFSET 17 -#define D18F6x90_Reserved_19_17_WIDTH 3 -#define D18F6x90_Reserved_19_17_MASK 0xe0000 -#define D18F6x90_NbPsLock_OFFSET 20 -#define D18F6x90_NbPsLock_WIDTH 1 -#define D18F6x90_NbPsLock_MASK 0x100000 -#define D18F6x90_Reserved_27_21_OFFSET 21 -#define D18F6x90_Reserved_27_21_WIDTH 7 -#define D18F6x90_Reserved_27_21_MASK 0xfe00000 -#define D18F6x90_NbPsForceReq_OFFSET 28 -#define D18F6x90_NbPsForceReq_WIDTH 1 -#define D18F6x90_NbPsForceReq_MASK 0x10000000 -#define D18F6x90_NbPsForceSel_OFFSET 29 -#define D18F6x90_NbPsForceSel_WIDTH 1 -#define D18F6x90_NbPsForceSel_MASK 0x20000000 -#define D18F6x90_NbPsCtrlDis_OFFSET 30 -#define D18F6x90_NbPsCtrlDis_WIDTH 1 -#define D18F6x90_NbPsCtrlDis_MASK 0x40000000 -#define D18F6x90_NbPsCap_OFFSET 31 -#define D18F6x90_NbPsCap_WIDTH 1 -#define D18F6x90_NbPsCap_MASK 0x80000000 - -/// D18F6x90 -typedef union { - struct { ///< - UINT32 NbPs1NclkDiv:7 ; ///< - UINT32 Reserved_7_7:1 ; ///< - UINT32 NbPs1Vid:7 ; ///< - UINT32 Reserved_15_15:1 ; ///< - UINT32 NbPs1GnbSlowIgn:1 ; ///< - UINT32 Reserved_19_17:3 ; ///< - UINT32 NbPsLock:1 ; ///< - UINT32 Reserved_27_21:7 ; ///< - UINT32 NbPsForceReq:1 ; ///< - UINT32 NbPsForceSel:1 ; ///< - UINT32 NbPsCtrlDis:1 ; ///< - UINT32 NbPsCap:1 ; ///< - } Field; ///< - UINT32 Value; ///< -} D18F6x90_STRUCT; - -// **** D18F6x94 Register Definition **** -// Address -#define D18F6x94_ADDRESS 0x94 - -// Type -#define D18F6x94_TYPE TYPE_D18F6 -// Field Data -#define D18F6x94_CpuPstateThr_OFFSET 0 -#define D18F6x94_CpuPstateThr_WIDTH 3 -#define D18F6x94_CpuPstateThr_MASK 0x7 -#define D18F6x94_CpuPstateThrEn_OFFSET 3 -#define D18F6x94_CpuPstateThrEn_WIDTH 1 -#define D18F6x94_CpuPstateThrEn_MASK 0x8 -#define D18F6x94_NbPs1NoTransOnDma_OFFSET 4 -#define D18F6x94_NbPs1NoTransOnDma_WIDTH 1 -#define D18F6x94_NbPs1NoTransOnDma_MASK 0x10 -#define D18F6x94_Reserved_19_5_OFFSET 5 -#define D18F6x94_Reserved_19_5_WIDTH 15 -#define D18F6x94_Reserved_19_5_MASK 0xfffe0 -#define D18F6x94_NbPsNonC0Timer_OFFSET 20 -#define D18F6x94_NbPsNonC0Timer_WIDTH 3 -#define D18F6x94_NbPsNonC0Timer_MASK 0x700000 -#define D18F6x94_NbPsC0Timer_OFFSET 23 -#define D18F6x94_NbPsC0Timer_WIDTH 3 -#define D18F6x94_NbPsC0Timer_MASK 0x3800000 -#define D18F6x94_NbPs1ResTmrMin_OFFSET 26 -#define D18F6x94_NbPs1ResTmrMin_WIDTH 3 -#define D18F6x94_NbPs1ResTmrMin_MASK 0x1c000000 -#define D18F6x94_NbPs0ResTmrMin_OFFSET 29 -#define D18F6x94_NbPs0ResTmrMin_WIDTH 3 -#define D18F6x94_NbPs0ResTmrMin_MASK 0xe0000000 - -/// D18F6x94 -typedef union { - struct { ///< - UINT32 CpuPstateThr:3 ; ///< - UINT32 CpuPstateThrEn:1 ; ///< - UINT32 NbPs1NoTransOnDma:1 ; ///< - UINT32 Reserved_19_5:15; ///< - UINT32 NbPsNonC0Timer:3 ; ///< - UINT32 NbPsC0Timer:3 ; ///< - UINT32 NbPs1ResTmrMin:3 ; ///< - UINT32 NbPs0ResTmrMin:3 ; ///< - } Field; ///< - UINT32 Value; ///< -} D18F6x94_STRUCT; - -// **** D18F6x98 Register Definition **** -// Address -#define D18F6x98_ADDRESS 0x98 - -// Type -#define D18F6x98_TYPE TYPE_D18F6 -// Field Data -#define D18F6x98_NbPsTransInFlight_OFFSET 0 -#define D18F6x98_NbPsTransInFlight_WIDTH 1 -#define D18F6x98_NbPsTransInFlight_MASK 0x1 -#define D18F6x98_NbPs1ActSts_OFFSET 1 -#define D18F6x98_NbPs1ActSts_WIDTH 1 -#define D18F6x98_NbPs1ActSts_MASK 0x2 -#define D18F6x98_NbPs1Act_OFFSET 2 -#define D18F6x98_NbPs1Act_WIDTH 1 -#define D18F6x98_NbPs1Act_MASK 0x4 -#define D18F6x98_Reserved_29_3_OFFSET 3 -#define D18F6x98_Reserved_29_3_WIDTH 27 -#define D18F6x98_Reserved_29_3_MASK 0x3ffffff8 -#define D18F6x98_NbPsCsrAccSel_OFFSET 30 -#define D18F6x98_NbPsCsrAccSel_WIDTH 1 -#define D18F6x98_NbPsCsrAccSel_MASK 0x40000000 -#define D18F6x98_NbPsDbgEn_OFFSET 31 -#define D18F6x98_NbPsDbgEn_WIDTH 1 -#define D18F6x98_NbPsDbgEn_MASK 0x80000000 - -/// D18F6x98 -typedef union { - struct { ///< - UINT32 NbPsTransInFlight:1 ; ///< - UINT32 NbPs1ActSts:1 ; ///< - UINT32 NbPs1Act:1 ; ///< - UINT32 Reserved_29_3:27; ///< - UINT32 NbPsCsrAccSel:1 ; ///< - UINT32 NbPsDbgEn:1 ; ///< - } Field; ///< - UINT32 Value; ///< -} D18F6x98_STRUCT; - -// **** D18F6x9C Register Definition **** -// Address -#define D18F6x9C_ADDRESS 0x9c - -// Type -#define D18F6x9C_TYPE TYPE_D18F6 -// Field Data -#define D18F6x9C_NclkRedDiv_OFFSET 0 -#define D18F6x9C_NclkRedDiv_WIDTH 7 -#define D18F6x9C_NclkRedDiv_MASK 0x7f -#define D18F6x9C_NclkRedSelfRefrAlways_OFFSET 7 -#define D18F6x9C_NclkRedSelfRefrAlways_WIDTH 1 -#define D18F6x9C_NclkRedSelfRefrAlways_MASK 0x80 -#define D18F6x9C_NclkRampWithDllRelock_OFFSET 8 -#define D18F6x9C_NclkRampWithDllRelock_WIDTH 1 -#define D18F6x9C_NclkRampWithDllRelock_MASK 0x100 -#define D18F6x9C_Reserved_31_9_OFFSET 9 -#define D18F6x9C_Reserved_31_9_WIDTH 23 -#define D18F6x9C_Reserved_31_9_MASK 0xfffffe00 - -/// D18F6x9C -typedef union { - struct { ///< - UINT32 NclkRedDiv:7 ; ///< - UINT32 NclkRedSelfRefrAlways:1 ; ///< - UINT32 NclkRampWithDllRelock:1 ; ///< - UINT32 Reserved_31_9:23; ///< - } Field; ///< - UINT32 Value; ///< -} D18F6x9C_STRUCT; - -// **** DxF0x00 Register Definition **** -// Address -#define DxF0x00_ADDRESS 0x0 - -// Type -#define DxF0x00_TYPE TYPE_D4F0 -// Field Data -#define DxF0x00_VendorID_OFFSET 0 -#define DxF0x00_VendorID_WIDTH 16 -#define DxF0x00_VendorID_MASK 0xffff -#define DxF0x00_DeviceID_OFFSET 16 -#define DxF0x00_DeviceID_WIDTH 16 -#define DxF0x00_DeviceID_MASK 0xffff0000 - -/// DxF0x00 -typedef union { - struct { ///< - UINT32 VendorID:16; ///< - UINT32 DeviceID:16; ///< - } Field; ///< - UINT32 Value; ///< -} DxF0x00_STRUCT; - -// **** DxF0x04 Register Definition **** -// Address -#define DxF0x04_ADDRESS 0x4 - -// Type -#define DxF0x04_TYPE TYPE_D4F0 -// Field Data -#define DxF0x04_IoAccessEn_OFFSET 0 -#define DxF0x04_IoAccessEn_WIDTH 1 -#define DxF0x04_IoAccessEn_MASK 0x1 -#define DxF0x04_MemAccessEn_OFFSET 1 -#define DxF0x04_MemAccessEn_WIDTH 1 -#define DxF0x04_MemAccessEn_MASK 0x2 -#define DxF0x04_BusMasterEn_OFFSET 2 -#define DxF0x04_BusMasterEn_WIDTH 1 -#define DxF0x04_BusMasterEn_MASK 0x4 -#define DxF0x04_SpecialCycleEn_OFFSET 3 -#define DxF0x04_SpecialCycleEn_WIDTH 1 -#define DxF0x04_SpecialCycleEn_MASK 0x8 -#define DxF0x04_MemWriteInvalidateEn_OFFSET 4 -#define DxF0x04_MemWriteInvalidateEn_WIDTH 1 -#define DxF0x04_MemWriteInvalidateEn_MASK 0x10 -#define DxF0x04_PalSnoopEn_OFFSET 5 -#define DxF0x04_PalSnoopEn_WIDTH 1 -#define DxF0x04_PalSnoopEn_MASK 0x20 -#define DxF0x04_ParityErrorEn_OFFSET 6 -#define DxF0x04_ParityErrorEn_WIDTH 1 -#define DxF0x04_ParityErrorEn_MASK 0x40 -#define DxF0x04_IdselStepping_OFFSET 7 -#define DxF0x04_IdselStepping_WIDTH 1 -#define DxF0x04_IdselStepping_MASK 0x80 -#define DxF0x04_SerrEn_OFFSET 8 -#define DxF0x04_SerrEn_WIDTH 1 -#define DxF0x04_SerrEn_MASK 0x100 -#define DxF0x04_FastB2BEn_OFFSET 9 -#define DxF0x04_FastB2BEn_WIDTH 1 -#define DxF0x04_FastB2BEn_MASK 0x200 -#define DxF0x04_IntDis_OFFSET 10 -#define DxF0x04_IntDis_WIDTH 1 -#define DxF0x04_IntDis_MASK 0x400 -#define DxF0x04_Reserved_18_11_OFFSET 11 -#define DxF0x04_Reserved_18_11_WIDTH 8 -#define DxF0x04_Reserved_18_11_MASK 0x7f800 -#define DxF0x04_IntStatus_OFFSET 19 -#define DxF0x04_IntStatus_WIDTH 1 -#define DxF0x04_IntStatus_MASK 0x80000 -#define DxF0x04_CapList_OFFSET 20 -#define DxF0x04_CapList_WIDTH 1 -#define DxF0x04_CapList_MASK 0x100000 -#define DxF0x04_PCI66En_OFFSET 21 -#define DxF0x04_PCI66En_WIDTH 1 -#define DxF0x04_PCI66En_MASK 0x200000 -#define DxF0x04_Reserved_22_22_OFFSET 22 -#define DxF0x04_Reserved_22_22_WIDTH 1 -#define DxF0x04_Reserved_22_22_MASK 0x400000 -#define DxF0x04_FastBackCapable_OFFSET 23 -#define DxF0x04_FastBackCapable_WIDTH 1 -#define DxF0x04_FastBackCapable_MASK 0x800000 -#define DxF0x04_MasterDataPerr_OFFSET 24 -#define DxF0x04_MasterDataPerr_WIDTH 1 -#define DxF0x04_MasterDataPerr_MASK 0x1000000 -#define DxF0x04_DevselTiming_OFFSET 25 -#define DxF0x04_DevselTiming_WIDTH 2 -#define DxF0x04_DevselTiming_MASK 0x6000000 -#define DxF0x04_SignaledTargetAbort_OFFSET 27 -#define DxF0x04_SignaledTargetAbort_WIDTH 1 -#define DxF0x04_SignaledTargetAbort_MASK 0x8000000 -#define DxF0x04_ReceivedTargetAbort_OFFSET 28 -#define DxF0x04_ReceivedTargetAbort_WIDTH 1 -#define DxF0x04_ReceivedTargetAbort_MASK 0x10000000 -#define DxF0x04_ReceivedMasterAbort_OFFSET 29 -#define DxF0x04_ReceivedMasterAbort_WIDTH 1 -#define DxF0x04_ReceivedMasterAbort_MASK 0x20000000 -#define DxF0x04_SignaledSystemError_OFFSET 30 -#define DxF0x04_SignaledSystemError_WIDTH 1 -#define DxF0x04_SignaledSystemError_MASK 0x40000000 -#define DxF0x04_ParityErrorDetected_OFFSET 31 -#define DxF0x04_ParityErrorDetected_WIDTH 1 -#define DxF0x04_ParityErrorDetected_MASK 0x80000000 - -/// DxF0x04 -typedef union { - struct { ///< - UINT32 IoAccessEn:1 ; ///< - UINT32 MemAccessEn:1 ; ///< - UINT32 BusMasterEn:1 ; ///< - UINT32 SpecialCycleEn:1 ; ///< - UINT32 MemWriteInvalidateEn:1 ; ///< - UINT32 PalSnoopEn:1 ; ///< - UINT32 ParityErrorEn:1 ; ///< - UINT32 IdselStepping:1 ; ///< - UINT32 SerrEn:1 ; ///< - UINT32 FastB2BEn:1 ; ///< - UINT32 IntDis:1 ; ///< - UINT32 Reserved_18_11:8 ; ///< - UINT32 IntStatus:1 ; ///< - UINT32 CapList:1 ; ///< - UINT32 PCI66En:1 ; ///< - UINT32 Reserved_22_22:1 ; ///< - UINT32 FastBackCapable:1 ; ///< - UINT32 MasterDataPerr:1 ; ///< - UINT32 DevselTiming:2 ; ///< - UINT32 SignaledTargetAbort:1 ; ///< - UINT32 ReceivedTargetAbort:1 ; ///< - UINT32 ReceivedMasterAbort:1 ; ///< - UINT32 SignaledSystemError:1 ; ///< - UINT32 ParityErrorDetected:1 ; ///< - } Field; ///< - UINT32 Value; ///< -} DxF0x04_STRUCT; - -// **** DxF0x08 Register Definition **** -// Address -#define DxF0x08_ADDRESS 0x8 - -// Type -#define DxF0x08_TYPE TYPE_D4F0 -// Field Data -#define DxF0x08_RevID_OFFSET 0 -#define DxF0x08_RevID_WIDTH 8 -#define DxF0x08_RevID_MASK 0xff -#define DxF0x08_ClassCode_OFFSET 8 -#define DxF0x08_ClassCode_WIDTH 24 -#define DxF0x08_ClassCode_MASK 0xffffff00 - -/// DxF0x08 -typedef union { - struct { ///< - UINT32 RevID:8 ; ///< - UINT32 ClassCode:24; ///< - } Field; ///< - UINT32 Value; ///< -} DxF0x08_STRUCT; - -// **** DxF0x0C Register Definition **** -// Address -#define DxF0x0C_ADDRESS 0xc - -// Type -#define DxF0x0C_TYPE TYPE_D4F0 -// Field Data -#define DxF0x0C_CacheLineSize_OFFSET 0 -#define DxF0x0C_CacheLineSize_WIDTH 8 -#define DxF0x0C_CacheLineSize_MASK 0xff -#define DxF0x0C_LatencyTimer_OFFSET 8 -#define DxF0x0C_LatencyTimer_WIDTH 8 -#define DxF0x0C_LatencyTimer_MASK 0xff00 -#define DxF0x0C_HeaderTypeReg_OFFSET 16 -#define DxF0x0C_HeaderTypeReg_WIDTH 8 -#define DxF0x0C_HeaderTypeReg_MASK 0xff0000 -#define DxF0x0C_BIST_OFFSET 24 -#define DxF0x0C_BIST_WIDTH 8 -#define DxF0x0C_BIST_MASK 0xff000000 - -/// DxF0x0C -typedef union { - struct { ///< - UINT32 CacheLineSize:8 ; ///< - UINT32 LatencyTimer:8 ; ///< - UINT32 HeaderTypeReg:8 ; ///< - UINT32 BIST:8 ; ///< - } Field; ///< - UINT32 Value; ///< -} DxF0x0C_STRUCT; - -// **** DxF0x18 Register Definition **** -// Address -#define DxF0x18_ADDRESS 0x18 - -// Type -#define DxF0x18_TYPE TYPE_D4F0 -// Field Data -#define DxF0x18_PrimaryBus_OFFSET 0 -#define DxF0x18_PrimaryBus_WIDTH 8 -#define DxF0x18_PrimaryBus_MASK 0xff -#define DxF0x18_SecondaryBus_OFFSET 8 -#define DxF0x18_SecondaryBus_WIDTH 8 -#define DxF0x18_SecondaryBus_MASK 0xff00 -#define DxF0x18_SubBusNumber_OFFSET 16 -#define DxF0x18_SubBusNumber_WIDTH 8 -#define DxF0x18_SubBusNumber_MASK 0xff0000 -#define DxF0x18_SecondaryLatencyTimer_OFFSET 24 -#define DxF0x18_SecondaryLatencyTimer_WIDTH 8 -#define DxF0x18_SecondaryLatencyTimer_MASK 0xff000000 - -/// DxF0x18 -typedef union { - struct { ///< - UINT32 PrimaryBus:8 ; ///< - UINT32 SecondaryBus:8 ; ///< - UINT32 SubBusNumber:8 ; ///< - UINT32 SecondaryLatencyTimer:8 ; ///< - } Field; ///< - UINT32 Value; ///< -} DxF0x18_STRUCT; - -// **** DxF0x1C Register Definition **** -// Address -#define DxF0x1C_ADDRESS 0x1c - -// Type -#define DxF0x1C_TYPE TYPE_D4F0 -// Field Data -#define DxF0x1C_Reserved_3_0_OFFSET 0 -#define DxF0x1C_Reserved_3_0_WIDTH 4 -#define DxF0x1C_Reserved_3_0_MASK 0xf -#define DxF0x1C_IOBase_15_12__OFFSET 4 -#define DxF0x1C_IOBase_15_12__WIDTH 4 -#define DxF0x1C_IOBase_15_12__MASK 0xf0 -#define DxF0x1C_Reserved_11_8_OFFSET 8 -#define DxF0x1C_Reserved_11_8_WIDTH 4 -#define DxF0x1C_Reserved_11_8_MASK 0xf00 -#define DxF0x1C_IOLimit_15_12__OFFSET 12 -#define DxF0x1C_IOLimit_15_12__WIDTH 4 -#define DxF0x1C_IOLimit_15_12__MASK 0xf000 -#define DxF0x1C_Reserved_20_16_OFFSET 16 -#define DxF0x1C_Reserved_20_16_WIDTH 5 -#define DxF0x1C_Reserved_20_16_MASK 0x1f0000 -#define DxF0x1C_PCI66En_OFFSET 21 -#define DxF0x1C_PCI66En_WIDTH 1 -#define DxF0x1C_PCI66En_MASK 0x200000 -#define DxF0x1C_Reserved_22_22_OFFSET 22 -#define DxF0x1C_Reserved_22_22_WIDTH 1 -#define DxF0x1C_Reserved_22_22_MASK 0x400000 -#define DxF0x1C_FastBackCapable_OFFSET 23 -#define DxF0x1C_FastBackCapable_WIDTH 1 -#define DxF0x1C_FastBackCapable_MASK 0x800000 -#define DxF0x1C_MasterDataPerr_OFFSET 24 -#define DxF0x1C_MasterDataPerr_WIDTH 1 -#define DxF0x1C_MasterDataPerr_MASK 0x1000000 -#define DxF0x1C_DevselTiming_OFFSET 25 -#define DxF0x1C_DevselTiming_WIDTH 2 -#define DxF0x1C_DevselTiming_MASK 0x6000000 -#define DxF0x1C_SignalTargetAbort_OFFSET 27 -#define DxF0x1C_SignalTargetAbort_WIDTH 1 -#define DxF0x1C_SignalTargetAbort_MASK 0x8000000 -#define DxF0x1C_ReceivedTargetAbort_OFFSET 28 -#define DxF0x1C_ReceivedTargetAbort_WIDTH 1 -#define DxF0x1C_ReceivedTargetAbort_MASK 0x10000000 -#define DxF0x1C_ReceivedMasterAbort_OFFSET 29 -#define DxF0x1C_ReceivedMasterAbort_WIDTH 1 -#define DxF0x1C_ReceivedMasterAbort_MASK 0x20000000 -#define DxF0x1C_ReceivedSystemError_OFFSET 30 -#define DxF0x1C_ReceivedSystemError_WIDTH 1 -#define DxF0x1C_ReceivedSystemError_MASK 0x40000000 -#define DxF0x1C_ParityErrorDetected_OFFSET 31 -#define DxF0x1C_ParityErrorDetected_WIDTH 1 -#define DxF0x1C_ParityErrorDetected_MASK 0x80000000 - -/// DxF0x1C -typedef union { - struct { ///< - UINT32 Reserved_3_0:4 ; ///< - UINT32 IOBase_15_12_:4 ; ///< - UINT32 Reserved_11_8:4 ; ///< - UINT32 IOLimit_15_12_:4 ; ///< - UINT32 Reserved_20_16:5 ; ///< - UINT32 PCI66En:1 ; ///< - UINT32 Reserved_22_22:1 ; ///< - UINT32 FastBackCapable:1 ; ///< - UINT32 MasterDataPerr:1 ; ///< - UINT32 DevselTiming:2 ; ///< - UINT32 SignalTargetAbort:1 ; ///< - UINT32 ReceivedTargetAbort:1 ; ///< - UINT32 ReceivedMasterAbort:1 ; ///< - UINT32 ReceivedSystemError:1 ; ///< - UINT32 ParityErrorDetected:1 ; ///< - } Field; ///< - UINT32 Value; ///< -} DxF0x1C_STRUCT; - -// **** DxF0x20 Register Definition **** -// Address -#define DxF0x20_ADDRESS 0x20 - -// Type -#define DxF0x20_TYPE TYPE_D4F0 -// Field Data -#define DxF0x20_Reserved_3_0_OFFSET 0 -#define DxF0x20_Reserved_3_0_WIDTH 4 -#define DxF0x20_Reserved_3_0_MASK 0xf -#define DxF0x20_MemBase_OFFSET 4 -#define DxF0x20_MemBase_WIDTH 12 -#define DxF0x20_MemBase_MASK 0xfff0 -#define DxF0x20_Reserved_19_16_OFFSET 16 -#define DxF0x20_Reserved_19_16_WIDTH 4 -#define DxF0x20_Reserved_19_16_MASK 0xf0000 -#define DxF0x20_MemLimit_OFFSET 20 -#define DxF0x20_MemLimit_WIDTH 12 -#define DxF0x20_MemLimit_MASK 0xfff00000 - -/// DxF0x20 -typedef union { - struct { ///< - UINT32 Reserved_3_0:4 ; ///< - UINT32 MemBase:12; ///< - UINT32 Reserved_19_16:4 ; ///< - UINT32 MemLimit:12; ///< - } Field; ///< - UINT32 Value; ///< -} DxF0x20_STRUCT; - -// **** DxF0x24 Register Definition **** -// Address -#define DxF0x24_ADDRESS 0x24 - -// Type -#define DxF0x24_TYPE TYPE_D4F0 -// Field Data -#define DxF0x24_PrefMemBaseR_OFFSET 0 -#define DxF0x24_PrefMemBaseR_WIDTH 4 -#define DxF0x24_PrefMemBaseR_MASK 0xf -#define DxF0x24_PrefMemBase_31_20__OFFSET 4 -#define DxF0x24_PrefMemBase_31_20__WIDTH 12 -#define DxF0x24_PrefMemBase_31_20__MASK 0xfff0 -#define DxF0x24_PrefMemLimitR_OFFSET 16 -#define DxF0x24_PrefMemLimitR_WIDTH 4 -#define DxF0x24_PrefMemLimitR_MASK 0xf0000 -#define DxF0x24_PrefMemLimit_OFFSET 20 -#define DxF0x24_PrefMemLimit_WIDTH 12 -#define DxF0x24_PrefMemLimit_MASK 0xfff00000 - -/// DxF0x24 -typedef union { - struct { ///< - UINT32 PrefMemBaseR:4 ; ///< - UINT32 PrefMemBase_31_20_:12; ///< - UINT32 PrefMemLimitR:4 ; ///< - UINT32 PrefMemLimit:12; ///< - } Field; ///< - UINT32 Value; ///< -} DxF0x24_STRUCT; - -// **** DxF0x28 Register Definition **** -// Address -#define DxF0x28_ADDRESS 0x28 - -// Type -#define DxF0x28_TYPE TYPE_D4F0 -// Field Data -#define DxF0x28_PrefMemBase_63_32__OFFSET 0 -#define DxF0x28_PrefMemBase_63_32__WIDTH 32 -#define DxF0x28_PrefMemBase_63_32__MASK 0xffffffff - -/// DxF0x28 -typedef union { - struct { ///< - UINT32 PrefMemBase_63_32_:32; ///< - } Field; ///< - UINT32 Value; ///< -} DxF0x28_STRUCT; - -// **** DxF0x2C Register Definition **** -// Address -#define DxF0x2C_ADDRESS 0x2c - -// Type -#define DxF0x2C_TYPE TYPE_D4F0 -// Field Data -#define DxF0x2C_PrefMemLimit_63_32__OFFSET 0 -#define DxF0x2C_PrefMemLimit_63_32__WIDTH 32 -#define DxF0x2C_PrefMemLimit_63_32__MASK 0xffffffff - -/// DxF0x2C -typedef union { - struct { ///< - UINT32 PrefMemLimit_63_32_:32; ///< - } Field; ///< - UINT32 Value; ///< -} DxF0x2C_STRUCT; - -// **** DxF0x30 Register Definition **** -// Address -#define DxF0x30_ADDRESS 0x30 - -// Type -#define DxF0x30_TYPE TYPE_D4F0 -// Field Data -#define DxF0x30_IOBase_31_16__OFFSET 0 -#define DxF0x30_IOBase_31_16__WIDTH 16 -#define DxF0x30_IOBase_31_16__MASK 0xffff -#define DxF0x30_IOLimit_31_16__OFFSET 16 -#define DxF0x30_IOLimit_31_16__WIDTH 16 -#define DxF0x30_IOLimit_31_16__MASK 0xffff0000 - -/// DxF0x30 -typedef union { - struct { ///< - UINT32 IOBase_31_16_:16; ///< - UINT32 IOLimit_31_16_:16; ///< - } Field; ///< - UINT32 Value; ///< -} DxF0x30_STRUCT; - -// **** DxF0x34 Register Definition **** -// Address -#define DxF0x34_ADDRESS 0x34 - -// Type -#define DxF0x34_TYPE TYPE_D4F0 -// Field Data -#define DxF0x34_CapPtr_OFFSET 0 -#define DxF0x34_CapPtr_WIDTH 8 -#define DxF0x34_CapPtr_MASK 0xff -#define DxF0x34_Reserved_31_8_OFFSET 8 -#define DxF0x34_Reserved_31_8_WIDTH 24 -#define DxF0x34_Reserved_31_8_MASK 0xffffff00 - -/// DxF0x34 -typedef union { - struct { ///< - UINT32 CapPtr:8 ; ///< - UINT32 Reserved_31_8:24; ///< - } Field; ///< - UINT32 Value; ///< -} DxF0x34_STRUCT; - -// **** DxF0x3C Register Definition **** -// Address -#define DxF0x3C_ADDRESS 0x3c - -// Type -#define DxF0x3C_TYPE TYPE_D4F0 -// Field Data -#define DxF0x3C_IntLine_OFFSET 0 -#define DxF0x3C_IntLine_WIDTH 8 -#define DxF0x3C_IntLine_MASK 0xff -#define DxF0x3C_IntPin_OFFSET 8 -#define DxF0x3C_IntPin_WIDTH 3 -#define DxF0x3C_IntPin_MASK 0x700 -#define DxF0x3C_IntPinR_OFFSET 11 -#define DxF0x3C_IntPinR_WIDTH 5 -#define DxF0x3C_IntPinR_MASK 0xf800 -#define DxF0x3C_ParityResponseEn_OFFSET 16 -#define DxF0x3C_ParityResponseEn_WIDTH 1 -#define DxF0x3C_ParityResponseEn_MASK 0x10000 -#define DxF0x3C_SerrEn_OFFSET 17 -#define DxF0x3C_SerrEn_WIDTH 1 -#define DxF0x3C_SerrEn_MASK 0x20000 -#define DxF0x3C_IsaEn_OFFSET 18 -#define DxF0x3C_IsaEn_WIDTH 1 -#define DxF0x3C_IsaEn_MASK 0x40000 -#define DxF0x3C_VgaEn_OFFSET 19 -#define DxF0x3C_VgaEn_WIDTH 1 -#define DxF0x3C_VgaEn_MASK 0x80000 -#define DxF0x3C_Vga16En_OFFSET 20 -#define DxF0x3C_Vga16En_WIDTH 1 -#define DxF0x3C_Vga16En_MASK 0x100000 -#define DxF0x3C_MasterAbortMode_OFFSET 21 -#define DxF0x3C_MasterAbortMode_WIDTH 1 -#define DxF0x3C_MasterAbortMode_MASK 0x200000 -#define DxF0x3C_SecondaryBusReset_OFFSET 22 -#define DxF0x3C_SecondaryBusReset_WIDTH 1 -#define DxF0x3C_SecondaryBusReset_MASK 0x400000 -#define DxF0x3C_FastB2BCap_OFFSET 23 -#define DxF0x3C_FastB2BCap_WIDTH 1 -#define DxF0x3C_FastB2BCap_MASK 0x800000 -#define DxF0x3C_Reserved_31_24_OFFSET 24 -#define DxF0x3C_Reserved_31_24_WIDTH 8 -#define DxF0x3C_Reserved_31_24_MASK 0xff000000 - -/// DxF0x3C -typedef union { - struct { ///< - UINT32 IntLine:8 ; ///< - UINT32 IntPin:3 ; ///< - UINT32 IntPinR:5 ; ///< - UINT32 ParityResponseEn:1 ; ///< - UINT32 SerrEn:1 ; ///< - UINT32 IsaEn:1 ; ///< - UINT32 VgaEn:1 ; ///< - UINT32 Vga16En:1 ; ///< - UINT32 MasterAbortMode:1 ; ///< - UINT32 SecondaryBusReset:1 ; ///< - UINT32 FastB2BCap:1 ; ///< - UINT32 Reserved_31_24:8 ; ///< - } Field; ///< - UINT32 Value; ///< -} DxF0x3C_STRUCT; - -// **** DxF0x50 Register Definition **** -// Address -#define DxF0x50_ADDRESS 0x50 - -// Type -#define DxF0x50_TYPE TYPE_D4F0 -// Field Data -#define DxF0x50_CapID_OFFSET 0 -#define DxF0x50_CapID_WIDTH 8 -#define DxF0x50_CapID_MASK 0xff -#define DxF0x50_NextPtr_OFFSET 8 -#define DxF0x50_NextPtr_WIDTH 8 -#define DxF0x50_NextPtr_MASK 0xff00 -#define DxF0x50_Version_OFFSET 16 -#define DxF0x50_Version_WIDTH 3 -#define DxF0x50_Version_MASK 0x70000 -#define DxF0x50_PmeClock_OFFSET 19 -#define DxF0x50_PmeClock_WIDTH 1 -#define DxF0x50_PmeClock_MASK 0x80000 -#define DxF0x50_Reserved_20_20_OFFSET 20 -#define DxF0x50_Reserved_20_20_WIDTH 1 -#define DxF0x50_Reserved_20_20_MASK 0x100000 -#define DxF0x50_DevSpecificInit_OFFSET 21 -#define DxF0x50_DevSpecificInit_WIDTH 1 -#define DxF0x50_DevSpecificInit_MASK 0x200000 -#define DxF0x50_AuxCurrent_OFFSET 22 -#define DxF0x50_AuxCurrent_WIDTH 3 -#define DxF0x50_AuxCurrent_MASK 0x1c00000 -#define DxF0x50_D1Support_OFFSET 25 -#define DxF0x50_D1Support_WIDTH 1 -#define DxF0x50_D1Support_MASK 0x2000000 -#define DxF0x50_D2Support_OFFSET 26 -#define DxF0x50_D2Support_WIDTH 1 -#define DxF0x50_D2Support_MASK 0x4000000 -#define DxF0x50_PmeSupport_OFFSET 27 -#define DxF0x50_PmeSupport_WIDTH 5 -#define DxF0x50_PmeSupport_MASK 0xf8000000 - -/// DxF0x50 -typedef union { - struct { ///< - UINT32 CapID:8 ; ///< - UINT32 NextPtr:8 ; ///< - UINT32 Version:3 ; ///< - UINT32 PmeClock:1 ; ///< - UINT32 Reserved_20_20:1 ; ///< - UINT32 DevSpecificInit:1 ; ///< - UINT32 AuxCurrent:3 ; ///< - UINT32 D1Support:1 ; ///< - UINT32 D2Support:1 ; ///< - UINT32 PmeSupport:5 ; ///< - } Field; ///< - UINT32 Value; ///< -} DxF0x50_STRUCT; - -// **** DxF0x54 Register Definition **** -// Address -#define DxF0x54_ADDRESS 0x54 - -// Type -#define DxF0x54_TYPE TYPE_D4F0 -// Field Data -#define DxF0x54_PowerState_OFFSET 0 -#define DxF0x54_PowerState_WIDTH 2 -#define DxF0x54_PowerState_MASK 0x3 -#define DxF0x54_Reserved_2_2_OFFSET 2 -#define DxF0x54_Reserved_2_2_WIDTH 1 -#define DxF0x54_Reserved_2_2_MASK 0x4 -#define DxF0x54_NoSoftReset_OFFSET 3 -#define DxF0x54_NoSoftReset_WIDTH 1 -#define DxF0x54_NoSoftReset_MASK 0x8 -#define DxF0x54_Reserved_7_4_OFFSET 4 -#define DxF0x54_Reserved_7_4_WIDTH 4 -#define DxF0x54_Reserved_7_4_MASK 0xf0 -#define DxF0x54_PmeEn_OFFSET 8 -#define DxF0x54_PmeEn_WIDTH 1 -#define DxF0x54_PmeEn_MASK 0x100 -#define DxF0x54_DataSelect_OFFSET 9 -#define DxF0x54_DataSelect_WIDTH 4 -#define DxF0x54_DataSelect_MASK 0x1e00 -#define DxF0x54_DataScale_OFFSET 13 -#define DxF0x54_DataScale_WIDTH 2 -#define DxF0x54_DataScale_MASK 0x6000 -#define DxF0x54_PmeStatus_OFFSET 15 -#define DxF0x54_PmeStatus_WIDTH 1 -#define DxF0x54_PmeStatus_MASK 0x8000 -#define DxF0x54_Reserved_21_16_OFFSET 16 -#define DxF0x54_Reserved_21_16_WIDTH 6 -#define DxF0x54_Reserved_21_16_MASK 0x3f0000 -#define DxF0x54_B2B3Support_OFFSET 22 -#define DxF0x54_B2B3Support_WIDTH 1 -#define DxF0x54_B2B3Support_MASK 0x400000 -#define DxF0x54_BusPwrEn_OFFSET 23 -#define DxF0x54_BusPwrEn_WIDTH 1 -#define DxF0x54_BusPwrEn_MASK 0x800000 -#define DxF0x54_PmeData_OFFSET 24 -#define DxF0x54_PmeData_WIDTH 8 -#define DxF0x54_PmeData_MASK 0xff000000 - -/// DxF0x54 -typedef union { - struct { ///< - UINT32 PowerState:2 ; ///< - UINT32 Reserved_2_2:1 ; ///< - UINT32 NoSoftReset:1 ; ///< - UINT32 Reserved_7_4:4 ; ///< - UINT32 PmeEn:1 ; ///< - UINT32 DataSelect:4 ; ///< - UINT32 DataScale:2 ; ///< - UINT32 PmeStatus:1 ; ///< - UINT32 Reserved_21_16:6 ; ///< - UINT32 B2B3Support:1 ; ///< - UINT32 BusPwrEn:1 ; ///< - UINT32 PmeData:8 ; ///< - } Field; ///< - UINT32 Value; ///< -} DxF0x54_STRUCT; - -// **** DxF0x58 Register Definition **** -// Address -#define DxF0x58_ADDRESS 0x58 - -// Type -#define DxF0x58_TYPE TYPE_D4F0 -// Field Data -#define DxF0x58_CapID_OFFSET 0 -#define DxF0x58_CapID_WIDTH 8 -#define DxF0x58_CapID_MASK 0xff -#define DxF0x58_NextPtr_OFFSET 8 -#define DxF0x58_NextPtr_WIDTH 8 -#define DxF0x58_NextPtr_MASK 0xff00 -#define DxF0x58_Version_OFFSET 16 -#define DxF0x58_Version_WIDTH 4 -#define DxF0x58_Version_MASK 0xf0000 -#define DxF0x58_DeviceType_OFFSET 20 -#define DxF0x58_DeviceType_WIDTH 4 -#define DxF0x58_DeviceType_MASK 0xf00000 -#define DxF0x58_SlotImplemented_OFFSET 24 -#define DxF0x58_SlotImplemented_WIDTH 1 -#define DxF0x58_SlotImplemented_MASK 0x1000000 -#define DxF0x58_IntMessageNum_OFFSET 25 -#define DxF0x58_IntMessageNum_WIDTH 5 -#define DxF0x58_IntMessageNum_MASK 0x3e000000 -#define DxF0x58_Reserved_31_30_OFFSET 30 -#define DxF0x58_Reserved_31_30_WIDTH 2 -#define DxF0x58_Reserved_31_30_MASK 0xc0000000 - -/// DxF0x58 -typedef union { - struct { ///< - UINT32 CapID:8 ; ///< - UINT32 NextPtr:8 ; ///< - UINT32 Version:4 ; ///< - UINT32 DeviceType:4 ; ///< - UINT32 SlotImplemented:1 ; ///< - UINT32 IntMessageNum:5 ; ///< - UINT32 Reserved_31_30:2 ; ///< - } Field; ///< - UINT32 Value; ///< -} DxF0x58_STRUCT; - -// **** DxF0x5C Register Definition **** -// Address -#define DxF0x5C_ADDRESS 0x5c - -// Type -#define DxF0x5C_TYPE TYPE_D4F0 -// Field Data -#define DxF0x5C_MaxPayloadSupport_OFFSET 0 -#define DxF0x5C_MaxPayloadSupport_WIDTH 3 -#define DxF0x5C_MaxPayloadSupport_MASK 0x7 -#define DxF0x5C_PhantomFunc_OFFSET 3 -#define DxF0x5C_PhantomFunc_WIDTH 2 -#define DxF0x5C_PhantomFunc_MASK 0x18 -#define DxF0x5C_ExtendedTag_OFFSET 5 -#define DxF0x5C_ExtendedTag_WIDTH 1 -#define DxF0x5C_ExtendedTag_MASK 0x20 -#define DxF0x5C_L0SAcceptableLatency_OFFSET 6 -#define DxF0x5C_L0SAcceptableLatency_WIDTH 3 -#define DxF0x5C_L0SAcceptableLatency_MASK 0x1c0 -#define DxF0x5C_L1AcceptableLatency_OFFSET 9 -#define DxF0x5C_L1AcceptableLatency_WIDTH 3 -#define DxF0x5C_L1AcceptableLatency_MASK 0xe00 -#define DxF0x5C_Reserved_14_12_OFFSET 12 -#define DxF0x5C_Reserved_14_12_WIDTH 3 -#define DxF0x5C_Reserved_14_12_MASK 0x7000 -#define DxF0x5C_RoleBasedErrReporting_OFFSET 15 -#define DxF0x5C_RoleBasedErrReporting_WIDTH 1 -#define DxF0x5C_RoleBasedErrReporting_MASK 0x8000 -#define DxF0x5C_Reserved_17_16_OFFSET 16 -#define DxF0x5C_Reserved_17_16_WIDTH 2 -#define DxF0x5C_Reserved_17_16_MASK 0x30000 -#define DxF0x5C_CapturedSlotPowerLimit_OFFSET 18 -#define DxF0x5C_CapturedSlotPowerLimit_WIDTH 8 -#define DxF0x5C_CapturedSlotPowerLimit_MASK 0x3fc0000 -#define DxF0x5C_CapturedSlotPowerScale_OFFSET 26 -#define DxF0x5C_CapturedSlotPowerScale_WIDTH 2 -#define DxF0x5C_CapturedSlotPowerScale_MASK 0xc000000 -#define DxF0x5C_FlrCapable_OFFSET 28 -#define DxF0x5C_FlrCapable_WIDTH 1 -#define DxF0x5C_FlrCapable_MASK 0x10000000 -#define DxF0x5C_Reserved_31_29_OFFSET 29 -#define DxF0x5C_Reserved_31_29_WIDTH 3 -#define DxF0x5C_Reserved_31_29_MASK 0xe0000000 - -/// DxF0x5C -typedef union { - struct { ///< - UINT32 MaxPayloadSupport:3 ; ///< - UINT32 PhantomFunc:2 ; ///< - UINT32 ExtendedTag:1 ; ///< - UINT32 L0SAcceptableLatency:3 ; ///< - UINT32 L1AcceptableLatency:3 ; ///< - UINT32 Reserved_14_12:3 ; ///< - UINT32 RoleBasedErrReporting:1 ; ///< - UINT32 Reserved_17_16:2 ; ///< - UINT32 CapturedSlotPowerLimit:8 ; ///< - UINT32 CapturedSlotPowerScale:2 ; ///< - UINT32 FlrCapable:1 ; ///< - UINT32 Reserved_31_29:3 ; ///< - } Field; ///< - UINT32 Value; ///< -} DxF0x5C_STRUCT; - -// **** DxF0x60 Register Definition **** -// Address -#define DxF0x60_ADDRESS 0x60 - -// Type -#define DxF0x60_TYPE TYPE_D4F0 -// Field Data -#define DxF0x60_CorrErrEn_OFFSET 0 -#define DxF0x60_CorrErrEn_WIDTH 1 -#define DxF0x60_CorrErrEn_MASK 0x1 -#define DxF0x60_NonFatalErrEn_OFFSET 1 -#define DxF0x60_NonFatalErrEn_WIDTH 1 -#define DxF0x60_NonFatalErrEn_MASK 0x2 -#define DxF0x60_FatalErrEn_OFFSET 2 -#define DxF0x60_FatalErrEn_WIDTH 1 -#define DxF0x60_FatalErrEn_MASK 0x4 -#define DxF0x60_UsrReportEn_OFFSET 3 -#define DxF0x60_UsrReportEn_WIDTH 1 -#define DxF0x60_UsrReportEn_MASK 0x8 -#define DxF0x60_RelaxedOrdEn_OFFSET 4 -#define DxF0x60_RelaxedOrdEn_WIDTH 1 -#define DxF0x60_RelaxedOrdEn_MASK 0x10 -#define DxF0x60_MaxPayloadSize_OFFSET 5 -#define DxF0x60_MaxPayloadSize_WIDTH 3 -#define DxF0x60_MaxPayloadSize_MASK 0xe0 -#define DxF0x60_ExtendedTagEn_OFFSET 8 -#define DxF0x60_ExtendedTagEn_WIDTH 1 -#define DxF0x60_ExtendedTagEn_MASK 0x100 -#define DxF0x60_PhantomFuncEn_OFFSET 9 -#define DxF0x60_PhantomFuncEn_WIDTH 1 -#define DxF0x60_PhantomFuncEn_MASK 0x200 -#define DxF0x60_AuxPowerPmEn_OFFSET 10 -#define DxF0x60_AuxPowerPmEn_WIDTH 1 -#define DxF0x60_AuxPowerPmEn_MASK 0x400 -#define DxF0x60_NoSnoopEnable_OFFSET 11 -#define DxF0x60_NoSnoopEnable_WIDTH 1 -#define DxF0x60_NoSnoopEnable_MASK 0x800 -#define DxF0x60_MaxRequestSize_OFFSET 12 -#define DxF0x60_MaxRequestSize_WIDTH 3 -#define DxF0x60_MaxRequestSize_MASK 0x7000 -#define DxF0x60_BridgeCfgRetryEn_OFFSET 15 -#define DxF0x60_BridgeCfgRetryEn_WIDTH 1 -#define DxF0x60_BridgeCfgRetryEn_MASK 0x8000 -#define DxF0x60_CorrErr_OFFSET 16 -#define DxF0x60_CorrErr_WIDTH 1 -#define DxF0x60_CorrErr_MASK 0x10000 -#define DxF0x60_NonFatalErr_OFFSET 17 -#define DxF0x60_NonFatalErr_WIDTH 1 -#define DxF0x60_NonFatalErr_MASK 0x20000 -#define DxF0x60_FatalErr_OFFSET 18 -#define DxF0x60_FatalErr_WIDTH 1 -#define DxF0x60_FatalErr_MASK 0x40000 -#define DxF0x60_UsrDetected_OFFSET 19 -#define DxF0x60_UsrDetected_WIDTH 1 -#define DxF0x60_UsrDetected_MASK 0x80000 -#define DxF0x60_AuxPwr_OFFSET 20 -#define DxF0x60_AuxPwr_WIDTH 1 -#define DxF0x60_AuxPwr_MASK 0x100000 -#define DxF0x60_TransactionsPending_OFFSET 21 -#define DxF0x60_TransactionsPending_WIDTH 1 -#define DxF0x60_TransactionsPending_MASK 0x200000 -#define DxF0x60_Reserved_31_22_OFFSET 22 -#define DxF0x60_Reserved_31_22_WIDTH 10 -#define DxF0x60_Reserved_31_22_MASK 0xffc00000 - -/// DxF0x60 -typedef union { - struct { ///< - UINT32 CorrErrEn:1 ; ///< - UINT32 NonFatalErrEn:1 ; ///< - UINT32 FatalErrEn:1 ; ///< - UINT32 UsrReportEn:1 ; ///< - UINT32 RelaxedOrdEn:1 ; ///< - UINT32 MaxPayloadSize:3 ; ///< - UINT32 ExtendedTagEn:1 ; ///< - UINT32 PhantomFuncEn:1 ; ///< - UINT32 AuxPowerPmEn:1 ; ///< - UINT32 NoSnoopEnable:1 ; ///< - UINT32 MaxRequestSize:3 ; ///< - UINT32 BridgeCfgRetryEn:1 ; ///< - UINT32 CorrErr:1 ; ///< - UINT32 NonFatalErr:1 ; ///< - UINT32 FatalErr:1 ; ///< - UINT32 UsrDetected:1 ; ///< - UINT32 AuxPwr:1 ; ///< - UINT32 TransactionsPending:1 ; ///< - UINT32 Reserved_31_22:10; ///< - } Field; ///< - UINT32 Value; ///< -} DxF0x60_STRUCT; - -// **** DxF0x64 Register Definition **** -// Address -#define DxF0x64_ADDRESS 0x64 - -// Type -#define DxF0x64_TYPE TYPE_D4F0 -// Field Data -#define DxF0x64_LinkSpeed_OFFSET 0 -#define DxF0x64_LinkSpeed_WIDTH 4 -#define DxF0x64_LinkSpeed_MASK 0xf -#define DxF0x64_LinkWidth_OFFSET 4 -#define DxF0x64_LinkWidth_WIDTH 6 -#define DxF0x64_LinkWidth_MASK 0x3f0 -#define DxF0x64_PMSupport_OFFSET 10 -#define DxF0x64_PMSupport_WIDTH 2 -#define DxF0x64_PMSupport_MASK 0xc00 -#define DxF0x64_L0sExitLatency_OFFSET 12 -#define DxF0x64_L0sExitLatency_WIDTH 3 -#define DxF0x64_L0sExitLatency_MASK 0x7000 -#define DxF0x64_L1ExitLatency_OFFSET 15 -#define DxF0x64_L1ExitLatency_WIDTH 3 -#define DxF0x64_L1ExitLatency_MASK 0x38000 -#define DxF0x64_ClockPowerManagement_OFFSET 18 -#define DxF0x64_ClockPowerManagement_WIDTH 1 -#define DxF0x64_ClockPowerManagement_MASK 0x40000 -#define DxF0x64_Reserved_19_19_OFFSET 19 -#define DxF0x64_Reserved_19_19_WIDTH 1 -#define DxF0x64_Reserved_19_19_MASK 0x80000 -#define DxF0x64_DlActiveReportingCapable_OFFSET 20 -#define DxF0x64_DlActiveReportingCapable_WIDTH 1 -#define DxF0x64_DlActiveReportingCapable_MASK 0x100000 -#define DxF0x64_LinkBWNotificationCap_OFFSET 21 -#define DxF0x64_LinkBWNotificationCap_WIDTH 1 -#define DxF0x64_LinkBWNotificationCap_MASK 0x200000 -#define DxF0x64_Reserved_23_22_OFFSET 22 -#define DxF0x64_Reserved_23_22_WIDTH 2 -#define DxF0x64_Reserved_23_22_MASK 0xc00000 -#define DxF0x64_PortNumber_OFFSET 24 -#define DxF0x64_PortNumber_WIDTH 8 -#define DxF0x64_PortNumber_MASK 0xff000000 - -/// DxF0x64 -typedef union { - struct { ///< - UINT32 LinkSpeed:4 ; ///< - UINT32 LinkWidth:6 ; ///< - UINT32 PMSupport:2 ; ///< - UINT32 L0sExitLatency:3 ; ///< - UINT32 L1ExitLatency:3 ; ///< - UINT32 ClockPowerManagement:1 ; ///< - UINT32 Reserved_19_19:1 ; ///< - UINT32 DlActiveReportingCapable:1 ; ///< - UINT32 LinkBWNotificationCap:1 ; ///< - UINT32 Reserved_23_22:2 ; ///< - UINT32 PortNumber:8 ; ///< - } Field; ///< - UINT32 Value; ///< -} DxF0x64_STRUCT; - -// **** DxF0x68 Register Definition **** -// Address -#define DxF0x68_ADDRESS 0x68 - -// Type -#define DxF0x68_TYPE TYPE_D4F0 -// Field Data -#define DxF0x68_PmControl_OFFSET 0 -#define DxF0x68_PmControl_WIDTH 2 -#define DxF0x68_PmControl_MASK 0x3 -#define DxF0x68_Reserved_2_2_OFFSET 2 -#define DxF0x68_Reserved_2_2_WIDTH 1 -#define DxF0x68_Reserved_2_2_MASK 0x4 -#define DxF0x68_ReadCplBoundary_OFFSET 3 -#define DxF0x68_ReadCplBoundary_WIDTH 1 -#define DxF0x68_ReadCplBoundary_MASK 0x8 -#define DxF0x68_LinkDis_OFFSET 4 -#define DxF0x68_LinkDis_WIDTH 1 -#define DxF0x68_LinkDis_MASK 0x10 -#define DxF0x68_RetrainLink_OFFSET 5 -#define DxF0x68_RetrainLink_WIDTH 1 -#define DxF0x68_RetrainLink_MASK 0x20 -#define DxF0x68_CommonClockCfg_OFFSET 6 -#define DxF0x68_CommonClockCfg_WIDTH 1 -#define DxF0x68_CommonClockCfg_MASK 0x40 -#define DxF0x68_ExtendedSync_OFFSET 7 -#define DxF0x68_ExtendedSync_WIDTH 1 -#define DxF0x68_ExtendedSync_MASK 0x80 -#define DxF0x68_ClockPowerManagementEn_OFFSET 8 -#define DxF0x68_ClockPowerManagementEn_WIDTH 1 -#define DxF0x68_ClockPowerManagementEn_MASK 0x100 -#define DxF0x68_HWAutonomousWidthDisable_OFFSET 9 -#define DxF0x68_HWAutonomousWidthDisable_WIDTH 1 -#define DxF0x68_HWAutonomousWidthDisable_MASK 0x200 -#define DxF0x68_LinkBWManagementEn_OFFSET 10 -#define DxF0x68_LinkBWManagementEn_WIDTH 1 -#define DxF0x68_LinkBWManagementEn_MASK 0x400 -#define DxF0x68_LinkAutonomousBWIntEn_OFFSET 11 -#define DxF0x68_LinkAutonomousBWIntEn_WIDTH 1 -#define DxF0x68_LinkAutonomousBWIntEn_MASK 0x800 -#define DxF0x68_Reserved_15_12_OFFSET 12 -#define DxF0x68_Reserved_15_12_WIDTH 4 -#define DxF0x68_Reserved_15_12_MASK 0xf000 -#define DxF0x68_LinkSpeed_OFFSET 16 -#define DxF0x68_LinkSpeed_WIDTH 4 -#define DxF0x68_LinkSpeed_MASK 0xf0000 -#define DxF0x68_NegotiatedLinkWidth_OFFSET 20 -#define DxF0x68_NegotiatedLinkWidth_WIDTH 6 -#define DxF0x68_NegotiatedLinkWidth_MASK 0x3f00000 -#define DxF0x68_Reserved_26_26_OFFSET 26 -#define DxF0x68_Reserved_26_26_WIDTH 1 -#define DxF0x68_Reserved_26_26_MASK 0x4000000 -#define DxF0x68_LinkTraining_OFFSET 27 -#define DxF0x68_LinkTraining_WIDTH 1 -#define DxF0x68_LinkTraining_MASK 0x8000000 -#define DxF0x68_SlotClockCfg_OFFSET 28 -#define DxF0x68_SlotClockCfg_WIDTH 1 -#define DxF0x68_SlotClockCfg_MASK 0x10000000 -#define DxF0x68_DlActive_OFFSET 29 -#define DxF0x68_DlActive_WIDTH 1 -#define DxF0x68_DlActive_MASK 0x20000000 -#define DxF0x68_LinkBWManagementStatus_OFFSET 30 -#define DxF0x68_LinkBWManagementStatus_WIDTH 1 -#define DxF0x68_LinkBWManagementStatus_MASK 0x40000000 -#define DxF0x68_LinkAutonomousBWStatus_OFFSET 31 -#define DxF0x68_LinkAutonomousBWStatus_WIDTH 1 -#define DxF0x68_LinkAutonomousBWStatus_MASK 0x80000000 - -/// DxF0x68 -typedef union { - struct { ///< - UINT32 PmControl:2 ; ///< - UINT32 Reserved_2_2:1 ; ///< - UINT32 ReadCplBoundary:1 ; ///< - UINT32 LinkDis:1 ; ///< - UINT32 RetrainLink:1 ; ///< - UINT32 CommonClockCfg:1 ; ///< - UINT32 ExtendedSync:1 ; ///< - UINT32 ClockPowerManagementEn:1 ; ///< - UINT32 HWAutonomousWidthDisable:1 ; ///< - UINT32 LinkBWManagementEn:1 ; ///< - UINT32 LinkAutonomousBWIntEn:1 ; ///< - UINT32 Reserved_15_12:4 ; ///< - UINT32 LinkSpeed:4 ; ///< - UINT32 NegotiatedLinkWidth:6 ; ///< - UINT32 Reserved_26_26:1 ; ///< - UINT32 LinkTraining:1 ; ///< - UINT32 SlotClockCfg:1 ; ///< - UINT32 DlActive:1 ; ///< - UINT32 LinkBWManagementStatus:1 ; ///< - UINT32 LinkAutonomousBWStatus:1 ; ///< - } Field; ///< - UINT32 Value; ///< -} DxF0x68_STRUCT; - -// **** DxF0x6C Register Definition **** -// Address -#define DxF0x6C_ADDRESS 0x6c - -// Type -#define DxF0x6C_TYPE TYPE_D4F0 -// Field Data -#define DxF0x6C_AttnButtonPresent_OFFSET 0 -#define DxF0x6C_AttnButtonPresent_WIDTH 1 -#define DxF0x6C_AttnButtonPresent_MASK 0x1 -#define DxF0x6C_PwrControllerPresent_OFFSET 1 -#define DxF0x6C_PwrControllerPresent_WIDTH 1 -#define DxF0x6C_PwrControllerPresent_MASK 0x2 -#define DxF0x6C_MrlSensorPresent_OFFSET 2 -#define DxF0x6C_MrlSensorPresent_WIDTH 1 -#define DxF0x6C_MrlSensorPresent_MASK 0x4 -#define DxF0x6C_AttnIndicatorPresent_OFFSET 3 -#define DxF0x6C_AttnIndicatorPresent_WIDTH 1 -#define DxF0x6C_AttnIndicatorPresent_MASK 0x8 -#define DxF0x6C_PwrIndicatorPresent_OFFSET 4 -#define DxF0x6C_PwrIndicatorPresent_WIDTH 1 -#define DxF0x6C_PwrIndicatorPresent_MASK 0x10 -#define DxF0x6C_HotplugSurprise_OFFSET 5 -#define DxF0x6C_HotplugSurprise_WIDTH 1 -#define DxF0x6C_HotplugSurprise_MASK 0x20 -#define DxF0x6C_HotplugCapable_OFFSET 6 -#define DxF0x6C_HotplugCapable_WIDTH 1 -#define DxF0x6C_HotplugCapable_MASK 0x40 -#define DxF0x6C_SlotPwrLimitValue_OFFSET 7 -#define DxF0x6C_SlotPwrLimitValue_WIDTH 8 -#define DxF0x6C_SlotPwrLimitValue_MASK 0x7f80 -#define DxF0x6C_SlotPwrLimitScale_OFFSET 15 -#define DxF0x6C_SlotPwrLimitScale_WIDTH 2 -#define DxF0x6C_SlotPwrLimitScale_MASK 0x18000 -#define DxF0x6C_ElecMechIlPresent_OFFSET 17 -#define DxF0x6C_ElecMechIlPresent_WIDTH 1 -#define DxF0x6C_ElecMechIlPresent_MASK 0x20000 -#define DxF0x6C_NoCmdCplSupport_OFFSET 18 -#define DxF0x6C_NoCmdCplSupport_WIDTH 1 -#define DxF0x6C_NoCmdCplSupport_MASK 0x40000 -#define DxF0x6C_PhysicalSlotNumber_OFFSET 19 -#define DxF0x6C_PhysicalSlotNumber_WIDTH 13 -#define DxF0x6C_PhysicalSlotNumber_MASK 0xfff80000 - -/// DxF0x6C -typedef union { - struct { ///< - UINT32 AttnButtonPresent:1 ; ///< - UINT32 PwrControllerPresent:1 ; ///< - UINT32 MrlSensorPresent:1 ; ///< - UINT32 AttnIndicatorPresent:1 ; ///< - UINT32 PwrIndicatorPresent:1 ; ///< - UINT32 HotplugSurprise:1 ; ///< - UINT32 HotplugCapable:1 ; ///< - UINT32 SlotPwrLimitValue:8 ; ///< - UINT32 SlotPwrLimitScale:2 ; ///< - UINT32 ElecMechIlPresent:1 ; ///< - UINT32 NoCmdCplSupport:1 ; ///< - UINT32 PhysicalSlotNumber:13; ///< - } Field; ///< - UINT32 Value; ///< -} DxF0x6C_STRUCT; - -// **** DxF0x70 Register Definition **** -// Address -#define DxF0x70_ADDRESS 0x70 - -// Type -#define DxF0x70_TYPE TYPE_D4F0 -// Field Data -#define DxF0x70_AttnButtonPressedEn_OFFSET 0 -#define DxF0x70_AttnButtonPressedEn_WIDTH 1 -#define DxF0x70_AttnButtonPressedEn_MASK 0x1 -#define DxF0x70_PwrFaultDetectedEn_OFFSET 1 -#define DxF0x70_PwrFaultDetectedEn_WIDTH 1 -#define DxF0x70_PwrFaultDetectedEn_MASK 0x2 -#define DxF0x70_MrlSensorChangedEn_OFFSET 2 -#define DxF0x70_MrlSensorChangedEn_WIDTH 1 -#define DxF0x70_MrlSensorChangedEn_MASK 0x4 -#define DxF0x70_PresenceDetectChangedEn_OFFSET 3 -#define DxF0x70_PresenceDetectChangedEn_WIDTH 1 -#define DxF0x70_PresenceDetectChangedEn_MASK 0x8 -#define DxF0x70_CmdCplIntrEn_OFFSET 4 -#define DxF0x70_CmdCplIntrEn_WIDTH 1 -#define DxF0x70_CmdCplIntrEn_MASK 0x10 -#define DxF0x70_HotplugIntrEn_OFFSET 5 -#define DxF0x70_HotplugIntrEn_WIDTH 1 -#define DxF0x70_HotplugIntrEn_MASK 0x20 -#define DxF0x70_AttnIndicatorControl_OFFSET 6 -#define DxF0x70_AttnIndicatorControl_WIDTH 2 -#define DxF0x70_AttnIndicatorControl_MASK 0xc0 -#define DxF0x70_PwrIndicatorCntl_OFFSET 8 -#define DxF0x70_PwrIndicatorCntl_WIDTH 2 -#define DxF0x70_PwrIndicatorCntl_MASK 0x300 -#define DxF0x70_PwrControllerCntl_OFFSET 10 -#define DxF0x70_PwrControllerCntl_WIDTH 1 -#define DxF0x70_PwrControllerCntl_MASK 0x400 -#define DxF0x70_ElecMechIlCntl_OFFSET 11 -#define DxF0x70_ElecMechIlCntl_WIDTH 1 -#define DxF0x70_ElecMechIlCntl_MASK 0x800 -#define DxF0x70_DlStateChangedEn_OFFSET 12 -#define DxF0x70_DlStateChangedEn_WIDTH 1 -#define DxF0x70_DlStateChangedEn_MASK 0x1000 -#define DxF0x70_Reserved_15_13_OFFSET 13 -#define DxF0x70_Reserved_15_13_WIDTH 3 -#define DxF0x70_Reserved_15_13_MASK 0xe000 -#define DxF0x70_AttnButtonPressed_OFFSET 16 -#define DxF0x70_AttnButtonPressed_WIDTH 1 -#define DxF0x70_AttnButtonPressed_MASK 0x10000 -#define DxF0x70_PwrFaultDetected_OFFSET 17 -#define DxF0x70_PwrFaultDetected_WIDTH 1 -#define DxF0x70_PwrFaultDetected_MASK 0x20000 -#define DxF0x70_MrlSensorChanged_OFFSET 18 -#define DxF0x70_MrlSensorChanged_WIDTH 1 -#define DxF0x70_MrlSensorChanged_MASK 0x40000 -#define DxF0x70_PresenceDetectChanged_OFFSET 19 -#define DxF0x70_PresenceDetectChanged_WIDTH 1 -#define DxF0x70_PresenceDetectChanged_MASK 0x80000 -#define DxF0x70_CmdCpl_OFFSET 20 -#define DxF0x70_CmdCpl_WIDTH 1 -#define DxF0x70_CmdCpl_MASK 0x100000 -#define DxF0x70_MrlSensorState_OFFSET 21 -#define DxF0x70_MrlSensorState_WIDTH 1 -#define DxF0x70_MrlSensorState_MASK 0x200000 -#define DxF0x70_PresenceDetectState_OFFSET 22 -#define DxF0x70_PresenceDetectState_WIDTH 1 -#define DxF0x70_PresenceDetectState_MASK 0x400000 -#define DxF0x70_ElecMechIlSts_OFFSET 23 -#define DxF0x70_ElecMechIlSts_WIDTH 1 -#define DxF0x70_ElecMechIlSts_MASK 0x800000 -#define DxF0x70_DlStateChanged_OFFSET 24 -#define DxF0x70_DlStateChanged_WIDTH 1 -#define DxF0x70_DlStateChanged_MASK 0x1000000 -#define DxF0x70_Reserved_31_25_OFFSET 25 -#define DxF0x70_Reserved_31_25_WIDTH 7 -#define DxF0x70_Reserved_31_25_MASK 0xfe000000 - -/// DxF0x70 -typedef union { - struct { ///< - UINT32 AttnButtonPressedEn:1 ; ///< - UINT32 PwrFaultDetectedEn:1 ; ///< - UINT32 MrlSensorChangedEn:1 ; ///< - UINT32 PresenceDetectChangedEn:1 ; ///< - UINT32 CmdCplIntrEn:1 ; ///< - UINT32 HotplugIntrEn:1 ; ///< - UINT32 AttnIndicatorControl:2 ; ///< - UINT32 PwrIndicatorCntl:2 ; ///< - UINT32 PwrControllerCntl:1 ; ///< - UINT32 ElecMechIlCntl:1 ; ///< - UINT32 DlStateChangedEn:1 ; ///< - UINT32 Reserved_15_13:3 ; ///< - UINT32 AttnButtonPressed:1 ; ///< - UINT32 PwrFaultDetected:1 ; ///< - UINT32 MrlSensorChanged:1 ; ///< - UINT32 PresenceDetectChanged:1 ; ///< - UINT32 CmdCpl:1 ; ///< - UINT32 MrlSensorState:1 ; ///< - UINT32 PresenceDetectState:1 ; ///< - UINT32 ElecMechIlSts:1 ; ///< - UINT32 DlStateChanged:1 ; ///< - UINT32 Reserved_31_25:7 ; ///< - } Field; ///< - UINT32 Value; ///< -} DxF0x70_STRUCT; - -// **** DxF0x74 Register Definition **** -// Address -#define DxF0x74_ADDRESS 0x74 - -// Type -#define DxF0x74_TYPE TYPE_D4F0 -// Field Data -#define DxF0x74_SerrOnCorrErrEn_OFFSET 0 -#define DxF0x74_SerrOnCorrErrEn_WIDTH 1 -#define DxF0x74_SerrOnCorrErrEn_MASK 0x1 -#define DxF0x74_SerrOnNonFatalErrEn_OFFSET 1 -#define DxF0x74_SerrOnNonFatalErrEn_WIDTH 1 -#define DxF0x74_SerrOnNonFatalErrEn_MASK 0x2 -#define DxF0x74_SerrOnFatalErrEn_OFFSET 2 -#define DxF0x74_SerrOnFatalErrEn_WIDTH 1 -#define DxF0x74_SerrOnFatalErrEn_MASK 0x4 -#define DxF0x74_PmIntEn_OFFSET 3 -#define DxF0x74_PmIntEn_WIDTH 1 -#define DxF0x74_PmIntEn_MASK 0x8 -#define DxF0x74_CrsSoftVisibilityEn_OFFSET 4 -#define DxF0x74_CrsSoftVisibilityEn_WIDTH 1 -#define DxF0x74_CrsSoftVisibilityEn_MASK 0x10 -#define DxF0x74_Reserved_15_5_OFFSET 5 -#define DxF0x74_Reserved_15_5_WIDTH 11 -#define DxF0x74_Reserved_15_5_MASK 0xffe0 -#define DxF0x74_CrsSoftVisibility_OFFSET 16 -#define DxF0x74_CrsSoftVisibility_WIDTH 1 -#define DxF0x74_CrsSoftVisibility_MASK 0x10000 -#define DxF0x74_Reserved_31_17_OFFSET 17 -#define DxF0x74_Reserved_31_17_WIDTH 15 -#define DxF0x74_Reserved_31_17_MASK 0xfffe0000 - -/// DxF0x74 -typedef union { - struct { ///< - UINT32 SerrOnCorrErrEn:1 ; ///< - UINT32 SerrOnNonFatalErrEn:1 ; ///< - UINT32 SerrOnFatalErrEn:1 ; ///< - UINT32 PmIntEn:1 ; ///< - UINT32 CrsSoftVisibilityEn:1 ; ///< - UINT32 Reserved_15_5:11; ///< - UINT32 CrsSoftVisibility:1 ; ///< - UINT32 Reserved_31_17:15; ///< - } Field; ///< - UINT32 Value; ///< -} DxF0x74_STRUCT; - -// **** DxF0x78 Register Definition **** -// Address -#define DxF0x78_ADDRESS 0x78 - -// Type -#define DxF0x78_TYPE TYPE_D4F0 -// Field Data -#define DxF0x78_PmeRequestorId_OFFSET 0 -#define DxF0x78_PmeRequestorId_WIDTH 16 -#define DxF0x78_PmeRequestorId_MASK 0xffff -#define DxF0x78_PmeStatus_OFFSET 16 -#define DxF0x78_PmeStatus_WIDTH 1 -#define DxF0x78_PmeStatus_MASK 0x10000 -#define DxF0x78_PmePending_OFFSET 17 -#define DxF0x78_PmePending_WIDTH 1 -#define DxF0x78_PmePending_MASK 0x20000 -#define DxF0x78_Reserved_31_18_OFFSET 18 -#define DxF0x78_Reserved_31_18_WIDTH 14 -#define DxF0x78_Reserved_31_18_MASK 0xfffc0000 - -/// DxF0x78 -typedef union { - struct { ///< - UINT32 PmeRequestorId:16; ///< - UINT32 PmeStatus:1 ; ///< - UINT32 PmePending:1 ; ///< - UINT32 Reserved_31_18:14; ///< - } Field; ///< - UINT32 Value; ///< -} DxF0x78_STRUCT; - -// **** DxF0x7C Register Definition **** -// Address -#define DxF0x7C_ADDRESS 0x7c - -// Type -#define DxF0x7C_TYPE TYPE_D4F0 -// Field Data -#define DxF0x7C_CplTimeoutRangeSup_OFFSET 0 -#define DxF0x7C_CplTimeoutRangeSup_WIDTH 4 -#define DxF0x7C_CplTimeoutRangeSup_MASK 0xf -#define DxF0x7C_CplTimeoutDisSup_OFFSET 4 -#define DxF0x7C_CplTimeoutDisSup_WIDTH 1 -#define DxF0x7C_CplTimeoutDisSup_MASK 0x10 -#define DxF0x7C_AriForwardingSupported_OFFSET 5 -#define DxF0x7C_AriForwardingSupported_WIDTH 1 -#define DxF0x7C_AriForwardingSupported_MASK 0x20 -#define DxF0x7C_Reserved_31_6_OFFSET 6 -#define DxF0x7C_Reserved_31_6_WIDTH 26 -#define DxF0x7C_Reserved_31_6_MASK 0xffffffc0 - -/// DxF0x7C -typedef union { - struct { ///< - UINT32 CplTimeoutRangeSup:4 ; ///< - UINT32 CplTimeoutDisSup:1 ; ///< - UINT32 AriForwardingSupported:1 ; ///< - UINT32 Reserved_31_6:26; ///< - } Field; ///< - UINT32 Value; ///< -} DxF0x7C_STRUCT; - -// **** DxF0x80 Register Definition **** -// Address -#define DxF0x80_ADDRESS 0x80 - -// Type -#define DxF0x80_TYPE TYPE_D4F0 -// Field Data -#define DxF0x80_CplTimeoutValue_OFFSET 0 -#define DxF0x80_CplTimeoutValue_WIDTH 4 -#define DxF0x80_CplTimeoutValue_MASK 0xf -#define DxF0x80_CplTimeoutDis_OFFSET 4 -#define DxF0x80_CplTimeoutDis_WIDTH 1 -#define DxF0x80_CplTimeoutDis_MASK 0x10 -#define DxF0x80_AriForwardingEn_OFFSET 5 -#define DxF0x80_AriForwardingEn_WIDTH 1 -#define DxF0x80_AriForwardingEn_MASK 0x20 -#define DxF0x80_Reserved_31_6_OFFSET 6 -#define DxF0x80_Reserved_31_6_WIDTH 26 -#define DxF0x80_Reserved_31_6_MASK 0xffffffc0 - -/// DxF0x80 -typedef union { - struct { ///< - UINT32 CplTimeoutValue:4 ; ///< - UINT32 CplTimeoutDis:1 ; ///< - UINT32 AriForwardingEn:1 ; ///< - UINT32 Reserved_31_6:26; ///< - } Field; ///< - UINT32 Value; ///< -} DxF0x80_STRUCT; - -// **** DxF0x84 Register Definition **** -// Address -#define DxF0x84_ADDRESS 0x84 - -// Type -#define DxF0x84_TYPE TYPE_D4F0 -// Field Data -#define DxF0x84_Reserved_31_0_OFFSET 0 -#define DxF0x84_Reserved_31_0_WIDTH 32 -#define DxF0x84_Reserved_31_0_MASK 0xffffffff - -/// DxF0x84 -typedef union { - struct { ///< - UINT32 Reserved_31_0:32; ///< - } Field; ///< - UINT32 Value; ///< -} DxF0x84_STRUCT; - -// **** DxF0x88 Register Definition **** -// Address -#define DxF0x88_ADDRESS 0x88 - -// Type -#define DxF0x88_TYPE TYPE_D4F0 -// Field Data -#define DxF0x88_TargetLinkSpeed_OFFSET 0 -#define DxF0x88_TargetLinkSpeed_WIDTH 4 -#define DxF0x88_TargetLinkSpeed_MASK 0xf -#define DxF0x88_EnterCompliance_OFFSET 4 -#define DxF0x88_EnterCompliance_WIDTH 1 -#define DxF0x88_EnterCompliance_MASK 0x10 -#define DxF0x88_HwAutonomousSpeedDisable_OFFSET 5 -#define DxF0x88_HwAutonomousSpeedDisable_WIDTH 1 -#define DxF0x88_HwAutonomousSpeedDisable_MASK 0x20 -#define DxF0x88_SelectableDeemphasis_OFFSET 6 -#define DxF0x88_SelectableDeemphasis_WIDTH 1 -#define DxF0x88_SelectableDeemphasis_MASK 0x40 -#define DxF0x88_XmitMargin_OFFSET 7 -#define DxF0x88_XmitMargin_WIDTH 3 -#define DxF0x88_XmitMargin_MASK 0x380 -#define DxF0x88_EnterModCompliance_OFFSET 10 -#define DxF0x88_EnterModCompliance_WIDTH 1 -#define DxF0x88_EnterModCompliance_MASK 0x400 -#define DxF0x88_ComplianceSOS_OFFSET 11 -#define DxF0x88_ComplianceSOS_WIDTH 1 -#define DxF0x88_ComplianceSOS_MASK 0x800 -#define DxF0x88_ComplianceDeemphasis_OFFSET 12 -#define DxF0x88_ComplianceDeemphasis_WIDTH 1 -#define DxF0x88_ComplianceDeemphasis_MASK 0x1000 -#define DxF0x88_Reserved_15_13_OFFSET 13 -#define DxF0x88_Reserved_15_13_WIDTH 3 -#define DxF0x88_Reserved_15_13_MASK 0xe000 -#define DxF0x88_CurDeemphasisLevel_OFFSET 16 -#define DxF0x88_CurDeemphasisLevel_WIDTH 1 -#define DxF0x88_CurDeemphasisLevel_MASK 0x10000 -#define DxF0x88_Reserved_31_17_OFFSET 17 -#define DxF0x88_Reserved_31_17_WIDTH 15 -#define DxF0x88_Reserved_31_17_MASK 0xfffe0000 - -/// DxF0x88 -typedef union { - struct { ///< - UINT32 TargetLinkSpeed:4 ; ///< - UINT32 EnterCompliance:1 ; ///< - UINT32 HwAutonomousSpeedDisable:1 ; ///< - UINT32 SelectableDeemphasis:1 ; ///< - UINT32 XmitMargin:3 ; ///< - UINT32 EnterModCompliance:1 ; ///< - UINT32 ComplianceSOS:1 ; ///< - UINT32 ComplianceDeemphasis:1 ; ///< - UINT32 Reserved_15_13:3 ; ///< - UINT32 CurDeemphasisLevel:1 ; ///< - UINT32 Reserved_31_17:15; ///< - } Field; ///< - UINT32 Value; ///< -} DxF0x88_STRUCT; - -// **** DxF0x8C Register Definition **** -// Address -#define DxF0x8C_ADDRESS 0x8c - -// Type -#define DxF0x8C_TYPE TYPE_D4F0 -// Field Data -#define DxF0x8C_Reserved_31_0_OFFSET 0 -#define DxF0x8C_Reserved_31_0_WIDTH 32 -#define DxF0x8C_Reserved_31_0_MASK 0xffffffff - -/// DxF0x8C -typedef union { - struct { ///< - UINT32 Reserved_31_0:32; ///< - } Field; ///< - UINT32 Value; ///< -} DxF0x8C_STRUCT; - -// **** DxF0x90 Register Definition **** -// Address -#define DxF0x90_ADDRESS 0x90 - -// Type -#define DxF0x90_TYPE TYPE_D4F0 -// Field Data -#define DxF0x90_Reserved_31_0_OFFSET 0 -#define DxF0x90_Reserved_31_0_WIDTH 32 -#define DxF0x90_Reserved_31_0_MASK 0xffffffff - -/// DxF0x90 -typedef union { - struct { ///< - UINT32 Reserved_31_0:32; ///< - } Field; ///< - UINT32 Value; ///< -} DxF0x90_STRUCT; - -// **** DxF0x128 Register Definition **** -// Address -#define DxF0x128_ADDRESS 0x128 - -// Type -#define DxF0x128_TYPE TYPE_D4F0 -// Field Data -#define DxF0x128_Reserved_15_0_OFFSET 0 -#define DxF0x128_Reserved_15_0_WIDTH 16 -#define DxF0x128_Reserved_15_0_MASK 0xffff -#define DxF0x128_PortArbTableStatus_OFFSET 16 -#define DxF0x128_PortArbTableStatus_WIDTH 1 -#define DxF0x128_PortArbTableStatus_MASK 0x10000 -#define DxF0x128_VcNegotiationPending_OFFSET 17 -#define DxF0x128_VcNegotiationPending_WIDTH 1 -#define DxF0x128_VcNegotiationPending_MASK 0x20000 -#define DxF0x128_Reserved_31_18_OFFSET 18 -#define DxF0x128_Reserved_31_18_WIDTH 14 -#define DxF0x128_Reserved_31_18_MASK 0xfffc0000 - -/// DxF0x128 -typedef union { - struct { ///< - UINT32 Reserved_15_0:16; ///< - UINT32 PortArbTableStatus:1 ; ///< - UINT32 VcNegotiationPending:1 ; ///< - UINT32 Reserved_31_18:14; ///< - } Field; ///< - UINT32 Value; ///< -} DxF0x128_STRUCT; - -// **** FCRxFE00_6000 Register Definition **** -// Address -#define FCRxFE00_6000_ADDRESS 0xfe006000 - -// Type -#define FCRxFE00_6000_TYPE TYPE_FCR -// Field Data -#define FCRxFE00_6000_Reserved_6_0_OFFSET 0 -#define FCRxFE00_6000_Reserved_6_0_WIDTH 7 -#define FCRxFE00_6000_Reserved_6_0_MASK 0x7f -#define FCRxFE00_6000_NbPs0Vid_OFFSET 7 -#define FCRxFE00_6000_NbPs0Vid_WIDTH 7 -#define FCRxFE00_6000_NbPs0Vid_MASK 0x3f80 -#define FCRxFE00_6000_NbPs1Vid_OFFSET 14 -#define FCRxFE00_6000_NbPs1Vid_WIDTH 7 -#define FCRxFE00_6000_NbPs1Vid_MASK 0x1fc000 -#define FCRxFE00_6000_Reserved_31_21_OFFSET 21 -#define FCRxFE00_6000_Reserved_31_21_WIDTH 11 -#define FCRxFE00_6000_Reserved_31_21_MASK 0xffe00000 - -/// FCRxFE00_6000 -typedef union { - struct { ///< - UINT32 Reserved_6_0:7 ; ///< - UINT32 NbPs0Vid:7 ; ///< - UINT32 NbPs1Vid:7 ; ///< - UINT32 Reserved_31_21:11; ///< - } Field; ///< - UINT32 Value; ///< -} FCRxFE00_6000_STRUCT; - -// **** FCRxFE00_6002 Register Definition **** -// Address -#define FCRxFE00_6002_ADDRESS 0xfe006002 - -// Type -#define FCRxFE00_6002_TYPE TYPE_FCR -// Field Data -#define FCRxFE00_6002_Reserved_4_0_OFFSET 0 -#define FCRxFE00_6002_Reserved_4_0_WIDTH 5 -#define FCRxFE00_6002_Reserved_4_0_MASK 0x1f -#define FCRxFE00_6002_NbPs1VidAddl_OFFSET 5 -#define FCRxFE00_6002_NbPs1VidAddl_WIDTH 7 -#define FCRxFE00_6002_NbPs1VidAddl_MASK 0xfe0 -#define FCRxFE00_6002_NbPs1VidHigh_OFFSET 12 -#define FCRxFE00_6002_NbPs1VidHigh_WIDTH 7 -#define FCRxFE00_6002_NbPs1VidHigh_MASK 0x7f000 -#define FCRxFE00_6002_Reserved_31_19_OFFSET 19 -#define FCRxFE00_6002_Reserved_31_19_WIDTH 13 -#define FCRxFE00_6002_Reserved_31_19_MASK 0xfff80000 - -/// FCRxFE00_6002 -typedef union { - struct { ///< - UINT32 Reserved_4_0:5 ; ///< - UINT32 NbPs1VidAddl:7 ; ///< - UINT32 NbPs1VidHigh:7 ; ///< - UINT32 Reserved_31_19:13; ///< - } Field; ///< - UINT32 Value; ///< -} FCRxFE00_6002_STRUCT; - -// **** FCRxFE00_7006 Register Definition **** -// Address -#define FCRxFE00_7006_ADDRESS 0xfe007006 - -// Type -#define FCRxFE00_7006_TYPE TYPE_FCR -// Field Data -#define FCRxFE00_7006_Reserved_13_0_OFFSET 0 -#define FCRxFE00_7006_Reserved_13_0_WIDTH 14 -#define FCRxFE00_7006_Reserved_13_0_MASK 0x3fff -#define FCRxFE00_7006_NbPs1NclkDiv_OFFSET 14 -#define FCRxFE00_7006_NbPs1NclkDiv_WIDTH 7 -#define FCRxFE00_7006_NbPs1NclkDiv_MASK 0x1fc000 -#define FCRxFE00_7006_MaxNbFreqAtMinVid_OFFSET 21 -#define FCRxFE00_7006_MaxNbFreqAtMinVid_WIDTH 5 -#define FCRxFE00_7006_MaxNbFreqAtMinVid_MASK 0x3e00000 -#define FCRxFE00_7006_Reserved_31_26_OFFSET 26 -#define FCRxFE00_7006_Reserved_31_26_WIDTH 6 -#define FCRxFE00_7006_Reserved_31_26_MASK 0xfc000000 - -/// FCRxFE00_7006 -typedef union { - struct { ///< - UINT32 Reserved_13_0:14; ///< - UINT32 NbPs1NclkDiv:7 ; ///< - UINT32 MaxNbFreqAtMinVid:5 ; ///< - UINT32 Reserved_31_26:6 ; ///< - } Field; ///< - UINT32 Value; ///< -} FCRxFE00_7006_STRUCT; - -// **** FCRxFE00_7009 Register Definition **** -// Address -#define FCRxFE00_7009_ADDRESS 0xfe007009 - -// Type -#define FCRxFE00_7009_TYPE TYPE_FCR -// Field Data -#define FCRxFE00_7009_Reserved_1_0_OFFSET 0 -#define FCRxFE00_7009_Reserved_1_0_WIDTH 2 -#define FCRxFE00_7009_Reserved_1_0_MASK 0x3 -#define FCRxFE00_7009_NbPs0NclkDiv_OFFSET 2 -#define FCRxFE00_7009_NbPs0NclkDiv_WIDTH 7 -#define FCRxFE00_7009_NbPs0NclkDiv_MASK 0x1fc -#define FCRxFE00_7009_Reserved_31_9_OFFSET 9 -#define FCRxFE00_7009_Reserved_31_9_WIDTH 23 -#define FCRxFE00_7009_Reserved_31_9_MASK 0xfffffe00 - -/// FCRxFE00_7009 -typedef union { - struct { ///< - UINT32 Reserved_1_0:2 ; ///< - UINT32 NbPs0NclkDiv:7 ; ///< - UINT32 Reserved_31_9:23; ///< - } Field; ///< - UINT32 Value; ///< -} FCRxFE00_7009_STRUCT; - -// **** FCRxFE00_705F Register Definition **** -// Address -#define FCRxFE00_705F_ADDRESS 0xfe00705f - -// Type -#define FCRxFE00_705F_TYPE TYPE_FCR -// Field Data -#define FCRxFE00_705F_Reserved_4_0_OFFSET 0 -#define FCRxFE00_705F_Reserved_4_0_WIDTH 5 -#define FCRxFE00_705F_Reserved_4_0_MASK 0x1f -#define FCRxFE00_705F_GnbIdleAdjustVid_OFFSET 5 -#define FCRxFE00_705F_GnbIdleAdjustVid_WIDTH 4 -#define FCRxFE00_705F_GnbIdleAdjustVid_MASK 0x1e0 -#define FCRxFE00_705F_Reserved_31_9_OFFSET 9 -#define FCRxFE00_705F_Reserved_31_9_WIDTH 23 -#define FCRxFE00_705F_Reserved_31_9_MASK 0xfffffe00 - -/// FCRxFE00_705F -typedef union { - struct { ///< - UINT32 Reserved_4_0:5 ; ///< - UINT32 GnbIdleAdjustVid:4 ; ///< - UINT32 Reserved_31_9:23; ///< - } Field; ///< - UINT32 Value; ///< -} FCRxFE00_705F_STRUCT; - -// **** FCRxFE00_7110 Register Definition **** -// Address -#define FCRxFE00_7110_ADDRESS 0xfe007110 - -// Type -#define FCRxFE00_7110_TYPE TYPE_FCR -// Field Data -#define FCRxFE00_7110_Reserved_5_0_OFFSET 0 -#define FCRxFE00_7110_Reserved_5_0_WIDTH 6 -#define FCRxFE00_7110_Reserved_5_0_MASK 0x3f -#define FCRxFE00_7110_LclkDpmDid0_OFFSET 6 -#define FCRxFE00_7110_LclkDpmDid0_WIDTH 7 -#define FCRxFE00_7110_LclkDpmDid0_MASK 0x1fc0 -#define FCRxFE00_7110_LclkDpmDid1_OFFSET 13 -#define FCRxFE00_7110_LclkDpmDid1_WIDTH 7 -#define FCRxFE00_7110_LclkDpmDid1_MASK 0xfe000 -#define FCRxFE00_7110_LclkDpmDid2_OFFSET 20 -#define FCRxFE00_7110_LclkDpmDid2_WIDTH 7 -#define FCRxFE00_7110_LclkDpmDid2_MASK 0x7f00000 -#define FCRxFE00_7110_Reserved_31_27_OFFSET 27 -#define FCRxFE00_7110_Reserved_31_27_WIDTH 5 -#define FCRxFE00_7110_Reserved_31_27_MASK 0xf8000000 - -/// FCRxFE00_7110 -typedef union { - struct { ///< - UINT32 Reserved_5_0:6 ; ///< - UINT32 LclkDpmDid0:7 ; ///< - UINT32 LclkDpmDid1:7 ; ///< - UINT32 LclkDpmDid2:7 ; ///< - UINT32 Reserved_31_27:5 ; ///< - } Field; ///< - UINT32 Value; ///< -} FCRxFE00_7110_STRUCT; - -// **** FCRxFE00_7113 Register Definition **** -// Address -#define FCRxFE00_7113_ADDRESS 0xfe007113 - -// Type -#define FCRxFE00_7113_TYPE TYPE_FCR -// Field Data -#define FCRxFE00_7113_Reserved_2_0_OFFSET 0 -#define FCRxFE00_7113_Reserved_2_0_WIDTH 3 -#define FCRxFE00_7113_Reserved_2_0_MASK 0x7 -#define FCRxFE00_7113_LclkDpmDid3_OFFSET 3 -#define FCRxFE00_7113_LclkDpmDid3_WIDTH 7 -#define FCRxFE00_7113_LclkDpmDid3_MASK 0x3f8 -#define FCRxFE00_7113_LclkDpmValid0_OFFSET 10 -#define FCRxFE00_7113_LclkDpmValid0_WIDTH 1 -#define FCRxFE00_7113_LclkDpmValid0_MASK 0x400 -#define FCRxFE00_7113_LclkDpmValid1_OFFSET 11 -#define FCRxFE00_7113_LclkDpmValid1_WIDTH 1 -#define FCRxFE00_7113_LclkDpmValid1_MASK 0x800 -#define FCRxFE00_7113_LclkDpmValid2_OFFSET 12 -#define FCRxFE00_7113_LclkDpmValid2_WIDTH 1 -#define FCRxFE00_7113_LclkDpmValid2_MASK 0x1000 -#define FCRxFE00_7113_LclkDpmValid3_OFFSET 13 -#define FCRxFE00_7113_LclkDpmValid3_WIDTH 1 -#define FCRxFE00_7113_LclkDpmValid3_MASK 0x2000 -#define FCRxFE00_7113_Reserved_31_14_OFFSET 14 -#define FCRxFE00_7113_Reserved_31_14_WIDTH 18 -#define FCRxFE00_7113_Reserved_31_14_MASK 0xffffc000 - -/// FCRxFE00_7113 -typedef union { - struct { ///< - UINT32 Reserved_2_0:3 ; ///< - UINT32 LclkDpmDid3:7 ; ///< - UINT32 LclkDpmValid0:1 ; ///< - UINT32 LclkDpmValid1:1 ; ///< - UINT32 LclkDpmValid2:1 ; ///< - UINT32 LclkDpmValid3:1 ; ///< - UINT32 Reserved_31_14:18; ///< - } Field; ///< - UINT32 Value; ///< -} FCRxFE00_7113_STRUCT; - -// **** FCRxFF30_0191 Register Definition **** -// Address -#define FCRxFF30_0191_ADDRESS 0xff300191 - -// Type -#define FCRxFF30_0191_TYPE TYPE_FCR -// Field Data -#define FCRxFF30_0191_Reserved_15_0_OFFSET 0 -#define FCRxFF30_0191_Reserved_15_0_WIDTH 16 -#define FCRxFF30_0191_Reserved_15_0_MASK 0xffff -#define FCRxFF30_0191_GfxIdleVoltChgEn_OFFSET 16 -#define FCRxFF30_0191_GfxIdleVoltChgEn_WIDTH 1 -#define FCRxFF30_0191_GfxIdleVoltChgEn_MASK 0x10000 -#define FCRxFF30_0191_GfxIdleVoltChgMode_OFFSET 17 -#define FCRxFF30_0191_GfxIdleVoltChgMode_WIDTH 1 -#define FCRxFF30_0191_GfxIdleVoltChgMode_MASK 0x20000 -#define FCRxFF30_0191_Reserved_31_18_OFFSET 18 -#define FCRxFF30_0191_Reserved_31_18_WIDTH 14 -#define FCRxFF30_0191_Reserved_31_18_MASK 0xfffc0000 - -/// FCRxFF30_0191 -typedef union { - struct { ///< - UINT32 Reserved_15_0:16; ///< - UINT32 GfxIdleVoltChgEn:1 ; ///< - UINT32 GfxIdleVoltChgMode:1 ; ///< - UINT32 Reserved_31_18:14; ///< - } Field; ///< - UINT32 Value; ///< -} FCRxFF30_0191_STRUCT; - -// **** FCRxFF30_01E4 Register Definition **** -// Address -#define FCRxFF30_01E4_ADDRESS 0xff3001e4 - -// Type -#define FCRxFF30_01E4_TYPE TYPE_FCR -// Field Data -#define FCRxFF30_01E4_Reserved_19_0_OFFSET 0 -#define FCRxFF30_01E4_Reserved_19_0_WIDTH 20 -#define FCRxFF30_01E4_Reserved_19_0_MASK 0xfffff -#define FCRxFF30_01E4_VoltageChangeEn_OFFSET 20 -#define FCRxFF30_01E4_VoltageChangeEn_WIDTH 1 -#define FCRxFF30_01E4_VoltageChangeEn_MASK 0x100000 -#define FCRxFF30_01E4_Reserved_31_21_OFFSET 21 -#define FCRxFF30_01E4_Reserved_31_21_WIDTH 11 -#define FCRxFF30_01E4_Reserved_31_21_MASK 0xffe00000 - -/// FCRxFF30_01E4 -typedef union { - struct { ///< - UINT32 Reserved_19_0:20; ///< - UINT32 VoltageChangeEn:1 ; ///< - UINT32 Reserved_31_21:11; ///< - } Field; ///< - UINT32 Value; ///< -} FCRxFF30_01E4_STRUCT; - -// **** FCRxFF30_01F4 Register Definition **** -// Address -#define FCRxFF30_01F4_ADDRESS 0xff3001f4 - -// Type -#define FCRxFF30_01F4_TYPE TYPE_FCR -// Field Data -#define FCRxFF30_01F4_CgRlcCgttSclkOverride_OFFSET 0 -#define FCRxFF30_01F4_CgRlcCgttSclkOverride_WIDTH 1 -#define FCRxFF30_01F4_CgRlcCgttSclkOverride_MASK 0x1 -#define FCRxFF30_01F4_CgCpCgttSclkOverride_OFFSET 1 -#define FCRxFF30_01F4_CgCpCgttSclkOverride_WIDTH 1 -#define FCRxFF30_01F4_CgCpCgttSclkOverride_MASK 0x2 -#define FCRxFF30_01F4_CgVgtCgttSclkOverride_OFFSET 2 -#define FCRxFF30_01F4_CgVgtCgttSclkOverride_WIDTH 1 -#define FCRxFF30_01F4_CgVgtCgttSclkOverride_MASK 0x4 -#define FCRxFF30_01F4_CgPaCgttSclkOverride_OFFSET 3 -#define FCRxFF30_01F4_CgPaCgttSclkOverride_WIDTH 1 -#define FCRxFF30_01F4_CgPaCgttSclkOverride_MASK 0x8 -#define FCRxFF30_01F4_CgScCgttSclkOverride_OFFSET 4 -#define FCRxFF30_01F4_CgScCgttSclkOverride_WIDTH 1 -#define FCRxFF30_01F4_CgScCgttSclkOverride_MASK 0x10 -#define FCRxFF30_01F4_CgSpimCgttSclkOverride_OFFSET 5 -#define FCRxFF30_01F4_CgSpimCgttSclkOverride_WIDTH 1 -#define FCRxFF30_01F4_CgSpimCgttSclkOverride_MASK 0x20 -#define FCRxFF30_01F4_CgSxmCgttSclkOverride_OFFSET 6 -#define FCRxFF30_01F4_CgSxmCgttSclkOverride_WIDTH 1 -#define FCRxFF30_01F4_CgSxmCgttSclkOverride_MASK 0x40 -#define FCRxFF30_01F4_CgSxsCgttSclkOverride_OFFSET 7 -#define FCRxFF30_01F4_CgSxsCgttSclkOverride_WIDTH 1 -#define FCRxFF30_01F4_CgSxsCgttSclkOverride_MASK 0x80 -#define FCRxFF30_01F4_CgCb0CgttSclkOverride_OFFSET 8 -#define FCRxFF30_01F4_CgCb0CgttSclkOverride_WIDTH 1 -#define FCRxFF30_01F4_CgCb0CgttSclkOverride_MASK 0x100 -#define FCRxFF30_01F4_CgCb1CgttSclkOverride_OFFSET 9 -#define FCRxFF30_01F4_CgCb1CgttSclkOverride_WIDTH 1 -#define FCRxFF30_01F4_CgCb1CgttSclkOverride_MASK 0x200 -#define FCRxFF30_01F4_ReservedCgtt10Override_OFFSET 10 -#define FCRxFF30_01F4_ReservedCgtt10Override_WIDTH 1 -#define FCRxFF30_01F4_ReservedCgtt10Override_MASK 0x400 -#define FCRxFF30_01F4_ReservedCgtt11Override_OFFSET 11 -#define FCRxFF30_01F4_ReservedCgtt11Override_WIDTH 1 -#define FCRxFF30_01F4_ReservedCgtt11Override_MASK 0x800 -#define FCRxFF30_01F4_CgDb0CgttSclkOverride_OFFSET 12 -#define FCRxFF30_01F4_CgDb0CgttSclkOverride_WIDTH 1 -#define FCRxFF30_01F4_CgDb0CgttSclkOverride_MASK 0x1000 -#define FCRxFF30_01F4_CgDb1CgttSclkOverride_OFFSET 13 -#define FCRxFF30_01F4_CgDb1CgttSclkOverride_WIDTH 1 -#define FCRxFF30_01F4_CgDb1CgttSclkOverride_MASK 0x2000 -#define FCRxFF30_01F4_ReservedCgtt14Override_OFFSET 14 -#define FCRxFF30_01F4_ReservedCgtt14Override_WIDTH 1 -#define FCRxFF30_01F4_ReservedCgtt14Override_MASK 0x4000 -#define FCRxFF30_01F4_ReservedCgtt15Override_OFFSET 15 -#define FCRxFF30_01F4_ReservedCgtt15Override_WIDTH 1 -#define FCRxFF30_01F4_ReservedCgtt15Override_MASK 0x8000 -#define FCRxFF30_01F4_CgVcCgttSclkOverride_OFFSET 16 -#define FCRxFF30_01F4_CgVcCgttSclkOverride_WIDTH 1 -#define FCRxFF30_01F4_CgVcCgttSclkOverride_MASK 0x10000 -#define FCRxFF30_01F4_CgAvpCgttSclkOverride_OFFSET 17 -#define FCRxFF30_01F4_CgAvpCgttSclkOverride_WIDTH 1 -#define FCRxFF30_01F4_CgAvpCgttSclkOverride_MASK 0x20000 -#define FCRxFF30_01F4_CgAvpCgttEclkOverride_OFFSET 18 -#define FCRxFF30_01F4_CgAvpCgttEclkOverride_WIDTH 1 -#define FCRxFF30_01F4_CgAvpCgttEclkOverride_MASK 0x40000 -#define FCRxFF30_01F4_CgUvdmCgttSclkOverride_OFFSET 19 -#define FCRxFF30_01F4_CgUvdmCgttSclkOverride_WIDTH 1 -#define FCRxFF30_01F4_CgUvdmCgttSclkOverride_MASK 0x80000 -#define FCRxFF30_01F4_CgUvdmCgttVclkOverride_OFFSET 20 -#define FCRxFF30_01F4_CgUvdmCgttVclkOverride_WIDTH 1 -#define FCRxFF30_01F4_CgUvdmCgttVclkOverride_MASK 0x100000 -#define FCRxFF30_01F4_CgUvdmCgttDclkOverride_OFFSET 21 -#define FCRxFF30_01F4_CgUvdmCgttDclkOverride_WIDTH 1 -#define FCRxFF30_01F4_CgUvdmCgttDclkOverride_MASK 0x200000 -#define FCRxFF30_01F4_CgBifCgttSclkOverride_OFFSET 22 -#define FCRxFF30_01F4_CgBifCgttSclkOverride_WIDTH 1 -#define FCRxFF30_01F4_CgBifCgttSclkOverride_MASK 0x400000 -#define FCRxFF30_01F4_CgRomCgttSclkOverride_OFFSET 23 -#define FCRxFF30_01F4_CgRomCgttSclkOverride_WIDTH 1 -#define FCRxFF30_01F4_CgRomCgttSclkOverride_MASK 0x800000 -#define FCRxFF30_01F4_CgDrmCgttSclkOverride_OFFSET 24 -#define FCRxFF30_01F4_CgDrmCgttSclkOverride_WIDTH 1 -#define FCRxFF30_01F4_CgDrmCgttSclkOverride_MASK 0x1000000 -#define FCRxFF30_01F4_CgDcCgttSclkOverride_OFFSET 25 -#define FCRxFF30_01F4_CgDcCgttSclkOverride_WIDTH 1 -#define FCRxFF30_01F4_CgDcCgttSclkOverride_MASK 0x2000000 -#define FCRxFF30_01F4_ReservedCgtt26Override_OFFSET 26 -#define FCRxFF30_01F4_ReservedCgtt26Override_WIDTH 1 -#define FCRxFF30_01F4_ReservedCgtt26Override_MASK 0x4000000 -#define FCRxFF30_01F4_CgMcbCgttSclkOverride_OFFSET 27 -#define FCRxFF30_01F4_CgMcbCgttSclkOverride_WIDTH 1 -#define FCRxFF30_01F4_CgMcbCgttSclkOverride_MASK 0x8000000 -#define FCRxFF30_01F4_CgMcdwCgttSclkOverride_OFFSET 28 -#define FCRxFF30_01F4_CgMcdwCgttSclkOverride_WIDTH 1 -#define FCRxFF30_01F4_CgMcdwCgttSclkOverride_MASK 0x10000000 -#define FCRxFF30_01F4_ReservedCgtt29Override_OFFSET 29 -#define FCRxFF30_01F4_ReservedCgtt29Override_WIDTH 1 -#define FCRxFF30_01F4_ReservedCgtt29Override_MASK 0x20000000 -#define FCRxFF30_01F4_ReservedCgtt30Override_OFFSET 30 -#define FCRxFF30_01F4_ReservedCgtt30Override_WIDTH 1 -#define FCRxFF30_01F4_ReservedCgtt30Override_MASK 0x40000000 -#define FCRxFF30_01F4_ReservedCgtt31Override_OFFSET 31 -#define FCRxFF30_01F4_ReservedCgtt31Override_WIDTH 1 -#define FCRxFF30_01F4_ReservedCgtt31Override_MASK 0x80000000 - -/// FCRxFF30_01F4 -typedef union { - struct { ///< - UINT32 CgRlcCgttSclkOverride:1 ; ///< - UINT32 CgCpCgttSclkOverride:1 ; ///< - UINT32 CgVgtCgttSclkOverride:1 ; ///< - UINT32 CgPaCgttSclkOverride:1 ; ///< - UINT32 CgScCgttSclkOverride:1 ; ///< - UINT32 CgSpimCgttSclkOverride:1 ; ///< - UINT32 CgSxmCgttSclkOverride:1 ; ///< - UINT32 CgSxsCgttSclkOverride:1 ; ///< - UINT32 CgCb0CgttSclkOverride:1 ; ///< - UINT32 CgCb1CgttSclkOverride:1 ; ///< - UINT32 ReservedCgtt10Override:1 ; ///< - UINT32 ReservedCgtt11Override:1 ; ///< - UINT32 CgDb0CgttSclkOverride:1 ; ///< - UINT32 CgDb1CgttSclkOverride:1 ; ///< - UINT32 ReservedCgtt14Override:1 ; ///< - UINT32 ReservedCgtt15Override:1 ; ///< - UINT32 CgVcCgttSclkOverride:1 ; ///< - UINT32 CgAvpCgttSclkOverride:1 ; ///< - UINT32 CgAvpCgttEclkOverride:1 ; ///< - UINT32 CgUvdmCgttSclkOverride:1 ; ///< - UINT32 CgUvdmCgttVclkOverride:1 ; ///< - UINT32 CgUvdmCgttDclkOverride:1 ; ///< - UINT32 CgBifCgttSclkOverride:1 ; ///< - UINT32 CgRomCgttSclkOverride:1 ; ///< - UINT32 CgDrmCgttSclkOverride:1 ; ///< - UINT32 CgDcCgttSclkOverride:1 ; ///< - UINT32 ReservedCgtt26Override:1 ; ///< - UINT32 CgMcbCgttSclkOverride:1 ; ///< - UINT32 CgMcdwCgttSclkOverride:1 ; ///< - UINT32 ReservedCgtt29Override:1 ; ///< - UINT32 ReservedCgtt30Override:1 ; ///< - UINT32 ReservedCgtt31Override:1 ; ///< - } Field; ///< - UINT32 Value; ///< -} FCRxFF30_01F4_STRUCT; - -// **** FCRxFF30_01F5 Register Definition **** -// Address -#define FCRxFF30_01F5_ADDRESS 0xff3001f5 - -// Type -#define FCRxFF30_01F5_TYPE TYPE_FCR -// Field Data -#define FCRxFF30_01F5_ReservedCgtt32Override_OFFSET 0 -#define FCRxFF30_01F5_ReservedCgtt32Override_WIDTH 1 -#define FCRxFF30_01F5_ReservedCgtt32Override_MASK 0x1 -#define FCRxFF30_01F5_ReservedCgtt33Override_OFFSET 1 -#define FCRxFF30_01F5_ReservedCgtt33Override_WIDTH 1 -#define FCRxFF30_01F5_ReservedCgtt33Override_MASK 0x2 -#define FCRxFF30_01F5_ReservedCgtt34Override_OFFSET 2 -#define FCRxFF30_01F5_ReservedCgtt34Override_WIDTH 1 -#define FCRxFF30_01F5_ReservedCgtt34Override_MASK 0x4 -#define FCRxFF30_01F5_ReservedCgtt35Override_OFFSET 3 -#define FCRxFF30_01F5_ReservedCgtt35Override_WIDTH 1 -#define FCRxFF30_01F5_ReservedCgtt35Override_MASK 0x8 -#define FCRxFF30_01F5_CgTaCgttSclkOverride_OFFSET 4 -#define FCRxFF30_01F5_CgTaCgttSclkOverride_WIDTH 1 -#define FCRxFF30_01F5_CgTaCgttSclkOverride_MASK 0x10 -#define FCRxFF30_01F5_CgTdCgttSclkOverride_OFFSET 5 -#define FCRxFF30_01F5_CgTdCgttSclkOverride_WIDTH 1 -#define FCRxFF30_01F5_CgTdCgttSclkOverride_MASK 0x20 -#define FCRxFF30_01F5_CgTcaCgttSclkOverride_OFFSET 6 -#define FCRxFF30_01F5_CgTcaCgttSclkOverride_WIDTH 1 -#define FCRxFF30_01F5_CgTcaCgttSclkOverride_MASK 0x40 -#define FCRxFF30_01F5_CgTcpCgttSclkOverride_OFFSET 7 -#define FCRxFF30_01F5_CgTcpCgttSclkOverride_WIDTH 1 -#define FCRxFF30_01F5_CgTcpCgttSclkOverride_MASK 0x80 -#define FCRxFF30_01F5_CgTccCgttSclkOverride_OFFSET 8 -#define FCRxFF30_01F5_CgTccCgttSclkOverride_WIDTH 1 -#define FCRxFF30_01F5_CgTccCgttSclkOverride_MASK 0x100 -#define FCRxFF30_01F5_CgSqCgttSclkOverride_OFFSET 9 -#define FCRxFF30_01F5_CgSqCgttSclkOverride_WIDTH 1 -#define FCRxFF30_01F5_CgSqCgttSclkOverride_MASK 0x200 -#define FCRxFF30_01F5_CgHdpCgttSclkOverride_OFFSET 10 -#define FCRxFF30_01F5_CgHdpCgttSclkOverride_WIDTH 1 -#define FCRxFF30_01F5_CgHdpCgttSclkOverride_MASK 0x400 -#define FCRxFF30_01F5_CgVmcCgttSclkOverride_OFFSET 11 -#define FCRxFF30_01F5_CgVmcCgttSclkOverride_WIDTH 1 -#define FCRxFF30_01F5_CgVmcCgttSclkOverride_MASK 0x800 -#define FCRxFF30_01F5_CgOrbCgttSclkOverride_OFFSET 12 -#define FCRxFF30_01F5_CgOrbCgttSclkOverride_WIDTH 1 -#define FCRxFF30_01F5_CgOrbCgttSclkOverride_MASK 0x1000 -#define FCRxFF30_01F5_CgOrbCgttLclkOverride_OFFSET 13 -#define FCRxFF30_01F5_CgOrbCgttLclkOverride_WIDTH 1 -#define FCRxFF30_01F5_CgOrbCgttLclkOverride_MASK 0x2000 -#define FCRxFF30_01F5_CgIocCgttSclkOverride_OFFSET 14 -#define FCRxFF30_01F5_CgIocCgttSclkOverride_WIDTH 1 -#define FCRxFF30_01F5_CgIocCgttSclkOverride_MASK 0x4000 -#define FCRxFF30_01F5_CgIocCgttLclkOverride_OFFSET 15 -#define FCRxFF30_01F5_CgIocCgttLclkOverride_WIDTH 1 -#define FCRxFF30_01F5_CgIocCgttLclkOverride_MASK 0x8000 -#define FCRxFF30_01F5_CgGrbmCgttSclkOverride_OFFSET 16 -#define FCRxFF30_01F5_CgGrbmCgttSclkOverride_WIDTH 1 -#define FCRxFF30_01F5_CgGrbmCgttSclkOverride_MASK 0x10000 -#define FCRxFF30_01F5_ReservedCgtt49Override_OFFSET 17 -#define FCRxFF30_01F5_ReservedCgtt49Override_WIDTH 1 -#define FCRxFF30_01F5_ReservedCgtt49Override_MASK 0x20000 -#define FCRxFF30_01F5_CgSmuCgttSclkOverride_OFFSET 18 -#define FCRxFF30_01F5_CgSmuCgttSclkOverride_WIDTH 1 -#define FCRxFF30_01F5_CgSmuCgttSclkOverride_MASK 0x40000 -#define FCRxFF30_01F5_ReservedCgtt51Override_OFFSET 19 -#define FCRxFF30_01F5_ReservedCgtt51Override_WIDTH 1 -#define FCRxFF30_01F5_ReservedCgtt51Override_MASK 0x80000 -#define FCRxFF30_01F5_CgIhCgttSclkOverride_OFFSET 20 -#define FCRxFF30_01F5_CgIhCgttSclkOverride_WIDTH 1 -#define FCRxFF30_01F5_CgIhCgttSclkOverride_MASK 0x100000 -#define FCRxFF30_01F5_CgDbgCgttSclkOverride_OFFSET 21 -#define FCRxFF30_01F5_CgDbgCgttSclkOverride_WIDTH 1 -#define FCRxFF30_01F5_CgDbgCgttSclkOverride_MASK 0x200000 -#define FCRxFF30_01F5_CgSemCgttSclkOverride_OFFSET 22 -#define FCRxFF30_01F5_CgSemCgttSclkOverride_WIDTH 1 -#define FCRxFF30_01F5_CgSemCgttSclkOverride_MASK 0x400000 -#define FCRxFF30_01F5_CgSrbmCgttSclkOverride_OFFSET 23 -#define FCRxFF30_01F5_CgSrbmCgttSclkOverride_WIDTH 1 -#define FCRxFF30_01F5_CgSrbmCgttSclkOverride_MASK 0x800000 -#define FCRxFF30_01F5_CgDrmdmaCgttSclkOverride_OFFSET 24 -#define FCRxFF30_01F5_CgDrmdmaCgttSclkOverride_WIDTH 1 -#define FCRxFF30_01F5_CgDrmdmaCgttSclkOverride_MASK 0x1000000 -#define FCRxFF30_01F5_CgUvduCgttSclkOverride_OFFSET 25 -#define FCRxFF30_01F5_CgUvduCgttSclkOverride_WIDTH 1 -#define FCRxFF30_01F5_CgUvduCgttSclkOverride_MASK 0x2000000 -#define FCRxFF30_01F5_CgUvduCgttVclkOverride_OFFSET 26 -#define FCRxFF30_01F5_CgUvduCgttVclkOverride_WIDTH 1 -#define FCRxFF30_01F5_CgUvduCgttVclkOverride_MASK 0x4000000 -#define FCRxFF30_01F5_CgUvduCgttDclkOverride_OFFSET 27 -#define FCRxFF30_01F5_CgUvduCgttDclkOverride_WIDTH 1 -#define FCRxFF30_01F5_CgUvduCgttDclkOverride_MASK 0x8000000 -#define FCRxFF30_01F5_CgDcCgttDispclkOverride_OFFSET 28 -#define FCRxFF30_01F5_CgDcCgttDispclkOverride_WIDTH 1 -#define FCRxFF30_01F5_CgDcCgttDispclkOverride_MASK 0x10000000 -#define FCRxFF30_01F5_CgXbrCgttSclkOverride_OFFSET 29 -#define FCRxFF30_01F5_CgXbrCgttSclkOverride_WIDTH 1 -#define FCRxFF30_01F5_CgXbrCgttSclkOverride_MASK 0x20000000 -#define FCRxFF30_01F5_CgSpimCgtsSclkOverride_OFFSET 30 -#define FCRxFF30_01F5_CgSpimCgtsSclkOverride_WIDTH 1 -#define FCRxFF30_01F5_CgSpimCgtsSclkOverride_MASK 0x40000000 -#define FCRxFF30_01F5_CgSpimCgtsSclkLsOverride_OFFSET 31 -#define FCRxFF30_01F5_CgSpimCgtsSclkLsOverride_WIDTH 1 -#define FCRxFF30_01F5_CgSpimCgtsSclkLsOverride_MASK 0x80000000 - -/// FCRxFF30_01F5 -typedef union { - struct { ///< - UINT32 ReservedCgtt32Override:1 ; ///< - UINT32 ReservedCgtt33Override:1 ; ///< - UINT32 ReservedCgtt34Override:1 ; ///< - UINT32 ReservedCgtt35Override:1 ; ///< - UINT32 CgTaCgttSclkOverride:1 ; ///< - UINT32 CgTdCgttSclkOverride:1 ; ///< - UINT32 CgTcaCgttSclkOverride:1 ; ///< - UINT32 CgTcpCgttSclkOverride:1 ; ///< - UINT32 CgTccCgttSclkOverride:1 ; ///< - UINT32 CgSqCgttSclkOverride:1 ; ///< - UINT32 CgHdpCgttSclkOverride:1 ; ///< - UINT32 CgVmcCgttSclkOverride:1 ; ///< - UINT32 CgOrbCgttSclkOverride:1 ; ///< - UINT32 CgOrbCgttLclkOverride:1 ; ///< - UINT32 CgIocCgttSclkOverride:1 ; ///< - UINT32 CgIocCgttLclkOverride:1 ; ///< - UINT32 CgGrbmCgttSclkOverride:1 ; ///< - UINT32 ReservedCgtt49Override:1 ; ///< - UINT32 CgSmuCgttSclkOverride:1 ; ///< - UINT32 ReservedCgtt51Override:1 ; ///< - UINT32 CgIhCgttSclkOverride:1 ; ///< - UINT32 CgDbgCgttSclkOverride:1 ; ///< - UINT32 CgSemCgttSclkOverride:1 ; ///< - UINT32 CgSrbmCgttSclkOverride:1 ; ///< - UINT32 CgDrmdmaCgttSclkOverride:1 ; ///< - UINT32 CgUvduCgttSclkOverride:1 ; ///< - UINT32 CgUvduCgttVclkOverride:1 ; ///< - UINT32 CgUvduCgttDclkOverride:1 ; ///< - UINT32 CgDcCgttDispclkOverride:1 ; ///< - UINT32 CgXbrCgttSclkOverride:1 ; ///< - UINT32 CgSpimCgtsSclkOverride:1 ; ///< - UINT32 CgSpimCgtsSclkLsOverride:1 ; ///< - } Field; ///< - UINT32 Value; ///< -} FCRxFF30_01F5_STRUCT; - -// **** FCRxFF30_0398 Register Definition **** -// Address -#define FCRxFF30_0398_ADDRESS 0xff300398 - -// Type -#define FCRxFF30_0398_TYPE TYPE_FCR -// Field Data -#define FCRxFF30_0398_Reserved_0_0_OFFSET 0 -#define FCRxFF30_0398_Reserved_0_0_WIDTH 1 -#define FCRxFF30_0398_Reserved_0_0_MASK 0x1 -#define FCRxFF30_0398_SoftResetBif_OFFSET 1 -#define FCRxFF30_0398_SoftResetBif_WIDTH 1 -#define FCRxFF30_0398_SoftResetBif_MASK 0x2 -#define FCRxFF30_0398_SoftResetCg_OFFSET 2 -#define FCRxFF30_0398_SoftResetCg_WIDTH 1 -#define FCRxFF30_0398_SoftResetCg_MASK 0x4 -#define FCRxFF30_0398_Reserved_4_3_OFFSET 3 -#define FCRxFF30_0398_Reserved_4_3_WIDTH 2 -#define FCRxFF30_0398_Reserved_4_3_MASK 0x18 -#define FCRxFF30_0398_SoftResetDc_OFFSET 5 -#define FCRxFF30_0398_SoftResetDc_WIDTH 1 -#define FCRxFF30_0398_SoftResetDc_MASK 0x20 -#define FCRxFF30_0398_Reserved_6_6_OFFSET 6 -#define FCRxFF30_0398_Reserved_6_6_WIDTH 1 -#define FCRxFF30_0398_Reserved_6_6_MASK 0x40 -#define FCRxFF30_0398_SoftResetDrm_OFFSET 7 -#define FCRxFF30_0398_SoftResetDrm_WIDTH 1 -#define FCRxFF30_0398_SoftResetDrm_MASK 0x80 -#define FCRxFF30_0398_SoftResetGrbm_OFFSET 8 -#define FCRxFF30_0398_SoftResetGrbm_WIDTH 1 -#define FCRxFF30_0398_SoftResetGrbm_MASK 0x100 -#define FCRxFF30_0398_SoftResetHdp_OFFSET 9 -#define FCRxFF30_0398_SoftResetHdp_WIDTH 1 -#define FCRxFF30_0398_SoftResetHdp_MASK 0x200 -#define FCRxFF30_0398_SoftResetIh_OFFSET 10 -#define FCRxFF30_0398_SoftResetIh_WIDTH 1 -#define FCRxFF30_0398_SoftResetIh_MASK 0x400 -#define FCRxFF30_0398_SoftResetMc_OFFSET 11 -#define FCRxFF30_0398_SoftResetMc_WIDTH 1 -#define FCRxFF30_0398_SoftResetMc_MASK 0x800 -#define FCRxFF30_0398_Reserved_12_12_OFFSET 12 -#define FCRxFF30_0398_Reserved_12_12_WIDTH 1 -#define FCRxFF30_0398_Reserved_12_12_MASK 0x1000 -#define FCRxFF30_0398_SoftResetRlc_OFFSET 13 -#define FCRxFF30_0398_SoftResetRlc_WIDTH 1 -#define FCRxFF30_0398_SoftResetRlc_MASK 0x2000 -#define FCRxFF30_0398_SoftResetRom_OFFSET 14 -#define FCRxFF30_0398_SoftResetRom_WIDTH 1 -#define FCRxFF30_0398_SoftResetRom_MASK 0x4000 -#define FCRxFF30_0398_SoftResetSem_OFFSET 15 -#define FCRxFF30_0398_SoftResetSem_WIDTH 1 -#define FCRxFF30_0398_SoftResetSem_MASK 0x8000 -#define FCRxFF30_0398_Reserved_16_16_OFFSET 16 -#define FCRxFF30_0398_Reserved_16_16_WIDTH 1 -#define FCRxFF30_0398_Reserved_16_16_MASK 0x10000 -#define FCRxFF30_0398_SoftResetVmc_OFFSET 17 -#define FCRxFF30_0398_SoftResetVmc_WIDTH 1 -#define FCRxFF30_0398_SoftResetVmc_MASK 0x20000 -#define FCRxFF30_0398_SoftResetUvd_OFFSET 18 -#define FCRxFF30_0398_SoftResetUvd_WIDTH 1 -#define FCRxFF30_0398_SoftResetUvd_MASK 0x40000 -#define FCRxFF30_0398_Reserved_19_19_OFFSET 19 -#define FCRxFF30_0398_Reserved_19_19_WIDTH 1 -#define FCRxFF30_0398_Reserved_19_19_MASK 0x80000 -#define FCRxFF30_0398_SoftResetDrmdma_OFFSET 20 -#define FCRxFF30_0398_SoftResetDrmdma_WIDTH 1 -#define FCRxFF30_0398_SoftResetDrmdma_MASK 0x100000 -#define FCRxFF30_0398_SoftResetTst_OFFSET 21 -#define FCRxFF30_0398_SoftResetTst_WIDTH 1 -#define FCRxFF30_0398_SoftResetTst_MASK 0x200000 -#define FCRxFF30_0398_SoftResetRegbb_OFFSET 22 -#define FCRxFF30_0398_SoftResetRegbb_WIDTH 1 -#define FCRxFF30_0398_SoftResetRegbb_MASK 0x400000 -#define FCRxFF30_0398_SoftResetOrb_OFFSET 23 -#define FCRxFF30_0398_SoftResetOrb_WIDTH 1 -#define FCRxFF30_0398_SoftResetOrb_MASK 0x800000 -#define FCRxFF30_0398_Reserved_31_24_OFFSET 24 -#define FCRxFF30_0398_Reserved_31_24_WIDTH 8 -#define FCRxFF30_0398_Reserved_31_24_MASK 0xff000000 - -/// FCRxFF30_0398 -typedef union { - struct { ///< - UINT32 Reserved_0_0:1 ; ///< - UINT32 SoftResetBif:1 ; ///< - UINT32 SoftResetCg:1 ; ///< - UINT32 Reserved_4_3:2 ; ///< - UINT32 SoftResetDc:1 ; ///< - UINT32 Reserved_6_6:1 ; ///< - UINT32 SoftResetDrm:1 ; ///< - UINT32 SoftResetGrbm:1 ; ///< - UINT32 SoftResetHdp:1 ; ///< - UINT32 SoftResetIh:1 ; ///< - UINT32 SoftResetMc:1 ; ///< - UINT32 Reserved_12_12:1 ; ///< - UINT32 SoftResetRlc:1 ; ///< - UINT32 SoftResetRom:1 ; ///< - UINT32 SoftResetSem:1 ; ///< - UINT32 Reserved_16_16:1 ; ///< - UINT32 SoftResetVmc:1 ; ///< - UINT32 SoftResetUvd:1 ; ///< - UINT32 Reserved_19_19:1 ; ///< - UINT32 SoftResetDrmdma:1 ; ///< - UINT32 SoftResetTst:1 ; ///< - UINT32 SoftResetRegbb:1 ; ///< - UINT32 SoftResetOrb:1 ; ///< - UINT32 Reserved_31_24:8 ; ///< - } Field; ///< - UINT32 Value; ///< -} FCRxFF30_0398_STRUCT; - -// **** FCRxFF30_1512 Register Definition **** -// Address -#define FCRxFF30_1512_ADDRESS 0xff301512 - -// Type -#define FCRxFF30_1512_TYPE TYPE_FCR -// Field Data -#define FCRxFF30_1512_Reserved_30_0_OFFSET 0 -#define FCRxFF30_1512_Reserved_30_0_WIDTH 31 -#define FCRxFF30_1512_Reserved_30_0_MASK 0x7fffffff -#define FCRxFF30_1512_SoftOverride0_OFFSET 31 -#define FCRxFF30_1512_SoftOverride0_WIDTH 1 -#define FCRxFF30_1512_SoftOverride0_MASK 0x80000000 - -/// FCRxFF30_1512 -typedef union { - struct { ///< - UINT32 Reserved_30_0:31; ///< - UINT32 SoftOverride0:1 ; ///< - } Field; ///< - UINT32 Value; ///< -} FCRxFF30_1512_STRUCT; - -// **** FCRxFF30_1529 Register Definition **** -// Address -#define FCRxFF30_1529_ADDRESS 0xff301529 - -// Type -#define FCRxFF30_1529_TYPE TYPE_FCR -// Field Data -#define FCRxFF30_1529_DelayCnt_OFFSET 0 -#define FCRxFF30_1529_DelayCnt_WIDTH 6 -#define FCRxFF30_1529_DelayCnt_MASK 0x3f -#define FCRxFF30_1529_Reserved_31_6_OFFSET 6 -#define FCRxFF30_1529_Reserved_31_6_WIDTH 26 -#define FCRxFF30_1529_Reserved_31_6_MASK 0xffffffc0 - -/// FCRxFF30_1529 -typedef union { - struct { ///< - UINT32 DelayCnt:6 ; ///< - UINT32 Reserved_31_6:26; ///< - } Field; ///< - UINT32 Value; ///< -} FCRxFF30_1529_STRUCT; - -// **** D0F0x64_x00 Register Definition **** -// Address -#define D0F0x64_x00_ADDRESS 0x0 - -// Type -#define D0F0x64_x00_TYPE TYPE_D0F0x64 -// Field Data -#define D0F0x64_x00_Reserved_5_0_OFFSET 0 -#define D0F0x64_x00_Reserved_5_0_WIDTH 6 -#define D0F0x64_x00_Reserved_5_0_MASK 0x3f -#define D0F0x64_x00_NbFchCfgEn_OFFSET 6 -#define D0F0x64_x00_NbFchCfgEn_WIDTH 1 -#define D0F0x64_x00_NbFchCfgEn_MASK 0x40 -#define D0F0x64_x00_HwInitWrLock_OFFSET 7 -#define D0F0x64_x00_HwInitWrLock_WIDTH 1 -#define D0F0x64_x00_HwInitWrLock_MASK 0x80 -#define D0F0x64_x00_Reserved_31_8_OFFSET 8 -#define D0F0x64_x00_Reserved_31_8_WIDTH 24 -#define D0F0x64_x00_Reserved_31_8_MASK 0xffffff00 - -/// D0F0x64_x00 -typedef union { - struct { ///< - UINT32 Reserved_5_0:6 ; ///< - UINT32 NbFchCfgEn:1 ; ///< - UINT32 HwInitWrLock:1 ; ///< - UINT32 Reserved_31_8:24; ///< - } Field; ///< - UINT32 Value; ///< -} D0F0x64_x00_STRUCT; - -// **** D0F0x64_x0B Register Definition **** -// Address -#define D0F0x64_x0B_ADDRESS 0xb - -// Type -#define D0F0x64_x0B_TYPE TYPE_D0F0x64 -// Field Data -#define D0F0x64_x0B_Reserved_19_0_OFFSET 0 -#define D0F0x64_x0B_Reserved_19_0_WIDTH 20 -#define D0F0x64_x0B_Reserved_19_0_MASK 0xfffff -#define D0F0x64_x0B_SetPowEn_OFFSET 20 -#define D0F0x64_x0B_SetPowEn_WIDTH 1 -#define D0F0x64_x0B_SetPowEn_MASK 0x100000 -#define D0F0x64_x0B_IocFchSetPowEn_OFFSET 21 -#define D0F0x64_x0B_IocFchSetPowEn_WIDTH 1 -#define D0F0x64_x0B_IocFchSetPowEn_MASK 0x200000 -#define D0F0x64_x0B_Reserved_22_22_OFFSET 22 -#define D0F0x64_x0B_Reserved_22_22_WIDTH 1 -#define D0F0x64_x0B_Reserved_22_22_MASK 0x400000 -#define D0F0x64_x0B_IocFchSetPmeTurnOffEn_OFFSET 23 -#define D0F0x64_x0B_IocFchSetPmeTurnOffEn_WIDTH 1 -#define D0F0x64_x0B_IocFchSetPmeTurnOffEn_MASK 0x800000 -#define D0F0x64_x0B_Reserved_31_24_OFFSET 24 -#define D0F0x64_x0B_Reserved_31_24_WIDTH 8 -#define D0F0x64_x0B_Reserved_31_24_MASK 0xff000000 - -/// D0F0x64_x0B -typedef union { - struct { ///< - UINT32 Reserved_19_0:20; ///< - UINT32 SetPowEn:1 ; ///< - UINT32 IocFchSetPowEn:1 ; ///< - UINT32 Reserved_22_22:1 ; ///< - UINT32 IocFchSetPmeTurnOffEn:1 ; ///< - UINT32 Reserved_31_24:8 ; ///< - } Field; ///< - UINT32 Value; ///< -} D0F0x64_x0B_STRUCT; - -// **** D0F0x64_x0C Register Definition **** -// Address -#define D0F0x64_x0C_ADDRESS 0xc - -// Type -#define D0F0x64_x0C_TYPE TYPE_D0F0x64 -// Field Data -#define D0F0x64_x0C_Reserved_1_0_OFFSET 0 -#define D0F0x64_x0C_Reserved_1_0_WIDTH 2 -#define D0F0x64_x0C_Reserved_1_0_MASK 0x3 -#define D0F0x64_x0C_Dev2BridgeDis_OFFSET 2 -#define D0F0x64_x0C_Dev2BridgeDis_WIDTH 1 -#define D0F0x64_x0C_Dev2BridgeDis_MASK 0x4 -#define D0F0x64_x0C_Dev3BridgeDis_OFFSET 3 -#define D0F0x64_x0C_Dev3BridgeDis_WIDTH 1 -#define D0F0x64_x0C_Dev3BridgeDis_MASK 0x8 -#define D0F0x64_x0C_Dev4BridgeDis_OFFSET 4 -#define D0F0x64_x0C_Dev4BridgeDis_WIDTH 1 -#define D0F0x64_x0C_Dev4BridgeDis_MASK 0x10 -#define D0F0x64_x0C_Dev5BridgeDis_OFFSET 5 -#define D0F0x64_x0C_Dev5BridgeDis_WIDTH 1 -#define D0F0x64_x0C_Dev5BridgeDis_MASK 0x20 -#define D0F0x64_x0C_Dev6BridgeDis_OFFSET 6 -#define D0F0x64_x0C_Dev6BridgeDis_WIDTH 1 -#define D0F0x64_x0C_Dev6BridgeDis_MASK 0x40 -#define D0F0x64_x0C_Dev7BridgeDis_OFFSET 7 -#define D0F0x64_x0C_Dev7BridgeDis_WIDTH 1 -#define D0F0x64_x0C_Dev7BridgeDis_MASK 0x80 -#define D0F0x64_x0C_Reserved_31_8_OFFSET 8 -#define D0F0x64_x0C_Reserved_31_8_WIDTH 24 -#define D0F0x64_x0C_Reserved_31_8_MASK 0xffffff00 - -/// D0F0x64_x0C -typedef union { - struct { ///< - UINT32 Reserved_1_0:2 ; ///< - UINT32 Dev2BridgeDis:1 ; ///< - UINT32 Dev3BridgeDis:1 ; ///< - UINT32 Dev4BridgeDis:1 ; ///< - UINT32 Dev5BridgeDis:1 ; ///< - UINT32 Dev6BridgeDis:1 ; ///< - UINT32 Dev7BridgeDis:1 ; ///< - UINT32 Reserved_31_8:24; ///< - } Field; ///< - UINT32 Value; ///< -} D0F0x64_x0C_STRUCT; - -// **** D0F0x64_x19 Register Definition **** -// Address -#define D0F0x64_x19_ADDRESS 0x19 - -// Type -#define D0F0x64_x19_TYPE TYPE_D0F0x64 -// Field Data -#define D0F0x64_x19_TomEn_OFFSET 0 -#define D0F0x64_x19_TomEn_WIDTH 1 -#define D0F0x64_x19_TomEn_MASK 0x1 -#define D0F0x64_x19_Reserved_22_1_OFFSET 1 -#define D0F0x64_x19_Reserved_22_1_WIDTH 22 -#define D0F0x64_x19_Reserved_22_1_MASK 0x7ffffe -#define D0F0x64_x19_Tom2_31_23__OFFSET 23 -#define D0F0x64_x19_Tom2_31_23__WIDTH 9 -#define D0F0x64_x19_Tom2_31_23__MASK 0xff800000 - -/// D0F0x64_x19 -typedef union { - struct { ///< - UINT32 TomEn:1 ; ///< - UINT32 Reserved_22_1:22; ///< - UINT32 Tom2_31_23_:9 ; ///< - } Field; ///< - UINT32 Value; ///< -} D0F0x64_x19_STRUCT; - -// **** D0F0x64_x1A Register Definition **** -// Address -#define D0F0x64_x1A_ADDRESS 0x1a - -// Type -#define D0F0x64_x1A_TYPE TYPE_D0F0x64 -// Field Data -#define D0F0x64_x1A_Tom2_39_32__OFFSET 0 -#define D0F0x64_x1A_Tom2_39_32__WIDTH 8 -#define D0F0x64_x1A_Tom2_39_32__MASK 0xff -#define D0F0x64_x1A_Reserved_31_8_OFFSET 8 -#define D0F0x64_x1A_Reserved_31_8_WIDTH 24 -#define D0F0x64_x1A_Reserved_31_8_MASK 0xffffff00 - -/// D0F0x64_x1A -typedef union { - struct { ///< - UINT32 Tom2_39_32_:8 ; ///< - UINT32 Reserved_31_8:24; ///< - } Field; ///< - UINT32 Value; ///< -} D0F0x64_x1A_STRUCT; - -// **** D0F0x64_x1D Register Definition **** -// Address -#define D0F0x64_x1D_ADDRESS 0x1d - -// Type -#define D0F0x64_x1D_TYPE TYPE_D0F0x64 -// Field Data -#define D0F0x64_x1D_IntGfxAsPcieEn_OFFSET 0 -#define D0F0x64_x1D_IntGfxAsPcieEn_WIDTH 1 -#define D0F0x64_x1D_IntGfxAsPcieEn_MASK 0x1 -#define D0F0x64_x1D_VgaEn_OFFSET 1 -#define D0F0x64_x1D_VgaEn_WIDTH 1 -#define D0F0x64_x1D_VgaEn_MASK 0x2 -#define D0F0x64_x1D_Reserved_2_2_OFFSET 2 -#define D0F0x64_x1D_Reserved_2_2_WIDTH 1 -#define D0F0x64_x1D_Reserved_2_2_MASK 0x4 -#define D0F0x64_x1D_Vga16En_OFFSET 3 -#define D0F0x64_x1D_Vga16En_WIDTH 1 -#define D0F0x64_x1D_Vga16En_MASK 0x8 -#define D0F0x64_x1D_Reserved_31_4_OFFSET 4 -#define D0F0x64_x1D_Reserved_31_4_WIDTH 28 -#define D0F0x64_x1D_Reserved_31_4_MASK 0xfffffff0 - -/// D0F0x64_x1D -typedef union { - struct { ///< - UINT32 IntGfxAsPcieEn:1 ; ///< - UINT32 VgaEn:1 ; ///< - UINT32 Reserved_2_2:1 ; ///< - UINT32 Vga16En:1 ; ///< - UINT32 Reserved_31_4:28; ///< - } Field; ///< - UINT32 Value; ///< -} D0F0x64_x1D_STRUCT; - -// **** D0F0x64_x20 Register Definition **** -// Address -#define D0F0x64_x20_ADDRESS 0x20 - -// Type -#define D0F0x64_x20_TYPE TYPE_D0F0x64 -// Field Data -#define D0F0x64_x20_Reserved_0_0_OFFSET 0 -#define D0F0x64_x20_Reserved_0_0_WIDTH 1 -#define D0F0x64_x20_Reserved_0_0_MASK 0x1 -#define D0F0x64_x20_IocPcieDevRemapDis_OFFSET 1 -#define D0F0x64_x20_IocPcieDevRemapDis_WIDTH 1 -#define D0F0x64_x20_IocPcieDevRemapDis_MASK 0x2 -#define D0F0x64_x20_Reserved_31_2_OFFSET 2 -#define D0F0x64_x20_Reserved_31_2_WIDTH 30 -#define D0F0x64_x20_Reserved_31_2_MASK 0xfffffffc - -/// D0F0x64_x20 -typedef union { - struct { ///< - UINT32 Reserved_0_0:1 ; ///< - UINT32 IocPcieDevRemapDis:1 ; ///< - UINT32 Reserved_31_2:30; ///< - } Field; ///< - UINT32 Value; ///< -} D0F0x64_x20_STRUCT; - -// **** D0F0x64_x22 Register Definition **** -// Address -#define D0F0x64_x22_ADDRESS 0x22 - -// Type -#define D0F0x64_x22_TYPE TYPE_D0F0x64 -// Field Data -#define D0F0x64_x22_Reserved_3_0_OFFSET 0 -#define D0F0x64_x22_Reserved_3_0_WIDTH 4 -#define D0F0x64_x22_Reserved_3_0_MASK 0xf -#define D0F0x64_x22_OffHysteresis_OFFSET 4 -#define D0F0x64_x22_OffHysteresis_WIDTH 8 -#define D0F0x64_x22_OffHysteresis_MASK 0xff0 -#define D0F0x64_x22_Reserved_25_12_OFFSET 12 -#define D0F0x64_x22_Reserved_25_12_WIDTH 14 -#define D0F0x64_x22_Reserved_25_12_MASK 0x3fff000 -#define D0F0x64_x22_SoftOverrideClk4_OFFSET 26 -#define D0F0x64_x22_SoftOverrideClk4_WIDTH 1 -#define D0F0x64_x22_SoftOverrideClk4_MASK 0x4000000 -#define D0F0x64_x22_SoftOverrideClk3_OFFSET 27 -#define D0F0x64_x22_SoftOverrideClk3_WIDTH 1 -#define D0F0x64_x22_SoftOverrideClk3_MASK 0x8000000 -#define D0F0x64_x22_SoftOverrideClk2_OFFSET 28 -#define D0F0x64_x22_SoftOverrideClk2_WIDTH 1 -#define D0F0x64_x22_SoftOverrideClk2_MASK 0x10000000 -#define D0F0x64_x22_SoftOverrideClk1_OFFSET 29 -#define D0F0x64_x22_SoftOverrideClk1_WIDTH 1 -#define D0F0x64_x22_SoftOverrideClk1_MASK 0x20000000 -#define D0F0x64_x22_SoftOverrideClk0_OFFSET 30 -#define D0F0x64_x22_SoftOverrideClk0_WIDTH 1 -#define D0F0x64_x22_SoftOverrideClk0_MASK 0x40000000 -#define D0F0x64_x22_Reserved_31_31_OFFSET 31 -#define D0F0x64_x22_Reserved_31_31_WIDTH 1 -#define D0F0x64_x22_Reserved_31_31_MASK 0x80000000 - -/// D0F0x64_x22 -typedef union { - struct { ///< - UINT32 Reserved_3_0:4 ; ///< - UINT32 OffHysteresis:8 ; ///< - UINT32 Reserved_25_12:14; ///< - UINT32 SoftOverrideClk4:1 ; ///< - UINT32 SoftOverrideClk3:1 ; ///< - UINT32 SoftOverrideClk2:1 ; ///< - UINT32 SoftOverrideClk1:1 ; ///< - UINT32 SoftOverrideClk0:1 ; ///< - UINT32 Reserved_31_31:1 ; ///< - } Field; ///< - UINT32 Value; ///< -} D0F0x64_x22_STRUCT; - -// **** D0F0x64_x23 Register Definition **** -// Address -#define D0F0x64_x23_ADDRESS 0x23 - -// Type -#define D0F0x64_x23_TYPE TYPE_D0F0x64 -// Field Data -#define D0F0x64_x23_Reserved_3_0_OFFSET 0 -#define D0F0x64_x23_Reserved_3_0_WIDTH 4 -#define D0F0x64_x23_Reserved_3_0_MASK 0xf -#define D0F0x64_x23_OffHysteresis_OFFSET 4 -#define D0F0x64_x23_OffHysteresis_WIDTH 8 -#define D0F0x64_x23_OffHysteresis_MASK 0xff0 -#define D0F0x64_x23_Reserved_25_12_OFFSET 12 -#define D0F0x64_x23_Reserved_25_12_WIDTH 14 -#define D0F0x64_x23_Reserved_25_12_MASK 0x3fff000 -#define D0F0x64_x23_SoftOverrideClk4_OFFSET 26 -#define D0F0x64_x23_SoftOverrideClk4_WIDTH 1 -#define D0F0x64_x23_SoftOverrideClk4_MASK 0x4000000 -#define D0F0x64_x23_SoftOverrideClk3_OFFSET 27 -#define D0F0x64_x23_SoftOverrideClk3_WIDTH 1 -#define D0F0x64_x23_SoftOverrideClk3_MASK 0x8000000 -#define D0F0x64_x23_SoftOverrideClk2_OFFSET 28 -#define D0F0x64_x23_SoftOverrideClk2_WIDTH 1 -#define D0F0x64_x23_SoftOverrideClk2_MASK 0x10000000 -#define D0F0x64_x23_SoftOverrideClk1_OFFSET 29 -#define D0F0x64_x23_SoftOverrideClk1_WIDTH 1 -#define D0F0x64_x23_SoftOverrideClk1_MASK 0x20000000 -#define D0F0x64_x23_SoftOverrideClk0_OFFSET 30 -#define D0F0x64_x23_SoftOverrideClk0_WIDTH 1 -#define D0F0x64_x23_SoftOverrideClk0_MASK 0x40000000 -#define D0F0x64_x23_Reserved_31_31_OFFSET 31 -#define D0F0x64_x23_Reserved_31_31_WIDTH 1 -#define D0F0x64_x23_Reserved_31_31_MASK 0x80000000 - -/// D0F0x64_x23 -typedef union { - struct { ///< - UINT32 Reserved_3_0:4 ; ///< - UINT32 OffHysteresis:8 ; ///< - UINT32 Reserved_25_12:14; ///< - UINT32 SoftOverrideClk4:1 ; ///< - UINT32 SoftOverrideClk3:1 ; ///< - UINT32 SoftOverrideClk2:1 ; ///< - UINT32 SoftOverrideClk1:1 ; ///< - UINT32 SoftOverrideClk0:1 ; ///< - UINT32 Reserved_31_31:1 ; ///< - } Field; ///< - UINT32 Value; ///< -} D0F0x64_x23_STRUCT; - -// **** D0F0x64_x24 Register Definition **** -// Address -#define D0F0x64_x24_ADDRESS 0x24 - -// Type -#define D0F0x64_x24_TYPE TYPE_D0F0x64 -// Field Data -#define D0F0x64_x24_Reserved_3_0_OFFSET 0 -#define D0F0x64_x24_Reserved_3_0_WIDTH 4 -#define D0F0x64_x24_Reserved_3_0_MASK 0xf -#define D0F0x64_x24_OffHysteresis_OFFSET 4 -#define D0F0x64_x24_OffHysteresis_WIDTH 8 -#define D0F0x64_x24_OffHysteresis_MASK 0xff0 -#define D0F0x64_x24_Reserved_28_12_OFFSET 12 -#define D0F0x64_x24_Reserved_28_12_WIDTH 17 -#define D0F0x64_x24_Reserved_28_12_MASK 0x1ffff000 -#define D0F0x64_x24_SoftOverrideClk1_OFFSET 29 -#define D0F0x64_x24_SoftOverrideClk1_WIDTH 1 -#define D0F0x64_x24_SoftOverrideClk1_MASK 0x20000000 -#define D0F0x64_x24_SoftOverrideClk0_OFFSET 30 -#define D0F0x64_x24_SoftOverrideClk0_WIDTH 1 -#define D0F0x64_x24_SoftOverrideClk0_MASK 0x40000000 -#define D0F0x64_x24_Reserved_31_31_OFFSET 31 -#define D0F0x64_x24_Reserved_31_31_WIDTH 1 -#define D0F0x64_x24_Reserved_31_31_MASK 0x80000000 - -/// D0F0x64_x24 -typedef union { - struct { ///< - UINT32 Reserved_3_0:4 ; ///< - UINT32 OffHysteresis:8 ; ///< - UINT32 Reserved_28_12:17; ///< - UINT32 SoftOverrideClk1:1 ; ///< - UINT32 SoftOverrideClk0:1 ; ///< - UINT32 Reserved_31_31:1 ; ///< - } Field; ///< - UINT32 Value; ///< -} D0F0x64_x24_STRUCT; - - -// **** D0F0x64_x4D Register Definition **** -// Address -#define D0F0x64_x4D_ADDRESS 0x4d - -// Type -#define D0F0x64_x4D_TYPE TYPE_D0F0x64 -// Field Data -#define D0F0x64_x4D_WriteData_OFFSET 0 -#define D0F0x64_x4D_WriteData_WIDTH 16 -#define D0F0x64_x4D_WriteData_MASK 0xffff -#define D0F0x64_x4D_SmuAddr_OFFSET 16 -#define D0F0x64_x4D_SmuAddr_WIDTH 8 -#define D0F0x64_x4D_SmuAddr_MASK 0xff0000 -#define D0F0x64_x4D_ReqToggle_OFFSET 24 -#define D0F0x64_x4D_ReqToggle_WIDTH 1 -#define D0F0x64_x4D_ReqToggle_MASK 0x1000000 -#define D0F0x64_x4D_ReqType_OFFSET 25 -#define D0F0x64_x4D_ReqType_WIDTH 1 -#define D0F0x64_x4D_ReqType_MASK 0x2000000 -#define D0F0x64_x4D_Reserved_31_26_OFFSET 26 -#define D0F0x64_x4D_Reserved_31_26_WIDTH 6 -#define D0F0x64_x4D_Reserved_31_26_MASK 0xfc000000 - -/// D0F0x64_x4D -typedef union { - struct { ///< - UINT32 WriteData:16; ///< - UINT32 SmuAddr:8 ; ///< - UINT32 ReqToggle:1 ; ///< - UINT32 ReqType:1 ; ///< - UINT32 Reserved_31_26:6 ; ///< - } Field; ///< - UINT32 Value; ///< -} D0F0x64_x4D_STRUCT; - -// **** D0F0x64_x4E Register Definition **** -// Address -#define D0F0x64_x4E_ADDRESS 0x4e - -// Type -#define D0F0x64_x4E_TYPE TYPE_D0F0x64 -// Field Data -#define D0F0x64_x4E_SmuReadData_OFFSET 0 -#define D0F0x64_x4E_SmuReadData_WIDTH 32 -#define D0F0x64_x4E_SmuReadData_MASK 0xffffffff - -/// D0F0x64_x4E -typedef union { - struct { ///< - UINT32 SmuReadData:32; ///< - } Field; ///< - UINT32 Value; ///< -} D0F0x64_x4E_STRUCT; - -// **** D0F0x64_x53 Register Definition **** -// Address -#define D0F0x64_x53_ADDRESS 0x53 - -// Type -#define D0F0x64_x53_TYPE TYPE_D0F0x64 -// Field Data -#define D0F0x64_x53_Reserved_19_0_OFFSET 0 -#define D0F0x64_x53_Reserved_19_0_WIDTH 20 -#define D0F0x64_x53_Reserved_19_0_MASK 0xfffff -#define D0F0x64_x53_SetPowEn_OFFSET 20 -#define D0F0x64_x53_SetPowEn_WIDTH 1 -#define D0F0x64_x53_SetPowEn_MASK 0x100000 -#define D0F0x64_x53_Reserved_31_21_OFFSET 21 -#define D0F0x64_x53_Reserved_31_21_WIDTH 11 -#define D0F0x64_x53_Reserved_31_21_MASK 0xffe00000 - -/// D0F0x64_x53 -typedef union { - struct { ///< - UINT32 Reserved_19_0:20; ///< - UINT32 SetPowEn:1 ; ///< - UINT32 Reserved_31_21:11; ///< - } Field; ///< - UINT32 Value; ///< -} D0F0x64_x53_STRUCT; - -// **** D0F0x64_x55 Register Definition **** -// Address -#define D0F0x64_x55_ADDRESS 0x55 - -// Type -#define D0F0x64_x55_TYPE TYPE_D0F0x64 -// Field Data -#define D0F0x64_x55_Reserved_19_0_OFFSET 0 -#define D0F0x64_x55_Reserved_19_0_WIDTH 20 -#define D0F0x64_x55_Reserved_19_0_MASK 0xfffff -#define D0F0x64_x55_SetPowEn_OFFSET 20 -#define D0F0x64_x55_SetPowEn_WIDTH 1 -#define D0F0x64_x55_SetPowEn_MASK 0x100000 -#define D0F0x64_x55_Reserved_31_21_OFFSET 21 -#define D0F0x64_x55_Reserved_31_21_WIDTH 11 -#define D0F0x64_x55_Reserved_31_21_MASK 0xffe00000 - -/// D0F0x64_x55 -typedef union { - struct { ///< - UINT32 Reserved_19_0:20; ///< - UINT32 SetPowEn:1 ; ///< - UINT32 Reserved_31_21:11; ///< - } Field; ///< - UINT32 Value; ///< -} D0F0x64_x55_STRUCT; - -// **** D0F0x64_x57 Register Definition **** -// Address -#define D0F0x64_x57_ADDRESS 0x57 - -// Type -#define D0F0x64_x57_TYPE TYPE_D0F0x64 -// Field Data -#define D0F0x64_x57_Reserved_19_0_OFFSET 0 -#define D0F0x64_x57_Reserved_19_0_WIDTH 20 -#define D0F0x64_x57_Reserved_19_0_MASK 0xfffff -#define D0F0x64_x57_SetPowEn_OFFSET 20 -#define D0F0x64_x57_SetPowEn_WIDTH 1 -#define D0F0x64_x57_SetPowEn_MASK 0x100000 -#define D0F0x64_x57_Reserved_31_21_OFFSET 21 -#define D0F0x64_x57_Reserved_31_21_WIDTH 11 -#define D0F0x64_x57_Reserved_31_21_MASK 0xffe00000 - -/// D0F0x64_x57 -typedef union { - struct { ///< - UINT32 Reserved_19_0:20; ///< - UINT32 SetPowEn:1 ; ///< - UINT32 Reserved_31_21:11; ///< - } Field; ///< - UINT32 Value; ///< -} D0F0x64_x57_STRUCT; - -// **** D0F0x64_x59 Register Definition **** -// Address -#define D0F0x64_x59_ADDRESS 0x59 - -// Type -#define D0F0x64_x59_TYPE TYPE_D0F0x64 -// Field Data -#define D0F0x64_x59_Reserved_19_0_OFFSET 0 -#define D0F0x64_x59_Reserved_19_0_WIDTH 20 -#define D0F0x64_x59_Reserved_19_0_MASK 0xfffff -#define D0F0x64_x59_SetPowEn_OFFSET 20 -#define D0F0x64_x59_SetPowEn_WIDTH 1 -#define D0F0x64_x59_SetPowEn_MASK 0x100000 -#define D0F0x64_x59_Reserved_31_21_OFFSET 21 -#define D0F0x64_x59_Reserved_31_21_WIDTH 11 -#define D0F0x64_x59_Reserved_31_21_MASK 0xffe00000 - -/// D0F0x64_x59 -typedef union { - struct { ///< - UINT32 Reserved_19_0:20; ///< - UINT32 SetPowEn:1 ; ///< - UINT32 Reserved_31_21:11; ///< - } Field; ///< - UINT32 Value; ///< -} D0F0x64_x59_STRUCT; - -// **** D0F0x64_x5B Register Definition **** -// Address -#define D0F0x64_x5B_ADDRESS 0x5b - -// Type -#define D0F0x64_x5B_TYPE TYPE_D0F0x64 -// Field Data -#define D0F0x64_x5B_Reserved_19_0_OFFSET 0 -#define D0F0x64_x5B_Reserved_19_0_WIDTH 20 -#define D0F0x64_x5B_Reserved_19_0_MASK 0xfffff -#define D0F0x64_x5B_SetPowEn_OFFSET 20 -#define D0F0x64_x5B_SetPowEn_WIDTH 1 -#define D0F0x64_x5B_SetPowEn_MASK 0x100000 -#define D0F0x64_x5B_Reserved_31_21_OFFSET 21 -#define D0F0x64_x5B_Reserved_31_21_WIDTH 11 -#define D0F0x64_x5B_Reserved_31_21_MASK 0xffe00000 - -/// D0F0x64_x5B -typedef union { - struct { ///< - UINT32 Reserved_19_0:20; ///< - UINT32 SetPowEn:1 ; ///< - UINT32 Reserved_31_21:11; ///< - } Field; ///< - UINT32 Value; ///< -} D0F0x64_x5B_STRUCT; - -// **** D0F0x64_x6A Register Definition **** -// Address -#define D0F0x64_x6A_ADDRESS 0x6a - -// Type -#define D0F0x64_x6A_TYPE TYPE_D0F0x64 -// Field Data -#define D0F0x64_x6A_VoltageForceEn_OFFSET 0 -#define D0F0x64_x6A_VoltageForceEn_WIDTH 1 -#define D0F0x64_x6A_VoltageForceEn_MASK 0x1 -#define D0F0x64_x6A_VoltageChangeEn_OFFSET 1 -#define D0F0x64_x6A_VoltageChangeEn_WIDTH 1 -#define D0F0x64_x6A_VoltageChangeEn_MASK 0x2 -#define D0F0x64_x6A_VoltageChangeReq_OFFSET 2 -#define D0F0x64_x6A_VoltageChangeReq_WIDTH 1 -#define D0F0x64_x6A_VoltageChangeReq_MASK 0x4 -#define D0F0x64_x6A_VoltageLevel_OFFSET 3 -#define D0F0x64_x6A_VoltageLevel_WIDTH 2 -#define D0F0x64_x6A_VoltageLevel_MASK 0x18 -#define D0F0x64_x6A_Reserved_31_5_OFFSET 5 -#define D0F0x64_x6A_Reserved_31_5_WIDTH 27 -#define D0F0x64_x6A_Reserved_31_5_MASK 0xffffffe0 - -/// D0F0x64_x6A -typedef union { - struct { ///< - UINT32 VoltageForceEn:1 ; ///< - UINT32 VoltageChangeEn:1 ; ///< - UINT32 VoltageChangeReq:1 ; ///< - UINT32 VoltageLevel:2 ; ///< - UINT32 Reserved_31_5:27; ///< - } Field; ///< - UINT32 Value; ///< -} D0F0x64_x6A_STRUCT; - -// **** D0F0x64_x6B Register Definition **** -// Address -#define D0F0x64_x6B_ADDRESS 0x6b - -// Type -#define D0F0x64_x6B_TYPE TYPE_D0F0x64 -// Field Data -#define D0F0x64_x6B_VoltageChangeAck_OFFSET 0 -#define D0F0x64_x6B_VoltageChangeAck_WIDTH 1 -#define D0F0x64_x6B_VoltageChangeAck_MASK 0x1 -#define D0F0x64_x6B_CurrentVoltageLevel_OFFSET 1 -#define D0F0x64_x6B_CurrentVoltageLevel_WIDTH 2 -#define D0F0x64_x6B_CurrentVoltageLevel_MASK 0x6 -#define D0F0x64_x6B_Reserved_31_3_OFFSET 3 -#define D0F0x64_x6B_Reserved_31_3_WIDTH 29 -#define D0F0x64_x6B_Reserved_31_3_MASK 0xfffffff8 - -/// D0F0x64_x6B -typedef union { - struct { ///< - UINT32 VoltageChangeAck:1 ; ///< - UINT32 CurrentVoltageLevel:2 ; ///< - UINT32 Reserved_31_3:29; ///< - } Field; ///< - UINT32 Value; ///< -} D0F0x64_x6B_STRUCT; - -// **** D0F0x98_x06 Register Definition **** -// Address -#define D0F0x98_x06_ADDRESS 0x6 - -// Type -#define D0F0x98_x06_TYPE TYPE_D0F0x98 -// Field Data -#define D0F0x98_x06_Reserved_25_0_OFFSET 0 -#define D0F0x98_x06_Reserved_25_0_WIDTH 26 -#define D0F0x98_x06_Reserved_25_0_MASK 0x3ffffff -#define D0F0x98_x06_UmiNpMemWrEn_OFFSET 26 -#define D0F0x98_x06_UmiNpMemWrEn_WIDTH 1 -#define D0F0x98_x06_UmiNpMemWrEn_MASK 0x4000000 -#define D0F0x98_x06_Reserved_31_27_OFFSET 27 -#define D0F0x98_x06_Reserved_31_27_WIDTH 5 -#define D0F0x98_x06_Reserved_31_27_MASK 0xf8000000 - -/// D0F0x98_x06 -typedef union { - struct { ///< - UINT32 Reserved_25_0:26; ///< - UINT32 UmiNpMemWrEn:1 ; ///< - UINT32 Reserved_31_27:5 ; ///< - } Field; ///< - UINT32 Value; ///< -} D0F0x98_x06_STRUCT; - -// **** D0F0x98_x07 Register Definition **** -// Address -#define D0F0x98_x07_ADDRESS 0x7 - -// Type -#define D0F0x98_x07_TYPE TYPE_D0F0x98 -// Field Data -#define D0F0x98_x07_IocBwOptEn_OFFSET 0 -#define D0F0x98_x07_IocBwOptEn_WIDTH 1 -#define D0F0x98_x07_IocBwOptEn_MASK 0x1 -#define D0F0x98_x07_Reserved_13_1_OFFSET 1 -#define D0F0x98_x07_Reserved_13_1_WIDTH 13 -#define D0F0x98_x07_Reserved_13_1_MASK 0x3ffe -#define D0F0x98_x07_MSIHTIntConversionEn_OFFSET 14 -#define D0F0x98_x07_MSIHTIntConversionEn_WIDTH 1 -#define D0F0x98_x07_MSIHTIntConversionEn_MASK 0x4000 -#define D0F0x98_x07_DropZeroMaskWrEn_OFFSET 15 -#define D0F0x98_x07_DropZeroMaskWrEn_WIDTH 1 -#define D0F0x98_x07_DropZeroMaskWrEn_MASK 0x8000 -#define D0F0x98_x07_Reserved_31_16_OFFSET 16 -#define D0F0x98_x07_Reserved_31_16_WIDTH 16 -#define D0F0x98_x07_Reserved_31_16_MASK 0xffff0000 - -/// D0F0x98_x07 -typedef union { - struct { ///< - UINT32 IocBwOptEn:1 ; ///< - UINT32 Reserved_13_1:13; ///< - UINT32 MSIHTIntConversionEn:1 ; ///< - UINT32 DropZeroMaskWrEn:1 ; ///< - UINT32 Reserved_31_16:16; ///< - } Field; ///< - UINT32 Value; ///< -} D0F0x98_x07_STRUCT; - -// **** D0F0x98_x08 Register Definition **** -// Address -#define D0F0x98_x08_ADDRESS 0x8 - -// Type -#define D0F0x98_x08_TYPE TYPE_D0F0x98 -// Field Data -#define D0F0x98_x08_NpWrrLenA_OFFSET 0 -#define D0F0x98_x08_NpWrrLenA_WIDTH 8 -#define D0F0x98_x08_NpWrrLenA_MASK 0xff -#define D0F0x98_x08_Reserved_15_8_OFFSET 8 -#define D0F0x98_x08_Reserved_15_8_WIDTH 8 -#define D0F0x98_x08_Reserved_15_8_MASK 0xff00 -#define D0F0x98_x08_NpWrrLenC_OFFSET 16 -#define D0F0x98_x08_NpWrrLenC_WIDTH 8 -#define D0F0x98_x08_NpWrrLenC_MASK 0xff0000 -#define D0F0x98_x08_Reserved_31_24_OFFSET 24 -#define D0F0x98_x08_Reserved_31_24_WIDTH 8 -#define D0F0x98_x08_Reserved_31_24_MASK 0xff000000 - -/// D0F0x98_x08 -typedef union { - struct { ///< - UINT32 NpWrrLenA:8 ; ///< - UINT32 Reserved_15_8:8 ; ///< - UINT32 NpWrrLenC:8 ; ///< - UINT32 Reserved_31_24:8 ; ///< - } Field; ///< - UINT32 Value; ///< -} D0F0x98_x08_STRUCT; - -// **** D0F0x98_x09 Register Definition **** -// Address -#define D0F0x98_x09_ADDRESS 0x9 - -// Type -#define D0F0x98_x09_TYPE TYPE_D0F0x98 -// Field Data -#define D0F0x98_x09_PWrrLenA_OFFSET 0 -#define D0F0x98_x09_PWrrLenA_WIDTH 8 -#define D0F0x98_x09_PWrrLenA_MASK 0xff -#define D0F0x98_x09_Reserved_23_8_OFFSET 8 -#define D0F0x98_x09_Reserved_23_8_WIDTH 16 -#define D0F0x98_x09_Reserved_23_8_MASK 0xffff00 -#define D0F0x98_x09_PWrrLenD_OFFSET 24 -#define D0F0x98_x09_PWrrLenD_WIDTH 8 -#define D0F0x98_x09_PWrrLenD_MASK 0xff000000 - -/// D0F0x98_x09 -typedef union { - struct { ///< - UINT32 PWrrLenA:8 ; ///< - UINT32 Reserved_23_8:16; ///< - UINT32 PWrrLenD:8 ; ///< - } Field; ///< - UINT32 Value; ///< -} D0F0x98_x09_STRUCT; - - -// **** D0F0x98_x0E Register Definition **** -// Address -#define D0F0x98_x0E_ADDRESS 0xe - -// Type -#define D0F0x98_x0E_TYPE TYPE_D0F0x98 -// Field Data -#define D0F0x98_x0E_MsiHtRsvIntRemapEn_OFFSET 0 -#define D0F0x98_x0E_MsiHtRsvIntRemapEn_WIDTH 1 -#define D0F0x98_x0E_MsiHtRsvIntRemapEn_MASK 0x1 -#define D0F0x98_x0E_Reserved_1_1_OFFSET 1 -#define D0F0x98_x0E_Reserved_1_1_WIDTH 1 -#define D0F0x98_x0E_Reserved_1_1_MASK 0x2 -#define D0F0x98_x0E_MsiHtRsvIntMt_OFFSET 2 -#define D0F0x98_x0E_MsiHtRsvIntMt_WIDTH 3 -#define D0F0x98_x0E_MsiHtRsvIntMt_MASK 0x1c -#define D0F0x98_x0E_MsiHtRsvIntRqEoi_OFFSET 5 -#define D0F0x98_x0E_MsiHtRsvIntRqEoi_WIDTH 1 -#define D0F0x98_x0E_MsiHtRsvIntRqEoi_MASK 0x20 -#define D0F0x98_x0E_MsiHtRsvIntDM_OFFSET 6 -#define D0F0x98_x0E_MsiHtRsvIntDM_WIDTH 1 -#define D0F0x98_x0E_MsiHtRsvIntDM_MASK 0x40 -#define D0F0x98_x0E_Reserved_7_7_OFFSET 7 -#define D0F0x98_x0E_Reserved_7_7_WIDTH 1 -#define D0F0x98_x0E_Reserved_7_7_MASK 0x80 -#define D0F0x98_x0E_MsiHtRsvIntDestination_OFFSET 8 -#define D0F0x98_x0E_MsiHtRsvIntDestination_WIDTH 8 -#define D0F0x98_x0E_MsiHtRsvIntDestination_MASK 0xff00 -#define D0F0x98_x0E_MsiHtRsvIntVector_OFFSET 16 -#define D0F0x98_x0E_MsiHtRsvIntVector_WIDTH 8 -#define D0F0x98_x0E_MsiHtRsvIntVector_MASK 0xff0000 -#define D0F0x98_x0E_Reserved_31_24_OFFSET 24 -#define D0F0x98_x0E_Reserved_31_24_WIDTH 8 -#define D0F0x98_x0E_Reserved_31_24_MASK 0xff000000 - -/// D0F0x98_x0E -typedef union { - struct { ///< - UINT32 MsiHtRsvIntRemapEn:1 ; ///< - UINT32 Reserved_1_1:1 ; ///< - UINT32 MsiHtRsvIntMt:3 ; ///< - UINT32 MsiHtRsvIntRqEoi:1 ; ///< - UINT32 MsiHtRsvIntDM:1 ; ///< - UINT32 Reserved_7_7:1 ; ///< - UINT32 MsiHtRsvIntDestination:8 ; ///< - UINT32 MsiHtRsvIntVector:8 ; ///< - UINT32 Reserved_31_24:8 ; ///< - } Field; ///< - UINT32 Value; ///< -} D0F0x98_x0E_STRUCT; - -// **** D0F0x98_x1E Register Definition **** -// Address -#define D0F0x98_x1E_ADDRESS 0x1e - -// Type -#define D0F0x98_x1E_TYPE TYPE_D0F0x98 -// Field Data -#define D0F0x98_x1E_Reserved_0_0_OFFSET 0 -#define D0F0x98_x1E_Reserved_0_0_WIDTH 1 -#define D0F0x98_x1E_Reserved_0_0_MASK 0x1 -#define D0F0x98_x1E_HiPriEn_OFFSET 1 -#define D0F0x98_x1E_HiPriEn_WIDTH 1 -#define D0F0x98_x1E_HiPriEn_MASK 0x2 -#define D0F0x98_x1E_Reserved_31_2_OFFSET 2 -#define D0F0x98_x1E_Reserved_31_2_WIDTH 30 -#define D0F0x98_x1E_Reserved_31_2_MASK 0xfffffffc - -/// D0F0x98_x1E -typedef union { - struct { ///< - UINT32 Reserved_0_0:1 ; ///< - UINT32 HiPriEn:1 ; ///< - UINT32 Reserved_31_2:30; ///< - } Field; ///< - UINT32 Value; ///< -} D0F0x98_x1E_STRUCT; - -// **** D0F0x98_x28 Register Definition **** -// Address -#define D0F0x98_x28_ADDRESS 0x28 - -// Type -#define D0F0x98_x28_TYPE TYPE_D0F0x98 -// Field Data -#define D0F0x98_x28_SmuPmInterfaceEn_OFFSET 0 -#define D0F0x98_x28_SmuPmInterfaceEn_WIDTH 1 -#define D0F0x98_x28_SmuPmInterfaceEn_MASK 0x1 -#define D0F0x98_x28_ForceCoherentIntr_OFFSET 1 -#define D0F0x98_x28_ForceCoherentIntr_WIDTH 1 -#define D0F0x98_x28_ForceCoherentIntr_MASK 0x2 -#define D0F0x98_x28_Reserved_31_2_OFFSET 2 -#define D0F0x98_x28_Reserved_31_2_WIDTH 30 -#define D0F0x98_x28_Reserved_31_2_MASK 0xfffffffc - -/// D0F0x98_x28 -typedef union { - struct { ///< - UINT32 SmuPmInterfaceEn:1 ; ///< - UINT32 ForceCoherentIntr:1 ; ///< - UINT32 Reserved_31_2:30; ///< - } Field; ///< - UINT32 Value; ///< -} D0F0x98_x28_STRUCT; - -// **** D0F0x98_x2C Register Definition **** -// Address -#define D0F0x98_x2C_ADDRESS 0x2c - -// Type -#define D0F0x98_x2C_TYPE TYPE_D0F0x98 -// Field Data -#define D0F0x98_x2C_Reserved_0_0_OFFSET 0 -#define D0F0x98_x2C_Reserved_0_0_WIDTH 1 -#define D0F0x98_x2C_Reserved_0_0_MASK 0x1 -#define D0F0x98_x2C_DynWakeEn_OFFSET 1 -#define D0F0x98_x2C_DynWakeEn_WIDTH 1 -#define D0F0x98_x2C_DynWakeEn_MASK 0x2 -#define D0F0x98_x2C_Reserved_15_2_OFFSET 2 -#define D0F0x98_x2C_Reserved_15_2_WIDTH 14 -#define D0F0x98_x2C_Reserved_15_2_MASK 0xfffc -#define D0F0x98_x2C_WakeHysteresis_OFFSET 16 -#define D0F0x98_x2C_WakeHysteresis_WIDTH 16 -#define D0F0x98_x2C_WakeHysteresis_MASK 0xffff0000 - -/// D0F0x98_x2C -typedef union { - struct { ///< - UINT32 Reserved_0_0:1 ; ///< - UINT32 DynWakeEn:1 ; ///< - UINT32 Reserved_15_2:14; ///< - UINT32 WakeHysteresis:16; ///< - } Field; ///< - UINT32 Value; ///< -} D0F0x98_x2C_STRUCT; - -// **** D0F0x98_x3A Register Definition **** -// Address -#define D0F0x98_x3A_ADDRESS 0x3a - -// Type -#define D0F0x98_x3A_TYPE TYPE_D0F0x98 -// Field Data -#define D0F0x98_x3A_Reserved_2_0_OFFSET 0 -#define D0F0x98_x3A_Reserved_2_0_WIDTH 3 -#define D0F0x98_x3A_Reserved_2_0_MASK 0x7 -#define D0F0x98_x3A_ClumpingEn_OFFSET 3 -#define D0F0x98_x3A_ClumpingEn_WIDTH 1 -#define D0F0x98_x3A_ClumpingEn_MASK 0x8 -#define D0F0x98_x3A_Reserved_31_4_OFFSET 4 -#define D0F0x98_x3A_Reserved_31_4_WIDTH 28 -#define D0F0x98_x3A_Reserved_31_4_MASK 0xfffffff0 - -/// D0F0x98_x3A -typedef union { - struct { ///< - UINT32 Reserved_2_0:3 ; ///< - UINT32 ClumpingEn:1 ; ///< - UINT32 Reserved_31_4:28; ///< - } Field; ///< - UINT32 Value; ///< -} D0F0x98_x3A_STRUCT; - -// **** D0F0x98_x49 Register Definition **** -// Address -#define D0F0x98_x49_ADDRESS 0x49 - -// Type -#define D0F0x98_x49_TYPE TYPE_D0F0x98 -// Field Data -#define D0F0x98_x49_Reserved_3_0_OFFSET 0 -#define D0F0x98_x49_Reserved_3_0_WIDTH 4 -#define D0F0x98_x49_Reserved_3_0_MASK 0xf -#define D0F0x98_x49_OffHysteresis_OFFSET 4 -#define D0F0x98_x49_OffHysteresis_WIDTH 8 -#define D0F0x98_x49_OffHysteresis_MASK 0xff0 -#define D0F0x98_x49_Reserved_23_12_OFFSET 12 -#define D0F0x98_x49_Reserved_23_12_WIDTH 12 -#define D0F0x98_x49_Reserved_23_12_MASK 0xfff000 -#define D0F0x98_x49_SoftOverrideClk6_OFFSET 24 -#define D0F0x98_x49_SoftOverrideClk6_WIDTH 1 -#define D0F0x98_x49_SoftOverrideClk6_MASK 0x1000000 -#define D0F0x98_x49_SoftOverrideClk5_OFFSET 25 -#define D0F0x98_x49_SoftOverrideClk5_WIDTH 1 -#define D0F0x98_x49_SoftOverrideClk5_MASK 0x2000000 -#define D0F0x98_x49_SoftOverrideClk4_OFFSET 26 -#define D0F0x98_x49_SoftOverrideClk4_WIDTH 1 -#define D0F0x98_x49_SoftOverrideClk4_MASK 0x4000000 -#define D0F0x98_x49_SoftOverrideClk3_OFFSET 27 -#define D0F0x98_x49_SoftOverrideClk3_WIDTH 1 -#define D0F0x98_x49_SoftOverrideClk3_MASK 0x8000000 -#define D0F0x98_x49_SoftOverrideClk2_OFFSET 28 -#define D0F0x98_x49_SoftOverrideClk2_WIDTH 1 -#define D0F0x98_x49_SoftOverrideClk2_MASK 0x10000000 -#define D0F0x98_x49_SoftOverrideClk1_OFFSET 29 -#define D0F0x98_x49_SoftOverrideClk1_WIDTH 1 -#define D0F0x98_x49_SoftOverrideClk1_MASK 0x20000000 -#define D0F0x98_x49_SoftOverrideClk0_OFFSET 30 -#define D0F0x98_x49_SoftOverrideClk0_WIDTH 1 -#define D0F0x98_x49_SoftOverrideClk0_MASK 0x40000000 -#define D0F0x98_x49_Reserved_31_31_OFFSET 31 -#define D0F0x98_x49_Reserved_31_31_WIDTH 1 -#define D0F0x98_x49_Reserved_31_31_MASK 0x80000000 - -/// D0F0x98_x49 -typedef union { - struct { ///< - UINT32 Reserved_3_0:4 ; ///< - UINT32 OffHysteresis:8 ; ///< - UINT32 Reserved_23_12:12; ///< - UINT32 SoftOverrideClk6:1 ; ///< - UINT32 SoftOverrideClk5:1 ; ///< - UINT32 SoftOverrideClk4:1 ; ///< - UINT32 SoftOverrideClk3:1 ; ///< - UINT32 SoftOverrideClk2:1 ; ///< - UINT32 SoftOverrideClk1:1 ; ///< - UINT32 SoftOverrideClk0:1 ; ///< - UINT32 Reserved_31_31:1 ; ///< - } Field; ///< - UINT32 Value; ///< -} D0F0x98_x49_STRUCT; - -// **** D0F0x98_x4A Register Definition **** -// Address -#define D0F0x98_x4A_ADDRESS 0x4a - -// Type -#define D0F0x98_x4A_TYPE TYPE_D0F0x98 -// Field Data -#define D0F0x98_x4A_Reserved_3_0_OFFSET 0 -#define D0F0x98_x4A_Reserved_3_0_WIDTH 4 -#define D0F0x98_x4A_Reserved_3_0_MASK 0xf -#define D0F0x98_x4A_OffHysteresis_OFFSET 4 -#define D0F0x98_x4A_OffHysteresis_WIDTH 8 -#define D0F0x98_x4A_OffHysteresis_MASK 0xff0 -#define D0F0x98_x4A_Reserved_23_12_OFFSET 12 -#define D0F0x98_x4A_Reserved_23_12_WIDTH 12 -#define D0F0x98_x4A_Reserved_23_12_MASK 0xfff000 -#define D0F0x98_x4A_SoftOverrideClk6_OFFSET 24 -#define D0F0x98_x4A_SoftOverrideClk6_WIDTH 1 -#define D0F0x98_x4A_SoftOverrideClk6_MASK 0x1000000 -#define D0F0x98_x4A_SoftOverrideClk5_OFFSET 25 -#define D0F0x98_x4A_SoftOverrideClk5_WIDTH 1 -#define D0F0x98_x4A_SoftOverrideClk5_MASK 0x2000000 -#define D0F0x98_x4A_SoftOverrideClk4_OFFSET 26 -#define D0F0x98_x4A_SoftOverrideClk4_WIDTH 1 -#define D0F0x98_x4A_SoftOverrideClk4_MASK 0x4000000 -#define D0F0x98_x4A_SoftOverrideClk3_OFFSET 27 -#define D0F0x98_x4A_SoftOverrideClk3_WIDTH 1 -#define D0F0x98_x4A_SoftOverrideClk3_MASK 0x8000000 -#define D0F0x98_x4A_SoftOverrideClk2_OFFSET 28 -#define D0F0x98_x4A_SoftOverrideClk2_WIDTH 1 -#define D0F0x98_x4A_SoftOverrideClk2_MASK 0x10000000 -#define D0F0x98_x4A_SoftOverrideClk1_OFFSET 29 -#define D0F0x98_x4A_SoftOverrideClk1_WIDTH 1 -#define D0F0x98_x4A_SoftOverrideClk1_MASK 0x20000000 -#define D0F0x98_x4A_SoftOverrideClk0_OFFSET 30 -#define D0F0x98_x4A_SoftOverrideClk0_WIDTH 1 -#define D0F0x98_x4A_SoftOverrideClk0_MASK 0x40000000 -#define D0F0x98_x4A_Reserved_31_31_OFFSET 31 -#define D0F0x98_x4A_Reserved_31_31_WIDTH 1 -#define D0F0x98_x4A_Reserved_31_31_MASK 0x80000000 - -/// D0F0x98_x4A -typedef union { - struct { ///< - UINT32 Reserved_3_0:4 ; ///< - UINT32 OffHysteresis:8 ; ///< - UINT32 Reserved_23_12:12; ///< - UINT32 SoftOverrideClk6:1 ; ///< - UINT32 SoftOverrideClk5:1 ; ///< - UINT32 SoftOverrideClk4:1 ; ///< - UINT32 SoftOverrideClk3:1 ; ///< - UINT32 SoftOverrideClk2:1 ; ///< - UINT32 SoftOverrideClk1:1 ; ///< - UINT32 SoftOverrideClk0:1 ; ///< - UINT32 Reserved_31_31:1 ; ///< - } Field; ///< - UINT32 Value; ///< -} D0F0x98_x4A_STRUCT; - -// **** D0F0x98_x4B Register Definition **** -// Address -#define D0F0x98_x4B_ADDRESS 0x4b - -// Type -#define D0F0x98_x4B_TYPE TYPE_D0F0x98 -// Field Data -#define D0F0x98_x4B_Reserved_3_0_OFFSET 0 -#define D0F0x98_x4B_Reserved_3_0_WIDTH 4 -#define D0F0x98_x4B_Reserved_3_0_MASK 0xf -#define D0F0x98_x4B_OffHysteresis_OFFSET 4 -#define D0F0x98_x4B_OffHysteresis_WIDTH 8 -#define D0F0x98_x4B_OffHysteresis_MASK 0xff0 -#define D0F0x98_x4B_Reserved_29_12_OFFSET 12 -#define D0F0x98_x4B_Reserved_29_12_WIDTH 18 -#define D0F0x98_x4B_Reserved_29_12_MASK 0x3ffff000 -#define D0F0x98_x4B_SoftOverrideClk_OFFSET 30 -#define D0F0x98_x4B_SoftOverrideClk_WIDTH 1 -#define D0F0x98_x4B_SoftOverrideClk_MASK 0x40000000 -#define D0F0x98_x4B_Reserved_31_31_OFFSET 31 -#define D0F0x98_x4B_Reserved_31_31_WIDTH 1 -#define D0F0x98_x4B_Reserved_31_31_MASK 0x80000000 - -/// D0F0x98_x4B -typedef union { - struct { ///< - UINT32 Reserved_3_0:4 ; ///< - UINT32 OffHysteresis:8 ; ///< - UINT32 Reserved_29_12:18; ///< - UINT32 SoftOverrideClk:1 ; ///< - UINT32 Reserved_31_31:1 ; ///< - } Field; ///< - UINT32 Value; ///< -} D0F0x98_x4B_STRUCT; - -// **** D0F0xE4_WRAP_0080 Register Definition **** -// Address -#define D0F0xE4_WRAP_0080_ADDRESS 0x80 - -// Type -#define D0F0xE4_WRAP_0080_TYPE TYPE_D0F0xE4 -// Field Data -#define D0F0xE4_WRAP_0080_StrapBifLinkConfig_OFFSET 0 -#define D0F0xE4_WRAP_0080_StrapBifLinkConfig_WIDTH 4 -#define D0F0xE4_WRAP_0080_StrapBifLinkConfig_MASK 0xf -#define D0F0xE4_WRAP_0080_Reserved_31_4_OFFSET 4 -#define D0F0xE4_WRAP_0080_Reserved_31_4_WIDTH 28 -#define D0F0xE4_WRAP_0080_Reserved_31_4_MASK 0xfffffff0 - -/// D0F0xE4_WRAP_0080 -typedef union { - struct { ///< - UINT32 StrapBifLinkConfig:4 ; ///< - UINT32 Reserved_31_4:28; ///< - } Field; ///< - UINT32 Value; ///< -} D0F0xE4_WRAP_0080_STRUCT; - -// **** D0F0xE4_WRAP_0800 Register Definition **** -// Address -#define D0F0xE4_WRAP_0800_ADDRESS 0x800 - -// Type -#define D0F0xE4_WRAP_0800_TYPE TYPE_D0F0xE4 -// Field Data -#define D0F0xE4_WRAP_0800_HoldTraining_OFFSET 0 -#define D0F0xE4_WRAP_0800_HoldTraining_WIDTH 1 -#define D0F0xE4_WRAP_0800_HoldTraining_MASK 0x1 -#define D0F0xE4_WRAP_0800_Reserved_31_1_OFFSET 1 -#define D0F0xE4_WRAP_0800_Reserved_31_1_WIDTH 31 -#define D0F0xE4_WRAP_0800_Reserved_31_1_MASK 0xfffffffe - -/// D0F0xE4_WRAP_0800 -typedef union { - struct { ///< - UINT32 HoldTraining:1 ; ///< - UINT32 Reserved_31_1:31; ///< - } Field; ///< - UINT32 Value; ///< -} D0F0xE4_WRAP_0800_STRUCT; - -// **** D0F0xE4_WRAP_0803 Register Definition **** -// Address -#define D0F0xE4_WRAP_0803_ADDRESS 0x803 - -// Type -#define D0F0xE4_WRAP_0803_TYPE TYPE_D0F0xE4 -// Field Data -#define D0F0xE4_WRAP_0803_Reserved_4_0_OFFSET 0 -#define D0F0xE4_WRAP_0803_Reserved_4_0_WIDTH 5 -#define D0F0xE4_WRAP_0803_Reserved_4_0_MASK 0x1f -#define D0F0xE4_WRAP_0803_StrapBifDeemphasisSel_OFFSET 5 -#define D0F0xE4_WRAP_0803_StrapBifDeemphasisSel_WIDTH 1 -#define D0F0xE4_WRAP_0803_StrapBifDeemphasisSel_MASK 0x20 -#define D0F0xE4_WRAP_0803_Reserved_31_6_OFFSET 6 -#define D0F0xE4_WRAP_0803_Reserved_31_6_WIDTH 26 -#define D0F0xE4_WRAP_0803_Reserved_31_6_MASK 0xffffffc0 - -/// D0F0xE4_WRAP_0803 -typedef union { - struct { ///< - UINT32 Reserved_4_0:5 ; ///< - UINT32 StrapBifDeemphasisSel:1 ; ///< - UINT32 Reserved_31_6:26; ///< - } Field; ///< - UINT32 Value; ///< -} D0F0xE4_WRAP_0803_STRUCT; - -// **** D0F0xE4_WRAP_0903 Register Definition **** -// Address -#define D0F0xE4_WRAP_0903_ADDRESS 0x903 - -// Type -#define D0F0xE4_WRAP_0903_TYPE TYPE_D0F0xE4 -// Field Data -#define D0F0xE4_WRAP_0903_Reserved_4_0_OFFSET 0 -#define D0F0xE4_WRAP_0903_Reserved_4_0_WIDTH 5 -#define D0F0xE4_WRAP_0903_Reserved_4_0_MASK 0x1f -#define D0F0xE4_WRAP_0903_StrapBifDeemphasisSel_OFFSET 5 -#define D0F0xE4_WRAP_0903_StrapBifDeemphasisSel_WIDTH 1 -#define D0F0xE4_WRAP_0903_StrapBifDeemphasisSel_MASK 0x20 -#define D0F0xE4_WRAP_0903_Reserved_31_6_OFFSET 6 -#define D0F0xE4_WRAP_0903_Reserved_31_6_WIDTH 26 -#define D0F0xE4_WRAP_0903_Reserved_31_6_MASK 0xffffffc0 - -/// D0F0xE4_WRAP_0903 -typedef union { - struct { ///< - UINT32 Reserved_4_0:5 ; ///< - UINT32 StrapBifDeemphasisSel:1 ; ///< - UINT32 Reserved_31_6:26; ///< - } Field; ///< - UINT32 Value; ///< -} D0F0xE4_WRAP_0903_STRUCT; - -// **** D0F0xE4_WRAP_8002 Register Definition **** -// Address -#define D0F0xE4_WRAP_8002_ADDRESS 0x8002 - -// Type -#define D0F0xE4_WRAP_8002_TYPE TYPE_D0F0xE4 -// Field Data -#define D0F0xE4_WRAP_8002_PcieWrapScratch_OFFSET 0 -#define D0F0xE4_WRAP_8002_PcieWrapScratch_WIDTH 32 -#define D0F0xE4_WRAP_8002_PcieWrapScratch_MASK 0xffffffff - -/// D0F0xE4_WRAP_8002 -typedef union { - struct { ///< - UINT32 PcieWrapScratch:32; ///< - } Field; ///< - UINT32 Value; ///< -} D0F0xE4_WRAP_8002_STRUCT; - -// **** D0F0xE4_WRAP_8011 Register Definition **** -// Address -#define D0F0xE4_WRAP_8011_ADDRESS 0x8011 - -// Type -#define D0F0xE4_WRAP_8011_TYPE TYPE_D0F0xE4 -// Field Data -#define D0F0xE4_WRAP_8011_TxclkDynGateLatency_OFFSET 0 -#define D0F0xE4_WRAP_8011_TxclkDynGateLatency_WIDTH 6 -#define D0F0xE4_WRAP_8011_TxclkDynGateLatency_MASK 0x3f -#define D0F0xE4_WRAP_8011_TxclkPermGateEven_OFFSET 6 -#define D0F0xE4_WRAP_8011_TxclkPermGateEven_WIDTH 1 -#define D0F0xE4_WRAP_8011_TxclkPermGateEven_MASK 0x40 -#define D0F0xE4_WRAP_8011_TxclkDynGateEnable_OFFSET 7 -#define D0F0xE4_WRAP_8011_TxclkDynGateEnable_WIDTH 1 -#define D0F0xE4_WRAP_8011_TxclkDynGateEnable_MASK 0x80 -#define D0F0xE4_WRAP_8011_TxclkPermStop_OFFSET 8 -#define D0F0xE4_WRAP_8011_TxclkPermStop_WIDTH 1 -#define D0F0xE4_WRAP_8011_TxclkPermStop_MASK 0x100 -#define D0F0xE4_WRAP_8011_TxclkRegsGateEnable_OFFSET 9 -#define D0F0xE4_WRAP_8011_TxclkRegsGateEnable_WIDTH 1 -#define D0F0xE4_WRAP_8011_TxclkRegsGateEnable_MASK 0x200 -#define D0F0xE4_WRAP_8011_TxclkRegsGateLatency_OFFSET 10 -#define D0F0xE4_WRAP_8011_TxclkRegsGateLatency_WIDTH 6 -#define D0F0xE4_WRAP_8011_TxclkRegsGateLatency_MASK 0xfc00 -#define D0F0xE4_WRAP_8011_RcvrDetClkEnable_OFFSET 16 -#define D0F0xE4_WRAP_8011_RcvrDetClkEnable_WIDTH 1 -#define D0F0xE4_WRAP_8011_RcvrDetClkEnable_MASK 0x10000 -#define D0F0xE4_WRAP_8011_TxclkPermGateLatency_OFFSET 17 -#define D0F0xE4_WRAP_8011_TxclkPermGateLatency_WIDTH 6 -#define D0F0xE4_WRAP_8011_TxclkPermGateLatency_MASK 0x7e0000 -#define D0F0xE4_WRAP_8011_Reserved_23_23_OFFSET 23 -#define D0F0xE4_WRAP_8011_Reserved_23_23_WIDTH 1 -#define D0F0xE4_WRAP_8011_Reserved_23_23_MASK 0x800000 -#define D0F0xE4_WRAP_8011_TxclkLcntGateEnable_OFFSET 24 -#define D0F0xE4_WRAP_8011_TxclkLcntGateEnable_WIDTH 1 -#define D0F0xE4_WRAP_8011_TxclkLcntGateEnable_MASK 0x1000000 -#define D0F0xE4_WRAP_8011_Reserved_30_25_OFFSET 25 -#define D0F0xE4_WRAP_8011_Reserved_30_25_WIDTH 6 -#define D0F0xE4_WRAP_8011_Reserved_30_25_MASK 0x7e000000 -#define D0F0xE4_WRAP_8011_StrapBifValid_OFFSET 31 -#define D0F0xE4_WRAP_8011_StrapBifValid_WIDTH 1 -#define D0F0xE4_WRAP_8011_StrapBifValid_MASK 0x80000000 - -/// D0F0xE4_WRAP_8011 -typedef union { - struct { ///< - UINT32 TxclkDynGateLatency:6 ; ///< - UINT32 TxclkPermGateEven:1 ; ///< - UINT32 TxclkDynGateEnable:1 ; ///< - UINT32 TxclkPermStop:1 ; ///< - UINT32 TxclkRegsGateEnable:1 ; ///< - UINT32 TxclkRegsGateLatency:6 ; ///< - UINT32 RcvrDetClkEnable:1 ; ///< - UINT32 TxclkPermGateLatency:6 ; ///< - UINT32 Reserved_23_23:1 ; ///< - UINT32 TxclkLcntGateEnable:1 ; ///< - UINT32 Reserved_30_25:6 ; ///< - UINT32 StrapBifValid:1 ; ///< - } Field; ///< - UINT32 Value; ///< -} D0F0xE4_WRAP_8011_STRUCT; - -// **** D0F0xE4_WRAP_8012 Register Definition **** -// Address -#define D0F0xE4_WRAP_8012_ADDRESS 0x8012 - -// Type -#define D0F0xE4_WRAP_8012_TYPE TYPE_D0F0xE4 -// Field Data -#define D0F0xE4_WRAP_8012_Pif1xIdleGateLatency_OFFSET 0 -#define D0F0xE4_WRAP_8012_Pif1xIdleGateLatency_WIDTH 6 -#define D0F0xE4_WRAP_8012_Pif1xIdleGateLatency_MASK 0x3f -#define D0F0xE4_WRAP_8012_Reserved_6_6_OFFSET 6 -#define D0F0xE4_WRAP_8012_Reserved_6_6_WIDTH 1 -#define D0F0xE4_WRAP_8012_Reserved_6_6_MASK 0x40 -#define D0F0xE4_WRAP_8012_Pif1xIdleGateEnable_OFFSET 7 -#define D0F0xE4_WRAP_8012_Pif1xIdleGateEnable_WIDTH 1 -#define D0F0xE4_WRAP_8012_Pif1xIdleGateEnable_MASK 0x80 -#define D0F0xE4_WRAP_8012_Pif1xIdleResumeLatency_OFFSET 8 -#define D0F0xE4_WRAP_8012_Pif1xIdleResumeLatency_WIDTH 6 -#define D0F0xE4_WRAP_8012_Pif1xIdleResumeLatency_MASK 0x3f00 -#define D0F0xE4_WRAP_8012_Reserved_15_14_OFFSET 14 -#define D0F0xE4_WRAP_8012_Reserved_15_14_WIDTH 2 -#define D0F0xE4_WRAP_8012_Reserved_15_14_MASK 0xc000 -#define D0F0xE4_WRAP_8012_Pif2p5xIdleGateLatency_OFFSET 16 -#define D0F0xE4_WRAP_8012_Pif2p5xIdleGateLatency_WIDTH 6 -#define D0F0xE4_WRAP_8012_Pif2p5xIdleGateLatency_MASK 0x3f0000 -#define D0F0xE4_WRAP_8012_Reserved_22_22_OFFSET 22 -#define D0F0xE4_WRAP_8012_Reserved_22_22_WIDTH 1 -#define D0F0xE4_WRAP_8012_Reserved_22_22_MASK 0x400000 -#define D0F0xE4_WRAP_8012_Pif2p5xIdleGateEnable_OFFSET 23 -#define D0F0xE4_WRAP_8012_Pif2p5xIdleGateEnable_WIDTH 1 -#define D0F0xE4_WRAP_8012_Pif2p5xIdleGateEnable_MASK 0x800000 -#define D0F0xE4_WRAP_8012_Pif2p5xIdleResumeLatency_OFFSET 24 -#define D0F0xE4_WRAP_8012_Pif2p5xIdleResumeLatency_WIDTH 6 -#define D0F0xE4_WRAP_8012_Pif2p5xIdleResumeLatency_MASK 0x3f000000 -#define D0F0xE4_WRAP_8012_Reserved_31_30_OFFSET 30 -#define D0F0xE4_WRAP_8012_Reserved_31_30_WIDTH 2 -#define D0F0xE4_WRAP_8012_Reserved_31_30_MASK 0xc0000000 - -/// D0F0xE4_WRAP_8012 -typedef union { - struct { ///< - UINT32 Pif1xIdleGateLatency:6 ; ///< - UINT32 Reserved_6_6:1 ; ///< - UINT32 Pif1xIdleGateEnable:1 ; ///< - UINT32 Pif1xIdleResumeLatency:6 ; ///< - UINT32 Reserved_15_14:2 ; ///< - UINT32 Pif2p5xIdleGateLatency:6 ; ///< - UINT32 Reserved_22_22:1 ; ///< - UINT32 Pif2p5xIdleGateEnable:1 ; ///< - UINT32 Pif2p5xIdleResumeLatency:6 ; ///< - UINT32 Reserved_31_30:2 ; ///< - } Field; ///< - UINT32 Value; ///< -} D0F0xE4_WRAP_8012_STRUCT; - - -// **** D0F0xE4_WRAP_8021 Register Definition **** -// Address -#define D0F0xE4_WRAP_8021_ADDRESS 0x8021 - -// Type -#define D0F0xE4_WRAP_8021_TYPE TYPE_D0F0xE4 -// Field Data -#define D0F0xE4_WRAP_8021_Lanes10_OFFSET 0 -#define D0F0xE4_WRAP_8021_Lanes10_WIDTH 4 -#define D0F0xE4_WRAP_8021_Lanes10_MASK 0xf -#define D0F0xE4_WRAP_8021_Lanes32_OFFSET 4 -#define D0F0xE4_WRAP_8021_Lanes32_WIDTH 4 -#define D0F0xE4_WRAP_8021_Lanes32_MASK 0xf0 -#define D0F0xE4_WRAP_8021_Lanes54_OFFSET 8 -#define D0F0xE4_WRAP_8021_Lanes54_WIDTH 4 -#define D0F0xE4_WRAP_8021_Lanes54_MASK 0xf00 -#define D0F0xE4_WRAP_8021_Lanes76_OFFSET 12 -#define D0F0xE4_WRAP_8021_Lanes76_WIDTH 4 -#define D0F0xE4_WRAP_8021_Lanes76_MASK 0xf000 -#define D0F0xE4_WRAP_8021_Lanes98_OFFSET 16 -#define D0F0xE4_WRAP_8021_Lanes98_WIDTH 4 -#define D0F0xE4_WRAP_8021_Lanes98_MASK 0xf0000 -#define D0F0xE4_WRAP_8021_Lanes1110_OFFSET 20 -#define D0F0xE4_WRAP_8021_Lanes1110_WIDTH 4 -#define D0F0xE4_WRAP_8021_Lanes1110_MASK 0xf00000 -#define D0F0xE4_WRAP_8021_Lanes1312_OFFSET 24 -#define D0F0xE4_WRAP_8021_Lanes1312_WIDTH 4 -#define D0F0xE4_WRAP_8021_Lanes1312_MASK 0xf000000 -#define D0F0xE4_WRAP_8021_Lanes1514_OFFSET 28 -#define D0F0xE4_WRAP_8021_Lanes1514_WIDTH 4 -#define D0F0xE4_WRAP_8021_Lanes1514_MASK 0xf0000000 - -/// D0F0xE4_WRAP_8021 -typedef union { - struct { ///< - UINT32 Lanes10:4 ; ///< - UINT32 Lanes32:4 ; ///< - UINT32 Lanes54:4 ; ///< - UINT32 Lanes76:4 ; ///< - UINT32 Lanes98:4 ; ///< - UINT32 Lanes1110:4 ; ///< - UINT32 Lanes1312:4 ; ///< - UINT32 Lanes1514:4 ; ///< - } Field; ///< - UINT32 Value; ///< -} D0F0xE4_WRAP_8021_STRUCT; - -// **** D0F0xE4_WRAP_8022 Register Definition **** -// Address -#define D0F0xE4_WRAP_8022_ADDRESS 0x8022 - -// Type -#define D0F0xE4_WRAP_8022_TYPE TYPE_D0F0xE4 -// Field Data -#define D0F0xE4_WRAP_8022_Lanes10_OFFSET 0 -#define D0F0xE4_WRAP_8022_Lanes10_WIDTH 4 -#define D0F0xE4_WRAP_8022_Lanes10_MASK 0xf -#define D0F0xE4_WRAP_8022_Lanes32_OFFSET 4 -#define D0F0xE4_WRAP_8022_Lanes32_WIDTH 4 -#define D0F0xE4_WRAP_8022_Lanes32_MASK 0xf0 -#define D0F0xE4_WRAP_8022_Lanes54_OFFSET 8 -#define D0F0xE4_WRAP_8022_Lanes54_WIDTH 4 -#define D0F0xE4_WRAP_8022_Lanes54_MASK 0xf00 -#define D0F0xE4_WRAP_8022_Lanes76_OFFSET 12 -#define D0F0xE4_WRAP_8022_Lanes76_WIDTH 4 -#define D0F0xE4_WRAP_8022_Lanes76_MASK 0xf000 -#define D0F0xE4_WRAP_8022_Lanes98_OFFSET 16 -#define D0F0xE4_WRAP_8022_Lanes98_WIDTH 4 -#define D0F0xE4_WRAP_8022_Lanes98_MASK 0xf0000 -#define D0F0xE4_WRAP_8022_Lanes1110_OFFSET 20 -#define D0F0xE4_WRAP_8022_Lanes1110_WIDTH 4 -#define D0F0xE4_WRAP_8022_Lanes1110_MASK 0xf00000 -#define D0F0xE4_WRAP_8022_Lanes1312_OFFSET 24 -#define D0F0xE4_WRAP_8022_Lanes1312_WIDTH 4 -#define D0F0xE4_WRAP_8022_Lanes1312_MASK 0xf000000 -#define D0F0xE4_WRAP_8022_Lanes1514_OFFSET 28 -#define D0F0xE4_WRAP_8022_Lanes1514_WIDTH 4 -#define D0F0xE4_WRAP_8022_Lanes1514_MASK 0xf0000000 - -/// D0F0xE4_WRAP_8022 -typedef union { - struct { ///< - UINT32 Lanes10:4 ; ///< - UINT32 Lanes32:4 ; ///< - UINT32 Lanes54:4 ; ///< - UINT32 Lanes76:4 ; ///< - UINT32 Lanes98:4 ; ///< - UINT32 Lanes1110:4 ; ///< - UINT32 Lanes1312:4 ; ///< - UINT32 Lanes1514:4 ; ///< - } Field; ///< - UINT32 Value; ///< -} D0F0xE4_WRAP_8022_STRUCT; - -// **** D0F0xE4_WRAP_8023 Register Definition **** -// Address -#define D0F0xE4_WRAP_8023_ADDRESS 0x8023 - -// Type -#define D0F0xE4_WRAP_8023_TYPE TYPE_D0F0xE4 -// Field Data -#define D0F0xE4_WRAP_8023_LaneEnable_OFFSET 0 -#define D0F0xE4_WRAP_8023_LaneEnable_WIDTH 16 -#define D0F0xE4_WRAP_8023_LaneEnable_MASK 0xffff -#define D0F0xE4_WRAP_8023_Reserved_31_16_OFFSET 16 -#define D0F0xE4_WRAP_8023_Reserved_31_16_WIDTH 16 -#define D0F0xE4_WRAP_8023_Reserved_31_16_MASK 0xffff0000 - -/// D0F0xE4_WRAP_8023 -typedef union { - struct { ///< - UINT32 LaneEnable:16; ///< - UINT32 Reserved_31_16:16; ///< - } Field; ///< - UINT32 Value; ///< -} D0F0xE4_WRAP_8023_STRUCT; - -// **** D0F0xE4_WRAP_8025 Register Definition **** -// Address -#define D0F0xE4_WRAP_8025_ADDRESS 0x8025 - -// Type -#define D0F0xE4_WRAP_8025_TYPE TYPE_D0F0xE4 -// Field Data -#define D0F0xE4_WRAP_8025_LMTxPhyCmd0_OFFSET 0 -#define D0F0xE4_WRAP_8025_LMTxPhyCmd0_WIDTH 3 -#define D0F0xE4_WRAP_8025_LMTxPhyCmd0_MASK 0x7 -#define D0F0xE4_WRAP_8025_LMRxPhyCmd0_OFFSET 3 -#define D0F0xE4_WRAP_8025_LMRxPhyCmd0_WIDTH 2 -#define D0F0xE4_WRAP_8025_LMRxPhyCmd0_MASK 0x18 -#define D0F0xE4_WRAP_8025_LMLinkSpeed0_OFFSET 5 -#define D0F0xE4_WRAP_8025_LMLinkSpeed0_WIDTH 1 -#define D0F0xE4_WRAP_8025_LMLinkSpeed0_MASK 0x20 -#define D0F0xE4_WRAP_8025_Reserved_7_6_OFFSET 6 -#define D0F0xE4_WRAP_8025_Reserved_7_6_WIDTH 2 -#define D0F0xE4_WRAP_8025_Reserved_7_6_MASK 0xc0 -#define D0F0xE4_WRAP_8025_LMTxPhyCmd1_OFFSET 8 -#define D0F0xE4_WRAP_8025_LMTxPhyCmd1_WIDTH 3 -#define D0F0xE4_WRAP_8025_LMTxPhyCmd1_MASK 0x700 -#define D0F0xE4_WRAP_8025_LMRxPhyCmd1_OFFSET 11 -#define D0F0xE4_WRAP_8025_LMRxPhyCmd1_WIDTH 2 -#define D0F0xE4_WRAP_8025_LMRxPhyCmd1_MASK 0x1800 -#define D0F0xE4_WRAP_8025_LMLinkSpeed1_OFFSET 13 -#define D0F0xE4_WRAP_8025_LMLinkSpeed1_WIDTH 1 -#define D0F0xE4_WRAP_8025_LMLinkSpeed1_MASK 0x2000 -#define D0F0xE4_WRAP_8025_Reserved_15_14_OFFSET 14 -#define D0F0xE4_WRAP_8025_Reserved_15_14_WIDTH 2 -#define D0F0xE4_WRAP_8025_Reserved_15_14_MASK 0xc000 -#define D0F0xE4_WRAP_8025_LMTxPhyCmd2_OFFSET 16 -#define D0F0xE4_WRAP_8025_LMTxPhyCmd2_WIDTH 3 -#define D0F0xE4_WRAP_8025_LMTxPhyCmd2_MASK 0x70000 -#define D0F0xE4_WRAP_8025_LMRxPhyCmd2_OFFSET 19 -#define D0F0xE4_WRAP_8025_LMRxPhyCmd2_WIDTH 2 -#define D0F0xE4_WRAP_8025_LMRxPhyCmd2_MASK 0x180000 -#define D0F0xE4_WRAP_8025_LMLinkSpeed2_OFFSET 21 -#define D0F0xE4_WRAP_8025_LMLinkSpeed2_WIDTH 1 -#define D0F0xE4_WRAP_8025_LMLinkSpeed2_MASK 0x200000 -#define D0F0xE4_WRAP_8025_Reserved_23_22_OFFSET 22 -#define D0F0xE4_WRAP_8025_Reserved_23_22_WIDTH 2 -#define D0F0xE4_WRAP_8025_Reserved_23_22_MASK 0xc00000 -#define D0F0xE4_WRAP_8025_LMTxPhyCmd3_OFFSET 24 -#define D0F0xE4_WRAP_8025_LMTxPhyCmd3_WIDTH 3 -#define D0F0xE4_WRAP_8025_LMTxPhyCmd3_MASK 0x7000000 -#define D0F0xE4_WRAP_8025_LMRxPhyCmd3_OFFSET 27 -#define D0F0xE4_WRAP_8025_LMRxPhyCmd3_WIDTH 2 -#define D0F0xE4_WRAP_8025_LMRxPhyCmd3_MASK 0x18000000 -#define D0F0xE4_WRAP_8025_LMLinkSpeed3_OFFSET 29 -#define D0F0xE4_WRAP_8025_LMLinkSpeed3_WIDTH 1 -#define D0F0xE4_WRAP_8025_LMLinkSpeed3_MASK 0x20000000 -#define D0F0xE4_WRAP_8025_Reserved_31_30_OFFSET 30 -#define D0F0xE4_WRAP_8025_Reserved_31_30_WIDTH 2 -#define D0F0xE4_WRAP_8025_Reserved_31_30_MASK 0xc0000000 - -/// D0F0xE4_WRAP_8025 -typedef union { - struct { ///< - UINT32 LMTxPhyCmd0:3 ; ///< - UINT32 LMRxPhyCmd0:2 ; ///< - UINT32 LMLinkSpeed0:1 ; ///< - UINT32 Reserved_7_6:2 ; ///< - UINT32 LMTxPhyCmd1:3 ; ///< - UINT32 LMRxPhyCmd1:2 ; ///< - UINT32 LMLinkSpeed1:1 ; ///< - UINT32 Reserved_15_14:2 ; ///< - UINT32 LMTxPhyCmd2:3 ; ///< - UINT32 LMRxPhyCmd2:2 ; ///< - UINT32 LMLinkSpeed2:1 ; ///< - UINT32 Reserved_23_22:2 ; ///< - UINT32 LMTxPhyCmd3:3 ; ///< - UINT32 LMRxPhyCmd3:2 ; ///< - UINT32 LMLinkSpeed3:1 ; ///< - UINT32 Reserved_31_30:2 ; ///< - } Field; ///< - UINT32 Value; ///< -} D0F0xE4_WRAP_8025_STRUCT; - -// **** D0F0xE4_WRAP_8031 Register Definition **** -// Address -#define D0F0xE4_WRAP_8031_ADDRESS 0x8031 - -// Type -#define D0F0xE4_WRAP_8031_TYPE TYPE_D0F0xE4 -// Field Data -#define D0F0xE4_WRAP_8031_LnCntBandwidth_OFFSET 0 -#define D0F0xE4_WRAP_8031_LnCntBandwidth_WIDTH 10 -#define D0F0xE4_WRAP_8031_LnCntBandwidth_MASK 0x3ff -#define D0F0xE4_WRAP_8031_Reserved_15_10_OFFSET 10 -#define D0F0xE4_WRAP_8031_Reserved_15_10_WIDTH 6 -#define D0F0xE4_WRAP_8031_Reserved_15_10_MASK 0xfc00 -#define D0F0xE4_WRAP_8031_LnCntValid_OFFSET 16 -#define D0F0xE4_WRAP_8031_LnCntValid_WIDTH 1 -#define D0F0xE4_WRAP_8031_LnCntValid_MASK 0x10000 -#define D0F0xE4_WRAP_8031_Reserved_31_17_OFFSET 17 -#define D0F0xE4_WRAP_8031_Reserved_31_17_WIDTH 15 -#define D0F0xE4_WRAP_8031_Reserved_31_17_MASK 0xfffe0000 - -/// D0F0xE4_WRAP_8031 -typedef union { - struct { ///< - UINT32 LnCntBandwidth:10; ///< - UINT32 Reserved_15_10:6 ; ///< - UINT32 LnCntValid:1 ; ///< - UINT32 Reserved_31_17:15; ///< - } Field; ///< - UINT32 Value; ///< -} D0F0xE4_WRAP_8031_STRUCT; - -// **** D0F0xE4_WRAP_8040 Register Definition **** -// Address -#define D0F0xE4_WRAP_8040_ADDRESS 0x8040 - -// Type -#define D0F0xE4_WRAP_8040_TYPE TYPE_D0F0xE4 -// Field Data -#define D0F0xE4_WRAP_8040_OwnPhyA_OFFSET 0 -#define D0F0xE4_WRAP_8040_OwnPhyA_WIDTH 1 -#define D0F0xE4_WRAP_8040_OwnPhyA_MASK 0x1 -#define D0F0xE4_WRAP_8040_OwnPhyB_OFFSET 1 -#define D0F0xE4_WRAP_8040_OwnPhyB_WIDTH 1 -#define D0F0xE4_WRAP_8040_OwnPhyB_MASK 0x2 -#define D0F0xE4_WRAP_8040_OwnPhyC_OFFSET 2 -#define D0F0xE4_WRAP_8040_OwnPhyC_WIDTH 1 -#define D0F0xE4_WRAP_8040_OwnPhyC_MASK 0x4 -#define D0F0xE4_WRAP_8040_OwnPhyD_OFFSET 3 -#define D0F0xE4_WRAP_8040_OwnPhyD_WIDTH 1 -#define D0F0xE4_WRAP_8040_OwnPhyD_MASK 0x8 -#define D0F0xE4_WRAP_8040_Reserved_7_4_OFFSET 4 -#define D0F0xE4_WRAP_8040_Reserved_7_4_WIDTH 4 -#define D0F0xE4_WRAP_8040_Reserved_7_4_MASK 0xf0 -#define D0F0xE4_WRAP_8040_DigaPwrdnValue_OFFSET 8 -#define D0F0xE4_WRAP_8040_DigaPwrdnValue_WIDTH 3 -#define D0F0xE4_WRAP_8040_DigaPwrdnValue_MASK 0x700 -#define D0F0xE4_WRAP_8040_Reserved_11_11_OFFSET 11 -#define D0F0xE4_WRAP_8040_Reserved_11_11_WIDTH 1 -#define D0F0xE4_WRAP_8040_Reserved_11_11_MASK 0x800 -#define D0F0xE4_WRAP_8040_DigbPwrdnValue_OFFSET 12 -#define D0F0xE4_WRAP_8040_DigbPwrdnValue_WIDTH 3 -#define D0F0xE4_WRAP_8040_DigbPwrdnValue_MASK 0x7000 -#define D0F0xE4_WRAP_8040_Reserved_15_15_OFFSET 15 -#define D0F0xE4_WRAP_8040_Reserved_15_15_WIDTH 1 -#define D0F0xE4_WRAP_8040_Reserved_15_15_MASK 0x8000 -#define D0F0xE4_WRAP_8040_CntPhyA_OFFSET 16 -#define D0F0xE4_WRAP_8040_CntPhyA_WIDTH 1 -#define D0F0xE4_WRAP_8040_CntPhyA_MASK 0x10000 -#define D0F0xE4_WRAP_8040_CntPhyB_OFFSET 17 -#define D0F0xE4_WRAP_8040_CntPhyB_WIDTH 1 -#define D0F0xE4_WRAP_8040_CntPhyB_MASK 0x20000 -#define D0F0xE4_WRAP_8040_CntPhyC_OFFSET 18 -#define D0F0xE4_WRAP_8040_CntPhyC_WIDTH 1 -#define D0F0xE4_WRAP_8040_CntPhyC_MASK 0x40000 -#define D0F0xE4_WRAP_8040_CntPhyD_OFFSET 19 -#define D0F0xE4_WRAP_8040_CntPhyD_WIDTH 1 -#define D0F0xE4_WRAP_8040_CntPhyD_MASK 0x80000 -#define D0F0xE4_WRAP_8040_CntDigA_OFFSET 20 -#define D0F0xE4_WRAP_8040_CntDigA_WIDTH 1 -#define D0F0xE4_WRAP_8040_CntDigA_MASK 0x100000 -#define D0F0xE4_WRAP_8040_CntDigB_OFFSET 21 -#define D0F0xE4_WRAP_8040_CntDigB_WIDTH 1 -#define D0F0xE4_WRAP_8040_CntDigB_MASK 0x200000 -#define D0F0xE4_WRAP_8040_ChangeLnSpd_OFFSET 22 -#define D0F0xE4_WRAP_8040_ChangeLnSpd_WIDTH 1 -#define D0F0xE4_WRAP_8040_ChangeLnSpd_MASK 0x400000 -#define D0F0xE4_WRAP_8040_Reserved_31_23_OFFSET 23 -#define D0F0xE4_WRAP_8040_Reserved_31_23_WIDTH 9 -#define D0F0xE4_WRAP_8040_Reserved_31_23_MASK 0xff800000 - -/// D0F0xE4_WRAP_8040 -typedef union { - struct { ///< - UINT32 OwnPhyA:1 ; ///< - UINT32 OwnPhyB:1 ; ///< - UINT32 OwnPhyC:1 ; ///< - UINT32 OwnPhyD:1 ; ///< - UINT32 Reserved_7_4:4 ; ///< - UINT32 DigaPwrdnValue:3 ; ///< - UINT32 Reserved_11_11:1 ; ///< - UINT32 DigbPwrdnValue:3 ; ///< - UINT32 Reserved_15_15:1 ; ///< - UINT32 CntPhyA:1 ; ///< - UINT32 CntPhyB:1 ; ///< - UINT32 CntPhyC:1 ; ///< - UINT32 CntPhyD:1 ; ///< - UINT32 CntDigA:1 ; ///< - UINT32 CntDigB:1 ; ///< - UINT32 ChangeLnSpd:1 ; ///< - UINT32 Reserved_31_23:9 ; ///< - } Field; ///< - UINT32 Value; ///< -} D0F0xE4_WRAP_8040_STRUCT; - -// **** D0F0xE4_WRAP_8060 Register Definition **** -// Address -#define D0F0xE4_WRAP_8060_ADDRESS 0x8060 - -// Type -#define D0F0xE4_WRAP_8060_TYPE TYPE_D0F0xE4 -// Field Data -#define D0F0xE4_WRAP_8060_Reconfigure_OFFSET 0 -#define D0F0xE4_WRAP_8060_Reconfigure_WIDTH 1 -#define D0F0xE4_WRAP_8060_Reconfigure_MASK 0x1 -#define D0F0xE4_WRAP_8060_Reserved_1_1_OFFSET 1 -#define D0F0xE4_WRAP_8060_Reserved_1_1_WIDTH 1 -#define D0F0xE4_WRAP_8060_Reserved_1_1_MASK 0x2 -#define D0F0xE4_WRAP_8060_ResetComplete_OFFSET 2 -#define D0F0xE4_WRAP_8060_ResetComplete_WIDTH 1 -#define D0F0xE4_WRAP_8060_ResetComplete_MASK 0x4 -#define D0F0xE4_WRAP_8060_Reserved_15_3_OFFSET 3 -#define D0F0xE4_WRAP_8060_Reserved_15_3_WIDTH 13 -#define D0F0xE4_WRAP_8060_Reserved_15_3_MASK 0xfff8 -#define D0F0xE4_WRAP_8060_BifGlobalReset_OFFSET 16 -#define D0F0xE4_WRAP_8060_BifGlobalReset_WIDTH 1 -#define D0F0xE4_WRAP_8060_BifGlobalReset_MASK 0x10000 -#define D0F0xE4_WRAP_8060_BifCalibrationReset_OFFSET 17 -#define D0F0xE4_WRAP_8060_BifCalibrationReset_WIDTH 1 -#define D0F0xE4_WRAP_8060_BifCalibrationReset_MASK 0x20000 -#define D0F0xE4_WRAP_8060_Reserved_31_18_OFFSET 18 -#define D0F0xE4_WRAP_8060_Reserved_31_18_WIDTH 14 -#define D0F0xE4_WRAP_8060_Reserved_31_18_MASK 0xfffc0000 - -/// D0F0xE4_WRAP_8060 -typedef union { - struct { ///< - UINT32 Reconfigure:1 ; ///< - UINT32 Reserved_1_1:1 ; ///< - UINT32 ResetComplete:1 ; ///< - UINT32 Reserved_15_3:13; ///< - UINT32 BifGlobalReset:1 ; ///< - UINT32 BifCalibrationReset:1 ; ///< - UINT32 Reserved_31_18:14; ///< - } Field; ///< - UINT32 Value; ///< -} D0F0xE4_WRAP_8060_STRUCT; - -// **** D0F0xE4_WRAP_8062 Register Definition **** -// Address -#define D0F0xE4_WRAP_8062_ADDRESS 0x8062 - -// Type -#define D0F0xE4_WRAP_8062_TYPE TYPE_D0F0xE4 -// Field Data -#define D0F0xE4_WRAP_8062_ReconfigureEn_OFFSET 0 -#define D0F0xE4_WRAP_8062_ReconfigureEn_WIDTH 1 -#define D0F0xE4_WRAP_8062_ReconfigureEn_MASK 0x1 -#define D0F0xE4_WRAP_8062_Reserved_1_1_OFFSET 1 -#define D0F0xE4_WRAP_8062_Reserved_1_1_WIDTH 1 -#define D0F0xE4_WRAP_8062_Reserved_1_1_MASK 0x2 -#define D0F0xE4_WRAP_8062_ResetPeriod_OFFSET 2 -#define D0F0xE4_WRAP_8062_ResetPeriod_WIDTH 3 -#define D0F0xE4_WRAP_8062_ResetPeriod_MASK 0x1c -#define D0F0xE4_WRAP_8062_Reserved_9_5_OFFSET 5 -#define D0F0xE4_WRAP_8062_Reserved_9_5_WIDTH 5 -#define D0F0xE4_WRAP_8062_Reserved_9_5_MASK 0x3e0 -#define D0F0xE4_WRAP_8062_BlockOnIdle_OFFSET 10 -#define D0F0xE4_WRAP_8062_BlockOnIdle_WIDTH 1 -#define D0F0xE4_WRAP_8062_BlockOnIdle_MASK 0x400 -#define D0F0xE4_WRAP_8062_ConfigXferMode_OFFSET 11 -#define D0F0xE4_WRAP_8062_ConfigXferMode_WIDTH 1 -#define D0F0xE4_WRAP_8062_ConfigXferMode_MASK 0x800 -#define D0F0xE4_WRAP_8062_Reserved_31_12_OFFSET 12 -#define D0F0xE4_WRAP_8062_Reserved_31_12_WIDTH 20 -#define D0F0xE4_WRAP_8062_Reserved_31_12_MASK 0xfffff000 - -/// D0F0xE4_WRAP_8062 -typedef union { - struct { ///< - UINT32 ReconfigureEn:1 ; ///< - UINT32 Reserved_1_1:1 ; ///< - UINT32 ResetPeriod:3 ; ///< - UINT32 Reserved_9_5:5 ; ///< - UINT32 BlockOnIdle:1 ; ///< - UINT32 ConfigXferMode:1 ; ///< - UINT32 Reserved_31_12:20; ///< - } Field; ///< - UINT32 Value; ///< -} D0F0xE4_WRAP_8062_STRUCT; - -// **** D0F0xE4_WRAP_80F0 Register Definition **** -// Address -#define D0F0xE4_WRAP_80F0_ADDRESS 0x80f0 - -// Type -#define D0F0xE4_WRAP_80F0_TYPE TYPE_D0F0xE4 -// Field Data -#define D0F0xE4_WRAP_80F0_MicroSeconds_OFFSET 0 -#define D0F0xE4_WRAP_80F0_MicroSeconds_WIDTH 32 -#define D0F0xE4_WRAP_80F0_MicroSeconds_MASK 0xffffffff - -/// D0F0xE4_WRAP_80F0 -typedef union { - struct { ///< - UINT32 MicroSeconds:32; ///< - } Field; ///< - UINT32 Value; ///< -} D0F0xE4_WRAP_80F0_STRUCT; - -// **** D0F0xE4_WRAP_80F1 Register Definition **** -// Address -#define D0F0xE4_WRAP_80F1_ADDRESS 0x80f1 - -// Type -#define D0F0xE4_WRAP_80F1_TYPE TYPE_D0F0xE4 -// Field Data -#define D0F0xE4_WRAP_80F1_ClockRate_OFFSET 0 -#define D0F0xE4_WRAP_80F1_ClockRate_WIDTH 8 -#define D0F0xE4_WRAP_80F1_ClockRate_MASK 0xff -#define D0F0xE4_WRAP_80F1_Reserved_31_8_OFFSET 8 -#define D0F0xE4_WRAP_80F1_Reserved_31_8_WIDTH 24 -#define D0F0xE4_WRAP_80F1_Reserved_31_8_MASK 0xffffff00 - -/// D0F0xE4_WRAP_80F1 -typedef union { - struct { ///< - UINT32 ClockRate:8 ; ///< - UINT32 Reserved_31_8:24; ///< - } Field; ///< - UINT32 Value; ///< -} D0F0xE4_WRAP_80F1_STRUCT; - -// **** D0F0xE4_PIF_0010 Register Definition **** -// Address -#define D0F0xE4_PIF_0010_ADDRESS 0x10 - -// Type -#define D0F0xE4_PIF_0010_TYPE TYPE_D0F0xE4 -// Field Data -#define D0F0xE4_PIF_0010_Reserved_3_0_OFFSET 0 -#define D0F0xE4_PIF_0010_Reserved_3_0_WIDTH 4 -#define D0F0xE4_PIF_0010_Reserved_3_0_MASK 0xf -#define D0F0xE4_PIF_0010_EiDetCycleMode_OFFSET 4 -#define D0F0xE4_PIF_0010_EiDetCycleMode_WIDTH 1 -#define D0F0xE4_PIF_0010_EiDetCycleMode_MASK 0x10 -#define D0F0xE4_PIF_0010_Reserved_5_5_OFFSET 5 -#define D0F0xE4_PIF_0010_Reserved_5_5_WIDTH 1 -#define D0F0xE4_PIF_0010_Reserved_5_5_MASK 0x20 -#define D0F0xE4_PIF_0010_RxDetectFifoResetMode_OFFSET 6 -#define D0F0xE4_PIF_0010_RxDetectFifoResetMode_WIDTH 1 -#define D0F0xE4_PIF_0010_RxDetectFifoResetMode_MASK 0x40 -#define D0F0xE4_PIF_0010_RxDetectTxPwrMode_OFFSET 7 -#define D0F0xE4_PIF_0010_RxDetectTxPwrMode_WIDTH 1 -#define D0F0xE4_PIF_0010_RxDetectTxPwrMode_MASK 0x80 -#define D0F0xE4_PIF_0010_Reserved_16_8_OFFSET 8 -#define D0F0xE4_PIF_0010_Reserved_16_8_WIDTH 9 -#define D0F0xE4_PIF_0010_Reserved_16_8_MASK 0x1ff00 -#define D0F0xE4_PIF_0010_Ls2ExitTime_OFFSET 17 -#define D0F0xE4_PIF_0010_Ls2ExitTime_WIDTH 3 -#define D0F0xE4_PIF_0010_Ls2ExitTime_MASK 0xe0000 -#define D0F0xE4_PIF_0010_EiCycleOffTime_OFFSET 20 -#define D0F0xE4_PIF_0010_EiCycleOffTime_WIDTH 3 -#define D0F0xE4_PIF_0010_EiCycleOffTime_MASK 0x700000 -#define D0F0xE4_PIF_0010_Reserved_31_23_OFFSET 23 -#define D0F0xE4_PIF_0010_Reserved_31_23_WIDTH 9 -#define D0F0xE4_PIF_0010_Reserved_31_23_MASK 0xff800000 - -/// D0F0xE4_PIF_0010 -typedef union { - struct { ///< - UINT32 Reserved_3_0:4 ; ///< - UINT32 EiDetCycleMode:1 ; ///< - UINT32 Reserved_5_5:1 ; ///< - UINT32 RxDetectFifoResetMode:1 ; ///< - UINT32 RxDetectTxPwrMode:1 ; ///< - UINT32 Reserved_16_8:9 ; ///< - UINT32 Ls2ExitTime:3 ; ///< - UINT32 EiCycleOffTime:3 ; ///< - UINT32 Reserved_31_23:9 ; ///< - } Field; ///< - UINT32 Value; ///< -} D0F0xE4_PIF_0010_STRUCT; - -// **** D0F0xE4_PIF_0011 Register Definition **** -// Address -#define D0F0xE4_PIF_0011_ADDRESS 0x11 - -// Type -#define D0F0xE4_PIF_0011_TYPE TYPE_D0F0xE4 -// Field Data -#define D0F0xE4_PIF_0011_X2Lane10_OFFSET 0 -#define D0F0xE4_PIF_0011_X2Lane10_WIDTH 1 -#define D0F0xE4_PIF_0011_X2Lane10_MASK 0x1 -#define D0F0xE4_PIF_0011_X2Lane32_OFFSET 1 -#define D0F0xE4_PIF_0011_X2Lane32_WIDTH 1 -#define D0F0xE4_PIF_0011_X2Lane32_MASK 0x2 -#define D0F0xE4_PIF_0011_X2Lane54_OFFSET 2 -#define D0F0xE4_PIF_0011_X2Lane54_WIDTH 1 -#define D0F0xE4_PIF_0011_X2Lane54_MASK 0x4 -#define D0F0xE4_PIF_0011_X2Lane76_OFFSET 3 -#define D0F0xE4_PIF_0011_X2Lane76_WIDTH 1 -#define D0F0xE4_PIF_0011_X2Lane76_MASK 0x8 -#define D0F0xE4_PIF_0011_Reserved_7_4_OFFSET 4 -#define D0F0xE4_PIF_0011_Reserved_7_4_WIDTH 4 -#define D0F0xE4_PIF_0011_Reserved_7_4_MASK 0xf0 -#define D0F0xE4_PIF_0011_X4Lane30_OFFSET 8 -#define D0F0xE4_PIF_0011_X4Lane30_WIDTH 1 -#define D0F0xE4_PIF_0011_X4Lane30_MASK 0x100 -#define D0F0xE4_PIF_0011_X4Lane74_OFFSET 9 -#define D0F0xE4_PIF_0011_X4Lane74_WIDTH 1 -#define D0F0xE4_PIF_0011_X4Lane74_MASK 0x200 -#define D0F0xE4_PIF_0011_Reserved_11_10_OFFSET 10 -#define D0F0xE4_PIF_0011_Reserved_11_10_WIDTH 2 -#define D0F0xE4_PIF_0011_Reserved_11_10_MASK 0xc00 -#define D0F0xE4_PIF_0011_X4Lane52_OFFSET 12 -#define D0F0xE4_PIF_0011_X4Lane52_WIDTH 1 -#define D0F0xE4_PIF_0011_X4Lane52_MASK 0x1000 -#define D0F0xE4_PIF_0011_Reserved_15_13_OFFSET 13 -#define D0F0xE4_PIF_0011_Reserved_15_13_WIDTH 3 -#define D0F0xE4_PIF_0011_Reserved_15_13_MASK 0xe000 -#define D0F0xE4_PIF_0011_X8Lane70_OFFSET 16 -#define D0F0xE4_PIF_0011_X8Lane70_WIDTH 1 -#define D0F0xE4_PIF_0011_X8Lane70_MASK 0x10000 -#define D0F0xE4_PIF_0011_Reserved_24_17_OFFSET 17 -#define D0F0xE4_PIF_0011_Reserved_24_17_WIDTH 8 -#define D0F0xE4_PIF_0011_Reserved_24_17_MASK 0x1fe0000 -#define D0F0xE4_PIF_0011_MultiPif_OFFSET 25 -#define D0F0xE4_PIF_0011_MultiPif_WIDTH 1 -#define D0F0xE4_PIF_0011_MultiPif_MASK 0x2000000 -#define D0F0xE4_PIF_0011_Reserved_31_26_OFFSET 26 -#define D0F0xE4_PIF_0011_Reserved_31_26_WIDTH 6 -#define D0F0xE4_PIF_0011_Reserved_31_26_MASK 0xfc000000 - -/// D0F0xE4_PIF_0011 -typedef union { - struct { ///< - UINT32 X2Lane10:1 ; ///< - UINT32 X2Lane32:1 ; ///< - UINT32 X2Lane54:1 ; ///< - UINT32 X2Lane76:1 ; ///< - UINT32 Reserved_7_4:4 ; ///< - UINT32 X4Lane30:1 ; ///< - UINT32 X4Lane74:1 ; ///< - UINT32 Reserved_11_10:2 ; ///< - UINT32 X4Lane52:1 ; ///< - UINT32 Reserved_15_13:3 ; ///< - UINT32 X8Lane70:1 ; ///< - UINT32 Reserved_24_17:8 ; ///< - UINT32 MultiPif:1 ; ///< - UINT32 Reserved_31_26:6 ; ///< - } Field; ///< - UINT32 Value; ///< -} D0F0xE4_PIF_0011_STRUCT; - -// **** D0F0xE4_PIF_0012 Register Definition **** -// Address -#define D0F0xE4_PIF_0012_ADDRESS 0x12 - -// Type -#define D0F0xE4_PIF_0012_TYPE TYPE_D0F0xE4 -// Field Data -#define D0F0xE4_PIF_0012_TxPowerStateInTxs2_OFFSET 0 -#define D0F0xE4_PIF_0012_TxPowerStateInTxs2_WIDTH 3 -#define D0F0xE4_PIF_0012_TxPowerStateInTxs2_MASK 0x7 -#define D0F0xE4_PIF_0012_ForceRxEnInL0s_OFFSET 3 -#define D0F0xE4_PIF_0012_ForceRxEnInL0s_WIDTH 1 -#define D0F0xE4_PIF_0012_ForceRxEnInL0s_MASK 0x8 -#define D0F0xE4_PIF_0012_RxPowerStateInRxs2_OFFSET 4 -#define D0F0xE4_PIF_0012_RxPowerStateInRxs2_WIDTH 3 -#define D0F0xE4_PIF_0012_RxPowerStateInRxs2_MASK 0x70 -#define D0F0xE4_PIF_0012_PllPowerStateInTxs2_OFFSET 7 -#define D0F0xE4_PIF_0012_PllPowerStateInTxs2_WIDTH 3 -#define D0F0xE4_PIF_0012_PllPowerStateInTxs2_MASK 0x380 -#define D0F0xE4_PIF_0012_PllPowerStateInOff_OFFSET 10 -#define D0F0xE4_PIF_0012_PllPowerStateInOff_WIDTH 3 -#define D0F0xE4_PIF_0012_PllPowerStateInOff_MASK 0x1c00 -#define D0F0xE4_PIF_0012_Reserved_15_13_OFFSET 13 -#define D0F0xE4_PIF_0012_Reserved_15_13_WIDTH 3 -#define D0F0xE4_PIF_0012_Reserved_15_13_MASK 0xe000 -#define D0F0xE4_PIF_0012_Tx2p5clkClockGatingEn_OFFSET 16 -#define D0F0xE4_PIF_0012_Tx2p5clkClockGatingEn_WIDTH 1 -#define D0F0xE4_PIF_0012_Tx2p5clkClockGatingEn_MASK 0x10000 -#define D0F0xE4_PIF_0012_Reserved_23_17_OFFSET 17 -#define D0F0xE4_PIF_0012_Reserved_23_17_WIDTH 7 -#define D0F0xE4_PIF_0012_Reserved_23_17_MASK 0xfe0000 -#define D0F0xE4_PIF_0012_PllRampUpTime_OFFSET 24 -#define D0F0xE4_PIF_0012_PllRampUpTime_WIDTH 3 -#define D0F0xE4_PIF_0012_PllRampUpTime_MASK 0x7000000 -#define D0F0xE4_PIF_0012_Reserved_27_27_OFFSET 27 -#define D0F0xE4_PIF_0012_Reserved_27_27_WIDTH 1 -#define D0F0xE4_PIF_0012_Reserved_27_27_MASK 0x8000000 -#define D0F0xE4_PIF_0012_PllPwrOverrideEn_OFFSET 28 -#define D0F0xE4_PIF_0012_PllPwrOverrideEn_WIDTH 1 -#define D0F0xE4_PIF_0012_PllPwrOverrideEn_MASK 0x10000000 -#define D0F0xE4_PIF_0012_PllPwrOverrideVal_OFFSET 29 -#define D0F0xE4_PIF_0012_PllPwrOverrideVal_WIDTH 3 -#define D0F0xE4_PIF_0012_PllPwrOverrideVal_MASK 0xe0000000 - -/// D0F0xE4_PIF_0012 -typedef union { - struct { ///< - UINT32 TxPowerStateInTxs2:3 ; ///< - UINT32 ForceRxEnInL0s:1 ; ///< - UINT32 RxPowerStateInRxs2:3 ; ///< - UINT32 PllPowerStateInTxs2:3 ; ///< - UINT32 PllPowerStateInOff:3 ; ///< - UINT32 Reserved_15_13:3 ; ///< - UINT32 Tx2p5clkClockGatingEn:1 ; ///< - UINT32 Reserved_23_17:7 ; ///< - UINT32 PllRampUpTime:3 ; ///< - UINT32 Reserved_27_27:1 ; ///< - UINT32 PllPwrOverrideEn:1 ; ///< - UINT32 PllPwrOverrideVal:3 ; ///< - } Field; ///< - UINT32 Value; ///< -} D0F0xE4_PIF_0012_STRUCT; - -// **** D0F0xE4_PIF_0013 Register Definition **** -// Address -#define D0F0xE4_PIF_0013_ADDRESS 0x13 - -// Type -#define D0F0xE4_PIF_0013_TYPE TYPE_D0F0xE4 -// Field Data -#define D0F0xE4_PIF_0013_TxPowerStateInTxs2_OFFSET 0 -#define D0F0xE4_PIF_0013_TxPowerStateInTxs2_WIDTH 3 -#define D0F0xE4_PIF_0013_TxPowerStateInTxs2_MASK 0x7 -#define D0F0xE4_PIF_0013_ForceRxEnInL0s_OFFSET 3 -#define D0F0xE4_PIF_0013_ForceRxEnInL0s_WIDTH 1 -#define D0F0xE4_PIF_0013_ForceRxEnInL0s_MASK 0x8 -#define D0F0xE4_PIF_0013_RxPowerStateInRxs2_OFFSET 4 -#define D0F0xE4_PIF_0013_RxPowerStateInRxs2_WIDTH 3 -#define D0F0xE4_PIF_0013_RxPowerStateInRxs2_MASK 0x70 -#define D0F0xE4_PIF_0013_PllPowerStateInTxs2_OFFSET 7 -#define D0F0xE4_PIF_0013_PllPowerStateInTxs2_WIDTH 3 -#define D0F0xE4_PIF_0013_PllPowerStateInTxs2_MASK 0x380 -#define D0F0xE4_PIF_0013_PllPowerStateInOff_OFFSET 10 -#define D0F0xE4_PIF_0013_PllPowerStateInOff_WIDTH 3 -#define D0F0xE4_PIF_0013_PllPowerStateInOff_MASK 0x1c00 -#define D0F0xE4_PIF_0013_Reserved_15_13_OFFSET 13 -#define D0F0xE4_PIF_0013_Reserved_15_13_WIDTH 3 -#define D0F0xE4_PIF_0013_Reserved_15_13_MASK 0xe000 -#define D0F0xE4_PIF_0013_Tx2p5clkClockGatingEn_OFFSET 16 -#define D0F0xE4_PIF_0013_Tx2p5clkClockGatingEn_WIDTH 1 -#define D0F0xE4_PIF_0013_Tx2p5clkClockGatingEn_MASK 0x10000 -#define D0F0xE4_PIF_0013_Reserved_23_17_OFFSET 17 -#define D0F0xE4_PIF_0013_Reserved_23_17_WIDTH 7 -#define D0F0xE4_PIF_0013_Reserved_23_17_MASK 0xfe0000 -#define D0F0xE4_PIF_0013_PllRampUpTime_OFFSET 24 -#define D0F0xE4_PIF_0013_PllRampUpTime_WIDTH 3 -#define D0F0xE4_PIF_0013_PllRampUpTime_MASK 0x7000000 -#define D0F0xE4_PIF_0013_Reserved_27_27_OFFSET 27 -#define D0F0xE4_PIF_0013_Reserved_27_27_WIDTH 1 -#define D0F0xE4_PIF_0013_Reserved_27_27_MASK 0x8000000 -#define D0F0xE4_PIF_0013_PllPwrOverrideEn_OFFSET 28 -#define D0F0xE4_PIF_0013_PllPwrOverrideEn_WIDTH 1 -#define D0F0xE4_PIF_0013_PllPwrOverrideEn_MASK 0x10000000 -#define D0F0xE4_PIF_0013_PllPwrOverrideVal_OFFSET 29 -#define D0F0xE4_PIF_0013_PllPwrOverrideVal_WIDTH 3 -#define D0F0xE4_PIF_0013_PllPwrOverrideVal_MASK 0xe0000000 - -/// D0F0xE4_PIF_0013 -typedef union { - struct { ///< - UINT32 TxPowerStateInTxs2:3 ; ///< - UINT32 ForceRxEnInL0s:1 ; ///< - UINT32 RxPowerStateInRxs2:3 ; ///< - UINT32 PllPowerStateInTxs2:3 ; ///< - UINT32 PllPowerStateInOff:3 ; ///< - UINT32 Reserved_15_13:3 ; ///< - UINT32 Tx2p5clkClockGatingEn:1 ; ///< - UINT32 Reserved_23_17:7 ; ///< - UINT32 PllRampUpTime:3 ; ///< - UINT32 Reserved_27_27:1 ; ///< - UINT32 PllPwrOverrideEn:1 ; ///< - UINT32 PllPwrOverrideVal:3 ; ///< - } Field; ///< - UINT32 Value; ///< -} D0F0xE4_PIF_0013_STRUCT; - -// **** D0F0xE4_PIF_0015 Register Definition **** -// Address -#define D0F0xE4_PIF_0015_ADDRESS 0x15 - -// Type -#define D0F0xE4_PIF_0015_TYPE TYPE_D0F0xE4 -// Field Data -#define D0F0xE4_PIF_0015_TxPhyStatus00_OFFSET 0 -#define D0F0xE4_PIF_0015_TxPhyStatus00_WIDTH 1 -#define D0F0xE4_PIF_0015_TxPhyStatus00_MASK 0x1 -#define D0F0xE4_PIF_0015_TxPhyStatus01_OFFSET 1 -#define D0F0xE4_PIF_0015_TxPhyStatus01_WIDTH 1 -#define D0F0xE4_PIF_0015_TxPhyStatus01_MASK 0x2 -#define D0F0xE4_PIF_0015_TxPhyStatus02_OFFSET 2 -#define D0F0xE4_PIF_0015_TxPhyStatus02_WIDTH 1 -#define D0F0xE4_PIF_0015_TxPhyStatus02_MASK 0x4 -#define D0F0xE4_PIF_0015_TxPhyStatus03_OFFSET 3 -#define D0F0xE4_PIF_0015_TxPhyStatus03_WIDTH 1 -#define D0F0xE4_PIF_0015_TxPhyStatus03_MASK 0x8 -#define D0F0xE4_PIF_0015_TxPhyStatus04_OFFSET 4 -#define D0F0xE4_PIF_0015_TxPhyStatus04_WIDTH 1 -#define D0F0xE4_PIF_0015_TxPhyStatus04_MASK 0x10 -#define D0F0xE4_PIF_0015_TxPhyStatus05_OFFSET 5 -#define D0F0xE4_PIF_0015_TxPhyStatus05_WIDTH 1 -#define D0F0xE4_PIF_0015_TxPhyStatus05_MASK 0x20 -#define D0F0xE4_PIF_0015_TxPhyStatus06_OFFSET 6 -#define D0F0xE4_PIF_0015_TxPhyStatus06_WIDTH 1 -#define D0F0xE4_PIF_0015_TxPhyStatus06_MASK 0x40 -#define D0F0xE4_PIF_0015_TxPhyStatus07_OFFSET 7 -#define D0F0xE4_PIF_0015_TxPhyStatus07_WIDTH 1 -#define D0F0xE4_PIF_0015_TxPhyStatus07_MASK 0x80 -#define D0F0xE4_PIF_0015_Reserved_31_8_OFFSET 8 -#define D0F0xE4_PIF_0015_Reserved_31_8_WIDTH 24 -#define D0F0xE4_PIF_0015_Reserved_31_8_MASK 0xffffff00 - -/// D0F0xE4_PIF_0015 -typedef union { - struct { ///< - UINT32 TxPhyStatus00:1 ; ///< - UINT32 TxPhyStatus01:1 ; ///< - UINT32 TxPhyStatus02:1 ; ///< - UINT32 TxPhyStatus03:1 ; ///< - UINT32 TxPhyStatus04:1 ; ///< - UINT32 TxPhyStatus05:1 ; ///< - UINT32 TxPhyStatus06:1 ; ///< - UINT32 TxPhyStatus07:1 ; ///< - UINT32 Reserved_31_8:24; ///< - } Field; ///< - UINT32 Value; ///< -} D0F0xE4_PIF_0015_STRUCT; - -// **** D0F0xE4_CORE_0002 Register Definition **** -// Address -#define D0F0xE4_CORE_0002_ADDRESS 0x2 - -// Type -#define D0F0xE4_CORE_0002_TYPE TYPE_D0F0xE4 -// Field Data -#define D0F0xE4_CORE_0002_HwDebug_0__OFFSET 0 -#define D0F0xE4_CORE_0002_HwDebug_0__WIDTH 1 -#define D0F0xE4_CORE_0002_HwDebug_0__MASK 0x1 -#define D0F0xE4_CORE_0002_Reserved_31_1_OFFSET 1 -#define D0F0xE4_CORE_0002_Reserved_31_1_WIDTH 31 -#define D0F0xE4_CORE_0002_Reserved_31_1_MASK 0xfffffffe - -/// D0F0xE4_CORE_0002 -typedef union { - struct { ///< - UINT32 HwDebug_0_:1 ; ///< - UINT32 Reserved_31_1:31; ///< - } Field; ///< - UINT32 Value; ///< -} D0F0xE4_CORE_0002_STRUCT; - - -// **** D0F0xE4_CORE_0011 Register Definition **** -// Address -#define D0F0xE4_CORE_0011_ADDRESS 0x11 - -// Type -#define D0F0xE4_CORE_0011_TYPE TYPE_D0F0xE4 -// Field Data -#define D0F0xE4_CORE_0011_DynClkLatency_OFFSET 0 -#define D0F0xE4_CORE_0011_DynClkLatency_WIDTH 4 -#define D0F0xE4_CORE_0011_DynClkLatency_MASK 0xf -#define D0F0xE4_CORE_0011_Reserved_31_4_OFFSET 4 -#define D0F0xE4_CORE_0011_Reserved_31_4_WIDTH 28 -#define D0F0xE4_CORE_0011_Reserved_31_4_MASK 0xfffffff0 - -/// D0F0xE4_CORE_0011 -typedef union { - struct { ///< - UINT32 DynClkLatency:4 ; ///< - UINT32 Reserved_31_4:28; ///< - } Field; ///< - UINT32 Value; ///< -} D0F0xE4_CORE_0011_STRUCT; - -// **** D0F0xE4_CORE_001C Register Definition **** -// Address -#define D0F0xE4_CORE_001C_ADDRESS 0x1c - -// Type -#define D0F0xE4_CORE_001C_TYPE TYPE_D0F0xE4 -// Field Data -#define D0F0xE4_CORE_001C_TxArbRoundRobinEn_OFFSET 0 -#define D0F0xE4_CORE_001C_TxArbRoundRobinEn_WIDTH 1 -#define D0F0xE4_CORE_001C_TxArbRoundRobinEn_MASK 0x1 -#define D0F0xE4_CORE_001C_TxArbSlvLimit_OFFSET 1 -#define D0F0xE4_CORE_001C_TxArbSlvLimit_WIDTH 5 -#define D0F0xE4_CORE_001C_TxArbSlvLimit_MASK 0x3e -#define D0F0xE4_CORE_001C_TxArbMstLimit_OFFSET 6 -#define D0F0xE4_CORE_001C_TxArbMstLimit_WIDTH 5 -#define D0F0xE4_CORE_001C_TxArbMstLimit_MASK 0x7c0 -#define D0F0xE4_CORE_001C_Reserved_31_11_OFFSET 11 -#define D0F0xE4_CORE_001C_Reserved_31_11_WIDTH 21 -#define D0F0xE4_CORE_001C_Reserved_31_11_MASK 0xfffff800 - -/// D0F0xE4_CORE_001C -typedef union { - struct { ///< - UINT32 TxArbRoundRobinEn:1 ; ///< - UINT32 TxArbSlvLimit:5 ; ///< - UINT32 TxArbMstLimit:5 ; ///< - UINT32 Reserved_31_11:21; ///< - } Field; ///< - UINT32 Value; ///< -} D0F0xE4_CORE_001C_STRUCT; - -// **** D0F0xE4_CORE_0040 Register Definition **** -// Address -#define D0F0xE4_CORE_0040_ADDRESS 0x40 - -// Type -#define D0F0xE4_CORE_0040_TYPE TYPE_D0F0xE4 -// Field Data -#define D0F0xE4_CORE_0040_Reserved_13_0_OFFSET 0 -#define D0F0xE4_CORE_0040_Reserved_13_0_WIDTH 14 -#define D0F0xE4_CORE_0040_Reserved_13_0_MASK 0x3fff -#define D0F0xE4_CORE_0040_PElecIdleMode_OFFSET 14 -#define D0F0xE4_CORE_0040_PElecIdleMode_WIDTH 2 -#define D0F0xE4_CORE_0040_PElecIdleMode_MASK 0xc000 -#define D0F0xE4_CORE_0040_Reserved_31_16_OFFSET 16 -#define D0F0xE4_CORE_0040_Reserved_31_16_WIDTH 16 -#define D0F0xE4_CORE_0040_Reserved_31_16_MASK 0xffff0000 - -/// D0F0xE4_CORE_0040 -typedef union { - struct { ///< - UINT32 Reserved_13_0:14; ///< - UINT32 PElecIdleMode:2 ; ///< - UINT32 Reserved_31_16:16; ///< - } Field; ///< - UINT32 Value; ///< -} D0F0xE4_CORE_0040_STRUCT; - -// **** D0F0xE4_CORE_00B0 Register Definition **** -// Address -#define D0F0xE4_CORE_00B0_ADDRESS 0xb0 - -// Type -#define D0F0xE4_CORE_00B0_TYPE TYPE_D0F0xE4 -// Field Data -#define D0F0xE4_CORE_00B0_Reserved_1_0_OFFSET 0 -#define D0F0xE4_CORE_00B0_Reserved_1_0_WIDTH 2 -#define D0F0xE4_CORE_00B0_Reserved_1_0_MASK 0x3 -#define D0F0xE4_CORE_00B0_StrapF0MsiEn_OFFSET 2 -#define D0F0xE4_CORE_00B0_StrapF0MsiEn_WIDTH 1 -#define D0F0xE4_CORE_00B0_StrapF0MsiEn_MASK 0x4 -#define D0F0xE4_CORE_00B0_Reserved_4_3_OFFSET 3 -#define D0F0xE4_CORE_00B0_Reserved_4_3_WIDTH 2 -#define D0F0xE4_CORE_00B0_Reserved_4_3_MASK 0x18 -#define D0F0xE4_CORE_00B0_StrapF0AerEn_OFFSET 5 -#define D0F0xE4_CORE_00B0_StrapF0AerEn_WIDTH 1 -#define D0F0xE4_CORE_00B0_StrapF0AerEn_MASK 0x20 -#define D0F0xE4_CORE_00B0_Reserved_31_6_OFFSET 6 -#define D0F0xE4_CORE_00B0_Reserved_31_6_WIDTH 26 -#define D0F0xE4_CORE_00B0_Reserved_31_6_MASK 0xffffffc0 - -/// D0F0xE4_CORE_00B0 -typedef union { - struct { ///< - UINT32 Reserved_1_0:2 ; ///< - UINT32 StrapF0MsiEn:1 ; ///< - UINT32 Reserved_4_3:2 ; ///< - UINT32 StrapF0AerEn:1 ; ///< - UINT32 Reserved_31_6:26; ///< - } Field; ///< - UINT32 Value; ///< -} D0F0xE4_CORE_00B0_STRUCT; - -// **** D0F0xE4_CORE_00C0 Register Definition **** -// Address -#define D0F0xE4_CORE_00C0_ADDRESS 0xc0 - -// Type -#define D0F0xE4_CORE_00C0_TYPE TYPE_D0F0xE4 -// Field Data -#define D0F0xE4_CORE_00C0_Reserved_27_0_OFFSET 0 -#define D0F0xE4_CORE_00C0_Reserved_27_0_WIDTH 28 -#define D0F0xE4_CORE_00C0_Reserved_27_0_MASK 0xfffffff -#define D0F0xE4_CORE_00C0_StrapReverseAll_OFFSET 28 -#define D0F0xE4_CORE_00C0_StrapReverseAll_WIDTH 1 -#define D0F0xE4_CORE_00C0_StrapReverseAll_MASK 0x10000000 -#define D0F0xE4_CORE_00C0_StrapMstAdr64En_OFFSET 29 -#define D0F0xE4_CORE_00C0_StrapMstAdr64En_WIDTH 1 -#define D0F0xE4_CORE_00C0_StrapMstAdr64En_MASK 0x20000000 -#define D0F0xE4_CORE_00C0_Reserved_31_30_OFFSET 30 -#define D0F0xE4_CORE_00C0_Reserved_31_30_WIDTH 2 -#define D0F0xE4_CORE_00C0_Reserved_31_30_MASK 0xc0000000 - -/// D0F0xE4_CORE_00C0 -typedef union { - struct { ///< - UINT32 Reserved_27_0:28; ///< - UINT32 StrapReverseAll:1 ; ///< - UINT32 StrapMstAdr64En:1 ; ///< - UINT32 Reserved_31_30:2 ; ///< - } Field; ///< - UINT32 Value; ///< -} D0F0xE4_CORE_00C0_STRUCT; - -// **** D0F0xE4_CORE_00C1 Register Definition **** -// Address -#define D0F0xE4_CORE_00C1_ADDRESS 0xc1 - -// Type -#define D0F0xE4_CORE_00C1_TYPE TYPE_D0F0xE4 -// Field Data -#define D0F0xE4_CORE_00C1_StrapLinkBwNotificationCapEn_OFFSET 0 -#define D0F0xE4_CORE_00C1_StrapLinkBwNotificationCapEn_WIDTH 1 -#define D0F0xE4_CORE_00C1_StrapLinkBwNotificationCapEn_MASK 0x1 -#define D0F0xE4_CORE_00C1_StrapGen2Compliance_OFFSET 1 -#define D0F0xE4_CORE_00C1_StrapGen2Compliance_WIDTH 1 -#define D0F0xE4_CORE_00C1_StrapGen2Compliance_MASK 0x2 -#define D0F0xE4_CORE_00C1_Reserved_31_2_OFFSET 2 -#define D0F0xE4_CORE_00C1_Reserved_31_2_WIDTH 30 -#define D0F0xE4_CORE_00C1_Reserved_31_2_MASK 0xfffffffc - -/// D0F0xE4_CORE_00C1 -typedef union { - struct { ///< - UINT32 StrapLinkBwNotificationCapEn:1 ; ///< - UINT32 StrapGen2Compliance:1 ; ///< - UINT32 Reserved_31_2:30; ///< - } Field; ///< - UINT32 Value; ///< -} D0F0xE4_CORE_00C1_STRUCT; - -// **** D0F0xE4_PHY_0009 Register Definition **** -// Address -#define D0F0xE4_PHY_0009_ADDRESS 0x9 - -// Type -#define D0F0xE4_PHY_0009_TYPE TYPE_D0F0xE4 -// Field Data -#define D0F0xE4_PHY_0009_Reserved_23_0_OFFSET 0 -#define D0F0xE4_PHY_0009_Reserved_23_0_WIDTH 24 -#define D0F0xE4_PHY_0009_Reserved_23_0_MASK 0xffffff -#define D0F0xE4_PHY_0009_ClkOff_OFFSET 24 -#define D0F0xE4_PHY_0009_ClkOff_WIDTH 1 -#define D0F0xE4_PHY_0009_ClkOff_MASK 0x1000000 -#define D0F0xE4_PHY_0009_DisplayStream_OFFSET 25 -#define D0F0xE4_PHY_0009_DisplayStream_WIDTH 1 -#define D0F0xE4_PHY_0009_DisplayStream_MASK 0x2000000 -#define D0F0xE4_PHY_0009_Reserved_27_26_OFFSET 26 -#define D0F0xE4_PHY_0009_Reserved_27_26_WIDTH 2 -#define D0F0xE4_PHY_0009_Reserved_27_26_MASK 0xc000000 -#define D0F0xE4_PHY_0009_CascadedPllSel_OFFSET 28 -#define D0F0xE4_PHY_0009_CascadedPllSel_WIDTH 1 -#define D0F0xE4_PHY_0009_CascadedPllSel_MASK 0x10000000 -#define D0F0xE4_PHY_0009_Reserved_30_29_OFFSET 29 -#define D0F0xE4_PHY_0009_Reserved_30_29_WIDTH 2 -#define D0F0xE4_PHY_0009_Reserved_30_29_MASK 0x60000000 -#define D0F0xE4_PHY_0009_PCIePllSel_OFFSET 31 -#define D0F0xE4_PHY_0009_PCIePllSel_WIDTH 1 -#define D0F0xE4_PHY_0009_PCIePllSel_MASK 0x80000000 - -/// D0F0xE4_PHY_0009 -typedef union { - struct { ///< - UINT32 Reserved_23_0:24; ///< - UINT32 ClkOff:1 ; ///< - UINT32 DisplayStream:1 ; ///< - UINT32 Reserved_27_26:2 ; ///< - UINT32 CascadedPllSel:1 ; ///< - UINT32 Reserved_30_29:2 ; ///< - UINT32 PCIePllSel:1 ; ///< - } Field; ///< - UINT32 Value; ///< -} D0F0xE4_PHY_0009_STRUCT; - -// **** D0F0xE4_PHY_000A Register Definition **** -// Address -#define D0F0xE4_PHY_000A_ADDRESS 0xa - -// Type -#define D0F0xE4_PHY_000A_TYPE TYPE_D0F0xE4 -// Field Data -#define D0F0xE4_PHY_000A_Reserved_23_0_OFFSET 0 -#define D0F0xE4_PHY_000A_Reserved_23_0_WIDTH 24 -#define D0F0xE4_PHY_000A_Reserved_23_0_MASK 0xffffff -#define D0F0xE4_PHY_000A_ClkOff_OFFSET 24 -#define D0F0xE4_PHY_000A_ClkOff_WIDTH 1 -#define D0F0xE4_PHY_000A_ClkOff_MASK 0x1000000 -#define D0F0xE4_PHY_000A_DisplayStream_OFFSET 25 -#define D0F0xE4_PHY_000A_DisplayStream_WIDTH 1 -#define D0F0xE4_PHY_000A_DisplayStream_MASK 0x2000000 -#define D0F0xE4_PHY_000A_Reserved_27_26_OFFSET 26 -#define D0F0xE4_PHY_000A_Reserved_27_26_WIDTH 2 -#define D0F0xE4_PHY_000A_Reserved_27_26_MASK 0xc000000 -#define D0F0xE4_PHY_000A_CascadedPllSel_OFFSET 28 -#define D0F0xE4_PHY_000A_CascadedPllSel_WIDTH 1 -#define D0F0xE4_PHY_000A_CascadedPllSel_MASK 0x10000000 -#define D0F0xE4_PHY_000A_Reserved_30_29_OFFSET 29 -#define D0F0xE4_PHY_000A_Reserved_30_29_WIDTH 2 -#define D0F0xE4_PHY_000A_Reserved_30_29_MASK 0x60000000 -#define D0F0xE4_PHY_000A_PCIePllSel_OFFSET 31 -#define D0F0xE4_PHY_000A_PCIePllSel_WIDTH 1 -#define D0F0xE4_PHY_000A_PCIePllSel_MASK 0x80000000 - -/// D0F0xE4_PHY_000A -typedef union { - struct { ///< - UINT32 Reserved_23_0:24; ///< - UINT32 ClkOff:1 ; ///< - UINT32 DisplayStream:1 ; ///< - UINT32 Reserved_27_26:2 ; ///< - UINT32 CascadedPllSel:1 ; ///< - UINT32 Reserved_30_29:2 ; ///< - UINT32 PCIePllSel:1 ; ///< - } Field; ///< - UINT32 Value; ///< -} D0F0xE4_PHY_000A_STRUCT; - -// **** D0F0xE4_PHY_000B Register Definition **** -// Address -#define D0F0xE4_PHY_000B_ADDRESS 0xb - -// Type -#define D0F0xE4_PHY_000B_TYPE TYPE_D0F0xE4 -// Field Data -#define D0F0xE4_PHY_000B_TxPwrSbiEn_OFFSET 0 -#define D0F0xE4_PHY_000B_TxPwrSbiEn_WIDTH 1 -#define D0F0xE4_PHY_000B_TxPwrSbiEn_MASK 0x1 -#define D0F0xE4_PHY_000B_RxPwrSbiEn_OFFSET 1 -#define D0F0xE4_PHY_000B_RxPwrSbiEn_WIDTH 1 -#define D0F0xE4_PHY_000B_RxPwrSbiEn_MASK 0x2 -#define D0F0xE4_PHY_000B_PcieModeSbiEn_OFFSET 2 -#define D0F0xE4_PHY_000B_PcieModeSbiEn_WIDTH 1 -#define D0F0xE4_PHY_000B_PcieModeSbiEn_MASK 0x4 -#define D0F0xE4_PHY_000B_FreqDivSbiEn_OFFSET 3 -#define D0F0xE4_PHY_000B_FreqDivSbiEn_WIDTH 1 -#define D0F0xE4_PHY_000B_FreqDivSbiEn_MASK 0x8 -#define D0F0xE4_PHY_000B_DllLockSbiEn_OFFSET 4 -#define D0F0xE4_PHY_000B_DllLockSbiEn_WIDTH 1 -#define D0F0xE4_PHY_000B_DllLockSbiEn_MASK 0x10 -#define D0F0xE4_PHY_000B_OffsetCancelSbiEn_OFFSET 5 -#define D0F0xE4_PHY_000B_OffsetCancelSbiEn_WIDTH 1 -#define D0F0xE4_PHY_000B_OffsetCancelSbiEn_MASK 0x20 -#define D0F0xE4_PHY_000B_SkipBitSbiEn_OFFSET 6 -#define D0F0xE4_PHY_000B_SkipBitSbiEn_WIDTH 1 -#define D0F0xE4_PHY_000B_SkipBitSbiEn_MASK 0x40 -#define D0F0xE4_PHY_000B_IncoherentClkSbiEn_OFFSET 7 -#define D0F0xE4_PHY_000B_IncoherentClkSbiEn_WIDTH 1 -#define D0F0xE4_PHY_000B_IncoherentClkSbiEn_MASK 0x80 -#define D0F0xE4_PHY_000B_EiDetSbiEn_OFFSET 8 -#define D0F0xE4_PHY_000B_EiDetSbiEn_WIDTH 1 -#define D0F0xE4_PHY_000B_EiDetSbiEn_MASK 0x100 -#define D0F0xE4_PHY_000B_Reserved_13_9_OFFSET 9 -#define D0F0xE4_PHY_000B_Reserved_13_9_WIDTH 5 -#define D0F0xE4_PHY_000B_Reserved_13_9_MASK 0x3e00 -#define D0F0xE4_PHY_000B_MargPktSbiEn_OFFSET 14 -#define D0F0xE4_PHY_000B_MargPktSbiEn_WIDTH 1 -#define D0F0xE4_PHY_000B_MargPktSbiEn_MASK 0x4000 -#define D0F0xE4_PHY_000B_PllCmpPktSbiEn_OFFSET 15 -#define D0F0xE4_PHY_000B_PllCmpPktSbiEn_WIDTH 1 -#define D0F0xE4_PHY_000B_PllCmpPktSbiEn_MASK 0x8000 -#define D0F0xE4_PHY_000B_Reserved_31_16_OFFSET 16 -#define D0F0xE4_PHY_000B_Reserved_31_16_WIDTH 16 -#define D0F0xE4_PHY_000B_Reserved_31_16_MASK 0xffff0000 - -/// D0F0xE4_PHY_000B -typedef union { - struct { ///< - UINT32 TxPwrSbiEn:1 ; ///< - UINT32 RxPwrSbiEn:1 ; ///< - UINT32 PcieModeSbiEn:1 ; ///< - UINT32 FreqDivSbiEn:1 ; ///< - UINT32 DllLockSbiEn:1 ; ///< - UINT32 OffsetCancelSbiEn:1 ; ///< - UINT32 SkipBitSbiEn:1 ; ///< - UINT32 IncoherentClkSbiEn:1 ; ///< - UINT32 EiDetSbiEn:1 ; ///< - UINT32 Reserved_13_9:5 ; ///< - UINT32 MargPktSbiEn:1 ; ///< - UINT32 PllCmpPktSbiEn:1 ; ///< - UINT32 Reserved_31_16:16; ///< - } Field; ///< - UINT32 Value; ///< -} D0F0xE4_PHY_000B_STRUCT; - -// **** D0F0xE4_PHY_2000 Register Definition **** -// Address -#define D0F0xE4_PHY_2000_ADDRESS 0x2000 - -// Type -#define D0F0xE4_PHY_2000_TYPE TYPE_D0F0xE4 -// Field Data -#define D0F0xE4_PHY_2000_PllPowerDownEn_OFFSET 0 -#define D0F0xE4_PHY_2000_PllPowerDownEn_WIDTH 3 -#define D0F0xE4_PHY_2000_PllPowerDownEn_MASK 0x7 -#define D0F0xE4_PHY_2000_PllAutoPwrDownDis_OFFSET 3 -#define D0F0xE4_PHY_2000_PllAutoPwrDownDis_WIDTH 1 -#define D0F0xE4_PHY_2000_PllAutoPwrDownDis_MASK 0x8 -#define D0F0xE4_PHY_2000_Reserved_31_4_OFFSET 4 -#define D0F0xE4_PHY_2000_Reserved_31_4_WIDTH 28 -#define D0F0xE4_PHY_2000_Reserved_31_4_MASK 0xfffffff0 - -/// D0F0xE4_PHY_2000 -typedef union { - struct { ///< - UINT32 PllPowerDownEn:3 ; ///< - UINT32 PllAutoPwrDownDis:1 ; ///< - UINT32 Reserved_31_4:28; ///< - } Field; ///< - UINT32 Value; ///< -} D0F0xE4_PHY_2000_STRUCT; - - -// **** D0F0xE4_PHY_2005 Register Definition **** -// Address -#define D0F0xE4_PHY_2005_ADDRESS 0x2005 - -// Type -#define D0F0xE4_PHY_2005_TYPE TYPE_D0F0xE4 -// Field Data -#define D0F0xE4_PHY_2005_PllClkFreq_OFFSET 0 -#define D0F0xE4_PHY_2005_PllClkFreq_WIDTH 4 -#define D0F0xE4_PHY_2005_PllClkFreq_MASK 0xf -#define D0F0xE4_PHY_2005_Reserved_8_4_OFFSET 4 -#define D0F0xE4_PHY_2005_Reserved_8_4_WIDTH 5 -#define D0F0xE4_PHY_2005_Reserved_8_4_MASK 0x1f0 -#define D0F0xE4_PHY_2005_PllClkFreqExt_OFFSET 9 -#define D0F0xE4_PHY_2005_PllClkFreqExt_WIDTH 2 -#define D0F0xE4_PHY_2005_PllClkFreqExt_MASK 0x600 -#define D0F0xE4_PHY_2005_Reserved_12_11_OFFSET 11 -#define D0F0xE4_PHY_2005_Reserved_12_11_WIDTH 2 -#define D0F0xE4_PHY_2005_Reserved_12_11_MASK 0x1800 -#define D0F0xE4_PHY_2005_PllMode_OFFSET 13 -#define D0F0xE4_PHY_2005_PllMode_WIDTH 2 -#define D0F0xE4_PHY_2005_PllMode_MASK 0x6000 -#define D0F0xE4_PHY_2005_Reserved_31_15_OFFSET 15 -#define D0F0xE4_PHY_2005_Reserved_31_15_WIDTH 17 -#define D0F0xE4_PHY_2005_Reserved_31_15_MASK 0xffff8000 - -/// D0F0xE4_PHY_2005 -typedef union { - struct { ///< - UINT32 PllClkFreq:4 ; ///< - UINT32 Reserved_8_4:5 ; ///< - UINT32 PllClkFreqExt:2 ; ///< - UINT32 Reserved_12_11:2 ; ///< - UINT32 PllMode:2 ; ///< - UINT32 Reserved_31_15:17; ///< - } Field; ///< - UINT32 Value; ///< -} D0F0xE4_PHY_2005_STRUCT; - -// **** D0F0xE4_PHY_2008 Register Definition **** -// Address -#define D0F0xE4_PHY_2008_ADDRESS 0x2008 - -// Type -#define D0F0xE4_PHY_2008_TYPE TYPE_D0F0xE4 -// Field Data -#define D0F0xE4_PHY_2008_PllControlUpdate_OFFSET 0 -#define D0F0xE4_PHY_2008_PllControlUpdate_WIDTH 1 -#define D0F0xE4_PHY_2008_PllControlUpdate_MASK 0x1 -#define D0F0xE4_PHY_2008_Reserved_22_1_OFFSET 1 -#define D0F0xE4_PHY_2008_Reserved_22_1_WIDTH 22 -#define D0F0xE4_PHY_2008_Reserved_22_1_MASK 0x7ffffe -#define D0F0xE4_PHY_2008_MeasCycCntVal_2_0__OFFSET 23 -#define D0F0xE4_PHY_2008_MeasCycCntVal_2_0__WIDTH 3 -#define D0F0xE4_PHY_2008_MeasCycCntVal_2_0__MASK 0x3800000 -#define D0F0xE4_PHY_2008_Reserved_28_26_OFFSET 26 -#define D0F0xE4_PHY_2008_Reserved_28_26_WIDTH 3 -#define D0F0xE4_PHY_2008_Reserved_28_26_MASK 0x1c000000 -#define D0F0xE4_PHY_2008_VdDetectEn_OFFSET 29 -#define D0F0xE4_PHY_2008_VdDetectEn_WIDTH 1 -#define D0F0xE4_PHY_2008_VdDetectEn_MASK 0x20000000 -#define D0F0xE4_PHY_2008_Reserved_31_30_OFFSET 30 -#define D0F0xE4_PHY_2008_Reserved_31_30_WIDTH 2 -#define D0F0xE4_PHY_2008_Reserved_31_30_MASK 0xc0000000 - -/// D0F0xE4_PHY_2008 -typedef union { - struct { ///< - UINT32 PllControlUpdate:1 ; ///< - UINT32 Reserved_22_1:22; ///< - UINT32 MeasCycCntVal_2_0_:3 ; ///< - UINT32 Reserved_28_26:3 ; ///< - UINT32 VdDetectEn:1 ; ///< - UINT32 Reserved_31_30:2 ; ///< - } Field; ///< - UINT32 Value; ///< -} D0F0xE4_PHY_2008_STRUCT; - -// **** D0F0xE4_PHY_4001 Register Definition **** -// Address -#define D0F0xE4_PHY_4001_ADDRESS 0x4001 - -// Type -#define D0F0xE4_PHY_4001_TYPE TYPE_D0F0xE4 -// Field Data -#define D0F0xE4_PHY_4001_Reserved_14_0_OFFSET 0 -#define D0F0xE4_PHY_4001_Reserved_14_0_WIDTH 15 -#define D0F0xE4_PHY_4001_Reserved_14_0_MASK 0x7fff -#define D0F0xE4_PHY_4001_ForceDccRecalc_OFFSET 15 -#define D0F0xE4_PHY_4001_ForceDccRecalc_WIDTH 1 -#define D0F0xE4_PHY_4001_ForceDccRecalc_MASK 0x8000 -#define D0F0xE4_PHY_4001_Reserved_31_16_OFFSET 16 -#define D0F0xE4_PHY_4001_Reserved_31_16_WIDTH 16 -#define D0F0xE4_PHY_4001_Reserved_31_16_MASK 0xffff0000 - -/// D0F0xE4_PHY_4001 -typedef union { - struct { ///< - UINT32 Reserved_14_0:15; ///< - UINT32 ForceDccRecalc:1 ; ///< - UINT32 Reserved_31_16:16; ///< - } Field; ///< - UINT32 Value; ///< -} D0F0xE4_PHY_4001_STRUCT; - -// **** D0F0xE4_PHY_4002 Register Definition **** -// Address -#define D0F0xE4_PHY_4002_ADDRESS 0x4002 - -// Type -#define D0F0xE4_PHY_4002_TYPE TYPE_D0F0xE4 -// Field Data -#define D0F0xE4_PHY_4002_Reserved_2_0_OFFSET 0 -#define D0F0xE4_PHY_4002_Reserved_2_0_WIDTH 3 -#define D0F0xE4_PHY_4002_Reserved_2_0_MASK 0x7 -#define D0F0xE4_PHY_4002_SamClkPiOffsetSign_OFFSET 3 -#define D0F0xE4_PHY_4002_SamClkPiOffsetSign_WIDTH 1 -#define D0F0xE4_PHY_4002_SamClkPiOffsetSign_MASK 0x8 -#define D0F0xE4_PHY_4002_SamClkPiOffset_OFFSET 4 -#define D0F0xE4_PHY_4002_SamClkPiOffset_WIDTH 3 -#define D0F0xE4_PHY_4002_SamClkPiOffset_MASK 0x70 -#define D0F0xE4_PHY_4002_SamClkPiOffsetEn_OFFSET 7 -#define D0F0xE4_PHY_4002_SamClkPiOffsetEn_WIDTH 1 -#define D0F0xE4_PHY_4002_SamClkPiOffsetEn_MASK 0x80 -#define D0F0xE4_PHY_4002_Reserved_13_8_OFFSET 8 -#define D0F0xE4_PHY_4002_Reserved_13_8_WIDTH 6 -#define D0F0xE4_PHY_4002_Reserved_13_8_MASK 0x3f00 -#define D0F0xE4_PHY_4002_LfcMin_OFFSET 14 -#define D0F0xE4_PHY_4002_LfcMin_WIDTH 8 -#define D0F0xE4_PHY_4002_LfcMin_MASK 0x3fc000 -#define D0F0xE4_PHY_4002_LfcMax_OFFSET 22 -#define D0F0xE4_PHY_4002_LfcMax_WIDTH 8 -#define D0F0xE4_PHY_4002_LfcMax_MASK 0x3fc00000 -#define D0F0xE4_PHY_4002_Reserved_31_30_OFFSET 30 -#define D0F0xE4_PHY_4002_Reserved_31_30_WIDTH 2 -#define D0F0xE4_PHY_4002_Reserved_31_30_MASK 0xc0000000 - -/// D0F0xE4_PHY_4002 -typedef union { - struct { ///< - UINT32 Reserved_2_0:3 ; ///< - UINT32 SamClkPiOffsetSign:1 ; ///< - UINT32 SamClkPiOffset:3 ; ///< - UINT32 SamClkPiOffsetEn:1 ; ///< - UINT32 Reserved_13_8:6 ; ///< - UINT32 LfcMin:8 ; ///< - UINT32 LfcMax:8 ; ///< - UINT32 Reserved_31_30:2 ; ///< - } Field; ///< - UINT32 Value; ///< -} D0F0xE4_PHY_4002_STRUCT; - -// **** D0F0xE4_PHY_4005 Register Definition **** -// Address -#define D0F0xE4_PHY_4005_ADDRESS 0x4005 - -// Type -#define D0F0xE4_PHY_4005_TYPE TYPE_D0F0xE4 -// Field Data -#define D0F0xE4_PHY_4005_Reserved_8_0_OFFSET 0 -#define D0F0xE4_PHY_4005_Reserved_8_0_WIDTH 9 -#define D0F0xE4_PHY_4005_Reserved_8_0_MASK 0x1ff -#define D0F0xE4_PHY_4005_JitterInjHold_OFFSET 9 -#define D0F0xE4_PHY_4005_JitterInjHold_WIDTH 1 -#define D0F0xE4_PHY_4005_JitterInjHold_MASK 0x200 -#define D0F0xE4_PHY_4005_JitterInjOffCnt_OFFSET 10 -#define D0F0xE4_PHY_4005_JitterInjOffCnt_WIDTH 6 -#define D0F0xE4_PHY_4005_JitterInjOffCnt_MASK 0xfc00 -#define D0F0xE4_PHY_4005_Reserved_22_16_OFFSET 16 -#define D0F0xE4_PHY_4005_Reserved_22_16_WIDTH 7 -#define D0F0xE4_PHY_4005_Reserved_22_16_MASK 0x7f0000 -#define D0F0xE4_PHY_4005_JitterInjOnCnt_OFFSET 23 -#define D0F0xE4_PHY_4005_JitterInjOnCnt_WIDTH 6 -#define D0F0xE4_PHY_4005_JitterInjOnCnt_MASK 0x1f800000 -#define D0F0xE4_PHY_4005_JitterInjDir_OFFSET 29 -#define D0F0xE4_PHY_4005_JitterInjDir_WIDTH 1 -#define D0F0xE4_PHY_4005_JitterInjDir_MASK 0x20000000 -#define D0F0xE4_PHY_4005_JitterInjEn_OFFSET 30 -#define D0F0xE4_PHY_4005_JitterInjEn_WIDTH 1 -#define D0F0xE4_PHY_4005_JitterInjEn_MASK 0x40000000 -#define D0F0xE4_PHY_4005_Reserved_31_31_OFFSET 31 -#define D0F0xE4_PHY_4005_Reserved_31_31_WIDTH 1 -#define D0F0xE4_PHY_4005_Reserved_31_31_MASK 0x80000000 - -/// D0F0xE4_PHY_4005 -typedef union { - struct { ///< - UINT32 Reserved_8_0:9 ; ///< - UINT32 JitterInjHold:1 ; ///< - UINT32 JitterInjOffCnt:6 ; ///< - UINT32 Reserved_22_16:7 ; ///< - UINT32 JitterInjOnCnt:6 ; ///< - UINT32 JitterInjDir:1 ; ///< - UINT32 JitterInjEn:1 ; ///< - UINT32 Reserved_31_31:1 ; ///< - } Field; ///< - UINT32 Value; ///< -} D0F0xE4_PHY_4005_STRUCT; - -// **** D0F0xE4_PHY_4006 Register Definition **** -// Address -#define D0F0xE4_PHY_4006_ADDRESS 0x4006 - -// Type -#define D0F0xE4_PHY_4006_TYPE TYPE_D0F0xE4 -// Field Data -#define D0F0xE4_PHY_4006_Reserved_4_0_OFFSET 0 -#define D0F0xE4_PHY_4006_Reserved_4_0_WIDTH 5 -#define D0F0xE4_PHY_4006_Reserved_4_0_MASK 0x1f -#define D0F0xE4_PHY_4006_DfeVoltage_OFFSET 5 -#define D0F0xE4_PHY_4006_DfeVoltage_WIDTH 2 -#define D0F0xE4_PHY_4006_DfeVoltage_MASK 0x60 -#define D0F0xE4_PHY_4006_DfeEn_OFFSET 7 -#define D0F0xE4_PHY_4006_DfeEn_WIDTH 1 -#define D0F0xE4_PHY_4006_DfeEn_MASK 0x80 -#define D0F0xE4_PHY_4006_Reserved_31_8_OFFSET 8 -#define D0F0xE4_PHY_4006_Reserved_31_8_WIDTH 24 -#define D0F0xE4_PHY_4006_Reserved_31_8_MASK 0xffffff00 - -/// D0F0xE4_PHY_4006 -typedef union { - struct { ///< - UINT32 Reserved_4_0:5 ; ///< - UINT32 DfeVoltage:2 ; ///< - UINT32 DfeEn:1 ; ///< - UINT32 Reserved_31_8:24; ///< - } Field; ///< - UINT32 Value; ///< -} D0F0xE4_PHY_4006_STRUCT; - -// **** D0F0xE4_PHY_400A Register Definition **** -// Address -#define D0F0xE4_PHY_400A_ADDRESS 0x400a - -// Type -#define D0F0xE4_PHY_400A_TYPE TYPE_D0F0xE4 -// Field Data -#define D0F0xE4_PHY_400A_EnCoreLoopFirst_OFFSET 0 -#define D0F0xE4_PHY_400A_EnCoreLoopFirst_WIDTH 1 -#define D0F0xE4_PHY_400A_EnCoreLoopFirst_MASK 0x1 -#define D0F0xE4_PHY_400A_Reserved_3_1_OFFSET 1 -#define D0F0xE4_PHY_400A_Reserved_3_1_WIDTH 3 -#define D0F0xE4_PHY_400A_Reserved_3_1_MASK 0xe -#define D0F0xE4_PHY_400A_LockDetOnLs2Exit_OFFSET 4 -#define D0F0xE4_PHY_400A_LockDetOnLs2Exit_WIDTH 1 -#define D0F0xE4_PHY_400A_LockDetOnLs2Exit_MASK 0x10 -#define D0F0xE4_PHY_400A_Reserved_6_5_OFFSET 5 -#define D0F0xE4_PHY_400A_Reserved_6_5_WIDTH 2 -#define D0F0xE4_PHY_400A_Reserved_6_5_MASK 0x60 -#define D0F0xE4_PHY_400A_BiasDisInLs2_OFFSET 7 -#define D0F0xE4_PHY_400A_BiasDisInLs2_WIDTH 1 -#define D0F0xE4_PHY_400A_BiasDisInLs2_MASK 0x80 -#define D0F0xE4_PHY_400A_Reserved_12_8_OFFSET 8 -#define D0F0xE4_PHY_400A_Reserved_12_8_WIDTH 5 -#define D0F0xE4_PHY_400A_Reserved_12_8_MASK 0x1f00 -#define D0F0xE4_PHY_400A_AnalogWaitTime_OFFSET 13 -#define D0F0xE4_PHY_400A_AnalogWaitTime_WIDTH 2 -#define D0F0xE4_PHY_400A_AnalogWaitTime_MASK 0x6000 -#define D0F0xE4_PHY_400A_Reserved_16_15_OFFSET 15 -#define D0F0xE4_PHY_400A_Reserved_16_15_WIDTH 2 -#define D0F0xE4_PHY_400A_Reserved_16_15_MASK 0x18000 -#define D0F0xE4_PHY_400A_DllLockFastModeEn_OFFSET 17 -#define D0F0xE4_PHY_400A_DllLockFastModeEn_WIDTH 1 -#define D0F0xE4_PHY_400A_DllLockFastModeEn_MASK 0x20000 -#define D0F0xE4_PHY_400A_Reserved_28_18_OFFSET 18 -#define D0F0xE4_PHY_400A_Reserved_28_18_WIDTH 11 -#define D0F0xE4_PHY_400A_Reserved_28_18_MASK 0x1ffc0000 -#define D0F0xE4_PHY_400A_Ls2ExitTime_OFFSET 29 -#define D0F0xE4_PHY_400A_Ls2ExitTime_WIDTH 3 -#define D0F0xE4_PHY_400A_Ls2ExitTime_MASK 0xe0000000 - -/// D0F0xE4_PHY_400A -typedef union { - struct { ///< - UINT32 EnCoreLoopFirst:1 ; ///< - UINT32 Reserved_3_1:3 ; ///< - UINT32 LockDetOnLs2Exit:1 ; ///< - UINT32 Reserved_6_5:2 ; ///< - UINT32 BiasDisInLs2:1 ; ///< - UINT32 Reserved_12_8:5 ; ///< - UINT32 AnalogWaitTime:2 ; ///< - UINT32 Reserved_16_15:2 ; ///< - UINT32 DllLockFastModeEn:1 ; ///< - UINT32 Reserved_28_18:11; ///< - UINT32 Ls2ExitTime:3 ; ///< - } Field; ///< - UINT32 Value; ///< -} D0F0xE4_PHY_400A_STRUCT; - -// **** D0F0xE4_PHY_6005 Register Definition **** -// Address -#define D0F0xE4_PHY_6005_ADDRESS 0x6005 - -// Type -#define D0F0xE4_PHY_6005_TYPE TYPE_D0F0xE4 -// Field Data -#define D0F0xE4_PHY_6005_Reserved_28_0_OFFSET 0 -#define D0F0xE4_PHY_6005_Reserved_28_0_WIDTH 29 -#define D0F0xE4_PHY_6005_Reserved_28_0_MASK 0x1fffffff -#define D0F0xE4_PHY_6005_IsOwnMstr_OFFSET 29 -#define D0F0xE4_PHY_6005_IsOwnMstr_WIDTH 1 -#define D0F0xE4_PHY_6005_IsOwnMstr_MASK 0x20000000 -#define D0F0xE4_PHY_6005_Reserved_30_30_OFFSET 30 -#define D0F0xE4_PHY_6005_Reserved_30_30_WIDTH 1 -#define D0F0xE4_PHY_6005_Reserved_30_30_MASK 0x40000000 -#define D0F0xE4_PHY_6005_GangedModeEn_OFFSET 31 -#define D0F0xE4_PHY_6005_GangedModeEn_WIDTH 1 -#define D0F0xE4_PHY_6005_GangedModeEn_MASK 0x80000000 - -/// D0F0xE4_PHY_6005 -typedef union { - struct { ///< - UINT32 Reserved_28_0:29; ///< - UINT32 IsOwnMstr:1 ; ///< - UINT32 Reserved_30_30:1 ; ///< - UINT32 GangedModeEn:1 ; ///< - } Field; ///< - UINT32 Value; ///< -} D0F0xE4_PHY_6005_STRUCT; - -// **** D18F2x09C_x0000_0000 Register Definition **** -// Address -#define D18F2x09C_x0000_0000_ADDRESS 0x0 - -// Type -#define D18F2x09C_x0000_0000_TYPE TYPE_D18F2x09C -// Field Data -#define D18F2x09C_x0000_0000_CkeDrvStren_OFFSET 0 -#define D18F2x09C_x0000_0000_CkeDrvStren_WIDTH 3 -#define D18F2x09C_x0000_0000_CkeDrvStren_MASK 0x7 -#define D18F2x09C_x0000_0000_Reserved_3_3_OFFSET 3 -#define D18F2x09C_x0000_0000_Reserved_3_3_WIDTH 1 -#define D18F2x09C_x0000_0000_Reserved_3_3_MASK 0x8 -#define D18F2x09C_x0000_0000_CsOdtDrvStren_OFFSET 4 -#define D18F2x09C_x0000_0000_CsOdtDrvStren_WIDTH 3 -#define D18F2x09C_x0000_0000_CsOdtDrvStren_MASK 0x70 -#define D18F2x09C_x0000_0000_Reserved_7_7_OFFSET 7 -#define D18F2x09C_x0000_0000_Reserved_7_7_WIDTH 1 -#define D18F2x09C_x0000_0000_Reserved_7_7_MASK 0x80 -#define D18F2x09C_x0000_0000_AddrCmdDrvStren_OFFSET 8 -#define D18F2x09C_x0000_0000_AddrCmdDrvStren_WIDTH 3 -#define D18F2x09C_x0000_0000_AddrCmdDrvStren_MASK 0x700 -#define D18F2x09C_x0000_0000_Reserved_11_11_OFFSET 11 -#define D18F2x09C_x0000_0000_Reserved_11_11_WIDTH 1 -#define D18F2x09C_x0000_0000_Reserved_11_11_MASK 0x800 -#define D18F2x09C_x0000_0000_ClkDrvStren_OFFSET 12 -#define D18F2x09C_x0000_0000_ClkDrvStren_WIDTH 3 -#define D18F2x09C_x0000_0000_ClkDrvStren_MASK 0x7000 -#define D18F2x09C_x0000_0000_Reserved_15_15_OFFSET 15 -#define D18F2x09C_x0000_0000_Reserved_15_15_WIDTH 1 -#define D18F2x09C_x0000_0000_Reserved_15_15_MASK 0x8000 -#define D18F2x09C_x0000_0000_DataDrvStren_OFFSET 16 -#define D18F2x09C_x0000_0000_DataDrvStren_WIDTH 3 -#define D18F2x09C_x0000_0000_DataDrvStren_MASK 0x70000 -#define D18F2x09C_x0000_0000_Reserved_19_19_OFFSET 19 -#define D18F2x09C_x0000_0000_Reserved_19_19_WIDTH 1 -#define D18F2x09C_x0000_0000_Reserved_19_19_MASK 0x80000 -#define D18F2x09C_x0000_0000_DqsDrvStren_OFFSET 20 -#define D18F2x09C_x0000_0000_DqsDrvStren_WIDTH 3 -#define D18F2x09C_x0000_0000_DqsDrvStren_MASK 0x700000 -#define D18F2x09C_x0000_0000_Reserved_27_23_OFFSET 23 -#define D18F2x09C_x0000_0000_Reserved_27_23_WIDTH 5 -#define D18F2x09C_x0000_0000_Reserved_27_23_MASK 0xf800000 -#define D18F2x09C_x0000_0000_ProcOdt_OFFSET 28 -#define D18F2x09C_x0000_0000_ProcOdt_WIDTH 3 -#define D18F2x09C_x0000_0000_ProcOdt_MASK 0x70000000 -#define D18F2x09C_x0000_0000_Reserved_31_31_OFFSET 31 -#define D18F2x09C_x0000_0000_Reserved_31_31_WIDTH 1 -#define D18F2x09C_x0000_0000_Reserved_31_31_MASK 0x80000000 - -/// D18F2x09C_x0000_0000 -typedef union { - struct { ///< - UINT32 CkeDrvStren:3 ; ///< - UINT32 Reserved_3_3:1 ; ///< - UINT32 CsOdtDrvStren:3 ; ///< - UINT32 Reserved_7_7:1 ; ///< - UINT32 AddrCmdDrvStren:3 ; ///< - UINT32 Reserved_11_11:1 ; ///< - UINT32 ClkDrvStren:3 ; ///< - UINT32 Reserved_15_15:1 ; ///< - UINT32 DataDrvStren:3 ; ///< - UINT32 Reserved_19_19:1 ; ///< - UINT32 DqsDrvStren:3 ; ///< - UINT32 Reserved_27_23:5 ; ///< - UINT32 ProcOdt:3 ; ///< - UINT32 Reserved_31_31:1 ; ///< - } Field; ///< - UINT32 Value; ///< -} D18F2x09C_x0000_0000_STRUCT; - -// **** D18F2x09C_x0000_0001 Register Definition **** -// Address -#define D18F2x09C_x0000_0001_ADDRESS 0x1 - -// Type -#define D18F2x09C_x0000_0001_TYPE TYPE_D18F2x09C -// Field Data -#define D18F2x09C_x0000_0001_WrDatFineDly_Byte0_OFFSET 0 -#define D18F2x09C_x0000_0001_WrDatFineDly_Byte0_WIDTH 5 -#define D18F2x09C_x0000_0001_WrDatFineDly_Byte0_MASK 0x1f -#define D18F2x09C_x0000_0001_WrDatGrossDly_Byte0_OFFSET 5 -#define D18F2x09C_x0000_0001_WrDatGrossDly_Byte0_WIDTH 3 -#define D18F2x09C_x0000_0001_WrDatGrossDly_Byte0_MASK 0xe0 -#define D18F2x09C_x0000_0001_WrDatFineDly_Byte1_OFFSET 8 -#define D18F2x09C_x0000_0001_WrDatFineDly_Byte1_WIDTH 5 -#define D18F2x09C_x0000_0001_WrDatFineDly_Byte1_MASK 0x1f00 -#define D18F2x09C_x0000_0001_WrDatGrossDly_Byte1_OFFSET 13 -#define D18F2x09C_x0000_0001_WrDatGrossDly_Byte1_WIDTH 3 -#define D18F2x09C_x0000_0001_WrDatGrossDly_Byte1_MASK 0xe000 -#define D18F2x09C_x0000_0001_WrDatFineDly_Byte2_OFFSET 16 -#define D18F2x09C_x0000_0001_WrDatFineDly_Byte2_WIDTH 5 -#define D18F2x09C_x0000_0001_WrDatFineDly_Byte2_MASK 0x1f0000 -#define D18F2x09C_x0000_0001_WrDatGrossDly_Byte2_OFFSET 21 -#define D18F2x09C_x0000_0001_WrDatGrossDly_Byte2_WIDTH 3 -#define D18F2x09C_x0000_0001_WrDatGrossDly_Byte2_MASK 0xe00000 -#define D18F2x09C_x0000_0001_WrDatFineDly_Byte3_OFFSET 24 -#define D18F2x09C_x0000_0001_WrDatFineDly_Byte3_WIDTH 5 -#define D18F2x09C_x0000_0001_WrDatFineDly_Byte3_MASK 0x1f000000 -#define D18F2x09C_x0000_0001_WrDatGrossDly_Byte3_OFFSET 29 -#define D18F2x09C_x0000_0001_WrDatGrossDly_Byte3_WIDTH 3 -#define D18F2x09C_x0000_0001_WrDatGrossDly_Byte3_MASK 0xe0000000 - -/// D18F2x09C_x0000_0001 -typedef union { - struct { ///< - UINT32 WrDatFineDly_Byte0:5 ; ///< - UINT32 WrDatGrossDly_Byte0:3 ; ///< - UINT32 WrDatFineDly_Byte1:5 ; ///< - UINT32 WrDatGrossDly_Byte1:3 ; ///< - UINT32 WrDatFineDly_Byte2:5 ; ///< - UINT32 WrDatGrossDly_Byte2:3 ; ///< - UINT32 WrDatFineDly_Byte3:5 ; ///< - UINT32 WrDatGrossDly_Byte3:3 ; ///< - } Field; ///< - UINT32 Value; ///< -} D18F2x09C_x0000_0001_STRUCT; - -// **** D18F2x09C_x0000_0002 Register Definition **** -// Address -#define D18F2x09C_x0000_0002_ADDRESS 0x2 - -// Type -#define D18F2x09C_x0000_0002_TYPE TYPE_D18F2x09C -// Field Data -#define D18F2x09C_x0000_0002_WrDatFineDly_Byte4_OFFSET 0 -#define D18F2x09C_x0000_0002_WrDatFineDly_Byte4_WIDTH 5 -#define D18F2x09C_x0000_0002_WrDatFineDly_Byte4_MASK 0x1f -#define D18F2x09C_x0000_0002_WrDatGrossDly_Byte4_OFFSET 5 -#define D18F2x09C_x0000_0002_WrDatGrossDly_Byte4_WIDTH 3 -#define D18F2x09C_x0000_0002_WrDatGrossDly_Byte4_MASK 0xe0 -#define D18F2x09C_x0000_0002_WrDatFineDly_Byte5_OFFSET 8 -#define D18F2x09C_x0000_0002_WrDatFineDly_Byte5_WIDTH 5 -#define D18F2x09C_x0000_0002_WrDatFineDly_Byte5_MASK 0x1f00 -#define D18F2x09C_x0000_0002_WrDatGrossDly_Byte5_OFFSET 13 -#define D18F2x09C_x0000_0002_WrDatGrossDly_Byte5_WIDTH 3 -#define D18F2x09C_x0000_0002_WrDatGrossDly_Byte5_MASK 0xe000 -#define D18F2x09C_x0000_0002_WrDatFineDly_Byte6_OFFSET 16 -#define D18F2x09C_x0000_0002_WrDatFineDly_Byte6_WIDTH 5 -#define D18F2x09C_x0000_0002_WrDatFineDly_Byte6_MASK 0x1f0000 -#define D18F2x09C_x0000_0002_WrDatGrossDly_Byte6_OFFSET 21 -#define D18F2x09C_x0000_0002_WrDatGrossDly_Byte6_WIDTH 3 -#define D18F2x09C_x0000_0002_WrDatGrossDly_Byte6_MASK 0xe00000 -#define D18F2x09C_x0000_0002_WrDatFineDly_Byte7_OFFSET 24 -#define D18F2x09C_x0000_0002_WrDatFineDly_Byte7_WIDTH 5 -#define D18F2x09C_x0000_0002_WrDatFineDly_Byte7_MASK 0x1f000000 -#define D18F2x09C_x0000_0002_WrDatGrossDly_Byte7_OFFSET 29 -#define D18F2x09C_x0000_0002_WrDatGrossDly_Byte7_WIDTH 3 -#define D18F2x09C_x0000_0002_WrDatGrossDly_Byte7_MASK 0xe0000000 - -/// D18F2x09C_x0000_0002 -typedef union { - struct { ///< - UINT32 WrDatFineDly_Byte4:5 ; ///< - UINT32 WrDatGrossDly_Byte4:3 ; ///< - UINT32 WrDatFineDly_Byte5:5 ; ///< - UINT32 WrDatGrossDly_Byte5:3 ; ///< - UINT32 WrDatFineDly_Byte6:5 ; ///< - UINT32 WrDatGrossDly_Byte6:3 ; ///< - UINT32 WrDatFineDly_Byte7:5 ; ///< - UINT32 WrDatGrossDly_Byte7:3 ; ///< - } Field; ///< - UINT32 Value; ///< -} D18F2x09C_x0000_0002_STRUCT; - -// **** D18F2x09C_x0000_0004 Register Definition **** -// Address -#define D18F2x09C_x0000_0004_ADDRESS 0x4 - -// Type -#define D18F2x09C_x0000_0004_TYPE TYPE_D18F2x09C -// Field Data -#define D18F2x09C_x0000_0004_CkeFineDelay_OFFSET 0 -#define D18F2x09C_x0000_0004_CkeFineDelay_WIDTH 5 -#define D18F2x09C_x0000_0004_CkeFineDelay_MASK 0x1f -#define D18F2x09C_x0000_0004_CkeSetup_OFFSET 5 -#define D18F2x09C_x0000_0004_CkeSetup_WIDTH 1 -#define D18F2x09C_x0000_0004_CkeSetup_MASK 0x20 -#define D18F2x09C_x0000_0004_Reserved_7_6_OFFSET 6 -#define D18F2x09C_x0000_0004_Reserved_7_6_WIDTH 2 -#define D18F2x09C_x0000_0004_Reserved_7_6_MASK 0xc0 -#define D18F2x09C_x0000_0004_CsOdtFineDelay_OFFSET 8 -#define D18F2x09C_x0000_0004_CsOdtFineDelay_WIDTH 5 -#define D18F2x09C_x0000_0004_CsOdtFineDelay_MASK 0x1f00 -#define D18F2x09C_x0000_0004_CsOdtSetup_OFFSET 13 -#define D18F2x09C_x0000_0004_CsOdtSetup_WIDTH 1 -#define D18F2x09C_x0000_0004_CsOdtSetup_MASK 0x2000 -#define D18F2x09C_x0000_0004_Reserved_15_14_OFFSET 14 -#define D18F2x09C_x0000_0004_Reserved_15_14_WIDTH 2 -#define D18F2x09C_x0000_0004_Reserved_15_14_MASK 0xc000 -#define D18F2x09C_x0000_0004_AddrCmdFineDelay_OFFSET 16 -#define D18F2x09C_x0000_0004_AddrCmdFineDelay_WIDTH 5 -#define D18F2x09C_x0000_0004_AddrCmdFineDelay_MASK 0x1f0000 -#define D18F2x09C_x0000_0004_AddrCmdSetup_OFFSET 21 -#define D18F2x09C_x0000_0004_AddrCmdSetup_WIDTH 1 -#define D18F2x09C_x0000_0004_AddrCmdSetup_MASK 0x200000 -#define D18F2x09C_x0000_0004_Reserved_31_22_OFFSET 22 -#define D18F2x09C_x0000_0004_Reserved_31_22_WIDTH 10 -#define D18F2x09C_x0000_0004_Reserved_31_22_MASK 0xffc00000 - -/// D18F2x09C_x0000_0004 -typedef union { - struct { ///< - UINT32 CkeFineDelay:5 ; ///< - UINT32 CkeSetup:1 ; ///< - UINT32 Reserved_7_6:2 ; ///< - UINT32 CsOdtFineDelay:5 ; ///< - UINT32 CsOdtSetup:1 ; ///< - UINT32 Reserved_15_14:2 ; ///< - UINT32 AddrCmdFineDelay:5 ; ///< - UINT32 AddrCmdSetup:1 ; ///< - UINT32 Reserved_31_22:10; ///< - } Field; ///< - UINT32 Value; ///< -} D18F2x09C_x0000_0004_STRUCT; - -// **** D18F2x09C_x0000_0005 Register Definition **** -// Address -#define D18F2x09C_x0000_0005_ADDRESS 0x5 - -// Type -#define D18F2x09C_x0000_0005_TYPE TYPE_D18F2x09C -// Field Data -#define D18F2x09C_x0000_0005_Reserved_0_0_OFFSET 0 -#define D18F2x09C_x0000_0005_Reserved_0_0_WIDTH 1 -#define D18F2x09C_x0000_0005_Reserved_0_0_MASK 0x1 -#define D18F2x09C_x0000_0005_RdDqsTime_Byte0_OFFSET 1 -#define D18F2x09C_x0000_0005_RdDqsTime_Byte0_WIDTH 5 -#define D18F2x09C_x0000_0005_RdDqsTime_Byte0_MASK 0x3e -#define D18F2x09C_x0000_0005_Reserved_8_6_OFFSET 6 -#define D18F2x09C_x0000_0005_Reserved_8_6_WIDTH 3 -#define D18F2x09C_x0000_0005_Reserved_8_6_MASK 0x1c0 -#define D18F2x09C_x0000_0005_RdDqsTime_Byte1_OFFSET 9 -#define D18F2x09C_x0000_0005_RdDqsTime_Byte1_WIDTH 5 -#define D18F2x09C_x0000_0005_RdDqsTime_Byte1_MASK 0x3e00 -#define D18F2x09C_x0000_0005_Reserved_16_14_OFFSET 14 -#define D18F2x09C_x0000_0005_Reserved_16_14_WIDTH 3 -#define D18F2x09C_x0000_0005_Reserved_16_14_MASK 0x1c000 -#define D18F2x09C_x0000_0005_RdDqsTime_Byte2_OFFSET 17 -#define D18F2x09C_x0000_0005_RdDqsTime_Byte2_WIDTH 5 -#define D18F2x09C_x0000_0005_RdDqsTime_Byte2_MASK 0x3e0000 -#define D18F2x09C_x0000_0005_Reserved_24_22_OFFSET 22 -#define D18F2x09C_x0000_0005_Reserved_24_22_WIDTH 3 -#define D18F2x09C_x0000_0005_Reserved_24_22_MASK 0x1c00000 -#define D18F2x09C_x0000_0005_RdDqsTime_Byte3_OFFSET 25 -#define D18F2x09C_x0000_0005_RdDqsTime_Byte3_WIDTH 5 -#define D18F2x09C_x0000_0005_RdDqsTime_Byte3_MASK 0x3e000000 -#define D18F2x09C_x0000_0005_Reserved_31_30_OFFSET 30 -#define D18F2x09C_x0000_0005_Reserved_31_30_WIDTH 2 -#define D18F2x09C_x0000_0005_Reserved_31_30_MASK 0xc0000000 - -/// D18F2x09C_x0000_0005 -typedef union { - struct { ///< - UINT32 Reserved_0_0:1 ; ///< - UINT32 RdDqsTime_Byte0:5 ; ///< - UINT32 Reserved_8_6:3 ; ///< - UINT32 RdDqsTime_Byte1:5 ; ///< - UINT32 Reserved_16_14:3 ; ///< - UINT32 RdDqsTime_Byte2:5 ; ///< - UINT32 Reserved_24_22:3 ; ///< - UINT32 RdDqsTime_Byte3:5 ; ///< - UINT32 Reserved_31_30:2 ; ///< - } Field; ///< - UINT32 Value; ///< -} D18F2x09C_x0000_0005_STRUCT; - -// **** D18F2x09C_x0000_0006 Register Definition **** -// Address -#define D18F2x09C_x0000_0006_ADDRESS 0x6 - -// Type -#define D18F2x09C_x0000_0006_TYPE TYPE_D18F2x09C -// Field Data -#define D18F2x09C_x0000_0006_Reserved_0_0_OFFSET 0 -#define D18F2x09C_x0000_0006_Reserved_0_0_WIDTH 1 -#define D18F2x09C_x0000_0006_Reserved_0_0_MASK 0x1 -#define D18F2x09C_x0000_0006_RdDqsTime_Byte4_OFFSET 1 -#define D18F2x09C_x0000_0006_RdDqsTime_Byte4_WIDTH 5 -#define D18F2x09C_x0000_0006_RdDqsTime_Byte4_MASK 0x3e -#define D18F2x09C_x0000_0006_Reserved_8_6_OFFSET 6 -#define D18F2x09C_x0000_0006_Reserved_8_6_WIDTH 3 -#define D18F2x09C_x0000_0006_Reserved_8_6_MASK 0x1c0 -#define D18F2x09C_x0000_0006_RdDqsTime_Byte5_OFFSET 9 -#define D18F2x09C_x0000_0006_RdDqsTime_Byte5_WIDTH 5 -#define D18F2x09C_x0000_0006_RdDqsTime_Byte5_MASK 0x3e00 -#define D18F2x09C_x0000_0006_Reserved_16_14_OFFSET 14 -#define D18F2x09C_x0000_0006_Reserved_16_14_WIDTH 3 -#define D18F2x09C_x0000_0006_Reserved_16_14_MASK 0x1c000 -#define D18F2x09C_x0000_0006_RdDqsTime_Byte6_OFFSET 17 -#define D18F2x09C_x0000_0006_RdDqsTime_Byte6_WIDTH 5 -#define D18F2x09C_x0000_0006_RdDqsTime_Byte6_MASK 0x3e0000 -#define D18F2x09C_x0000_0006_Reserved_24_22_OFFSET 22 -#define D18F2x09C_x0000_0006_Reserved_24_22_WIDTH 3 -#define D18F2x09C_x0000_0006_Reserved_24_22_MASK 0x1c00000 -#define D18F2x09C_x0000_0006_RdDqsTime_Byte7_OFFSET 25 -#define D18F2x09C_x0000_0006_RdDqsTime_Byte7_WIDTH 5 -#define D18F2x09C_x0000_0006_RdDqsTime_Byte7_MASK 0x3e000000 -#define D18F2x09C_x0000_0006_Reserved_31_30_OFFSET 30 -#define D18F2x09C_x0000_0006_Reserved_31_30_WIDTH 2 -#define D18F2x09C_x0000_0006_Reserved_31_30_MASK 0xc0000000 - -/// D18F2x09C_x0000_0006 -typedef union { - struct { ///< - UINT32 Reserved_0_0:1 ; ///< - UINT32 RdDqsTime_Byte4:5 ; ///< - UINT32 Reserved_8_6:3 ; ///< - UINT32 RdDqsTime_Byte5:5 ; ///< - UINT32 Reserved_16_14:3 ; ///< - UINT32 RdDqsTime_Byte6:5 ; ///< - UINT32 Reserved_24_22:3 ; ///< - UINT32 RdDqsTime_Byte7:5 ; ///< - UINT32 Reserved_31_30:2 ; ///< - } Field; ///< - UINT32 Value; ///< -} D18F2x09C_x0000_0006_STRUCT; - -// **** D18F2x09C_x0000_0008 Register Definition **** -// Address -#define D18F2x09C_x0000_0008_ADDRESS 0x8 - -// Type -#define D18F2x09C_x0000_0008_TYPE TYPE_D18F2x09C -// Field Data -#define D18F2x09C_x0000_0008_WrtLvTrEn_OFFSET 0 -#define D18F2x09C_x0000_0008_WrtLvTrEn_WIDTH 1 -#define D18F2x09C_x0000_0008_WrtLvTrEn_MASK 0x1 -#define D18F2x09C_x0000_0008_Reserved_1_1_OFFSET 1 -#define D18F2x09C_x0000_0008_Reserved_1_1_WIDTH 1 -#define D18F2x09C_x0000_0008_Reserved_1_1_MASK 0x2 -#define D18F2x09C_x0000_0008_Reserved_2_2_OFFSET 2 -#define D18F2x09C_x0000_0008_Reserved_2_2_WIDTH 1 -#define D18F2x09C_x0000_0008_Reserved_2_2_MASK 0x4 -#define D18F2x09C_x0000_0008_PhyFenceTrEn_OFFSET 3 -#define D18F2x09C_x0000_0008_PhyFenceTrEn_WIDTH 1 -#define D18F2x09C_x0000_0008_PhyFenceTrEn_MASK 0x8 -#define D18F2x09C_x0000_0008_TrDimmSel_OFFSET 4 -#define D18F2x09C_x0000_0008_TrDimmSel_WIDTH 1 -#define D18F2x09C_x0000_0008_TrDimmSel_MASK 0x10 -#define D18F2x09C_x0000_0008_Reserved_5_5_OFFSET 5 -#define D18F2x09C_x0000_0008_Reserved_5_5_WIDTH 1 -#define D18F2x09C_x0000_0008_Reserved_5_5_MASK 0x20 -#define D18F2x09C_x0000_0008_FenceTrSel_OFFSET 6 -#define D18F2x09C_x0000_0008_FenceTrSel_WIDTH 2 -#define D18F2x09C_x0000_0008_FenceTrSel_MASK 0xc0 -#define D18F2x09C_x0000_0008_WrLvOdt_OFFSET 8 -#define D18F2x09C_x0000_0008_WrLvOdt_WIDTH 4 -#define D18F2x09C_x0000_0008_WrLvOdt_MASK 0xf00 -#define D18F2x09C_x0000_0008_WrLvOdtEn_OFFSET 12 -#define D18F2x09C_x0000_0008_WrLvOdtEn_WIDTH 1 -#define D18F2x09C_x0000_0008_WrLvOdtEn_MASK 0x1000 -#define D18F2x09C_x0000_0008_DqsRcvTrEn_OFFSET 13 -#define D18F2x09C_x0000_0008_DqsRcvTrEn_WIDTH 1 -#define D18F2x09C_x0000_0008_DqsRcvTrEn_MASK 0x2000 -#define D18F2x09C_x0000_0008_Reserved_14_14_OFFSET 14 -#define D18F2x09C_x0000_0008_Reserved_14_14_WIDTH 1 -#define D18F2x09C_x0000_0008_Reserved_14_14_MASK 0x4000 -#define D18F2x09C_x0000_0008_PllMult_OFFSET 15 -#define D18F2x09C_x0000_0008_PllMult_WIDTH 7 -#define D18F2x09C_x0000_0008_PllMult_MASK 0x3f8000 -#define D18F2x09C_x0000_0008_Reserved_23_22_OFFSET 22 -#define D18F2x09C_x0000_0008_Reserved_23_22_WIDTH 2 -#define D18F2x09C_x0000_0008_Reserved_23_22_MASK 0xc00000 -#define D18F2x09C_x0000_0008_PllDiv_OFFSET 24 -#define D18F2x09C_x0000_0008_PllDiv_WIDTH 4 -#define D18F2x09C_x0000_0008_PllDiv_MASK 0xf000000 -#define D18F2x09C_x0000_0008_Reserved_31_28_OFFSET 28 -#define D18F2x09C_x0000_0008_Reserved_31_28_WIDTH 4 -#define D18F2x09C_x0000_0008_Reserved_31_28_MASK 0xf0000000 - -/// D18F2x09C_x0000_0008 -typedef union { - struct { ///< - UINT32 WrtLvTrEn:1 ; ///< - UINT32 Reserved_1_1:1 ; ///< - UINT32 Reserved_2_2:1 ; ///< - UINT32 PhyFenceTrEn:1 ; ///< - UINT32 TrDimmSel:1 ; ///< - UINT32 Reserved_5_5:1 ; ///< - UINT32 FenceTrSel:2 ; ///< - UINT32 WrLvOdt:4 ; ///< - UINT32 WrLvOdtEn:1 ; ///< - UINT32 DqsRcvTrEn:1 ; ///< - UINT32 Reserved_14_14:1 ; ///< - UINT32 PllMult:7 ; ///< - UINT32 Reserved_23_22:2 ; ///< - UINT32 PllDiv:4 ; ///< - UINT32 Reserved_31_28:4 ; ///< - } Field; ///< - UINT32 Value; ///< -} D18F2x09C_x0000_0008_STRUCT; - -// **** D18F2x09C_x0000_000B Register Definition **** -// Address -#define D18F2x09C_x0000_000B_ADDRESS 0xb - -// Type -#define D18F2x09C_x0000_000B_TYPE TYPE_D18F2x09C -// Field Data -#define D18F2x09C_x0000_000B_Reserved_22_0_OFFSET 0 -#define D18F2x09C_x0000_000B_Reserved_22_0_WIDTH 23 -#define D18F2x09C_x0000_000B_Reserved_22_0_MASK 0x7fffff -#define D18F2x09C_x0000_000B_PhySelfRefreshMode_OFFSET 23 -#define D18F2x09C_x0000_000B_PhySelfRefreshMode_WIDTH 1 -#define D18F2x09C_x0000_000B_PhySelfRefreshMode_MASK 0x800000 -#define D18F2x09C_x0000_000B_Reserved_30_24_OFFSET 24 -#define D18F2x09C_x0000_000B_Reserved_30_24_WIDTH 7 -#define D18F2x09C_x0000_000B_Reserved_30_24_MASK 0x7f000000 -#define D18F2x09C_x0000_000B_DynModeChange_OFFSET 31 -#define D18F2x09C_x0000_000B_DynModeChange_WIDTH 1 -#define D18F2x09C_x0000_000B_DynModeChange_MASK 0x80000000 - -/// D18F2x09C_x0000_000B -typedef union { - struct { ///< - UINT32 Reserved_22_0:23; ///< - UINT32 PhySelfRefreshMode:1 ; ///< - UINT32 Reserved_30_24:7 ; ///< - UINT32 DynModeChange:1 ; ///< - } Field; ///< - UINT32 Value; ///< -} D18F2x09C_x0000_000B_STRUCT; - -// **** D18F2x09C_x0000_000C Register Definition **** -// Address -#define D18F2x09C_x0000_000C_ADDRESS 0xc - -// Type -#define D18F2x09C_x0000_000C_TYPE TYPE_D18F2x09C -// Field Data -#define D18F2x09C_x0000_000C_ChipSelTri_OFFSET 0 -#define D18F2x09C_x0000_000C_ChipSelTri_WIDTH 8 -#define D18F2x09C_x0000_000C_ChipSelTri_MASK 0xff -#define D18F2x09C_x0000_000C_ODTTri_OFFSET 8 -#define D18F2x09C_x0000_000C_ODTTri_WIDTH 4 -#define D18F2x09C_x0000_000C_ODTTri_MASK 0xf00 -#define D18F2x09C_x0000_000C_CKETri_OFFSET 12 -#define D18F2x09C_x0000_000C_CKETri_WIDTH 2 -#define D18F2x09C_x0000_000C_CKETri_MASK 0x3000 -#define D18F2x09C_x0000_000C_Reserved_15_14_OFFSET 14 -#define D18F2x09C_x0000_000C_Reserved_15_14_WIDTH 2 -#define D18F2x09C_x0000_000C_Reserved_15_14_MASK 0xc000 -#define D18F2x09C_x0000_000C_FenceThresholdTxPad_OFFSET 16 -#define D18F2x09C_x0000_000C_FenceThresholdTxPad_WIDTH 5 -#define D18F2x09C_x0000_000C_FenceThresholdTxPad_MASK 0x1f0000 -#define D18F2x09C_x0000_000C_FenceThresholdRxDll_OFFSET 21 -#define D18F2x09C_x0000_000C_FenceThresholdRxDll_WIDTH 5 -#define D18F2x09C_x0000_000C_FenceThresholdRxDll_MASK 0x3e00000 -#define D18F2x09C_x0000_000C_FenceThresholdTxDll_OFFSET 26 -#define D18F2x09C_x0000_000C_FenceThresholdTxDll_WIDTH 5 -#define D18F2x09C_x0000_000C_FenceThresholdTxDll_MASK 0x7c000000 -#define D18F2x09C_x0000_000C_Reserved_31_31_OFFSET 31 -#define D18F2x09C_x0000_000C_Reserved_31_31_WIDTH 1 -#define D18F2x09C_x0000_000C_Reserved_31_31_MASK 0x80000000 - -/// D18F2x09C_x0000_000C -typedef union { - struct { ///< - UINT32 ChipSelTri:8 ; ///< - UINT32 ODTTri:4 ; ///< - UINT32 CKETri:2 ; ///< - UINT32 Reserved_15_14:2 ; ///< - UINT32 FenceThresholdTxPad:5 ; ///< - UINT32 FenceThresholdRxDll:5 ; ///< - UINT32 FenceThresholdTxDll:5 ; ///< - UINT32 Reserved_31_31:1 ; ///< - } Field; ///< - UINT32 Value; ///< -} D18F2x09C_x0000_000C_STRUCT; - -// **** D18F2x09C_x0000_000D Register Definition **** -// Address -#define D18F2x09C_x0000_000D_ADDRESS 0xd - -// Type -#define D18F2x09C_x0000_000D_TYPE TYPE_D18F2x09C -// Field Data -#define D18F2x09C_x0000_000D_TxMaxDurDllNoLock_OFFSET 0 -#define D18F2x09C_x0000_000D_TxMaxDurDllNoLock_WIDTH 4 -#define D18F2x09C_x0000_000D_TxMaxDurDllNoLock_MASK 0xf -#define D18F2x09C_x0000_000D_TxCPUpdPeriod_OFFSET 4 -#define D18F2x09C_x0000_000D_TxCPUpdPeriod_WIDTH 3 -#define D18F2x09C_x0000_000D_TxCPUpdPeriod_MASK 0x70 -#define D18F2x09C_x0000_000D_Reserved_7_7_OFFSET 7 -#define D18F2x09C_x0000_000D_Reserved_7_7_WIDTH 1 -#define D18F2x09C_x0000_000D_Reserved_7_7_MASK 0x80 -#define D18F2x09C_x0000_000D_TxDLLWakeupTime_OFFSET 8 -#define D18F2x09C_x0000_000D_TxDLLWakeupTime_WIDTH 2 -#define D18F2x09C_x0000_000D_TxDLLWakeupTime_MASK 0x300 -#define D18F2x09C_x0000_000D_Reserved_15_10_OFFSET 10 -#define D18F2x09C_x0000_000D_Reserved_15_10_WIDTH 6 -#define D18F2x09C_x0000_000D_Reserved_15_10_MASK 0xfc00 -#define D18F2x09C_x0000_000D_RxMaxDurDllNoLock_OFFSET 16 -#define D18F2x09C_x0000_000D_RxMaxDurDllNoLock_WIDTH 4 -#define D18F2x09C_x0000_000D_RxMaxDurDllNoLock_MASK 0xf0000 -#define D18F2x09C_x0000_000D_RxCPUpdPeriod_OFFSET 20 -#define D18F2x09C_x0000_000D_RxCPUpdPeriod_WIDTH 3 -#define D18F2x09C_x0000_000D_RxCPUpdPeriod_MASK 0x700000 -#define D18F2x09C_x0000_000D_Reserved_23_23_OFFSET 23 -#define D18F2x09C_x0000_000D_Reserved_23_23_WIDTH 1 -#define D18F2x09C_x0000_000D_Reserved_23_23_MASK 0x800000 -#define D18F2x09C_x0000_000D_RxDLLWakeupTime_OFFSET 24 -#define D18F2x09C_x0000_000D_RxDLLWakeupTime_WIDTH 2 -#define D18F2x09C_x0000_000D_RxDLLWakeupTime_MASK 0x3000000 -#define D18F2x09C_x0000_000D_Reserved_31_26_OFFSET 26 -#define D18F2x09C_x0000_000D_Reserved_31_26_WIDTH 6 -#define D18F2x09C_x0000_000D_Reserved_31_26_MASK 0xfc000000 - -/// D18F2x09C_x0000_000D -typedef union { - struct { ///< - UINT32 TxMaxDurDllNoLock:4 ; ///< - UINT32 TxCPUpdPeriod:3 ; ///< - UINT32 Reserved_7_7:1 ; ///< - UINT32 TxDLLWakeupTime:2 ; ///< - UINT32 Reserved_15_10:6 ; ///< - UINT32 RxMaxDurDllNoLock:4 ; ///< - UINT32 RxCPUpdPeriod:3 ; ///< - UINT32 Reserved_23_23:1 ; ///< - UINT32 RxDLLWakeupTime:2 ; ///< - UINT32 Reserved_31_26:6 ; ///< - } Field; ///< - UINT32 Value; ///< -} D18F2x09C_x0000_000D_STRUCT; - -// **** D18F2x09C_x0000_0010 Register Definition **** -// Address -#define D18F2x09C_x0000_0010_ADDRESS 0x10 - -// Type -#define D18F2x09C_x0000_0010_TYPE TYPE_D18F2x09C -// Field Data -#define D18F2x09C_x0000_0010_DqsRcvEnFineDelay_Byte0_OFFSET 0 -#define D18F2x09C_x0000_0010_DqsRcvEnFineDelay_Byte0_WIDTH 5 -#define D18F2x09C_x0000_0010_DqsRcvEnFineDelay_Byte0_MASK 0x1f -#define D18F2x09C_x0000_0010_DqsRcvEnGrossDelay_Byte0_OFFSET 5 -#define D18F2x09C_x0000_0010_DqsRcvEnGrossDelay_Byte0_WIDTH 4 -#define D18F2x09C_x0000_0010_DqsRcvEnGrossDelay_Byte0_MASK 0x1e0 -#define D18F2x09C_x0000_0010_Reserved_15_9_OFFSET 9 -#define D18F2x09C_x0000_0010_Reserved_15_9_WIDTH 7 -#define D18F2x09C_x0000_0010_Reserved_15_9_MASK 0xfe00 -#define D18F2x09C_x0000_0010_DqsRcvEnFineDelay_Byte1_OFFSET 16 -#define D18F2x09C_x0000_0010_DqsRcvEnFineDelay_Byte1_WIDTH 5 -#define D18F2x09C_x0000_0010_DqsRcvEnFineDelay_Byte1_MASK 0x1f0000 -#define D18F2x09C_x0000_0010_DqsRcvEnGrossDelay_Byte1_OFFSET 21 -#define D18F2x09C_x0000_0010_DqsRcvEnGrossDelay_Byte1_WIDTH 4 -#define D18F2x09C_x0000_0010_DqsRcvEnGrossDelay_Byte1_MASK 0x1e00000 -#define D18F2x09C_x0000_0010_Reserved_31_25_OFFSET 25 -#define D18F2x09C_x0000_0010_Reserved_31_25_WIDTH 7 -#define D18F2x09C_x0000_0010_Reserved_31_25_MASK 0xfe000000 - -/// D18F2x09C_x0000_0010 -typedef union { - struct { ///< - UINT32 DqsRcvEnFineDelay_Byte0:5 ; ///< - UINT32 DqsRcvEnGrossDelay_Byte0:4 ; ///< - UINT32 Reserved_15_9:7 ; ///< - UINT32 DqsRcvEnFineDelay_Byte1:5 ; ///< - UINT32 DqsRcvEnGrossDelay_Byte1:4 ; ///< - UINT32 Reserved_31_25:7 ; ///< - } Field; ///< - UINT32 Value; ///< -} D18F2x09C_x0000_0010_STRUCT; - -// **** D18F2x09C_x0000_0011 Register Definition **** -// Address -#define D18F2x09C_x0000_0011_ADDRESS 0x11 - -// Type -#define D18F2x09C_x0000_0011_TYPE TYPE_D18F2x09C -// Field Data -#define D18F2x09C_x0000_0011_DqsRcvEnFineDelay_Byte2_OFFSET 0 -#define D18F2x09C_x0000_0011_DqsRcvEnFineDelay_Byte2_WIDTH 5 -#define D18F2x09C_x0000_0011_DqsRcvEnFineDelay_Byte2_MASK 0x1f -#define D18F2x09C_x0000_0011_DqsRcvEnGrossDelay_Byte2_OFFSET 5 -#define D18F2x09C_x0000_0011_DqsRcvEnGrossDelay_Byte2_WIDTH 4 -#define D18F2x09C_x0000_0011_DqsRcvEnGrossDelay_Byte2_MASK 0x1e0 -#define D18F2x09C_x0000_0011_Reserved_15_9_OFFSET 9 -#define D18F2x09C_x0000_0011_Reserved_15_9_WIDTH 7 -#define D18F2x09C_x0000_0011_Reserved_15_9_MASK 0xfe00 -#define D18F2x09C_x0000_0011_DqsRcvEnFineDelay_Byte3_OFFSET 16 -#define D18F2x09C_x0000_0011_DqsRcvEnFineDelay_Byte3_WIDTH 5 -#define D18F2x09C_x0000_0011_DqsRcvEnFineDelay_Byte3_MASK 0x1f0000 -#define D18F2x09C_x0000_0011_DqsRcvEnGrossDelay_Byte3_OFFSET 21 -#define D18F2x09C_x0000_0011_DqsRcvEnGrossDelay_Byte3_WIDTH 4 -#define D18F2x09C_x0000_0011_DqsRcvEnGrossDelay_Byte3_MASK 0x1e00000 -#define D18F2x09C_x0000_0011_Reserved_31_25_OFFSET 25 -#define D18F2x09C_x0000_0011_Reserved_31_25_WIDTH 7 -#define D18F2x09C_x0000_0011_Reserved_31_25_MASK 0xfe000000 - -/// D18F2x09C_x0000_0011 -typedef union { - struct { ///< - UINT32 DqsRcvEnFineDelay_Byte2:5 ; ///< - UINT32 DqsRcvEnGrossDelay_Byte2:4 ; ///< - UINT32 Reserved_15_9:7 ; ///< - UINT32 DqsRcvEnFineDelay_Byte3:5 ; ///< - UINT32 DqsRcvEnGrossDelay_Byte3:4 ; ///< - UINT32 Reserved_31_25:7 ; ///< - } Field; ///< - UINT32 Value; ///< -} D18F2x09C_x0000_0011_STRUCT; - -// **** D18F2x09C_x0000_0013 Register Definition **** -// Address -#define D18F2x09C_x0000_0013_ADDRESS 0x13 - -// Type -#define D18F2x09C_x0000_0013_TYPE TYPE_D18F2x09C -// Field Data -#define D18F2x09C_x0000_0013_DqsRcvEnFineDelay_Byte0_OFFSET 0 -#define D18F2x09C_x0000_0013_DqsRcvEnFineDelay_Byte0_WIDTH 5 -#define D18F2x09C_x0000_0013_DqsRcvEnFineDelay_Byte0_MASK 0x1f -#define D18F2x09C_x0000_0013_DqsRcvEnGrossDelay_Byte0_OFFSET 5 -#define D18F2x09C_x0000_0013_DqsRcvEnGrossDelay_Byte0_WIDTH 4 -#define D18F2x09C_x0000_0013_DqsRcvEnGrossDelay_Byte0_MASK 0x1e0 -#define D18F2x09C_x0000_0013_Reserved_15_9_OFFSET 9 -#define D18F2x09C_x0000_0013_Reserved_15_9_WIDTH 7 -#define D18F2x09C_x0000_0013_Reserved_15_9_MASK 0xfe00 -#define D18F2x09C_x0000_0013_DqsRcvEnFineDelay_Byte1_OFFSET 16 -#define D18F2x09C_x0000_0013_DqsRcvEnFineDelay_Byte1_WIDTH 5 -#define D18F2x09C_x0000_0013_DqsRcvEnFineDelay_Byte1_MASK 0x1f0000 -#define D18F2x09C_x0000_0013_DqsRcvEnGrossDelay_Byte1_OFFSET 21 -#define D18F2x09C_x0000_0013_DqsRcvEnGrossDelay_Byte1_WIDTH 4 -#define D18F2x09C_x0000_0013_DqsRcvEnGrossDelay_Byte1_MASK 0x1e00000 -#define D18F2x09C_x0000_0013_Reserved_31_25_OFFSET 25 -#define D18F2x09C_x0000_0013_Reserved_31_25_WIDTH 7 -#define D18F2x09C_x0000_0013_Reserved_31_25_MASK 0xfe000000 - -/// D18F2x09C_x0000_0013 -typedef union { - struct { ///< - UINT32 DqsRcvEnFineDelay_Byte0:5 ; ///< - UINT32 DqsRcvEnGrossDelay_Byte0:4 ; ///< - UINT32 Reserved_15_9:7 ; ///< - UINT32 DqsRcvEnFineDelay_Byte1:5 ; ///< - UINT32 DqsRcvEnGrossDelay_Byte1:4 ; ///< - UINT32 Reserved_31_25:7 ; ///< - } Field; ///< - UINT32 Value; ///< -} D18F2x09C_x0000_0013_STRUCT; - -// **** D18F2x09C_x0000_0014 Register Definition **** -// Address -#define D18F2x09C_x0000_0014_ADDRESS 0x14 - -// Type -#define D18F2x09C_x0000_0014_TYPE TYPE_D18F2x09C -// Field Data -#define D18F2x09C_x0000_0014_DqsRcvEnFineDelay_Byte2_OFFSET 0 -#define D18F2x09C_x0000_0014_DqsRcvEnFineDelay_Byte2_WIDTH 5 -#define D18F2x09C_x0000_0014_DqsRcvEnFineDelay_Byte2_MASK 0x1f -#define D18F2x09C_x0000_0014_DqsRcvEnGrossDelay_Byte2_OFFSET 5 -#define D18F2x09C_x0000_0014_DqsRcvEnGrossDelay_Byte2_WIDTH 4 -#define D18F2x09C_x0000_0014_DqsRcvEnGrossDelay_Byte2_MASK 0x1e0 -#define D18F2x09C_x0000_0014_Reserved_15_9_OFFSET 9 -#define D18F2x09C_x0000_0014_Reserved_15_9_WIDTH 7 -#define D18F2x09C_x0000_0014_Reserved_15_9_MASK 0xfe00 -#define D18F2x09C_x0000_0014_DqsRcvEnFineDelay_Byte3_OFFSET 16 -#define D18F2x09C_x0000_0014_DqsRcvEnFineDelay_Byte3_WIDTH 5 -#define D18F2x09C_x0000_0014_DqsRcvEnFineDelay_Byte3_MASK 0x1f0000 -#define D18F2x09C_x0000_0014_DqsRcvEnGrossDelay_Byte3_OFFSET 21 -#define D18F2x09C_x0000_0014_DqsRcvEnGrossDelay_Byte3_WIDTH 4 -#define D18F2x09C_x0000_0014_DqsRcvEnGrossDelay_Byte3_MASK 0x1e00000 -#define D18F2x09C_x0000_0014_Reserved_31_25_OFFSET 25 -#define D18F2x09C_x0000_0014_Reserved_31_25_WIDTH 7 -#define D18F2x09C_x0000_0014_Reserved_31_25_MASK 0xfe000000 - -/// D18F2x09C_x0000_0014 -typedef union { - struct { ///< - UINT32 DqsRcvEnFineDelay_Byte2:5 ; ///< - UINT32 DqsRcvEnGrossDelay_Byte2:4 ; ///< - UINT32 Reserved_15_9:7 ; ///< - UINT32 DqsRcvEnFineDelay_Byte3:5 ; ///< - UINT32 DqsRcvEnGrossDelay_Byte3:4 ; ///< - UINT32 Reserved_31_25:7 ; ///< - } Field; ///< - UINT32 Value; ///< -} D18F2x09C_x0000_0014_STRUCT; - -// **** D18F2x09C_x0000_0020 Register Definition **** -// Address -#define D18F2x09C_x0000_0020_ADDRESS 0x20 - -// Type -#define D18F2x09C_x0000_0020_TYPE TYPE_D18F2x09C -// Field Data -#define D18F2x09C_x0000_0020_DqsRcvEnFineDelay_Byte4_OFFSET 0 -#define D18F2x09C_x0000_0020_DqsRcvEnFineDelay_Byte4_WIDTH 5 -#define D18F2x09C_x0000_0020_DqsRcvEnFineDelay_Byte4_MASK 0x1f -#define D18F2x09C_x0000_0020_DqsRcvEnGrossDelay_Byte4_OFFSET 5 -#define D18F2x09C_x0000_0020_DqsRcvEnGrossDelay_Byte4_WIDTH 4 -#define D18F2x09C_x0000_0020_DqsRcvEnGrossDelay_Byte4_MASK 0x1e0 -#define D18F2x09C_x0000_0020_Reserved_15_9_OFFSET 9 -#define D18F2x09C_x0000_0020_Reserved_15_9_WIDTH 7 -#define D18F2x09C_x0000_0020_Reserved_15_9_MASK 0xfe00 -#define D18F2x09C_x0000_0020_DqsRcvEnFineDelay_Byte5_OFFSET 16 -#define D18F2x09C_x0000_0020_DqsRcvEnFineDelay_Byte5_WIDTH 5 -#define D18F2x09C_x0000_0020_DqsRcvEnFineDelay_Byte5_MASK 0x1f0000 -#define D18F2x09C_x0000_0020_DqsRcvEnGrossDelay_Byte5_OFFSET 21 -#define D18F2x09C_x0000_0020_DqsRcvEnGrossDelay_Byte5_WIDTH 4 -#define D18F2x09C_x0000_0020_DqsRcvEnGrossDelay_Byte5_MASK 0x1e00000 -#define D18F2x09C_x0000_0020_Reserved_31_25_OFFSET 25 -#define D18F2x09C_x0000_0020_Reserved_31_25_WIDTH 7 -#define D18F2x09C_x0000_0020_Reserved_31_25_MASK 0xfe000000 - -/// D18F2x09C_x0000_0020 -typedef union { - struct { ///< - UINT32 DqsRcvEnFineDelay_Byte4:5 ; ///< - UINT32 DqsRcvEnGrossDelay_Byte4:4 ; ///< - UINT32 Reserved_15_9:7 ; ///< - UINT32 DqsRcvEnFineDelay_Byte5:5 ; ///< - UINT32 DqsRcvEnGrossDelay_Byte5:4 ; ///< - UINT32 Reserved_31_25:7 ; ///< - } Field; ///< - UINT32 Value; ///< -} D18F2x09C_x0000_0020_STRUCT; - -// **** D18F2x09C_x0000_0021 Register Definition **** -// Address -#define D18F2x09C_x0000_0021_ADDRESS 0x21 - -// Type -#define D18F2x09C_x0000_0021_TYPE TYPE_D18F2x09C -// Field Data -#define D18F2x09C_x0000_0021_DqsRcvEnFineDelay_Byte6_OFFSET 0 -#define D18F2x09C_x0000_0021_DqsRcvEnFineDelay_Byte6_WIDTH 5 -#define D18F2x09C_x0000_0021_DqsRcvEnFineDelay_Byte6_MASK 0x1f -#define D18F2x09C_x0000_0021_DqsRcvEnGrossDelay_Byte6_OFFSET 5 -#define D18F2x09C_x0000_0021_DqsRcvEnGrossDelay_Byte6_WIDTH 4 -#define D18F2x09C_x0000_0021_DqsRcvEnGrossDelay_Byte6_MASK 0x1e0 -#define D18F2x09C_x0000_0021_Reserved_15_9_OFFSET 9 -#define D18F2x09C_x0000_0021_Reserved_15_9_WIDTH 7 -#define D18F2x09C_x0000_0021_Reserved_15_9_MASK 0xfe00 -#define D18F2x09C_x0000_0021_DqsRcvEnFineDelay_Byte7_OFFSET 16 -#define D18F2x09C_x0000_0021_DqsRcvEnFineDelay_Byte7_WIDTH 5 -#define D18F2x09C_x0000_0021_DqsRcvEnFineDelay_Byte7_MASK 0x1f0000 -#define D18F2x09C_x0000_0021_DqsRcvEnGrossDelay_Byte7_OFFSET 21 -#define D18F2x09C_x0000_0021_DqsRcvEnGrossDelay_Byte7_WIDTH 4 -#define D18F2x09C_x0000_0021_DqsRcvEnGrossDelay_Byte7_MASK 0x1e00000 -#define D18F2x09C_x0000_0021_Reserved_31_25_OFFSET 25 -#define D18F2x09C_x0000_0021_Reserved_31_25_WIDTH 7 -#define D18F2x09C_x0000_0021_Reserved_31_25_MASK 0xfe000000 - -/// D18F2x09C_x0000_0021 -typedef union { - struct { ///< - UINT32 DqsRcvEnFineDelay_Byte6:5 ; ///< - UINT32 DqsRcvEnGrossDelay_Byte6:4 ; ///< - UINT32 Reserved_15_9:7 ; ///< - UINT32 DqsRcvEnFineDelay_Byte7:5 ; ///< - UINT32 DqsRcvEnGrossDelay_Byte7:4 ; ///< - UINT32 Reserved_31_25:7 ; ///< - } Field; ///< - UINT32 Value; ///< -} D18F2x09C_x0000_0021_STRUCT; - -// **** D18F2x09C_x0000_0023 Register Definition **** -// Address -#define D18F2x09C_x0000_0023_ADDRESS 0x23 - -// Type -#define D18F2x09C_x0000_0023_TYPE TYPE_D18F2x09C -// Field Data -#define D18F2x09C_x0000_0023_DqsRcvEnFineDelay_Byte4_OFFSET 0 -#define D18F2x09C_x0000_0023_DqsRcvEnFineDelay_Byte4_WIDTH 5 -#define D18F2x09C_x0000_0023_DqsRcvEnFineDelay_Byte4_MASK 0x1f -#define D18F2x09C_x0000_0023_DqsRcvEnGrossDelay_Byte4_OFFSET 5 -#define D18F2x09C_x0000_0023_DqsRcvEnGrossDelay_Byte4_WIDTH 4 -#define D18F2x09C_x0000_0023_DqsRcvEnGrossDelay_Byte4_MASK 0x1e0 -#define D18F2x09C_x0000_0023_Reserved_15_9_OFFSET 9 -#define D18F2x09C_x0000_0023_Reserved_15_9_WIDTH 7 -#define D18F2x09C_x0000_0023_Reserved_15_9_MASK 0xfe00 -#define D18F2x09C_x0000_0023_DqsRcvEnFineDelay_Byte5_OFFSET 16 -#define D18F2x09C_x0000_0023_DqsRcvEnFineDelay_Byte5_WIDTH 5 -#define D18F2x09C_x0000_0023_DqsRcvEnFineDelay_Byte5_MASK 0x1f0000 -#define D18F2x09C_x0000_0023_DqsRcvEnGrossDelay_Byte5_OFFSET 21 -#define D18F2x09C_x0000_0023_DqsRcvEnGrossDelay_Byte5_WIDTH 4 -#define D18F2x09C_x0000_0023_DqsRcvEnGrossDelay_Byte5_MASK 0x1e00000 -#define D18F2x09C_x0000_0023_Reserved_31_25_OFFSET 25 -#define D18F2x09C_x0000_0023_Reserved_31_25_WIDTH 7 -#define D18F2x09C_x0000_0023_Reserved_31_25_MASK 0xfe000000 - -/// D18F2x09C_x0000_0023 -typedef union { - struct { ///< - UINT32 DqsRcvEnFineDelay_Byte4:5 ; ///< - UINT32 DqsRcvEnGrossDelay_Byte4:4 ; ///< - UINT32 Reserved_15_9:7 ; ///< - UINT32 DqsRcvEnFineDelay_Byte5:5 ; ///< - UINT32 DqsRcvEnGrossDelay_Byte5:4 ; ///< - UINT32 Reserved_31_25:7 ; ///< - } Field; ///< - UINT32 Value; ///< -} D18F2x09C_x0000_0023_STRUCT; - -// **** D18F2x09C_x0000_0024 Register Definition **** -// Address -#define D18F2x09C_x0000_0024_ADDRESS 0x24 - -// Type -#define D18F2x09C_x0000_0024_TYPE TYPE_D18F2x09C -// Field Data -#define D18F2x09C_x0000_0024_DqsRcvEnFineDelay_Byte6_OFFSET 0 -#define D18F2x09C_x0000_0024_DqsRcvEnFineDelay_Byte6_WIDTH 5 -#define D18F2x09C_x0000_0024_DqsRcvEnFineDelay_Byte6_MASK 0x1f -#define D18F2x09C_x0000_0024_DqsRcvEnGrossDelay_Byte6_OFFSET 5 -#define D18F2x09C_x0000_0024_DqsRcvEnGrossDelay_Byte6_WIDTH 4 -#define D18F2x09C_x0000_0024_DqsRcvEnGrossDelay_Byte6_MASK 0x1e0 -#define D18F2x09C_x0000_0024_Reserved_15_9_OFFSET 9 -#define D18F2x09C_x0000_0024_Reserved_15_9_WIDTH 7 -#define D18F2x09C_x0000_0024_Reserved_15_9_MASK 0xfe00 -#define D18F2x09C_x0000_0024_DqsRcvEnFineDelay_Byte7_OFFSET 16 -#define D18F2x09C_x0000_0024_DqsRcvEnFineDelay_Byte7_WIDTH 5 -#define D18F2x09C_x0000_0024_DqsRcvEnFineDelay_Byte7_MASK 0x1f0000 -#define D18F2x09C_x0000_0024_DqsRcvEnGrossDelay_Byte7_OFFSET 21 -#define D18F2x09C_x0000_0024_DqsRcvEnGrossDelay_Byte7_WIDTH 4 -#define D18F2x09C_x0000_0024_DqsRcvEnGrossDelay_Byte7_MASK 0x1e00000 -#define D18F2x09C_x0000_0024_Reserved_31_25_OFFSET 25 -#define D18F2x09C_x0000_0024_Reserved_31_25_WIDTH 7 -#define D18F2x09C_x0000_0024_Reserved_31_25_MASK 0xfe000000 - -/// D18F2x09C_x0000_0024 -typedef union { - struct { ///< - UINT32 DqsRcvEnFineDelay_Byte6:5 ; ///< - UINT32 DqsRcvEnGrossDelay_Byte6:4 ; ///< - UINT32 Reserved_15_9:7 ; ///< - UINT32 DqsRcvEnFineDelay_Byte7:5 ; ///< - UINT32 DqsRcvEnGrossDelay_Byte7:4 ; ///< - UINT32 Reserved_31_25:7 ; ///< - } Field; ///< - UINT32 Value; ///< -} D18F2x09C_x0000_0024_STRUCT; - -// **** D18F2x09C_x0000_0030 Register Definition **** -// Address -#define D18F2x09C_x0000_0030_ADDRESS 0x30 - -// Type -#define D18F2x09C_x0000_0030_TYPE TYPE_D18F2x09C -// Field Data -#define D18F2x09C_x0000_0030_WrDqsFineDly_Byte0_OFFSET 0 -#define D18F2x09C_x0000_0030_WrDqsFineDly_Byte0_WIDTH 5 -#define D18F2x09C_x0000_0030_WrDqsFineDly_Byte0_MASK 0x1f -#define D18F2x09C_x0000_0030_WrDqsGrossDly_Byte0_OFFSET 5 -#define D18F2x09C_x0000_0030_WrDqsGrossDly_Byte0_WIDTH 3 -#define D18F2x09C_x0000_0030_WrDqsGrossDly_Byte0_MASK 0xe0 -#define D18F2x09C_x0000_0030_Reserved_15_8_OFFSET 8 -#define D18F2x09C_x0000_0030_Reserved_15_8_WIDTH 8 -#define D18F2x09C_x0000_0030_Reserved_15_8_MASK 0xff00 -#define D18F2x09C_x0000_0030_WrDqsFineDly_Byte1_OFFSET 16 -#define D18F2x09C_x0000_0030_WrDqsFineDly_Byte1_WIDTH 5 -#define D18F2x09C_x0000_0030_WrDqsFineDly_Byte1_MASK 0x1f0000 -#define D18F2x09C_x0000_0030_WrDqsGrossDly_Byte1_OFFSET 21 -#define D18F2x09C_x0000_0030_WrDqsGrossDly_Byte1_WIDTH 3 -#define D18F2x09C_x0000_0030_WrDqsGrossDly_Byte1_MASK 0xe00000 -#define D18F2x09C_x0000_0030_Reserved_31_24_OFFSET 24 -#define D18F2x09C_x0000_0030_Reserved_31_24_WIDTH 8 -#define D18F2x09C_x0000_0030_Reserved_31_24_MASK 0xff000000 - -/// D18F2x09C_x0000_0030 -typedef union { - struct { ///< - UINT32 WrDqsFineDly_Byte0:5 ; ///< - UINT32 WrDqsGrossDly_Byte0:3 ; ///< - UINT32 Reserved_15_8:8 ; ///< - UINT32 WrDqsFineDly_Byte1:5 ; ///< - UINT32 WrDqsGrossDly_Byte1:3 ; ///< - UINT32 Reserved_31_24:8 ; ///< - } Field; ///< - UINT32 Value; ///< -} D18F2x09C_x0000_0030_STRUCT; - -// **** D18F2x09C_x0000_0031 Register Definition **** -// Address -#define D18F2x09C_x0000_0031_ADDRESS 0x31 - -// Type -#define D18F2x09C_x0000_0031_TYPE TYPE_D18F2x09C -// Field Data -#define D18F2x09C_x0000_0031_WrDqsFineDly_Byte2_OFFSET 0 -#define D18F2x09C_x0000_0031_WrDqsFineDly_Byte2_WIDTH 5 -#define D18F2x09C_x0000_0031_WrDqsFineDly_Byte2_MASK 0x1f -#define D18F2x09C_x0000_0031_WrDqsGrossDly_Byte2_OFFSET 5 -#define D18F2x09C_x0000_0031_WrDqsGrossDly_Byte2_WIDTH 3 -#define D18F2x09C_x0000_0031_WrDqsGrossDly_Byte2_MASK 0xe0 -#define D18F2x09C_x0000_0031_Reserved_15_8_OFFSET 8 -#define D18F2x09C_x0000_0031_Reserved_15_8_WIDTH 8 -#define D18F2x09C_x0000_0031_Reserved_15_8_MASK 0xff00 -#define D18F2x09C_x0000_0031_WrDqsFineDly_Byte3_OFFSET 16 -#define D18F2x09C_x0000_0031_WrDqsFineDly_Byte3_WIDTH 5 -#define D18F2x09C_x0000_0031_WrDqsFineDly_Byte3_MASK 0x1f0000 -#define D18F2x09C_x0000_0031_WrDqsGrossDly_Byte3_OFFSET 21 -#define D18F2x09C_x0000_0031_WrDqsGrossDly_Byte3_WIDTH 3 -#define D18F2x09C_x0000_0031_WrDqsGrossDly_Byte3_MASK 0xe00000 -#define D18F2x09C_x0000_0031_Reserved_31_24_OFFSET 24 -#define D18F2x09C_x0000_0031_Reserved_31_24_WIDTH 8 -#define D18F2x09C_x0000_0031_Reserved_31_24_MASK 0xff000000 - -/// D18F2x09C_x0000_0031 -typedef union { - struct { ///< - UINT32 WrDqsFineDly_Byte2:5 ; ///< - UINT32 WrDqsGrossDly_Byte2:3 ; ///< - UINT32 Reserved_15_8:8 ; ///< - UINT32 WrDqsFineDly_Byte3:5 ; ///< - UINT32 WrDqsGrossDly_Byte3:3 ; ///< - UINT32 Reserved_31_24:8 ; ///< - } Field; ///< - UINT32 Value; ///< -} D18F2x09C_x0000_0031_STRUCT; - -// **** D18F2x09C_x0000_0033 Register Definition **** -// Address -#define D18F2x09C_x0000_0033_ADDRESS 0x33 - -// Type -#define D18F2x09C_x0000_0033_TYPE TYPE_D18F2x09C -// Field Data -#define D18F2x09C_x0000_0033_WrDqsFineDly_Byte0_OFFSET 0 -#define D18F2x09C_x0000_0033_WrDqsFineDly_Byte0_WIDTH 5 -#define D18F2x09C_x0000_0033_WrDqsFineDly_Byte0_MASK 0x1f -#define D18F2x09C_x0000_0033_WrDqsGrossDly_Byte0_OFFSET 5 -#define D18F2x09C_x0000_0033_WrDqsGrossDly_Byte0_WIDTH 3 -#define D18F2x09C_x0000_0033_WrDqsGrossDly_Byte0_MASK 0xe0 -#define D18F2x09C_x0000_0033_Reserved_15_8_OFFSET 8 -#define D18F2x09C_x0000_0033_Reserved_15_8_WIDTH 8 -#define D18F2x09C_x0000_0033_Reserved_15_8_MASK 0xff00 -#define D18F2x09C_x0000_0033_WrDqsFineDly_Byte1_OFFSET 16 -#define D18F2x09C_x0000_0033_WrDqsFineDly_Byte1_WIDTH 5 -#define D18F2x09C_x0000_0033_WrDqsFineDly_Byte1_MASK 0x1f0000 -#define D18F2x09C_x0000_0033_WrDqsGrossDly_Byte1_OFFSET 21 -#define D18F2x09C_x0000_0033_WrDqsGrossDly_Byte1_WIDTH 3 -#define D18F2x09C_x0000_0033_WrDqsGrossDly_Byte1_MASK 0xe00000 -#define D18F2x09C_x0000_0033_Reserved_31_24_OFFSET 24 -#define D18F2x09C_x0000_0033_Reserved_31_24_WIDTH 8 -#define D18F2x09C_x0000_0033_Reserved_31_24_MASK 0xff000000 - -/// D18F2x09C_x0000_0033 -typedef union { - struct { ///< - UINT32 WrDqsFineDly_Byte0:5 ; ///< - UINT32 WrDqsGrossDly_Byte0:3 ; ///< - UINT32 Reserved_15_8:8 ; ///< - UINT32 WrDqsFineDly_Byte1:5 ; ///< - UINT32 WrDqsGrossDly_Byte1:3 ; ///< - UINT32 Reserved_31_24:8 ; ///< - } Field; ///< - UINT32 Value; ///< -} D18F2x09C_x0000_0033_STRUCT; - -// **** D18F2x09C_x0000_0034 Register Definition **** -// Address -#define D18F2x09C_x0000_0034_ADDRESS 0x34 - -// Type -#define D18F2x09C_x0000_0034_TYPE TYPE_D18F2x09C -// Field Data -#define D18F2x09C_x0000_0034_WrDqsFineDly_Byte2_OFFSET 0 -#define D18F2x09C_x0000_0034_WrDqsFineDly_Byte2_WIDTH 5 -#define D18F2x09C_x0000_0034_WrDqsFineDly_Byte2_MASK 0x1f -#define D18F2x09C_x0000_0034_WrDqsGrossDly_Byte2_OFFSET 5 -#define D18F2x09C_x0000_0034_WrDqsGrossDly_Byte2_WIDTH 3 -#define D18F2x09C_x0000_0034_WrDqsGrossDly_Byte2_MASK 0xe0 -#define D18F2x09C_x0000_0034_Reserved_15_8_OFFSET 8 -#define D18F2x09C_x0000_0034_Reserved_15_8_WIDTH 8 -#define D18F2x09C_x0000_0034_Reserved_15_8_MASK 0xff00 -#define D18F2x09C_x0000_0034_WrDqsFineDly_Byte3_OFFSET 16 -#define D18F2x09C_x0000_0034_WrDqsFineDly_Byte3_WIDTH 5 -#define D18F2x09C_x0000_0034_WrDqsFineDly_Byte3_MASK 0x1f0000 -#define D18F2x09C_x0000_0034_WrDqsGrossDly_Byte3_OFFSET 21 -#define D18F2x09C_x0000_0034_WrDqsGrossDly_Byte3_WIDTH 3 -#define D18F2x09C_x0000_0034_WrDqsGrossDly_Byte3_MASK 0xe00000 -#define D18F2x09C_x0000_0034_Reserved_31_24_OFFSET 24 -#define D18F2x09C_x0000_0034_Reserved_31_24_WIDTH 8 -#define D18F2x09C_x0000_0034_Reserved_31_24_MASK 0xff000000 - -/// D18F2x09C_x0000_0034 -typedef union { - struct { ///< - UINT32 WrDqsFineDly_Byte2:5 ; ///< - UINT32 WrDqsGrossDly_Byte2:3 ; ///< - UINT32 Reserved_15_8:8 ; ///< - UINT32 WrDqsFineDly_Byte3:5 ; ///< - UINT32 WrDqsGrossDly_Byte3:3 ; ///< - UINT32 Reserved_31_24:8 ; ///< - } Field; ///< - UINT32 Value; ///< -} D18F2x09C_x0000_0034_STRUCT; - -// **** D18F2x09C_x0000_0040 Register Definition **** -// Address -#define D18F2x09C_x0000_0040_ADDRESS 0x40 - -// Type -#define D18F2x09C_x0000_0040_TYPE TYPE_D18F2x09C -// Field Data -#define D18F2x09C_x0000_0040_WrDqsFineDly_Byte4_OFFSET 0 -#define D18F2x09C_x0000_0040_WrDqsFineDly_Byte4_WIDTH 5 -#define D18F2x09C_x0000_0040_WrDqsFineDly_Byte4_MASK 0x1f -#define D18F2x09C_x0000_0040_WrDqsGrossDly_Byte4_OFFSET 5 -#define D18F2x09C_x0000_0040_WrDqsGrossDly_Byte4_WIDTH 3 -#define D18F2x09C_x0000_0040_WrDqsGrossDly_Byte4_MASK 0xe0 -#define D18F2x09C_x0000_0040_Reserved_15_8_OFFSET 8 -#define D18F2x09C_x0000_0040_Reserved_15_8_WIDTH 8 -#define D18F2x09C_x0000_0040_Reserved_15_8_MASK 0xff00 -#define D18F2x09C_x0000_0040_WrDqsFineDly_Byte5_OFFSET 16 -#define D18F2x09C_x0000_0040_WrDqsFineDly_Byte5_WIDTH 5 -#define D18F2x09C_x0000_0040_WrDqsFineDly_Byte5_MASK 0x1f0000 -#define D18F2x09C_x0000_0040_WrDqsGrossDly_Byte5_OFFSET 21 -#define D18F2x09C_x0000_0040_WrDqsGrossDly_Byte5_WIDTH 3 -#define D18F2x09C_x0000_0040_WrDqsGrossDly_Byte5_MASK 0xe00000 -#define D18F2x09C_x0000_0040_Reserved_31_24_OFFSET 24 -#define D18F2x09C_x0000_0040_Reserved_31_24_WIDTH 8 -#define D18F2x09C_x0000_0040_Reserved_31_24_MASK 0xff000000 - -/// D18F2x09C_x0000_0040 -typedef union { - struct { ///< - UINT32 WrDqsFineDly_Byte4:5 ; ///< - UINT32 WrDqsGrossDly_Byte4:3 ; ///< - UINT32 Reserved_15_8:8 ; ///< - UINT32 WrDqsFineDly_Byte5:5 ; ///< - UINT32 WrDqsGrossDly_Byte5:3 ; ///< - UINT32 Reserved_31_24:8 ; ///< - } Field; ///< - UINT32 Value; ///< -} D18F2x09C_x0000_0040_STRUCT; - -// **** D18F2x09C_x0000_0041 Register Definition **** -// Address -#define D18F2x09C_x0000_0041_ADDRESS 0x41 - -// Type -#define D18F2x09C_x0000_0041_TYPE TYPE_D18F2x09C -// Field Data -#define D18F2x09C_x0000_0041_WrDqsFineDly_Byte6_OFFSET 0 -#define D18F2x09C_x0000_0041_WrDqsFineDly_Byte6_WIDTH 5 -#define D18F2x09C_x0000_0041_WrDqsFineDly_Byte6_MASK 0x1f -#define D18F2x09C_x0000_0041_WrDqsGrossDly_Byte6_OFFSET 5 -#define D18F2x09C_x0000_0041_WrDqsGrossDly_Byte6_WIDTH 3 -#define D18F2x09C_x0000_0041_WrDqsGrossDly_Byte6_MASK 0xe0 -#define D18F2x09C_x0000_0041_Reserved_15_8_OFFSET 8 -#define D18F2x09C_x0000_0041_Reserved_15_8_WIDTH 8 -#define D18F2x09C_x0000_0041_Reserved_15_8_MASK 0xff00 -#define D18F2x09C_x0000_0041_WrDqsFineDly_Byte7_OFFSET 16 -#define D18F2x09C_x0000_0041_WrDqsFineDly_Byte7_WIDTH 5 -#define D18F2x09C_x0000_0041_WrDqsFineDly_Byte7_MASK 0x1f0000 -#define D18F2x09C_x0000_0041_WrDqsGrossDly_Byte7_OFFSET 21 -#define D18F2x09C_x0000_0041_WrDqsGrossDly_Byte7_WIDTH 3 -#define D18F2x09C_x0000_0041_WrDqsGrossDly_Byte7_MASK 0xe00000 -#define D18F2x09C_x0000_0041_Reserved_31_24_OFFSET 24 -#define D18F2x09C_x0000_0041_Reserved_31_24_WIDTH 8 -#define D18F2x09C_x0000_0041_Reserved_31_24_MASK 0xff000000 - -/// D18F2x09C_x0000_0041 -typedef union { - struct { ///< - UINT32 WrDqsFineDly_Byte6:5 ; ///< - UINT32 WrDqsGrossDly_Byte6:3 ; ///< - UINT32 Reserved_15_8:8 ; ///< - UINT32 WrDqsFineDly_Byte7:5 ; ///< - UINT32 WrDqsGrossDly_Byte7:3 ; ///< - UINT32 Reserved_31_24:8 ; ///< - } Field; ///< - UINT32 Value; ///< -} D18F2x09C_x0000_0041_STRUCT; - -// **** D18F2x09C_x0000_0043 Register Definition **** -// Address -#define D18F2x09C_x0000_0043_ADDRESS 0x43 - -// Type -#define D18F2x09C_x0000_0043_TYPE TYPE_D18F2x09C -// Field Data -#define D18F2x09C_x0000_0043_WrDqsFineDly_Byte4_OFFSET 0 -#define D18F2x09C_x0000_0043_WrDqsFineDly_Byte4_WIDTH 5 -#define D18F2x09C_x0000_0043_WrDqsFineDly_Byte4_MASK 0x1f -#define D18F2x09C_x0000_0043_WrDqsGrossDly_Byte4_OFFSET 5 -#define D18F2x09C_x0000_0043_WrDqsGrossDly_Byte4_WIDTH 3 -#define D18F2x09C_x0000_0043_WrDqsGrossDly_Byte4_MASK 0xe0 -#define D18F2x09C_x0000_0043_Reserved_15_8_OFFSET 8 -#define D18F2x09C_x0000_0043_Reserved_15_8_WIDTH 8 -#define D18F2x09C_x0000_0043_Reserved_15_8_MASK 0xff00 -#define D18F2x09C_x0000_0043_WrDqsFineDly_Byte5_OFFSET 16 -#define D18F2x09C_x0000_0043_WrDqsFineDly_Byte5_WIDTH 5 -#define D18F2x09C_x0000_0043_WrDqsFineDly_Byte5_MASK 0x1f0000 -#define D18F2x09C_x0000_0043_WrDqsGrossDly_Byte5_OFFSET 21 -#define D18F2x09C_x0000_0043_WrDqsGrossDly_Byte5_WIDTH 3 -#define D18F2x09C_x0000_0043_WrDqsGrossDly_Byte5_MASK 0xe00000 -#define D18F2x09C_x0000_0043_Reserved_31_24_OFFSET 24 -#define D18F2x09C_x0000_0043_Reserved_31_24_WIDTH 8 -#define D18F2x09C_x0000_0043_Reserved_31_24_MASK 0xff000000 - -/// D18F2x09C_x0000_0043 -typedef union { - struct { ///< - UINT32 WrDqsFineDly_Byte4:5 ; ///< - UINT32 WrDqsGrossDly_Byte4:3 ; ///< - UINT32 Reserved_15_8:8 ; ///< - UINT32 WrDqsFineDly_Byte5:5 ; ///< - UINT32 WrDqsGrossDly_Byte5:3 ; ///< - UINT32 Reserved_31_24:8 ; ///< - } Field; ///< - UINT32 Value; ///< -} D18F2x09C_x0000_0043_STRUCT; - -// **** D18F2x09C_x0000_0044 Register Definition **** -// Address -#define D18F2x09C_x0000_0044_ADDRESS 0x44 - -// Type -#define D18F2x09C_x0000_0044_TYPE TYPE_D18F2x09C -// Field Data -#define D18F2x09C_x0000_0044_WrDqsFineDly_Byte6_OFFSET 0 -#define D18F2x09C_x0000_0044_WrDqsFineDly_Byte6_WIDTH 5 -#define D18F2x09C_x0000_0044_WrDqsFineDly_Byte6_MASK 0x1f -#define D18F2x09C_x0000_0044_WrDqsGrossDly_Byte6_OFFSET 5 -#define D18F2x09C_x0000_0044_WrDqsGrossDly_Byte6_WIDTH 3 -#define D18F2x09C_x0000_0044_WrDqsGrossDly_Byte6_MASK 0xe0 -#define D18F2x09C_x0000_0044_Reserved_15_8_OFFSET 8 -#define D18F2x09C_x0000_0044_Reserved_15_8_WIDTH 8 -#define D18F2x09C_x0000_0044_Reserved_15_8_MASK 0xff00 -#define D18F2x09C_x0000_0044_WrDqsFineDly_Byte7_OFFSET 16 -#define D18F2x09C_x0000_0044_WrDqsFineDly_Byte7_WIDTH 5 -#define D18F2x09C_x0000_0044_WrDqsFineDly_Byte7_MASK 0x1f0000 -#define D18F2x09C_x0000_0044_WrDqsGrossDly_Byte7_OFFSET 21 -#define D18F2x09C_x0000_0044_WrDqsGrossDly_Byte7_WIDTH 3 -#define D18F2x09C_x0000_0044_WrDqsGrossDly_Byte7_MASK 0xe00000 -#define D18F2x09C_x0000_0044_Reserved_31_24_OFFSET 24 -#define D18F2x09C_x0000_0044_Reserved_31_24_WIDTH 8 -#define D18F2x09C_x0000_0044_Reserved_31_24_MASK 0xff000000 - -/// D18F2x09C_x0000_0044 -typedef union { - struct { ///< - UINT32 WrDqsFineDly_Byte6:5 ; ///< - UINT32 WrDqsGrossDly_Byte6:3 ; ///< - UINT32 Reserved_15_8:8 ; ///< - UINT32 WrDqsFineDly_Byte7:5 ; ///< - UINT32 WrDqsGrossDly_Byte7:3 ; ///< - UINT32 Reserved_31_24:8 ; ///< - } Field; ///< - UINT32 Value; ///< -} D18F2x09C_x0000_0044_STRUCT; - -// **** D18F2x09C_x0000_0050 Register Definition **** -// Address -#define D18F2x09C_x0000_0050_ADDRESS 0x50 - -// Type -#define D18F2x09C_x0000_0050_TYPE TYPE_D18F2x09C -// Field Data -#define D18F2x09C_x0000_0050_PhRecFineDly_Byte0_OFFSET 0 -#define D18F2x09C_x0000_0050_PhRecFineDly_Byte0_WIDTH 5 -#define D18F2x09C_x0000_0050_PhRecFineDly_Byte0_MASK 0x1f -#define D18F2x09C_x0000_0050_PhRecGrossDly_Byte0_OFFSET 5 -#define D18F2x09C_x0000_0050_PhRecGrossDly_Byte0_WIDTH 2 -#define D18F2x09C_x0000_0050_PhRecGrossDly_Byte0_MASK 0x60 -#define D18F2x09C_x0000_0050_Reserved_7_7_OFFSET 7 -#define D18F2x09C_x0000_0050_Reserved_7_7_WIDTH 1 -#define D18F2x09C_x0000_0050_Reserved_7_7_MASK 0x80 -#define D18F2x09C_x0000_0050_PhRecFineDly_Byte1_OFFSET 8 -#define D18F2x09C_x0000_0050_PhRecFineDly_Byte1_WIDTH 5 -#define D18F2x09C_x0000_0050_PhRecFineDly_Byte1_MASK 0x1f00 -#define D18F2x09C_x0000_0050_PhRecGrossDly_Byte1_OFFSET 13 -#define D18F2x09C_x0000_0050_PhRecGrossDly_Byte1_WIDTH 2 -#define D18F2x09C_x0000_0050_PhRecGrossDly_Byte1_MASK 0x6000 -#define D18F2x09C_x0000_0050_Reserved_15_15_OFFSET 15 -#define D18F2x09C_x0000_0050_Reserved_15_15_WIDTH 1 -#define D18F2x09C_x0000_0050_Reserved_15_15_MASK 0x8000 -#define D18F2x09C_x0000_0050_PhRecFineDly_Byte2_OFFSET 16 -#define D18F2x09C_x0000_0050_PhRecFineDly_Byte2_WIDTH 5 -#define D18F2x09C_x0000_0050_PhRecFineDly_Byte2_MASK 0x1f0000 -#define D18F2x09C_x0000_0050_PhRecGrossDly_Byte2_OFFSET 21 -#define D18F2x09C_x0000_0050_PhRecGrossDly_Byte2_WIDTH 2 -#define D18F2x09C_x0000_0050_PhRecGrossDly_Byte2_MASK 0x600000 -#define D18F2x09C_x0000_0050_Reserved_23_23_OFFSET 23 -#define D18F2x09C_x0000_0050_Reserved_23_23_WIDTH 1 -#define D18F2x09C_x0000_0050_Reserved_23_23_MASK 0x800000 -#define D18F2x09C_x0000_0050_PhRecFineDly_Byte3_OFFSET 24 -#define D18F2x09C_x0000_0050_PhRecFineDly_Byte3_WIDTH 5 -#define D18F2x09C_x0000_0050_PhRecFineDly_Byte3_MASK 0x1f000000 -#define D18F2x09C_x0000_0050_PhRecGrossDly_Byte3_OFFSET 29 -#define D18F2x09C_x0000_0050_PhRecGrossDly_Byte3_WIDTH 2 -#define D18F2x09C_x0000_0050_PhRecGrossDly_Byte3_MASK 0x60000000 -#define D18F2x09C_x0000_0050_Reserved_31_31_OFFSET 31 -#define D18F2x09C_x0000_0050_Reserved_31_31_WIDTH 1 -#define D18F2x09C_x0000_0050_Reserved_31_31_MASK 0x80000000 - -/// D18F2x09C_x0000_0050 -typedef union { - struct { ///< - UINT32 PhRecFineDly_Byte0:5 ; ///< - UINT32 PhRecGrossDly_Byte0:2 ; ///< - UINT32 Reserved_7_7:1 ; ///< - UINT32 PhRecFineDly_Byte1:5 ; ///< - UINT32 PhRecGrossDly_Byte1:2 ; ///< - UINT32 Reserved_15_15:1 ; ///< - UINT32 PhRecFineDly_Byte2:5 ; ///< - UINT32 PhRecGrossDly_Byte2:2 ; ///< - UINT32 Reserved_23_23:1 ; ///< - UINT32 PhRecFineDly_Byte3:5 ; ///< - UINT32 PhRecGrossDly_Byte3:2 ; ///< - UINT32 Reserved_31_31:1 ; ///< - } Field; ///< - UINT32 Value; ///< -} D18F2x09C_x0000_0050_STRUCT; - -// **** D18F2x09C_x0000_0051 Register Definition **** -// Address -#define D18F2x09C_x0000_0051_ADDRESS 0x51 - -// Type -#define D18F2x09C_x0000_0051_TYPE TYPE_D18F2x09C -// Field Data -#define D18F2x09C_x0000_0051_PhRecFineDly_Byte4_OFFSET 0 -#define D18F2x09C_x0000_0051_PhRecFineDly_Byte4_WIDTH 5 -#define D18F2x09C_x0000_0051_PhRecFineDly_Byte4_MASK 0x1f -#define D18F2x09C_x0000_0051_PhRecGrossDly_Byte4_OFFSET 5 -#define D18F2x09C_x0000_0051_PhRecGrossDly_Byte4_WIDTH 2 -#define D18F2x09C_x0000_0051_PhRecGrossDly_Byte4_MASK 0x60 -#define D18F2x09C_x0000_0051_Reserved_7_7_OFFSET 7 -#define D18F2x09C_x0000_0051_Reserved_7_7_WIDTH 1 -#define D18F2x09C_x0000_0051_Reserved_7_7_MASK 0x80 -#define D18F2x09C_x0000_0051_PhRecFineDly_Byte5_OFFSET 8 -#define D18F2x09C_x0000_0051_PhRecFineDly_Byte5_WIDTH 5 -#define D18F2x09C_x0000_0051_PhRecFineDly_Byte5_MASK 0x1f00 -#define D18F2x09C_x0000_0051_PhRecGrossDly_Byte5_OFFSET 13 -#define D18F2x09C_x0000_0051_PhRecGrossDly_Byte5_WIDTH 2 -#define D18F2x09C_x0000_0051_PhRecGrossDly_Byte5_MASK 0x6000 -#define D18F2x09C_x0000_0051_Reserved_15_15_OFFSET 15 -#define D18F2x09C_x0000_0051_Reserved_15_15_WIDTH 1 -#define D18F2x09C_x0000_0051_Reserved_15_15_MASK 0x8000 -#define D18F2x09C_x0000_0051_PhRecFineDly_Byte6_OFFSET 16 -#define D18F2x09C_x0000_0051_PhRecFineDly_Byte6_WIDTH 5 -#define D18F2x09C_x0000_0051_PhRecFineDly_Byte6_MASK 0x1f0000 -#define D18F2x09C_x0000_0051_PhRecGrossDly_Byte6_OFFSET 21 -#define D18F2x09C_x0000_0051_PhRecGrossDly_Byte6_WIDTH 2 -#define D18F2x09C_x0000_0051_PhRecGrossDly_Byte6_MASK 0x600000 -#define D18F2x09C_x0000_0051_Reserved_23_23_OFFSET 23 -#define D18F2x09C_x0000_0051_Reserved_23_23_WIDTH 1 -#define D18F2x09C_x0000_0051_Reserved_23_23_MASK 0x800000 -#define D18F2x09C_x0000_0051_PhRecFineDly_Byte7_OFFSET 24 -#define D18F2x09C_x0000_0051_PhRecFineDly_Byte7_WIDTH 5 -#define D18F2x09C_x0000_0051_PhRecFineDly_Byte7_MASK 0x1f000000 -#define D18F2x09C_x0000_0051_PhRecGrossDly_Byte7_OFFSET 29 -#define D18F2x09C_x0000_0051_PhRecGrossDly_Byte7_WIDTH 2 -#define D18F2x09C_x0000_0051_PhRecGrossDly_Byte7_MASK 0x60000000 -#define D18F2x09C_x0000_0051_Reserved_31_31_OFFSET 31 -#define D18F2x09C_x0000_0051_Reserved_31_31_WIDTH 1 -#define D18F2x09C_x0000_0051_Reserved_31_31_MASK 0x80000000 - -/// D18F2x09C_x0000_0051 -typedef union { - struct { ///< - UINT32 PhRecFineDly_Byte4:5 ; ///< - UINT32 PhRecGrossDly_Byte4:2 ; ///< - UINT32 Reserved_7_7:1 ; ///< - UINT32 PhRecFineDly_Byte5:5 ; ///< - UINT32 PhRecGrossDly_Byte5:2 ; ///< - UINT32 Reserved_15_15:1 ; ///< - UINT32 PhRecFineDly_Byte6:5 ; ///< - UINT32 PhRecGrossDly_Byte6:2 ; ///< - UINT32 Reserved_23_23:1 ; ///< - UINT32 PhRecFineDly_Byte7:5 ; ///< - UINT32 PhRecGrossDly_Byte7:2 ; ///< - UINT32 Reserved_31_31:1 ; ///< - } Field; ///< - UINT32 Value; ///< -} D18F2x09C_x0000_0051_STRUCT; - -// **** D18F2x09C_x0000_0101 Register Definition **** -// Address -#define D18F2x09C_x0000_0101_ADDRESS 0x101 - -// Type -#define D18F2x09C_x0000_0101_TYPE TYPE_D18F2x09C -// Field Data -#define D18F2x09C_x0000_0101_WrDatFineDly_Byte0_OFFSET 0 -#define D18F2x09C_x0000_0101_WrDatFineDly_Byte0_WIDTH 5 -#define D18F2x09C_x0000_0101_WrDatFineDly_Byte0_MASK 0x1f -#define D18F2x09C_x0000_0101_WrDatGrossDly_Byte0_OFFSET 5 -#define D18F2x09C_x0000_0101_WrDatGrossDly_Byte0_WIDTH 3 -#define D18F2x09C_x0000_0101_WrDatGrossDly_Byte0_MASK 0xe0 -#define D18F2x09C_x0000_0101_WrDatFineDly_Byte1_OFFSET 8 -#define D18F2x09C_x0000_0101_WrDatFineDly_Byte1_WIDTH 5 -#define D18F2x09C_x0000_0101_WrDatFineDly_Byte1_MASK 0x1f00 -#define D18F2x09C_x0000_0101_WrDatGrossDly_Byte1_OFFSET 13 -#define D18F2x09C_x0000_0101_WrDatGrossDly_Byte1_WIDTH 3 -#define D18F2x09C_x0000_0101_WrDatGrossDly_Byte1_MASK 0xe000 -#define D18F2x09C_x0000_0101_WrDatFineDly_Byte2_OFFSET 16 -#define D18F2x09C_x0000_0101_WrDatFineDly_Byte2_WIDTH 5 -#define D18F2x09C_x0000_0101_WrDatFineDly_Byte2_MASK 0x1f0000 -#define D18F2x09C_x0000_0101_WrDatGrossDly_Byte2_OFFSET 21 -#define D18F2x09C_x0000_0101_WrDatGrossDly_Byte2_WIDTH 3 -#define D18F2x09C_x0000_0101_WrDatGrossDly_Byte2_MASK 0xe00000 -#define D18F2x09C_x0000_0101_WrDatFineDly_Byte3_OFFSET 24 -#define D18F2x09C_x0000_0101_WrDatFineDly_Byte3_WIDTH 5 -#define D18F2x09C_x0000_0101_WrDatFineDly_Byte3_MASK 0x1f000000 -#define D18F2x09C_x0000_0101_WrDatGrossDly_Byte3_OFFSET 29 -#define D18F2x09C_x0000_0101_WrDatGrossDly_Byte3_WIDTH 3 -#define D18F2x09C_x0000_0101_WrDatGrossDly_Byte3_MASK 0xe0000000 - -/// D18F2x09C_x0000_0101 -typedef union { - struct { ///< - UINT32 WrDatFineDly_Byte0:5 ; ///< - UINT32 WrDatGrossDly_Byte0:3 ; ///< - UINT32 WrDatFineDly_Byte1:5 ; ///< - UINT32 WrDatGrossDly_Byte1:3 ; ///< - UINT32 WrDatFineDly_Byte2:5 ; ///< - UINT32 WrDatGrossDly_Byte2:3 ; ///< - UINT32 WrDatFineDly_Byte3:5 ; ///< - UINT32 WrDatGrossDly_Byte3:3 ; ///< - } Field; ///< - UINT32 Value; ///< -} D18F2x09C_x0000_0101_STRUCT; - -// **** D18F2x09C_x0000_0102 Register Definition **** -// Address -#define D18F2x09C_x0000_0102_ADDRESS 0x102 - -// Type -#define D18F2x09C_x0000_0102_TYPE TYPE_D18F2x09C -// Field Data -#define D18F2x09C_x0000_0102_WrDatFineDly_Byte4_OFFSET 0 -#define D18F2x09C_x0000_0102_WrDatFineDly_Byte4_WIDTH 5 -#define D18F2x09C_x0000_0102_WrDatFineDly_Byte4_MASK 0x1f -#define D18F2x09C_x0000_0102_WrDatGrossDly_Byte4_OFFSET 5 -#define D18F2x09C_x0000_0102_WrDatGrossDly_Byte4_WIDTH 3 -#define D18F2x09C_x0000_0102_WrDatGrossDly_Byte4_MASK 0xe0 -#define D18F2x09C_x0000_0102_WrDatFineDly_Byte5_OFFSET 8 -#define D18F2x09C_x0000_0102_WrDatFineDly_Byte5_WIDTH 5 -#define D18F2x09C_x0000_0102_WrDatFineDly_Byte5_MASK 0x1f00 -#define D18F2x09C_x0000_0102_WrDatGrossDly_Byte5_OFFSET 13 -#define D18F2x09C_x0000_0102_WrDatGrossDly_Byte5_WIDTH 3 -#define D18F2x09C_x0000_0102_WrDatGrossDly_Byte5_MASK 0xe000 -#define D18F2x09C_x0000_0102_WrDatFineDly_Byte6_OFFSET 16 -#define D18F2x09C_x0000_0102_WrDatFineDly_Byte6_WIDTH 5 -#define D18F2x09C_x0000_0102_WrDatFineDly_Byte6_MASK 0x1f0000 -#define D18F2x09C_x0000_0102_WrDatGrossDly_Byte6_OFFSET 21 -#define D18F2x09C_x0000_0102_WrDatGrossDly_Byte6_WIDTH 3 -#define D18F2x09C_x0000_0102_WrDatGrossDly_Byte6_MASK 0xe00000 -#define D18F2x09C_x0000_0102_WrDatFineDly_Byte7_OFFSET 24 -#define D18F2x09C_x0000_0102_WrDatFineDly_Byte7_WIDTH 5 -#define D18F2x09C_x0000_0102_WrDatFineDly_Byte7_MASK 0x1f000000 -#define D18F2x09C_x0000_0102_WrDatGrossDly_Byte7_OFFSET 29 -#define D18F2x09C_x0000_0102_WrDatGrossDly_Byte7_WIDTH 3 -#define D18F2x09C_x0000_0102_WrDatGrossDly_Byte7_MASK 0xe0000000 - -/// D18F2x09C_x0000_0102 -typedef union { - struct { ///< - UINT32 WrDatFineDly_Byte4:5 ; ///< - UINT32 WrDatGrossDly_Byte4:3 ; ///< - UINT32 WrDatFineDly_Byte5:5 ; ///< - UINT32 WrDatGrossDly_Byte5:3 ; ///< - UINT32 WrDatFineDly_Byte6:5 ; ///< - UINT32 WrDatGrossDly_Byte6:3 ; ///< - UINT32 WrDatFineDly_Byte7:5 ; ///< - UINT32 WrDatGrossDly_Byte7:3 ; ///< - } Field; ///< - UINT32 Value; ///< -} D18F2x09C_x0000_0102_STRUCT; - -// **** D18F2x09C_x0000_0105 Register Definition **** -// Address -#define D18F2x09C_x0000_0105_ADDRESS 0x105 - -// Type -#define D18F2x09C_x0000_0105_TYPE TYPE_D18F2x09C -// Field Data -#define D18F2x09C_x0000_0105_Reserved_0_0_OFFSET 0 -#define D18F2x09C_x0000_0105_Reserved_0_0_WIDTH 1 -#define D18F2x09C_x0000_0105_Reserved_0_0_MASK 0x1 -#define D18F2x09C_x0000_0105_RdDqsTime_Byte0_OFFSET 1 -#define D18F2x09C_x0000_0105_RdDqsTime_Byte0_WIDTH 5 -#define D18F2x09C_x0000_0105_RdDqsTime_Byte0_MASK 0x3e -#define D18F2x09C_x0000_0105_Reserved_8_6_OFFSET 6 -#define D18F2x09C_x0000_0105_Reserved_8_6_WIDTH 3 -#define D18F2x09C_x0000_0105_Reserved_8_6_MASK 0x1c0 -#define D18F2x09C_x0000_0105_RdDqsTime_Byte1_OFFSET 9 -#define D18F2x09C_x0000_0105_RdDqsTime_Byte1_WIDTH 5 -#define D18F2x09C_x0000_0105_RdDqsTime_Byte1_MASK 0x3e00 -#define D18F2x09C_x0000_0105_Reserved_16_14_OFFSET 14 -#define D18F2x09C_x0000_0105_Reserved_16_14_WIDTH 3 -#define D18F2x09C_x0000_0105_Reserved_16_14_MASK 0x1c000 -#define D18F2x09C_x0000_0105_RdDqsTime_Byte2_OFFSET 17 -#define D18F2x09C_x0000_0105_RdDqsTime_Byte2_WIDTH 5 -#define D18F2x09C_x0000_0105_RdDqsTime_Byte2_MASK 0x3e0000 -#define D18F2x09C_x0000_0105_Reserved_24_22_OFFSET 22 -#define D18F2x09C_x0000_0105_Reserved_24_22_WIDTH 3 -#define D18F2x09C_x0000_0105_Reserved_24_22_MASK 0x1c00000 -#define D18F2x09C_x0000_0105_RdDqsTime_Byte3_OFFSET 25 -#define D18F2x09C_x0000_0105_RdDqsTime_Byte3_WIDTH 5 -#define D18F2x09C_x0000_0105_RdDqsTime_Byte3_MASK 0x3e000000 -#define D18F2x09C_x0000_0105_Reserved_31_30_OFFSET 30 -#define D18F2x09C_x0000_0105_Reserved_31_30_WIDTH 2 -#define D18F2x09C_x0000_0105_Reserved_31_30_MASK 0xc0000000 - -/// D18F2x09C_x0000_0105 -typedef union { - struct { ///< - UINT32 Reserved_0_0:1 ; ///< - UINT32 RdDqsTime_Byte0:5 ; ///< - UINT32 Reserved_8_6:3 ; ///< - UINT32 RdDqsTime_Byte1:5 ; ///< - UINT32 Reserved_16_14:3 ; ///< - UINT32 RdDqsTime_Byte2:5 ; ///< - UINT32 Reserved_24_22:3 ; ///< - UINT32 RdDqsTime_Byte3:5 ; ///< - UINT32 Reserved_31_30:2 ; ///< - } Field; ///< - UINT32 Value; ///< -} D18F2x09C_x0000_0105_STRUCT; - -// **** D18F2x09C_x0000_0106 Register Definition **** -// Address -#define D18F2x09C_x0000_0106_ADDRESS 0x106 - -// Type -#define D18F2x09C_x0000_0106_TYPE TYPE_D18F2x09C -// Field Data -#define D18F2x09C_x0000_0106_Reserved_0_0_OFFSET 0 -#define D18F2x09C_x0000_0106_Reserved_0_0_WIDTH 1 -#define D18F2x09C_x0000_0106_Reserved_0_0_MASK 0x1 -#define D18F2x09C_x0000_0106_RdDqsTime_Byte4_OFFSET 1 -#define D18F2x09C_x0000_0106_RdDqsTime_Byte4_WIDTH 5 -#define D18F2x09C_x0000_0106_RdDqsTime_Byte4_MASK 0x3e -#define D18F2x09C_x0000_0106_Reserved_8_6_OFFSET 6 -#define D18F2x09C_x0000_0106_Reserved_8_6_WIDTH 3 -#define D18F2x09C_x0000_0106_Reserved_8_6_MASK 0x1c0 -#define D18F2x09C_x0000_0106_RdDqsTime_Byte5_OFFSET 9 -#define D18F2x09C_x0000_0106_RdDqsTime_Byte5_WIDTH 5 -#define D18F2x09C_x0000_0106_RdDqsTime_Byte5_MASK 0x3e00 -#define D18F2x09C_x0000_0106_Reserved_16_14_OFFSET 14 -#define D18F2x09C_x0000_0106_Reserved_16_14_WIDTH 3 -#define D18F2x09C_x0000_0106_Reserved_16_14_MASK 0x1c000 -#define D18F2x09C_x0000_0106_RdDqsTime_Byte6_OFFSET 17 -#define D18F2x09C_x0000_0106_RdDqsTime_Byte6_WIDTH 5 -#define D18F2x09C_x0000_0106_RdDqsTime_Byte6_MASK 0x3e0000 -#define D18F2x09C_x0000_0106_Reserved_24_22_OFFSET 22 -#define D18F2x09C_x0000_0106_Reserved_24_22_WIDTH 3 -#define D18F2x09C_x0000_0106_Reserved_24_22_MASK 0x1c00000 -#define D18F2x09C_x0000_0106_RdDqsTime_Byte7_OFFSET 25 -#define D18F2x09C_x0000_0106_RdDqsTime_Byte7_WIDTH 5 -#define D18F2x09C_x0000_0106_RdDqsTime_Byte7_MASK 0x3e000000 -#define D18F2x09C_x0000_0106_Reserved_31_30_OFFSET 30 -#define D18F2x09C_x0000_0106_Reserved_31_30_WIDTH 2 -#define D18F2x09C_x0000_0106_Reserved_31_30_MASK 0xc0000000 - -/// D18F2x09C_x0000_0106 -typedef union { - struct { ///< - UINT32 Reserved_0_0:1 ; ///< - UINT32 RdDqsTime_Byte4:5 ; ///< - UINT32 Reserved_8_6:3 ; ///< - UINT32 RdDqsTime_Byte5:5 ; ///< - UINT32 Reserved_16_14:3 ; ///< - UINT32 RdDqsTime_Byte6:5 ; ///< - UINT32 Reserved_24_22:3 ; ///< - UINT32 RdDqsTime_Byte7:5 ; ///< - UINT32 Reserved_31_30:2 ; ///< - } Field; ///< - UINT32 Value; ///< -} D18F2x09C_x0000_0106_STRUCT; - -// **** D18F2x09C_x0D0F_0002 Register Definition **** -// Address -#define D18F2x09C_x0D0F_0002_ADDRESS 0xd0f0002 - -// Type -#define D18F2x09C_x0D0F_0002_TYPE TYPE_D18F2x09C -// Field Data -#define D18F2x09C_x0D0F_0002_TxPreN_OFFSET 0 -#define D18F2x09C_x0D0F_0002_TxPreN_WIDTH 6 -#define D18F2x09C_x0D0F_0002_TxPreN_MASK 0x3f -#define D18F2x09C_x0D0F_0002_TxPreP_OFFSET 6 -#define D18F2x09C_x0D0F_0002_TxPreP_WIDTH 6 -#define D18F2x09C_x0D0F_0002_TxPreP_MASK 0xfc0 -#define D18F2x09C_x0D0F_0002_Reserved_14_12_OFFSET 12 -#define D18F2x09C_x0D0F_0002_Reserved_14_12_WIDTH 3 -#define D18F2x09C_x0D0F_0002_Reserved_14_12_MASK 0x7000 -#define D18F2x09C_x0D0F_0002_ValidTxAndPre_OFFSET 15 -#define D18F2x09C_x0D0F_0002_ValidTxAndPre_WIDTH 1 -#define D18F2x09C_x0D0F_0002_ValidTxAndPre_MASK 0x8000 -#define D18F2x09C_x0D0F_0002_Reserved_31_16_OFFSET 16 -#define D18F2x09C_x0D0F_0002_Reserved_31_16_WIDTH 16 -#define D18F2x09C_x0D0F_0002_Reserved_31_16_MASK 0xffff0000 - -/// D18F2x09C_x0D0F_0002 -typedef union { - struct { ///< - UINT32 TxPreN:6 ; ///< - UINT32 TxPreP:6 ; ///< - UINT32 Reserved_14_12:3 ; ///< - UINT32 ValidTxAndPre:1 ; ///< - UINT32 Reserved_31_16:16; ///< - } Field; ///< - UINT32 Value; ///< -} D18F2x09C_x0D0F_0002_STRUCT; - -// **** D18F2x09C_x0D0F_0006 Register Definition **** -// Address -#define D18F2x09C_x0D0F_0006_ADDRESS 0xd0f0006 - -// Type -#define D18F2x09C_x0D0F_0006_TYPE TYPE_D18F2x09C -// Field Data -#define D18F2x09C_x0D0F_0006_TxPreN_OFFSET 0 -#define D18F2x09C_x0D0F_0006_TxPreN_WIDTH 6 -#define D18F2x09C_x0D0F_0006_TxPreN_MASK 0x3f -#define D18F2x09C_x0D0F_0006_TxPreP_OFFSET 6 -#define D18F2x09C_x0D0F_0006_TxPreP_WIDTH 6 -#define D18F2x09C_x0D0F_0006_TxPreP_MASK 0xfc0 -#define D18F2x09C_x0D0F_0006_Reserved_31_12_OFFSET 12 -#define D18F2x09C_x0D0F_0006_Reserved_31_12_WIDTH 20 -#define D18F2x09C_x0D0F_0006_Reserved_31_12_MASK 0xfffff000 - -/// D18F2x09C_x0D0F_0006 -typedef union { - struct { ///< - UINT32 TxPreN:6 ; ///< - UINT32 TxPreP:6 ; ///< - UINT32 Reserved_31_12:20; ///< - } Field; ///< - UINT32 Value; ///< -} D18F2x09C_x0D0F_0006_STRUCT; - -// **** D18F2x09C_x0D0F_000A Register Definition **** -// Address -#define D18F2x09C_x0D0F_000A_ADDRESS 0xd0f000a - -// Type -#define D18F2x09C_x0D0F_000A_TYPE TYPE_D18F2x09C -// Field Data -#define D18F2x09C_x0D0F_000A_TxPreN_OFFSET 0 -#define D18F2x09C_x0D0F_000A_TxPreN_WIDTH 6 -#define D18F2x09C_x0D0F_000A_TxPreN_MASK 0x3f -#define D18F2x09C_x0D0F_000A_TxPreP_OFFSET 6 -#define D18F2x09C_x0D0F_000A_TxPreP_WIDTH 6 -#define D18F2x09C_x0D0F_000A_TxPreP_MASK 0xfc0 -#define D18F2x09C_x0D0F_000A_Reserved_31_12_OFFSET 12 -#define D18F2x09C_x0D0F_000A_Reserved_31_12_WIDTH 20 -#define D18F2x09C_x0D0F_000A_Reserved_31_12_MASK 0xfffff000 - -/// D18F2x09C_x0D0F_000A -typedef union { - struct { ///< - UINT32 TxPreN:6 ; ///< - UINT32 TxPreP:6 ; ///< - UINT32 Reserved_31_12:20; ///< - } Field; ///< - UINT32 Value; ///< -} D18F2x09C_x0D0F_000A_STRUCT; - -// **** D18F2x09C_x0D0F_000F Register Definition **** -// Address -#define D18F2x09C_x0D0F_000F_ADDRESS 0xd0f000f - -// Type -#define D18F2x09C_x0D0F_000F_TYPE TYPE_D18F2x09C -// Field Data -#define D18F2x09C_x0D0F_000F_Reserved_11_0_OFFSET 0 -#define D18F2x09C_x0D0F_000F_Reserved_11_0_WIDTH 12 -#define D18F2x09C_x0D0F_000F_Reserved_11_0_MASK 0xfff -#define D18F2x09C_x0D0F_000F_AlwaysEnDllClks_OFFSET 12 -#define D18F2x09C_x0D0F_000F_AlwaysEnDllClks_WIDTH 3 -#define D18F2x09C_x0D0F_000F_AlwaysEnDllClks_MASK 0x7000 -#define D18F2x09C_x0D0F_000F_Reserved_31_15_OFFSET 15 -#define D18F2x09C_x0D0F_000F_Reserved_31_15_WIDTH 17 -#define D18F2x09C_x0D0F_000F_Reserved_31_15_MASK 0xffff8000 - -/// D18F2x09C_x0D0F_000F -typedef union { - struct { ///< - UINT32 Reserved_11_0:12; ///< - UINT32 AlwaysEnDllClks:3 ; ///< - UINT32 Reserved_31_15:17; ///< - } Field; ///< - UINT32 Value; ///< -} D18F2x09C_x0D0F_000F_STRUCT; - -// **** D18F2x09C_x0D0F_0010 Register Definition **** -// Address -#define D18F2x09C_x0D0F_0010_ADDRESS 0xd0f0010 - -// Type -#define D18F2x09C_x0D0F_0010_TYPE TYPE_D18F2x09C -// Field Data -#define D18F2x09C_x0D0F_0010_Reserved_11_0_OFFSET 0 -#define D18F2x09C_x0D0F_0010_Reserved_11_0_WIDTH 12 -#define D18F2x09C_x0D0F_0010_Reserved_11_0_MASK 0xfff -#define D18F2x09C_x0D0F_0010_EnRxPadStandby_OFFSET 12 -#define D18F2x09C_x0D0F_0010_EnRxPadStandby_WIDTH 1 -#define D18F2x09C_x0D0F_0010_EnRxPadStandby_MASK 0x1000 -#define D18F2x09C_x0D0F_0010_Reserved_31_13_OFFSET 13 -#define D18F2x09C_x0D0F_0010_Reserved_31_13_WIDTH 19 -#define D18F2x09C_x0D0F_0010_Reserved_31_13_MASK 0xffffe000 - -/// D18F2x09C_x0D0F_0010 -typedef union { - struct { ///< - UINT32 Reserved_11_0:12; ///< - UINT32 EnRxPadStandby:1 ; ///< - UINT32 Reserved_31_13:19; ///< - } Field; ///< - UINT32 Value; ///< -} D18F2x09C_x0D0F_0010_STRUCT; - -// **** D18F2x09C_x0D0F_001F Register Definition **** -// Address -#define D18F2x09C_x0D0F_001F_ADDRESS 0xd0f001f - -// Type -#define D18F2x09C_x0D0F_001F_TYPE TYPE_D18F2x09C -// Field Data -#define D18F2x09C_x0D0F_001F_Reserved_2_0_OFFSET 0 -#define D18F2x09C_x0D0F_001F_Reserved_2_0_WIDTH 3 -#define D18F2x09C_x0D0F_001F_Reserved_2_0_MASK 0x7 -#define D18F2x09C_x0D0F_001F_RxVioLvl_OFFSET 3 -#define D18F2x09C_x0D0F_001F_RxVioLvl_WIDTH 2 -#define D18F2x09C_x0D0F_001F_RxVioLvl_MASK 0x18 -#define D18F2x09C_x0D0F_001F_Reserved_31_5_OFFSET 5 -#define D18F2x09C_x0D0F_001F_Reserved_31_5_WIDTH 27 -#define D18F2x09C_x0D0F_001F_Reserved_31_5_MASK 0xffffffe0 - -/// D18F2x09C_x0D0F_001F -typedef union { - struct { ///< - UINT32 Reserved_2_0:3 ; ///< - UINT32 RxVioLvl:2 ; ///< - UINT32 Reserved_31_5:27; ///< - } Field; ///< - UINT32 Value; ///< -} D18F2x09C_x0D0F_001F_STRUCT; - -// **** D18F2x09C_x0D0F_0030 Register Definition **** -// Address -#define D18F2x09C_x0D0F_0030_ADDRESS 0xd0f0030 - -// Type -#define D18F2x09C_x0D0F_0030_TYPE TYPE_D18F2x09C -// Field Data -#define D18F2x09C_x0D0F_0030_Reserved_4_0_OFFSET 0 -#define D18F2x09C_x0D0F_0030_Reserved_4_0_WIDTH 5 -#define D18F2x09C_x0D0F_0030_Reserved_4_0_MASK 0x1f -#define D18F2x09C_x0D0F_0030_PchgPdTxCClkGateDis_OFFSET 5 -#define D18F2x09C_x0D0F_0030_PchgPdTxCClkGateDis_WIDTH 1 -#define D18F2x09C_x0D0F_0030_PchgPdTxCClkGateDis_MASK 0x20 -#define D18F2x09C_x0D0F_0030_Reserved_31_6_OFFSET 6 -#define D18F2x09C_x0D0F_0030_Reserved_31_6_WIDTH 26 -#define D18F2x09C_x0D0F_0030_Reserved_31_6_MASK 0xffffffc0 - -/// D18F2x09C_x0D0F_0030 -typedef union { - struct { ///< - UINT32 Reserved_4_0:5 ; ///< - UINT32 PchgPdTxCClkGateDis:1 ; ///< - UINT32 Reserved_31_6:26; ///< - } Field; ///< - UINT32 Value; ///< -} D18F2x09C_x0D0F_0030_STRUCT; - -// **** D18F2x09C_x0D0F_0031 Register Definition **** -// Address -#define D18F2x09C_x0D0F_0031_ADDRESS 0xd0f0031 - -// Type -#define D18F2x09C_x0D0F_0031_TYPE TYPE_D18F2x09C -// Field Data -#define D18F2x09C_x0D0F_0031_Fence2ThresholdTxPad_OFFSET 0 -#define D18F2x09C_x0D0F_0031_Fence2ThresholdTxPad_WIDTH 4 -#define D18F2x09C_x0D0F_0031_Fence2ThresholdTxPad_MASK 0xf -#define D18F2x09C_x0D0F_0031_Fence2EnableTxPad_OFFSET 4 -#define D18F2x09C_x0D0F_0031_Fence2EnableTxPad_WIDTH 1 -#define D18F2x09C_x0D0F_0031_Fence2EnableTxPad_MASK 0x10 -#define D18F2x09C_x0D0F_0031_Fence2ThresholdTxDll_OFFSET 5 -#define D18F2x09C_x0D0F_0031_Fence2ThresholdTxDll_WIDTH 4 -#define D18F2x09C_x0D0F_0031_Fence2ThresholdTxDll_MASK 0x1e0 -#define D18F2x09C_x0D0F_0031_Fence2EnableTxDll_OFFSET 9 -#define D18F2x09C_x0D0F_0031_Fence2EnableTxDll_WIDTH 1 -#define D18F2x09C_x0D0F_0031_Fence2EnableTxDll_MASK 0x200 -#define D18F2x09C_x0D0F_0031_Fence2ThresholdRxDll_OFFSET 10 -#define D18F2x09C_x0D0F_0031_Fence2ThresholdRxDll_WIDTH 4 -#define D18F2x09C_x0D0F_0031_Fence2ThresholdRxDll_MASK 0x3c00 -#define D18F2x09C_x0D0F_0031_Fence2EnableRxDll_OFFSET 14 -#define D18F2x09C_x0D0F_0031_Fence2EnableRxDll_WIDTH 1 -#define D18F2x09C_x0D0F_0031_Fence2EnableRxDll_MASK 0x4000 -#define D18F2x09C_x0D0F_0031_Reserved_31_15_OFFSET 15 -#define D18F2x09C_x0D0F_0031_Reserved_31_15_WIDTH 17 -#define D18F2x09C_x0D0F_0031_Reserved_31_15_MASK 0xffff8000 - -/// D18F2x09C_x0D0F_0031 -typedef union { - struct { ///< - UINT32 Fence2ThresholdTxPad:4 ; ///< - UINT32 Fence2EnableTxPad:1 ; ///< - UINT32 Fence2ThresholdTxDll:4 ; ///< - UINT32 Fence2EnableTxDll:1 ; ///< - UINT32 Fence2ThresholdRxDll:4 ; ///< - UINT32 Fence2EnableRxDll:1 ; ///< - UINT32 Reserved_31_15:17; ///< - } Field; ///< - UINT32 Value; ///< -} D18F2x09C_x0D0F_0031_STRUCT; - -// **** D18F2x09C_x0D0F_0102 Register Definition **** -// Address -#define D18F2x09C_x0D0F_0102_ADDRESS 0xd0f0102 - -// Type -#define D18F2x09C_x0D0F_0102_TYPE TYPE_D18F2x09C -// Field Data -#define D18F2x09C_x0D0F_0102_TxPreN_OFFSET 0 -#define D18F2x09C_x0D0F_0102_TxPreN_WIDTH 6 -#define D18F2x09C_x0D0F_0102_TxPreN_MASK 0x3f -#define D18F2x09C_x0D0F_0102_TxPreP_OFFSET 6 -#define D18F2x09C_x0D0F_0102_TxPreP_WIDTH 6 -#define D18F2x09C_x0D0F_0102_TxPreP_MASK 0xfc0 -#define D18F2x09C_x0D0F_0102_Reserved_14_12_OFFSET 12 -#define D18F2x09C_x0D0F_0102_Reserved_14_12_WIDTH 3 -#define D18F2x09C_x0D0F_0102_Reserved_14_12_MASK 0x7000 -#define D18F2x09C_x0D0F_0102_ValidTxAndPre_OFFSET 15 -#define D18F2x09C_x0D0F_0102_ValidTxAndPre_WIDTH 1 -#define D18F2x09C_x0D0F_0102_ValidTxAndPre_MASK 0x8000 -#define D18F2x09C_x0D0F_0102_Reserved_31_16_OFFSET 16 -#define D18F2x09C_x0D0F_0102_Reserved_31_16_WIDTH 16 -#define D18F2x09C_x0D0F_0102_Reserved_31_16_MASK 0xffff0000 - -/// D18F2x09C_x0D0F_0102 -typedef union { - struct { ///< - UINT32 TxPreN:6 ; ///< - UINT32 TxPreP:6 ; ///< - UINT32 Reserved_14_12:3 ; ///< - UINT32 ValidTxAndPre:1 ; ///< - UINT32 Reserved_31_16:16; ///< - } Field; ///< - UINT32 Value; ///< -} D18F2x09C_x0D0F_0102_STRUCT; - -// **** D18F2x09C_x0D0F_0106 Register Definition **** -// Address -#define D18F2x09C_x0D0F_0106_ADDRESS 0xd0f0106 - -// Type -#define D18F2x09C_x0D0F_0106_TYPE TYPE_D18F2x09C -// Field Data -#define D18F2x09C_x0D0F_0106_TxPreN_OFFSET 0 -#define D18F2x09C_x0D0F_0106_TxPreN_WIDTH 6 -#define D18F2x09C_x0D0F_0106_TxPreN_MASK 0x3f -#define D18F2x09C_x0D0F_0106_TxPreP_OFFSET 6 -#define D18F2x09C_x0D0F_0106_TxPreP_WIDTH 6 -#define D18F2x09C_x0D0F_0106_TxPreP_MASK 0xfc0 -#define D18F2x09C_x0D0F_0106_Reserved_31_12_OFFSET 12 -#define D18F2x09C_x0D0F_0106_Reserved_31_12_WIDTH 20 -#define D18F2x09C_x0D0F_0106_Reserved_31_12_MASK 0xfffff000 - -/// D18F2x09C_x0D0F_0106 -typedef union { - struct { ///< - UINT32 TxPreN:6 ; ///< - UINT32 TxPreP:6 ; ///< - UINT32 Reserved_31_12:20; ///< - } Field; ///< - UINT32 Value; ///< -} D18F2x09C_x0D0F_0106_STRUCT; - -// **** D18F2x09C_x0D0F_010A Register Definition **** -// Address -#define D18F2x09C_x0D0F_010A_ADDRESS 0xd0f010a - -// Type -#define D18F2x09C_x0D0F_010A_TYPE TYPE_D18F2x09C -// Field Data -#define D18F2x09C_x0D0F_010A_TxPreN_OFFSET 0 -#define D18F2x09C_x0D0F_010A_TxPreN_WIDTH 6 -#define D18F2x09C_x0D0F_010A_TxPreN_MASK 0x3f -#define D18F2x09C_x0D0F_010A_TxPreP_OFFSET 6 -#define D18F2x09C_x0D0F_010A_TxPreP_WIDTH 6 -#define D18F2x09C_x0D0F_010A_TxPreP_MASK 0xfc0 -#define D18F2x09C_x0D0F_010A_Reserved_31_12_OFFSET 12 -#define D18F2x09C_x0D0F_010A_Reserved_31_12_WIDTH 20 -#define D18F2x09C_x0D0F_010A_Reserved_31_12_MASK 0xfffff000 - -/// D18F2x09C_x0D0F_010A -typedef union { - struct { ///< - UINT32 TxPreN:6 ; ///< - UINT32 TxPreP:6 ; ///< - UINT32 Reserved_31_12:20; ///< - } Field; ///< - UINT32 Value; ///< -} D18F2x09C_x0D0F_010A_STRUCT; - -// **** D18F2x09C_x0D0F_010F Register Definition **** -// Address -#define D18F2x09C_x0D0F_010F_ADDRESS 0xd0f010f - -// Type -#define D18F2x09C_x0D0F_010F_TYPE TYPE_D18F2x09C -// Field Data -#define D18F2x09C_x0D0F_010F_Reserved_11_0_OFFSET 0 -#define D18F2x09C_x0D0F_010F_Reserved_11_0_WIDTH 12 -#define D18F2x09C_x0D0F_010F_Reserved_11_0_MASK 0xfff -#define D18F2x09C_x0D0F_010F_AlwaysEnDllClks_OFFSET 12 -#define D18F2x09C_x0D0F_010F_AlwaysEnDllClks_WIDTH 3 -#define D18F2x09C_x0D0F_010F_AlwaysEnDllClks_MASK 0x7000 -#define D18F2x09C_x0D0F_010F_Reserved_31_15_OFFSET 15 -#define D18F2x09C_x0D0F_010F_Reserved_31_15_WIDTH 17 -#define D18F2x09C_x0D0F_010F_Reserved_31_15_MASK 0xffff8000 - -/// D18F2x09C_x0D0F_010F -typedef union { - struct { ///< - UINT32 Reserved_11_0:12; ///< - UINT32 AlwaysEnDllClks:3 ; ///< - UINT32 Reserved_31_15:17; ///< - } Field; ///< - UINT32 Value; ///< -} D18F2x09C_x0D0F_010F_STRUCT; - -// **** D18F2x09C_x0D0F_0110 Register Definition **** -// Address -#define D18F2x09C_x0D0F_0110_ADDRESS 0xd0f0110 - -// Type -#define D18F2x09C_x0D0F_0110_TYPE TYPE_D18F2x09C -// Field Data -#define D18F2x09C_x0D0F_0110_Reserved_11_0_OFFSET 0 -#define D18F2x09C_x0D0F_0110_Reserved_11_0_WIDTH 12 -#define D18F2x09C_x0D0F_0110_Reserved_11_0_MASK 0xfff -#define D18F2x09C_x0D0F_0110_EnRxPadStandby_OFFSET 12 -#define D18F2x09C_x0D0F_0110_EnRxPadStandby_WIDTH 1 -#define D18F2x09C_x0D0F_0110_EnRxPadStandby_MASK 0x1000 -#define D18F2x09C_x0D0F_0110_Reserved_31_13_OFFSET 13 -#define D18F2x09C_x0D0F_0110_Reserved_31_13_WIDTH 19 -#define D18F2x09C_x0D0F_0110_Reserved_31_13_MASK 0xffffe000 - -/// D18F2x09C_x0D0F_0110 -typedef union { - struct { ///< - UINT32 Reserved_11_0:12; ///< - UINT32 EnRxPadStandby:1 ; ///< - UINT32 Reserved_31_13:19; ///< - } Field; ///< - UINT32 Value; ///< -} D18F2x09C_x0D0F_0110_STRUCT; - -// **** D18F2x09C_x0D0F_011F Register Definition **** -// Address -#define D18F2x09C_x0D0F_011F_ADDRESS 0xd0f011f - -// Type -#define D18F2x09C_x0D0F_011F_TYPE TYPE_D18F2x09C -// Field Data -#define D18F2x09C_x0D0F_011F_Reserved_2_0_OFFSET 0 -#define D18F2x09C_x0D0F_011F_Reserved_2_0_WIDTH 3 -#define D18F2x09C_x0D0F_011F_Reserved_2_0_MASK 0x7 -#define D18F2x09C_x0D0F_011F_RxVioLvl_OFFSET 3 -#define D18F2x09C_x0D0F_011F_RxVioLvl_WIDTH 2 -#define D18F2x09C_x0D0F_011F_RxVioLvl_MASK 0x18 -#define D18F2x09C_x0D0F_011F_Reserved_31_5_OFFSET 5 -#define D18F2x09C_x0D0F_011F_Reserved_31_5_WIDTH 27 -#define D18F2x09C_x0D0F_011F_Reserved_31_5_MASK 0xffffffe0 - -/// D18F2x09C_x0D0F_011F -typedef union { - struct { ///< - UINT32 Reserved_2_0:3 ; ///< - UINT32 RxVioLvl:2 ; ///< - UINT32 Reserved_31_5:27; ///< - } Field; ///< - UINT32 Value; ///< -} D18F2x09C_x0D0F_011F_STRUCT; - -// **** D18F2x09C_x0D0F_0130 Register Definition **** -// Address -#define D18F2x09C_x0D0F_0130_ADDRESS 0xd0f0130 - -// Type -#define D18F2x09C_x0D0F_0130_TYPE TYPE_D18F2x09C -// Field Data -#define D18F2x09C_x0D0F_0130_Reserved_4_0_OFFSET 0 -#define D18F2x09C_x0D0F_0130_Reserved_4_0_WIDTH 5 -#define D18F2x09C_x0D0F_0130_Reserved_4_0_MASK 0x1f -#define D18F2x09C_x0D0F_0130_PchgPdTxCClkGateDis_OFFSET 5 -#define D18F2x09C_x0D0F_0130_PchgPdTxCClkGateDis_WIDTH 1 -#define D18F2x09C_x0D0F_0130_PchgPdTxCClkGateDis_MASK 0x20 -#define D18F2x09C_x0D0F_0130_Reserved_31_6_OFFSET 6 -#define D18F2x09C_x0D0F_0130_Reserved_31_6_WIDTH 26 -#define D18F2x09C_x0D0F_0130_Reserved_31_6_MASK 0xffffffc0 - -/// D18F2x09C_x0D0F_0130 -typedef union { - struct { ///< - UINT32 Reserved_4_0:5 ; ///< - UINT32 PchgPdTxCClkGateDis:1 ; ///< - UINT32 Reserved_31_6:26; ///< - } Field; ///< - UINT32 Value; ///< -} D18F2x09C_x0D0F_0130_STRUCT; - -// **** D18F2x09C_x0D0F_0131 Register Definition **** -// Address -#define D18F2x09C_x0D0F_0131_ADDRESS 0xd0f0131 - -// Type -#define D18F2x09C_x0D0F_0131_TYPE TYPE_D18F2x09C -// Field Data -#define D18F2x09C_x0D0F_0131_Fence2ThresholdTxPad_OFFSET 0 -#define D18F2x09C_x0D0F_0131_Fence2ThresholdTxPad_WIDTH 4 -#define D18F2x09C_x0D0F_0131_Fence2ThresholdTxPad_MASK 0xf -#define D18F2x09C_x0D0F_0131_Fence2EnableTxPad_OFFSET 4 -#define D18F2x09C_x0D0F_0131_Fence2EnableTxPad_WIDTH 1 -#define D18F2x09C_x0D0F_0131_Fence2EnableTxPad_MASK 0x10 -#define D18F2x09C_x0D0F_0131_Fence2ThresholdTxDll_OFFSET 5 -#define D18F2x09C_x0D0F_0131_Fence2ThresholdTxDll_WIDTH 4 -#define D18F2x09C_x0D0F_0131_Fence2ThresholdTxDll_MASK 0x1e0 -#define D18F2x09C_x0D0F_0131_Fence2EnableTxDll_OFFSET 9 -#define D18F2x09C_x0D0F_0131_Fence2EnableTxDll_WIDTH 1 -#define D18F2x09C_x0D0F_0131_Fence2EnableTxDll_MASK 0x200 -#define D18F2x09C_x0D0F_0131_Fence2ThresholdRxDll_OFFSET 10 -#define D18F2x09C_x0D0F_0131_Fence2ThresholdRxDll_WIDTH 4 -#define D18F2x09C_x0D0F_0131_Fence2ThresholdRxDll_MASK 0x3c00 -#define D18F2x09C_x0D0F_0131_Fence2EnableRxDll_OFFSET 14 -#define D18F2x09C_x0D0F_0131_Fence2EnableRxDll_WIDTH 1 -#define D18F2x09C_x0D0F_0131_Fence2EnableRxDll_MASK 0x4000 -#define D18F2x09C_x0D0F_0131_Reserved_31_15_OFFSET 15 -#define D18F2x09C_x0D0F_0131_Reserved_31_15_WIDTH 17 -#define D18F2x09C_x0D0F_0131_Reserved_31_15_MASK 0xffff8000 - -/// D18F2x09C_x0D0F_0131 -typedef union { - struct { ///< - UINT32 Fence2ThresholdTxPad:4 ; ///< - UINT32 Fence2EnableTxPad:1 ; ///< - UINT32 Fence2ThresholdTxDll:4 ; ///< - UINT32 Fence2EnableTxDll:1 ; ///< - UINT32 Fence2ThresholdRxDll:4 ; ///< - UINT32 Fence2EnableRxDll:1 ; ///< - UINT32 Reserved_31_15:17; ///< - } Field; ///< - UINT32 Value; ///< -} D18F2x09C_x0D0F_0131_STRUCT; - -// **** D18F2x09C_x0D0F_0202 Register Definition **** -// Address -#define D18F2x09C_x0D0F_0202_ADDRESS 0xd0f0202 - -// Type -#define D18F2x09C_x0D0F_0202_TYPE TYPE_D18F2x09C -// Field Data -#define D18F2x09C_x0D0F_0202_TxPreN_OFFSET 0 -#define D18F2x09C_x0D0F_0202_TxPreN_WIDTH 6 -#define D18F2x09C_x0D0F_0202_TxPreN_MASK 0x3f -#define D18F2x09C_x0D0F_0202_TxPreP_OFFSET 6 -#define D18F2x09C_x0D0F_0202_TxPreP_WIDTH 6 -#define D18F2x09C_x0D0F_0202_TxPreP_MASK 0xfc0 -#define D18F2x09C_x0D0F_0202_Reserved_14_12_OFFSET 12 -#define D18F2x09C_x0D0F_0202_Reserved_14_12_WIDTH 3 -#define D18F2x09C_x0D0F_0202_Reserved_14_12_MASK 0x7000 -#define D18F2x09C_x0D0F_0202_ValidTxAndPre_OFFSET 15 -#define D18F2x09C_x0D0F_0202_ValidTxAndPre_WIDTH 1 -#define D18F2x09C_x0D0F_0202_ValidTxAndPre_MASK 0x8000 -#define D18F2x09C_x0D0F_0202_Reserved_31_16_OFFSET 16 -#define D18F2x09C_x0D0F_0202_Reserved_31_16_WIDTH 16 -#define D18F2x09C_x0D0F_0202_Reserved_31_16_MASK 0xffff0000 - -/// D18F2x09C_x0D0F_0202 -typedef union { - struct { ///< - UINT32 TxPreN:6 ; ///< - UINT32 TxPreP:6 ; ///< - UINT32 Reserved_14_12:3 ; ///< - UINT32 ValidTxAndPre:1 ; ///< - UINT32 Reserved_31_16:16; ///< - } Field; ///< - UINT32 Value; ///< -} D18F2x09C_x0D0F_0202_STRUCT; - -// **** D18F2x09C_x0D0F_0206 Register Definition **** -// Address -#define D18F2x09C_x0D0F_0206_ADDRESS 0xd0f0206 - -// Type -#define D18F2x09C_x0D0F_0206_TYPE TYPE_D18F2x09C -// Field Data -#define D18F2x09C_x0D0F_0206_TxPreN_OFFSET 0 -#define D18F2x09C_x0D0F_0206_TxPreN_WIDTH 6 -#define D18F2x09C_x0D0F_0206_TxPreN_MASK 0x3f -#define D18F2x09C_x0D0F_0206_TxPreP_OFFSET 6 -#define D18F2x09C_x0D0F_0206_TxPreP_WIDTH 6 -#define D18F2x09C_x0D0F_0206_TxPreP_MASK 0xfc0 -#define D18F2x09C_x0D0F_0206_Reserved_31_12_OFFSET 12 -#define D18F2x09C_x0D0F_0206_Reserved_31_12_WIDTH 20 -#define D18F2x09C_x0D0F_0206_Reserved_31_12_MASK 0xfffff000 - -/// D18F2x09C_x0D0F_0206 -typedef union { - struct { ///< - UINT32 TxPreN:6 ; ///< - UINT32 TxPreP:6 ; ///< - UINT32 Reserved_31_12:20; ///< - } Field; ///< - UINT32 Value; ///< -} D18F2x09C_x0D0F_0206_STRUCT; - -// **** D18F2x09C_x0D0F_020A Register Definition **** -// Address -#define D18F2x09C_x0D0F_020A_ADDRESS 0xd0f020a - -// Type -#define D18F2x09C_x0D0F_020A_TYPE TYPE_D18F2x09C -// Field Data -#define D18F2x09C_x0D0F_020A_TxPreN_OFFSET 0 -#define D18F2x09C_x0D0F_020A_TxPreN_WIDTH 6 -#define D18F2x09C_x0D0F_020A_TxPreN_MASK 0x3f -#define D18F2x09C_x0D0F_020A_TxPreP_OFFSET 6 -#define D18F2x09C_x0D0F_020A_TxPreP_WIDTH 6 -#define D18F2x09C_x0D0F_020A_TxPreP_MASK 0xfc0 -#define D18F2x09C_x0D0F_020A_Reserved_31_12_OFFSET 12 -#define D18F2x09C_x0D0F_020A_Reserved_31_12_WIDTH 20 -#define D18F2x09C_x0D0F_020A_Reserved_31_12_MASK 0xfffff000 - -/// D18F2x09C_x0D0F_020A -typedef union { - struct { ///< - UINT32 TxPreN:6 ; ///< - UINT32 TxPreP:6 ; ///< - UINT32 Reserved_31_12:20; ///< - } Field; ///< - UINT32 Value; ///< -} D18F2x09C_x0D0F_020A_STRUCT; - -// **** D18F2x09C_x0D0F_020F Register Definition **** -// Address -#define D18F2x09C_x0D0F_020F_ADDRESS 0xd0f020f - -// Type -#define D18F2x09C_x0D0F_020F_TYPE TYPE_D18F2x09C -// Field Data -#define D18F2x09C_x0D0F_020F_Reserved_11_0_OFFSET 0 -#define D18F2x09C_x0D0F_020F_Reserved_11_0_WIDTH 12 -#define D18F2x09C_x0D0F_020F_Reserved_11_0_MASK 0xfff -#define D18F2x09C_x0D0F_020F_AlwaysEnDllClks_OFFSET 12 -#define D18F2x09C_x0D0F_020F_AlwaysEnDllClks_WIDTH 3 -#define D18F2x09C_x0D0F_020F_AlwaysEnDllClks_MASK 0x7000 -#define D18F2x09C_x0D0F_020F_Reserved_31_15_OFFSET 15 -#define D18F2x09C_x0D0F_020F_Reserved_31_15_WIDTH 17 -#define D18F2x09C_x0D0F_020F_Reserved_31_15_MASK 0xffff8000 - -/// D18F2x09C_x0D0F_020F -typedef union { - struct { ///< - UINT32 Reserved_11_0:12; ///< - UINT32 AlwaysEnDllClks:3 ; ///< - UINT32 Reserved_31_15:17; ///< - } Field; ///< - UINT32 Value; ///< -} D18F2x09C_x0D0F_020F_STRUCT; - -// **** D18F2x09C_x0D0F_0210 Register Definition **** -// Address -#define D18F2x09C_x0D0F_0210_ADDRESS 0xd0f0210 - -// Type -#define D18F2x09C_x0D0F_0210_TYPE TYPE_D18F2x09C -// Field Data -#define D18F2x09C_x0D0F_0210_Reserved_11_0_OFFSET 0 -#define D18F2x09C_x0D0F_0210_Reserved_11_0_WIDTH 12 -#define D18F2x09C_x0D0F_0210_Reserved_11_0_MASK 0xfff -#define D18F2x09C_x0D0F_0210_EnRxPadStandby_OFFSET 12 -#define D18F2x09C_x0D0F_0210_EnRxPadStandby_WIDTH 1 -#define D18F2x09C_x0D0F_0210_EnRxPadStandby_MASK 0x1000 -#define D18F2x09C_x0D0F_0210_Reserved_31_13_OFFSET 13 -#define D18F2x09C_x0D0F_0210_Reserved_31_13_WIDTH 19 -#define D18F2x09C_x0D0F_0210_Reserved_31_13_MASK 0xffffe000 - -/// D18F2x09C_x0D0F_0210 -typedef union { - struct { ///< - UINT32 Reserved_11_0:12; ///< - UINT32 EnRxPadStandby:1 ; ///< - UINT32 Reserved_31_13:19; ///< - } Field; ///< - UINT32 Value; ///< -} D18F2x09C_x0D0F_0210_STRUCT; - -// **** D18F2x09C_x0D0F_021F Register Definition **** -// Address -#define D18F2x09C_x0D0F_021F_ADDRESS 0xd0f021f - -// Type -#define D18F2x09C_x0D0F_021F_TYPE TYPE_D18F2x09C -// Field Data -#define D18F2x09C_x0D0F_021F_Reserved_2_0_OFFSET 0 -#define D18F2x09C_x0D0F_021F_Reserved_2_0_WIDTH 3 -#define D18F2x09C_x0D0F_021F_Reserved_2_0_MASK 0x7 -#define D18F2x09C_x0D0F_021F_RxVioLvl_OFFSET 3 -#define D18F2x09C_x0D0F_021F_RxVioLvl_WIDTH 2 -#define D18F2x09C_x0D0F_021F_RxVioLvl_MASK 0x18 -#define D18F2x09C_x0D0F_021F_Reserved_31_5_OFFSET 5 -#define D18F2x09C_x0D0F_021F_Reserved_31_5_WIDTH 27 -#define D18F2x09C_x0D0F_021F_Reserved_31_5_MASK 0xffffffe0 - -/// D18F2x09C_x0D0F_021F -typedef union { - struct { ///< - UINT32 Reserved_2_0:3 ; ///< - UINT32 RxVioLvl:2 ; ///< - UINT32 Reserved_31_5:27; ///< - } Field; ///< - UINT32 Value; ///< -} D18F2x09C_x0D0F_021F_STRUCT; - -// **** D18F2x09C_x0D0F_0230 Register Definition **** -// Address -#define D18F2x09C_x0D0F_0230_ADDRESS 0xd0f0230 - -// Type -#define D18F2x09C_x0D0F_0230_TYPE TYPE_D18F2x09C -// Field Data -#define D18F2x09C_x0D0F_0230_Reserved_4_0_OFFSET 0 -#define D18F2x09C_x0D0F_0230_Reserved_4_0_WIDTH 5 -#define D18F2x09C_x0D0F_0230_Reserved_4_0_MASK 0x1f -#define D18F2x09C_x0D0F_0230_PchgPdTxCClkGateDis_OFFSET 5 -#define D18F2x09C_x0D0F_0230_PchgPdTxCClkGateDis_WIDTH 1 -#define D18F2x09C_x0D0F_0230_PchgPdTxCClkGateDis_MASK 0x20 -#define D18F2x09C_x0D0F_0230_Reserved_31_6_OFFSET 6 -#define D18F2x09C_x0D0F_0230_Reserved_31_6_WIDTH 26 -#define D18F2x09C_x0D0F_0230_Reserved_31_6_MASK 0xffffffc0 - -/// D18F2x09C_x0D0F_0230 -typedef union { - struct { ///< - UINT32 Reserved_4_0:5 ; ///< - UINT32 PchgPdTxCClkGateDis:1 ; ///< - UINT32 Reserved_31_6:26; ///< - } Field; ///< - UINT32 Value; ///< -} D18F2x09C_x0D0F_0230_STRUCT; - -// **** D18F2x09C_x0D0F_0231 Register Definition **** -// Address -#define D18F2x09C_x0D0F_0231_ADDRESS 0xd0f0231 - -// Type -#define D18F2x09C_x0D0F_0231_TYPE TYPE_D18F2x09C -// Field Data -#define D18F2x09C_x0D0F_0231_Fence2ThresholdTxPad_OFFSET 0 -#define D18F2x09C_x0D0F_0231_Fence2ThresholdTxPad_WIDTH 4 -#define D18F2x09C_x0D0F_0231_Fence2ThresholdTxPad_MASK 0xf -#define D18F2x09C_x0D0F_0231_Fence2EnableTxPad_OFFSET 4 -#define D18F2x09C_x0D0F_0231_Fence2EnableTxPad_WIDTH 1 -#define D18F2x09C_x0D0F_0231_Fence2EnableTxPad_MASK 0x10 -#define D18F2x09C_x0D0F_0231_Fence2ThresholdTxDll_OFFSET 5 -#define D18F2x09C_x0D0F_0231_Fence2ThresholdTxDll_WIDTH 4 -#define D18F2x09C_x0D0F_0231_Fence2ThresholdTxDll_MASK 0x1e0 -#define D18F2x09C_x0D0F_0231_Fence2EnableTxDll_OFFSET 9 -#define D18F2x09C_x0D0F_0231_Fence2EnableTxDll_WIDTH 1 -#define D18F2x09C_x0D0F_0231_Fence2EnableTxDll_MASK 0x200 -#define D18F2x09C_x0D0F_0231_Fence2ThresholdRxDll_OFFSET 10 -#define D18F2x09C_x0D0F_0231_Fence2ThresholdRxDll_WIDTH 4 -#define D18F2x09C_x0D0F_0231_Fence2ThresholdRxDll_MASK 0x3c00 -#define D18F2x09C_x0D0F_0231_Fence2EnableRxDll_OFFSET 14 -#define D18F2x09C_x0D0F_0231_Fence2EnableRxDll_WIDTH 1 -#define D18F2x09C_x0D0F_0231_Fence2EnableRxDll_MASK 0x4000 -#define D18F2x09C_x0D0F_0231_Reserved_31_15_OFFSET 15 -#define D18F2x09C_x0D0F_0231_Reserved_31_15_WIDTH 17 -#define D18F2x09C_x0D0F_0231_Reserved_31_15_MASK 0xffff8000 - -/// D18F2x09C_x0D0F_0231 -typedef union { - struct { ///< - UINT32 Fence2ThresholdTxPad:4 ; ///< - UINT32 Fence2EnableTxPad:1 ; ///< - UINT32 Fence2ThresholdTxDll:4 ; ///< - UINT32 Fence2EnableTxDll:1 ; ///< - UINT32 Fence2ThresholdRxDll:4 ; ///< - UINT32 Fence2EnableRxDll:1 ; ///< - UINT32 Reserved_31_15:17; ///< - } Field; ///< - UINT32 Value; ///< -} D18F2x09C_x0D0F_0231_STRUCT; - -// **** D18F2x09C_x0D0F_0302 Register Definition **** -// Address -#define D18F2x09C_x0D0F_0302_ADDRESS 0xd0f0302 - -// Type -#define D18F2x09C_x0D0F_0302_TYPE TYPE_D18F2x09C -// Field Data -#define D18F2x09C_x0D0F_0302_TxPreN_OFFSET 0 -#define D18F2x09C_x0D0F_0302_TxPreN_WIDTH 6 -#define D18F2x09C_x0D0F_0302_TxPreN_MASK 0x3f -#define D18F2x09C_x0D0F_0302_TxPreP_OFFSET 6 -#define D18F2x09C_x0D0F_0302_TxPreP_WIDTH 6 -#define D18F2x09C_x0D0F_0302_TxPreP_MASK 0xfc0 -#define D18F2x09C_x0D0F_0302_Reserved_14_12_OFFSET 12 -#define D18F2x09C_x0D0F_0302_Reserved_14_12_WIDTH 3 -#define D18F2x09C_x0D0F_0302_Reserved_14_12_MASK 0x7000 -#define D18F2x09C_x0D0F_0302_ValidTxAndPre_OFFSET 15 -#define D18F2x09C_x0D0F_0302_ValidTxAndPre_WIDTH 1 -#define D18F2x09C_x0D0F_0302_ValidTxAndPre_MASK 0x8000 -#define D18F2x09C_x0D0F_0302_Reserved_31_16_OFFSET 16 -#define D18F2x09C_x0D0F_0302_Reserved_31_16_WIDTH 16 -#define D18F2x09C_x0D0F_0302_Reserved_31_16_MASK 0xffff0000 - -/// D18F2x09C_x0D0F_0302 -typedef union { - struct { ///< - UINT32 TxPreN:6 ; ///< - UINT32 TxPreP:6 ; ///< - UINT32 Reserved_14_12:3 ; ///< - UINT32 ValidTxAndPre:1 ; ///< - UINT32 Reserved_31_16:16; ///< - } Field; ///< - UINT32 Value; ///< -} D18F2x09C_x0D0F_0302_STRUCT; - -// **** D18F2x09C_x0D0F_0306 Register Definition **** -// Address -#define D18F2x09C_x0D0F_0306_ADDRESS 0xd0f0306 - -// Type -#define D18F2x09C_x0D0F_0306_TYPE TYPE_D18F2x09C -// Field Data -#define D18F2x09C_x0D0F_0306_TxPreN_OFFSET 0 -#define D18F2x09C_x0D0F_0306_TxPreN_WIDTH 6 -#define D18F2x09C_x0D0F_0306_TxPreN_MASK 0x3f -#define D18F2x09C_x0D0F_0306_TxPreP_OFFSET 6 -#define D18F2x09C_x0D0F_0306_TxPreP_WIDTH 6 -#define D18F2x09C_x0D0F_0306_TxPreP_MASK 0xfc0 -#define D18F2x09C_x0D0F_0306_Reserved_31_12_OFFSET 12 -#define D18F2x09C_x0D0F_0306_Reserved_31_12_WIDTH 20 -#define D18F2x09C_x0D0F_0306_Reserved_31_12_MASK 0xfffff000 - -/// D18F2x09C_x0D0F_0306 -typedef union { - struct { ///< - UINT32 TxPreN:6 ; ///< - UINT32 TxPreP:6 ; ///< - UINT32 Reserved_31_12:20; ///< - } Field; ///< - UINT32 Value; ///< -} D18F2x09C_x0D0F_0306_STRUCT; - -// **** D18F2x09C_x0D0F_030A Register Definition **** -// Address -#define D18F2x09C_x0D0F_030A_ADDRESS 0xd0f030a - -// Type -#define D18F2x09C_x0D0F_030A_TYPE TYPE_D18F2x09C -// Field Data -#define D18F2x09C_x0D0F_030A_TxPreN_OFFSET 0 -#define D18F2x09C_x0D0F_030A_TxPreN_WIDTH 6 -#define D18F2x09C_x0D0F_030A_TxPreN_MASK 0x3f -#define D18F2x09C_x0D0F_030A_TxPreP_OFFSET 6 -#define D18F2x09C_x0D0F_030A_TxPreP_WIDTH 6 -#define D18F2x09C_x0D0F_030A_TxPreP_MASK 0xfc0 -#define D18F2x09C_x0D0F_030A_Reserved_31_12_OFFSET 12 -#define D18F2x09C_x0D0F_030A_Reserved_31_12_WIDTH 20 -#define D18F2x09C_x0D0F_030A_Reserved_31_12_MASK 0xfffff000 - -/// D18F2x09C_x0D0F_030A -typedef union { - struct { ///< - UINT32 TxPreN:6 ; ///< - UINT32 TxPreP:6 ; ///< - UINT32 Reserved_31_12:20; ///< - } Field; ///< - UINT32 Value; ///< -} D18F2x09C_x0D0F_030A_STRUCT; - -// **** D18F2x09C_x0D0F_030F Register Definition **** -// Address -#define D18F2x09C_x0D0F_030F_ADDRESS 0xd0f030f - -// Type -#define D18F2x09C_x0D0F_030F_TYPE TYPE_D18F2x09C -// Field Data -#define D18F2x09C_x0D0F_030F_Reserved_11_0_OFFSET 0 -#define D18F2x09C_x0D0F_030F_Reserved_11_0_WIDTH 12 -#define D18F2x09C_x0D0F_030F_Reserved_11_0_MASK 0xfff -#define D18F2x09C_x0D0F_030F_AlwaysEnDllClks_OFFSET 12 -#define D18F2x09C_x0D0F_030F_AlwaysEnDllClks_WIDTH 3 -#define D18F2x09C_x0D0F_030F_AlwaysEnDllClks_MASK 0x7000 -#define D18F2x09C_x0D0F_030F_Reserved_31_15_OFFSET 15 -#define D18F2x09C_x0D0F_030F_Reserved_31_15_WIDTH 17 -#define D18F2x09C_x0D0F_030F_Reserved_31_15_MASK 0xffff8000 - -/// D18F2x09C_x0D0F_030F -typedef union { - struct { ///< - UINT32 Reserved_11_0:12; ///< - UINT32 AlwaysEnDllClks:3 ; ///< - UINT32 Reserved_31_15:17; ///< - } Field; ///< - UINT32 Value; ///< -} D18F2x09C_x0D0F_030F_STRUCT; - -// **** D18F2x09C_x0D0F_0310 Register Definition **** -// Address -#define D18F2x09C_x0D0F_0310_ADDRESS 0xd0f0310 - -// Type -#define D18F2x09C_x0D0F_0310_TYPE TYPE_D18F2x09C -// Field Data -#define D18F2x09C_x0D0F_0310_Reserved_11_0_OFFSET 0 -#define D18F2x09C_x0D0F_0310_Reserved_11_0_WIDTH 12 -#define D18F2x09C_x0D0F_0310_Reserved_11_0_MASK 0xfff -#define D18F2x09C_x0D0F_0310_EnRxPadStandby_OFFSET 12 -#define D18F2x09C_x0D0F_0310_EnRxPadStandby_WIDTH 1 -#define D18F2x09C_x0D0F_0310_EnRxPadStandby_MASK 0x1000 -#define D18F2x09C_x0D0F_0310_Reserved_31_13_OFFSET 13 -#define D18F2x09C_x0D0F_0310_Reserved_31_13_WIDTH 19 -#define D18F2x09C_x0D0F_0310_Reserved_31_13_MASK 0xffffe000 - -/// D18F2x09C_x0D0F_0310 -typedef union { - struct { ///< - UINT32 Reserved_11_0:12; ///< - UINT32 EnRxPadStandby:1 ; ///< - UINT32 Reserved_31_13:19; ///< - } Field; ///< - UINT32 Value; ///< -} D18F2x09C_x0D0F_0310_STRUCT; - -// **** D18F2x09C_x0D0F_031F Register Definition **** -// Address -#define D18F2x09C_x0D0F_031F_ADDRESS 0xd0f031f - -// Type -#define D18F2x09C_x0D0F_031F_TYPE TYPE_D18F2x09C -// Field Data -#define D18F2x09C_x0D0F_031F_Reserved_2_0_OFFSET 0 -#define D18F2x09C_x0D0F_031F_Reserved_2_0_WIDTH 3 -#define D18F2x09C_x0D0F_031F_Reserved_2_0_MASK 0x7 -#define D18F2x09C_x0D0F_031F_RxVioLvl_OFFSET 3 -#define D18F2x09C_x0D0F_031F_RxVioLvl_WIDTH 2 -#define D18F2x09C_x0D0F_031F_RxVioLvl_MASK 0x18 -#define D18F2x09C_x0D0F_031F_Reserved_31_5_OFFSET 5 -#define D18F2x09C_x0D0F_031F_Reserved_31_5_WIDTH 27 -#define D18F2x09C_x0D0F_031F_Reserved_31_5_MASK 0xffffffe0 - -/// D18F2x09C_x0D0F_031F -typedef union { - struct { ///< - UINT32 Reserved_2_0:3 ; ///< - UINT32 RxVioLvl:2 ; ///< - UINT32 Reserved_31_5:27; ///< - } Field; ///< - UINT32 Value; ///< -} D18F2x09C_x0D0F_031F_STRUCT; - -// **** D18F2x09C_x0D0F_0330 Register Definition **** -// Address -#define D18F2x09C_x0D0F_0330_ADDRESS 0xd0f0330 - -// Type -#define D18F2x09C_x0D0F_0330_TYPE TYPE_D18F2x09C -// Field Data -#define D18F2x09C_x0D0F_0330_Reserved_4_0_OFFSET 0 -#define D18F2x09C_x0D0F_0330_Reserved_4_0_WIDTH 5 -#define D18F2x09C_x0D0F_0330_Reserved_4_0_MASK 0x1f -#define D18F2x09C_x0D0F_0330_PchgPdTxCClkGateDis_OFFSET 5 -#define D18F2x09C_x0D0F_0330_PchgPdTxCClkGateDis_WIDTH 1 -#define D18F2x09C_x0D0F_0330_PchgPdTxCClkGateDis_MASK 0x20 -#define D18F2x09C_x0D0F_0330_Reserved_31_6_OFFSET 6 -#define D18F2x09C_x0D0F_0330_Reserved_31_6_WIDTH 26 -#define D18F2x09C_x0D0F_0330_Reserved_31_6_MASK 0xffffffc0 - -/// D18F2x09C_x0D0F_0330 -typedef union { - struct { ///< - UINT32 Reserved_4_0:5 ; ///< - UINT32 PchgPdTxCClkGateDis:1 ; ///< - UINT32 Reserved_31_6:26; ///< - } Field; ///< - UINT32 Value; ///< -} D18F2x09C_x0D0F_0330_STRUCT; - -// **** D18F2x09C_x0D0F_0331 Register Definition **** -// Address -#define D18F2x09C_x0D0F_0331_ADDRESS 0xd0f0331 - -// Type -#define D18F2x09C_x0D0F_0331_TYPE TYPE_D18F2x09C -// Field Data -#define D18F2x09C_x0D0F_0331_Fence2ThresholdTxPad_OFFSET 0 -#define D18F2x09C_x0D0F_0331_Fence2ThresholdTxPad_WIDTH 4 -#define D18F2x09C_x0D0F_0331_Fence2ThresholdTxPad_MASK 0xf -#define D18F2x09C_x0D0F_0331_Fence2EnableTxPad_OFFSET 4 -#define D18F2x09C_x0D0F_0331_Fence2EnableTxPad_WIDTH 1 -#define D18F2x09C_x0D0F_0331_Fence2EnableTxPad_MASK 0x10 -#define D18F2x09C_x0D0F_0331_Fence2ThresholdTxDll_OFFSET 5 -#define D18F2x09C_x0D0F_0331_Fence2ThresholdTxDll_WIDTH 4 -#define D18F2x09C_x0D0F_0331_Fence2ThresholdTxDll_MASK 0x1e0 -#define D18F2x09C_x0D0F_0331_Fence2EnableTxDll_OFFSET 9 -#define D18F2x09C_x0D0F_0331_Fence2EnableTxDll_WIDTH 1 -#define D18F2x09C_x0D0F_0331_Fence2EnableTxDll_MASK 0x200 -#define D18F2x09C_x0D0F_0331_Fence2ThresholdRxDll_OFFSET 10 -#define D18F2x09C_x0D0F_0331_Fence2ThresholdRxDll_WIDTH 4 -#define D18F2x09C_x0D0F_0331_Fence2ThresholdRxDll_MASK 0x3c00 -#define D18F2x09C_x0D0F_0331_Fence2EnableRxDll_OFFSET 14 -#define D18F2x09C_x0D0F_0331_Fence2EnableRxDll_WIDTH 1 -#define D18F2x09C_x0D0F_0331_Fence2EnableRxDll_MASK 0x4000 -#define D18F2x09C_x0D0F_0331_Reserved_31_15_OFFSET 15 -#define D18F2x09C_x0D0F_0331_Reserved_31_15_WIDTH 17 -#define D18F2x09C_x0D0F_0331_Reserved_31_15_MASK 0xffff8000 - -/// D18F2x09C_x0D0F_0331 -typedef union { - struct { ///< - UINT32 Fence2ThresholdTxPad:4 ; ///< - UINT32 Fence2EnableTxPad:1 ; ///< - UINT32 Fence2ThresholdTxDll:4 ; ///< - UINT32 Fence2EnableTxDll:1 ; ///< - UINT32 Fence2ThresholdRxDll:4 ; ///< - UINT32 Fence2EnableRxDll:1 ; ///< - UINT32 Reserved_31_15:17; ///< - } Field; ///< - UINT32 Value; ///< -} D18F2x09C_x0D0F_0331_STRUCT; - -// **** D18F2x09C_x0D0F_0402 Register Definition **** -// Address -#define D18F2x09C_x0D0F_0402_ADDRESS 0xd0f0402 - -// Type -#define D18F2x09C_x0D0F_0402_TYPE TYPE_D18F2x09C -// Field Data -#define D18F2x09C_x0D0F_0402_TxPreN_OFFSET 0 -#define D18F2x09C_x0D0F_0402_TxPreN_WIDTH 6 -#define D18F2x09C_x0D0F_0402_TxPreN_MASK 0x3f -#define D18F2x09C_x0D0F_0402_TxPreP_OFFSET 6 -#define D18F2x09C_x0D0F_0402_TxPreP_WIDTH 6 -#define D18F2x09C_x0D0F_0402_TxPreP_MASK 0xfc0 -#define D18F2x09C_x0D0F_0402_Reserved_14_12_OFFSET 12 -#define D18F2x09C_x0D0F_0402_Reserved_14_12_WIDTH 3 -#define D18F2x09C_x0D0F_0402_Reserved_14_12_MASK 0x7000 -#define D18F2x09C_x0D0F_0402_ValidTxAndPre_OFFSET 15 -#define D18F2x09C_x0D0F_0402_ValidTxAndPre_WIDTH 1 -#define D18F2x09C_x0D0F_0402_ValidTxAndPre_MASK 0x8000 -#define D18F2x09C_x0D0F_0402_Reserved_31_16_OFFSET 16 -#define D18F2x09C_x0D0F_0402_Reserved_31_16_WIDTH 16 -#define D18F2x09C_x0D0F_0402_Reserved_31_16_MASK 0xffff0000 - -/// D18F2x09C_x0D0F_0402 -typedef union { - struct { ///< - UINT32 TxPreN:6 ; ///< - UINT32 TxPreP:6 ; ///< - UINT32 Reserved_14_12:3 ; ///< - UINT32 ValidTxAndPre:1 ; ///< - UINT32 Reserved_31_16:16; ///< - } Field; ///< - UINT32 Value; ///< -} D18F2x09C_x0D0F_0402_STRUCT; - -// **** D18F2x09C_x0D0F_0406 Register Definition **** -// Address -#define D18F2x09C_x0D0F_0406_ADDRESS 0xd0f0406 - -// Type -#define D18F2x09C_x0D0F_0406_TYPE TYPE_D18F2x09C -// Field Data -#define D18F2x09C_x0D0F_0406_TxPreN_OFFSET 0 -#define D18F2x09C_x0D0F_0406_TxPreN_WIDTH 6 -#define D18F2x09C_x0D0F_0406_TxPreN_MASK 0x3f -#define D18F2x09C_x0D0F_0406_TxPreP_OFFSET 6 -#define D18F2x09C_x0D0F_0406_TxPreP_WIDTH 6 -#define D18F2x09C_x0D0F_0406_TxPreP_MASK 0xfc0 -#define D18F2x09C_x0D0F_0406_Reserved_31_12_OFFSET 12 -#define D18F2x09C_x0D0F_0406_Reserved_31_12_WIDTH 20 -#define D18F2x09C_x0D0F_0406_Reserved_31_12_MASK 0xfffff000 - -/// D18F2x09C_x0D0F_0406 -typedef union { - struct { ///< - UINT32 TxPreN:6 ; ///< - UINT32 TxPreP:6 ; ///< - UINT32 Reserved_31_12:20; ///< - } Field; ///< - UINT32 Value; ///< -} D18F2x09C_x0D0F_0406_STRUCT; - -// **** D18F2x09C_x0D0F_040A Register Definition **** -// Address -#define D18F2x09C_x0D0F_040A_ADDRESS 0xd0f040a - -// Type -#define D18F2x09C_x0D0F_040A_TYPE TYPE_D18F2x09C -// Field Data -#define D18F2x09C_x0D0F_040A_TxPreN_OFFSET 0 -#define D18F2x09C_x0D0F_040A_TxPreN_WIDTH 6 -#define D18F2x09C_x0D0F_040A_TxPreN_MASK 0x3f -#define D18F2x09C_x0D0F_040A_TxPreP_OFFSET 6 -#define D18F2x09C_x0D0F_040A_TxPreP_WIDTH 6 -#define D18F2x09C_x0D0F_040A_TxPreP_MASK 0xfc0 -#define D18F2x09C_x0D0F_040A_Reserved_31_12_OFFSET 12 -#define D18F2x09C_x0D0F_040A_Reserved_31_12_WIDTH 20 -#define D18F2x09C_x0D0F_040A_Reserved_31_12_MASK 0xfffff000 - -/// D18F2x09C_x0D0F_040A -typedef union { - struct { ///< - UINT32 TxPreN:6 ; ///< - UINT32 TxPreP:6 ; ///< - UINT32 Reserved_31_12:20; ///< - } Field; ///< - UINT32 Value; ///< -} D18F2x09C_x0D0F_040A_STRUCT; - -// **** D18F2x09C_x0D0F_040F Register Definition **** -// Address -#define D18F2x09C_x0D0F_040F_ADDRESS 0xd0f040f - -// Type -#define D18F2x09C_x0D0F_040F_TYPE TYPE_D18F2x09C -// Field Data -#define D18F2x09C_x0D0F_040F_Reserved_11_0_OFFSET 0 -#define D18F2x09C_x0D0F_040F_Reserved_11_0_WIDTH 12 -#define D18F2x09C_x0D0F_040F_Reserved_11_0_MASK 0xfff -#define D18F2x09C_x0D0F_040F_AlwaysEnDllClks_OFFSET 12 -#define D18F2x09C_x0D0F_040F_AlwaysEnDllClks_WIDTH 3 -#define D18F2x09C_x0D0F_040F_AlwaysEnDllClks_MASK 0x7000 -#define D18F2x09C_x0D0F_040F_Reserved_31_15_OFFSET 15 -#define D18F2x09C_x0D0F_040F_Reserved_31_15_WIDTH 17 -#define D18F2x09C_x0D0F_040F_Reserved_31_15_MASK 0xffff8000 - -/// D18F2x09C_x0D0F_040F -typedef union { - struct { ///< - UINT32 Reserved_11_0:12; ///< - UINT32 AlwaysEnDllClks:3 ; ///< - UINT32 Reserved_31_15:17; ///< - } Field; ///< - UINT32 Value; ///< -} D18F2x09C_x0D0F_040F_STRUCT; - -// **** D18F2x09C_x0D0F_0410 Register Definition **** -// Address -#define D18F2x09C_x0D0F_0410_ADDRESS 0xd0f0410 - -// Type -#define D18F2x09C_x0D0F_0410_TYPE TYPE_D18F2x09C -// Field Data -#define D18F2x09C_x0D0F_0410_Reserved_11_0_OFFSET 0 -#define D18F2x09C_x0D0F_0410_Reserved_11_0_WIDTH 12 -#define D18F2x09C_x0D0F_0410_Reserved_11_0_MASK 0xfff -#define D18F2x09C_x0D0F_0410_EnRxPadStandby_OFFSET 12 -#define D18F2x09C_x0D0F_0410_EnRxPadStandby_WIDTH 1 -#define D18F2x09C_x0D0F_0410_EnRxPadStandby_MASK 0x1000 -#define D18F2x09C_x0D0F_0410_Reserved_31_13_OFFSET 13 -#define D18F2x09C_x0D0F_0410_Reserved_31_13_WIDTH 19 -#define D18F2x09C_x0D0F_0410_Reserved_31_13_MASK 0xffffe000 - -/// D18F2x09C_x0D0F_0410 -typedef union { - struct { ///< - UINT32 Reserved_11_0:12; ///< - UINT32 EnRxPadStandby:1 ; ///< - UINT32 Reserved_31_13:19; ///< - } Field; ///< - UINT32 Value; ///< -} D18F2x09C_x0D0F_0410_STRUCT; - -// **** D18F2x09C_x0D0F_041F Register Definition **** -// Address -#define D18F2x09C_x0D0F_041F_ADDRESS 0xd0f041f - -// Type -#define D18F2x09C_x0D0F_041F_TYPE TYPE_D18F2x09C -// Field Data -#define D18F2x09C_x0D0F_041F_Reserved_2_0_OFFSET 0 -#define D18F2x09C_x0D0F_041F_Reserved_2_0_WIDTH 3 -#define D18F2x09C_x0D0F_041F_Reserved_2_0_MASK 0x7 -#define D18F2x09C_x0D0F_041F_RxVioLvl_OFFSET 3 -#define D18F2x09C_x0D0F_041F_RxVioLvl_WIDTH 2 -#define D18F2x09C_x0D0F_041F_RxVioLvl_MASK 0x18 -#define D18F2x09C_x0D0F_041F_Reserved_31_5_OFFSET 5 -#define D18F2x09C_x0D0F_041F_Reserved_31_5_WIDTH 27 -#define D18F2x09C_x0D0F_041F_Reserved_31_5_MASK 0xffffffe0 - -/// D18F2x09C_x0D0F_041F -typedef union { - struct { ///< - UINT32 Reserved_2_0:3 ; ///< - UINT32 RxVioLvl:2 ; ///< - UINT32 Reserved_31_5:27; ///< - } Field; ///< - UINT32 Value; ///< -} D18F2x09C_x0D0F_041F_STRUCT; - -// **** D18F2x09C_x0D0F_0430 Register Definition **** -// Address -#define D18F2x09C_x0D0F_0430_ADDRESS 0xd0f0430 - -// Type -#define D18F2x09C_x0D0F_0430_TYPE TYPE_D18F2x09C -// Field Data -#define D18F2x09C_x0D0F_0430_Reserved_4_0_OFFSET 0 -#define D18F2x09C_x0D0F_0430_Reserved_4_0_WIDTH 5 -#define D18F2x09C_x0D0F_0430_Reserved_4_0_MASK 0x1f -#define D18F2x09C_x0D0F_0430_PchgPdTxCClkGateDis_OFFSET 5 -#define D18F2x09C_x0D0F_0430_PchgPdTxCClkGateDis_WIDTH 1 -#define D18F2x09C_x0D0F_0430_PchgPdTxCClkGateDis_MASK 0x20 -#define D18F2x09C_x0D0F_0430_Reserved_31_6_OFFSET 6 -#define D18F2x09C_x0D0F_0430_Reserved_31_6_WIDTH 26 -#define D18F2x09C_x0D0F_0430_Reserved_31_6_MASK 0xffffffc0 - -/// D18F2x09C_x0D0F_0430 -typedef union { - struct { ///< - UINT32 Reserved_4_0:5 ; ///< - UINT32 PchgPdTxCClkGateDis:1 ; ///< - UINT32 Reserved_31_6:26; ///< - } Field; ///< - UINT32 Value; ///< -} D18F2x09C_x0D0F_0430_STRUCT; - -// **** D18F2x09C_x0D0F_0431 Register Definition **** -// Address -#define D18F2x09C_x0D0F_0431_ADDRESS 0xd0f0431 - -// Type -#define D18F2x09C_x0D0F_0431_TYPE TYPE_D18F2x09C -// Field Data -#define D18F2x09C_x0D0F_0431_Fence2ThresholdTxPad_OFFSET 0 -#define D18F2x09C_x0D0F_0431_Fence2ThresholdTxPad_WIDTH 4 -#define D18F2x09C_x0D0F_0431_Fence2ThresholdTxPad_MASK 0xf -#define D18F2x09C_x0D0F_0431_Fence2EnableTxPad_OFFSET 4 -#define D18F2x09C_x0D0F_0431_Fence2EnableTxPad_WIDTH 1 -#define D18F2x09C_x0D0F_0431_Fence2EnableTxPad_MASK 0x10 -#define D18F2x09C_x0D0F_0431_Fence2ThresholdTxDll_OFFSET 5 -#define D18F2x09C_x0D0F_0431_Fence2ThresholdTxDll_WIDTH 4 -#define D18F2x09C_x0D0F_0431_Fence2ThresholdTxDll_MASK 0x1e0 -#define D18F2x09C_x0D0F_0431_Fence2EnableTxDll_OFFSET 9 -#define D18F2x09C_x0D0F_0431_Fence2EnableTxDll_WIDTH 1 -#define D18F2x09C_x0D0F_0431_Fence2EnableTxDll_MASK 0x200 -#define D18F2x09C_x0D0F_0431_Fence2ThresholdRxDll_OFFSET 10 -#define D18F2x09C_x0D0F_0431_Fence2ThresholdRxDll_WIDTH 4 -#define D18F2x09C_x0D0F_0431_Fence2ThresholdRxDll_MASK 0x3c00 -#define D18F2x09C_x0D0F_0431_Fence2EnableRxDll_OFFSET 14 -#define D18F2x09C_x0D0F_0431_Fence2EnableRxDll_WIDTH 1 -#define D18F2x09C_x0D0F_0431_Fence2EnableRxDll_MASK 0x4000 -#define D18F2x09C_x0D0F_0431_Reserved_31_15_OFFSET 15 -#define D18F2x09C_x0D0F_0431_Reserved_31_15_WIDTH 17 -#define D18F2x09C_x0D0F_0431_Reserved_31_15_MASK 0xffff8000 - -/// D18F2x09C_x0D0F_0431 -typedef union { - struct { ///< - UINT32 Fence2ThresholdTxPad:4 ; ///< - UINT32 Fence2EnableTxPad:1 ; ///< - UINT32 Fence2ThresholdTxDll:4 ; ///< - UINT32 Fence2EnableTxDll:1 ; ///< - UINT32 Fence2ThresholdRxDll:4 ; ///< - UINT32 Fence2EnableRxDll:1 ; ///< - UINT32 Reserved_31_15:17; ///< - } Field; ///< - UINT32 Value; ///< -} D18F2x09C_x0D0F_0431_STRUCT; - -// **** D18F2x09C_x0D0F_0502 Register Definition **** -// Address -#define D18F2x09C_x0D0F_0502_ADDRESS 0xd0f0502 - -// Type -#define D18F2x09C_x0D0F_0502_TYPE TYPE_D18F2x09C -// Field Data -#define D18F2x09C_x0D0F_0502_TxPreN_OFFSET 0 -#define D18F2x09C_x0D0F_0502_TxPreN_WIDTH 6 -#define D18F2x09C_x0D0F_0502_TxPreN_MASK 0x3f -#define D18F2x09C_x0D0F_0502_TxPreP_OFFSET 6 -#define D18F2x09C_x0D0F_0502_TxPreP_WIDTH 6 -#define D18F2x09C_x0D0F_0502_TxPreP_MASK 0xfc0 -#define D18F2x09C_x0D0F_0502_Reserved_14_12_OFFSET 12 -#define D18F2x09C_x0D0F_0502_Reserved_14_12_WIDTH 3 -#define D18F2x09C_x0D0F_0502_Reserved_14_12_MASK 0x7000 -#define D18F2x09C_x0D0F_0502_ValidTxAndPre_OFFSET 15 -#define D18F2x09C_x0D0F_0502_ValidTxAndPre_WIDTH 1 -#define D18F2x09C_x0D0F_0502_ValidTxAndPre_MASK 0x8000 -#define D18F2x09C_x0D0F_0502_Reserved_31_16_OFFSET 16 -#define D18F2x09C_x0D0F_0502_Reserved_31_16_WIDTH 16 -#define D18F2x09C_x0D0F_0502_Reserved_31_16_MASK 0xffff0000 - -/// D18F2x09C_x0D0F_0502 -typedef union { - struct { ///< - UINT32 TxPreN:6 ; ///< - UINT32 TxPreP:6 ; ///< - UINT32 Reserved_14_12:3 ; ///< - UINT32 ValidTxAndPre:1 ; ///< - UINT32 Reserved_31_16:16; ///< - } Field; ///< - UINT32 Value; ///< -} D18F2x09C_x0D0F_0502_STRUCT; - -// **** D18F2x09C_x0D0F_0506 Register Definition **** -// Address -#define D18F2x09C_x0D0F_0506_ADDRESS 0xd0f0506 - -// Type -#define D18F2x09C_x0D0F_0506_TYPE TYPE_D18F2x09C -// Field Data -#define D18F2x09C_x0D0F_0506_TxPreN_OFFSET 0 -#define D18F2x09C_x0D0F_0506_TxPreN_WIDTH 6 -#define D18F2x09C_x0D0F_0506_TxPreN_MASK 0x3f -#define D18F2x09C_x0D0F_0506_TxPreP_OFFSET 6 -#define D18F2x09C_x0D0F_0506_TxPreP_WIDTH 6 -#define D18F2x09C_x0D0F_0506_TxPreP_MASK 0xfc0 -#define D18F2x09C_x0D0F_0506_Reserved_31_12_OFFSET 12 -#define D18F2x09C_x0D0F_0506_Reserved_31_12_WIDTH 20 -#define D18F2x09C_x0D0F_0506_Reserved_31_12_MASK 0xfffff000 - -/// D18F2x09C_x0D0F_0506 -typedef union { - struct { ///< - UINT32 TxPreN:6 ; ///< - UINT32 TxPreP:6 ; ///< - UINT32 Reserved_31_12:20; ///< - } Field; ///< - UINT32 Value; ///< -} D18F2x09C_x0D0F_0506_STRUCT; - -// **** D18F2x09C_x0D0F_050A Register Definition **** -// Address -#define D18F2x09C_x0D0F_050A_ADDRESS 0xd0f050a - -// Type -#define D18F2x09C_x0D0F_050A_TYPE TYPE_D18F2x09C -// Field Data -#define D18F2x09C_x0D0F_050A_TxPreN_OFFSET 0 -#define D18F2x09C_x0D0F_050A_TxPreN_WIDTH 6 -#define D18F2x09C_x0D0F_050A_TxPreN_MASK 0x3f -#define D18F2x09C_x0D0F_050A_TxPreP_OFFSET 6 -#define D18F2x09C_x0D0F_050A_TxPreP_WIDTH 6 -#define D18F2x09C_x0D0F_050A_TxPreP_MASK 0xfc0 -#define D18F2x09C_x0D0F_050A_Reserved_31_12_OFFSET 12 -#define D18F2x09C_x0D0F_050A_Reserved_31_12_WIDTH 20 -#define D18F2x09C_x0D0F_050A_Reserved_31_12_MASK 0xfffff000 - -/// D18F2x09C_x0D0F_050A -typedef union { - struct { ///< - UINT32 TxPreN:6 ; ///< - UINT32 TxPreP:6 ; ///< - UINT32 Reserved_31_12:20; ///< - } Field; ///< - UINT32 Value; ///< -} D18F2x09C_x0D0F_050A_STRUCT; - -// **** D18F2x09C_x0D0F_050F Register Definition **** -// Address -#define D18F2x09C_x0D0F_050F_ADDRESS 0xd0f050f - -// Type -#define D18F2x09C_x0D0F_050F_TYPE TYPE_D18F2x09C -// Field Data -#define D18F2x09C_x0D0F_050F_Reserved_11_0_OFFSET 0 -#define D18F2x09C_x0D0F_050F_Reserved_11_0_WIDTH 12 -#define D18F2x09C_x0D0F_050F_Reserved_11_0_MASK 0xfff -#define D18F2x09C_x0D0F_050F_AlwaysEnDllClks_OFFSET 12 -#define D18F2x09C_x0D0F_050F_AlwaysEnDllClks_WIDTH 3 -#define D18F2x09C_x0D0F_050F_AlwaysEnDllClks_MASK 0x7000 -#define D18F2x09C_x0D0F_050F_Reserved_31_15_OFFSET 15 -#define D18F2x09C_x0D0F_050F_Reserved_31_15_WIDTH 17 -#define D18F2x09C_x0D0F_050F_Reserved_31_15_MASK 0xffff8000 - -/// D18F2x09C_x0D0F_050F -typedef union { - struct { ///< - UINT32 Reserved_11_0:12; ///< - UINT32 AlwaysEnDllClks:3 ; ///< - UINT32 Reserved_31_15:17; ///< - } Field; ///< - UINT32 Value; ///< -} D18F2x09C_x0D0F_050F_STRUCT; - -// **** D18F2x09C_x0D0F_0510 Register Definition **** -// Address -#define D18F2x09C_x0D0F_0510_ADDRESS 0xd0f0510 - -// Type -#define D18F2x09C_x0D0F_0510_TYPE TYPE_D18F2x09C -// Field Data -#define D18F2x09C_x0D0F_0510_Reserved_11_0_OFFSET 0 -#define D18F2x09C_x0D0F_0510_Reserved_11_0_WIDTH 12 -#define D18F2x09C_x0D0F_0510_Reserved_11_0_MASK 0xfff -#define D18F2x09C_x0D0F_0510_EnRxPadStandby_OFFSET 12 -#define D18F2x09C_x0D0F_0510_EnRxPadStandby_WIDTH 1 -#define D18F2x09C_x0D0F_0510_EnRxPadStandby_MASK 0x1000 -#define D18F2x09C_x0D0F_0510_Reserved_31_13_OFFSET 13 -#define D18F2x09C_x0D0F_0510_Reserved_31_13_WIDTH 19 -#define D18F2x09C_x0D0F_0510_Reserved_31_13_MASK 0xffffe000 - -/// D18F2x09C_x0D0F_0510 -typedef union { - struct { ///< - UINT32 Reserved_11_0:12; ///< - UINT32 EnRxPadStandby:1 ; ///< - UINT32 Reserved_31_13:19; ///< - } Field; ///< - UINT32 Value; ///< -} D18F2x09C_x0D0F_0510_STRUCT; - -// **** D18F2x09C_x0D0F_051F Register Definition **** -// Address -#define D18F2x09C_x0D0F_051F_ADDRESS 0xd0f051f - -// Type -#define D18F2x09C_x0D0F_051F_TYPE TYPE_D18F2x09C -// Field Data -#define D18F2x09C_x0D0F_051F_Reserved_2_0_OFFSET 0 -#define D18F2x09C_x0D0F_051F_Reserved_2_0_WIDTH 3 -#define D18F2x09C_x0D0F_051F_Reserved_2_0_MASK 0x7 -#define D18F2x09C_x0D0F_051F_RxVioLvl_OFFSET 3 -#define D18F2x09C_x0D0F_051F_RxVioLvl_WIDTH 2 -#define D18F2x09C_x0D0F_051F_RxVioLvl_MASK 0x18 -#define D18F2x09C_x0D0F_051F_Reserved_31_5_OFFSET 5 -#define D18F2x09C_x0D0F_051F_Reserved_31_5_WIDTH 27 -#define D18F2x09C_x0D0F_051F_Reserved_31_5_MASK 0xffffffe0 - -/// D18F2x09C_x0D0F_051F -typedef union { - struct { ///< - UINT32 Reserved_2_0:3 ; ///< - UINT32 RxVioLvl:2 ; ///< - UINT32 Reserved_31_5:27; ///< - } Field; ///< - UINT32 Value; ///< -} D18F2x09C_x0D0F_051F_STRUCT; - -// **** D18F2x09C_x0D0F_0530 Register Definition **** -// Address -#define D18F2x09C_x0D0F_0530_ADDRESS 0xd0f0530 - -// Type -#define D18F2x09C_x0D0F_0530_TYPE TYPE_D18F2x09C -// Field Data -#define D18F2x09C_x0D0F_0530_Reserved_4_0_OFFSET 0 -#define D18F2x09C_x0D0F_0530_Reserved_4_0_WIDTH 5 -#define D18F2x09C_x0D0F_0530_Reserved_4_0_MASK 0x1f -#define D18F2x09C_x0D0F_0530_PchgPdTxCClkGateDis_OFFSET 5 -#define D18F2x09C_x0D0F_0530_PchgPdTxCClkGateDis_WIDTH 1 -#define D18F2x09C_x0D0F_0530_PchgPdTxCClkGateDis_MASK 0x20 -#define D18F2x09C_x0D0F_0530_Reserved_31_6_OFFSET 6 -#define D18F2x09C_x0D0F_0530_Reserved_31_6_WIDTH 26 -#define D18F2x09C_x0D0F_0530_Reserved_31_6_MASK 0xffffffc0 - -/// D18F2x09C_x0D0F_0530 -typedef union { - struct { ///< - UINT32 Reserved_4_0:5 ; ///< - UINT32 PchgPdTxCClkGateDis:1 ; ///< - UINT32 Reserved_31_6:26; ///< - } Field; ///< - UINT32 Value; ///< -} D18F2x09C_x0D0F_0530_STRUCT; - -// **** D18F2x09C_x0D0F_0531 Register Definition **** -// Address -#define D18F2x09C_x0D0F_0531_ADDRESS 0xd0f0531 - -// Type -#define D18F2x09C_x0D0F_0531_TYPE TYPE_D18F2x09C -// Field Data -#define D18F2x09C_x0D0F_0531_Fence2ThresholdTxPad_OFFSET 0 -#define D18F2x09C_x0D0F_0531_Fence2ThresholdTxPad_WIDTH 4 -#define D18F2x09C_x0D0F_0531_Fence2ThresholdTxPad_MASK 0xf -#define D18F2x09C_x0D0F_0531_Fence2EnableTxPad_OFFSET 4 -#define D18F2x09C_x0D0F_0531_Fence2EnableTxPad_WIDTH 1 -#define D18F2x09C_x0D0F_0531_Fence2EnableTxPad_MASK 0x10 -#define D18F2x09C_x0D0F_0531_Fence2ThresholdTxDll_OFFSET 5 -#define D18F2x09C_x0D0F_0531_Fence2ThresholdTxDll_WIDTH 4 -#define D18F2x09C_x0D0F_0531_Fence2ThresholdTxDll_MASK 0x1e0 -#define D18F2x09C_x0D0F_0531_Fence2EnableTxDll_OFFSET 9 -#define D18F2x09C_x0D0F_0531_Fence2EnableTxDll_WIDTH 1 -#define D18F2x09C_x0D0F_0531_Fence2EnableTxDll_MASK 0x200 -#define D18F2x09C_x0D0F_0531_Fence2ThresholdRxDll_OFFSET 10 -#define D18F2x09C_x0D0F_0531_Fence2ThresholdRxDll_WIDTH 4 -#define D18F2x09C_x0D0F_0531_Fence2ThresholdRxDll_MASK 0x3c00 -#define D18F2x09C_x0D0F_0531_Fence2EnableRxDll_OFFSET 14 -#define D18F2x09C_x0D0F_0531_Fence2EnableRxDll_WIDTH 1 -#define D18F2x09C_x0D0F_0531_Fence2EnableRxDll_MASK 0x4000 -#define D18F2x09C_x0D0F_0531_Reserved_31_15_OFFSET 15 -#define D18F2x09C_x0D0F_0531_Reserved_31_15_WIDTH 17 -#define D18F2x09C_x0D0F_0531_Reserved_31_15_MASK 0xffff8000 - -/// D18F2x09C_x0D0F_0531 -typedef union { - struct { ///< - UINT32 Fence2ThresholdTxPad:4 ; ///< - UINT32 Fence2EnableTxPad:1 ; ///< - UINT32 Fence2ThresholdTxDll:4 ; ///< - UINT32 Fence2EnableTxDll:1 ; ///< - UINT32 Fence2ThresholdRxDll:4 ; ///< - UINT32 Fence2EnableRxDll:1 ; ///< - UINT32 Reserved_31_15:17; ///< - } Field; ///< - UINT32 Value; ///< -} D18F2x09C_x0D0F_0531_STRUCT; - -// **** D18F2x09C_x0D0F_0602 Register Definition **** -// Address -#define D18F2x09C_x0D0F_0602_ADDRESS 0xd0f0602 - -// Type -#define D18F2x09C_x0D0F_0602_TYPE TYPE_D18F2x09C -// Field Data -#define D18F2x09C_x0D0F_0602_TxPreN_OFFSET 0 -#define D18F2x09C_x0D0F_0602_TxPreN_WIDTH 6 -#define D18F2x09C_x0D0F_0602_TxPreN_MASK 0x3f -#define D18F2x09C_x0D0F_0602_TxPreP_OFFSET 6 -#define D18F2x09C_x0D0F_0602_TxPreP_WIDTH 6 -#define D18F2x09C_x0D0F_0602_TxPreP_MASK 0xfc0 -#define D18F2x09C_x0D0F_0602_Reserved_14_12_OFFSET 12 -#define D18F2x09C_x0D0F_0602_Reserved_14_12_WIDTH 3 -#define D18F2x09C_x0D0F_0602_Reserved_14_12_MASK 0x7000 -#define D18F2x09C_x0D0F_0602_ValidTxAndPre_OFFSET 15 -#define D18F2x09C_x0D0F_0602_ValidTxAndPre_WIDTH 1 -#define D18F2x09C_x0D0F_0602_ValidTxAndPre_MASK 0x8000 -#define D18F2x09C_x0D0F_0602_Reserved_31_16_OFFSET 16 -#define D18F2x09C_x0D0F_0602_Reserved_31_16_WIDTH 16 -#define D18F2x09C_x0D0F_0602_Reserved_31_16_MASK 0xffff0000 - -/// D18F2x09C_x0D0F_0602 -typedef union { - struct { ///< - UINT32 TxPreN:6 ; ///< - UINT32 TxPreP:6 ; ///< - UINT32 Reserved_14_12:3 ; ///< - UINT32 ValidTxAndPre:1 ; ///< - UINT32 Reserved_31_16:16; ///< - } Field; ///< - UINT32 Value; ///< -} D18F2x09C_x0D0F_0602_STRUCT; - -// **** D18F2x09C_x0D0F_0606 Register Definition **** -// Address -#define D18F2x09C_x0D0F_0606_ADDRESS 0xd0f0606 - -// Type -#define D18F2x09C_x0D0F_0606_TYPE TYPE_D18F2x09C -// Field Data -#define D18F2x09C_x0D0F_0606_TxPreN_OFFSET 0 -#define D18F2x09C_x0D0F_0606_TxPreN_WIDTH 6 -#define D18F2x09C_x0D0F_0606_TxPreN_MASK 0x3f -#define D18F2x09C_x0D0F_0606_TxPreP_OFFSET 6 -#define D18F2x09C_x0D0F_0606_TxPreP_WIDTH 6 -#define D18F2x09C_x0D0F_0606_TxPreP_MASK 0xfc0 -#define D18F2x09C_x0D0F_0606_Reserved_31_12_OFFSET 12 -#define D18F2x09C_x0D0F_0606_Reserved_31_12_WIDTH 20 -#define D18F2x09C_x0D0F_0606_Reserved_31_12_MASK 0xfffff000 - -/// D18F2x09C_x0D0F_0606 -typedef union { - struct { ///< - UINT32 TxPreN:6 ; ///< - UINT32 TxPreP:6 ; ///< - UINT32 Reserved_31_12:20; ///< - } Field; ///< - UINT32 Value; ///< -} D18F2x09C_x0D0F_0606_STRUCT; - -// **** D18F2x09C_x0D0F_060A Register Definition **** -// Address -#define D18F2x09C_x0D0F_060A_ADDRESS 0xd0f060a - -// Type -#define D18F2x09C_x0D0F_060A_TYPE TYPE_D18F2x09C -// Field Data -#define D18F2x09C_x0D0F_060A_TxPreN_OFFSET 0 -#define D18F2x09C_x0D0F_060A_TxPreN_WIDTH 6 -#define D18F2x09C_x0D0F_060A_TxPreN_MASK 0x3f -#define D18F2x09C_x0D0F_060A_TxPreP_OFFSET 6 -#define D18F2x09C_x0D0F_060A_TxPreP_WIDTH 6 -#define D18F2x09C_x0D0F_060A_TxPreP_MASK 0xfc0 -#define D18F2x09C_x0D0F_060A_Reserved_31_12_OFFSET 12 -#define D18F2x09C_x0D0F_060A_Reserved_31_12_WIDTH 20 -#define D18F2x09C_x0D0F_060A_Reserved_31_12_MASK 0xfffff000 - -/// D18F2x09C_x0D0F_060A -typedef union { - struct { ///< - UINT32 TxPreN:6 ; ///< - UINT32 TxPreP:6 ; ///< - UINT32 Reserved_31_12:20; ///< - } Field; ///< - UINT32 Value; ///< -} D18F2x09C_x0D0F_060A_STRUCT; - -// **** D18F2x09C_x0D0F_060F Register Definition **** -// Address -#define D18F2x09C_x0D0F_060F_ADDRESS 0xd0f060f - -// Type -#define D18F2x09C_x0D0F_060F_TYPE TYPE_D18F2x09C -// Field Data -#define D18F2x09C_x0D0F_060F_Reserved_11_0_OFFSET 0 -#define D18F2x09C_x0D0F_060F_Reserved_11_0_WIDTH 12 -#define D18F2x09C_x0D0F_060F_Reserved_11_0_MASK 0xfff -#define D18F2x09C_x0D0F_060F_AlwaysEnDllClks_OFFSET 12 -#define D18F2x09C_x0D0F_060F_AlwaysEnDllClks_WIDTH 3 -#define D18F2x09C_x0D0F_060F_AlwaysEnDllClks_MASK 0x7000 -#define D18F2x09C_x0D0F_060F_Reserved_31_15_OFFSET 15 -#define D18F2x09C_x0D0F_060F_Reserved_31_15_WIDTH 17 -#define D18F2x09C_x0D0F_060F_Reserved_31_15_MASK 0xffff8000 - -/// D18F2x09C_x0D0F_060F -typedef union { - struct { ///< - UINT32 Reserved_11_0:12; ///< - UINT32 AlwaysEnDllClks:3 ; ///< - UINT32 Reserved_31_15:17; ///< - } Field; ///< - UINT32 Value; ///< -} D18F2x09C_x0D0F_060F_STRUCT; - -// **** D18F2x09C_x0D0F_0610 Register Definition **** -// Address -#define D18F2x09C_x0D0F_0610_ADDRESS 0xd0f0610 - -// Type -#define D18F2x09C_x0D0F_0610_TYPE TYPE_D18F2x09C -// Field Data -#define D18F2x09C_x0D0F_0610_Reserved_11_0_OFFSET 0 -#define D18F2x09C_x0D0F_0610_Reserved_11_0_WIDTH 12 -#define D18F2x09C_x0D0F_0610_Reserved_11_0_MASK 0xfff -#define D18F2x09C_x0D0F_0610_EnRxPadStandby_OFFSET 12 -#define D18F2x09C_x0D0F_0610_EnRxPadStandby_WIDTH 1 -#define D18F2x09C_x0D0F_0610_EnRxPadStandby_MASK 0x1000 -#define D18F2x09C_x0D0F_0610_Reserved_31_13_OFFSET 13 -#define D18F2x09C_x0D0F_0610_Reserved_31_13_WIDTH 19 -#define D18F2x09C_x0D0F_0610_Reserved_31_13_MASK 0xffffe000 - -/// D18F2x09C_x0D0F_0610 -typedef union { - struct { ///< - UINT32 Reserved_11_0:12; ///< - UINT32 EnRxPadStandby:1 ; ///< - UINT32 Reserved_31_13:19; ///< - } Field; ///< - UINT32 Value; ///< -} D18F2x09C_x0D0F_0610_STRUCT; - -// **** D18F2x09C_x0D0F_061F Register Definition **** -// Address -#define D18F2x09C_x0D0F_061F_ADDRESS 0xd0f061f - -// Type -#define D18F2x09C_x0D0F_061F_TYPE TYPE_D18F2x09C -// Field Data -#define D18F2x09C_x0D0F_061F_Reserved_2_0_OFFSET 0 -#define D18F2x09C_x0D0F_061F_Reserved_2_0_WIDTH 3 -#define D18F2x09C_x0D0F_061F_Reserved_2_0_MASK 0x7 -#define D18F2x09C_x0D0F_061F_RxVioLvl_OFFSET 3 -#define D18F2x09C_x0D0F_061F_RxVioLvl_WIDTH 2 -#define D18F2x09C_x0D0F_061F_RxVioLvl_MASK 0x18 -#define D18F2x09C_x0D0F_061F_Reserved_31_5_OFFSET 5 -#define D18F2x09C_x0D0F_061F_Reserved_31_5_WIDTH 27 -#define D18F2x09C_x0D0F_061F_Reserved_31_5_MASK 0xffffffe0 - -/// D18F2x09C_x0D0F_061F -typedef union { - struct { ///< - UINT32 Reserved_2_0:3 ; ///< - UINT32 RxVioLvl:2 ; ///< - UINT32 Reserved_31_5:27; ///< - } Field; ///< - UINT32 Value; ///< -} D18F2x09C_x0D0F_061F_STRUCT; - -// **** D18F2x09C_x0D0F_0630 Register Definition **** -// Address -#define D18F2x09C_x0D0F_0630_ADDRESS 0xd0f0630 - -// Type -#define D18F2x09C_x0D0F_0630_TYPE TYPE_D18F2x09C -// Field Data -#define D18F2x09C_x0D0F_0630_Reserved_4_0_OFFSET 0 -#define D18F2x09C_x0D0F_0630_Reserved_4_0_WIDTH 5 -#define D18F2x09C_x0D0F_0630_Reserved_4_0_MASK 0x1f -#define D18F2x09C_x0D0F_0630_PchgPdTxCClkGateDis_OFFSET 5 -#define D18F2x09C_x0D0F_0630_PchgPdTxCClkGateDis_WIDTH 1 -#define D18F2x09C_x0D0F_0630_PchgPdTxCClkGateDis_MASK 0x20 -#define D18F2x09C_x0D0F_0630_Reserved_31_6_OFFSET 6 -#define D18F2x09C_x0D0F_0630_Reserved_31_6_WIDTH 26 -#define D18F2x09C_x0D0F_0630_Reserved_31_6_MASK 0xffffffc0 - -/// D18F2x09C_x0D0F_0630 -typedef union { - struct { ///< - UINT32 Reserved_4_0:5 ; ///< - UINT32 PchgPdTxCClkGateDis:1 ; ///< - UINT32 Reserved_31_6:26; ///< - } Field; ///< - UINT32 Value; ///< -} D18F2x09C_x0D0F_0630_STRUCT; - -// **** D18F2x09C_x0D0F_0631 Register Definition **** -// Address -#define D18F2x09C_x0D0F_0631_ADDRESS 0xd0f0631 - -// Type -#define D18F2x09C_x0D0F_0631_TYPE TYPE_D18F2x09C -// Field Data -#define D18F2x09C_x0D0F_0631_Fence2ThresholdTxPad_OFFSET 0 -#define D18F2x09C_x0D0F_0631_Fence2ThresholdTxPad_WIDTH 4 -#define D18F2x09C_x0D0F_0631_Fence2ThresholdTxPad_MASK 0xf -#define D18F2x09C_x0D0F_0631_Fence2EnableTxPad_OFFSET 4 -#define D18F2x09C_x0D0F_0631_Fence2EnableTxPad_WIDTH 1 -#define D18F2x09C_x0D0F_0631_Fence2EnableTxPad_MASK 0x10 -#define D18F2x09C_x0D0F_0631_Fence2ThresholdTxDll_OFFSET 5 -#define D18F2x09C_x0D0F_0631_Fence2ThresholdTxDll_WIDTH 4 -#define D18F2x09C_x0D0F_0631_Fence2ThresholdTxDll_MASK 0x1e0 -#define D18F2x09C_x0D0F_0631_Fence2EnableTxDll_OFFSET 9 -#define D18F2x09C_x0D0F_0631_Fence2EnableTxDll_WIDTH 1 -#define D18F2x09C_x0D0F_0631_Fence2EnableTxDll_MASK 0x200 -#define D18F2x09C_x0D0F_0631_Fence2ThresholdRxDll_OFFSET 10 -#define D18F2x09C_x0D0F_0631_Fence2ThresholdRxDll_WIDTH 4 -#define D18F2x09C_x0D0F_0631_Fence2ThresholdRxDll_MASK 0x3c00 -#define D18F2x09C_x0D0F_0631_Fence2EnableRxDll_OFFSET 14 -#define D18F2x09C_x0D0F_0631_Fence2EnableRxDll_WIDTH 1 -#define D18F2x09C_x0D0F_0631_Fence2EnableRxDll_MASK 0x4000 -#define D18F2x09C_x0D0F_0631_Reserved_31_15_OFFSET 15 -#define D18F2x09C_x0D0F_0631_Reserved_31_15_WIDTH 17 -#define D18F2x09C_x0D0F_0631_Reserved_31_15_MASK 0xffff8000 - -/// D18F2x09C_x0D0F_0631 -typedef union { - struct { ///< - UINT32 Fence2ThresholdTxPad:4 ; ///< - UINT32 Fence2EnableTxPad:1 ; ///< - UINT32 Fence2ThresholdTxDll:4 ; ///< - UINT32 Fence2EnableTxDll:1 ; ///< - UINT32 Fence2ThresholdRxDll:4 ; ///< - UINT32 Fence2EnableRxDll:1 ; ///< - UINT32 Reserved_31_15:17; ///< - } Field; ///< - UINT32 Value; ///< -} D18F2x09C_x0D0F_0631_STRUCT; - -// **** D18F2x09C_x0D0F_0702 Register Definition **** -// Address -#define D18F2x09C_x0D0F_0702_ADDRESS 0xd0f0702 - -// Type -#define D18F2x09C_x0D0F_0702_TYPE TYPE_D18F2x09C -// Field Data -#define D18F2x09C_x0D0F_0702_TxPreN_OFFSET 0 -#define D18F2x09C_x0D0F_0702_TxPreN_WIDTH 6 -#define D18F2x09C_x0D0F_0702_TxPreN_MASK 0x3f -#define D18F2x09C_x0D0F_0702_TxPreP_OFFSET 6 -#define D18F2x09C_x0D0F_0702_TxPreP_WIDTH 6 -#define D18F2x09C_x0D0F_0702_TxPreP_MASK 0xfc0 -#define D18F2x09C_x0D0F_0702_Reserved_14_12_OFFSET 12 -#define D18F2x09C_x0D0F_0702_Reserved_14_12_WIDTH 3 -#define D18F2x09C_x0D0F_0702_Reserved_14_12_MASK 0x7000 -#define D18F2x09C_x0D0F_0702_ValidTxAndPre_OFFSET 15 -#define D18F2x09C_x0D0F_0702_ValidTxAndPre_WIDTH 1 -#define D18F2x09C_x0D0F_0702_ValidTxAndPre_MASK 0x8000 -#define D18F2x09C_x0D0F_0702_Reserved_31_16_OFFSET 16 -#define D18F2x09C_x0D0F_0702_Reserved_31_16_WIDTH 16 -#define D18F2x09C_x0D0F_0702_Reserved_31_16_MASK 0xffff0000 - -/// D18F2x09C_x0D0F_0702 -typedef union { - struct { ///< - UINT32 TxPreN:6 ; ///< - UINT32 TxPreP:6 ; ///< - UINT32 Reserved_14_12:3 ; ///< - UINT32 ValidTxAndPre:1 ; ///< - UINT32 Reserved_31_16:16; ///< - } Field; ///< - UINT32 Value; ///< -} D18F2x09C_x0D0F_0702_STRUCT; - -// **** D18F2x09C_x0D0F_0706 Register Definition **** -// Address -#define D18F2x09C_x0D0F_0706_ADDRESS 0xd0f0706 - -// Type -#define D18F2x09C_x0D0F_0706_TYPE TYPE_D18F2x09C -// Field Data -#define D18F2x09C_x0D0F_0706_TxPreN_OFFSET 0 -#define D18F2x09C_x0D0F_0706_TxPreN_WIDTH 6 -#define D18F2x09C_x0D0F_0706_TxPreN_MASK 0x3f -#define D18F2x09C_x0D0F_0706_TxPreP_OFFSET 6 -#define D18F2x09C_x0D0F_0706_TxPreP_WIDTH 6 -#define D18F2x09C_x0D0F_0706_TxPreP_MASK 0xfc0 -#define D18F2x09C_x0D0F_0706_Reserved_31_12_OFFSET 12 -#define D18F2x09C_x0D0F_0706_Reserved_31_12_WIDTH 20 -#define D18F2x09C_x0D0F_0706_Reserved_31_12_MASK 0xfffff000 - -/// D18F2x09C_x0D0F_0706 -typedef union { - struct { ///< - UINT32 TxPreN:6 ; ///< - UINT32 TxPreP:6 ; ///< - UINT32 Reserved_31_12:20; ///< - } Field; ///< - UINT32 Value; ///< -} D18F2x09C_x0D0F_0706_STRUCT; - -// **** D18F2x09C_x0D0F_070A Register Definition **** -// Address -#define D18F2x09C_x0D0F_070A_ADDRESS 0xd0f070a - -// Type -#define D18F2x09C_x0D0F_070A_TYPE TYPE_D18F2x09C -// Field Data -#define D18F2x09C_x0D0F_070A_TxPreN_OFFSET 0 -#define D18F2x09C_x0D0F_070A_TxPreN_WIDTH 6 -#define D18F2x09C_x0D0F_070A_TxPreN_MASK 0x3f -#define D18F2x09C_x0D0F_070A_TxPreP_OFFSET 6 -#define D18F2x09C_x0D0F_070A_TxPreP_WIDTH 6 -#define D18F2x09C_x0D0F_070A_TxPreP_MASK 0xfc0 -#define D18F2x09C_x0D0F_070A_Reserved_31_12_OFFSET 12 -#define D18F2x09C_x0D0F_070A_Reserved_31_12_WIDTH 20 -#define D18F2x09C_x0D0F_070A_Reserved_31_12_MASK 0xfffff000 - -/// D18F2x09C_x0D0F_070A -typedef union { - struct { ///< - UINT32 TxPreN:6 ; ///< - UINT32 TxPreP:6 ; ///< - UINT32 Reserved_31_12:20; ///< - } Field; ///< - UINT32 Value; ///< -} D18F2x09C_x0D0F_070A_STRUCT; - -// **** D18F2x09C_x0D0F_070F Register Definition **** -// Address -#define D18F2x09C_x0D0F_070F_ADDRESS 0xd0f070f - -// Type -#define D18F2x09C_x0D0F_070F_TYPE TYPE_D18F2x09C -// Field Data -#define D18F2x09C_x0D0F_070F_Reserved_11_0_OFFSET 0 -#define D18F2x09C_x0D0F_070F_Reserved_11_0_WIDTH 12 -#define D18F2x09C_x0D0F_070F_Reserved_11_0_MASK 0xfff -#define D18F2x09C_x0D0F_070F_AlwaysEnDllClks_OFFSET 12 -#define D18F2x09C_x0D0F_070F_AlwaysEnDllClks_WIDTH 3 -#define D18F2x09C_x0D0F_070F_AlwaysEnDllClks_MASK 0x7000 -#define D18F2x09C_x0D0F_070F_Reserved_31_15_OFFSET 15 -#define D18F2x09C_x0D0F_070F_Reserved_31_15_WIDTH 17 -#define D18F2x09C_x0D0F_070F_Reserved_31_15_MASK 0xffff8000 - -/// D18F2x09C_x0D0F_070F -typedef union { - struct { ///< - UINT32 Reserved_11_0:12; ///< - UINT32 AlwaysEnDllClks:3 ; ///< - UINT32 Reserved_31_15:17; ///< - } Field; ///< - UINT32 Value; ///< -} D18F2x09C_x0D0F_070F_STRUCT; - -// **** D18F2x09C_x0D0F_0710 Register Definition **** -// Address -#define D18F2x09C_x0D0F_0710_ADDRESS 0xd0f0710 - -// Type -#define D18F2x09C_x0D0F_0710_TYPE TYPE_D18F2x09C -// Field Data -#define D18F2x09C_x0D0F_0710_Reserved_11_0_OFFSET 0 -#define D18F2x09C_x0D0F_0710_Reserved_11_0_WIDTH 12 -#define D18F2x09C_x0D0F_0710_Reserved_11_0_MASK 0xfff -#define D18F2x09C_x0D0F_0710_EnRxPadStandby_OFFSET 12 -#define D18F2x09C_x0D0F_0710_EnRxPadStandby_WIDTH 1 -#define D18F2x09C_x0D0F_0710_EnRxPadStandby_MASK 0x1000 -#define D18F2x09C_x0D0F_0710_Reserved_31_13_OFFSET 13 -#define D18F2x09C_x0D0F_0710_Reserved_31_13_WIDTH 19 -#define D18F2x09C_x0D0F_0710_Reserved_31_13_MASK 0xffffe000 - -/// D18F2x09C_x0D0F_0710 -typedef union { - struct { ///< - UINT32 Reserved_11_0:12; ///< - UINT32 EnRxPadStandby:1 ; ///< - UINT32 Reserved_31_13:19; ///< - } Field; ///< - UINT32 Value; ///< -} D18F2x09C_x0D0F_0710_STRUCT; - -// **** D18F2x09C_x0D0F_071F Register Definition **** -// Address -#define D18F2x09C_x0D0F_071F_ADDRESS 0xd0f071f - -// Type -#define D18F2x09C_x0D0F_071F_TYPE TYPE_D18F2x09C -// Field Data -#define D18F2x09C_x0D0F_071F_Reserved_2_0_OFFSET 0 -#define D18F2x09C_x0D0F_071F_Reserved_2_0_WIDTH 3 -#define D18F2x09C_x0D0F_071F_Reserved_2_0_MASK 0x7 -#define D18F2x09C_x0D0F_071F_RxVioLvl_OFFSET 3 -#define D18F2x09C_x0D0F_071F_RxVioLvl_WIDTH 2 -#define D18F2x09C_x0D0F_071F_RxVioLvl_MASK 0x18 -#define D18F2x09C_x0D0F_071F_Reserved_31_5_OFFSET 5 -#define D18F2x09C_x0D0F_071F_Reserved_31_5_WIDTH 27 -#define D18F2x09C_x0D0F_071F_Reserved_31_5_MASK 0xffffffe0 - -/// D18F2x09C_x0D0F_071F -typedef union { - struct { ///< - UINT32 Reserved_2_0:3 ; ///< - UINT32 RxVioLvl:2 ; ///< - UINT32 Reserved_31_5:27; ///< - } Field; ///< - UINT32 Value; ///< -} D18F2x09C_x0D0F_071F_STRUCT; - -// **** D18F2x09C_x0D0F_0730 Register Definition **** -// Address -#define D18F2x09C_x0D0F_0730_ADDRESS 0xd0f0730 - -// Type -#define D18F2x09C_x0D0F_0730_TYPE TYPE_D18F2x09C -// Field Data -#define D18F2x09C_x0D0F_0730_Reserved_4_0_OFFSET 0 -#define D18F2x09C_x0D0F_0730_Reserved_4_0_WIDTH 5 -#define D18F2x09C_x0D0F_0730_Reserved_4_0_MASK 0x1f -#define D18F2x09C_x0D0F_0730_PchgPdTxCClkGateDis_OFFSET 5 -#define D18F2x09C_x0D0F_0730_PchgPdTxCClkGateDis_WIDTH 1 -#define D18F2x09C_x0D0F_0730_PchgPdTxCClkGateDis_MASK 0x20 -#define D18F2x09C_x0D0F_0730_Reserved_31_6_OFFSET 6 -#define D18F2x09C_x0D0F_0730_Reserved_31_6_WIDTH 26 -#define D18F2x09C_x0D0F_0730_Reserved_31_6_MASK 0xffffffc0 - -/// D18F2x09C_x0D0F_0730 -typedef union { - struct { ///< - UINT32 Reserved_4_0:5 ; ///< - UINT32 PchgPdTxCClkGateDis:1 ; ///< - UINT32 Reserved_31_6:26; ///< - } Field; ///< - UINT32 Value; ///< -} D18F2x09C_x0D0F_0730_STRUCT; - -// **** D18F2x09C_x0D0F_0731 Register Definition **** -// Address -#define D18F2x09C_x0D0F_0731_ADDRESS 0xd0f0731 - -// Type -#define D18F2x09C_x0D0F_0731_TYPE TYPE_D18F2x09C -// Field Data -#define D18F2x09C_x0D0F_0731_Fence2ThresholdTxPad_OFFSET 0 -#define D18F2x09C_x0D0F_0731_Fence2ThresholdTxPad_WIDTH 4 -#define D18F2x09C_x0D0F_0731_Fence2ThresholdTxPad_MASK 0xf -#define D18F2x09C_x0D0F_0731_Fence2EnableTxPad_OFFSET 4 -#define D18F2x09C_x0D0F_0731_Fence2EnableTxPad_WIDTH 1 -#define D18F2x09C_x0D0F_0731_Fence2EnableTxPad_MASK 0x10 -#define D18F2x09C_x0D0F_0731_Fence2ThresholdTxDll_OFFSET 5 -#define D18F2x09C_x0D0F_0731_Fence2ThresholdTxDll_WIDTH 4 -#define D18F2x09C_x0D0F_0731_Fence2ThresholdTxDll_MASK 0x1e0 -#define D18F2x09C_x0D0F_0731_Fence2EnableTxDll_OFFSET 9 -#define D18F2x09C_x0D0F_0731_Fence2EnableTxDll_WIDTH 1 -#define D18F2x09C_x0D0F_0731_Fence2EnableTxDll_MASK 0x200 -#define D18F2x09C_x0D0F_0731_Fence2ThresholdRxDll_OFFSET 10 -#define D18F2x09C_x0D0F_0731_Fence2ThresholdRxDll_WIDTH 4 -#define D18F2x09C_x0D0F_0731_Fence2ThresholdRxDll_MASK 0x3c00 -#define D18F2x09C_x0D0F_0731_Fence2EnableRxDll_OFFSET 14 -#define D18F2x09C_x0D0F_0731_Fence2EnableRxDll_WIDTH 1 -#define D18F2x09C_x0D0F_0731_Fence2EnableRxDll_MASK 0x4000 -#define D18F2x09C_x0D0F_0731_Reserved_31_15_OFFSET 15 -#define D18F2x09C_x0D0F_0731_Reserved_31_15_WIDTH 17 -#define D18F2x09C_x0D0F_0731_Reserved_31_15_MASK 0xffff8000 - -/// D18F2x09C_x0D0F_0731 -typedef union { - struct { ///< - UINT32 Fence2ThresholdTxPad:4 ; ///< - UINT32 Fence2EnableTxPad:1 ; ///< - UINT32 Fence2ThresholdTxDll:4 ; ///< - UINT32 Fence2EnableTxDll:1 ; ///< - UINT32 Fence2ThresholdRxDll:4 ; ///< - UINT32 Fence2EnableRxDll:1 ; ///< - UINT32 Reserved_31_15:17; ///< - } Field; ///< - UINT32 Value; ///< -} D18F2x09C_x0D0F_0731_STRUCT; - -// **** D18F2x09C_x0D0F_0F02 Register Definition **** -// Address -#define D18F2x09C_x0D0F_0F02_ADDRESS 0xd0f0f02 - -// Type -#define D18F2x09C_x0D0F_0F02_TYPE TYPE_D18F2x09C -// Field Data -#define D18F2x09C_x0D0F_0F02_TxPreN_OFFSET 0 -#define D18F2x09C_x0D0F_0F02_TxPreN_WIDTH 6 -#define D18F2x09C_x0D0F_0F02_TxPreN_MASK 0x3f -#define D18F2x09C_x0D0F_0F02_TxPreP_OFFSET 6 -#define D18F2x09C_x0D0F_0F02_TxPreP_WIDTH 6 -#define D18F2x09C_x0D0F_0F02_TxPreP_MASK 0xfc0 -#define D18F2x09C_x0D0F_0F02_Reserved_14_12_OFFSET 12 -#define D18F2x09C_x0D0F_0F02_Reserved_14_12_WIDTH 3 -#define D18F2x09C_x0D0F_0F02_Reserved_14_12_MASK 0x7000 -#define D18F2x09C_x0D0F_0F02_ValidTxAndPre_OFFSET 15 -#define D18F2x09C_x0D0F_0F02_ValidTxAndPre_WIDTH 1 -#define D18F2x09C_x0D0F_0F02_ValidTxAndPre_MASK 0x8000 -#define D18F2x09C_x0D0F_0F02_Reserved_31_16_OFFSET 16 -#define D18F2x09C_x0D0F_0F02_Reserved_31_16_WIDTH 16 -#define D18F2x09C_x0D0F_0F02_Reserved_31_16_MASK 0xffff0000 - -/// D18F2x09C_x0D0F_0F02 -typedef union { - struct { ///< - UINT32 TxPreN:6 ; ///< - UINT32 TxPreP:6 ; ///< - UINT32 Reserved_14_12:3 ; ///< - UINT32 ValidTxAndPre:1 ; ///< - UINT32 Reserved_31_16:16; ///< - } Field; ///< - UINT32 Value; ///< -} D18F2x09C_x0D0F_0F02_STRUCT; - -// **** D18F2x09C_x0D0F_0F06 Register Definition **** -// Address -#define D18F2x09C_x0D0F_0F06_ADDRESS 0xd0f0f06 - -// Type -#define D18F2x09C_x0D0F_0F06_TYPE TYPE_D18F2x09C -// Field Data -#define D18F2x09C_x0D0F_0F06_TxPreN_OFFSET 0 -#define D18F2x09C_x0D0F_0F06_TxPreN_WIDTH 6 -#define D18F2x09C_x0D0F_0F06_TxPreN_MASK 0x3f -#define D18F2x09C_x0D0F_0F06_TxPreP_OFFSET 6 -#define D18F2x09C_x0D0F_0F06_TxPreP_WIDTH 6 -#define D18F2x09C_x0D0F_0F06_TxPreP_MASK 0xfc0 -#define D18F2x09C_x0D0F_0F06_Reserved_31_12_OFFSET 12 -#define D18F2x09C_x0D0F_0F06_Reserved_31_12_WIDTH 20 -#define D18F2x09C_x0D0F_0F06_Reserved_31_12_MASK 0xfffff000 - -/// D18F2x09C_x0D0F_0F06 -typedef union { - struct { ///< - UINT32 TxPreN:6 ; ///< - UINT32 TxPreP:6 ; ///< - UINT32 Reserved_31_12:20; ///< - } Field; ///< - UINT32 Value; ///< -} D18F2x09C_x0D0F_0F06_STRUCT; - -// **** D18F2x09C_x0D0F_0F0A Register Definition **** -// Address -#define D18F2x09C_x0D0F_0F0A_ADDRESS 0xd0f0f0a - -// Type -#define D18F2x09C_x0D0F_0F0A_TYPE TYPE_D18F2x09C -// Field Data -#define D18F2x09C_x0D0F_0F0A_TxPreN_OFFSET 0 -#define D18F2x09C_x0D0F_0F0A_TxPreN_WIDTH 6 -#define D18F2x09C_x0D0F_0F0A_TxPreN_MASK 0x3f -#define D18F2x09C_x0D0F_0F0A_TxPreP_OFFSET 6 -#define D18F2x09C_x0D0F_0F0A_TxPreP_WIDTH 6 -#define D18F2x09C_x0D0F_0F0A_TxPreP_MASK 0xfc0 -#define D18F2x09C_x0D0F_0F0A_Reserved_31_12_OFFSET 12 -#define D18F2x09C_x0D0F_0F0A_Reserved_31_12_WIDTH 20 -#define D18F2x09C_x0D0F_0F0A_Reserved_31_12_MASK 0xfffff000 - -/// D18F2x09C_x0D0F_0F0A -typedef union { - struct { ///< - UINT32 TxPreN:6 ; ///< - UINT32 TxPreP:6 ; ///< - UINT32 Reserved_31_12:20; ///< - } Field; ///< - UINT32 Value; ///< -} D18F2x09C_x0D0F_0F0A_STRUCT; - -// **** D18F2x09C_x0D0F_0F0F Register Definition **** -// Address -#define D18F2x09C_x0D0F_0F0F_ADDRESS 0xd0f0f0f - -// Type -#define D18F2x09C_x0D0F_0F0F_TYPE TYPE_D18F2x09C -// Field Data -#define D18F2x09C_x0D0F_0F0F_Reserved_11_0_OFFSET 0 -#define D18F2x09C_x0D0F_0F0F_Reserved_11_0_WIDTH 12 -#define D18F2x09C_x0D0F_0F0F_Reserved_11_0_MASK 0xfff -#define D18F2x09C_x0D0F_0F0F_AlwaysEnDllClks_OFFSET 12 -#define D18F2x09C_x0D0F_0F0F_AlwaysEnDllClks_WIDTH 3 -#define D18F2x09C_x0D0F_0F0F_AlwaysEnDllClks_MASK 0x7000 -#define D18F2x09C_x0D0F_0F0F_Reserved_31_15_OFFSET 15 -#define D18F2x09C_x0D0F_0F0F_Reserved_31_15_WIDTH 17 -#define D18F2x09C_x0D0F_0F0F_Reserved_31_15_MASK 0xffff8000 - -/// D18F2x09C_x0D0F_0F0F -typedef union { - struct { ///< - UINT32 Reserved_11_0:12; ///< - UINT32 AlwaysEnDllClks:3 ; ///< - UINT32 Reserved_31_15:17; ///< - } Field; ///< - UINT32 Value; ///< -} D18F2x09C_x0D0F_0F0F_STRUCT; - -// **** D18F2x09C_x0D0F_0F10 Register Definition **** -// Address -#define D18F2x09C_x0D0F_0F10_ADDRESS 0xd0f0f10 - -// Type -#define D18F2x09C_x0D0F_0F10_TYPE TYPE_D18F2x09C -// Field Data -#define D18F2x09C_x0D0F_0F10_Reserved_11_0_OFFSET 0 -#define D18F2x09C_x0D0F_0F10_Reserved_11_0_WIDTH 12 -#define D18F2x09C_x0D0F_0F10_Reserved_11_0_MASK 0xfff -#define D18F2x09C_x0D0F_0F10_EnRxPadStandby_OFFSET 12 -#define D18F2x09C_x0D0F_0F10_EnRxPadStandby_WIDTH 1 -#define D18F2x09C_x0D0F_0F10_EnRxPadStandby_MASK 0x1000 -#define D18F2x09C_x0D0F_0F10_Reserved_31_13_OFFSET 13 -#define D18F2x09C_x0D0F_0F10_Reserved_31_13_WIDTH 19 -#define D18F2x09C_x0D0F_0F10_Reserved_31_13_MASK 0xffffe000 - -/// D18F2x09C_x0D0F_0F10 -typedef union { - struct { ///< - UINT32 Reserved_11_0:12; ///< - UINT32 EnRxPadStandby:1 ; ///< - UINT32 Reserved_31_13:19; ///< - } Field; ///< - UINT32 Value; ///< -} D18F2x09C_x0D0F_0F10_STRUCT; - -// **** D18F2x09C_x0D0F_0F13 Register Definition **** -// Address -#define D18F2x09C_x0D0F_0F13_ADDRESS 0xd0f0f13 - -// Type -#define D18F2x09C_x0D0F_0F13_TYPE TYPE_D18F2x09C -// Field Data -#define D18F2x09C_x0D0F_0F13_DllDisEarlyL_OFFSET 0 -#define D18F2x09C_x0D0F_0F13_DllDisEarlyL_WIDTH 1 -#define D18F2x09C_x0D0F_0F13_DllDisEarlyL_MASK 0x1 -#define D18F2x09C_x0D0F_0F13_DllDisEarlyU_OFFSET 1 -#define D18F2x09C_x0D0F_0F13_DllDisEarlyU_WIDTH 1 -#define D18F2x09C_x0D0F_0F13_DllDisEarlyU_MASK 0x2 -#define D18F2x09C_x0D0F_0F13_Reserved_6_2_OFFSET 2 -#define D18F2x09C_x0D0F_0F13_Reserved_6_2_WIDTH 5 -#define D18F2x09C_x0D0F_0F13_Reserved_6_2_MASK 0x7c -#define D18F2x09C_x0D0F_0F13_RxDqsUDllPowerDown_OFFSET 7 -#define D18F2x09C_x0D0F_0F13_RxDqsUDllPowerDown_WIDTH 1 -#define D18F2x09C_x0D0F_0F13_RxDqsUDllPowerDown_MASK 0x80 -#define D18F2x09C_x0D0F_0F13_Reserved_13_8_OFFSET 8 -#define D18F2x09C_x0D0F_0F13_Reserved_13_8_WIDTH 6 -#define D18F2x09C_x0D0F_0F13_Reserved_13_8_MASK 0x3f00 -#define D18F2x09C_x0D0F_0F13_ProcOdtAdv_OFFSET 14 -#define D18F2x09C_x0D0F_0F13_ProcOdtAdv_WIDTH 1 -#define D18F2x09C_x0D0F_0F13_ProcOdtAdv_MASK 0x4000 -#define D18F2x09C_x0D0F_0F13_Reserved_31_15_OFFSET 15 -#define D18F2x09C_x0D0F_0F13_Reserved_31_15_WIDTH 17 -#define D18F2x09C_x0D0F_0F13_Reserved_31_15_MASK 0xffff8000 - -/// D18F2x09C_x0D0F_0F13 -typedef union { - struct { ///< - UINT32 DllDisEarlyL:1 ; ///< - UINT32 DllDisEarlyU:1 ; ///< - UINT32 Reserved_6_2:5 ; ///< - UINT32 RxDqsUDllPowerDown:1 ; ///< - UINT32 Reserved_13_8:6 ; ///< - UINT32 ProcOdtAdv:1 ; ///< - UINT32 Reserved_31_15:17; ///< - } Field; ///< - UINT32 Value; ///< -} D18F2x09C_x0D0F_0F13_STRUCT; - -// **** D18F2x09C_x0D0F_0F1F Register Definition **** -// Address -#define D18F2x09C_x0D0F_0F1F_ADDRESS 0xd0f0f1f - -// Type -#define D18F2x09C_x0D0F_0F1F_TYPE TYPE_D18F2x09C -// Field Data -#define D18F2x09C_x0D0F_0F1F_Reserved_2_0_OFFSET 0 -#define D18F2x09C_x0D0F_0F1F_Reserved_2_0_WIDTH 3 -#define D18F2x09C_x0D0F_0F1F_Reserved_2_0_MASK 0x7 -#define D18F2x09C_x0D0F_0F1F_RxVioLvl_OFFSET 3 -#define D18F2x09C_x0D0F_0F1F_RxVioLvl_WIDTH 2 -#define D18F2x09C_x0D0F_0F1F_RxVioLvl_MASK 0x18 -#define D18F2x09C_x0D0F_0F1F_Reserved_31_5_OFFSET 5 -#define D18F2x09C_x0D0F_0F1F_Reserved_31_5_WIDTH 27 -#define D18F2x09C_x0D0F_0F1F_Reserved_31_5_MASK 0xffffffe0 - -/// D18F2x09C_x0D0F_0F1F -typedef union { - struct { ///< - UINT32 Reserved_2_0:3 ; ///< - UINT32 RxVioLvl:2 ; ///< - UINT32 Reserved_31_5:27; ///< - } Field; ///< - UINT32 Value; ///< -} D18F2x09C_x0D0F_0F1F_STRUCT; - -// **** D18F2x09C_x0D0F_0F30 Register Definition **** -// Address -#define D18F2x09C_x0D0F_0F30_ADDRESS 0xd0f0f30 - -// Type -#define D18F2x09C_x0D0F_0F30_TYPE TYPE_D18F2x09C -// Field Data -#define D18F2x09C_x0D0F_0F30_Reserved_4_0_OFFSET 0 -#define D18F2x09C_x0D0F_0F30_Reserved_4_0_WIDTH 5 -#define D18F2x09C_x0D0F_0F30_Reserved_4_0_MASK 0x1f -#define D18F2x09C_x0D0F_0F30_PchgPdTxCClkGateDis_OFFSET 5 -#define D18F2x09C_x0D0F_0F30_PchgPdTxCClkGateDis_WIDTH 1 -#define D18F2x09C_x0D0F_0F30_PchgPdTxCClkGateDis_MASK 0x20 -#define D18F2x09C_x0D0F_0F30_Reserved_31_6_OFFSET 6 -#define D18F2x09C_x0D0F_0F30_Reserved_31_6_WIDTH 26 -#define D18F2x09C_x0D0F_0F30_Reserved_31_6_MASK 0xffffffc0 - -/// D18F2x09C_x0D0F_0F30 -typedef union { - struct { ///< - UINT32 Reserved_4_0:5 ; ///< - UINT32 PchgPdTxCClkGateDis:1 ; ///< - UINT32 Reserved_31_6:26; ///< - } Field; ///< - UINT32 Value; ///< -} D18F2x09C_x0D0F_0F30_STRUCT; - -// **** D18F2x09C_x0D0F_0F31 Register Definition **** -// Address -#define D18F2x09C_x0D0F_0F31_ADDRESS 0xd0f0f31 - -// Type -#define D18F2x09C_x0D0F_0F31_TYPE TYPE_D18F2x09C -// Field Data -#define D18F2x09C_x0D0F_0F31_Fence2ThresholdTxPad_OFFSET 0 -#define D18F2x09C_x0D0F_0F31_Fence2ThresholdTxPad_WIDTH 4 -#define D18F2x09C_x0D0F_0F31_Fence2ThresholdTxPad_MASK 0xf -#define D18F2x09C_x0D0F_0F31_Fence2EnableTxPad_OFFSET 4 -#define D18F2x09C_x0D0F_0F31_Fence2EnableTxPad_WIDTH 1 -#define D18F2x09C_x0D0F_0F31_Fence2EnableTxPad_MASK 0x10 -#define D18F2x09C_x0D0F_0F31_Fence2ThresholdTxDll_OFFSET 5 -#define D18F2x09C_x0D0F_0F31_Fence2ThresholdTxDll_WIDTH 4 -#define D18F2x09C_x0D0F_0F31_Fence2ThresholdTxDll_MASK 0x1e0 -#define D18F2x09C_x0D0F_0F31_Fence2EnableTxDll_OFFSET 9 -#define D18F2x09C_x0D0F_0F31_Fence2EnableTxDll_WIDTH 1 -#define D18F2x09C_x0D0F_0F31_Fence2EnableTxDll_MASK 0x200 -#define D18F2x09C_x0D0F_0F31_Fence2ThresholdRxDll_OFFSET 10 -#define D18F2x09C_x0D0F_0F31_Fence2ThresholdRxDll_WIDTH 4 -#define D18F2x09C_x0D0F_0F31_Fence2ThresholdRxDll_MASK 0x3c00 -#define D18F2x09C_x0D0F_0F31_Fence2EnableRxDll_OFFSET 14 -#define D18F2x09C_x0D0F_0F31_Fence2EnableRxDll_WIDTH 1 -#define D18F2x09C_x0D0F_0F31_Fence2EnableRxDll_MASK 0x4000 -#define D18F2x09C_x0D0F_0F31_Reserved_31_15_OFFSET 15 -#define D18F2x09C_x0D0F_0F31_Reserved_31_15_WIDTH 17 -#define D18F2x09C_x0D0F_0F31_Reserved_31_15_MASK 0xffff8000 - -/// D18F2x09C_x0D0F_0F31 -typedef union { - struct { ///< - UINT32 Fence2ThresholdTxPad:4 ; ///< - UINT32 Fence2EnableTxPad:1 ; ///< - UINT32 Fence2ThresholdTxDll:4 ; ///< - UINT32 Fence2EnableTxDll:1 ; ///< - UINT32 Fence2ThresholdRxDll:4 ; ///< - UINT32 Fence2EnableRxDll:1 ; ///< - UINT32 Reserved_31_15:17; ///< - } Field; ///< - UINT32 Value; ///< -} D18F2x09C_x0D0F_0F31_STRUCT; - -// **** D18F2x09C_x0D0F_2002 Register Definition **** -// Address -#define D18F2x09C_x0D0F_2002_ADDRESS 0xd0f2002 - -// Type -#define D18F2x09C_x0D0F_2002_TYPE TYPE_D18F2x09C -// Field Data -#define D18F2x09C_x0D0F_2002_TxPreN_OFFSET 0 -#define D18F2x09C_x0D0F_2002_TxPreN_WIDTH 6 -#define D18F2x09C_x0D0F_2002_TxPreN_MASK 0x3f -#define D18F2x09C_x0D0F_2002_TxPreP_OFFSET 6 -#define D18F2x09C_x0D0F_2002_TxPreP_WIDTH 6 -#define D18F2x09C_x0D0F_2002_TxPreP_MASK 0xfc0 -#define D18F2x09C_x0D0F_2002_Reserved_14_12_OFFSET 12 -#define D18F2x09C_x0D0F_2002_Reserved_14_12_WIDTH 3 -#define D18F2x09C_x0D0F_2002_Reserved_14_12_MASK 0x7000 -#define D18F2x09C_x0D0F_2002_ValidTxAndPre_OFFSET 15 -#define D18F2x09C_x0D0F_2002_ValidTxAndPre_WIDTH 1 -#define D18F2x09C_x0D0F_2002_ValidTxAndPre_MASK 0x8000 -#define D18F2x09C_x0D0F_2002_Reserved_31_16_OFFSET 16 -#define D18F2x09C_x0D0F_2002_Reserved_31_16_WIDTH 16 -#define D18F2x09C_x0D0F_2002_Reserved_31_16_MASK 0xffff0000 - -/// D18F2x09C_x0D0F_2002 -typedef union { - struct { ///< - UINT32 TxPreN:6 ; ///< - UINT32 TxPreP:6 ; ///< - UINT32 Reserved_14_12:3 ; ///< - UINT32 ValidTxAndPre:1 ; ///< - UINT32 Reserved_31_16:16; ///< - } Field; ///< - UINT32 Value; ///< -} D18F2x09C_x0D0F_2002_STRUCT; - -// **** D18F2x09C_x0D0F_201F Register Definition **** -// Address -#define D18F2x09C_x0D0F_201F_ADDRESS 0xd0f201f - -// Type -#define D18F2x09C_x0D0F_201F_TYPE TYPE_D18F2x09C -// Field Data -#define D18F2x09C_x0D0F_201F_Reserved_2_0_OFFSET 0 -#define D18F2x09C_x0D0F_201F_Reserved_2_0_WIDTH 3 -#define D18F2x09C_x0D0F_201F_Reserved_2_0_MASK 0x7 -#define D18F2x09C_x0D0F_201F_RxVioLvl_OFFSET 3 -#define D18F2x09C_x0D0F_201F_RxVioLvl_WIDTH 2 -#define D18F2x09C_x0D0F_201F_RxVioLvl_MASK 0x18 -#define D18F2x09C_x0D0F_201F_Reserved_31_5_OFFSET 5 -#define D18F2x09C_x0D0F_201F_Reserved_31_5_WIDTH 27 -#define D18F2x09C_x0D0F_201F_Reserved_31_5_MASK 0xffffffe0 - -/// D18F2x09C_x0D0F_201F -typedef union { - struct { ///< - UINT32 Reserved_2_0:3 ; ///< - UINT32 RxVioLvl:2 ; ///< - UINT32 Reserved_31_5:27; ///< - } Field; ///< - UINT32 Value; ///< -} D18F2x09C_x0D0F_201F_STRUCT; - -// **** D18F2x09C_x0D0F_2020 Register Definition **** -// Address -#define D18F2x09C_x0D0F_2020_ADDRESS 0xd0f2020 - -// Type -#define D18F2x09C_x0D0F_2020_TYPE TYPE_D18F2x09C -// Field Data -#define D18F2x09C_x0D0F_2020_ClkFineDly_OFFSET 0 -#define D18F2x09C_x0D0F_2020_ClkFineDly_WIDTH 5 -#define D18F2x09C_x0D0F_2020_ClkFineDly_MASK 0x1f -#define D18F2x09C_x0D0F_2020_Reserved_6_5_OFFSET 5 -#define D18F2x09C_x0D0F_2020_Reserved_6_5_WIDTH 2 -#define D18F2x09C_x0D0F_2020_Reserved_6_5_MASK 0x60 -#define D18F2x09C_x0D0F_2020_FenceBit_OFFSET 7 -#define D18F2x09C_x0D0F_2020_FenceBit_WIDTH 1 -#define D18F2x09C_x0D0F_2020_FenceBit_MASK 0x80 -#define D18F2x09C_x0D0F_2020_Reserved_13_8_OFFSET 8 -#define D18F2x09C_x0D0F_2020_Reserved_13_8_WIDTH 6 -#define D18F2x09C_x0D0F_2020_Reserved_13_8_MASK 0x3f00 -#define D18F2x09C_x0D0F_2020_DllNukeLoad_OFFSET 14 -#define D18F2x09C_x0D0F_2020_DllNukeLoad_WIDTH 1 -#define D18F2x09C_x0D0F_2020_DllNukeLoad_MASK 0x4000 -#define D18F2x09C_x0D0F_2020_Reserved_31_15_OFFSET 15 -#define D18F2x09C_x0D0F_2020_Reserved_31_15_WIDTH 17 -#define D18F2x09C_x0D0F_2020_Reserved_31_15_MASK 0xffff8000 - -/// D18F2x09C_x0D0F_2020 -typedef union { - struct { ///< - UINT32 ClkFineDly:5 ; ///< - UINT32 Reserved_6_5:2 ; ///< - UINT32 FenceBit:1 ; ///< - UINT32 Reserved_13_8:6 ; ///< - UINT32 DllNukeLoad:1 ; ///< - UINT32 Reserved_31_15:17; ///< - } Field; ///< - UINT32 Value; ///< -} D18F2x09C_x0D0F_2020_STRUCT; - -// **** D18F2x09C_x0D0F_2030 Register Definition **** -// Address -#define D18F2x09C_x0D0F_2030_ADDRESS 0xd0f2030 - -// Type -#define D18F2x09C_x0D0F_2030_TYPE TYPE_D18F2x09C -// Field Data -#define D18F2x09C_x0D0F_2030_Reserved_3_0_OFFSET 0 -#define D18F2x09C_x0D0F_2030_Reserved_3_0_WIDTH 4 -#define D18F2x09C_x0D0F_2030_Reserved_3_0_MASK 0xf -#define D18F2x09C_x0D0F_2030_PwrDn_OFFSET 4 -#define D18F2x09C_x0D0F_2030_PwrDn_WIDTH 1 -#define D18F2x09C_x0D0F_2030_PwrDn_MASK 0x10 -#define D18F2x09C_x0D0F_2030_Reserved_31_5_OFFSET 5 -#define D18F2x09C_x0D0F_2030_Reserved_31_5_WIDTH 27 -#define D18F2x09C_x0D0F_2030_Reserved_31_5_MASK 0xffffffe0 - -/// D18F2x09C_x0D0F_2030 -typedef union { - struct { ///< - UINT32 Reserved_3_0:4 ; ///< - UINT32 PwrDn:1 ; ///< - UINT32 Reserved_31_5:27; ///< - } Field; ///< - UINT32 Value; ///< -} D18F2x09C_x0D0F_2030_STRUCT; - -// **** D18F2x09C_x0D0F_2031 Register Definition **** -// Address -#define D18F2x09C_x0D0F_2031_ADDRESS 0xd0f2031 - -// Type -#define D18F2x09C_x0D0F_2031_TYPE TYPE_D18F2x09C -// Field Data -#define D18F2x09C_x0D0F_2031_Fence2ThresholdTxPad_OFFSET 0 -#define D18F2x09C_x0D0F_2031_Fence2ThresholdTxPad_WIDTH 4 -#define D18F2x09C_x0D0F_2031_Fence2ThresholdTxPad_MASK 0xf -#define D18F2x09C_x0D0F_2031_Fence2EnableTxPad_OFFSET 4 -#define D18F2x09C_x0D0F_2031_Fence2EnableTxPad_WIDTH 1 -#define D18F2x09C_x0D0F_2031_Fence2EnableTxPad_MASK 0x10 -#define D18F2x09C_x0D0F_2031_Reserved_31_5_OFFSET 5 -#define D18F2x09C_x0D0F_2031_Reserved_31_5_WIDTH 27 -#define D18F2x09C_x0D0F_2031_Reserved_31_5_MASK 0xffffffe0 - -/// D18F2x09C_x0D0F_2031 -typedef union { - struct { ///< - UINT32 Fence2ThresholdTxPad:4 ; ///< - UINT32 Fence2EnableTxPad:1 ; ///< - UINT32 Reserved_31_5:27; ///< - } Field; ///< - UINT32 Value; ///< -} D18F2x09C_x0D0F_2031_STRUCT; - -// **** D18F2x09C_x0D0F_2102 Register Definition **** -// Address -#define D18F2x09C_x0D0F_2102_ADDRESS 0xd0f2102 - -// Type -#define D18F2x09C_x0D0F_2102_TYPE TYPE_D18F2x09C -// Field Data -#define D18F2x09C_x0D0F_2102_TxPreN_OFFSET 0 -#define D18F2x09C_x0D0F_2102_TxPreN_WIDTH 6 -#define D18F2x09C_x0D0F_2102_TxPreN_MASK 0x3f -#define D18F2x09C_x0D0F_2102_TxPreP_OFFSET 6 -#define D18F2x09C_x0D0F_2102_TxPreP_WIDTH 6 -#define D18F2x09C_x0D0F_2102_TxPreP_MASK 0xfc0 -#define D18F2x09C_x0D0F_2102_Reserved_14_12_OFFSET 12 -#define D18F2x09C_x0D0F_2102_Reserved_14_12_WIDTH 3 -#define D18F2x09C_x0D0F_2102_Reserved_14_12_MASK 0x7000 -#define D18F2x09C_x0D0F_2102_ValidTxAndPre_OFFSET 15 -#define D18F2x09C_x0D0F_2102_ValidTxAndPre_WIDTH 1 -#define D18F2x09C_x0D0F_2102_ValidTxAndPre_MASK 0x8000 -#define D18F2x09C_x0D0F_2102_Reserved_31_16_OFFSET 16 -#define D18F2x09C_x0D0F_2102_Reserved_31_16_WIDTH 16 -#define D18F2x09C_x0D0F_2102_Reserved_31_16_MASK 0xffff0000 - -/// D18F2x09C_x0D0F_2102 -typedef union { - struct { ///< - UINT32 TxPreN:6 ; ///< - UINT32 TxPreP:6 ; ///< - UINT32 Reserved_14_12:3 ; ///< - UINT32 ValidTxAndPre:1 ; ///< - UINT32 Reserved_31_16:16; ///< - } Field; ///< - UINT32 Value; ///< -} D18F2x09C_x0D0F_2102_STRUCT; - -// **** D18F2x09C_x0D0F_211F Register Definition **** -// Address -#define D18F2x09C_x0D0F_211F_ADDRESS 0xd0f211f - -// Type -#define D18F2x09C_x0D0F_211F_TYPE TYPE_D18F2x09C -// Field Data -#define D18F2x09C_x0D0F_211F_Reserved_2_0_OFFSET 0 -#define D18F2x09C_x0D0F_211F_Reserved_2_0_WIDTH 3 -#define D18F2x09C_x0D0F_211F_Reserved_2_0_MASK 0x7 -#define D18F2x09C_x0D0F_211F_RxVioLvl_OFFSET 3 -#define D18F2x09C_x0D0F_211F_RxVioLvl_WIDTH 2 -#define D18F2x09C_x0D0F_211F_RxVioLvl_MASK 0x18 -#define D18F2x09C_x0D0F_211F_Reserved_31_5_OFFSET 5 -#define D18F2x09C_x0D0F_211F_Reserved_31_5_WIDTH 27 -#define D18F2x09C_x0D0F_211F_Reserved_31_5_MASK 0xffffffe0 - -/// D18F2x09C_x0D0F_211F -typedef union { - struct { ///< - UINT32 Reserved_2_0:3 ; ///< - UINT32 RxVioLvl:2 ; ///< - UINT32 Reserved_31_5:27; ///< - } Field; ///< - UINT32 Value; ///< -} D18F2x09C_x0D0F_211F_STRUCT; - -// **** D18F2x09C_x0D0F_2120 Register Definition **** -// Address -#define D18F2x09C_x0D0F_2120_ADDRESS 0xd0f2120 - -// Type -#define D18F2x09C_x0D0F_2120_TYPE TYPE_D18F2x09C -// Field Data -#define D18F2x09C_x0D0F_2120_ClkFineDly_OFFSET 0 -#define D18F2x09C_x0D0F_2120_ClkFineDly_WIDTH 5 -#define D18F2x09C_x0D0F_2120_ClkFineDly_MASK 0x1f -#define D18F2x09C_x0D0F_2120_Reserved_6_5_OFFSET 5 -#define D18F2x09C_x0D0F_2120_Reserved_6_5_WIDTH 2 -#define D18F2x09C_x0D0F_2120_Reserved_6_5_MASK 0x60 -#define D18F2x09C_x0D0F_2120_FenceBit_OFFSET 7 -#define D18F2x09C_x0D0F_2120_FenceBit_WIDTH 1 -#define D18F2x09C_x0D0F_2120_FenceBit_MASK 0x80 -#define D18F2x09C_x0D0F_2120_Reserved_13_8_OFFSET 8 -#define D18F2x09C_x0D0F_2120_Reserved_13_8_WIDTH 6 -#define D18F2x09C_x0D0F_2120_Reserved_13_8_MASK 0x3f00 -#define D18F2x09C_x0D0F_2120_DllNukeLoad_OFFSET 14 -#define D18F2x09C_x0D0F_2120_DllNukeLoad_WIDTH 1 -#define D18F2x09C_x0D0F_2120_DllNukeLoad_MASK 0x4000 -#define D18F2x09C_x0D0F_2120_Reserved_31_15_OFFSET 15 -#define D18F2x09C_x0D0F_2120_Reserved_31_15_WIDTH 17 -#define D18F2x09C_x0D0F_2120_Reserved_31_15_MASK 0xffff8000 - -/// D18F2x09C_x0D0F_2120 -typedef union { - struct { ///< - UINT32 ClkFineDly:5 ; ///< - UINT32 Reserved_6_5:2 ; ///< - UINT32 FenceBit:1 ; ///< - UINT32 Reserved_13_8:6 ; ///< - UINT32 DllNukeLoad:1 ; ///< - UINT32 Reserved_31_15:17; ///< - } Field; ///< - UINT32 Value; ///< -} D18F2x09C_x0D0F_2120_STRUCT; - -// **** D18F2x09C_x0D0F_2130 Register Definition **** -// Address -#define D18F2x09C_x0D0F_2130_ADDRESS 0xd0f2130 - -// Type -#define D18F2x09C_x0D0F_2130_TYPE TYPE_D18F2x09C -// Field Data -#define D18F2x09C_x0D0F_2130_Reserved_3_0_OFFSET 0 -#define D18F2x09C_x0D0F_2130_Reserved_3_0_WIDTH 4 -#define D18F2x09C_x0D0F_2130_Reserved_3_0_MASK 0xf -#define D18F2x09C_x0D0F_2130_PwrDn_OFFSET 4 -#define D18F2x09C_x0D0F_2130_PwrDn_WIDTH 1 -#define D18F2x09C_x0D0F_2130_PwrDn_MASK 0x10 -#define D18F2x09C_x0D0F_2130_Reserved_31_5_OFFSET 5 -#define D18F2x09C_x0D0F_2130_Reserved_31_5_WIDTH 27 -#define D18F2x09C_x0D0F_2130_Reserved_31_5_MASK 0xffffffe0 - -/// D18F2x09C_x0D0F_2130 -typedef union { - struct { ///< - UINT32 Reserved_3_0:4 ; ///< - UINT32 PwrDn:1 ; ///< - UINT32 Reserved_31_5:27; ///< - } Field; ///< - UINT32 Value; ///< -} D18F2x09C_x0D0F_2130_STRUCT; - -// **** D18F2x09C_x0D0F_2131 Register Definition **** -// Address -#define D18F2x09C_x0D0F_2131_ADDRESS 0xd0f2131 - -// Type -#define D18F2x09C_x0D0F_2131_TYPE TYPE_D18F2x09C -// Field Data -#define D18F2x09C_x0D0F_2131_Fence2ThresholdTxPad_OFFSET 0 -#define D18F2x09C_x0D0F_2131_Fence2ThresholdTxPad_WIDTH 4 -#define D18F2x09C_x0D0F_2131_Fence2ThresholdTxPad_MASK 0xf -#define D18F2x09C_x0D0F_2131_Fence2EnableTxPad_OFFSET 4 -#define D18F2x09C_x0D0F_2131_Fence2EnableTxPad_WIDTH 1 -#define D18F2x09C_x0D0F_2131_Fence2EnableTxPad_MASK 0x10 -#define D18F2x09C_x0D0F_2131_Reserved_31_5_OFFSET 5 -#define D18F2x09C_x0D0F_2131_Reserved_31_5_WIDTH 27 -#define D18F2x09C_x0D0F_2131_Reserved_31_5_MASK 0xffffffe0 - -/// D18F2x09C_x0D0F_2131 -typedef union { - struct { ///< - UINT32 Fence2ThresholdTxPad:4 ; ///< - UINT32 Fence2EnableTxPad:1 ; ///< - UINT32 Reserved_31_5:27; ///< - } Field; ///< - UINT32 Value; ///< -} D18F2x09C_x0D0F_2131_STRUCT; - -// **** D18F2x09C_x0D0F_4009 Register Definition **** -// Address -#define D18F2x09C_x0D0F_4009_ADDRESS 0xd0f4009 - -// Type -#define D18F2x09C_x0D0F_4009_TYPE TYPE_D18F2x09C -// Field Data -#define D18F2x09C_x0D0F_4009_Reserved_1_0_OFFSET 0 -#define D18F2x09C_x0D0F_4009_Reserved_1_0_WIDTH 2 -#define D18F2x09C_x0D0F_4009_Reserved_1_0_MASK 0x3 -#define D18F2x09C_x0D0F_4009_ComparatorAdjust_OFFSET 2 -#define D18F2x09C_x0D0F_4009_ComparatorAdjust_WIDTH 2 -#define D18F2x09C_x0D0F_4009_ComparatorAdjust_MASK 0xc -#define D18F2x09C_x0D0F_4009_Reserved_13_4_OFFSET 4 -#define D18F2x09C_x0D0F_4009_Reserved_13_4_WIDTH 10 -#define D18F2x09C_x0D0F_4009_Reserved_13_4_MASK 0x3ff0 -#define D18F2x09C_x0D0F_4009_CmpVioLvl_OFFSET 14 -#define D18F2x09C_x0D0F_4009_CmpVioLvl_WIDTH 2 -#define D18F2x09C_x0D0F_4009_CmpVioLvl_MASK 0xc000 -#define D18F2x09C_x0D0F_4009_Reserved_31_16_OFFSET 16 -#define D18F2x09C_x0D0F_4009_Reserved_31_16_WIDTH 16 -#define D18F2x09C_x0D0F_4009_Reserved_31_16_MASK 0xffff0000 - -/// D18F2x09C_x0D0F_4009 -typedef union { - struct { ///< - UINT32 Reserved_1_0:2 ; ///< - UINT32 ComparatorAdjust:2 ; ///< - UINT32 Reserved_13_4:10; ///< - UINT32 CmpVioLvl:2 ; ///< - UINT32 Reserved_31_16:16; ///< - } Field; ///< - UINT32 Value; ///< -} D18F2x09C_x0D0F_4009_STRUCT; - -// **** D18F2x09C_x0D0F_8002 Register Definition **** -// Address -#define D18F2x09C_x0D0F_8002_ADDRESS 0xd0f8002 - -// Type -#define D18F2x09C_x0D0F_8002_TYPE TYPE_D18F2x09C -// Field Data -#define D18F2x09C_x0D0F_8002_TxPreN_OFFSET 0 -#define D18F2x09C_x0D0F_8002_TxPreN_WIDTH 6 -#define D18F2x09C_x0D0F_8002_TxPreN_MASK 0x3f -#define D18F2x09C_x0D0F_8002_TxPreP_OFFSET 6 -#define D18F2x09C_x0D0F_8002_TxPreP_WIDTH 6 -#define D18F2x09C_x0D0F_8002_TxPreP_MASK 0xfc0 -#define D18F2x09C_x0D0F_8002_Reserved_14_12_OFFSET 12 -#define D18F2x09C_x0D0F_8002_Reserved_14_12_WIDTH 3 -#define D18F2x09C_x0D0F_8002_Reserved_14_12_MASK 0x7000 -#define D18F2x09C_x0D0F_8002_ValidTxAndPre_OFFSET 15 -#define D18F2x09C_x0D0F_8002_ValidTxAndPre_WIDTH 1 -#define D18F2x09C_x0D0F_8002_ValidTxAndPre_MASK 0x8000 -#define D18F2x09C_x0D0F_8002_Reserved_31_16_OFFSET 16 -#define D18F2x09C_x0D0F_8002_Reserved_31_16_WIDTH 16 -#define D18F2x09C_x0D0F_8002_Reserved_31_16_MASK 0xffff0000 - -/// D18F2x09C_x0D0F_8002 -typedef union { - struct { ///< - UINT32 TxPreN:6 ; ///< - UINT32 TxPreP:6 ; ///< - UINT32 Reserved_14_12:3 ; ///< - UINT32 ValidTxAndPre:1 ; ///< - UINT32 Reserved_31_16:16; ///< - } Field; ///< - UINT32 Value; ///< -} D18F2x09C_x0D0F_8002_STRUCT; - -// **** D18F2x09C_x0D0F_8006 Register Definition **** -// Address -#define D18F2x09C_x0D0F_8006_ADDRESS 0xd0f8006 - -// Type -#define D18F2x09C_x0D0F_8006_TYPE TYPE_D18F2x09C -// Field Data -#define D18F2x09C_x0D0F_8006_TxPreN_OFFSET 0 -#define D18F2x09C_x0D0F_8006_TxPreN_WIDTH 6 -#define D18F2x09C_x0D0F_8006_TxPreN_MASK 0x3f -#define D18F2x09C_x0D0F_8006_TxPreP_OFFSET 6 -#define D18F2x09C_x0D0F_8006_TxPreP_WIDTH 6 -#define D18F2x09C_x0D0F_8006_TxPreP_MASK 0xfc0 -#define D18F2x09C_x0D0F_8006_Reserved_31_12_OFFSET 12 -#define D18F2x09C_x0D0F_8006_Reserved_31_12_WIDTH 20 -#define D18F2x09C_x0D0F_8006_Reserved_31_12_MASK 0xfffff000 - -/// D18F2x09C_x0D0F_8006 -typedef union { - struct { ///< - UINT32 TxPreN:6 ; ///< - UINT32 TxPreP:6 ; ///< - UINT32 Reserved_31_12:20; ///< - } Field; ///< - UINT32 Value; ///< -} D18F2x09C_x0D0F_8006_STRUCT; - -// **** D18F2x09C_x0D0F_800A Register Definition **** -// Address -#define D18F2x09C_x0D0F_800A_ADDRESS 0xd0f800a - -// Type -#define D18F2x09C_x0D0F_800A_TYPE TYPE_D18F2x09C -// Field Data -#define D18F2x09C_x0D0F_800A_TxPreN_OFFSET 0 -#define D18F2x09C_x0D0F_800A_TxPreN_WIDTH 6 -#define D18F2x09C_x0D0F_800A_TxPreN_MASK 0x3f -#define D18F2x09C_x0D0F_800A_TxPreP_OFFSET 6 -#define D18F2x09C_x0D0F_800A_TxPreP_WIDTH 6 -#define D18F2x09C_x0D0F_800A_TxPreP_MASK 0xfc0 -#define D18F2x09C_x0D0F_800A_Reserved_31_12_OFFSET 12 -#define D18F2x09C_x0D0F_800A_Reserved_31_12_WIDTH 20 -#define D18F2x09C_x0D0F_800A_Reserved_31_12_MASK 0xfffff000 - -/// D18F2x09C_x0D0F_800A -typedef union { - struct { ///< - UINT32 TxPreN:6 ; ///< - UINT32 TxPreP:6 ; ///< - UINT32 Reserved_31_12:20; ///< - } Field; ///< - UINT32 Value; ///< -} D18F2x09C_x0D0F_800A_STRUCT; - -// **** D18F2x09C_x0D0F_801F Register Definition **** -// Address -#define D18F2x09C_x0D0F_801F_ADDRESS 0xd0f801f - -// Type -#define D18F2x09C_x0D0F_801F_TYPE TYPE_D18F2x09C -// Field Data -#define D18F2x09C_x0D0F_801F_Reserved_2_0_OFFSET 0 -#define D18F2x09C_x0D0F_801F_Reserved_2_0_WIDTH 3 -#define D18F2x09C_x0D0F_801F_Reserved_2_0_MASK 0x7 -#define D18F2x09C_x0D0F_801F_RxVioLvl_OFFSET 3 -#define D18F2x09C_x0D0F_801F_RxVioLvl_WIDTH 2 -#define D18F2x09C_x0D0F_801F_RxVioLvl_MASK 0x18 -#define D18F2x09C_x0D0F_801F_Reserved_31_5_OFFSET 5 -#define D18F2x09C_x0D0F_801F_Reserved_31_5_WIDTH 27 -#define D18F2x09C_x0D0F_801F_Reserved_31_5_MASK 0xffffffe0 - -/// D18F2x09C_x0D0F_801F -typedef union { - struct { ///< - UINT32 Reserved_2_0:3 ; ///< - UINT32 RxVioLvl:2 ; ///< - UINT32 Reserved_31_5:27; ///< - } Field; ///< - UINT32 Value; ///< -} D18F2x09C_x0D0F_801F_STRUCT; - -// **** D18F2x09C_x0D0F_8031 Register Definition **** -// Address -#define D18F2x09C_x0D0F_8031_ADDRESS 0xd0f8031 - -// Type -#define D18F2x09C_x0D0F_8031_TYPE TYPE_D18F2x09C -// Field Data -#define D18F2x09C_x0D0F_8031_Fence2ThresholdTxPad_OFFSET 0 -#define D18F2x09C_x0D0F_8031_Fence2ThresholdTxPad_WIDTH 4 -#define D18F2x09C_x0D0F_8031_Fence2ThresholdTxPad_MASK 0xf -#define D18F2x09C_x0D0F_8031_Fence2EnableTxPad_OFFSET 4 -#define D18F2x09C_x0D0F_8031_Fence2EnableTxPad_WIDTH 1 -#define D18F2x09C_x0D0F_8031_Fence2EnableTxPad_MASK 0x10 -#define D18F2x09C_x0D0F_8031_Reserved_31_5_OFFSET 5 -#define D18F2x09C_x0D0F_8031_Reserved_31_5_WIDTH 27 -#define D18F2x09C_x0D0F_8031_Reserved_31_5_MASK 0xffffffe0 - -/// D18F2x09C_x0D0F_8031 -typedef union { - struct { ///< - UINT32 Fence2ThresholdTxPad:4 ; ///< - UINT32 Fence2EnableTxPad:1 ; ///< - UINT32 Reserved_31_5:27; ///< - } Field; ///< - UINT32 Value; ///< -} D18F2x09C_x0D0F_8031_STRUCT; - -// **** D18F2x09C_x0D0F_8102 Register Definition **** -// Address -#define D18F2x09C_x0D0F_8102_ADDRESS 0xd0f8102 - -// Type -#define D18F2x09C_x0D0F_8102_TYPE TYPE_D18F2x09C -// Field Data -#define D18F2x09C_x0D0F_8102_TxPreN_OFFSET 0 -#define D18F2x09C_x0D0F_8102_TxPreN_WIDTH 6 -#define D18F2x09C_x0D0F_8102_TxPreN_MASK 0x3f -#define D18F2x09C_x0D0F_8102_TxPreP_OFFSET 6 -#define D18F2x09C_x0D0F_8102_TxPreP_WIDTH 6 -#define D18F2x09C_x0D0F_8102_TxPreP_MASK 0xfc0 -#define D18F2x09C_x0D0F_8102_Reserved_14_12_OFFSET 12 -#define D18F2x09C_x0D0F_8102_Reserved_14_12_WIDTH 3 -#define D18F2x09C_x0D0F_8102_Reserved_14_12_MASK 0x7000 -#define D18F2x09C_x0D0F_8102_ValidTxAndPre_OFFSET 15 -#define D18F2x09C_x0D0F_8102_ValidTxAndPre_WIDTH 1 -#define D18F2x09C_x0D0F_8102_ValidTxAndPre_MASK 0x8000 -#define D18F2x09C_x0D0F_8102_Reserved_31_16_OFFSET 16 -#define D18F2x09C_x0D0F_8102_Reserved_31_16_WIDTH 16 -#define D18F2x09C_x0D0F_8102_Reserved_31_16_MASK 0xffff0000 - -/// D18F2x09C_x0D0F_8102 -typedef union { - struct { ///< - UINT32 TxPreN:6 ; ///< - UINT32 TxPreP:6 ; ///< - UINT32 Reserved_14_12:3 ; ///< - UINT32 ValidTxAndPre:1 ; ///< - UINT32 Reserved_31_16:16; ///< - } Field; ///< - UINT32 Value; ///< -} D18F2x09C_x0D0F_8102_STRUCT; - -// **** D18F2x09C_x0D0F_8106 Register Definition **** -// Address -#define D18F2x09C_x0D0F_8106_ADDRESS 0xd0f8106 - -// Type -#define D18F2x09C_x0D0F_8106_TYPE TYPE_D18F2x09C -// Field Data -#define D18F2x09C_x0D0F_8106_TxPreN_OFFSET 0 -#define D18F2x09C_x0D0F_8106_TxPreN_WIDTH 6 -#define D18F2x09C_x0D0F_8106_TxPreN_MASK 0x3f -#define D18F2x09C_x0D0F_8106_TxPreP_OFFSET 6 -#define D18F2x09C_x0D0F_8106_TxPreP_WIDTH 6 -#define D18F2x09C_x0D0F_8106_TxPreP_MASK 0xfc0 -#define D18F2x09C_x0D0F_8106_Reserved_31_12_OFFSET 12 -#define D18F2x09C_x0D0F_8106_Reserved_31_12_WIDTH 20 -#define D18F2x09C_x0D0F_8106_Reserved_31_12_MASK 0xfffff000 - -/// D18F2x09C_x0D0F_8106 -typedef union { - struct { ///< - UINT32 TxPreN:6 ; ///< - UINT32 TxPreP:6 ; ///< - UINT32 Reserved_31_12:20; ///< - } Field; ///< - UINT32 Value; ///< -} D18F2x09C_x0D0F_8106_STRUCT; - -// **** D18F2x09C_x0D0F_810A Register Definition **** -// Address -#define D18F2x09C_x0D0F_810A_ADDRESS 0xd0f810a - -// Type -#define D18F2x09C_x0D0F_810A_TYPE TYPE_D18F2x09C -// Field Data -#define D18F2x09C_x0D0F_810A_TxPreN_OFFSET 0 -#define D18F2x09C_x0D0F_810A_TxPreN_WIDTH 6 -#define D18F2x09C_x0D0F_810A_TxPreN_MASK 0x3f -#define D18F2x09C_x0D0F_810A_TxPreP_OFFSET 6 -#define D18F2x09C_x0D0F_810A_TxPreP_WIDTH 6 -#define D18F2x09C_x0D0F_810A_TxPreP_MASK 0xfc0 -#define D18F2x09C_x0D0F_810A_Reserved_31_12_OFFSET 12 -#define D18F2x09C_x0D0F_810A_Reserved_31_12_WIDTH 20 -#define D18F2x09C_x0D0F_810A_Reserved_31_12_MASK 0xfffff000 - -/// D18F2x09C_x0D0F_810A -typedef union { - struct { ///< - UINT32 TxPreN:6 ; ///< - UINT32 TxPreP:6 ; ///< - UINT32 Reserved_31_12:20; ///< - } Field; ///< - UINT32 Value; ///< -} D18F2x09C_x0D0F_810A_STRUCT; - -// **** D18F2x09C_x0D0F_811F Register Definition **** -// Address -#define D18F2x09C_x0D0F_811F_ADDRESS 0xd0f811f - -// Type -#define D18F2x09C_x0D0F_811F_TYPE TYPE_D18F2x09C -// Field Data -#define D18F2x09C_x0D0F_811F_Reserved_2_0_OFFSET 0 -#define D18F2x09C_x0D0F_811F_Reserved_2_0_WIDTH 3 -#define D18F2x09C_x0D0F_811F_Reserved_2_0_MASK 0x7 -#define D18F2x09C_x0D0F_811F_RxVioLvl_OFFSET 3 -#define D18F2x09C_x0D0F_811F_RxVioLvl_WIDTH 2 -#define D18F2x09C_x0D0F_811F_RxVioLvl_MASK 0x18 -#define D18F2x09C_x0D0F_811F_Reserved_31_5_OFFSET 5 -#define D18F2x09C_x0D0F_811F_Reserved_31_5_WIDTH 27 -#define D18F2x09C_x0D0F_811F_Reserved_31_5_MASK 0xffffffe0 - -/// D18F2x09C_x0D0F_811F -typedef union { - struct { ///< - UINT32 Reserved_2_0:3 ; ///< - UINT32 RxVioLvl:2 ; ///< - UINT32 Reserved_31_5:27; ///< - } Field; ///< - UINT32 Value; ///< -} D18F2x09C_x0D0F_811F_STRUCT; - -// **** D18F2x09C_x0D0F_812F Register Definition **** -// Address -#define D18F2x09C_x0D0F_812F_ADDRESS 0xd0f812f - -// Type -#define D18F2x09C_x0D0F_812F_TYPE TYPE_D18F2x09C -// Field Data -#define D18F2x09C_x0D0F_812F_PARTri_OFFSET 0 -#define D18F2x09C_x0D0F_812F_PARTri_WIDTH 1 -#define D18F2x09C_x0D0F_812F_PARTri_MASK 0x1 -#define D18F2x09C_x0D0F_812F_Reserved_4_1_OFFSET 1 -#define D18F2x09C_x0D0F_812F_Reserved_4_1_WIDTH 4 -#define D18F2x09C_x0D0F_812F_Reserved_4_1_MASK 0x1e -#define D18F2x09C_x0D0F_812F_Add17Tri_OFFSET 5 -#define D18F2x09C_x0D0F_812F_Add17Tri_WIDTH 1 -#define D18F2x09C_x0D0F_812F_Add17Tri_MASK 0x20 -#define D18F2x09C_x0D0F_812F_Reserved_6_6_OFFSET 6 -#define D18F2x09C_x0D0F_812F_Reserved_6_6_WIDTH 1 -#define D18F2x09C_x0D0F_812F_Reserved_6_6_MASK 0x40 -#define D18F2x09C_x0D0F_812F_Add16Tri_OFFSET 7 -#define D18F2x09C_x0D0F_812F_Add16Tri_WIDTH 1 -#define D18F2x09C_x0D0F_812F_Add16Tri_MASK 0x80 -#define D18F2x09C_x0D0F_812F_Reserved_31_8_OFFSET 8 -#define D18F2x09C_x0D0F_812F_Reserved_31_8_WIDTH 24 -#define D18F2x09C_x0D0F_812F_Reserved_31_8_MASK 0xffffff00 - -/// D18F2x09C_x0D0F_812F -typedef union { - struct { ///< - UINT32 PARTri:1 ; ///< - UINT32 Reserved_4_1:4 ; ///< - UINT32 Add17Tri:1 ; ///< - UINT32 Reserved_6_6:1 ; ///< - UINT32 Add16Tri:1 ; ///< - UINT32 Reserved_31_8:24; ///< - } Field; ///< - UINT32 Value; ///< -} D18F2x09C_x0D0F_812F_STRUCT; - -// **** D18F2x09C_x0D0F_8131 Register Definition **** -// Address -#define D18F2x09C_x0D0F_8131_ADDRESS 0xd0f8131 - -// Type -#define D18F2x09C_x0D0F_8131_TYPE TYPE_D18F2x09C -// Field Data -#define D18F2x09C_x0D0F_8131_Fence2ThresholdTxPad_OFFSET 0 -#define D18F2x09C_x0D0F_8131_Fence2ThresholdTxPad_WIDTH 4 -#define D18F2x09C_x0D0F_8131_Fence2ThresholdTxPad_MASK 0xf -#define D18F2x09C_x0D0F_8131_Fence2EnableTxPad_OFFSET 4 -#define D18F2x09C_x0D0F_8131_Fence2EnableTxPad_WIDTH 1 -#define D18F2x09C_x0D0F_8131_Fence2EnableTxPad_MASK 0x10 -#define D18F2x09C_x0D0F_8131_Reserved_31_5_OFFSET 5 -#define D18F2x09C_x0D0F_8131_Reserved_31_5_WIDTH 27 -#define D18F2x09C_x0D0F_8131_Reserved_31_5_MASK 0xffffffe0 - -/// D18F2x09C_x0D0F_8131 -typedef union { - struct { ///< - UINT32 Fence2ThresholdTxPad:4 ; ///< - UINT32 Fence2EnableTxPad:1 ; ///< - UINT32 Reserved_31_5:27; ///< - } Field; ///< - UINT32 Value; ///< -} D18F2x09C_x0D0F_8131_STRUCT; - -// **** D18F2x09C_x0D0F_C000 Register Definition **** -// Address -#define D18F2x09C_x0D0F_C000_ADDRESS 0xd0fc000 - -// Type -#define D18F2x09C_x0D0F_C000_TYPE TYPE_D18F2x09C -// Field Data -#define D18F2x09C_x0D0F_C000_Reserved_7_0_OFFSET 0 -#define D18F2x09C_x0D0F_C000_Reserved_7_0_WIDTH 8 -#define D18F2x09C_x0D0F_C000_Reserved_7_0_MASK 0xff -#define D18F2x09C_x0D0F_C000_LowPowerDrvStrengthEn_OFFSET 8 -#define D18F2x09C_x0D0F_C000_LowPowerDrvStrengthEn_WIDTH 1 -#define D18F2x09C_x0D0F_C000_LowPowerDrvStrengthEn_MASK 0x100 -#define D18F2x09C_x0D0F_C000_Reserved_31_9_OFFSET 9 -#define D18F2x09C_x0D0F_C000_Reserved_31_9_WIDTH 23 -#define D18F2x09C_x0D0F_C000_Reserved_31_9_MASK 0xfffffe00 - -/// D18F2x09C_x0D0F_C000 -typedef union { - struct { ///< - UINT32 Reserved_7_0:8 ; ///< - UINT32 LowPowerDrvStrengthEn:1 ; ///< - UINT32 Reserved_31_9:23; ///< - } Field; ///< - UINT32 Value; ///< -} D18F2x09C_x0D0F_C000_STRUCT; - -// **** D18F2x09C_x0D0F_C002 Register Definition **** -// Address -#define D18F2x09C_x0D0F_C002_ADDRESS 0xd0fc002 - -// Type -#define D18F2x09C_x0D0F_C002_TYPE TYPE_D18F2x09C -// Field Data -#define D18F2x09C_x0D0F_C002_TxPreN_OFFSET 0 -#define D18F2x09C_x0D0F_C002_TxPreN_WIDTH 6 -#define D18F2x09C_x0D0F_C002_TxPreN_MASK 0x3f -#define D18F2x09C_x0D0F_C002_TxPreP_OFFSET 6 -#define D18F2x09C_x0D0F_C002_TxPreP_WIDTH 6 -#define D18F2x09C_x0D0F_C002_TxPreP_MASK 0xfc0 -#define D18F2x09C_x0D0F_C002_Reserved_14_12_OFFSET 12 -#define D18F2x09C_x0D0F_C002_Reserved_14_12_WIDTH 3 -#define D18F2x09C_x0D0F_C002_Reserved_14_12_MASK 0x7000 -#define D18F2x09C_x0D0F_C002_ValidTxAndPre_OFFSET 15 -#define D18F2x09C_x0D0F_C002_ValidTxAndPre_WIDTH 1 -#define D18F2x09C_x0D0F_C002_ValidTxAndPre_MASK 0x8000 -#define D18F2x09C_x0D0F_C002_Reserved_31_16_OFFSET 16 -#define D18F2x09C_x0D0F_C002_Reserved_31_16_WIDTH 16 -#define D18F2x09C_x0D0F_C002_Reserved_31_16_MASK 0xffff0000 - -/// D18F2x09C_x0D0F_C002 -typedef union { - struct { ///< - UINT32 TxPreN:6 ; ///< - UINT32 TxPreP:6 ; ///< - UINT32 Reserved_14_12:3 ; ///< - UINT32 ValidTxAndPre:1 ; ///< - UINT32 Reserved_31_16:16; ///< - } Field; ///< - UINT32 Value; ///< -} D18F2x09C_x0D0F_C002_STRUCT; - -// **** D18F2x09C_x0D0F_C006 Register Definition **** -// Address -#define D18F2x09C_x0D0F_C006_ADDRESS 0xd0fc006 - -// Type -#define D18F2x09C_x0D0F_C006_TYPE TYPE_D18F2x09C -// Field Data -#define D18F2x09C_x0D0F_C006_TxPreN_OFFSET 0 -#define D18F2x09C_x0D0F_C006_TxPreN_WIDTH 6 -#define D18F2x09C_x0D0F_C006_TxPreN_MASK 0x3f -#define D18F2x09C_x0D0F_C006_TxPreP_OFFSET 6 -#define D18F2x09C_x0D0F_C006_TxPreP_WIDTH 6 -#define D18F2x09C_x0D0F_C006_TxPreP_MASK 0xfc0 -#define D18F2x09C_x0D0F_C006_Reserved_31_12_OFFSET 12 -#define D18F2x09C_x0D0F_C006_Reserved_31_12_WIDTH 20 -#define D18F2x09C_x0D0F_C006_Reserved_31_12_MASK 0xfffff000 - -/// D18F2x09C_x0D0F_C006 -typedef union { - struct { ///< - UINT32 TxPreN:6 ; ///< - UINT32 TxPreP:6 ; ///< - UINT32 Reserved_31_12:20; ///< - } Field; ///< - UINT32 Value; ///< -} D18F2x09C_x0D0F_C006_STRUCT; - -// **** D18F2x09C_x0D0F_C00A Register Definition **** -// Address -#define D18F2x09C_x0D0F_C00A_ADDRESS 0xd0fc00a - -// Type -#define D18F2x09C_x0D0F_C00A_TYPE TYPE_D18F2x09C -// Field Data -#define D18F2x09C_x0D0F_C00A_TxPreN_OFFSET 0 -#define D18F2x09C_x0D0F_C00A_TxPreN_WIDTH 6 -#define D18F2x09C_x0D0F_C00A_TxPreN_MASK 0x3f -#define D18F2x09C_x0D0F_C00A_TxPreP_OFFSET 6 -#define D18F2x09C_x0D0F_C00A_TxPreP_WIDTH 6 -#define D18F2x09C_x0D0F_C00A_TxPreP_MASK 0xfc0 -#define D18F2x09C_x0D0F_C00A_Reserved_31_12_OFFSET 12 -#define D18F2x09C_x0D0F_C00A_Reserved_31_12_WIDTH 20 -#define D18F2x09C_x0D0F_C00A_Reserved_31_12_MASK 0xfffff000 - -/// D18F2x09C_x0D0F_C00A -typedef union { - struct { ///< - UINT32 TxPreN:6 ; ///< - UINT32 TxPreP:6 ; ///< - UINT32 Reserved_31_12:20; ///< - } Field; ///< - UINT32 Value; ///< -} D18F2x09C_x0D0F_C00A_STRUCT; - -// **** D18F2x09C_x0D0F_C00E Register Definition **** -// Address -#define D18F2x09C_x0D0F_C00E_ADDRESS 0xd0fc00e - -// Type -#define D18F2x09C_x0D0F_C00E_TYPE TYPE_D18F2x09C -// Field Data -#define D18F2x09C_x0D0F_C00E_TxPreN_OFFSET 0 -#define D18F2x09C_x0D0F_C00E_TxPreN_WIDTH 6 -#define D18F2x09C_x0D0F_C00E_TxPreN_MASK 0x3f -#define D18F2x09C_x0D0F_C00E_TxPreP_OFFSET 6 -#define D18F2x09C_x0D0F_C00E_TxPreP_WIDTH 6 -#define D18F2x09C_x0D0F_C00E_TxPreP_MASK 0xfc0 -#define D18F2x09C_x0D0F_C00E_Reserved_31_12_OFFSET 12 -#define D18F2x09C_x0D0F_C00E_Reserved_31_12_WIDTH 20 -#define D18F2x09C_x0D0F_C00E_Reserved_31_12_MASK 0xfffff000 - -/// D18F2x09C_x0D0F_C00E -typedef union { - struct { ///< - UINT32 TxPreN:6 ; ///< - UINT32 TxPreP:6 ; ///< - UINT32 Reserved_31_12:20; ///< - } Field; ///< - UINT32 Value; ///< -} D18F2x09C_x0D0F_C00E_STRUCT; - -// **** D18F2x09C_x0D0F_C012 Register Definition **** -// Address -#define D18F2x09C_x0D0F_C012_ADDRESS 0xd0fc012 - -// Type -#define D18F2x09C_x0D0F_C012_TYPE TYPE_D18F2x09C -// Field Data -#define D18F2x09C_x0D0F_C012_TxPreN_OFFSET 0 -#define D18F2x09C_x0D0F_C012_TxPreN_WIDTH 6 -#define D18F2x09C_x0D0F_C012_TxPreN_MASK 0x3f -#define D18F2x09C_x0D0F_C012_TxPreP_OFFSET 6 -#define D18F2x09C_x0D0F_C012_TxPreP_WIDTH 6 -#define D18F2x09C_x0D0F_C012_TxPreP_MASK 0xfc0 -#define D18F2x09C_x0D0F_C012_Reserved_31_12_OFFSET 12 -#define D18F2x09C_x0D0F_C012_Reserved_31_12_WIDTH 20 -#define D18F2x09C_x0D0F_C012_Reserved_31_12_MASK 0xfffff000 - -/// D18F2x09C_x0D0F_C012 -typedef union { - struct { ///< - UINT32 TxPreN:6 ; ///< - UINT32 TxPreP:6 ; ///< - UINT32 Reserved_31_12:20; ///< - } Field; ///< - UINT32 Value; ///< -} D18F2x09C_x0D0F_C012_STRUCT; - -// **** D18F2x09C_x0D0F_C01F Register Definition **** -// Address -#define D18F2x09C_x0D0F_C01F_ADDRESS 0xd0fc01f - -// Type -#define D18F2x09C_x0D0F_C01F_TYPE TYPE_D18F2x09C -// Field Data -#define D18F2x09C_x0D0F_C01F_Reserved_2_0_OFFSET 0 -#define D18F2x09C_x0D0F_C01F_Reserved_2_0_WIDTH 3 -#define D18F2x09C_x0D0F_C01F_Reserved_2_0_MASK 0x7 -#define D18F2x09C_x0D0F_C01F_RxVioLvl_OFFSET 3 -#define D18F2x09C_x0D0F_C01F_RxVioLvl_WIDTH 2 -#define D18F2x09C_x0D0F_C01F_RxVioLvl_MASK 0x18 -#define D18F2x09C_x0D0F_C01F_Reserved_31_5_OFFSET 5 -#define D18F2x09C_x0D0F_C01F_Reserved_31_5_WIDTH 27 -#define D18F2x09C_x0D0F_C01F_Reserved_31_5_MASK 0xffffffe0 - -/// D18F2x09C_x0D0F_C01F -typedef union { - struct { ///< - UINT32 Reserved_2_0:3 ; ///< - UINT32 RxVioLvl:2 ; ///< - UINT32 Reserved_31_5:27; ///< - } Field; ///< - UINT32 Value; ///< -} D18F2x09C_x0D0F_C01F_STRUCT; - -// **** D18F2x09C_x0D0F_C031 Register Definition **** -// Address -#define D18F2x09C_x0D0F_C031_ADDRESS 0xd0fc031 - -// Type -#define D18F2x09C_x0D0F_C031_TYPE TYPE_D18F2x09C -// Field Data -#define D18F2x09C_x0D0F_C031_Fence2ThresholdTxPad_OFFSET 0 -#define D18F2x09C_x0D0F_C031_Fence2ThresholdTxPad_WIDTH 4 -#define D18F2x09C_x0D0F_C031_Fence2ThresholdTxPad_MASK 0xf -#define D18F2x09C_x0D0F_C031_Fence2EnableTxPad_OFFSET 4 -#define D18F2x09C_x0D0F_C031_Fence2EnableTxPad_WIDTH 1 -#define D18F2x09C_x0D0F_C031_Fence2EnableTxPad_MASK 0x10 -#define D18F2x09C_x0D0F_C031_Reserved_31_5_OFFSET 5 -#define D18F2x09C_x0D0F_C031_Reserved_31_5_WIDTH 27 -#define D18F2x09C_x0D0F_C031_Reserved_31_5_MASK 0xffffffe0 - -/// D18F2x09C_x0D0F_C031 -typedef union { - struct { ///< - UINT32 Fence2ThresholdTxPad:4 ; ///< - UINT32 Fence2EnableTxPad:1 ; ///< - UINT32 Reserved_31_5:27; ///< - } Field; ///< - UINT32 Value; ///< -} D18F2x09C_x0D0F_C031_STRUCT; - -// **** D18F2x09C_x0D0F_E003 Register Definition **** -// Address -#define D18F2x09C_x0D0F_E003_ADDRESS 0xd0fe003 - -// Type -#define D18F2x09C_x0D0F_E003_TYPE TYPE_D18F2x09C -// Field Data -#define D18F2x09C_x0D0F_E003_Reserved_12_0_OFFSET 0 -#define D18F2x09C_x0D0F_E003_Reserved_12_0_WIDTH 13 -#define D18F2x09C_x0D0F_E003_Reserved_12_0_MASK 0x1fff -#define D18F2x09C_x0D0F_E003_DisablePredriverCal_OFFSET 13 -#define D18F2x09C_x0D0F_E003_DisablePredriverCal_WIDTH 1 -#define D18F2x09C_x0D0F_E003_DisablePredriverCal_MASK 0x2000 -#define D18F2x09C_x0D0F_E003_DisAutoComp_OFFSET 14 -#define D18F2x09C_x0D0F_E003_DisAutoComp_WIDTH 1 -#define D18F2x09C_x0D0F_E003_DisAutoComp_MASK 0x4000 -#define D18F2x09C_x0D0F_E003_Reserved_31_15_OFFSET 15 -#define D18F2x09C_x0D0F_E003_Reserved_31_15_WIDTH 17 -#define D18F2x09C_x0D0F_E003_Reserved_31_15_MASK 0xffff8000 - -/// D18F2x09C_x0D0F_E003 -typedef union { - struct { ///< - UINT32 Reserved_12_0:13; ///< - UINT32 DisablePredriverCal:1 ; ///< - UINT32 DisAutoComp:1 ; ///< - UINT32 Reserved_31_15:17; ///< - } Field; ///< - UINT32 Value; ///< -} D18F2x09C_x0D0F_E003_STRUCT; - -// **** D18F2x09C_x0D0F_E006 Register Definition **** -// Address -#define D18F2x09C_x0D0F_E006_ADDRESS 0xd0fe006 - -// Type -#define D18F2x09C_x0D0F_E006_TYPE TYPE_D18F2x09C -// Field Data -#define D18F2x09C_x0D0F_E006_PllLockTime_OFFSET 0 -#define D18F2x09C_x0D0F_E006_PllLockTime_WIDTH 16 -#define D18F2x09C_x0D0F_E006_PllLockTime_MASK 0xffff -#define D18F2x09C_x0D0F_E006_Reserved_31_16_OFFSET 16 -#define D18F2x09C_x0D0F_E006_Reserved_31_16_WIDTH 16 -#define D18F2x09C_x0D0F_E006_Reserved_31_16_MASK 0xffff0000 - -/// D18F2x09C_x0D0F_E006 -typedef union { - struct { ///< - UINT32 PllLockTime:16; ///< - UINT32 Reserved_31_16:16; ///< - } Field; ///< - UINT32 Value; ///< -} D18F2x09C_x0D0F_E006_STRUCT; - -// **** D18F2x09C_x0D0F_E00A Register Definition **** -// Address -#define D18F2x09C_x0D0F_E00A_ADDRESS 0xd0fe00a - -// Type -#define D18F2x09C_x0D0F_E00A_TYPE TYPE_D18F2x09C -// Field Data -#define D18F2x09C_x0D0F_E00A_Reserved_3_0_OFFSET 0 -#define D18F2x09C_x0D0F_E00A_Reserved_3_0_WIDTH 4 -#define D18F2x09C_x0D0F_E00A_Reserved_3_0_MASK 0xf -#define D18F2x09C_x0D0F_E00A_SkewMemClk_OFFSET 4 -#define D18F2x09C_x0D0F_E00A_SkewMemClk_WIDTH 1 -#define D18F2x09C_x0D0F_E00A_SkewMemClk_MASK 0x10 -#define D18F2x09C_x0D0F_E00A_Reserved_11_5_OFFSET 5 -#define D18F2x09C_x0D0F_E00A_Reserved_11_5_WIDTH 7 -#define D18F2x09C_x0D0F_E00A_Reserved_11_5_MASK 0xfe0 -#define D18F2x09C_x0D0F_E00A_CsrPhySrPllPdMode_OFFSET 12 -#define D18F2x09C_x0D0F_E00A_CsrPhySrPllPdMode_WIDTH 2 -#define D18F2x09C_x0D0F_E00A_CsrPhySrPllPdMode_MASK 0x3000 -#define D18F2x09C_x0D0F_E00A_SelCsrPllPdMode_OFFSET 14 -#define D18F2x09C_x0D0F_E00A_SelCsrPllPdMode_WIDTH 1 -#define D18F2x09C_x0D0F_E00A_SelCsrPllPdMode_MASK 0x4000 -#define D18F2x09C_x0D0F_E00A_Reserved_31_15_OFFSET 15 -#define D18F2x09C_x0D0F_E00A_Reserved_31_15_WIDTH 17 -#define D18F2x09C_x0D0F_E00A_Reserved_31_15_MASK 0xffff8000 - -/// D18F2x09C_x0D0F_E00A -typedef union { - struct { ///< - UINT32 Reserved_3_0:4 ; ///< - UINT32 SkewMemClk:1 ; ///< - UINT32 Reserved_11_5:7 ; ///< - UINT32 CsrPhySrPllPdMode:2 ; ///< - UINT32 SelCsrPllPdMode:1 ; ///< - UINT32 Reserved_31_15:17; ///< - } Field; ///< - UINT32 Value; ///< -} D18F2x09C_x0D0F_E00A_STRUCT; - -// **** D18F2x09C_x0D0F_E013 Register Definition **** -// Address -#define D18F2x09C_x0D0F_E013_ADDRESS 0xd0fe013 - -// Type -#define D18F2x09C_x0D0F_E013_TYPE TYPE_D18F2x09C -// Field Data -#define D18F2x09C_x0D0F_E013_PllRegWaitTime_OFFSET 0 -#define D18F2x09C_x0D0F_E013_PllRegWaitTime_WIDTH 16 -#define D18F2x09C_x0D0F_E013_PllRegWaitTime_MASK 0xffff -#define D18F2x09C_x0D0F_E013_Reserved_31_16_OFFSET 16 -#define D18F2x09C_x0D0F_E013_Reserved_31_16_WIDTH 16 -#define D18F2x09C_x0D0F_E013_Reserved_31_16_MASK 0xffff0000 - -/// D18F2x09C_x0D0F_E013 -typedef union { - struct { ///< - UINT32 PllRegWaitTime:16; ///< - UINT32 Reserved_31_16:16; ///< - } Field; ///< - UINT32 Value; ///< -} D18F2x09C_x0D0F_E013_STRUCT; - -// **** D18F2x0F4_x06 Register Definition **** -// Address -#define D18F2x0F4_x06_ADDRESS 0x6 - -// Type -#define D18F2x0F4_x06_TYPE TYPE_D18F2x0F4 -// Field Data -#define D18F2x0F4_x06_TrdrdSD_OFFSET 0 -#define D18F2x0F4_x06_TrdrdSD_WIDTH 4 -#define D18F2x0F4_x06_TrdrdSD_MASK 0xf -#define D18F2x0F4_x06_Reserved_6_4_OFFSET 4 -#define D18F2x0F4_x06_Reserved_6_4_WIDTH 3 -#define D18F2x0F4_x06_Reserved_6_4_MASK 0x70 -#define D18F2x0F4_x06_TrdrdScEn_OFFSET 7 -#define D18F2x0F4_x06_TrdrdScEn_WIDTH 1 -#define D18F2x0F4_x06_TrdrdScEn_MASK 0x80 -#define D18F2x0F4_x06_TwrrdSD_OFFSET 8 -#define D18F2x0F4_x06_TwrrdSD_WIDTH 4 -#define D18F2x0F4_x06_TwrrdSD_MASK 0xf00 -#define D18F2x0F4_x06_Reserved_31_12_OFFSET 12 -#define D18F2x0F4_x06_Reserved_31_12_WIDTH 20 -#define D18F2x0F4_x06_Reserved_31_12_MASK 0xfffff000 - -/// D18F2x0F4_x06 -typedef union { - struct { ///< - UINT32 TrdrdSD:4 ; ///< - UINT32 Reserved_6_4:3 ; ///< - UINT32 TrdrdScEn:1 ; ///< - UINT32 TwrrdSD:4 ; ///< - UINT32 Reserved_31_12:20; ///< - } Field; ///< - UINT32 Value; ///< -} D18F2x0F4_x06_STRUCT; - -// **** D18F2x0F4_x16 Register Definition **** -// Address -#define D18F2x0F4_x16_ADDRESS 0x16 - -// Type -#define D18F2x0F4_x16_TYPE TYPE_D18F2x0F4 -// Field Data -#define D18F2x0F4_x16_TwrwrSD_OFFSET 0 -#define D18F2x0F4_x16_TwrwrSD_WIDTH 4 -#define D18F2x0F4_x16_TwrwrSD_MASK 0xf -#define D18F2x0F4_x16_Reserved_31_4_OFFSET 4 -#define D18F2x0F4_x16_Reserved_31_4_WIDTH 28 -#define D18F2x0F4_x16_Reserved_31_4_MASK 0xfffffff0 - -/// D18F2x0F4_x16 -typedef union { - struct { ///< - UINT32 TwrwrSD:4 ; ///< - UINT32 Reserved_31_4:28; ///< - } Field; ///< - UINT32 Value; ///< -} D18F2x0F4_x16_STRUCT; - -// **** D18F2x0F4_x30 Register Definition **** -// Address -#define D18F2x0F4_x30_ADDRESS 0x30 - -// Type -#define D18F2x0F4_x30_TYPE TYPE_D18F2x0F4 -// Field Data -#define D18F2x0F4_x30_DbeGskFifoNumerator_OFFSET 0 -#define D18F2x0F4_x30_DbeGskFifoNumerator_WIDTH 13 -#define D18F2x0F4_x30_DbeGskFifoNumerator_MASK 0x1fff -#define D18F2x0F4_x30_Reserved_31_13_OFFSET 13 -#define D18F2x0F4_x30_Reserved_31_13_WIDTH 19 -#define D18F2x0F4_x30_Reserved_31_13_MASK 0xffffe000 - -/// D18F2x0F4_x30 -typedef union { - struct { ///< - UINT32 DbeGskFifoNumerator:13; ///< - UINT32 Reserved_31_13:19; ///< - } Field; ///< - UINT32 Value; ///< -} D18F2x0F4_x30_STRUCT; - -// **** D18F2x0F4_x31 Register Definition **** -// Address -#define D18F2x0F4_x31_ADDRESS 0x31 - -// Type -#define D18F2x0F4_x31_TYPE TYPE_D18F2x0F4 -// Field Data -#define D18F2x0F4_x31_DbeGskFifoDenominator_OFFSET 0 -#define D18F2x0F4_x31_DbeGskFifoDenominator_WIDTH 13 -#define D18F2x0F4_x31_DbeGskFifoDenominator_MASK 0x1fff -#define D18F2x0F4_x31_Reserved_31_13_OFFSET 13 -#define D18F2x0F4_x31_Reserved_31_13_WIDTH 19 -#define D18F2x0F4_x31_Reserved_31_13_MASK 0xffffe000 - -/// D18F2x0F4_x31 -typedef union { - struct { ///< - UINT32 DbeGskFifoDenominator:13; ///< - UINT32 Reserved_31_13:19; ///< - } Field; ///< - UINT32 Value; ///< -} D18F2x0F4_x31_STRUCT; - -// **** D18F2x0F4_x32 Register Definition **** -// Address -#define D18F2x0F4_x32_ADDRESS 0x32 - -// Type -#define D18F2x0F4_x32_TYPE TYPE_D18F2x0F4 -// Field Data -#define D18F2x0F4_x32_DataTxFifoSchedDlySlot0_OFFSET 0 -#define D18F2x0F4_x32_DataTxFifoSchedDlySlot0_WIDTH 5 -#define D18F2x0F4_x32_DataTxFifoSchedDlySlot0_MASK 0x1f -#define D18F2x0F4_x32_Reserved_6_5_OFFSET 5 -#define D18F2x0F4_x32_Reserved_6_5_WIDTH 2 -#define D18F2x0F4_x32_Reserved_6_5_MASK 0x60 -#define D18F2x0F4_x32_DataTxFifoSchedDlyNegSlot0_OFFSET 7 -#define D18F2x0F4_x32_DataTxFifoSchedDlyNegSlot0_WIDTH 1 -#define D18F2x0F4_x32_DataTxFifoSchedDlyNegSlot0_MASK 0x80 -#define D18F2x0F4_x32_DataTxFifoSchedDlySlot1_OFFSET 8 -#define D18F2x0F4_x32_DataTxFifoSchedDlySlot1_WIDTH 5 -#define D18F2x0F4_x32_DataTxFifoSchedDlySlot1_MASK 0x1f00 -#define D18F2x0F4_x32_Reserved_14_13_OFFSET 13 -#define D18F2x0F4_x32_Reserved_14_13_WIDTH 2 -#define D18F2x0F4_x32_Reserved_14_13_MASK 0x6000 -#define D18F2x0F4_x32_DataTxFifoSchedDlyNegSlot1_OFFSET 15 -#define D18F2x0F4_x32_DataTxFifoSchedDlyNegSlot1_WIDTH 1 -#define D18F2x0F4_x32_DataTxFifoSchedDlyNegSlot1_MASK 0x8000 -#define D18F2x0F4_x32_Reserved_31_16_OFFSET 16 -#define D18F2x0F4_x32_Reserved_31_16_WIDTH 16 -#define D18F2x0F4_x32_Reserved_31_16_MASK 0xffff0000 - -/// D18F2x0F4_x32 -typedef union { - struct { ///< - UINT32 DataTxFifoSchedDlySlot0:5 ; ///< - UINT32 Reserved_6_5:2 ; ///< - UINT32 DataTxFifoSchedDlyNegSlot0:1 ; ///< - UINT32 DataTxFifoSchedDlySlot1:5 ; ///< - UINT32 Reserved_14_13:2 ; ///< - UINT32 DataTxFifoSchedDlyNegSlot1:1 ; ///< - UINT32 Reserved_31_16:16; ///< - } Field; ///< - UINT32 Value; ///< -} D18F2x0F4_x32_STRUCT; - -// **** D18F2x0F4_x40 Register Definition **** -// Address -#define D18F2x0F4_x40_ADDRESS 0x40 - -// Type -#define D18F2x0F4_x40_TYPE TYPE_D18F2x0F4 -// Field Data -#define D18F2x0F4_x40_Trcd_OFFSET 0 -#define D18F2x0F4_x40_Trcd_WIDTH 4 -#define D18F2x0F4_x40_Trcd_MASK 0xf -#define D18F2x0F4_x40_Reserved_7_4_OFFSET 4 -#define D18F2x0F4_x40_Reserved_7_4_WIDTH 4 -#define D18F2x0F4_x40_Reserved_7_4_MASK 0xf0 -#define D18F2x0F4_x40_Trp_OFFSET 8 -#define D18F2x0F4_x40_Trp_WIDTH 4 -#define D18F2x0F4_x40_Trp_MASK 0xf00 -#define D18F2x0F4_x40_Reserved_15_12_OFFSET 12 -#define D18F2x0F4_x40_Reserved_15_12_WIDTH 4 -#define D18F2x0F4_x40_Reserved_15_12_MASK 0xf000 -#define D18F2x0F4_x40_Tras_OFFSET 16 -#define D18F2x0F4_x40_Tras_WIDTH 5 -#define D18F2x0F4_x40_Tras_MASK 0x1f0000 -#define D18F2x0F4_x40_Reserved_23_21_OFFSET 21 -#define D18F2x0F4_x40_Reserved_23_21_WIDTH 3 -#define D18F2x0F4_x40_Reserved_23_21_MASK 0xe00000 -#define D18F2x0F4_x40_Trc_OFFSET 24 -#define D18F2x0F4_x40_Trc_WIDTH 6 -#define D18F2x0F4_x40_Trc_MASK 0x3f000000 -#define D18F2x0F4_x40_Reserved_31_30_OFFSET 30 -#define D18F2x0F4_x40_Reserved_31_30_WIDTH 2 -#define D18F2x0F4_x40_Reserved_31_30_MASK 0xc0000000 - -/// D18F2x0F4_x40 -typedef union { - struct { ///< - UINT32 Trcd:4 ; ///< - UINT32 Reserved_7_4:4 ; ///< - UINT32 Trp:4 ; ///< - UINT32 Reserved_15_12:4 ; ///< - UINT32 Tras:5 ; ///< - UINT32 Reserved_23_21:3 ; ///< - UINT32 Trc:6 ; ///< - UINT32 Reserved_31_30:2 ; ///< - } Field; ///< - UINT32 Value; ///< -} D18F2x0F4_x40_STRUCT; - -// **** D18F2x0F4_x41 Register Definition **** -// Address -#define D18F2x0F4_x41_ADDRESS 0x41 - -// Type -#define D18F2x0F4_x41_TYPE TYPE_D18F2x0F4 -// Field Data -#define D18F2x0F4_x41_Trtp_OFFSET 0 -#define D18F2x0F4_x41_Trtp_WIDTH 3 -#define D18F2x0F4_x41_Trtp_MASK 0x7 -#define D18F2x0F4_x41_Reserved_7_3_OFFSET 3 -#define D18F2x0F4_x41_Reserved_7_3_WIDTH 5 -#define D18F2x0F4_x41_Reserved_7_3_MASK 0xf8 -#define D18F2x0F4_x41_Trrd_OFFSET 8 -#define D18F2x0F4_x41_Trrd_WIDTH 3 -#define D18F2x0F4_x41_Trrd_MASK 0x700 -#define D18F2x0F4_x41_Reserved_15_11_OFFSET 11 -#define D18F2x0F4_x41_Reserved_15_11_WIDTH 5 -#define D18F2x0F4_x41_Reserved_15_11_MASK 0xf800 -#define D18F2x0F4_x41_Twtr_OFFSET 16 -#define D18F2x0F4_x41_Twtr_WIDTH 3 -#define D18F2x0F4_x41_Twtr_MASK 0x70000 -#define D18F2x0F4_x41_Reserved_31_19_OFFSET 19 -#define D18F2x0F4_x41_Reserved_31_19_WIDTH 13 -#define D18F2x0F4_x41_Reserved_31_19_MASK 0xfff80000 - -/// D18F2x0F4_x41 -typedef union { - struct { ///< - UINT32 Trtp:3 ; ///< - UINT32 Reserved_7_3:5 ; ///< - UINT32 Trrd:3 ; ///< - UINT32 Reserved_15_11:5 ; ///< - UINT32 Twtr:3 ; ///< - UINT32 Reserved_31_19:13; ///< - } Field; ///< - UINT32 Value; ///< -} D18F2x0F4_x41_STRUCT; - -// **** D18F2x0F4_x83 Register Definition **** -// Address -#define D18F2x0F4_x83_ADDRESS 0x83 - -// Type -#define D18F2x0F4_x83_TYPE TYPE_D18F2x0F4 -// Field Data -#define D18F2x0F4_x83_RdOdtTrnOnDly_OFFSET 0 -#define D18F2x0F4_x83_RdOdtTrnOnDly_WIDTH 3 -#define D18F2x0F4_x83_RdOdtTrnOnDly_MASK 0x7 -#define D18F2x0F4_x83_Reserved_3_3_OFFSET 3 -#define D18F2x0F4_x83_Reserved_3_3_WIDTH 1 -#define D18F2x0F4_x83_Reserved_3_3_MASK 0x8 -#define D18F2x0F4_x83_RdOdtOnDuration_OFFSET 4 -#define D18F2x0F4_x83_RdOdtOnDuration_WIDTH 3 -#define D18F2x0F4_x83_RdOdtOnDuration_MASK 0x70 -#define D18F2x0F4_x83_Reserved_7_7_OFFSET 7 -#define D18F2x0F4_x83_Reserved_7_7_WIDTH 1 -#define D18F2x0F4_x83_Reserved_7_7_MASK 0x80 -#define D18F2x0F4_x83_WrOdtTrnOnDly_OFFSET 8 -#define D18F2x0F4_x83_WrOdtTrnOnDly_WIDTH 1 -#define D18F2x0F4_x83_WrOdtTrnOnDly_MASK 0x100 -#define D18F2x0F4_x83_Reserved_11_9_OFFSET 9 -#define D18F2x0F4_x83_Reserved_11_9_WIDTH 3 -#define D18F2x0F4_x83_Reserved_11_9_MASK 0xe00 -#define D18F2x0F4_x83_WrOdtOnDuration_OFFSET 12 -#define D18F2x0F4_x83_WrOdtOnDuration_WIDTH 3 -#define D18F2x0F4_x83_WrOdtOnDuration_MASK 0x7000 -#define D18F2x0F4_x83_Reserved_31_15_OFFSET 15 -#define D18F2x0F4_x83_Reserved_31_15_WIDTH 17 -#define D18F2x0F4_x83_Reserved_31_15_MASK 0xffff8000 - -/// D18F2x0F4_x83 -typedef union { - struct { ///< - UINT32 RdOdtTrnOnDly:3 ; ///< - UINT32 Reserved_3_3:1 ; ///< - UINT32 RdOdtOnDuration:3 ; ///< - UINT32 Reserved_7_7:1 ; ///< - UINT32 WrOdtTrnOnDly:1 ; ///< - UINT32 Reserved_11_9:3 ; ///< - UINT32 WrOdtOnDuration:3 ; ///< - UINT32 Reserved_31_15:17; ///< - } Field; ///< - UINT32 Value; ///< -} D18F2x0F4_x83_STRUCT; - -// **** D18F2x0F4_x180 Register Definition **** -// Address -#define D18F2x0F4_x180_ADDRESS 0x180 - -// Type -#define D18F2x0F4_x180_TYPE TYPE_D18F2x0F4 -// Field Data -#define D18F2x0F4_x180_RdOdtPatCs0_OFFSET 0 -#define D18F2x0F4_x180_RdOdtPatCs0_WIDTH 4 -#define D18F2x0F4_x180_RdOdtPatCs0_MASK 0xf -#define D18F2x0F4_x180_Reserved_7_4_OFFSET 4 -#define D18F2x0F4_x180_Reserved_7_4_WIDTH 4 -#define D18F2x0F4_x180_Reserved_7_4_MASK 0xf0 -#define D18F2x0F4_x180_RdOdtPatCs1_OFFSET 8 -#define D18F2x0F4_x180_RdOdtPatCs1_WIDTH 4 -#define D18F2x0F4_x180_RdOdtPatCs1_MASK 0xf00 -#define D18F2x0F4_x180_Reserved_15_12_OFFSET 12 -#define D18F2x0F4_x180_Reserved_15_12_WIDTH 4 -#define D18F2x0F4_x180_Reserved_15_12_MASK 0xf000 -#define D18F2x0F4_x180_RdOdtPatCs2_OFFSET 16 -#define D18F2x0F4_x180_RdOdtPatCs2_WIDTH 4 -#define D18F2x0F4_x180_RdOdtPatCs2_MASK 0xf0000 -#define D18F2x0F4_x180_Reserved_23_20_OFFSET 20 -#define D18F2x0F4_x180_Reserved_23_20_WIDTH 4 -#define D18F2x0F4_x180_Reserved_23_20_MASK 0xf00000 -#define D18F2x0F4_x180_RdOdtPatCs3_OFFSET 24 -#define D18F2x0F4_x180_RdOdtPatCs3_WIDTH 4 -#define D18F2x0F4_x180_RdOdtPatCs3_MASK 0xf000000 -#define D18F2x0F4_x180_Reserved_31_28_OFFSET 28 -#define D18F2x0F4_x180_Reserved_31_28_WIDTH 4 -#define D18F2x0F4_x180_Reserved_31_28_MASK 0xf0000000 - -/// D18F2x0F4_x180 -typedef union { - struct { ///< - UINT32 RdOdtPatCs0:4 ; ///< - UINT32 Reserved_7_4:4 ; ///< - UINT32 RdOdtPatCs1:4 ; ///< - UINT32 Reserved_15_12:4 ; ///< - UINT32 RdOdtPatCs2:4 ; ///< - UINT32 Reserved_23_20:4 ; ///< - UINT32 RdOdtPatCs3:4 ; ///< - UINT32 Reserved_31_28:4 ; ///< - } Field; ///< - UINT32 Value; ///< -} D18F2x0F4_x180_STRUCT; - -// **** D18F2x0F4_x182 Register Definition **** -// Address -#define D18F2x0F4_x182_ADDRESS 0x182 - -// Type -#define D18F2x0F4_x182_TYPE TYPE_D18F2x0F4 -// Field Data -#define D18F2x0F4_x182_WrOdtPatCs0_OFFSET 0 -#define D18F2x0F4_x182_WrOdtPatCs0_WIDTH 4 -#define D18F2x0F4_x182_WrOdtPatCs0_MASK 0xf -#define D18F2x0F4_x182_Reserved_7_4_OFFSET 4 -#define D18F2x0F4_x182_Reserved_7_4_WIDTH 4 -#define D18F2x0F4_x182_Reserved_7_4_MASK 0xf0 -#define D18F2x0F4_x182_WrOdtPatCs1_OFFSET 8 -#define D18F2x0F4_x182_WrOdtPatCs1_WIDTH 4 -#define D18F2x0F4_x182_WrOdtPatCs1_MASK 0xf00 -#define D18F2x0F4_x182_Reserved_15_12_OFFSET 12 -#define D18F2x0F4_x182_Reserved_15_12_WIDTH 4 -#define D18F2x0F4_x182_Reserved_15_12_MASK 0xf000 -#define D18F2x0F4_x182_WrOdtPatCs2_OFFSET 16 -#define D18F2x0F4_x182_WrOdtPatCs2_WIDTH 4 -#define D18F2x0F4_x182_WrOdtPatCs2_MASK 0xf0000 -#define D18F2x0F4_x182_Reserved_23_20_OFFSET 20 -#define D18F2x0F4_x182_Reserved_23_20_WIDTH 4 -#define D18F2x0F4_x182_Reserved_23_20_MASK 0xf00000 -#define D18F2x0F4_x182_WrOdtPatCs3_OFFSET 24 -#define D18F2x0F4_x182_WrOdtPatCs3_WIDTH 4 -#define D18F2x0F4_x182_WrOdtPatCs3_MASK 0xf000000 -#define D18F2x0F4_x182_Reserved_31_28_OFFSET 28 -#define D18F2x0F4_x182_Reserved_31_28_WIDTH 4 -#define D18F2x0F4_x182_Reserved_31_28_MASK 0xf0000000 - -/// D18F2x0F4_x182 -typedef union { - struct { ///< - UINT32 WrOdtPatCs0:4 ; ///< - UINT32 Reserved_7_4:4 ; ///< - UINT32 WrOdtPatCs1:4 ; ///< - UINT32 Reserved_15_12:4 ; ///< - UINT32 WrOdtPatCs2:4 ; ///< - UINT32 Reserved_23_20:4 ; ///< - UINT32 WrOdtPatCs3:4 ; ///< - UINT32 Reserved_31_28:4 ; ///< - } Field; ///< - UINT32 Value; ///< -} D18F2x0F4_x182_STRUCT; - -// **** D18F2x0F4_x200 Register Definition **** -// Address -#define D18F2x0F4_x200_ADDRESS 0x200 - -// Type -#define D18F2x0F4_x200_TYPE TYPE_D18F2x0F4 -// Field Data -#define D18F2x0F4_x200_Txp_OFFSET 0 -#define D18F2x0F4_x200_Txp_WIDTH 4 -#define D18F2x0F4_x200_Txp_MASK 0xf -#define D18F2x0F4_x200_Reserved_7_4_OFFSET 4 -#define D18F2x0F4_x200_Reserved_7_4_WIDTH 4 -#define D18F2x0F4_x200_Reserved_7_4_MASK 0xf0 -#define D18F2x0F4_x200_Txpdll_OFFSET 8 -#define D18F2x0F4_x200_Txpdll_WIDTH 5 -#define D18F2x0F4_x200_Txpdll_MASK 0x1f00 -#define D18F2x0F4_x200_Reserved_31_13_OFFSET 13 -#define D18F2x0F4_x200_Reserved_31_13_WIDTH 19 -#define D18F2x0F4_x200_Reserved_31_13_MASK 0xffffe000 - -/// D18F2x0F4_x200 -typedef union { - struct { ///< - UINT32 Txp:4 ; ///< - UINT32 Reserved_7_4:4 ; ///< - UINT32 Txpdll:5 ; ///< - UINT32 Reserved_31_13:19; ///< - } Field; ///< - UINT32 Value; ///< -} D18F2x0F4_x200_STRUCT; - -// **** DxF0xE4_x02 Register Definition **** -// Address -#define DxF0xE4_x02_ADDRESS 0x2 - -// Type -#define DxF0xE4_x02_TYPE TYPE_D4F0xE4 -// Field Data -#define DxF0xE4_x02_Reserved_14_0_OFFSET 0 -#define DxF0xE4_x02_Reserved_14_0_WIDTH 15 -#define DxF0xE4_x02_Reserved_14_0_MASK 0x7fff -#define DxF0xE4_x02_RegsLcAllowTxL1Control_OFFSET 15 -#define DxF0xE4_x02_RegsLcAllowTxL1Control_WIDTH 1 -#define DxF0xE4_x02_RegsLcAllowTxL1Control_MASK 0x8000 -#define DxF0xE4_x02_Reserved_31_16_OFFSET 16 -#define DxF0xE4_x02_Reserved_31_16_WIDTH 16 -#define DxF0xE4_x02_Reserved_31_16_MASK 0xffff0000 - -/// DxF0xE4_x02 -typedef union { - struct { ///< - UINT32 Reserved_14_0:15; ///< - UINT32 RegsLcAllowTxL1Control:1 ; ///< - UINT32 Reserved_31_16:16; ///< - } Field; ///< - UINT32 Value; ///< -} DxF0xE4_x02_STRUCT; - -// **** DxF0xE4_x20 Register Definition **** -// Address -#define DxF0xE4_x20_ADDRESS 0x20 - -// Type -#define DxF0xE4_x20_TYPE TYPE_D4F0xE4 -// Field Data -#define DxF0xE4_x20_Reserved_14_0_OFFSET 0 -#define DxF0xE4_x20_Reserved_14_0_WIDTH 15 -#define DxF0xE4_x20_Reserved_14_0_MASK 0x7fff -#define DxF0xE4_x20_TxFlushTlpDis_OFFSET 15 -#define DxF0xE4_x20_TxFlushTlpDis_WIDTH 1 -#define DxF0xE4_x20_TxFlushTlpDis_MASK 0x8000 -#define DxF0xE4_x20_Reserved_31_16_OFFSET 16 -#define DxF0xE4_x20_Reserved_31_16_WIDTH 16 -#define DxF0xE4_x20_Reserved_31_16_MASK 0xffff0000 - -/// DxF0xE4_x20 -typedef union { - struct { ///< - UINT32 Reserved_14_0:15; ///< - UINT32 TxFlushTlpDis:1 ; ///< - UINT32 Reserved_31_16:16; ///< - } Field; ///< - UINT32 Value; ///< -} DxF0xE4_x20_STRUCT; - -// **** DxF0xE4_x50 Register Definition **** -// Address -#define DxF0xE4_x50_ADDRESS 0x50 - -// Type -#define DxF0xE4_x50_TYPE TYPE_D4F0xE4 -// Field Data -#define DxF0xE4_x50_PortLaneReversal_OFFSET 0 -#define DxF0xE4_x50_PortLaneReversal_WIDTH 1 -#define DxF0xE4_x50_PortLaneReversal_MASK 0x1 -#define DxF0xE4_x50_PhyLinkWidth_OFFSET 1 -#define DxF0xE4_x50_PhyLinkWidth_WIDTH 6 -#define DxF0xE4_x50_PhyLinkWidth_MASK 0x7e -#define DxF0xE4_x50_Reserved_31_7_OFFSET 7 -#define DxF0xE4_x50_Reserved_31_7_WIDTH 25 -#define DxF0xE4_x50_Reserved_31_7_MASK 0xffffff80 - -/// DxF0xE4_x50 -typedef union { - struct { ///< - UINT32 PortLaneReversal:1 ; ///< - UINT32 PhyLinkWidth:6 ; ///< - UINT32 Reserved_31_7:25; ///< - } Field; ///< - UINT32 Value; ///< -} DxF0xE4_x50_STRUCT; - -// **** DxF0xE4_x70 Register Definition **** -// Address -#define DxF0xE4_x70_ADDRESS 0x70 - -// Type -#define DxF0xE4_x70_TYPE TYPE_D4F0xE4 -// Field Data -#define DxF0xE4_x70_Reserved_15_0_OFFSET 0 -#define DxF0xE4_x70_Reserved_15_0_WIDTH 16 -#define DxF0xE4_x70_Reserved_15_0_MASK 0xffff -#define DxF0xE4_x70_RxRcbCplTimeout_OFFSET 16 -#define DxF0xE4_x70_RxRcbCplTimeout_WIDTH 3 -#define DxF0xE4_x70_RxRcbCplTimeout_MASK 0x70000 -#define DxF0xE4_x70_RxRcbCplTimeoutMode_OFFSET 19 -#define DxF0xE4_x70_RxRcbCplTimeoutMode_WIDTH 1 -#define DxF0xE4_x70_RxRcbCplTimeoutMode_MASK 0x80000 -#define DxF0xE4_x70_Reserved_31_20_OFFSET 20 -#define DxF0xE4_x70_Reserved_31_20_WIDTH 12 -#define DxF0xE4_x70_Reserved_31_20_MASK 0xfff00000 - -/// DxF0xE4_x70 -typedef union { - struct { ///< - UINT32 Reserved_15_0:16; ///< - UINT32 RxRcbCplTimeout:3 ; ///< - UINT32 RxRcbCplTimeoutMode:1 ; ///< - UINT32 Reserved_31_20:12; ///< - } Field; ///< - UINT32 Value; ///< -} DxF0xE4_x70_STRUCT; - -// **** DxF0xE4_xA0 Register Definition **** -// Address -#define DxF0xE4_xA0_ADDRESS 0xa0 - -// Type -#define DxF0xE4_xA0_TYPE TYPE_D4F0xE4 -// Field Data -#define DxF0xE4_xA0_Reserved_3_0_OFFSET 0 -#define DxF0xE4_xA0_Reserved_3_0_WIDTH 4 -#define DxF0xE4_xA0_Reserved_3_0_MASK 0xf -#define DxF0xE4_xA0_Lc16xClearTxPipe_OFFSET 4 -#define DxF0xE4_xA0_Lc16xClearTxPipe_WIDTH 4 -#define DxF0xE4_xA0_Lc16xClearTxPipe_MASK 0xf0 -#define DxF0xE4_xA0_LcL0sInactivity_OFFSET 8 -#define DxF0xE4_xA0_LcL0sInactivity_WIDTH 4 -#define DxF0xE4_xA0_LcL0sInactivity_MASK 0xf00 -#define DxF0xE4_xA0_LcL1Inactivity_OFFSET 12 -#define DxF0xE4_xA0_LcL1Inactivity_WIDTH 4 -#define DxF0xE4_xA0_LcL1Inactivity_MASK 0xf000 -#define DxF0xE4_xA0_Reserved_22_16_OFFSET 16 -#define DxF0xE4_xA0_Reserved_22_16_WIDTH 7 -#define DxF0xE4_xA0_Reserved_22_16_MASK 0x7f0000 -#define DxF0xE4_xA0_LcL1ImmediateAck_OFFSET 23 -#define DxF0xE4_xA0_LcL1ImmediateAck_WIDTH 1 -#define DxF0xE4_xA0_LcL1ImmediateAck_MASK 0x800000 -#define DxF0xE4_xA0_Reserved_31_24_OFFSET 24 -#define DxF0xE4_xA0_Reserved_31_24_WIDTH 8 -#define DxF0xE4_xA0_Reserved_31_24_MASK 0xff000000 - -/// DxF0xE4_xA0 -typedef union { - struct { ///< - UINT32 Reserved_3_0:4 ; ///< - UINT32 Lc16xClearTxPipe:4 ; ///< - UINT32 LcL0sInactivity:4 ; ///< - UINT32 LcL1Inactivity:4 ; ///< - UINT32 Reserved_22_16:7 ; ///< - UINT32 LcL1ImmediateAck:1 ; ///< - UINT32 Reserved_31_24:8 ; ///< - } Field; ///< - UINT32 Value; ///< -} DxF0xE4_xA0_STRUCT; - -// **** DxF0xE4_xA1 Register Definition **** -// Address -#define DxF0xE4_xA1_ADDRESS 0xa1 - -// Type -#define DxF0xE4_xA1_TYPE TYPE_D4F0xE4 -// Field Data -#define DxF0xE4_xA1_Reserved_10_0_OFFSET 0 -#define DxF0xE4_xA1_Reserved_10_0_WIDTH 11 -#define DxF0xE4_xA1_Reserved_10_0_MASK 0x7ff -#define DxF0xE4_xA1_LcDontGotoL0sifL1Armed_OFFSET 11 -#define DxF0xE4_xA1_LcDontGotoL0sifL1Armed_WIDTH 1 -#define DxF0xE4_xA1_LcDontGotoL0sifL1Armed_MASK 0x800 -#define DxF0xE4_xA1_LcInitSpdChgWithCsrEn_OFFSET 12 -#define DxF0xE4_xA1_LcInitSpdChgWithCsrEn_WIDTH 1 -#define DxF0xE4_xA1_LcInitSpdChgWithCsrEn_MASK 0x1000 -#define DxF0xE4_xA1_Reserved_31_13_OFFSET 13 -#define DxF0xE4_xA1_Reserved_31_13_WIDTH 19 -#define DxF0xE4_xA1_Reserved_31_13_MASK 0xffffe000 - -/// DxF0xE4_xA1 -typedef union { - struct { ///< - UINT32 Reserved_10_0:11; ///< - UINT32 LcDontGotoL0sifL1Armed:1 ; ///< - UINT32 LcInitSpdChgWithCsrEn:1 ; ///< - UINT32 Reserved_31_13:19; ///< - } Field; ///< - UINT32 Value; ///< -} DxF0xE4_xA1_STRUCT; - -// **** DxF0xE4_xA2 Register Definition **** -// Address -#define DxF0xE4_xA2_ADDRESS 0xa2 - -// Type -#define DxF0xE4_xA2_TYPE TYPE_D4F0xE4 -// Field Data -#define DxF0xE4_xA2_LcLinkWidth_OFFSET 0 -#define DxF0xE4_xA2_LcLinkWidth_WIDTH 3 -#define DxF0xE4_xA2_LcLinkWidth_MASK 0x7 -#define DxF0xE4_xA2_Reserved_3_3_OFFSET 3 -#define DxF0xE4_xA2_Reserved_3_3_WIDTH 1 -#define DxF0xE4_xA2_Reserved_3_3_MASK 0x8 -#define DxF0xE4_xA2_LcLinkWidthRd_OFFSET 4 -#define DxF0xE4_xA2_LcLinkWidthRd_WIDTH 3 -#define DxF0xE4_xA2_LcLinkWidthRd_MASK 0x70 -#define DxF0xE4_xA2_LcReconfigArcMissingEscape_OFFSET 7 -#define DxF0xE4_xA2_LcReconfigArcMissingEscape_WIDTH 1 -#define DxF0xE4_xA2_LcReconfigArcMissingEscape_MASK 0x80 -#define DxF0xE4_xA2_LcReconfigNow_OFFSET 8 -#define DxF0xE4_xA2_LcReconfigNow_WIDTH 1 -#define DxF0xE4_xA2_LcReconfigNow_MASK 0x100 -#define DxF0xE4_xA2_LcRenegotiationSupport_OFFSET 9 -#define DxF0xE4_xA2_LcRenegotiationSupport_WIDTH 1 -#define DxF0xE4_xA2_LcRenegotiationSupport_MASK 0x200 -#define DxF0xE4_xA2_LcRenegotiateEn_OFFSET 10 -#define DxF0xE4_xA2_LcRenegotiateEn_WIDTH 1 -#define DxF0xE4_xA2_LcRenegotiateEn_MASK 0x400 -#define DxF0xE4_xA2_LcShortReconfigEn_OFFSET 11 -#define DxF0xE4_xA2_LcShortReconfigEn_WIDTH 1 -#define DxF0xE4_xA2_LcShortReconfigEn_MASK 0x800 -#define DxF0xE4_xA2_LcUpconfigureSupport_OFFSET 12 -#define DxF0xE4_xA2_LcUpconfigureSupport_WIDTH 1 -#define DxF0xE4_xA2_LcUpconfigureSupport_MASK 0x1000 -#define DxF0xE4_xA2_LcUpconfigureDis_OFFSET 13 -#define DxF0xE4_xA2_LcUpconfigureDis_WIDTH 1 -#define DxF0xE4_xA2_LcUpconfigureDis_MASK 0x2000 -#define DxF0xE4_xA2_Reserved_19_14_OFFSET 14 -#define DxF0xE4_xA2_Reserved_19_14_WIDTH 6 -#define DxF0xE4_xA2_Reserved_19_14_MASK 0xfc000 -#define DxF0xE4_xA2_LcUpconfigCapable_OFFSET 20 -#define DxF0xE4_xA2_LcUpconfigCapable_WIDTH 1 -#define DxF0xE4_xA2_LcUpconfigCapable_MASK 0x100000 -#define DxF0xE4_xA2_LcDynLanesPwrState_OFFSET 21 -#define DxF0xE4_xA2_LcDynLanesPwrState_WIDTH 2 -#define DxF0xE4_xA2_LcDynLanesPwrState_MASK 0x600000 -#define DxF0xE4_xA2_Reserved_31_23_OFFSET 23 -#define DxF0xE4_xA2_Reserved_31_23_WIDTH 9 -#define DxF0xE4_xA2_Reserved_31_23_MASK 0xff800000 - -/// DxF0xE4_xA2 -typedef union { - struct { ///< - UINT32 LcLinkWidth:3 ; ///< - UINT32 Reserved_3_3:1 ; ///< - UINT32 LcLinkWidthRd:3 ; ///< - UINT32 LcReconfigArcMissingEscape:1 ; ///< - UINT32 LcReconfigNow:1 ; ///< - UINT32 LcRenegotiationSupport:1 ; ///< - UINT32 LcRenegotiateEn:1 ; ///< - UINT32 LcShortReconfigEn:1 ; ///< - UINT32 LcUpconfigureSupport:1 ; ///< - UINT32 LcUpconfigureDis:1 ; ///< - UINT32 Reserved_19_14:6 ; ///< - UINT32 LcUpconfigCapable:1 ; ///< - UINT32 LcDynLanesPwrState:2 ; ///< - UINT32 Reserved_31_23:9 ; ///< - } Field; ///< - UINT32 Value; ///< -} DxF0xE4_xA2_STRUCT; - -// **** DxF0xE4_xA3 Register Definition **** -// Address -#define DxF0xE4_xA3_ADDRESS 0xa3 - -// Type -#define DxF0xE4_xA3_TYPE TYPE_D4F0xE4 -// Field Data -#define DxF0xE4_xA3_Reserved_8_0_OFFSET 0 -#define DxF0xE4_xA3_Reserved_8_0_WIDTH 9 -#define DxF0xE4_xA3_Reserved_8_0_MASK 0x1ff -#define DxF0xE4_xA3_LcXmitFtsBeforeRecovery_OFFSET 9 -#define DxF0xE4_xA3_LcXmitFtsBeforeRecovery_WIDTH 1 -#define DxF0xE4_xA3_LcXmitFtsBeforeRecovery_MASK 0x200 -#define DxF0xE4_xA3_Reserved_31_10_OFFSET 10 -#define DxF0xE4_xA3_Reserved_31_10_WIDTH 22 -#define DxF0xE4_xA3_Reserved_31_10_MASK 0xfffffc00 - -/// DxF0xE4_xA3 -typedef union { - struct { ///< - UINT32 Reserved_8_0:9 ; ///< - UINT32 LcXmitFtsBeforeRecovery:1 ; ///< - UINT32 Reserved_31_10:22; ///< - } Field; ///< - UINT32 Value; ///< -} DxF0xE4_xA3_STRUCT; - -// **** DxF0xE4_xA4 Register Definition **** -// Address -#define DxF0xE4_xA4_ADDRESS 0xa4 - -// Type -#define DxF0xE4_xA4_TYPE TYPE_D4F0xE4 -// Field Data -#define DxF0xE4_xA4_LcGen2EnStrap_OFFSET 0 -#define DxF0xE4_xA4_LcGen2EnStrap_WIDTH 1 -#define DxF0xE4_xA4_LcGen2EnStrap_MASK 0x1 -#define DxF0xE4_xA4_Reserved_3_1_OFFSET 1 -#define DxF0xE4_xA4_Reserved_3_1_WIDTH 3 -#define DxF0xE4_xA4_Reserved_3_1_MASK 0xe -#define DxF0xE4_xA4_LcForceDisSwSpeedChange_OFFSET 4 -#define DxF0xE4_xA4_LcForceDisSwSpeedChange_WIDTH 1 -#define DxF0xE4_xA4_LcForceDisSwSpeedChange_MASK 0x10 -#define DxF0xE4_xA4_Reserved_6_5_OFFSET 5 -#define DxF0xE4_xA4_Reserved_6_5_WIDTH 2 -#define DxF0xE4_xA4_Reserved_6_5_MASK 0x60 -#define DxF0xE4_xA4_LcInitiateLinkSpeedChange_OFFSET 7 -#define DxF0xE4_xA4_LcInitiateLinkSpeedChange_WIDTH 1 -#define DxF0xE4_xA4_LcInitiateLinkSpeedChange_MASK 0x80 -#define DxF0xE4_xA4_Reserved_9_8_OFFSET 8 -#define DxF0xE4_xA4_Reserved_9_8_WIDTH 2 -#define DxF0xE4_xA4_Reserved_9_8_MASK 0x300 -#define DxF0xE4_xA4_LcSpeedChangeAttemptFailed_OFFSET 10 -#define DxF0xE4_xA4_LcSpeedChangeAttemptFailed_WIDTH 1 -#define DxF0xE4_xA4_LcSpeedChangeAttemptFailed_MASK 0x400 -#define DxF0xE4_xA4_Reserved_17_11_OFFSET 11 -#define DxF0xE4_xA4_Reserved_17_11_WIDTH 7 -#define DxF0xE4_xA4_Reserved_17_11_MASK 0x3f800 -#define DxF0xE4_xA4_LcGoToRecovery_OFFSET 18 -#define DxF0xE4_xA4_LcGoToRecovery_WIDTH 1 -#define DxF0xE4_xA4_LcGoToRecovery_MASK 0x40000 -#define DxF0xE4_xA4_Reserved_23_19_OFFSET 19 -#define DxF0xE4_xA4_Reserved_23_19_WIDTH 5 -#define DxF0xE4_xA4_Reserved_23_19_MASK 0xf80000 -#define DxF0xE4_xA4_LcOtherSideSupportsGen2_OFFSET 24 -#define DxF0xE4_xA4_LcOtherSideSupportsGen2_WIDTH 1 -#define DxF0xE4_xA4_LcOtherSideSupportsGen2_MASK 0x1000000 -#define DxF0xE4_xA4_Reserved_28_25_OFFSET 25 -#define DxF0xE4_xA4_Reserved_28_25_WIDTH 4 -#define DxF0xE4_xA4_Reserved_28_25_MASK 0x1e000000 -#define DxF0xE4_xA4_LcMultUpstreamAutoSpdChngEn_OFFSET 29 -#define DxF0xE4_xA4_LcMultUpstreamAutoSpdChngEn_WIDTH 1 -#define DxF0xE4_xA4_LcMultUpstreamAutoSpdChngEn_MASK 0x20000000 -#define DxF0xE4_xA4_Reserved_31_30_OFFSET 30 -#define DxF0xE4_xA4_Reserved_31_30_WIDTH 2 -#define DxF0xE4_xA4_Reserved_31_30_MASK 0xc0000000 - -/// DxF0xE4_xA4 -typedef union { - struct { ///< - UINT32 LcGen2EnStrap:1 ; ///< - UINT32 Reserved_3_1:3 ; ///< - UINT32 LcForceDisSwSpeedChange:1 ; ///< - UINT32 Reserved_6_5:2 ; ///< - UINT32 LcInitiateLinkSpeedChange:1 ; ///< - UINT32 Reserved_9_8:2 ; ///< - UINT32 LcSpeedChangeAttemptFailed:1 ; ///< - UINT32 Reserved_17_11:7 ; ///< - UINT32 LcGoToRecovery:1 ; ///< - UINT32 Reserved_23_19:5 ; ///< - UINT32 LcOtherSideSupportsGen2:1 ; ///< - UINT32 Reserved_28_25:4 ; ///< - UINT32 LcMultUpstreamAutoSpdChngEn:1 ; ///< - UINT32 Reserved_31_30:2 ; ///< - } Field; ///< - UINT32 Value; ///< -} DxF0xE4_xA4_STRUCT; - -// **** DxF0xE4_xA5 Register Definition **** -// Address -#define DxF0xE4_xA5_ADDRESS 0xa5 - -// Type -#define DxF0xE4_xA5_TYPE TYPE_D4F0xE4 -// Field Data -#define DxF0xE4_xA5_LcCurrentState_OFFSET 0 -#define DxF0xE4_xA5_LcCurrentState_WIDTH 6 -#define DxF0xE4_xA5_LcCurrentState_MASK 0x3f -#define DxF0xE4_xA5_Reserved_7_6_OFFSET 6 -#define DxF0xE4_xA5_Reserved_7_6_WIDTH 2 -#define DxF0xE4_xA5_Reserved_7_6_MASK 0xc0 -#define DxF0xE4_xA5_LcPrevState1_OFFSET 8 -#define DxF0xE4_xA5_LcPrevState1_WIDTH 6 -#define DxF0xE4_xA5_LcPrevState1_MASK 0x3f00 -#define DxF0xE4_xA5_Reserved_15_14_OFFSET 14 -#define DxF0xE4_xA5_Reserved_15_14_WIDTH 2 -#define DxF0xE4_xA5_Reserved_15_14_MASK 0xc000 -#define DxF0xE4_xA5_LcPrevState2_OFFSET 16 -#define DxF0xE4_xA5_LcPrevState2_WIDTH 6 -#define DxF0xE4_xA5_LcPrevState2_MASK 0x3f0000 -#define DxF0xE4_xA5_Reserved_23_22_OFFSET 22 -#define DxF0xE4_xA5_Reserved_23_22_WIDTH 2 -#define DxF0xE4_xA5_Reserved_23_22_MASK 0xc00000 -#define DxF0xE4_xA5_LcPrevState3_OFFSET 24 -#define DxF0xE4_xA5_LcPrevState3_WIDTH 6 -#define DxF0xE4_xA5_LcPrevState3_MASK 0x3f000000 -#define DxF0xE4_xA5_Reserved_31_30_OFFSET 30 -#define DxF0xE4_xA5_Reserved_31_30_WIDTH 2 -#define DxF0xE4_xA5_Reserved_31_30_MASK 0xc0000000 - -/// DxF0xE4_xA5 -typedef union { - struct { ///< - UINT32 LcCurrentState:6 ; ///< - UINT32 Reserved_7_6:2 ; ///< - UINT32 LcPrevState1:6 ; ///< - UINT32 Reserved_15_14:2 ; ///< - UINT32 LcPrevState2:6 ; ///< - UINT32 Reserved_23_22:2 ; ///< - UINT32 LcPrevState3:6 ; ///< - UINT32 Reserved_31_30:2 ; ///< - } Field; ///< - UINT32 Value; ///< -} DxF0xE4_xA5_STRUCT; - -// **** DxF0xE4_xB1 Register Definition **** -// Address -#define DxF0xE4_xB1_ADDRESS 0xb1 - -// Type -#define DxF0xE4_xB1_TYPE TYPE_D4F0xE4 -// Field Data -#define DxF0xE4_xB1_Reserved_18_0_OFFSET 0 -#define DxF0xE4_xB1_Reserved_18_0_WIDTH 19 -#define DxF0xE4_xB1_Reserved_18_0_MASK 0x7ffff -#define DxF0xE4_xB1_LcDeassertRxEnInL0s_OFFSET 19 -#define DxF0xE4_xB1_LcDeassertRxEnInL0s_WIDTH 1 -#define DxF0xE4_xB1_LcDeassertRxEnInL0s_MASK 0x80000 -#define DxF0xE4_xB1_LcBlockElIdleinL0_OFFSET 20 -#define DxF0xE4_xB1_LcBlockElIdleinL0_WIDTH 1 -#define DxF0xE4_xB1_LcBlockElIdleinL0_MASK 0x100000 -#define DxF0xE4_xB1_Reserved_31_21_OFFSET 21 -#define DxF0xE4_xB1_Reserved_31_21_WIDTH 11 -#define DxF0xE4_xB1_Reserved_31_21_MASK 0xffe00000 - -/// DxF0xE4_xB1 -typedef union { - struct { ///< - UINT32 Reserved_18_0:19; ///< - UINT32 LcDeassertRxEnInL0s:1 ; ///< - UINT32 LcBlockElIdleinL0:1 ; ///< - UINT32 Reserved_31_21:11; ///< - } Field; ///< - UINT32 Value; ///< -} DxF0xE4_xB1_STRUCT; - -// **** DxF0xE4_xC0 Register Definition **** -// Address -#define DxF0xE4_xC0_ADDRESS 0xc0 - -// Type -#define DxF0xE4_xC0_TYPE TYPE_D4F0xE4 -// Field Data -#define DxF0xE4_xC0_Reserved_12_0_OFFSET 0 -#define DxF0xE4_xC0_Reserved_12_0_WIDTH 13 -#define DxF0xE4_xC0_Reserved_12_0_MASK 0x1fff -#define DxF0xE4_xC0_StrapForceCompliance_OFFSET 13 -#define DxF0xE4_xC0_StrapForceCompliance_WIDTH 1 -#define DxF0xE4_xC0_StrapForceCompliance_MASK 0x2000 -#define DxF0xE4_xC0_Reserved_14_14_OFFSET 14 -#define DxF0xE4_xC0_Reserved_14_14_WIDTH 1 -#define DxF0xE4_xC0_Reserved_14_14_MASK 0x4000 -#define DxF0xE4_xC0_StrapAutoRcSpeedNegotiationDis_OFFSET 15 -#define DxF0xE4_xC0_StrapAutoRcSpeedNegotiationDis_WIDTH 1 -#define DxF0xE4_xC0_StrapAutoRcSpeedNegotiationDis_MASK 0x8000 -#define DxF0xE4_xC0_Reserved_31_16_OFFSET 16 -#define DxF0xE4_xC0_Reserved_31_16_WIDTH 16 -#define DxF0xE4_xC0_Reserved_31_16_MASK 0xffff0000 - -/// DxF0xE4_xC0 -typedef union { - struct { ///< - UINT32 Reserved_12_0:13; ///< - UINT32 StrapForceCompliance:1 ; ///< - UINT32 Reserved_14_14:1 ; ///< - UINT32 StrapAutoRcSpeedNegotiationDis:1 ; ///< - UINT32 Reserved_31_16:16; ///< - } Field; ///< - UINT32 Value; ///< -} DxF0xE4_xC0_STRUCT; - -// **** DxF0xE4_xC1 Register Definition **** -// Address -#define DxF0xE4_xC1_ADDRESS 0xc1 - -// Type -#define DxF0xE4_xC1_TYPE TYPE_D4F0xE4 -// Field Data -#define DxF0xE4_xC1_Reserved_3_0_OFFSET 0 -#define DxF0xE4_xC1_Reserved_3_0_WIDTH 4 -#define DxF0xE4_xC1_Reserved_3_0_MASK 0xf -#define DxF0xE4_xC1_StrapReverseLanes_OFFSET 4 -#define DxF0xE4_xC1_StrapReverseLanes_WIDTH 1 -#define DxF0xE4_xC1_StrapReverseLanes_MASK 0x10 -#define DxF0xE4_xC1_Reserved_31_5_OFFSET 5 -#define DxF0xE4_xC1_Reserved_31_5_WIDTH 27 -#define DxF0xE4_xC1_Reserved_31_5_MASK 0xffffffe0 - -/// DxF0xE4_xC1 -typedef union { - struct { ///< - UINT32 Reserved_3_0:4 ; ///< - UINT32 StrapReverseLanes:1 ; ///< - UINT32 Reserved_31_5:27; ///< - } Field; ///< - UINT32 Value; ///< -} DxF0xE4_xC1_STRUCT; - -// **** SMUx0B_x830C Register Definition **** -// Address -#define SMUx0B_x830C_ADDRESS 0x830c - -// Type -#define SMUx0B_x830C_TYPE TYPE_SMUx0B -// Field Data -#define SMUx0B_x830C_MinorVersion_OFFSET 0 -#define SMUx0B_x830C_MinorVersion_WIDTH 16 -#define SMUx0B_x830C_MinorVersion_MASK 0xffff -#define SMUx0B_x830C_MajorVersion_OFFSET 16 -#define SMUx0B_x830C_MajorVersion_WIDTH 16 -#define SMUx0B_x830C_MajorVersion_MASK 0xffff0000 - -/// SMUx0B_x830C -typedef union { - struct { ///< - UINT32 MinorVersion:16; ///< - UINT32 MajorVersion:16; ///< - } Field; ///< - UINT32 Value; ///< -} SMUx0B_x830C_STRUCT; - -// **** SMUx0B_x8408 Register Definition **** -// Address -#define SMUx0B_x8408_ADDRESS 0x8408 - -// Type -#define SMUx0B_x8408_TYPE TYPE_SMUx0B -// Field Data -#define SMUx0B_x8408_PsoControlId0_OFFSET 0 -#define SMUx0B_x8408_PsoControlId0_WIDTH 4 -#define SMUx0B_x8408_PsoControlId0_MASK 0xf -#define SMUx0B_x8408_PsoControlId1_OFFSET 4 -#define SMUx0B_x8408_PsoControlId1_WIDTH 4 -#define SMUx0B_x8408_PsoControlId1_MASK 0xf0 -#define SMUx0B_x8408_PsoControlId2_OFFSET 8 -#define SMUx0B_x8408_PsoControlId2_WIDTH 4 -#define SMUx0B_x8408_PsoControlId2_MASK 0xf00 -#define SMUx0B_x8408_PsoControlId3_OFFSET 12 -#define SMUx0B_x8408_PsoControlId3_WIDTH 4 -#define SMUx0B_x8408_PsoControlId3_MASK 0xf000 -#define SMUx0B_x8408_PsoControlId4_OFFSET 16 -#define SMUx0B_x8408_PsoControlId4_WIDTH 4 -#define SMUx0B_x8408_PsoControlId4_MASK 0xf0000 -#define SMUx0B_x8408_PsoControlId5_OFFSET 20 -#define SMUx0B_x8408_PsoControlId5_WIDTH 4 -#define SMUx0B_x8408_PsoControlId5_MASK 0xf00000 -#define SMUx0B_x8408_PsoControlId6_OFFSET 24 -#define SMUx0B_x8408_PsoControlId6_WIDTH 4 -#define SMUx0B_x8408_PsoControlId6_MASK 0xf000000 -#define SMUx0B_x8408_PsoControlId7_OFFSET 28 -#define SMUx0B_x8408_PsoControlId7_WIDTH 4 -#define SMUx0B_x8408_PsoControlId7_MASK 0xf0000000 - -/// SMUx0B_x8408 -typedef union { - struct { ///< - UINT32 PsoControlId0:4 ; ///< - UINT32 PsoControlId1:4 ; ///< - UINT32 PsoControlId2:4 ; ///< - UINT32 PsoControlId3:4 ; ///< - UINT32 PsoControlId4:4 ; ///< - UINT32 PsoControlId5:4 ; ///< - UINT32 PsoControlId6:4 ; ///< - UINT32 PsoControlId7:4 ; ///< - } Field; ///< - UINT32 Value; ///< -} SMUx0B_x8408_STRUCT; - -// **** SMUx0B_x840C Register Definition **** -// Address -#define SMUx0B_x840C_ADDRESS 0x840c - -// Type -#define SMUx0B_x840C_TYPE TYPE_SMUx0B -// Field Data -#define SMUx0B_x840C_PsoControlId8_OFFSET 0 -#define SMUx0B_x840C_PsoControlId8_WIDTH 4 -#define SMUx0B_x840C_PsoControlId8_MASK 0xf -#define SMUx0B_x840C_PsoControlId9_OFFSET 4 -#define SMUx0B_x840C_PsoControlId9_WIDTH 4 -#define SMUx0B_x840C_PsoControlId9_MASK 0xf0 -#define SMUx0B_x840C_PsoControlId10_OFFSET 8 -#define SMUx0B_x840C_PsoControlId10_WIDTH 4 -#define SMUx0B_x840C_PsoControlId10_MASK 0xf00 -#define SMUx0B_x840C_PsoControlId11_OFFSET 12 -#define SMUx0B_x840C_PsoControlId11_WIDTH 4 -#define SMUx0B_x840C_PsoControlId11_MASK 0xf000 -#define SMUx0B_x840C_PsoControlId12_OFFSET 16 -#define SMUx0B_x840C_PsoControlId12_WIDTH 4 -#define SMUx0B_x840C_PsoControlId12_MASK 0xf0000 -#define SMUx0B_x840C_PsoControlId13_OFFSET 20 -#define SMUx0B_x840C_PsoControlId13_WIDTH 4 -#define SMUx0B_x840C_PsoControlId13_MASK 0xf00000 -#define SMUx0B_x840C_PsoControlId14_OFFSET 24 -#define SMUx0B_x840C_PsoControlId14_WIDTH 4 -#define SMUx0B_x840C_PsoControlId14_MASK 0xf000000 -#define SMUx0B_x840C_PsoControlId15_OFFSET 28 -#define SMUx0B_x840C_PsoControlId15_WIDTH 4 -#define SMUx0B_x840C_PsoControlId15_MASK 0xf0000000 - -/// SMUx0B_x840C -typedef union { - struct { ///< - UINT32 PsoControlId8:4 ; ///< - UINT32 PsoControlId9:4 ; ///< - UINT32 PsoControlId10:4 ; ///< - UINT32 PsoControlId11:4 ; ///< - UINT32 PsoControlId12:4 ; ///< - UINT32 PsoControlId13:4 ; ///< - UINT32 PsoControlId14:4 ; ///< - UINT32 PsoControlId15:4 ; ///< - } Field; ///< - UINT32 Value; ///< -} SMUx0B_x840C_STRUCT; - -// **** SMUx0B_x8410 Register Definition **** -// Address -#define SMUx0B_x8410_ADDRESS 0x8410 - -// Type -#define SMUx0B_x8410_TYPE TYPE_SMUx0B -// Field Data -#define SMUx0B_x8410_PwrGatingEn_OFFSET 0 -#define SMUx0B_x8410_PwrGatingEn_WIDTH 1 -#define SMUx0B_x8410_PwrGatingEn_MASK 0x1 -#define SMUx0B_x8410_Reserved_2_1_OFFSET 1 -#define SMUx0B_x8410_Reserved_2_1_WIDTH 2 -#define SMUx0B_x8410_Reserved_2_1_MASK 0x6 -#define SMUx0B_x8410_PsoControlValidNum_OFFSET 3 -#define SMUx0B_x8410_PsoControlValidNum_WIDTH 5 -#define SMUx0B_x8410_PsoControlValidNum_MASK 0xf8 -#define SMUx0B_x8410_PsoControlPeriod_OFFSET 8 -#define SMUx0B_x8410_PsoControlPeriod_WIDTH 8 -#define SMUx0B_x8410_PsoControlPeriod_MASK 0xff00 -#define SMUx0B_x8410_RstPulseWidth_OFFSET 16 -#define SMUx0B_x8410_RstPulseWidth_WIDTH 8 -#define SMUx0B_x8410_RstPulseWidth_MASK 0xff0000 -#define SMUx0B_x8410_IsoDelay_OFFSET 24 -#define SMUx0B_x8410_IsoDelay_WIDTH 4 -#define SMUx0B_x8410_IsoDelay_MASK 0xf000000 -#define SMUx0B_x8410_PwrGaterSel_OFFSET 28 -#define SMUx0B_x8410_PwrGaterSel_WIDTH 4 -#define SMUx0B_x8410_PwrGaterSel_MASK 0xf0000000 - -/// SMUx0B_x8410 -typedef union { - struct { ///< - UINT32 PwrGatingEn:1 ; ///< - UINT32 Reserved_2_1:2 ; ///< - UINT32 PsoControlValidNum:5 ; ///< - UINT32 PsoControlPeriod:8 ; ///< - UINT32 RstPulseWidth:8 ; ///< - UINT32 IsoDelay:4 ; ///< - UINT32 PwrGaterSel:4 ; ///< - } Field; ///< - UINT32 Value; ///< -} SMUx0B_x8410_STRUCT; - -// **** SMUx0B_x8434 Register Definition **** -// Address -#define SMUx0B_x8434_ADDRESS 0x8434 - -// Type -#define SMUx0B_x8434_TYPE TYPE_SMUx0B -// Field Data -#define SMUx0B_x8434_LclkDpmEn_OFFSET 0 -#define SMUx0B_x8434_LclkDpmEn_WIDTH 1 -#define SMUx0B_x8434_LclkDpmEn_MASK 0x1 -#define SMUx0B_x8434_LclkDpmType_OFFSET 1 -#define SMUx0B_x8434_LclkDpmType_WIDTH 1 -#define SMUx0B_x8434_LclkDpmType_MASK 0x2 -#define SMUx0B_x8434_Reserved_3_2_OFFSET 2 -#define SMUx0B_x8434_Reserved_3_2_WIDTH 2 -#define SMUx0B_x8434_Reserved_3_2_MASK 0xc -#define SMUx0B_x8434_LclkTimerPrescalar_OFFSET 4 -#define SMUx0B_x8434_LclkTimerPrescalar_WIDTH 4 -#define SMUx0B_x8434_LclkTimerPrescalar_MASK 0xf0 -#define SMUx0B_x8434_Reserved_15_8_OFFSET 8 -#define SMUx0B_x8434_Reserved_15_8_WIDTH 8 -#define SMUx0B_x8434_Reserved_15_8_MASK 0xff00 -#define SMUx0B_x8434_LclkTimerPeriod_OFFSET 16 -#define SMUx0B_x8434_LclkTimerPeriod_WIDTH 16 -#define SMUx0B_x8434_LclkTimerPeriod_MASK 0xffff0000 - -/// SMUx0B_x8434 -typedef union { - struct { ///< - UINT32 LclkDpmEn:1 ; ///< - UINT32 LclkDpmType:1 ; ///< - UINT32 Reserved_3_2:2 ; ///< - UINT32 LclkTimerPrescalar:4 ; ///< - UINT32 Reserved_15_8:8 ; ///< - UINT32 LclkTimerPeriod:16; ///< - } Field; ///< - UINT32 Value; ///< -} SMUx0B_x8434_STRUCT; - -// **** SMUx0B_x8438 Register Definition **** -// Address -#define SMUx0B_x8438_ADDRESS 0x8438 - -// Type -#define SMUx0B_x8438_TYPE TYPE_SMUx0B -// Field Data -#define SMUx0B_x8438_FstatePeriod_1_OFFSET 0 -#define SMUx0B_x8438_FstatePeriod_1_WIDTH 16 -#define SMUx0B_x8438_FstatePeriod_1_MASK 0xffff -#define SMUx0B_x8438_FstatePeriod_0_OFFSET 16 -#define SMUx0B_x8438_FstatePeriod_0_WIDTH 16 -#define SMUx0B_x8438_FstatePeriod_0_MASK 0xffff0000 - -/// SMUx0B_x8438 -typedef union { - struct { ///< - UINT32 FstatePeriod_1:16; ///< - UINT32 FstatePeriod_0:16; ///< - } Field; ///< - UINT32 Value; ///< -} SMUx0B_x8438_STRUCT; - -// **** SMUx0B_x843C Register Definition **** -// Address -#define SMUx0B_x843C_ADDRESS 0x843c - -// Type -#define SMUx0B_x843C_TYPE TYPE_SMUx0B -// Field Data -#define SMUx0B_x843C_FstatePeriod_3_OFFSET 0 -#define SMUx0B_x843C_FstatePeriod_3_WIDTH 16 -#define SMUx0B_x843C_FstatePeriod_3_MASK 0xffff -#define SMUx0B_x843C_FstatePeriod_2_OFFSET 16 -#define SMUx0B_x843C_FstatePeriod_2_WIDTH 16 -#define SMUx0B_x843C_FstatePeriod_2_MASK 0xffff0000 - -/// SMUx0B_x843C -typedef union { - struct { ///< - UINT32 FstatePeriod_3:16; ///< - UINT32 FstatePeriod_2:16; ///< - } Field; ///< - UINT32 Value; ///< -} SMUx0B_x843C_STRUCT; - -// **** SMUx0B_x8440 Register Definition **** -// Address -#define SMUx0B_x8440_ADDRESS 0x8440 - -// Type -#define SMUx0B_x8440_TYPE TYPE_SMUx0B -// Field Data -#define SMUx0B_x8440_FstatePeriod_5_OFFSET 0 -#define SMUx0B_x8440_FstatePeriod_5_WIDTH 16 -#define SMUx0B_x8440_FstatePeriod_5_MASK 0xffff -#define SMUx0B_x8440_FstatePeriod_4_OFFSET 16 -#define SMUx0B_x8440_FstatePeriod_4_WIDTH 16 -#define SMUx0B_x8440_FstatePeriod_4_MASK 0xffff0000 - -/// SMUx0B_x8440 -typedef union { - struct { ///< - UINT32 FstatePeriod_5:16; ///< - UINT32 FstatePeriod_4:16; ///< - } Field; ///< - UINT32 Value; ///< -} SMUx0B_x8440_STRUCT; - -// **** SMUx0B_x8444 Register Definition **** -// Address -#define SMUx0B_x8444_ADDRESS 0x8444 - -// Type -#define SMUx0B_x8444_TYPE TYPE_SMUx0B -// Field Data -#define SMUx0B_x8444_FstatePeriod_7_OFFSET 0 -#define SMUx0B_x8444_FstatePeriod_7_WIDTH 16 -#define SMUx0B_x8444_FstatePeriod_7_MASK 0xffff -#define SMUx0B_x8444_FstatePeriod_6_OFFSET 16 -#define SMUx0B_x8444_FstatePeriod_6_WIDTH 16 -#define SMUx0B_x8444_FstatePeriod_6_MASK 0xffff0000 - -/// SMUx0B_x8444 -typedef union { - struct { ///< - UINT32 FstatePeriod_7:16; ///< - UINT32 FstatePeriod_6:16; ///< - } Field; ///< - UINT32 Value; ///< -} SMUx0B_x8444_STRUCT; - -// **** SMUx0B_x8448 Register Definition **** -// Address -#define SMUx0B_x8448_ADDRESS 0x8448 - -// Type -#define SMUx0B_x8448_TYPE TYPE_SMUx0B -// Field Data -#define SMUx0B_x8448_FstatePeriod_9_OFFSET 0 -#define SMUx0B_x8448_FstatePeriod_9_WIDTH 16 -#define SMUx0B_x8448_FstatePeriod_9_MASK 0xffff -#define SMUx0B_x8448_FstatePeriod_8_OFFSET 16 -#define SMUx0B_x8448_FstatePeriod_8_WIDTH 16 -#define SMUx0B_x8448_FstatePeriod_8_MASK 0xffff0000 - -/// SMUx0B_x8448 -typedef union { - struct { ///< - UINT32 FstatePeriod_9:16; ///< - UINT32 FstatePeriod_8:16; ///< - } Field; ///< - UINT32 Value; ///< -} SMUx0B_x8448_STRUCT; - -// **** SMUx0B_x8454 Register Definition **** -// Address -#define SMUx0B_x8454_ADDRESS 0x8454 - -// Type -#define SMUx0B_x8454_TYPE TYPE_SMUx0B -// Field Data -#define SMUx0B_x8454_Reserved_7_0_OFFSET 0 -#define SMUx0B_x8454_Reserved_7_0_WIDTH 8 -#define SMUx0B_x8454_Reserved_7_0_MASK 0xff -#define SMUx0B_x8454_Reserved_15_8_OFFSET 8 -#define SMUx0B_x8454_Reserved_15_8_WIDTH 8 -#define SMUx0B_x8454_Reserved_15_8_MASK 0xff00 -#define SMUx0B_x8454_FstateUpHyst_9_OFFSET 16 -#define SMUx0B_x8454_FstateUpHyst_9_WIDTH 8 -#define SMUx0B_x8454_FstateUpHyst_9_MASK 0xff0000 -#define SMUx0B_x8454_FstateUpHyst_8_OFFSET 24 -#define SMUx0B_x8454_FstateUpHyst_8_WIDTH 8 -#define SMUx0B_x8454_FstateUpHyst_8_MASK 0xff000000 - -/// SMUx0B_x8454 -typedef union { - struct { ///< - UINT32 Reserved_7_0:8 ; ///< - UINT32 Reserved_15_8:8 ; ///< - UINT32 FstateUpHyst_9:8 ; ///< - UINT32 FstateUpHyst_8:8 ; ///< - } Field; ///< - UINT32 Value; ///< -} SMUx0B_x8454_STRUCT; - -// **** SMUx0B_x8460 Register Definition **** -// Address -#define SMUx0B_x8460_ADDRESS 0x8460 - -// Type -#define SMUx0B_x8460_TYPE TYPE_SMUx0B -// Field Data -#define SMUx0B_x8460_Raising_OFFSET 0 -#define SMUx0B_x8460_Raising_WIDTH 16 -#define SMUx0B_x8460_Raising_MASK 0xffff -#define SMUx0B_x8460_Lowering_OFFSET 16 -#define SMUx0B_x8460_Lowering_WIDTH 16 -#define SMUx0B_x8460_Lowering_MASK 0xffff0000 - -/// SMUx0B_x8460 -typedef union { - struct { ///< - UINT32 Raising:16; ///< - UINT32 Lowering:16; ///< - } Field; ///< - UINT32 Value; ///< -} SMUx0B_x8460_STRUCT; - -// **** SMUx0B_x8461 Register Definition **** -// Address -#define SMUx0B_x8461_ADDRESS 0x8461 - -// Type -#define SMUx0B_x8461_TYPE TYPE_SMUx0B -// Field Data -#define SMUx0B_x8461_Raising_OFFSET 0 -#define SMUx0B_x8461_Raising_WIDTH 16 -#define SMUx0B_x8461_Raising_MASK 0xffff -#define SMUx0B_x8461_Lowering_OFFSET 16 -#define SMUx0B_x8461_Lowering_WIDTH 16 -#define SMUx0B_x8461_Lowering_MASK 0xffff0000 - -/// SMUx0B_x8461 -typedef union { - struct { ///< - UINT32 Raising:16; ///< - UINT32 Lowering:16; ///< - } Field; ///< - UINT32 Value; ///< -} SMUx0B_x8461_STRUCT; - -// **** SMUx0B_x8462 Register Definition **** -// Address -#define SMUx0B_x8462_ADDRESS 0x8462 - -// Type -#define SMUx0B_x8462_TYPE TYPE_SMUx0B -// Field Data -#define SMUx0B_x8462_Raising_OFFSET 0 -#define SMUx0B_x8462_Raising_WIDTH 16 -#define SMUx0B_x8462_Raising_MASK 0xffff -#define SMUx0B_x8462_Lowering_OFFSET 16 -#define SMUx0B_x8462_Lowering_WIDTH 16 -#define SMUx0B_x8462_Lowering_MASK 0xffff0000 - -/// SMUx0B_x8462 -typedef union { - struct { ///< - UINT32 Raising:16; ///< - UINT32 Lowering:16; ///< - } Field; ///< - UINT32 Value; ///< -} SMUx0B_x8462_STRUCT; - -// **** SMUx0B_x8463 Register Definition **** -// Address -#define SMUx0B_x8463_ADDRESS 0x8463 - -// Type -#define SMUx0B_x8463_TYPE TYPE_SMUx0B -// Field Data -#define SMUx0B_x8463_Raising_OFFSET 0 -#define SMUx0B_x8463_Raising_WIDTH 16 -#define SMUx0B_x8463_Raising_MASK 0xffff -#define SMUx0B_x8463_Lowering_OFFSET 16 -#define SMUx0B_x8463_Lowering_WIDTH 16 -#define SMUx0B_x8463_Lowering_MASK 0xffff0000 - -/// SMUx0B_x8463 -typedef union { - struct { ///< - UINT32 Raising:16; ///< - UINT32 Lowering:16; ///< - } Field; ///< - UINT32 Value; ///< -} SMUx0B_x8463_STRUCT; - -// **** SMUx0B_x8464 Register Definition **** -// Address -#define SMUx0B_x8464_ADDRESS 0x8464 - -// Type -#define SMUx0B_x8464_TYPE TYPE_SMUx0B -// Field Data -#define SMUx0B_x8464_Raising_OFFSET 0 -#define SMUx0B_x8464_Raising_WIDTH 16 -#define SMUx0B_x8464_Raising_MASK 0xffff -#define SMUx0B_x8464_Lowering_OFFSET 16 -#define SMUx0B_x8464_Lowering_WIDTH 16 -#define SMUx0B_x8464_Lowering_MASK 0xffff0000 - -/// SMUx0B_x8464 -typedef union { - struct { ///< - UINT32 Raising:16; ///< - UINT32 Lowering:16; ///< - } Field; ///< - UINT32 Value; ///< -} SMUx0B_x8464_STRUCT; - -// **** SMUx0B_x8465 Register Definition **** -// Address -#define SMUx0B_x8465_ADDRESS 0x8465 - -// Type -#define SMUx0B_x8465_TYPE TYPE_SMUx0B -// Field Data -#define SMUx0B_x8465_Raising_OFFSET 0 -#define SMUx0B_x8465_Raising_WIDTH 16 -#define SMUx0B_x8465_Raising_MASK 0xffff -#define SMUx0B_x8465_Lowering_OFFSET 16 -#define SMUx0B_x8465_Lowering_WIDTH 16 -#define SMUx0B_x8465_Lowering_MASK 0xffff0000 - -/// SMUx0B_x8465 -typedef union { - struct { ///< - UINT32 Raising:16; ///< - UINT32 Lowering:16; ///< - } Field; ///< - UINT32 Value; ///< -} SMUx0B_x8465_STRUCT; - -// **** SMUx0B_x8466 Register Definition **** -// Address -#define SMUx0B_x8466_ADDRESS 0x8466 - -// Type -#define SMUx0B_x8466_TYPE TYPE_SMUx0B -// Field Data -#define SMUx0B_x8466_Raising_OFFSET 0 -#define SMUx0B_x8466_Raising_WIDTH 16 -#define SMUx0B_x8466_Raising_MASK 0xffff -#define SMUx0B_x8466_Lowering_OFFSET 16 -#define SMUx0B_x8466_Lowering_WIDTH 16 -#define SMUx0B_x8466_Lowering_MASK 0xffff0000 - -/// SMUx0B_x8466 -typedef union { - struct { ///< - UINT32 Raising:16; ///< - UINT32 Lowering:16; ///< - } Field; ///< - UINT32 Value; ///< -} SMUx0B_x8466_STRUCT; - -// **** SMUx0B_x8467 Register Definition **** -// Address -#define SMUx0B_x8467_ADDRESS 0x8467 - -// Type -#define SMUx0B_x8467_TYPE TYPE_SMUx0B -// Field Data -#define SMUx0B_x8467_Raising_OFFSET 0 -#define SMUx0B_x8467_Raising_WIDTH 16 -#define SMUx0B_x8467_Raising_MASK 0xffff -#define SMUx0B_x8467_Lowering_OFFSET 16 -#define SMUx0B_x8467_Lowering_WIDTH 16 -#define SMUx0B_x8467_Lowering_MASK 0xffff0000 - -/// SMUx0B_x8467 -typedef union { - struct { ///< - UINT32 Raising:16; ///< - UINT32 Lowering:16; ///< - } Field; ///< - UINT32 Value; ///< -} SMUx0B_x8467_STRUCT; - -// **** SMUx0B_x8468 Register Definition **** -// Address -#define SMUx0B_x8468_ADDRESS 0x8468 - -// Type -#define SMUx0B_x8468_TYPE TYPE_SMUx0B -// Field Data -#define SMUx0B_x8468_Raising_OFFSET 0 -#define SMUx0B_x8468_Raising_WIDTH 16 -#define SMUx0B_x8468_Raising_MASK 0xffff -#define SMUx0B_x8468_Lowering_OFFSET 16 -#define SMUx0B_x8468_Lowering_WIDTH 16 -#define SMUx0B_x8468_Lowering_MASK 0xffff0000 - -/// SMUx0B_x8468 -typedef union { - struct { ///< - UINT32 Raising:16; ///< - UINT32 Lowering:16; ///< - } Field; ///< - UINT32 Value; ///< -} SMUx0B_x8468_STRUCT; - -// **** SMUx0B_x8469 Register Definition **** -// Address -#define SMUx0B_x8469_ADDRESS 0x8469 - -// Type -#define SMUx0B_x8469_TYPE TYPE_SMUx0B -// Field Data -#define SMUx0B_x8469_Raising_OFFSET 0 -#define SMUx0B_x8469_Raising_WIDTH 16 -#define SMUx0B_x8469_Raising_MASK 0xffff -#define SMUx0B_x8469_Lowering_OFFSET 16 -#define SMUx0B_x8469_Lowering_WIDTH 16 -#define SMUx0B_x8469_Lowering_MASK 0xffff0000 - -/// SMUx0B_x8469 -typedef union { - struct { ///< - UINT32 Raising:16; ///< - UINT32 Lowering:16; ///< - } Field; ///< - UINT32 Value; ///< -} SMUx0B_x8469_STRUCT; - -// **** SMUx0B_x846A Register Definition **** -// Address -#define SMUx0B_x846A_ADDRESS 0x846a - -// Type -#define SMUx0B_x846A_TYPE TYPE_SMUx0B -// Field Data -#define SMUx0B_x846A_Raising_OFFSET 0 -#define SMUx0B_x846A_Raising_WIDTH 16 -#define SMUx0B_x846A_Raising_MASK 0xffff -#define SMUx0B_x846A_Lowering_OFFSET 16 -#define SMUx0B_x846A_Lowering_WIDTH 16 -#define SMUx0B_x846A_Lowering_MASK 0xffff0000 - -/// SMUx0B_x846A -typedef union { - struct { ///< - UINT32 Raising:16; ///< - UINT32 Lowering:16; ///< - } Field; ///< - UINT32 Value; ///< -} SMUx0B_x846A_STRUCT; - -// **** SMUx0B_x846B Register Definition **** -// Address -#define SMUx0B_x846B_ADDRESS 0x846b - -// Type -#define SMUx0B_x846B_TYPE TYPE_SMUx0B -// Field Data -#define SMUx0B_x846B_Raising_OFFSET 0 -#define SMUx0B_x846B_Raising_WIDTH 16 -#define SMUx0B_x846B_Raising_MASK 0xffff -#define SMUx0B_x846B_Lowering_OFFSET 16 -#define SMUx0B_x846B_Lowering_WIDTH 16 -#define SMUx0B_x846B_Lowering_MASK 0xffff0000 - -/// SMUx0B_x846B -typedef union { - struct { ///< - UINT32 Raising:16; ///< - UINT32 Lowering:16; ///< - } Field; ///< - UINT32 Value; ///< -} SMUx0B_x846B_STRUCT; - -// **** SMUx0B_x846C Register Definition **** -// Address -#define SMUx0B_x846C_ADDRESS 0x846c - -// Type -#define SMUx0B_x846C_TYPE TYPE_SMUx0B -// Field Data -#define SMUx0B_x846C_Raising_OFFSET 0 -#define SMUx0B_x846C_Raising_WIDTH 16 -#define SMUx0B_x846C_Raising_MASK 0xffff -#define SMUx0B_x846C_Lowering_OFFSET 16 -#define SMUx0B_x846C_Lowering_WIDTH 16 -#define SMUx0B_x846C_Lowering_MASK 0xffff0000 - -/// SMUx0B_x846C -typedef union { - struct { ///< - UINT32 Raising:16; ///< - UINT32 Lowering:16; ///< - } Field; ///< - UINT32 Value; ///< -} SMUx0B_x846C_STRUCT; - -// **** SMUx0B_x846D Register Definition **** -// Address -#define SMUx0B_x846D_ADDRESS 0x846d - -// Type -#define SMUx0B_x846D_TYPE TYPE_SMUx0B -// Field Data -#define SMUx0B_x846D_Raising_OFFSET 0 -#define SMUx0B_x846D_Raising_WIDTH 16 -#define SMUx0B_x846D_Raising_MASK 0xffff -#define SMUx0B_x846D_Lowering_OFFSET 16 -#define SMUx0B_x846D_Lowering_WIDTH 16 -#define SMUx0B_x846D_Lowering_MASK 0xffff0000 - -/// SMUx0B_x846D -typedef union { - struct { ///< - UINT32 Raising:16; ///< - UINT32 Lowering:16; ///< - } Field; ///< - UINT32 Value; ///< -} SMUx0B_x846D_STRUCT; - -// **** SMUx0B_x846E Register Definition **** -// Address -#define SMUx0B_x846E_ADDRESS 0x846e - -// Type -#define SMUx0B_x846E_TYPE TYPE_SMUx0B -// Field Data -#define SMUx0B_x846E_Raising_OFFSET 0 -#define SMUx0B_x846E_Raising_WIDTH 16 -#define SMUx0B_x846E_Raising_MASK 0xffff -#define SMUx0B_x846E_Lowering_OFFSET 16 -#define SMUx0B_x846E_Lowering_WIDTH 16 -#define SMUx0B_x846E_Lowering_MASK 0xffff0000 - -/// SMUx0B_x846E -typedef union { - struct { ///< - UINT32 Raising:16; ///< - UINT32 Lowering:16; ///< - } Field; ///< - UINT32 Value; ///< -} SMUx0B_x846E_STRUCT; - -// **** SMUx0B_x846F Register Definition **** -// Address -#define SMUx0B_x846F_ADDRESS 0x846f - -// Type -#define SMUx0B_x846F_TYPE TYPE_SMUx0B -// Field Data -#define SMUx0B_x846F_Raising_OFFSET 0 -#define SMUx0B_x846F_Raising_WIDTH 16 -#define SMUx0B_x846F_Raising_MASK 0xffff -#define SMUx0B_x846F_Lowering_OFFSET 16 -#define SMUx0B_x846F_Lowering_WIDTH 16 -#define SMUx0B_x846F_Lowering_MASK 0xffff0000 - -/// SMUx0B_x846F -typedef union { - struct { ///< - UINT32 Raising:16; ///< - UINT32 Lowering:16; ///< - } Field; ///< - UINT32 Value; ///< -} SMUx0B_x846F_STRUCT; - -// **** SMUx0B_x8470 Register Definition **** -// Address -#define SMUx0B_x8470_ADDRESS 0x8470 - -// Type -#define SMUx0B_x8470_TYPE TYPE_SMUx0B -// Field Data -#define SMUx0B_x8470_Raising_OFFSET 0 -#define SMUx0B_x8470_Raising_WIDTH 16 -#define SMUx0B_x8470_Raising_MASK 0xffff -#define SMUx0B_x8470_Lowering_OFFSET 16 -#define SMUx0B_x8470_Lowering_WIDTH 16 -#define SMUx0B_x8470_Lowering_MASK 0xffff0000 - -/// SMUx0B_x8470 -typedef union { - struct { ///< - UINT32 Raising:16; ///< - UINT32 Lowering:16; ///< - } Field; ///< - UINT32 Value; ///< -} SMUx0B_x8470_STRUCT; - -// **** SMUx0B_x8471 Register Definition **** -// Address -#define SMUx0B_x8471_ADDRESS 0x8471 - -// Type -#define SMUx0B_x8471_TYPE TYPE_SMUx0B -// Field Data -#define SMUx0B_x8471_Raising_OFFSET 0 -#define SMUx0B_x8471_Raising_WIDTH 16 -#define SMUx0B_x8471_Raising_MASK 0xffff -#define SMUx0B_x8471_Lowering_OFFSET 16 -#define SMUx0B_x8471_Lowering_WIDTH 16 -#define SMUx0B_x8471_Lowering_MASK 0xffff0000 - -/// SMUx0B_x8471 -typedef union { - struct { ///< - UINT32 Raising:16; ///< - UINT32 Lowering:16; ///< - } Field; ///< - UINT32 Value; ///< -} SMUx0B_x8471_STRUCT; - -// **** SMUx0B_x8472 Register Definition **** -// Address -#define SMUx0B_x8472_ADDRESS 0x8472 - -// Type -#define SMUx0B_x8472_TYPE TYPE_SMUx0B -// Field Data -#define SMUx0B_x8472_Raising_OFFSET 0 -#define SMUx0B_x8472_Raising_WIDTH 16 -#define SMUx0B_x8472_Raising_MASK 0xffff -#define SMUx0B_x8472_Lowering_OFFSET 16 -#define SMUx0B_x8472_Lowering_WIDTH 16 -#define SMUx0B_x8472_Lowering_MASK 0xffff0000 - -/// SMUx0B_x8472 -typedef union { - struct { ///< - UINT32 Raising:16; ///< - UINT32 Lowering:16; ///< - } Field; ///< - UINT32 Value; ///< -} SMUx0B_x8472_STRUCT; - -// **** SMUx0B_x8473 Register Definition **** -// Address -#define SMUx0B_x8473_ADDRESS 0x8473 - -// Type -#define SMUx0B_x8473_TYPE TYPE_SMUx0B -// Field Data -#define SMUx0B_x8473_Raising_OFFSET 0 -#define SMUx0B_x8473_Raising_WIDTH 16 -#define SMUx0B_x8473_Raising_MASK 0xffff -#define SMUx0B_x8473_Lowering_OFFSET 16 -#define SMUx0B_x8473_Lowering_WIDTH 16 -#define SMUx0B_x8473_Lowering_MASK 0xffff0000 - -/// SMUx0B_x8473 -typedef union { - struct { ///< - UINT32 Raising:16; ///< - UINT32 Lowering:16; ///< - } Field; ///< - UINT32 Value; ///< -} SMUx0B_x8473_STRUCT; - -// **** SMUx0B_x8474 Register Definition **** -// Address -#define SMUx0B_x8474_ADDRESS 0x8474 - -// Type -#define SMUx0B_x8474_TYPE TYPE_SMUx0B -// Field Data -#define SMUx0B_x8474_Raising_OFFSET 0 -#define SMUx0B_x8474_Raising_WIDTH 16 -#define SMUx0B_x8474_Raising_MASK 0xffff -#define SMUx0B_x8474_Lowering_OFFSET 16 -#define SMUx0B_x8474_Lowering_WIDTH 16 -#define SMUx0B_x8474_Lowering_MASK 0xffff0000 - -/// SMUx0B_x8474 -typedef union { - struct { ///< - UINT32 Raising:16; ///< - UINT32 Lowering:16; ///< - } Field; ///< - UINT32 Value; ///< -} SMUx0B_x8474_STRUCT; - -// **** SMUx0B_x8475 Register Definition **** -// Address -#define SMUx0B_x8475_ADDRESS 0x8475 - -// Type -#define SMUx0B_x8475_TYPE TYPE_SMUx0B -// Field Data -#define SMUx0B_x8475_Raising_OFFSET 0 -#define SMUx0B_x8475_Raising_WIDTH 16 -#define SMUx0B_x8475_Raising_MASK 0xffff -#define SMUx0B_x8475_Lowering_OFFSET 16 -#define SMUx0B_x8475_Lowering_WIDTH 16 -#define SMUx0B_x8475_Lowering_MASK 0xffff0000 - -/// SMUx0B_x8475 -typedef union { - struct { ///< - UINT32 Raising:16; ///< - UINT32 Lowering:16; ///< - } Field; ///< - UINT32 Value; ///< -} SMUx0B_x8475_STRUCT; - -// **** SMUx0B_x8476 Register Definition **** -// Address -#define SMUx0B_x8476_ADDRESS 0x8476 - -// Type -#define SMUx0B_x8476_TYPE TYPE_SMUx0B -// Field Data -#define SMUx0B_x8476_Raising_OFFSET 0 -#define SMUx0B_x8476_Raising_WIDTH 16 -#define SMUx0B_x8476_Raising_MASK 0xffff -#define SMUx0B_x8476_Lowering_OFFSET 16 -#define SMUx0B_x8476_Lowering_WIDTH 16 -#define SMUx0B_x8476_Lowering_MASK 0xffff0000 - -/// SMUx0B_x8476 -typedef union { - struct { ///< - UINT32 Raising:16; ///< - UINT32 Lowering:16; ///< - } Field; ///< - UINT32 Value; ///< -} SMUx0B_x8476_STRUCT; - -// **** SMUx0B_x8477 Register Definition **** -// Address -#define SMUx0B_x8477_ADDRESS 0x8477 - -// Type -#define SMUx0B_x8477_TYPE TYPE_SMUx0B -// Field Data -#define SMUx0B_x8477_Raising_OFFSET 0 -#define SMUx0B_x8477_Raising_WIDTH 16 -#define SMUx0B_x8477_Raising_MASK 0xffff -#define SMUx0B_x8477_Lowering_OFFSET 16 -#define SMUx0B_x8477_Lowering_WIDTH 16 -#define SMUx0B_x8477_Lowering_MASK 0xffff0000 - -/// SMUx0B_x8477 -typedef union { - struct { ///< - UINT32 Raising:16; ///< - UINT32 Lowering:16; ///< - } Field; ///< - UINT32 Value; ///< -} SMUx0B_x8477_STRUCT; - -// **** SMUx0B_x8478 Register Definition **** -// Address -#define SMUx0B_x8478_ADDRESS 0x8478 - -// Type -#define SMUx0B_x8478_TYPE TYPE_SMUx0B -// Field Data -#define SMUx0B_x8478_Raising_OFFSET 0 -#define SMUx0B_x8478_Raising_WIDTH 16 -#define SMUx0B_x8478_Raising_MASK 0xffff -#define SMUx0B_x8478_Lowering_OFFSET 16 -#define SMUx0B_x8478_Lowering_WIDTH 16 -#define SMUx0B_x8478_Lowering_MASK 0xffff0000 - -/// SMUx0B_x8478 -typedef union { - struct { ///< - UINT32 Raising:16; ///< - UINT32 Lowering:16; ///< - } Field; ///< - UINT32 Value; ///< -} SMUx0B_x8478_STRUCT; - -// **** SMUx0B_x8479 Register Definition **** -// Address -#define SMUx0B_x8479_ADDRESS 0x8479 - -// Type -#define SMUx0B_x8479_TYPE TYPE_SMUx0B -// Field Data -#define SMUx0B_x8479_Raising_OFFSET 0 -#define SMUx0B_x8479_Raising_WIDTH 16 -#define SMUx0B_x8479_Raising_MASK 0xffff -#define SMUx0B_x8479_Lowering_OFFSET 16 -#define SMUx0B_x8479_Lowering_WIDTH 16 -#define SMUx0B_x8479_Lowering_MASK 0xffff0000 - -/// SMUx0B_x8479 -typedef union { - struct { ///< - UINT32 Raising:16; ///< - UINT32 Lowering:16; ///< - } Field; ///< - UINT32 Value; ///< -} SMUx0B_x8479_STRUCT; - -// **** SMUx0B_x847A Register Definition **** -// Address -#define SMUx0B_x847A_ADDRESS 0x847a - -// Type -#define SMUx0B_x847A_TYPE TYPE_SMUx0B -// Field Data -#define SMUx0B_x847A_Raising_OFFSET 0 -#define SMUx0B_x847A_Raising_WIDTH 16 -#define SMUx0B_x847A_Raising_MASK 0xffff -#define SMUx0B_x847A_Lowering_OFFSET 16 -#define SMUx0B_x847A_Lowering_WIDTH 16 -#define SMUx0B_x847A_Lowering_MASK 0xffff0000 - -/// SMUx0B_x847A -typedef union { - struct { ///< - UINT32 Raising:16; ///< - UINT32 Lowering:16; ///< - } Field; ///< - UINT32 Value; ///< -} SMUx0B_x847A_STRUCT; - -// **** SMUx0B_x847B Register Definition **** -// Address -#define SMUx0B_x847B_ADDRESS 0x847b - -// Type -#define SMUx0B_x847B_TYPE TYPE_SMUx0B -// Field Data -#define SMUx0B_x847B_Raising_OFFSET 0 -#define SMUx0B_x847B_Raising_WIDTH 16 -#define SMUx0B_x847B_Raising_MASK 0xffff -#define SMUx0B_x847B_Lowering_OFFSET 16 -#define SMUx0B_x847B_Lowering_WIDTH 16 -#define SMUx0B_x847B_Lowering_MASK 0xffff0000 - -/// SMUx0B_x847B -typedef union { - struct { ///< - UINT32 Raising:16; ///< - UINT32 Lowering:16; ///< - } Field; ///< - UINT32 Value; ///< -} SMUx0B_x847B_STRUCT; - -// **** SMUx0B_x847C Register Definition **** -// Address -#define SMUx0B_x847C_ADDRESS 0x847c - -// Type -#define SMUx0B_x847C_TYPE TYPE_SMUx0B -// Field Data -#define SMUx0B_x847C_Raising_OFFSET 0 -#define SMUx0B_x847C_Raising_WIDTH 16 -#define SMUx0B_x847C_Raising_MASK 0xffff -#define SMUx0B_x847C_Lowering_OFFSET 16 -#define SMUx0B_x847C_Lowering_WIDTH 16 -#define SMUx0B_x847C_Lowering_MASK 0xffff0000 - -/// SMUx0B_x847C -typedef union { - struct { ///< - UINT32 Raising:16; ///< - UINT32 Lowering:16; ///< - } Field; ///< - UINT32 Value; ///< -} SMUx0B_x847C_STRUCT; - -// **** SMUx0B_x8488 Register Definition **** -// Address -#define SMUx0B_x8488_ADDRESS 0x8488 - -// Type -#define SMUx0B_x8488_TYPE TYPE_SMUx0B -// Field Data -#define SMUx0B_x8488_FstateDiv_3_OFFSET 0 -#define SMUx0B_x8488_FstateDiv_3_WIDTH 7 -#define SMUx0B_x8488_FstateDiv_3_MASK 0x7f -#define SMUx0B_x8488_Reserved_7_7_OFFSET 7 -#define SMUx0B_x8488_Reserved_7_7_WIDTH 1 -#define SMUx0B_x8488_Reserved_7_7_MASK 0x80 -#define SMUx0B_x8488_FstateDiv_2_OFFSET 8 -#define SMUx0B_x8488_FstateDiv_2_WIDTH 7 -#define SMUx0B_x8488_FstateDiv_2_MASK 0x7f00 -#define SMUx0B_x8488_Reserved_15_15_OFFSET 15 -#define SMUx0B_x8488_Reserved_15_15_WIDTH 1 -#define SMUx0B_x8488_Reserved_15_15_MASK 0x8000 -#define SMUx0B_x8488_FstateDiv_1_OFFSET 16 -#define SMUx0B_x8488_FstateDiv_1_WIDTH 7 -#define SMUx0B_x8488_FstateDiv_1_MASK 0x7f0000 -#define SMUx0B_x8488_Reserved_23_23_OFFSET 23 -#define SMUx0B_x8488_Reserved_23_23_WIDTH 1 -#define SMUx0B_x8488_Reserved_23_23_MASK 0x800000 -#define SMUx0B_x8488_FstateDiv_0_OFFSET 24 -#define SMUx0B_x8488_FstateDiv_0_WIDTH 7 -#define SMUx0B_x8488_FstateDiv_0_MASK 0x7f000000 -#define SMUx0B_x8488_Reserved_31_31_OFFSET 31 -#define SMUx0B_x8488_Reserved_31_31_WIDTH 1 -#define SMUx0B_x8488_Reserved_31_31_MASK 0x80000000 - -/// SMUx0B_x8488 -typedef union { - struct { ///< - UINT32 FstateDiv_3:7 ; ///< - UINT32 Reserved_7_7:1 ; ///< - UINT32 FstateDiv_2:7 ; ///< - UINT32 Reserved_15_15:1 ; ///< - UINT32 FstateDiv_1:7 ; ///< - UINT32 Reserved_23_23:1 ; ///< - UINT32 FstateDiv_0:7 ; ///< - UINT32 Reserved_31_31:1 ; ///< - } Field; ///< - UINT32 Value; ///< -} SMUx0B_x8488_STRUCT; - -// **** SMUx0B_x848C Register Definition **** -// Address -#define SMUx0B_x848C_ADDRESS 0x848c - -// Type -#define SMUx0B_x848C_TYPE TYPE_SMUx0B -// Field Data -#define SMUx0B_x848C_FstateDiv_7_OFFSET 0 -#define SMUx0B_x848C_FstateDiv_7_WIDTH 7 -#define SMUx0B_x848C_FstateDiv_7_MASK 0x7f -#define SMUx0B_x848C_Reserved_7_7_OFFSET 7 -#define SMUx0B_x848C_Reserved_7_7_WIDTH 1 -#define SMUx0B_x848C_Reserved_7_7_MASK 0x80 -#define SMUx0B_x848C_FstateDiv_6_OFFSET 8 -#define SMUx0B_x848C_FstateDiv_6_WIDTH 7 -#define SMUx0B_x848C_FstateDiv_6_MASK 0x7f00 -#define SMUx0B_x848C_Reserved_15_15_OFFSET 15 -#define SMUx0B_x848C_Reserved_15_15_WIDTH 1 -#define SMUx0B_x848C_Reserved_15_15_MASK 0x8000 -#define SMUx0B_x848C_FstateDiv_5_OFFSET 16 -#define SMUx0B_x848C_FstateDiv_5_WIDTH 7 -#define SMUx0B_x848C_FstateDiv_5_MASK 0x7f0000 -#define SMUx0B_x848C_Reserved_23_23_OFFSET 23 -#define SMUx0B_x848C_Reserved_23_23_WIDTH 1 -#define SMUx0B_x848C_Reserved_23_23_MASK 0x800000 -#define SMUx0B_x848C_FstateDiv_4_OFFSET 24 -#define SMUx0B_x848C_FstateDiv_4_WIDTH 7 -#define SMUx0B_x848C_FstateDiv_4_MASK 0x7f000000 -#define SMUx0B_x848C_Reserved_31_31_OFFSET 31 -#define SMUx0B_x848C_Reserved_31_31_WIDTH 1 -#define SMUx0B_x848C_Reserved_31_31_MASK 0x80000000 - -/// SMUx0B_x848C -typedef union { - struct { ///< - UINT32 FstateDiv_7:7 ; ///< - UINT32 Reserved_7_7:1 ; ///< - UINT32 FstateDiv_6:7 ; ///< - UINT32 Reserved_15_15:1 ; ///< - UINT32 FstateDiv_5:7 ; ///< - UINT32 Reserved_23_23:1 ; ///< - UINT32 FstateDiv_4:7 ; ///< - UINT32 Reserved_31_31:1 ; ///< - } Field; ///< - UINT32 Value; ///< -} SMUx0B_x848C_STRUCT; - -// **** SMUx0B_x8490 Register Definition **** -// Address -#define SMUx0B_x8490_ADDRESS 0x8490 - -// Type -#define SMUx0B_x8490_TYPE TYPE_SMUx0B -// Field Data -#define SMUx0B_x8490_LclkState0Valid_OFFSET 0 -#define SMUx0B_x8490_LclkState0Valid_WIDTH 1 -#define SMUx0B_x8490_LclkState0Valid_MASK 0x1 -#define SMUx0B_x8490_LclkState1Valid_OFFSET 1 -#define SMUx0B_x8490_LclkState1Valid_WIDTH 1 -#define SMUx0B_x8490_LclkState1Valid_MASK 0x2 -#define SMUx0B_x8490_LclkState2Valid_OFFSET 2 -#define SMUx0B_x8490_LclkState2Valid_WIDTH 1 -#define SMUx0B_x8490_LclkState2Valid_MASK 0x4 -#define SMUx0B_x8490_LclkState3Valid_OFFSET 3 -#define SMUx0B_x8490_LclkState3Valid_WIDTH 1 -#define SMUx0B_x8490_LclkState3Valid_MASK 0x8 -#define SMUx0B_x8490_LclkState4Valid_OFFSET 4 -#define SMUx0B_x8490_LclkState4Valid_WIDTH 1 -#define SMUx0B_x8490_LclkState4Valid_MASK 0x10 -#define SMUx0B_x8490_LclkState5Valid_OFFSET 5 -#define SMUx0B_x8490_LclkState5Valid_WIDTH 1 -#define SMUx0B_x8490_LclkState5Valid_MASK 0x20 -#define SMUx0B_x8490_LclkState6Valid_OFFSET 6 -#define SMUx0B_x8490_LclkState6Valid_WIDTH 1 -#define SMUx0B_x8490_LclkState6Valid_MASK 0x40 -#define SMUx0B_x8490_LclkState7Valid_OFFSET 7 -#define SMUx0B_x8490_LclkState7Valid_WIDTH 1 -#define SMUx0B_x8490_LclkState7Valid_MASK 0x80 -#define SMUx0B_x8490_LclkDivTtExit_OFFSET 8 -#define SMUx0B_x8490_LclkDivTtExit_WIDTH 8 -#define SMUx0B_x8490_LclkDivTtExit_MASK 0xff00 -#define SMUx0B_x8490_MinDivAllowed_OFFSET 16 -#define SMUx0B_x8490_MinDivAllowed_WIDTH 8 -#define SMUx0B_x8490_MinDivAllowed_MASK 0xff0000 -#define SMUx0B_x8490_Reserved_31_24_OFFSET 24 -#define SMUx0B_x8490_Reserved_31_24_WIDTH 8 -#define SMUx0B_x8490_Reserved_31_24_MASK 0xff000000 - -/// SMUx0B_x8490 -typedef union { - struct { ///< - UINT32 LclkState0Valid:1 ; ///< - UINT32 LclkState1Valid:1 ; ///< - UINT32 LclkState2Valid:1 ; ///< - UINT32 LclkState3Valid:1 ; ///< - UINT32 LclkState4Valid:1 ; ///< - UINT32 LclkState5Valid:1 ; ///< - UINT32 LclkState6Valid:1 ; ///< - UINT32 LclkState7Valid:1 ; ///< - UINT32 LclkDivTtExit:8 ; ///< - UINT32 MinDivAllowed:8 ; ///< - UINT32 Reserved_31_24:8 ; ///< - } Field; ///< - UINT32 Value; ///< -} SMUx0B_x8490_STRUCT; - -// **** SMUx0B_x849C Register Definition **** -// Address -#define SMUx0B_x849C_ADDRESS 0x849c - -// Type -#define SMUx0B_x849C_TYPE TYPE_SMUx0B -// Field Data -#define SMUx0B_x849C_Reserved_1_0_OFFSET 0 -#define SMUx0B_x849C_Reserved_1_0_WIDTH 2 -#define SMUx0B_x849C_Reserved_1_0_MASK 0x3 -#define SMUx0B_x849C_Reserved_3_2_OFFSET 2 -#define SMUx0B_x849C_Reserved_3_2_WIDTH 2 -#define SMUx0B_x849C_Reserved_3_2_MASK 0xc -#define SMUx0B_x849C_Reserved_7_4_OFFSET 4 -#define SMUx0B_x849C_Reserved_7_4_WIDTH 4 -#define SMUx0B_x849C_Reserved_7_4_MASK 0xf0 -#define SMUx0B_x849C_Reserved_9_8_OFFSET 8 -#define SMUx0B_x849C_Reserved_9_8_WIDTH 2 -#define SMUx0B_x849C_Reserved_9_8_MASK 0x300 -#define SMUx0B_x849C_Reserved_11_10_OFFSET 10 -#define SMUx0B_x849C_Reserved_11_10_WIDTH 2 -#define SMUx0B_x849C_Reserved_11_10_MASK 0xc00 -#define SMUx0B_x849C_Reserved_15_12_OFFSET 12 -#define SMUx0B_x849C_Reserved_15_12_WIDTH 4 -#define SMUx0B_x849C_Reserved_15_12_MASK 0xf000 -#define SMUx0B_x849C_BaseVid_9_OFFSET 16 -#define SMUx0B_x849C_BaseVid_9_WIDTH 2 -#define SMUx0B_x849C_BaseVid_9_MASK 0x30000 -#define SMUx0B_x849C_TolExcdVid_9_OFFSET 18 -#define SMUx0B_x849C_TolExcdVid_9_WIDTH 2 -#define SMUx0B_x849C_TolExcdVid_9_MASK 0xc0000 -#define SMUx0B_x849C_Reserved_23_20_OFFSET 20 -#define SMUx0B_x849C_Reserved_23_20_WIDTH 4 -#define SMUx0B_x849C_Reserved_23_20_MASK 0xf00000 -#define SMUx0B_x849C_BaseVid_8_OFFSET 24 -#define SMUx0B_x849C_BaseVid_8_WIDTH 2 -#define SMUx0B_x849C_BaseVid_8_MASK 0x3000000 -#define SMUx0B_x849C_TolExcdVid_8_OFFSET 26 -#define SMUx0B_x849C_TolExcdVid_8_WIDTH 2 -#define SMUx0B_x849C_TolExcdVid_8_MASK 0xc000000 -#define SMUx0B_x849C_Reserved_31_28_OFFSET 28 -#define SMUx0B_x849C_Reserved_31_28_WIDTH 4 -#define SMUx0B_x849C_Reserved_31_28_MASK 0xf0000000 - -/// SMUx0B_x849C -typedef union { - struct { ///< - UINT32 Reserved_1_0:2 ; ///< - UINT32 Reserved_3_2:2 ; ///< - UINT32 Reserved_7_4:4 ; ///< - UINT32 Reserved_9_8:2 ; ///< - UINT32 Reserved_11_10:2 ; ///< - UINT32 Reserved_15_12:4 ; ///< - UINT32 BaseVid_9:2 ; ///< - UINT32 TolExcdVid_9:2 ; ///< - UINT32 Reserved_23_20:4 ; ///< - UINT32 BaseVid_8:2 ; ///< - UINT32 TolExcdVid_8:2 ; ///< - UINT32 Reserved_31_28:4 ; ///< - } Field; ///< - UINT32 Value; ///< -} SMUx0B_x849C_STRUCT; - -// **** SMUx0B_x84A0 Register Definition **** -// Address -#define SMUx0B_x84A0_ADDRESS 0x84a0 - -// Type -#define SMUx0B_x84A0_TYPE TYPE_SMUx0B -// Field Data -#define SMUx0B_x84A0_MothPsoPwrup_OFFSET 0 -#define SMUx0B_x84A0_MothPsoPwrup_WIDTH 16 -#define SMUx0B_x84A0_MothPsoPwrup_MASK 0xffff -#define SMUx0B_x84A0_MothPsoPwrdn_OFFSET 16 -#define SMUx0B_x84A0_MothPsoPwrdn_WIDTH 16 -#define SMUx0B_x84A0_MothPsoPwrdn_MASK 0xffff0000 - -/// SMUx0B_x84A0 -typedef union { - struct { ///< - UINT32 MothPsoPwrup:16; ///< - UINT32 MothPsoPwrdn:16; ///< - } Field; ///< - UINT32 Value; ///< -} SMUx0B_x84A0_STRUCT; - -// **** SMUx0B_x84A4 Register Definition **** -// Address -#define SMUx0B_x84A4_ADDRESS 0x84a4 - -// Type -#define SMUx0B_x84A4_TYPE TYPE_SMUx0B -// Field Data -#define SMUx0B_x84A4_DaugPsoPwrup_OFFSET 0 -#define SMUx0B_x84A4_DaugPsoPwrup_WIDTH 16 -#define SMUx0B_x84A4_DaugPsoPwrup_MASK 0xffff -#define SMUx0B_x84A4_DaugPsoPwrdn_OFFSET 16 -#define SMUx0B_x84A4_DaugPsoPwrdn_WIDTH 16 -#define SMUx0B_x84A4_DaugPsoPwrdn_MASK 0xffff0000 - -/// SMUx0B_x84A4 -typedef union { - struct { ///< - UINT32 DaugPsoPwrup:16; ///< - UINT32 DaugPsoPwrdn:16; ///< - } Field; ///< - UINT32 Value; ///< -} SMUx0B_x84A4_STRUCT; - -// **** SMUx0B_x84A8 Register Definition **** -// Address -#define SMUx0B_x84A8_ADDRESS 0x84a8 - -// Type -#define SMUx0B_x84A8_TYPE TYPE_SMUx0B -// Field Data -#define SMUx0B_x84A8_ResetTimer_OFFSET 0 -#define SMUx0B_x84A8_ResetTimer_WIDTH 16 -#define SMUx0B_x84A8_ResetTimer_MASK 0xffff -#define SMUx0B_x84A8_IsoTimer_OFFSET 16 -#define SMUx0B_x84A8_IsoTimer_WIDTH 16 -#define SMUx0B_x84A8_IsoTimer_MASK 0xffff0000 - -/// SMUx0B_x84A8 -typedef union { - struct { ///< - UINT32 ResetTimer:16; ///< - UINT32 IsoTimer:16; ///< - } Field; ///< - UINT32 Value; ///< -} SMUx0B_x84A8_STRUCT; - -// **** SMUx0B_x84C4 Register Definition **** -// Address -#define SMUx0B_x84C4_ADDRESS 0x84c4 - -// Type -#define SMUx0B_x84C4_TYPE TYPE_SMUx0B -// Field Data -#define SMUx0B_x84C4_FstateDnHyst_3_OFFSET 0 -#define SMUx0B_x84C4_FstateDnHyst_3_WIDTH 8 -#define SMUx0B_x84C4_FstateDnHyst_3_MASK 0xff -#define SMUx0B_x84C4_FstateDnHyst_2_OFFSET 8 -#define SMUx0B_x84C4_FstateDnHyst_2_WIDTH 8 -#define SMUx0B_x84C4_FstateDnHyst_2_MASK 0xff00 -#define SMUx0B_x84C4_FstateDnHyst_1_OFFSET 16 -#define SMUx0B_x84C4_FstateDnHyst_1_WIDTH 8 -#define SMUx0B_x84C4_FstateDnHyst_1_MASK 0xff0000 -#define SMUx0B_x84C4_FstateDnHyst_0_OFFSET 24 -#define SMUx0B_x84C4_FstateDnHyst_0_WIDTH 8 -#define SMUx0B_x84C4_FstateDnHyst_0_MASK 0xff000000 - -/// SMUx0B_x84C4 -typedef union { - struct { ///< - UINT32 FstateDnHyst_3:8 ; ///< - UINT32 FstateDnHyst_2:8 ; ///< - UINT32 FstateDnHyst_1:8 ; ///< - UINT32 FstateDnHyst_0:8 ; ///< - } Field; ///< - UINT32 Value; ///< -} SMUx0B_x84C4_STRUCT; - -// **** SMUx0B_x84C8 Register Definition **** -// Address -#define SMUx0B_x84C8_ADDRESS 0x84c8 - -// Type -#define SMUx0B_x84C8_TYPE TYPE_SMUx0B -// Field Data -#define SMUx0B_x84C8_FstateDnHyst_7_OFFSET 0 -#define SMUx0B_x84C8_FstateDnHyst_7_WIDTH 8 -#define SMUx0B_x84C8_FstateDnHyst_7_MASK 0xff -#define SMUx0B_x84C8_FstateDnHyst_6_OFFSET 8 -#define SMUx0B_x84C8_FstateDnHyst_6_WIDTH 8 -#define SMUx0B_x84C8_FstateDnHyst_6_MASK 0xff00 -#define SMUx0B_x84C8_FstateDnHyst_5_OFFSET 16 -#define SMUx0B_x84C8_FstateDnHyst_5_WIDTH 8 -#define SMUx0B_x84C8_FstateDnHyst_5_MASK 0xff0000 -#define SMUx0B_x84C8_FstateDnHyst_4_OFFSET 24 -#define SMUx0B_x84C8_FstateDnHyst_4_WIDTH 8 -#define SMUx0B_x84C8_FstateDnHyst_4_MASK 0xff000000 - -/// SMUx0B_x84C8 -typedef union { - struct { ///< - UINT32 FstateDnHyst_7:8 ; ///< - UINT32 FstateDnHyst_6:8 ; ///< - UINT32 FstateDnHyst_5:8 ; ///< - UINT32 FstateDnHyst_4:8 ; ///< - } Field; ///< - UINT32 Value; ///< -} SMUx0B_x84C8_STRUCT; - -// **** SMUx0B_x84D0 Register Definition **** -// Address -#define SMUx0B_x84D0_ADDRESS 0x84d0 - -// Type -#define SMUx0B_x84D0_TYPE TYPE_SMUx0B -// Field Data -#define SMUx0B_x84D0_FstateDivTol_5_OFFSET 0 -#define SMUx0B_x84D0_FstateDivTol_5_WIDTH 7 -#define SMUx0B_x84D0_FstateDivTol_5_MASK 0x7f -#define SMUx0B_x84D0_Reserved_7_7_OFFSET 7 -#define SMUx0B_x84D0_Reserved_7_7_WIDTH 1 -#define SMUx0B_x84D0_Reserved_7_7_MASK 0x80 -#define SMUx0B_x84D0_FstateDivTol_4_OFFSET 8 -#define SMUx0B_x84D0_FstateDivTol_4_WIDTH 7 -#define SMUx0B_x84D0_FstateDivTol_4_MASK 0x7f00 -#define SMUx0B_x84D0_Reserved_15_15_OFFSET 15 -#define SMUx0B_x84D0_Reserved_15_15_WIDTH 1 -#define SMUx0B_x84D0_Reserved_15_15_MASK 0x8000 -#define SMUx0B_x84D0_FstateDivTol_3_OFFSET 16 -#define SMUx0B_x84D0_FstateDivTol_3_WIDTH 7 -#define SMUx0B_x84D0_FstateDivTol_3_MASK 0x7f0000 -#define SMUx0B_x84D0_Reserved_23_23_OFFSET 23 -#define SMUx0B_x84D0_Reserved_23_23_WIDTH 1 -#define SMUx0B_x84D0_Reserved_23_23_MASK 0x800000 -#define SMUx0B_x84D0_FstateDivTol_2_OFFSET 24 -#define SMUx0B_x84D0_FstateDivTol_2_WIDTH 7 -#define SMUx0B_x84D0_FstateDivTol_2_MASK 0x7f000000 -#define SMUx0B_x84D0_Reserved_31_31_OFFSET 31 -#define SMUx0B_x84D0_Reserved_31_31_WIDTH 1 -#define SMUx0B_x84D0_Reserved_31_31_MASK 0x80000000 - -/// SMUx0B_x84D0 -typedef union { - struct { ///< - UINT32 FstateDivTol_5:7 ; ///< - UINT32 Reserved_7_7:1 ; ///< - UINT32 FstateDivTol_4:7 ; ///< - UINT32 Reserved_15_15:1 ; ///< - UINT32 FstateDivTol_3:7 ; ///< - UINT32 Reserved_23_23:1 ; ///< - UINT32 FstateDivTol_2:7 ; ///< - UINT32 Reserved_31_31:1 ; ///< - } Field; ///< - UINT32 Value; ///< -} SMUx0B_x84D0_STRUCT; - -// **** SMUx0B_x84D4 Register Definition **** -// Address -#define SMUx0B_x84D4_ADDRESS 0x84d4 - -// Type -#define SMUx0B_x84D4_TYPE TYPE_SMUx0B -// Field Data -#define SMUx0B_x84D4_FstateDivTol_9_OFFSET 0 -#define SMUx0B_x84D4_FstateDivTol_9_WIDTH 7 -#define SMUx0B_x84D4_FstateDivTol_9_MASK 0x7f -#define SMUx0B_x84D4_Reserved_7_7_OFFSET 7 -#define SMUx0B_x84D4_Reserved_7_7_WIDTH 1 -#define SMUx0B_x84D4_Reserved_7_7_MASK 0x80 -#define SMUx0B_x84D4_FstateDivTol_8_OFFSET 8 -#define SMUx0B_x84D4_FstateDivTol_8_WIDTH 7 -#define SMUx0B_x84D4_FstateDivTol_8_MASK 0x7f00 -#define SMUx0B_x84D4_Reserved_15_15_OFFSET 15 -#define SMUx0B_x84D4_Reserved_15_15_WIDTH 1 -#define SMUx0B_x84D4_Reserved_15_15_MASK 0x8000 -#define SMUx0B_x84D4_FstateDivTol_7_OFFSET 16 -#define SMUx0B_x84D4_FstateDivTol_7_WIDTH 7 -#define SMUx0B_x84D4_FstateDivTol_7_MASK 0x7f0000 -#define SMUx0B_x84D4_Reserved_23_23_OFFSET 23 -#define SMUx0B_x84D4_Reserved_23_23_WIDTH 1 -#define SMUx0B_x84D4_Reserved_23_23_MASK 0x800000 -#define SMUx0B_x84D4_FstateDivTol_6_OFFSET 24 -#define SMUx0B_x84D4_FstateDivTol_6_WIDTH 7 -#define SMUx0B_x84D4_FstateDivTol_6_MASK 0x7f000000 -#define SMUx0B_x84D4_Reserved_31_31_OFFSET 31 -#define SMUx0B_x84D4_Reserved_31_31_WIDTH 1 -#define SMUx0B_x84D4_Reserved_31_31_MASK 0x80000000 - -/// SMUx0B_x84D4 -typedef union { - struct { ///< - UINT32 FstateDivTol_9:7 ; ///< - UINT32 Reserved_7_7:1 ; ///< - UINT32 FstateDivTol_8:7 ; ///< - UINT32 Reserved_15_15:1 ; ///< - UINT32 FstateDivTol_7:7 ; ///< - UINT32 Reserved_23_23:1 ; ///< - UINT32 FstateDivTol_6:7 ; ///< - UINT32 Reserved_31_31:1 ; ///< - } Field; ///< - UINT32 Value; ///< -} SMUx0B_x84D4_STRUCT; - -// **** SMUx0B_x84E0 Register Definition **** -// Address -#define SMUx0B_x84E0_ADDRESS 0x84e0 - -// Type -#define SMUx0B_x84E0_TYPE TYPE_SMUx0B -// Field Data -#define SMUx0B_x84E0_Reserved_6_0_OFFSET 0 -#define SMUx0B_x84E0_Reserved_6_0_WIDTH 7 -#define SMUx0B_x84E0_Reserved_6_0_MASK 0x7f -#define SMUx0B_x84E0_Reserved_7_7_OFFSET 7 -#define SMUx0B_x84E0_Reserved_7_7_WIDTH 1 -#define SMUx0B_x84E0_Reserved_7_7_MASK 0x80 -#define SMUx0B_x84E0_Reserved_14_8_OFFSET 8 -#define SMUx0B_x84E0_Reserved_14_8_WIDTH 7 -#define SMUx0B_x84E0_Reserved_14_8_MASK 0x7f00 -#define SMUx0B_x84E0_Reserved_15_15_OFFSET 15 -#define SMUx0B_x84E0_Reserved_15_15_WIDTH 1 -#define SMUx0B_x84E0_Reserved_15_15_MASK 0x8000 -#define SMUx0B_x84E0_BaseDiv_9_OFFSET 16 -#define SMUx0B_x84E0_BaseDiv_9_WIDTH 7 -#define SMUx0B_x84E0_BaseDiv_9_MASK 0x7f0000 -#define SMUx0B_x84E0_Reserved_23_23_OFFSET 23 -#define SMUx0B_x84E0_Reserved_23_23_WIDTH 1 -#define SMUx0B_x84E0_Reserved_23_23_MASK 0x800000 -#define SMUx0B_x84E0_BaseDiv_8_OFFSET 24 -#define SMUx0B_x84E0_BaseDiv_8_WIDTH 7 -#define SMUx0B_x84E0_BaseDiv_8_MASK 0x7f000000 -#define SMUx0B_x84E0_Reserved_31_31_OFFSET 31 -#define SMUx0B_x84E0_Reserved_31_31_WIDTH 1 -#define SMUx0B_x84E0_Reserved_31_31_MASK 0x80000000 - -/// SMUx0B_x84E0 -typedef union { - struct { ///< - UINT32 Reserved_6_0:7 ; ///< - UINT32 Reserved_7_7:1 ; ///< - UINT32 Reserved_14_8:7 ; ///< - UINT32 Reserved_15_15:1 ; ///< - UINT32 BaseDiv_9:7 ; ///< - UINT32 Reserved_23_23:1 ; ///< - UINT32 BaseDiv_8:7 ; ///< - UINT32 Reserved_31_31:1 ; ///< - } Field; ///< - UINT32 Value; ///< -} SMUx0B_x84E0_STRUCT; - -// **** SMUx0B_x84EC Register Definition **** -// Address -#define SMUx0B_x84EC_ADDRESS 0x84ec - -// Type -#define SMUx0B_x84EC_TYPE TYPE_SMUx0B -// Field Data -#define SMUx0B_x84EC_SaveStateDone_OFFSET 0 -#define SMUx0B_x84EC_SaveStateDone_WIDTH 1 -#define SMUx0B_x84EC_SaveStateDone_MASK 0x1 -#define SMUx0B_x84EC_Reserved_31_1_OFFSET 1 -#define SMUx0B_x84EC_Reserved_31_1_WIDTH 31 -#define SMUx0B_x84EC_Reserved_31_1_MASK 0xfffffffe - -/// SMUx0B_x84EC -typedef union { - struct { ///< - UINT32 SaveStateDone:1 ; ///< - UINT32 Reserved_31_1:31; ///< - } Field; ///< - UINT32 Value; ///< -} SMUx0B_x84EC_STRUCT; - -// **** SMUx0B_x8580 Register Definition **** -// Address -#define SMUx0B_x8580_ADDRESS 0x8580 - -// Type -#define SMUx0B_x8580_TYPE TYPE_SMUx0B -// Field Data -#define SMUx0B_x8580_PdmEn_OFFSET 0 -#define SMUx0B_x8580_PdmEn_WIDTH 1 -#define SMUx0B_x8580_PdmEn_MASK 0x1 -#define SMUx0B_x8580_Reserved_9_1_OFFSET 1 -#define SMUx0B_x8580_Reserved_9_1_WIDTH 9 -#define SMUx0B_x8580_Reserved_9_1_MASK 0x3fe -#define SMUx0B_x8580_PdmCacEn_OFFSET 10 -#define SMUx0B_x8580_PdmCacEn_WIDTH 1 -#define SMUx0B_x8580_PdmCacEn_MASK 0x400 -#define SMUx0B_x8580_Reserved_11_11_OFFSET 11 -#define SMUx0B_x8580_Reserved_11_11_WIDTH 1 -#define SMUx0B_x8580_Reserved_11_11_MASK 0x800 -#define SMUx0B_x8580_PdmUnit_OFFSET 12 -#define SMUx0B_x8580_PdmUnit_WIDTH 4 -#define SMUx0B_x8580_PdmUnit_MASK 0xf000 -#define SMUx0B_x8580_PdmPeriod_OFFSET 16 -#define SMUx0B_x8580_PdmPeriod_WIDTH 16 -#define SMUx0B_x8580_PdmPeriod_MASK 0xffff0000 - -/// SMUx0B_x8580 -typedef union { - struct { ///< - UINT32 PdmEn:1 ; ///< - UINT32 Reserved_9_1:9 ; ///< - UINT32 PdmCacEn:1 ; ///< - UINT32 Reserved_11_11:1 ; ///< - UINT32 PdmUnit:4 ; ///< - UINT32 PdmPeriod:16; ///< - } Field; ///< - UINT32 Value; ///< -} SMUx0B_x8580_STRUCT; - -// **** SMUx0B_x858C Register Definition **** -// Address -#define SMUx0B_x858C_ADDRESS 0x858c - -// Type -#define SMUx0B_x858C_TYPE TYPE_SMUx0B -// Field Data -#define SMUx0B_x858C_Rx_OFFSET 0 -#define SMUx0B_x858C_Rx_WIDTH 1 -#define SMUx0B_x858C_Rx_MASK 0x1 -#define SMUx0B_x858C_Tx_OFFSET 1 -#define SMUx0B_x858C_Tx_WIDTH 1 -#define SMUx0B_x858C_Tx_MASK 0x2 -#define SMUx0B_x858C_Core_OFFSET 2 -#define SMUx0B_x858C_Core_WIDTH 1 -#define SMUx0B_x858C_Core_MASK 0x4 -#define SMUx0B_x858C_Reserved_15_3_OFFSET 3 -#define SMUx0B_x858C_Reserved_15_3_WIDTH 13 -#define SMUx0B_x858C_Reserved_15_3_MASK 0xfff8 -#define SMUx0B_x858C_LowerLaneId_OFFSET 16 -#define SMUx0B_x858C_LowerLaneId_WIDTH 8 -#define SMUx0B_x858C_LowerLaneId_MASK 0xff0000 -#define SMUx0B_x858C_UpperLaneId_OFFSET 24 -#define SMUx0B_x858C_UpperLaneId_WIDTH 8 -#define SMUx0B_x858C_UpperLaneId_MASK 0xff000000 - -/// SMUx0B_x858C -typedef union { - struct { ///< - UINT32 Rx:1 ; ///< - UINT32 Tx:1 ; ///< - UINT32 Core:1 ; ///< - UINT32 Reserved_15_3:13; ///< - UINT32 LowerLaneId:8 ; ///< - UINT32 UpperLaneId:8 ; ///< - } Field; ///< - UINT32 Value; ///< -} SMUx0B_x858C_STRUCT; - -// **** SMUx0B_x859C Register Definition **** -// Address -#define SMUx0B_x859C_ADDRESS 0x859c - -// Type -#define SMUx0B_x859C_TYPE TYPE_SMUx0B -// Field Data -#define SMUx0B_x859C_PllId_OFFSET 0 -#define SMUx0B_x859C_PllId_WIDTH 1 -#define SMUx0B_x859C_PllId_MASK 0x1 -#define SMUx0B_x859C_Reserved_31_1_OFFSET 1 -#define SMUx0B_x859C_Reserved_31_1_WIDTH 31 -#define SMUx0B_x859C_Reserved_31_1_MASK 0xfffffffe - -/// SMUx0B_x859C -typedef union { - struct { ///< - UINT32 PllId:1 ; ///< - UINT32 Reserved_31_1:31; ///< - } Field; ///< - UINT32 Value; ///< -} SMUx0B_x859C_STRUCT; - -// **** SMUx0B_x8600 Register Definition **** -// Address -#define SMUx0B_x8600_ADDRESS 0x8600 - -// Type -#define SMUx0B_x8600_TYPE TYPE_SMUx0B -// Field Data -#define SMUx0B_x8600_Txn1MBusAddr_7_0__OFFSET 0 -#define SMUx0B_x8600_Txn1MBusAddr_7_0__WIDTH 8 -#define SMUx0B_x8600_Txn1MBusAddr_7_0__MASK 0xff -#define SMUx0B_x8600_MemAddr_7_0__OFFSET 8 -#define SMUx0B_x8600_MemAddr_7_0__WIDTH 8 -#define SMUx0B_x8600_MemAddr_7_0__MASK 0xff00 -#define SMUx0B_x8600_MemAddr_15_8__OFFSET 16 -#define SMUx0B_x8600_MemAddr_15_8__WIDTH 8 -#define SMUx0B_x8600_MemAddr_15_8__MASK 0xff0000 -#define SMUx0B_x8600_TransactionCount_OFFSET 24 -#define SMUx0B_x8600_TransactionCount_WIDTH 8 -#define SMUx0B_x8600_TransactionCount_MASK 0xff000000 - -/// SMUx0B_x8600 -typedef union { - struct { ///< - UINT32 Txn1MBusAddr_7_0_:8 ; ///< - UINT32 MemAddr_7_0_:8 ; ///< - UINT32 MemAddr_15_8_:8 ; ///< - UINT32 TransactionCount:8 ; ///< - } Field; ///< - UINT32 Value; ///< -} SMUx0B_x8600_STRUCT; - -// **** SMUx0B_x8604 Register Definition **** -// Address -#define SMUx0B_x8604_ADDRESS 0x8604 - -// Type -#define SMUx0B_x8604_TYPE TYPE_SMUx0B -// Field Data -#define SMUx0B_x8604_Txn1TransferLength_7_0__OFFSET 0 -#define SMUx0B_x8604_Txn1TransferLength_7_0__WIDTH 8 -#define SMUx0B_x8604_Txn1TransferLength_7_0__MASK 0xff -#define SMUx0B_x8604_Txn1MBusAddr_31_24__OFFSET 8 -#define SMUx0B_x8604_Txn1MBusAddr_31_24__WIDTH 8 -#define SMUx0B_x8604_Txn1MBusAddr_31_24__MASK 0xff00 -#define SMUx0B_x8604_Txn1MBusAddr_23_16__OFFSET 16 -#define SMUx0B_x8604_Txn1MBusAddr_23_16__WIDTH 8 -#define SMUx0B_x8604_Txn1MBusAddr_23_16__MASK 0xff0000 -#define SMUx0B_x8604_Txn1MBusAddr_15_8__OFFSET 24 -#define SMUx0B_x8604_Txn1MBusAddr_15_8__WIDTH 8 -#define SMUx0B_x8604_Txn1MBusAddr_15_8__MASK 0xff000000 - -/// SMUx0B_x8604 -typedef union { - struct { ///< - UINT32 Txn1TransferLength_7_0_:8 ; ///< - UINT32 Txn1MBusAddr_31_24_:8 ; ///< - UINT32 Txn1MBusAddr_23_16_:8 ; ///< - UINT32 Txn1MBusAddr_15_8_:8 ; ///< - } Field; ///< - UINT32 Value; ///< -} SMUx0B_x8604_STRUCT; - -// **** SMUx0B_x8608 Register Definition **** -// Address -#define SMUx0B_x8608_ADDRESS 0x8608 - -// Type -#define SMUx0B_x8608_TYPE TYPE_SMUx0B -// Field Data -#define SMUx0B_x8608_Txn2Mbusaddr158_OFFSET 0 -#define SMUx0B_x8608_Txn2Mbusaddr158_WIDTH 8 -#define SMUx0B_x8608_Txn2Mbusaddr158_MASK 0xff -#define SMUx0B_x8608_Txn2Mbusaddr70_OFFSET 8 -#define SMUx0B_x8608_Txn2Mbusaddr70_WIDTH 8 -#define SMUx0B_x8608_Txn2Mbusaddr70_MASK 0xff00 -#define SMUx0B_x8608_Txn1Mode_OFFSET 16 -#define SMUx0B_x8608_Txn1Mode_WIDTH 2 -#define SMUx0B_x8608_Txn1Mode_MASK 0x30000 -#define SMUx0B_x8608_Txn1Static_OFFSET 18 -#define SMUx0B_x8608_Txn1Static_WIDTH 1 -#define SMUx0B_x8608_Txn1Static_MASK 0x40000 -#define SMUx0B_x8608_Txn1Overlap_OFFSET 19 -#define SMUx0B_x8608_Txn1Overlap_WIDTH 1 -#define SMUx0B_x8608_Txn1Overlap_MASK 0x80000 -#define SMUx0B_x8608_Txn1Spare_OFFSET 20 -#define SMUx0B_x8608_Txn1Spare_WIDTH 4 -#define SMUx0B_x8608_Txn1Spare_MASK 0xf00000 -#define SMUx0B_x8608_Txn1TransferLength_13_8__OFFSET 24 -#define SMUx0B_x8608_Txn1TransferLength_13_8__WIDTH 6 -#define SMUx0B_x8608_Txn1TransferLength_13_8__MASK 0x3f000000 -#define SMUx0B_x8608_Txn1Tsize_OFFSET 30 -#define SMUx0B_x8608_Txn1Tsize_WIDTH 2 -#define SMUx0B_x8608_Txn1Tsize_MASK 0xc0000000 - -/// SMUx0B_x8608 -typedef union { - struct { ///< - UINT32 Txn2Mbusaddr158:8 ; ///< - UINT32 Txn2Mbusaddr70:8 ; ///< - UINT32 Txn1Mode:2 ; ///< - UINT32 Txn1Static:1 ; ///< - UINT32 Txn1Overlap:1 ; ///< - UINT32 Txn1Spare:4 ; ///< - UINT32 Txn1TransferLength_13_8_:6 ; ///< - UINT32 Txn1Tsize:2 ; ///< - } Field; ///< - UINT32 Value; ///< -} SMUx0B_x8608_STRUCT; - -// **** SMUx0B_x860C Register Definition **** -// Address -#define SMUx0B_x860C_ADDRESS 0x860c - -// Type -#define SMUx0B_x860C_TYPE TYPE_SMUx0B -// Field Data -#define SMUx0B_x860C_Txn2TransferLength138_OFFSET 0 -#define SMUx0B_x860C_Txn2TransferLength138_WIDTH 6 -#define SMUx0B_x860C_Txn2TransferLength138_MASK 0x3f -#define SMUx0B_x860C_Txn2Tsize_OFFSET 6 -#define SMUx0B_x860C_Txn2Tsize_WIDTH 2 -#define SMUx0B_x860C_Txn2Tsize_MASK 0xc0 -#define SMUx0B_x860C_Txn2TransferLength70_OFFSET 8 -#define SMUx0B_x860C_Txn2TransferLength70_WIDTH 8 -#define SMUx0B_x860C_Txn2TransferLength70_MASK 0xff00 -#define SMUx0B_x860C_Txn2MBusAddr3124_OFFSET 16 -#define SMUx0B_x860C_Txn2MBusAddr3124_WIDTH 8 -#define SMUx0B_x860C_Txn2MBusAddr3124_MASK 0xff0000 -#define SMUx0B_x860C_Txn2MBusAddr2316_OFFSET 24 -#define SMUx0B_x860C_Txn2MBusAddr2316_WIDTH 8 -#define SMUx0B_x860C_Txn2MBusAddr2316_MASK 0xff000000 - -/// SMUx0B_x860C -typedef union { - struct { ///< - UINT32 Txn2TransferLength138:6 ; ///< - UINT32 Txn2Tsize:2 ; ///< - UINT32 Txn2TransferLength70:8 ; ///< - UINT32 Txn2MBusAddr3124:8 ; ///< - UINT32 Txn2MBusAddr2316:8 ; ///< - } Field; ///< - UINT32 Value; ///< -} SMUx0B_x860C_STRUCT; - -// **** SMUx0B_x8610 Register Definition **** -// Address -#define SMUx0B_x8610_ADDRESS 0x8610 - -// Type -#define SMUx0B_x8610_TYPE TYPE_SMUx0B -// Field Data -#define SMUx0B_x8610_Txn3MBusAddr2316_OFFSET 0 -#define SMUx0B_x8610_Txn3MBusAddr2316_WIDTH 8 -#define SMUx0B_x8610_Txn3MBusAddr2316_MASK 0xff -#define SMUx0B_x8610_Txn3MBusAddr158_OFFSET 8 -#define SMUx0B_x8610_Txn3MBusAddr158_WIDTH 8 -#define SMUx0B_x8610_Txn3MBusAddr158_MASK 0xff00 -#define SMUx0B_x8610_Txn3MBusAddr70_OFFSET 16 -#define SMUx0B_x8610_Txn3MBusAddr70_WIDTH 8 -#define SMUx0B_x8610_Txn3MBusAddr70_MASK 0xff0000 -#define SMUx0B_x8610_Txn2Mode_OFFSET 24 -#define SMUx0B_x8610_Txn2Mode_WIDTH 2 -#define SMUx0B_x8610_Txn2Mode_MASK 0x3000000 -#define SMUx0B_x8610_Txn2Static_OFFSET 26 -#define SMUx0B_x8610_Txn2Static_WIDTH 1 -#define SMUx0B_x8610_Txn2Static_MASK 0x4000000 -#define SMUx0B_x8610_Txn2Overlap_OFFSET 27 -#define SMUx0B_x8610_Txn2Overlap_WIDTH 1 -#define SMUx0B_x8610_Txn2Overlap_MASK 0x8000000 -#define SMUx0B_x8610_Txn2Spare_OFFSET 28 -#define SMUx0B_x8610_Txn2Spare_WIDTH 4 -#define SMUx0B_x8610_Txn2Spare_MASK 0xf0000000 - -/// SMUx0B_x8610 -typedef union { - struct { ///< - UINT32 Txn3MBusAddr2316:8 ; ///< - UINT32 Txn3MBusAddr158:8 ; ///< - UINT32 Txn3MBusAddr70:8 ; ///< - UINT32 Txn2Mode:2 ; ///< - UINT32 Txn2Static:1 ; ///< - UINT32 Txn2Overlap:1 ; ///< - UINT32 Txn2Spare:4 ; ///< - } Field; ///< - UINT32 Value; ///< -} SMUx0B_x8610_STRUCT; - -// **** SMUx0B_x8614 Register Definition **** -// Address -#define SMUx0B_x8614_ADDRESS 0x8614 - -// Type -#define SMUx0B_x8614_TYPE TYPE_SMUx0B -// Field Data -#define SMUx0B_x8614_Txn3Mode_OFFSET 0 -#define SMUx0B_x8614_Txn3Mode_WIDTH 2 -#define SMUx0B_x8614_Txn3Mode_MASK 0x3 -#define SMUx0B_x8614_Txn3Static_OFFSET 2 -#define SMUx0B_x8614_Txn3Static_WIDTH 1 -#define SMUx0B_x8614_Txn3Static_MASK 0x4 -#define SMUx0B_x8614_Txn3Overlap_OFFSET 3 -#define SMUx0B_x8614_Txn3Overlap_WIDTH 1 -#define SMUx0B_x8614_Txn3Overlap_MASK 0x8 -#define SMUx0B_x8614_Txn3Spare_OFFSET 4 -#define SMUx0B_x8614_Txn3Spare_WIDTH 4 -#define SMUx0B_x8614_Txn3Spare_MASK 0xf0 -#define SMUx0B_x8614_Txn3TransferLength138_OFFSET 8 -#define SMUx0B_x8614_Txn3TransferLength138_WIDTH 6 -#define SMUx0B_x8614_Txn3TransferLength138_MASK 0x3f00 -#define SMUx0B_x8614_Txn3Tsize_OFFSET 14 -#define SMUx0B_x8614_Txn3Tsize_WIDTH 2 -#define SMUx0B_x8614_Txn3Tsize_MASK 0xc000 -#define SMUx0B_x8614_Txn3TransferLength70_OFFSET 16 -#define SMUx0B_x8614_Txn3TransferLength70_WIDTH 8 -#define SMUx0B_x8614_Txn3TransferLength70_MASK 0xff0000 -#define SMUx0B_x8614_Txn3MBusAddr3124_OFFSET 24 -#define SMUx0B_x8614_Txn3MBusAddr3124_WIDTH 8 -#define SMUx0B_x8614_Txn3MBusAddr3124_MASK 0xff000000 - -/// SMUx0B_x8614 -typedef union { - struct { ///< - UINT32 Txn3Mode:2 ; ///< - UINT32 Txn3Static:1 ; ///< - UINT32 Txn3Overlap:1 ; ///< - UINT32 Txn3Spare:4 ; ///< - UINT32 Txn3TransferLength138:6 ; ///< - UINT32 Txn3Tsize:2 ; ///< - UINT32 Txn3TransferLength70:8 ; ///< - UINT32 Txn3MBusAddr3124:8 ; ///< - } Field; ///< - UINT32 Value; ///< -} SMUx0B_x8614_STRUCT; - -// **** SMUx0B_x8618 Register Definition **** -// Address -#define SMUx0B_x8618_ADDRESS 0x8618 - -// Type -#define SMUx0B_x8618_TYPE TYPE_SMUx0B -// Field Data -#define SMUx0B_x8618_Txn4MBusAddr3124_OFFSET 0 -#define SMUx0B_x8618_Txn4MBusAddr3124_WIDTH 8 -#define SMUx0B_x8618_Txn4MBusAddr3124_MASK 0xff -#define SMUx0B_x8618_Txn4MBusAddr2316_OFFSET 8 -#define SMUx0B_x8618_Txn4MBusAddr2316_WIDTH 8 -#define SMUx0B_x8618_Txn4MBusAddr2316_MASK 0xff00 -#define SMUx0B_x8618_Txn4MBusAddr158_OFFSET 16 -#define SMUx0B_x8618_Txn4MBusAddr158_WIDTH 8 -#define SMUx0B_x8618_Txn4MBusAddr158_MASK 0xff0000 -#define SMUx0B_x8618_Txn4MBusAddr70_OFFSET 24 -#define SMUx0B_x8618_Txn4MBusAddr70_WIDTH 8 -#define SMUx0B_x8618_Txn4MBusAddr70_MASK 0xff000000 - -/// SMUx0B_x8618 -typedef union { - struct { ///< - UINT32 Txn4MBusAddr3124:8 ; ///< - UINT32 Txn4MBusAddr2316:8 ; ///< - UINT32 Txn4MBusAddr158:8 ; ///< - UINT32 Txn4MBusAddr70:8 ; ///< - } Field; ///< - UINT32 Value; ///< -} SMUx0B_x8618_STRUCT; - -// **** SMUx0B_x861C Register Definition **** -// Address -#define SMUx0B_x861C_ADDRESS 0x861c - -// Type -#define SMUx0B_x861C_TYPE TYPE_SMUx0B -// Field Data -#define SMUx0B_x861C_Txn5Mbusaddr70_OFFSET 0 -#define SMUx0B_x861C_Txn5Mbusaddr70_WIDTH 8 -#define SMUx0B_x861C_Txn5Mbusaddr70_MASK 0xff -#define SMUx0B_x861C_Txn4Mode_OFFSET 8 -#define SMUx0B_x861C_Txn4Mode_WIDTH 2 -#define SMUx0B_x861C_Txn4Mode_MASK 0x300 -#define SMUx0B_x861C_Txn4Static_OFFSET 10 -#define SMUx0B_x861C_Txn4Static_WIDTH 1 -#define SMUx0B_x861C_Txn4Static_MASK 0x400 -#define SMUx0B_x861C_Txn4Overlap_OFFSET 11 -#define SMUx0B_x861C_Txn4Overlap_WIDTH 1 -#define SMUx0B_x861C_Txn4Overlap_MASK 0x800 -#define SMUx0B_x861C_Txn4Spare_OFFSET 12 -#define SMUx0B_x861C_Txn4Spare_WIDTH 4 -#define SMUx0B_x861C_Txn4Spare_MASK 0xf000 -#define SMUx0B_x861C_Txn4TransferLength138_OFFSET 16 -#define SMUx0B_x861C_Txn4TransferLength138_WIDTH 6 -#define SMUx0B_x861C_Txn4TransferLength138_MASK 0x3f0000 -#define SMUx0B_x861C_Txn4Tsize_OFFSET 22 -#define SMUx0B_x861C_Txn4Tsize_WIDTH 2 -#define SMUx0B_x861C_Txn4Tsize_MASK 0xc00000 -#define SMUx0B_x861C_Txn4TransferLength70_OFFSET 24 -#define SMUx0B_x861C_Txn4TransferLength70_WIDTH 8 -#define SMUx0B_x861C_Txn4TransferLength70_MASK 0xff000000 - -/// SMUx0B_x861C -typedef union { - struct { ///< - UINT32 Txn5Mbusaddr70:8 ; ///< - UINT32 Txn4Mode:2 ; ///< - UINT32 Txn4Static:1 ; ///< - UINT32 Txn4Overlap:1 ; ///< - UINT32 Txn4Spare:4 ; ///< - UINT32 Txn4TransferLength138:6 ; ///< - UINT32 Txn4Tsize:2 ; ///< - UINT32 Txn4TransferLength70:8 ; ///< - } Field; ///< - UINT32 Value; ///< -} SMUx0B_x861C_STRUCT; - -// **** SMUx0B_x8620 Register Definition **** -// Address -#define SMUx0B_x8620_ADDRESS 0x8620 - -// Type -#define SMUx0B_x8620_TYPE TYPE_SMUx0B -// Field Data -#define SMUx0B_x8620_Txn5TransferLength70_OFFSET 0 -#define SMUx0B_x8620_Txn5TransferLength70_WIDTH 8 -#define SMUx0B_x8620_Txn5TransferLength70_MASK 0xff -#define SMUx0B_x8620_Txn5MBusAddr3124_OFFSET 8 -#define SMUx0B_x8620_Txn5MBusAddr3124_WIDTH 8 -#define SMUx0B_x8620_Txn5MBusAddr3124_MASK 0xff00 -#define SMUx0B_x8620_Txn5MBusAddr2316_OFFSET 16 -#define SMUx0B_x8620_Txn5MBusAddr2316_WIDTH 8 -#define SMUx0B_x8620_Txn5MBusAddr2316_MASK 0xff0000 -#define SMUx0B_x8620_Txn5MBusAddr158_OFFSET 24 -#define SMUx0B_x8620_Txn5MBusAddr158_WIDTH 8 -#define SMUx0B_x8620_Txn5MBusAddr158_MASK 0xff000000 - -/// SMUx0B_x8620 -typedef union { - struct { ///< - UINT32 Txn5TransferLength70:8 ; ///< - UINT32 Txn5MBusAddr3124:8 ; ///< - UINT32 Txn5MBusAddr2316:8 ; ///< - UINT32 Txn5MBusAddr158:8 ; ///< - } Field; ///< - UINT32 Value; ///< -} SMUx0B_x8620_STRUCT; - -// **** SMUx0B_x8624 Register Definition **** -// Address -#define SMUx0B_x8624_ADDRESS 0x8624 - -// Type -#define SMUx0B_x8624_TYPE TYPE_SMUx0B -// Field Data -#define SMUx0B_x8624_Txn6MBusAddr158_OFFSET 0 -#define SMUx0B_x8624_Txn6MBusAddr158_WIDTH 8 -#define SMUx0B_x8624_Txn6MBusAddr158_MASK 0xff -#define SMUx0B_x8624_Txn6MBusAddr70_OFFSET 8 -#define SMUx0B_x8624_Txn6MBusAddr70_WIDTH 8 -#define SMUx0B_x8624_Txn6MBusAddr70_MASK 0xff00 -#define SMUx0B_x8624_Txn5Mode_OFFSET 16 -#define SMUx0B_x8624_Txn5Mode_WIDTH 2 -#define SMUx0B_x8624_Txn5Mode_MASK 0x30000 -#define SMUx0B_x8624_Txn5Static_OFFSET 18 -#define SMUx0B_x8624_Txn5Static_WIDTH 1 -#define SMUx0B_x8624_Txn5Static_MASK 0x40000 -#define SMUx0B_x8624_Txn5Overlap_OFFSET 19 -#define SMUx0B_x8624_Txn5Overlap_WIDTH 1 -#define SMUx0B_x8624_Txn5Overlap_MASK 0x80000 -#define SMUx0B_x8624_Txn5Spare_OFFSET 20 -#define SMUx0B_x8624_Txn5Spare_WIDTH 4 -#define SMUx0B_x8624_Txn5Spare_MASK 0xf00000 -#define SMUx0B_x8624_Txn5TransferLength138_OFFSET 24 -#define SMUx0B_x8624_Txn5TransferLength138_WIDTH 6 -#define SMUx0B_x8624_Txn5TransferLength138_MASK 0x3f000000 -#define SMUx0B_x8624_Txn5Tsize_OFFSET 30 -#define SMUx0B_x8624_Txn5Tsize_WIDTH 2 -#define SMUx0B_x8624_Txn5Tsize_MASK 0xc0000000 - -/// SMUx0B_x8624 -typedef union { - struct { ///< - UINT32 Txn6MBusAddr158:8 ; ///< - UINT32 Txn6MBusAddr70:8 ; ///< - UINT32 Txn5Mode:2 ; ///< - UINT32 Txn5Static:1 ; ///< - UINT32 Txn5Overlap:1 ; ///< - UINT32 Txn5Spare:4 ; ///< - UINT32 Txn5TransferLength138:6 ; ///< - UINT32 Txn5Tsize:2 ; ///< - } Field; ///< - UINT32 Value; ///< -} SMUx0B_x8624_STRUCT; - -// **** SMUx0B_x8628 Register Definition **** -// Address -#define SMUx0B_x8628_ADDRESS 0x8628 - -// Type -#define SMUx0B_x8628_TYPE TYPE_SMUx0B -// Field Data -#define SMUx0B_x8628_Txn6TransferLength138_OFFSET 0 -#define SMUx0B_x8628_Txn6TransferLength138_WIDTH 6 -#define SMUx0B_x8628_Txn6TransferLength138_MASK 0x3f -#define SMUx0B_x8628_Txn6Tsize_OFFSET 6 -#define SMUx0B_x8628_Txn6Tsize_WIDTH 2 -#define SMUx0B_x8628_Txn6Tsize_MASK 0xc0 -#define SMUx0B_x8628_Txn6TransferLength70_OFFSET 8 -#define SMUx0B_x8628_Txn6TransferLength70_WIDTH 8 -#define SMUx0B_x8628_Txn6TransferLength70_MASK 0xff00 -#define SMUx0B_x8628_Txn6MBusAddr3124_OFFSET 16 -#define SMUx0B_x8628_Txn6MBusAddr3124_WIDTH 8 -#define SMUx0B_x8628_Txn6MBusAddr3124_MASK 0xff0000 -#define SMUx0B_x8628_Txn6MBusAddr2316_OFFSET 24 -#define SMUx0B_x8628_Txn6MBusAddr2316_WIDTH 8 -#define SMUx0B_x8628_Txn6MBusAddr2316_MASK 0xff000000 - -/// SMUx0B_x8628 -typedef union { - struct { ///< - UINT32 Txn6TransferLength138:6 ; ///< - UINT32 Txn6Tsize:2 ; ///< - UINT32 Txn6TransferLength70:8 ; ///< - UINT32 Txn6MBusAddr3124:8 ; ///< - UINT32 Txn6MBusAddr2316:8 ; ///< - } Field; ///< - UINT32 Value; ///< -} SMUx0B_x8628_STRUCT; - -// **** SMUx0B_x862C Register Definition **** -// Address -#define SMUx0B_x862C_ADDRESS 0x862c - -// Type -#define SMUx0B_x862C_TYPE TYPE_SMUx0B -// Field Data -#define SMUx0B_x862C_Txn7MBusAddr2316_OFFSET 0 -#define SMUx0B_x862C_Txn7MBusAddr2316_WIDTH 8 -#define SMUx0B_x862C_Txn7MBusAddr2316_MASK 0xff -#define SMUx0B_x862C_Txn7MBusAddr158_OFFSET 8 -#define SMUx0B_x862C_Txn7MBusAddr158_WIDTH 8 -#define SMUx0B_x862C_Txn7MBusAddr158_MASK 0xff00 -#define SMUx0B_x862C_Txn7MBusAddr70_OFFSET 16 -#define SMUx0B_x862C_Txn7MBusAddr70_WIDTH 8 -#define SMUx0B_x862C_Txn7MBusAddr70_MASK 0xff0000 -#define SMUx0B_x862C_Txn6Mode_OFFSET 24 -#define SMUx0B_x862C_Txn6Mode_WIDTH 2 -#define SMUx0B_x862C_Txn6Mode_MASK 0x3000000 -#define SMUx0B_x862C_Txn6Static_OFFSET 26 -#define SMUx0B_x862C_Txn6Static_WIDTH 1 -#define SMUx0B_x862C_Txn6Static_MASK 0x4000000 -#define SMUx0B_x862C_Txn6Overlap_OFFSET 27 -#define SMUx0B_x862C_Txn6Overlap_WIDTH 1 -#define SMUx0B_x862C_Txn6Overlap_MASK 0x8000000 -#define SMUx0B_x862C_Txn6Spare_OFFSET 28 -#define SMUx0B_x862C_Txn6Spare_WIDTH 4 -#define SMUx0B_x862C_Txn6Spare_MASK 0xf0000000 - -/// SMUx0B_x862C -typedef union { - struct { ///< - UINT32 Txn7MBusAddr2316:8 ; ///< - UINT32 Txn7MBusAddr158:8 ; ///< - UINT32 Txn7MBusAddr70:8 ; ///< - UINT32 Txn6Mode:2 ; ///< - UINT32 Txn6Static:1 ; ///< - UINT32 Txn6Overlap:1 ; ///< - UINT32 Txn6Spare:4 ; ///< - } Field; ///< - UINT32 Value; ///< -} SMUx0B_x862C_STRUCT; - -// **** SMUx0B_x8630 Register Definition **** -// Address -#define SMUx0B_x8630_ADDRESS 0x8630 - -// Type -#define SMUx0B_x8630_TYPE TYPE_SMUx0B -// Field Data -#define SMUx0B_x8630_Txn7Mode_OFFSET 0 -#define SMUx0B_x8630_Txn7Mode_WIDTH 2 -#define SMUx0B_x8630_Txn7Mode_MASK 0x3 -#define SMUx0B_x8630_Txn7Static_OFFSET 2 -#define SMUx0B_x8630_Txn7Static_WIDTH 1 -#define SMUx0B_x8630_Txn7Static_MASK 0x4 -#define SMUx0B_x8630_Txn7Overlap_OFFSET 3 -#define SMUx0B_x8630_Txn7Overlap_WIDTH 1 -#define SMUx0B_x8630_Txn7Overlap_MASK 0x8 -#define SMUx0B_x8630_Txn7Spare_OFFSET 4 -#define SMUx0B_x8630_Txn7Spare_WIDTH 4 -#define SMUx0B_x8630_Txn7Spare_MASK 0xf0 -#define SMUx0B_x8630_Txn7TransferLength138_OFFSET 8 -#define SMUx0B_x8630_Txn7TransferLength138_WIDTH 6 -#define SMUx0B_x8630_Txn7TransferLength138_MASK 0x3f00 -#define SMUx0B_x8630_Txn7Tsize_OFFSET 14 -#define SMUx0B_x8630_Txn7Tsize_WIDTH 2 -#define SMUx0B_x8630_Txn7Tsize_MASK 0xc000 -#define SMUx0B_x8630_Txn7TransferLength70_OFFSET 16 -#define SMUx0B_x8630_Txn7TransferLength70_WIDTH 8 -#define SMUx0B_x8630_Txn7TransferLength70_MASK 0xff0000 -#define SMUx0B_x8630_Txn7MBusAddr3124_OFFSET 24 -#define SMUx0B_x8630_Txn7MBusAddr3124_WIDTH 8 -#define SMUx0B_x8630_Txn7MBusAddr3124_MASK 0xff000000 - -/// SMUx0B_x8630 -typedef union { - struct { ///< - UINT32 Txn7Mode:2 ; ///< - UINT32 Txn7Static:1 ; ///< - UINT32 Txn7Overlap:1 ; ///< - UINT32 Txn7Spare:4 ; ///< - UINT32 Txn7TransferLength138:6 ; ///< - UINT32 Txn7Tsize:2 ; ///< - UINT32 Txn7TransferLength70:8 ; ///< - UINT32 Txn7MBusAddr3124:8 ; ///< - } Field; ///< - UINT32 Value; ///< -} SMUx0B_x8630_STRUCT; - -// **** SMUx0B_x8634 Register Definition **** -// Address -#define SMUx0B_x8634_ADDRESS 0x8634 - -// Type -#define SMUx0B_x8634_TYPE TYPE_SMUx0B -// Field Data -#define SMUx0B_x8634_Txn8MBusAddr3124_OFFSET 0 -#define SMUx0B_x8634_Txn8MBusAddr3124_WIDTH 8 -#define SMUx0B_x8634_Txn8MBusAddr3124_MASK 0xff -#define SMUx0B_x8634_Txn8MBusAddr2316_OFFSET 8 -#define SMUx0B_x8634_Txn8MBusAddr2316_WIDTH 8 -#define SMUx0B_x8634_Txn8MBusAddr2316_MASK 0xff00 -#define SMUx0B_x8634_Txn8MBusAddr158_OFFSET 16 -#define SMUx0B_x8634_Txn8MBusAddr158_WIDTH 8 -#define SMUx0B_x8634_Txn8MBusAddr158_MASK 0xff0000 -#define SMUx0B_x8634_Txn8MBusAddr70_OFFSET 24 -#define SMUx0B_x8634_Txn8MBusAddr70_WIDTH 8 -#define SMUx0B_x8634_Txn8MBusAddr70_MASK 0xff000000 - -/// SMUx0B_x8634 -typedef union { - struct { ///< - UINT32 Txn8MBusAddr3124:8 ; ///< - UINT32 Txn8MBusAddr2316:8 ; ///< - UINT32 Txn8MBusAddr158:8 ; ///< - UINT32 Txn8MBusAddr70:8 ; ///< - } Field; ///< - UINT32 Value; ///< -} SMUx0B_x8634_STRUCT; - -// **** SMUx0B_x8638 Register Definition **** -// Address -#define SMUx0B_x8638_ADDRESS 0x8638 - -// Type -#define SMUx0B_x8638_TYPE TYPE_SMUx0B -// Field Data -#define SMUx0B_x8638_Txn9MBusAddr70_OFFSET 0 -#define SMUx0B_x8638_Txn9MBusAddr70_WIDTH 8 -#define SMUx0B_x8638_Txn9MBusAddr70_MASK 0xff -#define SMUx0B_x8638_Txn8Mode_OFFSET 8 -#define SMUx0B_x8638_Txn8Mode_WIDTH 2 -#define SMUx0B_x8638_Txn8Mode_MASK 0x300 -#define SMUx0B_x8638_Txn8Static_OFFSET 10 -#define SMUx0B_x8638_Txn8Static_WIDTH 1 -#define SMUx0B_x8638_Txn8Static_MASK 0x400 -#define SMUx0B_x8638_Txn8Overlap_OFFSET 11 -#define SMUx0B_x8638_Txn8Overlap_WIDTH 1 -#define SMUx0B_x8638_Txn8Overlap_MASK 0x800 -#define SMUx0B_x8638_Txn8Spare_OFFSET 12 -#define SMUx0B_x8638_Txn8Spare_WIDTH 4 -#define SMUx0B_x8638_Txn8Spare_MASK 0xf000 -#define SMUx0B_x8638_Txn8TransferLength138_OFFSET 16 -#define SMUx0B_x8638_Txn8TransferLength138_WIDTH 6 -#define SMUx0B_x8638_Txn8TransferLength138_MASK 0x3f0000 -#define SMUx0B_x8638_Txn8Tsize_OFFSET 22 -#define SMUx0B_x8638_Txn8Tsize_WIDTH 2 -#define SMUx0B_x8638_Txn8Tsize_MASK 0xc00000 -#define SMUx0B_x8638_Txn8TransferLength70_OFFSET 24 -#define SMUx0B_x8638_Txn8TransferLength70_WIDTH 8 -#define SMUx0B_x8638_Txn8TransferLength70_MASK 0xff000000 - -/// SMUx0B_x8638 -typedef union { - struct { ///< - UINT32 Txn9MBusAddr70:8 ; ///< - UINT32 Txn8Mode:2 ; ///< - UINT32 Txn8Static:1 ; ///< - UINT32 Txn8Overlap:1 ; ///< - UINT32 Txn8Spare:4 ; ///< - UINT32 Txn8TransferLength138:6 ; ///< - UINT32 Txn8Tsize:2 ; ///< - UINT32 Txn8TransferLength70:8 ; ///< - } Field; ///< - UINT32 Value; ///< -} SMUx0B_x8638_STRUCT; - -// **** SMUx0B_x863C Register Definition **** -// Address -#define SMUx0B_x863C_ADDRESS 0x863c - -// Type -#define SMUx0B_x863C_TYPE TYPE_SMUx0B -// Field Data -#define SMUx0B_x863C_Txn9TransferLength70_OFFSET 0 -#define SMUx0B_x863C_Txn9TransferLength70_WIDTH 8 -#define SMUx0B_x863C_Txn9TransferLength70_MASK 0xff -#define SMUx0B_x863C_Txn9MBusAddr3124_OFFSET 8 -#define SMUx0B_x863C_Txn9MBusAddr3124_WIDTH 8 -#define SMUx0B_x863C_Txn9MBusAddr3124_MASK 0xff00 -#define SMUx0B_x863C_Txn9MBuAaddr2316_OFFSET 16 -#define SMUx0B_x863C_Txn9MBuAaddr2316_WIDTH 8 -#define SMUx0B_x863C_Txn9MBuAaddr2316_MASK 0xff0000 -#define SMUx0B_x863C_Txn9MBusAddr158_OFFSET 24 -#define SMUx0B_x863C_Txn9MBusAddr158_WIDTH 8 -#define SMUx0B_x863C_Txn9MBusAddr158_MASK 0xff000000 - -/// SMUx0B_x863C -typedef union { - struct { ///< - UINT32 Txn9TransferLength70:8 ; ///< - UINT32 Txn9MBusAddr3124:8 ; ///< - UINT32 Txn9MBuAaddr2316:8 ; ///< - UINT32 Txn9MBusAddr158:8 ; ///< - } Field; ///< - UINT32 Value; ///< -} SMUx0B_x863C_STRUCT; - -// **** SMUx0B_x8640 Register Definition **** -// Address -#define SMUx0B_x8640_ADDRESS 0x8640 - -// Type -#define SMUx0B_x8640_TYPE TYPE_SMUx0B -// Field Data -#define SMUx0B_x8640_Txn10MBusAddr158_OFFSET 0 -#define SMUx0B_x8640_Txn10MBusAddr158_WIDTH 8 -#define SMUx0B_x8640_Txn10MBusAddr158_MASK 0xff -#define SMUx0B_x8640_Txn10MBusAddr70_OFFSET 8 -#define SMUx0B_x8640_Txn10MBusAddr70_WIDTH 8 -#define SMUx0B_x8640_Txn10MBusAddr70_MASK 0xff00 -#define SMUx0B_x8640_Txn9Mode_OFFSET 16 -#define SMUx0B_x8640_Txn9Mode_WIDTH 2 -#define SMUx0B_x8640_Txn9Mode_MASK 0x30000 -#define SMUx0B_x8640_Txn9Static_OFFSET 18 -#define SMUx0B_x8640_Txn9Static_WIDTH 1 -#define SMUx0B_x8640_Txn9Static_MASK 0x40000 -#define SMUx0B_x8640_Txn9Overlap_OFFSET 19 -#define SMUx0B_x8640_Txn9Overlap_WIDTH 1 -#define SMUx0B_x8640_Txn9Overlap_MASK 0x80000 -#define SMUx0B_x8640_Txn9Spare_OFFSET 20 -#define SMUx0B_x8640_Txn9Spare_WIDTH 4 -#define SMUx0B_x8640_Txn9Spare_MASK 0xf00000 -#define SMUx0B_x8640_Txn9TransferLength138_OFFSET 24 -#define SMUx0B_x8640_Txn9TransferLength138_WIDTH 6 -#define SMUx0B_x8640_Txn9TransferLength138_MASK 0x3f000000 -#define SMUx0B_x8640_Txn9Tsize_OFFSET 30 -#define SMUx0B_x8640_Txn9Tsize_WIDTH 2 -#define SMUx0B_x8640_Txn9Tsize_MASK 0xc0000000 - -/// SMUx0B_x8640 -typedef union { - struct { ///< - UINT32 Txn10MBusAddr158:8 ; ///< - UINT32 Txn10MBusAddr70:8 ; ///< - UINT32 Txn9Mode:2 ; ///< - UINT32 Txn9Static:1 ; ///< - UINT32 Txn9Overlap:1 ; ///< - UINT32 Txn9Spare:4 ; ///< - UINT32 Txn9TransferLength138:6 ; ///< - UINT32 Txn9Tsize:2 ; ///< - } Field; ///< - UINT32 Value; ///< -} SMUx0B_x8640_STRUCT; - -// **** SMUx0B_x8650 Register Definition **** -// Address -#define SMUx0B_x8650_ADDRESS 0x8650 - -// Type -#define SMUx0B_x8650_TYPE TYPE_SMUx0B -// Field Data -#define SMUx0B_x8650_Data_OFFSET 0 -#define SMUx0B_x8650_Data_WIDTH 32 -#define SMUx0B_x8650_Data_MASK 0xffffffff - -/// SMUx0B_x8650 -typedef union { - struct { ///< - UINT32 Data:32; ///< - } Field; ///< - UINT32 Value; ///< -} SMUx0B_x8650_STRUCT; - -// **** SMUx0B_x8654 Register Definition **** -// Address -#define SMUx0B_x8654_ADDRESS 0x8654 - -// Type -#define SMUx0B_x8654_TYPE TYPE_SMUx0B -// Field Data -#define SMUx0B_x8654_Data_OFFSET 0 -#define SMUx0B_x8654_Data_WIDTH 32 -#define SMUx0B_x8654_Data_MASK 0xffffffff - -/// SMUx0B_x8654 -typedef union { - struct { ///< - UINT32 Data:32; ///< - } Field; ///< - UINT32 Value; ///< -} SMUx0B_x8654_STRUCT; - -// **** SMUx0B_x8658 Register Definition **** -// Address -#define SMUx0B_x8658_ADDRESS 0x8658 - -// Type -#define SMUx0B_x8658_TYPE TYPE_SMUx0B -// Field Data -#define SMUx0B_x8658_Data_OFFSET 0 -#define SMUx0B_x8658_Data_WIDTH 32 -#define SMUx0B_x8658_Data_MASK 0xffffffff - -/// SMUx0B_x8658 -typedef union { - struct { ///< - UINT32 Data:32; ///< - } Field; ///< - UINT32 Value; ///< -} SMUx0B_x8658_STRUCT; - -// **** SMUx0B_x865C Register Definition **** -// Address -#define SMUx0B_x865C_ADDRESS 0x865c - -// Type -#define SMUx0B_x865C_TYPE TYPE_SMUx0B -// Field Data -#define SMUx0B_x865C_Data_OFFSET 0 -#define SMUx0B_x865C_Data_WIDTH 32 -#define SMUx0B_x865C_Data_MASK 0xffffffff - -/// SMUx0B_x865C -typedef union { - struct { ///< - UINT32 Data:32; ///< - } Field; ///< - UINT32 Value; ///< -} SMUx0B_x865C_STRUCT; - -// **** SMUx0B_x8660 Register Definition **** -// Address -#define SMUx0B_x8660_ADDRESS 0x8660 - -// Type -#define SMUx0B_x8660_TYPE TYPE_SMUx0B -// Field Data -#define SMUx0B_x8660_Data_OFFSET 0 -#define SMUx0B_x8660_Data_WIDTH 32 -#define SMUx0B_x8660_Data_MASK 0xffffffff - -/// SMUx0B_x8660 -typedef union { - struct { ///< - UINT32 Data:32; ///< - } Field; ///< - UINT32 Value; ///< -} SMUx0B_x8660_STRUCT; - -// **** SMUx0B_x8664 Register Definition **** -// Address -#define SMUx0B_x8664_ADDRESS 0x8664 - -// Type -#define SMUx0B_x8664_TYPE TYPE_SMUx0B -// Field Data -#define SMUx0B_x8664_Data_OFFSET 0 -#define SMUx0B_x8664_Data_WIDTH 32 -#define SMUx0B_x8664_Data_MASK 0xffffffff - -/// SMUx0B_x8664 -typedef union { - struct { ///< - UINT32 Data:32; ///< - } Field; ///< - UINT32 Value; ///< -} SMUx0B_x8664_STRUCT; - -// **** SMUx0B_x8668 Register Definition **** -// Address -#define SMUx0B_x8668_ADDRESS 0x8668 - -// Type -#define SMUx0B_x8668_TYPE TYPE_SMUx0B -// Field Data -#define SMUx0B_x8668_Data_OFFSET 0 -#define SMUx0B_x8668_Data_WIDTH 32 -#define SMUx0B_x8668_Data_MASK 0xffffffff - -/// SMUx0B_x8668 -typedef union { - struct { ///< - UINT32 Data:32; ///< - } Field; ///< - UINT32 Value; ///< -} SMUx0B_x8668_STRUCT; - -// **** SMUx0B_x866C Register Definition **** -// Address -#define SMUx0B_x866C_ADDRESS 0x866c - -// Type -#define SMUx0B_x866C_TYPE TYPE_SMUx0B -// Field Data -#define SMUx0B_x866C_Data_OFFSET 0 -#define SMUx0B_x866C_Data_WIDTH 32 -#define SMUx0B_x866C_Data_MASK 0xffffffff - -/// SMUx0B_x866C -typedef union { - struct { ///< - UINT32 Data:32; ///< - } Field; ///< - UINT32 Value; ///< -} SMUx0B_x866C_STRUCT; - -// **** SMUx0B_x8670 Register Definition **** -// Address -#define SMUx0B_x8670_ADDRESS 0x8670 - -// Type -#define SMUx0B_x8670_TYPE TYPE_SMUx0B -// Field Data -#define SMUx0B_x8670_Data_OFFSET 0 -#define SMUx0B_x8670_Data_WIDTH 32 -#define SMUx0B_x8670_Data_MASK 0xffffffff - -/// SMUx0B_x8670 -typedef union { - struct { ///< - UINT32 Data:32; ///< - } Field; ///< - UINT32 Value; ///< -} SMUx0B_x8670_STRUCT; - -// **** SMUx0B_x8674 Register Definition **** -// Address -#define SMUx0B_x8674_ADDRESS 0x8674 - -// Type -#define SMUx0B_x8674_TYPE TYPE_SMUx0B -// Field Data -#define SMUx0B_x8674_Data_OFFSET 0 -#define SMUx0B_x8674_Data_WIDTH 32 -#define SMUx0B_x8674_Data_MASK 0xffffffff - -/// SMUx0B_x8674 -typedef union { - struct { ///< - UINT32 Data:32; ///< - } Field; ///< - UINT32 Value; ///< -} SMUx0B_x8674_STRUCT; - -// **** SMUx0B_x8678 Register Definition **** -// Address -#define SMUx0B_x8678_ADDRESS 0x8678 - -// Type -#define SMUx0B_x8678_TYPE TYPE_SMUx0B -// Field Data -#define SMUx0B_x8678_Data_OFFSET 0 -#define SMUx0B_x8678_Data_WIDTH 32 -#define SMUx0B_x8678_Data_MASK 0xffffffff - -/// SMUx0B_x8678 -typedef union { - struct { ///< - UINT32 Data:32; ///< - } Field; ///< - UINT32 Value; ///< -} SMUx0B_x8678_STRUCT; - -// **** SMUx0B_x867C Register Definition **** -// Address -#define SMUx0B_x867C_ADDRESS 0x867c - -// Type -#define SMUx0B_x867C_TYPE TYPE_SMUx0B -// Field Data -#define SMUx0B_x867C_Data_OFFSET 0 -#define SMUx0B_x867C_Data_WIDTH 32 -#define SMUx0B_x867C_Data_MASK 0xffffffff - -/// SMUx0B_x867C -typedef union { - struct { ///< - UINT32 Data:32; ///< - } Field; ///< - UINT32 Value; ///< -} SMUx0B_x867C_STRUCT; - -// **** SMUx0B_x8680 Register Definition **** -// Address -#define SMUx0B_x8680_ADDRESS 0x8680 - -// Type -#define SMUx0B_x8680_TYPE TYPE_SMUx0B -// Field Data -#define SMUx0B_x8680_Data_OFFSET 0 -#define SMUx0B_x8680_Data_WIDTH 32 -#define SMUx0B_x8680_Data_MASK 0xffffffff - -/// SMUx0B_x8680 -typedef union { - struct { ///< - UINT32 Data:32; ///< - } Field; ///< - UINT32 Value; ///< -} SMUx0B_x8680_STRUCT; - -// **** SMUx0B_x8684 Register Definition **** -// Address -#define SMUx0B_x8684_ADDRESS 0x8684 - -// Type -#define SMUx0B_x8684_TYPE TYPE_SMUx0B -// Field Data -#define SMUx0B_x8684_Data_OFFSET 0 -#define SMUx0B_x8684_Data_WIDTH 32 -#define SMUx0B_x8684_Data_MASK 0xffffffff - -/// SMUx0B_x8684 -typedef union { - struct { ///< - UINT32 Data:32; ///< - } Field; ///< - UINT32 Value; ///< -} SMUx0B_x8684_STRUCT; - -// **** SMUx0B_x8688 Register Definition **** -// Address -#define SMUx0B_x8688_ADDRESS 0x8688 - -// Type -#define SMUx0B_x8688_TYPE TYPE_SMUx0B -// Field Data -#define SMUx0B_x8688_Data_OFFSET 0 -#define SMUx0B_x8688_Data_WIDTH 32 -#define SMUx0B_x8688_Data_MASK 0xffffffff - -/// SMUx0B_x8688 -typedef union { - struct { ///< - UINT32 Data:32; ///< - } Field; ///< - UINT32 Value; ///< -} SMUx0B_x8688_STRUCT; - -// **** SMUx0B_x868C Register Definition **** -// Address -#define SMUx0B_x868C_ADDRESS 0x868c - -// Type -#define SMUx0B_x868C_TYPE TYPE_SMUx0B -// Field Data -#define SMUx0B_x868C_Data_OFFSET 0 -#define SMUx0B_x868C_Data_WIDTH 32 -#define SMUx0B_x868C_Data_MASK 0xffffffff - -/// SMUx0B_x868C -typedef union { - struct { ///< - UINT32 Data:32; ///< - } Field; ///< - UINT32 Value; ///< -} SMUx0B_x868C_STRUCT; - -// **** SMUx0B_x8690 Register Definition **** -// Address -#define SMUx0B_x8690_ADDRESS 0x8690 - -// Type -#define SMUx0B_x8690_TYPE TYPE_SMUx0B -// Field Data -#define SMUx0B_x8690_Data_OFFSET 0 -#define SMUx0B_x8690_Data_WIDTH 32 -#define SMUx0B_x8690_Data_MASK 0xffffffff - -/// SMUx0B_x8690 -typedef union { - struct { ///< - UINT32 Data:32; ///< - } Field; ///< - UINT32 Value; ///< -} SMUx0B_x8690_STRUCT; - -// **** SMUx0B_x8694 Register Definition **** -// Address -#define SMUx0B_x8694_ADDRESS 0x8694 - -// Type -#define SMUx0B_x8694_TYPE TYPE_SMUx0B -// Field Data -#define SMUx0B_x8694_Data_OFFSET 0 -#define SMUx0B_x8694_Data_WIDTH 32 -#define SMUx0B_x8694_Data_MASK 0xffffffff - -/// SMUx0B_x8694 -typedef union { - struct { ///< - UINT32 Data:32; ///< - } Field; ///< - UINT32 Value; ///< -} SMUx0B_x8694_STRUCT; - -// **** SMUx0B_x8698 Register Definition **** -// Address -#define SMUx0B_x8698_ADDRESS 0x8698 - -// Type -#define SMUx0B_x8698_TYPE TYPE_SMUx0B -// Field Data -#define SMUx0B_x8698_Data_OFFSET 0 -#define SMUx0B_x8698_Data_WIDTH 32 -#define SMUx0B_x8698_Data_MASK 0xffffffff - -/// SMUx0B_x8698 -typedef union { - struct { ///< - UINT32 Data:32; ///< - } Field; ///< - UINT32 Value; ///< -} SMUx0B_x8698_STRUCT; - -// **** SMUx0B_x869C Register Definition **** -// Address -#define SMUx0B_x869C_ADDRESS 0x869c - -// Type -#define SMUx0B_x869C_TYPE TYPE_SMUx0B -// Field Data -#define SMUx0B_x869C_Data_OFFSET 0 -#define SMUx0B_x869C_Data_WIDTH 32 -#define SMUx0B_x869C_Data_MASK 0xffffffff - -/// SMUx0B_x869C -typedef union { - struct { ///< - UINT32 Data:32; ///< - } Field; ///< - UINT32 Value; ///< -} SMUx0B_x869C_STRUCT; - -// **** SMUx0B_x86A0 Register Definition **** -// Address -#define SMUx0B_x86A0_ADDRESS 0x86a0 - -// Type -#define SMUx0B_x86A0_TYPE TYPE_SMUx0B -// Field Data -#define SMUx0B_x86A0_Data_OFFSET 0 -#define SMUx0B_x86A0_Data_WIDTH 32 -#define SMUx0B_x86A0_Data_MASK 0xffffffff - -/// SMUx0B_x86A0 -typedef union { - struct { ///< - UINT32 Data:32; ///< - } Field; ///< - UINT32 Value; ///< -} SMUx0B_x86A0_STRUCT; - -// **** GMMx4D0 Register Definition **** -// Address -#define GMMx4D0_ADDRESS 0x4d0 - -// Type -#define GMMx4D0_TYPE TYPE_GMM -// Field Data -#define GMMx4D0_DispclkDccgGateDisable_OFFSET 0 -#define GMMx4D0_DispclkDccgGateDisable_WIDTH 1 -#define GMMx4D0_DispclkDccgGateDisable_MASK 0x1 -#define GMMx4D0_DispclkRDccgGateDisable_OFFSET 1 -#define GMMx4D0_DispclkRDccgGateDisable_WIDTH 1 -#define GMMx4D0_DispclkRDccgGateDisable_MASK 0x2 -#define GMMx4D0_SclkGateDisable_OFFSET 2 -#define GMMx4D0_SclkGateDisable_WIDTH 1 -#define GMMx4D0_SclkGateDisable_MASK 0x4 -#define GMMx4D0_Reserved_7_3_OFFSET 3 -#define GMMx4D0_Reserved_7_3_WIDTH 5 -#define GMMx4D0_Reserved_7_3_MASK 0xf8 -#define GMMx4D0_SymclkaGateDisable_OFFSET 8 -#define GMMx4D0_SymclkaGateDisable_WIDTH 1 -#define GMMx4D0_SymclkaGateDisable_MASK 0x100 -#define GMMx4D0_SymclkbGateDisable_OFFSET 9 -#define GMMx4D0_SymclkbGateDisable_WIDTH 1 -#define GMMx4D0_SymclkbGateDisable_MASK 0x200 -#define GMMx4D0_Reserved_31_10_OFFSET 10 -#define GMMx4D0_Reserved_31_10_WIDTH 22 -#define GMMx4D0_Reserved_31_10_MASK 0xfffffc00 - -/// GMMx4D0 -typedef union { - struct { ///< - UINT32 DispclkDccgGateDisable:1 ; ///< - UINT32 DispclkRDccgGateDisable:1 ; ///< - UINT32 SclkGateDisable:1 ; ///< - UINT32 Reserved_7_3:5 ; ///< - UINT32 SymclkaGateDisable:1 ; ///< - UINT32 SymclkbGateDisable:1 ; ///< - UINT32 Reserved_31_10:22; ///< - } Field; ///< - UINT32 Value; ///< -} GMMx4D0_STRUCT; - -// **** GMMx770 Register Definition **** -// Address -#define GMMx770_ADDRESS 0x770 - -// Type -#define GMMx770_TYPE TYPE_GMM -// Field Data -#define GMMx770_VoltageChangeReq_OFFSET 0 -#define GMMx770_VoltageChangeReq_WIDTH 1 -#define GMMx770_VoltageChangeReq_MASK 0x1 -#define GMMx770_VoltageLevel_OFFSET 1 -#define GMMx770_VoltageLevel_WIDTH 2 -#define GMMx770_VoltageLevel_MASK 0x6 -#define GMMx770_VoltageChangeEn_OFFSET 3 -#define GMMx770_VoltageChangeEn_WIDTH 1 -#define GMMx770_VoltageChangeEn_MASK 0x8 -#define GMMx770_VoltageForceEn_OFFSET 4 -#define GMMx770_VoltageForceEn_WIDTH 1 -#define GMMx770_VoltageForceEn_MASK 0x10 -#define GMMx770_Reserved_31_5_OFFSET 5 -#define GMMx770_Reserved_31_5_WIDTH 27 -#define GMMx770_Reserved_31_5_MASK 0xffffffe0 - -/// GMMx770 -typedef union { - struct { ///< - UINT32 VoltageChangeReq:1 ; ///< - UINT32 VoltageLevel:2 ; ///< - UINT32 VoltageChangeEn:1 ; ///< - UINT32 VoltageForceEn:1 ; ///< - UINT32 Reserved_31_5:27; ///< - } Field; ///< - UINT32 Value; ///< -} GMMx770_STRUCT; - -// **** GMMx774 Register Definition **** -// Address -#define GMMx774_ADDRESS 0x774 - -// Type -#define GMMx774_TYPE TYPE_GMM -// Field Data -#define GMMx774_VoltageChangeAck_OFFSET 0 -#define GMMx774_VoltageChangeAck_WIDTH 1 -#define GMMx774_VoltageChangeAck_MASK 0x1 -#define GMMx774_CurrentVoltageLevel_OFFSET 1 -#define GMMx774_CurrentVoltageLevel_WIDTH 2 -#define GMMx774_CurrentVoltageLevel_MASK 0x6 -#define GMMx774_Reserved_31_3_OFFSET 3 -#define GMMx774_Reserved_31_3_WIDTH 29 -#define GMMx774_Reserved_31_3_MASK 0xfffffff8 - -/// GMMx774 -typedef union { - struct { ///< - UINT32 VoltageChangeAck:1 ; ///< - UINT32 CurrentVoltageLevel:2 ; ///< - UINT32 Reserved_31_3:29; ///< - } Field; ///< - UINT32 Value; ///< -} GMMx774_STRUCT; - -// **** GMMx15C0 Register Definition **** -// Address -#define GMMx15C0_ADDRESS 0x15c0 - -// Type -#define GMMx15C0_TYPE TYPE_GMM -// Field Data -#define GMMx15C0_OnDly_OFFSET 0 -#define GMMx15C0_OnDly_WIDTH 6 -#define GMMx15C0_OnDly_MASK 0x3f -#define GMMx15C0_OffDly_OFFSET 6 -#define GMMx15C0_OffDly_WIDTH 6 -#define GMMx15C0_OffDly_MASK 0xfc0 -#define GMMx15C0_RdyDly_OFFSET 12 -#define GMMx15C0_RdyDly_WIDTH 6 -#define GMMx15C0_RdyDly_MASK 0x3f000 -#define GMMx15C0_Enable_OFFSET 18 -#define GMMx15C0_Enable_WIDTH 1 -#define GMMx15C0_Enable_MASK 0x40000 -#define GMMx15C0_Reserved_31_19_OFFSET 19 -#define GMMx15C0_Reserved_31_19_WIDTH 13 -#define GMMx15C0_Reserved_31_19_MASK 0xfff80000 - -/// GMMx15C0 -typedef union { - struct { ///< - UINT32 OnDly:6 ; ///< - UINT32 OffDly:6 ; ///< - UINT32 RdyDly:6 ; ///< - UINT32 Enable:1 ; ///< - UINT32 Reserved_31_19:13; ///< - } Field; ///< - UINT32 Value; ///< -} GMMx15C0_STRUCT; - -// **** GMMx2014 Register Definition **** -// Address -#define GMMx2014_ADDRESS 0x2014 - -// Type -#define GMMx2014_TYPE TYPE_GMM -// Field Data -#define GMMx2014_Rlc_OFFSET 0 -#define GMMx2014_Rlc_WIDTH 4 -#define GMMx2014_Rlc_MASK 0xf -#define GMMx2014_Vmc_OFFSET 4 -#define GMMx2014_Vmc_WIDTH 4 -#define GMMx2014_Vmc_MASK 0xf0 -#define GMMx2014_Dmif_OFFSET 8 -#define GMMx2014_Dmif_WIDTH 4 -#define GMMx2014_Dmif_MASK 0xf00 -#define GMMx2014_Mcif_OFFSET 12 -#define GMMx2014_Mcif_WIDTH 4 -#define GMMx2014_Mcif_MASK 0xf000 -#define GMMx2014_Reserved_31_16_OFFSET 16 -#define GMMx2014_Reserved_31_16_WIDTH 16 -#define GMMx2014_Reserved_31_16_MASK 0xffff0000 - -/// GMMx2014 -typedef union { - struct { ///< - UINT32 Rlc:4 ; ///< - UINT32 Vmc:4 ; ///< - UINT32 Dmif:4 ; ///< - UINT32 Mcif:4 ; ///< - UINT32 Reserved_31_16:16; ///< - } Field; ///< - UINT32 Value; ///< -} GMMx2014_STRUCT; - -// **** GMMx2018 Register Definition **** -// Address -#define GMMx2018_ADDRESS 0x2018 - -// Type -#define GMMx2018_TYPE TYPE_GMM -// Field Data -#define GMMx2018_Ih_OFFSET 0 -#define GMMx2018_Ih_WIDTH 4 -#define GMMx2018_Ih_MASK 0xf -#define GMMx2018_Mcif_OFFSET 4 -#define GMMx2018_Mcif_WIDTH 4 -#define GMMx2018_Mcif_MASK 0xf0 -#define GMMx2018_Rlc_OFFSET 8 -#define GMMx2018_Rlc_WIDTH 4 -#define GMMx2018_Rlc_MASK 0xf00 -#define GMMx2018_Vip_OFFSET 12 -#define GMMx2018_Vip_WIDTH 4 -#define GMMx2018_Vip_MASK 0xf000 -#define GMMx2018_Reserved_31_16_OFFSET 16 -#define GMMx2018_Reserved_31_16_WIDTH 16 -#define GMMx2018_Reserved_31_16_MASK 0xffff0000 - -/// GMMx2018 -typedef union { - struct { ///< - UINT32 Ih:4 ; ///< - UINT32 Mcif:4 ; ///< - UINT32 Rlc:4 ; ///< - UINT32 Vip:4 ; ///< - UINT32 Reserved_31_16:16; ///< - } Field; ///< - UINT32 Value; ///< -} GMMx2018_STRUCT; - -// **** GMMx201C Register Definition **** -// Address -#define GMMx201C_ADDRESS 0x201c - -// Type -#define GMMx201C_TYPE TYPE_GMM -// Field Data -#define GMMx201C_UvdExt0_OFFSET 0 -#define GMMx201C_UvdExt0_WIDTH 4 -#define GMMx201C_UvdExt0_MASK 0xf -#define GMMx201C_DrmDma_OFFSET 4 -#define GMMx201C_DrmDma_WIDTH 4 -#define GMMx201C_DrmDma_MASK 0xf0 -#define GMMx201C_Hdp_OFFSET 8 -#define GMMx201C_Hdp_WIDTH 4 -#define GMMx201C_Hdp_MASK 0xf00 -#define GMMx201C_Sem_OFFSET 12 -#define GMMx201C_Sem_WIDTH 4 -#define GMMx201C_Sem_MASK 0xf000 -#define GMMx201C_Umc_OFFSET 16 -#define GMMx201C_Umc_WIDTH 4 -#define GMMx201C_Umc_MASK 0xf0000 -#define GMMx201C_Uvd_OFFSET 20 -#define GMMx201C_Uvd_WIDTH 4 -#define GMMx201C_Uvd_MASK 0xf00000 -#define GMMx201C_UvdExt1_OFFSET 24 -#define GMMx201C_UvdExt1_WIDTH 4 -#define GMMx201C_UvdExt1_MASK 0xf000000 -#define GMMx201C_Reserved_31_28_OFFSET 28 -#define GMMx201C_Reserved_31_28_WIDTH 4 -#define GMMx201C_Reserved_31_28_MASK 0xf0000000 - -/// GMMx201C -typedef union { - struct { ///< - UINT32 UvdExt0:4 ; ///< - UINT32 DrmDma:4 ; ///< - UINT32 Hdp:4 ; ///< - UINT32 Sem:4 ; ///< - UINT32 Umc:4 ; ///< - UINT32 Uvd:4 ; ///< - UINT32 UvdExt1:4 ; ///< - UINT32 Reserved_31_28:4 ; ///< - } Field; ///< - UINT32 Value; ///< -} GMMx201C_STRUCT; - -// **** GMMx2020 Register Definition **** -// Address -#define GMMx2020_ADDRESS 0x2020 - -// Type -#define GMMx2020_TYPE TYPE_GMM -// Field Data -#define GMMx2020_UvdExt0_OFFSET 0 -#define GMMx2020_UvdExt0_WIDTH 4 -#define GMMx2020_UvdExt0_MASK 0xf -#define GMMx2020_DrmDma_OFFSET 4 -#define GMMx2020_DrmDma_WIDTH 4 -#define GMMx2020_DrmDma_MASK 0xf0 -#define GMMx2020_Hdp_OFFSET 8 -#define GMMx2020_Hdp_WIDTH 4 -#define GMMx2020_Hdp_MASK 0xf00 -#define GMMx2020_Sem_OFFSET 12 -#define GMMx2020_Sem_WIDTH 4 -#define GMMx2020_Sem_MASK 0xf000 -#define GMMx2020_Umc_OFFSET 16 -#define GMMx2020_Umc_WIDTH 4 -#define GMMx2020_Umc_MASK 0xf0000 -#define GMMx2020_Uvd_OFFSET 20 -#define GMMx2020_Uvd_WIDTH 4 -#define GMMx2020_Uvd_MASK 0xf00000 -#define GMMx2020_Xdp_OFFSET 24 -#define GMMx2020_Xdp_WIDTH 4 -#define GMMx2020_Xdp_MASK 0xf000000 -#define GMMx2020_UvdExt1_OFFSET 28 -#define GMMx2020_UvdExt1_WIDTH 4 -#define GMMx2020_UvdExt1_MASK 0xf0000000 - -/// GMMx2020 -typedef union { - struct { ///< - UINT32 UvdExt0:4 ; ///< - UINT32 DrmDma:4 ; ///< - UINT32 Hdp:4 ; ///< - UINT32 Sem:4 ; ///< - UINT32 Umc:4 ; ///< - UINT32 Uvd:4 ; ///< - UINT32 Xdp:4 ; ///< - UINT32 UvdExt1:4 ; ///< - } Field; ///< - UINT32 Value; ///< -} GMMx2020_STRUCT; - -// **** GMMx2024 Register Definition **** -// Address -#define GMMx2024_ADDRESS 0x2024 - -// Type -#define GMMx2024_TYPE TYPE_GMM -// Field Data -#define GMMx2024_Base_OFFSET 0 -#define GMMx2024_Base_WIDTH 16 -#define GMMx2024_Base_MASK 0xffff -#define GMMx2024_Top_OFFSET 16 -#define GMMx2024_Top_WIDTH 16 -#define GMMx2024_Top_MASK 0xffff0000 - -/// GMMx2024 -typedef union { - struct { ///< - UINT32 Base:16; ///< - UINT32 Top:16; ///< - } Field; ///< - UINT32 Value; ///< -} GMMx2024_STRUCT; - -// **** GMMx2028 Register Definition **** -// Address -#define GMMx2028_ADDRESS 0x2028 - -// Type -#define GMMx2028_TYPE TYPE_GMM -// Field Data -#define GMMx2028_SysTop_39_22__OFFSET 0 -#define GMMx2028_SysTop_39_22__WIDTH 18 -#define GMMx2028_SysTop_39_22__MASK 0x3ffff -#define GMMx2028_Reserved_31_18_OFFSET 18 -#define GMMx2028_Reserved_31_18_WIDTH 14 -#define GMMx2028_Reserved_31_18_MASK 0xfffc0000 - -/// GMMx2028 -typedef union { - struct { ///< - UINT32 SysTop_39_22_:18; ///< - UINT32 Reserved_31_18:14; ///< - } Field; ///< - UINT32 Value; ///< -} GMMx2028_STRUCT; - -// **** GMMx202C Register Definition **** -// Address -#define GMMx202C_ADDRESS 0x202c - -// Type -#define GMMx202C_TYPE TYPE_GMM -// Field Data -#define GMMx202C_SysBot_39_22__OFFSET 0 -#define GMMx202C_SysBot_39_22__WIDTH 18 -#define GMMx202C_SysBot_39_22__MASK 0x3ffff -#define GMMx202C_Reserved_31_18_OFFSET 18 -#define GMMx202C_Reserved_31_18_WIDTH 14 -#define GMMx202C_Reserved_31_18_MASK 0xfffc0000 - -/// GMMx202C -typedef union { - struct { ///< - UINT32 SysBot_39_22_:18; ///< - UINT32 Reserved_31_18:14; ///< - } Field; ///< - UINT32 Value; ///< -} GMMx202C_STRUCT; - -// **** GMMx20B8 Register Definition **** -// Address -#define GMMx20B8_ADDRESS 0x20b8 - -// Type -#define GMMx20B8_TYPE TYPE_GMM -// Field Data -#define GMMx20B8_OnDly_OFFSET 0 -#define GMMx20B8_OnDly_WIDTH 6 -#define GMMx20B8_OnDly_MASK 0x3f -#define GMMx20B8_OffDly_OFFSET 6 -#define GMMx20B8_OffDly_WIDTH 6 -#define GMMx20B8_OffDly_MASK 0xfc0 -#define GMMx20B8_RdyDly_OFFSET 12 -#define GMMx20B8_RdyDly_WIDTH 6 -#define GMMx20B8_RdyDly_MASK 0x3f000 -#define GMMx20B8_Enable_OFFSET 18 -#define GMMx20B8_Enable_WIDTH 1 -#define GMMx20B8_Enable_MASK 0x40000 -#define GMMx20B8_Reserved_31_19_OFFSET 19 -#define GMMx20B8_Reserved_31_19_WIDTH 13 -#define GMMx20B8_Reserved_31_19_MASK 0xfff80000 - -/// GMMx20B8 -typedef union { - struct { ///< - UINT32 OnDly:6 ; ///< - UINT32 OffDly:6 ; ///< - UINT32 RdyDly:6 ; ///< - UINT32 Enable:1 ; ///< - UINT32 Reserved_31_19:13; ///< - } Field; ///< - UINT32 Value; ///< -} GMMx20B8_STRUCT; - -// **** GMMx20BC Register Definition **** -// Address -#define GMMx20BC_ADDRESS 0x20bc - -// Type -#define GMMx20BC_TYPE TYPE_GMM -// Field Data -#define GMMx20BC_OnDly_OFFSET 0 -#define GMMx20BC_OnDly_WIDTH 6 -#define GMMx20BC_OnDly_MASK 0x3f -#define GMMx20BC_OffDly_OFFSET 6 -#define GMMx20BC_OffDly_WIDTH 6 -#define GMMx20BC_OffDly_MASK 0xfc0 -#define GMMx20BC_RdyDly_OFFSET 12 -#define GMMx20BC_RdyDly_WIDTH 6 -#define GMMx20BC_RdyDly_MASK 0x3f000 -#define GMMx20BC_Enable_OFFSET 18 -#define GMMx20BC_Enable_WIDTH 1 -#define GMMx20BC_Enable_MASK 0x40000 -#define GMMx20BC_Reserved_31_19_OFFSET 19 -#define GMMx20BC_Reserved_31_19_WIDTH 13 -#define GMMx20BC_Reserved_31_19_MASK 0xfff80000 - -/// GMMx20BC -typedef union { - struct { ///< - UINT32 OnDly:6 ; ///< - UINT32 OffDly:6 ; ///< - UINT32 RdyDly:6 ; ///< - UINT32 Enable:1 ; ///< - UINT32 Reserved_31_19:13; ///< - } Field; ///< - UINT32 Value; ///< -} GMMx20BC_STRUCT; - -// **** GMMx20C0 Register Definition **** -// Address -#define GMMx20C0_ADDRESS 0x20c0 - -// Type -#define GMMx20C0_TYPE TYPE_GMM -// Field Data -#define GMMx20C0_OnDly_OFFSET 0 -#define GMMx20C0_OnDly_WIDTH 6 -#define GMMx20C0_OnDly_MASK 0x3f -#define GMMx20C0_OffDly_OFFSET 6 -#define GMMx20C0_OffDly_WIDTH 6 -#define GMMx20C0_OffDly_MASK 0xfc0 -#define GMMx20C0_RdyDly_OFFSET 12 -#define GMMx20C0_RdyDly_WIDTH 6 -#define GMMx20C0_RdyDly_MASK 0x3f000 -#define GMMx20C0_Enable_OFFSET 18 -#define GMMx20C0_Enable_WIDTH 1 -#define GMMx20C0_Enable_MASK 0x40000 -#define GMMx20C0_Reserved_31_19_OFFSET 19 -#define GMMx20C0_Reserved_31_19_WIDTH 13 -#define GMMx20C0_Reserved_31_19_MASK 0xfff80000 - -/// GMMx20C0 -typedef union { - struct { ///< - UINT32 OnDly:6 ; ///< - UINT32 OffDly:6 ; ///< - UINT32 RdyDly:6 ; ///< - UINT32 Enable:1 ; ///< - UINT32 Reserved_31_19:13; ///< - } Field; ///< - UINT32 Value; ///< -} GMMx20C0_STRUCT; - -// **** GMMx20D4 Register Definition **** -// Address -#define GMMx20D4_ADDRESS 0x20d4 - -// Type -#define GMMx20D4_TYPE TYPE_GMM -// Field Data -#define GMMx20D4_LocalBlackout_OFFSET 0 -#define GMMx20D4_LocalBlackout_WIDTH 1 -#define GMMx20D4_LocalBlackout_MASK 0x1 -#define GMMx20D4_Reserved_31_1_OFFSET 1 -#define GMMx20D4_Reserved_31_1_WIDTH 31 -#define GMMx20D4_Reserved_31_1_MASK 0xfffffffe - -/// GMMx20D4 -typedef union { - struct { ///< - UINT32 LocalBlackout:1 ; ///< - UINT32 Reserved_31_1:31; ///< - } Field; ///< - UINT32 Value; ///< -} GMMx20D4_STRUCT; - -// **** GMMx20EC Register Definition **** -// Address -#define GMMx20EC_ADDRESS 0x20ec - -// Type -#define GMMx20EC_TYPE TYPE_GMM -// Field Data -#define GMMx20EC_RemoteBlackout_OFFSET 0 -#define GMMx20EC_RemoteBlackout_WIDTH 1 -#define GMMx20EC_RemoteBlackout_MASK 0x1 -#define GMMx20EC_LocalBlackout_OFFSET 1 -#define GMMx20EC_LocalBlackout_WIDTH 1 -#define GMMx20EC_LocalBlackout_MASK 0x2 -#define GMMx20EC_Reserved_31_2_OFFSET 2 -#define GMMx20EC_Reserved_31_2_WIDTH 30 -#define GMMx20EC_Reserved_31_2_MASK 0xfffffffc - -/// GMMx20EC -typedef union { - struct { ///< - UINT32 RemoteBlackout:1 ; ///< - UINT32 LocalBlackout:1 ; ///< - UINT32 Reserved_31_2:30; ///< - } Field; ///< - UINT32 Value; ///< -} GMMx20EC_STRUCT; - -// **** GMMx2114 Register Definition **** -// Address -#define GMMx2114_ADDRESS 0x2114 - -// Type -#define GMMx2114_TYPE TYPE_GMM -// Field Data -#define GMMx2114_Stor1Pri_OFFSET 0 -#define GMMx2114_Stor1Pri_WIDTH 8 -#define GMMx2114_Stor1Pri_MASK 0xff -#define GMMx2114_StallableStor_OFFSET 8 -#define GMMx2114_StallableStor_WIDTH 8 -#define GMMx2114_StallableStor_MASK 0xff00 -#define GMMx2114_Reserved_31_16_OFFSET 16 -#define GMMx2114_Reserved_31_16_WIDTH 16 -#define GMMx2114_Reserved_31_16_MASK 0xffff0000 - -/// GMMx2114 -typedef union { - struct { ///< - UINT32 Stor1Pri:8 ; ///< - UINT32 StallableStor:8 ; ///< - UINT32 Reserved_31_16:16; ///< - } Field; ///< - UINT32 Value; ///< -} GMMx2114_STRUCT; - -// **** GMMx2144 Register Definition **** -// Address -#define GMMx2144_ADDRESS 0x2144 - -// Type -#define GMMx2144_TYPE TYPE_GMM -// Field Data -#define GMMx2144_Reserved_10_0_OFFSET 0 -#define GMMx2144_Reserved_10_0_WIDTH 11 -#define GMMx2144_Reserved_10_0_MASK 0x7ff -#define GMMx2144_AskCredits_OFFSET 11 -#define GMMx2144_AskCredits_WIDTH 7 -#define GMMx2144_AskCredits_MASK 0x3f800 -#define GMMx2144_Reserved_31_18_OFFSET 18 -#define GMMx2144_Reserved_31_18_WIDTH 14 -#define GMMx2144_Reserved_31_18_MASK 0xfffc0000 - -/// GMMx2144 -typedef union { - struct { ///< - UINT32 Reserved_10_0:11; ///< - UINT32 AskCredits:7 ; ///< - UINT32 Reserved_31_18:14; ///< - } Field; ///< - UINT32 Value; ///< -} GMMx2144_STRUCT; - -// **** GMMx2160 Register Definition **** -// Address -#define GMMx2160_ADDRESS 0x2160 - -// Type -#define GMMx2160_TYPE TYPE_GMM -// Field Data -#define GMMx2160_Enable_OFFSET 0 -#define GMMx2160_Enable_WIDTH 1 -#define GMMx2160_Enable_MASK 0x1 -#define GMMx2160_Prescale_OFFSET 1 -#define GMMx2160_Prescale_WIDTH 2 -#define GMMx2160_Prescale_MASK 0x6 -#define GMMx2160_BlackoutExempt_OFFSET 3 -#define GMMx2160_BlackoutExempt_WIDTH 1 -#define GMMx2160_BlackoutExempt_MASK 0x8 -#define GMMx2160_StallMode_OFFSET 4 -#define GMMx2160_StallMode_WIDTH 2 -#define GMMx2160_StallMode_MASK 0x30 -#define GMMx2160_StallOverride_OFFSET 6 -#define GMMx2160_StallOverride_WIDTH 1 -#define GMMx2160_StallOverride_MASK 0x40 -#define GMMx2160_MaxBurst_OFFSET 7 -#define GMMx2160_MaxBurst_WIDTH 4 -#define GMMx2160_MaxBurst_MASK 0x780 -#define GMMx2160_LazyTimer_OFFSET 11 -#define GMMx2160_LazyTimer_WIDTH 4 -#define GMMx2160_LazyTimer_MASK 0x7800 -#define GMMx2160_StallOverrideWtm_OFFSET 15 -#define GMMx2160_StallOverrideWtm_WIDTH 1 -#define GMMx2160_StallOverrideWtm_MASK 0x8000 -#define GMMx2160_Reserved_19_16_OFFSET 16 -#define GMMx2160_Reserved_19_16_WIDTH 4 -#define GMMx2160_Reserved_19_16_MASK 0xf0000 -#define GMMx2160_Reserved_31_20_OFFSET 20 -#define GMMx2160_Reserved_31_20_WIDTH 12 -#define GMMx2160_Reserved_31_20_MASK 0xfff00000 - -/// GMMx2160 -typedef union { - struct { ///< - UINT32 Enable:1 ; ///< - UINT32 Prescale:2 ; ///< - UINT32 BlackoutExempt:1 ; ///< - UINT32 StallMode:2 ; ///< - UINT32 StallOverride:1 ; ///< - UINT32 MaxBurst:4 ; ///< - UINT32 LazyTimer:4 ; ///< - UINT32 StallOverrideWtm:1 ; ///< - UINT32 Reserved_19_16:4 ; ///< - UINT32 Reserved_31_20:12; ///< - } Field; ///< - UINT32 Value; ///< -} GMMx2160_STRUCT; - -// **** GMMx2164 Register Definition **** -// Address -#define GMMx2164_ADDRESS 0x2164 - -// Type -#define GMMx2164_TYPE TYPE_GMM -// Field Data -#define GMMx2164_Enable_OFFSET 0 -#define GMMx2164_Enable_WIDTH 1 -#define GMMx2164_Enable_MASK 0x1 -#define GMMx2164_Prescale_OFFSET 1 -#define GMMx2164_Prescale_WIDTH 2 -#define GMMx2164_Prescale_MASK 0x6 -#define GMMx2164_BlackoutExempt_OFFSET 3 -#define GMMx2164_BlackoutExempt_WIDTH 1 -#define GMMx2164_BlackoutExempt_MASK 0x8 -#define GMMx2164_StallMode_OFFSET 4 -#define GMMx2164_StallMode_WIDTH 2 -#define GMMx2164_StallMode_MASK 0x30 -#define GMMx2164_StallOverride_OFFSET 6 -#define GMMx2164_StallOverride_WIDTH 1 -#define GMMx2164_StallOverride_MASK 0x40 -#define GMMx2164_MaxBurst_OFFSET 7 -#define GMMx2164_MaxBurst_WIDTH 4 -#define GMMx2164_MaxBurst_MASK 0x780 -#define GMMx2164_LazyTimer_OFFSET 11 -#define GMMx2164_LazyTimer_WIDTH 4 -#define GMMx2164_LazyTimer_MASK 0x7800 -#define GMMx2164_StallOverrideWtm_OFFSET 15 -#define GMMx2164_StallOverrideWtm_WIDTH 1 -#define GMMx2164_StallOverrideWtm_MASK 0x8000 -#define GMMx2164_Reserved_19_16_OFFSET 16 -#define GMMx2164_Reserved_19_16_WIDTH 4 -#define GMMx2164_Reserved_19_16_MASK 0xf0000 -#define GMMx2164_Reserved_31_20_OFFSET 20 -#define GMMx2164_Reserved_31_20_WIDTH 12 -#define GMMx2164_Reserved_31_20_MASK 0xfff00000 - -/// GMMx2164 -typedef union { - struct { ///< - UINT32 Enable:1 ; ///< - UINT32 Prescale:2 ; ///< - UINT32 BlackoutExempt:1 ; ///< - UINT32 StallMode:2 ; ///< - UINT32 StallOverride:1 ; ///< - UINT32 MaxBurst:4 ; ///< - UINT32 LazyTimer:4 ; ///< - UINT32 StallOverrideWtm:1 ; ///< - UINT32 Reserved_19_16:4 ; ///< - UINT32 Reserved_31_20:12; ///< - } Field; ///< - UINT32 Value; ///< -} GMMx2164_STRUCT; - -// **** GMMx2168 Register Definition **** -// Address -#define GMMx2168_ADDRESS 0x2168 - -// Type -#define GMMx2168_TYPE TYPE_GMM -// Field Data -#define GMMx2168_Enable_OFFSET 0 -#define GMMx2168_Enable_WIDTH 1 -#define GMMx2168_Enable_MASK 0x1 -#define GMMx2168_Prescale_OFFSET 1 -#define GMMx2168_Prescale_WIDTH 2 -#define GMMx2168_Prescale_MASK 0x6 -#define GMMx2168_BlackoutExempt_OFFSET 3 -#define GMMx2168_BlackoutExempt_WIDTH 1 -#define GMMx2168_BlackoutExempt_MASK 0x8 -#define GMMx2168_StallMode_OFFSET 4 -#define GMMx2168_StallMode_WIDTH 2 -#define GMMx2168_StallMode_MASK 0x30 -#define GMMx2168_StallOverride_OFFSET 6 -#define GMMx2168_StallOverride_WIDTH 1 -#define GMMx2168_StallOverride_MASK 0x40 -#define GMMx2168_MaxBurst_OFFSET 7 -#define GMMx2168_MaxBurst_WIDTH 4 -#define GMMx2168_MaxBurst_MASK 0x780 -#define GMMx2168_LazyTimer_OFFSET 11 -#define GMMx2168_LazyTimer_WIDTH 4 -#define GMMx2168_LazyTimer_MASK 0x7800 -#define GMMx2168_StallOverrideWtm_OFFSET 15 -#define GMMx2168_StallOverrideWtm_WIDTH 1 -#define GMMx2168_StallOverrideWtm_MASK 0x8000 -#define GMMx2168_Reserved_19_16_OFFSET 16 -#define GMMx2168_Reserved_19_16_WIDTH 4 -#define GMMx2168_Reserved_19_16_MASK 0xf0000 -#define GMMx2168_Reserved_31_20_OFFSET 20 -#define GMMx2168_Reserved_31_20_WIDTH 12 -#define GMMx2168_Reserved_31_20_MASK 0xfff00000 - -/// GMMx2168 -typedef union { - struct { ///< - UINT32 Enable:1 ; ///< - UINT32 Prescale:2 ; ///< - UINT32 BlackoutExempt:1 ; ///< - UINT32 StallMode:2 ; ///< - UINT32 StallOverride:1 ; ///< - UINT32 MaxBurst:4 ; ///< - UINT32 LazyTimer:4 ; ///< - UINT32 StallOverrideWtm:1 ; ///< - UINT32 Reserved_19_16:4 ; ///< - UINT32 Reserved_31_20:12; ///< - } Field; ///< - UINT32 Value; ///< -} GMMx2168_STRUCT; - -// **** GMMx216C Register Definition **** -// Address -#define GMMx216C_ADDRESS 0x216c - -// Type -#define GMMx216C_TYPE TYPE_GMM -// Field Data -#define GMMx216C_Enable_OFFSET 0 -#define GMMx216C_Enable_WIDTH 1 -#define GMMx216C_Enable_MASK 0x1 -#define GMMx216C_Prescale_OFFSET 1 -#define GMMx216C_Prescale_WIDTH 2 -#define GMMx216C_Prescale_MASK 0x6 -#define GMMx216C_BlackoutExempt_OFFSET 3 -#define GMMx216C_BlackoutExempt_WIDTH 1 -#define GMMx216C_BlackoutExempt_MASK 0x8 -#define GMMx216C_StallMode_OFFSET 4 -#define GMMx216C_StallMode_WIDTH 2 -#define GMMx216C_StallMode_MASK 0x30 -#define GMMx216C_StallOverride_OFFSET 6 -#define GMMx216C_StallOverride_WIDTH 1 -#define GMMx216C_StallOverride_MASK 0x40 -#define GMMx216C_MaxBurst_OFFSET 7 -#define GMMx216C_MaxBurst_WIDTH 4 -#define GMMx216C_MaxBurst_MASK 0x780 -#define GMMx216C_LazyTimer_OFFSET 11 -#define GMMx216C_LazyTimer_WIDTH 4 -#define GMMx216C_LazyTimer_MASK 0x7800 -#define GMMx216C_StallOverrideWtm_OFFSET 15 -#define GMMx216C_StallOverrideWtm_WIDTH 1 -#define GMMx216C_StallOverrideWtm_MASK 0x8000 -#define GMMx216C_Reserved_19_16_OFFSET 16 -#define GMMx216C_Reserved_19_16_WIDTH 4 -#define GMMx216C_Reserved_19_16_MASK 0xf0000 -#define GMMx216C_Reserved_31_20_OFFSET 20 -#define GMMx216C_Reserved_31_20_WIDTH 12 -#define GMMx216C_Reserved_31_20_MASK 0xfff00000 - -/// GMMx216C -typedef union { - struct { ///< - UINT32 Enable:1 ; ///< - UINT32 Prescale:2 ; ///< - UINT32 BlackoutExempt:1 ; ///< - UINT32 StallMode:2 ; ///< - UINT32 StallOverride:1 ; ///< - UINT32 MaxBurst:4 ; ///< - UINT32 LazyTimer:4 ; ///< - UINT32 StallOverrideWtm:1 ; ///< - UINT32 Reserved_19_16:4 ; ///< - UINT32 Reserved_31_20:12; ///< - } Field; ///< - UINT32 Value; ///< -} GMMx216C_STRUCT; - -// **** GMMx2170 Register Definition **** -// Address -#define GMMx2170_ADDRESS 0x2170 - -// Type -#define GMMx2170_TYPE TYPE_GMM -// Field Data -#define GMMx2170_Enable_OFFSET 0 -#define GMMx2170_Enable_WIDTH 1 -#define GMMx2170_Enable_MASK 0x1 -#define GMMx2170_Prescale_OFFSET 1 -#define GMMx2170_Prescale_WIDTH 2 -#define GMMx2170_Prescale_MASK 0x6 -#define GMMx2170_BlackoutExempt_OFFSET 3 -#define GMMx2170_BlackoutExempt_WIDTH 1 -#define GMMx2170_BlackoutExempt_MASK 0x8 -#define GMMx2170_StallMode_OFFSET 4 -#define GMMx2170_StallMode_WIDTH 2 -#define GMMx2170_StallMode_MASK 0x30 -#define GMMx2170_StallOverride_OFFSET 6 -#define GMMx2170_StallOverride_WIDTH 1 -#define GMMx2170_StallOverride_MASK 0x40 -#define GMMx2170_MaxBurst_OFFSET 7 -#define GMMx2170_MaxBurst_WIDTH 4 -#define GMMx2170_MaxBurst_MASK 0x780 -#define GMMx2170_LazyTimer_OFFSET 11 -#define GMMx2170_LazyTimer_WIDTH 4 -#define GMMx2170_LazyTimer_MASK 0x7800 -#define GMMx2170_StallOverrideWtm_OFFSET 15 -#define GMMx2170_StallOverrideWtm_WIDTH 1 -#define GMMx2170_StallOverrideWtm_MASK 0x8000 -#define GMMx2170_Reserved_19_16_OFFSET 16 -#define GMMx2170_Reserved_19_16_WIDTH 4 -#define GMMx2170_Reserved_19_16_MASK 0xf0000 -#define GMMx2170_Reserved_31_20_OFFSET 20 -#define GMMx2170_Reserved_31_20_WIDTH 12 -#define GMMx2170_Reserved_31_20_MASK 0xfff00000 - -/// GMMx2170 -typedef union { - struct { ///< - UINT32 Enable:1 ; ///< - UINT32 Prescale:2 ; ///< - UINT32 BlackoutExempt:1 ; ///< - UINT32 StallMode:2 ; ///< - UINT32 StallOverride:1 ; ///< - UINT32 MaxBurst:4 ; ///< - UINT32 LazyTimer:4 ; ///< - UINT32 StallOverrideWtm:1 ; ///< - UINT32 Reserved_19_16:4 ; ///< - UINT32 Reserved_31_20:12; ///< - } Field; ///< - UINT32 Value; ///< -} GMMx2170_STRUCT; - -// **** GMMx2174 Register Definition **** -// Address -#define GMMx2174_ADDRESS 0x2174 - -// Type -#define GMMx2174_TYPE TYPE_GMM -// Field Data -#define GMMx2174_Enable_OFFSET 0 -#define GMMx2174_Enable_WIDTH 1 -#define GMMx2174_Enable_MASK 0x1 -#define GMMx2174_Prescale_OFFSET 1 -#define GMMx2174_Prescale_WIDTH 2 -#define GMMx2174_Prescale_MASK 0x6 -#define GMMx2174_BlackoutExempt_OFFSET 3 -#define GMMx2174_BlackoutExempt_WIDTH 1 -#define GMMx2174_BlackoutExempt_MASK 0x8 -#define GMMx2174_StallMode_OFFSET 4 -#define GMMx2174_StallMode_WIDTH 2 -#define GMMx2174_StallMode_MASK 0x30 -#define GMMx2174_StallOverride_OFFSET 6 -#define GMMx2174_StallOverride_WIDTH 1 -#define GMMx2174_StallOverride_MASK 0x40 -#define GMMx2174_MaxBurst_OFFSET 7 -#define GMMx2174_MaxBurst_WIDTH 4 -#define GMMx2174_MaxBurst_MASK 0x780 -#define GMMx2174_LazyTimer_OFFSET 11 -#define GMMx2174_LazyTimer_WIDTH 4 -#define GMMx2174_LazyTimer_MASK 0x7800 -#define GMMx2174_StallOverrideWtm_OFFSET 15 -#define GMMx2174_StallOverrideWtm_WIDTH 1 -#define GMMx2174_StallOverrideWtm_MASK 0x8000 -#define GMMx2174_Reserved_19_16_OFFSET 16 -#define GMMx2174_Reserved_19_16_WIDTH 4 -#define GMMx2174_Reserved_19_16_MASK 0xf0000 -#define GMMx2174_Reserved_31_20_OFFSET 20 -#define GMMx2174_Reserved_31_20_WIDTH 12 -#define GMMx2174_Reserved_31_20_MASK 0xfff00000 - -/// GMMx2174 -typedef union { - struct { ///< - UINT32 Enable:1 ; ///< - UINT32 Prescale:2 ; ///< - UINT32 BlackoutExempt:1 ; ///< - UINT32 StallMode:2 ; ///< - UINT32 StallOverride:1 ; ///< - UINT32 MaxBurst:4 ; ///< - UINT32 LazyTimer:4 ; ///< - UINT32 StallOverrideWtm:1 ; ///< - UINT32 Reserved_19_16:4 ; ///< - UINT32 Reserved_31_20:12; ///< - } Field; ///< - UINT32 Value; ///< -} GMMx2174_STRUCT; - -// **** GMMx2178 Register Definition **** -// Address -#define GMMx2178_ADDRESS 0x2178 - -// Type -#define GMMx2178_TYPE TYPE_GMM -// Field Data -#define GMMx2178_Enable_OFFSET 0 -#define GMMx2178_Enable_WIDTH 1 -#define GMMx2178_Enable_MASK 0x1 -#define GMMx2178_Prescale_OFFSET 1 -#define GMMx2178_Prescale_WIDTH 2 -#define GMMx2178_Prescale_MASK 0x6 -#define GMMx2178_BlackoutExempt_OFFSET 3 -#define GMMx2178_BlackoutExempt_WIDTH 1 -#define GMMx2178_BlackoutExempt_MASK 0x8 -#define GMMx2178_StallMode_OFFSET 4 -#define GMMx2178_StallMode_WIDTH 2 -#define GMMx2178_StallMode_MASK 0x30 -#define GMMx2178_StallOverride_OFFSET 6 -#define GMMx2178_StallOverride_WIDTH 1 -#define GMMx2178_StallOverride_MASK 0x40 -#define GMMx2178_MaxBurst_OFFSET 7 -#define GMMx2178_MaxBurst_WIDTH 4 -#define GMMx2178_MaxBurst_MASK 0x780 -#define GMMx2178_LazyTimer_OFFSET 11 -#define GMMx2178_LazyTimer_WIDTH 4 -#define GMMx2178_LazyTimer_MASK 0x7800 -#define GMMx2178_StallOverrideWtm_OFFSET 15 -#define GMMx2178_StallOverrideWtm_WIDTH 1 -#define GMMx2178_StallOverrideWtm_MASK 0x8000 -#define GMMx2178_Reserved_19_16_OFFSET 16 -#define GMMx2178_Reserved_19_16_WIDTH 4 -#define GMMx2178_Reserved_19_16_MASK 0xf0000 -#define GMMx2178_Reserved_31_20_OFFSET 20 -#define GMMx2178_Reserved_31_20_WIDTH 12 -#define GMMx2178_Reserved_31_20_MASK 0xfff00000 - -/// GMMx2178 -typedef union { - struct { ///< - UINT32 Enable:1 ; ///< - UINT32 Prescale:2 ; ///< - UINT32 BlackoutExempt:1 ; ///< - UINT32 StallMode:2 ; ///< - UINT32 StallOverride:1 ; ///< - UINT32 MaxBurst:4 ; ///< - UINT32 LazyTimer:4 ; ///< - UINT32 StallOverrideWtm:1 ; ///< - UINT32 Reserved_19_16:4 ; ///< - UINT32 Reserved_31_20:12; ///< - } Field; ///< - UINT32 Value; ///< -} GMMx2178_STRUCT; - -// **** GMMx217C Register Definition **** -// Address -#define GMMx217C_ADDRESS 0x217c - -// Type -#define GMMx217C_TYPE TYPE_GMM -// Field Data -#define GMMx217C_Enable_OFFSET 0 -#define GMMx217C_Enable_WIDTH 1 -#define GMMx217C_Enable_MASK 0x1 -#define GMMx217C_Prescale_OFFSET 1 -#define GMMx217C_Prescale_WIDTH 2 -#define GMMx217C_Prescale_MASK 0x6 -#define GMMx217C_BlackoutExempt_OFFSET 3 -#define GMMx217C_BlackoutExempt_WIDTH 1 -#define GMMx217C_BlackoutExempt_MASK 0x8 -#define GMMx217C_StallMode_OFFSET 4 -#define GMMx217C_StallMode_WIDTH 2 -#define GMMx217C_StallMode_MASK 0x30 -#define GMMx217C_StallOverride_OFFSET 6 -#define GMMx217C_StallOverride_WIDTH 1 -#define GMMx217C_StallOverride_MASK 0x40 -#define GMMx217C_MaxBurst_OFFSET 7 -#define GMMx217C_MaxBurst_WIDTH 4 -#define GMMx217C_MaxBurst_MASK 0x780 -#define GMMx217C_LazyTimer_OFFSET 11 -#define GMMx217C_LazyTimer_WIDTH 4 -#define GMMx217C_LazyTimer_MASK 0x7800 -#define GMMx217C_StallOverrideWtm_OFFSET 15 -#define GMMx217C_StallOverrideWtm_WIDTH 1 -#define GMMx217C_StallOverrideWtm_MASK 0x8000 -#define GMMx217C_Reserved_19_16_OFFSET 16 -#define GMMx217C_Reserved_19_16_WIDTH 4 -#define GMMx217C_Reserved_19_16_MASK 0xf0000 -#define GMMx217C_Reserved_31_20_OFFSET 20 -#define GMMx217C_Reserved_31_20_WIDTH 12 -#define GMMx217C_Reserved_31_20_MASK 0xfff00000 - -/// GMMx217C -typedef union { - struct { ///< - UINT32 Enable:1 ; ///< - UINT32 Prescale:2 ; ///< - UINT32 BlackoutExempt:1 ; ///< - UINT32 StallMode:2 ; ///< - UINT32 StallOverride:1 ; ///< - UINT32 MaxBurst:4 ; ///< - UINT32 LazyTimer:4 ; ///< - UINT32 StallOverrideWtm:1 ; ///< - UINT32 Reserved_19_16:4 ; ///< - UINT32 Reserved_31_20:12; ///< - } Field; ///< - UINT32 Value; ///< -} GMMx217C_STRUCT; - -// **** GMMx2180 Register Definition **** -// Address -#define GMMx2180_ADDRESS 0x2180 - -// Type -#define GMMx2180_TYPE TYPE_GMM -// Field Data -#define GMMx2180_Enable_OFFSET 0 -#define GMMx2180_Enable_WIDTH 1 -#define GMMx2180_Enable_MASK 0x1 -#define GMMx2180_Prescale_OFFSET 1 -#define GMMx2180_Prescale_WIDTH 2 -#define GMMx2180_Prescale_MASK 0x6 -#define GMMx2180_BlackoutExempt_OFFSET 3 -#define GMMx2180_BlackoutExempt_WIDTH 1 -#define GMMx2180_BlackoutExempt_MASK 0x8 -#define GMMx2180_StallMode_OFFSET 4 -#define GMMx2180_StallMode_WIDTH 2 -#define GMMx2180_StallMode_MASK 0x30 -#define GMMx2180_StallOverride_OFFSET 6 -#define GMMx2180_StallOverride_WIDTH 1 -#define GMMx2180_StallOverride_MASK 0x40 -#define GMMx2180_MaxBurst_OFFSET 7 -#define GMMx2180_MaxBurst_WIDTH 4 -#define GMMx2180_MaxBurst_MASK 0x780 -#define GMMx2180_LazyTimer_OFFSET 11 -#define GMMx2180_LazyTimer_WIDTH 4 -#define GMMx2180_LazyTimer_MASK 0x7800 -#define GMMx2180_StallOverrideWtm_OFFSET 15 -#define GMMx2180_StallOverrideWtm_WIDTH 1 -#define GMMx2180_StallOverrideWtm_MASK 0x8000 -#define GMMx2180_Reserved_19_16_OFFSET 16 -#define GMMx2180_Reserved_19_16_WIDTH 4 -#define GMMx2180_Reserved_19_16_MASK 0xf0000 -#define GMMx2180_Reserved_31_20_OFFSET 20 -#define GMMx2180_Reserved_31_20_WIDTH 12 -#define GMMx2180_Reserved_31_20_MASK 0xfff00000 - -/// GMMx2180 -typedef union { - struct { ///< - UINT32 Enable:1 ; ///< - UINT32 Prescale:2 ; ///< - UINT32 BlackoutExempt:1 ; ///< - UINT32 StallMode:2 ; ///< - UINT32 StallOverride:1 ; ///< - UINT32 MaxBurst:4 ; ///< - UINT32 LazyTimer:4 ; ///< - UINT32 StallOverrideWtm:1 ; ///< - UINT32 Reserved_19_16:4 ; ///< - UINT32 Reserved_31_20:12; ///< - } Field; ///< - UINT32 Value; ///< -} GMMx2180_STRUCT; - -// **** GMMx2184 Register Definition **** -// Address -#define GMMx2184_ADDRESS 0x2184 - -// Type -#define GMMx2184_TYPE TYPE_GMM -// Field Data -#define GMMx2184_Enable_OFFSET 0 -#define GMMx2184_Enable_WIDTH 1 -#define GMMx2184_Enable_MASK 0x1 -#define GMMx2184_Prescale_OFFSET 1 -#define GMMx2184_Prescale_WIDTH 2 -#define GMMx2184_Prescale_MASK 0x6 -#define GMMx2184_BlackoutExempt_OFFSET 3 -#define GMMx2184_BlackoutExempt_WIDTH 1 -#define GMMx2184_BlackoutExempt_MASK 0x8 -#define GMMx2184_StallMode_OFFSET 4 -#define GMMx2184_StallMode_WIDTH 2 -#define GMMx2184_StallMode_MASK 0x30 -#define GMMx2184_StallOverride_OFFSET 6 -#define GMMx2184_StallOverride_WIDTH 1 -#define GMMx2184_StallOverride_MASK 0x40 -#define GMMx2184_MaxBurst_OFFSET 7 -#define GMMx2184_MaxBurst_WIDTH 4 -#define GMMx2184_MaxBurst_MASK 0x780 -#define GMMx2184_LazyTimer_OFFSET 11 -#define GMMx2184_LazyTimer_WIDTH 4 -#define GMMx2184_LazyTimer_MASK 0x7800 -#define GMMx2184_StallOverrideWtm_OFFSET 15 -#define GMMx2184_StallOverrideWtm_WIDTH 1 -#define GMMx2184_StallOverrideWtm_MASK 0x8000 -#define GMMx2184_Reserved_19_16_OFFSET 16 -#define GMMx2184_Reserved_19_16_WIDTH 4 -#define GMMx2184_Reserved_19_16_MASK 0xf0000 -#define GMMx2184_Reserved_31_20_OFFSET 20 -#define GMMx2184_Reserved_31_20_WIDTH 12 -#define GMMx2184_Reserved_31_20_MASK 0xfff00000 - -/// GMMx2184 -typedef union { - struct { ///< - UINT32 Enable:1 ; ///< - UINT32 Prescale:2 ; ///< - UINT32 BlackoutExempt:1 ; ///< - UINT32 StallMode:2 ; ///< - UINT32 StallOverride:1 ; ///< - UINT32 MaxBurst:4 ; ///< - UINT32 LazyTimer:4 ; ///< - UINT32 StallOverrideWtm:1 ; ///< - UINT32 Reserved_19_16:4 ; ///< - UINT32 Reserved_31_20:12; ///< - } Field; ///< - UINT32 Value; ///< -} GMMx2184_STRUCT; - -// **** GMMx2188 Register Definition **** -// Address -#define GMMx2188_ADDRESS 0x2188 - -// Type -#define GMMx2188_TYPE TYPE_GMM -// Field Data -#define GMMx2188_Enable_OFFSET 0 -#define GMMx2188_Enable_WIDTH 1 -#define GMMx2188_Enable_MASK 0x1 -#define GMMx2188_Prescale_OFFSET 1 -#define GMMx2188_Prescale_WIDTH 2 -#define GMMx2188_Prescale_MASK 0x6 -#define GMMx2188_BlackoutExempt_OFFSET 3 -#define GMMx2188_BlackoutExempt_WIDTH 1 -#define GMMx2188_BlackoutExempt_MASK 0x8 -#define GMMx2188_StallMode_OFFSET 4 -#define GMMx2188_StallMode_WIDTH 2 -#define GMMx2188_StallMode_MASK 0x30 -#define GMMx2188_StallOverride_OFFSET 6 -#define GMMx2188_StallOverride_WIDTH 1 -#define GMMx2188_StallOverride_MASK 0x40 -#define GMMx2188_MaxBurst_OFFSET 7 -#define GMMx2188_MaxBurst_WIDTH 4 -#define GMMx2188_MaxBurst_MASK 0x780 -#define GMMx2188_LazyTimer_OFFSET 11 -#define GMMx2188_LazyTimer_WIDTH 4 -#define GMMx2188_LazyTimer_MASK 0x7800 -#define GMMx2188_StallOverrideWtm_OFFSET 15 -#define GMMx2188_StallOverrideWtm_WIDTH 1 -#define GMMx2188_StallOverrideWtm_MASK 0x8000 -#define GMMx2188_ReqLimit_OFFSET 16 -#define GMMx2188_ReqLimit_WIDTH 4 -#define GMMx2188_ReqLimit_MASK 0xf0000 -#define GMMx2188_Reserved_31_20_OFFSET 20 -#define GMMx2188_Reserved_31_20_WIDTH 12 -#define GMMx2188_Reserved_31_20_MASK 0xfff00000 - -/// GMMx2188 -typedef union { - struct { ///< - UINT32 Enable:1 ; ///< - UINT32 Prescale:2 ; ///< - UINT32 BlackoutExempt:1 ; ///< - UINT32 StallMode:2 ; ///< - UINT32 StallOverride:1 ; ///< - UINT32 MaxBurst:4 ; ///< - UINT32 LazyTimer:4 ; ///< - UINT32 StallOverrideWtm:1 ; ///< - UINT32 ReqLimit:4 ; ///< - UINT32 Reserved_31_20:12; ///< - } Field; ///< - UINT32 Value; ///< -} GMMx2188_STRUCT; - -// **** GMMx218C Register Definition **** -// Address -#define GMMx218C_ADDRESS 0x218c - -// Type -#define GMMx218C_TYPE TYPE_GMM -// Field Data -#define GMMx218C_Enable_OFFSET 0 -#define GMMx218C_Enable_WIDTH 1 -#define GMMx218C_Enable_MASK 0x1 -#define GMMx218C_Prescale_OFFSET 1 -#define GMMx218C_Prescale_WIDTH 2 -#define GMMx218C_Prescale_MASK 0x6 -#define GMMx218C_BlackoutExempt_OFFSET 3 -#define GMMx218C_BlackoutExempt_WIDTH 1 -#define GMMx218C_BlackoutExempt_MASK 0x8 -#define GMMx218C_StallMode_OFFSET 4 -#define GMMx218C_StallMode_WIDTH 2 -#define GMMx218C_StallMode_MASK 0x30 -#define GMMx218C_StallOverride_OFFSET 6 -#define GMMx218C_StallOverride_WIDTH 1 -#define GMMx218C_StallOverride_MASK 0x40 -#define GMMx218C_MaxBurst_OFFSET 7 -#define GMMx218C_MaxBurst_WIDTH 4 -#define GMMx218C_MaxBurst_MASK 0x780 -#define GMMx218C_LazyTimer_OFFSET 11 -#define GMMx218C_LazyTimer_WIDTH 4 -#define GMMx218C_LazyTimer_MASK 0x7800 -#define GMMx218C_StallOverrideWtm_OFFSET 15 -#define GMMx218C_StallOverrideWtm_WIDTH 1 -#define GMMx218C_StallOverrideWtm_MASK 0x8000 -#define GMMx218C_Reserved_19_16_OFFSET 16 -#define GMMx218C_Reserved_19_16_WIDTH 4 -#define GMMx218C_Reserved_19_16_MASK 0xf0000 -#define GMMx218C_Reserved_31_20_OFFSET 20 -#define GMMx218C_Reserved_31_20_WIDTH 12 -#define GMMx218C_Reserved_31_20_MASK 0xfff00000 - -/// GMMx218C -typedef union { - struct { ///< - UINT32 Enable:1 ; ///< - UINT32 Prescale:2 ; ///< - UINT32 BlackoutExempt:1 ; ///< - UINT32 StallMode:2 ; ///< - UINT32 StallOverride:1 ; ///< - UINT32 MaxBurst:4 ; ///< - UINT32 LazyTimer:4 ; ///< - UINT32 StallOverrideWtm:1 ; ///< - UINT32 Reserved_19_16:4 ; ///< - UINT32 Reserved_31_20:12; ///< - } Field; ///< - UINT32 Value; ///< -} GMMx218C_STRUCT; - -// **** GMMx2190 Register Definition **** -// Address -#define GMMx2190_ADDRESS 0x2190 - -// Type -#define GMMx2190_TYPE TYPE_GMM -// Field Data -#define GMMx2190_Enable_OFFSET 0 -#define GMMx2190_Enable_WIDTH 1 -#define GMMx2190_Enable_MASK 0x1 -#define GMMx2190_BlackoutExempt_OFFSET 1 -#define GMMx2190_BlackoutExempt_WIDTH 1 -#define GMMx2190_BlackoutExempt_MASK 0x2 -#define GMMx2190_StallMode_OFFSET 2 -#define GMMx2190_StallMode_WIDTH 1 -#define GMMx2190_StallMode_MASK 0x4 -#define GMMx2190_MaxBurst_OFFSET 3 -#define GMMx2190_MaxBurst_WIDTH 4 -#define GMMx2190_MaxBurst_MASK 0x78 -#define GMMx2190_AskCredits_OFFSET 7 -#define GMMx2190_AskCredits_WIDTH 6 -#define GMMx2190_AskCredits_MASK 0x1f80 -#define GMMx2190_LazyTimer_OFFSET 13 -#define GMMx2190_LazyTimer_WIDTH 4 -#define GMMx2190_LazyTimer_MASK 0x1e000 -#define GMMx2190_StallThreshold_OFFSET 17 -#define GMMx2190_StallThreshold_WIDTH 6 -#define GMMx2190_StallThreshold_MASK 0x7e0000 -#define GMMx2190_Reserved_31_23_OFFSET 23 -#define GMMx2190_Reserved_31_23_WIDTH 9 -#define GMMx2190_Reserved_31_23_MASK 0xff800000 - -/// GMMx2190 -typedef union { - struct { ///< - UINT32 Enable:1 ; ///< - UINT32 BlackoutExempt:1 ; ///< - UINT32 StallMode:1 ; ///< - UINT32 MaxBurst:4 ; ///< - UINT32 AskCredits:6 ; ///< - UINT32 LazyTimer:4 ; ///< - UINT32 StallThreshold:6 ; ///< - UINT32 Reserved_31_23:9 ; ///< - } Field; ///< - UINT32 Value; ///< -} GMMx2190_STRUCT; - -// **** GMMx2194 Register Definition **** -// Address -#define GMMx2194_ADDRESS 0x2194 - -// Type -#define GMMx2194_TYPE TYPE_GMM -// Field Data -#define GMMx2194_Enable_OFFSET 0 -#define GMMx2194_Enable_WIDTH 1 -#define GMMx2194_Enable_MASK 0x1 -#define GMMx2194_BlackoutExempt_OFFSET 1 -#define GMMx2194_BlackoutExempt_WIDTH 1 -#define GMMx2194_BlackoutExempt_MASK 0x2 -#define GMMx2194_StallMode_OFFSET 2 -#define GMMx2194_StallMode_WIDTH 1 -#define GMMx2194_StallMode_MASK 0x4 -#define GMMx2194_MaxBurst_OFFSET 3 -#define GMMx2194_MaxBurst_WIDTH 4 -#define GMMx2194_MaxBurst_MASK 0x78 -#define GMMx2194_AskCredits_OFFSET 7 -#define GMMx2194_AskCredits_WIDTH 6 -#define GMMx2194_AskCredits_MASK 0x1f80 -#define GMMx2194_LazyTimer_OFFSET 13 -#define GMMx2194_LazyTimer_WIDTH 4 -#define GMMx2194_LazyTimer_MASK 0x1e000 -#define GMMx2194_StallThreshold_OFFSET 17 -#define GMMx2194_StallThreshold_WIDTH 6 -#define GMMx2194_StallThreshold_MASK 0x7e0000 -#define GMMx2194_Reserved_31_23_OFFSET 23 -#define GMMx2194_Reserved_31_23_WIDTH 9 -#define GMMx2194_Reserved_31_23_MASK 0xff800000 - -/// GMMx2194 -typedef union { - struct { ///< - UINT32 Enable:1 ; ///< - UINT32 BlackoutExempt:1 ; ///< - UINT32 StallMode:1 ; ///< - UINT32 MaxBurst:4 ; ///< - UINT32 AskCredits:6 ; ///< - UINT32 LazyTimer:4 ; ///< - UINT32 StallThreshold:6 ; ///< - UINT32 Reserved_31_23:9 ; ///< - } Field; ///< - UINT32 Value; ///< -} GMMx2194_STRUCT; - -// **** GMMx2198 Register Definition **** -// Address -#define GMMx2198_ADDRESS 0x2198 - -// Type -#define GMMx2198_TYPE TYPE_GMM -// Field Data -#define GMMx2198_Enable_OFFSET 0 -#define GMMx2198_Enable_WIDTH 1 -#define GMMx2198_Enable_MASK 0x1 -#define GMMx2198_BlackoutExempt_OFFSET 1 -#define GMMx2198_BlackoutExempt_WIDTH 1 -#define GMMx2198_BlackoutExempt_MASK 0x2 -#define GMMx2198_StallMode_OFFSET 2 -#define GMMx2198_StallMode_WIDTH 1 -#define GMMx2198_StallMode_MASK 0x4 -#define GMMx2198_MaxBurst_OFFSET 3 -#define GMMx2198_MaxBurst_WIDTH 4 -#define GMMx2198_MaxBurst_MASK 0x78 -#define GMMx2198_AskCredits_OFFSET 7 -#define GMMx2198_AskCredits_WIDTH 6 -#define GMMx2198_AskCredits_MASK 0x1f80 -#define GMMx2198_LazyTimer_OFFSET 13 -#define GMMx2198_LazyTimer_WIDTH 4 -#define GMMx2198_LazyTimer_MASK 0x1e000 -#define GMMx2198_StallThreshold_OFFSET 17 -#define GMMx2198_StallThreshold_WIDTH 6 -#define GMMx2198_StallThreshold_MASK 0x7e0000 -#define GMMx2198_Reserved_31_23_OFFSET 23 -#define GMMx2198_Reserved_31_23_WIDTH 9 -#define GMMx2198_Reserved_31_23_MASK 0xff800000 - -/// GMMx2198 -typedef union { - struct { ///< - UINT32 Enable:1 ; ///< - UINT32 BlackoutExempt:1 ; ///< - UINT32 StallMode:1 ; ///< - UINT32 MaxBurst:4 ; ///< - UINT32 AskCredits:6 ; ///< - UINT32 LazyTimer:4 ; ///< - UINT32 StallThreshold:6 ; ///< - UINT32 Reserved_31_23:9 ; ///< - } Field; ///< - UINT32 Value; ///< -} GMMx2198_STRUCT; - -// **** GMMx219C Register Definition **** -// Address -#define GMMx219C_ADDRESS 0x219c - -// Type -#define GMMx219C_TYPE TYPE_GMM -// Field Data -#define GMMx219C_Enable_OFFSET 0 -#define GMMx219C_Enable_WIDTH 1 -#define GMMx219C_Enable_MASK 0x1 -#define GMMx219C_BlackoutExempt_OFFSET 1 -#define GMMx219C_BlackoutExempt_WIDTH 1 -#define GMMx219C_BlackoutExempt_MASK 0x2 -#define GMMx219C_StallMode_OFFSET 2 -#define GMMx219C_StallMode_WIDTH 1 -#define GMMx219C_StallMode_MASK 0x4 -#define GMMx219C_MaxBurst_OFFSET 3 -#define GMMx219C_MaxBurst_WIDTH 4 -#define GMMx219C_MaxBurst_MASK 0x78 -#define GMMx219C_AskCredits_OFFSET 7 -#define GMMx219C_AskCredits_WIDTH 6 -#define GMMx219C_AskCredits_MASK 0x1f80 -#define GMMx219C_LazyTimer_OFFSET 13 -#define GMMx219C_LazyTimer_WIDTH 4 -#define GMMx219C_LazyTimer_MASK 0x1e000 -#define GMMx219C_StallThreshold_OFFSET 17 -#define GMMx219C_StallThreshold_WIDTH 6 -#define GMMx219C_StallThreshold_MASK 0x7e0000 -#define GMMx219C_Reserved_31_23_OFFSET 23 -#define GMMx219C_Reserved_31_23_WIDTH 9 -#define GMMx219C_Reserved_31_23_MASK 0xff800000 - -/// GMMx219C -typedef union { - struct { ///< - UINT32 Enable:1 ; ///< - UINT32 BlackoutExempt:1 ; ///< - UINT32 StallMode:1 ; ///< - UINT32 MaxBurst:4 ; ///< - UINT32 AskCredits:6 ; ///< - UINT32 LazyTimer:4 ; ///< - UINT32 StallThreshold:6 ; ///< - UINT32 Reserved_31_23:9 ; ///< - } Field; ///< - UINT32 Value; ///< -} GMMx219C_STRUCT; - -// **** GMMx21A4 Register Definition **** -// Address -#define GMMx21A4_ADDRESS 0x21a4 - -// Type -#define GMMx21A4_TYPE TYPE_GMM -// Field Data -#define GMMx21A4_Enable_OFFSET 0 -#define GMMx21A4_Enable_WIDTH 1 -#define GMMx21A4_Enable_MASK 0x1 -#define GMMx21A4_Prescale_OFFSET 1 -#define GMMx21A4_Prescale_WIDTH 2 -#define GMMx21A4_Prescale_MASK 0x6 -#define GMMx21A4_BlackoutExempt_OFFSET 3 -#define GMMx21A4_BlackoutExempt_WIDTH 1 -#define GMMx21A4_BlackoutExempt_MASK 0x8 -#define GMMx21A4_StallMode_OFFSET 4 -#define GMMx21A4_StallMode_WIDTH 2 -#define GMMx21A4_StallMode_MASK 0x30 -#define GMMx21A4_StallOverride_OFFSET 6 -#define GMMx21A4_StallOverride_WIDTH 1 -#define GMMx21A4_StallOverride_MASK 0x40 -#define GMMx21A4_MaxBurst_OFFSET 7 -#define GMMx21A4_MaxBurst_WIDTH 4 -#define GMMx21A4_MaxBurst_MASK 0x780 -#define GMMx21A4_LazyTimer_OFFSET 11 -#define GMMx21A4_LazyTimer_WIDTH 4 -#define GMMx21A4_LazyTimer_MASK 0x7800 -#define GMMx21A4_StallOverrideWtm_OFFSET 15 -#define GMMx21A4_StallOverrideWtm_WIDTH 1 -#define GMMx21A4_StallOverrideWtm_MASK 0x8000 -#define GMMx21A4_Reserved_31_16_OFFSET 16 -#define GMMx21A4_Reserved_31_16_WIDTH 16 -#define GMMx21A4_Reserved_31_16_MASK 0xffff0000 - -/// GMMx21A4 -typedef union { - struct { ///< - UINT32 Enable:1 ; ///< - UINT32 Prescale:2 ; ///< - UINT32 BlackoutExempt:1 ; ///< - UINT32 StallMode:2 ; ///< - UINT32 StallOverride:1 ; ///< - UINT32 MaxBurst:4 ; ///< - UINT32 LazyTimer:4 ; ///< - UINT32 StallOverrideWtm:1 ; ///< - UINT32 Reserved_31_16:16; ///< - } Field; ///< - UINT32 Value; ///< -} GMMx21A4_STRUCT; - -// **** GMMx21A8 Register Definition **** -// Address -#define GMMx21A8_ADDRESS 0x21a8 - -// Type -#define GMMx21A8_TYPE TYPE_GMM -// Field Data -#define GMMx21A8_Enable_OFFSET 0 -#define GMMx21A8_Enable_WIDTH 1 -#define GMMx21A8_Enable_MASK 0x1 -#define GMMx21A8_Prescale_OFFSET 1 -#define GMMx21A8_Prescale_WIDTH 2 -#define GMMx21A8_Prescale_MASK 0x6 -#define GMMx21A8_BlackoutExempt_OFFSET 3 -#define GMMx21A8_BlackoutExempt_WIDTH 1 -#define GMMx21A8_BlackoutExempt_MASK 0x8 -#define GMMx21A8_StallMode_OFFSET 4 -#define GMMx21A8_StallMode_WIDTH 2 -#define GMMx21A8_StallMode_MASK 0x30 -#define GMMx21A8_StallOverride_OFFSET 6 -#define GMMx21A8_StallOverride_WIDTH 1 -#define GMMx21A8_StallOverride_MASK 0x40 -#define GMMx21A8_MaxBurst_OFFSET 7 -#define GMMx21A8_MaxBurst_WIDTH 4 -#define GMMx21A8_MaxBurst_MASK 0x780 -#define GMMx21A8_LazyTimer_OFFSET 11 -#define GMMx21A8_LazyTimer_WIDTH 4 -#define GMMx21A8_LazyTimer_MASK 0x7800 -#define GMMx21A8_StallOverrideWtm_OFFSET 15 -#define GMMx21A8_StallOverrideWtm_WIDTH 1 -#define GMMx21A8_StallOverrideWtm_MASK 0x8000 -#define GMMx21A8_Reserved_31_16_OFFSET 16 -#define GMMx21A8_Reserved_31_16_WIDTH 16 -#define GMMx21A8_Reserved_31_16_MASK 0xffff0000 - -/// GMMx21A8 -typedef union { - struct { ///< - UINT32 Enable:1 ; ///< - UINT32 Prescale:2 ; ///< - UINT32 BlackoutExempt:1 ; ///< - UINT32 StallMode:2 ; ///< - UINT32 StallOverride:1 ; ///< - UINT32 MaxBurst:4 ; ///< - UINT32 LazyTimer:4 ; ///< - UINT32 StallOverrideWtm:1 ; ///< - UINT32 Reserved_31_16:16; ///< - } Field; ///< - UINT32 Value; ///< -} GMMx21A8_STRUCT; - -// **** GMMx21AC Register Definition **** -// Address -#define GMMx21AC_ADDRESS 0x21ac - -// Type -#define GMMx21AC_TYPE TYPE_GMM -// Field Data -#define GMMx21AC_Enable_OFFSET 0 -#define GMMx21AC_Enable_WIDTH 1 -#define GMMx21AC_Enable_MASK 0x1 -#define GMMx21AC_Prescale_OFFSET 1 -#define GMMx21AC_Prescale_WIDTH 2 -#define GMMx21AC_Prescale_MASK 0x6 -#define GMMx21AC_BlackoutExempt_OFFSET 3 -#define GMMx21AC_BlackoutExempt_WIDTH 1 -#define GMMx21AC_BlackoutExempt_MASK 0x8 -#define GMMx21AC_StallMode_OFFSET 4 -#define GMMx21AC_StallMode_WIDTH 2 -#define GMMx21AC_StallMode_MASK 0x30 -#define GMMx21AC_StallOverride_OFFSET 6 -#define GMMx21AC_StallOverride_WIDTH 1 -#define GMMx21AC_StallOverride_MASK 0x40 -#define GMMx21AC_MaxBurst_OFFSET 7 -#define GMMx21AC_MaxBurst_WIDTH 4 -#define GMMx21AC_MaxBurst_MASK 0x780 -#define GMMx21AC_LazyTimer_OFFSET 11 -#define GMMx21AC_LazyTimer_WIDTH 4 -#define GMMx21AC_LazyTimer_MASK 0x7800 -#define GMMx21AC_StallOverrideWtm_OFFSET 15 -#define GMMx21AC_StallOverrideWtm_WIDTH 1 -#define GMMx21AC_StallOverrideWtm_MASK 0x8000 -#define GMMx21AC_Reserved_31_16_OFFSET 16 -#define GMMx21AC_Reserved_31_16_WIDTH 16 -#define GMMx21AC_Reserved_31_16_MASK 0xffff0000 - -/// GMMx21AC -typedef union { - struct { ///< - UINT32 Enable:1 ; ///< - UINT32 Prescale:2 ; ///< - UINT32 BlackoutExempt:1 ; ///< - UINT32 StallMode:2 ; ///< - UINT32 StallOverride:1 ; ///< - UINT32 MaxBurst:4 ; ///< - UINT32 LazyTimer:4 ; ///< - UINT32 StallOverrideWtm:1 ; ///< - UINT32 Reserved_31_16:16; ///< - } Field; ///< - UINT32 Value; ///< -} GMMx21AC_STRUCT; - -// **** GMMx21B0 Register Definition **** -// Address -#define GMMx21B0_ADDRESS 0x21b0 - -// Type -#define GMMx21B0_TYPE TYPE_GMM -// Field Data -#define GMMx21B0_Enable_OFFSET 0 -#define GMMx21B0_Enable_WIDTH 1 -#define GMMx21B0_Enable_MASK 0x1 -#define GMMx21B0_Prescale_OFFSET 1 -#define GMMx21B0_Prescale_WIDTH 2 -#define GMMx21B0_Prescale_MASK 0x6 -#define GMMx21B0_BlackoutExempt_OFFSET 3 -#define GMMx21B0_BlackoutExempt_WIDTH 1 -#define GMMx21B0_BlackoutExempt_MASK 0x8 -#define GMMx21B0_StallMode_OFFSET 4 -#define GMMx21B0_StallMode_WIDTH 2 -#define GMMx21B0_StallMode_MASK 0x30 -#define GMMx21B0_StallOverride_OFFSET 6 -#define GMMx21B0_StallOverride_WIDTH 1 -#define GMMx21B0_StallOverride_MASK 0x40 -#define GMMx21B0_MaxBurst_OFFSET 7 -#define GMMx21B0_MaxBurst_WIDTH 4 -#define GMMx21B0_MaxBurst_MASK 0x780 -#define GMMx21B0_LazyTimer_OFFSET 11 -#define GMMx21B0_LazyTimer_WIDTH 4 -#define GMMx21B0_LazyTimer_MASK 0x7800 -#define GMMx21B0_StallOverrideWtm_OFFSET 15 -#define GMMx21B0_StallOverrideWtm_WIDTH 1 -#define GMMx21B0_StallOverrideWtm_MASK 0x8000 -#define GMMx21B0_Reserved_31_16_OFFSET 16 -#define GMMx21B0_Reserved_31_16_WIDTH 16 -#define GMMx21B0_Reserved_31_16_MASK 0xffff0000 - -/// GMMx21B0 -typedef union { - struct { ///< - UINT32 Enable:1 ; ///< - UINT32 Prescale:2 ; ///< - UINT32 BlackoutExempt:1 ; ///< - UINT32 StallMode:2 ; ///< - UINT32 StallOverride:1 ; ///< - UINT32 MaxBurst:4 ; ///< - UINT32 LazyTimer:4 ; ///< - UINT32 StallOverrideWtm:1 ; ///< - UINT32 Reserved_31_16:16; ///< - } Field; ///< - UINT32 Value; ///< -} GMMx21B0_STRUCT; - -// **** GMMx21B4 Register Definition **** -// Address -#define GMMx21B4_ADDRESS 0x21b4 - -// Type -#define GMMx21B4_TYPE TYPE_GMM -// Field Data -#define GMMx21B4_Enable_OFFSET 0 -#define GMMx21B4_Enable_WIDTH 1 -#define GMMx21B4_Enable_MASK 0x1 -#define GMMx21B4_Prescale_OFFSET 1 -#define GMMx21B4_Prescale_WIDTH 2 -#define GMMx21B4_Prescale_MASK 0x6 -#define GMMx21B4_BlackoutExempt_OFFSET 3 -#define GMMx21B4_BlackoutExempt_WIDTH 1 -#define GMMx21B4_BlackoutExempt_MASK 0x8 -#define GMMx21B4_StallMode_OFFSET 4 -#define GMMx21B4_StallMode_WIDTH 2 -#define GMMx21B4_StallMode_MASK 0x30 -#define GMMx21B4_StallOverride_OFFSET 6 -#define GMMx21B4_StallOverride_WIDTH 1 -#define GMMx21B4_StallOverride_MASK 0x40 -#define GMMx21B4_MaxBurst_OFFSET 7 -#define GMMx21B4_MaxBurst_WIDTH 4 -#define GMMx21B4_MaxBurst_MASK 0x780 -#define GMMx21B4_LazyTimer_OFFSET 11 -#define GMMx21B4_LazyTimer_WIDTH 4 -#define GMMx21B4_LazyTimer_MASK 0x7800 -#define GMMx21B4_StallOverrideWtm_OFFSET 15 -#define GMMx21B4_StallOverrideWtm_WIDTH 1 -#define GMMx21B4_StallOverrideWtm_MASK 0x8000 -#define GMMx21B4_Reserved_31_16_OFFSET 16 -#define GMMx21B4_Reserved_31_16_WIDTH 16 -#define GMMx21B4_Reserved_31_16_MASK 0xffff0000 - -/// GMMx21B4 -typedef union { - struct { ///< - UINT32 Enable:1 ; ///< - UINT32 Prescale:2 ; ///< - UINT32 BlackoutExempt:1 ; ///< - UINT32 StallMode:2 ; ///< - UINT32 StallOverride:1 ; ///< - UINT32 MaxBurst:4 ; ///< - UINT32 LazyTimer:4 ; ///< - UINT32 StallOverrideWtm:1 ; ///< - UINT32 Reserved_31_16:16; ///< - } Field; ///< - UINT32 Value; ///< -} GMMx21B4_STRUCT; - -// **** GMMx21B8 Register Definition **** -// Address -#define GMMx21B8_ADDRESS 0x21b8 - -// Type -#define GMMx21B8_TYPE TYPE_GMM -// Field Data -#define GMMx21B8_Enable_OFFSET 0 -#define GMMx21B8_Enable_WIDTH 1 -#define GMMx21B8_Enable_MASK 0x1 -#define GMMx21B8_Prescale_OFFSET 1 -#define GMMx21B8_Prescale_WIDTH 2 -#define GMMx21B8_Prescale_MASK 0x6 -#define GMMx21B8_BlackoutExempt_OFFSET 3 -#define GMMx21B8_BlackoutExempt_WIDTH 1 -#define GMMx21B8_BlackoutExempt_MASK 0x8 -#define GMMx21B8_StallMode_OFFSET 4 -#define GMMx21B8_StallMode_WIDTH 2 -#define GMMx21B8_StallMode_MASK 0x30 -#define GMMx21B8_StallOverride_OFFSET 6 -#define GMMx21B8_StallOverride_WIDTH 1 -#define GMMx21B8_StallOverride_MASK 0x40 -#define GMMx21B8_MaxBurst_OFFSET 7 -#define GMMx21B8_MaxBurst_WIDTH 4 -#define GMMx21B8_MaxBurst_MASK 0x780 -#define GMMx21B8_LazyTimer_OFFSET 11 -#define GMMx21B8_LazyTimer_WIDTH 4 -#define GMMx21B8_LazyTimer_MASK 0x7800 -#define GMMx21B8_StallOverrideWtm_OFFSET 15 -#define GMMx21B8_StallOverrideWtm_WIDTH 1 -#define GMMx21B8_StallOverrideWtm_MASK 0x8000 -#define GMMx21B8_Reserved_31_16_OFFSET 16 -#define GMMx21B8_Reserved_31_16_WIDTH 16 -#define GMMx21B8_Reserved_31_16_MASK 0xffff0000 - -/// GMMx21B8 -typedef union { - struct { ///< - UINT32 Enable:1 ; ///< - UINT32 Prescale:2 ; ///< - UINT32 BlackoutExempt:1 ; ///< - UINT32 StallMode:2 ; ///< - UINT32 StallOverride:1 ; ///< - UINT32 MaxBurst:4 ; ///< - UINT32 LazyTimer:4 ; ///< - UINT32 StallOverrideWtm:1 ; ///< - UINT32 Reserved_31_16:16; ///< - } Field; ///< - UINT32 Value; ///< -} GMMx21B8_STRUCT; - -// **** GMMx21BC Register Definition **** -// Address -#define GMMx21BC_ADDRESS 0x21bc - -// Type -#define GMMx21BC_TYPE TYPE_GMM -// Field Data -#define GMMx21BC_Enable_OFFSET 0 -#define GMMx21BC_Enable_WIDTH 1 -#define GMMx21BC_Enable_MASK 0x1 -#define GMMx21BC_Prescale_OFFSET 1 -#define GMMx21BC_Prescale_WIDTH 2 -#define GMMx21BC_Prescale_MASK 0x6 -#define GMMx21BC_BlackoutExempt_OFFSET 3 -#define GMMx21BC_BlackoutExempt_WIDTH 1 -#define GMMx21BC_BlackoutExempt_MASK 0x8 -#define GMMx21BC_StallMode_OFFSET 4 -#define GMMx21BC_StallMode_WIDTH 2 -#define GMMx21BC_StallMode_MASK 0x30 -#define GMMx21BC_StallOverride_OFFSET 6 -#define GMMx21BC_StallOverride_WIDTH 1 -#define GMMx21BC_StallOverride_MASK 0x40 -#define GMMx21BC_MaxBurst_OFFSET 7 -#define GMMx21BC_MaxBurst_WIDTH 4 -#define GMMx21BC_MaxBurst_MASK 0x780 -#define GMMx21BC_LazyTimer_OFFSET 11 -#define GMMx21BC_LazyTimer_WIDTH 4 -#define GMMx21BC_LazyTimer_MASK 0x7800 -#define GMMx21BC_StallOverrideWtm_OFFSET 15 -#define GMMx21BC_StallOverrideWtm_WIDTH 1 -#define GMMx21BC_StallOverrideWtm_MASK 0x8000 -#define GMMx21BC_Reserved_31_16_OFFSET 16 -#define GMMx21BC_Reserved_31_16_WIDTH 16 -#define GMMx21BC_Reserved_31_16_MASK 0xffff0000 - -/// GMMx21BC -typedef union { - struct { ///< - UINT32 Enable:1 ; ///< - UINT32 Prescale:2 ; ///< - UINT32 BlackoutExempt:1 ; ///< - UINT32 StallMode:2 ; ///< - UINT32 StallOverride:1 ; ///< - UINT32 MaxBurst:4 ; ///< - UINT32 LazyTimer:4 ; ///< - UINT32 StallOverrideWtm:1 ; ///< - UINT32 Reserved_31_16:16; ///< - } Field; ///< - UINT32 Value; ///< -} GMMx21BC_STRUCT; - -// **** GMMx21C0 Register Definition **** -// Address -#define GMMx21C0_ADDRESS 0x21c0 - -// Type -#define GMMx21C0_TYPE TYPE_GMM -// Field Data -#define GMMx21C0_Enable_OFFSET 0 -#define GMMx21C0_Enable_WIDTH 1 -#define GMMx21C0_Enable_MASK 0x1 -#define GMMx21C0_Prescale_OFFSET 1 -#define GMMx21C0_Prescale_WIDTH 2 -#define GMMx21C0_Prescale_MASK 0x6 -#define GMMx21C0_BlackoutExempt_OFFSET 3 -#define GMMx21C0_BlackoutExempt_WIDTH 1 -#define GMMx21C0_BlackoutExempt_MASK 0x8 -#define GMMx21C0_StallMode_OFFSET 4 -#define GMMx21C0_StallMode_WIDTH 2 -#define GMMx21C0_StallMode_MASK 0x30 -#define GMMx21C0_StallOverride_OFFSET 6 -#define GMMx21C0_StallOverride_WIDTH 1 -#define GMMx21C0_StallOverride_MASK 0x40 -#define GMMx21C0_MaxBurst_OFFSET 7 -#define GMMx21C0_MaxBurst_WIDTH 4 -#define GMMx21C0_MaxBurst_MASK 0x780 -#define GMMx21C0_LazyTimer_OFFSET 11 -#define GMMx21C0_LazyTimer_WIDTH 4 -#define GMMx21C0_LazyTimer_MASK 0x7800 -#define GMMx21C0_StallOverrideWtm_OFFSET 15 -#define GMMx21C0_StallOverrideWtm_WIDTH 1 -#define GMMx21C0_StallOverrideWtm_MASK 0x8000 -#define GMMx21C0_Reserved_31_16_OFFSET 16 -#define GMMx21C0_Reserved_31_16_WIDTH 16 -#define GMMx21C0_Reserved_31_16_MASK 0xffff0000 - -/// GMMx21C0 -typedef union { - struct { ///< - UINT32 Enable:1 ; ///< - UINT32 Prescale:2 ; ///< - UINT32 BlackoutExempt:1 ; ///< - UINT32 StallMode:2 ; ///< - UINT32 StallOverride:1 ; ///< - UINT32 MaxBurst:4 ; ///< - UINT32 LazyTimer:4 ; ///< - UINT32 StallOverrideWtm:1 ; ///< - UINT32 Reserved_31_16:16; ///< - } Field; ///< - UINT32 Value; ///< -} GMMx21C0_STRUCT; - -// **** GMMx21C4 Register Definition **** -// Address -#define GMMx21C4_ADDRESS 0x21c4 - -// Type -#define GMMx21C4_TYPE TYPE_GMM -// Field Data -#define GMMx21C4_Enable_OFFSET 0 -#define GMMx21C4_Enable_WIDTH 1 -#define GMMx21C4_Enable_MASK 0x1 -#define GMMx21C4_Prescale_OFFSET 1 -#define GMMx21C4_Prescale_WIDTH 2 -#define GMMx21C4_Prescale_MASK 0x6 -#define GMMx21C4_BlackoutExempt_OFFSET 3 -#define GMMx21C4_BlackoutExempt_WIDTH 1 -#define GMMx21C4_BlackoutExempt_MASK 0x8 -#define GMMx21C4_StallMode_OFFSET 4 -#define GMMx21C4_StallMode_WIDTH 2 -#define GMMx21C4_StallMode_MASK 0x30 -#define GMMx21C4_StallOverride_OFFSET 6 -#define GMMx21C4_StallOverride_WIDTH 1 -#define GMMx21C4_StallOverride_MASK 0x40 -#define GMMx21C4_MaxBurst_OFFSET 7 -#define GMMx21C4_MaxBurst_WIDTH 4 -#define GMMx21C4_MaxBurst_MASK 0x780 -#define GMMx21C4_LazyTimer_OFFSET 11 -#define GMMx21C4_LazyTimer_WIDTH 4 -#define GMMx21C4_LazyTimer_MASK 0x7800 -#define GMMx21C4_StallOverrideWtm_OFFSET 15 -#define GMMx21C4_StallOverrideWtm_WIDTH 1 -#define GMMx21C4_StallOverrideWtm_MASK 0x8000 -#define GMMx21C4_Reserved_31_16_OFFSET 16 -#define GMMx21C4_Reserved_31_16_WIDTH 16 -#define GMMx21C4_Reserved_31_16_MASK 0xffff0000 - -/// GMMx21C4 -typedef union { - struct { ///< - UINT32 Enable:1 ; ///< - UINT32 Prescale:2 ; ///< - UINT32 BlackoutExempt:1 ; ///< - UINT32 StallMode:2 ; ///< - UINT32 StallOverride:1 ; ///< - UINT32 MaxBurst:4 ; ///< - UINT32 LazyTimer:4 ; ///< - UINT32 StallOverrideWtm:1 ; ///< - UINT32 Reserved_31_16:16; ///< - } Field; ///< - UINT32 Value; ///< -} GMMx21C4_STRUCT; - -// **** GMMx21C8 Register Definition **** -// Address -#define GMMx21C8_ADDRESS 0x21c8 - -// Type -#define GMMx21C8_TYPE TYPE_GMM -// Field Data -#define GMMx21C8_Enable_OFFSET 0 -#define GMMx21C8_Enable_WIDTH 1 -#define GMMx21C8_Enable_MASK 0x1 -#define GMMx21C8_Prescale_OFFSET 1 -#define GMMx21C8_Prescale_WIDTH 2 -#define GMMx21C8_Prescale_MASK 0x6 -#define GMMx21C8_BlackoutExempt_OFFSET 3 -#define GMMx21C8_BlackoutExempt_WIDTH 1 -#define GMMx21C8_BlackoutExempt_MASK 0x8 -#define GMMx21C8_StallMode_OFFSET 4 -#define GMMx21C8_StallMode_WIDTH 2 -#define GMMx21C8_StallMode_MASK 0x30 -#define GMMx21C8_StallOverride_OFFSET 6 -#define GMMx21C8_StallOverride_WIDTH 1 -#define GMMx21C8_StallOverride_MASK 0x40 -#define GMMx21C8_MaxBurst_OFFSET 7 -#define GMMx21C8_MaxBurst_WIDTH 4 -#define GMMx21C8_MaxBurst_MASK 0x780 -#define GMMx21C8_LazyTimer_OFFSET 11 -#define GMMx21C8_LazyTimer_WIDTH 4 -#define GMMx21C8_LazyTimer_MASK 0x7800 -#define GMMx21C8_StallOverrideWtm_OFFSET 15 -#define GMMx21C8_StallOverrideWtm_WIDTH 1 -#define GMMx21C8_StallOverrideWtm_MASK 0x8000 -#define GMMx21C8_Reserved_31_16_OFFSET 16 -#define GMMx21C8_Reserved_31_16_WIDTH 16 -#define GMMx21C8_Reserved_31_16_MASK 0xffff0000 - -/// GMMx21C8 -typedef union { - struct { ///< - UINT32 Enable:1 ; ///< - UINT32 Prescale:2 ; ///< - UINT32 BlackoutExempt:1 ; ///< - UINT32 StallMode:2 ; ///< - UINT32 StallOverride:1 ; ///< - UINT32 MaxBurst:4 ; ///< - UINT32 LazyTimer:4 ; ///< - UINT32 StallOverrideWtm:1 ; ///< - UINT32 Reserved_31_16:16; ///< - } Field; ///< - UINT32 Value; ///< -} GMMx21C8_STRUCT; - -// **** GMMx21CC Register Definition **** -// Address -#define GMMx21CC_ADDRESS 0x21cc - -// Type -#define GMMx21CC_TYPE TYPE_GMM -// Field Data -#define GMMx21CC_Enable_OFFSET 0 -#define GMMx21CC_Enable_WIDTH 1 -#define GMMx21CC_Enable_MASK 0x1 -#define GMMx21CC_Prescale_OFFSET 1 -#define GMMx21CC_Prescale_WIDTH 2 -#define GMMx21CC_Prescale_MASK 0x6 -#define GMMx21CC_BlackoutExempt_OFFSET 3 -#define GMMx21CC_BlackoutExempt_WIDTH 1 -#define GMMx21CC_BlackoutExempt_MASK 0x8 -#define GMMx21CC_StallMode_OFFSET 4 -#define GMMx21CC_StallMode_WIDTH 2 -#define GMMx21CC_StallMode_MASK 0x30 -#define GMMx21CC_StallOverride_OFFSET 6 -#define GMMx21CC_StallOverride_WIDTH 1 -#define GMMx21CC_StallOverride_MASK 0x40 -#define GMMx21CC_MaxBurst_OFFSET 7 -#define GMMx21CC_MaxBurst_WIDTH 4 -#define GMMx21CC_MaxBurst_MASK 0x780 -#define GMMx21CC_LazyTimer_OFFSET 11 -#define GMMx21CC_LazyTimer_WIDTH 4 -#define GMMx21CC_LazyTimer_MASK 0x7800 -#define GMMx21CC_StallOverrideWtm_OFFSET 15 -#define GMMx21CC_StallOverrideWtm_WIDTH 1 -#define GMMx21CC_StallOverrideWtm_MASK 0x8000 -#define GMMx21CC_Reserved_31_16_OFFSET 16 -#define GMMx21CC_Reserved_31_16_WIDTH 16 -#define GMMx21CC_Reserved_31_16_MASK 0xffff0000 - -/// GMMx21CC -typedef union { - struct { ///< - UINT32 Enable:1 ; ///< - UINT32 Prescale:2 ; ///< - UINT32 BlackoutExempt:1 ; ///< - UINT32 StallMode:2 ; ///< - UINT32 StallOverride:1 ; ///< - UINT32 MaxBurst:4 ; ///< - UINT32 LazyTimer:4 ; ///< - UINT32 StallOverrideWtm:1 ; ///< - UINT32 Reserved_31_16:16; ///< - } Field; ///< - UINT32 Value; ///< -} GMMx21CC_STRUCT; - -// **** GMMx21D0 Register Definition **** -// Address -#define GMMx21D0_ADDRESS 0x21d0 - -// Type -#define GMMx21D0_TYPE TYPE_GMM -// Field Data -#define GMMx21D0_Enable_OFFSET 0 -#define GMMx21D0_Enable_WIDTH 1 -#define GMMx21D0_Enable_MASK 0x1 -#define GMMx21D0_Prescale_OFFSET 1 -#define GMMx21D0_Prescale_WIDTH 2 -#define GMMx21D0_Prescale_MASK 0x6 -#define GMMx21D0_BlackoutExempt_OFFSET 3 -#define GMMx21D0_BlackoutExempt_WIDTH 1 -#define GMMx21D0_BlackoutExempt_MASK 0x8 -#define GMMx21D0_StallMode_OFFSET 4 -#define GMMx21D0_StallMode_WIDTH 2 -#define GMMx21D0_StallMode_MASK 0x30 -#define GMMx21D0_StallOverride_OFFSET 6 -#define GMMx21D0_StallOverride_WIDTH 1 -#define GMMx21D0_StallOverride_MASK 0x40 -#define GMMx21D0_MaxBurst_OFFSET 7 -#define GMMx21D0_MaxBurst_WIDTH 4 -#define GMMx21D0_MaxBurst_MASK 0x780 -#define GMMx21D0_LazyTimer_OFFSET 11 -#define GMMx21D0_LazyTimer_WIDTH 4 -#define GMMx21D0_LazyTimer_MASK 0x7800 -#define GMMx21D0_StallOverrideWtm_OFFSET 15 -#define GMMx21D0_StallOverrideWtm_WIDTH 1 -#define GMMx21D0_StallOverrideWtm_MASK 0x8000 -#define GMMx21D0_Reserved_31_16_OFFSET 16 -#define GMMx21D0_Reserved_31_16_WIDTH 16 -#define GMMx21D0_Reserved_31_16_MASK 0xffff0000 - -/// GMMx21D0 -typedef union { - struct { ///< - UINT32 Enable:1 ; ///< - UINT32 Prescale:2 ; ///< - UINT32 BlackoutExempt:1 ; ///< - UINT32 StallMode:2 ; ///< - UINT32 StallOverride:1 ; ///< - UINT32 MaxBurst:4 ; ///< - UINT32 LazyTimer:4 ; ///< - UINT32 StallOverrideWtm:1 ; ///< - UINT32 Reserved_31_16:16; ///< - } Field; ///< - UINT32 Value; ///< -} GMMx21D0_STRUCT; - -// **** GMMx2478 Register Definition **** -// Address -#define GMMx2478_ADDRESS 0x2478 - -// Type -#define GMMx2478_TYPE TYPE_GMM -// Field Data -#define GMMx2478_OnDly_OFFSET 0 -#define GMMx2478_OnDly_WIDTH 6 -#define GMMx2478_OnDly_MASK 0x3f -#define GMMx2478_OffDly_OFFSET 6 -#define GMMx2478_OffDly_WIDTH 6 -#define GMMx2478_OffDly_MASK 0xfc0 -#define GMMx2478_RdyDly_OFFSET 12 -#define GMMx2478_RdyDly_WIDTH 6 -#define GMMx2478_RdyDly_MASK 0x3f000 -#define GMMx2478_Enable_OFFSET 18 -#define GMMx2478_Enable_WIDTH 1 -#define GMMx2478_Enable_MASK 0x40000 -#define GMMx2478_Reserved_31_19_OFFSET 19 -#define GMMx2478_Reserved_31_19_WIDTH 13 -#define GMMx2478_Reserved_31_19_MASK 0xfff80000 - -/// GMMx2478 -typedef union { - struct { ///< - UINT32 OnDly:6 ; ///< - UINT32 OffDly:6 ; ///< - UINT32 RdyDly:6 ; ///< - UINT32 Enable:1 ; ///< - UINT32 Reserved_31_19:13; ///< - } Field; ///< - UINT32 Value; ///< -} GMMx2478_STRUCT; - -// **** GMMx25C0 Register Definition **** -// Address -#define GMMx25C0_ADDRESS 0x25c0 - -// Type -#define GMMx25C0_TYPE TYPE_GMM -// Field Data -#define GMMx25C0_BlackoutRd_OFFSET 0 -#define GMMx25C0_BlackoutRd_WIDTH 1 -#define GMMx25C0_BlackoutRd_MASK 0x1 -#define GMMx25C0_BlackoutWr_OFFSET 1 -#define GMMx25C0_BlackoutWr_WIDTH 1 -#define GMMx25C0_BlackoutWr_MASK 0x2 -#define GMMx25C0_Reserved_31_2_OFFSET 2 -#define GMMx25C0_Reserved_31_2_WIDTH 30 -#define GMMx25C0_Reserved_31_2_MASK 0xfffffffc - -/// GMMx25C0 -typedef union { - struct { ///< - UINT32 BlackoutRd:1 ; ///< - UINT32 BlackoutWr:1 ; ///< - UINT32 Reserved_31_2:30; ///< - } Field; ///< - UINT32 Value; ///< -} GMMx25C0_STRUCT; - -// **** GMMx25C8 Register Definition **** -// Address -#define GMMx25C8_ADDRESS 0x25c8 - -// Type -#define GMMx25C8_TYPE TYPE_GMM -// Field Data -#define GMMx25C8_ReadLcl_OFFSET 0 -#define GMMx25C8_ReadLcl_WIDTH 8 -#define GMMx25C8_ReadLcl_MASK 0xff -#define GMMx25C8_ReadHub_OFFSET 8 -#define GMMx25C8_ReadHub_WIDTH 8 -#define GMMx25C8_ReadHub_MASK 0xff00 -#define GMMx25C8_ReadPri_OFFSET 16 -#define GMMx25C8_ReadPri_WIDTH 8 -#define GMMx25C8_ReadPri_MASK 0xff0000 -#define GMMx25C8_LclPri_OFFSET 24 -#define GMMx25C8_LclPri_WIDTH 1 -#define GMMx25C8_LclPri_MASK 0x1000000 -#define GMMx25C8_HubPri_OFFSET 25 -#define GMMx25C8_HubPri_WIDTH 1 -#define GMMx25C8_HubPri_MASK 0x2000000 -#define GMMx25C8_Reserved_31_26_OFFSET 26 -#define GMMx25C8_Reserved_31_26_WIDTH 6 -#define GMMx25C8_Reserved_31_26_MASK 0xfc000000 - -/// GMMx25C8 -typedef union { - struct { ///< - UINT32 ReadLcl:8 ; ///< - UINT32 ReadHub:8 ; ///< - UINT32 ReadPri:8 ; ///< - UINT32 LclPri:1 ; ///< - UINT32 HubPri:1 ; ///< - UINT32 Reserved_31_26:6 ; ///< - } Field; ///< - UINT32 Value; ///< -} GMMx25C8_STRUCT; - -// **** GMMx25CC Register Definition **** -// Address -#define GMMx25CC_ADDRESS 0x25cc - -// Type -#define GMMx25CC_TYPE TYPE_GMM -// Field Data -#define GMMx25CC_WriteLcl_OFFSET 0 -#define GMMx25CC_WriteLcl_WIDTH 8 -#define GMMx25CC_WriteLcl_MASK 0xff -#define GMMx25CC_WriteHub_OFFSET 8 -#define GMMx25CC_WriteHub_WIDTH 8 -#define GMMx25CC_WriteHub_MASK 0xff00 -#define GMMx25CC_HubPri_OFFSET 16 -#define GMMx25CC_HubPri_WIDTH 1 -#define GMMx25CC_HubPri_MASK 0x10000 -#define GMMx25CC_Reserved_31_17_OFFSET 17 -#define GMMx25CC_Reserved_31_17_WIDTH 15 -#define GMMx25CC_Reserved_31_17_MASK 0xfffe0000 - -/// GMMx25CC -typedef union { - struct { ///< - UINT32 WriteLcl:8 ; ///< - UINT32 WriteHub:8 ; ///< - UINT32 HubPri:1 ; ///< - UINT32 Reserved_31_17:15; ///< - } Field; ///< - UINT32 Value; ///< -} GMMx25CC_STRUCT; - -// **** GMMx2620 Register Definition **** -// Address -#define GMMx2620_ADDRESS 0x2620 - -// Type -#define GMMx2620_TYPE TYPE_GMM -// Field Data -#define GMMx2620_TctFetch0_OFFSET 0 -#define GMMx2620_TctFetch0_WIDTH 4 -#define GMMx2620_TctFetch0_MASK 0xf -#define GMMx2620_TcvFetch0_OFFSET 4 -#define GMMx2620_TcvFetch0_WIDTH 4 -#define GMMx2620_TcvFetch0_MASK 0xf0 -#define GMMx2620_Vc0_OFFSET 8 -#define GMMx2620_Vc0_WIDTH 4 -#define GMMx2620_Vc0_MASK 0xf00 -#define GMMx2620_Cb0_OFFSET 12 -#define GMMx2620_Cb0_WIDTH 4 -#define GMMx2620_Cb0_MASK 0xf000 -#define GMMx2620_CbcMask0_OFFSET 16 -#define GMMx2620_CbcMask0_WIDTH 4 -#define GMMx2620_CbcMask0_MASK 0xf0000 -#define GMMx2620_CbfMask0_OFFSET 20 -#define GMMx2620_CbfMask0_WIDTH 4 -#define GMMx2620_CbfMask0_MASK 0xf00000 -#define GMMx2620_Db0_OFFSET 24 -#define GMMx2620_Db0_WIDTH 4 -#define GMMx2620_Db0_MASK 0xf000000 -#define GMMx2620_DbhTile0_OFFSET 28 -#define GMMx2620_DbhTile0_WIDTH 4 -#define GMMx2620_DbhTile0_MASK 0xf0000000 - -/// GMMx2620 -typedef union { - struct { ///< - UINT32 TctFetch0:4 ; ///< - UINT32 TcvFetch0:4 ; ///< - UINT32 Vc0:4 ; ///< - UINT32 Cb0:4 ; ///< - UINT32 CbcMask0:4 ; ///< - UINT32 CbfMask0:4 ; ///< - UINT32 Db0:4 ; ///< - UINT32 DbhTile0:4 ; ///< - } Field; ///< - UINT32 Value; ///< -} GMMx2620_STRUCT; - -// **** GMMx2624 Register Definition **** -// Address -#define GMMx2624_ADDRESS 0x2624 - -// Type -#define GMMx2624_TYPE TYPE_GMM -// Field Data -#define GMMx2624_Cb0_OFFSET 0 -#define GMMx2624_Cb0_WIDTH 4 -#define GMMx2624_Cb0_MASK 0xf -#define GMMx2624_CbcMask0_OFFSET 4 -#define GMMx2624_CbcMask0_WIDTH 4 -#define GMMx2624_CbcMask0_MASK 0xf0 -#define GMMx2624_CbfMask0_OFFSET 8 -#define GMMx2624_CbfMask0_WIDTH 4 -#define GMMx2624_CbfMask0_MASK 0xf00 -#define GMMx2624_Db0_OFFSET 12 -#define GMMx2624_Db0_WIDTH 4 -#define GMMx2624_Db0_MASK 0xf000 -#define GMMx2624_DbhTile0_OFFSET 16 -#define GMMx2624_DbhTile0_WIDTH 4 -#define GMMx2624_DbhTile0_MASK 0xf0000 -#define GMMx2624_Sx0_OFFSET 20 -#define GMMx2624_Sx0_WIDTH 4 -#define GMMx2624_Sx0_MASK 0xf00000 -#define GMMx2624_Bcast0_OFFSET 24 -#define GMMx2624_Bcast0_WIDTH 4 -#define GMMx2624_Bcast0_MASK 0xf000000 -#define GMMx2624_Cbimmed0_OFFSET 28 -#define GMMx2624_Cbimmed0_WIDTH 4 -#define GMMx2624_Cbimmed0_MASK 0xf0000000 - -/// GMMx2624 -typedef union { - struct { ///< - UINT32 Cb0:4 ; ///< - UINT32 CbcMask0:4 ; ///< - UINT32 CbfMask0:4 ; ///< - UINT32 Db0:4 ; ///< - UINT32 DbhTile0:4 ; ///< - UINT32 Sx0:4 ; ///< - UINT32 Bcast0:4 ; ///< - UINT32 Cbimmed0:4 ; ///< - } Field; ///< - UINT32 Value; ///< -} GMMx2624_STRUCT; - -// **** GMMx2628 Register Definition **** -// Address -#define GMMx2628_ADDRESS 0x2628 - -// Type -#define GMMx2628_TYPE TYPE_GMM -// Field Data -#define GMMx2628_TctFetch1_OFFSET 0 -#define GMMx2628_TctFetch1_WIDTH 4 -#define GMMx2628_TctFetch1_MASK 0xf -#define GMMx2628_TcvFetch1_OFFSET 4 -#define GMMx2628_TcvFetch1_WIDTH 4 -#define GMMx2628_TcvFetch1_MASK 0xf0 -#define GMMx2628_Vc1_OFFSET 8 -#define GMMx2628_Vc1_WIDTH 4 -#define GMMx2628_Vc1_MASK 0xf00 -#define GMMx2628_Cb1_OFFSET 12 -#define GMMx2628_Cb1_WIDTH 4 -#define GMMx2628_Cb1_MASK 0xf000 -#define GMMx2628_CbcMask1_OFFSET 16 -#define GMMx2628_CbcMask1_WIDTH 4 -#define GMMx2628_CbcMask1_MASK 0xf0000 -#define GMMx2628_CbfMask1_OFFSET 20 -#define GMMx2628_CbfMask1_WIDTH 4 -#define GMMx2628_CbfMask1_MASK 0xf00000 -#define GMMx2628_Db1_OFFSET 24 -#define GMMx2628_Db1_WIDTH 4 -#define GMMx2628_Db1_MASK 0xf000000 -#define GMMx2628_DbhTile1_OFFSET 28 -#define GMMx2628_DbhTile1_WIDTH 4 -#define GMMx2628_DbhTile1_MASK 0xf0000000 - -/// GMMx2628 -typedef union { - struct { ///< - UINT32 TctFetch1:4 ; ///< - UINT32 TcvFetch1:4 ; ///< - UINT32 Vc1:4 ; ///< - UINT32 Cb1:4 ; ///< - UINT32 CbcMask1:4 ; ///< - UINT32 CbfMask1:4 ; ///< - UINT32 Db1:4 ; ///< - UINT32 DbhTile1:4 ; ///< - } Field; ///< - UINT32 Value; ///< -} GMMx2628_STRUCT; - -// **** GMMx262C Register Definition **** -// Address -#define GMMx262C_ADDRESS 0x262c - -// Type -#define GMMx262C_TYPE TYPE_GMM -// Field Data -#define GMMx262C_Cb1_OFFSET 0 -#define GMMx262C_Cb1_WIDTH 4 -#define GMMx262C_Cb1_MASK 0xf -#define GMMx262C_CbcMask1_OFFSET 4 -#define GMMx262C_CbcMask1_WIDTH 4 -#define GMMx262C_CbcMask1_MASK 0xf0 -#define GMMx262C_CbfMask1_OFFSET 8 -#define GMMx262C_CbfMask1_WIDTH 4 -#define GMMx262C_CbfMask1_MASK 0xf00 -#define GMMx262C_Db1_OFFSET 12 -#define GMMx262C_Db1_WIDTH 4 -#define GMMx262C_Db1_MASK 0xf000 -#define GMMx262C_DbhTile1_OFFSET 16 -#define GMMx262C_DbhTile1_WIDTH 4 -#define GMMx262C_DbhTile1_MASK 0xf0000 -#define GMMx262C_Sx1_OFFSET 20 -#define GMMx262C_Sx1_WIDTH 4 -#define GMMx262C_Sx1_MASK 0xf00000 -#define GMMx262C_Bcast1_OFFSET 24 -#define GMMx262C_Bcast1_WIDTH 4 -#define GMMx262C_Bcast1_MASK 0xf000000 -#define GMMx262C_Cbimmed1_OFFSET 28 -#define GMMx262C_Cbimmed1_WIDTH 4 -#define GMMx262C_Cbimmed1_MASK 0xf0000000 - -/// GMMx262C -typedef union { - struct { ///< - UINT32 Cb1:4 ; ///< - UINT32 CbcMask1:4 ; ///< - UINT32 CbfMask1:4 ; ///< - UINT32 Db1:4 ; ///< - UINT32 DbhTile1:4 ; ///< - UINT32 Sx1:4 ; ///< - UINT32 Bcast1:4 ; ///< - UINT32 Cbimmed1:4 ; ///< - } Field; ///< - UINT32 Value; ///< -} GMMx262C_STRUCT; - -// **** GMMx2630 Register Definition **** -// Address -#define GMMx2630_ADDRESS 0x2630 - -// Type -#define GMMx2630_TYPE TYPE_GMM -// Field Data -#define GMMx2630_DbstEn0_OFFSET 0 -#define GMMx2630_DbstEn0_WIDTH 4 -#define GMMx2630_DbstEn0_MASK 0xf -#define GMMx2630_DbstEn1_OFFSET 4 -#define GMMx2630_DbstEn1_WIDTH 4 -#define GMMx2630_DbstEn1_MASK 0xf0 -#define GMMx2630_Reserved_31_8_OFFSET 8 -#define GMMx2630_Reserved_31_8_WIDTH 24 -#define GMMx2630_Reserved_31_8_MASK 0xffffff00 - -/// GMMx2630 -typedef union { - struct { ///< - UINT32 DbstEn0:4 ; ///< - UINT32 DbstEn1:4 ; ///< - UINT32 Reserved_31_8:24; ///< - } Field; ///< - UINT32 Value; ///< -} GMMx2630_STRUCT; - -// **** GMMx2634 Register Definition **** -// Address -#define GMMx2634_ADDRESS 0x2634 - -// Type -#define GMMx2634_TYPE TYPE_GMM -// Field Data -#define GMMx2634_DbstEn0_OFFSET 0 -#define GMMx2634_DbstEn0_WIDTH 4 -#define GMMx2634_DbstEn0_MASK 0xf -#define GMMx2634_DbstEn1_OFFSET 4 -#define GMMx2634_DbstEn1_WIDTH 4 -#define GMMx2634_DbstEn1_MASK 0xf0 -#define GMMx2634_Reserved_31_8_OFFSET 8 -#define GMMx2634_Reserved_31_8_WIDTH 24 -#define GMMx2634_Reserved_31_8_MASK 0xffffff00 - -/// GMMx2634 -typedef union { - struct { ///< - UINT32 DbstEn0:4 ; ///< - UINT32 DbstEn1:4 ; ///< - UINT32 Reserved_31_8:24; ///< - } Field; ///< - UINT32 Value; ///< -} GMMx2634_STRUCT; - -// **** GMMx2650 Register Definition **** -// Address -#define GMMx2650_ADDRESS 0x2650 - -// Type -#define GMMx2650_TYPE TYPE_GMM -// Field Data -#define GMMx2650_OnDly_OFFSET 0 -#define GMMx2650_OnDly_WIDTH 6 -#define GMMx2650_OnDly_MASK 0x3f -#define GMMx2650_OffDly_OFFSET 6 -#define GMMx2650_OffDly_WIDTH 6 -#define GMMx2650_OffDly_MASK 0xfc0 -#define GMMx2650_RdyDly_OFFSET 12 -#define GMMx2650_RdyDly_WIDTH 6 -#define GMMx2650_RdyDly_MASK 0x3f000 -#define GMMx2650_Enable_OFFSET 18 -#define GMMx2650_Enable_WIDTH 1 -#define GMMx2650_Enable_MASK 0x40000 -#define GMMx2650_Reserved_31_19_OFFSET 19 -#define GMMx2650_Reserved_31_19_WIDTH 13 -#define GMMx2650_Reserved_31_19_MASK 0xfff80000 - -/// GMMx2650 -typedef union { - struct { ///< - UINT32 OnDly:6 ; ///< - UINT32 OffDly:6 ; ///< - UINT32 RdyDly:6 ; ///< - UINT32 Enable:1 ; ///< - UINT32 Reserved_31_19:13; ///< - } Field; ///< - UINT32 Value; ///< -} GMMx2650_STRUCT; - -// **** GMMx2654 Register Definition **** -// Address -#define GMMx2654_ADDRESS 0x2654 - -// Type -#define GMMx2654_TYPE TYPE_GMM -// Field Data -#define GMMx2654_OnDly_OFFSET 0 -#define GMMx2654_OnDly_WIDTH 6 -#define GMMx2654_OnDly_MASK 0x3f -#define GMMx2654_OffDly_OFFSET 6 -#define GMMx2654_OffDly_WIDTH 6 -#define GMMx2654_OffDly_MASK 0xfc0 -#define GMMx2654_RdyDly_OFFSET 12 -#define GMMx2654_RdyDly_WIDTH 6 -#define GMMx2654_RdyDly_MASK 0x3f000 -#define GMMx2654_Enable_OFFSET 18 -#define GMMx2654_Enable_WIDTH 1 -#define GMMx2654_Enable_MASK 0x40000 -#define GMMx2654_Reserved_31_19_OFFSET 19 -#define GMMx2654_Reserved_31_19_WIDTH 13 -#define GMMx2654_Reserved_31_19_MASK 0xfff80000 - -/// GMMx2654 -typedef union { - struct { ///< - UINT32 OnDly:6 ; ///< - UINT32 OffDly:6 ; ///< - UINT32 RdyDly:6 ; ///< - UINT32 Enable:1 ; ///< - UINT32 Reserved_31_19:13; ///< - } Field; ///< - UINT32 Value; ///< -} GMMx2654_STRUCT; - -// **** GMMx2658 Register Definition **** -// Address -#define GMMx2658_ADDRESS 0x2658 - -// Type -#define GMMx2658_TYPE TYPE_GMM -// Field Data -#define GMMx2658_OnDly_OFFSET 0 -#define GMMx2658_OnDly_WIDTH 6 -#define GMMx2658_OnDly_MASK 0x3f -#define GMMx2658_OffDly_OFFSET 6 -#define GMMx2658_OffDly_WIDTH 6 -#define GMMx2658_OffDly_MASK 0xfc0 -#define GMMx2658_RdyDly_OFFSET 12 -#define GMMx2658_RdyDly_WIDTH 6 -#define GMMx2658_RdyDly_MASK 0x3f000 -#define GMMx2658_Enable_OFFSET 18 -#define GMMx2658_Enable_WIDTH 1 -#define GMMx2658_Enable_MASK 0x40000 -#define GMMx2658_Reserved_31_19_OFFSET 19 -#define GMMx2658_Reserved_31_19_WIDTH 13 -#define GMMx2658_Reserved_31_19_MASK 0xfff80000 - -/// GMMx2658 -typedef union { - struct { ///< - UINT32 OnDly:6 ; ///< - UINT32 OffDly:6 ; ///< - UINT32 RdyDly:6 ; ///< - UINT32 Enable:1 ; ///< - UINT32 Reserved_31_19:13; ///< - } Field; ///< - UINT32 Value; ///< -} GMMx2658_STRUCT; - -// **** GMMx277C Register Definition **** -// Address -#define GMMx277C_ADDRESS 0x277c - -// Type -#define GMMx277C_TYPE TYPE_GMM -// Field Data -#define GMMx277C_ActRd_OFFSET 0 -#define GMMx277C_ActRd_WIDTH 8 -#define GMMx277C_ActRd_MASK 0xff -#define GMMx277C_ActWr_OFFSET 8 -#define GMMx277C_ActWr_WIDTH 8 -#define GMMx277C_ActWr_MASK 0xff00 -#define GMMx277C_RasMActRd_OFFSET 16 -#define GMMx277C_RasMActRd_WIDTH 8 -#define GMMx277C_RasMActRd_MASK 0xff0000 -#define GMMx277C_RasMActWr_OFFSET 24 -#define GMMx277C_RasMActWr_WIDTH 8 -#define GMMx277C_RasMActWr_MASK 0xff000000 - -/// GMMx277C -typedef union { - struct { ///< - UINT32 ActRd:8 ; ///< - UINT32 ActWr:8 ; ///< - UINT32 RasMActRd:8 ; ///< - UINT32 RasMActWr:8 ; ///< - } Field; ///< - UINT32 Value; ///< -} GMMx277C_STRUCT; - -// **** GMMx2780 Register Definition **** -// Address -#define GMMx2780_ADDRESS 0x2780 - -// Type -#define GMMx2780_TYPE TYPE_GMM -// Field Data -#define GMMx2780_Ras2Ras_OFFSET 0 -#define GMMx2780_Ras2Ras_WIDTH 8 -#define GMMx2780_Ras2Ras_MASK 0xff -#define GMMx2780_Rp_OFFSET 8 -#define GMMx2780_Rp_WIDTH 8 -#define GMMx2780_Rp_MASK 0xff00 -#define GMMx2780_WrPlusRp_OFFSET 16 -#define GMMx2780_WrPlusRp_WIDTH 8 -#define GMMx2780_WrPlusRp_MASK 0xff0000 -#define GMMx2780_BusTurn_OFFSET 24 -#define GMMx2780_BusTurn_WIDTH 8 -#define GMMx2780_BusTurn_MASK 0xff000000 - -/// GMMx2780 -typedef union { - struct { ///< - UINT32 Ras2Ras:8 ; ///< - UINT32 Rp:8 ; ///< - UINT32 WrPlusRp:8 ; ///< - UINT32 BusTurn:8 ; ///< - } Field; ///< - UINT32 Value; ///< -} GMMx2780_STRUCT; - -// **** GMMx2784 Register Definition **** -// Address -#define GMMx2784_ADDRESS 0x2784 - -// Type -#define GMMx2784_TYPE TYPE_GMM -// Field Data -#define GMMx2784_WtMode_OFFSET 0 -#define GMMx2784_WtMode_WIDTH 2 -#define GMMx2784_WtMode_MASK 0x3 -#define GMMx2784_HarshPri_OFFSET 2 -#define GMMx2784_HarshPri_WIDTH 1 -#define GMMx2784_HarshPri_MASK 0x4 -#define GMMx2784_Reserved_31_3_OFFSET 3 -#define GMMx2784_Reserved_31_3_WIDTH 29 -#define GMMx2784_Reserved_31_3_MASK 0xfffffff8 - -/// GMMx2784 -typedef union { - struct { ///< - UINT32 WtMode:2 ; ///< - UINT32 HarshPri:1 ; ///< - UINT32 Reserved_31_3:29; ///< - } Field; ///< - UINT32 Value; ///< -} GMMx2784_STRUCT; - -// **** GMMx2788 Register Definition **** -// Address -#define GMMx2788_ADDRESS 0x2788 - -// Type -#define GMMx2788_TYPE TYPE_GMM -// Field Data -#define GMMx2788_WtMode_OFFSET 0 -#define GMMx2788_WtMode_WIDTH 2 -#define GMMx2788_WtMode_MASK 0x3 -#define GMMx2788_HarshPri_OFFSET 2 -#define GMMx2788_HarshPri_WIDTH 1 -#define GMMx2788_HarshPri_MASK 0x4 -#define GMMx2788_Reserved_31_3_OFFSET 3 -#define GMMx2788_Reserved_31_3_WIDTH 29 -#define GMMx2788_Reserved_31_3_MASK 0xfffffff8 - -/// GMMx2788 -typedef union { - struct { ///< - UINT32 WtMode:2 ; ///< - UINT32 HarshPri:1 ; ///< - UINT32 Reserved_31_3:29; ///< - } Field; ///< - UINT32 Value; ///< -} GMMx2788_STRUCT; - -// **** GMMx279C Register Definition **** -// Address -#define GMMx279C_ADDRESS 0x279c - -// Type -#define GMMx279C_TYPE TYPE_GMM -// Field Data -#define GMMx279C_Group0_OFFSET 0 -#define GMMx279C_Group0_WIDTH 8 -#define GMMx279C_Group0_MASK 0xff -#define GMMx279C_Group1_OFFSET 8 -#define GMMx279C_Group1_WIDTH 8 -#define GMMx279C_Group1_MASK 0xff00 -#define GMMx279C_Group2_OFFSET 16 -#define GMMx279C_Group2_WIDTH 8 -#define GMMx279C_Group2_MASK 0xff0000 -#define GMMx279C_Group3_OFFSET 24 -#define GMMx279C_Group3_WIDTH 8 -#define GMMx279C_Group3_MASK 0xff000000 - -/// GMMx279C -typedef union { - struct { ///< - UINT32 Group0:8 ; ///< - UINT32 Group1:8 ; ///< - UINT32 Group2:8 ; ///< - UINT32 Group3:8 ; ///< - } Field; ///< - UINT32 Value; ///< -} GMMx279C_STRUCT; - -// **** GMMx27A0 Register Definition **** -// Address -#define GMMx27A0_ADDRESS 0x27a0 - -// Type -#define GMMx27A0_TYPE TYPE_GMM -// Field Data -#define GMMx27A0_Group0_OFFSET 0 -#define GMMx27A0_Group0_WIDTH 8 -#define GMMx27A0_Group0_MASK 0xff -#define GMMx27A0_Group1_OFFSET 8 -#define GMMx27A0_Group1_WIDTH 8 -#define GMMx27A0_Group1_MASK 0xff00 -#define GMMx27A0_Group2_OFFSET 16 -#define GMMx27A0_Group2_WIDTH 8 -#define GMMx27A0_Group2_MASK 0xff0000 -#define GMMx27A0_Group3_OFFSET 24 -#define GMMx27A0_Group3_WIDTH 8 -#define GMMx27A0_Group3_MASK 0xff000000 - -/// GMMx27A0 -typedef union { - struct { ///< - UINT32 Group0:8 ; ///< - UINT32 Group1:8 ; ///< - UINT32 Group2:8 ; ///< - UINT32 Group3:8 ; ///< - } Field; ///< - UINT32 Value; ///< -} GMMx27A0_STRUCT; - -// **** GMMx27CC Register Definition **** -// Address -#define GMMx27CC_ADDRESS 0x27cc - -// Type -#define GMMx27CC_TYPE TYPE_GMM -// Field Data -#define GMMx27CC_StreakLimit_OFFSET 0 -#define GMMx27CC_StreakLimit_WIDTH 8 -#define GMMx27CC_StreakLimit_MASK 0xff -#define GMMx27CC_StreakLimitUber_OFFSET 8 -#define GMMx27CC_StreakLimitUber_WIDTH 8 -#define GMMx27CC_StreakLimitUber_MASK 0xff00 -#define GMMx27CC_StreakBreak_OFFSET 16 -#define GMMx27CC_StreakBreak_WIDTH 1 -#define GMMx27CC_StreakBreak_MASK 0x10000 -#define GMMx27CC_StreakUber_OFFSET 17 -#define GMMx27CC_StreakUber_WIDTH 1 -#define GMMx27CC_StreakUber_MASK 0x20000 -#define GMMx27CC_Reserved_31_18_OFFSET 18 -#define GMMx27CC_Reserved_31_18_WIDTH 14 -#define GMMx27CC_Reserved_31_18_MASK 0xfffc0000 - -/// GMMx27CC -typedef union { - struct { ///< - UINT32 StreakLimit:8 ; ///< - UINT32 StreakLimitUber:8 ; ///< - UINT32 StreakBreak:1 ; ///< - UINT32 StreakUber:1 ; ///< - UINT32 Reserved_31_18:14; ///< - } Field; ///< - UINT32 Value; ///< -} GMMx27CC_STRUCT; - -// **** GMMx27D0 Register Definition **** -// Address -#define GMMx27D0_ADDRESS 0x27d0 - -// Type -#define GMMx27D0_TYPE TYPE_GMM -// Field Data -#define GMMx27D0_StreakLimit_OFFSET 0 -#define GMMx27D0_StreakLimit_WIDTH 8 -#define GMMx27D0_StreakLimit_MASK 0xff -#define GMMx27D0_StreakLimitUber_OFFSET 8 -#define GMMx27D0_StreakLimitUber_WIDTH 8 -#define GMMx27D0_StreakLimitUber_MASK 0xff00 -#define GMMx27D0_StreakBreak_OFFSET 16 -#define GMMx27D0_StreakBreak_WIDTH 1 -#define GMMx27D0_StreakBreak_MASK 0x10000 -#define GMMx27D0_StreakUber_OFFSET 17 -#define GMMx27D0_StreakUber_WIDTH 1 -#define GMMx27D0_StreakUber_MASK 0x20000 -#define GMMx27D0_Reserved_31_18_OFFSET 18 -#define GMMx27D0_Reserved_31_18_WIDTH 14 -#define GMMx27D0_Reserved_31_18_MASK 0xfffc0000 - -/// GMMx27D0 -typedef union { - struct { ///< - UINT32 StreakLimit:8 ; ///< - UINT32 StreakLimitUber:8 ; ///< - UINT32 StreakBreak:1 ; ///< - UINT32 StreakUber:1 ; ///< - UINT32 Reserved_31_18:14; ///< - } Field; ///< - UINT32 Value; ///< -} GMMx27D0_STRUCT; - -// **** GMMx27DC Register Definition **** -// Address -#define GMMx27DC_ADDRESS 0x27dc - -// Type -#define GMMx27DC_TYPE TYPE_GMM -// Field Data -#define GMMx27DC_Lcl_OFFSET 0 -#define GMMx27DC_Lcl_WIDTH 8 -#define GMMx27DC_Lcl_MASK 0xff -#define GMMx27DC_Hub_OFFSET 8 -#define GMMx27DC_Hub_WIDTH 8 -#define GMMx27DC_Hub_MASK 0xff00 -#define GMMx27DC_Disp_OFFSET 16 -#define GMMx27DC_Disp_WIDTH 8 -#define GMMx27DC_Disp_MASK 0xff0000 -#define GMMx27DC_Reserved_31_24_OFFSET 24 -#define GMMx27DC_Reserved_31_24_WIDTH 8 -#define GMMx27DC_Reserved_31_24_MASK 0xff000000 - -/// GMMx27DC -typedef union { - struct { ///< - UINT32 Lcl:8 ; ///< - UINT32 Hub:8 ; ///< - UINT32 Disp:8 ; ///< - UINT32 Reserved_31_24:8 ; ///< - } Field; ///< - UINT32 Value; ///< -} GMMx27DC_STRUCT; - -// **** GMMx27E0 Register Definition **** -// Address -#define GMMx27E0_ADDRESS 0x27e0 - -// Type -#define GMMx27E0_TYPE TYPE_GMM -// Field Data -#define GMMx27E0_Lcl_OFFSET 0 -#define GMMx27E0_Lcl_WIDTH 8 -#define GMMx27E0_Lcl_MASK 0xff -#define GMMx27E0_Hub_OFFSET 8 -#define GMMx27E0_Hub_WIDTH 8 -#define GMMx27E0_Hub_MASK 0xff00 -#define GMMx27E0_Reserved_31_16_OFFSET 16 -#define GMMx27E0_Reserved_31_16_WIDTH 16 -#define GMMx27E0_Reserved_31_16_MASK 0xffff0000 - -/// GMMx27E0 -typedef union { - struct { ///< - UINT32 Lcl:8 ; ///< - UINT32 Hub:8 ; ///< - UINT32 Reserved_31_16:16; ///< - } Field; ///< - UINT32 Value; ///< -} GMMx27E0_STRUCT; - -// **** GMMx2814 Register Definition **** -// Address -#define GMMx2814_ADDRESS 0x2814 - -// Type -#define GMMx2814_TYPE TYPE_GMM -// Field Data -#define GMMx2814_WriteClks_OFFSET 0 -#define GMMx2814_WriteClks_WIDTH 9 -#define GMMx2814_WriteClks_MASK 0x1ff -#define GMMx2814_UvdHarshPriority_OFFSET 9 -#define GMMx2814_UvdHarshPriority_WIDTH 1 -#define GMMx2814_UvdHarshPriority_MASK 0x200 -#define GMMx2814_Reserved_31_10_OFFSET 10 -#define GMMx2814_Reserved_31_10_WIDTH 22 -#define GMMx2814_Reserved_31_10_MASK 0xfffffc00 - -/// GMMx2814 -typedef union { - struct { ///< - UINT32 WriteClks:9 ; ///< - UINT32 UvdHarshPriority:1 ; ///< - UINT32 Reserved_31_10:22; ///< - } Field; ///< - UINT32 Value; ///< -} GMMx2814_STRUCT; - -// **** GMMx281C Register Definition **** -// Address -#define GMMx281C_ADDRESS 0x281c - -// Type -#define GMMx281C_TYPE TYPE_GMM -// Field Data -#define GMMx281C_CSEnable_OFFSET 0 -#define GMMx281C_CSEnable_WIDTH 1 -#define GMMx281C_CSEnable_MASK 0x1 -#define GMMx281C_Reserved_4_1_OFFSET 1 -#define GMMx281C_Reserved_4_1_WIDTH 4 -#define GMMx281C_Reserved_4_1_MASK 0x1e -#define GMMx281C_BaseAddr_21_13__OFFSET 5 -#define GMMx281C_BaseAddr_21_13__WIDTH 9 -#define GMMx281C_BaseAddr_21_13__MASK 0x3fe0 -#define GMMx281C_Reserved_18_14_OFFSET 14 -#define GMMx281C_Reserved_18_14_WIDTH 5 -#define GMMx281C_Reserved_18_14_MASK 0x7c000 -#define GMMx281C_BaseAddr_36_27__OFFSET 19 -#define GMMx281C_BaseAddr_36_27__WIDTH 10 -#define GMMx281C_BaseAddr_36_27__MASK 0x1ff80000 -#define GMMx281C_Reserved_31_29_OFFSET 29 -#define GMMx281C_Reserved_31_29_WIDTH 3 -#define GMMx281C_Reserved_31_29_MASK 0xe0000000 - -/// GMMx281C -typedef union { - struct { ///< - UINT32 CSEnable:1 ; ///< - UINT32 Reserved_4_1:4 ; ///< - UINT32 BaseAddr_21_13_:9 ; ///< - UINT32 Reserved_18_14:5 ; ///< - UINT32 BaseAddr_36_27_:10; ///< - UINT32 Reserved_31_29:3 ; ///< - } Field; ///< - UINT32 Value; ///< -} GMMx281C_STRUCT; - -// **** GMMx2820 Register Definition **** -// Address -#define GMMx2820_ADDRESS 0x2820 - -// Type -#define GMMx2820_TYPE TYPE_GMM -// Field Data -#define GMMx2820_CSEnable_OFFSET 0 -#define GMMx2820_CSEnable_WIDTH 1 -#define GMMx2820_CSEnable_MASK 0x1 -#define GMMx2820_Reserved_4_1_OFFSET 1 -#define GMMx2820_Reserved_4_1_WIDTH 4 -#define GMMx2820_Reserved_4_1_MASK 0x1e -#define GMMx2820_BaseAddr_21_13__OFFSET 5 -#define GMMx2820_BaseAddr_21_13__WIDTH 9 -#define GMMx2820_BaseAddr_21_13__MASK 0x3fe0 -#define GMMx2820_Reserved_18_14_OFFSET 14 -#define GMMx2820_Reserved_18_14_WIDTH 5 -#define GMMx2820_Reserved_18_14_MASK 0x7c000 -#define GMMx2820_BaseAddr_36_27__OFFSET 19 -#define GMMx2820_BaseAddr_36_27__WIDTH 10 -#define GMMx2820_BaseAddr_36_27__MASK 0x1ff80000 -#define GMMx2820_Reserved_31_29_OFFSET 29 -#define GMMx2820_Reserved_31_29_WIDTH 3 -#define GMMx2820_Reserved_31_29_MASK 0xe0000000 - -/// GMMx2820 -typedef union { - struct { ///< - UINT32 CSEnable:1 ; ///< - UINT32 Reserved_4_1:4 ; ///< - UINT32 BaseAddr_21_13_:9 ; ///< - UINT32 Reserved_18_14:5 ; ///< - UINT32 BaseAddr_36_27_:10; ///< - UINT32 Reserved_31_29:3 ; ///< - } Field; ///< - UINT32 Value; ///< -} GMMx2820_STRUCT; - -// **** GMMx2824 Register Definition **** -// Address -#define GMMx2824_ADDRESS 0x2824 - -// Type -#define GMMx2824_TYPE TYPE_GMM -// Field Data -#define GMMx2824_CSEnable_OFFSET 0 -#define GMMx2824_CSEnable_WIDTH 1 -#define GMMx2824_CSEnable_MASK 0x1 -#define GMMx2824_Reserved_4_1_OFFSET 1 -#define GMMx2824_Reserved_4_1_WIDTH 4 -#define GMMx2824_Reserved_4_1_MASK 0x1e -#define GMMx2824_BaseAddr_21_13__OFFSET 5 -#define GMMx2824_BaseAddr_21_13__WIDTH 9 -#define GMMx2824_BaseAddr_21_13__MASK 0x3fe0 -#define GMMx2824_Reserved_18_14_OFFSET 14 -#define GMMx2824_Reserved_18_14_WIDTH 5 -#define GMMx2824_Reserved_18_14_MASK 0x7c000 -#define GMMx2824_BaseAddr_36_27__OFFSET 19 -#define GMMx2824_BaseAddr_36_27__WIDTH 10 -#define GMMx2824_BaseAddr_36_27__MASK 0x1ff80000 -#define GMMx2824_Reserved_31_29_OFFSET 29 -#define GMMx2824_Reserved_31_29_WIDTH 3 -#define GMMx2824_Reserved_31_29_MASK 0xe0000000 - -/// GMMx2824 -typedef union { - struct { ///< - UINT32 CSEnable:1 ; ///< - UINT32 Reserved_4_1:4 ; ///< - UINT32 BaseAddr_21_13_:9 ; ///< - UINT32 Reserved_18_14:5 ; ///< - UINT32 BaseAddr_36_27_:10; ///< - UINT32 Reserved_31_29:3 ; ///< - } Field; ///< - UINT32 Value; ///< -} GMMx2824_STRUCT; - -// **** GMMx2828 Register Definition **** -// Address -#define GMMx2828_ADDRESS 0x2828 - -// Type -#define GMMx2828_TYPE TYPE_GMM -// Field Data -#define GMMx2828_CSEnable_OFFSET 0 -#define GMMx2828_CSEnable_WIDTH 1 -#define GMMx2828_CSEnable_MASK 0x1 -#define GMMx2828_Reserved_4_1_OFFSET 1 -#define GMMx2828_Reserved_4_1_WIDTH 4 -#define GMMx2828_Reserved_4_1_MASK 0x1e -#define GMMx2828_BaseAddr_21_13__OFFSET 5 -#define GMMx2828_BaseAddr_21_13__WIDTH 9 -#define GMMx2828_BaseAddr_21_13__MASK 0x3fe0 -#define GMMx2828_Reserved_18_14_OFFSET 14 -#define GMMx2828_Reserved_18_14_WIDTH 5 -#define GMMx2828_Reserved_18_14_MASK 0x7c000 -#define GMMx2828_BaseAddr_36_27__OFFSET 19 -#define GMMx2828_BaseAddr_36_27__WIDTH 10 -#define GMMx2828_BaseAddr_36_27__MASK 0x1ff80000 -#define GMMx2828_Reserved_31_29_OFFSET 29 -#define GMMx2828_Reserved_31_29_WIDTH 3 -#define GMMx2828_Reserved_31_29_MASK 0xe0000000 - -/// GMMx2828 -typedef union { - struct { ///< - UINT32 CSEnable:1 ; ///< - UINT32 Reserved_4_1:4 ; ///< - UINT32 BaseAddr_21_13_:9 ; ///< - UINT32 Reserved_18_14:5 ; ///< - UINT32 BaseAddr_36_27_:10; ///< - UINT32 Reserved_31_29:3 ; ///< - } Field; ///< - UINT32 Value; ///< -} GMMx2828_STRUCT; - -// **** GMMx282C Register Definition **** -// Address -#define GMMx282C_ADDRESS 0x282c - -// Type -#define GMMx282C_TYPE TYPE_GMM -// Field Data -#define GMMx282C_CSEnable_OFFSET 0 -#define GMMx282C_CSEnable_WIDTH 1 -#define GMMx282C_CSEnable_MASK 0x1 -#define GMMx282C_Reserved_4_1_OFFSET 1 -#define GMMx282C_Reserved_4_1_WIDTH 4 -#define GMMx282C_Reserved_4_1_MASK 0x1e -#define GMMx282C_BaseAddr_21_13__OFFSET 5 -#define GMMx282C_BaseAddr_21_13__WIDTH 9 -#define GMMx282C_BaseAddr_21_13__MASK 0x3fe0 -#define GMMx282C_Reserved_18_14_OFFSET 14 -#define GMMx282C_Reserved_18_14_WIDTH 5 -#define GMMx282C_Reserved_18_14_MASK 0x7c000 -#define GMMx282C_BaseAddr_36_27__OFFSET 19 -#define GMMx282C_BaseAddr_36_27__WIDTH 10 -#define GMMx282C_BaseAddr_36_27__MASK 0x1ff80000 -#define GMMx282C_Reserved_31_29_OFFSET 29 -#define GMMx282C_Reserved_31_29_WIDTH 3 -#define GMMx282C_Reserved_31_29_MASK 0xe0000000 - -/// GMMx282C -typedef union { - struct { ///< - UINT32 CSEnable:1 ; ///< - UINT32 Reserved_4_1:4 ; ///< - UINT32 BaseAddr_21_13_:9 ; ///< - UINT32 Reserved_18_14:5 ; ///< - UINT32 BaseAddr_36_27_:10; ///< - UINT32 Reserved_31_29:3 ; ///< - } Field; ///< - UINT32 Value; ///< -} GMMx282C_STRUCT; - -// **** GMMx2830 Register Definition **** -// Address -#define GMMx2830_ADDRESS 0x2830 - -// Type -#define GMMx2830_TYPE TYPE_GMM -// Field Data -#define GMMx2830_CSEnable_OFFSET 0 -#define GMMx2830_CSEnable_WIDTH 1 -#define GMMx2830_CSEnable_MASK 0x1 -#define GMMx2830_Reserved_4_1_OFFSET 1 -#define GMMx2830_Reserved_4_1_WIDTH 4 -#define GMMx2830_Reserved_4_1_MASK 0x1e -#define GMMx2830_BaseAddr_21_13__OFFSET 5 -#define GMMx2830_BaseAddr_21_13__WIDTH 9 -#define GMMx2830_BaseAddr_21_13__MASK 0x3fe0 -#define GMMx2830_Reserved_18_14_OFFSET 14 -#define GMMx2830_Reserved_18_14_WIDTH 5 -#define GMMx2830_Reserved_18_14_MASK 0x7c000 -#define GMMx2830_BaseAddr_36_27__OFFSET 19 -#define GMMx2830_BaseAddr_36_27__WIDTH 10 -#define GMMx2830_BaseAddr_36_27__MASK 0x1ff80000 -#define GMMx2830_Reserved_31_29_OFFSET 29 -#define GMMx2830_Reserved_31_29_WIDTH 3 -#define GMMx2830_Reserved_31_29_MASK 0xe0000000 - -/// GMMx2830 -typedef union { - struct { ///< - UINT32 CSEnable:1 ; ///< - UINT32 Reserved_4_1:4 ; ///< - UINT32 BaseAddr_21_13_:9 ; ///< - UINT32 Reserved_18_14:5 ; ///< - UINT32 BaseAddr_36_27_:10; ///< - UINT32 Reserved_31_29:3 ; ///< - } Field; ///< - UINT32 Value; ///< -} GMMx2830_STRUCT; - -// **** GMMx2834 Register Definition **** -// Address -#define GMMx2834_ADDRESS 0x2834 - -// Type -#define GMMx2834_TYPE TYPE_GMM -// Field Data -#define GMMx2834_CSEnable_OFFSET 0 -#define GMMx2834_CSEnable_WIDTH 1 -#define GMMx2834_CSEnable_MASK 0x1 -#define GMMx2834_Reserved_4_1_OFFSET 1 -#define GMMx2834_Reserved_4_1_WIDTH 4 -#define GMMx2834_Reserved_4_1_MASK 0x1e -#define GMMx2834_BaseAddr_21_13__OFFSET 5 -#define GMMx2834_BaseAddr_21_13__WIDTH 9 -#define GMMx2834_BaseAddr_21_13__MASK 0x3fe0 -#define GMMx2834_Reserved_18_14_OFFSET 14 -#define GMMx2834_Reserved_18_14_WIDTH 5 -#define GMMx2834_Reserved_18_14_MASK 0x7c000 -#define GMMx2834_BaseAddr_36_27__OFFSET 19 -#define GMMx2834_BaseAddr_36_27__WIDTH 10 -#define GMMx2834_BaseAddr_36_27__MASK 0x1ff80000 -#define GMMx2834_Reserved_31_29_OFFSET 29 -#define GMMx2834_Reserved_31_29_WIDTH 3 -#define GMMx2834_Reserved_31_29_MASK 0xe0000000 - -/// GMMx2834 -typedef union { - struct { ///< - UINT32 CSEnable:1 ; ///< - UINT32 Reserved_4_1:4 ; ///< - UINT32 BaseAddr_21_13_:9 ; ///< - UINT32 Reserved_18_14:5 ; ///< - UINT32 BaseAddr_36_27_:10; ///< - UINT32 Reserved_31_29:3 ; ///< - } Field; ///< - UINT32 Value; ///< -} GMMx2834_STRUCT; - -// **** GMMx2838 Register Definition **** -// Address -#define GMMx2838_ADDRESS 0x2838 - -// Type -#define GMMx2838_TYPE TYPE_GMM -// Field Data -#define GMMx2838_CSEnable_OFFSET 0 -#define GMMx2838_CSEnable_WIDTH 1 -#define GMMx2838_CSEnable_MASK 0x1 -#define GMMx2838_Reserved_4_1_OFFSET 1 -#define GMMx2838_Reserved_4_1_WIDTH 4 -#define GMMx2838_Reserved_4_1_MASK 0x1e -#define GMMx2838_BaseAddr_21_13__OFFSET 5 -#define GMMx2838_BaseAddr_21_13__WIDTH 9 -#define GMMx2838_BaseAddr_21_13__MASK 0x3fe0 -#define GMMx2838_Reserved_18_14_OFFSET 14 -#define GMMx2838_Reserved_18_14_WIDTH 5 -#define GMMx2838_Reserved_18_14_MASK 0x7c000 -#define GMMx2838_BaseAddr_36_27__OFFSET 19 -#define GMMx2838_BaseAddr_36_27__WIDTH 10 -#define GMMx2838_BaseAddr_36_27__MASK 0x1ff80000 -#define GMMx2838_Reserved_31_29_OFFSET 29 -#define GMMx2838_Reserved_31_29_WIDTH 3 -#define GMMx2838_Reserved_31_29_MASK 0xe0000000 - -/// GMMx2838 -typedef union { - struct { ///< - UINT32 CSEnable:1 ; ///< - UINT32 Reserved_4_1:4 ; ///< - UINT32 BaseAddr_21_13_:9 ; ///< - UINT32 Reserved_18_14:5 ; ///< - UINT32 BaseAddr_36_27_:10; ///< - UINT32 Reserved_31_29:3 ; ///< - } Field; ///< - UINT32 Value; ///< -} GMMx2838_STRUCT; - -// **** GMMx283C Register Definition **** -// Address -#define GMMx283C_ADDRESS 0x283c - -// Type -#define GMMx283C_TYPE TYPE_GMM -// Field Data -#define GMMx283C_Reserved_4_0_OFFSET 0 -#define GMMx283C_Reserved_4_0_WIDTH 5 -#define GMMx283C_Reserved_4_0_MASK 0x1f -#define GMMx283C_AddrMask_21_13__OFFSET 5 -#define GMMx283C_AddrMask_21_13__WIDTH 9 -#define GMMx283C_AddrMask_21_13__MASK 0x3fe0 -#define GMMx283C_Reserved_18_14_OFFSET 14 -#define GMMx283C_Reserved_18_14_WIDTH 5 -#define GMMx283C_Reserved_18_14_MASK 0x7c000 -#define GMMx283C_AddrMask_36_27__OFFSET 19 -#define GMMx283C_AddrMask_36_27__WIDTH 10 -#define GMMx283C_AddrMask_36_27__MASK 0x1ff80000 -#define GMMx283C_Reserved_31_29_OFFSET 29 -#define GMMx283C_Reserved_31_29_WIDTH 3 -#define GMMx283C_Reserved_31_29_MASK 0xe0000000 - -/// GMMx283C -typedef union { - struct { ///< - UINT32 Reserved_4_0:5 ; ///< - UINT32 AddrMask_21_13_:9 ; ///< - UINT32 Reserved_18_14:5 ; ///< - UINT32 AddrMask_36_27_:10; ///< - UINT32 Reserved_31_29:3 ; ///< - } Field; ///< - UINT32 Value; ///< -} GMMx283C_STRUCT; - -// **** GMMx2840 Register Definition **** -// Address -#define GMMx2840_ADDRESS 0x2840 - -// Type -#define GMMx2840_TYPE TYPE_GMM -// Field Data -#define GMMx2840_Reserved_4_0_OFFSET 0 -#define GMMx2840_Reserved_4_0_WIDTH 5 -#define GMMx2840_Reserved_4_0_MASK 0x1f -#define GMMx2840_AddrMask_21_13__OFFSET 5 -#define GMMx2840_AddrMask_21_13__WIDTH 9 -#define GMMx2840_AddrMask_21_13__MASK 0x3fe0 -#define GMMx2840_Reserved_18_14_OFFSET 14 -#define GMMx2840_Reserved_18_14_WIDTH 5 -#define GMMx2840_Reserved_18_14_MASK 0x7c000 -#define GMMx2840_AddrMask_36_27__OFFSET 19 -#define GMMx2840_AddrMask_36_27__WIDTH 10 -#define GMMx2840_AddrMask_36_27__MASK 0x1ff80000 -#define GMMx2840_Reserved_31_29_OFFSET 29 -#define GMMx2840_Reserved_31_29_WIDTH 3 -#define GMMx2840_Reserved_31_29_MASK 0xe0000000 - -/// GMMx2840 -typedef union { - struct { ///< - UINT32 Reserved_4_0:5 ; ///< - UINT32 AddrMask_21_13_:9 ; ///< - UINT32 Reserved_18_14:5 ; ///< - UINT32 AddrMask_36_27_:10; ///< - UINT32 Reserved_31_29:3 ; ///< - } Field; ///< - UINT32 Value; ///< -} GMMx2840_STRUCT; - -// **** GMMx2844 Register Definition **** -// Address -#define GMMx2844_ADDRESS 0x2844 - -// Type -#define GMMx2844_TYPE TYPE_GMM -// Field Data -#define GMMx2844_Reserved_4_0_OFFSET 0 -#define GMMx2844_Reserved_4_0_WIDTH 5 -#define GMMx2844_Reserved_4_0_MASK 0x1f -#define GMMx2844_AddrMask_21_13__OFFSET 5 -#define GMMx2844_AddrMask_21_13__WIDTH 9 -#define GMMx2844_AddrMask_21_13__MASK 0x3fe0 -#define GMMx2844_Reserved_18_14_OFFSET 14 -#define GMMx2844_Reserved_18_14_WIDTH 5 -#define GMMx2844_Reserved_18_14_MASK 0x7c000 -#define GMMx2844_AddrMask_36_27__OFFSET 19 -#define GMMx2844_AddrMask_36_27__WIDTH 10 -#define GMMx2844_AddrMask_36_27__MASK 0x1ff80000 -#define GMMx2844_Reserved_31_29_OFFSET 29 -#define GMMx2844_Reserved_31_29_WIDTH 3 -#define GMMx2844_Reserved_31_29_MASK 0xe0000000 - -/// GMMx2844 -typedef union { - struct { ///< - UINT32 Reserved_4_0:5 ; ///< - UINT32 AddrMask_21_13_:9 ; ///< - UINT32 Reserved_18_14:5 ; ///< - UINT32 AddrMask_36_27_:10; ///< - UINT32 Reserved_31_29:3 ; ///< - } Field; ///< - UINT32 Value; ///< -} GMMx2844_STRUCT; - -// **** GMMx2848 Register Definition **** -// Address -#define GMMx2848_ADDRESS 0x2848 - -// Type -#define GMMx2848_TYPE TYPE_GMM -// Field Data -#define GMMx2848_Reserved_4_0_OFFSET 0 -#define GMMx2848_Reserved_4_0_WIDTH 5 -#define GMMx2848_Reserved_4_0_MASK 0x1f -#define GMMx2848_AddrMask_21_13__OFFSET 5 -#define GMMx2848_AddrMask_21_13__WIDTH 9 -#define GMMx2848_AddrMask_21_13__MASK 0x3fe0 -#define GMMx2848_Reserved_18_14_OFFSET 14 -#define GMMx2848_Reserved_18_14_WIDTH 5 -#define GMMx2848_Reserved_18_14_MASK 0x7c000 -#define GMMx2848_AddrMask_36_27__OFFSET 19 -#define GMMx2848_AddrMask_36_27__WIDTH 10 -#define GMMx2848_AddrMask_36_27__MASK 0x1ff80000 -#define GMMx2848_Reserved_31_29_OFFSET 29 -#define GMMx2848_Reserved_31_29_WIDTH 3 -#define GMMx2848_Reserved_31_29_MASK 0xe0000000 - -/// GMMx2848 -typedef union { - struct { ///< - UINT32 Reserved_4_0:5 ; ///< - UINT32 AddrMask_21_13_:9 ; ///< - UINT32 Reserved_18_14:5 ; ///< - UINT32 AddrMask_36_27_:10; ///< - UINT32 Reserved_31_29:3 ; ///< - } Field; ///< - UINT32 Value; ///< -} GMMx2848_STRUCT; - -// **** GMMx284C Register Definition **** -// Address -#define GMMx284C_ADDRESS 0x284c - -// Type -#define GMMx284C_TYPE TYPE_GMM -// Field Data -#define GMMx284C_Dimm0AddrMap_OFFSET 0 -#define GMMx284C_Dimm0AddrMap_WIDTH 4 -#define GMMx284C_Dimm0AddrMap_MASK 0xf -#define GMMx284C_Dimm1AddrMap_OFFSET 4 -#define GMMx284C_Dimm1AddrMap_WIDTH 4 -#define GMMx284C_Dimm1AddrMap_MASK 0xf0 -#define GMMx284C_Reserved_15_8_OFFSET 8 -#define GMMx284C_Reserved_15_8_WIDTH 8 -#define GMMx284C_Reserved_15_8_MASK 0xff00 -#define GMMx284C_BankSwizzleMode_OFFSET 16 -#define GMMx284C_BankSwizzleMode_WIDTH 1 -#define GMMx284C_BankSwizzleMode_MASK 0x10000 -#define GMMx284C_Ddr3Mode_OFFSET 17 -#define GMMx284C_Ddr3Mode_WIDTH 1 -#define GMMx284C_Ddr3Mode_MASK 0x20000 -#define GMMx284C_BurstLength32_OFFSET 18 -#define GMMx284C_BurstLength32_WIDTH 1 -#define GMMx284C_BurstLength32_MASK 0x40000 -#define GMMx284C_BankSwap_OFFSET 19 -#define GMMx284C_BankSwap_WIDTH 1 -#define GMMx284C_BankSwap_MASK 0x80000 -#define GMMx284C_Reserved_31_20_OFFSET 20 -#define GMMx284C_Reserved_31_20_WIDTH 12 -#define GMMx284C_Reserved_31_20_MASK 0xfff00000 - -/// GMMx284C -typedef union { - struct { ///< - UINT32 Dimm0AddrMap:4 ; ///< - UINT32 Dimm1AddrMap:4 ; ///< - UINT32 Reserved_15_8:8 ; ///< - UINT32 BankSwizzleMode:1 ; ///< - UINT32 Ddr3Mode:1 ; ///< - UINT32 BurstLength32:1 ; ///< - UINT32 BankSwap:1 ; ///< - UINT32 Reserved_31_20:12; ///< - } Field; ///< - UINT32 Value; ///< -} GMMx284C_STRUCT; - -// **** GMMx2850 Register Definition **** -// Address -#define GMMx2850_ADDRESS 0x2850 - -// Type -#define GMMx2850_TYPE TYPE_GMM -// Field Data -#define GMMx2850_Dimm0AddrMap_OFFSET 0 -#define GMMx2850_Dimm0AddrMap_WIDTH 4 -#define GMMx2850_Dimm0AddrMap_MASK 0xf -#define GMMx2850_Dimm1AddrMap_OFFSET 4 -#define GMMx2850_Dimm1AddrMap_WIDTH 4 -#define GMMx2850_Dimm1AddrMap_MASK 0xf0 -#define GMMx2850_Reserved_15_8_OFFSET 8 -#define GMMx2850_Reserved_15_8_WIDTH 8 -#define GMMx2850_Reserved_15_8_MASK 0xff00 -#define GMMx2850_BankSwizzleMode_OFFSET 16 -#define GMMx2850_BankSwizzleMode_WIDTH 1 -#define GMMx2850_BankSwizzleMode_MASK 0x10000 -#define GMMx2850_Ddr3Mode_OFFSET 17 -#define GMMx2850_Ddr3Mode_WIDTH 1 -#define GMMx2850_Ddr3Mode_MASK 0x20000 -#define GMMx2850_BurstLength32_OFFSET 18 -#define GMMx2850_BurstLength32_WIDTH 1 -#define GMMx2850_BurstLength32_MASK 0x40000 -#define GMMx2850_BankSwap_OFFSET 19 -#define GMMx2850_BankSwap_WIDTH 1 -#define GMMx2850_BankSwap_MASK 0x80000 -#define GMMx2850_Reserved_31_20_OFFSET 20 -#define GMMx2850_Reserved_31_20_WIDTH 12 -#define GMMx2850_Reserved_31_20_MASK 0xfff00000 - -/// GMMx2850 -typedef union { - struct { ///< - UINT32 Dimm0AddrMap:4 ; ///< - UINT32 Dimm1AddrMap:4 ; ///< - UINT32 Reserved_15_8:8 ; ///< - UINT32 BankSwizzleMode:1 ; ///< - UINT32 Ddr3Mode:1 ; ///< - UINT32 BurstLength32:1 ; ///< - UINT32 BankSwap:1 ; ///< - UINT32 Reserved_31_20:12; ///< - } Field; ///< - UINT32 Value; ///< -} GMMx2850_STRUCT; - -// **** GMMx2854 Register Definition **** -// Address -#define GMMx2854_ADDRESS 0x2854 - -// Type -#define GMMx2854_TYPE TYPE_GMM -// Field Data -#define GMMx2854_DctSelHiRngEn_OFFSET 0 -#define GMMx2854_DctSelHiRngEn_WIDTH 1 -#define GMMx2854_DctSelHiRngEn_MASK 0x1 -#define GMMx2854_DctSelHi_OFFSET 1 -#define GMMx2854_DctSelHi_WIDTH 1 -#define GMMx2854_DctSelHi_MASK 0x2 -#define GMMx2854_DctSelIntLvEn_OFFSET 2 -#define GMMx2854_DctSelIntLvEn_WIDTH 1 -#define GMMx2854_DctSelIntLvEn_MASK 0x4 -#define GMMx2854_Reserved_5_3_OFFSET 3 -#define GMMx2854_Reserved_5_3_WIDTH 3 -#define GMMx2854_Reserved_5_3_MASK 0x38 -#define GMMx2854_DctSelIntLvAddr_1_0__OFFSET 6 -#define GMMx2854_DctSelIntLvAddr_1_0__WIDTH 2 -#define GMMx2854_DctSelIntLvAddr_1_0__MASK 0xc0 -#define GMMx2854_Reserved_10_8_OFFSET 8 -#define GMMx2854_Reserved_10_8_WIDTH 3 -#define GMMx2854_Reserved_10_8_MASK 0x700 -#define GMMx2854_DctSelBaseAddr_39_27__OFFSET 11 -#define GMMx2854_DctSelBaseAddr_39_27__WIDTH 13 -#define GMMx2854_DctSelBaseAddr_39_27__MASK 0xfff800 -#define GMMx2854_Reserved_31_24_OFFSET 24 -#define GMMx2854_Reserved_31_24_WIDTH 8 -#define GMMx2854_Reserved_31_24_MASK 0xff000000 - -/// GMMx2854 -typedef union { - struct { ///< - UINT32 DctSelHiRngEn:1 ; ///< - UINT32 DctSelHi:1 ; ///< - UINT32 DctSelIntLvEn:1 ; ///< - UINT32 Reserved_5_3:3 ; ///< - UINT32 DctSelIntLvAddr_1_0_:2 ; ///< - UINT32 Reserved_10_8:3 ; ///< - UINT32 DctSelBaseAddr_39_27_:13; ///< - UINT32 Reserved_31_24:8 ; ///< - } Field; ///< - UINT32 Value; ///< -} GMMx2854_STRUCT; - -// **** GMMx2858 Register Definition **** -// Address -#define GMMx2858_ADDRESS 0x2858 - -// Type -#define GMMx2858_TYPE TYPE_GMM -// Field Data -#define GMMx2858_Reserved_8_0_OFFSET 0 -#define GMMx2858_Reserved_8_0_WIDTH 9 -#define GMMx2858_Reserved_8_0_MASK 0x1ff -#define GMMx2858_DctSelIntLvAddr_2__OFFSET 9 -#define GMMx2858_DctSelIntLvAddr_2__WIDTH 1 -#define GMMx2858_DctSelIntLvAddr_2__MASK 0x200 -#define GMMx2858_DctSelBaseOffset_39_26__OFFSET 10 -#define GMMx2858_DctSelBaseOffset_39_26__WIDTH 14 -#define GMMx2858_DctSelBaseOffset_39_26__MASK 0xfffc00 -#define GMMx2858_Reserved_31_24_OFFSET 24 -#define GMMx2858_Reserved_31_24_WIDTH 8 -#define GMMx2858_Reserved_31_24_MASK 0xff000000 - -/// GMMx2858 -typedef union { - struct { ///< - UINT32 Reserved_8_0:9 ; ///< - UINT32 DctSelIntLvAddr_2_:1 ; ///< - UINT32 DctSelBaseOffset_39_26_:14; ///< - UINT32 Reserved_31_24:8 ; ///< - } Field; ///< - UINT32 Value; ///< -} GMMx2858_STRUCT; - -// **** GMMx285C Register Definition **** -// Address -#define GMMx285C_ADDRESS 0x285c - -// Type -#define GMMx285C_TYPE TYPE_GMM -// Field Data -#define GMMx285C_DramHoleValid_OFFSET 0 -#define GMMx285C_DramHoleValid_WIDTH 1 -#define GMMx285C_DramHoleValid_MASK 0x1 -#define GMMx285C_Reserved_6_1_OFFSET 1 -#define GMMx285C_Reserved_6_1_WIDTH 6 -#define GMMx285C_Reserved_6_1_MASK 0x7e -#define GMMx285C_DramHoleOffset_31_23__OFFSET 7 -#define GMMx285C_DramHoleOffset_31_23__WIDTH 9 -#define GMMx285C_DramHoleOffset_31_23__MASK 0xff80 -#define GMMx285C_Reserved_23_16_OFFSET 16 -#define GMMx285C_Reserved_23_16_WIDTH 8 -#define GMMx285C_Reserved_23_16_MASK 0xff0000 -#define GMMx285C_DramHoleBase_31_24__OFFSET 24 -#define GMMx285C_DramHoleBase_31_24__WIDTH 8 -#define GMMx285C_DramHoleBase_31_24__MASK 0xff000000 - -/// GMMx285C -typedef union { - struct { ///< - UINT32 DramHoleValid:1 ; ///< - UINT32 Reserved_6_1:6 ; ///< - UINT32 DramHoleOffset_31_23_:9 ; ///< - UINT32 Reserved_23_16:8 ; ///< - UINT32 DramHoleBase_31_24_:8 ; ///< - } Field; ///< - UINT32 Value; ///< -} GMMx285C_STRUCT; - -// **** GMMx2860 Register Definition **** -// Address -#define GMMx2860_ADDRESS 0x2860 - -// Type -#define GMMx2860_TYPE TYPE_GMM -// Field Data -#define GMMx2860_IntLvRegionEn_OFFSET 0 -#define GMMx2860_IntLvRegionEn_WIDTH 1 -#define GMMx2860_IntLvRegionEn_MASK 0x1 -#define GMMx2860_Reserved_2_1_OFFSET 1 -#define GMMx2860_Reserved_2_1_WIDTH 2 -#define GMMx2860_Reserved_2_1_MASK 0x6 -#define GMMx2860_IntLvRegionBase_OFFSET 3 -#define GMMx2860_IntLvRegionBase_WIDTH 5 -#define GMMx2860_IntLvRegionBase_MASK 0xf8 -#define GMMx2860_Reserved_10_8_OFFSET 8 -#define GMMx2860_Reserved_10_8_WIDTH 3 -#define GMMx2860_Reserved_10_8_MASK 0x700 -#define GMMx2860_IntLvRegionLimit_OFFSET 11 -#define GMMx2860_IntLvRegionLimit_WIDTH 5 -#define GMMx2860_IntLvRegionLimit_MASK 0xf800 -#define GMMx2860_Reserved_31_16_OFFSET 16 -#define GMMx2860_Reserved_31_16_WIDTH 16 -#define GMMx2860_Reserved_31_16_MASK 0xffff0000 - -/// GMMx2860 -typedef union { - struct { ///< - UINT32 IntLvRegionEn:1 ; ///< - UINT32 Reserved_2_1:2 ; ///< - UINT32 IntLvRegionBase:5 ; ///< - UINT32 Reserved_10_8:3 ; ///< - UINT32 IntLvRegionLimit:5 ; ///< - UINT32 Reserved_31_16:16; ///< - } Field; ///< - UINT32 Value; ///< -} GMMx2860_STRUCT; - -// **** GMMx2864 Register Definition **** -// Address -#define GMMx2864_ADDRESS 0x2864 - -// Type -#define GMMx2864_TYPE TYPE_GMM -// Field Data -#define GMMx2864_A8Map_OFFSET 0 -#define GMMx2864_A8Map_WIDTH 4 -#define GMMx2864_A8Map_MASK 0xf -#define GMMx2864_A9Map_OFFSET 4 -#define GMMx2864_A9Map_WIDTH 4 -#define GMMx2864_A9Map_MASK 0xf0 -#define GMMx2864_A10Map_OFFSET 8 -#define GMMx2864_A10Map_WIDTH 4 -#define GMMx2864_A10Map_MASK 0xf00 -#define GMMx2864_A11Map_OFFSET 12 -#define GMMx2864_A11Map_WIDTH 4 -#define GMMx2864_A11Map_MASK 0xf000 -#define GMMx2864_A12Map_OFFSET 16 -#define GMMx2864_A12Map_WIDTH 4 -#define GMMx2864_A12Map_MASK 0xf0000 -#define GMMx2864_A13Map_OFFSET 20 -#define GMMx2864_A13Map_WIDTH 4 -#define GMMx2864_A13Map_MASK 0xf00000 -#define GMMx2864_A14Map_OFFSET 24 -#define GMMx2864_A14Map_WIDTH 4 -#define GMMx2864_A14Map_MASK 0xf000000 -#define GMMx2864_A15Map_OFFSET 28 -#define GMMx2864_A15Map_WIDTH 4 -#define GMMx2864_A15Map_MASK 0xf0000000 - -/// GMMx2864 -typedef union { - struct { ///< - UINT32 A8Map:4 ; ///< - UINT32 A9Map:4 ; ///< - UINT32 A10Map:4 ; ///< - UINT32 A11Map:4 ; ///< - UINT32 A12Map:4 ; ///< - UINT32 A13Map:4 ; ///< - UINT32 A14Map:4 ; ///< - UINT32 A15Map:4 ; ///< - } Field; ///< - UINT32 Value; ///< -} GMMx2864_STRUCT; - -// **** GMMx2868 Register Definition **** -// Address -#define GMMx2868_ADDRESS 0x2868 - -// Type -#define GMMx2868_TYPE TYPE_GMM -// Field Data -#define GMMx2868_A16Map_OFFSET 0 -#define GMMx2868_A16Map_WIDTH 4 -#define GMMx2868_A16Map_MASK 0xf -#define GMMx2868_A17Map_OFFSET 4 -#define GMMx2868_A17Map_WIDTH 4 -#define GMMx2868_A17Map_MASK 0xf0 -#define GMMx2868_A18Map_OFFSET 8 -#define GMMx2868_A18Map_WIDTH 4 -#define GMMx2868_A18Map_MASK 0xf00 -#define GMMx2868_A19Map_OFFSET 12 -#define GMMx2868_A19Map_WIDTH 4 -#define GMMx2868_A19Map_MASK 0xf000 -#define GMMx2868_Reserved_31_16_OFFSET 16 -#define GMMx2868_Reserved_31_16_WIDTH 16 -#define GMMx2868_Reserved_31_16_MASK 0xffff0000 - -/// GMMx2868 -typedef union { - struct { ///< - UINT32 A16Map:4 ; ///< - UINT32 A17Map:4 ; ///< - UINT32 A18Map:4 ; ///< - UINT32 A19Map:4 ; ///< - UINT32 Reserved_31_16:16; ///< - } Field; ///< - UINT32 Value; ///< -} GMMx2868_STRUCT; - -// **** GMMx286C Register Definition **** -// Address -#define GMMx286C_ADDRESS 0x286c - -// Type -#define GMMx286C_TYPE TYPE_GMM -// Field Data -#define GMMx286C_Base_OFFSET 0 -#define GMMx286C_Base_WIDTH 20 -#define GMMx286C_Base_MASK 0xfffff -#define GMMx286C_Reserved_31_20_OFFSET 20 -#define GMMx286C_Reserved_31_20_WIDTH 12 -#define GMMx286C_Reserved_31_20_MASK 0xfff00000 - -/// GMMx286C -typedef union { - struct { ///< - UINT32 Base:20; ///< - UINT32 Reserved_31_20:12; ///< - } Field; ///< - UINT32 Value; ///< -} GMMx286C_STRUCT; - -// **** GMMx2870 Register Definition **** -// Address -#define GMMx2870_ADDRESS 0x2870 - -// Type -#define GMMx2870_TYPE TYPE_GMM -// Field Data -#define GMMx2870_Base_OFFSET 0 -#define GMMx2870_Base_WIDTH 20 -#define GMMx2870_Base_MASK 0xfffff -#define GMMx2870_Reserved_31_20_OFFSET 20 -#define GMMx2870_Reserved_31_20_WIDTH 12 -#define GMMx2870_Reserved_31_20_MASK 0xfff00000 - -/// GMMx2870 -typedef union { - struct { ///< - UINT32 Base:20; ///< - UINT32 Reserved_31_20:12; ///< - } Field; ///< - UINT32 Value; ///< -} GMMx2870_STRUCT; - -// **** GMMx2874 Register Definition **** -// Address -#define GMMx2874_ADDRESS 0x2874 - -// Type -#define GMMx2874_TYPE TYPE_GMM -// Field Data -#define GMMx2874_Base_OFFSET 0 -#define GMMx2874_Base_WIDTH 20 -#define GMMx2874_Base_MASK 0xfffff -#define GMMx2874_Reserved_31_20_OFFSET 20 -#define GMMx2874_Reserved_31_20_WIDTH 12 -#define GMMx2874_Reserved_31_20_MASK 0xfff00000 - -/// GMMx2874 -typedef union { - struct { ///< - UINT32 Base:20; ///< - UINT32 Reserved_31_20:12; ///< - } Field; ///< - UINT32 Value; ///< -} GMMx2874_STRUCT; - -// **** GMMx2878 Register Definition **** -// Address -#define GMMx2878_ADDRESS 0x2878 - -// Type -#define GMMx2878_TYPE TYPE_GMM -// Field Data -#define GMMx2878_Base_OFFSET 0 -#define GMMx2878_Base_WIDTH 20 -#define GMMx2878_Base_MASK 0xfffff -#define GMMx2878_Reserved_31_20_OFFSET 20 -#define GMMx2878_Reserved_31_20_WIDTH 12 -#define GMMx2878_Reserved_31_20_MASK 0xfff00000 - -/// GMMx2878 -typedef union { - struct { ///< - UINT32 Base:20; ///< - UINT32 Reserved_31_20:12; ///< - } Field; ///< - UINT32 Value; ///< -} GMMx2878_STRUCT; - -// **** GMMx287C Register Definition **** -// Address -#define GMMx287C_ADDRESS 0x287c - -// Type -#define GMMx287C_TYPE TYPE_GMM -// Field Data -#define GMMx287C_Top_OFFSET 0 -#define GMMx287C_Top_WIDTH 20 -#define GMMx287C_Top_MASK 0xfffff -#define GMMx287C_Reserved_31_20_OFFSET 20 -#define GMMx287C_Reserved_31_20_WIDTH 12 -#define GMMx287C_Reserved_31_20_MASK 0xfff00000 - -/// GMMx287C -typedef union { - struct { ///< - UINT32 Top:20; ///< - UINT32 Reserved_31_20:12; ///< - } Field; ///< - UINT32 Value; ///< -} GMMx287C_STRUCT; - -// **** GMMx2880 Register Definition **** -// Address -#define GMMx2880_ADDRESS 0x2880 - -// Type -#define GMMx2880_TYPE TYPE_GMM -// Field Data -#define GMMx2880_Top_OFFSET 0 -#define GMMx2880_Top_WIDTH 20 -#define GMMx2880_Top_MASK 0xfffff -#define GMMx2880_Reserved_31_20_OFFSET 20 -#define GMMx2880_Reserved_31_20_WIDTH 12 -#define GMMx2880_Reserved_31_20_MASK 0xfff00000 - -/// GMMx2880 -typedef union { - struct { ///< - UINT32 Top:20; ///< - UINT32 Reserved_31_20:12; ///< - } Field; ///< - UINT32 Value; ///< -} GMMx2880_STRUCT; - -// **** GMMx2884 Register Definition **** -// Address -#define GMMx2884_ADDRESS 0x2884 - -// Type -#define GMMx2884_TYPE TYPE_GMM -// Field Data -#define GMMx2884_Top_OFFSET 0 -#define GMMx2884_Top_WIDTH 20 -#define GMMx2884_Top_MASK 0xfffff -#define GMMx2884_Reserved_31_20_OFFSET 20 -#define GMMx2884_Reserved_31_20_WIDTH 12 -#define GMMx2884_Reserved_31_20_MASK 0xfff00000 - -/// GMMx2884 -typedef union { - struct { ///< - UINT32 Top:20; ///< - UINT32 Reserved_31_20:12; ///< - } Field; ///< - UINT32 Value; ///< -} GMMx2884_STRUCT; - -// **** GMMx2888 Register Definition **** -// Address -#define GMMx2888_ADDRESS 0x2888 - -// Type -#define GMMx2888_TYPE TYPE_GMM -// Field Data -#define GMMx2888_Top_OFFSET 0 -#define GMMx2888_Top_WIDTH 20 -#define GMMx2888_Top_MASK 0xfffff -#define GMMx2888_Reserved_31_20_OFFSET 20 -#define GMMx2888_Reserved_31_20_WIDTH 12 -#define GMMx2888_Reserved_31_20_MASK 0xfff00000 - -/// GMMx2888 -typedef union { - struct { ///< - UINT32 Top:20; ///< - UINT32 Reserved_31_20:12; ///< - } Field; ///< - UINT32 Value; ///< -} GMMx2888_STRUCT; - -// **** GMMx288C Register Definition **** -// Address -#define GMMx288C_ADDRESS 0x288c - -// Type -#define GMMx288C_TYPE TYPE_GMM -// Field Data -#define GMMx288C_Base_OFFSET 0 -#define GMMx288C_Base_WIDTH 20 -#define GMMx288C_Base_MASK 0xfffff -#define GMMx288C_Reserved_31_20_OFFSET 20 -#define GMMx288C_Reserved_31_20_WIDTH 12 -#define GMMx288C_Reserved_31_20_MASK 0xfff00000 - -/// GMMx288C -typedef union { - struct { ///< - UINT32 Base:20; ///< - UINT32 Reserved_31_20:12; ///< - } Field; ///< - UINT32 Value; ///< -} GMMx288C_STRUCT; - -// **** GMMx2890 Register Definition **** -// Address -#define GMMx2890_ADDRESS 0x2890 - -// Type -#define GMMx2890_TYPE TYPE_GMM -// Field Data -#define GMMx2890_Top_OFFSET 0 -#define GMMx2890_Top_WIDTH 20 -#define GMMx2890_Top_MASK 0xfffff -#define GMMx2890_Reserved_31_20_OFFSET 20 -#define GMMx2890_Reserved_31_20_WIDTH 12 -#define GMMx2890_Reserved_31_20_MASK 0xfff00000 - -/// GMMx2890 -typedef union { - struct { ///< - UINT32 Top:20; ///< - UINT32 Reserved_31_20:12; ///< - } Field; ///< - UINT32 Value; ///< -} GMMx2890_STRUCT; - -// **** GMMx2894 Register Definition **** -// Address -#define GMMx2894_ADDRESS 0x2894 - -// Type -#define GMMx2894_TYPE TYPE_GMM -// Field Data -#define GMMx2894_Def_OFFSET 0 -#define GMMx2894_Def_WIDTH 28 -#define GMMx2894_Def_MASK 0xfffffff -#define GMMx2894_Reserved_31_28_OFFSET 28 -#define GMMx2894_Reserved_31_28_WIDTH 4 -#define GMMx2894_Reserved_31_28_MASK 0xf0000000 - -/// GMMx2894 -typedef union { - struct { ///< - UINT32 Def:28; ///< - UINT32 Reserved_31_28:4 ; ///< - } Field; ///< - UINT32 Value; ///< -} GMMx2894_STRUCT; - -// **** GMMx2898 Register Definition **** -// Address -#define GMMx2898_ADDRESS 0x2898 - -// Type -#define GMMx2898_TYPE TYPE_GMM -// Field Data -#define GMMx2898_Offset_OFFSET 0 -#define GMMx2898_Offset_WIDTH 20 -#define GMMx2898_Offset_MASK 0xfffff -#define GMMx2898_Base_OFFSET 20 -#define GMMx2898_Base_WIDTH 4 -#define GMMx2898_Base_MASK 0xf00000 -#define GMMx2898_Top_OFFSET 24 -#define GMMx2898_Top_WIDTH 4 -#define GMMx2898_Top_MASK 0xf000000 -#define GMMx2898_Reserved_31_28_OFFSET 28 -#define GMMx2898_Reserved_31_28_WIDTH 4 -#define GMMx2898_Reserved_31_28_MASK 0xf0000000 - -/// GMMx2898 -typedef union { - struct { ///< - UINT32 Offset:20; ///< - UINT32 Base:4 ; ///< - UINT32 Top:4 ; ///< - UINT32 Reserved_31_28:4 ; ///< - } Field; ///< - UINT32 Value; ///< -} GMMx2898_STRUCT; - -// **** GMMx28C8 Register Definition **** -// Address -#define GMMx28C8_ADDRESS 0x28c8 - -// Type -#define GMMx28C8_TYPE TYPE_GMM -// Field Data -#define GMMx28C8_Delay_OFFSET 0 -#define GMMx28C8_Delay_WIDTH 4 -#define GMMx28C8_Delay_MASK 0xf -#define GMMx28C8_Reserved_31_4_OFFSET 4 -#define GMMx28C8_Reserved_31_4_WIDTH 28 -#define GMMx28C8_Reserved_31_4_MASK 0xfffffff0 - -/// GMMx28C8 -typedef union { - struct { ///< - UINT32 Delay:4 ; ///< - UINT32 Reserved_31_4:28; ///< - } Field; ///< - UINT32 Value; ///< -} GMMx28C8_STRUCT; - -// **** GMMx28D8 Register Definition **** -// Address -#define GMMx28D8_ADDRESS 0x28d8 - -// Type -#define GMMx28D8_TYPE TYPE_GMM -// Field Data -#define GMMx28D8_ActRd_OFFSET 0 -#define GMMx28D8_ActRd_WIDTH 8 -#define GMMx28D8_ActRd_MASK 0xff -#define GMMx28D8_ActWr_OFFSET 8 -#define GMMx28D8_ActWr_WIDTH 8 -#define GMMx28D8_ActWr_MASK 0xff00 -#define GMMx28D8_RasMActRd_OFFSET 16 -#define GMMx28D8_RasMActRd_WIDTH 8 -#define GMMx28D8_RasMActRd_MASK 0xff0000 -#define GMMx28D8_RasMActWr_OFFSET 24 -#define GMMx28D8_RasMActWr_WIDTH 8 -#define GMMx28D8_RasMActWr_MASK 0xff000000 - -/// GMMx28D8 -typedef union { - struct { ///< - UINT32 ActRd:8 ; ///< - UINT32 ActWr:8 ; ///< - UINT32 RasMActRd:8 ; ///< - UINT32 RasMActWr:8 ; ///< - } Field; ///< - UINT32 Value; ///< -} GMMx28D8_STRUCT; - -// **** GMMx28DC Register Definition **** -// Address -#define GMMx28DC_ADDRESS 0x28dc - -// Type -#define GMMx28DC_TYPE TYPE_GMM -// Field Data -#define GMMx28DC_Ras2Ras_OFFSET 0 -#define GMMx28DC_Ras2Ras_WIDTH 8 -#define GMMx28DC_Ras2Ras_MASK 0xff -#define GMMx28DC_Rp_OFFSET 8 -#define GMMx28DC_Rp_WIDTH 8 -#define GMMx28DC_Rp_MASK 0xff00 -#define GMMx28DC_WrPlusRp_OFFSET 16 -#define GMMx28DC_WrPlusRp_WIDTH 8 -#define GMMx28DC_WrPlusRp_MASK 0xff0000 -#define GMMx28DC_BusTurn_OFFSET 24 -#define GMMx28DC_BusTurn_WIDTH 8 -#define GMMx28DC_BusTurn_MASK 0xff000000 - -/// GMMx28DC -typedef union { - struct { ///< - UINT32 Ras2Ras:8 ; ///< - UINT32 Rp:8 ; ///< - UINT32 WrPlusRp:8 ; ///< - UINT32 BusTurn:8 ; ///< - } Field; ///< - UINT32 Value; ///< -} GMMx28DC_STRUCT; - -// **** GMMx28EC Register Definition **** -// Address -#define GMMx28EC_ADDRESS 0x28ec - -// Type -#define GMMx28EC_TYPE TYPE_GMM -// Field Data -#define GMMx28EC_Reserved_17_0_OFFSET 0 -#define GMMx28EC_Reserved_17_0_WIDTH 18 -#define GMMx28EC_Reserved_17_0_MASK 0x3ffff -#define GMMx28EC_DctCredits_OFFSET 18 -#define GMMx28EC_DctCredits_WIDTH 4 -#define GMMx28EC_DctCredits_MASK 0x3c0000 -#define GMMx28EC_Reserved_31_22_OFFSET 22 -#define GMMx28EC_Reserved_31_22_WIDTH 10 -#define GMMx28EC_Reserved_31_22_MASK 0xffc00000 - -/// GMMx28EC -typedef union { - struct { ///< - UINT32 Reserved_17_0:18; ///< - UINT32 DctCredits:4 ; ///< - UINT32 Reserved_31_22:10; ///< - } Field; ///< - UINT32 Value; ///< -} GMMx28EC_STRUCT; - -// **** GMMx2B8C Register Definition **** -// Address -#define GMMx2B8C_ADDRESS 0x2b8c - -// Type -#define GMMx2B8C_TYPE TYPE_GMM -// Field Data -#define GMMx2B8C_RengRamIndex_OFFSET 0 -#define GMMx2B8C_RengRamIndex_WIDTH 10 -#define GMMx2B8C_RengRamIndex_MASK 0x3ff -#define GMMx2B8C_Reserved_31_10_OFFSET 10 -#define GMMx2B8C_Reserved_31_10_WIDTH 22 -#define GMMx2B8C_Reserved_31_10_MASK 0xfffffc00 - -/// GMMx2B8C -typedef union { - struct { ///< - UINT32 RengRamIndex:10; ///< - UINT32 Reserved_31_10:22; ///< - } Field; ///< - UINT32 Value; ///< -} GMMx2B8C_STRUCT; - -// **** GMMx2B90 Register Definition **** -// Address -#define GMMx2B90_ADDRESS 0x2b90 - -// Type -#define GMMx2B90_TYPE TYPE_GMM -// Field Data -#define GMMx2B90_RengRamData_OFFSET 0 -#define GMMx2B90_RengRamData_WIDTH 32 -#define GMMx2B90_RengRamData_MASK 0xffffffff - -/// GMMx2B90 -typedef union { - struct { ///< - UINT32 RengRamData:32; ///< - } Field; ///< - UINT32 Value; ///< -} GMMx2B90_STRUCT; - -// **** GMMx2B94 Register Definition **** -// Address -#define GMMx2B94_ADDRESS 0x2b94 - -// Type -#define GMMx2B94_TYPE TYPE_GMM -// Field Data -#define GMMx2B94_RengExecuteOnPwrUp_OFFSET 0 -#define GMMx2B94_RengExecuteOnPwrUp_WIDTH 1 -#define GMMx2B94_RengExecuteOnPwrUp_MASK 0x1 -#define GMMx2B94_Reserved_31_1_OFFSET 1 -#define GMMx2B94_Reserved_31_1_WIDTH 31 -#define GMMx2B94_Reserved_31_1_MASK 0xfffffffe - -/// GMMx2B94 -typedef union { - struct { ///< - UINT32 RengExecuteOnPwrUp:1 ; ///< - UINT32 Reserved_31_1:31; ///< - } Field; ///< - UINT32 Value; ///< -} GMMx2B94_STRUCT; - -// **** GMMx2B98 Register Definition **** -// Address -#define GMMx2B98_ADDRESS 0x2b98 - -// Type -#define GMMx2B98_TYPE TYPE_GMM -// Field Data -#define GMMx2B98_RengExecuteNonsecureStartPtr_OFFSET 0 -#define GMMx2B98_RengExecuteNonsecureStartPtr_WIDTH 10 -#define GMMx2B98_RengExecuteNonsecureStartPtr_MASK 0x3ff -#define GMMx2B98_Reserved_10_10_OFFSET 10 -#define GMMx2B98_Reserved_10_10_WIDTH 1 -#define GMMx2B98_Reserved_10_10_MASK 0x400 -#define GMMx2B98_RengExecuteOnRegUpdate_OFFSET 11 -#define GMMx2B98_RengExecuteOnRegUpdate_WIDTH 1 -#define GMMx2B98_RengExecuteOnRegUpdate_MASK 0x800 -#define GMMx2B98_Reserved_26_12_OFFSET 12 -#define GMMx2B98_Reserved_26_12_WIDTH 15 -#define GMMx2B98_Reserved_26_12_MASK 0x7fff000 -#define GMMx2B98_CriticalRegsLock_OFFSET 27 -#define GMMx2B98_CriticalRegsLock_WIDTH 1 -#define GMMx2B98_CriticalRegsLock_MASK 0x8000000 -#define GMMx2B98_Reserved_31_28_OFFSET 28 -#define GMMx2B98_Reserved_31_28_WIDTH 4 -#define GMMx2B98_Reserved_31_28_MASK 0xf0000000 -#define GMMx2B98_StctrlStutterEn_OFFSET 16 -#define GMMx2B98_StctrlStutterEn_WIDTH 1 -#define GMMx2B98_StctrlStutterEn_MASK 0x10000 - -/// GMMx2B98 -typedef union { - struct { ///< - UINT32 RengExecuteNonsecureStartPtr:10; ///< - UINT32 Reserved_10_10:1 ; ///< - UINT32 RengExecuteOnRegUpdate:1 ; ///< - UINT32 Reserved_26_12:15; ///< - UINT32 CriticalRegsLock:1 ; ///< - UINT32 Reserved_31_28:4 ; ///< - } Field; ///< - UINT32 Value; ///< -} GMMx2B98_STRUCT; - -// **** GMMx2C04 Register Definition **** -// Address -#define GMMx2C04_ADDRESS 0x2c04 - -// Type -#define GMMx2C04_TYPE TYPE_GMM -// Field Data -#define GMMx2C04_NonsurfBase_OFFSET 0 -#define GMMx2C04_NonsurfBase_WIDTH 28 -#define GMMx2C04_NonsurfBase_MASK 0xfffffff -#define GMMx2C04_Reserved_31_28_OFFSET 28 -#define GMMx2C04_Reserved_31_28_WIDTH 4 -#define GMMx2C04_Reserved_31_28_MASK 0xf0000000 - -/// GMMx2C04 -typedef union { - struct { ///< - UINT32 NonsurfBase:28; ///< - UINT32 Reserved_31_28:4 ; ///< - } Field; ///< - UINT32 Value; ///< -} GMMx2C04_STRUCT; - -// **** GMMx5428 Register Definition **** -// Address -#define GMMx5428_ADDRESS 0x5428 - -// Type -#define GMMx5428_TYPE TYPE_GMM -// Field Data -#define GMMx5428_ConfigMemsize_OFFSET 0 -#define GMMx5428_ConfigMemsize_WIDTH 32 -#define GMMx5428_ConfigMemsize_MASK 0xffffffff - -/// GMMx5428 -typedef union { - struct { ///< - UINT32 ConfigMemsize:32; ///< - } Field; ///< - UINT32 Value; ///< -} GMMx5428_STRUCT; - -// **** GMMx5490 Register Definition **** -// Address -#define GMMx5490_ADDRESS 0x5490 - -// Type -#define GMMx5490_TYPE TYPE_GMM -// Field Data -#define GMMx5490_FbReadEn_OFFSET 0 -#define GMMx5490_FbReadEn_WIDTH 1 -#define GMMx5490_FbReadEn_MASK 0x1 -#define GMMx5490_FbWriteEn_OFFSET 1 -#define GMMx5490_FbWriteEn_WIDTH 1 -#define GMMx5490_FbWriteEn_MASK 0x2 -#define GMMx5490_Reserved_31_2_OFFSET 2 -#define GMMx5490_Reserved_31_2_WIDTH 30 -#define GMMx5490_Reserved_31_2_MASK 0xfffffffc - -/// GMMx5490 -typedef union { - struct { ///< - UINT32 FbReadEn:1 ; ///< - UINT32 FbWriteEn:1 ; ///< - UINT32 Reserved_31_2:30; ///< - } Field; ///< - UINT32 Value; ///< -} GMMx5490_STRUCT; - -// **** SMUx01 Register Definition **** -// Address -#define SMUx01_ADDRESS 0x1 - -// Type -#define SMUx01_TYPE TYPE_SMU -// Field Data -#define SMUx01_RamSwitch_OFFSET 0 -#define SMUx01_RamSwitch_WIDTH 1 -#define SMUx01_RamSwitch_MASK 0x1 -#define SMUx01_Reset_OFFSET 1 -#define SMUx01_Reset_WIDTH 1 -#define SMUx01_Reset_MASK 0x2 -#define SMUx01_Reserved_17_2_OFFSET 2 -#define SMUx01_Reserved_17_2_WIDTH 16 -#define SMUx01_Reserved_17_2_MASK 0x3fffc -#define SMUx01_VectorOverride_OFFSET 18 -#define SMUx01_VectorOverride_WIDTH 1 -#define SMUx01_VectorOverride_MASK 0x40000 -#define SMUx01_Reserved_31_19_OFFSET 19 -#define SMUx01_Reserved_31_19_WIDTH 13 -#define SMUx01_Reserved_31_19_MASK 0xfff80000 - -/// SMUx01 -typedef union { - struct { ///< - UINT32 RamSwitch:1 ; ///< - UINT32 Reset:1 ; ///< - UINT32 Reserved_17_2:16; ///< - UINT32 VectorOverride:1 ; ///< - UINT32 Reserved_31_19:13; ///< - } Field; ///< - UINT32 Value; ///< -} SMUx01_STRUCT; - -// **** SMUx03 Register Definition **** -// Address -#define SMUx03_ADDRESS 0x3 - -// Type -#define SMUx03_TYPE TYPE_SMU -// Field Data -#define SMUx03_IntReq_OFFSET 0 -#define SMUx03_IntReq_WIDTH 1 -#define SMUx03_IntReq_MASK 0x1 -#define SMUx03_IntAck_OFFSET 1 -#define SMUx03_IntAck_WIDTH 1 -#define SMUx03_IntAck_MASK 0x2 -#define SMUx03_IntDone_OFFSET 2 -#define SMUx03_IntDone_WIDTH 1 -#define SMUx03_IntDone_MASK 0x4 -#define SMUx03_ServiceIndex_OFFSET 3 -#define SMUx03_ServiceIndex_WIDTH 8 -#define SMUx03_ServiceIndex_MASK 0x7f8 -#define SMUx03_Reserved_31_11_OFFSET 11 -#define SMUx03_Reserved_31_11_WIDTH 21 -#define SMUx03_Reserved_31_11_MASK 0xfffff800 - -/// SMUx03 -typedef union { - struct { ///< - UINT32 IntReq:1 ; ///< - UINT32 IntAck:1 ; ///< - UINT32 IntDone:1 ; ///< - UINT32 ServiceIndex:8 ; ///< - UINT32 Reserved_31_11:21; ///< - } Field; ///< - UINT32 Value; ///< -} SMUx03_STRUCT; - -// **** SMUx05 Register Definition **** -// Address -#define SMUx05_ADDRESS 0x5 - -// Type -#define SMUx05_TYPE TYPE_SMU -// Field Data -#define SMUx05_McuRam_OFFSET 0 -#define SMUx05_McuRam_WIDTH 32 -#define SMUx05_McuRam_MASK 0xffffffff - -/// SMUx05 -typedef union { - struct { ///< - UINT32 McuRam:32; ///< - } Field; ///< - UINT32 Value; ///< -} SMUx05_STRUCT; - -// **** SMUx0B Register Definition **** -// Address -#define SMUx0B_ADDRESS 0xb - -// Type -#define SMUx0B_TYPE TYPE_SMU -// Field Data -#define SMUx0B_MemAddr_OFFSET 0 -#define SMUx0B_MemAddr_WIDTH 16 -#define SMUx0B_MemAddr_MASK 0xffff - -/// SMUx0B -typedef union { - struct { ///< - UINT32 MemAddr:16; ///< - } Field; ///< - UINT32 Value; ///< -} SMUx0B_STRUCT; - -// **** SMUx1B Register Definition **** -// Address -#define SMUx1B_ADDRESS 0x1b - -// Type -#define SMUx1B_TYPE TYPE_SMU -// Field Data -#define SMUx1B_LclkDpSlpDiv_OFFSET 0 -#define SMUx1B_LclkDpSlpDiv_WIDTH 3 -#define SMUx1B_LclkDpSlpDiv_MASK 0x7 -#define SMUx1B_RampDis_OFFSET 3 -#define SMUx1B_RampDis_WIDTH 1 -#define SMUx1B_RampDis_MASK 0x8 -#define SMUx1B_Reserved_7_4_OFFSET 4 -#define SMUx1B_Reserved_7_4_WIDTH 4 -#define SMUx1B_Reserved_7_4_MASK 0xf0 -#define SMUx1B_LclkDpSlpMask_OFFSET 8 -#define SMUx1B_LclkDpSlpMask_WIDTH 8 -#define SMUx1B_LclkDpSlpMask_MASK 0xff00 - -/// SMUx1B -typedef union { - struct { ///< - UINT32 LclkDpSlpDiv:3 ; ///< - UINT32 RampDis:1 ; ///< - UINT32 Reserved_7_4:4 ; ///< - UINT32 LclkDpSlpMask:8 ; ///< - } Field; ///< - UINT32 Value; ///< -} SMUx1B_STRUCT; - -// **** SMUx1D Register Definition **** -// Address -#define SMUx1D_ADDRESS 0x1d - -// Type -#define SMUx1D_TYPE TYPE_SMU -// Field Data -#define SMUx1D_LclkDpSlpHyst_OFFSET 0 -#define SMUx1D_LclkDpSlpHyst_WIDTH 12 -#define SMUx1D_LclkDpSlpHyst_MASK 0xfff -#define SMUx1D_LclkDpSlpEn_OFFSET 12 -#define SMUx1D_LclkDpSlpEn_WIDTH 1 -#define SMUx1D_LclkDpSlpEn_MASK 0x1000 -#define SMUx1D_Reserved_15_13_OFFSET 13 -#define SMUx1D_Reserved_15_13_WIDTH 3 -#define SMUx1D_Reserved_15_13_MASK 0xe000 - -/// SMUx1D -typedef union { - struct { ///< - UINT32 LclkDpSlpHyst:12; ///< - UINT32 LclkDpSlpEn:1 ; ///< - UINT32 Reserved_15_13:3 ; ///< - } Field; ///< - UINT32 Value; ///< -} SMUx1D_STRUCT; - -// **** SMUx33 Register Definition **** -// Address -#define SMUx33_ADDRESS 0x33 - -// Type -#define SMUx33_TYPE TYPE_SMU -// Field Data -#define SMUx33_LclkActMonPrd_OFFSET 0 -#define SMUx33_LclkActMonPrd_WIDTH 16 -#define SMUx33_LclkActMonPrd_MASK 0xffff -#define SMUx33_LclkActMonUnt_OFFSET 16 -#define SMUx33_LclkActMonUnt_WIDTH 4 -#define SMUx33_LclkActMonUnt_MASK 0xf0000 -#define SMUx33_TrendMode_OFFSET 20 -#define SMUx33_TrendMode_WIDTH 1 -#define SMUx33_TrendMode_MASK 0x100000 -#define SMUx33_ForceTrend_OFFSET 21 -#define SMUx33_ForceTrend_WIDTH 1 -#define SMUx33_ForceTrend_MASK 0x200000 -#define SMUx33_ActMonRst_OFFSET 22 -#define SMUx33_ActMonRst_WIDTH 1 -#define SMUx33_ActMonRst_MASK 0x400000 -#define SMUx33_BusyCntSel_OFFSET 23 -#define SMUx33_BusyCntSel_WIDTH 2 -#define SMUx33_BusyCntSel_MASK 0x1800000 -#define SMUx33_AccessCntl_OFFSET 25 -#define SMUx33_AccessCntl_WIDTH 1 -#define SMUx33_AccessCntl_MASK 0x2000000 -#define SMUx33_Reserved_31_26_OFFSET 26 -#define SMUx33_Reserved_31_26_WIDTH 6 -#define SMUx33_Reserved_31_26_MASK 0xfc000000 - -/// SMUx33 -typedef union { - struct { ///< - UINT32 LclkActMonPrd:16; ///< - UINT32 LclkActMonUnt:4 ; ///< - UINT32 TrendMode:1 ; ///< - UINT32 ForceTrend:1 ; ///< - UINT32 ActMonRst:1 ; ///< - UINT32 BusyCntSel:2 ; ///< - UINT32 AccessCntl:1 ; ///< - UINT32 Reserved_31_26:6 ; ///< - } Field; ///< - UINT32 Value; ///< -} SMUx33_STRUCT; - -// **** SMUx35 Register Definition **** -// Address -#define SMUx35_ADDRESS 0x35 - -// Type -#define SMUx35_TYPE TYPE_SMU -// Field Data -#define SMUx35_DownTrendCoef_OFFSET 0 -#define SMUx35_DownTrendCoef_WIDTH 10 -#define SMUx35_DownTrendCoef_MASK 0x3ff -#define SMUx35_UpTrendCoef_OFFSET 10 -#define SMUx35_UpTrendCoef_WIDTH 10 -#define SMUx35_UpTrendCoef_MASK 0xffc00 -#define SMUx35_Reserved_31_20_OFFSET 20 -#define SMUx35_Reserved_31_20_WIDTH 12 -#define SMUx35_Reserved_31_20_MASK 0xfff00000 - -/// SMUx35 -typedef union { - struct { ///< - UINT32 DownTrendCoef:10; ///< - UINT32 UpTrendCoef:10; ///< - UINT32 Reserved_31_20:12; ///< - } Field; ///< - UINT32 Value; ///< -} SMUx35_STRUCT; - -// **** SMUx37 Register Definition **** -// Address -#define SMUx37_ADDRESS 0x37 - -// Type -#define SMUx37_TYPE TYPE_SMU -// Field Data -#define SMUx37_DownTrendCoef_OFFSET 0 -#define SMUx37_DownTrendCoef_WIDTH 10 -#define SMUx37_DownTrendCoef_MASK 0x3ff -#define SMUx37_UpTrendCoef_OFFSET 10 -#define SMUx37_UpTrendCoef_WIDTH 10 -#define SMUx37_UpTrendCoef_MASK 0xffc00 -#define SMUx37_Reserved_31_20_OFFSET 20 -#define SMUx37_Reserved_31_20_WIDTH 12 -#define SMUx37_Reserved_31_20_MASK 0xfff00000 - -/// SMUx37 -typedef union { - struct { ///< - UINT32 DownTrendCoef:10; ///< - UINT32 UpTrendCoef:10; ///< - UINT32 Reserved_31_20:12; ///< - } Field; ///< - UINT32 Value; ///< -} SMUx37_STRUCT; - -// **** SMUx39 Register Definition **** -// Address -#define SMUx39_ADDRESS 0x39 - -// Type -#define SMUx39_TYPE TYPE_SMU -// Field Data -#define SMUx39_DownTrendCoef_OFFSET 0 -#define SMUx39_DownTrendCoef_WIDTH 10 -#define SMUx39_DownTrendCoef_MASK 0x3ff -#define SMUx39_UpTrendCoef_OFFSET 10 -#define SMUx39_UpTrendCoef_WIDTH 10 -#define SMUx39_UpTrendCoef_MASK 0xffc00 -#define SMUx39_Reserved_31_20_OFFSET 20 -#define SMUx39_Reserved_31_20_WIDTH 12 -#define SMUx39_Reserved_31_20_MASK 0xfff00000 - -/// SMUx39 -typedef union { - struct { ///< - UINT32 DownTrendCoef:10; ///< - UINT32 UpTrendCoef:10; ///< - UINT32 Reserved_31_20:12; ///< - } Field; ///< - UINT32 Value; ///< -} SMUx39_STRUCT; - -// **** SMUx3B Register Definition **** -// Address -#define SMUx3B_ADDRESS 0x3b - -// Type -#define SMUx3B_TYPE TYPE_SMU -// Field Data -#define SMUx3B_DownTrendCoef_OFFSET 0 -#define SMUx3B_DownTrendCoef_WIDTH 10 -#define SMUx3B_DownTrendCoef_MASK 0x3ff -#define SMUx3B_UpTrendCoef_OFFSET 10 -#define SMUx3B_UpTrendCoef_WIDTH 10 -#define SMUx3B_UpTrendCoef_MASK 0xffc00 -#define SMUx3B_Reserved_31_20_OFFSET 20 -#define SMUx3B_Reserved_31_20_WIDTH 12 -#define SMUx3B_Reserved_31_20_MASK 0xfff00000 - -/// SMUx3B -typedef union { - struct { ///< - UINT32 DownTrendCoef:10; ///< - UINT32 UpTrendCoef:10; ///< - UINT32 Reserved_31_20:12; ///< - } Field; ///< - UINT32 Value; ///< -} SMUx3B_STRUCT; - -// **** SMUx3D Register Definition **** -// Address -#define SMUx3D_ADDRESS 0x3d - -// Type -#define SMUx3D_TYPE TYPE_SMU -// Field Data -#define SMUx3D_DownTrendCoef_OFFSET 0 -#define SMUx3D_DownTrendCoef_WIDTH 10 -#define SMUx3D_DownTrendCoef_MASK 0x3ff -#define SMUx3D_UpTrendCoef_OFFSET 10 -#define SMUx3D_UpTrendCoef_WIDTH 10 -#define SMUx3D_UpTrendCoef_MASK 0xffc00 -#define SMUx3D_Reserved_31_20_OFFSET 20 -#define SMUx3D_Reserved_31_20_WIDTH 12 -#define SMUx3D_Reserved_31_20_MASK 0xfff00000 - -/// SMUx3D -typedef union { - struct { ///< - UINT32 DownTrendCoef:10; ///< - UINT32 UpTrendCoef:10; ///< - UINT32 Reserved_31_20:12; ///< - } Field; ///< - UINT32 Value; ///< -} SMUx3D_STRUCT; - -// **** SMUx3F Register Definition **** -// Address -#define SMUx3F_ADDRESS 0x3f - -// Type -#define SMUx3F_TYPE TYPE_SMU -// Field Data -#define SMUx3F_DownTrendCoef_OFFSET 0 -#define SMUx3F_DownTrendCoef_WIDTH 10 -#define SMUx3F_DownTrendCoef_MASK 0x3ff -#define SMUx3F_UpTrendCoef_OFFSET 10 -#define SMUx3F_UpTrendCoef_WIDTH 10 -#define SMUx3F_UpTrendCoef_MASK 0xffc00 -#define SMUx3F_Reserved_31_20_OFFSET 20 -#define SMUx3F_Reserved_31_20_WIDTH 12 -#define SMUx3F_Reserved_31_20_MASK 0xfff00000 - -/// SMUx3F -typedef union { - struct { ///< - UINT32 DownTrendCoef:10; ///< - UINT32 UpTrendCoef:10; ///< - UINT32 Reserved_31_20:12; ///< - } Field; ///< - UINT32 Value; ///< -} SMUx3F_STRUCT; - -// **** SMUx41 Register Definition **** -// Address -#define SMUx41_ADDRESS 0x41 - -// Type -#define SMUx41_TYPE TYPE_SMU -// Field Data -#define SMUx41_DownTrendCoef_OFFSET 0 -#define SMUx41_DownTrendCoef_WIDTH 10 -#define SMUx41_DownTrendCoef_MASK 0x3ff -#define SMUx41_UpTrendCoef_OFFSET 10 -#define SMUx41_UpTrendCoef_WIDTH 10 -#define SMUx41_UpTrendCoef_MASK 0xffc00 -#define SMUx41_Reserved_31_20_OFFSET 20 -#define SMUx41_Reserved_31_20_WIDTH 12 -#define SMUx41_Reserved_31_20_MASK 0xfff00000 - -/// SMUx41 -typedef union { - struct { ///< - UINT32 DownTrendCoef:10; ///< - UINT32 UpTrendCoef:10; ///< - UINT32 Reserved_31_20:12; ///< - } Field; ///< - UINT32 Value; ///< -} SMUx41_STRUCT; - -// **** SMUx43 Register Definition **** -// Address -#define SMUx43_ADDRESS 0x43 - -// Type -#define SMUx43_TYPE TYPE_SMU -// Field Data -#define SMUx43_DownTrendCoef_OFFSET 0 -#define SMUx43_DownTrendCoef_WIDTH 10 -#define SMUx43_DownTrendCoef_MASK 0x3ff -#define SMUx43_UpTrendCoef_OFFSET 10 -#define SMUx43_UpTrendCoef_WIDTH 10 -#define SMUx43_UpTrendCoef_MASK 0xffc00 -#define SMUx43_Reserved_31_20_OFFSET 20 -#define SMUx43_Reserved_31_20_WIDTH 12 -#define SMUx43_Reserved_31_20_MASK 0xfff00000 - -/// SMUx43 -typedef union { - struct { ///< - UINT32 DownTrendCoef:10; ///< - UINT32 UpTrendCoef:10; ///< - UINT32 Reserved_31_20:12; ///< - } Field; ///< - UINT32 Value; ///< -} SMUx43_STRUCT; - -// **** SMUx45 Register Definition **** -// Address -#define SMUx45_ADDRESS 0x45 - -// Type -#define SMUx45_TYPE TYPE_SMU -// Field Data -#define SMUx45_DownTrendCoef_OFFSET 0 -#define SMUx45_DownTrendCoef_WIDTH 10 -#define SMUx45_DownTrendCoef_MASK 0x3ff -#define SMUx45_UpTrendCoef_OFFSET 10 -#define SMUx45_UpTrendCoef_WIDTH 10 -#define SMUx45_UpTrendCoef_MASK 0xffc00 -#define SMUx45_Reserved_31_20_OFFSET 20 -#define SMUx45_Reserved_31_20_WIDTH 12 -#define SMUx45_Reserved_31_20_MASK 0xfff00000 - -/// SMUx45 -typedef union { - struct { ///< - UINT32 DownTrendCoef:10; ///< - UINT32 UpTrendCoef:10; ///< - UINT32 Reserved_31_20:12; ///< - } Field; ///< - UINT32 Value; ///< -} SMUx45_STRUCT; - -// **** SMUx47 Register Definition **** -// Address -#define SMUx47_ADDRESS 0x47 - -// Type -#define SMUx47_TYPE TYPE_SMU -// Field Data -#define SMUx47_DownTrendCoef_OFFSET 0 -#define SMUx47_DownTrendCoef_WIDTH 10 -#define SMUx47_DownTrendCoef_MASK 0x3ff -#define SMUx47_UpTrendCoef_OFFSET 10 -#define SMUx47_UpTrendCoef_WIDTH 10 -#define SMUx47_UpTrendCoef_MASK 0xffc00 -#define SMUx47_Reserved_31_20_OFFSET 20 -#define SMUx47_Reserved_31_20_WIDTH 12 -#define SMUx47_Reserved_31_20_MASK 0xfff00000 - -/// SMUx47 -typedef union { - struct { ///< - UINT32 DownTrendCoef:10; ///< - UINT32 UpTrendCoef:10; ///< - UINT32 Reserved_31_20:12; ///< - } Field; ///< - UINT32 Value; ///< -} SMUx47_STRUCT; - -// **** SMUx49 Register Definition **** -// Address -#define SMUx49_ADDRESS 0x49 - -// Type -#define SMUx49_TYPE TYPE_SMU -// Field Data -#define SMUx49_DownTrendCoef_OFFSET 0 -#define SMUx49_DownTrendCoef_WIDTH 10 -#define SMUx49_DownTrendCoef_MASK 0x3ff -#define SMUx49_UpTrendCoef_OFFSET 10 -#define SMUx49_UpTrendCoef_WIDTH 10 -#define SMUx49_UpTrendCoef_MASK 0xffc00 -#define SMUx49_Reserved_31_20_OFFSET 20 -#define SMUx49_Reserved_31_20_WIDTH 12 -#define SMUx49_Reserved_31_20_MASK 0xfff00000 - -/// SMUx49 -typedef union { - struct { ///< - UINT32 DownTrendCoef:10; ///< - UINT32 UpTrendCoef:10; ///< - UINT32 Reserved_31_20:12; ///< - } Field; ///< - UINT32 Value; ///< -} SMUx49_STRUCT; - -// **** SMUx4B Register Definition **** -// Address -#define SMUx4B_ADDRESS 0x4b - -// Type -#define SMUx4B_TYPE TYPE_SMU -// Field Data -#define SMUx4B_DownTrendCoef_OFFSET 0 -#define SMUx4B_DownTrendCoef_WIDTH 10 -#define SMUx4B_DownTrendCoef_MASK 0x3ff -#define SMUx4B_UpTrendCoef_OFFSET 10 -#define SMUx4B_UpTrendCoef_WIDTH 10 -#define SMUx4B_UpTrendCoef_MASK 0xffc00 -#define SMUx4B_Reserved_31_20_OFFSET 20 -#define SMUx4B_Reserved_31_20_WIDTH 12 -#define SMUx4B_Reserved_31_20_MASK 0xfff00000 - -/// SMUx4B -typedef union { - struct { ///< - UINT32 DownTrendCoef:10; ///< - UINT32 UpTrendCoef:10; ///< - UINT32 Reserved_31_20:12; ///< - } Field; ///< - UINT32 Value; ///< -} SMUx4B_STRUCT; - -// **** SMUx4D Register Definition **** -// Address -#define SMUx4D_ADDRESS 0x4d - -// Type -#define SMUx4D_TYPE TYPE_SMU -// Field Data -#define SMUx4D_DownTrendCoef_OFFSET 0 -#define SMUx4D_DownTrendCoef_WIDTH 10 -#define SMUx4D_DownTrendCoef_MASK 0x3ff -#define SMUx4D_UpTrendCoef_OFFSET 10 -#define SMUx4D_UpTrendCoef_WIDTH 10 -#define SMUx4D_UpTrendCoef_MASK 0xffc00 -#define SMUx4D_Reserved_31_20_OFFSET 20 -#define SMUx4D_Reserved_31_20_WIDTH 12 -#define SMUx4D_Reserved_31_20_MASK 0xfff00000 - -/// SMUx4D -typedef union { - struct { ///< - UINT32 DownTrendCoef:10; ///< - UINT32 UpTrendCoef:10; ///< - UINT32 Reserved_31_20:12; ///< - } Field; ///< - UINT32 Value; ///< -} SMUx4D_STRUCT; - -// **** SMUx4F Register Definition **** -// Address -#define SMUx4F_ADDRESS 0x4f - -// Type -#define SMUx4F_TYPE TYPE_SMU -// Field Data -#define SMUx4F_DownTrendCoef_OFFSET 0 -#define SMUx4F_DownTrendCoef_WIDTH 10 -#define SMUx4F_DownTrendCoef_MASK 0x3ff -#define SMUx4F_UpTrendCoef_OFFSET 10 -#define SMUx4F_UpTrendCoef_WIDTH 10 -#define SMUx4F_UpTrendCoef_MASK 0xffc00 -#define SMUx4F_Reserved_31_20_OFFSET 20 -#define SMUx4F_Reserved_31_20_WIDTH 12 -#define SMUx4F_Reserved_31_20_MASK 0xfff00000 - -/// SMUx4F -typedef union { - struct { ///< - UINT32 DownTrendCoef:10; ///< - UINT32 UpTrendCoef:10; ///< - UINT32 Reserved_31_20:12; ///< - } Field; ///< - UINT32 Value; ///< -} SMUx4F_STRUCT; - -// **** SMUx51 Register Definition **** -// Address -#define SMUx51_ADDRESS 0x51 - -// Type -#define SMUx51_TYPE TYPE_SMU -// Field Data -#define SMUx51_DownTrendCoef_OFFSET 0 -#define SMUx51_DownTrendCoef_WIDTH 10 -#define SMUx51_DownTrendCoef_MASK 0x3ff -#define SMUx51_UpTrendCoef_OFFSET 10 -#define SMUx51_UpTrendCoef_WIDTH 10 -#define SMUx51_UpTrendCoef_MASK 0xffc00 -#define SMUx51_Reserved_31_20_OFFSET 20 -#define SMUx51_Reserved_31_20_WIDTH 12 -#define SMUx51_Reserved_31_20_MASK 0xfff00000 - -/// SMUx51 -typedef union { - struct { ///< - UINT32 DownTrendCoef:10; ///< - UINT32 UpTrendCoef:10; ///< - UINT32 Reserved_31_20:12; ///< - } Field; ///< - UINT32 Value; ///< -} SMUx51_STRUCT; - -// **** SMUx55 Register Definition **** -// Address -#define SMUx55_ADDRESS 0x55 - -// Type -#define SMUx55_TYPE TYPE_SMU -// Field Data -#define SMUx55_Threshold_0_OFFSET 0 -#define SMUx55_Threshold_0_WIDTH 16 -#define SMUx55_Threshold_0_MASK 0xffff -#define SMUx55_Threshold_1_OFFSET 16 -#define SMUx55_Threshold_1_WIDTH 16 -#define SMUx55_Threshold_1_MASK 0xffff0000 - -/// SMUx55 -typedef union { - struct { ///< - UINT32 Threshold_0:16; ///< - UINT32 Threshold_1:16; ///< - } Field; ///< - UINT32 Value; ///< -} SMUx55_STRUCT; - -// **** SMUx57 Register Definition **** -// Address -#define SMUx57_ADDRESS 0x57 - -// Type -#define SMUx57_TYPE TYPE_SMU -// Field Data -#define SMUx57_Threshold_2_OFFSET 0 -#define SMUx57_Threshold_2_WIDTH 16 -#define SMUx57_Threshold_2_MASK 0xffff -#define SMUx57_Threshold_3_OFFSET 16 -#define SMUx57_Threshold_3_WIDTH 16 -#define SMUx57_Threshold_3_MASK 0xffff0000 - -/// SMUx57 -typedef union { - struct { ///< - UINT32 Threshold_2:16; ///< - UINT32 Threshold_3:16; ///< - } Field; ///< - UINT32 Value; ///< -} SMUx57_STRUCT; - -// **** SMUx59 Register Definition **** -// Address -#define SMUx59_ADDRESS 0x59 - -// Type -#define SMUx59_TYPE TYPE_SMU -// Field Data -#define SMUx59_Threshold_4_OFFSET 0 -#define SMUx59_Threshold_4_WIDTH 16 -#define SMUx59_Threshold_4_MASK 0xffff -#define SMUx59_Threshold_5_OFFSET 16 -#define SMUx59_Threshold_5_WIDTH 16 -#define SMUx59_Threshold_5_MASK 0xffff0000 - -/// SMUx59 -typedef union { - struct { ///< - UINT32 Threshold_4:16; ///< - UINT32 Threshold_5:16; ///< - } Field; ///< - UINT32 Value; ///< -} SMUx59_STRUCT; - -// **** SMUx5B Register Definition **** -// Address -#define SMUx5B_ADDRESS 0x5b - -// Type -#define SMUx5B_TYPE TYPE_SMU -// Field Data -#define SMUx5B_Threshold_6_OFFSET 0 -#define SMUx5B_Threshold_6_WIDTH 16 -#define SMUx5B_Threshold_6_MASK 0xffff -#define SMUx5B_Threshold_7_OFFSET 16 -#define SMUx5B_Threshold_7_WIDTH 16 -#define SMUx5B_Threshold_7_MASK 0xffff0000 - -/// SMUx5B -typedef union { - struct { ///< - UINT32 Threshold_6:16; ///< - UINT32 Threshold_7:16; ///< - } Field; ///< - UINT32 Value; ///< -} SMUx5B_STRUCT; - -// **** SMUx5D Register Definition **** -// Address -#define SMUx5D_ADDRESS 0x5d - -// Type -#define SMUx5D_TYPE TYPE_SMU -// Field Data -#define SMUx5D_Threshold_8_OFFSET 0 -#define SMUx5D_Threshold_8_WIDTH 16 -#define SMUx5D_Threshold_8_MASK 0xffff -#define SMUx5D_Threshold_9_OFFSET 16 -#define SMUx5D_Threshold_9_WIDTH 16 -#define SMUx5D_Threshold_9_MASK 0xffff0000 - -/// SMUx5D -typedef union { - struct { ///< - UINT32 Threshold_8:16; ///< - UINT32 Threshold_9:16; ///< - } Field; ///< - UINT32 Value; ///< -} SMUx5D_STRUCT; - -// **** SMUx6F Register Definition **** -// Address -#define SMUx6F_ADDRESS 0x6f - -// Type -#define SMUx6F_TYPE TYPE_SMU -// Field Data -#define SMUx6F_OnDelay_OFFSET 0 -#define SMUx6F_OnDelay_WIDTH 4 -#define SMUx6F_OnDelay_MASK 0xf -#define SMUx6F_OffDelay_OFFSET 4 -#define SMUx6F_OffDelay_WIDTH 8 -#define SMUx6F_OffDelay_MASK 0xff0 -#define SMUx6F_Reserved_20_12_OFFSET 12 -#define SMUx6F_Reserved_20_12_WIDTH 9 -#define SMUx6F_Reserved_20_12_MASK 0x1ff000 -#define SMUx6F_RampDis0_OFFSET 21 -#define SMUx6F_RampDis0_WIDTH 1 -#define SMUx6F_RampDis0_MASK 0x200000 -#define SMUx6F_RampDisReg_OFFSET 22 -#define SMUx6F_RampDisReg_WIDTH 1 -#define SMUx6F_RampDisReg_MASK 0x400000 -#define SMUx6F_Reserved_31_23_OFFSET 23 -#define SMUx6F_Reserved_31_23_WIDTH 9 -#define SMUx6F_Reserved_31_23_MASK 0xff800000 - -/// SMUx6F -typedef union { - struct { ///< - UINT32 OnDelay:4 ; ///< - UINT32 OffDelay:8 ; ///< - UINT32 Reserved_20_12:9 ; ///< - UINT32 RampDis0:1 ; ///< - UINT32 RampDisReg:1 ; ///< - UINT32 Reserved_31_23:9 ; ///< - } Field; ///< - UINT32 Value; ///< -} SMUx6F_STRUCT; - -// **** SMUx71 Register Definition **** -// Address -#define SMUx71_ADDRESS 0x71 - -// Type -#define SMUx71_TYPE TYPE_SMU -// Field Data -#define SMUx71_OnDelay_OFFSET 0 -#define SMUx71_OnDelay_WIDTH 4 -#define SMUx71_OnDelay_MASK 0xf -#define SMUx71_OffDelay_OFFSET 4 -#define SMUx71_OffDelay_WIDTH 8 -#define SMUx71_OffDelay_MASK 0xff0 -#define SMUx71_Reserved_19_12_OFFSET 12 -#define SMUx71_Reserved_19_12_WIDTH 8 -#define SMUx71_Reserved_19_12_MASK 0xff000 -#define SMUx71_RampDis1_OFFSET 20 -#define SMUx71_RampDis1_WIDTH 1 -#define SMUx71_RampDis1_MASK 0x100000 -#define SMUx71_RampDis0_OFFSET 21 -#define SMUx71_RampDis0_WIDTH 1 -#define SMUx71_RampDis0_MASK 0x200000 -#define SMUx71_RampDisReg_OFFSET 22 -#define SMUx71_RampDisReg_WIDTH 1 -#define SMUx71_RampDisReg_MASK 0x400000 -#define SMUx71_Reserved_31_23_OFFSET 23 -#define SMUx71_Reserved_31_23_WIDTH 9 -#define SMUx71_Reserved_31_23_MASK 0xff800000 - -/// SMUx71 -typedef union { - struct { ///< - UINT32 OnDelay:4 ; ///< - UINT32 OffDelay:8 ; ///< - UINT32 Reserved_19_12:8 ; ///< - UINT32 RampDis1:1 ; ///< - UINT32 RampDis0:1 ; ///< - UINT32 RampDisReg:1 ; ///< - UINT32 Reserved_31_23:9 ; ///< - } Field; ///< - UINT32 Value; ///< -} SMUx71_STRUCT; - -// **** SMUx73 Register Definition **** -// Address -#define SMUx73_ADDRESS 0x73 - -// Type -#define SMUx73_TYPE TYPE_SMU -// Field Data -#define SMUx73_DisLclkGating_OFFSET 0 -#define SMUx73_DisLclkGating_WIDTH 1 -#define SMUx73_DisLclkGating_MASK 0x1 -#define SMUx73_DisSclkGating_OFFSET 1 -#define SMUx73_DisSclkGating_WIDTH 1 -#define SMUx73_DisSclkGating_MASK 0x2 -#define SMUx73_Reserved_15_2_OFFSET 2 -#define SMUx73_Reserved_15_2_WIDTH 14 -#define SMUx73_Reserved_15_2_MASK 0xfffc - -/// SMUx73 -typedef union { - struct { ///< - UINT32 DisLclkGating:1 ; ///< - UINT32 DisSclkGating:1 ; ///< - UINT32 Reserved_15_2:14; ///< - } Field; ///< - UINT32 Value; ///< -} SMUx73_STRUCT; - -// **** MSRC001_001A Register Definition **** -// Address -#define MSRC001_001A_ADDRESS 0xc001001a - -// Type -#define MSRC001_001A_TYPE TYPE_MSR -// Field Data -#define MSRC001_001A_RAZ_22_0_OFFSET 0 -#define MSRC001_001A_RAZ_22_0_WIDTH 23 -#define MSRC001_001A_RAZ_22_0_MASK 0x7fffff -#define MSRC001_001A_TOM_39_23__OFFSET 23 -#define MSRC001_001A_TOM_39_23__WIDTH 17 -#define MSRC001_001A_TOM_39_23__MASK 0xffff800000 -#define MSRC001_001A_MBZ_47_40_OFFSET 40 -#define MSRC001_001A_MBZ_47_40_WIDTH 8 -#define MSRC001_001A_MBZ_47_40_MASK 0xff0000000000 -#define MSRC001_001A_RAZ_63_48_OFFSET 48 -#define MSRC001_001A_RAZ_63_48_WIDTH 16 -#define MSRC001_001A_RAZ_63_48_MASK 0xffff000000000000 - -/// MSRC001_001A -typedef union { - struct { ///< - UINT64 RAZ_22_0:23; ///< - UINT64 TOM_39_23_:17; ///< - UINT64 MBZ_47_40:8 ; ///< - UINT64 RAZ_63_48:16; ///< - } Field; ///< - UINT64 Value; ///< -} MSRC001_001A_STRUCT; - - -// **** FCRxFF30_0AE6(GMMx2B98) Register Definition **** -// Address -#define FCRxFF30_0AE6_ADDRESS 0xff300AE6 - -// Field Data -#define FCRxFF30_0AE6_RengExecuteNonsecureStartPtr_OFFSET 0 -#define FCRxFF30_0AE6_RengExecuteNonsecureStartPtr_WIDTH 10 -#define FCRxFF30_0AE6_RengExecuteNowMode_OFFSET 10 -#define FCRxFF30_0AE6_RengExecuteNowMode_WIDTH 1 -#define FCRxFF30_0AE6_RengExecuteOnRegUpdate_OFFSET 11 -#define FCRxFF30_0AE6_RengExecuteOnRegUpdate_WIDTH 1 -#define FCRxFF30_0AE6_RengSrbmCreditsMcd_OFFSET 12 -#define FCRxFF30_0AE6_RengSrbmCreditsMcd_WIDTH 4 -#define FCRxFF30_0AE6_StctrlStutterEn_OFFSET 16 -#define FCRxFF30_0AE6_StctrlStutterEn_WIDTH 1 -#define FCRxFF30_0AE6_StctrlGmcIdleThreshold_OFFSET 17 -#define FCRxFF30_0AE6_StctrlGmcIdleThreshold_WIDTH 2 -#define FCRxFF30_0AE6_StctrlSrbmIdleThreshold_OFFSET 19 -#define FCRxFF30_0AE6_StctrlSrbmIdleThreshold_WIDTH 2 -#define FCRxFF30_0AE6_StctrlIgnorePreSr_OFFSET 21 -#define FCRxFF30_0AE6_StctrlIgnorePreSr_WIDTH 1 -#define FCRxFF30_0AE6_StctrlIgnoreAllowStop_OFFSET 22 -#define FCRxFF30_0AE6_StctrlIgnoreAllowStop_WIDTH 1 -#define FCRxFF30_0AE6_StctrlIgnoreDramOffline_OFFSET 23 -#define FCRxFF30_0AE6_StctrlIgnoreDramOffline_WIDTH 1 -#define FCRxFF30_0AE6_StctrlIgnoreProtectionFault_OFFSET 24 -#define FCRxFF30_0AE6_StctrlIgnoreProtectionFault_WIDTH 1 -#define FCRxFF30_0AE6_StctrlDisableAllowSr_OFFSET 25 -#define FCRxFF30_0AE6_StctrlDisableAllowSr_WIDTH 1 -#define FCRxFF30_0AE6_StctrlDisableGmcOffline_OFFSET 26 -#define FCRxFF30_0AE6_StctrlDisableGmcOffline_WIDTH 1 -#define FCRxFF30_0AE6_CriticalRegsLock_OFFSET 27 -#define FCRxFF30_0AE6_CriticalRegsLock_WIDTH 1 -#define FCRxFF30_0AE6_SmuExecuteOnRegUpdate_OFFSET 28 -#define FCRxFF30_0AE6_SmuExecuteOnRegUpdate_WIDTH 1 -#define FCRxFF30_0AE6_AllowDeepSleepMode_OFFSET 29 -#define FCRxFF30_0AE6_AllowDeepSleepMode_WIDTH 2 -#define FCRxFF30_0AE6_Reserved_31_31_OFFSET 31 -#define FCRxFF30_0AE6_Reserved_31_31_WIDTH 1 - -/// FCRxFF30_0AE6 -typedef union { - struct { ///< - UINT32 RengExecuteNonsecureStartPtr:10; ///< - UINT32 RengExecuteNowMode:1 ; ///< - UINT32 RengExecuteOnRegUpdate:1 ; ///< - UINT32 RengSrbmCreditsMcd:4 ; ///< - UINT32 StctrlStutterEn:1 ; ///< - UINT32 StctrlGmcIdleThreshold:2 ; ///< - UINT32 StctrlSrbmIdleThreshold:2 ; ///< - UINT32 StctrlIgnorePreSr:1 ; ///< - UINT32 StctrlIgnoreAllowStop:1 ; ///< - UINT32 StctrlIgnoreDramOffline:1 ; ///< - UINT32 StctrlIgnoreProtectionFault:1 ; ///< - UINT32 StctrlDisableAllowSr:1 ; ///< - UINT32 StctrlDisableGmcOffline:1 ; ///< - UINT32 CriticalRegsLock:1 ; ///< - UINT32 SmuExecuteOnRegUpdate:1 ; ///< - UINT32 AllowDeepSleepMode:2 ; ///< - UINT32 Reserved_31_31:1 ; ///< - } Field; - UINT32 Value; -} FCRxFF30_0AE6_STRUCT; - -// **** FCRxFF30_0134(GMMx4D0) Register Definition **** -// Address -#define FCRxFF30_0134_ADDRESS 0xff300134 - -// Field Data -#define FCRxFF30_0134_DispclkDccgGateDisable_OFFSET 0 -#define FCRxFF30_0134_DispclkDccgGateDisable_WIDTH 1 -#define FCRxFF30_0134_DispclkDccgGateDisable_MASK 0x1 -#define FCRxFF30_0134_DispclkRDccgGateDisable_OFFSET 1 -#define FCRxFF30_0134_DispclkRDccgGateDisable_WIDTH 1 -#define FCRxFF30_0134_DispclkRDccgGateDisable_MASK 0x2 -#define FCRxFF30_0134_SclkGateDisable_OFFSET 2 -#define FCRxFF30_0134_SclkGateDisable_WIDTH 1 -#define FCRxFF30_0134_SclkGateDisable_MASK 0x4 -#define FCRxFF30_0134_Reserved_7_3_OFFSET 3 -#define FCRxFF30_0134_Reserved_7_3_WIDTH 5 -#define FCRxFF30_0134_Reserved_7_3_MASK 0xf8 -#define FCRxFF30_0134_SymclkaGateDisable_OFFSET 8 -#define FCRxFF30_0134_SymclkaGateDisable_WIDTH 1 -#define FCRxFF30_0134_SymclkaGateDisable_MASK 0x100 -#define FCRxFF30_0134_SymclkbGateDisable_OFFSET 9 -#define FCRxFF30_0134_SymclkbGateDisable_WIDTH 1 -#define FCRxFF30_0134_SymclkbGateDisable_MASK 0x200 -#define FCRxFF30_0134_Reserved_31_10_OFFSET 10 -#define FCRxFF30_0134_Reserved_31_10_WIDTH 22 -#define FCRxFF30_0134_Reserved_31_10_MASK 0xfffffc00 - -/// FCRxFF30_0134 -typedef union { - struct { ///< - UINT32 DispclkDccgGateDisable:1 ; ///< - UINT32 DispclkRDccgGateDisable:1 ; ///< - UINT32 SclkGateDisable:1 ; ///< - UINT32 Reserved_7_3:5 ; ///< - UINT32 SymclkaGateDisable:1 ; ///< - UINT32 SymclkbGateDisable:1 ; ///< - UINT32 Reserved_31_10:22; ///< - } Field; ///< - UINT32 Value; ///< -} FCRxFF30_0134_STRUCT; - -// **** FCRxFF30_1B7C(GMMx6DF0) Register Definition **** -// Address -#define FCRxFF30_1B7C_ADDRESS 0xff301B7C - -// Field Data -#define FCRxFF30_1B7C_Reserved_3_0_OFFSET 0 -#define FCRxFF30_1B7C_Reserved_3_0_WIDTH 4 -#define FCRxFF30_1B7C_Reserved_3_0_MASK 0xf -#define FCRxFF30_1B7C_CrtcDispclkRDcfeGateDisable_OFFSET 4 -#define FCRxFF30_1B7C_CrtcDispclkRDcfeGateDisable_WIDTH 1 -#define FCRxFF30_1B7C_CrtcDispclkRDcfeGateDisable_MASK 0x10 -#define FCRxFF30_1B7C_Reserved_7_5_OFFSET 5 -#define FCRxFF30_1B7C_Reserved_7_5_WIDTH 3 -#define FCRxFF30_1B7C_Reserved_7_5_MASK 0xe0 -#define FCRxFF30_1B7C_CrtcDispclkGDcpGateDisable_OFFSET 8 -#define FCRxFF30_1B7C_CrtcDispclkGDcpGateDisable_WIDTH 1 -#define FCRxFF30_1B7C_CrtcDispclkGDcpGateDisable_MASK 0x100 -#define FCRxFF30_1B7C_Reserved_11_9_OFFSET 9 -#define FCRxFF30_1B7C_Reserved_11_9_WIDTH 3 -#define FCRxFF30_1B7C_Reserved_11_9_MASK 0xe00 -#define FCRxFF30_1B7C_CrtcDispclkGSclGateDisable_OFFSET 12 -#define FCRxFF30_1B7C_CrtcDispclkGSclGateDisable_WIDTH 1 -#define FCRxFF30_1B7C_CrtcDispclkGSclGateDisable_MASK 0x1000 -#define FCRxFF30_1B7C_Reserved_31_13_OFFSET 13 -#define FCRxFF30_1B7C_Reserved_31_13_WIDTH 19 -#define FCRxFF30_1B7C_Reserved_31_13_MASK 0xffffe000 - -/// FCRxFF30_1B7C -typedef union { - struct { ///< - UINT32 Reserved_3_0:4 ; ///< - UINT32 CrtcDispclkRDcfeGateDisable:1 ; ///< - UINT32 Reserved_7_5:3 ; ///< - UINT32 CrtcDispclkGDcpGateDisable:1 ; ///< - UINT32 Reserved_11_9:3 ; ///< - UINT32 CrtcDispclkGSclGateDisable:1 ; ///< - UINT32 Reserved_31_13:19; ///< - } Field; ///< - UINT32 Value; ///< -} FCRxFF30_1B7C_STRUCT; - -// **** FCRxFF30_1E7C(GMMx79F0) Register Definition **** -// Address -#define FCRxFF30_1E7C_ADDRESS 0xff301E7C - -// Field Data -#define FCRxFF30_1E7C_Reserved_3_0_OFFSET 0 -#define FCRxFF30_1E7C_Reserved_3_0_WIDTH 4 -#define FCRxFF30_1E7C_Reserved_3_0_MASK 0xf -#define FCRxFF30_1E7C_CrtcDispclkRDcfeGateDisable_OFFSET 4 -#define FCRxFF30_1E7C_CrtcDispclkRDcfeGateDisable_WIDTH 1 -#define FCRxFF30_1E7C_CrtcDispclkRDcfeGateDisable_MASK 0x10 -#define FCRxFF30_1E7C_Reserved_7_5_OFFSET 5 -#define FCRxFF30_1E7C_Reserved_7_5_WIDTH 3 -#define FCRxFF30_1E7C_Reserved_7_5_MASK 0xe0 -#define FCRxFF30_1E7C_CrtcDispclkGDcpGateDisable_OFFSET 8 -#define FCRxFF30_1E7C_CrtcDispclkGDcpGateDisable_WIDTH 1 -#define FCRxFF30_1E7C_CrtcDispclkGDcpGateDisable_MASK 0x100 -#define FCRxFF30_1E7C_Reserved_11_9_OFFSET 9 -#define FCRxFF30_1E7C_Reserved_11_9_WIDTH 3 -#define FCRxFF30_1E7C_Reserved_11_9_MASK 0xe00 -#define FCRxFF30_1E7C_CrtcDispclkGSclGateDisable_OFFSET 12 -#define FCRxFF30_1E7C_CrtcDispclkGSclGateDisable_WIDTH 1 -#define FCRxFF30_1E7C_CrtcDispclkGSclGateDisable_MASK 0x1000 -#define FCRxFF30_1E7C_Reserved_31_13_OFFSET 13 -#define FCRxFF30_1E7C_Reserved_31_13_WIDTH 19 -#define FCRxFF30_1E7C_Reserved_31_13_MASK 0xffffe000 - -/// FCRxFF30_1E7C -typedef union { - struct { ///< - UINT32 Reserved_3_0:4 ; ///< - UINT32 CrtcDispclkRDcfeGateDisable:1 ; ///< - UINT32 Reserved_7_5:3 ; ///< - UINT32 CrtcDispclkGDcpGateDisable:1 ; ///< - UINT32 Reserved_11_9:3 ; ///< - UINT32 CrtcDispclkGSclGateDisable:1 ; ///< - UINT32 Reserved_31_13:19; ///< - } Field; ///< - UINT32 Value; ///< -} FCRxFF30_1E7C_STRUCT; - -// **** FCRxFE00_600E Register Definition **** -// Address -#define FCRxFE00_600E_ADDRESS 0xfe00600e - -// Field Data -#define FCRxFE00_600E_MainPllOpFreqIdStartup_OFFSET 0 -#define FCRxFE00_600E_MainPllOpFreqIdStartup_WIDTH 6 -#define FCRxFE00_600E_WrCkDid_OFFSET 10 -#define FCRxFE00_600E_WrCkDid_WIDTH 5 - -/// FCRxFE00_600E -typedef union { - struct { - UINT32 MainPllOpFreqIdStartup:6 ; ///< - UINT32 Reserved:5 ; ///< - UINT32 WrCkDid:5 ; ///< - } Field; - UINT32 Value; -} FCRxFE00_600E_STRUCT; - -// **** SMUx0B_x8498 Register Definition **** -// Address -#define SMUx0B_x8498_ADDRESS 0x8498 - -// Field Data -#define SMUx0B_x8498_ConditionalBF_1_0_OFFSET 0 -#define SMUx0B_x8498_ConditionalBF_1_0_WIDTH 2 -#define SMUx0B_x8498_ConditionalBF_1_0_MASK 0x3 -#define SMUx0B_x8498_ConditionalBF_3_2_OFFSET 2 -#define SMUx0B_x8498_ConditionalBF_3_2_WIDTH 2 -#define SMUx0B_x8498_ConditionalBF_3_2_MASK 0xc -#define SMUx0B_x8498_Reserved_7_4_OFFSET 4 -#define SMUx0B_x8498_Reserved_7_4_WIDTH 4 -#define SMUx0B_x8498_Reserved_7_4_MASK 0xf0 -#define SMUx0B_x8498_ConditionalBF_9_8_OFFSET 8 -#define SMUx0B_x8498_ConditionalBF_9_8_WIDTH 2 -#define SMUx0B_x8498_ConditionalBF_9_8_MASK 0x300 -#define SMUx0B_x8498_ConditionalBF_11_10_OFFSET 10 -#define SMUx0B_x8498_ConditionalBF_11_10_WIDTH 2 -#define SMUx0B_x8498_ConditionalBF_11_10_MASK 0xc00 -#define SMUx0B_x8498_Reserved_15_12_OFFSET 12 -#define SMUx0B_x8498_Reserved_15_12_WIDTH 4 -#define SMUx0B_x8498_Reserved_15_12_MASK 0xf000 -#define SMUx0B_x8498_BaseVid_5_OFFSET 16 -#define SMUx0B_x8498_BaseVid_5_WIDTH 2 -#define SMUx0B_x8498_BaseVid_5_MASK 0x30000 -#define SMUx0B_x8498_TolExcdVid_5_OFFSET 18 -#define SMUx0B_x8498_TolExcdVid_5_WIDTH 2 -#define SMUx0B_x8498_TolExcdVid_5_MASK 0xc0000 -#define SMUx0B_x8498_Reserved_23_20_OFFSET 20 -#define SMUx0B_x8498_Reserved_23_20_WIDTH 4 -#define SMUx0B_x8498_Reserved_23_20_MASK 0xf00000 -#define SMUx0B_x8498_BaseVid_4_OFFSET 24 -#define SMUx0B_x8498_BaseVid_4_WIDTH 2 -#define SMUx0B_x8498_BaseVid_4_MASK 0x3000000 -#define SMUx0B_x8498_TolExcdVid_4_OFFSET 26 -#define SMUx0B_x8498_TolExcdVid_4_WIDTH 2 -#define SMUx0B_x8498_TolExcdVid_4_MASK 0xc000000 -#define SMUx0B_x8498_Reserved_31_28_OFFSET 28 -#define SMUx0B_x8498_Reserved_31_28_WIDTH 4 -#define SMUx0B_x8498_Reserved_31_28_MASK 0xf0000000 - -/// SMUx0B_x8498 -typedef union { - struct { ///< - UINT32 ConditionalBF_1_0:2 ; ///< - UINT32 ConditionalBF_3_2:2 ; ///< - UINT32 Reserved_7_4:4 ; ///< - UINT32 ConditionalBF_9_8:2 ; ///< - UINT32 ConditionalBF_11_10:2 ; ///< - UINT32 Reserved_15_12:4 ; ///< - UINT32 BaseVid_5:2 ; ///< - UINT32 TolExcdVid_5:2 ; ///< - UINT32 Reserved_23_20:4 ; ///< - UINT32 BaseVid_4:2 ; ///< - UINT32 TolExcdVid_4:2 ; ///< - UINT32 Reserved_31_28:4 ; ///< - } Field; ///< - UINT32 Value; ///< -} SMUx0B_x8498_STRUCT; - -// **** D0F0xE4_WRAP_8013 Register Definition **** -// Address -#define D0F0xE4_WRAP_8013_ADDRESS 0x8013 - -// Field Data -#define D0F0xE4_WRAP_8013_MasterPciePllA_OFFSET 0 -#define D0F0xE4_WRAP_8013_MasterPciePllA_WIDTH 1 -#define D0F0xE4_WRAP_8013_MasterPciePllA_MASK 0x1 -#define D0F0xE4_WRAP_8013_Reserved_1_1_OFFSET 1 -#define D0F0xE4_WRAP_8013_Reserved_1_1_WIDTH 1 -#define D0F0xE4_WRAP_8013_Reserved_1_1_MASK 0x2 -#define D0F0xE4_WRAP_8013_Reserved_2_2_OFFSET 2 -#define D0F0xE4_WRAP_8013_Reserved_2_2_WIDTH 1 -#define D0F0xE4_WRAP_8013_Reserved_2_2_MASK 0x4 -#define D0F0xE4_WRAP_8013_Reserved_3_3_OFFSET 3 -#define D0F0xE4_WRAP_8013_Reserved_3_3_WIDTH 1 -#define D0F0xE4_WRAP_8013_Reserved_3_3_MASK 0x8 -#define D0F0xE4_WRAP_8013_ClkDividerResetOverrideA_OFFSET 4 -#define D0F0xE4_WRAP_8013_ClkDividerResetOverrideA_WIDTH 1 -#define D0F0xE4_WRAP_8013_ClkDividerResetOverrideA_MASK 0x10 -#define D0F0xE4_WRAP_8013_Reserved_5_5_OFFSET 5 -#define D0F0xE4_WRAP_8013_Reserved_5_5_WIDTH 1 -#define D0F0xE4_WRAP_8013_Reserved_5_5_MASK 0x20 -#define D0F0xE4_WRAP_8013_Reserved_6_6_OFFSET 6 -#define D0F0xE4_WRAP_8013_Reserved_6_6_WIDTH 1 -#define D0F0xE4_WRAP_8013_Reserved_6_6_MASK 0x40 -#define D0F0xE4_WRAP_8013_Reserved_7_7_OFFSET 7 -#define D0F0xE4_WRAP_8013_Reserved_7_7_WIDTH 1 -#define D0F0xE4_WRAP_8013_Reserved_7_7_MASK 0x80 -#define D0F0xE4_WRAP_8013_TxclkSelCoreOverride_OFFSET 8 -#define D0F0xE4_WRAP_8013_TxclkSelCoreOverride_WIDTH 1 -#define D0F0xE4_WRAP_8013_TxclkSelCoreOverride_MASK 0x100 -#define D0F0xE4_WRAP_8013_TxclkSelPifAOverride_OFFSET 9 -#define D0F0xE4_WRAP_8013_TxclkSelPifAOverride_WIDTH 1 -#define D0F0xE4_WRAP_8013_TxclkSelPifAOverride_MASK 0x200 -#define D0F0xE4_WRAP_8013_Reserved_10_10_OFFSET 10 -#define D0F0xE4_WRAP_8013_Reserved_10_10_WIDTH 1 -#define D0F0xE4_WRAP_8013_Reserved_10_10_MASK 0x400 -#define D0F0xE4_WRAP_8013_Reserved_11_11_OFFSET 11 -#define D0F0xE4_WRAP_8013_Reserved_11_11_WIDTH 1 -#define D0F0xE4_WRAP_8013_Reserved_11_11_MASK 0x800 -#define D0F0xE4_WRAP_8013_Reserved_12_12_OFFSET 12 -#define D0F0xE4_WRAP_8013_Reserved_12_12_WIDTH 1 -#define D0F0xE4_WRAP_8013_Reserved_12_12_MASK 0x1000 -#define D0F0xE4_WRAP_8013_Reserved_15_13_OFFSET 13 -#define D0F0xE4_WRAP_8013_Reserved_15_13_WIDTH 3 -#define D0F0xE4_WRAP_8013_Reserved_15_13_MASK 0xe000 -#define D0F0xE4_WRAP_8013_Reserved_16_16_OFFSET 16 -#define D0F0xE4_WRAP_8013_Reserved_16_16_WIDTH 1 -#define D0F0xE4_WRAP_8013_Reserved_16_16_MASK 0x10000 -#define D0F0xE4_WRAP_8013_Reserved_19_17_OFFSET 17 -#define D0F0xE4_WRAP_8013_Reserved_19_17_WIDTH 3 -#define D0F0xE4_WRAP_8013_Reserved_19_17_MASK 0xe0000 -#define D0F0xE4_WRAP_8013_Reserved_20_20_OFFSET 20 -#define D0F0xE4_WRAP_8013_Reserved_20_20_WIDTH 1 -#define D0F0xE4_WRAP_8013_Reserved_20_20_MASK 0x100000 -#define D0F0xE4_WRAP_8013_Reserved_31_21_OFFSET 21 -#define D0F0xE4_WRAP_8013_Reserved_31_21_WIDTH 11 -#define D0F0xE4_WRAP_8013_Reserved_31_21_MASK 0xffe00000 - -/// D0F0xE4_WRAP_8013 -typedef union { - struct { ///< - UINT32 MasterPciePllA:1 ; ///< - UINT32 MasterPciePllB:1 ; ///< - UINT32 MasterPciePllC:1 ; ///< - UINT32 MasterPciePllD:1 ; ///< - UINT32 ClkDividerResetOverrideA:1 ; ///< - UINT32 Reserved_5_5:1 ; ///< - UINT32 Reserved_6_6:1 ; ///< - UINT32 Reserved_7_7:1 ; ///< - UINT32 TxclkSelCoreOverride:1 ; ///< - UINT32 TxclkSelPifAOverride:1 ; ///< - UINT32 Reserved_10_10:1 ; ///< - UINT32 Reserved_11_11:1 ; ///< - UINT32 Reserved_12_12:1 ; ///< - UINT32 Reserved_15_13:3 ; ///< - UINT32 Reserved_16_16:1 ; ///< - UINT32 Reserved_19_17:3 ; ///< - UINT32 Reserved_20_20:1 ; ///< - UINT32 Reserved_31_21:11; ///< - } Field; ///< - UINT32 Value; ///< -} D0F0xE4_WRAP_8013_STRUCT; - -// **** D0F0xE4_WRAP_8014 Register Definition **** -// Address -#define D0F0xE4_WRAP_8014_ADDRESS 0x8014 - -// Field Data -#define D0F0xE4_WRAP_8014_TxclkPermGateEnable_OFFSET 0 -#define D0F0xE4_WRAP_8014_TxclkPermGateEnable_WIDTH 1 -#define D0F0xE4_WRAP_8014_TxclkPermGateEnable_MASK 0x1 -#define D0F0xE4_WRAP_8014_TxclkPrbsGateEnable_OFFSET 1 -#define D0F0xE4_WRAP_8014_TxclkPrbsGateEnable_WIDTH 1 -#define D0F0xE4_WRAP_8014_TxclkPrbsGateEnable_MASK 0x2 -#define D0F0xE4_WRAP_8014_Reserved_2_2_OFFSET 2 -#define D0F0xE4_WRAP_8014_Reserved_2_2_WIDTH 1 -#define D0F0xE4_WRAP_8014_Reserved_2_2_MASK 0x4 -#define D0F0xE4_WRAP_8014_Reserved_3_3_OFFSET 3 -#define D0F0xE4_WRAP_8014_Reserved_3_3_WIDTH 1 -#define D0F0xE4_WRAP_8014_Reserved_3_3_MASK 0x8 -#define D0F0xE4_WRAP_8014_Reserved_4_4_OFFSET 4 -#define D0F0xE4_WRAP_8014_Reserved_4_4_WIDTH 1 -#define D0F0xE4_WRAP_8014_Reserved_4_4_MASK 0x10 -#define D0F0xE4_WRAP_8014_Reserved_5_5_OFFSET 5 -#define D0F0xE4_WRAP_8014_Reserved_5_5_WIDTH 1 -#define D0F0xE4_WRAP_8014_Reserved_5_5_MASK 0x20 -#define D0F0xE4_WRAP_8014_Reserved_6_6_OFFSET 6 -#define D0F0xE4_WRAP_8014_Reserved_6_6_WIDTH 1 -#define D0F0xE4_WRAP_8014_Reserved_6_6_MASK 0x40 -#define D0F0xE4_WRAP_8014_Reserved_7_7_OFFSET 7 -#define D0F0xE4_WRAP_8014_Reserved_7_7_WIDTH 1 -#define D0F0xE4_WRAP_8014_Reserved_7_7_MASK 0x80 -#define D0F0xE4_WRAP_8014_Reserved_8_8_OFFSET 8 -#define D0F0xE4_WRAP_8014_Reserved_8_8_WIDTH 1 -#define D0F0xE4_WRAP_8014_Reserved_8_8_MASK 0x100 -#define D0F0xE4_WRAP_8014_Reserved_9_9_OFFSET 9 -#define D0F0xE4_WRAP_8014_Reserved_9_9_WIDTH 1 -#define D0F0xE4_WRAP_8014_Reserved_9_9_MASK 0x200 -#define D0F0xE4_WRAP_8014_Reserved_10_10_OFFSET 10 -#define D0F0xE4_WRAP_8014_Reserved_10_10_WIDTH 1 -#define D0F0xE4_WRAP_8014_Reserved_10_10_MASK 0x400 -#define D0F0xE4_WRAP_8014_Reserved_11_11_OFFSET 11 -#define D0F0xE4_WRAP_8014_Reserved_11_11_WIDTH 1 -#define D0F0xE4_WRAP_8014_Reserved_11_11_MASK 0x800 -#define D0F0xE4_WRAP_8014_PcieGatePifA1xEnable_OFFSET 12 -#define D0F0xE4_WRAP_8014_PcieGatePifA1xEnable_WIDTH 1 -#define D0F0xE4_WRAP_8014_PcieGatePifA1xEnable_MASK 0x1000 -#define D0F0xE4_WRAP_8014_Reserved_13_13_OFFSET 13 -#define D0F0xE4_WRAP_8014_Reserved_13_13_WIDTH 1 -#define D0F0xE4_WRAP_8014_Reserved_13_13_MASK 0x2000 -#define D0F0xE4_WRAP_8014_Reserved_14_14_OFFSET 14 -#define D0F0xE4_WRAP_8014_Reserved_14_14_WIDTH 1 -#define D0F0xE4_WRAP_8014_Reserved_14_14_MASK 0x4000 -#define D0F0xE4_WRAP_8014_Reserved_15_15_OFFSET 15 -#define D0F0xE4_WRAP_8014_Reserved_15_15_WIDTH 1 -#define D0F0xE4_WRAP_8014_Reserved_15_15_MASK 0x8000 -#define D0F0xE4_WRAP_8014_PcieGatePifA2p5xEnable_OFFSET 16 -#define D0F0xE4_WRAP_8014_PcieGatePifA2p5xEnable_WIDTH 1 -#define D0F0xE4_WRAP_8014_PcieGatePifA2p5xEnable_MASK 0x10000 -#define D0F0xE4_WRAP_8014_Reserved_17_17_OFFSET 17 -#define D0F0xE4_WRAP_8014_Reserved_17_17_WIDTH 1 -#define D0F0xE4_WRAP_8014_Reserved_17_17_MASK 0x20000 -#define D0F0xE4_WRAP_8014_Reserved_18_18_OFFSET 18 -#define D0F0xE4_WRAP_8014_Reserved_18_18_WIDTH 1 -#define D0F0xE4_WRAP_8014_Reserved_18_18_MASK 0x40000 -#define D0F0xE4_WRAP_8014_Reserved_19_19_OFFSET 19 -#define D0F0xE4_WRAP_8014_Reserved_19_19_WIDTH 1 -#define D0F0xE4_WRAP_8014_Reserved_19_19_MASK 0x80000 -#define D0F0xE4_WRAP_8014_TxclkPermGateOnlyWhenPllPwrDn_OFFSET 20 -#define D0F0xE4_WRAP_8014_TxclkPermGateOnlyWhenPllPwrDn_WIDTH 1 -#define D0F0xE4_WRAP_8014_TxclkPermGateOnlyWhenPllPwrDn_MASK 0x100000 -#define D0F0xE4_WRAP_8014_Reserved_31_21_OFFSET 21 -#define D0F0xE4_WRAP_8014_Reserved_31_21_WIDTH 11 -#define D0F0xE4_WRAP_8014_Reserved_31_21_MASK 0xffe00000 - -/// D0F0xE4_WRAP_8014 -typedef union { - struct { - UINT32 TxclkPermGateEnable:1 ; ///< - UINT32 TxclkPrbsGateEnable:1 ; ///< - UINT32 DdiGatePifA1xEnable:1 ; ///< - UINT32 DdiGatePifB1xEnable:1 ; ///< - UINT32 DdiGatePifC1xEnable:1 ; ///< - UINT32 DdiGatePifD1xEnable:1 ; ///< - UINT32 DdiGateDigAEnable:1 ; ///< - UINT32 DdiGateDigBEnable:1 ; ///< - UINT32 DdiGatePifA2p5xEnable:1 ; ///< - UINT32 DdiGatePifB2p5xEnable:1 ; ///< - UINT32 DdiGatePifC2p5xEnable:1 ; ///< - UINT32 DdiGatePifD2p5xEnable:1 ; ///< - UINT32 PcieGatePifA1xEnable:1 ; ///< - UINT32 PcieGatePifB1xEnable:1 ; ///< - UINT32 PcieGatePifC1xEnable:1 ; ///< - UINT32 PcieGatePifD1xEnable:1 ; ///< - UINT32 PcieGatePifA2p5xEnable:1 ; ///< - UINT32 PcieGatePifB2p5xEnable:1 ; ///< - UINT32 PcieGatePifC2p5xEnable:1 ; ///< - UINT32 PcieGatePifD2p5xEnable:1 ; ///< - UINT32 TxclkPermGateOnlyWhenPllPwrDn:1 ; ///< - UINT32 Reserved_31_21:11; ///< - } Field; ///< - UINT32 Value; ///< -} D0F0xE4_WRAP_8014_STRUCT; - -// **** SMUx0B_x85B0 Register Definition **** -// Address -#define SMUx0B_x85B0_ADDRESS 0x85B0 - - -// **** SMUx0B_x85D0 Register Definition **** -// Address -#define SMUx0B_x85D0_ADDRESS 0x85D0 - -// **** SMUx0B_x842C Register Definition **** -// Address -#define SMUx0B_x842C_ADDRESS 0x842C - -// **** GMMx6124 Register Definition **** -// Address -#define GMMx6124_ADDRESS 0x6124 - -// **** GMMx6124 Register Definition **** -// Address -#define GMMx6124_ADDRESS 0x6124 - -// Type -#define GMMx6124_TYPE TYPE_GMM -// Field Data -#define GMMx6124_DoutScratch_OFFSET 0 -#define GMMx6124_DoutScratch_WIDTH 32 -#define GMMx6124_DoutScratch_MASK 0xffffffff - -// **** D0F0x64_x51 Register Definition **** -// Address -#define D0F0x64_x51_ADDRESS 0x51 - -// Type -#define D0F0x64_x51_TYPE TYPE_D0F0x64 -// Field Data -#define D0F0x64_x51_Reserved_2_0_OFFSET 0 -#define D0F0x64_x51_Reserved_2_0_WIDTH 3 -#define D0F0x64_x51_Reserved_2_0_MASK 0x7 -#define D0F0x64_x51_P2pDis_OFFSET 3 -#define D0F0x64_x51_P2pDis_WIDTH 1 -#define D0F0x64_x51_P2pDis_MASK 0x8 -#define D0F0x64_x51_Reserved_15_4_OFFSET 4 -#define D0F0x64_x51_Reserved_15_4_WIDTH 12 -#define D0F0x64_x51_Reserved_15_4_MASK 0xfff0 -#define D0F0x64_x51_ExtDevPlug_OFFSET 16 -#define D0F0x64_x51_ExtDevPlug_WIDTH 1 -#define D0F0x64_x51_ExtDevPlug_MASK 0x10000 -#define D0F0x64_x51_ExtDevCrsEn_OFFSET 17 -#define D0F0x64_x51_ExtDevCrsEn_WIDTH 1 -#define D0F0x64_x51_ExtDevCrsEn_MASK 0x20000 -#define D0F0x64_x51_CrsEn_OFFSET 18 -#define D0F0x64_x51_CrsEn_WIDTH 1 -#define D0F0x64_x51_CrsEn_MASK 0x40000 -#define D0F0x64_x51_IntSelMode_OFFSET 19 -#define D0F0x64_x51_IntSelMode_WIDTH 1 -#define D0F0x64_x51_IntSelMode_MASK 0x80000 -#define D0F0x64_x51_SetPowEn_OFFSET 20 -#define D0F0x64_x51_SetPowEn_WIDTH 1 -#define D0F0x64_x51_SetPowEn_MASK 0x100000 -#define D0F0x64_x51_Reserved_31_21_OFFSET 21 -#define D0F0x64_x51_Reserved_31_21_WIDTH 11 -#define D0F0x64_x51_Reserved_31_21_MASK 0xffe00000 - -/// D0F0x64_x51 -typedef union { - struct { ///< - UINT32 Reserved_2_0:3 ; ///< - UINT32 P2pDis:1 ; ///< - UINT32 Reserved_15_4:12; ///< - UINT32 ExtDevPlug:1 ; ///< - UINT32 ExtDevCrsEn:1 ; ///< - UINT32 CrsEn:1 ; ///< - UINT32 IntSelMode:1 ; ///< - UINT32 SetPowEn:1 ; ///< - UINT32 Reserved_31_21:11; ///< - } Field; ///< - UINT32 Value; ///< -} D0F0x64_x51_STRUCT; - -// **** D0F0xE4_PHY_2002 Register Definition **** -// Address -#define D0F0xE4_PHY_2002_ADDRESS 0x2002 - -// Type -#define D0F0xE4_PHY_2002_TYPE TYPE_D0F0xE4 -// Field Data -#define D0F0xE4_PHY_2002_Reserved_26_0_OFFSET 0 -#define D0F0xE4_PHY_2002_Reserved_26_0_WIDTH 27 -#define D0F0xE4_PHY_2002_Reserved_26_0_MASK 0x7ffffff -#define D0F0xE4_PHY_2002_RoCalEn_OFFSET 27 -#define D0F0xE4_PHY_2002_RoCalEn_WIDTH 1 -#define D0F0xE4_PHY_2002_RoCalEn_MASK 0x8000000 -#define D0F0xE4_PHY_2002_Reserved_30_28_OFFSET 28 -#define D0F0xE4_PHY_2002_Reserved_30_28_WIDTH 3 -#define D0F0xE4_PHY_2002_Reserved_30_28_MASK 0x70000000 -#define D0F0xE4_PHY_2002_IsLc_OFFSET 31 -#define D0F0xE4_PHY_2002_IsLc_WIDTH 1 -#define D0F0xE4_PHY_2002_IsLc_MASK 0x80000000 - -/// D0F0xE4_PHY_2002 -typedef union { - struct { ///< - UINT32 Reserved_26_0:27; ///< - UINT32 RoCalEn:1 ; ///< - UINT32 Reserved_30_28:3 ; ///< - UINT32 IsLc:1 ; ///< - } Field; ///< - UINT32 Value; ///< -} D0F0xE4_PHY_2002_STRUCT; - -// **** D0F0xE4_WRAP_FFF1 Register Definition **** -// Address -#define D0F0xE4_WRAP_FFF1_ADDRESS 0xfff1 - -// Type -#define D0F0xE4_WRAP_FFF1_TYPE TYPE_D0F0xE4 -// Field Data -#define D0F0xE4_WRAP_FFF1_Reserved_5_0_OFFSET 0 -#define D0F0xE4_WRAP_FFF1_Reserved_5_0_WIDTH 6 -#define D0F0xE4_WRAP_FFF1_Reserved_5_0_MASK 0x3f -#define D0F0xE4_WRAP_FFF1_LcSupportGen2_OFFSET 6 -#define D0F0xE4_WRAP_FFF1_LcSupportGen2_WIDTH 1 -#define D0F0xE4_WRAP_FFF1_LcSupportGen2_MASK 0x40 -#define D0F0xE4_WRAP_FFF1_ROSupportGen2_OFFSET 7 -#define D0F0xE4_WRAP_FFF1_ROSupportGen2_WIDTH 1 -#define D0F0xE4_WRAP_FFF1_ROSupportGen2_MASK 0x80 -#define D0F0xE4_WRAP_FFF1_Reserved_31_8_OFFSET 8 -#define D0F0xE4_WRAP_FFF1_Reserved_31_8_WIDTH 24 -#define D0F0xE4_WRAP_FFF1_Reserved_31_8_MASK 0xffffff00 - -/// D0F0xE4_WRAP_FFF1 -typedef union { - struct { ///< - UINT32 Reserved_5_0:6 ; ///< - UINT32 LcSupportGen2:1 ; ///< - UINT32 ROSupportGen2:1 ; ///< - UINT32 Reserved_31_8:24; ///< - } Field; ///< - UINT32 Value; ///< -} D0F0xE4_WRAP_FFF1_STRUCT; - -// **** D0F0xE4_CORE_0020 Register Definition **** -// Address -#define D0F0xE4_CORE_0020_ADDRESS 0x20 - -// Type -#define D0F0xE4_CORE_0020_TYPE TYPE_D0F0xE4 -// Field Data -// Field Data -#define D0F0xE4_CORE_0020_Reserved_8_0_OFFSET 0 -#define D0F0xE4_CORE_0020_Reserved_8_0_WIDTH 9 -#define D0F0xE4_CORE_0020_Reserved_8_0_MASK 0x1ff -#define D0F0xE4_CORE_0020_CiRcOrderingDis_OFFSET 9 -#define D0F0xE4_CORE_0020_CiRcOrderingDis_WIDTH 1 -#define D0F0xE4_CORE_0020_CiRcOrderingDis_MASK 0x200 -#define D0F0xE4_CORE_0020_Reserved_31_10_OFFSET 10 -#define D0F0xE4_CORE_0020_Reserved_31_10_WIDTH 22 -#define D0F0xE4_CORE_0020_Reserved_31_10_MASK 0xfffffc00 - -/// D0F0xE4_CORE_0020 -typedef union { - struct { ///< - UINT32 Reserved_8_0:9 ; ///< - UINT32 CiRcOrderingDis:1 ; ///< - UINT32 Reserved_31_10:22; ///< - } Field; ///< - UINT32 Value; ///< -} D0F0xE4_CORE_0020_STRUCT; - -// **** D0F0xE4_CORE_0010 Register Definition **** -// Address -#define D0F0xE4_CORE_0010_ADDRESS 0x10 - -// Type -#define D0F0xE4_CORE_0010_TYPE TYPE_D0F0xE4 -// Field Data -#define D0F0xE4_CORE_0010_HwInitWrLock_OFFSET 0 -#define D0F0xE4_CORE_0010_HwInitWrLock_WIDTH 1 -#define D0F0xE4_CORE_0010_HwInitWrLock_MASK 0x1 -#define D0F0xE4_CORE_0010_Reserved_8_1_OFFSET 1 -#define D0F0xE4_CORE_0010_Reserved_8_1_WIDTH 8 -#define D0F0xE4_CORE_0010_Reserved_8_1_MASK 0x1fe -#define D0F0xE4_CORE_0010_UmiNpMemWrite_OFFSET 9 -#define D0F0xE4_CORE_0010_UmiNpMemWrite_WIDTH 1 -#define D0F0xE4_CORE_0010_UmiNpMemWrite_MASK 0x200 -#define D0F0xE4_CORE_0010_RxSbAdjPayloadSize_OFFSET 10 -#define D0F0xE4_CORE_0010_RxSbAdjPayloadSize_WIDTH 3 -#define D0F0xE4_CORE_0010_RxSbAdjPayloadSize_MASK 0x1c00 -#define D0F0xE4_CORE_0010_Reserved_31_13_OFFSET 13 -#define D0F0xE4_CORE_0010_Reserved_31_13_WIDTH 3 -#define D0F0xE4_CORE_0010_Reserved_31_13_MASK 0xffffe000 - -/// D0F0xE4_CORE_0010 -typedef union { - struct { ///< - UINT32 HwInitWrLock:1 ; ///< - UINT32 Reserved_8_1:8 ; ///< - UINT32 UmiNpMemWrite:1 ; ///< - UINT32 RxSbAdjPayloadSize:3 ; ///< - UINT32 Reserved_31_13:19; ///< - } Field; ///< - UINT32 Value; ///< -} D0F0xE4_CORE_0010_STRUCT; - -// **** D0F0x98_x0C Register Definition **** -// Address -#define D0F0x98_x0C_ADDRESS 0xc - -// Type -#define D0F0x98_x0C_TYPE TYPE_D0F0x98 -// Field Data -#define D0F0x98_x0C_GcmWrrLenA_OFFSET 0 -#define D0F0x98_x0C_GcmWrrLenA_WIDTH 8 -#define D0F0x98_x0C_GcmWrrLenA_MASK 0xff -#define D0F0x98_x0C_GcmWrrLenB_OFFSET 8 -#define D0F0x98_x0C_GcmWrrLenB_WIDTH 8 -#define D0F0x98_x0C_GcmWrrLenB_MASK 0xff00 -#define D0F0x98_x0C_Reserved_29_16_OFFSET 16 -#define D0F0x98_x0C_Reserved_29_16_WIDTH 14 -#define D0F0x98_x0C_Reserved_29_16_MASK 0x3fff0000 -#define D0F0x98_x0C_StrictSelWinnerEn_OFFSET 30 -#define D0F0x98_x0C_StrictSelWinnerEn_WIDTH 1 -#define D0F0x98_x0C_StrictSelWinnerEn_MASK 0x40000000 -#define D0F0x98_x0C_Reserved_31_31_OFFSET 31 -#define D0F0x98_x0C_Reserved_31_31_WIDTH 1 -#define D0F0x98_x0C_Reserved_31_31_MASK 0x80000000 - -/// D0F0x98_x0C -typedef union { - struct { ///< - UINT32 GcmWrrLenA:8 ; ///< - UINT32 GcmWrrLenB:8 ; ///< - UINT32 Reserved_29_16:14; ///< - UINT32 StrictSelWinnerEn:1 ; ///< - UINT32 Reserved_31_31:1 ; ///< - } Field; ///< - UINT32 Value; ///< -} D0F0x98_x0C_STRUCT; - -// **** FCRxFE00_7103 Register Definition **** -// Address -#define FCRxFE00_7103_ADDRESS 0xfe007103 - -// Type -#define FCRxFE00_7103_TYPE TYPE_FCR -// Field Data -#define FCRxFE00_7103_Reserved_4_0_OFFSET 0 -#define FCRxFE00_7103_Reserved_4_0_WIDTH 5 -#define FCRxFE00_7103_Reserved_4_0_MASK 0x1f -#define FCRxFE00_7103_SclkDpmVid0_OFFSET 5 -#define FCRxFE00_7103_SclkDpmVid0_WIDTH 2 -#define FCRxFE00_7103_SclkDpmVid0_MASK 0x60 -#define FCRxFE00_7103_SclkDpmVid1_OFFSET 7 -#define FCRxFE00_7103_SclkDpmVid1_WIDTH 2 -#define FCRxFE00_7103_SclkDpmVid1_MASK 0x180 -#define FCRxFE00_7103_SclkDpmVid2_OFFSET 9 -#define FCRxFE00_7103_SclkDpmVid2_WIDTH 2 -#define FCRxFE00_7103_SclkDpmVid2_MASK 0x600 -#define FCRxFE00_7103_SclkDpmVid3_OFFSET 11 -#define FCRxFE00_7103_SclkDpmVid3_WIDTH 2 -#define FCRxFE00_7103_SclkDpmVid3_MASK 0x1800 -#define FCRxFE00_7103_SclkDpmVid4_OFFSET 13 -#define FCRxFE00_7103_SclkDpmVid4_WIDTH 2 -#define FCRxFE00_7103_SclkDpmVid4_MASK 0x6000 -#define FCRxFE00_7103_Reserved_31_15_OFFSET 15 -#define FCRxFE00_7103_Reserved_31_15_WIDTH 17 -#define FCRxFE00_7103_Reserved_31_15_MASK 0xffff8000 - -/// FCRxFE00_7103 -typedef union { - struct { ///< - UINT32 Reserved_4_0:5 ; ///< - UINT32 SclkDpmVid0:2 ; ///< - UINT32 SclkDpmVid1:2 ; ///< - UINT32 SclkDpmVid2:2 ; ///< - UINT32 SclkDpmVid3:2 ; ///< - UINT32 SclkDpmVid4:2 ; ///< - UINT32 Reserved_31_15:17; ///< - } Field; ///< - UINT32 Value; ///< -} FCRxFE00_7103_STRUCT; - -// **** FCRxFE00_7104 Register Definition **** -// Address -#define FCRxFE00_7104_ADDRESS 0xfe007104 - -// Type -#define FCRxFE00_7104_TYPE TYPE_FCR -// Field Data -#define FCRxFE00_7104_Reserved_6_0_OFFSET 0 -#define FCRxFE00_7104_Reserved_6_0_WIDTH 7 -#define FCRxFE00_7104_Reserved_6_0_MASK 0x7f -#define FCRxFE00_7104_SclkDpmDid0_OFFSET 7 -#define FCRxFE00_7104_SclkDpmDid0_WIDTH 7 -#define FCRxFE00_7104_SclkDpmDid0_MASK 0x3f80 -#define FCRxFE00_7104_SclkDpmDid1_OFFSET 14 -#define FCRxFE00_7104_SclkDpmDid1_WIDTH 7 -#define FCRxFE00_7104_SclkDpmDid1_MASK 0x1fc000 -#define FCRxFE00_7104_SclkDpmDid2_OFFSET 21 -#define FCRxFE00_7104_SclkDpmDid2_WIDTH 7 -#define FCRxFE00_7104_SclkDpmDid2_MASK 0xfe00000 -#define FCRxFE00_7104_Reserved_31_28_OFFSET 28 -#define FCRxFE00_7104_Reserved_31_28_WIDTH 4 -#define FCRxFE00_7104_Reserved_31_28_MASK 0xf0000000 - -/// FCRxFE00_7104 -typedef union { - struct { ///< - UINT32 Reserved_6_0:7 ; ///< - UINT32 SclkDpmDid0:7 ; ///< - UINT32 SclkDpmDid1:7 ; ///< - UINT32 SclkDpmDid2:7 ; ///< - UINT32 Reserved_31_28:4 ; ///< - } Field; ///< - UINT32 Value; ///< -} FCRxFE00_7104_STRUCT; - -// **** FCRxFE00_7107 Register Definition **** -// Address -#define FCRxFE00_7107_ADDRESS 0xfe007107 - -// Type -#define FCRxFE00_7107_TYPE TYPE_FCR -// Field Data -#define FCRxFE00_7107_Reserved_3_0_OFFSET 0 -#define FCRxFE00_7107_Reserved_3_0_WIDTH 4 -#define FCRxFE00_7107_Reserved_3_0_MASK 0xf -#define FCRxFE00_7107_SclkDpmDid3_OFFSET 4 -#define FCRxFE00_7107_SclkDpmDid3_WIDTH 7 -#define FCRxFE00_7107_SclkDpmDid3_MASK 0x7f0 -#define FCRxFE00_7107_SclkDpmDid4_OFFSET 11 -#define FCRxFE00_7107_SclkDpmDid4_WIDTH 7 -#define FCRxFE00_7107_SclkDpmDid4_MASK 0x3f800 -#define FCRxFE00_7107_Reserved_31_18_OFFSET 18 -#define FCRxFE00_7107_Reserved_31_18_WIDTH 14 -#define FCRxFE00_7107_Reserved_31_18_MASK 0xfffc0000 - -/// FCRxFE00_7107 -typedef union { - struct { ///< - UINT32 Reserved_3_0:4 ; ///< - UINT32 SclkDpmDid3:7 ; ///< - UINT32 SclkDpmDid4:7 ; ///< - UINT32 Reserved_31_18:14; ///< - } Field; ///< - UINT32 Value; ///< -} FCRxFE00_7107_STRUCT; - -// **** FCRxFE00_7109 Register Definition **** -// Address -#define FCRxFE00_7109_ADDRESS 0xfe007109 - -// Type -#define FCRxFE00_7109_TYPE TYPE_FCR -// Field Data -#define FCRxFE00_7109_Reserved_1_0_OFFSET 0 -#define FCRxFE00_7109_Reserved_1_0_WIDTH 2 -#define FCRxFE00_7109_Reserved_1_0_MASK 0x3 -#define FCRxFE00_7109_SclkDpmCacBase_OFFSET 2 -#define FCRxFE00_7109_SclkDpmCacBase_WIDTH 8 -#define FCRxFE00_7109_SclkDpmCacBase_MASK 0x3fc -#define FCRxFE00_7109_Reserved_31_10_OFFSET 10 -#define FCRxFE00_7109_Reserved_31_10_WIDTH 22 -#define FCRxFE00_7109_Reserved_31_10_MASK 0xfffffc00 - -/// FCRxFE00_7109 -typedef union { - struct { ///< - UINT32 Reserved_1_0:2 ; ///< - UINT32 SclkDpmCacBase:8 ; ///< - UINT32 Reserved_31_10:22; ///< - } Field; ///< - UINT32 Value; ///< -} FCRxFE00_7109_STRUCT; - -// **** FCRxFE00_710A Register Definition **** -// Address -#define FCRxFE00_710A_ADDRESS 0xfe00710a - -// Type -#define FCRxFE00_710A_TYPE TYPE_FCR -// Field Data -#define FCRxFE00_710A_Reserved_1_0_OFFSET 0 -#define FCRxFE00_710A_Reserved_1_0_WIDTH 2 -#define FCRxFE00_710A_Reserved_1_0_MASK 0x3 -#define FCRxFE00_710A_GpuPwrGtCac_OFFSET 2 -#define FCRxFE00_710A_GpuPwrGtCac_WIDTH 16 -#define FCRxFE00_710A_GpuPwrGtCac_MASK 0x3fffc -#define FCRxFE00_710A_Reserved_31_18_OFFSET 18 -#define FCRxFE00_710A_Reserved_31_18_WIDTH 14 -#define FCRxFE00_710A_Reserved_31_18_MASK 0xfffc0000 - -/// FCRxFE00_710A -typedef union { - struct { ///< - UINT32 Reserved_1_0:2 ; ///< - UINT32 GpuPwrGtCac:16; ///< - UINT32 Reserved_31_18:14; ///< - } Field; ///< - UINT32 Value; ///< -} FCRxFE00_710A_STRUCT; - -// **** FCRxFE00_710D Register Definition **** -// Address -#define FCRxFE00_710D_ADDRESS 0xfe00710d - -// Type -#define FCRxFE00_710D_TYPE TYPE_FCR -// Field Data -#define FCRxFE00_710D_Reserved_1_0_OFFSET 0 -#define FCRxFE00_710D_Reserved_1_0_WIDTH 2 -#define FCRxFE00_710D_Reserved_1_0_MASK 0x3 -#define FCRxFE00_710D_DispclkDid0_OFFSET 2 -#define FCRxFE00_710D_DispclkDid0_WIDTH 7 -#define FCRxFE00_710D_DispclkDid0_MASK 0x1fc -#define FCRxFE00_710D_DispclkDid1_OFFSET 9 -#define FCRxFE00_710D_DispclkDid1_WIDTH 7 -#define FCRxFE00_710D_DispclkDid1_MASK 0xfe00 -#define FCRxFE00_710D_DispclkDid2_OFFSET 16 -#define FCRxFE00_710D_DispclkDid2_WIDTH 7 -#define FCRxFE00_710D_DispclkDid2_MASK 0x7f0000 -#define FCRxFE00_710D_DispclkDid3_OFFSET 23 -#define FCRxFE00_710D_DispclkDid3_WIDTH 7 -#define FCRxFE00_710D_DispclkDid3_MASK 0x3f800000 -#define FCRxFE00_710D_Reserved_31_30_OFFSET 30 -#define FCRxFE00_710D_Reserved_31_30_WIDTH 2 -#define FCRxFE00_710D_Reserved_31_30_MASK 0xc0000000 - -/// FCRxFE00_710D -typedef union { - struct { ///< - UINT32 Reserved_1_0:2 ; ///< - UINT32 DispclkDid0:7 ; ///< - UINT32 DispclkDid1:7 ; ///< - UINT32 DispclkDid2:7 ; ///< - UINT32 DispclkDid3:7 ; ///< - UINT32 Reserved_31_30:2 ; ///< - } Field; ///< - UINT32 Value; ///< -} FCRxFE00_710D_STRUCT; - - - -// **** FCRxFE00_7114 Register Definition **** -// Address -#define FCRxFE00_7114_ADDRESS 0xfe007114 - -// Type -#define FCRxFE00_7114_TYPE TYPE_FCR -// Field Data -#define FCRxFE00_7114_Reserved_5_0_OFFSET 0 -#define FCRxFE00_7114_Reserved_5_0_WIDTH 6 -#define FCRxFE00_7114_Reserved_5_0_MASK 0x3f -#define FCRxFE00_7114_DclkDid0_OFFSET 6 -#define FCRxFE00_7114_DclkDid0_WIDTH 7 -#define FCRxFE00_7114_DclkDid0_MASK 0x1fc0 -#define FCRxFE00_7114_DclkDid1_OFFSET 13 -#define FCRxFE00_7114_DclkDid1_WIDTH 7 -#define FCRxFE00_7114_DclkDid1_MASK 0xfe000 -#define FCRxFE00_7114_DclkDid2_OFFSET 20 -#define FCRxFE00_7114_DclkDid2_WIDTH 7 -#define FCRxFE00_7114_DclkDid2_MASK 0x7f00000 -#define FCRxFE00_7114_Reserved_31_27_OFFSET 27 -#define FCRxFE00_7114_Reserved_31_27_WIDTH 5 -#define FCRxFE00_7114_Reserved_31_27_MASK 0xf8000000 - -/// FCRxFE00_7114 -typedef union { - struct { ///< - UINT32 Reserved_5_0:6 ; ///< - UINT32 DclkDid0:7 ; ///< - UINT32 DclkDid1:7 ; ///< - UINT32 DclkDid2:7 ; ///< - UINT32 Reserved_31_27:5 ; ///< - } Field; ///< - UINT32 Value; ///< -} FCRxFE00_7114_STRUCT; - -// **** FCRxFE00_7117 Register Definition **** -// Address -#define FCRxFE00_7117_ADDRESS 0xfe007117 - -// Type -#define FCRxFE00_7117_TYPE TYPE_FCR -// Field Data -#define FCRxFE00_7117_Reserved_2_0_OFFSET 0 -#define FCRxFE00_7117_Reserved_2_0_WIDTH 3 -#define FCRxFE00_7117_Reserved_2_0_MASK 0x7 -#define FCRxFE00_7117_DclkDid3_OFFSET 3 -#define FCRxFE00_7117_DclkDid3_WIDTH 7 -#define FCRxFE00_7117_DclkDid3_MASK 0x3f8 -#define FCRxFE00_7117_VclkDid3_OFFSET 10 -#define FCRxFE00_7117_VclkDid3_WIDTH 7 -#define FCRxFE00_7117_VclkDid3_MASK 0x1fc00 -#define FCRxFE00_7117_Reserved_31_17_OFFSET 17 -#define FCRxFE00_7117_Reserved_31_17_WIDTH 15 -#define FCRxFE00_7117_Reserved_31_17_MASK 0xfffe0000 - -/// FCRxFE00_7117 -typedef union { - struct { ///< - UINT32 Reserved_2_0:3 ; ///< - UINT32 DclkDid3:7 ; ///< - UINT32 VclkDid3:7 ; ///< - UINT32 Reserved_31_17:15; ///< - } Field; ///< - UINT32 Value; ///< -} FCRxFE00_7117_STRUCT; - -// **** FCRxFE00_7119 Register Definition **** -// Address -#define FCRxFE00_7119_ADDRESS 0xfe007119 - -// Type -#define FCRxFE00_7119_TYPE TYPE_FCR -// Field Data -#define FCRxFE00_7119_Reserved_0_0_OFFSET 0 -#define FCRxFE00_7119_Reserved_0_0_WIDTH 1 -#define FCRxFE00_7119_Reserved_0_0_MASK 0x1 -#define FCRxFE00_7119_SclkDpmValid0_OFFSET 1 -#define FCRxFE00_7119_SclkDpmValid0_WIDTH 5 -#define FCRxFE00_7119_SclkDpmValid0_MASK 0x3e -#define FCRxFE00_7119_SclkDpmValid1_OFFSET 6 -#define FCRxFE00_7119_SclkDpmValid1_WIDTH 5 -#define FCRxFE00_7119_SclkDpmValid1_MASK 0x7c0 -#define FCRxFE00_7119_SclkDpmValid2_OFFSET 11 -#define FCRxFE00_7119_SclkDpmValid2_WIDTH 5 -#define FCRxFE00_7119_SclkDpmValid2_MASK 0xf800 -#define FCRxFE00_7119_SclkDpmValid3_OFFSET 16 -#define FCRxFE00_7119_SclkDpmValid3_WIDTH 5 -#define FCRxFE00_7119_SclkDpmValid3_MASK 0x1f0000 -#define FCRxFE00_7119_SclkDpmValid4_OFFSET 21 -#define FCRxFE00_7119_SclkDpmValid4_WIDTH 5 -#define FCRxFE00_7119_SclkDpmValid4_MASK 0x3e00000 -#define FCRxFE00_7119_SclkDpmValid5_OFFSET 26 -#define FCRxFE00_7119_SclkDpmValid5_WIDTH 5 -#define FCRxFE00_7119_SclkDpmValid5_MASK 0x7c000000 -#define FCRxFE00_7119_Reserved_31_31_OFFSET 31 -#define FCRxFE00_7119_Reserved_31_31_WIDTH 1 -#define FCRxFE00_7119_Reserved_31_31_MASK 0x80000000 - -/// FCRxFE00_7119 -typedef union { - struct { ///< - UINT32 Reserved_0_0:1 ; ///< - UINT32 SclkDpmValid0:5 ; ///< - UINT32 SclkDpmValid1:5 ; ///< - UINT32 SclkDpmValid2:5 ; ///< - UINT32 SclkDpmValid3:5 ; ///< - UINT32 SclkDpmValid4:5 ; ///< - UINT32 SclkDpmValid5:5 ; ///< - UINT32 Reserved_31_31:1 ; ///< - } Field; ///< - UINT32 Value; ///< -} FCRxFE00_7119_STRUCT; - -// **** FCRxFE00_711C Register Definition **** -// Address -#define FCRxFE00_711C_ADDRESS 0xfe00711c - -// Type -#define FCRxFE00_711C_TYPE TYPE_FCR -// Field Data -#define FCRxFE00_711C_Reserved_6_0_OFFSET 0 -#define FCRxFE00_711C_Reserved_6_0_WIDTH 7 -#define FCRxFE00_711C_Reserved_6_0_MASK 0x7f -#define FCRxFE00_711C_PolicyLabel0_OFFSET 7 -#define FCRxFE00_711C_PolicyLabel0_WIDTH 2 -#define FCRxFE00_711C_PolicyLabel0_MASK 0x180 -#define FCRxFE00_711C_PolicyLabel1_OFFSET 9 -#define FCRxFE00_711C_PolicyLabel1_WIDTH 2 -#define FCRxFE00_711C_PolicyLabel1_MASK 0x600 -#define FCRxFE00_711C_PolicyLabel2_OFFSET 11 -#define FCRxFE00_711C_PolicyLabel2_WIDTH 2 -#define FCRxFE00_711C_PolicyLabel2_MASK 0x1800 -#define FCRxFE00_711C_PolicyLabel3_OFFSET 13 -#define FCRxFE00_711C_PolicyLabel3_WIDTH 2 -#define FCRxFE00_711C_PolicyLabel3_MASK 0x6000 -#define FCRxFE00_711C_PolicyLabel4_OFFSET 15 -#define FCRxFE00_711C_PolicyLabel4_WIDTH 2 -#define FCRxFE00_711C_PolicyLabel4_MASK 0x18000 -#define FCRxFE00_711C_PolicyLabel5_OFFSET 17 -#define FCRxFE00_711C_PolicyLabel5_WIDTH 2 -#define FCRxFE00_711C_PolicyLabel5_MASK 0x60000 -#define FCRxFE00_711C_Reserved_31_19_OFFSET 19 -#define FCRxFE00_711C_Reserved_31_19_WIDTH 13 -#define FCRxFE00_711C_Reserved_31_19_MASK 0xfff80000 - -/// FCRxFE00_711C -typedef union { - struct { ///< - UINT32 Reserved_6_0:7 ; ///< - UINT32 PolicyLabel0:2 ; ///< - UINT32 PolicyLabel1:2 ; ///< - UINT32 PolicyLabel2:2 ; ///< - UINT32 PolicyLabel3:2 ; ///< - UINT32 PolicyLabel4:2 ; ///< - UINT32 PolicyLabel5:2 ; ///< - UINT32 Reserved_31_19:13; ///< - } Field; ///< - UINT32 Value; ///< -} FCRxFE00_711C_STRUCT; - -// **** FCRxFE00_711E Register Definition **** -// Address -#define FCRxFE00_711E_ADDRESS 0xfe00711e - -// Type -#define FCRxFE00_711E_TYPE TYPE_FCR -// Field Data -#define FCRxFE00_711E_Reserved_2_0_OFFSET 0 -#define FCRxFE00_711E_Reserved_2_0_WIDTH 3 -#define FCRxFE00_711E_Reserved_2_0_MASK 0x7 -#define FCRxFE00_711E_PolicyFlags0_OFFSET 3 -#define FCRxFE00_711E_PolicyFlags0_WIDTH 7 -#define FCRxFE00_711E_PolicyFlags0_MASK 0x3f8 -#define FCRxFE00_711E_PolicyFlags1_OFFSET 10 -#define FCRxFE00_711E_PolicyFlags1_WIDTH 7 -#define FCRxFE00_711E_PolicyFlags1_MASK 0x1fc00 -#define FCRxFE00_711E_PolicyFlags2_OFFSET 17 -#define FCRxFE00_711E_PolicyFlags2_WIDTH 7 -#define FCRxFE00_711E_PolicyFlags2_MASK 0xfe0000 -#define FCRxFE00_711E_PolicyFlags3_OFFSET 24 -#define FCRxFE00_711E_PolicyFlags3_WIDTH 7 -#define FCRxFE00_711E_PolicyFlags3_MASK 0x7f000000 -#define FCRxFE00_711E_Reserved_31_31_OFFSET 31 -#define FCRxFE00_711E_Reserved_31_31_WIDTH 1 -#define FCRxFE00_711E_Reserved_31_31_MASK 0x80000000 - -/// FCRxFE00_711E -typedef union { - struct { ///< - UINT32 Reserved_2_0:3 ; ///< - UINT32 PolicyFlags0:7 ; ///< - UINT32 PolicyFlags1:7 ; ///< - UINT32 PolicyFlags2:7 ; ///< - UINT32 PolicyFlags3:7 ; ///< - UINT32 Reserved_31_31:1 ; ///< - } Field; ///< - UINT32 Value; ///< -} FCRxFE00_711E_STRUCT; - -// **** FCRxFE00_7121 Register Definition **** -// Address -#define FCRxFE00_7121_ADDRESS 0xfe007121 - -// Type -#define FCRxFE00_7121_TYPE TYPE_FCR -// Field Data -#define FCRxFE00_7121_Reserved_6_0_OFFSET 0 -#define FCRxFE00_7121_Reserved_6_0_WIDTH 7 -#define FCRxFE00_7121_Reserved_6_0_MASK 0x7f -#define FCRxFE00_7121_PolicyFlags4_OFFSET 7 -#define FCRxFE00_7121_PolicyFlags4_WIDTH 7 -#define FCRxFE00_7121_PolicyFlags4_MASK 0x3f80 -#define FCRxFE00_7121_PolicyFlags5_OFFSET 14 -#define FCRxFE00_7121_PolicyFlags5_WIDTH 7 -#define FCRxFE00_7121_PolicyFlags5_MASK 0x1fc000 -#define FCRxFE00_7121_Reserved_31_21_OFFSET 21 -#define FCRxFE00_7121_Reserved_31_21_WIDTH 11 -#define FCRxFE00_7121_Reserved_31_21_MASK 0xffe00000 - -/// FCRxFE00_7121 -typedef union { - struct { ///< - UINT32 Reserved_6_0:7 ; ///< - UINT32 PolicyFlags4:7 ; ///< - UINT32 PolicyFlags5:7 ; ///< - UINT32 Reserved_31_21:11; ///< - } Field; ///< - UINT32 Value; ///< -} FCRxFE00_7121_STRUCT; - -// **** FCRxFE00_6022 Register Definition **** -// Address -#define FCRxFE00_6022_ADDRESS 0xfe006022 - -// Type -#define FCRxFE00_6022_TYPE TYPE_FCR -// Field Data -#define FCRxFE00_6022_Reserved_2_0_OFFSET 0 -#define FCRxFE00_6022_Reserved_2_0_WIDTH 3 -#define FCRxFE00_6022_Reserved_2_0_MASK 0x7 -#define FCRxFE00_6022_DclkVclkSel0_OFFSET 3 -#define FCRxFE00_6022_DclkVclkSel0_WIDTH 2 -#define FCRxFE00_6022_DclkVclkSel0_MASK 0x18 -#define FCRxFE00_6022_DclkVclkSel1_OFFSET 5 -#define FCRxFE00_6022_DclkVclkSel1_WIDTH 2 -#define FCRxFE00_6022_DclkVclkSel1_MASK 0x60 -#define FCRxFE00_6022_DclkVclkSel2_OFFSET 7 -#define FCRxFE00_6022_DclkVclkSel2_WIDTH 2 -#define FCRxFE00_6022_DclkVclkSel2_MASK 0x180 -#define FCRxFE00_6022_DclkVclkSel3_OFFSET 9 -#define FCRxFE00_6022_DclkVclkSel3_WIDTH 2 -#define FCRxFE00_6022_DclkVclkSel3_MASK 0x600 -#define FCRxFE00_6022_DclkVclkSel4_OFFSET 11 -#define FCRxFE00_6022_DclkVclkSel4_WIDTH 2 -#define FCRxFE00_6022_DclkVclkSel4_MASK 0x1800 -#define FCRxFE00_6022_DclkVclkSel5_OFFSET 13 -#define FCRxFE00_6022_DclkVclkSel5_WIDTH 2 -#define FCRxFE00_6022_DclkVclkSel5_MASK 0x6000 -#define FCRxFE00_6022_Reserved_31_15_OFFSET 15 -#define FCRxFE00_6022_Reserved_31_15_WIDTH 17 -#define FCRxFE00_6022_Reserved_31_15_MASK 0xffff8000 - -/// FCRxFE00_6022 -typedef union { - struct { ///< - UINT32 Reserved_2_0:3 ; ///< - UINT32 DclkVclkSel0:2 ; ///< - UINT32 DclkVclkSel1:2 ; ///< - UINT32 DclkVclkSel2:2 ; ///< - UINT32 DclkVclkSel3:2 ; ///< - UINT32 DclkVclkSel4:2 ; ///< - UINT32 DclkVclkSel5:2 ; ///< - UINT32 Reserved_31_15:17; ///< - } Field; ///< - UINT32 Value; ///< -} FCRxFE00_6022_STRUCT; - -// **** FCRxFE00_4003 Register Definition **** -// Address -#define FCRxFE00_4003_ADDRESS 0xfe004003 - -// Type -#define FCRxFE00_4003_TYPE TYPE_FCR -// Field Data -#define FCRxFE00_4003_Reserved_6_0_OFFSET 0 -#define FCRxFE00_4003_Reserved_6_0_WIDTH 7 -#define FCRxFE00_4003_Reserved_6_0_MASK 0x7f -#define FCRxFE00_4003_VclkDid0_OFFSET 7 -#define FCRxFE00_4003_VclkDid0_WIDTH 7 -#define FCRxFE00_4003_VclkDid0_MASK 0x3f80 -#define FCRxFE00_4003_Reserved_31_14_OFFSET 14 -#define FCRxFE00_4003_Reserved_31_14_WIDTH 18 -#define FCRxFE00_4003_Reserved_31_14_MASK 0xffffc000 - -/// FCRxFE00_4003 -typedef union { - struct { ///< - UINT32 Reserved_6_0:7 ; ///< - UINT32 VclkDid0:7 ; ///< - UINT32 Reserved_31_14:18; ///< - } Field; ///< - UINT32 Value; ///< -} FCRxFE00_4003_STRUCT; - -// **** FCRxFE00_4008 Register Definition **** -// Address -#define FCRxFE00_4008_ADDRESS 0xfe004008 - -// Type -#define FCRxFE00_4008_TYPE TYPE_FCR -// Field Data -#define FCRxFE00_4008_Reserved_1_0_OFFSET 0 -#define FCRxFE00_4008_Reserved_1_0_WIDTH 2 -#define FCRxFE00_4008_Reserved_1_0_MASK 0x3 -#define FCRxFE00_4008_VclkDid1_OFFSET 2 -#define FCRxFE00_4008_VclkDid1_WIDTH 7 -#define FCRxFE00_4008_VclkDid1_MASK 0x1fc -#define FCRxFE00_4008_Reserved_31_9_OFFSET 9 -#define FCRxFE00_4008_Reserved_31_9_WIDTH 23 -#define FCRxFE00_4008_Reserved_31_9_MASK 0xfffffe00 - -/// FCRxFE00_4008 -typedef union { - struct { ///< - UINT32 Reserved_1_0:2 ; ///< - UINT32 VclkDid1:7 ; ///< - UINT32 Reserved_31_9:23; ///< - } Field; ///< - UINT32 Value; ///< -} FCRxFE00_4008_STRUCT; - -// **** FCRxFE00_4028 Register Definition **** -// Address -#define FCRxFE00_4028_ADDRESS 0xfe004028 - -// Type -#define FCRxFE00_4028_TYPE TYPE_FCR -// Field Data -#define FCRxFE00_4028_VclkDid2_OFFSET 0 -#define FCRxFE00_4028_VclkDid2_WIDTH 7 -#define FCRxFE00_4028_VclkDid2_MASK 0x7f -#define FCRxFE00_4028_Reserved_31_7_OFFSET 7 -#define FCRxFE00_4028_Reserved_31_7_WIDTH 25 -#define FCRxFE00_4028_Reserved_31_7_MASK 0xffffff80 - -/// FCRxFE00_4028 -typedef union { - struct { ///< - UINT32 VclkDid2:7 ; ///< - UINT32 Reserved_31_7:25; ///< - } Field; ///< - UINT32 Value; ///< -} FCRxFE00_4028_STRUCT; - -// **** FCRxFE00_4036 Register Definition **** -// Address -#define FCRxFE00_4036_ADDRESS 0xfe004036 - -// Type -#define FCRxFE00_4036_TYPE TYPE_FCR -// Field Data -#define FCRxFE00_4036_Reserved_1_0_OFFSET 0 -#define FCRxFE00_4036_Reserved_1_0_WIDTH 2 -#define FCRxFE00_4036_Reserved_1_0_MASK 0x3 -#define FCRxFE00_4036_PPlayTableRev_OFFSET 2 -#define FCRxFE00_4036_PPlayTableRev_WIDTH 4 -#define FCRxFE00_4036_PPlayTableRev_MASK 0x3c -#define FCRxFE00_4036_SclkThermDid_OFFSET 6 -#define FCRxFE00_4036_SclkThermDid_WIDTH 7 -#define FCRxFE00_4036_SclkThermDid_MASK 0x1fc0 -#define FCRxFE00_4036_PcieGen2Vid_OFFSET 13 -#define FCRxFE00_4036_PcieGen2Vid_WIDTH 2 -#define FCRxFE00_4036_PcieGen2Vid_MASK 0x6000 -#define FCRxFE00_4036_Reserved_31_15_OFFSET 15 -#define FCRxFE00_4036_Reserved_31_15_WIDTH 17 -#define FCRxFE00_4036_Reserved_31_15_MASK 0xffff8000 - -/// FCRxFE00_4036 -typedef union { - struct { ///< - UINT32 Reserved_1_0:2 ; ///< - UINT32 PPlayTableRev:4 ; ///< - UINT32 SclkThermDid:7 ; ///< - UINT32 PcieGen2Vid:2 ; ///< - UINT32 Reserved_31_15:17; ///< - } Field; ///< - UINT32 Value; ///< -} FCRxFE00_4036_STRUCT; - -// **** D18F3xA0 Register Definition **** -// Address -#define D18F3xA0_ADDRESS 0xa0 - -// Type -#define D18F3xA0_TYPE TYPE_D18F3 -// Field Data -#define D18F3xA0_PsiVid_OFFSET 0 -#define D18F3xA0_PsiVid_WIDTH 7 -#define D18F3xA0_PsiVid_MASK 0x7f -#define D18F3xA0_PsiVidEn_OFFSET 7 -#define D18F3xA0_PsiVidEn_WIDTH 1 -#define D18F3xA0_PsiVidEn_MASK 0x80 -#define D18F3xA0_Reserved_8_8_OFFSET 8 -#define D18F3xA0_Reserved_8_8_WIDTH 1 -#define D18F3xA0_Reserved_8_8_MASK 0x100 -#define D18F3xA0_SviHighFreqSel_OFFSET 9 -#define D18F3xA0_SviHighFreqSel_WIDTH 1 -#define D18F3xA0_SviHighFreqSel_MASK 0x200 -#define D18F3xA0_Reserved_15_10_OFFSET 10 -#define D18F3xA0_Reserved_15_10_WIDTH 6 -#define D18F3xA0_Reserved_15_10_MASK 0xfc00 -#define D18F3xA0_ConfigId_OFFSET 16 -#define D18F3xA0_ConfigId_WIDTH 12 -#define D18F3xA0_ConfigId_MASK 0xfff0000 -#define D18F3xA0_Reserved_30_28_OFFSET 28 -#define D18F3xA0_Reserved_30_28_WIDTH 3 -#define D18F3xA0_Reserved_30_28_MASK 0x70000000 -#define D18F3xA0_CofVidProg_OFFSET 31 -#define D18F3xA0_CofVidProg_WIDTH 1 -#define D18F3xA0_CofVidProg_MASK 0x80000000 - -/// D18F3xA0 -typedef union { - struct { ///< - UINT32 PsiVid:7 ; ///< - UINT32 PsiVidEn:1 ; ///< - UINT32 Reserved_8_8:1 ; ///< - UINT32 SviHighFreqSel:1 ; ///< - UINT32 Reserved_15_10:6 ; ///< - UINT32 ConfigId:12; ///< - UINT32 Reserved_30_28:3 ; ///< - UINT32 CofVidProg:1 ; ///< - } Field; ///< - UINT32 Value; ///< -} D18F3xA0_STRUCT; - -// **** D0F0xE4_WRAP_8015 Register Definition **** -// Address -#define D0F0xE4_WRAP_8015_ADDRESS 0x8015 - -// Type -#define D0F0xE4_WRAP_8015_TYPE TYPE_D0F0xE4 -// Field Data -#define D0F0xE4_WRAP_8015_Reserved_15_0_OFFSET 0 -#define D0F0xE4_WRAP_8015_Reserved_15_0_WIDTH 16 -#define D0F0xE4_WRAP_8015_Reserved_15_0_MASK 0xffff -#define D0F0xE4_WRAP_8015_RefclkRegsGateLatency_OFFSET 16 -#define D0F0xE4_WRAP_8015_RefclkRegsGateLatency_WIDTH 6 -#define D0F0xE4_WRAP_8015_RefclkRegsGateLatency_MASK 0x3f0000 -#define D0F0xE4_WRAP_8015_Reserved_22_22_OFFSET 22 -#define D0F0xE4_WRAP_8015_Reserved_22_22_WIDTH 1 -#define D0F0xE4_WRAP_8015_Reserved_22_22_MASK 0x400000 -#define D0F0xE4_WRAP_8015_RefclkRegsGateEnable_OFFSET 23 -#define D0F0xE4_WRAP_8015_RefclkRegsGateEnable_WIDTH 1 -#define D0F0xE4_WRAP_8015_RefclkRegsGateEnable_MASK 0x800000 -#define D0F0xE4_WRAP_8015_RefclkBphyGateLatency_OFFSET 24 -#define D0F0xE4_WRAP_8015_RefclkBphyGateLatency_WIDTH 6 -#define D0F0xE4_WRAP_8015_RefclkBphyGateLatency_MASK 0x3f000000 -#define D0F0xE4_WRAP_8015_Reserved_30_30_OFFSET 30 -#define D0F0xE4_WRAP_8015_Reserved_30_30_WIDTH 1 -#define D0F0xE4_WRAP_8015_Reserved_30_30_MASK 0x40000000 -#define D0F0xE4_WRAP_8015_RefclkBphyGateEnable_OFFSET 31 -#define D0F0xE4_WRAP_8015_RefclkBphyGateEnable_WIDTH 1 -#define D0F0xE4_WRAP_8015_RefclkBphyGateEnable_MASK 0x80000000 - -/// D0F0xE4_WRAP_8015 -typedef union { - struct { ///< - UINT32 Reserved_15_0:16; ///< - UINT32 RefclkRegsGateLatency:6 ; ///< - UINT32 Reserved_22_22:1 ; ///< - UINT32 RefclkRegsGateEnable:1 ; ///< - UINT32 RefclkBphyGateLatency:6 ; ///< - UINT32 Reserved_30_30:1 ; ///< - UINT32 RefclkBphyGateEnable:1 ; ///< - } Field; ///< - UINT32 Value; ///< -} D0F0xE4_WRAP_8015_STRUCT; - -// **** DxF0xE4_xB5 Register Definition **** -// Address -#define DxF0xE4_xB5_ADDRESS 0xb5 - -// Type -#define DxF0xE4_xB5_TYPE TYPE_D4F0xE4 -// Field Data -#define DxF0xE4_xB5_LcSelectDeemphasis_OFFSET 0 -#define DxF0xE4_xB5_LcSelectDeemphasis_WIDTH 1 -#define DxF0xE4_xB5_LcSelectDeemphasis_MASK 0x1 -#define DxF0xE4_xB5_LcSelectDeemphasisCntl_OFFSET 1 -#define DxF0xE4_xB5_LcSelectDeemphasisCntl_WIDTH 2 -#define DxF0xE4_xB5_LcSelectDeemphasisCntl_MASK 0x6 -#define DxF0xE4_xB5_LcRcvdDeemphasis_OFFSET 3 -#define DxF0xE4_xB5_LcRcvdDeemphasis_WIDTH 1 -#define DxF0xE4_xB5_LcRcvdDeemphasis_MASK 0x8 -#define DxF0xE4_xB5_Reserved_9_4_OFFSET 4 -#define DxF0xE4_xB5_Reserved_9_4_WIDTH 6 -#define DxF0xE4_xB5_Reserved_9_4_MASK 0x3f0 -#define DxF0xE4_xB5_LcEnhancedHotPlugEn_OFFSET 10 -#define DxF0xE4_xB5_LcEnhancedHotPlugEn_WIDTH 1 -#define DxF0xE4_xB5_LcEnhancedHotPlugEn_MASK 0x400 -#define DxF0xE4_xB5_Reserved_11_11_OFFSET 11 -#define DxF0xE4_xB5_Reserved_11_11_WIDTH 1 -#define DxF0xE4_xB5_Reserved_11_11_MASK 0x800 -#define DxF0xE4_xB5_LcEhpRxPhyCmd_OFFSET 12 -#define DxF0xE4_xB5_LcEhpRxPhyCmd_WIDTH 2 -#define DxF0xE4_xB5_LcEhpRxPhyCmd_MASK 0x3000 -#define DxF0xE4_xB5_LcEhpTxPhyCmd_OFFSET 14 -#define DxF0xE4_xB5_LcEhpTxPhyCmd_WIDTH 2 -#define DxF0xE4_xB5_LcEhpTxPhyCmd_MASK 0xc000 -#define DxF0xE4_xB5_Reserved_31_16_OFFSET 16 -#define DxF0xE4_xB5_Reserved_31_16_WIDTH 16 -#define DxF0xE4_xB5_Reserved_31_16_MASK 0xffff0000 - -/// DxF0xE4_xB5 -typedef union { - struct { ///< - UINT32 LcSelectDeemphasis:1 ; ///< - UINT32 LcSelectDeemphasisCntl:2 ; ///< - UINT32 LcRcvdDeemphasis:1 ; ///< - UINT32 Reserved_9_4:6 ; ///< - UINT32 LcEnhancedHotPlugEn:1 ; ///< - UINT32 Reserved_11_11:1 ; ///< - UINT32 LcEhpRxPhyCmd:2 ; ///< - UINT32 LcEhpTxPhyCmd:2 ; ///< - UINT32 Reserved_31_16:16; ///< - } Field; ///< - UINT32 Value; ///< -} DxF0xE4_xB5_STRUCT; - -/// GMMx6124 -typedef union { - struct { ///< - UINT32 DoutScratch:32; ///< - } Field; ///< - UINT32 Value; ///< -} GMMx6124_STRUCT; - -// **** D0F0xE4_PHY_6006 Register Definition **** -// Address -#define D0F0xE4_PHY_6006_ADDRESS 0x6006 - -// Type -#define D0F0xE4_PHY_6006_TYPE TYPE_D0F0xE4 -// Field Data -#define D0F0xE4_PHY_6006_TxMarginNom_OFFSET 0 -#define D0F0xE4_PHY_6006_TxMarginNom_WIDTH 8 -#define D0F0xE4_PHY_6006_TxMarginNom_MASK 0xff -#define D0F0xE4_PHY_6006_DeemphGen1Nom_OFFSET 8 -#define D0F0xE4_PHY_6006_DeemphGen1Nom_WIDTH 8 -#define D0F0xE4_PHY_6006_DeemphGen1Nom_MASK 0xff00 -#define D0F0xE4_PHY_6006_Reserved_31_16_OFFSET 16 -#define D0F0xE4_PHY_6006_Reserved_31_16_WIDTH 16 -#define D0F0xE4_PHY_6006_Reserved_31_16_MASK 0xffff0000 - -/// D0F0xE4_PHY_6006 -typedef union { - struct { ///< - UINT32 TxMarginNom:8 ; ///< - UINT32 DeemphGen1Nom:8 ; ///< - UINT32 Reserved_31_16:16; ///< - } Field; ///< - UINT32 Value; ///< -} D0F0xE4_PHY_6006_STRUCT; - -// **** SMUx0B_x84AC Register Definition **** -// Address -#define SMUx0B_x84AC_ADDRESS 0x84ac - -// Type -#define SMUx0B_x84AC_TYPE TYPE_SMUx0B -// Field Data -#define SMUx0B_x84AC_FstateCredits_1_OFFSET 0 -#define SMUx0B_x84AC_FstateCredits_1_WIDTH 16 -#define SMUx0B_x84AC_FstateCredits_1_MASK 0xffff -#define SMUx0B_x84AC_FstateCredits_0_OFFSET 16 -#define SMUx0B_x84AC_FstateCredits_0_WIDTH 16 -#define SMUx0B_x84AC_FstateCredits_0_MASK 0xffff0000 - -/// SMUx0B_x84AC -typedef union { - struct { ///< - UINT32 FstateCredits_1:16; ///< - UINT32 FstateCredits_0:16; ///< - } Field; ///< - UINT32 Value; ///< -} SMUx0B_x84AC_STRUCT; - -// **** D18F6x80 Register Definition **** -// Address -#define D18F6x80_ADDRESS 0x80 - -// Type -#define D18F6x80_TYPE TYPE_D18F6 -// Field Data -#define D18F6x80_Reserved_19_0_OFFSET 0 -#define D18F6x80_Reserved_19_0_WIDTH 20 -#define D18F6x80_Reserved_19_0_MASK 0xfffff -#define D18F6x80_CableSafeDisAux_3_1_OFFSET 20 -#define D18F6x80_CableSafeDisAux_3_1_WIDTH 3 -#define D18F6x80_CableSafeDisAux_3_1_MASK 0x700000 -#define D18F6x80_Reserved_23_23_OFFSET 23 -#define D18F6x80_Reserved_23_23_WIDTH 1 -#define D18F6x80_Reserved_23_23_MASK 0x800000 -#define D18F6x80_CableSafeDisAux_6_4_OFFSET 24 -#define D18F6x80_CableSafeDisAux_6_4_WIDTH 3 -#define D18F6x80_CableSafeDisAux_6_4_MASK 0x7000000 -#define D18F6x80_Reserved_31_27_OFFSET 27 -#define D18F6x80_Reserved_31_27_WIDTH 5 -#define D18F6x80_Reserved_31_27_MASK 0xf8000000 - -/// D18F6x80 -typedef union { - struct { ///< - UINT32 Reserved_19_0:20; ///< - UINT32 CableSafeDisAux_3_1:3 ; ///< - UINT32 Reserved_23_23:1 ; ///< - UINT32 CableSafeDisAux_6_4:3 ; ///< - UINT32 Reserved_31_27:5 ; ///< - } Field; ///< - UINT32 Value; ///< -} D18F6x80_STRUCT; - -// **** D0F0x64_x1C Register Definition **** -// Address -#define D0F0x64_x1C_ADDRESS 0x1c - -// Type -#define D0F0x64_x1C_TYPE TYPE_D0F0x64 -// Field Data -#define D0F0x64_x1C_WriteDis_OFFSET 0 -#define D0F0x64_x1C_WriteDis_WIDTH 1 -#define D0F0x64_x1C_WriteDis_MASK 0x1 -#define D0F0x64_x1C_F0NonlegacyDeviceTypeEn_OFFSET 1 -#define D0F0x64_x1C_F0NonlegacyDeviceTypeEn_WIDTH 1 -#define D0F0x64_x1C_F0NonlegacyDeviceTypeEn_MASK 0x2 -#define D0F0x64_x1C_F064BarEn_OFFSET 2 -#define D0F0x64_x1C_F064BarEn_WIDTH 1 -#define D0F0x64_x1C_F064BarEn_MASK 0x4 -#define D0F0x64_x1C_MemApSize_OFFSET 3 -#define D0F0x64_x1C_MemApSize_WIDTH 3 -#define D0F0x64_x1C_MemApSize_MASK 0x38 -#define D0F0x64_x1C_RegApSize_OFFSET 6 -#define D0F0x64_x1C_RegApSize_WIDTH 1 -#define D0F0x64_x1C_RegApSize_MASK 0x40 -#define D0F0x64_x1C_DualfuncDisplayEn_OFFSET 7 -#define D0F0x64_x1C_DualfuncDisplayEn_WIDTH 1 -#define D0F0x64_x1C_DualfuncDisplayEn_MASK 0x80 -#define D0F0x64_x1C_AudioEn_OFFSET 8 -#define D0F0x64_x1C_AudioEn_WIDTH 1 -#define D0F0x64_x1C_AudioEn_MASK 0x100 -#define D0F0x64_x1C_MsiDis_OFFSET 9 -#define D0F0x64_x1C_MsiDis_WIDTH 1 -#define D0F0x64_x1C_MsiDis_MASK 0x200 -#define D0F0x64_x1C_AudioNonlegacyDeviceTypeEn_OFFSET 10 -#define D0F0x64_x1C_AudioNonlegacyDeviceTypeEn_WIDTH 1 -#define D0F0x64_x1C_AudioNonlegacyDeviceTypeEn_MASK 0x400 -#define D0F0x64_x1C_Audio64BarEn_OFFSET 11 -#define D0F0x64_x1C_Audio64BarEn_WIDTH 1 -#define D0F0x64_x1C_Audio64BarEn_MASK 0x800 -#define D0F0x64_x1C_VgaDis_OFFSET 12 -#define D0F0x64_x1C_VgaDis_WIDTH 1 -#define D0F0x64_x1C_VgaDis_MASK 0x1000 -#define D0F0x64_x1C_FbAlwaysOn_OFFSET 13 -#define D0F0x64_x1C_FbAlwaysOn_WIDTH 1 -#define D0F0x64_x1C_FbAlwaysOn_MASK 0x2000 -#define D0F0x64_x1C_FbCplTypeSel_OFFSET 14 -#define D0F0x64_x1C_FbCplTypeSel_WIDTH 2 -#define D0F0x64_x1C_FbCplTypeSel_MASK 0xc000 -#define D0F0x64_x1C_IoBarDis_OFFSET 16 -#define D0F0x64_x1C_IoBarDis_WIDTH 1 -#define D0F0x64_x1C_IoBarDis_MASK 0x10000 -#define D0F0x64_x1C_F0En_OFFSET 17 -#define D0F0x64_x1C_F0En_WIDTH 1 -#define D0F0x64_x1C_F0En_MASK 0x20000 -#define D0F0x64_x1C_F0BarEn_OFFSET 18 -#define D0F0x64_x1C_F0BarEn_WIDTH 1 -#define D0F0x64_x1C_F0BarEn_MASK 0x40000 -#define D0F0x64_x1C_F1BarEn_OFFSET 19 -#define D0F0x64_x1C_F1BarEn_WIDTH 1 -#define D0F0x64_x1C_F1BarEn_MASK 0x80000 -#define D0F0x64_x1C_F2BarEn_OFFSET 20 -#define D0F0x64_x1C_F2BarEn_WIDTH 1 -#define D0F0x64_x1C_F2BarEn_MASK 0x100000 -#define D0F0x64_x1C_PcieDis_OFFSET 21 -#define D0F0x64_x1C_PcieDis_WIDTH 1 -#define D0F0x64_x1C_PcieDis_MASK 0x200000 -#define D0F0x64_x1C_BifBxcntlSpare0_OFFSET 22 -#define D0F0x64_x1C_BifBxcntlSpare0_WIDTH 1 -#define D0F0x64_x1C_BifBxcntlSpare0_MASK 0x400000 -#define D0F0x64_x1C_RcieEn_OFFSET 23 -#define D0F0x64_x1C_RcieEn_WIDTH 1 -#define D0F0x64_x1C_RcieEn_MASK 0x800000 -#define D0F0x64_x1C_BifBxcntlSpare_OFFSET 24 -#define D0F0x64_x1C_BifBxcntlSpare_WIDTH 8 -#define D0F0x64_x1C_BifBxcntlSpare_MASK 0xff000000 - -/// D0F0x64_x1C -typedef union { - struct { ///< - UINT32 WriteDis:1 ; ///< - UINT32 F0NonlegacyDeviceTypeEn:1 ; ///< - UINT32 F064BarEn:1 ; ///< - UINT32 MemApSize:3 ; ///< - UINT32 RegApSize:1 ; ///< - UINT32 DualfuncDisplayEn:1 ; ///< - UINT32 AudioEn:1 ; ///< - UINT32 MsiDis:1 ; ///< - UINT32 AudioNonlegacyDeviceTypeEn:1 ; ///< - UINT32 Audio64BarEn:1 ; ///< - UINT32 VgaDis:1 ; ///< - UINT32 FbAlwaysOn:1 ; ///< - UINT32 FbCplTypeSel:2 ; ///< - UINT32 IoBarDis:1 ; ///< - UINT32 F0En:1 ; ///< - UINT32 F0BarEn:1 ; ///< - UINT32 F1BarEn:1 ; ///< - UINT32 F2BarEn:1 ; ///< - UINT32 PcieDis:1 ; ///< - UINT32 BifBxcntlSpare0:1 ; ///< - UINT32 RcieEn:1 ; ///< - UINT32 BifBxcntlSpare:8 ; ///< - } Field; ///< - UINT32 Value; ///< -} D0F0x64_x1C_STRUCT; - -// **** GMMx00 Register Definition **** -// Address -#define GMMx00_ADDRESS 0x0 - -// Type -#define GMMx00_TYPE TYPE_GMM -// Field Data -#define GMMx00_Offset_OFFSET 0 -#define GMMx00_Offset_WIDTH 31 -#define GMMx00_Offset_MASK 0x7fffffff -#define GMMx00_Aper_OFFSET 31 -#define GMMx00_Aper_WIDTH 1 -#define GMMx00_Aper_MASK 0x80000000 - -/// GMMx00 -typedef union { - struct { ///< - UINT32 Offset:31; ///< - UINT32 Aper:1 ; ///< - } Field; ///< - UINT32 Value; ///< -} GMMx00_STRUCT; - -// **** GMMx04 Register Definition **** -// Address -#define GMMx04_ADDRESS 0x4 - -// Type -#define GMMx04_TYPE TYPE_GMM -// Field Data -#define GMMx04_Data_OFFSET 0 -#define GMMx04_Data_WIDTH 32 -#define GMMx04_Data_MASK 0xffffffff - -/// GMMx04 -typedef union { - struct { ///< - UINT32 Data:32; ///< - } Field; ///< - UINT32 Value; ///< -} GMMx04_STRUCT; - -// **** D18F3xD4 Register Definition **** -// Address -#define D18F3xD4_ADDRESS 0xd4 - -// Type -#define D18F3xD4_TYPE TYPE_D18F3 -// Field Data -#define D18F3xD4_MainPllOpFreqId_OFFSET 0 -#define D18F3xD4_MainPllOpFreqId_WIDTH 6 -#define D18F3xD4_MainPllOpFreqId_MASK 0x3f -#define D18F3xD4_Reserved_6_6_OFFSET 6 -#define D18F3xD4_Reserved_6_6_WIDTH 1 -#define D18F3xD4_Reserved_6_6_MASK 0x40 -#define D18F3xD4_ShallowHaltDidAllow_OFFSET 7 -#define D18F3xD4_ShallowHaltDidAllow_WIDTH 1 -#define D18F3xD4_ShallowHaltDidAllow_MASK 0x80 -#define D18F3xD4_ClkRampHystSel_OFFSET 8 -#define D18F3xD4_ClkRampHystSel_WIDTH 4 -#define D18F3xD4_ClkRampHystSel_MASK 0xf00 -#define D18F3xD4_OnionOutHyst_OFFSET 12 -#define D18F3xD4_OnionOutHyst_WIDTH 4 -#define D18F3xD4_OnionOutHyst_MASK 0xf000 -#define D18F3xD4_DisNclkGatingIdle_OFFSET 16 -#define D18F3xD4_DisNclkGatingIdle_WIDTH 1 -#define D18F3xD4_DisNclkGatingIdle_MASK 0x10000 -#define D18F3xD4_ClockGatingEnDram_OFFSET 17 -#define D18F3xD4_ClockGatingEnDram_WIDTH 1 -#define D18F3xD4_ClockGatingEnDram_MASK 0x20000 -#define D18F3xD4_Reserved_31_18_OFFSET 18 -#define D18F3xD4_Reserved_31_18_WIDTH 14 -#define D18F3xD4_Reserved_31_18_MASK 0xfffc0000 - -/// D18F3xD4 -typedef union { - struct { ///< - UINT32 MainPllOpFreqId:6 ; ///< - UINT32 Reserved_6_6:1 ; ///< - UINT32 ShallowHaltDidAllow:1 ; ///< - UINT32 ClkRampHystSel:4 ; ///< - UINT32 OnionOutHyst:4 ; ///< - UINT32 DisNclkGatingIdle:1 ; ///< - UINT32 ClockGatingEnDram:1 ; ///< - UINT32 Reserved_31_18:14; ///< - } Field; ///< - UINT32 Value; ///< -} D18F3xD4_STRUCT; - - -// **** D18F2x09C_x0D0FE00A Register Definition **** -// Address -#define D18F2x09C_x0D0FE00A_ADDRESS 0x0D0FE00A - -// Type -#define D18F2x09C_x0D0FE00A_TYPE TYPE_D18F2x9C -// Field Data -#define D18F2x09C_x0D0FE00A_Reserved_3_0_OFFSET 0 -#define D18F2x09C_x0D0FE00A_Reserved_3_0_WIDTH 4 -#define D18F2x09C_x0D0FE00A_Reserved_3_0_MASK 0xF -#define D18F2x09C_x0D0FE00A_SkewMemClk_OFFSET 4 -#define D18F2x09C_x0D0FE00A_SkewMemClk_WIDTH 1 -#define D18F2x09C_x0D0FE00A_SkewMemClk_MASK 0x10 -#define D18F2x09C_x0D0FE00A_Reserved_11_5_OFFSET 5 -#define D18F2x09C_x0D0FE00A_Reserved_11_5_WIDTH 7 -#define D18F2x09C_x0D0FE00A_Reserved_11_5_MASK 0xFE0 -#define D18F2x09C_x0D0FE00A_CsrPhySrPllPdMode_OFFSET 12 -#define D18F2x09C_x0D0FE00A_CsrPhySrPllPdMode_WIDTH 2 -#define D18F2x09C_x0D0FE00A_CsrPhySrPllPdMode_MASK 0x3000 -#define D18F2x09C_x0D0FE00A_SelCsrPllPdMode_OFFSET 14 -#define D18F2x09C_x0D0FE00A_SelCsrPllPdMode_WIDTH 1 -#define D18F2x09C_x0D0FE00A_SelCsrPllPdMode_MASK 0x4000 -#define D18F2x09C_x0D0FE00A_Reserved_31_15_OFFSET 15 -#define D18F2x09C_x0D0FE00A_Reserved_31_15_WIDTH 17 -#define D18F2x09C_x0D0FE00A_Reserved_31_15_MASK 0xFFFF8000 - -/// D18F2x09C_x0D0FE00A -typedef union { - struct { ///< - UINT32 Reserved_3_0:4; ///< - UINT32 SkewMemClk:1; ///< - UINT32 Reserved_11_5:7; ///< - UINT32 CsrPhySrPllPdMode:2; ///< - UINT32 SelCsrPllPdMode:1; ///< - UINT32 Reserved_31_15:17; ///< - } Field; ///< - UINT32 Value; ///< -} D18F2x09C_x0D0FE00A_STRUCT; - -// **** D0F0x64_x46 Register Definition **** -// Address -#define D0F0x64_x46_ADDRESS 0x46 - -// Type -#define D0F0x64_x46_TYPE TYPE_D0F0x64 -// Field Data -#define D0F0x64_x46_Reserved_0_0_OFFSET 0 -#define D0F0x64_x46_Reserved_0_0_WIDTH 1 -#define D0F0x64_x46_Reserved_0_0_MASK 0x1 -#define D0F0x64_x46_P2PMode_OFFSET 1 -#define D0F0x64_x46_P2PMode_WIDTH 2 -#define D0F0x64_x46_P2PMode_MASK 0x6 -#define D0F0x64_x46_Reserved_15_3_OFFSET 3 -#define D0F0x64_x46_Reserved_15_3_WIDTH 13 -#define D0F0x64_x46_Reserved_15_3_MASK 0xfff8 -#define D0F0x64_x46_Msi64bitEn_OFFSET 16 -#define D0F0x64_x46_Msi64bitEn_WIDTH 1 -#define D0F0x64_x46_Msi64bitEn_MASK 0x10000 -#define D0F0x64_x46_Reserved_31_17_OFFSET 17 -#define D0F0x64_x46_Reserved_31_17_WIDTH 15 -#define D0F0x64_x46_Reserved_31_17_MASK 0xfffe0000 - -/// D0F0x64_x46 -typedef union { - struct { ///< - UINT32 Reserved_0_0:1 ; ///< - UINT32 P2PMode:2 ; ///< - UINT32 Reserved_15_3:13; ///< - UINT32 Msi64bitEn:1 ; ///< - UINT32 Reserved_31_17:15; ///< - } Field; ///< - UINT32 Value; ///< -} D0F0x64_x46_STRUCT; - -// **** D0F0xE4_WRAP_8016 Register Definition **** -// Address -#define D0F0xE4_WRAP_8016_ADDRESS 0x8016 - -// Type -#define D0F0xE4_WRAP_8016_TYPE TYPE_D0F0xE4 -// Field Data -#define D0F0xE4_WRAP_8016_CalibAckLatency_OFFSET 0 -#define D0F0xE4_WRAP_8016_CalibAckLatency_WIDTH 6 -#define D0F0xE4_WRAP_8016_CalibAckLatency_MASK 0x3f -#define D0F0xE4_WRAP_8016_Reserved_15_6_OFFSET 6 -#define D0F0xE4_WRAP_8016_Reserved_15_6_WIDTH 10 -#define D0F0xE4_WRAP_8016_Reserved_15_6_MASK 0xffc0 -#define D0F0xE4_WRAP_8016_LclkDynGateLatency_OFFSET 16 -#define D0F0xE4_WRAP_8016_LclkDynGateLatency_WIDTH 6 -#define D0F0xE4_WRAP_8016_LclkDynGateLatency_MASK 0x3f0000 -#define D0F0xE4_WRAP_8016_LclkGateFree_OFFSET 22 -#define D0F0xE4_WRAP_8016_LclkGateFree_WIDTH 1 -#define D0F0xE4_WRAP_8016_LclkGateFree_MASK 0x400000 -#define D0F0xE4_WRAP_8016_LclkDynGateEnable_OFFSET 23 -#define D0F0xE4_WRAP_8016_LclkDynGateEnable_WIDTH 1 -#define D0F0xE4_WRAP_8016_LclkDynGateEnable_MASK 0x800000 -#define D0F0xE4_WRAP_8016_Reserved_31_24_OFFSET 24 -#define D0F0xE4_WRAP_8016_Reserved_31_24_WIDTH 8 -#define D0F0xE4_WRAP_8016_Reserved_31_24_MASK 0xff000000 - -/// D0F0xE4_WRAP_8016 -typedef union { - struct { ///< - UINT32 CalibAckLatency:6 ; ///< - UINT32 Reserved_15_6:10; ///< - UINT32 LclkDynGateLatency:6 ; ///< - UINT32 LclkGateFree:1 ; ///< - UINT32 LclkDynGateEnable:1 ; ///< - UINT32 Reserved_31_24:8 ; ///< - } Field; ///< - UINT32 Value; ///< -} D0F0xE4_WRAP_8016_STRUCT; - -// **** SMUx0B_x8400 Register Definition **** -// Address -#define SMUx0B_x8400_ADDRESS 0x8400 - -// **** SMUx0B_x85AC Register Definition **** -// Address -#define SMUx0B_x85AC_ADDRESS 0x85ac - -// **** SMUx0B_x9000 Register Definition **** -// Address -#define SMUx0B_x9000_ADDRESS 0x9000 - -// **** SMUx0B_x9004 Register Definition **** -// Address -#define SMUx0B_x9004_ADDRESS 0x9004 -// **** D18F6x78 Register Definition **** -// Address -#define D18F6x78_ADDRESS 0x78 - -// Type -#define D18F6x78_TYPE TYPE_D18F6 -// Field Data -#define D18F6x78_DispDbePrioEn_OFFSET 0 -#define D18F6x78_DispDbePrioEn_WIDTH 2 -#define D18F6x78_DispDbePrioEn_MASK 0x3 -#define D18F6x78_FeqDbePrioEn_OFFSET 2 -#define D18F6x78_FeqDbePrioEn_WIDTH 1 -#define D18F6x78_FeqDbePrioEn_MASK 0x4 -#define D18F6x78_DispArbCtrl_OFFSET 3 -#define D18F6x78_DispArbCtrl_WIDTH 1 -#define D18F6x78_DispArbCtrl_MASK 0x8 -#define D18F6x78_GlcEosDet_OFFSET 4 -#define D18F6x78_GlcEosDet_WIDTH 2 -#define D18F6x78_GlcEosDet_MASK 0x30 -#define D18F6x78_GlcEosDetDis_OFFSET 6 -#define D18F6x78_GlcEosDetDis_WIDTH 1 -#define D18F6x78_GlcEosDetDis_MASK 0x40 -#define D18F6x78_Reserved_7_7_OFFSET 7 -#define D18F6x78_Reserved_7_7_WIDTH 1 -#define D18F6x78_Reserved_7_7_MASK 0x80 -#define D18F6x78_DbeCmdThrottle_OFFSET 8 -#define D18F6x78_DbeCmdThrottle_WIDTH 8 -#define D18F6x78_DbeCmdThrottle_MASK 0xff00 -#define D18F6x78_Reserved_31_16_OFFSET 16 -#define D18F6x78_Reserved_31_16_WIDTH 16 -#define D18F6x78_Reserved_31_16_MASK 0xffff0000 - -/// D18F6x78 -typedef union { - struct { ///EngineData.StartLane && - DdiLaneConfigArray[DisplayPathIndex][1] == Engine->EngineData.EndLane) { - PrimaryDisplayPathId = DdiLaneConfigArray[DisplayPathIndex][2]; - SecondaryDisplayPathId = DdiLaneConfigArray[DisplayPathIndex][3]; - break; - } - } - if (PrimaryDisplayPathId != 0xff) { - IDS_HDT_CONSOLE (GFX_MISC, " Allocate Display Connector at Primary sPath[%d]\n", PrimaryDisplayPathId); - Engine->InitStatus |= INIT_STATUS_DDI_ACTIVE; - GfxIntegratedCopyDisplayInfo ( - Engine, - &DisplayPathList[PrimaryDisplayPathId], - (PrimaryDisplayPathId != SecondaryDisplayPathId) ? &DisplayPathList[SecondaryDisplayPathId] : NULL, - Gfx - ); - Status = AGESA_SUCCESS; - } else { - IDS_HDT_CONSOLE (GFX_MISC, " Error!!! Map DDI lanes %d - %d to display path failed\n", - Engine->EngineData.StartLane, - Engine->EngineData.EndLane - ); - PutEventLog ( - AGESA_ERROR, - GNB_EVENT_INVALID_DDI_LINK_CONFIGURATION, - Engine->EngineData.StartLane, - Engine->EngineData.EndLane, - 0, - 0, - GnbLibGetHeader (Gfx) - ); - Status = AGESA_ERROR; - } - return Status; -} - - -/*----------------------------------------------------------------------------------------*/ -/** - * Family specific integrated info table init - * - * - * @param[in] IntegratedInfoTable Integrated info table pointer - * @param[in] Gfx Gfx configuration info - */ - -VOID -GfxFmIntegratedInfoTableInit ( - IN OUT ATOM_INTEGRATED_SYSTEM_INFO_V6 *IntegratedInfoTable, - IN GFX_PLATFORM_CONFIG *Gfx - ) -{ - IntegratedInfoTable->ulDDR_DLL_PowerUpTime = 2380; - IntegratedInfoTable->ulDDR_PLL_PowerUpTime = 3400; - IntegratedInfoTable->ulGMCRestoreResetTime = F12NbPowerGateGmcRestoreLatency (GnbLibGetHeader (Gfx)); - if (((Gfx->UmaInfo.UmaAttributes & UMA_ATTRIBUTE_INTERLEAVE) == 0) && ((LibAmdGetPackageType (GnbLibGetHeader (Gfx)) & PACKAGE_TYPE_FM1) != 0)) { - GnbLibPciRMW ( - MAKE_SBDFO (0, 0, 0x18, 6, D18F6x78_ADDRESS), - AccessS3SaveWidth32, - 0xffffffff, - 1 << D18F6x78_DispArbCtrl_OFFSET, - GnbLibGetHeader (Gfx) - ); - } -} - - -/*----------------------------------------------------------------------------------------*/ -/** - * Family specific address swizzle settings. - * - * - * @param[in] Gfx Gfx configuration info - */ - -VOID -GfxFmGmcAddressSwizzel ( - IN GFX_PLATFORM_CONFIG *Gfx - ) -{ - GMMx2864_STRUCT GMMx2864; - GMMx2868_STRUCT GMMx2868; - UCHAR EffectiveChannels; - GMMx2864.Value = GmmRegisterRead (GMMx2864_ADDRESS, Gfx); - if (GMMx2864.Value == 0) { - // Check if two memory channels - EffectiveChannels = ((Gfx->UmaInfo.UmaAttributes & UMA_ATTRIBUTE_INTERLEAVE) == 0) ? 1 : 2; - if (EffectiveChannels == 2) { - GMMx2864.Value = 0x32009817; // Value for two channels - GMMx2868.Value = 0x00000004; - GmmRegisterWrite (GMMx2868_ADDRESS, GMMx2868.Value, TRUE, Gfx); - } else { - GMMx2864.Value = 0x32100876; // Value for single channel - } - GmmRegisterWrite ( - GMMx2864_ADDRESS, - GMMx2864.Value, - TRUE, - Gfx - ); - } -} - -/*----------------------------------------------------------------------------------------*/ - -VOID -GfxFmGmcAllowPstateHigh ( - IN GFX_PLATFORM_CONFIG *Gfx - ) -{ -} - -/*----------------------------------------------------------------------------------------*/ -/** - * Calculate COF for DFS out of Main PLL - * - * - * - * @param[in] Did Did - * @param[in] StdHeader Standard Configuration Header - * @retval COF in 10khz - */ - -UINT32 -GfxFmCalculateClock ( - IN UINT8 Did, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - UINT32 MainPllFreq10kHz; - MainPllFreq10kHz = GfxLibGetMainPllFreq (StdHeader) * 100; - return GfxLibCalculateClk (Did, MainPllFreq10kHz); -} - -/*----------------------------------------------------------------------------------------*/ -/** - * Set idle voltage mode for GFX - * - * - * @param[in] Gfx Pointer to global GFX configuration - */ - -VOID -GfxFmSetIdleVoltageMode ( - IN GFX_PLATFORM_CONFIG *Gfx - ) -{ - FCRxFF30_0191_STRUCT FCRxFF30_0191; - NbSmuSrbmRegisterRead (FCRxFF30_0191_ADDRESS, &FCRxFF30_0191.Value, GnbLibGetHeader (Gfx)); - FCRxFF30_0191.Field.GfxIdleVoltChgMode = (Gfx->GfxFusedOff || Gfx->UmaInfo.UmaMode != UMA_NONE) ? 0x0 : 0x1; - NbSmuSrbmRegisterWrite (FCRxFF30_0191_ADDRESS, &FCRxFF30_0191.Value, TRUE, GnbLibGetHeader (Gfx)); -} - -/*---------------------------------------------------------------------------------------- - * GMC Disable Clock Gating - *---------------------------------------------------------------------------------------- - */ - - -GMM_REG_ENTRY GmcDisableClockGating[] = { - { GMMx20C0_ADDRESS, 0x00000C80 }, - { GMMx2478_ADDRESS, 0x00000400 }, - { GMMx20B8_ADDRESS, 0x00000400 }, - { GMMx20BC_ADDRESS, 0x00000400 }, - { GMMx2650_ADDRESS, 0x00000400 }, - { GMMx2654_ADDRESS, 0x00000400 }, - { GMMx2658_ADDRESS, 0x00000400 }, - { GMMx15C0_ADDRESS, 0x00081401 } -}; - -TABLE_INDIRECT_PTR GmcDisableClockGatingPtr = { - sizeof (GmcDisableClockGating) / sizeof (GMM_REG_ENTRY), - GmcDisableClockGating -}; - - -/*---------------------------------------------------------------------------------------- - * GMC Enable Clock Gating - *---------------------------------------------------------------------------------------- - */ -GMM_REG_ENTRY GmcEnableClockGating[] = { - { GMMx20C0_ADDRESS, 0x00040C80 }, - { GMMx2478_ADDRESS, 0x00040400 }, - { GMMx20B8_ADDRESS, 0x00040400 }, - { GMMx20BC_ADDRESS, 0x00040400 }, - { GMMx2650_ADDRESS, 0x00040400 }, - { GMMx2654_ADDRESS, 0x00040400 }, - { GMMx2658_ADDRESS, 0x00040400 }, - { GMMx15C0_ADDRESS, 0x000C1401 } -}; - - -TABLE_INDIRECT_PTR GmcEnableClockGatingPtr = { - sizeof (GmcEnableClockGating) / sizeof (GMM_REG_ENTRY), - GmcEnableClockGating -}; - -/*---------------------------------------------------------------------------------------- - * GMC Performance Tuning - *---------------------------------------------------------------------------------------- - */ -GMM_REG_ENTRY GmcPerformanceTuningTable [] = { - { GMMx27CC_ADDRESS, 0x00032005 }, - { GMMx27DC_ADDRESS, 0x00734847 }, - { GMMx27D0_ADDRESS, 0x00012008 }, - { GMMx27E0_ADDRESS, 0x00003D3C }, - { GMMx2784_ADDRESS, 0x00000007 }, - { GMMx21C8_ADDRESS, 0x0000A1F1 }, - { GMMx217C_ADDRESS, 0x0000A1F1 }, - { GMMx2188_ADDRESS, 0x000221b1 }, - { GMMx2814_ADDRESS, 0x00000200 }, - { GMMx201C_ADDRESS, 0x03330003 }, - { GMMx2020_ADDRESS, 0x70760007 }, - { GMMx2018_ADDRESS, 0x00000050 }, - { GMMx2014_ADDRESS, 0x00005500 }, - { GMMx2620_ADDRESS, 0x44111222 }, - { GMMx2628_ADDRESS, 0x44111666 }, - { GMMx2630_ADDRESS, 0x00000044 }, - { GMMx2624_ADDRESS, 0x11333111 }, - { GMMx262C_ADDRESS, 0x21444222 }, - { GMMx2634_ADDRESS, 0x00000043 }, - { GMMx279C_ADDRESS, 0xfcfcfdfc }, - { GMMx27A0_ADDRESS, 0xfcfcfdfc } -}; - -TABLE_INDIRECT_PTR GmcPerformanceTuningTablePtr = { - sizeof (GmcPerformanceTuningTable) / sizeof (GMM_REG_ENTRY), - GmcPerformanceTuningTable -}; - - -/*---------------------------------------------------------------------------------------- - * GMC Misc init table - *---------------------------------------------------------------------------------------- - */ -GMM_REG_ENTRY GmcMiscInitTable [] = { - { GMMx25C8_ADDRESS, 0x007F605F }, - { GMMx25CC_ADDRESS, 0x00007F7E }, - { GMMx28EC_ADDRESS, 0x00187000 }, - { GMMx202C_ADDRESS, 0x0003FFFF } -}; - -TABLE_INDIRECT_PTR GmcMiscInitTablePtr = { - sizeof (GmcMiscInitTable) / sizeof (GMM_REG_ENTRY), - GmcMiscInitTable -}; - - -/*---------------------------------------------------------------------------------------- - * GMC Remove blackout - *---------------------------------------------------------------------------------------- - */ -GMM_REG_ENTRY GmcRemoveBlackoutTable [] = { - { GMMx25C0_ADDRESS, 0x00000000 }, - { GMMx20EC_ADDRESS, 0x000001FC }, - { GMMx20D4_ADDRESS, 0x00000016 } -}; - -TABLE_INDIRECT_PTR GmcRemoveBlackoutTablePtr = { - sizeof (GmcRemoveBlackoutTable) / sizeof (GMM_REG_ENTRY), - GmcRemoveBlackoutTable -}; - - - -/*---------------------------------------------------------------------------------------- - * GMC Register Engine Init Table - *---------------------------------------------------------------------------------------- - */ - -GMM_REG_ENTRY GmcRegisterEngineInitTable [] = { - { GMMx2B8C_ADDRESS, 0x00000000 }, - { GMMx2B90_ADDRESS, 0x001e0a07 }, - { GMMx2B8C_ADDRESS, 0x00000020 }, - { GMMx2B90_ADDRESS, 0x00050500 }, - { GMMx2B8C_ADDRESS, 0x00000027 }, - { GMMx2B90_ADDRESS, 0x0001050c }, - { GMMx2B8C_ADDRESS, 0x0000002a }, - { GMMx2B90_ADDRESS, 0x0001051c }, - { GMMx2B8C_ADDRESS, 0x0000002d }, - { GMMx2B90_ADDRESS, 0x00030534 }, - { GMMx2B8C_ADDRESS, 0x00000032 }, - { GMMx2B90_ADDRESS, 0x0001053e }, - { GMMx2B8C_ADDRESS, 0x00000035 }, - { GMMx2B90_ADDRESS, 0x00010546 }, - { GMMx2B8C_ADDRESS, 0x00000038 }, - { GMMx2B90_ADDRESS, 0x0002054e }, - { GMMx2B8C_ADDRESS, 0x0000003c }, - { GMMx2B90_ADDRESS, 0x00010557 }, - { GMMx2B8C_ADDRESS, 0x0000003f }, - { GMMx2B90_ADDRESS, 0x0001055f }, - { GMMx2B8C_ADDRESS, 0x00000042 }, - { GMMx2B90_ADDRESS, 0x00010567 }, - { GMMx2B8C_ADDRESS, 0x00000045 }, - { GMMx2B90_ADDRESS, 0x0001056f }, - { GMMx2B8C_ADDRESS, 0x00000048 }, - { GMMx2B90_ADDRESS, 0x00050572 }, - { GMMx2B8C_ADDRESS, 0x0000004f }, - { GMMx2B90_ADDRESS, 0x00000800 }, - { GMMx2B8C_ADDRESS, 0x00000051 }, - { GMMx2B90_ADDRESS, 0x00260801 }, - { GMMx2B8C_ADDRESS, 0x00000079 }, - { GMMx2B90_ADDRESS, 0x004b082d }, - { GMMx2B8C_ADDRESS, 0x000000c6 }, - { GMMx2B90_ADDRESS, 0x0013088d }, - { GMMx2B8C_ADDRESS, 0x000000db }, - { GMMx2B90_ADDRESS, 0x100008a1 }, - { GMMx2B90_ADDRESS, 0x00000040 }, - { GMMx2B90_ADDRESS, 0x00000040 }, - { GMMx2B8C_ADDRESS, 0x000000df }, - { GMMx2B90_ADDRESS, 0x000008a2 }, - { GMMx2B8C_ADDRESS, 0x000000e1 }, - { GMMx2B90_ADDRESS, 0x005a08cd }, - { GMMx2B8C_ADDRESS, 0x0000013d }, - { GMMx2B90_ADDRESS, 0x0001094d }, - { GMMx2B8C_ADDRESS, 0x00000140 }, - { GMMx2B90_ADDRESS, 0x00000952 }, - { GMMx2B8C_ADDRESS, 0x00000142 }, - { GMMx2B90_ADDRESS, 0x00010954 }, - { GMMx2B8C_ADDRESS, 0x00000145 }, - { GMMx2B90_ADDRESS, 0x0009095a }, - { GMMx2B8C_ADDRESS, 0x00000150 }, - { GMMx2B90_ADDRESS, 0x0029096d }, - { GMMx2B8C_ADDRESS, 0x0000017b }, - { GMMx2B90_ADDRESS, 0x000e0997 }, - { GMMx2B8C_ADDRESS, 0x0000018b }, - { GMMx2B90_ADDRESS, 0x100009a6 }, - { GMMx2B90_ADDRESS, 0x00000040 }, - { GMMx2B90_ADDRESS, 0x00000040 }, - { GMMx2B8C_ADDRESS, 0x0000018f }, - { GMMx2B90_ADDRESS, 0x000009a7 }, - { GMMx2B8C_ADDRESS, 0x00000191 }, - { GMMx2B90_ADDRESS, 0x002e09d7 }, - { GMMx2B8C_ADDRESS, 0x000001c1 }, - { GMMx2B90_ADDRESS, 0x00170a26 }, - { GMMx2B94_ADDRESS, 0x765d9000 }, - { GMMx2B98_ADDRESS, 0x410af020 } -}; - -TABLE_INDIRECT_PTR GmcRegisterEngineInitTablePtr = { - sizeof (GmcRegisterEngineInitTable) / sizeof (GMM_REG_ENTRY), - GmcRegisterEngineInitTable -}; - - -/*---------------------------------------------------------------------------------------- - * GMC Address Translation Table - *---------------------------------------------------------------------------------------- - */ -REGISTER_COPY_ENTRY CnbToGncRegisterCopyTable [] = { - { - MAKE_SBDFO (0, 0, 0x18, 2, D18F2x040_ADDRESS), - GMMx281C_ADDRESS, - 0, - 31, - 0, - 31 - }, - { - MAKE_SBDFO (0, 0, 0x18, 2, D18F2x140_ADDRESS), - GMMx2820_ADDRESS, - 0, - 31, - 0, - 31 - }, - { - MAKE_SBDFO (0, 0, 0x18, 2, D18F2x044_ADDRESS), - GMMx2824_ADDRESS, - 0, - 31, - 0, - 31 - }, - { - MAKE_SBDFO (0, 0, 0x18, 2, D18F2x144_ADDRESS), - GMMx2828_ADDRESS, - 0, - 31, - 0, - 31 - }, - { - MAKE_SBDFO (0, 0, 0x18, 2, D18F2x048_ADDRESS), - GMMx282C_ADDRESS, - 0, - 31, - 0, - 31 - }, - { - MAKE_SBDFO (0, 0, 0x18, 2, D18F2x148_ADDRESS), - GMMx2830_ADDRESS, - 0, - 31, - 0, - 31 - }, - { - MAKE_SBDFO (0, 0, 0x18, 2, D18F2x04C_ADDRESS), - GMMx2834_ADDRESS, - 0, - 31, - 0, - 31 - }, - { - MAKE_SBDFO (0, 0, 0x18, 2, D18F2x14C_ADDRESS), - GMMx2838_ADDRESS, - 0, - 31, - 0, - 31 - }, - { - MAKE_SBDFO (0, 0, 0x18, 2, D18F2x060_ADDRESS), - GMMx283C_ADDRESS, - 0, - 31, - 0, - 31 - }, - { - MAKE_SBDFO (0, 0, 0x18, 2, D18F2x064_ADDRESS), - GMMx2840_ADDRESS, - 0, - 31, - 0, - 31 - }, - { - MAKE_SBDFO (0, 0, 0x18, 2, D18F2x160_ADDRESS), - GMMx2844_ADDRESS, - 0, - 31, - 0, - 31 - }, - { - MAKE_SBDFO (0, 0, 0x18, 2, D18F2x164_ADDRESS), - GMMx2848_ADDRESS, - 0, - 31, - 0, - 31 - }, - { - MAKE_SBDFO (0, 0, 0x18, 2, D18F2x080_ADDRESS), - GMMx284C_ADDRESS, - D18F2x080_Dimm0AddrMap_OFFSET, - D18F2x080_Dimm0AddrMap_WIDTH + D18F2x080_Dimm1AddrMap_WIDTH, - GMMx284C_Dimm0AddrMap_OFFSET, - GMMx284C_Dimm0AddrMap_WIDTH + GMMx284C_Dimm1AddrMap_WIDTH - }, - { - MAKE_SBDFO (0, 0, 0x18, 2, D18F2x094_ADDRESS), - GMMx284C_ADDRESS, - D18F2x094_BankSwizzleMode_OFFSET, - D18F2x094_BankSwizzleMode_WIDTH, - GMMx284C_BankSwizzleMode_OFFSET, - GMMx284C_BankSwizzleMode_WIDTH - }, - { - MAKE_SBDFO (0, 0, 0x18, 2, D18F2x0A8_ADDRESS), - GMMx284C_ADDRESS, - D18F2x0A8_BankSwap_OFFSET, - D18F2x0A8_BankSwap_WIDTH, - GMMx284C_BankSwap_OFFSET, - GMMx284C_BankSwap_WIDTH - }, - { - MAKE_SBDFO (0, 0, 0x18, 2, D18F2x180_ADDRESS), - GMMx2850_ADDRESS, - D18F2x180_Dimm0AddrMap_OFFSET, - D18F2x180_Dimm0AddrMap_WIDTH + D18F2x180_Dimm1AddrMap_WIDTH, - GMMx2850_Dimm0AddrMap_OFFSET, - GMMx2850_Dimm0AddrMap_WIDTH + GMMx2850_Dimm1AddrMap_WIDTH - }, - { - MAKE_SBDFO (0, 0, 0x18, 2, D18F2x194_ADDRESS), - GMMx2850_ADDRESS, - D18F2x194_BankSwizzleMode_OFFSET, - D18F2x194_BankSwizzleMode_WIDTH, - GMMx2850_BankSwizzleMode_OFFSET, - GMMx2850_BankSwizzleMode_WIDTH - }, - { - MAKE_SBDFO (0, 0, 0x18, 2, D18F2x1A8_ADDRESS), - GMMx2850_ADDRESS, - D18F2x1A8_BankSwap_OFFSET, - D18F2x1A8_BankSwap_WIDTH, - GMMx2850_BankSwap_OFFSET, - GMMx2850_BankSwap_WIDTH - }, - { - MAKE_SBDFO (0, 0, 0x18, 2, D18F2x110_ADDRESS), - GMMx2854_ADDRESS, - 0, - 31, - 0, - 31 - }, - { - MAKE_SBDFO (0, 0, 0x18, 2, D18F2x114_ADDRESS), - GMMx2858_ADDRESS, - 0, - 31, - 0, - 31 - }, - { - MAKE_SBDFO (0, 0, 0x18, 1, D18F1xF0_ADDRESS), - GMMx285C_ADDRESS, - 0, - 31, - 0, - 31 - }, - { - MAKE_SBDFO (0, 0, 0x18, 2, D18F2x10C_ADDRESS), - GMMx2860_ADDRESS, - 0, - 31, - 0, - 31 - } -}; - - -TABLE_INDIRECT_PTR CnbToGncRegisterCopyTablePtr = { - sizeof (CnbToGncRegisterCopyTable) / sizeof (REGISTER_COPY_ENTRY), - CnbToGncRegisterCopyTable -}; - diff --git a/src/vendorcode/amd/agesa/f12/Proc/GNB/Gfx/Family/LN/Makefile.inc b/src/vendorcode/amd/agesa/f12/Proc/GNB/Gfx/Family/LN/Makefile.inc deleted file mode 100644 index 8b815d8f86..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/GNB/Gfx/Family/LN/Makefile.inc +++ /dev/null @@ -1 +0,0 @@ -libagesa-y += F12GfxServices.c diff --git a/src/vendorcode/amd/agesa/f12/Proc/GNB/Gfx/GfxConfigData.c b/src/vendorcode/amd/agesa/f12/Proc/GNB/Gfx/GfxConfigData.c deleted file mode 100644 index 92cebbe29f..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/GNB/Gfx/GfxConfigData.c +++ /dev/null @@ -1,131 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * Initialize GFX configuration data structure. - * - * - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: GNB - * @e \$Revision: 50010 $ @e \$Date: 2011-03-31 18:07:03 +0800 (Thu, 31 Mar 2011) $ - * - */ -/* -***************************************************************************** -* -* Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* *************************************************************************** -* -*/ - -/*---------------------------------------------------------------------------------------- - * M O D U L E S U S E D - *---------------------------------------------------------------------------------------- - */ -#include "AGESA.h" -#include "amdlib.h" -#include "Ids.h" -#include "heapManager.h" -#include "Gnb.h" -#include "GnbGfx.h" -#include "GnbCommonLib.h" -#include "GfxStrapsInit.h" -#include "OptionGnb.h" -#include "GfxConfigData.h" -#include "Filecode.h" -#define FILECODE PROC_GNB_GFX_GFXCONFIGDATA_FILECODE -/*---------------------------------------------------------------------------------------- - * D E F I N I T I O N S A N D M A C R O S - *---------------------------------------------------------------------------------------- - */ - -extern BUILD_OPT_CFG UserOptions; -extern GNB_BUILD_OPTIONS GnbBuildOptions; - -/*---------------------------------------------------------------------------------------- - * T Y P E D E F S A N D S T R U C T U R E S - *---------------------------------------------------------------------------------------- - */ - - -/*---------------------------------------------------------------------------------------- - * P R O T O T Y P E S O F L O C A L F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ - - -/*----------------------------------------------------------------------------------------*/ -/** - * Enable GMM Access - * - * - * - * @param[in,out] Gfx Pointer to GFX configuration - * @retval AGESA_STATUS - */ - -AGESA_STATUS -GfxEnableGmmAccess ( - IN OUT GFX_PLATFORM_CONFIG *Gfx - ) -{ - UINT32 Value; - - if (!GnbLibPciIsDevicePresent (Gfx->GfxPciAddress.AddressValue, GnbLibGetHeader (Gfx))) { - IDS_ERROR_TRAP; - return AGESA_ERROR; - } - - // Check if base address for GMM allocated - GnbLibPciRead (Gfx->GfxPciAddress.AddressValue | 0x18, AccessWidth32, &Gfx->GmmBase, GnbLibGetHeader (Gfx)); - if (Gfx->GmmBase == 0) { - IDS_ERROR_TRAP; - return AGESA_ERROR; - } - // Check if base address for FB allocated - GnbLibPciRead (Gfx->GfxPciAddress.AddressValue | 0x10, AccessWidth32, &Value, GnbLibGetHeader (Gfx)); - if ((Value & 0xfffffff0) == 0) { - IDS_ERROR_TRAP; - return AGESA_ERROR; - } - //Push CPU MMIO pci config to S3 script - GnbLibS3SaveConfigSpace (MAKE_SBDFO (0, 0, 0x18, 1, 0), 0xBC, 0x80, AccessS3SaveWidth32, GnbLibGetHeader (Gfx)); - // Turn on memory decoding on APC to enable access to GMM register space - if (Gfx->GfxControllerMode == GfxControllerLegacyBridgeMode) { - GnbLibPciRMW (MAKE_SBDFO (0, 0, 1, 0, 0x4), AccessWidth32, 0xffffffff, BIT1 | BIT2, GnbLibGetHeader (Gfx)); - //Push APC pci config to S3 script - GnbLibS3SaveConfigSpace (MAKE_SBDFO (0, 0, 1, 0, 0), 0x2C, 0x18, AccessS3SaveWidth32, GnbLibGetHeader (Gfx)); - GnbLibS3SaveConfigSpace (MAKE_SBDFO (0, 0, 1, 0, 0), 0x4, 0x4, AccessS3SaveWidth16, GnbLibGetHeader (Gfx)); - } - // Turn on memory decoding on GFX to enable access to GMM register space - GnbLibPciRMW (Gfx->GfxPciAddress.AddressValue | 0x4, AccessWidth32, 0xffffffff, BIT1 | BIT2, GnbLibGetHeader (Gfx)); - //Push iGPU pci config to S3 script - GnbLibS3SaveConfigSpace (Gfx->GfxPciAddress.AddressValue, 0x24, 0x10, AccessS3SaveWidth32, GnbLibGetHeader (Gfx)); - GnbLibS3SaveConfigSpace (Gfx->GfxPciAddress.AddressValue, 0x04, 0x04, AccessS3SaveWidth16, GnbLibGetHeader (Gfx)); - return AGESA_SUCCESS; -} diff --git a/src/vendorcode/amd/agesa/f12/Proc/GNB/Gfx/GfxConfigData.h b/src/vendorcode/amd/agesa/f12/Proc/GNB/Gfx/GfxConfigData.h deleted file mode 100644 index bb0ba62807..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/GNB/Gfx/GfxConfigData.h +++ /dev/null @@ -1,74 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * Initialize GFX configuration data structure. - * - * - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: GNB - * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $ - * - */ -/* -***************************************************************************** -* -* Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * -* *************************************************************************** -* -*/ - -#ifndef _GFXCONFIGDATA_H_ -#define _GFXCONFIGDATA_H_ - -AGESA_STATUS -GfxAllocateConfigData ( - IN AMD_CONFIG_PARAMS *StdHeader, - IN OUT GFX_PLATFORM_CONFIG **Gfx, - IN PLATFORM_CONFIGURATION *PlatformConfig - ); - -AGESA_STATUS -GfxEnableGmmAccess ( - IN OUT GFX_PLATFORM_CONFIG *Gfx - ); - -AGESA_STATUS -GfxConfigEnvInterface ( - IN AMD_CONFIG_PARAMS *StdHeader - ); - -/* - VOID -GfxGetUmaInfo ( - OUT UMA_INFO *UmaInfo, - IN AMD_CONFIG_PARAMS *StdHeader - ); -*/ -#endif diff --git a/src/vendorcode/amd/agesa/f12/Proc/GNB/Gfx/GfxGmcInit.c b/src/vendorcode/amd/agesa/f12/Proc/GNB/Gfx/GfxGmcInit.c deleted file mode 100644 index 69a60b10c1..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/GNB/Gfx/GfxGmcInit.c +++ /dev/null @@ -1,797 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * GMC init services. - * - * - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: GNB - * @e \$Revision: 50763 $ @e \$Date: 2011-04-14 06:25:56 +0800 (Thu, 14 Apr 2011) $ - * - */ -/* -***************************************************************************** -* -* Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* *************************************************************************** -* -*/ -/*---------------------------------------------------------------------------------------- - * M O D U L E S U S E D - *---------------------------------------------------------------------------------------- - */ -#include "AGESA.h" -#include "amdlib.h" -#include "Ids.h" -//#include "heapManager.h" -#include "Gnb.h" -#include "GnbGfx.h" -#include "GnbPcie.h" -#include "GnbGfxFamServices.h" -#include "GnbCommonLib.h" -#include "GfxLib.h" -#include "GfxFamilyServices.h" -#include "GfxRegisterAcc.h" -#include "OptionGnb.h" -#include "GnbRegistersLN.h" -#include "GfxGmcInit.h" -#include "Filecode.h" -#define FILECODE PROC_GNB_GFX_GFXGMCINIT_FILECODE -/*---------------------------------------------------------------------------------------- - * D E F I N I T I O N S A N D M A C R O S - *---------------------------------------------------------------------------------------- - */ - -/// DCT channel information -typedef struct { - D18F2x094_STRUCT D18F2x094; ///< Register 0x94 - D18F2x084_STRUCT D18F2x084; ///< Register 0x84 - D18F2x08C_STRUCT D18F2x08C; ///< Register 0x8C - D18F2x0F4_x40_STRUCT D18F2x0F4_x40; ///< Register 0x40 - D18F2x0F4_x41_STRUCT D18F2x0F4_x41; ///< Register 0x41 -} DCT_CHANNEL_INFO; - -/*---------------------------------------------------------------------------------------- - * T Y P E D E F S A N D S T R U C T U R E S - *---------------------------------------------------------------------------------------- - */ - - - -/*---------------------------------------------------------------------------------------- - * P R O T O T Y P E S O F L O C A L F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ -VOID -GfxGmcSetMemoryAddressTranslation ( - IN GFX_PLATFORM_CONFIG *Gfx - ); - -VOID -GfxGmcDisableClockGating ( - IN GFX_PLATFORM_CONFIG *Gfx - ); - -VOID -GfxGmcInitializeRegisterEngine ( - IN GFX_PLATFORM_CONFIG *Gfx - ); - -VOID -GfxGmcDctMemoryChannelInfo ( - IN UINT8 Channel, - OUT DCT_CHANNEL_INFO *DctChannelInfo, - IN GFX_PLATFORM_CONFIG *Gfx - ); - -VOID -GfxGmcInitializeSequencerModel ( - IN GFX_PLATFORM_CONFIG *Gfx - ); - -VOID -GfxGmcInitializeFbLocation ( - IN GFX_PLATFORM_CONFIG *Gfx - ); - -VOID -GfxGmcSecureGarlicAccess ( - IN GFX_PLATFORM_CONFIG *Gfx - ); - -VOID -GfxGmcPerformanceTuning ( - IN GFX_PLATFORM_CONFIG *Gfx - ); - -VOID -GfxGmcMiscInit ( - IN GFX_PLATFORM_CONFIG *Gfx - ); - -VOID -GfxGmcLockCriticalRegisters ( - IN GFX_PLATFORM_CONFIG *Gfx - ); - -VOID -GfxGmcRemoveBlackout ( - IN GFX_PLATFORM_CONFIG *Gfx - ); - -VOID -GfxGmcEnableClockGating ( - IN GFX_PLATFORM_CONFIG *Gfx - ); - -VOID -GfxGmcUmaSteering ( - IN GFX_PLATFORM_CONFIG *Gfx - ); - -VOID -GfxGmcInitializeC6Aperture ( - IN GFX_PLATFORM_CONFIG *Gfx - ); - -VOID -GfxGmcInitializePowerGating ( - IN GFX_PLATFORM_CONFIG *Gfx - ); - - -/*---------------------------------------------------------------------------------------- - * E X P O R T E D F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ - -//Family 12 or Family 14 specific tables - -extern TABLE_INDIRECT_PTR GmcDisableClockGatingPtr; -extern TABLE_INDIRECT_PTR GmcEnableClockGatingPtr; -extern TABLE_INDIRECT_PTR GmcPerformanceTuningTablePtr; -extern TABLE_INDIRECT_PTR GmcMiscInitTablePtr; -extern TABLE_INDIRECT_PTR GmcRemoveBlackoutTablePtr; -extern TABLE_INDIRECT_PTR GmcRegisterEngineInitTablePtr; -extern TABLE_INDIRECT_PTR CnbToGncRegisterCopyTablePtr; - -extern UINT8 NumberOfChannels; -/*----------------------------------------------------------------------------------------*/ -/** - * Init GMC memory address translation - * - * - * - * @param[in] Gfx Pointer to global GFX configuration - */ -VOID -GfxGmcSetMemoryAddressTranslation ( - IN GFX_PLATFORM_CONFIG *Gfx - ) -{ - UINTN Index; - REGISTER_COPY_ENTRY *CnbToGncRegisterCopyTable; - CnbToGncRegisterCopyTable = CnbToGncRegisterCopyTablePtr.TablePtr; - for (Index = 0; Index < CnbToGncRegisterCopyTablePtr.TableLength; Index++) { - UINT32 Value; - GnbLibPciRead ( - CnbToGncRegisterCopyTable[Index].CpuReg, - AccessWidth32, - &Value, - GnbLibGetHeader (Gfx) - ); - Value = (Value >> CnbToGncRegisterCopyTable[Index].CpuOffset) & ((1 << CnbToGncRegisterCopyTable[Index].CpuWidth) - 1); - GmmRegisterWriteField ( - CnbToGncRegisterCopyTable[Index].GmmReg, - CnbToGncRegisterCopyTable[Index].GmmOffset, - CnbToGncRegisterCopyTable[Index].GmmWidth, - Value, - TRUE, - Gfx - ); - } -} - -/*----------------------------------------------------------------------------------------*/ -/** - * Disable CLock Gating - * - * - * - * @param[in] Gfx Graphics configuration - */ - -VOID -GfxGmcDisableClockGating ( - IN GFX_PLATFORM_CONFIG *Gfx - ) -{ - GmmRegisterTableWrite ( - GmcDisableClockGatingPtr.TablePtr, - GmcDisableClockGatingPtr.TableLength, - TRUE, - Gfx - ); -} - -/*----------------------------------------------------------------------------------------*/ -/** - * Initialize Register Engine - * - * - * - * @param[in] Gfx Pointer to global GFX configuration - */ - -VOID -GfxGmcInitializeRegisterEngine ( - IN GFX_PLATFORM_CONFIG *Gfx - ) -{ - - GmmRegisterTableWrite ( - GmcRegisterEngineInitTablePtr.TablePtr, - GmcRegisterEngineInitTablePtr.TableLength, - TRUE, - Gfx - ); -} - -/*----------------------------------------------------------------------------------------*/ -/** - * Get DCT channel info - * - * - * @param[in] Channel DCT channel number - * @param[out] DctChannelInfo Various DCT channel info - * @param[in] Gfx Pointer to global GFX configuration - */ - -VOID -GfxGmcDctMemoryChannelInfo ( - IN UINT8 Channel, - OUT DCT_CHANNEL_INFO *DctChannelInfo, - IN GFX_PLATFORM_CONFIG *Gfx - ) -{ - GnbLibCpuPciIndirectRead ( - MAKE_SBDFO (0, 0, 0x18, 2, (Channel == 0) ? D18F2x0F0_ADDRESS : D18F2x1F0_ADDRESS), - D18F2x0F4_x40_ADDRESS, - &DctChannelInfo->D18F2x0F4_x40.Value, - GnbLibGetHeader (Gfx) - ); - - GnbLibCpuPciIndirectRead ( - MAKE_SBDFO (0, 0, 0x18, 2, (Channel == 0) ? D18F2x0F0_ADDRESS : D18F2x1F0_ADDRESS), - D18F2x0F4_x41_ADDRESS, - &DctChannelInfo->D18F2x0F4_x41.Value, - GnbLibGetHeader (Gfx) - ); - - GnbLibPciRead ( - MAKE_SBDFO (0, 0, 0x18, 2, (Channel == 0) ? D18F2x084_ADDRESS : D18F2x184_ADDRESS), - AccessWidth32, - &DctChannelInfo->D18F2x084.Value, - GnbLibGetHeader (Gfx) - ); - - GnbLibPciRead ( - MAKE_SBDFO (0, 0, 0x18, 2, (Channel == 0) ? D18F2x094_ADDRESS : D18F2x194_ADDRESS), - AccessWidth32, - &DctChannelInfo->D18F2x094.Value, - GnbLibGetHeader (Gfx) - ); - - GnbLibPciRead ( - MAKE_SBDFO (0, 0, 0x18, 2, (Channel == 0) ? D18F2x08C_ADDRESS : D18F2x18C_ADDRESS), - AccessWidth32, - &DctChannelInfo->D18F2x08C.Value, - GnbLibGetHeader (Gfx) - ); -} - -/*----------------------------------------------------------------------------------------*/ -/** - * Initialize Sequencer Model - * - * - * - * @param[in] Gfx Pointer to global GFX configuration - */ - -VOID -GfxGmcInitializeSequencerModel ( - IN GFX_PLATFORM_CONFIG *Gfx - ) -{ - GMMx277C_STRUCT GMMx277C; - GMMx2780_STRUCT GMMx2780; - DCT_CHANNEL_INFO DctChannel[2]; - UINT8 ActiveChannel; - - GfxGmcDctMemoryChannelInfo (0, &DctChannel[0], Gfx); - if (NumberOfChannels == 2) { - GfxGmcDctMemoryChannelInfo (1, &DctChannel[1], Gfx); - } - - // Find the Active Channels. For a single channel system, Active channel is 0; - if (NumberOfChannels == 1) { - ActiveChannel = 0; - } else { - //For two channel system, Active channel could be either 0 or 1 or both (2) - if (DctChannel[0].D18F2x094.Field.DisDramInterface == 0 && - DctChannel[1].D18F2x094.Field.DisDramInterface == 0) { - ActiveChannel = 2; - } else { - ActiveChannel = (DctChannel[0].D18F2x094.Field.DisDramInterface == 0) ? 0 : 1; - } - } - - if (ActiveChannel == 2) { - // Both controllers enabled - GMMx277C.Field.ActRd = MIN_UNSAFE (DctChannel[0].D18F2x0F4_x40.Field.Trcd, DctChannel[1].D18F2x0F4_x40.Field.Trcd) + 5; - GMMx277C.Field.RasMActRd = MIN_UNSAFE ((DctChannel[0].D18F2x0F4_x40.Field.Trc + 11 - (DctChannel[0].D18F2x0F4_x40.Field.Trcd + 5)), - (DctChannel[1].D18F2x0F4_x40.Field.Trc + 11 - (DctChannel[1].D18F2x0F4_x40.Field.Trcd + 5))); - GMMx2780.Field.Ras2Ras = MIN_UNSAFE (DctChannel[0].D18F2x0F4_x40.Field.Trc, DctChannel[1].D18F2x0F4_x40.Field.Trc) + 11 - 1; - GMMx2780.Field.Rp = MIN_UNSAFE (DctChannel[0].D18F2x0F4_x40.Field.Trp, DctChannel[1].D18F2x0F4_x40.Field.Trp) + 5 - 1; - GMMx2780.Field.WrPlusRp = MIN_UNSAFE ( - ((DctChannel[0].D18F2x084.Field.Twr == 0) ? 16 : - ((DctChannel[0].D18F2x084.Field.Twr < 4) ? (DctChannel[0].D18F2x084.Field.Twr + 4) : - (DctChannel[0].D18F2x084.Field.Twr * 2)) + DctChannel[0].D18F2x0F4_x40.Field.Trp + 5), - ((DctChannel[1].D18F2x084.Field.Twr == 0) ? 16 : - ((DctChannel[1].D18F2x084.Field.Twr < 4) ? (DctChannel[1].D18F2x084.Field.Twr + 4) : - (DctChannel[1].D18F2x084.Field.Twr * 2)) + DctChannel[1].D18F2x0F4_x40.Field.Trp + 5) - ) - 1; - GMMx2780.Field.BusTurn = (MIN_UNSAFE ( - DctChannel[0].D18F2x084.Field.Tcwl + 5 + - DctChannel[0].D18F2x0F4_x41.Field.Twtr + 4 + - DctChannel[0].D18F2x08C.Field.TrwtTO + 2 , - DctChannel[1].D18F2x084.Field.Tcwl + 5 + - DctChannel[1].D18F2x0F4_x41.Field.Twtr + 4 + - DctChannel[1].D18F2x08C.Field.TrwtTO + 2 - ) + 4) / 2; - } else { - // Only one channel is active. - GMMx277C.Field.ActRd = DctChannel[ActiveChannel].D18F2x0F4_x40.Field.Trcd + 5; - GMMx277C.Field.RasMActRd = DctChannel[ActiveChannel].D18F2x0F4_x40.Field.Trc + 11 - - (DctChannel[ActiveChannel].D18F2x0F4_x40.Field.Trcd + 5); - GMMx2780.Field.Ras2Ras = DctChannel[ActiveChannel].D18F2x0F4_x40.Field.Trc + 11 - 1; - GMMx2780.Field.Rp = DctChannel[ActiveChannel].D18F2x0F4_x40.Field.Trp + 5 - 1; - GMMx2780.Field.WrPlusRp = ((DctChannel[ActiveChannel].D18F2x084.Field.Twr == 0) ? 16 : - ((DctChannel[ActiveChannel].D18F2x084.Field.Twr < 4) ? (DctChannel[ActiveChannel].D18F2x084.Field.Twr + 4) : - (DctChannel[ActiveChannel].D18F2x084.Field.Twr * 2)) + - DctChannel[ActiveChannel].D18F2x0F4_x40.Field.Trp + 5) - 1; - GMMx2780.Field.BusTurn = ((DctChannel[ActiveChannel].D18F2x084.Field.Tcwl + 5 + - DctChannel[ActiveChannel].D18F2x0F4_x41.Field.Twtr + 4 + - DctChannel[ActiveChannel].D18F2x08C.Field.TrwtTO + 2) + 4) / 2; - } - GMMx277C.Field.ActWr = GMMx277C.Field.ActRd; - GMMx277C.Field.RasMActWr = GMMx277C.Field.RasMActRd; - - GmmRegisterWrite ( - GMMx277C_ADDRESS, - GMMx277C.Value, - TRUE, - Gfx - ); - GmmRegisterWrite ( - GMMx28D8_ADDRESS, - GMMx277C.Value, - TRUE, - Gfx - ); - GmmRegisterWrite ( - GMMx2780_ADDRESS, - GMMx2780.Value, - TRUE, - Gfx - ); - GmmRegisterWrite ( - GMMx28DC_ADDRESS, - GMMx2780.Value, - TRUE, - Gfx - ); -} - -/*----------------------------------------------------------------------------------------*/ -/** - * Initialize Frame Buffer Location - * - * - * - * @param[in] Gfx Pointer to global GFX configuration - */ - -VOID -GfxGmcInitializeFbLocation ( - IN GFX_PLATFORM_CONFIG *Gfx - ) -{ - //Logical FB location - GMMx2024_STRUCT GMMx2024; - GMMx2898_STRUCT GMMx2898; - GMMx2C04_STRUCT GMMx2C04; - GMMx5428_STRUCT GMMx5428; - UINT64 FBBase; - UINT64 FBTop; - FBBase = 0x0F00000000ull; - FBTop = FBBase + Gfx->UmaInfo.UmaSize - 1; - GMMx2024.Value = 0; - GMMx2898.Value = 0; - GMMx2C04.Value = 0; - GMMx5428.Value = 0; - GMMx2024.Field.Base = (UINT16) (FBBase >> 24); - GMMx2024.Field.Top = (UINT16) (FBTop >> 24); - GMMx2898.Field.Offset = (UINT32) (Gfx->UmaInfo.UmaBase >> 20); - GMMx2898.Field.Top = (UINT32) ((FBTop >> 20) & 0xf); - GMMx2898.Field.Base = (UINT32) ((FBBase >> 20) & 0xf); - GMMx2C04.Field.NonsurfBase = (UINT32) (FBBase >> 8); - GMMx5428.Field.ConfigMemsize = Gfx->UmaInfo.UmaSize; - - GmmRegisterWrite ( - GMMx2024_ADDRESS, - GMMx2024.Value, - TRUE, - Gfx - ); - GmmRegisterWrite ( - GMMx2898_ADDRESS, - GMMx2898.Value, - TRUE, - Gfx - ); - GmmRegisterWrite ( - GMMx2C04_ADDRESS, - GMMx2C04.Value, - TRUE, - Gfx - ); - GmmRegisterWrite ( - GMMx5428_ADDRESS, - GMMx5428.Value, - TRUE, - Gfx - ); - GmmRegisterWriteField ( - GMMx5490_ADDRESS, - GMMx5490_FbReadEn_OFFSET, - GMMx5490_FbReadEn_WIDTH, - 1, - TRUE, - Gfx - ); - GmmRegisterWriteField ( - GMMx5490_ADDRESS, - GMMx5490_FbWriteEn_OFFSET, - GMMx5490_FbWriteEn_WIDTH, - 1, - TRUE, - Gfx - ); -} - -/*----------------------------------------------------------------------------------------*/ -/** - * Secure Garlic Access - * - * - * - * @param[in] Gfx Pointer to global GFX configuration - */ - -VOID -GfxGmcSecureGarlicAccess ( - IN GFX_PLATFORM_CONFIG *Gfx - ) -{ - GMMx286C_STRUCT GMMx286C; - GMMx287C_STRUCT GMMx287C; - GMMx2894_STRUCT GMMx2894; - UINT32 Value; - GMMx286C.Value = (UINT32) (Gfx->UmaInfo.UmaBase >> 20); - GmmRegisterWrite (GMMx286C_ADDRESS, GMMx286C.Value, TRUE, Gfx); - GMMx287C.Value = (UINT32) (((Gfx->UmaInfo.UmaBase + Gfx->UmaInfo.UmaSize) >> 20) - 1); - GmmRegisterWrite (GMMx287C_ADDRESS, GMMx287C.Value, TRUE, Gfx); - // Areag FB - 20K reserved by VBIOS for SBIOS to use - GMMx2894.Value = (UINT32) ((Gfx->UmaInfo.UmaBase + Gfx->UmaInfo.UmaSize - 20 * 1024) >> 12); - GmmRegisterWrite (GMMx2894_ADDRESS, GMMx2894.Value, TRUE, Gfx); - Value = 0xfffff; - GmmRegisterWrite (GMMx2870_ADDRESS, Value, TRUE, Gfx); - GmmRegisterWrite (GMMx2874_ADDRESS, Value, TRUE, Gfx); - GmmRegisterWrite (GMMx2878_ADDRESS, Value, TRUE, Gfx); -} - -/*----------------------------------------------------------------------------------------*/ -/** - * Performance setting - * - * - * - * @param[in] Gfx Pointer to global GFX configuration - */ - -VOID -GfxGmcPerformanceTuning ( - IN GFX_PLATFORM_CONFIG *Gfx - ) -{ - GmmRegisterTableWrite ( - GmcPerformanceTuningTablePtr.TablePtr, - GmcPerformanceTuningTablePtr.TableLength, - TRUE, - Gfx - ); -} - -/*----------------------------------------------------------------------------------------*/ -/** - * Misc. Initialization - * - * - * - * @param[in] Gfx Pointer to global GFX configuration - */ - -VOID -GfxGmcMiscInit ( - IN GFX_PLATFORM_CONFIG *Gfx - ) -{ - GMMx2114_STRUCT GMMx2114; - - GMMx2114.Value = GmmRegisterRead (GMMx2114_ADDRESS, Gfx); - GMMx2114.Field.Stor1Pri = 0xC; - GmmRegisterWrite (GMMx2114_ADDRESS, GMMx2114.Value, TRUE, Gfx); - - GmmRegisterTableWrite ( - GmcMiscInitTablePtr.TablePtr, - GmcMiscInitTablePtr.TableLength, - TRUE, - Gfx - ); -} - -/*----------------------------------------------------------------------------------------*/ -/** - * Lock critical registers - * - * - * - * @param[in] Gfx Graphics configuration - */ - -VOID -GfxGmcLockCriticalRegisters ( - IN GFX_PLATFORM_CONFIG *Gfx - ) -{ - GmmRegisterWriteField ( - GMMx2B98_ADDRESS, - GMMx2B98_CriticalRegsLock_OFFSET, - GMMx2B98_CriticalRegsLock_WIDTH, - 1, - TRUE, - Gfx - ); -} - -/*----------------------------------------------------------------------------------------*/ -/** - * Remove blackout - * - * - * - * @param[in] Gfx Pointer to global GFX configuration - */ - -VOID -GfxGmcRemoveBlackout ( - IN GFX_PLATFORM_CONFIG *Gfx - ) -{ - GmmRegisterTableWrite ( - GmcRemoveBlackoutTablePtr.TablePtr, - GmcRemoveBlackoutTablePtr.TableLength, - TRUE, - Gfx - ); -} - -/*----------------------------------------------------------------------------------------*/ -/** - * Enable clock Gating - * - * - * - * @param[in] Gfx Graphics configuration - */ - -VOID -GfxGmcEnableClockGating ( - IN GFX_PLATFORM_CONFIG *Gfx - ) -{ - GmmRegisterTableWrite ( - GmcEnableClockGatingPtr.TablePtr, - GmcEnableClockGatingPtr.TableLength, - TRUE, - Gfx - ); -} - -/*----------------------------------------------------------------------------------------*/ -/** - * UMA steering - * - * - * - * @param[in] Gfx Graphics configuration - */ - -VOID -GfxGmcUmaSteering ( - IN GFX_PLATFORM_CONFIG *Gfx - ) -{ -} - -/*----------------------------------------------------------------------------------------*/ -/** - * Initialize C6 aperture - * - * - * - * @param[in] Gfx Graphics configuration - */ - -VOID -GfxGmcInitializeC6Aperture ( - IN GFX_PLATFORM_CONFIG *Gfx - ) -{ - D18F4x12C_STRUCT D18F4x12C; - GMMx288C_STRUCT GMMx288C; - GMMx2890_STRUCT GMMx2890; - - GnbLibPciRead ( - MAKE_SBDFO (0, 0, 0x18, 4, D18F4x12C_ADDRESS), - AccessWidth32, - &D18F4x12C.Value, - GnbLibGetHeader (Gfx) - ); - GMMx288C.Value = D18F4x12C.Field.C6Base_39_24_ << 4; - // Modify the values only if C6 Base is set - if (GMMx288C.Value != 0) { - GMMx2890.Value = (GMMx288C.Value + 16) - 1; - GmmRegisterWrite ( - GMMx288C_ADDRESS, - GMMx288C.Value, - TRUE, - Gfx - ); - GmmRegisterWrite ( - GMMx2890_ADDRESS, - GMMx2890.Value, - TRUE, - Gfx - ); - } -} -/*----------------------------------------------------------------------------------------*/ -/** - * Initialize Power Gating - * - * - * - * @param[in] Gfx Graphics configuration - */ - -VOID -GfxGmcInitializePowerGating ( - IN GFX_PLATFORM_CONFIG *Gfx - ) -{ - switch (Gfx->GmcPowerGating) { - case GmcPowerGatingDisabled: - break; - case GmcPowerGatingStutterOnly: - GmmRegisterWriteField ( - GMMx2B98_ADDRESS, - GMMx2B98_StctrlStutterEn_OFFSET, - GMMx2B98_StctrlStutterEn_WIDTH, - 1, - TRUE, - Gfx - ); - break; - case GmcPowerGatingWidthStutter: - GmmRegisterWriteField ( - GMMx2B94_ADDRESS, - GMMx2B94_RengExecuteOnPwrUp_OFFSET, - GMMx2B94_RengExecuteOnPwrUp_WIDTH, - 1, - TRUE, - Gfx - ); - GmmRegisterWriteField ( - GMMx2B98_ADDRESS, - GMMx2B98_RengExecuteOnRegUpdate_OFFSET, - GMMx2B98_RengExecuteOnRegUpdate_WIDTH, - 1, - TRUE, - Gfx - ); - break; - default: - ASSERT (FALSE); - } -} - - -/*----------------------------------------------------------------------------------------*/ -/** - * Init GMC - * - * - * - * @param[in] Gfx Pointer to global GFX configuration - * @retval AGESA_STATUS Always succeeds - */ - -AGESA_STATUS -GfxGmcInit ( - IN GFX_PLATFORM_CONFIG *Gfx - ) -{ - AGESA_STATUS Status; - Status = AGESA_SUCCESS; - IDS_HDT_CONSOLE (GNB_TRACE, "GfxGmcInit Enter\n"); - GfxGmcDisableClockGating (Gfx); - GfxGmcSetMemoryAddressTranslation (Gfx); - GfxGmcInitializeSequencerModel (Gfx); - GfxGmcInitializeRegisterEngine (Gfx); - GfxGmcInitializeFbLocation (Gfx); - GfxGmcUmaSteering (Gfx); - GfxGmcSecureGarlicAccess (Gfx); - GfxGmcInitializeC6Aperture (Gfx); - GfxFmGmcAddressSwizzel (Gfx); - IDS_OPTION_CALLOUT (IDS_CALLOUT_GNB_GMM_REGISTER_OVERRIDE, Gfx, GnbLibGetHeader (Gfx)); - GfxGmcLockCriticalRegisters (Gfx); - GfxGmcPerformanceTuning (Gfx); - GfxGmcMiscInit (Gfx); - GfxGmcRemoveBlackout (Gfx); - if (Gfx->GmcClockGating == OptionEnabled) { - GfxGmcEnableClockGating (Gfx); - } - GfxGmcInitializePowerGating (Gfx); - GfxFmGmcAllowPstateHigh (Gfx); - IDS_HDT_CONSOLE (GNB_TRACE, "GfxGmcInit Exit\n"); - return Status; -} diff --git a/src/vendorcode/amd/agesa/f12/Proc/GNB/Gfx/GfxGmcInit.h b/src/vendorcode/amd/agesa/f12/Proc/GNB/Gfx/GfxGmcInit.h deleted file mode 100644 index 2d2942b908..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/GNB/Gfx/GfxGmcInit.h +++ /dev/null @@ -1,55 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * GMC init services. - * - * - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: GNB - * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $ - * - */ -/* -***************************************************************************** -* -* Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* *************************************************************************** -* -*/ - -#ifndef _GFXGMCINIT_H_ -#define _GFXGMCINIT_H_ - - -AGESA_STATUS -GfxGmcInit ( - IN GFX_PLATFORM_CONFIG *Gfx - ); - -#endif diff --git a/src/vendorcode/amd/agesa/f12/Proc/GNB/Gfx/GfxInitAtEnvPost.c b/src/vendorcode/amd/agesa/f12/Proc/GNB/Gfx/GfxInitAtEnvPost.c deleted file mode 100644 index c9718c72e1..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/GNB/Gfx/GfxInitAtEnvPost.c +++ /dev/null @@ -1,111 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * Interface to initialize Graphics Controller at env POST - * - * - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: GNB - * @e \$Revision: 48452 $ @e \$Date: 2011-03-09 12:50:44 +0800 (Wed, 09 Mar 2011) $ - * - */ -/* -***************************************************************************** -* -* Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* *************************************************************************** -* -*/ - -/*---------------------------------------------------------------------------------------- - * M O D U L E S U S E D - *---------------------------------------------------------------------------------------- - */ -#include "AGESA.h" -#include "amdlib.h" -#include "Ids.h" -#include "Gnb.h" -#include "GnbGfx.h" -#include "GnbGfxConfig.h" -#include "GfxStrapsInit.h" -#include "GfxInitAtEnvPost.h" -#include "Filecode.h" -#define FILECODE PROC_GNB_GFX_GFXINITATENVPOST_FILECODE -/*---------------------------------------------------------------------------------------- - * D E F I N I T I O N S A N D M A C R O S - *---------------------------------------------------------------------------------------- - */ - - -/*---------------------------------------------------------------------------------------- - * T Y P E D E F S A N D S T R U C T U R E S - *---------------------------------------------------------------------------------------- - */ - - -/*---------------------------------------------------------------------------------------- - * P R O T O T Y P E S O F L O C A L F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ - - - -/*----------------------------------------------------------------------------------------*/ -/** - * Init GFX at Env Post. - * - * - * - * @param[in] StdHeader Standard configuration header - * @retval AGESA_STATUS - */ - - -AGESA_STATUS -GfxInitAtEnvPost ( - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - AGESA_STATUS Status; - GFX_PLATFORM_CONFIG *Gfx; - IDS_HDT_CONSOLE (GNB_TRACE, "GfxInitAtEnvPost Enter\n"); - Status = GfxLocateConfigData (StdHeader, &Gfx); - if (Status == AGESA_SUCCESS) { - if (Gfx->UmaInfo.UmaMode != UMA_NONE) { - Status = GfxStrapsInit (Gfx); - ASSERT (Status == AGESA_SUCCESS); - } else { - GfxDisableController (StdHeader); - } - } else { - GfxDisableController (StdHeader); - } - IDS_HDT_CONSOLE (GNB_TRACE, "GfxInitAtEnvPost Exit [0x%x]\n", Status); - return Status; -} diff --git a/src/vendorcode/amd/agesa/f12/Proc/GNB/Gfx/GfxInitAtEnvPost.h b/src/vendorcode/amd/agesa/f12/Proc/GNB/Gfx/GfxInitAtEnvPost.h deleted file mode 100644 index 99982771cc..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/GNB/Gfx/GfxInitAtEnvPost.h +++ /dev/null @@ -1,54 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * Interface to initialize Graphics Controller at env POST - * - * - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: GNB - * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $ - * - */ -/* -***************************************************************************** -* -* Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* *************************************************************************** -* -*/ - -#ifndef _GFXINITATENVPOST_H_ -#define _GFXINITATENVPOST_H_ - -AGESA_STATUS -GfxInitAtEnvPost ( - IN AMD_CONFIG_PARAMS *StdHeader - ); - -#endif diff --git a/src/vendorcode/amd/agesa/f12/Proc/GNB/Gfx/GfxInitAtMidPost.c b/src/vendorcode/amd/agesa/f12/Proc/GNB/Gfx/GfxInitAtMidPost.c deleted file mode 100644 index f7ea25b58b..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/GNB/Gfx/GfxInitAtMidPost.c +++ /dev/null @@ -1,132 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * Interface to initialize Graphics Controller at mid POST - * - * - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: GNB - * @e \$Revision: 51087 $ @e \$Date: 2011-04-19 07:38:57 +0800 (Tue, 19 Apr 2011) $ - * - */ -/* -***************************************************************************** -* -* Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* *************************************************************************** -* -*/ - -/*---------------------------------------------------------------------------------------- - * M O D U L E S U S E D - *---------------------------------------------------------------------------------------- - */ -#include "AGESA.h" -#include "amdlib.h" -#include "Ids.h" -#include "Gnb.h" -#include "GnbGfx.h" -#include "GnbGfxConfig.h" -#include "GfxConfigData.h" -#include "GfxStrapsInit.h" -#include "GfxGmcInit.h" -#include "GfxInitAtMidPost.h" -#include "GnbGfxInitLibV1.h" -#include "GnbGfxFamServices.h" -#include "Filecode.h" -#define FILECODE PROC_GNB_GFX_GFXINITATMIDPOST_FILECODE -/*---------------------------------------------------------------------------------------- - * D E F I N I T I O N S A N D M A C R O S - *---------------------------------------------------------------------------------------- - */ - - -/*---------------------------------------------------------------------------------------- - * T Y P E D E F S A N D S T R U C T U R E S - *---------------------------------------------------------------------------------------- - */ - - -/*---------------------------------------------------------------------------------------- - * P R O T O T Y P E S O F L O C A L F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ - - - -/*----------------------------------------------------------------------------------------*/ -/** - * Init GFX at Mid Post. - * - * - * - * @param[in] StdHeader Standard configuration header - * @retval AGESA_STATUS - */ - -AGESA_STATUS -GfxInitAtMidPost ( - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - AGESA_STATUS Status; - AGESA_STATUS AgesaStatus; - GFX_PLATFORM_CONFIG *Gfx; - IDS_HDT_CONSOLE (GNB_TRACE, "GfxInitAtMidPost Enter\n"); - AgesaStatus = AGESA_SUCCESS; - Status = GfxLocateConfigData (StdHeader, &Gfx); - AGESA_STATUS_UPDATE (Status, AgesaStatus); - if (Status == AGESA_FATAL) { - GfxDisableController (StdHeader); - } else { - if (Gfx->UmaInfo.UmaMode != UMA_NONE) { - Status = GfxEnableGmmAccess (Gfx); - ASSERT (Status == AGESA_SUCCESS); - AGESA_STATUS_UPDATE (Status, AgesaStatus); - if (Status != AGESA_SUCCESS) { - // Can not initialize GMM registers going to disable GFX controller - IDS_HDT_CONSOLE (GNB_TRACE, " Fail to establish GMM access\n"); - Gfx->UmaInfo.UmaMode = UMA_NONE; - GfxDisableController (StdHeader); - } else { - Status = GfxGmcInit (Gfx); - AGESA_STATUS_UPDATE (Status, AgesaStatus); - - Status = GfxSetBootUpVoltage (Gfx); - AGESA_STATUS_UPDATE (Status, AgesaStatus); - - Status = GfxInitSsid (Gfx); - AGESA_STATUS_UPDATE (Status, AgesaStatus); - } - } - GfxFmSetIdleVoltageMode (Gfx); - } - IDS_HDT_CONSOLE (GNB_TRACE, "GfxInitAtMidPost Exit [0x%x]\n", AgesaStatus); - return AgesaStatus; -} diff --git a/src/vendorcode/amd/agesa/f12/Proc/GNB/Gfx/GfxInitAtMidPost.h b/src/vendorcode/amd/agesa/f12/Proc/GNB/Gfx/GfxInitAtMidPost.h deleted file mode 100644 index 794241f5de..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/GNB/Gfx/GfxInitAtMidPost.h +++ /dev/null @@ -1,55 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * Interface to initialize Graphics Controller at mid POST - * - * - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: GNB - * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $ - * - */ -/* -***************************************************************************** -* -* Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* *************************************************************************** -* -*/ - -#ifndef _GFXINITATMIDPOST_H_ -#define _GFXINITATMIDPOST_H_ - -AGESA_STATUS -GfxInitAtMidPost ( - IN AMD_CONFIG_PARAMS *StdHeader - ); - -#endif - diff --git a/src/vendorcode/amd/agesa/f12/Proc/GNB/Gfx/GfxInitAtPost.c b/src/vendorcode/amd/agesa/f12/Proc/GNB/Gfx/GfxInitAtPost.c deleted file mode 100644 index 9e1fcff3c1..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/GNB/Gfx/GfxInitAtPost.c +++ /dev/null @@ -1,124 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * Interface to initialize Graphics Controller at POST - * - * - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: GNB - * @e \$Revision: 48452 $ @e \$Date: 2011-03-09 12:50:44 +0800 (Wed, 09 Mar 2011) $ - * - */ -/* -***************************************************************************** -* -* Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* *************************************************************************** -* -*/ - -/*---------------------------------------------------------------------------------------- - * M O D U L E S U S E D - *---------------------------------------------------------------------------------------- - */ -#include "AGESA.h" -#include "amdlib.h" -#include "Ids.h" -#include "Gnb.h" -#include "GnbPcie.h" -#include "GnbGfx.h" -#include "GnbGfxInitLibV1.h" -#include "GnbGfxConfig.h" -#include "GfxStrapsInit.h" -#include "GfxLib.h" -#include "GfxConfigData.h" -#include "GfxInitAtPost.h" -#include "Filecode.h" -#define FILECODE PROC_GNB_GFX_GFXINITATPOST_FILECODE -/*---------------------------------------------------------------------------------------- - * D E F I N I T I O N S A N D M A C R O S - *---------------------------------------------------------------------------------------- - */ - - -/*---------------------------------------------------------------------------------------- - * T Y P E D E F S A N D S T R U C T U R E S - *---------------------------------------------------------------------------------------- - */ - - -/*---------------------------------------------------------------------------------------- - * P R O T O T Y P E S O F L O C A L F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ - -/*----------------------------------------------------------------------------------------*/ -/** - * Init GFX at Post. - * - * - * - * @param[in] StdHeader Standard configuration header - * @retval AGESA_STATUS - */ - - -AGESA_STATUS -GfxInitAtPost ( - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - AMD_POST_PARAMS *PostParamsPtr; - AGESA_STATUS Status; - GFX_PLATFORM_CONFIG *Gfx; - PostParamsPtr = (AMD_POST_PARAMS *)StdHeader; - IDS_HDT_CONSOLE (GNB_TRACE, "GfxInitAtPost Enter\n"); - Status = GfxLocateConfigData (StdHeader, &Gfx); - ASSERT (Status == AGESA_SUCCESS); - if (Status == AGESA_SUCCESS) { - if (GfxLibIsControllerPresent (StdHeader)) { - if (PostParamsPtr->MemConfig.UmaMode != UMA_NONE) { - GfxGetDiscreteCardInfo (&Gfx->GfxDiscreteCardInfo, StdHeader); - if (Gfx->GfxDiscreteCardInfo.PciGfxCardBitmap != 0 || - (Gfx->GfxDiscreteCardInfo.AmdPcieGfxCardBitmap & Gfx->GfxDiscreteCardInfo.PcieGfxCardBitmap) != - Gfx->GfxDiscreteCardInfo.PcieGfxCardBitmap) { - PostParamsPtr->MemConfig.UmaMode = UMA_NONE; - IDS_HDT_CONSOLE (GFX_MISC, " GfxDisabled due to dGPU policy\n"); - } - } - } else { - PostParamsPtr->MemConfig.UmaMode = UMA_NONE; - Gfx->GfxFusedOff = TRUE; - } - } else { - PostParamsPtr->MemConfig.UmaMode = UMA_NONE; - } - IDS_HDT_CONSOLE (GNB_TRACE, "GfxInitAtPost Exit [0x%x]\n", Status); - return Status; -} diff --git a/src/vendorcode/amd/agesa/f12/Proc/GNB/Gfx/GfxInitAtPost.h b/src/vendorcode/amd/agesa/f12/Proc/GNB/Gfx/GfxInitAtPost.h deleted file mode 100644 index 3a45f31bd9..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/GNB/Gfx/GfxInitAtPost.h +++ /dev/null @@ -1,55 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * Interface to initialize Graphics Controller at POST - * - * - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: GNB - * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $ - * - */ -/* -***************************************************************************** -* -* Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* *************************************************************************** -* -*/ - -#ifndef _GFXINITATPOST_H_ -#define _GFXINITATPOST_H_ - -AGESA_STATUS -GfxInitAtPost ( - IN AMD_CONFIG_PARAMS *StdHeader - ); - -#endif - diff --git a/src/vendorcode/amd/agesa/f12/Proc/GNB/Gfx/GfxIntegratedInfoTableInit.c b/src/vendorcode/amd/agesa/f12/Proc/GNB/Gfx/GfxIntegratedInfoTableInit.c deleted file mode 100644 index 93c36e4382..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/GNB/Gfx/GfxIntegratedInfoTableInit.c +++ /dev/null @@ -1,701 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * Service procedure to initialize Integrated Info Table - * - * - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: GNB - * @e \$Revision: 48890 $ @e \$Date: 2011-03-14 14:32:00 +0800 (Mon, 14 Mar 2011) $ - * - */ -/* -***************************************************************************** -* -* Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* *************************************************************************** -* -*/ - - -/*---------------------------------------------------------------------------------------- - * M O D U L E S U S E D - *---------------------------------------------------------------------------------------- - */ -#include "AGESA.h" -#include "amdlib.h" -#include "Ids.h" -#include "heapManager.h" -#include "Gnb.h" -#include "GnbFuseTable.h" -#include "GnbPcie.h" -#include "GnbGfx.h" -#include "GnbSbLib.h" -#include "GnbCommonLib.h" -#include "GnbPcieConfig.h" -#include "GnbGfxInitLibV1.h" -#include "GnbGfxConfig.h" -#include "GnbNbInitLibV1.h" -#include "GfxLib.h" -#include "GfxConfigData.h" -#include "GfxRegisterAcc.h" -#include "GfxFamilyServices.h" -#include "GnbGfxFamServices.h" -#include "GfxIntegratedInfoTableInit.h" -#include "GnbRegistersLN.h" -#include "Filecode.h" -#define FILECODE PROC_GNB_GFX_GFXINTEGRATEDINFOTABLEINIT_FILECODE -/*---------------------------------------------------------------------------------------- - * D E F I N I T I O N S A N D M A C R O S - *---------------------------------------------------------------------------------------- - */ - - - -/*---------------------------------------------------------------------------------------- - * T Y P E D E F S A N D S T R U C T U R E S - *---------------------------------------------------------------------------------------- - */ - - - - -/*---------------------------------------------------------------------------------------- - * P R O T O T Y P E S O F L O C A L F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ -UINT32 -GfxLibGetCsrPhySrPllPdMode ( - IN UINT8 Channel, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -UINT32 -GfxLibGetDisDllShutdownSR ( - IN UINT8 Channel, - IN AMD_CONFIG_PARAMS *StdHeader - ); - - - -ULONG ulCSR_M3_ARB_CNTL_DEFAULT[] = { - 0x80040810, - 0x00040810, - 0x00040810, - 0x00040810, - 0x00040810, - 0x00040810, - 0x00204080, - 0x00204080, - 0x0000001E, - 0x00000000 -}; - - -ULONG ulCSR_M3_ARB_CNTL_UVD[] = { - 0x80040810, - 0x00040810, - 0x00040810, - 0x00040810, - 0x00040810, - 0x00040810, - 0x00204080, - 0x00204080, - 0x0000001E, - 0x00000000 -}; - - -ULONG ulCSR_M3_ARB_CNTL_FS3D[] = { - 0x80040810, - 0x00040810, - 0x00040810, - 0x00040810, - 0x00040810, - 0x00040810, - 0x00204080, - 0x00204080, - 0x0000001E, - 0x00000000 -}; - - -VOID -GfxIntegratedInfoInitDispclkTable ( - IN PP_FUSE_ARRAY *PpFuseArray, - IN ATOM_INTEGRATED_SYSTEM_INFO_V6 *IntegratedInfoTable, - IN GFX_PLATFORM_CONFIG *Gfx - ); - -VOID -GfxIntegratedInfoInitSclkTable ( - IN PP_FUSE_ARRAY *PpFuseArray, - IN ATOM_INTEGRATED_SYSTEM_INFO_V6 *IntegratedInfoTable, - IN GFX_PLATFORM_CONFIG *Gfx - ); - -VOID -GfxFillHtcData ( - IN OUT ATOM_INTEGRATED_SYSTEM_INFO_V6 *IntegratedInfoTable, - IN GFX_PLATFORM_CONFIG *Gfx - ); - -VOID -GfxFillNbPStateVid ( - IN OUT ATOM_INTEGRATED_SYSTEM_INFO_V6 *IntegratedInfoTable, - IN GFX_PLATFORM_CONFIG *Gfx - ); - -VOID -GfxFillM3ArbritrationControl ( - IN OUT ATOM_INTEGRATED_SYSTEM_INFO_V6 *IntegratedInfoTable, - IN GFX_PLATFORM_CONFIG *Gfx - ); - - -VOID -GfxFillSbMmioBaseAddress ( - IN OUT ATOM_INTEGRATED_SYSTEM_INFO_V6 *IntegratedInfoTable, - IN GFX_PLATFORM_CONFIG *Gfx - ); - -VOID -GfxFillNclkInfo ( - IN OUT ATOM_INTEGRATED_SYSTEM_INFO_V6 *IntegratedInfoTable, - IN GFX_PLATFORM_CONFIG *Gfx - ); - -AGESA_STATUS -GfxIntegratedInfoTableInit ( - IN GFX_PLATFORM_CONFIG *Gfx - ); - -/*----------------------------------------------------------------------------------------*/ -/** - * Get CSR phy self refresh power down mode. - * - * - * @param[in] Channel DCT controller index - * @param[in] StdHeader Standard configuration header - * @retval CsrPhySrPllPdMode - */ -UINT32 -GfxLibGetCsrPhySrPllPdMode ( - IN UINT8 Channel, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - D18F2x09C_x0D0FE00A_STRUCT D18F2x09C_x0D0FE00A; - - GnbLibCpuPciIndirectRead ( - MAKE_SBDFO ( 0, 0, 0x18, 2, (Channel == 0) ? D18F2x098_ADDRESS : D18F2x198_ADDRESS), - D18F2x09C_x0D0FE00A_ADDRESS, - &D18F2x09C_x0D0FE00A.Value, - StdHeader - ); - - return D18F2x09C_x0D0FE00A.Field.CsrPhySrPllPdMode; -} - -/*----------------------------------------------------------------------------------------*/ -/** - * Get disable DLL shutdown in self-refresh mode. - * - * - * @param[in] Channel DCT controller index - * @param[in] StdHeader Standard configuration header - * @retval DisDllShutdownSR - */ -UINT32 -GfxLibGetDisDllShutdownSR ( - IN UINT8 Channel, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - D18F2x090_STRUCT D18F2x090; - - GnbLibPciRead ( - MAKE_SBDFO ( 0, 0, 0x18, 2, (Channel == 0) ? D18F2x090_ADDRESS : D18F2x190_ADDRESS), - AccessWidth32, - &D18F2x090.Value, - StdHeader - ); - - return D18F2x090.Field.DisDllShutdownSR; -} - -/*----------------------------------------------------------------------------------------*/ -/** - * Build integrated info table - * GMC FB access requred - * - * - * @param[in] StdHeader Standard configuration header - * @retval AGESA_STATUS - */ -AGESA_STATUS -GfxIntegratedInfoTableEntry ( - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - AGESA_STATUS AgesaStatus; - AGESA_STATUS Status; - GFX_PLATFORM_CONFIG *Gfx; - IDS_HDT_CONSOLE (GNB_TRACE, "GfxIntegratedInfoTableEntry Enter\n"); - AgesaStatus = AGESA_SUCCESS; - if (GfxLibIsControllerPresent (StdHeader)) { - Status = GfxLocateConfigData (StdHeader, &Gfx); - AGESA_STATUS_UPDATE (Status, AgesaStatus); - if (Status != AGESA_FATAL) { - Status = GfxIntegratedInfoTableInit (Gfx); - AGESA_STATUS_UPDATE (Status, AgesaStatus); - } - } - IDS_HDT_CONSOLE (GNB_TRACE, "GfxIntegratedInfoTableEntry Exit[0x%x]\n", AgesaStatus); - return AgesaStatus; -} - -/*----------------------------------------------------------------------------------------*/ -/** - * Build integrated info table - * - * - * - * @param[in] Gfx Gfx configuration info - * @retval AGESA_STATUS - */ -AGESA_STATUS -GfxIntegratedInfoTableInit ( - IN GFX_PLATFORM_CONFIG *Gfx - ) -{ - AGESA_STATUS Status; - AGESA_STATUS AgesaStatus; - ATOM_FUSION_SYSTEM_INFO_V1 SystemInfoV1Table; - PP_FUSE_ARRAY *PpFuseArray; - PCIe_PLATFORM_CONFIG *Pcie; - UINT32 IntegratedInfoAddress; - ATOM_PPLIB_POWERPLAYTABLE3 *PpTable; - UINT8 Channel; - - AgesaStatus = AGESA_SUCCESS; - IDS_HDT_CONSOLE (GNB_TRACE, "GfxIntegratedInfoTableInit Enter\n"); - LibAmdMemFill (&SystemInfoV1Table, 0x00, sizeof (ATOM_FUSION_SYSTEM_INFO_V1), GnbLibGetHeader (Gfx)); - SystemInfoV1Table.sIntegratedSysInfo.sHeader.usStructureSize = sizeof (ATOM_INTEGRATED_SYSTEM_INFO_V6); - ASSERT (SystemInfoV1Table.sIntegratedSysInfo.sHeader.usStructureSize == 512); - SystemInfoV1Table.sIntegratedSysInfo.sHeader.ucTableFormatRevision = 1; - SystemInfoV1Table.sIntegratedSysInfo.sHeader.ucTableContentRevision = 6; - SystemInfoV1Table.sIntegratedSysInfo.ulDentistVCOFreq = GfxLibGetMainPllFreq (GnbLibGetHeader (Gfx)) * 100; - SystemInfoV1Table.sIntegratedSysInfo.ulBootUpUMAClock = Gfx->UmaInfo.MemClock * 100; - SystemInfoV1Table.sIntegratedSysInfo.usRequestedPWMFreqInHz = Gfx->LcdBackLightControl; - SystemInfoV1Table.sIntegratedSysInfo.ucUMAChannelNumber = ((Gfx->UmaInfo.UmaAttributes & UMA_ATTRIBUTE_INTERLEAVE) == 0) ? 1 : 2; - SystemInfoV1Table.sIntegratedSysInfo.ucMemoryType = 3; //DDR3 - SystemInfoV1Table.sIntegratedSysInfo.ulBootUpEngineClock = 200 * 100; //Set default engine clock to 200MhZ - SystemInfoV1Table.sIntegratedSysInfo.usBootUpNBVoltage = GnbLocateHighestVidIndex (GnbLibGetHeader (Gfx)); - SystemInfoV1Table.sIntegratedSysInfo.ulMinEngineClock = GfxLibGetMinSclk (GnbLibGetHeader (Gfx)); - SystemInfoV1Table.sIntegratedSysInfo.usPanelRefreshRateRange = Gfx->DynamicRefreshRate; - - SystemInfoV1Table.sIntegratedSysInfo.usLvdsSSPercentage = Gfx->LvdsSpreadSpectrum; - SystemInfoV1Table.sIntegratedSysInfo.usLvdsSSpreadRateIn10Hz = Gfx->LvdsSpreadSpectrumRate; - SystemInfoV1Table.sIntegratedSysInfo.usPCIEClkSSPercentage = Gfx->PcieRefClkSpreadSpectrum; - - //Locate PCIe configuration data to get definitions of display connectors - SystemInfoV1Table.sIntegratedSysInfo.sExtDispConnInfo.sHeader.usStructureSize = sizeof (ATOM_EXTERNAL_DISPLAY_CONNECTION_INFO); - SystemInfoV1Table.sIntegratedSysInfo.sExtDispConnInfo.sHeader.ucTableFormatRevision = 1; - SystemInfoV1Table.sIntegratedSysInfo.sExtDispConnInfo.sHeader.ucTableContentRevision = 1; - SystemInfoV1Table.sIntegratedSysInfo.sExtDispConnInfo.uc3DStereoPinId = Gfx->Gnb3dStereoPinIndex; - - ASSERT ((Gfx->UmaInfo.UmaAttributes & (UMA_ATTRIBUTE_ON_DCT0 | UMA_ATTRIBUTE_ON_DCT1)) != 0); - - if ((Gfx->UmaInfo.UmaAttributes & UMA_ATTRIBUTE_ON_DCT0) != 0) { - Channel = 0; - } else { - Channel = 1; - } - if (GfxLibGetCsrPhySrPllPdMode (Channel, GnbLibGetHeader (Gfx)) != 0) { - SystemInfoV1Table.sIntegratedSysInfo.ulSystemConfig |= BIT2; - } - if (GfxLibGetDisDllShutdownSR (Channel, GnbLibGetHeader (Gfx)) == 0) { - SystemInfoV1Table.sIntegratedSysInfo.ulSystemConfig |= BIT1; - } - Status = PcieLocateConfigurationData (GnbLibGetHeader (Gfx), &Pcie); - ASSERT (Status == AGESA_SUCCESS); - AGESA_STATUS_UPDATE (Status, AgesaStatus); - if (Status == AGESA_SUCCESS) { - Status = GfxIntegratedEnumerateAllConnectors ( - &SystemInfoV1Table.sIntegratedSysInfo.sExtDispConnInfo.sPath[0], - Pcie, - Gfx - ); - AGESA_STATUS_UPDATE (Status, AgesaStatus); - } - SystemInfoV1Table.sIntegratedSysInfo.usExtDispConnInfoOffset = offsetof (ATOM_INTEGRATED_SYSTEM_INFO_V6, sExtDispConnInfo); - // Build PP table - PpTable = (ATOM_PPLIB_POWERPLAYTABLE3*) &SystemInfoV1Table.ulPowerplayTable; - // Build PP table - Status = GfxPowerPlayBuildTable (PpTable, Gfx); - AGESA_STATUS_UPDATE (Status, AgesaStatus); - // Build info from fuses - PpFuseArray = GnbLocateHeapBuffer (AMD_PP_FUSE_TABLE_HANDLE, GnbLibGetHeader (Gfx)); - ASSERT (PpFuseArray != NULL); - if (PpFuseArray != NULL) { - // Build Display clock info - GfxIntegratedInfoInitDispclkTable (PpFuseArray, &SystemInfoV1Table.sIntegratedSysInfo, Gfx); - // Build Sclk info table - GfxIntegratedInfoInitSclkTable (PpFuseArray, &SystemInfoV1Table.sIntegratedSysInfo, Gfx); - } else { - Status = AGESA_ERROR; - AGESA_STATUS_UPDATE (Status, AgesaStatus); - } - // Fill in HTC Data - GfxFillHtcData (&SystemInfoV1Table.sIntegratedSysInfo, Gfx); - // Fill in NB P states VID - GfxFillNbPStateVid (&SystemInfoV1Table.sIntegratedSysInfo, Gfx); - // Fill in NCLK info - GfxFillNclkInfo (&SystemInfoV1Table.sIntegratedSysInfo, Gfx); - // Fill in the M3 arbitration control tables - GfxFillM3ArbritrationControl (&SystemInfoV1Table.sIntegratedSysInfo, Gfx); - // Fill South bridge MMIO Base address - GfxFillSbMmioBaseAddress (&SystemInfoV1Table.sIntegratedSysInfo, Gfx); - // Family specific data update - GfxFmIntegratedInfoTableInit (&SystemInfoV1Table.sIntegratedSysInfo, Gfx); - IDS_OPTION_CALLOUT (IDS_CALLOUT_GNB_INTEGRATED_TABLE_CONFIG, &SystemInfoV1Table.sIntegratedSysInfo, GnbLibGetHeader (Gfx)); - //Copy integrated info table to Frame Buffer. (Do not use LibAmdMemCopy, routine not guaranteed access to above 4G memory in 32 bit mode.) - IntegratedInfoAddress = (UINT32) (Gfx->UmaInfo.UmaSize - sizeof (ATOM_FUSION_SYSTEM_INFO_V1)); - GfxLibCopyMemToFb ((VOID *) (&SystemInfoV1Table), IntegratedInfoAddress, sizeof (ATOM_FUSION_SYSTEM_INFO_V1), Gfx); - IDS_HDT_CONSOLE (GNB_TRACE, "GfxIntegratedInfoTableInit Exit [0x%x]\n", Status); - return Status; -} - -/*----------------------------------------------------------------------------------------*/ -/** - *Init Dispclk <-> VID table - * - * - * @param[in] PpFuseArray Fuse array pointer - * @param[in] IntegratedInfoTable Integrated info table pointer - * @param[in] Gfx Gfx configuration info - */ - -VOID -GfxIntegratedInfoInitDispclkTable ( - IN PP_FUSE_ARRAY *PpFuseArray, - IN ATOM_INTEGRATED_SYSTEM_INFO_V6 *IntegratedInfoTable, - IN GFX_PLATFORM_CONFIG *Gfx - ) -{ - UINTN Index; - for (Index = 0; Index < 4; Index++) { - if (PpFuseArray->DisplclkDid[Index] != 0) { - IntegratedInfoTable->sDISPCLK_Voltage[Index].ulMaximumSupportedCLK = GfxLibCalculateClk ( - PpFuseArray->DisplclkDid[Index], - IntegratedInfoTable->ulDentistVCOFreq - ); - IntegratedInfoTable->sDISPCLK_Voltage[Index].ulVoltageIndex = (ULONG) Index; - } - } -} - -/*----------------------------------------------------------------------------------------*/ -/** - *Init Sclk <-> VID table - * - * - * @param[in] PpFuseArray Fuse array pointer - * @param[in] IntegratedInfoTable Integrated info table pointer - * @param[in] Gfx Gfx configuration info - */ - -VOID -GfxIntegratedInfoInitSclkTable ( - IN PP_FUSE_ARRAY *PpFuseArray, - IN ATOM_INTEGRATED_SYSTEM_INFO_V6 *IntegratedInfoTable, - IN GFX_PLATFORM_CONFIG *Gfx - ) -{ - UINTN Index; - UINTN TargetIndex; - UINTN ValidSclkStateMask; - UINT8 TempDID; - UINT8 SclkVidArray[4]; - UINTN AvailSclkIndex; - ATOM_AVAILABLE_SCLK_LIST *AvailSclkList; - BOOLEAN Sorting; - AvailSclkList = &IntegratedInfoTable->sAvail_SCLK[0]; - GnbLibPciRead ( - MAKE_SBDFO ( 0, 0, 0x18, 3, D18F3x15C_ADDRESS), - AccessWidth32, - &SclkVidArray[0], - GnbLibGetHeader (Gfx) - ); - AvailSclkIndex = 0; - for (Index = 0; Index < MAX_NUM_OF_FUSED_DPM_STATES; Index++) { - if (PpFuseArray->SclkDpmDid[Index] != 0) { - AvailSclkList[AvailSclkIndex].ulSupportedSCLK = GfxLibCalculateClk (PpFuseArray->SclkDpmDid[Index], IntegratedInfoTable->ulDentistVCOFreq); - AvailSclkList[AvailSclkIndex].usVoltageIndex = PpFuseArray->SclkDpmVid[Index]; - AvailSclkList[AvailSclkIndex].usVoltageID = SclkVidArray [PpFuseArray->SclkDpmVid[Index]]; - AvailSclkIndex++; - } - } - //Sort by VoltageIndex & ulSupportedSCLK - if (AvailSclkIndex > 1) { - do { - Sorting = FALSE; - for (Index = 0; Index < (AvailSclkIndex - 1); Index++) { - ATOM_AVAILABLE_SCLK_LIST Temp; - BOOLEAN Exchange; - Exchange = FALSE; - if (AvailSclkList[Index].usVoltageIndex > AvailSclkList[Index + 1].usVoltageIndex) { - Exchange = TRUE; - } - if ((AvailSclkList[Index].usVoltageIndex == AvailSclkList[Index + 1].usVoltageIndex) && - (AvailSclkList[Index].ulSupportedSCLK > AvailSclkList[Index + 1].ulSupportedSCLK)) { - Exchange = TRUE; - } - if (Exchange) { - Sorting = TRUE; - LibAmdMemCopy (&Temp, &AvailSclkList[Index], sizeof (ATOM_AVAILABLE_SCLK_LIST), GnbLibGetHeader (Gfx)); - LibAmdMemCopy (&AvailSclkList[Index], &AvailSclkList[Index + 1], sizeof (ATOM_AVAILABLE_SCLK_LIST), GnbLibGetHeader (Gfx)); - LibAmdMemCopy (&AvailSclkList[Index + 1], &Temp, sizeof (ATOM_AVAILABLE_SCLK_LIST), GnbLibGetHeader (Gfx)); - } - } - } while (Sorting); - } - - if (PpFuseArray->GpuBoostCap == 1) { - IntegratedInfoTable->SclkDpmThrottleMargin = PpFuseArray->SclkDpmThrottleMargin; - IntegratedInfoTable->SclkDpmTdpLimitPG = PpFuseArray->SclkDpmTdpLimitPG; - IntegratedInfoTable->EnableBoost = PpFuseArray->GpuBoostCap; - IntegratedInfoTable->SclkDpmBoostMargin = PpFuseArray->SclkDpmBoostMargin; - IntegratedInfoTable->SclkDpmTdpLimitBoost = (PpFuseArray->SclkDpmTdpLimit)[5]; - IntegratedInfoTable->ulBoostEngineCLock = GfxFmCalculateClock ((PpFuseArray->SclkDpmDid)[5], GnbLibGetHeader (Gfx)); - IntegratedInfoTable->ulBoostVid_2bit = (PpFuseArray->SclkDpmVid)[5]; - - ValidSclkStateMask = 0; - TargetIndex = 0; - for (Index = 0; Index < 6; Index++) { - ValidSclkStateMask |= (PpFuseArray->SclkDpmValid)[Index]; - } - TempDID = 0x7F; - for (Index = 0; Index < 6; Index++) { - if ((ValidSclkStateMask & ((UINTN)1 << Index)) != 0) { - if ((PpFuseArray->SclkDpmDid)[Index] <= TempDID) { - TempDID = (PpFuseArray->SclkDpmDid)[Index]; - TargetIndex = Index; - } - } - } - IntegratedInfoTable->GnbTdpLimit = (PpFuseArray->SclkDpmTdpLimit)[TargetIndex]; - } - -} - -/*----------------------------------------------------------------------------------------*/ -/** - *Init HTC Data - * - * - * @param[in] IntegratedInfoTable Integrated info table pointer - * @param[in] Gfx Gfx configuration info - */ - -VOID -GfxFillHtcData ( - IN OUT ATOM_INTEGRATED_SYSTEM_INFO_V6 *IntegratedInfoTable, - IN GFX_PLATFORM_CONFIG *Gfx - ) -{ - D18F3x64_STRUCT D18F3x64; - - GnbLibPciRead ( - MAKE_SBDFO ( 0, 0, 0x18, 3, D18F3x64_ADDRESS), - AccessWidth32, - &D18F3x64.Value, - GnbLibGetHeader (Gfx) - ); - IntegratedInfoTable->ucHtcTmpLmt = (UCHAR) (D18F3x64.Field.HtcTmpLmt / 2 + 52); - IntegratedInfoTable->ucHtcHystLmt = (UCHAR) (D18F3x64.Field.HtcHystLmt / 2); -} - -/*----------------------------------------------------------------------------------------*/ -/** - *Init NbPstateVid - * - * - * @param[in] IntegratedInfoTable Integrated info table pointer - * @param[in] Gfx Gfx configuration info - */ - -VOID -GfxFillNbPStateVid ( - IN OUT ATOM_INTEGRATED_SYSTEM_INFO_V6 *IntegratedInfoTable, - IN GFX_PLATFORM_CONFIG *Gfx - ) -{ - D18F3xDC_STRUCT D18F3xDC; - D18F6x90_STRUCT D18F6x90; - - GnbLibPciRead ( - MAKE_SBDFO ( 0, 0, 0x18, 3, D18F3xDC_ADDRESS), - AccessWidth32, - &D18F3xDC.Value, - GnbLibGetHeader (Gfx) - ); - IntegratedInfoTable->usNBP0Voltage = (USHORT) D18F3xDC.Field.NbPs0Vid; - - GnbLibPciRead ( - MAKE_SBDFO ( 0, 0, 0x18, 6, D18F6x90_ADDRESS), - AccessWidth32, - &D18F6x90.Value, - GnbLibGetHeader (Gfx) - ); - IntegratedInfoTable->usNBP1Voltage = (USHORT) D18F6x90.Field.NbPs1Vid; - IntegratedInfoTable->ulMinimumNClk = GfxLibCalculateClk ( - (UINT8) (((D18F6x90.Field.NbPs1NclkDiv != 0) && (D18F6x90.Field.NbPs1NclkDiv < D18F3xDC.Field.NbPs0NclkDiv)) ? D18F6x90.Field.NbPs1NclkDiv : D18F3xDC.Field.NbPs0NclkDiv), - IntegratedInfoTable->ulDentistVCOFreq - ); -} - -/*----------------------------------------------------------------------------------------*/ -/** - *Init M3 Arbitration Control values. - * - * - * @param[in] IntegratedInfoTable Integrated info table pointer - * @param[in] Gfx Gfx configuration info - */ - -VOID -GfxFillM3ArbritrationControl ( - IN OUT ATOM_INTEGRATED_SYSTEM_INFO_V6 *IntegratedInfoTable, - IN GFX_PLATFORM_CONFIG *Gfx - ) -{ - LibAmdMemCopy (IntegratedInfoTable->ulCSR_M3_ARB_CNTL_DEFAULT, ulCSR_M3_ARB_CNTL_DEFAULT, sizeof (ulCSR_M3_ARB_CNTL_DEFAULT), GnbLibGetHeader (Gfx)); - LibAmdMemCopy (IntegratedInfoTable->ulCSR_M3_ARB_CNTL_UVD, ulCSR_M3_ARB_CNTL_UVD, sizeof (ulCSR_M3_ARB_CNTL_UVD), GnbLibGetHeader (Gfx)); - LibAmdMemCopy (IntegratedInfoTable->ulCSR_M3_ARB_CNTL_FS3D, ulCSR_M3_ARB_CNTL_FS3D, sizeof (ulCSR_M3_ARB_CNTL_FS3D), GnbLibGetHeader (Gfx)); -} - -/*----------------------------------------------------------------------------------------*/ -/** - *Init M3 Arbitration Control values. - * - * - * @param[in] IntegratedInfoTable Integrated info table pointer - * @param[in] Gfx Gfx configuration info - */ - -VOID -GfxFillSbMmioBaseAddress ( - IN OUT ATOM_INTEGRATED_SYSTEM_INFO_V6 *IntegratedInfoTable, - IN GFX_PLATFORM_CONFIG *Gfx - ) -{ - IntegratedInfoTable->ulSB_MMIO_Base_Addr = SbGetSbMmioBaseAddress (GnbLibGetHeader (Gfx)) ; - IDS_HDT_CONSOLE (GFX_MISC, " ulSB_MMIO_Base_Addr = 0x%x\n", IntegratedInfoTable->ulSB_MMIO_Base_Addr); -} - -/*----------------------------------------------------------------------------------------*/ -/** - * Fill in NCLK info - * - * set ulMinimumNClk and ulIdleNClk - * - * @param[in] IntegratedInfoTable Integrated info table pointer - * @param[in] Gfx Gfx configuration info - */ - -VOID -GfxFillNclkInfo ( - IN OUT ATOM_INTEGRATED_SYSTEM_INFO_V6 *IntegratedInfoTable, - IN GFX_PLATFORM_CONFIG *Gfx - ) -{ - - D18F3xA0_STRUCT D18F3xA0; - D18F6x9C_STRUCT D18F6x9C; - D18F3xDC_STRUCT D18F3xDC; - D18F6x90_STRUCT D18F6x90; - - // - // ulIdleNClk = GfxLibGetMainPllFreq (...) / F6x9C[NclkRedDiv] divisor (main PLL frequency / NCLK divisor) - // - GnbLibPciRead ( - MAKE_SBDFO ( 0, 0, 0x18, 6, D18F6x9C_ADDRESS), - AccessWidth32, - &D18F6x9C.Value, - GnbLibGetHeader (Gfx) - ); - - IntegratedInfoTable->ulIdleNClk = GfxLibCalculateIdleNclk ( - (UINT8) D18F6x9C.Field.NclkRedDiv, - IntegratedInfoTable->ulDentistVCOFreq - ); - - // - // Set ulMinimumNClk depends on CPU fused and NB Pstate. - // - GnbLibPciRead ( - MAKE_SBDFO ( 0, 0, 0x18, 3, D18F3xA0_ADDRESS), - AccessWidth32, - &D18F3xA0.Value, - GnbLibGetHeader (Gfx) - ); - - if (D18F3xA0.Field.CofVidProg) { - - GnbLibPciRead ( - MAKE_SBDFO ( 0, 0, 0x18, 3, D18F3xDC_ADDRESS), - AccessWidth32, - &D18F3xDC.Value, - GnbLibGetHeader (Gfx) - ); - - GnbLibPciRead ( - MAKE_SBDFO ( 0, 0, 0x18, 6, D18F6x90_ADDRESS), - AccessWidth32, - &D18F6x90.Value, - GnbLibGetHeader (Gfx) - ); - - // - // Set ulMinimumNClk if (F6x90[NbPsCap]==1 && F6x90[NbPsCtrlDis]==0) then ( - // GfxLibGetMainPllFreq (...) / F6x90[NbPs1NclkDiv] divisor - // ) else ( GfxLibGetMainPllFreq (...) / F3xDC[NbPs0NclkDiv] divisor - // ) - // - IntegratedInfoTable->ulMinimumNClk = GfxLibCalculateNclk ( - (UINT8) (((D18F6x90.Field.NbPsCap == 1) && (D18F6x90.Field.NbPsCtrlDis == 0)) ? D18F6x90.Field.NbPs1NclkDiv : D18F3xDC.Field.NbPs0NclkDiv), - IntegratedInfoTable->ulDentistVCOFreq - ); - } else { - IntegratedInfoTable->ulMinimumNClk = 200 * 100; - } - -} diff --git a/src/vendorcode/amd/agesa/f12/Proc/GNB/Gfx/GfxIntegratedInfoTableInit.h b/src/vendorcode/amd/agesa/f12/Proc/GNB/Gfx/GfxIntegratedInfoTableInit.h deleted file mode 100644 index c933ceae25..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/GNB/Gfx/GfxIntegratedInfoTableInit.h +++ /dev/null @@ -1,60 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * Service procedure to initialize Integrated Info Table - * - * - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: GNB - * @e \$Revision: 45310 $ @e \$Date: 2011-01-14 18:12:32 +0800 (Fri, 14 Jan 2011) $ - * - */ -/* -***************************************************************************** -* -* Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* *************************************************************************** -* -*/ -#ifndef _GFXINTEGRATEDINFOTABLEINIT_H_ -#define _GFXINTEGRATEDINFOTABLEINIT_H_ - - -#define SB_IOMAP_REGCD6 0x0CD6 // PM_Index -#define SB_IOMAP_REGCD7 0x0CD7 // PM_Data -#define SB_MMIO_BASE_REG 0x24 // PMIO register 0x24 has SB MMIO base -#define SB_MMIO_DECODE_ENABLE BIT0 -#define SB_MMIO_IO_MAPPED_ENABLE BIT1 - -AGESA_STATUS -GfxIntegratedInfoTableEntry ( - IN AMD_CONFIG_PARAMS *StdHeader - ); - -#endif diff --git a/src/vendorcode/amd/agesa/f12/Proc/GNB/Gfx/GfxLib.c b/src/vendorcode/amd/agesa/f12/Proc/GNB/Gfx/GfxLib.c deleted file mode 100644 index e9fb5c0072..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/GNB/Gfx/GfxLib.c +++ /dev/null @@ -1,343 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * Initialize PP/DPM fuse table. - * - * - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: GNB - * @e \$Revision: 50955 $ @e \$Date: 2011-04-16 04:51:05 +0800 (Sat, 16 Apr 2011) $ - * - */ -/* -***************************************************************************** -* -* Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* *************************************************************************** -* -*/ - -/*---------------------------------------------------------------------------------------- - * M O D U L E S U S E D - *---------------------------------------------------------------------------------------- - */ -#include "AGESA.h" -#include "amdlib.h" -#include "Ids.h" -#include "heapManager.h" -#include "Gnb.h" -#include "GnbGfx.h" -#include "GnbFuseTable.h" -#include "GnbCommonLib.h" -#include "GfxLib.h" -#include "GnbRegistersLN.h" -#include "Filecode.h" -#define FILECODE PROC_GNB_GFX_GFXLIB_FILECODE -/*---------------------------------------------------------------------------------------- - * D E F I N I T I O N S A N D M A C R O S - *---------------------------------------------------------------------------------------- - */ - - - -/*---------------------------------------------------------------------------------------- - * T Y P E D E F S A N D S T R U C T U R E S - *---------------------------------------------------------------------------------------- - */ - - -/*---------------------------------------------------------------------------------------- - * P R O T O T Y P E S O F L O C A L F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ - -/*----------------------------------------------------------------------------------------*/ -/** - * Calculate main PLL VCO - * - * - * - * @param[in] StdHeader Standard configuration header - * @retval main PLL COF in Mhz - */ - -UINT32 -GfxLibGetMainPllFreq ( - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - UINT32 MainPllFreq; - D18F3xD4_STRUCT D18F3xD4; - GnbLibPciRead ( - MAKE_SBDFO ( 0, 0, 0x18, 3, D18F3xD4_ADDRESS), - AccessWidth32, - &D18F3xD4.Value, - StdHeader - ); - MainPllFreq = 100 * (D18F3xD4.Field.MainPllOpFreqId + 0x10); - return MainPllFreq; -} - -/*----------------------------------------------------------------------------------------*/ -/** - * Calculate clock from main VCO - * - * - * - * @param[in] Did Fuse Divider - * @param[in] MainPllVco Main Pll COF in 10KHz - * @retval Clock in 10KHz - */ - -UINT32 -GfxLibCalculateClk ( - IN UINT8 Did, - IN UINT32 MainPllVco - ) -{ - UINT32 Divider; - if (Did >= 8 && Did <= 0x3F) { - Divider = Did * 25; - } else if (Did > 0x3F && Did <= 0x5F) { - Divider = (Did - 64) * 50 + 1600; - } else if (Did > 0x5F && Did <= 0x7E) { - Divider = (Did - 96) * 100 + 3200; - } else if (Did == 0x7f) { - Divider = 128 * 100; - } else { - ASSERT (FALSE); - return 200 * 100; - } - ASSERT (Divider != 0); - return (((MainPllVco * 100) + (Divider - 1)) / Divider); -} - -/*----------------------------------------------------------------------------------------*/ -/** - * Calculate did from main VCO - * - * - * - * @param[in] Vco Vco in 10Khz - * @param[in] MainPllVco Main Pll COF in 10Khz - * @retval DID - */ - -UINT8 -GfxLibCalculateDid ( - IN UINT32 Vco, - IN UINT32 MainPllVco - ) -{ - UINT32 Divider; - UINT8 Did; - ASSERT (Vco != 0); - Divider = ((MainPllVco * 100) + (Vco - 1)) / Vco; - Did = 0; - if (Divider < 200) { - } else if (Divider <= 1575) { - Did = (UINT8) (Divider / 25); - } else if (Divider <= 3150) { - Did = (UINT8) ((Divider - 1600) / 50) + 64; - } else if (Divider <= 6200) { - Did = (UINT8) ((Divider - 3200) / 100) + 96; - } else { - Did = 0x7f; - } - return Did; -} - -/*----------------------------------------------------------------------------------------*/ -/** - * Get max non 0 VID index - * - * - * @param[in] StdHeader Standard configuration header - * @retval NBVDD VID index - */ -UINT8 -GfxLibMaxVidIndex ( - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - UINT8 MaxVid; - UINT8 MaxVidIndex; - UINT8 SclkVidArray[4]; - UINTN Index; - - GnbLibPciRead ( - MAKE_SBDFO ( 0, 0, 0x18, 3, D18F3x15C_ADDRESS), - AccessWidth32, - &SclkVidArray[0], - StdHeader - ); - MaxVidIndex = 0; - MaxVid = 0xff; - for (Index = 0; Index < 4; Index++) { - if (SclkVidArray[Index] != 0 && SclkVidArray[Index] < MaxVid) { - MaxVid = SclkVidArray[Index]; - MaxVidIndex = (UINT8) Index; - } - } - return MaxVidIndex; -} - - -/*----------------------------------------------------------------------------------------*/ -/** - * Get min SCLK - * - * - * @param[in] StdHeader Standard configuration header - * @retval Min SCLK in 10 khz - */ -UINT32 -GfxLibGetMinSclk ( - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - UINT32 WrCkClk; - UINT32 MinSclkClk; - WrCkClk = GfxLibGetWrCk (StdHeader); - - if ((2 * WrCkClk) < (8 * 100)) { - MinSclkClk = 8 * 100; - } else { - MinSclkClk = 2 * WrCkClk + 100; - } - return MinSclkClk; -} - -/*----------------------------------------------------------------------------------------*/ -/** - * Get min WRCK - * - * - * @param[in] StdHeader Standard configuration header - * @retval Min WRCK in 10 khZ - */ -UINT32 -GfxLibGetWrCk ( - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - PP_FUSE_ARRAY *PpFuseArray; - UINT8 WrCk; - PpFuseArray = GnbLocateHeapBuffer (AMD_PP_FUSE_TABLE_HANDLE, StdHeader); - ASSERT (PpFuseArray != NULL); - if (PpFuseArray != NULL) { - if (PpFuseArray->WrCkDid == 0x0) { - WrCk = 2; - } else if (PpFuseArray->WrCkDid <= 0x10) { - WrCk = PpFuseArray->WrCkDid + 1; - } else if (PpFuseArray->WrCkDid <= 0x1C) { - WrCk = 24 + 8 * (PpFuseArray->WrCkDid - 0x10); - } else { - WrCk = 128; - } - } else { - WrCk = 2; - } - return 100 * 100 / WrCk; -} - -/*----------------------------------------------------------------------------------------*/ -/** - * Calculate NCLK clock from main VCO - * - * - * - * @param[in] Did NCLK Divider - * @param[in] MainPllVco Main Pll COF in 10KHz - * @retval Clock in 10KHz - */ - -UINT32 -GfxLibCalculateNclk ( - IN UINT8 Did, - IN UINT32 MainPllVco - ) -{ - UINT32 Divider; - if (Did >= 8 && Did <= 0x3F) { - Divider = Did * 25; - } else if (Did > 0x3F && Did <= 0x5F) { - Divider = (Did - 64) * 50 + 1600; - } else if (Did > 0x5F && Did <= 0x7F) { - Divider = (Did - 64) * 100; - } else { - ASSERT (FALSE); - return 200 * 100; - } - ASSERT (Divider != 0); - return ((MainPllVco * 100) / Divider); -} - -/*----------------------------------------------------------------------------------------*/ -/** - * Calculate idle NCLK clock from main VCO - * - * - * - * @param[in] Did NCLK Divider - * @param[in] MainPllVco Main Pll COF in 10KHz - * @retval Clock in 10KHz - */ - -UINT32 -GfxLibCalculateIdleNclk ( - IN UINT8 Did, - IN UINT32 MainPllVco - ) -{ - UINT32 Divider; - switch (Did) { - case 0x20: - Divider = 8; - break; - case 0x40: - Divider = 16; - break; - case 0x60: - Divider = 32; - break; - case 0x78: - Divider = 56; - break; - case 0x7F: - Divider = 128; - break; - default: - ASSERT (FALSE); - return 200 * 100; - break; - } - - return (MainPllVco / Divider); -} diff --git a/src/vendorcode/amd/agesa/f12/Proc/GNB/Gfx/GfxLib.h b/src/vendorcode/amd/agesa/f12/Proc/GNB/Gfx/GfxLib.h deleted file mode 100644 index 625a3b3ad3..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/GNB/Gfx/GfxLib.h +++ /dev/null @@ -1,91 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * various service procedures - * - * - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: GNB - * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $ - * - */ -/* -***************************************************************************** -* -* Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* *************************************************************************** -* -*/ -#ifndef _GFXLIB_H_ -#define _GFXLIB_H_ - -UINT32 -GfxLibGetMainPllFreq ( - IN AMD_CONFIG_PARAMS *StdHeader - ); - -UINT32 -GfxLibCalculateClk ( - IN UINT8 Did, - IN UINT32 MainPllVco - ); - -UINT8 -GfxLibCalculateDid ( - IN UINT32 Vco, - IN UINT32 MainPllVco - ); - -UINT8 -GfxLibMaxVidIndex ( - IN AMD_CONFIG_PARAMS *StdHeader - ); - -UINT32 -GfxLibGetMinSclk ( - IN AMD_CONFIG_PARAMS *StdHeader - ); - -UINT32 -GfxLibGetWrCk ( - IN AMD_CONFIG_PARAMS *StdHeader - ); - -UINT32 -GfxLibCalculateNclk ( - IN UINT8 Did, - IN UINT32 MainPllVco - ); - -UINT32 -GfxLibCalculateIdleNclk ( - IN UINT8 Did, - IN UINT32 MainPllVco - ); -#endif diff --git a/src/vendorcode/amd/agesa/f12/Proc/GNB/Gfx/GfxRegisterAcc.c b/src/vendorcode/amd/agesa/f12/Proc/GNB/Gfx/GfxRegisterAcc.c deleted file mode 100644 index ba4e57d1c8..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/GNB/Gfx/GfxRegisterAcc.c +++ /dev/null @@ -1,208 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * Graphics controller access service routines. - * - * - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: GNB - * @e \$Revision: 48452 $ @e \$Date: 2011-03-09 12:50:44 +0800 (Wed, 09 Mar 2011) $ - * - */ -/* -***************************************************************************** -* -* Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* *************************************************************************** -* -*/ - -/*---------------------------------------------------------------------------------------- - * M O D U L E S U S E D - *---------------------------------------------------------------------------------------- - */ -#include "AGESA.h" -#include "amdlib.h" -#include "Ids.h" -#include "Gnb.h" -#include "GnbGfx.h" -#include "GnbCommonLib.h" -#include "GfxRegisterAcc.h" -#include "GnbRegistersLN.h" -#include "Filecode.h" -#define FILECODE PROC_GNB_GFX_GFXREGISTERACC_FILECODE -/*---------------------------------------------------------------------------------------- - * D E F I N I T I O N S A N D M A C R O S - *---------------------------------------------------------------------------------------- - */ - - -/*---------------------------------------------------------------------------------------- - * T Y P E D E F S A N D S T R U C T U R E S - *---------------------------------------------------------------------------------------- - */ - - -/*---------------------------------------------------------------------------------------- - * P R O T O T Y P E S O F L O C A L F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ - -/*----------------------------------------------------------------------------------------*/ -/** - * Write GMM register - * - * - * @param[in] Address GMM register address - * @param[in] Value Value - * @param[in] S3Save Save for S3 resume - * @param[in] Gfx Pointer to global GFX configuration - */ - -VOID -GmmRegisterWrite ( - IN UINT16 Address, - IN UINT32 Value, - IN BOOLEAN S3Save, - IN GFX_PLATFORM_CONFIG *Gfx - ) -{ - ASSERT (Gfx->GmmBase != 0); - GnbLibMemWrite (Gfx->GmmBase + Address, S3Save ? AccessS3SaveWidth32 : AccessWidth32, &Value, GnbLibGetHeader (Gfx)); -} - -/*----------------------------------------------------------------------------------------*/ -/** - * Read GMM register - * - * - * @param[in] Address GMM register address - * @param[in] Gfx Pointer to global GFX configuration - * @retval Value of GMM register - */ - -UINT32 -GmmRegisterRead ( - IN UINT16 Address, - IN GFX_PLATFORM_CONFIG *Gfx - ) -{ - UINT32 Value; - ASSERT (Gfx->GmmBase != 0); - GnbLibMemRead (Gfx->GmmBase + Address, AccessWidth32, &Value, GnbLibGetHeader (Gfx)); - return Value; -} - -/*----------------------------------------------------------------------------------------*/ -/** - * Write GMM register field - * - * - * @param[in] Address GMM register address - * @param[in] FieldOffset Register field offset - * @param[in] FieldWidth Register field width - * @param[in] Value Field value - * @param[in] S3Save Save for S3 resume - * @param[in] Gfx Pointer to global GFX configuration - */ - -VOID -GmmRegisterWriteField ( - IN UINT16 Address, - IN UINT8 FieldOffset, - IN UINT8 FieldWidth, - IN UINT32 Value, - IN BOOLEAN S3Save, - IN GFX_PLATFORM_CONFIG *Gfx - ) -{ - UINT32 Data; - UINT32 Mask; - Data = GmmRegisterRead (Address, Gfx); - Mask = (1 << FieldWidth) - 1; - Value &= Mask; - Data &= (~(Mask << FieldOffset)); - GmmRegisterWrite (Address, Data | (Value << FieldOffset), S3Save, Gfx); -} - -/*----------------------------------------------------------------------------------------*/ -/** - * Write GMM registers table - * - * - * @param[in] Table Pointer to table - * @param[in] TableLength Number of entries in table - * @param[in] S3Save Save for S3 resume - * @param[in] Gfx Pointer to global GFX configuration - */ - - -VOID -GmmRegisterTableWrite ( - IN GMM_REG_ENTRY Table[], - IN UINTN TableLength, - IN BOOLEAN S3Save, - IN GFX_PLATFORM_CONFIG *Gfx - ) -{ - UINTN Index; - for (Index = 0; Index < TableLength; Index++) { - GmmRegisterWrite (Table[Index].GmmReg, Table[Index].GmmData, S3Save, Gfx); - } -} - -/*----------------------------------------------------------------------------------------*/ -/** - * Copy memory content to FB - * - * - * @param[in] Source Pointer to source - * @param[in] FbOffset FB offset - * @param[in] Length The length to copy - * @param[in] Gfx Pointer to global GFX configuration - * - */ -VOID -GfxLibCopyMemToFb ( - IN VOID *Source, - IN UINT32 FbOffset, - IN UINT32 Length, - IN GFX_PLATFORM_CONFIG *Gfx - ) -{ - GMMx00_STRUCT GMMx00; - GMMx04_STRUCT GMMx04; - UINT32 Index; - for (Index = 0; Index < Length; Index = Index + 4 ) { - GMMx00.Value = 0x80000000 | (FbOffset + Index); - GMMx04.Value = *(UINT32*) ((UINT8*)Source + Index); - GmmRegisterWrite (GMMx00_ADDRESS, GMMx00.Value, FALSE, Gfx); - GmmRegisterWrite (GMMx04_ADDRESS, GMMx04.Value, FALSE, Gfx); - } -} diff --git a/src/vendorcode/amd/agesa/f12/Proc/GNB/Gfx/GfxRegisterAcc.h b/src/vendorcode/amd/agesa/f12/Proc/GNB/Gfx/GfxRegisterAcc.h deleted file mode 100644 index 76d3cb33db..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/GNB/Gfx/GfxRegisterAcc.h +++ /dev/null @@ -1,112 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * Graphics controller access service routines. - * - * - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: GNB - * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $ - * - */ -/* -***************************************************************************** -* -* Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* *************************************************************************** -* -*/ -#ifndef _GFXREGISTERACC_H_ -#define _GFXREGISTERACC_H_ - -/// GMM Register Entry -typedef struct { - UINT16 GmmReg; ///< Register - UINT32 GmmData; ///< Data -} GMM_REG_ENTRY; - -/// Register to Register copy -typedef struct { - UINT32 CpuReg; ///< CPU Register - UINT16 GmmReg; ///< GMM Register - UINT8 CpuOffset; ///< CPU register field start bit - UINT8 CpuWidth; ///< CPU register field width - UINT8 GmmOffset; ///< GMM register field start bit - UINT8 GmmWidth; ///< GMM register field width -} REGISTER_COPY_ENTRY; - - -/// Table length and table pointer -typedef struct { - UINT32 TableLength; ///< Table Length - VOID* TablePtr; ///< Table Pointer -} TABLE_INDIRECT_PTR; - -VOID -GmmRegisterWrite ( - IN UINT16 Address, - IN UINT32 Value, - IN BOOLEAN S3Save, - IN GFX_PLATFORM_CONFIG *Gfx - ); - -UINT32 -GmmRegisterRead ( - IN UINT16 Address, - IN GFX_PLATFORM_CONFIG *Gfx - ); - -VOID -GmmRegisterWriteField ( - IN UINT16 Address, - IN UINT8 FieldOffset, - IN UINT8 FieldWidth, - IN UINT32 Value, - IN BOOLEAN S3Save, - IN GFX_PLATFORM_CONFIG *Gfx - ); - - -VOID -GmmRegisterTableWrite ( - IN GMM_REG_ENTRY Table[], - IN UINTN TableLength, - IN BOOLEAN S3Save, - IN GFX_PLATFORM_CONFIG *Gfx - ); - -VOID -GfxLibCopyMemToFb ( - IN VOID *Source, - IN UINT32 FbOffset, - IN UINT32 Length, - IN GFX_PLATFORM_CONFIG *Gfx - ); - -#endif diff --git a/src/vendorcode/amd/agesa/f12/Proc/GNB/Gfx/GfxStrapsInit.c b/src/vendorcode/amd/agesa/f12/Proc/GNB/Gfx/GfxStrapsInit.c deleted file mode 100644 index c78c7bdb99..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/GNB/Gfx/GfxStrapsInit.c +++ /dev/null @@ -1,271 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * Graphics controller BIF straps control services. - * - * - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: GNB - * @e \$Revision: 51087 $ @e \$Date: 2011-04-19 07:38:57 +0800 (Tue, 19 Apr 2011) $ - * - */ -/* -***************************************************************************** -* -* Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* *************************************************************************** -* -*/ - -/*---------------------------------------------------------------------------------------- - * M O D U L E S U S E D - *---------------------------------------------------------------------------------------- - */ -#include "AGESA.h" -#include "amdlib.h" -#include "Ids.h" -//#include "heapManager.h" -#include "Gnb.h" -#include "GnbGfx.h" -#include "GnbCommonLib.h" -#include "GnbNbInitLibV1.h" -#include "GfxStrapsInit.h" -#include "GfxLib.h" -#include "GfxRegisterAcc.h" -#include "NbSmuLib.h" -#include "OptionGnb.h" -#include "GnbRegistersLN.h" -#include "Filecode.h" -#define FILECODE PROC_GNB_GFX_GFXSTRAPSINIT_FILECODE -/*---------------------------------------------------------------------------------------- - * D E F I N I T I O N S A N D M A C R O S - *---------------------------------------------------------------------------------------- - */ -extern BUILD_OPT_CFG UserOptions; -extern GNB_BUILD_OPTIONS GnbBuildOptions; - -/*---------------------------------------------------------------------------------------- - * T Y P E D E F S A N D S T R U C T U R E S - *---------------------------------------------------------------------------------------- - */ - - -/*---------------------------------------------------------------------------------------- - * P R O T O T Y P E S O F L O C A L F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ - -/*----------------------------------------------------------------------------------------*/ -/** - * Initialize GFX straps. - * - * - * @param[in] Gfx Pointer to global GFX configuration - * @retval AGESA_STATUS - */ - -AGESA_STATUS -GfxStrapsInit ( - IN GFX_PLATFORM_CONFIG *Gfx - ) -{ - D0F0x64_x1C_STRUCT D0F0x64_x1C; - D0F0x64_x1D_STRUCT D0F0x64_x1D; - IDS_HDT_CONSOLE (GNB_TRACE, "GfxStrapsInit Enter\n"); - - GnbLibPciIndirectRead ( - GNB_SBDFO | D0F0x60_ADDRESS, - D0F0x64_x1C_ADDRESS | IOC_WRITE_ENABLE, - AccessWidth32, - &D0F0x64_x1C.Value, - GnbLibGetHeader (Gfx) - ); - - GnbLibPciIndirectRead ( - GNB_SBDFO | D0F0x60_ADDRESS, - D0F0x64_x1D_ADDRESS | IOC_WRITE_ENABLE, - AccessWidth32, - &D0F0x64_x1D.Value, - GnbLibGetHeader (Gfx) - ); - - D0F0x64_x1C.Field.AudioNonlegacyDeviceTypeEn = 0x0; - D0F0x64_x1C.Field.F0NonlegacyDeviceTypeEn = 0x0; - - if (Gfx->GfxControllerMode == GfxControllerLegacyBridgeMode) { - D0F0x64_x1D.Field.IntGfxAsPcieEn = 0x0; - D0F0x64_x1C.Field.RcieEn = 0x0; - D0F0x64_x1C.Field.PcieDis = 0x1; - } else { - D0F0x64_x1D.Field.IntGfxAsPcieEn = 0x1; - D0F0x64_x1C.Field.RcieEn = 0x1; - D0F0x64_x1C.Field.PcieDis = 0x0; - //LN/ON A0 (MSI) - GnbLibPciRMW (MAKE_SBDFO (0, 0, 1, 0, 0x4), AccessS3SaveWidth32, 0xffffffff, BIT2, GnbLibGetHeader (Gfx)); - } - if (Gfx->ForceGfxMode == GfxEnableForceSecondary) { - D0F0x64_x1D.Field.VgaEn = 0x0; - } else { - D0F0x64_x1D.Field.VgaEn = 0x1; - } - D0F0x64_x1C.Field.AudioEn = Gfx->GnbHdAudio; - D0F0x64_x1C.Field.F0En = 0x1; - D0F0x64_x1C.Field.RegApSize = 0x1; - - if (Gfx->UmaInfo.UmaSize > 128 * 0x100000) { - D0F0x64_x1C.Field.MemApSize = 0x1; - } else if (Gfx->UmaInfo.UmaSize > 64 * 0x100000) { - D0F0x64_x1C.Field.MemApSize = 0x0; - } else if (Gfx->UmaInfo.UmaSize > 32 * 0x100000) { - D0F0x64_x1C.Field.MemApSize = 0x2; - } else { - D0F0x64_x1C.Field.MemApSize = 0x3; - } - GnbLibPciIndirectWrite ( - GNB_SBDFO | D0F0x60_ADDRESS, - D0F0x64_x1D_ADDRESS | IOC_WRITE_ENABLE, - AccessS3SaveWidth32, - &D0F0x64_x1D.Value, - GnbLibGetHeader (Gfx) - ); - - GnbLibPciIndirectWrite ( - GNB_SBDFO | D0F0x60_ADDRESS, - D0F0x64_x1C_ADDRESS | IOC_WRITE_ENABLE, - AccessS3SaveWidth32, - &D0F0x64_x1C.Value, - GnbLibGetHeader (Gfx) - ); - - D0F0x64_x1C.Field.WriteDis = 0x1; - - GnbLibPciIndirectWrite ( - GNB_SBDFO | D0F0x60_ADDRESS, - D0F0x64_x1C_ADDRESS | IOC_WRITE_ENABLE, - AccessS3SaveWidth32, - &D0F0x64_x1C.Value, - GnbLibGetHeader (Gfx) - ); - IDS_HDT_CONSOLE (GNB_TRACE, "GfxStrapsInit Exit\n"); - return AGESA_SUCCESS; -} - -/*----------------------------------------------------------------------------------------*/ -/** - * Disable integrated GFX controller - * - * - * @param[in] StdHeader Standard configuration header - */ - -VOID -GfxDisableController ( - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - FCRxFF30_0AE6_STRUCT FCRxFF30_0AE6; - D18F6x90_STRUCT D18F6x90; - IDS_HDT_CONSOLE (GNB_TRACE, "GfxDisableController Enter\n"); - GnbLibPciRMW ( - GNB_SBDFO | D0F0x7C_ADDRESS, - AccessS3SaveWidth32, - 0xffffffff, - 1 << D0F0x7C_ForceIntGFXDisable_OFFSET, - StdHeader - ); - - // With iGPU is disabled, Program D18F6x90[NbPs1GnbSlowIgn]=1 - GnbLibPciRead ( - MAKE_SBDFO ( 0, 0, 0x18, 6, D18F6x90_ADDRESS), - AccessWidth32, - &D18F6x90.Value, - StdHeader - ); - D18F6x90.Field.NbPs1GnbSlowIgn = 0x1; - GnbLibPciWrite ( - MAKE_SBDFO ( 0, 0, 0x18, 6, D18F6x90_ADDRESS), - AccessWidth32, - &D18F6x90.Value, - StdHeader - ); - - // With iGPU is disabled, Enable stutter without gmc power gating. - NbSmuSrbmRegisterRead (FCRxFF30_0AE6_ADDRESS, &FCRxFF30_0AE6.Value, StdHeader); - FCRxFF30_0AE6.Field.StctrlStutterEn = 0x1; - NbSmuSrbmRegisterWrite (FCRxFF30_0AE6_ADDRESS, &FCRxFF30_0AE6.Value, TRUE, StdHeader); - IDS_HDT_CONSOLE (GNB_TRACE, "GfxDisableController Exit\n"); -} - - - -/*----------------------------------------------------------------------------------------*/ -/** - * Request GFX boot up voltage - * - * - * @param[in] Gfx Pointer to global GFX configuration - * @retval AGESA_STATUS - */ - -AGESA_STATUS -GfxSetBootUpVoltage ( - IN GFX_PLATFORM_CONFIG *Gfx - ) -{ - GMMx770_STRUCT GMMx770; - GMMx774_STRUCT GMMx774; - IDS_HDT_CONSOLE (GNB_TRACE, "GfxSetBootUpVoltage Enter\n"); - - GMMx770.Value = GmmRegisterRead (GMMx770_ADDRESS, Gfx); - GMMx770.Field.VoltageChangeEn = 1; - GmmRegisterWrite (GMMx770_ADDRESS, GMMx770.Value, TRUE, Gfx); - GMMx770.Field.VoltageLevel = GnbLocateHighestVidIndex (GnbLibGetHeader (Gfx)); - GMMx770.Field.VoltageChangeReq = !GMMx770.Field.VoltageChangeReq; - GmmRegisterWrite (GMMx770_ADDRESS, GMMx770.Value, TRUE, Gfx); - do { - GMMx774.Value = GmmRegisterRead (GMMx774_ADDRESS, Gfx); - } while (GMMx774.Field.VoltageChangeAck != GMMx770.Field.VoltageChangeReq); - IDS_HDT_CONSOLE (GNB_TRACE, "GfxSetBootUpVoltage Exit\n"); - return AGESA_SUCCESS; -} - -/*----------------------------------------------------------------------------------------*/ -/** - * Set idle voltage mode for GFX - * - * - * @param[in] Gfx Pointer to global GFX configuration - */ - -VOID -GfxSetIdleVoltageMode ( - IN GFX_PLATFORM_CONFIG *Gfx - ) -{ -} diff --git a/src/vendorcode/amd/agesa/f12/Proc/GNB/Gfx/GfxStrapsInit.h b/src/vendorcode/amd/agesa/f12/Proc/GNB/Gfx/GfxStrapsInit.h deleted file mode 100644 index fdb686258a..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/GNB/Gfx/GfxStrapsInit.h +++ /dev/null @@ -1,77 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * Graphics controller BIF straps control services. - * - * - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: GNB - * @e \$Revision: 51087 $ @e \$Date: 2011-04-19 07:38:57 +0800 (Tue, 19 Apr 2011) $ - * - */ -/* -***************************************************************************** -* -* Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* *************************************************************************** -* -*/ - - -#ifndef _GFXSTRAPSINIT_H_ -#define _GFXSTRAPSINIT_H_ - -AGESA_STATUS -GfxInitSsid ( - IN GFX_PLATFORM_CONFIG *Gfx - ); - -AGESA_STATUS -GfxStrapsInit ( - IN GFX_PLATFORM_CONFIG *Gfx - ); - -VOID -GfxDisableController ( - IN AMD_CONFIG_PARAMS *StdHeader - ); - - -AGESA_STATUS -GfxSetBootUpVoltage ( - IN GFX_PLATFORM_CONFIG *Gfx - ); - -VOID -GfxSetIdleVoltageMode ( - IN GFX_PLATFORM_CONFIG *Gfx - ); - -#endif - diff --git a/src/vendorcode/amd/agesa/f12/Proc/GNB/Gfx/Makefile.inc b/src/vendorcode/amd/agesa/f12/Proc/GNB/Gfx/Makefile.inc deleted file mode 100644 index 3f0dfed1ae..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/GNB/Gfx/Makefile.inc +++ /dev/null @@ -1,9 +0,0 @@ -libagesa-y += GfxConfigData.c -libagesa-y += GfxGmcInit.c -libagesa-y += GfxInitAtEnvPost.c -libagesa-y += GfxInitAtMidPost.c -libagesa-y += GfxInitAtPost.c -libagesa-y += GfxIntegratedInfoTableInit.c -libagesa-y += GfxLib.c -libagesa-y += GfxRegisterAcc.c -libagesa-y += GfxStrapsInit.c diff --git a/src/vendorcode/amd/agesa/f12/Proc/GNB/GnbInitAtEarly.c b/src/vendorcode/amd/agesa/f12/Proc/GNB/GnbInitAtEarly.c deleted file mode 100644 index d43805fd2a..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/GNB/GnbInitAtEarly.c +++ /dev/null @@ -1,113 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * GNB early init interface - * - * - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: GNB - * @e \$Revision: 45357 $ @e \$Date: 2011-01-15 07:31:25 +0800 (Sat, 15 Jan 2011) $ - * - */ -/* -***************************************************************************** -* -* Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* *************************************************************************** -* -*/ - -/*---------------------------------------------------------------------------------------- - * M O D U L E S U S E D - *---------------------------------------------------------------------------------------- - */ -#include "AGESA.h" -#include "Ids.h" -#include "Gnb.h" -#include "OptionGnb.h" -#include "GnbLibFeatures.h" -#include "GnbInterface.h" -#include "Filecode.h" -#define FILECODE PROC_GNB_GNBINITATEARLY_FILECODE - -/*---------------------------------------------------------------------------------------- - * D E F I N I T I O N S A N D M A C R O S - *---------------------------------------------------------------------------------------- - */ -extern OPTION_GNB_CONFIGURATION GnbEarlyFeatureTable[]; -extern OPTION_GNB_CONFIGURATION GnbEarlierFeatureTable[]; -/*---------------------------------------------------------------------------------------- - * T Y P E D E F S A N D S T R U C T U R E S - *---------------------------------------------------------------------------------------- - */ - - -/*---------------------------------------------------------------------------------------- - * P R O T O T Y P E S O F L O C A L F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ - -/*----------------------------------------------------------------------------------------*/ -/** - * Init GNB at Early - * - * - * - * @param[in,out] EarlyParamsPtr Pointer to early configuration params. - * @retval Initialization status. - */ -AGESA_STATUS -GnbInitAtEarly ( - IN OUT AMD_EARLY_PARAMS *EarlyParamsPtr - ) -{ - AGESA_STATUS Status; - Status = GnbLibDispatchFeatures (&GnbEarlyFeatureTable[0], &EarlyParamsPtr->StdHeader); - return Status; -} - - -/*----------------------------------------------------------------------------------------*/ -/** - * Init GNB at Early before CPU - * - * - * - * @param[in,out] EarlyParamsPtr Pointer to early configuration params. - * @retval Initialization status. - */ -AGESA_STATUS -GnbInitAtEarlier ( - IN OUT AMD_EARLY_PARAMS *EarlyParamsPtr - ) -{ - AGESA_STATUS Status; - Status = GnbLibDispatchFeatures (&GnbEarlierFeatureTable[0], &EarlyParamsPtr->StdHeader); - return Status; -} diff --git a/src/vendorcode/amd/agesa/f12/Proc/GNB/GnbInitAtEnv.c b/src/vendorcode/amd/agesa/f12/Proc/GNB/GnbInitAtEnv.c deleted file mode 100644 index fc4e41abaf..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/GNB/GnbInitAtEnv.c +++ /dev/null @@ -1,125 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * GNB env init interface - * - * - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: GNB - * @e \$Revision: 47190 $ @e \$Date: 2011-02-16 14:25:13 +0800 (Wed, 16 Feb 2011) $ - * - */ -/* -***************************************************************************** -* -* Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* *************************************************************************** -* -*/ - -/*---------------------------------------------------------------------------------------- - * M O D U L E S U S E D - *---------------------------------------------------------------------------------------- - */ -#include "AGESA.h" -#include "Gnb.h" -#include "OptionGnb.h" -#include "GnbLibFeatures.h" -#include "GnbInterface.h" -#include "Filecode.h" -#define FILECODE PROC_GNB_GNBINITATENV_FILECODE -/*---------------------------------------------------------------------------------------- - * D E F I N I T I O N S A N D M A C R O S - *---------------------------------------------------------------------------------------- - */ -extern OPTION_GNB_CONFIGURATION GnbEnvFeatureTable[]; -extern BUILD_OPT_CFG UserOptions; -/*---------------------------------------------------------------------------------------- - * T Y P E D E F S A N D S T R U C T U R E S - *---------------------------------------------------------------------------------------- - */ - - -/*---------------------------------------------------------------------------------------- - * P R O T O T Y P E S O F L O C A L F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ - -/*----------------------------------------------------------------------------------------*/ -/** - * Default constructor of GNB configuration at Env - * - * - * - * @param[in] GnbEnvConfigPtr Pointer to gnb env configuration params. - * @param[in] EnvParamsPtr Pointer to env configuration params. - */ -VOID -GnbInitDataStructAtEnvDef ( - IN OUT GNB_ENV_CONFIGURATION *GnbEnvConfigPtr, - IN AMD_ENV_PARAMS *EnvParamsPtr - ) -{ - GnbEnvConfigPtr->Gnb3dStereoPinIndex = UserOptions.CfgGnb3dStereoPinIndex; - GnbEnvConfigPtr->IommuSupport = UserOptions.CfgIommuSupport; - GnbEnvConfigPtr->LvdsSpreadSpectrum = UserOptions.CfgLvdsSpreadSpectrum; - GnbEnvConfigPtr->LvdsSpreadSpectrumRate = UserOptions.CfgLvdsSpreadSpectrumRate; - GnbEnvConfigPtr->LvdsPowerOnSeqDigonToDe = UserOptions.CfgLvdsPowerOnSeqDigonToDe; - GnbEnvConfigPtr->LvdsPowerOnSeqDeToVaryBl = UserOptions.CfgLvdsPowerOnSeqDeToVaryBl; - GnbEnvConfigPtr->LvdsPowerOnSeqDeToDigon = UserOptions.CfgLvdsPowerOnSeqDeToDigon; - GnbEnvConfigPtr->LvdsPowerOnSeqVaryBlToDe = UserOptions.CfgLvdsPowerOnSeqVaryBlToDe; - GnbEnvConfigPtr->LvdsPowerOnSeqOnToOffDelay = UserOptions.CfgLvdsPowerOnSeqOnToOffDelay; - GnbEnvConfigPtr->LvdsPowerOnSeqVaryBlToBlon = UserOptions.CfgLvdsPowerOnSeqVaryBlToBlon; - GnbEnvConfigPtr->LvdsPowerOnSeqBlonToVaryBl = UserOptions.CfgLvdsPowerOnSeqBlonToVaryBl; - GnbEnvConfigPtr->LvdsMaxPixelClockFreq = UserOptions.CfgLvdsMaxPixelClockFreq; - GnbEnvConfigPtr->LcdBitDepthControlValue = UserOptions.CfgLcdBitDepthControlValue; - GnbEnvConfigPtr->Lvds24bbpPanelMode = UserOptions.CfgLvds24bbpPanelMode; - GnbEnvConfigPtr->PcieRefClkSpreadSpectrum = UserOptions.CfgPcieRefClkSpreadSpectrum; - -} - -/*----------------------------------------------------------------------------------------*/ -/** - * Init GNB at Env - * - * - * - * @param[in] EnvParamsPtr Pointer to env configuration params. - * @retval Initialization status. - */ - -AGESA_STATUS -GnbInitAtEnv ( - IN AMD_ENV_PARAMS *EnvParamsPtr - ) -{ - AGESA_STATUS Status; - Status = GnbLibDispatchFeatures (&GnbEnvFeatureTable[0], &EnvParamsPtr->StdHeader); - return Status; -} \ No newline at end of file diff --git a/src/vendorcode/amd/agesa/f12/Proc/GNB/GnbInitAtLate.c b/src/vendorcode/amd/agesa/f12/Proc/GNB/GnbInitAtLate.c deleted file mode 100644 index 9b03303336..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/GNB/GnbInitAtLate.c +++ /dev/null @@ -1,93 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * GNB late init interface - * - * - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: GNB - * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $ - * - */ -/* -***************************************************************************** -* -* Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* *************************************************************************** -* -*/ - -/*---------------------------------------------------------------------------------------- - * M O D U L E S U S E D - *---------------------------------------------------------------------------------------- - */ -#include "AGESA.h" -#include "Gnb.h" -#include "OptionGnb.h" -#include "GnbLibFeatures.h" -#include "GnbInterface.h" -#include "Filecode.h" -#define FILECODE PROC_GNB_GNBINITATLATE_FILECODE -/*---------------------------------------------------------------------------------------- - * D E F I N I T I O N S A N D M A C R O S - *---------------------------------------------------------------------------------------- - */ - -extern OPTION_GNB_CONFIGURATION GnbLateFeatureTable[]; -/*---------------------------------------------------------------------------------------- - * T Y P E D E F S A N D S T R U C T U R E S - *---------------------------------------------------------------------------------------- - */ - - -/*---------------------------------------------------------------------------------------- - * P R O T O T Y P E S O F L O C A L F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ - - -/*----------------------------------------------------------------------------------------*/ -/** - * Init GNB at Late post - * - * - * - * @param[in,out] LateParamsPtr Pointer to late configuration params. - * @retval Initialization status. - */ - -AGESA_STATUS -GnbInitAtLate ( - IN OUT AMD_LATE_PARAMS *LateParamsPtr - ) -{ - AGESA_STATUS Status; - Status = GnbLibDispatchFeatures (&GnbLateFeatureTable[0], &LateParamsPtr->StdHeader); - return Status; -} \ No newline at end of file diff --git a/src/vendorcode/amd/agesa/f12/Proc/GNB/GnbInitAtMid.c b/src/vendorcode/amd/agesa/f12/Proc/GNB/GnbInitAtMid.c deleted file mode 100644 index 7a5fb87383..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/GNB/GnbInitAtMid.c +++ /dev/null @@ -1,93 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * GNB mid init interface - * - * - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: GNB - * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $ - * - */ -/* -***************************************************************************** -* -* Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* *************************************************************************** -* -*/ - -/*---------------------------------------------------------------------------------------- - * M O D U L E S U S E D - *---------------------------------------------------------------------------------------- - */ -#include "AGESA.h" -#include "Gnb.h" -#include "OptionGnb.h" -#include "GnbLibFeatures.h" -#include "GnbInterface.h" -#include "Filecode.h" -#define FILECODE PROC_GNB_GNBINITATMID_FILECODE -/*---------------------------------------------------------------------------------------- - * D E F I N I T I O N S A N D M A C R O S - *---------------------------------------------------------------------------------------- - */ -extern OPTION_GNB_CONFIGURATION GnbMidFeatureTable[]; - -/*---------------------------------------------------------------------------------------- - * T Y P E D E F S A N D S T R U C T U R E S - *---------------------------------------------------------------------------------------- - */ - - -/*---------------------------------------------------------------------------------------- - * P R O T O T Y P E S O F L O C A L F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ - - -/*----------------------------------------------------------------------------------------*/ -/** - * Init GNB at Mid post - * - * - * - * @param[in,out] MidParamsPtr Pointer to mid configuration params. - * @retval Initialization status. - */ - -AGESA_STATUS -GnbInitAtMid ( - IN OUT AMD_MID_PARAMS *MidParamsPtr - ) -{ - AGESA_STATUS Status; - Status = GnbLibDispatchFeatures (&GnbMidFeatureTable[0], &MidParamsPtr->StdHeader); - return Status; -} \ No newline at end of file diff --git a/src/vendorcode/amd/agesa/f12/Proc/GNB/GnbInitAtPost.c b/src/vendorcode/amd/agesa/f12/Proc/GNB/GnbInitAtPost.c deleted file mode 100644 index c97f746482..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/GNB/GnbInitAtPost.c +++ /dev/null @@ -1,115 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * GNB POST init interface - * - * - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: GNB - * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $ - * - */ -/* -***************************************************************************** -* -* Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* *************************************************************************** -* -*/ - -/*---------------------------------------------------------------------------------------- - * M O D U L E S U S E D - *---------------------------------------------------------------------------------------- - */ -#include "AGESA.h" -#include "Gnb.h" -#include "OptionGnb.h" -#include "Ids.h" -#include "GnbLibFeatures.h" -#include "GnbInterface.h" -#include "Filecode.h" -#define FILECODE PROC_GNB_GNBINITATPOST_FILECODE -/*---------------------------------------------------------------------------------------- - * D E F I N I T I O N S A N D M A C R O S - *---------------------------------------------------------------------------------------- - */ -extern OPTION_GNB_CONFIGURATION GnbPostFeatureTable[]; -extern OPTION_GNB_CONFIGURATION GnbPostAfterDramFeatureTable[]; - -/*---------------------------------------------------------------------------------------- - * T Y P E D E F S A N D S T R U C T U R E S - *---------------------------------------------------------------------------------------- - */ - - -/*---------------------------------------------------------------------------------------- - * P R O T O T Y P E S O F L O C A L F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ - -/*----------------------------------------------------------------------------------------*/ -/** - * Init GNB at Post - * - * - * - * @param[in] PostParamsPtr Pointer to post configuration parameters - * @retval Initialization status. - */ - -AGESA_STATUS -GnbInitAtPost ( - IN OUT AMD_POST_PARAMS *PostParamsPtr - ) -{ - AGESA_STATUS Status; - Status = GnbLibDispatchFeatures (&GnbPostFeatureTable[0], &PostParamsPtr->StdHeader); - return Status; -} - - -/*----------------------------------------------------------------------------------------*/ -/** - * Init GNB at Post after DRAM init - * - * - * - * @param[in] PostParamsPtr Pointer to post configuration parameters - * @retval Initialization status. - */ - -AGESA_STATUS -GnbInitAtPostAfterDram ( - IN OUT AMD_POST_PARAMS *PostParamsPtr - ) -{ - AGESA_STATUS Status; - Status = GnbLibDispatchFeatures (&GnbPostAfterDramFeatureTable[0], &PostParamsPtr->StdHeader); - return Status; -} diff --git a/src/vendorcode/amd/agesa/f12/Proc/GNB/GnbInitAtReset.c b/src/vendorcode/amd/agesa/f12/Proc/GNB/GnbInitAtReset.c deleted file mode 100644 index 9bf62f56e7..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/GNB/GnbInitAtReset.c +++ /dev/null @@ -1,90 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * GNB reset init interface - * - * - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: GNB - * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $ - * - */ -/* -***************************************************************************** -* -* Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* *************************************************************************** -* -*/ - -/*---------------------------------------------------------------------------------------- - * M O D U L E S U S E D - *---------------------------------------------------------------------------------------- - */ -#include "AGESA.h" -#include "Gnb.h" -#include "GnbInterface.h" -#include "Filecode.h" -#define FILECODE PROC_GNB_GNBINITATRESET_FILECODE -/*---------------------------------------------------------------------------------------- - * D E F I N I T I O N S A N D M A C R O S - *---------------------------------------------------------------------------------------- - */ - - -/*---------------------------------------------------------------------------------------- - * T Y P E D E F S A N D S T R U C T U R E S - *---------------------------------------------------------------------------------------- - */ - - -/*---------------------------------------------------------------------------------------- - * P R O T O T Y P E S O F L O C A L F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ -/*----------------------------------------------------------------------------------------*/ -/** - * Init GNB at Reset - * - * - * - * @param[in] StdHeader Standard configuration header - * @retval AGESA_STATUS - */ - -AGESA_STATUS -GnbInitAtReset ( - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - AGESA_STATUS Status; - Status = AGESA_SUCCESS; - - return Status; -} \ No newline at end of file diff --git a/src/vendorcode/amd/agesa/f12/Proc/GNB/GnbPage.h b/src/vendorcode/amd/agesa/f12/Proc/GNB/GnbPage.h deleted file mode 100644 index 28b046d23f..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/GNB/GnbPage.h +++ /dev/null @@ -1,1856 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * Create outline and references for GNB Component mainpage documentation. - * - * Design guides, maintenance guides, and general documentation, are - * collected using this file onto the documentation mainpage. - * This file contains doxygen comment blocks, only. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: Documentation - * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $ - * - */ -/* - ****************************************************************************** - * - * Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - ****************************************************************************** - */ - -/** - * @page F12PcieLaneDescription Family 0x12 PCIe/DDI Lanes - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - *
Lane IDLane groupPin
0 SB P_SB_RX[P/N]/TX[P/N][0]
1 SB P_SB_RX[P/N]/TX[P/N][1]
2 SB P_SB_RX[P/N]/TX[P/N][2]
3 SB P_SB_RX[P/N]/TX[P/N][3]
4 GPPP_GPP_RX[P/N]/TX[P/N][0]
5 GPPP_GPP_RX[P/N]/TX[P/N][1]
6 GPPP_GPP_RX[P/N]/TX[P/N][2]
7 GPPP_GPP_RX[P/N]/TX[P/N][3]
8 GFXP_GFX_RX[P/N]/TX[P/N][0]
9 GFXP_GFX_RX[P/N]/TX[P/N][1]
10GFXP_GFX_RX[P/N]/TX[P/N][2]
11GFXP_GFX_RX[P/N]/TX[P/N][3]
12GFXP_GFX_RX[P/N]/TX[P/N][4]
13GFXP_GFX_RX[P/N]/TX[P/N][5]
14GFXP_GFX_RX[P/N]/TX[P/N][6]
15GFXP_GFX_RX[P/N]/TX[P/N][7]
16GFXP_GFX_RX[P/N]/TX[P/N][8]
17GFXP_GFX_RX[P/N]/TX[P/N][9]
18GFXP_GFX_RX[P/N]/TX[P/N][10]
19GFXP_GFX_RX[P/N]/TX[P/N][11]
20GFXP_GFX_RX[P/N]/TX[P/N][12]
21GFXP_GFX_RX[P/N]/TX[P/N][13]
22GFXP_GFX_RX[P/N]/TX[P/N][14]
23GFXP_GFX_RX[P/N]/TX[P/N][15]
24DDIDP1_TXP/N[0]
25DDIDP1_TXP/N[1]
26DDIDP1_TXP/N[2]
27DDIDP1_TXP/N[3]
28DDIDP0_TXP/N[0]
29DDIDP0_TXP/N[1]
30DDIDP0_TXP/N[2]
31DDIDP0_TXP/N[3]
- * - */ - - -/** - * @page F14PcieLaneDescription Family 0x14 PCIe/DDI Lanes - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - *
Lane IDLane groupPin
0 SB P_SB_RX[P/N]/TX[P/N][0]
1 SB P_SB_RX[P/N]/TX[P/N][1]
2 SB P_SB_RX[P/N]/TX[P/N][2]
3 SB P_SB_RX[P/N]/TX[P/N][3]
4 GPPP_GPP_RX[P/N]/TX[P/N][0]
5 GPPP_GPP_RX[P/N]/TX[P/N][1]
6 GPPP_GPP_RX[P/N]/TX[P/N][2]
7 GPPP_GPP_RX[P/N]/TX[P/N][3]
8DDIDP0_TXP/N[0]
9DDIDP0_TXP/N[1]
10DDIDP0_TXP/N[2]
11DDIDP0_TXP/N[3]
12DDIDP1_TXP/N[0]
13DDIDP1_TXP/N[1]
14DDIDP1_TXP/N[2]
15DDIDP1_TXP/N[3]
- * - */ - - -/** - * @page F12DualLinkDviDescription Family 0x12 Dual Link DVI connector description - * Examples of various Dual Link DVI descriptors. - * @code - * // Dual Link DVI on dedicated display lanes. DP1_TXP/N[0]..DP1_TXP/N[3] - master, DP0_TXP/N[0]..DP0_TXP/N[3] - slave. - * PCIe_PORT_DESCRIPTOR DdiList [] = { - * { - * DESCRIPTOR_TERMINATE_LIST, //Descriptor flags - * PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 24, 32), - * PCIE_DDI_DATA_INITIALIZER (ConnectorTypeDualLinkDvi, Aux1, Hdp1, 0) - * } - * } - * // Dual Link DVI on dedicated display lanes. DP0_TXP/N[0]..DP0_TXP/N[3] - master, DP1_TXP/N[0]..DP1_TXP/N[3] - slave. - * PCIe_PORT_DESCRIPTOR DdiList [] = { - * { - * DESCRIPTOR_TERMINATE_LIST, //Descriptor flags - * PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 32, 24), - * PCIE_DDI_DATA_INITIALIZER (ConnectorTypeDualLinkDvi, Aux1, Hdp1, 0) - * } - * } - * // Dual Link DVI on PCIe lanes. P_GFX_TXP/N[0]..P_GFX_TXP/N[3] - master, P_GFX_TXP/N[4]..P_GFX_TXP/N[7] - slave. - * PCIe_PORT_DESCRIPTOR DdiList [] = { - * { - * DESCRIPTOR_TERMINATE_LIST, //Descriptor flags - * PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 8, 15), - * PCIE_DDI_DATA_INITIALIZER (ConnectorTypeDualLinkDvi, Aux1, Hdp1, 0) - * } - * } - * // Dual Link DVI on PCIe lanes. P_GFX_TXP/N[7]..P_GFX_TXP/N[4] - master, P_GFX_TXP/N[0]..P_GFX_TXP/N[3] - slave. - * PCIe_PORT_DESCRIPTOR DdiList [] = { - * { - * DESCRIPTOR_TERMINATE_LIST, //Descriptor flags - * PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 15, 8), - * PCIE_DDI_DATA_INITIALIZER (ConnectorTypeDualLinkDvi, Aux1, Hdp1, 0) - * } - * } - * // Dual Link DVI on PCIe lanes. P_GFX_TXP/N[8]..P_GFX_TXP/N[11] - master, P_GFX_TXP/N[12]..P_GFX_TXP/N[15] - slave. - * PCIe_PORT_DESCRIPTOR DdiList [] = { - * { - * DESCRIPTOR_TERMINATE_LIST, //Descriptor flags - * PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 16, 23), - * PCIE_DDI_DATA_INITIALIZER (ConnectorTypeDualLinkDvi, Aux1, Hdp1, 0) - * } - * } - * // Dual Link DVI on PCIe lanes. P_GFX_TXP/N[12]..P_GFX_TXP/N[15] - master, P_GFX_TXP/N[8]..P_GFX_TXP/N[11] - slave. - * PCIe_PORT_DESCRIPTOR DdiList [] = { - * { - * DESCRIPTOR_TERMINATE_LIST, //Descriptor flags - * PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 23, 16), - * PCIE_DDI_DATA_INITIALIZER (ConnectorTypeDualLinkDvi, Aux1, Hdp1, 0) - * } - * } - * @endcode - */ - - -/** - * @page gnbmain GNB Component Documentation - * - * Additional documentation for the GNB component consists of - * - * - Maintenance Guides: - * - @subpage F12PcieLaneDescription "Family 0x12 PCIe/DDI Lane description table" - * - @subpage F14PcieLaneDescription "Family 0x14 PCIe/DDI Lane description table" - * - @subpage F12LaneConfigurations "Family 0x12 PCIe port/DDI link configurations" - * - @subpage F14LaneConfigurations "Family 0x14 PCIe port/DDI link configurations" - * - @subpage F12DualLinkDviDescription "Family 0x12 Dual Link DVI connector description" - * - add here >>> - * - Design Guides: - * - add here >>> - * - */ - - -/** - * @page F12LaneConfigurations Family 0x12 PCIe port/DDI link configurations - * - *
- * - *

PCIe port configurations - *for lanes 8 through 23.

- * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - *
- *

Configuration

- * 		- *

PCIe Port Device Number

- * 		- *

Start Lane (Start Lane in reverse - * configuration)

- * 		- *

End Line (End lane in reverse - * configuration)

- *
- *

Config A

- * 		- *

2

- * 		- *

8(23)

- * 		- *

23(8)

- *
- *

Config B

- * 		- *

2

- * 		- *

8(15)

- * 		- *

15(8)

- *
- *

8(11)

- * 		- *

11(8)

- *
- *

8(9)

- * 		- *

9(8)

- *
- *

10(11)

- * 		- *

11(10)

- *
- *

12(15)

- * 		- *

15(12)

- *
- *

12(13)

- * 		- *

13(12)

- *
- *

14(15)

- * 		- *

15(14)

- *
- *

3

- * 		- *

16(23)

- * 		- *

23(16)

- *
- *

16(19)

- * 		- *

19(16)

- *
- *

16(17)

- * 		- *

17(16)

- *
- *

18(19)

- * 		- *

19(18)

- *
- *

20(23)

- * 		- *

23(20)

- *
- *

20(21)

- * 		- *

21(20)

- *
- *

22(23)

- * 		- *

23(22)

- *
- * - *

 

- * - *

PCIe port configurations - *for lanes 4 through 7.

- * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - *
- *

Configuration

- * 		- *

PCIe Port Device Number

- * 		- *

Start Lane (Start Lane in reverse - * configuration)

- * 		- *

End Line (End lane in reverse - * configuration)

- *
- *

Config A

- * 		- *

4

- * 		- *

4(7)

- * 		- *

7(4)

- *
- *

 

- * 		- *

 

- *
- *

Config B

- * 		- *

4

- * 		- *

4(5)

- * 		- *

5(4)

- *
- *

4

- * 		- *

4

- *
- *

5

- * 		- *

5

- *
- *

5

- * 		- *

6(7)

- * 		- *

7(6)

- *
- *

6

- * 		- *

6

- *
- *

7

- * 		- *

7

- *
- *

Config C

- * 		- *

4

- * 		- *

4(5)

- * 		- *

5(4)

- *
- *

4

- * 		- *

4

- *
- *

5

- * 		- *

5

- *
- *

5

- * 		- *

6

- * 		- *

6

- *
- *

6

- * 		- *

7

- * 		- *

7

- *
- *

Config D

- * 		- *

4

- * 		- *

4

- * 		- *

4

- *
- *

5

- * 		- *

5

- * 		- *

5

- *
- *

6

- * 		- *

6

- * 		- *

6

- *
- *

7

- * 		- *

7

- * 		- *

7

- *
- * - *

 

- *

 

- * - *

DDI link configurations - *for lanes 24 through 31.

- * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - *
- *

Configuration

- * 		- *

Connector type

- * 		- *

Start Lane (Start Lane in reverse - * configuration)

- * 		- *

End Line (End lane in reverse - * configuration)

- *
- *

Config A

- * 		- *

Dual Link DVI-D

- * 		- *

24(31)

- * 		- *

31(24)

- *
- *

Config B

- * 		- *

HDMI

- *

Single Link DVI-D

- *

DP

- *

eDP

- *

Travis DP-to-CRT

- *

Travis DP-to-LVDS

- *

Hudson2 DP-to-CRT

- * 		- *

24

- * 		- *

27

- *
- *

HDMI

- *

Single Link DVI-D

- *

DP

- *

eDP

- *

Travis DP-to-CRT

- *

Travis DP-to-LVDS

- *

Hudson2 DP-to-CRT

- * 		- *

28

- * 		- *

31

- *
- * - *

 

- * - *

DDI link configurations - *for lanes 8 through 23.

- * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - *
- *

Configuration

- * 		- *

Connector type

- * 		- *

Start Lane (Start Lane in reverse - * configuration)

- * 		- *

End Line (End lane in reverse - * configuration)

- *
- *

Config A

- * 		- *

Dual Link DVI-D

- * 		- *

24(31)

- * 		- *

31(24)

- *
- *

Config B

- * 		- *

Dual Link DVI-D

- * 		- *

8(15)

- * 		- *

15(8)

- *
- *

Dual Link DVI-D

- * 		- *

16(23)

- * 		- *

23(16)

- *
- *

Config C

- * 		- *

Dual Link DVI-D

- * 		- *

8(15)

- * 		- *

15(8)

- *
- *

HDMI

- *

Single Link DVI-D

- *

DP

- *

eDP

- *

Travis DP-to-CRT

- *

Travis DP-to-LVDS

- *

Hudson2 DP-to-CRT

- * 		- *

16

- * 		- *

19

- *
- *

HDMI

- *

Single Link DVI-D

- *

DP

- *

eDP

- *

Travis DP-to-CRT

- *

Travis DP-to-LVDS

- *

Hudson2 DP-to-CRT

- * 		- *

20

- * 		- *

23

- *
- *

Config D

- * 		- *

HDMI

- *

Single Link DVI-D

- *

DP

- *

eDP

- *

Travis DP-to-CRT

- *

Travis DP-to-LVDS

- *

Hudson2 DP-to-CRT

- * 		- *

8

- * 		- *

11

- *
- *

HDMI

- *

Single Link DVI-D

- *

DP

- *

eDP

- *

Travis DP-to-CRT

- *

Travis DP-to-LVDS

- *

Hudson2 DP-to-CRT

- * 		- *

12

- * 		- *

15

- *
- *

Dual Link DVI-D

- * 		- *

16(23)

- * 		- *

23(16)

- *
- *

Config E

- * 		- *

HDMI

- *

Single Link DVI-D

- *

DP

- *

eDP

- *

Travis DP-to-CRT

- *

Travis DP-to-LVDS

- *

Hudson2 DP-to-CRT

- * 		- *

8

- * 		- *

11

- *
- *

HDMI

- *

Single Link DVI-D

- *

DP

- *

eDP

- *

Travis DP-to-CRT

- *

Travis DP-to-LVDS

- *

Hudson2 DP-to-CRT

- * 		- *

12

- * 		- *

15

- *
- *

HDMI

- *

Single Link DVI-D

- *

DP

- *

eDP

- *

Travis DP-to-CRT

- *

Travis DP-to-LVDS

- *

Hudson2 DP-to-CRT

- * 		- *

16

- * 		- *

19

- *
- *

HDMI

- *

Single Link DVI-D

- *

DP

- *

eDP

- *

Travis DP-to-CRT

- *

Travis DP-to-LVDS

- *

Hudson2 DP-to-CRT

- * 		- *

20

- * 		- *

23

- *
- *
- */ - -/** - * @page F14LaneConfigurations Family 0x14 PCIe port/DDI link configurations - * - *
- * - *

PCIe port - *configurations for lanes 4 through 7.

- * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - *
- *

Configuration

- * 		- *

PCIe Port Device Number

- * 		- *

Start Lane (Start Lane in reverse - * configuration)

- * 		- *

End Line (End lane in reverse - * configuration)

- *
- *

Config A

- * 		- *

4

- * 		- *

4(7)

- * 		- *

7(4)

- *
- *

 

- * 		- *

 

- *
- *

Config B

- * 		- *

4

- * 		- *

4(5)

- * 		- *

5(4)

- *
- *

4

- * 		- *

4

- *
- *

5

- * 		- *

5

- *
- *

5

- * 		- *

6(7)

- * 		- *

7(6)

- *
- *

6

- * 		- *

6

- *
- *

7

- * 		- *

7

- *
- *

Config C

- * 		- *

4

- * 		- *

4(5)

- * 		- *

5(4)

- *
- *

4

- * 		- *

4

- *
- *

5

- * 		- *

5

- *
- *

5

- * 		- *

6

- * 		- *

6

- *
- *

6

- * 		- *

7

- * 		- *

7

- *
- *

Config D

- * 		- *

4

- * 		- *

4

- * 		- *

4

- *
- *

5

- * 		- *

5

- * 		- *

5

- *
- *

6

- * 		- *

6

- * 		- *

6

- *
- *

7

- * 		- *

7

- * 		- *

7

- *
- * - *

 

- *

 

- * - *

CRT/DDI link - *configurations for lanes 8 through 19.

- * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - *
- *

Configuration

- * 		- *

Connector type

- * 		- *

Start Lane (Start Lane in reverse - * configuration)

- * 		- *

End Line (End lane in reverse - * configuration)

- *
- *

Config A

- * 		- *

HDMI

- *

Single Link DVI-D

- *

Single Link DVI-I*

- *

DP

- *

eDP

- *

Travis DP-to-CRT

- *

Travis DP-to-LVDS

- *

Hudson2 DP-to-CRT

- * 		- *

8

- * 		- *

11

- *
- *

HDMI

- *

Single Link DVI-D

- *

Single Link DVI-I*

- *

DP

- *

eDP

- *

Travis DP-to-CRT

- *

Travis DP-to-LVDS

- *

Hudson2 DP-to-CRT

- * 		- *

12

- * 		- *

15

- *
- *

CRT*

- * 		- *

16

- * 		- *

19

- *
- *

* - Only one connector of this type can exist in overall configuration

- *
- *
- */ - diff --git a/src/vendorcode/amd/agesa/f12/Proc/GNB/Makefile.inc b/src/vendorcode/amd/agesa/f12/Proc/GNB/Makefile.inc deleted file mode 100644 index d58d96c2b0..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/GNB/Makefile.inc +++ /dev/null @@ -1,6 +0,0 @@ -libagesa-y += GnbInitAtEarly.c -libagesa-y += GnbInitAtEnv.c -libagesa-y += GnbInitAtLate.c -libagesa-y += GnbInitAtMid.c -libagesa-y += GnbInitAtPost.c -libagesa-y += GnbInitAtReset.c diff --git a/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbCableSafe/GnbCableSafe.c b/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbCableSafe/GnbCableSafe.c deleted file mode 100644 index 249768bc58..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbCableSafe/GnbCableSafe.c +++ /dev/null @@ -1,249 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * Cable safe module - * - * - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: GNB - * @e \$Revision: 48452 $ @e \$Date: 2011-03-09 12:50:44 +0800 (Wed, 09 Mar 2011) $ - * - */ -/* -***************************************************************************** -* -* Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* *************************************************************************** -* -*/ - -/*---------------------------------------------------------------------------------------- - * M O D U L E S U S E D - *---------------------------------------------------------------------------------------- - */ -#include "AGESA.h" -#include "amdlib.h" -#include "Ids.h" -#include "Gnb.h" -#include "GnbPcie.h" -#include "OptionGnb.h" -#include "GnbPcieConfig.h" -#include "GnbCommonLib.h" -#include "GnbGfxInitLibV1.h" -#include "GnbRegistersLN.h" -#include "cpuFamilyTranslation.h" -#include "NbSmuLib.h" -#include "GnbCableSafeDefs.h" -#include "Filecode.h" -#define FILECODE PROC_GNB_MODULES_GNBCABLESAFE_GNBCABLESAFE_FILECODE - -/*---------------------------------------------------------------------------------------- - * D E F I N I T I O N S A N D M A C R O S - *---------------------------------------------------------------------------------------- - */ - -extern GNB_BUILD_OPTIONS GnbBuildOptions; - -/*---------------------------------------------------------------------------------------- - * T Y P E D E F S A N D S T R U C T U R E S - *---------------------------------------------------------------------------------------- - */ - - -UINT8 HdpIndexTranslationTable [] = { - 3, 2, 1, 0, 7, 6 -}; - -UINT8 AuxIndexTranslationTable [] = { - 5, 4, 11, 10, 9, 8 -}; - -UINT8 AuxDataTranslationTable [] = { - 0x10, 0x20, 0x40, 0x01, 0x02, 0x04 -}; - -/*---------------------------------------------------------------------------------------- - * P R O T O T Y P E S O F L O C A L F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ -AGESA_STATUS -GnbCableSafeEntry ( - IN AMD_CONFIG_PARAMS *StdHeader - ); - -VOID -STATIC -GnbCableSafeGetConnectorInfoArrayCallback ( - IN PCIe_ENGINE_CONFIG *Engine, - IN OUT VOID *Buffer, - IN PCIe_PLATFORM_CONFIG *Pcie - ); - -BOOLEAN -GnbCableSafeIsSupported ( - IN AMD_CONFIG_PARAMS *StdHeader - ); - -/*----------------------------------------------------------------------------------------*/ -/** - * Cable Safe module entry - * - * - * - * @param[in] StdHeader Standard configuration header - * @retval AGESA_STATUS - */ - -AGESA_STATUS -GnbCableSafeEntry ( - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - AGESA_STATUS Status; - PCIe_PLATFORM_CONFIG *Pcie; - PCIe_ENGINE_CONFIG *DdiEngineList [MaxHdp]; - UINT8 HdpIndex; - UINT8 CurrentIndex; - GNB_CABLE_SAFE_DATA CableSafeData; - BOOLEAN ForceCableSafeOff; - IDS_HDT_CONSOLE (GNB_TRACE, "GnbCableSafeEntry Enter\n"); - Status = AGESA_SUCCESS; - ForceCableSafeOff = GnbBuildOptions.CfgForceCableSafeOff; - IDS_OPTION_HOOK (IDS_GNB_FORCE_CABLESAFE, &ForceCableSafeOff, StdHeader); - if (GnbCableSafeIsSupported (StdHeader)) { - if (PcieLocateConfigurationData (StdHeader, &Pcie) == AGESA_SUCCESS) { - for (HdpIndex = 0; HdpIndex < MaxHdp; HdpIndex++) { - DdiEngineList[HdpIndex] = NULL; - } - LibAmdMemFill (&CableSafeData, 0, sizeof (CableSafeData), StdHeader); - if (!ForceCableSafeOff) { - PcieConfigRunProcForAllEngines ( - DESCRIPTOR_ALLOCATED | DESCRIPTOR_DDI_ENGINE, - GnbCableSafeGetConnectorInfoArrayCallback, - DdiEngineList, - Pcie - ); - CurrentIndex = 0; - for (HdpIndex = 0; HdpIndex < MaxHdp; HdpIndex++) { - if (DdiEngineList [HdpIndex] != NULL) { - CableSafeData.Data[HdpIndexTranslationTable[CurrentIndex]] = HdpIndex + 1; - CableSafeData.Data[AuxIndexTranslationTable[CurrentIndex]] = AuxDataTranslationTable [(DdiEngineList [HdpIndex])->Type.Ddi.DdiData.AuxIndex]; - IDS_HDT_CONSOLE (NB_MISC, " Index [%d] HDP 0x%02x AUX 0x%02x\n", CurrentIndex, HdpIndex, (DdiEngineList [HdpIndex])->Type.Ddi.DdiData.AuxIndex); - CurrentIndex++; - } - } - } else { - GMMx6124_STRUCT GMMx6124; - GMMx6124.Value = 0x3F; - NbSmuSrbmRegisterWrite (SMU_GMM_TO_FCR (GMMx6124_ADDRESS), &GMMx6124.Value, TRUE, GnbLibGetHeader (Pcie)); - GnbLibPciRMW ( - MAKE_SBDFO (0, 0, 0x18, 6, D18F6x80_ADDRESS), - AccessWidth32, - 0xffffffff, - (7 << D18F6x80_CableSafeDisAux_3_1_OFFSET) | (7 << D18F6x80_CableSafeDisAux_6_4_OFFSET), - GnbLibGetHeader (Pcie) - ); - } - CableSafeData.Config.Enable = 0x1; - CableSafeData.Config.DebounceFilter = 0; - CableSafeData.Config.SoftPeriod = 0x4; - CableSafeData.Config.Unit = 0x1; - CableSafeData.Config.Period = 0xf424; - NbSmuRcuRegisterWrite ( - SMUx0B_x85D0_ADDRESS, - (UINT32*) &CableSafeData, - sizeof (CableSafeData) / sizeof (UINT32), - TRUE, - StdHeader - ); - NbSmuServiceRequest (0x05, TRUE, StdHeader); - } else { - Status = AGESA_ERROR; - } - } - IDS_HDT_CONSOLE (GNB_TRACE, "GnbCableSafeEntry Exit [Status = 0x%04x]\n", Status); - return Status; -} - -/*----------------------------------------------------------------------------------------*/ -/** - * Callback to init max port Gen capability - * - * - * - * - * @param[in] Engine Pointer to engine config descriptor - * @param[in, out] Buffer Not used - * @param[in] Pcie Pointer to global PCIe configuration - * - */ - -VOID -STATIC -GnbCableSafeGetConnectorInfoArrayCallback ( - IN PCIe_ENGINE_CONFIG *Engine, - IN OUT VOID *Buffer, - IN PCIe_PLATFORM_CONFIG *Pcie - ) -{ - PCIe_ENGINE_CONFIG **EngineList; - EngineList = (PCIe_ENGINE_CONFIG**) Buffer; - EngineList [Engine->Type.Ddi.DdiData.HdpIndex] = Engine; -} - - -/*----------------------------------------------------------------------------------------*/ -/** - * Check if feature supported - * - * Module requre for LN B0 and above - * - * - * @param[in] StdHeader Standard configuration header - * @retval TRUE Cable safe needs to be enabled - */ - -BOOLEAN -GnbCableSafeIsSupported ( - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - BOOLEAN Result; - CPU_LOGICAL_ID LogicalId; - SMU_FIRMWARE_REV FirmwareRev; - Result = FALSE; - if (GfxLibIsControllerPresent (StdHeader)) { - GetLogicalIdOfCurrentCore (&LogicalId, StdHeader); - FirmwareRev = NbSmuFirmwareRevision (StdHeader); - if (SMI_FIRMWARE_REVISION (FirmwareRev) >= 0x010904 && LogicalId.Revision > AMD_F12_LN_A1) { - Result = TRUE; - } - } - return Result; -} diff --git a/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbCableSafe/GnbCableSafeDefs.h b/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbCableSafe/GnbCableSafeDefs.h deleted file mode 100644 index c4329d9817..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbCableSafe/GnbCableSafeDefs.h +++ /dev/null @@ -1,65 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * Cable safe module - * - * - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: GNB - * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $ - * - */ -/* -***************************************************************************** -* -* Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* *************************************************************************** -* -*/ - -#ifndef _GNBCABLESAFEDEFS_H_ -#define _GNBCABLESAFEDEFS_H_ - -#pragma pack (push, 1) - -/// Cable safe data package -typedef struct { - struct { - UINT32 Enable :1; ///< Enable cable safe - UINT32 DebounceFilter :3; ///< Debounce filter - UINT32 SoftPeriod :4; ///< Soft period - UINT32 Unit :4; ///< Unit - UINT32 Reserved :4; ///< Reserved - UINT32 Period :16; ///< Period - } Config; ///< Configuration package - UINT8 Data [12]; ///< HDP/AUX info array -} GNB_CABLE_SAFE_DATA; - -#pragma pack (pop) -#endif diff --git a/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbCableSafe/Makefile.inc b/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbCableSafe/Makefile.inc deleted file mode 100644 index 57b6c6a3a0..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbCableSafe/Makefile.inc +++ /dev/null @@ -1 +0,0 @@ -libagesa-y += GnbCableSafe.c diff --git a/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbCommonLib/GnbCommonLib.h b/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbCommonLib/GnbCommonLib.h deleted file mode 100644 index ea4eb86267..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbCommonLib/GnbCommonLib.h +++ /dev/null @@ -1,58 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * GNB register access services. - * - * - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: GNB - * @e \$Revision: 49526 $ @e \$Date: 2011-03-25 00:52:37 +0800 (Fri, 25 Mar 2011) $ - * - */ -/* -***************************************************************************** -* -* Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* *************************************************************************** -* -*/ -#ifndef _GNBCOMMONLIB_H_ -#define _GNBCOMMONLIB_H_ - -#include "GnbLib.h" -#include "GnbLibCpuAcc.h" -#include "GnbLibHeap.h" -#include "GnbLibIoAcc.h" -#include "GnbLibMemAcc.h" -#include "GnbLibPci.h" -#include "GnbLibPciAcc.h" -#include "GnbLibStall.h" -#include "GnbTable.h" - -#endif diff --git a/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbCommonLib/GnbLib.c b/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbCommonLib/GnbLib.c deleted file mode 100644 index 27ed1b823e..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbCommonLib/GnbLib.c +++ /dev/null @@ -1,609 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * GNB register access services. - * - * - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: GNB - * @e \$Revision: 49047 $ @e \$Date: 2011-03-16 15:27:08 +0800 (Wed, 16 Mar 2011) $ - * - */ -/* -***************************************************************************** -* -* Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* *************************************************************************** -* -*/ - -/*---------------------------------------------------------------------------------------- - * M O D U L E S U S E D - *---------------------------------------------------------------------------------------- - */ -#include "AGESA.h" -#include "Ids.h" -#include "amdlib.h" -#include "cpuFamilyTranslation.h" -#include "cpuServices.h" -#include "Gnb.h" -#include "GnbLib.h" -#include "GnbLibIoAcc.h" -#include "GnbLibPciAcc.h" -#include "GnbLibMemAcc.h" -#include "Filecode.h" -#define FILECODE PROC_GNB_MODULES_GNBCOMMONLIB_GNBLIB_FILECODE -/*---------------------------------------------------------------------------------------- - * D E F I N I T I O N S A N D M A C R O S - *---------------------------------------------------------------------------------------- - */ - -extern GNB_SERVICE *ServiceTable; - -/*---------------------------------------------------------------------------------------- - * T Y P E D E F S A N D S T R U C T U R E S - *---------------------------------------------------------------------------------------- - */ - - -/*---------------------------------------------------------------------------------------- - * P R O T O T Y P E S O F L O C A L F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ -VOID -GnbLibPciIndirectReadField ( - IN UINT32 Address, - IN UINT32 IndirectAddress, - IN UINT8 FieldOffset, - IN UINT8 FieldWidth, - OUT UINT32 *Value, - IN VOID *Config - ); - - -/*----------------------------------------------------------------------------------------*/ -/** - * Read GNB indirect registers - * - * - * - * @param[in] Address PCI address of indirect register - * @param[in] IndirectAddress Offset of indirect register - * @param[in] Width Width - * @param[out] Value Pointer to value - * @param[in] Config Pointer to standard header - */ -VOID -GnbLibPciIndirectRead ( - IN UINT32 Address, - IN UINT32 IndirectAddress, - IN ACCESS_WIDTH Width, - OUT VOID *Value, - IN VOID *Config - ) -{ - UINT32 IndexOffset; - IndexOffset = LibAmdAccessWidth (Width); - GnbLibPciWrite (Address, Width, &IndirectAddress, Config); - GnbLibPciRead (Address + IndexOffset, Width, Value, Config); -} -/*----------------------------------------------------------------------------------------*/ -/** - * Read GNB indirect registers field - * - * - * - * @param[in] Address PCI address of indirect register - * @param[in] IndirectAddress Offset of indirect register - * @param[in] FieldOffset Field offset - * @param[in] FieldWidth Field width - * @param[out] Value Pointer to value - * @param[in] Config Pointer to standard header - */ -VOID -GnbLibPciIndirectReadField ( - IN UINT32 Address, - IN UINT32 IndirectAddress, - IN UINT8 FieldOffset, - IN UINT8 FieldWidth, - OUT UINT32 *Value, - IN VOID *Config - ) -{ - UINT32 Mask; - GnbLibPciIndirectRead (Address, IndirectAddress, AccessWidth32, Value, Config); - Mask = (1 << FieldWidth) - 1; - *Value = (*Value >> FieldOffset) & Mask; -} - -/*----------------------------------------------------------------------------------------*/ -/** - * Write GNB indirect registers - * - * - * - * @param[in] Address PCI address of indirect register - * @param[in] IndirectAddress Offset of indirect register - * @param[in] Width Width - * @param[in] Value Pointer to value - * @param[in] Config Pointer to standard header - */ - -VOID -GnbLibPciIndirectWrite ( - IN UINT32 Address, - IN UINT32 IndirectAddress, - IN ACCESS_WIDTH Width, - IN VOID *Value, - IN VOID *Config - ) -{ - UINT32 IndexOffset; - IndexOffset = LibAmdAccessWidth (Width); - GnbLibPciWrite (Address, Width, &IndirectAddress, Config); - GnbLibPciWrite (Address + IndexOffset, Width, Value, Config); -} - -/*----------------------------------------------------------------------------------------*/ -/** - * Write GNB indirect registers field - * - * - * - * @param[in] Address PCI address of indirect register - * @param[in] IndirectAddress Offset of indirect register - * @param[in] FieldOffset Field offset - * @param[in] FieldWidth Field width - * @param[in] Value Pointer to value - * @param[in] S3Save Save for S3 (TRUE/FALSE) - * @param[in] Config Pointer to standard header - */ -VOID -GnbLibPciIndirectWriteField ( - IN UINT32 Address, - IN UINT32 IndirectAddress, - IN UINT8 FieldOffset, - IN UINT8 FieldWidth, - IN UINT32 Value, - IN BOOLEAN S3Save, - IN VOID *Config - ) -{ - UINT32 Data; - UINT32 Mask; - GnbLibPciIndirectRead (Address, IndirectAddress, AccessWidth32, &Data, Config); - Mask = (1 << FieldWidth) - 1; - Data &= (~(Mask << FieldOffset)); - Data |= ((Value & Mask) << FieldOffset); - GnbLibPciIndirectWrite (Address, IndirectAddress, S3Save ? AccessS3SaveWidth32 : AccessWidth32, &Data, Config); -} - -/*----------------------------------------------------------------------------------------*/ -/** - * Read/Modify/Write GNB indirect registers field - * - * - * - * @param[in] Address PCI address of indirect register - * @param[in] IndirectAddress Offset of indirect register - * @param[in] Width Width - * @param[in] Mask And Mask - * @param[in] Value Or Value - * @param[in] Config Pointer to standard header - */ -VOID -GnbLibPciIndirectRMW ( - IN UINT32 Address, - IN UINT32 IndirectAddress, - IN ACCESS_WIDTH Width, - IN UINT32 Mask, - IN UINT32 Value, - IN VOID *Config - ) -{ - UINT32 Data; - GnbLibPciIndirectRead ( - Address, - IndirectAddress, - (Width >= AccessS3SaveWidth8) ? (Width - (AccessS3SaveWidth8 - AccessWidth8)) : Width, - &Data, - Config - ); - Data = (Data & Mask) | Value; - GnbLibPciIndirectWrite (Address, IndirectAddress, Width, &Data, Config); -} - - -/*----------------------------------------------------------------------------------------*/ -/** - * Read/Modify/Write PCI registers - * - * - * - * @param[in] Address PCI address - * @param[in] Width Access width - * @param[in] Mask AND Mask - * @param[in] Value OR Value - * @param[in] Config Pointer to standard header - */ -VOID -GnbLibPciRMW ( - IN UINT32 Address, - IN ACCESS_WIDTH Width, - IN UINT32 Mask, - IN UINT32 Value, - IN VOID *Config - ) -{ - UINT32 Data; - GnbLibPciRead (Address, Width, &Data, Config); - Data = (Data & Mask) | Value; - GnbLibPciWrite (Address, Width, &Data, Config); -} - -/*----------------------------------------------------------------------------------------*/ -/** - * Read/Modify/Write I/O registers - * - * - * - * @param[in] Address I/O Port - * @param[in] Width Access width - * @param[in] Mask AND Mask - * @param[in] Value OR Mask - * @param[in] Config Pointer to standard header - */ -VOID -GnbLibIoRMW ( - IN UINT16 Address, - IN ACCESS_WIDTH Width, - IN UINT32 Mask, - IN UINT32 Value, - IN VOID *Config - ) -{ - UINT32 Data; - GnbLibIoRead (Address, Width, &Data, Config); - Data = (Data & Mask) | Value; - GnbLibIoWrite (Address, Width, &Data, Config); -} - -/*----------------------------------------------------------------------------------------*/ -/** - * Indirect IO block read - * - * - * - * @param[in] IndexPort Index Port - * @param[in] DataPort Data Port - * @param[in] Width Access width - * @param[in] IndexAddress Index Address - * @param[in] Count Count - * @param[in] Buffer Buffer - * @param[in] Config Pointer to standard header - */ -VOID -GnbLibIndirectIoBlockRead ( - IN UINT16 IndexPort, - IN UINT16 DataPort, - IN ACCESS_WIDTH Width, - IN UINT32 IndexAddress, - IN UINT32 Count, - IN VOID *Buffer, - IN VOID *Config - ) -{ - UINT32 Index; - for (Index = IndexAddress; Index < (IndexAddress + Count); Index++) { - GnbLibIoWrite (IndexPort, Width, &Index, Config); - GnbLibIoRead (DataPort, Width, Buffer, Config); - Buffer = (VOID *) ((UINT8 *) Buffer + LibAmdAccessWidth (Width)); - } -} - -/*----------------------------------------------------------------------------------------*/ -/** - * Get IOAPIC ID - * - * - * - * @param[in] IoApicBaseAddress IO APIC base address - * @param[in] Config Pointer to standard header - */ -UINT8 -GnbLiGetIoapicId ( - IN UINT64 IoApicBaseAddress, - IN VOID *Config - ) -{ - UINT32 Value; - Value = 0x0; - GnbLibMemWrite (IoApicBaseAddress, AccessWidth32, &Value, Config); - GnbLibMemRead (IoApicBaseAddress + 0x10, AccessWidth32, &Value, Config); - return (UINT8) (Value >> 24); -} - -/*----------------------------------------------------------------------------------------*/ -/** - * Read/Modify/Write MMIO registers - * - * - * - * @param[in] Address Physical address - * @param[in] Width Access width - * @param[in] Mask AND Mask - * @param[in] Value OR Value - * @param[in] Config Pointer to standard header - */ -VOID -GnbLibMemRMW ( - IN UINT64 Address, - IN ACCESS_WIDTH Width, - IN UINT32 Mask, - IN UINT32 Value, - IN VOID *Config - ) -{ - UINT32 Data; - GnbLibMemRead (Address, Width, &Data, Config); - Data = (Data & Mask) | Value; - GnbLibMemWrite (Address, Width, &Data, Config); -} -/*----------------------------------------------------------------------------------------*/ -/** - * Get number of sockets - * - * - * - * @param[in] StdHeader Standard configuration header - * @retval Total number of socket on platform - */ - -UINT32 -GnbGetNumberOfSockets ( - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - return GetPlatformNumberOfSockets (); -} - -/*----------------------------------------------------------------------------------------*/ -/** - * Get number of Silicons on the socket - * - * - * - * @param[in] SiliconId Socket ID - * @param[in] StdHeader Standard configuration header - * @retval Number of silicons/modules in device in socket - */ - -UINT32 -GnbGetNumberOfSiliconsOnSocket ( - IN UINT32 SiliconId, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - return 1; -} - -/*----------------------------------------------------------------------------------------*/ -/** - * Get PCI Address - * - * - * - * @param[in] SocketId Socket ID - * @param[in] SiliconId Silicon device Id - * @param[in] StdHeader Standard configuration header - * @retval PCI address of GNB for a given socket/silicon. - */ - -PCI_ADDR -GnbGetPciAddress ( - IN UINT32 SocketId, - IN UINT32 SiliconId, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - PCI_ADDR Gnb; - Gnb.AddressValue = MAKE_SBDFO (0, 0, 0, 0, 0); - return Gnb; -} - -/*----------------------------------------------------------------------------------------*/ -/** - * Check if anything plugged in socket - * - * - * - * @param[in] SocketId Socket ID - * @param[in] StdHeader Standard configuration header - * @retval TRUE CPU present in socket. - */ - -BOOLEAN -GnbIsDevicePresentInSocket ( - IN UINT32 SocketId, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - return IsProcessorPresent (SocketId, StdHeader); -} - - -/*----------------------------------------------------------------------------------------*/ -/** - * Claculate power of number - * - * - * - * @param[in] Value Number - * @param[in] Power Power - */ - -UINT32 -GnbLibPowerOf ( - IN UINT32 Value, - IN UINT32 Power - ) -{ - UINT32 Result; - if (Power == 0) { - return 1; - } - Result = Value; - while ((--Power) > 0) { - Result *= Value; - } - return Result; -} - -/*----------------------------------------------------------------------------------------*/ -/** - * Search buffer for pattern - * - * - * @param[in] Buf1 Pointer to source buffer which will be subject of search - * @param[in] Buf1Length Length of the source buffer - * @param[in] Buf2 Pointer to pattern buffer - * @param[in] Buf2Length Length of the pattern buffer - * @retval Pointer on first accurance of Buf2 in Buf1 or NULL - */ - -VOID* -GnbLibFind ( - IN UINT8 *Buf1, - IN UINTN Buf1Length, - IN UINT8 *Buf2, - IN UINTN Buf2Length - ) -{ - UINT8 *CurrentBuf1Ptr; - CurrentBuf1Ptr = Buf1; - while (CurrentBuf1Ptr < (Buf1 + Buf1Length - Buf2Length)) { - UINT8 *SourceBufPtr; - UINT8 *PatternBufPtr; - UINTN PatternBufLength; - SourceBufPtr = CurrentBuf1Ptr; - PatternBufPtr = Buf2; - PatternBufLength = Buf2Length; - while ((*SourceBufPtr++ == *PatternBufPtr++) && (PatternBufLength-- != 0)); - if (PatternBufLength == 0) { - return CurrentBuf1Ptr; - } - CurrentBuf1Ptr++; - } - return NULL; -} - -/*----------------------------------------------------------------------------------------*/ -/** - * Dump buffer to HDTOUT - * - * - * @param[in] Buffer Buffer pointer - * @param[in] Count Count of data elements - * @param[in] DataWidth DataWidth 1 - Byte; 2 - Word; 3 - DWORD; 4 - QWORD - * @param[in] LineWidth Number of data item per line - */ -VOID -GnbLibDebugDumpBuffer ( - IN VOID *Buffer, - IN UINT32 Count, - IN UINT8 DataWidth, - IN UINT8 LineWidth - ) -{ - UINT32 Index; - UINT32 DataItemCount; - ASSERT (LineWidth != 0); - ASSERT (DataWidth >= 1 && DataWidth <= 4); - DataItemCount = 0; - for (Index = 0; Index < Count; ) { - switch (DataWidth) { - case 1: - IDS_HDT_CONSOLE (GNB_TRACE, "%02x ", *((UINT8 *) Buffer + Index)); - Index += 1; - break; - case 2: - IDS_HDT_CONSOLE (GNB_TRACE, "%04x ", *(UINT16 *) ((UINT8 *) Buffer + Index)); - Index += 2; - break; - case 3: - IDS_HDT_CONSOLE (GNB_TRACE, "%08x ", *(UINT32 *) ((UINT8 *) Buffer + Index)); - Index += 4; - break; - case 4: - IDS_HDT_CONSOLE (GNB_TRACE, "%08x%08", *(UINT32 *) ((UINT8 *) Buffer + Index), *(UINT32 *) ((UINT8 *) Buffer + Index + 4)); - Index += 8; - break; - default: - IDS_HDT_CONSOLE (GNB_TRACE, "ERROR! Incorrect Data Width\n"); - return; - } - if (++DataItemCount >= LineWidth) { - IDS_HDT_CONSOLE (GNB_TRACE, "\n"); - DataItemCount = 0; - } - } -} - -/*----------------------------------------------------------------------------------------*/ -/** - * Dump buffer to HDTOUT - * - * - * @param[in] ServiceId Service ID - * @param[in] SocketId Socket ID - * @param[in] ServiceProtocol Service protocol - * @param[in] StdHeader Standard Configuration Header - */ -AGESA_STATUS -GnbLibLocateService ( - IN GNB_SERVICE_ID ServiceId, - IN UINT8 SocketId, - IN VOID **ServiceProtocol, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - GNB_SERVICE *SeviceEntry; - CPU_LOGICAL_ID LogicalId; - SeviceEntry = ServiceTable; - GetLogicalIdOfSocket (SocketId, &LogicalId, StdHeader); - while (SeviceEntry != NULL) { - if (SeviceEntry->ServiceId == ServiceId && (LogicalId.Family & SeviceEntry->Family) != 0) { - *ServiceProtocol = SeviceEntry->ServiceProtocol; - return AGESA_SUCCESS; - } - SeviceEntry = SeviceEntry->NextService; - } - return AGESA_UNSUPPORTED; -} - diff --git a/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbCommonLib/GnbLib.h b/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbCommonLib/GnbLib.h deleted file mode 100644 index 5db06ef31e..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbCommonLib/GnbLib.h +++ /dev/null @@ -1,195 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * GNB register access services. - * - * - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: GNB - * @e \$Revision: 47656 $ @e \$Date: 2011-02-25 02:39:38 +0800 (Fri, 25 Feb 2011) $ - * - */ -/* -***************************************************************************** -* -* Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* *************************************************************************** -* -*/ -#ifndef _GNBLIB_H_ -#define _GNBLIB_H_ - -#define IOC_WRITE_ENABLE 0x80 - -typedef AGESA_STATUS (F_GNB_REGISTER_ACCESS) ( - UINT8 RegisterSpaceType, - UINT32 Address, - VOID *Value, - UINT32 Flags, - AMD_CONFIG_PARAMS *StdHeader -); - -typedef F_GNB_REGISTER_ACCESS *PF_GNB_REGISTER_ACCESS; - -/// Register Read/Write protocol -typedef struct { - PF_GNB_REGISTER_ACCESS Read; ///< Read Register - PF_GNB_REGISTER_ACCESS Write; ///< Write Register -} GNB_REGISTER_PROTOCOL; - -VOID -GnbLibPciIndirectWrite ( - IN UINT32 Address, - IN UINT32 IndirectAddress, - IN ACCESS_WIDTH Width, - IN VOID *Value, - IN VOID *Config - ); - -VOID -GnbLibPciIndirectRead ( - IN UINT32 Address, - IN UINT32 IndirectAddress, - IN ACCESS_WIDTH Width, - OUT VOID *Value, - IN VOID *Config - ); - -VOID -GnbLibPciIndirectRMW ( - IN UINT32 Address, - IN UINT32 IndirectAddress, - IN ACCESS_WIDTH Width, - IN UINT32 Mask, - IN UINT32 Value, - IN VOID *Config - ); - -VOID -GnbLibPciIndirectWriteField ( - IN UINT32 Address, - IN UINT32 IndirectAddress, - IN UINT8 FieldOffset, - IN UINT8 FieldWidth, - IN UINT32 Value, - IN BOOLEAN S3Save, - IN VOID *Config - ); - - -VOID -GnbLibPciRMW ( - IN UINT32 Address, - IN ACCESS_WIDTH Width, - IN UINT32 Mask, - IN UINT32 Value, - IN VOID *Config - ); - -VOID -GnbLibIoRMW ( - IN UINT16 Address, - IN ACCESS_WIDTH Width, - IN UINT32 Mask, - IN UINT32 Value, - IN VOID *Config - ); - -UINT32 -GnbGetNumberOfSockets ( - IN AMD_CONFIG_PARAMS *StdHeader - ); - -UINT32 -GnbGetNumberOfSiliconsOnSocket ( - IN UINT32 SiliconId, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -BOOLEAN -GnbIsDevicePresentInSocket ( - IN UINT32 SocketId, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -PCI_ADDR -GnbGetPciAddress ( - IN UINT32 SocketId, - IN UINT32 SiliconId, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -UINT32 -GnbLibPowerOf ( - IN UINT32 Value, - IN UINT32 Power - ); - -VOID* -GnbLibFind ( - IN UINT8 *Buf1, - IN UINTN Buf1Length, - IN UINT8 *Buf2, - IN UINTN Buf2Length - ); - -VOID -GnbLibIndirectIoBlockRead ( - IN UINT16 IndexPort, - IN UINT16 DataPort, - IN ACCESS_WIDTH Width, - IN UINT32 IndexAddress, - IN UINT32 Count, - IN VOID *Buffer, - IN VOID *Config - ); - -UINT8 -GnbLiGetIoapicId ( - IN UINT64 IoApicBaseAddress, - IN VOID *Config - ); - -VOID -GnbLibDebugDumpBuffer ( - IN VOID *Buffer, - IN UINT32 Count, - IN UINT8 DataWidth, - IN UINT8 LineWidth - ); - -AGESA_STATUS -GnbLibLocateService ( - IN GNB_SERVICE_ID ServiceId, - IN UINT8 SocketId, - IN VOID **ServiceProtocol, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -#endif diff --git a/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbCommonLib/GnbLibCpuAcc.c b/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbCommonLib/GnbLibCpuAcc.c deleted file mode 100644 index bb15e6eb7e..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbCommonLib/GnbLibCpuAcc.c +++ /dev/null @@ -1,130 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * Service procedure to access various CPU registers. - * - * - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: GNB - * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $ - * - */ -/* -***************************************************************************** -* -* Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* *************************************************************************** -* -*/ - -/*---------------------------------------------------------------------------------------- - * M O D U L E S U S E D - *---------------------------------------------------------------------------------------- - */ -#include "Porting.h" -#include "AMD.h" -#include "GnbLibPciAcc.h" -#include "GnbLibCpuAcc.h" -#include "Filecode.h" -#define FILECODE PROC_GNB_MODULES_GNBCOMMONLIB_GNBLIBCPUACC_FILECODE -/*---------------------------------------------------------------------------------------- - * D E F I N I T I O N S A N D M A C R O S - *---------------------------------------------------------------------------------------- - */ - - -/*---------------------------------------------------------------------------------------- - * T Y P E D E F S A N D S T R U C T U R E S - *---------------------------------------------------------------------------------------- - */ - - -/*---------------------------------------------------------------------------------------- - * P R O T O T Y P E S O F L O C A L F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ - - -/*----------------------------------------------------------------------------------------*/ -/** - * Read CPU (DCT) indirect registers - * - * - * - * @param[in] Address PCI address of DCT register - * @param[in] IndirectAddress Offset of DCT register - * @param[out] Value Pointer to value - * @param[in] Config Pointer to standard header - */ -VOID -GnbLibCpuPciIndirectRead ( - IN UINT32 Address, - IN UINT32 IndirectAddress, - OUT UINT32 *Value, - IN VOID *Config - ) -{ - UINT32 OffsetRegisterValue; - GnbLibPciWrite (Address, AccessWidth32, &IndirectAddress, Config); - do { - GnbLibPciRead (Address , AccessWidth32, &OffsetRegisterValue, Config); - } while ((OffsetRegisterValue & BIT31) == 0); - GnbLibPciRead (Address + 4, AccessWidth32, Value, Config); -} - - -/*----------------------------------------------------------------------------------------*/ -/** - * Write CPU (DCT) indirect registers - * - * - * - * @param[in] Address PCI address of DCT register - * @param[in] IndirectAddress Offset of DCT register - * @param[in] Value Pointer to value - * @param[in] Config Pointer to standard header - */ -VOID -GnbLibCpuPciIndirectWrite ( - IN UINT32 Address, - IN UINT32 IndirectAddress, - IN UINT32 *Value, - IN VOID *Config - ) -{ - UINT32 OffsetRegisterValue; - OffsetRegisterValue = IndirectAddress | BIT30; - GnbLibPciWrite (Address + 4, AccessWidth32, Value, Config); - GnbLibPciWrite (Address, AccessWidth32, &IndirectAddress, Config); - do { - GnbLibPciRead (Address , AccessWidth32, &OffsetRegisterValue, Config); - } while ((OffsetRegisterValue & BIT31) == 0); -} - - diff --git a/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbCommonLib/GnbLibCpuAcc.h b/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbCommonLib/GnbLibCpuAcc.h deleted file mode 100644 index 5eda42405b..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbCommonLib/GnbLibCpuAcc.h +++ /dev/null @@ -1,65 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * Service procedure to access various CPU registers. - * - * - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: GNB - * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $ - * - */ -/* -***************************************************************************** -* -* Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* *************************************************************************** -* -*/ -#ifndef _CPUACCLIB_H_ -#define _CPUACCLIB_H_ - -VOID -GnbLibCpuPciIndirectWrite ( - IN UINT32 Address, - IN UINT32 IndirectAddress, - IN UINT32 *Value, - IN VOID *Config - ); - -VOID -GnbLibCpuPciIndirectRead ( - IN UINT32 Address, - IN UINT32 IndirectAddress, - OUT UINT32 *Value, - IN VOID *Config - ); - - -#endif diff --git a/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbCommonLib/GnbLibHeap.c b/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbCommonLib/GnbLibHeap.c deleted file mode 100644 index bfef4143e2..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbCommonLib/GnbLibHeap.c +++ /dev/null @@ -1,159 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * Service procedure to access heap. - * - * - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: GNB - * @e \$Revision: 49532 $ @e \$Date: 2011-03-25 02:54:43 +0800 (Fri, 25 Mar 2011) $ - * - */ -/* -***************************************************************************** -* -* Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* *************************************************************************** -* -*/ - -/*---------------------------------------------------------------------------------------- - * M O D U L E S U S E D - *---------------------------------------------------------------------------------------- - */ -#include "Porting.h" -#include "AMD.h" -#include "amdlib.h" -#include "heapManager.h" -#include "GnbLibPciAcc.h" -#include "GnbLibHeap.h" -#include "Filecode.h" -#define FILECODE PROC_GNB_MODULES_GNBCOMMONLIB_GNBLIBHEAP_FILECODE -/*---------------------------------------------------------------------------------------- - * D E F I N I T I O N S A N D M A C R O S - *---------------------------------------------------------------------------------------- - */ - - -/*---------------------------------------------------------------------------------------- - * T Y P E D E F S A N D S T R U C T U R E S - *---------------------------------------------------------------------------------------- - */ - - -/*---------------------------------------------------------------------------------------*/ -/** - * Allocates space for a new buffer in the heap - * - * - * @param[in] Handle Buffer handle - * @param[in] Length Buffer length - * @param[in] StdHeader Standard configuration header - * - * @retval NULL Buffer allocation fail - * - */ - -VOID * -GnbAllocateHeapBuffer ( - IN UINT32 Handle, - IN UINTN Length, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - AGESA_STATUS Status; - ALLOCATE_HEAP_PARAMS AllocHeapParams; - - AllocHeapParams.RequestedBufferSize = (UINT32) Length; - AllocHeapParams.BufferHandle = Handle; - AllocHeapParams.Persist = HEAP_SYSTEM_MEM; - Status = HeapAllocateBuffer (&AllocHeapParams, StdHeader); - if (Status != AGESA_SUCCESS) { - return NULL; - } - return AllocHeapParams.BufferPtr; -} - - -/*---------------------------------------------------------------------------------------*/ -/** - * Allocates space for a new buffer in the heap and clear it - * - * - * @param[in] Handle Buffer handle - * @param[in] Length Buffer length - * @param[in] StdHeader Standard configuration header - * - * @retval NULL Buffer allocation fail - * - */ - -VOID * -GnbAllocateHeapBufferAndClear ( - IN UINT32 Handle, - IN UINTN Length, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - VOID *Buffer; - Buffer = GnbAllocateHeapBuffer (Handle, Length, StdHeader); - if (Buffer != NULL) { - LibAmdMemFill (Buffer, 0x00, Length, StdHeader); - } - return Buffer; -} - -/*---------------------------------------------------------------------------------------*/ -/** - * Locates a previously allocated buffer on the heap. - * - * - * @param[in] Handle Buffer handle - * @param[in] StdHeader Standard configuration header - * - * @retval NULL Buffer handle not found - * - */ - -VOID * -GnbLocateHeapBuffer ( - IN UINT32 Handle, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - AGESA_STATUS Status; - LOCATE_HEAP_PTR LocHeapParams; - LocHeapParams.BufferHandle = Handle; - Status = HeapLocateBuffer (&LocHeapParams, StdHeader); - if (Status != AGESA_SUCCESS) { - return NULL; - } - return LocHeapParams.BufferPtr; -} - diff --git a/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbCommonLib/GnbLibHeap.h b/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbCommonLib/GnbLibHeap.h deleted file mode 100644 index 186e3f7354..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbCommonLib/GnbLibHeap.h +++ /dev/null @@ -1,69 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * Service procedure to access heap. - * - * - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: GNB - * @e \$Revision: 49532 $ @e \$Date: 2011-03-25 02:54:43 +0800 (Fri, 25 Mar 2011) $ - * - */ -/* -***************************************************************************** -* -* Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* *************************************************************************** -* -*/ - -#ifndef _GNBHEAPLIB_H_ -#define _GNBHEAPLIB_H_ - -VOID * -GnbAllocateHeapBuffer ( - IN UINT32 Handle, - IN UINTN Length, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -VOID * -GnbLocateHeapBuffer ( - IN UINT32 Handle, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -VOID * -GnbAllocateHeapBufferAndClear ( - IN UINT32 Handle, - IN UINTN Length, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -#endif diff --git a/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbCommonLib/GnbLibIoAcc.c b/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbCommonLib/GnbLibIoAcc.c deleted file mode 100644 index 1d6be12461..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbCommonLib/GnbLibIoAcc.c +++ /dev/null @@ -1,122 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * -* Service procedure to access I/O registers. - * - * - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: GNB - * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $ - * - */ -/* -***************************************************************************** -* -* Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* *************************************************************************** -* -*/ - -/*---------------------------------------------------------------------------------------- - * M O D U L E S U S E D - *---------------------------------------------------------------------------------------- - */ -#include "Porting.h" -#include "AMD.h" -#include "amdlib.h" -#include "GnbLibIoAcc.h" -#include "S3SaveState.h" -#include "Filecode.h" -#define FILECODE PROC_GNB_MODULES_GNBCOMMONLIB_GNBLIBIOACC_FILECODE -/*---------------------------------------------------------------------------------------- - * D E F I N I T I O N S A N D M A C R O S - *---------------------------------------------------------------------------------------- - */ - - -/*---------------------------------------------------------------------------------------- - * T Y P E D E F S A N D S T R U C T U R E S - *---------------------------------------------------------------------------------------- - */ - - -/*---------------------------------------------------------------------------------------- - * P R O T O T Y P E S O F L O C A L F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ -/*----------------------------------------------------------------------------------------*/ - -/*---------------------------------------------------------------------------------------*/ -/*----------------------------------------------------------------------------------------*/ -/** - * Write I/O Port - * - * - * - * @param[in] Address Physical Address - * @param[in] Width Access width - * @param[in] Value Pointer to value - * @param[in] StdHeader Standard configuration header - */ - -VOID -GnbLibIoWrite ( - IN UINT16 Address, - IN ACCESS_WIDTH Width, - IN VOID *Value, - IN VOID *StdHeader - ) -{ - if (Width >= AccessS3SaveWidth8) { - S3_SAVE_IO_WRITE (StdHeader, Address, Width, Value); - } - LibAmdIoWrite (Width, Address, Value, StdHeader); -} -/** - * Read IO port - * - * - * - * @param[in] Address Physical Address - * @param[in] Width Access width - * @param[out] Value Pointer to value - * @param[in] StdHeader Standard configuration header - */ - -VOID -GnbLibIoRead ( - IN UINT16 Address, - IN ACCESS_WIDTH Width, - OUT VOID *Value, - IN VOID *StdHeader - ) -{ - LibAmdIoRead (Width, Address, Value, StdHeader); -} - diff --git a/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbCommonLib/GnbLibIoAcc.h b/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbCommonLib/GnbLibIoAcc.h deleted file mode 100644 index ebfd248434..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbCommonLib/GnbLibIoAcc.h +++ /dev/null @@ -1,66 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * Service procedure to access I/O registers. - * - * - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: GNB - * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $ - * - */ -/* -***************************************************************************** -* -* Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* *************************************************************************** -* -*/ -#ifndef _IOACCLIB_H_ -#define _IOACCLIB_H_ - - -VOID -GnbLibIoWrite ( - IN UINT16 Address, - IN ACCESS_WIDTH Width, - IN VOID *Value, - IN VOID *StdHeader - ); - -VOID -GnbLibIoRead ( - IN UINT16 Address, - IN ACCESS_WIDTH Width, - OUT VOID *Value, - IN VOID *StdHeader - ); - - -#endif diff --git a/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbCommonLib/GnbLibMemAcc.c b/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbCommonLib/GnbLibMemAcc.c deleted file mode 100644 index db2f717e07..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbCommonLib/GnbLibMemAcc.c +++ /dev/null @@ -1,125 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * Service procedure to access MMIO registers. - * - * - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: GNB - * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $ - * - */ -/* -***************************************************************************** -* -* Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* *************************************************************************** -* -*/ - -/*---------------------------------------------------------------------------------------- - * M O D U L E S U S E D - *---------------------------------------------------------------------------------------- - */ -#include "Porting.h" -#include "AMD.h" -#include "amdlib.h" -#include "GnbLibMemAcc.h" -#include "S3SaveState.h" -#include "Filecode.h" -#define FILECODE PROC_GNB_MODULES_GNBCOMMONLIB_GNBLIBMEMACC_FILECODE -/*---------------------------------------------------------------------------------------- - * D E F I N I T I O N S A N D M A C R O S - *---------------------------------------------------------------------------------------- - */ - - -/*---------------------------------------------------------------------------------------- - * T Y P E D E F S A N D S T R U C T U R E S - *---------------------------------------------------------------------------------------- - */ - - -/*---------------------------------------------------------------------------------------- - * P R O T O T Y P E S O F L O C A L F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ - -/*----------------------------------------------------------------------------------------*/ -/** - * Write Memory/MMIO registers - * - * - * - * @param[in] Address Physical Address - * @param[in] Width Access width - * @param[in] Value Pointer to value - * @param[in] StdHeader Standard configuration header - */ - -VOID -GnbLibMemWrite ( - IN UINT64 Address, - IN ACCESS_WIDTH Width, - IN VOID *Value, - IN VOID *StdHeader - ) -{ - if (Width >= AccessS3SaveWidth8) { - S3_SAVE_MEM_WRITE (StdHeader, Address, Width, Value); - } - LibAmdMemWrite (Width, Address, Value, StdHeader); -} - -/*----------------------------------------------------------------------------------------*/ -/** - * Read Memory/MMIO registers - * - * - * - * @param[in] Address Physical Address - * @param[in] Width Access width - * @param[out] Value Pointer to value - * @param[in] StdHeader Standard configuration header - */ - -VOID -GnbLibMemRead ( - IN UINT64 Address, - IN ACCESS_WIDTH Width, - OUT VOID *Value, - IN VOID *StdHeader - ) -{ - LibAmdMemRead (Width, Address, Value, StdHeader); -} - - - - diff --git a/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbCommonLib/GnbLibMemAcc.h b/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbCommonLib/GnbLibMemAcc.h deleted file mode 100644 index a9a448d2da..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbCommonLib/GnbLibMemAcc.h +++ /dev/null @@ -1,73 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * Service procedure to access MMIO registers. - * - * - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: GNB - * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $ - * - */ -/* -***************************************************************************** -* -* Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* *************************************************************************** -* -*/ -#ifndef _MEMACCLIB_H_ -#define _MEMACCLIB_H_ - -VOID -GnbLibMemWrite ( - IN UINT64 Address, - IN ACCESS_WIDTH Width, - IN VOID *Value, - IN VOID *StdHeader - ); - -VOID -GnbLibMemRead ( - IN UINT64 Address, - IN ACCESS_WIDTH Width, - OUT VOID *Value, - IN VOID *StdHeader - ); - -VOID -GnbLibMemRMW ( - IN UINT64 Address, - IN ACCESS_WIDTH Width, - IN UINT32 Mask, - IN UINT32 Value, - IN VOID *Config - ); - -#endif diff --git a/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbCommonLib/GnbLibPci.c b/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbCommonLib/GnbLibPci.c deleted file mode 100644 index ef3c865e90..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbCommonLib/GnbLibPci.c +++ /dev/null @@ -1,410 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * Various PCI service routines. - * - * - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: GNB - * @e \$Revision: 49526 $ @e \$Date: 2011-03-25 00:52:37 +0800 (Fri, 25 Mar 2011) $ - * - */ -/* -***************************************************************************** -* -* Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* *************************************************************************** -* -*/ - - -#include "AGESA.h" -#include "amdlib.h" -#include "Gnb.h" -#include "GnbLibPciAcc.h" -#include "GnbLibPci.h" -#include "GnbLib.h" -#include "Filecode.h" -#define FILECODE PROC_GNB_MODULES_GNBCOMMONLIB_GNBLIBPCI_FILECODE - -UINT16 -GnbLibFindPcieExtendedCapability ( - IN UINT32 Address, - IN UINT16 ExtendedCapabilityId, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -/*----------------------------------------------------------------------------------------*/ -/* - * Check if device present - * - * - * - * @param[in] Address PCI address (as described in PCI_ADDR) - * @param[in] StdHeader Standard configuration header - * @retval TRUE Device is present - * @retval FALSE Device is not present - */ - -BOOLEAN -GnbLibPciIsDevicePresent ( - IN UINT32 Address, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - UINT32 DeviceId; - GnbLibPciRead (Address, AccessWidth32, &DeviceId, StdHeader); - if (DeviceId == 0xffffffff) { - return FALSE; - } else { - return TRUE; - } -} - - -/*----------------------------------------------------------------------------------------*/ -/* - * Check if device is bridge - * - * - * - * @param[in] Address PCI address (as described in PCI_ADDR) - * @param[in] StdHeader Standard configuration header - * @retval TRUE Device is a bridge - * @retval FALSE Device is not a bridge - */ - -BOOLEAN -GnbLibPciIsBridgeDevice ( - IN UINT32 Address, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - UINT8 Header; - GnbLibPciRead (Address | 0xe, AccessWidth8, &Header, StdHeader); - if ((Header & 0x7f) == 1) { - return TRUE; - } else { - return FALSE; - } -} - -/*----------------------------------------------------------------------------------------*/ -/* - * Check if device is multifunction - * - * - * - * @param[in] Address PCI address (as described in PCI_ADDR) - * @param[in] StdHeader Standard configuration header - * @retval TRUE Device is a multifunction device. - * @retval FALSE Device is a single function device. - * - */ -BOOLEAN -GnbLibPciIsMultiFunctionDevice ( - IN UINT32 Address, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - UINT8 Header; - GnbLibPciRead (Address | 0xe, AccessWidth8, &Header, StdHeader); - if ((Header & 0x80) != 0) { - return TRUE; - } else { - return FALSE; - } -} - -/*----------------------------------------------------------------------------------------*/ -/* - * Check if device is PCIe device - * - * - * - * @param[in] Address PCI address (as described in PCI_ADDR) - * @param[in] StdHeader Standard configuration header - * @retval TRUE Device is a PCIe device - * @retval FALSE Device is not a PCIe device - * - */ - -BOOLEAN -GnbLibPciIsPcieDevice ( - IN UINT32 Address, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - if (GnbLibFindPciCapability (Address, PCIE_CAP_ID, StdHeader) != 0 ) { - return TRUE; - } else { - return FALSE; - } -} - - -/*----------------------------------------------------------------------------------------*/ -/* - * Find PCI capability pointer - * - * - * - * @param[in] Address PCI address (as described in PCI_ADDR) - * @param[in] CapabilityId PCI capability ID - * @param[in] StdHeader Standard configuration header - * @retval Register address of capability pointer - * - */ - -UINT8 -GnbLibFindPciCapability ( - IN UINT32 Address, - IN UINT8 CapabilityId, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - UINT8 CapabilityPtr; - UINT8 CurrentCapabilityId; - CapabilityPtr = 0x34; - if (!GnbLibPciIsDevicePresent (Address, StdHeader)) { - return 0; - } - while (CapabilityPtr != 0) { - GnbLibPciRead (Address | CapabilityPtr, AccessWidth8 , &CapabilityPtr, StdHeader); - if (CapabilityPtr != 0) { - GnbLibPciRead (Address | CapabilityPtr , AccessWidth8 , &CurrentCapabilityId, StdHeader); - if (CurrentCapabilityId == CapabilityId) { - break; - } - CapabilityPtr++; - } - } - return CapabilityPtr; -} -/*----------------------------------------------------------------------------------------*/ -/* - * Find PCIe extended capability pointer - * - * - * - * @param[in] Address PCI address (as described in PCI_ADDR) - * @param[in] ExtendedCapabilityId Extended PCIe capability ID - * @param[in] StdHeader Standard configuration header - * @retval Register address of extended capability pointer - * - */ - - -UINT16 -GnbLibFindPcieExtendedCapability ( - IN UINT32 Address, - IN UINT16 ExtendedCapabilityId, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - UINT16 CapabilityPtr; - UINT32 ExtendedCapabilityIdBlock; - if (GnbLibPciIsPcieDevice (Address, StdHeader)) { - GnbLibPciRead (Address | 0x100 , AccessWidth32 , &ExtendedCapabilityIdBlock, StdHeader); - if ((ExtendedCapabilityIdBlock != 0) && ((UINT16)ExtendedCapabilityIdBlock != 0xffff)) { - do { - CapabilityPtr = (UINT16) ((ExtendedCapabilityIdBlock >> 20) & 0xfff); - if ((UINT16)ExtendedCapabilityIdBlock == ExtendedCapabilityId) { - return CapabilityPtr; - } - GnbLibPciRead (Address | CapabilityPtr , AccessWidth32 , &ExtendedCapabilityIdBlock, StdHeader); - } while (((ExtendedCapabilityIdBlock >> 20) & 0xfff) != 0); - } - } - return 0; -} - -/*----------------------------------------------------------------------------------------*/ -/* - * Scan range of device on PCI bus. - * - * - * - * @param[in] Start Start address to start scan from - * @param[in] End End address of scan - * @param[in] ScanData Supporting data - * - */ -/*----------------------------------------------------------------------------------------*/ -VOID -GnbLibPciScan ( - IN PCI_ADDR Start, - IN PCI_ADDR End, - IN GNB_PCI_SCAN_DATA *ScanData - ) -{ - UINTN Bus; - UINTN Device; - UINTN LastDevice; - UINTN Function; - UINTN LastFunction; - PCI_ADDR PciDevice; - SCAN_STATUS Status; - - for (Bus = Start.Address.Bus; Bus <= End.Address.Bus; Bus++) { - Device = (Bus == Start.Address.Bus) ? Start.Address.Device : 0x00; - LastDevice = (Bus == End.Address.Bus) ? End.Address.Device : 0x1F; - for ( ; Device <= LastDevice; Device++) { - if ((Bus == Start.Address.Bus) && (Device == Start.Address.Device)) { - Function = Start.Address.Function; - } else { - Function = 0x0; - } - PciDevice.AddressValue = MAKE_SBDFO (0, Bus, Device, Function, 0); - if (!GnbLibPciIsDevicePresent (PciDevice.AddressValue, ScanData->StdHeader)) { - continue; - } - if (GnbLibPciIsMultiFunctionDevice (PciDevice.AddressValue, ScanData->StdHeader)) { - if ((Bus == End.Address.Bus) && (Device == End.Address.Device)) { - LastFunction = Start.Address.Function; - } else { - LastFunction = 0x7; - } - } else { - LastFunction = 0x0; - } - for ( ; Function <= LastFunction; Function++) { - PciDevice.AddressValue = MAKE_SBDFO (0, Bus, Device, Function, 0); - if (GnbLibPciIsDevicePresent (PciDevice.AddressValue, ScanData->StdHeader)) { - Status = ScanData->GnbScanCallback (PciDevice, ScanData); - if ((Status & SCAN_SKIP_FUNCTIONS) != 0) { - Function = LastFunction + 1; - } - if ((Status & SCAN_SKIP_DEVICES) != 0) { - Device = LastDevice + 1; - } - if ((Status & SCAN_SKIP_BUSES) != 0) { - Bus = End.Address.Bus + 1; - } - } - } - } - } -} - -/*----------------------------------------------------------------------------------------*/ -/** - * Scan all subordinate buses - * - * - * @param[in] Bridge PCI bridge address - * @param[in,out] ScanData Scan configuration data - * - */ -VOID -GnbLibPciScanSecondaryBus ( - IN PCI_ADDR Bridge, - IN OUT GNB_PCI_SCAN_DATA *ScanData - ) -{ - PCI_ADDR StartRange; - PCI_ADDR EndRange; - UINT8 SecondaryBus; - GnbLibPciRead (Bridge.AddressValue | 0x19, AccessWidth8, &SecondaryBus, ScanData->StdHeader); - if (SecondaryBus != 0) { - StartRange.AddressValue = MAKE_SBDFO (0, SecondaryBus, 0, 0, 0); - EndRange.AddressValue = MAKE_SBDFO (0, SecondaryBus, 0x1f, 0x7, 0); - GnbLibPciScan (StartRange, EndRange, ScanData); - } -} - -/*----------------------------------------------------------------------------------------*/ -/** - * Get PCIe device type - * - * - * - * @param[in] Device PCI address of device. - * @param[in] StdHeader Northbridge configuration structure pointer. - * - * @retval PCIE_DEVICE_TYPE - */ - /*----------------------------------------------------------------------------------------*/ - -PCIE_DEVICE_TYPE -GnbLibGetPcieDeviceType ( - IN PCI_ADDR Device, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - UINT8 PcieCapPtr; - UINT8 Value; - - PcieCapPtr = GnbLibFindPciCapability (Device.AddressValue, PCIE_CAP_ID, StdHeader); - if (PcieCapPtr != 0) { - GnbLibPciRead (Device.AddressValue | (PcieCapPtr + 0x2) , AccessWidth8, &Value, StdHeader); - return Value >> 4; - } - return PcieNotPcieDevice; -} - -/*----------------------------------------------------------------------------------------*/ -/** - * Save config space area - * - * - * - * @param[in] Address PCI address of device. - * @param[in] StartRegisterAddress Start register address. - * @param[in] EndRegisterAddress End register address. - * @param[in] Width Acess width. - * @param[in] StdHeader Standard header. - * - */ - /*----------------------------------------------------------------------------------------*/ - -VOID -GnbLibS3SaveConfigSpace ( - IN UINT32 Address, - IN UINT16 StartRegisterAddress, - IN UINT16 EndRegisterAddress, - IN ACCESS_WIDTH Width, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - UINT16 Index; - UINT16 Delta; - UINT16 Length; - Length = (StartRegisterAddress < EndRegisterAddress) ? (EndRegisterAddress - StartRegisterAddress) : (StartRegisterAddress - EndRegisterAddress); - Delta = LibAmdAccessWidth (Width); - for (Index = 0; Index <= Length; Index = Index + Delta) { - GnbLibPciRMW ( - Address | ((StartRegisterAddress < EndRegisterAddress) ? (StartRegisterAddress + Index) : (StartRegisterAddress - Index)), - Width, - 0xffffffff, - 0x0, - StdHeader - ); - } -} diff --git a/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbCommonLib/GnbLibPci.h b/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbCommonLib/GnbLibPci.h deleted file mode 100644 index 4d824ed555..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbCommonLib/GnbLibPci.h +++ /dev/null @@ -1,150 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * Various PCI service routines. - * - * - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: GNB - * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $ - * - */ -/* -***************************************************************************** -* -* Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* *************************************************************************** -* -*/ - -#ifndef _GNBLIBPCI_H_ -#define _GNBLIBPCI_H_ - -#define PCIE_CAP_ID 0x10 -#define IOMMU_CAP_ID 0x0F - -/// PCIe device type -typedef enum { - PcieDeviceEndPoint, ///< Endpoint - PcieDeviceLegacyEndPoint, ///< Legacy endpoint - PcieDeviceRootComplex = 4, ///< Root complex - PcieDeviceUpstreamPort, ///< Upstream port - PcieDeviceDownstreamPort, ///< Downstream Port - PcieDevicePcieToPcix, ///< PCIe to PCI/PCIx bridge - PcieDevicePcixToPcie, ///< PCI/PCIx to PCIe bridge - PcieNotPcieDevice = 0xff ///< unknown device -} PCIE_DEVICE_TYPE; - -typedef UINT32 SCAN_STATUS; - -#define SCAN_SKIP_FUNCTIONS 0x1 -#define SCAN_SKIP_DEVICES 0x2 -#define SCAN_SKIP_BUSES 0x4 -#define SCAN_SUCCESS 0x0 - -// Forward declaration needed for multi-structure mutual references -AGESA_FORWARD_DECLARATION (GNB_PCI_SCAN_DATA); - -typedef SCAN_STATUS (*GNB_SCAN_CALLBACK) ( - IN PCI_ADDR Device, - IN OUT GNB_PCI_SCAN_DATA *ScanData - ); - -///Scan supporting data -typedef struct _GNB_PCI_SCAN_DATA { - GNB_SCAN_CALLBACK GnbScanCallback; ///< Callback for each found device - AMD_CONFIG_PARAMS *StdHeader; ///< Standard configuration header -} UnusedName; - -#define PCIE_CAP_ID 0x10 -#define PCIE_LINK_CAP_REGISTER 0x0C -#define PCIE_LINK_CTRL_REGISTER 0x10 -#define PCIE_DEVICE_CAP_REGISTER 0x04 -#define PCIE_ASPM_L1_SUPPORT_CAP BIT11 - -BOOLEAN -GnbLibPciIsDevicePresent ( - IN UINT32 Address, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -BOOLEAN -GnbLibPciIsBridgeDevice ( - IN UINT32 Address, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -BOOLEAN -GnbLibPciIsMultiFunctionDevice ( - IN UINT32 Address, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -BOOLEAN -GnbLibPciIsPcieDevice ( - IN UINT32 Address, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -UINT8 -GnbLibFindPciCapability ( - IN UINT32 Address, - IN UINT8 CapabilityId, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -VOID -GnbLibPciScan ( - IN PCI_ADDR Start, - IN PCI_ADDR End, - IN GNB_PCI_SCAN_DATA *ScanData - ); - -VOID -GnbLibPciScanSecondaryBus ( - IN PCI_ADDR Bridge, - IN OUT GNB_PCI_SCAN_DATA *ScanData - ); - -PCIE_DEVICE_TYPE -GnbLibGetPcieDeviceType ( - IN PCI_ADDR Device, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -VOID -GnbLibS3SaveConfigSpace ( - IN UINT32 Address, - IN UINT16 StartRegisterAddress, - IN UINT16 EndRegisterAddress, - IN ACCESS_WIDTH Width, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -#endif diff --git a/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbCommonLib/GnbLibPciAcc.c b/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbCommonLib/GnbLibPciAcc.c deleted file mode 100644 index a1758d0bf1..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbCommonLib/GnbLibPciAcc.c +++ /dev/null @@ -1,156 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * Service procedure to access PCI config space registers - * - * - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: GNB - * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $ - * - */ -/* -***************************************************************************** -* -* Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* *************************************************************************** -* -*/ - -/*---------------------------------------------------------------------------------------- - * M O D U L E S U S E D - *---------------------------------------------------------------------------------------- - */ -#include "Porting.h" -#include "AMD.h" -#include "amdlib.h" -#include "GnbLibPciAcc.h" -#include "S3SaveState.h" -#include "Filecode.h" -#define FILECODE PROC_GNB_MODULES_GNBCOMMONLIB_GNBLIBPCIACC_FILECODE -/*---------------------------------------------------------------------------------------- - * D E F I N I T I O N S A N D M A C R O S - *---------------------------------------------------------------------------------------- - */ - - -/*---------------------------------------------------------------------------------------- - * T Y P E D E F S A N D S T R U C T U R E S - *---------------------------------------------------------------------------------------- - */ - - -/*---------------------------------------------------------------------------------------- - * P R O T O T Y P E S O F L O C A L F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ - -/*----------------------------------------------------------------------------------------*/ -/** - * Write PCI registers - * - * - * - * @param[in] Address PCI address (as presented in PCI_ADDR.AddressValue) - * @param[in] Width Access width - * @param[in] Value Pointer to value - * @param[in] StdHeader Pointer to standard header - */ -VOID -GnbLibPciWrite ( - IN UINT32 Address, - IN ACCESS_WIDTH Width, - IN VOID *Value, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - PCI_ADDR PciAddress; - PciAddress.AddressValue = Address; - if (Width >= AccessS3SaveWidth8) { - S3_SAVE_PCI_WRITE (StdHeader, PciAddress, Width, Value); - } - LibAmdPciWrite (Width, PciAddress, Value, StdHeader); -} - -/*----------------------------------------------------------------------------------------*/ -/** - * Read PCI registers - * - * - * - * @param[in] Address PCI address (as presented in PCI_ADDR.AddressValue) - * @param[in] Width Access width - * @param[out] Value Pointer to value - * @param[in] StdHeader Pointer to standard header - */ - -VOID -GnbLibPciRead ( - IN UINT32 Address, - IN ACCESS_WIDTH Width, - OUT VOID *Value, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - PCI_ADDR PciAddress; - PciAddress.AddressValue = Address; - LibAmdPciRead (Width, PciAddress, Value, StdHeader); -} - - - -/*----------------------------------------------------------------------------------------*/ -/** - * Poll PCI reg - * - * - * - * @param[in] Address PCI address (as presented in PCI_ADDR.AddressValue) - * @param[in] Width Access width - * @param[in] Data Data to compare - * @param[in] DataMask AND mask - * @param[in] StdHeader Standard configuration header - */ - -VOID -GnbLibPciPoll ( - IN UINT32 Address, - IN ACCESS_WIDTH Width, - IN VOID *Data, - IN VOID *DataMask, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - PCI_ADDR PciAddress; - PciAddress.AddressValue = Address; - if (Width >= AccessS3SaveWidth8) { - S3_SAVE_PCI_POLL (StdHeader, PciAddress, Width, Data, DataMask, 0xffffffff); - } - LibAmdPciPoll (Width, PciAddress, Data, DataMask, 0xffffffff, StdHeader); -} diff --git a/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbCommonLib/GnbLibPciAcc.h b/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbCommonLib/GnbLibPciAcc.h deleted file mode 100644 index d2680f8117..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbCommonLib/GnbLibPciAcc.h +++ /dev/null @@ -1,73 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * Service procedure to access PCI config space registers - * - * - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: GNB - * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $ - * - */ -/* -***************************************************************************** -* -* Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* *************************************************************************** -* -*/ -#ifndef _GNBLIBPCIACC_H_ -#define _GNBLIBPCIACC_H_ - -VOID -GnbLibPciWrite ( - IN UINT32 Address, - IN ACCESS_WIDTH Width, - IN VOID *Value, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -VOID -GnbLibPciRead ( - IN UINT32 Address, - IN ACCESS_WIDTH Width, - OUT VOID *Value, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -VOID -GnbLibPciPoll ( - IN UINT32 Address, - IN ACCESS_WIDTH Width, - IN VOID *Data, - IN VOID *DataMask, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -#endif diff --git a/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbCommonLib/GnbLibStall.c b/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbCommonLib/GnbLibStall.c deleted file mode 100644 index c3f76ed992..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbCommonLib/GnbLibStall.c +++ /dev/null @@ -1,152 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * Various PCI service routines. - * - * - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: GNB - * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 01:16:51 -0800 (Wed, 22 Dec 2010) $ - * - */ -/* -***************************************************************************** -* -* Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* *************************************************************************** -* -*/ - - -#include "AGESA.h" -#include "amdlib.h" -#include "S3SaveState.h" -#include "Gnb.h" -#include "GnbLib.h" -#include "GnbLibStall.h" -#include "Filecode.h" -#define FILECODE PROC_GNB_MODULES_GNBCOMMONLIB_GNBLIBSTALL_FILECODE - - - - -/*----------------------------------------------------------------------------------------*/ -/* - * Stall and save to script table - * - * - * - * @param[in] Microsecond Stall time - * @param[in] StdHeader Standard configuration header - */ - -VOID -GnbLibStallS3Save ( - IN UINT32 Microsecond, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - S3_SAVE_DISPATCH (StdHeader, GnbLibStallS3Script_ID, sizeof (Microsecond), &Microsecond); - GnbLibStall (Microsecond, StdHeader); -} - - -/*----------------------------------------------------------------------------------------*/ -/* - * Stall - * - * - * - * @param[in] Microsecond Stall time - * @param[in] StdHeader Standard configuration header - */ - -VOID -GnbLibStall ( - IN UINT32 Microsecond, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - UINT32 TimeStampStart; - UINT32 TimeStampDelta; - UINT32 TimeStampCurrent; - - TimeStampStart = GnbLibTimeStamp (StdHeader); - do { - TimeStampCurrent = GnbLibTimeStamp (StdHeader); - TimeStampDelta = ((TimeStampCurrent > TimeStampStart) ? (TimeStampCurrent - TimeStampStart) : (0xffffffffull - TimeStampStart + TimeStampCurrent)); - } while (TimeStampDelta < Microsecond); -} - -/*----------------------------------------------------------------------------------------*/ -/** - * Stall S3 scrept - * - * - * - * @param[in] StdHeader Standard configuration header - * @param[in] ContextLength Context Length (not used) - * @param[in] Context Context pointer (not used) - */ -VOID -GnbLibStallS3Script ( - IN AMD_CONFIG_PARAMS *StdHeader, - IN UINT16 ContextLength, - IN VOID* Context - ) -{ - GnbLibStall (* ((UINT32*) Context), StdHeader); -} -/*----------------------------------------------------------------------------------------*/ -/* - * Time stamp in us - * - * - * - * @param[in] StdHeader Standard configuration header - * @retval TRUE Device is a bridge - * @retval FALSE Device is not a bridge - */ - -UINT32 -GnbLibTimeStamp ( - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - UINT32 TimeStamp; - GnbLibPciIndirectRead ( - MAKE_SBDFO (0, 0, 0, 0, 0xE0), - 0x13080F0, - AccessWidth32, - &TimeStamp, - StdHeader - ); - return TimeStamp; -} - diff --git a/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbCommonLib/GnbLibStall.h b/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbCommonLib/GnbLibStall.h deleted file mode 100644 index ad39c2f8c2..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbCommonLib/GnbLibStall.h +++ /dev/null @@ -1,73 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * Various PCI service routines. - * - * - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: GNB - * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 01:16:51 -0800 (Wed, 22 Dec 2010) $ - * - */ -/* -***************************************************************************** -* -* Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* *************************************************************************** -* -*/ - -#ifndef _GNBLIBSTALL_H_ -#define _GNBLIBSTALL_H_ - -VOID -GnbLibStallS3Save ( - IN UINT32 Microsecond, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -VOID -GnbLibStall ( - IN UINT32 Microsecond, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -UINT32 -GnbLibTimeStamp ( - IN AMD_CONFIG_PARAMS *StdHeader - ); - -VOID -GnbLibStallS3Script ( - IN AMD_CONFIG_PARAMS *StdHeader, - IN UINT16 ContextLength, - IN VOID* Context - ); - -#endif diff --git a/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbCommonLib/GnbTable.c b/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbCommonLib/GnbTable.c deleted file mode 100644 index 7de0d95a37..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbCommonLib/GnbTable.c +++ /dev/null @@ -1,310 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * Service procedure to access PCI config space registers - * - * - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: GNB - * @e \$Revision: 39623 $ @e \$Date: 2010-10-13 13:37:42 -0700 (Wed, 13 Oct 2010) $ - * - */ -/* -***************************************************************************** -* -* Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* *************************************************************************** -* -*/ - -/*---------------------------------------------------------------------------------------- - * M O D U L E S U S E D - *---------------------------------------------------------------------------------------- - */ -#include "AGESA.h" -#include "Ids.h" -#include "amdlib.h" -#include "cpuFamilyTranslation.h" -#include "Gnb.h" -#include "GnbLib.h" -#include "GnbLibStall.h" -#include "GnbTable.h" -#include "Filecode.h" -#define FILECODE PROC_GNB_MODULES_GNBCOMMONLIB_GNBTABLE_FILECODE -/*---------------------------------------------------------------------------------------- - * D E F I N I T I O N S A N D M A C R O S - *---------------------------------------------------------------------------------------- - */ - - -/*---------------------------------------------------------------------------------------- - * T Y P E D E F S A N D S T R U C T U R E S - *---------------------------------------------------------------------------------------- - */ - - -/*---------------------------------------------------------------------------------------- - * P R O T O T Y P E S O F L O C A L F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ - -/*----------------------------------------------------------------------------------------*/ -/** - * Process table - * - * - * - * @param[in] Table Table pointer - * @param[in] Property Property - * @param[in] Flags Flags - * @param[in] Protocol Register access protocol - * @param[in] StdHeader Standard configuration header - */ -AGESA_STATUS -GnbProcessTable ( - IN GNB_TABLE *Table, - IN UINT32 Property, - IN UINT32 Flags, - IN GNB_REGISTER_PROTOCOL *Protocol, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - return GnbProcessTableExt (0, 0, Table, Property, Flags, Protocol, StdHeader); -} - -/*----------------------------------------------------------------------------------------*/ -/** - * Process table - * - * @param[in] Socket Socket - * @param[in] Module Module - * @param[in] Table Table pointer - * @param[in] Property Property - * @param[in] Flags Flags - * @param[in] Protocol Register access protocol - * @param[in] StdHeader Standard configuration header - */ - -AGESA_STATUS -GnbProcessTableExt ( - IN UINT32 Socket, - IN UINT8 Module, - IN GNB_TABLE *Table, - IN UINT32 Property, - IN UINT32 Flags, - IN GNB_REGISTER_PROTOCOL *Protocol, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - UINT8 *EntryPointer; - UINT64 Data; - UINT64 Temp; - UINT64 Mask; - UINT32 WriteAccFlags; - CPU_LOGICAL_ID LogicalId; - IDS_HDT_CONSOLE (GNB_TRACE, "GnbProcessTableExt Enter\n"); - IDS_HDT_CONSOLE (GNB_TRACE, " Property - 0x%08x\n", Property); - GetLogicalIdOfSocket (Socket, &LogicalId, StdHeader); - EntryPointer = (UINT8 *) Table; - WriteAccFlags = 0; - if ((Flags & GNB_TABLE_FLAGS_FORCE_S3_SAVE) != 0) { - WriteAccFlags |= GNB_REG_ACC_FLAG_S3SAVE; - } - while (*EntryPointer != GnbEntryTerminate) { - Data = 0; - Temp = 0; - switch (*EntryPointer) { - case GnbEntryWr: - Protocol->Write ( - ((GNB_TABLE_ENTRY_WR*) EntryPointer)->RegisterSpaceType, - ((GNB_TABLE_ENTRY_WR*) EntryPointer)->Address, - &((GNB_TABLE_ENTRY_WR*) EntryPointer)->Value, - WriteAccFlags, - StdHeader - ); - EntryPointer = EntryPointer + sizeof (GNB_TABLE_ENTRY_WR); - break; - case GnbEntryPropertyWr: - if ((Property & ((GNB_TABLE_ENTRY_PROPERTY_WR *) EntryPointer)->Property) != 0) { - Protocol->Write ( - ((GNB_TABLE_ENTRY_PROPERTY_WR *) EntryPointer)->RegisterSpaceType, - ((GNB_TABLE_ENTRY_PROPERTY_WR *) EntryPointer)->Address, - &((GNB_TABLE_ENTRY_PROPERTY_WR *) EntryPointer)->Value, - WriteAccFlags, - StdHeader - ); - } - EntryPointer = EntryPointer + sizeof (GNB_TABLE_ENTRY_PROPERTY_WR); - break; - case GnbEntryFullWr: - if ((Property & ((GNB_TABLE_ENTRY_FULL_WR*) EntryPointer)->Property) != 0) { - if ((LogicalId.Revision & ((GNB_TABLE_ENTRY_FULL_WR*) EntryPointer)->Revision) != 0) { - Protocol->Write ( - ((GNB_TABLE_ENTRY_FULL_WR*) EntryPointer)->RegisterSpaceType, - ((GNB_TABLE_ENTRY_FULL_WR*) EntryPointer)->Address, - &((GNB_TABLE_ENTRY_FULL_WR*) EntryPointer)->Value, - WriteAccFlags, - StdHeader - ); - } - } - EntryPointer = EntryPointer + sizeof (GNB_TABLE_ENTRY_FULL_WR); - break; - case GnbEntryRmw: - Protocol->Read ( - ((GNB_TABLE_ENTRY_RMW*) EntryPointer)->RegisterSpaceType, - ((GNB_TABLE_ENTRY_RMW*) EntryPointer)->Address, - &Data, - 0, - StdHeader - ); - Data = (Data & (~ (UINT64) ((GNB_TABLE_ENTRY_RMW*) EntryPointer)->AndMask)) | ((GNB_TABLE_ENTRY_RMW*) EntryPointer)->OrMask; - Protocol->Write ( - ((GNB_TABLE_ENTRY_RMW*) EntryPointer)->RegisterSpaceType, - ((GNB_TABLE_ENTRY_RMW*) EntryPointer)->Address, - &Data, - WriteAccFlags, - StdHeader - ); - EntryPointer = EntryPointer + sizeof (GNB_TABLE_ENTRY_RMW); - break; - case GnbEntryPropertyRmw: - if ((Property & ((GNB_TABLE_ENTRY_PROPERTY_RMW *) EntryPointer)->Property) != 0) { - Protocol->Read ( - ((GNB_TABLE_ENTRY_PROPERTY_RMW *) EntryPointer)->RegisterSpaceType, - ((GNB_TABLE_ENTRY_PROPERTY_RMW *) EntryPointer)->Address, - &Data, - 0, - StdHeader - ); - Data = (Data & (~ (UINT64) ((GNB_TABLE_ENTRY_PROPERTY_RMW *) EntryPointer)->AndMask)) | ((GNB_TABLE_ENTRY_PROPERTY_RMW *) EntryPointer)->OrMask; - Protocol->Write ( - ((GNB_TABLE_ENTRY_PROPERTY_RMW *) EntryPointer)->RegisterSpaceType, - ((GNB_TABLE_ENTRY_PROPERTY_RMW *) EntryPointer)->Address, - &Data, - WriteAccFlags, - StdHeader - ); - } - EntryPointer = EntryPointer + sizeof (GNB_TABLE_ENTRY_PROPERTY_RMW); - break; - case GnbEntryFullRmw: - if ((Property & ((GNB_TABLE_ENTRY_FULL_WR *) EntryPointer)->Property) != 0) { - if ((LogicalId.Revision & ((GNB_TABLE_ENTRY_FULL_WR *) EntryPointer)->Revision) != 0) { - Protocol->Read ( - ((GNB_TABLE_ENTRY_FULL_RMW *) EntryPointer)->RegisterSpaceType, - ((GNB_TABLE_ENTRY_FULL_RMW *) EntryPointer)->Address, - &Data, - 0, - StdHeader - ); - Data = (Data & (~ (UINT64) ((GNB_TABLE_ENTRY_FULL_RMW *) EntryPointer)->AndMask)) | ((GNB_TABLE_ENTRY_FULL_RMW *) EntryPointer)->OrMask; - Protocol->Write ( - ((GNB_TABLE_ENTRY_FULL_RMW *) EntryPointer)->RegisterSpaceType, - ((GNB_TABLE_ENTRY_FULL_RMW *) EntryPointer)->Address, - &Data, - WriteAccFlags, - StdHeader - ); - } - } - EntryPointer = EntryPointer + sizeof (GNB_TABLE_ENTRY_FULL_RMW); - break; - case GnbEntryPoll: - do { - Protocol->Read ( - ((GNB_TABLE_ENTRY_POLL *) EntryPointer)->RegisterSpaceType, - ((GNB_TABLE_ENTRY_POLL *) EntryPointer)->Address, - &Data, - 0, - StdHeader - ); - } while ((Data & ((GNB_TABLE_ENTRY_POLL*) EntryPointer)->AndMask) != ((GNB_TABLE_ENTRY_POLL*) EntryPointer)->CompareValue); - EntryPointer = EntryPointer + sizeof (GNB_TABLE_ENTRY_POLL); - break; - case GnbEntryPropertyPoll: - if ((Property & ((GNB_TABLE_ENTRY_PROPERTY_POLL *) EntryPointer)->Property) != 0) { - do { - Protocol->Read ( - ((GNB_TABLE_ENTRY_PROPERTY_POLL *) EntryPointer)->RegisterSpaceType, - ((GNB_TABLE_ENTRY_PROPERTY_POLL *) EntryPointer)->Address, - &Data, - 0, - StdHeader - ); - } while ((Data & ((GNB_TABLE_ENTRY_PROPERTY_POLL *) EntryPointer)->AndMask) != ((GNB_TABLE_ENTRY_PROPERTY_POLL *) EntryPointer)->CompareValue); - } - EntryPointer = EntryPointer + sizeof (GNB_TABLE_ENTRY_PROPERTY_POLL); - break; - case GnbEntryCopy: - Protocol->Read ( - ((GNB_TABLE_ENTRY_COPY*) EntryPointer)->SrcRegisterSpaceType, - ((GNB_TABLE_ENTRY_COPY*) EntryPointer)->SrcAddress, - &Data, - 0, - StdHeader - ); - Mask = (1ull << ((GNB_TABLE_ENTRY_COPY*) EntryPointer)->SrcFieldWidth) - 1; - Data = (Data >> ((GNB_TABLE_ENTRY_COPY*) EntryPointer)->SrcFieldOffset) & Mask; - Protocol->Read ( - ((GNB_TABLE_ENTRY_COPY*) EntryPointer)->DestRegisterSpaceType, - ((GNB_TABLE_ENTRY_COPY*) EntryPointer)->DestAddress, - &Temp, - 0, - StdHeader - ); - Mask = (1ull << ((GNB_TABLE_ENTRY_COPY*) EntryPointer)->DestFieldWidth) - 1; - Temp = Temp & ( ~ (Mask << ((GNB_TABLE_ENTRY_COPY*) EntryPointer)->DestFieldOffset)); - Temp = Temp | ((Data & Mask) << ((GNB_TABLE_ENTRY_COPY*) EntryPointer)->DestFieldOffset); - Protocol->Write ( - ((GNB_TABLE_ENTRY_COPY*) EntryPointer)->DestRegisterSpaceType, - ((GNB_TABLE_ENTRY_COPY*) EntryPointer)->DestAddress, - &Temp, - WriteAccFlags, - StdHeader - ); - EntryPointer = EntryPointer + sizeof (GNB_TABLE_ENTRY_COPY); - break; - case GnbEntryStall: - if ((WriteAccFlags & GNB_TABLE_FLAGS_FORCE_S3_SAVE) != 0) { - GnbLibStallS3Save (((GNB_TABLE_ENTRY_STALL*) EntryPointer)->Microsecond, StdHeader); - } else { - GnbLibStall (((GNB_TABLE_ENTRY_STALL*) EntryPointer)->Microsecond, StdHeader); - } - EntryPointer = EntryPointer + sizeof (GNB_TABLE_ENTRY_STALL); - break; - default: - ASSERT (FALSE); - IDS_HDT_CONSOLE (NB_MISC, " ERROR!!! Regiter table parse\n"); - return AGESA_ERROR; - } - } - IDS_HDT_CONSOLE (GNB_TRACE, "GnbProcessTableExt Exit\n"); - return AGESA_SUCCESS; -} diff --git a/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbCommonLib/GnbTable.h b/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbCommonLib/GnbTable.h deleted file mode 100644 index ea12112fe2..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbCommonLib/GnbTable.h +++ /dev/null @@ -1,225 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * Service procedure to access PCI config space registers - * - * - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: GNB - * @e \$Revision: 39623 $ @e \$Date: 2010-10-13 13:37:42 -0700 (Wed, 13 Oct 2010) $ - * - */ -/* -***************************************************************************** -* -* Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* *************************************************************************** -* -*/ -#ifndef _GNBTABLE_H_ -#define _GNBTABLE_H_ - - -#pragma pack (push, 1) - -#define GNB_TABLE_FLAGS_FORCE_S3_SAVE 0x00000001 - -typedef UINT8 GNB_TABLE; - -#define __DATA(x) x - -#define _DATA32(Data) (__DATA(Data)) & 0xFF, ((__DATA(Data)) >> 8) & 0xFF, ((__DATA(Data)) >> 16) & 0xFF, ((__DATA(Data)) >> 24) & 0xFF - -/// Entry type -typedef enum { - GnbEntryWr, ///< Write register - GnbEntryPropertyWr, ///< Write register check property - GnbEntryFullWr, ///< Write Rgister check revision and property - GnbEntryRmw, ///< Read Modify Write register - GnbEntryPropertyRmw, ///< Read Modify Write register check property - GnbEntryFullRmw, ///< Read Modify Write register check revision and property - GnbEntryPoll, ///< Poll register - GnbEntryPropertyPoll, ///< Poll register check property - GnbEntryCopy, ///< Copy field from one register to another - GnbEntryStall, ///< Copy field from one register to another - GnbEntryTerminate = 0xFF ///< Terminate table -} GNB_TABLE_ENTRY_TYPE; - -#define GNB_ENTRY_WR(RegisterSpaceType, Address, Value) \ - GnbEntryWr, RegisterSpaceType, _DATA32 (Address), _DATA32 (Value) - -/// Write register entry -typedef struct { - UINT8 EntryType; ///< Entry type - UINT8 RegisterSpaceType; ///< Register space - UINT32 Address; ///< Register address - UINT32 Value; ///< Value -} GNB_TABLE_ENTRY_WR; - -#define GNB_ENTRY_PROPERTY_WR(Property, RegisterSpaceType, Address, Value) \ - GnbEntryPropertyWr, _DATA32 (Property), RegisterSpaceType, _DATA32 (Address), _DATA32 (Value) - -/// Write register entry -typedef struct { - UINT8 EntryType; ///< Entry type - UINT32 Property; ///< Property - UINT8 RegisterSpaceType; ///< Register space - UINT32 Address; ///< Register address - UINT32 Value; ///< Value -} GNB_TABLE_ENTRY_PROPERTY_WR; - - -#define GNB_ENTRY_RMW(RegisterSpaceType, Address, AndMask, OrMask) \ - GnbEntryRmw, RegisterSpaceType, _DATA32 (Address), _DATA32 (AndMask), _DATA32 (OrMask) - -/// Read Modify Write register entry -typedef struct { - UINT8 EntryType; ///< Entry type - UINT8 RegisterSpaceType; ///< Register space - UINT32 Address; ///< Register address - UINT32 AndMask; ///< And Mask - UINT32 OrMask; ///< Or Mask -} GNB_TABLE_ENTRY_RMW; - -#define GNB_ENTRY_FULL_WR(Property, Revision, RegisterSpaceType, Address, Value) \ - GnbEntryFullWr, _DATA32 (Property), _DATA64 (Revision), RegisterSpaceType, _DATA32 (Address), _DATA32 (Value) - -/// Write register entry -typedef struct { - UINT8 EntryType; ///< Entry type - UINT32 Property; ///< Property - UINT64 Revision; ///< Revision - UINT8 RegisterSpaceType; ///< Register space - UINT32 Address; ///< Register address - UINT32 Value; ///< Value -} GNB_TABLE_ENTRY_FULL_WR; - - -#define GNB_ENTRY_PROPERTY_RMW(Property, RegisterSpaceType, Address, AndMask, OrMask) \ - GnbEntryPropertyRmw, _DATA32 (Property), RegisterSpaceType, _DATA32 (Address), _DATA32 (AndMask), _DATA32 (OrMask) - -/// Read Modify Write register entry -typedef struct { - UINT8 EntryType; ///< Entry type - UINT32 Property; ///< Property - UINT8 RegisterSpaceType; ///< Register space - UINT32 Address; ///< Register address - UINT32 AndMask; ///< End Mask - UINT32 OrMask; ///< Or Mask -} GNB_TABLE_ENTRY_PROPERTY_RMW; - -#define GNB_ENTRY_FULL_RMW(Property, Revision, RegisterSpaceType, Address, AndMask, OrMask) \ - GnbEntryFullRmw, _DATA32 (Property), _DATA64 (Revision), RegisterSpaceType, _DATA32 (Address), _DATA32 (AndMask), _DATA32 (OrMask) - -/// Read Modify Write register entry -typedef struct { - UINT8 EntryType; ///< Entry type - UINT32 Property; ///< Property - UINT64 Revision; ///< Revision - UINT8 RegisterSpaceType; ///< Register space - UINT32 Address; ///< Register address - UINT32 AndMask; ///< End Mask - UINT32 OrMask; ///< Or Mask -} GNB_TABLE_ENTRY_FULL_RMW; - -#define GNB_ENTRY_POLL(RegisterSpaceType, Address, AndMask, CompareValue) \ - GnbEntryPoll, RegisterSpaceType, _DATA32 (Address), _DATA32 (AndMask), _DATA32 (CompareValue) -/// Poll register entry -typedef struct { - UINT8 EntryType; ///< Entry type - UINT8 RegisterSpaceType; ///< Register space - UINT32 Address; ///< Register address - UINT32 AndMask; ///< End mask - UINT32 CompareValue; ///< Compare value -} GNB_TABLE_ENTRY_POLL; - -#define GNB_ENTRY_PROPERTY_POLL(Property, RegisterSpaceType, Address, AndMask, CompareValue) \ - GnbEntryPropertyPoll, _DATA32 (Property), RegisterSpaceType, _DATA32 (Address), _DATA32 (AndMask), _DATA32 (CompareValue) -/// Poll register entry -typedef struct { - UINT8 EntryType; ///< Entry type - UINT32 Property; ///< Property - UINT8 RegisterSpaceType; ///< Register space - UINT32 Address; ///< Register address - UINT32 AndMask; ///< End mask - UINT32 CompareValue; ///< Compare value -} GNB_TABLE_ENTRY_PROPERTY_POLL; - - -#define GNB_ENTRY_COPY(DestRegSpaceType, DestAddress, DestFieldOffset, DestFieldWidth, SrcRegisterSpaceType, SrcAddress, SrcFieldOffset, SrcFieldWidth) \ - GnbEntryCopy, DestRegSpaceType, _DATA32 (DestAddress), DestFieldOffset, DestFieldWidth, SrcRegisterSpaceType, _DATA32 (SrcAddress), SrcFieldOffset, SrcFieldWidth - -/// Copy regster entry -typedef struct { - UINT8 EntryType; ///< Entry type - UINT8 DestRegisterSpaceType; ///< Register space - UINT32 DestAddress; ///< Register address - UINT8 DestFieldOffset; ///< Field Offset - UINT8 DestFieldWidth; ///< Field Width - UINT8 SrcRegisterSpaceType; ///< Register space - UINT32 SrcAddress; ///< Register address - UINT8 SrcFieldOffset; ///< Field Offset - UINT8 SrcFieldWidth; ///< Field Width -} GNB_TABLE_ENTRY_COPY; - -#define GNB_ENTRY_STALL(Microsecond) \ - GnbEntryStall, _DATA32 (Microsecond) - -/// Write register entry -typedef struct { - UINT8 EntryType; ///< Entry type - UINT32 Microsecond; ///< Value -} GNB_TABLE_ENTRY_STALL; - -#define GNB_ENTRY_TERMINATE GnbEntryTerminate - -AGESA_STATUS -GnbProcessTableExt ( - IN UINT32 Socket, - IN UINT8 Module, - IN GNB_TABLE *Table, - IN UINT32 Property, - IN UINT32 Flags, - IN GNB_REGISTER_PROTOCOL *Protocol, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -AGESA_STATUS -GnbProcessTable ( - IN GNB_TABLE *Table, - IN UINT32 Property, - IN UINT32 Flags, - IN GNB_REGISTER_PROTOCOL *Protocol, - IN AMD_CONFIG_PARAMS *StdHeader - ); - - -#pragma pack (pop) - -#endif diff --git a/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbCommonLib/Makefile.inc b/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbCommonLib/Makefile.inc deleted file mode 100644 index 8965cbed69..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbCommonLib/Makefile.inc +++ /dev/null @@ -1,8 +0,0 @@ -libagesa-y += GnbLib.c -libagesa-y += GnbLibCpuAcc.c -libagesa-y += GnbLibHeap.c -libagesa-y += GnbLibIoAcc.c -libagesa-y += GnbLibMemAcc.c -libagesa-y += GnbLibPci.c -libagesa-y += GnbLibPciAcc.c -libagesa-y += GnbLibStall.c diff --git a/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbGfxConfig/GfxConfigEnv.c b/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbGfxConfig/GfxConfigEnv.c deleted file mode 100644 index 05fb4ea8ff..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbGfxConfig/GfxConfigEnv.c +++ /dev/null @@ -1,189 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * Initialize GFX configuration data structure. - * - * - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: GNB - * @e \$Revision: 39255 $ @e \$Date: 2010-10-08 11:27:41 -0700 (Fri, 08 Oct 2010) $ - * - */ -/* -***************************************************************************** -* -* Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* *************************************************************************** -* -*/ - -/*---------------------------------------------------------------------------------------- - * M O D U L E S U S E D - *---------------------------------------------------------------------------------------- - */ -#include "AGESA.h" -#include "amdlib.h" -#include "Ids.h" -#include "heapManager.h" -#include "Gnb.h" -#include "GnbGfx.h" -#include "GnbGfxConfig.h" -#include "GnbCommonLib.h" -#include "GfxConfigPost.h" -#include "GfxConfigData.h" -#include "GnbGfxInitLibV1.h" -#include "OptionGnb.h" -#include "Filecode.h" -#define FILECODE PROC_GNB_MODULES_GNBGFXCONFIG_GFXCONFIGENV_FILECODE -/*---------------------------------------------------------------------------------------- - * D E F I N I T I O N S A N D M A C R O S - *---------------------------------------------------------------------------------------- - */ - -extern BUILD_OPT_CFG UserOptions; -extern GNB_BUILD_OPTIONS GnbBuildOptions; - -/*---------------------------------------------------------------------------------------- - * T Y P E D E F S A N D S T R U C T U R E S - *---------------------------------------------------------------------------------------- - */ - - -/*---------------------------------------------------------------------------------------- - * P R O T O T Y P E S O F L O C A L F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ - - - -/*----------------------------------------------------------------------------------------*/ -/** - * Get UMA info - * - * UMA info stored on heap by memory module - * - * @param[out] UmaInfo Pointer to UMA info structure - * @param[in] StdHeader Standard configuration header - */ - -VOID -GfxGetUmaInfo ( - OUT UMA_INFO *UmaInfo, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - UMA_INFO *MemUmaInfo; - - MemUmaInfo = GnbLocateHeapBuffer (AMD_UMA_INFO_HANDLE, StdHeader); - if (MemUmaInfo == NULL) { - LibAmdMemFill (UmaInfo, 0x00, sizeof (UMA_INFO), StdHeader); - UmaInfo->UmaMode = UMA_NONE; - } else { - LibAmdMemCopy (UmaInfo, MemUmaInfo, sizeof (UMA_INFO), StdHeader); - if ((UmaInfo->UmaBase == 0) || (UmaInfo->UmaSize == 0)) { - UmaInfo->UmaMode = UMA_NONE; - } - } -} - -/*----------------------------------------------------------------------------------------*/ -/** - * Locate UMA configuration data - * - * - * - * @param[in] StdHeader Standard configuration header - * @param[in,out] Gfx Pointer to GFX configuration - * @retval AGESA_STATUS Data located - * @retval AGESA_FATA Data not found - */ - -AGESA_STATUS -GfxLocateConfigData ( - IN AMD_CONFIG_PARAMS *StdHeader, - OUT GFX_PLATFORM_CONFIG **Gfx - ) -{ - *Gfx = GnbLocateHeapBuffer (AMD_GFX_PLATFORM_CONFIG_HANDLE, StdHeader); - if (*Gfx == NULL) { - IDS_ERROR_TRAP; - return AGESA_FATAL; - } - (*Gfx)->StdHeader = StdHeader; - return AGESA_SUCCESS; -} - - - -/*----------------------------------------------------------------------------------------*/ -/** - * Update GFX config info at ENV - * - * - * - * @param[in] StdHeader Standard configuration header - * @retval AGESA_STATUS Always succeeds - */ - -AGESA_STATUS -GfxConfigEnvInterface ( - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - - AMD_ENV_PARAMS *EnvParamsPtr; - GFX_PLATFORM_CONFIG *Gfx; - AGESA_STATUS Status; - IDS_HDT_CONSOLE (GNB_TRACE, "GfxConfigEnvInterface Enter\n"); - Status = GfxLocateConfigData (StdHeader, &Gfx); - ASSERT (Status == AGESA_SUCCESS); - if (Status == AGESA_SUCCESS) { - EnvParamsPtr = (AMD_ENV_PARAMS *) StdHeader; - Gfx->Gnb3dStereoPinIndex = EnvParamsPtr->GnbEnvConfiguration.Gnb3dStereoPinIndex; - Gfx->LvdsSpreadSpectrum = EnvParamsPtr->GnbEnvConfiguration.LvdsSpreadSpectrum; - Gfx->LvdsSpreadSpectrumRate = EnvParamsPtr->GnbEnvConfiguration.LvdsSpreadSpectrumRate; - Gfx->LvdsPowerOnSeqDigonToDe = EnvParamsPtr->GnbEnvConfiguration.LvdsPowerOnSeqDigonToDe; - Gfx->LvdsPowerOnSeqDeToVaryBl = EnvParamsPtr->GnbEnvConfiguration.LvdsPowerOnSeqDeToVaryBl; - Gfx->LvdsPowerOnSeqDeToDigon = EnvParamsPtr->GnbEnvConfiguration.LvdsPowerOnSeqDeToDigon; - Gfx->LvdsPowerOnSeqVaryBlToDe = EnvParamsPtr->GnbEnvConfiguration.LvdsPowerOnSeqVaryBlToDe; - Gfx->LvdsPowerOnSeqOnToOffDelay = EnvParamsPtr->GnbEnvConfiguration.LvdsPowerOnSeqOnToOffDelay; - Gfx->LvdsPowerOnSeqVaryBlToBlon = EnvParamsPtr->GnbEnvConfiguration.LvdsPowerOnSeqVaryBlToBlon; - Gfx->LvdsPowerOnSeqBlonToVaryBl = EnvParamsPtr->GnbEnvConfiguration.LvdsPowerOnSeqBlonToVaryBl; - Gfx->LvdsMaxPixelClockFreq = EnvParamsPtr->GnbEnvConfiguration.LvdsMaxPixelClockFreq; - Gfx->LcdBitDepthControlValue = EnvParamsPtr->GnbEnvConfiguration.LcdBitDepthControlValue; - Gfx->Lvds24bbpPanelMode = EnvParamsPtr->GnbEnvConfiguration.Lvds24bbpPanelMode; - Gfx->PcieRefClkSpreadSpectrum = EnvParamsPtr->GnbEnvConfiguration.PcieRefClkSpreadSpectrum; - GfxGetUmaInfo (&Gfx->UmaInfo, StdHeader); - } - GNB_DEBUG_CODE ( - GfxConfigDebugDump (Gfx); - ); - IDS_HDT_CONSOLE (GNB_TRACE, "GfxConfigEnvInterface Exit [0x%x]\n", Status); - return Status; -} diff --git a/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbGfxConfig/GfxConfigPost.c b/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbGfxConfig/GfxConfigPost.c deleted file mode 100644 index 0b41069d81..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbGfxConfig/GfxConfigPost.c +++ /dev/null @@ -1,177 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * Initialize GFX configuration data structure. - * - * - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: GNB - * @e \$Revision: 39255 $ @e \$Date: 2010-10-08 11:27:41 -0700 (Fri, 08 Oct 2010) $ - * - */ -/* -***************************************************************************** -* -* Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* *************************************************************************** -* -*/ - -/*---------------------------------------------------------------------------------------- - * M O D U L E S U S E D - *---------------------------------------------------------------------------------------- - */ -#include "AGESA.h" -#include "amdlib.h" -#include "Ids.h" -#include "heapManager.h" -#include "Gnb.h" -#include "GnbGfx.h" -#include "GnbCommonLib.h" -#include "GfxConfigPost.h" -#include "OptionGnb.h" -#include "Filecode.h" -#define FILECODE PROC_GNB_MODULES_GNBGFXCONFIG_GFXCONFIGPOST_FILECODE -/*---------------------------------------------------------------------------------------- - * D E F I N I T I O N S A N D M A C R O S - *---------------------------------------------------------------------------------------- - */ - -extern BUILD_OPT_CFG UserOptions; -extern GNB_BUILD_OPTIONS GnbBuildOptions; - -/*---------------------------------------------------------------------------------------- - * T Y P E D E F S A N D S T R U C T U R E S - *---------------------------------------------------------------------------------------- - */ - - -/*---------------------------------------------------------------------------------------- - * P R O T O T Y P E S O F L O C A L F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ - - -/*----------------------------------------------------------------------------------------*/ -/** - * Allocate UMA configuration data - * - * - * - * @param[in] StdHeader Standard configuration header - * @retval AGESA_STATUS Always succeeds - */ - -AGESA_STATUS -GfxConfigPostInterface ( - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - GFX_PLATFORM_CONFIG *Gfx; - AMD_POST_PARAMS *PostParamsPtr; - AGESA_STATUS Status; - PostParamsPtr = (AMD_POST_PARAMS *)StdHeader; - Status = AGESA_SUCCESS; - IDS_HDT_CONSOLE (GNB_TRACE, "GfxConfigPostInterface Enter\n"); - Gfx = GnbAllocateHeapBuffer (AMD_GFX_PLATFORM_CONFIG_HANDLE, sizeof (GFX_PLATFORM_CONFIG), StdHeader); - ASSERT (Gfx != NULL); - if (Gfx != NULL) { - LibAmdMemFill (Gfx, 0x00, sizeof (GFX_PLATFORM_CONFIG), StdHeader); - if (GnbBuildOptions.IgfxModeAsPcieEp) { - Gfx->GfxControllerMode = GfxControllerPcieEndpointMode; - Gfx->GfxPciAddress.AddressValue = MAKE_SBDFO (0, 0, 1, 0, 0); - } else { - Gfx->GfxControllerMode = GfxControllerLegacyBridgeMode; - Gfx->GfxPciAddress.AddressValue = MAKE_SBDFO (0, 1, 5, 0, 0); - } - Gfx->StdHeader = StdHeader; - Gfx->GnbHdAudio = PostParamsPtr->PlatformConfig.GnbHdAudio; - Gfx->AbmSupport = PostParamsPtr->PlatformConfig.AbmSupport; - Gfx->DynamicRefreshRate = PostParamsPtr->PlatformConfig.DynamicRefreshRate; - Gfx->LcdBackLightControl = PostParamsPtr->PlatformConfig.LcdBackLightControl; - Gfx->ForceGfxMode = GfxEnableAuto; - Gfx->AmdPlatformType = UserOptions.CfgAmdPlatformType; - Gfx->GmcClockGating = OptionEnabled; - Gfx->GmcPowerGating = GnbBuildOptions.GmcPowerGateStutterOnly ? GmcPowerGatingStutterOnly : GmcPowerGatingWidthStutter; - Gfx->UmaSteering = Garlic; - GNB_DEBUG_CODE ( - GfxConfigDebugDump (Gfx); - ); - } else { - Status = AGESA_ERROR; - } - IDS_OPTION_HOOK (IDS_GNB_PLATFORMCFG_OVERRIDE, Gfx, StdHeader); - IDS_HDT_CONSOLE (GNB_TRACE, "GfxConfigPostInterface Exit [0x%x]\n", Status); - return Status; -} - - -/*----------------------------------------------------------------------------------------*/ -/** - * Debug dump - * - * - * - * @param[in] Gfx Pointer to GFX configuration - */ - -VOID -GfxConfigDebugDump ( - IN GFX_PLATFORM_CONFIG *Gfx - ) -{ - IDS_HDT_CONSOLE (GFX_MISC, "<-------------- GFX Config Start ------------->\n"); - IDS_HDT_CONSOLE (GFX_MISC, " HD Audio - %s\n", (Gfx->GnbHdAudio == 0) ? "Disabled" : "Enabled"); - IDS_HDT_CONSOLE (GFX_MISC, " DynamicRefreshRate - 0x%x\n", Gfx->DynamicRefreshRate); - IDS_HDT_CONSOLE (GFX_MISC, " LcdBackLightControl - 0x%x\n", Gfx->LcdBackLightControl); - IDS_HDT_CONSOLE (GFX_MISC, " AbmSupport - %s\n", (Gfx->AbmSupport == 0) ? "Disabled" : "Enabled"); - IDS_HDT_CONSOLE (GFX_MISC, " GmcClockGating - %s\n", (Gfx->GmcClockGating == 0) ? "Disabled" : "Enabled"); - IDS_HDT_CONSOLE (GFX_MISC, " GmcPowerGating - %s\n", - (Gfx->GmcPowerGating == GmcPowerGatingDisabled) ? "Disabled" : ( - (Gfx->GmcPowerGating == GmcPowerGatingStutterOnly) ? "GmcPowerGatingStutterOnly" : ( - (Gfx->GmcPowerGating == GmcPowerGatingWidthStutter) ? "GmcPowerGatingWidthStutter" : "Unknown")) - ); - IDS_HDT_CONSOLE (GFX_MISC, " UmaSteering - %s\n", - (Gfx->UmaSteering == Onion) ? "Onion" : ( - (Gfx->UmaSteering == Garlic) ? "Garlic" : "Unknown") - ); - IDS_HDT_CONSOLE (GFX_MISC, " ForceGfxMode - %s\n", - (Gfx->ForceGfxMode == GfxEnableAuto) ? "Auto" : ( - (Gfx->ForceGfxMode == GfxEnableForcePrimary) ? "Force Primary" : ( - (Gfx->ForceGfxMode == GfxEnableForceSecondary) ? "Force Secondary" : "Unknown")) - ); - IDS_HDT_CONSOLE (GFX_MISC, " UmaMode - %s\n", (Gfx->UmaInfo.UmaMode == UMA_NONE) ? "No UMA" : "UMA"); - if (Gfx->UmaInfo.UmaMode != UMA_NONE) { - IDS_HDT_CONSOLE (GFX_MISC, " UmaBase - 0x%x\n", Gfx->UmaInfo.UmaBase); - IDS_HDT_CONSOLE (GFX_MISC, " UmaSize - 0x%x\n", Gfx->UmaInfo.UmaSize); - IDS_HDT_CONSOLE (GFX_MISC, " UmaAttributes - 0x%x\n", Gfx->UmaInfo.UmaAttributes); - } - IDS_HDT_CONSOLE (GFX_MISC, "<-------------- GFX Config End --------------->\n"); - -} diff --git a/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbGfxConfig/GfxConfigPost.h b/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbGfxConfig/GfxConfigPost.h deleted file mode 100644 index 44099870e1..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbGfxConfig/GfxConfigPost.h +++ /dev/null @@ -1,59 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * Initialize GFX configuration data structure. - * - * - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: GNB - * @e \$Revision: 39255 $ @e \$Date: 2010-10-08 11:27:41 -0700 (Fri, 08 Oct 2010) $ - * - */ -/* -***************************************************************************** -* -* Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* *************************************************************************** -* -*/ - -#ifndef _GFXCONFIGPOST_H_ -#define _GFXCONFIGPOST_H_ - -AGESA_STATUS -GfxConfigPostInterface ( - IN AMD_CONFIG_PARAMS *StdHeader - ); - -VOID -GfxConfigDebugDump ( - IN GFX_PLATFORM_CONFIG *Gfx - ); - -#endif diff --git a/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbGfxConfig/GnbGfxConfig.h b/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbGfxConfig/GnbGfxConfig.h deleted file mode 100644 index de35970149..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbGfxConfig/GnbGfxConfig.h +++ /dev/null @@ -1,55 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * Initialize GFX configuration data structure. - * - * - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: GNB - * @e \$Revision: 39255 $ @e \$Date: 2010-10-08 11:27:41 -0700 (Fri, 08 Oct 2010) $ - * - */ -/* -***************************************************************************** -* -* Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* *************************************************************************** -* -*/ - -#ifndef _GNBGFXCONFIG_H_ -#define _GNBGFXCONFIG_H_ - -AGESA_STATUS -GfxLocateConfigData ( - IN AMD_CONFIG_PARAMS *StdHeader, - OUT GFX_PLATFORM_CONFIG **Gfx - ); - -#endif diff --git a/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbGfxConfig/Makefile.inc b/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbGfxConfig/Makefile.inc deleted file mode 100644 index ae82cde5aa..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbGfxConfig/Makefile.inc +++ /dev/null @@ -1,2 +0,0 @@ -libagesa-y += GfxConfigEnv.c -libagesa-y += GfxConfigPost.c diff --git a/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbGfxInitLibV1/GfxCardInfo.c b/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbGfxInitLibV1/GfxCardInfo.c deleted file mode 100644 index ee3bb97948..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbGfxInitLibV1/GfxCardInfo.c +++ /dev/null @@ -1,184 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * Supporting services to collect discrete GFX card info - * - * - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: GNB - * @e \$Revision: 48452 $ @e \$Date: 2011-03-09 12:50:44 +0800 (Wed, 09 Mar 2011) $ - * - */ -/* -***************************************************************************** -* -* Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* *************************************************************************** -* -*/ - -/*---------------------------------------------------------------------------------------- - * M O D U L E S U S E D - *---------------------------------------------------------------------------------------- - */ -#include "AGESA.h" -#include "Ids.h" -#include "amdlib.h" -#include "Gnb.h" -#include "GnbGfx.h" -#include "GnbCommonLib.h" -#include "GfxCardInfo.h" -#include "Filecode.h" -#define FILECODE PROC_GNB_MODULES_GNBGFXINITLIBV1_GFXCARDINFO_FILECODE -/*---------------------------------------------------------------------------------------- - * D E F I N I T I O N S A N D M A C R O S - *---------------------------------------------------------------------------------------- - */ - - -/*---------------------------------------------------------------------------------------- - * T Y P E D E F S A N D S T R U C T U R E S - *---------------------------------------------------------------------------------------- - */ - -typedef struct { - GNB_PCI_SCAN_DATA ScanData; - GFX_CARD_CARD_INFO *GfxCardInfo; - PCI_ADDR BaseBridge; - UINT8 BusNumber; -} GFX_SCAN_DATA; - - -/*---------------------------------------------------------------------------------------- - * P R O T O T Y P E S O F L O C A L F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ - -SCAN_STATUS -GfxScanPcieDevice ( - IN PCI_ADDR Device, - IN OUT GNB_PCI_SCAN_DATA *ScanData - ); - - - -/*----------------------------------------------------------------------------------------*/ -/** - * Get information about all discrete GFX card in system - * - * - * - * @param[out] GfxCardInfo Pointer to GFX card info structure - * @param[in] StdHeader Standard configuration header - */ - -VOID -GfxGetDiscreteCardInfo ( - OUT GFX_CARD_CARD_INFO *GfxCardInfo, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - GFX_SCAN_DATA GfxScanData; - PCI_ADDR Start; - PCI_ADDR End; - IDS_HDT_CONSOLE (GNB_TRACE, "GfxGetDiscreteCardInfo Enter\n"); - Start.AddressValue = MAKE_SBDFO (0, 0, 2, 0, 0); - End.AddressValue = MAKE_SBDFO (0, 0, 0x1f, 7, 0); - GfxScanData.BusNumber = 5; - GfxScanData.ScanData.GnbScanCallback = GfxScanPcieDevice; - GfxScanData.ScanData.StdHeader = StdHeader; - GfxScanData.GfxCardInfo = GfxCardInfo; - GnbLibPciScan (Start, End, &GfxScanData.ScanData); - IDS_HDT_CONSOLE (GNB_TRACE, "GfxGetDiscreteCardInfo Exit\n"); -} - - -/*----------------------------------------------------------------------------------------*/ -/** - * Evaluate device - * - * - * - * @param[in] Device PCI Address - * @param[in,out] ScanData Scan configuration data - * @retval Scan Status of 0 - */ - -SCAN_STATUS -GfxScanPcieDevice ( - IN PCI_ADDR Device, - IN OUT GNB_PCI_SCAN_DATA *ScanData - ) -{ - UINT8 ClassCode; - UINT32 VendorId; - - IDS_HDT_CONSOLE (GFX_MISC, " Evaluate device [%d:%d:%d]\n", - Device.Address.Bus, Device.Address.Device, Device.Address.Function - ); - - if (GnbLibPciIsBridgeDevice (Device.AddressValue, ScanData->StdHeader)) { - UINT32 SaveBusConfiguration; - UINT32 Value; - - if (Device.Address.Bus == 0) { - ((GFX_SCAN_DATA *) ScanData)->BaseBridge = Device; - } - GnbLibPciRead (Device.AddressValue | 0x18, AccessWidth32, &SaveBusConfiguration, ScanData->StdHeader); - Value = (((0xFF << 8) | ((GFX_SCAN_DATA *) ScanData)->BusNumber) << 8) | Device.Address.Bus; - GnbLibPciWrite (Device.AddressValue | 0x18, AccessWidth32, &Value, ScanData->StdHeader); - ((GFX_SCAN_DATA *) ScanData)->BusNumber++; - - GnbLibPciScanSecondaryBus (Device, ScanData); - - ((GFX_SCAN_DATA *) ScanData)->BusNumber--; - GnbLibPciWrite (Device.AddressValue | 0x18, AccessWidth32, &SaveBusConfiguration, ScanData->StdHeader); - return 0; - } - GnbLibPciRead (Device.AddressValue | 0x0b, AccessWidth8, &ClassCode, ScanData->StdHeader); - if (ClassCode == 3) { - IDS_HDT_CONSOLE (GFX_MISC, " Found GFX Card\n" - ); - - GnbLibPciRead (Device.AddressValue | 0x00, AccessWidth32, &VendorId, ScanData->StdHeader); - if (!GnbLibPciIsPcieDevice (Device.AddressValue, ScanData->StdHeader)) { - IDS_HDT_CONSOLE (GFX_MISC, " GFX Card is PCI device\n" - ); - ((GFX_SCAN_DATA *) ScanData)->GfxCardInfo->PciGfxCardBitmap |= (1 << ((GFX_SCAN_DATA *) ScanData)->BaseBridge.Address.Device); - return 0; - } - if ((UINT16) VendorId == 0x1002) { - IDS_HDT_CONSOLE (GFX_MISC, " GFX Card is AMD PCIe device\n" - ); - ((GFX_SCAN_DATA *) ScanData)->GfxCardInfo->AmdPcieGfxCardBitmap |= (1 << ((GFX_SCAN_DATA *) ScanData)->BaseBridge.Address.Device); - } - ((GFX_SCAN_DATA *) ScanData)->GfxCardInfo->PcieGfxCardBitmap |= (1 << ((GFX_SCAN_DATA *) ScanData)->BaseBridge.Address.Device); - } - return 0; -} diff --git a/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbGfxInitLibV1/GfxCardInfo.h b/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbGfxInitLibV1/GfxCardInfo.h deleted file mode 100644 index a23257ea85..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbGfxInitLibV1/GfxCardInfo.h +++ /dev/null @@ -1,63 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * Supporting services to collect discrete GFX card info - * - * - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: GNB - * @e \$Revision: 46832 $ @e \$Date: 2011-02-11 02:21:54 +0800 (Fri, 11 Feb 2011) $ - * - */ -/* -***************************************************************************** -* -* Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* *************************************************************************** -* -*/ - - -#ifndef _GFXCARDINFO_H_ -#define _GFXCARDINFO_H_ - -/// Graphics card information structure -//typedef struct { -// UINT32 AmdPcieGfxCardBitmap; ///< AMD PCIE graphics card information -// UINT32 PcieGfxCardBitmap; ///< All PCIE graphics card information -// UINT32 PciGfxCardBitmap; ///< All PCI graphics card information -//} GFX_CARD_CARD_INFO; - -VOID -GfxGetDiscreteCardInfo ( - OUT GFX_CARD_CARD_INFO *GfxCardInfo, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -#endif diff --git a/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbGfxInitLibV1/GfxEnumConnectors.c b/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbGfxInitLibV1/GfxEnumConnectors.c deleted file mode 100644 index fd7ab4ee2d..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbGfxInitLibV1/GfxEnumConnectors.c +++ /dev/null @@ -1,587 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * Service procedure to initialize Integrated Info Table - * - * - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: GNB - * @e \$Revision: 48452 $ @e \$Date: 2011-03-09 12:50:44 +0800 (Wed, 09 Mar 2011) $ - * - */ -/* -***************************************************************************** -* -* Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* *************************************************************************** -* -*/ - - -/*---------------------------------------------------------------------------------------- - * M O D U L E S U S E D - *---------------------------------------------------------------------------------------- - */ -#include "AGESA.h" -#include "Ids.h" -#include "amdlib.h" -#include "Gnb.h" -#include "GnbPcie.h" -#include "GnbGfx.h" -#include "GnbCommonLib.h" -#include "GnbPcieInitLibV1.h" -#include "GnbPcieConfig.h" -#include "GnbGfxFamServices.h" -#include "GnbRegistersLN.h" -#include "GfxEnumConnectors.h" -#include "Filecode.h" -#define FILECODE PROC_GNB_MODULES_GNBGFXINITLIBV1_GFXENUMCONNECTORS_FILECODE -/*---------------------------------------------------------------------------------------- - * D E F I N I T I O N S A N D M A C R O S - *---------------------------------------------------------------------------------------- - */ - - - -/*---------------------------------------------------------------------------------------- - * T Y P E D E F S A N D S T R U C T U R E S - *---------------------------------------------------------------------------------------- - */ - - -typedef struct { - PCIE_CONNECTOR_TYPE ConnectorType; - UINT8 DisplayDeviceEnum; - UINT16 ConnectorEnum; - UINT16 EncoderEnum; - UINT8 ConnectorIndex; -} EXT_CONNECTOR_INFO; - -typedef struct { - UINT8 DisplayDeviceEnum; - UINT8 DeviceIndex; - UINT16 DeviceTag; - UINT16 DeviceAcpiEnum; -} EXT_DISPLAY_DEVICE_INFO; - -typedef struct { - AGESA_STATUS Status; - UINT8 DisplayDeviceEnum; - UINT8 RequestedPriorityIndex; - UINT8 CurrentPriorityIndex; - PCIe_ENGINE_CONFIG *Engine; -} CONNECTOR_ENUM_INFO; - - -/*---------------------------------------------------------------------------------------- - * P R O T O T Y P E S O F L O C A L F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ - -AGESA_STATUS -GfxIntegratedEnumConnectorsForDevice ( - IN UINT8 DisplayDeviceEnum, - OUT EXT_DISPLAY_PATH *DisplayPathList, - IN OUT PCIe_PLATFORM_CONFIG *Pcie, - IN GFX_PLATFORM_CONFIG *Gfx - ); - -VOID -GfxIntegratedDebugDumpDisplayPath ( - IN EXT_DISPLAY_PATH *DisplayPath, - IN GFX_PLATFORM_CONFIG *Gfx - ); - -EXT_CONNECTOR_INFO* -GfxIntegratedExtConnectorInfo ( - IN UINT8 ConnectorType - ); - -EXT_DISPLAY_DEVICE_INFO* -GfxIntegratedExtDisplayDeviceInfo ( - IN UINT8 DisplayDeviceEnum, - IN UINT8 DisplayDeviceIndex - ); - - -EXT_CONNECTOR_INFO ConnectorInfoTable[] = { - { - ConnectorTypeDP, - DEVICE_DFP, - CONNECTOR_DISPLAYPORT_ENUM, - ENCODER_NOT_PRESENT, - 0, - }, - { - ConnectorTypeEDP, - DEVICE_LCD, - CONNECTOR_eDP_ENUM, - ENCODER_NOT_PRESENT, - 1 - }, - { - ConnectorTypeSingleLinkDVI, - DEVICE_DFP, - CONNECTOR_SINGLE_LINK_DVI_D_ENUM, - ENCODER_NOT_PRESENT, - 2 - }, - { - ConnectorTypeDualLinkDVI, - DEVICE_DFP, - CONNECTOR_DUAL_LINK_DVI_D_ENUM, - ENCODER_NOT_PRESENT, - 3 - }, - { - ConnectorTypeHDMI, - DEVICE_DFP, - CONNECTOR_HDMI_TYPE_A_ENUM, - ENCODER_NOT_PRESENT, - 4 - }, - { - ConnectorTypeTravisDpToVga, - DEVICE_CRT, - CONNECTOR_VGA_ENUM, - ENCODER_TRAVIS_ENUM_ID1, - 5 - }, - { - ConnectorTypeTravisDpToLvds, - DEVICE_LCD, - CONNECTOR_LVDS_ENUM, - ENCODER_TRAVIS_ENUM_ID2, - 6 - }, - { - ConnectorTypeNutmegDpToVga, - DEVICE_CRT, - CONNECTOR_VGA_ENUM, - ENCODER_ALMOND_ENUM_ID1, - 5 - }, - { - ConnectorTypeSingleLinkDviI, - DEVICE_DFP, - CONNECTOR_SINGLE_LINK_DVI_I_ENUM, - ENCODER_NOT_PRESENT, - 5 - }, - { - ConnectorTypeCrt, - DEVICE_CRT, - CONNECTOR_VGA_ENUM, - ENCODER_NOT_PRESENT, - 5 - }, - { - ConnectorTypeLvds, - DEVICE_LCD, - CONNECTOR_LVDS_ENUM, - ENCODER_NOT_PRESENT, - 6 - }, - { - ConnectorTypeAutoDetect, - DEVICE_LCD, - CONNECTOR_LVDS_eDP_ENUM, - ENCODER_TRAVIS_ENUM_ID2, - 7 - } -}; - -UINT8 ConnectorNumerArray[] = { -// DP eDP SDVI-D DDVI-D HDMI VGA LVDS Auto (eDP, LVDS, Travis LVDS) - 6, 1, 6, 6, 6, 1, 1, 2 -}; -/*----------------------------------------------------------------------------------------*/ -/** - * Enumerate all display connectors for specific display device type. - * - * - * - * @param[in] ConnectorType Connector type (see PCIe_DDI_DATA::ConnectorType). - * @retval Pointer to EXT_CONNECTOR_INFO - * @retval NULL if connector type unknown. - */ -EXT_CONNECTOR_INFO* -GfxIntegratedExtConnectorInfo ( - IN UINT8 ConnectorType - ) -{ - UINTN Index; - for (Index = 0; Index < (sizeof (ConnectorInfoTable) / sizeof (EXT_CONNECTOR_INFO)); Index++) { - if (ConnectorInfoTable[Index].ConnectorType == ConnectorType) { - return &ConnectorInfoTable[Index]; - } - } - return NULL; -} - -EXT_DISPLAY_DEVICE_INFO DisplayDeviceInfoTable[] = { - { - DEVICE_CRT, - 1, - ATOM_DEVICE_CRT1_SUPPORT, - 0x100, - }, - { - DEVICE_LCD, - 1, - ATOM_DEVICE_LCD1_SUPPORT, - 0x110, - }, - { - DEVICE_DFP, - 1, - ATOM_DEVICE_DFP1_SUPPORT, - 0x210, - }, - { - DEVICE_DFP, - 2, - ATOM_DEVICE_DFP2_SUPPORT, - 0x220, - }, - { - DEVICE_DFP, - 3, - ATOM_DEVICE_DFP3_SUPPORT, - 0x230, - }, - { - DEVICE_DFP, - 4, - ATOM_DEVICE_DFP4_SUPPORT, - 0x240, - }, - { - DEVICE_DFP, - 5, - ATOM_DEVICE_DFP5_SUPPORT, - 0x250, - }, - { - DEVICE_DFP, - 6, - ATOM_DEVICE_DFP6_SUPPORT, - 0x260, - } -}; -/*----------------------------------------------------------------------------------------*/ -/** - * Enumerate all display connectors for specific display device type. - * - * - * - * @param[in] DisplayDeviceEnum Display device enum - * @param[in] DisplayDeviceIndex Display device index - * @retval Pointer to EXT_DISPLAY_DEVICE_INFO - * @retval NULL if can not get display device info - */ -EXT_DISPLAY_DEVICE_INFO* -GfxIntegratedExtDisplayDeviceInfo ( - IN UINT8 DisplayDeviceEnum, - IN UINT8 DisplayDeviceIndex - ) -{ - UINT8 Index; - UINT8 LastIndex; - LastIndex = 0xff; - for (Index = 0; Index < (sizeof (DisplayDeviceInfoTable) / sizeof (EXT_DISPLAY_DEVICE_INFO)); Index++) { - if (DisplayDeviceInfoTable[Index].DisplayDeviceEnum == DisplayDeviceEnum) { - LastIndex = Index; - if (DisplayDeviceInfoTable[Index].DeviceIndex == DisplayDeviceIndex) { - return &DisplayDeviceInfoTable[Index]; - } - } - } - if (DisplayDeviceEnum == DEVICE_LCD && LastIndex != 0xff) { - return &DisplayDeviceInfoTable[LastIndex]; - } - return NULL; -} - -/*----------------------------------------------------------------------------------------*/ -/** - * Enumerate all display connectors - * - * - * - * @param[out] DisplayPathList Display path list - * @param[in,out] Pcie PCIe platform configuration info - * @param[in] Gfx Gfx configuration info - */ -AGESA_STATUS -GfxIntegratedEnumerateAllConnectors ( - OUT EXT_DISPLAY_PATH *DisplayPathList, - IN OUT PCIe_PLATFORM_CONFIG *Pcie, - IN GFX_PLATFORM_CONFIG *Gfx - ) -{ - AGESA_STATUS AgesaStatus; - AGESA_STATUS Status; - AgesaStatus = AGESA_SUCCESS; - IDS_HDT_CONSOLE (GNB_TRACE, "GfxIntegratedEnumerateAllConnectors Enter\n"); - Status = GfxIntegratedEnumConnectorsForDevice ( - DEVICE_DFP, - DisplayPathList, - Pcie, - Gfx - ); - AGESA_STATUS_UPDATE (Status, AgesaStatus); - - Status = GfxIntegratedEnumConnectorsForDevice ( - DEVICE_CRT, - DisplayPathList, - Pcie, - Gfx - ); - AGESA_STATUS_UPDATE (Status, AgesaStatus); - - Status = GfxIntegratedEnumConnectorsForDevice ( - DEVICE_LCD, - DisplayPathList, - Pcie, - Gfx - ); - AGESA_STATUS_UPDATE (Status, AgesaStatus); - IDS_HDT_CONSOLE (GNB_TRACE, "GfxIntegratedEnumerateAllConnectors Exit [0x%x]\n", Status); - return AgesaStatus; -} - -/*----------------------------------------------------------------------------------------*/ -/** - * Enumerate all display connectors for specific display device type. - * - * - * - * @param[in] Engine Engine configuration info - * @param[in,out] Buffer Buffer pointer - * @param[in] Pcie PCIe configuration info - */ -VOID -STATIC -GfxIntegratedDdiInterfaceCallback ( - IN PCIe_ENGINE_CONFIG *Engine, - IN OUT VOID *Buffer, - IN PCIe_PLATFORM_CONFIG *Pcie - ) -{ - CONNECTOR_ENUM_INFO *ConnectorEnumInfo; - EXT_CONNECTOR_INFO *ExtConnectorInfo; - ConnectorEnumInfo = (CONNECTOR_ENUM_INFO*) Buffer; - ExtConnectorInfo = GfxIntegratedExtConnectorInfo (Engine->Type.Ddi.DdiData.ConnectorType); - if (ExtConnectorInfo == NULL) { - AGESA_STATUS_UPDATE (AGESA_ERROR, ConnectorEnumInfo->Status); - PcieConfigDisableEngine (Engine); - return; - } - if (ExtConnectorInfo->DisplayDeviceEnum != ConnectorEnumInfo->DisplayDeviceEnum) { - //Not device type we are looking for - return; - } - if (Engine->Type.Ddi.DisplayPriorityIndex >= ConnectorEnumInfo->RequestedPriorityIndex && - Engine->Type.Ddi.DisplayPriorityIndex < ConnectorEnumInfo->CurrentPriorityIndex) { - ConnectorEnumInfo->CurrentPriorityIndex = Engine->Type.Ddi.DisplayPriorityIndex; - ConnectorEnumInfo->Engine = Engine; - } -} - -/*----------------------------------------------------------------------------------------*/ -/** - * Enumerate all display connectors for specific display device type. - * - * - * - * @param[in] DisplayDeviceEnum Display device list - * @param[out] DisplayPathList Display path list - * @param[in,out] Pcie PCIe configuration info - * @param[in] Gfx Gfx configuration info - */ -AGESA_STATUS -GfxIntegratedEnumConnectorsForDevice ( - IN UINT8 DisplayDeviceEnum, - OUT EXT_DISPLAY_PATH *DisplayPathList, - IN OUT PCIe_PLATFORM_CONFIG *Pcie, - IN GFX_PLATFORM_CONFIG *Gfx - ) -{ - UINT8 DisplayDeviceIndex; - CONNECTOR_ENUM_INFO ConnectorEnumInfo; - EXT_CONNECTOR_INFO *ExtConnectorInfo; - EXT_DISPLAY_DEVICE_INFO *ExtDisplayDeviceInfo; - AGESA_STATUS Status; - UINT8 ConnectorIdArray[sizeof (ConnectorNumerArray)]; - ConnectorEnumInfo.Status = AGESA_SUCCESS; - DisplayDeviceIndex = 1; - ConnectorEnumInfo.RequestedPriorityIndex = 0; - ConnectorEnumInfo.DisplayDeviceEnum = DisplayDeviceEnum; - LibAmdMemFill (ConnectorIdArray, 0x00, sizeof (ConnectorIdArray), GnbLibGetHeader (Gfx)); - do { - ConnectorEnumInfo.Engine = NULL; - ConnectorEnumInfo.CurrentPriorityIndex = 0xff; - PcieConfigRunProcForAllEngines ( - DESCRIPTOR_ALLOCATED | DESCRIPTOR_VIRTUAL | DESCRIPTOR_DDI_ENGINE, - GfxIntegratedDdiInterfaceCallback, - &ConnectorEnumInfo, - Pcie - ); - if (ConnectorEnumInfo.Engine == NULL) { - break; // No more connector support this - } - ConnectorEnumInfo.RequestedPriorityIndex = ConnectorEnumInfo.CurrentPriorityIndex + 1; - ExtConnectorInfo = GfxIntegratedExtConnectorInfo (ConnectorEnumInfo.Engine->Type.Ddi.DdiData.ConnectorType); - ASSERT (ExtConnectorInfo != NULL); - ASSERT (ExtConnectorInfo->ConnectorIndex < sizeof (ConnectorIdArray)); - if (ConnectorIdArray[ExtConnectorInfo->ConnectorIndex] >= ConnectorNumerArray[ExtConnectorInfo->ConnectorIndex]) { - //Run out of supported connectors - AGESA_STATUS_UPDATE (AGESA_ERROR, ConnectorEnumInfo.Status); - PcieConfigDisableEngine (ConnectorEnumInfo.Engine); - continue; - } - ConnectorEnumInfo.Engine->Type.Ddi.ConnectorId = ConnectorIdArray[ExtConnectorInfo->ConnectorIndex] + 1; - ExtDisplayDeviceInfo = GfxIntegratedExtDisplayDeviceInfo (DisplayDeviceEnum, DisplayDeviceIndex); - if (ExtDisplayDeviceInfo == NULL) { - //Run out of supported display device types - AGESA_STATUS_UPDATE (AGESA_ERROR, ConnectorEnumInfo.Status); - Status = AGESA_ERROR; - PcieConfigDisableEngine (ConnectorEnumInfo.Engine); - } - - if ((Gfx->Gnb3dStereoPinIndex != 0) && (ConnectorEnumInfo.Engine->Type.Ddi.DdiData.HdpIndex == (Gfx->Gnb3dStereoPinIndex - 1))) { - AGESA_STATUS_UPDATE (AGESA_ERROR, ConnectorEnumInfo.Status); - Status = AGESA_ERROR; - PcieConfigDisableEngine (ConnectorEnumInfo.Engine); - } - - ConnectorEnumInfo.Engine->Type.Ddi.DisplayDeviceId = DisplayDeviceIndex; - - Status = GfxFmMapEngineToDisplayPath (ConnectorEnumInfo.Engine, DisplayPathList, Gfx); - AGESA_STATUS_UPDATE (Status, ConnectorEnumInfo.Status); - if (Status != AGESA_SUCCESS) { - continue; - } - ConnectorIdArray[ExtConnectorInfo->ConnectorIndex]++; - DisplayDeviceIndex++; - } while (ConnectorEnumInfo.Engine != NULL); - return ConnectorEnumInfo.Status; -} - -/*----------------------------------------------------------------------------------------*/ -/** - * Initialize display path for given engine - * - * - * - * @param[in] Engine Engine configuration info - * @param[out] DisplayPath Display path list - * @param[out] SecondaryDisplayPath Secondary display path list - * @param[in] Gfx Gfx configuration info - */ - -VOID -GfxIntegratedCopyDisplayInfo ( - IN PCIe_ENGINE_CONFIG *Engine, - OUT EXT_DISPLAY_PATH *DisplayPath, - OUT EXT_DISPLAY_PATH *SecondaryDisplayPath, - IN GFX_PLATFORM_CONFIG *Gfx - ) -{ - EXT_CONNECTOR_INFO *ExtConnectorInfo; - EXT_DISPLAY_DEVICE_INFO *ExtDisplayDeviceInfo; - ExtConnectorInfo = GfxIntegratedExtConnectorInfo (Engine->Type.Ddi.DdiData.ConnectorType); - ExtDisplayDeviceInfo = GfxIntegratedExtDisplayDeviceInfo (ExtConnectorInfo->DisplayDeviceEnum, Engine->Type.Ddi.DisplayDeviceId); - DisplayPath->usDeviceConnector = ExtConnectorInfo->ConnectorEnum | (Engine->Type.Ddi.ConnectorId << 8); - DisplayPath->usDeviceTag = ExtDisplayDeviceInfo->DeviceTag; - DisplayPath->usDeviceACPIEnum = ExtDisplayDeviceInfo->DeviceAcpiEnum; - DisplayPath->ucExtAUXDDCLutIndex = Engine->Type.Ddi.DdiData.AuxIndex; - DisplayPath->ucExtHPDPINLutIndex = Engine->Type.Ddi.DdiData.HdpIndex; - DisplayPath->ucChPNInvert = Engine->Type.Ddi.DdiData.LanePnInversionMask; - DisplayPath->usExtEncoderObjId = ExtConnectorInfo->EncoderEnum; - if (Engine->Type.Ddi.DdiData.Mapping[0].ChannelMappingValue == 0) { - DisplayPath->ChannelMapping.ucChannelMapping = (Engine->EngineData.StartLane < Engine->EngineData.EndLane) ? 0xE4 : 0x1B; - } else { - DisplayPath->ChannelMapping.ucChannelMapping = Engine->Type.Ddi.DdiData.Mapping[0].ChannelMappingValue; - } - GNB_DEBUG_CODE ( - GfxIntegratedDebugDumpDisplayPath (DisplayPath, Gfx); - ); - if (Engine->Type.Ddi.DdiData.ConnectorType == ConnectorTypeDualLinkDVI) { - ASSERT (SecondaryDisplayPath != NULL); - GNB_DEBUG_CODE ( - GfxIntegratedDebugDumpDisplayPath (DisplayPath, Gfx); - ); - SecondaryDisplayPath->usDeviceConnector = DisplayPath->usDeviceConnector; - if (Engine->Type.Ddi.DdiData.Mapping[1].ChannelMappingValue == 0) { - DisplayPath->ChannelMapping.ucChannelMapping = (Engine->EngineData.StartLane < Engine->EngineData.EndLane) ? 0xE4 : 0x1B; - } else { - DisplayPath->ChannelMapping.ucChannelMapping = Engine->Type.Ddi.DdiData.Mapping[1].ChannelMappingValue; - } - } -} - - - -/*----------------------------------------------------------------------------------------*/ -/** - * Dump display path settings - * - * - * - * @param[in] DisplayPath Display path - * @param[in] Gfx Gfx configuration - */ - -VOID -GfxIntegratedDebugDumpDisplayPath ( - IN EXT_DISPLAY_PATH *DisplayPath, - IN GFX_PLATFORM_CONFIG *Gfx - ) -{ - IDS_HDT_CONSOLE (GFX_MISC, " usDeviceConnector = 0x%x\n", - DisplayPath->usDeviceConnector - ); - IDS_HDT_CONSOLE (GFX_MISC, " usDeviceTag = 0x%x\n", - DisplayPath->usDeviceTag - ); - IDS_HDT_CONSOLE (GFX_MISC, " usDeviceACPIEnum = 0x%x\n", - DisplayPath->usDeviceACPIEnum - ); - IDS_HDT_CONSOLE (GFX_MISC, " usExtEncoderObjId = 0x%x\n", - DisplayPath->usExtEncoderObjId - ); - IDS_HDT_CONSOLE (GFX_MISC, " ucChannelMapping = 0x%x\n", - DisplayPath->ChannelMapping.ucChannelMapping - ); - IDS_HDT_CONSOLE (GFX_MISC, " ucChPNInvert = 0x%x\n", - DisplayPath->ucChPNInvert - ); -} diff --git a/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbGfxInitLibV1/GfxEnumConnectors.h b/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbGfxInitLibV1/GfxEnumConnectors.h deleted file mode 100644 index ee67b374cb..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbGfxInitLibV1/GfxEnumConnectors.h +++ /dev/null @@ -1,64 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * Service procedure to initialize Integrated Info Table - * - * - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: GNB - * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $ - * - */ -/* -***************************************************************************** -* -* Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* *************************************************************************** -* -*/ -#ifndef _GFXENUMCONNECTORS_H_ -#define _GFXENUMCONNECTORS_H_ - - -VOID -GfxIntegratedCopyDisplayInfo ( - IN PCIe_ENGINE_CONFIG *Engine, - OUT EXT_DISPLAY_PATH *DisplayPath, - OUT EXT_DISPLAY_PATH *SecondaryDisplayPath, - IN GFX_PLATFORM_CONFIG *Gfx - ); - -AGESA_STATUS -GfxIntegratedEnumerateAllConnectors ( - OUT EXT_DISPLAY_PATH *DisplayPathList, - IN OUT PCIe_PLATFORM_CONFIG *Pcie, - IN GFX_PLATFORM_CONFIG *Gfx - ); - -#endif diff --git a/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbGfxInitLibV1/GfxPowerPlayTable.c b/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbGfxInitLibV1/GfxPowerPlayTable.c deleted file mode 100644 index 7ecb6fa165..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbGfxInitLibV1/GfxPowerPlayTable.c +++ /dev/null @@ -1,735 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * Service procedure to initialize Integrated Info Table - * - * - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: GNB - * @e \$Revision: 48452 $ @e \$Date: 2011-03-09 12:50:44 +0800 (Wed, 09 Mar 2011) $ - * - */ -/* -***************************************************************************** -* -* Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* *************************************************************************** -* -*/ - - -/*---------------------------------------------------------------------------------------- - * M O D U L E S U S E D - *---------------------------------------------------------------------------------------- - */ -#include "AGESA.h" -#include "Ids.h" -#include "amdlib.h" -#include "heapManager.h" -#include "Gnb.h" -#include "GnbFuseTable.h" -#include "GnbPcie.h" -#include "GnbGfx.h" -#include "GnbFuseTable.h" -#include "GnbGfxFamServices.h" -#include "GnbCommonLib.h" -#include "GfxPowerPlayTable.h" -#include "Filecode.h" -#define FILECODE PROC_GNB_MODULES_GNBGFXINITLIBV1_GFXPOWERPLAYTABLE_FILECODE - -/*---------------------------------------------------------------------------------------- - * D E F I N I T I O N S A N D M A C R O S - *---------------------------------------------------------------------------------------- - */ - - - -/*---------------------------------------------------------------------------------------- - * T Y P E D E F S A N D S T R U C T U R E S - *---------------------------------------------------------------------------------------- - */ -/// Software state -typedef struct { - BOOLEAN Valid; ///< State valid - UINT16 Classification; ///< State classification - UINT32 CapsAndSettings; ///< State capability and settings - UINT16 Classification2; ///< State classification2 - UINT32 Vclk; ///< UVD VCLK - UINT32 Dclk; ///< UVD DCLK - UINT8 NumberOfDpmStates; ///< Number of DPM states - UINT8 DpmSatesArray[MAX_NUM_OF_DPM_STATES]; ///< DPM state index array -} SW_STATE; - -/// DPM state -typedef struct { - BOOLEAN Valid; ///< State valid - UINT32 Sclk; ///< Sclk in kHz - UINT8 Vid; ///< VID index - UINT16 Tdp; ///< Tdp limit -} DPM_STATE; - -/*---------------------------------------------------------------------------------------- - * P R O T O T Y P E S O F L O C A L F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ -UINT16 -GfxPowerPlayLocateTdp ( - IN PP_FUSE_ARRAY *PpFuses, - IN UINT32 Sclk, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -UINT8 -GfxPowerPlayAddDpmState ( - IN DPM_STATE *DpmStateArray, - IN UINT32 Sclk, - IN UINT8 Vid, - IN UINT16 Tdp - ); - -VOID -GfxPowerPlayAddDpmStateToSwState ( - IN OUT SW_STATE *SwStateArray, - IN UINT8 DpmStateIndex - ); - -SW_STATE* -GfxPowerPlayCreateSwState ( - IN OUT SW_STATE *SwStateArray - ); - -UINT8 -GfxPowerPlayCreateDpmState ( - IN DPM_STATE *DpmStateArray, - IN UINT32 Sclk, - IN UINT8 Vid, - IN UINT16 Tdp - ); - -UINT32 -GfxPowerPlayCopyStateInfo ( - IN OUT STATE_ARRAY *StateArray, - IN SW_STATE *SwStateArray, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -UINT32 -GfxPowerPlayCopyClockInfo ( - IN CLOCK_INFO_ARRAY *ClockInfoArray, - IN DPM_STATE *DpmStateArray, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -UINT32 -GfxPowerPlayCopyNonClockInfo ( - IN NON_CLOCK_INFO_ARRAY *NonClockInfoArray, - IN SW_STATE *SwStateArray, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -BOOLEAN -GfxPowerPlayIsFusedStateValid ( - IN UINT8 Index, - IN PP_FUSE_ARRAY *PpFuses, - IN GFX_PLATFORM_CONFIG *Gfx - ); - -UINT16 -GfxPowerPlayGetClassificationFromFuses ( - IN UINT8 Index, - IN PP_FUSE_ARRAY *PpFuses, - IN GFX_PLATFORM_CONFIG *Gfx - ); - -UINT16 -GfxPowerPlayGetClassification2FromFuses ( - IN UINT8 Index, - IN PP_FUSE_ARRAY *PpFuses, - IN GFX_PLATFORM_CONFIG *Gfx - ); - -VOID -GfxIntegratedDebugDumpPpTable ( - IN ATOM_PPLIB_POWERPLAYTABLE3 *PpTable, - IN GFX_PLATFORM_CONFIG *Gfx - ); - -/*----------------------------------------------------------------------------------------*/ -/** - * Locate existing tdp - * - * - * @param[in ] PpFuses Pointer to PP_FUSE_ARRAY - * @param[in] Sclk Sclk in 10kHz - * @param[in] StdHeader Standard configuration header - * @retval Tdp limit in DPM state array - */ - -UINT16 -GfxPowerPlayLocateTdp ( - IN PP_FUSE_ARRAY *PpFuses, - IN UINT32 Sclk, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - UINT8 Index; - UINT32 DpmIndex; - UINT32 DpmSclk; - UINT32 DeltaSclk; - UINT32 MinDeltaSclk; - - DpmIndex = 0; - MinDeltaSclk = 0xFFFFFFFF; - for (Index = 0; Index < MAX_NUM_OF_FUSED_DPM_STATES; Index++) { - if (PpFuses->SclkDpmDid[Index] != 0) { - DpmSclk = GfxFmCalculateClock (PpFuses->SclkDpmDid[Index], StdHeader); - DeltaSclk = (DpmSclk > Sclk) ? (DpmSclk - Sclk) : (Sclk - DpmSclk); - if (DeltaSclk < MinDeltaSclk) { - MinDeltaSclk = DeltaSclk; - DpmIndex = Index; - } - } - } - return PpFuses->SclkDpmTdpLimit[DpmIndex]; -} - -/*----------------------------------------------------------------------------------------*/ -/** - * Create new software state - * - * - * @param[in, out] SwStateArray Pointer to SW state array - * @retval Pointer to state entry in SW state array - */ - -SW_STATE* -GfxPowerPlayCreateSwState ( - IN OUT SW_STATE *SwStateArray - ) -{ - UINTN Index; - for (Index = 0; Index < MAX_NUM_OF_SW_STATES; Index++) { - if (SwStateArray[Index].Valid == FALSE) { - SwStateArray[Index].Valid = TRUE; - return &SwStateArray[Index]; - } - } - return NULL; -} - -/*----------------------------------------------------------------------------------------*/ -/** - * Create new DPM state - * - * - * @param[in, out] DpmStateArray Pointer to DPM state array - * @param[in] Sclk SCLK in kHz - * @param[in] Vid Vid index - * @param[in] Tdp Tdp limit - * @retval Index of state entry in DPM state array - */ - -UINT8 -GfxPowerPlayCreateDpmState ( - IN DPM_STATE *DpmStateArray, - IN UINT32 Sclk, - IN UINT8 Vid, - IN UINT16 Tdp - ) -{ - UINT8 Index; - for (Index = 0; Index < MAX_NUM_OF_DPM_STATES; Index++) { - if (DpmStateArray[Index].Valid == FALSE) { - DpmStateArray[Index].Sclk = Sclk; - DpmStateArray[Index].Vid = Vid; - DpmStateArray[Index].Valid = TRUE; - DpmStateArray[Index].Tdp = Tdp; - return Index; - } - } - return 0; -} - -/*----------------------------------------------------------------------------------------*/ -/** - * Locate existing or Create new DPM state - * - * - * @param[in, out] DpmStateArray Pointer to DPM state array - * @param[in] Sclk SCLK in kHz - * @param[in] Vid Vid index - * @param[in] Tdp Tdp limit - * @retval Index of state entry in DPM state array - */ - -UINT8 -GfxPowerPlayAddDpmState ( - IN DPM_STATE *DpmStateArray, - IN UINT32 Sclk, - IN UINT8 Vid, - IN UINT16 Tdp - ) -{ - UINT8 Index; - for (Index = 0; Index < MAX_NUM_OF_DPM_STATES; Index++) { - if (DpmStateArray[Index].Valid && Sclk == DpmStateArray[Index].Sclk && Vid == DpmStateArray[Index].Vid) { - return Index; - } - } - return GfxPowerPlayCreateDpmState (DpmStateArray, Sclk, Vid, Tdp); -} - -/*----------------------------------------------------------------------------------------*/ -/** - * Add reference to DPM state for SW state - * - * - * @param[in, out] SwStateArray Pointer to SW state array - * @param[in] DpmStateIndex DPM state index - */ - -VOID -GfxPowerPlayAddDpmStateToSwState ( - IN OUT SW_STATE *SwStateArray, - IN UINT8 DpmStateIndex - ) -{ - SwStateArray->DpmSatesArray[SwStateArray->NumberOfDpmStates++] = DpmStateIndex; -} - -/*----------------------------------------------------------------------------------------*/ -/** - * Copy SW state info to PPTable - * - * - * @param[out] StateArray Pointer to PPtable SW state array - * @param[in] SwStateArray Pointer to SW state array - * @param[in] StdHeader Standard configuration header - */ -UINT32 -GfxPowerPlayCopyStateInfo ( - IN OUT STATE_ARRAY *StateArray, - IN SW_STATE *SwStateArray, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - UINT8 Index; - UINT8 SwStateIndex; - ATOM_PPLIB_STATE_V2 *States; - States = &StateArray->States[0]; - SwStateIndex = 0; - for (Index = 0; Index < MAX_NUM_OF_SW_STATES; Index++) { - if (SwStateArray[Index].Valid && SwStateArray[Index].NumberOfDpmStates != 0) { - States->nonClockInfoIndex = SwStateIndex; - States->ucNumDPMLevels = SwStateArray[Index].NumberOfDpmStates; - LibAmdMemCopy ( - &States->ClockInfoIndex[0], - SwStateArray[Index].DpmSatesArray, - SwStateArray[Index].NumberOfDpmStates, - StdHeader - ); - States = (ATOM_PPLIB_STATE_V2*) ((UINT8*) States + sizeof (ATOM_PPLIB_STATE_V2) + sizeof (UINT8) * (States->ucNumDPMLevels - 1)); - SwStateIndex++; - } - } - StateArray->ucNumEntries = SwStateIndex; - return (UINT32) ((UINT8*) States - (UINT8*) StateArray); -} -/*----------------------------------------------------------------------------------------*/ -/** - * Copy clock info to PPTable - * - * - * @param[out] ClockInfoArray Pointer to clock info array - * @param[in] DpmStateArray Pointer to DPM state array - * @param[in] StdHeader Standard configuration header - */ - -UINT32 -GfxPowerPlayCopyClockInfo ( - IN CLOCK_INFO_ARRAY *ClockInfoArray, - IN DPM_STATE *DpmStateArray, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - UINT8 Index; - UINT8 ClkStateIndex; - ClkStateIndex = 0; - for (Index = 0; Index < MAX_NUM_OF_DPM_STATES; Index++) { - if (DpmStateArray[Index].Valid == TRUE) { - ClockInfoArray->ClockInfo[ClkStateIndex].ucEngineClockHigh = (UINT8) (DpmStateArray[Index].Sclk >> 16); - ClockInfoArray->ClockInfo[ClkStateIndex].usEngineClockLow = (UINT16) (DpmStateArray[Index].Sclk); - ClockInfoArray->ClockInfo[ClkStateIndex].vddcIndex = DpmStateArray[Index].Vid; - ClockInfoArray->ClockInfo[ClkStateIndex].tdpLimit = DpmStateArray[Index].Tdp; - ClkStateIndex++; - } - } - ClockInfoArray->ucNumEntries = ClkStateIndex; - ClockInfoArray->ucEntrySize = sizeof (ATOM_PPLIB_SUMO_CLOCK_INFO); - return sizeof (CLOCK_INFO_ARRAY) + sizeof (ATOM_PPLIB_SUMO_CLOCK_INFO) * (ClkStateIndex) - sizeof (ATOM_PPLIB_SUMO_CLOCK_INFO); -} - -/*----------------------------------------------------------------------------------------*/ -/** - * Copy non clock info to PPTable - * - * - * @param[out] NonClockInfoArray Pointer to PPtable Non clock array - * @param[in] SwStateArray Pointer to SW state array - * @param[in] StdHeader Standard configuration header - */ - -UINT32 -GfxPowerPlayCopyNonClockInfo ( - IN NON_CLOCK_INFO_ARRAY *NonClockInfoArray, - IN SW_STATE *SwStateArray, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - UINT8 Index; - UINT8 NonClkStateIndex; - NonClkStateIndex = 0; - for (Index = 0; Index < MAX_NUM_OF_SW_STATES; Index++) { - if (SwStateArray[Index].Valid && SwStateArray[Index].NumberOfDpmStates != 0) { - NonClockInfoArray->NonClockInfo[NonClkStateIndex].usClassification = SwStateArray[Index].Classification; - NonClockInfoArray->NonClockInfo[NonClkStateIndex].ulCapsAndSettings = SwStateArray[Index].CapsAndSettings; - NonClockInfoArray->NonClockInfo[NonClkStateIndex].usClassification2 = SwStateArray[Index].Classification2; - NonClockInfoArray->NonClockInfo[NonClkStateIndex].ulDCLK = SwStateArray[Index].Dclk; - NonClockInfoArray->NonClockInfo[NonClkStateIndex].ulVCLK = SwStateArray[Index].Vclk; - NonClkStateIndex++; - } - } - NonClockInfoArray->ucNumEntries = NonClkStateIndex; - NonClockInfoArray->ucEntrySize = sizeof (ATOM_PPLIB_NONCLOCK_INFO); - return sizeof (NON_CLOCK_INFO_ARRAY) + sizeof (ATOM_PPLIB_NONCLOCK_INFO) * NonClkStateIndex - sizeof (ATOM_PPLIB_NONCLOCK_INFO); -} - -/*----------------------------------------------------------------------------------------*/ -/** - * Check if fused state valid - * - * - * @param[out] Index State index - * @param[in] PpFuses Pointer to fuse table - * @param[in] Gfx Gfx configuration info - * @retval TRUE State is valid - */ -BOOLEAN -GfxPowerPlayIsFusedStateValid ( - IN UINT8 Index, - IN PP_FUSE_ARRAY *PpFuses, - IN GFX_PLATFORM_CONFIG *Gfx - ) -{ - BOOLEAN Result; - Result = FALSE; - if (PpFuses->SclkDpmValid[Index] != 0) { - Result = TRUE; - if (PpFuses->PolicyLabel[Index] == POLICY_LABEL_BATTERY && (Gfx->AmdPlatformType & AMD_PLATFORM_MOBILE) == 0) { - Result = FALSE; - } - } - return Result; -} - -/*----------------------------------------------------------------------------------------*/ -/** - * Get SW state calssification from fuses - * - * - * @param[out] Index State index - * @param[in] PpFuses Pointer to fuse table - * @param[in] Gfx Gfx configuration info - * @retval State classification - */ - -UINT16 -GfxPowerPlayGetClassificationFromFuses ( - IN UINT8 Index, - IN PP_FUSE_ARRAY *PpFuses, - IN GFX_PLATFORM_CONFIG *Gfx - ) -{ - UINT16 Classification; - Classification = 0; - switch (PpFuses->PolicyFlags[Index]) { - case 0x1: - Classification |= ATOM_PPLIB_CLASSIFICATION_NONUVDSTATE; - break; - case 0x2: - Classification |= ATOM_PPLIB_CLASSIFICATION_UVDSTATE; - break; - case 0x4: - //Possible SD + HD state - break; - case 0x8: - Classification |= ATOM_PPLIB_CLASSIFICATION_HDSTATE; - break; - case 0x10: - Classification |= ATOM_PPLIB_CLASSIFICATION_SDSTATE; - break; - default: - break; - } - switch (PpFuses->PolicyLabel[Index]) { - case POLICY_LABEL_BATTERY: - Classification |= ATOM_PPLIB_CLASSIFICATION_UI_BATTERY; - break; - case POLICY_LABEL_PERFORMANCE: - Classification |= ATOM_PPLIB_CLASSIFICATION_UI_PERFORMANCE; - break; - default: - break; - } - return Classification; -} - -/*----------------------------------------------------------------------------------------*/ -/** - * Get SW state calssification2 from fuses - * - * - * @param[out] Index State index - * @param[in] PpFuses Pointer to fuse table - * @param[in] Gfx Gfx configuration info - * @retval State classification2 - */ - -UINT16 -GfxPowerPlayGetClassification2FromFuses ( - IN UINT8 Index, - IN PP_FUSE_ARRAY *PpFuses, - IN GFX_PLATFORM_CONFIG *Gfx - ) -{ - UINT16 Classification2; - Classification2 = 0; - - switch (PpFuses->PolicyFlags[Index]) { - - case 0x4: - Classification2 |= ATOM_PPLIB_CLASSIFICATION2_MVC; - break; - - default: - break; - } - - return Classification2; -} - -/*----------------------------------------------------------------------------------------*/ -/** - * Build PP table - * - * - * @param[out] Buffer Buffer to create PP table - * @param[in] Gfx Gfx configuration info - * @retval AGESA_SUCCESS - * @retval AGESA_ERROR - */ - -AGESA_STATUS -GfxPowerPlayBuildTable ( - OUT VOID *Buffer, - IN GFX_PLATFORM_CONFIG *Gfx - ) -{ - ATOM_PPLIB_POWERPLAYTABLE3 *PpTable; - SW_STATE SwStateArray [MAX_NUM_OF_SW_STATES]; - DPM_STATE DpmStateArray[MAX_NUM_OF_DPM_STATES]; - UINT8 ClkStateIndex; - UINT8 DpmFuseIndex; - UINT8 Index; - UINT32 StateArrayLength; - UINT32 ClockArrayLength; - UINT32 NonClockArrayLength; - SW_STATE *State; - PP_FUSE_ARRAY *PpFuses; - UINT32 Sclk; - - PpFuses = GnbLocateHeapBuffer (AMD_PP_FUSE_TABLE_HANDLE, GnbLibGetHeader (Gfx)); - ASSERT (PpFuses != NULL); - if (PpFuses == NULL) { - return AGESA_ERROR; - } - - PpTable = (ATOM_PPLIB_POWERPLAYTABLE3 *) Buffer; - LibAmdMemFill (SwStateArray, 0x00, sizeof (SwStateArray), GnbLibGetHeader (Gfx)); - LibAmdMemFill (DpmStateArray, 0x00, sizeof (DpmStateArray), GnbLibGetHeader (Gfx)); - // Create States from Fuses - for (Index = 0; Index < MAX_NUM_OF_FUSED_SW_STATES; Index++) { - if (GfxPowerPlayIsFusedStateValid (Index, PpFuses, Gfx)) { - //Create new SW State; - State = GfxPowerPlayCreateSwState (SwStateArray); - State->Classification = GfxPowerPlayGetClassificationFromFuses (Index, PpFuses, Gfx); - State->Classification2 = GfxPowerPlayGetClassification2FromFuses (Index, PpFuses, Gfx); - if ((State->Classification & (ATOM_PPLIB_CLASSIFICATION_HDSTATE | ATOM_PPLIB_CLASSIFICATION_UVDSTATE)) != 0 || - (State->Classification2 & ATOM_PPLIB_CLASSIFICATION2_MVC) != 0) { - State->Vclk = (PpFuses->VclkDid[PpFuses->VclkDclkSel[Index]] != 0) ? GfxFmCalculateClock (PpFuses->VclkDid[PpFuses->VclkDclkSel[Index]], GnbLibGetHeader (Gfx)) : 0; - State->Dclk = (PpFuses->DclkDid[PpFuses->VclkDclkSel[Index]] != 0) ? GfxFmCalculateClock (PpFuses->DclkDid[PpFuses->VclkDclkSel[Index]], GnbLibGetHeader (Gfx)) : 0; - } - if ((State->Classification & 0x7) == ATOM_PPLIB_CLASSIFICATION_UI_BATTERY) { - if (Gfx->AbmSupport != 0) { - State->CapsAndSettings |= ATOM_PPLIB_ENABLE_VARIBRIGHT; - } - if (Gfx->DynamicRefreshRate != 0) { - State->CapsAndSettings |= ATOM_PPLIB_ENABLE_DRR; - } - } - for (DpmFuseIndex = 0; DpmFuseIndex < MAX_NUM_OF_FUSED_DPM_STATES; DpmFuseIndex++) { - if ((PpFuses->SclkDpmValid[Index] & (1 << DpmFuseIndex)) != 0 ) { - Sclk = (PpFuses->SclkDpmDid[DpmFuseIndex] != 0) ? GfxFmCalculateClock (PpFuses->SclkDpmDid[DpmFuseIndex], GnbLibGetHeader (Gfx)) : 0; - if (Sclk != 0) { - ClkStateIndex = GfxPowerPlayAddDpmState (DpmStateArray, Sclk, PpFuses->SclkDpmVid[DpmFuseIndex], PpFuses->SclkDpmTdpLimit[DpmFuseIndex]); - GfxPowerPlayAddDpmStateToSwState (State, ClkStateIndex); - } - } - } - } - } - // Create Boot State - State = GfxPowerPlayCreateSwState (SwStateArray); - State->Classification = ATOM_PPLIB_CLASSIFICATION_BOOT; - Sclk = 200 * 100; - ClkStateIndex = GfxPowerPlayAddDpmState (DpmStateArray, Sclk, 0, GfxPowerPlayLocateTdp (PpFuses, Sclk, GnbLibGetHeader (Gfx))); - GfxPowerPlayAddDpmStateToSwState (State, ClkStateIndex); - - // Create Thermal State - State = GfxPowerPlayCreateSwState (SwStateArray); - State->Classification = ATOM_PPLIB_CLASSIFICATION_THERMAL; - Sclk = GfxFmCalculateClock (PpFuses->SclkThermDid, GnbLibGetHeader (Gfx)); - ClkStateIndex = GfxPowerPlayAddDpmState (DpmStateArray, Sclk, 0, GfxPowerPlayLocateTdp (PpFuses, Sclk, GnbLibGetHeader (Gfx))); - GfxPowerPlayAddDpmStateToSwState (State, ClkStateIndex); - - //Copy state info to actual PP table - StateArrayLength = GfxPowerPlayCopyStateInfo ( - &PpTable->StateArray, - SwStateArray, - GnbLibGetHeader (Gfx) - ); - ClockArrayLength = GfxPowerPlayCopyClockInfo ( - (CLOCK_INFO_ARRAY*) ((UINT8 *)&PpTable->StateArray + StateArrayLength), - DpmStateArray, - GnbLibGetHeader (Gfx) - ); - NonClockArrayLength = GfxPowerPlayCopyNonClockInfo ( - (NON_CLOCK_INFO_ARRAY*) ((UINT8 *)&PpTable->StateArray + StateArrayLength + ClockArrayLength), - SwStateArray, - GnbLibGetHeader (Gfx) - ); - //Fill static info - PpTable->sHeader.ucTableFormatRevision = 6; - PpTable->sHeader.ucTableContentRevision = 1; - PpTable->ucDataRevision = PpFuses->PPlayTableRev; - PpTable->sThermalController.ucType = ATOM_PP_THERMALCONTROLLER_SUMO; - PpTable->sThermalController.ucFanParameters = ATOM_PP_FANPARAMETERS_NOFAN; - if ((Gfx->AmdPlatformType & AMD_PLATFORM_MOBILE) != 0) { - PpTable->ulPlatformCaps |= ATOM_PP_PLATFORM_CAP_POWERPLAY; - } - PpTable->usStateArrayOffset = offsetof (ATOM_PPLIB_POWERPLAYTABLE3, StateArray); - PpTable->usClockInfoArrayOffset = (USHORT) (offsetof (ATOM_PPLIB_POWERPLAYTABLE3, StateArray) + StateArrayLength); - PpTable->usNonClockInfoArrayOffset = (USHORT) (offsetof (ATOM_PPLIB_POWERPLAYTABLE3, StateArray) + StateArrayLength + ClockArrayLength); - PpTable->sHeader.usStructureSize = (USHORT) (offsetof (ATOM_PPLIB_POWERPLAYTABLE3, StateArray) + StateArrayLength + ClockArrayLength + NonClockArrayLength); - PpTable->usFormatID = 7; - GNB_DEBUG_CODE ( - GfxIntegratedDebugDumpPpTable (PpTable, Gfx); - ); - return AGESA_SUCCESS; -} - -/*----------------------------------------------------------------------------------------*/ -/** - * Dump PP table - * - * - * - * @param[in] PpTable Power Play table - * @param[in] Gfx Gfx configuration info - */ - -VOID -GfxIntegratedDebugDumpPpTable ( - IN ATOM_PPLIB_POWERPLAYTABLE3 *PpTable, - IN GFX_PLATFORM_CONFIG *Gfx - ) -{ - UINTN Index; - UINTN DpmIndex; - ATOM_PPLIB_STATE_V2 *StatesPtr; - NON_CLOCK_INFO_ARRAY *NonClockInfoArrayPtr; - CLOCK_INFO_ARRAY *ClockInfoArrayPtr; - IDS_HDT_CONSOLE (GFX_MISC, " < --- Power Play Table ------ > \n"); - - IDS_HDT_CONSOLE (GFX_MISC, " Table Revision = %d\n", PpTable->ucDataRevision - ); - StatesPtr = PpTable->StateArray.States; - NonClockInfoArrayPtr = (NON_CLOCK_INFO_ARRAY *) ((UINT8 *) PpTable + PpTable->usNonClockInfoArrayOffset); - ClockInfoArrayPtr = (CLOCK_INFO_ARRAY *) ((UINT8 *) PpTable + PpTable->usClockInfoArrayOffset); - for (Index = 0; Index < PpTable->StateArray.ucNumEntries; Index++) { - IDS_HDT_CONSOLE (GFX_MISC, " State #%d\n", Index + 1 - ); - IDS_HDT_CONSOLE (GFX_MISC, " Classification 0x%x\n", - NonClockInfoArrayPtr->NonClockInfo[StatesPtr->nonClockInfoIndex].usClassification - ); - IDS_HDT_CONSOLE (GFX_MISC, " Classification2 0x%x\n", - NonClockInfoArrayPtr->NonClockInfo[StatesPtr->nonClockInfoIndex].usClassification2 - ); - IDS_HDT_CONSOLE (GFX_MISC, " VCLK = %dkHz\n", - NonClockInfoArrayPtr->NonClockInfo[StatesPtr->nonClockInfoIndex].ulVCLK - ); - IDS_HDT_CONSOLE (GFX_MISC, " DCLK = %dkHz\n", - NonClockInfoArrayPtr->NonClockInfo[StatesPtr->nonClockInfoIndex].ulDCLK - ); - IDS_HDT_CONSOLE (GFX_MISC, " DPM State Index: "); - for (DpmIndex = 0; DpmIndex < StatesPtr->ucNumDPMLevels; DpmIndex++) { - IDS_HDT_CONSOLE (GFX_MISC, "%d ", - StatesPtr->ClockInfoIndex [DpmIndex] - ); - } - IDS_HDT_CONSOLE (GFX_MISC, "\n"); - StatesPtr = (ATOM_PPLIB_STATE_V2 *) ((UINT8 *) StatesPtr + sizeof (ATOM_PPLIB_STATE_V2) + StatesPtr->ucNumDPMLevels - 1); - } - for (Index = 0; Index < ClockInfoArrayPtr->ucNumEntries; Index++) { - UINT32 Sclk; - Sclk = ClockInfoArrayPtr->ClockInfo[Index].usEngineClockLow | (ClockInfoArrayPtr->ClockInfo[Index].ucEngineClockHigh << 16); - IDS_HDT_CONSOLE (GFX_MISC, " DPM State #%d\n", - Index - ); - IDS_HDT_CONSOLE (GFX_MISC, " SCLK = %d\n", - ClockInfoArrayPtr->ClockInfo[Index].usEngineClockLow | (ClockInfoArrayPtr->ClockInfo[Index].ucEngineClockHigh << 16) - ); - IDS_HDT_CONSOLE (GFX_MISC, " VID index = %d\n", - ClockInfoArrayPtr->ClockInfo[Index].vddcIndex - ); - IDS_HDT_CONSOLE (GFX_MISC, " tdpLimit = %d\n", - ClockInfoArrayPtr->ClockInfo[Index].tdpLimit - ); - } -} diff --git a/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbGfxInitLibV1/GfxPowerPlayTable.h b/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbGfxInitLibV1/GfxPowerPlayTable.h deleted file mode 100644 index 73c8fd416f..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbGfxInitLibV1/GfxPowerPlayTable.h +++ /dev/null @@ -1,200 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * Service procedure to initialize Power Play Table - * - * - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: GNB - * @e \$Revision: 45407 $ @e \$Date: 2011-01-17 15:28:58 +0800 (Mon, 17 Jan 2011) $ - * - */ -/* -***************************************************************************** -* -* Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* *************************************************************************** -* -*/ -#ifndef _GFXPOWERPLAYTABLE_H_ -#define _GFXPOWERPLAYTABLE_H_ - -#pragma pack (push, 1) - -#define POLICY_LABEL_BATTERY 0x1 -#define POLICY_LABEL_PERFORMANCE 0x2 - -#define MAX_NUM_OF_SW_STATES 10 -#define MAX_NUM_OF_DPM_STATES 10 -#define MAX_NUM_OF_FUSED_DPM_STATES 5 -#define MAX_NUM_OF_FUSED_SW_STATES 6 -/// ATOM_PPLIB_POWERPLAYTABLE::ulPlatformCaps -#define ATOM_PP_PLATFORM_CAP_BACKBIAS 1 -#define ATOM_PP_PLATFORM_CAP_POWERPLAY 2 -#define ATOM_PP_PLATFORM_CAP_SBIOSPOWERSOURCE 4 -#define ATOM_PP_PLATFORM_CAP_ASPM_L0s 8 -#define ATOM_PP_PLATFORM_CAP_ASPM_L1 16 -#define ATOM_PP_PLATFORM_CAP_HARDWAREDC 32 -#define ATOM_PP_PLATFORM_CAP_GEMINIPRIMARY 64 -#define ATOM_PP_PLATFORM_CAP_STEPVDDC 128 -#define ATOM_PP_PLATFORM_CAP_VOLTAGECONTROL 256 -#define ATOM_PP_PLATFORM_CAP_SIDEPORTCONTROL 512 -#define ATOM_PP_PLATFORM_CAP_TURNOFFPLL_ASPML1 1024 -#define ATOM_PP_PLATFORM_CAP_HTLINKCONTROL 2048 -#define ATOM_PP_PLATFORM_CAP_MVDDCONTROL 4096 -#define ATOM_PP_PLATFORM_CAP_GOTO_BOOT_ON_ALERT 0x2000 // Go to boot state on alerts, e.g. on an AC->DC transition. -#define ATOM_PP_PLATFORM_CAP_DONT_WAIT_FOR_VBLANK_ON_ALERT 0x4000 // Do NOT wait for VBLANK during an alert (e.g. AC->DC transition). -#define ATOM_PP_PLATFORM_CAP_VDDCI_CONTROL 0x8000 // Does -#define ATOM_PP_PLATFORM_CAP_REGULATOR_HOT 0x00010000 // Enable the 'regulator hot' feature. -#define ATOM_PP_PLATFORM_CAP_BACO 0x00020000 // Does the driver supports BACO state. - - -#define ATOM_PPLIB_CLASSIFICATION_UI_BATTERY 1 -#define ATOM_PPLIB_CLASSIFICATION_UI_BALANCED 3 -#define ATOM_PPLIB_CLASSIFICATION_UI_PERFORMANCE 5 - -#define ATOM_PPLIB_CLASSIFICATION_BOOT 0x0008 -#define ATOM_PPLIB_CLASSIFICATION_THERMAL 0x0010 -#define ATOM_PPLIB_CLASSIFICATION_LIMITEDPOWERSOURCE 0x0020 -#define ATOM_PPLIB_CLASSIFICATION_REST 0x0040 -#define ATOM_PPLIB_CLASSIFICATION_FORCED 0x0080 -#define ATOM_PPLIB_CLASSIFICATION_3DPERFORMANCE 0x0100 -#define ATOM_PPLIB_CLASSIFICATION_OVERDRIVETEMPLATE 0x0200 -#define ATOM_PPLIB_CLASSIFICATION_UVDSTATE 0x0400 -#define ATOM_PPLIB_CLASSIFICATION_3DLOW 0x0800 -#define ATOM_PPLIB_CLASSIFICATION_ACPI 0x1000 -#define ATOM_PPLIB_CLASSIFICATION_HD2STATE 0x2000 -#define ATOM_PPLIB_CLASSIFICATION_HDSTATE 0x4000 -#define ATOM_PPLIB_CLASSIFICATION_SDSTATE 0x8000 -#define ATOM_PPLIB_CLASSIFICATION_NONUVDSTATE 0x0000 - -#define ATOM_PPLIB_CLASSIFICATION2_MVC 0x0004 //Multi-View - -#define ATOM_PPLIB_ENABLE_VARIBRIGHT 0x00008000 -#define ATOM_PPLIB_ENABLE_DRR 0x00080000 - -#define ATOM_PP_FANPARAMETERS_NOFAN 0x80 -#define ATOM_PP_THERMALCONTROLLER_SUMO 0x0E - -/// DPM state info -typedef struct _ATOM_PPLIB_SUMO_CLOCK_INFO { - USHORT usEngineClockLow; ///< Sclk [15:0] (Sclk in 10khz) - UCHAR ucEngineClockHigh; ///< Sclk [23:16](Sclk in 10khz) - UCHAR vddcIndex; ///< 2-bit VDDC index; - USHORT tdpLimit; ///< TDP Limit - USHORT rsv1; ///< Reserved - ULONG rsv2[2]; ///< Reserved -} ATOM_PPLIB_SUMO_CLOCK_INFO; - -/// Non clock info -typedef struct _ATOM_PPLIB_NONCLOCK_INFO { - USHORT usClassification; ///< State classification see ATOM_PPLIB_CLASSIFICATION_* - UCHAR ucMinTemperature; ///< Reserved - UCHAR ucMaxTemperature; ///< Reserved - ULONG ulCapsAndSettings; ///< Capability Setting (ATOM_PPLIB_ENABLE_DRR or ATOM_PPLIB_ENABLE_VARIBRIGHT or 0) - UCHAR ucRequiredPower; ///< Reserved - USHORT usClassification2; ///< Reserved - ULONG ulVCLK; ///< UVD clocks VCLK unit is in 10KHz - ULONG ulDCLK; ///< UVD clocks DCLK unit is in 10KHz - UCHAR ucUnused[5]; ///< Reserved -} ATOM_PPLIB_NONCLOCK_INFO; - -/// Thermal controller info stub -typedef struct _ATOM_PPLIB_THERMALCONTROLLER { - UCHAR ucType; ///< Reserved. Should be set 0xE - UCHAR ucI2cLine; ///< Reserved. Should be set 0 - UCHAR ucI2cAddress; ///< Reserved. Should be set 0 - UCHAR ucFanParameters; ///< Reserved. Should be set 0x80 - UCHAR ucFanMinRPM; ///< Reserved. Should be set 0 - UCHAR ucFanMaxRPM; ///< Reserved. Should be set 0 - UCHAR ucReserved; ///< Reserved. Should be set 0 - UCHAR ucFlags; ///< Reserved. Should be set 0 -} ATOM_PPLIB_THERMALCONTROLLER; - -/// SW state info -typedef struct _ATOM_PPLIB_STATE_V2 { - UCHAR ucNumDPMLevels; ///< Number of valid DPM levels in this state - UCHAR nonClockInfoIndex; ///< Index to the array of NonClockInfos - UCHAR ClockInfoIndex[1]; ///< Array of DPM states. Actual number calculated during state enumeration -} ATOM_PPLIB_STATE_V2; - -/// SW state Array -typedef struct { - UCHAR ucNumEntries; ///< Number of SW states - ATOM_PPLIB_STATE_V2 States[1]; ///< SW state info. Actual number calculated during state enumeration -} STATE_ARRAY; - -/// Clock info Array -typedef struct { - UCHAR ucNumEntries; ///< Number of ClockInfo entries - UCHAR ucEntrySize; ///< size of ATOM_PPLIB_SUMO_CLOCK_INFO - ATOM_PPLIB_SUMO_CLOCK_INFO ClockInfo[1]; ///< Clock info array. Size will be determined dynamically base on fuses -} CLOCK_INFO_ARRAY; - -/// Non clock info Array -typedef struct { - - UCHAR ucNumEntries; ///< Number of Entries; - UCHAR ucEntrySize; ///< Size of NonClockInfo - ATOM_PPLIB_NONCLOCK_INFO NonClockInfo[1]; ///< Non clock info array -} NON_CLOCK_INFO_ARRAY; - -/// Power Play table -typedef struct _ATOM_PPLIB_POWERPLAYTABLE3 { - ATOM_COMMON_TABLE_HEADER sHeader; ///< Common header - UCHAR ucDataRevision; ///< Revision of PP table - UCHAR Reserved1[4]; ///< Reserved - USHORT usStateArrayOffset; ///< Offset from start of this table to array of ucNumStates ATOM_PPLIB_STATE structures - USHORT usClockInfoArrayOffset; ///< Offset from start of the table to ClockInfoArray - USHORT usNonClockInfoArrayOffset; ///< Offset from Start of the table to NonClockInfoArray - USHORT Reserved2[2]; ///< Reserved - USHORT usTableSize; ///< the size of this structure, or the extended structure - ULONG ulPlatformCaps; ///< See ATOM_PPLIB_CAPS_* - ATOM_PPLIB_THERMALCONTROLLER sThermalController; ///< Thermal controller stub. - USHORT Reserved4[2]; ///< Reserved - UCHAR Reserved5; ///< Reserved - USHORT Reserved6; ///< Reserved - USHORT usFormatID; ///< Format ID - USHORT Reserved7[2]; ///< Reserved - STATE_ARRAY StateArray; ///< Array to hold the states. - CLOCK_INFO_ARRAY ClockInfoArray; ///< Array to hold clock info. - NON_CLOCK_INFO_ARRAY NonClockInfoArray; ///< Array to hold non clock info. -} ATOM_PPLIB_POWERPLAYTABLE3; - -#pragma pack (pop) - - -AGESA_STATUS -GfxPowerPlayBuildTable ( - OUT VOID *Buffer, - IN GFX_PLATFORM_CONFIG *Gfx - ); - - -#endif diff --git a/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbGfxInitLibV1/GnbGfxInitLibV1.c b/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbGfxInitLibV1/GnbGfxInitLibV1.c deleted file mode 100644 index bfd0f31a85..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbGfxInitLibV1/GnbGfxInitLibV1.c +++ /dev/null @@ -1,143 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * Supporting services to collect discrete GFX card info - * - * - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: GNB - * @e \$Revision: 38931 $ @e \$Date: 2010-10-01 15:50:05 -0700 (Fri, 01 Oct 2010) $ - * - */ -/* -***************************************************************************** -* -* Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* *************************************************************************** -* -*/ - -/*---------------------------------------------------------------------------------------- - * M O D U L E S U S E D - *---------------------------------------------------------------------------------------- - */ -#include "AGESA.h" -#include "Ids.h" -#include "amdlib.h" -#include "heapManager.h" -#include "Gnb.h" -#include "GnbGfx.h" -#include "GnbCommonLib.h" -#include "GfxCardInfo.h" -#include "GfxStrapsInit.h" -#include "GnbGfxInitLibV1.h" -#include "Filecode.h" -#define FILECODE PROC_GNB_MODULES_GNBGFXINITLIBV1_GNBGFXINITLIBV1_FILECODE -/*---------------------------------------------------------------------------------------- - * D E F I N I T I O N S A N D M A C R O S - *---------------------------------------------------------------------------------------- - */ - -extern BUILD_OPT_CFG UserOptions; - -/*---------------------------------------------------------------------------------------- - * T Y P E D E F S A N D S T R U C T U R E S - *---------------------------------------------------------------------------------------- - */ - - - -/*---------------------------------------------------------------------------------------- - * P R O T O T Y P E S O F L O C A L F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ - - -/*----------------------------------------------------------------------------------------*/ -/** - * Check if GFX controller fused off - * - * - * @param[in] StdHeader Standard configuration header - * @retval TRUE Gfx controller present and available - */ -BOOLEAN -GfxLibIsControllerPresent ( - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - return GnbLibPciIsDevicePresent (MAKE_SBDFO (0, 0, 1, 0, 0), StdHeader); -} - - -/*----------------------------------------------------------------------------------------*/ -/** - * Init Gfx SSID Registers - * - * - * - * @param[in] Gfx Pointer to global GFX configuration - * @retval AGESA_STATUS Always succeeds - */ - -AGESA_STATUS -GfxInitSsid ( - IN GFX_PLATFORM_CONFIG *Gfx - ) -{ - AGESA_STATUS Status; - UINT32 TempData; - PCI_ADDR IgpuAddress; - PCI_ADDR HdaudioAddress; - - Status = AGESA_SUCCESS; - TempData = 0; - - IgpuAddress = Gfx->GfxPciAddress; - HdaudioAddress = Gfx->GfxPciAddress; - HdaudioAddress.Address.Function = 1; - - // Set SSID for internal GPU - if (UserOptions.CfgGnbIGPUSSID != 0) { - GnbLibPciRMW ((IgpuAddress.AddressValue | 0x4C), AccessS3SaveWidth32, 0, UserOptions.CfgGnbIGPUSSID, GnbLibGetHeader (Gfx)); - } else { - GnbLibPciRead (IgpuAddress.AddressValue, AccessS3SaveWidth32, &TempData, GnbLibGetHeader (Gfx)); - GnbLibPciRMW ((IgpuAddress.AddressValue | 0x4C), AccessS3SaveWidth32, 0, TempData, GnbLibGetHeader (Gfx)); - } - - // Set SSID for internal HD Audio - if (UserOptions.CfgGnbHDAudioSSID != 0) { - GnbLibPciRMW ((HdaudioAddress.AddressValue | 0x4C), AccessS3SaveWidth32, 0, UserOptions.CfgGnbHDAudioSSID, GnbLibGetHeader (Gfx)); - } else { - GnbLibPciRead (HdaudioAddress.AddressValue, AccessS3SaveWidth32, &TempData, GnbLibGetHeader (Gfx)); - GnbLibPciRMW ((HdaudioAddress.AddressValue | 0x4C), AccessS3SaveWidth32, 0, TempData, GnbLibGetHeader (Gfx)); - } - - return Status; -} diff --git a/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbGfxInitLibV1/GnbGfxInitLibV1.h b/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbGfxInitLibV1/GnbGfxInitLibV1.h deleted file mode 100644 index 3d142978cb..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbGfxInitLibV1/GnbGfxInitLibV1.h +++ /dev/null @@ -1,67 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * Gfx Library - * - * - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: GNB - * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $ - * - */ -/* -***************************************************************************** -* -* Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* *************************************************************************** -* -*/ - - -#ifndef _GNBGFXINITLIBV1_H_ -#define _GNBGFXINITLIBV1_H_ - -#include "GnbPcie.h" -#include "GnbGfx.h" -#include "GfxEnumConnectors.h" -#include "GfxPowerPlayTable.h" -#include "GfxCardInfo.h" - -BOOLEAN -GfxLibIsControllerPresent ( - IN AMD_CONFIG_PARAMS *StdHeader - ); - -VOID -GfxGetUmaInfo ( - OUT UMA_INFO *UmaInfo, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -#endif diff --git a/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbGfxInitLibV1/Makefile.inc b/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbGfxInitLibV1/Makefile.inc deleted file mode 100644 index 9611e8df29..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbGfxInitLibV1/Makefile.inc +++ /dev/null @@ -1,4 +0,0 @@ -libagesa-y += GfxCardInfo.c -libagesa-y += GfxEnumConnectors.c -libagesa-y += GfxPowerPlayTable.c -libagesa-y += GnbGfxInitLibV1.c diff --git a/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbNbInitLibV1/GnbNbInitLibV1.c b/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbNbInitLibV1/GnbNbInitLibV1.c deleted file mode 100644 index e668f1bb03..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbNbInitLibV1/GnbNbInitLibV1.c +++ /dev/null @@ -1,400 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * NB services - * - * - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: GNB - * @e \$Revision: 49911 $ @e \$Date: 2011-03-30 17:43:29 +0800 (Wed, 30 Mar 2011) $ - * - */ -/* -***************************************************************************** -* -* Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* *************************************************************************** -* -*/ - -/*---------------------------------------------------------------------------------------- - * M O D U L E S U S E D - *---------------------------------------------------------------------------------------- - */ -#include "AGESA.h" -#include "Ids.h" -#include "amdlib.h" -#include "heapManager.h" -#include "Gnb.h" -#include "GnbFuseTable.h" -#include "GnbCommonLib.h" -#include "GnbNbInitLibV1.h" -#include "GnbRegistersLN.h" -#include "Filecode.h" -#define FILECODE PROC_GNB_MODULES_GNBNBINITLIBV1_GNBNBINITLIBV1_FILECODE -/*---------------------------------------------------------------------------------------- - * D E F I N I T I O N S A N D M A C R O S - *---------------------------------------------------------------------------------------- - */ - - -/*---------------------------------------------------------------------------------------- - * T Y P E D E F S A N D S T R U C T U R E S - *---------------------------------------------------------------------------------------- - */ - - -/*---------------------------------------------------------------------------------------- - * P R O T O T Y P E S O F L O C A L F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ - -/*----------------------------------------------------------------------------------------*/ -/** - * Init NB set top of memory - * - * - * - * @param[in] NbPciAddress Gnb PCI address - * @param[in] StdHeader Standard Configuration Header - */ - -AGESA_STATUS -GnbSetTom ( - IN PCI_ADDR NbPciAddress, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - AGESA_STATUS Status; - UINT64 MsrData; - UINT32 Value; - Status = AGESA_SUCCESS; - //Read memory size below 4G from MSR C001_001A - LibAmdMsrRead (TOP_MEM, &MsrData, StdHeader); - //Write to NB register 0x90 - Value = (UINT32)MsrData & 0xFF800000; //Keep bits 31:23 - GnbLibPciRMW ( - NbPciAddress.AddressValue | D0F0x90_ADDRESS, - AccessS3SaveWidth32, - 0x007FFFFF, - Value, - StdHeader - ); - if (Value == 0) { - Status = AGESA_WARNING; - } - - LibAmdMsrRead (SYS_CFG, &MsrData, StdHeader); - if ((MsrData & BIT21) != 0) { - //Read memory size above 4G from MSR C001_001D - LibAmdMsrRead (TOP_MEM2, &MsrData, StdHeader); - // Write memory size[39:32] to indirect register 1A[7:0] - Value = (UINT32) ((MsrData >> 32) & 0xFF); - GnbLibPciIndirectRMW ( - NbPciAddress.AddressValue | D0F0x60_ADDRESS, - D0F0x64_x1A_ADDRESS | IOC_WRITE_ENABLE, - AccessS3SaveWidth32, - 0xFFFFFF00, - Value, - StdHeader - ); - - // Write memory size[31:23] to indirect register 19[31:23] and enable memory through bit 0 - Value = (UINT32)MsrData & 0xFF800000; //Keep bits 31:23 - Value |= BIT0; // Enable top of memory - GnbLibPciIndirectRMW ( - NbPciAddress.AddressValue | D0F0x60_ADDRESS, - D0F0x64_x19_ADDRESS | IOC_WRITE_ENABLE, - AccessS3SaveWidth32, - 0x007FFFFF, - Value, - StdHeader - ); - } - return Status; -} - - -/*----------------------------------------------------------------------------------------*/ -/** - * Avoid LPC DMA transaction deadlock - * - * - * - * @param[in] NbPciAddress Gnb PCI address - * @param[in] StdHeader Standard Configuration Header - */ - -VOID -GnbLpcDmaDeadlockPrevention ( - IN PCI_ADDR NbPciAddress, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - // For GPP Link core, enable special NP memory write protocol on the processor side PCIE controller - GnbLibPciIndirectRMW ( - NbPciAddress.AddressValue | D0F0xE0_ADDRESS, - CORE_SPACE (1, D0F0xE4_CORE_0010_ADDRESS), - AccessWidth32, - 0xFFFFFFFF, - 1 << D0F0xE4_CORE_0010_UmiNpMemWrite_OFFSET, - StdHeader - ); - - //Enable special NP memory write protocol in ORB - GnbLibPciIndirectRMW ( - NbPciAddress.AddressValue | D0F0x94_ADDRESS, - D0F0x98_x06_ADDRESS | (1 << D0F0x94_OrbIndWrEn_OFFSET), - AccessS3SaveWidth32, - 0xFFFFFFFF, - 1 << D0F0x98_x06_UmiNpMemWrEn_OFFSET, - StdHeader - ); -} - -/*----------------------------------------------------------------------------------------*/ -/** - * NB Dynamic Wake - * ORB_CNB_Wake signal is used to inform the CNB NCLK controller and GNB LCLK controller - * that ORB is (or will soon) push data into the synchronizer FIFO (i.e. wake is high). - * - * @param[in] NbPciAddress Gnb PCI address - * @param[in] StdHeader Standard Configuration Header - */ - -VOID -GnbOrbDynamicWake ( - IN PCI_ADDR NbPciAddress, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - - D0F0x98_x2C_STRUCT D0F0x98_x2C; - - GnbLibPciIndirectRead ( - NbPciAddress.AddressValue | D0F0x94_ADDRESS, - D0F0x98_x2C_ADDRESS | (1 << D0F0x94_OrbIndWrEn_OFFSET), - AccessWidth32, - &D0F0x98_x2C.Value, - StdHeader - ); - - // Enable Dynamic wake - // Wake Hysteresis timer value. Specifies the number of SMU pulses to count. - D0F0x98_x2C.Field.DynWakeEn = 1; - D0F0x98_x2C.Field.WakeHysteresis = 0x64; - - IDS_OPTION_HOOK (IDS_GNB_ORBDYNAMIC_WAKE, &D0F0x98_x2C, StdHeader); - - GnbLibPciIndirectWrite ( - NbPciAddress.AddressValue | D0F0x94_ADDRESS, - D0F0x98_x2C_ADDRESS | (1 << D0F0x94_OrbIndWrEn_OFFSET), - AccessS3SaveWidth32, - &D0F0x98_x2C.Value, - StdHeader - ); -} - -/*----------------------------------------------------------------------------------------*/ -/** - * Lock NB registers - * - * - * - * @param[in] NbPciAddress Gnb PCI address - * @param[in] StdHeader Standard Configuration Header - */ - -VOID -GnbLock ( - IN PCI_ADDR NbPciAddress, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - GnbLibPciIndirectWriteField ( - NbPciAddress.AddressValue | D0F0x60_ADDRESS, - D0F0x64_x00_ADDRESS | IOC_WRITE_ENABLE, - D0F0x64_x00_HwInitWrLock_OFFSET, - D0F0x64_x00_HwInitWrLock_WIDTH, - 0x1, - TRUE, - StdHeader - ); -} - - -/*----------------------------------------------------------------------------------------*/ -/** - * UnitID Clumping - * - * - * @param[in] NbPciAddress Gnb PCI address - * @param[in] StdHeader Standard Configuration Header - */ - -VOID -GnbClumpUnitID ( - IN PCI_ADDR NbPciAddress, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - UINT32 Value; - GnbLibPciRead (MAKE_SBDFO (0, NbPciAddress.Address.Bus, 2, 0, 0), AccessWidth32, &Value, StdHeader); - if (Value != 0xFFFFFFFF) { - GnbLibPciRead (MAKE_SBDFO (0, NbPciAddress.Address.Bus, 3, 0, 0), AccessWidth32, &Value, StdHeader); - if (Value == 0xFFFFFFFF) { - GnbLibPciIndirectRMW ( - NbPciAddress.AddressValue | D0F0x94_ADDRESS, - D0F0x98_x3A_ADDRESS | (1 << D0F0x94_OrbIndWrEn_OFFSET), - AccessS3SaveWidth32, - 0xFFFFFFFF, - 1 << D0F0x98_x3A_ClumpingEn_OFFSET, - StdHeader - ); - } - } -} - -/*----------------------------------------------------------------------------------------*/ -/** - * Get the index of highest SCLK VID - * - * @param[in] StdHeader Standard configuration header - * @retval NBVDD VID index - */ -UINT8 -GnbLocateHighestVidIndex ( - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - UINT8 MaxVid; - UINT8 MaxVidIndex; - UINTN Index; - PP_FUSE_ARRAY *PpFuseArray; - - PpFuseArray = (PP_FUSE_ARRAY *) GnbLocateHeapBuffer (AMD_PP_FUSE_TABLE_HANDLE, StdHeader); - ASSERT (PpFuseArray != NULL); - if (PpFuseArray == NULL) { - IDS_HDT_CONSOLE (GNB_TRACE, " ERROR!!! Heap Location\n"); - return 0; - } - - MaxVidIndex = 0; - MaxVid = 0xff; - for (Index = 0; Index < 4; Index++) { - if (PpFuseArray->SclkVid[Index] != 0 && PpFuseArray->SclkVid[Index] < MaxVid) { - MaxVid = PpFuseArray->SclkVid[Index]; - MaxVidIndex = (UINT8) Index; - } - } - ASSERT (PpFuseArray->SclkVid[MaxVidIndex] != 0); - return MaxVidIndex; -} - -/*----------------------------------------------------------------------------------------*/ -/** - * Get the index of lowest SCLK VID - * - * @param[in] StdHeader Standard configuration header - * @retval NBVDD VID index - */ -UINT8 -GnbLocateLowestVidIndex ( - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - UINT8 MinVidIndex; - UINTN Index; - PP_FUSE_ARRAY *PpFuseArray; - - PpFuseArray = (PP_FUSE_ARRAY *) GnbLocateHeapBuffer (AMD_PP_FUSE_TABLE_HANDLE, StdHeader); - ASSERT (PpFuseArray != NULL); - if (PpFuseArray == NULL) { - IDS_HDT_CONSOLE (GNB_TRACE, " ERROR!!! Heap Location\n"); - return 0; - } - - MinVidIndex = 0; - - for (Index = 0; Index < 4; Index++) { - if (PpFuseArray->SclkVid[Index] > PpFuseArray->SclkVid[MinVidIndex]) { - MinVidIndex = (UINT8) Index; - } - } - ASSERT (PpFuseArray->SclkVid[MinVidIndex] != 0); - return MinVidIndex; -} - -/*----------------------------------------------------------------------------------------*/ -/** - * Get the highest SCLK VID (high voltage) - * - * @param[in] StdHeader Standard configuration header - * @retval NBVDD VID - */ -UINT8 -GnbLocateHighestVidCode ( - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - UINT8 MaxVidIndex; - PP_FUSE_ARRAY *PpFuseArray; - - PpFuseArray = (PP_FUSE_ARRAY *) GnbLocateHeapBuffer (AMD_PP_FUSE_TABLE_HANDLE, StdHeader); - ASSERT (PpFuseArray != NULL); - - MaxVidIndex = GnbLocateHighestVidIndex (StdHeader); - ASSERT (PpFuseArray->SclkVid[MaxVidIndex] != 0); - return PpFuseArray->SclkVid[MaxVidIndex]; - -} - -/*----------------------------------------------------------------------------------------*/ -/** - * Get the lowest SCLK VID (low voltage) - * - * @param[in] StdHeader Standard configuration header - * @retval NBVDD VID - */ -UINT8 -GnbLocateLowestVidCode ( - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - UINT8 MinVidIndex; - PP_FUSE_ARRAY *PpFuseArray; - - PpFuseArray = (PP_FUSE_ARRAY *) GnbLocateHeapBuffer (AMD_PP_FUSE_TABLE_HANDLE, StdHeader); - ASSERT (PpFuseArray != NULL); - MinVidIndex = GnbLocateLowestVidIndex (StdHeader); - ASSERT (PpFuseArray->SclkVid[MinVidIndex] != 0); - return PpFuseArray->SclkVid[MinVidIndex]; -} - - diff --git a/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbNbInitLibV1/GnbNbInitLibV1.h b/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbNbInitLibV1/GnbNbInitLibV1.h deleted file mode 100644 index 87607a5d80..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbNbInitLibV1/GnbNbInitLibV1.h +++ /dev/null @@ -1,99 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * NB services - * - * - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: GNB - * @e \$Revision: 49911 $ @e \$Date: 2011-03-30 17:43:29 +0800 (Wed, 30 Mar 2011) $ - * - */ -/* -***************************************************************************** -* -* Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* *************************************************************************** -* -*/ -#ifndef _GNBNBINITLIBV1_H_ -#define _GNBNBINITLIBV1_H_ - - -AGESA_STATUS -GnbSetTom ( - IN PCI_ADDR NbPciAddress, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -VOID -GnbLpcDmaDeadlockPrevention ( - IN PCI_ADDR NbPciAddress, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -VOID -GnbOrbDynamicWake ( - IN PCI_ADDR NbPciAddress, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -VOID -GnbLock ( - IN PCI_ADDR NbPciAddress, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -VOID -GnbClumpUnitID ( - IN PCI_ADDR NbPciAddress, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -UINT8 -GnbLocateHighestVidIndex ( - IN AMD_CONFIG_PARAMS *StdHeader - ); -UINT8 -GnbLocateLowestVidIndex ( - IN AMD_CONFIG_PARAMS *StdHeader - ); - -UINT8 -GnbLocateHighestVidCode ( - IN AMD_CONFIG_PARAMS *StdHeader - ); - -UINT8 -GnbLocateLowestVidCode ( - IN AMD_CONFIG_PARAMS *StdHeader - ); - -#endif - diff --git a/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbNbInitLibV1/Makefile.inc b/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbNbInitLibV1/Makefile.inc deleted file mode 100644 index 9cd32dbe84..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbNbInitLibV1/Makefile.inc +++ /dev/null @@ -1 +0,0 @@ -libagesa-y += GnbNbInitLibV1.c diff --git a/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieAlibV1/Makefile.inc b/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieAlibV1/Makefile.inc deleted file mode 100644 index 8a251f6208..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieAlibV1/Makefile.inc +++ /dev/null @@ -1 +0,0 @@ -libagesa-y += PcieAlib.c diff --git a/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieAlibV1/PcieAlib.c b/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieAlibV1/PcieAlib.c deleted file mode 100644 index 333f46c4eb..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieAlibV1/PcieAlib.c +++ /dev/null @@ -1,439 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * PCIe ALIB - * - * - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: GNB - * @e \$Revision: 49916 $ @e \$Date: 2011-03-30 19:03:54 +0800 (Wed, 30 Mar 2011) $ - * - */ -/* -***************************************************************************** -* -* Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* *************************************************************************** -* -*/ - -/*---------------------------------------------------------------------------------------- - * M O D U L E S U S E D - *---------------------------------------------------------------------------------------- - */ - - -#include "AGESA.h" -#include "Ids.h" -#include "amdlib.h" -#include "heapManager.h" -#include "cpuLateInit.h" -#include "cpuRegisters.h" -#include "Gnb.h" -#include "GnbPcie.h" -#include "GnbPcieFamServices.h" -#include "GnbCommonLib.h" -#include "GnbPcieConfig.h" -#include "GnbPcieInitLibV1.h" -#include "GnbNbInitLibV1.h" -#include "GnbRegistersLN.h" -#include "OptionGnb.h" -#include "PcieAlib.h" -#include "GnbFuseTable.h" -#include "Filecode.h" -#define FILECODE PROC_GNB_MODULES_GNBPCIEALIBV1_PCIEALIB_FILECODE -/*---------------------------------------------------------------------------------------- - * D E F I N I T I O N S A N D M A C R O S - *---------------------------------------------------------------------------------------- - */ - -extern UINT8 AlibSsdt[]; - -/*---------------------------------------------------------------------------------------- - * T Y P E D E F S A N D S T R U C T U R E S - *---------------------------------------------------------------------------------------- - */ - - -/*---------------------------------------------------------------------------------------- - * P R O T O T Y P E S O F L O C A L F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ - -VOID -STATIC -PcieAlibSetPortMaxSpeedCallback ( - IN PCIe_ENGINE_CONFIG *Engine, - IN OUT VOID *Buffer, - IN PCIe_PLATFORM_CONFIG *Pcie - ); - -VOID -STATIC -PcieAlibSetPortOverrideSpeedCallback ( - IN PCIe_ENGINE_CONFIG *Engine, - IN OUT VOID *Buffer, - IN PCIe_PLATFORM_CONFIG *Pcie - ); - -VOID -STATIC -PcieAlibSetPortInfoCallback ( - IN PCIe_ENGINE_CONFIG *Engine, - IN OUT VOID *Buffer, - IN PCIe_PLATFORM_CONFIG *Pcie - ); - -AGESA_STATUS -PcieAlibBuildAcpiTable ( - IN AMD_CONFIG_PARAMS *StdHeader, - OUT VOID **AlibSsdtPtr - ); - -VOID -STATIC -PcieAlibSetSclkVid ( - IN OUT VOID *Buffer, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -/*----------------------------------------------------------------------------------------*/ -/** - * Create ACPI ALIB SSDT table - * - * - * - * @param[in] StdHeader Standard configuration header - * @retval AGESA_STATUS - */ - -AGESA_STATUS -PcieAlibFeature ( - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - AMD_LATE_PARAMS *LateParamsPtr; - LateParamsPtr = (AMD_LATE_PARAMS*) StdHeader; - return PcieAlibBuildAcpiTable (StdHeader, &LateParamsPtr->AcpiAlib); -} - -/*----------------------------------------------------------------------------------------*/ -/** - * Build ALIB ACPI table - * - * - * - * @param[in] StdHeader Standard Configuration Header - * @param[in,out] AlibSsdtPtr Pointer to pointer to ALIB SSDT table - * @retval AGESA_SUCCESS - * @retval AGESA_ERROR - */ - -AGESA_STATUS -PcieAlibBuildAcpiTable ( - IN AMD_CONFIG_PARAMS *StdHeader, - OUT VOID **AlibSsdtPtr - ) -{ - AGESA_STATUS Status; - AGESA_STATUS AgesaStatus; - UINT32 AmlObjName; - PCIe_PLATFORM_CONFIG *Pcie; - PP_FUSE_ARRAY *PpFuseArray; - VOID *AlibSsdtBuffer; - VOID *AmlObjPtr; - UINT8 BootUpVidIndex; - UINT8 Gen1VidIndex; - UINTN AlibSsdtlength; - IDS_HDT_CONSOLE (GNB_TRACE, "PcieAlibBuildAcpiTable Enter\n"); - AgesaStatus = AGESA_SUCCESS; - AlibSsdtlength = ((ACPI_TABLE_HEADER*) &AlibSsdt[0])->TableLength; - if (*AlibSsdtPtr == NULL) { - AlibSsdtBuffer = GnbAllocateHeapBuffer ( - AMD_ACPI_ALIB_BUFFER_HANDLE, - AlibSsdtlength, - StdHeader - ); - ASSERT (AlibSsdtBuffer != NULL); - if (AlibSsdtBuffer == NULL) { - return AGESA_ERROR; - } - *AlibSsdtPtr = AlibSsdtBuffer; - } else { - AlibSsdtBuffer = *AlibSsdtPtr; - } - // Copy template to buffer - LibAmdMemCopy (AlibSsdtBuffer, &AlibSsdt[0], AlibSsdtlength, StdHeader); - // Set PCI MMIO configuration -// AmlObjName = '10DA'; - AmlObjName = Int32FromChar ('1', '0', 'D', 'A'); - AmlObjPtr = GnbLibFind (AlibSsdtBuffer, AlibSsdtlength, (UINT8*) &AmlObjName, sizeof (AmlObjName)); - ASSERT (AmlObjPtr != NULL); - if (AmlObjPtr != NULL) { - UINT64 LocalMsrRegister; - LibAmdMsrRead (MSR_MMIO_Cfg_Base, &LocalMsrRegister, StdHeader); - if ((LocalMsrRegister & BIT0) != 0 && (LocalMsrRegister & 0xFFFFFFFF00000000ull) == 0) { - *(UINT32*)((UINT8*) AmlObjPtr + 5) = (UINT32)(LocalMsrRegister & 0xFFFFF00000ull); - } else { - AgesaStatus = AGESA_FATAL; - } - } else { - AgesaStatus = AGESA_FATAL; - } - // Set voltage configuration - PpFuseArray = GnbLocateHeapBuffer (AMD_PP_FUSE_TABLE_HANDLE, StdHeader); - ASSERT (PpFuseArray != NULL); - if (PpFuseArray != NULL) { -// AmlObjName = '30DA'; - AmlObjName = Int32FromChar ('3', '0', 'D', 'A'); - AmlObjPtr = GnbLibFind (AlibSsdtBuffer, AlibSsdtlength, (UINT8*) &AmlObjName, sizeof (AmlObjName)); - ASSERT (AmlObjPtr != NULL); - if (AmlObjPtr != NULL) { - *(UINT8*)((UINT8*) AmlObjPtr + 5) = PpFuseArray->PcieGen2Vid; - } else { - AgesaStatus = AGESA_FATAL; - } - } else { - AgesaStatus = AGESA_FATAL; - } - - Gen1VidIndex = GnbLocateLowestVidIndex (StdHeader); - BootUpVidIndex = GnbLocateHighestVidIndex (StdHeader); -// AmlObjName = '40DA'; - AmlObjName = Int32FromChar ('4', '0', 'D', 'A'); - AmlObjPtr = GnbLibFind (AlibSsdtBuffer, AlibSsdtlength, (UINT8*) &AmlObjName, sizeof (AmlObjName)); - ASSERT (AmlObjPtr != NULL); - if (AmlObjPtr != NULL) { - *(UINT8*)((UINT8*) AmlObjPtr + 5) = Gen1VidIndex; - } else { - AgesaStatus = AGESA_FATAL; - } -// AmlObjName = '50DA'; - AmlObjName = Int32FromChar ('5', '0', 'D', 'A'); - AmlObjPtr = GnbLibFind (AlibSsdtBuffer, AlibSsdtlength, (UINT8*) &AmlObjName, sizeof (AmlObjName)); - ASSERT (AmlObjPtr != NULL); - if (AmlObjPtr != NULL) { - *(UINT8*)((UINT8*) AmlObjPtr + 5) = BootUpVidIndex; - } else { - AgesaStatus = AGESA_FATAL; - } -// AmlObjName = '01DA'; - AmlObjName = Int32FromChar ('0', '1', 'D', 'A'); - AmlObjPtr = GnbLibFind (AlibSsdtBuffer, AlibSsdtlength, (UINT8*) &AmlObjName, sizeof (AmlObjName)); - ASSERT (AmlObjPtr != NULL); - if (AmlObjPtr != NULL) { - PcieAlibSetSclkVid ((UINT8*) ((UINT8*)AmlObjPtr + 7), StdHeader); - } else { - Status = AGESA_ERROR; - } - // Set PCIe configuration - if (PcieLocateConfigurationData (StdHeader, &Pcie) == AGESA_SUCCESS) { -// AmlObjName = '20DA'; - AmlObjName = Int32FromChar ('2', '0', 'D', 'A'); - AmlObjPtr = GnbLibFind (AlibSsdtBuffer, AlibSsdtlength, (UINT8*) &AmlObjName, sizeof (AmlObjName)); - ASSERT (AmlObjPtr != NULL); - if (AmlObjPtr != NULL) { - *(UINT8*)((UINT8*) AmlObjPtr + 5) = Pcie->PsppPolicy; - } else { - AgesaStatus = AGESA_FATAL; - } -// AmlObjName = '60DA'; - AmlObjName = Int32FromChar ('6', '0', 'D', 'A'); - AmlObjPtr = GnbLibFind (AlibSsdtBuffer, AlibSsdtlength, (UINT8*) &AmlObjName, sizeof (AmlObjName)); - ASSERT (AmlObjPtr != NULL); - if (AmlObjPtr != NULL) { - PcieConfigRunProcForAllEngines ( - DESCRIPTOR_ALLOCATED | DESCRIPTOR_PCIE_ENGINE, - PcieAlibSetPortMaxSpeedCallback, - (UINT8*)((UINT8*) AmlObjPtr + 7), - Pcie - ); - } else { - AgesaStatus = AGESA_FATAL; - } -// AmlObjName = '60DA'; - AmlObjName = Int32FromChar ('6', '0', 'D', 'A'); - AmlObjPtr = GnbLibFind (AlibSsdtBuffer, AlibSsdtlength, (UINT8*) &AmlObjName, sizeof (AmlObjName)); - ASSERT (AmlObjPtr != NULL); - if (AmlObjPtr != NULL) { - PcieConfigRunProcForAllEngines ( - DESCRIPTOR_ALLOCATED | DESCRIPTOR_PCIE_ENGINE, - PcieAlibSetPortOverrideSpeedCallback, - (UINT8*)((UINT8*) AmlObjPtr + 7), - Pcie - ); - } else { - AgesaStatus = AGESA_FATAL; - } -// AmlObjName = '70DA'; - AmlObjName = Int32FromChar ('7', '0', 'D', 'A'); - AmlObjPtr = GnbLibFind (AlibSsdtBuffer, AlibSsdtlength, (UINT8*) &AmlObjName, sizeof (AmlObjName)); - ASSERT (AmlObjPtr != NULL); - if (AmlObjPtr != NULL) { - PcieConfigRunProcForAllEngines ( - DESCRIPTOR_ALLOCATED | DESCRIPTOR_PCIE_ENGINE, - PcieAlibSetPortInfoCallback, - (UINT8*)((UINT8*) AmlObjPtr + 4), - Pcie - ); - } else { - AgesaStatus = AGESA_FATAL; - } - } else { - ASSERT (FALSE); - AgesaStatus = AGESA_ERROR; - } - Status = PcieFmAlibBuildAcpiTable (AlibSsdtBuffer, StdHeader); - AGESA_STATUS_UPDATE (Status, AgesaStatus); - if (AgesaStatus != AGESA_SUCCESS) { - //Shrink table length to size of the header - ((ACPI_TABLE_HEADER*) AlibSsdtBuffer)->TableLength = sizeof (ACPI_TABLE_HEADER); - } - ChecksumAcpiTable ((ACPI_TABLE_HEADER*) AlibSsdtBuffer, StdHeader); - IDS_HDT_CONSOLE (GNB_TRACE, "PcieAlibBuildAcpiTable Exit [0x%x]\n", AgesaStatus); - return AgesaStatus; -} - -/*----------------------------------------------------------------------------------------*/ -/** - * Callback to init max port speed capability - * - * - * - * - * @param[in] Engine Pointer to engine config descriptor - * @param[in, out] Buffer Not used - * @param[in] Pcie Pointer to global PCIe configuration - * - */ - -VOID -STATIC -PcieAlibSetPortMaxSpeedCallback ( - IN PCIe_ENGINE_CONFIG *Engine, - IN OUT VOID *Buffer, - IN PCIe_PLATFORM_CONFIG *Pcie - ) -{ - UINT8 *PsppMaxPortSpeedPackage; - PsppMaxPortSpeedPackage = (UINT8*) Buffer; - if (Engine->Type.Port.PortData.LinkHotplug != HotplugDisabled || PcieConfigCheckPortStatus (Engine, INIT_STATUS_PCIE_TRAINING_SUCCESS)) { - PsppMaxPortSpeedPackage[(Engine->Type.Port.Address.Address.Device - 2) * 2 + 1] = (UINT8) PcieFmGetLinkSpeedCap (PCIE_PORT_GEN_CAP_MAX, Engine); - } -} - -/*----------------------------------------------------------------------------------------*/ -/** - * Callback to init max port speed capability - * - * - * - * - * @param[in] Engine Pointer to engine config descriptor - * @param[in, out] Buffer Not used - * @param[in] Pcie Pointer to global PCIe configuration - * - */ - -VOID -STATIC -PcieAlibSetPortOverrideSpeedCallback ( - IN PCIe_ENGINE_CONFIG *Engine, - IN OUT VOID *Buffer, - IN PCIe_PLATFORM_CONFIG *Pcie - ) -{ - UINT8 *PsppOverridePortSpeedPackage; - PsppOverridePortSpeedPackage = (UINT8*) Buffer; - if (Engine->Type.Port.PortData.LinkHotplug != HotplugDisabled || PcieConfigCheckPortStatus (Engine, INIT_STATUS_PCIE_TRAINING_SUCCESS)) { - PsppOverridePortSpeedPackage[(Engine->Type.Port.Address.Address.Device - 2) * 2 + 1] = Engine->Type.Port.PortData.MiscControls.LinkSafeMode; - } - if (Engine->Type.Port.PortData.LinkHotplug == HotplugBasic && !PcieConfigCheckPortStatus (Engine, INIT_STATUS_PCIE_TRAINING_SUCCESS)) { - PsppOverridePortSpeedPackage[(Engine->Type.Port.Address.Address.Device - 2) * 2 + 1] = PcieGen1; - } -} - -/*----------------------------------------------------------------------------------------*/ -/** - * Callback to init port info - * - * - * - * - * @param[in] Engine Pointer to engine config descriptor - * @param[in, out] Buffer Not used - * @param[in] Pcie Pointer to global PCIe configuration - * - */ - -VOID -STATIC -PcieAlibSetPortInfoCallback ( - IN PCIe_ENGINE_CONFIG *Engine, - IN OUT VOID *Buffer, - IN PCIe_PLATFORM_CONFIG *Pcie - ) -{ - ALIB_PORT_INFO_PACKAGE *PortInfoPackage; - UINT8 PortIndex; - PortInfoPackage = (ALIB_PORT_INFO_PACKAGE*) Buffer; - PortIndex = (UINT8) Engine->Type.Port.Address.Address.Device - 2; - PortInfoPackage->PortInfo[PortIndex].StartPhyLane = (UINT8) Engine->EngineData.StartLane; - PortInfoPackage->PortInfo[PortIndex].EndPhyLane = (UINT8) Engine->EngineData.EndLane; - PortInfoPackage->PortInfo[PortIndex].StartCoreLane = (UINT8) Engine->Type.Port.StartCoreLane; - PortInfoPackage->PortInfo[PortIndex].EndCoreLane = (UINT8) Engine->Type.Port.EndCoreLane; - PortInfoPackage->PortInfo[PortIndex].PortId = Engine->Type.Port.PortId; - PortInfoPackage->PortInfo[PortIndex].WrapperId = 0x0130 + (UINT16)(PcieConfigGetParentWrapper (Engine)->WrapId); - PortInfoPackage->PortInfo[PortIndex].LinkHotplug = Engine->Type.Port.PortData.LinkHotplug; - PortInfoPackage->PortInfo[PortIndex].MaxSpeedCap = (UINT8) PcieFmGetLinkSpeedCap (PCIE_PORT_GEN_CAP_MAX, Engine); -} - -VOID -STATIC -PcieAlibSetSclkVid ( - IN OUT VOID *Buffer, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - UINT8 *SclkVid; - PP_FUSE_ARRAY *PpFuseArray; - UINT8 Index; - - SclkVid = (UINT8*) Buffer; - PpFuseArray = (PP_FUSE_ARRAY *) GnbLocateHeapBuffer (AMD_PP_FUSE_TABLE_HANDLE, StdHeader); - ASSERT (PpFuseArray != NULL); - if (PpFuseArray == NULL) { - IDS_HDT_CONSOLE (GNB_TRACE, " ERROR!!! Heap Location\n"); - return; - } - - for (Index = 0; Index < 4; Index++) { - SclkVid[Index * 2 + 1] = PpFuseArray->SclkVid[Index]; - } -} diff --git a/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieAlibV1/PcieAlib.h b/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieAlibV1/PcieAlib.h deleted file mode 100644 index b723c57e7e..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieAlibV1/PcieAlib.h +++ /dev/null @@ -1,82 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * PCIe ALIB - * - * - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: GNB - * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $ - * - */ -/* -***************************************************************************** -* -* Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* *************************************************************************** -* -*/ - -#ifndef _PCIEALIB_H_ -#define _PCIEALIB_H_ - -#pragma pack (push, 1) -///Port info asl buffer -typedef struct { - UINT8 BufferOp; ///< Opcode - UINT8 PkgLength; ///< Package length - UINT8 BufferSize; ///< Buffer size - UINT8 ByteList; ///< Byte lisy - UINT8 StartPhyLane; ///< Port Start PHY lane - UINT8 EndPhyLane; ///< Port End PHY lane - UINT8 StartCoreLane; ///< Port Start Core lane - UINT8 EndCoreLane; ///< Port End Core lane - UINT8 PortId; ///< Port ID - UINT16 WrapperId; ///< Wrapper ID - UINT8 LinkHotplug; ///< Link hotplug type - UINT8 MaxSpeedCap; ///< Max port speed capability - UINT8 Reserved[1]; ///< Reserved -} ALIB_PORT_INFO_BUFFER; -///Ports info asl package -typedef struct { - UINT8 PackageOp; ///< Opcode - UINT8 PkgLength; ///< Package length - UINT8 NumElements; ///< number of elements - UINT8 PackageElementList; ///< package element list - ALIB_PORT_INFO_BUFFER PortInfo[7]; ///< Array of port info buffers -} ALIB_PORT_INFO_PACKAGE; - -#pragma pack (pop) - -AGESA_STATUS -PcieAlibFeature ( - IN AMD_CONFIG_PARAMS *StdHeader - ); - -#endif diff --git a/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieAlibV1/PcieAlibConfig.esl b/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieAlibV1/PcieAlibConfig.esl deleted file mode 100644 index a8763dab8f..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieAlibV1/PcieAlibConfig.esl +++ /dev/null @@ -1,107 +0,0 @@ -/** - * @file - * - * ALIB PSPP config - * - * - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: GNB - * @e \$Revision: 49214 $ @e \$Date: 2011-03-19 07:05:12 +0800 (Sat, 19 Mar 2011) $ - * - */ -/* -***************************************************************************** -* -* Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* *************************************************************************** -* -*/ - -#ifndef _PCIEALIBCONFIG_H_ -#define _PCIEALIBCONFIG_H_ - -//#define PCIE_PHY_LANE_POWER_GATE_SUPPORT -// #define PCIE_DISABLE_UNUSED_LANES_ON_ACTIVE_LINK - -#define DEF_OFFSET_START_CORE_LANE 2 -#define DEF_OFFSET_END_CORE_LANE 3 -#define DEF_OFFSET_START_PHY_LANE 0 -#define DEF_OFFSET_END_PHY_LANE 1 -#define DEF_OFFSET_PORT_ID 4 -#define DEF_OFFSET_WRAPPER_ID 5 -#define DEF_OFFSET_LINK_HOTPLUG 7 -#define DEF_OFFSET_GEN2_CAP 8 -#define DEF_BASIC_HOTPLUG 1 - -#define DEF_PSPP_POLICY_START 1 -#define DEF_PSPP_POLICY_STOP 0 -#define DEF_PSPP_POLICY_PERFORMANCE 1 -#define DEF_PSPP_POLICY_BALANCEHIGH 2 -#define DEF_PSPP_POLICY_BALANCELOW 3 -#define DEF_PSPP_POLICY_POWERSAVING 4 -#define DEF_PSPP_STATE_AC 0 -#define DEF_PSPP_STATE_DC 1 - -#define DEF_TRAINING_STATE_COMPLETE 0 -#define DEF_TRAINING_STATE_DETECT_PRESENCE 1 -#define DEF_TRAINING_STATE_PRESENCE_DETECTED 2 -#define DEF_TRAINING_GEN2_WORKAROUND 3 -#define DEF_TRAINING_STATE_NOT_PRESENT 4 -#define DEF_TRAINING_DEVICE_PRESENT 5 -#define DEF_TRAINING_STATE_RELEASE_TRAINING 6 -#define DEF_TRAINING_STATE_REQUEST_RESET 7 -#define DEF_TRAINING_STATE_EXIT 8 - -#define DEF_LINK_SPEED_GEN1 1 -#define DEF_LINK_SPEED_GEN2 2 - -#define DEF_HOTPLUG_STATUS_DEVICE_NOT_PRESENT 0 -#define DEF_HOTPLUG_STATUS_DEVICE_PRESENT 1 - -#define DEF_PORT_NOT_ALLOCATED 0 -#define DEF_PORT_ALLOCATED 1 - -#define DEF_PCIE_LANE_POWERON 1 -#define DEF_PCIE_LANE_POWEROFF 0 -#define DEF_PCIE_LANE_POWEROFFUNUSED 2 - -#define DEF_SCARTCH_PSPP_START_OFFSET 0 -#define DEF_SCARTCH_PSPP_POLICY_OFFSET 1 -#define DEF_SCARTCH_PSPP_ACDC_OFFSET 5 -#define DEF_SCARTCH_PSPP_ACDC_OVR_OFFSET 6 -#define DEF_SCARTCH_PSPP_REQ_OFFSET 16 - -#define DEF_LINKWIDTH_ACTIVE 0 -#define DEF_LINKWIDTH_MAX_PHY 1 - - - -#define TRUE 1 -#define FALSE 0 - -#endif diff --git a/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieAlibV1/PcieAlibCore.esl b/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieAlibV1/PcieAlibCore.esl deleted file mode 100644 index 782a06fbce..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieAlibV1/PcieAlibCore.esl +++ /dev/null @@ -1,359 +0,0 @@ -/** - * @file - * - * ALIB ASL library - * - * - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: GNB - * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $ - * - */ -/* -***************************************************************************** -* -* Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* *************************************************************************** -* -*/ - - - /*----------------------------------------------------------------------------------------*/ - /** - * PCIe MMIO Base address - * - */ - - Name ( - AD01, - 0xE0000000 - ) - - Alias ( - AD01, - varPcieBase - ) - - - - /*----------------------------------------------------------------------------------------*/ - /** - * PCIe port info - * - */ - - Name ( - AD07, - Package () { - Buffer () {0,0,0,0,0,0,0,0,0,0}, //dev2 - Buffer () {0,0,0,0,0,0,0,0,0,0}, //dev3 - Buffer () {0,0,0,0,0,0,0,0,0,0}, //dev4 - Buffer () {0,0,0,0,0,0,0,0,0,0}, //dev5 - Buffer () {0,0,0,0,0,0,0,0,0,0}, //dev6 - Buffer () {0,0,0,0,0,0,0,0,0,0}, //dev7 - Buffer () {0,0,0,0,0,0,0,0,0,0}, //dev8 - Buffer () {0,0,0,0,0,0,0,0,0,0}, //dev9 - } - ) - - Alias ( - AD07, - varPortInfo - ) - - - Name (varStringBuffer, Buffer (256) {}) - - /*----------------------------------------------------------------------------------------*/ - /** - * Master control method - * - * Arg0 - Function ID - * Arg1 - Function specific data buffer - */ - Method (ALIB, 2, NotSerialized) { - If (Lequal (Arg0, 0x1)) { - return (procPsppReportAcDsState (Arg1)) - } - If (LEqual (Arg0, 0x2)) { - return (procPsppPerformanceRequest (Arg1)) - } - If (LEqual (Arg0, 0x3)) { - return (procPsppControl (Arg1)) - } - If (LEqual (Arg0, 0x4)) { - return (procPcieSetBusWidth (Arg1)) - } - If (LEqual (Arg0, 0x5)) { - return (procAlibInit ()) - } - If (LEqual (Arg0, 0x6)) { - return (procPciePortHotplug (Arg1)) - } - return (0) - } - - /*----------------------------------------------------------------------------------------*/ - /** - * Alib Init - * - * - */ - Method (procAlibInit, 0, Serialized) { - - return (0) - } - - /*----------------------------------------------------------------------------------------*/ - /** - * Read PCI config register through MMIO - * - * Arg0 - PCI address Bus/device/func - * Arg1 - Register offset - */ - Method (procPciDwordRead, 2, Serialized) { - Add (varPcieBase, ShiftLeft (Arg0, 12), Local0) - Add (Arg1, Local0, Local0) - OperationRegion(varOperationRegionMmio, SystemMemory, Local0, 0x4) - Field(varOperationRegionMmio, DWordAcc, NoLock, Preserve) { - Offset (0x0), - varPciReg32, 32, - } - return (varPciReg32) - } - /*----------------------------------------------------------------------------------------*/ - /** - * Write PCI config register through MMIO - * - * Arg0 - PCI address Bus/device/func - * Arg1 - Register offset - * Arg2 - Value - */ - Method (procPciDwordWrite, 3, Serialized) { - Add (varPcieBase, ShiftLeft (Arg0, 12), Local0) - Add (Arg1, Local0, Local0) - OperationRegion(varOperationRegionMmio, SystemMemory, Local0, 0x4) - Field(varOperationRegionMmio, DWordAcc, NoLock, Preserve) { - Offset (0x0), - varPciReg32, 32, - } - Store (Arg2, varPciReg32) - } - /*----------------------------------------------------------------------------------------*/ - /** - * Write PCI config register through MMIO - * - * Arg0 - PCI address Bus/device/func - * Arg1 - Register offset - * Arg2 - AND mask - * Arg3 - OR mask - */ - Method (procPciDwordRMW, 4, Serialized) { - Store (procPciDwordRead (Arg0, Arg1), Local0) - Or (And (Local0, Arg2), Arg3, Local0) - procPciDwordWrite (Arg0, Arg1, Local0) - } - - Mutex(varPciePortAccessMutex, 0) - /*----------------------------------------------------------------------------------------*/ - /** - * Read PCIe port indirect register - * - * Arg0 - Port Index - * Arg1 - Register offset - * - */ - Method (procPciePortIndirectRegisterRead, 2, NotSerialized) { - Acquire(varPciePortAccessMutex, 0xFFFF) - Store (ShiftLeft (Add( Arg0, 2), 3), Local0) - procPciDwordWrite (Local0, 0xe0, Arg1) - Store (procPciDwordRead (Local0, 0xe4), Local0) - Release (varPciePortAccessMutex) - return (Local0) - } - - /*----------------------------------------------------------------------------------------*/ - /** - * Write PCIe port indirect register - * - * Arg0 - Port Index - * Arg1 - Register offset - * Arg2 - Value - */ - Method (procPciePortIndirectRegisterWrite, 3, NotSerialized) { - Acquire(varPciePortAccessMutex, 0xFFFF) - Store (ShiftLeft (Add( Arg0, 2), 3), Local0) - procPciDwordWrite (Local0, 0xe0, Arg1) - procPciDwordWrite (Local0, 0xe4, Arg2) - Release (varPciePortAccessMutex) - } - /*----------------------------------------------------------------------------------------*/ - /** - * Read PCIe port indirect register - * - * Arg0 - Port Index - * Arg1 - Register offset - * Arg2 - AND Mask - * Arg3 - OR Mask - * - */ - Method (procPciePortIndirectRegisterRMW, 4, NotSerialized) { - Store (procPciePortIndirectRegisterRead (Arg0, Arg1), Local0) - Or (And (Local0, Arg2), Arg3, Local0) - procPciePortIndirectRegisterWrite (Arg0, Arg1, Local0) - } - Mutex(varHostAccessMutex, 0) - /*----------------------------------------------------------------------------------------*/ - /** - * Read PCIe port indirect register - * - * Arg0 - BDF - * Arg1 - Register offset - * Arg2 - Register address - * - */ - Method (procIndirectRegisterRead, 3, NotSerialized) { - Acquire(varHostAccessMutex, 0xFFFF) - procPciDwordWrite (Arg0, Arg1, Arg2) - Store (procPciDwordRead (Arg0, Add (Arg1, 4)), Local0) - Release(varHostAccessMutex) - return (Local0) - } - - /*----------------------------------------------------------------------------------------*/ - /** - * Write PCIe port indirect register - * - * Arg0 - BDF - * Arg1 - Register offset - * Arg2 - Register address - * Arg3 - Value - */ - Method (procIndirectRegisterWrite, 4, NotSerialized) { - Acquire(varHostAccessMutex, 0xFFFF) - procPciDwordWrite (Arg0, Arg1, Arg2) - procPciDwordWrite (Arg0, Add (Arg1, 4), Arg3) - Release(varHostAccessMutex) - } - - /*----------------------------------------------------------------------------------------*/ - /** - * Read Modify Write indirect registers - * - * Arg0 - BDF - * Arg1 - Register Offset - * Arg2 - Register Address - * Arg3 - AND Mask - * Arg4 - OR Mask - * - */ - Method (procIndirectRegisterRMW, 5, NotSerialized) { - Store (procIndirectRegisterRead (Arg0, Arg1, Arg2), Local0) - Or (And (Local0, Arg3), Arg4, Local0) - procIndirectRegisterWrite (Arg0, Arg1, Arg2, Local0) - } - - /*----------------------------------------------------------------------------------------*/ - /** - * - * - * Arg0 - Port ID - * Retval - buffer that represent port data set - */ - Method (procPcieGetPortInfo, 1, NotSerialized) { - return (DeRefOf (Index (varPortInfo, Arg0))) - } - - /*----------------------------------------------------------------------------------------*/ - /** - * Find Pci Capability - * - * Arg0 - PCI address Bus/device/func - * Arg1 - Capability id - */ - Method (procFindPciCapability, 2, NotSerialized) { - Store (0x34, Local1) - if (LEqual (procPciDwordRead (Arg0, 0x0), 0xFFFFFFFF)) { - // Device not present - return (0) - } - Store (1, Local0) - while (LEqual (Local0, 1)) { - Store (And (procPciDwordRead (Arg0, Local1), 0xFF), Local1) - if (LEqual (Local1, 0)) { - break - } - if (LEqual (And (procPciDwordRead (Arg0, Local1), 0xFF), Arg1)) { - Store (0, Local0) - } else { - Increment (Local1) - } - } - return (Local1) - } - - /*----------------------------------------------------------------------------------------*/ - /** - * - * - * Arg0 - Aspm - * Arg1 - 0: Read, 1: Write - */ - Method (procPcieSbAspmControl, 2, Serialized) { - // Create an opregion for PM IO Registers - OperationRegion (PMIO, SystemIO, 0xCD6, 0x2) - Field (PMIO, ByteAcc, NoLock, Preserve) - { - PMRI, 8, - PMRD, 8 - } - IndexField (PMRI, PMRD, ByteAcc, NoLock, Preserve) - { - Offset(0xE0), // IO Base address of A-Link Express/ A-Link Bridge register - ABAR, 32, - } - OperationRegion (ACFG, SystemIO, ABAR, 0x8) - Field (ACFG, DWordAcc, Nolock, Preserve) //AB_INDX/AB_DATA - { - ABIX, 32, - ABDA, 32 - } - - Store (0, Local0) - if (LEqual (Arg1, 0)) { - Store (0x80000068, ABIX) - Store (ABDA, Local0) - return (Local0) - } else { - Store (0x80000068, ABIX) - Store (ABDA, Local0) - Or (And (Local0, 0xfffffffc), Arg0, Local0) - Store (Local0, ABDA) - } - } - diff --git a/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieAlibV1/PcieAlibHotplug.esl b/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieAlibV1/PcieAlibHotplug.esl deleted file mode 100644 index e8cdb9e6a5..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieAlibV1/PcieAlibHotplug.esl +++ /dev/null @@ -1,532 +0,0 @@ -/** - * @file - * - * ALIB ASL library - * - * - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: GNB - * @e \$Revision: 49874 $ @e \$Date: 2011-03-30 11:18:34 +0800 (Wed, 30 Mar 2011) $ - * - */ -/* -***************************************************************************** -* -* Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* *************************************************************************** -* -*/ - - External(\_SB.ALIC, MethodObj) - - Name (varStartPhyLane, 0) - Name (varEndPhyLane, 0) - Name (varStartCoreLane, 0) - Name (varEndCoreLane, 0) - Name (varWrapperId, 0) - Name (varPortId, 0) - - Name (varNormalizeLinkWidthBuffer, Buffer () {1, 2, 4, 4, 8, 8, 8, 8, 16, 16, 16, 16, 16, 16, 16, 16}) - /*----------------------------------------------------------------------------------------*/ - /** - * Set PCIe Bus Width - * - * Arg0 - Data Buffer - */ - Method (procPcieSetBusWidth, 1, NotSerialized) { - Store ("procPcieSetBusWidth Enter", Debug) - - Name (varClientBus, 0) - Name (varArgBusWidth, 0) - Store (0, varPortIndex) - Store (Buffer (10) {}, Local7) - - //ClientId: WORD - //Bits 2-0: Function number. - //Bits 7-3: Device number. - //Bits 15-8: Bus number. - Store (DerefOf (Index (Arg0, 0x3)), varClientBus) - Store (DerefOf (Index (Arg0, 0x4)), varArgBusWidth) - Store (Concatenate (" Client Bus : ", ToHexString (varClientBus), varStringBuffer), Debug) - Store (Concatenate (" Arg Bus Width : ", ToHexString (varArgBusWidth), varStringBuffer), Debug) - - Store (3, Index (Local7, 0x0)) // Return Buffer Length - Store (0, Index (Local7, 0x1)) // Return Buffer Length - Store (varArgBusWidth, Index (Local7, 0x2)) // Return BusWidth - - - //deternime correct lane bitmap (check for reversal) gate/ungate unused lanes - - // determine port index base on "Client ID" - while (LLessEqual (varPortIndex, varMaxPortIndexNumber)) { - if (LEqual (procChecPortAllocated (varPortIndex), DEF_PORT_ALLOCATED)) { - Store (procPciDwordRead (ShiftLeft (Add( varPortIndex, 2), 3), 0x18), Local1) - And (ShiftRight (Local1, 16), 0xff, varSubordinateBusLocal2) //Local2 Port Subordinate Bus number - And (ShiftRight (Local1, 8), 0xff, varSecondaryBusLocal1) //Local1 Port Secondary Bus number - if (LAnd (LGreaterEqual (varClientBus, Local1), LLessEqual(varClientBus, Local2))) { - break - } - } - Increment (varPortIndex) - } - if (LGreater (varPortIndex, varMaxPortIndexNumber)) { - Store ("procPcieSetBusWidth Exit -- over max port index", Debug) - return (Local7) - } - - Store (Concatenate (" Pcie Set BusWidth for port index : ", ToHexString (varPortIndex), varStringBuffer), Debug) - - // Normalize link width (Num Lanes) to correct value x1, x2.x4,x8,x16, - // make sure that number of lanes requested to be powered on less or equal mx port link width - if (LLessEqual (procPcieGetLinkWidth (varPortIndex, DEF_LINKWIDTH_MAX_PHY), varArgBusWidth)) { - // Active link equal max link width, nothing needs to be done - Store ("procPcieSetBusWidth Exit -- over max lanes supported", Debug) - return (Local7) - } - Store (DeRefOf (Index (varNormalizeLinkWidthBuffer, varArgBusWidth)), Local1) - - - // call procPcieLaneControl to power on all lanes (Arg0 - port index , Arg1 - 1, Arg2 = 0) - procPcieLaneControl (varPortIndex, DEF_PCIE_LANE_POWERON, 0) - - // call procPcieLaneControl power off unused lanes (Arg0 - port index, Arg1 - 1, Arg2 = Link width) - procPcieLaneControl (varPortIndex, DEF_PCIE_LANE_POWEROFFUNUSED, Local1) - -#ifdef PHY_SPEED_REPORT_SUPPORT - procReportPhySpeedCap () -#endif - Store (Local1, Index (Local7, 0x2)) // Return BusWidth - - Store ("procPcieSetBusWidth Exit", Debug) - return (Local7) - } - - - /*----------------------------------------------------------------------------------------*/ - /** - * PCIe port hotplug - * - * Arg0 - Data Buffer - * Retval - Return buffer - */ - Method (procPciePortHotplug, 1, Serialized) { - Store ("PciePortHotplug Enter", Debug) - Store (DerefOf (Index (Arg0, 4)), varHotplugStateLocal0) - Store (DerefOf (Index (Arg0, 2)), varPortIndexLocal1) - - Subtract (ShiftRight (varPortBdfLocal1, 3), 2, varPortIndexLocal1) - if (LEqual(varHotplugStateLocal0, 1)) { - // Enable port - Store (DEF_TRAINING_STATE_RELEASE_TRAINING, Local2) - } else { - // Disable port - Store (DEF_TRAINING_STATE_NOT_PRESENT, Local2) - } - - Store (procPciePortTraining (varPortIndexLocal1, Local2), varHotplugStateLocal0) - -#ifdef PHY_SPEED_REPORT_SUPPORT - procReportPhySpeedCap () -#endif - - Store (Buffer (10) {}, Local7) - CreateWordField (Local7, 0x0, varReturnBufferLength) - CreateByteField (Local7, 0x2, varReturnStatus) - CreateByteField (Local7, 0x3, varReturnDeviceStatus) - Store (0x4, varReturnBufferLength) - Store (0x0, varReturnStatus) - Store (varHotplugStateLocal0, varReturnDeviceStatus) - Store ("PciePortHotplug Exit", Debug) - return (Local7) - } - - Name (varSpeedRequest, Buffer (10) {0,0,0,0,0,0,0,0,0,0}) - - /*----------------------------------------------------------------------------------------*/ - /** - * Train PCIe port - * - * - * Arg0 - Port Index - * Arg1 - Initial state - */ - Method (procPciePortTraining, 2, Serialized) { - Store ("PciePortTraining Enter", Debug) - Store (DEF_HOTPLUG_STATUS_DEVICE_NOT_PRESENT, varResultLocal4) - Store (procPcieGetPortInfo (Arg0), Local7) - // Check if port supports basic hotplug - Store (DerefOf (Index (Local7, DEF_OFFSET_LINK_HOTPLUG)), varTempLocal1) - if (LNotEqual (varTempLocal1, DEF_BASIC_HOTPLUG)) { - Store (" No action.[Hotplug type]", Debug) - Store ("procPciePortTraining Exit", Debug) - return (varResultLocal4) - } - Store (Arg1, varStateLocal2) - while (LNotEqual (varStateLocal2, DEF_TRAINING_STATE_EXIT)) { - if (LEqual (varStateLocal2, DEF_TRAINING_STATE_RELEASE_TRAINING)) { - Store (" State: Release training", Debug) - // Remove link speed override - Store (0, Index (varOverrideLinkSpeed, Arg0)) - // Enable link width upconfigure - procPciePortIndirectRegisterRMW (Arg0, 0xA2, Not (0x2000), 0x0000) - // Request Max link speed for hotplug by going to AC state - Store (0, varPsppAcDcOverride) - procApplyPsppState () - // Power on/enable port lanes - procPcieLaneControl (Arg0, DEF_PCIE_LANE_POWERON, 0) - // Release training - procPcieTrainingControl (Arg0, 0) - // Move to next state to check presence detection - Store (DEF_TRAINING_STATE_DETECT_PRESENCE, varStateLocal2) - // Initialize retry count - Store(0, varCountLocal3) - } - if (LEqual (varStateLocal2, DEF_TRAINING_STATE_DETECT_PRESENCE)) { - Store (" State: Detect presence", Debug) - And (procPciePortIndirectRegisterRead (Arg0, 0xa5), 0x3f, varTempLocal1) - if (LGreater (varTempLocal1, 0x4)) { - // device connection detected move to next state - Store (DEF_TRAINING_STATE_PRESENCE_DETECTED, varStateLocal2) - // reset retry counter - Store(0, varCountLocal3) - continue - } - if (LLess (varCountLocal3, 80)) { - Sleep (1) - Increment (varCountLocal3) - } else { - // detection time expired move to device not present state - Store (DEF_TRAINING_STATE_NOT_PRESENT, varStateLocal2) - } - } - if (LEqual (varStateLocal2, DEF_TRAINING_STATE_PRESENCE_DETECTED)) { - Store (" State: Device detected", Debug) - Store (procPciePortIndirectRegisterRead (Arg0, 0xa5), varTempLocal1) - And (varTempLocal1, 0x3f, varTempLocal1) - if (LEqual (varTempLocal1, 0x10)) { - Store (DEF_TRAINING_DEVICE_PRESENT, varStateLocal2) - continue - } - if (LLess (varCountLocal3, 80)) { - Sleep (1) - Increment (varCountLocal3) - continue - } - Store (DEF_TRAINING_STATE_NOT_PRESENT, varStateLocal2) - - if (LEqual (DeRefOf (Index (varOverrideLinkSpeed, Arg0)), DEF_LINK_SPEED_GEN1)) { - // GEN2 workaround already applied but device not trained successfully move device not present state - continue - } - - if (LEqual (procPcieCheckForGen2Workaround (Arg0), TRUE)) { - Store (" Request Gen2 workaround", Debug) - procPciePortIndirectRegisterRMW (Arg0, 0xA2, Not (0x2000), 0x2000) - Store (DEF_LINK_SPEED_GEN1, Index (varOverrideLinkSpeed, Arg0)) - procPcieSetLinkSpeed (Arg0, DEF_LINK_SPEED_GEN1) - Store (DEF_TRAINING_STATE_REQUEST_RESET, varStateLocal2) - } - } - if (LEqual (varStateLocal2, DEF_TRAINING_STATE_NOT_PRESENT)) { - Store (" State: Device not present", Debug) - procPcieTrainingControl (Arg0, 1) - procPcieLaneControl (Arg0, DEF_PCIE_LANE_POWEROFF, 0) - // Exclude device from PSPP managment since it is not present - Store (DEF_LINK_SPEED_GEN1, Index (varOverrideLinkSpeed, Arg0)) - Store (DEF_TRAINING_STATE_COMPLETE, varStateLocal2) - } - if (LEqual (varStateLocal2, DEF_TRAINING_STATE_REQUEST_RESET)) { - Store (" State: Request Reset", Debug) - if (CondRefOf (\_SB.ALIC, Local6)) { - Store (" Call ALIC method", Debug) - //varTempLocal1 contain port BDF - Store(ShiftLeft (Add (Arg0, 2), 3), varTempLocal1) - \_SB.ALIC (varTempLocal1, 0) - Sleep (2) - \_SB.ALIC (varTempLocal1, 1) - Store (0, varCountLocal3) - Store (DEF_TRAINING_STATE_DETECT_PRESENCE, varStateLocal2) - continue - } - Store (DEF_TRAINING_STATE_NOT_PRESENT, varStateLocal2) - } - if (LEqual (varStateLocal2, DEF_TRAINING_DEVICE_PRESENT)) { - Store (" State: Device present", Debug) - Store (DEF_HOTPLUG_STATUS_DEVICE_PRESENT, varResultLocal4) - Store (DEF_TRAINING_STATE_COMPLETE, varStateLocal2) -#ifdef PCIE_DISABLE_UNUSED_LANES_ON_ACTIVE_LINK - procPcieLaneControl (Arg0, DEF_PCIE_LANE_POWEROFFUNUSED, 0) -#endif - } - if (LEqual (varStateLocal2, DEF_TRAINING_STATE_COMPLETE)) { - - Store (1, varPsppAcDcOverride) - procApplyPsppState () - - Store (DEF_TRAINING_STATE_EXIT, varStateLocal2) - } - } - Store ("PciePortTraining Exit", Debug) - return (varResultLocal4) - } - - - /*----------------------------------------------------------------------------------------*/ - /** - * Lane control - * - * Arg0 - Port Index - * Arg1 - 0 - Power off all lanes / 1 - Power on all Lanes / 2 Power off unused lanes - * Arg2 - link width - */ - - Method (procPcieLaneControl, 3, Serialized) { - Store ("PcieLaneControl Enter", Debug) - Store (Concatenate (" Arg0 : ", ToHexString (Arg0), varStringBuffer), Debug) - Store (Concatenate (" Arg1 : ", ToHexString (Arg1), varStringBuffer), Debug) - Store (procPcieGetPortInfo (Arg0), Local7) -#ifdef PCIE_PHY_LANE_POWER_GATE_SUPPORT - Store (DerefOf (Index (Local7, DEF_OFFSET_START_PHY_LANE)), varStartPhyLane) - Store (DerefOf (Index (Local7, DEF_OFFSET_END_PHY_LANE)), varEndPhyLane) -#endif - Store (DerefOf (Index (Local7, DEF_OFFSET_START_CORE_LANE)), varStartCoreLane) - Store (DerefOf (Index (Local7, DEF_OFFSET_END_CORE_LANE)), varEndCoreLane) - - if (LEqual (Arg1, DEF_PCIE_LANE_POWEROFF)) { - procPcieLaneEnableControl (Arg0, varStartCoreLane, varEndCoreLane, 1) -#ifdef PCIE_PHY_LANE_POWER_GATE_SUPPORT - procPcieLanePowerControl (varStartPhyLane, varEndPhyLane, 1) -#endif - } - if (LEqual (Arg1, DEF_PCIE_LANE_POWERON)) { -#ifdef PCIE_PHY_LANE_POWER_GATE_SUPPORT - procPcieLanePowerControl (varStartPhyLane, varEndPhyLane, 0) -#endif - procPcieLaneEnableControl (Arg0, varStartCoreLane, varEndCoreLane, 0) - } - if (LNotEqual (Arg1, DEF_PCIE_LANE_POWEROFFUNUSED)) { - return (0) - } - - // Local2 should have link width (active lanes) - // Local3 should have first non active lanes - // Local4 should have last non active lanes - - if (LEqual(Arg2, 0)) { - Store (procPcieGetLinkWidth (Arg0, DEF_LINKWIDTH_ACTIVE), varActiveLinkWidthLocal2) - } else { - Store ( Arg2 , varActiveLinkWidthLocal2) - } - // Let say Link width is x1 than local2 = 1, Local3 = 1 Local4 = 15 for non reversed case - // while for reversed case should be Local2 = 1 Local3 = 0 and Local4 = 14 - - if (LLessEqual (procPcieGetLinkWidth (Arg0, DEF_LINKWIDTH_MAX_PHY), varActiveLinkWidthLocal2)) { - // Active link equal max link width, nothing needs to be done - return (0) - } - - Store (procPcieIsPortReversed (Arg0), varIsReversedLocal1) - //There is unused lanes after device plugged - if (LEqual(varIsReversedLocal1, FALSE)) { - Store (" Port Not Reversed", Debug) - // Link not reversed - Add (varStartCoreLane, varActiveLinkWidthLocal2, Local3) - Store (varEndCoreLane, Local4) - } else { - // Link reversed - Store (" Port Reversed", Debug) - Subtract (varEndCoreLane, varActiveLinkWidthLocal2, Local4) - Store (varStartCoreLane, Local3) - } - procPcieLaneEnableControl (Arg0, Local3, Local4, 1) -#ifdef PCIE_PHY_LANE_POWER_GATE_SUPPORT - if (LGreater (varStartPhyLane, varEndPhyLane)) { - Store (varEndPhyLane, Local3) - Store (varStartPhyLane, Local4) - } else { - Store (varEndPhyLane, Local4) - Store (varStartPhyLane, Local3) - } - if (LEqual(varIsReversedLocal1, FALSE)) { - // Not reversed - Add (Local3, varActiveLinkWidthLocal2, Local3) - } else { - // Link reversed - Subtract (Local4, varActiveLinkWidthLocal2, Local4) - } - procPcieLanePowerControl (Local3, Local4, 1) -#endif - return (0) - } - - /*----------------------------------------------------------------------------------------*/ - /** - * Check if GEN2 workaround applicable - * - * Arg0 - Port Index - * Retval - TRUE / FALSE - */ - - Method (procPcieCheckForGen2Workaround, 1, NotSerialized) { - Store (Buffer (16) {}, Local1) - Store (0x0, Local0) - while (LLessEqual (Local0, 0x3)) { - Store (procPciePortIndirectRegisterRead (Arg0, Add (Local0, 0xA5)), Local2) - Store (Local2, Index (Local1, Multiply (Local0, 4))) - Store (ShiftRight (Local2, 8), Index (Local1, Add (Multiply (Local0, 4), 1))) - Store (ShiftRight (Local2, 16), Index (Local1, Add (Multiply (Local0, 4), 2))) - Store (ShiftRight (Local2, 24), Index (Local1, Add (Multiply (Local0, 4), 3))) - Increment (Local0) - } - Store (0, Local0) - while (LLess (Local0, 15)) { - if (LAnd (LEqual (DeRefOf (Index (Local1, Local0)), 0x2a), LEqual (DeRefOf (Index (Local1, Add (Local0, 1))), 0x9))) { - return (TRUE) - } - Increment (Local0) - } - return (FALSE) - } - - /*----------------------------------------------------------------------------------------*/ - /** - * Is port reversed - * - * Arg0 - Port Index - * Retval - 0 - Not reversed / !=0 - Reversed - */ - Method (procPcieIsPortReversed , 1, Serialized) { - Store (procPcieGetPortInfo (Arg0), Local7) - - Store (DerefOf (Index (Local7, DEF_OFFSET_START_PHY_LANE)), varStartPhyLane) - Store (DerefOf (Index (Local7, DEF_OFFSET_END_PHY_LANE)), varEndPhyLane) - Store (0, Local0) - if (LGreater (varStartPhyLane, varEndPhyLane)) { - Store (1, Local0) - } - And (procPciePortIndirectRegisterRead (Arg0, 0x50), 0x1, Local1) - return (And (Xor (Local0, Local1), 0x1)) - } - - /*----------------------------------------------------------------------------------------*/ - /** - * Training Control - * - * Arg0 - Port Index - * Arg1 - Hold Training (1) / Release Training (0) - */ - Method (procPcieTrainingControl , 2, NotSerialized) { - Store ("PcieTrainingControl Enter", Debug) - Store (procPcieGetPortInfo (Arg0), Local7) - Store (DerefOf (Index (Local7, DEF_OFFSET_PORT_ID)), varPortId) - Store ( - Or (ShiftLeft (DerefOf (Index (Local7, Add (DEF_OFFSET_WRAPPER_ID, 1))), 8), DerefOf (Index (Local7, DEF_OFFSET_WRAPPER_ID))), - varWrapperId - ) - procIndirectRegisterRMW (0x0, 0xE0, Or (ShiftLeft (varWrapperId, 16), Add (0x800, Multiply (0x100, varPortId))), Not (0x1), Arg1); - Store ("PcieTrainingControl Exit", Debug) - } - - -Name (varLinkWidthBuffer, Buffer () {0, 1, 2, 4, 8, 12, 16}) -/*----------------------------------------------------------------------------------------*/ - /** - * Get actual negotiated/PHY or core link width - * - * Arg0 - Port Index - * Arg1 - 0/1 Negotiated/Phy - * Retval - Link Width - */ - Method (procPcieGetLinkWidth, 2, NotSerialized) { - Store ("PcieGetLinkWidth Enter", Debug) - Store (Concatenate (" Arg0 : ", ToHexString (Arg0), varStringBuffer), Debug) - Store (Concatenate (" Arg1 : ", ToHexString (Arg1), varStringBuffer), Debug) - - if (LEqual (Arg1, DEF_LINKWIDTH_ACTIVE)){ - //Get negotiated length - And (ShiftRight (procPciePortIndirectRegisterRead (Arg0, 0xA2), 4), 0x7, Local0) - Store (DeRefOf (Index (varLinkWidthBuffer, Local0)), Local1) - Store (Concatenate (" Active Link Width :", ToHexString (Local1), varStringBuffer), Debug) - } else { - //Get phy length - Store (procPcieGetPortInfo (Arg0), Local7) - Store (DerefOf (Index (Local7, DEF_OFFSET_START_PHY_LANE)), varStartPhyLane) - Store (DerefOf (Index (Local7, DEF_OFFSET_END_PHY_LANE)), varEndPhyLane) - if (LGreater (varStartPhyLane, varEndPhyLane)) { - Subtract (varStartPhyLane, varEndPhyLane, Local1) - } else { - Subtract (varEndPhyLane, varStartPhyLane, Local1) - } - Increment (Local1) - Store (Concatenate (" PHY Link Width :", ToHexString (Local1), varStringBuffer), Debug) - } - Store ("PcieGetLinkWidth Exit", Debug) - return (Local1) - } - - /*----------------------------------------------------------------------------------------*/ - /** - * PCIe lane mux lane enable control (hotplug support) - * - * Arg0 - Port Index - * Arg1 - Start Lane - * Arg2 - End Lane - * Arg3 - Enable(0) / Disable(1) - */ - Method (procPcieLaneEnableControl, 4, Serialized) { - Store ("PcieLaneEnableControl Enter", Debug) - Store (Concatenate (" Arg0 : ", ToHexString (Arg0), varStringBuffer), Debug) - Store (Concatenate (" Arg1 : ", ToHexString (Arg1), varStringBuffer), Debug) - Store (Concatenate (" Arg2 : ", ToHexString (Arg2), varStringBuffer), Debug) - Store (Concatenate (" Arg3 : ", ToHexString (Arg3), varStringBuffer), Debug) - Store (procPcieGetPortInfo (Arg0), Local7) - Store (Arg1, varStartCoreLane) - Store (Arg2, varEndCoreLane) - Store ( - Or (ShiftLeft (DerefOf (Index (Local7, Add (DEF_OFFSET_WRAPPER_ID, 1))), 8), DerefOf (Index (Local7, DEF_OFFSET_WRAPPER_ID))), - varWrapperId - ) - if (LGreater (varStartCoreLane, varEndCoreLane)) { - Subtract (varStartCoreLane, varEndCoreLane, Local1) - Store (varEndCoreLane, Local2) - } else { - Subtract (varEndCoreLane, varStartCoreLane, Local1) - Store (varStartCoreLane, Local2) - } - ShiftLeft (Subtract (ShiftLeft (1, Add (Local1, 1)), 1), Local2, varLaneBitmapOrMaskLocal3) - Store (Not (varLaneBitmapOrMaskLocal3), varLaneBitmapAndMaskLocal4) - Store (Concatenate (" Lane Bitmap : ", ToHexString (varLaneBitmapOrMaskLocal3), varStringBuffer), Debug) - if (Lequal (Arg3, 1)) { - Store (0, varLaneBitmapOrMaskLocal3) - } - procIndirectRegisterRMW (0x0, 0xE0, Or (ShiftLeft (varWrapperId, 16), 0x8023), varLaneBitmapAndMaskLocal4, varLaneBitmapOrMaskLocal3); - Stall (10) - Store ("PcieLaneEnableControl Exit", Debug) - } - - diff --git a/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieAlibV1/PcieAlibPspp.esl b/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieAlibV1/PcieAlibPspp.esl deleted file mode 100644 index ffc50f8054..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieAlibV1/PcieAlibPspp.esl +++ /dev/null @@ -1,772 +0,0 @@ -/** -* @file -* -* ALIB PSPP ASL library -* -* -* -* @xrefitem bom "File Content Label" "Release Content" -* @e project: AGESA -* @e sub-project: GNB -* @e \$Revision: 49911 $ @e \$Date: 2011-03-30 17:43:29 +0800 (Wed, 30 Mar 2011) $ -* -*/ -/* -***************************************************************************** -* -* Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* *************************************************************************** -* -*/ - - /*----------------------------------------------------------------------------------------*/ - /** - * PCIe Performance Policy - * - * varPsppPolicy - 0 Disabled - * 1 Performance - * 2 Balance Hight - * 3 Balance Low - * 4 Power Saving - */ - Name ( - AD02, - 0x0 - ) - - Alias ( - AD02, - varPsppPolicy - ) - - /*----------------------------------------------------------------------------------------*/ - /** - * GEN2 VID - * - */ - - Name ( - AD03, - 0x0 - ) - - Alias ( - AD03, - varGen2Vid - ) - - /*----------------------------------------------------------------------------------------*/ - /** - * GEN1 VID - * - */ - Name ( - AD04, - 0x0 - ) - - Alias ( - AD04, - varGen1Vid - ) - - /*----------------------------------------------------------------------------------------*/ - /** - * Boot VID - * - */ - - Name ( - AD05, - 0x0 - ) - - Alias ( - AD05, - varBootVid - ) - - /*----------------------------------------------------------------------------------------*/ - /** - * Max Port link speed - * - */ - Name (AD06, Package () {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}) - - Alias (AD06, varMaxLinkSpeed) - - - /*----------------------------------------------------------------------------------------*/ - /** - * Max link speed that was changed during runtime (hotplug for instance) - * - */ - - Name (AD08, Package () {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}) - - Alias (AD08, varOverrideLinkSpeed) - - /*----------------------------------------------------------------------------------------*/ - /** - * Policy service status - * - * varPsppPolicyService - 0 (Stopped) - * 1 (Started) - */ - - Name (varPsppPolicyService, 0x0 ) - - /*----------------------------------------------------------------------------------------*/ - /** - * AC DC state - * - * varPsppAcDcState - 0 (AC) - * 1 (DC) - */ - - Name (varPsppAcDcState, 0x0) - Name (varPsppAcDcOverride, 0x1) - - /*----------------------------------------------------------------------------------------*/ - /** - * Client ID array - * - */ - - Name (varPsppClientIdArray, - Package () {0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000} - ) - - Name (varDefaultPsppClientIdArray, - Package () {0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000} - ) - /*----------------------------------------------------------------------------------------*/ - /** - * LInk speed requested by device driver - * - */ - - Name (varRequestedLinkSpeed, Package () {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}) - - /*----------------------------------------------------------------------------------------*/ - /** - * Current link speed - * - */ - Name (AD09, Package () {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }) - Alias (AD09, varCurrentLinkSpeed) - /*----------------------------------------------------------------------------------------*/ - /** - * Template link speed - * - */ - Name ( - varGen1LinkSpeedTemplate, - Package () { - DEF_LINK_SPEED_GEN1, - DEF_LINK_SPEED_GEN1, - DEF_LINK_SPEED_GEN1, - DEF_LINK_SPEED_GEN1, - DEF_LINK_SPEED_GEN1, - DEF_LINK_SPEED_GEN1, - DEF_LINK_SPEED_GEN1, - DEF_LINK_SPEED_GEN1 - }) - - /*----------------------------------------------------------------------------------------*/ - /** - * Template link speed - * - */ - Name (varLowVoltageRequest, Package () {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }) - - /*----------------------------------------------------------------------------------------*/ - /** - * Global varuable - * - */ - Name (varPortIndex, 0) - - /*----------------------------------------------------------------------------------------*/ - /** - * Sclk VID that was changed during runtime - * - */ - - Name (AD10, Package () {0x00, 0x00, 0x00, 0x00}) - - Alias (AD10, varSclkVid) - - /*----------------------------------------------------------------------------------------*/ - /** - * Report AC/DC state - * - * Arg0 - Data Buffer - */ - Method (procPsppReportAcDsState, 1, Serialized) { - Store ("PsppReportAcDsState Enter", Debug) - - Store (DeRefOf (Index (Arg0, 0x2)), varArgAcDcStateLocal1) - Store (Concatenate (" AC/DC state: ", ToHexString (varArgAcDcStateLocal1), varStringBuffer), Debug) - - Store (procPsppGetAcDcState(), varCurrentAcDcStateLocal0) - Store (varArgAcDcStateLocal1, varPsppAcDcState) - - Or (ShiftLeft (1, DEF_SCARTCH_PSPP_ACDC_OFFSET), ShiftLeft (1, DEF_SCARTCH_PSPP_ACDC_OVR_OFFSET), Local2) - Or (ShiftLeft (varPsppAcDcState, DEF_SCARTCH_PSPP_ACDC_OFFSET), ShiftLeft (varPsppAcDcOverride, DEF_SCARTCH_PSPP_ACDC_OVR_OFFSET), Local3) - procIndirectRegisterRMW (0x0, 0x60, 0xF4, Not (Local2), And (Local2, Local3)) - - - if (LEqual (varArgAcDcStateLocal1, varCurrentAcDcStateLocal0)) { - Store (" No action. [AC/DC state not changed]", Debug) - Store ("PsppReportAcDsState Exit", Debug) - return (0) - } - - // Disable both APM (boost) and PDM flow on DC event enable it on AC. - procApmPdmActivate(varPsppAcDcState) - - // Set DPM state for Power Saving, due to this policy will not attend ApplyPsppState service. - if (LEqual (varPsppPolicy, DEF_PSPP_POLICY_POWERSAVING)) { - procNbLclkDpmActivate(DEF_LINK_SPEED_GEN1) -#ifdef ALTVDDNB_SUPPORT - procNbAltVddNb (DEF_LINK_SPEED_GEN1) -#endif - } - if (LOr (LLessEqual (varPsppPolicy, DEF_PSPP_POLICY_PERFORMANCE), LGreaterEqual (varPsppPolicy, DEF_PSPP_POLICY_POWERSAVING))) { - Store (" No action. [Policy type]", Debug) - Store ("PsppReportAcDsState Exit", Debug) - return (0) - } - if (LEqual (varPsppPolicyService, DEF_PSPP_POLICY_STOP)) { - Store (" No action. [Policy not started]", Debug) - Store ("PsppReportAcDsState Exit", Debug) - return (0) - } - procApplyPsppState () - Store ("PsppReportAcDsState Exit", Debug) - return (0) - } - - /*----------------------------------------------------------------------------------------*/ - /** - * PCIe Performance Request - * - * Arg0 - Data Buffer - */ - Method (procPsppPerformanceRequest, 1, NotSerialized) { - Store (procPsppProcessPerformanceRequest (Arg0), Local7) - Store (DeRefOf (Index (Local7, 2)), varReturnStatusLocal0) - if (LNotEqual (varReturnStatusLocal0, 2)) { - return (Local7) - } - procApplyPsppState () - return (Local7) - } - /*----------------------------------------------------------------------------------------*/ - /** - * PCIe Performance Request - * - * Arg0 - Data Buffer - */ - Method (procPsppProcessPerformanceRequest, 1, NotSerialized) { - Store ("PsppProcessPerformanceRequest Enter", Debug) - Name (varClientBus, 0) - Store (0, varPortIndex) - Store (Buffer (10) {}, Local7) - CreateWordField (Local7, 0x0, varReturnBufferLength) - Store (3, varReturnBufferLength) - CreateByteField (Local7, 0x2, varReturnStatus) - Store (1, varReturnStatus) - - if (LOr (LLessEqual (varPsppPolicy, DEF_PSPP_POLICY_PERFORMANCE), LGreaterEqual (varPsppPolicy, DEF_PSPP_POLICY_POWERSAVING))) { - Store (" No action. [Policy type]", Debug) - Store ("PsppPerformanceRequest Exit", Debug) - return (Local7) - } - if (LEqual (varPsppPolicyService, DEF_PSPP_POLICY_STOP)) { - Store (" No action. [Policy not started]", Debug) - Store ("PsppPerformanceRequest Exit", Debug) - return (Local7) - } - CreateWordField (Arg0, 0x2, varClientId) - CreateWordField (Arg0, 0x4, varValidFlag) - CreateWordField (Arg0, 0x6, varFlag) - CreateByteField (Arg0, 0x8, varRequestType) - CreateByteField (Arg0, 0x9, varRequestData) - - Store (Concatenate (" Client ID : ", ToHexString (varClientId), varStringBuffer), Debug) - Store (Concatenate (" Valid Flags : ", ToHexString (varValidFlag), varStringBuffer), Debug) - Store (Concatenate (" Flags : ", ToHexString (varFlag), varStringBuffer), Debug) - Store (Concatenate (" Request Type: ", ToHexString (varRequestType), varStringBuffer), Debug) - Store (Concatenate (" Request Data: ", ToHexString (varRequestData), varStringBuffer), Debug) - - - And (ShiftRight (varClientId, 8), 0xff, varClientBus) - while (LLessEqual (varPortIndex, varMaxPortIndexNumber)) { - if (LEqual (procChecPortAllocated (varPortIndex), DEF_PORT_ALLOCATED)) { - Store (procPciDwordRead (ShiftLeft (Add( varPortIndex, 2), 3), 0x18), Local1) - And (ShiftRight (Local1, 16), 0xff, varSubordinateBusLocal2) //Local2 Port Subordinate Bus number - And (ShiftRight (Local1, 8), 0xff, varSecondaryBusLocal1) //Local1 Port Secondary Bus number - if (LAnd (LGreaterEqual (varClientBus, Local1), LLessEqual(varClientBus, Local2))) { - break - } - } - Increment (varPortIndex) - } - if (LGreater (varPortIndex, varMaxPortIndexNumber)) { - Store ("PsppPerformanceRequest Exit", Debug) - return (Local7) - } - - Store (Concatenate (" Performance request for port index : ", ToHexString (varPortIndex), Local6), Debug) - - if (LEqual (DeRefOf (Index (varPsppClientIdArray, varPortIndex)), 0x0000)) { - Store (varClientId, Index (varPsppClientIdArray, varPortIndex)) - } ElseIf (LNotEqual (DeRefOf (Index (varPsppClientIdArray, varPortIndex)), varClientId)) { - // We already have registered client - Store (" No action. [Unsupported request]", Debug) - Store ("PsppPerformanceRequest Exit", Debug) - return (Local7) - } - Store (0, Index (varLowVoltageRequest, varPortIndex)) - if (LEqual (varRequestData, 0)) { - Store (0x0000, Index (varPsppClientIdArray, varPortIndex)) - } - if (LEqual (varRequestData, 1)) { - Store (1, Index (varLowVoltageRequest, varPortIndex)) - } - if (LEqual (varRequestData, 2)) { - Store (DEF_LINK_SPEED_GEN1, Index (varRequestedLinkSpeed, varPortIndex)) - } - if (LEqual (varRequestData, 3)) { - Store (DEF_LINK_SPEED_GEN2, Index (varRequestedLinkSpeed, varPortIndex)) - } - if (LEqual (And (varValidFlag, varFlag), 0x1)) { - Store (DerefOf (Index (varMaxLinkSpeed, varPortIndex)), Index (varRequestedLinkSpeed, varPortIndex)) - } - Store (2, varReturnStatus) - Store ("PsppProcessPerformanceRequest Exit", Debug) - return (Local7) - } - - /*----------------------------------------------------------------------------------------*/ - /** - * PSPP Start/Stop Management Request - * - * Arg0 - Data Buffer - */ - - Method (procChecPortAllocated, 1, Serialized) { - if (LEqual (DeRefOf (Index (varMaxLinkSpeed, Arg0)), 0)) { - return (DEF_PORT_NOT_ALLOCATED) - } - return (DEF_PORT_ALLOCATED) - } - - /*----------------------------------------------------------------------------------------*/ - /** - * PSPP Start/Stop Management Request - * - * Arg0 - Data Buffer - */ - Method (procPsppControl, 1, Serialized) { - Store ("PsppControl Enter", Debug) - Store (Buffer (256) {}, Local7) - Store (3, Index (Local7, 0x0)) // Return Buffer Length - Store (0, Index (Local7, 0x1)) // Return Buffer Length - Store (0, Index (Local7, 0x2)) // Return Status - - Store (DerefOf (Index (Arg0, 0x2)), varPsppPolicyService) - - Store (procIndirectRegisterRead (0x0, 0x60, 0xF4), varPsppScratchLocal0) - - if (LEqual (varPsppPolicyService, DEF_PSPP_POLICY_START)) { - if (LEqual (And (varPsppScratchLocal0, 1), DEF_PSPP_POLICY_START)) { - // Policy already started - Store (" No action. [Policy already started]", Debug) - Store ("PsppControl Exit", Debug) - return (Local7) - } - Or (varPsppScratchLocal0, DEF_PSPP_POLICY_START, varPsppScratchLocal0) - } - if (LEqual (varPsppPolicyService, DEF_PSPP_POLICY_STOP)) { - if (LEqual (And (varPsppScratchLocal0, 1), DEF_PSPP_POLICY_STOP)) { - // Policy already stopped - Store (" No action. [Policy already stopped]", Debug) - Store ("PsppControl Exit", Debug) - return (Local7) - } - And (varPsppScratchLocal0, Not (DEF_PSPP_POLICY_START), varPsppScratchLocal0) - } - Or (varPsppScratchLocal0, Shiftleft (varPsppPolicy, DEF_SCARTCH_PSPP_POLICY_OFFSET), varPsppScratchLocal0) - procIndirectRegisterWrite (0x0, 0x60, 0xF4, varPsppScratchLocal0) - - procCopyPackage (RefOf (varDefaultPsppClientIdArray), RefOf (varPsppClientIdArray)) - - // Reevaluate APM/PDM state here on S3 resume while staying on DC. - procApmPdmActivate(varPsppAcDcState) - - // Set DPM state for PSPP Power Saving, due to this policy will not attend ApplyPsppState service. - if (LEqual (varPsppPolicy, DEF_PSPP_POLICY_POWERSAVING)) { - procNbLclkDpmActivate(DEF_LINK_SPEED_GEN1) -#ifdef ALTVDDNB_SUPPORT - procNbAltVddNb (DEF_LINK_SPEED_GEN1) -#endif - } - //Reevaluate PCIe speed for all devices base on PSPP state switch to boot up voltage - if (LAnd (LGreater (varPsppPolicy, DEF_PSPP_POLICY_PERFORMANCE), LLess (varPsppPolicy, DEF_PSPP_POLICY_POWERSAVING))) { - // Load default speed capability state - if (LEqual (varPsppPolicy, DEF_PSPP_POLICY_BALANCEHIGH)) { - procCopyPackage (RefOf (varMaxLinkSpeed), RefOf (varCurrentLinkSpeed)) - Store (0, varPortIndex) - while (LLessEqual (varPortIndex, varMaxPortIndexNumber)) { - if (LNotEqual (DeRefOf (Index (varOverrideLinkSpeed, varPortIndex)), 0)) { - Store (DeRefOf (Index (varOverrideLinkSpeed, varPortIndex)), Index (varCurrentLinkSpeed, varPortIndex)) - } - Increment (varPortIndex) - } - } else { - procCopyPackage (RefOf (varGen1LinkSpeedTemplate), RefOf (varCurrentLinkSpeed)) - } - procApplyPsppState () - } - Store ("PsppControl Exit", Debug) - return (Local7) - } - - Name (varNewLinkSpeed, Package () {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}) - - /*----------------------------------------------------------------------------------------*/ - /** - * Evaluate PCIe speed on all links according to PSPP state and client requests - * - * - * - */ - Method (procApplyPsppState, 0, Serialized) { - Store ("ApplyPsppState Enter", Debug) - Store (0, varPortIndex) - - procCopyPackage (RefOf (varGen1LinkSpeedTemplate), RefOf (varNewLinkSpeed)) - while (LLessEqual (varPortIndex, varMaxPortIndexNumber)) { - if (LEqual (procChecPortAllocated(varPortIndex), DEF_PORT_ALLOCATED)) { - Store (procGetPortRequestedCapability (varPortIndex), Index (varNewLinkSpeed, varPortIndex)) - } - Increment (varPortIndex) - } - if (LNotEqual(Match (varLowVoltageRequest, MEQ, 0x01, MTR, 0, 0), ONES)) { - procCopyPackage (RefOf (varGen1LinkSpeedTemplate), RefOf (varNewLinkSpeed)) - } - if (LNotEqual(Match (varNewLinkSpeed, MEQ, DEF_LINK_SPEED_GEN2, MTR, 0, 0), ONES)) { - // Set GEN2 voltage - Store ("Set GEN2 VID", Debug) -#ifdef ALTVDDNB_SUPPORT - procNbAltVddNb (DEF_LINK_SPEED_GEN2) -#endif - procPcieSetVoltage (varGen2Vid, 1) -// procPcieAdjustPll (DEF_LINK_SPEED_GEN2) - procNbLclkDpmActivate(DEF_LINK_SPEED_GEN2) - } - Store (0, varPortIndex) - while (LLessEqual (varPortIndex, varMaxPortIndexNumber)) { - if (LEqual (procChecPortAllocated(varPortIndex), DEF_PORT_NOT_ALLOCATED)) { - Increment (varPortIndex) - continue - } - Store (DerefOf (Index (varCurrentLinkSpeed, varPortIndex)), varCurrentLinkSpeedLocal0) - Store (DerefOf (Index (varNewLinkSpeed, varPortIndex)), varNewLinkSpeedLocal2) - if (LEqual (varCurrentLinkSpeedLocal0, varNewLinkSpeedLocal2)) { - Increment (varPortIndex) - continue - } - Store (varNewLinkSpeedLocal2, Index (varCurrentLinkSpeed, varPortIndex)) - procSetPortCapabilityAndSpeed (varPortIndex, varNewLinkSpeedLocal2) - Increment (varPortIndex) - } - if (LEqual(Match (varNewLinkSpeed, MEQ, DEF_LINK_SPEED_GEN2, MTR, 0, 0), ONES)) { - // Set GEN1 voltage - Store ("Set GEN1 VID", Debug) - procNbLclkDpmActivate(DEF_LINK_SPEED_GEN1) -// procPcieAdjustPll (DEF_LINK_SPEED_GEN1) - procPcieSetVoltage (varGen1Vid, 0) -#ifdef ALTVDDNB_SUPPORT - procNbAltVddNb (DEF_LINK_SPEED_GEN1) -#endif - } -#ifdef PHY_SPEED_REPORT_SUPPORT - procReportPhySpeedCap () -#endif - Store ("ApplyPsppState Exit", Debug) - } - /*----------------------------------------------------------------------------------------*/ - /** - * Read PCI config register - * - * Arg0 - Port Index - * - */ - Method (procGetPortRequestedCapability, 1) { - Store (DEF_LINK_SPEED_GEN2, Local0) - if (LEqual (DerefOf (Index (varPsppClientIdArray, Arg0)), 0x0000)) { - if (LOr (LEqual (procPsppGetAcDcState(), DEF_PSPP_STATE_DC), LEqual (varPsppPolicy, DEF_PSPP_POLICY_BALANCELOW))) { - // Default policy cap to GEN1 - Store (DEF_LINK_SPEED_GEN1, Local0) - } - if (LNotEqual (DerefOf (Index (varOverrideLinkSpeed, Arg0)), 0)) { - Store (DerefOf (Index (varOverrideLinkSpeed, Arg0)), Local0) - } - } else { - Store (DerefOf (Index (varRequestedLinkSpeed, Arg0)), Local0) - } - return (Local0) - } - - /*----------------------------------------------------------------------------------------*/ - /** - * Set capability and speed - * - * Arg0 - Port Index - * Arg1 - Link speed - */ - Method (procSetPortCapabilityAndSpeed, 2, NotSerialized) { - Store ("SetPortCapabilityAndSpeed Enter", Debug) - Store (Concatenate (" Port Index : ", ToHexString (Arg0), varStringBuffer), Debug) - Store (Concatenate (" Speed : ", ToHexString (Arg1), varStringBuffer), Debug) - - //UnHide UMI port - if (LEqual (Arg0, 6)) { - procIndirectRegisterRMW (0x0, 0x60, 0x80, Not (0x40), 0x40); - } - - procPcieSetLinkSpeed (Arg0, Arg1) - - // Programming for LcInitSpdChgWithCsrEn - if (LNotEqual (DeRefOf (Index (varPsppClientIdArray, Arg0)), 0x0000)) { - // Registered port, LcInitSpdChgWithCsrEn = 0. - procPciePortIndirectRegisterRMW (Arg0, 0xA1, Not (0x00001000), 0x0) - } else { - procPciePortIndirectRegisterRMW (Arg0, 0xA1, Not (0x00001000), 0x00001000) - } - - // Determine port PCI address and check port present - Store (ShiftLeft (Add( Arg0, 2), 3), varPortBdfLocal1) - And (procPciDwordRead (varPortBdfLocal1, 0x70), 0x400000, varPortPresentLocal3) - if (LNotEqual (varPortPresentLocal3, 0)) { - procDisableAndSaveAspm (Arg0) - Store (1, Local2) - while (Local2) { - //retrain port - procPciDwordRMW (varPortBdfLocal1, 0x68, Not (0x00000000), 0x20) - Sleep (30) - while (And (procPciDwordRead (varPortBdfLocal1, 0x68), 0x08000000)) { - Sleep (10) - } - Store (0, Local2) - if (LEqual (Arg1, DEF_LINK_SPEED_GEN1)) { - Store (procPciePortIndirectRegisterRead (Arg0, 0xA4), varLcCurrentDataRateLocal4) - if (LNotEqual (And (varLcCurrentDataRateLocal4, 0x800), 0)) { - Store (1, Local2) - } - } - } - procRestoreAspm (Arg0) - } else { - Store (" Device not present. Set capability and speed only", Debug) - } - //Hide UMI port - if (LEqual (Arg0, 6)) { - procIndirectRegisterRMW (0x0, 0x60, 0x80, Not (0x40), 0x00); - } - Store ("SetPortCapabilityAndSpeed Exit", Debug) - } - - Name (varPcieLinkControlArray, Package () {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}) - Name (varPcieLinkControlOffset, 0) - Name (varPcieLinkControlData, 0) - - /*----------------------------------------------------------------------------------------*/ - /** - * Disable and save ASPM state - * - * Arg0 - Port Index - */ - Method (procDisableAndSaveAspm, 1, Serialized) { - Store (0, varPcieLinkControlOffset) - Store (0, varPcieLinkControlData) - - Store (ShiftLeft (Add( Arg0, 2), 3), varPortBdfLocal1) - if (LEqual (Arg0, 6)) { - Store (" Disable SB ASPM", Debug) - Store (procPcieSbAspmControl (0, 0), Index (varPcieLinkControlArray, 0)) - Store (Concatenate (" PcieLinkControl Data : ", ToHexString (DerefOf(Index (varPcieLinkControlArray, 0))), varStringBuffer), Debug) - procPcieSbAspmControl (0, 1) - return (0) - } - - Store (procPciDwordRead (varPortBdfLocal1, 0x18), varTempLocal3) - Store (And (ShiftRight (varTempLocal3, 8), 0xFF), varTempLocal3) - - Store (Concatenate (" Disable EP ASPM on Secondary Bus : ", ToHexString (varTempLocal3), varStringBuffer), Debug) - - Store (ShiftLeft (varTempLocal3, 8), varEndpointBdfLocal2) - Store (procPciDwordRead (varEndpointBdfLocal2, 0xC), varTempLocal3) - Store (And (ShiftRight (varTempLocal3, 16), 0xFF), varTempLocal3) - - Store (Concatenate (" EP Header type : ", ToHexString (varTempLocal3), varStringBuffer), Debug) - - if (LNotEqual (And (varTempLocal3, 0x80), 0)) { - Store (0x7, varMaxFunctionLocal0) - } else { - Store (0x0, varMaxFunctionLocal0) - } - Store (0, varFunctionLocal4) - while (LLessEqual (varFunctionLocal4, varMaxFunctionLocal0)) { - //Find PcieLinkControl register offset = PcieCapPtr + 0x10 - Store (procFindPciCapability (Add (varEndpointBdfLocal2, varFunctionLocal4), 0x10), varPcieLinkControlOffset) - if (LEqual (varPcieLinkControlOffset, 0)) { - Increment (varFunctionLocal4) - continue - } - Add (varPcieLinkControlOffset, 0x10, varPcieLinkControlOffset) - - Store (Concatenate (" Function number of Secondary Bus : ", ToHexString (varFunctionLocal4), varStringBuffer), Debug) - Store (Concatenate (" PcieLinkControl register offset : ", ToHexString (varPcieLinkControlOffset), varStringBuffer), Debug) - // Save ASPM on EP - Store (procPciDwordRead (Add (varEndpointBdfLocal2, varFunctionLocal4) , varPcieLinkControlOffset), varPcieLinkControlData) - Store (And (varPcieLinkControlData, 0x3), Index (varPcieLinkControlArray, varFunctionLocal4)) - - Store (Concatenate (" PcieLinkControl Data : ", ToHexString (varPcieLinkControlData), varStringBuffer), Debug) - - procPciDwordRMW (Add (varEndpointBdfLocal2, varFunctionLocal4), varPcieLinkControlOffset, Not (0x00000003), 0x00) - Store ("Disable ASPM on EP Complete!!", Debug) - Increment (varFunctionLocal4) - } - } - /*----------------------------------------------------------------------------------------*/ - /** - * Restore ASPM - * - * Arg0 - Port Index - */ - Method (procRestoreAspm, 1, Serialized) { - - Store (0, varPcieLinkControlOffset) - Store (0, varPcieLinkControlData) - - - // Restore SB ASPM - if (LEqual (Arg0, 6)) { - Store (" Restore SB ASPM", Debug) - Store (Concatenate (" PcieLinkControl Data : ", ToHexString (DerefOf(Index (varPcieLinkControlArray, 0))), varStringBuffer), Debug) - procPcieSbAspmControl (DerefOf(Index (varPcieLinkControlArray, 0)), 1) - return (0) - } - Store (ShiftLeft (Add( Arg0, 2), 3), varPortBdfLocal1) - // Restore EP ASPM - Store (procPciDwordRead (varPortBdfLocal1, 0x18), varTempLocal3) - Store (And (ShiftRight (varTempLocal3, 8), 0xFF), varTempLocal3) - - Store (Concatenate (" Disable EP ASPM on SecondaryBus : ", ToHexString (varTempLocal3), varStringBuffer), Debug) - - Store (ShiftLeft (varTempLocal3, 8), varEndpointBdfLocal2) - Store (procPciDwordRead (varEndpointBdfLocal2, 0xC), varTempLocal3) - Store (And (ShiftRight (varTempLocal3, 16), 0xFF), varTempLocal3) - - Store (Concatenate (" EP Header type : ", ToHexString (varTempLocal3), varStringBuffer), Debug) - - if (LNotEqual (And (varTempLocal3, 0x80), 0)) { - Store (0x7, varMaxFunctionLocal0) - } else { - Store (0x0, varMaxFunctionLocal0) - } - Store (0, varFunctionLocal4) - while (LLessEqual (varFunctionLocal4, varMaxFunctionLocal0)) { - //Find PcieLinkControl register offset = PcieCapPtr + 0x10 - Store (procFindPciCapability (Add (varEndpointBdfLocal2, varFunctionLocal4), 0x10), varPcieLinkControlOffset) - if (LEqual (varPcieLinkControlOffset, 0)) { - Increment (varFunctionLocal4) - continue - } - Add (varPcieLinkControlOffset, 0x10, varPcieLinkControlOffset) - - Store (Concatenate (" Restore Function number of SecondaryBus : ", ToHexString (varFunctionLocal4), varStringBuffer), Debug) - Store (Concatenate (" Restore PcieLinkControl register offset : ", ToHexString (varPcieLinkControlOffset), varStringBuffer), Debug) - Store (Concatenate (" PcieLinkControl Data : ", ToHexString (DerefOf (Index (varPcieLinkControlArray, varFunctionLocal4))), varStringBuffer), Debug) - - procPciDwordWrite (Add (varEndpointBdfLocal2, varFunctionLocal4), varPcieLinkControlOffset, DerefOf (Index (varPcieLinkControlArray, varFunctionLocal4))) - Increment (varFunctionLocal4) - } - } - - /*----------------------------------------------------------------------------------------*/ - /** - * Request VID - * - * Arg0 - Port Index - * Arg1 - PCIe speed - */ - - Method (procPcieSetLinkSpeed, 2) { - Store (ShiftLeft (Add( Arg0, 2), 3), Local0) - if (LEqual (Arg1, DEF_LINK_SPEED_GEN1)) { - procPciDwordRMW (Local0, 0x88, Not (0x0000002f), 0x21) - procPciePortIndirectRegisterRMW (Arg0, 0xA4, Not (0x20000001), 0x0) - } else { - procPciePortIndirectRegisterRMW (Arg0, 0xA4, Not (0x20000001), 0x20000001) - procPciDwordRMW (Local0, 0x88, Not (0x0000002f), 0x2) - } - } - - /*----------------------------------------------------------------------------------------*/ - /** - * Read PCIe port indirect register - * - * Arg0 - Ref Source Pckage - * Arg1 - Ref to Destination Package - * - */ - Method (procCopyPackage, 2, NotSerialized) { - - Store (SizeOf (Arg0), Local1) - Store (0, Local0) - While (LLess (Local0, Local1)) { - Store (DerefOf(Index(DerefOf (Arg0), Local0)), Index(DerefOf (Arg1), Local0)) - Increment (Local0) - } - } - - /*----------------------------------------------------------------------------------------*/ - /** - * Read PCIe port indirect register - * - * Arg0 - Ref Source Pckage - * Arg1 - Ref to Destination Package - * - */ - Method (procPsppGetAcDcState, 0 , NotSerialized) { - Return (And (varPsppAcDcState, varPsppAcDcOverride)) - } diff --git a/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieConfig/GnbPcieConfig.h b/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieConfig/GnbPcieConfig.h deleted file mode 100644 index 8e91224070..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieConfig/GnbPcieConfig.h +++ /dev/null @@ -1,53 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * PCIe configuration - * - * - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: GNB - * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $ - * - */ -/* -***************************************************************************** -* -* Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* *************************************************************************** -* -*/ - -#ifndef _GNBPCIECONFIG_H_ -#define _GNBPCIECONFIG_H_ - - -#include "PcieConfigData.h" -#include "PcieConfigLib.h" - -#endif diff --git a/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieConfig/Makefile.inc b/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieConfig/Makefile.inc deleted file mode 100644 index d9edf85fae..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieConfig/Makefile.inc +++ /dev/null @@ -1,4 +0,0 @@ -libagesa-y += PcieConfigData.c -libagesa-y += PcieConfigLib.c -libagesa-y += PcieInputParser.c -libagesa-y += PcieMapTopology.c diff --git a/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieConfig/PcieConfigData.c b/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieConfig/PcieConfigData.c deleted file mode 100644 index 62468baafa..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieConfig/PcieConfigData.c +++ /dev/null @@ -1,528 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * GNB function to create/locate PCIe configuration data area - * - * Contain code that create/locate and rebase configuration data area. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: GNB - * @e \$Revision: 49916 $ @e \$Date: 2011-03-30 19:03:54 +0800 (Wed, 30 Mar 2011) $ - * - */ -/* -***************************************************************************** -* -* Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* *************************************************************************** -* -*/ - -/*---------------------------------------------------------------------------------------- - * M O D U L E S U S E D - *---------------------------------------------------------------------------------------- - */ -#include "AGESA.h" -#include "Ids.h" -#include "amdlib.h" -#include "heapManager.h" -#include "OptionGnb.h" -#include "Gnb.h" -#include "GnbPcie.h" -#include "GnbPcieFamServices.h" -#include "cpuRegisters.h" -#include "cpuServices.h" -#include "GnbCommonLib.h" -#include "GnbPcieConfig.h" -#include "PcieMapTopology.h" -#include "PcieInputParser.h" -#include "PcieConfigLib.h" -#include "Filecode.h" -#define FILECODE PROC_GNB_MODULES_GNBPCIECONFIG_PCIECONFIGDATA_FILECODE -/*---------------------------------------------------------------------------------------- - * D E F I N I T I O N S A N D M A C R O S - *---------------------------------------------------------------------------------------- - */ - -extern BUILD_OPT_CFG UserOptions; -extern GNB_BUILD_OPTIONS ROMDATA GnbBuildOptions; - -/*---------------------------------------------------------------------------------------- - * T Y P E D E F S A N D S T R U C T U R E S - *---------------------------------------------------------------------------------------- - */ - - -/*---------------------------------------------------------------------------------------- - * P R O T O T Y P E S O F L O C A L F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ -AGESA_STATUS -PcieConfigurationInit ( - IN AMD_CONFIG_PARAMS *StdHeader - ); - -VOID -STATIC -PcieConfigAttachComplexes ( - IN OUT PCIe_COMPLEX_CONFIG *Base, - IN OUT PCIe_COMPLEX_CONFIG *New - ); - -AGESA_STATUS -PcieUpdateConfigurationData ( - IN PCIe_PLATFORM_CONFIG *Pcie - ); - -AGESA_STATUS -STATIC -PcieConfigBuildData ( - IN AMD_EARLY_PARAMS *EarlyParamsPtr, - IN PCIe_COMPLEX_DESCRIPTOR *PcieComplexList, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -PCIe_COMPLEX_DESCRIPTOR * -PcieConfigProcessUserConfig ( - IN PCIe_COMPLEX_DESCRIPTOR *PcieComplexList, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -/*----------------------------------------------------------------------------------------*/ -/** - * Create internal PCIe configuration data - * - * - * - * @param[in] StdHeader Standard configuration header - * @retval AGESA_SUCCESS Configuration data successfully allocated. - * @retval AGESA_FATAL Configuration data allocation failed. - */ - -AGESA_STATUS -PcieConfigurationInit ( - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - AMD_EARLY_PARAMS *EarlyParamsPtr; - PCIe_COMPLEX_DESCRIPTOR *PcieComplexList; - AGESA_STATUS Status; - EarlyParamsPtr = (AMD_EARLY_PARAMS *) StdHeader; - - /* FIXME: Intentionally discard qualifier const of - * GnbConfig.PcieComplexList here. - */ - PcieComplexList = PcieConfigProcessUserConfig ( - (PCIe_COMPLEX_DESCRIPTOR *)EarlyParamsPtr->GnbConfig.PcieComplexList, - StdHeader); - - if (PcieComplexList == NULL) { - return AGESA_FATAL; - } - GNB_DEBUG_CODE ( - PcieUserConfigConfigDump (PcieComplexList); - ); - Status = PcieConfigBuildData (EarlyParamsPtr, PcieComplexList, StdHeader); - HeapDeallocateBuffer (AMD_GNB_TEMP_DATA_HANDLE, StdHeader); - return Status; -} - -/*----------------------------------------------------------------------------------------*/ -/** - * Create internal PCIe configuration data - * - * - * - * @param[in] StdHeader Standard configuration header - * @retval AGESA_SUCCESS Configuration data successfully allocated. - * @retval AGESA_FATAL Configuration data allocation failed. - */ - -AGESA_STATUS -STATIC -PcieConfigBuildData ( - IN AMD_EARLY_PARAMS *EarlyParamsPtr, - IN PCIe_COMPLEX_DESCRIPTOR *PcieComplexList, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - PCIe_PLATFORM_CONFIG *Pcie; - AGESA_STATUS AgesaStatus; - AGESA_STATUS Status; - PCIe_COMPLEX_DESCRIPTOR *ComplexDescriptor; - UINTN ComplexesDataLength; - UINTN ComplexIndex; - UINTN NumberOfComplexes; - VOID *Buffer; - UINTN Index; - UINT32 NumberOfSockets; - UINT8 SocketId; - PCIe_SILICON_CONFIG *Silicon; - UINTN CurrentComplexesDataLength; - IDS_HDT_CONSOLE (GNB_TRACE, "PcieConfigurationInit Enter\n"); - AgesaStatus = AGESA_SUCCESS; - ComplexesDataLength = 0; - NumberOfSockets = GnbGetNumberOfSockets (StdHeader); - for (SocketId = 0; SocketId < NumberOfSockets; SocketId++) { - if (GnbIsDevicePresentInSocket (SocketId, StdHeader)) { - Status = PcieFmGetComplexDataLength (SocketId, &CurrentComplexesDataLength, StdHeader); - ASSERT (Status == AGESA_SUCCESS); - ComplexesDataLength += CurrentComplexesDataLength; - } - } - NumberOfComplexes = PcieInputParserGetNumberOfComplexes (PcieComplexList); - Pcie = GnbAllocateHeapBuffer (AMD_PCIE_COMPLEX_DATA_HANDLE, sizeof (PCIe_PLATFORM_CONFIG) + ComplexesDataLength, StdHeader); - if (Pcie == NULL) { - IDS_ERROR_TRAP; - return AGESA_FATAL; - } - LibAmdMemFill (Pcie, 0x00, sizeof (PCIe_PLATFORM_CONFIG) + ComplexesDataLength, StdHeader); - Pcie->StdHeader = (PVOID) (intptr_t) StdHeader; - Pcie->Header.Child = offsetof (PCIe_PLATFORM_CONFIG, ComplexList); - PcieConfigSetDescriptorFlags (Pcie, DESCRIPTOR_PLATFORM | DESCRIPTOR_TERMINATE_LIST | DESCRIPTOR_TERMINATE_TOPOLOGY); - Buffer = (UINT8 *) (Pcie) + sizeof (PCIe_PLATFORM_CONFIG); - ComplexIndex = 0; - for (SocketId = 0; SocketId < NumberOfSockets; SocketId++) { - if (GnbIsDevicePresentInSocket (SocketId, StdHeader)) { - if (ComplexIndex > MAX_NUMBER_OF_COMPLEXES) { - IDS_ERROR_TRAP; - return AGESA_FATAL; - } - Pcie->ComplexList[ComplexIndex].Header.Child = (UINT16) ((UINT8 *) Buffer - (UINT8 *) &Pcie->ComplexList[ComplexIndex]); - Pcie->ComplexList[ComplexIndex].Header.Parent = (UINT16) ((UINT8 *) &Pcie->ComplexList[ComplexIndex] - (UINT8 *) Pcie); - PcieConfigSetDescriptorFlags (&Pcie->ComplexList[ComplexIndex], DESCRIPTOR_COMPLEX | DESCRIPTOR_TERMINATE_LIST | DESCRIPTOR_TERMINATE_GNB | DESCRIPTOR_TERMINATE_TOPOLOGY); - PcieFmBuildComplexConfiguration (SocketId, Buffer, StdHeader); - Silicon = PcieConfigGetChildSilicon (&Pcie->ComplexList[ComplexIndex]); - Silicon->Header.Parent = (UINT16) ((UINT8 *) Silicon - (UINT8 *) &Pcie->ComplexList[ComplexIndex]); - for (Index = 0; Index < NumberOfComplexes; Index++) { - ComplexDescriptor = PcieInputParserGetComplexDescriptor (PcieComplexList, Index); - if (ComplexDescriptor->SocketId == SocketId) { - Status = PcieMapTopologyOnComplex (ComplexDescriptor, &Pcie->ComplexList[ComplexIndex], Pcie); - Pcie->ComplexList[ComplexIndex].SocketId = SocketId; - AGESA_STATUS_UPDATE (Status, AgesaStatus); - if (ComplexIndex > 0) { - PcieConfigAttachComplexes (&Pcie->ComplexList[ComplexIndex - 1], &Pcie->ComplexList[ComplexIndex]); - } - } - } - PcieFmGetComplexDataLength (SocketId, &CurrentComplexesDataLength, StdHeader); - Buffer = (VOID *) ((UINT8 *) Buffer + CurrentComplexesDataLength); - ComplexIndex++; - } - } - Pcie->LinkReceiverDetectionPooling = GnbBuildOptions.CfgGnbLinkReceiverDetectionPooling; - Pcie->LinkL0Pooling = GnbBuildOptions.CfgGnbLinkL0Pooling; - Pcie->LinkGpioResetAssertionTime = GnbBuildOptions.CfgGnbLinkGpioResetAssertionTime; - Pcie->LinkResetToTrainingTime = GnbBuildOptions.CfgGnbLinkResetToTrainingTime; - Pcie->GfxCardWorkaround = GfxWorkaroundEnable; - Pcie->TrainingExitState = LinkStateTrainingCompleted; - Pcie->TrainingAlgorithm = GnbBuildOptions.CfgGnbTrainingAlgorithm; - if ((UserOptions.CfgAmdPlatformType & AMD_PLATFORM_MOBILE) != 0) { - Pcie->GfxCardWorkaround = GfxWorkaroundDisable; - } - Pcie->PsppPolicy = EarlyParamsPtr->GnbConfig.PsppPolicy; - IDS_OPTION_CALLOUT (IDS_CALLOUT_GNB_PCIE_PLATFORM_CONFIG, Pcie, StdHeader); - GNB_DEBUG_CODE ( - PcieConfigDebugDump (Pcie); - ); - IDS_HDT_CONSOLE (GNB_TRACE, "PcieConfigurationInit Exit [0x%x]\n", AgesaStatus); - return AgesaStatus; -} - -/*----------------------------------------------------------------------------------------*/ -/** - * Locate global PCIe configuration data - * - * - * - * @param[in] PcieComplexList User PCIe topology configuration - * @param[out] StdHeader Standard configuration header - * @retval Updated topology configuration - */ -PCIe_COMPLEX_DESCRIPTOR * -PcieConfigProcessUserConfig ( - IN PCIe_COMPLEX_DESCRIPTOR *PcieComplexList, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - UINT32 Node0SocketId; - UINT32 Node0SiliconId; - UINTN NumberOfComplexes; - UINTN NumberOfPorts; - UINTN Index; - UINT16 DescriptorLoLane; - UINT16 DescriptorHiLane; - PCIe_COMPLEX_DESCRIPTOR *ResultComplexConfig; - PCIe_COMPLEX_DESCRIPTOR *SbComplexDescriptor; - PCIe_PORT_DESCRIPTOR *SbPortDescriptor; - PCIe_PORT_DESCRIPTOR DefaultSbPortDescriptor; - PCIe_ENGINE_DESCRIPTOR *EngineDescriptor; - AGESA_STATUS Status; - SbPortDescriptor = NULL; - GetSocketModuleOfNode (0, &Node0SocketId, &Node0SiliconId, StdHeader); - Status = PcieFmGetSbConfigInfo ((UINT8) Node0SocketId, &DefaultSbPortDescriptor, StdHeader); - if (Status == AGESA_UNSUPPORTED) { - return PcieComplexList; - } - if (PcieComplexList == NULL) { - // No complex descriptor for any silicon was provided - // 1. Create complex descriptor - // 2. Create SB port descriptor - // 3. Attach SB descriptor to complex descriptor created in step #1 - ResultComplexConfig = (PCIe_COMPLEX_DESCRIPTOR *) GnbAllocateHeapBufferAndClear ( - AMD_GNB_TEMP_DATA_HANDLE, - sizeof (PCIe_COMPLEX_DESCRIPTOR) + sizeof (PCIe_PORT_DESCRIPTOR), - StdHeader - ); - SbComplexDescriptor = ResultComplexConfig; - SbPortDescriptor = (PCIe_PORT_DESCRIPTOR *) ((UINT8 *) ResultComplexConfig + sizeof (PCIe_COMPLEX_DESCRIPTOR)); - LibAmdMemCopy (SbPortDescriptor, &DefaultSbPortDescriptor, sizeof (PCIe_PORT_DESCRIPTOR), StdHeader); - SbPortDescriptor->Flags |= DESCRIPTOR_TERMINATE_LIST; - // Attach post array to complex descriptor - SbComplexDescriptor->PciePortList = SbPortDescriptor; - SbComplexDescriptor->SocketId = Node0SocketId; - SbComplexDescriptor->Flags |= DESCRIPTOR_TERMINATE_LIST; - } else { - NumberOfComplexes = PcieInputParserGetNumberOfComplexes (PcieComplexList); - SbComplexDescriptor = PcieInputParserGetComplexDescriptorOfSocket (PcieComplexList, Node0SocketId); - if (SbComplexDescriptor == NULL) { - // No complex descriptor for silicon that have SB attached. - // 1. Create complex descriptor. Will be first one in the list - // 2. Create SB port descriptor - // 3. Attach SB descriptor to complex descriptor created in step #1 - ResultComplexConfig = (PCIe_COMPLEX_DESCRIPTOR *) GnbAllocateHeapBufferAndClear ( - AMD_GNB_TEMP_DATA_HANDLE, - (NumberOfComplexes + 1) * sizeof (PCIe_COMPLEX_DESCRIPTOR) + sizeof (PCIe_PORT_DESCRIPTOR), - StdHeader - ); - SbComplexDescriptor = ResultComplexConfig; - SbPortDescriptor = (PCIe_PORT_DESCRIPTOR *) ((UINT8 *) ResultComplexConfig + (NumberOfComplexes + 1) * sizeof (PCIe_COMPLEX_DESCRIPTOR)); - LibAmdMemCopy (SbPortDescriptor, &DefaultSbPortDescriptor, sizeof (PCIe_PORT_DESCRIPTOR), StdHeader); - SbPortDescriptor->Flags |= DESCRIPTOR_TERMINATE_LIST; - // Attach post array to complex descriptor - SbComplexDescriptor->PciePortList = SbPortDescriptor; - SbComplexDescriptor->SocketId = Node0SocketId; - SbComplexDescriptor->Flags |= DESCRIPTOR_TERMINATE_LIST; - LibAmdMemCopy ( - (UINT8 *) ResultComplexConfig + sizeof (PCIe_COMPLEX_DESCRIPTOR), - PcieComplexList, - NumberOfComplexes * sizeof (PCIe_COMPLEX_DESCRIPTOR), - StdHeader - ); - - } else { - // Complex descriptor that represent silicon that have SB attached exist - // 1. Determine if complex have descriptor for SB - // 2. Create new descriptor for SB if needed - NumberOfPorts = PcieInputParserGetLengthOfPcieEnginesList (SbComplexDescriptor); - ResultComplexConfig = (PCIe_COMPLEX_DESCRIPTOR *) GnbAllocateHeapBuffer ( - AMD_GNB_TEMP_DATA_HANDLE, - NumberOfComplexes * sizeof (PCIe_COMPLEX_DESCRIPTOR) + (NumberOfPorts + 1) * sizeof (PCIe_PORT_DESCRIPTOR), - StdHeader - ); - // Copy complex descriptor array - LibAmdMemCopy ( - ResultComplexConfig, - PcieComplexList, - NumberOfComplexes * sizeof (PCIe_COMPLEX_DESCRIPTOR), - StdHeader - ); - if (NumberOfPorts != 0) { - // Copy port descriptor array associated with complex with SB attached - LibAmdMemCopy ( - (UINT8*) ResultComplexConfig + NumberOfComplexes * sizeof (PCIe_COMPLEX_DESCRIPTOR) + sizeof (PCIe_PORT_DESCRIPTOR), - SbComplexDescriptor->PciePortList, - NumberOfPorts * sizeof (PCIe_PORT_DESCRIPTOR), - StdHeader - ); - // Update SB complex pointer on in memory list - SbComplexDescriptor = PcieInputParserGetComplexDescriptorOfSocket ((PCIe_COMPLEX_DESCRIPTOR *) ResultComplexConfig, Node0SocketId); - // Attach port descriptor array to complex - SbComplexDescriptor->PciePortList = (PCIe_PORT_DESCRIPTOR *) ((UINT8*) ResultComplexConfig + NumberOfComplexes * sizeof (PCIe_COMPLEX_DESCRIPTOR) + sizeof (PCIe_PORT_DESCRIPTOR)); - for (Index = 0; Index < NumberOfPorts; ++Index) { - EngineDescriptor = PcieInputParserGetEngineDescriptor (SbComplexDescriptor, Index); - if (EngineDescriptor->EngineData.EngineType == PciePortEngine) { - DescriptorLoLane = MIN (EngineDescriptor->EngineData.StartLane, EngineDescriptor->EngineData.EndLane); - DescriptorHiLane = MAX (EngineDescriptor->EngineData.StartLane, EngineDescriptor->EngineData.EndLane); - if (DescriptorLoLane >= DefaultSbPortDescriptor.EngineData.StartLane && DescriptorLoLane <= DefaultSbPortDescriptor.EngineData.EndLane) { - SbPortDescriptor = (PCIe_PORT_DESCRIPTOR *) EngineDescriptor; - } - } - } - } - if (SbPortDescriptor == NULL) { - // No descriptor that represent SB where found, create new one, will be first one in list - SbPortDescriptor = (PCIe_PORT_DESCRIPTOR *) ((UINT8*) ResultComplexConfig + NumberOfComplexes * sizeof (PCIe_COMPLEX_DESCRIPTOR)); - // Copy default config info - LibAmdMemCopy (SbPortDescriptor, &DefaultSbPortDescriptor, sizeof (PCIe_PORT_DESCRIPTOR), StdHeader); - // Reattach descriptor list to complex - SbComplexDescriptor->PciePortList = SbPortDescriptor; - } else { - // Move SB descriptor to be first one in array - LibAmdMemCopy ( - (UINT8*) ResultComplexConfig + NumberOfComplexes * sizeof (PCIe_COMPLEX_DESCRIPTOR), - SbPortDescriptor, - sizeof (PCIe_PORT_DESCRIPTOR), - StdHeader - ); - // Disable original SB descriptor - SbPortDescriptor->EngineData.EngineType = PcieUnusedEngine; - //Update pointer to new SB descriptor - SbPortDescriptor = (PCIe_PORT_DESCRIPTOR *) ((UINT8*) ResultComplexConfig + NumberOfComplexes * sizeof (PCIe_COMPLEX_DESCRIPTOR)); - //It is no longer a descriptor that terminates list - SbPortDescriptor->Flags &= (~ DESCRIPTOR_TERMINATE_LIST); - // Reattach descriptor list to complex - SbComplexDescriptor->PciePortList = SbPortDescriptor; - } - } - } - // Mark descriptor as SB link - SbPortDescriptor->Port.MiscControls.SbLink = 0x1; - return ResultComplexConfig; -} - -/*----------------------------------------------------------------------------------------*/ -/** - * Locate global PCIe configuration data - * - * - * - * @param[in] StdHeader Standard configuration header - * @param[out] Pcie Pointer to global PCIe configuration - * @retval AGESA_SUCCESS Configuration data successfully located - * @retval AGESA_FATAL Configuration can not be located. - */ -AGESA_STATUS -PcieLocateConfigurationData ( - IN AMD_CONFIG_PARAMS *StdHeader, - OUT PCIe_PLATFORM_CONFIG **Pcie - ) -{ - *Pcie = GnbLocateHeapBuffer (AMD_PCIE_COMPLEX_DATA_HANDLE, StdHeader); - if (*Pcie == NULL) { - IDS_ERROR_TRAP; - return AGESA_FATAL; - } - PcieUpdateConfigurationData (*Pcie); - (*Pcie)->StdHeader = (PVOID) (intptr_t) StdHeader; - return AGESA_SUCCESS; -} - -/*----------------------------------------------------------------------------------------*/ -/** - * Attache descriptors - * - * - * @param[in] Type Descriptor type - * @param[in,out] Base Base descriptor - * @param[in,out] New New descriptor - */ -VOID -STATIC -PcieConfigAttachDescriptors ( - IN UINT32 Type, - IN OUT PCIe_DESCRIPTOR_HEADER *Base, - IN OUT PCIe_DESCRIPTOR_HEADER *New - ) -{ - PCIe_DESCRIPTOR_HEADER *Left; - PCIe_DESCRIPTOR_HEADER *Right; - - Left = PcieConfigGetPeer (DESCRIPTOR_TERMINATE_GNB, PcieConfigGetChild (Type, Base)); - Right = PcieConfigGetChild (Type, New); - Left->Peer = (UINT16) ((UINT8 *) Right - (UINT8 *) Left); - PcieConfigResetDescriptorFlags (Left, DESCRIPTOR_TERMINATE_TOPOLOGY); -} - - -/*----------------------------------------------------------------------------------------*/ -/** - * Attach configurations of two GNB to each other. - * - * Function will link all data structure to linked lists - * - * @param[in,out] Base Base complex descriptor - * @param[in,out] New New complex descriptor - */ -VOID -STATIC -PcieConfigAttachComplexes ( - IN OUT PCIe_COMPLEX_CONFIG *Base, - IN OUT PCIe_COMPLEX_CONFIG *New - ) -{ - // Connect Complex - Base->Header.Peer = (UINT16) ((UINT8 *) New - (UINT8 *) Base); - PcieConfigResetDescriptorFlags (Base, DESCRIPTOR_TERMINATE_TOPOLOGY); - // Connect Silicon - PcieConfigAttachDescriptors (DESCRIPTOR_SILICON, &Base->Header, &New->Header); - // Connect Wrappers - PcieConfigAttachDescriptors (DESCRIPTOR_PCIE_WRAPPER | DESCRIPTOR_DDI_WRAPPER, &Base->Header, &New->Header); - // Connect Engines - PcieConfigAttachDescriptors (DESCRIPTOR_PCIE_ENGINE | DESCRIPTOR_DDI_ENGINE, &Base->Header, &New->Header); -} - -/*----------------------------------------------------------------------------------------*/ -/** - * Update configuration data - * - * Puprouse of this structure to update config data that base on programming of - * other silicon compoments. For instance PCI address of GNB and PCIe ports - * can change by AGESA or external agent - * - * - * @param[in,out] Pcie Pointer to global PCIe configuration - * @retval AGESA_SUCCESS Configuration data successfully update - * @retval AGESA_FATAL Failt to update configuration - */ -AGESA_STATUS -PcieUpdateConfigurationData ( - IN PCIe_PLATFORM_CONFIG *Pcie - ) -{ - PCIe_SILICON_CONFIG *Silicon; - PCIe_ENGINE_CONFIG *Engine; - PCI_ADDR NewAddress; - // Update silicon configuration - Silicon = PcieConfigGetChildSilicon (Pcie); - while (Silicon != NULL) { - NewAddress = GnbGetPciAddress (PcieConfigGetParentComplex (Silicon)->SocketId, Silicon->SiliconId, GnbLibGetHeader (Pcie)); - if (Silicon->Address.AddressValue != NewAddress.AddressValue) { - Silicon->Address.AddressValue = NewAddress.AddressValue; - Engine = PcieConfigGetChildEngine (Silicon); - while (Engine != NULL) { - if (PcieConfigIsPcieEngine (Engine)) { - Engine->Type.Port.Address.Address.Bus = Silicon->Address.Address.Bus; - } - Engine = (PCIe_ENGINE_CONFIG *) PcieConfigGetNextTopologyDescriptor (Engine, DESCRIPTOR_TERMINATE_GNB); - } - } - Silicon = (PCIe_SILICON_CONFIG *) PcieConfigGetNextTopologyDescriptor (Silicon, DESCRIPTOR_TERMINATE_TOPOLOGY); - } - return AGESA_SUCCESS; -} diff --git a/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieConfig/PcieConfigData.h b/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieConfig/PcieConfigData.h deleted file mode 100644 index 6a1b3accab..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieConfig/PcieConfigData.h +++ /dev/null @@ -1,57 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * GNB function to create/locate PCIe configuration data area - * - * Contain code that create/locate and rebase configuration data area. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: GNB - * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $ - * - */ -/* -***************************************************************************** -* -* Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* *************************************************************************** -* -*/ - -#ifndef _PCIECONFIGDATA_H_ -#define _PCIECONFIGDATA_H_ - - -AGESA_STATUS -PcieLocateConfigurationData ( - IN AMD_CONFIG_PARAMS *StdHeader, - OUT PCIe_PLATFORM_CONFIG **Pcie - ); - -#endif - diff --git a/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieConfig/PcieConfigLib.c b/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieConfig/PcieConfigLib.c deleted file mode 100644 index c76b290727..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieConfig/PcieConfigLib.c +++ /dev/null @@ -1,720 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * GNB function to create/locate PCIe configuration data area - * - * Contain code that create/locate and rebase configuration data area. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: GNB - * @e \$Revision: 49532 $ @e \$Date: 2011-03-25 02:54:43 +0800 (Fri, 25 Mar 2011) $ - * - */ -/* -***************************************************************************** -* -* Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* *************************************************************************** -* -*/ - -/*---------------------------------------------------------------------------------------- - * M O D U L E S U S E D - *---------------------------------------------------------------------------------------- - */ -#include "AGESA.h" -#include "Ids.h" -#include "amdlib.h" -#include "Gnb.h" -#include "GnbPcie.h" -#include "GnbPcieFamServices.h" -#include "GnbCommonLib.h" -#include "GnbPcieConfig.h" -#include "PcieMapTopology.h" -#include "PcieInputParser.h" -#include "Filecode.h" -#define FILECODE PROC_GNB_MODULES_GNBPCIECONFIG_PCIECONFIGLIB_FILECODE -/*---------------------------------------------------------------------------------------- - * D E F I N I T I O N S A N D M A C R O S - *---------------------------------------------------------------------------------------- - */ - - -/*---------------------------------------------------------------------------------------- - * T Y P E D E F S A N D S T R U C T U R E S - *---------------------------------------------------------------------------------------- - */ - - -/*---------------------------------------------------------------------------------------- - * P R O T O T Y P E S O F L O C A L F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ - -/*----------------------------------------------------------------------------------------*/ -/** - * get Master Lane of PCIe port engine - * - * - * - * @param[in] Engine Pointer to engine descriptor - * @retval Master Engine Lane Number - */ -UINT8 -PcieConfigGetPcieEngineMasterLane ( - IN PCIe_ENGINE_CONFIG *Engine - ) -{ - UINT8 MasterLane; - ASSERT (PcieConfigIsPcieEngine (Engine)); - if (Engine->EngineData.StartLane <= Engine->EngineData.EndLane) { - MasterLane = (UINT8) Engine->Type.Port.StartCoreLane; - } else { - MasterLane = (UINT8) Engine->Type.Port.EndCoreLane; - } - return MasterLane; -} - -/*----------------------------------------------------------------------------------------*/ -/** - * Get number of core lanes - * - * - * - * @param[in] Engine Pointer to engine descriptor - * @retval Number of core lane - */ -UINT8 -PcieConfigGetNumberOfCoreLane ( - IN PCIe_ENGINE_CONFIG *Engine - ) -{ - if (Engine->Type.Port.StartCoreLane >= UNUSED_LANE_ID || Engine->Type.Port.EndCoreLane >= UNUSED_LANE_ID) { - return 0; - } - return (UINT8) (Engine->Type.Port.EndCoreLane - Engine->Type.Port.StartCoreLane + 1); -} - -/*----------------------------------------------------------------------------------------*/ -/** - * Disable engine - * - * - * - * @param[in] Engine Pointer to engine config descriptor - */ -VOID -PcieConfigDisableEngine ( - IN PCIe_ENGINE_CONFIG *Engine - ) -{ - if (PcieConfigIsSbPcieEngine (Engine)) { - return; - } - PcieConfigResetDescriptorFlags (Engine, DESCRIPTOR_ALLOCATED); -} - - -/*----------------------------------------------------------------------------------------*/ -/** - * Disable all engines on wrapper - * - * - * - * @param[in] EngineTypeMask Engine type bitmap. - * @param[in] Wrapper Pointer to wrapper config descriptor - */ -VOID -PcieConfigDisableAllEngines ( - IN UINTN EngineTypeMask, - IN PCIe_WRAPPER_CONFIG *Wrapper - ) -{ - PCIe_ENGINE_CONFIG *EngineList; - EngineList = PcieConfigGetChildEngine (Wrapper); - while (EngineList != NULL) { - if ((EngineList->EngineData.EngineType & EngineTypeMask) != 0) { - PcieConfigDisableEngine (EngineList); - } - EngineList = PcieLibGetNextDescriptor (EngineList); - } -} - - -/*----------------------------------------------------------------------------------------*/ -/** - * Get engine PHY lanes bitmap - * - * - * - * @param[in] Engine Pointer to engine config descriptor - */ -UINT32 -PcieConfigGetEnginePhyLaneBitMap ( - IN PCIe_ENGINE_CONFIG *Engine - ) -{ - UINT32 LaneBitMap; - LaneBitMap = 0; - if (PcieLibIsEngineAllocated (Engine)) { - LaneBitMap = ((1 << PcieConfigGetNumberOfPhyLane (Engine)) - 1) << (PcieLibGetLoPhyLane (Engine) - PcieConfigGetParentWrapper (Engine)->StartPhyLane); - } - return LaneBitMap; -} - - -/*----------------------------------------------------------------------------------------*/ -/** - * Get number of phy lanes - * - * - * - * @param[in] Engine Pointer to engine config descriptor - * @retval Number of Phy lane - */ -UINT8 -PcieConfigGetNumberOfPhyLane ( - IN PCIe_ENGINE_CONFIG *Engine - ) -{ - if (Engine->EngineData.StartLane >= UNUSED_LANE_ID || Engine->EngineData.EndLane >= UNUSED_LANE_ID) { - return 0; - } - if (Engine->EngineData.StartLane > Engine->EngineData.EndLane) { - return (UINT8) (Engine->EngineData.StartLane - Engine->EngineData.EndLane + 1); - } else { - return (UINT8) (Engine->EngineData.EndLane - Engine->EngineData.StartLane + 1); - } -} - -/*----------------------------------------------------------------------------------------*/ -/** - * Get port configuration signature for given wrapper and core - * - * Support for unify register access through index/data pair on GNB - * - * @param[in] Wrapper Pointer to wrapper config descriptor - * @param[in] CoreId Core ID - * @retval Configuration Signature - */ -UINT64 -PcieConfigGetConfigurationSignature ( - IN PCIe_WRAPPER_CONFIG *Wrapper, - IN UINT8 CoreId - ) -{ - UINT64 ConfigurationSignature; - PCIe_ENGINE_CONFIG *EngineList; - ConfigurationSignature = 0; - EngineList = PcieConfigGetChildEngine (Wrapper); - while (EngineList != NULL) { - if (EngineList->Type.Port.CoreId == CoreId) { - ConfigurationSignature = (ConfigurationSignature << 8) | PcieConfigGetNumberOfCoreLane (EngineList); - } - EngineList = PcieLibGetNextDescriptor (EngineList); - } - return ConfigurationSignature; -} - -/*----------------------------------------------------------------------------------------*/ -/** - * Check Port Status - * - * - * - * @param[in] Engine Pointer to engine config descriptor - * @param[in] PortStatus Check if status asserted for port - * @retval TRUE if status asserted - */ -BOOLEAN -PcieConfigCheckPortStatus ( - IN PCIe_ENGINE_CONFIG *Engine, - IN UINT32 PortStatus - ) -{ - return (Engine->InitStatus & PortStatus) == 0 ? FALSE : TRUE; -} - -/*----------------------------------------------------------------------------------------*/ -/** - * Set/Reset port status - * - * - * - * @param[in] Engine Pointer to engine config descriptor - * @param[in] SetStatus SetStatus - * @param[in] ResetStatus ResetStatus - * - */ -UINT32 -PcieConfigUpdatePortStatus ( - IN PCIe_ENGINE_CONFIG *Engine, - IN UINT32 SetStatus, - IN UINT32 ResetStatus - ) -{ - Engine->InitStatus |= SetStatus; - Engine->InitStatus &= (~ResetStatus); - return Engine->InitStatus; -} - -/*----------------------------------------------------------------------------------------*/ -/** - * Execute callback on all descriptor of specific type - * - * - * @param[in] DescriptorFlags Descriptor flags - * @param[in] TerminateFlags terminate flags - * @param[in] Callback Pointer to callback function - * @param[in, out] Buffer Pointer to buffer to pass information to callback - * @param[in] Pcie Pointer to global PCIe configuration - */ - -AGESA_STATUS -PcieConfigRunProcForAllDescriptors ( - IN UINT32 InDescriptorFlags, - IN UINT32 OutDescriptorFlags, - IN UINT32 TerminationFlags, - IN PCIe_RUN_ON_DESCRIPTOR_CALLBACK Callback, - IN OUT VOID *Buffer, - IN PCIe_PLATFORM_CONFIG *Pcie - ) -{ - AGESA_STATUS AgesaStatus; - AGESA_STATUS Status; - PCIe_DESCRIPTOR_HEADER *Descriptor; - - AgesaStatus = AGESA_SUCCESS; - Descriptor = PcieConfigGetChild (InDescriptorFlags & DESCRIPTOR_ALL_TYPES, &Pcie->Header); - while (Descriptor != NULL) { - if ((InDescriptorFlags & Descriptor->DescriptorFlags) != 0 && (OutDescriptorFlags && Descriptor->DescriptorFlags) == 0) { - Status = Callback (Descriptor, Buffer, Pcie); - AGESA_STATUS_UPDATE (Status, AgesaStatus); - } - Descriptor = (PCIe_DESCRIPTOR_HEADER *) PcieConfigGetNextTopologyDescriptor (Descriptor, TerminationFlags); - } - return AgesaStatus; -} - -/*----------------------------------------------------------------------------------------*/ -/** - * Execute callback on all wrappers in topology - * - * - * @param[in] DescriptorFlags Wrapper Flags - * @param[in] Callback Pointer to callback function - * @param[in, out] Buffer Pointer to buffer to pass information to callback - * @param[in] Pcie Pointer to global PCIe configuration - */ - -AGESA_STATUS -PcieConfigRunProcForAllWrappers ( - IN UINT32 DescriptorFlags, - IN PCIe_RUN_ON_WRAPPER_CALLBACK Callback, - IN OUT VOID *Buffer, - IN PCIe_PLATFORM_CONFIG *Pcie - ) -{ - AGESA_STATUS AgesaStatus; - AGESA_STATUS Status; - PCIe_WRAPPER_CONFIG *Wrapper; - - AgesaStatus = AGESA_SUCCESS; - Wrapper = (PCIe_WRAPPER_CONFIG *) PcieConfigGetChild (DESCRIPTOR_ALL_WRAPPERS, &Pcie->Header); - while (Wrapper != NULL) { - if (!(PcieLibIsVirtualDesciptor (Wrapper) && (DescriptorFlags & DESCRIPTOR_VIRTUAL) == 0)) { - if ((DescriptorFlags & DESCRIPTOR_ALL_WRAPPERS & Wrapper->Header.DescriptorFlags) != 0) { - Status = Callback (Wrapper, Buffer, Pcie); - AGESA_STATUS_UPDATE (Status, AgesaStatus); - } - } - Wrapper = (PCIe_WRAPPER_CONFIG *) PcieConfigGetNextTopologyDescriptor (Wrapper, DESCRIPTOR_TERMINATE_TOPOLOGY); - } - return AgesaStatus; -} - - -/*----------------------------------------------------------------------------------------*/ -/** - * Execute callback on all engine in topology - * - * - * @param[in] DescriptorFlags Engine flags. - * @param[in] Callback Pointer to callback function - * @param[in, out] Buffer Pointer to buffer to pass information to callback - * @param[in] Pcie Pointer to global PCIe configuration - */ - -VOID -PcieConfigRunProcForAllEngines ( - IN UINT32 DescriptorFlags, - IN PCIe_RUN_ON_ENGINE_CALLBACK Callback, - IN OUT VOID *Buffer, - IN PCIe_PLATFORM_CONFIG *Pcie - ) -{ - - PCIe_ENGINE_CONFIG *Engine; - Engine = (PCIe_ENGINE_CONFIG *) PcieConfigGetChild (DESCRIPTOR_ALL_ENGINES, &Pcie->Header); - while (Engine != NULL) { - if (!(PcieLibIsVirtualDesciptor (Engine) && (DescriptorFlags & DESCRIPTOR_VIRTUAL) == 0)) { - if (!((DescriptorFlags & DESCRIPTOR_ALLOCATED) != 0 && !PcieLibIsEngineAllocated (Engine))) { - if ((Engine->Header.DescriptorFlags & DESCRIPTOR_ALL_ENGINES & DescriptorFlags) != 0) { - Callback (Engine, Buffer, Pcie); - } - } - } - Engine = (PCIe_ENGINE_CONFIG *) PcieConfigGetNextTopologyDescriptor (Engine, DESCRIPTOR_TERMINATE_TOPOLOGY); - } -} - -/*----------------------------------------------------------------------------------------*/ -/** - * Get parent descriptor of specific type - * - * - * @param[in] Type Descriptor type - * @param[in] Descriptor Pointer to buffer to pass information to callback - */ -PCIe_DESCRIPTOR_HEADER * -PcieConfigGetParent ( - IN UINT32 Type, - IN PCIe_DESCRIPTOR_HEADER *Descriptor - ) -{ - while ((Descriptor->DescriptorFlags & Type) == 0) { - if (Descriptor->Parent != 0) { - Descriptor = (PCIe_DESCRIPTOR_HEADER *) ((UINT8 *) Descriptor - Descriptor->Parent); - } else { - return NULL; - } - } - return Descriptor; -} - -/*----------------------------------------------------------------------------------------*/ -/** - * Get child descriptor of specific type - * - * - * @param[in] Type Descriptor type - * @param[in] Descriptor Pointer to buffer to pass information to callback - */ -PCIe_DESCRIPTOR_HEADER * -PcieConfigGetChild ( - IN UINT32 Type, - IN PCIe_DESCRIPTOR_HEADER *Descriptor - ) -{ - while ((Descriptor->DescriptorFlags & Type) == 0) { - if (Descriptor->Child != 0) { - Descriptor = (PCIe_DESCRIPTOR_HEADER *) ((UINT8 *) Descriptor + Descriptor->Child); - } else { - return NULL; - } - } - return Descriptor; -} - -/*----------------------------------------------------------------------------------------*/ -/** - * Get peer descriptor of specific type - * - * - * @param[in] Type Descriptor type - * @param[in] Descriptor Pointer to buffer to pass information to callback - */ -PCIe_DESCRIPTOR_HEADER * -PcieConfigGetPeer ( - IN UINT32 Type, - IN PCIe_DESCRIPTOR_HEADER *Descriptor - ) -{ - while ((Descriptor->DescriptorFlags & Type) == 0) { - if (Descriptor->Peer != 0) { - Descriptor = (PCIe_DESCRIPTOR_HEADER *) ((UINT8 *) Descriptor + Descriptor->Peer); - } else { - return NULL; - } - } - return Descriptor; -} - -/*----------------------------------------------------------------------------------------*/ -/** - * Helper function to dump engine configuration - * - * - * @param[in] EngineList Engine Configuration - */ -VOID -PcieConfigEngineDebugDump ( - IN PCIe_ENGINE_CONFIG *EngineList - ) -{ - IDS_HDT_CONSOLE (PCIE_MISC, " Descriptor Flags - 0x%08x\n", EngineList->Header.DescriptorFlags); - IDS_HDT_CONSOLE (PCIE_MISC, " Engine Type - %s\n Start Phy Lane - %d\n End Phy Lane - %d\n", - ((EngineList->EngineData.EngineType == PciePortEngine) ? "PCIe Port" : "DDI Link"), - EngineList->EngineData.StartLane, - EngineList->EngineData.EndLane - ); - IDS_HDT_CONSOLE (PCIE_MISC, " Scrath - %d\n", EngineList->Scratch); - IDS_HDT_CONSOLE (PCIE_MISC, " Init Status - 0x%08x\n", EngineList->InitStatus); - if (PcieLibIsPcieEngine (EngineList)) { - IDS_HDT_CONSOLE (PCIE_MISC, " PCIe port configuration:\n"); - IDS_HDT_CONSOLE (PCIE_MISC, " Port Training - %s\n", - (EngineList->Type.Port.PortData.PortPresent == PortDisabled) ? "Disable" : "Enabled" - ); - IDS_HDT_CONSOLE (PCIE_MISC, " Start Core Lane - %d\n", EngineList->Type.Port.StartCoreLane); - IDS_HDT_CONSOLE (PCIE_MISC, " End Core Lane - %d\n", EngineList->Type.Port.EndCoreLane); - IDS_HDT_CONSOLE (PCIE_MISC, " Requested PCI Dev Number - %d\n",EngineList->Type.Port.PortData.DeviceNumber); - IDS_HDT_CONSOLE (PCIE_MISC, " Requested PCI Func Number - %d\n",EngineList->Type.Port.PortData.FunctionNumber); - IDS_HDT_CONSOLE (PCIE_MISC, " PCI Address - %d:%d:%d\n", - EngineList->Type.Port.Address.Address.Bus, - EngineList->Type.Port.Address.Address.Device, - EngineList->Type.Port.Address.Address.Function - ); - IDS_HDT_CONSOLE (PCIE_MISC, " Misc Control - %d\n", EngineList->Type.Port.PortData.MiscControls); - IDS_HDT_CONSOLE (PCIE_MISC, " Native PCI Dev Number - %d\n", EngineList->Type.Port.NativeDevNumber); - IDS_HDT_CONSOLE (PCIE_MISC, " Native PCI Func Number - %d\n", EngineList->Type.Port.NativeFunNumber); - IDS_HDT_CONSOLE (PCIE_MISC, " Hotplug - %s\n", - (EngineList->Type.Port.PortData.LinkHotplug == HotplugDisabled) ? "Disabled" : ( - (EngineList->Type.Port.PortData.LinkHotplug == HotplugBasic) ? "Basic" : ( - (EngineList->Type.Port.PortData.LinkHotplug == HotplugServer) ? "Server" : ( - (EngineList->Type.Port.PortData.LinkHotplug == HotplugEnhanced) ? "Enhanced" : ( - (EngineList->Type.Port.PortData.LinkHotplug == HotplugInboard) ? "Inboard" : "Unknown")))) - ); - ASSERT (EngineList->Type.Port.PortData.LinkHotplug < MaxHotplug); - IDS_HDT_CONSOLE (PCIE_MISC, " ASPM - %s\n", - (EngineList->Type.Port.PortData.LinkAspm == AspmDisabled) ? "Disabled" : ( - (EngineList->Type.Port.PortData.LinkAspm == AspmL0s) ? "L0s" : ( - (EngineList->Type.Port.PortData.LinkAspm == AspmL1) ? "L1" : ( - (EngineList->Type.Port.PortData.LinkAspm == AspmL0sL1) ? "L0s & L1" : "Unknown"))) - ); - ASSERT (EngineList->Type.Port.PortData.LinkAspm < MaxAspm); - IDS_HDT_CONSOLE (PCIE_MISC, " Speed - %d\n", - EngineList->Type.Port.PortData.LinkSpeedCapability - ); - } else { - IDS_HDT_CONSOLE (PCIE_MISC, " DDI configuration:\n"); - IDS_HDT_CONSOLE (PCIE_MISC, " Connector - %s\n", - (EngineList->Type.Ddi.DdiData.ConnectorType == ConnectorTypeDP) ? "DP" : ( - (EngineList->Type.Ddi.DdiData.ConnectorType == ConnectorTypeEDP) ? "eDP" : ( - (EngineList->Type.Ddi.DdiData.ConnectorType == ConnectorTypeSingleLinkDVI) ? "Single Link DVI" : ( - (EngineList->Type.Ddi.DdiData.ConnectorType == ConnectorTypeDualLinkDVI) ? "Dual Link DVI" : ( - (EngineList->Type.Ddi.DdiData.ConnectorType == ConnectorTypeHDMI) ? "HDMI" : ( - (EngineList->Type.Ddi.DdiData.ConnectorType == ConnectorTypeTravisDpToVga) ? "Travis DP-to-VGA" : ( - (EngineList->Type.Ddi.DdiData.ConnectorType == ConnectorTypeTravisDpToLvds) ? "Travis DP-to-LVDS" : ( - (EngineList->Type.Ddi.DdiData.ConnectorType == ConnectorTypeLvds) ? "LVDS" : ( - (EngineList->Type.Ddi.DdiData.ConnectorType == ConnectorTypeNutmegDpToVga) ? "Hudson-2 Nutmeg DP-to-VGA" : ( - (EngineList->Type.Ddi.DdiData.ConnectorType == ConnectorTypeSingleLinkDviI) ? "Single Link DVI-I" : ( - (EngineList->Type.Ddi.DdiData.ConnectorType == ConnectorTypeCrt) ? "CRT" : ( - (EngineList->Type.Ddi.DdiData.ConnectorType == ConnectorTypeAutoDetect) ? "Autodetect" : "Unknown"))))))))))) - ); - ASSERT (EngineList->Type.Ddi.DdiData.ConnectorType < MaxConnectorType); - IDS_HDT_CONSOLE (PCIE_MISC, " Aux - Aux%d\n", EngineList->Type.Ddi.DdiData.AuxIndex + 1); - ASSERT (EngineList->Type.Ddi.DdiData.AuxIndex < MaxAux); - IDS_HDT_CONSOLE (PCIE_MISC, " Hdp - Hdp%d\n", EngineList->Type.Ddi.DdiData.HdpIndex + 1); - ASSERT (EngineList->Type.Ddi.DdiData.HdpIndex < MaxHdp); - } -} - -/*----------------------------------------------------------------------------------------*/ -/** - * Helper function to dump wrapper configuration - * - * - * @param[in] WrapperList Wrapper Configuration - */ -VOID -PcieConfigWrapperDebugDump ( - IN PCIe_WRAPPER_CONFIG *WrapperList - ) -{ - PCIe_ENGINE_CONFIG *EngineList; - IDS_HDT_CONSOLE (PCIE_MISC, " <---------Wrapper - %s Config -------->\n", - PcieFmDebugGetWrapperNameString (WrapperList) - ); - IDS_HDT_CONSOLE (PCIE_MISC, " Descriptor Flags - 0x%08x\n", WrapperList->Header.DescriptorFlags); - IDS_HDT_CONSOLE (PCIE_MISC, " PowerOffUnusedLanes - %x\n PowerOffUnusedPlls - %x\n ClkGating - %x\n" - " LclkGating - %x\n TxclkGatingPllPowerDown - %x\n PllOffInL1 - %x\n", - WrapperList->Features.PowerOffUnusedLanes, - WrapperList->Features.PowerOffUnusedPlls, - WrapperList->Features.ClkGating, - WrapperList->Features.LclkGating, - WrapperList->Features.TxclkGatingPllPowerDown, - WrapperList->Features.PllOffInL1 - ); - IDS_HDT_CONSOLE (PCIE_MISC, " <---------Wrapper - %s Config End----->\n", - PcieFmDebugGetWrapperNameString (WrapperList) - ); - EngineList = PcieConfigGetChildEngine (WrapperList); - while (EngineList != NULL) { - if (PcieLibIsEngineAllocated (EngineList)) { - PcieConfigEngineDebugDump (EngineList); - } - EngineList = PcieLibGetNextDescriptor (EngineList); - } -} - -/*----------------------------------------------------------------------------------------*/ -/** - * Helper function to dump configuration to debug out - * - * - * @param[in] Pcie Pointer to global PCIe configuration - */ -VOID -PcieConfigDebugDump ( - IN PCIe_PLATFORM_CONFIG *Pcie - ) -{ - PCIe_SILICON_CONFIG *SiliconList; - PCIe_WRAPPER_CONFIG *WrapperList; - PCIe_COMPLEX_CONFIG *ComplexList; - ComplexList = (PCIe_COMPLEX_CONFIG *) PcieConfigGetChild (DESCRIPTOR_COMPLEX, &Pcie->Header); - IDS_HDT_CONSOLE (PCIE_MISC, "<-------------- PCIe Config Start------------>\n"); - IDS_HDT_CONSOLE (PCIE_MISC, " PSPP Policy - %s\n", - (Pcie->PsppPolicy == PsppPowerSaving) ? "Power Saving" : - (Pcie->PsppPolicy == PsppBalanceHigh) ? "Balance-High" : ( - (Pcie->PsppPolicy == PsppBalanceLow) ? "Balance-Low" : ( - (Pcie->PsppPolicy == PsppPerformance) ? "Performance" : ( - (Pcie->PsppPolicy == PsppDisabled) ? "Disabled" : "Unknown"))) - ); - IDS_HDT_CONSOLE (PCIE_MISC, " GFX Workaround - %s\n", - (Pcie->GfxCardWorkaround == 0) ? "Disabled" : "Enabled" - ); - IDS_HDT_CONSOLE (PCIE_MISC, " LinkL0Pooling - %dus\n", - Pcie->LinkL0Pooling - ); - IDS_HDT_CONSOLE (PCIE_MISC, " LinkGpioResetAssertionTime - %dus\n", - Pcie->LinkGpioResetAssertionTime - ); - IDS_HDT_CONSOLE (PCIE_MISC, " LinkReceiverDetectionPooling - %dus\n", - Pcie->LinkReceiverDetectionPooling - ); - IDS_HDT_CONSOLE (PCIE_MISC, " Training Algorythm - %s\n", - (Pcie->TrainingAlgorithm == PcieTrainingStandard) ? "PcieTrainingStandard" : ( - (Pcie->TrainingAlgorithm == PcieTrainingDistributed) ? "PcieTrainingDistributed" : "Unknown") - ); - while (ComplexList != NULL) { - IDS_HDT_CONSOLE (PCIE_MISC, " <---------- Complex Config Start ---------->\n"); - IDS_HDT_CONSOLE (PCIE_MISC, " Descriptor Flags - 0x%08x\n", ComplexList->Header.DescriptorFlags); - IDS_HDT_CONSOLE (PCIE_MISC, " Socket ID - %d\n", ComplexList->SocketId); - SiliconList = PcieConfigGetChildSilicon (ComplexList); - while (SiliconList != NULL) { - IDS_HDT_CONSOLE (PCIE_MISC, " <---------- Silicon Config Start -------->\n"); - IDS_HDT_CONSOLE (PCIE_MISC, " Descriptor Flags - 0x%08x\n", SiliconList->Header.DescriptorFlags); - IDS_HDT_CONSOLE (PCIE_MISC, " Silicon ID - %d\n", SiliconList->SiliconId); - IDS_HDT_CONSOLE (PCIE_MISC, " Host PCI Address - %d:%d:%d\n", - SiliconList->Address.Address.Bus, - SiliconList->Address.Address.Device, - SiliconList->Address.Address.Function - ); - WrapperList = PcieConfigGetChildWrapper (SiliconList); - while (WrapperList != NULL) { - PcieConfigWrapperDebugDump (WrapperList); - WrapperList = PcieLibGetNextDescriptor (WrapperList); - } - IDS_HDT_CONSOLE (PCIE_MISC, " <---------- Silicon Config End ---------->\n"); - SiliconList = PcieLibGetNextDescriptor (SiliconList); - } - IDS_HDT_CONSOLE (PCIE_MISC, " <---------- Complex Config End ------------>\n"); - ComplexList = PcieLibGetNextDescriptor (ComplexList); - } - IDS_HDT_CONSOLE (PCIE_MISC, "<-------------- PCIe Config End-------------->\n"); -} - - -/*----------------------------------------------------------------------------------------*/ -/** - * Helper function to dump input configuration to debug out - * - * - * @param[in] ComplexDescriptor Pointer to used define complex descriptor - * @param[in] Pcie Pointer to global PCIe configuration - */ -VOID -PcieUserConfigConfigDump ( - IN PCIe_COMPLEX_DESCRIPTOR *ComplexDescriptor - ) -{ - PCIe_ENGINE_DESCRIPTOR *EngineDescriptor; - PCIe_COMPLEX_DESCRIPTOR *CurrentComplexDescriptor; - UINTN ComplexIndex; - UINTN Index; - UINTN NumberOfEngines; - UINTN NumberOfComplexes; - - IDS_HDT_CONSOLE (PCIE_MISC, "<---------- PCIe User Config Start------------->\n"); - - NumberOfComplexes = PcieInputParserGetNumberOfComplexes (ComplexDescriptor); - for (ComplexIndex = 0; ComplexIndex < NumberOfComplexes; ++ComplexIndex) { - CurrentComplexDescriptor = PcieInputParserGetComplexDescriptor (ComplexDescriptor, ComplexIndex); - NumberOfEngines = PcieInputParserGetNumberOfEngines (CurrentComplexDescriptor); - IDS_HDT_CONSOLE (PCIE_MISC, " ComplexDescriptor SocketId - %d\n NumberOfEngines - %d\n", - ComplexDescriptor->SocketId, - NumberOfEngines - ); - - for (Index = 0; Index < NumberOfEngines; Index++) { - EngineDescriptor = PcieInputParserGetEngineDescriptor (ComplexDescriptor, Index); - IDS_HDT_CONSOLE (PCIE_MISC, " Engine Type - %s\n", - (EngineDescriptor->EngineData.EngineType == PciePortEngine) ? "PCIe Port" : ( - (EngineDescriptor->EngineData.EngineType == PcieDdiEngine) ? "DDI Link" : ( - (EngineDescriptor->EngineData.EngineType == PcieUnusedEngine) ? "Unused" : "Invalid")) - ); - IDS_HDT_CONSOLE (PCIE_MISC, " Start Phy Lane - %d\n End Phy Lane - %d\n", - EngineDescriptor->EngineData.StartLane, - EngineDescriptor->EngineData.EndLane - ); - if (EngineDescriptor->EngineData.EngineType == PciePortEngine) { - IDS_HDT_CONSOLE (PCIE_MISC, " PortPresent - %d\n ChannelType - %d\n DeviceNumber - %d\n FunctionNumber - %d\n LinkSpeedCapability - %d\n LinkAspm - %d\n LinkHotplug - %d\n ResetId - %d\n SB link - %d\n" , - ((PCIe_PORT_DESCRIPTOR *) EngineDescriptor)->Port.PortPresent, - ((PCIe_PORT_DESCRIPTOR *) EngineDescriptor)->Port.ChannelType, - ((PCIe_PORT_DESCRIPTOR *) EngineDescriptor)->Port.DeviceNumber, - ((PCIe_PORT_DESCRIPTOR *) EngineDescriptor)->Port.FunctionNumber, - ((PCIe_PORT_DESCRIPTOR *) EngineDescriptor)->Port.LinkSpeedCapability, - ((PCIe_PORT_DESCRIPTOR *) EngineDescriptor)->Port.LinkAspm, - ((PCIe_PORT_DESCRIPTOR *) EngineDescriptor)->Port.LinkHotplug, - ((PCIe_PORT_DESCRIPTOR *) EngineDescriptor)->Port.ResetId, - ((PCIe_PORT_DESCRIPTOR *) EngineDescriptor)->Port.MiscControls.SbLink - ); - } - if (EngineDescriptor->EngineData.EngineType == PcieDdiEngine) { - IDS_HDT_CONSOLE (PCIE_MISC, " ConnectorType - %d\n AuxIndex - %d\n HdpIndex - %d\n" , - ((PCIe_DDI_DESCRIPTOR *) EngineDescriptor)->Ddi.ConnectorType, - ((PCIe_DDI_DESCRIPTOR *) EngineDescriptor)->Ddi.AuxIndex, - ((PCIe_DDI_DESCRIPTOR *) EngineDescriptor)->Ddi.HdpIndex - ); - } - } - } - IDS_HDT_CONSOLE (PCIE_MISC, "<---------- PCIe User Config End-------------->\n"); -} - diff --git a/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieConfig/PcieConfigLib.h b/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieConfig/PcieConfigLib.h deleted file mode 100644 index 682e336dda..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieConfig/PcieConfigLib.h +++ /dev/null @@ -1,202 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * GNB function to create/locate PCIe configuration data area - * - * Contain code that create/locate and rebase configuration data area. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: GNB - * @e \$Revision: 49532 $ @e \$Date: 2011-03-25 02:54:43 +0800 (Fri, 25 Mar 2011) $ - * - */ -/* -***************************************************************************** -* -* Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* *************************************************************************** -* -*/ - -#ifndef _PCIECONFIGLIB_H_ -#define _PCIECONFIGLIB_H_ - -typedef VOID (*PCIe_RUN_ON_ENGINE_CALLBACK) ( - IN PCIe_ENGINE_CONFIG *Engine, - IN OUT VOID *Buffer, - IN PCIe_PLATFORM_CONFIG *Pcie - ); - -typedef AGESA_STATUS (*PCIe_RUN_ON_WRAPPER_CALLBACK) ( - IN PCIe_WRAPPER_CONFIG *Wrapper, - IN OUT VOID *Buffer, - IN PCIe_PLATFORM_CONFIG *Pcie - ); - -typedef AGESA_STATUS (*PCIe_RUN_ON_DESCRIPTOR_CALLBACK) ( - IN PCIe_DESCRIPTOR_HEADER *Descriptor, - IN OUT VOID *Buffer, - IN PCIe_PLATFORM_CONFIG *Pcie - ); - -UINT8 -PcieConfigGetPcieEngineMasterLane ( - IN PCIe_ENGINE_CONFIG *Engine - ); - -UINT8 -PcieConfigGetNumberOfCoreLane ( - IN PCIe_ENGINE_CONFIG *Engine - ); - -VOID -PcieConfigDisableAllEngines ( - IN UINTN EngineTypeMask, - IN PCIe_WRAPPER_CONFIG *Wrapper - ); - -VOID -PcieConfigDisableEngine ( - IN PCIe_ENGINE_CONFIG *Engine - ); - -UINT32 -PcieConfigGetEnginePhyLaneBitMap ( - IN PCIe_ENGINE_CONFIG *Engine - ); - -UINT8 -PcieConfigGetNumberOfPhyLane ( - IN PCIe_ENGINE_CONFIG *Engine - ); - -UINT64 -PcieConfigGetConfigurationSignature ( - IN PCIe_WRAPPER_CONFIG *Wrapper, - IN UINT8 CoreId - ); - -BOOLEAN -PcieConfigCheckPortStatus ( - IN PCIe_ENGINE_CONFIG *Engine, - IN UINT32 PortStatus - ); - -UINT32 -PcieConfigUpdatePortStatus ( - IN PCIe_ENGINE_CONFIG *Engine, - IN UINT32 SetStatus, - IN UINT32 ResetStatus - ); - -VOID -PcieConfigRunProcForAllEngines ( - IN UINT32 DescriptorFlags, - IN PCIe_RUN_ON_ENGINE_CALLBACK Callback, - IN OUT VOID *Buffer, - IN PCIe_PLATFORM_CONFIG *Pcie - ); - -AGESA_STATUS -PcieConfigRunProcForAllWrappers ( - IN UINT32 DescriptorFlags, - IN PCIe_RUN_ON_WRAPPER_CALLBACK Callback, - IN OUT VOID *Buffer, - IN PCIe_PLATFORM_CONFIG *Pcie - ); - -AGESA_STATUS -PcieConfigRunProcForAllDescriptors ( - IN UINT32 InDescriptorFlags, - IN UINT32 OutDescriptorFlags, - IN UINT32 TerminationFlags, - IN PCIe_RUN_ON_DESCRIPTOR_CALLBACK Callback, - IN OUT VOID *Buffer, - IN PCIe_PLATFORM_CONFIG *Pcie - ); - -PCIe_DESCRIPTOR_HEADER * -PcieConfigGetParent ( - IN UINT32 Type, - IN PCIe_DESCRIPTOR_HEADER *Descriptor - ); - -PCIe_DESCRIPTOR_HEADER * -PcieConfigGetChild ( - IN UINT32 Type, - IN PCIe_DESCRIPTOR_HEADER *Descriptor - ); - -PCIe_DESCRIPTOR_HEADER * -PcieConfigGetPeer ( - IN UINT32 Type, - IN PCIe_DESCRIPTOR_HEADER *Descriptor - ); - -VOID -PcieConfigDebugDump ( - IN PCIe_PLATFORM_CONFIG *Pcie - ); - -VOID -PcieConfigWrapperDebugDump ( - IN PCIe_WRAPPER_CONFIG *WrapperList - ); - -VOID -PcieConfigEngineDebugDump ( - IN PCIe_ENGINE_CONFIG *EngineList - ); - -VOID -PcieUserConfigConfigDump ( - IN PCIe_COMPLEX_DESCRIPTOR *ComplexDescriptor - ); - -#define PcieConfigGetParentWrapper(Descriptor) ((PCIe_WRAPPER_CONFIG *) PcieConfigGetParent (DESCRIPTOR_ALL_WRAPPERS, &((Descriptor)->Header))) -#define PcieConfigGetParentSilicon(Descriptor) ((PCIe_SILICON_CONFIG *) PcieConfigGetParent (DESCRIPTOR_SILICON, &((Descriptor)->Header))) -#define PcieConfigGetParentComplex(Descriptor) ((PCIe_COMPLEX_CONFIG *) PcieConfigGetParent (DESCRIPTOR_COMPLEX, &((Descriptor)->Header))) -#define PcieConfigGetPlatform(Descriptor) ((PCIe_PLATFORM_CONFIG *) PcieConfigGetParent (DESCRIPTOR_PLATFORM, &((Descriptor)->Header))) -#define PcieConfigGetChildWrapper(Descriptor) ((PCIe_WRAPPER_CONFIG *) PcieConfigGetChild (DESCRIPTOR_ALL_WRAPPERS, &((Descriptor)->Header))) -#define PcieConfigGetChildEngine(Descriptor) ((PCIe_ENGINE_CONFIG *) PcieConfigGetChild (DESCRIPTOR_ALL_ENGINES, &((Descriptor)->Header))) -#define PcieConfigGetChildSilicon(Descriptor) ((PCIe_SILICON_CONFIG *) PcieConfigGetChild (DESCRIPTOR_SILICON, &((Descriptor)->Header))) -#define PcieConfigGetNextDescriptor(Descriptor) (Descriptor != NULL ? ((((Descriptor->Header.DescriptorFlags & DESCRIPTOR_TERMINATE_LIST) != 0) ? NULL : (Descriptor+1))) : NULL) -#define PcieConfigIsPcieEngine(Descriptor) (Descriptor != NULL ? ((Descriptor->Header.DescriptorFlags & DESCRIPTOR_PCIE_ENGINE) != 0) : (1==0)) -#define PcieConfigIsDdiEngine(Descriptor) (Descriptor != NULL ? ((Descriptor->Header.DescriptorFlags & DESCRIPTOR_DDI_ENGINE) != 0) : (1==0)) -#define PcieConfigIsPcieWrapper(Descriptor) (Descriptor != NULL ? ((Descriptor->Header.DescriptorFlags & DESCRIPTOR_PCIE_WRAPPER) != 0) : (1==0)) -#define PcieConfigIsSbPcieEngine(Engine) ((BOOLEAN) (Engine->Type.Port.PortData.MiscControls.SbLink)) -#define PcieConfigIsDdiWrapper(Descriptor) (Descriptor != NULL ? ((Descriptor->Header.DescriptorFlags & DESCRIPTOR_DDI_WRAPPER) != 0) : (1==0)) -#define PcieConfigIsEngineAllocated(Descriptor) (Descriptor != NULL ? ((Descriptor->Header.DescriptorFlags & DESCRIPTOR_ALLOCATED) != 0) : (1==0)) -#define PcieConfigIsVirtualDesciptor(Descriptor) (Descriptor != NULL ? ((Descriptor->Header.DescriptorFlags & DESCRIPTOR_VIRTUAL) != 0) : (1==0)) -#define PcieConfigSetDescriptorFlags(Descriptor, SetDescriptorFlags) (Descriptor)->Header.DescriptorFlags |= SetDescriptorFlags -#define PcieConfigResetDescriptorFlags(Descriptor, ResetDescriptorFlags) ((PCIe_DESCRIPTOR_HEADER *) Descriptor)->DescriptorFlags &= (~(ResetDescriptorFlags)) -#define PcieInputParsetGetNextDescriptor(Descriptor) (Descriptor != NULL ? ((((Descriptor->Flags & DESCRIPTOR_TERMINATE_LIST) != 0) ? NULL : (Descriptor+1))) : NULL) -#define PcieConfigGetNextTopologyDescriptor(Descriptor, Termination) (((((PCIe_DESCRIPTOR_HEADER *) Descriptor)->DescriptorFlags & Termination) != 0) ? NULL : ((UINT8 *) Descriptor + ((PCIe_DESCRIPTOR_HEADER *) Descriptor)->Peer)) - -#endif - diff --git a/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieConfig/PcieInputParser.c b/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieConfig/PcieInputParser.c deleted file mode 100644 index 5398ca1041..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieConfig/PcieInputParser.c +++ /dev/null @@ -1,256 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * Procedure to parse PCIe input configuration data - * - * - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: GNB - * @e \$Revision: 49532 $ @e \$Date: 2011-03-25 02:54:43 +0800 (Fri, 25 Mar 2011) $ - * - */ -/* -***************************************************************************** -* -* Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* *************************************************************************** -* -*/ - -/*---------------------------------------------------------------------------------------- - * M O D U L E S U S E D - *---------------------------------------------------------------------------------------- - */ -#include "AGESA.h" -#include "Ids.h" -#include "Gnb.h" -#include "GnbPcie.h" -#include "PcieConfigLib.h" -#include "PcieInputParser.h" -#include "Filecode.h" -#define FILECODE PROC_GNB_MODULES_GNBPCIECONFIG_PCIEINPUTPARSER_FILECODE -/*---------------------------------------------------------------------------------------- - * D E F I N I T I O N S A N D M A C R O S - *---------------------------------------------------------------------------------------- - */ - - -/*---------------------------------------------------------------------------------------- - * T Y P E D E F S A N D S T R U C T U R E S - *---------------------------------------------------------------------------------------- - */ - - -/*---------------------------------------------------------------------------------------- - * P R O T O T Y P E S O F L O C A L F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ -UINTN -PcieInputParserGetLengthOfDdiEnginesList ( - IN CONST PCIe_COMPLEX_DESCRIPTOR *Complex - ); - -/*----------------------------------------------------------------------------------------*/ -/** - * Get number of complexes in platform topology configuration - * - * - * - * @param[in] ComplexList First complex configuration in complex configuration array - * @retval Number of Complexes - * - */ -UINTN -PcieInputParserGetNumberOfComplexes ( - IN CONST PCIe_COMPLEX_DESCRIPTOR *ComplexList - ) -{ - UINTN Result; - Result = 0; - if (ComplexList != NULL) { - while (ComplexList != NULL) { - Result++; - ComplexList = PcieInputParsetGetNextDescriptor (ComplexList); - } - } - return Result; -} - -/*----------------------------------------------------------------------------------------*/ -/** - * Get number of PCIe engines in given complex - * - * - * - * @param[in] Complex Complex configuration - * @retval Number of Engines - */ -UINTN -PcieInputParserGetLengthOfPcieEnginesList ( - IN CONST PCIe_COMPLEX_DESCRIPTOR *Complex - ) -{ - UINTN Result; - CONST PCIe_PORT_DESCRIPTOR *PciePortList; - Result = 0; - if (Complex != NULL) { - PciePortList = Complex->PciePortList; - while (PciePortList != NULL) { - Result++; - PciePortList = PcieInputParsetGetNextDescriptor (PciePortList); - } - } - return Result; -} - -/*----------------------------------------------------------------------------------------*/ -/** - * Get number of DDI engines in given complex - * - * - * - * @param[in] Complex Complex configuration - * @retval Number of Engines - */ -UINTN -PcieInputParserGetLengthOfDdiEnginesList ( - IN CONST PCIe_COMPLEX_DESCRIPTOR *Complex - ) -{ - UINTN Result; - CONST PCIe_DDI_DESCRIPTOR *DdiLinkList; - Result = 0; - if (Complex != NULL) { - DdiLinkList = Complex->DdiLinkList; - while (DdiLinkList != NULL) { - Result++; - DdiLinkList = PcieInputParsetGetNextDescriptor (DdiLinkList); - } - } - return Result; -} - - -/*----------------------------------------------------------------------------------------*/ -/** - * Get number of engines in given complex - * - * - * - * @param[in] Complex Complex configuration header - * @retval Number of Engines - */ -UINTN -PcieInputParserGetNumberOfEngines ( - IN CONST PCIe_COMPLEX_DESCRIPTOR *Complex - ) -{ - UINTN Result; - - Result = PcieInputParserGetLengthOfDdiEnginesList (Complex) + - PcieInputParserGetLengthOfPcieEnginesList (Complex); - return Result; -} - - -/*----------------------------------------------------------------------------------------*/ -/** - * Get Complex descriptor by index from given Platform configuration - * - * - * - * @param[in] ComplexList Platform topology configuration - * @param[in] Index Complex descriptor Index - * @retval Pointer to Complex Descriptor - */ -PCIe_COMPLEX_DESCRIPTOR* -PcieInputParserGetComplexDescriptor ( - IN PCIe_COMPLEX_DESCRIPTOR *ComplexList, - IN UINTN Index - ) -{ - ASSERT (Index < (PcieInputParserGetNumberOfComplexes (ComplexList))); - return &ComplexList[Index]; -} - -/*----------------------------------------------------------------------------------------*/ -/** - * Get Complex descriptor by index from given Platform configuration - * - * - * - * @param[in] ComplexList Platform topology configuration - * @param[in] Index Complex descriptor Index - * @retval Pointer to Complex Descriptor - */ -PCIe_COMPLEX_DESCRIPTOR* -PcieInputParserGetComplexDescriptorOfSocket ( - IN PCIe_COMPLEX_DESCRIPTOR *ComplexList, - IN UINT32 SocketId - ) -{ - PCIe_COMPLEX_DESCRIPTOR *Result; - Result = NULL; - while (ComplexList != NULL) { - if (ComplexList->SocketId == SocketId ) { - Result = ComplexList; - break; - } - ComplexList = PcieInputParsetGetNextDescriptor (ComplexList); - } - return Result; -} - - -/*----------------------------------------------------------------------------------------*/ -/** - * Get Engine descriptor from given complex by index - * - * - * - * @param[in] Complex Complex descriptor - * @param[in] Index Engine descriptor index - * @retval Pointer to Engine Descriptor - */ -PCIe_ENGINE_DESCRIPTOR* -PcieInputParserGetEngineDescriptor ( - IN PCIe_COMPLEX_DESCRIPTOR *Complex, - IN UINTN Index - ) -{ - UINTN PcieListlength; - ASSERT (Index < (PcieInputParserGetNumberOfEngines (Complex))); - PcieListlength = PcieInputParserGetLengthOfPcieEnginesList (Complex); - if (Index < PcieListlength) { - return (PCIe_ENGINE_DESCRIPTOR*) &((Complex->PciePortList)[Index]); - } else { - return (PCIe_ENGINE_DESCRIPTOR*) &((Complex->DdiLinkList)[Index - PcieListlength]); - } -} - diff --git a/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieConfig/PcieInputParser.h b/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieConfig/PcieInputParser.h deleted file mode 100644 index ed2e33ac69..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieConfig/PcieInputParser.h +++ /dev/null @@ -1,83 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * Procedure to parse PCIe input configuration data - * - * - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: GNB - * @e \$Revision: 49532 $ @e \$Date: 2011-03-25 02:54:43 +0800 (Fri, 25 Mar 2011) $ - * - */ -/* -***************************************************************************** -* -* Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* *************************************************************************** -* -*/ -#ifndef _PCIEINPUTPARSER_H_ -#define _PCIEINPUTPARSER_H_ - - -UINTN -PcieInputParserGetNumberOfComplexes ( - IN CONST PCIe_COMPLEX_DESCRIPTOR *ComplexList - ); - -UINTN -PcieInputParserGetNumberOfEngines ( - IN CONST PCIe_COMPLEX_DESCRIPTOR *Complex - ); - - -PCIe_COMPLEX_DESCRIPTOR* -PcieInputParserGetComplexDescriptor ( - IN PCIe_COMPLEX_DESCRIPTOR *ComplexList, - IN UINTN Index - ); - -PCIe_ENGINE_DESCRIPTOR* -PcieInputParserGetEngineDescriptor ( - IN PCIe_COMPLEX_DESCRIPTOR *Complex, - IN UINTN Index - ); - -PCIe_COMPLEX_DESCRIPTOR* -PcieInputParserGetComplexDescriptorOfSocket ( - IN PCIe_COMPLEX_DESCRIPTOR *ComplexList, - IN UINT32 SocketId - ); - -UINTN -PcieInputParserGetLengthOfPcieEnginesList ( - IN CONST PCIe_COMPLEX_DESCRIPTOR *Complex - ); -#endif - diff --git a/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieConfig/PcieMapTopology.c b/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieConfig/PcieMapTopology.c deleted file mode 100644 index 1c103f7ce1..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieConfig/PcieMapTopology.c +++ /dev/null @@ -1,658 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * Procedure to map user define topology to processor configuration - * - * - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: GNB - * @e \$Revision: 49532 $ @e \$Date: 2011-03-25 02:54:43 +0800 (Fri, 25 Mar 2011) $ - * - */ -/* -***************************************************************************** -* -* Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* *************************************************************************** -* -*/ - -/*---------------------------------------------------------------------------------------- - * M O D U L E S U S E D - *---------------------------------------------------------------------------------------- - */ -#include "AGESA.h" -#include "Ids.h" -#include "amdlib.h" -#include "Gnb.h" -#include "GnbPcie.h" -#include "GnbPcieFamServices.h" -#include "GeneralServices.h" -#include "PcieInputParser.h" -#include "PcieMapTopology.h" -#include "GnbPcieConfig.h" -#include "Filecode.h" -#define FILECODE PROC_GNB_MODULES_GNBPCIECONFIG_PCIEMAPTOPOLOGY_FILECODE -/*---------------------------------------------------------------------------------------- - * D E F I N I T I O N S A N D M A C R O S - *---------------------------------------------------------------------------------------- - */ - - -/*---------------------------------------------------------------------------------------- - * T Y P E D E F S A N D S T R U C T U R E S - *---------------------------------------------------------------------------------------- - */ - - -/*---------------------------------------------------------------------------------------- - * P R O T O T Y P E S O F L O C A L F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ - - -AGESA_STATUS -STATIC -PcieMapPortsPciAddresses ( - IN PCIe_SILICON_CONFIG *Silicon, - IN PCIe_PLATFORM_CONFIG *Pcie - ); - -AGESA_STATUS -PcieMapTopologyOnWrapper ( - IN PCIe_COMPLEX_DESCRIPTOR *ComplexDescriptor, - IN OUT PCIe_WRAPPER_CONFIG *Wrapper, - IN PCIe_PLATFORM_CONFIG *Pcie - ); - -VOID -PcieMapInitializeEngineData ( - IN PCIe_COMPLEX_DESCRIPTOR *ComplexDescriptor, - IN OUT PCIe_WRAPPER_CONFIG *Wrapper, - IN PCIe_PLATFORM_CONFIG *Pcie - ); - -BOOLEAN -PcieCheckPortPciDeviceMapping ( - IN PCIe_PORT_DESCRIPTOR *PortDescriptor, - IN PCIe_ENGINE_CONFIG *Engine - ); - -VOID -PcieComplexConfigConfigDump ( - IN PCIe_COMPLEX_DESCRIPTOR *ComplexDescriptor, - IN PCIe_PLATFORM_CONFIG *Pcie - ); - -BOOLEAN -PcieIsDescriptorLinkWidthValid ( - IN PCIe_ENGINE_DESCRIPTOR *EngineDescriptor - ); - -BOOLEAN -PcieCheckLanesMatch ( - IN PCIe_ENGINE_DESCRIPTOR *EngineDescriptor, - IN PCIe_ENGINE_CONFIG *Engine - ); - -AGESA_STATUS -PcieEnginesToWrapper ( - IN PCIE_ENGINE_TYPE EngineType, - IN PCIe_COMPLEX_DESCRIPTOR *ComplexDescriptor, - IN PCIe_WRAPPER_CONFIG *Wrapper - ); - -BOOLEAN -PcieCheckDescriptorMapsToWrapper ( - IN PCIe_ENGINE_DESCRIPTOR *EngineDescriptor, - IN PCIe_WRAPPER_CONFIG *Wrapper - ); - -VOID -PcieAllocateEngine ( - IN UINT8 DescriptorIndex, - IN PCIe_ENGINE_CONFIG *Engine - ); -/*----------------------------------------------------------------------------------------*/ -/** - * Configure engine list to support lane allocation according to configuration ID. - * - * - * - * @param[in] ComplexDescriptor Pointer to used define complex descriptor - * @param[in] Complex Pointer to complex descriptor - * @param[in] Pcie Pointer to global PCIe configuration - * @retval AGESA_SUCCESS Topology successfully mapped - * @retval AGESA_ERROR Topology can not be mapped - */ - -AGESA_STATUS -PcieMapTopologyOnComplex ( - IN PCIe_COMPLEX_DESCRIPTOR *ComplexDescriptor, - IN PCIe_COMPLEX_CONFIG *Complex, - IN PCIe_PLATFORM_CONFIG *Pcie - ) -{ - PCIe_SILICON_CONFIG *Silicon; - PCIe_WRAPPER_CONFIG *Wrapper; - AGESA_STATUS AgesaStatus; - AGESA_STATUS Status; - - AgesaStatus = AGESA_SUCCESS; - IDS_HDT_CONSOLE (GNB_TRACE, "PcieMapTopologyOnComplex Enter\n"); - Silicon = PcieConfigGetChildSilicon (Complex); - while (Silicon != NULL) { - Wrapper = PcieConfigGetChildWrapper (Silicon); - while (Wrapper != NULL) { - Status = PcieMapTopologyOnWrapper (ComplexDescriptor, Wrapper, Pcie); - AGESA_STATUS_UPDATE (Status, AgesaStatus); - if (Status == AGESA_ERROR) { - PcieConfigDisableAllEngines (PciePortEngine | PcieDdiEngine, Wrapper); - IDS_HDT_CONSOLE (PCIE_MISC, " ERROR! Fail to map topology on %s Wrapper\n", - PcieFmDebugGetWrapperNameString (Wrapper) - ); - ASSERT (FALSE); - } - Wrapper = PcieLibGetNextDescriptor (Wrapper); - } - Status = PcieMapPortsPciAddresses (Silicon, Pcie); - AGESA_STATUS_UPDATE (Status, AgesaStatus); - Silicon = PcieLibGetNextDescriptor (Silicon); - } - IDS_HDT_CONSOLE (GNB_TRACE, "PcieMapTopologyOnComplex Exit [%x]\n", AgesaStatus); - return AgesaStatus; -} - -/*----------------------------------------------------------------------------------------*/ -/** - * Configure engine list to support lane allocation according to configuration ID. - * - * - * - * @param[in] EngineType Engine type - * @param[in] ComplexDescriptor Pointer to used define complex descriptor - * @param[in] Wrapper Pointer to wrapper config descriptor - * @retval AGESA_SUCCESS Topology successfully mapped - * @retval AGESA_ERROR Topology can not be mapped - */ -AGESA_STATUS -PcieEnginesToWrapper ( - IN PCIE_ENGINE_TYPE EngineType, - IN PCIe_COMPLEX_DESCRIPTOR *ComplexDescriptor, - IN PCIe_WRAPPER_CONFIG *Wrapper - ) -{ - AGESA_STATUS Status; - PCIe_ENGINE_CONFIG *EngineList; - PCIe_ENGINE_DESCRIPTOR *EngineDescriptor; - UINT8 ConfigurationId; - UINT8 Allocations; - UINTN Index; - UINTN NumberOfDescriptors; - - ConfigurationId = 0; - Allocations = 0; - IDS_HDT_CONSOLE (GNB_TRACE, "PcieEnginesToWrapper Enter\n"); - NumberOfDescriptors = PcieInputParserGetNumberOfEngines (ComplexDescriptor); - do { - Status = PcieFmConfigureEnginesLaneAllocation (Wrapper, EngineType, ConfigurationId++); - - if (Status == AGESA_SUCCESS) { - Allocations = 0; - for (Index = 0; Index < NumberOfDescriptors; Index++) { - EngineDescriptor = PcieInputParserGetEngineDescriptor (ComplexDescriptor, Index); - if (EngineDescriptor->EngineData.EngineType == EngineType) { - // Step 1, belongs to wrapper check. - if (PcieCheckDescriptorMapsToWrapper (EngineDescriptor, Wrapper)) { - ++Allocations; - EngineList = PcieConfigGetChildEngine (Wrapper); - while (EngineList != NULL) { - if (!PcieLibIsEngineAllocated (EngineList)) { - // Step 2.user descriptor less or equal to link width of engine - if (PcieCheckLanesMatch (EngineDescriptor, EngineList)) { - // Step 3, Check if link width is correct.x1, x2, x4, x8, x16. - if (!PcieIsDescriptorLinkWidthValid (EngineDescriptor)) { - PcieConfigDisableEngine (EngineList); - return AGESA_ERROR; - } - if (EngineDescriptor->EngineData.EngineType == PciePortEngine) { - // Step 4, Family specifc, port device number match engine device - if (PcieCheckPortPciDeviceMapping ((PCIe_PORT_DESCRIPTOR*) EngineDescriptor, EngineList)) { - //Step 5, Family specifc, lanes can be muxed. - if (PcieFmCheckPortPcieLaneCanBeMuxed ((PCIe_PORT_DESCRIPTOR*) EngineDescriptor, EngineList)) { - PcieAllocateEngine ((UINT8) Index, EngineList); - --Allocations; - break; - } - } - } else { - PcieAllocateEngine ((UINT8) Index, EngineList); - --Allocations; - break; - } - } - }//end if PcieLibIsEngineAllocated - EngineList = PcieLibGetNextDescriptor (EngineList); - } - }//end if PcieCheckDescriptorMapsToWrapper - }// end if EngineType - }//end for - } - } while (Status == AGESA_SUCCESS && Allocations != 0); - IDS_HDT_CONSOLE (GNB_TRACE, "PcieEnginesToWrapper Exit [%x]\n", Status); - return Status; -} - -/*----------------------------------------------------------------------------------------*/ -/** - * Check if lane from user port descriptor (PCIe_PORT_DESCRIPTOR) belongs to wrapper (PCIe_WRAPPER_CONFIG) - * - * - * @param[in] EngineDescriptor Pointer to used define engine descriptor - * @param[in] Wrapper Pointer to PCIe_WRAPPER_CONFIG - * @retval TRUE Belongs to wrapper - * @retval FALSE Not belongs to wrapper - */ -BOOLEAN -PcieCheckDescriptorMapsToWrapper ( - IN PCIe_ENGINE_DESCRIPTOR *EngineDescriptor, - IN PCIe_WRAPPER_CONFIG *Wrapper - ) -{ - BOOLEAN Result; - UINT16 DescriptorHiLane; - UINT16 DescriptorLoLane; - UINT16 DescriptorNumberOfLanes; - - DescriptorLoLane = MIN (EngineDescriptor->EngineData.StartLane, EngineDescriptor->EngineData.EndLane); - DescriptorHiLane = MAX (EngineDescriptor->EngineData.StartLane, EngineDescriptor->EngineData.EndLane); - DescriptorNumberOfLanes = DescriptorHiLane - DescriptorLoLane + 1; - Result = TRUE; - - if (!(DescriptorLoLane >= Wrapper->StartPhyLane && DescriptorHiLane <= Wrapper->EndPhyLane)) { - // Lanes of descriptor does not belongs to wrapper - Result = FALSE; - } - return Result; -} - -/*----------------------------------------------------------------------------------------*/ -/** - * Set Engine to be allocated. - * - * - * @param[in] DescriptorIndex UINT8 index - * @param[in] Engine Pointer to engine config - */ -VOID -PcieAllocateEngine ( - IN UINT8 DescriptorIndex, - IN PCIe_ENGINE_CONFIG *Engine - ) -{ - PcieConfigSetDescriptorFlags (Engine, DESCRIPTOR_ALLOCATED); - Engine->Scratch = DescriptorIndex; -} - -/*----------------------------------------------------------------------------------------*/ -/** - * Configure engine list to support lane allocation according to configuration ID. - * - * PCIE port - * - * - * 1 Check if lane from user port descriptor (PCIe_PORT_DESCRIPTOR) belongs to wrapper (PCIe_WRAPPER_CONFIG) - * 2 Check if link width from user descriptor less or equal to link width of engine (PCIe_ENGINE_CONFIG) - * 3 Check if link width is correct. Correct link width for PCIe port x1, x2, x4, x8, x16, correct link width for DDI x4, x8 - * 4 Check if user port device number (PCIe_PORT_DESCRIPTOR) match engine port device number (PCIe_ENGINE_CONFIG) - * 5 Check if lane can be muxed - * - * - * DDI Link - * - * 1 Check if lane from user port descriptor (PCIe_DDI_DESCRIPTOR) belongs to wrapper (PCIe_WRAPPER_CONFIG) - * 2 Check lane from (PCIe_DDI_DESCRIPTOR) match exactly phy lane (PCIe_ENGINE_CONFIG) - * - * - * - * @param[in] ComplexDescriptor Pointer to used define complex descriptor - * @param[in,out] Wrapper Pointer to wrapper config descriptor - * @param[in] Pcie Pointer to global PCIe configuration - * @retval AGESA_SUCCESS Topology successfully mapped - * @retval AGESA_ERROR Topology can not be mapped - */ -AGESA_STATUS -PcieMapTopologyOnWrapper ( - IN PCIe_COMPLEX_DESCRIPTOR *ComplexDescriptor, - IN OUT PCIe_WRAPPER_CONFIG *Wrapper, - IN PCIe_PLATFORM_CONFIG *Pcie - ) -{ - AGESA_STATUS AgesaStatus; - AGESA_STATUS Status; - PCIe_ENGINE_CONFIG *EngineList; - UINT32 WrapperPhyLaneBitMap; - - AgesaStatus = AGESA_SUCCESS; - if (PcieLibIsPcieWrapper (Wrapper)) { - Status = PcieEnginesToWrapper (PciePortEngine, ComplexDescriptor, Wrapper); - AGESA_STATUS_UPDATE (Status, AgesaStatus); - if (Status == AGESA_ERROR) { - // If we can not map topology on wrapper we can not enable any engines. - PutEventLog ( - AGESA_ERROR, - GNB_EVENT_INVALID_PCIE_TOPOLOGY_CONFIGURATION, - Wrapper->WrapId, - Wrapper->StartPhyLane, - Wrapper->EndPhyLane, - 0, - GnbLibGetHeader (Pcie) - ); - PcieConfigDisableAllEngines (PciePortEngine, Wrapper); - } - } - if (PcieLibIsDdiWrapper (Wrapper)) { - Status = PcieEnginesToWrapper (PcieDdiEngine, ComplexDescriptor, Wrapper); - AGESA_STATUS_UPDATE (Status, AgesaStatus); - if (Status == AGESA_ERROR) { - // If we can not map topology on wrapper we can not enable any engines. - PutEventLog ( - AGESA_ERROR, - GNB_EVENT_INVALID_DDI_TOPOLOGY_CONFIGURATION, - Wrapper->WrapId, - Wrapper->StartPhyLane, - Wrapper->EndPhyLane, - 0, - GnbLibGetHeader (Pcie) - ); - PcieConfigDisableAllEngines (PcieDdiEngine, Wrapper); - } - } - // Copy engine data - PcieMapInitializeEngineData (ComplexDescriptor, Wrapper, Pcie); - - EngineList = PcieConfigGetChildEngine (Wrapper); - // Verify if we oversubscribe lanes and PHY link width - WrapperPhyLaneBitMap = 0; - while (EngineList != NULL) { - UINT32 EnginePhyLaneBitMap; - if (PcieLibIsEngineAllocated (EngineList)) { - EnginePhyLaneBitMap = PcieConfigGetEnginePhyLaneBitMap (EngineList); - if ((WrapperPhyLaneBitMap & EnginePhyLaneBitMap) != 0) { - IDS_HDT_CONSOLE (PCIE_MISC, " ERROR! Lanes double subscribe lanes [Engine Lanes %d..%d]\n", - EngineList->EngineData.StartLane, - EngineList->EngineData.EndLane - ); - PutEventLog ( - AGESA_ERROR, - GNB_EVENT_INVALID_LANES_CONFIGURATION, - EngineList->EngineData.StartLane, - EngineList->EngineData.EndLane, - 0, - 0, - GnbLibGetHeader (Pcie) - ); - PcieConfigDisableEngine (EngineList); - Status = AGESA_ERROR; - AGESA_STATUS_UPDATE (Status, AgesaStatus); - } else { - WrapperPhyLaneBitMap |= EnginePhyLaneBitMap; - } - } - EngineList = PcieLibGetNextDescriptor (EngineList); - } - return AgesaStatus; -} - - -/*----------------------------------------------------------------------------------------*/ -/** - * Initialize engine data - * - * - * - * @param[in] ComplexDescriptor Pointer to user defined complex descriptor - * @param[in,out] Wrapper Pointer to wrapper config descriptor - * @param[in] Pcie Pointer to global PCIe configuration - */ -VOID -PcieMapInitializeEngineData ( - IN PCIe_COMPLEX_DESCRIPTOR *ComplexDescriptor, - IN OUT PCIe_WRAPPER_CONFIG *Wrapper, - IN PCIe_PLATFORM_CONFIG *Pcie - ) -{ - PCIe_ENGINE_CONFIG *EngineList; - PCIe_ENGINE_DESCRIPTOR *EngineDescriptor; - - EngineList = PcieConfigGetChildEngine (Wrapper); - while (EngineList != NULL) { - if (PcieLibIsEngineAllocated (EngineList)) { - if (EngineList->Scratch != 0xFF) { - EngineDescriptor = PcieInputParserGetEngineDescriptor (ComplexDescriptor, EngineList->Scratch); - LibAmdMemCopy (&EngineList->EngineData, &EngineDescriptor->EngineData, sizeof (EngineDescriptor->EngineData), GnbLibGetHeader (Pcie)); - if (PcieLibIsDdiEngine (EngineList)) { - LibAmdMemCopy (&EngineList->Type.Ddi, &((PCIe_DDI_DESCRIPTOR*) EngineDescriptor)->Ddi, sizeof (PCIe_DDI_DATA), GnbLibGetHeader (Pcie)); - EngineList->Type.Ddi.DisplayPriorityIndex = (UINT8) EngineList->Scratch; - } else if (PcieLibIsPcieEngine (EngineList)) { - LibAmdMemCopy (&EngineList->Type.Port, &((PCIe_PORT_DESCRIPTOR*) EngineDescriptor)->Port, sizeof (PCIe_PORT_DATA), GnbLibGetHeader (Pcie)); - } - } - } - EngineList = PcieLibGetNextDescriptor (EngineList); - } -} - -/*----------------------------------------------------------------------------------------*/ -/** - * Allocate PCI addresses for all PCIe engines on silicon - * - * - * - * @param[in] PortDescriptor Pointer to user defined engine descriptor - * @param[in] Engine Pointer engine configuration - * @retval TRUE Descriptor can be mapped to engine - * @retval FALSE Descriptor can NOT be mapped to engine - */ - -BOOLEAN -PcieCheckPortPciDeviceMapping ( - IN PCIe_PORT_DESCRIPTOR *PortDescriptor, - IN PCIe_ENGINE_CONFIG *Engine - ) -{ - BOOLEAN Result; - - if ((PortDescriptor->Port.DeviceNumber == Engine->Type.Port.NativeDevNumber && - PortDescriptor->Port.FunctionNumber == Engine->Type.Port.NativeFunNumber) || - (PortDescriptor->Port.DeviceNumber == 0 && PortDescriptor->Port.FunctionNumber == 0)) { - Result = TRUE; - } else { - Result = PcieFmCheckPortPciDeviceMapping (PortDescriptor, Engine); - } - - return Result; -} - -/*----------------------------------------------------------------------------------------*/ -/** - * Allocate PCI addresses for all PCIe engines on silicon - * - * - * - * @param[in] Silicon Pointer to silicon configurration - * @param[in] Pcie Pointer PCIe configuration - * @retval AGESA_ERROR Fail to allocate PCI device address - * @retval AGESA_SUCCESS Successfully allocate PCI address for all PCIe ports - */ - -AGESA_STATUS -STATIC -PcieMapPortsPciAddresses ( - IN PCIe_SILICON_CONFIG *Silicon, - IN PCIe_PLATFORM_CONFIG *Pcie - ) -{ - AGESA_STATUS Status; - AGESA_STATUS AgesaStatus; - PCIe_WRAPPER_CONFIG *WrapperList; - PCIe_ENGINE_CONFIG *EngineList; - AgesaStatus = AGESA_SUCCESS; - WrapperList = PcieConfigGetChildWrapper (Silicon); - while (WrapperList != NULL) { - EngineList = PcieConfigGetChildEngine (WrapperList); - while (EngineList != NULL) { - if (PcieLibIsPcieEngine (EngineList) && PcieLibIsEngineAllocated (EngineList)) { - Status = PcieFmMapPortPciAddress (EngineList); - AGESA_STATUS_UPDATE (Status, AgesaStatus); - if (Status == AGESA_SUCCESS) { - EngineList->Type.Port.Address.AddressValue = MAKE_SBDFO ( - 0, - Silicon->Address.Address.Bus, - EngineList->Type.Port.PortData.DeviceNumber, - EngineList->Type.Port.PortData.FunctionNumber, - 0 - ); - } else { - EngineList->Type.Port.PortData.PortPresent = OFF; - IDS_HDT_CONSOLE (PCIE_MISC, " ERROR! Fail to allocate PCI address for PCIe port\n" - ); - //Report error - PutEventLog ( - AGESA_ERROR, - GNB_EVENT_INVALID_PCIE_PORT_CONFIGURATION, - EngineList->Type.Port.PortData.DeviceNumber, - 0, - 0, - 0, - GnbLibGetHeader (Pcie) - ); - } - } - EngineList = PcieLibGetNextDescriptor (EngineList); - } - WrapperList = PcieLibGetNextDescriptor (WrapperList); - } - return AgesaStatus; -} - -/*----------------------------------------------------------------------------------------*/ -/** - * If link width from user descriptor less or equal to link width of engine - * - * - * @param[in] EngineDescriptor Pointer to used define engine descriptor - * @param[in] Engine Pointer to engine config - * @retval TRUE Descriptor can be mapped to engine - * @retval FALSE Descriptor can NOT be mapped to engine - */ - -BOOLEAN -PcieCheckLanesMatch ( - IN PCIe_ENGINE_DESCRIPTOR *EngineDescriptor, - IN PCIe_ENGINE_CONFIG *Engine - ) -{ - BOOLEAN Result; - UINT16 DescriptorHiLane; - UINT16 DescriptorLoLane; - UINT16 DescriptorNumberOfLanes; - - DescriptorLoLane = MIN (EngineDescriptor->EngineData.StartLane, EngineDescriptor->EngineData.EndLane); - DescriptorHiLane = MAX (EngineDescriptor->EngineData.StartLane, EngineDescriptor->EngineData.EndLane); - DescriptorNumberOfLanes = DescriptorHiLane - DescriptorLoLane + 1; - Result = FALSE; - - if (EngineDescriptor->EngineData.EngineType == PciePortEngine) { - // - // If link width from user descriptor less or equal to link width of engine (PCIe_ENGINE_CONFIG) - // - if (DescriptorNumberOfLanes <= PcieConfigGetNumberOfCoreLane (Engine)) { - Result = TRUE; - } - } else if (EngineDescriptor->EngineData.EngineType == PcieDdiEngine) { - // - //For Ddi, check lane from (PCIe_DDI_DESCRIPTOR) match exactly phy lane (PCIe_ENGINE_CONFIG) - // - if ((Engine->EngineData.StartLane == DescriptorLoLane) && (Engine->EngineData.EndLane == DescriptorHiLane)) { - Result = TRUE; - } - } - - return Result; -} - -/*----------------------------------------------------------------------------------------*/ -/** - * Correct link width for PCIe port x1, x2, x4, x8, x16, correct link width for DDI x4, x8 - * - * - * @param[in] EngineDescriptor A pointer of PCIe_ENGINE_DESCRIPTOR - * @retval TRUE Descriptor can be mapped to engine - * @retval FALSE Descriptor can NOT be mapped to engine - */ - -BOOLEAN -PcieIsDescriptorLinkWidthValid ( - IN PCIe_ENGINE_DESCRIPTOR *EngineDescriptor - ) -{ - BOOLEAN Result; - UINT16 DescriptorHiLane; - UINT16 DescriptorLoLane; - UINT16 DescriptorNumberOfLanes; - - Result = FALSE; - DescriptorLoLane = MIN (EngineDescriptor->EngineData.StartLane, EngineDescriptor->EngineData.EndLane); - DescriptorHiLane = MAX (EngineDescriptor->EngineData.StartLane, EngineDescriptor->EngineData.EndLane); - DescriptorNumberOfLanes = DescriptorHiLane - DescriptorLoLane + 1; - - if (EngineDescriptor->EngineData.EngineType == PciePortEngine) { - if (DescriptorNumberOfLanes == 1 || DescriptorNumberOfLanes == 2 || DescriptorNumberOfLanes == 4 || - DescriptorNumberOfLanes == 8 || DescriptorNumberOfLanes == 16) { - Result = TRUE; - } - } else if (EngineDescriptor->EngineData.EngineType == PcieDdiEngine) { - if (DescriptorNumberOfLanes == 4 || DescriptorNumberOfLanes == 8 || DescriptorNumberOfLanes == 7) { - Result = TRUE; - } - } - - GNB_DEBUG_CODE ( - if (!Result) { - IDS_HDT_CONSOLE (PCIE_MISC, " Invalid Link width [Engine Lanes %d..%d]\n", - DescriptorLoLane, - DescriptorHiLane - ); - } - ); - - return Result; -} - diff --git a/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieConfig/PcieMapTopology.h b/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieConfig/PcieMapTopology.h deleted file mode 100644 index d68429d55d..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieConfig/PcieMapTopology.h +++ /dev/null @@ -1,57 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * Procedure to map user define topology to processor configuration - * - * - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: GNB - * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $ - * - */ -/* -***************************************************************************** -* -* Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* *************************************************************************** -* -*/ -#ifndef _PCIEMAPTOPOLOGY_H_ -#define _PCIEMAPTOPOLOGY_H_ - -AGESA_STATUS -PcieMapTopologyOnComplex ( - IN PCIe_COMPLEX_DESCRIPTOR *ComplexDescriptor, - IN PCIe_COMPLEX_CONFIG *Complex, - IN PCIe_PLATFORM_CONFIG *Pcie - ); - -#endif - - diff --git a/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieInitLibV1/GnbPcieInitLibV1.h b/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieInitLibV1/GnbPcieInitLibV1.h deleted file mode 100644 index 1cb6d5d8e4..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieInitLibV1/GnbPcieInitLibV1.h +++ /dev/null @@ -1,60 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * PCIe Init Library - * - * - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: GNB - * @e \$Revision: 47656 $ @e \$Date: 2011-02-25 02:39:38 +0800 (Fri, 25 Feb 2011) $ - * - */ -/* -***************************************************************************** -* -* Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* *************************************************************************** -* -*/ -#ifndef _PCIEINITLIBV1_H_ -#define _PCIEINITLIBV1_H_ - -#include "PciePifServices.h" -#include "PciePortRegAcc.h" -#include "PciePowerMgmt.h" -#include "PcieTimer.h" -#include "PcieTopologyServices.h" -#include "PcieUtilityLib.h" -#include "PcieWrapperRegAcc.h" -#include "PcieAspmExitLatency.h" -#include "PcieSiliconServices.h" -#include "PciePortServices.h" -#include "PcieAspm.h" -#include "PciePhyServices.h" -#endif diff --git a/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieInitLibV1/Makefile.inc b/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieInitLibV1/Makefile.inc deleted file mode 100644 index a182555014..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieInitLibV1/Makefile.inc +++ /dev/null @@ -1,13 +0,0 @@ -libagesa-y += PcieAspm.c -libagesa-y += PcieAspmBlackList.c -libagesa-y += PcieAspmExitLatency.c -libagesa-y += PciePhyServices.c -libagesa-y += PciePifServices.c -libagesa-y += PciePortRegAcc.c -libagesa-y += PciePortServices.c -libagesa-y += PciePowerMgmt.c -libagesa-y += PcieSiliconServices.c -libagesa-y += PcieTimer.c -libagesa-y += PcieTopologyServices.c -libagesa-y += PcieUtilityLib.c -libagesa-y += PcieWrapperRegAcc.c diff --git a/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieInitLibV1/PcieAspm.c b/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieInitLibV1/PcieAspm.c deleted file mode 100644 index 19b6055180..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieInitLibV1/PcieAspm.c +++ /dev/null @@ -1,350 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * PCIe link ASPM - * - * - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: GNB - * @e \$Revision: 48452 $ @e \$Date: 2011-03-09 12:50:44 +0800 (Wed, 09 Mar 2011) $ - * - */ -/* -***************************************************************************** -* -* Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* *************************************************************************** -* -*/ - -/*---------------------------------------------------------------------------------------- - * M O D U L E S U S E D - *---------------------------------------------------------------------------------------- - */ -#include "AGESA.h" -#include "Ids.h" -#include "Gnb.h" -#include "GnbPcie.h" -#include "OptionGnb.h" -#include "GnbCommonLib.h" -#include "GnbPcieInitLibV1.h" -#include "PcieAspmBlackList.h" -#include "Filecode.h" -#define FILECODE PROC_GNB_MODULES_GNBPCIEINITLIBV1_PCIEASPM_FILECODE -/*---------------------------------------------------------------------------------------- - * D E F I N I T I O N S A N D M A C R O S - *---------------------------------------------------------------------------------------- - */ - -extern GNB_BUILD_OPTIONS GnbBuildOptions; -/*---------------------------------------------------------------------------------------- - * T Y P E D E F S A N D S T R U C T U R E S - *---------------------------------------------------------------------------------------- - */ - -typedef struct { - GNB_PCI_SCAN_DATA ScanData; - PCIE_ASPM_TYPE Aspm; - PCI_ADDR DownstreamPort; -} PCIE_ASPM_DATA; - -/*---------------------------------------------------------------------------------------- - * P R O T O T Y P E S O F L O C A L F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ -VOID -PcieAspmEnableOnDevice ( - IN PCI_ADDR Device, - IN PCIE_ASPM_TYPE Aspm, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -SCAN_STATUS -PcieAspmCallback ( - IN PCI_ADDR Device, - IN OUT GNB_PCI_SCAN_DATA *ScanData - ); - -VOID -PcieAspmEnableOnLink ( - IN PCI_ADDR Downstream, - IN PCI_ADDR Upstream, - IN PCIE_ASPM_TYPE Aspm, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -PCIE_ASPM_TYPE -PcieAspmGetPmCapability ( - IN PCI_ADDR Device, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -/*----------------------------------------------------------------------------------------*/ -/** - * Enable PCIE Advance state power management - * - * - * - * @param[in] DownstreamPort PCI Address of the downstream port - * @param[in] Aspm ASPM type - * @param[in] StdHeader Standard configuration header - * @retval AGESA_STATUS - */ - -VOID -PcieLinkAspmEnable ( - IN PCI_ADDR DownstreamPort, - IN PCIE_ASPM_TYPE Aspm, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - PCIE_ASPM_DATA PcieAspmData; - PcieAspmData.Aspm = Aspm; - PcieAspmData.ScanData.StdHeader = StdHeader; - PcieAspmData.ScanData.GnbScanCallback = PcieAspmCallback; - GnbLibPciScan (DownstreamPort, DownstreamPort, &PcieAspmData.ScanData); -} - -/*----------------------------------------------------------------------------------------*/ -/** - * Evaluate device - * - * - * - * @param[in] Device PCI Address - * @param[in,out] ScanData Scan configuration data - * @retval Scan Status of 0 - */ - -SCAN_STATUS -PcieAspmCallback ( - IN PCI_ADDR Device, - IN OUT GNB_PCI_SCAN_DATA *ScanData - ) -{ - SCAN_STATUS ScanStatus; - PCIE_ASPM_DATA *PcieAspmData; - PCIE_DEVICE_TYPE DeviceType; - ScanStatus = SCAN_SUCCESS; - IDS_HDT_CONSOLE (GNB_TRACE, " PcieAspmCallback for Device = %d:%d:%d\n", - Device.Address.Bus, - Device.Address.Device, - Device.Address.Function - ); - PcieAspmData = (PCIE_ASPM_DATA *) ScanData; - ScanStatus = SCAN_SUCCESS; - DeviceType = GnbLibGetPcieDeviceType (Device, ScanData->StdHeader); - switch (DeviceType) { - case PcieDeviceRootComplex: - case PcieDeviceDownstreamPort: - PcieAspmData->DownstreamPort = Device; - //PcieExitLatencyData->LinkCount++; - GnbLibPciRMW (Device.AddressValue | 0x18, AccessS3SaveWidth32, 0xffffffffull, 0x0, ScanData->StdHeader); - GnbLibPciScanSecondaryBus (Device, &PcieAspmData->ScanData); - //PcieExitLatencyData->LinkCount--; - break; - case PcieDeviceUpstreamPort: - PcieAspmEnableOnLink ( - PcieAspmData->DownstreamPort, - Device, - PcieAspmData->Aspm, - ScanData->StdHeader - ); - GnbLibPciRMW (Device.AddressValue | 0x18, AccessS3SaveWidth32, 0xffffffffull, 0x0, ScanData->StdHeader); - GnbLibPciScanSecondaryBus (Device, &PcieAspmData->ScanData); - ScanStatus = SCAN_SKIP_FUNCTIONS | SCAN_SKIP_DEVICES | SCAN_SKIP_BUSES; - break; - case PcieDeviceEndPoint: - case PcieDeviceLegacyEndPoint: - PcieAspmEnableOnLink ( - PcieAspmData->DownstreamPort, - Device, - PcieAspmData->Aspm, - ScanData->StdHeader - ); - ScanStatus = SCAN_SKIP_FUNCTIONS | SCAN_SKIP_DEVICES | SCAN_SKIP_BUSES; - break; - default: - break; - } - return ScanStatus; -} - -/*----------------------------------------------------------------------------------------*/ -/** - * Set ASMP State on PCIe device function - * - * - * - * @param[in] Function PCI address of function. - * @param[in] Aspm Aspm capability to enable - * @param[in] StdHeader Standard configuration header - * - */ - /*----------------------------------------------------------------------------------------*/ -VOID -PcieAspmEnableOnFunction ( - IN PCI_ADDR Function, - IN PCIE_ASPM_TYPE Aspm, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - UINT8 PcieCapPtr; - PcieCapPtr = GnbLibFindPciCapability (Function.AddressValue, PCIE_CAP_ID, StdHeader); - if (PcieCapPtr != 0) { - GnbLibPciRMW ( - Function.AddressValue | (PcieCapPtr + PCIE_LINK_CTRL_REGISTER) , - AccessS3SaveWidth8, - ~(UINT32)(BIT0 & BIT1), - Aspm, - StdHeader - ); - } -} - -/*----------------------------------------------------------------------------------------*/ -/** - * Set ASMP State on all function of PCI device - * - * - * - * @param[in] Device PCI address of device. - * @param[in] Aspm Aspm capability to enable - * @param[in] StdHeader Standard configuration header - * - */ - /*----------------------------------------------------------------------------------------*/ -VOID -PcieAspmEnableOnDevice ( - IN PCI_ADDR Device, - IN PCIE_ASPM_TYPE Aspm, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - UINT8 MaxFunc; - UINT8 CurrentFunc; - MaxFunc = GnbLibPciIsMultiFunctionDevice (Device.AddressValue, StdHeader) ? 7 : 0; - for (CurrentFunc = 0; CurrentFunc <= MaxFunc; CurrentFunc++) { - Device.Address.Function = CurrentFunc; - if (GnbLibPciIsDevicePresent (Device.AddressValue, StdHeader)) { - PcieAspmEnableOnFunction (Device, Aspm, StdHeader); - } - } -} - -/*----------------------------------------------------------------------------------------*/ -/** - * Enable ASPM on link - * - * - * - * @param[in] Downstream PCI Address of downstrteam port - * @param[in] Upstream PCI Address of upstream port - * @param[in] Aspm Aspm capability to enable - * @param[in] StdHeader Standard configuration header - */ - -VOID -PcieAspmEnableOnLink ( - IN PCI_ADDR Downstream, - IN PCI_ADDR Upstream, - IN PCIE_ASPM_TYPE Aspm, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - PCIe_LINK_ASPM LinkAsmp; - PCIE_ASPM_TYPE DownstreamCap; - PCIE_ASPM_TYPE UpstreamCap; - LinkAsmp.DownstreamPort = Downstream; - DownstreamCap = PcieAspmGetPmCapability (Downstream, StdHeader); - LinkAsmp.UpstreamPort = Upstream; - UpstreamCap = PcieAspmGetPmCapability (Upstream, StdHeader); - LinkAsmp.DownstreamAspm = DownstreamCap & UpstreamCap & Aspm & AspmL1; - LinkAsmp.UpstreamAspm = LinkAsmp.DownstreamAspm; - LinkAsmp.RequestedAspm = Aspm; - if ((UpstreamCap & Aspm & AspmL0s) != 0) { - LinkAsmp.UpstreamAspm |= AspmL0s; - } - if ((DownstreamCap & Aspm & AspmL0s) != 0) { - LinkAsmp.DownstreamAspm |= AspmL0s; - } - if (GnbBuildOptions.PcieAspmBlackListEnable == 1) { - PcieAspmBlackListFeature (&LinkAsmp, StdHeader); - } - //AgesaPcieLinkAspm (&LinkAsmp, StdHeader); - IDS_HDT_CONSOLE (GNB_TRACE, " Set ASPM [%d] for Device = %d:%d:%d\n", - (LinkAsmp.UpstreamAspm) , - LinkAsmp.UpstreamPort.Address.Bus, - LinkAsmp.UpstreamPort.Address.Device, - LinkAsmp.UpstreamPort.Address.Function - ); - IDS_HDT_CONSOLE (GNB_TRACE, " Set ASPM [%d] for Device = %d:%d:%d\n", - (LinkAsmp.DownstreamAspm) , - LinkAsmp.DownstreamPort.Address.Bus, - LinkAsmp.DownstreamPort.Address.Device, - LinkAsmp.DownstreamPort.Address.Function - ); - PcieAspmEnableOnDevice (Upstream, LinkAsmp.UpstreamAspm, StdHeader); - PcieAspmEnableOnFunction (Downstream, LinkAsmp.DownstreamAspm, StdHeader); -} - - - -/**----------------------------------------------------------------------------------------*/ -/** - * Port/Endpoint ASMP capability - * - * - * - * @param[in] Device PCI address of downstream port - * @param[in] StdHeader Standard configuration header - * - * @retval PCIE_ASPM_TYPE - */ - /*----------------------------------------------------------------------------------------*/ -PCIE_ASPM_TYPE -PcieAspmGetPmCapability ( - IN PCI_ADDR Device, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - UINT8 PcieCapPtr; - UINT32 Value; - PcieCapPtr = GnbLibFindPciCapability (Device.AddressValue, PCIE_CAP_ID, StdHeader); - if (PcieCapPtr == 0) { - return 0; - } - GnbLibPciRead ( - Device.AddressValue | (PcieCapPtr + PCIE_LINK_CAP_REGISTER), - AccessWidth32, - &Value, - StdHeader - ); - return (Value >> 10) & 3; -} diff --git a/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieInitLibV1/PcieAspm.h b/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieInitLibV1/PcieAspm.h deleted file mode 100644 index 4bb154c0e3..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieInitLibV1/PcieAspm.h +++ /dev/null @@ -1,63 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * PCIe link ASPM - * - * - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: GNB - * @e \$Revision: 47656 $ @e \$Date: 2011-02-25 02:39:38 +0800 (Fri, 25 Feb 2011) $ - * - */ -/* -***************************************************************************** -* -* Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* *************************************************************************** -* -*/ - -#ifndef _PCIEASPM_H_ -#define _PCIEASPM_H_ - -VOID -PcieLinkAspmEnable ( - IN PCI_ADDR DownstreamPort, - IN PCIE_ASPM_TYPE Aspm, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -VOID -PcieAspmEnableOnFunction ( - IN PCI_ADDR Function, - IN PCIE_ASPM_TYPE Aspm, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -#endif diff --git a/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieInitLibV1/PcieAspmBlackList.c b/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieInitLibV1/PcieAspmBlackList.c deleted file mode 100644 index d31876a72d..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieInitLibV1/PcieAspmBlackList.c +++ /dev/null @@ -1,141 +0,0 @@ -/** - * @file - * - * PCIe link ASPM Black List - * - * - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: GNB - * @e \$Revision: 48452 $ @e \$Date: 2011-03-09 12:50:44 +0800 (Wed, 09 Mar 2011) $ - * - */ -/* -***************************************************************************** -* -* Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* *************************************************************************** -* -*/ - -/*---------------------------------------------------------------------------------------- - * M O D U L E S U S E D - *---------------------------------------------------------------------------------------- - */ -#include "AGESA.h" -#include "Gnb.h" -#include "GnbPcie.h" -#include "GnbCommonLib.h" -#include "PcieAspmBlackList.h" -#include "Filecode.h" -#define FILECODE PROC_GNB_MODULES_GNBPCIEINITLIBV1_PCIEASPMBLACKLIST_FILECODE -/*---------------------------------------------------------------------------------------- - * D E F I N I T I O N S A N D M A C R O S - *---------------------------------------------------------------------------------------- - */ - - -/*---------------------------------------------------------------------------------------- - * T Y P E D E F S A N D S T R U C T U R E S - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------- - * P R O T O T Y P E S O F L O C A L F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ - - -UINT16 AspmBrDeviceTable[] = { - 0x1002, 0x9441, (UINT16) ~(AspmL1 | AspmL0s), - 0x10B5, 0xFFFF, (UINT16) ~(AspmL1 | AspmL0s), - 0x10DE, 0x0402, (UINT16) ~(AspmL1 | AspmL0s), - 0x10DE, 0x0193, (UINT16) ~(AspmL1 | AspmL0s), - 0x10DE, 0x0422, (UINT16) ~(AspmL1 | AspmL0s), - 0x10DE, 0x0292, (UINT16) ~(AspmL1 | AspmL0s), - 0x10DE, 0x00F9, (UINT16) ~(AspmL1 | AspmL0s), - 0x10DE, 0x0141, (UINT16) ~(AspmL1 | AspmL0s), - 0x10DE, 0x0092, (UINT16) ~(AspmL1 | AspmL0s), - 0x10DE, 0x01D0, (UINT16) ~(AspmL1 | AspmL0s), - 0x10DE, 0x01D1, (UINT16) ~(AspmL1 | AspmL0s), - 0x10DE, 0x01D2, (UINT16) ~(AspmL1 | AspmL0s), - 0x10DE, 0x01D3, (UINT16) ~(AspmL1 | AspmL0s), - 0x10DE, 0x01D5, (UINT16) ~(AspmL1 | AspmL0s), - 0x10DE, 0x01D7, (UINT16) ~(AspmL1 | AspmL0s), - 0x10DE, 0x01D8, (UINT16) ~(AspmL1 | AspmL0s), - 0x10DE, 0x01DC, (UINT16) ~(AspmL1 | AspmL0s), - 0x10DE, 0x01DE, (UINT16) ~(AspmL1 | AspmL0s), - 0x10DE, 0x01DF, (UINT16) ~(AspmL1 | AspmL0s), - 0x10DE, 0x016A, (UINT16) ~(AspmL1 | AspmL0s), - 0x10DE, 0x0392, (UINT16) ~(AspmL1 | AspmL0s), - 0x168C, 0xFFFF, (UINT16) ~(AspmL0s), - 0x1B4B, 0x91A3, (UINT16) ~(AspmL0s), - 0x1B4B, 0x9123, (UINT16) ~(AspmL0s) -}; - -/*----------------------------------------------------------------------------------------*/ -/** - * Pcie ASPM Black List - * - * - * - * @param[in] LinkAsmp PCie ASPM black list - * @param[in] StdHeader Standard configuration header - * @retval AGESA_STATUS - */ - -AGESA_STATUS -PcieAspmBlackListFeature ( - IN PCIe_LINK_ASPM *LinkAsmp, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - UINT32 UpstreamDeviceId; - UINT32 DownstreamDeviceId; - UINTN i; - GnbLibPciRead (LinkAsmp->UpstreamPort.AddressValue, AccessWidth32, &UpstreamDeviceId, StdHeader); - GnbLibPciRead (LinkAsmp->DownstreamPort.AddressValue, AccessWidth32, &DownstreamDeviceId, StdHeader); - for (i = 0; i < (sizeof (AspmBrDeviceTable) / sizeof (UINT16)); i = i + 3) { - UINT32 DeviceId; - UINT32 VendorId; - VendorId = AspmBrDeviceTable[i]; - DeviceId = AspmBrDeviceTable[i + 1]; - if (VendorId == (UINT16)UpstreamDeviceId || VendorId == (UINT16)DownstreamDeviceId ) { - if (DeviceId == 0xFFFF || DeviceId == (UpstreamDeviceId >> 16) || DeviceId == (DownstreamDeviceId >> 16)) { - LinkAsmp->UpstreamAspm &= AspmBrDeviceTable[i + 2]; - LinkAsmp->DownstreamAspm &= AspmBrDeviceTable[i + 2]; - } - } - } - if ((UINT16)UpstreamDeviceId == 0x168c) { - // Atheros (Ignore dev capability enable L1 if requested) - LinkAsmp->UpstreamAspm = LinkAsmp->RequestedAspm & AspmL1; - LinkAsmp->DownstreamAspm = LinkAsmp->UpstreamAspm; - GnbLibPciRMW (LinkAsmp->UpstreamPort.AddressValue | 0x70C, AccessS3SaveWidth32, 0x0, 0x0F003F01, StdHeader); - } - return AGESA_SUCCESS; -} diff --git a/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieInitLibV1/PcieAspmBlackList.h b/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieInitLibV1/PcieAspmBlackList.h deleted file mode 100644 index 15445f3da9..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieInitLibV1/PcieAspmBlackList.h +++ /dev/null @@ -1,55 +0,0 @@ -/** - * @file - * - * PCIe ASPM Black List - * - * - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: GNB - * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $ - * - */ -/* -***************************************************************************** -* -* Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* *************************************************************************** -* -*/ - -#ifndef _PCIEASPMBLACKLIST_H_ -#define _PCIEASPMBLACKLIST_H_ - -///PCIe ASPM Black List - -AGESA_STATUS -PcieAspmBlackListFeature ( - IN PCIe_LINK_ASPM *LinkAsmp, - IN AMD_CONFIG_PARAMS *StdHeader - ); -#endif diff --git a/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieInitLibV1/PcieAspmExitLatency.c b/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieInitLibV1/PcieAspmExitLatency.c deleted file mode 100644 index 2d4ffe593b..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieInitLibV1/PcieAspmExitLatency.c +++ /dev/null @@ -1,191 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * Service procedure to calculate PCIe topology segment maximum exit latency - * - * - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: GNB - * @e \$Revision: 48452 $ @e \$Date: 2011-03-09 12:50:44 +0800 (Wed, 09 Mar 2011) $ - * - */ -/* -***************************************************************************** -* -* Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* *************************************************************************** -* -*/ - -/*---------------------------------------------------------------------------------------- - * M O D U L E S U S E D - *---------------------------------------------------------------------------------------- - */ -#include "AGESA.h" -#include "Ids.h" -#include "Gnb.h" -#include "GnbPcie.h" -#include "GnbCommonLib.h" -#include "GnbPcieInitLibV1.h" -#include "Filecode.h" -#define FILECODE PROC_GNB_MODULES_GNBPCIEINITLIBV1_PCIEASPMEXITLATENCY_FILECODE -/*---------------------------------------------------------------------------------------- - * D E F I N I T I O N S A N D M A C R O S - *---------------------------------------------------------------------------------------- - */ - - -/*---------------------------------------------------------------------------------------- - * T Y P E D E F S A N D S T R U C T U R E S - *---------------------------------------------------------------------------------------- - */ - -typedef struct { - GNB_PCI_SCAN_DATA ScanData; - PCIe_ASPM_LATENCY_INFO *AspmLatencyInfo; - PCI_ADDR DownstreamPort; - UINT8 LinkCount; -} PCIE_EXIT_LATENCY_DATA; - -/*---------------------------------------------------------------------------------------- - * P R O T O T Y P E S O F L O C A L F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ - -SCAN_STATUS -PcieAspmGetMaxExitLatencyCallback ( - IN PCI_ADDR Device, - IN OUT GNB_PCI_SCAN_DATA *ScanData - ); - -/*----------------------------------------------------------------------------------------*/ -/** - * Determine ASPM L-state maximum exit latency for PCIe segment - * - * Scan through all link in segment to determine maxim exit latency requirement by EPs. - * - * @param[in] DownstreamPort PCI address of PCIe port - * @param[out] AspmLatencyInfo Latency info - * @param[in] StdHeader Standard configuration header - * - */ - -VOID -PcieAspmGetMaxExitLatency ( - IN PCI_ADDR DownstreamPort, - OUT PCIe_ASPM_LATENCY_INFO *AspmLatencyInfo, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - PCIE_EXIT_LATENCY_DATA PcieExitLatencyData; - PcieExitLatencyData.AspmLatencyInfo = AspmLatencyInfo; - PcieExitLatencyData.ScanData.StdHeader = StdHeader; - PcieExitLatencyData.LinkCount = 0; - PcieExitLatencyData.ScanData.GnbScanCallback = PcieAspmGetMaxExitLatencyCallback; - GnbLibPciScan (DownstreamPort, DownstreamPort, &PcieExitLatencyData.ScanData); -} - -/*----------------------------------------------------------------------------------------*/ -/** - * Evaluate device - * - * - * - * @param[in] Device PCI Address - * @param[in,out] ScanData Scan configuration data - * @retval Scan Status of 0 - */ - -SCAN_STATUS -PcieAspmGetMaxExitLatencyCallback ( - IN PCI_ADDR Device, - IN OUT GNB_PCI_SCAN_DATA *ScanData - ) -{ - SCAN_STATUS ScanStatus; - PCIE_EXIT_LATENCY_DATA *PcieExitLatencyData; - PCIE_DEVICE_TYPE DeviceType; - UINT32 Value; - UINT8 PcieCapPtr; - UINT8 L1AcceptableLatency; - - PcieExitLatencyData = (PCIE_EXIT_LATENCY_DATA*) ScanData; - ScanStatus = SCAN_SUCCESS; - DeviceType = GnbLibGetPcieDeviceType (Device, ScanData->StdHeader); - IDS_HDT_CONSOLE (GNB_TRACE, " PcieAspmGetMaxExitLatencyCallback for Device = %d:%d:%d\n", - Device.Address.Bus, - Device.Address.Device, - Device.Address.Function - ); - switch (DeviceType) { - case PcieDeviceRootComplex: - case PcieDeviceDownstreamPort: - PcieExitLatencyData->DownstreamPort = Device; - PcieExitLatencyData->LinkCount++; - GnbLibPciScanSecondaryBus (Device, &PcieExitLatencyData->ScanData); - PcieExitLatencyData->LinkCount--; - break; - case PcieDeviceUpstreamPort: - GnbLibPciScanSecondaryBus (Device, &PcieExitLatencyData->ScanData); - break; - case PcieDeviceEndPoint: - case PcieDeviceLegacyEndPoint: - PcieCapPtr = GnbLibFindPciCapability (Device.AddressValue, PCIE_CAP_ID, ScanData->StdHeader); - ASSERT (PcieCapPtr != 0); - GnbLibPciRead ( - Device.AddressValue | (PcieCapPtr + PCIE_LINK_CAP_REGISTER), - AccessWidth32, - &Value, - ScanData->StdHeader - ); - if ((Value & PCIE_ASPM_L1_SUPPORT_CAP) != 0) { - GnbLibPciRead ( - Device.AddressValue | (PcieCapPtr + PCIE_DEVICE_CAP_REGISTER), - AccessWidth32, - &Value, - ScanData->StdHeader - ); - L1AcceptableLatency = (UINT8) (1 << ((Value >> 9) & 0x7)); - if (PcieExitLatencyData->LinkCount > 1) { - L1AcceptableLatency = L1AcceptableLatency + PcieExitLatencyData->LinkCount; - } - if (PcieExitLatencyData->AspmLatencyInfo->MaxL1ExitLatency < L1AcceptableLatency) { - PcieExitLatencyData->AspmLatencyInfo->MaxL1ExitLatency = L1AcceptableLatency; - } - IDS_HDT_CONSOLE (PCIE_MISC, " Device max exit latency L1 - %d us\n", - L1AcceptableLatency - ); - } - break; - default: - break; - } - return SCAN_SUCCESS; -} - diff --git a/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieInitLibV1/PcieAspmExitLatency.h b/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieInitLibV1/PcieAspmExitLatency.h deleted file mode 100644 index 8d68dd0cf0..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieInitLibV1/PcieAspmExitLatency.h +++ /dev/null @@ -1,55 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * Service procedure to calculate PCIe topology segment maximum exit latency - * - * - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: GNB - * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $ - * - */ -/* -***************************************************************************** -* -* Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* *************************************************************************** -* -*/ - -#ifndef _PCIEASPMEXITLATENCY_H_ -#define _PCIEASPMEXITLATENCY_H_ - -VOID -PcieAspmGetMaxExitLatency ( - IN PCI_ADDR DownstreamPort, - OUT PCIe_ASPM_LATENCY_INFO *AspmLatencyInfo, - IN AMD_CONFIG_PARAMS *StdHeader - ); -#endif diff --git a/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieInitLibV1/PciePhyServices.c b/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieInitLibV1/PciePhyServices.c deleted file mode 100644 index 884f076677..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieInitLibV1/PciePhyServices.c +++ /dev/null @@ -1,310 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * PCIe PIF initialization routine - * - * - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: GNB - * @e \$Revision: 48452 $ @e \$Date: 2011-03-09 12:50:44 +0800 (Wed, 09 Mar 2011) $ - * - */ -/* -***************************************************************************** -* -* Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* *************************************************************************** -* -*/ -/*---------------------------------------------------------------------------------------- - * M O D U L E S U S E D - *---------------------------------------------------------------------------------------- - */ - -#include "AGESA.h" -#include "Ids.h" -#include "amdlib.h" -#include "Gnb.h" -#include "GnbPcie.h" -#include "GnbCommonLib.h" -#include "GnbPcieConfig.h" -#include "GnbPcieInitLibV1.h" -#include "GnbRegistersLN.h" -#include "Filecode.h" -#define FILECODE PROC_GNB_MODULES_GNBPCIEINITLIBV1_PCIEPHYSERVICES_FILECODE -/*---------------------------------------------------------------------------------------- - * D E F I N I T I O N S A N D M A C R O S - *---------------------------------------------------------------------------------------- - */ - -#define MAX_NUM_PHYs 2 -#define MAX_NUM_LANE_PER_PHY 8 - -/*---------------------------------------------------------------------------------------- - * T Y P E D E F S A N D S T R U C T U R E S - *---------------------------------------------------------------------------------------- - */ - -// Required init values -INT8 ReqdInitValLo [] = { 42, 64, 0, 42, 64, 77}; -INT8 ReqdInitValHi [] = { 42, 64, 0, 42, 64, 77}; - - -//Channel Type: LowLoss / HighLoss / Mob0db / Mob3db / Ext6db / Ext8db -INT8 DeemphasisSel [] = { 1, 0, 1, 1, 0, 0}; -INT8 DeemphGen1Nom [] = { 42, 42, 0, 0, 42, 42}; - -/*---------------------------------------------------------------------------------------- - * P R O T O T Y P E S O F L O C A L F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ - - -/*---------------------------------------------------------------------------------------- - * E X P O R T E D F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ - - -/*----------------------------------------------------------------------------------------*/ -/** - * PHY lane ganging - * - * - * - * @param[out] Wrapper Pointer to internal configuration data area - * @param[in] Pcie Pointer to global PCIe configuration - */ -VOID -PciePhyApplyGanging ( - IN PCIe_WRAPPER_CONFIG *Wrapper, - IN PCIe_PLATFORM_CONFIG *Pcie - ) -{ - PCIe_ENGINE_CONFIG *EngineList; - UINT8 GangMatrix [MAX_NUM_PHYs][MAX_NUM_LANE_PER_PHY]; - UINT8 MasterMatrix [MAX_NUM_PHYs][MAX_NUM_LANE_PER_PHY]; - UINT16 LoPhylane; - UINT16 HiPhylane; - UINT8 Phy; - UINT16 Lane; - UINT16 PhyLinkWidth; - IDS_HDT_CONSOLE (GNB_TRACE, "PciePhyApplyGanging Enter\n"); - LibAmdMemFill (GangMatrix, 0, sizeof (GangMatrix), GnbLibGetHeader (Pcie)); - LibAmdMemFill (MasterMatrix, 0, sizeof (MasterMatrix), GnbLibGetHeader (Pcie)); - EngineList = PcieConfigGetChildEngine (Wrapper); - while (EngineList != NULL) { - if (PcieLibIsEngineAllocated (EngineList)) { - HiPhylane = PcieLibGetHiPhyLane (EngineList) - Wrapper->StartPhyLane; - LoPhylane = PcieLibGetLoPhyLane (EngineList) - Wrapper->StartPhyLane; - PhyLinkWidth = HiPhylane - LoPhylane + 1; - - if (PhyLinkWidth >= 8) { - for (Lane = LoPhylane; Lane <= HiPhylane; Lane++) { - ((UINT8 *) GangMatrix)[Lane] = 1; - } - } else { - if (PhyLinkWidth > 0 && PhyLinkWidth < 4) { - for (Lane = (LoPhylane / 4) * 4; Lane < (((LoPhylane / 4) * 4) + 4) ; Lane++) { - ((UINT8 *) MasterMatrix)[Lane] = 1; - } - } - } - } - EngineList = PcieLibGetNextDescriptor (EngineList); - } - for (Phy = 0; Phy < Wrapper->NumberOfPIFs; Phy++) { - for (Lane = 0; Lane < MAX_NUM_LANE_PER_PHY; Lane++) { - D0F0xE4_PHY_6005_STRUCT D0F0xE4_PHY_6005; - D0F0xE4_PHY_6005.Value = PcieRegisterRead ( - Wrapper, - PHY_SPACE (Wrapper->WrapId, Phy, D0F0xE4_PHY_6005_ADDRESS + Lane * 0x80), - Pcie - ); - D0F0xE4_PHY_6005.Field.GangedModeEn = GangMatrix [Phy][Lane]; - D0F0xE4_PHY_6005.Field.IsOwnMstr = MasterMatrix [Phy][Lane]; - PcieRegisterWrite ( - Wrapper, - PHY_SPACE (Wrapper->WrapId, Phy, D0F0xE4_PHY_6005_ADDRESS + Lane * 0x80), - D0F0xE4_PHY_6005.Value, - FALSE, - Pcie - ); - } - } - IDS_HDT_CONSOLE (GNB_TRACE, "PciePhyApplyGanging Exit\n"); -} - - -/*----------------------------------------------------------------------------------------*/ -/** - * Point "virtual" PLL clock picker away from PCIe - * - * - * - * @param[in] Wrapper Pointer to internal configuration data area - * @param[in] Pcie Pointer to global PCIe configuration - */ -VOID -PciePhyAvertClockPickers ( - IN PCIe_WRAPPER_CONFIG *Wrapper, - IN PCIe_PLATFORM_CONFIG *Pcie - ) -{ - UINT32 DdiLanes; - UINT8 Nibble; - IDS_HDT_CONSOLE (GNB_TRACE, "PciePhyAvertClockPickers Enter\n"); - DdiLanes = PcieUtilGetWrapperLaneBitMap (LANE_TYPE_DDI_PHY_NATIVE, 0, Wrapper); - for (Nibble = 0; Nibble < 4; Nibble++) { - if (DdiLanes & (0xf << (Nibble * 4))) { - PcieRegisterRMW ( - Wrapper, - PHY_SPACE (Wrapper->WrapId, (Nibble >> 1), D0F0xE4_PHY_0009_ADDRESS + (Nibble & 0x1)), - D0F0xE4_PHY_0009_PCIePllSel_MASK, - 0x0 << D0F0xE4_PHY_0009_PCIePllSel_OFFSET, - FALSE, - Pcie - ); - PcieRegisterRMW ( - Wrapper, - PHY_SPACE (Wrapper->WrapId, (Nibble >> 1), D0F0xE4_PHY_000B_ADDRESS + (Nibble & 0x1)), - D0F0xE4_PHY_000B_MargPktSbiEn_MASK | D0F0xE4_PHY_000B_PcieModeSbiEn_MASK, - (0x0 << D0F0xE4_PHY_000B_MargPktSbiEn_OFFSET) | (0x0 << D0F0xE4_PHY_000B_PcieModeSbiEn_OFFSET), - FALSE, - Pcie - ); - } - } - IDS_HDT_CONSOLE (GNB_TRACE, "PciePhyAvertClockPickers Exit\n"); -} - -/*----------------------------------------------------------------------------------------*/ -/** - * Set PHY channel characteristic - * - * - * - * @param[in] Engine Pointer to engine configuration - * @param[in] Pcie Pointer to global PCIe configuration - */ -VOID -PciePhyChannelCharacteristic ( - IN PCIe_ENGINE_CONFIG *Engine, - IN PCIe_PLATFORM_CONFIG *Pcie - ) -{ - PCIe_WRAPPER_CONFIG *Wrapper; - UINT16 StartLane; - UINT16 EndLane; - UINT16 Lane; - UINT8 ChannelType; - - Wrapper = PcieConfigGetParentWrapper (Engine); - ChannelType = Engine->Type.Port.PortData.ChannelType; - StartLane = MIN (Engine->EngineData.StartLane, Engine->EngineData.EndLane) - Wrapper->StartPhyLane; - EndLane = MAX (Engine->EngineData.StartLane, Engine->EngineData.EndLane) - Wrapper->StartPhyLane; - - PcieRegisterRMW ( - Wrapper, - WRAP_SPACE (Wrapper->WrapId, D0F0xE4_WRAP_0803_ADDRESS + (Engine->Type.Port.PortId) * 0x100), - D0F0xE4_WRAP_0903_StrapBifDeemphasisSel_MASK, - DeemphasisSel[ChannelType] << D0F0xE4_WRAP_0903_StrapBifDeemphasisSel_OFFSET, - FALSE, - Pcie - ); - for (Lane = StartLane; Lane <= EndLane; Lane++) { - UINT16 PhyLane; - UINT16 Phy; - if (Lane < MAX_NUM_LANE_PER_PHY ) { - Phy = 0; - PhyLane = Lane; - } else { - Phy = 1; - PhyLane = Lane - MAX_NUM_LANE_PER_PHY; - } - PcieRegisterRMW ( - Wrapper, - PHY_SPACE (Wrapper->WrapId, Phy, D0F0xE4_PHY_6006_ADDRESS + PhyLane * 0x80), - D0F0xE4_PHY_6006_DeemphGen1Nom_MASK, - DeemphGen1Nom[ChannelType] << D0F0xE4_PHY_6006_DeemphGen1Nom_OFFSET, - FALSE, - Pcie - ); - PcieRegisterRMW ( - Wrapper, - PHY_SPACE (Wrapper->WrapId, Phy, D0F0xE4_PHY_6006_ADDRESS + PhyLane * 0x80), - 0x00FF000, - ReqdInitValLo[ChannelType] << 16, - FALSE, - Pcie - ); - PcieRegisterRMW ( - Wrapper, - PHY_SPACE (Wrapper->WrapId, Phy, D0F0xE4_PHY_6006_ADDRESS + PhyLane * 0x80), - 0xFF000000, - ReqdInitValHi[ChannelType] << 24, - FALSE, - Pcie - ); - } -} - -/*----------------------------------------------------------------------------------------*/ -/** - * DCC recalibration - * - * - * - * @param[in] Wrapper Pointer to internal configuration data area - * @param[in] Pcie Pointer to global PCIe configuration - */ - -AGESA_STATUS -PciePhyForceDccRecalibration ( - IN PCIe_WRAPPER_CONFIG *Wrapper, - IN PCIe_PLATFORM_CONFIG *Pcie - ) -{ - UINT8 Phy; - UINT8 PhyLane; - for (Phy = 0; Phy < Wrapper->NumberOfPIFs; Phy++) { - for (PhyLane = 0; PhyLane < MAX_NUM_LANE_PER_PHY; PhyLane++) { - PcieRegisterWriteField ( - Wrapper, - PHY_SPACE (Wrapper->WrapId, Phy, D0F0xE4_PHY_4001_ADDRESS + PhyLane * 0x80), - D0F0xE4_PHY_4001_ForceDccRecalc_OFFSET, - D0F0xE4_PHY_4001_ForceDccRecalc_WIDTH, - 0x1, - FALSE, - Pcie - ); - } - } - return AGESA_SUCCESS; -} diff --git a/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieInitLibV1/PciePhyServices.h b/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieInitLibV1/PciePhyServices.h deleted file mode 100644 index 61124198c0..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieInitLibV1/PciePhyServices.h +++ /dev/null @@ -1,73 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * PCIe PIF initialization routine - * - * - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: GNB - * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $ - * - */ -/* -***************************************************************************** -* -* Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* *************************************************************************** -* -*/ - -#ifndef _PCIEPHYSERVICES_H_ -#define _PCIEPHYSERVICES_H_ - -VOID -PciePhyApplyGanging ( - IN PCIe_WRAPPER_CONFIG *Wrapper, - IN PCIe_PLATFORM_CONFIG *Pcie - ); - -VOID -PciePhyAvertClockPickers ( - IN PCIe_WRAPPER_CONFIG *Wrapper, - IN PCIe_PLATFORM_CONFIG *Pcie - ); - -VOID -PciePhyChannelCharacteristic ( - IN PCIe_ENGINE_CONFIG *Engine, - IN PCIe_PLATFORM_CONFIG *Pcie - ); - -AGESA_STATUS -PciePhyForceDccRecalibration ( - IN PCIe_WRAPPER_CONFIG *Wrapper, - IN PCIe_PLATFORM_CONFIG *Pcie - ); - -#endif diff --git a/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieInitLibV1/PciePifServices.c b/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieInitLibV1/PciePifServices.c deleted file mode 100644 index b4ee0db197..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieInitLibV1/PciePifServices.c +++ /dev/null @@ -1,627 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * PCIe PIF initialization routine - * - * - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: GNB - * @e \$Revision: 48452 $ @e \$Date: 2011-03-09 12:50:44 +0800 (Wed, 09 Mar 2011) $ - * - */ -/* -***************************************************************************** -* -* Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* *************************************************************************** -* -*/ -/*---------------------------------------------------------------------------------------- - * M O D U L E S U S E D - *---------------------------------------------------------------------------------------- - */ - -#include "AGESA.h" -#include "Ids.h" -#include "amdlib.h" -#include "Gnb.h" -#include "GnbPcie.h" -#include "GnbCommonLib.h" -#include "GnbPcieConfig.h" -#include "GnbPcieInitLibV1.h" -#include "GnbRegistersLN.h" -#include "Filecode.h" -#define FILECODE PROC_GNB_MODULES_GNBPCIEINITLIBV1_PCIEPIFSERVICES_FILECODE -/*---------------------------------------------------------------------------------------- - * D E F I N I T I O N S A N D M A C R O S - *---------------------------------------------------------------------------------------- - */ - -#define PIF_GANG_0to1 0x1 -#define PIF_GANG_2to3 (0x1 << 1) -#define PIF_GANG_4to5 (0x1 << 2) -#define PIF_GANG_6to7 (0x1 << 3) -#define PIF_GANG_0to3 (0x1 << 4) -#define PIF_GANG_4to7 (0x1 << 8) -#define PIF_GANG_0to7 (0x1 << 9) -#define PIF_GANG_ALL (0x1 << 25) - -/*---------------------------------------------------------------------------------------- - * T Y P E D E F S A N D S T R U C T U R E S - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------- - * P R O T O T Y P E S O F L O C A L F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ - - -/*---------------------------------------------------------------------------------------- - * E X P O R T E D F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ - - -/*----------------------------------------------------------------------------------------*/ -/** - * Apply PIF ganging for all lanes for given wrapper - * - * - * - * @param[in] Wrapper Pointer to Wrapper config descriptor - * @param[in] Pcie Pointer to PICe configuration data area - */ - - -VOID -PciePifApplyGanging ( - IN PCIe_WRAPPER_CONFIG *Wrapper, - IN PCIe_PLATFORM_CONFIG *Pcie - ) -{ - PCIe_ENGINE_CONFIG *EngineList; - UINT32 LaneBitmap; - UINT8 Pif; - D0F0xE4_PIF_0011_STRUCT D0F0xE4_PIF_0011[2]; - IDS_HDT_CONSOLE (GNB_TRACE, "PciePifApplyGanging Enter\n"); - LibAmdMemFill (&D0F0xE4_PIF_0011, 0, sizeof (D0F0xE4_PIF_0011), GnbLibGetHeader (Pcie)); - EngineList = PcieConfigGetChildEngine (Wrapper); - while (EngineList != NULL) { - if (PcieLibIsEngineAllocated (EngineList)) { - LaneBitmap = PcieUtilGetEngineLaneBitMap (LANE_TYPE_PCIE_PHY_NATIVE, 0, EngineList); - switch (LaneBitmap) { - case 0x0003: - D0F0xE4_PIF_0011[0].Field.X2Lane10 = 0x1; - break; - case 0x000c: - D0F0xE4_PIF_0011[0].Field.X2Lane32 = 0x1; - break; - case 0x0030: - D0F0xE4_PIF_0011[0].Field.X2Lane54 = 0x1; - break; - case 0x00c0: - D0F0xE4_PIF_0011[0].Field.X2Lane76 = 0x1; - break; - case 0x000f: - D0F0xE4_PIF_0011[0].Field.X4Lane30 = 0x1; - break; - case 0x00f0: - D0F0xE4_PIF_0011[0].Field.X4Lane74 = 0x1; - break; - case 0x00ff: - D0F0xE4_PIF_0011[0].Field.X8Lane70 = 0x1; - break; - case 0x0300: - D0F0xE4_PIF_0011[1].Field.X2Lane10 = 1; - break; - case 0x0c00: - D0F0xE4_PIF_0011[1].Field.X2Lane32 = 0x1; - break; - case 0x3000: - D0F0xE4_PIF_0011[1].Field.X2Lane54 = 0x1; - break; - case 0xc000: - D0F0xE4_PIF_0011[1].Field.X2Lane76 = 0x1; - break; - case 0x0f00: - D0F0xE4_PIF_0011[1].Field.X4Lane30 = 0x1; - break; - case 0xf000: - D0F0xE4_PIF_0011[1].Field.X4Lane74 = 0x1; - break; - case 0xff00: - D0F0xE4_PIF_0011[1].Field.X8Lane70 = 0x1; - break; - case 0xffff: - D0F0xE4_PIF_0011[0].Field.MultiPif = 0x1; - D0F0xE4_PIF_0011[1].Field.MultiPif = 0x1; - break; - default: - break; - } - } - EngineList = PcieLibGetNextDescriptor (EngineList); - } - for (Pif = 0; Pif < Wrapper->NumberOfPIFs; Pif++) { - PcieRegisterWrite ( - Wrapper, - PIF_SPACE (Wrapper->WrapId, Pif, D0F0xE4_PIF_0011_ADDRESS), - D0F0xE4_PIF_0011[Pif].Value, - FALSE, - Pcie - ); - } - IDS_HDT_CONSOLE (GNB_TRACE, "PciePifApplyGanging Exit\n"); -} - - -/*----------------------------------------------------------------------------------------*/ -/** - * PLL powerdown - * - * - * @param[in] LaneBitmap Power down PLL for these lanes - * @param[in] Wrapper Pointer to Wrapper config descriptor - * @param[in] Pcie Pointer to PICe configuration data area - */ - -VOID -PciePifPllPowerDown ( - IN UINT32 LaneBitmap, - IN PCIe_WRAPPER_CONFIG *Wrapper, - IN PCIe_PLATFORM_CONFIG *Pcie - ) -{ - UINT8 Nibble; - UINT16 NibbleBitmap; - D0F0xE4_PIF_0012_STRUCT D0F0xE4_PIF_0012; - IDS_HDT_CONSOLE (GNB_TRACE, "PciePifPllPowerDown Enter\n"); - for (Nibble = 0; Nibble < 4; Nibble++) { - NibbleBitmap = (0xF << (Nibble * 4)); - if ((LaneBitmap & NibbleBitmap) == NibbleBitmap) { - D0F0xE4_PIF_0012.Value = PcieRegisterRead ( - Wrapper, - PIF_SPACE (Wrapper->WrapId, (Nibble >> 1), D0F0xE4_PIF_0012_ADDRESS + (Nibble & 0x1)), - Pcie - ); - - D0F0xE4_PIF_0012.Field.PllPowerStateInTxs2 = PifPowerStateOff; - D0F0xE4_PIF_0012.Field.PllPowerStateInOff = PifPowerStateOff; - D0F0xE4_PIF_0012.Field.TxPowerStateInTxs2 = PifPowerStateOff; - D0F0xE4_PIF_0012.Field.RxPowerStateInRxs2 = PifPowerStateOff; - PcieRegisterWrite ( - Wrapper, - PIF_SPACE (Wrapper->WrapId, (Nibble >> 1), D0F0xE4_PIF_0012_ADDRESS + (Nibble & 0x1)), - D0F0xE4_PIF_0012.Value, - TRUE, - Pcie - ); - } - } - IDS_HDT_CONSOLE (GNB_TRACE, "PciePifPllPowerDown Exit\n"); -} - -/*----------------------------------------------------------------------------------------*/ -/** - * PLL init for DDI - * - * - * - * @param[in] Wrapper Pointer to Wrapper config descriptor - * @param[in] Pcie Pointer to PICe configuration data area - */ - -VOID -PciePifPllInitForDdi ( - IN PCIe_WRAPPER_CONFIG *Wrapper, - IN PCIe_PLATFORM_CONFIG *Pcie - ) -{ - UINT8 Nibble; - UINT32 LaneBitmap; - D0F0xE4_PIF_0012_STRUCT D0F0xE4_PIF_0012; - IDS_HDT_CONSOLE (GNB_TRACE, "PciePifPllInitForDdi Enter\n"); - LaneBitmap = PcieUtilGetWrapperLaneBitMap (LANE_TYPE_DDI_PHY_NATIVE, 0, Wrapper); - for (Nibble = 0; Nibble < 4; Nibble++) { - if (LaneBitmap & (0xF << (Nibble * 4))) { - D0F0xE4_PIF_0012.Value = PcieRegisterRead ( - Wrapper, - PIF_SPACE (Wrapper->WrapId, (Nibble >> 1), D0F0xE4_PIF_0012_ADDRESS + (Nibble & 0x1)), - Pcie - ); - - D0F0xE4_PIF_0012.Field.PllPowerStateInTxs2 = PifPowerStateOff; - D0F0xE4_PIF_0012.Field.PllPowerStateInOff = PifPowerStateOff; - D0F0xE4_PIF_0012.Field.PllRampUpTime = 0x2; - PcieRegisterWrite ( - Wrapper, - PIF_SPACE (Wrapper->WrapId, (Nibble >> 1), D0F0xE4_PIF_0012_ADDRESS + (Nibble & 0x1)), - D0F0xE4_PIF_0012.Value, - FALSE, - Pcie - ); - } - } - IDS_HDT_CONSOLE (GNB_TRACE, "PciePifPllInitForDdi Exit\n"); -} - -/*----------------------------------------------------------------------------------------*/ -/** - * Poll for on PIF to indicate action completion - * - * - * - * @param[in] Wrapper Pointer to wrapper config descriptor - * @param[in] Pcie Pointer to global PCIe configuration - */ -VOID -PciePollPifForCompeletion ( - IN PCIe_WRAPPER_CONFIG *Wrapper, - IN PCIe_PLATFORM_CONFIG *Pcie - ) -{ - UINT32 TimeStamp; - UINT8 Pif; - D0F0xE4_PIF_0015_STRUCT D0F0xE4_PIF_0015; - TimeStamp = PcieTimerGetTimeStamp (Pcie); - for (Pif = 0; Pif < Wrapper->NumberOfPIFs; Pif++) { - do { - D0F0xE4_PIF_0015.Value = PcieRegisterRead ( - Wrapper, - PIF_SPACE (Wrapper->WrapId, Pif, D0F0xE4_PIF_0015_ADDRESS), - Pcie - ); - if (TIMESTAMPS_DELTA (TimeStamp, PcieTimerGetTimeStamp (Pcie)) > 100) { - break; - } - } while ((D0F0xE4_PIF_0015.Value & 0xff) != 0xff); - } -} - -/*----------------------------------------------------------------------------------------*/ -/** - * Disable fifo reset - * - * - * - * @param[in] Wrapper Pointer to Wrapper config descriptor - * @param[in] Pcie Pointer to PICe configuration data area - */ - - -VOID -PciePifDisableFifoReset ( - IN PCIe_WRAPPER_CONFIG *Wrapper, - IN PCIe_PLATFORM_CONFIG *Pcie - ) -{ - UINT8 Pif; - for (Pif = 0; Pif < Wrapper->NumberOfPIFs; Pif++) { - PcieRegisterWriteField ( - Wrapper, - PIF_SPACE (Wrapper->WrapId, Pif, D0F0xE4_PIF_0010_ADDRESS), - D0F0xE4_PIF_0010_RxDetectFifoResetMode_OFFSET, - D0F0xE4_PIF_0010_RxDetectFifoResetMode_WIDTH, - 0, - FALSE, - Pcie - ); - } -} - -/*----------------------------------------------------------------------------------------*/ -/** - * Program LS2 exit time - * - * - * - * @param[in] Wrapper Pointer to wrapper config descriptor - * @param[in] Pcie Pointer to global PCIe configuration - */ - -VOID -PciePifSetLs2ExitTime ( - IN PCIe_WRAPPER_CONFIG *Wrapper, - IN PCIe_PLATFORM_CONFIG *Pcie - ) -{ - UINT8 Pif; - IDS_HDT_CONSOLE (GNB_TRACE, "PciePifSetLs2ExitTime Enter\n"); - for (Pif = 0; Pif < Wrapper->NumberOfPIFs; Pif++) { - PcieRegisterWriteField ( - Wrapper, - PIF_SPACE (Wrapper->WrapId, Pif, D0F0xE4_PIF_0010_ADDRESS), - D0F0xE4_PIF_0010_Ls2ExitTime_OFFSET, - D0F0xE4_PIF_0010_Ls2ExitTime_WIDTH, - 0x0, - FALSE, - Pcie - ); - } - IDS_HDT_CONSOLE (GNB_TRACE, "PciePifSetLs2ExitTime Exit\n"); -} - -/*----------------------------------------------------------------------------------------*/ -/** - * Set PLL mode for L1 - * - * - * @param[in] LaneBitmap Power down PLL for these lanes - * @param[in] Wrapper Pointer to Wrapper config descriptor - * @param[in] Pcie Pointer to PICe configuration data area - */ - -VOID -PciePifSetPllModeForL1 ( - IN UINT32 LaneBitmap, - IN PCIe_WRAPPER_CONFIG *Wrapper, - IN PCIe_PLATFORM_CONFIG *Pcie - ) -{ - UINT8 Nibble; - D0F0xE4_PIF_0012_STRUCT D0F0xE4_PIF_0012; - for (Nibble = 0; Nibble < 4; Nibble++) { - if (LaneBitmap & (0xF << (Nibble * 4))) { - D0F0xE4_PIF_0012.Value = PcieRegisterRead ( - Wrapper, - PIF_SPACE (Wrapper->WrapId, (Nibble >> 1), D0F0xE4_PIF_0012_ADDRESS + (Nibble & 0x1)), - Pcie - ); - D0F0xE4_PIF_0012.Field.RxPowerStateInRxs2 = PifPowerStateLS2; - D0F0xE4_PIF_0012.Field.TxPowerStateInTxs2 = PifPowerStateLS2; - D0F0xE4_PIF_0012.Field.PllPowerStateInTxs2 = PifPowerStateOff; - D0F0xE4_PIF_0012.Field.PllPowerStateInOff = PifPowerStateOff; - D0F0xE4_PIF_0012.Field.PllRampUpTime = 0x1; - PcieRegisterWrite ( - Wrapper, - PIF_SPACE (Wrapper->WrapId, (Nibble >> 1), D0F0xE4_PIF_0012_ADDRESS + (Nibble & 0x1)), - D0F0xE4_PIF_0012.Value, - TRUE, - Pcie - ); - } - } -} - -/*----------------------------------------------------------------------------------------*/ -/** - * Program receiver detection power mode - * - * - * - * @param[in] Wrapper Pointer to wrapper config descriptor - * @param[in] Pcie Pointer to global PCIe configuration - */ - -VOID -PciePifSetRxDetectPowerMode ( - IN PCIe_WRAPPER_CONFIG *Wrapper, - IN PCIe_PLATFORM_CONFIG *Pcie - ) -{ - UINT8 Pif; - IDS_HDT_CONSOLE (GNB_TRACE, "PciePifSetRxDetectPowerMode Enter\n"); - for (Pif = 0; Pif < Wrapper->NumberOfPIFs; Pif++) { - PcieRegisterWriteField ( - Wrapper, - PIF_SPACE (Wrapper->WrapId, Pif, D0F0xE4_PIF_0010_ADDRESS), - D0F0xE4_PIF_0010_RxDetectTxPwrMode_OFFSET, - D0F0xE4_PIF_0010_RxDetectTxPwrMode_WIDTH, - 0x1, - FALSE, - Pcie - ); - } - IDS_HDT_CONSOLE (GNB_TRACE, "PciePifSetRxDetectPowerMode Enter\n"); -} - - -/*----------------------------------------------------------------------------------------*/ -/** - * Pll ramp up time - * - * - * - * @param[in] Rampup Ramp up time - * @param[in] Wrapper Pointer to wrapper config descriptor - * @param[in] Pcie Pointer to global PCIe configuration - */ -VOID -PciePifSetPllRampTime ( - IN PCIE_PLL_RAMPUP_TIME Rampup, - IN PCIe_WRAPPER_CONFIG *Wrapper, - IN PCIe_PLATFORM_CONFIG *Pcie - ) -{ - UINT8 Pif; - D0F0xE4_PIF_0012_STRUCT D0F0xE4_PIF_0012; - D0F0xE4_PIF_0013_STRUCT D0F0xE4_PIF_0013; - D0F0xE4_PIF_0010_STRUCT D0F0xE4_PIF_0010; - IDS_HDT_CONSOLE (GNB_TRACE, "PciePifSetPllRampTime Enter\n"); - for (Pif = 0; Pif < Wrapper->NumberOfPIFs; Pif++) { - D0F0xE4_PIF_0012.Value = PcieRegisterRead ( - Wrapper, - PIF_SPACE (Wrapper->WrapId, Pif, D0F0xE4_PIF_0012_ADDRESS), - Pcie - ); - D0F0xE4_PIF_0013.Value = PcieRegisterRead ( - Wrapper, - PIF_SPACE (Wrapper->WrapId, Pif, D0F0xE4_PIF_0013_ADDRESS), - Pcie - ); - D0F0xE4_PIF_0010.Value = PcieRegisterRead ( - Wrapper, - PIF_SPACE (Wrapper->WrapId, Pif, D0F0xE4_PIF_0010_ADDRESS), - Pcie - ); - if (Rampup == NormalRampup) { - D0F0xE4_PIF_0012.Field.PllRampUpTime = 0x1; - D0F0xE4_PIF_0013.Field.PllRampUpTime = 0x1; - D0F0xE4_PIF_0010.Field.Ls2ExitTime = 0x0; - } else { - D0F0xE4_PIF_0012.Field.PllRampUpTime = 0x3; - D0F0xE4_PIF_0013.Field.PllRampUpTime = 0x3; - D0F0xE4_PIF_0010.Field.Ls2ExitTime = 0x6; - } - PcieRegisterWrite ( - Wrapper, - PIF_SPACE (Wrapper->WrapId, Pif, D0F0xE4_PIF_0012_ADDRESS), - D0F0xE4_PIF_0012.Value, - FALSE, - Pcie - ); - PcieRegisterWrite ( - Wrapper, - PIF_SPACE (Wrapper->WrapId, Pif, D0F0xE4_PIF_0013_ADDRESS), - D0F0xE4_PIF_0013.Value, - FALSE, - Pcie - ); - PcieRegisterWrite ( - Wrapper, - PIF_SPACE (Wrapper->WrapId, Pif, D0F0xE4_PIF_0010_ADDRESS), - D0F0xE4_PIF_0010.Value, - FALSE, - Pcie - ); - } - IDS_HDT_CONSOLE (GNB_TRACE, "PciePifSetPllRampTime Exit\n"); -} - - -/*----------------------------------------------------------------------------------------*/ -/** - * Power down PIFs - * - * - * - * @param[in] Control Power up or Power down control - * @param[in] Wrapper Pointer to wrapper config descriptor - * @param[in] Pcie Pointer to global PCIe configuration - */ -VOID -PciePifPllPowerControl ( - IN PCIE_PIF_POWER_CONTROL Control, - IN PCIe_WRAPPER_CONFIG *Wrapper, - IN PCIe_PLATFORM_CONFIG *Pcie - ) -{ - UINT8 Pif; - UINT8 PllPowerStateInOff; - PllPowerStateInOff = (Control == PowerDownPifs) ? PifPowerStateOff : PifPowerStateL0; - for (Pif = 0; Pif < Wrapper->NumberOfPIFs; Pif++) { - PcieRegisterWriteField ( - Wrapper, - PIF_SPACE (Wrapper->WrapId, Pif, D0F0xE4_PIF_0012_ADDRESS), - D0F0xE4_PIF_0012_PllPowerStateInOff_OFFSET, - D0F0xE4_PIF_0012_PllPowerStateInOff_WIDTH, - PllPowerStateInOff, - FALSE, - Pcie - ); - PcieRegisterWriteField ( - Wrapper, - PIF_SPACE (Wrapper->WrapId, Pif, D0F0xE4_PIF_0013_ADDRESS), - D0F0xE4_PIF_0013_PllPowerStateInOff_OFFSET, - D0F0xE4_PIF_0013_PllPowerStateInOff_WIDTH, - PllPowerStateInOff, - FALSE, - Pcie - ); - } -} - - -/*----------------------------------------------------------------------------------------*/ -/** - * Power down PIFs - * - * - * - * @param[in] Control Power up/Down control - * @param[in] Wrapper Pointer to wrapper config descriptor - * @param[in] Pcie Pointer to global PCIe configuration - */ -VOID -PciePifFullPowerStateControl ( - IN PCIE_PIF_POWER_CONTROL Control, - IN PCIe_WRAPPER_CONFIG *Wrapper, - IN PCIe_PLATFORM_CONFIG *Pcie - ) -{ - UINT8 Pif; - D0F0xE4_PIF_0012_STRUCT D0F0xE4_PIF_0012; - D0F0xE4_PIF_0013_STRUCT D0F0xE4_PIF_0013; - for (Pif = 0; Pif < Wrapper->NumberOfPIFs; Pif++) { - D0F0xE4_PIF_0012.Value = PcieRegisterRead ( - Wrapper, - PIF_SPACE (Wrapper->WrapId, Pif, D0F0xE4_PIF_0012_ADDRESS), - Pcie - ); - D0F0xE4_PIF_0013.Value = PcieRegisterRead ( - Wrapper, - PIF_SPACE (Wrapper->WrapId, Pif, D0F0xE4_PIF_0013_ADDRESS), - Pcie - ); - if (Control == PowerDownPifs) { - D0F0xE4_PIF_0012.Field.PllPowerStateInOff = PifPowerStateOff; - D0F0xE4_PIF_0012.Field.PllPowerStateInTxs2 = PifPowerStateOff; - D0F0xE4_PIF_0012.Field.TxPowerStateInTxs2 = PifPowerStateOff; - D0F0xE4_PIF_0012.Field.RxPowerStateInRxs2 = PifPowerStateOff; - D0F0xE4_PIF_0013.Field.PllPowerStateInOff = PifPowerStateOff; - D0F0xE4_PIF_0013.Field.PllPowerStateInTxs2 = PifPowerStateOff; - D0F0xE4_PIF_0013.Field.TxPowerStateInTxs2 = PifPowerStateOff; - D0F0xE4_PIF_0013.Field.RxPowerStateInRxs2 = PifPowerStateOff; - } else { - D0F0xE4_PIF_0012.Field.PllPowerStateInOff = PifPowerStateLS2; - D0F0xE4_PIF_0012.Field.PllPowerStateInTxs2 = PifPowerStateLS2; - D0F0xE4_PIF_0012.Field.TxPowerStateInTxs2 = PifPowerStateL0; - D0F0xE4_PIF_0012.Field.RxPowerStateInRxs2 = PifPowerStateL0; - D0F0xE4_PIF_0013.Field.PllPowerStateInOff = PifPowerStateLS2; - D0F0xE4_PIF_0013.Field.PllPowerStateInTxs2 = PifPowerStateLS2; - D0F0xE4_PIF_0013.Field.TxPowerStateInTxs2 = PifPowerStateL0; - D0F0xE4_PIF_0013.Field.RxPowerStateInRxs2 = PifPowerStateL0; - } - PcieRegisterWrite ( - Wrapper, - PIF_SPACE (Wrapper->WrapId, Pif, D0F0xE4_PIF_0012_ADDRESS), - D0F0xE4_PIF_0012.Value, - FALSE, - Pcie - ); - PcieRegisterWrite ( - Wrapper, - PIF_SPACE (Wrapper->WrapId, Pif, D0F0xE4_PIF_0013_ADDRESS), - D0F0xE4_PIF_0013.Value, - FALSE, - Pcie - ); - } -} diff --git a/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieInitLibV1/PciePifServices.h b/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieInitLibV1/PciePifServices.h deleted file mode 100644 index 2089976b82..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieInitLibV1/PciePifServices.h +++ /dev/null @@ -1,120 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * PCIe PIF initialization routine - * - * - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: GNB - * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $ - * - */ -/* -***************************************************************************** -* -* Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* *************************************************************************** -* -*/ - -#ifndef _PCIEPIFSERVICES_H_ -#define _PCIEPIFSERVICES_H_ - -VOID -PciePifApplyGanging ( - IN PCIe_WRAPPER_CONFIG *Wrapper, - IN PCIe_PLATFORM_CONFIG *Pcie - ); - -VOID -PciePifPllPowerDown ( - IN UINT32 LaneBitmap, - IN PCIe_WRAPPER_CONFIG *Wrapper, - IN PCIe_PLATFORM_CONFIG *Pcie - ); - -VOID -PciePifPllInitForDdi ( - IN PCIe_WRAPPER_CONFIG *Wrapper, - IN PCIe_PLATFORM_CONFIG *Pcie - ); - -VOID -PciePollPifForCompeletion ( - IN PCIe_WRAPPER_CONFIG *Wrapper, - IN PCIe_PLATFORM_CONFIG *Pcie - ); - -VOID -PciePifDisableFifoReset ( - IN PCIe_WRAPPER_CONFIG *Wrapper, - IN PCIe_PLATFORM_CONFIG *Pcie - ); - -VOID -PciePifSetLs2ExitTime ( - IN PCIe_WRAPPER_CONFIG *Wrapper, - IN PCIe_PLATFORM_CONFIG *Pcie - ); - -VOID -PciePifSetPllModeForL1 ( - IN UINT32 LaneBitmap, - IN PCIe_WRAPPER_CONFIG *Wrapper, - IN PCIe_PLATFORM_CONFIG *Pcie - ); - -VOID -PciePifSetRxDetectPowerMode ( - IN PCIe_WRAPPER_CONFIG *Wrapper, - IN PCIe_PLATFORM_CONFIG *Pcie - ); - -VOID -PciePifSetPllRampTime ( - IN PCIE_PLL_RAMPUP_TIME Rampup, - IN PCIe_WRAPPER_CONFIG *Wrapper, - IN PCIe_PLATFORM_CONFIG *Pcie - ); - -VOID -PciePifPllPowerControl ( - IN PCIE_PIF_POWER_CONTROL Control, - IN PCIe_WRAPPER_CONFIG *Wrapper, - IN PCIe_PLATFORM_CONFIG *Pcie - ); - -VOID -PciePifFullPowerStateControl ( - IN PCIE_PIF_POWER_CONTROL Control, - IN PCIe_WRAPPER_CONFIG *Wrapper, - IN PCIe_PLATFORM_CONFIG *Pcie - ); - -#endif diff --git a/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieInitLibV1/PciePortRegAcc.c b/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieInitLibV1/PciePortRegAcc.c deleted file mode 100644 index 556c7fd40f..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieInitLibV1/PciePortRegAcc.c +++ /dev/null @@ -1,230 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * Supporting services to access PCIe port indirect register - * space. - * - * - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: GNB - * @e \$Revision: 48452 $ @e \$Date: 2011-03-09 12:50:44 +0800 (Wed, 09 Mar 2011) $ - * - */ -/* -***************************************************************************** -* -* Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* *************************************************************************** -* -*/ - -/*---------------------------------------------------------------------------------------- - * M O D U L E S U S E D - *---------------------------------------------------------------------------------------- - */ -#include "AGESA.h" -#include "Ids.h" -#include "Gnb.h" -#include "GnbPcie.h" -#include "GnbPcieFamServices.h" -#include "GnbCommonLib.h" -#include "PciePortRegAcc.h" -#include "Filecode.h" -#define FILECODE PROC_GNB_MODULES_GNBPCIEINITLIBV1_PCIEPORTREGACC_FILECODE -/*---------------------------------------------------------------------------------------- - * D E F I N I T I O N S A N D M A C R O S - *---------------------------------------------------------------------------------------- - */ - - -/*---------------------------------------------------------------------------------------- - * T Y P E D E F S A N D S T R U C T U R E S - *---------------------------------------------------------------------------------------- - */ - - -/*---------------------------------------------------------------------------------------- - * P R O T O T Y P E S O F L O C A L F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ - - -/*----------------------------------------------------------------------------------------*/ -/** - * Read PCIe port indirect register. - * - * Support for unify register access through index/data pair on PCIe port - * - * @param[in] Engine Pointer to Engine descriptor for this port - * @param[in] Address Register address - * @param[in] Pcie Pointer to internal configuration data area - * @retval Register Value - */ - -UINT32 -PciePortRegisterRead ( - IN PCIe_ENGINE_CONFIG *Engine, - IN UINT16 Address, - IN PCIe_PLATFORM_CONFIG *Pcie - ) -{ - UINT32 Value; - GnbLibPciWrite (Engine->Type.Port.Address.AddressValue | 0xE0, AccessWidth32, &Address, GnbLibGetHeader (Pcie)); - GnbLibPciRead (Engine->Type.Port.Address.AddressValue | 0xE4, AccessWidth32, &Value, GnbLibGetHeader (Pcie)); - return Value; -} - -/*----------------------------------------------------------------------------------------*/ -/** - * Write PCIe Port Indirect register. - * - * Support for unify register access through index/data pair on GNB - * - * @param[in] Engine Pointer to Engine descriptor for this port - * @param[in] Address Register address - * @param[in] Value New register value - * @param[in] S3Save Save for S3 flag - * @param[in] Pcie Pointer to internal configuration data area - */ -VOID -PciePortRegisterWrite ( - IN PCIe_ENGINE_CONFIG *Engine, - IN UINT16 Address, - IN UINT32 Value, - IN BOOLEAN S3Save, - IN PCIe_PLATFORM_CONFIG *Pcie - ) -{ - ASSERT (S3Save == TRUE || S3Save == FALSE); - - IDS_HDT_CONSOLE (PCIE_PORTREG_TRACE, " *WR PCIEIND_P (%d:%d:%d):0x%04x = 0x%08x\n", - Engine->Type.Port.Address.Address.Bus, - Engine->Type.Port.Address.Address.Device, - Engine->Type.Port.Address.Address.Function, - Address, - Value - ); - GnbLibPciWrite (Engine->Type.Port.Address.AddressValue | 0xE0, S3Save ? AccessS3SaveWidth32 : AccessWidth32, &Address, GnbLibGetHeader (Pcie)); - GnbLibPciWrite (Engine->Type.Port.Address.AddressValue | 0xE4, S3Save ? AccessS3SaveWidth32 : AccessWidth32, &Value, GnbLibGetHeader (Pcie)); -} - -/*----------------------------------------------------------------------------------------*/ -/** - * Write PCIe Port Indirect register field. - * - * Support for unify register access through index/data pair on GNB - * - * @param[in] Engine Pointer to Engine descriptor for this port - * @param[in] Address Register address - * @param[in] FieldOffset Field offset - * @param[in] FieldWidth Field width - * @param[in] S3Save Save for S3 flag - * @param[in] Value New register value - * @param[in] Pcie Pointer to internal configuration data area - */ - -VOID -PciePortRegisterWriteField ( - IN PCIe_ENGINE_CONFIG *Engine, - IN UINT16 Address, - IN UINT8 FieldOffset, - IN UINT8 FieldWidth, - IN UINT32 Value, - IN BOOLEAN S3Save, - IN PCIe_PLATFORM_CONFIG *Pcie - ) -{ - UINT32 Data; - UINT32 Mask; - Data = PciePortRegisterRead (Engine, Address, Pcie); - Mask = (1 << FieldWidth) - 1; - Value &= Mask; - Data &= (~(Mask << FieldOffset)); - PciePortRegisterWrite (Engine, Address, Data | (Value << FieldOffset), S3Save, Pcie); -} - -/*----------------------------------------------------------------------------------------*/ -/** - * Write PCIe Port Indirect register field. - * - * Support for unify register access through index/data pair on GNB - * - * @param[in] Engine Pointer to Engine descriptor for this port - * @param[in] Address Register address - * @param[in] FieldOffset Field offset - * @param[in] FieldWidth Field width - * @param[in] Pcie Pointer to internal configuration data area - * @retval Register Field Value. - */ - -UINT32 -PciePortRegisterReadField ( - IN PCIe_ENGINE_CONFIG *Engine, - IN UINT16 Address, - IN UINT8 FieldOffset, - IN UINT8 FieldWidth, - IN PCIe_PLATFORM_CONFIG *Pcie - ) -{ - UINT32 Value; - Value = PciePortRegisterRead (Engine, Address, Pcie); - Value = (Value >> FieldOffset) & ((1 << FieldWidth) - 1); - return Value; -} - -/*----------------------------------------------------------------------------------------*/ -/** - * Read/Modify/Write PCIe port register. - * - * Support for unify register access through index/data pair on GNB - * - * @param[in] Engine Pointer to Engine descriptor for this port - * @param[in] Address Register address - * @param[in] AndMask Value & (~AndMask) - * @param[in] OrMask Value | OrMask - * @param[in] S3Save Save register for S3 (True/False) - * @param[in] Pcie Pointer to global PCIe configuration - */ - -VOID -PciePortRegisterRMW ( - IN PCIe_ENGINE_CONFIG *Engine, - IN UINT16 Address, - IN UINT32 AndMask, - IN UINT32 OrMask, - IN BOOLEAN S3Save, - IN PCIe_PLATFORM_CONFIG *Pcie - ) -{ - UINT32 Value; - Value = PciePortRegisterRead (Engine, Address, Pcie); - Value = (Value & (~AndMask)) | OrMask; - PciePortRegisterWrite (Engine, Address, Value, S3Save, Pcie); -} - diff --git a/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieInitLibV1/PciePortRegAcc.h b/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieInitLibV1/PciePortRegAcc.h deleted file mode 100644 index 2a593c83a4..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieInitLibV1/PciePortRegAcc.h +++ /dev/null @@ -1,94 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * Supporting services to access PCIe port indirect register space. - * - * - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: GNB - * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $ - * - */ -/* -***************************************************************************** -* -* Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* *************************************************************************** -* -*/ -#ifndef _PCIEPORTREGACC_H_ -#define _PCIEPORTREGACC_H_ - -UINT32 -PciePortRegisterRead ( - IN PCIe_ENGINE_CONFIG *Engine, - IN UINT16 Address, - IN PCIe_PLATFORM_CONFIG *Pcie - ); - -VOID -PciePortRegisterWrite ( - IN PCIe_ENGINE_CONFIG *Engine, - IN UINT16 Address, - IN UINT32 Value, - IN BOOLEAN S3Save, - IN PCIe_PLATFORM_CONFIG *Pcie - ); - -VOID -PciePortRegisterWriteField ( - IN PCIe_ENGINE_CONFIG *Engine, - IN UINT16 Address, - IN UINT8 FieldOffset, - IN UINT8 FieldWidth, - IN UINT32 Value, - IN BOOLEAN S3Save, - IN PCIe_PLATFORM_CONFIG *Pcie - ); - -UINT32 -PciePortRegisterReadField ( - IN PCIe_ENGINE_CONFIG *Engine, - IN UINT16 Address, - IN UINT8 FieldOffset, - IN UINT8 FieldWidth, - IN PCIe_PLATFORM_CONFIG *Pcie - ); - -VOID -PciePortRegisterRMW ( - IN PCIe_ENGINE_CONFIG *Engine, - IN UINT16 Address, - IN UINT32 AndMask, - IN UINT32 OrMask, - IN BOOLEAN S3Save, - IN PCIe_PLATFORM_CONFIG *Pcie - ); - -#endif diff --git a/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieInitLibV1/PciePortServices.c b/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieInitLibV1/PciePortServices.c deleted file mode 100644 index 6f5d34ee39..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieInitLibV1/PciePortServices.c +++ /dev/null @@ -1,511 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * PCIe port initialization service procedure - * - * - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: GNB - * @e \$Revision: 49532 $ @e \$Date: 2011-03-25 02:54:43 +0800 (Fri, 25 Mar 2011) $ - * - */ -/* -***************************************************************************** -* -* Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* *************************************************************************** -* -*/ - -/*---------------------------------------------------------------------------------------- - * M O D U L E S U S E D - *---------------------------------------------------------------------------------------- - */ -#include "AGESA.h" -#include "Ids.h" -#include "amdlib.h" -#include "Gnb.h" -#include "GnbPcie.h" -#include "GnbSbLib.h" -#include "GnbCommonLib.h" -#include "GnbPcieConfig.h" -#include "GnbPcieInitLibV1.h" -#include "GnbRegistersLN.h" -#include "Filecode.h" -#define FILECODE PROC_GNB_MODULES_GNBPCIEINITLIBV1_PCIEPORTSERVICES_FILECODE -/*---------------------------------------------------------------------------------------- - * D E F I N I T I O N S A N D M A C R O S - *---------------------------------------------------------------------------------------- - */ - - -/*---------------------------------------------------------------------------------------- - * T Y P E D E F S A N D S T R U C T U R E S - *---------------------------------------------------------------------------------------- - */ - - -/*---------------------------------------------------------------------------------------- - * P R O T O T Y P E S O F L O C A L F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ - -/*----------------------------------------------------------------------------------------*/ -/** - * Set completion timeout - * - * - * - * @param[in] Engine Pointer to engine config descriptor - * @param[in] Pcie Pointer to global PCIe configuration - * - */ - -VOID -PcieCompletionTimeout ( - IN PCIe_ENGINE_CONFIG *Engine, - IN PCIe_PLATFORM_CONFIG *Pcie - ) -{ - GnbLibPciRMW ( - Engine->Type.Port.Address.AddressValue | DxF0x80_ADDRESS, - AccessWidth32, - 0xffffffff, - 0x6 << DxF0x80_CplTimeoutValue_OFFSET, - GnbLibGetHeader (Pcie) - ); - if (Engine->Type.Port.PortData.LinkHotplug != HotplugDisabled) { - PciePortRegisterWriteField ( - Engine, - DxF0xE4_x20_ADDRESS, - DxF0xE4_x20_TxFlushTlpDis_OFFSET, - DxF0xE4_x20_TxFlushTlpDis_WIDTH, - 0x0, - TRUE, - Pcie - ); - } -} - -/*----------------------------------------------------------------------------------------*/ -/** - * Init hotplug port - * - * - * - * @param[in] Engine Pointer to engine config descriptor - * @param[in] Pcie Pointer to global PCIe configuration - * - */ - -VOID -PcieLinkInitHotplug ( - IN PCIe_ENGINE_CONFIG *Engine, - IN PCIe_PLATFORM_CONFIG *Pcie - ) -{ - DxF0xE4_xB5_STRUCT DxF0xE4_xB5; - if ((Engine->Type.Port.PortData.LinkHotplug == HotplugEnhanced) || (Engine->Type.Port.PortData.LinkHotplug == HotplugInboard)) { - DxF0xE4_xB5.Value = PciePortRegisterRead (Engine, DxF0xE4_xB5_ADDRESS, Pcie); - DxF0xE4_xB5.Field.LcEhpRxPhyCmd = 0x3; - DxF0xE4_xB5.Field.LcEhpTxPhyCmd = 0x3; - DxF0xE4_xB5.Field.LcEnhancedHotPlugEn = 0x1; - PciePortRegisterWrite ( - Engine, - DxF0xE4_xB5_ADDRESS, - DxF0xE4_xB5.Value, - TRUE, - Pcie - ); - PcieRegisterWriteField ( - PcieConfigGetParentWrapper (Engine), - CORE_SPACE (Engine->Type.Port.CoreId, 0x10), - 1, - 3, - 0x5, - TRUE, - Pcie - ); - PcieRegisterWriteField ( - PcieConfigGetParentWrapper (Engine), - WRAP_SPACE (PcieConfigGetParentWrapper (Engine)->WrapId, D0F0xE4_WRAP_8011_ADDRESS), - D0F0xE4_WRAP_8011_RcvrDetClkEnable_OFFSET, - D0F0xE4_WRAP_8011_RcvrDetClkEnable_WIDTH, - 0x1, - TRUE, - Pcie - ); - } - if (Engine->Type.Port.PortData.LinkHotplug != HotplugDisabled) { - GnbLibPciRMW ( - Engine->Type.Port.Address.AddressValue | DxF0x6C_ADDRESS, - AccessS3SaveWidth32, - 0xffffffff, - 1 << DxF0x6C_HotplugCapable_OFFSET, - GnbLibGetHeader (Pcie) - ); - PciePortRegisterWriteField ( - Engine, - DxF0xE4_x20_ADDRESS, - DxF0xE4_x20_TxFlushTlpDis_OFFSET, - DxF0xE4_x20_TxFlushTlpDis_WIDTH, - 0x0, - TRUE, - Pcie - ); - PciePortRegisterWriteField ( - Engine, - DxF0xE4_x70_ADDRESS, - DxF0xE4_x70_RxRcbCplTimeoutMode_OFFSET, - DxF0xE4_x70_RxRcbCplTimeoutMode_WIDTH, - 0x1, - FALSE, - Pcie - ); - } -} - -/*----------------------------------------------------------------------------------------*/ -/** - * Set misc slot capability - * - * - * - * @param[in] Engine Pointer to engine config descriptor - * @param[in] Pcie Pointer to global PCIe configuration - * - */ - -VOID -PcieLinkSetSlotCap ( - IN PCIe_ENGINE_CONFIG *Engine, - IN PCIe_PLATFORM_CONFIG *Pcie - ) -{ - GnbLibPciRMW ( - Engine->Type.Port.Address.AddressValue | DxF0x58_ADDRESS, - AccessWidth32, - 0xffffffff, - 1 << DxF0x58_SlotImplemented_OFFSET, - GnbLibGetHeader (Pcie) - ); - GnbLibPciRMW ( - Engine->Type.Port.Address.AddressValue | DxF0x3C_ADDRESS, - AccessWidth32, - 0xffffffff, - 1 << DxF0x3C_IntPin_OFFSET, - GnbLibGetHeader (Pcie) - ); -} - -/*----------------------------------------------------------------------------------------*/ -/** - * Safe mode to force link advertize Gen1 only capability in TS - * - * - * - * @param[in] Engine Pointer to engine config descriptor - * @param[in] Pcie Pointer to global PCIe configuration - * - */ - -VOID -PcieLinkSafeMode ( - IN PCIe_ENGINE_CONFIG *Engine, - IN PCIe_PLATFORM_CONFIG *Pcie - ) -{ - //Engine->Type.Port.PortData.LinkSpeedCapability = PcieGen1; - PcieSetLinkSpeedCap (PcieGen1, Engine, Pcie); - PciePortRegisterRMW ( - Engine, - DxF0xE4_xA2_ADDRESS, - DxF0xE4_xA2_LcUpconfigureDis_MASK, - (1 << DxF0xE4_xA2_LcUpconfigureDis_OFFSET), - FALSE, - Pcie - ); -} - - -/*----------------------------------------------------------------------------------------*/ -/** - * Set current link speed - * - * - * @param[in] Engine Pointer to engine configuration descriptor - * @param[in] Pcie Pointer to global PCIe configuration - * - */ -VOID -PcieSetLinkWidthCap ( - IN PCIe_ENGINE_CONFIG *Engine, - IN PCIe_PLATFORM_CONFIG *Pcie - ) -{ - PciePortRegisterRMW ( - Engine, - DxF0xE4_xA2_ADDRESS, - DxF0xE4_xA2_LcUpconfigureDis_MASK, - 0, - FALSE, - Pcie - ); -} - -/*----------------------------------------------------------------------------------------*/ -/** - * Set current link speed - * - * - * @param[in] LinkSpeedCapability Link Speed Capability - * @param[in] Engine Pointer to engine configuration descriptor - * @param[in] Pcie Pointer to global PCIe configuration - * - */ -VOID -PcieSetLinkSpeedCap ( - IN PCIE_LINK_SPEED_CAP LinkSpeedCapability, - IN PCIe_ENGINE_CONFIG *Engine, - IN PCIe_PLATFORM_CONFIG *Pcie - ) -{ - DxF0xE4_xA4_STRUCT DxF0xE4_xA4; - DxF0xE4_xC0_STRUCT DxF0xE4_xC0; - DxF0x88_STRUCT DxF0x88; - GnbLibPciRead ( - Engine->Type.Port.Address.AddressValue | DxF0x88_ADDRESS, - AccessWidth32, - &DxF0x88.Value, - GnbLibGetHeader (Pcie) - ); - DxF0xE4_xA4.Value = PciePortRegisterRead ( - Engine, - DxF0xE4_xA4_ADDRESS, - Pcie - ); - DxF0xE4_xC0.Value = PciePortRegisterRead ( - Engine, - DxF0xE4_xC0_ADDRESS, - Pcie - ); - - switch (LinkSpeedCapability) { - case PcieGen2: - DxF0xE4_xA4.Field.LcGen2EnStrap = 0x1; - DxF0xE4_xA4.Field.LcMultUpstreamAutoSpdChngEn = 0x1; - DxF0xE4_xC0.Field.StrapAutoRcSpeedNegotiationDis = 0x0; - DxF0x88.Field.TargetLinkSpeed = 0x2; - DxF0x88.Field.HwAutonomousSpeedDisable = 0x0; - break; - case PcieGen1: - DxF0xE4_xA4.Field.LcGen2EnStrap = 0x0; - DxF0xE4_xA4.Field.LcMultUpstreamAutoSpdChngEn = 0x0; - DxF0xE4_xC0.Field.StrapAutoRcSpeedNegotiationDis = 0x1; - DxF0x88.Field.TargetLinkSpeed = 0x1; - DxF0x88.Field.HwAutonomousSpeedDisable = 0x1; - PcieRegisterWriteField ( - PcieConfigGetParentWrapper (Engine), - WRAP_SPACE (PcieConfigGetParentWrapper (Engine)->WrapId, D0F0xE4_WRAP_0803_ADDRESS + 0x100 * Engine->Type.Port.PortId), - D0F0xE4_WRAP_0803_StrapBifDeemphasisSel_OFFSET, - D0F0xE4_WRAP_0803_StrapBifDeemphasisSel_WIDTH, - 0, - FALSE, - Pcie - ); - break; - default: - ASSERT (FALSE); - break; - } - PciePortRegisterWrite ( - Engine, - DxF0xE4_xA4_ADDRESS, - DxF0xE4_xA4.Value, - FALSE, - Pcie - ); - PciePortRegisterWrite ( - Engine, - DxF0xE4_xC0_ADDRESS, - DxF0xE4_xC0.Value, - FALSE, - Pcie - ); - GnbLibPciWrite ( - Engine->Type.Port.Address.AddressValue | DxF0x88_ADDRESS, - AccessWidth32, - &DxF0x88.Value, - GnbLibGetHeader (Pcie) - ); -} - - -/*----------------------------------------------------------------------------------------*/ -/** - * Force compliance - * - * - * - * @param[in] Engine Pointer to engine config descriptor - * @param[in] Pcie Pointer to global PCIe configuration - * - */ - -VOID -PcieForceCompliance ( - IN PCIe_ENGINE_CONFIG *Engine, - IN PCIe_PLATFORM_CONFIG *Pcie - ) -{ - if (Engine->Type.Port.PortData.LinkSpeedCapability >= PcieGen2) { - GnbLibPciRMW ( - Engine->Type.Port.Address.AddressValue | DxF0x88_ADDRESS, - AccessWidth32, - 0xffffffff, - 0x1 << DxF0x88_EnterCompliance_OFFSET, - GnbLibGetHeader (Pcie) - ); - } else if (Engine->Type.Port.PortData.LinkSpeedCapability == PcieGen1) { - PciePortRegisterWriteField ( - Engine, - DxF0xE4_xC0_ADDRESS, - DxF0xE4_xC0_StrapForceCompliance_OFFSET, - DxF0xE4_xC0_StrapForceCompliance_WIDTH, - 0x1, - FALSE, - Pcie - ); - } -} - -/*----------------------------------------------------------------------------------------*/ -/** - * Set slo power limit - * - * - * - * @param[in] Engine Pointer to engine configuration - * @param[in] Pcie Pointer to PCIe configuration - */ - - -VOID -PcieEnableSlotPowerLimit ( - IN PCIe_ENGINE_CONFIG *Engine, - IN PCIe_PLATFORM_CONFIG *Pcie - ) -{ - ASSERT (Engine->EngineData.EngineType == PciePortEngine); - if (PcieLibIsEngineAllocated (Engine) && Engine->Type.Port.PortData.PortPresent != PortDisabled && !PcieConfigIsSbPcieEngine (Engine)) { - IDS_HDT_CONSOLE (PCIE_MISC, " Enable Slot Power Limit for Port % d\n", Engine->Type.Port.Address.Address.Device); - GnbLibPciIndirectRMW ( - MAKE_SBDFO (0, 0, 0, 0, D0F0x60_ADDRESS), - (D0F0x64_x51_ADDRESS + (Engine->Type.Port.Address.Address.Device - 2) * 2) | IOC_WRITE_ENABLE, - AccessS3SaveWidth32, - 0xffffffff, - 1 << D0F0x64_x51_SetPowEn_OFFSET, - GnbLibGetHeader (Pcie) - ); - } -} - -/*----------------------------------------------------------------------------------------*/ -/** - * Enable ASPM - * - * - * - * @param[in] Engine Pointer to engine config descriptor - * @param[in] Pcie Pointer to global PCIe configuration - * - */ - -VOID -PcieEnableAspm ( - IN PCIe_ENGINE_CONFIG *Engine, - IN PCIe_PLATFORM_CONFIG *Pcie - ) -{ - if (Engine->Type.Port.PortData.LinkAspm != AspmDisabled) { - if (PcieConfigIsSbPcieEngine (Engine)) { - SbPcieLinkAspmControl (Engine, Pcie); - } else { - PcieLinkAspmEnable ( - Engine->Type.Port.Address, - Engine->Type.Port.PortData.LinkAspm, - GnbLibGetHeader (Pcie) - ); - } - } -} - - -UINT8 L1State = 0x1b; -/*----------------------------------------------------------------------------------------*/ -/** - * Poll for link to get into L1 - * - * - * - * @param[in] Engine Pointer to Engine config descriptor - * @param[in] Pcie Pointer to global PCIe configuration - */ -VOID -PciePollLinkForL1Entry ( - IN PCIe_ENGINE_CONFIG *Engine, - IN PCIe_PLATFORM_CONFIG *Pcie - ) -{ - UINT8 LinkHwStateHistory[8]; - do { - PcieUtilGetLinkHwStateHistory (Engine, &LinkHwStateHistory[0], sizeof (LinkHwStateHistory), Pcie); - } while (!PcieUtilSearchArray (LinkHwStateHistory, sizeof (LinkHwStateHistory), &L1State, sizeof (L1State))); -} - -/*----------------------------------------------------------------------------------------*/ -/** - * Poll for link to get into L1 - * - * - * - * @param[in] Engine Pointer to Engine config descriptor - * @param[in] Pcie Pointer to global PCIe configuration - */ -VOID -PciePollLinkForL0Exit ( - IN PCIe_ENGINE_CONFIG *Engine, - IN PCIe_PLATFORM_CONFIG *Pcie - ) -{ - UINT8 LinkHwStateHistory[4]; - do { - PcieUtilGetLinkHwStateHistory (Engine, &LinkHwStateHistory[0], sizeof (LinkHwStateHistory), Pcie); - } while (LinkHwStateHistory[0] != 0x10); -} diff --git a/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieInitLibV1/PciePortServices.h b/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieInitLibV1/PciePortServices.h deleted file mode 100644 index 8b1ac5b3ff..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieInitLibV1/PciePortServices.h +++ /dev/null @@ -1,118 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * PCIe port initialization service procedure - * - * - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: GNB - * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $ - * - */ -/* -***************************************************************************** -* -* Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* *************************************************************************** -* -*/ -#ifndef _PCIEPORTSERVICES_H_ -#define _PCIEPORTSERVICES_H_ - - -VOID -PcieSetLinkSpeedCap ( - IN PCIE_LINK_SPEED_CAP LinkSpeedCapability, - IN PCIe_ENGINE_CONFIG *Engine, - IN PCIe_PLATFORM_CONFIG *Pcie - ); - -VOID -PcieSetLinkWidthCap ( - IN PCIe_ENGINE_CONFIG *Engine, - IN PCIe_PLATFORM_CONFIG *Pcie - ); - -VOID -PcieLinkSafeMode ( - IN PCIe_ENGINE_CONFIG *Engine, - IN PCIe_PLATFORM_CONFIG *Pcie - ); - -VOID -PcieCompletionTimeout ( - IN PCIe_ENGINE_CONFIG *Engine, - IN PCIe_PLATFORM_CONFIG *Pcie - ); - -VOID -PcieLinkSetSlotCap ( - IN PCIe_ENGINE_CONFIG *Engine, - IN PCIe_PLATFORM_CONFIG *Pcie - ); - -VOID -PcieLinkInitHotplug ( - IN PCIe_ENGINE_CONFIG *Engine, - IN PCIe_PLATFORM_CONFIG *Pcie - ); - -VOID -PcieForceCompliance ( - IN PCIe_ENGINE_CONFIG *Engine, - IN PCIe_PLATFORM_CONFIG *Pcie - ); - -VOID -PcieEnableSlotPowerLimit ( - IN PCIe_ENGINE_CONFIG *Engine, - IN PCIe_PLATFORM_CONFIG *Pcie - ); - -VOID -PcieEnableAspm ( - IN PCIe_ENGINE_CONFIG *Engine, - IN PCIe_PLATFORM_CONFIG *Pcie - ); - -VOID -PciePollLinkForL1Entry ( - IN PCIe_ENGINE_CONFIG *Engine, - IN PCIe_PLATFORM_CONFIG *Pcie - ); - -VOID -PciePollLinkForL0Exit ( - IN PCIe_ENGINE_CONFIG *Engine, - IN PCIe_PLATFORM_CONFIG *Pcie - ); - -#endif - - diff --git a/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieInitLibV1/PciePowerMgmt.c b/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieInitLibV1/PciePowerMgmt.c deleted file mode 100644 index cf9d127cb8..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieInitLibV1/PciePowerMgmt.c +++ /dev/null @@ -1,391 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * Power saving features/services - * - * - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: GNB - * @e \$Revision: 49532 $ @e \$Date: 2011-03-25 02:54:43 +0800 (Fri, 25 Mar 2011) $ - * - */ -/* -***************************************************************************** -* -* Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* *************************************************************************** -* -*/ - -/*---------------------------------------------------------------------------------------- - * M O D U L E S U S E D - *---------------------------------------------------------------------------------------- - */ -#include "AGESA.h" -#include "Ids.h" -#include "amdlib.h" -#include "Gnb.h" -#include "GnbPcie.h" -#include "GnbCommonLib.h" -#include "GnbPcieConfig.h" -#include "GnbPcieInitLibV1.h" -#include "GnbRegistersLN.h" -#include "Filecode.h" -#define FILECODE PROC_GNB_MODULES_GNBPCIEINITLIBV1_PCIEPOWERMGMT_FILECODE - -/*---------------------------------------------------------------------------------------- - * D E F I N I T I O N S A N D M A C R O S - *---------------------------------------------------------------------------------------- - */ - - -/*---------------------------------------------------------------------------------------- - * T Y P E D E F S A N D S T R U C T U R E S - *---------------------------------------------------------------------------------------- - */ - - -/*---------------------------------------------------------------------------------------- - * P R O T O T Y P E S O F L O C A L F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ - -/*----------------------------------------------------------------------------------------*/ -/** - * Power down unused lanes and plls - * - * - * @param[in] Wrapper Pointer to wrapper config descriptor - * @param[in] Pcie Pointer to global PCIe configuration - */ - -VOID -PciePwrPowerDownUnusedLanes ( - IN PCIe_WRAPPER_CONFIG *Wrapper, - IN PCIe_PLATFORM_CONFIG *Pcie - ) -{ - UINT32 UnusedLanes; - IDS_HDT_CONSOLE (GNB_TRACE, "PciePwrPowerDownUnusedLanes Enter\n"); - if (Wrapper->Features.PowerOffUnusedLanes != 0) { - UnusedLanes = PcieUtilGetWrapperLaneBitMap (LANE_TYPE_CORE_ALL, LANE_TYPE_PCIE_CORE_ALLOC_ACTIVE, Wrapper); - PcieTopologyLaneControl ( - DisableLanes, - UnusedLanes, - Wrapper, - Pcie - ); - } - if (Wrapper->Features.PowerOffUnusedPlls != 0) { - UnusedLanes = PcieUtilGetWrapperLaneBitMap (LANE_TYPE_PHY_NATIVE_ALL, LANE_TYPE_PCIE_PHY_NATIVE_ALLOC_ACTIVE | LANE_TYPE_DDI_PHY_NATIVE_ACTIVE, Wrapper); - PciePifPllPowerDown ( - UnusedLanes, - Wrapper, - Pcie - ); - } - IDS_HDT_CONSOLE (GNB_TRACE, "PciePwrPowerDownUnusedLanes Exit\n"); -} - - -/*----------------------------------------------------------------------------------------*/ -/** - * Lane bitmam to enable PLL power down in L1 - * - * - * @param[in] PllPowerUpLatency Pointer to wrapper config descriptor - * @param[in] Wrapper Pointer to wrapper config descriptor - * @param[in] Pcie Pointer to global PCIe configuration - * @retval Lane bitmap for which PLL can be powered down in L1 - */ - -UINT32 -PcieLanesToPowerDownPllInL1 ( - IN UINT8 PllPowerUpLatency, - IN PCIe_WRAPPER_CONFIG *Wrapper, - IN PCIe_PLATFORM_CONFIG *Pcie - ) -{ - UINT8 LaneGroupExitLatency [4]; - UINT32 LaneBitmapForPllOffInL1; - PCIe_ENGINE_CONFIG *EngineList; - UINTN Index; - IDS_HDT_CONSOLE (GNB_TRACE, "PcieLanesToPowerDownPllInL1 Enter\n"); - LaneBitmapForPllOffInL1 = 0; - if (PcieUtilGetWrapperLaneBitMap (LANE_TYPE_PCIE_PHY_NATIVE_ALLOC_ACTIVE | LANE_TYPE_PCIE_PHY_NATIVE_HOTPLUG, 0, Wrapper) != 0) { - if (Wrapper->Features.PllOffInL1 != 0) { - LibAmdMemFill (&LaneGroupExitLatency[0], 0xFF, sizeof (LaneGroupExitLatency), GnbLibGetHeader (Pcie)); - EngineList = PcieConfigGetChildEngine (Wrapper); - while (EngineList != NULL) { - PCIe_ASPM_LATENCY_INFO LinkLatencyInfo; - UINT32 ActiveLanesBitmap; - UINT32 HotplugLanesBitmap; - if (EngineList->EngineData.EngineType == PciePortEngine) { - LinkLatencyInfo.MaxL1ExitLatency = 0; - LinkLatencyInfo.MaxL0sExitLatency = 0; - ActiveLanesBitmap = PcieUtilGetEngineLaneBitMap (LANE_TYPE_PCIE_PHY_NATIVE_ALLOC_ACTIVE, 0, EngineList); - HotplugLanesBitmap = PcieUtilGetEngineLaneBitMap (LANE_TYPE_PCIE_PHY_NATIVE_HOTPLUG, 0, EngineList); - if (ActiveLanesBitmap != 0 && HotplugLanesBitmap == 0 && !PcieConfigIsSbPcieEngine (EngineList)) { - PcieAspmGetMaxExitLatency (EngineList->Type.Port.Address, &LinkLatencyInfo, GnbLibGetHeader (Pcie)); - } - if (HotplugLanesBitmap != 0 || PcieConfigIsSbPcieEngine (EngineList)) { - LinkLatencyInfo.MaxL1ExitLatency = 0xff; - } - IDS_HDT_CONSOLE (GNB_TRACE, " Engine %d Active Lanes 0x%x, Hotplug Lanes 0x%x\n", EngineList->Type.Port.NativeDevNumber, ActiveLanesBitmap, HotplugLanesBitmap); - for (Index = 0; Index < 4; Index++) { - if ((ActiveLanesBitmap & (0xF << (Index * 4))) != 0) { - if (LaneGroupExitLatency [Index] > LinkLatencyInfo.MaxL1ExitLatency) { - IDS_HDT_CONSOLE (GNB_TRACE, " Index %d Latency %d\n", Index, LinkLatencyInfo.MaxL1ExitLatency); - LaneGroupExitLatency [Index] = LinkLatencyInfo.MaxL1ExitLatency; - } - } - } - } - EngineList = PcieLibGetNextDescriptor (EngineList); - } - LaneBitmapForPllOffInL1 = 0; - for (Index = 0; Index < 4; Index++) { - IDS_HDT_CONSOLE (GNB_TRACE, " Index %d Final Latency %d\n", Index, LaneGroupExitLatency[Index]); - if (LaneGroupExitLatency[Index] > PllPowerUpLatency) { - LaneBitmapForPllOffInL1 |= (0xF << (Index * 4)); - } - } - } - } - IDS_HDT_CONSOLE (GNB_TRACE, " Lane bitmap %04x\n", LaneBitmapForPllOffInL1); - IDS_HDT_CONSOLE (GNB_TRACE, "PcieLanesToPowerDownPllInL1 Exit\n"); - return LaneBitmapForPllOffInL1; -} - -/*----------------------------------------------------------------------------------------*/ -/** - * Auto-Power Down electrical Idle detector - * - * - * @param[in] Wrapper Pointer to wrapper config descriptor - * @param[in] Pcie Pointer to global PCIe configuration - */ - -VOID -PciePwrAutoPowerDownElectricalIdleDetector ( - IN PCIe_WRAPPER_CONFIG *Wrapper, - IN PCIe_PLATFORM_CONFIG *Pcie - ) -{ - UINT8 Pif; - IDS_HDT_CONSOLE (GNB_TRACE, "PciePwrAutoPowerDownElectricalIdleDetector Enter\n"); - for (Pif = 0; Pif < Wrapper->NumberOfPIFs; Pif++) { - PcieRegisterWriteField ( - Wrapper, - PIF_SPACE (Wrapper->WrapId, Pif, D0F0xE4_PIF_0010_ADDRESS), - D0F0xE4_PIF_0010_EiDetCycleMode_OFFSET, - D0F0xE4_PIF_0010_EiDetCycleMode_WIDTH, - 0x0, - TRUE, - Pcie - ); - - PcieRegisterWriteField ( - Wrapper, - PIF_SPACE (Wrapper->WrapId, Pif, D0F0xE4_PIF_0010_ADDRESS), - D0F0xE4_PIF_0010_EiCycleOffTime_OFFSET, - D0F0xE4_PIF_0010_EiCycleOffTime_WIDTH, - 0x2, - TRUE, - Pcie - ); - - PcieRegisterWriteField ( - Wrapper, - PIF_SPACE (Wrapper->WrapId, Pif, D0F0xE4_PIF_0010_ADDRESS), - D0F0xE4_PIF_0010_EiDetCycleMode_OFFSET, - D0F0xE4_PIF_0010_EiDetCycleMode_WIDTH, - 0x1, - TRUE, - Pcie - ); - } - IDS_HDT_CONSOLE (GNB_TRACE, "PciePwrAutoPowerDownElectricalIdleDetector Exit\n"); -} - -/*----------------------------------------------------------------------------------------*/ -/** - * Clock gating - * - * - * - * @param[in] Wrapper Pointer to wrapper config descriptor - * @param[in] Pcie Pointer to global PCIe configuration - */ - -VOID -PciePwrClockGating ( - IN PCIe_WRAPPER_CONFIG *Wrapper, - IN PCIe_PLATFORM_CONFIG *Pcie - ) -{ - D0F0xE4_WRAP_8011_STRUCT D0F0xE4_WRAP_8011; - D0F0xE4_WRAP_8012_STRUCT D0F0xE4_WRAP_8012; - D0F0xE4_WRAP_8014_STRUCT D0F0xE4_WRAP_8014; - D0F0xE4_WRAP_8015_STRUCT D0F0xE4_WRAP_8015; - D0F0xE4_WRAP_8016_STRUCT D0F0xE4_WRAP_8016; - UINT8 CoreId; - IDS_HDT_CONSOLE (GNB_TRACE, "PciePwrClockGating Enter\n"); - D0F0xE4_WRAP_8014.Value = PcieRegisterRead ( - Wrapper, - WRAP_SPACE (Wrapper->WrapId, D0F0xE4_WRAP_8014_ADDRESS), - Pcie - ); - D0F0xE4_WRAP_8015.Value = PcieRegisterRead ( - Wrapper, - WRAP_SPACE (Wrapper->WrapId, D0F0xE4_WRAP_8015_ADDRESS), - Pcie - ); - - D0F0xE4_WRAP_8012.Value = PcieRegisterRead ( - Wrapper, - WRAP_SPACE (Wrapper->WrapId, D0F0xE4_WRAP_8012_ADDRESS), - Pcie - ); - - D0F0xE4_WRAP_8011.Value = PcieRegisterRead ( - Wrapper, - WRAP_SPACE (Wrapper->WrapId, D0F0xE4_WRAP_8011_ADDRESS), - Pcie - ); - - if (Wrapper->Features.ClkGating == 0x1) { - D0F0xE4_WRAP_8014.Field.TxclkPermGateEnable = 0x1; - D0F0xE4_WRAP_8014.Field.TxclkPrbsGateEnable = 0x1; - - D0F0xE4_WRAP_8014.Field.PcieGatePifA1xEnable = 0x1; - D0F0xE4_WRAP_8014.Field.PcieGatePifB1xEnable = 0x1; - D0F0xE4_WRAP_8014.Field.PcieGatePifC1xEnable = 0x1; - D0F0xE4_WRAP_8014.Field.PcieGatePifD1xEnable = 0x1; - - D0F0xE4_WRAP_8014.Field.PcieGatePifA2p5xEnable = 0x1; - D0F0xE4_WRAP_8014.Field.PcieGatePifB2p5xEnable = 0x1; - D0F0xE4_WRAP_8014.Field.PcieGatePifC2p5xEnable = 0x1; - D0F0xE4_WRAP_8014.Field.PcieGatePifD2p5xEnable = 0x1; - - - D0F0xE4_WRAP_8011.Field.TxclkDynGateEnable = 0x1; - D0F0xE4_WRAP_8011.Field.TxclkRegsGateEnable = 0x1; - D0F0xE4_WRAP_8011.Field.TxclkLcntGateEnable = 0x1; - D0F0xE4_WRAP_8011.Field.RcvrDetClkEnable = 0x1; - D0F0xE4_WRAP_8011.Field.TxclkPermGateEven = 0x1; - D0F0xE4_WRAP_8011.Field.TxclkDynGateLatency = 0x3f; - D0F0xE4_WRAP_8011.Field.TxclkRegsGateLatency = 0x3f; - D0F0xE4_WRAP_8011.Field.TxclkPermGateLatency = 0x3f; - - D0F0xE4_WRAP_8012.Field.Pif2p5xIdleResumeLatency = 0x7; - D0F0xE4_WRAP_8012.Field.Pif2p5xIdleGateEnable = 0x1; - D0F0xE4_WRAP_8012.Field.Pif2p5xIdleGateLatency = 0x1; - D0F0xE4_WRAP_8012.Field.Pif1xIdleResumeLatency = 0x7; - D0F0xE4_WRAP_8012.Field.Pif1xIdleGateEnable = 0x1; - D0F0xE4_WRAP_8012.Field.Pif1xIdleGateLatency = 0x1; - - D0F0xE4_WRAP_8015.Field.RefclkBphyGateEnable = 0x1; - D0F0xE4_WRAP_8015.Field.RefclkBphyGateLatency = 0x0; - D0F0xE4_WRAP_8015.Field.RefclkRegsGateEnable = 0x1; - D0F0xE4_WRAP_8015.Field.RefclkRegsGateLatency = 0x3f; - - D0F0xE4_WRAP_8014.Field.DdiGateDigAEnable = 0x1; - D0F0xE4_WRAP_8014.Field.DdiGateDigBEnable = 0x1; - D0F0xE4_WRAP_8014.Field.DdiGatePifA1xEnable = 0x1; - D0F0xE4_WRAP_8014.Field.DdiGatePifB1xEnable = 0x1; - D0F0xE4_WRAP_8014.Field.DdiGatePifC1xEnable = 0x1; - D0F0xE4_WRAP_8014.Field.DdiGatePifD1xEnable = 0x1; - D0F0xE4_WRAP_8014.Field.DdiGatePifA2p5xEnable = 0x1; - D0F0xE4_WRAP_8014.Field.DdiGatePifB2p5xEnable = 0x1; - D0F0xE4_WRAP_8014.Field.DdiGatePifC2p5xEnable = 0x1; - D0F0xE4_WRAP_8014.Field.DdiGatePifD2p5xEnable = 0x1; - } - if (Wrapper->Features.TxclkGatingPllPowerDown == 0x1) { - D0F0xE4_WRAP_8014.Field.TxclkPermGateOnlyWhenPllPwrDn = 0x1; - } - PcieRegisterWrite ( - Wrapper, - WRAP_SPACE (Wrapper->WrapId, D0F0xE4_WRAP_8014_ADDRESS), - D0F0xE4_WRAP_8014.Value, - TRUE, - Pcie - ); - PcieRegisterWrite ( - Wrapper, - WRAP_SPACE (Wrapper->WrapId, D0F0xE4_WRAP_8015_ADDRESS), - D0F0xE4_WRAP_8015.Value, - TRUE, - Pcie - ); - PcieRegisterWrite ( - Wrapper, - WRAP_SPACE (Wrapper->WrapId, D0F0xE4_WRAP_8012_ADDRESS), - D0F0xE4_WRAP_8012.Value, - TRUE, - Pcie - ); - PcieRegisterWrite ( - Wrapper, - WRAP_SPACE (Wrapper->WrapId, D0F0xE4_WRAP_8011_ADDRESS), - D0F0xE4_WRAP_8011.Value, - TRUE, - Pcie - ); - for (CoreId = Wrapper->StartPcieCoreId; CoreId <= Wrapper->EndPcieCoreId; CoreId++) { - PcieRegisterWriteField ( - Wrapper, - CORE_SPACE (CoreId, D0F0xE4_CORE_0011_ADDRESS), - D0F0xE4_CORE_0011_DynClkLatency_OFFSET, - D0F0xE4_CORE_0011_DynClkLatency_WIDTH, - 0xf, - TRUE, - Pcie - ); - } - if (Wrapper->Features.LclkGating == 0x1) { - D0F0xE4_WRAP_8016.Value = PcieRegisterRead ( - Wrapper, - WRAP_SPACE (Wrapper->WrapId, D0F0xE4_WRAP_8016_ADDRESS), - Pcie - ); - D0F0xE4_WRAP_8016.Field.LclkDynGateEnable = 0x1; - D0F0xE4_WRAP_8016.Field.LclkGateFree = 0x1; - PcieRegisterWrite ( - Wrapper, - WRAP_SPACE (Wrapper->WrapId, D0F0xE4_WRAP_8016_ADDRESS), - D0F0xE4_WRAP_8016.Value, - TRUE, - Pcie - ); - } - IDS_HDT_CONSOLE (GNB_TRACE, "PciePwrClockGating Exit\n"); -} - - diff --git a/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieInitLibV1/PciePowerMgmt.h b/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieInitLibV1/PciePowerMgmt.h deleted file mode 100644 index 5dd3b0c74f..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieInitLibV1/PciePowerMgmt.h +++ /dev/null @@ -1,74 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * Power saving features/services - * - * - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: GNB - * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $ - * - */ -/* -***************************************************************************** -* -* Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* *************************************************************************** -* -*/ -#ifndef _PCIEPOWERSAVINGFEATURES_H_ -#define _PCIEPOWERSAVINGFEATURES_H_ - - -VOID -PciePwrPowerDownUnusedLanes ( - IN PCIe_WRAPPER_CONFIG *Wrapper, - IN PCIe_PLATFORM_CONFIG *Pcie - ); - -UINT32 -PcieLanesToPowerDownPllInL1 ( - IN UINT8 PllPowerUpLatency, - IN PCIe_WRAPPER_CONFIG *Wrapper, - IN PCIe_PLATFORM_CONFIG *Pcie - ); - -VOID -PciePwrAutoPowerDownElectricalIdleDetector ( - IN PCIe_WRAPPER_CONFIG *Wrapper, - IN PCIe_PLATFORM_CONFIG *Pcie - ); - -VOID -PciePwrClockGating ( - IN PCIe_WRAPPER_CONFIG *Wrapper, - IN PCIe_PLATFORM_CONFIG *Pcie - ); - -#endif diff --git a/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieInitLibV1/PcieSiliconServices.c b/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieInitLibV1/PcieSiliconServices.c deleted file mode 100644 index 1d0d0bade7..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieInitLibV1/PcieSiliconServices.c +++ /dev/null @@ -1,254 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * Family specific PCIe complex initialization services - * - * - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: GNB - * @e \$Revision: 49532 $ @e \$Date: 2011-03-25 02:54:43 +0800 (Fri, 25 Mar 2011) $ - * - */ -/* -***************************************************************************** -* -* Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* *************************************************************************** -* -*/ -/*---------------------------------------------------------------------------------------- - * M O D U L E S U S E D - *---------------------------------------------------------------------------------------- - */ -#include "AGESA.h" -#include "Ids.h" -#include "amdlib.h" -#include "Gnb.h" -#include "GnbPcie.h" -#include "GnbCommonLib.h" -#include "GnbPcieConfig.h" -#include "GnbPcieInitLibV1.h" -#include "GnbRegistersLN.h" -#include "Filecode.h" -#define FILECODE PROC_GNB_MODULES_GNBPCIEINITLIBV1_PCIESILICONSERVICES_FILECODE -/*---------------------------------------------------------------------------------------- - * D E F I N I T I O N S A N D M A C R O S - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------- - * T Y P E D E F S A N D S T R U C T U R E S - *---------------------------------------------------------------------------------------- - */ - - -/*---------------------------------------------------------------------------------------- - * P R O T O T Y P E S O F L O C A L F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ - - -/*----------------------------------------------------------------------------------------*/ -/** - * Get Gen1 voltage Index - * - * - * - * - * @param[in] StdHeader Standard configuration header - */ -UINT8 -PcieSiliconGetGen1VoltageIndex ( - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - UINT8 Index; - UINT8 Gen1VidIndex; - UINT8 SclkVidArray[4]; - GnbLibPciRead ( - MAKE_SBDFO ( 0, 0, 0x18, 3, D18F3x15C_ADDRESS), - AccessWidth32, - &SclkVidArray[0], - StdHeader - ); - Gen1VidIndex = 0; - for (Index = 0; Index < 4; Index++) { - if (SclkVidArray[Index] > SclkVidArray[Gen1VidIndex]) { - Gen1VidIndex = Index; - } - } - return Gen1VidIndex; -} - -/*----------------------------------------------------------------------------------------*/ -/** - * Request Pcie voltage change - * - * - * - * @param[in] VidIndex The request VID index - * @param[in] StdHeader Standard configuration header - */ -VOID -PcieSiliconRequestVoltage ( - IN UINT8 VidIndex, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - D0F0x64_x6A_STRUCT D0F0x64_x6A; - D0F0x64_x6B_STRUCT D0F0x64_x6B; - - //Enable voltage client - GnbLibPciIndirectRead ( - MAKE_SBDFO (0, 0, 0, 0, D0F0x60_ADDRESS), - D0F0x64_x6A_ADDRESS | IOC_WRITE_ENABLE, - AccessS3SaveWidth32, - &D0F0x64_x6A.Value, - StdHeader - ); - - D0F0x64_x6A.Field.VoltageChangeEn = 0x1; - - GnbLibPciIndirectWrite ( - MAKE_SBDFO (0, 0, 0, 0, D0F0x60_ADDRESS), - D0F0x64_x6A_ADDRESS | IOC_WRITE_ENABLE, - AccessS3SaveWidth32, - &D0F0x64_x6A.Value, - StdHeader - ); - - D0F0x64_x6A.Field.VoltageLevel = VidIndex; - D0F0x64_x6A.Field.VoltageChangeReq = !D0F0x64_x6A.Field.VoltageChangeReq; - - GnbLibPciIndirectWrite ( - MAKE_SBDFO (0, 0, 0, 0, D0F0x60_ADDRESS), - D0F0x64_x6A_ADDRESS | IOC_WRITE_ENABLE, - AccessS3SaveWidth32, - &D0F0x64_x6A.Value, - StdHeader - ); - do { - GnbLibPciIndirectRead ( - MAKE_SBDFO (0, 0, 0, 0, D0F0x60_ADDRESS), - D0F0x64_x6B_ADDRESS | IOC_WRITE_ENABLE, - AccessS3SaveWidth32, - &D0F0x64_x6B.Value, - StdHeader - ); - } while (D0F0x64_x6A.Field.VoltageChangeReq != D0F0x64_x6B.Field.VoltageChangeAck); -} - -/*----------------------------------------------------------------------------------------*/ -/** - * Unhide all ports - * - * - * - * @param[in] Silicon Pointer to silicon configuration descriptor - * @param[in] Pcie Pointer to global PCIe configuration - */ - -VOID -PcieSiliconUnHidePorts ( - IN PCIe_SILICON_CONFIG *Silicon, - IN PCIe_PLATFORM_CONFIG *Pcie - ) -{ - GnbLibPciIndirectRMW ( - Silicon->Address.AddressValue | D0F0x60_ADDRESS, - D0F0x64_x0C_ADDRESS | IOC_WRITE_ENABLE, - AccessS3SaveWidth32, - ~(UINT32)(BIT2 | BIT3 | BIT4 | BIT5 | BIT6 | BIT7), - 0x0, - GnbLibGetHeader (Pcie) - ); - GnbLibPciIndirectRMW ( - Silicon->Address.AddressValue | D0F0x60_ADDRESS, - D0F0x64_x00_ADDRESS | IOC_WRITE_ENABLE, - AccessS3SaveWidth32, - ~(UINT32)BIT6, - BIT6, - GnbLibGetHeader (Pcie) - ); -} - -/*----------------------------------------------------------------------------------------*/ -/** - * Hide unused ports - * - * - * - * @param[in] Silicon Pointer to silicon configuration data area - * @param[in] Pcie Pointer to data area up to 256 byte - */ - -VOID -PcieSiliconHidePorts ( - IN PCIe_SILICON_CONFIG *Silicon, - IN PCIe_PLATFORM_CONFIG *Pcie - ) -{ - D0F0x64_x0C_STRUCT D0F0x64_x0C; - PCIe_WRAPPER_CONFIG *WrapperList; - D0F0x64_x0C.Value = 0; - WrapperList = PcieConfigGetChildWrapper (Silicon); - while (WrapperList != NULL) { - PCIe_ENGINE_CONFIG *EngineList; - EngineList = PcieConfigGetChildEngine (WrapperList); - while (EngineList != NULL) { - if (EngineList->EngineData.EngineType == PciePortEngine) { - if (!PcieConfigCheckPortStatus (EngineList, INIT_STATUS_PCIE_TRAINING_SUCCESS) && - ((EngineList->Type.Port.PortData.LinkHotplug == HotplugDisabled) || (EngineList->Type.Port.PortData.LinkHotplug == HotplugInboard)) && - !PcieConfigIsSbPcieEngine (EngineList)) { - D0F0x64_x0C.Value |= 1 << EngineList->Type.Port.NativeDevNumber; - } - } - EngineList = PcieLibGetNextDescriptor (EngineList); - } - WrapperList = PcieLibGetNextDescriptor (WrapperList); - } - - GnbLibPciIndirectRMW ( - Silicon->Address.AddressValue | D0F0x60_ADDRESS, - D0F0x64_x0C_ADDRESS | IOC_WRITE_ENABLE, - AccessS3SaveWidth32, - ~(UINT32)(BIT2 | BIT3 | BIT4 | BIT5 | BIT6 | BIT7), - D0F0x64_x0C.Value, - GnbLibGetHeader (Pcie) - ); - GnbLibPciIndirectRMW ( - Silicon->Address.AddressValue | D0F0x60_ADDRESS, - D0F0x64_x00_ADDRESS | IOC_WRITE_ENABLE, - AccessS3SaveWidth32, - ~(UINT32)BIT6, - 0x0, - GnbLibGetHeader (Pcie) - ); -} - diff --git a/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieInitLibV1/PcieSiliconServices.h b/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieInitLibV1/PcieSiliconServices.h deleted file mode 100644 index ed83fc9467..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieInitLibV1/PcieSiliconServices.h +++ /dev/null @@ -1,72 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * PCIe Complex Services - * - * - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: GNB - * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $ - * - */ -/* -***************************************************************************** -* -* Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* *************************************************************************** -* -*/ - -#ifndef _PCIESILICONSERVICES_H_ -#define _PCIESILICONSERVICES_H_ - -UINT8 -PcieSiliconGetGen1VoltageIndex ( - IN AMD_CONFIG_PARAMS *StdHeader - ); - -VOID -PcieSiliconRequestVoltage ( - IN UINT8 VidIndex, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -VOID -PcieSiliconUnHidePorts ( - IN PCIe_SILICON_CONFIG *Silicon, - IN PCIe_PLATFORM_CONFIG *Pcie - ); - -VOID -PcieSiliconHidePorts ( - IN PCIe_SILICON_CONFIG *Silicon, - IN PCIe_PLATFORM_CONFIG *Pcie - ); - -#endif diff --git a/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieInitLibV1/PcieSmuLib.esl b/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieInitLibV1/PcieSmuLib.esl deleted file mode 100644 index 27fed7d8e4..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieInitLibV1/PcieSmuLib.esl +++ /dev/null @@ -1,248 +0,0 @@ -/** - * @file - * - * ALIB PSPP Pcie Smu Lib V1 - * - * - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: GNB - * @e \$Revision: 49911 $ @e \$Date: 2011-03-30 17:43:29 +0800 (Wed, 30 Mar 2011) $ - * - */ -/* -***************************************************************************** -* -* Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* *************************************************************************** -* -*/ - /*----------------------------------------------------------------------------------------*/ - /** - * SMU indirect register read - * - * Arg0 - Smu register offset - * - */ - Method (procNbSmuIndirectRegisterRead, 1, NotSerialized) { - Store (procIndirectRegisterRead (0x0, 0x60, 0xCD), Local0) - // Access 32 bit width - Increment (Arg0) - // Reverse ReqToggle - Or (And (Local0, 0xFEFFFFFF), And (Not (And (Local0, 0x01000000)), 0x01000000),Local0) - // Assign Address and ReqType = 0 - Or (And (Local0, 0xFD00FFFF), ShiftLeft (Arg0, 16), Local0) - - procIndirectRegisterWrite (0x0, 0x60, 0xCD, Local0) - - Store (procIndirectRegisterRead (0x0, 0x60, 0xCE), Local0) - return (Local0) - } - - /*----------------------------------------------------------------------------------------*/ - /** - * SMU indirect register Write - * - * Arg0 - Smu register offset - * Arg1 - Value - * Arg2 - Width, 0 = 16, 1 = 32 - * - */ - Method (procNbSmuIndirectRegisterWrite, 3, NotSerialized) { - Store (procIndirectRegisterRead (0x0, 0x60, 0xCD), Local0) - // Get low 16 bit value - Store (And (Arg1, 0xFFFF), Local1) - // Reverse ReqToggle - Or (And (Local0, 0xFEFFFFFF), And (Not (And (Local0, 0x01000000)), 0x01000000),Local0) - // Assign Address - Or (And (Local0, 0xFD000000), ShiftLeft (Arg0, 16), Local0) - // ReqType = 1 - Or (Local0, 0x02000000, Local0) - // Assign Low 16 bit value - Or (Local0, Local1, Local0) - - procIndirectRegisterWrite (0x0, 0x60, 0xCD, Local0) - - if (LEqual (Arg2, 1)) { - // Get high 16 bit value - Store (ShiftRight (Arg1, 16), Local1) - // Reverse ReqToggle - Or (And (Local0, 0xFEFFFFFF), And (Not (And (Local0, 0x01000000)), 0x01000000),Local0) - // Assign Address - Or (And (Local0, 0xFF000000), ShiftLeft (Add (Arg0, 1), 16), Local0) - // Assign High 16 bit value - Or (Local0, Local1, Local0) - - procIndirectRegisterWrite (0x0, 0x60, 0xCD, Local0) - } - - } - - /*----------------------------------------------------------------------------------------*/ - /** - * SMU Service request - * - * Arg0 - Smu service id - * Arg1 - Flags - Poll Ack = 1, Poll down = 2 - * - */ - Method (procNbSmuServiceRequest, 2, NotSerialized) { - Store ("NbSmuServiceRequest Enter", Debug) - Store ("Request id =", Debug) - Store (Arg0, Debug) - - Or (ShiftLeft (Arg0, 3), 0x1, Local0) - procNbSmuIndirectRegisterWrite (0x3, Local0, 1) - - if (LAnd (Arg1, 1)) { - while (LNotEqual (AND(procNbSmuIndirectRegisterRead (0x3), 0x2), 0x2)) { - Store ("--Wait Ack--", Debug) - } - } - if (LAnd (Arg1, 2)) { - while (LNotEqual (AND(procNbSmuIndirectRegisterRead (0x3), 0x4), 0x4)) { - Store ("--Wait Done--", Debug) - } - } - // Clear IRQ register - procNbSmuIndirectRegisterWrite (0x3, 0, 1) - Store ("NbSmuServiceRequest Exit", Debug) - } - - /*----------------------------------------------------------------------------------------*/ - /** - * Write RCU register - * - * Arg0 - Register Address - * Arg1 - Register Data - * - */ - Method (procSmuRcuWrite, 2, NotSerialized) { - procNbSmuIndirectRegisterWrite (0xB, Arg0, 0) - procNbSmuIndirectRegisterWrite (0x5, Arg1, 1) - - } - - /*----------------------------------------------------------------------------------------*/ - /** - * Read RCU register - * - * Arg0 - Register Address - * Retval - RCU register value - */ - Method (procSmuRcuRead, 1, NotSerialized) { - procNbSmuIndirectRegisterWrite (0xB, Arg0, 0) - Store (procNbSmuIndirectRegisterRead (0x5), Local0) - return (Local0) - } - - /*----------------------------------------------------------------------------------------*/ - /** - * SMU SRBM Register Read - * - * Arg0 - FCR register address - * - */ - Method (procNbSmuSrbmRegisterRead, 1, NotSerialized) { - //SMUx0B_x8600 - Store (Or (And (Arg0, 0xFF), 0x01865000), Local0) - //SMUx0B_x8604 - Store (Or (And (Arg0, 0xFFFFFF00), 4), Local1) - //SMUx0B_x8608 - Store (Or (ShiftLeft (3, 30), ShiftLeft (1, 18)), Local2) - //Write SMU RCU - procSmuRcuWrite (0x8600, Local0) - procSmuRcuWrite (0x8604, Local1) - procSmuRcuWrite (0x8608, Local2) - // ServiceId - if (LEqual (ShiftRight (Arg0, 16), 0xFE00)) { - procNbSmuServiceRequest (0xD, 0x3) - } - if (LEqual (ShiftRight (Arg0, 16), 0xFE30)) { - procNbSmuServiceRequest (0xB, 0x3) - } - return (procSmuRcuRead(0x8650)) - } - - - /*----------------------------------------------------------------------------------------*/ - /** - * SMU SRBM Register Write - * - * Arg0 - FCR register address - * Arg1 - Value - * - */ - Method (procNbSmuSrbmRegisterWrite, 2, NotSerialized) { - //SMUx0B_x8600 - Store (Or (And (Arg0, 0xFF), 0x01865000), Local0) - //SMUx0B_x8604 - Store (Or (And (Arg0, 0xFFFFFF00), 4), Local1) - //SMUx0B_x8608 - Store (Or (ShiftLeft (3, 30), ShiftLeft (1, 18)), Local2) - Or (Local2, ShiftLeft (1, 16), Local2) - //Write SMU RCU - procSmuRcuWrite (0x8600, Local0) - procSmuRcuWrite (0x8604, Local1) - procSmuRcuWrite (0x8608, Local2) - //Write Data - procSmuRcuWrite (0x8650, Arg1) - // ServiceId - procNbSmuServiceRequest (0xB, 0x3) - } - - /*----------------------------------------------------------------------------------------*/ - /** - * Request VID - * - * Arg0 - VID index - * Arg1 - 0 = do not wait intil voltage is set - * 1 = wait until voltage is set - */ - Method (procPcieSetVoltage, 2, Serialized) { - Store ("PcieSetVoltage Enter", Debug) - Store (procIndirectRegisterRead (0x0, 0x60, 0xEA), Local1) - //Enable voltage change - Or (Local1, 0x2, Local1) - procIndirectRegisterWrite (0x0, 0x60, 0xEA, Local1) - //Clear voltage index - And (Local1, Not (ShiftLeft (0x3, 3)), Local1) - - Store (Concatenate (" Voltage Index:", ToHexString (Arg0), Local6), Debug) - //Set new voltage index - Or (Local1, ShiftLeft (Arg0, 3), Local1) - //Togle request - And (Not (Local1), 0x4, Local2) - Or (And (Local1, Not (0x4)), Local2, Local1) - procIndirectRegisterWrite (0x0, 0x60, 0xEA, Local1) - if (LNotEqual (Arg1, 0)) { - while (LNotEqual (ShiftLeft(Local1, 0x2), Local2)) { - And (procIndirectRegisterRead (0x0, 0x60, 0xEB), 0x1, Local1) - } - } - Store ("PcieSetVoltage Exit", Debug) - } diff --git a/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieInitLibV1/PcieTimer.c b/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieInitLibV1/PcieTimer.c deleted file mode 100644 index a9f8b300f9..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieInitLibV1/PcieTimer.c +++ /dev/null @@ -1,100 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * PCIe timer access procedure - * - * - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: GNB - * @e \$Revision: 48452 $ @e \$Date: 2011-03-09 12:50:44 +0800 (Wed, 09 Mar 2011) $ - * - */ -/* -***************************************************************************** -* -* Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* *************************************************************************** -* -*/ - -/*---------------------------------------------------------------------------------------- - * M O D U L E S U S E D - *---------------------------------------------------------------------------------------- - */ -#include "AGESA.h" -#include "Ids.h" -#include "amdlib.h" -#include "Gnb.h" -#include "GnbPcie.h" -#include "GnbCommonLib.h" -#include "GnbPcieConfig.h" -#include "GnbPcieInitLibV1.h" -#include "GnbRegistersLN.h" -#include "Filecode.h" -#define FILECODE PROC_GNB_MODULES_GNBPCIEINITLIBV1_PCIETIMER_FILECODE -/*---------------------------------------------------------------------------------------- - * D E F I N I T I O N S A N D M A C R O S - *---------------------------------------------------------------------------------------- - */ - - -/*---------------------------------------------------------------------------------------- - * T Y P E D E F S A N D S T R U C T U R E S - *---------------------------------------------------------------------------------------- - */ - - -/*---------------------------------------------------------------------------------------- - * P R O T O T Y P E S O F L O C A L F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ - -/*----------------------------------------------------------------------------------------*/ -/** - * Get PCIe timer timestamp - * - * - * - * @param[in] Pcie Pointer to internal configuration data area - * @retval Time stamp value - */ - -UINT32 -PcieTimerGetTimeStamp ( - IN PCIe_PLATFORM_CONFIG *Pcie - ) -{ - D0F0xE4_WRAP_80F0_STRUCT D0F0xE4_WRAP_80F0; - D0F0xE4_WRAP_80F0.Value = PcieRegisterRead ( - (PCIe_WRAPPER_CONFIG *) PcieConfigGetChild (DESCRIPTOR_PCIE_WRAPPER, &Pcie->Header), - WRAP_SPACE (0, D0F0xE4_WRAP_80F0_ADDRESS), - Pcie - ); - return D0F0xE4_WRAP_80F0.Value; -} \ No newline at end of file diff --git a/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieInitLibV1/PcieTimer.h b/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieInitLibV1/PcieTimer.h deleted file mode 100644 index 5c719c26e7..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieInitLibV1/PcieTimer.h +++ /dev/null @@ -1,55 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * PCIe timer access procedure - * - * - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: GNB - * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $ - * - */ -/* -***************************************************************************** -* -* Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* *************************************************************************** -* -*/ -#ifndef _PCIETIMER_H_ -#define _PCIETIMER_H_ - -UINT32 -PcieTimerGetTimeStamp ( - IN PCIe_PLATFORM_CONFIG *Pcie - ); - -#define TIMESTAMPS_DELTA(Time2, Time1) ((Time2 > Time1) ? (Time2 - Time1) : (0xffffffffull - Time1 + Time2)) - -#endif diff --git a/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieInitLibV1/PcieTopologyServices.c b/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieInitLibV1/PcieTopologyServices.c deleted file mode 100644 index 2da536eb99..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieInitLibV1/PcieTopologyServices.c +++ /dev/null @@ -1,724 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * PCIe topology initialization service procedures. - * - * - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: GNB - * @e \$Revision: 52794 $ @e \$Date: 2011-05-12 05:52:37 +0800 (Thu, 12 May 2011) $ - * - */ -/* -***************************************************************************** -* -* Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* *************************************************************************** -* -*/ - -/*---------------------------------------------------------------------------------------- - * M O D U L E S U S E D - *---------------------------------------------------------------------------------------- - */ -#include "AGESA.h" -#include "Ids.h" -#include "amdlib.h" -#include "Gnb.h" -#include "GnbPcie.h" -#include "GnbPcieFamServices.h" -#include "GnbCommonLib.h" -#include "GnbPcieConfig.h" -#include "GnbPcieInitLibV1.h" -#include "GnbRegistersLN.h" -#include "Filecode.h" -#define FILECODE PROC_GNB_MODULES_GNBPCIEINITLIBV1_PCIETOPOLOGYSERVICES_FILECODE -/*---------------------------------------------------------------------------------------- - * D E F I N I T I O N S A N D M A C R O S - *---------------------------------------------------------------------------------------- - */ - - -/*---------------------------------------------------------------------------------------- - * T Y P E D E F S A N D S T R U C T U R E S - *---------------------------------------------------------------------------------------- - */ - - -/*---------------------------------------------------------------------------------------- - * P R O T O T Y P E S O F L O C A L F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ -UINT8 -PcieTopologyLocateMuxIndex ( - IN OUT UINT8 *LaneMuxSelectorArrayPtr, - IN UINT8 LaneMuxValue - ); - - -/*----------------------------------------------------------------------------------------*/ -/** - * Prepare for reconfiguration - * - * - * - * @param[in] Wrapper Pointer to wrapper config descriptor - * @param[in] Pcie Pointer to global PCIe configuration - */ -VOID -PcieTopologyPrepareForReconfig ( - IN PCIe_WRAPPER_CONFIG *Wrapper, - IN PCIe_PLATFORM_CONFIG *Pcie - ) -{ - D0F0xE4_WRAP_8062_STRUCT D0F0xE4_WRAP_8062; - UINT8 CoreId; - if (PcieLibIsPcieWrapper (Wrapper)) { - for (CoreId = Wrapper->StartPcieCoreId; CoreId <= Wrapper->EndPcieCoreId; CoreId++) { - PcieRegisterWriteField ( - Wrapper, - CORE_SPACE (CoreId, D0F0xE4_CORE_0011_ADDRESS), - D0F0xE4_CORE_0011_DynClkLatency_OFFSET, - D0F0xE4_CORE_0011_DynClkLatency_WIDTH, - 0xf, - FALSE, - Pcie - ); - } - - D0F0xE4_WRAP_8062.Value = PcieRegisterRead ( - Wrapper, - WRAP_SPACE (Wrapper->WrapId, D0F0xE4_WRAP_8062_ADDRESS), - Pcie - ); - - D0F0xE4_WRAP_8062.Field.ConfigXferMode = 0x0; - D0F0xE4_WRAP_8062.Field.BlockOnIdle = 0x0; - PcieRegisterWrite ( - Wrapper, - WRAP_SPACE (Wrapper->WrapId, D0F0xE4_WRAP_8062_ADDRESS), - D0F0xE4_WRAP_8062.Value, - FALSE, - Pcie - ); - } -} - - -UINT8 LaneMuxSelectorTable[8] = { 0, 1, 2, 3, 4, 5, 6, 7 }; - -/*----------------------------------------------------------------------------------------*/ -/** - * Locate mux array index - * - * - * - * @param[in, out] LaneMuxSelectorArrayPtr Pointer to mux selector array - * @param[in] LaneMuxValue The value that match to array - * @retval Index Index successfully mapped - */ -UINT8 -PcieTopologyLocateMuxIndex ( - IN OUT UINT8 *LaneMuxSelectorArrayPtr, - IN UINT8 LaneMuxValue - ) -{ - UINT8 Index; - for (Index = 0; Index < sizeof (LaneMuxSelectorTable); Index++ ) { - if (LaneMuxSelectorArrayPtr [Index] == LaneMuxValue) { - return Index; - } - } - return 0; -} - -/*----------------------------------------------------------------------------------------*/ -/** - * Apply lane mux - * - * - * - * @param[in] Wrapper Pointer to wrapper config descriptor - * @param[in] Pcie Pointer to global PCIe configuration - */ - -VOID -PcieTopologyApplyLaneMux ( - IN PCIe_WRAPPER_CONFIG *Wrapper, - IN PCIe_PLATFORM_CONFIG *Pcie - ) -{ - PCIe_ENGINE_CONFIG *EngineList; - UINT8 CurrentPhyLane; - UINT8 CurrentCoreLane; - UINT8 CoreLaneIndex; - UINT8 PhyLaneIndex; - UINT8 NumberOfPhyLane; - UINT8 TxLaneMuxSelectorArray [sizeof (LaneMuxSelectorTable)]; - UINT8 RxLaneMuxSelectorArray [sizeof (LaneMuxSelectorTable)]; - UINT8 Index; - UINT32 TxMaxSelectorValue; - UINT32 RxMaxSelectorValue; - - IDS_HDT_CONSOLE (GNB_TRACE, "PcieTopologyApplyLaneMux Enter\n"); - if (PcieLibIsPcieWrapper (Wrapper)) { - EngineList = PcieConfigGetChildEngine (Wrapper); - LibAmdMemCopy ( - &TxLaneMuxSelectorArray[0], - &LaneMuxSelectorTable[0], - sizeof (LaneMuxSelectorTable), - GnbLibGetHeader (Pcie) - ); - LibAmdMemCopy ( - &RxLaneMuxSelectorArray[0], - &LaneMuxSelectorTable[0], - sizeof (LaneMuxSelectorTable), - GnbLibGetHeader (Pcie) - ); - while (EngineList != NULL) { - if (PcieLibIsPcieEngine (EngineList) && PcieLibIsEngineAllocated (EngineList)) { - CurrentPhyLane = (UINT8) PcieLibGetLoPhyLane (EngineList) - Wrapper->StartPhyLane; - NumberOfPhyLane = (UINT8) PcieConfigGetNumberOfPhyLane (EngineList); - CurrentCoreLane = (UINT8) EngineList->Type.Port.StartCoreLane; - if (PcieUtilIsLinkReversed (FALSE, EngineList, Pcie)) { - CurrentCoreLane = CurrentCoreLane + PcieConfigGetNumberOfCoreLane (EngineList) - NumberOfPhyLane; - } - for (Index = 0; Index < NumberOfPhyLane; Index = Index + 2 ) { - CoreLaneIndex = (CurrentCoreLane + Index) / 2; - PhyLaneIndex = (CurrentPhyLane + Index) / 2; - - if (RxLaneMuxSelectorArray [CoreLaneIndex] != PhyLaneIndex) { - RxLaneMuxSelectorArray [PcieTopologyLocateMuxIndex (RxLaneMuxSelectorArray, PhyLaneIndex)] = RxLaneMuxSelectorArray [CoreLaneIndex]; - RxLaneMuxSelectorArray [CoreLaneIndex] = PhyLaneIndex; - } - if (TxLaneMuxSelectorArray [PhyLaneIndex] != CoreLaneIndex) { - TxLaneMuxSelectorArray [PcieTopologyLocateMuxIndex (TxLaneMuxSelectorArray, CoreLaneIndex)] = TxLaneMuxSelectorArray [PhyLaneIndex]; - TxLaneMuxSelectorArray [PhyLaneIndex] = CoreLaneIndex; - } - } - } - EngineList = PcieLibGetNextDescriptor (EngineList); - } - RxMaxSelectorValue = 0; - TxMaxSelectorValue = 0; - for (Index = 0; Index < sizeof (LaneMuxSelectorTable); Index++) { - RxMaxSelectorValue |= (RxLaneMuxSelectorArray[Index] << (Index * 4)); - TxMaxSelectorValue |= (TxLaneMuxSelectorArray[Index] << (Index * 4)); - } - PcieRegisterWrite ( - Wrapper, - WRAP_SPACE (Wrapper->WrapId, D0F0xE4_WRAP_8021_ADDRESS), - TxMaxSelectorValue, - FALSE, - Pcie - ); - PcieRegisterWrite ( - Wrapper, - WRAP_SPACE (Wrapper->WrapId, D0F0xE4_WRAP_8022_ADDRESS), - RxMaxSelectorValue, - FALSE, - Pcie - ); - } - IDS_HDT_CONSOLE (GNB_TRACE, "PcieTopologyApplyLaneMux Exit\n"); -} - - -/*----------------------------------------------------------------------------------------*/ -/** - * Select master PLL - * - * - * - * @param[in] Wrapper Pointer to wrapper config descriptor - * @param[in] Pcie Pointer to global PCIe configuration - */ - -VOID -PcieTopologySelectMasterPll ( - IN PCIe_WRAPPER_CONFIG *Wrapper, - IN PCIe_PLATFORM_CONFIG *Pcie - ) -{ - PCIe_ENGINE_CONFIG *EngineList; - UINT16 MasterLane; - UINT16 MasterHotplugLane; - D0F0xE4_WRAP_8013_STRUCT D0F0xE4_WRAP_8013; - IDS_HDT_CONSOLE (GNB_TRACE, "PcieTopologySelectMasterPll Enter\n"); - MasterLane = 0xFFFF; - MasterHotplugLane = 0xFFFF; - EngineList = PcieConfigGetChildEngine (Wrapper); - while (EngineList != NULL) { - if (PcieConfigIsEngineAllocated (EngineList) && PcieConfigIsPcieEngine (EngineList)) { - if (EngineList->Type.Port.PortData.LinkHotplug != HotplugDisabled) { - MasterHotplugLane = PcieConfigGetPcieEngineMasterLane (EngineList); - } else { - MasterLane = PcieConfigGetPcieEngineMasterLane (EngineList); - if (PcieConfigIsSbPcieEngine (EngineList)) { - break; - } - } - } - EngineList = PcieLibGetNextDescriptor (EngineList); - } - - if (MasterLane == 0xffff) { - if (MasterHotplugLane != 0xffff) { - MasterLane = MasterHotplugLane; - } else { - MasterLane = 0x0; - } - } - - D0F0xE4_WRAP_8013.Value = PcieRegisterRead ( - Wrapper, - WRAP_SPACE (Wrapper->WrapId, D0F0xE4_WRAP_8013_ADDRESS), - Pcie - ); - - if ( MasterLane <= 3 ) { - D0F0xE4_WRAP_8013.Field.MasterPciePllA = 0x1; - D0F0xE4_WRAP_8013.Field.MasterPciePllB = 0x0; - D0F0xE4_WRAP_8013.Field.MasterPciePllC = 0x0; - D0F0xE4_WRAP_8013.Field.MasterPciePllD = 0x0; - } else if (MasterLane <= 7) { - D0F0xE4_WRAP_8013.Field.MasterPciePllA = 0x0; - D0F0xE4_WRAP_8013.Field.MasterPciePllB = 0x1; - D0F0xE4_WRAP_8013.Field.MasterPciePllC = 0x0; - D0F0xE4_WRAP_8013.Field.MasterPciePllD = 0x0; - } else if (MasterLane <= 11) { - D0F0xE4_WRAP_8013.Field.MasterPciePllA = 0x0; - D0F0xE4_WRAP_8013.Field.MasterPciePllB = 0x0; - D0F0xE4_WRAP_8013.Field.MasterPciePllC = 0x1; - D0F0xE4_WRAP_8013.Field.MasterPciePllD = 0x0; - } else { - D0F0xE4_WRAP_8013.Field.MasterPciePllA = 0x0; - D0F0xE4_WRAP_8013.Field.MasterPciePllB = 0x0; - D0F0xE4_WRAP_8013.Field.MasterPciePllC = 0x0; - D0F0xE4_WRAP_8013.Field.MasterPciePllD = 0x1; - } - PcieRegisterWrite ( - Wrapper, - WRAP_SPACE (Wrapper->WrapId, D0F0xE4_WRAP_8013_ADDRESS), - D0F0xE4_WRAP_8013.Value, - FALSE, - Pcie - ); - - IDS_HDT_CONSOLE (GNB_TRACE, "PcieTopologySelectMasterPll Exit\n"); -} - -/*----------------------------------------------------------------------------------------*/ -/** - * Execute/clean up reconfiguration - * - * - * @param[in] Wrapper Pointer to wrapper config descriptor - * @param[in] Pcie Pointer to global PCIe configuration - */ -VOID -PcieTopologyExecuteReconfig ( - IN PCIe_WRAPPER_CONFIG *Wrapper, - IN PCIe_PLATFORM_CONFIG *Pcie - ) -{ - D0F0xE4_WRAP_8062_STRUCT D0F0xE4_WRAP_8062; - D0F0xE4_WRAP_8060_STRUCT D0F0xE4_WRAP_8060; - - if (PcieLibIsPcieWrapper (Wrapper)) { - IDS_HDT_CONSOLE (GNB_TRACE, "PcieTopologyExecuteReconfig Enter\n"); - - PcieTopologyInitSrbmReset (FALSE, Wrapper, Pcie); - - D0F0xE4_WRAP_8062.Value = PcieRegisterRead ( - Wrapper, - WRAP_SPACE (Wrapper->WrapId, D0F0xE4_WRAP_8062_ADDRESS), - Pcie - ); - D0F0xE4_WRAP_8060.Value = PcieRegisterRead ( - Wrapper, - WRAP_SPACE (Wrapper->WrapId, D0F0xE4_WRAP_8060_ADDRESS), - Pcie - ); - - D0F0xE4_WRAP_8062.Field.ReconfigureEn = 0x1; - PcieRegisterWrite ( - Wrapper, - WRAP_SPACE (Wrapper->WrapId, D0F0xE4_WRAP_8062_ADDRESS), - D0F0xE4_WRAP_8062.Value, - FALSE, - Pcie - ); - D0F0xE4_WRAP_8060.Field.Reconfigure = 0x1; - PcieRegisterWrite ( - Wrapper, - WRAP_SPACE (Wrapper->WrapId, D0F0xE4_WRAP_8060_ADDRESS), - D0F0xE4_WRAP_8060.Value, - FALSE, - Pcie - ); - do { - D0F0xE4_WRAP_8060.Value = PcieRegisterRead ( - Wrapper, - WRAP_SPACE (Wrapper->WrapId, D0F0xE4_WRAP_8060_ADDRESS), - Pcie - ); - - } while (D0F0xE4_WRAP_8060.Field.Reconfigure == 1); - D0F0xE4_WRAP_8062.Field.ConfigXferMode = 0x1; - D0F0xE4_WRAP_8062.Field.ReconfigureEn = 0x0; - PcieRegisterWrite ( - Wrapper, - WRAP_SPACE (Wrapper->WrapId, D0F0xE4_WRAP_8062_ADDRESS), - D0F0xE4_WRAP_8062.Value, - FALSE, - Pcie - ); - PcieTopologyInitSrbmReset (TRUE, Wrapper, Pcie); - IDS_HDT_CONSOLE (GNB_TRACE, "PcieTopologyExecuteReconfig Exit\n"); - } -} - -/*----------------------------------------------------------------------------------------*/ -/** - * Enable lane reversal - * - * - * @param[in] Wrapper Pointer to wrapper config descriptor - * @param[in] Pcie Pointer to global PCIe configuration - */ -VOID -PcieTopologySetLinkReversal ( - IN PCIe_WRAPPER_CONFIG *Wrapper, - IN PCIe_PLATFORM_CONFIG *Pcie - ) -{ - PCIe_ENGINE_CONFIG *EngineList; - IDS_HDT_CONSOLE (GNB_TRACE, "PcieTopologySetLinkReversal Enter\n"); - EngineList = PcieConfigGetChildEngine (Wrapper); - while (EngineList != NULL) { - if (PcieLibIsEngineAllocated (EngineList)) { - if (PcieLibIsPcieEngine (EngineList)) { - if (EngineList->EngineData.StartLane > EngineList->EngineData.EndLane) { - PciePortRegisterWriteField ( - EngineList, - DxF0xE4_xC1_ADDRESS, - DxF0xE4_xC1_StrapReverseLanes_OFFSET, - DxF0xE4_xC1_StrapReverseLanes_WIDTH, - 0x1, - FALSE, - Pcie - ); - } - } - } - EngineList = PcieLibGetNextDescriptor (EngineList); - } - IDS_HDT_CONSOLE (GNB_TRACE, "PcieTopologySetLinkReversal Exit\n"); -} - - -/*----------------------------------------------------------------------------------------*/ -/** - * Reduce link width - * - * - * @param[in] LinkWidth Link width - * @param[in] Engine Pointer to Engine config descriptor - * @param[in] Pcie Pointer to global PCIe configuration - */ -VOID -PcieTopologyReduceLinkWidth ( - IN UINT8 LinkWidth, - IN PCIe_ENGINE_CONFIG *Engine, - IN PCIe_PLATFORM_CONFIG *Pcie - ) -{ - PCIe_WRAPPER_CONFIG *Wrapper; - UINT32 LinkReversed; - UINT8 DeltaLinkWidthBitmap; - UINT32 LanesToDisable; - Wrapper = PcieConfigGetParentWrapper (Engine); - LinkReversed = PcieUtilIsLinkReversed (TRUE, Engine, Pcie); - - DeltaLinkWidthBitmap = (1 << (PcieConfigGetNumberOfCoreLane (Engine) - LinkWidth)) - 1; - LanesToDisable = (DeltaLinkWidthBitmap << ((LinkReversed == 1) ? Engine->Type.Port.StartCoreLane : (Engine->Type.Port.StartCoreLane + LinkWidth))); - - PcieTopologyLaneControl ( - DisableLanes, - LanesToDisable, - Wrapper, - Pcie - ); -} - -/*----------------------------------------------------------------------------------------*/ -/** - * Lanes enable/disable control - * - * @param[in] Control Lane control action - * @param[in] LaneBitMap Core lanes bitmap - * @param[in] Wrapper Pointer to Wrapper config descriptor - * @param[in] Pcie Pointer to global PCIe configuration - */ -VOID -PcieTopologyLaneControl ( - IN LANE_CONTROL Control, - IN UINT32 LaneBitMap, - IN PCIe_WRAPPER_CONFIG *Wrapper, - IN PCIe_PLATFORM_CONFIG *Pcie - ) -{ - D0F0xE4_WRAP_8023_STRUCT D0F0xE4_WRAP_8023; - D0F0xE4_WRAP_8023.Value = PcieRegisterRead ( - Wrapper, - WRAP_SPACE (Wrapper->WrapId, D0F0xE4_WRAP_8023_ADDRESS), - Pcie - ); - - if (Control == EnableLanes) { - D0F0xE4_WRAP_8023.Value |= LaneBitMap; - } else if (Control == DisableLanes) { - D0F0xE4_WRAP_8023.Value &= (~LaneBitMap); - } - D0F0xE4_WRAP_8023.Value &= ((1 << Wrapper->NumberOfLanes) - 1); - PcieRegisterWrite ( - Wrapper, - WRAP_SPACE (Wrapper->WrapId, D0F0xE4_WRAP_8023_ADDRESS), - D0F0xE4_WRAP_8023.Value, - TRUE, - Pcie - ); -} - -/*----------------------------------------------------------------------------------------*/ -/** - * Init SRBM reset - * - * @param[in] SrbmResetEnable SRBM reset enable flag. - * @param[in] Wrapper Pointer to wrapper config descriptor - * @param[in] Pcie Pointer to global PCIe configuration - */ -VOID -PcieTopologyInitSrbmReset ( - IN BOOLEAN SrbmResetEnable, - IN PCIe_WRAPPER_CONFIG *Wrapper, - IN PCIe_PLATFORM_CONFIG *Pcie - ) -{ - UINT32 pcireg; - UINT32 regmask = 0x7030;; - pcireg = PcieRegisterRead ( - Wrapper, - WRAP_SPACE (Wrapper->WrapId, 0x8063), - Pcie - ); - if (SrbmResetEnable) { - pcireg |= regmask; - } else { - pcireg &= ~(regmask); - } - PcieRegisterWrite ( - Wrapper, - WRAP_SPACE (Wrapper->WrapId, 0x8063), - pcireg, - FALSE, - Pcie - ); - -} - -/*----------------------------------------------------------------------------------------*/ -/** - * Set core configuration according to PCIe port topology - * - * - * - * @param[in] Wrapper Pointer to wrapper config descriptor - * @param[in] Pcie Pointer to global PCIe configuration - * @retval AGESA_SUCCESS Topology successfully mapped - * @retval AGESA_ERROR Topology can not be mapped - */ - -AGESA_STATUS -PcieTopologySetCoreConfig ( - IN PCIe_WRAPPER_CONFIG *Wrapper, - IN PCIe_PLATFORM_CONFIG *Pcie - ) -{ - UINT8 CoreId; - AGESA_STATUS Status; - Status = AGESA_SUCCESS; - if (PcieLibIsPcieWrapper (Wrapper)) { - for (CoreId = Wrapper->StartPcieCoreId; CoreId <= Wrapper->EndPcieCoreId; CoreId++) { - UINT64 ConfigurationSignature; - UINT8 NewConfigurationValue; - ConfigurationSignature = PcieConfigGetConfigurationSignature (Wrapper, CoreId); - Status = PcieFmGetCoreConfigurationValue (Wrapper, CoreId, ConfigurationSignature, &NewConfigurationValue); - if (Status == AGESA_SUCCESS) { - IDS_HDT_CONSOLE (PCIE_MISC, " Core Configuration: Wrapper [%s], CoreID [%d] - %s\n", - PcieFmDebugGetWrapperNameString (Wrapper), - CoreId, - PcieFmDebugGetCoreConfigurationString (Wrapper, NewConfigurationValue) - ); - PcieRegisterWriteField ( - Wrapper, - WRAP_SPACE (Wrapper->WrapId, D0F0xE4_WRAP_0080_ADDRESS), - D0F0xE4_WRAP_0080_StrapBifLinkConfig_OFFSET, - D0F0xE4_WRAP_0080_StrapBifLinkConfig_WIDTH, - NewConfigurationValue, - FALSE, - Pcie - ); - } else { - IDS_HDT_CONSOLE (PCIE_MISC, " ERROR! Core Configuration : Wrapper [%s], Signature [0x%x, 0x%x]\n", - PcieFmDebugGetWrapperNameString (Wrapper), - ((UINT32*)&ConfigurationSignature)[1], - ((UINT32*)&ConfigurationSignature)[0] - ); - PcieConfigDisableAllEngines (PciePortEngine | PcieDdiEngine, Wrapper); - } - } - } - return Status; -} - -/*----------------------------------------------------------------------------------------*/ -/** - * Relinquish control to DDI for specific lanes - * - * - * @param[in] Wrapper Pointer to wrapper configuration descriptor - * @param[in] Pcie Pointer to global PCIe configuration - */ -VOID -PcieSetDdiOwnPhy ( - IN PCIe_WRAPPER_CONFIG *Wrapper, - IN PCIe_PLATFORM_CONFIG *Pcie - ) -{ - D0F0xE4_WRAP_8040_STRUCT D0F0xE4_WRAP_8040; - UINT32 LaneBitmap; - - if (PcieLibIsDdiWrapper (Wrapper)) { - IDS_HDT_CONSOLE (GNB_TRACE, "PcieFmSetDdiOwnPhy Enter\n"); - LaneBitmap = PcieUtilGetWrapperLaneBitMap (LANE_TYPE_DDI_PHY_NATIVE, 0, Wrapper); - D0F0xE4_WRAP_8040.Value = PcieRegisterRead ( - Wrapper, - WRAP_SPACE (Wrapper->WrapId, D0F0xE4_WRAP_8040_ADDRESS), - Pcie - ); - if ((LaneBitmap & BIT0) != 0) { - D0F0xE4_WRAP_8040.Field.OwnPhyA = 0x1; - } - if ((LaneBitmap & BIT4) != 0) { - D0F0xE4_WRAP_8040.Field.OwnPhyB = 0x1; - } - if ((LaneBitmap & BIT8) != 0) { - D0F0xE4_WRAP_8040.Field.OwnPhyC = 0x1; - } - if ((LaneBitmap & BIT12) != 0) { - D0F0xE4_WRAP_8040.Field.OwnPhyD = 0x1; - } - PcieRegisterWrite ( - Wrapper, - WRAP_SPACE (Wrapper->WrapId, D0F0xE4_WRAP_8040_ADDRESS), - D0F0xE4_WRAP_8040.Value, - FALSE, - Pcie - ); - IDS_HDT_CONSOLE (GNB_TRACE, "PcieFmSetDdiOwnPhy Exit\n"); - } -} - -/*----------------------------------------------------------------------------------------*/ -/** - * Set TX control for PCIe lanes - * - * - * - * @param[in] Wrapper Pointer to wrapper config descriptor - * @param[in] Pcie Pointer to global PCIe configuration - */ -VOID -PcieWrapSetTxS1CtrlForLaneMux ( - IN PCIe_WRAPPER_CONFIG *Wrapper, - IN PCIe_PLATFORM_CONFIG *Pcie - ) -{ - D0F0xE4_WRAP_8025_STRUCT D0F0xE4_WRAP_8025; - UINT32 LaneBitmap; - UINTN Index; - D0F0xE4_WRAP_8025.Value = PcieRegisterRead ( - Wrapper, - WRAP_SPACE (Wrapper->WrapId, D0F0xE4_WRAP_8025_ADDRESS), - Pcie - ); - Index = 0; - LaneBitmap = PcieUtilGetWrapperLaneBitMap (LANE_TYPE_CORE_ALL, LANE_TYPE_PCIE_SB_CORE_CONFIG, Wrapper); - while (LaneBitmap != 0) { - if ((LaneBitmap & 0xf) != 0) { - D0F0xE4_WRAP_8025.Value &= (~(0xff << (Index * 8))); - D0F0xE4_WRAP_8025.Value |= (((0x03 << 3) | 0x1) << (Index * 8)); - } - LaneBitmap >>= 4; - ++Index; - } - PcieRegisterWrite ( - Wrapper, - WRAP_SPACE (Wrapper->WrapId, D0F0xE4_WRAP_8025_ADDRESS), - D0F0xE4_WRAP_8025.Value, - FALSE, - Pcie - ); -} - -/*----------------------------------------------------------------------------------------*/ -/** - * Set TX control for lane muxes - * - * - * - * @param[in] Wrapper Pointer to wrapper config descriptor - * @param[in] Pcie Pointer to global PCIe configuration - */ -VOID -PcieWrapSetTxOffCtrlForLaneMux ( - IN PCIe_WRAPPER_CONFIG *Wrapper, - IN PCIe_PLATFORM_CONFIG *Pcie - ) -{ - PcieRegisterWrite ( - Wrapper, - WRAP_SPACE (Wrapper->WrapId, D0F0xE4_WRAP_8025_ADDRESS), - 0x1f1f1f1f, - FALSE, - Pcie - ); -} diff --git a/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieInitLibV1/PcieTopologyServices.h b/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieInitLibV1/PcieTopologyServices.h deleted file mode 100644 index f4c446a2fc..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieInitLibV1/PcieTopologyServices.h +++ /dev/null @@ -1,133 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * PCIe topology initialization service procedures. - * - * - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: GNB - * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $ - * - */ -/* -***************************************************************************** -* -* Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* *************************************************************************** -* -*/ -#ifndef _PCIETOPOLOGYSERVICES_H_ -#define _PCIETOPOLOGYSERVICES_H_ - -/// Lane Control -typedef enum { - EnableLanes, ///< Enable Lanes - DisableLanes ///< Disable Lanes -} LANE_CONTROL; - -VOID -PcieTopologyPrepareForReconfig ( - IN PCIe_WRAPPER_CONFIG *Wrapper, - IN PCIe_PLATFORM_CONFIG *Pcie - ); - -AGESA_STATUS -PcieTopologySetCoreConfig ( - IN PCIe_WRAPPER_CONFIG *Wrapper, - IN PCIe_PLATFORM_CONFIG *Pcie - ); - -VOID -PcieTopologyApplyLaneMux ( - IN PCIe_WRAPPER_CONFIG *Wrapper, - IN PCIe_PLATFORM_CONFIG *Pcie - ); - -VOID -PcieTopologySelectMasterPll ( - IN PCIe_WRAPPER_CONFIG *Wrapper, - IN PCIe_PLATFORM_CONFIG *Pcie - ); - -VOID -PcieTopologyExecuteReconfig ( - IN PCIe_WRAPPER_CONFIG *Wrapper, - IN PCIe_PLATFORM_CONFIG *Pcie - ); - -VOID -PcieTopologySetLinkReversal ( - IN PCIe_WRAPPER_CONFIG *Wrapper, - IN PCIe_PLATFORM_CONFIG *Pcie - ); - - -VOID -PcieTopologyReduceLinkWidth ( - IN UINT8 LinkWidth, - IN PCIe_ENGINE_CONFIG *Engine, - IN PCIe_PLATFORM_CONFIG *Pcie - ); - -VOID -PcieTopologyLaneControl ( - IN LANE_CONTROL Control, - IN UINT32 LaneBitMap, - IN PCIe_WRAPPER_CONFIG *Wrapper, - IN PCIe_PLATFORM_CONFIG *Pcie - ); - -VOID -PcieTopologyInitSrbmReset ( - IN BOOLEAN SrbmResetEnable, - IN PCIe_WRAPPER_CONFIG *Wrapper, - IN PCIe_PLATFORM_CONFIG *Pcie - ); - -VOID -PcieSetDdiOwnPhy ( - IN PCIe_WRAPPER_CONFIG *Wrapper, - IN PCIe_PLATFORM_CONFIG *Pcie - ); - -VOID -PcieWrapSetTxS1CtrlForLaneMux ( - IN PCIe_WRAPPER_CONFIG *Wrapper, - IN PCIe_PLATFORM_CONFIG *Pcie - ); - -VOID -PcieWrapSetTxOffCtrlForLaneMux ( - IN PCIe_WRAPPER_CONFIG *Wrapper, - IN PCIe_PLATFORM_CONFIG *Pcie - ); - -#endif - - diff --git a/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieInitLibV1/PcieUtilityLib.c b/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieInitLibV1/PcieUtilityLib.c deleted file mode 100644 index fd37187fdd..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieInitLibV1/PcieUtilityLib.c +++ /dev/null @@ -1,648 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * PCIe utility. Various supporting functions. - * - * - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: GNB - * @e \$Revision: 49532 $ @e \$Date: 2011-03-25 02:54:43 +0800 (Fri, 25 Mar 2011) $ - * - */ -/* -***************************************************************************** -* -* Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* *************************************************************************** -* -*/ - -/*---------------------------------------------------------------------------------------- - * M O D U L E S U S E D - *---------------------------------------------------------------------------------------- - */ -#include "AGESA.h" -#include "Ids.h" -#include "amdlib.h" -#include "Gnb.h" -#include "GnbPcie.h" -#include "GnbPcieFamServices.h" -#include "GnbCommonLib.h" -#include "GnbPcieConfig.h" -#include "GnbPcieInitLibV1.h" -#include "GnbRegistersLN.h" -#include "Filecode.h" -#define FILECODE PROC_GNB_MODULES_GNBPCIEINITLIBV1_PCIEUTILITYLIB_FILECODE -/*---------------------------------------------------------------------------------------- - * D E F I N I T I O N S A N D M A C R O S - *---------------------------------------------------------------------------------------- - */ -/// Lane type -typedef enum { - LaneTypeCore, ///< Core Lane - LaneTypePhy, ///< Package Phy Lane - LaneTypeNativePhy ///< Native Phy Lane -} LANE_TYPE; - -/// Lane Property -typedef enum { - LanePropertyConfig, ///< Configuration - LanePropertyActive, ///< Active - LanePropertyAllocated ///< Allocated -} LANE_PROPERTY; - - -/*---------------------------------------------------------------------------------------- - * T Y P E D E F S A N D S T R U C T U R E S - *---------------------------------------------------------------------------------------- - */ -typedef struct { - UINT32 Flags; - PCIE_LINK_SPEED_CAP LinkSpeedCapability; -} PCIE_GLOBAL_GEN_CAP_WORKSPACE; - -/*---------------------------------------------------------------------------------------- - * P R O T O T Y P E S O F L O C A L F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ -UINT32 -PcieUtilGetPcieEngineLaneBitMap ( - IN LANE_TYPE LaneType, - IN LANE_PROPERTY LaneProperty, - IN PCIe_ENGINE_CONFIG *Engine - ); - -UINT32 -PcieUtilGetDdiEngineLaneBitMap ( - IN LANE_TYPE LaneType, - IN LANE_PROPERTY LaneProperty, - IN PCIe_ENGINE_CONFIG *Engine - ); - -/*----------------------------------------------------------------------------------------*/ -/** - * Get link state history from HW state machine - * - * - * - * @param[in] Engine Pointer to engine config descriptor - * @param[out] History Buffer to save history - * @param[in] Length Buffer length - * @param[in] Pcie Pointer to global PCIe configuration - */ - -VOID -PcieUtilGetLinkHwStateHistory ( - IN PCIe_ENGINE_CONFIG *Engine, - OUT UINT8 *History, - IN UINT8 Length, - IN PCIe_PLATFORM_CONFIG *Pcie - ) -{ - UINT8 ReadLength; - UINT32 LocalHistory [6]; - UINT16 Index; - ASSERT (Length <= 16); - ASSERT (Length > 0); - if (Length > 6*4) { - Length = 6*4; - } - ReadLength = (Length + 3) / 4; - for (Index = 0; Index < ReadLength; Index++) { - LocalHistory[Index] = PciePortRegisterRead ( - Engine, - DxF0xE4_xA5_ADDRESS + Index, - Pcie - ); - } - LibAmdMemCopy (History, LocalHistory, Length, GnbLibGetHeader (Pcie)); -} - -/*----------------------------------------------------------------------------------------*/ -/** - * Search array for specific pattern - * - * - * @param[in] Buf1 Pointer to source buffer which will be subject of search - * @param[in] Buf1Length Length of the source buffer - * @param[in] Buf2 Pointer to pattern buffer - * @param[in] Buf2Length Length of the pattern buffer - * @retval TRUE Pattern found - * @retval TRUE Pattern not found - */ - -BOOLEAN -PcieUtilSearchArray ( - IN UINT8 *Buf1, - IN UINTN Buf1Length, - IN UINT8 *Buf2, - IN UINTN Buf2Length - ) -{ - UINT8 *CurrentBuf1Ptr; - CurrentBuf1Ptr = Buf1; - while (CurrentBuf1Ptr < (Buf1 + Buf1Length - Buf2Length)) { - UINT8 *SourceBufPtr; - UINT8 *PatternBufPtr; - UINTN PatternBufLength; - SourceBufPtr = CurrentBuf1Ptr; - PatternBufPtr = Buf2; - PatternBufLength = Buf2Length; - while ((*SourceBufPtr++ == *PatternBufPtr++) && (PatternBufLength-- != 0)); - if (PatternBufLength == 0) { - return TRUE; - } - CurrentBuf1Ptr++; - } - return FALSE; -} - - -/*----------------------------------------------------------------------------------------*/ -/** - * Check if link reversed - * - * - * @param[in] HwLinkState Check for HW auto link reversal - * @param[in] Engine Pointer to engine config descriptor - * @param[in] Pcie Pointer to PCIe config descriptor - * @retval TRUE if link reversed - */ -BOOLEAN -PcieUtilIsLinkReversed ( - IN BOOLEAN HwLinkState, - IN PCIe_ENGINE_CONFIG *Engine, - IN PCIe_PLATFORM_CONFIG *Pcie - ) -{ - UINT32 LinkReversal; - - LinkReversal = (Engine->EngineData.StartLane > Engine->EngineData.EndLane) ? 1 : 0; - if (HwLinkState) { - DxF0xE4_x50_STRUCT DxF0xE4_x50; - DxF0xE4_x50.Value = PciePortRegisterRead ( - Engine, - DxF0xE4_x50_ADDRESS, - Pcie - ); - LinkReversal ^= DxF0xE4_x50.Field.PortLaneReversal; - } - return ((LinkReversal & BIT0) != 0) ? TRUE : FALSE; -} - - -/*----------------------------------------------------------------------------------------*/ -/** - * Get link width detected during training - * - * - * - * @param[in] Engine Pointer to engine config descriptor - * @param[in] Pcie Pointer to global PCIe configuration - * @retval Link width - */ -UINT8 -PcieUtilGetLinkWidth ( - IN PCIe_ENGINE_CONFIG *Engine, - IN PCIe_PLATFORM_CONFIG *Pcie - ) -{ - UINT8 LinkWidth; - DxF0xE4_xA2_STRUCT DxF0xE4_xA2; - DxF0xE4_xA2.Value = PciePortRegisterRead ( - Engine, - DxF0xE4_xA2_ADDRESS, - Pcie - ); - switch (DxF0xE4_xA2.Field.LcLinkWidthRd) { - case 0x6: - LinkWidth = 16; - break; - case 0x5: - LinkWidth = 12; - break; - case 0x4: - LinkWidth = 8; - break; - case 0x3: - LinkWidth = 4; - break; - case 0x2: - LinkWidth = 2; - break; - case 0x1: - LinkWidth = 1; - break; - default: - LinkWidth = 0; - } - return LinkWidth; -} - -/*----------------------------------------------------------------------------------------*/ -/** - * Get bitmap of PCIE engine lane of requested type - * - * - * @param[in] LaneType Lane type - * @param[in] LaneProperty Lane Property - * @param[in] Engine Pointer to engine config descriptor - * @retval Lane bitmap - */ - -UINT32 -PcieUtilGetPcieEngineLaneBitMap ( - IN LANE_TYPE LaneType, - IN LANE_PROPERTY LaneProperty, - IN PCIe_ENGINE_CONFIG *Engine - ) -{ - UINT32 LaneBitmap; - UINT8 Width; - UINT16 Offset; - UINT16 LoPhylane; - UINT16 HiPhylane; - PCIe_PLATFORM_CONFIG *Pcie; - - Width = 0; - Offset = 0; - LaneBitmap = 0; - Pcie = (PCIe_PLATFORM_CONFIG *) PcieConfigGetParent (DESCRIPTOR_PLATFORM, &Engine->Header); - - if (PcieConfigIsPcieEngine (Engine)) { - if (LaneType == LaneTypeCore && LaneProperty == LanePropertyConfig) { - Width = PcieConfigGetNumberOfCoreLane (Engine); - Offset = Engine->Type.Port.StartCoreLane; - LaneBitmap = ((1 << Width) - 1) << Offset; - } else if (PcieConfigIsEngineAllocated (Engine)) { - if (LaneType == LaneTypeNativePhy) { - LaneBitmap = PcieUtilGetPcieEngineLaneBitMap (LaneTypePhy, LaneProperty, Engine); - LaneBitmap = PcieFmGetNativePhyLaneBitmap (LaneBitmap, Engine); - } else { - if (LaneType == LaneTypeCore) { - if (LaneProperty == LanePropertyActive) { - Width = PcieUtilGetLinkWidth (Engine, Pcie); - Offset = PcieUtilIsLinkReversed (TRUE, Engine, Pcie) ? (Engine->Type.Port.EndCoreLane - Width + 1) : Engine->Type.Port.StartCoreLane; - } else if (LaneProperty == LanePropertyAllocated) { - Width = PcieConfigGetNumberOfPhyLane (Engine); - Offset = PcieUtilIsLinkReversed (FALSE, Engine, Pcie) ? (Engine->Type.Port.EndCoreLane - Width + 1) : Engine->Type.Port.StartCoreLane; - } - } - if (LaneType == LaneTypePhy) { - LoPhylane = PcieLibGetLoPhyLane (Engine); - HiPhylane = PcieLibGetHiPhyLane (Engine); - if (LaneProperty == LanePropertyActive) { - Width = PcieUtilGetLinkWidth (Engine, Pcie); - Offset = (PcieUtilIsLinkReversed (TRUE, Engine, Pcie) ? (HiPhylane - Width + 1) : LoPhylane) - PcieConfigGetParentWrapper (Engine)->StartPhyLane; - } else if (LaneProperty == LanePropertyAllocated) { - Width = PcieConfigGetNumberOfPhyLane (Engine); - Offset = LoPhylane - PcieConfigGetParentWrapper (Engine)->StartPhyLane; - } - } - LaneBitmap = ((1 << Width) - 1) << Offset; - } - } - } - return LaneBitmap; -} - -/*----------------------------------------------------------------------------------------*/ -/** - * Get bitmap of PCIE engine lane of requested type - * - * - * @param[in] LaneType Lane type - * @param[in] LaneProperty Lane Property - * @param[in] Engine Pointer to engine config descriptor - * @retval Lane bitmap - */ - -UINT32 -PcieUtilGetDdiEngineLaneBitMap ( - IN LANE_TYPE LaneType, - IN LANE_PROPERTY LaneProperty, - IN PCIe_ENGINE_CONFIG *Engine - ) -{ - UINT32 LaneBitmap; - UINT8 Width; - UINT16 Offset; - Width = 0; - Offset = 0; - LaneBitmap = 0; - if (PcieConfigIsDdiEngine (Engine)) { - if (PcieConfigIsEngineAllocated (Engine)) { - if (LaneType == LaneTypePhy && ((LaneProperty == LanePropertyActive && (Engine->InitStatus & INIT_STATUS_DDI_ACTIVE)) || (LaneProperty == LanePropertyAllocated))) { - Width = PcieConfigGetNumberOfPhyLane (Engine); - Offset = PcieLibGetLoPhyLane (Engine) - PcieConfigGetParentWrapper (Engine)->StartPhyLane; - LaneBitmap = ((1 << Width) - 1) << Offset; - } - if (LaneType == LaneTypeNativePhy) { - LaneBitmap = PcieUtilGetDdiEngineLaneBitMap (LaneTypePhy, LaneProperty, Engine); - LaneBitmap = PcieFmGetNativePhyLaneBitmap (LaneBitmap, Engine); - } - } - } - return LaneBitmap; -} - - -/*----------------------------------------------------------------------------------------*/ -/** - * Get bitmap of engine lane of requested type - * - * - * @param[in] IncludeLaneType Include Lane type - * @param[in] ExcludeLaneType Exclude Lane type - * @param[in] Engine Pointer to engine config descriptor - * @retval Lane bitmap - */ - -UINT32 -PcieUtilGetEngineLaneBitMap ( - IN UINT32 IncludeLaneType, - IN UINT32 ExcludeLaneType, - IN PCIe_ENGINE_CONFIG *Engine - ) -{ - UINT32 LaneBitmap; - LaneBitmap = 0; - if (IncludeLaneType & LANE_TYPE_PCIE_LANES) { - if (IncludeLaneType & LANE_TYPE_PCIE_CORE_CONFIG) { - LaneBitmap |= PcieUtilGetPcieEngineLaneBitMap (LaneTypeCore, LanePropertyConfig, Engine); - } - if (IncludeLaneType & LANE_TYPE_PCIE_CORE_ALLOC) { - LaneBitmap |= PcieUtilGetPcieEngineLaneBitMap (LaneTypeCore, LanePropertyAllocated, Engine); - } - if (IncludeLaneType & (LANE_TYPE_PCIE_CORE_ACTIVE | LANE_TYPE_PCIE_CORE_ALLOC_ACTIVE)) { - if (Engine->Type.Port.PortData.LinkHotplug == HotplugEnhanced || PcieConfigCheckPortStatus (Engine, INIT_STATUS_PCIE_PORT_IN_COMPLIANCE)) { - LaneBitmap |= PcieUtilGetPcieEngineLaneBitMap (LaneTypeCore, LanePropertyAllocated, Engine); - } else if (PcieConfigCheckPortStatus (Engine, INIT_STATUS_PCIE_TRAINING_SUCCESS)) { - if (IncludeLaneType & LANE_TYPE_PCIE_CORE_ALLOC_ACTIVE) { - LaneBitmap |= PcieUtilGetPcieEngineLaneBitMap (LaneTypeCore, LanePropertyAllocated, Engine); - } else { - LaneBitmap |= PcieUtilGetPcieEngineLaneBitMap (LaneTypeCore, LanePropertyActive, Engine); - } - } - } - if ((IncludeLaneType & LANE_TYPE_PCIE_SB_CORE_CONFIG) && PcieConfigIsSbPcieEngine (Engine)) { - LaneBitmap |= PcieUtilGetPcieEngineLaneBitMap (LaneTypeCore, LanePropertyConfig, Engine); - } - if ((IncludeLaneType & LANE_TYPE_PCIE_CORE_HOTPLUG) && (Engine->Type.Port.PortData.LinkHotplug != HotplugDisabled)) { - LaneBitmap |= PcieUtilGetPcieEngineLaneBitMap (LaneTypeCore, LanePropertyAllocated, Engine); - } - if (IncludeLaneType & LANE_TYPE_PCIE_PHY) { - LaneBitmap |= PcieUtilGetPcieEngineLaneBitMap (LaneTypePhy, LanePropertyAllocated, Engine); - } - if (IncludeLaneType & LANE_TYPE_PCIE_PHY_NATIVE) { - LaneBitmap |= PcieUtilGetPcieEngineLaneBitMap (LaneTypeNativePhy, LanePropertyAllocated, Engine); - } - if (IncludeLaneType & (LANE_TYPE_PCIE_PHY_NATIVE_ACTIVE | LANE_TYPE_PCIE_PHY_NATIVE_ALLOC_ACTIVE)) { - if (Engine->Type.Port.PortData.LinkHotplug == HotplugEnhanced || PcieConfigCheckPortStatus (Engine, INIT_STATUS_PCIE_PORT_IN_COMPLIANCE)) { - LaneBitmap |= PcieUtilGetPcieEngineLaneBitMap (LaneTypeNativePhy, LanePropertyAllocated, Engine); - } else if (PcieConfigCheckPortStatus (Engine, INIT_STATUS_PCIE_TRAINING_SUCCESS)) { - if (IncludeLaneType & LANE_TYPE_PCIE_PHY_NATIVE_ALLOC_ACTIVE) { - LaneBitmap |= PcieUtilGetPcieEngineLaneBitMap (LaneTypeNativePhy, LanePropertyAllocated, Engine); - } else { - LaneBitmap |= PcieUtilGetPcieEngineLaneBitMap (LaneTypeNativePhy, LanePropertyActive, Engine); - } - } - } - if ((IncludeLaneType & LANE_TYPE_PCIE_PHY_NATIVE_HOTPLUG) && (Engine->Type.Port.PortData.LinkHotplug != HotplugDisabled)) { - LaneBitmap |= PcieUtilGetPcieEngineLaneBitMap (LaneTypeNativePhy, LanePropertyAllocated, Engine); - } - } - if (IncludeLaneType & LANE_TYPE_DDI_LANES) { - if (IncludeLaneType & LANE_TYPE_DDI_PHY) { - LaneBitmap |= PcieUtilGetDdiEngineLaneBitMap (LaneTypePhy, LanePropertyAllocated, Engine); - } - if (IncludeLaneType & LANE_TYPE_DDI_PHY_NATIVE) { - LaneBitmap |= PcieUtilGetDdiEngineLaneBitMap (LaneTypeNativePhy, LanePropertyAllocated, Engine); - } - if (IncludeLaneType & LANE_TYPE_DDI_PHY_NATIVE_ACTIVE) { - LaneBitmap |= PcieUtilGetDdiEngineLaneBitMap (LaneTypeNativePhy, LanePropertyActive, Engine); - } - } - if (ExcludeLaneType != 0) { - LaneBitmap &= (~PcieUtilGetEngineLaneBitMap (ExcludeLaneType, 0, Engine)); - } - return LaneBitmap; -} - -/*----------------------------------------------------------------------------------------*/ -/** - * Get bitmap of Wrapper lane of requested type - * - * - * @param[in] IncludeLaneType Include Lane type - * @param[in] ExcludeLaneType Exclude Lane type - * @param[in] Wrapper Pointer to wrapper config descriptor - * @retval Lane bitmap - */ - -UINT32 -PcieUtilGetWrapperLaneBitMap ( - IN UINT32 IncludeLaneType, - IN UINT32 ExcludeLaneType, - IN PCIe_WRAPPER_CONFIG *Wrapper - ) -{ - PCIe_ENGINE_CONFIG *EngineList; - UINT32 LaneBitmap; - EngineList = PcieConfigGetChildEngine (Wrapper); - LaneBitmap = 0; - if ((IncludeLaneType | ExcludeLaneType) != 0) { - if ((IncludeLaneType & LANE_TYPE_ALL) == LANE_TYPE_ALL) { - LaneBitmap = (1 << (Wrapper->EndPhyLane - Wrapper->StartPhyLane + 1)) - 1; - if (ExcludeLaneType != 0) { - LaneBitmap &= (~PcieUtilGetWrapperLaneBitMap (ExcludeLaneType, 0, Wrapper)); - } - } else { - while (EngineList != NULL) { - LaneBitmap |= PcieUtilGetEngineLaneBitMap (IncludeLaneType, ExcludeLaneType, EngineList); - EngineList = PcieLibGetNextDescriptor (EngineList); - } - } - } - return LaneBitmap; -} - -/*----------------------------------------------------------------------------------------*/ -/** - * Program port register table - * - * - * - * @param[in] Table Pointer to table - * @param[in] Length number of entries - * @param[in] Engine Pointer to engine config descriptor - * @param[in] S3Save Save for S3 flag - * @param[in] Pcie Pointer to global PCIe configuration - * - */ - -VOID -PciePortProgramRegisterTable ( - IN PCIE_PORT_REGISTER_ENTRY *Table, - IN UINTN Length, - IN PCIe_ENGINE_CONFIG *Engine, - IN BOOLEAN S3Save, - IN PCIe_PLATFORM_CONFIG *Pcie - ) -{ - UINTN Index; - UINT32 Value; - for (Index = 0; Index < Length; Index++) { - Value = PciePortRegisterRead ( - Engine, - Table[Index].Reg, - Pcie - ); - Value &= (~Table[Index].Mask); - Value |= Table[Index].Data; - PciePortRegisterWrite ( - Engine, - Table[Index].Reg, - Value, - S3Save, - Pcie - ); - } -} - - -/*----------------------------------------------------------------------------------------*/ -/** - * Lock registers - * - * - * @param[in] Wrapper Pointer to wrapper config descriptor - * @param[in] Pcie Pointer to global PCIe configuration - */ - -VOID -PcieLockRegisters ( - IN PCIe_WRAPPER_CONFIG *Wrapper, - IN PCIe_PLATFORM_CONFIG *Pcie - ) -{ - UINT8 CoreId; - IDS_HDT_CONSOLE (GNB_TRACE, "PcieLockRegisters Enter\n"); - if (PcieLibIsPcieWrapper (Wrapper)) { - for (CoreId = Wrapper->StartPcieCoreId; CoreId <= Wrapper->EndPcieCoreId; CoreId++) { - PcieRegisterWriteField ( - Wrapper, - CORE_SPACE (CoreId, D0F0xE4_CORE_0010_ADDRESS), - D0F0xE4_CORE_0010_HwInitWrLock_OFFSET, - D0F0xE4_CORE_0010_HwInitWrLock_WIDTH, - 0x1, - TRUE, - Pcie - ); - } - } - IDS_HDT_CONSOLE (GNB_TRACE, "PcieLockRegisters Exit\n"); -} - - -/*----------------------------------------------------------------------------------------*/ -/** - * Training state handling - * - * - * - * @param[in] Engine Pointer to engine config descriptor - * @param[in, out] Buffer Indicate if engine in non final state - * @param[in] Pcie Pointer to global PCIe configuration - * - */ - -VOID -STATIC -PcieUtilGlobalGenCapabilityCallback ( - IN PCIe_ENGINE_CONFIG *Engine, - IN OUT VOID *Buffer, - IN PCIe_PLATFORM_CONFIG *Pcie - ) -{ - PCIE_GLOBAL_GEN_CAP_WORKSPACE *GlobalGenCapability; - PCIE_LINK_SPEED_CAP LinkSpeedCapability; - PCIE_HOTPLUG_TYPE HotPlugType; - UINT32 Flags; - - Flags = PCIE_GLOBAL_GEN_CAP_ALL_PORTS; - GlobalGenCapability = (PCIE_GLOBAL_GEN_CAP_WORKSPACE*) Buffer; - LinkSpeedCapability = PcieGen1; - if (PcieConfigCheckPortStatus (Engine, INIT_STATUS_PCIE_TRAINING_SUCCESS)) { - Flags |= PCIE_GLOBAL_GEN_CAP_TRAINED_PORTS; - } - HotPlugType = Engine->Type.Port.PortData.LinkHotplug; - if ((HotPlugType == HotplugBasic) || (HotPlugType == HotplugServer) || (HotPlugType == HotplugEnhanced)) { - Flags |= PCIE_GLOBAL_GEN_CAP_HOTPLUG_PORTS; - } - if ((GlobalGenCapability->Flags & Flags) != 0) { - ASSERT ((GlobalGenCapability->Flags & (PCIE_PORT_GEN_CAP_MAX | PCIE_PORT_GEN_CAP_BOOT)) != 0); - LinkSpeedCapability = PcieFmGetLinkSpeedCap (GlobalGenCapability->Flags, Engine); - if (GlobalGenCapability->LinkSpeedCapability < LinkSpeedCapability) { - GlobalGenCapability->LinkSpeedCapability = LinkSpeedCapability; - } - } -} - -/*----------------------------------------------------------------------------------------*/ -/** - * Determine global GEN capability - * - * - * @param[in] Flags global GEN capability flags - * @param[in] Pcie Pointer to global PCIe configuration - * - */ -PCIE_LINK_SPEED_CAP -PcieUtilGlobalGenCapability ( - IN UINT32 Flags, - IN PCIe_PLATFORM_CONFIG *Pcie - ) -{ - PCIE_LINK_SPEED_CAP GlobalCapability; - PCIE_GLOBAL_GEN_CAP_WORKSPACE GlobalGenCap; - - GlobalGenCap.LinkSpeedCapability = PcieGen1; - GlobalGenCap.Flags = Flags; - PcieConfigRunProcForAllEngines ( - DESCRIPTOR_ALLOCATED | DESCRIPTOR_PCIE_ENGINE, - PcieUtilGlobalGenCapabilityCallback, - &GlobalGenCap, - Pcie - ); - - GlobalCapability = GlobalGenCap.LinkSpeedCapability; - - return GlobalCapability; -} diff --git a/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieInitLibV1/PcieUtilityLib.h b/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieInitLibV1/PcieUtilityLib.h deleted file mode 100644 index bf4aa23827..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieInitLibV1/PcieUtilityLib.h +++ /dev/null @@ -1,131 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * PCIe utility. Various supporting functions. - * - * - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: GNB - * @e \$Revision: 48318 $ @e \$Date: 2011-03-08 01:48:31 +0800 (Tue, 08 Mar 2011) $ - * - */ -/* -***************************************************************************** -* -* Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* *************************************************************************** -* -*/ - -#ifndef _PCIEUTILLIB_H_ -#define _PCIEUTILLIB_H_ - -/// Core lanes -typedef enum { - AllCoreLanes, ///< All core lanes - AllocatedCoreLanes, ///< Allocated core lanes - ActiveCoreLanes, ///< Active core lanes - HotplugCoreLanes, ///< Hot plug core lanes - SbCoreLanes, ///< South bridge core lanes -} CORE_LANES; - -/// DDI lanes -typedef enum { - DdiAllLanes, ///< All DDI Lanes - DdiActiveLanes ///< Active DDI Lanes -} DDI_LANES; - -BOOLEAN -PcieUtilSearchArray ( - IN UINT8 *Buf1, - IN UINTN Buf1Length, - IN UINT8 *Buf2, - IN UINTN Buf2Length - ); - -VOID -PcieUtilGetLinkHwStateHistory ( - IN PCIe_ENGINE_CONFIG *Engine, - OUT UINT8 *History, - IN UINT8 Length, - IN PCIe_PLATFORM_CONFIG *Pcie - ); - - -BOOLEAN -PcieUtilIsLinkReversed ( - IN BOOLEAN HwLinkState, - IN PCIe_ENGINE_CONFIG *Engine, - IN PCIe_PLATFORM_CONFIG *Pcie - ); - - -UINT8 -PcieUtilGetLinkWidth ( - IN PCIe_ENGINE_CONFIG *Engine, - IN PCIe_PLATFORM_CONFIG *Pcie - ); - - -UINT32 -PcieUtilGetEngineLaneBitMap ( - IN UINT32 IncludeLaneType, - IN UINT32 ExcludeLaneType, - IN PCIe_ENGINE_CONFIG *Engine - ); - -UINT32 -PcieUtilGetWrapperLaneBitMap ( - IN UINT32 IncludeLaneType, - IN UINT32 ExcludeLaneType, - IN PCIe_WRAPPER_CONFIG *Wrapper - ); - -VOID -PciePortProgramRegisterTable ( - IN PCIE_PORT_REGISTER_ENTRY *Table, - IN UINTN Length, - IN PCIe_ENGINE_CONFIG *Engine, - IN BOOLEAN S3Save, - IN PCIe_PLATFORM_CONFIG *Pcie - ); - -VOID -PcieLockRegisters ( - IN PCIe_WRAPPER_CONFIG *Wrapper, - IN PCIe_PLATFORM_CONFIG *Pcie - ); - -PCIE_LINK_SPEED_CAP -PcieUtilGlobalGenCapability ( - IN UINT32 Flags, - IN PCIe_PLATFORM_CONFIG *Pcie - ); - -#endif diff --git a/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieInitLibV1/PcieWrapperRegAcc.c b/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieInitLibV1/PcieWrapperRegAcc.c deleted file mode 100644 index 576d2d8809..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieInitLibV1/PcieWrapperRegAcc.c +++ /dev/null @@ -1,291 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * Supporting services to access PCIe wrapper/core/PIF/PHY indirect register spaces - * - * - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: GNB - * @e \$Revision: 48452 $ @e \$Date: 2011-03-09 12:50:44 +0800 (Wed, 09 Mar 2011) $ - * - */ -/* -***************************************************************************** -* -* Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* *************************************************************************** -* -*/ - -#include "AGESA.h" -#include "Ids.h" -#include "Gnb.h" -#include "GnbPcie.h" -#include "GnbPcieFamServices.h" -#include "GnbCommonLib.h" -#include "GnbPcieConfig.h" -#include "GnbPcieInitLibV1.h" -#include "Filecode.h" -#define FILECODE PROC_GNB_MODULES_GNBPCIEINITLIBV1_PCIEWRAPPERREGACC_FILECODE -/*----------------------------------------------------------------------------------------*/ -/** - * Read PCIe register value. - * - * Support for unify register access through index/data pair on GNB - * - * @param[in] Wrapper Pointer to Wrapper descriptor - * @param[in] Address Register address - * @param[in] Pcie Pointer to global PCIe configuration - * @retval Register Value - */ -UINT32 -PcieRegisterRead ( - IN PCIe_WRAPPER_CONFIG *Wrapper, - IN UINT32 Address, - IN PCIe_PLATFORM_CONFIG *Pcie - ) -{ - return PcieSiliconRegisterRead (PcieConfigGetParentSilicon (Wrapper), Address, Pcie); -} - -/*----------------------------------------------------------------------------------------*/ -/** - * Read PCIe register value. - * - * Support for unify register access through index/data pair on GNB - * - * @param[in] Silicon Pointer to silicon descriptor - * @param[in] Address Register address - * @param[in] Pcie Pointer to global PCIe configuration - * @retval Register Value - */ - -UINT32 -PcieSiliconRegisterRead ( - IN PCIe_SILICON_CONFIG *Silicon, - IN UINT32 Address, - IN PCIe_PLATFORM_CONFIG *Pcie - ) -{ - UINT32 Value; - GnbLibPciWrite (Silicon->Address.AddressValue | 0xE0, AccessWidth32, &Address, GnbLibGetHeader (Pcie)); - GnbLibPciRead (Silicon->Address.AddressValue | 0xE4, AccessWidth32, &Value, GnbLibGetHeader (Pcie)); - return Value; -} - -/*----------------------------------------------------------------------------------------*/ -/** - * Write PCIe register value. - * - * Support for unify register access through index/data pair on GNB - * - * @param[in] Wrapper Pointer to wrapper descriptor - * @param[in] Address Register address - * @param[in] Value New register value - * @param[in] S3Save Save register for S3 (True/False) - * @param[in] Pcie Pointer to global PCIe configuration - */ -VOID -PcieRegisterWrite ( - IN PCIe_WRAPPER_CONFIG *Wrapper, - IN UINT32 Address, - IN UINT32 Value, - IN BOOLEAN S3Save, - IN PCIe_PLATFORM_CONFIG *Pcie - ) -{ - PcieSiliconRegisterWrite ( - PcieConfigGetParentSilicon (Wrapper), - Address, - Value, - S3Save, - Pcie - ); -} - -/*----------------------------------------------------------------------------------------*/ -/** - * Write PCIe register value. - * - * Support for unify register access through index/data pair on GNB - * - * @param[in] Silicon Pointer to silicon descriptor - * @param[in] Address Register address - * @param[in] Value New register value - * @param[in] S3Save Save register for S3 (True/False) - * @param[in] Pcie Pointer to global PCIe configuration - */ -VOID -PcieSiliconRegisterWrite ( - IN PCIe_SILICON_CONFIG *Silicon, - IN UINT32 Address, - IN UINT32 Value, - IN BOOLEAN S3Save, - IN PCIe_PLATFORM_CONFIG *Pcie - ) -{ - IDS_HDT_CONSOLE (PCIE_HOSTREG_TRACE, " *WR %s (%d:%d:%d):0x%08x = 0x%08x\n", - PcieFmDebugGetHostRegAddressSpaceString (Silicon, (UINT16) (Address >> 16)), - Silicon->Address.Address.Bus, - Silicon->Address.Address.Device, - Silicon->Address.Address.Function, - Address, - Value - ); - GnbLibPciWrite (Silicon->Address.AddressValue | 0xE0, S3Save ? AccessS3SaveWidth32 : AccessWidth32, &Address, GnbLibGetHeader (Pcie)); - GnbLibPciWrite (Silicon->Address.AddressValue | 0xE4, S3Save ? AccessS3SaveWidth32 : AccessWidth32, &Value, GnbLibGetHeader (Pcie)); -} -/*----------------------------------------------------------------------------------------*/ -/** - * Read PCIe register field. - * - * Support for unify register access through index/data pair on GNB - * - * @param[in] Wrapper Pointer to wrapper descriptor - * @param[in] Address Register address - * @param[in] FieldOffset Field offset - * @param[in] FieldWidth Field width - * @param[in] Pcie Pointer to global PCIe configuration - * @retval Register field value - */ - -UINT32 -PcieRegisterReadField ( - IN PCIe_WRAPPER_CONFIG *Wrapper, - IN UINT32 Address, - IN UINT8 FieldOffset, - IN UINT8 FieldWidth, - IN PCIe_PLATFORM_CONFIG *Pcie - ) -{ - UINT32 Value; - Value = PcieRegisterRead (Wrapper, Address, Pcie); - Value = (Value >> FieldOffset) & (~(0xFFFFFFFF << FieldWidth)); - return Value; -} - -/*----------------------------------------------------------------------------------------*/ -/** - * Write PCIe register field. - * - * Support for unify register access through index/data pair on GNB - * - * @param[in] Wrapper Pointer to wrapper descriptor - * @param[in] Address Register address - * @param[in] FieldOffset Field offset - * @param[in] FieldWidth Field width - * @param[in] Value Value to write - * @param[in] S3Save Save register for S3 (True/False) - * @param[in] Pcie Pointer to global PCIe configuration - */ - - -VOID -PcieRegisterWriteField ( - IN PCIe_WRAPPER_CONFIG *Wrapper, - IN UINT32 Address, - IN UINT8 FieldOffset, - IN UINT8 FieldWidth, - IN UINT32 Value, - IN BOOLEAN S3Save, - IN PCIe_PLATFORM_CONFIG *Pcie - ) -{ - UINT32 TempValue; - UINT32 Mask; - TempValue = PcieRegisterRead (Wrapper, Address, Pcie); - Mask = (~(0xFFFFFFFF << FieldWidth)); - Value &= Mask; - TempValue &= (~(Mask << FieldOffset)); - PcieRegisterWrite (Wrapper, Address, TempValue | (Value << FieldOffset), S3Save, Pcie); -} - -/*----------------------------------------------------------------------------------------*/ -/** - * Read/Modify/Write PCIe register. - * - * Support for unify register access through index/data pair on GNB - * - * @param[in] Wrapper Pointer to wrapper descriptor - * @param[in] Address Register address - * @param[in] AndMask Value & (~AndMask) - * @param[in] OrMask Value | OrMask - * @param[in] S3Save Save register for S3 (True/False) - * @param[in] Pcie Pointer to global PCIe configuration - */ - -VOID -PcieRegisterRMW ( - IN PCIe_WRAPPER_CONFIG *Wrapper, - IN UINT32 Address, - IN UINT32 AndMask, - IN UINT32 OrMask, - IN BOOLEAN S3Save, - IN PCIe_PLATFORM_CONFIG *Pcie - ) -{ - PcieSiliconRegisterRMW ( - PcieConfigGetParentSilicon (Wrapper), - Address, - AndMask, - OrMask, - S3Save, - Pcie - ); -} - -/*----------------------------------------------------------------------------------------*/ -/** - * Read/Modify/Write PCIe register. - * - * Support for unify register access through index/data pair on GNB - * - * @param[in] Silicon Pointer to silicon descriptor - * @param[in] Address Register address - * @param[in] AndMask Value & (~AndMask) - * @param[in] OrMask Value | OrMask - * @param[in] S3Save Save register for S3 (True/False) - * @param[in] Pcie Pointer to global PCIe configuration - */ - -VOID -PcieSiliconRegisterRMW ( - IN PCIe_SILICON_CONFIG *Silicon, - IN UINT32 Address, - IN UINT32 AndMask, - IN UINT32 OrMask, - IN BOOLEAN S3Save, - IN PCIe_PLATFORM_CONFIG *Pcie - ) -{ - UINT32 Value; - Value = PcieSiliconRegisterRead (Silicon, Address, Pcie); - Value = (Value & (~AndMask)) | OrMask; - PcieSiliconRegisterWrite (Silicon, Address, Value, S3Save, Pcie); -} \ No newline at end of file diff --git a/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieInitLibV1/PcieWrapperRegAcc.h b/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieInitLibV1/PcieWrapperRegAcc.h deleted file mode 100644 index 033e281df1..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieInitLibV1/PcieWrapperRegAcc.h +++ /dev/null @@ -1,127 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * Supporting services to access PCIe wrapper/core/PIF/PHY indirect register spaces - * - * - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: GNB - * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $ - * - */ -/* -***************************************************************************** -* -* Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* *************************************************************************** -* -*/ - -#ifndef _PCIEWRAPPERREGACC_H_ -#define _PCIEWRAPPERREGACC_H_ - -//#define WRAP_SPACE(w, x) (0x01300000 | (w << 16) | (x)) -//#define CORE_SPACE(c, x) (0x00010000 | (c << 24) | (x)) -//#define PHY_SPACE(w, p, x) (0x00200000 | ((p + 1) << 24) | (w << 16) | (x)) -//#define PIF_SPACE(w, p, x) (0x00100000 | ((p + 1) << 24) | (w << 16) | (x)) -#define IMP_SPACE(x) (0x01080000 | (x)) - -UINT32 -PcieRegisterRead ( - IN PCIe_WRAPPER_CONFIG *Wrapper, - IN UINT32 Address, - IN PCIe_PLATFORM_CONFIG *Pcie - ); - -VOID -PcieRegisterWrite ( - IN PCIe_WRAPPER_CONFIG *Wrapper, - IN UINT32 Address, - IN UINT32 Value, - IN BOOLEAN S3Save, - IN PCIe_PLATFORM_CONFIG *Pcie - ); - -UINT32 -PcieRegisterReadField ( - IN PCIe_WRAPPER_CONFIG *Wrapper, - IN UINT32 Address, - IN UINT8 FieldOffset, - IN UINT8 FieldWidth, - IN PCIe_PLATFORM_CONFIG *Pcie - ); - -VOID -PcieRegisterWriteField ( - IN PCIe_WRAPPER_CONFIG *Wrapper, - IN UINT32 Address, - IN UINT8 FieldOffset, - IN UINT8 FieldWidth, - IN UINT32 Value, - IN BOOLEAN S3Save, - IN PCIe_PLATFORM_CONFIG *Pcie - ); - -VOID -PcieRegisterRMW ( - IN PCIe_WRAPPER_CONFIG *Wrapper, - IN UINT32 Address, - IN UINT32 AndMask, - IN UINT32 OrMask, - IN BOOLEAN S3Save, - IN PCIe_PLATFORM_CONFIG *Pcie - ); - -UINT32 -PcieSiliconRegisterRead ( - IN PCIe_SILICON_CONFIG *Silicon, - IN UINT32 Address, - IN PCIe_PLATFORM_CONFIG *Pcie - ); - -VOID -PcieSiliconRegisterWrite ( - IN PCIe_SILICON_CONFIG *Silicon, - IN UINT32 Address, - IN UINT32 Value, - IN BOOLEAN S3Save, - IN PCIe_PLATFORM_CONFIG *Pcie - ); - -VOID -PcieSiliconRegisterRMW ( - IN PCIe_SILICON_CONFIG *Silicon, - IN UINT32 Address, - IN UINT32 AndMask, - IN UINT32 OrMask, - IN BOOLEAN S3Save, - IN PCIe_PLATFORM_CONFIG *Pcie - ); - -#endif diff --git a/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieTrainingV1/GnbPcieTrainingV1.h b/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieTrainingV1/GnbPcieTrainingV1.h deleted file mode 100644 index 9b1891762b..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieTrainingV1/GnbPcieTrainingV1.h +++ /dev/null @@ -1,51 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * PCIe training library - * - * - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: GNB - * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $ - * - */ -/* -***************************************************************************** -* -* Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* *************************************************************************** -* -*/ -#ifndef _GNBPCIETRAININGV1_H_ -#define _GNBPCIETRAININGV1_H_ - -#include "PcieTraining.h" -#include "PcieWorkarounds.h" - -#endif diff --git a/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieTrainingV1/Makefile.inc b/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieTrainingV1/Makefile.inc deleted file mode 100644 index 5b6b04d092..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieTrainingV1/Makefile.inc +++ /dev/null @@ -1,2 +0,0 @@ -libagesa-y += PcieTraining.c -libagesa-y += PcieWorkarounds.c diff --git a/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieTrainingV1/PcieTraining.c b/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieTrainingV1/PcieTraining.c deleted file mode 100644 index 48d59afbdd..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieTrainingV1/PcieTraining.c +++ /dev/null @@ -1,864 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * PCIe link training - * - * - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: GNB - * @e \$Revision: 48452 $ @e \$Date: 2011-03-09 12:50:44 +0800 (Wed, 09 Mar 2011) $ - * - */ -/* -***************************************************************************** -* -* Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* *************************************************************************** -* -*/ - -/*---------------------------------------------------------------------------------------- - * M O D U L E S U S E D - *---------------------------------------------------------------------------------------- - */ -#include "AGESA.h" -#include "Ids.h" -#include "amdlib.h" -#include "GeneralServices.h" -#include "Gnb.h" -#include "GnbPcie.h" -#include "GnbCommonLib.h" -#include "GnbPcieConfig.h" -#include "GnbPcieInitLibV1.h" -#include "PcieWorkarounds.h" -#include "PcieTraining.h" -#include "GnbRegistersLN.h" -#include "Filecode.h" -#define FILECODE PROC_GNB_MODULES_GNBPCIETRAININGV1_PCIETRAINING_FILECODE -/*---------------------------------------------------------------------------------------- - * D E F I N I T I O N S A N D M A C R O S - *---------------------------------------------------------------------------------------- - */ - - -/*---------------------------------------------------------------------------------------- - * T Y P E D E F S A N D S T R U C T U R E S - *---------------------------------------------------------------------------------------- - */ - - -/*---------------------------------------------------------------------------------------- - * P R O T O T Y P E S O F L O C A L F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ -VOID -PcieSetResetStateOnEngines ( - IN PCIe_ENGINE_CONFIG *Engine, - IN OUT VOID *Buffer, - IN PCIe_PLATFORM_CONFIG *Pcie - ); - -VOID -PcieTrainingCheckResetDuration ( - IN PCIe_ENGINE_CONFIG *CurrentEngine, - IN PCIe_PLATFORM_CONFIG *Pcie - ); - -VOID -PcieTrainingDeassertReset ( - IN PCIe_ENGINE_CONFIG *CurrentEngine, - IN PCIe_PLATFORM_CONFIG *Pcie - ); - -VOID -PcieTrainingBrokenLine ( - IN PCIe_ENGINE_CONFIG *CurrentEngine, - IN PCIe_PLATFORM_CONFIG *Pcie - ); - -VOID -PcieTrainingGen2Fail ( - IN PCIe_ENGINE_CONFIG *CurrentEngine, - IN PCIe_PLATFORM_CONFIG *Pcie - ); - -/* - VOID -STATIC -PcieTrainingDebugDumpPortState ( - IN PCIe_ENGINE_CONFIG *CurrentEngine, - IN PCIe_PLATFORM_CONFIG *Pcie - ); -*/ - - -/*----------------------------------------------------------------------------------------*/ -/** - * Set link State - * - * - * @param[in] CurrentEngine Pointer to engine config descriptor - * @param[in] State State to set - * @param[in] UpdateTimeStamp Update time stamp - * @param[in] Pcie Pointer to global PCIe configuration - * - */ -VOID -PcieTrainingSetPortState ( - IN PCIe_ENGINE_CONFIG *CurrentEngine, - IN UINT8 State, - IN BOOLEAN UpdateTimeStamp, - IN PCIe_PLATFORM_CONFIG *Pcie - ) -{ - UINT32 TimeStamp; - CurrentEngine->Type.Port.State = State; - if (UpdateTimeStamp) { - TimeStamp = PcieTimerGetTimeStamp (Pcie); - CurrentEngine->Type.Port.TimeStamp = TimeStamp; - } - GNB_DEBUG_CODE ( - PcieTrainingDebugDumpPortState (CurrentEngine, Pcie) - ); -} - - -/*----------------------------------------------------------------------------------------*/ -/** - * Set state for all engines connected to same reset ID - * - * - * - * @param[in] Engine Pointer to engine config descriptor - * @param[in, out] Buffer Pointer to Reset Id - * @param[in] Pcie Pointer to global PCIe configuration - * - */ -VOID -PcieSetResetStateOnEngines ( - IN PCIe_ENGINE_CONFIG *Engine, - IN OUT VOID *Buffer, - IN PCIe_PLATFORM_CONFIG *Pcie - ) -{ - UINT8 ResetId; - ResetId = *(UINT8 *)Buffer; - if (Engine->Type.Port.PortData.ResetId == ResetId) { - PcieTrainingSetPortState (Engine, LinkStateResetDuration, TRUE, Pcie); - } -} - - -/*----------------------------------------------------------------------------------------*/ -/** - * Assert GPIO port reset. - * - * Transition to LinkStateResetDuration state - * - * @param[in] CurrentEngine Pointer to engine config descriptor - * @param[in] Pcie Pointer to global PCIe configuration - * - */ -VOID -STATIC -PcieTrainingAssertReset ( - IN PCIe_ENGINE_CONFIG *CurrentEngine, - IN PCIe_PLATFORM_CONFIG *Pcie - ) -{ - PCIe_SLOT_RESET_INFO ResetInfo; - ResetInfo.ResetControl = AssertSlotReset; - ResetInfo.ResetId = CurrentEngine->Type.Port.PortData.ResetId; - LibAmdMemCopy (&ResetInfo.StdHeader, GnbLibGetHeader (Pcie), sizeof (AMD_CONFIG_PARAMS), GnbLibGetHeader (Pcie)); - AgesaPcieSlotResetControl (0, &ResetInfo); - PcieConfigRunProcForAllEngines ( - DESCRIPTOR_ALLOCATED | DESCRIPTOR_PCIE_ENGINE, - PcieSetResetStateOnEngines, - (VOID *)&CurrentEngine->Type.Port.PortData.ResetId, - Pcie - ); -} - - -/*----------------------------------------------------------------------------------------*/ -/** - * Check for reset duration - * - * Transition to LinkStateResetDuration state - * - * @param[in] CurrentEngine Pointer to engine config descriptor - * @param[in] Pcie Pointer to global PCIe configuration - * - */ -VOID -PcieTrainingCheckResetDuration ( - IN PCIe_ENGINE_CONFIG *CurrentEngine, - IN PCIe_PLATFORM_CONFIG *Pcie - ) -{ - UINT32 TimeStamp; - TimeStamp = PcieTimerGetTimeStamp (Pcie); - if (TIMESTAMPS_DELTA (TimeStamp, CurrentEngine->Type.Port.TimeStamp) >= Pcie->LinkGpioResetAssertionTime) { - PcieTrainingSetPortState (CurrentEngine, LinkStateResetExit, FALSE, Pcie); - } -} - -/*----------------------------------------------------------------------------------------*/ -/** - * Deassert GPIO port reset. - * - * Transition to LinkStateResetDuration state - * - * @param[in] CurrentEngine Pointer to engine config descriptor - * @param[in] Pcie Platform configuration - * - */ -VOID -PcieTrainingDeassertReset ( - IN PCIe_ENGINE_CONFIG *CurrentEngine, - IN PCIe_PLATFORM_CONFIG *Pcie - ) -{ - PCIe_SLOT_RESET_INFO ResetInfo; - ResetInfo.ResetControl = DeassertSlotReset; - ResetInfo.ResetId = CurrentEngine->Type.Port.PortData.ResetId; - LibAmdMemCopy (&ResetInfo.StdHeader, GnbLibGetHeader (Pcie), sizeof (AMD_CONFIG_PARAMS), GnbLibGetHeader (Pcie)); - AgesaPcieSlotResetControl (0, &ResetInfo); - PcieTrainingSetPortState (CurrentEngine, LinkTrainingResetTimeout, TRUE, Pcie); -} - -/*----------------------------------------------------------------------------------------*/ -/** - * Check for after reset deassertion timeout - * - * - * @param[in] CurrentEngine Pointer to engine config descriptor - * @param[in] Pcie Pointer to global PCIe configuration - * - */ -VOID -STATIC -PcieTrainingCheckResetTimeout ( - IN PCIe_ENGINE_CONFIG *CurrentEngine, - IN PCIe_PLATFORM_CONFIG *Pcie - ) -{ - UINT32 TimeStamp; - TimeStamp = PcieTimerGetTimeStamp (Pcie); - if (TIMESTAMPS_DELTA (TimeStamp, CurrentEngine->Type.Port.TimeStamp) >= Pcie->LinkResetToTrainingTime) { - PcieTrainingSetPortState (CurrentEngine, LinkStateReleaseTraining, FALSE, Pcie); - } -} - - -/*----------------------------------------------------------------------------------------*/ -/** - * Release training - * - * - * @param[in] CurrentEngine Pointer to engine config descriptor - * @param[in] Pcie Pointer to global PCIe configuration - * - */ -VOID -STATIC -PcieTrainingRelease ( - IN PCIe_ENGINE_CONFIG *CurrentEngine, - IN PCIe_PLATFORM_CONFIG *Pcie - ) -{ - UINT8 LinkTrainingState; - PcieRegisterWriteField ( - PcieConfigGetParentWrapper (CurrentEngine), - WRAP_SPACE (PcieConfigGetParentWrapper (CurrentEngine)->WrapId, D0F0xE4_WRAP_0800_ADDRESS + 0x100 * CurrentEngine->Type.Port.PortId), - D0F0xE4_WRAP_0800_HoldTraining_OFFSET, - D0F0xE4_WRAP_0800_HoldTraining_WIDTH, - 0, - FALSE, - Pcie - ); - if (CurrentEngine->Type.Port.PortData.MiscControls.LinkComplianceMode == 0x1) { - LinkTrainingState = LinkStateCompliance; - } else { - LinkTrainingState = LinkStateDetectPresence; - } - PcieTrainingSetPortState (CurrentEngine, LinkTrainingState, TRUE, Pcie); -} - -/*----------------------------------------------------------------------------------------*/ -/** - * Detect presence of any EP on the link - * - * - * @param[in] CurrentEngine Pointer to engine config descriptor - * @param[in] Pcie Pointer to global PCIe configuration - * - */ - -VOID -STATIC -PcieTrainingDetectPresence ( - IN PCIe_ENGINE_CONFIG *CurrentEngine, - IN PCIe_PLATFORM_CONFIG *Pcie - ) -{ - UINT8 LinkHwStateHistory[4]; - UINT32 TimeStamp; - PcieUtilGetLinkHwStateHistory (CurrentEngine, &LinkHwStateHistory[0], 4, Pcie); - if (LinkHwStateHistory[0] > 4) { - PcieTrainingSetPortState (CurrentEngine, LinkStateDetecting, TRUE, Pcie); - return; - } - TimeStamp = PcieTimerGetTimeStamp (Pcie); - if (TIMESTAMPS_DELTA (TimeStamp, CurrentEngine->Type.Port.TimeStamp) >= Pcie->LinkReceiverDetectionPooling) { - PcieTrainingSetPortState (CurrentEngine, LinkStateDeviceNotPresent, FALSE, Pcie); - } -} - -UINT8 FailPattern1 [] = {0x2a, 0x6}; -UINT8 FailPattern2 [] = {0x2a, 0x9}; - -/*----------------------------------------------------------------------------------------*/ -/** - * Detect Link State - * - * - * @param[in] CurrentEngine Pointer to engine config descriptor - * @param[in] Pcie Pointer to global PCIe configuration - * - */ - -VOID -STATIC -PcieTrainingDetectLinkState ( - IN PCIe_ENGINE_CONFIG *CurrentEngine, - IN PCIe_PLATFORM_CONFIG *Pcie - ) -{ - UINT8 LinkHwStateHistory[16]; - UINT32 TimeStamp; - UINT8 LinkTrainingState; - PcieUtilGetLinkHwStateHistory (CurrentEngine, &LinkHwStateHistory[0], 4, Pcie); - if (LinkHwStateHistory[0] == 0x10) { - PcieTrainingSetPortState (CurrentEngine, LinkStateL0, FALSE, Pcie); - return; - }; - TimeStamp = PcieTimerGetTimeStamp (Pcie); - if (TIMESTAMPS_DELTA (TimeStamp, CurrentEngine->Type.Port.TimeStamp) >= Pcie->LinkL0Pooling) { - LinkTrainingState = LinkStateTrainingFail; - PcieUtilGetLinkHwStateHistory (CurrentEngine, &LinkHwStateHistory[0], 16, Pcie); - if (LinkHwStateHistory[0] == 0x7) { - LinkTrainingState = LinkStateCompliance; - } else if (PcieUtilSearchArray (LinkHwStateHistory, sizeof (LinkHwStateHistory), FailPattern1, sizeof (FailPattern1))) { - LinkTrainingState = LinkStateBrokenLane; - } else if (PcieUtilSearchArray (LinkHwStateHistory, sizeof (LinkHwStateHistory), FailPattern2, sizeof (FailPattern2))) { - LinkTrainingState = LinkStateGen2Fail; - } - PcieTrainingSetPortState (CurrentEngine, LinkTrainingState, FALSE, Pcie); - } -} - -/*----------------------------------------------------------------------------------------*/ -/** - * Broken Lane - * - * - * @param[in] CurrentEngine Pointer to engine config descriptor - * @param[in] Pcie Pointer to global PCIe configuration - * - */ - -VOID -PcieTrainingBrokenLine ( - IN PCIe_ENGINE_CONFIG *CurrentEngine, - IN PCIe_PLATFORM_CONFIG *Pcie - ) -{ - UINT8 CurrentLinkWidth; - UINT8 LinkTrainingState; - CurrentLinkWidth = PcieUtilGetLinkWidth (CurrentEngine, Pcie); - if (CurrentLinkWidth < PcieConfigGetNumberOfPhyLane (CurrentEngine) && CurrentLinkWidth > 0) { - CurrentEngine->InitStatus |= INIT_STATUS_PCIE_PORT_BROKEN_LANE_RECOVERY; - PcieTopologyReduceLinkWidth (CurrentLinkWidth, CurrentEngine, Pcie); - LinkTrainingState = LinkStateResetAssert; - PutEventLog ( - AGESA_WARNING, - GNB_EVENT_BROKEN_LANE_RECOVERY, - CurrentEngine->Type.Port.Address.AddressValue, - 0, - 0, - 0, - GnbLibGetHeader (Pcie) - ); - } else { - LinkTrainingState = LinkStateGen2Fail; - } - PcieTrainingSetPortState (CurrentEngine, LinkTrainingState, FALSE, Pcie); -} - -/*----------------------------------------------------------------------------------------*/ -/** - * Check if link fail because device does not support Gen2 - * - * - * @param[in] CurrentEngine Pointer to engine config descriptor - * @param[in] Pcie Pointer to global PCIe configuration - * - */ -VOID -PcieTrainingGen2Fail ( - IN PCIe_ENGINE_CONFIG *CurrentEngine, - IN PCIe_PLATFORM_CONFIG *Pcie - ) -{ - UINT8 LinkTrainingState; - if (CurrentEngine->Type.Port.PortData.MiscControls.LinkSafeMode != PcieGen1) { - PcieConfigUpdatePortStatus (CurrentEngine, INIT_STATUS_PCIE_PORT_GEN2_RECOVERY, 0); - CurrentEngine->Type.Port.PortData.MiscControls.LinkSafeMode = PcieGen1; - PcieLinkSafeMode (CurrentEngine, Pcie); - LinkTrainingState = LinkStateResetAssert; - PutEventLog ( - AGESA_WARNING, - GNB_EVENT_BROKEN_LANE_RECOVERY, - CurrentEngine->Type.Port.Address.AddressValue, - 0, - 0, - 0, - GnbLibGetHeader (Pcie) - ); - } else { - LinkTrainingState = LinkStateTrainingFail; - } - PcieTrainingSetPortState (CurrentEngine, LinkTrainingState, FALSE, Pcie); -} - -/*----------------------------------------------------------------------------------------*/ -/** - * Link in L0 - * - * - * @param[in] CurrentEngine Pointer to engine config descriptor - * @param[in] Pcie Pointer to global PCIe configuration - * - */ -VOID -STATIC -PcieCheckLinkL0 ( - IN PCIe_ENGINE_CONFIG *CurrentEngine, - IN PCIe_PLATFORM_CONFIG *Pcie - ) -{ - PcieTrainingSetPortState (CurrentEngine, LinkStateVcoNegotiation, TRUE, Pcie); -} -/*----------------------------------------------------------------------------------------*/ -/** - * Check if link fail because device does not support Gen X - * - * - * @param[in] CurrentEngine Pointer to engine config descriptor - * @param[in] Pcie Pointer to global PCIe configuration - * - */ -VOID -STATIC -PcieTrainingCheckVcoNegotiation ( - IN PCIe_ENGINE_CONFIG *CurrentEngine, - IN PCIe_PLATFORM_CONFIG *Pcie - ) -{ - UINT32 TimeStamp; - DxF0x128_STRUCT DxF0x128; - TimeStamp = PcieTimerGetTimeStamp (Pcie); - GnbLibPciRead (CurrentEngine->Type.Port.Address.AddressValue | DxF0x128_ADDRESS, AccessWidth32, &DxF0x128, GnbLibGetHeader (Pcie)); - if (DxF0x128.Field.VcNegotiationPending == 0) { - UINT16 NumberOfPhyLane; - NumberOfPhyLane = PcieConfigGetNumberOfPhyLane (CurrentEngine); - if (Pcie->GfxCardWorkaround == GfxWorkaroundEnable && NumberOfPhyLane >= 8) { - // Limit exposure of workaround to x8 and x16 port. - PcieTrainingSetPortState (CurrentEngine, LinkStateGfxWorkaround, TRUE, Pcie); - } else { - PcieTrainingSetPortState (CurrentEngine, LinkStateTrainingSuccess, FALSE, Pcie); - } - return; - } - if (TIMESTAMPS_DELTA (TimeStamp, CurrentEngine->Type.Port.TimeStamp) >= 1000 * 1000) { - PcieTrainingSetPortState (CurrentEngine, LinkStateRetrain, FALSE, Pcie); - } -} - -/*----------------------------------------------------------------------------------------*/ -/** - * Check if for GFX workaround condition - * - * - * @param[in] CurrentEngine Pointer to engine config descriptor - * @param[in] Pcie Pointer to global PCIe configuration - * - */ -VOID -STATIC -PcieTrainingGfxWorkaround ( - IN PCIe_ENGINE_CONFIG *CurrentEngine, - IN PCIe_PLATFORM_CONFIG *Pcie - ) -{ - UINT32 TimeStamp; - GFX_WORKAROUND_STATUS GfxWorkaroundStatus; - TimeStamp = PcieTimerGetTimeStamp (Pcie); - - GfxWorkaroundStatus = PcieGfxCardWorkaround (CurrentEngine->Type.Port.Address, GnbLibGetHeader (Pcie)); - switch (GfxWorkaroundStatus) { - case GFX_WORKAROUND_DEVICE_NOT_READY: - if (TIMESTAMPS_DELTA (TimeStamp, CurrentEngine->Type.Port.TimeStamp) >= 1000 * 2000) { - PcieTrainingSetPortState (CurrentEngine, LinkStateTrainingFail, TRUE, Pcie); - } - break; - case GFX_WORKAROUND_SUCCESS: - PcieTrainingSetPortState (CurrentEngine, LinkStateTrainingSuccess, FALSE, Pcie); - break; - case GFX_WORKAROUND_RESET_DEVICE: - if (CurrentEngine->Type.Port.GfxWrkRetryCount < 5) { - CurrentEngine->Type.Port.GfxWrkRetryCount++; - PcieTrainingSetPortState (CurrentEngine, LinkStateResetAssert, TRUE, Pcie); - } else { - PcieTrainingSetPortState (CurrentEngine, LinkStateTrainingFail, TRUE, Pcie); - } - break; - default: - ASSERT (FALSE); - } -} - -/*----------------------------------------------------------------------------------------*/ -/** - * Retrain link - * - * - * @param[in] CurrentEngine Pointer to engine config descriptor - * @param[in] Pcie Pointer to global PCIe configuration - * - */ -VOID -STATIC -PcieTrainingRetrainLink ( - IN PCIe_ENGINE_CONFIG *CurrentEngine, - IN PCIe_PLATFORM_CONFIG *Pcie - ) -{ - PciePortRegisterWriteField ( - CurrentEngine, - DxF0xE4_xA2_ADDRESS, - DxF0xE4_xA2_LcReconfigNow_OFFSET, - DxF0xE4_xA2_LcReconfigNow_WIDTH, - 1, - FALSE, - Pcie - ); - PcieTrainingSetPortState (CurrentEngine, LinkStateDetecting, TRUE, Pcie); -} - -/*----------------------------------------------------------------------------------------*/ -/** - * Training fail on this port - * - * - * @param[in] CurrentEngine Pointer to engine config descriptor - * @param[in] Pcie Pointer to global PCIe configuration - * - */ -VOID -STATIC -PcieTrainingFail ( - IN PCIe_ENGINE_CONFIG *CurrentEngine, - IN PCIe_PLATFORM_CONFIG *Pcie - ) -{ - PcieConfigUpdatePortStatus (CurrentEngine, INIT_STATUS_PCIE_PORT_TRAINING_FAIL, 0); - PcieTrainingSetPortState (CurrentEngine, LinkStateDeviceNotPresent, FALSE, Pcie); -} - -/*----------------------------------------------------------------------------------------*/ -/** - * Links training success - * - * - * @param[in] CurrentEngine Pointer to engine config descriptor - * @param[in] Pcie Pointer to global PCIe configuration - * - */ - -VOID -STATIC -PcieTrainingSuccess ( - IN PCIe_ENGINE_CONFIG *CurrentEngine, - IN PCIe_PLATFORM_CONFIG *Pcie - ) -{ - PcieConfigUpdatePortStatus (CurrentEngine, INIT_STATUS_PCIE_TRAINING_SUCCESS, 0); - PcieTrainingSetPortState (CurrentEngine, LinkStateTrainingCompleted, FALSE, Pcie); -} - -/*----------------------------------------------------------------------------------------*/ -/** - * Links in compliance - * - * - * @param[in] CurrentEngine Pointer to engine config descriptor - * @param[in] Pcie Pointer to global PCIe configuration - * - */ -VOID -STATIC -PcieTrainingCompliance ( - IN PCIe_ENGINE_CONFIG *CurrentEngine, - IN PCIe_PLATFORM_CONFIG *Pcie - ) -{ - PcieConfigUpdatePortStatus (CurrentEngine, INIT_STATUS_PCIE_PORT_IN_COMPLIANCE, 0); - PcieTrainingSetPortState (CurrentEngine, LinkStateTrainingCompleted, FALSE, Pcie); -} - -/*----------------------------------------------------------------------------------------*/ -/** - * PCie EP not present - * - * - * @param[in] CurrentEngine Pointer to engine config descriptor - * @param[in] Pcie Pointer to global PCIe configuration - * - */ -VOID -STATIC -PcieTrainingNotPresent ( - IN PCIe_ENGINE_CONFIG *CurrentEngine, - IN PCIe_PLATFORM_CONFIG *Pcie - ) -{ - if ((CurrentEngine->Type.Port.PortData.LinkHotplug == HotplugEnhanced) || (CurrentEngine->Type.Port.PortData.LinkHotplug == HotplugServer)) { - } else { - PcieRegisterWriteField ( - PcieConfigGetParentWrapper (CurrentEngine), - WRAP_SPACE (PcieConfigGetParentWrapper (CurrentEngine)->WrapId, D0F0xE4_WRAP_0800_ADDRESS + 0x100 * CurrentEngine->Type.Port.PortId), - D0F0xE4_WRAP_0800_HoldTraining_OFFSET, - D0F0xE4_WRAP_0800_HoldTraining_WIDTH, - 1, - FALSE, - Pcie - ); - } - PcieTrainingSetPortState (CurrentEngine, LinkStateTrainingCompleted, FALSE, Pcie); -} - -/*----------------------------------------------------------------------------------------*/ -/** - * Final state. Port training completed. - * - * Initialization status recorded in PCIe_ENGINE_CONFIG.InitStatus - * - * @param[in] CurrentEngine Pointer to engine config descriptor - * @param[in] Pcie Pointer to global PCIe configuration - * - */ -VOID -STATIC -PcieTrainingCompleted ( - IN PCIe_ENGINE_CONFIG *CurrentEngine, - IN PCIe_PLATFORM_CONFIG *Pcie - ) -{ -} - -/*----------------------------------------------------------------------------------------*/ -/** - * Training state handling - * - * - * - * @param[in] Engine Pointer to engine config descriptor - * @param[in, out] Buffer Indicate if engine in non final state - * @param[in] Pcie Pointer to global PCIe configuration - * - */ - -VOID -STATIC -PcieTrainingPortCallback ( - IN PCIe_ENGINE_CONFIG *Engine, - IN OUT VOID *Buffer, - IN PCIe_PLATFORM_CONFIG *Pcie - ) -{ - BOOLEAN *TrainingComplete; - TrainingComplete = (BOOLEAN *) Buffer; - if (Engine->Type.Port.State < Pcie->TrainingExitState) { - *TrainingComplete = FALSE; - } else { - return; - } - switch (Engine->Type.Port.State) { - case LinkStateResetAssert: - PcieTrainingAssertReset (Engine, Pcie); - break; - case LinkStateResetDuration: - PcieTrainingCheckResetDuration (Engine, Pcie); - break; - case LinkStateResetExit: - PcieTrainingDeassertReset (Engine, Pcie); - break; - case LinkTrainingResetTimeout: - PcieTrainingCheckResetTimeout (Engine, Pcie); - break; - case LinkStateReleaseTraining: - PcieTrainingRelease (Engine, Pcie); - break; - case LinkStateDetectPresence: - PcieTrainingDetectPresence (Engine, Pcie); - break; - case LinkStateDetecting: - PcieTrainingDetectLinkState (Engine, Pcie); - break; - case LinkStateBrokenLane: - PcieTrainingBrokenLine (Engine, Pcie); - break; - case LinkStateGen2Fail: - PcieTrainingGen2Fail (Engine, Pcie); - break; - case LinkStateL0: - PcieCheckLinkL0 (Engine, Pcie); - break; - case LinkStateVcoNegotiation: - PcieTrainingCheckVcoNegotiation (Engine, Pcie); - break; - case LinkStateRetrain: - PcieTrainingRetrainLink (Engine, Pcie); - break; - case LinkStateTrainingFail: - PcieTrainingFail (Engine, Pcie); - break; - case LinkStateGfxWorkaround: - PcieTrainingGfxWorkaround (Engine, Pcie); - break; - case LinkStateTrainingSuccess: - PcieTrainingSuccess (Engine, Pcie); - break; - case LinkStateCompliance: - PcieTrainingCompliance (Engine, Pcie); - break; - case LinkStateDeviceNotPresent: - PcieTrainingNotPresent (Engine, Pcie); - break; - case LinkStateTrainingCompleted: - PcieTrainingCompleted (Engine, Pcie); - break; - default: - break; - } - -} - - -/*----------------------------------------------------------------------------------------*/ -/** - * Main link training procedure - * - * Port end up in three possible state LinkStateTrainingNotPresent/LinkStateCompliance/ - * LinkStateTrainingSuccess - * - * @param[in] Pcie Pointer to global PCIe configuration - * @retval AGESA_STATUS - * - */ - -AGESA_STATUS -PcieTraining ( - IN PCIe_PLATFORM_CONFIG *Pcie - ) -{ - AGESA_STATUS Status; - BOOLEAN TrainingComplete; - Status = AGESA_SUCCESS; - IDS_HDT_CONSOLE (GNB_TRACE, "PcieTraining Enter\n"); - do { - TrainingComplete = TRUE; - PcieConfigRunProcForAllEngines ( - DESCRIPTOR_ALLOCATED | DESCRIPTOR_PCIE_ENGINE, - PcieTrainingPortCallback, - &TrainingComplete, - Pcie - ); - } while (!TrainingComplete); - IDS_HDT_CONSOLE (GNB_TRACE, "PcieTraining Exit [%x]\n", Status); - return Status; -} - -/*----------------------------------------------------------------------------------------*/ -/** - * Helper function to dump port state on state transition - * - * - * @param[in] CurrentEngine Pointer to engine config descriptor - * @param[in] Pcie Pointer to global PCIe configuration - * - */ - -/* -VOID -STATIC -PcieTrainingDebugDumpPortState ( - IN PCIe_ENGINE_CONFIG *CurrentEngine, - IN PCIe_PLATFORM_CONFIG *Pcie - ) -{ - IDS_HDT_CONSOLE (PCIE_MISC, " Port %d:%d:%d State [%s] Time Stamp [%d]\n", - CurrentEngine->Type.Port.Address.Address.Bus, - CurrentEngine->Type.Port.Address.Address.Device, - CurrentEngine->Type.Port.Address.Address.Function, - (CurrentEngine->Type.Port.State == LinkStateTrainingFail) ? "LinkStateTrainingFail " : ( - (CurrentEngine->Type.Port.State == LinkStateTrainingSuccess) ? "LinkStateTrainingSuccess " : ( - (CurrentEngine->Type.Port.State == LinkStateCompliance) ? "LinkStateCompliance " : ( - (CurrentEngine->Type.Port.State == LinkStateDeviceNotPresent) ? "LinkStateDeviceNotPresent" : ( - (CurrentEngine->Type.Port.State == LinkStateResetAssert) ? "LinkStateResetAssert " : ( - (CurrentEngine->Type.Port.State == LinkStateResetDuration) ? "LinkStateResetDuration " : ( - (CurrentEngine->Type.Port.State == LinkStateResetDuration) ? "LinkStateResetExit " : ( - (CurrentEngine->Type.Port.State == LinkTrainingResetTimeout) ? "LinkTrainingResetTimeout " : ( - (CurrentEngine->Type.Port.State == LinkStateReleaseTraining) ? "LinkStateReleaseTraining " : ( - (CurrentEngine->Type.Port.State == LinkStateDetectPresence) ? "LinkStateDetectPresence " : ( - (CurrentEngine->Type.Port.State == LinkStateDetecting) ? "LinkStateDetecting " : ( - (CurrentEngine->Type.Port.State == LinkStateBrokenLane) ? "LinkStateBrokenLane " : ( - (CurrentEngine->Type.Port.State == LinkStateGen2Fail) ? "LinkStateGen2Fail " : ( - (CurrentEngine->Type.Port.State == LinkStateL0) ? "LinkStateL0 " : ( - (CurrentEngine->Type.Port.State == LinkStateVcoNegotiation) ? "LinkStateVcoNegotiation " : ( - (CurrentEngine->Type.Port.State == LinkStateGfxWorkaround) ? "LinkStateGfxWorkaround " : ( - (CurrentEngine->Type.Port.State == LinkStateTrainingCompleted) ? "LinkStateTrainingComplete" : ( - (CurrentEngine->Type.Port.State == LinkStateRetrain) ? "LinkStateRetrain " : ( - (CurrentEngine->Type.Port.State == LinkStateResetExit) ? "LinkStateResetExit " : "Unknown")))))))))))))))))), - CurrentEngine->Type.Port.TimeStamp - ); -} -*/ diff --git a/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieTrainingV1/PcieTraining.h b/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieTrainingV1/PcieTraining.h deleted file mode 100644 index 302c78adb4..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieTrainingV1/PcieTraining.h +++ /dev/null @@ -1,63 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * PCIe link training - * - * - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: GNB - * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $ - * - */ -/* -***************************************************************************** -* -* Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* *************************************************************************** -* -*/ -#ifndef _PCIETRAINING_H_ -#define _PCIETRAINING_H_ - - -AGESA_STATUS -PcieTraining ( - IN PCIe_PLATFORM_CONFIG *Pcie - ); - -VOID -PcieTrainingSetPortState ( - IN PCIe_ENGINE_CONFIG *CurrentEngine, - IN UINT8 State, - IN BOOLEAN UpdateTimeStamp, - IN PCIe_PLATFORM_CONFIG *Pcie - ); - -#endif - diff --git a/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieTrainingV1/PcieWorkarounds.c b/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieTrainingV1/PcieWorkarounds.c deleted file mode 100644 index 891463189e..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieTrainingV1/PcieWorkarounds.c +++ /dev/null @@ -1,375 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * Various workarounds - * - * - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: GNB - * @e \$Revision: 48452 $ @e \$Date: 2011-03-09 12:50:44 +0800 (Wed, 09 Mar 2011) $ - * - */ -/* -***************************************************************************** -* -* Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* *************************************************************************** -* -*/ - -/*---------------------------------------------------------------------------------------- - * M O D U L E S U S E D - *---------------------------------------------------------------------------------------- - */ -#include "AGESA.h" -#include "Ids.h" -#include "amdlib.h" -#include "Gnb.h" -#include "GnbPcie.h" -#include "GnbCommonLib.h" -#include "GnbPcieConfig.h" -#include "GnbRegistersLN.h" -#include "PcieWorkarounds.h" -#include "Filecode.h" -#define FILECODE PROC_GNB_MODULES_GNBPCIETRAININGV1_PCIEWORKAROUNDS_FILECODE -/*---------------------------------------------------------------------------------------- - * D E F I N I T I O N S A N D M A C R O S - *---------------------------------------------------------------------------------------- - */ - -extern BUILD_OPT_CFG UserOptions; - -/*---------------------------------------------------------------------------------------- - * T Y P E D E F S A N D S T R U C T U R E S - *---------------------------------------------------------------------------------------- - */ -AGESA_STATUS -PcieConfigureBridgeResources ( - IN PCI_ADDR Port, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -VOID -PcieFreeBridgeResources ( - IN PCI_ADDR Port, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -GFX_WORKAROUND_STATUS -PcieDeskewWorkaround ( - IN PCI_ADDR Device, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -GFX_WORKAROUND_STATUS -PcieNvWorkaround ( - IN PCI_ADDR Device, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -VOID -PcieProgramCpuMmio ( - OUT UINT32 *SaveValues, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -VOID -PcieRestoreCpuMmio ( - IN UINT32 *RestoreValues, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -BOOLEAN -PcieIsDeskewCardDetected ( - IN UINT16 DeviceId - ); - -/*---------------------------------------------------------------------------------------- - * P R O T O T Y P E S O F L O C A L F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ - -/*----------------------------------------------------------------------------------------*/ -/** - * ATI RV370/RV380 card workaround - * - * - * - * @param[in] Port PCI addreses of the port - * @param[in] StdHeader Standard configuration header - * @retval GFX_WORKAROUND_STATUS Return the GFX Card Workaround status - */ -GFX_WORKAROUND_STATUS -PcieGfxCardWorkaround ( - IN PCI_ADDR Port, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - GFX_WORKAROUND_STATUS Status; - UINT16 DeviceId; - UINT16 VendorId; - UINT8 DevClassCode; - UINT32 SaveValueData[2]; - PCI_ADDR Ep; - - Status = GFX_WORKAROUND_SUCCESS; - - Ep.AddressValue = MAKE_SBDFO (0, Port.Address.Bus + Port.Address.Device, 0, 0, 0); - if (PcieConfigureBridgeResources (Port, StdHeader) == AGESA_SUCCESS) { - GnbLibPciRead (Ep.AddressValue | 0x00, AccessWidth16, &DeviceId, StdHeader); - Status = GFX_WORKAROUND_DEVICE_NOT_READY; - if (DeviceId != 0xffff) { - GnbLibPciRead (Ep.AddressValue | 0x02, AccessWidth16, &VendorId, StdHeader); - if (VendorId != 0xffff) { - GnbLibPciRead (Ep.AddressValue | 0x0B, AccessWidth8, &DevClassCode, StdHeader); - Status = GFX_WORKAROUND_SUCCESS; - if (DevClassCode == 3) { - PcieProgramCpuMmio (SaveValueData, StdHeader); - if (VendorId == 0x1002 && PcieIsDeskewCardDetected (DeviceId)) { - Status = PcieDeskewWorkaround (Ep, StdHeader); - } else if (VendorId == 0x10DE) { - Status = PcieNvWorkaround (Ep, StdHeader); - } - PcieRestoreCpuMmio (SaveValueData, StdHeader); - } - } - } - PcieFreeBridgeResources (Port, StdHeader); - } - return Status; -} - - -/*----------------------------------------------------------------------------------------*/ -/** - * RV370/RV380 Deskew workaround - * - * - * - * @param[in] Device Pcie Address of ATI RV370/RV380 card. - * @param[in] StdHeader Standard configuration header - */ -GFX_WORKAROUND_STATUS -PcieDeskewWorkaround ( - IN PCI_ADDR Device, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - UINTN MmioBase; - UINT16 MmioData1; - UINT32 MmioData2; - - MmioBase = UserOptions.CfgTempPcieMmioBaseAddress; - if (MmioBase == 0) { - return GFX_WORKAROUND_SUCCESS; - } - GnbLibPciWrite (Device.AddressValue | 0x18, AccessWidth32, &MmioBase, StdHeader); - GnbLibPciRMW (Device.AddressValue | 0x04, AccessWidth8 , ~(UINT32)BIT1, BIT1, StdHeader); - GnbLibMemRMW (MmioBase + 0x120, AccessWidth16, 0, 0xb700, StdHeader); - GnbLibMemRead (MmioBase + 0x120, AccessWidth16, &MmioData1, StdHeader); - if (MmioData1 == 0xb700) { - GnbLibMemRMW (MmioBase + 0x124, AccessWidth32, 0, 0x13, StdHeader); - GnbLibMemRead (MmioBase + 0x124, AccessWidth32, &MmioData2, StdHeader); - if (MmioData2 == 0x13) { - GnbLibMemRead (MmioBase + 0x12C, AccessWidth32, &MmioData2, StdHeader); - if (MmioData2 & BIT8) { - return GFX_WORKAROUND_RESET_DEVICE; - } - } - } - GnbLibPciRMW (Device.AddressValue | 0x04, AccessWidth8, ~(UINT32)BIT1, 0x0, StdHeader); - GnbLibPciRMW (Device.AddressValue | 0x18, AccessWidth32, 0x0, 0x0, StdHeader); - - return GFX_WORKAROUND_SUCCESS; -} - -/*----------------------------------------------------------------------------------------*/ -/** - * NV43 card workaround (lost SSID) - * - * - * - * @param[in] Device Pcie Address of NV43 card. - * @param[in] StdHeader Standard configuration header - */ -GFX_WORKAROUND_STATUS -PcieNvWorkaround ( - IN PCI_ADDR Device, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - UINT32 DeviceSSID; - UINTN MmioBase; - UINT32 MmioData3; - - MmioBase = UserOptions.CfgTempPcieMmioBaseAddress; - if (MmioBase == 0) { - return GFX_WORKAROUND_SUCCESS; - } - GnbLibPciRMW (Device.AddressValue | 0x30, AccessWidth32, 0x0, ((UINT32)MmioBase) | 1, StdHeader); - GnbLibPciRMW (Device.AddressValue | 0x4, AccessWidth8, 0x0, 0x2, StdHeader); - GnbLibPciRead (Device.AddressValue | 0x2c, AccessWidth32, &DeviceSSID, StdHeader); - GnbLibMemRead (MmioBase + 0x54, AccessWidth32, &MmioData3, StdHeader); - if (DeviceSSID != MmioData3) { - GnbLibPciRMW (Device.AddressValue | 0x40, AccessWidth32, 0x0, MmioData3, StdHeader); - } - GnbLibPciRMW (Device.AddressValue | 0x30, AccessWidth32, 0x0, 0x0, StdHeader); - GnbLibPciRMW (Device.AddressValue | 0x4, AccessWidth8, 0x0, 0x0, StdHeader); - return GFX_WORKAROUND_SUCCESS; -} - -/*----------------------------------------------------------------------------------------*/ -/** - * Allocate temporary resources for Pcie P2P bridge - * - * - * - * @param[in] Port Pci Address of Port to initialize. - * @param[in] StdHeader Standard configuration header - */ -AGESA_STATUS -PcieConfigureBridgeResources ( - IN PCI_ADDR Port, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - UINT32 Value; - UINT32 MmioBase; - - MmioBase = UserOptions.CfgTempPcieMmioBaseAddress; - if (MmioBase == 0) { - return AGESA_WARNING; - } - Value = Port.Address.Bus + ((Port.Address.Bus + Port.Address.Device) << 8) + ((Port.Address.Bus + Port.Address.Device) << 16); - GnbLibPciWrite (Port.AddressValue | DxF0x18_ADDRESS, AccessWidth32, &Value, StdHeader); - Value = MmioBase + (MmioBase >> 16); - GnbLibPciWrite (Port.AddressValue | DxF0x20_ADDRESS, AccessWidth32, &Value, StdHeader); - Value = 0x000fff0; - GnbLibPciWrite (Port.AddressValue | DxF0x24_ADDRESS, AccessWidth32, &Value, StdHeader); - Value = 0x2; - GnbLibPciWrite (Port.AddressValue | DxF0x04_ADDRESS, AccessWidth8, &Value, StdHeader); - return AGESA_SUCCESS; -} - -/*----------------------------------------------------------------------------------------*/ -/** - * Free temporary resources for Pcie P2P bridge - * - * - * - * @param[in] Port Pci Address of Port to clear resource allocation. - * @param[in] StdHeader Standard configuration header - */ -VOID -PcieFreeBridgeResources ( - IN PCI_ADDR Port, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - UINT32 Value; - - Value = 0; - GnbLibPciWrite (Port.AddressValue | DxF0x04_ADDRESS, AccessWidth8, &Value, StdHeader); - GnbLibPciWrite (Port.AddressValue | DxF0x18_ADDRESS, AccessWidth32, &Value, StdHeader); - GnbLibPciWrite (Port.AddressValue | DxF0x20_ADDRESS, AccessWidth32, &Value, StdHeader); - GnbLibPciWrite (Port.AddressValue | DxF0x24_ADDRESS, AccessWidth32, &Value, StdHeader); - -} - - -/*----------------------------------------------------------------------------------------*/ -/* - * Save CPU MMIO register - * - * - * - * @param[out] UINT32 SaveValues - * @param[in] StdHeader Standard configuration header - * - */ -VOID -PcieProgramCpuMmio ( - OUT UINT32 *SaveValues, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - //Save CPU MMIO Register - GnbLibPciRead (MAKE_SBDFO (0, 0, 0x18, 0x1, 0xB8), AccessWidth32, SaveValues, StdHeader); - GnbLibPciRead (MAKE_SBDFO (0, 0, 0x18, 0x1, 0xBC), AccessWidth32, SaveValues + 1, StdHeader); - - //Write Temp Pcie MMIO to CPU - GnbLibPciRMW (MAKE_SBDFO (0, 0, 0x18, 0x1, 0xBC), AccessWidth32, 0, (UserOptions.CfgTempPcieMmioBaseAddress >> 16) << 8, StdHeader); - GnbLibPciRMW (MAKE_SBDFO (0, 0, 0x18, 0x1, 0xB8), AccessWidth32, 0, ((UserOptions.CfgTempPcieMmioBaseAddress >> 16) << 8) | 0x3, StdHeader); - -} - -/*----------------------------------------------------------------------------------------*/ -/* - * Restore CPU MMIO register - * - * - * - * @param[in] PCIe_PLATFORM_CONFIG Pcie - * @param[in] StdHeader Standard configuration header - */ -VOID -PcieRestoreCpuMmio ( - IN UINT32 *RestoreValues, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - //Restore CPU MMIO Register - GnbLibPciRMW (MAKE_SBDFO (0, 0, 0x18, 0x1, 0xB8), AccessWidth32, 0, *RestoreValues, StdHeader); - GnbLibPciRMW (MAKE_SBDFO (0, 0, 0x18, 0x1, 0xBC), AccessWidth32, 0, *(RestoreValues + 1), StdHeader); - -} - -/*----------------------------------------------------------------------------------------*/ -/* - * Check if card required test for deskew workaround - * - * - * - * @param[in] DeviceId Device ID - */ - -BOOLEAN -PcieIsDeskewCardDetected ( - IN UINT16 DeviceId - ) -{ - if ((DeviceId >= 0x3150 && DeviceId <= 0x3152) || (DeviceId == 0x3154) || - (DeviceId == 0x3E50) || (DeviceId == 0x3E54) || - ((DeviceId & 0xfff8) == 0x5460) || ((DeviceId & 0xfff8) == 0x5B60)) { - return TRUE; - } - return FALSE; -} - - diff --git a/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieTrainingV1/PcieWorkarounds.h b/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieTrainingV1/PcieWorkarounds.h deleted file mode 100644 index 14bc3350ea..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieTrainingV1/PcieWorkarounds.h +++ /dev/null @@ -1,55 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * Various workarounds - * - * - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: GNB - * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $ - * - */ -/* -***************************************************************************** -* -* Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* *************************************************************************** -* -*/ -#ifndef _PCIEWORKAROUNDS_H_ -#define _PCIEWORKAROUNDS_H_ - -GFX_WORKAROUND_STATUS -PcieGfxCardWorkaround ( - IN PCI_ADDR Port, - IN AMD_CONFIG_PARAMS *StdHeader - ); - - -#endif diff --git a/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbSbLib/GnbSbLib.c b/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbSbLib/GnbSbLib.c deleted file mode 100644 index 898521ae96..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbSbLib/GnbSbLib.c +++ /dev/null @@ -1,132 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * SB services - * - * - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: GNB - * @e \$Revision: 39931 $ @e \$Date: 2010-10-16 18:19:16 -0700 (Sat, 16 Oct 2010) $ - * - */ -/* -***************************************************************************** -* -* Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* *************************************************************************** -* -*/ - -/*---------------------------------------------------------------------------------------- - * M O D U L E S U S E D - *---------------------------------------------------------------------------------------- - */ -#include "AGESA.h" -#include "Ids.h" -#include "amdlib.h" -#include "Gnb.h" -#include "GnbSbLib.h" -#include "GnbCommonLib.h" -#include "Filecode.h" -#define FILECODE PROC_GNB_MODULES_GNBSBLIB_GNBSBLIB_FILECODE -/*---------------------------------------------------------------------------------------- - * D E F I N I T I O N S A N D M A C R O S - *---------------------------------------------------------------------------------------- - */ - - -/*---------------------------------------------------------------------------------------- - * T Y P E D E F S A N D S T R U C T U R E S - *---------------------------------------------------------------------------------------- - */ - - -/*---------------------------------------------------------------------------------------- - * P R O T O T Y P E S O F L O C A L F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ - - - -/*----------------------------------------------------------------------------------------*/ -/** - *Get SB IOAPIC Base Address - * - * - * @param[in] StdHeader Standard configuration header - * @retval APIC base address - */ -UINT32 -SbGetSbIoApicBaseAddress ( - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - UINT32 ApicBaseAddress; - GnbLibIndirectIoBlockRead (0xCD6, 0xCD7, AccessWidth8, 0x34, 4, &ApicBaseAddress, StdHeader); - return ApicBaseAddress & 0xfffffff8; -} - -/*----------------------------------------------------------------------------------------*/ -/** - *Get SB MMIO Base Address - * - * - * @param[in] StdHeader Standard configuration header - * @retval MMIO base address - */ -UINT32 -SbGetSbMmioBaseAddress ( - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - UINT32 MmioBaseAddress; - GnbLibIndirectIoBlockRead (0xCD6, 0xCD7, AccessWidth8, 0x24, 4, &MmioBaseAddress, StdHeader); - return MmioBaseAddress & 0xfffffffc; -} - - -/*----------------------------------------------------------------------------------------*/ -/** - * Get Alink config address - * - * @param[in] StdHeader Standard configuration header - * @retval Alink base address - */ -/*----------------------------------------------------------------------------------------*/ - -UINT16 -SbGetAlinkIoAddress ( - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - - UINT16 AlinkPortAddress; - GnbLibIndirectIoBlockRead (0xCD6, 0xCD7, AccessWidth8, 0xE0, 2, &AlinkPortAddress, StdHeader); - return AlinkPortAddress; -} diff --git a/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbSbLib/GnbSbLib.h b/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbSbLib/GnbSbLib.h deleted file mode 100644 index ed9e32fcea..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbSbLib/GnbSbLib.h +++ /dev/null @@ -1,78 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * SB services - * - * - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: GNB - * @e \$Revision: 39931 $ @e \$Date: 2010-10-16 18:19:16 -0700 (Sat, 16 Oct 2010) $ - * - */ -/* -***************************************************************************** -* -* Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* *************************************************************************** -* -*/ -#ifndef _GNBSBLIB_H_ -#define _GNBSBLIB_H_ - -#include "GnbPcie.h" - -UINT32 -SbGetSbIoApicBaseAddress ( - IN AMD_CONFIG_PARAMS *StdHeader - ); - -UINT32 -SbGetSbMmioBaseAddress ( - IN AMD_CONFIG_PARAMS *StdHeader - ); - -UINT16 -SbGetAlinkIoAddress ( - IN AMD_CONFIG_PARAMS *StdHeader - ); - -AGESA_STATUS -SbPcieInitAspm ( - IN PCIE_ASPM_TYPE Aspm, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -AGESA_STATUS -SbPcieLinkAspmControl ( - IN PCIe_ENGINE_CONFIG *Engine, - IN PCIe_PLATFORM_CONFIG *Pcie - ); - - -#endif diff --git a/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbSbLib/GnbSbPcie.c b/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbSbLib/GnbSbPcie.c deleted file mode 100644 index 76c4a0bbe9..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbSbLib/GnbSbPcie.c +++ /dev/null @@ -1,142 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * GNB-SB link procedure - * - * - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: GNB - * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 01:16:51 -0800 (Wed, 22 Dec 2010) $ - * - */ -/* -***************************************************************************** -* -* Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* *************************************************************************** -* -*/ - -/*---------------------------------------------------------------------------------------- - * M O D U L E S U S E D - *---------------------------------------------------------------------------------------- - */ -#include "AGESA.h" -#include "Ids.h" -#include "amdlib.h" -#include "Gnb.h" -#include "GnbPcie.h" -#include "GnbCommonLib.h" -#include "GnbPcieInitLibV1.h" -#include "GnbSbLib.h" -#include "Filecode.h" -#define FILECODE PROC_GNB_MODULES_GNBSBLIB_GNBSBPCIE_FILECODE -/*---------------------------------------------------------------------------------------- - * D E F I N I T I O N S A N D M A C R O S - *---------------------------------------------------------------------------------------- - */ - - -/*---------------------------------------------------------------------------------------- - * T Y P E D E F S A N D S T R U C T U R E S - *---------------------------------------------------------------------------------------- - */ - - -/*---------------------------------------------------------------------------------------- - * P R O T O T Y P E S O F L O C A L F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ - - -/*----------------------------------------------------------------------------------------*/ -/** - * Enable/Disable ASPM on GNB-SB link - * - * - * - * @param[in] Engine Pointer to engine config descriptor - * @param[in] Pcie Pointer to global PCIe configuration - * - */ - -AGESA_STATUS -SbPcieLinkAspmControl ( - IN PCIe_ENGINE_CONFIG *Engine, - IN PCIe_PLATFORM_CONFIG *Pcie - ) -{ - AGESA_STATUS Status; - PCIE_ASPM_TYPE Aspm; - - Aspm = Engine->Type.Port.PortData.LinkAspm; - - Status = SbPcieInitAspm (Aspm, GnbLibGetHeader (Pcie)); - if (Status != AGESA_SUCCESS) { - return AGESA_UNSUPPORTED; - } - - PcieAspmEnableOnFunction (Engine->Type.Port.Address, Aspm, GnbLibGetHeader (Pcie)); - return AGESA_SUCCESS; -} - -/*----------------------------------------------------------------------------------------*/ -/** - * Init SB ASPM. - * Enable ASPM states on SB - * - * - * @param[in] Aspm ASPM bitmap. - * @param[in] StdHeader Standard configuration header - */ -/*----------------------------------------------------------------------------------------*/ - -AGESA_STATUS -SbPcieInitAspm ( - IN PCIE_ASPM_TYPE Aspm, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - UINT16 AlinkPort; - - AlinkPort = SbGetAlinkIoAddress (StdHeader); - ASSERT (AlinkPort != 0); - if (AlinkPort == 0) { - return AGESA_UNSUPPORTED; - } - GnbLibIoRMW (AlinkPort, AccessS3SaveWidth32, 0x0, 0x40000038, StdHeader); - GnbLibIoRMW (AlinkPort + 4, AccessS3SaveWidth32, 0x0, 0xA0, StdHeader); - GnbLibIoRMW (AlinkPort, AccessS3SaveWidth32, 0x0, 0x4000003c, StdHeader); - GnbLibIoRMW (AlinkPort + 4, AccessS3SaveWidth32, 0xffff00ff, 0x6900, StdHeader); - GnbLibIoRMW (AlinkPort, AccessS3SaveWidth32, 0x0, 0x80000068, StdHeader); - GnbLibIoRMW (AlinkPort + 4, AccessS3SaveWidth32, 0xfffffffc, Aspm, StdHeader); - return AGESA_SUCCESS; -} - - diff --git a/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbSbLib/Makefile.inc b/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbSbLib/Makefile.inc deleted file mode 100644 index e5434c2041..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbSbLib/Makefile.inc +++ /dev/null @@ -1,2 +0,0 @@ -libagesa-y += GnbSbLib.c -libagesa-y += GnbSbPcie.c diff --git a/src/vendorcode/amd/agesa/f12/Proc/GNB/Nb/Family/LN/F12NbLclkDpm.c b/src/vendorcode/amd/agesa/f12/Proc/GNB/Nb/Family/LN/F12NbLclkDpm.c deleted file mode 100644 index 5034ed535f..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/GNB/Nb/Family/LN/F12NbLclkDpm.c +++ /dev/null @@ -1,347 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * LCLK DPM initialization - * - * - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: GNB - * @e \$Revision: 39007 $ @e \$Date: 2010-10-05 00:32:54 +0800 (Tue, 05 Oct 2010) $ - * - */ -/* -***************************************************************************** -* -* Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* *************************************************************************** -* -*/ - -/*---------------------------------------------------------------------------------------- - * M O D U L E S U S E D - *---------------------------------------------------------------------------------------- - */ - -#include "AGESA.h" -#include "amdlib.h" -#include "Ids.h" -#include "heapManager.h" -#include "Gnb.h" -#include "GnbFuseTable.h" -#include "GnbPcie.h" -#include "GnbCommonLib.h" -#include "GnbPcieConfig.h" -#include "GnbRegistersLN.h" -#include "OptionGnb.h" -#include "GfxLib.h" -#include "NbConfigData.h" -#include "NbSmuLib.h" -#include "NbLclkDpm.h" -#include "NbFamilyServices.h" -#include "Filecode.h" - -#define FILECODE PROC_GNB_NB_FAMILY_LN_F12NBLCLKDPM_FILECODE -/*---------------------------------------------------------------------------------------- - * D E F I N I T I O N S A N D M A C R O S - *---------------------------------------------------------------------------------------- - */ - -extern GNB_BUILD_OPTIONS GnbBuildOptions; -/*---------------------------------------------------------------------------------------- - * T Y P E D E F S A N D S T R U C T U R E S - *---------------------------------------------------------------------------------------- - */ - -UINT32 LclkDpmCacTable [] = { - 0x0, - 0x0, - 0x0, - 0x0 -}; - -UINT32 LclkDpmActivityThresholdTable [] = { - 0x100, - 0x40FFFF, - 0x40FFFF, - 0x0 -}; - -/*---------------------------------------------------------------------------------------- - * P R O T O T Y P E S O F L O C A L F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ - -/*----------------------------------------------------------------------------------------*/ -/** - * Init NB LCLK DPM in Root Complex Activity mode - * - * - * - * @param[in] StdHeader Pointer to Standard configuration - * @retval Initialization status - */ - -AGESA_STATUS -NbFmInitLclkDpmRcActivity ( - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - AGESA_STATUS Status; - PP_FUSE_ARRAY *PpFuseArray; - INT8 Index; - UINTN LclkState; - Status = AGESA_SUCCESS; - IDS_HDT_CONSOLE (GNB_TRACE, "NbFmInitLclkDpmRcActivity F12 Enter\n"); - PpFuseArray = GnbLocateHeapBuffer (AMD_PP_FUSE_TABLE_HANDLE, StdHeader); - if (PpFuseArray != NULL) { - UINT32 ActivityThreshold [8]; - UINT16 SamplingPeriod [10]; - UINT8 LclkScalingDid [4]; - UINT8 LclkScalingVid [4]; - UINT32 LclkDpmValid; - UINT32 MainPllVcoKHz; - LibAmdMemFill (&ActivityThreshold[0], 0, sizeof (ActivityThreshold), StdHeader); - LibAmdMemFill (&SamplingPeriod[0], 0, sizeof (SamplingPeriod), StdHeader); - MainPllVcoKHz = GfxLibGetMainPllFreq (StdHeader) * 100; - LclkDpmValid = 0; - LclkState = 7; - for (Index = 3; Index >= 0; Index--) { - if (PpFuseArray->LclkDpmValid [Index] != 0) { - // Set valid DPM state - LclkDpmValid |= (1 << (LclkState)); - // Set LCLK scaling DID - LclkScalingDid [7 - LclkState] = PpFuseArray->LclkDpmDid [Index]; - // Set LCLK scaling VID - LclkScalingVid [7 - LclkState] = PpFuseArray->LclkDpmVid [Index]; - // Set sampling period - SamplingPeriod [LclkState] = 0xC350; - // Changed from 0xC350 to 0x1388 for DPM 0 - if (Index == 0) { - SamplingPeriod [LclkState] = 0x1388; - } - // Set activity threshold from BKDG: - // Raising -- ActivityThreshold [LclkState] = ((102 * (GfxLibCalculateClk (LclkScalingDid [7 - LclkState], MainPllVcoKHz) / 100)) - 10) / 10; - // Lowering -- ActivityThreshold [LclkState] |= (((407 * (GfxLibCalculateClk (LclkScalingDid [7 - LclkState], MainPllVcoKHz) / 100)) + 99) / 10) << 16; - // For ON specific enable LCLK DPM : - ActivityThreshold [LclkState] = LclkDpmActivityThresholdTable [Index]; - - IDS_HDT_CONSOLE (GNB_TRACE, "Fused State Index:%d LCLK DPM State [%d]: LclkScalingDid - 0x%x, ActivityThreshold - 0x%x, SamplingPeriod - 0x%x\n", - Index, LclkState, LclkScalingDid [7 - LclkState], ActivityThreshold [LclkState], SamplingPeriod [LclkState] - ); - LclkState--; - } - } - if (LclkState != 7) { - SMUx33_STRUCT SMUx33; - SMUx0B_x8434_STRUCT SMUx0B_x8434; - FCRxFF30_01E4_STRUCT FCRxFF30_01E4; - UINT8 CurrentUnit; - UINT16 FinalUnit; - UINT16 FinalPeriod; - UINT32 Freq; - UINT32 FreqDelta; - UINT32 Value; - ASSERT (LclkScalingDid [0] != 0); - FreqDelta = 0xffffffff; - FinalPeriod = 0; - FinalUnit = 0; - Freq = (65535 * 100 * 100) / GfxLibCalculateClk (LclkScalingDid [0], MainPllVcoKHz); - for (CurrentUnit = 0; CurrentUnit < 16; CurrentUnit++) { - UINT32 CurrentFreqDelta; - UINT32 CurrentPeriod; - UINT32 Temp; - Temp = GnbLibPowerOf (4, CurrentUnit); - CurrentPeriod = Freq / Temp; - if (CurrentPeriod <= 0xFFFF) { - CurrentFreqDelta = Freq - Temp * CurrentPeriod; - if (FreqDelta > CurrentFreqDelta) { - FinalUnit = CurrentUnit; - FinalPeriod = (UINT16) CurrentPeriod; - FreqDelta = CurrentFreqDelta; - } - } - } - //Process to enablement LCLK DPM States - NbSmuIndirectRead (SMUx33_ADDRESS, AccessWidth32, &SMUx33.Value, StdHeader); - SMUx33.Field.BusyCntSel = 0x3; - SMUx33.Field.LclkActMonUnt = FinalUnit; - SMUx33.Field.LclkActMonPrd = FinalPeriod; - NbSmuIndirectWrite (SMUx33_ADDRESS, AccessS3SaveWidth32, &SMUx33.Value, StdHeader); - SMUx0B_x8434.Value = 0; - SMUx0B_x8434.Field.LclkDpmType = 0x1; - SMUx0B_x8434.Field.LclkDpmEn = 0x1; - SMUx0B_x8434.Field.LclkTimerPeriod = 0x0C350; - SMUx0B_x8434.Field.LclkTimerPrescalar = 0x1; - NbSmuRcuRegisterWrite ( - SMUx0B_x8434_ADDRESS, - &SMUx0B_x8434.Value, - 1, - TRUE, - StdHeader - ); - // Set CAC Credits - NbSmuRcuRegisterWrite ( - SMUx0B_x84AC_ADDRESS, - &LclkDpmCacTable[0], - sizeof (LclkDpmCacTable) / sizeof (UINT32), - TRUE, - StdHeader - ); - // Program activity threshold - IDS_HDT_CONSOLE (GNB_TRACE, "ActivityThreshold[4] - 0x%x ActivityThreshold[5] - 0x%x ActivityThreshold[6] - 0x%x ActivityThreshold[7] - 0x%x\n", - ActivityThreshold[4], ActivityThreshold[5], ActivityThreshold[6], ActivityThreshold [7] - ); - NbSmuRcuRegisterWrite ( - SMUx0B_x8470_ADDRESS, - &ActivityThreshold[4], - 4, - TRUE, - StdHeader - ); - // Program sampling period - for (Index = 0; Index < (sizeof (SamplingPeriod) / sizeof (SamplingPeriod[0])); Index = Index + 2) { - UINT16 Temp; - Temp = SamplingPeriod[Index]; - SamplingPeriod[Index] = SamplingPeriod[Index + 1]; - SamplingPeriod[Index + 1] = Temp; - } - IDS_HDT_CONSOLE (GNB_TRACE, "SamplingPeriod[4] - 0x%x SamplingPeriod[5] - 0x%x SamplingPeriod[6] - 0x%x SamplingPeriod[7] - 0x%x \n", - SamplingPeriod[4], SamplingPeriod[5], SamplingPeriod[6], SamplingPeriod[7] - ); - NbSmuRcuRegisterWrite ( - SMUx0B_x8440_ADDRESS, - (UINT32*) &SamplingPeriod[4], - 2, - TRUE, - StdHeader - ); - // Program LCK scaling DID - NbSmuRcuRegisterWrite ( - SMUx0B_x848C_ADDRESS, - (UINT32*) &LclkScalingDid[0], - 1, - TRUE, - StdHeader - ); - // Program LCK scaling VID - NbSmuRcuRegisterWrite ( - SMUx0B_x8498_ADDRESS, - (UINT32*) &LclkScalingVid[0], - 1, - TRUE, - StdHeader - ); - // Program valid LCLK DPM states - LclkDpmValid = NbFmDpmStateBootupInit (LclkDpmValid, StdHeader); - NbSmuRcuRegisterWrite ( - SMUx0B_x8490_ADDRESS, - &LclkDpmValid, - 1, - TRUE, - StdHeader - ); - //Setup Activity Monitor Coefficients - Value = (0x24 << SMUx35_DownTrendCoef_OFFSET) | (0x24 << SMUx35_UpTrendCoef_OFFSET); - NbSmuIndirectWrite (SMUx35_ADDRESS, AccessS3SaveWidth32, &Value, StdHeader); - Value = (0x22 << SMUx35_DownTrendCoef_OFFSET) | (0x22 << SMUx35_UpTrendCoef_OFFSET); - for (Index = SMUx37_ADDRESS; Index <= SMUx51_ADDRESS; Index = Index + 2) { - NbSmuIndirectWrite (Index, AccessS3SaveWidth32, &Value, StdHeader); - } - // Enable LCLK DPM as voltage client - NbSmuSrbmRegisterRead (FCRxFF30_01E4_ADDRESS, &FCRxFF30_01E4.Value, StdHeader); - FCRxFF30_01E4.Field.VoltageChangeEn = 0x1; - NbSmuSrbmRegisterWrite (FCRxFF30_01E4_ADDRESS, &FCRxFF30_01E4.Value, TRUE, StdHeader); - // Start LCLK service - NbSmuServiceRequest (0x8, TRUE, StdHeader); - } - } else { - IDS_HDT_CONSOLE (GNB_TRACE, " ERROR! Cannot locate fuse table\n"); - Status = AGESA_ERROR; - } - IDS_HDT_CONSOLE (GNB_TRACE, "NbFmInitLclkDpmRcActivity F12 Exit [0x%x]\n", Status); - return Status; -} - - - -/*----------------------------------------------------------------------------------------*/ -/** - * Family specific check PsppPolicy to initially enable appropriate DPM states - * - * - * @param[in] LclkDpmValid UINT32 Lclk Dpm Valid - * @param[in] StdHeader Pointer to AMD_CONFIG_PARAMS - */ -UINT32 -NbFmDpmStateBootupInit ( - IN UINT32 LclkDpmValid, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - PCIe_PLATFORM_CONFIG *Pcie; - UINT32 LclkDpmValidState; - UINT8 Dpm0ValidOffset; - - if ((LclkDpmValid & 0xFF) == 0) { - IDS_HDT_CONSOLE (NB_MISC, " No valid DPM State Bootup Init\n"); - return 0; - } - - // For LN, from DPM0(the most right non-zero bit) to highest DPM(bit 7) - Dpm0ValidOffset = LibAmdBitScanForward (LclkDpmValid & 0xFF); - // Enable DPM0 - LclkDpmValidState = 1 << Dpm0ValidOffset; - - if (PcieLocateConfigurationData (StdHeader, &Pcie) == AGESA_SUCCESS) { - switch (Pcie->PsppPolicy) { - case PsppDisabled: - case PsppPerformance: - case PsppBalanceHigh: - if ((Dpm0ValidOffset + 2) <= 7) { - // Enable DPM0 + DPM2 - LclkDpmValidState = LclkDpmValidState + (1 << (Dpm0ValidOffset + 2)); - } - break; - case PsppBalanceLow: - if ((Dpm0ValidOffset + 1) <= 7) { - // Enable DPM0 + DPM1 - LclkDpmValidState = LclkDpmValidState + (1 << (Dpm0ValidOffset + 1)); - } - break; - case PsppPowerSaving: - // Enable DPM0 - break; - default: - ASSERT (FALSE); - } - } else { - IDS_HDT_CONSOLE (NB_MISC, " DPM State Bootup Init Pcie Locate ConfigurationData Fail!! -- Enable DPM0 only\n"); - } - return LclkDpmValidState; -} diff --git a/src/vendorcode/amd/agesa/f12/Proc/GNB/Nb/Family/LN/F12NbPowerGate.c b/src/vendorcode/amd/agesa/f12/Proc/GNB/Nb/Family/LN/F12NbPowerGate.c deleted file mode 100644 index 7611473b97..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/GNB/Nb/Family/LN/F12NbPowerGate.c +++ /dev/null @@ -1,600 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * NB Power gate Gfx/Uvd/Gmc - * - * - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: GNB - * @e \$Revision: 48452 $ @e \$Date: 2011-03-09 12:50:44 +0800 (Wed, 09 Mar 2011) $ - * - */ -/* -***************************************************************************** -* -* Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* *************************************************************************** -* -*/ - -/*---------------------------------------------------------------------------------------- - * M O D U L E S U S E D - *---------------------------------------------------------------------------------------- - */ - -#include "AGESA.h" -#include "amdlib.h" -#include "Ids.h" -#include "heapManager.h" -#include "Gnb.h" -#include "GnbGfx.h" -#include "GnbPcie.h" -#include "GnbFuseTable.h" -#include "GnbCommonLib.h" -#include "GnbGfxInitLibV1.h" -#include "GnbRegistersLN.h" -#include "GfxLib.h" -#include "NbSmuLib.h" -#include "NbConfigData.h" -#include "NbFamilyServices.h" -#include "F12NbPowerGate.h" -#include "Filecode.h" - -#define FILECODE PROC_GNB_NB_FAMILY_LN_F12NBPOWERGATE_FILECODE -/*---------------------------------------------------------------------------------------- - * D E F I N I T I O N S A N D M A C R O S - *---------------------------------------------------------------------------------------- - */ -#define POWER_GATE_GMC_PSO_CONTROL_VALID_NUM 1 -#define POWER_GATE_GMC_MOTH_PSO_PWRUP 153 -#define POWER_GATE_GMC_MOTH_PSO_PWRDN 50 -#define POWER_GATE_GMC_DAUG_PSO_PWRUP 50 -#define POWER_GATE_GMC_DAUG_PSO_PWRDN 0 -#define POWER_GATE_GMC_RESET_TIMER 10 -#define POWER_GATE_GMC_ISO_TIMER 10 - -#define POWER_GATE_UVD_MOTH_PSO_PWRUP 113 -#define POWER_GATE_UVD_MOTH_PSO_PWRDN 50 -#define POWER_GATE_UVD_DAUG_PSO_PWRUP 50 -#define POWER_GATE_UVD_DAUG_PSO_PWRDN 50 -#define POWER_GATE_UVD_RESET_TIMER 50 -#define POWER_GATE_UVD_ISO_TIMER 50 - -/*---------------------------------------------------------------------------------------- - * T Y P E D E F S A N D S T R U C T U R E S - *---------------------------------------------------------------------------------------- - */ - -POWER_GATE_DATA F12NbGmcPowerGatingData = { - POWER_GATE_GMC_MOTH_PSO_PWRUP, - POWER_GATE_GMC_MOTH_PSO_PWRDN, - POWER_GATE_GMC_DAUG_PSO_PWRUP, - POWER_GATE_GMC_DAUG_PSO_PWRDN, - POWER_GATE_GMC_RESET_TIMER, - POWER_GATE_GMC_ISO_TIMER -}; - -/// GMC power gating -UINT32 F12GmcPowerGatingTable_1[] = { -// SMUx0B_x8408_ADDRESS - 0, -// SMUx0B_x840C_ADDRESS - 0, -// SMUx0B_x8410_ADDRESS - (0x1 << SMUx0B_x8410_PwrGatingEn_OFFSET) | - (0x0 << SMUx0B_x8410_Reserved_2_1_OFFSET) | - (POWER_GATE_GMC_PSO_CONTROL_VALID_NUM << SMUx0B_x8410_PsoControlValidNum_OFFSET) | - (0x0 << SMUx0B_x8410_PwrGaterSel_OFFSET) -}; - -/*----------------------------------------------------------------------------------------*/ -/** - * GMC Power Gating - * - * - * @param[in] StdHeader Standard Configuration Header - * @param[in] PowerGateData Pointer power gate data - * @retval AGESA_STATUS - */ - -AGESA_STATUS -STATIC -F12NbSmuGmcPowerGatingInit ( - IN AMD_CONFIG_PARAMS *StdHeader, - IN POWER_GATE_DATA *PowerGateData - ) -{ - IDS_HDT_CONSOLE (GNB_TRACE, "NbSmuGmcPowerGatingInit Enter\n"); - NbSmuRcuRegisterWrite ( - SMUx0B_x8408_ADDRESS, - &F12GmcPowerGatingTable_1[0], - sizeof (POWER_GATE_DATA) / sizeof (UINT32), - TRUE, - StdHeader - ); - - NbSmuRcuRegisterWrite ( - SMUx0B_x84A0_ADDRESS, - (UINT32 *) PowerGateData, - sizeof (POWER_GATE_DATA) / sizeof (UINT32), - TRUE, - StdHeader - ); - - NbSmuServiceRequest (0x01, TRUE, StdHeader); - IDS_HDT_CONSOLE (GNB_TRACE, "NbSmuGmcPowerGatingInit Exit\n"); - return AGESA_SUCCESS; -} - - -POWER_GATE_DATA F12NbUvdPowerGatingData = { - POWER_GATE_UVD_MOTH_PSO_PWRUP, - POWER_GATE_UVD_MOTH_PSO_PWRDN, - POWER_GATE_UVD_DAUG_PSO_PWRUP, - POWER_GATE_UVD_DAUG_PSO_PWRDN, - POWER_GATE_UVD_RESET_TIMER, - POWER_GATE_UVD_ISO_TIMER -}; - -/// UVD power gating -UINT32 F12UvdPowerGatingTable_1[] = { -// SMUx0B_x8408_ADDRESS - 0, -// SMUx0B_x840C_ADDRESS - 0, -// SMUx0B_x8410_ADDRESS - (0x0 << SMUx0B_x8410_PwrGatingEn_OFFSET) | - (0x0 << SMUx0B_x8410_Reserved_2_1_OFFSET) | - (0x1 << SMUx0B_x8410_PsoControlValidNum_OFFSET) | - (0x2 << SMUx0B_x8410_PwrGaterSel_OFFSET) -}; - - -/*----------------------------------------------------------------------------------------*/ -/** - * UVD Power Gating - * - * - * - * @param[in] StdHeader Standard Configuration Header - * @param[in] PowerGateData Pointer power gate data - * - */ - - -VOID -STATIC -F12NbSmuUvdPowerGatingInit ( - IN AMD_CONFIG_PARAMS *StdHeader, - IN POWER_GATE_DATA *PowerGateData - ) -{ - IDS_HDT_CONSOLE (GNB_TRACE, "NbSmuUvdPowerGatingInit Enter\n"); - NbSmuRcuRegisterWrite ( - SMUx0B_x8408_ADDRESS, - &F12UvdPowerGatingTable_1[0], - sizeof (F12UvdPowerGatingTable_1) / sizeof (UINT32), - TRUE, - StdHeader - ); - - NbSmuRcuRegisterWrite ( - SMUx0B_x84A0_ADDRESS, - (UINT32 *) PowerGateData, - sizeof (POWER_GATE_DATA) / sizeof (UINT32), - TRUE, - StdHeader - ); - IDS_HDT_CONSOLE (GNB_TRACE, "NbSmuUvdPowerGatingInit Exit\n"); - NbSmuServiceRequest (0x01, TRUE, StdHeader); -} - - - -/*----------------------------------------------------------------------------------------*/ -/** - * UVD Power Shutdown - * - * - * - * @param[in] StdHeader Standard Configuration Header - */ - - -VOID -STATIC -F12NbSmuUvdShutdown ( - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - IDS_HDT_CONSOLE (GNB_TRACE, "NbSmuUvdShutdown Enter\n"); - NbSmuServiceRequest (0x03, TRUE, StdHeader); - IDS_HDT_CONSOLE (GNB_TRACE, "NbSmuUvdShutdown Exit\n"); -} - - -/// GMC shutdown table -UINT32 F12SmuGmcShutdownTable_1[] = { -// SMUx0B_x8600_ADDRESS, - (0x3 << SMUx0B_x8600_TransactionCount_OFFSET) | - (0x8650 << SMUx0B_x8600_MemAddr_7_0__OFFSET), -// SMUx0B_x8604_ADDRESS, - (0xFE << SMUx0B_x8604_Txn1MBusAddr_31_24__OFFSET) | - (0x60 << SMUx0B_x8604_Txn1MBusAddr_23_16__OFFSET) | - (0x14 << SMUx0B_x8604_Txn1TransferLength_7_0__OFFSET), -// SMUx0B_x8608_ADDRESS, - (0x03ull << SMUx0B_x8608_Txn1Tsize_OFFSET) | - (0x01ull << SMUx0B_x8608_Txn1Overlap_OFFSET) | - (0x01ull << SMUx0B_x8608_Txn1Mode_OFFSET) | - (0x07ull << SMUx0B_x8608_Txn2Mbusaddr70_OFFSET), -// SMUx0B_x860C_ADDRESS, - (0xFE << SMUx0B_x860C_Txn2MBusAddr3124_OFFSET) | - (0x60 << SMUx0B_x860C_Txn2MBusAddr2316_OFFSET) | - (0x4 << SMUx0B_x860C_Txn2TransferLength70_OFFSET) | - (0x3 << SMUx0B_x860C_Txn2Tsize_OFFSET), -// SMUx0B_x8610_ADDRESS, - (0x1 << SMUx0B_x8610_Txn2Overlap_OFFSET) | - (0x1 << SMUx0B_x8610_Txn2Mode_OFFSET) | - (0x60 << SMUx0B_x8610_Txn3MBusAddr2316_OFFSET) | - (0x6 << SMUx0B_x8610_Txn3MBusAddr70_OFFSET), -// SMUx0B_x8614_ADDRESS, - (0xFEull << SMUx0B_x8614_Txn3MBusAddr3124_OFFSET) | - (0x04ull << SMUx0B_x8614_Txn3TransferLength70_OFFSET) | - (0x03ull << SMUx0B_x8614_Txn3Tsize_OFFSET) | - (0x01ull << SMUx0B_x8614_Txn3Mode_OFFSET), -}; - -UINT32 F12SmuGmcShutdownTable_2[] = { -// SMUx0B_x8650_ADDRESS, - 0x76543210, -// SMUx0B_x8654_ADDRESS, - 0xFEDCBA98, -// SMUx0B_x8658_ADDRESS, - 0x8, -// SMUx0B_x865C_ADDRESS, - 0x00320032, -// SMUx0B_x8660_ADDRESS, - 0x00100010, -// SMUx0B_x8664_ADDRESS, - 0x00320032, -// SMUx0B_x866C_ADDRESS, - 0x00 -}; - -/*----------------------------------------------------------------------------------------*/ -/** - * Shutdown GMC - * - * - * - * @param[in] StdHeader Standard Configuration Header - */ - -VOID -STATIC -F12NbSmuGmcShutdown ( - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - IDS_HDT_CONSOLE (GNB_TRACE, "NbSmuGmcShutdown Enter\n"); - NbSmuRcuRegisterWrite ( - SMUx0B_x8600_ADDRESS, - &F12SmuGmcShutdownTable_1[0], - sizeof (F12SmuGmcShutdownTable_1) / sizeof (UINT32), - TRUE, - StdHeader - ); - - NbSmuRcuRegisterWrite ( - SMUx0B_x8650_ADDRESS, - &F12SmuGmcShutdownTable_2[0], - sizeof (F12SmuGmcShutdownTable_2) / sizeof (UINT32), - TRUE, - StdHeader - ); - - NbSmuServiceRequest (0x0B, TRUE, StdHeader); - IDS_HDT_CONSOLE (GNB_TRACE, "NbSmuGmcShutdown Exit\n"); -} - -/// GFX shutdown table -UINT32 F12SmuGfxShutdownTable_1[] = { -// SMUx0B_x8600_ADDRESS, - (0x09ull << SMUx0B_x8600_TransactionCount_OFFSET) | - (0x8650ull << SMUx0B_x8600_MemAddr_7_0__OFFSET) | - (0x00ull << SMUx0B_x8600_Txn1MBusAddr_7_0__OFFSET), -// SMUx0B_x8604_ADDRESS, - (0xFEull << SMUx0B_x8604_Txn1MBusAddr_31_24__OFFSET) | - (0x70ull << SMUx0B_x8604_Txn1MBusAddr_23_16__OFFSET) | - (0x00ull << SMUx0B_x8604_Txn1MBusAddr_15_8__OFFSET) | - (0x14ull << SMUx0B_x8604_Txn1TransferLength_7_0__OFFSET), -// SMUx0B_x8608_ADDRESS, - (0x03ull << SMUx0B_x8608_Txn1Tsize_OFFSET) | - (0x00ull << SMUx0B_x8608_Txn1TransferLength_13_8__OFFSET) | - (0x00ull << SMUx0B_x8608_Txn1Spare_OFFSET) | - (0x01ull << SMUx0B_x8608_Txn1Overlap_OFFSET) | - (0x00ull << SMUx0B_x8608_Txn1Static_OFFSET) | - (0x01ull << SMUx0B_x8608_Txn1Mode_OFFSET) | - (0x00ull << SMUx0B_x8608_Txn2Mbusaddr158_OFFSET) | - (0x07ull << SMUx0B_x8608_Txn2Mbusaddr70_OFFSET), -// SMUx0B_x860C_ADDRESS, - (0xFEull << SMUx0B_x860C_Txn2MBusAddr3124_OFFSET) | - (0x70ull << SMUx0B_x860C_Txn2MBusAddr2316_OFFSET) | - (0x04ull << SMUx0B_x860C_Txn2TransferLength70_OFFSET) | - (0x03ull << SMUx0B_x860C_Txn2Tsize_OFFSET) | - (0x00ull << SMUx0B_x860C_Txn2TransferLength138_OFFSET), -// SMUx0B_x8610_ADDRESS, - (0x00ull << SMUx0B_x8610_Txn2Spare_OFFSET) | - (0x01ull << SMUx0B_x8610_Txn2Overlap_OFFSET) | - (0x00ull << SMUx0B_x8610_Txn2Static_OFFSET) | - (0x01ull << SMUx0B_x8610_Txn2Mode_OFFSET) | - (0x70ull << SMUx0B_x8610_Txn3MBusAddr2316_OFFSET) | - (0x00ull << SMUx0B_x8610_Txn3MBusAddr158_OFFSET) | - (0x06ull << SMUx0B_x8610_Txn3MBusAddr70_OFFSET), -// SMUx0B_x8614_ADDRESS, - (0xFEull << SMUx0B_x8614_Txn3MBusAddr3124_OFFSET) | - (0x04ull << SMUx0B_x8614_Txn3TransferLength70_OFFSET) | - (0x03ull << SMUx0B_x8614_Txn3Tsize_OFFSET) | - (0x00ull << SMUx0B_x8614_Txn3TransferLength138_OFFSET) | - (0x00ull << SMUx0B_x8614_Txn3Spare_OFFSET) | - (0x00ull << SMUx0B_x8614_Txn3Overlap_OFFSET) | - (0x00ull << SMUx0B_x8614_Txn3Static_OFFSET) | - (0x01ull << SMUx0B_x8614_Txn3Mode_OFFSET), -// SMUx0B_x8618_ADDRESS, - (0xFEull << SMUx0B_x8618_Txn4MBusAddr3124_OFFSET) | - (0xA0ull << SMUx0B_x8618_Txn4MBusAddr2316_OFFSET) | - (0x00ull << SMUx0B_x8618_Txn4MBusAddr158_OFFSET) | - (0x00ull << SMUx0B_x8618_Txn4MBusAddr70_OFFSET), -// SMUx0B_x861C_ADDRESS, - (0x07ull << SMUx0B_x861C_Txn5Mbusaddr70_OFFSET) | - (0x14ull << SMUx0B_x861C_Txn4TransferLength70_OFFSET) | - (0x03ull << SMUx0B_x861C_Txn4Tsize_OFFSET) | - (0x00ull << SMUx0B_x861C_Txn4TransferLength138_OFFSET) | - (0x00ull << SMUx0B_x861C_Txn4Spare_OFFSET) | - (0x01ull << SMUx0B_x861C_Txn4Overlap_OFFSET) | - (0x00ull << SMUx0B_x861C_Txn4Static_OFFSET) | - (0x01ull << SMUx0B_x861C_Txn4Mode_OFFSET), -// SMUx0B_x8620_ADDRESS, - (0x00ull << SMUx0B_x8620_Txn5MBusAddr158_OFFSET) | - (0xA0ull << SMUx0B_x8620_Txn5MBusAddr2316_OFFSET) | - (0xFEull << SMUx0B_x8620_Txn5MBusAddr3124_OFFSET) | - (0x04ull << SMUx0B_x8620_Txn5TransferLength70_OFFSET), -// SMUx0B_x8624_ADDRESS, - (0x03ull << SMUx0B_x8624_Txn5Tsize_OFFSET) | - (0x00ull << SMUx0B_x8624_Txn5TransferLength138_OFFSET) | - (0x00ull << SMUx0B_x8624_Txn5Spare_OFFSET) | - (0x01ull << SMUx0B_x8624_Txn5Overlap_OFFSET) | - (0x00ull << SMUx0B_x8624_Txn5Static_OFFSET) | - (0x01ull << SMUx0B_x8624_Txn5Mode_OFFSET) | - (0x00ull << SMUx0B_x8624_Txn6MBusAddr158_OFFSET) | - (0x06ull << SMUx0B_x8624_Txn6MBusAddr70_OFFSET), -// SMUx0B_x8628_ADDRESS, - (0xFEull << SMUx0B_x8628_Txn6MBusAddr3124_OFFSET) | - (0xA0ull << SMUx0B_x8628_Txn6MBusAddr2316_OFFSET) | - (0x04ull << SMUx0B_x8628_Txn6TransferLength70_OFFSET) | - (0x03ull << SMUx0B_x8628_Txn6Tsize_OFFSET) | - (0x00ull << SMUx0B_x8628_Txn6TransferLength138_OFFSET), -// SMUx0B_x862C_ADDRESS, - (0xB0ull << SMUx0B_x862C_Txn7MBusAddr2316_OFFSET) | - (0x00ull << SMUx0B_x862C_Txn7MBusAddr158_OFFSET) | - (0x00ull << SMUx0B_x862C_Txn7MBusAddr70_OFFSET) | - (0x00ull << SMUx0B_x862C_Txn6Spare_OFFSET) | - (0x00ull << SMUx0B_x862C_Txn6Overlap_OFFSET) | - (0x00ull << SMUx0B_x862C_Txn6Static_OFFSET) | - (0x01ull << SMUx0B_x862C_Txn6Mode_OFFSET), -// SMUx0B_x8630_ADDRESS, - (0xFEull << SMUx0B_x8630_Txn7MBusAddr3124_OFFSET) | - (0x14ull << SMUx0B_x8630_Txn7TransferLength70_OFFSET) | - (0x03ull << SMUx0B_x8630_Txn7Tsize_OFFSET) | - (0x00ull << SMUx0B_x8630_Txn7TransferLength138_OFFSET) | - (0x00ull << SMUx0B_x8630_Txn7Spare_OFFSET) | - (0x01ull << SMUx0B_x8630_Txn7Overlap_OFFSET) | - (0x00ull << SMUx0B_x8630_Txn7Static_OFFSET) | - (0x01ull << SMUx0B_x8630_Txn7Mode_OFFSET), -// SMUx0B_x8634_ADDRESS, - (0xFEull << SMUx0B_x8634_Txn8MBusAddr3124_OFFSET) | - (0xB0ull << SMUx0B_x8634_Txn8MBusAddr2316_OFFSET) | - (0x00ull << SMUx0B_x8634_Txn8MBusAddr158_OFFSET) | - (0x07ull << SMUx0B_x8634_Txn8MBusAddr70_OFFSET), -// SMUx0B_x8638_ADDRESS, - (0x06ull << SMUx0B_x8638_Txn9MBusAddr70_OFFSET) | - (0x04ull << SMUx0B_x8638_Txn8TransferLength70_OFFSET) | - (0x03ull << SMUx0B_x8638_Txn8Tsize_OFFSET) | - (0x00ull << SMUx0B_x8638_Txn8TransferLength138_OFFSET) | - (0x00ull << SMUx0B_x8638_Txn8Spare_OFFSET) | - (0x01ull << SMUx0B_x8638_Txn8Overlap_OFFSET) | - (0x00ull << SMUx0B_x8638_Txn8Static_OFFSET) | - (0x01ull << SMUx0B_x8638_Txn8Mode_OFFSET), -// SMUx0B_x863C_ADDRESS, - (0x00ull << SMUx0B_x863C_Txn9MBusAddr158_OFFSET) | - (0xB0ull << SMUx0B_x863C_Txn9MBuAaddr2316_OFFSET) | - (0xFEull << SMUx0B_x863C_Txn9MBusAddr3124_OFFSET) | - (0x04ull << SMUx0B_x863C_Txn9TransferLength70_OFFSET), -// SMUx0B_x8640_ADDRESS, - (0x03ull << SMUx0B_x8640_Txn9Tsize_OFFSET) | - (0x00ull << SMUx0B_x8640_Txn9TransferLength138_OFFSET) | - (0x00ull << SMUx0B_x8640_Txn9Spare_OFFSET) | - (0x00ull << SMUx0B_x8640_Txn9Overlap_OFFSET) | - (0x00ull << SMUx0B_x8640_Txn9Static_OFFSET) | - (0x01ull << SMUx0B_x8640_Txn9Mode_OFFSET) | - (0x00ull << SMUx0B_x8640_Txn10MBusAddr158_OFFSET) | - (0x00ull << SMUx0B_x8640_Txn10MBusAddr70_OFFSET) -}; -UINT32 F12SmuGfxShutdownTable_2[] = { -// SMUx0B_x8650_ADDRESS, - 0x76543210, -// SMUx0B_x8654_ADDRESS, - 0xFEDCBA98, -// SMUx0B_x8658_ADDRESS, - 0x80, -// SMUx0B_x865C_ADDRESS, - 0x00320032, -// SMUx0B_x8660_ADDRESS, - 0x00100010, -// SMUx0B_x8664_ADDRESS, - 0x00320032, -// SMUx0B_x866C_ADDRESS, - 0x00, -// SMUx0B_x8670_ADDRESS, - 0x76543210, -// SMUx0B_x8674_ADDRESS, - 0xFEDCBA98, -// SMUx0B_x8678_ADDRESS, - 0x80, -// SMUx0B_x867C_ADDRESS, - 0x00320032, -// SMUx0B_x8680_ADDRESS, - 0x00100010, -// SMUx0B_x8684_ADDRESS, - 0x00320032, -// SMUx0B_x868C_ADDRESS, - 0x00, -// SMUx0B_x8690_ADDRESS, - 0x76543210, -// SMUx0B_x8694_ADDRESS, - 0xFEDCBA98, -// SMUx0B_x8698_ADDRESS, - 0x80, -// SMUx0B_x869C_ADDRESS, - 0x00320032, -// SMUx0B_x86A0_ADDRESS, - 0x00100010, - 0x00320032, - 0x00 -}; - -/*----------------------------------------------------------------------------------------*/ -/** - * Shutdown GFX - * - * - * - * @param[in] StdHeader Standard Configuration Header - */ - - - -VOID -STATIC -F12NbSmuGfxShutdown ( - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - IDS_HDT_CONSOLE (GNB_TRACE, "NbSmuGfxShutdown Enter\n"); - NbSmuRcuRegisterWrite ( - SMUx0B_x8600_ADDRESS, - &F12SmuGfxShutdownTable_1[0], - sizeof (F12SmuGfxShutdownTable_1) / sizeof (UINT32), - TRUE, - StdHeader - ); - - NbSmuRcuRegisterWrite ( - SMUx0B_x8650_ADDRESS, - &F12SmuGfxShutdownTable_2[0], - sizeof (F12SmuGfxShutdownTable_2) / sizeof (UINT32), - TRUE, - StdHeader - ); - - NbSmuServiceRequest (0x0B, TRUE, StdHeader); - IDS_HDT_CONSOLE (GNB_TRACE, "NbSmuGfxShutdown Exit\n"); -} - - -/*----------------------------------------------------------------------------------------*/ -/** - * Power gate unused blocks - * - * - * - * @param[in] StdHeader Pointer to Standard configuration - * @retval AGESA_STATUS - */ - -AGESA_STATUS -F12NbPowerGateFeature ( - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - NB_POWERGATE_CONFIG NbPowerGate; - FCRxFF30_0398_STRUCT FCRxFF30_0398; - IDS_HDT_CONSOLE (GNB_TRACE, "NbPowerGateFeature Enter\n"); - - NbPowerGate.Services.GmcPowerGate = 0x1; - NbPowerGate.Services.UvdPowerGate = 0x1; - NbPowerGate.Services.GfxPowerGate = 0x1; - LibAmdMemCopy (&NbPowerGate.Gmc, &F12NbGmcPowerGatingData, sizeof (POWER_GATE_DATA), StdHeader); - LibAmdMemCopy (&NbPowerGate.Uvd, &F12NbUvdPowerGatingData, sizeof (POWER_GATE_DATA), StdHeader); - IDS_OPTION_CALLOUT (IDS_CALLOUT_GNB_NB_POWERGATE_CONFIG, &NbPowerGate, StdHeader); - F12NbSmuGmcPowerGatingInit (StdHeader, &NbPowerGate.Gmc); - F12NbSmuUvdPowerGatingInit (StdHeader, &NbPowerGate.Uvd); - if (!GfxLibIsControllerPresent (StdHeader)) { - FCRxFF30_0398.Value = (1 << FCRxFF30_0398_SoftResetGrbm_OFFSET) | (1 << FCRxFF30_0398_SoftResetMc_OFFSET) | - (1 << FCRxFF30_0398_SoftResetDc_OFFSET) | (1 << FCRxFF30_0398_SoftResetRlc_OFFSET) | - (1 << FCRxFF30_0398_SoftResetUvd_OFFSET); - NbSmuSrbmRegisterWrite (FCRxFF30_0398_ADDRESS, &FCRxFF30_0398.Value, TRUE, StdHeader); - if (NbPowerGate.Services.GmcPowerGate == 1) { - IDS_HDT_CONSOLE (GNB_TRACE, " Shutdown GMC\n"); - F12NbSmuGmcShutdown (StdHeader); - } - if (NbPowerGate.Services.UvdPowerGate == 1) { - IDS_HDT_CONSOLE (GNB_TRACE, " Shutdown UVD\n"); - F12NbSmuUvdShutdown (StdHeader); - } - if (NbPowerGate.Services.GfxPowerGate == 1) { - IDS_HDT_CONSOLE (GNB_TRACE, " Shutdown GFX\n"); - F12NbSmuGfxShutdown (StdHeader); - } - } - IDS_HDT_CONSOLE (GNB_TRACE, "NbPowerGateFeature Exit\n"); - return AGESA_SUCCESS; -} - -/*----------------------------------------------------------------------------------------*/ -/** - * Get GMC restore latency - * - * Exit Latency = ((( DAUG_PSO_PWRUP + MOTH_PSO_PWRUP + ISO_TIMER + 7) * PSO_CONTROL_VALID_NUM) + RESET_TIMER ) * 10ns - * - * @param[in] StdHeader Pointer to Standard configuration - * @retval AGESA_STATUS - */ - -UINT32 -F12NbPowerGateGmcRestoreLatency ( - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - UINT32 RestoreLatency; - //@todo may need dynamic calculation - RestoreLatency = ((POWER_GATE_GMC_DAUG_PSO_PWRUP + POWER_GATE_GMC_MOTH_PSO_PWRUP + POWER_GATE_GMC_ISO_TIMER + 7) * - POWER_GATE_GMC_PSO_CONTROL_VALID_NUM + POWER_GATE_GMC_RESET_TIMER) * 10; - return RestoreLatency; -} diff --git a/src/vendorcode/amd/agesa/f12/Proc/GNB/Nb/Family/LN/F12NbPowerGate.h b/src/vendorcode/amd/agesa/f12/Proc/GNB/Nb/Family/LN/F12NbPowerGate.h deleted file mode 100644 index 1bdb973ce4..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/GNB/Nb/Family/LN/F12NbPowerGate.h +++ /dev/null @@ -1,60 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * NB Power gate Gfx/Uvd/Gmc - * - * - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: GNB - * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $ - * - */ -/* -***************************************************************************** -* -* Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* *************************************************************************** -* -*/ - -#ifndef _F12NBPOWERGATE_H_ -#define _F12NBPOWERGATE_H_ - -AGESA_STATUS -F12NbPowerGateFeature ( - IN AMD_CONFIG_PARAMS *StdHeader - ); - - -UINT32 -F12NbPowerGateGmcRestoreLatency ( - IN AMD_CONFIG_PARAMS *StdHeader - ); - -#endif diff --git a/src/vendorcode/amd/agesa/f12/Proc/GNB/Nb/Family/LN/F12NbServices.c b/src/vendorcode/amd/agesa/f12/Proc/GNB/Nb/Family/LN/F12NbServices.c deleted file mode 100644 index 3d81adf77d..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/GNB/Nb/Family/LN/F12NbServices.c +++ /dev/null @@ -1,713 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * Graphics Controller family specific service procedure - * - * - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: GNB - * @e \$Revision: 48452 $ @e \$Date: 2011-03-09 12:50:44 +0800 (Wed, 09 Mar 2011) $ - * - */ -/* -***************************************************************************** -* -* Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* *************************************************************************** -* -*/ - - -/*---------------------------------------------------------------------------------------- - * M O D U L E S U S E D - *---------------------------------------------------------------------------------------- - */ -#include "AGESA.h" -#include "amdlib.h" -#include "Ids.h" -#include "Gnb.h" -#include "GnbFuseTable.h" -#include "GnbPcie.h" -#include "GnbCommonLib.h" -#include "GnbGfxInitLibV1.h" -#include "GnbNbInitLibV1.h" -#include "GnbPcieConfig.h" -#include "NbConfigData.h" -#include "OptionGnb.h" -#include "NbLclkDpm.h" -#include "NbFamilyServices.h" -#include "NbPowerMgmt.h" -#include "GnbRegistersLN.h" -#include "cpuFamilyTranslation.h" -#include "GfxLib.h" -#include "Filecode.h" -#define FILECODE PROC_GNB_NB_FAMILY_LN_F12NBSERVICES_FILECODE -/*---------------------------------------------------------------------------------------- - * D E F I N I T I O N S A N D M A C R O S - *---------------------------------------------------------------------------------------- - */ - - -/*---------------------------------------------------------------------------------------- - * T Y P E D E F S A N D S T R U C T U R E S - *---------------------------------------------------------------------------------------- - */ - -extern GNB_BUILD_OPTIONS GnbBuildOptions; -FUSE_TABLE FuseTable; - -/*---------------------------------------------------------------------------------------- - * P R O T O T Y P E S O F L O C A L F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ - -/*----------------------------------------------------------------------------------------*/ -/** - * NB family specific clock gating - * - * - * @param[in, out] NbClkGatingCtrl Pointer to NB_CLK_GATING_CTRL - * @param[in] StdHeader Pointer to AMD_CONFIG_PARAMS - */ -VOID -NbFmNbClockGating ( - IN OUT VOID *NbClkGatingCtrl, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - return; -} - -/*----------------------------------------------------------------------------------------*/ -/** - * UnitID Clumping - * - * - * @param[in] NbPciAddress - * @param[in] StdHeader Standard Configuration Header - * @retval AGESA_STATUS - */ - -VOID -NbFmClumpUnitID ( - IN PCI_ADDR NbPciAddress, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - GnbClumpUnitID (NbPciAddress, StdHeader); -} - -/*----------------------------------------------------------------------------------------*/ -/** - * Get Fuse translation table - * - * - * @retval pointer to fuse translation table - */ - -FUSE_TABLE* -NbFmGetFuseTranslationTable ( - ) -{ - return &FuseTable; -} - -/*----------------------------------------------------------------------------------------*/ -/** - * Family specific fuse table patch - * Is's correct behavior if we would have 4 states, it would be - * PP_FUSE_ARRAY->LclkDpmDid[0] - Goes to State 5 - * PP_FUSE_ARRAY->LclkDpmDid[1] - Goes to State 6 - * PP_FUSE_ARRAY->LclkDpmDid[2] - Goes to State 7 - * If we would have 4 states it would be - * PP_FUSE_ARRAY->LclkDpmDid[0] - Goes to State 4 - * PP_FUSE_ARRAY->LclkDpmDid[1] - Goes to State 5 - * PP_FUSE_ARRAY->LclkDpmDid[2] - Goes to State 6 - * PP_FUSE_ARRAY->LclkDpmDid[3] - Goes to State 7 - * - * @param[in] PpFuseArray Pointer to PP_FUSE_ARRAY - * @param[in] StdHeader Pointer to AMD_CONFIG_PARAMS - */ -VOID -NbFmFuseAdjustFuseTablePatch ( - IN OUT PP_FUSE_ARRAY *PpFuseArray, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - UINT8 LclkDpmMode; - UINT8 SwSatateIndex; - UINT8 MaxSclkIndex; - UINT8 DpmStateIndex; - UINT8 CurrentSclkDpmDid; - CPU_LOGICAL_ID LogicalId; - D18F3x15C_STRUCT D18F3x15C; - - LclkDpmMode = GnbBuildOptions.LclkDpmEn ? LclkDpmRcActivity : LclkDpmDisabled; - GetLogicalIdOfCurrentCore (&LogicalId, StdHeader); - if ((LogicalId.Revision & (AMD_F12_LN_A0 | AMD_F12_LN_A1)) != 0) { - LclkDpmMode = LclkDpmDisabled; - } - IDS_OPTION_HOOK (IDS_GNB_LCLK_DPM_EN, &LclkDpmMode, StdHeader); - - // Read Sclk VID - GnbLibPciRead ( - MAKE_SBDFO ( 0, 0, 0x18, 3, D18F3x15C_ADDRESS), - AccessWidth32, - &D18F3x15C.Value, - StdHeader - ); - PpFuseArray->SclkVid[0] = (UINT8) (D18F3x15C.Field.SclkVidLevel0); - PpFuseArray->SclkVid[1] = (UINT8) (D18F3x15C.Field.SclkVidLevel1); - PpFuseArray->SclkVid[2] = (UINT8) (D18F3x15C.Field.SclkVidLevel2); - PpFuseArray->SclkVid[3] = (UINT8) (D18F3x15C.Field.SclkVidLevel3); - - //For all CPU rev LclkDpmValid[3] = 0 - PpFuseArray->LclkDpmValid[3] = 0; - PpFuseArray->LclkDpmVid[3] = 0; - PpFuseArray->LclkDpmDid[3] = 0; - - // For LCLKDPM set LclkDpmVid[0] = 0, no matter if LCLK DMP enable or disable. - PpFuseArray->LclkDpmVid[0] = 0; - - if (LclkDpmMode != LclkDpmRcActivity) { - //If LCLK DPM disable (LclkDpmMode != LclkDpmRcActivity) - // - LclkDpmDid[1,2] = LclkDpmDid [0], LclkDpmVid[1,2] = LclkDpmVid[0] - // - Execute LCLK DPM init - - PpFuseArray->LclkDpmVid[1] = PpFuseArray->LclkDpmVid[0]; - PpFuseArray->LclkDpmVid[2] = PpFuseArray->LclkDpmVid[0]; - PpFuseArray->LclkDpmDid[1] = PpFuseArray->LclkDpmDid[0]; - PpFuseArray->LclkDpmDid[2] = PpFuseArray->LclkDpmDid[0]; - IDS_HDT_CONSOLE (NB_MISC, " F12 LCLK DPM Mode Disable -- use DPM0 fusing\n"); - - } else { - // If LCLK DPM enabled - // - use fused values for LclkDpmDid[0,1,2] and appropriate voltage - // - Execute LCLK DPM init - PpFuseArray->LclkDpmVid[2] = PpFuseArray->PcieGen2Vid; - if (GfxLibIsControllerPresent (StdHeader)) { - //VID index = VID index associated with highest SCLK DPM state in the Powerplay state where Label_Performance=1 // This would ignore the UVD case (where Label_Performance would be 0). - for (SwSatateIndex = 0 ; SwSatateIndex < PP_FUSE_MAX_NUM_SW_STATE; SwSatateIndex++) { - if (PpFuseArray->PolicyLabel[SwSatateIndex] == POLICY_LABEL_PERFORMANCE) { - break; - } - } - MaxSclkIndex = 0; - CurrentSclkDpmDid = 0xff; - ASSERT (PpFuseArray->SclkDpmValid[SwSatateIndex] != 0); - for (DpmStateIndex = 0; DpmStateIndex < PP_FUSE_MAX_NUM_DPM_STATE; DpmStateIndex++) { - if ((PpFuseArray->SclkDpmValid[SwSatateIndex] & (1 << DpmStateIndex)) != 0) { - if (PpFuseArray->SclkDpmDid[DpmStateIndex] < CurrentSclkDpmDid) { - CurrentSclkDpmDid = PpFuseArray->SclkDpmDid[DpmStateIndex]; - MaxSclkIndex = DpmStateIndex; - } - } - } - PpFuseArray->LclkDpmVid[1] = PpFuseArray->SclkDpmVid[MaxSclkIndex]; - } else { - PpFuseArray->LclkDpmVid[1] = PpFuseArray->LclkDpmVid[0]; - PpFuseArray->LclkDpmDid[1] = PpFuseArray->LclkDpmDid[0]; - } - // - use fused values for LclkDpmDid[0,1,2] and appropriate voltage - //Keep using actual fusing - IDS_HDT_CONSOLE (NB_MISC, " LCLK DPM use actual fusing.\n"); - } - - //Patch SclkThermDid to 200Mhz if not fused - if (PpFuseArray->SclkThermDid == 0) { - PpFuseArray->SclkThermDid = GfxLibCalculateDid (200 * 100, GfxLibGetMainPllFreq (StdHeader) * 100); - } -} - - -/*---------------------------------------------------------------------------------------- - * FUSE translation table - *---------------------------------------------------------------------------------------- - */ - -FUSE_REGISTER_ENTRY FCRxFE00_600E_TABLE [] = { - { - FCRxFE00_600E_MainPllOpFreqIdStartup_OFFSET, - FCRxFE00_600E_MainPllOpFreqIdStartup_WIDTH, - (UINT8) offsetof (PP_FUSE_ARRAY, MainPllId) - }, - { - FCRxFE00_600E_WrCkDid_OFFSET, - FCRxFE00_600E_WrCkDid_WIDTH, - (UINT8) offsetof (PP_FUSE_ARRAY, WrCkDid) - } -}; - -FUSE_REGISTER_ENTRY FCRxFE00_6022_TABLE [] = { - { - FCRxFE00_6022_DclkVclkSel0_OFFSET, - FCRxFE00_6022_DclkVclkSel0_WIDTH, - (UINT8) offsetof (PP_FUSE_ARRAY, VclkDclkSel[0]) - }, - { - FCRxFE00_6022_DclkVclkSel1_OFFSET, - FCRxFE00_6022_DclkVclkSel1_WIDTH, - (UINT8) offsetof (PP_FUSE_ARRAY, VclkDclkSel[1]) - }, - { - FCRxFE00_6022_DclkVclkSel2_OFFSET, - FCRxFE00_6022_DclkVclkSel2_WIDTH, - (UINT8) offsetof (PP_FUSE_ARRAY, VclkDclkSel[2]) - }, - { - FCRxFE00_6022_DclkVclkSel3_OFFSET, - FCRxFE00_6022_DclkVclkSel3_WIDTH, - (UINT8) offsetof (PP_FUSE_ARRAY, VclkDclkSel[3]) - }, - { - FCRxFE00_6022_DclkVclkSel4_OFFSET, - FCRxFE00_6022_DclkVclkSel4_WIDTH, - (UINT8) offsetof (PP_FUSE_ARRAY, VclkDclkSel[4]) - }, - { - FCRxFE00_6022_DclkVclkSel5_OFFSET, - FCRxFE00_6022_DclkVclkSel5_WIDTH, - (UINT8) offsetof (PP_FUSE_ARRAY, VclkDclkSel[5]) - }, -}; - -FUSE_REGISTER_ENTRY FCRxFE00_7103_TABLE [] = { - { - FCRxFE00_7103_SclkDpmVid0_OFFSET, - FCRxFE00_7103_SclkDpmVid0_WIDTH, - (UINT8) offsetof (PP_FUSE_ARRAY, SclkDpmVid[0]) - }, - { - FCRxFE00_7103_SclkDpmVid1_OFFSET, - FCRxFE00_7103_SclkDpmVid1_WIDTH, - (UINT8) offsetof (PP_FUSE_ARRAY, SclkDpmVid[1]) - }, - { - FCRxFE00_7103_SclkDpmVid2_OFFSET, - FCRxFE00_7103_SclkDpmVid2_WIDTH, - (UINT8) offsetof (PP_FUSE_ARRAY, SclkDpmVid[2]) - }, - { - FCRxFE00_7103_SclkDpmVid3_OFFSET, - FCRxFE00_7103_SclkDpmVid3_WIDTH, - (UINT8) offsetof (PP_FUSE_ARRAY, SclkDpmVid[3]) - }, - { - FCRxFE00_7103_SclkDpmVid4_OFFSET, - FCRxFE00_7103_SclkDpmVid4_WIDTH, - (UINT8) offsetof (PP_FUSE_ARRAY, SclkDpmVid[4]) - }, -}; - -FUSE_REGISTER_ENTRY FCRxFE00_7104_TABLE [] = { - { - FCRxFE00_7104_SclkDpmDid0_OFFSET, - FCRxFE00_7104_SclkDpmDid0_WIDTH, - (UINT8) offsetof (PP_FUSE_ARRAY, SclkDpmDid[0]) - }, - { - FCRxFE00_7104_SclkDpmDid1_OFFSET, - FCRxFE00_7104_SclkDpmDid1_WIDTH, - (UINT8) offsetof (PP_FUSE_ARRAY, SclkDpmDid[1]) - }, - { - FCRxFE00_7104_SclkDpmDid2_OFFSET, - FCRxFE00_7104_SclkDpmDid2_WIDTH, - (UINT8) offsetof (PP_FUSE_ARRAY, SclkDpmDid[2]) - } -}; - -FUSE_REGISTER_ENTRY FCRxFE00_7107_TABLE [] = { - { - FCRxFE00_7107_SclkDpmDid3_OFFSET, - FCRxFE00_7107_SclkDpmDid3_WIDTH, - (UINT8) offsetof (PP_FUSE_ARRAY, SclkDpmDid[3]) - }, - { - FCRxFE00_7107_SclkDpmDid4_OFFSET, - FCRxFE00_7107_SclkDpmDid4_WIDTH, - (UINT8) offsetof (PP_FUSE_ARRAY, SclkDpmDid[4]) - } -}; - -FUSE_REGISTER_ENTRY FCRxFE00_7109_TABLE [] = { - { - FCRxFE00_7109_SclkDpmCacBase_OFFSET, - FCRxFE00_7109_SclkDpmCacBase_WIDTH, - (UINT8) offsetof (PP_FUSE_ARRAY, SclkDpmCac[4]) - } -}; - - -FUSE_REGISTER_ENTRY FCRxFE00_710D_TABLE [] = { - { - FCRxFE00_710D_DispclkDid0_OFFSET, - FCRxFE00_710D_DispclkDid0_WIDTH, - (UINT8) offsetof (PP_FUSE_ARRAY, DisplclkDid[0]) - }, - { - FCRxFE00_710D_DispclkDid1_OFFSET, - FCRxFE00_710D_DispclkDid1_WIDTH, - (UINT8) offsetof (PP_FUSE_ARRAY, DisplclkDid[1]) - }, - { - FCRxFE00_710D_DispclkDid2_OFFSET, - FCRxFE00_710D_DispclkDid2_WIDTH, - (UINT8) offsetof (PP_FUSE_ARRAY, DisplclkDid[2]) - }, - { - FCRxFE00_710D_DispclkDid3_OFFSET, - FCRxFE00_710D_DispclkDid3_WIDTH, - (UINT8) offsetof (PP_FUSE_ARRAY, DisplclkDid[3]) - } -}; - -FUSE_REGISTER_ENTRY FCRxFE00_7110_TABLE [] = { - { - FCRxFE00_7110_LclkDpmDid0_OFFSET, - FCRxFE00_7110_LclkDpmDid0_WIDTH, - (UINT8) offsetof (PP_FUSE_ARRAY, LclkDpmDid[0]) - }, - { - FCRxFE00_7110_LclkDpmDid1_OFFSET, - FCRxFE00_7110_LclkDpmDid1_WIDTH, - (UINT8) offsetof (PP_FUSE_ARRAY, LclkDpmDid[1]) - }, - { - FCRxFE00_7110_LclkDpmDid2_OFFSET, - FCRxFE00_7110_LclkDpmDid2_WIDTH, - (UINT8) offsetof (PP_FUSE_ARRAY, LclkDpmDid[2]) - } -}; - -FUSE_REGISTER_ENTRY FCRxFE00_7113_TABLE [] = { - { - FCRxFE00_7113_LclkDpmDid3_OFFSET, - FCRxFE00_7113_LclkDpmDid3_WIDTH, - (UINT8) offsetof (PP_FUSE_ARRAY, LclkDpmDid[3]) - }, - { - FCRxFE00_7113_LclkDpmValid0_OFFSET, - FCRxFE00_7113_LclkDpmValid0_WIDTH, - (UINT8) offsetof (PP_FUSE_ARRAY, LclkDpmValid[0]) - }, - { - FCRxFE00_7113_LclkDpmValid1_OFFSET, - FCRxFE00_7113_LclkDpmValid1_WIDTH, - (UINT8) offsetof (PP_FUSE_ARRAY, LclkDpmValid[1]) - }, - { - FCRxFE00_7113_LclkDpmValid2_OFFSET, - FCRxFE00_7113_LclkDpmValid2_WIDTH, - (UINT8) offsetof (PP_FUSE_ARRAY, LclkDpmValid[2]) - }, - { - FCRxFE00_7113_LclkDpmValid3_OFFSET, - FCRxFE00_7113_LclkDpmValid3_WIDTH, - (UINT8) offsetof (PP_FUSE_ARRAY, LclkDpmValid[3]) - } -}; - -FUSE_REGISTER_ENTRY FCRxFE00_7114_TABLE [] = { - { - FCRxFE00_7114_DclkDid0_OFFSET, - FCRxFE00_7114_DclkDid0_WIDTH, - (UINT8) offsetof (PP_FUSE_ARRAY, DclkDid[0]) - }, - { - FCRxFE00_7114_DclkDid1_OFFSET, - FCRxFE00_7114_DclkDid1_WIDTH, - (UINT8) offsetof (PP_FUSE_ARRAY, DclkDid[1]) - }, - { - FCRxFE00_7114_DclkDid2_OFFSET, - FCRxFE00_7114_DclkDid2_WIDTH, - (UINT8) offsetof (PP_FUSE_ARRAY, DclkDid[2]) - } -}; - -FUSE_REGISTER_ENTRY FCRxFE00_7117_TABLE [] = { - { - FCRxFE00_7117_DclkDid3_OFFSET, - FCRxFE00_7117_DclkDid3_WIDTH, - (UINT8) offsetof (PP_FUSE_ARRAY, DclkDid[3]) - }, - { - FCRxFE00_7117_VclkDid3_OFFSET, - FCRxFE00_7117_VclkDid3_WIDTH, - (UINT8) offsetof (PP_FUSE_ARRAY, VclkDid[3]) - } -}; - -FUSE_REGISTER_ENTRY FCRxFE00_7119_TABLE [] = { - { - FCRxFE00_7119_SclkDpmValid0_OFFSET, - FCRxFE00_7119_SclkDpmValid0_WIDTH, - (UINT8) offsetof (PP_FUSE_ARRAY, SclkDpmValid[0]) - }, - { - FCRxFE00_7119_SclkDpmValid1_OFFSET, - FCRxFE00_7119_SclkDpmValid1_WIDTH, - (UINT8) offsetof (PP_FUSE_ARRAY, SclkDpmValid[1]) - }, - { - FCRxFE00_7119_SclkDpmValid2_OFFSET, - FCRxFE00_7119_SclkDpmValid2_WIDTH, - (UINT8) offsetof (PP_FUSE_ARRAY, SclkDpmValid[2]) - }, - { - FCRxFE00_7119_SclkDpmValid3_OFFSET, - FCRxFE00_7119_SclkDpmValid3_WIDTH, - (UINT8) offsetof (PP_FUSE_ARRAY, SclkDpmValid[3]) - }, - { - FCRxFE00_7119_SclkDpmValid4_OFFSET, - FCRxFE00_7119_SclkDpmValid4_WIDTH, - (UINT8) offsetof (PP_FUSE_ARRAY, SclkDpmValid[4]) - }, - { - FCRxFE00_7119_SclkDpmValid5_OFFSET, - FCRxFE00_7119_SclkDpmValid5_WIDTH, - (UINT8) offsetof (PP_FUSE_ARRAY, SclkDpmValid[5]) - } -}; - -FUSE_REGISTER_ENTRY FCRxFE00_711C_TABLE [] = { - { - FCRxFE00_711C_PolicyLabel0_OFFSET, - FCRxFE00_711C_PolicyLabel0_WIDTH, - (UINT8) offsetof (PP_FUSE_ARRAY, PolicyLabel[0]) - }, - { - FCRxFE00_711C_PolicyLabel1_OFFSET, - FCRxFE00_711C_PolicyLabel1_WIDTH, - (UINT8) offsetof (PP_FUSE_ARRAY, PolicyLabel[1]) - }, - { - FCRxFE00_711C_PolicyLabel2_OFFSET, - FCRxFE00_711C_PolicyLabel2_WIDTH, - (UINT8) offsetof (PP_FUSE_ARRAY, PolicyLabel[2]) - }, - { - FCRxFE00_711C_PolicyLabel3_OFFSET, - FCRxFE00_711C_PolicyLabel3_WIDTH, - (UINT8) offsetof (PP_FUSE_ARRAY, PolicyLabel[3]) - }, - { - FCRxFE00_711C_PolicyLabel4_OFFSET, - FCRxFE00_711C_PolicyLabel4_WIDTH, - (UINT8) offsetof (PP_FUSE_ARRAY, PolicyLabel[4]) - }, - { - FCRxFE00_711C_PolicyLabel5_OFFSET, - FCRxFE00_711C_PolicyLabel5_WIDTH, - (UINT8) offsetof (PP_FUSE_ARRAY, PolicyLabel[5]) - } -}; - -FUSE_REGISTER_ENTRY FCRxFE00_711E_TABLE [] = { - { - FCRxFE00_711E_PolicyFlags0_OFFSET, - FCRxFE00_711E_PolicyFlags0_WIDTH, - (UINT8) offsetof (PP_FUSE_ARRAY, PolicyFlags[0]) - }, - { - FCRxFE00_711E_PolicyFlags1_OFFSET, - FCRxFE00_711E_PolicyFlags1_WIDTH, - (UINT8) offsetof (PP_FUSE_ARRAY, PolicyFlags[1]) - }, - { - FCRxFE00_711E_PolicyFlags2_OFFSET, - FCRxFE00_711E_PolicyFlags2_WIDTH, - (UINT8) offsetof (PP_FUSE_ARRAY, PolicyFlags[2]) - }, - { - FCRxFE00_711E_PolicyFlags3_OFFSET, - FCRxFE00_711E_PolicyFlags3_WIDTH, - (UINT8) offsetof (PP_FUSE_ARRAY, PolicyFlags[3]) - } -}; - -FUSE_REGISTER_ENTRY FCRxFE00_7121_TABLE [] = { - { - FCRxFE00_7121_PolicyFlags4_OFFSET, - FCRxFE00_7121_PolicyFlags4_WIDTH, - (UINT8) offsetof (PP_FUSE_ARRAY, PolicyFlags[4]) - }, - { - FCRxFE00_7121_PolicyFlags5_OFFSET, - FCRxFE00_7121_PolicyFlags5_WIDTH, - (UINT8) offsetof (PP_FUSE_ARRAY, PolicyFlags[5]) - } -}; - -FUSE_REGISTER_ENTRY FCRxFE00_4036_TABLE [] = { - { - FCRxFE00_4036_PPlayTableRev_OFFSET, - FCRxFE00_4036_PPlayTableRev_WIDTH, - (UINT8) offsetof (PP_FUSE_ARRAY, PPlayTableRev) - }, - { - FCRxFE00_4036_SclkThermDid_OFFSET, - FCRxFE00_4036_SclkThermDid_WIDTH, - (UINT8) offsetof (PP_FUSE_ARRAY, SclkThermDid) - }, - { - FCRxFE00_4036_PcieGen2Vid_OFFSET, - FCRxFE00_4036_PcieGen2Vid_WIDTH, - (UINT8) offsetof (PP_FUSE_ARRAY, PcieGen2Vid) - } -}; - -FUSE_REGISTER_ENTRY FCRxFE00_4003_TABLE [] = { - { - FCRxFE00_4003_VclkDid0_OFFSET, - FCRxFE00_4003_VclkDid0_WIDTH, - (UINT8) offsetof (PP_FUSE_ARRAY, VclkDid[0]) - } -}; - -FUSE_REGISTER_ENTRY FCRxFE00_4008_TABLE [] = { - { - FCRxFE00_4008_VclkDid1_OFFSET, - FCRxFE00_4008_VclkDid1_WIDTH, - (UINT8) offsetof (PP_FUSE_ARRAY, VclkDid[1]) - } -}; - -FUSE_REGISTER_ENTRY FCRxFE00_4028_TABLE [] = { - { - FCRxFE00_4028_VclkDid2_OFFSET, - FCRxFE00_4028_VclkDid2_WIDTH, - (UINT8) offsetof (PP_FUSE_ARRAY, VclkDid[2]) - } -}; - -FUSE_TABLE_ENTRY FuseRegisterTable [] = { - { - FCRxFE00_4003_ADDRESS, - sizeof (FCRxFE00_4003_TABLE) / sizeof (FUSE_REGISTER_ENTRY), - FCRxFE00_4003_TABLE - }, - { - FCRxFE00_4008_ADDRESS, - sizeof (FCRxFE00_4008_TABLE) / sizeof (FUSE_REGISTER_ENTRY), - FCRxFE00_4008_TABLE - }, - { - FCRxFE00_4028_ADDRESS, - sizeof (FCRxFE00_4028_TABLE) / sizeof (FUSE_REGISTER_ENTRY), - FCRxFE00_4028_TABLE - }, - { - FCRxFE00_4036_ADDRESS, - sizeof (FCRxFE00_4036_TABLE) / sizeof (FUSE_REGISTER_ENTRY), - FCRxFE00_4036_TABLE - }, - { - FCRxFE00_600E_ADDRESS, - sizeof (FCRxFE00_600E_TABLE) / sizeof (FUSE_REGISTER_ENTRY), - FCRxFE00_600E_TABLE - }, - { - FCRxFE00_6022_ADDRESS, - sizeof (FCRxFE00_6022_TABLE) / sizeof (FUSE_REGISTER_ENTRY), - FCRxFE00_6022_TABLE - }, - { - FCRxFE00_7103_ADDRESS, - sizeof (FCRxFE00_7103_TABLE) / sizeof (FUSE_REGISTER_ENTRY), - FCRxFE00_7103_TABLE - }, - { - FCRxFE00_7104_ADDRESS, - sizeof (FCRxFE00_7104_TABLE) / sizeof (FUSE_REGISTER_ENTRY), - FCRxFE00_7104_TABLE - }, - { - FCRxFE00_7107_ADDRESS, - sizeof (FCRxFE00_7107_TABLE) / sizeof (FUSE_REGISTER_ENTRY), - FCRxFE00_7107_TABLE - }, - { - FCRxFE00_7109_ADDRESS, - sizeof (FCRxFE00_7109_TABLE) / sizeof (FUSE_REGISTER_ENTRY), - FCRxFE00_7109_TABLE - }, - { - FCRxFE00_710D_ADDRESS, - sizeof (FCRxFE00_710D_TABLE) / sizeof (FUSE_REGISTER_ENTRY), - FCRxFE00_710D_TABLE - }, - { - FCRxFE00_7110_ADDRESS, - sizeof (FCRxFE00_7110_TABLE) / sizeof (FUSE_REGISTER_ENTRY), - FCRxFE00_7110_TABLE - }, - { - FCRxFE00_7113_ADDRESS, - sizeof (FCRxFE00_7113_TABLE) / sizeof (FUSE_REGISTER_ENTRY), - FCRxFE00_7113_TABLE - }, - { - FCRxFE00_7114_ADDRESS, - sizeof (FCRxFE00_7114_TABLE) / sizeof (FUSE_REGISTER_ENTRY), - FCRxFE00_7114_TABLE - }, - { - FCRxFE00_7117_ADDRESS, - sizeof (FCRxFE00_7117_TABLE) / sizeof (FUSE_REGISTER_ENTRY), - FCRxFE00_7117_TABLE - }, - { - FCRxFE00_7119_ADDRESS, - sizeof (FCRxFE00_7119_TABLE) / sizeof (FUSE_REGISTER_ENTRY), - FCRxFE00_7119_TABLE - }, - { - FCRxFE00_711C_ADDRESS, - sizeof (FCRxFE00_711C_TABLE) / sizeof (FUSE_REGISTER_ENTRY), - FCRxFE00_711C_TABLE - }, - { - FCRxFE00_711E_ADDRESS, - sizeof (FCRxFE00_711E_TABLE) / sizeof (FUSE_REGISTER_ENTRY), - FCRxFE00_711E_TABLE - }, - { - FCRxFE00_7121_ADDRESS, - sizeof (FCRxFE00_7121_TABLE) / sizeof (FUSE_REGISTER_ENTRY), - FCRxFE00_7121_TABLE - } -}; - -FUSE_TABLE FuseTable = { - sizeof (FuseRegisterTable) / sizeof (FUSE_TABLE_ENTRY), - FuseRegisterTable -}; diff --git a/src/vendorcode/amd/agesa/f12/Proc/GNB/Nb/Family/LN/F12NbSmu.c b/src/vendorcode/amd/agesa/f12/Proc/GNB/Nb/Family/LN/F12NbSmu.c deleted file mode 100644 index 934c7dc700..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/GNB/Nb/Family/LN/F12NbSmu.c +++ /dev/null @@ -1,101 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * SMU initialization - * - * - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: GNB - * @e \$Revision: 47632 $ @e \$Date: 2011-02-24 13:42:20 +0800 (Thu, 24 Feb 2011) $ - * - */ -/* -***************************************************************************** -* -* Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* *************************************************************************** -* -*/ - -/*---------------------------------------------------------------------------------------- - * M O D U L E S U S E D - *---------------------------------------------------------------------------------------- - */ -#include "AGESA.h" -#include "amdlib.h" -#include "Ids.h" -//#include "heapManager.h" -#include "Gnb.h" -#include "NbSmuLib.h" -#include "F12NbSmuFirmware.h" -#include "Filecode.h" - -#define FILECODE PROC_GNB_NB_FAMILY_LN_F12NBSMU_FILECODE -/*---------------------------------------------------------------------------------------- - * D E F I N I T I O N S A N D M A C R O S - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------- - * T Y P E D E F S A N D S T R U C T U R E S - *---------------------------------------------------------------------------------------- - */ -AGESA_STATUS -F12NbSmuInitFeature ( - IN AMD_CONFIG_PARAMS *StdHeader - ); - - -/*----------------------------------------------------------------------------------------*/ -/** - * SMU Initialize - * - * - * - * @param[in] StdHeader Pointer to Standard configuration - * @retval AGESA_STATUS - */ - -AGESA_STATUS -F12NbSmuInitFeature ( - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - SMU_FIRMWARE_REV Revision; - IDS_HDT_CONSOLE (GNB_TRACE, "NbSmuInitFeature Enter\n"); - Revision = NbSmuFirmwareRevision (StdHeader); - IDS_HDT_CONSOLE (NB_MISC, " Current SMU firmware rev %d.%x\n", Revision.MajorRev, Revision.MinorRev); - IDS_HDT_CONSOLE (NB_MISC, " New SMU firmware rev %d.%x\n", Fm.Revision.MajorRev, Fm.Revision.MinorRev); - if ((Revision.MajorRev < Fm.Revision.MajorRev) || (Revision.MajorRev == Fm.Revision.MajorRev && Revision.MinorRev < Fm.Revision.MinorRev)) { - IDS_HDT_CONSOLE (NB_MISC, " Updating SMU firmware\n"); - NbSmuFirmwareDownload (&Fm, StdHeader); - } - IDS_HDT_CONSOLE (GNB_TRACE, "NbSmuInitFeature Exit\n"); - return AGESA_SUCCESS; -} diff --git a/src/vendorcode/amd/agesa/f12/Proc/GNB/Nb/Family/LN/F12NbSmuFirmware.h b/src/vendorcode/amd/agesa/f12/Proc/GNB/Nb/Family/LN/F12NbSmuFirmware.h deleted file mode 100644 index 6c5facf8ef..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/GNB/Nb/Family/LN/F12NbSmuFirmware.h +++ /dev/null @@ -1,3009 +0,0 @@ -/** - * @file - * - * SMU firmware. - * - * - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: GNB - * @e \$Revision: 18962 \$ @e \$Date: 2009-09-07 20:35:39 -0700 (Mon, 07 Sep 2009) \$ - * - */ -/* - ****************************************************************************** - * - * Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - ****************************************************************************** - */ - - -#ifndef _F12NBSMUFIRMWARE_H_ -#define _F12NBSMUFIRMWARE_H_ - -UINT32 DataBlock0[] = { - 0x00110100, - 0xbdff018e, - 0x00ce03bc, - 0x00ce1810, - 0xa6082000, - 0x00a71800, - 0x8c081808, - 0xf3251000, - 0x270000cc, - 0x97bdce0b, - 0x8308006f, - 0xf8260100, - 0xbcbd248d, - 0x90fb2006, - 0xde20900a, - 0x02de3c00, - 0x3c04de3c, - 0x9f3c06de, - 0x06df3806, - 0x3804df38, - 0xdf3802df, - 0x06de3b00, - 0xde069f3c, - 0xce183c08, - 0x90fc0c83, - 0x02ed1802, - 0x180090fc, - 0x7fce00ed, - 0x03001caa, - 0xed185f4f, - 0x0ced180e, - 0x1812ed18, - 0xed1810ed, - 0x14ed1816, - 0x181aed18, - 0x85ce18ed, - 0xed02edb4, - 0x2883ce00, - 0x00ed02ed, - 0xed2c83ce, - 0xce00ed02, - 0x02ed3084, - 0x84ce00ed, - 0xed02ed2c, - 0x00ce1800, - 0xf5babd47, - 0x0c274085, - 0xcc3083ce, - 0x02ed0100, - 0x07205f4f, - 0x4f3083ce, - 0xed02ed5f, - 0xfc8fce00, - 0x02ed5f4f, - 0x82ce00ed, - 0x9993ccd6, - 0x82ce00ed, - 0xe79dccc4, - 0x82ce00ed, - 0xff9dccc6, - 0x82ce00ed, - 0x29b9ccc8, - 0x82ce00ed, - 0x699accca, - 0x82ce00ed, - 0xb293ccda, - 0x82ce00ed, - 0x8a9bccdc, - 0x82ce00ed, - 0x689bccde, - 0x82ce00ed, - 0x9294cce2, - 0x82ce00ed, - 0x9d99cce4, - 0x82ce00ed, - 0x8497cce6, - 0x82ce00ed, - 0xcd97cce8, - 0x82ce00ed, - 0x2898ccea, - 0x82ce00ed, - 0x9d98ccec, - 0x82ce00ed, - 0xf098ccee, - 0x82ce00ed, - 0x1399ccf0, - 0x82ce00ed, - 0x3899ccf2, - 0x82ce00ed, - 0x1697ccf4, - 0x82ce00ed, - 0x579cccf6, - 0x82ce00ed, - 0xea94ccf8, - 0x82ce00ed, - 0xd2b6cc9a, - 0x82ce00ed, - 0x49b9cc94, - 0xbcce00ed, - 0x09bdffb8, - 0x4f2482ce, - 0xed02ed5f, - 0x2882ce00, - 0x00ed02ed, - 0xed2c82ce, - 0xce00ed02, - 0x02ed3082, - 0x85ce00ed, - 0xed02ed84, - 0x8885ce00, - 0xed0100cc, - 0xed5f4f02, - 0x80ce1800, - 0x687ece12, - 0x00e703c6, - 0x1802df18, - 0xce647ece, - 0xefcd00fe, - 0x667ece00, - 0xed1240cc, - 0xe6188f00, - 0x7ece8f00, - 0xc400e667, - 0xcef72701, - 0x00ec607e, - 0x00ed02de, - 0x1804df18, - 0xce1480ce, - 0x00ec627e, - 0x1800ed18, - 0xce1804de, - 0x7ece1680, - 0x1640cc66, - 0x7ece00ed, - 0x1800e664, - 0xde1802df, - 0x677ece04, - 0x01c400e6, - 0x7ecef727, - 0x1800ec60, - 0xde1804df, - 0x00ed1802, - 0x08180818, - 0xec627ece, - 0x00ed1800, - 0x08180818, - 0xcc667ece, - 0x00ed1a40, - 0xe6647ece, - 0x02df1800, - 0xce04de18, - 0x00e6677e, - 0xf72701c4, - 0xec607ece, - 0x04df1800, - 0x1802de18, - 0x081800ed, - 0x7ece0818, - 0x1800ec62, - 0x081800ed, - 0x7ece0818, - 0x1e40cc66, - 0x7ece00ed, - 0x1800e664, - 0xde1802df, - 0x677ece04, - 0x01c400e6, - 0x7ecef727, - 0x1800ec60, - 0xde1804df, - 0x00ed1802, - 0x08180818, - 0xec627ece, - 0x00ed1800, - 0xbd04de18, - 0xbbbdb3b4, - 0x687eced5, - 0x00e703c6, - 0x647ece18, - 0xcd00fece, - 0x7ece00ef, - 0x5f70cc66, - 0x188f00ed, - 0xce8f00e6, - 0x00e6677e, - 0xf72701c4, - 0x18607ece, - 0x1800e68f, - 0x617ece8f, - 0x8f1800e6, - 0x8f1809d7, - 0x0409d617, - 0x04040404, - 0x83ce0fc4, - 0xce00e731, - 0xc6cc5884, - 0xcc02ed90, - 0x00ed0090, - 0xadc3e4ce, - 0x84ce1800, - 0x3083ce5e, - 0xc400e618, - 0x1800e77f, - 0x7fc400e6, - 0x83ce09d7, - 0xdb00e631, - 0x2a09d709, - 0x00e61807, - 0x09d77fc4, - 0x83ce09d6, - 0x0e00e731, - 0xc6ed84ce, - 0xc600e701, - 0xcf00e702, - 0x00defd20, - 0x3c02de3c, - 0xde3c04de, - 0x069f3c06, - 0x3806df38, - 0xdf3804df, - 0x00df3802, - 0x3c00de3b, - 0xde3c02de, - 0x06de3c04, - 0x38069f3c, - 0xdf3806df, - 0x02df3804, - 0x3b00df38, - 0x9f3c06de, - 0x06df3806, - 0x3c06de39, - 0x86ce069f, - 0xc100e600, - 0x8d07220b, - 0x7fd5ce40, - 0xdf3800ad, - 0x06de3906, - 0xce069f3c, - 0x00e60086, - 0x25220bc1, - 0x7ece278d, - 0xe7dfc601, - 0x647ece00, - 0xed02ffcc, - 0x627ece00, - 0xed0086cc, - 0x017ece00, - 0x20c400e6, - 0x9ebdf727, - 0x06df3871, - 0x3c06de39, - 0x08de069f, - 0x3c0ade3c, - 0x4f0886ce, - 0xdd0add5f, - 0xde02df08, - 0x3f001d02, - 0x1804df18, - 0x8f1802de, - 0x180700c3, - 0xde0adc8f, - 0x0100c308, - 0xdd080124, - 0x1808df0a, - 0xde1802df, - 0x00008c04, - 0x831a0626, - 0xcf230a00, - 0x86ce04df, - 0xdd5f4f04, - 0xdf08dd0a, - 0xde04de02, - 0x1800df02, - 0x081800de, - 0xc38f04df, - 0x188f0700, - 0xf08400ec, - 0x04de02df, - 0xfe00831a, - 0x00cc1426, - 0x00ed18fe, - 0xe680001d, - 0xc1f0c400, - 0x1d032620, - 0x0adc0e00, - 0x00c308de, - 0x08012401, - 0x08df0add, - 0x831a0626, - 0xb7230a00, - 0x380adf38, - 0xdf3808df, - 0x06de3906, - 0xce069f3c, - 0x00e60785, - 0x4f0000ce, - 0x2600008c, - 0x00831a06, - 0x8c2d2701, - 0x362e0000, - 0x831a342b, - 0x0b220100, - 0x2600008c, - 0x2700dd29, - 0x8c23200f, - 0x1e260000, - 0x0200831a, - 0x16201227, - 0xbd0885cc, - 0x0e20999e, - 0xbd3085cc, - 0x0620999e, - 0xbd5885cc, - 0xdf38999e, - 0x06de3906, - 0xde069f3c, - 0x0ade3c08, - 0xaa7fce3c, - 0xce01001d, - 0x001c8f7f, - 0x8d1bc610, - 0x377f846b, - 0xbd1bc636, - 0x04c62c96, - 0x7fce5e8d, - 0x10001d8f, - 0x1daa7fce, - 0x001c0100, - 0x38313101, - 0xdf380adf, - 0x06df3808, - 0x3c06de39, - 0x08de069f, - 0x3c0ade3c, - 0x1daa7fce, - 0x7fce0100, - 0x10001c8f, - 0x288d1bc6, - 0x3637808a, - 0x96bd1bc6, - 0x8d04c62c, - 0x8f7fce1b, - 0xce10001d, - 0x001daa7f, - 0x01001c01, - 0xdf383131, - 0x08df380a, - 0x3906df38, - 0x9f3c06de, - 0x3c08de06, - 0xde3c0ade, - 0x0ede3c0c, - 0xcc0dd73c, - 0x36374d00, - 0x36375f4f, - 0xce6000cc, - 0xa0bd0002, - 0x6400cca6, - 0xbd0002ce, - 0x08df84a0, - 0x37cd00cc, - 0x375f4f36, - 0x6000cc36, - 0xbd0002ce, - 0x8f18a6a0, - 0x8f180dd6, - 0x7f0edf18, - 0x0edc0e00, - 0x007f0cdd, - 0x0e007f0f, - 0x38183818, - 0x38183818, - 0x018508dc, - 0x0cde0826, - 0x8f018a8f, - 0x0edc0cdf, - 0x0cdc3637, - 0x00cc3637, - 0x0002ce64, - 0xcca6a0bd, - 0x36374e00, - 0x36375f4f, - 0xce6000cc, - 0xa0bd0002, - 0x6400cca6, - 0xbd0002ce, - 0x381884a0, - 0x38183818, - 0x38183818, - 0x180edf18, - 0x0cdf1838, - 0xdf183818, - 0x1838180a, - 0x381808df, - 0x3906df18, - 0x9f3c06de, - 0x3c08de06, - 0xde3c0ade, - 0x0ede3c0c, - 0xcc0dd73c, - 0x36374d00, - 0x36375f4f, - 0xce6000cc, - 0xa0bd0002, - 0x6400cca6, - 0xbd0002ce, - 0x08df84a0, - 0x37cd00cc, - 0x375f4f36, - 0x6000cc36, - 0xbd0002ce, - 0x8f18a6a0, - 0x8f180dd6, - 0x7f0edf18, - 0x007f0e00, - 0x0c007f0d, - 0x02ce5f4f, - 0x0e9a8f00, - 0xdd8f0fda, - 0xde0cdf0e, - 0x9a05ec06, - 0xde0fda0e, - 0x180edd0c, - 0x18381838, - 0xdc381838, - 0x26018508, - 0x018a8f06, - 0xdc0cdf8f, - 0xdc36370e, - 0xcc36370c, - 0x02ce6400, - 0xa6a0bd00, - 0xdf383838, - 0x0cdf380e, - 0x380adf38, - 0xdf3808df, - 0x06de3906, - 0xde069f3c, - 0x0ade3c08, - 0x0a007f3c, - 0x007f0bd7, - 0x08007f09, - 0x36370adc, - 0x363708dc, - 0xce6000cc, - 0xa0bd0002, - 0x6400cca6, - 0xbd0002ce, - 0x381884a0, - 0x38183818, - 0x180adf18, - 0x08df1838, - 0xdf183818, - 0x06de3906, - 0xde069f3c, - 0x0ade3c08, - 0x3c0cde3c, - 0xce3c0ede, - 0x02ec9085, - 0x00ec0edd, - 0x0edc0cdd, - 0xcaf0845f, - 0xdd0e8a04, - 0xaa7fce0e, - 0xde01001d, - 0xe19fbd0c, - 0x08df0add, - 0xe69785ce, - 0xdc062600, - 0x20118a0a, - 0x840adc04, - 0x370addef, - 0x3708dc36, - 0xde0edc36, - 0x2ca0bd0c, - 0x1caa7fce, - 0x38380100, - 0x380edf38, - 0xdf380cdf, - 0x08df380a, - 0x3906df38, - 0x9f3c06de, - 0x8f85ce06, - 0x03c400e6, - 0xce181827, - 0xe6182e84, - 0x2601c400, - 0x85ce180d, - 0x02ec188c, - 0xbd00eecd, - 0x85cecfa0, - 0xc400e68f, - 0x18162704, - 0x188c85ce, - 0xafbd00ec, - 0x2e84ce82, - 0x02c400e6, - 0xb0bd0326, - 0x06df38ea, - 0x3c06de39, - 0x85ce069f, - 0xc400e68f, - 0xce142707, - 0x00ec8c85, - 0xcefaafbd, - 0x00e62e84, - 0x032602c4, - 0xced3b1bd, - 0x00e68f85, - 0x2c2703c4, - 0xe62e84ce, - 0x2601c400, - 0x8c85ce23, - 0x00ee02ec, - 0xcee5a2bd, - 0x00e68f85, - 0x102701c4, - 0xec8c85ce, - 0xe2a6bd00, - 0xec8c85ce, - 0xfca8bd00, - 0x3906df38, - 0x9f3c06de, - 0x9b85ce06, - 0x02c400e6, - 0xce180a27, - 0xec189885, - 0x73bbbd00, - 0xe69b85ce, - 0x2703c400, - 0x84ce1828, - 0x00e6182e, - 0x1d2601c4, - 0xe68b85ce, - 0xce092600, - 0x00e69885, - 0x0d2303c1, - 0x9885ce18, - 0xcd02ec18, - 0xb2bd00ee, - 0x9885cee7, - 0x03c100e6, - 0x85ce1f22, - 0xc400e69b, - 0x180a2704, - 0x189885ce, - 0xb0bd00ec, - 0x2e84ce70, - 0x02c400e6, - 0xb0bd0326, - 0x06df38ea, - 0x3c06de39, - 0x85ce069f, - 0xc100e698, - 0xce1d2203, - 0x00e69b85, - 0x082707c4, - 0xec9885ce, - 0xaeb0bd00, - 0xe62e84ce, - 0x2602c400, - 0xd3b1bd03, - 0xe69b85ce, - 0x2702c400, - 0x2e84ce1b, - 0x01c400e6, - 0x85ce0a26, - 0xee02ec98, - 0x80b3bd00, - 0xe69885ce, - 0x3cbbbd00, - 0x3906df38, - 0x9f3c06de, - 0x9f85ce06, - 0x01c100e6, - 0x85ce0526, - 0xce006f89, - 0x00e62e84, - 0x032602c4, - 0x38eab0bd, - 0xde3906df, - 0x069f3c06, - 0xe69f85ce, - 0x2601c100, - 0x8985ce07, - 0x00e701c6, - 0xe62e84ce, - 0x2602c400, - 0xd3b1bd03, - 0x3906df38, - 0x9f3c06de, - 0x2e84ce06, - 0x02c400e6, - 0xb0bd0326, - 0x06df38ea, - 0x3c06de39, - 0x8f18069f, - 0xe6ff80ce, - 0xc60c2600, - 0xce00e704, - 0x001c207e, - 0x1c032001, - 0x7ece0400, - 0xe7efc600, - 0x217ece00, - 0xdf1800ec, - 0xce00d300, - 0x00ed277e, - 0xe6007ece, - 0x2710c400, - 0xff80cef7, - 0xe604001d, - 0xce062600, - 0x001d207e, - 0x06df3801, - 0x3c06de39, - 0x85ce069f, - 0xc400e683, - 0x7e032601, - 0x85ce459a, - 0xed5f4fb8, - 0xce00ed02, - 0x02edbc85, - 0x85ce00ed, - 0xed02edc0, - 0xc485ce00, - 0x00ed02ed, - 0xedc885ce, - 0xce00ed02, - 0x02edcc85, - 0x85ce00ed, - 0xc400e682, - 0xbd032608, - 0x83ce16b6, - 0x0004cc08, - 0x83ce00ed, - 0xed5f4f14, - 0xce00ed02, - 0x02ed1083, - 0x85ce00ed, - 0x5400e683, - 0xe71283ce, - 0xff80ce00, - 0xce08001c, - 0x00e68285, - 0x7ecef0c4, - 0xe701ca20, - 0x217ece00, - 0xce00ee1a, - 0x00ec8085, - 0x8f1800dd, - 0x8f1800d3, - 0x1a297ece, - 0x7ece00ef, - 0xe7dfc600, - 0x027ece00, - 0x2020001c, - 0xff80ce20, - 0xe608001d, - 0xce062600, - 0x001d207e, - 0x007ece01, - 0x00e7dfc6, - 0x1d027ece, - 0xb8bd2000, - 0x06df38ae, - 0x3c06de39, - 0x85ce069f, - 0xc400e6d3, - 0x7e032601, - 0x85ce479b, - 0xed5f4fe0, - 0xce00ed02, - 0x02ede485, - 0xce1800ed, - 0xbabd4918, - 0xe785cef5, - 0x85ce00e7, - 0xed5f4fe8, - 0xce00ed02, - 0x02edec85, - 0x85ce00ed, - 0xed02edf0, - 0xfc85ce00, - 0x00ed02ed, - 0xced9babd, - 0x001daa7f, - 0x8f7fce01, - 0xc610001c, - 0xd296bd1d, - 0x2883ce18, - 0xcd02ed18, - 0x04c600ef, - 0xce7095bd, - 0x001d8f7f, - 0xaa7fce10, - 0x1c01001d, - 0x83ce0100, - 0xc400e62b, - 0xce0d2701, - 0x08cc2c83, - 0xcc02ed54, - 0x0b200002, - 0xcc2c83ce, - 0x02ed5428, - 0xed0102cc, - 0xff80ce00, - 0xce01001c, - 0x00e6d285, - 0x58585858, - 0xca207ece, - 0xce00e701, - 0xee1a217e, - 0xd085ce00, - 0x00dd00ec, - 0x00d38f18, - 0x7ece8f18, - 0x00ef1a23, - 0xc6007ece, - 0xce00e7fb, - 0x001c027e, - 0xce1d2004, - 0x001dff80, - 0x2600e601, - 0x207ece06, - 0xce01001d, - 0xfbc6007e, - 0x7ece00e7, - 0x04001d02, - 0x3906df38, - 0x9f3c06de, - 0xf284ce06, - 0xf0c400ec, - 0x607e831a, - 0x00ec0726, - 0xed5000c3, - 0x3ad6ce00, - 0xdf3800ad, - 0x06de3906, - 0xce069f3c, - 0x00ecfc84, - 0x831af0c4, - 0x072600fe, - 0x00c300ec, - 0xce00ed50, - 0x00ade0d6, - 0x3906df38, - 0x9f3c06de, - 0x5884ce06, - 0xed90c6cc, - 0x0090cc02, - 0xe4ce00ed, - 0xce00adc3, - 0x001c5c84, - 0x20001d10, - 0xad92e4ce, - 0x5884ce00, - 0xed98c6cc, - 0x0090cc02, - 0xe4ce00ed, - 0xce00adc3, - 0x00e65f84, - 0xf22604c4, - 0x3906df38, - 0x9f3c06de, - 0x5884ce06, - 0xed90c6cc, - 0x0090cc02, - 0xe4ce00ed, - 0xce00adc3, - 0x001c5c84, - 0x92e4ce30, - 0x84ce00ad, - 0x98c6cc58, - 0x90cc02ed, - 0xce00ed00, - 0x00adc3e4, - 0xe65f84ce, - 0x2704c400, - 0x06df38f2, - 0x3c06de39, - 0x84ce069f, - 0x90c6cc58, - 0x90cc02ed, - 0xce00ed00, - 0x00adc3e4, - 0x1d5c84ce, - 0xe4ce3000, - 0x3800ad92, - 0xde3906df, - 0x069f3c06, - 0xce3c08de, - 0x00e63384, - 0x032703c1, - 0xce489d7e, - 0x00e62f84, - 0x032701c1, - 0xce489d7e, - 0x00e63383, - 0x9d7e0327, - 0x3283ce48, - 0x032700e6, - 0xcee09d7e, - 0xc6cc5884, - 0xcc02ed98, - 0x00ed0090, - 0x1804df18, - 0x18c3e4ce, - 0x84ce00ad, - 0xc400e65f, - 0xceed2704, - 0xc6cc5884, - 0xcc02ed90, - 0x00ed0090, - 0xadc3e4ce, - 0x84ce1800, - 0x001d185e, - 0x00e6187f, - 0xdd3183ce, - 0xd700e604, - 0xda04dc09, - 0x00e71809, - 0xcc5884ce, - 0x02ed90c6, - 0xed0090cc, - 0x92e4ce00, - 0x04df00ad, - 0xe6fc8fce, - 0xc404de00, - 0xbdf32601, - 0x8fceac9b, - 0xc400e6fc, - 0xbdf72608, - 0x04dff09b, - 0xe6fc8fce, - 0xc404de00, - 0x18f32610, - 0xbd9101ce, - 0xca8ff5ba, - 0xce188f01, - 0xbbbd9101, - 0xfc8fce12, - 0x02c400e6, - 0x9cbdf726, - 0xce04df31, - 0x00e6fc8f, - 0x20c404de, - 0x83cef326, - 0xe701c632, - 0xe09d7e00, - 0xe63283ce, - 0x2701c100, - 0xe09d7e03, - 0x9101ce18, - 0x8af5babd, - 0x01ce1801, - 0x12bbbd91, - 0xc101ce18, - 0xc4f5babd, - 0x2610c1f0, - 0x01ce18f3, - 0xf5babd91, - 0x8ffec48f, - 0x9101ce18, - 0xce12bbbd, - 0xc6cc5884, - 0xcc02ed90, - 0x00ed0090, - 0xadc3e4ce, - 0x84ce1800, - 0x001d185e, - 0x00e6187f, - 0xdd3083ce, - 0xd700e604, - 0xda04dc09, - 0x00e71809, - 0xcc5884ce, - 0x02ed90c6, - 0xed0090cc, - 0x92e4ce00, - 0x9bbd00ad, - 0xf09bbdac, - 0x18319cbd, - 0xbd9101ce, - 0xfe84f5ba, - 0x9101ce18, - 0xce12bbbd, - 0x006f3283, - 0x3808df38, - 0xde3906df, - 0x069f3c06, - 0xc63383ce, - 0xbd00e701, - 0xc9ce579c, - 0x3800ad41, - 0xde3906df, - 0x069f3c06, - 0xad68c9ce, - 0x00ce1800, - 0xf5babd47, - 0x2604845f, - 0x3383cef4, - 0x9cbd00e7, - 0x06df3857, - 0x3c06de39, - 0x85ce069f, - 0xc400e6b7, - 0xce372701, - 0x001daa7f, - 0x7fce1801, - 0x001c188f, - 0x2c83ce10, - 0x00ee02ec, - 0x1884a0bd, - 0x188f7fce, - 0x1810001d, - 0x18aa7fce, - 0x1801001d, - 0xc401001c, - 0x2603c103, - 0x0100cc05, - 0x5f4f0220, - 0x180000ce, - 0x06df1838, - 0x3c08de39, - 0xb65086ce, - 0x19270086, - 0x00a60897, - 0xa703a616, - 0xec03e700, - 0xe702a701, - 0x3a04c601, - 0x2e08007a, - 0x08df38e9, - 0x3c08de39, - 0xde3c0ade, - 0x08dd3c0c, - 0x86607ece, - 0xcc0ba701, - 0x0cedc015, - 0xedc115cc, - 0x0080cc0e, - 0xc6cc0add, - 0xdc0cdd54, - 0x868f1808, - 0xdc089709, - 0xdc00ed0a, - 0xa602ed0c, - 0x27018407, - 0x00ec18fa, - 0xec1800ed, - 0xa602ed02, - 0x27018407, - 0x8a0adcfa, - 0xdc00ed01, - 0xcb02ed0c, - 0xa60cdd04, - 0x27018407, - 0x00ec18fa, - 0xec1800ed, - 0xc602ed02, - 0xa63a1804, - 0x27018407, - 0x08007afa, - 0x0adcb52e, - 0x0cdc00ed, - 0x07a602ed, - 0xfa270184, - 0xed00ec18, - 0x02ec1800, - 0x07a602ed, - 0xfa270184, - 0x380ba74f, - 0xdf380cdf, - 0x08df380a, - 0x06de1839, - 0x069f3c18, - 0x807fce18, - 0x3701a718, - 0x02caf8c4, - 0x8f00e718, - 0xfc8a0184, - 0x1803a718, - 0xfd8602e7, - 0x8604a718, - 0x07c43301, - 0x5a480427, - 0xa718fc2e, - 0x0002cc05, - 0x1806a718, - 0x06de07e7, - 0x181606a6, - 0xed1808ed, - 0xb703860a, - 0x7fb68c7f, - 0x2680848c, - 0x06df38f9, - 0x7fce1839, - 0x01a71880, - 0xf8c43737, - 0xe71804ca, - 0x01848f00, - 0xa718fc8a, - 0x02e71803, - 0xa718fd86, - 0x33018604, - 0x042707c4, - 0xfc2e5a48, - 0xcc05a718, - 0xa7180002, - 0x07e71806, - 0x7fb70186, - 0x8c7fb68c, - 0xf9268084, - 0x1803c433, - 0x00e6183a, - 0x7fce1839, - 0x01a71880, - 0xcaf8c437, - 0x00e71804, - 0x03a7188f, - 0x4f02e718, - 0x3304a718, - 0x042704c4, - 0x0220f086, - 0xa7180f86, - 0x0002cc05, - 0x1806a718, - 0x018607e7, - 0xb68c7fb7, - 0x80848c7f, - 0xa618f926, - 0x02e61803, - 0x01a6188f, - 0x3900e618, - 0x1806de18, - 0x18069f3c, - 0x18807fce, - 0xc43701a7, - 0x00e718f8, - 0x03a7188f, - 0x4f02e718, - 0x3304a718, - 0x042704c4, - 0x0220f086, - 0xa7180f86, - 0x0002cc05, - 0x1806a718, - 0x06de07e7, - 0xe71807ec, - 0x09a71808, - 0xe71805ec, - 0x0ba7180a, - 0x7fb70386, - 0x8c7fb68c, - 0xf9268084, - 0x3906df38, - 0x807fce18, - 0x3701a718, - 0x04caf8c4, - 0x8f00e718, - 0xfc8a0384, - 0x1803a718, - 0xfd8602e7, - 0x7e04a718, - 0xde18fb9f, - 0x9f3c1806, - 0x7fce1806, - 0x01a71880, - 0xcaf8c437, - 0x00e71802, - 0x8a03848f, - 0x03a718fc, - 0x8602e718, - 0x04a718fd, - 0x184ba07e, - 0x3c1808de, - 0x180ade18, - 0x0cde183c, - 0xc4173c18, - 0x4409d701, - 0x08970184, - 0x007f0adf, - 0x08c18f0d, - 0xff864a2c, - 0x4804275d, - 0x97fc265a, - 0x9708860c, - 0x9107860b, - 0x7d1f2c0a, - 0x08270800, - 0x9a2782b6, - 0x2782b70c, - 0x2709007d, - 0x2582b608, - 0x82b70c9a, - 0x010d1425, - 0xff861620, - 0x0ad007c6, - 0x5a440427, - 0x0c94fc26, - 0x20c60c97, - 0xcb200bd7, - 0x10c10bd6, - 0xff864b2c, - 0x042708c0, - 0xfc265a48, - 0x10860c97, - 0x0f860b97, - 0x1f2c0a91, - 0x2708007d, - 0x2b82b608, - 0x82b70c9a, - 0x09007d2b, - 0x82b60827, - 0xb70c9a29, - 0x0d142982, - 0x86162002, - 0xd00fc6ff, - 0x4404270a, - 0x94fc265a, - 0xc60c970c, - 0x200bd720, - 0xc10bd6cb, - 0x864b2c18, - 0x2710c0ff, - 0x265a4804, - 0x860c97fc, - 0x860b9718, - 0x2c0a9117, - 0x08007d1f, - 0x82b60827, - 0xb70c9a2f, - 0x007d2f82, - 0xb6082709, - 0x0c9a2d82, - 0x142d82b7, - 0x1620040d, - 0x17c6ff86, - 0x04270ad0, - 0xfc265a44, - 0x0c970c94, - 0x0bd720c6, - 0x0bd6cb20, - 0x432c20c1, - 0x18c0ff86, - 0x5a480427, - 0x0c97fc26, - 0x0a911f86, - 0x007d1f2c, - 0xb6082708, - 0x0c9a3382, - 0x7d3382b7, - 0x08270900, - 0x9a3182b6, - 0x3182b70c, - 0x20080d14, - 0xc6ff8612, - 0x270ad01f, - 0x265a4404, - 0x970c94fc, - 0x7dcf200c, - 0x03260d00, - 0xcedba27e, - 0x0186607e, - 0x00cc0ba7, - 0xcc0ced28, - 0x0eed2900, - 0x01840d96, - 0x01cc2027, - 0xcc00ed20, - 0x02ed1200, - 0x018407a6, - 0x82fcfa27, - 0xfc00ed24, - 0x02ed2682, - 0x018407a6, - 0x0d96fa27, - 0x20270284, - 0xed2101cc, - 0x1200cc00, - 0x07a602ed, - 0xfa270184, - 0xed2882fc, - 0x2a82fc00, - 0x07a602ed, - 0xfa270184, - 0x04840d96, - 0x02cc2027, - 0xcc00ed21, - 0x02ed1200, - 0x018407a6, - 0x82fcfa27, - 0xfc00ed2c, - 0x02ed2e82, - 0x018407a6, - 0x0d96fa27, - 0x20270884, - 0xed2201cc, - 0x1200cc00, - 0x07a602ed, - 0xfa270184, - 0xed3082fc, - 0x3282fc00, - 0x07a602ed, - 0xfa270184, - 0x380ba74f, - 0xdf380cdf, - 0x08df380a, - 0x08de1839, - 0xde183c18, - 0x183c180a, - 0x3c180cde, - 0x180ede18, - 0x10de183c, - 0xde183c18, - 0x183c1812, - 0x3c1814de, - 0xd701c417, - 0x01844409, - 0x0adf0897, - 0xcc0d007f, - 0x0edd0000, - 0x12dd10dd, - 0xc18f14dd, - 0x86422c08, - 0x04275dff, - 0xfc265a48, - 0x08860c97, - 0x07860b97, - 0x172c0a91, - 0x2708007d, - 0x970c9604, - 0x09007d0f, - 0x0c960427, - 0x0d140e97, - 0x86162001, - 0xd007c6ff, - 0x4404270a, - 0x94fc265a, - 0xc60c970c, - 0x200bd720, - 0xc10bd6d3, - 0x86432c10, - 0x2708c0ff, - 0x265a4804, - 0x860c97fc, - 0x860b9710, - 0x2c0a910f, - 0x08007d17, - 0x0c960427, - 0x007d1197, - 0x96042709, - 0x1410970c, - 0x1620020d, - 0x0fc6ff86, - 0x04270ad0, - 0xfc265a44, - 0x0c970c94, - 0x0bd720c6, - 0x0bd6d320, - 0x432c18c1, - 0x10c0ff86, - 0x5a480427, - 0x0c97fc26, - 0x0b971886, - 0x0a911786, - 0x007d172c, - 0x96042708, - 0x7d13970c, - 0x04270900, - 0x12970c96, - 0x20040d14, - 0xc6ff8616, - 0x270ad017, - 0x265a4404, - 0x970c94fc, - 0xd720c60c, - 0xd6d3200b, - 0x2c20c10b, - 0xc0ff863b, - 0x48042718, - 0x97fc265a, - 0x911f860c, - 0x7d172c0a, - 0x04270800, - 0x15970c96, - 0x2709007d, - 0x970c9604, - 0x080d1414, - 0xff861220, - 0x0ad01fc6, - 0x5a440427, - 0x0c94fc26, - 0xd7200c97, - 0x260d007d, - 0xcca67e03, - 0x86607ece, - 0xcc0ba701, - 0x0ced2800, - 0xed2900cc, - 0x840d960e, - 0xcc2a2701, - 0x00ed2001, - 0xed1200cc, - 0x8407a602, - 0xfcfa2701, - 0x0e9a2482, - 0x82fd00ed, - 0x2682fc24, - 0x02ed0f9a, - 0xa62682fd, - 0x27018407, - 0x840d96fa, - 0xcc2a2702, - 0x00ed2101, - 0xed1200cc, - 0x8407a602, - 0xfcfa2701, - 0x109a2882, - 0x82fd00ed, - 0x2a82fc28, - 0x02ed119a, - 0xa62a82fd, - 0x27018407, - 0x840d96fa, - 0xcc2a2704, - 0x00ed2102, - 0xed1200cc, - 0x8407a602, - 0xfcfa2701, - 0x129a2c82, - 0x82fd00ed, - 0x2e82fc2c, - 0x02ed139a, - 0xa62e82fd, - 0x27018407, - 0x840d96fa, - 0xcc2a2708, - 0x00ed2201, - 0xed1200cc, - 0x8407a602, - 0xfcfa2701, - 0x149a3082, - 0x82fd00ed, - 0x3282fc30, - 0x02ed159a, - 0xa63282fd, - 0x27018407, - 0x840d96fa, - 0xcc2e2701, - 0x00ed2001, - 0xed1200cc, - 0x8407a602, - 0xfcfa2701, - 0xda532482, - 0x00ed530e, - 0xfc2482fd, - 0xda532682, - 0x02ed530f, - 0xa62682fd, - 0x27018407, - 0x840d96fa, - 0xcc2e2702, - 0x00ed2101, - 0xed1200cc, - 0x8407a602, - 0xfcfa2701, - 0xda532882, - 0x00ed5310, - 0xfc2882fd, - 0xda532a82, - 0x02ed5311, - 0xa62a82fd, - 0x27018407, - 0x840d96fa, - 0xcc2e2704, - 0x00ed2102, - 0xed1200cc, - 0x8407a602, - 0xfcfa2701, - 0xda532c82, - 0x00ed5312, - 0xfc2c82fd, - 0xda532e82, - 0x02ed5313, - 0xa62e82fd, - 0x27018407, - 0x840d96fa, - 0xcc2e2708, - 0x00ed2201, - 0xed1200cc, - 0x8407a602, - 0xfcfa2701, - 0xda533082, - 0x00ed5314, - 0xfc3082fd, - 0xda533282, - 0x02ed5315, - 0xa63282fd, - 0x27018407, - 0x00ce18fa, - 0x207ef605, - 0x54545454, - 0xbd78b4bd, - 0x7ece4d99, - 0x840d9660, - 0xcc2e2701, - 0x00ed2001, - 0xed1200cc, - 0x8407a602, - 0xfcfa2701, - 0x9a432482, - 0x00ed430e, - 0xfc2482fd, - 0x9a432682, - 0x02ed430f, - 0xa62682fd, - 0x27018407, - 0x840d96fa, - 0xcc2e2702, - 0x00ed2101, - 0xed1200cc, - 0x8407a602, - 0xfcfa2701, - 0x9a432882, - 0x00ed4310, - 0xfc2882fd, - 0x9a432a82, - 0x02ed4311, - 0xa62a82fd, - 0x27018407, - 0x840d96fa, - 0xcc2e2704, - 0x00ed2102, - 0xed1200cc, - 0x8407a602, - 0xfcfa2701, - 0x9a432c82, - 0x00ed4312, - 0xfc2c82fd, - 0x9a432e82, - 0x02ed4313, - 0xa62e82fd, - 0x27018407, - 0x840d96fa, - 0xcc2e2708, - 0x00ed2201, - 0xed1200cc, - 0x8407a602, - 0xfcfa2701, - 0x9a433082, - 0x00ed4314, - 0xfc3082fd, - 0x9a433282, - 0x02ed4315, - 0xa63282fd, - 0x27018407, - 0x0ba74ffa, - 0x3814df38, - 0xdf3812df, - 0x0edf3810, - 0x380cdf38, - 0xdf380adf, - 0x08de3908, - 0x3c0ade3c, - 0xdd3c0cde, - 0x607ece08, - 0x0ba70186, - 0xed2800cc, - 0x2900cc0c, - 0x08dc0eed, - 0x032f07c1, - 0xd789a77e, - 0xd708c60b, - 0x2e078109, - 0x860a970a, - 0xd6099720, - 0x8606200b, - 0xd60a9707, - 0xcc0bd70b, - 0x00ed2001, - 0x045f0b96, - 0x11ca408a, - 0x0cdd02ed, - 0x018407a6, - 0xce18fa27, - 0x0b968083, - 0x26048416, - 0x18585806, - 0x4805203a, - 0x3a181648, - 0xed00ec18, - 0x02ec1800, - 0x07a602ed, - 0xfa270184, - 0xed2001cc, - 0xc40cdc00, - 0xa602edfe, - 0x27018407, - 0x9c83fcfa, - 0x83fc00ed, - 0xa602ed9e, - 0x27018407, - 0x160b96fa, - 0x260a915c, - 0xc108dc98, - 0xc0742e0f, - 0xc60bd708, - 0x8109d710, - 0x800c2e0f, - 0x860a9708, - 0xd6099720, - 0x8606200b, - 0xd60a9707, - 0xcc0bd70b, - 0x00ed2101, - 0x045f0b96, - 0x11ca408a, - 0x0cdd02ed, - 0x018407a6, - 0xce18fa27, - 0xec189883, - 0x1800ed00, - 0x02ed02ec, - 0x018407a6, - 0x01ccfa27, - 0xdc00ed21, - 0xedfec40c, - 0x8407a602, - 0x18fa2701, - 0x00ed04ec, - 0xed06ec18, - 0x8407a602, - 0x96fa2701, - 0x915c160b, - 0xdcaa260a, - 0x2e17c108, - 0xd710c074, - 0xd718c60b, - 0x2e178109, - 0x9710800c, - 0x9720860a, - 0x200bd609, - 0x97078606, - 0xd70bd60a, - 0x2102cc0b, - 0x0b9600ed, - 0x408a045f, - 0x02ed11ca, - 0x07a60cdd, - 0xfa270184, - 0x9483ce18, - 0xed00ec18, - 0x02ec1800, - 0x07a602ed, - 0xfa270184, - 0xed2102cc, - 0xc40cdc00, - 0xa602edfe, - 0x27018407, - 0x08ec18fa, - 0xec1800ed, - 0xa602ed0a, - 0x27018407, - 0x160b96fa, - 0x260a915c, - 0xc108dcaa, - 0xc06c2e1f, - 0x810bd718, - 0x80082e1f, - 0xd60a9718, - 0x8606200b, - 0xd60a9707, - 0xcc0bd70b, - 0x00ed2201, - 0x045f0b96, - 0x11ca408a, - 0x0cdd02ed, - 0x018407a6, - 0xce18fa27, - 0xec189883, - 0x1800ed00, - 0x02ed02ec, - 0x018407a6, - 0x01ccfa27, - 0xdc00ed22, - 0xedfec40c, - 0x8407a602, - 0x18fa2701, - 0x00ed04ec, - 0xed06ec18, - 0x8407a602, - 0x96fa2701, - 0x915c160b, - 0x4faa260a, - 0xdf380ba7, - 0x0adf380c, - 0x3908df38, - 0xde3c08de, - 0x0cde3c0a, - 0x3c0ede3c, - 0xdd3c10de, - 0x0000cc08, - 0x10dd0add, - 0x4600ce18, - 0x54207ef6, - 0xbd545454, - 0x99bd78b4, - 0x607ece4d, - 0x0ba70186, - 0xed2800cc, - 0x2900cc0c, - 0x4a8d0eed, - 0x7f2daabd, - 0xabbd0e00, - 0x970186ac, - 0x85acbd0e, - 0xf401ce18, - 0x54207ef6, - 0xbd545454, - 0x99bd78b4, - 0x607ece4d, - 0xbd0e007f, - 0x018685ac, - 0xabbd0e97, - 0x69adbdac, - 0x4f5aaebd, - 0xdf380ba7, - 0x0edf3810, - 0x380cdf38, - 0xdf380adf, - 0xde183908, - 0x183c1808, - 0x2e07c18f, - 0xd701c616, - 0xd708c60a, - 0x2e078109, - 0x97208604, - 0x2001cc09, - 0xdcc4aebd, - 0x2e0fc108, - 0xc454542b, - 0xca01c801, - 0xc60bd702, - 0xd70ada02, - 0xd710c60a, - 0x2e0f8109, - 0x0284440d, - 0x0b94018a, - 0x20860b97, - 0x01cc0997, - 0xc4aebd21, - 0x17c108dc, - 0x04c42b2e, - 0x08ca04c8, - 0x0bd70bda, - 0x0ada04c6, - 0x18c60ad7, - 0x178109d7, - 0x84480d2e, - 0x94f78a08, - 0x860b970b, - 0xcc099720, - 0xaebd2102, - 0xc108dcc4, - 0xc41c2e1f, - 0xc8585804, - 0x840bda10, - 0x48484804, - 0xc60b971b, - 0xd70ada08, - 0x2201cc0a, - 0x18c4aebd, - 0x08df1838, - 0x840a9639, - 0xcc572701, - 0x00ed3001, - 0xbd2380cc, - 0x04a672af, - 0xff8608dc, - 0x4804275d, - 0x97fc265a, - 0x91078610, - 0x20022c08, - 0xc6ff8610, - 0x2708d007, - 0x265a4404, - 0x971094fc, - 0x7bafbd10, - 0x83fd00ec, - 0xfd02ec74, - 0x01cc7683, - 0xcc00ed30, - 0xafbd2380, - 0x7483fc72, - 0x83fc00ed, - 0xbd10da76, - 0x0a9672af, - 0x7a270684, - 0xed3101cc, - 0x2580cc00, - 0xa672afbd, - 0x7bafbd04, - 0x83fd00ec, - 0xfd02ec78, - 0x0b967a83, - 0x40160184, - 0xff880784, - 0x1b7b83b4, - 0x967b83b7, - 0x0184440b, - 0x07844016, - 0x83b4ff88, - 0x83b71b7a, - 0x440b967a, - 0x16018444, - 0x88078440, - 0x7983b4ff, - 0x7983b71b, - 0x44440b96, - 0x16018444, - 0x88078440, - 0x7883b4ff, - 0x7883b71b, - 0xed3101cc, - 0x2580cc00, - 0xfc72afbd, - 0x00ed7883, - 0xbd7a83fc, - 0x0a9672af, - 0x59270884, - 0xed3201cc, - 0x2580cc00, - 0xa672afbd, - 0x7bafbd04, - 0x83fd00ec, - 0xfd02ec7c, - 0x0b967e83, - 0x44444444, - 0x40160184, - 0xff880784, - 0x1b7f83b4, - 0xd67f83b7, - 0x0505050b, - 0x40160184, - 0xff880784, - 0x1b7e83b4, - 0xcc7e83b7, - 0x00ed3201, - 0xbd2580cc, - 0x83fc72af, - 0xfc00ed7c, - 0xafbd7e83, - 0x840a9672, - 0x18072701, - 0xbd1001ce, - 0x0a969cae, - 0x07270284, - 0x1101ce18, - 0x969caebd, - 0x2704840a, - 0x02ce1807, - 0x9caebd11, - 0x08840a96, - 0xce180727, - 0xaebd1201, - 0xa701869c, - 0x2800cc0b, - 0x00cc0ced, - 0x390eed29, - 0x06840a96, - 0xac7e0326, - 0x160b9633, - 0x84400184, - 0x48484803, - 0x260e007d, - 0xb4ff8807, - 0x03207b83, - 0xb77b83ba, - 0x48177b83, - 0x40088448, - 0x007d1884, - 0x8807260e, - 0x7a83b4ff, - 0x83ba0320, - 0x7a83b77a, - 0x08844817, - 0x7d188440, - 0x07260e00, - 0x83b4ff88, - 0xba032079, - 0x83b77983, - 0x08841779, - 0x7d188440, - 0x07260e00, - 0x83b4ff88, - 0xba032078, - 0x83b77883, - 0x3101cc78, - 0x80cc00ed, - 0x72afbd25, - 0xed7883fc, - 0x7a83fc00, - 0x9672afbd, - 0x2708840a, - 0x160b964b, - 0x40088444, - 0x007d1884, - 0x8807260e, - 0x7f83b4ff, - 0x83ba0320, - 0x7f83b77f, - 0x84444417, - 0x18844008, - 0x260e007d, - 0xb4ff8807, - 0x03207e83, - 0xb77e83ba, - 0x01cc7e83, - 0xcc00ed32, - 0xafbd2580, - 0x7c83fc72, - 0x83fc00ed, - 0x72afbd7e, - 0x160a9639, - 0x2b270184, - 0x0d970996, - 0x0c970896, - 0x27028417, - 0x97078604, - 0x01ce180c, - 0x0d965f20, - 0xcac08a04, - 0x8baebd0b, - 0x0c910d96, - 0x007c0527, - 0x96e6200d, - 0x0284160a, - 0x09963727, - 0x0d970880, - 0x08800896, - 0x84170c97, - 0x7f032701, - 0x84170d00, - 0x86042704, - 0x180c9707, - 0x5f2101ce, - 0x8a040d96, - 0xbd0bcac0, - 0x0d968bae, - 0x05270c91, - 0x200d007c, - 0x160a96e6, - 0x37270484, - 0x10800996, - 0x08960d97, - 0x0c971080, - 0x27028417, - 0x0d007f03, - 0x27088417, - 0x97078604, - 0x02ce180c, - 0x0d965f21, - 0xcac08a04, - 0x8baebd0b, - 0x0c910d96, - 0x007c0527, - 0x96e6200d, - 0x0884160a, - 0x09962e27, - 0x0d971880, - 0x18800896, - 0x84170c97, - 0x7f032704, - 0xce180d00, - 0x965f2201, - 0xc08a040d, - 0xaebd0bca, - 0x910d968b, - 0x7c05270c, - 0xe6200d00, - 0x840a9639, - 0xcc1c2701, - 0x00ed3001, - 0xbd2380cc, - 0x83fc72af, - 0xd600ed74, - 0x83f45310, - 0x7683b677, - 0x9672afbd, - 0x2706840a, - 0x160b964e, - 0x84400184, - 0x7b83ba07, - 0x177b83b7, - 0x40018444, - 0x83ba0784, - 0x7a83b77a, - 0x84444417, - 0x07844001, - 0xb77983ba, - 0x44177983, - 0x01844444, - 0xba078440, - 0x83b77883, - 0x3101cc78, - 0x80cc00ed, - 0x72afbd25, - 0xed7883fc, - 0x7a83fc00, - 0x9672afbd, - 0x2708840a, - 0x160b9636, - 0x44444444, - 0x84400184, - 0x7f83ba07, - 0x057f83b7, - 0x01840505, - 0xba078440, - 0x83b77e83, - 0x3201cc7e, - 0x80cc00ed, - 0x72afbd25, - 0xed7c83fc, - 0x7e83fc00, - 0x9672afbd, - 0x2701840a, - 0x01ce1806, - 0x96758d10, - 0x2702840a, - 0x01ce1806, - 0x96698d11, - 0x2704840a, - 0x02ce1806, - 0x965d8d11, - 0x2708840a, - 0x01ce1806, - 0x86518d12, - 0xcc0ba701, - 0x0ced2800, - 0xed2900cc, - 0x0a96390e, - 0x06270184, - 0xbd2001cc, - 0x0a961daf, - 0x06270284, - 0xbd2101cc, - 0x0a961daf, - 0x06270484, - 0xbd2102cc, - 0x0a961daf, - 0x06270884, - 0xbd2201cc, - 0x1a391daf, - 0xafbd00ef, - 0x0000cc72, - 0x0ed600ed, - 0x3972afbd, - 0xfd30ffcc, - 0x00cc647e, - 0x667efd28, - 0x607eff18, - 0xbd1500cc, - 0x00cc72af, - 0x667efd29, - 0xafbd04a6, - 0x8103a67b, - 0x39f526ff, - 0x8f1800ed, - 0xbd0b00cc, - 0x04a672af, - 0xec7bafbd, - 0xec0cdd00, - 0x180edd02, - 0x1800ed8f, - 0x0b00cc8f, - 0xdc72afbd, - 0xdc00ed0c, - 0xbddfc40e, - 0x8f1872af, - 0x8f1800ed, - 0x8d0c00cc, - 0x8d04a675, - 0xdd00ec7a, - 0xdd02ec0c, - 0xed8f180e, - 0x0c00cc00, - 0x0cdc608d, - 0x0edc00ed, - 0x568ddfc4, - 0x1800ed39, - 0x0b00cc8f, - 0x04a64c8d, - 0x00ec518d, - 0x02ec0cdd, - 0x8f180edd, - 0x8f1800ed, - 0x8d0b00cc, - 0xed0cdc35, - 0xca0edc00, - 0x182b8d20, - 0x1800ed8f, - 0x0c00cc8f, - 0x04a6208d, - 0x00ec258d, - 0x02ec0cdd, - 0x8f180edd, - 0x00cc00ed, - 0xdc0b8d0c, - 0xdc00ed0c, - 0x8d20ca0e, - 0x02ed3901, - 0x018407a6, - 0xa639fa27, - 0x27018407, - 0x08de39fa, - 0x3c0ade3c, - 0x18c108dd, - 0x0781652c, - 0x07c1612f, - 0x08c6022e, - 0x0a910ad7, - 0x17813427, - 0x0a90092c, - 0x00cc0b97, - 0x86092001, - 0x970a9017, - 0x0100cc0b, - 0x7a49590d, - 0xf82e0b00, - 0x0ad68f18, - 0x1808c04f, - 0x1821278f, - 0x8f188f8f, - 0xfc2e0905, - 0x0ad61620, - 0x0d2708c0, - 0x00cc0ad7, - 0x007a0501, - 0x20fa2e0a, - 0x0100cc03, - 0x85b45343, - 0x8785f486, - 0x388685fd, - 0xdf380adf, - 0x08de3908, - 0x3c0ade3c, - 0x18c108dd, - 0x0781632c, - 0x07c15f2f, - 0x08c6022e, - 0x0a910ad7, - 0x17813427, - 0x0a90092c, - 0x00cc0b97, - 0x86092001, - 0x970a9017, - 0x0100cc0b, - 0x7a49590d, - 0xf82e0b00, - 0x0ad68f18, - 0x1808c04f, - 0x1821278f, - 0x8f188f8f, - 0xfc2e0905, - 0x0ad61620, - 0x0d2708c0, - 0x00cc0ad7, - 0x007a0501, - 0x20fa2e0a, - 0x0100cc03, - 0xfa8685ba, - 0x85fd8785, - 0x0adf3886, - 0x3908df38, - 0xdd3c08de, - 0x58581708, - 0x971b5858, - 0x26089609, - 0x0f00cc05, - 0x01811520, - 0x00cc0526, - 0x810c20f0, - 0xcc052602, - 0x0320000f, - 0x9400f0cc, - 0x4309d409, - 0x8685b453, - 0xfd8785f4, - 0xdf388685, - 0x08de3908, - 0x1708dd3c, - 0x58585858, - 0x9609971b, - 0xcc052608, - 0x15200f00, - 0x05260181, - 0x20f000cc, - 0x2602810c, - 0x000fcc05, - 0xf0cc0320, - 0xd4099400, - 0x8685ba09, - 0xfd8785fa, - 0xdf388685, - 0x85fc3908, - 0x7e032786, - 0x85b6beb1, - 0x7e032789, - 0x85b6beb1, - 0x7e03268b, - 0xdf86beb1, - 0xce017eb7, - 0xffcc607e, - 0xcc04ed02, - 0x02ed08bd, - 0x84017eb6, - 0xcef92720, - 0x01cc3482, - 0xed00ed31, - 0x1180cc08, - 0x60c602ed, - 0x01cc0aed, - 0xed10ed21, - 0x0c00cc18, - 0x0bc612ed, - 0x02cc1aed, - 0xed20ed21, - 0x0c00cc28, - 0x0bc622ed, - 0xdf862aed, - 0xce017eb7, - 0xffcc607e, - 0xcc04ed02, - 0x02ed0abc, - 0x84017eb6, - 0xcef92720, - 0x01863482, - 0x06a706aa, - 0x0daa0186, - 0x7fcc0da7, - 0xe416a4fc, - 0xcc16ed17, - 0x1ea4fc7f, - 0x1eed1fe4, - 0xa4fc7fcc, - 0xed27e426, - 0xfc7fcc26, - 0x2fe42ea4, - 0xdf862eed, - 0xce017eb7, - 0xffcc607e, - 0xcc04ed02, - 0x02ed61bc, - 0x84017eb6, - 0xcef92720, - 0x00adf6cc, - 0xbd8b857f, - 0x1a39ea94, - 0x02ed00ef, - 0xdc7bafbd, - 0xdc00ed08, - 0xbd02ed0a, - 0xde397baf, - 0x0ade3c08, - 0x3c0cde3c, - 0xfc3c0ede, - 0x08268685, - 0x268985b6, - 0xdab27e03, - 0x278b85b6, - 0xdab27e03, - 0xad8fc9ce, - 0x607ece00, - 0x0ba70186, - 0xed2800cc, - 0x2900cc0c, - 0x5f4f0eed, - 0x7ccc08dd, - 0x180add30, - 0xcc3101ce, - 0xa38d6380, - 0xdd0003cc, - 0x03ce180a, - 0x1100cc11, - 0x5f4f958d, - 0xce180add, - 0x70cc2103, - 0xcc888d05, - 0x08dd0102, - 0xdda21fcc, - 0x01ce180a, - 0x1200cc11, - 0xccbfb1bd, - 0xb1bd1300, - 0x02ce18bf, - 0x1200cc11, - 0xccbfb1bd, - 0xb1bd1300, - 0xdd5f4fbf, - 0x180add08, - 0xcc3101ce, - 0xb1bd2380, - 0x0f77ccbf, - 0x80cc0add, - 0xbfb1bd40, - 0x08dd5f4f, - 0xce180add, - 0x00cc2103, - 0xbfb1bd09, - 0xddfb81cc, - 0x0b00cc0a, - 0x4fbfb1bd, - 0xcc0add5f, - 0xb1bd0a00, - 0xfb81ccbf, - 0x00cc0add, - 0xbfb1bd0c, - 0x0ed70ac6, - 0xdfb8bcce, - 0xdd04ec0c, - 0xdd06ec08, - 0x00ee1a0a, - 0x7ece02ec, - 0xbfb1bd60, - 0x08c60cde, - 0x0e007a3a, - 0x0186e126, - 0xbd8b85b7, - 0xdf382d95, - 0x0cdf380e, - 0x380adf38, - 0x183908df, - 0x3c1808de, - 0x180ade18, - 0x01c4173c, - 0x844409d7, - 0xdf089701, - 0x0fc48f0a, - 0x48484817, - 0x0b971b48, - 0x01840a96, - 0xf0860427, - 0x0f860220, - 0x0b970b94, - 0x58540ad6, - 0x82ce1858, - 0x7d3a1828, - 0x06270800, - 0x1803aa18, - 0x007d03a7, - 0x96082709, - 0x01aa180b, - 0xce01a718, - 0x0186607e, - 0x00cc0ba7, - 0xcc0ced28, - 0x0eed2900, - 0x16440a96, - 0x018b0184, - 0xca01cb54, - 0xcc00ed20, - 0x02ed1200, - 0x018407a6, - 0xec18fa27, - 0x1800ed00, - 0x02ed02ec, - 0x018407a6, - 0xa74ffa27, - 0x0adf380b, - 0x3908df38, - 0x1808de18, - 0x0ade183c, - 0xc4173c18, - 0x4409d701, - 0x08970184, - 0xc48f0adf, - 0x4848170f, - 0x971b4848, - 0x840a960b, - 0x86042701, - 0x860220f0, - 0x970b940f, - 0x540ad60b, - 0xce185858, - 0x3a182882, - 0x2608007d, - 0x71b47e03, - 0x1802aa18, - 0x7ece02a7, - 0xa7018660, - 0x2800cc0b, - 0x00cc0ced, - 0x960eed29, - 0x8416440a, - 0x54018b01, - 0x20ca01cb, - 0x00ed08dd, - 0xed1200cc, - 0x8407a602, - 0x18fa2701, - 0x00ed00ec, - 0xed02ec18, - 0x8407a602, - 0x96fa2701, - 0xa418430b, - 0x03a71803, - 0x00ed08dc, - 0xed1200cc, - 0x8407a602, - 0x18fa2701, - 0x00ed00ec, - 0xed02ec18, - 0x8407a602, - 0x18fa2701, - 0x00ce183c, - 0x207ef605, - 0x54545454, - 0x99bd3a8d, - 0xce38184d, - 0x0b96607e, - 0x02a41843, - 0xdc02a718, - 0xcc00ed08, - 0x02ed1200, - 0x018407a6, - 0xec18fa27, - 0x1800ed00, - 0x02ed02ec, - 0x018407a6, - 0xa74ffa27, - 0x0adf380b, - 0x3908df38, - 0x6fc010ce, - 0x8f184f04, - 0x078605ed, - 0x00cc09a7, - 0xa607ed64, - 0x27018409, - 0xc48f18fa, - 0x274d170f, - 0xe740c617, - 0xc6056f04, - 0xc609e707, - 0xe606e704, - 0x2701c409, - 0xef2e4afa, - 0xde3902ec, - 0x0ade3c08, - 0x3c0cde3c, - 0x440280b6, - 0x84444444, - 0xce099701, - 0xce181280, - 0x03a69083, - 0x0cdd02e6, - 0x00e601a6, - 0x0d007905, - 0x360c0079, - 0x09da3f84, - 0xb5bd0add, - 0x0d96339e, - 0x0c007905, - 0x0c007905, - 0x050c9616, - 0x09da3f84, - 0xce180add, - 0xb5bd9483, - 0xe604a69e, - 0x3f840403, - 0x09dafec4, - 0xce180add, - 0xb5bd9883, - 0x4804a69e, - 0x06a605e6, - 0x84054959, - 0xdafec43f, - 0x8283fd09, - 0x7f80837f, - 0x08a68183, - 0xe607a644, - 0x04564606, - 0xc43f8404, - 0xfd09dafe, - 0x837f8683, - 0x85837f84, - 0x08e609a6, - 0xfec43f84, - 0x83fd09da, - 0x88837f8a, - 0xa689837f, - 0x050ae60b, - 0x0cd70505, - 0x545409e6, - 0xda545454, - 0xc43f840c, - 0xfd09dafe, - 0x837f8e83, - 0x8d837f8c, - 0x0be60ca6, - 0x1f840404, - 0x09dafec4, - 0xce180add, - 0x3f8d9c83, - 0x380cdf38, - 0xdf380adf, - 0x0b963908, - 0x0bd60f84, - 0x5858f0c4, - 0x03a7181b, - 0x05050adc, - 0x4801c416, - 0x1b388448, - 0x9602a718, - 0x1884160a, - 0x01c45454, - 0xc40ad61b, - 0x1b585820, - 0x1801a718, - 0x9639006f, - 0xd603840b, - 0x5804c40b, - 0xc40bd61b, - 0x1b585808, - 0x0adc0c97, - 0x0505f0c4, - 0x180cda05, - 0x841603e7, - 0x58f8c407, - 0x84161b58, - 0x58c0c427, - 0x02a7181b, - 0x84160a96, - 0x54544818, - 0x181b01c4, - 0x6f1801a7, - 0xfecc3900, - 0xfc84fd00, - 0xfdf370cc, - 0x00ccfe84, - 0xfa84fd03, - 0x8de0d6bd, - 0xa085f775, - 0x8fa185b7, - 0x86a285b7, - 0xff84b7f6, - 0x8de0d6bd, - 0xa385f761, - 0x8fa685b7, - 0x86a785b7, - 0xff84b7f9, - 0x8de0d6bd, - 0xae85fd4d, - 0xad85b78f, - 0x84b7fc86, - 0xe0d6bdff, - 0x85fd3c8d, - 0x85b78faa, - 0xb7ff86a9, - 0xd6bdff84, - 0xf72b8de0, - 0x85b7a485, - 0x85b78fa5, - 0x0a71cca8, - 0xbdfe84fd, - 0x85cee0d6, - 0x02ee1a00, - 0x185401e6, - 0x1856468f, - 0x8f18548f, - 0x84fd5646, - 0x08de39be, - 0x0085ce3c, - 0x03a600e6, - 0x01e608dd, - 0x007902a6, - 0x79495909, - 0x00790800, - 0x79495909, - 0x00790800, - 0x79495909, - 0x08de0800, - 0xdf183818, - 0x08de3908, - 0x3c0ade3c, - 0x86607ece, - 0xcc08a703, - 0x04ed60fe, - 0xed0200cc, - 0xa604a606, - 0x27018407, - 0x0b974ffa, - 0x018403a6, - 0x274d0a97, - 0x8403a62e, - 0x4d0a9704, - 0x83ce2527, - 0x2702ec10, - 0x8407110f, - 0x4d0b9704, - 0x036f0427, - 0x036c0220, - 0xd70883f6, - 0x06ee1a08, - 0xef1a0818, - 0xce392006, - 0x036f1083, - 0xfd0090cc, - 0xc6cc5884, - 0x5a84fde4, - 0xcec3e4bd, - 0x84b60000, - 0x01c4165f, - 0x0404163a, - 0x163a01c4, - 0x01c40404, - 0x0404163a, - 0x8f3a01c4, - 0xd704cb50, - 0x0883f708, - 0xb885ce4f, - 0xd6f7b8bd, - 0x85ce4f08, - 0xf7b8bdc0, - 0xd7a685f6, - 0x85ce1809, - 0xdbb8bdb8, - 0xd7a785f6, - 0x85ce1809, - 0xdbb8bdc0, - 0x08978086, - 0x848285b6, - 0xce5b2704, - 0x0386607e, - 0xfecc08a7, - 0xcc04ed70, - 0x06ed0200, - 0x07a604a6, - 0xfa270184, - 0x048403a6, - 0x01884444, - 0xc885ce5f, - 0xf6f7b8bd, - 0x09d7a585, - 0xc885ce18, - 0xcedbb8bd, - 0xce18cc85, - 0x00ec0000, - 0x02a61426, - 0x03a61026, - 0x24a485b1, - 0x84fe1809, - 0xa885b6be, - 0xff180897, - 0xb74fab7f, - 0x85cead7f, - 0xa085f6ac, - 0xbc85fe18, - 0x85b62026, - 0xb61b26be, - 0x85f6bf85, - 0x2503a1a3, - 0xa285f611, - 0x0a2502a1, - 0xa1a185f6, - 0xf6032501, - 0x09d7a085, - 0xf6a885ce, - 0xfe18a085, - 0x1d26c485, - 0x26c685b6, - 0xc785b618, - 0x112201a1, - 0xa1a185f6, - 0xf60a2202, - 0x03a1a285, - 0x85f60322, - 0x2209d1a3, - 0xd609d702, - 0x18054f08, - 0x4f09d68f, - 0xd740eabd, - 0x260a9609, - 0x0091cc1c, - 0xcc5884fd, - 0x84fd0cc4, - 0xc3e4bd5a, - 0x84f709d6, - 0xf781c65d, - 0xe4bd5884, - 0x1083ce92, - 0x00c304ec, - 0xc304ed01, - 0x0a260000, - 0x06ec8f18, - 0x8f1800ed, - 0x0b9606ed, - 0x8085f35f, - 0xfd217ef3, - 0xdf86297e, - 0x38007eb7, - 0xdf380adf, - 0x91cc3908, - 0x5884fd00, - 0xfd0cc4cc, - 0xe4bd5a84, - 0xa085f6c3, - 0xc65d84f7, - 0x5884f781, - 0xb692e4bd, - 0x04848285, - 0x4f5f0827, - 0xb7ab7ffd, - 0x1839ad7f, - 0xeecd00ec, - 0x09007d02, - 0x8f040a27, - 0x7a8f5646, - 0xf6260900, - 0xcd04ed18, - 0x583906ef, - 0xe3585858, - 0xec02ed02, - 0x8900c900, - 0xec00ed00, - 0x18435304, - 0x5306ec8f, - 0x0100c343, - 0x00c98f18, - 0x8f180089, - 0x02ed02e3, - 0x01e98f18, - 0x00ed00a9, - 0xb385f639, - 0xf68f184f, - 0x5454207e, - 0xb4bd5454, - 0x8f7fce78, - 0xbd10001c, - 0x7fce4d99, - 0x10001d8f, - 0x3c08de39, - 0xde3c0ade, - 0x85ce3c0c, - 0xce08dfd4, - 0x85b6fc85, - 0x444444d3, - 0x2703a144, - 0x7e036c05, - 0x036fc1ba, - 0x5d219ebd, - 0x80cc2f27, - 0x5884fd00, - 0xfd80c6cc, - 0x85fc5a84, - 0xc4f884f4, - 0x5c84fd8f, - 0xfdf685fc, - 0xe4bd5e84, - 0xb7fb8692, - 0x7eb6007e, - 0xb7fb8402, - 0xba7e027e, - 0x18ce18cf, - 0xf5babd48, - 0xfde085ff, - 0x08dee285, - 0x032600e6, - 0x4fc1ba7e, - 0x08de0c97, - 0x032600e6, - 0x8f64ba7e, - 0x86e385f6, - 0x07270901, - 0x007c4854, - 0xd7f6200c, - 0xc40b970a, - 0xd6132701, - 0xe785f40b, - 0x01867326, - 0x00e608de, - 0xe885ce5a, - 0xce181a20, - 0x03860718, - 0x00e608de, - 0x183d375a, - 0xf5babd3a, - 0x01844417, - 0x33e885ce, - 0x4d00a73a, - 0x066f0426, - 0x85f60e20, - 0x07c454d3, - 0x042706e1, - 0x3520066c, - 0x00e608de, - 0x545407c4, - 0xce1801c8, - 0x3a18f485, - 0x274d06e6, - 0x00ea1810, - 0xd600e718, - 0xfb85fa0b, - 0x20fb85f7, - 0xe4185310, - 0x00e71800, - 0xf4530bd6, - 0x85f7fb85, - 0x09007cfb, - 0x860c007c, - 0x270c9106, - 0xb7b97e03, - 0xf1fb85f6, - 0x5527e785, - 0xfd0080cc, - 0xc6cc5884, - 0x5a84fd80, - 0xfdf485fc, - 0x85fc5c84, - 0x5e84fdf6, - 0x1892e4bd, - 0x8d4918ce, - 0x2083ff68, - 0x182283fd, - 0xfe4918ce, - 0x85fcf885, - 0x2602c1fa, - 0xbeaace07, - 0x0520ef86, - 0x86bedece, - 0xe485ffad, - 0x8de685fd, - 0x18ce185d, - 0xff3a8d49, - 0x83fd2483, - 0xd085fc26, - 0xfd217ef3, - 0xfb86237e, - 0x38007eb7, - 0xdf380cdf, - 0x08df380a, - 0x0090cc39, - 0xcc5884fd, - 0x84fd80c6, - 0xc3e4bd5a, - 0xfd5c84fc, - 0x84fcf485, - 0xf685fd5e, - 0x7eff1839, - 0xffce1866, - 0x7eff1830, - 0x647eb664, - 0x84677eb6, - 0xfef92701, - 0x7efc607e, - 0xff183962, - 0x8c18667e, - 0x0a264918, - 0x1a83ff18, - 0xfd1c83ff, - 0xce181e83, - 0xff1830ff, - 0x7eff647e, - 0x627efd60, - 0x84677eb6, - 0x39f92701, - 0xde3c08de, - 0x08d73c0a, - 0xc4028417, - 0x54544404, - 0x8f2101c3, - 0x01c408d6, - 0x0b00c34f, - 0x2800ce18, - 0xce18b48d, - 0x918d2900, - 0xce1801ca, - 0xa68d2900, - 0x380adf38, - 0xde3908df, - 0x0ade3c08, - 0xc10fc43c, - 0xdd4f260f, - 0x02841608, - 0x544404c4, - 0x2101c354, - 0xd68f0add, - 0x4f01c408, - 0x180b00c3, - 0xbd2800ce, - 0xce1812bb, - 0xbabd2900, - 0x18fec4f5, - 0xbd2900ce, - 0x0ade12bb, - 0x01840896, - 0x0306c35f, - 0xce18f08a, - 0xbbbd2800, - 0x0000ce12, - 0x180300cc, - 0xbd2900ce, - 0xdf3812bb, - 0x08df380a, - 0x18ce1839, - 0xf5babd49, - 0x18263fc4, - 0x4918ce18, - 0xcc0000ce, - 0xbbbd3f00, - 0x0000cc12, - 0xfdf885fd, - 0x0a20fa85, - 0xff0000ce, - 0xfd4ff885, - 0x4f39fa85, - 0x3e0e3906, - 0x820cfc20, - 0x30002834, - 0x01c004ff, - 0xff300029, - 0x2800c004, - 0x04ff3000, - 0x002901c0, - 0xc004ff30, - 0x30002800, - 0x01c004ff, - 0xff300029, - 0x2800c004, - 0x04ff3000, - 0x002901c0, - 0xc004ff30, - 0x30002800, - 0x01c004ff, - 0xff300029, - 0x2800c004, - 0x04ff3000, - 0x002901c0, - 0xc004ff30, - 0x34820c00, - 0xff300028, - 0x2909c004, - 0x04ff3000, - 0x002809c0, - 0xc004ff30, - 0x30002909, - 0x09c004ff, - 0xff300028, - 0x2909c004, - 0x04ff3000, - 0x002809c0, - 0xc004ff30, - 0x30002909, - 0x09c004ff, - 0xff300028, - 0x2909c004, - 0x04ff3000, - 0x002809c0, - 0xc004ff30, - 0x30002909, - 0x01c004ff, - 0x10803101, - 0x00000000, - 0x11803101, - 0x00000000, - 0x12803101, - 0x00000000, - 0x13803101, - 0x00000000, - 0x14803101, - 0x00000000, - 0x15803101, - 0x00000000, - 0x16803101, - 0x00000000, - 0x17803101, - 0x00000000, - 0x11000102, - 0x00000000, - 0x63803101, - 0x00000000, - 0x28000014, - 0x04ff3000, - 0x002901c0, - 0xc004ff30, - 0x30002800, - 0x01c004ff, - 0xff300029, - 0x2800c004, - 0x04ff3000, - 0x002901c0, - 0xc004ff30, - 0x30002800, - 0x01c004ff, - 0xff300029, - 0x2800c004, - 0x04ff3000, - 0x002901c0, - 0xc004ff30, - 0x30002800, - 0x01c004ff, - 0xff300029, - 0x2800c004, - 0x04ff3000, - 0x002901c0, - 0xc004ff30, - 0x30002800, - 0x01c004ff, - 0xff300029, - 0x2800c004, - 0x04ff3000, - 0x002901c0, - 0xc004ff30, - 0x30002800, - 0x01c004ff, - 0xff300029, - 0x0000c004 -}; - -UINT32 DataBlock1[] = { - 0x3b903b90, - 0x3b903b90, - 0x3b903b90, - 0x3b903b90, - 0x3b903b90, - 0x3b903b90, - 0x3b903b90, - 0x3b903b90, - 0x3b903b90, - 0x3b903b90, - 0x3b903b90, - 0x3b903b90, - 0xc0e33b90, - 0x3b90d8e3, - 0x04900490, - 0x04900490 -}; - -SMU_FIRMWARE_BLOCK FmBlockArray[] = { - { - 0x9000, - 0xb66, - &DataBlock0[0] - }, - { - 0xbfc0, - 0x10, - &DataBlock1[0] - } -}; - -SMU_FIRMWARE_HEADER Fm = { - { - 0x1, 0x1100 - }, - 2, - &FmBlockArray[0] -}; -#endif - diff --git a/src/vendorcode/amd/agesa/f12/Proc/GNB/Nb/Family/LN/Makefile.inc b/src/vendorcode/amd/agesa/f12/Proc/GNB/Nb/Family/LN/Makefile.inc deleted file mode 100644 index 477451e560..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/GNB/Nb/Family/LN/Makefile.inc +++ /dev/null @@ -1,4 +0,0 @@ -libagesa-y += F12NbLclkDpm.c -libagesa-y += F12NbPowerGate.c -libagesa-y += F12NbServices.c -libagesa-y += F12NbSmu.c diff --git a/src/vendorcode/amd/agesa/f12/Proc/GNB/Nb/Family/NbFamilyServices.h b/src/vendorcode/amd/agesa/f12/Proc/GNB/Nb/Family/NbFamilyServices.h deleted file mode 100644 index 483bcf3613..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/GNB/Nb/Family/NbFamilyServices.h +++ /dev/null @@ -1,114 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * Family specific service routine - * - * - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: GNB - * @e \$Revision: 47475 $ @e \$Date: 2011-02-22 11:28:52 +0800 (Tue, 22 Feb 2011) $ - * - */ -/* -***************************************************************************** -* -* Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* *************************************************************************** -* -*/ - -#ifndef _NBFAMILYSERVICES_H_ -#define _NBFAMILYSERVICES_H_ - -/// Fuse field entry -typedef struct { - UINT8 FieldOffset; ///< Field offset in fuse register - UINT8 FieldWidth; ///< Width of field - UINT16 FuseOffset; ///< destination offset in translation table -} FUSE_REGISTER_ENTRY; - -/// Fuse register entry -typedef struct { - UINT32 Register; ///< FCR register address - UINT8 FuseRegisterTableLength; ///< Length of field table for this register - FUSE_REGISTER_ENTRY *FuseRegisterTable; ///< Pointer to field table -} FUSE_TABLE_ENTRY; - -/// Fuse translation table -typedef struct { - UINT8 FuseTableLength; ///< Length of translation table - FUSE_TABLE_ENTRY *FuseTable; ///< Pointer to register table -} FUSE_TABLE; - -/// NB power gate configuration -typedef struct { - struct { - UINT32 GmcPowerGate:1; ///< Power Gate GMC - UINT32 GfxPowerGate:1; ///< Power gate GFX - UINT32 UvdPowerGate:1; ///< Power gate UVD - } Services; ///< Power gate services - POWER_GATE_DATA Gmc; ///< Gmc Power gating Data - POWER_GATE_DATA Uvd; ///< Uvd Power gating Data -} NB_POWERGATE_CONFIG; - -VOID -NbFmNbClockGating ( - IN OUT VOID *NbClkGatingCtrl, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -VOID -NbFmClumpUnitID ( - IN PCI_ADDR NbPciAddress, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -FUSE_TABLE* -NbFmGetFuseTranslationTable ( - VOID - ); - -VOID -NbFmFuseAdjustFuseTablePatch ( - IN OUT PP_FUSE_ARRAY *PpFuseArray, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -UINT32 -NbFmDpmStateBootupInit ( - IN UINT32 LclkDpmValid, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -AGESA_STATUS -NbFmInitLclkDpmRcActivity ( - IN AMD_CONFIG_PARAMS *StdHeader - ); -#endif - diff --git a/src/vendorcode/amd/agesa/f12/Proc/GNB/Nb/Feature/Makefile.inc b/src/vendorcode/amd/agesa/f12/Proc/GNB/Nb/Feature/Makefile.inc deleted file mode 100644 index fca82d5f13..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/GNB/Nb/Feature/Makefile.inc +++ /dev/null @@ -1,2 +0,0 @@ -libagesa-y += NbFuseTable.c -libagesa-y += NbLclkDpm.c diff --git a/src/vendorcode/amd/agesa/f12/Proc/GNB/Nb/Feature/NbFuseTable.c b/src/vendorcode/amd/agesa/f12/Proc/GNB/Nb/Feature/NbFuseTable.c deleted file mode 100644 index bb9ad5ea9e..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/GNB/Nb/Feature/NbFuseTable.c +++ /dev/null @@ -1,432 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * Fuse table initialization - * - * - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: GNB - * @e \$Revision: 48452 $ @e \$Date: 2011-03-09 12:50:44 +0800 (Wed, 09 Mar 2011) $ - * - */ -/* -***************************************************************************** -* -* Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* *************************************************************************** -* -*/ - -/*---------------------------------------------------------------------------------------- - * M O D U L E S U S E D - *---------------------------------------------------------------------------------------- - */ - -#include "AGESA.h" -#include "amdlib.h" -#include "Ids.h" -#include "heapManager.h" -#include "Gnb.h" -#include "GnbFuseTable.h" -#include "GnbCommonLib.h" -#include "GnbNbInitLibV1.h" -#include "OptionGnb.h" -#include "GnbRegistersLN.h" -#include "NbSmuLib.h" -#include "NbConfigData.h" -#include "NbFuseTable.h" -#include "NbFamilyServices.h" -#include "GfxLib.h" -#include "Filecode.h" - -#define FILECODE PROC_GNB_NB_FEATURE_NBFUSETABLE_FILECODE -/*---------------------------------------------------------------------------------------- - * D E F I N I T I O N S A N D M A C R O S - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------- - * T Y P E D E F S A N D S T R U C T U R E S - *---------------------------------------------------------------------------------------- - */ -extern GNB_BUILD_OPTIONS GnbBuildOptions; - -/*---------------------------------------------------------------------------------------- - * P R O T O T Y P E S O F L O C A L F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ - -VOID -NbFuseLoadDefaultFuseTable ( - OUT PP_FUSE_ARRAY *PpFuseArray, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -VOID -NbFuseLoadFuseTableFromFcr ( - OUT PP_FUSE_ARRAY *PpFuseArray, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -VOID -NbFuseDebugDump ( - IN PP_FUSE_ARRAY *PpFuseArray, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -VOID -NbFuseAdjustFuseTableToCurrentMainPllVco ( - IN OUT PP_FUSE_ARRAY *PpFuseArray, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -PP_FUSE_ARRAY DefaultPpFuseArray = { - 0, ///< PP table revision - {1, 0, 0, 0, 0, 0}, ///< Valid DPM states - {0x40, 0, 0, 0, 0, 0}, ///< Sclk DPM DID - {0, 0, 0, 0, 0, 0}, ///< Sclk DPM VID - {0, 0, 0, 0, 0}, ///< Sclk DPM Cac - {1, 0, 0, 0, 0, 0}, ///< State policy flags - {2, 0, 0, 0, 0, 0}, ///< State policy label - {0x40, 0, 0, 0}, ///< VCLK DID - {0x40, 0, 0, 0}, ///< DCLK DID - 0x40, ///< Thermal SCLK - {0, 0, 0, 0, 0, 0}, ///< Vclk/Dclk selector - {0, 0, 0, 0}, ///< Valid Lclk DPM states - {0, 0, 0, 0}, ///< Lclk DPM DID - {0, 0, 0, 0}, ///< Lclk DPM VID - {0, 0, 0, 0}, ///< Displclk DID - 3, ///< Pcie Gen 2 VID - 0x10, ///< Main PLL id for 3200 VCO - 0, ///< WRCK SMU clock Divisor - {0x24, 0x24, 0x24, 0x24} ///< Sclk VID -}; - - -/*----------------------------------------------------------------------------------------*/ -/** - * Fuse Table Init - * - * - * - * @param[in] StdHeader Pointer to Standard configuration - * @retval AGESA_STATUS - */ - -AGESA_STATUS -NbFuseTableFeature ( - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - PP_FUSE_ARRAY *PpFuseArray; - D18F3xA0_STRUCT D18F3xA0; - BOOLEAN LoadDefaultFuses; - IDS_HDT_CONSOLE (GNB_TRACE, "NbFuseTableFeature Enter\n"); - - PpFuseArray = (PP_FUSE_ARRAY *) GnbAllocateHeapBuffer (AMD_PP_FUSE_TABLE_HANDLE, sizeof (PP_FUSE_ARRAY), StdHeader); - ASSERT (PpFuseArray != NULL); - if (PpFuseArray == NULL) { - IDS_HDT_CONSOLE (GNB_TRACE, " ERROR!!! Heap Allocation\n"); - return AGESA_ERROR; - } - LibAmdMemFill (PpFuseArray, 0x00, sizeof (PP_FUSE_ARRAY), StdHeader); - GnbLibPciRead ( - MAKE_SBDFO ( 0, 0, 0x18, 3, D18F3xA0_ADDRESS), - AccessWidth32, - &D18F3xA0.Value, - StdHeader - ); - - LoadDefaultFuses = TRUE; - if (GnbBuildOptions.GnbLoadRealFuseTable == 1) { - if (D18F3xA0.Field.CofVidProg == 1) { - IDS_HDT_CONSOLE (NB_MISC, " Processor Fused\n"); - NbFuseLoadFuseTableFromFcr (PpFuseArray, StdHeader); - if (PpFuseArray->PPlayTableRev != 0) { - LoadDefaultFuses = FALSE; - } else { - IDS_HDT_CONSOLE (NB_MISC, " PowerPlay Table Unfused\n"); - } - } else { - IDS_HDT_CONSOLE (NB_MISC, " Processor Unfuse\n"); - } - } else { - IDS_HDT_CONSOLE (NB_MISC, " Force default fuse table Unfuse\n"); - } - - if (LoadDefaultFuses) { - IDS_HDT_CONSOLE (NB_MISC, " Load default fuses\n"); - NbFuseLoadDefaultFuseTable (PpFuseArray, StdHeader); - } - NbFmFuseAdjustFuseTablePatch (PpFuseArray, StdHeader); - NbFuseAdjustFuseTableToCurrentMainPllVco (PpFuseArray, StdHeader); - IDS_OPTION_CALLOUT (IDS_CALLOUT_GNB_PPFUSE_OVERRIDE, PpFuseArray, StdHeader); - GNB_DEBUG_CODE ( - NbFuseDebugDump (PpFuseArray, StdHeader) - ); - IDS_HDT_CONSOLE (GNB_TRACE, "NbFuseTableFeature Exit\n"); - return AGESA_SUCCESS; -} - - -/*----------------------------------------------------------------------------------------*/ -/** - * Load Fuse Table From FCRs - * - * - * @param[out] PpFuseArray Pointer to save fuse table - * @param[in] StdHeader Pointer to Standard configuration - * @retval AGESA_STATUS - */ - -VOID -NbFuseLoadFuseTableFromFcr ( - OUT PP_FUSE_ARRAY *PpFuseArray, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - FUSE_TABLE *FuseTable; - UINTN RegisterIndex; - FuseTable = NbFmGetFuseTranslationTable (); - for (RegisterIndex = 0; RegisterIndex < FuseTable->FuseTableLength; RegisterIndex++ ) { - UINTN FieldIndex; - UINTN FuseRegisterTableLength; - UINT32 FuseValue; - FuseRegisterTableLength = FuseTable->FuseTable[RegisterIndex].FuseRegisterTableLength; - FuseValue = NbSmuReadEfuse ( - FuseTable->FuseTable[RegisterIndex].Register, - StdHeader - ); - for (FieldIndex = 0; FieldIndex < FuseRegisterTableLength; FieldIndex++) { - FUSE_REGISTER_ENTRY RegisterEntry; - UINT8 *FuseArrayPtr; - UINT32 FuseArrauValue; - RegisterEntry = FuseTable->FuseTable[RegisterIndex].FuseRegisterTable[FieldIndex]; - FuseArrayPtr = (UINT8*) PpFuseArray + RegisterEntry.FuseOffset; - FuseArrauValue = (FuseValue >> RegisterEntry.FieldOffset) & ((1 << RegisterEntry.FieldWidth) - 1); - if (RegisterEntry.FieldWidth > 16) { - *((UINT32 *) FuseArrayPtr) = FuseArrauValue; - } else if (RegisterEntry.FieldWidth > 8) { - *((UINT16 *) FuseArrayPtr) = (UINT16) FuseArrauValue; - } else { - *((UINT8 *) FuseArrayPtr) = (UINT8) FuseArrauValue; - } - } - } -} - -/*----------------------------------------------------------------------------------------*/ -/** - * Load Default Fuse Table - * - * - * @param[out] PpFuseArray Pointer to save fuse table - * @param[in] StdHeader Pointer to Standard configuration - * @retval AGESA_STATUS - */ - -VOID -NbFuseLoadDefaultFuseTable ( - OUT PP_FUSE_ARRAY *PpFuseArray, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - D18F3x15C_STRUCT D18F3x15C; - UINT8 MaxVidIndex; - LibAmdMemCopy (PpFuseArray, &DefaultPpFuseArray, sizeof (PP_FUSE_ARRAY), StdHeader); - GnbLibPciRead ( - MAKE_SBDFO ( 0, 0, 0x18, 3, D18F3x15C_ADDRESS), - AccessWidth32, - &D18F3x15C.Value, - StdHeader - ); - if (D18F3x15C.Value == 0) { - D18F3x15C.Value = 0x24242424; - GnbLibPciWrite ( - MAKE_SBDFO ( 0, 0, 0x18, 3, D18F3x15C_ADDRESS), - AccessWidth32, - &D18F3x15C.Value, - StdHeader - ); - } - MaxVidIndex = GnbLocateHighestVidIndex (StdHeader); - PpFuseArray->SclkDpmVid[0] = MaxVidIndex; - PpFuseArray->PcieGen2Vid = MaxVidIndex; - -} - -/*----------------------------------------------------------------------------------------*/ -/** - * Adjust DIDs to current main PLL VCO - * - * Main PLL VCO can be changed for debug perpouses - * - * @param[in,out] PpFuseArray Pointer to save fuse table - * @param[in] StdHeader Pointer to Standard configuration - */ - -VOID -NbFuseAdjustFuseTableToCurrentMainPllVco ( - IN OUT PP_FUSE_ARRAY *PpFuseArray, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - UINT32 EffectiveMainPllFreq10KHz; - UINT32 FusedMainPllFreq10KHz; - UINT32 TempVco; - UINTN Index; - EffectiveMainPllFreq10KHz = GfxLibGetMainPllFreq (StdHeader) * 100; - FusedMainPllFreq10KHz = (PpFuseArray->MainPllId + 0x10) * 100 * 100; - if (FusedMainPllFreq10KHz != EffectiveMainPllFreq10KHz) { - IDS_HDT_CONSOLE (NB_MISC, " WARNING! Adjusting fuse table for reprogrammed VCO \n"); - IDS_HDT_CONSOLE (NB_MISC, " Actual main Freq %d \n", EffectiveMainPllFreq10KHz); - IDS_HDT_CONSOLE (NB_MISC, " Fused main Freq %d \n", FusedMainPllFreq10KHz); - for (Index = 0; Index < 5; Index++) { - if (PpFuseArray->SclkDpmDid[Index] != 0) { - TempVco = GfxLibCalculateClk (PpFuseArray->SclkDpmDid[Index], FusedMainPllFreq10KHz); - PpFuseArray->SclkDpmDid[Index] = GfxLibCalculateDid (TempVco, EffectiveMainPllFreq10KHz); - } - } - for (Index = 0; Index < 4; Index++) { - if (PpFuseArray->VclkDid[Index] != 0) { - TempVco = GfxLibCalculateClk (PpFuseArray->VclkDid[Index], FusedMainPllFreq10KHz); - PpFuseArray->VclkDid[Index] = GfxLibCalculateDid (TempVco, EffectiveMainPllFreq10KHz); - } - if (PpFuseArray->DclkDid[Index] != 0) { - TempVco = GfxLibCalculateClk (PpFuseArray->DclkDid[Index], FusedMainPllFreq10KHz); - PpFuseArray->DclkDid[Index] = GfxLibCalculateDid (TempVco, EffectiveMainPllFreq10KHz); - } - if (PpFuseArray->LclkDpmDid[Index] != 0) { - TempVco = GfxLibCalculateClk (PpFuseArray->LclkDpmDid[Index], FusedMainPllFreq10KHz); - PpFuseArray->LclkDpmDid[Index] = GfxLibCalculateDid (TempVco, EffectiveMainPllFreq10KHz); - } - if (PpFuseArray->DisplclkDid[Index] != 0) { - TempVco = GfxLibCalculateClk (PpFuseArray->DisplclkDid[Index], FusedMainPllFreq10KHz); - PpFuseArray->DisplclkDid[Index] = GfxLibCalculateDid (TempVco, EffectiveMainPllFreq10KHz); - } - } - if (PpFuseArray->SclkThermDid != 0) { - TempVco = GfxLibCalculateClk (PpFuseArray->SclkThermDid , FusedMainPllFreq10KHz); - PpFuseArray->SclkThermDid = GfxLibCalculateDid (TempVco, EffectiveMainPllFreq10KHz); - } - } -} - -/*----------------------------------------------------------------------------------------*/ -/** - * Debug dump fuse table - * - * - * @param[out] PpFuseArray Pointer to save fuse table - * @param[in] StdHeader Pointer to Standard configuration - */ - -VOID -NbFuseDebugDump ( - IN PP_FUSE_ARRAY *PpFuseArray, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - UINTN Index; - UINT32 EffectiveMainPllFreq10KHz; - - EffectiveMainPllFreq10KHz = GfxLibGetMainPllFreq (StdHeader) * 100; - IDS_HDT_CONSOLE (NB_MISC, "<------------ GNB FUSE TABLE------------>\n"); - for (Index = 0; Index < 4; Index++) { - if (PpFuseArray->LclkDpmValid[Index] != 0) { - IDS_HDT_CONSOLE ( - NB_MISC, - " LCLK DID[%d] - 0x%02x (%dMHz)\n", - Index, - PpFuseArray->LclkDpmDid[Index], - GfxLibCalculateClk (PpFuseArray->LclkDpmDid[Index], EffectiveMainPllFreq10KHz) / 100); - IDS_HDT_CONSOLE (NB_MISC, " LCLK VID[%d] - 0x02%x\n", Index, PpFuseArray->LclkDpmVid[Index]); - } - } - for (Index = 0; Index < 4; Index++) { - IDS_HDT_CONSOLE ( - NB_MISC, - " VCLK DID[%d] - 0x%02x (%dMHz)\n", - Index, - PpFuseArray->VclkDid[Index], - (PpFuseArray->VclkDid[Index] != 0) ? (GfxLibCalculateClk (PpFuseArray->VclkDid[Index], EffectiveMainPllFreq10KHz) / 100) : 0 - ); - IDS_HDT_CONSOLE ( - NB_MISC, - " DCLK DID[%d] - 0x%02x (%dMHz)\n", - Index, - PpFuseArray->DclkDid[Index], - (PpFuseArray->DclkDid[Index] != 0) ? (GfxLibCalculateClk (PpFuseArray->DclkDid[Index], EffectiveMainPllFreq10KHz) / 100) : 0 - ); - } - for (Index = 0; Index < 4; Index++) { - IDS_HDT_CONSOLE ( - NB_MISC, - " DISPCLK DID[%d] - 0x%02x (%dMHz)\n", - Index, - PpFuseArray->DisplclkDid[Index], - (PpFuseArray->DisplclkDid[Index] != 0) ? (GfxLibCalculateClk (PpFuseArray->DisplclkDid[Index], EffectiveMainPllFreq10KHz) / 100) : 0 - ); - } - for (Index = 0; Index < 6; Index++) { - IDS_HDT_CONSOLE ( - NB_MISC, - " SCLK DID[%d] - 0x%02x (%dMHz)\n", - Index, - PpFuseArray->SclkDpmDid[Index], - (PpFuseArray->SclkDpmDid[Index] != 0) ? (GfxLibCalculateClk (PpFuseArray->SclkDpmDid[Index], EffectiveMainPllFreq10KHz) / 100) : 0 - ); - IDS_HDT_CONSOLE ( - NB_MISC, - " SCLK TDP[%d] - 0x%x \n", - Index, - PpFuseArray->SclkDpmTdpLimit[Index] - ); - IDS_HDT_CONSOLE (NB_MISC, " SCLK VID[%d] - 0x%02x\n", Index, PpFuseArray->SclkDpmVid[Index]); - } - for (Index = 0; Index < 6; Index++) { - IDS_HDT_CONSOLE (NB_MISC, " State #%d\n", Index); - IDS_HDT_CONSOLE (NB_MISC, " Policy Label - 0x%x\n", PpFuseArray->PolicyLabel[Index]); - IDS_HDT_CONSOLE (NB_MISC, " Policy Flag - 0x%x\n", PpFuseArray->PolicyFlags[Index]); - IDS_HDT_CONSOLE (NB_MISC, " Valid SCLK - 0x%x\n", PpFuseArray->SclkDpmValid[Index]); - IDS_HDT_CONSOLE (NB_MISC, " Vclk/Dclk Index - 0x%x\n", PpFuseArray->VclkDclkSel[Index]); - } - IDS_HDT_CONSOLE (NB_MISC, " GEN2 VID - 0x%x\n", PpFuseArray->PcieGen2Vid); - IDS_HDT_CONSOLE (NB_MISC, " Main PLL Id - 0x%x\n", PpFuseArray->MainPllId); - IDS_HDT_CONSOLE (NB_MISC, " GpuBoostCap - %x\n", PpFuseArray->GpuBoostCap); - IDS_HDT_CONSOLE (NB_MISC, " SclkDpmBoostMargin - %x\n", PpFuseArray->SclkDpmBoostMargin); - IDS_HDT_CONSOLE (NB_MISC, " SclkDpmThrottleMargin - %x\n", PpFuseArray->SclkDpmThrottleMargin); - IDS_HDT_CONSOLE (NB_MISC, " SclkDpmTdpLimitPG - %x\n", PpFuseArray->SclkDpmTdpLimitPG); - IDS_HDT_CONSOLE ( - NB_MISC, " SclkThermDid - %x(%dMHz)\n", - PpFuseArray->SclkThermDid, - (PpFuseArray->SclkThermDid != 0) ? (GfxLibCalculateClk (PpFuseArray->SclkThermDid, EffectiveMainPllFreq10KHz) / 100) : 0 - ); - IDS_HDT_CONSOLE (NB_MISC, "<------------ GNB FUSE END-------------->\n"); -} diff --git a/src/vendorcode/amd/agesa/f12/Proc/GNB/Nb/Feature/NbFuseTable.h b/src/vendorcode/amd/agesa/f12/Proc/GNB/Nb/Feature/NbFuseTable.h deleted file mode 100644 index e1415193a2..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/GNB/Nb/Feature/NbFuseTable.h +++ /dev/null @@ -1,53 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * Fuse table initialization - * - * - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: GNB - * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $ - * - */ -/* -***************************************************************************** -* -* Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* *************************************************************************** -* -*/ -#ifndef _NBFUSETABLE_H_ -#define _NBFUSETABLE_H_ - -AGESA_STATUS -NbFuseTableFeature ( - IN AMD_CONFIG_PARAMS *StdHeader - ); - -#endif diff --git a/src/vendorcode/amd/agesa/f12/Proc/GNB/Nb/Feature/NbLclkDpm.c b/src/vendorcode/amd/agesa/f12/Proc/GNB/Nb/Feature/NbLclkDpm.c deleted file mode 100644 index 541880e806..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/GNB/Nb/Feature/NbLclkDpm.c +++ /dev/null @@ -1,108 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * LCLK DPM initialization - * - * - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: GNB - * @e \$Revision: 48452 $ @e \$Date: 2011-03-09 12:50:44 +0800 (Wed, 09 Mar 2011) $ - * - */ -/* -***************************************************************************** -* -* Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* *************************************************************************** -* -*/ - -/*---------------------------------------------------------------------------------------- - * M O D U L E S U S E D - *---------------------------------------------------------------------------------------- - */ - -#include "AGESA.h" -#include "amdlib.h" -#include "Ids.h" -#include "heapManager.h" -#include "Gnb.h" -#include "GnbFuseTable.h" -#include "GnbCommonLib.h" -#include "GnbRegistersLN.h" -#include "OptionGnb.h" -#include "GfxLib.h" -#include "NbConfigData.h" -#include "NbSmuLib.h" -#include "NbLclkDpm.h" -#include "NbFamilyServices.h" -#include "Filecode.h" - -#define FILECODE PROC_GNB_NB_FEATURE_NBLCLKDPM_FILECODE -/*---------------------------------------------------------------------------------------- - * D E F I N I T I O N S A N D M A C R O S - *---------------------------------------------------------------------------------------- - */ - -extern GNB_BUILD_OPTIONS GnbBuildOptions; -/*---------------------------------------------------------------------------------------- - * T Y P E D E F S A N D S T R U C T U R E S - *---------------------------------------------------------------------------------------- - */ - - -/*---------------------------------------------------------------------------------------- - * P R O T O T Y P E S O F L O C A L F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ - - -/*----------------------------------------------------------------------------------------*/ -/** - * LCLK DPM init - * - * - * - * @param[in] StdHeader Pointer to Standard configuration - * @retval Initialization status - */ - -AGESA_STATUS -NbLclkDpmFeature ( - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - AGESA_STATUS Status; - IDS_HDT_CONSOLE (GNB_TRACE, "NbLclkDpmFeature Enter\n"); - - Status = NbFmInitLclkDpmRcActivity (StdHeader); - - IDS_HDT_CONSOLE (GNB_TRACE, "NbLclkDpmFeature Exit [0x%x]\n", Status); - return Status; -} diff --git a/src/vendorcode/amd/agesa/f12/Proc/GNB/Nb/Feature/NbLclkDpm.h b/src/vendorcode/amd/agesa/f12/Proc/GNB/Nb/Feature/NbLclkDpm.h deleted file mode 100644 index 41c95fb73c..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/GNB/Nb/Feature/NbLclkDpm.h +++ /dev/null @@ -1,54 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * NB Lclk DPM - * - * - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: GNB - * @e \$Revision: 47050 $ @e \$Date: 2011-02-15 05:50:36 +0800 (Tue, 15 Feb 2011) $ - * - */ -/* -***************************************************************************** -* -* Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* *************************************************************************** -* -*/ - -#ifndef _NBLCLKDPM_H_ -#define _NBLCLKDPM_H_ - -AGESA_STATUS -NbLclkDpmFeature ( - IN AMD_CONFIG_PARAMS *StdHeader - ); - -#endif diff --git a/src/vendorcode/amd/agesa/f12/Proc/GNB/Nb/Makefile.inc b/src/vendorcode/amd/agesa/f12/Proc/GNB/Nb/Makefile.inc deleted file mode 100644 index 578c5f857c..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/GNB/Nb/Makefile.inc +++ /dev/null @@ -1,9 +0,0 @@ -libagesa-y += NbConfigData.c -libagesa-y += NbInit.c -libagesa-y += NbInitAtEarly.c -libagesa-y += NbInitAtEnv.c -libagesa-y += NbInitAtLatePost.c -libagesa-y += NbInitAtPost.c -libagesa-y += NbInitAtReset.c -libagesa-y += NbPowerMgmt.c -libagesa-y += NbSmuLib.c diff --git a/src/vendorcode/amd/agesa/f12/Proc/GNB/Nb/NbConfigData.c b/src/vendorcode/amd/agesa/f12/Proc/GNB/Nb/NbConfigData.c deleted file mode 100644 index c24cac7a40..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/GNB/Nb/NbConfigData.c +++ /dev/null @@ -1,94 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * Initialize NB configuration data structure. - * - * - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: GNB - * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $ - * - */ -/* -***************************************************************************** -* -* Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* *************************************************************************** -* -*/ - -/*---------------------------------------------------------------------------------------- - * M O D U L E S U S E D - *---------------------------------------------------------------------------------------- - */ -#include "AGESA.h" -#include "amdlib.h" -#include "Ids.h" -#include "Gnb.h" -#include "NbConfigData.h" -#include "Filecode.h" -#define FILECODE PROC_GNB_NB_NBCONFIGDATA_FILECODE -/*---------------------------------------------------------------------------------------- - * D E F I N I T I O N S A N D M A C R O S - *---------------------------------------------------------------------------------------- - */ - - -/*---------------------------------------------------------------------------------------- - * T Y P E D E F S A N D S T R U C T U R E S - *---------------------------------------------------------------------------------------- - */ - - -/*---------------------------------------------------------------------------------------- - * P R O T O T Y P E S O F L O C A L F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ - -/*----------------------------------------------------------------------------------------*/ -/** - * Create configuration data - * - * - * @param[in] StdHeader Standard configuration header - * @param[in] Gnb Pointer to global Gnb configuration - * @retval AGESA_STATUS - */ - -AGESA_STATUS -NbAllocateConfigData ( - IN AMD_CONFIG_PARAMS *StdHeader, - IN GNB_PLATFORM_CONFIG *Gnb - ) -{ - AGESA_STATUS Status; - Status = AGESA_SUCCESS; - Gnb->StdHeader = StdHeader; - return Status; -} \ No newline at end of file diff --git a/src/vendorcode/amd/agesa/f12/Proc/GNB/Nb/NbConfigData.h b/src/vendorcode/amd/agesa/f12/Proc/GNB/Nb/NbConfigData.h deleted file mode 100644 index 56fce0d805..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/GNB/Nb/NbConfigData.h +++ /dev/null @@ -1,68 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * Initialize NB configuration data structure. - * - * - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: GNB - * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $ - * - */ -/* -***************************************************************************** -* -* Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* *************************************************************************** -* -*/ - -#ifndef _NBCONFIGDATA_H_ -#define _NBCONFIGDATA_H_ - -/// NB register entry -typedef struct { - UINT16 Reg; ///< Register address - UINT32 Mask; ///< Mask - UINT32 Data; ///< Data -} NB_REGISTER_ENTRY; - -/// GNB Platform Configuration -typedef struct { - AMD_CONFIG_PARAMS *StdHeader; ///< Standard configuration header - PCI_ADDR GnbPciAddress; ///< PCI Address -} GNB_PLATFORM_CONFIG; - -AGESA_STATUS -NbAllocateConfigData ( - IN AMD_CONFIG_PARAMS *StdHeader, - IN GNB_PLATFORM_CONFIG *Gnb - ); - -#endif diff --git a/src/vendorcode/amd/agesa/f12/Proc/GNB/Nb/NbInit.c b/src/vendorcode/amd/agesa/f12/Proc/GNB/Nb/NbInit.c deleted file mode 100644 index 0e44ebb196..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/GNB/Nb/NbInit.c +++ /dev/null @@ -1,233 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * Various NB initialization services - * - * - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: GNB - * @e \$Revision: 48952 $ @e \$Date: 2011-03-15 06:45:49 +0800 (Tue, 15 Mar 2011) $ - * - */ -/* -***************************************************************************** -* -* Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* *************************************************************************** -* -*/ - -/*---------------------------------------------------------------------------------------- - * M O D U L E S U S E D - *---------------------------------------------------------------------------------------- - */ -#include "AGESA.h" -#include "amdlib.h" -#include "Ids.h" -#include "Gnb.h" -#include "GnbCommonLib.h" -#include "GnbGfxInitLibV1.h" -#include "NbSmuLib.h" -#include "NbConfigData.h" -#include "GnbRegistersLN.h" -#include "NbInit.h" -#include "Filecode.h" -#define FILECODE PROC_GNB_NB_NBINIT_FILECODE -/*---------------------------------------------------------------------------------------- - * D E F I N I T I O N S A N D M A C R O S - *---------------------------------------------------------------------------------------- - */ - - -/*---------------------------------------------------------------------------------------- - * T Y P E D E F S A N D S T R U C T U R E S - *---------------------------------------------------------------------------------------- - */ - - -/*---------------------------------------------------------------------------------------- - * P R O T O T Y P E S O F L O C A L F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ - -CONST NB_REGISTER_ENTRY NbPciInitTable [] = { - { - D0F0x04_ADDRESS, - 0xffffffff, - (0x1 << D0F0x04_MemAccessEn_WIDTH) | (0x1 << D0F0x04_BusMasterEn_OFFSET) - }, - { - D0F0x4C_ADDRESS, - ~(UINT32)(0x3ull << D0F0x4C_CfgRdTime_OFFSET), - 0x2 << D0F0x4C_CfgRdTime_OFFSET - }, - { - D0F0x84_ADDRESS, - ~(UINT32)(0x1ull << D0F0x84_Ev6Mode_OFFSET), - 0x1 << D0F0x84_Ev6Mode_OFFSET - } -}; - -CONST NB_REGISTER_ENTRY NbMiscInitTable [] = { - { - D0F0x64_x46_ADDRESS, - ~(UINT32)(0x3ull << D0F0x64_x46_P2PMode_OFFSET), - 1 << D0F0x64_x46_Msi64bitEn_OFFSET - } -}; - - -CONST NB_REGISTER_ENTRY NbOrbInitTable [] = { - { - D0F0x98_x07_ADDRESS, - 0xffffffff, - (1 << D0F0x98_x07_IocBwOptEn_OFFSET) | - (1 << D0F0x98_x07_MSIHTIntConversionEn_OFFSET) | - (1 << D0F0x98_x07_DropZeroMaskWrEn_OFFSET) - }, - { - D0F0x98_x08_ADDRESS, - ~(UINT32)(0xffull << D0F0x98_x08_NpWrrLenC_OFFSET), - 1 << D0F0x98_x08_NpWrrLenC_OFFSET - }, - { - D0F0x98_x09_ADDRESS, - ~(UINT32)(0xffull << D0F0x98_x09_PWrrLenD_OFFSET), - 1 << D0F0x98_x09_PWrrLenD_OFFSET - }, - { - D0F0x98_x0C_ADDRESS, - 0xffffffff, - 1 << D0F0x98_x0C_StrictSelWinnerEn_OFFSET - }, - { - D0F0x98_x0E_ADDRESS, - 0xffffffff, - 1 << D0F0x98_x0E_MsiHtRsvIntRemapEn_OFFSET - }, - { - D0F0x98_x28_ADDRESS, - 0xffffffff, - (1 << D0F0x98_x28_SmuPmInterfaceEn_OFFSET) | - (1 << D0F0x98_x28_ForceCoherentIntr_OFFSET) - } -}; - - -/*----------------------------------------------------------------------------------------*/ -/** - * Init NB at Power On - * - * - * - * @param[in] Gnb Pointer to global Gnb configuration - * @retval AGESA_STATUS - */ - - -AGESA_STATUS -NbInitOnPowerOn ( - IN GNB_PLATFORM_CONFIG *Gnb - ) -{ - UINTN Index; - FCRxFF30_0398_STRUCT FCRxFF30_0398; - UINT32 Value; - - // Init NBCONFIG - for (Index = 0; Index < (sizeof (NbPciInitTable) / sizeof (NB_REGISTER_ENTRY)); Index++) { - GnbLibPciRMW ( - Gnb->GnbPciAddress.AddressValue | NbPciInitTable[Index].Reg, - AccessWidth32, - NbPciInitTable[Index].Mask, - NbPciInitTable[Index].Data, - Gnb->StdHeader - ); - } - - // Init MISCIND - for (Index = 0; Index < (sizeof (NbMiscInitTable) / sizeof (NB_REGISTER_ENTRY)); Index++) { - GnbLibPciIndirectRMW ( - Gnb->GnbPciAddress.AddressValue | D0F0x60_ADDRESS, - NbMiscInitTable[Index].Reg | IOC_WRITE_ENABLE, - AccessWidth32, - NbMiscInitTable[Index].Mask, - NbMiscInitTable[Index].Data, - Gnb->StdHeader - ); - } - - // Init ORB - for (Index = 0; Index < (sizeof (NbOrbInitTable) / sizeof (NB_REGISTER_ENTRY)); Index++) { - GnbLibPciIndirectRMW ( - Gnb->GnbPciAddress.AddressValue | D0F0x94_ADDRESS, - NbOrbInitTable[Index].Reg | (1 << D0F0x94_OrbIndWrEn_OFFSET), - AccessWidth32, - NbOrbInitTable[Index].Mask, - NbOrbInitTable[Index].Data, - Gnb->StdHeader - ); - } - if (!GfxLibIsControllerPresent (Gnb->StdHeader)) { - FCRxFF30_0398.Value = (1 << FCRxFF30_0398_SoftResetGrbm_OFFSET) | (1 << FCRxFF30_0398_SoftResetMc_OFFSET) | - (1 << FCRxFF30_0398_SoftResetDc_OFFSET) | (1 << FCRxFF30_0398_SoftResetRlc_OFFSET) | - (1 << FCRxFF30_0398_SoftResetUvd_OFFSET); - NbSmuSrbmRegisterWrite (FCRxFF30_0398_ADDRESS, &FCRxFF30_0398.Value, FALSE, Gnb->StdHeader); - } - - Value = 0; - for (Index = 0x8400; Index <= 0x85AC; Index = Index + 4) { - NbSmuRcuRegisterWrite ( - (UINT16) Index, - &Value, - 1, - FALSE, - Gnb->StdHeader - ); - } - - NbSmuRcuRegisterWrite ( - 0x9000, - &Value, - 1, - FALSE, - Gnb->StdHeader - ); - - NbSmuRcuRegisterWrite ( - 0x9004, - &Value, - 1, - FALSE, - Gnb->StdHeader - ); - - return AGESA_SUCCESS; -} - diff --git a/src/vendorcode/amd/agesa/f12/Proc/GNB/Nb/NbInit.h b/src/vendorcode/amd/agesa/f12/Proc/GNB/Nb/NbInit.h deleted file mode 100644 index 5f5504b956..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/GNB/Nb/NbInit.h +++ /dev/null @@ -1,54 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * Various NB initialization services - * - * - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: GNB - * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $ - * - */ -/* -***************************************************************************** -* -* Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* *************************************************************************** -* -*/ - -#ifndef _NBINIT_H_ -#define _NBINIT_H_ - -AGESA_STATUS -NbInitOnPowerOn ( - IN GNB_PLATFORM_CONFIG *Gnb - ); - -#endif diff --git a/src/vendorcode/amd/agesa/f12/Proc/GNB/Nb/NbInitAtEarly.c b/src/vendorcode/amd/agesa/f12/Proc/GNB/Nb/NbInitAtEarly.c deleted file mode 100644 index 4b997c451b..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/GNB/Nb/NbInitAtEarly.c +++ /dev/null @@ -1,122 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * NB early initialization interface - * - * - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: GNB - * @e \$Revision: 48452 $ @e \$Date: 2011-03-09 12:50:44 +0800 (Wed, 09 Mar 2011) $ - * - */ -/* -***************************************************************************** -* -* Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* *************************************************************************** -* -*/ - -/*---------------------------------------------------------------------------------------- - * M O D U L E S U S E D - *---------------------------------------------------------------------------------------- - */ -#include "AGESA.h" -#include "amdlib.h" -#include "Ids.h" -#include "Gnb.h" -#include "GnbCommonLib.h" -#include "GnbNbInitLibV1.h" -#include "NbConfigData.h" -#include "NbInit.h" -#include "NbInitAtEarly.h" -#include "Filecode.h" -#define FILECODE PROC_GNB_NB_NBINITATEARLY_FILECODE -/*---------------------------------------------------------------------------------------- - * D E F I N I T I O N S A N D M A C R O S - *---------------------------------------------------------------------------------------- - */ - - -/*---------------------------------------------------------------------------------------- - * T Y P E D E F S A N D S T R U C T U R E S - *---------------------------------------------------------------------------------------- - */ - - -/*---------------------------------------------------------------------------------------- - * P R O T O T Y P E S O F L O C A L F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ - - - -/*----------------------------------------------------------------------------------------*/ -/** - * Init GNB at Reset - * - * - * - * @param[in] StdHeader Standard configuration header - * @retval AGESA_STATUS - */ - -AGESA_STATUS -NbInitAtEarly ( - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - AGESA_STATUS Status; - AGESA_STATUS AgesaStatus; - GNB_PLATFORM_CONFIG Gnb; - UINT32 NumberOfSockets; - UINT32 SocketId; - AgesaStatus = AGESA_SUCCESS; - IDS_HDT_CONSOLE (GNB_TRACE, "NbInitAtEarly Enter\n"); - NbAllocateConfigData (StdHeader, &Gnb); - NumberOfSockets = GnbGetNumberOfSockets (StdHeader); - for (SocketId = 0; SocketId < NumberOfSockets; SocketId++) { - UINT32 NumberOfSilicons; - UINT32 SiliconId; - if (!GnbIsDevicePresentInSocket (SocketId, StdHeader)) { - continue; - } - NumberOfSilicons = GnbGetNumberOfSiliconsOnSocket (SocketId, StdHeader); - for (SiliconId = 0; SiliconId < NumberOfSilicons; SiliconId++) { - Gnb.GnbPciAddress = GnbGetPciAddress (SocketId, SiliconId, StdHeader); - Status = NbInitOnPowerOn (&Gnb); - AGESA_STATUS_UPDATE (Status, AgesaStatus); - ASSERT (Status == AGESA_SUCCESS); - } - } - IDS_HDT_CONSOLE (GNB_TRACE, "NbInitAtEarly Exit[0x%x]\n", AgesaStatus); - return AgesaStatus; -} - - diff --git a/src/vendorcode/amd/agesa/f12/Proc/GNB/Nb/NbInitAtEarly.h b/src/vendorcode/amd/agesa/f12/Proc/GNB/Nb/NbInitAtEarly.h deleted file mode 100644 index 9cd9dd9c00..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/GNB/Nb/NbInitAtEarly.h +++ /dev/null @@ -1,53 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * NB early initialization interface - * - * - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: - * @e sub-project: - * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $ - * - */ -/* -***************************************************************************** -* -* Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* *************************************************************************** -* -*/ -#ifndef _NBINITATRESET_H_ -#define _NBINITATRESET_H_ - -AGESA_STATUS -NbInitAtEarly ( - IN AMD_CONFIG_PARAMS *StdHeader - ); - -#endif diff --git a/src/vendorcode/amd/agesa/f12/Proc/GNB/Nb/NbInitAtEnv.c b/src/vendorcode/amd/agesa/f12/Proc/GNB/Nb/NbInitAtEnv.c deleted file mode 100644 index 55784698d8..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/GNB/Nb/NbInitAtEnv.c +++ /dev/null @@ -1,123 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * NB init at ENV interface - * - * - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: GNB - * @e \$Revision: 48452 $ @e \$Date: 2011-03-09 12:50:44 +0800 (Wed, 09 Mar 2011) $ - * - */ -/* -***************************************************************************** -* -* Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* *************************************************************************** -* -*/ - - -/*---------------------------------------------------------------------------------------- - * M O D U L E S U S E D - *---------------------------------------------------------------------------------------- - */ -#include "AGESA.h" -#include "amdlib.h" -#include "Ids.h" -#include "Gnb.h" -#include "GnbFuseTable.h" -#include "GnbCommonLib.h" -#include "GnbNbInitLibV1.h" -#include "NbConfigData.h" -#include "NbFamilyServices.h" -#include "NbInitAtEnv.h" -#include "Filecode.h" -#define FILECODE PROC_GNB_NB_NBINITATENV_FILECODE -/*---------------------------------------------------------------------------------------- - * D E F I N I T I O N S A N D M A C R O S - *---------------------------------------------------------------------------------------- - */ - - -/*---------------------------------------------------------------------------------------- - * T Y P E D E F S A N D S T R U C T U R E S - *---------------------------------------------------------------------------------------- - */ - - -/*---------------------------------------------------------------------------------------- - * P R O T O T Y P E S O F L O C A L F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ - -/*----------------------------------------------------------------------------------------*/ -/** - * Init GNB at ENV - * - * - * - * @param[in] StdHeader Standard configuration header - * @retval AGESA_STATUS - */ - -AGESA_STATUS -NbInitAtEnv ( - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - AGESA_STATUS Status; - AGESA_STATUS AgesaStatus; - GNB_PLATFORM_CONFIG Gnb; - UINT32 NumberOfSockets; - UINT32 SocketId; - AgesaStatus = AGESA_SUCCESS; - IDS_HDT_CONSOLE (GNB_TRACE, "NbInitAtEnv Enter\n"); - NbAllocateConfigData (StdHeader, &Gnb); - NumberOfSockets = GnbGetNumberOfSockets (StdHeader); - for (SocketId = 0; SocketId < NumberOfSockets; SocketId++) { - UINT32 NumberOfSilicons; - UINT32 SiliconId; - if (!GnbIsDevicePresentInSocket (SocketId, StdHeader)) { - continue; - } - NumberOfSilicons = GnbGetNumberOfSiliconsOnSocket (SocketId, StdHeader); - for (SiliconId = 0; SiliconId < NumberOfSilicons; SiliconId++) { - Gnb.GnbPciAddress = GnbGetPciAddress (SocketId, SiliconId, StdHeader); - GnbLpcDmaDeadlockPrevention (Gnb.GnbPciAddress, StdHeader); - Status = GnbSetTom (Gnb.GnbPciAddress, StdHeader); - AGESA_STATUS_UPDATE (Status, AgesaStatus); - ASSERT (Status == AGESA_SUCCESS); - NbFmClumpUnitID (Gnb.GnbPciAddress, StdHeader); - GnbOrbDynamicWake (Gnb.GnbPciAddress, StdHeader); - } - } - IDS_HDT_CONSOLE (GNB_TRACE, "NbInitAtEnv Exit[0x%x]\n", AgesaStatus); - return AgesaStatus; -} diff --git a/src/vendorcode/amd/agesa/f12/Proc/GNB/Nb/NbInitAtEnv.h b/src/vendorcode/amd/agesa/f12/Proc/GNB/Nb/NbInitAtEnv.h deleted file mode 100644 index 9e6bb70017..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/GNB/Nb/NbInitAtEnv.h +++ /dev/null @@ -1,57 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * NB post init interface - * - * - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: GNB - * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $ - * - */ -/* -***************************************************************************** -* -* Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* *************************************************************************** -* -*/ - -#ifndef _NBINITATENV_H_ -#define _NBINITATENV_H_ - -AGESA_STATUS -NbInitAtEnv ( - IN AMD_CONFIG_PARAMS *StdHeader - ); - -#endif - - - diff --git a/src/vendorcode/amd/agesa/f12/Proc/GNB/Nb/NbInitAtLatePost.c b/src/vendorcode/amd/agesa/f12/Proc/GNB/Nb/NbInitAtLatePost.c deleted file mode 100644 index 27135cd608..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/GNB/Nb/NbInitAtLatePost.c +++ /dev/null @@ -1,121 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * NB late POST init interface - * - * - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: - * @e sub-project: - * @e \$Revision: 48452 $ @e \$Date: 2011-03-09 12:50:44 +0800 (Wed, 09 Mar 2011) $ - * - */ -/* -***************************************************************************** -* -* Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* *************************************************************************** -* -*/ - - -/*---------------------------------------------------------------------------------------- - * M O D U L E S U S E D - *---------------------------------------------------------------------------------------- - */ -#include "AGESA.h" -#include "amdlib.h" -#include "Ids.h" -#include "Gnb.h" -#include "GnbCommonLib.h" -#include "GnbNbInitLibV1.h" -#include "NbConfigData.h" -#include "NbPowerMgmt.h" -#include "NbInitAtLatePost.h" -#include "Filecode.h" - -#define FILECODE PROC_GNB_NB_NBINITATLATEPOST_FILECODE -/*---------------------------------------------------------------------------------------- - * D E F I N I T I O N S A N D M A C R O S - *---------------------------------------------------------------------------------------- - */ - - -/*---------------------------------------------------------------------------------------- - * T Y P E D E F S A N D S T R U C T U R E S - *---------------------------------------------------------------------------------------- - */ - - -/*---------------------------------------------------------------------------------------- - * P R O T O T Y P E S O F L O C A L F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ - -/*----------------------------------------------------------------------------------------*/ -/** - * Init GNB at Late Post - * - * - * - * @param[in] StdHeader Standard configuration header - * @retval AGESA_STATUS - */ - -AGESA_STATUS -NbInitAtLatePost ( - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - AGESA_STATUS Status; - AGESA_STATUS AgesaStatus; - GNB_PLATFORM_CONFIG Gnb; - UINT32 NumberOfSockets; - UINT32 SocketId; - AgesaStatus = AGESA_SUCCESS; - IDS_HDT_CONSOLE (GNB_TRACE, "NbInitAtLatePost Enter\n"); - Status = NbAllocateConfigData (StdHeader, &Gnb); - AGESA_STATUS_UPDATE (Status, AgesaStatus); - NumberOfSockets = GnbGetNumberOfSockets (StdHeader); - for (SocketId = 0; SocketId < NumberOfSockets; SocketId++) { - UINT32 NumberOfSilicons; - UINT32 SiliconId; - if (!GnbIsDevicePresentInSocket (SocketId, StdHeader)) { - continue; - } - NumberOfSilicons = GnbGetNumberOfSiliconsOnSocket (SocketId, StdHeader); - for (SiliconId = 0; SiliconId < NumberOfSilicons; SiliconId++) { - Gnb.GnbPciAddress = GnbGetPciAddress (SocketId, SiliconId, StdHeader); - Status = NbInitPowerManagement (&Gnb); - AGESA_STATUS_UPDATE (Status, AgesaStatus); - GnbLock (Gnb.GnbPciAddress, StdHeader); - } - } - IDS_HDT_CONSOLE (GNB_TRACE, "NbInitAtLatePost Exit[0x%x]\n", Status); - return Status; -} diff --git a/src/vendorcode/amd/agesa/f12/Proc/GNB/Nb/NbInitAtLatePost.h b/src/vendorcode/amd/agesa/f12/Proc/GNB/Nb/NbInitAtLatePost.h deleted file mode 100644 index fde262ff9c..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/GNB/Nb/NbInitAtLatePost.h +++ /dev/null @@ -1,55 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * NB late POST init interface - * - * - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: - * @e sub-project: - * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $ - * - */ -/* -***************************************************************************** -* -* Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* *************************************************************************** -* -*/ - -#ifndef _NBINITATLATEPOST_H_ -#define _NBINITATLATEPOST_H_ - -AGESA_STATUS -NbInitAtLatePost ( - IN AMD_CONFIG_PARAMS *StdHeader - ); - -#endif - diff --git a/src/vendorcode/amd/agesa/f12/Proc/GNB/Nb/NbInitAtPost.c b/src/vendorcode/amd/agesa/f12/Proc/GNB/Nb/NbInitAtPost.c deleted file mode 100644 index aee9193a38..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/GNB/Nb/NbInitAtPost.c +++ /dev/null @@ -1,121 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * NB Post initialization interface - * - * - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: GNB - * @e \$Revision: 34897 $ @e \$Date: 2010-07-14 10:07:10 +0800 (Wed, 14 Jul 2010) $ - * - */ -/* -***************************************************************************** -* -* Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* *************************************************************************** -* -*/ - -/*---------------------------------------------------------------------------------------- - * M O D U L E S U S E D - *---------------------------------------------------------------------------------------- - */ -#include "AGESA.h" -#include "amdlib.h" -#include "Ids.h" -#include "Gnb.h" -#include "GnbCommonLib.h" -#include "GnbNbInitLibV1.h" -#include "NbConfigData.h" -#include "NbInitAtPost.h" -#include "Filecode.h" -#define FILECODE PROC_GNB_NB_NBINITATPOST_FILECODE -/*---------------------------------------------------------------------------------------- - * D E F I N I T I O N S A N D M A C R O S - *---------------------------------------------------------------------------------------- - */ - - -/*---------------------------------------------------------------------------------------- - * T Y P E D E F S A N D S T R U C T U R E S - *---------------------------------------------------------------------------------------- - */ - - -/*---------------------------------------------------------------------------------------- - * P R O T O T Y P E S O F L O C A L F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ - - - -/*----------------------------------------------------------------------------------------*/ -/** - * Init NB at POST - * - * - * - * @param[in] StdHeader Standard configuration header - * @retval AGESA_STATUS - */ - -AGESA_STATUS -NbInitAtPost ( - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - AGESA_STATUS Status; - AGESA_STATUS AgesaStatus; - GNB_PLATFORM_CONFIG Gnb; - UINT32 NumberOfSockets; - UINT32 SocketId; - AgesaStatus = AGESA_SUCCESS; - IDS_HDT_CONSOLE (GNB_TRACE, "NbInitAtPost Enter\n"); - NbAllocateConfigData (StdHeader, &Gnb); - NumberOfSockets = GnbGetNumberOfSockets (StdHeader); - for (SocketId = 0; SocketId < NumberOfSockets; SocketId++) { - UINT32 NumberOfSilicons; - UINT32 SiliconId; - if (!GnbIsDevicePresentInSocket (SocketId, StdHeader)) { - continue; - } - NumberOfSilicons = GnbGetNumberOfSiliconsOnSocket (SocketId, StdHeader); - for (SiliconId = 0; SiliconId < NumberOfSilicons; SiliconId++) { - Gnb.GnbPciAddress = GnbGetPciAddress (SocketId, SiliconId, StdHeader); - Status = GnbSetTom (Gnb.GnbPciAddress, StdHeader); - AGESA_STATUS_UPDATE (Status, AgesaStatus); - ASSERT (Status == AGESA_SUCCESS); - } - } - IDS_HDT_CONSOLE (GNB_TRACE, "NbInitAtPost Exit[0x%x]\n", AgesaStatus); - return AgesaStatus; -} - - diff --git a/src/vendorcode/amd/agesa/f12/Proc/GNB/Nb/NbInitAtPost.h b/src/vendorcode/amd/agesa/f12/Proc/GNB/Nb/NbInitAtPost.h deleted file mode 100644 index 76ce8e0399..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/GNB/Nb/NbInitAtPost.h +++ /dev/null @@ -1,53 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * NB Post initialization interface - * - * - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: - * @e sub-project: - * @e \$Revision: 34897 $ @e \$Date: 2010-07-14 10:07:10 +0800 (Wed, 14 Jul 2010) $ - * - */ -/* -***************************************************************************** -* -* Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* *************************************************************************** -* -*/ -#ifndef _NBINITATPOST_H_ -#define _NBINITATPOST_H_ - -AGESA_STATUS -NbInitAtPost ( - IN AMD_CONFIG_PARAMS *StdHeader - ); - -#endif diff --git a/src/vendorcode/amd/agesa/f12/Proc/GNB/Nb/NbInitAtReset.c b/src/vendorcode/amd/agesa/f12/Proc/GNB/Nb/NbInitAtReset.c deleted file mode 100644 index 84f12d7141..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/GNB/Nb/NbInitAtReset.c +++ /dev/null @@ -1,95 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * NB reset init interface - * - * - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: GNB - * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $ - * - */ -/* -***************************************************************************** -* -* Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* *************************************************************************** -* -*/ - -/*---------------------------------------------------------------------------------------- - * M O D U L E S U S E D - *---------------------------------------------------------------------------------------- - */ -#include "AGESA.h" -#include "amdlib.h" -#include "Ids.h" -#include "Gnb.h" -#include "NbInitAtReset.h" -#include "Filecode.h" -#define FILECODE PROC_GNB_NB_NBINITATRESET_FILECODE - -/*---------------------------------------------------------------------------------------- - * D E F I N I T I O N S A N D M A C R O S - *---------------------------------------------------------------------------------------- - */ - - -/*---------------------------------------------------------------------------------------- - * T Y P E D E F S A N D S T R U C T U R E S - *---------------------------------------------------------------------------------------- - */ - - -/*---------------------------------------------------------------------------------------- - * P R O T O T Y P E S O F L O C A L F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ - - - -/*----------------------------------------------------------------------------------------*/ -/** - * Init GNB at Reset - * - * - * - * @param[in] StdHeader Standard configuration header - * @retval AGESA_STATUS - */ - -AGESA_STATUS -NbInitAtReset ( - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - AGESA_STATUS Status; - Status = AGESA_SUCCESS; - return Status; -} \ No newline at end of file diff --git a/src/vendorcode/amd/agesa/f12/Proc/GNB/Nb/NbInitAtReset.h b/src/vendorcode/amd/agesa/f12/Proc/GNB/Nb/NbInitAtReset.h deleted file mode 100644 index d05ff351fd..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/GNB/Nb/NbInitAtReset.h +++ /dev/null @@ -1,53 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * NB reset init interface - * - * - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: - * @e sub-project: - * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $ - * - */ -/* -***************************************************************************** -* -* Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* *************************************************************************** -* -*/ -#ifndef _NBINITATRESET_H_ -#define _NBINITATRESET_H_ - -AGESA_STATUS -NbInitAtReset ( - IN AMD_CONFIG_PARAMS *StdHeader - ); - -#endif diff --git a/src/vendorcode/amd/agesa/f12/Proc/GNB/Nb/NbPowerMgmt.c b/src/vendorcode/amd/agesa/f12/Proc/GNB/Nb/NbPowerMgmt.c deleted file mode 100644 index 2afca26015..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/GNB/Nb/NbPowerMgmt.c +++ /dev/null @@ -1,647 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * NB power management features - * - * - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: GNB - * @e \$Revision: 48978 $ @e \$Date: 2011-03-15 13:53:53 +0800 (Tue, 15 Mar 2011) $ - * - */ -/* -***************************************************************************** -* -* Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* *************************************************************************** -* -*/ - -/*---------------------------------------------------------------------------------------- - * M O D U L E S U S E D - *---------------------------------------------------------------------------------------- - */ -#include "AGESA.h" -#include "amdlib.h" -#include "Ids.h" -#include "Gnb.h" -#include "GnbFuseTable.h" -#include "GnbGfx.h" -#include "GnbPcie.h" -#include "GnbCommonLib.h" -#include "GnbGfxInitLibV1.h" -#include "NbConfigData.h" -#include "NbSmuLib.h" -#include "NbFamilyServices.h" -#include "NbPowerMgmt.h" -#include "OptionGnb.h" -#include "GfxLib.h" -#include "GnbRegistersLN.h" -#include "Filecode.h" -#define FILECODE PROC_GNB_NB_NBPOWERMGMT_FILECODE -/*---------------------------------------------------------------------------------------- - * D E F I N I T I O N S A N D M A C R O S - *---------------------------------------------------------------------------------------- - */ -extern GNB_BUILD_OPTIONS GnbBuildOptions; - -/*---------------------------------------------------------------------------------------- - * T Y P E D E F S A N D S T R U C T U R E S - *---------------------------------------------------------------------------------------- - */ - - -/*---------------------------------------------------------------------------------------- - * P R O T O T Y P E S O F L O C A L F U N C T I O N S - *---------------------------------------------------------------------------------------- -*/ - -VOID -NbInitLclkDeepSleep ( - IN GNB_PLATFORM_CONFIG *Gnb - ); - -VOID -NbInitClockGating ( - IN GNB_PLATFORM_CONFIG *Gnb - ); - -VOID -NbInitSmuClockGating ( - IN NB_CLK_GATING_CTRL *NbClkGatingCtrl, - IN GNB_PLATFORM_CONFIG *Gnb - ); - -VOID -NbInitOrbClockGating ( - IN NB_CLK_GATING_CTRL *NbClkGatingCtrl, - IN GNB_PLATFORM_CONFIG *Gnb - ); - -VOID -NbInitIocClockGating ( - IN NB_CLK_GATING_CTRL *NbClkGatingCtrl, - IN GNB_PLATFORM_CONFIG *Gnb - ); - -VOID -NbInitBifClockGating ( - IN NB_CLK_GATING_CTRL *NbClkGatingCtrl, - IN GNB_PLATFORM_CONFIG *Gnb - ); - -VOID -NbInitGmcClockGating ( - IN NB_CLK_GATING_CTRL *NbClkGatingCtrl, - IN GNB_PLATFORM_CONFIG *Gnb - ); - -VOID -NbInitDceSclkClockGating ( - IN NB_CLK_GATING_CTRL *NbClkGatingCtrl, - IN GNB_PLATFORM_CONFIG *Gnb - ); - -VOID -NbInitDceDisplayClockGating ( - IN NB_CLK_GATING_CTRL *NbClkGatingCtrl, - IN GNB_PLATFORM_CONFIG *Gnb - ); - -/*----------------------------------------------------------------------------------------*/ -/** - * Init various power management features - * - * - * - * @param[in] Gnb Pointer to global Gnb configuration - * @retval AGESA_SUCCESS LCLK DPM initialization success - * @retval AGESA_ERROR LCLK DPM initialization error - */ - -AGESA_STATUS -NbInitPowerManagement ( - IN GNB_PLATFORM_CONFIG *Gnb - ) -{ - AGESA_STATUS Status; - Status = AGESA_SUCCESS; - NbInitLclkDeepSleep (Gnb); - NbInitClockGating (Gnb); - return Status; -} - - -/*----------------------------------------------------------------------------------------*/ -/** - * Init NB LCLK Deep Sleep - * - * - * - * @param[in] Gnb Pointer to global Gnb configuration - */ - -VOID -NbInitLclkDeepSleep ( - IN GNB_PLATFORM_CONFIG *Gnb - ) -{ - SMUx1B_STRUCT SMUx1B; - SMUx1D_STRUCT SMUx1D; - UINT32 LclkDpSlpEn; - IDS_HDT_CONSOLE (GNB_TRACE, "NbInitLclkDeepSleep Enter\n"); - LclkDpSlpEn = GnbBuildOptions.LclkDeepSleepEn ? 1 : 0; - NbSmuIndirectRead (SMUx1B_ADDRESS, AccessWidth16, &SMUx1B.Value, Gnb->StdHeader); - NbSmuIndirectRead (SMUx1D_ADDRESS, AccessWidth16, &SMUx1D.Value, Gnb->StdHeader); - SMUx1B.Field.LclkDpSlpDiv = 5; - SMUx1B.Field.LclkDpSlpMask = (GfxLibIsControllerPresent (Gnb->StdHeader) ? (0xFF) : 0xEF); - SMUx1B.Field.RampDis = 0; - SMUx1D.Field.LclkDpSlpHyst = 0xf; - SMUx1D.Field.LclkDpSlpEn = LclkDpSlpEn; - IDS_HDT_CONSOLE (GNB_TRACE, " LCLK Deep Sleep [%s]\n", (LclkDpSlpEn != 0) ? "Enabled" : "Disabled"); - NbSmuIndirectWrite (SMUx1B_ADDRESS, AccessS3SaveWidth16, &SMUx1B.Value, Gnb->StdHeader); - NbSmuIndirectWrite (SMUx1D_ADDRESS, AccessS3SaveWidth16, &SMUx1D.Value, Gnb->StdHeader); - IDS_HDT_CONSOLE (GNB_TRACE, "NbInitLclkDeepSleep Exit\n"); -} - -/** - * Init NB SMU clock gating - * - * - * - * @param[in] NbClkGatingCtrl Pointer to Clock gating control structure - * @param[in] Gnb Pointer to global Gnb configuration - */ - -VOID -NbInitSmuClockGating ( - IN NB_CLK_GATING_CTRL *NbClkGatingCtrl, - IN GNB_PLATFORM_CONFIG *Gnb - ) -{ - BOOLEAN Smu_Lclk_Gating; - BOOLEAN Smu_Sclk_Gating; - SMUx73_STRUCT SMUx73; - UINT32 Value; - - Smu_Lclk_Gating = NbClkGatingCtrl->Smu_Lclk_Gating; - Smu_Sclk_Gating = NbClkGatingCtrl->Smu_Sclk_Gating; -//SMUx6F - Value = 0x006001F0; - NbSmuIndirectWrite (SMUx6F_ADDRESS, AccessS3SaveWidth32, &Value, Gnb->StdHeader); -//SMUx71 - Value = 0x007001F0; - NbSmuIndirectWrite (SMUx71_ADDRESS, AccessS3SaveWidth32, &Value, Gnb->StdHeader); -//SMUx73 - NbSmuIndirectRead (SMUx73_ADDRESS, AccessWidth16, &SMUx73.Value, Gnb->StdHeader); - SMUx73.Field.DisLclkGating = Smu_Lclk_Gating ? 0 : 1; - SMUx73.Field.DisSclkGating = Smu_Sclk_Gating ? 0 : 1; - NbSmuIndirectWrite (SMUx73_ADDRESS, AccessS3SaveWidth16, &SMUx73.Value, Gnb->StdHeader); - -} - -/** - * Init NB ORB clock gating - * - * - * - * @param[in] NbClkGatingCtrl Pointer to Clock gating control structure - * @param[in] Gnb Pointer to global Gnb configuration - */ - -VOID -NbInitOrbClockGating ( - IN NB_CLK_GATING_CTRL *NbClkGatingCtrl, - IN GNB_PLATFORM_CONFIG *Gnb - ) -{ - BOOLEAN Orb_Sclk_Gating; - BOOLEAN Orb_Lclk_Gating; - D0F0x98_x49_STRUCT D0F0x98_x49; - D0F0x98_x4A_STRUCT D0F0x98_x4A; - D0F0x98_x4B_STRUCT D0F0x98_x4B; - FCRxFF30_01F5_STRUCT FCRxFF30_01F5; - - Orb_Sclk_Gating = NbClkGatingCtrl->Orb_Sclk_Gating; - Orb_Lclk_Gating = NbClkGatingCtrl->Orb_Lclk_Gating; - - // ORB clock gating (Lclk) -//D0F0x98_x4[A:9] - GnbLibPciIndirectRead ( - Gnb->GnbPciAddress.AddressValue | D0F0x94_ADDRESS, - D0F0x98_x49_ADDRESS, - AccessWidth32, - &D0F0x98_x49.Value, - Gnb->StdHeader - ); - - D0F0x98_x49.Field.SoftOverrideClk6 = Orb_Lclk_Gating ? 0 : 1; - D0F0x98_x49.Field.SoftOverrideClk5 = Orb_Lclk_Gating ? 0 : 1; - D0F0x98_x49.Field.SoftOverrideClk4 = Orb_Lclk_Gating ? 0 : 1; - D0F0x98_x49.Field.SoftOverrideClk3 = Orb_Lclk_Gating ? 0 : 1; - D0F0x98_x49.Field.SoftOverrideClk2 = Orb_Lclk_Gating ? 0 : 1; - D0F0x98_x49.Field.SoftOverrideClk1 = Orb_Lclk_Gating ? 0 : 1; - D0F0x98_x49.Field.SoftOverrideClk0 = Orb_Lclk_Gating ? 0 : 1; - - GnbLibPciIndirectWrite ( - Gnb->GnbPciAddress.AddressValue | D0F0x94_ADDRESS, - D0F0x98_x49_ADDRESS | (1 << D0F0x94_OrbIndWrEn_OFFSET), - AccessS3SaveWidth32, - &D0F0x98_x49.Value, - Gnb->StdHeader - ); - - GnbLibPciIndirectRead ( - Gnb->GnbPciAddress.AddressValue | D0F0x94_ADDRESS, - D0F0x98_x4A_ADDRESS | (1 << D0F0x94_OrbIndWrEn_OFFSET), - AccessWidth32, - &D0F0x98_x4A.Value, - Gnb->StdHeader - ); - - D0F0x98_x4A.Field.SoftOverrideClk6 = Orb_Lclk_Gating ? 0 : 1; - D0F0x98_x4A.Field.SoftOverrideClk5 = Orb_Lclk_Gating ? 0 : 1; - D0F0x98_x4A.Field.SoftOverrideClk4 = Orb_Lclk_Gating ? 0 : 1; - D0F0x98_x4A.Field.SoftOverrideClk3 = Orb_Lclk_Gating ? 0 : 1; - D0F0x98_x4A.Field.SoftOverrideClk2 = Orb_Lclk_Gating ? 0 : 1; - D0F0x98_x4A.Field.SoftOverrideClk1 = Orb_Lclk_Gating ? 0 : 1; - D0F0x98_x4A.Field.SoftOverrideClk0 = Orb_Lclk_Gating ? 0 : 1; - - - GnbLibPciIndirectWrite ( - Gnb->GnbPciAddress.AddressValue | D0F0x94_ADDRESS, - D0F0x98_x4A_ADDRESS | (1 << D0F0x94_OrbIndWrEn_OFFSET), - AccessS3SaveWidth32, - &D0F0x98_x4A.Value, - Gnb->StdHeader - ); - -//D0F0x98_x4B - GnbLibPciIndirectRead ( - Gnb->GnbPciAddress.AddressValue | D0F0x94_ADDRESS, - D0F0x98_x4B_ADDRESS | (1 << D0F0x94_OrbIndWrEn_OFFSET), - AccessWidth32, - &D0F0x98_x4B.Value, - Gnb->StdHeader - ); - - D0F0x98_x4B.Field.SoftOverrideClk = Orb_Sclk_Gating ? 0 : 1; - - GnbLibPciIndirectWrite ( - Gnb->GnbPciAddress.AddressValue | D0F0x94_ADDRESS, - D0F0x98_x4B_ADDRESS | (1 << D0F0x94_OrbIndWrEn_OFFSET), - AccessS3SaveWidth32, - &D0F0x98_x4B.Value, - Gnb->StdHeader - ); - -//FCRxFF30_01F5[CgOrbCgttLclkOverride, CgOrbCgttSclkOverride] - NbSmuSrbmRegisterRead (FCRxFF30_01F5_ADDRESS, &FCRxFF30_01F5.Value, Gnb->StdHeader); - FCRxFF30_01F5.Field.CgOrbCgttLclkOverride = 0; - FCRxFF30_01F5.Field.CgOrbCgttSclkOverride = 0; - NbSmuSrbmRegisterWrite (FCRxFF30_01F5_ADDRESS, &FCRxFF30_01F5.Value, TRUE, Gnb->StdHeader); - -} - -/** - * Init NB IOC clock gating - * - * - * - * @param[in] NbClkGatingCtrl Pointer to Clock gating control structure - * @param[in] Gnb Pointer to global Gnb configuration - */ - -VOID -NbInitIocClockGating ( - IN NB_CLK_GATING_CTRL *NbClkGatingCtrl, - IN GNB_PLATFORM_CONFIG *Gnb - ) -{ - BOOLEAN Ioc_Lclk_Gating; - BOOLEAN Ioc_Sclk_Gating; - D0F0x64_x22_STRUCT D0F0x64_x22; - D0F0x64_x23_STRUCT D0F0x64_x23; - D0F0x64_x24_STRUCT D0F0x64_x24; - FCRxFF30_01F5_STRUCT FCRxFF30_01F5; - - Ioc_Lclk_Gating = NbClkGatingCtrl->Ioc_Lclk_Gating; - Ioc_Sclk_Gating = NbClkGatingCtrl->Ioc_Sclk_Gating; - -//D0F0x64_x22 - GnbLibPciIndirectRead ( - Gnb->GnbPciAddress.AddressValue | D0F0x60_ADDRESS, - D0F0x64_x22_ADDRESS | IOC_WRITE_ENABLE, - AccessWidth32, - &D0F0x64_x22.Value, - Gnb->StdHeader - ); - - D0F0x64_x22.Field.SoftOverrideClk4 = Ioc_Lclk_Gating ? 0 : 1; - D0F0x64_x22.Field.SoftOverrideClk3 = Ioc_Lclk_Gating ? 0 : 1; - D0F0x64_x22.Field.SoftOverrideClk2 = Ioc_Lclk_Gating ? 0 : 1; - D0F0x64_x22.Field.SoftOverrideClk1 = Ioc_Lclk_Gating ? 0 : 1; - D0F0x64_x22.Field.SoftOverrideClk0 = Ioc_Lclk_Gating ? 0 : 1; - - GnbLibPciIndirectWrite ( - Gnb->GnbPciAddress.AddressValue | D0F0x60_ADDRESS, - D0F0x64_x22_ADDRESS | IOC_WRITE_ENABLE, - AccessS3SaveWidth32, - &D0F0x64_x22.Value, - Gnb->StdHeader - ); -//D0F0x64_x23 - GnbLibPciIndirectRead ( - Gnb->GnbPciAddress.AddressValue | D0F0x60_ADDRESS, - D0F0x64_x23_ADDRESS | IOC_WRITE_ENABLE, - AccessWidth32, - &D0F0x64_x23.Value, - Gnb->StdHeader - ); - - D0F0x64_x23.Field.SoftOverrideClk4 = Ioc_Lclk_Gating ? 0 : 1; - D0F0x64_x23.Field.SoftOverrideClk3 = Ioc_Lclk_Gating ? 0 : 1; - D0F0x64_x23.Field.SoftOverrideClk2 = Ioc_Lclk_Gating ? 0 : 1; - D0F0x64_x23.Field.SoftOverrideClk1 = Ioc_Lclk_Gating ? 0 : 1; - D0F0x64_x23.Field.SoftOverrideClk0 = Ioc_Lclk_Gating ? 0 : 1; - - GnbLibPciIndirectWrite ( - Gnb->GnbPciAddress.AddressValue | D0F0x60_ADDRESS, - D0F0x64_x23_ADDRESS | IOC_WRITE_ENABLE, - AccessS3SaveWidth32, - &D0F0x64_x23.Value, - Gnb->StdHeader - ); - //D0F0x64_x24 - GnbLibPciIndirectRead ( - Gnb->GnbPciAddress.AddressValue | D0F0x60_ADDRESS, - D0F0x64_x24_ADDRESS | IOC_WRITE_ENABLE, - AccessWidth32, - &D0F0x64_x24.Value, - Gnb->StdHeader - ); - - D0F0x64_x24.Field.SoftOverrideClk1 = Ioc_Sclk_Gating ? 0 : 1; - D0F0x64_x24.Field.SoftOverrideClk0 = Ioc_Sclk_Gating ? 0 : 1; - - GnbLibPciIndirectWrite ( - Gnb->GnbPciAddress.AddressValue | D0F0x60_ADDRESS, - D0F0x64_x24_ADDRESS | IOC_WRITE_ENABLE, - AccessS3SaveWidth32, - &D0F0x64_x24.Value, - Gnb->StdHeader - ); -//FCRxFF30_01F5[CgIocCgttLclkOverride, CgIocCgttSclkOverride] - NbSmuSrbmRegisterRead (FCRxFF30_01F5_ADDRESS, &FCRxFF30_01F5.Value, Gnb->StdHeader); - FCRxFF30_01F5.Field.CgIocCgttLclkOverride = 0; - FCRxFF30_01F5.Field.CgIocCgttSclkOverride = 0; - NbSmuSrbmRegisterWrite (FCRxFF30_01F5_ADDRESS, &FCRxFF30_01F5.Value, TRUE, Gnb->StdHeader); -} -/** - * Init NB BIF clock gating - * - * - * - * @param[in] NbClkGatingCtrl Pointer to Clock gating control structure - * @param[in] Gnb Pointer to global Gnb configuration - */ - -VOID -NbInitBifClockGating ( - IN NB_CLK_GATING_CTRL *NbClkGatingCtrl, - IN GNB_PLATFORM_CONFIG *Gnb - ) -{ - BOOLEAN Bif_Sclk_Gating; - FCRxFF30_01F4_STRUCT FCRxFF30_01F4; - FCRxFF30_1512_STRUCT FCRxFF30_1512; - - - Bif_Sclk_Gating = NbClkGatingCtrl->Bif_Sclk_Gating; - -//FCRxFF30_01F4[CgBifCgttSclkOverride]. - NbSmuSrbmRegisterRead (FCRxFF30_01F4_ADDRESS, &FCRxFF30_01F4.Value, Gnb->StdHeader); - FCRxFF30_01F4.Field.CgBifCgttSclkOverride = 0; - NbSmuSrbmRegisterWrite (FCRxFF30_01F4_ADDRESS, &FCRxFF30_01F4.Value, TRUE, Gnb->StdHeader); -//FCRxFF30_1512 - NbSmuSrbmRegisterRead (FCRxFF30_1512_ADDRESS, &FCRxFF30_1512.Value, Gnb->StdHeader); - FCRxFF30_1512.Field.SoftOverride0 = Bif_Sclk_Gating ? 0 : 1; - NbSmuSrbmRegisterWrite (FCRxFF30_1512_ADDRESS, &FCRxFF30_1512.Value, TRUE, Gnb->StdHeader); - -} - -/** - * Init NB Gmc clock gating - * - * - * - * @param[in] NbClkGatingCtrl Pointer to Clock gating control structure - * @param[in] Gnb Pointer to global Gnb configuration - */ - -VOID -NbInitGmcClockGating ( - IN NB_CLK_GATING_CTRL *NbClkGatingCtrl, - IN GNB_PLATFORM_CONFIG *Gnb - ) -{ - BOOLEAN Gmc_Sclk_Gating; - FCRxFF30_01F4_STRUCT FCRxFF30_01F4; - FCRxFF30_01F5_STRUCT FCRxFF30_01F5; - - Gmc_Sclk_Gating = NbClkGatingCtrl->Gmc_Sclk_Gating; - -//FCRxFF30_01F4[CgMcdwCgttSclkOverride, CgMcbCgttSclkOverride] - NbSmuSrbmRegisterRead (FCRxFF30_01F4_ADDRESS, &FCRxFF30_01F4.Value, Gnb->StdHeader); - FCRxFF30_01F4.Field.CgMcbCgttSclkOverride = Gmc_Sclk_Gating ? 0 : 1; - FCRxFF30_01F4.Field.CgMcdwCgttSclkOverride = Gmc_Sclk_Gating ? 0 : 1; - NbSmuSrbmRegisterWrite (FCRxFF30_01F4_ADDRESS, &FCRxFF30_01F4.Value, TRUE, Gnb->StdHeader); - -//FCRxFF30_01F5[CgVmcCgttSclkOverride] - NbSmuSrbmRegisterRead (FCRxFF30_01F5_ADDRESS, &FCRxFF30_01F5.Value, Gnb->StdHeader); - FCRxFF30_01F5.Field.CgVmcCgttSclkOverride = Gmc_Sclk_Gating ? 0 : 1; - NbSmuSrbmRegisterWrite (FCRxFF30_01F5_ADDRESS, &FCRxFF30_01F5.Value, TRUE, Gnb->StdHeader); - -} - -/** - * Init NB Dce Sclk clock gating - * - * - * - * @param[in] NbClkGatingCtrl Pointer to Clock gating control structure - * @param[in] Gnb Pointer to global Gnb configuration - */ - -VOID -NbInitDceSclkClockGating ( - IN NB_CLK_GATING_CTRL *NbClkGatingCtrl, - IN GNB_PLATFORM_CONFIG *Gnb - ) -{ - BOOLEAN Dce_Sclk_Gating; - FCRxFF30_0134_STRUCT FCRxFF30_0134; - FCRxFF30_01F4_STRUCT FCRxFF30_01F4; - - Dce_Sclk_Gating = NbClkGatingCtrl->Dce_Sclk_Gating; - -//GMMx4D0[SymclkbGateDisable, SymclkaGateDisable, SclkGateDisable] - NbSmuSrbmRegisterRead (FCRxFF30_0134_ADDRESS, &FCRxFF30_0134.Value, Gnb->StdHeader); - FCRxFF30_0134.Field.SclkGateDisable = Dce_Sclk_Gating ? 0 : 1; - FCRxFF30_0134.Field.SymclkaGateDisable = Dce_Sclk_Gating ? 0 : 1; - FCRxFF30_0134.Field.SymclkbGateDisable = Dce_Sclk_Gating ? 0 : 1; - NbSmuSrbmRegisterWrite (FCRxFF30_0134_ADDRESS, &FCRxFF30_0134.Value, TRUE, Gnb->StdHeader); - -//FCRxFF30_01F4[CgDcCgttSclkOverride] - NbSmuSrbmRegisterRead (FCRxFF30_01F4_ADDRESS, &FCRxFF30_01F4.Value, Gnb->StdHeader); - FCRxFF30_01F4.Field.CgDcCgttSclkOverride = 0; - NbSmuSrbmRegisterWrite (FCRxFF30_01F4_ADDRESS, &FCRxFF30_01F4.Value, TRUE, Gnb->StdHeader); - -} - -/** - * Init NB Dce Display clock gating - * - * - * - * @param[in] NbClkGatingCtrl Pointer to Clock gating control structure - * @param[in] Gnb Pointer to global Gnb configuration - */ - -VOID -NbInitDceDisplayClockGating ( - IN NB_CLK_GATING_CTRL *NbClkGatingCtrl, - IN GNB_PLATFORM_CONFIG *Gnb - ) -{ - BOOLEAN Dce_Dispclk_Gating; - FCRxFF30_0134_STRUCT FCRxFF30_0134; - FCRxFF30_1B7C_STRUCT FCRxFF30_1B7C; - FCRxFF30_1E7C_STRUCT FCRxFF30_1E7C; - FCRxFF30_01F5_STRUCT FCRxFF30_01F5; - - Dce_Dispclk_Gating = NbClkGatingCtrl->Dce_Dispclk_Gating; - -//GMMx4D0[DispclkRDccgGateDisable,DispclkDccgGateDisable] - NbSmuSrbmRegisterRead (FCRxFF30_0134_ADDRESS, &FCRxFF30_0134.Value, Gnb->StdHeader); - FCRxFF30_0134.Field.DispclkDccgGateDisable = Dce_Dispclk_Gating ? 0 : 1; - FCRxFF30_0134.Field.DispclkRDccgGateDisable = Dce_Dispclk_Gating ? 0 : 1; - NbSmuSrbmRegisterWrite (FCRxFF30_0134_ADDRESS, &FCRxFF30_0134.Value, TRUE, Gnb->StdHeader); - -//GMMx[79,6D]F0[CrtcDispclkGSclGateDisable, CrtcDispclkGDcpGateDisable, CrtcDispclkRDcfeGateDisable] - NbSmuSrbmRegisterRead (FCRxFF30_1B7C_ADDRESS, &FCRxFF30_1B7C.Value, Gnb->StdHeader); - FCRxFF30_1B7C.Field.CrtcDispclkRDcfeGateDisable = Dce_Dispclk_Gating ? 0 : 1; - FCRxFF30_1B7C.Field.CrtcDispclkGDcpGateDisable = Dce_Dispclk_Gating ? 0 : 1; - FCRxFF30_1B7C.Field.CrtcDispclkGSclGateDisable = Dce_Dispclk_Gating ? 0 : 1; - NbSmuSrbmRegisterWrite (FCRxFF30_1B7C_ADDRESS, &FCRxFF30_1B7C.Value, TRUE, Gnb->StdHeader); - - NbSmuSrbmRegisterRead (FCRxFF30_1E7C_ADDRESS, &FCRxFF30_1E7C.Value, Gnb->StdHeader); - FCRxFF30_1E7C.Field.CrtcDispclkRDcfeGateDisable = Dce_Dispclk_Gating ? 0 : 1; - FCRxFF30_1E7C.Field.CrtcDispclkGDcpGateDisable = Dce_Dispclk_Gating ? 0 : 1; - FCRxFF30_1E7C.Field.CrtcDispclkGSclGateDisable = Dce_Dispclk_Gating ? 0 : 1; - NbSmuSrbmRegisterWrite (FCRxFF30_1E7C_ADDRESS, &FCRxFF30_1E7C.Value, TRUE, Gnb->StdHeader); - -//FCRxFF30_01F5[CgDcCgttDispclkOverride] - NbSmuSrbmRegisterRead (FCRxFF30_01F5_ADDRESS, &FCRxFF30_01F5.Value, Gnb->StdHeader); - FCRxFF30_01F5.Field.CgDcCgttDispclkOverride = 0; - NbSmuSrbmRegisterWrite (FCRxFF30_01F5_ADDRESS, &FCRxFF30_01F5.Value, TRUE, Gnb->StdHeader); - -} - -/*----------------------------------------------------------------------------------------*/ -/** - * Init NB clock gating - * - * - * - * @param[in] Gnb Pointer to global Gnb configuration - */ - -VOID -NbInitClockGating ( - IN GNB_PLATFORM_CONFIG *Gnb - ) -{ - NB_CLK_GATING_CTRL NbClkGatingCtrl; - - //Init the default value of control structure. - NbClkGatingCtrl.Smu_Sclk_Gating = GnbBuildOptions.SmuSclkClockGatingEnable; - NbClkGatingCtrl.Smu_Lclk_Gating = TRUE; - NbClkGatingCtrl.Orb_Sclk_Gating = TRUE; - NbClkGatingCtrl.Orb_Lclk_Gating = TRUE; - NbClkGatingCtrl.Ioc_Sclk_Gating = TRUE; - NbClkGatingCtrl.Ioc_Lclk_Gating = TRUE; - NbClkGatingCtrl.Bif_Sclk_Gating = TRUE; - NbClkGatingCtrl.Gmc_Sclk_Gating = TRUE; - NbClkGatingCtrl.Dce_Sclk_Gating = TRUE; - NbClkGatingCtrl.Dce_Dispclk_Gating = TRUE; - - NbFmNbClockGating (&NbClkGatingCtrl, Gnb->StdHeader); - - IDS_OPTION_HOOK (IDS_GNB_CLOCK_GATING, &NbClkGatingCtrl, Gnb->StdHeader); - - - IDS_HDT_CONSOLE (GNB_TRACE, "NbInitClockGating Enter\n"); - -//SMU SCLK/LCLK clock gating - NbInitSmuClockGating (&NbClkGatingCtrl, Gnb); - -// ORB clock gating - NbInitOrbClockGating (&NbClkGatingCtrl, Gnb); - -//IOC clock gating - NbInitIocClockGating (&NbClkGatingCtrl, Gnb); - -//BIF Clock Gating - NbInitBifClockGating (&NbClkGatingCtrl, Gnb); - -//GMC Clock Gating - NbInitGmcClockGating (&NbClkGatingCtrl, Gnb); - -//DCE Sclk clock gating - NbInitDceSclkClockGating (&NbClkGatingCtrl, Gnb); - -//DCE Display clock gating - NbInitDceDisplayClockGating (&NbClkGatingCtrl, Gnb); - - GNB_DEBUG_CODE ( - { - FCRxFF30_01F4_STRUCT FCRxFF30_01F4; - FCRxFF30_01F5_STRUCT FCRxFF30_01F5; - FCRxFF30_1512_STRUCT FCRxFF30_1512; - NbSmuSrbmRegisterRead (FCRxFF30_01F4_ADDRESS, &FCRxFF30_01F4.Value, Gnb->StdHeader); - NbSmuSrbmRegisterRead (FCRxFF30_01F5_ADDRESS, &FCRxFF30_01F5.Value, Gnb->StdHeader); - NbSmuSrbmRegisterRead (FCRxFF30_1512_ADDRESS, &FCRxFF30_1512.Value, Gnb->StdHeader); - IDS_HDT_CONSOLE (NB_MISC, " Clock Gating FCRxFF30_01F4 - 0x%x\n", FCRxFF30_01F4.Value); - IDS_HDT_CONSOLE (NB_MISC, " Clock Gating FCRxFF30_01F5 - 0x%x\n", FCRxFF30_01F5.Value); - IDS_HDT_CONSOLE (NB_MISC, " Clock Gating FCRxFF30_1512 - 0x%x\n", FCRxFF30_1512.Value); - } - ); - IDS_HDT_CONSOLE (GNB_TRACE, "NbInitClockGating End\n"); -} diff --git a/src/vendorcode/amd/agesa/f12/Proc/GNB/Nb/NbPowerMgmt.h b/src/vendorcode/amd/agesa/f12/Proc/GNB/Nb/NbPowerMgmt.h deleted file mode 100644 index 1800a0e606..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/GNB/Nb/NbPowerMgmt.h +++ /dev/null @@ -1,69 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * NB power management features - * - * - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: GNB - * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $ - * - */ -/* -***************************************************************************** -* -* Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* *************************************************************************** -* -*/ - -#ifndef _NBPOWERMGMT_H_ -#define _NBPOWERMGMT_H_ - - -AGESA_STATUS -NbInitPowerManagement ( - IN GNB_PLATFORM_CONFIG *Gnb - ); - -///Control structure for clock gating feature -typedef struct { - BOOLEAN Smu_Sclk_Gating; ///= AccessS3SaveWidth8) ? AccessS3SaveWidth32 : AccessWidth32, - &D0F0x64_x4D.Value, - StdHeader - ); - - GnbLibPciIndirectRead ( - MAKE_SBDFO (0, 0, 0, 0, D0F0x60_ADDRESS), - D0F0x64_x4E_ADDRESS | IOC_WRITE_ENABLE, - (Width >= AccessS3SaveWidth8) ? AccessS3SaveWidth32 : AccessWidth32, - &Data, - StdHeader - ); - - switch (Width) { - case AccessWidth16: - //no break; intended to fall through - case AccessS3SaveWidth16: - *(UINT16 *) Value = (UINT16) Data; - break; - case AccessWidth32: - //no break; intended to fall through - case AccessS3SaveWidth32: - *(UINT32 *) Value = Data; - break; - default: - ASSERT (FALSE); - } -} - -/*----------------------------------------------------------------------------------------*/ -/** - * SMU indirect register read - * - * - * - * @param[in] Address Register Address - * @param[in] Width Access width - * @param[in] Mask Data mask for compare - * @param[in] CompateData Compare data - * @param[in] StdHeader Pointer to standard configuration - */ - - -VOID -NbSmuIndirectPoll ( - IN UINT8 Address, - IN ACCESS_WIDTH Width, - IN UINT32 Mask, - IN UINT32 CompateData, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - UINT32 Value; - - do { - NbSmuIndirectRead ( - Address, - Width, - &Value, - StdHeader - ); - } while ((Value & Mask) != CompateData); -} - - -/*----------------------------------------------------------------------------------------*/ -/** - * SMU indirect register write - * - * - * - * @param[in] Address Register Address - * @param[in] Width Data width for write - * @param[in] Value Pointer to write value - * @param[in] StdHeader Pointer to standard configuration - */ - - -VOID -NbSmuIndirectWriteEx ( - IN UINT8 Address, - IN ACCESS_WIDTH Width, - IN VOID *Value, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - D0F0x64_x4D_STRUCT D0F0x64_x4D; - ASSERT (Width != AccessWidth8); - ASSERT (Width != AccessS3SaveWidth8); - - GnbLibPciIndirectRead ( - MAKE_SBDFO (0, 0, 0, 0, D0F0x60_ADDRESS), - D0F0x64_x4D_ADDRESS | IOC_WRITE_ENABLE, - AccessWidth32, - &D0F0x64_x4D.Value, - StdHeader - ); - - D0F0x64_x4D.Field.ReqType = 0x1; - D0F0x64_x4D.Field.SmuAddr = Address; - D0F0x64_x4D.Field.ReqToggle = (!D0F0x64_x4D.Field.ReqToggle); - - D0F0x64_x4D.Field.WriteData = ((UINT16 *) Value) [0]; - - GnbLibPciIndirectWrite ( - MAKE_SBDFO (0, 0, 0, 0, D0F0x60_ADDRESS), - D0F0x64_x4D_ADDRESS | IOC_WRITE_ENABLE, - (Width >= AccessS3SaveWidth8) ? AccessS3SaveWidth32 : AccessWidth32, - &D0F0x64_x4D.Value, - StdHeader - ); - if (LibAmdAccessWidth (Width) <= 2) { - return; - } - D0F0x64_x4D.Field.ReqType = 0x1; - D0F0x64_x4D.Field.SmuAddr = Address + 1; - D0F0x64_x4D.Field.ReqToggle = (!D0F0x64_x4D.Field.ReqToggle); - D0F0x64_x4D.Field.WriteData = ((UINT16 *) Value)[1]; - - GnbLibPciIndirectWrite ( - MAKE_SBDFO (0, 0, 0, 0, D0F0x60_ADDRESS), - D0F0x64_x4D_ADDRESS | IOC_WRITE_ENABLE, - (Width >= AccessS3SaveWidth8) ? AccessS3SaveWidth32 : AccessWidth32, - &D0F0x64_x4D.Value, - StdHeader - ); -} - - -/*----------------------------------------------------------------------------------------*/ -/** - * SMU indirect register write - * - * - * - * @param[in] Address Register Address - * @param[in] Width Data width for write - * @param[in] Value Pointer to write value - * @param[in] StdHeader Pointer to standard configuration - */ - - -VOID -NbSmuIndirectWrite ( - IN UINT8 Address, - IN ACCESS_WIDTH Width, - IN VOID *Value, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - if (Width >= AccessS3SaveWidth8) { - SMU_INDIRECT_WRITE_DATA Data; - Data.Address = Address; - Data.Width = Width; - Data.Value = *((UINT32*) Value); - S3_SAVE_DISPATCH (StdHeader, NbSmuIndirectWriteS3Script_ID, sizeof (SMU_INDIRECT_WRITE_DATA), &Data); - Width = Width - (AccessS3SaveWidth8 - AccessWidth8); - } - NbSmuIndirectWriteEx (Address, Width, Value, StdHeader); -} - - -/*----------------------------------------------------------------------------------------*/ -/** - * SMU Service request for S3 script - * - * - * @param[in] StdHeader Standard configuration header - * @param[in] ContextLength Not used - * @param[in] Context Pointer to service request ID - */ - -VOID -NbSmuIndirectWriteS3Script ( - IN AMD_CONFIG_PARAMS *StdHeader, - IN UINT16 ContextLength, - IN VOID* Context - ) -{ - SMU_INDIRECT_WRITE_DATA *Data; - Data = (SMU_INDIRECT_WRITE_DATA*) Context; - NbSmuIndirectWriteEx (Data->Address, Data->Width, &Data->Value, StdHeader); -} - -/*----------------------------------------------------------------------------------------*/ -/** - * SMU RAM mapped register write - * - * - * - * @param[in] Address Register Address - * @param[in] Value Data pointer for write - * @param[in] Count Number of registers to write - * @param[in] S3Save Save for S3 (True/False) - * @param[in] StdHeader Standard configuration header - */ - -VOID -NbSmuRcuRegisterWrite ( - IN UINT16 Address, - IN UINT32 *Value, - IN UINT32 Count, - IN BOOLEAN S3Save, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - UINT32 CurrentAddress; - CurrentAddress = Address; - NbSmuIndirectWrite ( - SMUx0B_ADDRESS, - S3Save ? AccessS3SaveWidth16 : AccessWidth16, - &Address, - StdHeader - ); - while (Count-- > 0) { - IDS_HDT_CONSOLE (NB_SMUREG_TRACE, " *WR SMUx0B:0x%x = 0x%x\n", CurrentAddress, *Value); - NbSmuIndirectWrite ( - SMUx05_ADDRESS, - S3Save ? AccessS3SaveWidth32 : AccessWidth32, - Value++, - StdHeader - ); - CurrentAddress += 4; - } -} - - -/*----------------------------------------------------------------------------------------*/ -/** - * SMU RAM mapped register read - * - * - * - * @param[in] Address Register Address - * @param[out] Value Pointer read value - * @param[in] Count Number of registers to read - * @param[in] StdHeader Pointer to standard configuration - */ - -VOID -NbSmuRcuRegisterRead ( - IN UINT16 Address, - OUT UINT32 *Value, - IN UINT32 Count, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - NbSmuIndirectWrite (SMUx0B_ADDRESS, AccessWidth16, &Address, StdHeader); - while (Count-- > 0) { - NbSmuIndirectRead (SMUx05_ADDRESS, AccessWidth32, Value++, StdHeader); - } -} - - -/*----------------------------------------------------------------------------------------*/ -/** - * SMU Service request Ext - * - * - * @param[in] RequestId request ID - * @param[in] Flags Flags - * @param[in] StdHeader Standard configuration header - */ - -VOID -NbSmuServiceRequestEx ( - IN UINT8 RequestId, - IN UINT8 Flags, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - SMUx03_STRUCT SMUx03; - SMUx03.Value = 0; - SMUx03.Field.IntReq = 1; - SMUx03.Field.ServiceIndex = RequestId; - NbSmuIndirectWrite (SMUx03_ADDRESS, AccessWidth32, &SMUx03.Value, StdHeader); - if ((Flags & SMU_EXT_SERVICE_FLAGS_POLL_ACK) != 0) { - NbSmuIndirectPoll (SMUx03_ADDRESS, AccessWidth32, BIT1, BIT1, StdHeader); // Wait till IntAck - } - if ((Flags & SMU_EXT_SERVICE_FLAGS_POLL_DONE) != 0) { - NbSmuIndirectPoll (SMUx03_ADDRESS, AccessWidth32, BIT2, BIT2, StdHeader); // Wait till IntDone - } - SMUx03.Value = 0; // Clear IRQ register - NbSmuIndirectWrite (SMUx03_ADDRESS, AccessWidth32, &SMUx03.Value, StdHeader); -} - -/*----------------------------------------------------------------------------------------*/ -/** - * SMU Service request - * - * - * @param[in] RequestId request ID - * @param[in] S3Save Save for S3 (True/False) - * @param[in] StdHeader Standard configuration header - */ - -VOID -NbSmuServiceRequest ( - IN UINT8 RequestId, - IN BOOLEAN S3Save, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - IDS_HDT_CONSOLE (GNB_TRACE, "NbSmuServiceRequest Enter [0x%02x]\n", RequestId); - if (S3Save) { - S3_SAVE_DISPATCH (StdHeader, NbSmuServiceRequestS3Script_ID, sizeof (RequestId), &RequestId); - } - NbSmuServiceRequestEx ( - RequestId, - SMU_EXT_SERVICE_FLAGS_POLL_ACK | SMU_EXT_SERVICE_FLAGS_POLL_DONE, - StdHeader - ); - IDS_HDT_CONSOLE (GNB_TRACE, "NbSmuServiceRequest Exit\n"); -} - -/*----------------------------------------------------------------------------------------*/ -/** - * SMU Service request for S3 script - * - * - * @param[in] StdHeader Standard configuration header - * @param[in] ContextLength Not used - * @param[in] Context Pointer to service request ID - */ - -VOID -NbSmuServiceRequestS3Script ( - IN AMD_CONFIG_PARAMS *StdHeader, - IN UINT16 ContextLength, - IN VOID* Context - ) -{ - NbSmuServiceRequest (*((UINT8*) Context), FALSE, StdHeader); -} - -/*----------------------------------------------------------------------------------------*/ -/** - * SMU Read FCR register - * - * - * @param[in] Address FCR Address - * @param[in] StdHeader Standard configuration header - */ - -UINT32 -NbSmuReadEfuse ( - IN UINT32 Address, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - UINT32 Value; - - NbSmuSrbmRegisterRead (Address, &Value, StdHeader); - Value = (Value >> 24) | (Value << 24) | ((Value >> 8) & 0xFF00) | ((Value << 8) & 0xFF0000); - return Value; -} - -/*----------------------------------------------------------------------------------------*/ -/** - * SMU Read arbitrary fuse field - * - * - * @param[in] Chain Address - * @param[in] Offset Offcet - * @param[in] Length Length - * @param[in] StdHeader Standard configuration header - */ - -UINT32 -NbSmuReadEfuseField ( - IN UINT8 Chain, - IN UINT16 Offset, - IN UINT8 Length, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - UINT32 Value; - UINT32 Result; - UINT32 Address; - UINT16 Shift; - ASSERT (Length <= 32); - Shift = (Offset - (Offset & ~0x7)); - Address = 0xFE000000 | (Chain << 12) | (Offset >> 3); - Value = NbSmuReadEfuse (Address, StdHeader); - Result = Value >> Shift; - if ((Shift + Length) > 32) { - Value = NbSmuReadEfuse (Address + 1, StdHeader); - Result |= (Value << (32 - Shift)); - } - Result &= ((1 << Length) - 1); - return Value; -} - -/*----------------------------------------------------------------------------------------*/ -/** - * SMU SRBM (GMM) register read - * - * - * - * @param[in] Address Register Address - * @param[out] Value Pointer read value - * @param[in] StdHeader Pointer to standard configuration - */ - -VOID -NbSmuSrbmRegisterRead ( - IN UINT32 Address, - OUT UINT32 *Value, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - MBUS Mbus; - Mbus.SMUx0B_x8600.Value = (0x8650 << SMUx0B_x8600_MemAddr_7_0__OFFSET) | - (1 << SMUx0B_x8600_TransactionCount_OFFSET); - Mbus.SMUx0B_x8604.Value = (4 << SMUx0B_x8604_Txn1TransferLength_7_0__OFFSET); - Mbus.SMUx0B_x8608.Value = (UINT32) (3 << SMUx0B_x8608_Txn1Tsize_OFFSET); - Mbus.SMUx0B_x8600.Field.Txn1MBusAddr_7_0_ = Address & 0xff; - Mbus.SMUx0B_x8604.Field.Txn1MBusAddr_15_8_ = (Address >> 8) & 0xff; - Mbus.SMUx0B_x8604.Field.Txn1MBusAddr_23_16_ = (Address >> 16) & 0xff; - Mbus.SMUx0B_x8604.Field.Txn1MBusAddr_31_24_ = (Address >> 24) & 0xff; - NbSmuRcuRegisterWrite (SMUx0B_x8600_ADDRESS, (UINT32*) &Mbus, 3, FALSE, StdHeader); - NbSmuServiceRequest (0x0B, FALSE, StdHeader); - NbSmuRcuRegisterRead (SMUx0B_x8650_ADDRESS, Value, 1, StdHeader); -} - -/*----------------------------------------------------------------------------------------*/ -/** - * SMU SRBM (GMM) register write - * - * - * - * @param[in] Address Register Address - * @param[in] Value Data pointer for write - * @param[in] S3Save Save for S3 (True/False) - * @param[in] StdHeader Standard configuration header - */ - -VOID -NbSmuSrbmRegisterWrite ( - IN UINT32 Address, - IN UINT32 *Value, - IN BOOLEAN S3Save, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - MBUS Mbus; - IDS_HDT_CONSOLE (NB_SMUREG_TRACE, " *WR SRBM (GMM):0x%x = 0x%x\n", Address, *Value); - Mbus.SMUx0B_x8600.Value = (0x8650 << SMUx0B_x8600_MemAddr_7_0__OFFSET) | - (1 << SMUx0B_x8600_TransactionCount_OFFSET); - Mbus.SMUx0B_x8604.Value = (4 << SMUx0B_x8604_Txn1TransferLength_7_0__OFFSET); - Mbus.SMUx0B_x8608.Value = (UINT32) (3 << SMUx0B_x8608_Txn1Tsize_OFFSET); - Mbus.SMUx0B_x8608.Field.Txn1Mode = 0x1; - Mbus.SMUx0B_x8600.Field.Txn1MBusAddr_7_0_ = Address & 0xff; - Mbus.SMUx0B_x8604.Field.Txn1MBusAddr_15_8_ = (Address >> 8) & 0xff; - Mbus.SMUx0B_x8604.Field.Txn1MBusAddr_23_16_ = (Address >> 16) & 0xff; - Mbus.SMUx0B_x8604.Field.Txn1MBusAddr_31_24_ = (Address >> 24) & 0xff; - NbSmuRcuRegisterWrite (SMUx0B_x8600_ADDRESS, (UINT32*) &Mbus, 3, S3Save, StdHeader); - NbSmuRcuRegisterWrite (SMUx0B_x8650_ADDRESS, Value, 1, S3Save, StdHeader); - NbSmuServiceRequest (0x0B, S3Save, StdHeader); -} - -/*----------------------------------------------------------------------------------------*/ -/** - * SMU firmware download - * - * - * - * @param[in] StdHeader Pointer to Standard configuration - * @param[in] Firmware Pointer to SMU firmware header - * @retval AGESA_STATUS - */ - -VOID -NbSmuFirmwareDownload ( - IN SMU_FIRMWARE_HEADER *Firmware, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - UINTN Index; - SMUx01_STRUCT SMUx01; - NbSmuServiceRequestEx (0x10, SMU_EXT_SERVICE_FLAGS_POLL_ACK , StdHeader); - SMUx01.Value = (1 << SMUx01_RamSwitch_OFFSET) | (1 << SMUx01_VectorOverride_OFFSET); - NbSmuIndirectWrite (SMUx01_ADDRESS, AccessWidth32, &SMUx01.Value, StdHeader); - for (Index = 0; Index < Firmware->NumberOfBlock; Index++) { - NbSmuRcuRegisterWrite ( - (Firmware->BlockArray)[Index].Address, - (Firmware->BlockArray)[Index].Data, - (Firmware->BlockArray)[Index].Length, - FALSE, - StdHeader - ); - } - SMUx01.Value = (1 << SMUx01_Reset_OFFSET) | (1 << SMUx01_VectorOverride_OFFSET); - NbSmuIndirectWrite (SMUx01_ADDRESS, AccessWidth32, &SMUx01.Value, StdHeader); -} - -/*----------------------------------------------------------------------------------------*/ -/** - * SMU firmware revision - * - * - * - * @param[in] StdHeader Pointer to Standard configuration - * @retval Firmware revision info - */ - -SMU_FIRMWARE_REV -NbSmuFirmwareRevision ( - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - SMU_FIRMWARE_REV Revision; - UINT32 FmRev; - NbSmuRcuRegisterRead ( - 0x830C, - &FmRev, - 1, - StdHeader - ); - Revision.MajorRev = ((UINT16*)&FmRev) [1]; - Revision.MinorRev = ((UINT16*)&FmRev) [0]; - return Revision; -} diff --git a/src/vendorcode/amd/agesa/f12/Proc/GNB/Nb/NbSmuLib.h b/src/vendorcode/amd/agesa/f12/Proc/GNB/Nb/NbSmuLib.h deleted file mode 100644 index 6a1435f496..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/GNB/Nb/NbSmuLib.h +++ /dev/null @@ -1,184 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * Various NB initialization services - * - * - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: GNB - * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $ - * - */ -/* -***************************************************************************** -* -* Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* *************************************************************************** -* -*/ -#ifndef _NBSMULIB_H_ -#define _NBSMULIB_H_ - - -#define SMU_EXT_SERVICE_FLAGS_POLL_ACK 0x1 -#define SMU_EXT_SERVICE_FLAGS_POLL_DONE 0x2 -#define SMU_GMM_TO_FCR(GmmReg) ((GmmReg >> 2) | 0xFF300000) - -#pragma pack (push, 1) -/// SMU Register Entry -typedef struct { - UINT16 Reg; ///< Register address - UINT32 Value; ///< Register data -} SMU_REGISTER_ENTRY; - -/// SMU Firmware revision -typedef struct { - UINT16 MajorRev; ///< Major revision - UINT16 MinorRev; ///< Minor revision -} SMU_FIRMWARE_REV; - -/// Firmware block -typedef struct { - UINT16 Address; ///< Block Address - UINT16 Length; ///< Block length in DWORD - UINT32 *Data; ///< Pointer to data array -} SMU_FIRMWARE_BLOCK; - -/// Firmware header -typedef struct { - SMU_FIRMWARE_REV Revision; ///< Revision info - UINT16 NumberOfBlock; ///< Number of blocks - SMU_FIRMWARE_BLOCK *BlockArray; ///< Pointer to block definition array -} SMU_FIRMWARE_HEADER; - -/// SMU indirect register write data context -typedef struct { - UINT8 Address; ///< SMU indirect register address - ACCESS_WIDTH Width; ///< SMU indirect register width - UINT32 Value; ///< Value -} SMU_INDIRECT_WRITE_DATA; -#pragma pack (pop) - -VOID -NbSmuIndirectRead ( - IN UINT8 Address, - IN ACCESS_WIDTH Width, - OUT VOID *Value, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -VOID -NbSmuIndirectPoll ( - IN UINT8 Address, - IN ACCESS_WIDTH Width, - IN UINT32 Mask, - IN UINT32 CompateData, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -VOID -NbSmuIndirectWrite ( - IN UINT8 Address, - IN ACCESS_WIDTH Width, - IN VOID *Value, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -VOID -NbSmuRcuRegisterWrite ( - IN UINT16 Address, - IN UINT32 *Value, - IN UINT32 Count, - IN BOOLEAN S3Save, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -VOID -NbSmuRcuRegisterRead ( - IN UINT16 Address, - OUT UINT32 *Value, - IN UINT32 Count, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -VOID -NbSmuSrbmRegisterRead ( - IN UINT32 Address, - OUT UINT32 *Value, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -VOID -NbSmuSrbmRegisterWrite ( - IN UINT32 Address, - IN UINT32 *Value, - IN BOOLEAN S3Save, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -VOID -NbSmuServiceRequestEx ( - IN UINT8 RequestId, - IN UINT8 Flags, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -VOID -NbSmuServiceRequest ( - IN UINT8 RequestId, - IN BOOLEAN S3Save, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -VOID -NbSmuServiceRequestS3Script ( - IN AMD_CONFIG_PARAMS *StdHeader, - IN UINT16 ContextLength, - IN VOID* Context - ); - -UINT32 -NbSmuReadEfuse ( - IN UINT32 Address, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -VOID -NbSmuFirmwareDownload ( - IN SMU_FIRMWARE_HEADER *Firmware, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -SMU_FIRMWARE_REV -NbSmuFirmwareRevision ( - IN AMD_CONFIG_PARAMS *StdHeader - ); - -#define SMI_FIRMWARE_REVISION(x) ((x.MajorRev << 16) | x.MinorRev) -#endif diff --git a/src/vendorcode/amd/agesa/f12/Proc/GNB/PCIe/Family/LN/F12PcieAlib.c b/src/vendorcode/amd/agesa/f12/Proc/GNB/PCIe/Family/LN/F12PcieAlib.c deleted file mode 100644 index 80095063c9..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/GNB/PCIe/Family/LN/F12PcieAlib.c +++ /dev/null @@ -1,135 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * PCIe ALIB - * - * - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: GNB - * @e \$Revision: 49994 $ @e \$Date: 2011-03-31 15:44:04 +0800 (Thu, 31 Mar 2011) $ - * - */ -/* -***************************************************************************** -* -* Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* *************************************************************************** -* -*/ - -/*---------------------------------------------------------------------------------------- - * M O D U L E S U S E D - *---------------------------------------------------------------------------------------- - */ - -#include "AGESA.h" -#include "Ids.h" -#include "Gnb.h" -#include "OptionGnb.h" -#include "GnbPcie.h" -#include "GnbGfx.h" -#include "cpuLateInit.h" -#include "GnbCommonLib.h" -#include "GnbGfxConfig.h" -#include "GnbGfxInitLibV1.h" -#include "F12PcieAlibSsdt.h" -#include "GnbPcieFamServices.h" -#include "Filecode.h" -#define FILECODE PROC_GNB_PCIE_FAMILY_LN_F12PCIEALIB_FILECODE -/*---------------------------------------------------------------------------------------- - * D E F I N I T I O N S A N D M A C R O S - *---------------------------------------------------------------------------------------- - */ - -extern GNB_BUILD_OPTIONS GnbBuildOptions; - -/*---------------------------------------------------------------------------------------- - * T Y P E D E F S A N D S T R U C T U R E S - *---------------------------------------------------------------------------------------- - */ - - - -/*---------------------------------------------------------------------------------------- - * P R O T O T Y P E S O F L O C A L F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ - - -/*----------------------------------------------------------------------------------------*/ -/** - * Build ALIB ACPI table - * - * - * - * @param[in,out] AlibSsdtPtr Pointer to ALIB SSDT table - * @param[in] StdHeader Standard Configuration Header - * @retval AGESA_SUCCESS - * @retval AGESA_FATAL - */ - -AGESA_STATUS -PcieFmAlibBuildAcpiTable ( - IN VOID *AlibSsdtPtr, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - AGESA_STATUS Status; - AGESA_STATUS AgesaStatus; - UINT32 AmlObjName; - GFX_PLATFORM_CONFIG *Gfx; - VOID *AmlObjPtr; - BOOLEAN AltVddNbSupport; - IDS_HDT_CONSOLE (GNB_TRACE, "PcieFmAlibBuildAcpiTable Enter\n"); - AgesaStatus = AGESA_SUCCESS; - AltVddNbSupport = TRUE; -// AmlObjName = 'A0DA'; - AmlObjName = Int32FromChar ('A', '0', 'D', 'A'); - AmlObjPtr = GnbLibFind (AlibSsdtPtr, ((ACPI_TABLE_HEADER*) &AlibSsdt[0])->TableLength, (UINT8*) &AmlObjName, sizeof (AmlObjName)); - ASSERT (AmlObjPtr != NULL); - if (AmlObjPtr != NULL) { - Status = GfxLocateConfigData (StdHeader, &Gfx); - AGESA_STATUS_UPDATE (Status, AgesaStatus); - ASSERT (Status == AGESA_SUCCESS); - if ((Status != AGESA_SUCCESS) || (GnbBuildOptions.CfgAltVddNb == FALSE) || (Gfx->UmaInfo.MemClock > DDR1333_FREQUENCY) || - ((Gfx->GfxDiscreteCardInfo.AmdPcieGfxCardBitmap != 0) && GfxLibIsControllerPresent (StdHeader))) { - AltVddNbSupport = FALSE; - } - // CBS/IDS can change AltVddNbSupport - IDS_OPTION_HOOK (IDS_GNB_ALTVDDNB, &AltVddNbSupport, StdHeader); - if (!AltVddNbSupport) { - IDS_HDT_CONSOLE (GNB_TRACE, " AltVddNb - Disabled\n"); - *(UINT8*)((UINT8*) AmlObjPtr + 5) = 0; - } - } else { - AgesaStatus = AGESA_ERROR; - } - IDS_HDT_CONSOLE (GNB_TRACE, "PcieFmAlibBuildAcpiTable Exit[0x%x]\n", AgesaStatus); - return AgesaStatus; -} diff --git a/src/vendorcode/amd/agesa/f12/Proc/GNB/PCIe/Family/LN/F12PcieAlib.esl b/src/vendorcode/amd/agesa/f12/Proc/GNB/PCIe/Family/LN/F12PcieAlib.esl deleted file mode 100644 index 01c55e87d0..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/GNB/PCIe/Family/LN/F12PcieAlib.esl +++ /dev/null @@ -1,237 +0,0 @@ -/** - * @file - * - * ALIB ASL library - * - * - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: GNB - * @e \$Revision: 31805 $ @e \$Date: 2010-05-21 17:58:16 -0700 (Fri, 21 May 2010) $ - * - */ -/* -***************************************************************************** -* -* Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* *************************************************************************** -* -*/ - -DefinitionBlock ( - "F12PcieAlibSsdt.aml", - "SSDT", - 2, - "AMD", - "ALIB", - 0x1 - ) -{ - Scope(\_SB) { - - Name (varMaxPortIndexNumber, 6) - - include ("PcieAlibCore.asl") - include ("PcieSmuLib.asl") - include ("PcieAlibPspp.asl") - include ("PcieAlibHotplug.asl") - - Name (varBoostState, 0) - Name (varPdmState, 0) - Name (varIntRateMonitorMaskState, 0) - Name (varIsStateInitialized, 0) - - /*----------------------------------------------------------------------------------------*/ - /** - * Activate APM/PDM state - * - * Arg0 - 0 (AC) 1 (DC) - */ - Method (procApmPdmActivate, 1, NotSerialized) { - Store (Or(ShiftLeft (0x18, 3), 4), Local1) - if (LEqual (varIsStateInitialized, 0)) { - Store (procSmuRcuRead (0x8580), varPdmState) - Store (procPciDwordRead (Local1, 0x15C), varBoostState) - Store (procPciDwordRead (Local1, 0x1A4), varIntRateMonitorMaskState) - Store (1, varIsStateInitialized) - } - Store (procSmuRcuRead (0x8580), Local0) - Store (Or(ShiftLeft (0x18, 3), 4), Local1) - Store (procPciDwordRead (Local1, 0x15C), Local2) - Store (procPciDwordRead (Local1, 0x1A4), Local3) - if (LEqual (Arg0, 1)) { - // DC mode -- - //1. To stall the PDM flow: - //Bit SMU0xB_x8580[PdmEn] needs to be cleared (0). The bit needs to be set to 0 and the service routine 12h (SMU) called. This will force the disabling of the PDM flow. - //2. To disable the APM: F4x15C[1:0]=00 - //3. F4x1A4 needs to be set to FFFF_FFFF - And (Local0, 0xFFFFFFFE, Local0) - And (Local2, 0xFFFFFFFC, Local2) - Or (Local3, 0x3, Local3) - } else { - Or (Local0, And (varPdmState, 1), Local0) - // Restore only D18F4x15C[0:1] - Or (Local2, And (varBoostState, 0x3), Local2) - // Restore only D18F4x1A4[0:1] - And (Local3, Or (0xFFFFFFFC, varIntRateMonitorMaskState), Local3) - } - procPciDwordWrite (Local1, 0x1A4, Local3) - procPciDwordWrite (Local1, 0x15C, Local2) - procSmuRcuWrite (0x8580, Local0) - procNbSmuServiceRequest (0x12, 0x3) - } - - /*----------------------------------------------------------------------------------------*/ - /** - * Activate ALTVDDNB - * - * Arg0 - 1 - GEN1 2 - GEN2 - */ - Method (procNbLclkDpmActivate, 1, NotSerialized) { - Store (procPsppGetAcDcState(), varAcDcStateLocal1) - Store (procSmuRcuRead (0x8490), Local0) - // Patch state only if at least one state is enable - if (LNotEqual (And (Local0, 0xF0), 0)) { - if (LEqual (Arg0, DEF_LINK_SPEED_GEN2)) { - //If AC/DC, & Gen2 supported, activate state DPM0 and DPM2, - //set SMUx0B_x8490[LclkDpmValid[5, 7] = 1, set SMUx0B_x8490[LclkDpmValid[6]] = 0 - //This is a battery idle state along with a perf state that will be programmed to the max LCLK achievable at the Gen2 VID - And (Local0, 0xFFFFFFA0, Local0) - Or (Local0, 0xA0, Local0) - - } else { - if (LEqual (varAcDcStateLocal1, DEF_PSPP_STATE_AC)) { - //If AC, & if only Gen1 supported, activate state DPM0 and DPM1 - //set SMUx0B_x8490[LclkDpmValid[6, 5]] = 1, set SMUx0B_x8490[LclkDpmValid[7]] = 0 - And (Local0, 0xFFFFFF60, Local0) - Or (Local0, 0x60, Local0) - } else { - //If DC mode & Gen1 supported, activate only state DPM0 - //set SMUx0B_x8490[LclkDpmValid[7, 6]] = 0, set SMUx0B_x8490[LclkDpmValid[5]] = 1 - And (Local0, 0xFFFFFF20, Local0) - Or (Local0, 0x20, Local0) - } - } - procSmuRcuWrite (0x8490, Local0) - } - } - Name (AD0A, 1) -#ifdef ALTVDDNB_SUPPORT - /*----------------------------------------------------------------------------------------*/ - /** - * AltvddNb control - * - * Arg0 - 1 - GEN1 2 - GEN2 - */ - Method (procNbAltVddNb, 1, NotSerialized) { - if (LEqual (AD0A, 1)) { - Store (procPsppGetAcDcState(), varAcDcStateLocal1) - Store (procSmuRcuRead (0x842C), Local0) - And (Local0, 0xFFFFFFFE, Local0) - if (LAnd (LEqual (Arg0, DEF_LINK_SPEED_GEN1), LEqual (varAcDcStateLocal1, DEF_PSPP_STATE_DC))) { - Or (Local0, 0x1, Local0) - } - procSmuRcuWrite (0x842C, Local0) - procNbSmuServiceRequest (0x1B, 0x3) - } - } -#endif - -#ifdef PCIE_PHY_LANE_POWER_GATE_SUPPORT - /*----------------------------------------------------------------------------------------*/ - /** - * Power gate PCIe phy lanes (hotplug support) - * - * Arg0 - Start Lane ID - * Arg1 - End Lane ID - * Arg2 - Power ON(0) / OFF(1) - */ - Method (procPcieLanePowerControl, 3, NotSerialized) { - Store ("PcieLanePowerControl Enter", Debug) - - Store (Concatenate (" Start Lane ID : ", ToHexString (Arg0), Local6), Debug) - Store (Concatenate (" End Lane ID : ", ToHexString (Arg1), Local6), Debug) - Store (Concatenate (" Power ON(0) / OFF(1) : ", ToHexString (Arg2), Local6), Debug) - - //Start Arg0, End Arg1, Core 0, Tx 1, Rx 1 - //[Core, Tx, Rx]=[0, 1, 1] for both plug and unplug, the only difference is ServiceId. - Or (Or (ShiftLeft (Arg1, 24), ShiftLeft (Arg0, 16)), 0x3, Local0) - //Store (Local0, Debug) - - procSmuRcuWrite (0x858C, Local0) - //Arg2 - Power ON(0) / OFF(1) - //Service ID : 0x14 Ungate. 0x13 Gate. So subtract Arg2 to determine SeriveId. - procNbSmuServiceRequest (Subtract (0x14, Arg2), 0x3) - - Store ("PcieLanePowerControl Exit", Debug) - } -#endif - /*----------------------------------------------------------------------------------------*/ - /** - * Pcie Adjust Pll - * - * Arg0 - 1 - GEN1 2 - GEN2 - * - */ - Method (procPcieAdjustPll, 1, NotSerialized) { - - Store ("PcieAdjustPll Enter", Debug) - Store (Arg0, Local0) - if (LEqual (Arg0, 0x2)) { - Store (0, Local0) - } - //GPP - //Store ("GPP Lane bit map = ", Debug) - //Store (procIndirectRegisterRead (0x0, 0xE0, 0x01308023), Debug) - if (LNotEqual (procIndirectRegisterRead (0x0, 0xE0, 0x01308023), 0)) { - //Store ("Before GPP 0x0130_8016 = ", Debug) - //Store (procIndirectRegisterRead (0x0, 0xE0, 0x01308016), Debug) - procIndirectRegisterRMW (0x0, 0xE0, 0x01308016, Not (0x00001000), ShiftLeft (Local0, 12)); - //Store ("After GPP 0x0130_8016 = ", Debug) - //Store (procIndirectRegisterRead (0x0, 0xE0, 0x01308016), Debug) - // Waiting for PLL changing done. - while (LNotEqual (AND(procIndirectRegisterRead (0x0, 0xE0, 0x01308016), 0x00002000), ShiftLeft (Local0, 13))) {Stall (10)} - } - //GFX - //Store ("GFX Lane bit map = ", Debug) - //Store (procIndirectRegisterRead (0x0, 0xE0, 0x01318023), Debug) - if (LNotEqual (procIndirectRegisterRead (0x0, 0xE0, 0x01318023), 0)) { - //Store ("Before GFX 0x0131_8016 = ", Debug) - //Store (procIndirectRegisterRead (0x0, 0xE0, 0x01318016), Debug) - procIndirectRegisterRMW (0x0, 0xE0, 0x01318016, Not (0x00001000), ShiftLeft (Local0, 12)); - //Store ("After GFX 0x0131_8016 = ", Debug) - //Store (procIndirectRegisterRead (0x0, 0xE0, 0x01318016), Debug) - // Waiting for PLL changing done. - while (LNotEqual (AND(procIndirectRegisterRead (0x0, 0xE0, 0x01318016), 0x00002000), ShiftLeft (Local0, 13))) {Stall (10)} - } - - Store ("PcieAdjustPll Exit", Debug) - } - } //End of Scope(\_SB) -} //End of DefinitionBlock - - diff --git a/src/vendorcode/amd/agesa/f12/Proc/GNB/PCIe/Family/LN/F12PcieAlibSsdt.h b/src/vendorcode/amd/agesa/f12/Proc/GNB/PCIe/Family/LN/F12PcieAlibSsdt.h deleted file mode 100644 index e42f5bbec6..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/GNB/PCIe/Family/LN/F12PcieAlibSsdt.h +++ /dev/null @@ -1,856 +0,0 @@ -/** - * @file - * - * ALIB SSDT table - * - * - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: GNB - * @e $Revision:$ @e $Date:$ - * - */ -/* -***************************************************************************** -* -* Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* *************************************************************************** -* -*/ - -#ifndef _F12PCIEALIBSSDT_H_ -#define _F12PCIEALIBSSDT_H_ - -UINT8 AlibSsdt[] = { - 0x53, 0x53, 0x44, 0x54, 0x23, 0x19, 0x00, 0x00, - 0x02, 0x38, 0x41, 0x4D, 0x44, 0x00, 0x00, 0x00, - 0x41, 0x4C, 0x49, 0x42, 0x00, 0x00, 0x00, 0x00, - 0x01, 0x00, 0x00, 0x00, 0x4D, 0x53, 0x46, 0x54, - 0x00, 0x00, 0x00, 0x04, 0x10, 0x8E, 0x8F, 0x01, - 0x5C, 0x5F, 0x53, 0x42, 0x5F, 0x08, 0x41, 0x30, - 0x30, 0x31, 0x0A, 0x06, 0x08, 0x41, 0x44, 0x30, - 0x31, 0x0C, 0x00, 0x00, 0x00, 0xE0, 0x06, 0x41, - 0x44, 0x30, 0x31, 0x41, 0x30, 0x39, 0x32, 0x08, - 0x41, 0x44, 0x30, 0x37, 0x12, 0x43, 0x07, 0x08, - 0x11, 0x0D, 0x0A, 0x0A, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x11, 0x0D, - 0x0A, 0x0A, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x11, 0x0D, 0x0A, 0x0A, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x11, 0x0D, 0x0A, 0x0A, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x11, 0x0D, 0x0A, 0x0A, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x11, 0x0D, - 0x0A, 0x0A, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x11, 0x0D, 0x0A, 0x0A, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x11, 0x0D, 0x0A, 0x0A, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x06, 0x41, 0x44, 0x30, 0x37, 0x41, 0x30, 0x39, - 0x33, 0x08, 0x41, 0x30, 0x39, 0x34, 0x11, 0x04, - 0x0B, 0x00, 0x01, 0x14, 0x41, 0x05, 0x41, 0x4C, - 0x49, 0x42, 0x02, 0xA0, 0x0B, 0x93, 0x68, 0x0A, - 0x01, 0xA4, 0x41, 0x30, 0x33, 0x36, 0x69, 0xA0, - 0x0B, 0x93, 0x68, 0x0A, 0x02, 0xA4, 0x41, 0x30, - 0x33, 0x38, 0x69, 0xA0, 0x0B, 0x93, 0x68, 0x0A, - 0x03, 0xA4, 0x41, 0x30, 0x34, 0x39, 0x69, 0xA0, - 0x0B, 0x93, 0x68, 0x0A, 0x04, 0xA4, 0x41, 0x30, - 0x37, 0x34, 0x69, 0xA0, 0x0A, 0x93, 0x68, 0x0A, - 0x05, 0xA4, 0x41, 0x30, 0x39, 0x35, 0xA0, 0x0B, - 0x93, 0x68, 0x0A, 0x06, 0xA4, 0x41, 0x30, 0x37, - 0x38, 0x69, 0xA4, 0x0A, 0x00, 0x14, 0x09, 0x41, - 0x30, 0x39, 0x35, 0x08, 0xA4, 0x0A, 0x00, 0x14, - 0x31, 0x41, 0x30, 0x30, 0x38, 0x0A, 0x72, 0x41, - 0x30, 0x39, 0x32, 0x79, 0x68, 0x0A, 0x0C, 0x00, - 0x60, 0x72, 0x69, 0x60, 0x60, 0x5B, 0x80, 0x41, - 0x30, 0x39, 0x36, 0x00, 0x60, 0x0A, 0x04, 0x5B, - 0x81, 0x0B, 0x41, 0x30, 0x39, 0x36, 0x03, 0x41, - 0x30, 0x39, 0x37, 0x20, 0xA4, 0x41, 0x30, 0x39, - 0x37, 0x14, 0x32, 0x41, 0x30, 0x30, 0x39, 0x0B, - 0x72, 0x41, 0x30, 0x39, 0x32, 0x79, 0x68, 0x0A, - 0x0C, 0x00, 0x60, 0x72, 0x69, 0x60, 0x60, 0x5B, - 0x80, 0x41, 0x30, 0x39, 0x36, 0x00, 0x60, 0x0A, - 0x04, 0x5B, 0x81, 0x0B, 0x41, 0x30, 0x39, 0x36, - 0x03, 0x41, 0x30, 0x39, 0x37, 0x20, 0x70, 0x6A, - 0x41, 0x30, 0x39, 0x37, 0x14, 0x1C, 0x41, 0x30, - 0x35, 0x39, 0x0C, 0x70, 0x41, 0x30, 0x30, 0x38, - 0x68, 0x69, 0x60, 0x7D, 0x7B, 0x60, 0x6A, 0x00, - 0x6B, 0x60, 0x41, 0x30, 0x30, 0x39, 0x68, 0x69, - 0x60, 0x5B, 0x01, 0x41, 0x30, 0x39, 0x38, 0x00, - 0x14, 0x32, 0x41, 0x30, 0x36, 0x30, 0x02, 0x5B, - 0x23, 0x41, 0x30, 0x39, 0x38, 0xFF, 0xFF, 0x70, - 0x79, 0x72, 0x68, 0x0A, 0x02, 0x00, 0x0A, 0x03, - 0x00, 0x60, 0x41, 0x30, 0x30, 0x39, 0x60, 0x0A, - 0xE0, 0x69, 0x70, 0x41, 0x30, 0x30, 0x38, 0x60, - 0x0A, 0xE4, 0x60, 0x5B, 0x27, 0x41, 0x30, 0x39, - 0x38, 0xA4, 0x60, 0x14, 0x2F, 0x41, 0x30, 0x39, - 0x39, 0x03, 0x5B, 0x23, 0x41, 0x30, 0x39, 0x38, - 0xFF, 0xFF, 0x70, 0x79, 0x72, 0x68, 0x0A, 0x02, - 0x00, 0x0A, 0x03, 0x00, 0x60, 0x41, 0x30, 0x30, - 0x39, 0x60, 0x0A, 0xE0, 0x69, 0x41, 0x30, 0x30, - 0x39, 0x60, 0x0A, 0xE4, 0x6A, 0x5B, 0x27, 0x41, - 0x30, 0x39, 0x38, 0x14, 0x1C, 0x41, 0x30, 0x35, - 0x37, 0x04, 0x70, 0x41, 0x30, 0x36, 0x30, 0x68, - 0x69, 0x60, 0x7D, 0x7B, 0x60, 0x6A, 0x00, 0x6B, - 0x60, 0x41, 0x30, 0x39, 0x39, 0x68, 0x69, 0x60, - 0x5B, 0x01, 0x41, 0x31, 0x30, 0x30, 0x00, 0x14, - 0x29, 0x41, 0x30, 0x31, 0x36, 0x03, 0x5B, 0x23, - 0x41, 0x31, 0x30, 0x30, 0xFF, 0xFF, 0x41, 0x30, - 0x30, 0x39, 0x68, 0x69, 0x6A, 0x70, 0x41, 0x30, - 0x30, 0x38, 0x68, 0x72, 0x69, 0x0A, 0x04, 0x00, - 0x60, 0x5B, 0x27, 0x41, 0x31, 0x30, 0x30, 0xA4, - 0x60, 0x14, 0x26, 0x41, 0x30, 0x35, 0x30, 0x04, - 0x5B, 0x23, 0x41, 0x31, 0x30, 0x30, 0xFF, 0xFF, - 0x41, 0x30, 0x30, 0x39, 0x68, 0x69, 0x6A, 0x41, - 0x30, 0x30, 0x39, 0x68, 0x72, 0x69, 0x0A, 0x04, - 0x00, 0x6B, 0x5B, 0x27, 0x41, 0x31, 0x30, 0x30, - 0x14, 0x1E, 0x41, 0x30, 0x31, 0x37, 0x05, 0x70, - 0x41, 0x30, 0x31, 0x36, 0x68, 0x69, 0x6A, 0x60, - 0x7D, 0x7B, 0x60, 0x6B, 0x00, 0x6C, 0x60, 0x41, - 0x30, 0x35, 0x30, 0x68, 0x69, 0x6A, 0x60, 0x14, - 0x0F, 0x41, 0x30, 0x38, 0x32, 0x01, 0xA4, 0x83, - 0x88, 0x41, 0x30, 0x39, 0x33, 0x68, 0x00, 0x14, - 0x42, 0x05, 0x41, 0x30, 0x36, 0x36, 0x02, 0x70, - 0x0A, 0x34, 0x61, 0xA0, 0x11, 0x93, 0x41, 0x30, - 0x30, 0x38, 0x68, 0x0A, 0x00, 0x0C, 0xFF, 0xFF, - 0xFF, 0xFF, 0xA4, 0x0A, 0x00, 0x70, 0x0A, 0x01, - 0x60, 0xA2, 0x2E, 0x93, 0x60, 0x0A, 0x01, 0x70, - 0x7B, 0x41, 0x30, 0x30, 0x38, 0x68, 0x61, 0x0A, - 0xFF, 0x00, 0x61, 0xA0, 0x06, 0x93, 0x61, 0x0A, - 0x00, 0xA5, 0xA0, 0x11, 0x93, 0x7B, 0x41, 0x30, - 0x30, 0x38, 0x68, 0x61, 0x0A, 0xFF, 0x00, 0x69, - 0x70, 0x0A, 0x00, 0x60, 0xA1, 0x03, 0x75, 0x61, - 0xA4, 0x61, 0x14, 0x47, 0x09, 0x41, 0x30, 0x36, - 0x35, 0x0A, 0x5B, 0x80, 0x50, 0x4D, 0x49, 0x4F, - 0x01, 0x0B, 0xD6, 0x0C, 0x0A, 0x02, 0x5B, 0x81, - 0x10, 0x50, 0x4D, 0x49, 0x4F, 0x01, 0x50, 0x4D, - 0x52, 0x49, 0x08, 0x50, 0x4D, 0x52, 0x44, 0x08, - 0x5B, 0x86, 0x12, 0x50, 0x4D, 0x52, 0x49, 0x50, - 0x4D, 0x52, 0x44, 0x01, 0x00, 0x40, 0x70, 0x41, - 0x42, 0x41, 0x52, 0x20, 0x5B, 0x80, 0x41, 0x43, - 0x46, 0x47, 0x01, 0x41, 0x42, 0x41, 0x52, 0x0A, - 0x08, 0x5B, 0x81, 0x10, 0x41, 0x43, 0x46, 0x47, - 0x03, 0x41, 0x42, 0x49, 0x58, 0x20, 0x41, 0x42, - 0x44, 0x41, 0x20, 0x70, 0x0A, 0x00, 0x60, 0xA0, - 0x17, 0x93, 0x69, 0x0A, 0x00, 0x70, 0x0C, 0x68, - 0x00, 0x00, 0x80, 0x41, 0x42, 0x49, 0x58, 0x70, - 0x41, 0x42, 0x44, 0x41, 0x60, 0xA4, 0x60, 0xA1, - 0x22, 0x70, 0x0C, 0x68, 0x00, 0x00, 0x80, 0x41, - 0x42, 0x49, 0x58, 0x70, 0x41, 0x42, 0x44, 0x41, - 0x60, 0x7D, 0x7B, 0x60, 0x0C, 0xFC, 0xFF, 0xFF, - 0xFF, 0x00, 0x68, 0x60, 0x70, 0x60, 0x41, 0x42, - 0x44, 0x41, 0x14, 0x48, 0x05, 0x41, 0x30, 0x38, - 0x38, 0x01, 0x70, 0x41, 0x30, 0x31, 0x36, 0x0A, - 0x00, 0x0A, 0x60, 0x0A, 0xCD, 0x60, 0x75, 0x68, - 0x7D, 0x7B, 0x60, 0x0C, 0xFF, 0xFF, 0xFF, 0xFE, - 0x00, 0x7B, 0x80, 0x7B, 0x60, 0x0C, 0x00, 0x00, - 0x00, 0x01, 0x00, 0x00, 0x0C, 0x00, 0x00, 0x00, - 0x01, 0x00, 0x60, 0x7D, 0x7B, 0x60, 0x0C, 0xFF, - 0xFF, 0x00, 0xFD, 0x00, 0x79, 0x68, 0x0A, 0x10, - 0x00, 0x60, 0x41, 0x30, 0x35, 0x30, 0x0A, 0x00, - 0x0A, 0x60, 0x0A, 0xCD, 0x60, 0x70, 0x41, 0x30, - 0x31, 0x36, 0x0A, 0x00, 0x0A, 0x60, 0x0A, 0xCE, - 0x60, 0xA4, 0x60, 0x14, 0x47, 0x0A, 0x41, 0x30, - 0x38, 0x39, 0x03, 0x70, 0x41, 0x30, 0x31, 0x36, - 0x0A, 0x00, 0x0A, 0x60, 0x0A, 0xCD, 0x60, 0x70, - 0x7B, 0x69, 0x0B, 0xFF, 0xFF, 0x00, 0x61, 0x7D, - 0x7B, 0x60, 0x0C, 0xFF, 0xFF, 0xFF, 0xFE, 0x00, - 0x7B, 0x80, 0x7B, 0x60, 0x0C, 0x00, 0x00, 0x00, - 0x01, 0x00, 0x00, 0x0C, 0x00, 0x00, 0x00, 0x01, - 0x00, 0x60, 0x7D, 0x7B, 0x60, 0x0C, 0x00, 0x00, - 0x00, 0xFD, 0x00, 0x79, 0x68, 0x0A, 0x10, 0x00, - 0x60, 0x7D, 0x60, 0x0C, 0x00, 0x00, 0x00, 0x02, - 0x60, 0x7D, 0x60, 0x61, 0x60, 0x41, 0x30, 0x35, - 0x30, 0x0A, 0x00, 0x0A, 0x60, 0x0A, 0xCD, 0x60, - 0xA0, 0x4A, 0x04, 0x93, 0x6A, 0x0A, 0x01, 0x70, - 0x7A, 0x69, 0x0A, 0x10, 0x00, 0x61, 0x7D, 0x7B, - 0x60, 0x0C, 0xFF, 0xFF, 0xFF, 0xFE, 0x00, 0x7B, - 0x80, 0x7B, 0x60, 0x0C, 0x00, 0x00, 0x00, 0x01, - 0x00, 0x00, 0x0C, 0x00, 0x00, 0x00, 0x01, 0x00, - 0x60, 0x7D, 0x7B, 0x60, 0x0C, 0x00, 0x00, 0x00, - 0xFF, 0x00, 0x79, 0x72, 0x68, 0x0A, 0x01, 0x00, - 0x0A, 0x10, 0x00, 0x60, 0x7D, 0x60, 0x61, 0x60, - 0x41, 0x30, 0x35, 0x30, 0x0A, 0x00, 0x0A, 0x60, - 0x0A, 0xCD, 0x60, 0x14, 0x4F, 0x04, 0x41, 0x30, - 0x31, 0x31, 0x02, 0x7D, 0x79, 0x68, 0x0A, 0x03, - 0x00, 0x0A, 0x01, 0x60, 0x41, 0x30, 0x38, 0x39, - 0x0A, 0x03, 0x60, 0x0A, 0x01, 0xA0, 0x15, 0x90, - 0x69, 0x0A, 0x01, 0xA2, 0x0F, 0x92, 0x93, 0x7B, - 0x41, 0x30, 0x38, 0x38, 0x0A, 0x03, 0x0A, 0x02, - 0x00, 0x0A, 0x02, 0xA0, 0x15, 0x90, 0x69, 0x0A, - 0x02, 0xA2, 0x0F, 0x92, 0x93, 0x7B, 0x41, 0x30, - 0x38, 0x38, 0x0A, 0x03, 0x0A, 0x04, 0x00, 0x0A, - 0x04, 0x41, 0x30, 0x38, 0x39, 0x0A, 0x03, 0x0A, - 0x00, 0x0A, 0x01, 0x14, 0x18, 0x41, 0x30, 0x31, - 0x30, 0x02, 0x41, 0x30, 0x38, 0x39, 0x0A, 0x0B, - 0x68, 0x0A, 0x00, 0x41, 0x30, 0x38, 0x39, 0x0A, - 0x05, 0x69, 0x0A, 0x01, 0x14, 0x19, 0x41, 0x30, - 0x30, 0x37, 0x01, 0x41, 0x30, 0x38, 0x39, 0x0A, - 0x0B, 0x68, 0x0A, 0x00, 0x70, 0x41, 0x30, 0x38, - 0x38, 0x0A, 0x05, 0x60, 0xA4, 0x60, 0x14, 0x49, - 0x07, 0x41, 0x30, 0x39, 0x30, 0x01, 0x70, 0x7D, - 0x7B, 0x68, 0x0A, 0xFF, 0x00, 0x0C, 0x00, 0x50, - 0x86, 0x01, 0x00, 0x60, 0x70, 0x7D, 0x7B, 0x68, - 0x0C, 0x00, 0xFF, 0xFF, 0xFF, 0x00, 0x0A, 0x04, - 0x00, 0x61, 0x70, 0x7D, 0x79, 0x0A, 0x03, 0x0A, - 0x1E, 0x00, 0x79, 0x0A, 0x01, 0x0A, 0x12, 0x00, - 0x00, 0x62, 0x41, 0x30, 0x31, 0x30, 0x0B, 0x00, - 0x86, 0x60, 0x41, 0x30, 0x31, 0x30, 0x0B, 0x04, - 0x86, 0x61, 0x41, 0x30, 0x31, 0x30, 0x0B, 0x08, - 0x86, 0x62, 0xA0, 0x12, 0x93, 0x7A, 0x68, 0x0A, - 0x10, 0x00, 0x0B, 0x00, 0xFE, 0x41, 0x30, 0x31, - 0x31, 0x0A, 0x0D, 0x0A, 0x03, 0xA0, 0x12, 0x93, - 0x7A, 0x68, 0x0A, 0x10, 0x00, 0x0B, 0x30, 0xFE, - 0x41, 0x30, 0x31, 0x31, 0x0A, 0x0B, 0x0A, 0x03, - 0xA4, 0x41, 0x30, 0x30, 0x37, 0x0B, 0x50, 0x86, - 0x14, 0x44, 0x06, 0x41, 0x30, 0x39, 0x31, 0x02, - 0x70, 0x7D, 0x7B, 0x68, 0x0A, 0xFF, 0x00, 0x0C, - 0x00, 0x50, 0x86, 0x01, 0x00, 0x60, 0x70, 0x7D, - 0x7B, 0x68, 0x0C, 0x00, 0xFF, 0xFF, 0xFF, 0x00, - 0x0A, 0x04, 0x00, 0x61, 0x70, 0x7D, 0x79, 0x0A, - 0x03, 0x0A, 0x1E, 0x00, 0x79, 0x0A, 0x01, 0x0A, - 0x12, 0x00, 0x00, 0x62, 0x7D, 0x62, 0x79, 0x0A, - 0x01, 0x0A, 0x10, 0x00, 0x62, 0x41, 0x30, 0x31, - 0x30, 0x0B, 0x00, 0x86, 0x60, 0x41, 0x30, 0x31, - 0x30, 0x0B, 0x04, 0x86, 0x61, 0x41, 0x30, 0x31, - 0x30, 0x0B, 0x08, 0x86, 0x62, 0x41, 0x30, 0x31, - 0x30, 0x0B, 0x50, 0x86, 0x69, 0x41, 0x30, 0x31, - 0x31, 0x0A, 0x0B, 0x0A, 0x03, 0x14, 0x41, 0x07, - 0x41, 0x30, 0x35, 0x34, 0x0A, 0x70, 0x41, 0x30, - 0x31, 0x36, 0x0A, 0x00, 0x0A, 0x60, 0x0A, 0xEA, - 0x61, 0x7D, 0x61, 0x0A, 0x02, 0x61, 0x41, 0x30, - 0x35, 0x30, 0x0A, 0x00, 0x0A, 0x60, 0x0A, 0xEA, - 0x61, 0x7B, 0x61, 0x80, 0x79, 0x0A, 0x03, 0x0A, - 0x03, 0x00, 0x00, 0x61, 0x7D, 0x61, 0x79, 0x68, - 0x0A, 0x03, 0x00, 0x61, 0x7B, 0x80, 0x61, 0x00, - 0x0A, 0x04, 0x62, 0x7D, 0x7B, 0x61, 0x80, 0x0A, - 0x04, 0x00, 0x00, 0x62, 0x61, 0x41, 0x30, 0x35, - 0x30, 0x0A, 0x00, 0x0A, 0x60, 0x0A, 0xEA, 0x61, - 0xA0, 0x1E, 0x92, 0x93, 0x69, 0x0A, 0x00, 0xA2, - 0x17, 0x92, 0x93, 0x79, 0x61, 0x0A, 0x02, 0x00, - 0x62, 0x7B, 0x41, 0x30, 0x31, 0x36, 0x0A, 0x00, - 0x0A, 0x60, 0x0A, 0xEB, 0x0A, 0x01, 0x61, 0x08, - 0x41, 0x44, 0x30, 0x32, 0x0A, 0x00, 0x06, 0x41, - 0x44, 0x30, 0x32, 0x41, 0x30, 0x31, 0x38, 0x08, - 0x41, 0x44, 0x30, 0x33, 0x0A, 0x00, 0x06, 0x41, - 0x44, 0x30, 0x33, 0x41, 0x30, 0x31, 0x39, 0x08, - 0x41, 0x44, 0x30, 0x34, 0x0A, 0x00, 0x06, 0x41, - 0x44, 0x30, 0x34, 0x41, 0x30, 0x32, 0x30, 0x08, - 0x41, 0x44, 0x30, 0x35, 0x0A, 0x00, 0x06, 0x41, - 0x44, 0x30, 0x35, 0x41, 0x30, 0x32, 0x31, 0x08, - 0x41, 0x44, 0x30, 0x36, 0x12, 0x12, 0x08, 0x0A, - 0x00, 0x0A, 0x00, 0x0A, 0x00, 0x0A, 0x00, 0x0A, - 0x00, 0x0A, 0x00, 0x0A, 0x00, 0x0A, 0x00, 0x06, - 0x41, 0x44, 0x30, 0x36, 0x41, 0x30, 0x32, 0x32, - 0x08, 0x41, 0x44, 0x30, 0x38, 0x12, 0x12, 0x08, - 0x0A, 0x00, 0x0A, 0x00, 0x0A, 0x00, 0x0A, 0x00, - 0x0A, 0x00, 0x0A, 0x00, 0x0A, 0x00, 0x0A, 0x00, - 0x06, 0x41, 0x44, 0x30, 0x38, 0x41, 0x30, 0x32, - 0x33, 0x08, 0x41, 0x30, 0x32, 0x34, 0x0A, 0x00, - 0x08, 0x41, 0x30, 0x32, 0x35, 0x0A, 0x00, 0x08, - 0x41, 0x30, 0x32, 0x36, 0x0A, 0x01, 0x08, 0x41, - 0x30, 0x32, 0x37, 0x12, 0x12, 0x08, 0x0A, 0x00, - 0x0A, 0x00, 0x0A, 0x00, 0x0A, 0x00, 0x0A, 0x00, - 0x0A, 0x00, 0x0A, 0x00, 0x0A, 0x00, 0x08, 0x41, - 0x30, 0x32, 0x38, 0x12, 0x12, 0x08, 0x0A, 0x00, - 0x0A, 0x00, 0x0A, 0x00, 0x0A, 0x00, 0x0A, 0x00, - 0x0A, 0x00, 0x0A, 0x00, 0x0A, 0x00, 0x08, 0x41, - 0x30, 0x32, 0x39, 0x12, 0x12, 0x08, 0x0A, 0x00, - 0x0A, 0x00, 0x0A, 0x00, 0x0A, 0x00, 0x0A, 0x00, - 0x0A, 0x00, 0x0A, 0x00, 0x0A, 0x00, 0x08, 0x41, - 0x44, 0x30, 0x39, 0x12, 0x12, 0x08, 0x0A, 0x00, - 0x0A, 0x00, 0x0A, 0x00, 0x0A, 0x00, 0x0A, 0x00, - 0x0A, 0x00, 0x0A, 0x00, 0x0A, 0x00, 0x06, 0x41, - 0x44, 0x30, 0x39, 0x41, 0x30, 0x33, 0x30, 0x08, - 0x41, 0x30, 0x33, 0x31, 0x12, 0x12, 0x08, 0x0A, - 0x01, 0x0A, 0x01, 0x0A, 0x01, 0x0A, 0x01, 0x0A, - 0x01, 0x0A, 0x01, 0x0A, 0x01, 0x0A, 0x01, 0x08, - 0x41, 0x30, 0x33, 0x32, 0x12, 0x12, 0x08, 0x0A, - 0x00, 0x0A, 0x00, 0x0A, 0x00, 0x0A, 0x00, 0x0A, - 0x00, 0x0A, 0x00, 0x0A, 0x00, 0x0A, 0x00, 0x08, - 0x41, 0x30, 0x33, 0x34, 0x0A, 0x00, 0x08, 0x41, - 0x44, 0x31, 0x30, 0x12, 0x0A, 0x04, 0x0A, 0x00, - 0x0A, 0x00, 0x0A, 0x00, 0x0A, 0x00, 0x06, 0x41, - 0x44, 0x31, 0x30, 0x41, 0x30, 0x33, 0x35, 0x14, - 0x4A, 0x09, 0x41, 0x30, 0x33, 0x36, 0x09, 0x70, - 0x83, 0x88, 0x68, 0x0A, 0x02, 0x00, 0x61, 0x70, - 0x41, 0x30, 0x31, 0x33, 0x60, 0x70, 0x61, 0x41, - 0x30, 0x32, 0x35, 0x7D, 0x79, 0x0A, 0x01, 0x0A, - 0x05, 0x00, 0x79, 0x0A, 0x01, 0x0A, 0x06, 0x00, - 0x62, 0x7D, 0x79, 0x41, 0x30, 0x32, 0x35, 0x0A, - 0x05, 0x00, 0x79, 0x41, 0x30, 0x32, 0x36, 0x0A, - 0x06, 0x00, 0x63, 0x41, 0x30, 0x31, 0x37, 0x0A, - 0x00, 0x0A, 0x60, 0x0A, 0xF4, 0x80, 0x62, 0x00, - 0x7B, 0x62, 0x63, 0x00, 0xA0, 0x07, 0x93, 0x61, - 0x60, 0xA4, 0x0A, 0x00, 0x41, 0x30, 0x30, 0x36, - 0x41, 0x30, 0x32, 0x35, 0xA0, 0x14, 0x93, 0x41, - 0x30, 0x31, 0x38, 0x0A, 0x04, 0x41, 0x30, 0x31, - 0x32, 0x0A, 0x01, 0x41, 0x30, 0x31, 0x34, 0x0A, - 0x01, 0xA0, 0x15, 0x91, 0x92, 0x94, 0x41, 0x30, - 0x31, 0x38, 0x0A, 0x01, 0x92, 0x95, 0x41, 0x30, - 0x31, 0x38, 0x0A, 0x04, 0xA4, 0x0A, 0x00, 0xA0, - 0x0B, 0x93, 0x41, 0x30, 0x32, 0x34, 0x0A, 0x00, - 0xA4, 0x0A, 0x00, 0x41, 0x30, 0x33, 0x37, 0xA4, - 0x0A, 0x00, 0x14, 0x24, 0x41, 0x30, 0x33, 0x38, - 0x01, 0x70, 0x41, 0x30, 0x33, 0x39, 0x68, 0x67, - 0x70, 0x83, 0x88, 0x67, 0x0A, 0x02, 0x00, 0x60, - 0xA0, 0x08, 0x92, 0x93, 0x60, 0x0A, 0x02, 0xA4, - 0x67, 0x41, 0x30, 0x33, 0x37, 0xA4, 0x67, 0x14, - 0x4E, 0x1B, 0x41, 0x30, 0x33, 0x39, 0x01, 0x08, - 0x41, 0x30, 0x34, 0x30, 0x0A, 0x00, 0x70, 0x0A, - 0x00, 0x41, 0x30, 0x33, 0x34, 0x70, 0x11, 0x03, - 0x0A, 0x0A, 0x67, 0x8B, 0x67, 0x0A, 0x00, 0x41, - 0x30, 0x34, 0x31, 0x70, 0x0A, 0x03, 0x41, 0x30, - 0x34, 0x31, 0x8C, 0x67, 0x0A, 0x02, 0x41, 0x30, - 0x34, 0x32, 0x70, 0x0A, 0x01, 0x41, 0x30, 0x34, - 0x32, 0xA0, 0x14, 0x91, 0x92, 0x94, 0x41, 0x30, - 0x31, 0x38, 0x0A, 0x01, 0x92, 0x95, 0x41, 0x30, - 0x31, 0x38, 0x0A, 0x04, 0xA4, 0x67, 0xA0, 0x0A, - 0x93, 0x41, 0x30, 0x32, 0x34, 0x0A, 0x00, 0xA4, - 0x67, 0x8B, 0x68, 0x0A, 0x02, 0x41, 0x30, 0x34, - 0x33, 0x8B, 0x68, 0x0A, 0x04, 0x41, 0x30, 0x34, - 0x34, 0x8B, 0x68, 0x0A, 0x06, 0x41, 0x30, 0x34, - 0x35, 0x8C, 0x68, 0x0A, 0x08, 0x41, 0x30, 0x34, - 0x36, 0x8C, 0x68, 0x0A, 0x09, 0x41, 0x30, 0x34, - 0x37, 0x7B, 0x7A, 0x41, 0x30, 0x34, 0x33, 0x0A, - 0x08, 0x00, 0x0A, 0xFF, 0x41, 0x30, 0x34, 0x30, - 0xA2, 0x47, 0x05, 0x92, 0x94, 0x41, 0x30, 0x33, - 0x34, 0x41, 0x30, 0x30, 0x31, 0xA0, 0x45, 0x04, - 0x93, 0x41, 0x30, 0x34, 0x38, 0x41, 0x30, 0x33, - 0x34, 0x0A, 0x01, 0x70, 0x41, 0x30, 0x30, 0x38, - 0x79, 0x72, 0x41, 0x30, 0x33, 0x34, 0x0A, 0x02, - 0x00, 0x0A, 0x03, 0x00, 0x0A, 0x18, 0x61, 0x7B, - 0x7A, 0x61, 0x0A, 0x10, 0x00, 0x0A, 0xFF, 0x62, - 0x7B, 0x7A, 0x61, 0x0A, 0x08, 0x00, 0x0A, 0xFF, - 0x61, 0xA0, 0x11, 0x90, 0x92, 0x95, 0x41, 0x30, - 0x34, 0x30, 0x61, 0x92, 0x94, 0x41, 0x30, 0x34, - 0x30, 0x62, 0xA5, 0x75, 0x41, 0x30, 0x33, 0x34, - 0xA0, 0x0C, 0x94, 0x41, 0x30, 0x33, 0x34, 0x41, - 0x30, 0x30, 0x31, 0xA4, 0x67, 0xA0, 0x1E, 0x93, - 0x83, 0x88, 0x41, 0x30, 0x32, 0x37, 0x41, 0x30, - 0x33, 0x34, 0x00, 0x0A, 0x00, 0x70, 0x41, 0x30, - 0x34, 0x33, 0x88, 0x41, 0x30, 0x32, 0x37, 0x41, - 0x30, 0x33, 0x34, 0x00, 0xA1, 0x16, 0xA0, 0x14, - 0x92, 0x93, 0x83, 0x88, 0x41, 0x30, 0x32, 0x37, - 0x41, 0x30, 0x33, 0x34, 0x00, 0x41, 0x30, 0x34, - 0x33, 0xA4, 0x67, 0x70, 0x0A, 0x00, 0x88, 0x41, - 0x30, 0x33, 0x32, 0x41, 0x30, 0x33, 0x34, 0x00, - 0xA0, 0x15, 0x93, 0x41, 0x30, 0x34, 0x37, 0x0A, - 0x00, 0x70, 0x0A, 0x00, 0x88, 0x41, 0x30, 0x32, - 0x37, 0x41, 0x30, 0x33, 0x34, 0x00, 0xA0, 0x15, - 0x93, 0x41, 0x30, 0x34, 0x37, 0x0A, 0x01, 0x70, - 0x0A, 0x01, 0x88, 0x41, 0x30, 0x33, 0x32, 0x41, - 0x30, 0x33, 0x34, 0x00, 0xA0, 0x15, 0x93, 0x41, - 0x30, 0x34, 0x37, 0x0A, 0x02, 0x70, 0x0A, 0x01, - 0x88, 0x41, 0x30, 0x32, 0x39, 0x41, 0x30, 0x33, - 0x34, 0x00, 0xA0, 0x15, 0x93, 0x41, 0x30, 0x34, - 0x37, 0x0A, 0x03, 0x70, 0x0A, 0x02, 0x88, 0x41, - 0x30, 0x32, 0x39, 0x41, 0x30, 0x33, 0x34, 0x00, - 0xA0, 0x24, 0x93, 0x7B, 0x41, 0x30, 0x34, 0x34, - 0x41, 0x30, 0x34, 0x35, 0x00, 0x0A, 0x01, 0x70, - 0x83, 0x88, 0x41, 0x30, 0x32, 0x32, 0x41, 0x30, - 0x33, 0x34, 0x00, 0x88, 0x41, 0x30, 0x32, 0x39, - 0x41, 0x30, 0x33, 0x34, 0x00, 0x70, 0x0A, 0x02, - 0x41, 0x30, 0x34, 0x32, 0xA4, 0x67, 0x14, 0x19, - 0x41, 0x30, 0x34, 0x38, 0x09, 0xA0, 0x0F, 0x93, - 0x83, 0x88, 0x41, 0x30, 0x32, 0x32, 0x68, 0x00, - 0x0A, 0x00, 0xA4, 0x0A, 0x00, 0xA4, 0x0A, 0x01, - 0x14, 0x43, 0x13, 0x41, 0x30, 0x34, 0x39, 0x09, - 0x70, 0x11, 0x04, 0x0B, 0x00, 0x01, 0x67, 0x70, - 0x0A, 0x03, 0x88, 0x67, 0x0A, 0x00, 0x00, 0x70, - 0x0A, 0x00, 0x88, 0x67, 0x0A, 0x01, 0x00, 0x70, - 0x0A, 0x00, 0x88, 0x67, 0x0A, 0x02, 0x00, 0x70, - 0x83, 0x88, 0x68, 0x0A, 0x02, 0x00, 0x41, 0x30, - 0x32, 0x34, 0x70, 0x41, 0x30, 0x31, 0x36, 0x0A, - 0x00, 0x0A, 0x60, 0x0A, 0xF4, 0x60, 0xA0, 0x19, - 0x93, 0x41, 0x30, 0x32, 0x34, 0x0A, 0x01, 0xA0, - 0x0B, 0x93, 0x7B, 0x60, 0x0A, 0x01, 0x00, 0x0A, - 0x01, 0xA4, 0x67, 0x7D, 0x60, 0x0A, 0x01, 0x60, - 0xA0, 0x1B, 0x93, 0x41, 0x30, 0x32, 0x34, 0x0A, - 0x00, 0xA0, 0x0B, 0x93, 0x7B, 0x60, 0x0A, 0x01, - 0x00, 0x0A, 0x00, 0xA4, 0x67, 0x7B, 0x60, 0x80, - 0x0A, 0x01, 0x00, 0x60, 0x7D, 0x60, 0x79, 0x41, - 0x30, 0x31, 0x38, 0x0A, 0x01, 0x00, 0x60, 0x41, - 0x30, 0x35, 0x30, 0x0A, 0x00, 0x0A, 0x60, 0x0A, - 0xF4, 0x60, 0x41, 0x30, 0x35, 0x31, 0x71, 0x41, - 0x30, 0x32, 0x38, 0x71, 0x41, 0x30, 0x32, 0x37, - 0x41, 0x30, 0x30, 0x36, 0x41, 0x30, 0x32, 0x35, - 0xA0, 0x14, 0x93, 0x41, 0x30, 0x31, 0x38, 0x0A, - 0x04, 0x41, 0x30, 0x31, 0x32, 0x0A, 0x01, 0x41, - 0x30, 0x31, 0x34, 0x0A, 0x01, 0xA0, 0x4C, 0x07, - 0x90, 0x94, 0x41, 0x30, 0x31, 0x38, 0x0A, 0x01, - 0x95, 0x41, 0x30, 0x31, 0x38, 0x0A, 0x04, 0xA0, - 0x46, 0x05, 0x93, 0x41, 0x30, 0x31, 0x38, 0x0A, - 0x02, 0x41, 0x30, 0x35, 0x31, 0x71, 0x41, 0x30, - 0x32, 0x32, 0x71, 0x41, 0x30, 0x33, 0x30, 0x70, - 0x0A, 0x00, 0x41, 0x30, 0x33, 0x34, 0xA2, 0x37, - 0x92, 0x94, 0x41, 0x30, 0x33, 0x34, 0x41, 0x30, - 0x30, 0x31, 0xA0, 0x26, 0x92, 0x93, 0x83, 0x88, - 0x41, 0x30, 0x32, 0x33, 0x41, 0x30, 0x33, 0x34, - 0x00, 0x0A, 0x00, 0x70, 0x83, 0x88, 0x41, 0x30, - 0x32, 0x33, 0x41, 0x30, 0x33, 0x34, 0x00, 0x88, - 0x41, 0x30, 0x33, 0x30, 0x41, 0x30, 0x33, 0x34, - 0x00, 0x75, 0x41, 0x30, 0x33, 0x34, 0xA1, 0x0F, - 0x41, 0x30, 0x35, 0x31, 0x71, 0x41, 0x30, 0x33, - 0x31, 0x71, 0x41, 0x30, 0x33, 0x30, 0x41, 0x30, - 0x33, 0x37, 0xA4, 0x67, 0x08, 0x41, 0x30, 0x35, - 0x32, 0x12, 0x12, 0x08, 0x0A, 0x00, 0x0A, 0x00, - 0x0A, 0x00, 0x0A, 0x00, 0x0A, 0x00, 0x0A, 0x00, - 0x0A, 0x00, 0x0A, 0x00, 0x14, 0x42, 0x12, 0x41, - 0x30, 0x33, 0x37, 0x08, 0x70, 0x0A, 0x00, 0x41, - 0x30, 0x33, 0x34, 0x41, 0x30, 0x35, 0x31, 0x71, - 0x41, 0x30, 0x33, 0x31, 0x71, 0x41, 0x30, 0x35, - 0x32, 0xA2, 0x30, 0x92, 0x94, 0x41, 0x30, 0x33, - 0x34, 0x41, 0x30, 0x30, 0x31, 0xA0, 0x1F, 0x93, - 0x41, 0x30, 0x34, 0x38, 0x41, 0x30, 0x33, 0x34, - 0x0A, 0x01, 0x70, 0x41, 0x30, 0x35, 0x33, 0x41, - 0x30, 0x33, 0x34, 0x88, 0x41, 0x30, 0x35, 0x32, - 0x41, 0x30, 0x33, 0x34, 0x00, 0x75, 0x41, 0x30, - 0x33, 0x34, 0xA0, 0x1F, 0x92, 0x93, 0x89, 0x41, - 0x30, 0x33, 0x32, 0x01, 0x0A, 0x01, 0x00, 0x0A, - 0x00, 0x0A, 0x00, 0xFF, 0x41, 0x30, 0x35, 0x31, - 0x71, 0x41, 0x30, 0x33, 0x31, 0x71, 0x41, 0x30, - 0x35, 0x32, 0xA0, 0x27, 0x92, 0x93, 0x89, 0x41, - 0x30, 0x35, 0x32, 0x01, 0x0A, 0x02, 0x00, 0x0A, - 0x00, 0x0A, 0x00, 0xFF, 0x41, 0x30, 0x31, 0x34, - 0x0A, 0x02, 0x41, 0x30, 0x35, 0x34, 0x41, 0x30, - 0x31, 0x39, 0x0A, 0x01, 0x41, 0x30, 0x31, 0x32, - 0x0A, 0x02, 0x70, 0x0A, 0x00, 0x41, 0x30, 0x33, - 0x34, 0xA2, 0x4E, 0x05, 0x92, 0x94, 0x41, 0x30, - 0x33, 0x34, 0x41, 0x30, 0x30, 0x31, 0xA0, 0x12, - 0x93, 0x41, 0x30, 0x34, 0x38, 0x41, 0x30, 0x33, - 0x34, 0x0A, 0x00, 0x75, 0x41, 0x30, 0x33, 0x34, - 0x9F, 0x70, 0x83, 0x88, 0x41, 0x30, 0x33, 0x30, - 0x41, 0x30, 0x33, 0x34, 0x00, 0x60, 0x70, 0x83, - 0x88, 0x41, 0x30, 0x35, 0x32, 0x41, 0x30, 0x33, - 0x34, 0x00, 0x62, 0xA0, 0x0A, 0x93, 0x60, 0x62, - 0x75, 0x41, 0x30, 0x33, 0x34, 0x9F, 0x70, 0x62, - 0x88, 0x41, 0x30, 0x33, 0x30, 0x41, 0x30, 0x33, - 0x34, 0x00, 0x41, 0x30, 0x35, 0x35, 0x41, 0x30, - 0x33, 0x34, 0x62, 0x75, 0x41, 0x30, 0x33, 0x34, - 0xA0, 0x26, 0x93, 0x89, 0x41, 0x30, 0x35, 0x32, - 0x01, 0x0A, 0x02, 0x00, 0x0A, 0x00, 0x0A, 0x00, - 0xFF, 0x41, 0x30, 0x31, 0x32, 0x0A, 0x01, 0x41, - 0x30, 0x35, 0x34, 0x41, 0x30, 0x32, 0x30, 0x0A, - 0x00, 0x41, 0x30, 0x31, 0x34, 0x0A, 0x01, 0x14, - 0x43, 0x05, 0x41, 0x30, 0x35, 0x33, 0x01, 0x70, - 0x0A, 0x02, 0x60, 0xA0, 0x39, 0x93, 0x83, 0x88, - 0x41, 0x30, 0x32, 0x37, 0x68, 0x00, 0x0A, 0x00, - 0xA0, 0x14, 0x91, 0x93, 0x41, 0x30, 0x31, 0x33, - 0x0A, 0x01, 0x93, 0x41, 0x30, 0x31, 0x38, 0x0A, - 0x03, 0x70, 0x0A, 0x01, 0x60, 0xA0, 0x17, 0x92, - 0x93, 0x83, 0x88, 0x41, 0x30, 0x32, 0x33, 0x68, - 0x00, 0x0A, 0x00, 0x70, 0x83, 0x88, 0x41, 0x30, - 0x32, 0x33, 0x68, 0x00, 0x60, 0xA1, 0x0B, 0x70, - 0x83, 0x88, 0x41, 0x30, 0x32, 0x39, 0x68, 0x00, - 0x60, 0xA4, 0x60, 0x14, 0x43, 0x0E, 0x41, 0x30, - 0x35, 0x35, 0x02, 0xA0, 0x15, 0x93, 0x68, 0x0A, - 0x06, 0x41, 0x30, 0x31, 0x37, 0x0A, 0x00, 0x0A, - 0x60, 0x0A, 0x80, 0x80, 0x0A, 0x40, 0x00, 0x0A, - 0x40, 0x41, 0x30, 0x35, 0x36, 0x68, 0x69, 0xA0, - 0x1B, 0x92, 0x93, 0x83, 0x88, 0x41, 0x30, 0x32, - 0x37, 0x68, 0x00, 0x0A, 0x00, 0x41, 0x30, 0x35, - 0x37, 0x68, 0x0A, 0xA1, 0x80, 0x0B, 0x00, 0x10, - 0x00, 0x0A, 0x00, 0xA1, 0x10, 0x41, 0x30, 0x35, - 0x37, 0x68, 0x0A, 0xA1, 0x80, 0x0B, 0x00, 0x10, - 0x00, 0x0B, 0x00, 0x10, 0x70, 0x79, 0x72, 0x68, - 0x0A, 0x02, 0x00, 0x0A, 0x03, 0x00, 0x61, 0x7B, - 0x41, 0x30, 0x30, 0x38, 0x61, 0x0A, 0x70, 0x0C, - 0x00, 0x00, 0x40, 0x00, 0x63, 0xA0, 0x41, 0x06, - 0x92, 0x93, 0x63, 0x0A, 0x00, 0x41, 0x30, 0x35, - 0x38, 0x68, 0x70, 0x0A, 0x01, 0x62, 0xA2, 0x4B, - 0x04, 0x62, 0x41, 0x30, 0x35, 0x39, 0x61, 0x0A, - 0x68, 0x80, 0x0A, 0x00, 0x00, 0x0A, 0x20, 0x5B, - 0x22, 0x0A, 0x1E, 0xA2, 0x13, 0x7B, 0x41, 0x30, - 0x30, 0x38, 0x61, 0x0A, 0x68, 0x0C, 0x00, 0x00, - 0x00, 0x08, 0x00, 0x5B, 0x22, 0x0A, 0x0A, 0x70, - 0x0A, 0x00, 0x62, 0xA0, 0x1E, 0x93, 0x69, 0x0A, - 0x01, 0x70, 0x41, 0x30, 0x36, 0x30, 0x68, 0x0A, - 0xA4, 0x64, 0xA0, 0x0F, 0x92, 0x93, 0x7B, 0x64, - 0x0B, 0x00, 0x08, 0x00, 0x0A, 0x00, 0x70, 0x0A, - 0x01, 0x62, 0x41, 0x30, 0x36, 0x31, 0x68, 0xA1, - 0x01, 0xA0, 0x15, 0x93, 0x68, 0x0A, 0x06, 0x41, - 0x30, 0x31, 0x37, 0x0A, 0x00, 0x0A, 0x60, 0x0A, - 0x80, 0x80, 0x0A, 0x40, 0x00, 0x0A, 0x00, 0x08, - 0x41, 0x30, 0x36, 0x32, 0x12, 0x14, 0x09, 0x0A, - 0x00, 0x0A, 0x00, 0x0A, 0x00, 0x0A, 0x00, 0x0A, - 0x00, 0x0A, 0x00, 0x0A, 0x00, 0x0A, 0x00, 0x0A, - 0x00, 0x08, 0x41, 0x30, 0x36, 0x33, 0x0A, 0x00, - 0x08, 0x41, 0x30, 0x36, 0x34, 0x0A, 0x00, 0x14, - 0x4C, 0x0E, 0x41, 0x30, 0x35, 0x38, 0x09, 0x70, - 0x0A, 0x00, 0x41, 0x30, 0x36, 0x33, 0x70, 0x0A, - 0x00, 0x41, 0x30, 0x36, 0x34, 0x70, 0x79, 0x72, - 0x68, 0x0A, 0x02, 0x00, 0x0A, 0x03, 0x00, 0x61, - 0xA0, 0x21, 0x93, 0x68, 0x0A, 0x06, 0x70, 0x41, - 0x30, 0x36, 0x35, 0x0A, 0x00, 0x0A, 0x00, 0x88, - 0x41, 0x30, 0x36, 0x32, 0x0A, 0x00, 0x00, 0x41, - 0x30, 0x36, 0x35, 0x0A, 0x00, 0x0A, 0x01, 0xA4, - 0x0A, 0x00, 0x70, 0x41, 0x30, 0x30, 0x38, 0x61, - 0x0A, 0x18, 0x63, 0x70, 0x7B, 0x7A, 0x63, 0x0A, - 0x08, 0x00, 0x0A, 0xFF, 0x00, 0x63, 0x70, 0x79, - 0x63, 0x0A, 0x08, 0x00, 0x62, 0x70, 0x41, 0x30, - 0x30, 0x38, 0x62, 0x0A, 0x0C, 0x63, 0x70, 0x7B, - 0x7A, 0x63, 0x0A, 0x10, 0x00, 0x0A, 0xFF, 0x00, - 0x63, 0xA0, 0x0E, 0x92, 0x93, 0x7B, 0x63, 0x0A, - 0x80, 0x00, 0x0A, 0x00, 0x70, 0x0A, 0x07, 0x60, - 0xA1, 0x05, 0x70, 0x0A, 0x00, 0x60, 0x70, 0x0A, - 0x00, 0x64, 0xA2, 0x41, 0x06, 0x92, 0x94, 0x64, - 0x60, 0x70, 0x41, 0x30, 0x36, 0x36, 0x72, 0x62, - 0x64, 0x00, 0x0A, 0x10, 0x41, 0x30, 0x36, 0x33, - 0xA0, 0x0B, 0x93, 0x41, 0x30, 0x36, 0x33, 0x0A, - 0x00, 0x75, 0x64, 0x9F, 0x72, 0x41, 0x30, 0x36, - 0x33, 0x0A, 0x10, 0x41, 0x30, 0x36, 0x33, 0x70, - 0x41, 0x30, 0x30, 0x38, 0x72, 0x62, 0x64, 0x00, - 0x41, 0x30, 0x36, 0x33, 0x41, 0x30, 0x36, 0x34, - 0x70, 0x7B, 0x41, 0x30, 0x36, 0x34, 0x0A, 0x03, - 0x00, 0x88, 0x41, 0x30, 0x36, 0x32, 0x64, 0x00, - 0x41, 0x30, 0x35, 0x39, 0x72, 0x62, 0x64, 0x00, - 0x41, 0x30, 0x36, 0x33, 0x80, 0x0A, 0x03, 0x00, - 0x0A, 0x00, 0x75, 0x64, 0x14, 0x43, 0x0C, 0x41, - 0x30, 0x36, 0x31, 0x09, 0x70, 0x0A, 0x00, 0x41, - 0x30, 0x36, 0x33, 0x70, 0x0A, 0x00, 0x41, 0x30, - 0x36, 0x34, 0xA0, 0x17, 0x93, 0x68, 0x0A, 0x06, - 0x41, 0x30, 0x36, 0x35, 0x83, 0x88, 0x41, 0x30, - 0x36, 0x32, 0x0A, 0x00, 0x00, 0x0A, 0x01, 0xA4, - 0x0A, 0x00, 0x70, 0x79, 0x72, 0x68, 0x0A, 0x02, - 0x00, 0x0A, 0x03, 0x00, 0x61, 0x70, 0x41, 0x30, - 0x30, 0x38, 0x61, 0x0A, 0x18, 0x63, 0x70, 0x7B, - 0x7A, 0x63, 0x0A, 0x08, 0x00, 0x0A, 0xFF, 0x00, - 0x63, 0x70, 0x79, 0x63, 0x0A, 0x08, 0x00, 0x62, - 0x70, 0x41, 0x30, 0x30, 0x38, 0x62, 0x0A, 0x0C, - 0x63, 0x70, 0x7B, 0x7A, 0x63, 0x0A, 0x10, 0x00, - 0x0A, 0xFF, 0x00, 0x63, 0xA0, 0x0E, 0x92, 0x93, - 0x7B, 0x63, 0x0A, 0x80, 0x00, 0x0A, 0x00, 0x70, - 0x0A, 0x07, 0x60, 0xA1, 0x05, 0x70, 0x0A, 0x00, - 0x60, 0x70, 0x0A, 0x00, 0x64, 0xA2, 0x42, 0x04, - 0x92, 0x94, 0x64, 0x60, 0x70, 0x41, 0x30, 0x36, - 0x36, 0x72, 0x62, 0x64, 0x00, 0x0A, 0x10, 0x41, - 0x30, 0x36, 0x33, 0xA0, 0x0B, 0x93, 0x41, 0x30, - 0x36, 0x33, 0x0A, 0x00, 0x75, 0x64, 0x9F, 0x72, - 0x41, 0x30, 0x36, 0x33, 0x0A, 0x10, 0x41, 0x30, - 0x36, 0x33, 0x41, 0x30, 0x30, 0x39, 0x72, 0x62, - 0x64, 0x00, 0x41, 0x30, 0x36, 0x33, 0x83, 0x88, - 0x41, 0x30, 0x36, 0x32, 0x64, 0x00, 0x75, 0x64, - 0x14, 0x47, 0x05, 0x41, 0x30, 0x35, 0x36, 0x02, - 0x70, 0x79, 0x72, 0x68, 0x0A, 0x02, 0x00, 0x0A, - 0x03, 0x00, 0x60, 0xA0, 0x22, 0x93, 0x69, 0x0A, - 0x01, 0x41, 0x30, 0x35, 0x39, 0x60, 0x0A, 0x88, - 0x80, 0x0A, 0x2F, 0x00, 0x0A, 0x21, 0x41, 0x30, - 0x35, 0x37, 0x68, 0x0A, 0xA4, 0x80, 0x0C, 0x01, - 0x00, 0x00, 0x20, 0x00, 0x0A, 0x00, 0xA1, 0x21, - 0x41, 0x30, 0x35, 0x37, 0x68, 0x0A, 0xA4, 0x80, - 0x0C, 0x01, 0x00, 0x00, 0x20, 0x00, 0x0C, 0x01, - 0x00, 0x00, 0x20, 0x41, 0x30, 0x35, 0x39, 0x60, - 0x0A, 0x88, 0x80, 0x0A, 0x2F, 0x00, 0x0A, 0x02, - 0x14, 0x21, 0x41, 0x30, 0x35, 0x31, 0x02, 0x70, - 0x87, 0x68, 0x61, 0x70, 0x0A, 0x00, 0x60, 0xA2, - 0x12, 0x95, 0x60, 0x61, 0x70, 0x83, 0x88, 0x83, - 0x68, 0x60, 0x00, 0x88, 0x83, 0x69, 0x60, 0x00, - 0x75, 0x60, 0x14, 0x11, 0x41, 0x30, 0x31, 0x33, - 0x00, 0xA4, 0x7B, 0x41, 0x30, 0x32, 0x35, 0x41, - 0x30, 0x32, 0x36, 0x00, 0x08, 0x41, 0x30, 0x36, - 0x37, 0x0A, 0x00, 0x08, 0x41, 0x30, 0x36, 0x38, - 0x0A, 0x00, 0x08, 0x41, 0x30, 0x36, 0x39, 0x0A, - 0x00, 0x08, 0x41, 0x30, 0x37, 0x30, 0x0A, 0x00, - 0x08, 0x41, 0x30, 0x37, 0x31, 0x0A, 0x00, 0x08, - 0x41, 0x30, 0x37, 0x32, 0x0A, 0x00, 0x08, 0x41, - 0x30, 0x37, 0x33, 0x11, 0x13, 0x0A, 0x10, 0x01, - 0x02, 0x04, 0x04, 0x08, 0x08, 0x08, 0x08, 0x10, - 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x14, - 0x48, 0x0F, 0x41, 0x30, 0x37, 0x34, 0x01, 0x08, - 0x41, 0x30, 0x34, 0x30, 0x0A, 0x00, 0x08, 0x41, - 0x30, 0x37, 0x35, 0x0A, 0x00, 0x70, 0x0A, 0x00, - 0x41, 0x30, 0x33, 0x34, 0x70, 0x11, 0x03, 0x0A, - 0x0A, 0x67, 0x70, 0x83, 0x88, 0x68, 0x0A, 0x03, - 0x00, 0x41, 0x30, 0x34, 0x30, 0x70, 0x83, 0x88, - 0x68, 0x0A, 0x04, 0x00, 0x41, 0x30, 0x37, 0x35, - 0x70, 0x0A, 0x03, 0x88, 0x67, 0x0A, 0x00, 0x00, - 0x70, 0x0A, 0x00, 0x88, 0x67, 0x0A, 0x01, 0x00, - 0x70, 0x41, 0x30, 0x37, 0x35, 0x88, 0x67, 0x0A, - 0x02, 0x00, 0xA2, 0x47, 0x05, 0x92, 0x94, 0x41, - 0x30, 0x33, 0x34, 0x41, 0x30, 0x30, 0x31, 0xA0, - 0x45, 0x04, 0x93, 0x41, 0x30, 0x34, 0x38, 0x41, - 0x30, 0x33, 0x34, 0x0A, 0x01, 0x70, 0x41, 0x30, - 0x30, 0x38, 0x79, 0x72, 0x41, 0x30, 0x33, 0x34, - 0x0A, 0x02, 0x00, 0x0A, 0x03, 0x00, 0x0A, 0x18, - 0x61, 0x7B, 0x7A, 0x61, 0x0A, 0x10, 0x00, 0x0A, - 0xFF, 0x62, 0x7B, 0x7A, 0x61, 0x0A, 0x08, 0x00, - 0x0A, 0xFF, 0x61, 0xA0, 0x11, 0x90, 0x92, 0x95, - 0x41, 0x30, 0x34, 0x30, 0x61, 0x92, 0x94, 0x41, - 0x30, 0x34, 0x30, 0x62, 0xA5, 0x75, 0x41, 0x30, - 0x33, 0x34, 0xA0, 0x0C, 0x94, 0x41, 0x30, 0x33, - 0x34, 0x41, 0x30, 0x30, 0x31, 0xA4, 0x67, 0xA0, - 0x13, 0x92, 0x94, 0x41, 0x30, 0x37, 0x36, 0x41, - 0x30, 0x33, 0x34, 0x0A, 0x01, 0x41, 0x30, 0x37, - 0x35, 0xA4, 0x67, 0x70, 0x83, 0x88, 0x41, 0x30, - 0x37, 0x33, 0x41, 0x30, 0x37, 0x35, 0x00, 0x61, - 0x41, 0x30, 0x37, 0x37, 0x41, 0x30, 0x33, 0x34, - 0x0A, 0x01, 0x0A, 0x00, 0x41, 0x30, 0x37, 0x37, - 0x41, 0x30, 0x33, 0x34, 0x0A, 0x02, 0x61, 0x70, - 0x61, 0x88, 0x67, 0x0A, 0x02, 0x00, 0xA4, 0x67, - 0x14, 0x4C, 0x06, 0x41, 0x30, 0x37, 0x38, 0x09, - 0x70, 0x83, 0x88, 0x68, 0x0A, 0x04, 0x00, 0x60, - 0x70, 0x83, 0x88, 0x68, 0x0A, 0x02, 0x00, 0x61, - 0x74, 0x7A, 0x61, 0x0A, 0x03, 0x00, 0x0A, 0x02, - 0x61, 0xA0, 0x09, 0x93, 0x60, 0x0A, 0x01, 0x70, - 0x0A, 0x06, 0x62, 0xA1, 0x05, 0x70, 0x0A, 0x04, - 0x62, 0x70, 0x41, 0x30, 0x37, 0x39, 0x61, 0x62, - 0x60, 0x70, 0x11, 0x03, 0x0A, 0x0A, 0x67, 0x8B, - 0x67, 0x0A, 0x00, 0x41, 0x30, 0x34, 0x31, 0x8C, - 0x67, 0x0A, 0x02, 0x41, 0x30, 0x34, 0x32, 0x8C, - 0x67, 0x0A, 0x03, 0x41, 0x30, 0x38, 0x30, 0x70, - 0x0A, 0x04, 0x41, 0x30, 0x34, 0x31, 0x70, 0x0A, - 0x00, 0x41, 0x30, 0x34, 0x32, 0x70, 0x60, 0x41, - 0x30, 0x38, 0x30, 0xA4, 0x67, 0x08, 0x41, 0x30, - 0x38, 0x31, 0x11, 0x0D, 0x0A, 0x0A, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x14, 0x45, 0x1A, 0x41, 0x30, 0x37, 0x39, 0x0A, - 0x70, 0x0A, 0x00, 0x64, 0x70, 0x41, 0x30, 0x38, - 0x32, 0x68, 0x67, 0x70, 0x83, 0x88, 0x67, 0x0A, - 0x07, 0x00, 0x61, 0xA0, 0x08, 0x92, 0x93, 0x61, - 0x0A, 0x01, 0xA4, 0x64, 0x70, 0x69, 0x62, 0xA2, - 0x4C, 0x17, 0x92, 0x93, 0x62, 0x0A, 0x08, 0xA0, - 0x41, 0x04, 0x93, 0x62, 0x0A, 0x06, 0x70, 0x0A, - 0x00, 0x88, 0x41, 0x30, 0x32, 0x33, 0x68, 0x00, - 0x41, 0x30, 0x35, 0x37, 0x68, 0x0A, 0xA2, 0x80, - 0x0B, 0x00, 0x20, 0x00, 0x0A, 0x00, 0x70, 0x0A, - 0x00, 0x41, 0x30, 0x32, 0x36, 0x41, 0x30, 0x33, - 0x37, 0x41, 0x30, 0x37, 0x37, 0x68, 0x0A, 0x01, - 0x0A, 0x00, 0x41, 0x30, 0x38, 0x33, 0x68, 0x0A, - 0x00, 0x70, 0x0A, 0x01, 0x62, 0x70, 0x0A, 0x00, - 0x63, 0xA0, 0x31, 0x93, 0x62, 0x0A, 0x01, 0x7B, - 0x41, 0x30, 0x36, 0x30, 0x68, 0x0A, 0xA5, 0x0A, - 0x3F, 0x61, 0xA0, 0x0E, 0x94, 0x61, 0x0A, 0x04, - 0x70, 0x0A, 0x02, 0x62, 0x70, 0x0A, 0x00, 0x63, - 0x9F, 0xA0, 0x0B, 0x95, 0x63, 0x0A, 0x50, 0x5B, - 0x22, 0x0A, 0x01, 0x75, 0x63, 0xA1, 0x05, 0x70, - 0x0A, 0x04, 0x62, 0xA0, 0x4C, 0x06, 0x93, 0x62, - 0x0A, 0x02, 0x70, 0x41, 0x30, 0x36, 0x30, 0x68, - 0x0A, 0xA5, 0x61, 0x7B, 0x61, 0x0A, 0x3F, 0x61, - 0xA0, 0x0A, 0x93, 0x61, 0x0A, 0x10, 0x70, 0x0A, - 0x05, 0x62, 0x9F, 0xA0, 0x0C, 0x95, 0x63, 0x0A, - 0x50, 0x5B, 0x22, 0x0A, 0x01, 0x75, 0x63, 0x9F, - 0x70, 0x0A, 0x04, 0x62, 0xA0, 0x0D, 0x93, 0x83, - 0x88, 0x41, 0x30, 0x32, 0x33, 0x68, 0x00, 0x0A, - 0x01, 0x9F, 0xA0, 0x2D, 0x93, 0x41, 0x30, 0x38, - 0x34, 0x68, 0x0A, 0x01, 0x41, 0x30, 0x35, 0x37, - 0x68, 0x0A, 0xA2, 0x80, 0x0B, 0x00, 0x20, 0x00, - 0x0B, 0x00, 0x20, 0x70, 0x0A, 0x01, 0x88, 0x41, - 0x30, 0x32, 0x33, 0x68, 0x00, 0x41, 0x30, 0x35, - 0x36, 0x68, 0x0A, 0x01, 0x70, 0x0A, 0x07, 0x62, - 0xA0, 0x23, 0x93, 0x62, 0x0A, 0x04, 0x41, 0x30, - 0x38, 0x33, 0x68, 0x0A, 0x01, 0x41, 0x30, 0x37, - 0x37, 0x68, 0x0A, 0x00, 0x0A, 0x00, 0x70, 0x0A, - 0x01, 0x88, 0x41, 0x30, 0x32, 0x33, 0x68, 0x00, - 0x70, 0x0A, 0x00, 0x62, 0xA0, 0x4C, 0x04, 0x93, - 0x62, 0x0A, 0x07, 0xA0, 0x41, 0x04, 0x5B, 0x12, - 0x5C, 0x2E, 0x5F, 0x53, 0x42, 0x5F, 0x41, 0x4C, - 0x49, 0x43, 0x66, 0x70, 0x79, 0x72, 0x68, 0x0A, - 0x02, 0x00, 0x0A, 0x03, 0x00, 0x61, 0x5C, 0x2E, - 0x5F, 0x53, 0x42, 0x5F, 0x41, 0x4C, 0x49, 0x43, - 0x61, 0x0A, 0x00, 0x5B, 0x22, 0x0A, 0x02, 0x5C, - 0x2E, 0x5F, 0x53, 0x42, 0x5F, 0x41, 0x4C, 0x49, - 0x43, 0x61, 0x0A, 0x01, 0x70, 0x0A, 0x00, 0x63, - 0x70, 0x0A, 0x01, 0x62, 0x9F, 0x70, 0x0A, 0x04, - 0x62, 0xA0, 0x0D, 0x93, 0x62, 0x0A, 0x05, 0x70, - 0x0A, 0x01, 0x64, 0x70, 0x0A, 0x00, 0x62, 0xA0, - 0x14, 0x93, 0x62, 0x0A, 0x00, 0x70, 0x0A, 0x01, - 0x41, 0x30, 0x32, 0x36, 0x41, 0x30, 0x33, 0x37, - 0x70, 0x0A, 0x08, 0x62, 0xA4, 0x64, 0x14, 0x40, - 0x0B, 0x41, 0x30, 0x37, 0x37, 0x0B, 0x70, 0x41, - 0x30, 0x38, 0x32, 0x68, 0x67, 0x70, 0x83, 0x88, - 0x67, 0x0A, 0x02, 0x00, 0x41, 0x30, 0x36, 0x39, - 0x70, 0x83, 0x88, 0x67, 0x0A, 0x03, 0x00, 0x41, - 0x30, 0x37, 0x30, 0xA0, 0x14, 0x93, 0x69, 0x0A, - 0x00, 0x41, 0x30, 0x38, 0x35, 0x68, 0x41, 0x30, - 0x36, 0x39, 0x41, 0x30, 0x37, 0x30, 0x0A, 0x01, - 0xA0, 0x14, 0x93, 0x69, 0x0A, 0x01, 0x41, 0x30, - 0x38, 0x35, 0x68, 0x41, 0x30, 0x36, 0x39, 0x41, - 0x30, 0x37, 0x30, 0x0A, 0x00, 0xA0, 0x09, 0x92, - 0x93, 0x69, 0x0A, 0x02, 0xA4, 0x0A, 0x00, 0xA0, - 0x0E, 0x93, 0x6A, 0x0A, 0x00, 0x70, 0x41, 0x30, - 0x37, 0x36, 0x68, 0x0A, 0x00, 0x62, 0xA1, 0x04, - 0x70, 0x6A, 0x62, 0xA0, 0x0E, 0x92, 0x94, 0x41, - 0x30, 0x37, 0x36, 0x68, 0x0A, 0x01, 0x62, 0xA4, - 0x0A, 0x00, 0x70, 0x41, 0x30, 0x38, 0x36, 0x68, - 0x61, 0xA0, 0x12, 0x93, 0x61, 0x0A, 0x00, 0x72, - 0x41, 0x30, 0x36, 0x39, 0x62, 0x63, 0x70, 0x41, - 0x30, 0x37, 0x30, 0x64, 0xA1, 0x0E, 0x74, 0x41, - 0x30, 0x37, 0x30, 0x62, 0x64, 0x70, 0x41, 0x30, - 0x36, 0x39, 0x63, 0x41, 0x30, 0x38, 0x35, 0x68, - 0x63, 0x64, 0x0A, 0x01, 0xA4, 0x0A, 0x00, 0x14, - 0x40, 0x09, 0x41, 0x30, 0x38, 0x34, 0x01, 0x70, - 0x11, 0x03, 0x0A, 0x10, 0x61, 0x70, 0x0A, 0x00, - 0x60, 0xA2, 0x45, 0x05, 0x92, 0x94, 0x60, 0x0A, - 0x03, 0x70, 0x41, 0x30, 0x36, 0x30, 0x68, 0x72, - 0x60, 0x0A, 0xA5, 0x00, 0x62, 0x70, 0x62, 0x88, - 0x61, 0x77, 0x60, 0x0A, 0x04, 0x00, 0x00, 0x70, - 0x7A, 0x62, 0x0A, 0x08, 0x00, 0x88, 0x61, 0x72, - 0x77, 0x60, 0x0A, 0x04, 0x00, 0x0A, 0x01, 0x00, - 0x00, 0x70, 0x7A, 0x62, 0x0A, 0x10, 0x00, 0x88, - 0x61, 0x72, 0x77, 0x60, 0x0A, 0x04, 0x00, 0x0A, - 0x02, 0x00, 0x00, 0x70, 0x7A, 0x62, 0x0A, 0x18, - 0x00, 0x88, 0x61, 0x72, 0x77, 0x60, 0x0A, 0x04, - 0x00, 0x0A, 0x03, 0x00, 0x00, 0x75, 0x60, 0x70, - 0x0A, 0x00, 0x60, 0xA2, 0x21, 0x95, 0x60, 0x0A, - 0x0F, 0xA0, 0x19, 0x90, 0x93, 0x83, 0x88, 0x61, - 0x60, 0x00, 0x0A, 0x2A, 0x93, 0x83, 0x88, 0x61, - 0x72, 0x60, 0x0A, 0x01, 0x00, 0x00, 0x0A, 0x09, - 0xA4, 0x0A, 0x01, 0x75, 0x60, 0xA4, 0x0A, 0x00, - 0x14, 0x4B, 0x04, 0x41, 0x30, 0x38, 0x36, 0x09, - 0x70, 0x41, 0x30, 0x38, 0x32, 0x68, 0x67, 0x70, - 0x83, 0x88, 0x67, 0x0A, 0x00, 0x00, 0x41, 0x30, - 0x36, 0x37, 0x70, 0x83, 0x88, 0x67, 0x0A, 0x01, - 0x00, 0x41, 0x30, 0x36, 0x38, 0x70, 0x0A, 0x00, - 0x60, 0xA0, 0x0E, 0x94, 0x41, 0x30, 0x36, 0x37, - 0x41, 0x30, 0x36, 0x38, 0x70, 0x0A, 0x01, 0x60, - 0x7B, 0x41, 0x30, 0x36, 0x30, 0x68, 0x0A, 0x50, - 0x0A, 0x01, 0x61, 0xA4, 0x7B, 0x7F, 0x60, 0x61, - 0x00, 0x0A, 0x01, 0x00, 0x14, 0x49, 0x05, 0x41, - 0x30, 0x38, 0x33, 0x02, 0x70, 0x41, 0x30, 0x38, - 0x32, 0x68, 0x67, 0x70, 0x83, 0x88, 0x67, 0x0A, - 0x04, 0x00, 0x41, 0x30, 0x37, 0x32, 0x70, 0x7D, - 0x79, 0x83, 0x88, 0x67, 0x72, 0x0A, 0x05, 0x0A, - 0x01, 0x00, 0x00, 0x0A, 0x08, 0x00, 0x83, 0x88, - 0x67, 0x0A, 0x05, 0x00, 0x00, 0x41, 0x30, 0x37, - 0x31, 0x41, 0x30, 0x31, 0x37, 0x0A, 0x00, 0x0A, - 0xE0, 0x7D, 0x79, 0x41, 0x30, 0x37, 0x31, 0x0A, - 0x10, 0x00, 0x72, 0x0B, 0x00, 0x08, 0x77, 0x0B, - 0x00, 0x01, 0x41, 0x30, 0x37, 0x32, 0x00, 0x00, - 0x00, 0x80, 0x0A, 0x01, 0x00, 0x69, 0x08, 0x41, - 0x30, 0x38, 0x37, 0x11, 0x0A, 0x0A, 0x07, 0x00, - 0x01, 0x02, 0x04, 0x08, 0x0C, 0x10, 0x14, 0x4B, - 0x06, 0x41, 0x30, 0x37, 0x36, 0x02, 0xA0, 0x1E, - 0x93, 0x69, 0x0A, 0x00, 0x7B, 0x7A, 0x41, 0x30, - 0x36, 0x30, 0x68, 0x0A, 0xA2, 0x0A, 0x04, 0x00, - 0x0A, 0x07, 0x60, 0x70, 0x83, 0x88, 0x41, 0x30, - 0x38, 0x37, 0x60, 0x00, 0x61, 0xA1, 0x42, 0x04, - 0x70, 0x41, 0x30, 0x38, 0x32, 0x68, 0x67, 0x70, - 0x83, 0x88, 0x67, 0x0A, 0x00, 0x00, 0x41, 0x30, - 0x36, 0x37, 0x70, 0x83, 0x88, 0x67, 0x0A, 0x01, - 0x00, 0x41, 0x30, 0x36, 0x38, 0xA0, 0x14, 0x94, - 0x41, 0x30, 0x36, 0x37, 0x41, 0x30, 0x36, 0x38, - 0x74, 0x41, 0x30, 0x36, 0x37, 0x41, 0x30, 0x36, - 0x38, 0x61, 0xA1, 0x0B, 0x74, 0x41, 0x30, 0x36, - 0x38, 0x41, 0x30, 0x36, 0x37, 0x61, 0x75, 0x61, - 0xA4, 0x61, 0x14, 0x4C, 0x09, 0x41, 0x30, 0x38, - 0x35, 0x0C, 0x70, 0x41, 0x30, 0x38, 0x32, 0x68, - 0x67, 0x70, 0x69, 0x41, 0x30, 0x36, 0x39, 0x70, - 0x6A, 0x41, 0x30, 0x37, 0x30, 0x70, 0x7D, 0x79, - 0x83, 0x88, 0x67, 0x72, 0x0A, 0x05, 0x0A, 0x01, - 0x00, 0x00, 0x0A, 0x08, 0x00, 0x83, 0x88, 0x67, - 0x0A, 0x05, 0x00, 0x00, 0x41, 0x30, 0x37, 0x31, - 0xA0, 0x1A, 0x94, 0x41, 0x30, 0x36, 0x39, 0x41, - 0x30, 0x37, 0x30, 0x74, 0x41, 0x30, 0x36, 0x39, - 0x41, 0x30, 0x37, 0x30, 0x61, 0x70, 0x41, 0x30, - 0x37, 0x30, 0x62, 0xA1, 0x11, 0x74, 0x41, 0x30, - 0x37, 0x30, 0x41, 0x30, 0x36, 0x39, 0x61, 0x70, - 0x41, 0x30, 0x36, 0x39, 0x62, 0x79, 0x74, 0x79, - 0x0A, 0x01, 0x72, 0x61, 0x0A, 0x01, 0x00, 0x00, - 0x0A, 0x01, 0x00, 0x62, 0x63, 0x70, 0x80, 0x63, - 0x00, 0x64, 0xA0, 0x09, 0x93, 0x6B, 0x0A, 0x01, - 0x70, 0x0A, 0x00, 0x63, 0x41, 0x30, 0x31, 0x37, - 0x0A, 0x00, 0x0A, 0xE0, 0x7D, 0x79, 0x41, 0x30, - 0x37, 0x31, 0x0A, 0x10, 0x00, 0x0B, 0x23, 0x80, - 0x00, 0x64, 0x63, 0x5B, 0x21, 0x0A, 0x0A, 0x08, - 0x41, 0x30, 0x30, 0x32, 0x0A, 0x00, 0x08, 0x41, - 0x30, 0x30, 0x33, 0x0A, 0x00, 0x08, 0x41, 0x30, - 0x30, 0x34, 0x0A, 0x00, 0x08, 0x41, 0x30, 0x30, - 0x35, 0x0A, 0x00, 0x14, 0x45, 0x0D, 0x41, 0x30, - 0x30, 0x36, 0x01, 0x70, 0x7D, 0x79, 0x0A, 0x18, - 0x0A, 0x03, 0x00, 0x0A, 0x04, 0x00, 0x61, 0xA0, - 0x35, 0x93, 0x41, 0x30, 0x30, 0x35, 0x0A, 0x00, - 0x70, 0x41, 0x30, 0x30, 0x37, 0x0B, 0x80, 0x85, - 0x41, 0x30, 0x30, 0x33, 0x70, 0x41, 0x30, 0x30, - 0x38, 0x61, 0x0B, 0x5C, 0x01, 0x41, 0x30, 0x30, - 0x32, 0x70, 0x41, 0x30, 0x30, 0x38, 0x61, 0x0B, - 0xA4, 0x01, 0x41, 0x30, 0x30, 0x34, 0x70, 0x0A, - 0x01, 0x41, 0x30, 0x30, 0x35, 0x70, 0x41, 0x30, - 0x30, 0x37, 0x0B, 0x80, 0x85, 0x60, 0x70, 0x7D, - 0x79, 0x0A, 0x18, 0x0A, 0x03, 0x00, 0x0A, 0x04, - 0x00, 0x61, 0x70, 0x41, 0x30, 0x30, 0x38, 0x61, - 0x0B, 0x5C, 0x01, 0x62, 0x70, 0x41, 0x30, 0x30, - 0x38, 0x61, 0x0B, 0xA4, 0x01, 0x63, 0xA0, 0x1A, - 0x93, 0x68, 0x0A, 0x01, 0x7B, 0x60, 0x0C, 0xFE, - 0xFF, 0xFF, 0xFF, 0x60, 0x7B, 0x62, 0x0C, 0xFC, - 0xFF, 0xFF, 0xFF, 0x62, 0x7D, 0x63, 0x0A, 0x03, - 0x63, 0xA1, 0x25, 0x7D, 0x60, 0x7B, 0x41, 0x30, - 0x30, 0x33, 0x0A, 0x01, 0x00, 0x60, 0x7D, 0x62, - 0x7B, 0x41, 0x30, 0x30, 0x32, 0x0A, 0x03, 0x00, - 0x62, 0x7B, 0x63, 0x7D, 0x0C, 0xFC, 0xFF, 0xFF, - 0xFF, 0x41, 0x30, 0x30, 0x34, 0x00, 0x63, 0x41, - 0x30, 0x30, 0x39, 0x61, 0x0B, 0xA4, 0x01, 0x63, - 0x41, 0x30, 0x30, 0x39, 0x61, 0x0B, 0x5C, 0x01, - 0x62, 0x41, 0x30, 0x31, 0x30, 0x0B, 0x80, 0x85, - 0x60, 0x41, 0x30, 0x31, 0x31, 0x0A, 0x12, 0x0A, - 0x03, 0x14, 0x41, 0x06, 0x41, 0x30, 0x31, 0x32, - 0x01, 0x70, 0x41, 0x30, 0x31, 0x33, 0x61, 0x70, - 0x41, 0x30, 0x30, 0x37, 0x0B, 0x90, 0x84, 0x60, - 0xA0, 0x4A, 0x04, 0x92, 0x93, 0x7B, 0x60, 0x0A, - 0xF0, 0x00, 0x0A, 0x00, 0xA0, 0x12, 0x93, 0x68, - 0x0A, 0x02, 0x7B, 0x60, 0x0C, 0xA0, 0xFF, 0xFF, - 0xFF, 0x60, 0x7D, 0x60, 0x0A, 0xA0, 0x60, 0xA1, - 0x23, 0xA0, 0x12, 0x93, 0x61, 0x0A, 0x00, 0x7B, - 0x60, 0x0C, 0x60, 0xFF, 0xFF, 0xFF, 0x60, 0x7D, - 0x60, 0x0A, 0x60, 0x60, 0xA1, 0x0E, 0x7B, 0x60, - 0x0C, 0x20, 0xFF, 0xFF, 0xFF, 0x60, 0x7D, 0x60, - 0x0A, 0x20, 0x60, 0x41, 0x30, 0x31, 0x30, 0x0B, - 0x90, 0x84, 0x60, 0x08, 0x41, 0x44, 0x30, 0x41, - 0x0A, 0x01, 0x14, 0x47, 0x04, 0x41, 0x30, 0x31, - 0x34, 0x01, 0xA0, 0x3F, 0x93, 0x41, 0x44, 0x30, - 0x41, 0x0A, 0x01, 0x70, 0x41, 0x30, 0x31, 0x33, - 0x61, 0x70, 0x41, 0x30, 0x30, 0x37, 0x0B, 0x2C, - 0x84, 0x60, 0x7B, 0x60, 0x0C, 0xFE, 0xFF, 0xFF, - 0xFF, 0x60, 0xA0, 0x0F, 0x90, 0x93, 0x68, 0x0A, - 0x01, 0x93, 0x61, 0x0A, 0x01, 0x7D, 0x60, 0x0A, - 0x01, 0x60, 0x41, 0x30, 0x31, 0x30, 0x0B, 0x2C, - 0x84, 0x60, 0x41, 0x30, 0x31, 0x31, 0x0A, 0x1B, - 0x0A, 0x03, 0x14, 0x48, 0x0A, 0x41, 0x30, 0x31, - 0x35, 0x01, 0x70, 0x68, 0x60, 0xA0, 0x09, 0x93, - 0x68, 0x0A, 0x02, 0x70, 0x0A, 0x00, 0x60, 0xA0, - 0x49, 0x04, 0x92, 0x93, 0x41, 0x30, 0x31, 0x36, - 0x0A, 0x00, 0x0A, 0xE0, 0x0C, 0x23, 0x80, 0x30, - 0x01, 0x0A, 0x00, 0x41, 0x30, 0x31, 0x37, 0x0A, - 0x00, 0x0A, 0xE0, 0x0C, 0x16, 0x80, 0x30, 0x01, - 0x80, 0x0B, 0x00, 0x10, 0x00, 0x79, 0x60, 0x0A, - 0x0C, 0x00, 0xA2, 0x1E, 0x92, 0x93, 0x7B, 0x41, - 0x30, 0x31, 0x36, 0x0A, 0x00, 0x0A, 0xE0, 0x0C, - 0x16, 0x80, 0x30, 0x01, 0x0B, 0x00, 0x20, 0x00, - 0x79, 0x60, 0x0A, 0x0D, 0x00, 0x5B, 0x21, 0x0A, - 0x0A, 0xA0, 0x49, 0x04, 0x92, 0x93, 0x41, 0x30, - 0x31, 0x36, 0x0A, 0x00, 0x0A, 0xE0, 0x0C, 0x23, - 0x80, 0x31, 0x01, 0x0A, 0x00, 0x41, 0x30, 0x31, - 0x37, 0x0A, 0x00, 0x0A, 0xE0, 0x0C, 0x16, 0x80, - 0x31, 0x01, 0x80, 0x0B, 0x00, 0x10, 0x00, 0x79, - 0x60, 0x0A, 0x0C, 0x00, 0xA2, 0x1E, 0x92, 0x93, - 0x7B, 0x41, 0x30, 0x31, 0x36, 0x0A, 0x00, 0x0A, - 0xE0, 0x0C, 0x16, 0x80, 0x31, 0x01, 0x0B, 0x00, - 0x20, 0x00, 0x79, 0x60, 0x0A, 0x0D, 0x00, 0x5B, - 0x21, 0x0A, 0x0A -}; - -#endif diff --git a/src/vendorcode/amd/agesa/f12/Proc/GNB/PCIe/Family/LN/F12PcieComplexConfig.c b/src/vendorcode/amd/agesa/f12/Proc/GNB/PCIe/Family/LN/F12PcieComplexConfig.c deleted file mode 100644 index a1b9d4bd2b..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/GNB/PCIe/Family/LN/F12PcieComplexConfig.c +++ /dev/null @@ -1,162 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * Family specific PCIe configuration data services - * - * - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: GNB - * @e \$Revision: 49532 $ @e \$Date: 2011-03-25 02:54:43 +0800 (Fri, 25 Mar 2011) $ - * - */ -/* -***************************************************************************** -* -* Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* *************************************************************************** -* -*/ - -/*---------------------------------------------------------------------------------------- - * M O D U L E S U S E D - *---------------------------------------------------------------------------------------- - */ -#include "AGESA.h" -#include "Ids.h" -#include "amdlib.h" -#include "Gnb.h" -#include "GnbPcie.h" -#include "GnbPcieConfig.h" -#include "GnbPcieFamServices.h" -#include "LlanoDefinitions.h" -#include "LlanoComplexData.h" -#include "Filecode.h" -#define FILECODE PROC_GNB_PCIE_FAMILY_LN_F12PCIECOMPLEXCONFIG_FILECODE -/*---------------------------------------------------------------------------------------- - * D E F I N I T I O N S A N D M A C R O S - *---------------------------------------------------------------------------------------- - */ - - -/*---------------------------------------------------------------------------------------- - * T Y P E D E F S A N D S T R U C T U R E S - *---------------------------------------------------------------------------------------- - */ - - -/*---------------------------------------------------------------------------------------- - * P R O T O T Y P E S O F L O C A L F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ - - -/*----------------------------------------------------------------------------------------*/ -/** - * Get total number of silicons/wrappers/engines for this complex - * - * - * @param[in] SocketId Socket ID. - * @param[out] Length Length of configuration info block - * @param[in] StdHeader Standard configuration header. - * @retval AGESA_SUCCESS Configuration data length is correct - */ -AGESA_STATUS -PcieFmGetComplexDataLength ( - IN UINT8 SocketId, - OUT UINTN *Length, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - *Length = sizeof (ComplexData); - return AGESA_SUCCESS; -} - - - - -/*----------------------------------------------------------------------------------------*/ -/** - * Build configuration - * - * - * @param[in] SocketId Socket ID - * @param[out] Buffer Pointer to buffer to build internal complex data structure - * @param[in] StdHeader Standard configuration header. - * @retval AGESA_SUCCESS Configuration data build successfully - */ -AGESA_STATUS -PcieFmBuildComplexConfiguration ( - IN UINT8 SocketId, - OUT VOID *Buffer, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - LibAmdMemCopy (Buffer, &ComplexData, sizeof (ComplexData), StdHeader); - return AGESA_SUCCESS; -} - - -/*----------------------------------------------------------------------------------------*/ -/** - * get native PHY lane bitmap - * - * - * @param[in] PhyLaneBitmap Package PHY lane bitmap - * @param[in] Engine Standard configuration header. - * @retval Native PHY lane bitmap - */ -UINT32 -PcieFmGetNativePhyLaneBitmap ( - IN UINT32 PhyLaneBitmap, - IN PCIe_ENGINE_CONFIG *Engine - ) -{ - return PhyLaneBitmap; -} -/*----------------------------------------------------------------------------------------*/ -/** - * Get SB port info - * - * - * @param[out] SocketId Socket ID - * @param[out] SbPort Pointer to SB configuration descriptor - * @param[in] StdHeader Standard configuration header. - * @retval AGESA_SUCCESS SB configuration determined successfully - */ -AGESA_STATUS -PcieFmGetSbConfigInfo ( - IN UINT8 SocketId, - OUT PCIe_PORT_DESCRIPTOR *SbPort, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - LibAmdMemCopy (SbPort, &DefaultSbPort, sizeof (PCIe_PORT_DESCRIPTOR), StdHeader); - return AGESA_SUCCESS; -} - diff --git a/src/vendorcode/amd/agesa/f12/Proc/GNB/PCIe/Family/LN/F12PcieComplexServices.c b/src/vendorcode/amd/agesa/f12/Proc/GNB/PCIe/Family/LN/F12PcieComplexServices.c deleted file mode 100644 index c7b08a3e65..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/GNB/PCIe/Family/LN/F12PcieComplexServices.c +++ /dev/null @@ -1,243 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * Family specific PCIe complex initialization services - * - * - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: GNB - * @e \$Revision: 49532 $ @e \$Date: 2011-03-25 02:54:43 +0800 (Fri, 25 Mar 2011) $ - * - */ -/* -***************************************************************************** -* -* Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* *************************************************************************** -* -*/ -/*---------------------------------------------------------------------------------------- - * M O D U L E S U S E D - *---------------------------------------------------------------------------------------- - */ -#include "AGESA.h" -#include "Ids.h" -#include "Gnb.h" -#include "GnbPcie.h" -#include "GnbCommonLib.h" -#include "GnbPcieInitLibV1.h" -#include "GnbPcieConfig.h" -#include "PcieFamilyServices.h" -#include "GnbPcieFamServices.h" -#include "LlanoDefinitions.h" -#include "GnbRegistersLN.h" -#include "NbSmuLib.h" -#include "Filecode.h" -#include "GnbPcieInitLibV1.h" -#define FILECODE PROC_GNB_PCIE_FAMILY_LN_F12PCIECOMPLEXSERVICES_FILECODE -/*---------------------------------------------------------------------------------------- - * D E F I N I T I O N S A N D M A C R O S - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------- - * T Y P E D E F S A N D S T R U C T U R E S - *---------------------------------------------------------------------------------------- - */ - - -/*---------------------------------------------------------------------------------------- - * P R O T O T Y P E S O F L O C A L F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ - - -/*----------------------------------------------------------------------------------------*/ -/** - * Control port visability - * - * - * @param[in] Control Hide/Unhide control - * @param[in] Silicon Pointer to silicon configuration descriptor - * @param[in] Pcie Pointer to global PCIe configuration - */ - -VOID -PcieFmPortVisabilityControl ( - IN PCIE_PORT_VISIBILITY Control, - IN PCIe_SILICON_CONFIG *Silicon, - IN PCIe_PLATFORM_CONFIG *Pcie - ) -{ - switch (Control) { - case UnhidePorts: - PcieSiliconUnHidePorts (Silicon, Pcie); - break; - case HidePorts: - PcieSiliconHidePorts (Silicon, Pcie); - break; - default: - ASSERT (FALSE); - } -} - - -/*----------------------------------------------------------------------------------------*/ -/** - * Request boot up voltage - * - * - * - * @param[in] LinkCap Global GEN capability - * @param[in] Pcie Pointer to PCIe configuration data area - */ -VOID -PcieFmSetBootUpVoltage ( - IN PCIE_LINK_SPEED_CAP LinkCap, - IN PCIe_PLATFORM_CONFIG *Pcie - ) -{ - FCRxFE00_4036_STRUCT FCRxFE00_4036; - D18F3x15C_STRUCT D18F3x15C; - UINT8 TargetVidIndex; - UINT32 Temp; - IDS_HDT_CONSOLE (GNB_TRACE, "PcieFmSetBootUpVoltage Enter\n"); - GnbLibPciRead ( - MAKE_SBDFO ( 0, 0, 0x18, 3, D18F3x15C_ADDRESS), - AccessWidth32, - &D18F3x15C.Value, - GnbLibGetHeader (Pcie) - ); - Temp = D18F3x15C.Value; - if (LinkCap > PcieGen1) { - FCRxFE00_4036.Value = NbSmuReadEfuse (FCRxFE00_4036_ADDRESS, GnbLibGetHeader (Pcie)); - TargetVidIndex = (UINT8) FCRxFE00_4036.Field.PcieGen2Vid; - } else { - TargetVidIndex = PcieSiliconGetGen1VoltageIndex (GnbLibGetHeader (Pcie)); - } - IDS_HDT_CONSOLE (PCIE_MISC, " Set Voltage for Gen %d, Vid Index %d\n", LinkCap, TargetVidIndex); - if (TargetVidIndex == 3) { - D18F3x15C.Field.SclkVidLevel2 = D18F3x15C.Field.SclkVidLevel3; - GnbLibPciWrite ( - MAKE_SBDFO ( 0, 0, 0x18, 3, D18F3x15C_ADDRESS), - AccessWidth32, - &D18F3x15C.Value, - GnbLibGetHeader (Pcie) - ); - PcieSiliconRequestVoltage (2, GnbLibGetHeader (Pcie)); - } - GnbLibPciWrite ( - MAKE_SBDFO ( 0, 0, 0x18, 3, D18F3x15C_ADDRESS), - AccessWidth32, - &Temp, - GnbLibGetHeader (Pcie) - ); - PcieSiliconRequestVoltage (TargetVidIndex, GnbLibGetHeader (Pcie)); - IDS_HDT_CONSOLE (GNB_TRACE, "PcieFmSetBootUpVoltage Exit\n"); -} - -/*----------------------------------------------------------------------------------------*/ -/** - * Map engine to specific PCI device address - * - * - * - * @param[in] Engine Pointer to engine configuration - * @retval AGESA_ERROR Fail to map PCI device address - * @retval AGESA_SUCCESS Successfully allocate PCI address - */ - -AGESA_STATUS -PcieFmMapPortPciAddress ( - IN PCIe_ENGINE_CONFIG *Engine - ) -{ - PCIe_WRAPPER_CONFIG *Wrapper; - PCIe_PLATFORM_CONFIG *Pcie; - UINT64 ConfigurationSignature; - - Wrapper = PcieConfigGetParentWrapper (Engine); - Pcie = (PCIe_PLATFORM_CONFIG *) PcieConfigGetParent (DESCRIPTOR_PLATFORM, &Engine->Header); - if (Wrapper->WrapId == GPP_WRAP_ID) { - ConfigurationSignature = PcieConfigGetConfigurationSignature (Wrapper, Engine->Type.Port.CoreId); - if ((ConfigurationSignature == GPP_CORE_x4x2x1x1_ST) || (ConfigurationSignature == GPP_CORE_x4x2x2_ST)) { - //Enable device remapping - GnbLibPciIndirectRMW ( - MAKE_SBDFO (0, 0, 0, 0, D0F0x60_ADDRESS), - D0F0x64_x20_ADDRESS | IOC_WRITE_ENABLE, - AccessS3SaveWidth32, - ~(UINT32) (1 << D0F0x64_x20_IocPcieDevRemapDis_OFFSET), - 0x0, - GnbLibGetHeader (Pcie) - ); - } - } - if (Engine->Type.Port.PortData.DeviceNumber == 0 && Engine->Type.Port.PortData.FunctionNumber == 0) { - Engine->Type.Port.PortData.DeviceNumber = Engine->Type.Port.NativeDevNumber; - Engine->Type.Port.PortData.FunctionNumber = Engine->Type.Port.NativeFunNumber; - return AGESA_SUCCESS; - } - if (Engine->Type.Port.PortData.DeviceNumber == Engine->Type.Port.NativeDevNumber && - Engine->Type.Port.PortData.FunctionNumber == Engine->Type.Port.NativeFunNumber) { - return AGESA_SUCCESS; - } - return AGESA_ERROR; -} - -/*----------------------------------------------------------------------------------------*/ -/** - * Set slo power limit - * - * - * - * @param[in] Engine Pointer to engine configuration - * @param[in] Pcie Pointer to PCIe configuration - */ - - -VOID -PcieFmEnableSlotPowerLimit ( - IN PCIe_ENGINE_CONFIG *Engine, - IN PCIe_PLATFORM_CONFIG *Pcie - ) -{ - ASSERT (Engine->EngineData.EngineType == PciePortEngine); - if (PcieLibIsEngineAllocated (Engine) && Engine->Type.Port.PortData.PortPresent != PortDisabled && !PcieConfigIsSbPcieEngine (Engine)) { - IDS_HDT_CONSOLE (PCIE_MISC, " Enable Slot Power Limit for Port % d\n", Engine->Type.Port.Address.Address.Device); - GnbLibPciIndirectRMW ( - MAKE_SBDFO (0, 0, 0, 0, D0F0x60_ADDRESS), - (D0F0x64_x51_ADDRESS + (Engine->Type.Port.Address.Address.Device - 2) * 2) | IOC_WRITE_ENABLE, - AccessS3SaveWidth32, - 0xffffffff, - 1 << D0F0x64_x51_SetPowEn_OFFSET, - GnbLibGetHeader (Pcie) - ); - } -} - diff --git a/src/vendorcode/amd/agesa/f12/Proc/GNB/PCIe/Family/LN/F12PciePhyServices.c b/src/vendorcode/amd/agesa/f12/Proc/GNB/PCIe/Family/LN/F12PciePhyServices.c deleted file mode 100644 index ca7f472959..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/GNB/PCIe/Family/LN/F12PciePhyServices.c +++ /dev/null @@ -1,535 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * Family specific PCIe PHY initialization services - * - * - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: GNB - * @e \$Revision: 49532 $ @e \$Date: 2011-03-25 02:54:43 +0800 (Fri, 25 Mar 2011) $ - * - */ -/* -***************************************************************************** -* -* Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* *************************************************************************** -* -*/ - -/*---------------------------------------------------------------------------------------- - * M O D U L E S U S E D - *---------------------------------------------------------------------------------------- - */ -#include "AGESA.h" -#include "Ids.h" -#include "Gnb.h" -#include "GnbPcie.h" -#include "GnbCommonLib.h" -#include "GnbPcieConfig.h" -#include "GnbPcieInitLibV1.h" -#include "PcieFamilyServices.h" -#include "LlanoDefinitions.h" -#include "cpuRegisters.h" -#include "GnbRegistersLN.h" -#include "cpuFamilyTranslation.h" -#include "NbSmuLib.h" -#include "GnbSbLib.h" -#include "Filecode.h" -#define FILECODE PROC_GNB_PCIE_FAMILY_LN_F12PCIEPHYSERVICES_FILECODE -/*---------------------------------------------------------------------------------------- - * D E F I N I T I O N S A N D M A C R O S - *---------------------------------------------------------------------------------------- - */ - - -/*---------------------------------------------------------------------------------------- - * T Y P E D E F S A N D S T R U C T U R E S - *---------------------------------------------------------------------------------------- - */ - - -/*---------------------------------------------------------------------------------------- - * P R O T O T Y P E S O F L O C A L F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ -AGESA_STATUS -PcieFmPreOscPifInitCallback ( - IN PCIe_WRAPPER_CONFIG *Wrapper, - IN OUT VOID *Buffer, - IN PCIe_PLATFORM_CONFIG *Pcie - ); - -AGESA_STATUS -PcieFmPostOscPifInitCallback ( - IN PCIe_WRAPPER_CONFIG *Wrapper, - IN OUT VOID *Buffer, - IN PCIe_PLATFORM_CONFIG *Pcie - ); - - -/*----------------------------------------------------------------------------------------*/ -/** - * Set PLL personality - * - * - * - * @param[in] Wrapper Pointer to wrapper config descriptor - * @param[in] Pcie Pointer to global PCIe configuration - */ -VOID -STATIC -PcieFmSetPhyPersonality ( - IN PCIe_WRAPPER_CONFIG *Wrapper, - IN PCIe_PLATFORM_CONFIG *Pcie - ) -{ - UINT8 Phy; - UINT8 Mode; - if (Wrapper->WrapId == GFX_WRAP_ID || Wrapper->WrapId == DDI_WRAP_ID) { - for (Phy = 0; Phy < Wrapper->NumberOfPIFs; Phy++) { - if (Wrapper->WrapId == GFX_WRAP_ID) { - Mode = (Phy == 0) ? 0x3 : 0x1; - } else { - Mode = 0x2; - } - PcieRegisterWriteField ( - Wrapper, - PHY_SPACE (Wrapper->WrapId, Phy, D0F0xE4_PHY_2005_ADDRESS), - D0F0xE4_PHY_2005_PllMode_OFFSET, - D0F0xE4_PHY_2005_PllMode_WIDTH, - Mode, - FALSE, - Pcie - ); - } - } -} - - -/*----------------------------------------------------------------------------------------*/ -/** - * PHY Pll Personality Init - * - * - * - * @param[in] Wrapper Pointer to wrapper config descriptor - * @param[in] Buffer Pointer to buffer - * @param[in] Pcie Pointer to global PCIe configuration - */ -AGESA_STATUS -PcieFmPhyLetPllPersonalityInitCallback ( - IN PCIe_WRAPPER_CONFIG *Wrapper, - IN VOID *Buffer, - IN PCIe_PLATFORM_CONFIG *Pcie - ) -{ - IDS_HDT_CONSOLE (GNB_TRACE, "PcieFmPhyLetPllPersonalityInitCallback Enter\n"); - PciePifPllPowerControl (PowerDownPifs, Wrapper, Pcie); - PciePifSetPllRampTime (NormalRampup, Wrapper, Pcie); - PciePollPifForCompeletion (Wrapper, Pcie); - PcieTopologyLaneControl ( - DisableLanes, - PcieUtilGetWrapperLaneBitMap (LANE_TYPE_CORE_ALL, LANE_TYPE_PCIE_SB_CORE_CONFIG, Wrapper), - Wrapper, - Pcie - ); - PciePollPifForCompeletion (Wrapper, Pcie); - PcieFmSetPhyPersonality (Wrapper, Pcie); - PcieWrapSetTxS1CtrlForLaneMux (Wrapper, Pcie); - PciePollPifForCompeletion (Wrapper, Pcie); - PcieTopologyLaneControl ( - EnableLanes, - PcieUtilGetWrapperLaneBitMap (LANE_TYPE_CORE_ALL, 0, Wrapper), - Wrapper, - Pcie - ); - PcieWrapSetTxOffCtrlForLaneMux (Wrapper, Pcie); - PciePollPifForCompeletion (Wrapper, Pcie); - PciePifPllPowerControl (PowerUpPifs, Wrapper, Pcie); - IDS_HDT_CONSOLE (GNB_TRACE, "PcieFmPhyLetPllPersonalityInitCallback Exit\n"); - return AGESA_SUCCESS; -} - -/*----------------------------------------------------------------------------------------*/ -/** - * Set PHY channel characteristic - * - * - * - * @param[in] Engine Pointer to engine configuration - * @param[in] Pcie Pointer to global PCIe configuration - */ -VOID -PcieFmPhyChannelCharacteristic ( - IN PCIe_ENGINE_CONFIG *Engine, - IN PCIe_PLATFORM_CONFIG *Pcie - ) -{ - //@todo -} - -/*----------------------------------------------------------------------------------------*/ -/** - * Point "virtual" PLL clock picker away from PCIe - * - * - * - * @param[in] Wrapper Pointer to internal configuration data area - * @param[in] Pcie Pointer to global PCIe configuration - */ -VOID -PcieFmAvertClockPickers ( - IN PCIe_WRAPPER_CONFIG *Wrapper, - IN PCIe_PLATFORM_CONFIG *Pcie - ) -{ - PciePhyAvertClockPickers (Wrapper, Pcie); -} - -/*----------------------------------------------------------------------------------------*/ -/** - * PHY lane ganging - * - * - * - * @param[out] Wrapper Pointer to internal configuration data area - * @param[in] Pcie Pointer to global PCIe configuration - */ -VOID -PcieFmPhyApplyGanging ( - IN PCIe_WRAPPER_CONFIG *Wrapper, - IN PCIe_PLATFORM_CONFIG *Pcie - ) -{ - PciePhyApplyGanging (Wrapper, Pcie); -} - -/*----------------------------------------------------------------------------------------*/ -/** - * DCC recalibration - * - * - * - * @param[in] Wrapper Pointer to internal configuration data area - * @param[in,out] Buffer Pointer to buffer - * @param[in] Pcie Pointer to global PCIe configuration - */ - -AGESA_STATUS -PcieFmForceDccRecalibrationCallback ( - IN PCIe_WRAPPER_CONFIG *Wrapper, - IN OUT VOID *Buffer, - IN PCIe_PLATFORM_CONFIG *Pcie - ) -{ - if (Wrapper->WrapId != DDI_WRAP_ID) { - PciePhyForceDccRecalibration (Wrapper, Pcie); - } - return AGESA_SUCCESS; -} - - -/*----------------------------------------------------------------------------------------*/ -/** - * Prepare for Osc switch - * - * - * - * @param[in] Wrapper Pointer to Wrapper config descriptor - * @param[in] Buffer Pointer to buffer - * @param[in] Pcie Pointer to global PCIe configuration - */ - -AGESA_STATUS -PcieFmPreOscPifInitCallback ( - IN PCIe_WRAPPER_CONFIG *Wrapper, - IN OUT VOID *Buffer, - IN PCIe_PLATFORM_CONFIG *Pcie - ) -{ - if (Wrapper->WrapId != DDI_WRAP_ID) { - PciePifFullPowerStateControl (PowerDownPifs, Wrapper, Pcie); - PcieTopologyLaneControl ( - DisableLanes, - PcieUtilGetWrapperLaneBitMap (LANE_TYPE_CORE_ALL, LANE_TYPE_PCIE_SB_CORE_CONFIG, Wrapper), - Wrapper, - Pcie - ); - PciePifSetPllRampTime (LongRampup, Wrapper, Pcie); - } - return AGESA_SUCCESS; -} - -/*----------------------------------------------------------------------------------------*/ -/** - * Post Osc init - * - * - * - * @param[in] Wrapper Pointer to Wrapper config descriptor - * @param[in] Buffer Pointer to buffer - * @param[in] Pcie Pointer to global PCIe configuration - */ -AGESA_STATUS -PcieFmPostOscPifInitCallback ( - IN PCIe_WRAPPER_CONFIG *Wrapper, - IN OUT VOID *Buffer, - IN PCIe_PLATFORM_CONFIG *Pcie - ) -{ - if (Wrapper->WrapId != DDI_WRAP_ID) { - PcieWrapSetTxS1CtrlForLaneMux (Wrapper, Pcie); - PciePollPifForCompeletion (Wrapper, Pcie); - PcieTopologyLaneControl ( - EnableLanes, - PcieUtilGetWrapperLaneBitMap (LANE_TYPE_CORE_ALL, 0, Wrapper), - Wrapper, - Pcie - ); - PcieWrapSetTxOffCtrlForLaneMux (Wrapper, Pcie); - PciePollPifForCompeletion (Wrapper, Pcie); - PciePifSetPllRampTime (NormalRampup, Wrapper, Pcie); - PciePifFullPowerStateControl (PowerUpPifs, Wrapper, Pcie); - } - return AGESA_SUCCESS; -} - -/*----------------------------------------------------------------------------------------*/ -/** - * Prepare PHY for Gen2 - * - * - * - * @param[in] Pcie Pointer to global PCIe configuration - */ - -VOID -PcieFmOscInitPhyForGen2 ( - IN PCIe_PLATFORM_CONFIG *Pcie - ) -{ - F12_COMPLEX_CONFIG *ComplexData; - F12_PCIe_SILICON_CONFIG *FmSilicon; - D0F0xE4_WRAP_FFF1_STRUCT D0F0xE4_WRAP_FFF1; - AGESA_STATUS Status; - UINT8 SaveSbLinkAspm; - CPU_LOGICAL_ID LogicalId; - UINT32 Value; - - Value = 0; - IDS_HDT_CONSOLE (GNB_TRACE, "PcieFmOscInitPhyForGen2 Enter\n"); - ComplexData = (F12_COMPLEX_CONFIG *) PcieConfigGetChild (DESCRIPTOR_SILICON, &Pcie->Header); - FmSilicon = &ComplexData->FmSilicon; - GetLogicalIdOfCurrentCore (&LogicalId, GnbLibGetHeader (Pcie)); - - IDS_HDT_CONSOLE (GNB_TRACE, " OSC Mode - %s\n", - (FmSilicon->OscMode == OscFuses) ? "Fuses" : ( - (FmSilicon->OscMode == OscRO) ? "RO" : ( - (FmSilicon->OscMode == OscLC) ? "LC" : ( - (FmSilicon->OscMode == OscDefault) ? "Skip" : "Unknown"))) - ); - - if (FmSilicon->OscMode == OscFuses) { - D0F0xE4_WRAP_FFF1.Value = PcieRegisterRead ( - &ComplexData->GppWrapper, - WRAP_SPACE (ComplexData->GppWrapper.WrapId, D0F0xE4_WRAP_FFF1_ADDRESS), - Pcie - ); - if (D0F0xE4_WRAP_FFF1.Field.ROSupportGen2) { - FmSilicon->OscMode = OscRO; - } else if (D0F0xE4_WRAP_FFF1.Field.LcSupportGen2) { - FmSilicon->OscMode = OscLC; - } else { - if ((LogicalId.Revision & (AMD_F12_LN_A0 | AMD_F12_LN_A1)) != 0) { - FmSilicon->OscMode = OscRO; - } else { - FmSilicon->OscMode = OscDefault; - } - } - IDS_HDT_CONSOLE (GNB_TRACE, " OSC Mode From Fuses - %s\n", - (FmSilicon->OscMode == OscFuses) ? "Fuses" : ( - (FmSilicon->OscMode == OscRO) ? "RO" : ( - (FmSilicon->OscMode == OscLC) ? "LC" : ( - (FmSilicon->OscMode == OscDefault) ? "Skip" : "Unknown"))) - ); - } - if (FmSilicon->OscMode != OscDefault) { - //Gang SB pif/phy lanes - PcieRegisterRMW ( - &ComplexData->GppWrapper, - PIF_SPACE (ComplexData->GppWrapper.WrapId, 0, D0F0xE4_PIF_0011_ADDRESS), - D0F0xE4_PIF_0011_MultiPif_MASK | D0F0xE4_PIF_0011_X4Lane30_MASK | D0F0xE4_PIF_0011_X4Lane74_MASK, - (1 << D0F0xE4_PIF_0011_X4Lane30_OFFSET) | (1 << D0F0xE4_PIF_0011_X4Lane74_OFFSET), - FALSE, - Pcie - ); - PcieConfigRunProcForAllWrappers ( - DESCRIPTOR_ALL_WRAPPERS, - PcieFmPreOscPifInitCallback, - NULL, - Pcie - ); - switch (FmSilicon->OscMode) { - case OscLC: - PcieRegisterWriteField ( - &ComplexData->GppWrapper, - PHY_SPACE (ComplexData->GppWrapper.WrapId, 0, D0F0xE4_PHY_2002_ADDRESS), - D0F0xE4_PHY_2002_IsLc_OFFSET, - D0F0xE4_PHY_2002_IsLc_WIDTH, - 0x1, - FALSE, - Pcie - ); - break; - case OscRO: - PcieRegisterWriteField ( - &ComplexData->GppWrapper, - PHY_SPACE (ComplexData->GppWrapper.WrapId, 0, D0F0xE4_PHY_2002_ADDRESS), - D0F0xE4_PHY_2002_RoCalEn_OFFSET, - D0F0xE4_PHY_2002_RoCalEn_WIDTH, - 0x0, - FALSE, - Pcie - ); - PcieRegisterWriteField ( - &ComplexData->GppWrapper, - PHY_SPACE (ComplexData->GppWrapper.WrapId, 0, D0F0xE4_PHY_2002_ADDRESS), - D0F0xE4_PHY_2002_RoCalEn_OFFSET, - D0F0xE4_PHY_2002_RoCalEn_WIDTH, - 0x1, - FALSE, - Pcie - ); - break; - default: - ASSERT (FALSE); - } - PcieConfigRunProcForAllWrappers ( - DESCRIPTOR_ALL_WRAPPERS, - PcieFmForceDccRecalibrationCallback, - NULL, - Pcie - ); - - SaveSbLinkAspm = ComplexData->Port8.Type.Port.PortData.LinkAspm; - ComplexData->Port8.Type.Port.PortData.LinkAspm = AspmL1; - Status = SbPcieLinkAspmControl (&ComplexData->Port8, Pcie); - ASSERT (Status == AGESA_SUCCESS); -#ifdef USE_L1_POLLING - //Use L1 Entry pooling - PciePollLinkForL1Entry (&ComplexData->Port8, Pcie); -#else - // Use SMU service - NbSmuRcuRegisterRead ( - SMUx0B_x85B0_ADDRESS, - &Value, - 1, - GnbLibGetHeader (Pcie) - ); - Value = (Value & (~0xff)) | 60; - NbSmuRcuRegisterWrite ( - SMUx0B_x85B0_ADDRESS, - &Value, - 1, - FALSE, - GnbLibGetHeader (Pcie) - ); - NbSmuServiceRequest (4, FALSE, GnbLibGetHeader (Pcie)); -#endif - ComplexData->Port8.Type.Port.PortData.LinkAspm = AspmDisabled; - SbPcieLinkAspmControl (&ComplexData->Port8, Pcie); - PciePollLinkForL0Exit (&ComplexData->Port8, Pcie); - - ComplexData->Port8.Type.Port.PortData.LinkAspm = SaveSbLinkAspm; - - PcieConfigRunProcForAllWrappers ( - DESCRIPTOR_ALL_WRAPPERS, - PcieFmPostOscPifInitCallback, - NULL, - Pcie - ); - } - IDS_HDT_CONSOLE (GNB_TRACE, "PcieFmOscInitPhyForGen2 Exit\n"); -} - -/*----------------------------------------------------------------------------------------*/ -/** - * Program receiver detection power mode - * - * - * - * @param[in] Wrapper Pointer to wrapper config descriptor - * @param[in] Pcie Pointer to global PCIe configuration - */ - -VOID -PcieFmPifSetRxDetectPowerMode ( - IN PCIe_WRAPPER_CONFIG *Wrapper, - IN PCIe_PLATFORM_CONFIG *Pcie - ) -{ - PciePifSetRxDetectPowerMode (Wrapper, Pcie); -} - -/*----------------------------------------------------------------------------------------*/ -/** - * PHY lane parameter Init - * - * - * - * @param[in] Wrapper Pointer to wrapper config descriptor - * @param[in] Buffer Pointer to buffer - * @param[in] Pcie Pointer to global PCIe configuration - */ -AGESA_STATUS -PcieFmPhyLaneInitInitCallback ( - IN PCIe_WRAPPER_CONFIG *Wrapper, - IN VOID *Buffer, - IN PCIe_PLATFORM_CONFIG *Pcie - ) -{ - UINT8 Phy; - UINT8 PhyLane; - IDS_HDT_CONSOLE (GNB_TRACE, "PcieFmPhyLaneInitInitCallback Enter\n"); - for (Phy = 0; Phy < Wrapper->NumberOfPIFs; Phy++) { - for (PhyLane = 0; PhyLane < MAX_NUM_LANE_PER_PHY; PhyLane++) { - PcieRegisterRMW ( - Wrapper, - PHY_SPACE (Wrapper->WrapId, Phy, D0F0xE4_PHY_400A_ADDRESS + PhyLane * 0x80), - D0F0xE4_PHY_400A_BiasDisInLs2_MASK | D0F0xE4_PHY_400A_Ls2ExitTime_MASK, - (1 << D0F0xE4_PHY_400A_BiasDisInLs2_OFFSET) | (1 << D0F0xE4_PHY_400A_Ls2ExitTime_OFFSET), - FALSE, - Pcie - ); - } - } - IDS_HDT_CONSOLE (GNB_TRACE, "PcieFmPhyLaneInitInitCallback Exit\n"); - return AGESA_SUCCESS; -} diff --git a/src/vendorcode/amd/agesa/f12/Proc/GNB/PCIe/Family/LN/F12PciePifServices.c b/src/vendorcode/amd/agesa/f12/Proc/GNB/PCIe/Family/LN/F12PciePifServices.c deleted file mode 100644 index f1aff83596..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/GNB/PCIe/Family/LN/F12PciePifServices.c +++ /dev/null @@ -1,120 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * Family specific PCIe PHY initialization services - * - * - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: GNB - * @e \$Revision: 48452 $ @e \$Date: 2011-03-09 12:50:44 +0800 (Wed, 09 Mar 2011) $ - * - */ -/* -***************************************************************************** -* -* Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* *************************************************************************** -* -*/ - -/*---------------------------------------------------------------------------------------- - * M O D U L E S U S E D - *---------------------------------------------------------------------------------------- - */ -#include "AGESA.h" -#include "Ids.h" -#include "Gnb.h" -#include "GnbPcie.h" -#include "GnbCommonLib.h" -#include "GnbPcieInitLibV1.h" -#include "PcieFamilyServices.h" -#include "GnbRegistersLN.h" -#include "Filecode.h" -#define FILECODE PROC_GNB_PCIE_FAMILY_LN_F12PCIEPIFSERVICES_FILECODE -/*---------------------------------------------------------------------------------------- - * D E F I N I T I O N S A N D M A C R O S - *---------------------------------------------------------------------------------------- - */ - - -/*---------------------------------------------------------------------------------------- - * T Y P E D E F S A N D S T R U C T U R E S - *---------------------------------------------------------------------------------------- - */ - - -/*---------------------------------------------------------------------------------------- - * P R O T O T Y P E S O F L O C A L F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ - - -/*----------------------------------------------------------------------------------------*/ -/** - * Set PLL mode for L1 - * - * - * @param[in] LaneBitmap Power down PLL for these lanes - * @param[in] Wrapper Pointer to Wrapper config descriptor - * @param[in] Pcie Pointer to PICe configuration data area - */ -VOID -PcieFmPifSetPllModeForL1 ( - IN UINT32 LaneBitmap, - IN PCIe_WRAPPER_CONFIG *Wrapper, - IN PCIe_PLATFORM_CONFIG *Pcie - ) -{ - UINT32 ActiveLaneBitmap; - ActiveLaneBitmap = PcieUtilGetWrapperLaneBitMap (LANE_TYPE_PCIE_PHY_NATIVE_ACTIVE | LANE_TYPE_PCIE_PHY_NATIVE_HOTPLUG, 0, Wrapper); - // This limits PLL setting to be identical for all PLL on wrapper. - if ((ActiveLaneBitmap & LaneBitmap) == ActiveLaneBitmap) { - LaneBitmap &= PcieUtilGetWrapperLaneBitMap (LANE_TYPE_PHY_NATIVE_ALL, 0, Wrapper); - PciePifSetPllModeForL1 (LaneBitmap, Wrapper, Pcie); - } -} - - -/*----------------------------------------------------------------------------------------*/ -/** - * PLL power up latency - * - * - * @param[in] Wrapper Pointer to Wrapper config descriptor - * @param[in] Pcie Pointer to PICe configuration data area - * @retval Pll wake up latency in us - */ -UINT8 -PcieFmPifGetPllPowerUpLatency ( - IN PCIe_WRAPPER_CONFIG *Wrapper, - IN PCIe_PLATFORM_CONFIG *Pcie - ) -{ - return 20; -} diff --git a/src/vendorcode/amd/agesa/f12/Proc/GNB/PCIe/Family/LN/F12PcieWrapperServices.c b/src/vendorcode/amd/agesa/f12/Proc/GNB/PCIe/Family/LN/F12PcieWrapperServices.c deleted file mode 100644 index 5823eb6b4d..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/GNB/PCIe/Family/LN/F12PcieWrapperServices.c +++ /dev/null @@ -1,841 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * Family specific PCIe wrapper configuration services - * - * - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: GNB - * @e \$Revision: 50124 $ @e \$Date: 2011-04-02 16:39:33 +0800 (Sat, 02 Apr 2011) $ - * - */ -/* -***************************************************************************** -* -* Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* *************************************************************************** -* -*/ - -/*---------------------------------------------------------------------------------------- - * M O D U L E S U S E D - *---------------------------------------------------------------------------------------- - */ -#include "AGESA.h" -#include "Ids.h" -#include "Gnb.h" -#include "GnbPcie.h" -#include "PcieFamilyServices.h" -#include "GnbCommonLib.h" -#include "GnbPcieConfig.h" -#include "GnbPcieInitLibV1.h" -#include "PcieFamilyServices.h" -#include "GnbPcieFamServices.h" -#include "LlanoDefinitions.h" -#include "GnbRegistersLN.h" -#include "Filecode.h" -#define FILECODE PROC_GNB_PCIE_FAMILY_LN_F12PCIEWRAPPERSERVICES_FILECODE -/*---------------------------------------------------------------------------------------- - * D E F I N I T I O N S A N D M A C R O S - *---------------------------------------------------------------------------------------- - */ -extern BUILD_OPT_CFG UserOptions; - -/*---------------------------------------------------------------------------------------- - * T Y P E D E F S A N D S T R U C T U R E S - *---------------------------------------------------------------------------------------- - */ - - -/*---------------------------------------------------------------------------------------- - * P R O T O T Y P E S O F L O C A L F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ - - -AGESA_STATUS -STATIC -PcieLnConfigureGfxEnginesLaneAllocation ( - IN PCIe_WRAPPER_CONFIG *Wrapper, - IN PCIE_ENGINE_TYPE EngineType, - IN UINT8 ConfigurationId - ); - -AGESA_STATUS -STATIC -PcieLnConfigureGppEnginesLaneAllocation ( - IN PCIe_WRAPPER_CONFIG *Wrapper, - IN UINT8 ConfigurationId - ); - -AGESA_STATUS -STATIC -PcieLnConfigureDdiEnginesLaneAllocation ( - IN PCIe_WRAPPER_CONFIG *Wrapper, - IN UINT8 ConfigurationId - ); - -AGESA_STATUS -PcieLnGetGppConfigurationValue ( - IN UINT64 ConfigurationSignature, - OUT UINT8 *ConfigurationValue - ); - -AGESA_STATUS -PcieLnGetGfxConfigurationValue ( - IN UINT64 ConfigurationSignature, - OUT UINT8 *ConfigurationValue - ); - - -/*---------------------------------------------------------------------------------------- - * T A B L E S - *---------------------------------------------------------------------------------------- - */ -PCIE_HOST_REGISTER_ENTRY PcieInitTable [] = { - { - PHY_SPACE (GFX_WRAP_ID, 0, D0F0xE4_PHY_0009_ADDRESS), - D0F0xE4_PHY_0009_PCIePllSel_MASK, - 0x1ull << D0F0xE4_PHY_0009_PCIePllSel_OFFSET - }, - { - PHY_SPACE (GFX_WRAP_ID, 0, D0F0xE4_PHY_000A_ADDRESS), - D0F0xE4_PHY_000A_PCIePllSel_MASK, - 0x1ull << D0F0xE4_PHY_000A_PCIePllSel_OFFSET - }, - { - PHY_SPACE (GFX_WRAP_ID, 1, D0F0xE4_PHY_0009_ADDRESS), - D0F0xE4_PHY_0009_PCIePllSel_MASK, - 0x1ull << D0F0xE4_PHY_0009_PCIePllSel_OFFSET - }, - { - PHY_SPACE (GFX_WRAP_ID, 1, D0F0xE4_PHY_000A_ADDRESS), - D0F0xE4_PHY_000A_PCIePllSel_MASK, - 0x1ull << D0F0xE4_PHY_000A_PCIePllSel_OFFSET - }, - { - WRAP_SPACE (GPP_WRAP_ID, D0F0xE4_WRAP_8016_ADDRESS), - D0F0xE4_WRAP_8016_CalibAckLatency_MASK, - 0 - }, - { - PHY_SPACE (GPP_WRAP_ID, 0, D0F0xE4_PHY_2008_ADDRESS), - D0F0xE4_PHY_2008_VdDetectEn_MASK, - 0x1 << D0F0xE4_PHY_2008_VdDetectEn_OFFSET - }, - { - PHY_SPACE (GFX_WRAP_ID, 0, D0F0xE4_PHY_2008_ADDRESS), - D0F0xE4_PHY_2008_VdDetectEn_MASK, - 0x1 << D0F0xE4_PHY_2008_VdDetectEn_OFFSET - }, - { - PHY_SPACE (GFX_WRAP_ID, 1, D0F0xE4_PHY_2008_ADDRESS), - D0F0xE4_PHY_2008_VdDetectEn_MASK, - 0x1 << D0F0xE4_PHY_2008_VdDetectEn_OFFSET - }, - { - PHY_SPACE (DDI_WRAP_ID, 0, D0F0xE4_PHY_2008_ADDRESS), - D0F0xE4_PHY_2008_VdDetectEn_MASK, - 0x1 << D0F0xE4_PHY_2008_VdDetectEn_OFFSET - } -}; - -/*----------------------------------------------------------------------------------------*/ -/** - * Configure engine list to support lane allocation according to configuration ID. - * - * - * - * @param[in] Wrapper Pointer to wrapper config descriptor - * @param[in] EngineType Engine Type - * @param[in] ConfigurationId Configuration ID - * @retval AGESA_SUCCESS Configuration successfully applied - * @retval AGESA_UNSUPPORTED No more configuration available for given engine type - * @retval AGESA_ERROR Requested configuration not supported - */ -AGESA_STATUS -PcieFmConfigureEnginesLaneAllocation ( - IN PCIe_WRAPPER_CONFIG *Wrapper, - IN PCIE_ENGINE_TYPE EngineType, - IN UINT8 ConfigurationId - ) -{ - AGESA_STATUS Status; - Status = AGESA_ERROR; - switch (Wrapper->WrapId) { - case GFX_WRAP_ID: - Status = PcieLnConfigureGfxEnginesLaneAllocation (Wrapper, EngineType, ConfigurationId); - break; - case GPP_WRAP_ID: - if (EngineType != PciePortEngine) { - return AGESA_UNSUPPORTED; - } - Status = PcieLnConfigureGppEnginesLaneAllocation (Wrapper, ConfigurationId); - break; - case DDI_WRAP_ID: - if (EngineType != PcieDdiEngine) { - return AGESA_UNSUPPORTED; - } - Status = PcieLnConfigureDdiEnginesLaneAllocation (Wrapper, ConfigurationId); - break; - default: - ASSERT (FALSE); - - } - return Status; -} - -CONST UINT8 GfxPortLaneConfigurationTable [][NUMBER_OF_GFX_PORTS * 2] = { - {0, 15, UNUSED_LANE_ID, UNUSED_LANE_ID}, - {0, 7, 8, 15} -}; - -/*----------------------------------------------------------------------------------------*/ -/** - * Configure GFX engine list to support lane allocation according to configuration ID. - * - * - * - * @param[in] Wrapper Pointer to wrapper config descriptor - * @param[in] ConfigurationId Configuration ID - * @retval AGESA_SUCCESS Configuration successfully applied - * @retval AGESA_ERROR Requested configuration not supported - */ - -AGESA_STATUS -STATIC -PcieLnConfigureGfxPortEnginesLaneAllocation ( - IN PCIe_WRAPPER_CONFIG *Wrapper, - IN UINT8 ConfigurationId - ) -{ - UINTN CoreLaneIndex; - PCIe_ENGINE_CONFIG *EnginesList; - if (ConfigurationId > ((sizeof (GfxPortLaneConfigurationTable) / (NUMBER_OF_GFX_PORTS * 2)) - 1)) { - return AGESA_ERROR; - } - EnginesList = PcieConfigGetChildEngine (Wrapper); - CoreLaneIndex = 0; - while (EnginesList != NULL) { - if (PcieLibIsPcieEngine (EnginesList)) { - PcieConfigResetDescriptorFlags (EnginesList, DESCRIPTOR_ALLOCATED); - EnginesList->Type.Port.StartCoreLane = GfxPortLaneConfigurationTable [ConfigurationId][CoreLaneIndex++]; - EnginesList->Type.Port.EndCoreLane = GfxPortLaneConfigurationTable [ConfigurationId][CoreLaneIndex++]; - } - EnginesList = PcieLibGetNextDescriptor (EnginesList); - } - return AGESA_SUCCESS; -} - -CONST UINT8 GfxDdiLaneConfigurationTable [][NUMBER_OF_GFX_DDIS * 2] = { - {0, 7, 8, 15, UNUSED_LANE_ID, UNUSED_LANE_ID, UNUSED_LANE_ID, UNUSED_LANE_ID}, - {0, 7, 8, 11, 12, 15, UNUSED_LANE_ID, UNUSED_LANE_ID}, - {0, 3, 4, 7, 8, 15, UNUSED_LANE_ID, UNUSED_LANE_ID}, - {0, 3, 4, 7, 8, 11, 12, 15} -}; -/*----------------------------------------------------------------------------------------*/ -/** - * Configure GFX engine list to support lane allocation according to configuration ID. - * - * - * - * @param[in] Wrapper Pointer to wrapper config descriptor - * @param[in] ConfigurationId Configuration ID - * @retval AGESA_SUCCESS Configuration successfully applied - * @retval AGESA_ERROR Requested configuration not supported - */ - -AGESA_STATUS -STATIC -PcieLnConfigureGfxDdiEnginesLaneAllocation ( - IN PCIe_WRAPPER_CONFIG *Wrapper, - IN UINT8 ConfigurationId - ) -{ - UINTN LaneIndex; - PCIe_ENGINE_CONFIG *EnginesList; - if (ConfigurationId > ((sizeof (GfxDdiLaneConfigurationTable) / (NUMBER_OF_GFX_DDIS * 2)) - 1)) { - return AGESA_ERROR; - } - LaneIndex = 0; - EnginesList = PcieConfigGetChildEngine (Wrapper); - while (EnginesList != NULL) { - if (PcieLibIsDdiEngine (EnginesList)) { - PcieConfigResetDescriptorFlags (EnginesList, DESCRIPTOR_ALLOCATED); - EnginesList->EngineData.StartLane = GfxDdiLaneConfigurationTable [ConfigurationId][LaneIndex++] + Wrapper->StartPhyLane; - EnginesList->EngineData.EndLane = GfxDdiLaneConfigurationTable [ConfigurationId][LaneIndex++] + Wrapper->StartPhyLane; - } - EnginesList = PcieLibGetNextDescriptor (EnginesList); - } - return AGESA_SUCCESS; -} - -/*----------------------------------------------------------------------------------------*/ -/** - * Configure GFX engine list to support lane allocation according to configuration ID. - * - * - * - * @param[in] Wrapper Pointer to wrapper config descriptor - * @param[in] EngineType Engine Type - * @param[in] ConfigurationId Configuration ID - * @retval AGESA_SUCCESS Configuration successfully applied - * @retval AGESA_UNSUPPORTED Configuration not applicable - * @retval AGESA_ERROR Requested configuration not supported - */ - -AGESA_STATUS -STATIC -PcieLnConfigureGfxEnginesLaneAllocation ( - IN PCIe_WRAPPER_CONFIG *Wrapper, - IN PCIE_ENGINE_TYPE EngineType, - IN UINT8 ConfigurationId - ) -{ - AGESA_STATUS Status; - - switch (EngineType) { - case PciePortEngine: - Status = PcieLnConfigureGfxPortEnginesLaneAllocation (Wrapper, ConfigurationId); - break; - case PcieDdiEngine: - Status = PcieLnConfigureGfxDdiEnginesLaneAllocation (Wrapper, ConfigurationId); - break; - default: - Status = AGESA_UNSUPPORTED; - } - return Status; -} - - - -CONST UINT8 GppLaneConfigurationTable [][NUMBER_OF_GPP_PORTS * 2] = { -//4 5 6 7 8 (SB) - {4, 7, UNUSED_LANE_ID, UNUSED_LANE_ID, UNUSED_LANE_ID, UNUSED_LANE_ID, UNUSED_LANE_ID, UNUSED_LANE_ID, 0, 3}, - {4, 5, 6, 7, UNUSED_LANE_ID, UNUSED_LANE_ID, UNUSED_LANE_ID, UNUSED_LANE_ID, 0, 3}, - {4, 5, UNUSED_LANE_ID, UNUSED_LANE_ID, 6, 7, UNUSED_LANE_ID, UNUSED_LANE_ID, 0, 3}, - {4, 5, 6, 6, 7, 7, UNUSED_LANE_ID, UNUSED_LANE_ID, 0, 3}, - {4, 5, UNUSED_LANE_ID, UNUSED_LANE_ID, 6, 6, 7, 7, 0, 3}, - {4, 4, 5, 5, 6, 6, 7, 7, 0, 3} -}; - -CONST UINT8 GppPortIdConfigurationTable [][NUMBER_OF_GPP_PORTS] = { -//4 5 6 7 8 (SB) - {1, 2, 3, 4, 0}, - {1, 2, 3, 4, 0}, - {1, 3, 2, 4, 0}, - {1, 2, 3, 4, 0}, - {1, 4, 2, 3, 0}, - {1, 2, 3, 4, 0} -}; - -/*----------------------------------------------------------------------------------------*/ -/** - * Configure GFX engine list to support lane allocation according to configuration ID. - * - * - * - * @param[in] Wrapper Pointer to wrapper config descriptor - * @param[in] ConfigurationId Configuration ID - * @retval AGESA_SUCCESS Configuration successfully applied - * @retval AGESA_ERROR Requested configuration not supported - */ - - -AGESA_STATUS -STATIC -PcieLnConfigureGppEnginesLaneAllocation ( - IN PCIe_WRAPPER_CONFIG *Wrapper, - IN UINT8 ConfigurationId - ) -{ - PCIe_ENGINE_CONFIG *EnginesList; - UINTN CoreLaneIndex; - UINTN PortIdIndex; - if (ConfigurationId > ((sizeof (GppLaneConfigurationTable) / (NUMBER_OF_GPP_PORTS * 2)) - 1)) { - return AGESA_ERROR; - } - EnginesList = PcieConfigGetChildEngine (Wrapper); - CoreLaneIndex = 0; - PortIdIndex = 0; - while (EnginesList != NULL) { - PcieConfigResetDescriptorFlags (EnginesList, DESCRIPTOR_ALLOCATED); - EnginesList->Type.Port.PortId = GppPortIdConfigurationTable [ConfigurationId][PortIdIndex++]; - EnginesList->Type.Port.StartCoreLane = GppLaneConfigurationTable [ConfigurationId][CoreLaneIndex++]; - EnginesList->Type.Port.EndCoreLane = GppLaneConfigurationTable [ConfigurationId][CoreLaneIndex++]; - EnginesList = PcieLibGetNextDescriptor (EnginesList); - } - return AGESA_SUCCESS; -} - - -CONST UINT8 DdiLaneConfigurationTable [][NUMBER_OF_DDIS * 2] = { - {0, 3, 4, 7}, - {0, 7, UNUSED_LANE_ID, UNUSED_LANE_ID} -}; - -/*----------------------------------------------------------------------------------------*/ -/** - * Configure DDI engine list to support lane allocation according to configuration ID. - * - * - * - * @param[in] Wrapper Pointer to wrapper config descriptor - * @param[in] ConfigurationId Configuration ID - * @retval AGESA_SUCCESS Configuration successfully applied - * @retval AGESA_ERROR Requested configuration not supported - */ - - -AGESA_STATUS -STATIC -PcieLnConfigureDdiEnginesLaneAllocation ( - IN PCIe_WRAPPER_CONFIG *Wrapper, - IN UINT8 ConfigurationId - ) -{ - PCIe_ENGINE_CONFIG *EnginesList; - UINTN LaneIndex; - EnginesList = PcieConfigGetChildEngine (Wrapper); - if (ConfigurationId > ((sizeof (DdiLaneConfigurationTable) / (NUMBER_OF_DDIS * 2)) - 1)) { - return AGESA_ERROR; - } - LaneIndex = 0; - while (EnginesList != NULL) { - PcieConfigResetDescriptorFlags (EnginesList, DESCRIPTOR_ALLOCATED); - EnginesList->EngineData.StartLane = DdiLaneConfigurationTable [ConfigurationId][LaneIndex++] + Wrapper->StartPhyLane; - EnginesList->EngineData.EndLane = DdiLaneConfigurationTable [ConfigurationId][LaneIndex++] + Wrapper->StartPhyLane; - EnginesList = PcieLibGetNextDescriptor (EnginesList); - } - return AGESA_SUCCESS; -} - -/*----------------------------------------------------------------------------------------*/ -/** - * Get configuration Value for GFX wrapper - * - * - * - * @param[in] ConfigurationSignature Configuration signature - * @param[out] ConfigurationValue Configuration value - * @retval AGESA_SUCCESS Correct core configuration value returned by in *ConfigurationValue - * @retval AGESA_ERROR ConfigurationSignature is incorrect. - */ -AGESA_STATUS -PcieLnGetGfxConfigurationValue ( - IN UINT64 ConfigurationSignature, - OUT UINT8 *ConfigurationValue - ) -{ - switch (ConfigurationSignature) { - case GFX_CORE_x16: - *ConfigurationValue = 0; - break; - case GFX_CORE_x8x8: - *ConfigurationValue = 0x5; - break; - default: - ASSERT (FALSE); - return AGESA_ERROR; - } - return AGESA_SUCCESS; -} - -/*----------------------------------------------------------------------------------------*/ -/** - * Get configuration Value for GPP wrapper - * - * - * - * @param[in] ConfigurationSignature Configuration signature - * @param[out] ConfigurationValue Configuration value - * @retval AGESA_SUCCESS Correct core configuration value returned by in *ConfigurationValue - * @retval AGESA_ERROR ConfigurationSignature is incorrect - */ -AGESA_STATUS -PcieLnGetGppConfigurationValue ( - IN UINT64 ConfigurationSignature, - OUT UINT8 *ConfigurationValue - ) -{ - switch (ConfigurationSignature) { - case GPP_CORE_x4x1x1x1x1: - *ConfigurationValue = 0x4; - break; - case GPP_CORE_x4x2x1x1: - case GPP_CORE_x4x2x1x1_ST: - //Configuration 2:1:1 - Device Numbers 4:5:6 - //Configuration 2:1:1 - Device Numbers 4:6:7 - *ConfigurationValue = 0x3; - break; - case GPP_CORE_x4x2x2: - case GPP_CORE_x4x2x2_ST: - //Configuration 2:2 - Device Numbers 4:5 - //Configuration 2:2 - Device Numbers 4:6 - *ConfigurationValue = 0x2; - break; - case GPP_CORE_x4x4: - *ConfigurationValue = 0x1; - break; - default: - ASSERT (FALSE); - return AGESA_ERROR; - } - return AGESA_SUCCESS; -} - -/*----------------------------------------------------------------------------------------*/ -/** - * Get core configuration value - * - * - * - * @param[in] Wrapper Pointer to internal configuration data area - * @param[in] CoreId Core ID - * @param[in] ConfigurationSignature Configuration signature - * @param[out] ConfigurationValue Configuration value (for core configuration) - * @retval AGESA_SUCCESS Configuration successfully applied - * @retval AGESA_ERROR Core configuration value can not be determined - */ -AGESA_STATUS -PcieFmGetCoreConfigurationValue ( - IN PCIe_WRAPPER_CONFIG *Wrapper, - IN UINT8 CoreId, - IN UINT64 ConfigurationSignature, - IN UINT8 *ConfigurationValue - ) -{ - AGESA_STATUS Status; - - if (Wrapper->WrapId == GFX_WRAP_ID) { - Status = PcieLnGetGfxConfigurationValue (ConfigurationSignature, ConfigurationValue); - } else if (Wrapper->WrapId == GPP_WRAP_ID) { - Status = PcieLnGetGppConfigurationValue (ConfigurationSignature, ConfigurationValue); - } else { - Status = AGESA_ERROR; - } - return Status; -} - -/*----------------------------------------------------------------------------------------*/ -/** - * Get max link speed capability supported by this port - * - * - * - * @param[in] Flags See Flags PCIE_PORT_GEN_CAP_BOOT / PCIE_PORT_GEN_CAP_MAX - * @param[in] Engine Pointer to engine config descriptor - * @retval PcieGen1/PcieGen2 Max supported link gen capability - */ -PCIE_LINK_SPEED_CAP -PcieFmGetLinkSpeedCap ( - IN UINT32 Flags, - IN PCIe_ENGINE_CONFIG *Engine - ) -{ - PCIE_LINK_SPEED_CAP LinkSpeedCapability; - F12_COMPLEX_CONFIG *ComplexData; - PCIe_PLATFORM_CONFIG *Pcie; - - ASSERT (Engine->Type.Port.PortData.LinkSpeedCapability < MaxPcieGen); - Pcie = (PCIe_PLATFORM_CONFIG *) PcieConfigGetParent (DESCRIPTOR_PLATFORM, &Engine->Header); - LinkSpeedCapability = PcieGen2; - ComplexData = (F12_COMPLEX_CONFIG *) PcieConfigGetParent (DESCRIPTOR_SILICON, &Engine->Header); - if (ComplexData->FmSilicon.OscMode == OscRO || ComplexData->FmSilicon.OscMode == OscLC || ComplexData->FmSilicon.OscMode == OscDefault) { - LinkSpeedCapability = PcieGen2; - } else { - LinkSpeedCapability = PcieGen1; - } - if (Engine->Type.Port.PortData.LinkSpeedCapability == PcieGenMaxSupported) { - Engine->Type.Port.PortData.LinkSpeedCapability = (UINT8) LinkSpeedCapability; - } - if (Pcie->PsppPolicy == PsppPowerSaving) { - LinkSpeedCapability = PcieGen1; - } - if (Engine->Type.Port.PortData.LinkSpeedCapability < LinkSpeedCapability) { - LinkSpeedCapability = Engine->Type.Port.PortData.LinkSpeedCapability; - } - if ((Flags & PCIE_PORT_GEN_CAP_BOOT) != 0) { - if (Pcie->PsppPolicy == PsppBalanceLow || Engine->Type.Port.PortData.MiscControls.LinkSafeMode == PcieGen1) { - LinkSpeedCapability = PcieGen1; - } - } - return LinkSpeedCapability; -} - -/*----------------------------------------------------------------------------------------*/ -/** - * Various initialization needed prior topology and configuration initialization - * - * - * - * @param[in] Pcie Pointer to global PCIe configuration - * - */ -VOID -PcieFmPreInit ( - IN PCIe_PLATFORM_CONFIG *Pcie - ) -{ - UINT32 Index; - PCIe_SILICON_CONFIG *Silicon; - Silicon = PcieConfigGetChildSilicon (&Pcie->ComplexList[0]); - - PcieConfigRunProcForAllWrappers ( - DESCRIPTOR_ALL_WRAPPERS, - PcieFmPhyLetPllPersonalityInitCallback, - NULL, - Pcie - ); - PcieFmOscInitPhyForGen2 (Pcie); - - PcieConfigRunProcForAllWrappers ( - DESCRIPTOR_PCIE_WRAPPER, - PcieFmPhyLaneInitInitCallback, - NULL, - Pcie - ); - - for (Index = 0; Index < (sizeof (PcieInitTable) / sizeof (PCIE_HOST_REGISTER_ENTRY)); Index++) { - PcieSiliconRegisterRMW ( - Silicon, - PcieInitTable[Index].Reg, - PcieInitTable[Index].Mask, - PcieInitTable[Index].Data, - FALSE, - Pcie - ); - } - - // Set PCIe SSID. - PcieSiliconRegisterRMW ( - Silicon, - WRAP_SPACE (0, D0F0xE4_WRAP_8002_ADDRESS), - D0F0xE4_WRAP_8002_PcieWrapScratch_MASK, - UserOptions.CfgGnbPcieSSID << D0F0xE4_WRAP_8002_PcieWrapScratch_OFFSET, - FALSE, - Pcie - ); - - PcieSiliconRegisterRMW ( - Silicon, - WRAP_SPACE (1, D0F0xE4_WRAP_8002_ADDRESS), - D0F0xE4_WRAP_8002_PcieWrapScratch_MASK, - UserOptions.CfgGnbPcieSSID << D0F0xE4_WRAP_8002_PcieWrapScratch_OFFSET, - FALSE, - Pcie - ); -} - -/*----------------------------------------------------------------------------------------*/ -/** - * Check if engine can be remapped to Device/function number requested by user - * defined engine descriptor - * - * Function only called if requested device/function does not much native device/function - * - * @param[in] PortDescriptor Pointer to user defined engine descriptor - * @param[in] Engine Pointer engine configuration - * @retval TRUE Descriptor can be mapped to engine - * @retval FALSE Descriptor can NOT be mapped to engine - */ - -BOOLEAN -PcieFmCheckPortPciDeviceMapping ( - IN PCIe_PORT_DESCRIPTOR *PortDescriptor, - IN PCIe_ENGINE_CONFIG *Engine - ) -{ - return FALSE; -} - -/*----------------------------------------------------------------------------------------*/ -/** - * Get core configuration string - * - * Debug function for logging configuration - * - * @param[in] Wrapper Pointer to internal configuration data area - * @param[in] ConfigurationValue Configuration value - * @retval Configuration string - */ - -CONST CHAR8* -PcieFmDebugGetCoreConfigurationString ( - IN PCIe_WRAPPER_CONFIG *Wrapper, - IN UINT8 ConfigurationValue - ) -{ - switch (ConfigurationValue) { - case 0: - return (CONST CHAR8*) "1x16"; - case 5: - return (CONST CHAR8*) "2x8"; - case 4: - return (CONST CHAR8*) "1x4, 4x1"; - case 3: - return (CONST CHAR8*) "1x4, 1x2, 2x1"; - case 2: - return (CONST CHAR8*) "1x4, 2x2"; - case 1: - return (CONST CHAR8*) "1x4, 1x4"; - default: - break; - } - return (CONST CHAR8*) " !!! Something Wrong !!!"; -} - -/*----------------------------------------------------------------------------------------*/ -/** - * Get wrapper name - * - * Debug function for logging wrapper name - * - * @param[in] Wrapper Pointer to internal configuration data area - * @retval Wrapper Name string - */ - -CONST CHAR8* -PcieFmDebugGetWrapperNameString ( - IN PCIe_WRAPPER_CONFIG *Wrapper - ) -{ - switch (Wrapper->WrapId) { - case GPP_WRAP_ID: - return (CONST CHAR8*) "GPPSB"; - case GFX_WRAP_ID: - return (CONST CHAR8*) "GFX"; - case DDI_WRAP_ID: - return (CONST CHAR8*) "DDI"; - default: - break; - } - return (CONST CHAR8*) " !!! Something Wrong !!!"; -} - -/*----------------------------------------------------------------------------------------*/ -/** - * Get register address name - * - * Debug function for logging register trace - * - * @param[in] Silicon Silicon config descriptor - * @param[in] AddressFrame Address Frame - * @retval Register address name - */ -CONST CHAR8* -PcieFmDebugGetHostRegAddressSpaceString ( - IN PCIe_SILICON_CONFIG *Silicon, - IN UINT16 AddressFrame - ) -{ - switch (AddressFrame) { - case 0x130: - return (CONST CHAR8*) "GPP WRAP"; - case 0x131: - return (CONST CHAR8*) "GFX WRAP"; - case 0x132: - return (CONST CHAR8*) "DDI WRAP"; - case 0x110: - return (CONST CHAR8*) "GPP PIF0"; - case 0x111: - return (CONST CHAR8*) "GFX PIF0"; - case 0x211: - return (CONST CHAR8*) "GFX PIF1"; - case 0x112: - return (CONST CHAR8*) "DDI PIF0"; - case 0x120: - return (CONST CHAR8*) "GPP PHY0"; - case 0x121: - return (CONST CHAR8*) "GFX PHY0"; - case 0x221: - return (CONST CHAR8*) "GFX PHY1"; - case 0x122: - return (CONST CHAR8*) "DDI PHY0"; - case 0x101: - return (CONST CHAR8*) "GPP CORE"; - case 0x201: - return (CONST CHAR8*) "GFX CORE"; - default: - break; - } - return (CONST CHAR8*) " !!! Something Wrong !!!"; -} - - -/*----------------------------------------------------------------------------------------*/ -/** - * Check if the lane can be muxed by link width requested by user - * defined engine descriptor - * - * Check Engine StartCoreLane could be aligned by user requested link width(x1, x2, x4, x8, x16). - * Check Engine StartCoreLane could be aligned by user requested link width x2. - * - * @param[in] PortDescriptor Pointer to user defined engine descriptor - * @param[in] Engine Pointer engine configuration - * @retval TRUE Lane can be muxed - * @retval FALSE LAne can NOT be muxed - */ - -BOOLEAN -PcieFmCheckPortPcieLaneCanBeMuxed ( - IN PCIe_PORT_DESCRIPTOR *PortDescriptor, - IN PCIe_ENGINE_CONFIG *Engine - ) -{ - UINT16 DescriptorHiLane; - UINT16 DescriptorLoLane; - UINT16 DescriptorNumberOfLanes; - PCIe_WRAPPER_CONFIG *Wrapper; - UINT16 NormalizedLoPhyLane; - BOOLEAN Result; - - Result = FALSE; - Wrapper = PcieConfigGetParentWrapper (Engine); - DescriptorLoLane = MIN (PortDescriptor->EngineData.StartLane, PortDescriptor->EngineData.EndLane); - DescriptorHiLane = MAX (PortDescriptor->EngineData.StartLane, PortDescriptor->EngineData.EndLane); - DescriptorNumberOfLanes = DescriptorHiLane - DescriptorLoLane + 1; - - NormalizedLoPhyLane = DescriptorLoLane - Wrapper->StartPhyLane; - - if (NormalizedLoPhyLane == Engine->Type.Port.StartCoreLane) { - Result = TRUE; - } else { - if ((PortDescriptor->Port.MiscControls.SbLink == 0x0) && (((Engine->Type.Port.StartCoreLane % 2) == 0) || (Engine->Type.Port.StartCoreLane == 0))) { - if (NormalizedLoPhyLane == 0) { - Result = TRUE; - } else { - if (((NormalizedLoPhyLane % 2) == 0) && ((NormalizedLoPhyLane % DescriptorNumberOfLanes) == 0)) { - Result = TRUE; - } - } - } - } - return Result; -} diff --git a/src/vendorcode/amd/agesa/f12/Proc/GNB/PCIe/Family/LN/LlanoComplexData.h b/src/vendorcode/amd/agesa/f12/Proc/GNB/PCIe/Family/LN/LlanoComplexData.h deleted file mode 100644 index f15374e748..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/GNB/PCIe/Family/LN/LlanoComplexData.h +++ /dev/null @@ -1,391 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * Family specific PCIe configuration data definition - * - * - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: GNB - * @e \$Revision: 49532 $ @e \$Date: 2011-03-25 02:54:43 +0800 (Fri, 25 Mar 2011) $ - * - */ -/* -***************************************************************************** -* -* Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* *************************************************************************** -* -*/ -#ifndef _LLANOCOMPLEXDATA_H_ -#define _LLANOCOMPLEXDATA_H_ - - -F12_COMPLEX_CONFIG ComplexData = { - //Silicon - { - { - DESCRIPTOR_SILICON | DESCRIPTOR_TERMINATE_LIST | DESCRIPTOR_TERMINATE_GNB | DESCRIPTOR_TERMINATE_TOPOLOGY, - 0, - 0, - offsetof (F12_COMPLEX_CONFIG, GfxWrapper) - offsetof (F12_COMPLEX_CONFIG, Silicon) - }, - 0, - }, - //Gfx Wrapper - { - { - DESCRIPTOR_PCIE_WRAPPER | DESCRIPTOR_DDI_WRAPPER, - offsetof (F12_COMPLEX_CONFIG, GfxWrapper) - offsetof (F12_COMPLEX_CONFIG, Silicon), - offsetof (F12_COMPLEX_CONFIG, GppWrapper) - offsetof (F12_COMPLEX_CONFIG, GfxWrapper), - offsetof (F12_COMPLEX_CONFIG, Port2) - offsetof (F12_COMPLEX_CONFIG, GfxWrapper) - }, - GFX_WRAP_ID, - GFX_NUMBER_OF_PIFs, - GFX_START_PHY_LANE, - GFX_END_PHY_LANE, - GFX_CORE_ID, - GFX_CORE_ID, - 16, - { - 1, //PowerOffUnusedLanesEnabled, - 1, //PowerOffUnusedPllsEnabled - 1, //ClkGating - 1, //LclkGating - 1, //TxclkGatingPllPowerDown - 1 //PllOffInL1 - }, - }, - //Gpp Wrapper - { - { - DESCRIPTOR_PCIE_WRAPPER, - offsetof (F12_COMPLEX_CONFIG, GppWrapper) - offsetof (F12_COMPLEX_CONFIG, Silicon), - offsetof (F12_COMPLEX_CONFIG, DdiWrapper) - offsetof (F12_COMPLEX_CONFIG, GppWrapper), - offsetof (F12_COMPLEX_CONFIG, Port4) - offsetof (F12_COMPLEX_CONFIG, GppWrapper) - }, - GPP_WRAP_ID, - GPP_NUMBER_OF_PIFs, - GPP_START_PHY_LANE, - GPP_END_PHY_LANE, - GPP_CORE_ID, - GPP_CORE_ID, - 8, - { - 1, //PowerOffUnusedLanesEnabled, - 1, //PowerOffUnusedPllsEnabled - 1, //ClkGating - 1, //LclkGating - 1, //TxclkGatingPllPowerDown - 1 //PllOffInL1 - }, - }, - //DDI Wrapper - { - { - DESCRIPTOR_DDI_WRAPPER | DESCRIPTOR_TERMINATE_LIST | DESCRIPTOR_TERMINATE_GNB | DESCRIPTOR_TERMINATE_TOPOLOGY, - offsetof (F12_COMPLEX_CONFIG, DdiWrapper) - offsetof (F12_COMPLEX_CONFIG, Silicon), - 0, - offsetof (F12_COMPLEX_CONFIG, Dpa) - offsetof (F12_COMPLEX_CONFIG, DdiWrapper) - }, - DDI_WRAP_ID, - DDI_NUMBER_OF_PIFs, - DDI_START_PHY_LANE, - DDI_END_PHY_LANE, - 0x0f, - 0x0, - 8, - { - 1, //PowerOffUnusedLanesEnabled, - 1, //PowerOffUnusedPllsEnabled - 1, //ClkGating - 1, //LclkGating - 1, //TxclkGatingPllPowerDown - 0 //PllOffInL1 - }, - }, - //Port 2 - { - { - DESCRIPTOR_PCIE_ENGINE, - offsetof (F12_COMPLEX_CONFIG, Port2) - offsetof (F12_COMPLEX_CONFIG, GfxWrapper), - offsetof (F12_COMPLEX_CONFIG, Port3) - offsetof (F12_COMPLEX_CONFIG, Port2), - 0 - }, - { PciePortEngine, 8, 23}, - 0, //Initialization Status - 0xFF, //Scratch - { - { - {0}, - 0, - 15, - 2, - 0, - GFX_CORE_ID, - 0, - {0}, - LinkStateResetExit - }, - }, - }, - //Port 3 - { - { - DESCRIPTOR_PCIE_ENGINE, - offsetof (F12_COMPLEX_CONFIG, Port3) - offsetof (F12_COMPLEX_CONFIG, GfxWrapper), - offsetof (F12_COMPLEX_CONFIG, Dp1) - offsetof (F12_COMPLEX_CONFIG, Port3), - 0 - }, - { PciePortEngine, UNUSED_LANE_ID, UNUSED_LANE_ID }, - 0, //Initialization Status - 0xFF, //Scratch - { - { - {0}, - UNUSED_LANE_ID, - UNUSED_LANE_ID, - 3, - 0, - GFX_CORE_ID, - 1, - {0}, - LinkStateResetExit - }, - }, - }, - //Ddi1 - { - { - DESCRIPTOR_DDI_ENGINE, - offsetof (F12_COMPLEX_CONFIG, Dp1) - offsetof (F12_COMPLEX_CONFIG, GfxWrapper), - offsetof (F12_COMPLEX_CONFIG, Dp2) - offsetof (F12_COMPLEX_CONFIG, Dp1), - 0 - }, - {PcieDdiEngine}, - 0, //Initialization Status - 0xFF //Scratch - }, - //Ddi2 - { - { - DESCRIPTOR_DDI_ENGINE, - offsetof (F12_COMPLEX_CONFIG, Dp2) - offsetof (F12_COMPLEX_CONFIG, GfxWrapper), - offsetof (F12_COMPLEX_CONFIG, Dp3) - offsetof (F12_COMPLEX_CONFIG, Dp2), - 0 - }, - {PcieDdiEngine}, - 0, //Initialization Status - 0xFF //Scratch - }, - //Ddi3 - { - { - DESCRIPTOR_DDI_ENGINE, - offsetof (F12_COMPLEX_CONFIG, Dp3) - offsetof (F12_COMPLEX_CONFIG, GfxWrapper), - offsetof (F12_COMPLEX_CONFIG, Dp4) - offsetof (F12_COMPLEX_CONFIG, Dp3), - 0 - }, - {PcieDdiEngine}, - 0, //Initialization Status - 0xFF //Scratch - }, - //Ddi4 - { - { - DESCRIPTOR_DDI_ENGINE | DESCRIPTOR_TERMINATE_LIST, - offsetof (F12_COMPLEX_CONFIG, Dp4) - offsetof (F12_COMPLEX_CONFIG, GfxWrapper), - offsetof (F12_COMPLEX_CONFIG, Port4) - offsetof (F12_COMPLEX_CONFIG, Dp4), - 0 - }, - {PcieDdiEngine}, - 0, //Initialization Status - 0xFF //Scratch - }, - //Port 4 - { - { - DESCRIPTOR_PCIE_ENGINE, - offsetof (F12_COMPLEX_CONFIG, Port4) - offsetof (F12_COMPLEX_CONFIG, GppWrapper), - offsetof (F12_COMPLEX_CONFIG, Port5) - offsetof (F12_COMPLEX_CONFIG, Port4), - 0 - }, - { PciePortEngine, 4, 4}, - 0, //Initialization Status - 0xFF, //Scratch - { - { - {0}, - 4, - 4, - 4, - 0, - GPP_CORE_ID, - 1, - {0}, - LinkStateResetExit - }, - }, - }, - //Port 5 - { - { - DESCRIPTOR_PCIE_ENGINE, - offsetof (F12_COMPLEX_CONFIG, Port5) - offsetof (F12_COMPLEX_CONFIG, GppWrapper), - offsetof (F12_COMPLEX_CONFIG, Port6) - offsetof (F12_COMPLEX_CONFIG, Port5), - 0 - }, - { PciePortEngine, 5, 5}, - 0, //Initialization Status - 0xFF, //Scratch - { - { - {0}, - 5, - 5, - 5, - 0, - GPP_CORE_ID, - 2, - {0}, - LinkStateResetExit - }, - }, - }, - //Port 6 - { - { - DESCRIPTOR_PCIE_ENGINE, - offsetof (F12_COMPLEX_CONFIG, Port6) - offsetof (F12_COMPLEX_CONFIG, GppWrapper), - offsetof (F12_COMPLEX_CONFIG, Port7) - offsetof (F12_COMPLEX_CONFIG, Port6), - 0 - }, - { PciePortEngine, 6, 6 }, - 0, //Initialization Status - 0xFF, //Scratch - { - { - {0}, - 6, - 6, - 6, - 0, - GPP_CORE_ID, - 3, - {0}, - LinkStateResetExit - }, - }, - }, - //Port 7 - { - { - DESCRIPTOR_PCIE_ENGINE, - offsetof (F12_COMPLEX_CONFIG, Port7) - offsetof (F12_COMPLEX_CONFIG, GppWrapper), - offsetof (F12_COMPLEX_CONFIG, Port8) - offsetof (F12_COMPLEX_CONFIG, Port7), - 0 - }, - { PciePortEngine, 7, 7 }, - 0, //Initialization Status - 0xFF, //Scratch - { - { - {0}, - 7, - 7, - 7, - 0, - GPP_CORE_ID, - 4, - {0}, - LinkStateResetExit - }, - }, - }, - //Port 8 - { - { - DESCRIPTOR_PCIE_ENGINE | DESCRIPTOR_TERMINATE_LIST, - offsetof (F12_COMPLEX_CONFIG, Port8) - offsetof (F12_COMPLEX_CONFIG, GppWrapper), - offsetof (F12_COMPLEX_CONFIG, Dpa) - offsetof (F12_COMPLEX_CONFIG, Port8), - 0 - }, - { PciePortEngine, 0, 3 }, - INIT_STATUS_PCIE_TRAINING_SUCCESS, //Initialization Status - 0xFF, //Scratch - { - { - {PortEnabled, 0, 8, 0, PcieGenMaxSupported, AspmL0sL1, HotplugDisabled, 0x0, {0}}, - 0, - 3, - 8, - 0, - GPP_CORE_ID, - 0, - {MAKE_SBDFO (0, 0, 8, 0, 0)}, - LinkStateTrainingSuccess - }, - }, - }, - //DpA - { - { - DESCRIPTOR_DDI_ENGINE, - offsetof (F12_COMPLEX_CONFIG, Dpa) - offsetof (F12_COMPLEX_CONFIG, DdiWrapper), - offsetof (F12_COMPLEX_CONFIG, Dpb) - offsetof (F12_COMPLEX_CONFIG, Dpa), - 0 - }, - {PcieDdiEngine}, - 0, //Initialization Status - 0xFF //Scratch - }, - //DpB - { - { - DESCRIPTOR_DDI_ENGINE | DESCRIPTOR_TERMINATE_LIST | DESCRIPTOR_TERMINATE_GNB | DESCRIPTOR_TERMINATE_TOPOLOGY, - offsetof (F12_COMPLEX_CONFIG, Dpb) - offsetof (F12_COMPLEX_CONFIG, DdiWrapper), - 0, - 0 - }, - {PcieDdiEngine}, - 0, //Initialization Status - 0xFF //Scratch - }, - //F12 specific Silicon - { - OscFuses - } -}; - -PCIe_PORT_DESCRIPTOR DefaultSbPort = { - 0, - PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 0, 3), - PCIE_PORT_DATA_INITIALIZER (PortEnabled, ChannelTypeLowLoss, 8, HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, AspmL0sL1, 0) -}; - -#endif diff --git a/src/vendorcode/amd/agesa/f12/Proc/GNB/PCIe/Family/LN/LlanoDefinitions.h b/src/vendorcode/amd/agesa/f12/Proc/GNB/PCIe/Family/LN/LlanoDefinitions.h deleted file mode 100644 index 2d657feaf6..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/GNB/PCIe/Family/LN/LlanoDefinitions.h +++ /dev/null @@ -1,129 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * Family specific PCIe definitions - * - * - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: GNB - * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $ - * - */ -/* -***************************************************************************** -* -* Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* *************************************************************************** -* -*/ -#ifndef _LLANODEFINITIONS_H_ -#define _LLANODEFINITIONS_H_ - -#define SOCKET_ID 0 - -#define MAX_NUM_PHYs 2 -#define MAX_NUM_LANE_PER_PHY 8 - -#define NUMBER_OF_PORTS 8 -#define NUMBER_OF_GPP_PORTS 5 -#define NUMBER_OF_GFX_PORTS 2 -#define NUMBER_OF_GFX_DDIS 4 -#define NUMBER_OF_DDIS 2 -#define NUMBER_OF_WRAPPERS 3 -#define NUMBER_OF_SILICONS 1 - -#define GFX_WRAP_ID 1 -#define GFX_NUMBER_OF_PIFs 2 -#define GFX_START_PHY_LANE 8 -#define GFX_END_PHY_LANE 23 -#define GFX_CORE_ID 2 - -#define GFX_CORE_x16 ((16 << 8) | 0) -#define GFX_CORE_x8x8 ((8 << 8) | 8) - -#define GPP_WRAP_ID 0 -#define GPP_NUMBER_OF_PIFs 1 -#define GPP_START_PHY_LANE 0 -#define GPP_END_PHY_LANE 7 -#define GPP_CORE_ID 1 - -#define GPP_CORE_x4x1x1x1x1 ((1ull << 32) | (1ull << 24) | (1ull << 16) | (1ull << 8) | (4ull << 0)) -#define GPP_CORE_x4x2x1x1 ((2ull << 32) | (1ull << 24) | (1ull << 16) | (0ull << 8) | (4ull << 0)) -#define GPP_CORE_x4x2x1x1_ST ((2ull << 32) | (0ull << 24) | (1ull << 16) | (1ull << 8) | (4ull << 0)) -#define GPP_CORE_x4x2x2 ((2ull << 32) | (2ull << 24) | (0ull << 16) | (0ull << 8) | (4ull << 0)) -#define GPP_CORE_x4x2x2_ST ((2ull << 32) | (0ull << 24) | (2ull << 16) | (0ull << 8) | (4ull << 0)) -#define GPP_CORE_x4x4 ((4ull << 32) | (0ull << 24) | (0ull << 16) | (0ull << 8) | (4ull << 0)) - -#define DDI_WRAP_ID 2 -#define DDI_NUMBER_OF_PIFs 1 -#define DDI_START_PHY_LANE 24 -#define DDI_END_PHY_LANE 31 - -///Gen2 capability -typedef enum { - OscFuses, ///< Not capable - OscRO, ///< Gen2 with RO - OscLC, ///< Gen2 with LC - OscDefault, ///< Skip initialization of OSC -} OSC_MODE; - -///Family specific silicon configuration -typedef struct { - OSC_MODE OscMode; ///>= 1; - } -} - - -/*----------------------------------------------------------------------------------------*/ -/** - * Pll access required - * - * @param[in] PllId Pll ID - * @param[in] AccessRequired Access required - * @param[in] Pcie Pointer to global PCIe configuration - */ -VOID -STATIC -PciePowerGatePllControl ( - IN UINT8 PllId, - IN BOOLEAN AccessRequired, - IN PCIe_PLATFORM_CONFIG *Pcie - ) -{ - UINT32 Value; - IDS_HDT_CONSOLE (GNB_TRACE, "PciePowerGatePllControl Enter\n"); - NbSmuRcuRegisterRead (0x859C, &Value, 1, GnbLibGetHeader (Pcie)); - Value = (Value & 0xFFFFFF00) | PllId; - NbSmuRcuRegisterWrite (0x859C, &Value, 1, TRUE, GnbLibGetHeader (Pcie)); - NbSmuServiceRequest (AccessRequired ? 0x18 : 0x17, TRUE, GnbLibGetHeader (Pcie)); - IDS_HDT_CONSOLE (GNB_TRACE, "PciePowerGatePllControl Exit\n"); -} - -/*----------------------------------------------------------------------------------------*/ -/** - * Report used lanes to SMU. - * - * - * @param[in] Wrapper Wrapper configuration descriptor - * @param[in, out] Buffer Not used - * @param[in] Pcie Pointer to global PCIe configuration - * @retval AGESA_STATUS - */ - -AGESA_STATUS -STATIC -PciePowerGateReportUsedLanesCallback ( - IN PCIe_WRAPPER_CONFIG *Wrapper, - IN OUT VOID *Buffer, - IN PCIe_PLATFORM_CONFIG *Pcie - ) -{ - UINT32 LaneBitmap; - LaneBitmap = PcieUtilGetWrapperLaneBitMap (LANE_TYPE_PCIE_PHY_NATIVE_ACTIVE | LANE_TYPE_DDI_PHY_NATIVE_ACTIVE | LANE_TYPE_PCIE_PHY_NATIVE_HOTPLUG, 0, Wrapper); - if (LaneBitmap != 0) { - PcieSmuPowerGateLanes (LaneBitmap, Wrapper->StartPhyLane, 0x14, 0x1, 0x0, 0x0, Pcie); - } - return AGESA_SUCCESS; -} - -/*----------------------------------------------------------------------------------------*/ -/** - * PCIe PowerGate PHY lanes - * - * - * @param[in] Wrapper Wrapper configuration descriptor - * @param[out] Buffer Pointer to Boolean to report if DDI lanes present - * @param[in] Pcie Pointer to global PCIe configuration - * @retval AGESA_STATUS - */ - -AGESA_STATUS -STATIC -PciePowerGatePhyLaneCallback ( - IN PCIe_WRAPPER_CONFIG *Wrapper, - IN OUT VOID *Buffer, - IN PCIe_PLATFORM_CONFIG *Pcie - ) -{ - UINT32 LaneBitmap; - BOOLEAN *IsDdiPresent; - IsDdiPresent = (BOOLEAN*) Buffer; - LaneBitmap = PcieUtilGetWrapperLaneBitMap ( - LANE_TYPE_PHY_NATIVE_ALL, - LANE_TYPE_PCIE_PHY_NATIVE_ACTIVE | LANE_TYPE_DDI_PHY_NATIVE_ACTIVE | LANE_TYPE_PCIE_PHY_NATIVE_HOTPLUG, - Wrapper - ); - if (LaneBitmap != 0) { - PcieSmuPowerGateLanes (LaneBitmap, Wrapper->StartPhyLane, 0x13, 0x1, 0x1, 0x1, Pcie); - } - // Powergate inactive hotplug lanes - LaneBitmap = PcieUtilGetWrapperLaneBitMap (LANE_TYPE_PCIE_PHY_NATIVE_HOTPLUG, LANE_TYPE_PCIE_PHY_NATIVE_ACTIVE, Wrapper); - if (LaneBitmap != 0) { - PcieSmuPowerGateLanes (LaneBitmap, Wrapper->StartPhyLane, 0x13, 0x0, 0x1, 0x1, Pcie); - } - // Powergate DDI lanes - LaneBitmap = PcieUtilGetWrapperLaneBitMap (LANE_TYPE_DDI_PHY_NATIVE_ACTIVE, 0, Wrapper); - if (LaneBitmap != 0) { - *IsDdiPresent = TRUE; - PcieSmuPowerGateLanes (LaneBitmap, Wrapper->StartPhyLane, 0x13, 0x0, 0x0, 0x1, Pcie); - } - return AGESA_SUCCESS; -} - -/*----------------------------------------------------------------------------------------*/ -/** - * PCIe PowerGate PHY lanes - * - * - * - * @param[in] StdHeader Standard Configuration Header - * @retval AGESA_STATUS - */ - -AGESA_STATUS -STATIC -PciePowerGatePhyLane ( - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - AGESA_STATUS Status; - AGESA_STATUS AgesaStatus; - BOOLEAN IsDdiPresent; - PCIe_PLATFORM_CONFIG *Pcie; - AgesaStatus = AGESA_SUCCESS; - IDS_HDT_CONSOLE (GNB_TRACE, "PciePowerGatePhyLane Enter\n"); - Status = PcieLocateConfigurationData (StdHeader, &Pcie); - ASSERT (Status == AGESA_SUCCESS); - AGESA_STATUS_UPDATE (Status, AgesaStatus); - if (Status == AGESA_SUCCESS) { - PciePortsVisibilityControl (UnhidePorts, Pcie); - IsDdiPresent = FALSE; - Status = PcieConfigRunProcForAllWrappers (DESCRIPTOR_ALL_WRAPPERS, PciePowerGateReportUsedLanesCallback, NULL, Pcie ); - AGESA_STATUS_UPDATE (Status, AgesaStatus); - PciePowerGatePllControl (0x1, TRUE, Pcie); - Status = PcieConfigRunProcForAllWrappers (DESCRIPTOR_ALL_WRAPPERS, PciePowerGatePhyLaneCallback, &IsDdiPresent, Pcie ); - AGESA_STATUS_UPDATE (Status, AgesaStatus); - if (!IsDdiPresent) { - PciePowerGatePllControl (0x1, FALSE, Pcie); - } - PciePortsVisibilityControl (HidePorts, Pcie); - } - IDS_HDT_CONSOLE (GNB_TRACE, "PciePowerGatePhyLane Exit\n"); - return Status; -} - -/*----------------------------------------------------------------------------------------*/ -/** - * Power PCIe block - * - * - * - * @param[in] StdHeader Pointer to Standard configuration - * @retval AGESA_STATUS - */ - -AGESA_STATUS -PciePowerGateFeature ( - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - PCIE_POWERGATE_CONFIG PciePowerGate; - AGESA_STATUS Status; - UINT32 Flags; - IDS_HDT_CONSOLE (GNB_TRACE, "PciePowerGateFeature Enter\n"); - Status = AGESA_SUCCESS; - PciePowerGate.Services.PciePowerGate = 0x1; - PciePowerGate.Services.PciePhyLanePowerGate = 0x1; - LibAmdMemCopy (&PciePowerGate.Pcie, &PciePowerGatingData, sizeof (POWER_GATE_DATA), StdHeader); - IDS_OPTION_CALLOUT (IDS_CALLOUT_GNB_PCIE_POWERGATE_CONFIG, &PciePowerGate, StdHeader); - Flags = 0; - if (PciePowerGate.Services.PciePowerGate == 0x0) { - IDS_HDT_CONSOLE (PCIE_MISC, " Pcie Power Gating - Disabled\n"); - Flags |= FORCE_PCIE_POWERGATING_DISABLE; - } - if (PciePowerGate.Services.PciePhyLanePowerGate == 0x0) { - IDS_HDT_CONSOLE (PCIE_MISC, " Pcie Phy Power Gating - Disabled\n"); - Flags |= FORCE_PCIE_PHY_POWERGATING_DISABLE; - } - if (Flags != 0) { - UINT32 Value; - NbSmuRcuRegisterRead (SMUx0B_x842C_ADDRESS, &Value, 1, StdHeader); - Value |= Flags; - NbSmuRcuRegisterWrite (SMUx0B_x842C_ADDRESS, &Value, 1, TRUE, StdHeader); - } - - PcieSmuPowerGatingInit (StdHeader, &PciePowerGate.Pcie); - Status = PciePowerGatePhyLane (StdHeader); - IDS_HDT_CONSOLE (GNB_TRACE, "PciePowerGateFeature Exit [0x%x]\n", Status); - return Status; -} diff --git a/src/vendorcode/amd/agesa/f12/Proc/GNB/PCIe/Feature/PciePowerGate.h b/src/vendorcode/amd/agesa/f12/Proc/GNB/PCIe/Feature/PciePowerGate.h deleted file mode 100644 index 235246409c..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/GNB/PCIe/Feature/PciePowerGate.h +++ /dev/null @@ -1,73 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * Service procedure to calculate PCIe topology segment maximum exit latency - * - * - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: GNB - * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $ - * - */ -/* -***************************************************************************** -* -* Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* *************************************************************************** -* -*/ - -#ifndef _PCIEPOWERGATE_H_ -#define _PCIEPOWERGATE_H_ - -/// PCIe power gate configuration -typedef struct { - struct { - UINT32 PciePowerGate :1; ///< Enable core power gating - UINT32 PciePhyLanePowerGate:1; ///< Enable phy lane power gating - } Services; ///< Power gating services - POWER_GATE_DATA Pcie; ///< PCIe Power gating Data -} PCIE_POWERGATE_CONFIG; - -/// PCIe PHY power gate config -typedef struct { - UINT32 Rx :1; ///< RX state - UINT32 Tx :1; ///< TX state - UINT32 Core :1; ///< Core - UINT32 Reserved :13; ///< reserved - UINT32 LowerLaneId :8; ///< Lower lane ID - UINT32 UpperLaneId :8; ///< Upper lane ID -} PCIe_PHY_POWER_GATE; - -AGESA_STATUS -PciePowerGateFeature ( - IN AMD_CONFIG_PARAMS *StdHeader - ); - -#endif diff --git a/src/vendorcode/amd/agesa/f12/Proc/GNB/PCIe/Makefile.inc b/src/vendorcode/amd/agesa/f12/Proc/GNB/PCIe/Makefile.inc deleted file mode 100644 index 4da756ed9e..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/GNB/PCIe/Makefile.inc +++ /dev/null @@ -1,8 +0,0 @@ -libagesa-y += PcieInit.c -libagesa-y += PcieInitAtEarlyPost.c -libagesa-y += PcieInitAtEnv.c -libagesa-y += PcieInitAtLatePost.c -libagesa-y += PcieInitAtPost.c -libagesa-y += PcieLateInit.c -libagesa-y += PciePortInit.c -libagesa-y += PciePortLateInit.c diff --git a/src/vendorcode/amd/agesa/f12/Proc/GNB/PCIe/PcieInit.c b/src/vendorcode/amd/agesa/f12/Proc/GNB/PCIe/PcieInit.c deleted file mode 100644 index 1f16b7f89f..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/GNB/PCIe/PcieInit.c +++ /dev/null @@ -1,366 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * Pre-training PCIe subsystem initialization routines. - * - * - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: GNB - * @e \$Revision: 48452 $ @e \$Date: 2011-03-09 12:50:44 +0800 (Wed, 09 Mar 2011) $ - * - */ -/* -***************************************************************************** -* -* Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* *************************************************************************** -* -*/ - -/*---------------------------------------------------------------------------------------- - * M O D U L E S U S E D - *---------------------------------------------------------------------------------------- - */ - -#include "AGESA.h" -#include "Ids.h" -#include "Gnb.h" -#include "GnbPcie.h" -#include "GnbPcieFamServices.h" -#include "PcieFamilyServices.h" -#include "PcieInit.h" -#include "GnbPcieInitLibV1.h" -#include "GnbPcieConfig.h" -#include "GnbPcieTrainingV1.h" -#include "GnbRegistersLN.h" -#include "Filecode.h" -#define FILECODE PROC_GNB_PCIE_PCIEINIT_FILECODE -/*---------------------------------------------------------------------------------------- - * D E F I N I T I O N S A N D M A C R O S - *---------------------------------------------------------------------------------------- - */ - - -/*---------------------------------------------------------------------------------------- - * T Y P E D E F S A N D S T R U C T U R E S - *---------------------------------------------------------------------------------------- - */ - - -/*---------------------------------------------------------------------------------------- - * P R O T O T Y P E S O F L O C A L F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ -VOID -PcieCommonCoreInit ( - IN PCIe_WRAPPER_CONFIG *Wrapper, - IN PCIe_PLATFORM_CONFIG *Pcie - ); - -AGESA_STATUS -PcieInitSrbmCallback ( - IN PCIe_WRAPPER_CONFIG *Wrapper, - IN OUT VOID *Buffer, - IN PCIe_PLATFORM_CONFIG *Pcie - ); - -AGESA_STATUS -PcieInitCallback ( - IN PCIe_WRAPPER_CONFIG *Wrapper, - IN OUT VOID *Buffer, - IN PCIe_PLATFORM_CONFIG *Pcie - ); - -AGESA_STATUS -PciePostInitCallback ( - IN PCIe_WRAPPER_CONFIG *Wrapper, - IN OUT VOID *Buffer, - IN PCIe_PLATFORM_CONFIG *Pcie - ); - - -/*----------------------------------------------------------------------------------------*/ -/** - * Control port visibility in PCI config space - * - * - * @param[in] Control Make port Hide/Unhide ports - * @param[in] Pcie Pointer to global PCIe configuration - */ -VOID -PciePortsVisibilityControl ( - IN PCIE_PORT_VISIBILITY Control, - IN PCIe_PLATFORM_CONFIG *Pcie - ) -{ - PCIe_COMPLEX_CONFIG *ComplexList; - ComplexList = &Pcie->ComplexList[0]; - while (ComplexList != NULL) { - PCIe_SILICON_CONFIG *SiliconList; - SiliconList = PcieConfigGetChildSilicon (ComplexList); - while (SiliconList != NULL) { - PcieFmPortVisabilityControl (Control, SiliconList, Pcie); - SiliconList = PcieLibGetNextDescriptor (SiliconList); - } - ComplexList = PcieLibGetNextDescriptor (ComplexList); - } -} - - -PCIE_HOST_REGISTER_ENTRY CoreInitTable [] = { - { - D0F0xE4_CORE_0020_ADDRESS, - D0F0xE4_CORE_0020_CiRcOrderingDis_MASK, - (0x1 << D0F0xE4_CORE_0020_CiRcOrderingDis_OFFSET) - }, - { - D0F0xE4_CORE_0010_ADDRESS, - D0F0xE4_CORE_0010_RxSbAdjPayloadSize_MASK, - (0x4 << D0F0xE4_CORE_0010_RxSbAdjPayloadSize_OFFSET) - }, - { - D0F0xE4_CORE_001C_ADDRESS, - D0F0xE4_CORE_001C_TxArbRoundRobinEn_MASK | - D0F0xE4_CORE_001C_TxArbSlvLimit_MASK | - D0F0xE4_CORE_001C_TxArbMstLimit_MASK, - (0x1 << D0F0xE4_CORE_001C_TxArbRoundRobinEn_OFFSET) | - (0x4 << D0F0xE4_CORE_001C_TxArbSlvLimit_OFFSET) | - (0x4 << D0F0xE4_CORE_001C_TxArbMstLimit_OFFSET) - }, - { - D0F0xE4_CORE_0040_ADDRESS, - D0F0xE4_CORE_0040_PElecIdleMode_MASK, - (0x2 << D0F0xE4_CORE_0040_PElecIdleMode_OFFSET) - }, - { - D0F0xE4_CORE_0002_ADDRESS, - D0F0xE4_CORE_0002_HwDebug_0__MASK, - (0x1 << D0F0xE4_CORE_0002_HwDebug_0__OFFSET) - }, - { - D0F0xE4_CORE_00C1_ADDRESS, - D0F0xE4_CORE_00C1_StrapLinkBwNotificationCapEn_MASK | - D0F0xE4_CORE_00C1_StrapGen2Compliance_MASK, - (0x1 << D0F0xE4_CORE_00C1_StrapLinkBwNotificationCapEn_OFFSET) | - (0x1 << D0F0xE4_CORE_00C1_StrapGen2Compliance_OFFSET) - }, - { - D0F0xE4_CORE_00B0_ADDRESS, - D0F0xE4_CORE_00B0_StrapF0MsiEn_MASK | - D0F0xE4_CORE_00B0_StrapF0AerEn_MASK, - (0x1 << D0F0xE4_CORE_00B0_StrapF0MsiEn_OFFSET) - } -}; - -/*----------------------------------------------------------------------------------------*/ -/** - * Common Core Init - * - * - * @param[in] Wrapper Pointer to wrapper configuration descriptor - * @param[in] Pcie Pointer to global PCIe configuration - */ -VOID -PcieCommonCoreInit ( - IN PCIe_WRAPPER_CONFIG *Wrapper, - IN PCIe_PLATFORM_CONFIG *Pcie - ) -{ - UINT8 CoreId; - UINTN Index; - if (PcieLibIsPcieWrapper (Wrapper)) { - IDS_HDT_CONSOLE (GNB_TRACE, "PcieCommonCoreInit Enter\n"); - for (CoreId = Wrapper->StartPcieCoreId; CoreId <= Wrapper->EndPcieCoreId; CoreId++) { - for (Index = 0; Index < sizeof (CoreInitTable) / sizeof (PCIE_HOST_REGISTER_ENTRY); Index++) { - UINT32 Value; - Value = PcieRegisterRead ( - Wrapper, - CORE_SPACE (CoreId, CoreInitTable[Index].Reg), - Pcie - ); - Value &= (~CoreInitTable[Index].Mask); - Value |= CoreInitTable[Index].Data; - PcieRegisterWrite ( - Wrapper, - CORE_SPACE (CoreId, CoreInitTable[Index].Reg), - Value, - FALSE, - Pcie - ); - } - } - IDS_HDT_CONSOLE (GNB_TRACE, "PcieCommonCoreInit Exit\n"); - } -} - - -/*----------------------------------------------------------------------------------------*/ -/** - * Per wrapper Pcie Init SRBM reset prior Aaccess to wrapper registers. - * - * - * @param[in] Wrapper Pointer to wrapper configuration descriptor - * @param[in] Buffer Pointer buffer - * @param[in] Pcie Pointer to global PCIe configuration - */ -AGESA_STATUS -PcieInitSrbmCallback ( - IN PCIe_WRAPPER_CONFIG *Wrapper, - IN OUT VOID *Buffer, - IN PCIe_PLATFORM_CONFIG *Pcie - ) -{ - PcieTopologyInitSrbmReset (TRUE, Wrapper, Pcie); - return AGESA_SUCCESS; -} -/*----------------------------------------------------------------------------------------*/ -/** - * Per wrapper Pcie Init prior training. - * - * - * @param[in] Wrapper Pointer to wrapper configuration descriptor - * @param[in] Buffer Pointer buffer - * @param[in] Pcie Pointer to global PCIe configuration - */ -AGESA_STATUS -PcieInitCallback ( - IN PCIe_WRAPPER_CONFIG *Wrapper, - IN OUT VOID *Buffer, - IN PCIe_PLATFORM_CONFIG *Pcie - ) -{ - AGESA_STATUS Status; - PcieTopologyPrepareForReconfig (Wrapper, Pcie); - Status = PcieTopologySetCoreConfig (Wrapper, Pcie); - ASSERT (Status == AGESA_SUCCESS); - PcieTopologyApplyLaneMux (Wrapper, Pcie); - PcieFmPifSetRxDetectPowerMode (Wrapper, Pcie); - PciePifSetLs2ExitTime (Wrapper, Pcie); - PcieTopologySelectMasterPll (Wrapper, Pcie); - PcieTopologyExecuteReconfig (Wrapper, Pcie); - PcieTopologySetLinkReversal (Wrapper, Pcie); - PciePifApplyGanging (Wrapper, Pcie); - PcieFmPhyApplyGanging (Wrapper, Pcie); - PciePifPllInitForDdi (Wrapper, Pcie); - PcieTopologyLaneControl ( - DisableLanes, - PcieUtilGetWrapperLaneBitMap (LANE_TYPE_CORE_ALL, LANE_TYPE_PCIE_CORE_ALLOC, Wrapper), - Wrapper, - Pcie - ); - PcieSetDdiOwnPhy (Wrapper, Pcie); - PciePollPifForCompeletion (Wrapper, Pcie); - PcieFmAvertClockPickers (Wrapper, Pcie); - PcieCommonCoreInit (Wrapper, Pcie); - PciePifDisableFifoReset (Wrapper, Pcie); - return Status; -} - -/*----------------------------------------------------------------------------------------*/ -/** - * Pcie Init - * - * - * - * @param[in] Pcie Pointer to global PCIe configuration - * @retval AGESA_SUCCESS Topology successfully mapped - * @retval AGESA_ERROR Topology can not be mapped - */ - -AGESA_STATUS -PcieInit ( - IN PCIe_PLATFORM_CONFIG *Pcie - ) -{ - AGESA_STATUS Status; - AGESA_STATUS AgesaStatus; - IDS_HDT_CONSOLE (GNB_TRACE, "PcieInit Enter\n"); - AgesaStatus = AGESA_SUCCESS; - Status = PcieConfigRunProcForAllWrappers (DESCRIPTOR_ALL_WRAPPERS, PcieInitSrbmCallback, NULL, Pcie); - AGESA_STATUS_UPDATE (Status, AgesaStatus); - PcieFmPreInit (Pcie); - Status = PcieConfigRunProcForAllWrappers (DESCRIPTOR_ALL_WRAPPERS, PcieInitCallback, NULL, Pcie); - AGESA_STATUS_UPDATE (Status, AgesaStatus); - IDS_HDT_CONSOLE (GNB_TRACE, "PcieInit Exit [%x]\n", AgesaStatus); - return AgesaStatus; -} - - -/*----------------------------------------------------------------------------------------*/ -/** - * Per wrapper Pcie Init prior training. - * - * - * @param[in] Wrapper Pointer to wrapper configuration descriptor - * @param[in] Buffer Pointer buffer - * @param[in] Pcie Pointer to global PCIe configuration - */ -AGESA_STATUS -PciePostInitCallback ( - IN PCIe_WRAPPER_CONFIG *Wrapper, - IN OUT VOID *Buffer, - IN PCIe_PLATFORM_CONFIG *Pcie - ) -{ - AGESA_STATUS Status; - Status = AGESA_SUCCESS; - return Status; -} - -/*----------------------------------------------------------------------------------------*/ -/** - * Pcie Init - * - * - * - * @param[in] Pcie Pointer to global PCIe configuration - * @retval AGESA_SUCCESS Topology successfully mapped - * @retval AGESA_ERROR Topology can not be mapped - */ - -AGESA_STATUS -PciePostInit ( - IN PCIe_PLATFORM_CONFIG *Pcie - ) -{ - AGESA_STATUS Status; - AGESA_STATUS AgesaStatus; - - IDS_HDT_CONSOLE (GNB_TRACE, "PciePostInit Enter\n"); - AgesaStatus = AGESA_SUCCESS; - Status = PcieConfigRunProcForAllWrappers (DESCRIPTOR_PCIE_WRAPPER, PciePostInitCallback, NULL, Pcie); - AGESA_STATUS_UPDATE (Status, AgesaStatus); - PcieFmSetBootUpVoltage ( - PcieUtilGlobalGenCapability (PCIE_PORT_GEN_CAP_BOOT | PCIE_GLOBAL_GEN_CAP_ALL_PORTS, Pcie), - Pcie - ); - IDS_HDT_CONSOLE (GNB_TRACE, "PciePostInit Exit [%x]\n", AgesaStatus); - return AgesaStatus; -} - diff --git a/src/vendorcode/amd/agesa/f12/Proc/GNB/PCIe/PcieInit.h b/src/vendorcode/amd/agesa/f12/Proc/GNB/PCIe/PcieInit.h deleted file mode 100644 index 47994ee52b..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/GNB/PCIe/PcieInit.h +++ /dev/null @@ -1,66 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * Pre-training PCIe subsystem initialization routines. - * - * - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: GNB - * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $ - * - */ -/* -***************************************************************************** -* -* Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* *************************************************************************** -* -*/ -#ifndef _PCIEINIT_H_ -#define _PCIEINIT_H_ - -AGESA_STATUS -PcieInit ( - IN PCIe_PLATFORM_CONFIG *Pcie - ); - -AGESA_STATUS -PciePostInit ( - IN PCIe_PLATFORM_CONFIG *Pcie - ); - -VOID -PciePortsVisibilityControl ( - IN PCIE_PORT_VISIBILITY Control, - IN PCIe_PLATFORM_CONFIG *Pcie - ); - -#endif - - diff --git a/src/vendorcode/amd/agesa/f12/Proc/GNB/PCIe/PcieInitAtEarlyPost.c b/src/vendorcode/amd/agesa/f12/Proc/GNB/PCIe/PcieInitAtEarlyPost.c deleted file mode 100644 index 60640c5238..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/GNB/PCIe/PcieInitAtEarlyPost.c +++ /dev/null @@ -1,124 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * PCIe early post initialization. - * - * - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: GNB - * @e \$Revision: 48452 $ @e \$Date: 2011-03-09 12:50:44 +0800 (Wed, 09 Mar 2011) $ - * - */ -/* -***************************************************************************** -* -* Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* *************************************************************************** -* -*/ - -/*---------------------------------------------------------------------------------------- - * M O D U L E S U S E D - *---------------------------------------------------------------------------------------- - */ - -#include "AGESA.h" -#include "Ids.h" -#include "Gnb.h" -#include "GnbPcie.h" -#include "PcieInit.h" -#include "PciePortInit.h" -#include "GnbPcieTrainingV1.h" -#include "GnbPcieConfig.h" -#include "PcieInitAtEarlyPost.h" -#include "Filecode.h" -#define FILECODE PROC_GNB_PCIE_PCIEINITATEARLYPOST_FILECODE -/*---------------------------------------------------------------------------------------- - * D E F I N I T I O N S A N D M A C R O S - *---------------------------------------------------------------------------------------- - */ - - -/*---------------------------------------------------------------------------------------- - * T Y P E D E F S A N D S T R U C T U R E S - *---------------------------------------------------------------------------------------- - */ - - -/*---------------------------------------------------------------------------------------- - * P R O T O T Y P E S O F L O C A L F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ - -/*----------------------------------------------------------------------------------------*/ -/** - * PCIe Early Post Init - * - * - * - * @param[in] StdHeader Standard configuration header - * @retval AGESA_STATUS - */ - -AGESA_STATUS -PcieInitAtEarly ( - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - AGESA_STATUS AgesaStatus; - AGESA_STATUS Status; - PCIe_PLATFORM_CONFIG *Pcie; - IDS_HDT_CONSOLE (GNB_TRACE, "PcieInitAtEarly Enter\n"); - AgesaStatus = AGESA_SUCCESS; - Status = PcieLocateConfigurationData (StdHeader, &Pcie); - AGESA_STATUS_UPDATE (Status, AgesaStatus); - if (Status != AGESA_FATAL) { - - PciePortsVisibilityControl (UnhidePorts, Pcie); - - Status = PcieInit (Pcie); - AGESA_STATUS_UPDATE (Status, AgesaStatus); - ASSERT (Status == AGESA_SUCCESS); - - Status = PciePortInit (Pcie); - AGESA_STATUS_UPDATE (Status, AgesaStatus); - ASSERT (Status == AGESA_SUCCESS); - - IDS_OPTION_CALLOUT (IDS_CALLOUT_GNB_PCIE_PHY_CONFIG, Pcie, StdHeader); - - Status = PcieTraining (Pcie); - AGESA_STATUS_UPDATE (Status, AgesaStatus); - ASSERT (Status == AGESA_SUCCESS); - - PciePortsVisibilityControl (HidePorts, Pcie); - } - IDS_HDT_CONSOLE (GNB_TRACE, "PcieInitAtEarly Exit [0x%x]\n", AgesaStatus); - return AgesaStatus; -} - diff --git a/src/vendorcode/amd/agesa/f12/Proc/GNB/PCIe/PcieInitAtEarlyPost.h b/src/vendorcode/amd/agesa/f12/Proc/GNB/PCIe/PcieInitAtEarlyPost.h deleted file mode 100644 index c018a7bab9..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/GNB/PCIe/PcieInitAtEarlyPost.h +++ /dev/null @@ -1,54 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * PCIe early post initialization. - * - * - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: GNB - * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $ - * - */ -/* -***************************************************************************** -* -* Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* *************************************************************************** -* -*/ - -#ifndef _PCIEINITATEARLYPOST_H_ -#define _PCIEINITATEARLYPOST_H_ - -AGESA_STATUS -PcieInitAtEarly ( - IN AMD_CONFIG_PARAMS *StdHeader - ); - -#endif diff --git a/src/vendorcode/amd/agesa/f12/Proc/GNB/PCIe/PcieInitAtEnv.c b/src/vendorcode/amd/agesa/f12/Proc/GNB/PCIe/PcieInitAtEnv.c deleted file mode 100644 index 146b60075d..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/GNB/PCIe/PcieInitAtEnv.c +++ /dev/null @@ -1,91 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * PCIe late post initialization. - * - * - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: GNB - * @e \$Revision: 46515 $ @e \$Date: 2011-02-04 09:15:52 +0800 (Fri, 04 Feb 2011) $ - * - */ -/* -***************************************************************************** -* -* Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* *************************************************************************** -* -*/ -/*---------------------------------------------------------------------------------------- - * M O D U L E S U S E D - *---------------------------------------------------------------------------------------- - */ -#include "AGESA.h" -#include "Ids.h" -#include "Gnb.h" -#include "GnbPcie.h" -#include "PcieInit.h" -#include "PcieInitAtEnv.h" -#include "S3SaveState.h" -#include "Filecode.h" -#define FILECODE PROC_GNB_PCIE_PCIEINITATENV_FILECODE -/*---------------------------------------------------------------------------------------- - * D E F I N I T I O N S A N D M A C R O S - *---------------------------------------------------------------------------------------- - */ - - -/*---------------------------------------------------------------------------------------- - * T Y P E D E F S A N D S T R U C T U R E S - *---------------------------------------------------------------------------------------- - */ - - -/*---------------------------------------------------------------------------------------- - * P R O T O T Y P E S O F L O C A L F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ - -/*----------------------------------------------------------------------------------------*/ -/** - * PCIe Env Init - * - * - * - * @param[in] StdHeader Standard configuration header - * @retval AGESA_STATUS - */ -AGESA_STATUS -PcieInitAtEnv ( - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - S3_SAVE_DISPATCH (StdHeader, PcieLateRestoreS3Script_ID, 0, NULL); - return AGESA_SUCCESS; -} diff --git a/src/vendorcode/amd/agesa/f12/Proc/GNB/PCIe/PcieInitAtEnv.h b/src/vendorcode/amd/agesa/f12/Proc/GNB/PCIe/PcieInitAtEnv.h deleted file mode 100644 index 6d3f0506a5..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/GNB/PCIe/PcieInitAtEnv.h +++ /dev/null @@ -1,54 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * PCIe late post initialization. - * - * - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: GNB - * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $ - * - */ -/* -***************************************************************************** -* -* Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* *************************************************************************** -* -*/ - -#ifndef _PCIEINITATENV_H_ -#define _PCIEINITATENV_H_ - -AGESA_STATUS -PcieInitAtEnv ( - IN AMD_CONFIG_PARAMS *StdHeader - ); - -#endif diff --git a/src/vendorcode/amd/agesa/f12/Proc/GNB/PCIe/PcieInitAtLatePost.c b/src/vendorcode/amd/agesa/f12/Proc/GNB/PCIe/PcieInitAtLatePost.c deleted file mode 100644 index 81939e97e2..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/GNB/PCIe/PcieInitAtLatePost.c +++ /dev/null @@ -1,113 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * PCIe late post initialization. - * - * - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: GNB - * @e \$Revision: 48452 $ @e \$Date: 2011-03-09 12:50:44 +0800 (Wed, 09 Mar 2011) $ - * - */ -/* -***************************************************************************** -* -* Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* *************************************************************************** -* -*/ -/*---------------------------------------------------------------------------------------- - * M O D U L E S U S E D - *---------------------------------------------------------------------------------------- - */ -#include "AGESA.h" -#include "Ids.h" -#include "Gnb.h" -#include "GnbPcie.h" -#include "GnbPcieConfig.h" -#include "PcieInit.h" -#include "PcieLateInit.h" -#include "PciePortLateInit.h" -#include "PcieInitAtLatePost.h" -#include "Filecode.h" -#define FILECODE PROC_GNB_PCIE_PCIEINITATLATEPOST_FILECODE -/*---------------------------------------------------------------------------------------- - * D E F I N I T I O N S A N D M A C R O S - *---------------------------------------------------------------------------------------- - */ - - -/*---------------------------------------------------------------------------------------- - * T Y P E D E F S A N D S T R U C T U R E S - *---------------------------------------------------------------------------------------- - */ - - -/*---------------------------------------------------------------------------------------- - * P R O T O T Y P E S O F L O C A L F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ - -/*----------------------------------------------------------------------------------------*/ -/** - * PCIe Mid Init - * - * - * - * @param[in] StdHeader Standard configuration header - * @retval AGESA_STATUS - */ -AGESA_STATUS -PcieInitAtMid ( - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - AGESA_STATUS AgesaStatus; - AGESA_STATUS Status; - PCIe_PLATFORM_CONFIG *Pcie; - IDS_HDT_CONSOLE (GNB_TRACE, "PcieInitAtMid Enter\n"); - AgesaStatus = AGESA_SUCCESS; - Status = PcieLocateConfigurationData (StdHeader, &Pcie); - AGESA_STATUS_UPDATE (Status, AgesaStatus); - if (Status == AGESA_SUCCESS) { - PciePortsVisibilityControl (UnhidePorts, Pcie); - - Status = PciePortLateInit (Pcie); - AGESA_STATUS_UPDATE (Status, AgesaStatus); - ASSERT (Status == AGESA_SUCCESS); - - Status = PcieLateInit (Pcie); - AGESA_STATUS_UPDATE (Status, AgesaStatus); - ASSERT (Status == AGESA_SUCCESS); - - PciePortsVisibilityControl (HidePorts, Pcie); - } - IDS_HDT_CONSOLE (GNB_TRACE, "PcieInitAtMid Exit [0x%x]\n", AgesaStatus); - return AgesaStatus; -} diff --git a/src/vendorcode/amd/agesa/f12/Proc/GNB/PCIe/PcieInitAtLatePost.h b/src/vendorcode/amd/agesa/f12/Proc/GNB/PCIe/PcieInitAtLatePost.h deleted file mode 100644 index f1444a1360..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/GNB/PCIe/PcieInitAtLatePost.h +++ /dev/null @@ -1,54 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * PCIe late post initialization. - * - * - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: GNB - * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $ - * - */ -/* -***************************************************************************** -* -* Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* *************************************************************************** -* -*/ - -#ifndef _PCIEINITATLATEPOST_H_ -#define _PCIEINITATLATEPOST_H_ - -AGESA_STATUS -PcieInitAtMid ( - IN AMD_CONFIG_PARAMS *StdHeader - ); - -#endif diff --git a/src/vendorcode/amd/agesa/f12/Proc/GNB/PCIe/PcieInitAtPost.c b/src/vendorcode/amd/agesa/f12/Proc/GNB/PCIe/PcieInitAtPost.c deleted file mode 100644 index d8c9cece8e..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/GNB/PCIe/PcieInitAtPost.c +++ /dev/null @@ -1,223 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * PCIe late post initialization. - * - * - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: GNB - * @e \$Revision: 48452 $ @e \$Date: 2011-03-09 12:50:44 +0800 (Wed, 09 Mar 2011) $ - * - */ -/* -***************************************************************************** -* -* Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* *************************************************************************** -* -*/ -/*---------------------------------------------------------------------------------------- - * M O D U L E S U S E D - *---------------------------------------------------------------------------------------- - */ -#include "AGESA.h" -#include "Ids.h" -#include "Gnb.h" -#include "GnbPcie.h" -#include "PcieInit.h" -#include "PciePortInit.h" -#include "GnbPcieInitLibV1.h" -#include "GnbPcieConfig.h" -#include "GnbPcieTrainingV1.h" -#include "PcieInitAtPost.h" -#include "Filecode.h" -#define FILECODE PROC_GNB_PCIE_PCIEINITATPOST_FILECODE -/*---------------------------------------------------------------------------------------- - * D E F I N I T I O N S A N D M A C R O S - *---------------------------------------------------------------------------------------- - */ - - -/*---------------------------------------------------------------------------------------- - * T Y P E D E F S A N D S T R U C T U R E S - *---------------------------------------------------------------------------------------- - */ - - -/*---------------------------------------------------------------------------------------- - * P R O T O T Y P E S O F L O C A L F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ - -/*----------------------------------------------------------------------------------------*/ -/** - * PCIe Post Init prior DRAM init - * - * - * - * @param[in] StdHeader Standard configuration header - * @retval AGESA_STATUS - */ -AGESA_STATUS -PcieInitAtPostEarly ( - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - AGESA_STATUS AgesaStatus; - AGESA_STATUS Status; - PCIe_PLATFORM_CONFIG *Pcie; - IDS_HDT_CONSOLE (GNB_TRACE, "PcieInitAtPostEarly Enter\n"); - AgesaStatus = AGESA_SUCCESS; - Status = PcieLocateConfigurationData (StdHeader, &Pcie); - AGESA_STATUS_UPDATE (Status, AgesaStatus); - if (Status == AGESA_SUCCESS) { - PciePortsVisibilityControl (UnhidePorts, Pcie); - - Status = PciePortPostEarlyInit (Pcie); - AGESA_STATUS_UPDATE (Status, AgesaStatus); - ASSERT (Status == AGESA_SUCCESS); - - Status = PcieTraining (Pcie); - AGESA_STATUS_UPDATE (Status, AgesaStatus); - ASSERT (Status == AGESA_SUCCESS); - - PciePortsVisibilityControl (HidePorts, Pcie); - } - IDS_HDT_CONSOLE (GNB_TRACE, "PcieInitAtPostEarly Exit [0x%x]\n", AgesaStatus); - return AgesaStatus; -} - -/*----------------------------------------------------------------------------------------*/ -/** - * PCIe Post Init - * - * - * - * @param[in] StdHeader Standard configuration header - * @retval AGESA_STATUS - */ -AGESA_STATUS -PcieInitAtPost ( - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - AGESA_STATUS AgesaStatus; - AGESA_STATUS Status; - PCIe_PLATFORM_CONFIG *Pcie; - IDS_HDT_CONSOLE (GNB_TRACE, "PcieInitAtPost Enter\n"); - AgesaStatus = AGESA_SUCCESS; - Status = PcieLocateConfigurationData (StdHeader, &Pcie); - AGESA_STATUS_UPDATE (Status, AgesaStatus); - if (Status == AGESA_SUCCESS) { - PciePortsVisibilityControl (UnhidePorts, Pcie); - - Status = PciePostInit (Pcie); - AGESA_STATUS_UPDATE (Status, AgesaStatus); - ASSERT (Status == AGESA_SUCCESS); - - Status = PciePortPostInit (Pcie); - AGESA_STATUS_UPDATE (Status, AgesaStatus); - ASSERT (Status == AGESA_SUCCESS); - - Status = PcieTraining (Pcie); - AGESA_STATUS_UPDATE (Status, AgesaStatus); - ASSERT (Status == AGESA_SUCCESS); - - PciePortsVisibilityControl (HidePorts, Pcie); - } - IDS_HDT_CONSOLE (GNB_TRACE, "PcieInitAtPost Exit [0x%x]\n", AgesaStatus); - return AgesaStatus; -} - - -/*----------------------------------------------------------------------------------------*/ -/** - * PCIe Post Init - * - * - * - * @param[in] StdHeader Standard configuration header - * @retval AGESA_STATUS - */ -AGESA_STATUS -PcieInitAtPostS3 ( - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - AGESA_STATUS AgesaStatus; - AGESA_STATUS Status; - PCIe_PLATFORM_CONFIG *Pcie; - IDS_HDT_CONSOLE (GNB_TRACE, "PcieInitAtPostS3 Enter\n"); - AgesaStatus = AGESA_SUCCESS; - Status = PcieLocateConfigurationData (StdHeader, &Pcie); - AGESA_STATUS_UPDATE (Status, AgesaStatus); - if (Status == AGESA_SUCCESS) { - PciePortsVisibilityControl (UnhidePorts, Pcie); - - Status = PciePostInit (Pcie); - AGESA_STATUS_UPDATE (Status, AgesaStatus); - ASSERT (Status == AGESA_SUCCESS); - - if (Pcie->TrainingAlgorithm == PcieTrainingDistributed) { - Status = PciePortPostS3Init (Pcie); - } else { - Status = PciePortPostInit (Pcie); - } - AGESA_STATUS_UPDATE (Status, AgesaStatus); - ASSERT (Status == AGESA_SUCCESS); - - Status = PcieTraining (Pcie); - AGESA_STATUS_UPDATE (Status, AgesaStatus); - ASSERT (Status == AGESA_SUCCESS); - - PciePortsVisibilityControl (HidePorts, Pcie); - } - IDS_HDT_CONSOLE (GNB_TRACE, "PcieInitAtPostS3 Exit [0x%x]\n", AgesaStatus); - return AgesaStatus; -} - -/*----------------------------------------------------------------------------------------*/ -/** - * PCIe S3 restore - * - * - * - * @param[in] StdHeader Standard configuration header - * @param[in] ContextLength Context Length (not used) - * @param[in] Context Context pointer (not used) - */ -VOID -PcieLateRestoreS3Script ( - IN AMD_CONFIG_PARAMS *StdHeader, - IN UINT16 ContextLength, - IN VOID* Context - ) -{ - PcieInitAtPostS3 (StdHeader); -} diff --git a/src/vendorcode/amd/agesa/f12/Proc/GNB/PCIe/PcieInitAtPost.h b/src/vendorcode/amd/agesa/f12/Proc/GNB/PCIe/PcieInitAtPost.h deleted file mode 100644 index 5eb6846954..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/GNB/PCIe/PcieInitAtPost.h +++ /dev/null @@ -1,71 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * PCIe late post initialization. - * - * - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: GNB - * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $ - * - */ -/* -***************************************************************************** -* -* Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* *************************************************************************** -* -*/ - -#ifndef _PCIEINITATPOST_H_ -#define _PCIEINITATPOST_H_ - -AGESA_STATUS -PcieInitAtPostEarly ( - IN AMD_CONFIG_PARAMS *StdHeader - ); - -AGESA_STATUS -PcieInitAtPost ( - IN AMD_CONFIG_PARAMS *StdHeader - ); - -AGESA_STATUS -PcieInitAtPostS3 ( - IN AMD_CONFIG_PARAMS *StdHeader - ); - -VOID -PcieLateRestoreS3Script ( - IN AMD_CONFIG_PARAMS *StdHeader, - IN UINT16 ContextLength, - IN VOID* Context - ); - -#endif diff --git a/src/vendorcode/amd/agesa/f12/Proc/GNB/PCIe/PcieLateInit.c b/src/vendorcode/amd/agesa/f12/Proc/GNB/PCIe/PcieLateInit.c deleted file mode 100644 index 7094ca6994..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/GNB/PCIe/PcieLateInit.c +++ /dev/null @@ -1,164 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * Pre-training PCIe subsystem initialization routines. - * - * - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: GNB - * @e \$Revision: 48452 $ @e \$Date: 2011-03-09 12:50:44 +0800 (Wed, 09 Mar 2011) $ - * - */ -/* -***************************************************************************** -* -* Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* *************************************************************************** -* -*/ - -/*---------------------------------------------------------------------------------------- - * M O D U L E S U S E D - *---------------------------------------------------------------------------------------- - */ - -#include "AGESA.h" -#include "Ids.h" -#include "Gnb.h" -#include "GnbPcie.h" -#include "PcieLateInit.h" -#include "PcieFamilyServices.h" -#include "GnbCommonLib.h" -#include "GnbPcieInitLibV1.h" -#include "GnbPcieConfig.h" -#include "GnbRegistersLN.h" -#include "Filecode.h" -#define FILECODE PROC_GNB_PCIE_PCIELATEINIT_FILECODE -/*---------------------------------------------------------------------------------------- - * D E F I N I T I O N S A N D M A C R O S - *---------------------------------------------------------------------------------------- - */ - - -/*---------------------------------------------------------------------------------------- - * T Y P E D E F S A N D S T R U C T U R E S - *---------------------------------------------------------------------------------------- - */ - - -/*---------------------------------------------------------------------------------------- - * P R O T O T Y P E S O F L O C A L F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ -VOID -PciePwrPowerDownPllInL1 ( - IN PCIe_WRAPPER_CONFIG *Wrapper, - IN PCIe_PLATFORM_CONFIG *Pcie - ); - -AGESA_STATUS -PcieLateInitCallback ( - IN PCIe_WRAPPER_CONFIG *Wrapper, - IN OUT VOID *Buffer, - IN PCIe_PLATFORM_CONFIG *Pcie - ); - -/*----------------------------------------------------------------------------------------*/ -/** - * Power down inactive lanes - * - * - * @param[in] Wrapper Pointer to wrapper config descriptor - * @param[in] Pcie Pointer to global PCIe configuration - */ - -VOID -PciePwrPowerDownPllInL1 ( - IN PCIe_WRAPPER_CONFIG *Wrapper, - IN PCIe_PLATFORM_CONFIG *Pcie - ) -{ - - UINT32 LaneBitmapForPllOffInL1; - UINT8 PllPowerUpLatency; - IDS_HDT_CONSOLE (GNB_TRACE, "PciePwrPowerDownPllInL1 Enter\n"); - PllPowerUpLatency = PcieFmPifGetPllPowerUpLatency (Wrapper, Pcie); - LaneBitmapForPllOffInL1 = PcieLanesToPowerDownPllInL1 (PllPowerUpLatency, Wrapper, Pcie); - if (LaneBitmapForPllOffInL1 != 0) { - PcieFmPifSetPllModeForL1 (LaneBitmapForPllOffInL1, Wrapper, Pcie); - } - IDS_HDT_CONSOLE (GNB_TRACE, "PciePwrPowerDownPllInL1 Exit\n"); -} - - -/*----------------------------------------------------------------------------------------*/ -/** - * Per wrapper Pcie Late Init. - * - * - * @param[in] Wrapper Pointer to wrapper configuration descriptor - * @param[in] Buffer Pointer buffer - * @param[in] Pcie Pointer to global PCIe configuration - */ -AGESA_STATUS -PcieLateInitCallback ( - IN PCIe_WRAPPER_CONFIG *Wrapper, - IN OUT VOID *Buffer, - IN PCIe_PLATFORM_CONFIG *Pcie - ) -{ - PciePwrPowerDownUnusedLanes (Wrapper, Pcie); - PciePwrPowerDownPllInL1 (Wrapper, Pcie); - PciePwrClockGating (Wrapper, Pcie); - PcieLockRegisters (Wrapper, Pcie); - return AGESA_SUCCESS; -} - -/*----------------------------------------------------------------------------------------*/ -/** - * Pcie Late Init - * - * Late PCIe initialization - * - * @param[in] Pcie Pointer to global PCIe configuration - * @retval AGESA_SUCCESS Topology successfully mapped - * @retval AGESA_ERROR Topology can not be mapped - */ - -AGESA_STATUS -PcieLateInit ( - IN PCIe_PLATFORM_CONFIG *Pcie - ) -{ - AGESA_STATUS Status; - IDS_HDT_CONSOLE (GNB_TRACE, "PcieLateInit Enter\n"); - Status = PcieConfigRunProcForAllWrappers (DESCRIPTOR_ALL_WRAPPERS, PcieLateInitCallback, NULL, Pcie); - IDS_HDT_CONSOLE (GNB_TRACE, "PcieLateInit Exit [0x%x]\n", Status); - return Status; -} diff --git a/src/vendorcode/amd/agesa/f12/Proc/GNB/PCIe/PcieLateInit.h b/src/vendorcode/amd/agesa/f12/Proc/GNB/PCIe/PcieLateInit.h deleted file mode 100644 index ae33626343..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/GNB/PCIe/PcieLateInit.h +++ /dev/null @@ -1,55 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * Late initialization routine. - * - * - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: GNB - * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $ - * - */ -/* -***************************************************************************** -* -* Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* *************************************************************************** -* -*/ - -#ifndef _PCIELATEINIT_H_ -#define _PCIELATEINIT_H_ - -AGESA_STATUS -PcieLateInit ( - IN PCIe_PLATFORM_CONFIG *Pcie - ); - -#endif - diff --git a/src/vendorcode/amd/agesa/f12/Proc/GNB/PCIe/PciePortInit.c b/src/vendorcode/amd/agesa/f12/Proc/GNB/PCIe/PciePortInit.c deleted file mode 100644 index 5ed8bd2b06..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/GNB/PCIe/PciePortInit.c +++ /dev/null @@ -1,362 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * PCIe port initialization service procedure - * - * - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: GNB - * @e \$Revision: 49774 $ @e \$Date: 2011-03-29 08:38:56 +0800 (Tue, 29 Mar 2011) $ - * - */ -/* -***************************************************************************** -* -* Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* *************************************************************************** -* -*/ - -/*---------------------------------------------------------------------------------------- - * M O D U L E S U S E D - *---------------------------------------------------------------------------------------- - */ -#include "AGESA.h" -#include "Ids.h" -#include "Gnb.h" -#include "GnbPcie.h" -#include "GnbPcieFamServices.h" -#include "PcieFamilyServices.h" -#include "GnbCommonLib.h" -#include "GnbPcieInitLibV1.h" -#include "GnbPcieConfig.h" -#include "GnbPcieTrainingV1.h" -#include "GnbRegistersLN.h" -#include "PciePortInit.h" -#include "Filecode.h" -#define FILECODE PROC_GNB_PCIE_PCIEPORTINIT_FILECODE -/*---------------------------------------------------------------------------------------- - * D E F I N I T I O N S A N D M A C R O S - *---------------------------------------------------------------------------------------- - */ - - -/*---------------------------------------------------------------------------------------- - * T Y P E D E F S A N D S T R U C T U R E S - *---------------------------------------------------------------------------------------- - */ - - -/*---------------------------------------------------------------------------------------- - * P R O T O T Y P E S O F L O C A L F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ - -PCIE_PORT_REGISTER_ENTRY PortInitTable [] = { - { - DxF0xE4_x02_ADDRESS, - DxF0xE4_x02_RegsLcAllowTxL1Control_MASK, - (0x1 << DxF0xE4_x02_RegsLcAllowTxL1Control_OFFSET) - }, - { - DxF0xE4_x70_ADDRESS, - DxF0xE4_x70_RxRcbCplTimeoutMode_MASK, - (0x1 << DxF0xE4_x70_RxRcbCplTimeoutMode_OFFSET) - }, - { - DxF0xE4_xA0_ADDRESS, - DxF0xE4_xA0_Lc16xClearTxPipe_MASK | DxF0xE4_xA0_LcL1ImmediateAck_MASK, - (0x3 << DxF0xE4_xA0_Lc16xClearTxPipe_OFFSET) | - (0x1 << DxF0xE4_xA0_LcL1ImmediateAck_OFFSET) - }, - { - DxF0xE4_xA1_ADDRESS, - DxF0xE4_xA1_LcDontGotoL0sifL1Armed_MASK, - (0x1 << DxF0xE4_xA1_LcDontGotoL0sifL1Armed_OFFSET) - }, - { - DxF0xE4_xA2_ADDRESS, - DxF0xE4_xA2_LcRenegotiateEn_MASK | DxF0xE4_xA2_LcUpconfigureSupport_MASK, - (0x1 << DxF0xE4_xA2_LcRenegotiateEn_OFFSET) | - (0x1 << DxF0xE4_xA2_LcUpconfigureSupport_OFFSET) - }, - { - DxF0xE4_xA3_ADDRESS, - DxF0xE4_xA3_LcXmitFtsBeforeRecovery_MASK, - (0x1 << DxF0xE4_xA3_LcXmitFtsBeforeRecovery_OFFSET) - }, - { - DxF0xE4_xB1_ADDRESS, - DxF0xE4_xB1_LcDeassertRxEnInL0s_MASK | DxF0xE4_xB1_LcBlockElIdleinL0_MASK, - (0x1 << DxF0xE4_xB1_LcDeassertRxEnInL0s_OFFSET) | - (0x1 << DxF0xE4_xB1_LcBlockElIdleinL0_OFFSET) - } -}; - - -/*----------------------------------------------------------------------------------------*/ -/** - * Callback to init various features on all active ports - * - * - * - * - * @param[in] Engine Pointer to engine config descriptor - * @param[in, out] Buffer Not used - * @param[in] Pcie Pointer to global PCIe configuration - * - */ - -VOID -STATIC -PciePortInitCallback ( - IN PCIe_ENGINE_CONFIG *Engine, - IN OUT VOID *Buffer, - IN PCIe_PLATFORM_CONFIG *Pcie - ) -{ - ASSERT (Engine->EngineData.EngineType == PciePortEngine); - PciePortProgramRegisterTable (PortInitTable, (sizeof (PortInitTable) / sizeof (PCIE_PORT_REGISTER_ENTRY)), Engine, FALSE, Pcie); - PcieSetLinkSpeedCap (PcieGen1, Engine, Pcie); - PcieSetLinkWidthCap (Engine, Pcie); - PcieCompletionTimeout (Engine, Pcie); - PcieLinkSetSlotCap (Engine, Pcie); - PcieLinkInitHotplug (Engine, Pcie); - PcieFmPhyChannelCharacteristic (Engine, Pcie); - if (Engine->Type.Port.PortData.MiscControls.LinkSafeMode == PcieGen1) { - PcieLinkSafeMode (Engine, Pcie); - } - if (Engine->Type.Port.PortData.PortPresent == PortDisabled) { - ASSERT (!PcieConfigIsSbPcieEngine (Engine)); - PcieTrainingSetPortState (Engine, LinkStateDeviceNotPresent, FALSE, Pcie); - } - // Train port that forced to compliance in last stage of training - if (Engine->Type.Port.PortData.MiscControls.LinkComplianceMode == 0x1) { - PcieTrainingSetPortState (Engine, LinkStateTrainingCompleted, FALSE, Pcie); - } -} - -/*----------------------------------------------------------------------------------------*/ -/** - * Master procedure to init various features on all active ports - * - * - * - * - * @param[in] Pcie Pointer to global PCIe configuration - * @retval AGESA_STATUS - * - */ - -AGESA_STATUS -PciePortInit ( - IN PCIe_PLATFORM_CONFIG *Pcie - ) -{ - AGESA_STATUS Status; - Status = AGESA_SUCCESS; - // Leave all device in Presence Detect Presence state for distributed training will be completed at PciePortPostEarlyInit - if (Pcie->TrainingAlgorithm == PcieTrainingDistributed) { - Pcie->TrainingExitState = LinkStateResetExit; - } - PcieConfigRunProcForAllEngines ( - DESCRIPTOR_ALLOCATED | DESCRIPTOR_PCIE_ENGINE, - PciePortInitCallback, - NULL, - Pcie - ); - return Status; -} - -/*----------------------------------------------------------------------------------------*/ -/** - * Callback to init various features on all ports - * - * - * - * - * @param[in] Engine Pointer to engine config descriptor - * @param[in, out] Buffer Not used - * @param[in] Pcie Pointer to global PCIe configuration - * - */ - -VOID -STATIC -PciePortPostInitCallback ( - IN PCIe_ENGINE_CONFIG *Engine, - IN OUT VOID *Buffer, - IN PCIe_PLATFORM_CONFIG *Pcie - ) -{ - PCIE_LINK_SPEED_CAP LinkSpeedCapability; - ASSERT (Engine->EngineData.EngineType == PciePortEngine); - if (Engine->Type.Port.PortData.MiscControls.LinkSafeMode == PcieGen1) { - PcieLinkSafeMode (Engine, Pcie); - } - LinkSpeedCapability = PcieFmGetLinkSpeedCap (PCIE_PORT_GEN_CAP_BOOT, Engine); - PcieSetLinkSpeedCap (LinkSpeedCapability, Engine, Pcie); - // Retrain only present port to Gen2 - if (PcieConfigCheckPortStatus (Engine, INIT_STATUS_PCIE_TRAINING_SUCCESS) && (LinkSpeedCapability > PcieGen1) && !PcieConfigIsSbPcieEngine (Engine)) { - PcieTrainingSetPortState (Engine, LinkStateRetrain, FALSE, Pcie); - PcieConfigUpdatePortStatus (Engine, 0, INIT_STATUS_PCIE_TRAINING_SUCCESS); - } - // Train ports forced to compliance - if (Engine->Type.Port.PortData.MiscControls.LinkComplianceMode == 0x1) { - PcieForceCompliance (Engine, Pcie); - PcieTrainingSetPortState (Engine, LinkStateResetExit, FALSE, Pcie); - } -} - - -/*----------------------------------------------------------------------------------------*/ -/** - * Master procedure to init various features on all active ports - * - * - * - * - * @param[in] Pcie Pointer to global PCIe configuration - * @retval AGESA_STATUS - * - */ - -AGESA_STATUS -PciePortPostInit ( - IN PCIe_PLATFORM_CONFIG *Pcie - ) -{ - AGESA_STATUS Status; - Status = AGESA_SUCCESS; - PcieConfigRunProcForAllEngines ( - DESCRIPTOR_ALLOCATED | DESCRIPTOR_PCIE_ENGINE, - PciePortPostInitCallback, - NULL, - Pcie - ); - return Status; -} - -/*----------------------------------------------------------------------------------------*/ -/** - * Callback to init various features on all ports on S3 resume path - * - * - * - * - * @param[in] Engine Pointer to engine config descriptor - * @param[in, out] Buffer Not used - * @param[in] Pcie Pointer to global PCIe configuration - * - */ - -VOID -STATIC -PciePortPostS3InitCallback ( - IN PCIe_ENGINE_CONFIG *Engine, - IN OUT VOID *Buffer, - IN PCIe_PLATFORM_CONFIG *Pcie - ) -{ - PCIE_LINK_SPEED_CAP LinkSpeedCapability; - ASSERT (Engine->EngineData.EngineType == PciePortEngine); - LinkSpeedCapability = PcieFmGetLinkSpeedCap (PCIE_PORT_GEN_CAP_BOOT, Engine); - PcieSetLinkSpeedCap (LinkSpeedCapability, Engine, Pcie); - if (Engine->Type.Port.PortData.MiscControls.LinkSafeMode == PcieGen1) { - PcieLinkSafeMode (Engine, Pcie); - } - if (Engine->Type.Port.PortData.MiscControls.LinkComplianceMode == 0x1) { - PcieForceCompliance (Engine, Pcie); - } - if (!PcieConfigIsSbPcieEngine (Engine)) { - if ((PcieConfigCheckPortStatus (Engine, INIT_STATUS_PCIE_TRAINING_SUCCESS) || - ((Engine->Type.Port.PortData.LinkHotplug != HotplugDisabled) && (Engine->Type.Port.PortData.LinkHotplug != HotplugInboard)) || - (Engine->Type.Port.PortData.MiscControls.LinkComplianceMode == 0x1))) { - PcieTrainingSetPortState (Engine, LinkStateResetExit, FALSE, Pcie); - } else { - PcieTrainingSetPortState (Engine, LinkStateDeviceNotPresent, FALSE, Pcie); - } - PcieConfigUpdatePortStatus (Engine, 0, INIT_STATUS_PCIE_TRAINING_SUCCESS); - } else { - PcieTrainingSetPortState (Engine, LinkStateTrainingSuccess, FALSE, Pcie); - } -} -/*----------------------------------------------------------------------------------------*/ -/** - * Init port on S3 resume during destributed training - * - * - * - * - * @param[in] Pcie Pointer to global PCIe configuration - * @retval AGESA_STATUS - * - */ - -AGESA_STATUS -PciePortPostS3Init ( - IN PCIe_PLATFORM_CONFIG *Pcie - ) -{ - AGESA_STATUS Status; - Status = AGESA_SUCCESS; - PcieConfigRunProcForAllEngines ( - DESCRIPTOR_ALLOCATED | DESCRIPTOR_PCIE_ENGINE, - PciePortPostS3InitCallback, - NULL, - Pcie - ); - return Status; -} - -/*----------------------------------------------------------------------------------------*/ -/** - * Master procedure to init various features on all active ports - * - * - * - * - * @param[in] Pcie Pointer to global PCIe configuration - * @retval AGESA_STATUS - * - */ - -AGESA_STATUS -PciePortPostEarlyInit ( - IN PCIe_PLATFORM_CONFIG *Pcie - ) -{ - AGESA_STATUS Status; - Status = AGESA_SUCCESS; - // Distributed Training started at PciePortInit complete it now to get access to PCIe devices - if (Pcie->TrainingAlgorithm == PcieTrainingDistributed) { - Pcie->TrainingExitState = LinkStateTrainingCompleted; - } - return Status; -} diff --git a/src/vendorcode/amd/agesa/f12/Proc/GNB/PCIe/PciePortInit.h b/src/vendorcode/amd/agesa/f12/Proc/GNB/PCIe/PciePortInit.h deleted file mode 100644 index 1208f2aa3d..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/GNB/PCIe/PciePortInit.h +++ /dev/null @@ -1,70 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * PCIe port initialization service procedure - * - * - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: GNB - * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $ - * - */ -/* -***************************************************************************** -* -* Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* *************************************************************************** -* -*/ -#ifndef _PCIEPORTINITG_H_ -#define _PCIEPORTINITG_H_ - - -AGESA_STATUS -PciePortInit ( - IN PCIe_PLATFORM_CONFIG *Pcie - ); - -AGESA_STATUS -PciePortPostInit ( - IN PCIe_PLATFORM_CONFIG *Pcie - ); - -AGESA_STATUS -PciePortPostEarlyInit ( - IN PCIe_PLATFORM_CONFIG *Pcie - ); - -AGESA_STATUS -PciePortPostS3Init ( - IN PCIe_PLATFORM_CONFIG *Pcie - ); -#endif - - diff --git a/src/vendorcode/amd/agesa/f12/Proc/GNB/PCIe/PciePortLateInit.c b/src/vendorcode/amd/agesa/f12/Proc/GNB/PCIe/PciePortLateInit.c deleted file mode 100644 index 450cde2f0c..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/GNB/PCIe/PciePortLateInit.c +++ /dev/null @@ -1,201 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * PCIe port initialization service procedure - * - * - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: GNB - * @e \$Revision: 48452 $ @e \$Date: 2011-03-09 12:50:44 +0800 (Wed, 09 Mar 2011) $ - * - */ -/* -***************************************************************************** -* -* Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* *************************************************************************** -* -*/ - -/*---------------------------------------------------------------------------------------- - * M O D U L E S U S E D - *---------------------------------------------------------------------------------------- - */ -#include "AGESA.h" -#include "Ids.h" -#include "Gnb.h" -#include "GnbPcie.h" -#include "GnbSbLib.h" -#include "PcieFamilyServices.h" -#include "GnbCommonLib.h" -#include "GnbPcieInitLibV1.h" -#include "GnbPcieConfig.h" -#include "PciePortLateInit.h" -#include "GnbRegistersLN.h" -#include "Filecode.h" -#define FILECODE PROC_GNB_PCIE_PCIEPORTLATEINIT_FILECODE -/*---------------------------------------------------------------------------------------- - * D E F I N I T I O N S A N D M A C R O S - *---------------------------------------------------------------------------------------- - */ - - -/*---------------------------------------------------------------------------------------- - * T Y P E D E F S A N D S T R U C T U R E S - *---------------------------------------------------------------------------------------- - */ - - -/*---------------------------------------------------------------------------------------- - * P R O T O T Y P E S O F L O C A L F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ -VOID -PcieSlotPowerLimit ( - IN PCIe_ENGINE_CONFIG *Engine, - IN PCIe_PLATFORM_CONFIG *Pcie - ); - - -PCIE_PORT_REGISTER_ENTRY PortLateInitTable [] = { - { - DxF0xE4_xA2_ADDRESS, - DxF0xE4_xA2_LcDynLanesPwrState_MASK, - (0x3 << DxF0xE4_xA2_LcDynLanesPwrState_OFFSET) - }, - { - DxF0xE4_xC0_ADDRESS, - DxF0xE4_xC0_StrapAutoRcSpeedNegotiationDis_MASK, - (0x1 << DxF0xE4_xC0_StrapAutoRcSpeedNegotiationDis_OFFSET) - } -}; - -/*----------------------------------------------------------------------------------------*/ -/** - * Set slot power limit - * - * - * - * @param[in] Engine Pointer to engine config descriptor - * @param[in] Pcie Pointer to global PCIe configuration - * - */ - -VOID -PcieSlotPowerLimit ( - IN PCIe_ENGINE_CONFIG *Engine, - IN PCIe_PLATFORM_CONFIG *Pcie - ) -{ - DxF0x6C_STRUCT DxF0x6C; - GnbLibPciRead ( - Engine->Type.Port.Address.AddressValue | DxF0x6C_ADDRESS, - AccessWidth32, - &DxF0x6C.Value, - GnbLibGetHeader (Pcie) - ); - - DxF0x6C.Field.SlotPwrLimitValue = 75; - DxF0x6C.Field.PhysicalSlotNumber = Engine->Type.Port.Address.Address.Device; - - GnbLibPciWrite ( - Engine->Type.Port.Address.AddressValue | DxF0x6C_ADDRESS, - AccessS3SaveWidth32, - &DxF0x6C.Value, - GnbLibGetHeader (Pcie) - ); - PcieFmEnableSlotPowerLimit (Engine, Pcie); -} - - -/*----------------------------------------------------------------------------------------*/ -/** - * Callback to init various features on all active ports - * - * - * - * - * @param[in] Engine Pointer to engine config descriptor - * @param[in, out] Buffer Not used - * @param[in] Pcie Pointer to global PCIe configuration - * - */ - -VOID -STATIC -PciePortLateInitCallback ( - IN PCIe_ENGINE_CONFIG *Engine, - IN OUT VOID *Buffer, - IN PCIe_PLATFORM_CONFIG *Pcie - ) -{ - PciePortProgramRegisterTable (PortLateInitTable, (sizeof (PortLateInitTable) / sizeof (PCIE_PORT_REGISTER_ENTRY)), Engine, TRUE, Pcie); - if (PcieConfigCheckPortStatus (Engine, INIT_STATUS_PCIE_TRAINING_SUCCESS) || Engine->Type.Port.PortData.LinkHotplug != HotplugDisabled) { - PcieSlotPowerLimit (Engine, Pcie); - } - PcieEnableAspm (Engine, Pcie); -} - -/*----------------------------------------------------------------------------------------*/ -/** - * Master procedure to init various features on all active ports - * - * - * - * - * @param[in] Pcie Pointer to global PCIe configuration - * @retval AGESA_STATUS - * - */ - -AGESA_STATUS -PciePortLateInit ( - IN PCIe_PLATFORM_CONFIG *Pcie - ) -{ - AGESA_STATUS Status; - PCIE_LINK_SPEED_CAP GlobalSpeedCap; - - Status = AGESA_SUCCESS; - PcieConfigRunProcForAllEngines ( - DESCRIPTOR_ALLOCATED | DESCRIPTOR_PCIE_ENGINE, - PciePortLateInitCallback, - NULL, - Pcie - ); - - GlobalSpeedCap = PcieUtilGlobalGenCapability ( - PCIE_PORT_GEN_CAP_BOOT | PCIE_GLOBAL_GEN_CAP_TRAINED_PORTS | PCIE_GLOBAL_GEN_CAP_HOTPLUG_PORTS, - Pcie - ); - - PcieFmSetBootUpVoltage (GlobalSpeedCap, Pcie); - - return Status; -} diff --git a/src/vendorcode/amd/agesa/f12/Proc/GNB/PCIe/PciePortLateInit.h b/src/vendorcode/amd/agesa/f12/Proc/GNB/PCIe/PciePortLateInit.h deleted file mode 100644 index 3904bb6c19..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/GNB/PCIe/PciePortLateInit.h +++ /dev/null @@ -1,54 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * PCIe port initialization service procedure - * - * - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: GNB - * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $ - * - */ -/* -***************************************************************************** -* -* Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* *************************************************************************** -* -*/ - -#ifndef _PCIEPORTLATEINIT_H_ -#define _PCIEPORTLATEINIT_H_ - -AGESA_STATUS -PciePortLateInit ( - IN PCIe_PLATFORM_CONFIG *Pcie - ); - -#endif diff --git a/src/vendorcode/amd/agesa/f12/Proc/HT/Fam12/Makefile.inc b/src/vendorcode/amd/agesa/f12/Proc/HT/Fam12/Makefile.inc deleted file mode 100644 index 3393a31432..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/HT/Fam12/Makefile.inc +++ /dev/null @@ -1,2 +0,0 @@ -libagesa-y += htNbFam12.c -libagesa-y += htNbUtilitiesFam12.c diff --git a/src/vendorcode/amd/agesa/f12/Proc/HT/Fam12/htNbFam12.c b/src/vendorcode/amd/agesa/f12/Proc/HT/Fam12/htNbFam12.c deleted file mode 100644 index d75bd49181..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/HT/Fam12/htNbFam12.c +++ /dev/null @@ -1,148 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * The initializer for Family 12h northbridge support. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: HyperTransport - * @e \$Revision: 44846 $ @e \$Date: 2011-01-07 13:21:05 +0800 (Fri, 07 Jan 2011) $ - * - */ -/* -***************************************************************************** -* -* Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* *************************************************************************** -* -*/ - -/* - *---------------------------------------------------------------------------- - * MODULES USED - * - *---------------------------------------------------------------------------- - */ - -#include "AGESA.h" -#include "amdlib.h" -#include "OptionsHt.h" -#include "Ids.h" -#include "Topology.h" -#include "htFeat.h" -#include "htNb.h" -#include "CommonReturns.h" -#include "htNbUtilitiesFam12.h" -#include "cpuFamRegisters.h" -#include "Filecode.h" -CODE_GROUP (G1_PEICC) -RDATA_GROUP (G1_PEICC) - -#define FILECODE PROC_HT_FAM12_HTNBFAM12_FILECODE - -extern OPTION_HT_CONFIGURATION OptionHtConfiguration; - -/*---------------------------------------------------------------------------- - * DEFINITIONS AND MACROS - * - *---------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------- - * TYPEDEFS AND STRUCTURES - * - *---------------------------------------------------------------------------- - */ -/*---------------------------------------------------------------------------- - * PROTOTYPES OF LOCAL FUNCTIONS - * - *---------------------------------------------------------------------------- - */ - -/*************************************************************************** - *** FAMILY/NORTHBRIDGE SPECIFIC FUNCTIONS *** - ***************************************************************************/ - - -/** - * Initial construction data for no HT Northbridge. - */ -CONST NORTHBRIDGE ROMDATA HtFam12Nb = -{ - 1, - (PF_WRITE_ROUTING_TABLE)CommonVoid, - (PF_WRITE_NODEID)CommonVoid, - (PF_READ_DEFAULT_LINK)CommonReturnZero8, - (PF_ENABLE_ROUTING_TABLES)CommonVoid, - (PF_DISABLE_ROUTING_TABLES)CommonVoid, - (PF_VERIFY_LINK_IS_COHERENT)CommonReturnFalse, - (PF_READ_TOKEN)CommonReturnZero8, - (PF_WRITE_TOKEN)CommonVoid, - (PF_WRITE_FULL_ROUTING_TABLE)CommonVoid, - (PF_IS_ILLEGAL_TYPE_MIX)CommonReturnFalse, - (PF_IS_EXCEEDED_CAPABLE)CommonReturnFalse, - (PF_STOP_LINK)CommonVoid, - (PF_HANDLE_SPECIAL_LINK_CASE)CommonReturnFalse, - (PF_HANDLE_SPECIAL_NODE_CASE)CommonReturnFalse, - (PF_READ_SB_LINK)CommonReturnZero8, - (PF_VERIFY_LINK_IS_NON_COHERENT)CommonReturnFalse, - (PF_SET_CONFIG_ADDR_MAP)CommonVoid, - (PF_NORTH_BRIDGE_FREQ_MASK)CommonReturnZero32, - (PF_GATHER_LINK_FEATURES)CommonVoid, - (PF_SET_LINK_REGANG)CommonVoid, - (PF_SET_LINK_FREQUENCY)CommonVoid, - (PF_SET_LINK_UNITID_CLUMPING)CommonVoid, - (PF_WRITE_TRAFFIC_DISTRIBUTION)CommonVoid, - (PF_WRITE_LINK_PAIR_DISTRIBUTION)CommonVoid, - (PF_WRITE_VICTIM_DISTRIBUTION)CommonVoid, - (PF_BUFFER_OPTIMIZATIONS)CommonVoid, - Fam12GetNumCoresOnNode, - (PF_SET_TOTAL_NODES_AND_CORES)CommonVoid, - Fam12GetNodeCount, - (PF_LIMIT_NODES)CommonVoid, - (PF_READ_TRUE_LINK_FAIL_STATUS)CommonReturnFalse, - (PF_GET_NEXT_LINK)CommonReturnZero32, - (PF_GET_PACKAGE_LINK)CommonReturnZero8, - (PF_MAKE_LINK_BASE)CommonReturnZero32, - (PF_GET_MODULE_INFO)CommonVoid, - (PF_POST_MAILBOX)CommonVoid, - Fam12RetrieveMailbox, - (PF_GET_SOCKET)CommonReturnZero8, - (PF_GET_ENABLED_COMPUTE_UNITS)CommonReturnZero8, - (PF_GET_DUALCORE_COMPUTE_UNITS)CommonReturnZero8, - 0, - 0, - 0, - TRUE, - TRUE, - AMD_FAMILY_12, - NULL, - 0, - NULL, - (PF_MAKE_KEY)CommonReturnZero64, - NULL -}; diff --git a/src/vendorcode/amd/agesa/f12/Proc/HT/Fam12/htNbUtilitiesFam12.c b/src/vendorcode/amd/agesa/f12/Proc/HT/Fam12/htNbUtilitiesFam12.c deleted file mode 100644 index b0932923a7..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/HT/Fam12/htNbUtilitiesFam12.c +++ /dev/null @@ -1,141 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * Northbridge utility routines. - * - * These routines are needed for support of more than one feature area. - * Collect them in this file so build options don't remove them. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: HyperTransport - * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $ - * - */ -/* -***************************************************************************** -* -* Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* *************************************************************************** -* -*/ - -/* - *---------------------------------------------------------------------------- - * MODULES USED - * - *---------------------------------------------------------------------------- - */ - - - -#include "AGESA.h" -#include "amdlib.h" -#include "Ids.h" -#include "Topology.h" -#include "htFeat.h" -#include "htNb.h" -#include "htNbCommonHardware.h" -#include "htNbUtilitiesFam12.h" -#include "Filecode.h" -CODE_GROUP (G2_PEI) -RDATA_GROUP (G2_PEI) - -#define FILECODE PROC_HT_FAM12_HTNBUTILITIESFAM12_FILECODE -/*---------------------------------------------------------------------------- - * DEFINITIONS AND MACROS - * - *---------------------------------------------------------------------------- - */ - -/*----------------------------------------------------------------------------------------*/ -/** - * Return the number of cores (1 based count) on Node. - * - * @HtNbMethod{::F_GET_NUM_CORES_ON_NODE} - * - * @param[in] Node the Node that will be examined - * @param[in] Nb this northbridge - * - * @return the number of cores - */ -UINT8 -Fam12GetNumCoresOnNode ( - IN UINT8 Node, - IN NORTHBRIDGE *Nb - ) -{ - UINT32 Cores; - PCI_ADDR Reg; - - ASSERT ((Node < MAX_NODES)); - // Read CmpCap - Reg.AddressValue = MAKE_SBDFO (MakePciSegmentFromNode (Node), - MakePciBusFromNode (Node), - MakePciDeviceFromNode (Node), - CPU_NB_FUNC_03, - REG_NB_CAPABILITY_3XE8); - - LibAmdPciReadBits (Reg, 13, 12, &Cores, Nb->ConfigHandle); - - return (UINT8) (Cores + 1); -} - -/*----------------------------------------------------------------------------------------*/ -/** - * Get the Count (1 based) of Nodes in the system. - * - * @HtNbMethod{::F_GET_NODE_COUNT} - * - * This is intended to support AP Core HT init, since the Discovery State data is not - * available (State->NodesDiscovered), there needs to be this way to find the number - * of Nodes, which is just one. - * - * @param[in] Nb this northbridge - * - * @return The number of nodes - */ -UINT8 -Fam12GetNodeCount ( - IN NORTHBRIDGE *Nb - ) -{ - ASSERT (Nb != NULL); - return (1); -} - -AP_MAIL_INFO -Fam12RetrieveMailbox ( - IN UINT8 Node, - IN NORTHBRIDGE *Nb - ) -{ - AP_MAIL_INFO NodeApMailBox; - ASSERT (Nb != NULL); - NodeApMailBox.Info = 0; - return NodeApMailBox; -} diff --git a/src/vendorcode/amd/agesa/f12/Proc/HT/Fam12/htNbUtilitiesFam12.h b/src/vendorcode/amd/agesa/f12/Proc/HT/Fam12/htNbUtilitiesFam12.h deleted file mode 100644 index 14fc79be6c..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/HT/Fam12/htNbUtilitiesFam12.h +++ /dev/null @@ -1,67 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * Northbridge utility routines. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: HyperTransport - * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $ - * - */ -/* -***************************************************************************** -* -* Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* *************************************************************************** -* -*/ - -#ifndef _HT_NB_UTILITIES_FAM12_H_ -#define _HT_NB_UTILITIES_FAM12_H_ - -/** - * Return the number of cores (1 based count) on Node. - * - */ -UINT8 -Fam12GetNumCoresOnNode ( - IN UINT8 Node, - IN NORTHBRIDGE *Nb - ); - -UINT8 -Fam12GetNodeCount ( - IN NORTHBRIDGE *Nb - ); - -AP_MAIL_INFO -Fam12RetrieveMailbox ( - IN UINT8 Node, - IN NORTHBRIDGE *Nb - ); -#endif // _HT_NB_UTILITIES_FAM12_H_ diff --git a/src/vendorcode/amd/agesa/f12/Proc/HT/Makefile.inc b/src/vendorcode/amd/agesa/f12/Proc/HT/Makefile.inc deleted file mode 100644 index f54568a1f1..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/HT/Makefile.inc +++ /dev/null @@ -1,8 +0,0 @@ -libagesa-y += htFeat.c -libagesa-y += htInterface.c -libagesa-y += htInterfaceCoherent.c -libagesa-y += htInterfaceGeneral.c -libagesa-y += htInterfaceNonCoherent.c -libagesa-y += htMain.c -libagesa-y += htNb.c -libagesa-y += htNotify.c diff --git a/src/vendorcode/amd/agesa/f12/Proc/HT/htFeat.c b/src/vendorcode/amd/agesa/f12/Proc/HT/htFeat.c deleted file mode 100644 index 5f5d6c651d..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/HT/htFeat.c +++ /dev/null @@ -1,111 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * HyperTransport features constructor. - * - * Initialize the set of available features. - * This file implements build options using conditional compilation. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: HyperTransport - * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $ - * - */ -/* - ***************************************************************************** - * - * Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * *************************************************************************** - * - */ - -/* - *---------------------------------------------------------------------------- - * MODULES USED - * - *---------------------------------------------------------------------------- - */ - - - -#include "AGESA.h" -#include "amdlib.h" -#include "OptionsHt.h" -#include "Ids.h" -#include "Topology.h" -#include "htFeat.h" -#include "CommonReturns.h" -#include "Filecode.h" -CODE_GROUP (G1_PEICC) -RDATA_GROUP (G1_PEICC) - -#define FILECODE PROC_HT_HTFEAT_FILECODE -extern CONST OPTION_HT_CONFIGURATION OptionHtConfiguration; - -/** - * A no features Initializer. - */ -CONST HT_FEATURES ROMDATA HtFeaturesNone = -{ - (PF_COHERENT_DISCOVERY)CommonVoid, - (PF_LOOKUP_COMPUTE_AND_LOAD_ROUTING_TABLES)CommonVoid, - (PF_MAKE_HOP_COUNT_TABLE)CommonVoid, - (PF_PROCESS_LINK)CommonVoid, - (PF_GATHER_LINK_DATA)CommonVoid, - (PF_SELECT_OPTIMAL_WIDTH_AND_FREQUENCY)CommonVoid, - (PF_REGANG_LINKS)CommonVoid, - (PF_SUBLINK_RATIO_FIXUP)CommonVoid, - (PF_IS_COHERENT_RETRY_FIXUP)CommonReturnFalse, - (PF_SET_LINK_DATA)CommonVoid, - (PF_TRAFFIC_DISTRIBUTION)CommonVoid, - (PF_SET_HT_CONTROL_REGISTER_BITS)CommonVoid, - (PF_CONVERT_WIDTH_TO_BITS)CommonReturnZero8 -}; - -/*----------------------------------------------------------------------------------------*/ -/** - * Provide the current Feature set implementation. - * - * Initialize using the installed initializer. - * - * @param[in] HtFeatures A feature object to initialize - * @param[in] StdHeader Opaque handle to standard config header -*/ -VOID -NewHtFeatures ( - OUT HT_FEATURES *HtFeatures, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - LibAmdMemCopy ( - (VOID *) HtFeatures, - (VOID *) OptionHtConfiguration.HtOptionInternalFeatures , - (UINT32) (sizeof (HT_FEATURES)), - StdHeader - ); -} diff --git a/src/vendorcode/amd/agesa/f12/Proc/HT/htFeat.h b/src/vendorcode/amd/agesa/f12/Proc/HT/htFeat.h deleted file mode 100644 index 2a70be461a..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/HT/htFeat.h +++ /dev/null @@ -1,561 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * HT Features. - * - * This file provides definitions used in common by HT internal modules. The - * data is private and not for external client access. - * Definitions include the HT global internal state data structures, and - * access to the available HT features from the main HT entry point. - * - * This file includes the feature constructor and feature support which is not - * removed with various build options. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: HyperTransport - * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $ - * - */ -/* -***************************************************************************** -* -* Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* *************************************************************************** -* -*/ - -#ifndef _HT_FEAT_H_ -#define _HT_FEAT_H_ - -/** - * @page htimplfeat HT Features Implementation Guide - * - * HT Features provides access to the HT Feature set, in a manner that isolates - * calling code from knowledge about the Feature set implementation or which - * features are supported in the current build. In the case of feature sets, this - * is mostly used for build options to reduce code size by removing unneeded features. - * - * @par Adding a Method to HT Features - * - * To add a new method to the HT Features, follow these steps. - *
    - *
  • Create a typedef for the Method with the correct parameters and return type. - * - *
      - *
    • Name the method typedef (F_METHOD_NAME)(), where METHOD_NAME is the same name as the method table item, - * but with "_"'s and UPPERCASE, rather than mixed case. - * @n typedef VOID (F_METHOD_NAME)(); @n - * - *
    • Make a reference type for references to a method implementation: - * @n /// Reference to a Method - * @n typedef F_METHOD_NAME *PF_METHOD_NAME @n - *
    - * - *
  • Provide a standard doxygen function preamble for the Method typedef. Begin the - * detailed description by providing a reference to the method instances page by including - * the lines below: - * @code - * * - * * @HtFeatInstances. - * * - * @endcode - * @note It is important to provide documentation for the method type, because the method may not - * have an implementation in any families supported by the current package. @n - * - *
  • Add to the _HT_FEATURES struct an item for the Method: - * @n PF_METHOD_NAME MethodName; ///< Method: description. @n - *
- * - * @par Implementing an HT Features Instance of the method. - * - * To implement an instance of a method for a specific feature follow these steps. - * - * - In appropriate files, implement the method with the return type and parameters - * matching the method typedef. - * - * - Name the function MethodName(). - * - * - Create a doxygen function preamble for the method instance. Begin the detailed description with - * an Implements command to reference the method type and add this instance to the Method Instances page. - * @code - * * - * * @HtFeatMethod{::F_METHOD_NAME}. - * * - * @endcode - * - * - To access other Ht feature routines or data as part of the method implementation, the function - * must use HtFeatures->OtherMethod(). Do not directly access other HT feature - * routines, because in the table there may be overrides or this routine may be shared by multiple configurations. - * - * - Add the instance to the HT_FEATURES instances. - * - * - If a configuration does not need an instance of the method use one of the CommonReturns from - * CommonReturns.h with the same return type. - * - * @par Invoking HT Features Methods. - * - * The first step is carried out only once by the top level HT entry point. - * @n @code - * HT_FEATURES HtFeatures; - * // Get the current HT Feature Set - * NewHtFeatures (&HtFeatures); - * State->HtFeatures = &HtFeatures; - * @endcode - * - * The following example shows how to invoke a HT Features method. - * @n @code - * State->HtFeatures->MethodName (); - * @endcode - * - */ - -/*---------------------------------------------------------------------------- - * Mixed (DEFINITIONS AND MACROS / TYPEDEFS, STRUCTURES, ENUMS) - * - *---------------------------------------------------------------------------- - */ - -/*----------------------------------------------------------------------------- - * DEFINITIONS AND MACROS - * - *----------------------------------------------------------------------------- - */ -#define MAX_PLATFORM_LINKS 64 -#define MAX_LINK_PAIRS 4 - -/* These following are internal definitions */ -#define ROUTE_TO_SELF 0x0F -#define INVALID_LINK 0xCC /* Used in port list data structure to mark unused data entries. - Can also be used for no Link found in a port list search */ - -/* definitions for working with the port list structure */ -#define PORTLIST_TYPE_CPU 0 -#define PORTLIST_TYPE_IO 1 - -/* - * Hypertransport Capability definitions and macros - * - */ - -#define HT_INTERFACE_CAP_SUBTYPE_MASK ((UINT32)0xE00000FF) -#define HT_CAP_SUBTYPE_MASK ((UINT32)0xF80000FF) - -/* HT Host Capability */ -#define HT_HOST_CAPABILITY 1 -#define HT_HOST_CAP_SIZE 0x20 - -/* Host CapabilityRegisters */ -#define HTHOST_LINK_CAPABILITY_REG 0x00 -#define HTHOST_LINK_CONTROL_REG 0x04 -#define HTHOST_FREQ_REV_REG 0x08 -#define HTHOST_REV_REV3 0x60 -#define HTHOST_FEATURE_CAP_REG 0x0C -#define HTHOST_BUFFER_COUNT_REG 0x10 -#define HTHOST_ISOC_REG 0x14 -#define HTHOST_LINK_TYPE_REG 0x18 -#define HTHOST_FREQ_EXTENSION 0x1C -#define HTHOST_TYPE_COHERENT 3 -#define HTHOST_TYPE_NONCOHERENT 7 -#define HTHOST_TYPE_MASK 0x1F - -/* HT Slave Capability (HT1 compat) */ -#define HT_SLAVE_CAPABILITY 0 -#define HTSLAVE_LINK01_OFFSET 4 -#define HTSLAVE_LINK_CONTROL_0_REG 4 -#define HTSLAVE_FREQ_REV_0_REG 0xC -#define HTSLAVE_FEATURECAP_REG 0x10 -#define HT_CONTROL_CLEAR_CRC (~(3 << 8)) -#define HT_FREQUENCY_CLEAR_LINK_ERRORS (~(0x7 << 12)) -#define MAX_BUID 31 - -/* HT3 gen Capability */ -#define HT_GEN3_CAPABILITY (0xD << 1) -#define HTGEN3_LINK01_OFFSET 0x10 -#define HTGEN3_LINK_TRAINING_0_REG 0x10 - -/* HT3 Retry Capability */ -#define HT_RETRY_CAPABILITY (0xC << 1) -#define HTRETRY_CONTROL_REG 4 - -/* Unit ID Clumping Capability */ -#define HT_UNITID_CAPABILITY (0x9 << 1) -#define HTUNIT_SUPPORT_REG 4 -#define HTUNIT_ENABLE_REG 8 -#define HT_CLUMPING_PASSIVE 1 - -/*---------------------------------------------------------------------------- - * TYPEDEFS, STRUCTURES, ENUMS - * - *---------------------------------------------------------------------------- - */ - -// Forward declarations. -/// Used for forward reference. -typedef struct _NORTHBRIDGE NORTHBRIDGE; -/// Used for forward reference. -typedef struct _HT_FEATURES HT_FEATURES; -/// Used for forward reference. -typedef struct _HT_INTERFACE HT_INTERFACE; - -/** - * Coherent Init Data. - * - * Metrics representing the coherent fabric which was discovered: Degree of nodes, adjacency, - * node numbering permutations, and the topology which it matched. - */ -typedef struct { - /** The number of coherent Links connected on each Node (the 'Degree' of the Node) */ - UINT8 SysDegree[MAX_NODES]; - /** The systems adjacency (sysMatrix[i][j] is true if Node_i has a Link to Node_j) */ - BOOLEAN SysMatrix[MAX_NODES][MAX_NODES]; - - UINT8 DbDegree[MAX_NODES]; /**< Like sysDegree, but for the current database topology */ - BOOLEAN DbMatrix[MAX_NODES][MAX_NODES]; /**< Like sysMatrix, but for the current database topology */ - - UINT8 Perm[MAX_NODES]; /**< The Node mapping from the system to the database */ - UINT8 ReversePerm[MAX_NODES]; /**< The Node mapping from the database to the system */ - UINT8 *MatchedTopology; /**< The topology that matched the current system or NULL */ -} COHERENT_FABRIC; - -/** - * Represent the system as Links of matched port pairs. - * A pair consists of a source Node, a Link to the destination Node, the - * destination Node, and its Link back to source Node. The even indices are - * the source Nodes and Links, and the odd indices are for the destination - * Nodes and Links. - * @note The Port pair 2*N and 2*N+1 are connected together to form a Link - * (e.g. 0,1 and 8,9 are ports on either end of an HT Link) The lower number - * port (2*N) is the source port. The device that owns the source port is - * always the device closer to the BSP. (i.e. nearer the CPU in a - * non-coherent chain, or the CPU with the lower NodeID). - */ -typedef struct { - /* This section is where the Link is in the system and how to find it */ - UINT8 Type; /**< 0 = CPU, 1 = Device, all others reserved */ - UINT8 Link; /**< 0-1 for devices, 0-7 for CPUs */ - UINT8 NodeID; /**< The Node, or a pointer to the devices parent Node */ - UINT8 HostLink; /**< For Devices, the root CPU's Link to the chain */ - UINT8 HostDepth; /**< Link Depth in chain, only used by devices */ - PCI_ADDR Pointer; /**< A pointer to the device's slave HT capability, so we don't have to keep searching */ - - /* This section is for the final settings, which are written to hardware */ - BOOLEAN SelRegang; /**< Indicates to software regang Link, only used for CPU->CPU Links */ - UINT8 SelWidthIn; /**< Width in setting */ - UINT8 SelWidthOut; /**< Width out setting */ - UINT8 SelFrequency; /**< Frequency setting */ - - /* This section is for keeping track of capabilities and possible configurations */ - BOOLEAN RegangCap; /**< Is the port capable of reganging? CPUs only */ - UINT32 PrvFrequencyCap; /**< Possible frequency settings */ - UINT8 PrvWidthInCap; /**< Possible Width setting */ - UINT8 PrvWidthOutCap; /**< Possible Width setting */ - UINT32 CompositeFrequencyCap; /**< Possible Link frequency setting */ - UINT32 ClumpingSupport; /**< Unit ID Clumping value (bit 0 = passive support) */ -} PORT_DESCRIPTOR; - -/// Reference to a set of PORT_DESCRIPTORs. -typedef PORT_DESCRIPTOR (*PORT_LIST)[MAX_PLATFORM_LINKS*2]; - -/** - * Our global state data structure - */ -typedef struct { - AMD_HT_INTERFACE *HtBlock; /**< The input data structure. */ - - UINT8 NodesDiscovered; /**< One less than the number of Nodes found in the system */ - UINT8 TotalLinks; /**< How many HT Links have we discovered so far. */ - UINT8 SysMpCap; /**< The maximum number of Nodes that all processors are capable of */ - AGESA_STATUS MaxEventClass; /**< The event class of the highest severity event generated */ - - PORT_LIST PortList; /**< Represent the system as a set of Links, each two Ports. */ - COHERENT_FABRIC *Fabric; /**< Describe metrics about the coherent fabric. - * Limited scope to CoherentInit(). */ - /* Data interface to other Agesa Modules */ - SOCKET_DIE_TO_NODE_MAP SocketDieToNodeMap; /**< For each Socket, Die the Node ids */ - NODE_TO_SOCKET_DIE_MAP NodeToSocketDieMap; /**< For each Node id, Socket and Die */ - HOP_COUNT_TABLE *HopCountTable; /**< Table of hops between nodes */ - - /* Data for non-coherent initialization */ - UINT8 AutoBusCurrent; /**< The next bus number available */ - UINT8 UsedCfgMapEntries; /**< The next Config address Map set available, Limit 4 (F1X[EC:E0]) */ - BOOLEAN IsUsingRecoveryHt; /**< Manual BUID Swap List processing should assume that HT Recovery was used */ - BOOLEAN IsSetHtCrcFlood; /**< Enable setting of HT CRC Flood */ - BOOLEAN IsUsingUnitIdClumping; /**< Enable automatic Unit Id Clumping configuration. */ - - HT_INTERFACE *HtInterface; /**< Interface for feature code to external parameters */ - HT_FEATURES *HtFeatures; /**< The current feature implementations */ - NORTHBRIDGE *Nb; /**< The current northbridge */ - - PLATFORM_CONFIGURATION *PlatformConfiguration; /**< The platform specific configuration customizations */ - VOID *ConfigHandle; /**< Config Pointer, opaque handle for passing to lib */ -} STATE_DATA; - -// -// Feature Method types -// - -/** - * Discover all coherent devices in the system. - * - * @HtFeatInstances. - * - * @param[in,out] State our global state - * - */ -typedef VOID F_COHERENT_DISCOVERY ( - IN OUT STATE_DATA *State - ); -/// Reference to a method. -typedef F_COHERENT_DISCOVERY *PF_COHERENT_DISCOVERY; - -/** - * Using the description of the fabric topology we discovered, try to find a match - * among the supported topologies. - * - * @HtFeatInstances. - * - * @param[in,out] State the discovered fabric, degree matrix, permutation - * - */ -typedef VOID F_LOOKUP_COMPUTE_AND_LOAD_ROUTING_TABLES ( - IN OUT STATE_DATA *State - ); -/// Reference to a method. -typedef F_LOOKUP_COMPUTE_AND_LOAD_ROUTING_TABLES *PF_LOOKUP_COMPUTE_AND_LOAD_ROUTING_TABLES; - -/** - * Make a Hop Count Table for the installed topology. - * - * @HtFeatInstances. - * - * @param[in,out] State access topology, permutation, update hop table - * - */ -typedef VOID F_MAKE_HOP_COUNT_TABLE ( - IN OUT STATE_DATA *State - ); -/// Reference to a method. -typedef F_MAKE_HOP_COUNT_TABLE *PF_MAKE_HOP_COUNT_TABLE; - -/** - * Process a non-coherent Link. - * - * @HtFeatInstances. - * - * @param[in] Node Node on which to process nc init - * @param[in] Link The non-coherent Link on that Node - * @param[in] IsCompatChain Is this the chain with the southbridge? TRUE if yes. - * @param[in,out] State our global state - */ -typedef VOID F_PROCESS_LINK ( - IN UINT8 Node, - IN UINT8 Link, - IN BOOLEAN IsCompatChain, - IN OUT STATE_DATA *State - ); -/// Reference to a method. -typedef F_PROCESS_LINK *PF_PROCESS_LINK; - -/** - * Get Link features into system data structure. - * - * @HtFeatInstances. - * - * @param[in] State our global state, port list - */ -typedef VOID F_GATHER_LINK_DATA ( - IN STATE_DATA *State - ); -/// Reference to a method. -typedef F_GATHER_LINK_DATA *PF_GATHER_LINK_DATA; - -/** - * Optimize Links. - * - * @HtFeatInstances. - * - * @param[in,out] State Process and update portlist - */ -typedef VOID F_SELECT_OPTIMAL_WIDTH_AND_FREQUENCY ( - IN OUT STATE_DATA *State - ); -/// Reference to a method. -typedef F_SELECT_OPTIMAL_WIDTH_AND_FREQUENCY *PF_SELECT_OPTIMAL_WIDTH_AND_FREQUENCY; - -/** - * Change the hardware state for all Links according to the now optimized data in the - * port list data structure. - * - * @HtFeatInstances. - * - * @param[in] State our global state, port list - */ -typedef VOID F_SET_LINK_DATA ( - IN STATE_DATA *State - ); -/// Reference to a method. -typedef F_SET_LINK_DATA *PF_SET_LINK_DATA; - -/** - * Retry must be enabled on all coherent links if it is enabled on any coherent links. - * - * @HtFeatInstances. - * - * @param[in,out] State global state, port frequency settings. - * - * @retval TRUE Fixup occurred, all coherent links HT1 - * @retval FALSE No changes - */ -typedef BOOLEAN F_IS_COHERENT_RETRY_FIXUP ( - IN STATE_DATA *State - ); -/// Reference to a method. -typedef F_IS_COHERENT_RETRY_FIXUP *PF_IS_COHERENT_RETRY_FIXUP; - - -/** - * Test the subLinks of a Link to see if they qualify to be reganged. - * - * @HtFeatInstances. - * - * @param[in,out] State Our global state - */ -typedef VOID F_REGANG_LINKS ( - IN OUT STATE_DATA *State - ); -/// Reference to a method. -typedef F_REGANG_LINKS *PF_REGANG_LINKS; - -/** - * Iterate through all Links, checking the frequency of each subLink pair. - * - * @HtFeatInstances. - * - * @param[in,out] State Link state and port list - * - */ -typedef VOID F_SUBLINK_RATIO_FIXUP ( - IN OUT STATE_DATA *State - ); -/// Reference to a method. -typedef F_SUBLINK_RATIO_FIXUP *PF_SUBLINK_RATIO_FIXUP; - -/** - * Identify Links which can have traffic distribution. - * - * @HtFeatInstances. - * - * @param[in] State port list data - */ -typedef VOID F_TRAFFIC_DISTRIBUTION ( - IN STATE_DATA *State - ); -/// Reference to a method. -typedef F_TRAFFIC_DISTRIBUTION *PF_TRAFFIC_DISTRIBUTION; - -/** - * Access HT Link Control Register. - * - * @HtFeatInstances. - * - * @param[in] Reg the PCI config address the control register - * @param[in] HiBit the high bit number - * @param[in] LoBit the low bit number - * @param[in] Value the value to write to that bit range. Bit 0 => loBit. - * @param[in] State Our state, config handle for lib - */ -typedef VOID F_SET_HT_CONTROL_REGISTER_BITS ( - IN PCI_ADDR Reg, - IN UINT8 HiBit, - IN UINT8 LoBit, - IN UINT32 *Value, - IN STATE_DATA *State - ); -/// Reference to a method. -typedef F_SET_HT_CONTROL_REGISTER_BITS *PF_SET_HT_CONTROL_REGISTER_BITS; - -/** - * Translate a desired width setting to the bits to set in the register field. - * - * @HtFeatInstances. - * - * @param[in] Value the width Value - * - * @return The bits for the register - */ -typedef UINT8 F_CONVERT_WIDTH_TO_BITS ( - IN UINT8 Value - ); -/// Reference to a method. -typedef F_CONVERT_WIDTH_TO_BITS *PF_CONVERT_WIDTH_TO_BITS; - -/** - * HT Feature Methods. - * - * Provides abstract methods which are bound to specific feature implementations. - */ -struct _HT_FEATURES { - PF_COHERENT_DISCOVERY CoherentDiscovery; /**< Method: Coherent Discovery. */ - PF_LOOKUP_COMPUTE_AND_LOAD_ROUTING_TABLES LookupComputeAndLoadRoutingTables; - /**< Method: Route the discovered system */ - PF_MAKE_HOP_COUNT_TABLE MakeHopCountTable; /**< Method: Compute slit hop counts */ - PF_PROCESS_LINK ProcessLink; /**< Method: Process a non-coherent Link. */ - PF_GATHER_LINK_DATA GatherLinkData; /**< Method: Gather Link Capabilities and data. */ - PF_SELECT_OPTIMAL_WIDTH_AND_FREQUENCY SelectOptimalWidthAndFrequency; - /**< Method: Optimize link features. */ - PF_REGANG_LINKS RegangLinks; /**< Method: Regang Sublinks. */ - PF_SUBLINK_RATIO_FIXUP SubLinkRatioFixup; /**< Method: Fix Sublink Frequency ratios */ - PF_IS_COHERENT_RETRY_FIXUP IsCoherentRetryFixup; - /**< Method: Fix Retry mixed on coherent links. */ - PF_SET_LINK_DATA SetLinkData; /**< Method: Set optimized values. */ - PF_TRAFFIC_DISTRIBUTION TrafficDistribution; /**< Method: Detect and Initialize Traffic Distribution */ - PF_SET_HT_CONTROL_REGISTER_BITS SetHtControlRegisterBits; /**< Method: Access HT Link Control Reg. */ - PF_CONVERT_WIDTH_TO_BITS ConvertWidthToBits; /**< Method: Convert a bit width to the value used for register setting. */ -} ; - -/*---------------------------------------------------------------------------- - * Prototypes - * - *---------------------------------------------------------------------------- - */ - -/** - * Provide the current Feature set implementation. - * - * Add an implementation reference for the constructor, just to make sure the page is created. - * @HtFeatMethod{_HT_FEATURES}. - * - */ -VOID -NewHtFeatures ( - OUT HT_FEATURES *HtFeatures, - IN AMD_CONFIG_PARAMS *StdHeader - ); - - -#endif /* _HT_FEAT_H_ */ diff --git a/src/vendorcode/amd/agesa/f12/Proc/HT/htGraph.h b/src/vendorcode/amd/agesa/f12/Proc/HT/htGraph.h deleted file mode 100644 index 9f8c104c7b..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/HT/htGraph.h +++ /dev/null @@ -1,143 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * Topology Interface. - * - * Contains interface to the topology data. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: HyperTransport - * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $ - * - */ -/* - ***************************************************************************** - * - * Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * *************************************************************************** - * - */ - -#ifndef _HT_GRAPH_H_ -#define _HT_GRAPH_H_ - -/** - * @page htgraphdesign Graph Support routines - * - * These routines provide support for dealing with the graph representation - * of the topologies, along with the routing table information for that topology. - * The routing information is compressed and these routines currently decompress - * 'on the fly'. A graph is represented as a set of routes. All the edges in the - * graph are routes; a direct route from Node i to Node j exists in the graph IFF - * there is an edge directly connecting Node i to Node j. All other routes designate - * the edge which the route to that Node initially takes, by designating a Node - * to which a direct connection exists. That is, the route to non-adjacent Node j - * from Node i specifies Node k where Node i directly connects to Node k. - * - *@code - * pseudo definition of compressed graph: - * typedef struct - * { - * // First byte - * UINT8 broadcast[8]:1; // that is, 8 1-bit values - * // Second byte - * UINT8 requestRoute:4; // [3:0] - * UINT8 responseRoute:4; // [7:4] - * } sRoute; - * typedef struct - * { - * UINT8 size; - * sRoute graph[size][size]; - * } sGraph; - *@endcode - */ - -/*---------------------------------------------------------------------------- - * Mixed (DEFINITIONS AND MACROS / TYPEDEFS, STRUCTURES, ENUMS) - * - *---------------------------------------------------------------------------- - */ - -/*----------------------------------------------------------------------------- - * DEFINITIONS AND MACROS - * - *----------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------- - * TYPEDEFS, STRUCTURES, ENUMS - * - *---------------------------------------------------------------------------- - */ - - -/*---------------------------------------------------------------------------- - * FUNCTIONS PROTOTYPE - * - *---------------------------------------------------------------------------- - */ -VOID -GetAmdTopolist ( - OUT UINT8 ***List - ); - -UINT8 -GraphHowManyNodes ( - IN UINT8 *Graph - ); - -BOOLEAN -GraphIsAdjacent ( - IN UINT8 *Graph, - IN UINT8 NodeA, - IN UINT8 NodeB - ); - -UINT8 -GraphGetRsp ( - IN UINT8 *Graph, - IN UINT8 NodeA, - IN UINT8 NodeB - ); - -UINT8 -GraphGetReq ( - IN UINT8 *Graph, - IN UINT8 NodeA, - IN UINT8 NodeB - ); - -UINT8 -GraphGetBc ( - IN UINT8 *Graph, - IN UINT8 NodeA, - IN UINT8 NodeB - ); - -#endif /* _HT_GRAPH_H_ */ - diff --git a/src/vendorcode/amd/agesa/f12/Proc/HT/htInterface.c b/src/vendorcode/amd/agesa/f12/Proc/HT/htInterface.c deleted file mode 100644 index b0617b1d62..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/HT/htInterface.c +++ /dev/null @@ -1,241 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * External Interface implementation. - * - * Contains routines for implementing the interface to the client BIOS. - * This file includes the interface access constructor. - * This file implements build options using conditional compilation. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: HyperTransport - * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $ - * - */ -/* - ***************************************************************************** - * - * Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * *************************************************************************** - * - */ - -/* - *---------------------------------------------------------------------------- - * MODULES USED - * - *---------------------------------------------------------------------------- - */ - - - -#include "AGESA.h" -#include "AdvancedApi.h" -#include "amdlib.h" -#include "OptionsHt.h" -#include "Ids.h" -#include "Topology.h" -#include "htFeat.h" -#include "htInterface.h" -#include "CommonReturns.h" -#include "htInterfaceGeneral.h" -#include "htInterfaceCoherent.h" -#include "htInterfaceNonCoherent.h" -#include "Filecode.h" -CODE_GROUP (G1_PEICC) -RDATA_GROUP (G1_PEICC) - -#define FILECODE PROC_HT_HTINTERFACE_FILECODE -/*---------------------------------------------------------------------------- - * DEFINITIONS AND MACROS - * - *---------------------------------------------------------------------------- - */ - -extern CONST OPTION_HT_CONFIGURATION OptionHtConfiguration; - -/*---------------------------------------------------------------------------- - * TYPEDEFS AND STRUCTURES - * - *---------------------------------------------------------------------------- - */ - -/** - * The default initializer for the HT internal interface, full features. - */ -CONST HT_INTERFACE ROMDATA HtInterfaceDefault = -{ - GetCpu2CpuPcbLimits, - GetSkipRegang, - NewHopCountTable, - GetOverrideBusNumbers, - GetManualBuidSwapList, - GetDeviceCapOverride, - GetIoPcbLimits, - GetSocketFromMap, - GetIgnoreLink, - PostMapToAp, - NewNodeAndSocketTables, - CleanMapsAfterError, - SetNodeToSocketMap, - GetMinNbCoreFreq -}; - -/** - * The non-coherent only build option initializer for the HT internal interface. - */ -CONST HT_INTERFACE ROMDATA HtInterfaceNonCoherentOnly = -{ - (PF_GET_CPU_2_CPU_PCB_LIMITS)CommonVoid, - (PF_GET_SKIP_REGANG)CommonReturnFalse, - (PF_NEW_HOP_COUNT_TABLE)CommonVoid, - GetOverrideBusNumbers, - GetManualBuidSwapList, - GetDeviceCapOverride, - GetIoPcbLimits, - GetSocketFromMap, - GetIgnoreLink, - PostMapToAp, - NewNodeAndSocketTables, - (PF_CLEAN_MAPS_AFTER_ERROR)CommonVoid, - SetNodeToSocketMap, - GetMinNbCoreFreq -}; - -/** - * Topology Maps only feature build option initializer for the HT internal interface. - */ -CONST HT_INTERFACE ROMDATA HtInterfaceMapsOnly = -{ - (PF_GET_CPU_2_CPU_PCB_LIMITS)CommonVoid, - (PF_GET_SKIP_REGANG)CommonReturnFalse, - (PF_NEW_HOP_COUNT_TABLE)CommonVoid, - (PF_GET_OVERRIDE_BUS_NUMBERS)CommonReturnFalse, - (PF_GET_MANUAL_BUID_SWAP_LIST)CommonReturnFalse, - (PF_GET_DEVICE_CAP_OVERRIDE)CommonVoid, - (PF_GET_IO_PCB_LIMITS)CommonVoid, - (PF_GET_SOCKET_FROM_MAP)CommonReturnZero8, - (PF_GET_IGNORE_LINK)CommonReturnFalse, - PostMapToAp, - NewNodeAndSocketTables, - (PF_CLEAN_MAPS_AFTER_ERROR)CommonVoid, - SetNodeToSocketMap, - (PF_GET_MIN_NB_CORE_FREQ)CommonReturnZero8 -}; - -/** - * No features build option initializer for the HT internal interface. - */ -CONST HT_INTERFACE ROMDATA HtInterfaceNone = -{ - (PF_GET_CPU_2_CPU_PCB_LIMITS)CommonVoid, - (PF_GET_SKIP_REGANG)CommonReturnFalse, - (PF_NEW_HOP_COUNT_TABLE)CommonVoid, - (PF_GET_OVERRIDE_BUS_NUMBERS)CommonReturnFalse, - (PF_GET_MANUAL_BUID_SWAP_LIST)CommonReturnFalse, - (PF_GET_DEVICE_CAP_OVERRIDE)CommonVoid, - (PF_GET_IO_PCB_LIMITS)CommonVoid, - (PF_GET_SOCKET_FROM_MAP)CommonReturnZero8, - (PF_GET_IGNORE_LINK)CommonReturnFalse, - (PF_POST_MAP_TO_AP)CommonVoid, - (PF_NEW_NODE_AND_SOCKET_TABLES)CommonVoid, - (PF_CLEAN_MAPS_AFTER_ERROR)CommonVoid, - (PF_SET_NODE_TO_SOCKET_MAP)CommonVoid, - (PF_GET_MIN_NB_CORE_FREQ)CommonReturnZero8 -}; - -/*---------------------------------------------------------------------------- - * PROTOTYPES OF LOCAL FUNCTIONS - * - *---------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------- - * EXPORTED FUNCTIONS - * - *---------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------- - * LOCAL FUNCTIONS - * - *---------------------------------------------------------------------------- - */ - -/*----------------------------------------------------------------------------------------*/ -/** - * A constructor for the internal Ht Interface. - * - * The install has a reference to the initializer appropriate to the user selected build - * options. Use the selected initializer to construct the internal interface. - * - * @param[in,out] HtInterface Contains pointer to HT Interface structure to initialize. - * @param[in] StdHeader Opaque handle to standard config header - * -*/ -VOID -NewHtInterface ( - OUT HT_INTERFACE *HtInterface, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - LibAmdMemCopy ( - (VOID *) HtInterface, - (VOID *) OptionHtConfiguration.HtOptionInternalInterface, - (sizeof (HT_INTERFACE)), - StdHeader - ); -} - -/*----------------------------------------------------------------------------------------*/ -/** - * A "constructor" for the HyperTransport external interface. - * - * Sets inputs to valid, basic level, defaults. - * - * Copy the initial default values from the build options tables to the interface struct. - * - * @param[in] StdHeader Opaque handle to standard config header - * @param[in] AmdHtInterface HT Interface structure to initialize. - * - * @retval AGESA_SUCCESS Constructors are not allowed to fail -*/ -AGESA_STATUS -AmdHtInterfaceConstructor ( - IN AMD_CONFIG_PARAMS *StdHeader, - IN AMD_HT_INTERFACE *AmdHtInterface - ) -{ - LibAmdMemCopy ( - (VOID *) AmdHtInterface, - (VOID *) OptionHtConfiguration.HtOptionPlatformDefaults, - (UINT32) (sizeof (AMD_HT_INTERFACE)), - StdHeader - ); - return AGESA_SUCCESS; -} diff --git a/src/vendorcode/amd/agesa/f12/Proc/HT/htInterface.h b/src/vendorcode/amd/agesa/f12/Proc/HT/htInterface.h deleted file mode 100644 index 0b9dedc8ae..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/HT/htInterface.h +++ /dev/null @@ -1,489 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * Internal access to HT Interface. - * - * This file provides definitions used by HT internal modules. The - * external HT interface (in agesa.h) is accessed using these methods. - * This keeps the HT Feature implementations abstracted from the HT - * interface. - * - * This file includes the interface access constructor and interface - * support which is not removed with various build options. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: HyperTransport - * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $ - * - */ -/* -***************************************************************************** -* -* Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* *************************************************************************** -* -*/ - -#ifndef _HT_INTERFACE_H_ -#define _HT_INTERFACE_H_ - -/** - * @page htimplintf HT Internal Interface Implementation Guide - * - * HT Internal Interface provides access to the HT Component external interface (see AGESA.h), - * in a manner that isolates calling code from knowledge about the external interface or which - * interfaces are supported in the current build. - * - * @par Adding a Method to HT Internal Interface - * - * To add a new method to the HT Internal Interface, follow these steps. - *
    - *
  • Create a typedef for the Method with the correct parameters and return type. - * - *
      - *
    • Name the method typedef (F_METHOD_NAME)(), where METHOD_NAME is the same name as the method table item, - * but with "_"'s and UPPERCASE, rather than mixed case. - * @n typedef VOID (F_METHOD_NAME)(); @n - * - *
    • Make a reference type for references to a method implementation: - * @n /// Reference to a Method - * @n typedef F_METHOD_NAME *PF_METHOD_NAME @n - *
    - * - *
  • Provide a standard doxygen function preamble for the Method typedef. Begin the - * detailed description by providing a reference to the method instances page by including - * the lines below: - * @code - * * - * * @HtInterfaceInstances - * * - * @endcode - * @note It is important to provide documentation for the method type, because the method may not - * have an implementation in any families supported by the current package. @n - * - *
  • Add to the HT_INTERFACE struct an item for the Method: - * @n PF_METHOD_NAME MethodName; ///< Method: description. @n - *
- * - * @par Implementing an HT Internal Interface Instance of the method. - * - * To implement an instance of a method for a specific interface follow these steps. - * - * - In appropriate files, implement the method with the return type and parameters - * matching the method typedef. - * - * - Name the function MethodName(). - * - * - Create a doxygen function preamble for the method instance. Begin the detailed description with - * an Implements command to reference the method type and add this instance to the Method Instances page. - * @code - * * - * * @HtInterfaceMethod{::F_METHOD_NAME}. - * * - * @endcode - * - * - To access other Ht internal interface routines or data as part of the method implementation, the function - * must use HtInterface->OtherMethod(). Do not directly access other HT internal interface - * routines, because in the table there may be overrides or this routine may be shared by multiple families. - * - * - Add the instance to the HT_INTERFACE instances. - * - * - If a configuration does not need an instance of the method use one of the CommonReturns from - * CommonReturns.h with the same return type. - * - * @par Invoking HT Internal Interface Methods. - * - * The first step is carried out only once by the top level HT entry point. - * @n @code - * HT_INTERFACE HtInterface; - * // Get the current HT internal interface (to HtBlock data) - * NewHtInterface (&HtInterface); - * State->HtInterface = &HtInterface; - * @endcode - * - * The following example shows how to invoke a HT Internal Interface method. - * @n @code - * State->HtInterface->MethodName (); - * @endcode - * - */ - -/*---------------------------------------------------------------------------- - * Mixed (DEFINITIONS AND MACROS / TYPEDEFS, STRUCTURES, ENUMS) - * - *---------------------------------------------------------------------------- - */ - -/*----------------------------------------------------------------------------- - * DEFINITIONS AND MACROS - * - *----------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------- - * TYPEDEFS, STRUCTURES, ENUMS - * - *---------------------------------------------------------------------------- - */ - -/** - * Get limits for CPU to CPU Links. - * - * @HtInterfaceInstances. - * - * @param[in] NodeA One Node on which this Link is located - * @param[in] LinkA The Link on this Node - * @param[in] NodeB The other Node on which this Link is located - * @param[in] LinkB The Link on that Node - * @param[in,out] ABLinkWidthLimit modify to change the Link Width In - * @param[in,out] BALinkWidthLimit modify to change the Link Width Out - * @param[in,out] PcbFreqCap modify to change the Link's frequency capability - * @param[in] State the input data - * - */ -typedef VOID F_GET_CPU_2_CPU_PCB_LIMITS ( - IN UINT8 NodeA, - IN UINT8 LinkA, - IN UINT8 NodeB, - IN UINT8 LinkB, - IN OUT UINT8 *ABLinkWidthLimit, - IN OUT UINT8 *BALinkWidthLimit, - IN OUT UINT32 *PcbFreqCap, - IN STATE_DATA *State - ); -/// Reference to a method. -typedef F_GET_CPU_2_CPU_PCB_LIMITS *PF_GET_CPU_2_CPU_PCB_LIMITS; - -/** - * Skip reganging of subLinks. - * - * @HtInterfaceInstances. - * - * @param[in] NodeA One Node on which this Link is located - * @param[in] LinkA The Link on this Node - * @param[in] NodeB The other Node on which this Link is located - * @param[in] LinkB The Link on that Node - * @param[in] State the input data - * - * @retval MATCHED leave Link unganged - * @retval POWERED_OFF leave link unganged and power off the paired sublink - * @retval UNMATCHED regang Link automatically - */ -typedef FINAL_LINK_STATE F_GET_SKIP_REGANG ( - IN UINT8 NodeA, - IN UINT8 LinkA, - IN UINT8 NodeB, - IN UINT8 LinkB, - IN STATE_DATA *State - ); -/// Reference to a method. -typedef F_GET_SKIP_REGANG *PF_GET_SKIP_REGANG; - -/** - * Manually control bus number assignment. - * - * @HtInterfaceInstances. - * - * @param[in] Node The Node on which this chain is located - * @param[in] Link The Link on the host for this chain - * @param[out] SecBus Secondary Bus number for this non-coherent chain - * @param[out] SubBus Subordinate Bus number - * @param[in] State the input data - * - * @retval TRUE this routine is supplying the bus numbers - * @retval FALSE use auto Bus numbering - */ -typedef BOOLEAN F_GET_OVERRIDE_BUS_NUMBERS ( - IN UINT8 Node, - IN UINT8 Link, - OUT UINT8 *SecBus, - OUT UINT8 *SubBus, - IN STATE_DATA *State - ); -/// Reference to a method. -typedef F_GET_OVERRIDE_BUS_NUMBERS *PF_GET_OVERRIDE_BUS_NUMBERS; - -/** - * Get Manual BUID assignment list. - * - * @HtInterfaceInstances. - * - * @param[in] Node The Node on which this chain is located - * @param[in] Link The Link on the host for this chain - * @param[out] List a pointer to a list, if returns TRUE - * @param[in] State the input data - * - * @retval TRUE use manual List - * @retval FALSE initialize the Link automatically. List not valid. - */ -typedef BOOLEAN F_GET_MANUAL_BUID_SWAP_LIST ( - IN UINT8 Node, - IN UINT8 Link, - OUT BUID_SWAP_LIST **List, - IN STATE_DATA *State - ); -/// Reference to a method. -typedef F_GET_MANUAL_BUID_SWAP_LIST *PF_GET_MANUAL_BUID_SWAP_LIST; - -/** - * Override capabilities of a device. - * - * @HtInterfaceInstances. - * - * @param[in] HostNode The Node on which this chain is located - * @param[in] HostLink The Link on the host for this chain - * @param[in] Depth The Depth in the I/O chain from the Host - * @param[in] PciAddress The Device's PCI config address (for callout) - * @param[in] DevVenId The Device's PCI Vendor + Device ID (offset 0x00) - * @param[in] Revision The Device's PCI Revision - * @param[in] Link The Device's Link number (0 or 1) - * @param[in,out] LinkWidthIn modify to change the Link Width In - * @param[in,out] LinkWidthOut modify to change the Link Width Out - * @param[in,out] FreqCap modify to change the Link's frequency capability - * @param[in,out] Clumping modify to change unit id clumping capability - * @param[in] State the input data - * - */ -typedef VOID F_GET_DEVICE_CAP_OVERRIDE ( - IN UINT8 HostNode, - IN UINT8 HostLink, - IN UINT8 Depth, - IN PCI_ADDR PciAddress, - IN UINT32 DevVenId, - IN UINT8 Revision, - IN UINT8 Link, - IN OUT UINT8 *LinkWidthIn, - IN OUT UINT8 *LinkWidthOut, - IN OUT UINT32 *FreqCap, - IN OUT UINT32 *Clumping, - IN STATE_DATA *State - ); -/// Reference to a method. -typedef F_GET_DEVICE_CAP_OVERRIDE *PF_GET_DEVICE_CAP_OVERRIDE; - -/** - * Get limits for non-coherent Links. - * - * @HtInterfaceInstances. - * - * @param[in] HostNode The Node on which this Link is located - * @param[in] HostLink The Link about to be initialized - * @param[in] Depth The Depth in the I/O chain from the Host - * @param[in,out] DownstreamLinkWidthLimit modify to change the Link Width In - * @param[in,out] UpstreamLinkWidthLimit modify to change the Link Width Out - * @param[in,out] PcbFreqCap modify to change the Link's frequency capability - * @param[in] State the input data - */ -typedef VOID F_GET_IO_PCB_LIMITS ( - IN UINT8 HostNode, - IN UINT8 HostLink, - IN UINT8 Depth, - IN OUT UINT8 *DownstreamLinkWidthLimit, - IN OUT UINT8 *UpstreamLinkWidthLimit, - IN OUT UINT32 *PcbFreqCap, - IN STATE_DATA *State - ); -/// Reference to a method. -typedef F_GET_IO_PCB_LIMITS *PF_GET_IO_PCB_LIMITS; - -/** - * Get the Socket number for a given Node number. - * - * @HtInterfaceInstances. - * - * @param[in] Node Node discovered event data. - * @param[in] State reference to Node to socket map - * - * @return the socket id - * - */ -typedef UINT8 F_GET_SOCKET_FROM_MAP ( - IN UINT8 Node, - IN STATE_DATA *State - ); -/// Reference to a method. -typedef F_GET_SOCKET_FROM_MAP *PF_GET_SOCKET_FROM_MAP; - -/** - * Ignore a Link. - * - * @HtInterfaceInstances. - * - * @param[in] Node The Node on which this Link is located - * @param[in] Link The Link about to be initialized - * @param[in] NbList The northbridge default ignore link list - * @param[in] State the input data - * - * @retval MATCHED ignore this Link and skip it - * @retval POWERED_OFF ignore this link and power it off. - * @retval UNMATCHED initialize the Link normally - */ -typedef FINAL_LINK_STATE F_GET_IGNORE_LINK ( - IN UINT8 Node, - IN UINT8 Link, - IN IGNORE_LINK *NbIgnoreLinkList, - IN STATE_DATA *State - ); -/// Reference to a method. -typedef F_GET_IGNORE_LINK *PF_GET_IGNORE_LINK; - -/** - * Post Node id and other context info to AP cores via mailbox. - * - * @HtInterfaceInstances. - * - * @param[in] State Our state - */ -typedef VOID F_POST_MAP_TO_AP ( - IN STATE_DATA *State - ); -/// Reference to a method. -typedef F_POST_MAP_TO_AP *PF_POST_MAP_TO_AP; - -/** - * Clean up the map structures after severe event has caused a fall back to 1 node. - * - * @HtInterfaceInstances. - * - * @param[in] State Our state - */ -typedef VOID F_CLEAN_MAPS_AFTER_ERROR ( - IN STATE_DATA *State - ); -/// Reference to a method. -typedef F_CLEAN_MAPS_AFTER_ERROR *PF_CLEAN_MAPS_AFTER_ERROR; - -/** - * Get a new Socket Die to Node Map. - * - * @HtInterfaceInstances. - * - * @param[in,out] State global state - */ -typedef VOID F_NEW_NODE_AND_SOCKET_TABLES ( - IN OUT STATE_DATA *State - ); -/// Reference to a method. -typedef F_NEW_NODE_AND_SOCKET_TABLES *PF_NEW_NODE_AND_SOCKET_TABLES; - -/** - * Fill in the socket's Node id when a processor is discovered in that socket. - * - * @HtInterfaceInstances. - * - * @param[in] Node Node from which a new node was discovered - * @param[in] CurrentNodeModule The current node's module id in it's processor. - * @param[in] PackageLink The package level link from Node to NewNode. - * @param[in] NewNode The new node's id - * @param[in] HardwareSocket If we use the hardware method (preferred), this is the socket of new node. - * @param[in] Module The new node's module id in it's processor. - * @param[in] State our State - */ -typedef VOID F_SET_NODE_TO_SOCKET_MAP ( - IN UINT8 Node, - IN UINT8 CurrentNodeModule, - IN UINT8 PackageLink, - IN UINT8 NewNode, - IN UINT8 HardwareSocket, - IN UINT8 Module, - IN STATE_DATA *State - ); -/// Reference to a method. -typedef F_SET_NODE_TO_SOCKET_MAP *PF_SET_NODE_TO_SOCKET_MAP; - -/** - * Get a new, empty Hop Count Table, to make one for the installed topology. - * - * @HtInterfaceInstances. - * - * @param[in,out] State Keep our buffer handle. - * - */ -typedef VOID F_NEW_HOP_COUNT_TABLE ( - IN OUT STATE_DATA *State - ); -/// Reference to a method. -typedef F_NEW_HOP_COUNT_TABLE *PF_NEW_HOP_COUNT_TABLE; - -/** - * Get the minimum Northbridge frequency for the system. - * - * @HtInterfaceInstances. - * - * Invoke the CPU component power mgt interface. - * - * @param[in] PlatformConfig Platform profile/build option config structure. - * @param[in] StdHeader Config for library and services. - * - * @return Frequency in MHz. - * - */ -typedef UINT32 F_GET_MIN_NB_CORE_FREQ ( - IN PLATFORM_CONFIGURATION *PlatformConfig, - IN AMD_CONFIG_PARAMS *StdHeader - ); -/// Reference to a Method. -typedef F_GET_MIN_NB_CORE_FREQ *PF_GET_MIN_NB_CORE_FREQ; - -/** - * The HT Interface, feature code uses these methods to get interface parameters. - */ -struct _HT_INTERFACE { // See Forward Declaration in HtFeates.h - PF_GET_CPU_2_CPU_PCB_LIMITS GetCpu2CpuPcbLimits; /**< Method: Get link limits for coherent links. */ - PF_GET_SKIP_REGANG GetSkipRegang; /**< Method: Skip reganging for coherent links. */ - PF_NEW_HOP_COUNT_TABLE NewHopCountTable; /**< Method: Get a new hop count table. */ - PF_GET_OVERRIDE_BUS_NUMBERS GetOverrideBusNumbers; /**< Method: Control Bus number assignment. */ - PF_GET_MANUAL_BUID_SWAP_LIST GetManualBuidSwapList; /**< Method: Assign device IDs. */ - PF_GET_DEVICE_CAP_OVERRIDE GetDeviceCapOverride; /**< Method: Override Device capabilities. */ - PF_GET_IO_PCB_LIMITS GetIoPcbLimits; /**< Method: Get link limits for noncoherent links. */ - PF_GET_SOCKET_FROM_MAP GetSocketFromMap; /**< Method: Get the Socket for a node id. */ - PF_GET_IGNORE_LINK GetIgnoreLink; /**< Method: Ignore a link. */ - PF_POST_MAP_TO_AP PostMapToAp; /**< Method: Post Socket and other info to AP cores. */ - PF_NEW_NODE_AND_SOCKET_TABLES NewNodeAndSocketTables; /**< Method: Get new socket and node maps. */ - PF_CLEAN_MAPS_AFTER_ERROR CleanMapsAfterError; /**< Method: Clean up maps for forced 1P on error fall back. */ - PF_SET_NODE_TO_SOCKET_MAP SetNodeToSocketMap; /**< Method: Associate a node id with a socket. */ - PF_GET_MIN_NB_CORE_FREQ GetMinNbCoreFreq; /**< Method: Get the minimum northbridge frequency */ -} ; - -/*---------------------------------------------------------------------------- - * Prototypes to Interface from Feature Code - * - *---------------------------------------------------------------------------- - */ - -/** - * A constructor for the internal Ht Interface. - * -*/ -VOID -NewHtInterface ( - OUT HT_INTERFACE *HtInterface, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -#endif /* _HT_INTERFACE_H_ */ diff --git a/src/vendorcode/amd/agesa/f12/Proc/HT/htInterfaceCoherent.c b/src/vendorcode/amd/agesa/f12/Proc/HT/htInterfaceCoherent.c deleted file mode 100644 index d6d7f2060c..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/HT/htInterfaceCoherent.c +++ /dev/null @@ -1,263 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * External Interface implementation for coherent features. - * - * Contains routines for accessing the interface to the client BIOS, - * for support only required for coherent features. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: HyperTransport - * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $ - * - */ -/* - ***************************************************************************** - * - * Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * *************************************************************************** - * - */ - -/* - *---------------------------------------------------------------------------- - * MODULES USED - * - *---------------------------------------------------------------------------- - */ - - - -#include "AGESA.h" -#include "amdlib.h" -#include "Ids.h" -#include "Topology.h" -#include "htFeat.h" -#include "htInterface.h" -#include "htInterfaceGeneral.h" -#include "htInterfaceCoherent.h" -#include "htNb.h" -#include "heapManager.h" -#include "Filecode.h" -CODE_GROUP (G1_PEICC) -RDATA_GROUP (G1_PEICC) - -#define FILECODE PROC_HT_HTINTERFACECOHERENT_FILECODE -/*---------------------------------------------------------------------------- - * DEFINITIONS AND MACROS - * - *---------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------- - * TYPEDEFS AND STRUCTURES - * - *---------------------------------------------------------------------------- - */ -/*---------------------------------------------------------------------------- - * PROTOTYPES OF LOCAL FUNCTIONS - * - *---------------------------------------------------------------------------- - */ -/*---------------------------------------------------------------------------- - * EXPORTED FUNCTIONS - * - *---------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------- - * LOCAL FUNCTIONS - * - *---------------------------------------------------------------------------- - */ - -/*----------------------------------------------------------------------------------------*/ -/*----------------------------------------------------------------------------------------*/ -/** - * Get limits for CPU to CPU Links. - * - * @HtInterfaceMethod{::F_GET_CPU_2_CPU_PCB_LIMITS} - * - * For each coherent connection this routine is called once. Update the frequency - * and width if needed for this Link (usually based on board restriction). This is - * used with CPU device capabilities and northbridge limits to compute the default - * settings. The input width and frequency are valid, but do not necessarily reflect - * the minimum setting that will be chosen. - * - * @param[in] NodeA One Node on which this Link is located - * @param[in] LinkA The Link on this Node - * @param[in] NodeB The other Node on which this Link is located - * @param[in] LinkB The Link on that Node - * @param[in,out] ABLinkWidthLimit modify to change the Link Width In - * @param[in,out] BALinkWidthLimit modify to change the Link Width Out - * @param[in,out] PcbFreqCap modify to change the Link's frequency capability - * @param[in] State the input data - * - */ -VOID -GetCpu2CpuPcbLimits ( - IN UINT8 NodeA, - IN UINT8 LinkA, - IN UINT8 NodeB, - IN UINT8 LinkB, - IN OUT UINT8 *ABLinkWidthLimit, - IN OUT UINT8 *BALinkWidthLimit, - IN OUT UINT32 *PcbFreqCap, - IN STATE_DATA *State - ) -{ - CPU_TO_CPU_PCB_LIMITS *p; - UINT8 SocketA; - UINT8 SocketB; - UINT8 PackageLinkA; - UINT8 PackageLinkB; - - ASSERT ((NodeA < MAX_NODES) && (NodeB < MAX_NODES)); - ASSERT ((LinkA < State->Nb->MaxLinks) && (LinkB < State->Nb->MaxLinks)); - - SocketA = State->HtInterface->GetSocketFromMap (NodeA, State); - PackageLinkA = State->Nb->GetPackageLink (NodeA, LinkA, State->Nb); - SocketB = State->HtInterface->GetSocketFromMap (NodeB, State); - PackageLinkB = State->Nb->GetPackageLink (NodeB, LinkB, State->Nb); - - if (State->HtBlock->CpuToCpuPcbLimitsList != NULL) { - p = State->HtBlock->CpuToCpuPcbLimitsList; - - while (p->SocketA != HT_LIST_TERMINAL) { - if (((p->SocketA == SocketA) || (p->SocketA == HT_LIST_MATCH_ANY)) && - ((p->LinkA == PackageLinkA) || ((p->LinkA == HT_LIST_MATCH_ANY) && (!IsPackageLinkInternal (PackageLinkA))) || - ((p->LinkA == HT_LIST_MATCH_INTERNAL_LINK) && (IsPackageLinkInternal (PackageLinkA)))) && - ((p->SocketB == SocketB) || (p->SocketB == HT_LIST_MATCH_ANY)) && - ((p->LinkB == PackageLinkB) || ((p->LinkB == HT_LIST_MATCH_ANY) && (!IsPackageLinkInternal (PackageLinkB))) || - ((p->LinkB == HT_LIST_MATCH_INTERNAL_LINK) && (IsPackageLinkInternal (PackageLinkB))))) { - // Found a match, update width and frequency - *ABLinkWidthLimit = p->ABLinkWidthLimit; - *BALinkWidthLimit = p->BALinkWidthLimit; - *PcbFreqCap = p->PcbFreqCap; - break; - } else { - p++; - } - } - } -} - -/*----------------------------------------------------------------------------------------*/ -/** - * Skip reganging of subLinks. - * - * @HtInterfaceMethod{::F_GET_SKIP_REGANG} - * - * This routine is called whenever two subLinks are both connected to the same CPUs. - * Normally, unganged sublinks between the same two CPUs are reganged. Return true - * from this routine to leave the Links unganged. - * - * @param[in] NodeA One Node on which this Link is located - * @param[in] LinkA The Link on this Node - * @param[in] NodeB The other Node on which this Link is located - * @param[in] LinkB The Link on that Node - * @param[in] State the input data - * - * @retval MATCHED leave Link unganged - * @retval POWERED_OFF leave link unganged and power off the paired sublink - * @retval UNMATCHED regang Link automatically - */ -FINAL_LINK_STATE -GetSkipRegang ( - IN UINT8 NodeA, - IN UINT8 LinkA, - IN UINT8 NodeB, - IN UINT8 LinkB, - IN STATE_DATA *State - ) -{ - SKIP_REGANG *p; - FINAL_LINK_STATE Result; - UINT8 SocketA; - UINT8 SocketB; - UINT8 PackageLinkA; - UINT8 PackageLinkB; - - ASSERT ((NodeA < MAX_NODES) && (NodeB < MAX_NODES)); - ASSERT ((LinkA < State->Nb->MaxLinks) && (LinkB < State->Nb->MaxLinks)); - - Result = UNMATCHED; - SocketA = State->HtInterface->GetSocketFromMap (NodeA, State); - PackageLinkA = State->Nb->GetPackageLink (NodeA, LinkA, State->Nb); - SocketB = State->HtInterface->GetSocketFromMap (NodeB, State); - PackageLinkB = State->Nb->GetPackageLink (NodeB, LinkB, State->Nb); - - if (State->HtBlock->SkipRegangList != NULL) { - p = State->HtBlock->SkipRegangList; - - while (p->SocketA != HT_LIST_TERMINAL) { - if (((p->SocketA == SocketA) || (p->SocketA == HT_LIST_MATCH_ANY)) && - ((p->LinkA == PackageLinkA) || ((p->LinkA == HT_LIST_MATCH_ANY) && (!IsPackageLinkInternal (PackageLinkA))) || - ((p->LinkA == HT_LIST_MATCH_INTERNAL_LINK) && (IsPackageLinkInternal (PackageLinkA)))) && - ((p->SocketB == SocketB) || (p->SocketB == HT_LIST_MATCH_ANY)) && - ((p->LinkB == PackageLinkB) || ((p->LinkB == HT_LIST_MATCH_ANY) && (!IsPackageLinkInternal (PackageLinkB))) || - ((p->LinkB == HT_LIST_MATCH_INTERNAL_LINK) && (IsPackageLinkInternal (PackageLinkB))))) { - // Found a match return final link state - Result = p->LinkState; - break; - } else { - p++; - } - } - } - return Result; -} - -/*----------------------------------------------------------------------------------------*/ -/** - * Get a new, empty Hop Count Table, to make one for the installed topology. - * - * @HtInterfaceMethod{::F_NEW_HOP_COUNT_TABLE} - * - * For SLIT, publish a matrix with the hop count, by allocating a buffer on heap with a - * known signature. - * - * @param[in,out] State Keep our buffer handle. - * - */ -VOID -NewHopCountTable ( - IN OUT STATE_DATA *State - ) -{ - ALLOCATE_HEAP_PARAMS AllocHeapParams; - - AllocHeapParams.RequestedBufferSize = sizeof (HOP_COUNT_TABLE); - AllocHeapParams.BufferHandle = HOP_COUNT_TABLE_HANDLE; - AllocHeapParams.Persist = HEAP_SYSTEM_MEM; - if (HeapAllocateBuffer ( &AllocHeapParams, State->ConfigHandle) == AGESA_SUCCESS) { - State->HopCountTable = (HOP_COUNT_TABLE *)AllocHeapParams.BufferPtr; - } else { - State->HopCountTable = NULL; - } -} diff --git a/src/vendorcode/amd/agesa/f12/Proc/HT/htInterfaceCoherent.h b/src/vendorcode/amd/agesa/f12/Proc/HT/htInterfaceCoherent.h deleted file mode 100644 index 417d35c09d..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/HT/htInterfaceCoherent.h +++ /dev/null @@ -1,114 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * Internal access to HT Interface for coherent features. - * - * This file provides definitions used by HT internal modules. The - * external HT interface (in agesa.h) is accessed using these methods. - * This keeps the HT Feature implementations abstracted from the HT - * interface. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: HyperTransport - * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $ - * - */ -/* -***************************************************************************** -* -* Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* *************************************************************************** -* -*/ - -#ifndef _HT_INTERFACE_COHERENT_H_ -#define _HT_INTERFACE_COHERENT_H_ - -/*---------------------------------------------------------------------------- - * Mixed (DEFINITIONS AND MACROS / TYPEDEFS, STRUCTURES, ENUMS) - * - *---------------------------------------------------------------------------- - */ - -/*----------------------------------------------------------------------------- - * DEFINITIONS AND MACROS - * - *----------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------- - * TYPEDEFS, STRUCTURES, ENUMS - * - *---------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------- - * Prototypes to Interface from Feature Code - * - *---------------------------------------------------------------------------- - */ - -/** - * Get limits for CPU to CPU Links. - * - */ -VOID -GetCpu2CpuPcbLimits ( - IN UINT8 NodeA, - IN UINT8 LinkA, - IN UINT8 NodeB, - IN UINT8 LinkB, - IN OUT UINT8 *ABLinkWidthLimit, - IN OUT UINT8 *BALinkWidthLimit, - IN OUT UINT32 *PcbFreqCap, - IN STATE_DATA *State - ); - -/** - * Skip reganging of subLinks. - * - */ -FINAL_LINK_STATE -GetSkipRegang ( - IN UINT8 NodeA, - IN UINT8 LinkA, - IN UINT8 NodeB, - IN UINT8 LinkB, - IN STATE_DATA *State - ); - -/** - * Get a new, empty Hop Count Table, to make one for the installed topology. - * - */ -VOID -NewHopCountTable ( - IN OUT STATE_DATA *State - ); - -#endif /* _HT_INTERFACE_COHERENT_H_ */ diff --git a/src/vendorcode/amd/agesa/f12/Proc/HT/htInterfaceGeneral.c b/src/vendorcode/amd/agesa/f12/Proc/HT/htInterfaceGeneral.c deleted file mode 100644 index 9bbb32ce2e..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/HT/htInterfaceGeneral.c +++ /dev/null @@ -1,539 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * External Interface implementation, general purpose features. - * - * Contains routines for implementing the interface to the client BIOS. This file - * includes the interface support which is not removed with various build options. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: HyperTransport - * @e \$Revision: 48937 $ @e \$Date: 2011-03-15 03:37:15 +0800 (Tue, 15 Mar 2011) $ - * - */ -/* - ***************************************************************************** - * - * Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * *************************************************************************** - * - */ - -/* - *---------------------------------------------------------------------------- - * MODULES USED - * - *---------------------------------------------------------------------------- - */ - - - -#include "AGESA.h" -#include "amdlib.h" -#include "OptionMultiSocket.h" -#include "Ids.h" -#include "Topology.h" -#include "htFeat.h" -#include "htInterface.h" -#include "htInterfaceGeneral.h" -#include "htNb.h" -#include "cpuRegisters.h" -#include "cpuServices.h" -#include "cpuFeatures.h" -#include "heapManager.h" -#include "Filecode.h" -CODE_GROUP (G1_PEICC) -RDATA_GROUP (G1_PEICC) - -#define FILECODE PROC_HT_HTINTERFACEGENERAL_FILECODE -/*---------------------------------------------------------------------------- - * DEFINITIONS AND MACROS - * - *---------------------------------------------------------------------------- - */ -extern OPTION_MULTISOCKET_CONFIGURATION OptionMultiSocketConfiguration; - -/*---------------------------------------------------------------------------- - * TYPEDEFS AND STRUCTURES - * - *---------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------- - * PROTOTYPES OF LOCAL FUNCTIONS - * - *---------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------- - * EXPORTED FUNCTIONS - * - *---------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------- - * LOCAL FUNCTIONS - * - *---------------------------------------------------------------------------- - */ - -/*----------------------------------------------------------------------------------------*/ -/** - * Is PackageLink an Internal Link? - * - * This is a test for the logical link match codes in the user interface, not a test for - * the actual northbridge links. - * - * @param[in] PackageLink The link - * - * @retval TRUE This is an internal link - * @retval FALSE This is not an internal link - */ -BOOLEAN -IsPackageLinkInternal ( - IN UINT8 PackageLink - ) -{ - return (BOOLEAN) ((PackageLink <= HT_LIST_MATCH_INTERNAL_LINK_2) && (PackageLink >= HT_LIST_MATCH_INTERNAL_LINK_0)); -} - -/*----------------------------------------------------------------------------------------*/ -/** - * Ignore a Link. - * - * @HtInterfaceMethod{::F_GET_IGNORE_LINK} - * - * This routine is called every time a coherent Link is found and then every time a - * non-coherent Link from a CPU is found. Any coherent or non-coherent Link from a - * CPU can be ignored and not used for discovery or initialization. Useful for - * connection based systems. - * - * @note not called for IO device to IO Device Links. - * - * @param[in] Node The Node on which this Link is located - * @param[in] Link The Link about to be initialized - * @param[in] NbIgnoreLinkList The northbridge default ignore link list - * @param[in] State the input data - * - * @retval MATCHED ignore this Link and skip it - * @retval POWERED_OFF ignore this link and power it off. - * @retval UNMATCHED initialize the Link normally - */ -FINAL_LINK_STATE -GetIgnoreLink ( - IN UINT8 Node, - IN UINT8 Link, - IN IGNORE_LINK *NbIgnoreLinkList, - IN STATE_DATA *State - ) -{ - IGNORE_LINK *p; - FINAL_LINK_STATE Result; - BOOLEAN IsFound; - UINT8 Socket; - UINT8 PackageLink; - - ASSERT ((Node < MAX_NODES) && (Link < MAX_NODES)); - - Result = UNMATCHED; - IsFound = FALSE; - Socket = State->HtInterface->GetSocketFromMap (Node, State); - PackageLink = State->Nb->GetPackageLink (Node, Link, State->Nb); - - if (State->HtBlock->IgnoreLinkList != NULL) { - p = State->HtBlock->IgnoreLinkList; - while (p->Socket != HT_LIST_TERMINAL) { - if (((p->Socket == Socket) || (p->Socket == HT_LIST_MATCH_ANY)) && - ((p->Link == PackageLink) || - ((p->Link == HT_LIST_MATCH_ANY) && (!IsPackageLinkInternal (PackageLink))) || - ((p->Link == HT_LIST_MATCH_INTERNAL_LINK) && (IsPackageLinkInternal (PackageLink))))) { - // Found a match return the desired link state. - ASSERT (Result < MaxFinalLinkState); - Result = p->LinkState; - IsFound = TRUE; - break; - } else { - p++; - } - } - } - // If there wasn't a match in the user interface, see if the northbridge provides one. - if (!IsFound && (NbIgnoreLinkList != NULL)) { - p = NbIgnoreLinkList; - while (p->Socket != HT_LIST_TERMINAL) { - if (((p->Socket == Socket) || (p->Socket == HT_LIST_MATCH_ANY)) && - ((p->Link == PackageLink) || - ((p->Link == HT_LIST_MATCH_ANY) && (!IsPackageLinkInternal (PackageLink))) || - ((p->Link == HT_LIST_MATCH_INTERNAL_LINK) && (IsPackageLinkInternal (PackageLink))))) { - // Found a match return the desired link state. - ASSERT (Result < MaxFinalLinkState); - Result = p->LinkState; - break; - } else { - p++; - } - } - } - return Result; -} - -/*----------------------------------------------------------------------------------------*/ -/** - * Get the Socket number for a given Node number. - * - * @HtInterfaceMethod{::F_GET_SOCKET_FROM_MAP} - * - * Return the id. - * - * @param[in] Node The Node to translate - * @param[in] State reference to Node to socket map - * - * @return the socket id - * - */ -UINT8 -GetSocketFromMap ( - IN UINT8 Node, - IN STATE_DATA *State - ) -{ - UINT8 Socket; - - ASSERT (State->NodeToSocketDieMap != NULL); - - Socket = (*State->NodeToSocketDieMap)[Node].Socket; - return Socket; -} - -/*----------------------------------------------------------------------------------------*/ -/** - * Get a new Socket Die to Node Map. - * - * @HtInterfaceMethod{::F_NEW_NODE_AND_SOCKET_TABLES} - * - * Put the Socket Die Table in heap with a known handle. Content will be generated as - * each node is discovered. - * - * @param[in,out] State global state - */ -VOID -NewNodeAndSocketTables ( - IN OUT STATE_DATA *State - ) -{ - UINT8 i; - UINT8 j; - ALLOCATE_HEAP_PARAMS AllocHeapParams; - - // Allocate heap for the table - State->SocketDieToNodeMap = NULL; - AllocHeapParams.RequestedBufferSize = (((MAX_SOCKETS) * (MAX_DIES)) * sizeof (SOCKET_DIE_TO_NODE_ITEM)); - AllocHeapParams.BufferHandle = SOCKET_DIE_MAP_HANDLE; - AllocHeapParams.Persist = HEAP_SYSTEM_MEM; - if (HeapAllocateBuffer (&AllocHeapParams, State->ConfigHandle) == AGESA_SUCCESS) { - State->SocketDieToNodeMap = (SOCKET_DIE_TO_NODE_MAP)AllocHeapParams.BufferPtr; - // Initialize shared data structures - for (i = 0; i < MAX_SOCKETS; i++) { - for (j = 0; j < MAX_DIES; j++) { - (*State->SocketDieToNodeMap)[i][j].Node = HT_LIST_TERMINAL; - (*State->SocketDieToNodeMap)[i][j].LowCore = HT_LIST_TERMINAL; - (*State->SocketDieToNodeMap)[i][j].HighCore = HT_LIST_TERMINAL; - } - } - } - // Allocate heap for the table - State->NodeToSocketDieMap = NULL; - AllocHeapParams.RequestedBufferSize = (MAX_NODES * sizeof (NODE_TO_SOCKET_DIE_ITEM)); - AllocHeapParams.BufferHandle = NODE_ID_MAP_HANDLE; - AllocHeapParams.Persist = HEAP_SYSTEM_MEM; - if (HeapAllocateBuffer (&AllocHeapParams, State->ConfigHandle) == AGESA_SUCCESS) { - State->NodeToSocketDieMap = (NODE_TO_SOCKET_DIE_MAP)AllocHeapParams.BufferPtr; - // Initialize shared data structures - for (i = 0; i < MAX_NODES; i++) { - (*State->NodeToSocketDieMap)[i].Socket = HT_LIST_TERMINAL; - (*State->NodeToSocketDieMap)[i].Die = HT_LIST_TERMINAL; - } - } -} - -/*----------------------------------------------------------------------------------------*/ -/** - * Get the minimum Northbridge frequency for the system. - * - * @HtInterfaceMethod{::F_GET_MIN_NB_CORE_FREQ} - * - * Invoke the CPU component power mgt interface. - * - * @param[in] PlatformConfig Platform profile/build option config structure. - * @param[in] StdHeader Config for library and services. - * - * @return Frequency in MHz. - * - */ -UINT32 -GetMinNbCoreFreq ( - IN PLATFORM_CONFIGURATION *PlatformConfig, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - UINT32 MinSysNbFreq; - UINT32 MinP0NbFreq; - - OptionMultiSocketConfiguration.GetMinNbCof (PlatformConfig, &MinSysNbFreq, &MinP0NbFreq, StdHeader); - - ASSERT (MinSysNbFreq != 0); - - return MinSysNbFreq; -} - -/** - * @page physicalsockethowto Physical Socket Map, How To Create - * - * To create a physical system socket map for a platform: - * - * - Start at the Node which will be the BSP. - * - * - Begin a breadth first enumeration of all the coherent Links between sockets - * by creating a socket structure for each socket connection from the BSP. - * For example, if the BSP is in socket zero and Link one connects to socket two, - * create socket {0, 1, 2}. - * - * - When all Links from the BSP are described, go to the first socket connected - * to the BSP and continue the breadth first enumeration. - * - * - It should not be necessary to describe the back Links; in the example above, there - * should be no need to create {2, 1, 0} (assuming socket two connects back to - * socket zero on its Link one). - * - * - When completed: - * - * - Every socket except the BSP's (usually zero) must be listed as a targetSocket, - * at least once. Some sockets may be listed more than once. - * - * - There usually should be at least as many entries as Links. An exception is a - * fully connected system, only the Links from the BSP are needed. - * - * - Every socket but the last one in the breadth first order should usually have one - * or more entries listing it as a currentSocket. (The last one has only back Links.) - * - * There are no strict assumptions about the ordering of the socket structures. - */ - -/*----------------------------------------------------------------------------------------*/ -/** - * Update maps between Sockets and Nodes for a specific newly discovered node. - * - * @HtInterfaceMethod{::F_SET_NODE_TO_SOCKET_MAP} - * - * There are two methods for providing socket naming of nodes. - * - * Hardware Method (preferred): A value strapped in hardware by the board is read and - * passed to this routine. - * - * Software Method: The current node's socket is looked up, since it was - * previously a new node and went through this process. The link is converted to - * a package level link. A user data structure describing the package level - * layout of the system is searched for the current node's socket and package link, - * and now we know the new node's socket. - * - * In either case, the Socket, Module to Node map and the Node to Socket, Module - * map are updated with the new node, socket, and module. - * - * Data needed to do this is passed in to the routine as arguments rather than read by this routine, - * so that it is not necessary to know a valid temporary route to either node at the time this code runs. - * - * @param[in] Node Node from which a new node was discovered - * @param[in] CurrentNodeModule The current node's module id in it's processor. - * @param[in] PackageLink The package link for the current node's link. - * @param[in] NewNode The new node's id - * @param[in] HardwareSocket If we use the hardware method (preferred), this is the socket of new node. - * @param[in] Module The new node's module id in it's processor. - * @param[in] State our State - */ -VOID -SetNodeToSocketMap ( - IN UINT8 Node, - IN UINT8 CurrentNodeModule, - IN UINT8 PackageLink, - IN UINT8 NewNode, - IN UINT8 HardwareSocket, - IN UINT8 Module, - IN STATE_DATA *State - ) -{ - UINT8 SourceSocket; - UINT8 TargetSocket; - SYSTEM_PHYSICAL_SOCKET_MAP *Map; - - // While this code could be written to recover from a NULL socket map, AGESA cannot function without one. - ASSERT (State->SocketDieToNodeMap != NULL); - - if (State->HtBlock->SystemPhysicalSocketMap != NULL) { - if (NewNode != 0) { - // Find the logical Node from which a new Node was discovered in the Node field of - // some socket. It must already be there, Nodes are assigned ascending. - // - for (SourceSocket = 0; SourceSocket < MAX_SOCKETS; SourceSocket++) { - if ((*State->SocketDieToNodeMap)[SourceSocket][CurrentNodeModule].Node == Node) { - break; - } - } - // This ASSERT should be understood as "the Node did not have a match", not as a limit check on SourceSocket. - ASSERT (SourceSocket != MAX_SOCKETS); - - // Find the sourceSocket in the CurrentSocket field, for the Link on which a new Node - // was discovered. When we find an entry with that socket and Link number, update the - // Node for that socket. - // - if (IsPackageLinkInternal (PackageLink)) { - // Internal Nodes are in the same socket, don't search the physical system map. - TargetSocket = SourceSocket; - } else { - // Find the target socket in the physical system map. - Map = State->HtBlock->SystemPhysicalSocketMap; - while ((Map->CurrentSocket != 0xFF) && - ((Map->CurrentSocket != SourceSocket) || (Map->CurrentLink != PackageLink))) { - Map++; - } - ASSERT (Map->CurrentSocket != 0xFF); - TargetSocket = Map->TargetSocket; - } - } else { - // The BSP (BSN, if you will) has no predecessor node from which it is discovered. - TargetSocket = 0; - } - } else { - // Use the hardware method - // The hardware strapped socket id is passed to us in this case. - TargetSocket = HardwareSocket; - } - // If the target socket, module is already mapped to something, that's not good. Socket labeling conflict. - // Check that the board is strapped correctly. If not you need a SystemPhysicalSocketMap. If you have one, - // check it for correctness. - ASSERT ((*State->SocketDieToNodeMap)[TargetSocket][Module].Node == 0xFF); - // Update the map for the rest of agesa - (*State->SocketDieToNodeMap)[TargetSocket][Module].Node = NewNode; - // and the node to socket map - ASSERT (State->NodeToSocketDieMap != NULL); - (*State->NodeToSocketDieMap)[NewNode].Socket = TargetSocket; - (*State->NodeToSocketDieMap)[NewNode].Die = Module; -} - -/*----------------------------------------------------------------------------------------*/ -/** - * Clean up the map structures after severe event has caused a fall back to 1 node. - * - * @HtInterfaceMethod{::F_CLEAN_MAPS_AFTER_ERROR} - * - * @param[in] State Our state, access to socket, node maps - * - */ -VOID -CleanMapsAfterError ( - IN STATE_DATA *State - ) -{ - UINTN Socket; - UINTN Module; - UINTN Node; - - ASSERT (State->NodeToSocketDieMap != NULL); - ASSERT (State->SocketDieToNodeMap != NULL); - - // Clear all the socket, module items except for the socket and module containing node zero. - for (Socket = 0; Socket < MAX_SOCKETS; Socket++) { - for (Module = 0; Module < MAX_DIES; Module++) { - if (((*State->NodeToSocketDieMap)[0].Socket != Socket) || ((*State->NodeToSocketDieMap)[0].Die != Module)) { - (*State->SocketDieToNodeMap)[Socket][Module].Node = HT_LIST_TERMINAL; - (*State->SocketDieToNodeMap)[Socket][Module].LowCore = HT_LIST_TERMINAL; - (*State->SocketDieToNodeMap)[Socket][Module].HighCore = HT_LIST_TERMINAL; - } - } - } - // Clear all the node items except for node zero. - for (Node = 1; Node < MAX_NODES; Node++) { - (*State->NodeToSocketDieMap)[Node].Socket = HT_LIST_TERMINAL; - (*State->NodeToSocketDieMap)[Node].Die = HT_LIST_TERMINAL; - } -} - -/*----------------------------------------------------------------------------------------*/ -/** - * Post Node id and other context info to AP cores via mailbox. - * - * @HtInterfaceMethod{::F_POST_MAP_TO_AP} - * - * Since Ap's can not view map until after mp communication is established, - * provide them with initial context info via a mailbox register. A mailbox - * register is one that can be written in PCI space and read in MSR space. - * - * @param[in] State Our state, access to socket, node maps - */ -VOID -PostMapToAp ( - IN STATE_DATA *State - ) -{ - UINT8 ModuleType; - UINT8 Module; - AP_MAILBOXES ApMailboxes; - UINT8 Node; - UINT32 Degree; - AGESA_STATUS CalledStatus; - - // Dispatch any features (such as Preserve Mailbox) that need to run as soon as discovery is completed. - IDS_HDT_CONSOLE (CPU_TRACE, " Dispatch CPU features after HT discovery\n"); - CalledStatus = DispatchCpuFeatures (CPU_FEAT_AFTER_COHERENT_DISCOVERY, State->PlatformConfiguration, State->ConfigHandle); - - ASSERT (State->Fabric != NULL); - Degree = 0; - // Compute the degree of the system by finding the maximum degree of any node. - for (Node = 0; Node < (State->NodesDiscovered + 1); Node++) { - if (State->Fabric->SysDegree[Node] > Degree) { - Degree = State->Fabric->SysDegree[Node]; - } - } - // Post the information on all nodes. - for (Node = 0; Node < (State->NodesDiscovered + 1); Node++) { - ModuleType = 0; - Module = 0; - State->Nb->GetModuleInfo (Node, &ModuleType, &Module, State->Nb); - ApMailboxes.ApMailInfo.Info = 0; - ApMailboxes.ApMailInfo.Fields.Node = Node; - ApMailboxes.ApMailInfo.Fields.Socket = State->HtInterface->GetSocketFromMap (Node, State); - ApMailboxes.ApMailInfo.Fields.ModuleType = ModuleType; - ApMailboxes.ApMailInfo.Fields.Module = Module; - ApMailboxes.ApMailExtInfo.Info = 0; - ApMailboxes.ApMailExtInfo.Fields.SystemDegree = Degree; - // other fields of the extended info are used during ap init, and will be initialized at that time. - State->Nb->PostMailbox (Node, ApMailboxes, State->Nb); - } - // Now that the mailboxes have been initialized, cache the info on the BSC. The APs - // will cache during heap initialization. - CacheApMailbox (State->ConfigHandle); -} diff --git a/src/vendorcode/amd/agesa/f12/Proc/HT/htInterfaceGeneral.h b/src/vendorcode/amd/agesa/f12/Proc/HT/htInterfaceGeneral.h deleted file mode 100644 index 79cd0c930b..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/HT/htInterfaceGeneral.h +++ /dev/null @@ -1,161 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * Internal access to HT Interface, general purpose features. - * - * This file provides definitions used by HT internal modules. The - * external HT interface (in agesa.h) is accessed using these methods. - * This keeps the HT Feature implementations abstracted from the HT - * external interface. - * - * This file includes the interface support which is not removed with - * various build options. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: HyperTransport - * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $ - * - */ -/* -***************************************************************************** -* -* Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* *************************************************************************** -* -*/ - -#ifndef _HT_INTERFACE_GENERAL_H_ -#define _HT_INTERFACE_GENERAL_H_ - -/*---------------------------------------------------------------------------- - * Mixed (DEFINITIONS AND MACROS / TYPEDEFS, STRUCTURES, ENUMS) - * - *---------------------------------------------------------------------------- - */ - -/*----------------------------------------------------------------------------- - * DEFINITIONS AND MACROS - * - *----------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------- - * TYPEDEFS, STRUCTURES, ENUMS - * - *---------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------- - * Prototypes to Interface from Feature Code - * - *---------------------------------------------------------------------------- - */ - -/** - * Is PackageLink an Internal Link? - */ -BOOLEAN -IsPackageLinkInternal ( - IN UINT8 PackageLink - ); - -/** - * Get the Socket number for a given Node number. - * - */ -UINT8 -GetSocketFromMap ( - IN UINT8 Node, - IN STATE_DATA *State - ); - -/** - * Ignore a Link. - * - */ -FINAL_LINK_STATE -GetIgnoreLink ( - IN UINT8 Node, - IN UINT8 Link, - IN IGNORE_LINK *NbIgnoreLinkList, - IN STATE_DATA *State - ); - -/** - * Get a new Socket Die to Node Map. - * - */ -VOID -NewNodeAndSocketTables ( - IN OUT STATE_DATA *State - ); - -/** - * Get the minimum Northbridge frequency for the system. - * - */ -UINT32 -GetMinNbCoreFreq ( - IN PLATFORM_CONFIGURATION *PlatformConfig, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -/** - * Fill in the socket's Node id when a processor is discovered in that socket. - * - */ -VOID -SetNodeToSocketMap ( - IN UINT8 Node, - IN UINT8 CurrentNodeModule, - IN UINT8 PackageLink, - IN UINT8 NewNode, - IN UINT8 HardwareSocket, - IN UINT8 Module, - IN STATE_DATA *State - ); - -/** - * Clean up the map structures after severe event has caused a fall back to 1 node. - * - */ -VOID -CleanMapsAfterError ( - IN STATE_DATA *State - ); - -/** - * Post Node id and other context info to AP cores via mailbox. - * - */ -VOID -PostMapToAp ( - IN STATE_DATA *State - ); - -#endif /* _HT_INTERFACE_GENERAL_H_ */ diff --git a/src/vendorcode/amd/agesa/f12/Proc/HT/htInterfaceNonCoherent.c b/src/vendorcode/amd/agesa/f12/Proc/HT/htInterfaceNonCoherent.c deleted file mode 100644 index cd19d3d05a..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/HT/htInterfaceNonCoherent.c +++ /dev/null @@ -1,393 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * External Interface implementation for non-coherent features. - * - * Contains routines for accessing the interface to the client BIOS, - * for non-coherent features. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: HyperTransport - * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $ - * - */ -/* - ***************************************************************************** - * - * Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * *************************************************************************** - * - */ - -/* - *---------------------------------------------------------------------------- - * MODULES USED - * - *---------------------------------------------------------------------------- - */ - - - -#include "AGESA.h" -#include "amdlib.h" -#include "Ids.h" -#include "Topology.h" -#include "htFeat.h" -#include "htInterface.h" -#include "htInterfaceNonCoherent.h" -#include "htNb.h" -#include "Filecode.h" -CODE_GROUP (G1_PEICC) -RDATA_GROUP (G1_PEICC) - -#define FILECODE PROC_HT_HTINTERFACENONCOHERENT_FILECODE -/*---------------------------------------------------------------------------- - * DEFINITIONS AND MACROS - * - *---------------------------------------------------------------------------- - */ -#define UNUSED_ZERO_32 ((UINT32)0) - -/*---------------------------------------------------------------------------- - * TYPEDEFS AND STRUCTURES - * - *---------------------------------------------------------------------------- - */ -/*---------------------------------------------------------------------------- - * EXPORTED FUNCTIONS - * - *---------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------- - * LOCAL FUNCTIONS - * - *---------------------------------------------------------------------------- - */ - -/*----------------------------------------------------------------------------------------*/ -/** - * Get Manual BUID assignment list. - * - * @HtInterfaceMethod{::F_GET_MANUAL_BUID_SWAP_LIST} - * - * This routine is called every time a non-coherent chain is processed. BUID - * assignment may be controlled explicitly on a non-coherent chain. Swaps controls - * the BUID assignment and FinalIds provides the device to device Linking. Device - * orientation can be detected automatically, or explicitly. See documentation for - * more details. - * - * If a manual swap list is not supplied, automatic non-coherent init assigns BUIDs - * starting at 1 and incrementing sequentially based on each device's unit count. - * - * @param[in] Node The Node on which this chain is located - * @param[in] Link The Link on the host for this chain - * @param[out] List supply a pointer to a list. - * List is NOT valid unless routine returns TRUE. - * @param[in] State the input data - * - * @retval TRUE use a manual list - * @retval FALSE initialize the Link automatically - */ -BOOLEAN -GetManualBuidSwapList ( - IN UINT8 Node, - IN UINT8 Link, - OUT BUID_SWAP_LIST **List, - IN STATE_DATA *State - ) -{ - MANUAL_BUID_SWAP_LIST *p; - BOOLEAN result; - UINT8 Socket; - UINT8 PackageLink; - - ASSERT ((Node < MAX_NODES) && (List != NULL)); - - result = FALSE; - Socket = State->HtInterface->GetSocketFromMap (Node, State); - PackageLink = State->Nb->GetPackageLink (Node, Link, State->Nb); - - if (State->HtBlock->ManualBuidSwapList != NULL) { - p = State->HtBlock->ManualBuidSwapList; - - while (p->Socket != HT_LIST_TERMINAL) { - if (((p->Socket == Socket) || (p->Socket == HT_LIST_MATCH_ANY)) && - ((p->Link == PackageLink) || (p->Link == HT_LIST_MATCH_ANY))) { - // Found a match implies TRUE, ignore the Link - result = TRUE; - *List = &(p->SwapList); - break; - } else { - p++; - } - } - } - // List is not valid if Result is FALSE. - return result; -} - -/*----------------------------------------------------------------------------------------*/ -/** - * Override capabilities of a device. - * - * @HtInterfaceMethod{::F_GET_DEVICE_CAP_OVERRIDE} - * - * This routine is called once for every Link on every IO device. Update the width - * and frequency capability if needed for this device. This is used along with - * device capabilities, the limit call backs, and northbridge limits to compute the - * default settings. The components of the device's PCI config address are provided, - * so its settings can be consulted if need be. The input width and frequency are the - * reported device capabilities. - * - * @param[in] HostNode The Node on which this chain is located - * @param[in] HostLink The Link on the host for this chain - * @param[in] Depth The Depth in the I/O chain from the Host - * @param[in] PciAddress The Device's PCI config address (for callout) - * @param[in] DevVenId The Device's PCI Vendor + Device ID (offset 0x00) - * @param[in] Revision The Device's PCI Revision - * @param[in] Link The Device's Link number (0 or 1) - * @param[in,out] LinkWidthIn modify to change the Link Width In - * @param[in,out] LinkWidthOut modify to change the Link Width Out - * @param[in,out] FreqCap modify to change the Link's frequency capability - * @param[in,out] Clumping modify to change unit id clumping capability - * @param[in] State the input data and config header - * - */ -VOID -GetDeviceCapOverride ( - IN UINT8 HostNode, - IN UINT8 HostLink, - IN UINT8 Depth, - IN PCI_ADDR PciAddress, - IN UINT32 DevVenId, - IN UINT8 Revision, - IN UINT8 Link, - IN OUT UINT8 *LinkWidthIn, - IN OUT UINT8 *LinkWidthOut, - IN OUT UINT32 *FreqCap, - IN OUT UINT32 *Clumping, - IN STATE_DATA *State - ) -{ - DEVICE_CAP_OVERRIDE *p; - UINT8 HostSocket; - UINT8 PackageLink; - DEVICE_CAP_CALLOUT_PARAMS CalloutParams; - AGESA_STATUS CalloutStatus; - - ASSERT ((HostNode < MAX_NODES) && (Depth < 32) && ((Link == 0) || (Link == 1))); - - HostSocket = State->HtInterface->GetSocketFromMap (HostNode, State); - PackageLink = State->Nb->GetPackageLink (HostNode, HostLink, State->Nb); - - if (State->HtBlock->DeviceCapOverrideList != NULL) { - p = State->HtBlock->DeviceCapOverrideList; - - while (p->HostSocket != HT_LIST_TERMINAL) { - if (((p->HostSocket == HostSocket) || (p->HostSocket == HT_LIST_MATCH_ANY)) && - ((p->HostLink == PackageLink) || (p->HostLink == HT_LIST_MATCH_ANY)) && - ((p->Depth == Depth) || (p->Depth == HT_LIST_MATCH_ANY)) && - ((p->Link == Link) || (p->Link == HT_LIST_MATCH_ANY)) && - // Found a potential match. Check the additional optional matches. - ((p->Options.IsCheckDevVenId == 0) || (p->DevVenId == DevVenId)) && - ((p->Options.IsCheckRevision == 0) || (p->Revision == Revision))) { - // - // Found a match. Check what override actions are desired. - // Unlike the PCB limit routines, which handle the info returned, - // deviceCapOverride is actually overriding the settings, so we need - // to check that the field actually has an update. - // The Callout is a catch all for situations the data is not up to handling. - // It is expected, but not enforced, that either the data overrides are used, - // or the callout is used, rather than both. - // - if (p->Options.IsOverrideWidthIn != 0) { - *LinkWidthIn = p->LinkWidthIn; - } - if (p->Options.IsOverrideWidthOut != 0) { - *LinkWidthOut = p->LinkWidthOut; - } - if (p->Options.IsOverrideFreq != 0) { - *FreqCap = p->FreqCap; - } - if (p->Options.IsOverrideClumping != 0) { - *Clumping = p->Clumping; - } - if (p->Options.IsDoCallout != 0) { - // - // Pass the actual info being matched, not the matched struct data. - // This callout is expected to be built in as part of the options file, and does not use the - // callout interface, even though we use the consistent interface declaration for the routine. - // So, the first two int parameters have no meaning in this case. - // It is not meaningful for the callout to have any status but Success. - // - CalloutParams.HostSocket = HostSocket; - CalloutParams.HostLink = PackageLink; - CalloutParams.Depth = Depth; - CalloutParams.DevVenId = DevVenId; - CalloutParams.Revision = Revision; - CalloutParams.Link = Link; - CalloutParams.PciAddress = PciAddress; - CalloutParams.LinkWidthIn = LinkWidthIn; - CalloutParams.LinkWidthOut = LinkWidthOut; - CalloutParams.FreqCap = FreqCap; - CalloutParams.Clumping = Clumping; - CalloutParams.StdHeader = *((AMD_CONFIG_PARAMS *) (State->ConfigHandle)); - CalloutStatus = p->Callout (UNUSED_ZERO_32, UNUSED_ZERO_32, (VOID *) &CalloutParams); - ASSERT (CalloutStatus == AGESA_SUCCESS); - } - break; - } else { - p++; - } - } - } -} - -/*----------------------------------------------------------------------------------------*/ -/** - * Get limits for non-coherent Links. - * - * @HtInterfaceMethod{::F_GET_IO_PCB_LIMITS} - * - * For each non-coherent connection this routine is called once. Update the - * frequency and width if needed for this Link (usually based on board restriction). - * This is used with device capabilities, device overrides, and northbridge limits to - * compute the default settings. The input width and frequency are valid, but do not - * necessarily reflect the minimum setting that will be chosen. - * - * @param[in] HostNode The Node on which this Link is located - * @param[in] HostLink The Link about to be initialized - * @param[in] Depth The Depth in the I/O chain from the Host - * @param[in,out] DownstreamLinkWidthLimit modify to change the Link Width In - * @param[in,out] UpstreamLinkWidthLimit modify to change the Link Width Out - * @param[in,out] PcbFreqCap modify to change the Link's frequency capability - * @param[in] State the input data - */ -VOID -GetIoPcbLimits ( - IN UINT8 HostNode, - IN UINT8 HostLink, - IN UINT8 Depth, - IN OUT UINT8 *DownstreamLinkWidthLimit, - IN OUT UINT8 *UpstreamLinkWidthLimit, - IN OUT UINT32 *PcbFreqCap, - IN STATE_DATA *State - ) -{ - IO_PCB_LIMITS *p; - UINT8 Socket; - UINT8 PackageLink; - - ASSERT ((HostNode < MAX_NODES) && (HostLink < MAX_NODES)); - - Socket = State->HtInterface->GetSocketFromMap (HostNode, State); - PackageLink = State->Nb->GetPackageLink (HostNode, HostLink, State->Nb); - - if (State->HtBlock->IoPcbLimitsList != NULL) { - p = State->HtBlock->IoPcbLimitsList; - - while (p->HostSocket != HT_LIST_TERMINAL) { - if (((p->HostSocket == Socket) || (p->HostSocket == HT_LIST_MATCH_ANY)) && - ((p->HostLink == PackageLink) || (p->HostLink == HT_LIST_MATCH_ANY)) && - ((p->Depth == Depth) || (p->Depth == HT_LIST_MATCH_ANY))) { - // Found a match, return the override info - *DownstreamLinkWidthLimit = p->DownstreamLinkWidthLimit; - *UpstreamLinkWidthLimit = p->UpstreamLinkWidthLimit; - *PcbFreqCap = p->PcbFreqCap; - break; - } else { - p++; - } - } - } -} - -/*----------------------------------------------------------------------------------------*/ -/** - * Manually control bus number assignment. - * - * @HtInterfaceMethod{::F_GET_OVERRIDE_BUS_NUMBERS} - * - * This routine is called every time a non-coherent chain is processed. If a system - * can not use the auto Bus numbering feature for non-coherent chain bus assignments, - * this routine can provide explicit control. For each chain, provide the bus number - * range to use. - * - * The outputs SecBus and SubBus are not valid unless this routine returns TRUE - * - * @param[in] Node The Node on which this chain is located - * @param[in] Link The Link on the host for this chain - * @param[out] SecBus Secondary Bus number for this non-coherent chain - * @param[out] SubBus Subordinate Bus number - * @param[in] State the input data - * - * @retval TRUE this routine is supplying the bus numbers. - * @retval FALSE use auto Bus numbering, bus outputs not valid. - */ -BOOLEAN -GetOverrideBusNumbers ( - IN UINT8 Node, - IN UINT8 Link, - OUT UINT8 *SecBus, - OUT UINT8 *SubBus, - IN STATE_DATA *State - ) -{ - OVERRIDE_BUS_NUMBERS *p; - BOOLEAN result; - UINT8 Socket; - UINT8 PackageLink; - - ASSERT ((Node < MAX_NODES) && (Link < MAX_NODES)); - - result = FALSE; - Socket = State->HtInterface->GetSocketFromMap (Node, State); - PackageLink = State->Nb->GetPackageLink (Node, Link, State->Nb); - - if (State->HtBlock->OverrideBusNumbersList != NULL) { - p = State->HtBlock->OverrideBusNumbersList; - - while (p->Socket != HT_LIST_TERMINAL) { - if (((p->Socket == Socket) || (p->Socket == HT_LIST_MATCH_ANY)) && - ((p->Link == PackageLink) || (p->Link == HT_LIST_MATCH_ANY))) { - // Found a match, return the bus overrides - *SecBus = p->SecBus; - *SubBus = p->SubBus; - ASSERT (*SubBus > *SecBus); - result = TRUE; - break; - } else { - p++; - } - } - } - // SecBus, SubBus are not valid if Result is FALSE. - return result; -} - diff --git a/src/vendorcode/amd/agesa/f12/Proc/HT/htInterfaceNonCoherent.h b/src/vendorcode/amd/agesa/f12/Proc/HT/htInterfaceNonCoherent.h deleted file mode 100644 index 4403784c48..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/HT/htInterfaceNonCoherent.h +++ /dev/null @@ -1,137 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * Internal access to HT Interface, for non-coherent features. - * - * This file provides definitions used by HT internal modules. The - * external HT interface (in agesa.h) is accessed using these methods. - * This keeps the HT Feature implementations abstracted from the HT - * interface. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: HyperTransport - * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $ - * - */ -/* -***************************************************************************** -* -* Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* *************************************************************************** -* -*/ - -#ifndef _HT_INTERFACE_NONCOHERENT_H_ -#define _HT_INTERFACE_NONCOHERENT_H_ - -/*---------------------------------------------------------------------------- - * Mixed (DEFINITIONS AND MACROS / TYPEDEFS, STRUCTURES, ENUMS) - * - *---------------------------------------------------------------------------- - */ - -/*----------------------------------------------------------------------------- - * DEFINITIONS AND MACROS - * - *----------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------- - * TYPEDEFS, STRUCTURES, ENUMS - * - *---------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------- - * Prototypes to Interface from Feature Code - * - *---------------------------------------------------------------------------- - */ - -/** - * Manually control bus number assignment. - * - */ -BOOLEAN -GetOverrideBusNumbers ( - IN UINT8 Node, - IN UINT8 Link, - OUT UINT8 *SecBus, - OUT UINT8 *SubBus, - IN STATE_DATA *State - ); - -/** - * Get Manual BUID assignment list. - * - */ -BOOLEAN -GetManualBuidSwapList ( - IN UINT8 Node, - IN UINT8 Link, - OUT BUID_SWAP_LIST **List, - IN STATE_DATA *State - ); - -/** - * Override capabilities of a device. - * - */ - -VOID -GetDeviceCapOverride ( - IN UINT8 HostNode, - IN UINT8 HostLink, - IN UINT8 Depth, - IN PCI_ADDR PciAddress, - IN UINT32 DevVenId, - IN UINT8 Revision, - IN UINT8 Link, - IN OUT UINT8 *LinkWidthIn, - IN OUT UINT8 *LinkWidthOut, - IN OUT UINT32 *FreqCap, - IN OUT UINT32 *Clumping, - IN STATE_DATA *State - ); - -/** - * Get limits for non-coherent Links. - * - */ -VOID -GetIoPcbLimits ( - IN UINT8 HostNode, - IN UINT8 HostLink, - IN UINT8 Depth, - IN OUT UINT8 *DownstreamLinkWidthLimit, - IN OUT UINT8 *UpstreamLinkWidthLimit, - IN OUT UINT32 *PcbFreqCap, - IN STATE_DATA *State - ); - -#endif /* _HT_INTERFACE_NONCOHERENT_H_ */ diff --git a/src/vendorcode/amd/agesa/f12/Proc/HT/htMain.c b/src/vendorcode/amd/agesa/f12/Proc/HT/htMain.c deleted file mode 100644 index af8d63ee17..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/HT/htMain.c +++ /dev/null @@ -1,579 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * HyperTransport features and sequence implementation. - * - * Implements the external AmdHtInitialize entry point. - * Contains routines for directing the sequence of available features. - * Mostly, but not exclusively, AGESA_TESTPOINT invocations should be - * contained in this file, and not in the feature code. - * - * From a build option perspective, it may be that a few lines could be removed - * from compilation in this file for certain options. It is considered that - * the code savings from this are too small to be of concern and this file - * should not have any explicit build option implementation. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: HyperTransport - * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $ - * - */ -/* - ***************************************************************************** - * - * Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * *************************************************************************** - * - */ - -/* - *---------------------------------------------------------------------------- - * MODULES USED - * - *---------------------------------------------------------------------------- - */ - - - -#include "AGESA.h" -#include "AdvancedApi.h" -#include "amdlib.h" -#include "Ids.h" -#include "Topology.h" -#include "htFeat.h" -#include "htInterface.h" -#include "htNb.h" -#include "heapManager.h" -#include "cpuRegisters.h" -#include "cpuServices.h" -#include "OptionsHt.h" -#include "Filecode.h" -CODE_GROUP (G1_PEICC) -RDATA_GROUP (G1_PEICC) - -#define FILECODE PROC_HT_HTMAIN_FILECODE -#define APIC_Base_BSP 8 -#define APIC_Base 0x1b - -extern OPTION_HT_CONFIGURATION OptionHtConfiguration; - -BOOLEAN -STATIC -IsBootCore ( - IN STATE_DATA *State - ); - -/*----------------------------------------------------------------------------------------*/ -/** - * Update maps with the core range for each module. - * - * Cores are numbered relative to a Processor, but sometimes there is a need to know the - * starting and ending core ids on a particular node. This same info is also useful for - * supporting the Core count on a node other than the one currently executing. - * - * For each Processor, get the core count of each node using the family specific PCI core count - * interface. The order of cores in a processor, and whether it is special for the BSP is family - * specific. But whether the processor orders core ids by module or node, iterate in the right - * order and use the counts to determine each start and end range. - * - * Update compute unit status for each node. - * - * @param[in] State number of Nodes discovered. -*/ -VOID -STATIC -UpdateCoreRanges ( - IN STATE_DATA *State - ) -{ - UINT8 Node; - UINT8 ProcessorCores; - UINT8 ModuleCoreCount[MAX_DIES]; - UINT8 Socket; - UINT8 Module; - - ASSERT (State->SocketDieToNodeMap != NULL); - ASSERT (State->NodeToSocketDieMap != NULL); - - for (Socket = 0; Socket < MAX_SOCKETS; Socket++) { - // Is a Processor present in Socket? - if ((*State->SocketDieToNodeMap)[Socket][0].Node != HT_LIST_TERMINAL) { - // Get all the Module core counts for this processor - // Note that the core counts are 1 based counts. - // Since Compute Unit info is not module ordering dependent, write it now. - for (Module = 0; Module < MAX_DIES; Module++) { - if ((*State->SocketDieToNodeMap)[Socket][Module].Node != HT_LIST_TERMINAL) { - ModuleCoreCount[Module] = State->Nb->GetNumCoresOnNode ((*State->SocketDieToNodeMap)[Socket][Module].Node, State->Nb); - (*State->SocketDieToNodeMap)[Socket][Module].EnabledComputeUnits = - State->Nb->GetEnabledComputeUnits ((*State->SocketDieToNodeMap)[Socket][Module].Node, State->Nb); - (*State->SocketDieToNodeMap)[Socket][Module].DualCoreComputeUnits = - State->Nb->GetDualCoreComputeUnits ((*State->SocketDieToNodeMap)[Socket][Module].Node, State->Nb); - } else { - ModuleCoreCount[Module] = 0; - } - } - // Determine the core ordering rule for this processor. - if ((((*State->NodeToSocketDieMap)[0].Socket == Socket) && State->Nb->IsOrderBSPCoresByNode) || - (!State->Nb->IsOrderCoresByModule)) { - // Order core ranges on this processor by Node Id. - ProcessorCores = 0; - for (Node = 0; Node < State->Nb->GetNodeCount (State->Nb); Node++) { - // Is this node a module in this processor? - if ((*State->NodeToSocketDieMap)[Node].Socket == Socket) { - Module = (*State->NodeToSocketDieMap)[Node].Die; - if (ModuleCoreCount[Module] != 0) { - (*State->SocketDieToNodeMap)[Socket][Module].LowCore = ProcessorCores; - (*State->SocketDieToNodeMap)[Socket][Module].HighCore = ProcessorCores + (ModuleCoreCount[Module] - 1); - IDS_HDT_CONSOLE ( - HT_TRACE, - (IsBootCore (State) ? - "Topology: Socket %d, Die %d, is Node %d, with Cores %d thru %d. Compute Unit status (0x%x,0x%x).\n" : - ""), - Socket, - Module, - Node, - (*State->SocketDieToNodeMap)[Socket][Module].LowCore, - (*State->SocketDieToNodeMap)[Socket][Module].HighCore, - (*State->SocketDieToNodeMap)[Socket][Module].EnabledComputeUnits, - (*State->SocketDieToNodeMap)[Socket][Module].DualCoreComputeUnits - ); - ProcessorCores = ProcessorCores + ModuleCoreCount[Module]; - } - } - } - } else { - // Order core ranges in this processor by Module Id. - ProcessorCores = 0; - for (Module = 0; Module < MAX_DIES; Module++) { - if (ModuleCoreCount[Module] != 0) { - (*State->SocketDieToNodeMap)[Socket][Module].LowCore = ProcessorCores; - (*State->SocketDieToNodeMap)[Socket][Module].HighCore = ProcessorCores + (ModuleCoreCount[Module] - 1); - IDS_HDT_CONSOLE ( - HT_TRACE, - (IsBootCore (State) ? - "Topology: Socket %d, Die %d, is Node %d, with Cores %d thru %d. Compute Unit status (0x%x,0x%x).\n" : - ""), - Socket, - Module, - (*State->SocketDieToNodeMap)[Socket][Module].Node, - (*State->SocketDieToNodeMap)[Socket][Module].LowCore, - (*State->SocketDieToNodeMap)[Socket][Module].HighCore, - (*State->SocketDieToNodeMap)[Socket][Module].EnabledComputeUnits, - (*State->SocketDieToNodeMap)[Socket][Module].DualCoreComputeUnits - ); - ProcessorCores = ProcessorCores + ModuleCoreCount[Module]; - } - } - } - } - } -} - -/*----------------------------------------------------------------------------------------*/ -/** - * Complete the coherent init with any system level initialization. - * - * Find the total number of cores and update the number of Nodes and cores in all cpus. - * Limit cpu config access to installed cpus. - * - * @param[in] State number of Nodes discovered. -*/ -VOID -STATIC -FinalizeCoherentInit ( - IN STATE_DATA *State - ) -{ - UINT8 Node; - UINT8 TotalCores; - - TotalCores = 0; - - for (Node = 0; Node < (State->NodesDiscovered + 1); Node++) { - TotalCores = TotalCores + State->Nb->GetNumCoresOnNode (Node, State->Nb); - } - - for (Node = 0; Node < (State->NodesDiscovered + 1); Node++) { - State->Nb->SetTotalNodesAndCores (Node, State->NodesDiscovered + 1, TotalCores, State->Nb); - } - - // Set all nodes to limit config space based on node count, after all nodes have a valid count. - // (just being cautious, probably we could combine the loops.) - for (Node = 0; Node < (State->NodesDiscovered + 1); Node++) { - State->Nb->LimitNodes (Node, State->Nb); - } -} - -/*----------------------------------------------------------------------------------------*/ -/** - * Initialize the coherent fabric. - * - * Perform discovery and initialization of the coherent fabric, for builds including - * support for multiple coherent nodes. - * - * @param[in] State global state - */ -VOID -STATIC -CoherentInit ( - IN OUT STATE_DATA *State - ) -{ - UINT8 i; - UINT8 j; - UINT8 ModuleType; - UINT8 Module; - UINT8 HardwareSocket; - COHERENT_FABRIC Fabric; - - // Because Node 0, the BSP, is not discovered, initialize info about it specially here. - // Allocate Socket Die Map. - // While the BSP is always capable of being the only processor in the system, call the - // IsExceededCapable method to make sure the BSP's capability is included in the aggregate system - // capability. We don't care to check the return value. - // - State->Fabric = &Fabric; - State->NodesDiscovered = 0; - State->TotalLinks = 0; - State->SysMpCap = MAX_NODES; - State->Nb->IsExceededCapable (0, State, State->Nb); - HardwareSocket = State->Nb->GetSocket (0, 0, State->Nb); - ModuleType = 0; - Module = 0; - State->Nb->GetModuleInfo (0, &ModuleType, &Module, State->Nb); - // No predecessor info for BSP, so pass 0xFF for those parameters. - State->HtInterface->SetNodeToSocketMap (0xFF, 0xFF, 0xFF, 0, HardwareSocket, Module, State); - - // Initialize system state data structures - for (i = 0; i < MAX_NODES; i++) { - State->Fabric->SysDegree[i] = 0; - for (j = 0; j < MAX_NODES; j++) { - State->Fabric->SysMatrix[i][j] = 0; - } - } - - // - // Call the coherent init features - // - - // Discovery - State->HtFeatures->CoherentDiscovery (State); - State->HtInterface->PostMapToAp (State); - // Topology matching and Routing - AGESA_TESTPOINT (TpProcHtTopology, State->ConfigHandle); - State->HtFeatures->LookupComputeAndLoadRoutingTables (State); - State->HtFeatures->MakeHopCountTable (State); - - // UpdateCoreRanges requires the other maps to be initialized, and the node count set. - FinalizeCoherentInit (State); - UpdateCoreRanges (State); - State->Fabric = NULL; -} - -/*************************************************************************** - *** Non-coherent init code *** - *** Algorithms *** - ***************************************************************************/ -/*----------------------------------------------------------------------------------------*/ -/** - * Initialize the non-coherent fabric. - * - * Begin with the Compat Link on the BSP, then find and initialize all other - * non-coherent chains. - * - * @param[in] State our global state - */ -VOID -STATIC -NcInit ( - IN STATE_DATA *State - ) -{ - UINT8 Node; - UINT8 Link; - UINT8 CompatLink; - FINAL_LINK_STATE FinalLinkState; - - // Initialize the southbridge chain. - State->AutoBusCurrent = State->HtBlock->AutoBusStart; - State->UsedCfgMapEntries = 0; - CompatLink = State->Nb->ReadSouthbridgeLink (State->Nb); - State->HtFeatures->ProcessLink (0, CompatLink, TRUE, State); - - // Find and initialize all other non-coherent chains. - for (Node = 0; Node <= State->NodesDiscovered; Node++) { - for (Link = 0; Link < State->Nb->MaxLinks; Link++) { - // Skip the Link, if any of these tests indicate - FinalLinkState = State->HtInterface->GetIgnoreLink (Node, Link, State->Nb->DefaultIgnoreLinkList, State); - if (FinalLinkState == UNMATCHED) { - if ( !((Node == 0) && (Link == CompatLink))) { - if ( !(State->Nb->ReadTrueLinkFailStatus (Node, Link, State, State->Nb))) { - if (State->Nb->VerifyLinkIsNonCoherent (Node, Link, State->Nb)) { - State->HtFeatures->ProcessLink (Node, Link, FALSE, State); - } - } - } - } - } - } -} - -/*************************************************************************** - *** Link Optimization *** - ***************************************************************************/ - -/*----------------------------------------------------------------------------------------*/ -/** - * Optimize Link Features. - * - * Based on Link capabilities, apply optimization rules to come up with the best - * settings, including several external limit decision from the interface. This includes - * handling of subLinks. Finally, after the port list data is updated, set the hardware - * state for all Links. - * - * @param[in] State our global state - */ -VOID -STATIC -LinkOptimization ( - IN STATE_DATA *State - ) -{ - AGESA_TESTPOINT (TpProcHtOptGather, State->ConfigHandle); - State->HtFeatures->GatherLinkData (State); - - AGESA_TESTPOINT (TpProcHtOptRegang, State->ConfigHandle); - State->HtFeatures->RegangLinks (State); - - AGESA_TESTPOINT (TpProcHtOptLinks, State->ConfigHandle); - State->HtFeatures->SelectOptimalWidthAndFrequency (State); - - // A likely cause of mixed Retry settings on coherent links is sublink ratio balancing - // so check this after doing the sublinks. - AGESA_TESTPOINT (TpProcHtOptSubLinks, State->ConfigHandle); - State->HtFeatures->SubLinkRatioFixup (State); - if (State->HtFeatures->IsCoherentRetryFixup (State)) { - // Fix sublinks again within HT1 only frequencies, as ratios may be invalid again. - State->HtFeatures->SubLinkRatioFixup (State); - } - - AGESA_TESTPOINT (TpProcHtOptFinish, State->ConfigHandle); - State->HtFeatures->SetLinkData (State); -} - -/*----------------------------------------------------------------------------------------*/ -/** - * Handle system and performance tunings. - * - * Including traffic distribution, fifo and - * buffer tuning that can't be placed in the register table, - * and special config tunings. - * - * @param[in] State Total Nodes, port list data - */ -VOID -STATIC -Tuning ( - IN STATE_DATA *State - ) -{ - UINT8 Node; - - // See if traffic distribution can be done and do it if so. - // - AGESA_TESTPOINT (TpProcHtTrafficDist, State->ConfigHandle); - State->HtFeatures->TrafficDistribution (State); - - // For each Node, invoke northbridge specific buffer tunings that can not be done in reg table. - // - AGESA_TESTPOINT (TpProcHtTuning, State->ConfigHandle); - for (Node = 0; Node < (State->NodesDiscovered + 1); Node++) { - State->Nb->BufferOptimizations (Node, State, State->Nb); - } -} - -/*----------------------------------------------------------------------------------------*/ -/** - * Initialize the Node and Socket maps for an AP Core. - * - * In each core's local heap, create a Node to Socket map and a Socket/Module to Node map. - * The mapping is filled in by reading the AP Mailboxes from PCI config on each node. - * - * @param[in] State global state, input data - * - */ -VOID -STATIC -InitApMaps ( - IN STATE_DATA *State - ) -{ - UINT8 Node; - AP_MAIL_INFO NodeApMailBox; - - // There is no option to not have socket - node maps, if they aren't allocated that is a fatal bug. - ASSERT (State->SocketDieToNodeMap != NULL); - ASSERT (State->NodeToSocketDieMap != NULL); - - for (Node = 0; Node < State->Nb->GetNodeCount (State->Nb); Node++) { - NodeApMailBox = State->Nb->RetrieveMailbox (Node, State->Nb); - (*State->SocketDieToNodeMap)[NodeApMailBox.Fields.Socket][NodeApMailBox.Fields.Module].Node = Node; - (*State->NodeToSocketDieMap)[Node].Socket = (UINT8)NodeApMailBox.Fields.Socket; - (*State->NodeToSocketDieMap)[Node].Die = (UINT8)NodeApMailBox.Fields.Module; - } - // This requires the other maps to be initialized. - UpdateCoreRanges (State); -} - -/*----------------------------------------------------------------------------------------*/ -/** - * Is the currently running core the BSC? - * - * Determine whether the init steps for BSC or AP core should be run. - * - * @param[in] State global state, input data - * - * @retval TRUE This is the boot core. - * @retval FALSE This is not the boot core. - */ -BOOLEAN -STATIC -IsBootCore ( - IN STATE_DATA *State - ) -{ - UINT64 Value; - - LibAmdMsrRead (APIC_Base, &Value, State->ConfigHandle); - - return ((BOOLEAN) (((UINT32) (Value & 0xFFFFFFFF) & ((UINT32)1 << APIC_Base_BSP)) != 0)); -} - -/*************************************************************************** - *** HT Initialize *** - ***************************************************************************/ - -/*----------------------------------------------------------------------------------------*/ -/** - * The top level external interface for Hypertransport Initialization. - * - * Create our initial internal state, initialize the coherent fabric, - * initialize the non-coherent chains, and perform any required fabric tuning or - * optimization. - * - * @param[in] StdHeader Opaque handle to standard config header - * @param[in] PlatformConfiguration The platform configuration options. - * @param[in] AmdHtInterface HT Interface structure. - * - * @retval AGESA_SUCCESS Only information events logged. - * @retval AGESA_ALERT Sync Flood or CRC error logged. - * @retval AGESA_WARNING Example: expected capability not found - * @retval AGESA_ERROR logged events indicating some devices may not be available - * @retval AGESA_FATAL Mixed Family or MP capability mismatch - * - */ -AGESA_STATUS -AmdHtInitialize ( - IN AMD_CONFIG_PARAMS *StdHeader, - IN PLATFORM_CONFIGURATION *PlatformConfiguration, - IN AMD_HT_INTERFACE *AmdHtInterface - ) -{ - STATE_DATA State; - NORTHBRIDGE Nb; - HT_FEATURES HtFeatures; - HT_INTERFACE HtInterface; - AGESA_STATUS DeallocateStatus; - AP_MAIL_INFO ApMailboxInfo; - UINT8 ApNode; - - ALLOCATE_HEAP_PARAMS AllocHeapParams; - - State.HtBlock = AmdHtInterface; - State.ConfigHandle = StdHeader; - State.PlatformConfiguration = PlatformConfiguration; - - // Get the current HT internal interface (to HtBlock data) - NewHtInterface (&HtInterface, State.ConfigHandle); - State.HtInterface = &HtInterface; - - // Get the current HT Feature Set - NewHtFeatures (&HtFeatures, State.ConfigHandle); - State.HtFeatures = &HtFeatures; - - // Initialize from static options - State.IsUsingRecoveryHt = OptionHtConfiguration.IsUsingRecoveryHt; - State.IsSetHtCrcFlood = OptionHtConfiguration.IsSetHtCrcFlood; - State.IsUsingUnitIdClumping = OptionHtConfiguration.IsUsingUnitIdClumping; - - // Initialize for status and event output - State.MaxEventClass = AGESA_SUCCESS; - - // Allocate permanent heap structs that are interfaces to other AGESA services. - State.HtInterface->NewNodeAndSocketTables (&State); - - if (IsBootCore (&State)) { - AGESA_TESTPOINT (TpProcHtEntry, State.ConfigHandle); - // Allocate Bsp only interface heap structs. - State.HtInterface->NewHopCountTable (&State); - // Allocate heap for our temporary working space. - AllocHeapParams.RequestedBufferSize = (sizeof (PORT_DESCRIPTOR) * (MAX_PLATFORM_LINKS * 2)); - AllocHeapParams.BufferHandle = HT_STATE_DATA_HANDLE; - AllocHeapParams.Persist = HEAP_LOCAL_CACHE; - if (HeapAllocateBuffer (&AllocHeapParams, State.ConfigHandle) == AGESA_SUCCESS) { - State.PortList = (PORT_LIST)AllocHeapParams.BufferPtr; - // Create the BSP's northbridge. - NewNorthBridge (0, &State, &Nb); - State.Nb = &Nb; - - CoherentInit (&State); - NcInit (&State); - LinkOptimization (&State); - Tuning (&State); - - DeallocateStatus = HeapDeallocateBuffer (HT_STATE_DATA_HANDLE, State.ConfigHandle); - ASSERT (DeallocateStatus == AGESA_SUCCESS); - AGESA_TESTPOINT (TpProcHtDone, State.ConfigHandle); - } else { - ASSERT (FALSE); - State.MaxEventClass = AGESA_ERROR; - // Cannot Log entry due to heap allocate failed. - } - } else { - // Do the AP HT Init, which produces Node and Socket Maps for the AP's use. - AGESA_TESTPOINT (TpProcHtApMapEntry, State.ConfigHandle); - GetApMailbox (&ApMailboxInfo.Info, State.ConfigHandle); - ASSERT (ApMailboxInfo.Fields.Node < MAX_NODES); - ApNode = (UINT8)ApMailboxInfo.Fields.Node; - NewNorthBridge (ApNode, &State, &Nb); - State.Nb = &Nb; - InitApMaps (&State); - AGESA_TESTPOINT (TpProcHtApMapDone, State.ConfigHandle); - } - return State.MaxEventClass; -} diff --git a/src/vendorcode/amd/agesa/f12/Proc/HT/htNb.c b/src/vendorcode/amd/agesa/f12/Proc/HT/htNb.c deleted file mode 100644 index 428e897a8a..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/HT/htNb.c +++ /dev/null @@ -1,247 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * Construct a northbridge interface for a Node. - * - * Handle build options and run-time detection. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: HyperTransport - * @e \$Revision: 44846 $ @e \$Date: 2011-01-07 13:21:05 +0800 (Fri, 07 Jan 2011) $ - * - */ -/* -***************************************************************************** -* -* Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* *************************************************************************** -* -*/ - -/* - *---------------------------------------------------------------------------- - * MODULES USED - * - *---------------------------------------------------------------------------- - */ - -#include "AGESA.h" -#include "amdlib.h" -#include "OptionsHt.h" -#include "Ids.h" -#include "Topology.h" -#include "htFeat.h" -#include "htNb.h" -#include "htNbCommonHardware.h" -#include "CommonReturns.h" -#include "cpuRegisters.h" -#include "cpuFamilyTranslation.h" -#include "cpuFamRegisters.h" -CODE_GROUP (G1_PEICC) -RDATA_GROUP (G1_PEICC) - -#include "Filecode.h" - -#define FILECODE PROC_HT_HTNB_FILECODE - -extern OPTION_HT_CONFIGURATION OptionHtConfiguration; - -/*---------------------------------------------------------------------------- - * DEFINITIONS AND MACROS - * - *---------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------- - * TYPEDEFS AND STRUCTURES - * - *---------------------------------------------------------------------------- - */ -/*---------------------------------------------------------------------------- - * PROTOTYPES OF LOCAL FUNCTIONS - * - *---------------------------------------------------------------------------- - */ - -/*************************************************************************** - *** FAMILY/NORTHBRIDGE SPECIFIC FUNCTIONS *** - ***************************************************************************/ - - -/** - * Initial construction data for no HT Northbridge. - */ -CONST NORTHBRIDGE ROMDATA HtFam10NbNone = -{ - 1, - (PF_WRITE_ROUTING_TABLE)CommonVoid, - (PF_WRITE_NODEID)CommonVoid, - (PF_READ_DEFAULT_LINK)CommonReturnZero8, - (PF_ENABLE_ROUTING_TABLES)CommonVoid, - (PF_DISABLE_ROUTING_TABLES)CommonVoid, - (PF_VERIFY_LINK_IS_COHERENT)CommonReturnFalse, - (PF_READ_TOKEN)CommonReturnZero8, - (PF_WRITE_TOKEN)CommonVoid, - (PF_WRITE_FULL_ROUTING_TABLE)CommonVoid, - (PF_IS_ILLEGAL_TYPE_MIX)CommonReturnFalse, - (PF_IS_EXCEEDED_CAPABLE)CommonReturnFalse, - (PF_STOP_LINK)CommonVoid, - (PF_HANDLE_SPECIAL_LINK_CASE)CommonReturnFalse, - (PF_HANDLE_SPECIAL_NODE_CASE)CommonReturnFalse, - (PF_READ_SB_LINK)CommonReturnZero8, - (PF_VERIFY_LINK_IS_NON_COHERENT)CommonReturnFalse, - (PF_SET_CONFIG_ADDR_MAP)CommonVoid, - (PF_NORTH_BRIDGE_FREQ_MASK)CommonReturnZero32, - (PF_GATHER_LINK_FEATURES)CommonVoid, - (PF_SET_LINK_REGANG)CommonVoid, - (PF_SET_LINK_FREQUENCY)CommonVoid, - (PF_SET_LINK_UNITID_CLUMPING)CommonVoid, - (PF_WRITE_TRAFFIC_DISTRIBUTION)CommonVoid, - (PF_WRITE_LINK_PAIR_DISTRIBUTION)CommonVoid, - (PF_WRITE_VICTIM_DISTRIBUTION)CommonVoid, - (PF_BUFFER_OPTIMIZATIONS)CommonVoid, - (PF_GET_NUM_CORES_ON_NODE)CommonReturnZero8, - (PF_SET_TOTAL_NODES_AND_CORES)CommonVoid, - (PF_GET_NODE_COUNT)CommonReturnZero8, - (PF_LIMIT_NODES)CommonVoid, - (PF_READ_TRUE_LINK_FAIL_STATUS)CommonReturnFalse, - (PF_GET_NEXT_LINK)CommonReturnZero32, - (PF_GET_PACKAGE_LINK)CommonReturnZero8, - (PF_MAKE_LINK_BASE)CommonReturnZero32, - (PF_GET_MODULE_INFO)CommonVoid, - (PF_POST_MAILBOX)CommonVoid, - (PF_RETRIEVE_MAILBOX)CommonReturnZero32, - (PF_GET_SOCKET)CommonReturnZero8, - (PF_GET_ENABLED_COMPUTE_UNITS)CommonReturnZero8, - (PF_GET_DUALCORE_COMPUTE_UNITS)CommonReturnZero8, - 0, - 0, - 0, - TRUE, - TRUE, - 0, - NULL, - 0, - NULL, - (PF_MAKE_KEY)CommonReturnZero64, - NULL -}; - -/*----------------------------------------------------------------------------------------*/ -/** - * Make a compatibility key. - * - * @HtNbMethod{::F_MAKE_KEY} - * - * Private routine to northbridge code. - * Create a key which can be used to determine whether a Node is compatible with - * the discovered configuration so far. Currently, that means the family, - * extended family of the new Node are the same as the BSP's. Family specific - * implementations can add whatever else is necessary. - * - * @param[in] Node the Node - * @param[in] Nb this northbridge - * - * @return the key - */ -UINT64 -MakeKey ( - IN UINT8 Node, - IN NORTHBRIDGE *Nb - ) -{ - CPU_LOGICAL_ID LogicalId; - UINT32 RawCpuId; - PCI_ADDR Reg; - - Reg.AddressValue = MAKE_SBDFO (MakePciSegmentFromNode (Node), - MakePciBusFromNode (Node), - MakePciDeviceFromNode (Node), - CPU_NB_FUNC_03, - REG_NB_CPUID_3XFC); - - LibAmdPciReadBits (Reg, 31, 0, &RawCpuId, Nb->ConfigHandle); - GetLogicalIdFromCpuid (RawCpuId, &LogicalId, Nb->ConfigHandle); - return LogicalId.Family; -} - -/*----------------------------------------------------------------------------------------*/ -/** - * Construct a new northbridge. - * - * This routine encapsulates knowledge of how to tell significant differences between - * families of supported northbridges and what routines can be used in common and - * which are unique. A fully populated northbridge interface is provided by Nb. - * - * @param[in] Node create a northbridge interface for this Node. - * @param[in] State global state - * @param[out] Nb the caller's northbridge structure to initialize. - */ -VOID -NewNorthBridge ( - IN UINT8 Node, - IN STATE_DATA *State, - OUT NORTHBRIDGE *Nb - ) -{ - CPU_LOGICAL_ID LogicalId; - UINT64 Match; - UINT32 RawCpuId; - PCI_ADDR Reg; - NORTHBRIDGE **InitializerInstance; - - // Start with enough of the key to identify the northbridge interface - Reg.AddressValue = MAKE_SBDFO (MakePciSegmentFromNode (Node), - MakePciBusFromNode (Node), - MakePciDeviceFromNode (Node), - CPU_NB_FUNC_03, - REG_NB_CPUID_3XFC); - LibAmdPciReadBits (Reg, 31, 0, &RawCpuId, State->ConfigHandle); - IDS_HDT_CONSOLE (HT_TRACE, "AMD Processor at Node %d has raw CPUID=%x.\n", Node, RawCpuId); - GetLogicalIdFromCpuid (RawCpuId, &LogicalId, State->ConfigHandle); - Match = LogicalId.Family; - - // Test each Northbridge interface in turn looking for a match. - // Use it to Init the Nb struct if a match is found. - // - ASSERT (OptionHtConfiguration.HtOptionFamilyNorthbridgeList != NULL); - InitializerInstance = (NORTHBRIDGE **) (OptionHtConfiguration.HtOptionFamilyNorthbridgeList); - while (*InitializerInstance != NULL) { - if ((Match & (*InitializerInstance)->CompatibleKey) != 0) { - LibAmdMemCopy ((VOID *)Nb, (VOID *)*InitializerInstance, (UINT32) sizeof (NORTHBRIDGE), State->ConfigHandle); - break; - } - InitializerInstance++; - } - // There must be an available northbridge implementation. - ASSERT (*InitializerInstance != NULL); - - // Set the config handle for passing to the library. - Nb->ConfigHandle = State->ConfigHandle; -} - diff --git a/src/vendorcode/amd/agesa/f12/Proc/HT/htNb.h b/src/vendorcode/amd/agesa/f12/Proc/HT/htNb.h deleted file mode 100644 index ef266e0315..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/HT/htNb.h +++ /dev/null @@ -1,1133 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * HT NorthBridge header - * - * Defines the interface to the HT NorthBridge module for use by other internal - * HT modules. This is not a wrapper or external interface, "public" in the - * comments below is used in the class definition style and refers to HT client - * modules only ("private" being for use only by the HT NB module itself). - * - * It is expected that there will be multiple northbridge implementation files all - * conforming to this common interface. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: HyperTransport - * @e \$Revision: 44846 $ @e \$Date: 2011-01-07 13:21:05 +0800 (Fri, 07 Jan 2011) $ - * - */ -/* -***************************************************************************** -* -* Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* *************************************************************************** -* -*/ - -#ifndef _HT_NB_H_ -#define _HT_NB_H_ - -/** - * @page htimplnb HT Northbridge Implementation Guide - * - * The HT Northbridge provides access to the Northbridge hardware, in a manner that - * isolates calling code from knowledge about the hardware implementation or which - * features are supported in the current build. This is the mechanism in the HT code for - * supporting new Family or Model northbridges, as well as the means for supporting - * multiple northbridges in a single build or mixed revision northbridge sets. - * - * @par Adding a Method to the Northbridge - * - * To add a new method to the Northbridge, follow these steps. - *
    - *
  • Create a typedef for the Method with the correct parameters and return type. - * - *
      - *
    • Name the method typedef (F_METHOD_NAME)(), where METHOD_NAME is the same - * name as the method table item, but with "_"'s and UPPERCASE, rather than mixed case. - * @n typedef VOID (F_METHOD_NAME)(); @n - * - *
    • Make a reference type for references to a method implementation: - * @n /// Reference to a Method - * @n typedef F_METHOD_NAME *PF_METHOD_NAME @n - *
    - * - *
  • One of the parameters to @b all northbridge Methods is @b required to be a - * reference to its current northbridge object. By convention, this is the - * last parameter. - * - *
  • Provide a standard doxygen function preamble for the Method typedef. Begin the - * detailed description by providing a reference to the method instances page by including - * the lines below: - * @code - * * - * * @HtNbInstances - * * - * @endcode - * @note It is important to provide documentation for the method type, because the method may not - * have an implementation in any families supported by the current package. @n - * - *
  • Add to the NORTHBRIDGE struct an item for the Method: - * @n PF_METHOD_NAME MethodName; ///< Method: description. @n - *
- * - * @par Implementing an Instance of a Northbridge method. - * - * To implement an instance of a method for a specific feature follow these steps. - * - * - In appropriate files, implement the method with the return type and parameters - * matching the Method typedef. - * - If the Method implementation is common to all families, use the northbridge file - * for the function area, for example, add a new coherent initialization support method to the - * coherent northbridge file. - * - If the Method implementation is unique to each supported northbridge, use the - * family specific file for that function area (create it, if it doesn't already exist). - * The family specific files have the same name as the common one suffixed with "FamNN", - * or "FamNNRevX" if for a model or revision. - * - * - Name the function MethodName(). If Family specific, FamNNMethodName(). - * - * - Create a doxygen function preamble for the method instance. Begin the detailed description with - * an Implements command to reference the method type and add this instance to the Method Instances page. - * @code - * * - * * @HtNbMethod{::F_METHOD_NAME}. - * * - * @endcode - * - * - To access other northbridge routines or data as part of the method implementation, - * the function must use Nb->OtherMethod(). Do not directly access other northbridge - * routines, because in the table there may be overrides or this routine may be shared by - * multiple configurations. - * - * - Add the instance, or the correct family specific instance, to the NORTHBRIDGE instances - * used by the northbridge constructor. - * - * - If a northbridge does not need an instance of the method use one of the CommonReturns from - * CommonReturns.h with the same return type. - * - * @par Making common Northbridge Methods. - * - * In some cases, Northbridge methods can easily have a common implementation because the hardware - * is very compatible or is even standard. In other cases, where processor family northbridges - * differ in their implementation, it may be possible to provide a single, common method - * implementation. This can be accomplished by adding Northbridge data members. - * - * For example, a bit position or bit field mask can be used to accommodate different bit placement or size. - * Another example, a small table can be used to translate index values from a common set - * to specific sets. - * - * The Northbridge Method Instance must use its NORTHBRIDGE reference parameter to access - * private data members. - * - * @par Invoking HT Northbridge Methods. - * - * Each unique northbridge is constructed based on matching the current northbridge. - * @n @code - * NORTHBRIDGE Nb; - * // Create the BSP's northbridge. - * NewNorthBridge (0, State, &Nb); - * State->Nb = &Nb; - * @endcode - * - * The following example shows how to invoke a Northbridge method. - * @n @code - * State->Nb->MethodName (State->Nb); - * @endcode - * - */ - -/*---------------------------------------------------------------------------- - * Mixed (DEFINITIONS AND MACROS / TYPEDEFS, STRUCTURES, ENUMS) - * - *---------------------------------------------------------------------------- - */ - -/*----------------------------------------------------------------------------- - * DEFINITIONS AND MACROS - * - *----------------------------------------------------------------------------- - */ - -/** Use a macro to convert a Node number to a PCI device. If some future port of - * this code needs to, this can easily be replaced by the function declaration: - * UINT8 makePCIDeviceFromNode(UINT8 Node); - */ -#define MakePciDeviceFromNode(Node) \ - ((UINT8) (24 + (Node))) - -/** Use a macro to convert a Node number to a PCI bus. If some future port of - * this code needs to, this can easily be replaced by the function declaration: - * UINT8 MakePciBusFromNode(UINT8 Node); - */ -#define MakePciBusFromNode(Node) \ - ((UINT8) (0)) - -/** Use a macro to convert a Node number to a PCI Segment. If some future port of - * this code needs to, this can easily be replaced by the function declaration: - * UINT8 MakePciSegmentFromNode(UINT8 Node); - */ -#define MakePciSegmentFromNode(Node) \ - ((UINT8) (0)) - -/*---------------------------------------------------------------------------- - * TYPEDEFS, STRUCTURES, ENUMS - * - *---------------------------------------------------------------------------- - */ -/** - * Status for iterating through internal (if supported) and external links. - */ -typedef enum { - LinkIteratorEnd, ///< This is the end of all links, no valid link. - LinkIteratorExternal, ///< The next link (the one we got on this call) is an external link. - LinkIteratorInternal, ///< The next link (the one we got on this call) is an internal link. - LinkIteratorMax ///< For bounds checking and limit only. -} LINK_ITERATOR_STATUS; - -#define LINK_ITERATOR_BEGIN 0xFF - -/** - * Write a temporary Route. - * - * @HtNbInstances - * - * @param[in] Node The node on which to set a temporary route - * @param[in] Target A route to this node, which route table entry is to be set - * @param[in] Link The link which routes to the target node - * @param[in] Nb This northbridge - */ -typedef VOID F_WRITE_ROUTING_TABLE ( - IN UINT8 Node, - IN UINT8 Target, - IN UINT8 Link, - IN NORTHBRIDGE *Nb - ); -/// Reference to a method. -typedef F_WRITE_ROUTING_TABLE *PF_WRITE_ROUTING_TABLE; - -/** - * Modifies the NodeID register on the target Node - * - * @HtNbInstances - * - * @param[in] Node the Node that will have its NodeID altered. - * @param[in] NodeID the new value for NodeID - * @param[in] Nb this northbridge - */ -typedef VOID F_WRITE_NODEID ( - IN UINT8 Node, - IN UINT8 NodeID, - IN NORTHBRIDGE *Nb - ); -/// Reference to a method. -typedef F_WRITE_NODEID *PF_WRITE_NODEID; - -/** - * Read the Default Link - * - * @HtNbInstances - * - * @param[in] Node the Node that will have its NodeID altered. - * @param[in] Nb this northbridge - * - * @return The HyperTransport Link where the request to - * read the default Link came from. Since this code is running on the BSP, - * this should be the Link pointing back towards the BSP. - */ -typedef UINT8 F_READ_DEFAULT_LINK ( - IN UINT8 Node, - IN NORTHBRIDGE *Nb - ); -/// Reference to a method. -typedef F_READ_DEFAULT_LINK *PF_READ_DEFAULT_LINK; - -/** - * Turns routing tables on for a given Node - * - * @HtNbInstances - * - * @param[in] Node the Node that will have it's routing tables enabled - * @param[in] Nb this northbridge - */ -typedef VOID F_ENABLE_ROUTING_TABLES ( - IN UINT8 Node, - IN NORTHBRIDGE *Nb - ); -/// Reference to a method. -typedef F_ENABLE_ROUTING_TABLES *PF_ENABLE_ROUTING_TABLES; - -/** - * Turns routing tables off for a given Node - * - * @HtNbInstances - * - * @param[in] Node the Node that will have it's routing tables disabled - * @param[in] Nb this northbridge - */ -typedef VOID F_DISABLE_ROUTING_TABLES ( - IN UINT8 Node, - IN NORTHBRIDGE *Nb - ); -/// Reference to a method. -typedef F_DISABLE_ROUTING_TABLES *PF_DISABLE_ROUTING_TABLES; - -/** - * Verify that the Link is coherent, connected, and ready - * - * @HtNbInstances - * - * @param[in] Node the Node that will be examined - * @param[in] Link the Link on that Node to examine - * @param[in] Nb this northbridge - * - * @retval TRUE The Link is coherent - * @retval FALSE The Link has some other status -*/ -typedef BOOLEAN F_VERIFY_LINK_IS_COHERENT ( - IN UINT8 Node, - IN UINT8 Link, - IN NORTHBRIDGE *Nb - ); -/// Reference to a method. -typedef F_VERIFY_LINK_IS_COHERENT *PF_VERIFY_LINK_IS_COHERENT; - -/** - * Read the token stored in the scratchpad register field. - * - * @HtNbInstances - * - * @param[in] Node the Node that will be examined - * @param[in] Nb this northbridge - * - * @return the Token read from the Node - */ -typedef UINT8 F_READ_TOKEN ( - IN UINT8 Node, - IN NORTHBRIDGE *Nb - ); -/// Reference to a method. -typedef F_READ_TOKEN *PF_READ_TOKEN; - -/** - * Write the token stored in the scratchpad register - * - * @HtNbInstances - * - * @param[in] Node the Node that marked with token - * @param[in] Value the token Value - * @param[in] Nb this northbridge - */ -typedef VOID F_WRITE_TOKEN ( - IN UINT8 Node, - IN UINT8 Value, - IN NORTHBRIDGE *Nb - ); -/// Reference to a method. -typedef F_WRITE_TOKEN *PF_WRITE_TOKEN; - -/** - * Full Routing Table Register initialization - * - * @HtNbInstances - * - * @param[in] Node the Node that will be examined - * @param[in] Target the Target Node for these routes - * @param[in] ReqLink the Link for requests to Target - * @param[in] RspLink the Link for responses to Target - * @param[in] BroadcastLinks the broadcast Links - * @param[in] Nb this northbridge - */ -typedef VOID F_WRITE_FULL_ROUTING_TABLE ( - IN UINT8 Node, - IN UINT8 Target, - IN UINT8 ReqLink, - IN UINT8 RspLink, - IN UINT32 BroadcastLinks, - IN NORTHBRIDGE *Nb - ); -/// Reference to a method. -typedef F_WRITE_FULL_ROUTING_TABLE *PF_WRITE_FULL_ROUTING_TABLE; - -/** - * Determine whether a Node is compatible with the discovered configuration so far. - * - * @HtNbInstances - * - * @param[in] Node the Node - * @param[in] Nb this northbridge - * - * @retval TRUE the node is not compatible - * @retval FALSE the node is compatible - */ -typedef BOOLEAN F_IS_ILLEGAL_TYPE_MIX ( - IN UINT8 Node, - IN NORTHBRIDGE *Nb - ); -/// Reference to a method. -typedef F_IS_ILLEGAL_TYPE_MIX *PF_IS_ILLEGAL_TYPE_MIX; - -/** - * Return whether the current configuration exceeds the capability - * of the nodes detected. - * - * @HtNbInstances - * - * @param[in] Node the Node - * @param[in] State sysMpCap (updated) and NodesDiscovered - * @param[in] Nb this northbridge - * - * @retval TRUE system is not capable of current config. - * @retval FALSE system is capable of current config. - */ -typedef BOOLEAN F_IS_EXCEEDED_CAPABLE ( - IN UINT8 Node, - IN STATE_DATA *State, - IN NORTHBRIDGE *Nb - ); -/// Reference to a method. -typedef F_IS_EXCEEDED_CAPABLE *PF_IS_EXCEEDED_CAPABLE; - -/** - * Stop a link, so that it is isolated from a connected device. - * - * @HtNbInstances - * - * Use is for fatal incompatible configurations. - * While XMIT and RCV off are HT standard, the use of these bits - * is generally family specific. - * - * @param[in] Node the node to stop a link on. - * @param[in] Link the link to stop. - * @param[in] State access to special routine for writing link control register - * @param[in] Nb this northbridge. - */ -typedef VOID F_STOP_LINK ( - IN UINT8 Node, - IN UINT8 Link, - IN STATE_DATA *State, - IN NORTHBRIDGE *Nb - ); -/// Reference to a method. -typedef F_STOP_LINK *PF_STOP_LINK; - -/** - * Fix (hopefully) exceptional conditions. - * - * @HtNbInstances - * - * This routine is expected to be unimplemented for most families. - * Some configurations may require that links be processed specially to prevent - * serious problems, like hangs. Check for that condition in this routine, - * handle the link both for hardware and for adding to port list, if appropriate. - * If this routine adds the link to port list or the link should not be added, return TRUE. - * - * @param[in] Node The Node which has this link - * @param[in] Link The link to check for special conditions. - * @param[in] State our global state. - * @param[in] Nb this northbridge. - * - * @retval TRUE This link received special handling. - * @retval FALSE This link was not handled specially, handle it normally. - * - */ -typedef BOOLEAN F_HANDLE_SPECIAL_LINK_CASE ( - IN UINT8 Node, - IN UINT8 Link, - IN STATE_DATA *State, - IN NORTHBRIDGE *Nb - ); -/// Reference to a method. -typedef F_HANDLE_SPECIAL_LINK_CASE *PF_HANDLE_SPECIAL_LINK_CASE; - -/** - * Fix (hopefully) exceptional conditions. - * - * @HtNbInstances - * - * This routine is expected to be unimplemented for most families. - * Some configurations may require that nodes be processed specially to prevent - * serious problems, like hangs. Check for that condition in this routine, - * handle the node both for hardware and for adding to port list, if appropriate. - * If this routine adds the node to port list or the node should not be added, return TRUE. - * - * @param[in] Node The Node which need to be checked. - * @param[in] Link The link to check for special conditions. - * @param[in] State our global state. - * @param[in] Nb this northbridge. - * - * @retval TRUE This node received special handling. - * @retval FALSE This node was not handled specially, handle it normally. - * - */ -typedef BOOLEAN F_HANDLE_SPECIAL_NODE_CASE ( - IN UINT8 Node, - IN UINT8 Link, - IN STATE_DATA *State, - IN NORTHBRIDGE *Nb - ); -/// Reference to a method. -typedef F_HANDLE_SPECIAL_NODE_CASE *PF_HANDLE_SPECIAL_NODE_CASE; - -/** - * Get Info about Module Type of this northbridge - * - * @HtNbInstances - * - * @param[in] Node the Node - * @param[out] ModuleType 0 for Single, 1 for Multi - * @param[out] Module The module number of this node (0 if Single) - * @param[in] Nb this northbridge - * - */ -typedef VOID F_GET_MODULE_INFO ( - IN UINT8 Node, - OUT UINT8 *ModuleType, - OUT UINT8 *Module, - IN NORTHBRIDGE *Nb - ); -/// Reference to a method. -typedef F_GET_MODULE_INFO *PF_GET_MODULE_INFO; - -/** - * Post info to AP cores via a mailbox. - * - * @HtNbInstances - * - * @param[in] Node the Node - * @param[in] ApMailInfo The info to post - * @param[in] Nb this northbridge - * - */ -typedef VOID F_POST_MAILBOX ( - IN UINT8 Node, - IN AP_MAILBOXES ApMailInfo, - IN NORTHBRIDGE *Nb - ); -/// Reference to a method. -typedef F_POST_MAILBOX *PF_POST_MAILBOX; - -/** - * Retrieve info from a node's AP mailbox. - * - * @HtNbInstances - * - * @param[in] Node the Node - * @param[in] ApMailInfo The info to post - * @param[in] Nb this northbridge - * - */ -typedef AP_MAIL_INFO F_RETRIEVE_MAILBOX ( - IN UINT8 Node, - IN NORTHBRIDGE *Nb - ); -/// Reference to a method. -typedef F_RETRIEVE_MAILBOX *PF_RETRIEVE_MAILBOX; - -/** - * Implement the hardware method of doing Socket Naming, by accessing this northbridge's Socket Id register. - * - * @HtNbInstances - * - * @param[in] Node The node for which we want the socket id. - * @param[in] TempNode The temporary node id route where the node can be accessed. - * @param[in] Nb Our Northbridge. - * - * @return The Socket Id - */ -typedef UINT8 F_GET_SOCKET ( - IN UINT8 Node, - IN UINT8 TempNode, - IN NORTHBRIDGE *Nb - ); - -/// Reference to a method. -typedef F_GET_SOCKET *PF_GET_SOCKET; - -/** - * Get the enabled Compute Units. - * - * Processors which don't support compute units return zero. - * - * @HtNbInstances - * - * @param[in] Node The node for which we want the socket id. - * @param[in] Nb Our Northbridge. - * - * @return The Socket Id - */ -typedef UINT8 F_GET_ENABLED_COMPUTE_UNITS ( - IN UINT8 Node, - IN NORTHBRIDGE *Nb - ); - -/// Reference to a method. -typedef F_GET_ENABLED_COMPUTE_UNITS *PF_GET_ENABLED_COMPUTE_UNITS; - -/** - * Get the dual core Compute Units. - * - * Processors which don't support compute units return zero. - * - * @HtNbInstances - * - * @param[in] Node The node for which we want the socket id. - * @param[in] Nb Our Northbridge. - * - * @return The Socket Id - */ -typedef UINT8 F_GET_DUALCORE_COMPUTE_UNITS ( - IN UINT8 Node, - IN NORTHBRIDGE *Nb - ); - -/// Reference to a method. -typedef F_GET_DUALCORE_COMPUTE_UNITS *PF_GET_DUALCORE_COMPUTE_UNITS; - -/** - * Return the Link to the Southbridge - * - * @HtNbInstances - * - * @param[in] Nb this northbridge - * - * @return the Link to the southbridge - */ -typedef UINT8 F_READ_SB_LINK ( - IN NORTHBRIDGE *Nb - ); -/// Reference to a method. -typedef F_READ_SB_LINK *PF_READ_SB_LINK; - -/** - * Verify that the Link is non-coherent, connected, and ready - * - * @HtNbInstances - * - * @param[in] Node the Node that will be examined - * @param[in] Link the Link on that Node to examine - * @param[in] Nb this northbridge - * - * @retval TRUE The Link is non-coherent. - * @retval FALSE The Link has some other status - */ -typedef BOOLEAN F_VERIFY_LINK_IS_NON_COHERENT ( - IN UINT8 Node, - IN UINT8 Link, - IN NORTHBRIDGE *Nb - ); -/// Reference to a method. -typedef F_VERIFY_LINK_IS_NON_COHERENT *PF_VERIFY_LINK_IS_NON_COHERENT; - -/** - * Enable config access to a non-coherent chain for the given bus range. - * - * @HtNbInstances - * - * @param[in] ConfigMapIndex the map entry to set - * @param[in] SecBus The secondary bus number to use - * @param[in] SubBus The subordinate bus number to use - * @param[in] TargetNode The Node that shall be the recipient of the traffic - * @param[in] TargetLink The Link that shall be the recipient of the traffic - * @param[in] State our global state - * @param[in] Nb this northbridge - */ -typedef VOID F_SET_CONFIG_ADDR_MAP ( - IN UINT8 ConfigMapIndex, - IN UINT8 SecBus, - IN UINT8 SubBus, - IN UINT8 TargetNode, - IN UINT8 TargetLink, - IN STATE_DATA *State, - IN NORTHBRIDGE *Nb - ); -/// Reference to a method. -typedef F_SET_CONFIG_ADDR_MAP *PF_SET_CONFIG_ADDR_MAP; - -/** - * Northbridge specific Frequency limit. - * - * @HtNbInstances - * - * Return a mask that eliminates HT frequencies that cannot be used due to a slow - * northbridge frequency. - * - * @param[in] Node Result could (later) be for a specific Node - * @param[in] Interface Access to non-HT support functions. - * @param[in] PlatformConfig Platform profile/build option config structure. - * @param[in] Nb this northbridge - * - * @return Frequency mask - */ -typedef UINT32 F_NORTH_BRIDGE_FREQ_MASK ( - IN UINT8 Node, - IN HT_INTERFACE *Interface, - IN PLATFORM_CONFIGURATION *PlatformConfig, - IN NORTHBRIDGE *Nb - ); -/// Reference to a method. -typedef F_NORTH_BRIDGE_FREQ_MASK *PF_NORTH_BRIDGE_FREQ_MASK; - -/** - * Get Link features into system data structure. - * - * @HtNbInstances - * - * @param[in,out] ThisPort The PortList structure entry for this link's port - * @param[in] Interface Access to non-HT support functions. - * @param[in] PlatformConfig Platform profile/build option config structure. - * @param[in] Nb this northbridge - */ -typedef VOID F_GATHER_LINK_FEATURES ( - IN OUT PORT_DESCRIPTOR *ThisPort, - IN HT_INTERFACE *Interface, - IN PLATFORM_CONFIGURATION *PlatformConfig, - IN NORTHBRIDGE *Nb - ); -/// Reference to a method. -typedef F_GATHER_LINK_FEATURES *PF_GATHER_LINK_FEATURES; - -/** - * Change the hardware state for all Links according to the now optimized data in the - * port list data structure. - * - * @HtNbInstances - * - * @param[in] Node the node on which to regang a link - * @param[in] Link the sublink 0 of the sublink pair to regang - * @param[in] Nb this northbridge - */ -typedef VOID F_SET_LINK_REGANG ( - IN UINT8 Node, - IN UINT8 Link, - IN NORTHBRIDGE *Nb - ); -/// Reference to a method. -typedef F_SET_LINK_REGANG *PF_SET_LINK_REGANG; - -/** - * Change the hardware state for all Links according to the now optimized data in the - * port list data structure. - * - * @HtNbInstances - * - * @param[in] Node the node on which to set frequency for a link - * @param[in] Link the link to set frequency - * @param[in] Frequency the frequency to set - * @param[in] Nb this northbridge - */ -typedef VOID F_SET_LINK_FREQUENCY ( - IN UINT8 Node, - IN UINT8 Link, - IN UINT8 Frequency, - IN NORTHBRIDGE *Nb - ); -/// Reference to a method. -typedef F_SET_LINK_FREQUENCY *PF_SET_LINK_FREQUENCY; - -/** - * Set the link's Unit Id Clumping enable. - * - * @HtNbInstances - * - * This applies to the host root of a non-coherent chain. - * - * @param[in] Node the node on which to set frequency for a link - * @param[in] Link the link to set frequency - * @param[in] ClumpingEnables the unit id clumping enables to set - * @param[in] Nb this northbridge - */ -typedef VOID F_SET_LINK_UNITID_CLUMPING ( - IN UINT8 Node, - IN UINT8 Link, - IN UINT32 ClumpingEnables, - IN NORTHBRIDGE *Nb - ); -/// Reference to a method. -typedef F_SET_LINK_UNITID_CLUMPING *PF_SET_LINK_UNITID_CLUMPING; - -/** - * Set the traffic distribution register for the Links provided. - * - * @HtNbInstances - * - * @param[in] Links01 coherent Links from Node 0 to 1 - * @param[in] Links10 coherent Links from Node 1 to 0 - * @param[in] Nb this northbridge - */ -typedef VOID F_WRITE_TRAFFIC_DISTRIBUTION ( - IN UINT32 Links01, - IN UINT32 Links10, - IN NORTHBRIDGE *Nb - ); -/// Reference to a method. -typedef F_WRITE_TRAFFIC_DISTRIBUTION *PF_WRITE_TRAFFIC_DISTRIBUTION; - -/** - * Set the traffic distribution register for the Links provided. - * - * @HtNbInstances - * - * @param[in] NodeA Source Node from Node A To Node B and DstNode from Node A To Node B - * @param[in] NodeB Source Node from Node B To Node A and DstNode from Node A To Node B - * @param[in] VictimedLinkFromNodeAToNodeB Victimed Link from Node A To Node B - * @param[in] VictimedLinkFromNodeBToNodeA Victimed Link from Node B To Node A - * @param[in] Nb this northbridge - */ -typedef VOID F_WRITE_VICTIM_DISTRIBUTION ( - IN UINT8 NodeA, - IN UINT8 NodeB, - IN UINT32 VictimedLinkFromNodeAToNodeB, - IN UINT32 VictimedLinkFromNodeBToNodeA, - IN NORTHBRIDGE *Nb - ); -/// Reference to a method. -typedef F_WRITE_VICTIM_DISTRIBUTION *PF_WRITE_VICTIM_DISTRIBUTION; - -/** - * Write a link pair to the link pair distribution and fixups. - * - * @HtNbInstances - * - * @param[in] Node Set the pair on this node - * @param[in] ConnectedNode The Node to which this link pair directly connects. - * @param[in] Pair Using this pair set in the register - * @param[in] Asymmetric True if different widths - * @param[in] MasterLink Set this as the master link and in the route - * @param[in] AlternateLink Set this as the alternate link - * @param[in] Nb this northbridge - * - */ -typedef VOID F_WRITE_LINK_PAIR_DISTRIBUTION ( - IN UINT8 Node, - IN UINT8 ConnectedNode, - IN UINT8 Pair, - IN BOOLEAN Asymmetric, - IN UINT8 MasterLink, - IN UINT8 AlternateLink, - IN NORTHBRIDGE *Nb - ); -/// Pointer to method WriteLinkPairDistribution -typedef F_WRITE_LINK_PAIR_DISTRIBUTION *PF_WRITE_LINK_PAIR_DISTRIBUTION; - -/** - * Family specific tunings. - * - * @HtNbInstances - * - * Buffer tunings are inherently northbridge specific. Check for specific configs - * which require adjustments and apply any standard workarounds to this Node. - * - * @param[in] Node the Node to tune - * @param[in] State global state - * @param[in] Nb this northbridge - */ -typedef VOID F_BUFFER_OPTIMIZATIONS ( - IN UINT8 Node, - IN STATE_DATA *State, - IN NORTHBRIDGE *Nb - ); -/// Reference to a method. -typedef F_BUFFER_OPTIMIZATIONS *PF_BUFFER_OPTIMIZATIONS; - -/** - * Return the number of cores (1 based count) on Node. - * - * @HtNbInstances - * - * @param[in] Node the Node that will be examined - * @param[in] Nb this northbridge - * - * @return the number of cores - */ -typedef UINT8 F_GET_NUM_CORES_ON_NODE ( - IN UINT8 Node, - IN NORTHBRIDGE *Nb - ); -/// Reference to a method. -typedef F_GET_NUM_CORES_ON_NODE *PF_GET_NUM_CORES_ON_NODE; - -/** - * Write the total number of cores and Nodes to the Node - * - * @HtNbInstances - * - * @param[in] Node the Node that will be examined - * @param[in] TotalNodes the total number of Nodes - * @param[in] TotalCores the total number of cores - * @param[in] Nb this northbridge - */ -typedef VOID F_SET_TOTAL_NODES_AND_CORES ( - IN UINT8 Node, - IN UINT8 TotalNodes, - IN UINT8 TotalCores, - IN NORTHBRIDGE *Nb - ); -/// Reference to a method. -typedef F_SET_TOTAL_NODES_AND_CORES *PF_SET_TOTAL_NODES_AND_CORES; - -/** - * Get the Count of Nodes in the system. - * - * @HtNbInstances - * - * @param[in] Nb This Northbridge. - * - * @return The Count (1 based) of Nodes in the system. - */ -typedef UINT8 F_GET_NODE_COUNT ( - IN NORTHBRIDGE *Nb - ); - -/// Reference to a method. -typedef F_GET_NODE_COUNT *PF_GET_NODE_COUNT; - -/** - * Limit coherent config accesses to cpus as indicated by Nodecnt. - * - * @HtNbInstances - * - * @param[in] Node the Node that will be examined - * @param[in] Nb this northbridge - */ -typedef VOID F_LIMIT_NODES ( - IN UINT8 Node, - IN NORTHBRIDGE *Nb - ); -/// Reference to a method. -typedef F_LIMIT_NODES *PF_LIMIT_NODES; - -/** - * Return the LinkFailed status AFTER an attempt is made to clear the bit. - * - * @HtNbInstances - * - * @param[in] Node the Node that will be examined - * @param[in] Link the Link on that Node to examine - * @param[in] State access to call back routine - * @param[in] Nb this northbridge - * - * @retval TRUE the Link is not connected or has hard error - * @retval FALSE the Link is connected - */ -typedef BOOLEAN F_READ_TRUE_LINK_FAIL_STATUS ( - IN UINT8 Node, - IN UINT8 Link, - IN STATE_DATA *State, - IN NORTHBRIDGE *Nb - ); -/// Reference to a method. -typedef F_READ_TRUE_LINK_FAIL_STATUS *PF_READ_TRUE_LINK_FAIL_STATUS; - -/** - * Get the next link for iterating over the links on a node in the correct order. - * - * @HtNbInstances - * - * @param[in] Node The node on which to iterate links. - * @param[in,out] Link IN: the current iteration context, OUT: the next link. - * @param[in] Nb This Northbridge, access to config pointer. - * - * @retval LinkIteratorEnd There is no next link (Link is back to BEGIN). - * @retval LinkIteratorExternal The next Link is an external link. - * @retval LinkIteratorInternal The next Link is an internal link. - */ -typedef LINK_ITERATOR_STATUS F_GET_NEXT_LINK ( - IN UINT8 Node, - IN OUT UINT8 *Link, - IN NORTHBRIDGE *Nb - ); -/// Pointer to method GetNextLink -typedef F_GET_NEXT_LINK *PF_GET_NEXT_LINK; - -/** - * Get the Package Link number, given the node and real link number. - * - * @HtNbInstances - * - * @param[in] Node the node which has this link - * @param[in] Link the link on that node - * @param[in] Nb this northbridge - * - * @return the Package Link - * - */ -typedef UINT8 F_GET_PACKAGE_LINK ( - IN UINT8 Node, - IN UINT8 Link, - IN NORTHBRIDGE *Nb - ); -/// Reference to a method -typedef F_GET_PACKAGE_LINK *PF_GET_PACKAGE_LINK; - -/** - * Return the HT Host capability base PCI config address for a Link. - * - * @HtNbInstances - * - * @param[in] Node the Node this Link is on - * @param[in] Link the Link - * @param[in] Nb this northbridge - * - * @return the pci config address - */ -typedef PCI_ADDR F_MAKE_LINK_BASE ( - IN UINT8 Node, - IN UINT8 Link, - IN NORTHBRIDGE *Nb - ); -/// Reference to a method. -typedef F_MAKE_LINK_BASE *PF_MAKE_LINK_BASE; - -/** - * Make a compatibility key. - * - * @HtNbInstances - * - * @param[in] Node the Node - * @param[in] Nb this northbridge - * - * @return the key - */ -typedef UINT64 F_MAKE_KEY ( - IN UINT8 Node, - IN NORTHBRIDGE *Nb - ); -/// Reference to a method. -typedef F_MAKE_KEY *PF_MAKE_KEY; - -/** - * The northbridge interface. - * - * Abstract the hardware implementation of the processor northbridge. Feature code does - * not need to be tailored to specific families. Also, more than a single family (or - * model in some cases) can be supported at once. Multiple family support can be for - * mixed revisions or for incompatible revisions where only one is used at a time. - * - * The northbridge object contains both HT component public and northbridge private - * members. These sets are grouped together. Within each group, members are grouped - * according to the function area they support. - * - */ -struct _NORTHBRIDGE { // See forward declaration in HtFeats.h - /* Public data, clients of northbridge can access */ - UINT8 MaxLinks; /**< The maximum number of Links implemented by the northbridge */ - - /* Public Interfaces for northbridge clients, coherent init*/ - PF_WRITE_ROUTING_TABLE WriteRoutingTable; /**< Method: Write a Temporary route for discovery */ - PF_WRITE_NODEID WriteNodeID; /**< Method: Assign a Node ID*/ - PF_READ_DEFAULT_LINK ReadDefaultLink; /**< Method: Which link are we connected to on a remote node? */ - PF_ENABLE_ROUTING_TABLES EnableRoutingTables; /**< Method: Make the routing table active */ - PF_DISABLE_ROUTING_TABLES DisableRoutingTables; /**< Method: Put a node back in discoverable state (deflnk) */ - PF_VERIFY_LINK_IS_COHERENT VerifyLinkIsCoherent; /**< Method: is a link connected and coherent? */ - PF_READ_TOKEN ReadToken; /**< Method: Read the enumeration token from a node */ - PF_WRITE_TOKEN WriteToken; /**< Method: Assign an enumeration token to a node */ - PF_WRITE_FULL_ROUTING_TABLE WriteFullRoutingTable; /**< Method: Set a complete routing table entry on a node */ - PF_IS_ILLEGAL_TYPE_MIX IsIllegalTypeMix; /**< Method: Is this node compatible with the system */ - PF_IS_EXCEEDED_CAPABLE IsExceededCapable; /**< Method: Is this node capable of working in this system */ - PF_STOP_LINK StopLink; /**< Method: stop a link which must be unused */ - PF_HANDLE_SPECIAL_LINK_CASE HandleSpecialLinkCase; /**< Method: Fix broken configuration designs */ - PF_HANDLE_SPECIAL_NODE_CASE HandleSpecialNodeCase; /**< Method: Fix broken configuration designs */ - - /* Public Interfaces for northbridge clients, noncoherent init */ - PF_READ_SB_LINK ReadSouthbridgeLink; /**< Method: Which link goes to the southbridge? */ - PF_VERIFY_LINK_IS_NON_COHERENT VerifyLinkIsNonCoherent; /**< Method: is a link connected and non-coherent? */ - PF_SET_CONFIG_ADDR_MAP SetConfigAddrMap; /**< Method: Add a non-coherent chain to the PCI Config Bus Address Map */ - - /* Public Interfaces for northbridge clients, Optimization */ - PF_NORTH_BRIDGE_FREQ_MASK NorthBridgeFreqMask; /**< Method: Check for frequency limits other than HT */ - PF_GATHER_LINK_FEATURES GatherLinkFeatures; /**< Method: Get frequency and link features */ - PF_SET_LINK_REGANG SetLinkRegang; /**< Method: Set a Link to regang */ - PF_SET_LINK_FREQUENCY SetLinkFrequency; /**< Method: Set the link Frequency */ - PF_SET_LINK_UNITID_CLUMPING SetLinkUnitIdClumping; /**< Method: Set the link's Unit Id Clumping register */ - - /* Public Interfaces for northbridge clients, System and performance Tuning. */ - PF_WRITE_TRAFFIC_DISTRIBUTION WriteTrafficDistribution; /**< Method: traffic distribution setting */ - PF_WRITE_LINK_PAIR_DISTRIBUTION WriteLinkPairDistribution; /**< Method: Link Pair setting and fix up */ - PF_WRITE_VICTIM_DISTRIBUTION WriteVictimDistribution; /**< Method: victim distribution setting */ - PF_BUFFER_OPTIMIZATIONS BufferOptimizations; /**< Method: system tunings which can not be - * done using register table */ - - /* Public Interfaces for northbridge clients, utility routines */ - PF_GET_NUM_CORES_ON_NODE GetNumCoresOnNode; /**< Method: Count cores */ - PF_SET_TOTAL_NODES_AND_CORES SetTotalNodesAndCores; /**< Method: Set Node and Core counts */ - PF_GET_NODE_COUNT GetNodeCount; /**< Method: Get the Count (1 based) of Nodes in the system. */ - PF_LIMIT_NODES LimitNodes; /**< Method: Set the Limit Config Space feature */ - PF_READ_TRUE_LINK_FAIL_STATUS ReadTrueLinkFailStatus; /**< Method: Get Fault status and connectivity of a link */ - PF_GET_NEXT_LINK GetNextLink; /**< Method: Iterate over a node's Internal, then External links. */ - PF_GET_PACKAGE_LINK GetPackageLink; /**< Method: the package link corresponding to a node's link */ - PF_MAKE_LINK_BASE MakeLinkBase; /**< Method: Provide the PCI Config Base register offset of a CPU link */ - PF_GET_MODULE_INFO GetModuleInfo; /**< Method: Get Module Type and internal Module number */ - PF_POST_MAILBOX PostMailbox; /**< Method: Post info to the mailbox register */ - PF_RETRIEVE_MAILBOX RetrieveMailbox; /**< Method: Retrieve info from the mailbox register */ - PF_GET_SOCKET GetSocket; /**< Method: Get a node's Socket, using the hardware naming method. */ - PF_GET_ENABLED_COMPUTE_UNITS GetEnabledComputeUnits; /**< Method: Get the Enabled Compute Units */ - PF_GET_DUALCORE_COMPUTE_UNITS GetDualCoreComputeUnits; /**< Method: Get which Compute Units have two cores. */ - - /* Private Data for northbridge implementation use only */ - UINT32 SelfRouteRequestMask; /**< Bit pattern for route request to self in routing table register */ - UINT32 SelfRouteResponseMask; /**< Bit pattern for route response to self in routing table register */ - UINT8 BroadcastSelfBit; /**< Bit offset of broadcast self bit in routing table register */ - BOOLEAN IsOrderBSPCoresByNode; /**< This processor orders Cores by Node id on the BSP, if TRUE. */ - BOOLEAN IsOrderCoresByModule; /**< Processors other than the BSP order Cores by Module, if TRUE. */ - UINT64 CompatibleKey; /**< Used for checking compatibility of northbridges in the system */ - PACKAGE_HTLINK_MAP PackageLinkMap; /**< Tell GetPackageLink() how to assign link names */ - UINT32 CoreFrequency; /**< Cache the northbridge core frequency, so repeated interface calls are avoided. - * A value of zero, means no value yet. */ - IGNORE_LINK *DefaultIgnoreLinkList; /**< After processing the user interface ignore link, process this list. */ - - /* Private Interfaces for northbridge implementation. */ - PF_MAKE_KEY MakeKey; /**< Method: make the compatibility key for this node */ - - /** Config Pointer, opaque handle for passing to lib */ - VOID *ConfigHandle; -}; - -/*---------------------------------------------------------------------------- - * FUNCTIONS PROTOTYPE - * - *---------------------------------------------------------------------------- - */ -/** - * Make a compatibility key. - * - */ -UINT64 -MakeKey ( - IN UINT8 Node, - IN NORTHBRIDGE *Nb - ); - -VOID -NewNorthBridge ( - IN UINT8 Node, - IN STATE_DATA *State, - OUT NORTHBRIDGE *Nb - ); - -#endif /* _HT_NB_H_ */ diff --git a/src/vendorcode/amd/agesa/f12/Proc/HT/htNbCommonHardware.h b/src/vendorcode/amd/agesa/f12/Proc/HT/htNbCommonHardware.h deleted file mode 100644 index 24acf8ff55..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/HT/htNbCommonHardware.h +++ /dev/null @@ -1,122 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * Northbridge hardware definitions for Family 10h. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: HyperTransport - * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $ - * - */ -/* -***************************************************************************** -* -* Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* *************************************************************************** -* -*/ -#ifndef _HT_NB_HARDWARE_FAM10_H_ -#define _HT_NB_HARDWARE_FAM10_H_ - -/* - *---------------------------------------------------------------------------- - * MODULES USED - * - *---------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------- - * DEFINITIONS AND MACROS - * - *---------------------------------------------------------------------------- - */ - -/* CPU Northbridge Functions */ -#define CPU_HTNB_FUNC_00 0 -#define CPU_HTNB_FUNC_04 4 -#define CPU_ADDR_FUNC_01 1 -#define CPU_NB_FUNC_03 3 -#define CPU_NB_FUNC_05 5 - -/* Function 0 registers */ -#define REG_ROUTE0_0X40 0x40 -#define REG_ROUTE1_0X44 0x44 -#define REG_NODE_ID_0X60 0x60 -#define REG_UNIT_ID_0X64 0x64 -#define REG_LINK_TRANS_CONTROL_0X68 0x68 -#define REG_LINK_INIT_CONTROL_0X6C 0x6C -#define REG_HT_CAP_BASE_0X80 0x80 -#define REG_HT_LINK_CLUMPING0_0X110 0x110 -#define REG_HT_LINK_RETRY0_0X130 0x130 -#define REG_HT_EXTENDED_NODE_ID_F0X160 0x160 -#define HTREG_NODE_CPUCNT_4_0 0x1F -#define HTREG_EXTNODE_CPUCNT_7_5 0xE0 -#define REG_HT_TRAFFIC_DIST_0X164 0x164 -#define REG_LINK_GLOBAL_EXT_CONTROL_0x16C 0x16C -#define REG_HT_LINK_EXT_CONTROL0_0X170 0x170 -#define REG_HT_LINK_INITIALIZATION_0X1A0 0x1A0 -#define PAIR_SELECT_OFFSET 8 -#define REG_HT_LINK_PAIR_DIST_0X1E0 0x1E0 - -/* Function 1 registers */ -#define REG_ADDR_CONFIG_MAP0_1XE0 0xE0 -#define CPU_ADDR_NUM_CONFIG_MAPS 4 - -/* Function 3 registers */ -#define REG_NB_SRI_XBAR_BUF_3X70 0x70 -#define REG_NB_MCT_XBAR_BUF_3X78 0x78 -#define REG_NB_FIFOPTR_3XDC 0xDC -#define REG_NB_CAPABILITY_3XE8 0xE8 -#define REG_NB_CPUID_3XFC 0xFC -#define REG_NB_LINK_XCS_TOKEN0_3X148 0x148 -#define REG_NB_MCA_LINK_THRESHOLD_3X168 0x168 -#define REG_NB_MCA_L3_THRESHOLD_3X170 0x170 -#define REG_NB_DOWNCORE_3X190 0x190 -#define REG_NB_SBI_CONTROL_3X1E4 0x1E4 - -/* Function 4 registers */ - -/* Function 5 registers */ -#define REG_NB_COMPUTE_UNIT_5X80 0x80 -#define REG_NB_CAPABILITY_2_5X84 0x84 - - -/*---------------------------------------------------------------------------- - * TYPEDEFS AND STRUCTURES - * - *---------------------------------------------------------------------------- - */ - - -/*---------------------------------------------------------------------------- - * PROTOTYPES OF LOCAL FUNCTIONS - * - *---------------------------------------------------------------------------- - */ - -#endif /* _HT_NB_HARDWARE_FAM10_H_ */ diff --git a/src/vendorcode/amd/agesa/f12/Proc/HT/htNotify.c b/src/vendorcode/amd/agesa/f12/Proc/HT/htNotify.c deleted file mode 100644 index 696f3f6184..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/HT/htNotify.c +++ /dev/null @@ -1,669 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * Code for detailed notification of events and status. - * - * Routines for logging and reporting details and summary status. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: HyperTransport - * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $ - * - */ -/* - ***************************************************************************** - * - * Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * *************************************************************************** - * - */ - -/* - *---------------------------------------------------------------------------- - * MODULES USED - * - *---------------------------------------------------------------------------- - */ - - - -#include "AGESA.h" -#include "amdlib.h" -#include "Ids.h" -#include "Topology.h" -#include "htFeat.h" -#include "htNotify.h" -#include "GeneralServices.h" -#include "Filecode.h" -CODE_GROUP (G1_PEICC) -RDATA_GROUP (G1_PEICC) - -#define FILECODE PROC_HT_HTNOTIFY_FILECODE -/*---------------------------------------------------------------------------- - * DEFINITIONS AND MACROS - * - *---------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------- - * EXPORTED FUNCTIONS - * - *---------------------------------------------------------------------------- - */ - -/*----------------------------------------------------------------------------------------*/ -/** - * Log an event. - * - * Errors, events, faults, warnings, and useful information are provided by - * calling this routine as often as necessary, once for each notification. - * @sa AGESA.h for class, and event definitions. - * @sa htNotify.h for event data definitions. - * - * @param[in] EvtClass What level event is this - * @param[in] Event A unique ID of this event - * @param[in] EventData useful data associated with the event. - * @param[in] State the log area and remaining free space - */ -VOID -STATIC -setEventNotify ( - IN AGESA_STATUS EvtClass, - IN UINT32 Event, - IN CONST UINT8 *EventData, - IN STATE_DATA *State - ) -{ - UINT32 DataParam[NUMBER_OF_EVENT_DATA_PARAMS]; - - // Remember the highest event class notified, that becomes our return code. - if (State->MaxEventClass < EvtClass) { - State->MaxEventClass = EvtClass; - } - - // Copy the event data to the log data - LibAmdMemCopy ( - DataParam, - (VOID *)EventData, - (sizeof(UINT32) * NUMBER_OF_EVENT_DATA_PARAMS), - State->ConfigHandle - ); - - // Log the event - PutEventLog ( - EvtClass, - Event, - DataParam[0], - DataParam[1], - DataParam[2], - DataParam[3], - State->ConfigHandle - ); -} - -/*----------------------------------------------------------------------------------------*/ -/** - * For event HT_EVENT_HW_SYNCFLOOD - * - * @param[in] Node The node on which the fault is reported - * @param[in] Link The link from that node - * @param[in] State our State - * - */ -VOID -NotifyAlertHwSyncFlood ( - IN UINT8 Node, - IN UINT8 Link, - IN STATE_DATA *State - ) -{ - HT_EVENT_DATA_HW_SYNCFLOOD Evt; - // Zero out the event data - LibAmdMemFill ( - &Evt, - 0, - (sizeof(UINT32) * NUMBER_OF_EVENT_DATA_PARAMS), - State->ConfigHandle - ); - - IDS_HDT_CONSOLE (HT_TRACE, "Sync Flood on Node %d Link %d.\n", Node, Link); - Evt.Node = Node; - Evt.Link = Link; - setEventNotify (AGESA_ALERT, - HT_EVENT_HW_SYNCFLOOD, - (UINT8 *)&Evt, State); -} - -/*----------------------------------------------------------------------------------------*/ -/** - * For event HT_EVENT_HW_HTCRC - * - * @param[in] Node The node on which the error is reported - * @param[in] Link The link from that node - * @param[in] LaneMask The lanes which had CRC - * @param[in] State our State - * - */ -VOID -NotifyAlertHwHtCrc ( - IN UINT8 Node, - IN UINT8 Link, - IN UINT8 LaneMask, - IN STATE_DATA *State - ) -{ - HT_EVENT_DATA_HW_HT_CRC Evt; - // Zero out the event data - LibAmdMemFill ( - &Evt, - 0, - (sizeof(UINT32) * NUMBER_OF_EVENT_DATA_PARAMS), - State->ConfigHandle - ); - - IDS_HDT_CONSOLE (HT_TRACE, "CRC Error on Node %d Link %d lanes %x.\n", Node, Link, LaneMask); - Evt.Node = Node; - Evt.Link = Link; - Evt.LaneMask = LaneMask; - setEventNotify (AGESA_ALERT, - HT_EVENT_HW_HTCRC, - (UINT8 *)&Evt, State); -} - -/*----------------------------------------------------------------------------------------*/ -/** - * For event HT_EVENT_NCOH_BUS_MAX_EXCEED - * - * @param[in] Node The node on which the chain is located - * @param[in] Link The link from that node - * @param[in] Bus The bus number to assign - * @param[in] State our State - * - */ -VOID -NotifyErrorNcohBusMaxExceed ( - IN UINT8 Node, - IN UINT8 Link, - IN UINT8 Bus, - IN STATE_DATA *State - ) -{ - HT_EVENT_DATA_NCOH_BUS_MAX_EXCEED Evt; - // Zero out the event data - LibAmdMemFill ( - &Evt, - 0, - (sizeof(UINT32) * NUMBER_OF_EVENT_DATA_PARAMS), - State->ConfigHandle - ); - - Evt.Node = Node; - Evt.Link = Link; - Evt.Bus = Bus; - setEventNotify (AGESA_ERROR, - HT_EVENT_NCOH_BUS_MAX_EXCEED, - (UINT8 *)&Evt, State); -} - -/*----------------------------------------------------------------------------------------*/ -/** - * For event HT_EVENT_NCOH_CFG_MAP_EXCEED - * - * @param[in] Node The node on which the chain is located - * @param[in] Link The link from that node - * @param[in] State our State - * - */ -VOID -NotifyErrorNcohCfgMapExceed ( - IN UINT8 Node, - IN UINT8 Link, - IN STATE_DATA *State - ) -{ - HT_EVENT_DATA_NCOH_CFG_MAP_EXCEED Evt; - // Zero out the event data - LibAmdMemFill ( - &Evt, - 0, - (sizeof(UINT32) * NUMBER_OF_EVENT_DATA_PARAMS), - State->ConfigHandle - ); - - Evt.Node = Node; - Evt.Link = Link; - setEventNotify (AGESA_ERROR, - HT_EVENT_NCOH_CFG_MAP_EXCEED, - (UINT8 *)&Evt, State); -} - -/*----------------------------------------------------------------------------------------*/ -/** - * For event HT_EVENT_NCOH_BUID_EXCEED - * - * @param[in] Node The node on which the chain is located - * @param[in] Link The link from that node - * @param[in] Depth Position on chain - * @param[in] Id The Id which was attempted to assigned - * @param[in] Units The number of units in this device - * @param[in] State our State - * - */ -VOID -NotifyErrorNcohBuidExceed ( - IN UINT8 Node, - IN UINT8 Link, - IN UINT8 Depth, - IN UINT8 Id, - IN UINT8 Units, - IN STATE_DATA *State - ) -{ - HT_EVENT_DATA_NCOH_BUID_EXCEED Evt; - // Zero out the event data - LibAmdMemFill ( - &Evt, - 0, - (sizeof(UINT32) * NUMBER_OF_EVENT_DATA_PARAMS), - State->ConfigHandle - ); - - Evt.Node = Node; - Evt.Link = Link; - Evt.Depth = Depth; - Evt.CurrentBuid = Id; - Evt.UnitCount = Units; - setEventNotify (AGESA_ERROR, - HT_EVENT_NCOH_BUID_EXCEED, - (UINT8 *)&Evt, State); -} - -/*----------------------------------------------------------------------------------------*/ -/** - * For event HT_EVENT_NCOH_DEVICE_FAILED - * - * @param[in] Node The node on which the chain is located - * @param[in] Link The link from that node - * @param[in] Depth Position on chain - * @param[in] Id The Id which was attempted to assigned - * @param[in] State our State - * - */ -VOID -NotifyErrorNcohDeviceFailed ( - IN UINT8 Node, - IN UINT8 Link, - IN UINT8 Depth, - IN UINT8 Id, - IN STATE_DATA *State - ) -{ - HT_EVENT_DATA_NCOH_DEVICE_FAILED Evt; - // Zero out the event data - LibAmdMemFill ( - &Evt, - 0, - (sizeof(UINT32) * NUMBER_OF_EVENT_DATA_PARAMS), - State->ConfigHandle - ); - - Evt.Node = Node; - Evt.Link = Link; - Evt.Depth = Depth; - Evt.AttemptedBuid = Id; - setEventNotify (AGESA_ERROR, - HT_EVENT_NCOH_DEVICE_FAILED, - (UINT8 *)&Evt, State); -} - -/*----------------------------------------------------------------------------------------*/ -/** - * For event HT_EVENT_NCOH_AUTO_DEPTH - * - * @param[in] Node The node on which the chain is located - * @param[in] Link The link from that node - * @param[in] Depth Position on chain - * @param[in] State our State - * - */ -VOID -NotifyInfoNcohAutoDepth ( - IN UINT8 Node, - IN UINT8 Link, - IN UINT8 Depth, - IN STATE_DATA *State - ) -{ - HT_EVENT_DATA_NCOH_AUTO_DEPTH Evt; - // Zero out the event data - LibAmdMemFill ( - &Evt, - 0, - (sizeof(UINT32) * NUMBER_OF_EVENT_DATA_PARAMS), - State->ConfigHandle - ); - - Evt.Node = Node; - Evt.Link = Link; - Evt.Depth = Depth; - setEventNotify (AGESA_SUCCESS, - HT_EVENT_NCOH_AUTO_DEPTH, - (UINT8 *)&Evt, State); -} - -/*----------------------------------------------------------------------------------------*/ -/** - * For event HT_EVENT_OPT_REQUIRED_CAP_RETRY - * - * @param[in] Node The node on which the chain is located - * @param[in] Link The link from that node - * @param[in] Depth Position on chain - * @param[in] State our State - * - */ -VOID -NotifyWarningOptRequiredCapRetry ( - IN UINT8 Node, - IN UINT8 Link, - IN UINT8 Depth, - IN STATE_DATA *State - ) -{ - HT_EVENT_DATA_OPT_REQUIRED_CAP Evt; - // Zero out the event data - LibAmdMemFill ( - &Evt, - 0, - (sizeof(UINT32) * NUMBER_OF_EVENT_DATA_PARAMS), - State->ConfigHandle - ); - - Evt.Node = Node; - Evt.Link = Link; - Evt.Depth = Depth; - setEventNotify (AGESA_WARNING, - HT_EVENT_OPT_REQUIRED_CAP_RETRY, - (UINT8 *)&Evt, State); -} - -/*----------------------------------------------------------------------------------------*/ -/** - * For event HT_EVENT_OPT_REQUIRED_CAP_GEN3 - * - * @param[in] Node The node on which the chain is located - * @param[in] Link The link from that node - * @param[in] Depth Position on chain - * @param[in] State our State - * - */ -VOID -NotifyWarningOptRequiredCapGen3 ( - IN UINT8 Node, - IN UINT8 Link, - IN UINT8 Depth, - IN STATE_DATA *State - ) -{ - HT_EVENT_DATA_OPT_REQUIRED_CAP Evt; - // Zero out the event data - LibAmdMemFill ( - &Evt, - 0, - (sizeof(UINT32) * NUMBER_OF_EVENT_DATA_PARAMS), - State->ConfigHandle - ); - - Evt.Node = Node; - Evt.Link = Link; - Evt.Depth = Depth; - setEventNotify (AGESA_WARNING, - HT_EVENT_OPT_REQUIRED_CAP_GEN3, - (UINT8 *)&Evt, State); -} - -/*----------------------------------------------------------------------------------------*/ -/** - * For event HT_EVENT_OPT_UNUSED_LINKS - * - * @param[in] NodeA One of the nodes connected - * @param[in] NodeB The other connected node - * @param[in] LinkA its unusable link - * @param[in] LinkB its unusable link - * @param[in] State our State - * - */ -VOID -NotifyWarningOptUnusedLinks ( - IN UINT32 NodeA, - IN UINT32 LinkA, - IN UINT32 NodeB, - IN UINT32 LinkB, - IN STATE_DATA *State - ) -{ - HT_EVENT_DATA_OPT_UNUSED_LINKS Evt; - // Zero out the event data - LibAmdMemFill ( - &Evt, - 0, - (sizeof(UINT32) * NUMBER_OF_EVENT_DATA_PARAMS), - State->ConfigHandle - ); - - Evt.NodeA = NodeA; - Evt.LinkA = LinkA; - Evt.NodeB = NodeB; - Evt.LinkB = LinkB; - setEventNotify (AGESA_WARNING, - HT_EVENT_OPT_UNUSED_LINKS, - (UINT8 *)&Evt, State); -} - - -/*----------------------------------------------------------------------------------------*/ -/** - * For event HT_EVENT_OPT_LINK_PAIR_EXCEED - * - * @param[in] NodeA One of the nodes connected - * @param[in] NodeB The other connected node - * @param[in] MasterLink its unusable Masterlink - * @param[in] AltLink its unusable Alternate link - * @param[in] State our State - * - */ -VOID -NotifyWarningOptLinkPairExceed ( - IN UINT32 NodeA, - IN UINT32 NodeB, - IN UINT32 MasterLink, - IN UINT32 AltLink, - IN STATE_DATA *State - ) -{ - HT_EVENT_DATA_OPT_LINK_PAIR_EXCEED Evt; - // Zero out the event data - LibAmdMemFill ( - &Evt, - 0, - (sizeof(UINT32) * NUMBER_OF_EVENT_DATA_PARAMS), - State->ConfigHandle - ); - - Evt.NodeA = NodeA; - Evt.MasterLink = MasterLink; - Evt.NodeB = NodeB; - Evt.AltLink = AltLink; - setEventNotify (AGESA_WARNING, - HT_EVENT_OPT_LINK_PAIR_EXCEED, - (UINT8 *)&Evt, State); -} - - -/*----------------------------------------------------------------------------------------*/ -/** - * For event HT_EVENT_COH_NO_TOPOLOGY - * - * @param[in] Nodes The total number of nodes found so far - * @param[in] State our State - * - */ -VOID -NotifyErrorCohNoTopology ( - IN UINT8 Nodes, - IN STATE_DATA *State - ) -{ - HT_EVENT_DATA_COH_NO_TOPOLOGY Evt; - // Zero out the event data - LibAmdMemFill ( - &Evt, - 0, - (sizeof(UINT32) * NUMBER_OF_EVENT_DATA_PARAMS), - State->ConfigHandle - ); - - IDS_HDT_CONSOLE (HT_TRACE, "No Topology Matched system with %d nodes found.\n", Nodes); - Evt.TotalNodes = Nodes; - setEventNotify (AGESA_ERROR, - HT_EVENT_COH_NO_TOPOLOGY, - (UINT8 *)&Evt, State); -} - -/*----------------------------------------------------------------------------------------*/ -/** - * For event HT_EVENT_COH_PROCESSOR_TYPE_MIX - * - * @param[in] Node The node from which a new node was discovered - * @param[in] Link The link from that node - * @param[in] Nodes The total number of nodes found so far - * @param[in] State our State - * - */ -VOID -NotifyFatalCohProcessorTypeMix ( - IN UINT8 Node, - IN UINT8 Link, - IN UINT8 Nodes, - IN STATE_DATA *State - ) -{ - HT_EVENT_DATA_COH_PROCESSOR_TYPE_MIX Evt; - // Zero out the event data - LibAmdMemFill ( - &Evt, - 0, - (sizeof(UINT32) * NUMBER_OF_EVENT_DATA_PARAMS), - State->ConfigHandle - ); - - IDS_HDT_CONSOLE (HT_TRACE, "Illegal Processor Type Mix.\n"); - Evt.Node = Node; - Evt.Link = Link; - Evt.TotalNodes = Nodes; - setEventNotify (AGESA_CRITICAL, - HT_EVENT_COH_PROCESSOR_TYPE_MIX, - (UINT8 *)&Evt, State); -} - -/*----------------------------------------------------------------------------------------*/ -/** - * For event HT_EVENT_COH_NODE_DISCOVERED - * - * @param[in] Node Node from which a new node was discovered - * @param[in] Link The link to that new node - * @param[in] NewNode The new node's id - * @param[in] TempRoute Temporarily, during discovery, the new node is accessed at this id. - * @param[in] State our State - * - */ -VOID -NotifyInfoCohNodeDiscovered ( - IN UINT8 Node, - IN UINT8 Link, - IN UINT8 NewNode, - IN UINT8 TempRoute, - IN STATE_DATA *State - ) -{ - HT_EVENT_DATA_COH_NODE_DISCOVERED Evt; - // Zero out the event data - LibAmdMemFill ( - &Evt, - 0, - (sizeof(UINT32) * NUMBER_OF_EVENT_DATA_PARAMS), - State->ConfigHandle - ); - - IDS_HDT_CONSOLE (HT_TRACE, "Adding Node %d.\n", NewNode); - Evt.Node = Node; - Evt.Link = Link; - Evt.NewNode = NewNode; - Evt.TempRoute = TempRoute; - setEventNotify (AGESA_SUCCESS, - HT_EVENT_COH_NODE_DISCOVERED, - (UINT8 *)&Evt, State); -} - -/*----------------------------------------------------------------------------------------*/ -/** - * For event HT_EVENT_COH_MPCAP_MISMATCH - * - * @param[in] Node The node from which a new node was discovered - * @param[in] Link The link from that node - * @param[in] Cap The aggregate system MP Capability - * @param[in] Nodes The total number of nodes found so far - * @param[in] State our State - * - */ -VOID -NotifyFatalCohMpCapMismatch ( - IN UINT8 Node, - IN UINT8 Link, - IN UINT8 Cap, - IN UINT8 Nodes, - IN STATE_DATA *State - ) -{ - HT_EVENT_DATA_COH_MP_CAP_MISMATCH Evt; - // Zero out the event data - LibAmdMemFill ( - &Evt, - 0, - (sizeof(UINT32) * NUMBER_OF_EVENT_DATA_PARAMS), - State->ConfigHandle - ); - - IDS_HDT_CONSOLE (HT_TRACE, "Mp Capability Mismatch.\n"); - Evt.Node = Node; - Evt.Link = Link; - Evt.SysMpCap = Cap; - Evt.TotalNodes = Nodes; - setEventNotify (AGESA_CRITICAL, - HT_EVENT_COH_MPCAP_MISMATCH, - (UINT8 *)&Evt, State); -} diff --git a/src/vendorcode/amd/agesa/f12/Proc/HT/htNotify.h b/src/vendorcode/amd/agesa/f12/Proc/HT/htNotify.h deleted file mode 100644 index c7c1ba4079..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/HT/htNotify.h +++ /dev/null @@ -1,297 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * HT Notify interface. - * - * This file provides internal interface to event and status - * notification. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: HyperTransport - * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $ - * - */ -/* -***************************************************************************** -* -* Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* *************************************************************************** -* -*/ - -#ifndef _HT_NOTIFY_H_ -#define _HT_NOTIFY_H_ - -/*----------------------------------------------------------------------------------------*/ -/* Event specific event data definitions. - * All structures must be 4 UINT32's in size, no more, no less. - */ - -/// For event ::HT_EVENT_HW_SYNCFLOOD -typedef struct { - UINT32 Node; ///< The Node on which observed - UINT32 Link; ///< The Link on that Node which reported synch flood - UINT32 Reserved1; ///< Reserved. - UINT32 Reserved2; ///< Reserved. -} HT_EVENT_DATA_HW_SYNCFLOOD; - -/// For event ::HT_EVENT_HW_HTCRC -typedef struct { - UINT32 Node; ///< The Node on which event is observed - UINT32 Link; ///< The Link on that Node which reported CRC error - UINT32 LaneMask; ///< The CRC lane mask for the Link - UINT32 Reserved1; ///< Reserved. -} HT_EVENT_DATA_HW_HT_CRC; - -/// For event ::HT_EVENT_NCOH_BUS_MAX_EXCEED -typedef struct { - UINT32 Node; ///< the Node with this non-coherent chain - UINT32 Link; ///< the Link on that Node to this chain - UINT32 Bus; ///< the current bus number - UINT32 Reserved1; ///< Reserved. -} HT_EVENT_DATA_NCOH_BUS_MAX_EXCEED; - -/// For event ::HT_EVENT_NCOH_CFG_MAP_EXCEED -typedef struct { - UINT32 Node; ///< the Node with this non-coherent chain - UINT32 Link; ///< the Link on that Node to this chain - UINT32 Reserved1; ///< Reserved. - UINT32 Reserved2; ///< Reserved. -} HT_EVENT_DATA_NCOH_CFG_MAP_EXCEED; - -/// For event ::HT_EVENT_NCOH_BUID_EXCEED -typedef struct { - UINT32 Node; ///< the Node with this non-coherent chain - UINT32 Link; ///< the Link on that Node to this chain - UINT32 Depth; ///< the position on the chain, zero is CPU host - UINT16 CurrentBuid; ///< the current available BUID - UINT16 UnitCount; ///< the number of ids which would be consumed by this device -} HT_EVENT_DATA_NCOH_BUID_EXCEED; - -/// For event ::HT_EVENT_NCOH_DEVICE_FAILED -typedef struct { - UINT32 Node; ///< the Node with this non-coherent chain - UINT32 Link; ///< the Link on that Node to this chain - UINT32 Depth; ///< the position on the chain, zero is CPU host - UINT32 AttemptedBuid; ///< the BUID we tried to assign to that device -} HT_EVENT_DATA_NCOH_DEVICE_FAILED; - -/// For event ::HT_EVENT_NCOH_AUTO_DEPTH -typedef struct { - UINT32 Node; ///< the Node with this non-coherent chain - UINT32 Link; ///< the Link on that Node to this chain - UINT32 Depth; ///< the position on the chain of the last device, zero is CPU host - UINT32 Reserved1; ///< Reserved. -} HT_EVENT_DATA_NCOH_AUTO_DEPTH; - -/// For event ::HT_EVENT_OPT_REQUIRED_CAP_RETRY, -/// ::HT_EVENT_OPT_REQUIRED_CAP_GEN3. -typedef struct { - UINT32 Node; ///< the Node with this non-coherent chain - UINT32 Link; ///< the Link on that Node to this chain - UINT32 Depth; ///< the position on the chain, zero is CPU host - UINT32 Reserved1; ///< Reserved. -} HT_EVENT_DATA_OPT_REQUIRED_CAP; - -/// For event ::HT_EVENT_OPT_UNUSED_LINKS -typedef struct { - UINT32 NodeA; ///< One of the nodes connected - UINT32 LinkA; ///< its unusable link - UINT32 NodeB; ///< The other connected node - UINT32 LinkB; ///< its unusable link -} HT_EVENT_DATA_OPT_UNUSED_LINKS; - -/// For event ::HT_EVENT_OPT_LINK_PAIR_EXCEED -typedef struct { - UINT32 NodeA; ///< One of the nodes connected - UINT32 NodeB; ///< The other connected node - UINT32 MasterLink; ///< NodeA's unusable Master link - UINT32 AltLink; ///< NodeA's unusable Alternatelink -} HT_EVENT_DATA_OPT_LINK_PAIR_EXCEED; - -/// For event ::HT_EVENT_COH_NO_TOPOLOGY. -/// There is no routing for this system's topology. -typedef struct { - UINT32 TotalNodes; ///< the number of Nodes in the unmatched topology - UINT32 Reserved1; ///< Reserved. - UINT32 Reserved2; ///< Reserved. - UINT32 Reserved3; ///< Reserved. -} HT_EVENT_DATA_COH_NO_TOPOLOGY; - -/// For event ::HT_EVENT_COH_PROCESSOR_TYPE_MIX -typedef struct { - UINT32 Node; ///< the Node from which the incompatible family was found - UINT32 Link; ///< the Link to the incompatible Node - UINT32 TotalNodes; ///< the number of Nodes found at that point - UINT32 Reserved1; ///< Reserved. -} HT_EVENT_DATA_COH_PROCESSOR_TYPE_MIX; - -/// For event ::HT_EVENT_COH_NODE_DISCOVERED -typedef struct { - UINT32 Node; ///< the Node from which the new Node was found - UINT32 Link; ///< the Link to the new Node - UINT32 NewNode; ///< the Node id of the newly discovered Node - UINT32 TempRoute; ///< the new Node is temporarily at this id -} HT_EVENT_DATA_COH_NODE_DISCOVERED; - -/// For event ::HT_EVENT_COH_MPCAP_MISMATCH -typedef struct { - UINT32 Node; ///< the Node from which condition was observed - UINT32 Link; ///< the Link on the current Node - UINT32 SysMpCap; ///< the current aggregate system capability (the minimum found so far) - UINT32 TotalNodes; ///< the number of Nodes found, before this was observed -} HT_EVENT_DATA_COH_MP_CAP_MISMATCH; - -/*----------------------------------------------------------------------------------------*/ -/* Event specific Notify functions. - */ - -VOID -NotifyAlertHwSyncFlood ( - IN UINT8 Node, - IN UINT8 Link, - IN STATE_DATA *State - ); - -VOID -NotifyAlertHwHtCrc ( - IN UINT8 Node, - IN UINT8 Link, - IN UINT8 LaneMask, - IN STATE_DATA *State - ); - -VOID -NotifyErrorNcohBusMaxExceed ( - IN UINT8 Node, - IN UINT8 Link, - IN UINT8 Bus, - IN STATE_DATA *State - ); - -VOID -NotifyErrorNcohCfgMapExceed ( - IN UINT8 Node, - IN UINT8 Link, - IN STATE_DATA *State - ); - -VOID -NotifyErrorNcohBuidExceed ( - IN UINT8 Node, - IN UINT8 Link, - IN UINT8 Depth, - IN UINT8 Id, - IN UINT8 Units, - IN STATE_DATA *State - ); - -VOID -NotifyErrorNcohDeviceFailed ( - IN UINT8 Node, - IN UINT8 Link, - IN UINT8 Depth, - IN UINT8 Id, - IN STATE_DATA *State - ); - -VOID -NotifyInfoNcohAutoDepth ( - IN UINT8 Node, - IN UINT8 Link, - IN UINT8 Depth, - IN STATE_DATA *State - ); - -VOID -NotifyWarningOptRequiredCapRetry ( - IN UINT8 Node, - IN UINT8 Link, - IN UINT8 Depth, - IN STATE_DATA *State - ); - -VOID -NotifyWarningOptRequiredCapGen3 ( - IN UINT8 Node, - IN UINT8 Link, - IN UINT8 Depth, - IN STATE_DATA *State - ); - -VOID -NotifyWarningOptUnusedLinks ( - IN UINT32 NodeA, - IN UINT32 LinkA, - IN UINT32 NodeB, - IN UINT32 LinkB, - IN STATE_DATA *State - ); - -VOID -NotifyWarningOptLinkPairExceed ( - IN UINT32 NodeA, - IN UINT32 NodeB, - IN UINT32 MasterLink, - IN UINT32 AltLink, - IN STATE_DATA *State - ); - -VOID -NotifyErrorCohNoTopology ( - IN UINT8 Nodes, - IN STATE_DATA *State - ); - -VOID -NotifyFatalCohProcessorTypeMix ( - IN UINT8 Node, - IN UINT8 Link, - IN UINT8 Nodes, - IN STATE_DATA *State - ); - -VOID -NotifyInfoCohNodeDiscovered ( - IN UINT8 Node, - IN UINT8 Link, - IN UINT8 NewNode, - IN UINT8 TempRoute, - IN STATE_DATA *State - ); - -VOID -NotifyFatalCohMpCapMismatch ( - IN UINT8 Node, - IN UINT8 Link, - IN UINT8 Cap, - IN UINT8 Nodes, - IN STATE_DATA *State - ); - -#endif /* _HT_NOTIFY_H_ */ diff --git a/src/vendorcode/amd/agesa/f12/Proc/HT/htPage.h b/src/vendorcode/amd/agesa/f12/Proc/HT/htPage.h deleted file mode 100644 index a45aa406d6..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/HT/htPage.h +++ /dev/null @@ -1,64 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * Create outline and references for HyperTransport Component mainpage documentation. - * - * Design guides, maintenance guides, and general documentation, are - * collected using this file onto the documentation mainpage. - * This file contains doxygen comment blocks, only. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: Documentation - * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $ - * - */ -/* - ****************************************************************************** - * - * Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - ****************************************************************************** - */ - -/** - * @page htmain HyperTransport Component Documentation - * - * Additional documentation for the HyperTransport component consists of - * - * - Member Cross References - * - @subpage instanceshtnb "HT Northbridge Method Instances" - * - Maintenance Guides: - * - @subpage htimplintf "HT Internal Interface Implementation Guide" - * - @subpage htimplfeat "HT Feature Implementation Guide" - * - @subpage htimplnb "HT Northbridge Implementation Guide" - * - add here >>> - * - Design Guides: - * - @subpage htgraphdesign "Graph Support Design" - * - @subpage physicalsockethowto "How to Create a Physical System Socket Map" - * - add here >>> - * - */ diff --git a/src/vendorcode/amd/agesa/f12/Proc/HT/htTopologies.h b/src/vendorcode/amd/agesa/f12/Proc/HT/htTopologies.h deleted file mode 100644 index 440eb6c935..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/HT/htTopologies.h +++ /dev/null @@ -1,71 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * Provide selection of available topologies. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: HyperTransport - * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $ - * - */ -/* -***************************************************************************** -* -* Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* *************************************************************************** -* -*/ -#ifndef _HT_TOPOLOGIES_H_ -#define _HT_TOPOLOGIES_H_ - -extern CONST UINT8 ROMDATA amdHtTopologySingleNode[]; -extern CONST UINT8 ROMDATA amdHtTopologyDualNode[]; -extern CONST UINT8 ROMDATA amdHtTopologyThreeLine[]; -extern CONST UINT8 ROMDATA amdHtTopologyTriangle[]; -extern CONST UINT8 ROMDATA amdHtTopologyFourLine[]; -extern CONST UINT8 ROMDATA amdHtTopologyFourStar[]; -extern CONST UINT8 ROMDATA amdHtTopologyFourDegenerate[]; -extern CONST UINT8 ROMDATA amdHtTopologyFourSquare[]; -extern CONST UINT8 ROMDATA amdHtTopologyFourKite[]; -extern CONST UINT8 ROMDATA amdHtTopologyFourFully[]; -extern CONST UINT8 ROMDATA amdHtTopologyFiveFully[]; -extern CONST UINT8 ROMDATA amdHtTopologyFiveTwistedLadder[]; -extern CONST UINT8 ROMDATA amdHtTopologySixFully[]; -extern CONST UINT8 ROMDATA amdHtTopologySixDoubloonLower[]; -extern CONST UINT8 ROMDATA amdHtTopologySixDoubloonUpper[]; -extern CONST UINT8 ROMDATA amdHtTopologySixTwistedLadder[]; -extern CONST UINT8 ROMDATA amdHtTopologySevenFully[]; -extern CONST UINT8 ROMDATA amdHtTopologySevenTwistedLadder[]; -extern CONST UINT8 ROMDATA amdHtTopologyEightFully[]; -extern CONST UINT8 ROMDATA amdHtTopologyEightDoubloon[]; -extern CONST UINT8 ROMDATA amdHtTopologyEightTwistedLadder[]; -extern CONST UINT8 ROMDATA amdHtTopologyEightStraightLadder[]; -extern CONST UINT8 ROMDATA amdHtTopologySixTwinTriangles[]; -extern CONST UINT8 ROMDATA amdHtTopologyEightTwinFullyFourWays[]; - -#endif // _HT_TOPOLOGIES_H_ diff --git a/src/vendorcode/amd/agesa/f12/Proc/IDS/IdsLib.h b/src/vendorcode/amd/agesa/f12/Proc/IDS/IdsLib.h deleted file mode 100644 index 3b55253c93..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/IDS/IdsLib.h +++ /dev/null @@ -1,125 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * AMD IDS Routines - * - * Contains AMD AGESA Integrated Debug Macros - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: IDS - * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $ - */ -/***************************************************************************** - * - * Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ***************************************************************************/ - -#ifndef _IDS_LIB_H_ -#define _IDS_LIB_H_ -#include "OptionsIds.h" -#include "cpuRegisters.h" -#include "cpuApicUtilities.h" -#include "Table.h" -///Specific time stamp performance analysis which need ids control support -#if IDSOPT_CONTROL_ENABLED == TRUE - #define PERF_SPEC_TS_ANALYSE(StdHeader) -#else - #define PERF_SPEC_TS_ANALYSE(StdHeader) -#endif - - -#define IDS_NV_READ_SKIP(NvValue, Nvid, IdsNvPtr, StdHeader) -#define IDS_GET_MASK32(HighBit, LowBit) - -#define IDS_MAX_MEM_ITEMS 80 ///< Maximum IDS Mem Table Size in Heap. - - -// TYPEDEFS, STRUCTURES, ENUMS -// - - -///Structure define for MSR register -typedef struct _REG_MSR { - UINT32 msraddr; ///< Address of MSR Register - UINT32 andmaskhi; ///< And Mask Bit63:32 - UINT32 andmasklo; ///< And Mask Bit31:0 - UINT32 ormaskhi; ///< Or Mask Bit63:32 - UINT32 ormasklo; ///< Or Mask Bit31:0 -} REG_MSR; - -typedef AGESA_STATUS (*PF_IDS_AP_TASK) (VOID *AptaskPara, AMD_CONFIG_PARAMS *StdHeader); - -///Structure define for IdsAgesaRunFcnOnApLate -typedef struct _IDSAPLATETASK { - PF_IDS_AP_TASK ApTask; ///< Point function which AP need to do - VOID *ApTaskPara; ///< Point to Ap function parameter1 -} IDSAPLATETASK; - -/// Data Structure defining IDS Data in HEAP -/// This data structure contains information that is stored in HEAP and will be -/// used in IDS backend function. It includes the size of memory to be allocated -/// for IDS, the relative offsets of the mapping table IDS setup options, the GRA -/// table and the register table to override mem setting. It also includes a base -/// address of IDS override image which will be used to control the behavior of -/// AGESA testpoint if this feature is enabled. -typedef struct { - BOOLEAN IgnoreIdsDefault; ///< Control ignore Default value of IDS NV list specified by IdsNvTableOffset - UINT64 IdsImageBase; ///< IDS Override Image Base Address - UINT32 IdsHeapMemSize; ///< IDS Total Memory Size in Heap - UINT32 IdsNvTableOffset; ///< Offset of IDS NV Table - UINT32 IdsMemTableOffset; ///< Offset of IDS Mem Table - UINT32 IdsExtendOffset; ///< Offset of Ids extend heap -} IDS_CONTROL_STRUCT; - - -/// Data Structure of Parameters for TestPoint_TSC. -typedef struct { - UINT8 TestPoint; ///< The TestPoint of TestPoint_TSC - UINT64 StartTsc; ///< The StartTimer of TestPoint_TSC -} TestPoint_TSC; - -/// Data Structure of Parameters for TP_Perf_STRUCT. -typedef struct { - UINT8 Index; ///< The Index of TP_Perf_STRUCT - UINT32 TscInMhz; ///< Tsc counter in 1 mhz - TestPoint_TSC TP[EndAgesaTps]; ///< The TP of TP_Perf_STRUCT -} TP_Perf_STRUCT; - - -///Bus speed Optimization -typedef enum { - IDS_POWER_POLICY_PERFORMANCE = 0, ///< Performance - IDS_POWER_POLICY_POWER = 1, ///< Power - IDS_POWER_POLICY_AUTO = 3, ///< Auto -} IDS_NV_AMDBUSSPEEDOPTIMIZATION; - -#define IDS_CPB_BOOST_DIS_IGNORE 0xFFFFFFFF - -#endif //_IDS_LIB_H_ - diff --git a/src/vendorcode/amd/agesa/f12/Proc/IDS/IdsPage.h b/src/vendorcode/amd/agesa/f12/Proc/IDS/IdsPage.h deleted file mode 100644 index 7b652e6478..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/IDS/IdsPage.h +++ /dev/null @@ -1,57 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * Create outline and references for Integrated Debug Support Component mainpage documentation. - * - * Design guides, maintenance guides, and general documentation, are - * collected using this file onto the documentation mainpage. - * This file contains doxygen comment blocks, only. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: Documentation - * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $ - * - */ -/* - ****************************************************************************** - * - * Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - ****************************************************************************** - */ - -/** - * @page idsmain Integrated Debug Support Component Documentation - * - * Additional documentation for the Integrated Debug Support component consists of - * - * - Maintenance Guides: - * - add here >>> - * - Design Guides: - * - add here >>> - * - */ diff --git a/src/vendorcode/amd/agesa/f12/Proc/Mem/Ardk/LN/Makefile.inc b/src/vendorcode/amd/agesa/f12/Proc/Mem/Ardk/LN/Makefile.inc deleted file mode 100644 index 809efdf2b1..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/Mem/Ardk/LN/Makefile.inc +++ /dev/null @@ -1,2 +0,0 @@ -libagesa-y += masln3.c -libagesa-y += mauln3.c diff --git a/src/vendorcode/amd/agesa/f12/Proc/Mem/Ardk/LN/masln3.c b/src/vendorcode/amd/agesa/f12/Proc/Mem/Ardk/LN/masln3.c deleted file mode 100644 index 590d8fc4d1..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/Mem/Ardk/LN/masln3.c +++ /dev/null @@ -1,288 +0,0 @@ -/* $NoKeywords:$ */ -/* - * @file - * - * masln3.c - * - * Platform specific settings for LN DDR3 SO-dimms - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: (Mem/Ardk) - * @e \$Revision: 47807 $ @e \$Date: 2011-03-01 01:53:18 +0800 (Tue, 01 Mar 2011) $ - * - **/ -/***************************************************************************** - * - * Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * *************************************************************************** - * - */ - -/* This file contains routine that add platform specific support AM3 */ - - -#include "AGESA.h" -#include "amdlib.h" -#include "mport.h" -#include "PlatformMemoryConfiguration.h" -#include "ma.h" -#include "mu.h" -#include "Ids.h" -#include "F12PackageType.h" -#include "cpuFamRegisters.h" -#include "Filecode.h" -CODE_GROUP (G2_PEI) -RDATA_GROUP (G2_PEI) - -#define FILECODE PROC_MEM_ARDK_LN_MASLN3_FILECODE -/*---------------------------------------------------------------------------- - * DEFINITIONS AND MACROS - * - *---------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------- - * TYPEDEFS AND STRUCTURES - * - *---------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------- - * PROTOTYPES OF LOCAL FUNCTIONS - * - *---------------------------------------------------------------------------- - */ - -/* - *----------------------------------------------------------------------------- - * EXPORTED FUNCTIONS - * - *----------------------------------------------------------------------------- - */ - -STATIC CONST UINT8 ROMDATA LnSDdr3CLKDis[] = {0xFF, 0xFF, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}; -STATIC CONST UINT8 ROMDATA LnSDdr3CLKDisFM1[] = {0xFF, 0xFF, 0xFF, 0xFF, 0x00, 0x00, 0x00, 0x00}; -STATIC CONST UINT8 ROMDATA LnSDdr3CKETri[] = {0x55, 0xAA}; -STATIC CONST UINT8 ROMDATA LnSDdr3ODTTri[] = {0x01, 0x02, 0x04, 0x08}; -STATIC CONST UINT8 ROMDATA LnSDdr3CSTri[] = {0x01, 0x02, 0x04, 0x08, 0x00, 0x00, 0x00, 0x00}; - -/* -----------------------------------------------------------------------------*/ -/** - * - * This is function sets the platform specific settings for LN DDR3 SO-dimms - * - * - * @param[in,out] *MemData Pointer to MEM_DATA_STRUCTURE - * @param[in] SocketID Socket number - * @param[in,out] *CurrentChannel Pointer to CH_DEF_STRUCT - * - * @return AGESA_SUCCESS - * @return CurrentChannel->MemClkDisMap Points this pointer to LN MemClkDis table - * @return CurrentChannel->ChipSelTriMap Points this pointer to LN CS table - * @return CurrentChannel->CKETriMap Points this pointer to LN ODT table - * @return CurrentChannel->ODTTriMap Points this pointer to LN CKE table - * @return CurrentChannel->DctEccDQSLike Indicates the bytes that should be averaged for ECC - * @return CurrentChannel->DctEccDQSScale Indicates the scale that should be used for Averaging ECC byte - * @return CurrentChannel->DctAddrTmg Address Command Timing Settings for specified channel - * @return CurrentChannel->DctOdcCtl Drive Strength settings for specified channel - * @return CurrentChannel->SlowMode Slow Mode - * - * - */ - -AGESA_STATUS -MemAGetPsCfgSLN3 ( - IN OUT MEM_DATA_STRUCT *MemData, - IN UINT8 SocketID, - IN OUT CH_DEF_STRUCT *CurrentChannel - ) -{ - STATIC CONST ADV_PSCFG_ENTRY PSCfg[] = { - {DDR800_FREQUENCY, ANY_, 0x00000000, 0x00002222, 1}, - {DDR800_FREQUENCY, ANY_, 0x00000039, 0x20222323, 2}, - {DDR1066_FREQUENCY, ANY_, 0x003D3D3D, 0x10002222, 1}, - {DDR1066_FREQUENCY, ANY_, 0x00000037, 0x30222323, 2}, - {DDR1333_FREQUENCY, ANY_, 0x003D3D3D, 0x20002222, 1}, - {DDR1333_FREQUENCY, ANY_, 0x00000035, 0x30222323, 2}, - {DDR1600_FREQUENCY, ANY_, 0x003C3C3C, 0x30112222, 1}, - {DDR1600_FREQUENCY, ANY_, 0x00000033, 0x30222323, 2}, - {DDR1866_FREQUENCY, ANY_, 0x00003C3C, 0x30112222, 1}, - {DDR1866_FREQUENCY, ANY_, 0x00000031, 0x30222323, 2}, - }; - // - // DIMM ODT Pattern - // - // Dimm Config , - // Fn2_F4 180, Fn2_F4 181, Fn2_F4 182, Fn2_F4 183, # Dimms to match - // - STATIC CONST ADV_PSCFG_ODT_ENTRY PSCfgDIMMsODT[] = { - {SR_DIMM0, \ - 0x00000000, 0x00000000, 0x00000001, 0x00000000, 1}, - {DR_DIMM0, \ - 0x00000000, 0x00000000, 0x00000201, 0x00000000, 1}, - {SR_DIMM1, \ - 0x00000000, 0x00000000, 0x00040000, 0x00000000, 1}, - {DR_DIMM1, \ - 0x00000000, 0x00000000, 0x08040000, 0x00000000, 1}, - {SR_DIMM0 + DR_DIMM0 + SR_DIMM1 + DR_DIMM1, \ - 0x01010404, 0x00000000, 0x09050605, 0x00000000, 2} - }; - - UINT16 i; - UINT16 j; - UINT8 Loads; - UINT8 Dimms; - UINT16 Speed; - UINT32 AddrTmgCTL; - UINT32 DctOdcCtl; - UINT32 PhyRODTCS; - UINT32 PhyWODTCS; - UINT8 PhyWLODT[4]; - BOOLEAN SlowMode; - UINT16 DIMMRankType; - UINT16 _DIMMRankType; - UINT8 DimmTpMatch; - UINT8 *DimmsPerChPtr; - UINT8 DimmsPerCH; - - ASSERT (MemData != 0); - ASSERT (CurrentChannel != 0); - - AddrTmgCTL = 0; - DctOdcCtl = 0; - PhyRODTCS = 0; - PhyWODTCS = 0; - PhyWLODT[0] = 0x0F; - PhyWLODT[1] = 0x0F; - PhyWLODT[2] = 0x0F; - PhyWLODT[3] = 0x0F; - - if ((CurrentChannel->MCTPtr->LogicalCpuid.Family & AMD_FAMILY_LN) == 0) { - return AGESA_UNSUPPORTED; - } - if (CurrentChannel->TechType != DDR3_TECHNOLOGY) { - return AGESA_UNSUPPORTED; - } - if (CurrentChannel->SODimmPresent != CurrentChannel->ChDimmValid) { - return AGESA_UNSUPPORTED; - } - - // Prepare inputs - DIMMRankType = MemAGetPsRankType (CurrentChannel); - Loads = CurrentChannel->Loads; - Dimms = CurrentChannel->Dimms; - Speed = CurrentChannel->DCTPtr->Timings.Speed; - SlowMode = TRUE; // 2T - DimmsPerChPtr = FindPSOverrideEntry (MemData->ParameterListPtr->PlatformMemoryConfiguration, PSO_MAX_DIMMS, SocketID, CurrentChannel->ChannelID); - if (DimmsPerChPtr != NULL) { - DimmsPerCH = *DimmsPerChPtr; - } else { - DimmsPerCH = 1; - } - - for (i = 0; i < GET_SIZE_OF (PSCfg); i++) { - if ((PSCfg[i].Dimms == ANY_) || (PSCfg[i].Dimms == Dimms)) { - if ((PSCfg[i].Speed == ANY_) || (PSCfg[i].Speed == Speed)) { - if ((PSCfg[i].Loads == ANY_) || (PSCfg[i].Loads >= Loads)) { - AddrTmgCTL = PSCfg[i].AddrTmg; - DctOdcCtl = PSCfg[i].Odc; - break; - } - } - } - } - ASSERT (i < GET_SIZE_OF (PSCfg)); - - // Exceptions - if (Dimms == 1) { - if (Speed != DDR1866_FREQUENCY) { - SlowMode = FALSE; - } - if (CurrentChannel->DimmDrPresent != 0) { - if (Speed == DDR1066_FREQUENCY) { - AddrTmgCTL = 0x00000000; - } else if (Speed == DDR1333_FREQUENCY) { - AddrTmgCTL = 0x00003D3D; - } else if (Speed == DDR1600_FREQUENCY) { - AddrTmgCTL = 0x00003C3C; - SlowMode = TRUE; - } - } - } - - // - // Programmable ODT pattern - // - for (i = 0; i < GET_SIZE_OF (PSCfgDIMMsODT); i++) { - if (Dimms != PSCfgDIMMsODT[i].Dimms) { - continue; - } - DimmTpMatch = 0; - _DIMMRankType = DIMMRankType & PSCfgDIMMsODT[i].DIMMRankType; - for (j = 0; j < MAX_DIMMS_PER_CHANNEL; j++) { - if ((_DIMMRankType & (UINT16) 0x0F << (j << 2)) != 0) { - DimmTpMatch++; - } - } - if (DimmTpMatch == PSCfgDIMMsODT[i].Dimms) { - PhyRODTCS = PSCfgDIMMsODT[i].PhyRODTCSLow; - PhyWODTCS = PSCfgDIMMsODT[i].PhyWODTCSLow; - break; - } - } - - // - // WL ODT - // - PhyWLODT[0] = PhyWLODT[2] = (UINT8) (PhyWODTCS & 0x0F); - PhyWLODT[1] = PhyWLODT[3] = (UINT8) ((PhyWODTCS >> 16) & 0x0F); - - if (LibAmdGetPackageType (&(MemData->StdHeader)) == PACKAGE_TYPE_FM1) { - CurrentChannel->MemClkDisMap = (UINT8 *) LnSDdr3CLKDisFM1; - } else { - CurrentChannel->MemClkDisMap = (UINT8 *) LnSDdr3CLKDis; - } - CurrentChannel->CKETriMap = (UINT8 *) LnSDdr3CKETri; - CurrentChannel->ODTTriMap = (UINT8 *) LnSDdr3ODTTri; - CurrentChannel->ChipSelTriMap = (UINT8 *) LnSDdr3CSTri; - - CurrentChannel->DctAddrTmg = AddrTmgCTL; - CurrentChannel->DctOdcCtl = DctOdcCtl; - CurrentChannel->PhyRODTCSLow = PhyRODTCS; - CurrentChannel->PhyWODTCSLow = PhyWODTCS; - for (i = 0; i < sizeof (CurrentChannel->PhyWLODT); i++) { - CurrentChannel->PhyWLODT[i] = PhyWLODT[i]; - } - CurrentChannel->SlowMode = SlowMode; - - if ((DimmsPerCH == 2) && (Speed >= DDR1333_FREQUENCY) && (Dimms == 1)) { - // Set Dqs and DQ drive strength to 1.0x for 1 dimm on 2 dimms per channel DDR3-1333 - CurrentChannel->DctOdcCtl |= 0x110000; - } - - return AGESA_SUCCESS; -} diff --git a/src/vendorcode/amd/agesa/f12/Proc/Mem/Ardk/LN/mauln3.c b/src/vendorcode/amd/agesa/f12/Proc/Mem/Ardk/LN/mauln3.c deleted file mode 100644 index 953bad26e4..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/Mem/Ardk/LN/mauln3.c +++ /dev/null @@ -1,269 +0,0 @@ -/* $NoKeywords:$ */ -/* - * @file - * - * mauln3.c - * - * Platform specific settings for LN DDR3 unbuffered dimms - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: (Mem/Ardk) - * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $ - * - **/ -/***************************************************************************** - * - * Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * *************************************************************************** - * - */ - -/* This file contains routine that add platform specific support AM3 */ - - -#include "AGESA.h" -#include "mport.h" -#include "PlatformMemoryConfiguration.h" -#include "ma.h" -#include "Ids.h" -#include "cpuFamRegisters.h" -#include "Filecode.h" -CODE_GROUP (G2_PEI) -RDATA_GROUP (G2_PEI) - -#define FILECODE PROC_MEM_ARDK_LN_MAULN3_FILECODE -/*---------------------------------------------------------------------------- - * DEFINITIONS AND MACROS - * - *---------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------- - * TYPEDEFS AND STRUCTURES - * - *---------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------- - * PROTOTYPES OF LOCAL FUNCTIONS - * - *---------------------------------------------------------------------------- - */ - -/* - *----------------------------------------------------------------------------- - * EXPORTED FUNCTIONS - * - *----------------------------------------------------------------------------- - */ - -STATIC CONST UINT8 ROMDATA LnUDdr3CLKDis[] = {0xFF, 0xFF, 0xFF, 0xFF, 0x00, 0x00, 0x00, 0x00}; -STATIC CONST UINT8 ROMDATA LnUDdr3CKETri[] = {0x55, 0xAA}; -STATIC CONST UINT8 ROMDATA LnUDdr3ODTTri[] = {0x01, 0x02, 0x04, 0x08}; -STATIC CONST UINT8 ROMDATA LnUDdr3CSTri[] = {0x01, 0x02, 0x04, 0x08, 0x00, 0x00, 0x00, 0x00}; - -/* -----------------------------------------------------------------------------*/ -/** - * - * This is function sets the platform specific settings for LN DDR3 Unbuffered dimms - * - * - * @param[in,out] *MemData Pointer to MEM_DATA_STRUCTURE - * @param[in] SocketID Socket number - * @param[in,out] *CurrentChannel Pointer to CH_DEF_STRUCT - * - * @return AGESA_SUCCESS - * @return CurrentChannel->MemClkDisMap Points this pointer to LN MemClkDis table - * @return CurrentChannel->ChipSelTriMap Points this pointer to LN CS table - * @return CurrentChannel->CKETriMap Points this pointer to LN ODT table - * @return CurrentChannel->ODTTriMap Points this pointer to LN CKE table - * @return CurrentChannel->DctEccDQSLike Indicates the bytes that should be averaged for ECC - * @return CurrentChannel->DctEccDQSScale Indicates the scale that should be used for Averaging ECC byte - * @return CurrentChannel->DctAddrTmg Address Command Timing Settings for specified channel - * @return CurrentChannel->DctOdcCtl Drive Strength settings for specified channel - * @return CurrentChannel->SlowMode Slow Mode - * - */ - -AGESA_STATUS -MemAGetPsCfgULN3 ( - IN OUT MEM_DATA_STRUCT *MemData, - IN UINT8 SocketID, - IN OUT CH_DEF_STRUCT *CurrentChannel - ) -{ - STATIC CONST ADV_PSCFG_ENTRY PSCfg[] = { - {DDR800_FREQUENCY, ANY_, 0x003B0000, 0x00112222, 1}, - {DDR800_FREQUENCY, ANY_, 0x00390039, 0x20222322, 2}, - {DDR1066_FREQUENCY, ANY_, 0x00380000, 0x10112222, 1}, - {DDR1066_FREQUENCY, ANY_, 0x00350037, 0x30222322, 2}, - {DDR1333_FREQUENCY, ANY_, 0x00360000, 0x20112222, 1}, - {DDR1333_FREQUENCY, ANY_, 0x00000035, 0x30222322, 2}, - {DDR1600_FREQUENCY, ANY_, 0x00000000, 0x30112222, 1}, - {DDR1600_FREQUENCY, ANY_, 0x00000033, 0x30222322, 2}, - {DDR1866_FREQUENCY, ANY_, 0x00000000, 0x30112222, 1}, - {DDR1866_FREQUENCY, ANY_, 0x00000031, 0x30222322, 2}, - }; - // - // DIMM ODT Pattern - // - // Dimm Config , - // Fn2_F4 180, Fn2_F4 181, Fn2_F4 182, Fn2_F4 183, # Dimms to match - // - STATIC CONST ADV_PSCFG_ODT_ENTRY PSCfgDIMMsODT[] = { - {SR_DIMM0, \ - 0x00000000, 0x00000000, 0x00000001, 0x00000000, 1}, - {DR_DIMM0, \ - 0x00000000, 0x00000000, 0x00000201, 0x00000000, 1}, - {SR_DIMM1, \ - 0x00000000, 0x00000000, 0x00040000, 0x00000000, 1}, - {DR_DIMM1, \ - 0x00000000, 0x00000000, 0x08040000, 0x00000000, 1}, - {SR_DIMM0 + DR_DIMM0 + SR_DIMM1 + DR_DIMM1, \ - 0x01010404, 0x00000000, 0x09050605, 0x00000000, 2} - }; - - UINT16 i; - UINT16 j; - UINT8 Loads; - UINT8 Dimms; - UINT16 Speed; - UINT16 DIMMRankType; - UINT16 _DIMMRankType; - UINT32 AddrTmgCTL; - UINT32 DctOdcCtl; - UINT32 PhyRODTCS; - UINT32 PhyWODTCS; - UINT8 PhyWLODT[4]; - BOOLEAN SlowMode; - UINT8 DimmTpMatch; - - ASSERT (MemData != 0); - ASSERT (CurrentChannel != 0); - - AddrTmgCTL = 0; - DctOdcCtl = 0; - PhyRODTCS = 0; - PhyWODTCS = 0; - PhyWLODT[0] = 0x0F; - PhyWLODT[1] = 0x0F; - PhyWLODT[2] = 0x0F; - PhyWLODT[3] = 0x0F; - - if ((CurrentChannel->MCTPtr->LogicalCpuid.Family & AMD_FAMILY_LN) == 0) { - return AGESA_UNSUPPORTED; - } - if (CurrentChannel->TechType != DDR3_TECHNOLOGY) { - return AGESA_UNSUPPORTED; - } - if ((CurrentChannel->RegDimmPresent != 0) || (CurrentChannel->SODimmPresent != 0)) { - return AGESA_UNSUPPORTED; - } - - // Prepare inputs - Loads = CurrentChannel->Loads; - Dimms = CurrentChannel->Dimms; - Speed = CurrentChannel->DCTPtr->Timings.Speed; - - DIMMRankType = MemAGetPsRankType (CurrentChannel); - - SlowMode = FALSE; // 1T - if ((Speed >= DDR1333_FREQUENCY) && (Dimms == 2)) { - SlowMode = TRUE; // 2T - } - - for (i = 0; i < GET_SIZE_OF (PSCfg); i++) { - if ((PSCfg[i].Dimms == ANY_) || (PSCfg[i].Dimms == Dimms)) { - if ((PSCfg[i].Speed == ANY_) || (PSCfg[i].Speed == Speed)) { - if ((PSCfg[i].Loads == ANY_) || (PSCfg[i].Loads >= Loads)) { - AddrTmgCTL = PSCfg[i].AddrTmg; - DctOdcCtl = PSCfg[i].Odc; - break; - } - } - } - } - ASSERT (i < GET_SIZE_OF (PSCfg)); - - // - // Overrides and/or exceptions - // - if (Dimms == 1) { - if (CurrentChannel->DimmDrPresent != 0) { - if (Speed >= DDR1600_FREQUENCY) { - SlowMode = TRUE; - } - } else { - AddrTmgCTL = 0x00000000; - } - } - - // - // Programmable ODT pattern - // - for (i = 0; i < GET_SIZE_OF (PSCfgDIMMsODT); i++) { - if (Dimms != PSCfgDIMMsODT[i].Dimms) { - continue; - } - DimmTpMatch = 0; - _DIMMRankType = DIMMRankType & PSCfgDIMMsODT[i].DIMMRankType; - for (j = 0; j < MAX_DIMMS_PER_CHANNEL; j++) { - if ((_DIMMRankType & (UINT16) 0x0F << (j << 2)) != 0) { - DimmTpMatch++; - } - } - if (DimmTpMatch == PSCfgDIMMsODT[i].Dimms) { - PhyRODTCS = PSCfgDIMMsODT[i].PhyRODTCSLow; - PhyWODTCS = PSCfgDIMMsODT[i].PhyWODTCSLow; - break; - } - } - - // - // WL ODT - // - PhyWLODT[0] = PhyWLODT[2] = (UINT8) (PhyWODTCS & 0x0F); - PhyWLODT[1] = PhyWLODT[3] = (UINT8) ((PhyWODTCS >> 16) & 0x0F); - - CurrentChannel->MemClkDisMap = (UINT8 *) LnUDdr3CLKDis; - CurrentChannel->CKETriMap = (UINT8 *) LnUDdr3CKETri; - CurrentChannel->ODTTriMap = (UINT8 *) LnUDdr3ODTTri; - CurrentChannel->ChipSelTriMap = (UINT8 *) LnUDdr3CSTri; - - CurrentChannel->DctEccDqsLike = 0x0403; - CurrentChannel->DctEccDqsScale = 0x70; - CurrentChannel->DctAddrTmg = AddrTmgCTL; - CurrentChannel->DctOdcCtl = DctOdcCtl; - CurrentChannel->PhyRODTCSLow = PhyRODTCS; - CurrentChannel->PhyWODTCSLow = PhyWODTCS; - for (i = 0; i < sizeof (CurrentChannel->PhyWLODT); i++) { - CurrentChannel->PhyWLODT[i] = PhyWLODT[i]; - } - CurrentChannel->SlowMode = SlowMode; - - return AGESA_SUCCESS; -} diff --git a/src/vendorcode/amd/agesa/f12/Proc/Mem/Ardk/Makefile.inc b/src/vendorcode/amd/agesa/f12/Proc/Mem/Ardk/Makefile.inc deleted file mode 100644 index 3b5087cbcb..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/Mem/Ardk/Makefile.inc +++ /dev/null @@ -1 +0,0 @@ -libagesa-y += ma.c diff --git a/src/vendorcode/amd/agesa/f12/Proc/Mem/Ardk/ma.c b/src/vendorcode/amd/agesa/f12/Proc/Mem/Ardk/ma.c deleted file mode 100644 index 18154d42d6..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/Mem/Ardk/ma.c +++ /dev/null @@ -1,139 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * ma.c - * - * Initializes ARDK Block - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: (Mem/Ardk) - * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $ - * - **/ -/***************************************************************************** -* -* Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* *************************************************************************** -* -*/ - -/* - *---------------------------------------------------------------------------- - * MODULES USED - * - *---------------------------------------------------------------------------- - */ - - -#include "AGESA.h" -#include "ma.h" -#include "Filecode.h" -CODE_GROUP (G2_PEI) -RDATA_GROUP (G2_PEI) - -#define FILECODE PROC_MEM_ARDK_MA_FILECODE -/*---------------------------------------------------------------------------- - * DEFINITIONS AND MACROS - * - *---------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------- - * TYPEDEFS AND STRUCTURES - * - *---------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------- - * PROTOTYPES OF LOCAL FUNCTIONS - * - *---------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------- - * EXPORTED FUNCTIONS - * - *---------------------------------------------------------------------------- - */ - -/* -----------------------------------------------------------------------------*/ -/** - * - * This is the default return function of the ARDK block. The function always - * returns AGESA_UNSUPPORTED - * - * @param[in,out] *MemData Pointer to MEM_DATA_STRUCTURE - * @param[in] SocketID Socket number - * @param[in] *CurrentChannel Pointer to CH_DEF_STRUCT - * - * @return AGESA_UNSUPPORTED AGESA status indicating that default is unsupported - * - */ - -AGESA_STATUS -MemAGetPsCfgDef ( - IN OUT MEM_DATA_STRUCT *MemData, - IN UINT8 SocketID, - IN OUT CH_DEF_STRUCT *CurrentChannel - ) -{ - return AGESA_UNSUPPORTED; -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * This function returns the rank type map of a channel. - * - * @param[in] *CurrentChannel Pointer to CH_DEF_STRUCT - * - * @return UINT16 - The map of rank type. - * - */ -UINT16 -MemAGetPsRankType ( - IN CH_DEF_STRUCT *CurrentChannel - ) -{ - UINT8 i; - UINT16 DIMMRankType; - - DIMMRankType = 0; - for (i = 0; i < MAX_DIMMS_PER_CHANNEL; i++) { - if ((CurrentChannel->DimmQrPresent & (UINT8) 1 << i) != 0) { - if (i < 2) { - DIMMRankType |= (UINT16) 4 << (i << 2); - } - } else if ((CurrentChannel->DimmDrPresent & (UINT8) 1 << i) != 0) { - DIMMRankType |= (UINT16) 2 << (i << 2); - } else if ((CurrentChannel->DimmSRPresent & (UINT8) 1 << i) != 0) { - DIMMRankType |= (UINT16) 1 << (i << 2); - } - } - return DIMMRankType; -} diff --git a/src/vendorcode/amd/agesa/f12/Proc/Mem/Feat/CHINTLV/Makefile.inc b/src/vendorcode/amd/agesa/f12/Proc/Mem/Feat/CHINTLV/Makefile.inc deleted file mode 100644 index 6599c4723d..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/Mem/Feat/CHINTLV/Makefile.inc +++ /dev/null @@ -1 +0,0 @@ -libagesa-y += mfchi.c diff --git a/src/vendorcode/amd/agesa/f12/Proc/Mem/Feat/CHINTLV/mfchi.c b/src/vendorcode/amd/agesa/f12/Proc/Mem/Feat/CHINTLV/mfchi.c deleted file mode 100644 index 8d70c4be78..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/Mem/Feat/CHINTLV/mfchi.c +++ /dev/null @@ -1,211 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * mfchi.c - * - * Feature Channel interleaving support - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: (Mem/Feat/Chintlv) - * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $ - * - **/ -/***************************************************************************** - * - * Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * *************************************************************************** - * - */ - - -/* - *---------------------------------------------------------------------------- - * MODULES USED - * - *---------------------------------------------------------------------------- - */ - - - -#include "AGESA.h" -#include "mm.h" -#include "mn.h" -#include "mfchi.h" -#include "Ids.h" -#include "GeneralServices.h" -#include "Filecode.h" -CODE_GROUP (G2_PEI) -RDATA_GROUP (G2_PEI) - -#define FILECODE PROC_MEM_FEAT_CHINTLV_MFCHI_FILECODE -/*---------------------------------------------------------------------------- - * DEFINITIONS AND MACROS - * - *---------------------------------------------------------------------------- - */ -#define _4GB_ (0x10000 >> 10) - -/*---------------------------------------------------------------------------- - * TYPEDEFS AND STRUCTURES - * - *---------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------- - * PROTOTYPES OF LOCAL FUNCTIONS - * - *---------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------- - * EXPORTED FUNCTIONS - * - *---------------------------------------------------------------------------- - */ - -/* -----------------------------------------------------------------------------*/ -/** - * - * MemFInterleaveChannels: - * - * Applies DIMM channel interleaving if enabled, if not ganged mode, and - * there are valid dimms in both channels. Called once per Node. - * - * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK - * - * @return TRUE - This feature is enabled. - * @return FALSE - This feature is not enabled. - */ - -BOOLEAN -MemFInterleaveChannels ( - IN OUT MEM_NB_BLOCK *NBPtr - ) -{ - UINT32 DramBase; - UINT32 DctSelBase; - UINT32 HoleSize; - UINT32 HoleBase; - UINT32 HoleOffset; - UINT32 Dct0Size; - UINT32 Dct1Size; - UINT32 SmallerDct; - UINT8 DctSelIntLvAddr; - UINT8 DctSelHi; - UINT8 DctSelHiRngEn; - UINT32 HoleValid; - - MEM_PARAMETER_STRUCT *RefPtr; - DIE_STRUCT *MCTPtr; - - ASSERT (NBPtr != NULL); - - RefPtr = NBPtr->RefPtr; - - DctSelIntLvAddr = NBPtr->DefDctSelIntLvAddr; - if (RefPtr->EnableChannelIntlv) { - HoleSize = 0; - HoleBase = 0; - if (RefPtr->GStatus[GsbSoftHole] || RefPtr->GStatus[GsbHWHole]) { - // HoleBase scaled from [47:16] to [47:26] - HoleBase = RefPtr->HoleBase >> 10; - HoleSize = _4GB_ - HoleBase; - } - - MCTPtr = NBPtr->MCTPtr; - - HoleValid = NBPtr->GetBitField (NBPtr, BFDramHoleValid); - if ((!MCTPtr->GangedMode) && - (MCTPtr->DctData[0].Timings.DctMemSize != 0) && - (MCTPtr->DctData[1].Timings.DctMemSize != 0)) { - // DramBase scaled [47:16] to [47:26] - DramBase = MCTPtr->NodeSysBase >> 10; - // Scale NodeSysLimit [47:16] to [47:26] - Dct1Size = (MCTPtr->NodeSysLimit + 1) >> 10; - Dct0Size = NBPtr->GetBitField (NBPtr, BFDctSelBaseOffset); - if ((Dct0Size >= _4GB_) && (DramBase < HoleBase)) { - Dct0Size -= HoleSize; - } - if ((Dct1Size >= _4GB_) && (DramBase < HoleBase)) { - Dct1Size -= HoleSize; - } - Dct1Size -= Dct0Size; - Dct0Size -= DramBase; - - // Select the bigger size DCT to put in DctSelHi - DctSelHiRngEn = 1; - DctSelHi = 0; - SmallerDct = Dct1Size; - if (Dct1Size == Dct0Size) { - SmallerDct = 0; - DctSelHiRngEn = 0; - } else if (Dct1Size > Dct0Size) { - SmallerDct = Dct0Size; - DctSelHi = 1; - } - - if (SmallerDct != 0) { - DctSelBase = (SmallerDct * 2) + DramBase; - } else { - DctSelBase = 0; - } - if ((DctSelBase >= HoleBase) && (DramBase < HoleBase)) { - DctSelBase += HoleSize; - } - IDS_OPTION_HOOK (IDS_CHANNEL_INTERLEAVE, &DctSelIntLvAddr, &(NBPtr->MemPtr->StdHeader)); - NBPtr->SetBitField (NBPtr, BFDctSelBaseAddr, DctSelBase >> 1); - NBPtr->SetBitField (NBPtr, BFDctSelHiRngEn, DctSelHiRngEn); - NBPtr->SetBitField (NBPtr, BFDctSelHi, DctSelHi); - NBPtr->SetBitField (NBPtr, BFDctSelIntLvAddr, DctSelIntLvAddr); - NBPtr->SetBitField (NBPtr, BFDctSelIntLvEn, 1); - - // DctSelBaseOffset = DctSelBaseAddr - Interleaved region - NBPtr->SetBitField (NBPtr, BFDctSelBaseOffset, DctSelBase - SmallerDct); - - // Adjust DramHoleOffset - if (HoleValid != 0) { - HoleOffset = DramBase; - if ((DctSelBase < HoleBase) && (DctSelBase != 0)) { - HoleOffset += (DctSelBase - DramBase) >> 1; - } - HoleOffset += HoleSize; - NBPtr->SetBitField (NBPtr, BFDramHoleOffset, HoleOffset << 3); - } - } else { - // - // Channel Interleaving is requested but cannot be enabled - // - PutEventLog (AGESA_WARNING, MEM_WARNING_CHANNEL_INTERLEAVING_NOT_ENABLED, NBPtr->Node, 0, 0, 0, &NBPtr->MemPtr->StdHeader); - SetMemError (AGESA_WARNING, MCTPtr); - } - - return TRUE; - } else { - return FALSE; - } -} diff --git a/src/vendorcode/amd/agesa/f12/Proc/Mem/Feat/CHINTLV/mfchi.h b/src/vendorcode/amd/agesa/f12/Proc/Mem/Feat/CHINTLV/mfchi.h deleted file mode 100644 index 75f516654a..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/Mem/Feat/CHINTLV/mfchi.h +++ /dev/null @@ -1,80 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * mfchi.h - * - * Feature channel interleaving - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: (Mem) - * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $ - * - **/ -/***************************************************************************** - * - * Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * *************************************************************************** - * - */ - - -#ifndef _MFCHI_H_ -#define _MFCHI_H_ - -/*---------------------------------------------------------------------------- - * Mixed (DEFINITIONS AND MACROS / TYPEDEFS, STRUCTURES, ENUMS) - * - *---------------------------------------------------------------------------- - */ - -/*----------------------------------------------------------------------------- - * DEFINITIONS AND MACROS - * - *----------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------- - * TYPEDEFS, STRUCTURES, ENUMS - * - *---------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------- - * FUNCTIONS PROTOTYPE - * - *---------------------------------------------------------------------------- - */ - -BOOLEAN -MemFInterleaveChannels ( - IN OUT MEM_NB_BLOCK *NBPtr - ); - -#endif /* _MFCHI_H_ */ - - diff --git a/src/vendorcode/amd/agesa/f12/Proc/Mem/Feat/CSINTLV/Makefile.inc b/src/vendorcode/amd/agesa/f12/Proc/Mem/Feat/CSINTLV/Makefile.inc deleted file mode 100644 index c7dc75b38c..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/Mem/Feat/CSINTLV/Makefile.inc +++ /dev/null @@ -1 +0,0 @@ -libagesa-y += mfcsi.c diff --git a/src/vendorcode/amd/agesa/f12/Proc/Mem/Feat/CSINTLV/mfcsi.c b/src/vendorcode/amd/agesa/f12/Proc/Mem/Feat/CSINTLV/mfcsi.c deleted file mode 100644 index 4bc794c666..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/Mem/Feat/CSINTLV/mfcsi.c +++ /dev/null @@ -1,352 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * mfcsi.c - * - * Feature bank interleaving support (AKA Chip Select Interleaving ) - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: (Mem/Feat/Csintlv) - * @e \$Revision: 49979 $ @e \$Date: 2011-03-31 12:08:42 +0800 (Thu, 31 Mar 2011) $ - * - **/ -/***************************************************************************** - * - * Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * *************************************************************************** - * - */ - - -/* This file contains functions for Chip Select interleaving */ - - - -#include "AGESA.h" -#include "amdlib.h" -#include "mm.h" -#include "mn.h" -#include "mt.h" -#include "mfcsi.h" -#include "Ids.h" -#include "GeneralServices.h" -#include "Filecode.h" -CODE_GROUP (G2_PEI) -RDATA_GROUP (G2_PEI) - -#define FILECODE PROC_MEM_FEAT_CSINTLV_MFCSI_FILECODE -/*---------------------------------------------------------------------------- - * DEFINITIONS AND MACROS - * - *---------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------- - * TYPEDEFS AND STRUCTURES - * - *---------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------- - * PROTOTYPES OF LOCAL FUNCTIONS - * - *---------------------------------------------------------------------------- - */ - -BOOLEAN -STATIC -MemFDctInterleaveBanks ( - IN OUT MEM_NB_BLOCK *NBPtr - ); - -VOID -STATIC -CsIntSwap ( - IN OUT UINT32 *BaseMaskRegPtr, - IN UINT8 EnChipSels, - IN UINT8 LoBit, - IN UINT8 HiBit - ); - -/* - *----------------------------------------------------------------------------- - * EXPORTED FUNCTIONS - * - *----------------------------------------------------------------------------- - */ -BOOLEAN -MemFUndoInterleaveBanks ( - IN OUT MEM_NB_BLOCK *NBPtr - ); - -/* -----------------------------------------------------------------------------*/ -/** - * - * - * This function Applies DIMM bank (chip-select) interleaving if enabled - * and if all criteria are met. Interleaves chip-selects on page boundaries. - * This function calls subfunctions that sets up CS interleaving on multiple Sockets - * - * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK - * - * @return TRUE - This feature is enabled. - * @return FALSE - This feature is not enabled. - */ - -BOOLEAN -MemFInterleaveBanks ( - IN OUT MEM_NB_BLOCK *NBPtr - ) -{ - UINT8 Dct; - BOOLEAN RetFlag; - - ASSERT (NBPtr != NULL); - - RetFlag = FALSE; - if (NBPtr->RefPtr->EnableBankIntlv) { - if (NBPtr->MCTPtr->NodeMemSize) { - for (Dct = 0; Dct < NBPtr->DctCount; Dct++) { - NBPtr->SwitchDCT (NBPtr, Dct); - RetFlag |= MemFDctInterleaveBanks (NBPtr); - } - } - } - return RetFlag; -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * - * This function checks if bank interleaving has been enabled or not. If yes, it will - * undo bank interleaving. Otherwise, it does nothing. - * - * - * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK - * - * @return TRUE - Bank interleaving has been enabled. - * @return FALSE - Bank interleaving has not been enabled. - */ - -BOOLEAN -MemFUndoInterleaveBanks ( - IN OUT MEM_NB_BLOCK *NBPtr - ) -{ - UINT8 Cs; - UINT8 Dct; - UINT32 CSMask; - BOOLEAN CSIntlvEnabled; - BOOLEAN RetFlag; - - ASSERT (NBPtr != NULL); - - RetFlag = FALSE; - - if (NBPtr->RefPtr->EnableBankIntlv) { - for (Dct = 0; Dct < NBPtr->DctCount; Dct++) { - NBPtr->SwitchDCT (NBPtr, Dct); - if (NBPtr->DCTPtr->Timings.DctMemSize) { - CSIntlvEnabled = FALSE; - for (Cs = 0; Cs < MAX_CS_PER_CHANNEL; Cs++) { - if ((NBPtr->GetBitField (NBPtr, BFCSBaseAddr0Reg + Cs) & 1) != 0) { - CSMask = NBPtr->GetBitField (NBPtr, BFCSMask0Reg + (Cs / 2)); - if (((CSMask >> 5) & 0x1FF) != 0x1FF) { - CSIntlvEnabled = TRUE; - break; - } - } - } - if (CSIntlvEnabled) { - MemFDctInterleaveBanks (NBPtr); - RetFlag = TRUE; - } - } - } - } - return RetFlag; -} - -/*---------------------------------------------------------------------------- - * LOCAL FUNCTIONS - * - *---------------------------------------------------------------------------- - */ - -/* -----------------------------------------------------------------------------*/ -/** - * - * - * This function Applies DIMM bank (chip-select) interleaving if enabled - * and if all criteria are met. Interleaves chip-selects on page boundaries. - * This function is run once per Socket - * - * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK - * - * @return TRUE - Register bits have been swapped. - * @return FALSE - Register bits have not been swapped. - * - */ - -BOOLEAN -STATIC -MemFDctInterleaveBanks ( - IN OUT MEM_NB_BLOCK *NBPtr - ) -{ - UINT8 Cs; - UINT8 EnChipSels; - UINT8 BankEncd; - UINT8 BankEncd0; - UINT8 i; - UINT8 j; - UINT32 BankAddrReg; - UINT32 BaseRegS0; - UINT32 BaseRegS1; - UINT32 MaskReg; - UINT8 Offset; - UINT8 Dct; - - ASSERT (NBPtr != NULL); - - Dct = NBPtr->Dct; - - // Check if CS interleaving can be enabled - EnChipSels = 0; - BankEncd0 = 0xFF; - Offset = 0; - for (Cs = 0; Cs < MAX_CS_PER_CHANNEL; Cs++) { - if ((NBPtr->GetBitField (NBPtr, BFCSBaseAddr0Reg + Cs) & 1) != 0) { - BankAddrReg = NBPtr->GetBitField (NBPtr, BFDramBankAddrReg); - BankEncd = (UINT8) ((BankAddrReg >> ((Cs / 2) * 4)) & 0xF); - if (BankEncd0 == 0xFF) { - BankEncd0 = BankEncd; - } else if (BankEncd0 != BankEncd) { - break; - } - EnChipSels++; - } - } - - // Swap Dram Base/Mask Addr to enable CS interleaving - if ((Cs == MAX_CS_PER_CHANNEL) && ((EnChipSels == 2) || (EnChipSels == 4) || (EnChipSels == 8))) { - NBPtr->TechPtr->GetCSIntLvAddr (BankEncd0, &i, &j); - // Family specific CS interleaving low address adjustment - NBPtr->FamilySpecificHook[AdjustCSIntLvLowAddr] (NBPtr, &i); - - if (NBPtr->MCTPtr->Status[Sb128bitmode]) { - i++; - j++; - } - - for (Cs = 0; Cs < MAX_CS_PER_CHANNEL; Cs += 2) { - // - // LRDIMMS - Add an offset to the bit positions specified based on D18F2x[6C:60]_dct[1:0][RankDef] as follows: - // RankDef=0xb: 0 RankDef=10b: 1 RankDef=11b: 2 - // Using RankMult information: Lo/HiBit <<= (Mult >> 1) - // - if (NBPtr->MCTPtr->Status[SbLrdimms]) { - Offset = ((NBPtr->ChannelPtr->LrDimmRankMult[Cs >> 1]) >> 1); - } - BaseRegS0 = NBPtr->GetBitField (NBPtr, BFCSBaseAddr0Reg + Cs); - BaseRegS1 = NBPtr->GetBitField (NBPtr, BFCSBaseAddr0Reg + Cs + 1); - if (((BaseRegS0 | BaseRegS1) & 1) != 0) { - // Swap Mask register bits - MaskReg = NBPtr->GetBitField (NBPtr, BFCSMask0Reg + (Cs / 2)); - CsIntSwap (&MaskReg, EnChipSels, (i + Offset), (j + Offset)); - NBPtr->SetBitField (NBPtr, BFCSMask0Reg + (Cs / 2), MaskReg); - - // Swap Base register bits - CsIntSwap (&BaseRegS0, EnChipSels, (i + Offset), (j + Offset)); - NBPtr->SetBitField (NBPtr, BFCSBaseAddr0Reg + Cs, BaseRegS0); - CsIntSwap (&BaseRegS1, EnChipSels, (i + Offset), (j + Offset)); - NBPtr->SetBitField (NBPtr, BFCSBaseAddr0Reg + Cs + 1, BaseRegS1); - } - } - // - // Bank Interleaving is requested and has been enabled as well - // - NBPtr->MCTPtr->DctData[Dct].BkIntDis = FALSE; - return TRUE; - } else { - // - // Bank Interleaving is requested but cannot be enabled - // - PutEventLog (AGESA_WARNING, MEM_WARNING_BANK_INTERLEAVING_NOT_ENABLED, NBPtr->Node, NBPtr->Dct, NBPtr->Channel, 0, &NBPtr->MemPtr->StdHeader); - SetMemError (AGESA_WARNING, NBPtr->MCTPtr); - NBPtr->MCTPtr->DctData[Dct].BkIntDis = TRUE; - } - return FALSE; -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * This supporting function swaps Chip selects - * - * @param[in,out] *BaseMaskRegPtr - Pointer to the Mask Register - * @param[in] *EnChipSels - Chip Selects to Enable - * @param[in] *LoBit - Lowest Bit - * @param[in] *HiBit - Highest Bit - * - * - */ - -VOID -STATIC -CsIntSwap ( - IN OUT UINT32 *BaseMaskRegPtr, - IN UINT8 EnChipSels, - IN UINT8 LoBit, - IN UINT8 HiBit - ) -{ - UINT8 BitDelta; - UINT32 TempHi; - UINT32 TempLo; - UINT32 AddrLoMask; - UINT32 AddrHiMask; - - ASSERT (BaseMaskRegPtr != NULL); - ASSERT (HiBit > LoBit); - - BitDelta = HiBit - LoBit; - AddrLoMask = (((UINT32)EnChipSels) - 1) << LoBit; - AddrHiMask = AddrLoMask << BitDelta; - - TempHi = TempLo = *BaseMaskRegPtr; - TempLo &= AddrLoMask; - TempLo <<= BitDelta; // move lower bits to upper bit position - TempHi &= AddrHiMask; - TempHi >>= BitDelta; // move upper bits to lower bit position - - *BaseMaskRegPtr &= ~AddrLoMask; - *BaseMaskRegPtr &= ~AddrHiMask; - *BaseMaskRegPtr |= TempLo | TempHi; -} diff --git a/src/vendorcode/amd/agesa/f12/Proc/Mem/Feat/CSINTLV/mfcsi.h b/src/vendorcode/amd/agesa/f12/Proc/Mem/Feat/CSINTLV/mfcsi.h deleted file mode 100644 index f31896c292..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/Mem/Feat/CSINTLV/mfcsi.h +++ /dev/null @@ -1,80 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * mfcsi.h - * - * Memory Controller - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: (Mem) - * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $ - * - **/ -/***************************************************************************** - * - * Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * *************************************************************************** - * - */ - - -#ifndef _MFCSI_H_ -#define _MFCSI_H_ - -/*---------------------------------------------------------------------------- - * Mixed (DEFINITIONS AND MACROS / TYPEDEFS, STRUCTURES, ENUMS) - * - *---------------------------------------------------------------------------- - */ - -/*----------------------------------------------------------------------------- - * DEFINITIONS AND MACROS - * - *----------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------- - * TYPEDEFS, STRUCTURES, ENUMS - * - *---------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------- - * FUNCTIONS PROTOTYPE - * - *---------------------------------------------------------------------------- - */ - -BOOLEAN -MemFInterleaveBanks ( - IN OUT MEM_NB_BLOCK *NBPtr - ); - -#endif /* _MFCSI_H_ */ - - diff --git a/src/vendorcode/amd/agesa/f12/Proc/Mem/Feat/DMI/Makefile.inc b/src/vendorcode/amd/agesa/f12/Proc/Mem/Feat/DMI/Makefile.inc deleted file mode 100644 index c5c1eac7d8..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/Mem/Feat/DMI/Makefile.inc +++ /dev/null @@ -1 +0,0 @@ -libagesa-y += mfDMI.c diff --git a/src/vendorcode/amd/agesa/f12/Proc/Mem/Feat/DMI/mfDMI.c b/src/vendorcode/amd/agesa/f12/Proc/Mem/Feat/DMI/mfDMI.c deleted file mode 100644 index a663337b29..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/Mem/Feat/DMI/mfDMI.c +++ /dev/null @@ -1,588 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * mfDMI.c - * - * Memory DMI table support. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: (Mem/Main) - * @e \$Revision: 51884 $ @e \$Date: 2011-04-28 22:48:03 +0800 (Thu, 28 Apr 2011) $ - * - **/ -/***************************************************************************** - * - * Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * *************************************************************************** - * - */ - -/* - *---------------------------------------------------------------------------- - * MODULES USED - * - *---------------------------------------------------------------------------- - */ - -#include "AGESA.h" -#include "Ids.h" -#include "heapManager.h" -#include "cpuRegisters.h" -#include "cpuServices.h" -#include "mm.h" -#include "mn.h" -#include "mu.h" -#include "GeneralServices.h" -#include "Filecode.h" -CODE_GROUP (G2_PEI) -RDATA_GROUP (G2_PEI) - -#define FILECODE PROC_MEM_FEAT_DMI_MFDMI_FILECODE -/*---------------------------------------------------------------------------- - * DEFINITIONS AND MACROS - * - *---------------------------------------------------------------------------- - */ - -#define MAX_DCTS_PER_DIE 2 - -/*---------------------------------------------------------------------------- - * TYPEDEFS AND STRUCTURES - * - *---------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------- - * PROTOTYPES OF LOCAL FUNCTIONS - * - *---------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------- - * EXPORTED FUNCTIONS - * - *---------------------------------------------------------------------------- - */ -BOOLEAN -MemFDMISupport3 ( - IN OUT MEM_MAIN_DATA_BLOCK *MemMainPtr - ); - -BOOLEAN -MemFDMISupport2 ( - IN OUT MEM_MAIN_DATA_BLOCK *MemMainPtr - ); - -/* -----------------------------------------------------------------------------*/ -/** - * - * - * This function gets DDR3 DMI information from SPD buffer and stores the info into heap - * - * @param[in,out] *MemMainPtr - Pointer to the MEM_MAIN_DATA_BLOCK - * - */ -BOOLEAN -MemFDMISupport3 ( - IN OUT MEM_MAIN_DATA_BLOCK *MemMainPtr - ) -{ - UINT8 i; - UINT8 Dimm; - UINT8 Socket; - UINT8 NodeId; - UINT8 Dct; - UINT8 Channel; - UINT8 temp; - UINT8 MaxDimms; - UINT8 DimmIndex; - UINT8 MaxChannelsPerSocket; - UINT8 MaxDimmsPerChannel; - UINT8 FormFactor; - UINT16 TotalWidth; - UINT16 Speed; - UINT16 Capacity; - UINT16 Width; - UINT16 Rank; - UINT16 BusWidth; - UINT64 ManufacturerIdCode; - UINT32 MaxSockets; - UINT32 Address; - UINT32 TotalSize; - - MEM_NB_BLOCK *NBPtr; - MEM_DATA_STRUCT *MemPtr; - ALLOCATE_HEAP_PARAMS AllocHeapParams; - MEM_DMI_INFO *DmiTable; - MEM_PARAMETER_STRUCT *RefPtr; - - DIE_STRUCT *MCTPtr; - CH_DEF_STRUCT *ChannelPtr; - SPD_DEF_STRUCT *SpdDataStructure; - - NBPtr = MemMainPtr->NBPtr; - MemPtr = MemMainPtr->MemPtr; - SpdDataStructure = MemPtr->SpdDataStructure; - MCTPtr = NBPtr->MCTPtr; - RefPtr = MemPtr->ParameterListPtr; - - // Initialize local variables - MaxDimms = 0; - TotalSize = 0; - - AGESA_TESTPOINT (TpProcMemDmi, &MemPtr->StdHeader); - - ASSERT (NBPtr != NULL); - - MaxSockets = (UINT8) (0x000000FF & GetPlatformNumberOfSockets ()); - for (Socket = 0; Socket < MaxSockets; Socket++) { - for (Channel = 0; Channel < GetMaxChannelsPerSocket (RefPtr->PlatformMemoryConfiguration, Socket, &MemPtr->StdHeader); Channel++) { - temp = GetMaxDimmsPerChannel (RefPtr->PlatformMemoryConfiguration, Socket, Channel); - MaxDimms = MaxDimms + temp; - } - } - - // Allocate heap for memory DMI table 16, 17, 19, 20 - AllocHeapParams.RequestedBufferSize = MaxDimms * sizeof (MEM_DMI_INFO) + 6 + sizeof (DMI_T17_MEMORY_TYPE); - - AllocHeapParams.BufferHandle = AMD_DMI_MEM_DEV_INFO_HANDLE; - AllocHeapParams.Persist = HEAP_SYSTEM_MEM; - if (AGESA_SUCCESS != HeapAllocateBuffer (&AllocHeapParams, &MemPtr->StdHeader)) { - PutEventLog (AGESA_CRITICAL, MEM_ERROR_HEAP_ALLOCATE_FOR_DMI_TABLE_DDR3, NBPtr->Node, 0, 0, 0, &MemPtr->StdHeader); - SetMemError (AGESA_CRITICAL, MCTPtr); - ASSERT(FALSE); // Could not allocate heap for memory DMI table 16,17,19 and 20 for DDR3 - return FALSE; - } - - DmiTable = (MEM_DMI_INFO *) ((UINT8 *) (AllocHeapParams.BufferPtr) + 6 + sizeof (DMI_T17_MEMORY_TYPE)); - *((UINT16 *) (AllocHeapParams.BufferPtr)) = MaxDimms; // Number of memory devices - *((DMI_T17_MEMORY_TYPE *) ((UINT8 *) (AllocHeapParams.BufferPtr) + 6)) = Ddr3MemType; // Memory type - - // - // DMI TYPE 17 - // - DimmIndex = 0; - for (Socket = 0; Socket < MaxSockets; Socket++) { - MaxChannelsPerSocket = GetMaxChannelsPerSocket (RefPtr->PlatformMemoryConfiguration, Socket, &MemPtr->StdHeader); - for (Channel = 0; Channel < MaxChannelsPerSocket; Channel++) { - // - // Get Node number and Dct number for this channel - // - ChannelPtr = MemPtr->SocketList[Socket].ChannelPtr[Channel]; - NodeId = ChannelPtr->MCTPtr->NodeId; - Dct = ChannelPtr->Dct; - NBPtr[NodeId].SwitchDCT (&NBPtr[NodeId], Dct); - MaxDimmsPerChannel = GetMaxDimmsPerChannel (RefPtr->PlatformMemoryConfiguration, Socket, Channel); - for (Dimm = 0; Dimm < MaxDimmsPerChannel; Dimm++, DimmIndex++) { - DmiTable[DimmIndex].TotalWidth = 0xFFFF; - DmiTable[DimmIndex].DataWidth = 0xFFFF; - DmiTable[DimmIndex].MemorySize = 0; - DmiTable[DimmIndex].Speed = 0; - DmiTable[DimmIndex].ManufacturerIdCode = 0; - DmiTable[DimmIndex].Attributes = 0; - DmiTable[DimmIndex].StartingAddr = 0; - DmiTable[DimmIndex].EndingAddr = 0; - DmiTable[DimmIndex].DimmPresent = 0; - DmiTable[DimmIndex].Socket = Socket; - DmiTable[DimmIndex].Channel = Channel; - DmiTable[DimmIndex].Dimm = Dimm; - DmiTable[DimmIndex].ConfigSpeed = 0; - - for (i = 0; i < 4; i++) { - DmiTable[DimmIndex].SerialNumber[i] = 0xFF; - } - - for (i = 0; i < 18; i++) { - DmiTable[DimmIndex].PartNumber[i] = 0x0; - } - - if (SpdDataStructure[DimmIndex].DimmPresent) { - // Total Width (offset 08h) & Data Width (offset 0Ah) - TotalWidth = (UINT16) SpdDataStructure[DimmIndex].Data[8]; - if ((TotalWidth & 0x18) == 0) { - // non ECC - if ((TotalWidth & 0x07) == 0) { - DmiTable[DimmIndex].TotalWidth = 8; // 8 bits - } else if ((TotalWidth & 0x07) == 1) { - DmiTable[DimmIndex].TotalWidth = 16; // 16 bits - } else if ((TotalWidth & 0x07) == 2) { - DmiTable[DimmIndex].TotalWidth = 32; // 32 bits - } else if ((TotalWidth & 0x07) == 3) { - DmiTable[DimmIndex].TotalWidth = 64; // 64 bits - } - DmiTable[DimmIndex].DataWidth = DmiTable[DimmIndex].TotalWidth ; - } else { - // ECC - if ((TotalWidth & 0x07) == 0) { - DmiTable[DimmIndex].TotalWidth = 8 + 8; // 8 bits - } else if ((TotalWidth & 0x07) == 1) { - DmiTable[DimmIndex].TotalWidth = 16 + 8; // 16 bits - } else if ((TotalWidth & 0x07) == 2) { - DmiTable[DimmIndex].TotalWidth = 32 + 8; // 32 bits - } else if ((TotalWidth & 0x07) == 3) { - DmiTable[DimmIndex].TotalWidth = 64 + 8; // 64 bits - } - DmiTable[DimmIndex].DataWidth = DmiTable[DimmIndex].TotalWidth - 8; - } - - // Memory Size (offset 0Ch) - Capacity = 0; - BusWidth = 0; - Width = 0; - Rank = 0; - temp = (UINT8) SpdDataStructure[DimmIndex].Data[4]; - if ((temp & 0x0F) == 0) { - Capacity = 0x0100; // 256M - } else if ((temp & 0x0F) == 1) { - Capacity = 0x0200; // 512M - } else if ((temp & 0x0F) == 2) { - Capacity = 0x0400; // 1G - } else if ((temp & 0x0F) == 3) { - Capacity = 0x0800; // 2G - } else if ((temp & 0x0F) == 4) { - Capacity = 0x1000; // 4G - } else if ((temp & 0x0F) == 5) { - Capacity = 0x2000; // 8G - } else if ((temp & 0x0F) == 6) { - Capacity = 0x4000; // 16G - } - - temp = (UINT8) SpdDataStructure[DimmIndex].Data[8]; - if ((temp & 0x07) == 0) { - BusWidth = 8; // 8 bits - } else if ((temp & 0x07) == 1) { - BusWidth = 16; // 16 bits - } else if ((temp & 0x07) == 2) { - BusWidth = 32; // 32 bits - } else if ((temp & 0x07) == 3) { - BusWidth = 64; // 64 bits - } - - temp = (UINT8) SpdDataStructure[DimmIndex].Data[7]; - if ((temp & 0x07) == 0) { - Width = 4; // 4 bits - } else if ((temp & 0x07) == 1) { - Width = 8; // 8 bits - } else if ((temp & 0x07) == 2) { - Width = 16; // 16 bits - } else if ((temp & 0x07) == 3) { - Width = 32; // 32 bits - } - - temp = (UINT8) SpdDataStructure[DimmIndex].Data[7]; - if (((temp >> 3) & 0x07) == 0) { - Rank = 1; // 4 bits - DmiTable[DimmIndex].Attributes = 1; // Single Rank Dimm - } else if (((temp >> 3) & 0x07) == 1) { - Rank = 2; // 8 bits - DmiTable[DimmIndex].Attributes = 2; // Dual Rank Dimm - } else if (((temp >> 3) & 0x07) == 2) { - Rank = 3; // 16 bits - } else if (((temp >> 3) & 0x07) == 3) { - Rank = 4; // 32 bits - DmiTable[DimmIndex].Attributes = 4; // Quad Rank Dimm - } - - DmiTable[DimmIndex].MemorySize = (UINT16) (Capacity / 8 * BusWidth / Width * Rank); - - // Form Factor (offset 0Eh) - FormFactor = (UINT8) SpdDataStructure[DimmIndex].Data[3]; - if ((FormFactor & 0x01) == 0 || (FormFactor & 0x02) == 0) { - DmiTable[DimmIndex].FormFactor = 0x09; // RDIMM or UDIMM - } else if ((FormFactor & 0x03) == 0) { - DmiTable[DimmIndex].FormFactor = 0x0D; // SO-DIMM - } - - // DIMM Present - DmiTable[DimmIndex].DimmPresent = 1; - - // Speed (offset 15h) - Speed = (UINT16) SpdDataStructure[DimmIndex].Data[12]; - if (Speed == 20) { - DmiTable[DimmIndex].Speed = 800; // DDR3-800 - } else if (Speed == 15) { - DmiTable[DimmIndex].Speed = 1066; // DDR3-1066 - } else if (Speed == 12) { - DmiTable[DimmIndex].Speed = 1333; // DDR3-1333 - } else if (Speed == 10) { - DmiTable[DimmIndex].Speed = 1600; // DDR3-1600 - } - - // Manufacturer (offset 17h) - ManufacturerIdCode = (UINT64) SpdDataStructure[DimmIndex].Data[118]; - DmiTable[DimmIndex].ManufacturerIdCode = (ManufacturerIdCode << 8) | ((UINT64) SpdDataStructure[DimmIndex].Data[117]); - - // Serial Number (offset 18h) - for (i = 0; i < 4; i++) { - DmiTable[DimmIndex].SerialNumber[i] = (UINT8) SpdDataStructure[DimmIndex].Data[i + 122]; - } - // Part Number (offset 1Ah) - for (i = 0; i < 18; i++) { - DmiTable[DimmIndex].PartNumber[i] = (UINT8) SpdDataStructure[DimmIndex].Data[i + 128]; - } - // Extended Size (offset 1Ch) - @todo: pending for SPD SPEC update - DmiTable[DimmIndex].ExtSize = 0; - - // Configured Memory Clock Speed (offset 20h) - DmiTable[DimmIndex].ConfigSpeed = NBPtr[NodeId].DCTPtr->Timings.Speed; - - // Starting/Ending Address for each DIMM - if ((NBPtr[NodeId].GetBitField (&NBPtr[NodeId], BFCSBaseAddr0Reg + 2 * Dimm) & 1) != 0) { - Address = (NBPtr[NodeId].GetBitField (&NBPtr[NodeId], BFCSBaseAddr0Reg + 2 * Dimm)) & NBPtr->CsRegMsk; - Address = (Address & 0xFFFF0000) >> 2; - DmiTable[DimmIndex].StartingAddr = Address; - if (RefPtr->EnableBankIntlv && !NBPtr[NodeId].MCTPtr->DctData[Dct].BkIntDis) { - DmiTable[DimmIndex].EndingAddr = Address + (((NBPtr[NodeId].GetBitField (&NBPtr[NodeId], BFCSMask0Reg + Dimm) & 0xFFFF0000) + 0x00080000) >> 2) - 1; - } else { - DmiTable[DimmIndex].EndingAddr = Address + (UINT32) (DmiTable[DimmIndex].MemorySize * 0x0400) - 1; - } - } - } // Dimm present - TotalSize += (UINT32) DmiTable[DimmIndex].MemorySize; - } // Dimm loop - } // Channel loop - } // Socket loop - - *((UINT32 *) ((UINT8 *) (AllocHeapParams.BufferPtr) + 2)) = TotalSize; // Max Capacity - - return TRUE; -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * - * This function gets DDR2 DMI information from SPD buffer and stores the info into heap - * - * @param[in,out] *MemMainPtr - Pointer to the MEM_MAIN_DATA_BLOCK - * - */ -BOOLEAN -MemFDMISupport2 ( - IN OUT MEM_MAIN_DATA_BLOCK *MemMainPtr - ) -{ - UINT8 i; - UINT8 Dimm; - UINT8 Socket; - UINT8 NodeId; - UINT8 Dct; - UINT8 Channel; - UINT8 temp; - UINT8 MaxDimms; - UINT8 DimmIndex; - UINT8 MaxChannelsPerSocket; - UINT8 MaxDimmsPerChannel; - UINT8 FormFactor; - UINT8 Temp; - UINT8 Rank; - UINT16 TotalWidth; - UINT32 Speed; - UINT32 MaxSockets; - UINT32 Address; - - MEM_NB_BLOCK *NBPtr; - MEM_DATA_STRUCT *MemPtr; - ALLOCATE_HEAP_PARAMS AllocHeapParams; - MEM_DMI_INFO *DmiTable; - DIE_STRUCT *MCTPtr; - CH_DEF_STRUCT *ChannelPtr; - SPD_DEF_STRUCT *SpdDataStructure; - MEM_PARAMETER_STRUCT *RefPtr; - - NBPtr = MemMainPtr->NBPtr; - MemPtr = MemMainPtr->MemPtr; - SpdDataStructure = MemPtr->SpdDataStructure; - MCTPtr = NBPtr->MCTPtr; - RefPtr = MemPtr->ParameterListPtr; - - // Initialize local variables - MaxDimms = 0; - - ASSERT (NBPtr != NULL); - - MaxSockets = (UINT8) (0x000000FF & GetPlatformNumberOfSockets ()); - for (Socket = 0; Socket < MaxSockets; Socket++) { - for (Channel = 0; Channel < GetMaxChannelsPerSocket (RefPtr->PlatformMemoryConfiguration, Socket, &MemPtr->StdHeader); Channel++) { - temp = GetMaxDimmsPerChannel (RefPtr->PlatformMemoryConfiguration, Socket, Channel); - MaxDimms = MaxDimms + temp; - } - } - - // Allocate heap for memory DMI table 16, 17, 19, 20 - AllocHeapParams.RequestedBufferSize = MaxDimms * sizeof (MEM_DMI_INFO) + 3; - - AllocHeapParams.BufferHandle = AMD_DMI_MEM_DEV_INFO_HANDLE; - AllocHeapParams.Persist = HEAP_SYSTEM_MEM; - if (AGESA_SUCCESS != HeapAllocateBuffer (&AllocHeapParams, &MemPtr->StdHeader)) { - PutEventLog (AGESA_CRITICAL, MEM_ERROR_HEAP_ALLOCATE_FOR_DMI_TABLE_DDR2, NBPtr->Node, 0, 0, 0, &MemPtr->StdHeader); - SetMemError (AGESA_CRITICAL, MCTPtr); - ASSERT(FALSE); // Could not allocate heap for memory DMI table 16,17,19 and 20 for DDR2 - return FALSE; - } - - DmiTable = (MEM_DMI_INFO *) ((UINT8 *) (AllocHeapParams.BufferPtr) + 2 + sizeof (DMI_T17_MEMORY_TYPE)); - *((UINT16 *) (AllocHeapParams.BufferPtr)) = MaxDimms; // Number of memory devices - *((DMI_T17_MEMORY_TYPE *) ((UINT8 *) (AllocHeapParams.BufferPtr) + 2)) = Ddr2MemType; // Memory type - - // - // DMI TYPE 17 - // - DimmIndex = 0; - for (Socket = 0; Socket < MaxSockets; Socket++) { - MaxChannelsPerSocket = GetMaxChannelsPerSocket (RefPtr->PlatformMemoryConfiguration, Socket, &MemPtr->StdHeader); - for (Channel = 0; Channel < MaxChannelsPerSocket; Channel++) { - // - // Get Node number and Dct number for this channel - // - ChannelPtr = MemPtr->SocketList[Socket].ChannelPtr[Channel]; - NodeId = ChannelPtr->MCTPtr->NodeId; - Dct = ChannelPtr->Dct; - NBPtr[NodeId].SwitchDCT (&NBPtr[NodeId], Dct); - NBPtr[NodeId].SwitchDCT (&NBPtr[NodeId], Dct); - MaxDimmsPerChannel = GetMaxDimmsPerChannel (RefPtr->PlatformMemoryConfiguration, Socket, Channel); - for (Dimm = 0; Dimm < MaxDimmsPerChannel; Dimm++, DimmIndex++) { - DmiTable[DimmIndex].TotalWidth = 0xFFFF; - DmiTable[DimmIndex].DataWidth = 0xFFFF; - DmiTable[DimmIndex].MemorySize = 0xFFFF; - DmiTable[DimmIndex].Speed = 0; - DmiTable[DimmIndex].ManufacturerIdCode = 0; - DmiTable[DimmIndex].Attributes = 0; - DmiTable[DimmIndex].StartingAddr = 0xFFFFFFFF; - DmiTable[DimmIndex].EndingAddr = 0xFFFFFFFF; - DmiTable[DimmIndex].DimmPresent = 0; - DmiTable[DimmIndex].ConfigSpeed = 0; - - for (i = 0; i < 4; i++) { - DmiTable[DimmIndex].SerialNumber[i] = 0xFF; - } - - for (i = 0; i < 18; i++) { - DmiTable[DimmIndex].PartNumber[i] = 0x0; - } - - if (SpdDataStructure[DimmIndex].DimmPresent) { - // Total Width (offset 08h) & Data Width (offset 0Ah) - TotalWidth = (UINT16) SpdDataStructure[DimmIndex].Data[13]; - if ((TotalWidth & 0x04) != 0) { - DmiTable[DimmIndex].TotalWidth = 4; // 4 bits - } else if ((TotalWidth & 0x08) != 0) { - DmiTable[DimmIndex].TotalWidth = 8; // 8 bits - } else if ((TotalWidth & 0x10) != 0) { - DmiTable[DimmIndex].TotalWidth = 16; // 16 bits - } else if ((TotalWidth & 0x20) != 0) { - DmiTable[DimmIndex].TotalWidth = 32; // 32 bits - } - DmiTable[DimmIndex].DataWidth = DmiTable[DimmIndex].TotalWidth; - - // Memory Size (offset 0Ch), Attributes (offset 1Bh) - Rank = (UINT8) SpdDataStructure[DimmIndex].Data[5] & 0x07; - if (Rank == 0) { - DmiTable[DimmIndex].Attributes = 1; // Single Rank Dimm - } else if (Rank == 1) { - DmiTable[DimmIndex].Attributes = 2; // Dual Rank Dimm - } else if (Rank == 3) { - DmiTable[DimmIndex].Attributes = 4; // Quad Rank Dimm - } - - Temp = (UINT8) SpdDataStructure[DimmIndex].Data[31]; - for (i = 0; i < 8; i++) { - if ((Temp & 0x01) == 1) { - DmiTable[DimmIndex].MemorySize = 0x80 * (i + 1) * (Rank + 1); - } - Temp = Temp >> 1; - } - - // Form Factor (offset 0Eh) - FormFactor = (UINT8) SpdDataStructure[DimmIndex].Data[20]; - if ((FormFactor & 0x04) == 4) { - DmiTable[DimmIndex].FormFactor = 0x0D; // SO-DIMM - } else { - DmiTable[DimmIndex].FormFactor = 0x09; // RDIMM or UDIMM - } - - // DIMM Present - DmiTable[DimmIndex].DimmPresent = 1; - - // DIMM Index - DmiTable[DimmIndex].Socket = Socket; - DmiTable[DimmIndex].Channel = Channel; - DmiTable[DimmIndex].Dimm = Dimm; - - // Speed (offset 15h) - Speed = NBPtr[NodeId].GetBitField (&NBPtr[NodeId], BFDramConfigHiReg); - Speed = Speed & 0x00000007; - if (Speed == 0) { - DmiTable[DimmIndex].Speed = 400; // 400MHz - } else if (Speed == 1) { - DmiTable[DimmIndex].Speed = 533; // 533MHz - } else if (Speed == 2) { - DmiTable[DimmIndex].Speed = 667; // 667MHz - } else if (Speed == 3) { - DmiTable[DimmIndex].Speed = 800; // 800MHz - } - - // Manufacturer (offset 17h) - DmiTable[DimmIndex].ManufacturerIdCode = (UINT64) SpdDataStructure[DimmIndex].Data[64]; - - // Serial Number (offset 18h) - for (i = 0; i < 4; i++) { - DmiTable[DimmIndex].SerialNumber[i] = (UINT8) SpdDataStructure[DimmIndex].Data[i + 95]; - } - - // Part Number (offset 1Ah) - for (i = 0; i < 18; i++) { - DmiTable[DimmIndex].PartNumber[i] = (UINT8) SpdDataStructure[DimmIndex].Data[i + 73]; - } - - // Configured Memory Clock Speed (offset 20h) - DmiTable[DimmIndex].ConfigSpeed = NBPtr[NodeId].DCTPtr->Timings.Speed; - - // AGESA does NOT support this feature when bank interleaving is enabled. - if (!RefPtr->EnableBankIntlv) { - if ((NBPtr[NodeId].GetBitField (&NBPtr[NodeId], BFCSBaseAddr0Reg + 2 * Dimm) & 1) != 0) { - Address = (NBPtr[NodeId].GetBitField (&NBPtr[NodeId], BFCSBaseAddr0Reg + 2 * Dimm)) & NBPtr->CsRegMsk; - Address = Address >> 2; - DmiTable[DimmIndex].StartingAddr = Address; - DmiTable[DimmIndex].EndingAddr = Address + (UINT32) (DmiTable[DimmIndex].MemorySize * 0x0400); - } - } - - } // DIMM Present - } // DIMM loop - } - } - - return TRUE; -} - -/*--------------------------------------------------------------------------------------- - * L O C A L F U N C T I O N S - *--------------------------------------------------------------------------------------- - */ - diff --git a/src/vendorcode/amd/agesa/f12/Proc/Mem/Feat/ECC/Makefile.inc b/src/vendorcode/amd/agesa/f12/Proc/Mem/Feat/ECC/Makefile.inc deleted file mode 100644 index 25c0f38607..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/Mem/Feat/ECC/Makefile.inc +++ /dev/null @@ -1,2 +0,0 @@ -libagesa-y += mfecc.c -libagesa-y += mfemp.c diff --git a/src/vendorcode/amd/agesa/f12/Proc/Mem/Feat/ECC/mfecc.c b/src/vendorcode/amd/agesa/f12/Proc/Mem/Feat/ECC/mfecc.c deleted file mode 100644 index 757a19c776..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/Mem/Feat/ECC/mfecc.c +++ /dev/null @@ -1,328 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * mfecc.c - * - * Feature ECC initialization functions - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: (Mem/Feat/ECC) - * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $ - * - **/ -/***************************************************************************** - * - * Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * *************************************************************************** - * - */ - -#include "AGESA.h" -#include "amdlib.h" -#include "Ids.h" -#include "mm.h" -#include "mn.h" -#include "mfecc.h" -#include "Filecode.h" -#include "mfmemclr.h" -#include "GeneralServices.h" -CODE_GROUP (G2_PEI) -RDATA_GROUP (G2_PEI) - -#define FILECODE PROC_MEM_FEAT_ECC_MFECC_FILECODE -/*---------------------------------------------------------------------------- - * DEFINITIONS AND MACROS - * - *---------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------- - * TYPEDEFS AND STRUCTURES - * - *---------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------- - * PROTOTYPES OF LOCAL FUNCTIONS - * - *---------------------------------------------------------------------------- - */ -/* -UINT32 -STATIC -MemFGetScrubAddr ( - IN OUT MEM_NB_BLOCK *NBPtr - ); -*/ - -VOID -STATIC -InitECCOverriedeStruct ( - IN OUT MEM_NB_BLOCK *NBPtr, - IN OUT ECC_OVERRIDE_STRUCT *pecc_override_struct - ); - -/* - *----------------------------------------------------------------------------- - * EXPORTED FUNCTIONS - * - *----------------------------------------------------------------------------- - */ -BOOLEAN -MemFCheckECC ( - IN OUT MEM_NB_BLOCK *NBPtr - ); - -extern BUILD_OPT_CFG UserOptions; - -/* -----------------------------------------------------------------------------*/ -/** - * - * - * This function checks to see if ECC can be enabled on all nodes - * - * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK - * - * @return TRUE - This feature is enabled. - * @return FALSE - This feature is not enabled. - */ - -BOOLEAN -MemFCheckECC ( - IN OUT MEM_NB_BLOCK *NBPtr - ) -{ - DIE_STRUCT *MCTPtr; - MEM_SHARED_DATA *SharedPtr; - BOOLEAN ErrorRecovery; - - ASSERT (NBPtr != NULL); - - MCTPtr = NBPtr->MCTPtr; - SharedPtr = NBPtr->SharedPtr; - - ErrorRecovery = TRUE; - IDS_OPTION_HOOK (IDS_MEM_ERROR_RECOVERY, &ErrorRecovery, &NBPtr->MemPtr->StdHeader); - - if (MCTPtr->NodeMemSize != 0) { - if (SharedPtr->AllECC && MCTPtr->Status[SbEccDimms] && (ErrorRecovery || (MCTPtr->ErrCode < AGESA_ERROR))) { - // Clear all MCA reports before using scrubber - // to initialize ECC check bits - // - NBPtr->McaNbCtlReg = NBPtr->GetBitField (NBPtr, BFMcaNbCtlReg); - NBPtr->SetBitField (NBPtr, BFMcaNbCtlReg, 0); - NBPtr->SetBitField (NBPtr, BFSyncOnUcEccEn, 0); - // In unganged mode, set DctDctIntlv - if (!NBPtr->Ganged) { - NBPtr->SetBitField (NBPtr, BFDctDatIntLv, 1); - } - // - // Set Ecc Symbol Size - // - NBPtr->SetEccSymbolSize (NBPtr); - // If ECC can be enabled on this node, - // set the master ECCen bit (according to setup) - // - NBPtr->SetBitField (NBPtr, BFDramEccEn, 1); - // Do mem clear on current node - MemFMctMemClr_Init (NBPtr); - return TRUE; - } else { - if (SharedPtr->AllECC) { - SharedPtr->AllECC = FALSE; - } - // ECC requested but cannot be enabled - MCTPtr->Status[SbEccDimms] = FALSE; - MCTPtr->ErrStatus[EsbDramECCDis] = TRUE; - PutEventLog (AGESA_ERROR, MEM_ERROR_ECC_DIS, NBPtr->Node, 0, 0, 0, &NBPtr->MemPtr->StdHeader); - SetMemError (AGESA_ERROR, MCTPtr); - } - } - return FALSE; -} - - /* -----------------------------------------------------------------------------*/ -/** - * - * - * This function initializes the ECC on all nodes - * - * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK - * - * @return TRUE - This feature is enabled. - * @return FALSE - This feature is not enabled. - */ - -BOOLEAN -MemFInitECC ( - IN OUT MEM_NB_BLOCK *NBPtr - ) -{ - UINT8 Node; - UINT32 ScrubAddrRJ16; - DIE_STRUCT *MCTPtr; - MEM_SHARED_DATA *SharedPtr; - ECC_OVERRIDE_STRUCT ecc_override_struct; - BOOLEAN Flag; - - InitECCOverriedeStruct (NBPtr, &ecc_override_struct); - IDS_OPTION_HOOK (IDS_ECC, &ecc_override_struct, &(NBPtr->MemPtr->StdHeader)); - - ASSERT (NBPtr != NULL); - - MCTPtr = NBPtr->MCTPtr; - Node = MCTPtr->NodeId; - SharedPtr = NBPtr->SharedPtr; - Flag = TRUE; - - NBPtr->FamilySpecificHook[ScrubberErratum] (NBPtr, (VOID *) &Flag); - - if ((MCTPtr->Status[SbEccDimms]) && (SharedPtr->AllECC)) { - // Check if the input dram scrub rate is supported or not - ASSERT (ecc_override_struct.CfgScrubDramRate <= 0x16); - if (ecc_override_struct.CfgScrubDramRate != 0) { - // Program scrub address, - // let the scrub Addr be the Base of this Node - // Only enable Dram scrubber when there is memory on current node - // - NBPtr->SetBitField (NBPtr, BFScrubReDirEn, 0); - ScrubAddrRJ16 = (NBPtr->GetBitField (NBPtr, BFDramBaseReg0 + Node) & 0xFFFF0000) >> 8; - ScrubAddrRJ16 |= NBPtr->GetBitField (NBPtr, BFDramBaseHiReg0 + Node) << 24; - NBPtr->SetBitField (NBPtr, BFScrubAddrLoReg, ScrubAddrRJ16 << 16); - NBPtr->SetBitField (NBPtr, BFScrubAddrHiReg, ScrubAddrRJ16 >> 16); - NBPtr->SetBitField (NBPtr, BFDramScrub, ecc_override_struct.CfgScrubDramRate); - } - } - // Scrub CTL for Dcache, L2, L3 - // Check if the input L2 scrub rate is supported or not - ASSERT (ecc_override_struct.CfgScrubL2Rate <= 0x16); - NBPtr->SetBitField (NBPtr, BFL2Scrub, ecc_override_struct.CfgScrubL2Rate); - // Check if the input Dcache scrub rate is supported or not - ASSERT (ecc_override_struct.CfgScrubDcRate <= 0x16); - NBPtr->SetBitField (NBPtr, BFDcacheScrub, ecc_override_struct.CfgScrubDcRate); - // Do not enable L3 Scrub if F3xE8[L3Capable] is 0 or F3x188[DisableL3] is 1 - if ((NBPtr->GetBitField (NBPtr, BFL3Capable) == 1) && (NBPtr->GetBitField (NBPtr, BFDisableL3) == 0)) { - // Check if input L3 scrub rate is supported or not - ASSERT (ecc_override_struct.CfgScrubL3Rate <= 0x16); - NBPtr->SetBitField (NBPtr, BFL3Scrub, ecc_override_struct.CfgScrubL3Rate); - } - - // Check if Dcache scrubber or L2 scrubber is enabled - if ((ecc_override_struct.CfgScrubL2Rate != 0) || (ecc_override_struct.CfgScrubDcRate!= 0)) { - // If ClkDivisor is deeper than divide-by-16 - if (NBPtr->GetBitField (NBPtr, BFC1ClkDivisor) > 4) { - // Set it to divide-by-16 - NBPtr->SetBitField (NBPtr, BFC1ClkDivisor, 4); - } - } - - NBPtr->SetBitField (NBPtr, BFScrubReDirEn, ecc_override_struct.CfgEccRedirection); - NBPtr->SetBitField (NBPtr, BFSyncOnUcEccEn, ecc_override_struct.CfgEccSyncFlood); - // Restore MCA reports after scrubber is done - // with initializing ECC check bits - NBPtr->SetBitField (NBPtr, BFMcaNbCtlReg, NBPtr->McaNbCtlReg); - - Flag = FALSE; - NBPtr->FamilySpecificHook[ScrubberErratum] (NBPtr, (VOID *) &Flag); - - return TRUE; -} - -VOID -STATIC -InitECCOverriedeStruct ( - IN OUT MEM_NB_BLOCK *NBPtr, - IN OUT ECC_OVERRIDE_STRUCT *pecc_override_struct - ) -{ - pecc_override_struct->CfgEccRedirection = UserOptions.CfgEccRedirection; - pecc_override_struct->CfgEccSyncFlood = UserOptions.CfgEccSyncFlood; - pecc_override_struct->CfgScrubDcRate = UserOptions.CfgScrubDcRate; - - if (UserOptions.CfgScrubDramRate != 0xFF) { - pecc_override_struct->CfgScrubDramRate = UserOptions.CfgScrubDramRate; - } else { - if (NBPtr->MCTPtr->NodeMemSize <= 0x4000) { - pecc_override_struct->CfgScrubDramRate = 0x12; // 1 ~ 1 GB - } else if (NBPtr->MCTPtr->NodeMemSize <= 0x8000) { - pecc_override_struct->CfgScrubDramRate = 0x11; // 1 GB + 1 ~ 2 GB - } else if (NBPtr->MCTPtr->NodeMemSize <= 0x10000) { - pecc_override_struct->CfgScrubDramRate = 0x10; // 2 GB + 1 ~ 4 GB - } else if (NBPtr->MCTPtr->NodeMemSize <= 0x20000) { - pecc_override_struct->CfgScrubDramRate = 0x0F; // 4 GB + 1 ~ 8 GB - } else if (NBPtr->MCTPtr->NodeMemSize <= 0x40000) { - pecc_override_struct->CfgScrubDramRate = 0x0E; // 8 GB + 1 ~ 16 GB - } else { - pecc_override_struct->CfgScrubDramRate = 0x0D; //16 GB + 1 above - } - } - - pecc_override_struct->CfgScrubL2Rate = UserOptions.CfgScrubL2Rate; - pecc_override_struct->CfgScrubL3Rate = UserOptions.CfgScrubL3Rate; -} -/*---------------------------------------------------------------------------- - * LOCAL FUNCTIONS - * - *---------------------------------------------------------------------------- - */ - -/* -----------------------------------------------------------------------------*/ -/** - * - * - * This function gets the current 40-bit Scrub ADDR address, scaled to 32-bits, - * of the specified Node. - * - * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK - * - * @return Scrubber Address - */ - -/*UINT32 -STATIC -MemFGetScrubAddr ( - IN OUT MEM_NB_BLOCK *NBPtr - ) -{ - UINT32 ScrubAddrHi; - UINT32 ScrubAddrLo; - UINT32 ScrubAddrRJ16; - - ASSERT (NBPtr != NULL); - - ScrubAddrHi = NBPtr->GetBitField (NBPtr, BFScrubAddrHiReg); - ScrubAddrLo = NBPtr->GetBitField (NBPtr, BFScrubAddrLoReg); - // Scrub Addr High again, detect 32-bit wrap - ScrubAddrRJ16 = NBPtr->GetBitField (NBPtr, BFScrubAddrHiReg); - if (ScrubAddrRJ16 != ScrubAddrHi) { - ScrubAddrHi = ScrubAddrRJ16; - ScrubAddrLo = NBPtr->GetBitField (NBPtr, BFScrubAddrLoReg); - } - return ((ScrubAddrHi << 16) | (ScrubAddrLo >> 16)); -} -*/ diff --git a/src/vendorcode/amd/agesa/f12/Proc/Mem/Feat/ECC/mfecc.h b/src/vendorcode/amd/agesa/f12/Proc/Mem/Feat/ECC/mfecc.h deleted file mode 100644 index aed0eecab4..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/Mem/Feat/ECC/mfecc.h +++ /dev/null @@ -1,80 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * mfecc.h - * - * Feature ECC initialization functions - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: (Mem) - * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $ - * - **/ -/***************************************************************************** - * - * Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * *************************************************************************** - * - */ - - -#ifndef _MFECC_H_ -#define _MFECC_H_ - -/*---------------------------------------------------------------------------- - * Mixed (DEFINITIONS AND MACROS / TYPEDEFS, STRUCTURES, ENUMS) - * - *---------------------------------------------------------------------------- - */ - -/*----------------------------------------------------------------------------- - * DEFINITIONS AND MACROS - * - *----------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------- - * TYPEDEFS, STRUCTURES, ENUMS - * - *---------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------- - * FUNCTIONS PROTOTYPE - * - *---------------------------------------------------------------------------- - */ - -BOOLEAN -MemFInitECC ( - IN OUT MEM_NB_BLOCK *NBPtr - ); - -#endif /* _MFECC_H_ */ - - diff --git a/src/vendorcode/amd/agesa/f12/Proc/Mem/Feat/ECC/mfemp.c b/src/vendorcode/amd/agesa/f12/Proc/Mem/Feat/ECC/mfemp.c deleted file mode 100644 index 75763c03ad..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/Mem/Feat/ECC/mfemp.c +++ /dev/null @@ -1,176 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * mfemp.c - * - * Feature EMP initialization functions - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: (Mem/Feat/ECC) - * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $ - * - **/ -/***************************************************************************** - * - * Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * *************************************************************************** - * - */ - - - - -#include "AGESA.h" -#include "mm.h" -#include "mn.h" -#include "Ids.h" -#include "GeneralServices.h" -#include "Filecode.h" -CODE_GROUP (G2_PEI) -RDATA_GROUP (G2_PEI) - -#define FILECODE PROC_MEM_FEAT_ECC_MFEMP_FILECODE -/*---------------------------------------------------------------------------- - * DEFINITIONS AND MACROS - * - *---------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------- - * TYPEDEFS AND STRUCTURES - * - *---------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------- - * PROTOTYPES OF LOCAL FUNCTIONS - * - *---------------------------------------------------------------------------- - */ -BOOLEAN -STATIC -IsPowerOfTwo ( - IN UINT32 TestNumber - ); - -/* - *----------------------------------------------------------------------------- - * EXPORTED FUNCTIONS - * - *----------------------------------------------------------------------------- - */ -BOOLEAN -MemFInitEMP ( - IN OUT MEM_NB_BLOCK *NBPtr - ); - -extern BUILD_OPT_CFG UserOptions; - -/* -----------------------------------------------------------------------------*/ -/** - * - * - * This function initializes EMP (Enhanced Memory Protection) - * - * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK - * - * @return TRUE - This feature is enabled. - * @return FALSE - This feature is not enabled. - */ - -BOOLEAN -MemFInitEMP ( - IN OUT MEM_NB_BLOCK *NBPtr - ) -{ - MEM_PARAMETER_STRUCT *RefPtr; - DIE_STRUCT *MCTPtr; - - ASSERT (NBPtr != NULL); - - RefPtr = NBPtr->RefPtr; - MCTPtr = NBPtr->MCTPtr; - if (RefPtr->EnableEccFeature) { - if (NBPtr->GetBitField (NBPtr, BFEnhMemProtCap) == 0) { - PutEventLog (AGESA_WARNING, MEM_WARNING_EMP_NOT_SUPPORTED, 0, 0, 0, 0, &NBPtr->MemPtr->StdHeader); - MCTPtr->ErrStatus[EsbEMPNotSupported] = TRUE; - } else if (RefPtr->EnableChannelIntlv || RefPtr->EnableBankIntlv || RefPtr->EnableBankSwizzle) { - PutEventLog (AGESA_WARNING, MEM_WARNING_EMP_CONFLICT, 0, 0, 0, 0, &NBPtr->MemPtr->StdHeader); - MCTPtr->ErrStatus[EsbEMPConflict] = TRUE; - } else if ((!MCTPtr->GangedMode) && - (!IsPowerOfTwo (MCTPtr->DctData[0].Timings.DctMemSize) && - !IsPowerOfTwo (MCTPtr->DctData[1].Timings.DctMemSize))) { - PutEventLog (AGESA_WARNING, MEM_WARNING_EMP_NOT_ENABLED, 0, 0, 0, 0, &NBPtr->MemPtr->StdHeader); - MCTPtr->ErrStatus[EsbEMPDis] = TRUE; - } else { - // Reduce memory size to 7/8 of the original memory size - ASSERT ((MCTPtr->NodeMemSize % 8) == 0); - NBPtr->SetBitField (NBPtr, BFDramHoleValid, 0); - MCTPtr->NodeMemSize = (MCTPtr->NodeMemSize / 8) * 7; - NBPtr->HtMemMapInit (NBPtr); - NBPtr->CpuMemTyping (NBPtr); - - // Enable EMP - NBPtr->SetBitField (NBPtr, BFDramEccEn, 1); - - // Scrub CTL settings for Dcache, L2 - NBPtr->SetBitField (NBPtr, BFL2Scrub, UserOptions.CfgScrubL2Rate); - NBPtr->SetBitField (NBPtr, BFDcacheScrub, UserOptions.CfgScrubDcRate); - - NBPtr->SetBitField (NBPtr, BFSyncOnUcEccEn, UserOptions.CfgEccSyncFlood); - return TRUE; - } - } - return FALSE; -} - -/*---------------------------------------------------------------------------- - * LOCAL FUNCTIONS - * - *---------------------------------------------------------------------------- - */ - -/* -----------------------------------------------------------------------------*/ -/** - * - * - * This function checks to see if the input is power of two. - * - * @param[in] TestNumber - Value to check for power of two - * - * @return TRUE - is power of two - * FALSE - is not power of two - */ -BOOLEAN -STATIC -IsPowerOfTwo ( - IN UINT32 TestNumber - ) -{ - return (BOOLEAN) ((TestNumber & (TestNumber - 1)) == 0); -} diff --git a/src/vendorcode/amd/agesa/f12/Proc/Mem/Feat/EXCLUDIMM/Makefile.inc b/src/vendorcode/amd/agesa/f12/Proc/Mem/Feat/EXCLUDIMM/Makefile.inc deleted file mode 100644 index 31cf348efc..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/Mem/Feat/EXCLUDIMM/Makefile.inc +++ /dev/null @@ -1 +0,0 @@ -libagesa-y += mfdimmexclud.c diff --git a/src/vendorcode/amd/agesa/f12/Proc/Mem/Feat/EXCLUDIMM/mfdimmexclud.c b/src/vendorcode/amd/agesa/f12/Proc/Mem/Feat/EXCLUDIMM/mfdimmexclud.c deleted file mode 100644 index d14674344d..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/Mem/Feat/EXCLUDIMM/mfdimmexclud.c +++ /dev/null @@ -1,201 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * mfdimmexclud.c - * - * Feature DIMM exclude. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: (Mem/Feat/EXCLUDIMM) - * @e \$Revision: 47509 $ @e \$Date: 2011-02-23 06:15:32 +0800 (Wed, 23 Feb 2011) $ - * - **/ -/***************************************************************************** -* -* Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* *************************************************************************** -* -*/ - -/* - *---------------------------------------------------------------------------- - * MODULES USED - * - *---------------------------------------------------------------------------- - */ - - -#include "AGESA.h" -#include "OptionMemory.h" -#include "mm.h" -#include "mn.h" -#include "mt.h" -#include "Ids.h" -#include "Filecode.h" -CODE_GROUP (G2_PEI) -RDATA_GROUP (G2_PEI) - -#define FILECODE PROC_MEM_FEAT_EXCLUDIMM_MFDIMMEXCLUD_FILECODE - -/*---------------------------------------------------------------------------- - * DEFINITIONS AND MACROS - * - *---------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------- - * TYPEDEFS AND STRUCTURES - * - *---------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------- - * PROTOTYPES OF LOCAL FUNCTIONS - * - *---------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------- - * EXPORTED FUNCTIONS - * - *---------------------------------------------------------------------------- - */ -BOOLEAN -MemFRASExcludeDIMM ( - IN OUT MEM_NB_BLOCK *NBPtr - ); - -/* -----------------------------------------------------------------------------*/ -/** - * - * Check and disable Chip selects that fail training for each node. - * - * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK - * - * @return TRUE - This feature is enabled. - * @return FALSE - This feature is not enabled. - */ -BOOLEAN -MemFRASExcludeDIMM ( - IN OUT MEM_NB_BLOCK *NBPtr - ) -{ - UINT8 Dct; - UINT8 ReserveDCT; - UINT8 q; - BOOLEAN Flag; - BOOLEAN IsCSIntlvEnabled; - UINT16 CsTestFail; - DIE_STRUCT *MCTPtr; - BOOLEAN RetVal; - - ASSERT (NBPtr != NULL); - ReserveDCT = NBPtr->Dct; - CsTestFail = 0; - for (Dct = 0; Dct < NBPtr->DctCount; Dct++) { - NBPtr->SwitchDCT (NBPtr, Dct); - if (NBPtr->DCTPtr->Timings.CsTestFail != 0) { - // When there is no new failed dimm that needs to be excluded, then no need to go through the process. - switch (NBPtr->SharedPtr->DimmExcludeFlag) { - case NORMAL: - // See there is new dimm that needs to be excluded - if ((NBPtr->DCTPtr->Timings.CsTestFail & NBPtr->DCTPtr->Timings.CsEnabled) != 0) { - CsTestFail |= NBPtr->DCTPtr->Timings.CsTestFail; - } - break; - case TRAINING: - // Do not do any dimm excluding during training - // Dimm exclude will be done at the end of training - break; - case END_TRAINING: - // Exclude all dimms that have failures during training - if ((NBPtr->DCTPtr->Timings.CsTrainFail != 0) || - ((NBPtr->DCTPtr->Timings.CsTestFail & NBPtr->DCTPtr->Timings.CsEnabled) != 0)) { - CsTestFail |= NBPtr->DCTPtr->Timings.CsTestFail; - } - break; - default: - IDS_ERROR_TRAP; - } - } - } - - if (CsTestFail != 0) { - IsCSIntlvEnabled = FALSE; - MCTPtr = NBPtr->MCTPtr; - MCTPtr->NodeMemSize = 0; - NBPtr->SharedPtr->NodeMap[NBPtr->Node].IsValid = FALSE; - NBPtr->SharedPtr->NodeMap[NBPtr->Node].SysBase = 0; - NBPtr->SharedPtr->NodeMap[NBPtr->Node].SysLimit = 0; - NBPtr->SetBitField (NBPtr, BFDramBaseAddr, 0); - NBPtr->SetBitField (NBPtr, BFDramLimitAddr, 0); - - if (MCTPtr->GangedMode) { - // if ganged mode, disable all pairs of CS that fail. - NBPtr->DCTPtr->Timings.CsTestFail |= CsTestFail; - } - - // if chip select interleaving has been enabled, need to undo it before remapping memory - if (NBPtr->FeatPtr->UndoInterleaveBanks (NBPtr)) { - IsCSIntlvEnabled = TRUE; - } - - Flag = TRUE; - NBPtr->FamilySpecificHook[BfAfExcludeDimm] (NBPtr, &Flag); - for (Dct = 0; Dct < NBPtr->DctCount; Dct++) { - NBPtr->SwitchDCT (NBPtr, Dct); - if (!MCTPtr->GangedMode || (MCTPtr->Dct == 0)) { - if (NBPtr->DCTPtr->Timings.DctMemSize != 0) { - NBPtr->DCTPtr->Timings.DctMemSize = 0; - - NBPtr->DCTPtr->Timings.CsEnabled = 0; - for (q = 0; q < MAX_CS_PER_CHANNEL; q++) { - NBPtr->SetBitField (NBPtr, BFCSBaseAddr0Reg + q, 0); - } - - Flag = NBPtr->StitchMemory (NBPtr); - ASSERT (Flag == TRUE); - } - } - } - Flag = FALSE; - NBPtr->FamilySpecificHook[BfAfExcludeDimm] (NBPtr, &Flag); - - // Re-enable chip select interleaving when remapping is done. - if (IsCSIntlvEnabled) { - NBPtr->FeatPtr->InterleaveBanks (NBPtr); - } - - RetVal = TRUE; - } else { - RetVal = FALSE; - } - NBPtr->SwitchDCT (NBPtr, ReserveDCT); - return RetVal; -} - diff --git a/src/vendorcode/amd/agesa/f12/Proc/Mem/Feat/IDENDIMM/Makefile.inc b/src/vendorcode/amd/agesa/f12/Proc/Mem/Feat/IDENDIMM/Makefile.inc deleted file mode 100644 index 8f98ec3c1b..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/Mem/Feat/IDENDIMM/Makefile.inc +++ /dev/null @@ -1 +0,0 @@ -libagesa-y += mfidendimm.c diff --git a/src/vendorcode/amd/agesa/f12/Proc/Mem/Feat/IDENDIMM/mfidendimm.c b/src/vendorcode/amd/agesa/f12/Proc/Mem/Feat/IDENDIMM/mfidendimm.c deleted file mode 100644 index 02f56309c7..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/Mem/Feat/IDENDIMM/mfidendimm.c +++ /dev/null @@ -1,537 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * mfidendimm.c - * - * Translate physical system address to dimm identification. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: (Mem/Feat) - * @e \$Revision: 45911 $ @e \$Date: 2011-01-25 04:55:11 +0800 (Tue, 25 Jan 2011) $ - * - **/ -/***************************************************************************** -* -* Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* *************************************************************************** -* -*/ - -/* - *---------------------------------------------------------------------------- - * MODULES USED - * - *---------------------------------------------------------------------------- - */ - - - -#include "AGESA.h" -#include "amdlib.h" -#include "mm.h" -#include "mn.h" -#include "Ids.h" -#include "OptionMemory.h" -#include "heapManager.h" -#include "mfidendimm.h" -#include "GeneralServices.h" -#include "Filecode.h" -CODE_GROUP (G2_PEI) -RDATA_GROUP (G2_PEI) - -#define FILECODE PROC_MEM_FEAT_IDENDIMM_MFIDENDIMM_FILECODE -extern MEM_NB_SUPPORT memNBInstalled[]; - -/*---------------------------------------------------------------------------- - * DEFINITIONS AND MACROS - * - *---------------------------------------------------------------------------- - */ -#define MAX_DCTS_PER_DIE 2 ///< Max DCTs per die -#define MAX_CHLS_PER_DCT 1 ///< Max Channels per DCT - -/*---------------------------------------------------------------------------- - * TYPEDEFS AND STRUCTURES - * - *---------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------- - * PROTOTYPES OF LOCAL FUNCTIONS - * - *---------------------------------------------------------------------------- - */ -AGESA_STATUS -STATIC -MemFTransSysAddrToCS ( - IN OUT AMD_IDENTIFY_DIMM *AmdDimmIdentify, - IN MEM_MAIN_DATA_BLOCK *mmPtr - ); - -UINT32 -STATIC -MemFGetPCI ( - IN MEM_NB_BLOCK *NBPtr, - IN UINT8 NodeID, - IN UINT8 DctNum, - IN BIT_FIELD_NAME BitFieldName - ); - -UINT8 -STATIC -MemFUnaryXOR ( - IN UINT32 address - ); - -/*---------------------------------------------------------------------------- - * EXPORTED FUNCTIONS - * - *---------------------------------------------------------------------------- - */ -/*-----------------------------------------------------------------------------*/ -/** -* -* This function identifies the dimm on which the given memory address locates. -* -* @param[in, out] *AmdDimmIdentify - Pointer to the parameter structure AMD_IDENTIFY_DIMM -* -* @retval AGESA_SUCCESS - Successfully translate physical system address -* to dimm identification. -* AGESA_BOUNDS_CHK - Targeted address is out of bound. -* -*/ - -AGESA_STATUS -AmdIdentifyDimm ( - IN OUT AMD_IDENTIFY_DIMM *AmdDimmIdentify - ) -{ - UINT8 i; - AGESA_STATUS RetVal; - MEM_MAIN_DATA_BLOCK mmData; // Main Data block - MEM_NB_BLOCK *NBPtr; - MEM_DATA_STRUCT MemData; - LOCATE_HEAP_PTR LocHeap; - ALLOCATE_HEAP_PARAMS AllocHeapParams; - UINT8 Node; - UINT8 Dct; - UINT8 Die; - UINT8 DieCount; - - LibAmdMemCopy (&(MemData.StdHeader), &(AmdDimmIdentify->StdHeader), sizeof (AMD_CONFIG_PARAMS), &(AmdDimmIdentify->StdHeader)); - mmData.MemPtr = &MemData; - RetVal = MemSocketScan (&mmData); - if (RetVal == AGESA_FATAL) { - return RetVal; - } - DieCount = mmData.DieCount; - - // Search for AMD_MEM_AUTO_HANDLE on the heap first. - // Only apply for space on the heap if cannot find AMD_MEM_AUTO_HANDLE on the heap. - LocHeap.BufferHandle = AMD_MEM_AUTO_HANDLE; - if (HeapLocateBuffer (&LocHeap, &AmdDimmIdentify->StdHeader) == AGESA_SUCCESS) { - // NB block has already been constructed by main block. - // No need to construct it here. - NBPtr = (MEM_NB_BLOCK *)LocHeap.BufferPtr; - mmData.NBPtr = NBPtr; - } else { - AllocHeapParams.RequestedBufferSize = (DieCount * (sizeof (MEM_NB_BLOCK))); - AllocHeapParams.BufferHandle = AMD_MEM_AUTO_HANDLE; - AllocHeapParams.Persist = HEAP_SYSTEM_MEM; - if (HeapAllocateBuffer (&AllocHeapParams, &AmdDimmIdentify->StdHeader) != AGESA_SUCCESS) { - PutEventLog (AGESA_FATAL, MEM_ERROR_HEAP_ALLOCATE_FOR_IDENTIFY_DIMM_MEM_NB_BLOCK, 0, 0, 0, 0, &AmdDimmIdentify->StdHeader); - ASSERT(FALSE); // Could not allocate heap space for NB block for Identify DIMM - return AGESA_FATAL; - } - NBPtr = (MEM_NB_BLOCK *)AllocHeapParams.BufferPtr; - mmData.NBPtr = NBPtr; - // Construct each die. - for (Die = 0; Die < DieCount; Die ++) { - i = 0; - while (memNBInstalled[i].MemIdentifyDimmConstruct != 0) { - if (memNBInstalled[i].MemIdentifyDimmConstruct (&NBPtr[Die], &MemData, Die)) { - break; - } - i++; - }; - if (memNBInstalled[i].MemIdentifyDimmConstruct == 0) { - PutEventLog (AGESA_FATAL, MEM_ERROR_NO_CONSTRUCTOR_FOR_IDENTIFY_DIMM, Die, 0, 0, 0, &AmdDimmIdentify->StdHeader); - ASSERT(FALSE); // No Identify DIMM constructor found - return AGESA_FATAL; - } - } - } - - if ((RetVal = MemFTransSysAddrToCS (AmdDimmIdentify, &mmData)) == AGESA_SUCCESS) { - // Translate Node, DCT and Chip select number to Socket, Channel and Dimm number. - Node = AmdDimmIdentify->SocketId; - Dct = AmdDimmIdentify->MemChannelId; - AmdDimmIdentify->SocketId = MemData.DiesPerSystem[Node].SocketId; - AmdDimmIdentify->MemChannelId = NBPtr[Node].GetSocketRelativeChannel (&NBPtr[Node], Dct, 0); - AmdDimmIdentify->DimmId /= 2; - } - - return RetVal; -} - - -/*---------------------------------------------------------------------------- - * LOCAL FUNCTIONS - * - *---------------------------------------------------------------------------- - */ - -/*-----------------------------------------------------------------------------*/ -/** -* -* This function translates the given physical system address to -* a node, channel select, chip select, bank, row, and column address. -* -* @param[in, out] *AmdDimmIdentify - Pointer to the parameter structure AMD_IDENTIFY_DIMM -* @param[in, out] *mmPtr - Pointer to the MEM_MAIN_DATA_BLOCK -* -* @retval AGESA_SUCCESS - The chip select address is found -* @retval AGESA_BOUNDS_CHK - Targeted address is out of bound. -* -*/ -AGESA_STATUS -STATIC -MemFTransSysAddrToCS ( - IN OUT AMD_IDENTIFY_DIMM *AmdDimmIdentify, - IN MEM_MAIN_DATA_BLOCK *mmPtr - ) -{ - BOOLEAN CSFound; - BOOLEAN DctSelHiRngEn; - BOOLEAN DctSelIntLvEn; - BOOLEAN DctGangEn; - BOOLEAN HiRangeSelected; - BOOLEAN DramHoleValid; - BOOLEAN CSEn; - BOOLEAN SwapDone; - BOOLEAN IntLvRgnSwapEn; - UINT8 DctSelHi; - UINT8 DramEn; - UINT8 range; - UINT8 IntlvEn; - UINT8 IntlvSel; - UINT8 ILog; - UINT8 DctSelIntLvAddr; - UINT8 DctNum; - UINT8 cs; - UINT8 BadDramCs; - UINT8 spare; - UINT8 IntLvRgnBaseAddr; - UINT8 IntLvRgnLmtAddr; - UINT8 IntLvRgnSize; - UINT32 temp; - UINT32 DramHoleOffset; - UINT32 DramHoleBase; - UINT64 DramBase; - UINT64 DramLimit; - UINT64 DramLimitSysAddr; - UINT64 DctSelBaseAddr; - UINT64 DctSelBaseOffset; - UINT64 ChannelAddr; - UINT64 CSBase; - UINT64 CSMask; - UINT64 InputAddr; - UINT64 ChannelOffset; - MEM_NB_BLOCK *NBPtr; - - UINT64 SysAddr; - UINT8 *NodeID; - UINT8 *ChannelSelect; - UINT8 *ChipSelect; - - SysAddr = AmdDimmIdentify->MemoryAddress; - NodeID = &(AmdDimmIdentify->SocketId); - ChannelSelect = &(AmdDimmIdentify->MemChannelId); - ChipSelect = &(AmdDimmIdentify->DimmId); - CSFound = FALSE; - ILog = 0; - NBPtr = mmPtr->NBPtr; - - // Loop to determine the dram range - for (range = 0; range < mmPtr->DieCount; range ++) { - // DRAM Base - temp = MemFGetPCI (NBPtr, 0, 0, BFDramBaseReg0 + range); - DramEn = (UINT8) (temp & 0x3); - IntlvEn = (UINT8) ((temp >> 8) & 0x7); - - DramBase = ((UINT64) (MemFGetPCI (NBPtr, 0, 0, BFDramBaseHiReg0 + range) & 0xFF) << 40) | - (((UINT64) temp & 0xFFFF0000) << 8); - - // DRAM Limit - temp = MemFGetPCI (NBPtr, 0, 0, BFDramLimitReg0 + range); - *NodeID = (UINT8) (temp & 0x7); - IntlvSel = (UINT8) ((temp >> 8) & 0x7); - DramLimit = ((UINT64) (MemFGetPCI (NBPtr, 0, 0, BFDramLimitHiReg0 + range) & 0xFF) << 40) | - (((UINT64) temp << 8) | 0xFFFFFF); - DramLimitSysAddr = (((UINT64) MemFGetPCI (NBPtr, *NodeID, 0, BFDramLimitAddr)) << 27) | 0x7FFFFFF; - ASSERT (DramLimit <= DramLimitSysAddr); - - if ((DramEn != 0) && (DramBase <= SysAddr) && (SysAddr <= DramLimitSysAddr) && - ((IntlvEn == 0) || (IntlvSel == ((SysAddr >> 12) & IntlvEn)))) { - // Determine the number of bit positions consumed by Node Interleaving - switch (IntlvEn) { - - case 0x0: - ILog = 0; - break; - - case 0x1: - ILog = 1; - break; - - case 0x3: - ILog = 2; - break; - - case 0x7: - ILog = 3; - break; - - default: - IDS_ERROR_TRAP; - } - - DramHoleOffset = MemFGetPCI (NBPtr, *NodeID, 0, BFDramHoleOffset) << 23; - DramHoleValid = (BOOLEAN) MemFGetPCI (NBPtr, *NodeID, 0, BFDramHoleValid); - DramHoleBase = MemFGetPCI (NBPtr, *NodeID, 0, BFDramHoleBase) << 24; - // Address belongs to this node based on DramBase/Limit, - // but is in the memory hole so it doesn't map to DRAM - if (DramHoleValid && (DramHoleBase <= SysAddr) && (SysAddr < 0x100000000ull)) { - return AGESA_BOUNDS_CHK; - } - - // F2x10C Swapped Interleaved Region - IntLvRgnSwapEn = (BOOLEAN) MemFGetPCI (NBPtr, *NodeID, 0, BFIntLvRgnSwapEn); - if (IntLvRgnSwapEn) { - IntLvRgnBaseAddr = (UINT8) MemFGetPCI (NBPtr, *NodeID, 0, BFIntLvRgnBaseAddr); - IntLvRgnLmtAddr = (UINT8) MemFGetPCI (NBPtr, *NodeID, 0, BFIntLvRgnLmtAddr); - IntLvRgnSize = (UINT8) MemFGetPCI (NBPtr, *NodeID, 0, BFIntLvRgnSize); - ASSERT (IntLvRgnSize == (IntLvRgnLmtAddr - IntLvRgnBaseAddr + 1)); - if (((SysAddr >> 34) == 0) && - ((((SysAddr >> 27) >= IntLvRgnBaseAddr) && ((SysAddr >> 27) <= IntLvRgnLmtAddr)) - || ((SysAddr >> 27) < IntLvRgnSize))) { - SysAddr ^= (UINT64) IntLvRgnBaseAddr << 27; - } - } - - // Extract variables from F2x110 DRAM Controller Select Low Register - DctSelHiRngEn = (BOOLEAN) MemFGetPCI (NBPtr, *NodeID, 0, BFDctSelHiRngEn); - DctSelHi = (UINT8) MemFGetPCI (NBPtr, *NodeID, 0, BFDctSelHi); - DctSelIntLvEn = (BOOLEAN) MemFGetPCI (NBPtr, *NodeID, 0, BFDctSelIntLvEn); - DctGangEn = (BOOLEAN) MemFGetPCI (NBPtr, *NodeID, 0, BFDctGangEn); - DctSelIntLvAddr = (UINT8) MemFGetPCI (NBPtr, *NodeID, 0, BFDctSelIntLvAddr); - DctSelBaseAddr = (UINT64) MemFGetPCI (NBPtr, *NodeID, 0, BFDctSelBaseAddr) << 27; - DctSelBaseOffset = (UINT64) MemFGetPCI (NBPtr, *NodeID, 0, BFDctSelBaseOffset) << 26; - - - // Determine if high DCT address range is being selected - if (DctSelHiRngEn && !DctGangEn && (SysAddr >= DctSelBaseAddr)) { - HiRangeSelected = TRUE; - } else { - HiRangeSelected = FALSE; - } - - // Determine Channel - if (DctGangEn) { - *ChannelSelect = (UINT8) ((SysAddr >> 3) & 0x1); - } else if (HiRangeSelected) { - *ChannelSelect = DctSelHi; - } else if (DctSelIntLvEn && (DctSelIntLvAddr == 0)) { - *ChannelSelect = (UINT8) ((SysAddr >> 6) & 0x1); - } else if (DctSelIntLvEn && (((DctSelIntLvAddr >> 1) & 0x1) != 0)) { - temp = MemFUnaryXOR ((UINT32) ((SysAddr >> 16) & 0x1F)); - if ((DctSelIntLvAddr & 0x1) != 0) { - *ChannelSelect = (UINT8) (((SysAddr >> 9) & 0x1) ^ temp); - } else { - *ChannelSelect = (UINT8) (((SysAddr >> 6) & 0x1) ^ temp); - } - } else if (DctSelIntLvEn) { - *ChannelSelect = (UINT8) ((SysAddr >> (12 + ILog)) & 0x1); - } else if (DctSelHiRngEn) { - *ChannelSelect = ~DctSelHi & 0x1; - } else { - *ChannelSelect = 0; - } - ASSERT (*ChannelSelect < NBPtr[*NodeID].DctCount); - - // Determine base address offset - if (HiRangeSelected) { - if ((DctSelBaseAddr < DramHoleBase) && DramHoleValid && (SysAddr >= 0x100000000ull)) { - ChannelOffset = (UINT64) DramHoleOffset; - } else { - ChannelOffset = DctSelBaseOffset; - } - } else { - if (DramHoleValid && (SysAddr >= 0x100000000ull)) { - ChannelOffset = (UINT64) DramHoleOffset; - } else { - ChannelOffset = DramBase; - } - } - - // Remove hoisting offset and normalize to DRAM bus addresses - ChannelAddr = SysAddr - ChannelOffset; - - // Remove node interleaving - if (IntlvEn != 0) { - ChannelAddr = ((ChannelAddr >> (12 + ILog)) << 12) | (ChannelAddr & 0xFFF); - } - - // Remove channel interleave - if (DctSelIntLvEn && !HiRangeSelected && !DctGangEn) { - if ((DctSelIntLvAddr & 1) != 1) { - // A[6] Select or Hash 6 - ChannelAddr = ((ChannelAddr >> 7) << 6) | (ChannelAddr & 0x3F); - } else if (DctSelIntLvAddr == 1) { - // A[12] - ChannelAddr = ((ChannelAddr >> 13) << 12) | (ChannelAddr & 0xFFF); - } else { - // Hash 9 - ChannelAddr = ((ChannelAddr >> 10) << 9) | (ChannelAddr & 0x1FF); - } - } - - // Determine the Chip Select - for (cs = 0; cs < MAX_CS_PER_CHANNEL; ++ cs) { - DctNum = DctGangEn ? 0 : *ChannelSelect; - - // Obtain the CS Base - temp = MemFGetPCI (NBPtr, *NodeID, DctNum, BFCSBaseAddr0Reg + cs); - CSEn = (BOOLEAN) (temp & 0x1); - CSBase = ((UINT64) temp & NBPtr->CsRegMsk) << 8; - - // Obtain the CS Mask - CSMask = ((UINT64) MemFGetPCI (NBPtr, *NodeID, DctNum, BFCSMask0Reg + (cs >> 1)) & NBPtr->CsRegMsk) << 8; - - // Adjust the Channel Addr for easy comparison - InputAddr = ((ChannelAddr >> 8) & NBPtr->CsRegMsk) << 8; - - if (CSEn && ((InputAddr & ~CSMask) == (CSBase & ~CSMask))) { - CSFound = TRUE; - - *ChipSelect = cs; - - temp = MemFGetPCI (NBPtr, *NodeID, 0, BFOnLineSpareControl); - SwapDone = (BOOLEAN) ((temp >> (1 + 2 * (*ChannelSelect))) & 0x1); - BadDramCs = (UINT8) ((temp >> (4 + 4 * (*ChannelSelect))) & 0x7); - if (SwapDone && (cs == BadDramCs)) { - // Find the spare rank for the channel - for (spare = 0; spare < MAX_CS_PER_CHANNEL; ++spare) { - if ((MemFGetPCI (NBPtr, *NodeID, DctNum, BFCSBaseAddr0Reg + spare) & 0x2) != 0) { - *ChipSelect = spare; - break; - } - } - } - ASSERT (*ChipSelect < MAX_CS_PER_CHANNEL); - - break; - } - } - } - if (CSFound) { - break; - } - } - - // last ditch sanity check - ASSERT (!CSFound || ((*NodeID < mmPtr->DieCount) && (*ChannelSelect < NBPtr[*NodeID].DctCount) && (*ChipSelect < MAX_CS_PER_CHANNEL))); - if (CSFound) { - return AGESA_SUCCESS; - } else { - return AGESA_BOUNDS_CHK; - } - -} - - -/*-----------------------------------------------------------------------------*/ -/** -* -* This function is the interface to call the PCI register access function -* defined in NB block. -* -* @param[in] *NBPtr - Pointer to the parameter structure MEM_NB_BLOCK -* @param[in] NodeID - Node ID number of the target Northbridge -* @param[in] DctNum - DCT number if applicable, otherwise, put 0 -* @param[in] BitFieldName - targeted bitfield -* -* @retval UINT32 - 32 bits PCI register value -* -*/ -UINT32 -STATIC -MemFGetPCI ( - IN MEM_NB_BLOCK *NBPtr, - IN UINT8 NodeID, - IN UINT8 DctNum, - IN BIT_FIELD_NAME BitFieldName - ) -{ - MEM_NB_BLOCK *LocalNBPtr; - // Get the northbridge pointer for the targeted node. - LocalNBPtr = &NBPtr[NodeID]; - LocalNBPtr->FamilySpecificHook[DCTSelectSwitch] (LocalNBPtr, &DctNum); - LocalNBPtr->Dct = DctNum; - // The caller of this function will take care of the ganged/unganged situation. - // So Ganged is set to be false here, and do PCI read on the DCT specified by DctNum. - return LocalNBPtr->GetBitField (LocalNBPtr, BitFieldName); -} - -/*-----------------------------------------------------------------------------*/ -/** -* -* This function returns an even parity bit (making the total # of 1's even) -* {0, 1} = number of set bits in argument is {even, odd}. -* -* @param[in] address - the address on which the parity bit will be calculated -* -* @retval UINT8 - parity bit -* -*/ - -UINT8 -STATIC -MemFUnaryXOR ( - IN UINT32 address - ) -{ - UINT8 parity; - UINT8 index; - parity = 0; - for (index = 0; index < 32; ++ index) { - parity = (UINT8) (parity ^ (address & 0x1)); - address = address >> 1; - } - return parity; -} diff --git a/src/vendorcode/amd/agesa/f12/Proc/Mem/Feat/IDENDIMM/mfidendimm.h b/src/vendorcode/amd/agesa/f12/Proc/Mem/Feat/IDENDIMM/mfidendimm.h deleted file mode 100644 index 870763c8de..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/Mem/Feat/IDENDIMM/mfidendimm.h +++ /dev/null @@ -1,107 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * mfidendimm.h - * - * Header file for address to dimm identification translator. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: (Mem) - * @e \$Revision: 45911 $ @e \$Date: 2011-01-25 04:55:11 +0800 (Tue, 25 Jan 2011) $ - * - **/ -/***************************************************************************** -* -* Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* *************************************************************************** -* -*/ - -#ifndef _MFIDENDIMM_H_ -#define _MFIDENDIMM_H_ - -/*---------------------------------------------------------------------------- - * Mixed (DEFINITIONS AND MACROS / TYPEDEFS, STRUCTURES, ENUMS) - * - *---------------------------------------------------------------------------- - */ - -/*----------------------------------------------------------------------------- - * DEFINITIONS AND MACROS - * - *----------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------- - * TYPEDEFS, STRUCTURES, ENUMS - * - *---------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------- - * FUNCTIONS PROTOTYPE - * - *---------------------------------------------------------------------------- - */ - -BOOLEAN -MemNIdentifyDimmConstructorDr ( - IN OUT MEM_NB_BLOCK *NBPtr, - IN OUT MEM_DATA_STRUCT *MemPtr, - IN UINT8 NodeID - ); - -BOOLEAN -MemNIdentifyDimmConstructorDA ( - IN OUT MEM_NB_BLOCK *NBPtr, - IN OUT MEM_DATA_STRUCT *MemPtr, - IN UINT8 NodeID - ); - -BOOLEAN -MemNIdentifyDimmConstructorHy ( - IN OUT MEM_NB_BLOCK *NBPtr, - IN OUT MEM_DATA_STRUCT *MemPtr, - IN UINT8 NodeID - ); - -BOOLEAN -MemNIdentifyDimmConstructorC32 ( - IN OUT MEM_NB_BLOCK *NBPtr, - IN OUT MEM_DATA_STRUCT *MemPtr, - IN UINT8 NodeID - ); - -BOOLEAN -MemNIdentifyDimmConstructorLN ( - IN OUT MEM_NB_BLOCK *NBPtr, - IN OUT MEM_DATA_STRUCT *MemPtr, - IN UINT8 NodeID - ); - -#endif //_MFIDENDIMM_H_ diff --git a/src/vendorcode/amd/agesa/f12/Proc/Mem/Feat/INTLVRN/Makefile.inc b/src/vendorcode/amd/agesa/f12/Proc/Mem/Feat/INTLVRN/Makefile.inc deleted file mode 100644 index d9fca46951..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/Mem/Feat/INTLVRN/Makefile.inc +++ /dev/null @@ -1 +0,0 @@ -libagesa-y += mfintlvrn.c diff --git a/src/vendorcode/amd/agesa/f12/Proc/Mem/Feat/INTLVRN/mfintlvrn.c b/src/vendorcode/amd/agesa/f12/Proc/Mem/Feat/INTLVRN/mfintlvrn.c deleted file mode 100644 index f04d119681..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/Mem/Feat/INTLVRN/mfintlvrn.c +++ /dev/null @@ -1,163 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * mfrintlv.c - * - * Feature Region interleaving support - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: (Mem/Feat/Intlvrgn) - * @e \$Revision: 49831 $ @e \$Date: 2011-03-30 00:26:15 +0800 (Wed, 30 Mar 2011) $ - * - **/ -/***************************************************************************** - * - * Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * *************************************************************************** - * - */ - - -/* - *---------------------------------------------------------------------------- - * MODULES USED - * - *---------------------------------------------------------------------------- - */ - - - -#include "AGESA.h" -#include "amdlib.h" -#include "heapManager.h" -#include "mport.h" -#include "mm.h" -#include "mn.h" -#include "mfintlvrn.h" -#include "Ids.h" -#include "Filecode.h" -CODE_GROUP (G2_PEI) -RDATA_GROUP (G2_PEI) - -#define FILECODE PROC_MEM_FEAT_INTLVRN_MFINTLVRN_FILECODE -/*---------------------------------------------------------------------------- - * DEFINITIONS AND MACROS - * - *---------------------------------------------------------------------------- - */ -#define _4GB_RJ27 ((UINT32)4 << (30 - 27)) -/*---------------------------------------------------------------------------- - * TYPEDEFS AND STRUCTURES - * - *---------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------- - * PROTOTYPES OF LOCAL FUNCTIONS - * - *---------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------- - * EXPORTED FUNCTIONS - * - *---------------------------------------------------------------------------- - */ - -/* -----------------------------------------------------------------------------*/ -/** - * - * MemFInterleaveRegion: - * - * Applies region interleaving if both DCTs have different size of memory, and - * the channel interleaving region doesn't have UMA covered. - * - * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK - * - */ - -VOID -MemFInterleaveRegion ( - IN OUT MEM_NB_BLOCK *NBPtr - ) -{ - UINT32 TOM; - UINT32 TOM2; - UINT32 TOMused; - UINT32 UmaBase; - UINT32 DctSelBase; - S_UINT64 SMsr; - LOCATE_HEAP_PTR LocHeap; - UMA_INFO *UmaInfoPtr; - - MEM_DATA_STRUCT *MemPtr; - MEM_PARAMETER_STRUCT *RefPtr; - DIE_STRUCT *MCTPtr; - - MemPtr = NBPtr->MemPtr; - RefPtr = NBPtr->RefPtr; - MCTPtr = NBPtr->MCTPtr; - - UmaBase = (UINT32) RefPtr->UmaBase >> (27 - 16); - - //TOM scaled from [47:0] to [47:27] - LibAmdMsrRead (TOP_MEM, (UINT64 *)&SMsr, &MemPtr->StdHeader); - SMsr.lo += (16 << 20); // Add 16MB to gain back C6 region if C6 is enabled - TOM = (SMsr.lo >> 27) | (SMsr.hi << (32 - 27)); - - //TOM2 scaled from [47:0] to [47:27] - LibAmdMsrRead (TOP_MEM2, (UINT64 *)&SMsr, &MemPtr->StdHeader); - TOM2 = (SMsr.lo >> 27) | (SMsr.hi << (32 - 27)); - - TOMused = (UmaBase >= _4GB_RJ27) ? TOM2 : TOM; - - if (UmaBase != 0) { - //Check if channel interleaving is enabled ? if so, go to next step. - if (NBPtr->GetBitField (NBPtr, BFDctSelIntLvEn) == 1) { - DctSelBase = NBPtr->GetBitField (NBPtr, BFDctSelBaseAddr); - //Skip if DctSelBase is equal to 0, because DCT0 has as the same memory size as DCT1. - if (DctSelBase != 0) { - //We need not enable swapped interleaved region when channel interleaving region has covered all of the UMA. - if (DctSelBase < TOMused) { - NBPtr->EnableSwapIntlvRgn (NBPtr, UmaBase, TOMused); - - // Set UMA attribute to interleaved after interleaved region has been swapped - LocHeap.BufferHandle = AMD_UMA_INFO_HANDLE; - if (HeapLocateBuffer (&LocHeap, &(NBPtr->MemPtr->StdHeader)) == AGESA_SUCCESS) { - UmaInfoPtr = (UMA_INFO *) LocHeap.BufferPtr; - UmaInfoPtr->UmaAttributes = UMA_ATTRIBUTE_INTERLEAVE | UMA_ATTRIBUTE_ON_DCT0 | UMA_ATTRIBUTE_ON_DCT1; - } else { - ASSERT (FALSE); - } - } - } - } - } -} - - diff --git a/src/vendorcode/amd/agesa/f12/Proc/Mem/Feat/INTLVRN/mfintlvrn.h b/src/vendorcode/amd/agesa/f12/Proc/Mem/Feat/INTLVRN/mfintlvrn.h deleted file mode 100644 index 364d0f2db0..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/Mem/Feat/INTLVRN/mfintlvrn.h +++ /dev/null @@ -1,80 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * mfintlvrn.h - * - * Feature region interleaving - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: (Mem) - * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $ - * - **/ -/***************************************************************************** - * - * Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * *************************************************************************** - * - */ - - -#ifndef _MFINTLVRN_H_ -#define _MFINTLVRN_H_ - -/*---------------------------------------------------------------------------- - * Mixed (DEFINITIONS AND MACROS / TYPEDEFS, STRUCTURES, ENUMS) - * - *---------------------------------------------------------------------------- - */ - -/*----------------------------------------------------------------------------- - * DEFINITIONS AND MACROS - * - *----------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------- - * TYPEDEFS, STRUCTURES, ENUMS - * - *---------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------- - * FUNCTIONS PROTOTYPE - * - *---------------------------------------------------------------------------- - */ - -VOID -MemFInterleaveRegion ( - IN OUT MEM_NB_BLOCK *NBPtr - ); - -#endif /* _MFINTLVRN_H_ */ - - diff --git a/src/vendorcode/amd/agesa/f12/Proc/Mem/Feat/LVDDR3/Makefile.inc b/src/vendorcode/amd/agesa/f12/Proc/Mem/Feat/LVDDR3/Makefile.inc deleted file mode 100644 index 436ceb372c..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/Mem/Feat/LVDDR3/Makefile.inc +++ /dev/null @@ -1 +0,0 @@ -libagesa-y += mflvddr3.c diff --git a/src/vendorcode/amd/agesa/f12/Proc/Mem/Feat/LVDDR3/mflvddr3.c b/src/vendorcode/amd/agesa/f12/Proc/Mem/Feat/LVDDR3/mflvddr3.c deleted file mode 100644 index f4f90daafe..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/Mem/Feat/LVDDR3/mflvddr3.c +++ /dev/null @@ -1,172 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * lvddr3.c - * - * Voltage change for DDR3 DIMMs. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: (Mem/Feat/LVDDR3) - * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $ - * - **/ -/***************************************************************************** -* -* Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* *************************************************************************** -* -*/ - -/* - *---------------------------------------------------------------------------- - * MODULES USED - * - *---------------------------------------------------------------------------- - */ - - - -#include "AGESA.h" -#include "amdlib.h" -#include "Ids.h" -#include "mm.h" -#include "mn.h" -#include "mt.h" -#include "Filecode.h" -CODE_GROUP (G2_PEI) -RDATA_GROUP (G2_PEI) - -#define FILECODE PROC_MEM_FEAT_LVDDR3_MFLVDDR3_FILECODE -/* features */ -#include "mflvddr3.h" - - -/*---------------------------------------------------------------------------- - * DEFINITIONS AND MACROS - * - *---------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------- - * TYPEDEFS AND STRUCTURES - * - *---------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------- - * PROTOTYPES OF LOCAL FUNCTIONS - * - *---------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------- - * EXPORTED FUNCTIONS - * - *---------------------------------------------------------------------------- - */ - -/*-----------------------------------------------------------------------------*/ -/** - * - * This function calculate the common lowest voltage supported by all DDR3 - * DIMMs in the system. This function only needs to be called on BSP. - * - * @param[in, out] *NBPtr - Pointer to NB block - * - * @return TRUE - This feature is enabled. - * @return FALSE - This feature is not enabled. - */ - -BOOLEAN -MemFLvDdr3 ( - IN OUT MEM_NB_BLOCK *NBPtr - ) -{ - CH_DEF_STRUCT *ChannelPtr; - MEM_TECH_BLOCK *TechPtr; - MEM_SHARED_DATA *mmSharedPtr; - UINT8 Dct; - UINT8 Channel; - UINT8 Dimm; - UINT8 *SpdBufferPtr; - UINT8 VDDByte; - UINT8 VoltageMap; - - mmSharedPtr = NBPtr->SharedPtr; - TechPtr = NBPtr->TechPtr; - VoltageMap = 0xFF; - - for (Dct = 0; Dct < NBPtr->DctCount; Dct++) { - NBPtr->SwitchDCT (NBPtr, Dct); - for (Channel = 0; Channel < NBPtr->ChannelCount; Channel++) { - NBPtr->SwitchChannel (NBPtr, Channel); - ChannelPtr = NBPtr->ChannelPtr; - for (Dimm = 0; Dimm < MAX_DIMMS_PER_CHANNEL; Dimm++) { - if (TechPtr->GetDimmSpdBuffer (TechPtr, &SpdBufferPtr, Dimm)) { - // SPD byte 6: Module Nominal Voltage, VDD - // 1.5v - bit 0 - // 1.35v - bit 1 - // 1.2v - bit 2 - VDDByte = SpdBufferPtr[MNVVDD]; - IDS_HDT_CONSOLE (MEM_FLOW, "Node%d DCT%d Channel%d Dimm%d VDD Byte: 0x%02x\n", NBPtr->Node, Dct, Channel, Dimm, VDDByte); - - // Reverse the 1.5V operable bit. So its encoding can be consistent - // with that of 1.35V and 1.25V operable bit. - VDDByte ^= 1; - ASSERT (VDDByte != 0); - - if (mmSharedPtr->VoltageMap != 0) { - // Get the common supported voltage map - VoltageMap &= VDDByte; - } else { - // This is the second execution of all the loop as no common voltage is found - if (VDDByte == (1 << VOLT1_5_ENCODED_VAL)) { - // Always exclude 1.5V dimm if no common voltage is found - ChannelPtr->DimmExclude |= (UINT16) 1 << Dimm; - } - } - } - } - if (mmSharedPtr->VoltageMap == 0) { - NBPtr->DCTPtr->Timings.DimmExclude |= ChannelPtr->DimmExclude; - } - } - } - - if (mmSharedPtr->VoltageMap != 0) { - mmSharedPtr->VoltageMap &= VoltageMap; - } - - return TRUE; -} - -/*---------------------------------------------------------------------------- - * LOCAL FUNCTIONS - * - *---------------------------------------------------------------------------- - */ diff --git a/src/vendorcode/amd/agesa/f12/Proc/Mem/Feat/LVDDR3/mflvddr3.h b/src/vendorcode/amd/agesa/f12/Proc/Mem/Feat/LVDDR3/mflvddr3.h deleted file mode 100644 index b5545ca569..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/Mem/Feat/LVDDR3/mflvddr3.h +++ /dev/null @@ -1,78 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * mflvddr3.h - * - * Header file for DDR3 DIMMs voltage configuration. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: (Mem) - * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $ - * - **/ -/***************************************************************************** -* -* Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* *************************************************************************** -* -*/ - -#ifndef _MFLVDDR3_H_ -#define _MFLVDDR3_H_ - -/*---------------------------------------------------------------------------- - * Mixed (DEFINITIONS AND MACROS / TYPEDEFS, STRUCTURES, ENUMS) - * - *---------------------------------------------------------------------------- - */ - -/*----------------------------------------------------------------------------- - * DEFINITIONS AND MACROS - * - *----------------------------------------------------------------------------- - */ -#define MNVVDD 6 -#define LOWEST_VOLT_BIT 2 - -/*---------------------------------------------------------------------------- - * TYPEDEFS, STRUCTURES, ENUMS - * - *---------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------- - * FUNCTIONS PROTOTYPE - * - *---------------------------------------------------------------------------- - */ -BOOLEAN -MemFLvDdr3 ( - IN OUT MEM_NB_BLOCK *NBPtr -); - -#endif //_MFLVDDR3_H_ diff --git a/src/vendorcode/amd/agesa/f12/Proc/Mem/Feat/MEMCLR/Makefile.inc b/src/vendorcode/amd/agesa/f12/Proc/Mem/Feat/MEMCLR/Makefile.inc deleted file mode 100644 index 94d80c7187..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/Mem/Feat/MEMCLR/Makefile.inc +++ /dev/null @@ -1 +0,0 @@ -libagesa-y += mfmemclr.c diff --git a/src/vendorcode/amd/agesa/f12/Proc/Mem/Feat/MEMCLR/mfmemclr.c b/src/vendorcode/amd/agesa/f12/Proc/Mem/Feat/MEMCLR/mfmemclr.c deleted file mode 100644 index 8ace00fa67..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/Mem/Feat/MEMCLR/mfmemclr.c +++ /dev/null @@ -1,151 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * mfmemclr.c - * - * Feature function for memory clear operation - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: (Mem/Feat/Memclr) - * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $ - * - **/ -/***************************************************************************** - * - * Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * *************************************************************************** - * - */ - - - - -#include "AGESA.h" -#include "mm.h" -#include "mn.h" -#include "mfmemclr.h" -#include "Ids.h" -#include "merrhdl.h" -#include "Filecode.h" -CODE_GROUP (G2_PEI) -RDATA_GROUP (G2_PEI) - -#define FILECODE PROC_MEM_FEAT_MEMCLR_MFMEMCLR_FILECODE -/*---------------------------------------------------------------------------- - * DEFINITIONS AND MACROS - * - *---------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------- - * TYPEDEFS AND STRUCTURES - * - *---------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------- - * PROTOTYPES OF LOCAL FUNCTIONS - * - *---------------------------------------------------------------------------- - */ - -/* - *----------------------------------------------------------------------------- - * EXPORTED FUNCTIONS - * - *----------------------------------------------------------------------------- - */ - -/* -----------------------------------------------------------------------------*/ -/** - * - * - * Initiates memory clear operation on one node with Dram on it. - * - * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK - * - */ - -BOOLEAN -MemFMctMemClr_Init ( - IN OUT MEM_NB_BLOCK *NBPtr - ) -{ - AGESA_TESTPOINT (TpProcMemMemClr, &NBPtr->MemPtr->StdHeader); - if (NBPtr->RefPtr->EnableMemClr == TRUE) { - if (NBPtr->MCTPtr->NodeMemSize != 0) { - if (!NBPtr->MemCleared) { - NBPtr->PollBitField (NBPtr, BFMemClrBusy, 0, SPECIAL_PCI_ACCESS_TIMEOUT, FALSE); - if (NBPtr->GetBitField (NBPtr, BFDramEnabled) == 1) { - NBPtr->FamilySpecificHook[BeforeMemClr] (NBPtr, NBPtr); - NBPtr->SetBitField (NBPtr, BFDramBaseAddr, 0); - NBPtr->SetBitField (NBPtr, BFMemClrInit, 1); - } - } - } - } - return TRUE; -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * - * Ensures memory clear operation has completed on one node with Dram on it. - * - * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK - * - */ - -BOOLEAN -MemFMctMemClr_Sync ( - IN OUT MEM_NB_BLOCK *NBPtr - ) -{ - UINT32 MicroSecondToWait; - - MicroSecondToWait = 0; - if (NBPtr->RefPtr->EnableMemClr == TRUE) { - if (NBPtr->MCTPtr->NodeMemSize != 0) { - // Calculate Timeout value: - // Timeout (in microsecond) = Memory Size * 1.5 ns / 8 Byte * 4 (Margin) * 1000 (change millisecond to us) - // NodeMemSize is system address right shifted by 16, so shift it 4 bits to right to convert it to MB. - // 1.5 / 8 * 4 * 1000 = 750 - MicroSecondToWait = (NBPtr->MCTPtr->NodeMemSize >> 4) * 750; - - if (!NBPtr->MemCleared) { - NBPtr->PollBitField (NBPtr, BFMemClrBusy, 0, MicroSecondToWait, FALSE); - NBPtr->PollBitField (NBPtr, BFMemCleared, 1, MicroSecondToWait, FALSE); - NBPtr->SetBitField (NBPtr, BFDramBaseAddr, NBPtr->MCTPtr->NodeSysBase >> (27 - 16)); - NBPtr->MemCleared = TRUE; - } - } - } - return TRUE; -} - diff --git a/src/vendorcode/amd/agesa/f12/Proc/Mem/Feat/ODTHERMAL/Makefile.inc b/src/vendorcode/amd/agesa/f12/Proc/Mem/Feat/ODTHERMAL/Makefile.inc deleted file mode 100644 index e1b5923668..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/Mem/Feat/ODTHERMAL/Makefile.inc +++ /dev/null @@ -1 +0,0 @@ -libagesa-y += mfodthermal.c diff --git a/src/vendorcode/amd/agesa/f12/Proc/Mem/Feat/ODTHERMAL/mfodthermal.c b/src/vendorcode/amd/agesa/f12/Proc/Mem/Feat/ODTHERMAL/mfodthermal.c deleted file mode 100644 index 4150301c94..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/Mem/Feat/ODTHERMAL/mfodthermal.c +++ /dev/null @@ -1,174 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * mfodthermal.c - * - * On Dimm thermal management. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: (Mem/Feat) - * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $ - * - **/ -/***************************************************************************** -* -* Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* *************************************************************************** -* -*/ - -/* - *---------------------------------------------------------------------------- - * MODULES USED - * - *---------------------------------------------------------------------------- - */ - - - -#include "AGESA.h" -#include "mm.h" -#include "mn.h" -#include "mt.h" -#include "Ids.h" -#include "mfodthermal.h" -#include "Filecode.h" -CODE_GROUP (G2_PEI) -RDATA_GROUP (G2_PEI) - -#define FILECODE PROC_MEM_FEAT_ODTHERMAL_MFODTHERMAL_FILECODE - -/*---------------------------------------------------------------------------- - * DEFINITIONS AND MACROS - * - *---------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------- - * TYPEDEFS AND STRUCTURES - * - *---------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------- - * PROTOTYPES OF LOCAL FUNCTIONS - * - *---------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------- - * EXPORTED FUNCTIONS - * - *---------------------------------------------------------------------------- - */ -/*-----------------------------------------------------------------------------*/ -/** - * - * This function does On-Dimm thermal management. - * - * @param[in, out] *NBPtr - Pointer to the MEM_NB_BLOCK. - * - * @return TRUE - This feature is enabled. - * @return FALSE - This feature is not enabled. - */ - -BOOLEAN -MemFOnDimmThermal ( - IN OUT MEM_NB_BLOCK *NBPtr - ) -{ - UINT8 i; - UINT8 Dct; - CH_DEF_STRUCT *ChannelPtr; - MEM_DATA_STRUCT *MemPtr; - UINT8 *SpdBufferPtr; - UINT8 ThermalOp; - BOOLEAN ODTSEn; - BOOLEAN ExtendTmp; - - ODTSEn = FALSE; - ExtendTmp = FALSE; - - ASSERT (NBPtr != NULL); - MemPtr = NBPtr->MemPtr; - AGESA_TESTPOINT (TpProcMemOnDimmThermal, &MemPtr->StdHeader); - if (NBPtr->MCTPtr->NodeMemSize != 0) { - for (Dct = 0; Dct < NBPtr->DctCount; Dct++) { - NBPtr->SwitchDCT (NBPtr, Dct); - // Only go through the DCT if it is not disabled. - if (NBPtr->GetBitField (NBPtr, BFDisDramInterface) == 0) { - ChannelPtr = NBPtr->ChannelPtr; - // If Ganged mode is enabled, need to go through all dram devices on both DCTs. - if (!NBPtr->Ganged || (NBPtr->Dct != 1)) { - if (!(NBPtr->IsSupported[CheckSetSameDctODTsEn]) || (NBPtr->IsSupported[CheckSetSameDctODTsEn] && (NBPtr->Dct != 1))) { - ODTSEn = TRUE; - ExtendTmp = TRUE; - } - } - for (i = 0; i < MAX_DIMMS_PER_CHANNEL; i ++) { - if (NBPtr->TechPtr->GetDimmSpdBuffer (NBPtr->TechPtr, &SpdBufferPtr, i)) { - // Check byte 31: thermal and refresh option. - ThermalOp = SpdBufferPtr[THERMAL_OPT]; - // Bit 3: ODTS readout - if (!((ThermalOp >> 3) & 1)) { - ODTSEn = FALSE; - } - // Bit 0: Extended Temperature Range. - if (!(ThermalOp & 1)) { - ExtendTmp = FALSE; - } - } - } - - if (!NBPtr->Ganged || (NBPtr->Dct == 1)) { - // If in ganged mode, need to switch back to DCT0 to set the registers. - if (NBPtr->Ganged || NBPtr->IsSupported[CheckSetSameDctODTsEn]) { - NBPtr->SwitchDCT (NBPtr, 0); - ChannelPtr = NBPtr->ChannelPtr; - } - // If all dram devices on a DCT support ODTS - if (ODTSEn) { - NBPtr->SetBitField (NBPtr, BFODTSEn, 1); - } - ChannelPtr->ExtendTmp = ExtendTmp; - } - } - IDS_HDT_CONSOLE (MEM_FLOW, "\tDct %d\n", Dct); - IDS_HDT_CONSOLE (MEM_FLOW, "\t\tODTSEn = %d\n", ODTSEn); - IDS_HDT_CONSOLE (MEM_FLOW, "\t\tExtendTmp = %d\n", ExtendTmp); - } - } - return TRUE; -} - - -/*---------------------------------------------------------------------------- - * LOCAL FUNCTIONS - * - *---------------------------------------------------------------------------- - */ diff --git a/src/vendorcode/amd/agesa/f12/Proc/Mem/Feat/ODTHERMAL/mfodthermal.h b/src/vendorcode/amd/agesa/f12/Proc/Mem/Feat/ODTHERMAL/mfodthermal.h deleted file mode 100644 index 0cdf270136..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/Mem/Feat/ODTHERMAL/mfodthermal.h +++ /dev/null @@ -1,77 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * mfodthermal.h - * - * Header file for On-Dimm thermal management. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: (Mem) - * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $ - * - **/ -/***************************************************************************** -* -* Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* *************************************************************************** -* -*/ - -#ifndef _MFODTHERMAL_H_ -#define _MFODTHERMAL_H_ - -/*---------------------------------------------------------------------------- - * Mixed (DEFINITIONS AND MACROS / TYPEDEFS, STRUCTURES, ENUMS) - * - *---------------------------------------------------------------------------- - */ - -/*----------------------------------------------------------------------------- - * DEFINITIONS AND MACROS - * - *----------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------- - * TYPEDEFS, STRUCTURES, ENUMS - * - *---------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------- - * FUNCTIONS PROTOTYPE - * - *---------------------------------------------------------------------------- - */ - -BOOLEAN -MemFOnDimmThermal ( - IN OUT MEM_NB_BLOCK *NBPtr - ); - -#endif //_MFODTHERMAL_H_ diff --git a/src/vendorcode/amd/agesa/f12/Proc/Mem/Feat/PARTRN/Makefile.inc b/src/vendorcode/amd/agesa/f12/Proc/Mem/Feat/PARTRN/Makefile.inc deleted file mode 100644 index 90c8566627..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/Mem/Feat/PARTRN/Makefile.inc +++ /dev/null @@ -1,2 +0,0 @@ -libagesa-y += mfParallelTraining.c -libagesa-y += mfStandardTraining.c diff --git a/src/vendorcode/amd/agesa/f12/Proc/Mem/Feat/PARTRN/mfParallelTraining.c b/src/vendorcode/amd/agesa/f12/Proc/Mem/Feat/PARTRN/mfParallelTraining.c deleted file mode 100644 index 69e207b3ed..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/Mem/Feat/PARTRN/mfParallelTraining.c +++ /dev/null @@ -1,284 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * mfParallelTraining.c - * - * This is the parallel training feature - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: (Mem/Feat/PARTRN) - * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $ - * - **/ -/***************************************************************************** - * - * Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * *************************************************************************** - * - */ - - - - -#include "AGESA.h" -#include "amdlib.h" -#include "OptionMemory.h" -#include "mm.h" -#include "mn.h" -#include "Ids.h" -#include "cpuRegisters.h" -#include "cpuApicUtilities.h" -#include "mfParallelTraining.h" -#include "heapManager.h" -#include "GeneralServices.h" -#include "Filecode.h" -CODE_GROUP (G2_PEI) -RDATA_GROUP (G2_PEI) - -#define FILECODE PROC_MEM_FEAT_PARTRN_MFPARALLELTRAINING_FILECODE - -/*----------------------------------------------------------------------------- - * EXPORTED FUNCTIONS - * - *----------------------------------------------------------------------------- - */ -extern MEM_TECH_CONSTRUCTOR* memTechInstalled[]; - -/* -----------------------------------------------------------------------------*/ -/** - * - * - * This is the main function to perform parallel training on all nodes. - * This is the routine which will run on the remote AP. - * - * @param[in,out] *EnvPtr - Pointer to the Training Environment Data - * @param[in,out] *StdHeader - Pointer to the Standard Header of the AP - * - * @return TRUE - This feature is enabled. - * @return FALSE - This feature is not enabled. - */ -BOOLEAN -MemFParallelTraining ( - IN OUT REMOTE_TRAINING_ENV *EnvPtr, - IN OUT AMD_CONFIG_PARAMS *StdHeader - ) -{ - MEM_PARAMETER_STRUCT ParameterList; - MEM_NB_BLOCK NB; - MEM_TECH_BLOCK TB; - ALLOCATE_HEAP_PARAMS AllocHeapParams; - MEM_DATA_STRUCT *MemPtr; - DIE_STRUCT *MCTPtr; - UINT8 p; - UINT8 i; - UINT8 Dct; - UINT8 Channel; - UINT8 *BufferPtr; - UINT8 DctCount; - UINT8 ChannelCount; - UINT8 RowCount; - UINT8 ColumnCount; - UINT16 SizeOfNewBuffer; - AP_DATA_TRANSFER ReturnData; - - // - // Initialize Parameters - // - ReturnData.DataPtr = NULL; - ReturnData.DataSizeInDwords = 0; - ReturnData.DataTransferFlags = 0; - - ASSERT (EnvPtr != NULL); - // - // Replace Standard header of a AP - // - LibAmdMemCopy (StdHeader, &(EnvPtr->StdHeader), sizeof (AMD_CONFIG_PARAMS), &(EnvPtr->StdHeader)); - - - // - // Allocate buffer for training data - // - BufferPtr = (UINT8 *) (&EnvPtr->DieStruct); - DctCount = EnvPtr->DieStruct.DctCount; - BufferPtr += sizeof (DIE_STRUCT); - ChannelCount = ((DCT_STRUCT *) BufferPtr)->ChannelCount; - BufferPtr += DctCount * sizeof (DCT_STRUCT); - RowCount = ((CH_DEF_STRUCT *) BufferPtr)->RowCount; - ColumnCount = ((CH_DEF_STRUCT *) BufferPtr)->ColumnCount; - - SizeOfNewBuffer = sizeof (DIE_STRUCT) + - DctCount * ( - sizeof (DCT_STRUCT) + ( - ChannelCount * ( - sizeof (CH_DEF_STRUCT) + sizeof (MEM_PS_BLOCK) + ( - RowCount * ColumnCount * NUMBER_OF_DELAY_TABLES + - (MAX_BYTELANES_PER_CHANNEL * MAX_CS_PER_CHANNEL * NUMBER_OF_FAILURE_MASK_TABLES) - ) - ) - ) - ); - AllocHeapParams.RequestedBufferSize = SizeOfNewBuffer; - AllocHeapParams.BufferHandle = GENERATE_MEM_HANDLE (ALLOC_PAR_TRN_HANDLE, 0, 0, 0); - AllocHeapParams.Persist = HEAP_LOCAL_CACHE; - if (HeapAllocateBuffer (&AllocHeapParams, StdHeader) == AGESA_SUCCESS) { - BufferPtr = AllocHeapParams.BufferPtr; - LibAmdMemCopy ( BufferPtr, - &(EnvPtr->DieStruct), - sizeof (DIE_STRUCT) + DctCount * (sizeof (DCT_STRUCT) + ChannelCount * (sizeof (CH_DEF_STRUCT) + sizeof (MEM_PS_BLOCK))), - StdHeader - ); - - // - // Fix up pointers - // - MCTPtr = (DIE_STRUCT *) BufferPtr; - BufferPtr += sizeof (DIE_STRUCT); - MCTPtr->DctData = (DCT_STRUCT *) BufferPtr; - BufferPtr += MCTPtr->DctCount * sizeof (DCT_STRUCT); - for (Dct = 0; Dct < MCTPtr->DctCount; Dct++) { - MCTPtr->DctData[Dct].ChData = (CH_DEF_STRUCT *) BufferPtr; - BufferPtr += MCTPtr->DctData[Dct].ChannelCount * sizeof (CH_DEF_STRUCT); - for (Channel = 0; Channel < MCTPtr->DctData[Dct].ChannelCount; Channel++) { - MCTPtr->DctData[Dct].ChData[Channel].MCTPtr = MCTPtr; - MCTPtr->DctData[Dct].ChData[Channel].DCTPtr = &MCTPtr->DctData[Dct]; - } - } - NB.PSBlock = (MEM_PS_BLOCK *) BufferPtr; - BufferPtr += DctCount * ChannelCount * sizeof (MEM_PS_BLOCK); - - ReturnData.DataPtr = AllocHeapParams.BufferPtr; - ReturnData.DataSizeInDwords = (SizeOfNewBuffer + 3) / 4; - ReturnData.DataTransferFlags = 0; - - // - // Allocate Memory for the MEM_DATA_STRUCT we will use - // - AllocHeapParams.RequestedBufferSize = sizeof (MEM_DATA_STRUCT); - AllocHeapParams.BufferHandle = AMD_MEM_DATA_HANDLE; - AllocHeapParams.Persist = HEAP_LOCAL_CACHE; - if (HeapAllocateBuffer (&AllocHeapParams, StdHeader) == AGESA_SUCCESS) { - MemPtr = (MEM_DATA_STRUCT *)AllocHeapParams.BufferPtr; - - LibAmdMemCopy (&(MemPtr->StdHeader), &(EnvPtr->StdHeader), sizeof (AMD_CONFIG_PARAMS), StdHeader); - - // - // Copy Parameters from environment - // - ParameterList.HoleBase = EnvPtr->HoleBase; - ParameterList.BottomIo = EnvPtr->BottomIo; - ParameterList.UmaSize = EnvPtr->UmaSize; - ParameterList.SysLimit = EnvPtr->SysLimit; - ParameterList.TableBasedAlterations = EnvPtr->TableBasedAlterations; - ParameterList.PlatformMemoryConfiguration = EnvPtr->PlatformMemoryConfiguration; - MemPtr->ParameterListPtr = &ParameterList; - - for (p = 0; p < MAX_PLATFORM_TYPES; p++) { - MemPtr->GetPlatformCfg[p] = EnvPtr->GetPlatformCfg[p]; - } - - MemPtr->ErrorHandling = EnvPtr->ErrorHandling; - // - // Create Local NBBlock and Tech Block - // - EnvPtr->NBBlockCtor (&NB, MCTPtr, EnvPtr->FeatPtr); - NB.RefPtr = &ParameterList; - NB.MemPtr = MemPtr; - i = 0; - while (memTechInstalled[i] != NULL) { - if (memTechInstalled[i] (&TB, &NB)) { - break; - } - i++; - } - NB.TechPtr = &TB; - NB.TechBlockSwitch (&NB); - - // - // Setup CPU Mem Type MSRs on the AP - // - NB.CpuMemTyping (&NB); - - IDS_HDT_CONSOLE (MEM_STATUS, "Node %d\n", NB.Node); - // - // Call Technology Specific Training routine - // - NB.TrainingFlow (&NB); - // - // Copy training data to ReturnData buffer - // - LibAmdMemCopy ( BufferPtr, - MCTPtr->DctData[0].ChData[0].RcvEnDlys, - ((DctCount * ChannelCount) * ( - (RowCount * ColumnCount * NUMBER_OF_DELAY_TABLES) + - (MAX_BYTELANES_PER_CHANNEL * MAX_CS_PER_CHANNEL * NUMBER_OF_FAILURE_MASK_TABLES) - ) - ), - StdHeader); - - HeapDeallocateBuffer (AMD_MEM_DATA_HANDLE, StdHeader); - // - // Restore pointers - // - for (Dct = 0; Dct < MCTPtr->DctCount; Dct++) { - for (Channel = 0; Channel < MCTPtr->DctData[Dct].ChannelCount; Channel++) { - MCTPtr->DctData[Dct].ChData[Channel].MCTPtr = &EnvPtr->DieStruct; - MCTPtr->DctData[Dct].ChData[Channel].DCTPtr = &EnvPtr->DieStruct.DctData[Dct]; - - MCTPtr->DctData[Dct].ChData[Channel].RcvEnDlys = EnvPtr->DieStruct.DctData[Dct].ChData[Channel].RcvEnDlys; - MCTPtr->DctData[Dct].ChData[Channel].WrDqsDlys = EnvPtr->DieStruct.DctData[Dct].ChData[Channel].WrDqsDlys; - MCTPtr->DctData[Dct].ChData[Channel].RdDqsDlys = EnvPtr->DieStruct.DctData[Dct].ChData[Channel].RdDqsDlys; - MCTPtr->DctData[Dct].ChData[Channel].WrDatDlys = EnvPtr->DieStruct.DctData[Dct].ChData[Channel].WrDatDlys; - MCTPtr->DctData[Dct].ChData[Channel].RdDqsMinDlys = EnvPtr->DieStruct.DctData[Dct].ChData[Channel].RdDqsMinDlys; - MCTPtr->DctData[Dct].ChData[Channel].RdDqsMaxDlys = EnvPtr->DieStruct.DctData[Dct].ChData[Channel].RdDqsMaxDlys; - MCTPtr->DctData[Dct].ChData[Channel].WrDatMinDlys = EnvPtr->DieStruct.DctData[Dct].ChData[Channel].WrDatMinDlys; - MCTPtr->DctData[Dct].ChData[Channel].WrDatMaxDlys = EnvPtr->DieStruct.DctData[Dct].ChData[Channel].WrDatMaxDlys; - MCTPtr->DctData[Dct].ChData[Channel].FailingBitMask = EnvPtr->DieStruct.DctData[Dct].ChData[Channel].FailingBitMask; - } - MCTPtr->DctData[Dct].ChData = EnvPtr->DieStruct.DctData[Dct].ChData; - } - MCTPtr->DctData = EnvPtr->DieStruct.DctData; - } - - // - // Signal to BSP that training is complete and Send Results - // - ASSERT (ReturnData.DataPtr != NULL); - ApUtilTransmitBuffer (EnvPtr->BspSocket, EnvPtr->BspCore, &ReturnData, StdHeader); - - // - // Clean up and exit. - // - HeapDeallocateBuffer (GENERATE_MEM_HANDLE (ALLOC_PAR_TRN_HANDLE, 0, 0, 0), StdHeader); - } else { - MCTPtr = &EnvPtr->DieStruct; - PutEventLog (AGESA_FATAL, MEM_ERROR_HEAP_ALLOCATE_FOR_TRAINING_DATA, MCTPtr->NodeId, 0, 0, 0, StdHeader); - SetMemError (AGESA_FATAL, MCTPtr); - ASSERT(FALSE); // Could not allocate heap for buffer for parallel training data - } - return TRUE; -} diff --git a/src/vendorcode/amd/agesa/f12/Proc/Mem/Feat/PARTRN/mfStandardTraining.c b/src/vendorcode/amd/agesa/f12/Proc/Mem/Feat/PARTRN/mfStandardTraining.c deleted file mode 100644 index be45c95668..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/Mem/Feat/PARTRN/mfStandardTraining.c +++ /dev/null @@ -1,86 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * mfStandardTraining.c - * - * This is the standard training routine which performs all training from the BSP - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: (Mem/Feat/PARTRN) - * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $ - * - **/ -/***************************************************************************** - * - * Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * *************************************************************************** - * - */ - - - - -#include "AGESA.h" -#include "mm.h" -#include "mn.h" -#include "mt.h" -#include "Ids.h" -#include "mfStandardTraining.h" -#include "Filecode.h" -CODE_GROUP (G1_PEICC) -RDATA_GROUP (G1_PEICC) - -#define FILECODE PROC_MEM_FEAT_PARTRN_MFSTANDARDTRAINING_FILECODE -/*----------------------------------------------------------------------------- -* EXPORTED FUNCTIONS -* -*----------------------------------------------------------------------------- -*/ - -/* -----------------------------------------------------------------------------*/ -/** - * - * - * This is the main function to perform memory training on all nodes from - * the BSP only. - * - * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK - * - * @return TRUE - This feature is enabled. - * @return FALSE - This feature is not enabled. - */ -BOOLEAN -MemFStandardTraining ( - IN OUT MEM_NB_BLOCK *NBPtr - ) -{ - ASSERT (NBPtr != NULL); - - NBPtr->TrainingFlow (NBPtr); - return TRUE; -} diff --git a/src/vendorcode/amd/agesa/f12/Proc/Mem/Feat/S3/Makefile.inc b/src/vendorcode/amd/agesa/f12/Proc/Mem/Feat/S3/Makefile.inc deleted file mode 100644 index 506cda03d7..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/Mem/Feat/S3/Makefile.inc +++ /dev/null @@ -1 +0,0 @@ -libagesa-y += mfs3.c diff --git a/src/vendorcode/amd/agesa/f12/Proc/Mem/Feat/S3/mfs3.c b/src/vendorcode/amd/agesa/f12/Proc/Mem/Feat/S3/mfs3.c deleted file mode 100644 index 728bd01d25..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/Mem/Feat/S3/mfs3.c +++ /dev/null @@ -1,717 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * mfs3.c - * - * Main S3 resume memory Entrypoint file - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: (Mem/FEAT/S3) - * @e \$Revision: 47676 $ @e \$Date: 2011-02-25 06:29:57 +0800 (Fri, 25 Feb 2011) $ - * - **/ -/***************************************************************************** -* -* Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* *************************************************************************** -* -*/ - -/* - *---------------------------------------------------------------------------- - * MODULES USED - * - *---------------------------------------------------------------------------- - */ - - - -#include "AGESA.h" -#include "Ids.h" -#include "cpuRegisters.h" -#include "OptionMemory.h" -#include "mm.h" -#include "mn.h" -#include "S3.h" -#include "mfs3.h" -#include "heapManager.h" -#include "amdlib.h" -#include "GeneralServices.h" -#include "cpuFamilyTranslation.h" -#include "Filecode.h" -CODE_GROUP (G2_PEI) -RDATA_GROUP (G2_PEI) - -#define FILECODE PROC_MEM_FEAT_S3_MFS3_FILECODE - -extern MEM_NB_SUPPORT memNBInstalled[]; - -/*---------------------------------------------------------------------------- - * DEFINITIONS AND MACROS - * - *---------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------- - * TYPEDEFS AND STRUCTURES - * - *---------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------- - * PROTOTYPES OF LOCAL FUNCTIONS - * - *---------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------- - * EXPORTED FUNCTIONS - * - *---------------------------------------------------------------------------- - */ -/* -----------------------------------------------------------------------------*/ -/** - * - * - * This function is the main memory entry point for the S3 resume sequence - * Requirements: - * - * Run-Time Requirements: - * 1. Complete Hypertransport Bus Configuration - * 4. BSP in Big Real Mode - * 5. Stack available - * - * @param[in] *StdHeader - Config handle for library and services - * - * @return AGESA_STATUS - * - AGESA_ALERT - * - AGESA_FATAL - * - AGESA_SUCCESS - * - AGESA_WARNING - */ -AGESA_STATUS -AmdMemS3Resume ( - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - AGESA_STATUS RetVal; - MEM_MAIN_DATA_BLOCK mmData; - S3_MEM_NB_BLOCK *S3NBPtr; - MEM_DATA_STRUCT *MemData; - UINT8 Die; - UINT8 DieCount; - - //--------------------------------------------- - // Creation of NB Block for S3 resume - //--------------------------------------------- - RetVal = MemS3InitNB (&S3NBPtr, &MemData, &mmData, StdHeader); - if (RetVal == AGESA_FATAL) { - return RetVal; - } - DieCount = mmData.DieCount; - - //--------------------------------------------- - //1. Errata Before resume sequence - //2. S3 Resume sequence - //3. Errata After resume sequence - //--------------------------------------------- - for (Die = 0; Die < DieCount; Die ++) { - if (!S3NBPtr[Die].MemS3Resume (&S3NBPtr[Die], Die)) { - return AGESA_FATAL; - } - S3NBPtr[Die].MemS3RestoreScrub (S3NBPtr[Die].NBPtr, Die); - } - - HeapDeallocateBuffer (AMD_MEM_S3_DATA_HANDLE, StdHeader); - return AGESA_SUCCESS; -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * - * This function deallocates heap space allocated in memory S3 resume. - * - * @param[in] *StdHeader - Config handle for library and services - * - * @return AGESA_STATUS - * - AGESA_ALERT - * - AGESA_FATAL - * - AGESA_SUCCESS - * - AGESA_WARNING - */ -AGESA_STATUS -MemS3Deallocate ( - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - AGESA_STATUS RetVal; - AGESA_STATUS tempRetVal; - UINT8 Tab; - - RetVal = AGESA_SUCCESS; - for (Tab = 0; Tab < NumberOfNbRegTables; Tab++) { - HeapDeallocateBuffer (GENERATE_MEM_HANDLE (ALLOC_NB_REG_TABLE, Tab, 0, 0), StdHeader); - } - - tempRetVal = HeapDeallocateBuffer (GENERATE_MEM_HANDLE (ALLOC_DIE_STRUCT_HANDLE, 0, 0, 0), StdHeader); - if (tempRetVal > RetVal) { - RetVal = tempRetVal; - } - tempRetVal = HeapDeallocateBuffer (AMD_MEM_AUTO_HANDLE, StdHeader); - if (tempRetVal > RetVal) { - RetVal = tempRetVal; - } - RetVal = HeapDeallocateBuffer (AMD_MEM_S3_NB_HANDLE, StdHeader); - if (tempRetVal > RetVal) { - RetVal = tempRetVal; - } - RetVal = HeapDeallocateBuffer (AMD_MEM_DATA_HANDLE, StdHeader); - if (tempRetVal > RetVal) { - RetVal = tempRetVal; - } - return RetVal; -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * - * This function is the entrance to get device list for memory registers. - * - * @param[in, out] **DeviceBlockHdrPtr - Pointer to the memory containing the - * device descriptor list - * @param[in] *StdHeader - Config handle for library and services - * @return AGESA_STATUS - * - AGESA_ALERT - * - AGESA_FATAL - * - AGESA_SUCCESS - * - AGESA_WARNING - */ -AGESA_STATUS -MemFS3GetDeviceList ( - IN OUT DEVICE_BLOCK_HEADER **DeviceBlockHdrPtr, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - UINT8 i; - UINT16 BufferSize; - UINT64 BufferOffset; - S3_MEM_NB_BLOCK *S3NBPtr; - MEM_DATA_STRUCT *MemData; - MEM_MAIN_DATA_BLOCK mmData; - UINT8 Die; - UINT8 DieCount; - AGESA_STATUS RetVal; - ALLOCATE_HEAP_PARAMS AllocHeapParams; - DESCRIPTOR_GROUP DeviceDescript[MAX_NODES_SUPPORTED]; - BufferSize = 0; - - //--------------------------------------------- - // Creation of NB Block for S3 resume - //--------------------------------------------- - RetVal = MemS3InitNB (&S3NBPtr, &MemData, &mmData, StdHeader); - if (RetVal == AGESA_FATAL) { - return RetVal; - } - DieCount = mmData.DieCount; - - // Get the mask bit and the register list for node that presents - for (Die = 0; Die < DieCount; Die ++) { - S3NBPtr->MemS3GetConPCIMask (S3NBPtr[Die].NBPtr, (VOID *)&DeviceDescript[Die]); - S3NBPtr->MemS3GetConMSRMask (S3NBPtr[Die].NBPtr, (VOID *)&DeviceDescript[Die]); - BufferSize = BufferSize + S3NBPtr->MemS3GetRegLstPtr (S3NBPtr[Die].NBPtr, (VOID *)&DeviceDescript[Die]); - } - - // Base on the size of the device list, apply for a buffer for it. - AllocHeapParams.RequestedBufferSize = BufferSize + sizeof (DEVICE_BLOCK_HEADER); - AllocHeapParams.BufferHandle = AMD_S3_NB_INFO_BUFFER_HANDLE; - AGESA_TESTPOINT (TpIfBeforeAllocateMemoryS3SaveBuffer, StdHeader); - if (HeapAllocateBuffer (&AllocHeapParams, StdHeader) != AGESA_SUCCESS) { - return AGESA_FATAL; - } - AGESA_TESTPOINT (TpIfAfterAllocateMemoryS3SaveBuffer, StdHeader); - - *DeviceBlockHdrPtr = (DEVICE_BLOCK_HEADER *) AllocHeapParams.BufferPtr; - (*DeviceBlockHdrPtr)->RelativeOrMaskOffset = (UINT16) AllocHeapParams.RequestedBufferSize; - - // Copy device list on the stack to the heap. - BufferOffset = sizeof (DEVICE_BLOCK_HEADER) + (UINT64) (intptr_t) AllocHeapParams.BufferPtr; - for (Die = 0; Die < DieCount; Die ++) { - for (i = PRESELFREF; i <= POSTSELFREF; i ++) { - // Copy PCI device descriptor to the heap if it exists. - if (DeviceDescript[Die].PCIDevice[i].RegisterListID != 0xFFFFFFFF) { - LibAmdMemCopy ((VOID *) (intptr_t) BufferOffset, &(DeviceDescript[Die].PCIDevice[i]), sizeof (PCI_DEVICE_DESCRIPTOR), StdHeader); - (*DeviceBlockHdrPtr)->NumDevices ++; - BufferOffset += sizeof (PCI_DEVICE_DESCRIPTOR); - } - // Copy conditional PCI device descriptor to the heap if it exists. - if (DeviceDescript[Die].CPCIDevice[i].RegisterListID != 0xFFFFFFFF) { - LibAmdMemCopy ((VOID *) (intptr_t) BufferOffset, &(DeviceDescript[Die].CPCIDevice[i]), sizeof (CONDITIONAL_PCI_DEVICE_DESCRIPTOR), StdHeader); - (*DeviceBlockHdrPtr)->NumDevices ++; - BufferOffset += sizeof (CONDITIONAL_PCI_DEVICE_DESCRIPTOR); - } - // Copy MSR device descriptor to the heap if it exists. - if (DeviceDescript[Die].MSRDevice[i].RegisterListID != 0xFFFFFFFF) { - LibAmdMemCopy ((VOID *) (intptr_t) BufferOffset, &(DeviceDescript[Die].MSRDevice[i]), sizeof (MSR_DEVICE_DESCRIPTOR), StdHeader); - (*DeviceBlockHdrPtr)->NumDevices ++; - BufferOffset += sizeof (MSR_DEVICE_DESCRIPTOR); - } - // Copy conditional MSR device descriptor to the heap if it exists. - if (DeviceDescript[Die].CMSRDevice[i].RegisterListID != 0xFFFFFFFF) { - LibAmdMemCopy ((VOID *) (intptr_t) BufferOffset, &(DeviceDescript[Die].PCIDevice[i]), sizeof (CONDITIONAL_MSR_DEVICE_DESCRIPTOR), StdHeader); - (*DeviceBlockHdrPtr)->NumDevices ++; - BufferOffset += sizeof (CONDITIONAL_MSR_DEVICE_DESCRIPTOR); - } - } - } - - return RetVal; -} - - -/* -----------------------------------------------------------------------------*/ -/** - * - * - * This function initialize the northbridge block and apply for heap space - * before any function call is made to memory component during S3 resume. - * - * @param[in] *StdHeader - Config handle for library and services - * @return AGESA_STATUS - * - AGESA_ALERT - * - AGESA_FATAL - * - AGESA_SUCCESS - * - AGESA_WARNING - */ -AGESA_STATUS -MemS3ResumeInitNB ( - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - AGESA_STATUS RetVal; - MEM_MAIN_DATA_BLOCK mmData; - S3_MEM_NB_BLOCK *S3NBPtr; - MEM_DATA_STRUCT *MemData; - UINT8 Die; - UINT8 DieCount; - UINT8 SpecialCaseHeapSize; - ALLOCATE_HEAP_PARAMS AllocHeapParams; - S3_SPECIAL_CASE_HEAP_HEADER SpecialHeapHeader[MAX_NODES_SUPPORTED]; - - SpecialCaseHeapSize = 0; - - //--------------------------------------------- - // Creation of NB Block for S3 resume - //--------------------------------------------- - RetVal = MemS3InitNB (&S3NBPtr, &MemData, &mmData, StdHeader); - if (RetVal == AGESA_FATAL) { - return RetVal; - } - DieCount = mmData.DieCount; - - //-------------------------------------------------- - // Apply for heap space for special case registers - //-------------------------------------------------- - for (Die = 0; Die < DieCount; Die ++) { - // Construct the header for the special case heap. - SpecialHeapHeader[Die].Node = S3NBPtr[Die].NBPtr->Node; - SpecialHeapHeader[Die].Offset = SpecialCaseHeapSize + (DieCount * (sizeof (S3_SPECIAL_CASE_HEAP_HEADER))); - SpecialCaseHeapSize = SpecialCaseHeapSize + S3NBPtr->MemS3SpecialCaseHeapSize; - } - AllocHeapParams.RequestedBufferSize = (DieCount * (sizeof (S3_SPECIAL_CASE_HEAP_HEADER))) + SpecialCaseHeapSize; - AllocHeapParams.BufferHandle = AMD_MEM_S3_DATA_HANDLE; - AllocHeapParams.Persist = HEAP_SYSTEM_MEM; - if (HeapAllocateBuffer (&AllocHeapParams, StdHeader) != AGESA_SUCCESS) { - PutEventLog (AGESA_FATAL, MEM_ERROR_HEAP_ALLOCATE_FOR_S3_SPECIAL_CASE_REGISTERS, S3NBPtr[Die].NBPtr->Node, 0, 0, 0, StdHeader); - SetMemError (AGESA_FATAL, S3NBPtr[Die].NBPtr->MCTPtr); - ASSERT(FALSE); // Could not allocate heap space for "S3_SPECIAL_CASE_HEAP_HEADER" - return AGESA_FATAL; - } - LibAmdMemCopy ((VOID *) AllocHeapParams.BufferPtr, (VOID *) SpecialHeapHeader, (sizeof (S3_SPECIAL_CASE_HEAP_HEADER) * DieCount), StdHeader); - return AGESA_SUCCESS; -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * - * This function returns the PCI device register list according to the register - * list ID. - * - * @param[in] *Device - pointer to the PCI_DEVICE_DESCRIPTOR - * @param[out] **RegisterHdr - pointer to the address of the register list - * @param[in] *StdHeader - Config handle for library and services - * - * @return AGESA_STATUS - * - AGESA_ALERT - * - AGESA_FATAL - * - AGESA_SUCCESS - * - AGESA_WARNING - */ -AGESA_STATUS -MemFS3GetPciDeviceRegisterList ( - IN PCI_DEVICE_DESCRIPTOR *Device, - OUT PCI_REGISTER_BLOCK_HEADER **RegisterHdr, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - AGESA_STATUS RetVal; - S3_MEM_NB_BLOCK *S3NBPtr; - VOID *RegisterHeader; - LOCATE_HEAP_PTR LocHeap; - AGESA_BUFFER_PARAMS LocBufferParams; - LocHeap.BufferHandle = AMD_MEM_S3_NB_HANDLE; - - LibAmdMemCopy (&LocBufferParams.StdHeader, StdHeader, sizeof (AMD_CONFIG_PARAMS), StdHeader); - LocBufferParams.BufferHandle = AMD_MEM_S3_NB_HANDLE; - - AGESA_TESTPOINT (TpIfBeforeLocateS3PciBuffer, StdHeader); - if (HeapLocateBuffer (&LocHeap, StdHeader) == AGESA_SUCCESS) { - S3NBPtr = (S3_MEM_NB_BLOCK *)LocHeap.BufferPtr; - } else { - ASSERT(FALSE) ; // No match for heap status, but could not locate "AMD_MEM_S3_NB_HANDLE" in heap for S3GetMsr - return AGESA_FATAL; - } - AGESA_TESTPOINT (TpIfAfterLocateS3PciBuffer, StdHeader); - - // NB block has already been constructed by main block. - // No need to construct it here. - RetVal = S3NBPtr[Device->Node].MemS3GetDeviceRegLst (Device->RegisterListID, &RegisterHeader); - *RegisterHdr = (PCI_REGISTER_BLOCK_HEADER *)RegisterHeader; - return RetVal; -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * - * This function returns the conditional PCI device register list according - * to the register list ID. - * - * @param[in] *Device - pointer to the CONDITIONAL_PCI_DEVICE_DESCRIPTOR - * @param[out] **RegisterHdr - pointer to the address of the register list - * @param[in] *StdHeader - Config handle for library and services - * - * @return AGESA_STATUS - * - AGESA_ALERT - * - AGESA_FATAL - * - AGESA_SUCCESS - * - AGESA_WARNING - */ -AGESA_STATUS -MemFS3GetCPciDeviceRegisterList ( - IN CONDITIONAL_PCI_DEVICE_DESCRIPTOR *Device, - OUT CPCI_REGISTER_BLOCK_HEADER **RegisterHdr, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - AGESA_STATUS RetVal; - S3_MEM_NB_BLOCK *S3NBPtr; - VOID *RegisterHeader; - LOCATE_HEAP_PTR LocHeap; - AGESA_BUFFER_PARAMS LocBufferParams; - - LibAmdMemCopy (&LocBufferParams.StdHeader, StdHeader, sizeof (AMD_CONFIG_PARAMS), StdHeader); - LocHeap.BufferHandle = AMD_MEM_S3_NB_HANDLE; - LocBufferParams.BufferHandle = AMD_MEM_S3_NB_HANDLE; - - AGESA_TESTPOINT (TpIfBeforeLocateS3CPciBuffer, StdHeader); - if (HeapLocateBuffer (&LocHeap, StdHeader) == AGESA_SUCCESS) { - S3NBPtr = (S3_MEM_NB_BLOCK *)LocHeap.BufferPtr; - } else { - ASSERT(FALSE) ; // No match for heap status, but could not locate "AMD_MEM_S3_NB_HANDLE" in heap for S3GetMsr - return AGESA_FATAL; - } - AGESA_TESTPOINT (TpIfAfterLocateS3CPciBuffer, StdHeader); - - // NB block has already been constructed by main block. - // No need to construct it here. - RetVal = S3NBPtr[Device->Node].MemS3GetDeviceRegLst (Device->RegisterListID, &RegisterHeader); - *RegisterHdr = (CPCI_REGISTER_BLOCK_HEADER *)RegisterHeader; - return RetVal; -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * - * This function returns the MSR device register list according to the register - * list ID. - * - * @param[in] *Device - pointer to the MSR_DEVICE_DESCRIPTOR - * @param[out] **RegisterHdr - pointer to the address of the register list - * @param[in] *StdHeader - Config handle for library and services - * - * @return AGESA_STATUS - * - AGESA_ALERT - * - AGESA_FATAL - * - AGESA_SUCCESS - * - AGESA_WARNING - */ -AGESA_STATUS -MemFS3GetMsrDeviceRegisterList ( - IN MSR_DEVICE_DESCRIPTOR *Device, - OUT MSR_REGISTER_BLOCK_HEADER **RegisterHdr, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - AGESA_STATUS RetVal; - S3_MEM_NB_BLOCK *S3NBPtr; - VOID *RegisterHeader; - LOCATE_HEAP_PTR LocHeap; - AGESA_BUFFER_PARAMS LocBufferParams; - - LibAmdMemCopy (&LocBufferParams.StdHeader, StdHeader, sizeof (AMD_CONFIG_PARAMS), StdHeader); - LocHeap.BufferHandle = AMD_MEM_S3_NB_HANDLE; - LocBufferParams.BufferHandle = AMD_MEM_S3_NB_HANDLE; - - AGESA_TESTPOINT (TpIfBeforeLocateS3MsrBuffer, StdHeader); - if (HeapLocateBuffer (&LocHeap, StdHeader) == AGESA_SUCCESS) { - S3NBPtr = (S3_MEM_NB_BLOCK *)LocHeap.BufferPtr; - } else { - ASSERT(FALSE) ; // No match for heap status, but could not locate "AMD_MEM_S3_NB_HANDLE" in heap for S3GetMsr - return AGESA_FATAL; - } - AGESA_TESTPOINT (TpIfAfterLocateS3MsrBuffer, StdHeader); - - // NB block has already been constructed by main block. - // No need to construct it here. - RetVal = S3NBPtr[BSP_DIE].MemS3GetDeviceRegLst (Device->RegisterListID, &RegisterHeader); - *RegisterHdr = (MSR_REGISTER_BLOCK_HEADER *)RegisterHeader; - return RetVal; -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * - * This function returns the conditional MSR device register list according - * to the register list ID. - * - * @param[in] *Device - pointer to the CONDITIONAL_PCI_DEVICE_DESCRIPTOR - * @param[out] **RegisterHdr - pointer to the address of the register list - * @param[in] *StdHeader - Config handle for library and services - * - * @return AGESA_STATUS - * - AGESA_ALERT - * - AGESA_FATAL - * - AGESA_SUCCESS - * - AGESA_WARNING - */ -AGESA_STATUS -MemFS3GetCMsrDeviceRegisterList ( - IN CONDITIONAL_MSR_DEVICE_DESCRIPTOR *Device, - OUT CMSR_REGISTER_BLOCK_HEADER **RegisterHdr, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - AGESA_STATUS RetVal; - S3_MEM_NB_BLOCK *S3NBPtr; - VOID *RegisterHeader; - LOCATE_HEAP_PTR LocHeap; - AGESA_BUFFER_PARAMS LocBufferParams; - - LibAmdMemCopy (&LocBufferParams.StdHeader, StdHeader, sizeof (AMD_CONFIG_PARAMS), StdHeader); - LocHeap.BufferHandle = AMD_MEM_S3_NB_HANDLE; - LocBufferParams.BufferHandle = AMD_MEM_S3_NB_HANDLE; - - - AGESA_TESTPOINT (TpIfBeforeLocateS3CMsrBuffer, StdHeader); - if (HeapLocateBuffer (&LocHeap, StdHeader) == AGESA_SUCCESS) { - S3NBPtr = (S3_MEM_NB_BLOCK *)LocHeap.BufferPtr; - } else { - ASSERT(FALSE) ; // No match for heap status, but could not locate "AMD_MEM_S3_NB_HANDLE" in heap for S3GetMsr - return AGESA_FATAL; - } - AGESA_TESTPOINT (TpIfAfterLocateS3CMsrBuffer, StdHeader); - - // NB block has already been constructed by main block. - // No need to construct it here. - RetVal = S3NBPtr[BSP_DIE].MemS3GetDeviceRegLst (Device->RegisterListID, &RegisterHeader); - *RegisterHdr = (CMSR_REGISTER_BLOCK_HEADER *)RegisterHeader; - return RetVal; -} - -/*---------------------------------------------------------------------------- - * LOCAL FUNCTIONS - * - *---------------------------------------------------------------------------- - */ - -/* -----------------------------------------------------------------------------*/ -/** - * - * - * This function initialize needed data structures for S3 resume. - * - * @param[in, out] **S3NBPtr - Pointer to the pointer of northbridge block. - * @param[in, out] *MemPtr - Pointer to MEM_DATA_STRUCT. - * @param[in, out] *mmData - Pointer to MEM_MAIN_DATA_BLOCK. - * @param[in] *StdHeader - Config handle for library and services. - * - * @return AGESA_STATUS - * - AGESA_ALERT - * - AGESA_FATAL - * - AGESA_SUCCESS - * - AGESA_WARNING - */ -AGESA_STATUS -MemS3InitNB ( - IN OUT S3_MEM_NB_BLOCK **S3NBPtr, - IN OUT MEM_DATA_STRUCT **MemPtr, - IN OUT MEM_MAIN_DATA_BLOCK *mmData, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - UINT8 i; - AGESA_STATUS RetVal; - LOCATE_HEAP_PTR LocHeap; - MEM_NB_BLOCK *NBPtr; - ALLOCATE_HEAP_PARAMS AllocHeapParams; - UINT8 Die; - UINT8 DieCount; - BOOLEAN SkipScan; - CPU_SPECIFIC_SERVICES *FamilySpecificServices; - - SkipScan = FALSE; - LocHeap.BufferHandle = AMD_MEM_DATA_HANDLE; - if (HeapLocateBuffer (&LocHeap, StdHeader) == AGESA_SUCCESS) { - // NB block has already been constructed by main block. - // No need to construct it here. - *MemPtr = (MEM_DATA_STRUCT *)LocHeap.BufferPtr; - SkipScan = TRUE; - } else { - AllocHeapParams.RequestedBufferSize = sizeof (MEM_DATA_STRUCT); - AllocHeapParams.BufferHandle = AMD_MEM_DATA_HANDLE; - AllocHeapParams.Persist = HEAP_SYSTEM_MEM; - if (HeapAllocateBuffer (&AllocHeapParams, StdHeader) != AGESA_SUCCESS) { - ASSERT(FALSE); // Allocate failed for MEM_DATA_STRUCT - return AGESA_FATAL; - } - *MemPtr = (MEM_DATA_STRUCT *)AllocHeapParams.BufferPtr; - LibAmdMemCopy (&(*MemPtr)->StdHeader, StdHeader, sizeof (AMD_CONFIG_PARAMS), StdHeader); - - GetCpuServicesOfCurrentCore ((const CPU_SPECIFIC_SERVICES **) &FamilySpecificServices, &(*MemPtr)->StdHeader); - FamilySpecificServices->GetTscRate (FamilySpecificServices, &(*MemPtr)->TscRate, &(*MemPtr)->StdHeader); - - } - mmData->MemPtr = *MemPtr; - - if (!SkipScan) { - RetVal = MemSocketScan (mmData); - if (RetVal == AGESA_FATAL) { - return RetVal; - } - } else { - // We already have initialize data block, no need to do it again. - mmData->DieCount = mmData->MemPtr->DieCount; - } - DieCount = mmData->DieCount; - - //--------------------------------------------- - // Creation of NB Block for S3 resume - //--------------------------------------------- - // Search for AMD_MEM_AUTO_HANDLE on the heap first. - // Only apply for space on the heap if cannot find AMD_MEM_AUTO_HANDLE on the heap. - LocHeap.BufferHandle = AMD_MEM_S3_NB_HANDLE; - if (HeapLocateBuffer (&LocHeap, StdHeader) == AGESA_SUCCESS) { - // NB block has already been constructed by main block. - // No need to construct it here. - *S3NBPtr = (S3_MEM_NB_BLOCK *)LocHeap.BufferPtr; - } else { - AllocHeapParams.RequestedBufferSize = (DieCount * (sizeof (S3_MEM_NB_BLOCK))); - AllocHeapParams.BufferHandle = AMD_MEM_S3_NB_HANDLE; - AllocHeapParams.Persist = HEAP_SYSTEM_MEM; - if (HeapAllocateBuffer (&AllocHeapParams, StdHeader) != AGESA_SUCCESS) { - ASSERT(FALSE); // Could not allocate space for "S3_MEM_NB_BLOCK" - return AGESA_FATAL; - } - *S3NBPtr = (S3_MEM_NB_BLOCK *)AllocHeapParams.BufferPtr; - - LocHeap.BufferHandle = AMD_MEM_AUTO_HANDLE; - if (HeapLocateBuffer (&LocHeap, StdHeader) == AGESA_SUCCESS) { - // NB block has already been constructed by main block. - // No need to construct it here. - NBPtr = (MEM_NB_BLOCK *)LocHeap.BufferPtr; - } else { - AllocHeapParams.RequestedBufferSize = (DieCount * (sizeof (MEM_NB_BLOCK))); - AllocHeapParams.BufferHandle = AMD_MEM_AUTO_HANDLE; - AllocHeapParams.Persist = HEAP_SYSTEM_MEM; - if (HeapAllocateBuffer (&AllocHeapParams, StdHeader) != AGESA_SUCCESS) { - ASSERT(FALSE); // Allocate failed for "MEM_NB_BLOCK" - return AGESA_FATAL; - } - NBPtr = (MEM_NB_BLOCK *)AllocHeapParams.BufferPtr; - } - // Construct each die. - for (Die = 0; Die < DieCount; Die ++) { - i = 0; - ((*S3NBPtr)[Die]).NBPtr = &NBPtr[Die]; - while (memNBInstalled[i].MemS3ResumeConstructNBBlock != 0) { - if (memNBInstalled[i].MemS3ResumeConstructNBBlock ((VOID *)&((*S3NBPtr)[Die]), *MemPtr, Die)) { - break; - } - i++; - }; - if (memNBInstalled[i].MemS3ResumeConstructNBBlock == 0) { - ASSERT(FALSE); // S3 resume NB constructor not found - return AGESA_FATAL; - } - } - } - return AGESA_SUCCESS; -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * Waits specified number of 10ns cycles - * @param[in,out] MemPtr - pointer to MEM_DATA_STRUCTURE - * @param[in] Count - Number of 10ns cycles to wait - * - * ---------------------------------------------------------------------------- - */ - -VOID -MemFS3Wait10ns ( - IN UINT32 Count, - IN OUT MEM_DATA_STRUCT *MemPtr - ) -{ - UINT64 TargetTsc; - UINT64 CurrentTsc; - - ASSERT (Count <= 1000000); - - LibAmdMsrRead (TSC, &CurrentTsc, &MemPtr->StdHeader); - TargetTsc = CurrentTsc + ((Count * MemPtr->TscRate + 99) / 100); - do { - LibAmdMsrRead (TSC, &CurrentTsc, &MemPtr->StdHeader); - } while (CurrentTsc < TargetTsc); -} diff --git a/src/vendorcode/amd/agesa/f12/Proc/Mem/Feat/TABLE/Makefile.inc b/src/vendorcode/amd/agesa/f12/Proc/Mem/Feat/TABLE/Makefile.inc deleted file mode 100644 index 27dcfe7f00..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/Mem/Feat/TABLE/Makefile.inc +++ /dev/null @@ -1 +0,0 @@ -libagesa-y += mftds.c diff --git a/src/vendorcode/amd/agesa/f12/Proc/Mem/Feat/TABLE/mftds.c b/src/vendorcode/amd/agesa/f12/Proc/Mem/Feat/TABLE/mftds.c deleted file mode 100644 index 42617e6fec..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/Mem/Feat/TABLE/mftds.c +++ /dev/null @@ -1,330 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * mftds.c - * - * Northbridge table drive support file for DR - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: (Mem/Feat/TABLE) - * @e \$Revision: 47683 $ @e \$Date: 2011-02-25 10:06:08 +0800 (Fri, 25 Feb 2011) $ - * - **/ -/***************************************************************************** - * - * Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * *************************************************************************** - * - */ - - - -#include "AGESA.h" -#include "amdlib.h" -#include "mm.h" -#include "mn.h" -#include "mt.h" -#include "mftds.h" -#include "Ids.h" -#include "OptionMemory.h" -#include "Filecode.h" -CODE_GROUP (G2_PEI) -RDATA_GROUP (G2_PEI) - -#define FILECODE PROC_MEM_FEAT_TABLE_MFTDS_FILECODE -/*---------------------------------------------------------------------------- - * Mixed (DEFINITIONS AND MACROS / TYPEDEFS, STRUCTURES, ENUMS) - * - *---------------------------------------------------------------------------- - */ - -/*----------------------------------------------------------------------------- - * DEFINITIONS AND MACROS - * - *----------------------------------------------------------------------------- - */ -#define MAX_BYTELANES_PER_CHANNEL (8 + 1) ///< Max Bytelanes per channel - -/*---------------------------------------------------------------------------- - * TYPEDEFS, STRUCTURES, ENUMS - * - *---------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------- - * FUNCTIONS PROTOTYPE - * - *---------------------------------------------------------------------------- - */ - -VOID -SetTableValues ( - IN OUT MEM_NB_BLOCK *NBPtr, - IN MEM_TABLE_ALIAS MTPtr - ); - -VOID -SetTableValuesLoop ( - IN OUT MEM_NB_BLOCK *NBPtr, - IN MEM_TABLE_ALIAS *MTPtr, - IN UINT8 time - ); - -/*----------------------------------------------------------------------------- - * - * This function initializes bit field translation table - * - * @param[in,out] *NBPtr - Pointer to the MEM_TABLE_ALIAS structure - * @param[in] time - Indicate the timing for the register which is written. - * - * @return None - * ---------------------------------------------------------------------------- - */ -VOID -MemFInitTableDrive ( - IN OUT MEM_NB_BLOCK *NBPtr, - IN UINT8 time - ) -{ - MEM_TABLE_ALIAS *MTPtr; - MEM_TABLE_ALIAS *IdsMTPtr; - - ASSERT (NBPtr != NULL); - IdsMTPtr = NULL; - IDS_HDT_CONSOLE (MEM_FLOW, "MemFInitTableDrive [%X] Start\n", time); - MTPtr = (MEM_TABLE_ALIAS *) NBPtr->RefPtr->TableBasedAlterations; - - IDS_SKIP_HOOK (IDS_GET_DRAM_TABLE, &IdsMTPtr, &(NBPtr->MemPtr->StdHeader)) { - IDS_OPTION_HOOK (IDS_INIT_DRAM_TABLE, NBPtr, &(NBPtr->MemPtr->StdHeader)); - IDS_OPTION_HOOK (IDS_GET_DRAM_TABLE, &IdsMTPtr, &(NBPtr->MemPtr->StdHeader)); - } - - SetTableValuesLoop (NBPtr, MTPtr, time); - SetTableValuesLoop (NBPtr, IdsMTPtr, time); - - IDS_HDT_CONSOLE (MEM_FLOW, "MemFInitTableDrive End\n"); -} - -/*----------------------------------------------------------------------------- - * - * This function initializes bit field translation table - * - * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK - * @param[in,out] *MTPtr - Pointer to the MEM_TABLE_ALIAS structure - * @param[in] time - Indicate the timing for the register which is written. - * - * @return None - * ---------------------------------------------------------------------------- - */ -VOID -SetTableValuesLoop ( - IN OUT MEM_NB_BLOCK *NBPtr, - IN MEM_TABLE_ALIAS *MTPtr, - IN UINT8 time - ) -{ - UINT8 i; - UINT8 CurDct; - - if (MTPtr != NULL) { - CurDct = NBPtr->Dct; - for (i = 0; MTPtr[i].time != MTEnd; i++) { - if ((MTPtr[i].attr != MTAuto) && (MTPtr[i].time == time)) { - SetTableValues (NBPtr, MTPtr[i]); - } - } - NBPtr->SwitchDCT (NBPtr, CurDct); - } -} - -/*----------------------------------------------------------------------------- - * - * Engine for setting Table Value. - * - * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK - * @param[in] MTPtr - Pointer to the MEM_TABLE_ALIAS structure - * - * @return None - * ---------------------------------------------------------------------------- - */ -VOID -SetTableValues ( - IN OUT MEM_NB_BLOCK *NBPtr, - IN MEM_TABLE_ALIAS MTPtr - ) -{ - UINT8 AccessType; - UINT16 ByteLane; - UINT8 Dct; - UINT8 i; - UINT8 j; - UINT32 TempVal[36]; - UINT8 *DqsSavePtr; - UINT8 DqsOffset; - BOOLEAN SaveDqs; - - AccessType = 0; - DqsSavePtr = NULL; - SaveDqs = TRUE; - - ASSERT (MTPtr.time <= MTValidTimePointLimit); - ASSERT (MTPtr.attr <= MTOr); - ASSERT (MTPtr.node <= MTNodes); - ASSERT (MTPtr.dct <= MTDcts); - ASSERT (MTPtr.dimm <= MTDIMMs); - ASSERT (MTPtr.data.s.bytelane <= MTBLs); - - for (Dct = 0; Dct < NBPtr->DctCount; Dct++) { - if ((MTPtr.dct == MTDcts) || (MTPtr.dct == Dct)) { - NBPtr->SwitchDCT (NBPtr, Dct); - switch (MTPtr.bfindex) { - case BFRcvEnDly: - AccessType = AccessRcvEnDly; - DqsSavePtr = NULL; - break; - case BFWrDatDly: - AccessType = AccessWrDatDly; - DqsSavePtr = NBPtr->ChannelPtr->WrDatDlys; - break; - case BFRdDqsDly: - AccessType = AccessRdDqsDly; - DqsSavePtr = NBPtr->ChannelPtr->RdDqsDlys; - break; - case BFWrDqsDly: - AccessType = AccessWrDqsDly; - DqsSavePtr = NBPtr->ChannelPtr->WrDqsDlys; - break; - case BFPhRecDly: - AccessType = AccessPhRecDly; - SaveDqs = FALSE; - break; - default: - AccessType = 0xFF; - break; - } - if (AccessType == 0xFF) { - if (MTPtr.attr == MTOverride) { - NBPtr->SetBitField (NBPtr, MTPtr.bfindex, MTPtr.data.s.value); - } - if (MTPtr.attr == MTSubtract) { - NBPtr->SetBitField (NBPtr, MTPtr.bfindex, NBPtr->GetBitField (NBPtr, MTPtr.bfindex) - MTPtr.data.s.value); - } - if (MTPtr.attr == MTAdd) { - NBPtr->SetBitField (NBPtr, MTPtr.bfindex, NBPtr->GetBitField (NBPtr, MTPtr.bfindex) + MTPtr.data.s.value); - } - if (MTPtr.attr == MTAnd) { - NBPtr->SetBitField (NBPtr, MTPtr.bfindex, (NBPtr->GetBitField (NBPtr, MTPtr.bfindex) & MTPtr.data.s.value)); - } - if (MTPtr.attr == MTOr) { - NBPtr->SetBitField (NBPtr, MTPtr.bfindex, (NBPtr->GetBitField (NBPtr, MTPtr.bfindex) | MTPtr.data.s.value)); - } - } else { - // Store the DQS data first - for (i = 0; i < MAX_DIMMS_PER_CHANNEL; i++) { - for (j = 0; j < MAX_BYTELANES_PER_CHANNEL; j++) { - TempVal[i * MAX_BYTELANES_PER_CHANNEL + j] = NBPtr->GetTrainDly (NBPtr, AccessType, DIMM_BYTE_ACCESS (i, j)); - } - } - // - // Single Value with Bytleane mask option - // Indicated by the vtype flag - // - if (MTPtr.vtype == VT_MSK_VALUE) { - // set the value which defined in Memory table. - for (i = 0; i < MAX_DIMMS_PER_CHANNEL; i++) { - ByteLane = MTPtr.data.s.bytelane; - if ((MTPtr.dimm == MTDIMMs) || (MTPtr.dimm == i)) { - for (j = 0; j < MAX_BYTELANES_PER_CHANNEL; j++) { - DqsOffset = (i * MAX_BYTELANES_PER_CHANNEL + j); - if ((ByteLane & (UINT16)1) != 0) { - if (MTPtr.attr == MTOverride) { - TempVal[DqsOffset] = (UINT16)MTPtr.data.s.value; - } - if (MTPtr.attr == MTSubtract) { - TempVal[DqsOffset] -= (UINT16)MTPtr.data.s.value; - } - if (MTPtr.attr == MTAdd) { - TempVal[DqsOffset] += (UINT16)MTPtr.data.s.value; - } - NBPtr->SetTrainDly (NBPtr, AccessType, DIMM_BYTE_ACCESS (i, j), (UINT16)TempVal[DqsOffset]); - if (SaveDqs) { - if (DqsSavePtr == NULL) { - NBPtr->ChannelPtr->RcvEnDlys[DqsOffset] = (UINT16)TempVal[DqsOffset]; - } else { - DqsSavePtr[DqsOffset] = (UINT8)TempVal[DqsOffset]; - } - } - } - ByteLane = ByteLane >> (UINT16)1; - } - } - } - } else { - // Multiple values specified in a byte array - for (i = 0; i < MAX_DIMMS_PER_CHANNEL; i++) { - if ((MTPtr.dimm == MTDIMMs) || (MTPtr.dimm == i)) { - for (j = 0; j < MAX_BYTELANES_PER_CHANNEL; j++) { - DqsOffset = (i * MAX_BYTELANES_PER_CHANNEL + j); - if (MTPtr.attr == MTOverride) { - TempVal[DqsOffset] = MTPtr.data.bytelanevalue[j]; - } - if (MTPtr.attr == MTSubtract) { - TempVal[DqsOffset] -= MTPtr.data.bytelanevalue[j]; - } - if (MTPtr.attr == MTAdd) { - TempVal[DqsOffset] += MTPtr.data.bytelanevalue[j]; - } - NBPtr->SetTrainDly (NBPtr, AccessType, DIMM_BYTE_ACCESS (i, j), (UINT16)TempVal[DqsOffset]); - if (SaveDqs) { - if (DqsSavePtr == NULL) { - NBPtr->ChannelPtr->RcvEnDlys[DqsOffset] = (UINT16)TempVal[DqsOffset]; - } else { - DqsSavePtr[DqsOffset] = (UINT8)TempVal[DqsOffset]; - } - } - } - } - } - } - // set the DQS value to left DIMMs. - i = MTPtr.dimm; - while ((i != MTDIMMs) && ((++i) < MAX_DIMMS_PER_CHANNEL)) { - for (j = 0; j < MAX_BYTELANES_PER_CHANNEL; j++) { - NBPtr->SetTrainDly (NBPtr, AccessType, DIMM_BYTE_ACCESS (i, j), (UINT16)TempVal[i * MAX_BYTELANES_PER_CHANNEL + j]); - } - } - } - } - } -} - - - - - - diff --git a/src/vendorcode/amd/agesa/f12/Proc/Mem/Main/LN/Makefile.inc b/src/vendorcode/amd/agesa/f12/Proc/Mem/Main/LN/Makefile.inc deleted file mode 100644 index ebcfe3c423..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/Mem/Main/LN/Makefile.inc +++ /dev/null @@ -1 +0,0 @@ -libagesa-y += mmflowln.c diff --git a/src/vendorcode/amd/agesa/f12/Proc/Mem/Main/LN/mmflowln.c b/src/vendorcode/amd/agesa/f12/Proc/Mem/Main/LN/mmflowln.c deleted file mode 100644 index 39ab982cd2..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/Mem/Main/LN/mmflowln.c +++ /dev/null @@ -1,321 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * mmflowln.c - * - * Main Memory initialization sequence for LN - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: (Mem/Main/LN) - * @e \$Revision: 49794 $ @e \$Date: 2011-03-29 13:59:05 +0800 (Tue, 29 Mar 2011) $ - * - **/ -/***************************************************************************** -* -* Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* *************************************************************************** -* -*/ - -/* - *---------------------------------------------------------------------------- - * MODULES USED - * - *---------------------------------------------------------------------------- - */ - - - -#include "AGESA.h" -#include "Ids.h" -#include "OptionMemory.h" -#include "mm.h" -#include "mn.h" -#include "mnln.h" -#include "mt.h" -#include "cpuFamilyTranslation.h" -#include "Filecode.h" -#include "GeneralServices.h" -CODE_GROUP (G1_PEICC) -RDATA_GROUP (G1_PEICC) - -#define FILECODE PROC_MEM_MAIN_LN_MMFLOWLN_FILECODE -/* features */ -#include "mftds.h" - -extern MEM_FEAT_BLOCK_MAIN MemFeatMain; - -/*---------------------------------------------------------------------------- - * DEFINITIONS AND MACROS - * - *---------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------- - * TYPEDEFS AND STRUCTURES - * - *---------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------- - * PROTOTYPES OF LOCAL FUNCTIONS - * - *---------------------------------------------------------------------------- - */ -AGESA_STATUS -MemMFlowLN ( - IN OUT MEM_MAIN_DATA_BLOCK *MemMainPtr - ); - -/*---------------------------------------------------------------------------- - * EXPORTED FUNCTIONS - * - *---------------------------------------------------------------------------- - */ -/* -----------------------------------------------------------------------------*/ -/** - * - * - * This function defines the memory initialization flow for - * systems that only support LN processors. - * - * @param[in,out] *MemMainPtr - Pointer to the MEM_MAIN_DATA_BLOCK - * - * @return AGESA_STATUS - * - AGESA_ALERT - * - AGESA_FATAL - * - AGESA_SUCCESS - * - AGESA_WARNING - */ -AGESA_STATUS -MemMFlowLN ( - IN OUT MEM_MAIN_DATA_BLOCK *MemMainPtr - ) -{ - MEM_NB_BLOCK *NBPtr; - MEM_DATA_STRUCT *MemPtr; - - NBPtr = MemMainPtr->NBPtr; - MemPtr = MemMainPtr->MemPtr; - - GetLogicalIdOfSocket (MemPtr->DiesPerSystem[BSP_DIE].SocketId, &(MemPtr->DiesPerSystem[BSP_DIE].LogicalCpuid), &(MemPtr->StdHeader)); - if (!MemNIsIdSupportedLN (NBPtr, &(MemPtr->DiesPerSystem[BSP_DIE].LogicalCpuid))) { - MemPtr->IsFlowControlSupported = FALSE; - return AGESA_FATAL; - } else { - MemPtr->IsFlowControlSupported = TRUE; - } - - MemFInitTableDrive (&NBPtr[BSP_DIE], MTBeforeInitializeMCT); - - //---------------------------------------------------------------- - // Low voltage DDR3 - //---------------------------------------------------------------- - // Levelize DDR3 voltage based on socket, as each socket has its own voltage for dimms. - AGESA_TESTPOINT (TpProcMemLvDdr3, &(MemMainPtr->MemPtr->StdHeader)); - if (!MemFeatMain.LvDDR3 (MemMainPtr)) { - return AGESA_FATAL; - } - - //---------------------------------------------------------------- - // Initialize DRAM and DCTs, and Create Memory Map - //---------------------------------------------------------------- - AGESA_TESTPOINT (TpProcMemInitMCT, &(MemMainPtr->MemPtr->StdHeader)); - // Initialize Memory Controller and Dram - IDS_HDT_CONSOLE (MEM_STATUS, "Node 0\n"); - - if (!NBPtr[BSP_DIE].InitMCT (&NBPtr[BSP_DIE])) { - return AGESA_FATAL; //fatalexit - } - - // Create memory map - AGESA_TESTPOINT (TpProcMemSystemMemoryMapping, &(MemMainPtr->MemPtr->StdHeader)); - if (!NBPtr[BSP_DIE].HtMemMapInit (&NBPtr[BSP_DIE])) { - return AGESA_FATAL; - } - - //---------------------------------------------------- - // If there is no dimm on the system, do fatal exit - //---------------------------------------------------- - if (NBPtr[BSP_DIE].RefPtr->SysLimit == 0) { - PutEventLog (AGESA_FATAL, MEM_ERROR_NO_DIMM_FOUND_ON_SYSTEM, 0, 0, 0, 0, &(MemMainPtr->MemPtr->StdHeader)); - ASSERT(FALSE); // Size of memory on BSP = 0, so no DIMM found - return AGESA_FATAL; - } - - //---------------------------------------------------------------- - // Synchronize DCTs - //---------------------------------------------------------------- - AGESA_TESTPOINT (TpProcMemSynchronizeDcts, &(MemMainPtr->MemPtr->StdHeader)); - if (!NBPtr[BSP_DIE].SyncDctsReady (&NBPtr[BSP_DIE])) { - return AGESA_FATAL; - } - - //---------------------------------------------------------------- - // CpuMemTyping - //---------------------------------------------------------------- - AGESA_TESTPOINT (TpProcMemMtrrConfiguration, &(MemMainPtr->MemPtr->StdHeader)); - if (!NBPtr[BSP_DIE].CpuMemTyping (&NBPtr[BSP_DIE])) { - return AGESA_FATAL; - } - - //---------------------------------------------------------------- - // Before Training Table values - //---------------------------------------------------------------- - MemFInitTableDrive (&NBPtr[BSP_DIE], MTBeforeTrn); - - //---------------------------------------------------------------- - // Memory Context Restore - //---------------------------------------------------------------- - if (!MemFeatMain.MemRestore (MemMainPtr)) { - // Do DQS training only if memory context restore fails - - //---------------------------------------------------------------- - // Training - //---------------------------------------------------------------- - MemMainPtr->mmSharedPtr->DimmExcludeFlag = TRAINING; - AGESA_TESTPOINT (TpProcMemDramTraining, &(MemMainPtr->MemPtr->StdHeader)); - IDS_SKIP_HOOK (IDS_BEFORE_DQS_TRAINING, MemMainPtr, &(MemMainPtr->MemPtr->StdHeader)) { - if (!MemFeatMain.Training (MemMainPtr)) { - return AGESA_FATAL; - } - } - IDS_HDT_CONSOLE (MEM_FLOW, "\nEnd DQS training\n\n"); - } - - //---------------------------------------------------------------- - // Disable chipselects that fail training - //---------------------------------------------------------------- - MemMainPtr->mmSharedPtr->DimmExcludeFlag = END_TRAINING; - MemFeatMain.ExcludeDIMM (MemMainPtr); - MemMainPtr->mmSharedPtr->DimmExcludeFlag = NORMAL; - - //---------------------------------------------------------------- - // OtherTiming - //---------------------------------------------------------------- - AGESA_TESTPOINT (TpProcMemOtherTiming, &(MemMainPtr->MemPtr->StdHeader)); - if (!NBPtr[BSP_DIE].OtherTiming (&NBPtr[BSP_DIE])) { - return AGESA_FATAL; - } - - //---------------------------------------------------------------- - // After Training Table values - //---------------------------------------------------------------- - MemFInitTableDrive (&NBPtr[BSP_DIE], MTAfterTrn); - - - //---------------------------------------------------------------- - // Interleave banks - //---------------------------------------------------------------- - if (NBPtr[BSP_DIE].FeatPtr->InterleaveBanks (&NBPtr[BSP_DIE])) { - if (NBPtr[BSP_DIE].MCTPtr->ErrCode == AGESA_FATAL) { - return AGESA_FATAL; - } - } - - //---------------------------------------------------------------- - // Interleave channels - //---------------------------------------------------------------- - if (NBPtr[BSP_DIE].FeatPtr->InterleaveChannels (&NBPtr[BSP_DIE])) { - if (NBPtr[BSP_DIE].MCTPtr->ErrCode == AGESA_FATAL) { - return AGESA_FATAL; - } - } - - //---------------------------------------------------------------- - // After Programming Interleave registers - //---------------------------------------------------------------- - MemFInitTableDrive (&NBPtr[BSP_DIE], MTAfterInterleave); - - //---------------------------------------------------------------- - // Memory Clear - //---------------------------------------------------------------- - AGESA_TESTPOINT (TpProcMemMemClr, &(MemMainPtr->MemPtr->StdHeader)); - if (!MemFeatMain.MemClr (MemMainPtr)) { - return AGESA_FATAL; - } - - //---------------------------------------------------------------- - // C6 Storage Allocation - //---------------------------------------------------------------- - NBPtr[BSP_DIE].AllocateC6Storage (&NBPtr[BSP_DIE]); - - //---------------------------------------------------------------- - // UMA Allocation & UMAMemTyping - //---------------------------------------------------------------- - AGESA_TESTPOINT (TpProcMemUMAMemTyping, &(MemMainPtr->MemPtr->StdHeader)); - if (!MemFeatMain.UmaAllocation (MemMainPtr)) { - return AGESA_FATAL; - } - - //---------------------------------------------------------------- - // Interleave region - //---------------------------------------------------------------- - NBPtr[BSP_DIE].FeatPtr->InterleaveRegion (&NBPtr[BSP_DIE]); - - //---------------------------------------------------------------- - // OnDimm Thermal - //---------------------------------------------------------------- - if (NBPtr[BSP_DIE].FeatPtr->OnDimmThermal (&NBPtr[BSP_DIE])) { - if (NBPtr[BSP_DIE].MCTPtr->ErrCode == AGESA_FATAL) { - return AGESA_FATAL; - } - } - - //---------------------------------------------------------------- - // Finalize MCT - //---------------------------------------------------------------- - if (!NBPtr[BSP_DIE].FinalizeMCT (&NBPtr[BSP_DIE])) { - return AGESA_FATAL; - } - - //---------------------------------------------------------------- - // After Finalize MCT - //---------------------------------------------------------------- - MemFInitTableDrive (&NBPtr[BSP_DIE], MTAfterFinalizeMCT); - - //---------------------------------------------------------------- - // Memory Context Save - //---------------------------------------------------------------- - MemFeatMain.MemSave (MemMainPtr); - - //---------------------------------------------------------------- - // Memory DMI support - //---------------------------------------------------------------- - if (!MemFeatMain.MemDmi (MemMainPtr)) { - return AGESA_CRITICAL; - } - - return AGESA_SUCCESS; -} - -/*---------------------------------------------------------------------------- - * LOCAL FUNCTIONS - * - *---------------------------------------------------------------------------- - */ diff --git a/src/vendorcode/amd/agesa/f12/Proc/Mem/Main/Makefile.inc b/src/vendorcode/amd/agesa/f12/Proc/Mem/Main/Makefile.inc deleted file mode 100644 index 4c61d95629..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/Mem/Main/Makefile.inc +++ /dev/null @@ -1,18 +0,0 @@ -libagesa-y += mdef.c -libagesa-y += merrhdl.c -libagesa-y += minit.c -libagesa-y += mm.c -libagesa-y += mmConditionalPso.c -libagesa-y += mmEcc.c -libagesa-y += mmExcludeDimm.c -libagesa-y += mmLvDdr3.c -libagesa-y += mmMemClr.c -libagesa-y += mmMemRestore.c -libagesa-y += mmNodeInterleave.c -libagesa-y += mmOnlineSpare.c -libagesa-y += mmParallelTraining.c -libagesa-y += mmStandardTraining.c -libagesa-y += mmUmaAlloc.c -libagesa-y += mmflow.c -libagesa-y += mu.c -libagesa-y += muc.c diff --git a/src/vendorcode/amd/agesa/f12/Proc/Mem/Main/mdef.c b/src/vendorcode/amd/agesa/f12/Proc/Mem/Main/mdef.c deleted file mode 100644 index c64b9152ef..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/Mem/Main/mdef.c +++ /dev/null @@ -1,147 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * mdef.c - * - * Memory Controller header file - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: (Mem/Main) - * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $ - * - **/ -/***************************************************************************** - * - * Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * *************************************************************************** - * - */ - - -/* - *---------------------------------------------------------------------------- - * MODULES USED - * - *---------------------------------------------------------------------------- - */ - -#include "AGESA.h" -#include "Filecode.h" -#include "mm.h" -#include "AdvancedApi.h" -CODE_GROUP (G1_PEICC) -RDATA_GROUP (G1_PEICC) - -#define FILECODE PROC_MEM_MAIN_MDEF_FILECODE -/*---------------------------------------------------------------------------- - * DEFINITIONS AND MACROS - * - *---------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------- - * TYPEDEFS AND STRUCTURES - * - *---------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------- - * PROTOTYPES OF LOCAL FUNCTIONS - * - *---------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------- - * EXPORTED FUNCTIONS - * - *---------------------------------------------------------------------------- - */ -AGESA_STATUS -MemMFlowDef ( - IN OUT MEM_MAIN_DATA_BLOCK *MemMainPtr - ); - -/* -----------------------------------------------------------------------------*/ -/** - * - * This is the default return function - */ - -VOID -memDefRet (VOID) -{ -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * This function is the default return function that returns TRUE - * - */ -BOOLEAN -memDefTrue (VOID) -{ - return TRUE; -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * This function is used in place of an un-supported function that returns FALSE. - * - */ -BOOLEAN -memDefFalse (VOID) -{ - return FALSE; -} -/* -----------------------------------------------------------------------------*/ -/** - * - * This is the default return function for flow control - */ -AGESA_STATUS -MemMFlowDef ( - IN OUT MEM_MAIN_DATA_BLOCK *MemMainPtr - ) -{ - MemMainPtr->MemPtr->IsFlowControlSupported = FALSE; - return AGESA_SUCCESS; -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * This function is used in place of an un-supported function that returns AGESA_SUCCESS. - * - */ -AGESA_STATUS -memDefRetSuccess (VOID) -{ - return AGESA_SUCCESS; -} diff --git a/src/vendorcode/amd/agesa/f12/Proc/Mem/Main/merrhdl.c b/src/vendorcode/amd/agesa/f12/Proc/Mem/Main/merrhdl.c deleted file mode 100644 index 1bf4e5d62c..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/Mem/Main/merrhdl.c +++ /dev/null @@ -1,187 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * merrhdl.c - * - * Memory error handling - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: (Mem/Main) - * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $ - * - **/ -/***************************************************************************** -* -* Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* *************************************************************************** -* -*/ - -/* - *---------------------------------------------------------------------------- - * MODULES USED - * - *---------------------------------------------------------------------------- - */ - -#include "AGESA.h" -#include "amdlib.h" -#include "Ids.h" -#include "OptionMemory.h" -#include "mm.h" -#include "mn.h" -#include "mt.h" -#include "heapManager.h" -#include "merrhdl.h" -#include "Filecode.h" -CODE_GROUP (G1_PEICC) -RDATA_GROUP (G1_PEICC) - -#define FILECODE PROC_MEM_MAIN_MERRHDL_FILECODE - -extern MEM_FEAT_BLOCK_MAIN MemFeatMain; -/*---------------------------------------------------------------------------- - * DEFINITIONS AND MACROS - * - *---------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------- - * TYPEDEFS AND STRUCTURES - * - *---------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------- - * PROTOTYPES OF LOCAL FUNCTIONS - * - *---------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------- - * EXPORTED FUNCTIONS - * - *---------------------------------------------------------------------------- - */ - -/* -----------------------------------------------------------------------------*/ -/** - * - * This function handle errors occur in memory code. - * - * - * @param[in,out] *MCTPtr - pointer to DIE_STRUCT. - * @param[in,out] DCT - DCT that needs to be handled. - * @param[in,out] ChipSelMask - Chip select mask that needs to be handled - * @param[in,out] *StdHeader - pointer to AMD_CONFIG_PARAMS - * - * @return TRUE - No fatal error occurs. - * @return FALSE - Fatal error occurs. - */ -BOOLEAN -MemErrHandle ( - IN DIE_STRUCT *MCTPtr, - IN UINT8 DCT, - IN UINT16 ChipSelMask, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - BOOLEAN ErrorRecovery; - BOOLEAN IgnoreErr; - DCT_STRUCT *DCTPtr; - UINT8 CurrentDCT; - LOCATE_HEAP_PTR LocHeap; - MEM_NB_BLOCK *NBPtr; - MEM_MAIN_DATA_BLOCK mmData; - - DCTPtr = MCTPtr->DctData; - ErrorRecovery = TRUE; - IgnoreErr = FALSE; - IDS_OPTION_HOOK (IDS_MEM_ERROR_RECOVERY, &ErrorRecovery, StdHeader); - - if (ErrorRecovery) { - if (DCT == EXCLUDE_ALL_DCT) { - // Exclude all DCTs on a node - for (CurrentDCT = 0; CurrentDCT < MCTPtr->DctCount; CurrentDCT++) { - DCTPtr[CurrentDCT].Timings.CsTestFail = DCTPtr[CurrentDCT].Timings.CsPresent; - } - } else if (ChipSelMask == EXCLUDE_ALL_CHIPSEL) { - // Exclude the specified DCT - DCTPtr[DCT].Timings.CsTestFail = DCTPtr[DCT].Timings.CsPresent; - } else { - // Exclude the chip select that has been marked out - DCTPtr[DCT].Timings.CsTestFail |= ChipSelMask & DCTPtr[DCT].Timings.CsPresent; - IDS_OPTION_HOOK (IDS_LOADCARD_ERROR_RECOVERY, &DCTPtr[DCT], StdHeader); - } - - // Exclude the failed dimm to recovery from error - if (MCTPtr->NodeMemSize != 0) { - LocHeap.BufferHandle = AMD_MEM_AUTO_HANDLE; - if (HeapLocateBuffer (&LocHeap, StdHeader) == AGESA_SUCCESS) { - // NB block has already been constructed by main block. - // No need to construct it here. - NBPtr = (MEM_NB_BLOCK *)LocHeap.BufferPtr; - if (!NBPtr->SharedPtr->NodeMap[MCTPtr->NodeId].IsValid) { - // Memory map has not been calculated, no need to remap memory across node here. - // Only need to remap memory within the node. - NBPtr = &NBPtr[MCTPtr->NodeId]; - NBPtr->FeatPtr->ExcludeDIMM (NBPtr); - } else { - // Need to remap memory across the whole system. - mmData.MemPtr = NBPtr->MemPtr; - mmData.mmSharedPtr = NBPtr->SharedPtr; - mmData.NBPtr = NBPtr; - mmData.TechPtr = (MEM_TECH_BLOCK *) (&NBPtr[NBPtr->MemPtr->DieCount]); - mmData.DieCount = NBPtr->MemPtr->DieCount; - if (!MemFeatMain.ExcludeDIMM (&mmData)) { - return FALSE; - } - } - } - // If allocation fails, that means the code is not running at BSP. - // Parallel training is in process. - // Remap for parallel training will be done when control returns to BSP. - } - return TRUE; - } else { - IDS_OPTION_HOOK (IDS_MEM_IGNORE_ERROR, &IgnoreErr, StdHeader); - if (IgnoreErr) { - return TRUE; - } - SetMemError (AGESA_FATAL, MCTPtr); - ASSERT(FALSE); // ErrorRecovery is FALSE - return FALSE; - } -} - -/*---------------------------------------------------------------------------- - * LOCAL FUNCTIONS - * - *---------------------------------------------------------------------------- - */ - diff --git a/src/vendorcode/amd/agesa/f12/Proc/Mem/Main/minit.c b/src/vendorcode/amd/agesa/f12/Proc/Mem/Main/minit.c deleted file mode 100644 index 22c4b76512..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/Mem/Main/minit.c +++ /dev/null @@ -1,137 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * minit.c - * - * Initializer support function - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: (Mem/Main) - * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $ - * - **/ -/***************************************************************************** - * - * Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * *************************************************************************** - * - */ - -/* - *---------------------------------------------------------------------------- - * MODULES USED - * - *---------------------------------------------------------------------------- - */ - - -#include "AGESA.h" -#include "amdlib.h" -#include "mu.h" -#include "OptionMemory.h" -#include "Ids.h" -#include "merrhdl.h" -#include "AdvancedApi.h" -#include "Filecode.h" -CODE_GROUP (G1_PEICC) -RDATA_GROUP (G1_PEICC) - -#define FILECODE PROC_MEM_MAIN_MINIT_FILECODE -/*---------------------------------------------------------------------------- - * DEFINITIONS AND MACROS - * - *---------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------- - * TYPEDEFS AND STRUCTURES - * - *---------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------- - * PROTOTYPES OF LOCAL FUNCTIONS - * - *---------------------------------------------------------------------------- - */ - -extern MEM_NB_SUPPORT memNBInstalled[]; -extern MEM_PLATFORM_CFG* memPlatformTypeInstalled[]; - - -/*---------------------------------------------------------------------------- - * EXPORTED FUNCTIONS - * - *---------------------------------------------------------------------------- - */ -/* -----------------------------------------------------------------------------*/ -/** - * - * - * This function initializes the default parameter, function pointers, build options - * and SPD data for memory configuration - * - * @param[in,out] *MemPtr - Pointer to the MEM_DATA_STRUCT - * @param[in,out] *PlatFormConfig - Platform profile/build option config structure - * - */ - -VOID -AmdMemInitDataStructDef ( - IN OUT MEM_DATA_STRUCT *MemPtr, - IN OUT PLATFORM_CONFIGURATION *PlatFormConfig - ) -{ - UINT8 p; - UINT8 i; - // We need a way of specifying default values for each particular northbridge - // family. We also need to make sure that the IBV knows which parameter struct - // is for which northbridge. - //---------------------------------------------------------------------------- - AGESA_TESTPOINT (TpProcMemBeforeMemDataInit, &MemPtr->StdHeader); - - MemPtr->PlatFormConfig = PlatFormConfig; - - memNBInstalled[0].MemNInitDefaults (MemPtr); - - //---------------------------------------------------------------------------- - // INITIALIZE PLATFORM SPECIFIC CONFIGURATION STRUCT - //---------------------------------------------------------------------------- - AGESA_TESTPOINT (TpProcMemPlatformSpecificConfig, &MemPtr->StdHeader); - i = 0; - for (p = 0; p < MAX_PLATFORM_TYPES; p++) { - if (memPlatformTypeInstalled[i] != NULL) { - MemPtr->GetPlatformCfg[p] = memPlatformTypeInstalled[i]; - i++; - } else { - MemPtr->GetPlatformCfg[p] = MemAGetPsCfgDef; - } - } - AGESA_TESTPOINT (TpProcMemAfterMemDataInit, &MemPtr->StdHeader); - MemPtr->ErrorHandling = MemErrHandle; -} diff --git a/src/vendorcode/amd/agesa/f12/Proc/Mem/Main/mm.c b/src/vendorcode/amd/agesa/f12/Proc/Mem/Main/mm.c deleted file mode 100644 index c7b0bdbf03..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/Mem/Main/mm.c +++ /dev/null @@ -1,238 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * mm.c - * - * Main Memory Entrypoint file - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: (Mem/Main) - * @e \$Revision: 48768 $ @e \$Date: 2011-03-11 06:18:53 +0800 (Fri, 11 Mar 2011) $ - * - **/ -/***************************************************************************** -* -* Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* *************************************************************************** -* -*/ - -/* - *---------------------------------------------------------------------------- - * MODULES USED - * - *---------------------------------------------------------------------------- - */ - - - -#include "AGESA.h" -#include "amdlib.h" -#include "Ids.h" -#include "cpuRegisters.h" -#include "cpuServices.h" -#include "GeneralServices.h" -#include "OptionMemory.h" -#include "mm.h" -#include "mn.h" -#include "mt.h" -#include "heapManager.h" -#include "Filecode.h" -CODE_GROUP (G1_PEICC) -RDATA_GROUP (G1_PEICC) - -#define FILECODE PROC_MEM_MAIN_MM_FILECODE -/* features */ - -/*---------------------------------------------------------------------------- - * DEFINITIONS AND MACROS - * - *---------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------- - * TYPEDEFS AND STRUCTURES - * - *---------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------- - * PROTOTYPES OF LOCAL FUNCTIONS - * - *---------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------- - * EXPORTED FUNCTIONS - * - *---------------------------------------------------------------------------- - */ - -/* -----------------------------------------------------------------------------*/ -/** - * - * - * This function deallocates heap buffers that were allocated in AmdMemAuto - * - * @param[in,out] *MemPtr - Pointer to the MEM_DATA_STRUCT - * - * @return AGESA_STATUS - * - AGESA_ALERT - * - AGESA_FATAL - * - AGESA_SUCCESS - * - AGESA_WARNING - */ -AGESA_STATUS -MemAmdFinalize ( - IN OUT MEM_DATA_STRUCT *MemPtr - ) -{ - UINT8 Die; - - for (Die = 0; Die < MemPtr->DieCount; Die++ ) { - HeapDeallocateBuffer (GENERATE_MEM_HANDLE (ALLOC_TRN_DATA_HANDLE, Die, 0, 0), &MemPtr->StdHeader); - HeapDeallocateBuffer (GENERATE_MEM_HANDLE (ALLOC_DCT_STRUCT_HANDLE, Die, 0, 0), &MemPtr->StdHeader); - } - - HeapDeallocateBuffer (GENERATE_MEM_HANDLE (ALLOC_DIE_STRUCT_HANDLE, 0, 0, 0), &MemPtr->StdHeader); - HeapDeallocateBuffer (AMD_S3_SAVE_HANDLE, &MemPtr->StdHeader); - HeapDeallocateBuffer (AMD_MEM_SPD_HANDLE, &MemPtr->StdHeader); - HeapDeallocateBuffer (AMD_MEM_AUTO_HANDLE, &MemPtr->StdHeader); - return AGESA_SUCCESS; -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * - * MemSocketScan - Scan all nodes, recording the physical Socket number, - * Die Number (relative to the socket), and PCI Device address of each - * populated socket. - * - * This information is used by the northbridge block to map a dram - * channel on a particular DCT, on a particular CPU Die, in a particular - * socket to a the DRAM SPD Data for the DIMMS physically connected to - * that channel. - * - * Also, the customer socket map is populated with pointers to the - * appropriate channel structures, so that the customer can locate the - * appropriate channel configuration data. - * - * This socket scan will always result in Die 0 as the BSP. - * - * @param[in,out] *mmPtr - Pointer to the MEM_MAIN_DATA_BLOCK - * - */ -AGESA_STATUS -MemSocketScan ( - IN OUT MEM_MAIN_DATA_BLOCK *mmPtr - ) -{ - MEM_DATA_STRUCT *MemPtr; - UINT8 DieIndex; - UINT8 DieCount; - UINT32 SocketId; - UINT32 DieId; - UINT8 Die; - PCI_ADDR Address; - AGESA_STATUS AgesaStatus; - ALLOCATE_HEAP_PARAMS AllocHeapParams; - - ASSERT (mmPtr != NULL); - ASSERT (mmPtr->MemPtr != NULL); - MemPtr = mmPtr->MemPtr; - - // - // Count the number of dies in the system - // - DieCount = 0; - for (Die = 0; Die < MAX_NODES_SUPPORTED; Die++) { - if (GetSocketModuleOfNode ((UINT32)Die, &SocketId, &DieId, (VOID *)MemPtr)) { - DieCount++; - } - } - MemPtr->DieCount = DieCount; - mmPtr->DieCount = DieCount; - - if (DieCount > 0) { - // - // Allocate buffer for DIE_STRUCTs - // - AllocHeapParams.RequestedBufferSize = ((UINT16)DieCount * sizeof (DIE_STRUCT)); - AllocHeapParams.BufferHandle = GENERATE_MEM_HANDLE (ALLOC_DIE_STRUCT_HANDLE, 0, 0, 0); - AllocHeapParams.Persist = HEAP_LOCAL_CACHE; - if (HeapAllocateBuffer (&AllocHeapParams, &MemPtr->StdHeader) == AGESA_SUCCESS) { - MemPtr->DiesPerSystem = (DIE_STRUCT *)AllocHeapParams.BufferPtr; - // - // Find SocketId, DieId, and PCI address of each node - // - DieIndex = 0; - for (Die = 0; Die < MAX_NODES_SUPPORTED; Die++) { - if (GetSocketModuleOfNode ((UINT32)Die, &SocketId, &DieId, (VOID *)MemPtr)) { - if (GetPciAddress ((VOID *)MemPtr, (UINT8)SocketId, (UINT8)DieId, &Address, &AgesaStatus)) { - MemPtr->DiesPerSystem[DieIndex].SocketId = (UINT8)SocketId; - MemPtr->DiesPerSystem[DieIndex].DieId = (UINT8)DieId; - MemPtr->DiesPerSystem[DieIndex].PciAddr.AddressValue = Address.AddressValue; - - DieIndex++; - } - } - } - AgesaStatus = AGESA_SUCCESS; - } else { - ASSERT(FALSE); // Heap allocation failed for DIE_STRUCTs - AgesaStatus = AGESA_FATAL; - } - } else { - ASSERT(FALSE); // No die in the system - AgesaStatus = AGESA_FATAL; - } - return AgesaStatus; -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * - * This function sets memory errors into MemDataStruct - * - * - * @param[in,out] *MCTPtr - Pointer to the DIE_STRUCT - * @param[in] Errorval - Error value to update - */ - -VOID -SetMemError ( - IN AGESA_STATUS Errorval, - IN OUT DIE_STRUCT *MCTPtr - ) -{ - if (MCTPtr->ErrCode < Errorval) { - MCTPtr->ErrCode = Errorval; - } -} diff --git a/src/vendorcode/amd/agesa/f12/Proc/Mem/Main/mmConditionalPso.c b/src/vendorcode/amd/agesa/f12/Proc/Mem/Main/mmConditionalPso.c deleted file mode 100644 index 59069b48ad..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/Mem/Main/mmConditionalPso.c +++ /dev/null @@ -1,695 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * mmConditionalPso.c - * - * Functions to support conditional entries in the Platform Specific Override Table - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: (Mem/Main) - * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $ - * - **/ -/***************************************************************************** -* -* Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* *************************************************************************** -* -*/ - -/* - *---------------------------------------------------------------------------- - * MODULES USED - * - *---------------------------------------------------------------------------- - */ - - - -#include "AGESA.h" -#include "amdlib.h" -#include "OptionMemory.h" -#include "PlatformMemoryConfiguration.h" -#include "Ids.h" -#include "Filecode.h" -CODE_GROUP (G1_PEICC) -RDATA_GROUP (G1_PEICC) - -#define FILECODE PROC_MEM_MAIN_MMCONDITIONALPSO_FILECODE -/*---------------------------------------------------------------------------- - * DEFINITIONS AND MACROS - * - *---------------------------------------------------------------------------- - */ - - -/*---------------------------------------------------------------------------- - * TYPEDEFS AND STRUCTURES - * - *---------------------------------------------------------------------------- - */ - -#define PSO_TYPE 0 -#define PSO_LENGTH 1 -#define PSO_DATA 2 - -typedef enum _PSO_STATE { - PSO_FIND_CONDITION = 100, // Searching for initial Condition statement - PSO_FIND_ACTION, // Searching for initial Action Statement - PSO_MATCH_ACTION, // Trying to find an action that matches the caller's request - PSO_CHECK_CONDITION, // Checking the condition that preceded the found action - PSO_DO_ACTION, // Performing Action - PSO_COMPLETE // Completed processing of this request -} PSO_STATE; - -typedef struct _D3_CMP_CAL { - UINT32 D3Cmp0NCal :3; - UINT32 Reserved34 :2; - UINT32 D3Cmp0PCal :3; - UINT32 Reserved89 :2; - UINT32 D3Cmp1NCal :3; - UINT32 Reserved1314 :2; - UINT32 D3Cmp1PCal :3; - UINT32 Reserved1819 :2; - UINT32 D3Cmp2NCal :3; - UINT32 Reserved2324 :2; - UINT32 D3Cmp2PCal :3; - UINT32 Reserved2831 :2; -} D3_CMP_CAL; - -/*---------------------------------------------------------------------------- - * PROTOTYPES OF LOCAL FUNCTIONS - * - *---------------------------------------------------------------------------- - */ -BOOLEAN - STATIC - MemPSODoActionODT ( - IN OUT MEM_NB_BLOCK *NBPtr, - IN UINT8 *Buffer - ); - - BOOLEAN - STATIC - MemPSODoActionAddrTmg ( - IN OUT MEM_NB_BLOCK *NBPtr, - IN UINT8 *Buffer - ); - - BOOLEAN - STATIC - MemPSODoActionODCControl ( - IN OUT MEM_NB_BLOCK *NBPtr, - IN UINT8 *Buffer - ); - - BOOLEAN - STATIC - MemPSODoActionSlewRate ( - IN OUT MEM_NB_BLOCK *NBPtr, - IN UINT8 *Buffer - ); - -BOOLEAN -STATIC -MemPSODoActionGetFreqLimit ( - IN OUT MEM_NB_BLOCK *NBPtr, - IN UINT8 *Buffer - ); - -BOOLEAN -STATIC -MemCheckRankType ( - IN CH_DEF_STRUCT *CurrentChannel, - IN UINT16 RankType - ); -/*---------------------------------------------------------------------------- - * EXPORTED FUNCTIONS - * - *---------------------------------------------------------------------------- - */ - - -/* -----------------------------------------------------------------------------*/ -/** - * - * Process Conditional Platform Specific Overrides - * - * @param[in] PlatformMemoryConfiguration - Pointer to Platform config table - * @param[in] NBPtr - Pointer to Current NBBlock - * @param[in] PsoAction - Action type - * @param[in] Dimm - Dimm Number - * - * @return BOOLEAN - TRUE : Action was performed - * FALSE: Action was not performed - * - * ---------------------------------------------------------------------------- - */ -BOOLEAN -MemProcessConditionalOverrides ( - IN PSO_TABLE *PlatformMemoryConfiguration, - IN OUT MEM_NB_BLOCK *NBPtr, - IN UINT8 PsoAction, - IN UINT8 Dimm - ) -{ - BOOLEAN Result; - MEM_TECH_BLOCK *TechPtr; - UINT8 *Buffer; - UINT8 *ConditionStartPtr; - UINT8 *ActionStartPtr; - UINT8 *SpdBufferPtr; - UINT8 i; - UINT8 DimmMask; - UINT8 CurDimmMask; - BOOLEAN Condition; - BOOLEAN TmpCond; - PSO_STATE State; - ASSERT (PlatformMemoryConfiguration != NULL); - ASSERT (NBPtr != NULL); - ASSERT ((PsoAction >= PSO_ACTION_MIN) && (PsoAction <= PSO_ACTION_MAX)); - // - // Set up local data - // - TechPtr = NBPtr->TechPtr; - Buffer = PlatformMemoryConfiguration; - State = PSO_FIND_CONDITION; - ConditionStartPtr = NULL; - ActionStartPtr = NULL; - Condition = FALSE; - DimmMask = 0xFF; - CurDimmMask = 0xFF; - Result = FALSE; - - if (Dimm != 0xFF) { - DimmMask = ( 1 << Dimm); - } - DimmMask &= (UINT8) (NBPtr->ChannelPtr->ChDimmValid & 0xFF); - if (DimmMask == 0) { - return Result; - } - - // - // Search for Condition Entry - // - while (State != PSO_COMPLETE) { - switch (State) { - // - // Searching for initial Condition statement - // - case PSO_FIND_CONDITION: - ASSERT (Buffer != NULL); - while (Buffer[PSO_TYPE] != PSO_CONDITION_AND) { - // - // If end of table is reached, Change state to complete and break. - // - if (Buffer[PSO_TYPE] == PSO_END) { - State = PSO_COMPLETE; - break; - } - // - // Otherwise, increment Buffer Pointer to the next PSO entry. - // - Buffer += (Buffer[PSO_LENGTH] + 2); - } - // - // If Condition statement has been found, save the Condition Start Pointer, - // and change to next state - // - if (State != PSO_COMPLETE) { - ASSERT (Buffer != NULL); - State = PSO_FIND_ACTION; - ConditionStartPtr = Buffer; - Buffer += (Buffer[PSO_LENGTH] + 2); - } - break; - // - // Searching for an action that matches the caller's request - // - case PSO_FIND_ACTION: - ASSERT (Buffer != NULL); - while (Buffer[PSO_TYPE] != PsoAction) { - // - // If non-conditional entry, change state to complete and break. - // - if ((Buffer[PSO_TYPE] < CONDITIONAL_PSO_MIN) || (Buffer[PSO_TYPE] > CONDITIONAL_PSO_MAX)) { - State = PSO_COMPLETE; - break; - } - // - // Check for the Start of a new condition block - // - if (Buffer[PSO_TYPE] == PSO_CONDITION_AND) { - ConditionStartPtr = Buffer; - } - // - // Otherwise, increment buffer pointer to the next PSO entry. - // - Buffer += (Buffer[PSO_LENGTH] + 2); - } - // - // If Action statement has been found, Save the Action Start Pointer, Reset Buffer to Condition Start - // and Change to next state. - // - if (State != PSO_COMPLETE) { - State = PSO_CHECK_CONDITION; - ASSERT (Buffer != NULL); - ActionStartPtr = Buffer; - Buffer = ConditionStartPtr; - Condition = TRUE; - } - break; - // - // Checking the condition that preceded the found action - // - case PSO_CHECK_CONDITION: - ASSERT (Buffer != NULL); - // - // Point to the next Condition - // - Buffer += (Buffer[PSO_LENGTH] + 2); - ASSERT ((Buffer[PSO_TYPE] >= CONDITIONAL_PSO_MIN) && (Buffer[PSO_TYPE] <= CONDITIONAL_PSO_MAX)); - // - // This section has already been checked for invalid statements so just exit on ACTION_xx - // - if ((Buffer[PSO_TYPE] >= PSO_ACTION_MIN) && (Buffer[PSO_TYPE] <= PSO_ACTION_MAX)) { - if (Condition) { - ASSERT (Buffer != NULL); - State = PSO_DO_ACTION; // Perform the Action - } else { - State = PSO_FIND_CONDITION; // Go back and look for another condition/action - } - Buffer = ActionStartPtr; // Restore Action Pointer - break; - } - switch (Buffer[PSO_TYPE]) { - - case PSO_CONDITION_AND: - // - // Additional CONDITION_AND is ORed with Previous ones, so if Previous result is TRUE - // just restore action pointer and perform the action. - // - if (Condition) { - State = PSO_DO_ACTION; - Buffer = ActionStartPtr; - } else { - // - // If its false, Start over and evaluate next cond. - // reset the Current Dimm Mask - // - Condition = TRUE; - CurDimmMask = 0xFF; - } - break; - - case PSO_CONDITION_LOC: - // - // Condition location - // - CurDimmMask = Buffer[4]; - Condition &= ( ((Buffer[2] & (1 << (NBPtr->MCTPtr->SocketId))) != 0) && - ((Buffer[3] & (1 << (NBPtr->ChannelPtr->ChannelID))) != 0) && - ((CurDimmMask & DimmMask) != 0) ); - break; - - case PSO_CONDITION_SPD: - // - // Condition SPD - // - TmpCond = FALSE; - for (i = 0; i < MAX_DIMMS_PER_CHANNEL; i ++) { - if ( ((DimmMask & CurDimmMask) & ((UINT16) (1 << i))) != 0) { - if (TechPtr->GetDimmSpdBuffer (TechPtr, &SpdBufferPtr, i)) { - TmpCond |= ( (SpdBufferPtr[Buffer[2]] & Buffer[3]) == Buffer[4]); - } - } - } - Condition &= TmpCond; - break; - - case PSO_CONDITION_REG: - // - // Condition Register - unsupported at this time - // - break; - - default: - ASSERT (FALSE); - } // End Condition Switch - break; - - case PSO_DO_ACTION: - ASSERT (Buffer != NULL); - // - // Performing Action - // - if ((Buffer[PSO_TYPE] < PSO_ACTION_MIN) || (Buffer[PSO_TYPE] > PSO_ACTION_MAX)) { - State = PSO_COMPLETE; - } - if (Buffer[PSO_TYPE] == PsoAction) { - switch (Buffer[PSO_TYPE]) { - case PSO_ACTION_ODT: - Result = MemPSODoActionODT (NBPtr, &Buffer[PSO_DATA]); - break; - case PSO_ACTION_ADDRTMG: - Result = MemPSODoActionAddrTmg (NBPtr, &Buffer[PSO_DATA]); - break; - case PSO_ACTION_ODCCONTROL: - Result = MemPSODoActionODCControl (NBPtr, &Buffer[PSO_DATA]); - break; - case PSO_ACTION_SLEWRATE: - Result = MemPSODoActionSlewRate (NBPtr, &Buffer[PSO_DATA]); - break; - case PSO_ACTION_SPEEDLIMIT: - Result = MemPSODoActionGetFreqLimit (NBPtr, &Buffer[PSO_DATA]); - break; - case PSO_ACTION_REG: - break; - default: - ASSERT (FALSE); - } // End Action Switch - // - // If Action was performed, mark complete. - // - if (Result) { - State = PSO_COMPLETE; - } - }// End Action - - // - // Point to the next PSO Entry - // - Buffer += (Buffer[PSO_LENGTH] + 2); - break; - - case PSO_COMPLETE: - // - // Completed processing of this request - // - break; - - default: - ASSERT (FALSE); - } // End State Switch - - } // End While - - return Result; -} - -/*---------------------------------------------------------------------------- - * LOCAL FUNCTIONS - * - *---------------------------------------------------------------------------- - */ - -/* -----------------------------------------------------------------------------*/ -/** - * Perform ODT Platform Override - * - * @param[in] NBPtr - Pointer to Current NBBlock - * @param[in] Buffer - Pointer to the Action Command Data (w/o Type and Len) - * - * @return BOOLEAN - TRUE : Action was performed - * FALSE: Action was not performed - * - * ---------------------------------------------------------------------------- - */ -BOOLEAN -STATIC -MemPSODoActionODT ( - IN OUT MEM_NB_BLOCK *NBPtr, - IN UINT8 *Buffer - ) -{ - BOOLEAN Result; - UINT32 Speed; - UINT8 Dimms; - UINT8 i; - UINT8 QR_Dimms; - Result = FALSE; - Speed = ((UINT32) 1 << (NBPtr->DCTPtr->Timings.Speed / 66)); - Dimms = NBPtr->ChannelPtr->Dimms; - QR_Dimms = 0; - for (i = 0; i < MAX_DIMMS_PER_CHANNEL; i++) { - if (((NBPtr->ChannelPtr->DimmQrPresent & (UINT16) (1 << i)) != 0) && (i < 2)) { - QR_Dimms ++; - } - } - if ((Speed & ((UINT32 *) Buffer)[0]) != 0) { - if ((((UINT8) (1 << (Dimms - 1)) & Buffer[4]) != 0) || (Buffer[4] == ANY_NUM)) { - if (((QR_Dimms == 0) && (Buffer[5] == NO_DIMM)) || - ((QR_Dimms > 0) && (((UINT8) (1 << (QR_Dimms - 1)) & Buffer[5]) != 0)) || - (Buffer[5] == ANY_NUM)) { - NBPtr->PsPtr->DramTerm = Buffer[6]; - NBPtr->PsPtr->QR_DramTerm = Buffer[7]; - NBPtr->PsPtr->DynamicDramTerm = Buffer[8]; - Result = TRUE; - IDS_HDT_CONSOLE (MEM_FLOW, " Platform Override: DramTerm:%02x, QRDramTerm:%02x, DynDramTerm:%02x\n", Buffer[6], Buffer[7], Buffer[8]); - } - } - } - return Result; - } - - /* -----------------------------------------------------------------------------*/ -/** - * Perform Address Timing Platform Override - * - * @param[in] NBPtr - Pointer to Current NBBlock - * @param[in] Buffer - Pointer to the Action Command Data (w/o Type and Len) - * - * @return BOOLEAN - TRUE : Action was performed - * FALSE: Action was not performed - * - * ---------------------------------------------------------------------------- - */ -BOOLEAN -STATIC -MemPSODoActionAddrTmg ( - IN OUT MEM_NB_BLOCK *NBPtr, - IN UINT8 *Buffer - ) -{ - BOOLEAN Result; - CH_DEF_STRUCT *ChannelPtr; - UINT32 Speed; - UINT16 DimmConfig; - - Result = FALSE; - ChannelPtr = NBPtr->ChannelPtr; - Speed = ((UINT32) 1 << (NBPtr->DCTPtr->Timings.Speed / 66)); - DimmConfig = *(UINT16 *) &(Buffer[4]); - - if ((Speed & ((UINT32 *) Buffer)[0]) != 0) { - if (MemCheckRankType (ChannelPtr, DimmConfig)) { - ChannelPtr->DctAddrTmg = *(UINT32*) &(Buffer[6]); - Result = TRUE; - IDS_HDT_CONSOLE (MEM_FLOW, " Platform Override: Address Timing:%08x\n", *(UINT32*) &(Buffer[6])); - } - } - return Result; - } - - /* -----------------------------------------------------------------------------*/ -/** - * Perform Drive Strength Platform Override - * - * @param[in] NBPtr - Pointer to Current NBBlock - * @param[in] Buffer - Pointer to the Action Command Data (w/o Type and Len) - * - * @return BOOLEAN - TRUE : Action was performed - * FALSE: Action was not performed - * - * ---------------------------------------------------------------------------- - */ -BOOLEAN -STATIC -MemPSODoActionODCControl ( - IN OUT MEM_NB_BLOCK *NBPtr, - IN UINT8 *Buffer - ) -{ - BOOLEAN Result; - CH_DEF_STRUCT *ChannelPtr; - UINT32 Speed; - UINT16 DimmConfig; - - Result = FALSE; - ChannelPtr = NBPtr->ChannelPtr; - Speed = ((UINT32) 1 << (NBPtr->DCTPtr->Timings.Speed / 66)); - DimmConfig = *(UINT16 *) &(Buffer[4]); - - if ((Speed & ((UINT32 *) Buffer)[0]) != 0) { - if (MemCheckRankType (ChannelPtr, DimmConfig)) { - ChannelPtr->DctOdcCtl = *(UINT32*) &(Buffer[6]); - Result = TRUE; - IDS_HDT_CONSOLE (MEM_FLOW, " Platform Override: ODC Control:%08x\n", *(UINT32*)&(Buffer[6])); - } - } - return Result; - } - - /* -----------------------------------------------------------------------------*/ -/** - * Perform Slew Rate Platform Override - * - * @param[in] NBPtr - Pointer to Current NBBlock - * @param[in] Buffer - Pointer to the Action Command Data (w/o Type and Len) - * - * @return BOOLEAN - TRUE : Action was performed - * FALSE: Action was not performed - * - * ---------------------------------------------------------------------------- - */ -BOOLEAN -STATIC -MemPSODoActionSlewRate ( - IN OUT MEM_NB_BLOCK *NBPtr, - IN UINT8 *Buffer - ) -{ - BOOLEAN Result; - CH_DEF_STRUCT *ChannelPtr; - UINT32 Speed; - UINT16 DimmConfig; - - Result = FALSE; - ChannelPtr = NBPtr->ChannelPtr; - Speed = ((UINT32) 1 << (NBPtr->DCTPtr->Timings.Speed / 66)); - DimmConfig = *(UINT16 *) &(Buffer[4]); - - if ((Speed & ((UINT32 *) Buffer)[0]) != 0) { - if (MemCheckRankType (ChannelPtr, DimmConfig)) { - MemNSetBitFieldNb (NBPtr, BFD3Cmp0NCal, ((D3_CMP_CAL *) &(Buffer[6]))->D3Cmp0NCal ); - MemNSetBitFieldNb (NBPtr, BFD3Cmp0PCal, ((D3_CMP_CAL *) &(Buffer[6]))->D3Cmp0PCal ); - MemNSetBitFieldNb (NBPtr, BFD3Cmp1NCal, ((D3_CMP_CAL *) &(Buffer[6]))->D3Cmp1NCal ); - MemNSetBitFieldNb (NBPtr, BFD3Cmp1PCal, ((D3_CMP_CAL *) &(Buffer[6]))->D3Cmp1PCal ); - MemNSetBitFieldNb (NBPtr, BFD3Cmp2NCal, ((D3_CMP_CAL *) &(Buffer[6]))->D3Cmp2NCal ); - MemNSetBitFieldNb (NBPtr, BFD3Cmp2PCal, ((D3_CMP_CAL *) &(Buffer[6]))->D3Cmp2PCal ); - Result = TRUE; - IDS_HDT_CONSOLE (MEM_FLOW, " Platform Override: Slew Rate:%08x\n", *(UINT32 *) &(Buffer[6])); - } - } - return Result; - } - -/* -----------------------------------------------------------------------------*/ -/** - * - * This function overrides the POR supported speed for a specific config - * - * @param[in] NBPtr - Pointer to Current NBBlock - * @param[in] Buffer - Pointer to the Action Command Data (w/o Type and Len) - * - * @return BOOLEAN - TRUE : Action was performed - * FALSE: Action was not performed - * - */ -BOOLEAN -STATIC -MemPSODoActionGetFreqLimit ( - IN OUT MEM_NB_BLOCK *NBPtr, - IN UINT8 *Buffer - ) -{ - BOOLEAN Result; - CH_DEF_STRUCT *ChannelPtr; - DCT_STRUCT *DCTPtr; - UINT16 DimmConfig; - UINT16 SpeedLimit; - - Result = FALSE; - ChannelPtr = NBPtr->ChannelPtr; - DCTPtr = NBPtr->DCTPtr; - DimmConfig = *(UINT16*) &(Buffer[0]); - SpeedLimit = 0; - // - // Match number of dimms, then Rank Type - // - if (ChannelPtr->Dimms == Buffer[2]) { - if (MemCheckRankType (ChannelPtr, DimmConfig)) { - // - // Select speed based on current voltage - // - if (NBPtr->RefPtr->DDR3Voltage == VOLT1_5) { - SpeedLimit = *(UINT16*) &(Buffer[3]); - } else if (NBPtr->RefPtr->DDR3Voltage == VOLT1_25) { - SpeedLimit = *(UINT16*) &(Buffer[7]); - } else { - SpeedLimit = *(UINT16*) &(Buffer[5]); - } - // - // Set the Speed limit - // - if (DCTPtr->Timings.TargetSpeed > SpeedLimit) { - DCTPtr->Timings.TargetSpeed = SpeedLimit; - } - Result = TRUE; - IDS_HDT_CONSOLE (MEM_FLOW, " Platform Override: Max Memory Speed for Channel %d: %d\n", NBPtr->Channel, SpeedLimit); - } - } - return Result; -} - - /* -----------------------------------------------------------------------------*/ -/** - * - * This function matches a particular Rank Type Mask to the installed - * DIMM configuration on the provided channel. - * - * @param[in] *CurrentChannel Pointer to CH_DEF_STRUCT - * @param[in] RankType Mask of rank type to match - * - * @return BOOLEAN - TRUE : Rank types match - * FALSE: Rank types do not match - * - */ -BOOLEAN -STATIC -MemCheckRankType ( - IN CH_DEF_STRUCT *CurrentChannel, - IN UINT16 RankType - ) -{ - BOOLEAN Result; - UINT8 i; - UINT16 DIMMRankType; - - DIMMRankType = MemAGetPsRankType (CurrentChannel); - Result = TRUE; - for (i = 0; i < MAX_DIMMS_PER_CHANNEL; i++) { - if ( ((DIMMRankType & (0x0F << (i << 2))) + (RankType & (0x0F << (i << 2)))) != 0) { - Result &= (((DIMMRankType & (0x0F << (i << 2))) & ( RankType & ( 0x0F << ( i << 2)))) != 0); - } - if (!Result) { - break; - } - } - return Result; -} \ No newline at end of file diff --git a/src/vendorcode/amd/agesa/f12/Proc/Mem/Main/mmEcc.c b/src/vendorcode/amd/agesa/f12/Proc/Mem/Main/mmEcc.c deleted file mode 100644 index cdf02e3273..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/Mem/Main/mmEcc.c +++ /dev/null @@ -1,129 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * mmEcc.c - * - * Main Memory Feature implementation file for ECC Initialization - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: (Mem/Main) - * @e \$Revision: 49885 $ @e \$Date: 2011-03-30 13:51:08 +0800 (Wed, 30 Mar 2011) $ - * - **/ -/***************************************************************************** -* -* Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* *************************************************************************** -* -*/ - -/* - *---------------------------------------------------------------------------- - * MODULES USED - * - *---------------------------------------------------------------------------- - */ - - -#include "Porting.h" -#include "AGESA.h" -#include "Ids.h" -#include "cpuRegisters.h" -#include "OptionMemory.h" -#include "mm.h" -#include "mn.h" -#include "mt.h" -#include "ma.h" -#include "mfmemclr.h" -#include "Filecode.h" -CODE_GROUP (G1_PEICC) -RDATA_GROUP (G1_PEICC) - -#define FILECODE PROC_MEM_MAIN_MMECC_FILECODE - -/*----------------------------------------------------------------------------- -* EXPORTED FUNCTIONS -* -*----------------------------------------------------------------------------- -*/ -BOOLEAN -MemMEcc ( - IN OUT MEM_MAIN_DATA_BLOCK *mmPtr - ); - -/* -----------------------------------------------------------------------------*/ -/** - * - * - * - * - * @param[in,out] *mmPtr - Pointer to the MEM_MAIN_DATA_BLOCK - * - * @return TRUE - No fatal error occurs. - * @return FALSE - Fatal error occurs. - */ -BOOLEAN -MemMEcc ( - IN OUT MEM_MAIN_DATA_BLOCK *mmPtr - ) -{ - UINT8 Die; - MEM_SHARED_DATA *SharedPtr; - MEM_PARAMETER_STRUCT *RefPtr; - BOOLEAN RetVal; - - RetVal = TRUE; - RefPtr = mmPtr->MemPtr->ParameterListPtr; - SharedPtr = mmPtr->mmSharedPtr; - - // - // Run Northbridge-specific ECC initialization feature for each die. - // - SharedPtr->AllECC = FALSE; - if (RefPtr->EnableEccFeature) { - SharedPtr->AllECC = TRUE; - AGESA_TESTPOINT (TpProcMemEccInitialization, &(mmPtr->MemPtr->StdHeader)); - - for (Die = 0 ; Die < mmPtr->DieCount ; Die ++ ) { - mmPtr->NBPtr[Die].FeatPtr->CheckEcc (&(mmPtr->NBPtr[Die])); - RetVal &= (BOOLEAN) (mmPtr->NBPtr[Die].MCTPtr->ErrCode < AGESA_FATAL); - } - if (SharedPtr->AllECC == TRUE) { - RefPtr->GStatus[GsbAllECCDimms] = TRUE; - // Sync mem clear before setting scrub rate. - for (Die = 0; Die < mmPtr->DieCount; Die++) { - MemFMctMemClr_Sync (&(mmPtr->NBPtr[Die])); - } - } - } - // Scrubber control - for (Die = 0 ; Die < mmPtr->DieCount ; Die ++ ) { - mmPtr->NBPtr[Die].FeatPtr->InitEcc (&(mmPtr->NBPtr[Die])); - } - return RetVal; -} diff --git a/src/vendorcode/amd/agesa/f12/Proc/Mem/Main/mmExcludeDimm.c b/src/vendorcode/amd/agesa/f12/Proc/Mem/Main/mmExcludeDimm.c deleted file mode 100644 index e2415cc498..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/Mem/Main/mmExcludeDimm.c +++ /dev/null @@ -1,238 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * mmExcludeDimm.c - * - * Main Memory Feature implementation file for RAS DIMM Exclude Feature - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: (Mem/Main) - * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $ - * - **/ -/***************************************************************************** -* -* Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* *************************************************************************** -* -*/ - -/* - *---------------------------------------------------------------------------- - * MODULES USED - * - *---------------------------------------------------------------------------- - */ - - -#include "AGESA.h" -#include "Ids.h" -#include "mport.h" -#include "amdlib.h" -#include "OptionMemory.h" -#include "mm.h" -#include "mn.h" -#include "GeneralServices.h" -#include "Filecode.h" -CODE_GROUP (G1_PEICC) -RDATA_GROUP (G1_PEICC) - -#define FILECODE PROC_MEM_MAIN_MMEXCLUDEDIMM_FILECODE - -extern MEM_FEAT_BLOCK_MAIN MemFeatMain; -/*----------------------------------------------------------------------------- -* EXPORTED FUNCTIONS -* -*----------------------------------------------------------------------------- -*/ -BOOLEAN -MemMRASExcludeDIMM ( - IN OUT MEM_MAIN_DATA_BLOCK *MemMainPtr - ); - -/* -----------------------------------------------------------------------------*/ -/** - * - * Check and disable Chip selects that fail training on all nodes. - * - * @param[in,out] *MemMainPtr - Pointer to the MEM_MAIN_DATA_BLOCK - * - * @return TRUE - No fatal error occurs. - * @return FALSE - Fatal error occurs. - */ -BOOLEAN -MemMRASExcludeDIMM ( - IN OUT MEM_MAIN_DATA_BLOCK *MemMainPtr - ) -{ - UINT8 Node; - BOOLEAN IsEnabled; - BOOLEAN RetVal; - BOOLEAN IsChannelIntlvEnabled[MAX_NODES_SUPPORTED]; - UINT8 FirstEnabledNode; - UINT32 BottomIO; - MEM_NB_BLOCK *NBPtr; - MEM_PARAMETER_STRUCT *RefPtr; - S_UINT64 SMsr; - - FirstEnabledNode = 0; - IsEnabled = FALSE; - RetVal = TRUE; - NBPtr = MemMainPtr->NBPtr; - RefPtr = NBPtr[BSP_DIE].RefPtr; - for (Node = 0; Node < MemMainPtr->DieCount; Node++) { - if (NBPtr[Node].FeatPtr->ExcludeDIMM (&NBPtr[Node])) { - if (!IsEnabled) { - // Record the first node that has exclude dimm enabled - FirstEnabledNode = Node; - IsEnabled = TRUE; - } - } - } - - // Force memory address remap when we want to undo 1TB hoisting - if (NBPtr->SharedPtr->UndoHoistingAbove1TB) { - IsEnabled = TRUE; - } - - if (IsEnabled) { - // Check if all nodes have all dimms excluded. If yes, fatal exit - NBPtr[BSP_DIE].SharedPtr->CurrentNodeSysBase = 0; - BottomIO = (NBPtr[BSP_DIE].RefPtr->BottomIo & 0xF8) << 8; - // If the first node that has excluded dimms does not have a system base smaller - // than bottomIO, then we don't need to reset the GStatus, as we don't need to - // remap memory hole. - if (NBPtr[FirstEnabledNode].MCTPtr->NodeSysBase < BottomIO) { - RefPtr->GStatus[GsbHWHole] = FALSE; - RefPtr->GStatus[GsbSpIntRemapHole] = FALSE; - RefPtr->GStatus[GsbSoftHole] = FALSE; - RefPtr->HoleBase = 0; - RefPtr->SysLimit = 0; - } - // If Node Interleaving has been executed before the remapping then we need to - // start from the first node. - // There may be a few senarios: - // 1. Node interleaving is not enabled before the remap, and still cannot be enabled after - // remap - // 2. Node interleaving cannot be enabled before the remap, but it can be enabled after - // remap - // 3. Node interleaving is enabled before the remap, but it cannot be enabled after the remap - if (NBPtr->SharedPtr->NodeIntlv.IsValid) { - FirstEnabledNode = 0; - } - - for (Node = 0; Node < MemMainPtr->DieCount; Node++) { - IsChannelIntlvEnabled [Node] = FALSE; - // Check if node interleaving has been enabled on this node - // if yes, disable it. - if (NBPtr[Node].GetBitField (&NBPtr[Node], BFDramIntlvEn) != 0) { - NBPtr[Node].SetBitField (&NBPtr[Node], BFDramIntlvEn, 0); - NBPtr[Node].SetBitField (&NBPtr[Node], BFDramIntlvSel, 0); - } - if (Node >= FirstEnabledNode) { - // Remap memory on nodes with node number larger than the first node that has excluded dimms. - // If channel interleaving has already been enabled, need to disable it before remapping memory. - if (NBPtr[Node].GetBitField (&NBPtr[Node], BFDctSelIntLvEn) != 0) { - NBPtr[Node].SetBitField (&NBPtr[Node], BFDctSelIntLvEn, 0); - IsChannelIntlvEnabled [Node] = TRUE; - } - NBPtr[Node].MCTPtr->Status[SbHWHole] = FALSE; - NBPtr[Node].MCTPtr->Status[SbSWNodeHole] = FALSE; - NBPtr[Node].SetBitField (&NBPtr[Node], BFDctSelBaseAddr, 0); - NBPtr[Node].SetBitField (&NBPtr[Node], BFDctSelHiRngEn, 0); - NBPtr[Node].SetBitField (&NBPtr[Node], BFDctSelHi, 0); - NBPtr[Node].SetBitField (&NBPtr[Node], BFDctSelBaseOffset, 0); - NBPtr[Node].SetBitField (&NBPtr[Node], BFDramHoleAddrReg, 0); - NBPtr[Node].HtMemMapInit (&NBPtr[Node]); - } else if (NBPtr[Node].MCTPtr->NodeMemSize != 0) { - // No change is needed in the memory map of this node. - // Need to adjust the current system base for other nodes processed later. - NBPtr[Node].SharedPtr->CurrentNodeSysBase = (NBPtr[Node].MCTPtr->NodeSysLimit + 1) & 0xFFFFFFF0; - RefPtr->SysLimit = NBPtr[Node].MCTPtr->NodeSysLimit; - // If the current node does not have the memory hole, then set DramHoleAddrReg to be 0. - // If memory hoisting is enabled later by other node, SyncAddrMapToAllNodes will set the base - // and DramMemHoistValid. - // Otherwise, do not change the register value, as we need to keep DramHoleOffset unchanged, as well - // DramHoleValid. - if (!NBPtr[Node].MCTPtr->Status[SbHWHole]) { - NBPtr[Node].SetBitField (&NBPtr[Node], BFDramHoleAddrReg, 0); - } - } - } - - for (Node = 0; Node < MemMainPtr->DieCount; Node++) { - NBPtr[Node].SyncAddrMapToAllNodes (&NBPtr[Node]); - } - - LibAmdMsrRead (TOP_MEM, (UINT64 *)&SMsr, &NBPtr->MemPtr->StdHeader); - // Only when TOM is set can CpuMemTyping be re-run - if ((SMsr.hi == 0) && (SMsr.lo == 0)) { - if (RefPtr->SysLimit != 0) { - NBPtr[BSP_DIE].CpuMemTyping (&NBPtr[BSP_DIE]); - - // When 1TB hoisting is not supported, TOP_MEM2 cannot exceed HT reserved region base. - if ((RefPtr->SysLimit >= HT_REGION_BASE_RJ16) && (NBPtr->SharedPtr->UndoHoistingAbove1TB)) { - SMsr.hi = HT_REGION_BASE_RJ16 >> (32 - 16); - SMsr.lo = HT_REGION_BASE_RJ16 << 16; - LibAmdMsrWrite (TOP_MEM2, (UINT64 *)&SMsr, &NBPtr->MemPtr->StdHeader); - IDS_HDT_CONSOLE (MEM_FLOW, "TOP_MEM2: %08x0000\n", HT_REGION_BASE_RJ16); - RefPtr->Sub1THoleBase = HT_REGION_BASE_RJ16; - RefPtr->SysLimit = HT_REGION_BASE_RJ16 - 1; - } - } - } - - // Re-run node interleaving if it has been exeucuted before the remap - if (NBPtr->SharedPtr->NodeIntlv.IsValid) { - MemFeatMain.InterleaveNodes (MemMainPtr); - } - - // Re-enable channel interleaving if it was enabled before remapping memory - for (Node = 0; Node < MemMainPtr->DieCount; Node++) { - if (IsChannelIntlvEnabled [Node]) { - NBPtr[Node].FeatPtr->InterleaveChannels (&NBPtr[Node]); - } - } - - // Reset UndoHoistingAbove1TB if it was previously set - NBPtr->SharedPtr->UndoHoistingAbove1TB = FALSE; - } - - // if all dimms on all nodes are excluded, do fatal exit - if (RefPtr->SysLimit == 0) { - PutEventLog (AGESA_FATAL, MEM_ERROR_NO_DIMM_FOUND_ON_SYSTEM, 0, 0, 0, 0, &NBPtr->MemPtr->StdHeader); - SetMemError (AGESA_FATAL, NBPtr[BSP_DIE].MCTPtr); - ASSERT (FALSE); - } - - for (Node = 0; Node < MemMainPtr->DieCount; Node ++) { - RetVal &= (BOOLEAN) (NBPtr[Node].MCTPtr->ErrCode < AGESA_FATAL); - } - - return RetVal; -} diff --git a/src/vendorcode/amd/agesa/f12/Proc/Mem/Main/mmLvDdr3.c b/src/vendorcode/amd/agesa/f12/Proc/Mem/Main/mmLvDdr3.c deleted file mode 100644 index 156ab1ee62..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/Mem/Main/mmLvDdr3.c +++ /dev/null @@ -1,285 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * mmLvDdr3.c - * - * Main Memory Feature implementation file for low voltage DDR3 support - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: (Mem/Main) - * @e \$Revision: 47408 $ @e \$Date: 2011-02-19 00:56:31 +0800 (Sat, 19 Feb 2011) $ - * - **/ -/***************************************************************************** -* -* Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* *************************************************************************** -* -*/ - -/* - *---------------------------------------------------------------------------- - * MODULES USED - * - *---------------------------------------------------------------------------- - */ - - -#include "AGESA.h" -#include "Ids.h" -#include "amdlib.h" -#include "OptionMemory.h" -#include "mmlvddr3.h" -#include "mm.h" -#include "mn.h" -#include "GeneralServices.h" -#include "Filecode.h" -CODE_GROUP (G1_PEICC) -RDATA_GROUP (G1_PEICC) - -#define FILECODE PROC_MEM_MAIN_MMLVDDR3_FILECODE - -extern MEM_FEAT_BLOCK_MAIN MemFeatMain; -/*----------------------------------------------------------------------------- -* EXPORTED FUNCTIONS -* -*----------------------------------------------------------------------------- -*/ - -/* -----------------------------------------------------------------------------*/ -/** - * - * Find the common supported voltage on all nodes. - * - * @param[in,out] *MemMainPtr - Pointer to the MEM_MAIN_DATA_BLOCK - * - * @return TRUE - No fatal error occurs. - * @return FALSE - Fatal error occurs. - */ -BOOLEAN -MemMLvDdr3 ( - IN OUT MEM_MAIN_DATA_BLOCK *MemMainPtr - ) -{ - UINT8 Node; - BOOLEAN RetVal; - BOOLEAN SecondLoop; - MEM_NB_BLOCK *NBPtr; - MEM_PARAMETER_STRUCT *ParameterPtr; - MEM_SHARED_DATA *mmSharedPtr; - - NBPtr = MemMainPtr->NBPtr; - mmSharedPtr = MemMainPtr->mmSharedPtr; - ParameterPtr = MemMainPtr->MemPtr->ParameterListPtr; - mmSharedPtr->VoltageMap = 0xFF; - SecondLoop = FALSE; - RetVal = TRUE; - - for (Node = 0; Node < MemMainPtr->DieCount; Node++) { - NBPtr[Node].FeatPtr->LvDdr3 (&NBPtr[Node]); - // Check if there is no common supported voltage - if ((mmSharedPtr->VoltageMap == 0) && !SecondLoop) { - // restart node loop by setting node to 0xFF - Node = 0xFF; - SecondLoop = TRUE; - } - } - - if (mmSharedPtr->VoltageMap == 0) { - IDS_HDT_CONSOLE (MEM_FLOW, "\nNo commonly supported VDDIO is found.\n"); - PutEventLog (AGESA_WARNING, MEM_WARNING_NO_COMMONLY_SUPPORTED_VDDIO, 0, 0, 0, 0, &(NBPtr[BSP_DIE].MemPtr->StdHeader)); - SetMemError (AGESA_WARNING, NBPtr[BSP_DIE].MCTPtr); - // When there is no commonly supported VDDIO, use 1.35V as the temporal VDDIO - ParameterPtr->DDR3Voltage = VOLT1_35; - } else { - IDS_HDT_CONSOLE (MEM_FLOW, "\nCommonly supported VDDIO is: %s%s%s.\n", ((mmSharedPtr->VoltageMap & 1) != 0) ? "1.5V, " : "", ((mmSharedPtr->VoltageMap & 2) != 0) ? "1.35V, " : "", ((mmSharedPtr->VoltageMap & 4) != 0) ? "1.25V" : ""); - ParameterPtr->DDR3Voltage = CONVERT_ENCODED_TO_VDDIO (LibAmdBitScanReverse (mmSharedPtr->VoltageMap)); - } - - for (Node = 0; Node < MemMainPtr->DieCount; Node ++) { - // Check if the voltage needs force to 1.5V - NBPtr[Node].FamilySpecificHook[ForceLvDimmVoltage] (&NBPtr[Node], MemMainPtr); - - RetVal &= (BOOLEAN) (NBPtr[Node].MCTPtr->ErrCode < AGESA_FATAL); - } - - return RetVal; -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * Find the common supported voltage on all nodes, taken into account of the - * user option for performance and power saving. - * - * @param[in,out] *MemMainPtr - Pointer to the MEM_MAIN_DATA_BLOCK - * - * @return TRUE - No fatal error occurs. - * @return FALSE - Fatal error occurs. - */ -BOOLEAN -MemMLvDdr3PerformanceEnhPre ( - IN OUT MEM_MAIN_DATA_BLOCK *MemMainPtr - ) -{ - UINT8 Node; - BOOLEAN RetVal; - DIMM_VOLTAGE VDDIO; - MEM_NB_BLOCK *NBPtr; - MEM_PARAMETER_STRUCT *ParameterPtr; - MEM_SHARED_DATA *mmSharedPtr; - PLATFORM_POWER_POLICY PowerPolicy; - - NBPtr = MemMainPtr->NBPtr; - mmSharedPtr = MemMainPtr->mmSharedPtr; - ParameterPtr = MemMainPtr->MemPtr->ParameterListPtr; - PowerPolicy = MemMainPtr->MemPtr->PlatFormConfig->PlatformProfile.PlatformPowerPolicy; - - IDS_OPTION_HOOK (IDS_SKIP_PERFORMANCE_OPT, &PowerPolicy, &NBPtr->MemPtr->StdHeader); - IDS_HDT_CONSOLE (MEM_FLOW, (PowerPolicy == Performance) ? "\nMaximize Performance\n" : "\nMaximize Battery Life\n"); - - if (ParameterPtr->DDR3Voltage != VOLT_INITIAL) { - mmSharedPtr->VoltageMap = VDDIO_DETERMINED; - PutEventLog (AGESA_WARNING, MEM_WARNING_INITIAL_DDR3VOLT_NONZERO, 0, 0, 0, 0, &(NBPtr[BSP_DIE].MemPtr->StdHeader)); - SetMemError (AGESA_WARNING, NBPtr[BSP_DIE].MCTPtr); - IDS_HDT_CONSOLE (MEM_FLOW, "Warning: Initial Value for VDDIO has been changed.\n"); - RetVal = TRUE; - } else { - RetVal = MemMLvDdr3 (MemMainPtr); - - VDDIO = ParameterPtr->DDR3Voltage; - if (NBPtr->IsSupported[PerformanceOnly] || ((PowerPolicy == Performance) && (mmSharedPtr->VoltageMap != 0))) { - // When there is no commonly supported voltage, do not optimize performance - // For cases where we can maximize performance, do the following - // When VDDIO is enforced, DDR3Voltage will be overriden by specific VDDIO - // So cases with DDR3Voltage left to be VOLT_UNSUPPORTED will be open to maximizing performance. - ParameterPtr->DDR3Voltage = VOLT_UNSUPPORTED; - } - - IDS_OPTION_HOOK (IDS_ENFORCE_VDDIO, &(ParameterPtr->DDR3Voltage), &NBPtr->MemPtr->StdHeader); - - if (ParameterPtr->DDR3Voltage != VOLT_UNSUPPORTED) { - // When Voltage is already determined, do not have further process to choose maximum frequency to optimize performance - mmSharedPtr->VoltageMap = VDDIO_DETERMINED; - IDS_HDT_CONSOLE (MEM_FLOW, "VDDIO is determined. No further optimization will be done.\n"); - } else { - for (Node = 0; Node < MemMainPtr->DieCount; Node++) { - NBPtr[Node].MaxFreqVDDIO[VOLT1_5_ENCODED_VAL] = UNSUPPORTED_DDR_FREQUENCY; - NBPtr[Node].MaxFreqVDDIO[VOLT1_35_ENCODED_VAL] = UNSUPPORTED_DDR_FREQUENCY; - NBPtr[Node].MaxFreqVDDIO[VOLT1_25_ENCODED_VAL] = UNSUPPORTED_DDR_FREQUENCY; - } - // Reprogram the leveling result as temporal candidate - ParameterPtr->DDR3Voltage = VDDIO; - } - } - - ASSERT (ParameterPtr->DDR3Voltage != VOLT_UNSUPPORTED); - return RetVal; -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * Finalize the VDDIO for the board for performance enhancement. - * - * @param[in,out] *MemMainPtr - Pointer to the MEM_MAIN_DATA_BLOCK - * - * @return TRUE - No fatal error occurs. - * @return FALSE - Fatal error occurs. - */ -BOOLEAN -MemMLvDdr3PerformanceEnhFinalize ( - IN OUT MEM_MAIN_DATA_BLOCK *MemMainPtr - ) -{ - UINT8 Dct; - UINT8 Node; - UINT8 NodeCnt[VOLT1_25 + 1]; - UINT8 MaxCnt; - MEM_NB_BLOCK *NBPtr; - MEM_PARAMETER_STRUCT *ParameterPtr; - MEM_SHARED_DATA *mmSharedPtr; - UINT8 CurrentVoltage; - DIMM_VOLTAGE Voltage; - MEMORY_BUS_SPEED HighestFreq; - - ParameterPtr = MemMainPtr->MemPtr->ParameterListPtr; - mmSharedPtr = MemMainPtr->mmSharedPtr; - NBPtr = MemMainPtr->NBPtr; - - LibAmdMemFill (NodeCnt, 0, VOLT1_25_ENCODED_VAL + 1, &NBPtr->MemPtr->StdHeader); - if (mmSharedPtr->VoltageMap != VDDIO_DETERMINED) { - Voltage = ParameterPtr->DDR3Voltage; - IDS_HDT_CONSOLE (MEM_FLOW, "\nSearching for VDDIO that can maximize frequency: \n"); - for (Node = 0; Node < MemMainPtr->DieCount; Node++) { - HighestFreq = 0; - // Find out what the highest frequency that can be reached is on this node across different voltage. - for (CurrentVoltage = VOLT1_5_ENCODED_VAL; CurrentVoltage <= VOLT1_25_ENCODED_VAL; CurrentVoltage ++) { - if (HighestFreq < NBPtr[Node].MaxFreqVDDIO[CurrentVoltage]) { - HighestFreq = NBPtr[Node].MaxFreqVDDIO[CurrentVoltage]; - } - } - IDS_HDT_CONSOLE (MEM_FLOW, "Node%d: 1.5V -> %dMHz, 1.35V -> %dMHz, 1.25V -> %dMHz\n", Node, NBPtr[Node].MaxFreqVDDIO[VOLT1_5_ENCODED_VAL], NBPtr[Node].MaxFreqVDDIO[VOLT1_35_ENCODED_VAL], NBPtr[Node].MaxFreqVDDIO[VOLT1_25_ENCODED_VAL]); - // Figure out what voltage we can have when attaining the highest frequency. - for (CurrentVoltage = VOLT1_5_ENCODED_VAL; CurrentVoltage <= VOLT1_25_ENCODED_VAL; CurrentVoltage ++) { - if (NBPtr[Node].MaxFreqVDDIO[CurrentVoltage] == HighestFreq) { - NodeCnt[CurrentVoltage] ++; - } - } - } - IDS_HDT_CONSOLE (MEM_FLOW, "Number of nodes that can run at maximize performance: 1.5V -> %d Nodes 1.35V -> %d Nodes 1.25V -> %d Nodes.\n", NodeCnt[VOLT1_5_ENCODED_VAL], NodeCnt[VOLT1_35_ENCODED_VAL], NodeCnt[VOLT1_25_ENCODED_VAL]); - MaxCnt = 0; - // Use the VDDIO at which most nodes can run at higher frequency - for (CurrentVoltage = VOLT1_5_ENCODED_VAL; CurrentVoltage <= VOLT1_25_ENCODED_VAL; CurrentVoltage ++) { - if (MaxCnt <= NodeCnt[CurrentVoltage]) { - MaxCnt = NodeCnt[CurrentVoltage]; - ParameterPtr->DDR3Voltage = CONVERT_ENCODED_TO_VDDIO (CurrentVoltage); - } - } - - ASSERT (ParameterPtr->DDR3Voltage != VOLT_UNSUPPORTED); - - mmSharedPtr->VoltageMap = VDDIO_DETERMINED; - if (Voltage != ParameterPtr->DDR3Voltage) { - // Finalize frequency with updated finalized VDDIO - for (Node = 0; Node < MemMainPtr->DieCount; Node++) { - // Need to re-sync target speed and different VDDIO may cause different settings - NBPtr[Node].TechPtr->SpdGetTargetSpeed (NBPtr[Node].TechPtr); - for (Dct = 0; Dct < NBPtr[Node].DctCount; Dct++) { - NBPtr[Node].SwitchDCT (&(NBPtr[Node]), Dct); - if (NBPtr[Node].DCTPtr->Timings.CsEnabled != 0) { - if (!NBPtr[Node].PlatformSpec (&(NBPtr[Node]))) { - return FALSE; - } - } - } - } - } - } - return TRUE; -} diff --git a/src/vendorcode/amd/agesa/f12/Proc/Mem/Main/mmMemClr.c b/src/vendorcode/amd/agesa/f12/Proc/Mem/Main/mmMemClr.c deleted file mode 100644 index e62b449336..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/Mem/Main/mmMemClr.c +++ /dev/null @@ -1,112 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * mmMemclr.c - * - * Main Memory Feature implementation file for Memory Clear. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: (Mem/Main) - * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $ - * - **/ -/***************************************************************************** -* -* Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* *************************************************************************** -* -*/ - -/* - *---------------------------------------------------------------------------- - * MODULES USED - * - *---------------------------------------------------------------------------- - */ - - -#include "AGESA.h" -#include "OptionMemory.h" -#include "mm.h" -#include "mn.h" -#include "Ids.h" -#include "mfmemclr.h" -#include "Filecode.h" -CODE_GROUP (G2_PEI) -RDATA_GROUP (G2_PEI) - -#define FILECODE PROC_MEM_MAIN_MMMEMCLR_FILECODE -/*----------------------------------------------------------------------------- -* EXPORTED FUNCTIONS -* -*----------------------------------------------------------------------------- -*/ -BOOLEAN -MemMMctMemClr ( - IN OUT MEM_MAIN_DATA_BLOCK *MemMainPtr - ); - - -/* -----------------------------------------------------------------------------*/ -/** - * - * - * Initiates/synchronizes memory clear on all nodes with Dram on it. - * - * @param[in,out] *MemMainPtr - Pointer to the MEM_MAIN_DATA_BLOCK - * - * @return TRUE - No fatal error occurs. - * @return FALSE - Fatal error occurs. - */ -BOOLEAN -MemMMctMemClr ( - IN OUT MEM_MAIN_DATA_BLOCK *MemMainPtr - ) -{ - UINT8 Node; - UINT8 NodeCnt; - BOOLEAN RetVal; - MEM_NB_BLOCK *NBPtr; - - NBPtr = MemMainPtr->NBPtr; - NodeCnt = MemMainPtr->DieCount; - RetVal = TRUE; - - IDS_OPTION_HOOK (IDS_BEFORE_MEMCLR, NULL, &NBPtr->MemPtr->StdHeader); - - for (Node = 0; Node < NodeCnt; Node++) { - MemFMctMemClr_Init (&NBPtr[Node]); - } - - for (Node = 0; Node < NodeCnt; Node++) { - MemFMctMemClr_Sync (&NBPtr[Node]); - RetVal &= (BOOLEAN) (NBPtr[Node].MCTPtr->ErrCode < AGESA_FATAL); - } - - return RetVal; -} \ No newline at end of file diff --git a/src/vendorcode/amd/agesa/f12/Proc/Mem/Main/mmMemRestore.c b/src/vendorcode/amd/agesa/f12/Proc/Mem/Main/mmMemRestore.c deleted file mode 100644 index 5aff259c51..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/Mem/Main/mmMemRestore.c +++ /dev/null @@ -1,605 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * mmMemRestore.c - * - * Main Memory Feature implementation file for Node Interleaving - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: (Mem/Main) - * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $ - * - **/ -/***************************************************************************** -* -* Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* *************************************************************************** -* -*/ - -/* - *---------------------------------------------------------------------------- - * MODULES USED - * - *---------------------------------------------------------------------------- - */ - -#include "AGESA.h" -#include "amdlib.h" -#include "OptionMemory.h" -#include "mm.h" -#include "mn.h" -#include "Ids.h" -#include "S3.h" -#include "mfs3.h" -#include "heapManager.h" -#include "Filecode.h" -CODE_GROUP (G1_PEICC) -RDATA_GROUP (G1_PEICC) - -#define FILECODE PROC_MEM_MAIN_MMMEMRESTORE_FILECODE - -#define ST_PRE_ESR 0 -#define ST_POST_ESR 1 -#define ST_DONE 2 - -/*---------------------------------------------------------------------------- - * PROTOTYPES OF LOCAL FUNCTIONS - * - *---------------------------------------------------------------------------- - */ -BOOLEAN -STATIC -MemMRestoreDqsTimings ( - IN VOID *Storage, - IN MEM_MAIN_DATA_BLOCK *MemMainPtr - ); - -BOOLEAN -STATIC -MemMSetCSRNb ( - IN OUT MEM_NB_BLOCK *NBPtr, - IN PCI_SPECIAL_CASE *SpecialCases, - IN PCI_ADDR PciAddr, - IN UINT32 Value - ); - -VOID -STATIC -MemMCreateS3NbBlock ( - IN OUT MEM_MAIN_DATA_BLOCK *MemMainPtr, - OUT S3_MEM_NB_BLOCK **S3NBPtr - ); -/*----------------------------------------------------------------------------- -* EXPORTED FUNCTIONS -* -*----------------------------------------------------------------------------- -*/ -VOID -MemMContextSave ( - IN OUT MEM_MAIN_DATA_BLOCK *MemMainPtr - ); - -BOOLEAN -MemMContextRestore ( - IN OUT MEM_MAIN_DATA_BLOCK *MemMainPtr - ); - -extern MEM_NB_SUPPORT memNBInstalled[]; - -/* -----------------------------------------------------------------------------*/ -/** - * - * Check and save memory context if possible. - * - * @param[in,out] *MemMainPtr - Pointer to the MEM_MAIN_DATA_BLOCK - * - */ -VOID -MemMContextSave ( - IN OUT MEM_MAIN_DATA_BLOCK *MemMainPtr - ) -{ - UINT8 Node; - UINT8 i; - MEM_PARAMETER_STRUCT *RefPtr; - LOCATE_HEAP_PTR LocHeap; - ALLOCATE_HEAP_PARAMS AllocHeapParams; - DEVICE_BLOCK_HEADER *DeviceList; - AMD_CONFIG_PARAMS *StdHeader; - UINT32 BufferSize; - VOID *BufferOffset; - MEM_NB_BLOCK *NBArray; - S3_MEM_NB_BLOCK *S3NBPtr; - DESCRIPTOR_GROUP DeviceDescript[MAX_NODES_SUPPORTED]; - - NBArray = MemMainPtr->NBPtr; - RefPtr = NBArray[BSP_DIE].RefPtr; - - if (RefPtr->SaveMemContextCtl) { - RefPtr->MemContext.NvStorage = NULL; - RefPtr->MemContext.NvStorageSize = 0; - - // Make sure DQS training has occurred before saving memory context - if (!RefPtr->MemRestoreCtl) { - StdHeader = &MemMainPtr->MemPtr->StdHeader; - - MemMCreateS3NbBlock (MemMainPtr, &S3NBPtr); - if (S3NBPtr != NULL) { - // Get the mask bit and the register list for node that presents - BufferSize = 0; - for (Node = 0; Node < MemMainPtr->DieCount; Node ++) { - S3NBPtr->MemS3GetConPCIMask (&NBArray[Node], (VOID *)&DeviceDescript[Node]); - S3NBPtr->MemS3GetConMSRMask (&NBArray[Node], (VOID *)&DeviceDescript[Node]); - BufferSize += S3NBPtr->MemS3GetRegLstPtr (&NBArray[Node], (VOID *)&DeviceDescript[Node]); - } - - // Base on the size of the device list, apply for a buffer for it. - AllocHeapParams.RequestedBufferSize = (UINT32) (BufferSize + sizeof (DEVICE_BLOCK_HEADER)); - AllocHeapParams.BufferHandle = AMD_MEM_S3_DATA_HANDLE; - AllocHeapParams.Persist = HEAP_LOCAL_CACHE; - if (HeapAllocateBuffer (&AllocHeapParams, StdHeader) == AGESA_SUCCESS) { - DeviceList = (DEVICE_BLOCK_HEADER *) AllocHeapParams.BufferPtr; - DeviceList->RelativeOrMaskOffset = (UINT16) AllocHeapParams.RequestedBufferSize; - - // Copy device list on the stack to the heap. - BufferOffset = sizeof (DEVICE_BLOCK_HEADER) + AllocHeapParams.BufferPtr; - for (Node = 0; Node < MemMainPtr->DieCount; Node ++) { - for (i = PRESELFREF; i <= POSTSELFREF; i ++) { - // Copy PCI device descriptor to the heap if it exists. - if (DeviceDescript[Node].PCIDevice[i].RegisterListID != 0xFFFFFFFF) { - LibAmdMemCopy ((VOID *) BufferOffset, &(DeviceDescript[Node].PCIDevice[i]), sizeof (PCI_DEVICE_DESCRIPTOR), StdHeader); - DeviceList->NumDevices ++; - BufferOffset += sizeof (PCI_DEVICE_DESCRIPTOR); - } - // Copy conditional PCI device descriptor to the heap if it exists. - if (DeviceDescript[Node].CPCIDevice[i].RegisterListID != 0xFFFFFFFF) { - LibAmdMemCopy ((VOID *) BufferOffset, &(DeviceDescript[Node].CPCIDevice[i]), sizeof (CONDITIONAL_PCI_DEVICE_DESCRIPTOR), StdHeader); - DeviceList->NumDevices ++; - BufferOffset += sizeof (CONDITIONAL_PCI_DEVICE_DESCRIPTOR); - } - // Copy MSR device descriptor to the heap if it exists. - if (DeviceDescript[Node].MSRDevice[i].RegisterListID != 0xFFFFFFFF) { - LibAmdMemCopy ((VOID *) BufferOffset, &(DeviceDescript[Node].MSRDevice[i]), sizeof (MSR_DEVICE_DESCRIPTOR), StdHeader); - DeviceList->NumDevices ++; - BufferOffset += sizeof (MSR_DEVICE_DESCRIPTOR); - } - // Copy conditional MSR device descriptor to the heap if it exists. - if (DeviceDescript[Node].CMSRDevice[i].RegisterListID != 0xFFFFFFFF) { - LibAmdMemCopy ((VOID *) BufferOffset, &(DeviceDescript[Node].PCIDevice[i]), sizeof (CONDITIONAL_MSR_DEVICE_DESCRIPTOR), StdHeader); - DeviceList->NumDevices ++; - BufferOffset += sizeof (CONDITIONAL_MSR_DEVICE_DESCRIPTOR); - } - } - } - - // Determine size needed - BufferSize = GetWorstCaseContextSize (DeviceList, INIT_RESUME, StdHeader); - AllocHeapParams.RequestedBufferSize = BufferSize; - AllocHeapParams.BufferHandle = AMD_S3_SAVE_HANDLE; - AllocHeapParams.Persist = HEAP_LOCAL_CACHE; - if (HeapAllocateBuffer (&AllocHeapParams, StdHeader) == AGESA_SUCCESS) { - // Save memory context - SaveDeviceListContext (DeviceList, AllocHeapParams.BufferPtr, INIT_RESUME, &BufferSize, StdHeader); - RefPtr->MemContext.NvStorageSize = BufferSize; - } - - HeapDeallocateBuffer (AMD_MEM_S3_DATA_HANDLE, StdHeader); - } - } - HeapDeallocateBuffer (AMD_MEM_S3_NB_HANDLE, StdHeader); - - // Locate MemContext since it might have been shifted after deallocating - LocHeap.BufferHandle = AMD_S3_SAVE_HANDLE; - if (HeapLocateBuffer (&LocHeap, StdHeader) == AGESA_SUCCESS) { - RefPtr->MemContext.NvStorage = LocHeap.BufferPtr; - } - } - } - - for (Node = 0; Node < MemMainPtr->DieCount; Node++) { - NBArray[Node].FamilySpecificHook[AfterSaveRestore] (&NBArray[Node], &NBArray[Node]); - } -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * Check and restore memory context if possible. - * - * @param[in,out] *MemMainPtr - Pointer to the MEM_MAIN_DATA_BLOCK - * - * @return TRUE - DQS timing restore succeeds. - * @return FALSE - DQS timing restore fails. - */ -BOOLEAN -MemMContextRestore ( - IN OUT MEM_MAIN_DATA_BLOCK *MemMainPtr - ) -{ - UINT8 Node; - MEM_NB_BLOCK *NBArray; - MEM_PARAMETER_STRUCT *RefPtr; - S3_MEM_NB_BLOCK *S3NBPtr; - - NBArray = MemMainPtr->NBPtr; - RefPtr = NBArray[BSP_DIE].RefPtr; - - IDS_HDT_CONSOLE (MEM_STATUS, "\nStart Mem Restore\n"); - if (RefPtr->MemRestoreCtl) { - if (RefPtr->MemContext.NvStorage != NULL) { - MemMCreateS3NbBlock (MemMainPtr, &S3NBPtr); - if (S3NBPtr != NULL) { - // Check DIMM config and restore DQS timings if possible - if (!MemMRestoreDqsTimings (RefPtr->MemContext.NvStorage, MemMainPtr)) { - RefPtr->MemRestoreCtl = FALSE; - } - } else { - RefPtr->MemRestoreCtl = FALSE; - } - HeapDeallocateBuffer (AMD_MEM_S3_NB_HANDLE, &(MemMainPtr->MemPtr->StdHeader)); - } else { - RefPtr->MemRestoreCtl = FALSE; - } - } - - for (Node = 0; Node < MemMainPtr->DieCount; Node++) { - NBArray[Node].FamilySpecificHook[AfterSaveRestore] (&NBArray[Node], &NBArray[Node]); - } - IDS_HDT_CONSOLE (MEM_FLOW, RefPtr->MemRestoreCtl ? "Mem Restore Succeeds!\n" : "Mem Restore Fails!\n"); - return RefPtr->MemRestoreCtl; -} - -/*---------------------------------------------------------------------------- - * LOCAL FUNCTIONS - * - *---------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------*/ -/** - * Restores all devices that contains DQS timings - * - * @param[in] Storage Beginning of the device list. - * @param[in,out] MemMainPtr - Pointer to the MEM_MAIN_DATA_BLOCK - * - * @return TRUE - No fatal error occurs. - * @return FALSE - Fatal error occurs. - * - */ -BOOLEAN -STATIC -MemMRestoreDqsTimings ( - IN VOID *Storage, - IN MEM_MAIN_DATA_BLOCK *MemMainPtr - ) -{ - AMD_CONFIG_PARAMS *StdHeader; - UINT8 *OrMask; - DEVICE_DESCRIPTORS Device; - INT16 i; - INT16 j; - DEVICE_BLOCK_HEADER *DeviceList; - PCI_REGISTER_BLOCK_HEADER *Reg; - CPCI_REGISTER_BLOCK_HEADER *CReg; - MSR_REGISTER_BLOCK_HEADER *MsrReg; - CMSR_REGISTER_BLOCK_HEADER *CMsrReg; - PCI_ADDR PciAddress; - MEM_NB_BLOCK *NBArray; - UINT8 State; - UINT8 Node; - UINT8 Dct; - UINT8 MaxNode; - - NBArray = MemMainPtr->NBPtr; - StdHeader = &(MemMainPtr->MemPtr->StdHeader); - DeviceList = (DEVICE_BLOCK_HEADER *) Storage; - Device.CommonDeviceHeader = (DEVICE_DESCRIPTOR *) &DeviceList[1]; - OrMask = (UINT8 *) DeviceList + DeviceList->RelativeOrMaskOffset; - - if (DeviceList->NumDevices == 0) { - return FALSE; - } - - MaxNode = 0; - State = ST_PRE_ESR; - for (i = 0; State != ST_DONE; i++) { - if (((State == ST_PRE_ESR) && (Device.CommonDeviceHeader->Type == DEV_TYPE_PCI_PRE_ESR)) || - ((State == ST_POST_ESR) && (Device.CommonDeviceHeader->Type == DEV_TYPE_PCI))) { - MemFS3GetPciDeviceRegisterList (Device.PciDevice, &Reg, StdHeader); - Node = Device.PciDevice->Node; - IDS_HDT_CONSOLE (MEM_STATUS, "Node %d\n", Node); - PciAddress = NBArray[Node].PciAddr; - for (j = 0; j < Reg->NumRegisters; j++) { - PciAddress.Address.Function = Reg->RegisterList[j].Function; - PciAddress.Address.Register = Reg->RegisterList[j].Offset; - PciAddress.Address.Segment = (Reg->RegisterList[j].Type.SpecialCaseFlag != 0) ? - 0xF - Reg->RegisterList[j].Type.SpecialCaseIndex : 0; - if (!MemMSetCSRNb (&NBArray[Node], Reg->SpecialCases, PciAddress, *((UINT32 *) OrMask) & Reg->RegisterList[j].AndMask)) { - return FALSE; // Restore fails - } - OrMask += (Reg->RegisterList[j].Type.RegisterSize == 0) ? 4 : Reg->RegisterList[j].Type.RegisterSize; - } - - if (MaxNode < Node) { - MaxNode = Node; - } - - } else if (((State == ST_PRE_ESR) && (Device.CommonDeviceHeader->Type == DEV_TYPE_CPCI_PRE_ESR)) || - ((State == ST_POST_ESR) && (Device.CommonDeviceHeader->Type == DEV_TYPE_CPCI))) { - MemFS3GetCPciDeviceRegisterList (Device.CPciDevice, &CReg, StdHeader); - Node = Device.CPciDevice->Node; - IDS_HDT_CONSOLE (MEM_STATUS, "Node %d\n", Node); - PciAddress = NBArray[Node].PciAddr; - for (j = 0; j < CReg->NumRegisters; j++) { - if (((Device.CPciDevice->Mask1 & CReg->RegisterList[j].Mask1) != 0) && - ((Device.CPciDevice->Mask2 & CReg->RegisterList[j].Mask2) != 0)) { - PciAddress.Address.Function = CReg->RegisterList[j].Function; - PciAddress.Address.Register = CReg->RegisterList[j].Offset; - PciAddress.Address.Segment = (CReg->RegisterList[j].Type.SpecialCaseFlag != 0) ? - 0xF - CReg->RegisterList[j].Type.SpecialCaseIndex : 0; - if (!MemMSetCSRNb (&NBArray[Node], CReg->SpecialCases, PciAddress, *((UINT32 *) OrMask) & CReg->RegisterList[j].AndMask)) { - return FALSE; // Restore fails - } - OrMask += (CReg->RegisterList[j].Type.RegisterSize == 0) ? 4 : CReg->RegisterList[j].Type.RegisterSize; - } - } - } else if (((State == ST_PRE_ESR) && (Device.CommonDeviceHeader->Type == DEV_TYPE_MSR_PRE_ESR)) || - ((State == ST_POST_ESR) && (Device.CommonDeviceHeader->Type == DEV_TYPE_MSR))) { - MemFS3GetMsrDeviceRegisterList (Device.MsrDevice, &MsrReg, StdHeader); - for (j = 0; j < MsrReg->NumRegisters; j++) { - OrMask += 8; - } - } else if (((State == ST_PRE_ESR) && (Device.CommonDeviceHeader->Type == DEV_TYPE_CMSR_PRE_ESR)) || - ((State == ST_POST_ESR) && (Device.CommonDeviceHeader->Type == DEV_TYPE_CMSR))) { - MemFS3GetCMsrDeviceRegisterList (Device.CMsrDevice, &CMsrReg, StdHeader); - for (j = 0; j < CMsrReg->NumRegisters; j++) { - if (((Device.CMsrDevice->Mask1 & CMsrReg->RegisterList[j].Mask1) != 0) && - ((Device.CMsrDevice->Mask2 & CMsrReg->RegisterList[j].Mask2) != 0)) { - OrMask += 8; - } - } - } - - switch (Device.CommonDeviceHeader->Type) { - case DEV_TYPE_PCI_PRE_ESR: - // Fall through to advance the pointer after restoring context - case DEV_TYPE_PCI: - Device.PciDevice++; - break; - case DEV_TYPE_CPCI_PRE_ESR: - // Fall through to advance the pointer after restoring context - case DEV_TYPE_CPCI: - Device.CPciDevice++; - break; - case DEV_TYPE_MSR_PRE_ESR: - // Fall through to advance the pointer after restoring context - case DEV_TYPE_MSR: - Device.MsrDevice++; - break; - case DEV_TYPE_CMSR_PRE_ESR: - // Fall through to advance the pointer after restoring context - case DEV_TYPE_CMSR: - Device.CMsrDevice++; - break; - default: - ASSERT (FALSE); - break; - } - - if (i == (DeviceList->NumDevices - 1)) { - // Go to next state - State++; - i = -1; - Device.CommonDeviceHeader = (DEVICE_DESCRIPTOR *) &DeviceList[1]; - - // Check to see if processor or DIMM population has changed - if ((MaxNode + 1) != MemMainPtr->DieCount) { - IDS_HDT_CONSOLE (MEM_FLOW, "\tSTOP: Population changed\n"); - return FALSE; - } - - // Perform MemClk frequency change - for (Node = 0; Node < MemMainPtr->DieCount; Node ++) { - if (NBArray[Node].MCTPtr->NodeMemSize != 0) { - NBArray[Node].BeforeDqsTraining (&NBArray[Node]); - if (NBArray[Node].DCTPtr->Timings.Speed < NBArray[Node].DCTPtr->Timings.TargetSpeed) { - for (Dct = 0; Dct < NBArray[Node].DctCount; Dct++) { - NBArray[Node].SwitchDCT (&NBArray[Node], Dct); - NBArray[Node].DCTPtr->Timings.Speed = NBArray[Node].DCTPtr->Timings.TargetSpeed; - } - IDS_OPTION_HOOK (IDS_BEFORE_MEM_FREQ_CHG, &NBArray[Node], &(MemMainPtr->MemPtr->StdHeader)); - NBArray[Node].ChangeFrequency (&NBArray[Node]); - } - } - } - } - } - - return TRUE; -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * This function filters out other settings and only restores DQS timings. - * - * @param[in,out] NBPtr - Pointer to the MEM_NB_BLOCK - * @param[in] SpecialCases - Pointer to special cases array handlers - * @param[in] PciAddr - address of the CSR register in PCI_ADDR format. - * @param[in] Value - Value to be programmed - * - * @return TRUE - No fatal error occurs. - * @return FALSE - Fatal error occurs. - * - */ - -BOOLEAN -STATIC -MemMSetCSRNb ( - IN OUT MEM_NB_BLOCK *NBPtr, - IN PCI_SPECIAL_CASE *SpecialCases, - IN PCI_ADDR PciAddr, - IN UINT32 Value - ) -{ - UINT32 Offset; - UINT8 Dct; - UINT32 Temp; - BOOLEAN RetVal; - UINT32 BOffset; - - RetVal = TRUE; - if (PciAddr.Address.Segment != 0) { - if (PciAddr.Address.Segment == 0xF) { - PciAddr.Address.Segment = 0; - Dct = (UINT8) ((PciAddr.Address.Register >> 10) & 1); - Offset = PciAddr.Address.Register & 0x3FF; - BOffset = PciAddr.Address.Register & 0xFF; - if ((PciAddr.Address.Register & 0x800) == 0) { - if (((BOffset >= 1) && (BOffset <= 3)) || - ((BOffset >= 5) && (BOffset <= 7)) || - ((Offset >= 0x10) && (Offset <= 0x2B)) || - ((Offset >= 0x30) && (Offset <= 0x4A))) { - IDS_HDT_CONSOLE (MEM_FLOW, "\t\tF2_%d9C_%03x = %08x\n", Dct, Offset, Value); - //MemNS3SetCSR - SpecialCases[0].Restore (AccessS3SaveWidth32, PciAddr, &Value, &NBPtr->MemPtr->StdHeader); - } - } - } - } else { - Dct = (UINT8) ((PciAddr.Address.Register >> 8) & 1); - Offset = PciAddr.Address.Register & 0xFF; - - if (PciAddr.Address.Function == 2) { - if ((Offset >= 0x40) && (Offset < 0x60) && ((Value & 4) != 0)) { - // If TestFail bit is set, set CsTestFail - NBPtr->SwitchDCT (NBPtr, Dct); - NBPtr->DCTPtr->Timings.CsTrainFail |= (UINT16)1 << ((Offset - 0x40) >> 2); - IDS_HDT_CONSOLE (MEM_FLOW, "\tBad CS:%d\n", ((Offset - 0x40) >> 2)); - } else if (Offset == 0x80) { - LibAmdPciRead (AccessWidth32, PciAddr, &Temp, &NBPtr->MemPtr->StdHeader); - if (Temp != Value) { - IDS_HDT_CONSOLE (MEM_FLOW, "\tSTOP: DIMM config changed\n"); - RetVal = FALSE; - } - } else if (Offset == 0x90) { - LibAmdPciRead (AccessWidth32, PciAddr, &Temp, &NBPtr->MemPtr->StdHeader); - if ((Temp & 0x0001F000) != (Value & 0x0001F000)) { - IDS_HDT_CONSOLE (MEM_FLOW, "\tSTOP: DIMM config changed\n"); - RetVal = FALSE; - } - } else if (Offset == 0x94) { - LibAmdPciRead (AccessWidth32, PciAddr, &Temp, &NBPtr->MemPtr->StdHeader); - if ((Temp & 0x00061000) != (Value & 0x00061000)) { - IDS_HDT_CONSOLE (MEM_FLOW, "\tSTOP: DIMM config changed\n"); - RetVal = FALSE; - } - if (((Value & 0x4000) == 0) && (NBPtr->GetMemClkFreqId (NBPtr, NBPtr->DCTPtr->Timings.TargetSpeed) != ((Value & 7) + 1))) { - IDS_HDT_CONSOLE (MEM_FLOW, "\tSTOP: MemClk has changed\n"); - RetVal = FALSE; - } - // Restore ZqcsInterval - Temp &= 0xFFFFF3FF; - Temp |= (Value & 0x00000C00); - LibAmdPciWrite (AccessWidth32, PciAddr, &Temp, &NBPtr->MemPtr->StdHeader); - } else if (Offset == 0x78) { - // Program MaxRdLat - LibAmdPciRead (AccessWidth32, PciAddr, &Temp, &NBPtr->MemPtr->StdHeader); - Temp &= 0x0009BF0F; - Temp |= (Value & 0xFFC00000); - LibAmdPciWrite (AccessWidth32, PciAddr, &Temp, &NBPtr->MemPtr->StdHeader); - } else if (PciAddr.Address.Register == 0x110) { - if ((NBPtr->MCTPtr->NodeMemSize != 0) && (Value == 0x00000100)) { - IDS_HDT_CONSOLE (MEM_FLOW, "\tSTOP: DIMM config changed\n"); - RetVal = FALSE; - } - } - } - } - - if (RetVal == FALSE) { - NBPtr->SwitchDCT (NBPtr, 0); - NBPtr->DCTPtr->Timings.CsTrainFail = 0; - NBPtr->SwitchDCT (NBPtr, 1); - NBPtr->DCTPtr->Timings.CsTrainFail = 0; - } - - return RetVal; -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * Create S3 NB Block. - * - * @param[in,out] MemMainPtr - Pointer to the MEM_MAIN_DATA_BLOCK - * @param[out] S3NBPtr - Pointer to the S3 NB Block pointer - * - */ -VOID -STATIC -MemMCreateS3NbBlock ( - IN OUT MEM_MAIN_DATA_BLOCK *MemMainPtr, - OUT S3_MEM_NB_BLOCK **S3NBPtr - ) -{ - UINT8 Node; - UINT8 i; - MEM_NB_BLOCK *NBArray; - MEM_NB_BLOCK *DummyNBs; - ALLOCATE_HEAP_PARAMS AllocHeapParams; - - NBArray = MemMainPtr->NBPtr; - - *S3NBPtr = NULL; - - // Allocate heap for S3 NB Blocks - AllocHeapParams.RequestedBufferSize = (MemMainPtr->DieCount * (sizeof (S3_MEM_NB_BLOCK) + sizeof (MEM_NB_BLOCK))); - AllocHeapParams.BufferHandle = AMD_MEM_S3_NB_HANDLE; - AllocHeapParams.Persist = HEAP_LOCAL_CACHE; - if (HeapAllocateBuffer (&AllocHeapParams, &(MemMainPtr->MemPtr->StdHeader)) == AGESA_SUCCESS) { - *S3NBPtr = (S3_MEM_NB_BLOCK *) AllocHeapParams.BufferPtr; - DummyNBs = (MEM_NB_BLOCK *) (AllocHeapParams.BufferPtr + MemMainPtr->DieCount * sizeof (S3_MEM_NB_BLOCK)); - - // Initialize S3 NB Blocks - for (Node = 0; Node < MemMainPtr->DieCount; Node ++) { - (*S3NBPtr)[Node].NBPtr = &DummyNBs[Node]; - - for (i = 0; memNBInstalled[i].MemS3ResumeConstructNBBlock != 0; i++) { - if (memNBInstalled[i].MemS3ResumeConstructNBBlock (&(*S3NBPtr)[Node], NBArray[BSP_DIE].MemPtr, Node)) { - break; - } - }; - if (memNBInstalled[i].MemS3ResumeConstructNBBlock == 0) { - *S3NBPtr = NULL; - break; - } - } - } -} \ No newline at end of file diff --git a/src/vendorcode/amd/agesa/f12/Proc/Mem/Main/mmNodeInterleave.c b/src/vendorcode/amd/agesa/f12/Proc/Mem/Main/mmNodeInterleave.c deleted file mode 100644 index 9bfec387e3..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/Mem/Main/mmNodeInterleave.c +++ /dev/null @@ -1,140 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * mmNodeInterleave.c - * - * Main Memory Feature implementation file for Node Interleaving - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: (Mem/Main) - * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $ - * - **/ -/***************************************************************************** -* -* Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* *************************************************************************** -* -*/ - -/* - *---------------------------------------------------------------------------- - * MODULES USED - * - *---------------------------------------------------------------------------- - */ - - -#include "AGESA.h" -#include "OptionMemory.h" -#include "mm.h" -#include "mn.h" -#include "Ids.h" -#include "GeneralServices.h" -#include "Filecode.h" -CODE_GROUP (G2_PEI) -RDATA_GROUP (G2_PEI) - -#define FILECODE PROC_MEM_MAIN_MMNODEINTERLEAVE_FILECODE - -extern MEM_FEAT_BLOCK_MAIN MemFeatMain; -/*----------------------------------------------------------------------------- -* EXPORTED FUNCTIONS -* -*----------------------------------------------------------------------------- -*/ -BOOLEAN -MemMInterleaveNodes ( - IN OUT MEM_MAIN_DATA_BLOCK *MemMainPtr - ); - -/* -----------------------------------------------------------------------------*/ -/** - * - * Check and enable node interleaving on all nodes. - * - * @param[in,out] *MemMainPtr - Pointer to the MEM_MAIN_DATA_BLOCK - * - * @return TRUE - No fatal error occurs. - * @return FALSE - Fatal error occurs. - */ -BOOLEAN -MemMInterleaveNodes ( - IN OUT MEM_MAIN_DATA_BLOCK *MemMainPtr - ) -{ - UINT8 Node; - UINT8 NodeCnt; - BOOLEAN RetVal; - MEM_NB_BLOCK *NBPtr; - - NBPtr = MemMainPtr->NBPtr; - NodeCnt = 0; - RetVal = TRUE; - - if (NBPtr->RefPtr->EnableNodeIntlv) { - if (!MemFeatMain.MemClr (MemMainPtr)) { - PutEventLog (AGESA_WARNING, MEM_WARNING_NODE_INTERLEAVING_NOT_ENABLED, 0, 0, 0, 0, &NBPtr->MemPtr->StdHeader); - SetMemError (AGESA_WARNING, NBPtr->MCTPtr); - return FALSE; - } - - MemMainPtr->mmSharedPtr->NodeIntlv.IsValid = FALSE; - MemMainPtr->mmSharedPtr->NodeIntlv.NodeIntlvSel = 0; - - for (Node = 0; Node < MemMainPtr->DieCount; Node++) { - if (!NBPtr[Node].FeatPtr->CheckInterleaveNodes (&NBPtr[Node])) { - break; - } - if (NBPtr[Node].MCTPtr->NodeMemSize != 0) { - NodeCnt ++; - } - } - - if ((Node == MemMainPtr->DieCount) && (NodeCnt != 0) && ((NodeCnt & (NodeCnt - 1)) == 0)) { - MemMainPtr->mmSharedPtr->NodeIntlv.NodeCnt = NodeCnt; - for (Node = 0; Node < MemMainPtr->DieCount; Node++) { - if (NBPtr[Node].MCTPtr->NodeMemSize != 0) { - NBPtr[Node].FeatPtr->InterleaveNodes (&NBPtr[Node]); - } - } - for (Node = 0; Node < MemMainPtr->DieCount; Node++) { - NBPtr[Node].SyncAddrMapToAllNodes (&NBPtr[Node]); - RetVal &= (BOOLEAN) (NBPtr[Node].MCTPtr->ErrCode < AGESA_FATAL); - } - } else { - // - // If all nodes cannot be interleaved - // - PutEventLog (AGESA_WARNING, MEM_WARNING_NODE_INTERLEAVING_NOT_ENABLED, 0, 0, 0, 0, &NBPtr->MemPtr->StdHeader); - SetMemError (AGESA_WARNING, NBPtr->MCTPtr); - } - } - - return RetVal; -} diff --git a/src/vendorcode/amd/agesa/f12/Proc/Mem/Main/mmOnlineSpare.c b/src/vendorcode/amd/agesa/f12/Proc/Mem/Main/mmOnlineSpare.c deleted file mode 100644 index a610f0799f..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/Mem/Main/mmOnlineSpare.c +++ /dev/null @@ -1,160 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * mmOnlineSpare.c - * - * Main Memory Feature implementation file for Node Interleaving - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: (Mem/Main) - * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $ - * - **/ -/***************************************************************************** -* -* Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* *************************************************************************** -* -*/ - -/* - *---------------------------------------------------------------------------- - * MODULES USED - * - *---------------------------------------------------------------------------- - */ - - -#include "AGESA.h" -#include "OptionMemory.h" -#include "mm.h" -#include "mn.h" -#include "Ids.h" -#include "Filecode.h" -CODE_GROUP (G2_PEI) -RDATA_GROUP (G2_PEI) - -#define FILECODE PROC_MEM_MAIN_MMONLINESPARE_FILECODE - -/*----------------------------------------------------------------------------- -* EXPORTED FUNCTIONS -* -*----------------------------------------------------------------------------- -*/ -BOOLEAN -MemMOnlineSpare ( - IN OUT MEM_MAIN_DATA_BLOCK *MemMainPtr - ); - -/* -----------------------------------------------------------------------------*/ -/** - * - * Check and enable online spare on all nodes. - * - * @param[in,out] *MemMainPtr - Pointer to the MEM_MAIN_DATA_BLOCK - * - * @return TRUE - No fatal error occurs. - * @return FALSE - Fatal error occurs. - */ -BOOLEAN -MemMOnlineSpare ( - IN OUT MEM_MAIN_DATA_BLOCK *MemMainPtr - ) -{ - UINT8 Node; - BOOLEAN IsEnabled; - UINT8 FirstEnabledNode; - UINT32 BottomIO; - BOOLEAN RetVal; - MEM_NB_BLOCK *NBPtr; - MEM_PARAMETER_STRUCT *RefPtr; - - AGESA_TESTPOINT (TpProcMemOnlineSpareInit, &(MemMainPtr->MemPtr->StdHeader)); - FirstEnabledNode = 0; - IsEnabled = FALSE; - RetVal = TRUE; - NBPtr = MemMainPtr->NBPtr; - RefPtr = NBPtr[BSP_DIE].RefPtr; - - for (Node = 0; Node < MemMainPtr->DieCount; Node++) { - if (NBPtr[Node].FeatPtr->OnlineSpare (&NBPtr[Node])) { - if (!IsEnabled) { - // Record the first node that has spared dimm enabled - FirstEnabledNode = Node; - IsEnabled = TRUE; - } - } - } - - if (IsEnabled) { - NBPtr[BSP_DIE].SharedPtr->CurrentNodeSysBase = 0; - BottomIO = (NBPtr[BSP_DIE].RefPtr->BottomIo & 0xF8) << 8; - // If the first node that has spared dimms does not have a system base smaller - // than bottomIO, then we don't need to reset the GStatus, as we don't need to - // remap memory hole. - if (NBPtr[FirstEnabledNode].MCTPtr->NodeSysBase < BottomIO) { - RefPtr->GStatus[GsbHWHole] = FALSE; - RefPtr->GStatus[GsbSpIntRemapHole] = FALSE; - RefPtr->GStatus[GsbSoftHole] = FALSE; - RefPtr->HoleBase = 0; - } - - for (Node = 0; Node < MemMainPtr->DieCount; Node++) { - if (Node >= FirstEnabledNode) { - // Remap memory on nodes with node number larger than the first node that has spared dimms. - NBPtr[Node].MCTPtr->Status[SbHWHole] = FALSE; - NBPtr[Node].MCTPtr->Status[SbSWNodeHole] = FALSE; - NBPtr[Node].SetBitField (&NBPtr[Node], BFDctSelBaseAddr, 0); - NBPtr[Node].SetBitField (&NBPtr[Node], BFDctSelHiRngEn, 0); - NBPtr[Node].SetBitField (&NBPtr[Node], BFDctSelHi, 0); - NBPtr[Node].SetBitField (&NBPtr[Node], BFDctSelBaseOffset, 0); - NBPtr[Node].SetBitField (&NBPtr[Node], BFDramHoleAddrReg, 0); - NBPtr[Node].HtMemMapInit (&NBPtr[Node]); - } else { - // No change is needed in the memory map of this node. - // Need to adjust the current system base for other nodes processed later. - NBPtr[Node].SharedPtr->CurrentNodeSysBase = (NBPtr[Node].MCTPtr->NodeSysLimit + 1) & 0xFFFFFFF0; - // If the current node does not have the memory hole, then set DramHoleAddrReg to be 0. - // If memory hoisting is enabled later by other node, SyncAddrMapToAllNodes will set the base - // and DramMemHoistValid. - // Otherwise, do not change the register value, as we need to keep DramHoleOffset unchanged, as well - // DramHoleValid. - if (!NBPtr[Node].MCTPtr->Status[SbHWHole]) { - NBPtr[Node].SetBitField (&NBPtr[Node], BFDramHoleAddrReg, 0); - } - } - } - - for (Node = 0; Node < MemMainPtr->DieCount; Node++) { - NBPtr[Node].SyncAddrMapToAllNodes (&NBPtr[Node]); - RetVal &= (BOOLEAN) (NBPtr[Node].MCTPtr->ErrCode < AGESA_FATAL); - } - NBPtr[BSP_DIE].CpuMemTyping (&NBPtr[BSP_DIE]); - } - return RetVal; -} diff --git a/src/vendorcode/amd/agesa/f12/Proc/Mem/Main/mmParallelTraining.c b/src/vendorcode/amd/agesa/f12/Proc/Mem/Main/mmParallelTraining.c deleted file mode 100644 index e66d825e52..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/Mem/Main/mmParallelTraining.c +++ /dev/null @@ -1,278 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * mmNodeInterleave.c - * - * Main Memory Feature implementation file for Node Interleaving - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: (Mem/Main) - * @e \$Revision: 44393 $ @e \$Date: 2010-12-24 07:38:46 +0800 (Fri, 24 Dec 2010) $ - * - **/ -/***************************************************************************** -* -* Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* *************************************************************************** -* -*/ - -/* - *---------------------------------------------------------------------------- - * MODULES USED - * - *---------------------------------------------------------------------------- - */ - - -#include "Porting.h" -#include "AGESA.h" -#include "amdlib.h" -#include "Ids.h" -#include "cpuRegisters.h" -#include "cpuServices.h" -#include "cpuApicUtilities.h" -#include "GeneralServices.h" -#include "OptionMemory.h" -#include "mm.h" -#include "mn.h" -#include "mt.h" -#include "ma.h" -#include "mu.h" -#include "mfParallelTraining.h" -#include "GeneralServices.h" -#include "heapManager.h" -#include "merrhdl.h" -#include "Filecode.h" -CODE_GROUP (G2_PEI) -RDATA_GROUP (G2_PEI) - -#define FILECODE PROC_MEM_MAIN_MMPARALLELTRAINING_FILECODE - -extern MEM_FEAT_BLOCK_MAIN MemFeatMain; -/*----------------------------------------------------------------------------- -* EXPORTED FUNCTIONS -* -*----------------------------------------------------------------------------- -*/ -BOOLEAN -MemMParallelTraining ( - IN OUT MEM_MAIN_DATA_BLOCK *mmPtr - ); - -/* -----------------------------------------------------------------------------*/ -/** - * - * - * - * - * @param[in,out] *mmPtr - Pointer to the MEM_MAIN_DATA_BLOCK - * - * @return TRUE - No fatal error occurs. - * @return FALSE - Fatal error occurs. - */ -BOOLEAN -MemMParallelTraining ( - IN OUT MEM_MAIN_DATA_BLOCK *mmPtr - ) -{ - AMD_CONFIG_PARAMS *StdHeader; - MEM_DATA_STRUCT *MemPtr; - MEM_NB_BLOCK *NBPtr; - DIE_INFO TrainInfo[MAX_NODES_SUPPORTED]; - AP_DATA_TRANSFER ReturnData; - AGESA_STATUS Status; - UINT8 ApSts; - UINT8 Die; - UINT8 Socket; - UINT32 Module; - UINT32 LowCore; - UINT32 HighCore; - UINT32 Time; - UINT32 TimeOut; - UINT32 TargetApicId; - BOOLEAN StillTraining; - ALLOCATE_HEAP_PARAMS AllocHeapParams; - UINT8 *BufferPtr; - BOOLEAN TimeoutEn; - - NBPtr = mmPtr->NBPtr; - MemPtr = mmPtr->MemPtr; - StdHeader = &(mmPtr->MemPtr->StdHeader); - Time = 0; - TimeOut = PARALLEL_TRAINING_TIMEOUT; - TimeoutEn = TRUE; - IDS_TIMEOUT_CTL (&TimeoutEn); - - IDS_HDT_CONSOLE (MEM_STATUS, "\nStart parallel training\n"); - AGESA_TESTPOINT (TpProcMemBeforeAnyTraining, StdHeader); - // - // Initialize Training Info Array - // - for (Die = 0; Die < mmPtr->DieCount; Die ++) { - Socket = TrainInfo[Die].Socket = NBPtr[Die].MCTPtr->SocketId; - Module = NBPtr[Die].MCTPtr->DieId; - GetGivenModuleCoreRange (Socket, Module, &LowCore, &HighCore, StdHeader); - TrainInfo[Die].Core = (UINT8) (LowCore & 0x000000FF); - IDS_HDT_CONSOLE (MEM_FLOW, "\tLaunch core %d of socket %d\n", LowCore, Socket); - TrainInfo[Die].Training = FALSE; - } - // - // Start Training on Each remote die. - // - for (Die = 0; Die < mmPtr->DieCount; Die ++ ) { - if (Die != BSP_DIE) { - NBPtr[Die].BeforeDqsTraining (&(mmPtr->NBPtr[Die])); - if (NBPtr[Die].MCTPtr->NodeMemSize != 0) { - if (!NBPtr[Die].FeatPtr->Training (&(mmPtr->NBPtr[Die]))) { - // Fail to launch code on AP - PutEventLog (AGESA_ERROR, MEM_ERROR_PARALLEL_TRAINING_LAUNCH_FAIL, NBPtr->Node, NBPtr->Dct, NBPtr->Channel, 0, &NBPtr->MemPtr->StdHeader); - SetMemError (AGESA_ERROR, NBPtr[Die].MCTPtr); - MemPtr->ErrorHandling (NBPtr[Die].MCTPtr, EXCLUDE_ALL_DCT, EXCLUDE_ALL_CHIPSEL, &MemPtr->StdHeader); - } else { - TrainInfo[Die].Training = TRUE; - } - } - } - } - // - // Call training on BSP - // - IDS_HDT_CONSOLE (MEM_STATUS, "Node %d\n", NBPtr[BSP_DIE].Node); - NBPtr[BSP_DIE].BeforeDqsTraining (&(mmPtr->NBPtr[BSP_DIE])); - NBPtr[BSP_DIE].TrainingFlow (&(mmPtr->NBPtr[BSP_DIE])); - NBPtr[BSP_DIE].AfterDqsTraining (&(mmPtr->NBPtr[BSP_DIE])); - - // - // Get Results from remote processors training - // - do { - StillTraining = FALSE; - for (Die = 0; Die < mmPtr->DieCount; Die ++ ) { - // - // For each Die that is training, read the status - // - if (TrainInfo[Die].Training == TRUE) { - GetLocalApicIdForCore (TrainInfo[Die].Socket, TrainInfo[Die].Core, &TargetApicId, StdHeader); - ApSts = ApUtilReadRemoteControlByte (TargetApicId, StdHeader); - if ((ApSts & 0x80) == 0) { - // - // Allocate buffer for received data - // - AllocHeapParams.RequestedBufferSize = ( - sizeof (DIE_STRUCT) + - NBPtr[Die].DctCount * ( - sizeof (DCT_STRUCT) + ( - NBPtr[Die].ChannelCount * ( - sizeof (CH_DEF_STRUCT) + sizeof (MEM_PS_BLOCK) + ( - (NBPtr[Die].MCTPtr->DctData[0].ChData[0].RowCount * - NBPtr[Die].MCTPtr->DctData[0].ChData[0].ColumnCount * - NUMBER_OF_DELAY_TABLES) + - (MAX_BYTELANES_PER_CHANNEL * MAX_CS_PER_CHANNEL * NUMBER_OF_FAILURE_MASK_TABLES) - ) - ) - ) - ) - ) + 3; - AllocHeapParams.BufferHandle = GENERATE_MEM_HANDLE (ALLOC_PAR_TRN_HANDLE, Die, 0, 0); - AllocHeapParams.Persist = HEAP_LOCAL_CACHE; - if (HeapAllocateBuffer (&AllocHeapParams, StdHeader) == AGESA_SUCCESS) { - // - // Receive Training Results - // - - ReturnData.DataPtr = AllocHeapParams.BufferPtr; - ReturnData.DataSizeInDwords = (UINT16) AllocHeapParams.RequestedBufferSize / 4; - ReturnData.DataTransferFlags = 0; - Status = ApUtilReceiveBuffer (TrainInfo[Die].Socket, TrainInfo[Die].Core, &ReturnData, StdHeader); - if (Status != AGESA_SUCCESS) { - SetMemError (Status, NBPtr[Die].MCTPtr); - } - - BufferPtr = AllocHeapParams.BufferPtr; - LibAmdMemCopy (NBPtr[Die].MCTPtr, BufferPtr, sizeof (DIE_STRUCT), StdHeader); - BufferPtr += sizeof (DIE_STRUCT); - LibAmdMemCopy ( NBPtr[Die].MCTPtr->DctData, - BufferPtr, - NBPtr[Die].DctCount * (sizeof (DCT_STRUCT) + NBPtr[Die].ChannelCount * sizeof (CH_DEF_STRUCT)), - StdHeader); - BufferPtr += NBPtr[Die].DctCount * (sizeof (DCT_STRUCT) + NBPtr[Die].ChannelCount * sizeof (CH_DEF_STRUCT)); - LibAmdMemCopy ( NBPtr[Die].PSBlock, - BufferPtr, - NBPtr[Die].DctCount * NBPtr[Die].ChannelCount * sizeof (MEM_PS_BLOCK), - StdHeader); - BufferPtr += NBPtr[Die].DctCount * NBPtr[Die].ChannelCount * sizeof (MEM_PS_BLOCK); - LibAmdMemCopy ( NBPtr[Die].MCTPtr->DctData[0].ChData[0].RcvEnDlys, - BufferPtr, - (NBPtr[Die].DctCount * NBPtr[Die].ChannelCount) * - ((NBPtr[Die].MCTPtr->DctData[0].ChData[0].RowCount * - NBPtr[Die].MCTPtr->DctData[0].ChData[0].ColumnCount * - NUMBER_OF_DELAY_TABLES) + - (MAX_BYTELANES_PER_CHANNEL * MAX_CS_PER_CHANNEL * NUMBER_OF_FAILURE_MASK_TABLES) - ), - StdHeader); - - HeapDeallocateBuffer (AllocHeapParams.BufferHandle, StdHeader); - - NBPtr[Die].AfterDqsTraining (&(mmPtr->NBPtr[Die])); - TrainInfo[Die].Training = FALSE; - } else { - PutEventLog (AGESA_FATAL, MEM_ERROR_HEAP_ALLOCATE_FOR_RECEIVED_DATA, NBPtr[Die].Node, 0, 0, 0, StdHeader); - SetMemError (AGESA_FATAL, NBPtr[Die].MCTPtr); - ASSERT(FALSE); // Insufficient Heap Space allocation for parallel training buffer - } - } else if (ApSts == CORE_IDLE) { - // AP does not have buffer to transmit to BSP - // AP fails to locate a buffer for data transfer - TrainInfo[Die].Training = FALSE; - } else { - // Signal to loop through again - StillTraining = TRUE; - } - } - } - // Wait for 1 us - MemUWait10ns (100, NBPtr->MemPtr); - Time ++; - } while ((StillTraining) && ((Time < TimeOut) || !TimeoutEn)); // Continue until all Dies are finished - // if cannot finish in 1 s, do fatal exit - - if (StillTraining && TimeoutEn) { - // Parallel training time out, do fatal exit, as there is at least one AP hangs. - PutEventLog (AGESA_FATAL, MEM_ERROR_PARALLEL_TRAINING_TIME_OUT, 0, 0, 0, 0, &NBPtr->MemPtr->StdHeader); - SetMemError (AGESA_FATAL, NBPtr[BSP_DIE].MCTPtr); - ASSERT(FALSE); // Timeout occurred while still training - } - - for (Die = 0; Die < mmPtr->DieCount; Die ++ ) { - if (NBPtr[Die].MCTPtr->ErrCode == AGESA_FATAL) { - return FALSE; - } - } - return TRUE; -} diff --git a/src/vendorcode/amd/agesa/f12/Proc/Mem/Main/mmStandardTraining.c b/src/vendorcode/amd/agesa/f12/Proc/Mem/Main/mmStandardTraining.c deleted file mode 100644 index 5f48b0e33d..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/Mem/Main/mmStandardTraining.c +++ /dev/null @@ -1,113 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * mmStandardTraining.c - * - * Main Memory Feature implementation file for Standard Training - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: (Mem/Main) - * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $ - * - **/ -/***************************************************************************** -* -* Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* *************************************************************************** -* -*/ - -/* - *---------------------------------------------------------------------------- - * MODULES USED - * - *---------------------------------------------------------------------------- - */ - - -#include "Porting.h" -#include "AGESA.h" -#include "Ids.h" -#include "cpuRegisters.h" -#include "OptionMemory.h" -#include "mm.h" -#include "mn.h" -#include "mt.h" -#include "ma.h" -#include "Filecode.h" -CODE_GROUP (G1_PEICC) -RDATA_GROUP (G1_PEICC) - -#define FILECODE PROC_MEM_MAIN_MMSTANDARDTRAINING_FILECODE - -/*----------------------------------------------------------------------------- -* EXPORTED FUNCTIONS -* -*----------------------------------------------------------------------------- -*/ -BOOLEAN -MemMStandardTraining ( - IN OUT MEM_MAIN_DATA_BLOCK *mmPtr - ); - -/* -----------------------------------------------------------------------------*/ -/** - * - * MemMStandardTraining - * - * This function implements standard memory training whereby training functions - * for all nodes are run by the BSP. - * - * - * @param[in,out] *mmPtr - Pointer to the MEM_MAIN_DATA_BLOCK - * - * @return TRUE - No fatal error occurs. - * @return FALSE - Fatal error occurs. - */ -BOOLEAN -MemMStandardTraining ( - IN OUT MEM_MAIN_DATA_BLOCK *mmPtr - ) -{ - UINT8 Die; - // - // Run Northbridge-specific Standard Training feature for each die. - // - IDS_HDT_CONSOLE (MEM_STATUS, "\nStart serial training\n"); - for (Die = 0 ; Die < mmPtr->DieCount ; Die ++ ) { - IDS_HDT_CONSOLE (MEM_STATUS, "Node %d\n", Die); - AGESA_TESTPOINT (TpProcMemBeforeAnyTraining, &(mmPtr->MemPtr->StdHeader)); - mmPtr->NBPtr[Die].BeforeDqsTraining (&mmPtr->NBPtr[Die]); - mmPtr->NBPtr[Die].FeatPtr->Training (&mmPtr->NBPtr[Die]); - mmPtr->NBPtr[Die].AfterDqsTraining (&mmPtr->NBPtr[Die]); - if (mmPtr->NBPtr[Die].MCTPtr->ErrCode == AGESA_FATAL) { - break; - } - } - return (BOOLEAN) (Die == mmPtr->DieCount); -} diff --git a/src/vendorcode/amd/agesa/f12/Proc/Mem/Main/mmUmaAlloc.c b/src/vendorcode/amd/agesa/f12/Proc/Mem/Main/mmUmaAlloc.c deleted file mode 100644 index 8bdc7fe78b..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/Mem/Main/mmUmaAlloc.c +++ /dev/null @@ -1,245 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * mmUmaAlloc.c - * - * Main Memory Feature implementation file for UMA allocation. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: (Mem/Main) - * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $ - * - **/ -/***************************************************************************** -* -* Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* *************************************************************************** -* -*/ - -/* - *---------------------------------------------------------------------------- - * MODULES USED - * - *---------------------------------------------------------------------------- - */ - - -#include "AGESA.h" -#include "amdlib.h" -#include "heapManager.h" -#include "OptionMemory.h" -#include "mm.h" -#include "mn.h" -#include "Ids.h" -#include "mport.h" -#include "Filecode.h" -CODE_GROUP (G1_PEICC) -RDATA_GROUP (G1_PEICC) - -#define FILECODE PROC_MEM_MAIN_MMUMAALLOC_FILECODE -/*---------------------------------------------------------------------------- - * DEFINITIONS AND MACROS - * - *---------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------- - * TYPEDEFS AND STRUCTURES - * - *---------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------- - * PROTOTYPES OF LOCAL FUNCTIONS - * - *---------------------------------------------------------------------------- - */ -/*----------------------------------------------------------------------------- -* EXPORTED FUNCTIONS -* -*----------------------------------------------------------------------------- -*/ -BOOLEAN -MemMUmaAlloc ( - IN OUT MEM_MAIN_DATA_BLOCK *MemMainPtr - ); - -extern BUILD_OPT_CFG UserOptions; - -/* -----------------------------------------------------------------------------*/ -/** - * - * - * UMA allocation mechanism. - * - * @param[in,out] *MemMainPtr - Pointer to the MEM_MAIN_DATA_BLOCK - * - */ -BOOLEAN -MemMUmaAlloc ( - IN OUT MEM_MAIN_DATA_BLOCK *MemMainPtr - ) -{ - UINT32 TOM; - UINT32 TOM2; - UINT32 UmaSize; - UINT32 TopOfChIntlv; - UINT32 DctSelHi; - UINT32 UmaAlignment; - UINT32 UmaAbove4GBase; - UINT32 UmaBelow4GBase; - BOOLEAN DctSelIntLvEn; - BOOLEAN UmaAbove4GEn; - S_UINT64 SMsr; - ALLOCATE_HEAP_PARAMS AllocHeapParams; - UMA_INFO *UmaInfoPtr; - - MEM_DATA_STRUCT *MemPtr; - MEM_NB_BLOCK *NBPtr; - MEM_PARAMETER_STRUCT *RefPtr; - - MemPtr = MemMainPtr->MemPtr; - NBPtr = &(MemMainPtr->NBPtr[BSP_DIE]); - RefPtr = NBPtr->RefPtr; - - TOM2 = 0; - SMsr.lo = SMsr.hi = 0; - UmaAbove4GBase = 0; - RefPtr->UmaBase = 0; - UmaAlignment = (UINT32) UserOptions.CfgUmaAlignment; - UmaAbove4GEn = UserOptions.CfgUmaAbove4G; - DctSelIntLvEn = (NBPtr->GetBitField (NBPtr, BFDctSelIntLvEn) == 1) ? TRUE : FALSE; - TopOfChIntlv = NBPtr->GetBitField (NBPtr, BFDctSelBaseAddr) << (27 - 16); - DctSelHi = NBPtr->GetBitField (NBPtr, BFDctSelHi); - - // Allocate heap for UMA_INFO - AllocHeapParams.RequestedBufferSize = sizeof (UMA_INFO); - AllocHeapParams.BufferHandle = AMD_UMA_INFO_HANDLE; - AllocHeapParams.Persist = HEAP_SYSTEM_MEM; - if (AGESA_SUCCESS != HeapAllocateBuffer (&AllocHeapParams, &MemPtr->StdHeader)) { - ASSERT(FALSE); // Could not allocate heap for Uma information. - return FALSE; - } - UmaInfoPtr = (UMA_INFO *) AllocHeapParams.BufferPtr; - // Default all the fields of UMA_INFO - UmaInfoPtr->UmaMode = (UINT8) UMA_NONE; - UmaInfoPtr->UmaSize = 0; - UmaInfoPtr->UmaBase = 0; - UmaInfoPtr->UmaAttributes = 0; - UmaInfoPtr->MemClock = NBPtr->DCTPtr->Timings.TargetSpeed; - - switch (RefPtr->UmaMode) { - case UMA_NONE: - UmaSize = 0; - break; - case UMA_SPECIFIED: - UmaSize = RefPtr->UmaSize; - break; - case UMA_AUTO: - UmaSize = NBPtr->GetUmaSize (NBPtr); - break; - default: - UmaSize = 0; - IDS_ERROR_TRAP; - } - - if (UmaSize != 0) { - //TOM scaled from [47:0] to [47:16] - LibAmdMsrRead (TOP_MEM, (UINT64 *)&SMsr, &(NBPtr->MemPtr->StdHeader)); - TOM = (SMsr.lo >> 16) | (SMsr.hi << (32 - 16)); - - UmaBelow4GBase = (TOM - UmaSize) & UmaAlignment; - // Initialize Ref->UmaBase to UmaBelow4GBase - RefPtr->UmaBase = UmaBelow4GBase; - - // Uma Above 4G support - if (UmaAbove4GEn) { - //TOM2 scaled from [47:0] to [47:16] - LibAmdMsrRead (TOP_MEM2, (UINT64 *)&SMsr, &(NBPtr->MemPtr->StdHeader)); - TOM2 = (SMsr.lo >> 16) | (SMsr.hi << (32 - 16)); - if (TOM2 != 0) { - UmaAbove4GBase = (TOM2 - UmaSize) & UmaAlignment; - //Set UmaAbove4GBase to 0 if UmaAbove4GBase is below 4GB - if (UmaAbove4GBase < _4GB_RJ16) { - UmaAbove4GBase = 0; - } - if (UmaAbove4GBase != 0) { - RefPtr->UmaBase = UmaAbove4GBase; - // 1. TopOfChIntlv == 0 indicates that whole DCT0 and DCT1 memory are interleaved. - // 2. TopOfChIntlv >= TOM tells us : - // -All or portion of Uma region that above 4G is NOT interleaved. - // -Whole Uma region that below 4G is interleaved. - if (DctSelIntLvEn && (TopOfChIntlv >= TOM)) { - RefPtr->UmaBase = UmaBelow4GBase; - } - } - } - } - - UmaInfoPtr->UmaMode = (UINT8) (RefPtr->UmaMode); - UmaInfoPtr->UmaBase = (UINT64) ((UINT64) RefPtr->UmaBase << 16); - - if (RefPtr->UmaBase >= _4GB_RJ16) { - // UmaSize might be extended if it is 128MB or 256MB .. aligned, so update it. - RefPtr->UmaSize = TOM2 - UmaAbove4GBase; - // Uma Typing - MemNSetMTRRUmaRegionUCNb (NBPtr, &UmaAbove4GBase, &TOM2); - if (DctSelIntLvEn && (TopOfChIntlv == 0)) { - UmaInfoPtr->UmaAttributes = UMA_ATTRIBUTE_INTERLEAVE | UMA_ATTRIBUTE_ON_DCT0 | UMA_ATTRIBUTE_ON_DCT1; - } else { - // Entire UMA region is in the high DCT - UmaInfoPtr->UmaAttributes = (DctSelHi == 0) ? UMA_ATTRIBUTE_ON_DCT0 : UMA_ATTRIBUTE_ON_DCT1; - } - } else { - // UmaSize might be extended if it is 128MB or 256MB .. aligned, so update it. - RefPtr->UmaSize = TOM - UmaBelow4GBase; - // Uma Typing - NBPtr->UMAMemTyping (NBPtr); - if (DctSelIntLvEn && ((TopOfChIntlv == 0) || (TopOfChIntlv >= TOM))) { - UmaInfoPtr->UmaAttributes = UMA_ATTRIBUTE_INTERLEAVE | UMA_ATTRIBUTE_ON_DCT0 | UMA_ATTRIBUTE_ON_DCT1; - } else { - if (UmaBelow4GBase >= TopOfChIntlv) { - // Entire UMA region is in the high DCT - UmaInfoPtr->UmaAttributes = (DctSelHi == 0) ? UMA_ATTRIBUTE_ON_DCT0 : UMA_ATTRIBUTE_ON_DCT1; - } else if (TopOfChIntlv >= TOM) { - // Entire UMA region is in the low DCT - UmaInfoPtr->UmaAttributes = (DctSelHi == 1) ? UMA_ATTRIBUTE_ON_DCT0 : UMA_ATTRIBUTE_ON_DCT1; - } else { - // UMA region is in both DCT0 and DCT1 - UmaInfoPtr->UmaAttributes = UMA_ATTRIBUTE_ON_DCT0 | UMA_ATTRIBUTE_ON_DCT1; - } - } - } - UmaInfoPtr->UmaSize = (RefPtr->UmaSize) << 16; - IDS_HDT_CONSOLE (MEM_FLOW, "UMA is allocated:\n\tBase: %x0000\n\tSize: %x0000\n", RefPtr->UmaBase, RefPtr->UmaSize); - } - - return TRUE; -} - diff --git a/src/vendorcode/amd/agesa/f12/Proc/Mem/Main/mmflow.c b/src/vendorcode/amd/agesa/f12/Proc/Mem/Main/mmflow.c deleted file mode 100644 index 8dc1191f8f..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/Mem/Main/mmflow.c +++ /dev/null @@ -1,392 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * mmflow.c - * - * Main Memory Flow Entrypoint file - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: (Mem/Main) - * @e \$Revision: 48768 $ @e \$Date: 2011-03-11 06:18:53 +0800 (Fri, 11 Mar 2011) $ - * - **/ -/***************************************************************************** -* -* Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* *************************************************************************** -* -*/ - -/* - *---------------------------------------------------------------------------- - * MODULES USED - * - *---------------------------------------------------------------------------- - */ - - -#include "AGESA.h" -#include "amdlib.h" -#include "Ids.h" -#include "cpuRegisters.h" -#include "cpuServices.h" -#include "GeneralServices.h" -#include "cpuFamilyTranslation.h" -#include "OptionMemory.h" -#include "mm.h" -#include "mn.h" -#include "mt.h" -#include "mu.h" -#include "heapManager.h" -#include "AdvancedApi.h" -#include "Filecode.h" -CODE_GROUP (G1_PEICC) -RDATA_GROUP (G1_PEICC) - -#define FILECODE PROC_MEM_MAIN_MMFLOW_FILECODE -/* features */ - -extern MEM_NB_SUPPORT memNBInstalled[]; -extern MEM_TECH_CONSTRUCTOR* memTechInstalled[]; -extern MEM_FEAT_BLOCK_MAIN MemFeatMain; -extern MEM_FLOW_CFG* memFlowControlInstalled[]; - -/*---------------------------------------------------------------------------- - * DEFINITIONS AND MACROS - * - *---------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------- - * TYPEDEFS AND STRUCTURES - * - *---------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------- - * PROTOTYPES OF LOCAL FUNCTIONS - * - *---------------------------------------------------------------------------- - */ -VOID -STATIC -MemSPDDataProcess ( - IN OUT MEM_DATA_STRUCT *MemPtr - ); - -/*---------------------------------------------------------------------------- - * EXPORTED FUNCTIONS - * - *---------------------------------------------------------------------------- - */ -/* -----------------------------------------------------------------------------*/ -/** - * - * - * This function is the main memory configuration function for DR DDR3 - * - * Requirements: - * - * Run-Time Requirements: - * 1. Complete Hypertransport Bus Configuration - * 2. AmdMemInitDataStructDef must be run to set default values - * 3. MSR bit to allow access to high PCI regs set on all nodes - * 4. BSP in Big Real Mode - * 5. Stack available - * 6. MCG_CTL=-1, MC4_EN=0 for all CPUs - * 7. MCi_STS from shutdown/warm reset recorded (if desired) prior to entry - * 8. All var MTRRs reset to zero - * 9. State of NB_CFG.DisDatMsk set properly on all CPUs - * - * @param[in,out] *MemPtr - Pointer to the MEM_DATA_STRUCT - * - * @return AGESA_STATUS - * - AGESA_ALERT - * - AGESA_FATAL - * - AGESA_SUCCESS - * - AGESA_WARNING - */ -AGESA_STATUS -AmdMemAuto ( - IN OUT MEM_DATA_STRUCT *MemPtr - ) -{ - MEM_SHARED_DATA mmSharedData; - MEM_MAIN_DATA_BLOCK mmData; - MEM_NB_BLOCK *NBPtr; - MEM_TECH_BLOCK *TechPtr; - ALLOCATE_HEAP_PARAMS AllocHeapParams; - AGESA_STATUS Retval; - UINT8 i; - UINT8 Die; - UINT8 DieCount; - UINT8 Tab; - CPU_SPECIFIC_SERVICES *FamilySpecificServices; - - ASSERT (MemPtr != NULL); - - AGESA_TESTPOINT (TpProcMemAmdMemAuto, &MemPtr->StdHeader); - - IDS_HDT_CONSOLE (MEM_FLOW, "MEM PARAMS:\n"); - IDS_HDT_CONSOLE (MEM_FLOW, "\tBottomIo : %04x\n", MemPtr->ParameterListPtr->BottomIo); - IDS_HDT_CONSOLE (MEM_FLOW, "\tMemHoleRemap : %d\n", MemPtr->ParameterListPtr->MemHoleRemapping); - IDS_HDT_CONSOLE (MEM_FLOW, "\tLimitBelow1TB : %d\n", MemPtr->ParameterListPtr->LimitMemoryToBelow1Tb); - IDS_HDT_CONSOLE (MEM_FLOW, "\tUserTimingMode : %d\n", MemPtr->ParameterListPtr->UserTimingMode); - IDS_HDT_CONSOLE (MEM_FLOW, "\tMemClockValue : %d\n", MemPtr->ParameterListPtr->MemClockValue); - IDS_HDT_CONSOLE (MEM_FLOW, "\tBankIntlv : %d\n", MemPtr->ParameterListPtr->EnableBankIntlv); - IDS_HDT_CONSOLE (MEM_FLOW, "\tNodeIntlv : %d\n", MemPtr->ParameterListPtr->EnableNodeIntlv); - IDS_HDT_CONSOLE (MEM_FLOW, "\tChannelIntlv : %d\n", MemPtr->ParameterListPtr->EnableChannelIntlv); - IDS_HDT_CONSOLE (MEM_FLOW, "\tEccFeature : %d\n", MemPtr->ParameterListPtr->EnableEccFeature); - IDS_HDT_CONSOLE (MEM_FLOW, "\tPowerDown : %d\n", MemPtr->ParameterListPtr->EnablePowerDown); - IDS_HDT_CONSOLE (MEM_FLOW, "\tOnLineSpare : %d\n", MemPtr->ParameterListPtr->EnableOnLineSpareCtl); - IDS_HDT_CONSOLE (MEM_FLOW, "\tParity : %d\n", MemPtr->ParameterListPtr->EnableParity); - IDS_HDT_CONSOLE (MEM_FLOW, "\tBankSwizzle : %d\n", MemPtr->ParameterListPtr->EnableBankSwizzle); - IDS_HDT_CONSOLE (MEM_FLOW, "\tMemClr : %d\n", MemPtr->ParameterListPtr->EnableMemClr); - IDS_HDT_CONSOLE (MEM_FLOW, "\tUmaMode : %d\n", MemPtr->ParameterListPtr->UmaMode); - IDS_HDT_CONSOLE (MEM_FLOW, "\tUmaSize : %d\n", MemPtr->ParameterListPtr->UmaSize); - IDS_HDT_CONSOLE (MEM_FLOW, "\tMemRestoreCtl : %d\n", MemPtr->ParameterListPtr->MemRestoreCtl); - IDS_HDT_CONSOLE (MEM_FLOW, "\tSaveMemContextCtl : %d\n\n", MemPtr->ParameterListPtr->SaveMemContextCtl); - - //---------------------------------------------------------------------------- - // Get TSC rate, which will be used later in Wait10ns routine - //---------------------------------------------------------------------------- - GetCpuServicesOfCurrentCore ((const CPU_SPECIFIC_SERVICES **)&FamilySpecificServices, &MemPtr->StdHeader); - FamilySpecificServices->GetTscRate (FamilySpecificServices, &MemPtr->TscRate, &MemPtr->StdHeader); - - //---------------------------------------------------------------------------- - // Read In SPD Data - //---------------------------------------------------------------------------- - AGESA_TESTPOINT (TpProcMemBeforeSpdProcessing, &MemPtr->StdHeader); - MemSPDDataProcess (MemPtr); - - //---------------------------------------------------------------- - // Initialize Main Data Block - //---------------------------------------------------------------- - mmData.MemPtr = MemPtr; - mmData.mmSharedPtr = &mmSharedData; - LibAmdMemFill (&mmSharedData, 0, sizeof (mmSharedData), &MemPtr->StdHeader); - mmSharedData.DimmExcludeFlag = NORMAL; - mmSharedData.NodeIntlv.IsValid = FALSE; - //---------------------------------------------------------------- - // Discover populated CPUs - // - //---------------------------------------------------------------- - Retval = MemSocketScan (&mmData); - if (Retval == AGESA_FATAL) { - return Retval; - } - DieCount = mmData.DieCount; - //---------------------------------------------------------------- - // - // Allocate Memory for NB and Tech Blocks - // - // NBPtr[Die]----+ - // | - // V - // +---+---+---+---+---+---+---+---+ - // | 0 | 1 | 2 | 3 | 4 | 5 | 6 | 7 | NB Blocks - // +---+---+---+---+---+---+---+---+ - // | | | | | | | | - // | | | | | | | | - // v v v v v v v v - // +---+---+---+---+---+---+---+---+ - // | 0 | 1 | 2 | 3 | 4 | 5 | 6 | 7 | Tech Blocks - // +---+---+---+---+---+---+---+---+ - // - // - //---------------------------------------------------------------- - AllocHeapParams.RequestedBufferSize = (DieCount * (sizeof (MEM_NB_BLOCK) + sizeof (MEM_TECH_BLOCK))); - AllocHeapParams.BufferHandle = AMD_MEM_AUTO_HANDLE; - AllocHeapParams.Persist = HEAP_LOCAL_CACHE; - if (AGESA_SUCCESS != HeapAllocateBuffer (&AllocHeapParams, &MemPtr->StdHeader)) { - ASSERT(FALSE); // NB and Tech Block Heap allocate error - return AGESA_FATAL; - } - NBPtr = (MEM_NB_BLOCK *)AllocHeapParams.BufferPtr; - TechPtr = (MEM_TECH_BLOCK *) (&NBPtr[DieCount]); - mmData.NBPtr = NBPtr; - mmData.TechPtr = TechPtr; - - //---------------------------------------------------------------- - // Create NB Blocks - // - //---------------------------------------------------------------- - for (Die = 0 ; Die < DieCount ; Die++ ) { - i = 0; - while (memNBInstalled[i].MemConstructNBBlock != 0) { - if (memNBInstalled[i].MemConstructNBBlock (&NBPtr[Die], MemPtr, memNBInstalled[i].MemFeatBlock, &mmSharedData, Die) == TRUE) { - break; - } - i++; - } - // Couldn't find a NB which supported this family - if (memNBInstalled[i].MemConstructNBBlock == 0) { - return AGESA_FATAL; - } - } - //---------------------------------------------------------------- - // Create Technology Blocks - // - //---------------------------------------------------------------- - for (Die = 0 ; Die < DieCount ; Die++ ) { - i = 0; - while (memTechInstalled[i] != NULL) { - if (memTechInstalled[i] (&TechPtr[Die], &NBPtr[Die])) { - NBPtr[Die].TechPtr = &TechPtr[Die]; - break; - } - i++; - } - // Couldn't find a Tech block which supported this family - if (memTechInstalled[i] == NULL) { - return AGESA_FATAL; - } - } - //---------------------------------------------------------------- - // - // MEMORY INITIALIZATION TASKS - // - //---------------------------------------------------------------- - i = 0; - while (memFlowControlInstalled[i] != NULL) { - Retval = memFlowControlInstalled[i] (&mmData); - if (MemPtr->IsFlowControlSupported == TRUE) { - break; - } - i++; - } - - //---------------------------------------------------------------- - // Deallocate NB register tables - //---------------------------------------------------------------- - for (Tab = 0; Tab < NumberOfNbRegTables; Tab++) { - HeapDeallocateBuffer (GENERATE_MEM_HANDLE (ALLOC_NB_REG_TABLE, Tab, 0, 0), &MemPtr->StdHeader); - } - - //---------------------------------------------------------------- - // Check for errors and return - //---------------------------------------------------------------- - AGESA_TESTPOINT (TpProcMemEnd, &MemPtr->StdHeader); - for (Die = 0; Die < DieCount; Die++) { - if (NBPtr[Die].MCTPtr->ErrCode > Retval) { - Retval = NBPtr[Die].MCTPtr->ErrCode; - } - } - return Retval; -} - - -/* -----------------------------------------------------------------------------*/ -/** - * - * - * This function fills a default SPD buffer with SPD values for all DIMMs installed in the system - * - * The SPD Buffer is populated with a Socket-Channel-Dimm centric view of the Dimms. At this - * point, the Memory controller type is not known, and the platform BIOS does not know the anything - * about which DIMM is on which DCT. So the DCT relationship is abstracted from the arrangement - * of SPD information here. We use the utility functions GetSpdSocketIndex(), GetMaxChannelsPerSocket(), - * and GetMaxDimmsPerChannel() to Map the SPD data according to which Socket-relative channel the DIMMs - * are connected to. The functions rely on either the maximum values in the - * PlatformSpecificOverridingTable or if unspecified, the absolute maximums in AGESA.H. - * - * This mapping is translated in the Northbridge object Constructor and the Technology block constructor. - * - * @param[in,out] *MemPtr - Pointer to the MEM_DATA_STRUCT - * - */ - -VOID -STATIC -MemSPDDataProcess ( - IN OUT MEM_DATA_STRUCT *MemPtr - ) -{ - UINT8 Socket; - UINT8 Channel; - UINT8 Dimm; - UINT8 DimmIndex; - UINT32 AgesaStatus; - UINT8 MaxSockets; - UINT8 MaxChannelsPerSocket; - UINT8 MaxDimmsPerChannel; - SPD_DEF_STRUCT *DimmSPDPtr; - PSO_TABLE *PsoTable; - ALLOCATE_HEAP_PARAMS AllocHeapParams; - AGESA_READ_SPD_PARAMS SpdParam; - - ASSERT (MemPtr != NULL); - MaxSockets = (UINT8) (0x000000FF & GetPlatformNumberOfSockets ()); - PsoTable = MemPtr->ParameterListPtr->PlatformMemoryConfiguration; - // - // Allocate heap for the table - // - AllocHeapParams.RequestedBufferSize = (GetSpdSocketIndex (PsoTable, MaxSockets, &MemPtr->StdHeader) * sizeof (SPD_DEF_STRUCT)); - AllocHeapParams.BufferHandle = AMD_MEM_SPD_HANDLE; - AllocHeapParams.Persist = HEAP_LOCAL_CACHE; - if (HeapAllocateBuffer (&AllocHeapParams, &MemPtr->StdHeader) == AGESA_SUCCESS) { - MemPtr->SpdDataStructure = (SPD_DEF_STRUCT *) AllocHeapParams.BufferPtr; - // - // Initialize SpdParam Structure - // - LibAmdMemCopy ((VOID *)&SpdParam, (VOID *)MemPtr, (UINTN)sizeof (SpdParam.StdHeader), &MemPtr->StdHeader); - // - // Populate SPDDataBuffer - // - SpdParam.MemData = MemPtr; - DimmIndex = 0; - for (Socket = 0; Socket < (UINT16)MaxSockets; Socket++) { - MaxChannelsPerSocket = GetMaxChannelsPerSocket (PsoTable, Socket, &MemPtr->StdHeader); - SpdParam.SocketId = Socket; - for (Channel = 0; Channel < MaxChannelsPerSocket; Channel++) { - SpdParam.MemChannelId = Channel; - MaxDimmsPerChannel = GetMaxDimmsPerChannel (PsoTable, Socket, Channel); - for (Dimm = 0; Dimm < MaxDimmsPerChannel; Dimm++) { - SpdParam.DimmId = Dimm; - DimmSPDPtr = &(MemPtr->SpdDataStructure[DimmIndex++]); - SpdParam.Buffer = DimmSPDPtr->Data; - AGESA_TESTPOINT (TpProcMemBeforeAgesaReadSpd, &MemPtr->StdHeader); - AgesaStatus = AgesaReadSpd (0, &SpdParam); - AGESA_TESTPOINT (TpProcMemAfterAgesaReadSpd, &MemPtr->StdHeader); - if (AgesaStatus == AGESA_SUCCESS) { - DimmSPDPtr->DimmPresent = TRUE; - IDS_HDT_CONSOLE (MEM_FLOW, "SPD Socket %d Channel %d Dimm %d: %08x\n", Socket, Channel, Dimm, SpdParam.Buffer); - } else { - DimmSPDPtr->DimmPresent = FALSE; - } - } - } - } - } else { - PutEventLog (AGESA_FATAL, MEM_ERROR_HEAP_ALLOCATE_FOR_SPD, 0, 0, 0, 0, &MemPtr->StdHeader); - // - // Assert here if unable to allocate heap for SPDs - // - IDS_ERROR_TRAP; - } -} diff --git a/src/vendorcode/amd/agesa/f12/Proc/Mem/Main/mmlvddr3.h b/src/vendorcode/amd/agesa/f12/Proc/Mem/Main/mmlvddr3.h deleted file mode 100644 index bb689e904e..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/Mem/Main/mmlvddr3.h +++ /dev/null @@ -1,85 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * mmLvDdr3.h - * - * Main low voltage DDR3 support common header - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: (Mem/Main) - * @e \$Revision: 37291 $ @e \$Date: 2010-09-01 13:55:44 -0500 (Wed, 01 Sep 2010) $ - * - **/ -/***************************************************************************** - * - * Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * *************************************************************************** - * - */ - -#ifndef _MMLVDDR3_H_ -#define _MMLVDDR3_H_ - -/*---------------------------------------------------------------------------- - * Mixed (DEFINITIONS AND MACROS / TYPEDEFS, STRUCTURES, ENUMS) - * - *---------------------------------------------------------------------------- - */ - -/*----------------------------------------------------------------------------- - * DEFINITIONS AND MACROS - * - *----------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------- - * TYPEDEFS, STRUCTURES, ENUMS - * - *---------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------- - * FUNCTIONS PROTOTYPE - * - *---------------------------------------------------------------------------- - */ -BOOLEAN -MemMLvDdr3 ( - IN OUT MEM_MAIN_DATA_BLOCK *MemMainPtr - ); - -BOOLEAN -MemMLvDdr3PerformanceEnhPre ( - IN OUT MEM_MAIN_DATA_BLOCK *MemMainPtr - ); - -BOOLEAN -MemMLvDdr3PerformanceEnhFinalize ( - IN OUT MEM_MAIN_DATA_BLOCK *MemMainPtr - ); -#endif /* _MMLVDDR3_H_ */ diff --git a/src/vendorcode/amd/agesa/f12/Proc/Mem/Main/mu.c b/src/vendorcode/amd/agesa/f12/Proc/Mem/Main/mu.c deleted file mode 100644 index c31d794ea0..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/Mem/Main/mu.c +++ /dev/null @@ -1,253 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * HyperTransport features and sequence implementation. - * - * Implements the external AmdHtInitialize entry point. - * Contains routines for directing the sequence of available features. - * Mostly, but not exclusively, AGESA_TESTPOINT invocations should be - * contained in this file, and not in the feature code. - * - * From a build option perspective, it may be that a few lines could be removed - * from compilation in this file for certain options. It is considered that - * the code savings from this are too small to be of concern and this file - * should not have any explicit build option implementation. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: HyperTransport - * @e \$Revision: 35978 $ @e \$Date: 2010-08-07 02:18:50 +0800 (Sat, 07 Aug 2010) $ - * - */ -/* - ***************************************************************************** - * - * Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * *************************************************************************** - * - */ - -/*---------------------------------------------------------------------------------------- - * M O D U L E S U S E D - *---------------------------------------------------------------------------------------- - */ - -#include "AGESA.h" -#include "amdlib.h" -#include "Filecode.h" - -/*---------------------------------------------------------------------------------------- - * D E F I N I T I O N S A N D M A C R O S - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------- - * T Y P E D E F S A N D S T R U C T U R E S - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------- - * P R O T O T Y P E S O F L O C A L F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ - -VOID -MemUWriteCachelines ( - IN UINT32 Address, - IN UINT8 Pattern[], - IN UINT16 ClCount - ); - -VOID -MemUReadCachelines ( - IN UINT8 Buffer[], - IN UINT32 Address, - IN UINT16 ClCount - ); - -VOID -MemUDummyCLRead ( - IN UINT32 Address - ); - -VOID -MemUMFenceInstr ( - VOID - ); - -VOID -MemUFlushPattern ( - IN UINT32 Address, - IN UINT16 ClCount - ); - -VOID -AlignPointerTo16Byte ( - IN OUT UINT8 **BufferPtrPtr - ); - -/*---------------------------------------------------------------------------------------- - * E X P O R T E D F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ - -/*--------------------------------------------------------------------------------------- - * L O C A L F U N C T I O N S - *--------------------------------------------------------------------------------------- - */ - - - -//---------------------------------------------------------------------------- - -VOID -MemUWriteCachelines ( - IN UINT32 Address, - IN UINT8 Pattern[], - IN UINT16 ClCount - ) -{ - UINTN Index; - CHAR8 *Position; - __m128i *Src = (void *) Pattern; - __m128i *Dest = (void *) (size_t)Address; - - Position = (void *) Pattern; - - // ssd - important: without this, the src data may get evicted from cache - _mm_mfence (); - - for (Index = 0; Index < ClCount * 4; Index++){ - _mm_stream_si128_fs (Dest, Src); - Src++; - Dest++; - } - - // ssd - might not be required, but no measurable boot time impact - _mm_mfence (); -} - - -//---------------------------------------------------------------------------- -// MemUReadCachelines: -// -// Read a pattern of 72 bit times (per DQ), to test dram functionality. The -// pattern is a stress pattern which exercises both ISI and crosstalk. The number -// of cache lines to fill is dependent on DCT width mode and burstlength. -// -// In: Buffer - pointer to a buffer where read data will be stored -// Address - Physical address to be read -// ClCount - number of cachelines to be read - -VOID -MemUReadCachelines ( - IN UINT8 Buffer[], - IN UINT32 Address, - IN UINT16 ClCount - ) -{ - UINTN Index; - UINT32 *Dest; - - for (Index = 0; Index < ClCount * 16; Index++) { - Dest = (void *) &Buffer [Index * 4]; - *Dest = __readfsdword (Address + Index * 4); - _mm_mfence (); - } -} - -//---------------------------------------------------------------------------- -// MemUDummyCLRead: -// -// Perform a single cache line read from a given physical address. -// -// In: Address - Physical address to be read -// ClCount - number of cachelines to be read - -//FUNC_ATTRIBUTE (noinline) -VOID -MemUDummyCLRead ( - IN UINT32 Address - ) -{ - _mm_sfence (); - __readfsbyte (Address); -} - -//---------------------------------------------------------------------------- - -VOID -MemUMFenceInstr ( - VOID - ) -{ - _mm_mfence (); -} - -//---------------------------------------------------------------------------- -// MemUFlushPattern: -// -// Flush a pattern of 72 bit times (per DQ) from cache. This procedure is used -// to ensure cache miss on the next read training. -// -// In: Address - Physical address to be flushed -// ClCount - number of cachelines to be flushed -//FUNC_ATTRIBUTE(noinline) -VOID -MemUFlushPattern ( - IN UINT32 Address, - IN UINT16 ClCount - ) -{ - UINTN Index; - - // ssd - theory: a tlb flush is needed to avoid problems with clflush - __writemsr (0x20F, __readmsr (0x20F)); - - for (Index = 0; Index < ClCount; Index++) { - // mfence prevents speculative execution of the clflush - _mm_mfence (); - _mm_clflush_fs ((void *) (size_t) (Address + Index * 64)); - } -} - -//---------------------------------------------------------------------------- - -//FUNC_ATTRIBUTE(noinline) -VOID -AlignPointerTo16Byte ( - IN OUT UINT8 **BufferPtrPtr - ) -{ - size_t Address = (size_t) *BufferPtrPtr; - Address += 15; - Address -= Address % 16; - *BufferPtrPtr = (void *) Address; -} - -//---------------------------------------------------------------------------- diff --git a/src/vendorcode/amd/agesa/f12/Proc/Mem/Main/muc.c b/src/vendorcode/amd/agesa/f12/Proc/Mem/Main/muc.c deleted file mode 100644 index a6d7bb1aff..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/Mem/Main/muc.c +++ /dev/null @@ -1,669 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * muc.c - * - * Utility functions - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: (Mem/Main) - * @e \$Revision: 45735 $ @e \$Date: 2011-01-21 07:49:28 +0800 (Fri, 21 Jan 2011) $ - * - **/ -/***************************************************************************** -* -* Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* *************************************************************************** -* -*/ - -/* - *---------------------------------------------------------------------------- - * MODULES USED - * - *---------------------------------------------------------------------------- - */ - - - -#include "AGESA.h" -#include "cpuRegisters.h" -#include "cpuServices.h" -#include "amdlib.h" -#include "OptionMemory.h" -#include "PlatformMemoryConfiguration.h" -#include "Ids.h" -#include "mport.h" -#include "mu.h" -#include "cpuFamilyTranslation.h" -#include "cpuCacheInit.h" -#include "Filecode.h" -CODE_GROUP (G1_PEICC) -RDATA_GROUP (G1_PEICC) - -#define FILECODE PROC_MEM_MAIN_MUC_FILECODE -/*---------------------------------------------------------------------------- - * DEFINITIONS AND MACROS - * - *---------------------------------------------------------------------------- - */ -CONST UINT32 Pattern2[16] = { - 0x12345678, 0x87654321, 0x23456789, 0x98765432, - 0x59385824, 0x30496724, 0x24490795, 0x99938733, - 0x40385642, 0x38465245, 0x29432163, 0x05067894, - 0x12349045, 0x98723467, 0x12387634, 0x34587623 -}; - -CONST UINT32 MaxLatPat[48] = { - 0x6E0E3FAC, 0x0C3CFF52, - 0x4A688181, 0x49C5B613, - 0x7C780BA6, 0x5C1650E3, - 0x0C4F9D76, 0x0C6753E6, - 0x205535A5, 0xBABFB6CA, - 0x610E6E5F, 0x0C5F1C87, - 0x488493CE, 0x14C9C383, - 0xF5B9A5CD, 0x9CE8F615, - - 0xAAD714B5, 0xC38F1B4C, - 0x72ED647C, 0x669F7562, - 0x5233F802, 0x4A898B30, - 0x10A40617, 0x3326B465, - 0x55386E04, 0xC807E3D3, - 0xAB49E193, 0x14B4E63A, - 0x67DF2495, 0xEA517C45, - 0x7624CE51, 0xF8140C51, - - 0x4824BD23, 0xB61DD0C9, - 0x072BCFBE, 0xE8F3807D, - 0x919EA373, 0x25E30C47, - 0xFEB12958, 0x4DA80A5A, - 0xE9A0DDF8, 0x792B0076, - 0xE81C73DC, 0xF025B496, - 0x1DB7E627, 0x808594FE, - 0x82668268, 0x655C7783 -}; - -CONST UINT8 PatternJD[9] = {0x44, 0xA6, 0x38, 0x4F, 0x4B, 0x2E, 0xEF, 0xD5, 0x54}; - -CONST UINT8 PatternJD_256[256] = { - 0x00, 0xFF, 0x00, 0x00, 0xFF, 0x00, 0x00, 0x00, - 0xFF, 0x00, 0x00, 0x00, 0x00, 0xFF, 0x00, 0xFF, - 0xFF, 0x00, 0xFF, 0xFF, 0xFF, 0x00, 0xFF, 0xFF, - 0xFF, 0xFF, 0x00, 0xF7, 0x08, 0xF7, 0x00, 0xFF, - 0x00, 0xF7, 0x00, 0xFF, 0x00, 0xF7, 0x00, 0xF7, - 0x08, 0xF7, 0x08, 0xFF, 0x00, 0xFF, 0x08, 0xFF, - 0x00, 0xFF, 0x08, 0xFF, 0x08, 0xF7, 0xFB, 0x04, - 0xFB, 0xFB, 0x04, 0xFB, 0xFB, 0xFB, 0x04, 0xFB, - 0xFB, 0xFB, 0xFB, 0x04, 0xFB, 0x04, 0x04, 0xFB, - 0x04, 0x04, 0x04, 0xFB, 0x04, 0x04, 0x04, 0x04, - 0xFB, 0x7F, 0x80, 0x7F, 0x00, 0xFF, 0x00, 0x7F, - 0x00, 0xFF, 0x00, 0x7F, 0x00, 0x7F, 0x80, 0x7F, - 0x80, 0xFF, 0x00, 0xFF, 0x80, 0xFF, 0x00, 0xFF, - 0x80, 0xFF, 0x80, 0x7F, 0xBF, 0x40, 0xBF, 0xBF, - 0x40, 0xBF, 0xBF, 0xBF, 0x40, 0xBF, 0xBF, 0xBF, - 0xBF, 0x40, 0xBF, 0x40, 0x40, 0xBF, 0x40, 0x40, - 0x40, 0xBF, 0x40, 0x40, 0x40, 0x40, 0xBF, 0xFD, - 0x02, 0xFD, 0x00, 0xFF, 0x00, 0xFD, 0x00, 0xFF, - 0x00, 0xFD, 0x00, 0xFD, 0x02, 0xFD, 0x02, 0xFF, - 0x00, 0xFF, 0x02, 0xFF, 0x00, 0xFF, 0x02, 0xFF, - 0x02, 0xFD, 0xFE, 0x01, 0xFE, 0xFE, 0x01, 0xFE, - 0xFE, 0xFE, 0x01, 0xFE, 0xFE, 0xFE, 0xFE, 0x01, - 0xFE, 0x01, 0x01, 0xFE, 0x01, 0x01, 0x01, 0xFE, - 0x01, 0x01, 0x01, 0x01, 0xFE, 0xDF, 0x20, 0xDF, - 0x00, 0xFF, 0x00, 0xDF, 0x00, 0xFF, 0x00, 0xDF, - 0x00, 0xDF, 0x20, 0xDF, 0x20, 0xFF, 0x00, 0xFF, - 0x20, 0xFF, 0x00, 0xFF, 0x20, 0xFF, 0x20, 0xDF, - 0xEF, 0x10, 0xEF, 0xEF, 0x10, 0xEF, 0xEF, 0xEF, - 0x10, 0xEF, 0xEF, 0xEF, 0xEF, 0x10, 0xEF, 0x10, - 0x10, 0xEF, 0x10, 0x10, 0x10, 0xEF, 0x10, 0x10, - 0x10, 0x10, 0xEF, 0xF7, 0x00, 0xFF, 0x04, 0x7F, - 0x00, 0xFF, 0x40, 0xFD, 0x00, 0xFF, 0x01, 0xDF -}; - -/*---------------------------------------------------------------------------- - * TYPEDEFS AND STRUCTURES - * - *---------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------- - * PROTOTYPES OF LOCAL FUNCTIONS - * - *---------------------------------------------------------------------------- - */ - - -/*---------------------------------------------------------------------------- - * EXPORTED FUNCTIONS - * - *---------------------------------------------------------------------------- - */ -/* -----------------------------------------------------------------------------*/ -/** - * - * This function returns the (index)th UINT8 - * from an indicated test pattern. - * - * @param[in] Pattern - encoding of test pattern type - * @param[in] Buffer[] - buffer to be filled - * @param[in] Size - Size of the buffer - * - * ---------------------------------------------------------------------------- - */ - -VOID -MemUFillTrainPattern ( - IN TRAIN_PATTERN Pattern, - IN UINT8 Buffer[], - IN UINT16 Size - ) -{ - UINT8 Result; - UINT8 i; - UINT8 Mask; - UINT16 Index; - UINT16 k; - - for (Index = 0; Index < Size; Index++) { - k = Index; - // get one byte from Pattern - switch (Pattern) { - case TestPattern0: - Result = 0xAA; - break; - case TestPattern1: - Result = 0x55; - break; - case TestPattern2: - ASSERT (Index < sizeof (Pattern2)); - Result = ((UINT8 *)Pattern2)[Index]; - break; - case TestPatternML: - if (Size != 6 * 64) { - Result = ((UINT8 *)MaxLatPat)[Index]; - } else { - Result = ((UINT8 *)MaxLatPat)[Index & 0xF7]; - } - break; - case TestPatternJD256B: - k >>= 1; - // fall through - TestPatternJD256B also need to run TestPatternJD256A sequence - case TestPatternJD256A: - k >>= 3; - ASSERT (k < sizeof (PatternJD_256)); - Result = PatternJD_256[k]; - break; - case TestPatternJD1B: - k >>= 1; - // fall through - TestPatternJD1B also need to run TestPatternJD1A sequence - case TestPatternJD1A: - k >>= 3; - i = (UINT8) (k >> 3); - Mask = (UINT8) (0x80 >> (k & 7)); - - if (i == 0) { - Result = 0; - } else { - Result = (UINT16)1 << (i - 1); - } - - ASSERT (i < sizeof (PatternJD)); - if (PatternJD[i] & Mask) { - Result = ~Result; - } - break; - case TestPattern3: - Result = 0x36; - break; - case TestPattern4: - Result = 0xC9; - break; - default: - Result = 0; - IDS_ERROR_TRAP; - } - - // fill in the Pattern buffer - Buffer[Index] = Result; - } -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * This function flushes cache lines - * - * @param[in,out] MemPtr - pointer to MEM_DATA_STRUCTURE - * @param[in] ClCount - Number of cache lines - * @param[in] Address - System Address [47:16] - * - * ---------------------------------------------------------------------------- - */ - -VOID -MemUProcIOClFlush ( - IN UINT32 Address, - IN UINT16 ClCount, - IN OUT MEM_DATA_STRUCT *MemPtr - ) -{ - MemUSetTargetWTIO (Address, MemPtr); - MemUFlushPattern (MemUSetUpperFSbase (Address, MemPtr), ClCount); - MemUResetTargetWTIO (MemPtr); -} - -/*---------------------------------------------------------------------------- - * LOCAL FUNCTIONS - * - *---------------------------------------------------------------------------- - */ - -/* -----------------------------------------------------------------------------*/ -/** - * - * This function sets the upper 32-bits of the Base address, 4GB aligned) for the FS selector. - * @param[in,out] MemPtr - pointer to MEM_DATA_STRUCTURE - * @param[in] Address - System Address [47:16] - * - * @return Address - Lowest 32-bit of physical address - * ---------------------------------------------------------------------------- - */ - -UINT32 -MemUSetUpperFSbase ( - IN UINT32 Address, - IN OUT MEM_DATA_STRUCT *MemPtr - ) -{ - S_UINT64 SMsr; - - SMsr.lo = 0; - SMsr.hi = Address >> 16; - LibAmdMsrWrite (FS_BASE, (UINT64 *)&SMsr, &MemPtr->StdHeader); - return Address << 16; -} - - -/* -----------------------------------------------------------------------------*/ -/** - * - * This function resets the target address space to Write Through IO by disabling IORRs - * - * @param[in,out] MemPtr - pointer to MEM_DATA_STRUCTURE - * - * ---------------------------------------------------------------------------- - */ - -VOID -MemUResetTargetWTIO ( - IN OUT MEM_DATA_STRUCT *MemPtr - ) -{ - S_UINT64 SMsr; - SMsr.hi = 0; - SMsr.lo = 0; - LibAmdMsrWrite (IORR0_MASK, (UINT64 *)&SMsr, &MemPtr->StdHeader); -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * This function sets the target range to WT IO (using an IORR overlapping - * the already existing - * - * @param[in,out] MemPtr - pointer to MEM_DATA_STRUCTURE - * @param[in] Address - System Address [47:16] - * - * ---------------------------------------------------------------------------- - */ - -VOID -MemUSetTargetWTIO ( - IN UINT32 Address, - IN OUT MEM_DATA_STRUCT *MemPtr - ) -{ - S_UINT64 SMsr; - - SMsr.lo = Address << 16; - SMsr.hi = Address >> 16; - LibAmdMsrWrite (IORR0_BASE,(UINT64 *)&SMsr, &MemPtr->StdHeader); // IORR0 Base - SMsr.hi = 0xFFFF; - SMsr.lo = 0xFC000800; - LibAmdMsrWrite (IORR0_MASK, (UINT64 *)&SMsr, &MemPtr->StdHeader); // 64MB Mask -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * Waits specified number of 10ns cycles - * @param[in,out] MemPtr - pointer to MEM_DATA_STRUCTURE - * @param[in] Count - Number of 10ns cycles to wait; Note that Count must not exceed 1000000 - * - * ---------------------------------------------------------------------------- - */ - -VOID -MemUWait10ns ( - IN UINT32 Count, - IN OUT MEM_DATA_STRUCT *MemPtr - ) -{ - UINT64 TargetTsc; - UINT64 CurrentTsc; - - ASSERT (Count <= 1000000); - - MemUMFenceInstr (); - - LibAmdMsrRead (TSC, &CurrentTsc, &MemPtr->StdHeader); - TargetTsc = CurrentTsc + ((Count * MemPtr->TscRate + 99) / 100); - do { - LibAmdMsrRead (TSC, &CurrentTsc, &MemPtr->StdHeader); - } while (CurrentTsc < TargetTsc); -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * Find the entry of platform specific overriding table. - * - * @param[in] PlatformMemoryConfiguration - Platform config table - * @param[in] EntryType - Entry type - * @param[in] SocketID - Physical socket ID - * @param[in] ChannelID - Physical channel ID - * - * @return NULL - entry could not be found. - * @return Pointer - points to the entry's data. - * - * ---------------------------------------------------------------------------- - */ - -VOID * -FindPSOverrideEntry ( - IN PSO_TABLE *PlatformMemoryConfiguration, - IN PSO_ENTRY EntryType, - IN UINT8 SocketID, - IN UINT8 ChannelID - ) -{ - UINT8 *Buffer; - - Buffer = PlatformMemoryConfiguration; - while (Buffer[0] != PSO_END) { - if (Buffer[0] == EntryType) { - if ((Buffer[2] & ((UINT8) 1 << SocketID)) != 0 ) { - if ((Buffer[3] & ((UINT8) 1 << ChannelID)) != 0 ) { - return &Buffer[4]; - } - } - } - Buffer += Buffer[1] + 2; - } - return NULL; -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * - * This function returns the max dimms for a given memory channel on a given - * processor. It first searches the platform override table for the max dimms - * value. If it is not provided, the AGESA default value is returned. The target - * socket must be a valid present socket. - * - * @param[in] PlatformMemoryConfiguration - Platform config table - * @param[in] SocketID - ID of the processor that owns the channel - * @param[in] ChannelID - Channel to get max dimms for - * - * - * @return UINT8 - Max Number of Dimms for that channel - */ -UINT8 -GetMaxDimmsPerChannel ( - IN PSO_TABLE *PlatformMemoryConfiguration, - IN UINT8 SocketID, - IN UINT8 ChannelID - ) -{ - UINT8 *DimmsPerChPtr; - UINT8 MaxDimmPerCH; - - DimmsPerChPtr = FindPSOverrideEntry (PlatformMemoryConfiguration, PSO_MAX_DIMMS, SocketID, ChannelID); - if (DimmsPerChPtr != NULL) { - MaxDimmPerCH = *DimmsPerChPtr; - } else { - MaxDimmPerCH = MAX_DIMMS_PER_CHANNEL; - } - // Maximum number of dimms per channel cannot be larger than its default value. - ASSERT (MaxDimmPerCH <= MAX_DIMMS_PER_CHANNEL); - - return MaxDimmPerCH; -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * - * This function returns the max memory channels on a given processor. - * It first searches the platform override table for the max channels value. - * If it is not provided, the AGESA default value is returned. - * - * @param[in] PlatformMemoryConfiguration - Platform config table - * @param[in] SocketID - ID of the processor - * @param[in] StdHeader - Header for library and services - * - * - * @return UINT8 - Max Number of Channels on that Processor - */ -UINT8 -GetMaxChannelsPerSocket ( - IN PSO_TABLE *PlatformMemoryConfiguration, - IN UINT8 SocketID, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - UINT8 *ChannelsPerSocketPtr; - UINT8 MaxChannelsPerSocket; - - if (IsProcessorPresent (SocketID, StdHeader)) { - ChannelsPerSocketPtr = FindPSOverrideEntry (PlatformMemoryConfiguration, PSO_MAX_CHNLS, SocketID, 0); - if (ChannelsPerSocketPtr != NULL) { - MaxChannelsPerSocket = *ChannelsPerSocketPtr; - } else { - MaxChannelsPerSocket = MAX_CHANNELS_PER_SOCKET; - } - // Maximum number of channels per socket cannot be larger than its default value. - ASSERT (MaxChannelsPerSocket <= MAX_CHANNELS_PER_SOCKET); - } else { - MaxChannelsPerSocket = 0; - } - - return MaxChannelsPerSocket; -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * - * This function returns the max number of chip select on a given channel of - * a given processor. It first searches the platform override table for the max - * chip select value. If it is not provided, the AGESA default value is returned. - * The target socket must be a valid present socket. - * - * @param[in] PlatformMemoryConfiguration - Platform config table - * @param[in] SocketID - ID of the processor - * @param[in] ChannelID - ID of a channel - * - * - * @return UINT8 - Max Number of chip selects on the channel of the Processor - */ -UINT8 -GetMaxCSPerChannel ( - IN PSO_TABLE *PlatformMemoryConfiguration, - IN UINT8 SocketID, - IN UINT8 ChannelID - ) -{ - UINT8 *CSPerSocketPtr; - UINT8 MaxCSPerChannel; - - CSPerSocketPtr = FindPSOverrideEntry (PlatformMemoryConfiguration, PSO_MAX_CHIPSELS, SocketID, ChannelID); - if (CSPerSocketPtr != NULL) { - MaxCSPerChannel = *CSPerSocketPtr; - } else { - MaxCSPerChannel = MAX_CS_PER_CHANNEL; - } - // Max chip select per channel cannot be larger than its default value - ASSERT (MaxCSPerChannel <= MAX_CS_PER_CHANNEL); - - return MaxCSPerChannel; -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * - * This function returns the index of the first Dimm SPD structure for a - * given processor socket. It checks the Max Dimms per channel for every memory - * channel on every processor up to the current one, and adds them together. - * - * This function may also be used to calculate the maximum dimms per system - * by passing the total number of dimm sockets - * - * @param[in] PlatformMemoryConfiguration - Platform config table - * @param[in] SocketID - ID of the processor - * @param[in] StdHeader - Header for library and services - * - * @return UINT8 - SPD Index - */ -UINT8 -GetSpdSocketIndex ( - IN PSO_TABLE *PlatformMemoryConfiguration, - IN UINT8 SocketID, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - UINT8 SpdSocketIndex; - UINT8 Socket; - UINT8 Channel; - UINT8 MaxChannelsPerSocket; - - SpdSocketIndex = 0; - for (Socket = 0; Socket < SocketID; Socket++) { - MaxChannelsPerSocket = GetMaxChannelsPerSocket (PlatformMemoryConfiguration, Socket, StdHeader); - for (Channel = 0; Channel < MaxChannelsPerSocket; Channel++) { - SpdSocketIndex = SpdSocketIndex + GetMaxDimmsPerChannel (PlatformMemoryConfiguration, Socket, Channel); - } - } - return SpdSocketIndex; -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * - * This function returns the index of the first Dimm SPD structure for a - * given channel relative to the processor socket. It checks the Max Dimms per - * channel for every memory channel on that processor up to the current one, - * and adds them together. - * - * This function may also be used to calculate the maximum dimms per system - * by passing the total number of DIMM sockets - * - * @param[in] PlatformMemoryConfiguration - Platform config table - * @param[in] SocketID - ID of the processor - * @param[in] ChannelID - ID of the Channel - * @param[in] StdHeader - Header for library and services - * - * @return UINT8 - SPD Index - */ -UINT8 -GetSpdChannelIndex ( - IN PSO_TABLE *PlatformMemoryConfiguration, - IN UINT8 SocketID, - IN UINT8 ChannelID, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - UINT8 SpdChannelIndex; - UINT8 Channel; - - SpdChannelIndex = 0; - ASSERT (ChannelID < GetMaxChannelsPerSocket (PlatformMemoryConfiguration, SocketID, StdHeader)) - for (Channel = 0; Channel < ChannelID; Channel++) { - SpdChannelIndex = SpdChannelIndex + GetMaxDimmsPerChannel (PlatformMemoryConfiguration, SocketID, Channel); - } - return SpdChannelIndex; -} - -/*-----------------------------------------------------------------------------*/ -/** - * - * This function returns the upper 32 bits mask for variable MTRR based on - * the CPU_LOGICAL_ID. - * @param[in] *LogicalIdPtr - Pointer to the CPU_LOGICAL_ID - * @param[in] StdHeader - Header for library and services - * - * @return UINT32 - MTRR mask for upper 32 bits - * - */ -UINT32 -GetVarMtrrHiMsk ( - IN CPU_LOGICAL_ID *LogicalIdPtr, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - UINT8 TempNotCare; - CPU_SPECIFIC_SERVICES *FamilySpecificServices; - CACHE_INFO *CacheInfoPtr; - - GetCpuServicesFromLogicalId (LogicalIdPtr, (const CPU_SPECIFIC_SERVICES **)&FamilySpecificServices, StdHeader); - FamilySpecificServices->GetCacheInfo (FamilySpecificServices, (const VOID **)&CacheInfoPtr, &TempNotCare, StdHeader); - return (UINT32) (CacheInfoPtr->VariableMtrrMask >> 32); -} - - -/*-----------------------------------------------------------------------------*/ -/** - * - * This function returns number of memclk converted from ns - * @param[in] Speed - memclk frequency - * @param[in] NumberOfns - number of ns to be converted - * - * @return UINT32 - number of memclk - * - */ -UINT32 -MemUnsToMemClk ( - IN MEMORY_BUS_SPEED Speed, - IN UINT32 NumberOfns - ) -{ - return (UINT32) ((NumberOfns * Speed + 999) / 1000); -} diff --git a/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/LN/Makefile.inc b/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/LN/Makefile.inc deleted file mode 100644 index 2c6cb498d7..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/LN/Makefile.inc +++ /dev/null @@ -1,10 +0,0 @@ -libagesa-y += mnS3ln.c -libagesa-y += mndctln.c -libagesa-y += mnflowln.c -libagesa-y += mnidendimmln.c -libagesa-y += mnln.c -libagesa-y += mnmctln.c -libagesa-y += mnotln.c -libagesa-y += mnphyln.c -libagesa-y += mnprotoln.c -libagesa-y += mnregln.c diff --git a/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/LN/mnS3ln.c b/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/LN/mnS3ln.c deleted file mode 100644 index 812c6041b3..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/LN/mnS3ln.c +++ /dev/null @@ -1,794 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * mns3ln.c - * - * LN memory specific function to support S3 resume - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: (Mem/NB/LN) - * @e \$Revision: 51670 $ @e \$Date: 2011-04-27 03:26:02 +0800 (Wed, 27 Apr 2011) $ - * - **/ -/***************************************************************************** -* -* Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* *************************************************************************** -* -*/ - -/* - *---------------------------------------------------------------------------- - * MODULES USED - * - *---------------------------------------------------------------------------- - */ - - - -#include "AGESA.h" -#include "AdvancedApi.h" -#include "amdlib.h" -#include "Ids.h" -#include "OptionMemory.h" -#include "mm.h" -#include "mn.h" -#include "S3.h" -#include "mfs3.h" -#include "mnln.h" -#include "cpuRegisters.h" -#include "cpuFamRegisters.h" -#include "cpuFamilyTranslation.h" -#include "GeneralServices.h" -#include "cpuCommonF12Utilities.h" -#include "mnS3ln.h" -#include "heapManager.h" -#include "Filecode.h" -CODE_GROUP (G3_DXE) -RDATA_GROUP (G3_DXE) - -#define FILECODE PROC_MEM_NB_LN_MNS3LN_FILECODE - -/*---------------------------------------------------------------------------- - * TYPEDEFS AND STRUCTURES - * - *---------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------- - * PROTOTYPES OF LOCAL FUNCTIONS - * - *---------------------------------------------------------------------------- - */ -BOOLEAN -MemS3ResumeConstructNBBlockLN ( - IN OUT VOID *S3NBPtr, - IN OUT MEM_DATA_STRUCT *MemPtr, - IN UINT8 NodeID - ); - -UINT16 -STATIC -MemNS3GetRegLstPtrLN ( - IN OUT MEM_NB_BLOCK *NBPtr, - IN OUT DESCRIPTOR_GROUP *DescriptPtr - ); - -AGESA_STATUS -STATIC -MemNS3GetDeviceRegLstLN ( - IN UINT32 RegisterLstID, - OUT VOID **RegisterHeader - ); - -VOID -STATIC -MemNS3SetDfltPllLockTimeLN ( - IN ACCESS_WIDTH AccessWidth, - IN PCI_ADDR Address, - IN OUT VOID *Value, - IN OUT VOID *ConfigPtr - ); - -VOID -STATIC -MemNS3SetDramPhyCtrlRegLN ( - IN ACCESS_WIDTH AccessWidth, - IN PCI_ADDR Address, - IN OUT VOID *Value, - IN OUT VOID *ConfigPtr - ); - -BOOLEAN -STATIC -MemNS3ChangeNbFrequencyWrapLN ( - IN OUT MEM_NB_BLOCK *NBPtr, - IN UINT32 NBPstate - ); - -VOID -STATIC -MemNS3GetConPCIMaskLN ( - IN OUT MEM_NB_BLOCK *NBPtr, - IN OUT DESCRIPTOR_GROUP *DescriptPtr - ); -/*---------------------------------------------------------------------------- - * DEFINITIONS AND MACROS - * - *---------------------------------------------------------------------------- - */ -PCI_SPECIAL_CASE PciSpecialCaseFuncLN[] = { - {MemNS3GetCSRNb, MemNS3SetCSRNb}, - {MemNS3GetBitFieldNb, MemNS3SetBitFieldNb}, - {MemNS3DisNbPsDbgNb, MemNS3DisNbPsDbgNb}, - {MemNS3EnNbPsDbg1Nb, MemNS3EnNbPsDbg1Nb}, - { (VOID (*) (ACCESS_WIDTH, PCI_ADDR, VOID *, VOID *)) memDefRet, MemNS3SetDfltPllLockTimeLN}, - { (VOID (*) (ACCESS_WIDTH, PCI_ADDR, VOID *, VOID *)) memDefRet, MemNS3SetDisAutoCompUnb}, - { (VOID (*) (ACCESS_WIDTH, PCI_ADDR, VOID *, VOID *)) memDefRet, MemNS3SetDynModeChangeNb}, - { (VOID (*) (ACCESS_WIDTH, PCI_ADDR, VOID *, VOID *)) memDefRet, MemNS3DisableChannelNb}, - {MemNS3GetBitFieldNb, MemNS3SetDramPhyCtrlRegLN}, - {MemNS3GetBitFieldNb, MemNS3SetPreDriverCalUnb}, - {MemNS3GetBitFieldNb, MemNS3SetPhyClkDllFineClientNb} -}; - -PCI_REG_DESCRIPTOR ROMDATA S3PciPreSelfRefDescriptorLN[] = { - {{0, 0, 0}, FUNC_2, 0x110, 0x00FFFFCF}, - {{0, 0, 0}, FUNC_1, 0x40, 0xFFFF0003}, - {{0, 0, 0}, FUNC_1, 0x44, 0xFFFF0000}, - {{0, 0, 0}, FUNC_1, 0xF0, 0xFF00FF81}, - {{0, 2, 0}, FUNC_2, 0x10C, 0x0000FFFF}, - {{0, 0, 0}, FUNC_2, 0x114, 0x00FFFE00}, - {{0, 0, 0}, FUNC_2, 0x118, 0x0F00CFFF}, - {{0, 0, 0}, FUNC_2, 0x11C, 0x61CC507C} -}; - -CONST PCI_REGISTER_BLOCK_HEADER ROMDATA S3PciPreSelfRefLN = { - 0, - (sizeof (S3PciPreSelfRefDescriptorLN) / sizeof (PCI_REG_DESCRIPTOR)), - S3PciPreSelfRefDescriptorLN, - NULL -}; - -CONDITIONAL_PCI_REG_DESCRIPTOR ROMDATA S3CPciPreSelfDescriptorLN[] = { - // DCT 0 - {{0, 0, 0}, FUNC_2, 0x40, 0x1FF83FED, DCT0_MASK, DCT0_ANY_DIMM_MASK}, - {{0, 0, 0}, FUNC_2, 0x44, 0x1FF83FED, DCT0_MASK, DCT0_ANY_DIMM_MASK}, - {{0, 0, 0}, FUNC_2, 0x48, 0x1FF83FED, DCT0_MASK, DCT0_ANY_DIMM_MASK}, - {{0, 0, 0}, FUNC_2, 0x4C, 0x1FF83FED, DCT0_MASK, DCT0_ANY_DIMM_MASK}, - {{0, 0, 0}, FUNC_2, 0x60, 0x1FF83FE0, DCT0_MASK, DCT0_ANY_DIMM_MASK}, - {{0, 0, 0}, FUNC_2, 0x64, 0x1FF83FE0, DCT0_MASK, DCT0_ANY_DIMM_MASK}, - {{0, 1, 0}, FUNC_2, 0x80, 0x000000FF, DCT0_MASK, DCT0_ANY_DIMM_MASK}, - {{0, 0, 0}, FUNC_2, 0x84, 0x00FC2FFF, DCT0_MASK, DCT0_ANY_DIMM_MASK}, - {{0, 0, 0}, FUNC_2, 0x88, 0xFF00000F, DCT0_MASK, DCT0_ANY_DIMM_MASK}, - {{0, 0, 0}, FUNC_2, 0x8C, 0x03F7FCFF, DCT0_MASK, DCT0_ANY_DIMM_MASK}, - {{0, 0, 0}, FUNC_2, 0x90, 0x0EF20003, DCT0_MASK, DCT0_ANY_DIMM_MASK}, - {{0, 1, 0}, FUNC_2, 0xA4, 0x00000007, DCT0_MASK + DCT1_MASK, ANY_DIMM_MASK}, - {{0, 0, 0}, FUNC_2, 0xA8, 0x0078FF1F, DCT0_MASK, DCT0_ANY_DIMM_MASK}, - {{0, 2, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_EXTRA_FLAG, 0, 0x06), 0x00000F8F, DCT0_MASK, ANY_DIMM_MASK}, - {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_EXTRA_FLAG, 0, 0x16), 0x0000000F, DCT0_MASK, ANY_DIMM_MASK}, - {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_EXTRA_FLAG, 0, 0x40), 0x3F1F0F0F, DCT0_MASK, ANY_DIMM_MASK}, - {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_EXTRA_FLAG, 0, 0x41), 0x00070707, DCT0_MASK, ANY_DIMM_MASK}, - {{0, 2, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_EXTRA_FLAG, 0, 0x83), 0x00007177, DCT0_MASK, ANY_DIMM_MASK}, - {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_EXTRA_FLAG, 0, 0x180), 0x0F0F0F0F, DCT0_MASK, ANY_DIMM_MASK}, - {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_EXTRA_FLAG, 0, 0x182), 0x0F0F0F0F, DCT0_MASK, ANY_DIMM_MASK}, - {{0, 2, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_EXTRA_FLAG, 0, 0x200), 0x00001F0F, DCT0_MASK, ANY_DIMM_MASK}, - - // DCT 1 - {{0, 0, 0}, FUNC_2, 0x140, 0x1FF83FED, DCT1_MASK, DCT1_ANY_DIMM_MASK}, - {{0, 0, 0}, FUNC_2, 0x144, 0x1FF83FED, DCT1_MASK, DCT1_ANY_DIMM_MASK}, - {{0, 0, 0}, FUNC_2, 0x148, 0x1FF83FED, DCT1_MASK, DCT1_ANY_DIMM_MASK}, - {{0, 0, 0}, FUNC_2, 0x14C, 0x1FF83FED, DCT1_MASK, DCT1_ANY_DIMM_MASK}, - {{0, 0, 0}, FUNC_2, 0x160, 0x1FF83FE0, DCT1_MASK, DCT1_ANY_DIMM_MASK}, - {{0, 0, 0}, FUNC_2, 0x164, 0x1FF83FE0, DCT1_MASK, DCT1_ANY_DIMM_MASK}, - {{0, 1, 0}, FUNC_2, 0x180, 0x000000FF, DCT1_MASK, DCT1_ANY_DIMM_MASK}, - {{0, 0, 0}, FUNC_2, 0x184, 0x00FC2FFF, DCT1_MASK, DCT1_ANY_DIMM_MASK}, - {{0, 0, 0}, FUNC_2, 0x188, 0xFF00000F, DCT1_MASK, DCT1_ANY_DIMM_MASK}, - {{0, 0, 0}, FUNC_2, 0x18C, 0x03F7FCFF, DCT1_MASK, DCT1_ANY_DIMM_MASK}, - {{0, 0, 0}, FUNC_2, 0x190, 0x0EF20003, DCT1_MASK, DCT1_ANY_DIMM_MASK}, - {{0, 0, 0}, FUNC_2, 0x1A8, 0x0078FF1F, DCT1_MASK, DCT1_ANY_DIMM_MASK}, - {{0, 2, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_EXTRA_FLAG, 1, 0x06), 0x00000F8F, DCT1_MASK, ANY_DIMM_MASK}, - {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_EXTRA_FLAG, 1, 0x16), 0x0000000F, DCT1_MASK, ANY_DIMM_MASK}, - {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_EXTRA_FLAG, 1, 0x40), 0x3F1F0F0F, DCT1_MASK, ANY_DIMM_MASK}, - {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_EXTRA_FLAG, 1, 0x41), 0x00070707, DCT1_MASK, ANY_DIMM_MASK}, - {{0, 2, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_EXTRA_FLAG, 1, 0x83), 0x00007177, DCT1_MASK, ANY_DIMM_MASK}, - {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_EXTRA_FLAG, 1, 0x180), 0x0F0F0F0F, DCT1_MASK, ANY_DIMM_MASK}, - {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_EXTRA_FLAG, 1, 0x182), 0x0F0F0F0F, DCT1_MASK, ANY_DIMM_MASK}, - {{0, 2, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_EXTRA_FLAG, 1, 0x200), 0x00001F0F, DCT1_MASK, ANY_DIMM_MASK}, - - // DCT 0 - // Phy Initialization - {{6, 3, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x0B), 0, DCT0_MASK + DCT1_MASK, ANY_DIMM_MASK}, - {{1, 2, 1}, DCT0, BFPllRegWaitTime, 0, DCT0_MASK, ANY_DIMM_MASK}, - // 3. Phy voltage related - {{1, 1, 1}, DCT0, BFDataRxVioLvl, 0x00000018, DCT0_MASK, ANY_DIMM_MASK}, - {{1, 1, 1}, DCT0, BFClkRxVioLvl, 0x00000018, DCT0_MASK, ANY_DIMM_MASK}, - {{1, 2, 1}, DCT0, BFCmpVioLvl, 0x0000C000, DCT0_MASK, ANY_DIMM_MASK}, - {{1, 1, 1}, DCT0, BFCmdRxVioLvl, 0x00000018, DCT0_MASK, ANY_DIMM_MASK}, - {{1, 1, 1}, DCT0, BFCsrComparator, 0x0000000C, DCT0_MASK, ANY_DIMM_MASK}, - {{1, 1, 1}, DCT0, BFAddrRxVioLvl, 0x00000018, DCT0_MASK, ANY_DIMM_MASK}, - // DCT 1 - // Phy Initialization - {{6, 3, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x0B), 0, DCT0_MASK + DCT1_MASK, ANY_DIMM_MASK}, - {{1, 2, 1}, DCT1, BFPllRegWaitTime, 0, DCT1_MASK, ANY_DIMM_MASK}, - // 3. Phy voltage related - {{1, 1, 1}, DCT1, BFDataRxVioLvl, 0x00000018, DCT1_MASK, ANY_DIMM_MASK}, - {{1, 1, 1}, DCT1, BFClkRxVioLvl, 0x00000018, DCT1_MASK, ANY_DIMM_MASK}, - {{1, 2, 1}, DCT1, BFCmpVioLvl, 0x0000C000, DCT1_MASK, ANY_DIMM_MASK}, - {{1, 1, 1}, DCT1, BFCmdRxVioLvl, 0x00000018, DCT1_MASK, ANY_DIMM_MASK}, - {{1, 1, 1}, DCT1, BFAddrRxVioLvl, 0x00000018, DCT1_MASK, ANY_DIMM_MASK}, - - // 4. Frequency Change - // Check if a channel needs to be disabled - {{1, 1, 1}, DCT0, BFCKETri, 0, DCT0_MASK + DCT1_MASK, ANY_DIMM_MASK}, - {{7, 3, 1}, DCT0, 0, 0, DCT0_MASK + DCT1_MASK, ANY_DIMM_MASK}, - {{1, 1, 1}, DCT1, BFCKETri, 0, DCT0_MASK + DCT1_MASK, ANY_DIMM_MASK}, - {{7, 3, 1}, DCT1, 0, 0, DCT0_MASK + DCT1_MASK, ANY_DIMM_MASK}, - - {{4, 3, 1}, DCT0, BFPllLockTime, 0, DCT0_MASK, ANY_DIMM_MASK}, - {{4, 3, 1}, DCT1, BFPllLockTime, 0, DCT1_MASK, ANY_DIMM_MASK}, - {{0, 0, 0}, FUNC_2, 0x94, 0xFFD1CC1F, DCT0_MASK, ANY_DIMM_MASK}, - {{0, 0, 0}, FUNC_2, 0x194, 0xFFD1CC1F, DCT1_MASK, ANY_DIMM_MASK}, - - // NB Pstate Related Register for Pstate 0 - {{0, 0, 0}, FUNC_2, 0x78, 0xFFF67FCF, DCT0_MASK, DCT0_ANY_DIMM_MASK}, - {{0, 0, 0}, FUNC_2, 0x178, 0xFFF67FCF, DCT1_MASK, DCT1_ANY_DIMM_MASK}, - {{0, 2, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_EXTRA_FLAG, 0, 0x30), 0x00001FFF, DCT0_MASK, ANY_DIMM_MASK}, - {{0, 2, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_EXTRA_FLAG, 0, 0x31), 0x00001FFF, DCT0_MASK, ANY_DIMM_MASK}, - {{0, 2, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_EXTRA_FLAG, 0, 0x32), 0x00009F9F, DCT0_MASK, ANY_DIMM_MASK}, - {{0, 2, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_EXTRA_FLAG, 1, 0x30), 0x00001FFF, DCT1_MASK, ANY_DIMM_MASK}, - {{0, 2, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_EXTRA_FLAG, 1, 0x31), 0x00001FFF, DCT1_MASK, ANY_DIMM_MASK}, - {{0, 2, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_EXTRA_FLAG, 1, 0x32), 0x00009F9F, DCT1_MASK, ANY_DIMM_MASK}, - - // Access NB Pstate 1 - {{3, 3, 1}, FUNC_6, 0x98, 0, DCT0_NBPSTATE_SUPPORT_MASK + DCT1_NBPSTATE_SUPPORT_MASK, ANY_DIMM_MASK}, - // NB Pstate Related Register for Pstate 1 - {{0, 0, 0}, FUNC_2, 0x78, 0xFFF67FCF, DCT0_NBPSTATE_SUPPORT_MASK, DCT0_ANY_DIMM_MASK}, - {{0, 0, 0}, FUNC_2, 0x178, 0xFFF67FCF, DCT1_NBPSTATE_SUPPORT_MASK, DCT1_ANY_DIMM_MASK}, - {{0, 2, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_EXTRA_FLAG, 0, 0x30), 0x00001FFF, DCT0_NBPSTATE_SUPPORT_MASK, ANY_DIMM_MASK}, - {{0, 2, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_EXTRA_FLAG, 0, 0x31), 0x00001FFF, DCT0_NBPSTATE_SUPPORT_MASK, ANY_DIMM_MASK}, - {{0, 2, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_EXTRA_FLAG, 0, 0x32), 0x00009F9F, DCT0_NBPSTATE_SUPPORT_MASK, ANY_DIMM_MASK}, - {{0, 2, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_EXTRA_FLAG, 1, 0x30), 0x00001FFF, DCT1_NBPSTATE_SUPPORT_MASK, ANY_DIMM_MASK}, - {{0, 2, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_EXTRA_FLAG, 1, 0x31), 0x00001FFF, DCT1_NBPSTATE_SUPPORT_MASK, ANY_DIMM_MASK}, - {{0, 2, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_EXTRA_FLAG, 1, 0x32), 0x00009F9F, DCT1_NBPSTATE_SUPPORT_MASK, ANY_DIMM_MASK}, - // Disable Access to NB Pstate 1 - {{2, 3, 1}, FUNC_6, 0x98, 0, DCT0_NBPSTATE_SUPPORT_MASK + DCT1_NBPSTATE_SUPPORT_MASK, ANY_DIMM_MASK}, - - {{1, 2, 1}, DCT0, BFProcOdtAdv, 0x00004000, DCT0_MASK, ANY_DIMM_MASK}, - {{1, 2, 1}, DCT1, BFProcOdtAdv, 0x00004000, DCT1_MASK, ANY_DIMM_MASK}, - {{1, 1, 1}, DCT0, BFMemClkFreqVal, 0, DCT0_MASK, ANY_DIMM_MASK}, - {{1, 1, 1}, DCT1, BFMemClkFreqVal, 0, DCT1_MASK, ANY_DIMM_MASK}, - {{8, 0, 1}, DCT0, BFDramPhyCtlReg, 0x0FBF8000, DCT0_MASK, ANY_DIMM_MASK}, - {{8, 0, 1}, DCT1, BFDramPhyCtlReg, 0x0FBF8000, DCT1_MASK, ANY_DIMM_MASK}, - {{1, 2, 1}, DCT0, BFPllLockTime, 0, DCT0_MASK, ANY_DIMM_MASK}, - {{1, 2, 1}, DCT1, BFPllLockTime, 0, DCT1_MASK, ANY_DIMM_MASK}, - - // DCT 0 - // 5. Phy Fence - {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x0C), 0x7FFF0FFF, DCT0_MASK + DCT1_MASK, ANY_DIMM_MASK}, - {{1, 2, 1}, DCT0, BFDataFence2, 0x00007FFF, DCT0_MASK, ANY_DIMM_MASK}, - {{1, 1, 1}, DCT0, BFClkFence2, 0x0000001F, DCT0_MASK, ANY_DIMM_MASK}, - {{1, 1, 1}, DCT0, BFCmdFence2, 0x0000001F, DCT0_MASK, ANY_DIMM_MASK}, - {{1, 1, 1}, DCT0, BFAddrFence2, 0x0000001F, DCT0_MASK, ANY_DIMM_MASK}, - {{10, 2, 1}, DCT0, BFPhyClkDllFine0, 0x0000409F, DCT0_MASK, ANY_DIMM_MASK}, - {{10, 2, 1}, DCT0, BFPhyClkDllFine1, 0x0000409F, DCT0_MASK, ANY_DIMM_MASK}, - {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x00), 0x70777777, DCT0_MASK, ANY_DIMM_MASK}, - {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x04), 0x003F3F3F, DCT0_MASK, ANY_DIMM_MASK}, - // 6. Phy Compensation Init - {{5, 3, 1}, DCT0, BFDisablePredriverCal, 0, DCT0_MASK + DCT1_MASK, ANY_DIMM_MASK}, - {{1, 2, 1}, DCT0, BFDataByteTxPreDriverCal2Pad1, 0, DCT0_MASK, ANY_DIMM_MASK}, - {{1, 2, 1}, DCT0, BFDataByteTxPreDriverCal2Pad2, 0, DCT0_MASK, ANY_DIMM_MASK}, - {{9, 2, 1}, DCT0, BFDataByteTxPreDriverCal, 0, DCT0_MASK, ANY_DIMM_MASK}, - {{1, 2, 1}, DCT0, BFCmdAddr0TxPreDriverCal2Pad1, 0, DCT0_MASK, ANY_DIMM_MASK}, - {{1, 2, 1}, DCT0, BFCmdAddr0TxPreDriverCal2Pad2, 0, DCT0_MASK, ANY_DIMM_MASK}, - {{1, 2, 1}, DCT0, BFCmdAddr1TxPreDriverCal2Pad1, 0, DCT0_MASK, ANY_DIMM_MASK}, - {{1, 2, 1}, DCT0, BFCmdAddr1TxPreDriverCal2Pad2, 0, DCT0_MASK, ANY_DIMM_MASK}, - {{1, 2, 1}, DCT0, BFAddrTxPreDriverCal2Pad1, 0, DCT0_MASK, ANY_DIMM_MASK}, - {{1, 2, 1}, DCT0, BFAddrTxPreDriverCal2Pad2, 0, DCT0_MASK, ANY_DIMM_MASK}, - {{1, 2, 1}, DCT0, BFAddrTxPreDriverCal2Pad3, 0, DCT0_MASK, ANY_DIMM_MASK}, - {{1, 2, 1}, DCT0, BFAddrTxPreDriverCal2Pad4, 0, DCT0_MASK, ANY_DIMM_MASK}, - {{9, 2, 1}, DCT0, BFCmdAddr0TxPreDriverCalPad0, 0, DCT0_MASK, ANY_DIMM_MASK}, - {{9, 2, 1}, DCT0, BFCmdAddr1TxPreDriverCalPad0, 0, DCT0_MASK, ANY_DIMM_MASK}, - {{9, 2, 1}, DCT0, BFAddrTxPreDriverCalPad0, 0, DCT0_MASK, ANY_DIMM_MASK}, - {{9, 2, 1}, DCT0, BFClock0TxPreDriverCalPad0, 0, DCT0_MASK, ANY_DIMM_MASK}, - {{9, 2, 1}, DCT0, BFClock1TxPreDriverCalPad0, 0, DCT0_MASK, ANY_DIMM_MASK}, - // DCT 1 - // 5. Phy Fence - {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x0C), 0x7FFF0FFF, DCT1_MASK, ANY_DIMM_MASK}, - {{1, 2, 1}, DCT1, BFDataFence2, 0x00007FFF, DCT1_MASK, ANY_DIMM_MASK}, - {{1, 1, 1}, DCT1, BFClkFence2, 0x0000001F, DCT1_MASK, ANY_DIMM_MASK}, - {{1, 1, 1}, DCT1, BFCmdFence2, 0x0000001F, DCT1_MASK, ANY_DIMM_MASK}, - {{1, 1, 1}, DCT1, BFAddrFence2, 0x0000001F, DCT1_MASK, ANY_DIMM_MASK}, - {{10, 2, 1}, DCT1, BFPhyClkDllFine0, 0x0000409F, DCT1_MASK, ANY_DIMM_MASK}, - {{10, 2, 1}, DCT1, BFPhyClkDllFine1, 0x0000409F, DCT1_MASK, ANY_DIMM_MASK}, - {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x00), 0x70777777, DCT1_MASK, ANY_DIMM_MASK}, - {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x04), 0x003F3F3F, DCT1_MASK, ANY_DIMM_MASK}, - // 6. Phy Compensation Init - {{1, 2, 1}, DCT1, BFDataByteTxPreDriverCal2Pad1, 0, DCT1_MASK, ANY_DIMM_MASK}, - {{1, 2, 1}, DCT1, BFDataByteTxPreDriverCal2Pad2, 0, DCT1_MASK, ANY_DIMM_MASK}, - {{9, 2, 1}, DCT1, BFDataByteTxPreDriverCal, 0, DCT1_MASK, ANY_DIMM_MASK}, - {{1, 2, 1}, DCT1, BFCmdAddr0TxPreDriverCal2Pad1, 0, DCT1_MASK, ANY_DIMM_MASK}, - {{1, 2, 1}, DCT1, BFCmdAddr0TxPreDriverCal2Pad2, 0, DCT1_MASK, ANY_DIMM_MASK}, - {{1, 2, 1}, DCT1, BFCmdAddr1TxPreDriverCal2Pad1, 0, DCT1_MASK, ANY_DIMM_MASK}, - {{1, 2, 1}, DCT1, BFCmdAddr1TxPreDriverCal2Pad2, 0, DCT1_MASK, ANY_DIMM_MASK}, - {{1, 2, 1}, DCT1, BFAddrTxPreDriverCal2Pad1, 0, DCT1_MASK, ANY_DIMM_MASK}, - {{1, 2, 1}, DCT1, BFAddrTxPreDriverCal2Pad2, 0, DCT1_MASK, ANY_DIMM_MASK}, - {{1, 2, 1}, DCT1, BFAddrTxPreDriverCal2Pad3, 0, DCT1_MASK, ANY_DIMM_MASK}, - {{1, 2, 1}, DCT1, BFAddrTxPreDriverCal2Pad4, 0, DCT1_MASK, ANY_DIMM_MASK}, - {{9, 2, 1}, DCT1, BFCmdAddr0TxPreDriverCalPad0, 0, DCT1_MASK, ANY_DIMM_MASK}, - {{9, 2, 1}, DCT1, BFCmdAddr1TxPreDriverCalPad0, 0, DCT1_MASK, ANY_DIMM_MASK}, - {{9, 2, 1}, DCT1, BFAddrTxPreDriverCalPad0, 0, DCT1_MASK, ANY_DIMM_MASK}, - {{9, 2, 1}, DCT1, BFClock0TxPreDriverCalPad0, 0, DCT1_MASK, ANY_DIMM_MASK}, - {{9, 2, 1}, DCT1, BFClock1TxPreDriverCalPad0, 0, DCT1_MASK, ANY_DIMM_MASK}, - - {{1, 2, 1}, DCT0, BFDisablePredriverCal, 0x00006000, DCT0_MASK + DCT1_MASK, ANY_DIMM_MASK} -}; - -CONST CPCI_REGISTER_BLOCK_HEADER ROMDATA S3CPciPreSelfRefLN = { - 0, - (sizeof (S3CPciPreSelfDescriptorLN) / sizeof (CONDITIONAL_PCI_REG_DESCRIPTOR)), - S3CPciPreSelfDescriptorLN, - PciSpecialCaseFuncLN -}; - -CONDITIONAL_PCI_REG_DESCRIPTOR ROMDATA S3CPciPostSelfDescriptorLN[] = { - // DCT0 - {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x10), 0x01FF01FF, DCT0_MASK, 0x01}, - {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x11), 0x01FF01FF, DCT0_MASK, 0x01}, - {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x13), 0x01FF01FF, DCT0_MASK, 0x04}, - {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x14), 0x01FF01FF, DCT0_MASK, 0x04}, - {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x20), 0x01FF01FF, DCT0_MASK, 0x01}, - {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x21), 0x01FF01FF, DCT0_MASK, 0x01}, - {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x23), 0x01FF01FF, DCT0_MASK, 0x04}, - {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x24), 0x01FF01FF, DCT0_MASK, 0x04}, - {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x01), 0xFFFFFFFF, DCT0_MASK, 0x01}, - {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x02), 0xFFFFFFFF, DCT0_MASK, 0x01}, - {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x101), 0xFFFFFFFF, DCT0_MASK, 0x04}, - {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x102), 0xFFFFFFFF, DCT0_MASK, 0x04}, - {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x05), 0x3E3E3E3E, DCT0_MASK, 0x01}, - {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x06), 0x3E3E3E3E, DCT0_MASK, 0x01}, - {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x105), 0x3E3E3E3E, DCT0_MASK, 0x04}, - {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x106), 0x3E3E3E3E, DCT0_MASK, 0x04}, - {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x30), 0x00FF00FF, DCT0_DDR3_MASK, 0x01}, - {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x31), 0x00FF00FF, DCT0_DDR3_MASK, 0x01}, - {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x33), 0x00FF00FF, DCT0_DDR3_MASK, 0x04}, - {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x34), 0x00FF00FF, DCT0_DDR3_MASK, 0x04}, - {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x40), 0x00FF00FF, DCT0_DDR3_MASK, 0x01}, - {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x41), 0x00FF00FF, DCT0_DDR3_MASK, 0x01}, - {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x43), 0x00FF00FF, DCT0_DDR3_MASK, 0x04}, - {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x44), 0x00FF00FF, DCT0_DDR3_MASK, 0x04}, - {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x0D), 0x037F037F, DCT0_MASK, ANY_DIMM_MASK}, - {{1, 1, 1}, DCT0, BFPhyClkConfig0, 0x00000010, DCT0_MASK, ANY_DIMM_MASK}, - {{1, 1, 1}, DCT0, BFPhyClkConfig1, 0x00000010, DCT0_MASK, ANY_DIMM_MASK}, - {{1, 1, 1}, DCT0, BFPhy0x0D0F0F13Bit0to7, 0x00000083, DCT0_MASK, ANY_DIMM_MASK}, - {{1, 1, 1}, DCT0, BFAddrCmdTri, 0x0000000B1, DCT0_MASK, ANY_DIMM_MASK}, - {{1, 2, 1}, DCT0, BFLowPowerDrvStrengthEn, 0x00000100, DCT0_MASK, ANY_DIMM_MASK}, - {{1, 2, 1}, DCT0, BFEnRxPadStandby, 0x000001000, DCT0_MASK, ANY_DIMM_MASK}, - {{1, 2, 1}, DCT0, BFPhy0x0D0FE00A, 0x000007010, DCT0_MASK, ANY_DIMM_MASK}, - {{1, 1, 1}, DCT0, BFDisDllShutdownSR, 0x00000001, DCT0_MASK, ANY_DIMM_MASK}, - - // DCT1 - {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x10), 0x01FF01FF, DCT1_MASK, 0x02}, - {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x11), 0x01FF01FF, DCT1_MASK, 0x02}, - {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x13), 0x01FF01FF, DCT1_MASK, 0x08}, - {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x14), 0x01FF01FF, DCT1_MASK, 0x08}, - {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x20), 0x01FF01FF, DCT1_MASK, 0x02}, - {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x21), 0x01FF01FF, DCT1_MASK, 0x02}, - {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x23), 0x01FF01FF, DCT1_MASK, 0x08}, - {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x24), 0x01FF01FF, DCT1_MASK, 0x08}, - {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x01), 0xFFFFFFFF, DCT1_MASK, 0x02}, - {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x02), 0xFFFFFFFF, DCT1_MASK, 0x02}, - {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x101), 0xFFFFFFFF, DCT1_MASK, 0x08}, - {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x102), 0xFFFFFFFF, DCT1_MASK, 0x08}, - {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x05), 0x3E3E3E3E, DCT1_MASK, 0x02}, - {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x06), 0x3E3E3E3E, DCT1_MASK, 0x02}, - {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x105), 0x3E3E3E3E, DCT1_MASK, 0x08}, - {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x106), 0x3E3E3E3E, DCT1_MASK, 0x08}, - {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x30), 0x00FF00FF, DCT1_DDR3_MASK, 0x02}, - {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x31), 0x00FF00FF, DCT1_DDR3_MASK, 0x02}, - {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x33), 0x00FF00FF, DCT1_DDR3_MASK, 0x08}, - {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x34), 0x00FF00FF, DCT1_DDR3_MASK, 0x08}, - {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x40), 0x00FF00FF, DCT1_DDR3_MASK, 0x02}, - {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x41), 0x00FF00FF, DCT1_DDR3_MASK, 0x02}, - {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x43), 0x00FF00FF, DCT1_DDR3_MASK, 0x08}, - {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x44), 0x00FF00FF, DCT1_DDR3_MASK, 0x08}, - {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x0D), 0x037F037F, DCT1_MASK, ANY_DIMM_MASK}, - {{1, 1, 1}, DCT1, BFPhyClkConfig0, 0x00000017, DCT1_MASK, ANY_DIMM_MASK}, - {{1, 1, 1}, DCT1, BFPhyClkConfig1, 0x00000017, DCT1_MASK, ANY_DIMM_MASK}, - {{1, 1, 1}, DCT1, BFPhy0x0D0F0F13Bit0to7, 0x00000083, DCT1_MASK, ANY_DIMM_MASK}, - {{1, 1, 1}, DCT1, BFAddrCmdTri, 0x0000000B1, DCT1_MASK, ANY_DIMM_MASK}, - {{1, 2, 1}, DCT1, BFLowPowerDrvStrengthEn, 0x00000100, DCT1_MASK, ANY_DIMM_MASK}, - {{1, 2, 1}, DCT1, BFEnRxPadStandby, 0x000001000, DCT1_MASK, ANY_DIMM_MASK}, - {{1, 2, 1}, DCT1, BFPhy0x0D0FE00A, 0x000007010, DCT1_MASK, ANY_DIMM_MASK}, - {{1, 1, 1}, DCT1, BFDisDllShutdownSR, 0x00000001, DCT1_MASK, ANY_DIMM_MASK}, - - {{0, 0, 0}, FUNC_2, 0x1C0, 0x100000, ANY_DIMM_MASK, ANY_DIMM_MASK}, - {{0, 0, 0}, FUNC_3, 0x84, 0x00060006, ANY_DIMM_MASK, ANY_DIMM_MASK}, - {{0, 2, 0}, FUNC_4, 0x12C, 0x0000FFFF, ANY_DIMM_MASK, ANY_DIMM_MASK}, - {{0, 0, 0}, FUNC_4, 0x1A8, 0x3F000000, ANY_DIMM_MASK, ANY_DIMM_MASK}, - {{0, 0, 0}, FUNC_3, 0x188, 0x00400000, ANY_DIMM_MASK, ANY_DIMM_MASK}, - {{0, 2, 0}, FUNC_6, 0x78, 0x0000FF00, ANY_DIMM_MASK, ANY_DIMM_MASK}, - {{0, 2, 0}, FUNC_6, 0x9C, 0x00000100, ANY_DIMM_MASK, ANY_DIMM_MASK}, - // Release NB P-state force - {{0, 0, 0}, FUNC_6, 0x90, 0x50000000, ANY_DIMM_MASK, ANY_DIMM_MASK}, - {{0, 0, 0}, FUNC_2, 0x118, 0x00080000, ANY_DIMM_MASK, ANY_DIMM_MASK}, -}; - -CONST CPCI_REGISTER_BLOCK_HEADER ROMDATA S3CPciPostSelfRefLN = { - 0, - (sizeof (S3CPciPostSelfDescriptorLN) / sizeof (CONDITIONAL_PCI_REG_DESCRIPTOR)), - S3CPciPostSelfDescriptorLN, - PciSpecialCaseFuncLN -}; - -MSR_REG_DESCRIPTOR ROMDATA S3MSRPreSelfRefDescriptorLN[] = { - {{0, 0, 0}, 0xC0010010, 0x00000000007F0700ull}, - {{0, 0, 0}, 0xC001001A, 0x000000FFFF800000ull}, - {{0, 0, 0}, 0xC001001D, 0x000000FFFF800000ull}, - {{0, 0, 0}, 0xC001001F, 0x8480FC6A434243E0ull} -}; - -CONST MSR_REGISTER_BLOCK_HEADER ROMDATA S3MSRPreSelfRefLN = { - 0, - (sizeof (S3MSRPreSelfRefDescriptorLN) / sizeof (MSR_REG_DESCRIPTOR)), - S3MSRPreSelfRefDescriptorLN, - NULL -}; - -VOID *MemS3RegListLN[] = { - (VOID *)&S3PciPreSelfRefLN, - NULL, - (VOID *)&S3CPciPreSelfRefLN, - (VOID *)&S3CPciPostSelfRefLN, - (VOID *)&S3MSRPreSelfRefLN, - NULL, - NULL, - NULL -}; - -/*---------------------------------------------------------------------------- - * EXPORTED FUNCTIONS - * - *---------------------------------------------------------------------------- - */ -/* -----------------------------------------------------------------------------*/ -/** - * - * - * This function initializes the northbridge block for S3 resume - * - * @param[in,out] *S3NBPtr - Pointer to MEM_NB_BLOCK. - * @param[in,out] *MemPtr - Pointer to MEM_DATA_STRUCT. - * @param[in] NodeID - Node ID of the target node. - * - * @return BOOLEAN - * TRUE - This is the correct constructor for the targeted node. - * FALSE - This isn't the correct constructor for the targeted node. - */ -BOOLEAN -MemS3ResumeConstructNBBlockLN ( - IN OUT VOID *S3NBPtr, - IN OUT MEM_DATA_STRUCT *MemPtr, - IN UINT8 NodeID - ) -{ - INT32 i; - MEM_NB_BLOCK *NBPtr; - - NBPtr = ((S3_MEM_NB_BLOCK *)S3NBPtr)->NBPtr; - - // - // Determine if this is the expected NB Type - // - GetLogicalIdOfSocket (MemPtr->DiesPerSystem[NodeID].SocketId, &(MemPtr->DiesPerSystem[NodeID].LogicalCpuid), &(MemPtr->StdHeader)); - if (!MemNIsIdSupportedLN (NBPtr, &(MemPtr->DiesPerSystem[NodeID].LogicalCpuid))) { - return FALSE; - } - - NBPtr->MemPtr = MemPtr; - NBPtr->MCTPtr = &(MemPtr->DiesPerSystem[NodeID]); - NBPtr->PciAddr.AddressValue = MemPtr->DiesPerSystem[NodeID].PciAddr.AddressValue; - MemNInitNBRegTableLN (NBPtr, NBPtr->NBRegTable); - NBPtr->Node = ((UINT8) NBPtr->PciAddr.Address.Device) - 24; - NBPtr->Dct = 0; - NBPtr->Channel = 0; - NBPtr->Ganged = FALSE; - NBPtr->NodeCount = MAX_NODES_SUPPORTED_LN; - NBPtr->DctCount = MAX_DCTS_PER_NODE_LN; - - for (i = 0; i < EnumSize; i++) { - NBPtr->IsSupported[i] = FALSE; - } - - for (i = 0; i < NumberOfHooks; i++) { - NBPtr->FamilySpecificHook[i] = (BOOLEAN (*) (MEM_NB_BLOCK *, VOID *)) memDefTrue; - } - - LibAmdMemFill (NBPtr->DctCache, 0, sizeof (NBPtr->DctCache), &MemPtr->StdHeader); - - NBPtr->SwitchDCT = MemNSwitchDCTNb; - NBPtr->SwitchChannel = MemNSwitchChannelNb; - NBPtr->MemNCmnGetSetFieldNb = MemNCmnGetSetFieldLN; - NBPtr->GetBitField = MemNGetBitFieldNb; - NBPtr->SetBitField = MemNSetBitFieldNb; - NBPtr->MemNIsIdSupportedNb = MemNIsIdSupportedLN; - NBPtr->ChangeNbFrequencyWrap = MemNS3ChangeNbFrequencyWrapLN; - ((S3_MEM_NB_BLOCK *)S3NBPtr)->MemS3ExitSelfRefReg = (VOID (*) (MEM_NB_BLOCK *, AMD_CONFIG_PARAMS *)) memDefRet; - ((S3_MEM_NB_BLOCK *)S3NBPtr)->MemS3GetConPCIMask = MemNS3GetConPCIMaskLN; - ((S3_MEM_NB_BLOCK *)S3NBPtr)->MemS3GetConMSRMask = (VOID (*) (MEM_NB_BLOCK *, DESCRIPTOR_GROUP *)) memDefRet; - ((S3_MEM_NB_BLOCK *)S3NBPtr)->MemS3Resume = MemNS3ResumeClientNb; - ((S3_MEM_NB_BLOCK *)S3NBPtr)->MemS3RestoreScrub = (VOID (*) (MEM_NB_BLOCK *, UINT8)) memDefRet; - ((S3_MEM_NB_BLOCK *)S3NBPtr)->MemS3GetRegLstPtr = MemNS3GetRegLstPtrLN; - ((S3_MEM_NB_BLOCK *)S3NBPtr)->MemS3GetDeviceRegLst = MemNS3GetDeviceRegLstLN; - ((S3_MEM_NB_BLOCK *)S3NBPtr)->MemS3SpecialCaseHeapSize = 0; - - MemNSwitchDCTNb (NBPtr, 0); - - return TRUE; -} - -/*---------------------------------------------------------------------------- - * LOCAL FUNCTIONS - * - *----------------------------------------------------------------------------*/ -/* -----------------------------------------------------------------------------*/ -/** - * - * - * This function returns the conditional PCI device mask - * - * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK - * @param[in, out] *DescriptPtr - Pointer to DESCRIPTOR_GROUP - * @return none - */ -VOID -STATIC -MemNS3GetConPCIMaskLN ( - IN OUT MEM_NB_BLOCK *NBPtr, - IN OUT DESCRIPTOR_GROUP *DescriptPtr - ) -{ - BIT_FIELD_NAME bitfield; - UINT32 RegVal; - UINT8 DCT; - UINT8 DimmMask; - UINT8 BadDimmMask; - UINT8 NbPsCap; - - DimmMask = 0; - BadDimmMask = 0; - for (DCT = 0; DCT < MAX_DCTS_PER_NODE_LN; DCT ++) { - MemNSwitchDCTNb (NBPtr, DCT); - if (MemNGetBitFieldNb (NBPtr, BFMemClkFreqVal)) { - for (bitfield = BFCSBaseAddr0Reg; bitfield <= BFCSBaseAddr3Reg; bitfield ++) { - RegVal = MemNGetBitFieldNb (NBPtr, bitfield); - if (RegVal & 0x1) { - DimmMask |= (UINT8) (1 << ((((bitfield - BFCSBaseAddr0Reg) >> 1) << 1) + DCT)); - } else if (RegVal & 0x4) { - BadDimmMask |= (UINT8) (1 << ((((bitfield - BFCSBaseAddr0Reg) >> 1) << 1) + DCT)); - } - } - } - } - // Check if the system is capable of doing NB Pstate transition - NbPsCap = (UINT8) MemNGetBitFieldNb (NBPtr, BFNbPsCap); - - MemNSwitchDCTNb (NBPtr, 0); - // Set channel mask - DescriptPtr->CPCIDevice[PRESELFREF].Mask1 = 0; - DescriptPtr->CPCIDevice[POSTSELFREF].Mask1 = 0; - for (DCT = 0; DCT < MAX_DCTS_PER_NODE_LN; DCT ++) { - if (DimmMask & (0x5 << DCT)) { - // Set mask before exit self refresh - DescriptPtr->CPCIDevice[PRESELFREF].Mask1 |= ((NbPsCap == 1) ? 5 : 1) << DCT; - // Set mask after exit self refresh - DescriptPtr->CPCIDevice[POSTSELFREF].Mask1 |= 1 << DCT; - // Set DDR3 mask if Dimms present are DDR3 - DescriptPtr->CPCIDevice[POSTSELFREF].Mask1 |= (DescriptPtr->CPCIDevice[POSTSELFREF].Mask1 << 4); - } else if (BadDimmMask & (0x5 << DCT)) { - // Need to save function 2 registers for bad dimm - DescriptPtr->CPCIDevice[PRESELFREF].Mask1 |= 1 << DCT; - } - } - - // Set dimm mask - DescriptPtr->CPCIDevice[PRESELFREF].Mask2 = DimmMask; - DescriptPtr->CPCIDevice[POSTSELFREF].Mask2 = DimmMask; -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * - * This function returns the register list for each device for LN - * - * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK - * @param[in, out] *DescriptPtr - Pointer to DESCRIPTOR_GROUP - * @return UINT16 - size of the device descriptor on the target node. - */ -UINT16 -STATIC -MemNS3GetRegLstPtrLN ( - IN OUT MEM_NB_BLOCK *NBPtr, - IN OUT DESCRIPTOR_GROUP *DescriptPtr - ) -{ - UINT8 i; - UINT16 Size; - Size = 0; - for (i = PRESELFREF; i <= POSTSELFREF; i ++) { - DescriptPtr->PCIDevice[i].Type = (UINT8) (DEV_TYPE_PCI_PRE_ESR + i); - DescriptPtr->PCIDevice[i].Node = NBPtr->Node; - DescriptPtr->PCIDevice[i].RegisterListID = 0xFFFFFFFF; - if ((PCI_REGISTER_BLOCK_HEADER *) MemS3RegListLN[PCI_LST_ESR_LN - PCI_LST_ESR_LN + i] != NULL) { - DescriptPtr->PCIDevice[i].RegisterListID = PCI_LST_ESR_LN + i; - Size += sizeof (PCI_DEVICE_DESCRIPTOR); - } - DescriptPtr->CPCIDevice[i].Type = (UINT8) (DEV_TYPE_CPCI_PRE_ESR + i); - DescriptPtr->CPCIDevice[i].Node = NBPtr->Node; - DescriptPtr->CPCIDevice[i].RegisterListID = 0xFFFFFFFF; - if ((CPCI_REGISTER_BLOCK_HEADER *) MemS3RegListLN[CPCI_LST_ESR_LN - PCI_LST_ESR_LN + i] != NULL) { - DescriptPtr->CPCIDevice[i].RegisterListID = CPCI_LST_ESR_LN + i; - Size += sizeof (CONDITIONAL_PCI_DEVICE_DESCRIPTOR); - } - DescriptPtr->MSRDevice[i].Type = (UINT8) (DEV_TYPE_MSR_PRE_ESR + i); - DescriptPtr->MSRDevice[i].RegisterListID = 0xFFFFFFFF; - if ((MSR_REGISTER_BLOCK_HEADER *) MemS3RegListLN[MSR_LST_ESR_LN - PCI_LST_ESR_LN + i] != NULL) { - DescriptPtr->MSRDevice[i].RegisterListID = MSR_LST_ESR_LN + i; - Size += sizeof (MSR_DEVICE_DESCRIPTOR); - } - DescriptPtr->CMSRDevice[i].Type = (UINT8) (DEV_TYPE_CMSR_PRE_ESR + i); - DescriptPtr->CMSRDevice[i].RegisterListID = 0xFFFFFFFF; - if ((CMSR_REGISTER_BLOCK_HEADER *) MemS3RegListLN[CMSR_LST_ESR_LN - PCI_LST_ESR_LN + i] != NULL) { - DescriptPtr->CMSRDevice[i].RegisterListID = CMSR_LST_ESR_LN + i; - Size += sizeof (CONDITIONAL_MSR_DEVICE_DESCRIPTOR); - } - } - return Size; -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * - * This function return the register list according to the register ID. - * - * @param[in] RegisterLstID - value of the Register list ID. - * @param[out] **RegisterHeader - pointer to the address of the register list. - * @return none - */ -AGESA_STATUS -STATIC -MemNS3GetDeviceRegLstLN ( - IN UINT32 RegisterLstID, - OUT VOID **RegisterHeader - ) -{ - if (RegisterLstID >= (sizeof (MemS3RegListLN) / sizeof (VOID *))) { - ASSERT(FALSE); // RegisterListID exceeded size of Register list - return AGESA_FATAL; - } - if (MemS3RegListLN[RegisterLstID] != NULL) { - *RegisterHeader = MemS3RegListLN[RegisterLstID]; - return AGESA_SUCCESS; - } - ASSERT(FALSE); // Device register list error - return AGESA_FATAL; -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * - * This function that set PllLockTime to default state. - * - * @param[in] AccessWidth - Access width of the register. - * @param[in] Address - address in PCI_ADDR format. - * @param[in, out] *Value - Pointer to the value to be written. - * @param[in, out] *ConfigPtr - Pointer to Config handle. - * @return none - */ -VOID -STATIC -MemNS3SetDfltPllLockTimeLN ( - IN ACCESS_WIDTH AccessWidth, - IN PCI_ADDR Address, - IN OUT VOID *Value, - IN OUT VOID *ConfigPtr - ) -{ - UINT16 RegValue; - - RegValue = 0x190; - MemNS3SetBitFieldNb (AccessS3SaveWidth16, Address, &RegValue, ConfigPtr); -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * - * This function sets PllUpdate bit before restoring Dram Phy Control - * - * @param[in] AccessWidth - Access width of the register. - * @param[in] Address - address in PCI_ADDR format. - * @param[in, out] *Value - Pointer to the value to be written. - * @param[in, out] *ConfigPtr - Pointer to Config handle. - * @return none - */ -VOID -STATIC -MemNS3SetDramPhyCtrlRegLN ( - IN ACCESS_WIDTH AccessWidth, - IN PCI_ADDR Address, - IN OUT VOID *Value, - IN OUT VOID *ConfigPtr - ) -{ - UINT32 RegValue; - - RegValue = *(UINT32 *)Value | 0x00800000; - MemNS3SetBitFieldNb (AccessWidth, Address, &RegValue, ConfigPtr); -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * This function is a wrapper to call a CPU routine to change NB P-state and - * update NB frequency. - * - * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK - * @param[in] *NBPstate - NB Pstate - * - * @return TRUE - Succeed - * @return FALSE - Fail - */ - -BOOLEAN -STATIC -MemNS3ChangeNbFrequencyWrapLN ( - IN OUT MEM_NB_BLOCK *NBPtr, - IN UINT32 NBPstate - ) -{ - BOOLEAN Status; - UINT32 NBFreq; - UINT32 Speed; - - MemNSwitchDCTNb (NBPtr, 1); - Speed = MemNGetBitFieldNb (NBPtr, BFMemClkFreq); - MemNSwitchDCTNb (NBPtr, 0); - Speed |= MemNGetBitFieldNb (NBPtr, BFMemClkFreq); - Status = F12NbPstateInit (((Speed + 6) * 3335) / 100, - Speed, - NBPstate, - &NBFreq, - &(NBPtr->MemPtr->StdHeader)); - - return Status; -} - - diff --git a/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/LN/mnS3ln.h b/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/LN/mnS3ln.h deleted file mode 100644 index fb5d0c9df4..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/LN/mnS3ln.h +++ /dev/null @@ -1,83 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * mnS3ln.h - * - * S3 resume memory related function for LN. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: (Mem/NB/LN) - * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $ - * - **/ -/***************************************************************************** -* -* Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* *************************************************************************** -* -*/ - -#ifndef _MNS3LN_H_ -#define _MNS3LN_H_ - -/*---------------------------------------------------------------------------- - * Mixed (DEFINITIONS AND MACROS / TYPEDEFS, STRUCTURES, ENUMS) - * - *---------------------------------------------------------------------------- - */ -/// ID for register list of LN -typedef enum { - PCI_LST_ESR_LN, ///< Assign 0x0000 for PCI register list for pre exit self refresh. - PCI_LST_LN, ///< Assign 0x0001 for PCI register list for post exist self refresh. - CPCI_LST_ESR_LN, ///< Assign 0x0002 for conditional PCI register list for pre exit self refresh. - CPCI_LST_LN, ///< Assign 0x0003 for conditional PCI register list for post exit self refresh. - MSR_LST_ESR_LN, ///< Assign 0x0004 for MSR register list for pre exit self refresh. - MSR_LST_LN, ///< Assign 0x0005 for MSR register list for post exit self refresh. - CMSR_LST_ESR_LN, ///< Assign 0x0006 for conditional MSR register list for pre exit self refresh. - CMSR_LST_LN ///< Assign 0x0007 for conditional MSR register list for post exit self refresh. -} RegisterListIDLN; - -/*----------------------------------------------------------------------------- - * DEFINITIONS AND MACROS - * - *----------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------- - * TYPEDEFS, STRUCTURES, ENUMS - * - *---------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------- - * FUNCTIONS PROTOTYPE - * - *---------------------------------------------------------------------------- - */ - -#endif //_MNS3LN_H_ diff --git a/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/LN/mndctln.c b/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/LN/mndctln.c deleted file mode 100644 index 6db8efd070..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/LN/mndctln.c +++ /dev/null @@ -1,469 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * mndctln.c - * - * Northbridge LN DCT supporting functions - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: (Mem/NB/LN) - * @e \$Revision: 45647 $ @e \$Date: 2011-01-20 04:53:23 +0800 (Thu, 20 Jan 2011) $ - * - **/ -/***************************************************************************** -* -* Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* *************************************************************************** -* -*/ - - -/* - *---------------------------------------------------------------------------- - * MODULES USED - * - *---------------------------------------------------------------------------- - */ - - - -#include "AGESA.h" -#include "amdlib.h" -#include "Ids.h" -#include "mm.h" -#include "mn.h" -#include "mt.h" -#include "mu.h" -#include "OptionMemory.h" // need def for MEM_FEAT_BLOCK_NB -#include "mnln.h" -#include "mftds.h" -#include "merrhdl.h" -#include "GeneralServices.h" -#include "cpuFamilyTranslation.h" -#include "cpuCommonF12Utilities.h" -#include "Filecode.h" -CODE_GROUP (G1_PEICC) -RDATA_GROUP (G1_PEICC) - -#define FILECODE PROC_MEM_NB_LN_MNDCTLN_FILECODE -/*---------------------------------------------------------------------------- - * DEFINITIONS AND MACROS - * - *---------------------------------------------------------------------------- - */ -#define MAX_RD_DQS_DLY 0x1F - -/*---------------------------------------------------------------------------- - * TYPEDEFS AND STRUCTURES - * - *---------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------- - * PROTOTYPES OF LOCAL FUNCTIONS - * - *---------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------- - * EXPORTED FUNCTIONS - * - *---------------------------------------------------------------------------- - */ - -extern BUILD_OPT_CFG UserOptions; - -/* -----------------------------------------------------------------------------*/ -/** - * - * - * This function programs the memory controller with configuration parameters - * - * - * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK - * - * @return TRUE - An Error value lower than AGESA_FATAL may have occurred - * @return FALSE - An Error value greater than or equal to AGESA_FATAL may have occurred - * @return NBPtr->MCTPtr->ErrCode - Contains detailed AGESA_STATUS value - */ - -BOOLEAN -MemNAutoConfigLN ( - IN OUT MEM_NB_BLOCK *NBPtr - ) -{ - DIE_STRUCT *MCTPtr; - DCT_STRUCT *DCTPtr; - UINT8 PowerDownMode; - - MCTPtr = NBPtr->MCTPtr; - DCTPtr = NBPtr->DCTPtr; - - //====================================================================== - // Build Dram Control Register Value (F2x78) - //====================================================================== - // - - //====================================================================== - // Build Dram Config Lo Register Value - //====================================================================== - // - MemNSetBitFieldNb (NBPtr, BFEnDispAutoPrecharge, 1); - - MemNSetBitFieldNb (NBPtr, BFIdleCycInit, 3); - - //====================================================================== - // Build Dram Config Hi Register Value - //====================================================================== - // - - PowerDownMode = (UINT8) ((UserOptions.CfgPowerDownMode == POWER_DOWN_MODE_AUTO) ? POWER_DOWN_BY_CHIP_SELECT : UserOptions.CfgPowerDownMode); - PowerDownMode = (!NBPtr->IsSupported[ChannelPDMode]) ? PowerDownMode : 0; - IDS_OPTION_HOOK (IDS_POWERDOWN_MODE, &PowerDownMode, &(NBPtr->MemPtr->StdHeader)); - if (PowerDownMode == 1) { - MemNSetBitFieldNb (NBPtr, BFPowerDownMode, 1); - } - - MemNSetBitFieldNb (NBPtr, BFPchgPDModeSel, 1); - - MemNSetBitFieldNb (NBPtr, BFDcqBypassMax, 0xE); - - //====================================================================== - // Build Dram Config Misc Register Value - //====================================================================== - // - // Max out Non-SPD timings - MemNSetBitFieldNb (NBPtr, BFNonSPD, 0x18FF); - MemNSetBitFieldNb (NBPtr, BFNonSPDHi, 0x2A); - MemNSetBitFieldNb (NBPtr, BFTwrrdSD, 0xA); - MemNSetBitFieldNb (NBPtr, BFTrdrdSD, 0x8); - MemNSetBitFieldNb (NBPtr, BFTwrwrSD, 0x9); - - MemNSetBitFieldNb (NBPtr, BFWrOdtOnDuration, DEFAULT_WR_ODT_ON_LN); - MemNSetBitFieldNb (NBPtr, BFRdOdtOnDuration, DEFAULT_RD_ODT_ON_LN); - MemNSetBitFieldNb (NBPtr, BFWrOdtTrnOnDly, 0); - - //====================================================================== - // DRAM MRS Register, set ODT - //====================================================================== - MemNSetBitFieldNb (NBPtr, BFBurstCtrl, 1); - - return (BOOLEAN) (MCTPtr->ErrCode < AGESA_FATAL); -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * This function sends an MRS command - * - * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK - * - */ - -VOID -MemNSendMrsCmdLN ( - IN OUT MEM_NB_BLOCK *NBPtr - ) -{ - MemNSetASRSRTNb (NBPtr); - MemNSwapBitsNb (NBPtr); - - IDS_HDT_CONSOLE (MEM_FLOW, "\t\t\tCS%d MR%d %04x\n", - (MemNGetBitFieldNb (NBPtr, BFDramInitRegReg) >> 20) & 0xF, - (MemNGetBitFieldNb (NBPtr, BFDramInitRegReg) >> 16) & 0xF, - (MemNGetBitFieldNb (NBPtr, BFDramInitRegReg) & 0xFFFF)); - - // 1.Set SendMrsCmd=1 - MemNSetBitFieldNb (NBPtr, BFSendMrsCmd, 1); - - // 2.Wait for SendMrsCmd=0 - MemNPollBitFieldNb (NBPtr, BFSendMrsCmd, 0, PCI_ACCESS_TIMEOUT, FALSE); -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * - * This function sets the maximum round-trip latency in the system from the processor to the DRAM - * devices and back for Llano. - * - * - * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK - * @param[in] MaxRcvEnDly - Maximum receiver enable delay value - * - */ - -VOID -MemNSetMaxLatencyLN ( - IN OUT MEM_NB_BLOCK *NBPtr, - IN UINT16 MaxRcvEnDly - ) -{ - UINT32 N; - UINT32 T; - UINT32 P; - UINT32 Px2; - UINT32 MemClkPeriod; - - AGESA_TESTPOINT (TpProcMemRcvrCalcLatency, &(NBPtr->MemPtr->StdHeader)); - - N = 0x50; // init value for MaxRdLat used in SW RcvEn training, when MaxRcvEnDly==FFFF - - if (MaxRcvEnDly != 0xFFFF) { - T = MemNTotalSyncComponentsClientNb (NBPtr); - - // P = P + CEIL(MAX (total delay in DqsRcvEn + RdDqsTime)) - P = ((MaxRcvEnDly + MAX_RD_DQS_DLY) + 31) / 32; - - // P = P + 7.5 - // T = T + 2586 ps - Px2 = (P * 2) + 15; - T += 2586; - - if (NBPtr->IsSupported[ExtraPclkInMaxRdLat]) { - Px2 += 2; - } - - // N = (P/(MemClkFreq * 2) + T) * NclkFreq - MemClkPeriod = 1000000 / NBPtr->DCTPtr->Timings.Speed; - N = ((((Px2 * MemClkPeriod + 3) / 4) + T) * NBPtr->NBClkFreq + 999999) / 1000000; - } - - NBPtr->DCTPtr->Timings.MaxRdLat = (UINT16) N; - ASSERT (N <= 0x50); - IDS_HDT_CONSOLE (MEM_FLOW, "\t\tMaxRdLat: %03x\n", N); - MemNSetBitFieldNb (NBPtr, BFMaxLatency, N); -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * - * This function retrieves the Max latency parameters - * - * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK - * - * @param[in] *MinDlyPtr - Pointer to variable to store the Minimum Delay value - * @param[in] *MaxDlyPtr - Pointer to variable to store the Maximum Delay value - * @param[in] *DlyBiasPtr - Pointer to variable to store Delay Bias value - * @param[in] MaxDlyForMaxRdLat - Maximum receiver enable delay value - * - */ - -VOID -MemNGetMaxLatParamsClientLN ( - IN OUT MEM_NB_BLOCK *NBPtr, - IN UINT16 MaxDlyForMaxRdLat, - IN OUT UINT16 *MinDlyPtr, - IN OUT UINT16 *MaxDlyPtr, - IN OUT UINT16 *DlyBiasPtr - ) -{ - UINT32 P; - UINT32 Px2; - UINT32 T; - UINT32 MemClkPeriod; - - T = MemNTotalSyncComponentsClientNb (NBPtr); - - // P = P + CEIL(MAX (total delay in DqsRcvEn + RdDqsTime)) - P = (MaxDlyForMaxRdLat + 31) / 32; - - // P = P + 8.5 - // T = T + 2586 ps - Px2 = (P * 2) + 17; - T += 2586; - - // N = (P/(MemClkFreq * 2) + T) * NclkFreq - MemClkPeriod = 1000000 / NBPtr->DCTPtr->Timings.Speed; - - *MinDlyPtr = (UINT16) (((((Px2 * MemClkPeriod + 3) / 4) + T) * NBPtr->NBClkFreq + 999999) / 1000000); - - *MaxDlyPtr = 100 + *MinDlyPtr; // 100 fixed iterations - - // IF (REVB) THEN - // IF (D18F2x[1,0]78[MaxSkipErrTrain]==0 && NCLK!=MEMCLK && NCLK!=MEMCLK/2) - // THEN TrainingOffset = 3 - // ELSE TrainingOffset = 2 - // ELSE - // IF (NCLK!=MEMCLK && NCLK!=MEMCLK/2) - // THEN TrainingOffset = 3 - // ELSE TrainingOffset = 2 - *DlyBiasPtr = 3; - if (((NBPtr->DCTPtr->Timings.CasL > 5) && NBPtr->IsSupported[SkipErrTrain]) || - (NBPtr->NBClkFreq == NBPtr->DCTPtr->Timings.Speed) || - (NBPtr->NBClkFreq == (UINT32) (NBPtr->DCTPtr->Timings.Speed / 2)) || - (NBPtr->NBClkFreq == (UINT32) (NBPtr->DCTPtr->Timings.Speed / 2 + 1))) { - *DlyBiasPtr = 2; - } - - // Register settings required before MaxRdLat training - if (NBPtr->DCTPtr->Timings.CasL == 5) { - MemNSetBitFieldNb (NBPtr, BFMaxSkipErrTrain, 0); - } else { - MemNSetBitFieldNb (NBPtr, BFMaxSkipErrTrain, 1); - } - MemNSetBitFieldNb (NBPtr, BFSlotSel, 0); - MemNSetBitFieldNb (NBPtr, BFSlot1ExtraClkEn, 0); - MemNSetBitFieldNb (NBPtr, BFForceCasToSlot0, 1); -} - -/*---------------------------------------------------------------------------- - * LOCAL FUNCTIONS - * - *---------------------------------------------------------------------------- - */ - -/* -----------------------------------------------------------------------------*/ -/** - * - * This function is a wrapper to call a CPU routine to change NB P-state and - * update NB frequency. - * - * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK - * @param[in] *NBPstate - NB Pstate - * - * @return TRUE - Succeed - * @return FALSE - Fail - */ - -BOOLEAN -MemNChangeNbFrequencyWrapLN ( - IN OUT MEM_NB_BLOCK *NBPtr, - IN UINT32 NBPstate - ) -{ - BOOLEAN Status; - UINT32 NBFreq; - UINT32 Memclk; - CPU_SPECIFIC_SERVICES *FamilySpecificServices; - - if (NBPtr->NbFreqChgState == 0) { - // While in state 0, report the new memclk to the - // CPU module to adjust the NB P-state settings. - Memclk = NBPtr->DCTPtr->Timings.Speed; - } else { - // We have already adjusted for target memclk. - // Indicate NB P-state change only. - Memclk = 0; - } - - Status = F12NbPstateInit (Memclk, - MemNGetMemClkFreqIdClientNb (NBPtr, NBPtr->DCTPtr->Timings.Speed), - NBPstate, - &NBFreq, - &(NBPtr->MemPtr->StdHeader)); - - if (Status) { - // When NB frequency change succeeds, TSC rate may have changed. - // We need to update TSC rate - GetCpuServicesOfCurrentCore ((const CPU_SPECIFIC_SERVICES **) &FamilySpecificServices, &NBPtr->MemPtr->StdHeader); - FamilySpecificServices->GetTscRate (FamilySpecificServices, &NBPtr->MemPtr->TscRate, &NBPtr->MemPtr->StdHeader); - - if (NBPtr->DCTPtr->Timings.Speed == NBPtr->DCTPtr->Timings.TargetSpeed) { - // Turn on adjust negative WL only at target speed - NBPtr->IsSupported[WLNegativeDelay] = TRUE; - } - } - return Status; -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * - * This function enables swapping interleaved region feature. - * - * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK - * @param[in] Base - Swap interleaved region base [47:27] - * @param[in] Limit - Swap interleaved region limit [47:27] - * - */ -VOID -MemNEnableSwapIntlvRgnLN ( - IN OUT MEM_NB_BLOCK *NBPtr, - IN UINT32 Base, - IN UINT32 Limit - ) -{ - // Swapped interleaving region must be below 4G - if (Limit < (1 << (32 - 27))) { - MemNSetBitFieldNb (NBPtr, BFIntlvRegionBase, Base); - MemNSetBitFieldNb (NBPtr, BFIntlvRegionLimit, (Limit - 1)); - MemNSetBitFieldNb (NBPtr, BFIntlvRegionEn, 1); - } -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * This function skips setting LowPowerDrvStrengthEn on two DIMMs per channel config - * - * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK - * @param[in,out] OptParam - Optional parameter - * - * @return FALSE - Set LowPowerDrvStrengthEn - * @return TRUE - Clear LowPowerDrvStrengthEn - * ---------------------------------------------------------------------------- - */ -BOOLEAN -MemNDisLowPwrDrvStrLN ( - IN OUT MEM_NB_BLOCK *NBPtr, - IN OUT VOID *OptParam - ) -{ - if (NBPtr->ChannelPtr->Dimms > 1) { - return TRUE; - } else { - return FALSE; - } -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * - * This function returns MR0[WR] value - * - * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK - * - * @return MR0[WR] value - */ -UINT32 -MemNGetMR0WRLN ( - IN OUT MEM_NB_BLOCK *NBPtr - ) -{ - UINT32 Value32; - - Value32 = NBPtr->DCTPtr->Timings.Twr; - Value32 = ((Value32 >= 10) ? ((Value32 + 1) / 2) : (Value32 - 4)) & 7; - Value32 = Value32 << 9; - - return Value32; -} diff --git a/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/LN/mnflowln.c b/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/LN/mnflowln.c deleted file mode 100644 index 9b66b23f83..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/LN/mnflowln.c +++ /dev/null @@ -1,166 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * mnflowln.c - * - * Llano initializer for MCT and DCT - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: (Mem/Main) - * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $ - * - **/ -/***************************************************************************** -* -* Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* *************************************************************************** -* -*/ - -/* - *---------------------------------------------------------------------------- - * MODULES USED - * - *---------------------------------------------------------------------------- - */ - - - -#include "AGESA.h" -#include "AdvancedApi.h" -#include "amdlib.h" -#include "Ids.h" -#include "OptionMemory.h" -#include "mm.h" -#include "mn.h" -#include "mt.h" -#include "mnln.h" -#include "Filecode.h" -CODE_GROUP (G1_PEICC) -RDATA_GROUP (G1_PEICC) - -#define FILECODE PROC_MEM_NB_LN_MNFLOWLN_FILECODE - -/*---------------------------------------------------------------------------- - * DEFINITIONS AND MACROS - * - *---------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------- - * TYPEDEFS AND STRUCTURES - * - *---------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------- - * PROTOTYPES OF LOCAL FUNCTIONS - * - *---------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------- - * EXPORTED FUNCTIONS - * - *---------------------------------------------------------------------------- - */ -extern MEM_PLAT_SPEC_CFG* memPlatSpecFFInstalledLN[MAX_FF_TYPES]; -/* -----------------------------------------------------------------------------*/ -/** - * - * - * This function initializes the platform specific block - * - * - * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK - * - * @return TRUE - AGESA_SUCCESS at least one dorm factor was found - * @return FALSE - AGESA_UNSUPPORTED - Error indicating that no form factors were found - */ - -BOOLEAN -MemNPlatformSpecificFormFactorInitLN ( - IN OUT MEM_NB_BLOCK *NBPtr - ) -{ - UINT8 Dct; - UINT8 f; - for (Dct = 0; Dct < MAX_DCTS_PER_NODE_LN; Dct++) { - NBPtr->SwitchDCT (NBPtr, Dct); - if (NBPtr->ChannelPtr->ChDimmValid != 0) { - for (f = 0; memPlatSpecFFInstalledLN[f] != NULL; f++) { - if (memPlatSpecFFInstalledLN[f] (NBPtr->MemPtr, NBPtr->ChannelPtr, NBPtr->PsPtr) == AGESA_SUCCESS) { - break; - } - } - if (memPlatSpecFFInstalledLN[f] == NULL) { - return FALSE; // No FF types are supported - } - } - } - return TRUE; -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * This function selects appropriate Tech functions for the NB. - * - * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK - * - */ - -VOID -MemNTechBlockSwitchLN ( - IN OUT MEM_NB_BLOCK *NBPtr - ) -{ - MEM_TECH_BLOCK *TechPtr; - - TechPtr = NBPtr->TechPtr; - - // Specify Dimm-Byte training for Nb - MemTDimmByteTrainInit (TechPtr); - - // Remove the following functions because they are not needed for LN - TechPtr->SetDramMode = (BOOLEAN (*) (MEM_TECH_BLOCK *)) memDefTrue; - TechPtr->SpdCalcWidth = (BOOLEAN (*) (MEM_TECH_BLOCK *)) memDefTrue; - TechPtr->SetDqsEccTmgs = (BOOLEAN (*) (MEM_TECH_BLOCK *)) memDefTrue; - TechPtr->AdjustTwrwr = (VOID (*) (MEM_TECH_BLOCK *)) memDefRet; - TechPtr->AdjustTwrrd = (VOID (*) (MEM_TECH_BLOCK *)) memDefRet; - TechPtr->GetLD = (INT8 (*) (MEM_TECH_BLOCK *)) memDefRet; - TechPtr->FindMaxDlyForMaxRdLat = MemTFindMaxRcvrEnDlyRdDqsDlyByte; - TechPtr->ResetDCTWrPtr = (VOID (*) (MEM_TECH_BLOCK *, UINT8)) memDefRet; -} - -/*---------------------------------------------------------------------------- - * LOCAL FUNCTIONS - * - *---------------------------------------------------------------------------- - */ - diff --git a/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/LN/mnidendimmln.c b/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/LN/mnidendimmln.c deleted file mode 100644 index 759bb4fdc2..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/LN/mnidendimmln.c +++ /dev/null @@ -1,136 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * mnidendimmln.c - * - * LN northbridge constructor for dimm identification translator. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: (Mem/NB/HY) - * @e \$Revision: 45911 $ @e \$Date: 2011-01-25 04:55:11 +0800 (Tue, 25 Jan 2011) $ - * - **/ -/***************************************************************************** -* -* Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* *************************************************************************** -* -*/ - -/* - *---------------------------------------------------------------------------- - * MODULES USED - * - *---------------------------------------------------------------------------- - */ - - - -#include "AGESA.h" -#include "mm.h" -#include "mn.h" -#include "OptionMemory.h" // need def for MEM_FEAT_BLOCK_NB -#include "cpuFamilyTranslation.h" -#include "mnln.h" -#include "mfidendimm.h" -#include "Filecode.h" -CODE_GROUP (G2_PEI) -RDATA_GROUP (G2_PEI) - -#define FILECODE PROC_MEM_NB_LN_MNIDENDIMMLN_FILECODE - -/*---------------------------------------------------------------------------- - * DEFINITIONS AND MACROS - * - *---------------------------------------------------------------------------- - */ - - -/*---------------------------------------------------------------------------- - * TYPEDEFS AND STRUCTURES - * - *---------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------- - * PROTOTYPES OF LOCAL FUNCTIONS - * - *---------------------------------------------------------------------------- - */ - - -/*---------------------------------------------------------------------------- - * EXPORTED FUNCTIONS - * - *---------------------------------------------------------------------------- - */ - -/* -----------------------------------------------------------------------------*/ -/** - * - * - * This function initializes the northbridge block for dimm identification translator - * - * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK - * @param[in,out] *MemPtr - Pointer to the MEM_DATA_STRUCT - * @param[in,out] NodeID - ID of current node to construct - * @return TRUE - This is the correct constructor for the targeted node. - * @return FALSE - This isn't the correct constructor for the targeted node. - */ - -BOOLEAN -MemNIdentifyDimmConstructorLN ( - IN OUT MEM_NB_BLOCK *NBPtr, - IN OUT MEM_DATA_STRUCT *MemPtr, - IN UINT8 NodeID - ) -{ - // - // Determine if this is the expected NB Type - // - GetLogicalIdOfSocket (MemPtr->DiesPerSystem[NodeID].SocketId, &(MemPtr->DiesPerSystem[NodeID].LogicalCpuid), &(MemPtr->StdHeader)); - if (!MemNIsIdSupportedLN (NBPtr, &(MemPtr->DiesPerSystem[NodeID].LogicalCpuid))) { - return FALSE; - } - - NBPtr->NodeCount = MAX_NODES_SUPPORTED_LN; - NBPtr->DctCount = MAX_DCTS_PER_NODE_LN; - NBPtr->CsRegMsk = 0x1FF83FE0; - NBPtr->MemPtr = MemPtr; - NBPtr->MCTPtr = &(MemPtr->DiesPerSystem[NodeID]); - NBPtr->PciAddr.AddressValue = MemPtr->DiesPerSystem[NodeID].PciAddr.AddressValue; - NBPtr->Node = ((UINT8) NBPtr->PciAddr.Address.Device) - 24; - NBPtr->Ganged = FALSE; - MemNInitNBRegTableLN (NBPtr, NBPtr->NBRegTable); - NBPtr->MemNCmnGetSetFieldNb = MemNCmnGetSetFieldLN; - NBPtr->SetBitField = MemNSetBitFieldNb; - NBPtr->GetBitField = MemNGetBitFieldNb; - NBPtr->GetSocketRelativeChannel = MemNGetSocketRelativeChannelNb; - - return TRUE; -} diff --git a/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/LN/mnln.c b/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/LN/mnln.c deleted file mode 100644 index 26f9c45750..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/LN/mnln.c +++ /dev/null @@ -1,499 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * mnln.c - * - * Common Northbridge functions for LN - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: (Mem/NB/LN) - * @e \$Revision: 48400 $ @e \$Date: 2011-03-08 16:28:12 +0800 (Tue, 08 Mar 2011) $ - * - **/ -/***************************************************************************** -* -* Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* *************************************************************************** -* -*/ -/* - *---------------------------------------------------------------------------- - * MODULES USED - * - *---------------------------------------------------------------------------- - */ - - - -#include "AGESA.h" -#include "AdvancedApi.h" -#include "amdlib.h" -#include "Ids.h" -#include "OptionMemory.h" -#include "mm.h" -#include "mn.h" -#include "mnln.h" -#include "mu.h" -#include "S3.h" -#include "cpuRegisters.h" -#include "cpuFamRegisters.h" -#include "cpuFamilyTranslation.h" -#include "heapManager.h" -#include "GeneralServices.h" -#include "Filecode.h" -CODE_GROUP (G1_PEICC) -RDATA_GROUP (G1_PEICC) - -#define FILECODE PROC_MEM_NB_LN_MNLN_FILECODE -/*---------------------------------------------------------------------------- - * DEFINITIONS AND MACROS - * - *---------------------------------------------------------------------------- - */ - -#define SPLIT_CHANNEL (UINT32) 0x20000000 -#define CHANNEL_SELECT (UINT32) 0x10000000 - -/*---------------------------------------------------------------------------- - * TYPEDEFS AND STRUCTURES - * - *---------------------------------------------------------------------------- - */ -CONST MEM_FREQ_CHANGE_PARAM FreqChangeParamLN = {0x0190, 7, 7, 14, 3, 18, 470, 946}; -/*---------------------------------------------------------------------------- - * PROTOTYPES OF LOCAL FUNCTIONS - * - *---------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------- - * EXPORTED FUNCTIONS - * - *---------------------------------------------------------------------------- - */ - -extern BUILD_OPT_CFG UserOptions; -extern PSO_ENTRY DefaultPlatformMemoryConfiguration[]; -extern OPTION_MEM_FEATURE_NB* memNTrainFlowControl[]; - -/* -----------------------------------------------------------------------------*/ -/** - * - * This function initializes the northbridge block - * - * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK - * @param[in,out] *MemPtr - Pointer to the MEM_DATA_STRUCT - * @param[in] *FeatPtr - Pointer to the MEM_FEAT_BLOCK_NB - * @param[in] *SharedPtr - Pointer to the MEM_SHARED_DATA - * @param[in] NodeID - UINT8 indicating node ID of the NB object. - * - * @retval Boolean indicating that this is the correct memory - * controller type for the node number that was passed in. - */ - -BOOLEAN -MemConstructNBBlockLN ( - IN OUT MEM_NB_BLOCK *NBPtr, - IN OUT MEM_DATA_STRUCT *MemPtr, - IN MEM_FEAT_BLOCK_NB *FeatPtr, - IN MEM_SHARED_DATA *SharedPtr, - IN UINT8 NodeID - ) -{ - UINT8 Dct; - UINT8 Channel; - UINT8 SpdSocketIndex; - UINT8 SpdChannelIndex; - DIE_STRUCT *MCTPtr; - ALLOCATE_HEAP_PARAMS AllocHeapParams; - - // - // Determine if this is the expected NB Type - // - GetLogicalIdOfSocket (MemPtr->DiesPerSystem[NodeID].SocketId, &(MemPtr->DiesPerSystem[NodeID].LogicalCpuid), &(MemPtr->StdHeader)); - if (!MemNIsIdSupportedLN (NBPtr, &(MemPtr->DiesPerSystem[NodeID].LogicalCpuid))) { - return FALSE; - } - - NBPtr->MemPtr = MemPtr; - NBPtr->RefPtr = MemPtr->ParameterListPtr; - NBPtr->SharedPtr = SharedPtr; - - MCTPtr = &(MemPtr->DiesPerSystem[NodeID]); - NBPtr->MCTPtr = MCTPtr; - NBPtr->MCTPtr->NodeId = NodeID; - NBPtr->PciAddr.AddressValue = MCTPtr->PciAddr.AddressValue; - NBPtr->VarMtrrHiMsk = GetVarMtrrHiMsk (&(MemPtr->DiesPerSystem[NodeID].LogicalCpuid), &(MemPtr->StdHeader)); - - // - // Allocate buffer for DCT_STRUCTs and CH_DEF_STRUCTs - // - AllocHeapParams.RequestedBufferSize = MAX_DCTS_PER_NODE_LN * ( - sizeof (DCT_STRUCT) + ( - MAX_CHANNELS_PER_DCT_LN * (sizeof (CH_DEF_STRUCT) + sizeof (MEM_PS_BLOCK)) - ) - ); - AllocHeapParams.BufferHandle = GENERATE_MEM_HANDLE (ALLOC_DCT_STRUCT_HANDLE, NodeID, 0, 0); - AllocHeapParams.Persist = HEAP_LOCAL_CACHE; - if (HeapAllocateBuffer (&AllocHeapParams, &MemPtr->StdHeader) != AGESA_SUCCESS) { - PutEventLog (AGESA_FATAL, MEM_ERROR_HEAP_ALLOCATE_FOR_DCT_STRUCT_AND_CH_DEF_STRUCTs, NBPtr->Node, 0, 0, 0, &MemPtr->StdHeader); - SetMemError (AGESA_FATAL, MCTPtr); - ASSERT(FALSE); // Could not allocate buffer for DCT_STRUCTs and CH_DEF_STRUCTs - return FALSE; - } - - MCTPtr->DctCount = MAX_DCTS_PER_NODE_LN; - MCTPtr->DctData = (DCT_STRUCT *) AllocHeapParams.BufferPtr; - AllocHeapParams.BufferPtr += MAX_DCTS_PER_NODE_LN * sizeof (DCT_STRUCT); - for (Dct = 0; Dct < MAX_DCTS_PER_NODE_LN; Dct++) { - MCTPtr->DctData[Dct].Dct = Dct; - MCTPtr->DctData[Dct].ChannelCount = MAX_CHANNELS_PER_DCT_LN; - MCTPtr->DctData[Dct].ChData = (CH_DEF_STRUCT *) AllocHeapParams.BufferPtr; - MCTPtr->DctData[Dct].ChData[0].Dct = Dct; - AllocHeapParams.BufferPtr += MAX_CHANNELS_PER_DCT_LN * sizeof (CH_DEF_STRUCT); - } - NBPtr->PSBlock = (MEM_PS_BLOCK *) AllocHeapParams.BufferPtr; - - - // - // Initialize Socket List - // - for (Dct = 0; Dct < MAX_DCTS_PER_NODE_LN; Dct++) { - MemPtr->SocketList[MCTPtr->SocketId].ChannelPtr[Dct] = &(MCTPtr->DctData[Dct].ChData[0]); - MemPtr->SocketList[MCTPtr->SocketId].TimingsPtr[Dct] = &(MCTPtr->DctData[Dct].Timings); - MCTPtr->DctData[Dct].ChData[0].ChannelID = Dct; - } - - // - // Initialize NB block member variables - // - NBPtr->DctCachePtr = NBPtr->DctCache; - NBPtr->PsPtr = NBPtr->PSBlock; - - MemNInitNBRegTableLN (NBPtr, NBPtr->NBRegTable); - NBPtr->Node = 0; - NBPtr->Dct = 0; - NBPtr->Channel = 0; - NBPtr->DctCount = MAX_DCTS_PER_NODE_LN; - NBPtr->ChannelCount = MAX_CHANNELS_PER_DCT_LN; - NBPtr->NodeCount = MAX_NODES_SUPPORTED_LN; - NBPtr->Ganged = FALSE; - NBPtr->PosTrnPattern = POS_PATTERN_256B; - NBPtr->MemCleared = FALSE; - NBPtr->StartupSpeed = DDR800_FREQUENCY; - NBPtr->RcvrEnDlyLimit = 0x1FF; - NBPtr->NbFreqChgState = 0; - NBPtr->DefDctSelIntLvAddr = 5; - NBPtr->FreqChangeParam = (MEM_FREQ_CHANGE_PARAM *) &FreqChangeParamLN; - NBPtr->CsRegMsk = 0x1FF83FE0; - NBPtr->MaxRxEnSeedTotal = 0x33F; - NBPtr->MinRxEnSeedGross = 0; - - LibAmdMemFill (NBPtr->DctCache, 0, sizeof (NBPtr->DctCache), &NBPtr->MemPtr->StdHeader); - - NBPtr->SetMaxLatency = MemNSetMaxLatencyLN; - NBPtr->getMaxLatParams = MemNGetMaxLatParamsClientLN; - NBPtr->InitializeMCT = (BOOLEAN (*) (MEM_NB_BLOCK *)) memDefTrue; - NBPtr->FinalizeMCT = MemNFinalizeMctLN; - NBPtr->SendMrsCmd = MemNSendMrsCmdLN; - NBPtr->sendZQCmd = MemNSendZQCmdNb; - NBPtr->WritePattern = MemNWritePatternLN; - NBPtr->ReadPattern = MemNReadPatternLN; - NBPtr->GenHwRcvEnReads = (VOID (*) (MEM_NB_BLOCK *, UINT32)) memDefRet; - - NBPtr->CompareTestPattern = MemNCompareTestPatternNb; - NBPtr->InsDlyCompareTestPattern = MemNInsDlyCompareTestPatternNb; - NBPtr->InitMCT = MemNInitMCTNb; - NBPtr->StitchMemory = MemNStitchMemoryNb; - NBPtr->AutoConfig = MemNAutoConfigLN; - NBPtr->PlatformSpec = MemNPlatformSpecUnb; - NBPtr->DisableDCT = MemNDisableDCTClientNb; - NBPtr->StartupDCT = MemNStartupDCTUnb; - NBPtr->SyncTargetSpeed = MemNSyncTargetSpeedNb; - NBPtr->MemNCapSpeedBatteryLife = (VOID (*) (MEM_NB_BLOCK *)) memDefRet; - NBPtr->ChangeFrequency = MemNChangeFrequencyClientNb; - NBPtr->RampUpFrequency = MemNRampUpFrequencyNb; - NBPtr->ChangeNbFrequency = MemNChangeNbFrequencyNb; - NBPtr->ProgramNbPsDependentRegs = MemNProgramNbPstateDependentRegistersClientNb; - NBPtr->ProgramCycTimings = MemNProgramCycTimingsClientNb; - NBPtr->SyncDctsReady = (BOOLEAN (*) (MEM_NB_BLOCK *)) memDefTrue; - NBPtr->HtMemMapInit = MemNHtMemMapInitLN; - NBPtr->SyncAddrMapToAllNodes = (VOID (*) (MEM_NB_BLOCK *)) memDefRet; - NBPtr->CpuMemTyping = MemNCPUMemTypingNb; - NBPtr->UMAMemTyping = MemNUMAMemTypingNb; - NBPtr->BeforeDqsTraining = MemNBeforeDQSTrainingLN; - NBPtr->AfterDqsTraining = MemNAfterDQSTrainingLN; - NBPtr->OtherTiming = MemNOtherTimingLN; - NBPtr->GetSocketRelativeChannel = MemNGetSocketRelativeChannelNb; - NBPtr->TechBlockSwitch = MemNTechBlockSwitchLN; - NBPtr->SetEccSymbolSize = (VOID (*) (MEM_NB_BLOCK *)) memDefRet; - NBPtr->TrainingFlow = (VOID (*) (MEM_NB_BLOCK *))(memNTrainFlowControl[DDR3_TRAIN_FLOW]); - NBPtr->MinDataEyeWidth = MemNMinDataEyeWidthNb; - NBPtr->ChangeNbFrequencyWrap = MemNChangeNbFrequencyWrapLN; - NBPtr->AllocateC6Storage = MemNAllocateC6StorageClientNb; - - MemNInitNBDataNb (NBPtr); - FeatPtr->InitHwRxEn (NBPtr); - - NBPtr->PollBitField = MemNPollBitFieldNb; - NBPtr->BrdcstCheck = MemNBrdcstCheckNb; - NBPtr->BrdcstSet = MemNBrdcstSetNb; - NBPtr->GetTrainDly = MemNGetTrainDlyNb; - NBPtr->SetTrainDly = MemNSetTrainDlyNb; - NBPtr->PhyFenceTraining = MemNPhyFenceTrainingUnb; - NBPtr->GetSysAddr = MemNGetMCTSysAddrNb; - NBPtr->RankEnabled = MemNRankEnabledNb; - NBPtr->MemNCmnGetSetFieldNb = MemNCmnGetSetFieldLN; - NBPtr->MemNBeforeDramInitNb = (VOID (*) (MEM_NB_BLOCK *)) memDefRet; - NBPtr->MemNBeforePlatformSpecNb = (VOID (*) (MEM_NB_BLOCK *)) memDefRet; - NBPtr->MemNInitPhyComp = MemNInitPhyCompClientNb; - NBPtr->MemNcmnGetSetTrainDly = MemNcmnGetSetTrainDlyClientNb; - NBPtr->MemPPhyFenceTrainingNb = (VOID (*) (MEM_NB_BLOCK *)) memDefRet; - NBPtr->MemNPlatformSpecificFormFactorInitNb = MemNPlatformSpecificFormFactorInitLN; - NBPtr->MemNPFenceAdjustNb = MemNPFenceAdjustUnb; - NBPtr->GetTrainDlyParms = MemNGetTrainDlyParmsClientNb; - NBPtr->TrainingPatternInit = MemNTrainingPatternInitNb; - NBPtr->TrainingPatternFinalize = MemNTrainingPatternFinalizeNb; - NBPtr->GetApproximateWriteDatDelay = MemNGetApproximateWriteDatDelayNb; - NBPtr->CSPerChannel = MemNCSPerChannelLN; - NBPtr->CSPerDelay = MemNCSPerDelayNb; - NBPtr->FlushPattern = MemNFlushPatternNb; - NBPtr->GetUmaSize = MemNGetUmaSizeLN; - NBPtr->GetMemClkFreqId = MemNGetMemClkFreqIdClientNb; - NBPtr->EnableSwapIntlvRgn = MemNEnableSwapIntlvRgnLN; - NBPtr->WaitXMemClks = MemNWaitXMemClksNb; - NBPtr->MemNGetDramTerm = MemNGetDramTermNb; - NBPtr->MemNGetDynDramTerm = MemNGetDynDramTermNb; - NBPtr->MemNGetMR0CL = MemNGetMR0CLNb; - NBPtr->MemNGetMR0WR = MemNGetMR0WRLN; - NBPtr->MemNSaveMR0 = (VOID (*) (MEM_NB_BLOCK *, UINT32)) memDefRet; - NBPtr->MemNGetMR2CWL = MemNGetMR2CWLNb; - - NBPtr->IsSupported[SetDllShutDown] = TRUE; - NBPtr->IsSupported[CheckPhyFenceTraining] = TRUE; - NBPtr->IsSupported[CheckSendAllMRCmds] = TRUE; - NBPtr->IsSupported[CheckFindPSDct] = TRUE; - NBPtr->IsSupported[FenceTrnBeforeDramInit] = TRUE; - NBPtr->IsSupported[WLSeedAdjust] = TRUE; - NBPtr->IsSupported[UnifiedNbFence] = TRUE; - NBPtr->IsSupported[CheckODTControls] = TRUE; - NBPtr->IsSupported[ReverseMaxRdLatTrain] = TRUE; - NBPtr->IsSupported[SkipErrTrain] = TRUE; - NBPtr->IsSupported[DramSrHys] = TRUE; - NBPtr->IsSupported[CheckMaxDramRate] = TRUE; - NBPtr->IsSupported[SchedDlySlot1Extra] = TRUE; - NBPtr->IsSupported[CsrPhyPllPdEn] = TRUE; - NBPtr->IsSupported[AdjustTrc] = TRUE; - NBPtr->IsSupported[ProgramCsrComparator] = TRUE; - NBPtr->IsSupported[CheckDrvImpCtrl] = TRUE; - NBPtr->IsSupported[EnProcOdtAdvForUDIMM] = TRUE; - - NBPtr->FamilySpecificHook[AddlMaxRdLatTrain] = MemNSlot1MaxRdLatTrainClientNb; - NBPtr->FamilySpecificHook[BeforePhyFenceTraining] = MemNBeforePhyFenceTrainingClientNb; - NBPtr->FamilySpecificHook[ReEnablePhyComp] = MemNReEnablePhyCompNb; - NBPtr->FamilySpecificHook[AdjustTxpdll] = MemNAdjustTxpdllClientNb; - NBPtr->FamilySpecificHook[DisLowPwrDrvStr] = MemNDisLowPwrDrvStrLN; - NBPtr->FamilySpecificHook[CalcWrDqDqsEarly] = MemNCalcWrDqDqsEarlyClientNb; - NBPtr->FamilySpecificHook[InitializeRxEnSeedlessTraining] = MemNInitializeRxEnSeedlessTrainingUnb; - NBPtr->FamilySpecificHook[TrackRxEnSeedlessRdWrNoWindBLError] = MemNTrackRxEnSeedlessRdWrNoWindBLErrorUnb; - NBPtr->FamilySpecificHook[TrackRxEnSeedlessRdWrSmallWindBLError] = MemNTrackRxEnSeedlessRdWrSmallWindBLErrorUnb; - NBPtr->FamilySpecificHook[InitialzeRxEnSeedlessByteLaneError] = MemNInitialzeRxEnSeedlessByteLaneErrorUnb; - NBPtr->FamilySpecificHook[OverridePrevPassRcvEnDly] = MemNOverridePrevPassRcvEnDlyLN; - NBPtr->FamilySpecificHook[ResetRxFifoPtr] = MemNResetRxFifoPtrClientNb; - NBPtr->FamilySpecificHook[BfAfExcludeDimm] = MemNBfAfExcludeDimmClientNb; - - FeatPtr->InitCPG (NBPtr); - FeatPtr->InitEarlySampleSupport (NBPtr); - - NBPtr->FeatPtr = FeatPtr; - - // - // Calculate SPD Offsets per channel and assign pointers - // to the data. - // - SpdSocketIndex = GetSpdSocketIndex (NBPtr->RefPtr->PlatformMemoryConfiguration, NBPtr->MCTPtr->SocketId, &MemPtr->StdHeader); - // - // Traverse the Dct/Channel structures - // - for (Dct = 0; Dct < MAX_DCTS_PER_NODE_LN; Dct++) { - for (Channel = 0; Channel < MAX_CHANNELS_PER_DCT_LN; Channel++) { - // - // Calculate the number of Dimms on this channel using the - // die/dct/channel to Socket/channel conversion. - // - SpdChannelIndex = GetSpdChannelIndex (NBPtr->RefPtr->PlatformMemoryConfiguration, - NBPtr->MCTPtr->SocketId, - MemNGetSocketRelativeChannelNb (NBPtr, Dct, Channel), - &MemPtr->StdHeader); - NBPtr->MCTPtr->DctData[Dct].ChData[Channel].SpdPtr = &(MemPtr->SpdDataStructure[SpdSocketIndex + SpdChannelIndex]); - } - } - - MemNSwitchDCTNb (NBPtr, 0); - NBPtr->Channel = 0; - - return TRUE; -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * This function initializes the default values in the MEM_DATA_STRUCT - * - * @param[in,out] *MemPtr - Pointer to the MEM_DATA_STRUCT - * - * @retval None - */ -VOID -MemNInitDefaultsLN ( - IN OUT MEM_DATA_STRUCT *MemPtr - ) -{ - UINT8 Socket; - UINT8 Channel; - MEM_PARAMETER_STRUCT *RefPtr; - AGESA_TESTPOINT (TpProcMemBeforeMemDataInit, &(MemPtr->StdHeader)); - ASSERT (MemPtr != NULL); - RefPtr = MemPtr->ParameterListPtr; - - // Memory Map/Mgt. - // Mask Bottom IO with 0xF8 to force hole size to have granularity of 128MB - RefPtr->BottomIo = 0xE0; - RefPtr->UmaMode = UserOptions.CfgUmaMode; - RefPtr->UmaSize = UserOptions.CfgUmaSize; - RefPtr->MemHoleRemapping = TRUE; - RefPtr->LimitMemoryToBelow1Tb = UserOptions.CfgLimitMemoryToBelow1Tb; - // - - - // Dram Timing - RefPtr->UserTimingMode = UserOptions.CfgTimingModeSelect; - RefPtr->MemClockValue = UserOptions.CfgMemoryClockSelect; - for (Socket = 0; Socket < MAX_SOCKETS_SUPPORTED; Socket++) { - for (Channel = 0; Channel < MAX_CHANNELS_PER_SOCKET; Channel++) { - MemPtr->SocketList[Socket].ChannelPtr[Channel] = NULL; - MemPtr->SocketList[Socket].TimingsPtr[Channel] = NULL; - } - } - - // Memory Clear - RefPtr->EnableMemClr = TRUE; - - // TableBasedAlterations - RefPtr->TableBasedAlterations = NULL; - - // Platform config table - RefPtr->PlatformMemoryConfiguration = DefaultPlatformMemoryConfiguration; - - // Memory Restore - RefPtr->MemRestoreCtl = FALSE; - RefPtr->SaveMemContextCtl = FALSE; - AmdS3ParamsInitializer (&RefPtr->MemContext); - - // Dram Configuration - RefPtr->EnableBankIntlv = UserOptions.CfgMemoryEnableBankInterleaving; - RefPtr->EnableNodeIntlv = FALSE; - RefPtr->EnableChannelIntlv = UserOptions.CfgMemoryChannelInterleaving; - RefPtr->EnableBankSwizzle = UserOptions.CfgBankSwizzle; - RefPtr->EnableParity = FALSE; - RefPtr->EnableOnLineSpareCtl = FALSE; - - // Dram Power - RefPtr->EnablePowerDown = UserOptions.CfgMemoryPowerDown; - - // ECC - RefPtr->EnableEccFeature = UserOptions.CfgEnableEccFeature; -} - -/*-----------------------------------------------------------------------------*/ -/** - * - * This function writes training pattern - * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK - * @param[in] Pattern[] - Pattern to write - * @param[in] Address - System Address [47:16] - * @param[in] ClCount - Number of cache lines - * - */ - -VOID -MemNWritePatternLN ( - IN OUT MEM_NB_BLOCK *NBPtr, - IN UINT32 Address, - IN UINT8 Pattern[], - IN UINT16 ClCount - ) -{ - Address = MemUSetUpperFSbase (Address, NBPtr->MemPtr); - MemUWriteCachelines (Address, Pattern, ClCount); -} - -/*-----------------------------------------------------------------------------*/ -/** - * - * This function reads training pattern - * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK - * @param[in] Buffer[] - Buffer to fill - * @param[in] Address - System Address [47:16] - * @param[in] ClCount - Number of cache lines - * - */ - -VOID -MemNReadPatternLN ( - IN OUT MEM_NB_BLOCK *NBPtr, - IN UINT8 Buffer[], - IN UINT32 Address, - IN UINT16 ClCount - ) -{ - Address = MemUSetUpperFSbase (Address, NBPtr->MemPtr); - MemUReadCachelines (Buffer, Address, ClCount); -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * This function initiates DQS training for Client NB - * - * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK - * - */ - -BOOLEAN -memNEnableTrainSequenceLN ( - IN OUT MEM_NB_BLOCK *NBPtr - ) -{ - BOOLEAN Retval; - Retval = TRUE; - if (!MemNIsIdSupportedLN (NBPtr, &(NBPtr->MemPtr->DiesPerSystem[NBPtr->MCTPtr->NodeId].LogicalCpuid))) { - Retval = FALSE; - } - return Retval; -} diff --git a/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/LN/mnln.h b/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/LN/mnln.h deleted file mode 100644 index 73f67483fb..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/LN/mnln.h +++ /dev/null @@ -1,236 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * mnln.h - * - * Llano Northbridge block - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: (Mem) - * @e \$Revision: 48400 $ @e \$Date: 2011-03-08 16:28:12 +0800 (Tue, 08 Mar 2011) $ - * - **/ -/***************************************************************************** - * - * Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * *************************************************************************** - * - */ - -#ifndef _MNLN_H_ -#define _MNLN_H_ - -/*---------------------------------------------------------------------------- - * Mixed (DEFINITIONS AND MACROS / TYPEDEFS, STRUCTURES, ENUMS) - * - *---------------------------------------------------------------------------- - */ -#define MAX_CHANNELS_PER_SOCKET_LN 2 -#define MAX_DCTS_PER_NODE_LN 2 -#define MAX_CHANNELS_PER_DCT_LN 1 -#define MAX_DIMMS_PER_CHANNEL_LN 2 -#define MAX_NODES_SUPPORTED_LN 1 - -#define DEFAULT_WR_ODT_ON_LN 6 -#define DEFAULT_RD_ODT_ON_LN 6 -/*----------------------------------------------------------------------------- - * DEFINITIONS AND MACROS - * - *----------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------- - * TYPEDEFS, STRUCTURES, ENUMS - * - *---------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------- - * FUNCTIONS PROTOTYPE - * - *---------------------------------------------------------------------------- - */ - -BOOLEAN -MemConstructNBBlockLN ( - IN OUT MEM_NB_BLOCK *NBPtr, - IN OUT MEM_DATA_STRUCT *MemPtr, - IN MEM_FEAT_BLOCK_NB *FeatPtr, - IN MEM_SHARED_DATA *SharedPtr, - IN UINT8 NodeID - ); - -VOID -MemNInitDefaultsLN ( - IN OUT MEM_DATA_STRUCT *MemPtr - ); - -VOID -MemNSendMrsCmdLN ( - IN OUT MEM_NB_BLOCK *NBPtr - ); - -BOOLEAN -MemNAutoConfigLN ( - IN OUT MEM_NB_BLOCK *NBPtr - ); - -BOOLEAN -MemNOtherTimingLN ( - IN OUT MEM_NB_BLOCK *NBPtr - ); - -VOID -MemNWritePatternLN ( - IN OUT MEM_NB_BLOCK *NBPtr, - IN UINT32 Address, - IN UINT8 Pattern[], - IN UINT16 ClCount - ); - -VOID -MemNReadPatternLN ( - IN OUT MEM_NB_BLOCK *NBPtr, - IN UINT8 Buffer[], - IN UINT32 Address, - IN UINT16 ClCount - ); - -VOID -MemNInitNBRegTableLN ( - IN OUT MEM_NB_BLOCK *NBPtr, - IN OUT TSEFO NBRegTable[] - ); - -VOID -MemNBeforeDQSTrainingLN ( - IN OUT MEM_NB_BLOCK *NBPtr - ); - -VOID -MemNAfterDQSTrainingLN ( - IN OUT MEM_NB_BLOCK *NBPtr - ); - -BOOLEAN -MemNPlatformSpecificFormFactorInitLN ( - IN OUT MEM_NB_BLOCK *NBPtr - ); - -BOOLEAN -MemNIsIdSupportedLN ( - IN OUT MEM_NB_BLOCK *NBPtr, - IN CPU_LOGICAL_ID *LogicalIdPtr - ); - -UINT32 -MemNCmnGetSetFieldLN ( - IN OUT MEM_NB_BLOCK *NBPtr, - IN UINT8 IsSet, - IN BIT_FIELD_NAME FieldName, - IN UINT32 Field - ); - -UINT32 -MemNGetUmaSizeLN ( - IN OUT MEM_NB_BLOCK *NBPtr - ); - -BOOLEAN -MemNFinalizeMctLN ( - IN OUT MEM_NB_BLOCK *NBPtr - ); - -VOID -MemNTechBlockSwitchLN ( - IN OUT MEM_NB_BLOCK *NBPtr - ); - -BOOLEAN -MemNHtMemMapInitLN ( - IN OUT MEM_NB_BLOCK *NBPtr - ); - -UINT8 -MemNCSPerChannelLN ( - IN OUT MEM_NB_BLOCK *NBPtr - ); - -VOID -MemNSetMaxLatencyLN ( - IN OUT MEM_NB_BLOCK *NBPtr, - IN UINT16 MaxRcvEnDly - ); - -VOID -MemNEnableSwapIntlvRgnLN ( - IN OUT MEM_NB_BLOCK *NBPtr, - IN UINT32 Base, - IN UINT32 Limit - ); - -BOOLEAN -memNEnableTrainSequenceLN ( - IN OUT MEM_NB_BLOCK *NBPtr - ); - -BOOLEAN -MemNChangeNbFrequencyWrapLN ( - IN OUT MEM_NB_BLOCK *NBPtr, - IN UINT32 NBPstate - ); - -VOID -MemNGetMaxLatParamsClientLN ( - IN OUT MEM_NB_BLOCK *NBPtr, - IN UINT16 MaxDlyForMaxRdLat, - IN OUT UINT16 *MinDlyPtr, - IN OUT UINT16 *MaxDlyPtr, - IN OUT UINT16 *DlyBiasPtr - ); - -BOOLEAN -MemNDisLowPwrDrvStrLN ( - IN OUT MEM_NB_BLOCK *NBPtr, - IN OUT VOID *OptParam - ); - -UINT32 -MemNGetMR0WRLN ( - IN OUT MEM_NB_BLOCK *NBPtr - ); - -BOOLEAN -MemNOverridePrevPassRcvEnDlyLN ( - IN OUT MEM_NB_BLOCK *NBPtr, - IN OUT VOID *PrevPassRcvEnDly - ); - -#endif /* _MNLN_H_ */ - - diff --git a/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/LN/mnmctln.c b/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/LN/mnmctln.c deleted file mode 100644 index e36bd96919..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/LN/mnmctln.c +++ /dev/null @@ -1,287 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * mnmctln.c - * - * Northbridge LN MCT supporting functions - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: (Mem/NB/LN) - * @e \$Revision: 46486 $ @e \$Date: 2011-02-04 00:58:37 +0800 (Fri, 04 Feb 2011) $ - * - **/ -/***************************************************************************** -* -* Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* *************************************************************************** -* -*/ - -/* - *---------------------------------------------------------------------------- - * MODULES USED - * - *---------------------------------------------------------------------------- - */ - - - -#include "AGESA.h" -#include "amdlib.h" -#include "Ids.h" -#include "mm.h" -#include "mn.h" -#include "OptionMemory.h" // need def for MEM_FEAT_BLOCK_NB -#include "cpuFeatures.h" -#include "mnln.h" -#include "Filecode.h" -CODE_GROUP (G1_PEICC) -RDATA_GROUP (G1_PEICC) - -#define FILECODE PROC_MEM_NB_LN_MNMCTLN_FILECODE -/*---------------------------------------------------------------------------- - * DEFINITIONS AND MACROS - * - *---------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------- - * TYPEDEFS AND STRUCTURES - * - *---------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------- - * PROTOTYPES OF LOCAL FUNCTIONS - * - *---------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------- - * EXPORTED FUNCTIONS - * - *---------------------------------------------------------------------------- - */ -/* -----------------------------------------------------------------------------*/ -/** - * - * This function create the HT memory map - * - * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK - * - * @return TRUE - No fatal error occurs. - * @return FALSE - Fatal error occurs. - */ - -BOOLEAN -MemNHtMemMapInitLN ( - IN OUT MEM_NB_BLOCK *NBPtr - ) -{ - UINT8 WeReMask; - UINT32 BottomIo; - UINT32 HoleOffset; - UINT32 DctSelBaseAddr; - UINT32 NodeSysBase; - UINT32 NodeSysLimit; - MEM_PARAMETER_STRUCT *RefPtr; - DIE_STRUCT *MCTPtr; - - RefPtr = NBPtr->RefPtr; - MCTPtr = NBPtr->MCTPtr; - // - // Physical addresses in this function are right adjusted by 16 bits ([47:16]) - // They are BottomIO, HoleOffset, DctSelBaseAddr, NodeSysBase, NodeSysLimit. - // - - // Enforce bottom of IO be be 128MB aligned - BottomIo = (RefPtr->BottomIo & 0xF8) << 8; - - if (MCTPtr->NodeMemSize != 0) { - NodeSysBase = 0; - NodeSysLimit = MCTPtr->NodeMemSize - 1; - DctSelBaseAddr = MCTPtr->DctData[0].Timings.DctMemSize; - - if (NodeSysLimit >= BottomIo) { - // HW Dram Remap - MCTPtr->Status[SbHWHole] = TRUE; - RefPtr->GStatus[GsbHWHole] = TRUE; - MCTPtr->NodeHoleBase = BottomIo; - RefPtr->HoleBase = BottomIo; - - HoleOffset = _4GB_RJ16 - BottomIo; - - NodeSysLimit += HoleOffset; - - if ((DctSelBaseAddr > 0) && (DctSelBaseAddr < BottomIo)) { - HoleOffset += DctSelBaseAddr; - } else { - if (DctSelBaseAddr > BottomIo) { - DctSelBaseAddr += HoleOffset; - } - HoleOffset += NodeSysBase; - } - - MemNSetBitFieldNb (NBPtr, BFDramHoleBase, BottomIo >> 8); - MemNSetBitFieldNb (NBPtr, BFDramHoleOffset, HoleOffset >> 7); - MemNSetBitFieldNb (NBPtr, BFDramHoleValid, 1); - - } else { - // No Remapping. Normal Contiguous mapping - } - MCTPtr->NodeSysBase = NodeSysBase; - MCTPtr->NodeSysLimit = NodeSysLimit; - RefPtr->SysLimit = MCTPtr->NodeSysLimit; - - WeReMask = 3; - // Set the Dram base and set the WE and RE flags in the base. - MemNSetBitFieldNb (NBPtr, BFDramBaseReg0, (NodeSysBase << 8) | WeReMask); - // Set the Dram limit and set DstNode. - MemNSetBitFieldNb (NBPtr, BFDramLimitReg0, ((NodeSysLimit << 8) & 0xFFFF0000)); - - if ((MCTPtr->DctData[1].Timings.DctMemSize != 0) && (!NBPtr->Ganged)) { - MemNSetBitFieldNb (NBPtr, BFDctSelBaseAddr, DctSelBaseAddr >> 11); - MemNSetBitFieldNb (NBPtr, BFDctSelHiRngEn, 1); - MemNSetBitFieldNb (NBPtr, BFDctSelHi, 1); - MemNSetBitFieldNb (NBPtr, BFDctSelBaseOffset, DctSelBaseAddr >> 10); - } - } - return (BOOLEAN) (NBPtr->MCTPtr->ErrCode < AGESA_FATAL); -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * - * Report the Uma size that is going to be allocated. - * Total system memory UMASize - * >= 2G 512M - * >=1G 256M - * <1G 64M - * - * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK - * - * @return Uma size [31:0] = Addr [47:16] - */ -UINT32 -MemNGetUmaSizeLN ( - IN OUT MEM_NB_BLOCK *NBPtr - ) -{ - UINT32 SysMemSize; - UINT32 SizeOfUma; - - SysMemSize = NBPtr->RefPtr->SysLimit + 1; - SysMemSize = (SysMemSize + 0x100) & 0xFFFFF000; // Ignore 16MB allocated for C6 when finding UMA size - if (SysMemSize >= 0x8000) { - SizeOfUma = 512 << (20 - 16); - } else if (SysMemSize >= 0x4000) { - SizeOfUma = 256 << (20 - 16); - } else { - SizeOfUma = 64 << (20 - 16); - } - - return SizeOfUma; -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * - * This function programs memory prefetch and priority control - * - * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK - * - * @return TRUE - No fatal error occurs. - * @return FALSE - Fatal error occurs. - */ - -BOOLEAN -MemNFinalizeMctLN ( - IN OUT MEM_NB_BLOCK *NBPtr - ) -{ - UINT32 MctCfgLoReg; - UINT32 MctCfgHiReg; - UINT8 Dct; - - // To support ODTS, with assumption that Tref is set to 7.8us always in AGESA - MemNSwitchDCTNb (NBPtr, 0); - MemNSetBitFieldNb (NBPtr, BFDoubleTrefRateEn, 1); - - // Program memory read/write priority - MctCfgLoReg = MemNGetBitFieldNb (NBPtr, BFMctCfgLoReg); - MemNSetBitFieldNb (NBPtr, BFMctCfgLoReg, (MctCfgLoReg & 0xFFFFF000) | 0x04A4); - - // Program memory prefetching - MctCfgHiReg = MemNGetBitFieldNb (NBPtr, BFMctCfgHiReg); - MemNSetBitFieldNb (NBPtr, BFMctCfgHiReg, (MctCfgHiReg & 0x9E33AF83) | 0x00404070); - - // DRAM self-refresh - MemNSetBitFieldNb (NBPtr, BFDramSrEn, 1); - MemNSetBitFieldNb (NBPtr, BFDramSrHys, 5); - if (NBPtr->IsSupported[DramSrHys]) { - MemNSetBitFieldNb (NBPtr, BFDramSrHysEn, 1); - } - - MemNSetBitFieldNb (NBPtr, BFMemTriStateEn, 1); - MemNSetBitFieldNb (NBPtr, BFAcpiPwrStsCtrlHi, MemNGetBitFieldNb (NBPtr, BFAcpiPwrStsCtrlHi) | 0x00060006); - - for (Dct = 0; Dct < MAX_DCTS_PER_NODE_LN; Dct++) { - MemNSwitchDCTNb (NBPtr, Dct); - if (NBPtr->DCTPtr->Timings.DctMemSize != 0) { - // PchgPdTxCClkGateDis is 0 by default - // Set SelCsrPllPdMode and CsrPhySrPllPdMode: - MemNSetBitFieldNb (NBPtr, BFPllPdMode, 0x6000); - // SkewMemClk is 0 by default - - // Phy Power Saving - MemNPhyPowerSavingClientNb (NBPtr); - } - } - - // Set NclkRampWithDllRelock=1 - MemNSetBitFieldNb (NBPtr, BFNclkRampWithDllRelock, 1); - - // Release NB P-state force - MemNSetBitFieldNb (NBPtr, BFNbPsCtrlDis, 0); - MemNSetBitFieldNb (NBPtr, BFNbPsForceReq, 0); - - // Set C6DramLock - if (IsFeatureEnabled (C6Cstate, NBPtr->MemPtr->PlatFormConfig, &(NBPtr->MemPtr->StdHeader))) { - MemNSetBitFieldNb (NBPtr, BFC6DramLock, 1); - } - - return (BOOLEAN) (NBPtr->MCTPtr->ErrCode < AGESA_FATAL); -} - -/*---------------------------------------------------------------------------- - * LOCAL FUNCTIONS - * - *---------------------------------------------------------------------------- - */ diff --git a/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/LN/mnotln.c b/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/LN/mnotln.c deleted file mode 100644 index ded05e4665..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/LN/mnotln.c +++ /dev/null @@ -1,206 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * mnotln.c - * - * Northbridge Non-SPD timings for LN - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: (Mem/NB/LN) - * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $ - * - **/ -/***************************************************************************** -* -* Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* *************************************************************************** -* -*/ - -/* - *---------------------------------------------------------------------------- - * MODULES USED - * - *---------------------------------------------------------------------------- - */ - - - -#include "AGESA.h" -#include "Ids.h" -#include "mm.h" -#include "mn.h" -#include "OptionMemory.h" // need def for MEM_FEAT_BLOCK_NB -#include "mnln.h" -#include "mu.h" -#include "Filecode.h" -CODE_GROUP (G1_PEICC) -RDATA_GROUP (G1_PEICC) - -#define FILECODE PROC_MEM_NB_LN_MNOTLN_FILECODE - - -/*---------------------------------------------------------------------------- - * DEFINITIONS AND MACROS - * - *---------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------- - * TYPEDEFS AND STRUCTURES - * - *---------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------- - * PROTOTYPES OF LOCAL FUNCTIONS - * - *---------------------------------------------------------------------------- - */ -VOID -STATIC -MemNPowerDownCtlLN ( - IN OUT MEM_NB_BLOCK *NBPtr - ); - -/*---------------------------------------------------------------------------- - * EXPORTED FUNCTIONS - * - *---------------------------------------------------------------------------- - */ - -/* -----------------------------------------------------------------------------*/ -/** - * - * This function sets the non-SPD timings - * - * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK - * - * @return TRUE - No fatal error occurs. - * @return FALSE - Fatal error occurs. - */ - -BOOLEAN -MemNOtherTimingLN ( - IN OUT MEM_NB_BLOCK *NBPtr - ) -{ - UINT8 Dct; - INT16 WOD; - INT16 ROD; - UINT8 LD; - UINT8 Tcwl; - INT16 CDDTrdrd; - INT16 CDDTwrwr; - INT16 CDDTwrrdSD; - INT16 CDDTwrrd; - INT16 CDDTrwtTO; - INT16 Trdrd; - INT16 Twrwr; - INT16 TwrrdSD; - INT16 Twrrd; - INT16 TrwtTO; - - for (Dct = 0; Dct < MAX_DCTS_PER_NODE_LN; Dct++) { - MemNSwitchDCTNb (NBPtr, Dct); - if (NBPtr->DCTPtr->Timings.DctDimmValid > 0) { - // Enable power down - MemNPowerDownCtlLN (NBPtr); - - // Calculate needed terms - ROD = DEFAULT_RD_ODT_ON_LN - 6; - WOD = DEFAULT_WR_ODT_ON_LN - 6; - Tcwl = (UINT8) (NBPtr->DCTPtr->Timings.Speed / 133) + 2; - LD = NBPtr->DCTPtr->Timings.CasL - Tcwl; - CDDTrdrd = (MemNCalcCDDNb (NBPtr, AccessRcvEnDly, AccessRcvEnDly, FALSE, TRUE) + 1 + 1) / 2; // +0.5 CLK - CDDTwrwr = (MemNCalcCDDNb (NBPtr, AccessWrDqsDly, AccessWrDqsDly, FALSE, TRUE) + 1 + 1) / 2; // +0.5 CLK - CDDTwrrdSD = (MemNCalcCDDNb (NBPtr, AccessWrDqsDly, AccessRcvEnDly, TRUE, FALSE) + 1 + 1) / 2; // +0.5 CLK - CDDTwrrd = (MemNCalcCDDNb (NBPtr, AccessWrDqsDly, AccessRcvEnDly, FALSE, TRUE) + 1 + 1) / 2; // +0.5 CLK - CDDTrwtTO = (MemNCalcCDDNb (NBPtr, AccessRcvEnDly, AccessWrDqsDly, TRUE, TRUE) - 1 + 1) / 2; // -0.5 CLK - - // Program non-SPD timings - MemNSetBitFieldNb (NBPtr, BFTrdrdSD, 3 - 2); - Trdrd = MAX (ROD, CDDTrdrd) + 3; - ASSERT (Trdrd <= 10); - MemNSetBitFieldNb (NBPtr, BFTrdrd, (UINT8) (Trdrd - 2)); - // Twrwr and TwrwrSD - MemNSetBitFieldNb (NBPtr, BFTwrwrSD, WOD + 3 - 1); - Twrwr = MAX (WOD + 3, CDDTwrwr + 3); - ASSERT (Twrwr <= 10); - MemNSetBitFieldNb (NBPtr, BFTwrwr, (UINT8) (Twrwr - 1)); - // Twrrd and TwrrdSD - TwrrdSD = MAX (1, MAX (WOD, CDDTwrrdSD) - LD + 3); - ASSERT (TwrrdSD <= 11); - MemNSetBitFieldNb (NBPtr, BFTwrrdSD, (UINT8) (TwrrdSD - 1)); - Twrrd = MAX (TwrrdSD, MAX (WOD, CDDTwrrd) - LD + 3); - ASSERT (Twrrd <= 11); - MemNSetBitFieldNb (NBPtr, BFTwrrd, (UINT8) (Twrrd - 1)); - // TrwtTO and TrwtWB - TrwtTO = MAX (ROD, CDDTrwtTO) + LD + 3; - ASSERT (TrwtTO <= 17); - MemNSetBitFieldNb (NBPtr, BFTrwtTO, (UINT8) (TrwtTO - 2)); - MemNSetBitFieldNb (NBPtr, BFTrwtWB, 0x4); - } - } - - return (BOOLEAN) (NBPtr->MCTPtr->ErrCode < AGESA_FATAL); -} - -/*---------------------------------------------------------------------------- - * LOCAL FUNCTIONS - * - *---------------------------------------------------------------------------- - */ - -/* -----------------------------------------------------------------------------*/ -/** - * - * This function enables power down mode - * - * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK - * - */ - -VOID -STATIC -MemNPowerDownCtlLN ( - IN OUT MEM_NB_BLOCK *NBPtr - ) -{ - if (NBPtr->RefPtr->EnablePowerDown) { - MemNSetTxpNb (NBPtr); - MemNSetBitFieldNb (NBPtr, BFPowerDownEn, 1); - } - - if (NBPtr->RefPtr->EnableBankSwizzle) { - MemNSetBitFieldNb (NBPtr, BFBankSwizzleMode, 1); - } -} - - - diff --git a/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/LN/mnphyln.c b/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/LN/mnphyln.c deleted file mode 100644 index 766b44467e..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/LN/mnphyln.c +++ /dev/null @@ -1,213 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * mnphyln.c - * - * Northbridge Phy support for LN - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: (Mem/NB/LN) - * @e \$Revision: 48400 $ @e \$Date: 2011-03-08 16:28:12 +0800 (Tue, 08 Mar 2011) $ - * - **/ -/***************************************************************************** -* -* Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* *************************************************************************** -* -*/ - - -/* - *---------------------------------------------------------------------------- - * MODULES USED - * - *---------------------------------------------------------------------------- - */ - - - -#include "AGESA.h" -#include "amdlib.h" -#include "Ids.h" -#include "mm.h" -#include "mn.h" -#include "mt.h" -#include "mu.h" -#include "merrhdl.h" -#include "OptionMemory.h" // need def for MEM_FEAT_BLOCK_NB -#include "mnln.h" -#include "Filecode.h" -CODE_GROUP (G1_PEICC) -RDATA_GROUP (G1_PEICC) - -#define FILECODE PROC_MEM_NB_LN_MNPHYLN_FILECODE -/*---------------------------------------------------------------------------- - * DEFINITIONS AND MACROS - * - *---------------------------------------------------------------------------- - */ -#define MAX_CS_PER_CHANNEL_LN 4 - -/*---------------------------------------------------------------------------- - * TYPEDEFS AND STRUCTURES - * - *---------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------- - * PROTOTYPES OF LOCAL FUNCTIONS - * - *---------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------- - * EXPORTED FUNCTIONS - * - *---------------------------------------------------------------------------- - */ - -/* -----------------------------------------------------------------------------*/ -/** - * - * - * This is a general purpose function that executes before DRAM training - * - * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK - * - */ - -VOID -MemNBeforeDQSTrainingLN ( - IN OUT MEM_NB_BLOCK *NBPtr - ) -{ - UINT8 Dct; - - MemTBeginTraining (NBPtr->TechPtr); - - for (Dct = 0; Dct < MAX_DCTS_PER_NODE_LN; Dct++) { - MemNSwitchDCTNb (NBPtr, Dct); - if (NBPtr->DCTPtr->Timings.DctMemSize != 0) { - MemNSetBitFieldNb (NBPtr, BFDisAutoRefresh, 1); - MemNSetBitFieldNb (NBPtr, BFZqcsInterval, 0); - - MemNSetBitFieldNb (NBPtr, BFRxMaxDurDllNoLock, 0); - MemNSetBitFieldNb (NBPtr, BFTxMaxDurDllNoLock, 0); - MemNSetBitFieldNb (NBPtr, BFEnRxPadStandby, 0); - - // Enable cut through mode for NB P0 - MemNSetBitFieldNb (NBPtr, BFDisCutThroughMode, 0); - - MemNSetBitFieldNb (NBPtr, BFMaxLatency, 0x12); - } - MemNSetBitFieldNb (NBPtr, BFTraceModeEn, 0); - } - - MemNSetBitFieldNb (NBPtr, BFPrefCpuDis, 1); - MemNSetBitFieldNb (NBPtr, BFDctWrLimit, 0x1F); - - MemNSetBitFieldNb (NBPtr, BFEnCpuSerRdBehindNpIoWr, 1); // #158498 - - MemTEndTraining (NBPtr->TechPtr); -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * - * This is a general purpose function that executes after DRAM training - * - * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK - * - */ - -VOID -MemNAfterDQSTrainingLN ( - IN OUT MEM_NB_BLOCK *NBPtr - ) -{ - UINT8 Dct; - for (Dct = 0; Dct < MAX_DCTS_PER_NODE_LN; Dct++) { - MemNSwitchDCTNb (NBPtr, Dct); - if (NBPtr->DCTPtr->Timings.DctMemSize != 0) { - MemNSetBitFieldNb (NBPtr, BFDisAutoRefresh, 0); - MemNSetBitFieldNb (NBPtr, BFZqcsInterval, 2); - - MemNSetBitFieldNb (NBPtr, BFAddrCmdTriEn, 1); - } - } - - MemNSetBitFieldNb (NBPtr, BFPrefCpuDis, 0); - MemNSetBitFieldNb (NBPtr, BFDctWrLimit, 0x1C); - MemNSetBitFieldNb (NBPtr, BFDramTrainPdbDis, 1); - - MemNSetBitFieldNb (NBPtr, BFEnCpuSerRdBehindNpIoWr, 0); -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * This function returns the number of chipselects per channel of Llano. - * - * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK - * - * @return - */ - -UINT8 -MemNCSPerChannelLN ( - IN OUT MEM_NB_BLOCK *NBPtr - ) -{ - return MAX_CS_PER_CHANNEL_LN; -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * This function overrides the seed for Pass N hardware based RcvEn training of UNB. - * - * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK - * @param[in,out] *PrevPassRcvEnDly - Pointer to the PrevPassRcvEnDly - * - * @return TRUE - */ - -BOOLEAN -MemNOverridePrevPassRcvEnDlyLN ( - IN OUT MEM_NB_BLOCK *NBPtr, - IN OUT VOID *PrevPassRcvEnDly - ) -{ - if ((*(UINT16*)PrevPassRcvEnDly) < 0x20) { - *(UINT16*)PrevPassRcvEnDly += 0x40; - } - return TRUE; -} - diff --git a/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/LN/mnprotoln.c b/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/LN/mnprotoln.c deleted file mode 100644 index b0fc19d06f..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/LN/mnprotoln.c +++ /dev/null @@ -1,210 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * mnprotoln.c - * - * Northbridge support functions for Errata and early samples - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: (Mem/NB/LN) - * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $ - * - **/ -/***************************************************************************** -* -* Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* *************************************************************************** -* -*/ - - - -#include "AGESA.h" -#include "mm.h" -#include "mn.h" -#include "cpuRegisters.h" -#include "Filecode.h" -CODE_GROUP (G1_PEICC) -RDATA_GROUP (G1_PEICC) - -#define FILECODE PROC_MEM_NB_LN_MNPROTOLN_FILECODE - -/*---------------------------------------------------------------------------- - * PROTOTYPES OF LOCAL FUNCTIONS - * - *---------------------------------------------------------------------------- - */ -VOID -MemNInitEarlySampleSupportLN ( - IN OUT MEM_NB_BLOCK *NBPtr - ); - -BOOLEAN -STATIC -MemNAfterMemClkFreqValLN ( - IN OUT MEM_NB_BLOCK *NBPtr, - IN OUT VOID *OptParam - ); - -BOOLEAN -STATIC -MemNOverridePllMultValueLN ( - IN OUT MEM_NB_BLOCK *NBPtr, - IN OUT VOID *PllMult - ); - -BOOLEAN -STATIC -MemNOverridePllDivValueLN ( - IN OUT MEM_NB_BLOCK *NBPtr, - IN OUT VOID *PllDiv - ); - -/* - *----------------------------------------------------------------------------- - * EXPORTED FUNCTIONS - * - *----------------------------------------------------------------------------- - */ -CONST UINT8 PllDivOverrideTab[] = {0, 0, 0, 6, 4, 3, 3, 3}; -CONST UINT8 PllMultOverrideTab[] = {0, 0, 0, 48, 42, 40, 48, 56}; - -/* -----------------------------------------------------------------------------*/ -/** - * - * This function initializes early sample support for Llano - * - * @param[in,out] NBPtr - Pointer to the MEM_NB_BLOCK - * - */ -VOID -MemNInitEarlySampleSupportLN ( - IN OUT MEM_NB_BLOCK *NBPtr - ) -{ - if ((NBPtr->MCTPtr->LogicalCpuid.Revision & AMD_F12_LN_A0) != 0) { - if (MemNGetBitFieldNb (NBPtr, BFErratum468WorkaroundNotRequired) == 0) { - NBPtr->FamilySpecificHook[AfterMemClkFreqVal] = MemNAfterMemClkFreqValLN; - NBPtr->FamilySpecificHook[OverridePllMult] = MemNOverridePllMultValueLN; - NBPtr->FamilySpecificHook[OverridePllDiv] = MemNOverridePllDivValueLN; - } - } - - if ((NBPtr->MCTPtr->LogicalCpuid.Revision & (AMD_F12_LN_A0 | AMD_F12_LN_A1)) != 0) { - NBPtr->NBRegTable[BFDoubleTrefRateEn] = 0; // Erratum 445 - NBPtr->IsSupported[AdjustTwr] = TRUE; // Erratum 434 - NBPtr->IsSupported[ChannelPDMode] = TRUE; // Erratum 435 - NBPtr->NBRegTable[BFLowPowerDrvStrengthEn] = 0; - NBPtr->IsSupported[SkipErrTrain] = FALSE; // Rev A does not support skip error training - NBPtr->IsSupported[DramSrHys] = FALSE; // UBTS 233978 - NBPtr->IsSupported[SchedDlySlot1Extra] = FALSE; // UBTS 244062 - NBPtr->IsSupported[ExtraPclkInMaxRdLat] = TRUE; // UBTS 185210 - NBPtr->IsSupported[AdjustTrc] = FALSE; - } -} - -/*---------------------------------------------------------------------------- - * LOCAL FUNCTIONS - * - *---------------------------------------------------------------------------- - */ - -/*----------------------------------------------------------------------------- - * - * - * This function overrides PllMult and PllDiv bitfields - * - * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK - * @param[in,out] OptParam - Optional parameter - * - * @return TRUE - * ---------------------------------------------------------------------------- - */ -BOOLEAN -STATIC -MemNAfterMemClkFreqValLN ( - IN OUT MEM_NB_BLOCK *NBPtr, - IN OUT VOID *OptParam - ) -{ - // BIOS needs to override PllMult and PllDiv as follow: - // DDR800 48 / 6 - // DDR1066 42 / 5 - // DDR1333 no override - // DDR1600 48 / 3 - if ((NBPtr->DCTPtr->Timings.Speed != DDR1333_FREQUENCY) && (NBPtr->DCTPtr->Timings.Speed != DDR1866_FREQUENCY)) { - MemNBrdcstSetNb (NBPtr, BFDramPhyCtlReg, (MemNGetBitFieldNb (NBPtr, BFDramPhyCtlReg) & 0x7FFF) | ( - (NBPtr->DCTPtr->Timings.Speed == DDR800_FREQUENCY) ? 0x09980000 : - (NBPtr->DCTPtr->Timings.Speed == DDR1066_FREQUENCY) ? 0x02950000 : 0x08980000)); - } - return TRUE; -} - -/*----------------------------------------------------------------------------- - * - * - * This function overrides PllMult variable - * - * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK - * @param[in,out] PllMult - PllMult parameter - * - * @return TRUE - * ---------------------------------------------------------------------------- - */ -BOOLEAN -STATIC -MemNOverridePllMultValueLN ( - IN OUT MEM_NB_BLOCK *NBPtr, - IN OUT VOID *PllMult - ) -{ - * (UINT8 *) PllMult = PllMultOverrideTab[NBPtr->DCTPtr->Timings.Speed / 133]; - return TRUE; -} - -/*----------------------------------------------------------------------------- - * - * - * This function overrides PllDiv variable - * - * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK - * @param[in,out] PllDiv - PllDiv parameter - * - * @return TRUE - * ---------------------------------------------------------------------------- - */ -BOOLEAN -STATIC -MemNOverridePllDivValueLN ( - IN OUT MEM_NB_BLOCK *NBPtr, - IN OUT VOID *PllDiv - ) -{ - * (UINT8 *) PllDiv = PllDivOverrideTab[NBPtr->DCTPtr->Timings.Speed / 133]; - return TRUE; -} diff --git a/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/LN/mnregln.c b/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/LN/mnregln.c deleted file mode 100644 index 607fce0ec2..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/LN/mnregln.c +++ /dev/null @@ -1,608 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * mnregln.c - * - * Common Northbridge register related functions for LN - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: (Mem/NB/LN) - * @e \$Revision: 47676 $ @e \$Date: 2011-02-25 06:29:57 +0800 (Fri, 25 Feb 2011) $ - * - **/ -/***************************************************************************** -* -* Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* *************************************************************************** -* -*/ -/* - *---------------------------------------------------------------------------- - * MODULES USED - * - *---------------------------------------------------------------------------- - */ - - - -#include "AGESA.h" -#include "AdvancedApi.h" -#include "amdlib.h" -#include "Ids.h" -#include "OptionMemory.h" -#include "mm.h" -#include "mn.h" -#include "mnln.h" -#include "merrhdl.h" -#include "cpuRegisters.h" -#include "cpuFamRegisters.h" -#include "cpuFamilyTranslation.h" -#include "heapManager.h" -#include "Filecode.h" -CODE_GROUP (G1_PEICC) -RDATA_GROUP (G1_PEICC) - -#define FILECODE PROC_MEM_NB_LN_MNREGLN_FILECODE -/*---------------------------------------------------------------------------- - * DEFINITIONS AND MACROS - * - *---------------------------------------------------------------------------- - */ -#define PHY_DIRECT_ADDRESS_MASK 0x0D000000 - -STATIC CONST UINT8 InstancesPerTypeLN[8] = {8, 2, 1, 0, 2, 0, 1, 1}; - -/*---------------------------------------------------------------------------- - * TYPEDEFS AND STRUCTURES - * - *---------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------- - * PROTOTYPES OF LOCAL FUNCTIONS - * - *---------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------- - * EXPORTED FUNCTIONS - * - *---------------------------------------------------------------------------- - */ -/*-----------------------------------------------------------------------------*/ -/** - * - * This function matches the CPU_LOGICAL_ID with certain criteria to - * determine if it is supported by this NBBlock. - * - * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK - * @param[in] *LogicalIdPtr - Pointer to the CPU_LOGICAL_ID - * - * @return TRUE - This node is a Llano. - * @return FALSE - This node is not a Llano. - */ -BOOLEAN -MemNIsIdSupportedLN ( - IN OUT MEM_NB_BLOCK *NBPtr, - IN CPU_LOGICAL_ID *LogicalIdPtr - ) -{ - if (((LogicalIdPtr->Family & AMD_FAMILY_12_LN) != 0) - && ((LogicalIdPtr->Revision & (UINT64) AMD_F12_ALL) != 0)) { - return TRUE; - } else { - return FALSE; - } -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * - * This function gets or sets a value to a bit field in a PCI register. - * - * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK - * @param[in] FieldName - Bit Field to be programmed - * @param[in] Field - Value to be programmed - * @param[in] IsSet - Indicates if the function will set or get - * - * @return value read, if the function is used as a "get" - */ - -UINT32 -MemNCmnGetSetFieldLN ( - IN OUT MEM_NB_BLOCK *NBPtr, - IN UINT8 IsSet, - IN BIT_FIELD_NAME FieldName, - IN UINT32 Field - ) -{ - TSEFO Address; - PCI_ADDR PciAddr; - UINT8 Type; - UINT8 IsLinked; - UINT32 Value; - UINT32 Highbit; - UINT32 Lowbit; - UINT32 Mask; - UINT8 IsPhyDirectAccess; - UINT8 IsWholeRegAccess; - UINT8 NumOfInstances; - UINT8 Instance; - - Value = 0; - if (FieldName == BFDctAccessDone) { - // Llano does not support DctAccessDone. Assume DctAccessDone=1 always. - Value = 1; - } else if (FieldName < BFEndOfList) { - Address = NBPtr->NBRegTable[FieldName]; - if (Address) { - Lowbit = TSEFO_END (Address); - Highbit = TSEFO_START (Address); - Type = (UINT8) TSEFO_TYPE (Address); - IsLinked = (UINT8) TSEFO_LINKED (Address); - IsPhyDirectAccess = (UINT8) TSEFO_DIRECT_EN (Address); - IsWholeRegAccess = (UINT8) TSEFO_WHOLE_REG_ACCESS (Address); - - // If Fn2 and DCT1 selected, set Address to be 1xx - if ((Type == NB_ACCESS) && ((Address & 0xF000) == 0x2000) && NBPtr->Dct) { - Address |= 0x0100; - } - - ASSERT ((Address & ((UINT32) 1) << 29) == 0); // Old Phy direct access method is not supported - - Address = TSEFO_OFFSET (Address); - - // By default, a bit field has only one instance - NumOfInstances = 1; - - if ((Type == DCT_PHY_ACCESS) && IsPhyDirectAccess) { - Address |= PHY_DIRECT_ADDRESS_MASK; - if (IsWholeRegAccess) { - // In the case of whole regiter access (bit 0 to 15), - // HW broadcast and nibble mask will be used. - Address |= Lowbit << 16; - Lowbit = 0; - Highbit = 15; - } else { - // In the case only some bits on a register is accessed, - // BIOS will do read-mod-write to all chiplets manually. - // And nibble mask will be 1111b always. - Address |= 0x000F0000; - Field >>= Lowbit; - if ((Address & 0x0F00) == 0x0F00) { - // Broadcast mode - // Find out how many instances to write to - NumOfInstances = InstancesPerTypeLN[(Address >> 13) & 0x7]; - if (!IsSet) { - // For read, only read from instance 0 in broadcast mode - NumOfInstances = 1; - } - } - } - } - - ASSERT (NumOfInstances > 0); - - for (Instance = 0; Instance < NumOfInstances; Instance++) { - if (Type == NB_ACCESS) { - PciAddr.AddressValue = Address; - PciAddr.Address.Device = NBPtr->PciAddr.Address.Device; - PciAddr.Address.Bus = NBPtr->PciAddr.Address.Bus; - PciAddr.Address.Segment = NBPtr->PciAddr.Address.Segment; - Address = PciAddr.AddressValue; - LibAmdPciRead (AccessWidth32, PciAddr, &Value, &NBPtr->MemPtr->StdHeader); - if ((FieldName != BFDctAddlDataReg) && (FieldName != BFDctAddlOffsetReg) && - (FieldName != BFDctExtraDataReg) && (FieldName != BFDctExtraOffsetReg)) { - IDS_HDT_CONSOLE (MEM_GETREG, "~Fn%d_%03x = %x\n", (Address >> 12) & 0x7, Address & 0xFFF, Value); - } - } else if (Type == DCT_PHY_ACCESS) { - if (IsPhyDirectAccess && (NumOfInstances > 1)) { - Address = (Address & 0x0FFFF0FF) | (((UINT32) Instance) << 8); - } - MemNSetBitFieldNb (NBPtr, BFDctAddlOffsetReg, Address); - Value = MemNGetBitFieldNb (NBPtr, BFDctAddlDataReg); - IDS_HDT_CONSOLE (MEM_GETREG, "~Fn2_%d9C_%x = %x\n", NBPtr->Dct, Address & 0x0FFFFFFF, Value); - } else if (Type == DCT_EXTRA) { - MemNSetBitFieldNb (NBPtr, BFDctExtraOffsetReg, Address); - Value = MemNGetBitFieldNb (NBPtr, BFDctExtraDataReg); - IDS_HDT_CONSOLE (MEM_GETREG, "~Fn2_%dF4_%x = %x\n", NBPtr->Dct, Address & 0x0FFFFFFF, Value); - } else { - IDS_ERROR_TRAP; - } - - if (IsSet) { - // A 1<<32 == 1<<0 due to x86 SHL instruction, so skip if that is the case - if ((Highbit - Lowbit) != 31) { - Mask = (((UINT32)1 << (Highbit - Lowbit + 1)) - 1); - } else { - Mask = (UINT32)0xFFFFFFFF; - } - Value &= ~(Mask << Lowbit); - Value |= (Field & Mask) << Lowbit; - - if (Type == NB_ACCESS) { - PciAddr.AddressValue = Address; - LibAmdPciWrite (AccessWidth32, PciAddr, &Value, &NBPtr->MemPtr->StdHeader); - if ((FieldName != BFDctAddlDataReg) && (FieldName != BFDctAddlOffsetReg) && - (FieldName != BFDctExtraDataReg) && (FieldName != BFDctExtraOffsetReg)) { - IDS_HDT_CONSOLE (MEM_SETREG, "~Fn%d_%03x [%d:%d] = %x\n", (Address >> 12) & 0x7, Address & 0xFFF, Highbit, Lowbit, Field); - } - } else if (Type == DCT_PHY_ACCESS) { - MemNSetBitFieldNb (NBPtr, BFDctAddlDataReg, Value); - Address |= DCT_ACCESS_WRITE; - MemNSetBitFieldNb (NBPtr, BFDctAddlOffsetReg, Address); - IDS_HDT_CONSOLE (MEM_SETREG, "~Fn2_%d9C_%x [%d:%d] = %x\n", NBPtr->Dct, Address & 0x0FFFFFFF, Highbit, Lowbit, Field); - } else if (Type == DCT_EXTRA) { - MemNSetBitFieldNb (NBPtr, BFDctExtraDataReg, Value); - Address |= DCT_ACCESS_WRITE; - MemNSetBitFieldNb (NBPtr, BFDctExtraOffsetReg, Address); - IDS_HDT_CONSOLE (MEM_SETREG, "~Fn2_%dF4_%x [%d:%d] = %x\n", NBPtr->Dct, Address & 0x0FFFFFFF, Highbit, Lowbit, Field); - } else { - IDS_ERROR_TRAP; - } - if (IsLinked) { - MemNCmnGetSetFieldLN (NBPtr, 1, FieldName + 1, Field >> (Highbit - Lowbit + 1)); - } - } else { - Value = Value >> Lowbit; // Shift - // A 1<<32 == 1<<0 due to x86 SHL instruction, so skip if that is the case - if ((Highbit - Lowbit) != 31) { - Value &= (((UINT32)1 << (Highbit - Lowbit + 1)) - 1); - } - if (IsLinked) { - Value |= MemNCmnGetSetFieldLN (NBPtr, 0, FieldName + 1, 0) << (Highbit - Lowbit + 1); - } - // For direct phy access, shift the bit back for compatibility reason. - if ((Type == DCT_PHY_ACCESS) && IsPhyDirectAccess) { - Value <<= Lowbit; - } - } - } - } - } else { - IDS_ERROR_TRAP; // Invalid bit field index - } - return Value; -} - - -/* -----------------------------------------------------------------------------*/ -/** - * - * This function initializes bit field translation table - * - * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK - * @param[in,out] NBRegTable[] - Pointer to the bit field data structure - * - */ - -VOID -MemNInitNBRegTableLN ( - IN OUT MEM_NB_BLOCK *NBPtr, - IN OUT TSEFO NBRegTable[] - ) -{ - UINT16 i; - - // Allocate heap for NB register table - if (!MemNAllocateNBRegTableNb (NBPtr, NbRegTabLN)) { - return; // escape if fails - } - NBRegTable = NBPtr->NBRegTable; - - for (i = 0; i < BFEndOfList; i++) { - NBRegTable[i] = 0; - } - - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (0, 0x00), 31, 0, BFDevVendorIDReg); - - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x40), 31, 0, BFDramBaseReg0); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x44), 31, 0, BFDramLimitReg0); - - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0xF0), 31, 24, BFDramHoleBase); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0xF0), 15, 7, BFDramHoleOffset); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0xF0), 0, 0, BFDramHoleValid); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0xF0), 31, 0, BFDramHoleAddrReg); - - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x40), 31, 0, BFCSBaseAddr0Reg); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x44), 31, 0, BFCSBaseAddr1Reg); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x48), 31, 0, BFCSBaseAddr2Reg); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x4C), 31, 0, BFCSBaseAddr3Reg); - - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x60), 31, 0, BFCSMask0Reg); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x64), 31, 0, BFCSMask1Reg); - - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x78), 31, 0, BFDramControlReg); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x7C), 31, 0, BFDramInitRegReg); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x80), 31, 0, BFDramBankAddrReg); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x84), 31, 0, BFDramMRSReg); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x88), 31, 0, BFDramTimingLoReg); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x8C), 31, 0, BFDramTimingHiReg); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x90), 31, 0, BFDramConfigLoReg); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x94), 31, 0, BFDramConfigHiReg); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x98), 31, 0, BFDctAddlOffsetReg); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x9C), 31, 0, BFDctAddlDataReg); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0xA0), 31, 0, BFDramConfigMiscReg); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0xA8), 31, 0, BFDramCtrlMiscReg2); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0xF0), 31, 0, BFDctExtraOffsetReg); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0xF4), 31, 0, BFDctExtraDataReg); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x11C), 31, 0, BFMctCfgHiReg); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x118), 31, 0, BFMctCfgLoReg); - - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x78), 13, 8, BFNonSPDHi); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x78), 3, 0, BFRdPtrInit); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x78), 6, 6, BFRxPtrInitReq); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x78), 9, 8, BFTwrrdHi); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x78), 11, 10, BFTwrwrHi); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x78), 13, 12, BFTrdrdHi); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x78), 14, 14, BFSlot1ExtraClkEn); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x78), 15, 15, BFMaxSkipErrTrain); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x78), 17, 17, BFAddrCmdTriEn); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x78), 19, 19, BFSlotSel); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x78), 20, 20, BFForceCasToSlot0); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x78), 21, 21, BFDisCutThroughMode); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x78), 31, 22, BFMaxLatency); - - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x7C), 15, 0, BFMrsAddress); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x7C), 18, 16, BFMrsBank); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x7C), 22, 20, BFMrsChipSel); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x7C), 24, 24, BFSendPchgAll); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x7C), 25, 25, BFSendAutoRefresh); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x7C), 26, 26, BFSendMrsCmd); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x7C), 27, 27, BFDeassertMemRstX); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x7C), 28, 28, BFAssertCke); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x7C), 29, 29, BFSendZQCmd); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x7C), 31, 31, BFEnDramInit); - - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x84), 1, 0, BFBurstCtrl); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x84), 6, 4, BFTwrDDR3); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x84), 22, 20, BFTcwl); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x84), 23, 23, BFPchgPDModeSel); - - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x88), 3, 0, BFTcl); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x88), 31, 24, BFMemClkDis); - - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x8C), 15, 0, BFNonSPD); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x8C), 3, 0, BFTrwtWB); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x8C), 7, 4, BFTrwtTO); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x8C), 11, 10, BFTwrrd); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x8C), 13, 12, BFTwrwr); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x8C), 15, 14, BFTrdrd); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x8C), 17, 16, BFTref); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x8C), 18, 18, BFDisAutoRefresh); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x8C), 22, 20, BFTrfc0); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x8C), 25, 23, BFTrfc1); - - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x90), 0, 0, BFInitDram); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x90), 1, 1, BFExitSelfRef); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x90), 17, 17, BFEnterSelfRef); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x90), 22, 21, BFIdleCycInit); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x90), 25, 25, BFEnDispAutoPrecharge); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x90), 26, 26, BFDbeSkidBufDis); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x90), 27, 27, BFDisDllShutdownSR); - - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x94), 4, 0, BFMemClkFreq); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x94), 7, 7, BFMemClkFreqVal); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x94), 11, 10, BFZqcsInterval); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x94), 14, 14, BFDisDramInterface); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x94), 15, 15, BFPowerDownEn); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x94), 16, 16, BFPowerDownMode); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x94), 20, 20, BFSlowAccessMode); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x94), 22, 22, BFBankSwizzleMode); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x94), 27, 24, BFDcqBypassMax); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x94), 31, 28, BFFourActWindow); - - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0xA4), 0, 0, BFDoubleTrefRateEn); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0xA4), 2, 1, BFThrottleEn); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0xA8), 22, 21, BFDbeGskMemClkAlignMode); - - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0xC0), 0, 0, BFTraceModeEn); - - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x10C), 0, 0, BFIntlvRegionEn); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x10C), 7, 3, BFIntlvRegionBase); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x10C), 15, 11, BFIntlvRegionLimit); - - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x110), 0, 0, BFDctSelHiRngEn); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x110), 1, 1, BFDctSelHi); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x110), 2, 2, BFDctSelIntLvEn); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x110), 3, 3, BFMemClrInit); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x110), 7, 6, BFDctSelIntLvAddr); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x110), 8, 8, BFDramEnabled); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x110), 9, 9, BFMemClrBusy); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x110), 10, 10, BFMemCleared); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x110), 31, 11, BFDctSelBaseAddr); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x114), 9, 9, BFDctSelIntLvAddrHi); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x114), 31, 10, BFDctSelBaseOffset); - - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x118), 19, 19, BFC6DramLock); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x11C), 12, 12, BFPrefCpuDis); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x11C), 6, 2, BFDctWrLimit); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x1C0), 23, 23, BFRdTrainGo); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x1C0), 22, 22, BFRdDramTrainMode); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x1C0), 20, 20, BFDramTrainPdbDis); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x1C0), 17, 2, BFTrainLength); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x1C0), 1, 1, BFWrTrainGo); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x1C0), 0, 0, BFWrDramTrainMode); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x1C8), 31, 0, BFWrTrainAdrPtrLo); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x1CC), 17, 16, BFWrTrainAdrPtrHi); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x1D0), 9, 0, BFWrTrainBufAddr); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x1D4), 31, 0, BFWrTrainBufDat); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x1E8), 15, 8, BFTrainCmpSts2); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x1E8), 7, 0, BFTrainCmpSts); - - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (3, 0x84), 31, 0, BFAcpiPwrStsCtrlHi); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (3, 0xDC), 19, 19, BFNclkFreqDone); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (3, 0xD4), 5, 0, BFMainPllOpFreqId); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (3, 0xDC), 26, 20, BFNbPs0NclkDiv); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (3, 0xE8), 7, 5, BFDdrMaxRate); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (3, 0x188), 22, 22, BFEnCpuSerRdBehindNpIoWr); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (3, 0x1FC), 0, 0, BFErratum468WorkaroundNotRequired); - - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (4, 0x12C), 15, 0, BFC6Base); - - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (4, 0x1A8), 29, 29, BFDramSrHysEn); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (4, 0x1A8), 28, 26, BFDramSrHys); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (4, 0x1A8), 25, 25, BFMemTriStateEn); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (4, 0x1A8), 24, 24, BFDramSrEn); - - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (6, 0x90), 6, 0, BFNbPs1NclkDiv); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (6, 0x90), 28, 28, BFNbPsForceReq); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (6, 0x90), 30, 30, BFNbPsCtrlDis); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (6, 0x90), 31, 31, BFNbPsCap); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (6, 0x98), 30, 30, BFNbPsCsrAccSel); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (6, 0x98), 31, 31, BFNbPsDbgEn); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (6, 0x9C), 8, 8, BFNclkRampWithDllRelock); - - MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x00, 2, 0, BFCkeDrvStren); - MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x00, 6, 4, BFCsOdtDrvStren); - MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x00, 10, 8, BFAddrCmdDrvStren); - MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x00, 14, 12, BFClkDrvStren); - MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x00, 18, 16, BFDataDrvStren); - MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x00, 22, 20, BFDqsDrvStren); - MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x00, 30, 28, BFProcOdt); - MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x00, 31, 0, BFODCControl); - MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x04, 31, 0, BFAddrTmgControl); - - MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x08, 0, 0, BFWrtLvTrEn); - MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x08, 1, 1, BFWrtLvTrMode); - MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x08, 3, 3, BFPhyFenceTrEn); - MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x08, 4, 4, BFTrDimmSel); - MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x08, 7, 6, BFFenceTrSel); - MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x08, 11, 8, BFWrLvOdt); - MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x08, 12, 12, BFWrLvOdtEn); - MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x08, 13, 13, BFDqsRcvTrEn); - MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x08, 31, 0, BFDramPhyCtlReg); - - MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x0B, 31, 0, BFDramPhyStatusReg); - - MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x0C, 20, 16, BFPhyFence); - MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x0C, 13, 12, BFCKETri); - MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x0C, 11, 8, BFODTTri); - MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x0C, 7, 0, BFChipSelTri); - - MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x0D, 25, 24, BFRxDLLWakeupTime); - MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x0D, 22, 20, BFRxCPUpdPeriod); - MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x0D, 19, 16, BFRxMaxDurDllNoLock); - MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x0D, 9, 8, BFTxDLLWakeupTime); - MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x0D, 6, 4, BFTxCPUpdPeriod); - MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x0D, 3, 0, BFTxMaxDurDllNoLock); - - MAKE_TSEFO (NBRegTable, DCT_PHY_DIRECT, 0x0D0F0F10, 12, 12, BFEnRxPadStandby); - - MAKE_TSEFO (NBRegTable, DCT_PHY_DIRECT, 0x0D0FE003, 14, 13, BFDisablePredriverCal); - MAKE_TSEFO (NBRegTable, DCT_PHY_DIRECT, 0x0D0FE006, 15, 0, BFPllLockTime); - MAKE_TSEFO (NBRegTable, DCT_PHY_DIRECT, 0x0D0FE013, 15, 0, BFPllRegWaitTime); - MAKE_TSEFO (NBRegTable, DCT_PHY_DIRECT, 0x0D0F2030, 4, 4, BFPhyClkConfig0); - MAKE_TSEFO (NBRegTable, DCT_PHY_DIRECT, 0x0D0F2130, 4, 4, BFPhyClkConfig1); - - MAKE_TSEFO (NBRegTable, DCT_PHY_DIRECT, 0x0D0F0F02, 15, 0, BFDataByteTxPreDriverCal); - MAKE_TSEFO (NBRegTable, DCT_PHY_DIRECT, 0x0D0F0F06, 15, 0, BFDataByteTxPreDriverCal2Pad1); - MAKE_TSEFO (NBRegTable, DCT_PHY_DIRECT, 0x0D0F0F0A, 15, 0, BFDataByteTxPreDriverCal2Pad2); - MAKE_TSEFO (NBRegTable, DCT_PHY_DIRECT, 0x0D0F8006, 15, 0, BFCmdAddr0TxPreDriverCal2Pad1); - MAKE_TSEFO (NBRegTable, DCT_PHY_DIRECT, 0x0D0F800A, 15, 0, BFCmdAddr0TxPreDriverCal2Pad2); - MAKE_TSEFO (NBRegTable, DCT_PHY_DIRECT, 0x0D0F8106, 15, 0, BFCmdAddr1TxPreDriverCal2Pad1); - MAKE_TSEFO (NBRegTable, DCT_PHY_DIRECT, 0x0D0F810A, 15, 0, BFCmdAddr1TxPreDriverCal2Pad2); - MAKE_TSEFO (NBRegTable, DCT_PHY_DIRECT, 0x0D0FC006, 15, 0, BFAddrTxPreDriverCal2Pad1); - MAKE_TSEFO (NBRegTable, DCT_PHY_DIRECT, 0x0D0FC00A, 15, 0, BFAddrTxPreDriverCal2Pad2); - MAKE_TSEFO (NBRegTable, DCT_PHY_DIRECT, 0x0D0FC00E, 15, 0, BFAddrTxPreDriverCal2Pad3); - MAKE_TSEFO (NBRegTable, DCT_PHY_DIRECT, 0x0D0FC012, 15, 0, BFAddrTxPreDriverCal2Pad4); - MAKE_TSEFO (NBRegTable, DCT_PHY_DIRECT, 0x0D0F8002, 15, 0, BFCmdAddr0TxPreDriverCalPad0); - MAKE_TSEFO (NBRegTable, DCT_PHY_DIRECT, 0x0D0F8102, 15, 0, BFCmdAddr1TxPreDriverCalPad0); - MAKE_TSEFO (NBRegTable, DCT_PHY_DIRECT, 0x0D0FC002, 15, 0, BFAddrTxPreDriverCalPad0); - MAKE_TSEFO (NBRegTable, DCT_PHY_DIRECT, 0x0D0F2002, 15, 0, BFClock0TxPreDriverCalPad0); - MAKE_TSEFO (NBRegTable, DCT_PHY_DIRECT, 0x0D0F2102, 15, 0, BFClock1TxPreDriverCalPad0); - MAKE_TSEFO (NBRegTable, DCT_PHY_DIRECT, 0x0D0F2020, 15, 0, BFPhyClkDllFine0); - MAKE_TSEFO (NBRegTable, DCT_PHY_DIRECT, 0x0D0F2120, 15, 0, BFPhyClkDllFine1); - - MAKE_TSEFO (NBRegTable, DCT_PHY_DIRECT, 0x0D0F0F13, 14, 14, BFProcOdtAdv); - MAKE_TSEFO (NBRegTable, DCT_PHY_DIRECT, 0x0D0F0F13, 7, 0, BFPhy0x0D0F0F13Bit0to7); - MAKE_TSEFO (NBRegTable, DCT_PHY_DIRECT, 0x0D0FE00A, 15, 0, BFPhy0x0D0FE00A); - MAKE_TSEFO (NBRegTable, DCT_PHY_DIRECT, 0x0D0FE00A, 14, 12, BFPllPdMode); - - MAKE_TSEFO (NBRegTable, DCT_PHY_DIRECT, 0x0D0F0F1F, 4, 3, BFDataRxVioLvl); - MAKE_TSEFO (NBRegTable, DCT_PHY_DIRECT, 0x0D0F2F1F, 4, 3, BFClkRxVioLvl); - MAKE_TSEFO (NBRegTable, DCT_PHY_DIRECT, 0x0D0F4009, 3, 2, BFCsrComparator); - MAKE_TSEFO (NBRegTable, DCT_PHY_DIRECT, 0x0D0F4009, 15, 14, BFCmpVioLvl); - MAKE_TSEFO (NBRegTable, DCT_PHY_DIRECT, 0x0D0F8F1F, 4, 3, BFCmdRxVioLvl); - MAKE_TSEFO (NBRegTable, DCT_PHY_DIRECT, 0x0D0FC01F, 4, 3, BFAddrRxVioLvl); - - MAKE_TSEFO (NBRegTable, DCT_PHY_DIRECT, 0x0D0F0F31, 14, 0, BFDataFence2); - MAKE_TSEFO (NBRegTable, DCT_PHY_DIRECT, 0x0D0F2F31, 4, 0, BFClkFence2); - MAKE_TSEFO (NBRegTable, DCT_PHY_DIRECT, 0x0D0F8F31, 4, 0, BFCmdFence2); - MAKE_TSEFO (NBRegTable, DCT_PHY_DIRECT, 0x0D0FC031, 4, 0, BFAddrFence2); - - MAKE_TSEFO (NBRegTable, DCT_PHY_DIRECT, 0x0D0F812F, 15, 0, BFAddrCmdTri); - MAKE_TSEFO (NBRegTable, DCT_PHY_DIRECT, 0x0D0FC000, 8, 8, BFLowPowerDrvStrengthEn); - MAKE_TSEFO (NBRegTable, DCT_PHY_DIRECT, 0x0D0F0F0F, 14, 12, BFAlwaysEnDllClks); - - MAKE_TSEFO (NBRegTable, DCT_PHY_DIRECT, 0x0D080F0C, 15, 0, BFPhy0x0D080F0C); - MAKE_TSEFO (NBRegTable, DCT_PHY_DIRECT, 0x0D0F0F30, 8, 8, BFBlockRxDqsLock); - - MAKE_TSEFO (NBRegTable, DCT_EXTRA, 0x06, 11, 8, BFTwrrdSD); - MAKE_TSEFO (NBRegTable, DCT_EXTRA, 0x06, 3, 0, BFTrdrdSD); - MAKE_TSEFO (NBRegTable, DCT_EXTRA, 0x16, 3, 0, BFTwrwrSD); - - MAKE_TSEFO (NBRegTable, DCT_EXTRA, 0x30, 12, 0, BFDbeGskFifoNumerator); - MAKE_TSEFO (NBRegTable, DCT_EXTRA, 0x31, 12, 0, BFDbeGskFifoDenominator); - - MAKE_TSEFO (NBRegTable, DCT_EXTRA, 0x32, 4, 0, BFDataTxFifoSchedDlySlot0); - MAKE_TSEFO (NBRegTable, DCT_EXTRA, 0x32, 7, 7, BFDataTxFifoSchedDlyNegSlot0); - MAKE_TSEFO (NBRegTable, DCT_EXTRA, 0x32, 12, 8, BFDataTxFifoSchedDlySlot1); - MAKE_TSEFO (NBRegTable, DCT_EXTRA, 0x32, 15, 15, BFDataTxFifoSchedDlyNegSlot1); - - MAKE_TSEFO (NBRegTable, DCT_EXTRA, 0x40, 3, 0, BFTrcd); - MAKE_TSEFO (NBRegTable, DCT_EXTRA, 0x40, 11, 8, BFTrp); - MAKE_TSEFO (NBRegTable, DCT_EXTRA, 0x40, 20, 16, BFTras); - MAKE_TSEFO (NBRegTable, DCT_EXTRA, 0x40, 29, 24, BFTrc); - MAKE_TSEFO (NBRegTable, DCT_EXTRA, 0x41, 2, 0, BFTrtp); - MAKE_TSEFO (NBRegTable, DCT_EXTRA, 0x41, 10, 8, BFTrrd); - MAKE_TSEFO (NBRegTable, DCT_EXTRA, 0x41, 18, 16, BFTwtr); - - MAKE_TSEFO (NBRegTable, DCT_EXTRA, 0x83, 2, 0, BFRdOdtTrnOnDly); - MAKE_TSEFO (NBRegTable, DCT_EXTRA, 0x83, 6, 4, BFRdOdtOnDuration); - MAKE_TSEFO (NBRegTable, DCT_EXTRA, 0x83, 8, 8, BFWrOdtTrnOnDly); - MAKE_TSEFO (NBRegTable, DCT_EXTRA, 0x83, 14, 12, BFWrOdtOnDuration); - MAKE_TSEFO (NBRegTable, DCT_EXTRA, 0x180, 31, 0, BFRdOdtPatReg); - MAKE_TSEFO (NBRegTable, DCT_EXTRA, 0x182, 31, 0, BFWrOdtPatReg); - - MAKE_TSEFO (NBRegTable, DCT_EXTRA, 0x200, 3, 0, BFTxp); - MAKE_TSEFO (NBRegTable, DCT_EXTRA, 0x200, 12, 8, BFTxpdll); - - LINK_TSEFO (NBRegTable, BFTwrrd, BFTwrrdHi); - LINK_TSEFO (NBRegTable, BFTwrwr, BFTwrwrHi); - LINK_TSEFO (NBRegTable, BFTrdrd, BFTrdrdHi); - LINK_TSEFO (NBRegTable, BFDctSelIntLvAddr, BFDctSelIntLvAddrHi); -} - -/*---------------------------------------------------------------------------- - * LOCAL FUNCTIONS - * - *----------------------------------------------------------------------------*/ - - diff --git a/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/Makefile.inc b/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/Makefile.inc deleted file mode 100644 index eb029c2692..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/Makefile.inc +++ /dev/null @@ -1,9 +0,0 @@ -libagesa-y += mn.c -libagesa-y += mnS3.c -libagesa-y += mndct.c -libagesa-y += mnfeat.c -libagesa-y += mnflow.c -libagesa-y += mnmct.c -libagesa-y += mnphy.c -libagesa-y += mnreg.c -libagesa-y += mntrain3.c diff --git a/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/mn.c b/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/mn.c deleted file mode 100644 index ab261f76ed..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/mn.c +++ /dev/null @@ -1,525 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * mn.c - * - * Common Northbridge functions - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: (Mem/NB/) - * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $ - * - **/ -/***************************************************************************** -* -* Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* *************************************************************************** -* -*/ -/* - *---------------------------------------------------------------------------- - * MODULES USED - * - *---------------------------------------------------------------------------- - */ - -#include "AGESA.h" -#include "AdvancedApi.h" -#include "amdlib.h" -#include "Ids.h" -#include "mport.h" -#include "OptionMemory.h" -#include "mm.h" -#include "mn.h" -#include "mu.h" -#include "Filecode.h" -CODE_GROUP (G1_PEICC) -RDATA_GROUP (G1_PEICC) - -#define FILECODE PROC_MEM_NB_MN_FILECODE - - -/*---------------------------------------------------------------------------- - * DEFINITIONS AND MACROS - * - *---------------------------------------------------------------------------- - */ -/*---------------------------------------------------------------------------- - * TYPEDEFS AND STRUCTURES - * - *---------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------- - * PROTOTYPES OF LOCAL FUNCTIONS - * - *---------------------------------------------------------------------------- - */ -BOOLEAN -STATIC -MemNDefaultFamilyHookNb ( - IN OUT MEM_NB_BLOCK *NBPtr, - IN OUT VOID *OptParam - ); - -/*---------------------------------------------------------------------------- - * EXPORTED FUNCTIONS - * - *---------------------------------------------------------------------------- - */ -extern OPTION_MEM_FEATURE_NB* memNTrainFlowControl[]; - -extern BUILD_OPT_CFG UserOptions; - -/* -----------------------------------------------------------------------------*/ -/** - * - * This function initializes member functions and variables of NB block. - * - * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK - * - */ - -VOID -MemNInitNBDataNb ( - IN OUT MEM_NB_BLOCK *NBPtr - ) -{ - INT32 i; - UINT8 *BytePtr; - - NBPtr->DctCachePtr = NBPtr->DctCache; - NBPtr->PsPtr = NBPtr->PSBlock; - - BytePtr = (UINT8 *) (NBPtr->DctCache); - for (i = 0; i < sizeof (NBPtr->DctCache); i++) { - *BytePtr++ = 0; - } - - for (i = 0; i < EnumSize; i++) { - NBPtr->IsSupported[i] = FALSE; - } - - for (i = 0; i < NumberOfHooks; i++) { - NBPtr->FamilySpecificHook[i] = MemNDefaultFamilyHookNb; - } - - NBPtr->SwitchDCT = MemNSwitchDCTNb; - NBPtr->SwitchChannel = MemNSwitchChannelNb; - NBPtr->GetBitField = MemNGetBitFieldNb; - NBPtr->SetBitField = MemNSetBitFieldNb; -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * - * Get System address of Chipselect RJ 16 bits (Addr[47:16]) - * - * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK - * @param[in] Receiver - Chipselect to be targeted [0-7] - * @param[out] AddrPtr - Pointer to System Address [47:16] - * - * @return TRUE - Address is valid - * @return FALSE - Address is not valid - */ - -BOOLEAN -MemNGetMCTSysAddrNb ( - IN OUT MEM_NB_BLOCK *NBPtr, - IN UINT8 Receiver, - OUT UINT32 *AddrPtr - ) -{ - S_UINT64 SMsr; - UINT32 CSBase; - UINT32 HoleBase; - UINT32 DctSelBaseAddr; - UINT32 BottomUma; - DIE_STRUCT *MCTPtr; - MEM_DATA_STRUCT *MemPtr; - - MCTPtr = NBPtr->MCTPtr; - MemPtr = NBPtr->MemPtr; - - ASSERT (Receiver < 8); - - CSBase = MemNGetBitFieldNb (NBPtr, BFCSBaseAddr0Reg + Receiver); - if (CSBase & 1) { - ASSERT ((CSBase & 0xE0) == 0); // Should not enable CS interleaving before DQS training. - - // Scale base address from [39:8] to [47:16] - CSBase >>= 8; - - HoleBase = MCTPtr->NodeHoleBase ? MCTPtr->NodeHoleBase : 0x7FFFFFFF; - - if ((MemNGetBitFieldNb (NBPtr, BFDctSelHiRngEn) == 1) && (NBPtr->Dct == MemNGetBitFieldNb (NBPtr, BFDctSelHi))) { - DctSelBaseAddr = MemNGetBitFieldNb (NBPtr, BFDctSelBaseAddr) << (27 - 16); - if (DctSelBaseAddr > HoleBase) { - DctSelBaseAddr -= _4GB_RJ16 - HoleBase; - } - CSBase += DctSelBaseAddr; - } else { - CSBase += MCTPtr->NodeSysBase; - } - - if (CSBase >= HoleBase) { - CSBase += _4GB_RJ16 - HoleBase; - } - - CSBase += (UINT32)1 << (21 - 16); // Add 2MB offset to avoid compat area. - if ((CSBase >= (MCT_TRNG_KEEPOUT_START >> 8)) && (CSBase <= (MCT_TRNG_KEEPOUT_END >> 8))) { - CSBase += (((MCT_TRNG_KEEPOUT_END >> 8) - CSBase) + 0x0F) & 0xFFFFFFF0; - } - - if (MCTPtr->Status[SbHWHole]) { - if (MCTPtr->Status[SbSWNodeHole]) { - LibAmdMsrRead (TOP_MEM, (UINT64 *)&SMsr, &MemPtr->StdHeader); - - if ((CSBase >= (SMsr.lo >> 16)) && (CSBase < _4GB_RJ16)) { - return FALSE; - } - } - } - - BottomUma = NBPtr->RefPtr->Sub4GCacheTop >> 16; - if (BottomUma && (CSBase >= BottomUma) && (CSBase < _4GB_RJ16)) { - return FALSE; - } - *AddrPtr = CSBase; - return TRUE; - } - return FALSE; -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * This function determines if a Rank is enabled. - * - * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK - * @param[in] Receiver - Receiver to check - * @return - FALSE - * - */ - -BOOLEAN -MemNRankEnabledNb ( - IN OUT MEM_NB_BLOCK *NBPtr, - IN UINT8 Receiver - ) -{ - UINT32 CSBase; - CSBase = MemNGetBitFieldNb (NBPtr, BFCSBaseAddr0Reg + Receiver); - if (CSBase & 1) { - return TRUE; - } else { - return FALSE; - } -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * - * This function sets the EccSymbolSize bit depending upon configurations - * and system override. - * - * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK - * - */ - -VOID -MemNSetEccSymbolSizeNb ( - IN OUT MEM_NB_BLOCK *NBPtr - ) -{ - UINT16 X4DimmsOnly; - BOOLEAN Size; - DIE_STRUCT *MCTPtr; - DCT_STRUCT *DCTPtr; - - ASSERT (NBPtr != NULL); - - MCTPtr = NBPtr->MCTPtr; - DCTPtr = NBPtr->DCTPtr; - - // Determine if this node has only x4 DRAM parts - X4DimmsOnly = (UINT16) ((!(DCTPtr->Timings.Dimmx8Present | DCTPtr->Timings.Dimmx16Present)) && DCTPtr->Timings.Dimmx4Present); - // - // Check if EccSymbolSize BKDG value is overridden - // - if (UserOptions.CfgEccSymbolSize != ECCSYMBOLSIZE_USE_BKDG) { - Size = (UserOptions.CfgEccSymbolSize == ECCSYMBOLSIZE_FORCE_X4) ? FALSE : TRUE; - } else { - if (X4DimmsOnly && MCTPtr->GangedMode) { - Size = FALSE; - } else { - Size = TRUE; - } - } - IDS_OPTION_HOOK (IDS_ECCSYMBOLSIZE, &Size, &(NBPtr->MemPtr->StdHeader)); - MemNSetBitFieldNb (NBPtr, BFEccSymbolSize, (UINT32) Size); -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * This function sets the training control flow - * The DDR3 mode bit must be set prior to calling this function - * - * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK - */ -BOOLEAN -MemNTrainingFlowNb ( - IN OUT MEM_NB_BLOCK *NBPtr - ) -{ - if (MemNGetBitFieldNb (NBPtr, BFDdr3Mode)!= 0) { - memNTrainFlowControl[DDR3_TRAIN_FLOW] (NBPtr); - } else { - memNTrainFlowControl[DDR2_TRAIN_FLOW] (NBPtr); - } - return TRUE; -} - -/*-----------------------------------------------------------------------------*/ -/** - * - * This function flushes the training pattern - * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK - * @param[in] Address - System Address [47:16] - * @param[in] ClCount - Number of cache lines - * - */ - -VOID -MemNFlushPatternNb ( - IN OUT MEM_NB_BLOCK *NBPtr, - IN UINT32 Address, - IN UINT16 ClCount - ) -{ - // Due to speculative execution during MemUReadCachelines, we must - // flush one more cache line than we read. - MemUProcIOClFlush (Address, ClCount + 1, NBPtr->MemPtr); -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * This function compares test pattern with data in buffer and - * return a pass/fail bitmap for 8 bytelanes (upper 8 bits are reserved) - * - * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK - * @param[in] Buffer[] - Buffer data from DRAM (Measured data from DRAM) to compare - * @param[in] Pattern[] - Pattern (Expected data in ROM/CACHE) to compare against - * @param[in] ByteCount - Byte count - * - * @return PASS - Bitmap of results of comparison - */ - -UINT16 -MemNCompareTestPatternNb ( - IN OUT MEM_NB_BLOCK *NBPtr, - IN UINT8 Buffer[], - IN UINT8 Pattern[], - IN UINT16 ByteCount - ) -{ - UINT16 i; - UINT16 Pass; - UINT8 ColumnCount; - UINT8 FailingBitMask[8]; - - ASSERT ((ByteCount == 18 * 64) || (ByteCount == 9 * 64) || (ByteCount == 64 * 64) || (ByteCount == 32 * 64) || (ByteCount == 3 * 64)); - - ColumnCount = NBPtr->ChannelPtr->ColumnCount; - Pass = 0xFFFF; - // - // Clear Failing Bit Mask - // - for (i = 0; i < sizeof (FailingBitMask); i++) { - FailingBitMask[i] = 0; - } - - if (NBPtr->Ganged && (NBPtr->Dct != 0)) { - i = 8; // DCT 1 in ganged mode - } else { - i = 0; - } - - for (; i < ByteCount; i++) { - if (Buffer[i] != Pattern[i]) { - // if bytelane n fails - Pass &= ~((UINT16)1 << (i % 8)); // clear bit n - FailingBitMask[i % NBPtr->TechPtr->MaxByteLanes ()] |= (Buffer[i] ^ Pattern[i]); - } - - if (NBPtr->Ganged && ((i & 7) == 7)) { - i += 8; // if ganged, skip over other Channel's Data - } - } - // - // Accumulate Failing bit data - // - for (i = 0; i < sizeof (FailingBitMask); i++) { - NBPtr->ChannelPtr->FailingBitMask[(ColumnCount * NBPtr->TechPtr->ChipSel) + i] &= - FailingBitMask[i]; - } - - return Pass; -} - -/*----------------------------------------------------------------------------- - * - * - * This function compares test pattern with data in buffer and - * return a pass/fail bitmap for 8 bytelanes (upper 8 bits are reserved) - * - * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK - * @param[in] Buffer[] - Buffer data from DRAM (Measured data from DRAM) to compare - * @param[in] Pattern[] - Pattern (Expected data in ROM/CACHE) to compare against - * @param[in] ByteCount - Byte count - * - * @retval PASS - Bitmap of results of comparison - * ---------------------------------------------------------------------------- - */ -UINT16 -MemNInsDlyCompareTestPatternNb ( - IN MEM_NB_BLOCK *NBPtr, - IN UINT8 Buffer[], - IN UINT8 Pattern[], - IN UINT16 ByteCount - ) -{ - UINT16 i; - UINT16 Pass; - UINT16 BeatOffset; - UINT16 BeatCnt; - UINT8 ColumnCount; - UINT8 FailingBitMask[8]; - - ASSERT ((ByteCount == 18 * 64) || (ByteCount == 9 * 64) || (ByteCount == 64 * 64) || (ByteCount == 32 * 64) || (ByteCount == 3 * 64)); - - ColumnCount = NBPtr->ChannelPtr->ColumnCount; - Pass = 0xFFFF; - // - // Clear Failing Bit Mask - // - for (i = 0; i < sizeof (FailingBitMask); i++) { - FailingBitMask[i] = 0; - } - - if (NBPtr->Ganged && (NBPtr->Dct != 0)) { - i = 8; // DCT 1 in ganged mode - } else { - i = 0; - } - - if (NBPtr->Ganged) { - BeatOffset = 16; - } else { - BeatOffset = 8; - } - - BeatCnt = 0; - for (; i < ByteCount; i++) { - - if (Buffer[i] != Pattern[i + BeatOffset]) { - // if bytelane n fails - Pass &= ~((UINT16)1 << (i % 8)); // clear bit n - FailingBitMask[i % NBPtr->TechPtr->MaxByteLanes ()] |= (Buffer[i] ^ Pattern[i + BeatOffset]); - } - - if ((i & 7) == 7) { - if (NBPtr->Ganged) { - i += 8; // if ganged, skip over other Channel's Data - } - BeatCnt++; - } - - if ((BeatCnt & 3) == 3) { - // Skip last data beat of a 4-beat burst. - BeatCnt++; - i = i + BeatOffset; - } - } - // - // Accumulate Failing bit data - // - for (i = 0; i < sizeof (FailingBitMask); i++) { - NBPtr->ChannelPtr->FailingBitMask[(ColumnCount * NBPtr->TechPtr->ChipSel) + i] &= - FailingBitMask[i]; - } - - return Pass; -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * This function sets the training control flow for UNB - * The DDR3 mode bit must be set prior to calling this function - * - * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK - */ -BOOLEAN -MemNTrainingFlowUnb ( - IN OUT MEM_NB_BLOCK *NBPtr - ) -{ - memNTrainFlowControl[DDR3_TRAIN_FLOW] (NBPtr); - return TRUE; -} -/*---------------------------------------------------------------------------- - * LOCAL FUNCTIONS - * - *---------------------------------------------------------------------------- - */ - -/*----------------------------------------------------------------------------- - * - * - * This function is an empty function used to intialize FamilySpecificHook array - * - * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK - * @param[in,out] OptParam - Optional parameter - * - * @return TRUE - always - * ---------------------------------------------------------------------------- - */ -BOOLEAN -STATIC -MemNDefaultFamilyHookNb ( - IN OUT MEM_NB_BLOCK *NBPtr, - IN OUT VOID *OptParam - ) -{ - return TRUE; -} diff --git a/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/mnS3.c b/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/mnS3.c deleted file mode 100644 index a2f68f9811..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/mnS3.c +++ /dev/null @@ -1,1353 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * mnS3.c - * - * Common Northbridge S3 - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: (Mem/NB) - * @e \$Revision: 51670 $ @e \$Date: 2011-04-27 03:26:02 +0800 (Wed, 27 Apr 2011) $ - * - **/ -/***************************************************************************** -* -* Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* *************************************************************************** -* -*/ - -/* - *---------------------------------------------------------------------------- - * MODULES USED - * - *---------------------------------------------------------------------------- - */ - -#include "AGESA.h" -#include "AdvancedApi.h" -#include "amdlib.h" -#include "Ids.h" -#include "OptionMemory.h" -#include "mm.h" -#include "mn.h" -#include "S3.h" -#include "mfs3.h" -#include "cpuFamilyTranslation.h" -#include "heapManager.h" -#include "Filecode.h" -CODE_GROUP (G3_DXE) -RDATA_GROUP (G3_DXE) - -#define FILECODE PROC_MEM_NB_MNS3_FILECODE -/*---------------------------------------------------------------------------- - * DEFINITIONS AND MACROS - * - *---------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------- - * TYPEDEFS AND STRUCTURES - * - *---------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------- - * PROTOTYPES OF LOCAL FUNCTIONS - * - *---------------------------------------------------------------------------- - */ -VOID -STATIC -MemNS3GetSetBitField ( - IN ACCESS_WIDTH AccessWidth, - IN PCI_ADDR Address, - IN BOOLEAN IsSet, - IN OUT VOID *Value, - IN OUT VOID *ConfigPtr - ); - -BOOLEAN -STATIC -MemNS3GetDummyReadAddr ( - IN OUT MEM_NB_BLOCK *NBPtr, - OUT UINT64 *TestAddr - ); -/*---------------------------------------------------------------------------- - * EXPORTED FUNCTIONS - * - *---------------------------------------------------------------------------- - */ - -/* -----------------------------------------------------------------------------*/ -/** - * - * - * This function executes the S3 resume for a node - * - * @param[in,out] *S3NBPtr - Pointer to the S3_MEM_NB_BLOCK - * @param[in] NodeID - The Node id of the target die - * - * @return BOOLEAN - * TRUE - This is the correct constructor for the targeted node. - * FALSE - This isn't the correct constructor for the targeted node. - */ - -BOOLEAN -MemNS3ResumeNb ( - IN OUT S3_MEM_NB_BLOCK *S3NBPtr, - IN UINT8 NodeID - ) -{ - UINT8 DCT; - BOOLEAN GangedEn; - UINT64 TestAddr; - MEM_NB_BLOCK *NBPtr; - MEM_DATA_STRUCT *MemPtr; - - NBPtr = S3NBPtr->NBPtr; - MemPtr = NBPtr->MemPtr; - GangedEn = (MemNGetBitFieldNb (NBPtr, BFDctGangEn) == 1) ? TRUE : FALSE; - - // Errata before S3 resume sequence - - // Resume Sequence - // 1. Program F2x[1,0]9C_x08[DisAutoComp]=1 - MemNSwitchDCTNb (NBPtr, 0); - MemNSetBitFieldNb (NBPtr, BFDisAutoComp, 1); - - // Program F2x[1, 0]94[MemClkFreqVal] = 1. - // 2. Wait for F2x[1,0]94[FreqChgInPrg]=0 - for (DCT = 0; DCT < NBPtr->DctCount; DCT ++) { - MemNSwitchDCTNb (NBPtr, DCT); - if ((MemNGetBitFieldNb (NBPtr, BFDisDramInterface) == 0) && !((DCT == 1) && GangedEn)) { - MemNSetBitFieldNb (NBPtr, BFMemClkFreqVal, 1); - while (MemNGetBitFieldNb (NBPtr, BFFreqChgInProg) != 0) {} - } - } - - // Program F2x9C_x08[DisAutoComp]=0 - MemNSwitchDCTNb (NBPtr, 0); - MemNSetBitFieldNb (NBPtr, BFDisAutoComp, 0); - // BIOS must wait 750 us for the phy compensation engine - // to reinitialize. - MemFS3Wait10ns (75000, NBPtr->MemPtr); - - // 3. Restore F2x[1,0]90_x00, F2x9C_x0A, and F2x[1,0]9C_x0C - // 4. Restore F2x[1,0]9C_x04 - // Get the register value from the heap. - S3NBPtr->MemS3ExitSelfRefReg (NBPtr, &MemPtr->StdHeader); - - // Add a hook here - AGESA_TESTPOINT (TpProcMemBeforeAgesaHookBeforeExitSelfRef, &MemPtr->StdHeader); - if (AgesaHookBeforeExitSelfRefresh (0, MemPtr) == AGESA_SUCCESS) { - } - AGESA_TESTPOINT (TpProcMemAfterAgesaHookBeforeExitSelfRef, &MemPtr->StdHeader); - - // 5. Set F2x[1,0]90[ExitSelfRef] - // 6. Wait for F2x[1,0]90[ExitSelfRef]=0 - for (DCT = 0; DCT < NBPtr->DctCount; DCT ++) { - MemNSwitchDCTNb (NBPtr, DCT); - if ((MemNGetBitFieldNb (NBPtr, BFDisDramInterface) == 0) && !((DCT == 1) && GangedEn)) { - MemNSetBitFieldNb (NBPtr, BFExitSelfRef, 1); - while (MemNGetBitFieldNb (NBPtr, BFExitSelfRef) != 0) {} - } - if ((MemNGetBitFieldNb (NBPtr, BFMemClkFreq) == DDR1333_FREQUENCY) && (NBPtr->IsSupported[CheckDllSpeedUp])) { - MemNSetBitFieldNb (NBPtr, BFPhy0x0D080F11, (MemNGetBitFieldNb (NBPtr, BFPhy0x0D080F11) | 0x2000)); - MemNSetBitFieldNb (NBPtr, BFPhy0x0D080F10, (MemNGetBitFieldNb (NBPtr, BFPhy0x0D080F10) | 0x2000)); - MemNSetBitFieldNb (NBPtr, BFPhy0x0D088F30, (MemNGetBitFieldNb (NBPtr, BFPhy0x0D088F30) | 0x2000)); - MemNSetBitFieldNb (NBPtr, BFPhy0x0D08C030, (MemNGetBitFieldNb (NBPtr, BFPhy0x0D08C030) | 0x2000)); - if (DCT == 0) { - MemNSetBitFieldNb (NBPtr, BFPhy0x0D082F30, (MemNGetBitFieldNb (NBPtr, BFPhy0x0D082F30) | 0x2000)); - } - // NOTE: wait 512 clocks for DLL-relock - MemFS3Wait10ns (50000, NBPtr->MemPtr); // wait 500us - } - } - - // Errata After S3 resume sequence - // Errata 350 - for (DCT = 0; DCT < NBPtr->DctCount; DCT ++) { - MemNSwitchDCTNb (NBPtr, DCT); - if (MemNGetBitFieldNb (NBPtr, BFDisDramInterface) == 0) { - if (!((DCT == 1) && GangedEn)) { - if (MemNS3GetDummyReadAddr (NBPtr, &TestAddr)) { - // Do dummy read - Read64Mem8 (TestAddr); - // Flush the cache line - LibAmdCLFlush (TestAddr, 1); - } - } - MemNSetBitFieldNb (NBPtr, BFErr350, 0x8000); - MemFS3Wait10ns (60, NBPtr->MemPtr); // Wait 300ns - MemNSetBitFieldNb (NBPtr, BFErr350, 0x0000); - MemFS3Wait10ns (400, NBPtr->MemPtr); // Wait 2us - } - } - - return TRUE; -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * - * This function executes the S3 resume for a node on a client NB - * - * @param[in,out] *S3NBPtr - Pointer to the S3_MEM_NB_BLOCK - * @param[in] NodeID - The Node id of the target die - * - * @return BOOLEAN - * TRUE - This is the correct constructor for the targeted node. - * FALSE - This isn't the correct constructor for the targeted node. - */ -BOOLEAN -MemNS3ResumeClientNb ( - IN OUT S3_MEM_NB_BLOCK *S3NBPtr, - IN UINT8 NodeID - ) -{ - UINT8 DCT; - MEM_NB_BLOCK *NBPtr; - MEM_DATA_STRUCT *MemPtr; - - NBPtr = S3NBPtr->NBPtr; - MemPtr = NBPtr->MemPtr; - - // Errata before S3 resume sequence - - // Add a hook here - AGESA_TESTPOINT (TpProcMemBeforeAgesaHookBeforeExitSelfRef, &MemPtr->StdHeader); - if (AgesaHookBeforeExitSelfRefresh (0, MemPtr) == AGESA_SUCCESS) { - } - AGESA_TESTPOINT (TpProcMemAfterAgesaHookBeforeExitSelfRef, &MemPtr->StdHeader); - - NBPtr->ChangeNbFrequencyWrap (NBPtr, 0); - //Override the NB Pstate if needed - IDS_OPTION_HOOK (IDS_NB_PSTATE_DIDVID, S3NBPtr->NBPtr, &MemPtr->StdHeader); - // Set F2x[1,0]90[ExitSelfRef] - // Wait for F2x[1,0]90[ExitSelfRef]=0 - for (DCT = 0; DCT < NBPtr->DctCount; DCT ++) { - MemNSwitchDCTNb (NBPtr, DCT); - if (MemNGetBitFieldNb (NBPtr, BFDisDramInterface) == 0) { - MemNSetBitFieldNb (NBPtr, BFDisDllShutdownSR, 1); - MemNSetBitFieldNb (NBPtr, BFExitSelfRef, 1); - while (MemNGetBitFieldNb (NBPtr, BFExitSelfRef) != 0) {} - MemNSetBitFieldNb (NBPtr, BFDisDllShutdownSR, 0); - } - } - - // Errata After S3 resume sequence - return TRUE; -} -/* -----------------------------------------------------------------------------*/ -/** - * - * - * This function executes the S3 resume for a node on a UNB - * - * @param[in,out] *S3NBPtr - Pointer to the S3_MEM_NB_BLOCK - * @param[in] NodeID - The Node id of the target die - * - * @return BOOLEAN - * TRUE - This is the correct constructor for the targeted node. - * FALSE - This isn't the correct constructor for the targeted node. - */ -BOOLEAN -MemNS3ResumeUNb ( - IN OUT S3_MEM_NB_BLOCK *S3NBPtr, - IN UINT8 NodeID - ) -{ - UINT8 DCT; - MEM_NB_BLOCK *NBPtr; - MEM_DATA_STRUCT *MemPtr; - - NBPtr = S3NBPtr->NBPtr; - MemPtr = NBPtr->MemPtr; - - // Errata before S3 resume sequence - - // Add a hook here - AGESA_TESTPOINT (TpProcMemBeforeAgesaHookBeforeExitSelfRef, &MemPtr->StdHeader); - if (AgesaHookBeforeExitSelfRefresh (0, MemPtr) == AGESA_SUCCESS) { - } - AGESA_TESTPOINT (TpProcMemAfterAgesaHookBeforeExitSelfRef, &MemPtr->StdHeader); - - //Override the NB Pstate if needed - IDS_OPTION_HOOK (IDS_NB_PSTATE_DIDVID, S3NBPtr->NBPtr, &MemPtr->StdHeader); - // Set F2x[1,0]90[ExitSelfRef] - // Wait for F2x[1,0]90[ExitSelfRef]=0 - for (DCT = 0; DCT < NBPtr->DctCount; DCT ++) { - MemNSwitchDCTNb (NBPtr, DCT); - if (MemNGetBitFieldNb (NBPtr, BFDisDramInterface) == 0) { - MemNSetBitFieldNb (NBPtr, BFDisDllShutdownSR, 1); - MemNSetBitFieldNb (NBPtr, BFExitSelfRef, 1); - while (MemNGetBitFieldNb (NBPtr, BFExitSelfRef) != 0) {} - MemNSetBitFieldNb (NBPtr, BFDisDllShutdownSR, 0); - } - } - - // Errata After S3 resume sequence - return TRUE; -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * - * This function returns the conditional PCI device mask - * - * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK - * @param[in, out] *DescriptPtr - Pointer to DESCRIPTOR_GROUP - * @return none - */ -VOID -MemNS3GetConPCIMaskNb ( - IN OUT MEM_NB_BLOCK *NBPtr, - IN OUT DESCRIPTOR_GROUP *DescriptPtr - ) -{ - BIT_FIELD_NAME bitfield; - UINT32 RegVal; - UINT8 DCT; - UINT8 DimmMask; - UINT8 BadDimmMask; - UINT8 DctGangEn; - BOOLEAN IsDDR3; - - IsDDR3 = FALSE; - DimmMask = 0; - BadDimmMask = 0; - for (DCT = 0; DCT < NBPtr->DctCount; DCT ++) { - NBPtr->SwitchDCT (NBPtr, DCT); - if (MemNGetBitFieldNb (NBPtr, BFMemClkFreqVal)) { - if (MemNGetBitFieldNb (NBPtr, BFDdr3Mode) == 1) { - IsDDR3 = TRUE; - } - for (bitfield = BFCSBaseAddr0Reg; bitfield <= BFCSBaseAddr7Reg; bitfield ++) { - RegVal = MemNGetBitFieldNb (NBPtr, bitfield); - if (RegVal & 0x3) { - DimmMask |= (UINT8) (1 << ((((bitfield - BFCSBaseAddr0Reg) >> 1) << 1) + DCT)); - } else if (RegVal & 0x4) { - BadDimmMask |= (UINT8) (1 << ((((bitfield - BFCSBaseAddr0Reg) >> 1) << 1) + DCT)); - } - } - } - } - - NBPtr->SwitchDCT (NBPtr, 0); - DctGangEn = (UINT8) MemNGetBitFieldNb (NBPtr, BFDctGangEn); - // Set channel mask - DescriptPtr->CPCIDevice[PRESELFREF].Mask1 = 0; - DescriptPtr->CPCIDevice[POSTSELFREF].Mask1 = 0; - for (DCT = 0; DCT < NBPtr->DctCount; DCT ++) { - if (DimmMask & (0x55 << DCT)) { - // Set mask before exit self refresh - DescriptPtr->CPCIDevice[PRESELFREF].Mask1 |= 1 << DCT; - // Set mask after exit self refresh - DescriptPtr->CPCIDevice[POSTSELFREF].Mask1 |= 1 << DCT; - // Set DDR3 mask if Dimms present are DDR3 - if (IsDDR3) { - DescriptPtr->CPCIDevice[POSTSELFREF].Mask1 |= (DescriptPtr->CPCIDevice[POSTSELFREF].Mask1 << 4); - } - } else if (BadDimmMask & (0x55 << DCT)) { - // Need to save function 2 registers for bad dimm - DescriptPtr->CPCIDevice[PRESELFREF].Mask1 |= 1 << DCT; - } - } - - // Set dimm mask - DescriptPtr->CPCIDevice[PRESELFREF].Mask2 = DimmMask; - DescriptPtr->CPCIDevice[POSTSELFREF].Mask2 = DimmMask; - if (DctGangEn) { - // Need to set channel mask bit to 1 on DCT1 in ganged mode as some registers - // need to be restored on both channels in ganged mode - DescriptPtr->CPCIDevice[PRESELFREF].Mask1 |= 2; - DescriptPtr->CPCIDevice[POSTSELFREF].Mask1 |= 2; - if (IsDDR3) { - DescriptPtr->CPCIDevice[PRESELFREF].Mask1 |= (2 << 4); - DescriptPtr->CPCIDevice[POSTSELFREF].Mask1 |= (2 << 4); - } - // Before exit self refresh, do not copy dimm mask to DCT1 as registers restored - // in that time frame don't care about individual dimm population. We want to - // skip registers that are not needed to be restored for DCT1 in ganged mode. - // - // After exit self refresh, training registers will be restored and will only be - // restored for slots which have dimms on it. So dimm mask needs to be copied to DCT1. - // - DescriptPtr->CPCIDevice[POSTSELFREF].Mask2 |= DimmMask << 1; - } - - // Adjust the mask if there is no dimm on the node - if ((DescriptPtr->CPCIDevice[PRESELFREF].Mask2 == 0) && - (DescriptPtr->CPCIDevice[POSTSELFREF].Mask2 == 0)) { - DescriptPtr->CPCIDevice[PRESELFREF].Mask1 = DescriptPtr->CPCIDevice[PRESELFREF].Mask2 = NODE_WITHOUT_DIMM_MASK; - DescriptPtr->CPCIDevice[POSTSELFREF].Mask1 = DescriptPtr->CPCIDevice[POSTSELFREF].Mask2 = NODE_WITHOUT_DIMM_MASK; - } -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * - * This function returns the conditional PCI device mask - * - * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK - * @param[in, out] *DescriptPtr - Pointer to DESCRIPTOR_GROUP - * @return none - */ -VOID -MemNS3GetConPCIMaskUnb ( - IN OUT MEM_NB_BLOCK *NBPtr, - IN OUT DESCRIPTOR_GROUP *DescriptPtr - ) -{ - BIT_FIELD_NAME bitfield; - UINT32 RegVal; - UINT8 DCT; - UINT8 DimmMask; - UINT8 BadDimmMask; - UINT8 NbPsCap; - - DimmMask = 0; - BadDimmMask = 0; - for (DCT = 0; DCT < NBPtr->DctCount; DCT ++) { - MemNSwitchDCTNb (NBPtr, DCT); - if (MemNGetBitFieldNb (NBPtr, BFMemClkFreqVal)) { - for (bitfield = BFCSBaseAddr0Reg; bitfield <= BFCSBaseAddr7Reg; bitfield ++) { - RegVal = MemNGetBitFieldNb (NBPtr, bitfield); - if (RegVal & 0x1) { - DimmMask |= (UINT8) (1 << ((((bitfield - BFCSBaseAddr0Reg) >> 1) << 1) + DCT)); - } else if (RegVal & 0x4) { - BadDimmMask |= (UINT8) (1 << ((((bitfield - BFCSBaseAddr0Reg) >> 1) << 1) + DCT)); - } - } - } - } - // Check if the system is capable of doing NB Pstate change - NbPsCap = (UINT8) MemNGetBitFieldNb (NBPtr, BFNbPstateDis); - - MemNSwitchDCTNb (NBPtr, 0); - // Set channel mask - DescriptPtr->CPCIDevice[PRESELFREF].Mask1 = 0; - DescriptPtr->CPCIDevice[POSTSELFREF].Mask1 = 0; - for (DCT = 0; DCT < NBPtr->DctCount; DCT ++) { - if (DimmMask & (0x55 << DCT)) { - // Set mask before exit self refresh - DescriptPtr->CPCIDevice[PRESELFREF].Mask1 |= ((NbPsCap == 0) ? 5 : 1) << DCT; - // Set mask after exit self refresh - DescriptPtr->CPCIDevice[POSTSELFREF].Mask1 |= 1 << DCT; - // Set DDR3 mask if Dimms present are DDR3 - DescriptPtr->CPCIDevice[POSTSELFREF].Mask1 |= (DescriptPtr->CPCIDevice[POSTSELFREF].Mask1 << 4); - } else if (BadDimmMask & (0x55 << DCT)) { - // Need to save function 2 registers for bad dimm - DescriptPtr->CPCIDevice[PRESELFREF].Mask1 |= 1 << DCT; - } - } - - // Set dimm mask - DescriptPtr->CPCIDevice[PRESELFREF].Mask2 = DimmMask; - DescriptPtr->CPCIDevice[POSTSELFREF].Mask2 = DimmMask; - - // Adjust the mask if there is no dimm on the node - if ((DescriptPtr->CPCIDevice[PRESELFREF].Mask2 == 0) && - (DescriptPtr->CPCIDevice[POSTSELFREF].Mask2 == 0)) { - DescriptPtr->CPCIDevice[PRESELFREF].Mask1 = DescriptPtr->CPCIDevice[PRESELFREF].Mask2 = NODE_WITHOUT_DIMM_MASK; - DescriptPtr->CPCIDevice[POSTSELFREF].Mask1 = DescriptPtr->CPCIDevice[POSTSELFREF].Mask2 = NODE_WITHOUT_DIMM_MASK; - } -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * - * This function read the value of CSR register. - * - * @param[in] AccessWidth - Access width of the register - * @param[in] Address - address of the CSR register in PCI_ADDR format. - * @param[in] *Value - Pointer to the value be read. - * @param[in, out] *ConfigPtr - Pointer to Config handle. - * @return none - */ -VOID -MemNS3GetCSRNb ( - IN ACCESS_WIDTH AccessWidth, - IN PCI_ADDR Address, - IN VOID *Value, - IN OUT VOID *ConfigPtr - ) -{ - UINT32 ExtendOffset; - UINT32 ValueRead; - UINT8 DataPort; - - ValueRead = 0; - ExtendOffset = Address.Address.Register; - if (ExtendOffset & 0x800) { - Address.Address.Register = 0xF0; - DataPort = 0xF4; - } else { - Address.Address.Register = 0x98; - DataPort = 0x9C; - } - if (ExtendOffset & 0x400) { - Address.Address.Register |= 0x100; - } - ExtendOffset &= 0x3FF; - LibAmdPciWrite (AccessS3SaveWidth32, Address, &ExtendOffset, ConfigPtr); - while (((ValueRead >> 31) & 1) == 0) { - LibAmdPciRead (AccessS3SaveWidth32, Address, &ValueRead, ConfigPtr); - } - Address.Address.Register = (Address.Address.Register & 0xF00) | DataPort; - LibAmdPciRead (AccessWidth, Address, Value, ConfigPtr); -} - - -/* -----------------------------------------------------------------------------*/ -/** - * - * - * This function write to a CSR register - * - * @param[in] AccessWidth - Access width of the register - * @param[in] Address - address of the CSR register in PCI_ADDR format. - * @param[in, out] *Value - Pointer to the value be read. - * @param[in, out] *ConfigPtr - Pointer to Config handle. - * @return none - */ -VOID -MemNS3SetCSRNb ( - IN ACCESS_WIDTH AccessWidth, - IN PCI_ADDR Address, - IN OUT VOID *Value, - IN OUT VOID *ConfigPtr - ) -{ - UINT32 ExtendOffset; - UINT32 ValueRead; - UINT32 ValueWrite; - UINT8 DataOffset; - - ValueRead = 0; - ExtendOffset = Address.Address.Register; - // Check the flag and see the type of the access - if (ExtendOffset & 0x800) { - Address.Address.Register = 0xF4; - DataOffset = 0xF0; - } else { - Address.Address.Register = 0x9C; - DataOffset = 0x98; - } - if (ExtendOffset & 0x400) { - Address.Address.Register |= 0x100; - } - ExtendOffset &= 0x3FF; - ExtendOffset |= 0x40000000; - switch (AccessWidth) { - case AccessS3SaveWidth8: - ValueWrite = *(UINT8 *) Value; - break; - case AccessS3SaveWidth16: - ValueWrite = *(UINT16 *) Value; - break; - case AccessS3SaveWidth32: - ValueWrite = *(UINT32 *) Value; - break; - default: - ASSERT (FALSE); - } - LibAmdPciWrite (AccessS3SaveWidth32, Address, &ValueWrite, ConfigPtr); - Address.Address.Register = (Address.Address.Register & 0xF00) | DataOffset; - LibAmdPciWrite (AccessS3SaveWidth32, Address, &ExtendOffset, ConfigPtr); - while (((ValueRead >> 31) & 1) == 0) { - LibAmdPciRead (AccessS3SaveWidth32, Address, &ValueRead, ConfigPtr); - } -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * - * This function reads register bitfield - * - * @param[in] AccessWidth - Access width of the register - * @param[in] Address - address of the CSR register in PCI_ADDR format. - * @param[in, out] *Value - Pointer to the value be read. - * @param[in, out] *ConfigPtr - Pointer to Config handle. - * @return none - */ -VOID -MemNS3GetBitFieldNb ( - IN ACCESS_WIDTH AccessWidth, - IN PCI_ADDR Address, - IN OUT VOID *Value, - IN OUT VOID *ConfigPtr - ) -{ - MemNS3GetSetBitField (AccessWidth, Address, FALSE, Value, ConfigPtr); -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * - * This function writes register bitfield - * - * @param[in] AccessWidth - Access width of the register - * @param[in] Address - address of the CSR register in PCI_ADDR format. - * @param[in, out] *Value - Pointer to the value to be written. - * @param[in, out] *ConfigPtr - Pointer to Config handle. - * @return none - */ -VOID -MemNS3SetBitFieldNb ( - IN ACCESS_WIDTH AccessWidth, - IN PCI_ADDR Address, - IN OUT VOID *Value, - IN OUT VOID *ConfigPtr - ) -{ - MemNS3GetSetBitField (AccessWidth, Address, TRUE, Value, ConfigPtr); -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * - * This function restores scrubber base register - * - * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK - * @param[in] Node - The Node id of the target die - * - */ -VOID -MemNS3RestoreScrubNb ( - IN OUT MEM_NB_BLOCK *NBPtr, - IN UINT8 Node - ) -{ - UINT32 ScrubAddrRJ16; - - ScrubAddrRJ16 = (MemNGetBitFieldNb (NBPtr, BFDramBaseReg0 + Node) & 0xFFFF0000) >> 8; - ScrubAddrRJ16 |= MemNGetBitFieldNb (NBPtr, BFDramBaseHiReg0 + Node) << 24; - MemNSetBitFieldNb (NBPtr, BFScrubAddrLoReg, ScrubAddrRJ16 << 16); - MemNSetBitFieldNb (NBPtr, BFScrubAddrHiReg, ScrubAddrRJ16 >> 16); -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * - * This function disable NB Pstate Debug. - * - * @param[in] AccessWidth - Access width of the register. - * @param[in] Address - address in PCI_ADDR format. - * @param[in, out] *Value - Pointer to the value to be written. - * @param[in, out] *ConfigPtr - Pointer to Config handle. - * @return none - */ -VOID -MemNS3DisNbPsDbgNb ( - IN ACCESS_WIDTH AccessWidth, - IN PCI_ADDR Address, - IN OUT VOID *Value, - IN OUT VOID *ConfigPtr - ) -{ - UINT32 RegValue; - - LibAmdPciRead (AccessS3SaveWidth32, Address, &RegValue, ConfigPtr); - // Clear NbPsDbgEn and NbPsCsrAccSel - if ((RegValue & 0xC0000000) != 0) { - RegValue &= 0x3FFFFFFF; - LibAmdPciWrite (AccessS3SaveWidth32, Address, &RegValue, ConfigPtr); - } -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * - * This function that enable NB Pstate debug register to allow access to NB Pstate - * 1 registers without actually changing NB Pstate. - * - * @param[in] AccessWidth - Access width of the register. - * @param[in] Address - address in PCI_ADDR format. - * @param[in, out] *Value - Pointer to the value to be written. - * @param[in, out] *ConfigPtr - Pointer to Config handle. - * @return none - */ -VOID -MemNS3EnNbPsDbg1Nb ( - IN ACCESS_WIDTH AccessWidth, - IN PCI_ADDR Address, - IN OUT VOID *Value, - IN OUT VOID *ConfigPtr - ) -{ - UINT32 RegValue; - - LibAmdPciRead (AccessS3SaveWidth32, Address, &RegValue, ConfigPtr); - // Set NbPsDbgEn to 1 and NbPsCsrAccSel to 1 - if ((RegValue & 0xC0000000) != 0xC0000000) { - RegValue = (*(UINT32 *)Value & 0x3FFFFFFF) | 0xC0000000; - LibAmdPciWrite (AccessS3SaveWidth32, Address, &RegValue, ConfigPtr); - } -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * - * This function sets bit 31 [DynModeChange] of F2x9C_xB - * - * @param[in] AccessWidth - Access width of the register. - * @param[in] Address - address in PCI_ADDR format. - * @param[in, out] *Value - Pointer to the value to be written. - * @param[in, out] *ConfigPtr - Pointer to Config handle. - * @return none - */ -VOID -MemNS3SetDynModeChangeNb ( - IN ACCESS_WIDTH AccessWidth, - IN PCI_ADDR Address, - IN OUT VOID *Value, - IN OUT VOID *ConfigPtr - ) -{ - UINT32 RegValue; - - RegValue = 0x80000000; - IDS_SKIP_HOOK (IDS_BEFORE_S3_SPECIAL, &Address, ConfigPtr) { - MemNS3SetCSRNb (AccessS3SaveWidth32, Address, &RegValue, ConfigPtr); - } -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * - * This function does the channel disable sequence - * - * @param[in] AccessWidth - Access width of the register. - * @param[in] Address - address in PCI_ADDR format. - * @param[in, out] *Value - Pointer to the value to be written. - * @param[in, out] *ConfigPtr - Pointer to Config handle. - * @return none - */ -VOID -MemNS3DisableChannelNb ( - IN ACCESS_WIDTH AccessWidth, - IN PCI_ADDR Address, - IN OUT VOID *Value, - IN OUT VOID *ConfigPtr - ) -{ - MEM_NB_BLOCK *NBPtr; - LOCATE_HEAP_PTR LocateBufferPtr; - S3_MEM_NB_BLOCK *S3NBPtr; - UINT32 RegValue; - UINT8 Die; - - // See which Node should be accessed - Die = (UINT8) (Address.Address.Device - 24); - - LocateBufferPtr.BufferHandle = AMD_MEM_S3_NB_HANDLE; - if (HeapLocateBuffer (&LocateBufferPtr, ConfigPtr) == AGESA_SUCCESS) { - S3NBPtr = (S3_MEM_NB_BLOCK *) LocateBufferPtr.BufferPtr; - NBPtr = S3NBPtr[Die].NBPtr; - - // Function field contains the DCT number - NBPtr->SwitchDCT (NBPtr, (UINT8) Address.Address.Function); - RegValue = MemNGetBitFieldNb (NBPtr, BFCKETri); - // if CKETri is 0b11, this channel is disabled - if (RegValue == 3) { - //Wait for 24 MEMCLKs, which is 60ns under 400MHz - MemFS3Wait10ns (6, NBPtr->MemPtr); - MemNSetBitFieldNb (NBPtr, BFMemClkDis, 0xFF); - MemNSetBitFieldNb (NBPtr, BFDisDramInterface, 1); - MemNSetBitFieldNb (NBPtr, BFDramPhyStatusReg, 0x80800000); - } - } -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * - * This function disables auto compensation. - * - * @param[in] AccessWidth - Access width of the register. - * @param[in] Address - address in PCI_ADDR format. - * @param[in, out] *Value - Pointer to the value to be written. - * @param[in, out] *ConfigPtr - Pointer to Config handle. - * @return none - */ -VOID -MemNS3SetDisAutoCompUnb ( - IN ACCESS_WIDTH AccessWidth, - IN PCI_ADDR Address, - IN OUT VOID *Value, - IN OUT VOID *ConfigPtr - ) -{ - UINT16 RegValue; - - MemNS3GetBitFieldNb (AccessS3SaveWidth16, Address, &RegValue, ConfigPtr); - RegValue = 0x6000 | RegValue; - MemNS3SetBitFieldNb (AccessS3SaveWidth16, Address, &RegValue, ConfigPtr); -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * - * This function retores Pre Driver Calibration with pre driver calibration code - * code valid bit set. - * - * @param[in] AccessWidth - Access width of the register. - * @param[in] Address - address in PCI_ADDR format. - * @param[in, out] *Value - Pointer to the value to be written. - * @param[in, out] *ConfigPtr - Pointer to Config handle. - * @return none - */ -VOID -MemNS3SetPreDriverCalUnb ( - IN ACCESS_WIDTH AccessWidth, - IN PCI_ADDR Address, - IN OUT VOID *Value, - IN OUT VOID *ConfigPtr - ) -{ - UINT16 RegValue; - - RegValue = 0x8000 | *(UINT16 *) Value; - MemNS3SetBitFieldNb (AccessS3SaveWidth16, Address, &RegValue, ConfigPtr); -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * This function is used by families that use a separate DctCfgSel bit to - * select the current DCT which will be accessed by function 2. - * NOTE: This function must be called BEFORE the NBPtr->Dct variable is - * updated. - * - * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK - * @param[in] *Dct - Pointer to ID of the target DCT - * - */ - -BOOLEAN -MemNS3DctCfgSelectUnb ( - IN OUT MEM_NB_BLOCK *NBPtr, - IN VOID *Dct - ) -{ - // Set the DctCfgSel to new DCT - // - MemNSetBitFieldNb (NBPtr, BFDctCfgSel, *(UINT8*)Dct); - - return TRUE; -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * - * This function write to a register that has one copy for each NB Pstate - * - * @param[in] AccessWidth - Access width of the register - * @param[in] Address - address of the CSR register in PCI_ADDR format. - * @param[in, out] *Value - Pointer to the value be read. - * @param[in, out] *ConfigPtr - Pointer to Config handle. - * @return none - */ -VOID -MemNS3GetNBPStateDepRegUnb ( - IN ACCESS_WIDTH AccessWidth, - IN PCI_ADDR Address, - IN OUT VOID *Value, - IN OUT VOID *ConfigPtr - ) -{ - UINT8 NBPstate; - UINT8 TempValue; - UINT8 Dct; - UINT32 Temp; - - Temp = Address.Address.Register; - NBPstate = (UINT8) (Temp >> 10); - Dct = (UINT8) Address.Address.Function; - Temp &= 0x3FF; - - // Switch Dct - // Function field contains DCT value - Address.Address.Function = FUNC_1; - Address.Address.Register = 0x10C; - LibAmdPciRead (AccessS3SaveWidth8, Address, &TempValue, ConfigPtr); - TempValue = (TempValue & 0xCE) | ((NBPstate << 4) | Dct); - LibAmdPciWrite (AccessS3SaveWidth8, Address, &TempValue, ConfigPtr); - - Address.Address.Function = FUNC_2; - Address.Address.Register = Temp; - LibAmdPciRead (AccessWidth, Address, Value, ConfigPtr); - - Address.Address.Function = FUNC_1; - Address.Address.Register = 0x10C; - TempValue = 0; - LibAmdPciWrite (AccessS3SaveWidth32, Address, &TempValue, ConfigPtr); -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * - * This function write to a register that has one copy for each NB Pstate - * - * @param[in] AccessWidth - Access width of the register - * @param[in] Address - address of the CSR register in PCI_ADDR format. - * @param[in, out] *Value - Pointer to the value be read. - * @param[in, out] *ConfigPtr - Pointer to Config handle. - * @return none - */ -VOID -MemNS3SetNBPStateDepRegUnb ( - IN ACCESS_WIDTH AccessWidth, - IN PCI_ADDR Address, - IN OUT VOID *Value, - IN OUT VOID *ConfigPtr - ) -{ - UINT8 NBPstate; - UINT8 TempValue; - UINT8 Dct; - UINT32 Temp; - - Temp = Address.Address.Register; - NBPstate = (UINT8) (Temp >> 10); - Dct = (UINT8) Address.Address.Function; - Temp &= 0x3FF; - - // Switch Dct - // Function field contains DCT value - Address.Address.Function = FUNC_1; - Address.Address.Register = 0x10C; - LibAmdPciRead (AccessS3SaveWidth8, Address, &TempValue, ConfigPtr); - TempValue = (TempValue & 0xCE) | ((NBPstate << 4) | Dct); - LibAmdPciWrite (AccessS3SaveWidth8, Address, &TempValue, ConfigPtr); - - Address.Address.Function = FUNC_2; - Address.Address.Register = Temp; - LibAmdPciWrite (AccessWidth, Address, Value, ConfigPtr); - - Address.Address.Function = FUNC_1; - Address.Address.Register = 0x10C; - TempValue = 0; - LibAmdPciWrite (AccessS3SaveWidth32, Address, &TempValue, ConfigPtr); -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * - * This function read the value of Function 2 PCI register. - * - * @param[in] AccessWidth - Access width of the register - * @param[in] Address - address of the NB register in PCI_ADDR format. - * @param[in] *Value - Pointer to the value be read. - * @param[in, out] *ConfigPtr - Pointer to Config handle. - * @return none - */ -VOID -MemNS3SaveNBRegiserUnb ( - IN ACCESS_WIDTH AccessWidth, - IN PCI_ADDR Address, - IN OUT VOID *Value, - IN OUT VOID *ConfigPtr - ) -{ - UINT8 TempValue; - UINT8 Dct; - UINT32 Temp; - - Temp = Address.Address.Register; - Dct = (UINT8) Address.Address.Function; - - // Switch Dct - // Function field contains DCT value - Address.Address.Function = FUNC_1; - Address.Address.Register = 0x10C; - LibAmdPciRead (AccessS3SaveWidth8, Address, &TempValue, ConfigPtr); - TempValue = (TempValue & 0xFE) | Dct; - LibAmdPciWrite (AccessS3SaveWidth8, Address, &TempValue, ConfigPtr); - - Address.Address.Register = Temp; - Address.Address.Function = FUNC_2; - LibAmdPciRead (AccessWidth, Address, Value, ConfigPtr); -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * - * This function set the value of Function 2 PCI register. - * - * @param[in] AccessWidth - Access width of the register - * @param[in] Address - address of the NB register in PCI_ADDR format. - * @param[in] *Value - Pointer to the value be write. - * @param[in, out] *ConfigPtr - Pointer to Config handle. - * @return none - */ -VOID -MemNS3RestoreNBRegiserUnb ( - IN ACCESS_WIDTH AccessWidth, - IN PCI_ADDR Address, - IN OUT VOID *Value, - IN OUT VOID *ConfigPtr - ) -{ - UINT8 TempValue; - UINT8 Dct; - UINT32 Temp; - - Temp = Address.Address.Register; - Dct = (UINT8) Address.Address.Function; - - // Switch Dct - // Function field contains DCT value - Address.Address.Function = FUNC_1; - Address.Address.Register = 0x10C; - LibAmdPciRead (AccessS3SaveWidth8, Address, &TempValue, ConfigPtr); - TempValue = (TempValue & 0xFE) | Dct; - LibAmdPciWrite (AccessS3SaveWidth8, Address, &TempValue, ConfigPtr); - - Address.Address.Register = Temp; - Address.Address.Function = FUNC_2; - LibAmdPciWrite (AccessWidth, Address, Value, ConfigPtr); -} - -/*---------------------------------------------------------------------------- - * LOCAL FUNCTIONS - * - *----------------------------------------------------------------------------*/ - -/* -----------------------------------------------------------------------------*/ -/** - * - * - * This function reads and writes register bitfield - * - * @param[in] AccessWidth - Access width of the register - * @param[in] Address - address of the CSR register in PCI_ADDR format. - * @param[in] IsSet - if this is a register read or write - * @param[in, out] *Value - Pointer to the value be read or written. - * @param[in, out] *ConfigPtr - Pointer to Config handle. - * @return none - */ -VOID -STATIC -MemNS3GetSetBitField ( - IN ACCESS_WIDTH AccessWidth, - IN PCI_ADDR Address, - IN BOOLEAN IsSet, - IN OUT VOID *Value, - IN OUT VOID *ConfigPtr - ) -{ - BIT_FIELD_NAME BitField; - MEM_NB_BLOCK *NBPtr; - LOCATE_HEAP_PTR LocateBufferPtr; - S3_MEM_NB_BLOCK *S3NBPtr; - UINT32 RegValue; - UINT8 Die; - - RegValue = 0; - // See which Node should be accessed - Die = (UINT8) (Address.Address.Device - 24); - - LocateBufferPtr.BufferHandle = AMD_MEM_S3_NB_HANDLE; - if (HeapLocateBuffer (&LocateBufferPtr, ConfigPtr) == AGESA_SUCCESS) { - S3NBPtr = (S3_MEM_NB_BLOCK *) LocateBufferPtr.BufferPtr; - NBPtr = S3NBPtr[Die].NBPtr; - - // Function field contains the DCT number - NBPtr->SwitchDCT (NBPtr, (UINT8) Address.Address.Function); - - // Get the bitfield name to be accessed - // Register field contains the bitfield name - BitField = (BIT_FIELD_NAME) Address.Address.Register; - - if (IsSet) { - switch (AccessWidth) { - case AccessS3SaveWidth8: - RegValue = *(UINT8 *) Value; - break; - case AccessS3SaveWidth16: - RegValue = *(UINT16 *) Value; - break; - case AccessS3SaveWidth32: - RegValue = *(UINT32 *) Value; - break; - default: - ASSERT (FALSE); - } - MemNSetBitFieldNb (NBPtr, BitField, RegValue); - } else { - RegValue = MemNGetBitFieldNb (NBPtr, BitField); - - switch (AccessWidth) { - case AccessS3SaveWidth8: - *(UINT8 *) Value = (UINT8) RegValue; - break; - case AccessS3SaveWidth16: - *(UINT16 *) Value = (UINT16) RegValue; - break; - case AccessS3SaveWidth32: - *(UINT32 *) Value = RegValue; - break; - default: - ASSERT (FALSE); - } - } - } else { - ASSERT (FALSE); - } -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * - * This function gets the dummy read address for a channel of a node. - * - * @param[in, out] *NBPtr - Pointer to northbridge block - * @param[out] *TestAddr - Pointer to the test address - * - * @retval TRUE - Dummy read address can be found - * @retval FALSE - Dummy read address cannot be found - * - */ -BOOLEAN -STATIC -MemNS3GetDummyReadAddr ( - IN OUT MEM_NB_BLOCK *NBPtr, - OUT UINT64 *TestAddr - ) -{ - BOOLEAN DctSelIntlvEn; - UINT8 DramIntlvEn; - UINT8 DctSelIntlvAddr; - UINT8 IntLvRgnBaseAddr; - UINT8 IntLvRgnLmtAddr; - UINT8 IntLvRgnSize; - UINT32 DctSelBaseAddr; - UINT64 TOM; - BOOLEAN AddrFound; - - AddrFound = TRUE; - // Check if Node interleaving is enabled - DramIntlvEn = (UINT8) MemNGetBitFieldNb (NBPtr, BFDramIntlvEn); - if (DramIntlvEn != 0) { - // Set the address bits that identify the node - *TestAddr = (UINT64) MemNGetBitFieldNb (NBPtr, BFDramIntlvSel) << 12; - } else { - *TestAddr = (UINT64) MemNGetBitFieldNb (NBPtr, BFDramBaseAddr) << 27; - } - - // Check if channel interleaving is enabled - DctSelIntlvEn = (BOOLEAN) MemNGetBitFieldNb (NBPtr, BFDctSelIntLvEn); - DctSelBaseAddr = MemNGetBitFieldNb (NBPtr, BFDctSelBaseAddr); - if (!DctSelIntlvEn) { - if ((NBPtr->Dct == 1) && ((UINT8) MemNGetBitFieldNb (NBPtr, BFDctSelHi) == 1)) { - *TestAddr = ((UINT64) DctSelBaseAddr << 27) | (*TestAddr & 0xFFFFFFF); - } - } else { - DctSelIntlvAddr = (UINT8) MemNGetBitFieldNb (NBPtr, BFDctSelIntLvAddr); - // Set the address bits that identify the channel - if ((DctSelIntlvAddr == 0) || (DctSelIntlvAddr == 2)) { - *TestAddr |= (UINT64) NBPtr->Dct << 6; - } else if (DctSelIntlvAddr == 1) { - *TestAddr |= (UINT64) NBPtr->Dct << (12 + LibAmdBitScanReverse (DramIntlvEn + 1)); - } else if (DctSelIntlvAddr == 3) { - *TestAddr |= (UINT64) NBPtr->Dct << 9; - } - } - // Adding 2M to avoid conflict - *TestAddr += 0x200000; - - // If memory hoisting is disabled, the address can fall into MMIO area - // Need to find an address out of MMIO area but belongs to the channel - // If the whole channel is in MMIO, then do not do dummy read. - // - LibAmdMsrRead (TOP_MEM, &TOM, &NBPtr->MemPtr->StdHeader); - if ((*TestAddr >= TOM) && (*TestAddr < ((UINT64) _4GB_RJ16 << 16))) { - if ((NBPtr->Dct == 1) && ((UINT8) MemNGetBitFieldNb (NBPtr, BFDctSelHi) == 1)) { - // This is the DCT that goes to high address range - if (DctSelBaseAddr >= (_4GB_RJ16 >> (27 - 16))) { - // When DctSelBaseAddr is higher than 4G, choose DctSelBaseAddr as the dummy read addr - if (DctSelIntlvEn) { - *TestAddr = ((UINT64) DctSelBaseAddr << 27) | (*TestAddr & 0xFFFFFFF); - } - } else if (MemNGetBitFieldNb (NBPtr, BFDramLimitAddr) > (UINT32) (_4GB_RJ16 >> (27 - 16))) { - // if DctSelBase is smaller than 4G, but Dram limit is larger than 4G, then choose 4G as - // dummy read address - *TestAddr = ((UINT64) _4GB_RJ16 << 16) | (*TestAddr & 0xFFFFFF); - } else { - AddrFound = FALSE; - } - } else { - // This is the DCT that only goes to low address range - if (DctSelBaseAddr > (_4GB_RJ16 >> (27 - 16))) { - // When DctSelBaseAddr is larger than 4G, choose 4G as the dummy read address - // Keep the lower bits for node and channel selection - *TestAddr = ((UINT64) _4GB_RJ16 << 16) | (*TestAddr & 0xFFFFFF); - } else { - AddrFound = FALSE; - } - } - } - - // Interleaved Swap Region handling - if ((BOOLEAN) MemNGetBitFieldNb (NBPtr, BFIntLvRgnSwapEn)) { - IntLvRgnBaseAddr = (UINT8) MemNGetBitFieldNb (NBPtr, BFIntLvRgnBaseAddr); - IntLvRgnLmtAddr = (UINT8) MemNGetBitFieldNb (NBPtr, BFIntLvRgnLmtAddr); - IntLvRgnSize = (UINT8) MemNGetBitFieldNb (NBPtr, BFIntLvRgnSize); - ASSERT (IntLvRgnSize == (IntLvRgnLmtAddr - IntLvRgnBaseAddr + 1)); - if (((*TestAddr >> 34) == 0) && - ((((*TestAddr >> 27) >= IntLvRgnBaseAddr) && ((*TestAddr >> 27) <= IntLvRgnLmtAddr)) - || ((*TestAddr >> 27) < IntLvRgnSize))) { - *TestAddr ^= (UINT64) IntLvRgnBaseAddr << 27; - } - } - - return AddrFound; -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * - * This function sets bit 7 [MemClkFreqVal] of F2x94_dct[1:0] - * - * @param[in] AccessWidth - Access width of the register. - * @param[in] Address - address in PCI_ADDR format. - * @param[in, out] *Value - Pointer to the value to be written. - * @param[in, out] *ConfigPtr - Pointer to Config handle. - * @return none - */ -VOID -MemNS3SetMemClkFreqValUnb ( - IN ACCESS_WIDTH AccessWidth, - IN PCI_ADDR Address, - IN OUT VOID *Value, - IN OUT VOID *ConfigPtr - ) -{ - UINT32 TempValue; - - // 1. Program F2x94_dct[1:0][MemClkFreqVal] = 1 - MemNS3SaveNBRegiserUnb (AccessWidth, Address, &TempValue, ConfigPtr); - TempValue |= 0x80; - MemNS3RestoreNBRegiserUnb (AccessWidth, Address, &TempValue, ConfigPtr); - - // 2. Wait for F2x94_dct[1:0][FreqChgInPrg] = 0 - MemNS3SaveNBRegiserUnb (AccessWidth, Address, &TempValue, ConfigPtr); - while ((TempValue & 0x200000) != 0) { - MemNS3SaveNBRegiserUnb (AccessWidth, Address, &TempValue, ConfigPtr); - } -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * - * This function changes memory Pstate context - * - * @param[in] AccessWidth - Access width of the register. - * @param[in] Address - address in PCI_ADDR format. Target MemPState is in - * Address.Address.Register. - * @param[in, out] *Value - Pointer to the value to be written. - * @param[in, out] *ConfigPtr - Pointer to Config handle. - * @return none - * - * @return TRUE - * ---------------------------------------------------------------------------- - */ -VOID -MemNS3ChangeMemPStateContextNb ( - IN ACCESS_WIDTH AccessWidth, - IN PCI_ADDR Address, - IN OUT VOID *Value, - IN OUT VOID *ConfigPtr - ) -{ - MEM_NB_BLOCK *NBPtr; - LOCATE_HEAP_PTR LocateBufferPtr; - S3_MEM_NB_BLOCK *S3NBPtr; - UINT8 Die; - - // See which Node should be accessed - Die = (UINT8) (Address.Address.Device - 24); - - LocateBufferPtr.BufferHandle = AMD_MEM_S3_NB_HANDLE; - if (HeapLocateBuffer (&LocateBufferPtr, ConfigPtr) == AGESA_SUCCESS) { - S3NBPtr = (S3_MEM_NB_BLOCK *) LocateBufferPtr.BufferPtr; - NBPtr = S3NBPtr[Die].NBPtr; - MemNChangeMemPStateContextNb (NBPtr, Address.Address.Register); - } -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * - * This function retores Phy Clk DLL fine delay - * - * @param[in] AccessWidth - Access width of the register. - * @param[in] Address - address in PCI_ADDR format. - * @param[in, out] *Value - Pointer to the value to be written. - * @param[in, out] *ConfigPtr - Pointer to Config handle. - * @return none - */ -VOID -MemNS3SetPhyClkDllFineClientNb ( - IN ACCESS_WIDTH AccessWidth, - IN PCI_ADDR Address, - IN OUT VOID *Value, - IN OUT VOID *ConfigPtr - ) -{ - UINT16 RegValue; - - RegValue = 0x4000 | *(UINT16 *) Value; - MemNS3SetBitFieldNb (AccessS3SaveWidth16, Address, &RegValue, ConfigPtr); - RegValue = 0xBFFF & *(UINT16 *) Value; - MemNS3SetBitFieldNb (AccessS3SaveWidth16, Address, &RegValue, ConfigPtr); -} diff --git a/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/mndct.c b/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/mndct.c deleted file mode 100644 index 5ccc85292b..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/mndct.c +++ /dev/null @@ -1,3414 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * mndct.c - * - * Common Northbridge DCT support - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: (Mem/NB) - * @e \$Revision: 49790 $ @e \$Date: 2011-03-29 13:03:34 +0800 (Tue, 29 Mar 2011) $ - * - **/ -/***************************************************************************** -* -* Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* *************************************************************************** -* -*/ - - -/* - *---------------------------------------------------------------------------- - * MODULES USED - * - *---------------------------------------------------------------------------- - */ - - - -#include "AGESA.h" -#include "amdlib.h" -#include "Ids.h" -#include "mport.h" -#include "mm.h" -#include "mn.h" -#include "mt.h" -#include "mu.h" -#include "mftds.h" -#include "merrhdl.h" -#include "cpuFamilyTranslation.h" -#include "OptionMemory.h" -#include "PlatformMemoryConfiguration.h" -#include "Filecode.h" -CODE_GROUP (G1_PEICC) -RDATA_GROUP (G1_PEICC) - -#define FILECODE PROC_MEM_NB_MNDCT_FILECODE -/*---------------------------------------------------------------------------- - * DEFINITIONS AND MACROS - * - *---------------------------------------------------------------------------- - */ -#define UNUSED_CLK 4 - -/*---------------------------------------------------------------------------- - * TYPEDEFS AND STRUCTURES - * - *---------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------- - * PROTOTYPES OF LOCAL FUNCTIONS - * - *---------------------------------------------------------------------------- - */ - -VOID -STATIC -MemNAfterStitchMemNb ( - IN OUT MEM_NB_BLOCK *NBPtr - ); - -UINT8 -MemNGet1KTFawTkNb ( - IN UINT8 k - ); - -UINT8 -MemNGet2KTFawTkNb ( - IN UINT8 k - ); - -VOID -STATIC -MemNQuarterMemClk2NClkNb ( - IN OUT MEM_NB_BLOCK *NBPtr, - IN OUT UINT16 *SubTotalPtr - ); - -/*---------------------------------------------------------------------------- - * EXPORTED FUNCTIONS - * - *---------------------------------------------------------------------------- - */ - -extern BUILD_OPT_CFG UserOptions; - -/* -----------------------------------------------------------------------------*/ -/** - * - * - * This function combines all the memory into a contiguous map. - * Requires that Mask values for each bank be programmed first and that - * the chip-select population indicator is correctly set. - * - * - * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK - * - * @return TRUE - An Error value lower than AGESA_FATAL may have occurred - * @return FALSE - An Error value greater than or equal to AGESA_FATAL may have occurred - */ - -BOOLEAN -MemNStitchMemoryNb ( - IN OUT MEM_NB_BLOCK *NBPtr - ) -{ - BOOLEAN DSpareEn; - UINT32 NxtCSBase; - UINT32 CurCSBase; - UINT32 CsSize; - UINT32 BiggestBank; - UINT8 p; - UINT8 q; - UINT8 BiggestDimm; - MEM_PARAMETER_STRUCT *RefPtr; - DIE_STRUCT *MCTPtr; - DCT_STRUCT *DCTPtr; - RefPtr = NBPtr->RefPtr; - MCTPtr = NBPtr->MCTPtr; - DCTPtr = NBPtr->DCTPtr; - DSpareEn = FALSE; - if (NBPtr->IsSupported[SetSpareEn]) { - DSpareEn = FALSE; - if (RefPtr->GStatus[GsbEnDIMMSpareNW]) { - DSpareEn = TRUE; - } - } - - DCTPtr->Timings.CsEnabled = 0; - NxtCSBase = 0; - for (p = 0; p < MAX_CS_PER_CHANNEL; p++) { - BiggestBank = 0; - BiggestDimm = 0; - for (q = 0; q < MAX_CS_PER_CHANNEL; q++) { - if (((DCTPtr->Timings.CsPresent & ~DCTPtr->Timings.CsTestFail) & ((UINT16)1 << q)) != 0) { - if ((MemNGetBitFieldNb (NBPtr, BFCSBaseAddr0Reg + q) & 7) == 0) { - // (CSEnable|Spare==1)bank is not enabled yet - CsSize = MemNGetBitFieldNb (NBPtr, BFCSMask0Reg + (q >> 1)); - if (CsSize != 0) { - CsSize += ((UINT32)1 << 19); - CsSize &= 0xFFF80000; - } - if (CsSize > BiggestBank) { - BiggestBank = CsSize; - BiggestDimm = q; - } - } - } - } - - if (BiggestBank != 0) { - CurCSBase = NxtCSBase; - if (NBPtr->IsSupported[CheckSpareEn]) { - if (DSpareEn) { - CurCSBase = ((UINT32)1 << BFSpare); - DSpareEn = FALSE; - } else { - CurCSBase |= ((UINT32)1 << BFCSEnable); - NxtCSBase += BiggestBank; - } - } else { - CurCSBase |= ((UINT32)1 << BFCSEnable); - NxtCSBase += BiggestBank; - } - if ((BiggestDimm & 1) != 0) { - if (!(MCTPtr->Status[SbLrdimms])) { - // For LRDIMMS, On Dimm Mirroring is enabled after SDI - if ((DCTPtr->Timings.DimmMirrorPresent & (1 << (BiggestDimm >> 1))) != 0) { - CurCSBase |= ((UINT32)1 << BFOnDimmMirror); - } - } - } - MemNSetBitFieldNb (NBPtr, BFCSBaseAddr0Reg + BiggestDimm, CurCSBase); - DCTPtr->Timings.CsEnabled |= (1 << BiggestDimm); - } - if ((DCTPtr->Timings.CsTestFail & ((UINT16)1 << p)) != 0) { - IDS_HDT_CONSOLE (MEM_FLOW, "Node %d Dct %d exclude CS %d\n", NBPtr->Node, NBPtr->Dct, p); - MemNSetBitFieldNb (NBPtr, (BFCSBaseAddr0Reg + p), (UINT32)1 << BFTestFail); - } - } - - if (NxtCSBase != 0) { - DCTPtr->Timings.DctMemSize = NxtCSBase >> 8; // Scale base address from [39:8] to [47:16] - MemNAfterStitchMemNb (NBPtr); - } - - return (BOOLEAN) (MCTPtr->ErrCode < AGESA_FATAL); -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * - * This function gets platform specific config/timing values from the interface layer and - * programs them into DCT. - * - * - * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK - * - * @return TRUE - An Error value lower than AGESA_FATAL may have occurred - * @return FALSE - An Error value greater than or equal to AGESA_FATAL may have occurred - */ - -BOOLEAN -MemNPlatformSpecNb ( - IN OUT MEM_NB_BLOCK *NBPtr - ) -{ - CONST BIT_FIELD_NAME ChipletPDRegs[] = { - BFPhyClkConfig0, - BFPhyClkConfig3, - BFPhyClkConfig1, - BFPhyClkConfig2 - }; - CONST UINT8 ChipletPDClkDisMap[][2] = { - //F2[1, 0]x9C_x0D0F2030 -> F2x[1, 0]88[MemClkDis[1:0]] - {0, 1}, - //F2[1, 0]x9C_x0D0F2330 -> F2x[1, 0]88[MemClkDis[7:6]] - {6, 7}, - //F2x09C_x0D0F2130 -> F2x88[MemClkDis[5:4]] - {4, 5}, - //F2x09C_x0D0F2230 -> F2x88[MemClkDis[3:2]] - {2, 3}, - //F2x19C_x0D0F2130 -> F2x188[MemClkDis[5:2]] - {2, 5}, - //F2x19C_x0D0F2230 -> F2x188[MemClkDis[4:3]] - {3, 4} - }; - - UINT8 MemClkDis; - UINT8 i; - UINT8 MemoryAllClocks; - UINT8 *MemClkDisMap; - UINT16 CsPresent; - UINT8 RegIndex; - UINT8 Cs1; - UINT8 Cs2; - - if (!MemNGetPlatformCfgNb (NBPtr)) { - IDS_ERROR_TRAP; - } - - if (!NBPtr->PsPtr->MemPDoPs (NBPtr)) { - IDS_ERROR_TRAP; - } - MemNProgramPlatformSpecNb (NBPtr); - - MemProcessConditionalOverrides (NBPtr->RefPtr->PlatformMemoryConfiguration, NBPtr, PSO_ACTION_ODT, ALL_DIMMS); - - if (NBPtr->MCTPtr->GangedMode) { - MemNSwitchDCTNb (NBPtr, 1); - if (!MemNGetPlatformCfgNb (NBPtr)) { - IDS_ERROR_TRAP; - } - MemNProgramPlatformSpecNb (NBPtr); - MemNSwitchDCTNb (NBPtr, 0); - } - - //====================================================================== - // Disable unused MemClk to save power - //====================================================================== - // - MemClkDis = 0; - MemoryAllClocks = UserOptions.CfgMemoryAllClocksOn; - IDS_OPTION_HOOK (IDS_ALL_MEMORY_CLOCK, &MemoryAllClocks, &(NBPtr->MemPtr->StdHeader)); - if (!MemoryAllClocks) { - // Special Jedec SPD diagnostic bit - "enable all clocks" - if (!NBPtr->MCTPtr->Status[SbDiagClks]) { - MemClkDisMap = FindPSOverrideEntry (NBPtr->RefPtr->PlatformMemoryConfiguration, PSO_MEMCLK_DIS, NBPtr->MCTPtr->SocketId, MemNGetSocketRelativeChannelNb (NBPtr, NBPtr->Dct, 0)); - if (MemClkDisMap == NULL) { - MemClkDisMap = NBPtr->ChannelPtr->MemClkDisMap; - } - - // Turn off the unused CS clocks - CsPresent = NBPtr->DCTPtr->Timings.CsPresent; - - if (NBPtr->IsSupported[CheckMemClkCSPresent]) { - if (NBPtr->ChannelPtr->RegDimmPresent != 0) { - // All DDR3 RDIMM use only one MEMCLOCK from edge finger to the register - // regardless of how many Ranks are on the DIMM (Single, Dual or Quad) - CsPresent = (CsPresent | (CsPresent >> 1)) & 0x5555; - } - } - for (i = 0; i < 8; i++) { - if ((CsPresent & MemClkDisMap[i]) == 0) { - MemClkDis |= (UINT8) (1 << i); - } - } - //Chiplet power down - for (RegIndex = 0; RegIndex < GET_SIZE_OF (ChipletPDRegs); RegIndex++) { - if ((NBPtr->Dct == 1) && (RegIndex >= 2)) { - Cs1 = MemClkDisMap[ChipletPDClkDisMap[RegIndex + 2][0]]; - Cs2 = MemClkDisMap[ChipletPDClkDisMap[RegIndex + 2][1]]; - } else { - Cs1 = MemClkDisMap[ChipletPDClkDisMap[RegIndex][0]]; - Cs2 = MemClkDisMap[ChipletPDClkDisMap[RegIndex][1]]; - } - if ((CsPresent & (UINT16) (Cs1 | Cs2)) == 0) { - MemNSetBitFieldNb (NBPtr, ChipletPDRegs[RegIndex], (MemNGetBitFieldNb (NBPtr, ChipletPDRegs[RegIndex]) | 0x10)); - } - } - } - } - MemNSetBitFieldNb (NBPtr, BFMemClkDis, MemClkDis); - - AGESA_TESTPOINT (TPProcMemPhyCompensation, &(NBPtr->MemPtr->StdHeader)); - NBPtr->MemNInitPhyComp (NBPtr); - - MemProcessConditionalOverrides (NBPtr->RefPtr->PlatformMemoryConfiguration, NBPtr, PSO_ACTION_SLEWRATE, ALL_DIMMS); - - // Program DramTerm for DDR2 - if ((MemNGetBitFieldNb (NBPtr, BFDdr3Mode)) == 0) { - MemNSetBitFieldNb (NBPtr, BFDramTerm, NBPtr->PsPtr->DramTerm); - } else { - // Dynamic Dynamic DramTerm for DDR3 - // Dram Term for DDR3 may vary based on chip selects - MemNSetBitFieldNb (NBPtr, BFDramTermDyn, NBPtr->PsPtr->DynamicDramTerm); - } - - MemFInitTableDrive (NBPtr, MTAfterPlatformSpec); - - return (BOOLEAN) (NBPtr->MCTPtr->ErrCode < AGESA_FATAL); -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * - * This function gets platform specific config/timing values from the interface layer and - * programs them into DCT. - * - * - * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK - * - * @return TRUE - An Error value lower than AGESA_FATAL may have occurred - * @return FALSE - An Error value greater than or equal to AGESA_FATAL may have occurred - */ - -BOOLEAN -MemNPlatformSpecUnb ( - IN OUT MEM_NB_BLOCK *NBPtr - ) -{ - UINT8 MemClkDis; - UINT8 i; - UINT8 MemoryAllClocks; - UINT8 *MemClkDisMap; - UINT16 CsPresent; - - if (!MemNGetPlatformCfgNb (NBPtr)) { - IDS_ERROR_TRAP; - } - - if (!NBPtr->PsPtr->MemPDoPs (NBPtr)) { - IDS_HDT_CONSOLE (MEM_FLOW, "\tDisable DCT%d due to unsupported DIMM configuration\n", NBPtr->Dct); - NBPtr->MemPtr->ErrorHandling (NBPtr->MCTPtr, NBPtr->Dct, EXCLUDE_ALL_CHIPSEL, &NBPtr->MemPtr->StdHeader); - NBPtr->DisableDCT (NBPtr); - } else { - - MemNProgramPlatformSpecNb (NBPtr); - MemProcessConditionalOverrides (NBPtr->RefPtr->PlatformMemoryConfiguration, NBPtr, PSO_ACTION_ODT, ALL_DIMMS); - - //====================================================================== - // Disable unused MemClk to save power - //====================================================================== - // - MemClkDis = 0; - MemoryAllClocks = UserOptions.CfgMemoryAllClocksOn; - IDS_OPTION_HOOK (IDS_ALL_MEMORY_CLOCK, &MemoryAllClocks, &(NBPtr->MemPtr->StdHeader)); - if (!MemoryAllClocks) { - // Special Jedec SPD diagnostic bit - "enable all clocks" - if (!NBPtr->MCTPtr->Status[SbDiagClks]) { - MemClkDisMap = FindPSOverrideEntry (NBPtr->RefPtr->PlatformMemoryConfiguration, PSO_MEMCLK_DIS, NBPtr->MCTPtr->SocketId, NBPtr->Dct); - if (MemClkDisMap == NULL) { - MemClkDisMap = NBPtr->ChannelPtr->MemClkDisMap; - } - - // Turn off unused clocks - CsPresent = NBPtr->DCTPtr->Timings.CsPresent; - - for (i = 0; i < 8; i++) { - if ((CsPresent & MemClkDisMap[i]) == 0) { - MemClkDis |= (UINT8) (1 << i); - } - } - - // Turn off unused chiplets - for (i = 0; i < 3; i++) { - if (((MemClkDis >> (i * 2)) & 0x3) == 0x3) { - MemNSetBitFieldNb (NBPtr, BFPhyClkConfig0 + i, 0x0010); - } - } - } - } - MemNSetBitFieldNb (NBPtr, BFMemClkDis, MemClkDis); - MemFInitTableDrive (NBPtr, MTAfterPlatformSpec); - } - - return (BOOLEAN) (NBPtr->MCTPtr->ErrCode < AGESA_FATAL); -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * - * This function disables the DCT and mem clock - * - * - * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK - * - */ - -VOID -MemNDisableDCTNb ( - IN OUT MEM_NB_BLOCK *NBPtr - ) -{ - MemNSetBitFieldNb (NBPtr, BFCKETri, 0x03); - MemNSetBitFieldNb (NBPtr, BFODTTri, 0x0F); - MemNSetBitFieldNb (NBPtr, BFChipSelTri, 0xFF); - - // To maximize power savings when DisDramInterface=1b, - // all of the MemClkDis bits should also be set. - // - MemNSetBitFieldNb (NBPtr, BFMemClkDis, 0xFF); - MemNSetBitFieldNb (NBPtr, BFDisDramInterface, 1); -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * - * This function disables the DCT and mem clock for client NB - * - * - * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK - * - */ - -VOID -MemNDisableDCTClientNb ( - IN OUT MEM_NB_BLOCK *NBPtr - ) -{ - MemNSetBitFieldNb (NBPtr, BFCKETri, 0x03); - MemNSetBitFieldNb (NBPtr, BFODTTri, 0x0F); - MemNSetBitFieldNb (NBPtr, BFChipSelTri, 0xFF); - - //Wait for 24 MEMCLKs - MemNWaitXMemClksNb (NBPtr, 24); - - // To maximize power savings when DisDramInterface=1b, - // all of the MemClkDis bits should also be set. - // - MemNSetBitFieldNb (NBPtr, BFMemClkDis, 0xFF); - - MemNSetBitFieldNb (NBPtr, BFDramPhyStatusReg, 0x80800000); - - MemNSetBitFieldNb (NBPtr, BFDisDramInterface, 1); -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * - * This function disables the DCT and mem clock for UNB - * - * - * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK - * - */ - -VOID -MemNDisableDCTUnb ( - IN OUT MEM_NB_BLOCK *NBPtr - ) -{ - MemNSetBitFieldNb (NBPtr, BFCKETri, 0x03); - MemNSetBitFieldNb (NBPtr, BFODTTri, 0x0F); - MemNSetBitFieldNb (NBPtr, BFChipSelTri, 0xFF); - - //Wait for 24 MEMCLKs - MemNWaitXMemClksNb (NBPtr, 24); - - // To maximize power savings when DisDramInterface=1b, - // all of the MemClkDis bits should also be set. - // - MemNSetBitFieldNb (NBPtr, BFMemClkDis, 0xFF); - - MemNSetBitFieldNb (NBPtr, BFDisDramInterface, 1); - - if (NBPtr->Dct == 0) { - MemNSetBitFieldNb (NBPtr, BFPhyPSMasterChannel, 0x100); - } -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * - * This function initializes the DRAM devices on all DCTs at the same time - * - * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK - * - */ - -VOID -MemNStartupDCTNb ( - IN OUT MEM_NB_BLOCK *NBPtr - ) -{ - // 1. Ensure F2x[1, 0]9C_x08[DisAutoComp] = 1. - // 2. BIOS waits 5 us for the disabling of the compensation engine to complete. - // DisAutoComp is still being set since InitPhyComp - - if (NBPtr->MCTPtr->NodeMemSize != 0) { - // Init MemClk frequency - MemNBrdcstSetNb (NBPtr, BFMemClkFreqVal, 1); - - - AGESA_TESTPOINT (TpProcMemBeforeDramInit, &(NBPtr->MemPtr->StdHeader)); - NBPtr->MemNBeforeDramInitNb (NBPtr); - IDS_HDT_CONSOLE (MEM_FLOW, "\nMemClkFreq: %d MHz\n", NBPtr->DCTPtr->Timings.Speed); - AGESA_TESTPOINT (TpProcMemDramInit, &(NBPtr->MemPtr->StdHeader)); - NBPtr->FeatPtr->DramInit (NBPtr->TechPtr); - } - - // 7. Program F2x[1, 0]9C_x08[DisAutoComp] = 0. - // 8. BIOS must wait 750 us for the phy compensation engine - // to reinitialize. - // DisAutoComp will be cleared after DramEnabled turns to 1 - -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * - * This function initializes the DRAM devices on all DCTs at the same time - * - * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK - * - */ - -VOID -MemNStartupDCTUnb ( - IN OUT MEM_NB_BLOCK *NBPtr - ) -{ - UINT8 Dct; - UINT16 FinalPllLockTime; - - if (NBPtr->MCTPtr->NodeMemSize != 0) { - // Update NB frequency for startup DDR speed - NBPtr->ChangeNbFrequency (NBPtr); - - if (NBPtr->FamilySpecificHook[ForcePhyToM0] (NBPtr, NULL)) { - // Program D18F2x[1,0]9C_x0000_000B = 80000000h. #109999. - MemNBrdcstSetNb (NBPtr, BFDramPhyStatusReg, 0x80000000); - - // Program D18F2x[1,0]9C_x0D0F_E013[PllRegWaitTime] = 0118h. #194060. - MemNBrdcstSetNb (NBPtr, BFPllRegWaitTime, 0x118); - } - - // Phy Voltage Level Programming - MemNPhyVoltageLevelNb (NBPtr); - - // Run frequency change sequence - MemNBrdcstSetNb (NBPtr, BFPllLockTime, NBPtr->FreqChangeParam->PllLockTimeDefault); - MemNBrdcstSetNb (NBPtr, BFMemClkFreq, NBPtr->GetMemClkFreqId (NBPtr, NBPtr->DCTPtr->Timings.Speed)); - NBPtr->FamilySpecificHook[SetSkewMemClk] (NBPtr, NULL); - NBPtr->ProgramNbPsDependentRegs (NBPtr); - MemNBrdcstSetNb (NBPtr, BFMemClkFreqVal, 1); - MemNPollBitFieldNb (NBPtr, BFFreqChgInProg, 0, PCI_ACCESS_TIMEOUT, TRUE); - FinalPllLockTime = 0xF; - NBPtr->FamilySpecificHook[AfterMemClkFreqVal] (NBPtr, &FinalPllLockTime); - if (!NBPtr->IsSupported[CsrPhyPllPdEn]) { - // IF (D18F2x[1,0]9C_x0D0F_E00A[CsrPhySrPllPdMode]==0) THEN program - // D18F2x[1,0]9C_x0D0F_E006[PllLockTime] = 0Fh - MemNBrdcstSetNb (NBPtr, BFPllLockTime, FinalPllLockTime); - } - - NBPtr->FamilySpecificHook[BeforePhyFenceTraining] (NBPtr, NBPtr); - - for (Dct = 0; Dct < NBPtr->DctCount; Dct++) { - MemNSwitchDCTNb (NBPtr, Dct); - if (NBPtr->DCTPtr->Timings.DctMemSize != 0) { - IDS_HDT_CONSOLE (MEM_STATUS, "\tDct %d\n", Dct); - - // Phy fence programming - AGESA_TESTPOINT (TpProcMemPhyFenceTraining, &(NBPtr->MemPtr->StdHeader)); - NBPtr->PhyFenceTraining (NBPtr); - - // Phy compensation initialization - AGESA_TESTPOINT (TPProcMemPhyCompensation, &(NBPtr->MemPtr->StdHeader)); - NBPtr->MemNInitPhyComp (NBPtr); - MemProcessConditionalOverrides (NBPtr->RefPtr->PlatformMemoryConfiguration, NBPtr, PSO_ACTION_SLEWRATE, ALL_DIMMS); - } - } - - AGESA_TESTPOINT (TpProcMemBeforeDramInit, &(NBPtr->MemPtr->StdHeader)); - NBPtr->MemNBeforeDramInitNb (NBPtr); - - AGESA_TESTPOINT (TpProcMemDramInit, &(NBPtr->MemPtr->StdHeader)); - IDS_HDT_CONSOLE (MEM_FLOW, "\nMemClkFreq: %d MHz\n", NBPtr->DCTPtr->Timings.Speed); - NBPtr->FeatPtr->DramInit (NBPtr->TechPtr); - } -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * MemNChangeFrequencyHy: - * - * This function change MemClk frequency to the value that is specified by DCTPtr->Timings.Speed - * - * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK - * - */ - -VOID -MemNChangeFrequencyNb ( - IN OUT MEM_NB_BLOCK *NBPtr - ) -{ - MEM_TECH_BLOCK *TechPtr; - UINT8 Dct; - UINT8 ChipSel; - UINT32 Dummy; - - TechPtr = NBPtr->TechPtr; - if (NBPtr->IsSupported[CheckDisDllShutdownSR] && !(NBPtr->IsSupported[SetDllShutDown])) { - // #107421 - MemNBrdcstSetNb (NBPtr, BFDisDllShutdownSR, 1); - } - - //Program F2x[1,0]90[EnterSelfRefresh]=1. - //Wait until the hardware resets F2x[1,0]90[EnterSelfRefresh]=0. - MemNBrdcstSetNb (NBPtr, BFEnterSelfRef, 1); - MemNPollBitFieldNb (NBPtr, BFEnterSelfRef, 0, PCI_ACCESS_TIMEOUT, TRUE); - - //Program F2x9C_x08[DisAutoComp]=1 - MemNSwitchDCTNb (NBPtr, 0); - MemNSetBitFieldNb (NBPtr, BFDisAutoComp, 1); - - //Program F2x[1, 0]94[MemClkFreqVal] = 0. - MemNBrdcstSetNb (NBPtr, BFMemClkFreqVal, 0); - - //Program F2x[1, 0]94[MemClkFreq] to specify the target MEMCLK frequency. - MemNBrdcstSetNb (NBPtr, BFMemClkFreq, NBPtr->GetMemClkFreqId (NBPtr, NBPtr->DCTPtr->Timings.Speed)); - - IDS_OPTION_HOOK (IDS_BEFORE_MEM_FREQ_CHG, NBPtr, &(NBPtr->MemPtr->StdHeader)); - //Program F2x[1, 0]94[MemClkFreqVal] = 1. - MemNBrdcstSetNb (NBPtr, BFMemClkFreqVal, 1); - - //Wait until F2x[1, 0]94[FreqChgInProg]=0. - MemNPollBitFieldNb (NBPtr, BFFreqChgInProg, 0, PCI_ACCESS_TIMEOUT, TRUE); - - if (NBPtr->IsSupported[CheckPhyFenceTraining]) { - //Perform Phy Fence retraining after frequency changed - AGESA_TESTPOINT (TpProcMemPhyFenceTraining, &(NBPtr->MemPtr->StdHeader)); - for (Dct = 0; Dct < NBPtr->DctCount; Dct++) { - MemNSwitchDCTNb (NBPtr, Dct); - if (NBPtr->DCTPtr->Timings.DctMemSize != 0) { - IDS_HDT_CONSOLE (MEM_STATUS, "\tDct %d\n", Dct); - AGESA_TESTPOINT (TpProcMemPhyFenceTraining, &(NBPtr->MemPtr->StdHeader)); - MemNPhyFenceTrainingNb (NBPtr); - } - } - } - - //Program F2x9C_x08[DisAutoComp]=0 - MemNSwitchDCTNb (NBPtr, 0); - MemNSetBitFieldNb (NBPtr, BFDisAutoComp, 0); - - //Program F2x[1,0]90[ExitSelfRef]=1 for both DCTs. - //Wait until the hardware resets F2x[1, 0]90[ExitSelfRef]=0. - MemNBrdcstSetNb (NBPtr, BFExitSelfRef, 1); - MemNPollBitFieldNb (NBPtr, BFExitSelfRef, 0, PCI_ACCESS_TIMEOUT, TRUE); - - if (NBPtr->MCTPtr->Status[SbRegistered]) { - for (Dct = 0; Dct < NBPtr->DctCount; Dct++) { - MemNSwitchDCTNb (NBPtr, Dct); - if (NBPtr->DCTPtr->Timings.DctMemSize != 0) { - TechPtr->FreqChgCtrlWrd (TechPtr); - } - } - } - - //wait for 500 MCLKs after ExitSelfRef, 500*2.5ns=1250ns - MemNWaitXMemClksNb (NBPtr, 500); - - if (NBPtr->IsSupported[CheckDisDllShutdownSR] && !(NBPtr->IsSupported[SetDllShutDown])) { - // #107421 - MemNBrdcstSetNb (NBPtr, BFDisDllShutdownSR, 0); - } - - for (Dct = 0; Dct < NBPtr->DctCount; Dct++) { - IDS_HDT_CONSOLE (MEM_STATUS, "\tDct %d\n", Dct); - MemNSwitchDCTNb (NBPtr, Dct); - if (NBPtr->DCTPtr->Timings.DctMemSize != 0) { - - //9.Configure the DCT to send initialization MR commands: - // BIOS must reprogram Twr, Tcwl, and Tcl based on the new MEMCLK frequency. - // Program F2x[1, 0]7C similar to step #2 in Pass 1 above for the new Dimm values. - TechPtr->AutoCycTiming (TechPtr); - if (!MemNPlatformSpecNb (NBPtr)) { - IDS_ERROR_TRAP; - } - - for (ChipSel = 0; ChipSel < MAX_CS_PER_CHANNEL; ChipSel++) { - if (NBPtr->IsSupported[CheckGetMCTSysAddr]) { - if (MemNGetMCTSysAddrNb (NBPtr, ChipSel, &Dummy)) { - // if chip select present - TechPtr->SendAllMRCmds (TechPtr, ChipSel); - // NOTE: wait 512 clocks for DLL-relock - MemUWait10ns (50000, NBPtr->MemPtr); // wait 500us - } - } - if (NBPtr->IsSupported[CheckSendAllMRCmds]) { - if (MemNGetMCTSysAddrNb (NBPtr, ChipSel, &Dummy)) { - // if chip select present - TechPtr->SendAllMRCmds (TechPtr, ChipSel); - } - } - } - if ((NBPtr->DCTPtr->Timings.Speed == DDR1600_FREQUENCY) && (NBPtr->IsSupported[CheckDllSpeedUp])) { - MemNSetBitFieldNb (NBPtr, BFPhy0x0D080F11, (MemNGetBitFieldNb (NBPtr, BFPhy0x0D080F11) | 0x2000)); - MemNSetBitFieldNb (NBPtr, BFPhy0x0D080F10, (MemNGetBitFieldNb (NBPtr, BFPhy0x0D080F10) | 0x2000)); - MemNSetBitFieldNb (NBPtr, BFPhy0x0D088F30, (MemNGetBitFieldNb (NBPtr, BFPhy0x0D088F30) | 0x2000)); - MemNSetBitFieldNb (NBPtr, BFPhy0x0D08C030, (MemNGetBitFieldNb (NBPtr, BFPhy0x0D08C030) | 0x2000)); - if (Dct == 0) { - MemNSetBitFieldNb (NBPtr, BFPhy0x0D082F30, (MemNGetBitFieldNb (NBPtr, BFPhy0x0D082F30) | 0x2000)); - } - // NOTE: wait 512 clocks for DLL-relock - MemUWait10ns (50000, NBPtr->MemPtr); // wait 500us - } - } - } - // Re-enable phy compensation since it had been disabled during InitPhyComp - MemNSwitchDCTNb (NBPtr, 0); - MemNSetBitFieldNb (NBPtr, BFDisAutoComp, 0); - - MemFInitTableDrive (NBPtr, MTAfterFreqChg); -} - - -/* -----------------------------------------------------------------------------*/ -/** - * - * This function ramp up frequency the next level if it have not reached - * its TargetSpeed yet. - * - * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK - * - * @return TRUE - No fatal error occurs. - * @return FALSE - Fatal error occurs. - */ - -BOOLEAN -MemNRampUpFrequencyNb ( - IN OUT MEM_NB_BLOCK *NBPtr - ) -{ - CONST UINT16 FreqList[] = { - DDR400_FREQUENCY, - DDR533_FREQUENCY, - DDR667_FREQUENCY, - DDR800_FREQUENCY, - DDR1066_FREQUENCY, - DDR1333_FREQUENCY, - DDR1600_FREQUENCY, - DDR1866_FREQUENCY - }; - UINT8 Dct; - UINT8 i; - UINT16 NewSpeed; - DIE_STRUCT *MCTPtr; - - MCTPtr = NBPtr->MCTPtr; - - // Do not change frequency when it is already at TargetSpeed - if (NBPtr->DCTPtr->Timings.Speed == NBPtr->DCTPtr->Timings.TargetSpeed) { - return TRUE; - } - - // Find the next supported frequency level - NewSpeed = NBPtr->DCTPtr->Timings.TargetSpeed; - for (i = 0; i < (GET_SIZE_OF (FreqList) - 1); i++) { - if (NBPtr->DCTPtr->Timings.Speed == FreqList[i]) { - NewSpeed = FreqList[i + 1]; - break; - } - } - ASSERT (i < (GET_SIZE_OF (FreqList) - 1)); - ASSERT (NewSpeed <= NBPtr->DCTPtr->Timings.TargetSpeed); - - // BIOS must program both DCTs to the same frequency. - IDS_HDT_CONSOLE (MEM_FLOW, "\nMemClkFreq changed: %d MHz", NBPtr->DCTPtr->Timings.Speed); - for (Dct = 0; Dct < MCTPtr->DctCount; Dct++) { - NBPtr->SwitchDCT (NBPtr, Dct); - NBPtr->DCTPtr->Timings.Speed = NewSpeed; - } - IDS_HDT_CONSOLE (MEM_FLOW, " -> %d MHz", NewSpeed); - - NBPtr->ChangeFrequency (NBPtr); - - return (BOOLEAN) (MCTPtr->ErrCode < AGESA_FATAL); -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * This function ramp up frequency to target frequency - * - * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK - * - * @return TRUE - No fatal error occurs. - * @return FALSE - Fatal error occurs. - */ - -BOOLEAN -MemNRampUpFrequencyUnb ( - IN OUT MEM_NB_BLOCK *NBPtr - ) -{ - UINT8 Dct; - DIE_STRUCT *MCTPtr; - - MCTPtr = NBPtr->MCTPtr; - - // Do not change frequency when it is already at TargetSpeed - if (NBPtr->DCTPtr->Timings.Speed == NBPtr->DCTPtr->Timings.TargetSpeed) { - return TRUE; - } - - // BIOS must program both DCTs to the same frequency. - IDS_HDT_CONSOLE (MEM_FLOW, "\nMemClkFreq changed: %d MHz", NBPtr->DCTPtr->Timings.Speed); - for (Dct = 0; Dct < MCTPtr->DctCount; Dct++) { - NBPtr->SwitchDCT (NBPtr, Dct); - NBPtr->DCTPtr->Timings.Speed = NBPtr->DCTPtr->Timings.TargetSpeed; - } - IDS_HDT_CONSOLE (MEM_FLOW, " -> %d MHz", NBPtr->DCTPtr->Timings.TargetSpeed); - - NBPtr->ChangeFrequency (NBPtr); - - return (BOOLEAN) (MCTPtr->ErrCode < AGESA_FATAL); -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * - * This function uses calculated values from DCT.Timings structure to - * program its registers. - * - * - * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK - * - */ - -VOID -MemNProgramCycTimingsNb ( - IN OUT MEM_NB_BLOCK *NBPtr - ) -{ - CONST CTENTRY TmgAdjTab[] = { - // BitField, Min, Max, Bias, Ratio_x2 - {BFTcl, 4, 12, 4, 2}, - {BFTrcd, 5, 12, 5, 2}, - {BFTrp, 5, 12, 5, 2}, - {BFTrtp, 4, 7, 4, 2}, - {BFTras, 15, 30, 15, 2}, - {BFTrc, 11, 42, 11, 2}, - {BFTwrDDR3, 5, 12, 4, 2}, - {BFTrrd, 4, 7, 4, 2}, - {BFTwtr, 4, 7, 4, 2}, - {BFFourActWindow, 16, 32, 14, 1} - }; - - DCT_STRUCT *DCTPtr; - UINT8 *MiniMaxTmg; - UINT8 *MiniMaxTrfc; - UINT8 Value8; - UINT8 j; - BIT_FIELD_NAME BitField; - - DCTPtr = NBPtr->DCTPtr; - - //====================================================================== - // Program turnaround timings to their max during DRAM init and training - //====================================================================== - // - MemNSetBitFieldNb (NBPtr, BFNonSPD, 0x28FF); - - MemNSetBitFieldNb (NBPtr, BFNonSPDHi, 0x2A); - - //====================================================================== - // Program DRAM Timing values - //====================================================================== - // - MiniMaxTmg = &DCTPtr->Timings.CasL; - for (j = 0; j < GET_SIZE_OF (TmgAdjTab); j++) { - BitField = TmgAdjTab[j].BitField; - - if (MiniMaxTmg[j] < TmgAdjTab[j].Min) { - MiniMaxTmg[j] = TmgAdjTab[j].Min; - } else if (MiniMaxTmg[j] > TmgAdjTab[j].Max) { - MiniMaxTmg[j] = TmgAdjTab[j].Max; - } - - Value8 = (UINT8) MiniMaxTmg[j]; - - if (BitField == BFTwrDDR3) { - Value8 = (Value8 == 10) ? 9 : (Value8 >= 11) ? 10 : Value8; - } else if (BitField == BFTrtp) { - Value8 = (DCTPtr->Timings.Speed <= DDR1066_FREQUENCY) ? 4 : (DCTPtr->Timings.Speed == DDR1333_FREQUENCY) ? 5 : 6; - } - - Value8 = Value8 - TmgAdjTab[j].Bias; - Value8 = (Value8 * TmgAdjTab[j].Ratio_x2) >> 1; - - ASSERT ((BitField == BFTcl ) ? (Value8 <= 8) : - (BitField == BFTrcd) ? (Value8 <= 7) : - (BitField == BFTrp ) ? (Value8 <= 7) : - (BitField == BFTrtp) ? (Value8 <= 3) : - (BitField == BFTras) ? (Value8 <= 15) : - (BitField == BFTrc ) ? (Value8 <= 31) : - (BitField == BFTrrd) ? (Value8 <= 3) : - (BitField == BFTwtr) ? (Value8 <= 3) : - (BitField == BFTwrDDR3) ? ((Value8 >= 1) && (Value8 <= 6)) : - (BitField == BFFourActWindow) ? ((Value8 >= 1) && (Value8 <= 9)) : FALSE); - MemNSetBitFieldNb (NBPtr, BitField, Value8); - } - - MiniMaxTrfc = &DCTPtr->Timings.Trfc0; - for (j = 0; j < 4; j++) { - ASSERT (MiniMaxTrfc[j] <= 4); - MemNSetBitFieldNb (NBPtr, BFTrfc0 + j, MiniMaxTrfc[j]); - } - - MemNSetBitFieldNb (NBPtr, BFTcwl, ((DCTPtr->Timings.Speed >= DDR800_FREQUENCY) ? - (NBPtr->GetMemClkFreqId (NBPtr, DCTPtr->Timings.Speed) - 3) : 0)); - - MemNSetBitFieldNb (NBPtr, BFTref, 2); // 7.8 us - - //====================================================================== - // DRAM MRS Register, set ODT - //====================================================================== - // - // DrvImpCtrl: drive impedance control.01b(34 ohm driver; Ron34 = Rzq/7) - MemNSetBitFieldNb (NBPtr, BFDrvImpCtrl, 1); - - // burst length control - if (NBPtr->MCTPtr->Status[Sb128bitmode]) { - MemNSetBitFieldNb (NBPtr, BFBurstCtrl, 2); - } - - // ASR=1, auto self refresh; SRT=0 - MemNSetBitFieldNb (NBPtr, BFASR, 1); -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * - * This function uses calculated values from DCT.Timings structure to - * program its registers. - * - * - * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK - * - */ - -VOID -MemNProgramCycTimingsClientNb ( - IN OUT MEM_NB_BLOCK *NBPtr - ) -{ - CONST CTENTRY TmgAdjTab[] = { - // BitField, Min, Max, Bias, Ratio_x2 - {BFTcl, 5, 14, 4, 2}, - {BFTrcd, 5, 14, 5, 2}, - {BFTrp, 5, 14, 5, 2}, - {BFTrtp, 4, 8, 4, 2}, - {BFTras, 15, 36, 15, 2}, - {BFTrc, 20, 49, 11, 2}, - {BFTwrDDR3, 5, 16, 4, 2}, - {BFTrrd, 4, 8, 4, 2}, - {BFTwtr, 4, 8, 4, 2}, - {BFFourActWindow, 16, 40, 14, 1} - }; - - DCT_STRUCT *DCTPtr; - UINT8 *MiniMaxTmg; - UINT8 *MiniMaxTrfc; - UINT8 Value8; - UINT8 j; - UINT8 Tcwl; - UINT8 Trcd; - INT32 TCK_ps; - BIT_FIELD_NAME BitField; - - DCTPtr = NBPtr->DCTPtr; - - //====================================================================== - // Program DRAM Timing values - //====================================================================== - // - MiniMaxTmg = &DCTPtr->Timings.CasL; - for (j = 0; j < GET_SIZE_OF (TmgAdjTab); j++) { - BitField = TmgAdjTab[j].BitField; - - if ((BitField == BFTrc) && NBPtr->IsSupported[AdjustTrc]) { - MiniMaxTmg[j] = (MiniMaxTmg[j] > 5) ? (MiniMaxTmg[j] - 5) : 0; - } - - if (MiniMaxTmg[j] < TmgAdjTab[j].Min) { - MiniMaxTmg[j] = TmgAdjTab[j].Min; - } else if (MiniMaxTmg[j] > TmgAdjTab[j].Max) { - MiniMaxTmg[j] = TmgAdjTab[j].Max; - } - - Value8 = (UINT8) MiniMaxTmg[j]; - - if (BitField == BFTwrDDR3) { - if (NBPtr->IsSupported[AdjustTwr]) { - Value8 ++; - } - Value8 = (Value8 >= 10) ? (((Value8 + 1) / 2) + 4) : Value8; - } - - Value8 = Value8 - TmgAdjTab[j].Bias; - Value8 = (Value8 * TmgAdjTab[j].Ratio_x2) >> 1; - - ASSERT ((BitField == BFTcl ) ? ((Value8 >= 1) && (Value8 <= 10)) : - (BitField == BFTrcd) ? (Value8 <= 9) : - (BitField == BFTrp ) ? (Value8 <= 9) : - (BitField == BFTrtp) ? (Value8 <= 4) : - (BitField == BFTras) ? (Value8 <= 21) : - (BitField == BFTrc ) ? ((Value8 >= 9) && (Value8 <= 38)) : - (BitField == BFTrrd) ? (Value8 <= 4) : - (BitField == BFTwtr) ? (Value8 <= 4) : - (BitField == BFTwrDDR3) ? (Value8 <= 7) : - (BitField == BFFourActWindow) ? ((Value8 >= 1) && (Value8 <= 13)) : FALSE); - MemNSetBitFieldNb (NBPtr, BitField, Value8); - } - - MiniMaxTrfc = &DCTPtr->Timings.Trfc0; - for (j = 0; j < 4; j++) { - ASSERT (MiniMaxTrfc[j] <= 5); - MemNSetBitFieldNb (NBPtr, BFTrfc0 + j, MiniMaxTrfc[j]); - } - - Tcwl = (UINT8) (DCTPtr->Timings.Speed / 133) + 2; - MemNSetBitFieldNb (NBPtr, BFTcwl, ((Tcwl > 5) ? (Tcwl - 5) : 0)); - - MemNSetBitFieldNb (NBPtr, BFTref, 2); // Tref = 7.8 us - - // Skid buffer can only be programmed once before Dram init - if (NBPtr->DCTPtr->Timings.Speed == DDR800_FREQUENCY) { - TCK_ps = 1000500 / DCTPtr->Timings.TargetSpeed; - Trcd = (UINT8) ((((1000 / 40) * (UINT32)DCTPtr->Timings.DIMMTrcd) + TCK_ps - 1) / TCK_ps); - MemNSetBitFieldNb (NBPtr, BFDbeSkidBufDis, (Trcd > 10) ? 0 : 1); - } - - MemNSetBitFieldNb (NBPtr, BFRdOdtTrnOnDly, (DCTPtr->Timings.CasL > Tcwl) ? (DCTPtr->Timings.CasL - Tcwl) : 0); - -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * - * This function uses calculated values from DCT.Timings structure to - * program its registers for UNB - * - * - * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK - * - */ - -VOID -MemNProgramCycTimingsUnb ( - IN OUT MEM_NB_BLOCK *NBPtr - ) -{ - CONST CTENTRY TmgAdjTab[] = { - // BitField, Min, Max, Bias, Ratio_x2 - {BFTcl, 5, 14, 0, 2}, - {BFTrcd, 2, 19, 0, 2}, - {BFTrp, 2, 19, 0, 2}, - {BFTrtp, 4, 10, 0, 2}, - {BFTras, 8, 40, 0, 2}, - {BFTrc, 10, 56, 0, 2}, - {BFTwrDDR3, 5, 16, 0, 2}, - {BFTrrd, 1, 9, 0, 2}, - {BFTwtr, 4, 9, 0, 2}, - {BFFourActWindow, 6, 42, 0, 2} - }; - - DCT_STRUCT *DCTPtr; - UINT8 *MiniMaxTmg; - UINT8 *MiniMaxTrfc; - UINT8 Value8; - UINT8 j; - UINT8 Tcwl; - UINT8 RdOdtTrnOnDly; - BIT_FIELD_NAME BitField; - - DCTPtr = NBPtr->DCTPtr; - - //====================================================================== - // Program DRAM Timing values - //====================================================================== - // - MiniMaxTmg = &DCTPtr->Timings.CasL; - for (j = 0; j < GET_SIZE_OF (TmgAdjTab); j++) { - BitField = TmgAdjTab[j].BitField; - - if (MiniMaxTmg[j] < TmgAdjTab[j].Min) { - MiniMaxTmg[j] = TmgAdjTab[j].Min; - } else if (MiniMaxTmg[j] > TmgAdjTab[j].Max) { - MiniMaxTmg[j] = TmgAdjTab[j].Max; - } - - Value8 = (UINT8) MiniMaxTmg[j]; - - if (BitField == BFTwrDDR3) { - if ((Value8 > 8) && ((Value8 & 1) != 0)) { - ASSERT (FALSE); - } - } - MemNSetBitFieldNb (NBPtr, BitField, Value8); - } - - MiniMaxTrfc = &DCTPtr->Timings.Trfc0; - for (j = 0; j < 4; j++) { - if ((NBPtr->DCTPtr->Timings.CsPresent & (3 << (j * 2))) != 0) { - ASSERT (MiniMaxTrfc[j] <= 4); - MemNSetBitFieldNb (NBPtr, BFTrfc0 + j, MiniMaxTrfc[j]); - } - } - - Tcwl = (UINT8) (DCTPtr->Timings.Speed / 133) + 2; - MemNSetBitFieldNb (NBPtr, BFTcwl, ((Tcwl > 5) ? Tcwl : 5)); - - MemNSetBitFieldNb (NBPtr, BFTref, 2); // 7.8 us - - RdOdtTrnOnDly = (DCTPtr->Timings.CasL > Tcwl) ? (DCTPtr->Timings.CasL - Tcwl) : 0; - NBPtr->FamilySpecificHook[CalRdOdtTrnOnDlyLrDimm] (NBPtr, &RdOdtTrnOnDly); - MemNSetBitFieldNb (NBPtr, BFRdOdtTrnOnDly, RdOdtTrnOnDly); - - // - // Program Tmod - // - MemNSetBitFieldNb (NBPtr, BFTmod, (DCTPtr->Timings.Speed == DDR1866_FREQUENCY) ? 0xE : 0xC ); -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * - * This function gets platform specific settings for the current channel - * - * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK - * - * @return TRUE - All platform types defined have initialized successfully - * @return FALSE - At least one of the platform types gave not been initialized successfully - */ - -BOOLEAN -MemNGetPlatformCfgNb ( - IN OUT MEM_NB_BLOCK *NBPtr - ) -{ - UINT8 p; - - for (p = 0; p < MAX_PLATFORM_TYPES; p++) { - ASSERT (NBPtr->MemPtr->GetPlatformCfg[p] != NULL); - if (NBPtr->MemPtr->GetPlatformCfg[p] (NBPtr->MemPtr, NBPtr->MCTPtr->SocketId, NBPtr->ChannelPtr) == AGESA_SUCCESS) { - break; - } - } - return (p < MAX_PLATFORM_TYPES); -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * - * This function retrieves the Max latency parameters - * - * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK - * - * @param[in] *MinDlyPtr - Pointer to variable to store the Minimum Delay value - * @param[in] *MaxDlyPtr - Pointer to variable to store the Maximum Delay value - * @param[in] *DlyBiasPtr - Pointer to variable to store Delay Bias value - * @param[in] MaxRcvEnDly - Maximum receiver enable delay value - */ - -VOID -MemNGetMaxLatParamsNb ( - IN OUT MEM_NB_BLOCK *NBPtr, - IN UINT16 MaxRcvEnDly, - IN OUT UINT16 *MinDlyPtr, - IN OUT UINT16 *MaxDlyPtr, - IN OUT UINT16 *DlyBiasPtr - ) -{ - *MinDlyPtr = (MemNTotalSyncComponentsNb (NBPtr) + (MaxRcvEnDly >> 5)) * 2; - MemNQuarterMemClk2NClkNb (NBPtr, MinDlyPtr); - - *MaxDlyPtr = 0x3FF; - - *DlyBiasPtr = 4; - MemNQuarterMemClk2NClkNb (NBPtr, DlyBiasPtr); // 1 MEMCLK Margin - - *DlyBiasPtr += 1; // add 1 NCLK -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * - * This function sets the maximum round-trip latency in the system from the processor to the DRAM - * devices and back. - * - * - * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK - * @param[in] MaxRcvEnDly - Maximum receiver enable delay value - * - */ - -VOID -MemNSetMaxLatencyNb ( - IN OUT MEM_NB_BLOCK *NBPtr, - IN UINT16 MaxRcvEnDly - ) -{ - UINT16 SubTotal; - - AGESA_TESTPOINT (TpProcMemRcvrCalcLatency, &(NBPtr->MemPtr->StdHeader)); - - SubTotal = 0xC8; // init value for MaxRdLat used in training - - - if (MaxRcvEnDly != 0xFFFF) { - // Get all sync components BKDG steps 1-5 - SubTotal = MemNTotalSyncComponentsNb (NBPtr); - - // Add the maximum (worst case) delay value of DqsRcvEnGrossDelay - // that exists across all DIMMs and byte lanes. - // - SubTotal += MaxRcvEnDly >> 5; - - - // Add 14.5 to the sub-total. 14.5 represents part of the processor - // specific constant delay value in the DRAM clock domain. - // - SubTotal <<= 1; // scale 1/2 MemClk to 1/4 MemClk - SubTotal += 29; // add 14.5 1/2 MemClk - - // Convert the sub-total (in 1/2 MEMCLKs) to northbridge clocks (NCLKs) - // as follows (assuming DDR400 and assuming that no P-state or link speed - // changes have occurred). - // - MemNQuarterMemClk2NClkNb (NBPtr, &SubTotal); - - // Add 2 NCLKs to the sub-total. 2 represents part of the processor - // specific constant value in the northbridge clock domain. - // - SubTotal += 2; - } - - NBPtr->DCTPtr->Timings.MaxRdLat = SubTotal; - // Program the F2x[1, 0]78[MaxRdLatency] register with the total delay value - IDS_HDT_CONSOLE (MEM_FLOW, "\t\tMaxRdLat: %03x\n", SubTotal); - MemNSetBitFieldNb (NBPtr, BFMaxLatency, SubTotal); -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * - * This function sends the ZQCL command - * - * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK - * - */ - -VOID -MemNSendZQCmdNb ( - IN OUT MEM_NB_BLOCK *NBPtr - ) -{ - // 1.Program MrsAddress[10]=1 - MemNSetBitFieldNb (NBPtr, BFMrsAddress, (UINT32)1 << 10); - - // 2.Set SendZQCmd=1 - MemNSetBitFieldNb (NBPtr, BFSendZQCmd, 1); - - // 3.Wait for SendZQCmd=0 - MemNPollBitFieldNb (NBPtr, BFSendZQCmd, 0, PCI_ACCESS_TIMEOUT, FALSE); - - // 4.Wait 512 MEMCLKs - MemNWaitXMemClksNb (NBPtr, 512); -} - - -/*---------------------------------------------------------------------------- - * LOCAL FUNCTIONS - * - *---------------------------------------------------------------------------- - */ - -/* -----------------------------------------------------------------------------*/ -/** - * - * - * This function is used to create the DRAM map - * - * - * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK - */ - -VOID -STATIC -MemNAfterStitchMemNb ( - IN OUT MEM_NB_BLOCK *NBPtr - ) -{ - if (NBPtr->MCTPtr->GangedMode) { - NBPtr->MCTPtr->NodeMemSize = NBPtr->DCTPtr->Timings.DctMemSize; - NBPtr->MCTPtr->NodeSysLimit = NBPtr->MCTPtr->NodeMemSize - 1; - NBPtr->MCTPtr->DctData[1].Timings.CsPresent = NBPtr->DCTPtr->Timings.CsPresent; - NBPtr->MCTPtr->DctData[1].Timings.CsEnabled = NBPtr->DCTPtr->Timings.CsEnabled; - NBPtr->MCTPtr->DctData[1].Timings.DctMemSize = NBPtr->DCTPtr->Timings.DctMemSize; - } else { - // In unganged mode, add DCT0 and DCT1 to NodeMemSize - NBPtr->MCTPtr->NodeMemSize += NBPtr->DCTPtr->Timings.DctMemSize; - NBPtr->MCTPtr->NodeSysLimit = NBPtr->MCTPtr->NodeMemSize - 1; - } -} - - -/* -----------------------------------------------------------------------------*/ -/** - * - * - * This function Return the binary value of tfaw associated with - * the index k - * - * @param[in] k value - * - * @return F[k], in Binary MHz. - */ - -UINT8 -MemNGet1KTFawTkNb ( - IN UINT8 k - ) -{ - CONST UINT8 Tab1KTfawTK[] = {0, 8, 10, 13, 14, 19}; - ASSERT (k <= 5); - return Tab1KTfawTK[k]; -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * - * This function Return the binary value of the 2KTFaw associated with - * the index k - * - * @param[in] k value - * - * @return 2KTFaw converted based on k. - */ - -UINT8 -MemNGet2KTFawTkNb ( - IN UINT8 k - ) -{ - CONST UINT8 Tab2KTfawTK[] = {0, 10, 14, 17, 18, 24}; - ASSERT (k <= 5); - return Tab2KTfawTK[k]; -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * - * This function converts the sub-total (in 1/4 MEMCLKs) to northbridge clocks (NCLKs) - * (assuming DDR400 and assuming that no P-state or link speed - * changes have occurred). - * - * - * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK - * @param[in,out] *SubTotalPtr - pointer to Sub-Total - */ - -VOID -STATIC -MemNQuarterMemClk2NClkNb ( - IN OUT MEM_NB_BLOCK *NBPtr, - IN OUT UINT16 *SubTotalPtr - ) -{ - UINT32 NBFreq; - UINT32 MemFreq; - - // Multiply SubTotal by NB COF - NBFreq = (MemNGetBitFieldNb (NBPtr, BFNbFid) + 4) * 200; - // Divide SubTotal by 4 times current MemClk frequency - MemFreq = NBPtr->DCTPtr->Timings.Speed * 4; - *SubTotalPtr = (UINT16) (((NBFreq * (*SubTotalPtr)) + MemFreq - 1) / MemFreq); // round up -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * - * This function gets the total of sync components for Max Read Latency calculation - * - * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK - * - * @return Total in 1/2 MEMCLKs - */ - -UINT16 -MemNTotalSyncComponentsNb ( - IN OUT MEM_NB_BLOCK *NBPtr - ) -{ - UINT16 SubTotal; - - // Multiply the CAS Latency by two to get a number of 1/2 MEMCLKs UINTs. - SubTotal = (UINT16) MemNGetBitFieldNb (NBPtr, BFTcl) + 1; - if ((MemNGetBitFieldNb (NBPtr, BFDdr3Mode)) != 0) { - SubTotal += 3; - } - SubTotal *= 2; - - // If registered DIMMs are being used then add 1 MEMCLK to the sub-total. - if ((MemNGetBitFieldNb (NBPtr, BFUnBuffDimm)) == 0) { - SubTotal += 2; - } - - // If (F2x[1, 0]9C_x04[AddrCmdSetup] and F2x[1, 0]9C_x04[CsOdtSetup] and F2x[1, 0]9C_x04[Cke-Setup] = 0) then K = K + 1 - // If (F2x[1, 0]9C_x04[AddrCmdSetup] or F2x[1, 0]9C_x04[CsOdtSetup] or F2x[1, 0]9C_x04[CkeSetup] = 1) then K = K + 2 - if ((MemNGetBitFieldNb (NBPtr, BFAddrTmgControl) & 0x0202020) == 0) { - SubTotal += 1; - } else { - SubTotal += 2; - } - - // If the F2x[1, 0]78[RdPtrInit] field is 4, 5, 6 or 7 MEMCLKs, - // then add 4, 3, 2, or 1 MEMCLKs, respectively to the sub-total. - // - SubTotal = SubTotal + (8 - (UINT16) MemNGetBitFieldNb (NBPtr, BFRdPtrInit)); - - return SubTotal; -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * - * This function swaps bits for OnDimmMirror support - * - * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK - * - */ - -VOID -MemNSwapBitsNb ( - IN OUT MEM_NB_BLOCK *NBPtr - ) -{ - UINT8 ChipSel; - UINT32 MRSReg; - - ChipSel = (UINT8) MemNGetBitFieldNb (NBPtr, BFMrsChipSel); - if ((ChipSel & 1) != 0) { - MRSReg = MemNGetBitFieldNb (NBPtr, BFDramInitRegReg); - if ((NBPtr->DCTPtr->Timings.DimmMirrorPresent & (1 << (ChipSel >> 1))) != 0) { - MRSReg = (MRSReg & 0xFFFCFE07) | ((MRSReg&0x100A8) << 1) | ((MRSReg&0x20150) >> 1); - MemNSetBitFieldNb (NBPtr, BFDramInitRegReg, MRSReg); - } - } -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * - * This function swaps bits for OnDimmMirror support for Unb - * - * Dimm Mirroring Requires that, during MRS command cycles, the following - * bits are swapped by software - * - * A3 -> A4 A7 -> A8 - * A4 -> A3 BA0 -> BA1 - * A5 -> A6 BA1 -> BA0 - * A6 -> A5 - * - * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK - * - */ - -VOID -MemNSwapBitsUnb ( - IN OUT MEM_NB_BLOCK *NBPtr - ) -{ - UINT8 ChipSel; - UINT32 MRSBank; - UINT32 MRSAddr; - - ChipSel = (UINT8) MemNGetBitFieldNb (NBPtr, BFMrsChipSel); - if ((ChipSel & 1) != 0) { - if ((NBPtr->DCTPtr->Timings.DimmMirrorPresent & (1 << (ChipSel >> 1))) != 0) { - MRSBank = MemNGetBitFieldNb (NBPtr, BFMrsBank); - MRSAddr = MemNGetBitFieldNb (NBPtr, BFMrsAddress); - - IDS_HDT_CONSOLE (MEM_FLOW, "\t\t\tCS%d MR%d %05x swapped to ->", - (ChipSel & 0x7), - (MRSBank & 0x7), - (MRSAddr & 0x3FFFF)); - // - // Swap Mrs Bank bits 0 with 1 - MRSBank = (MRSBank & 0x0100) | ((MRSBank & 0x01) << 1) | ((MRSBank & 0x02) >> 1); - // - // Swap Mrs Address bits 3 with 4, 5 with 6, and 7 with 8 - MRSAddr = (MRSAddr & 0x03FE07) | ((MRSAddr&0x000A8) << 1) | ((MRSAddr&0x00150) >> 1); - MemNSetBitFieldNb (NBPtr, BFMrsBank, MRSBank); - MemNSetBitFieldNb (NBPtr, BFMrsAddress, MRSAddr); - } - } -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * Programs Address/command timings, driver strengths, and tri-state fields. - * - * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK - * - */ -VOID -MemNProgramPlatformSpecNb ( - IN OUT MEM_NB_BLOCK *NBPtr - ) -{ - CONST UINT8 PinType[3] = {PSO_CKE_TRI, PSO_ODT_TRI, PSO_CS_TRI}; - CONST UINT8 TabSize[3] = { 2, 4, 8}; - CONST BIT_FIELD_NAME BitField[3] = { BFCKETri, BFODTTri, BFChipSelTri}; - UINT8 *TabPtr; - UINT8 i; - UINT8 k; - UINT8 Value; - //=================================================================== - // Tristate unused CKE, ODT and chip select to save power - //=================================================================== - // - TabPtr = NULL; - for (k = 0; k < sizeof (PinType); k++) { - if (NBPtr->IsSupported[CheckFindPSOverideWithSocket]) { - TabPtr = FindPSOverrideEntry (NBPtr->RefPtr->PlatformMemoryConfiguration, PinType[k], NBPtr->MCTPtr->SocketId, MemNGetSocketRelativeChannelNb (NBPtr, NBPtr->Dct, 0)); - } - if (NBPtr->IsSupported[CheckFindPSDct]) { - TabPtr = FindPSOverrideEntry (NBPtr->RefPtr->PlatformMemoryConfiguration, PinType[k], NBPtr->MCTPtr->SocketId, NBPtr->Dct); - } - if (TabPtr == NULL) { - switch (k) { - case 0: - TabPtr = NBPtr->ChannelPtr->CKETriMap; - break; - case 1: - TabPtr = NBPtr->ChannelPtr->ODTTriMap; - break; - case 2: - TabPtr = NBPtr->ChannelPtr->ChipSelTriMap; - break; - default: - IDS_ERROR_TRAP; - } - } - ASSERT (TabPtr != NULL); - - Value = 0; - for (i = 0; i < TabSize[k]; i++) { - if ((NBPtr->DCTPtr->Timings.CsPresent & TabPtr[i]) == 0) { - Value |= (UINT8) (1 << i); - } - } - - if (k == PSO_CS_TRI) { - NBPtr->FamilySpecificHook[BeforeSetCsTri] (NBPtr, &Value); - } - - ASSERT (k < GET_SIZE_OF (BitField)); - MemNSetBitFieldNb (NBPtr, BitField[k], Value); - } - NBPtr->MemNBeforePlatformSpecNb (NBPtr); - - //=================================================================== - // Program Address/Command timings and driver strength - //=================================================================== - // - MemProcessConditionalOverrides (NBPtr->RefPtr->PlatformMemoryConfiguration, NBPtr, PSO_ACTION_ADDRTMG, ALL_DIMMS); - MemProcessConditionalOverrides (NBPtr->RefPtr->PlatformMemoryConfiguration, NBPtr, PSO_ACTION_ODCCONTROL, ALL_DIMMS); - - MemNSetBitFieldNb (NBPtr, BFSlowAccessMode, (NBPtr->ChannelPtr->SlowMode) ? 1 : 0); - MemNSetBitFieldNb (NBPtr, BFODCControl, NBPtr->ChannelPtr->DctOdcCtl); - MemNSetBitFieldNb (NBPtr, BFAddrTmgControl, NBPtr->ChannelPtr->DctAddrTmg); - NBPtr->FamilySpecificHook[SetDqsODT] (NBPtr, NBPtr); - - if (NBPtr->IsSupported[CheckODTControls]) { - MemNSetBitFieldNb (NBPtr, BFPhyRODTCSLow, NBPtr->ChannelPtr->PhyRODTCSLow); - MemNSetBitFieldNb (NBPtr, BFPhyRODTCSHigh, NBPtr->ChannelPtr->PhyRODTCSHigh); - MemNSetBitFieldNb (NBPtr, BFPhyWODTCSLow, NBPtr->ChannelPtr->PhyWODTCSLow); - MemNSetBitFieldNb (NBPtr, BFPhyWODTCSHigh, NBPtr->ChannelPtr->PhyWODTCSHigh); - } -} -/* -----------------------------------------------------------------------------*/ -/** - * - * - * This function gets the Trdrd value - * - * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK - * - * @return Trdrd value - */ - -UINT8 -MemNGetTrdrdNb ( - IN OUT MEM_NB_BLOCK *NBPtr - ) -{ - DCT_STRUCT *DCTPtr; - INT8 Cgdd; - - DCTPtr = NBPtr->DCTPtr; - - // BIOS calculates Trdrd (in MEMCLKs) = CGDD / 2 + 3 clocks and programs F2x[1, 0]8C[Trdrd] with the - // converted field value. BIOS rounds fractional values down. - // The Critical Gross Delay Difference (CGDD) for Trdrd on any given byte lane is the largest F2x[1, - // 0]9C_x[3:0][2B:10][DqsRcvEnGrossDelay] delay of any DIMM minus the F2x[1, - // 0]9C_x[3:0][2B:10][DqsRcvEnGrossDelay] delay of any other DIMM. - - Cgdd = MemNGetOptimalCGDDNb (NBPtr, AccessRcvEnDly, AccessRcvEnDly); - DCTPtr->Timings.Trdrd = (Cgdd / 2) + 3; - - // Transfer clk to reg definition, 2T is 00b, etc. - DCTPtr->Timings.Trdrd -= 2; - if (DCTPtr->Timings.Trdrd > 8) { - DCTPtr->Timings.Trdrd = 8; - } - - return DCTPtr->Timings.Trdrd; -} - - -/* -----------------------------------------------------------------------------*/ -/** - * - * - * This function gets the Twrwr value - * - * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK - * - * @return Twrwr value - */ - -UINT8 -MemNGetTwrwrNb ( - IN OUT MEM_NB_BLOCK *NBPtr - ) -{ - DCT_STRUCT *DCTPtr; - INT8 Cgdd; - - DCTPtr = NBPtr->DCTPtr; - - // Twrwr (in MEMCLKs) = CGDD / 2 + 3 clocks and programs F2x[1, 0]8C[Twrwr] with the - // converted field value. BIOS rounds fractional values down. - // On any given byte lane, the largest F2x[1, 0]9C_x[3:0][A, 7, 6, 0][2:1]:F2x[1, 0]9C_x[3:0][A, 7, 6, - // 0]3[WrDatGrossDlyByte] delay of any DIMM minus the F2x[1, 0]9C_x[3:0][A, 7, 6, 0][2:1]:F2x[1, - // 0]9C_x[3:0][A, 7, 6, 0]3[WrDatGrossDlyByte] delay of any other DIMM is equal to the Critical Gross - // Delay Difference (CGDD) for Twrwr. - - Cgdd = MemNGetOptimalCGDDNb (NBPtr, AccessWrDatDly, AccessWrDatDly); - DCTPtr->Timings.Twrwr = (Cgdd / 2) + 3; - NBPtr->TechPtr->AdjustTwrwr (NBPtr->TechPtr); - - return DCTPtr->Timings.Twrwr; -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * - * This function gets the Twrrd value. BIOS calculates Twrrd (in MEMCLKs) = CGDD / 2 - LD + 3 clocks and programs - * F2x[1, 0]8C[Twrrd] with the converted field value. BIOS rounds fractional - * values down. - * - * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK - * - * @return Value to be programmed to Twrrd field - * pDCT->Timings.Twrrd updated - */ - -UINT8 -MemNGetTwrrdNb ( - IN OUT MEM_NB_BLOCK *NBPtr - ) -{ - INT8 Cgdd; - INT8 Ld; - INT8 Twrrd; - DCT_STRUCT *DCTPtr; - - DCTPtr = NBPtr->DCTPtr; - - // - // For DDR3, BIOS calculates the latency difference (Ld) as equal to read CAS latency minus write CAS - // latency, in MEMCLKs (see F2x[1, 0]88[Tcl] and F2x[1, 0]84[Tcwl]) which can be a negative or positive - // value. - // For DDR2, LD is always one clock (For DDR2, Tcwl is always Tcl minus 1). - // - Ld = NBPtr->TechPtr->GetLD (NBPtr->TechPtr); - - // On any given byte lane, the largest WrDatGrossDlyByte delay of any DIMM - // minus the DqsRcvEnGrossDelay delay of any other DIMM is - // equal to the Critical Gross Delay Difference (CGDD) for Twrrd. - Cgdd = MemNGetOptimalCGDDNb (NBPtr, AccessWrDatDly, AccessRcvEnDly); - Twrrd = (Cgdd / 2) - Ld + 3; - DCTPtr->Timings.Twrrd = (UINT8) ((Twrrd >= 0) ? Twrrd : 0); - NBPtr->TechPtr->AdjustTwrrd (NBPtr->TechPtr); - - return DCTPtr->Timings.Twrrd; -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * - * This function gets the TrwtTO value - * - * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK - * - * @return pDCT->Timings.TrwtTO updated - */ - -UINT8 -MemNGetTrwtTONb ( - IN OUT MEM_NB_BLOCK *NBPtr - ) -{ - INT8 Cgdd; - INT8 Ld; - INT8 TrwtTO; - DCT_STRUCT *DCTPtr; - - DCTPtr = NBPtr->DCTPtr; - // - // For DDR3, BIOS calculates the latency difference (Ld) as equal to read CAS latency minus write CAS - // latency, in MEMCLKs (see F2x[1, 0]88[Tcl] and F2x[1, 0]84[Tcwl]) which can be a negative or positive - // value. - // For DDR2, LD is always one clock (For DDR2, Tcwl is always Tcl minus 1). - // - Ld = NBPtr->TechPtr->GetLD (NBPtr->TechPtr); - - // On any byte lane, the largest DqsRcvEnGrossDelay delay of any DIMM minus - // the WrDatGrossDlyByte delay of any other DIMM is equal to the Critical Gross - // Delay Difference (CGDD) for TrwtTO. - Cgdd = MemNGetOptimalCGDDNb (NBPtr, AccessRcvEnDly, AccessWrDatDly); - TrwtTO = (Cgdd / 2) + Ld + 3; - TrwtTO -= 2; - DCTPtr->Timings.TrwtTO = (UINT8) ((TrwtTO > 1) ? TrwtTO : 1); - - return DCTPtr->Timings.TrwtTO; -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * - * This function gets the TrwtWB value - * - * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK - * - * @return TrwtWB value - */ -UINT8 -MemNGetTrwtWBNb ( - IN OUT MEM_NB_BLOCK *NBPtr - ) -{ - DCT_STRUCT *DCTPtr; - - DCTPtr = NBPtr->DCTPtr; - - // TrwtWB ensures read-to-write data-bus turnaround. - // This value should be one more than the programmed TrwtTO. - return DCTPtr->Timings.TrwtWB = DCTPtr->Timings.TrwtTO; -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * - * This function converts MemClk frequency in MHz to MemClkFreq value - * - * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK - * @param[in] Speed - MemClk frequency in MHz - * - * @return MemClkFreq value - */ -UINT8 -MemNGetMemClkFreqIdNb ( - IN OUT MEM_NB_BLOCK *NBPtr, - IN UINT16 Speed - ) -{ - return (UINT8) ((Speed < DDR800_FREQUENCY) ? ((Speed / 66) - 3) : (Speed / 133)); -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * - * This function enables swapping interleaved region feature. - * - * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK - * @param[in] Base - Swap interleaved region base [47:27] - * @param[in] Limit - Swap interleaved region limit [47:27] - * - */ -VOID -MemNEnableSwapIntlvRgnNb ( - IN OUT MEM_NB_BLOCK *NBPtr, - IN UINT32 Base, - IN UINT32 Limit - ) -{ - UINT32 Size; - UINT32 SizeOfAlign; - - // Swapped interleaving region must be below 16G - if (Limit < (1 << (34 - 27))) { - // Adjust Base and Size to meet : - // 1. The size of the swapped region must be less than or equal to the alignment of F2x10C[IntLvRegionBase]. - // 2. Entire UMA region is swapped with interleaving region. - Size = Limit - Base; - SizeOfAlign = (UINT32) 1 << LibAmdBitScanForward (Base); - while (SizeOfAlign <= Size) { - // In case of SizeOfAlign <= Size, UmaBase -= 128MB, SizeOfIntlvrgn += 128MB. - Base -= 1; - Size += 1; - SizeOfAlign = (UINT32) 1 << LibAmdBitScanForward (Base); - } - MemNSetBitFieldNb (NBPtr, BFIntLvRgnBaseAddr, Base); - MemNSetBitFieldNb (NBPtr, BFIntLvRgnLmtAddr, (Limit - 1)); - MemNSetBitFieldNb (NBPtr, BFIntLvRgnSize, Size); - MemNSetBitFieldNb (NBPtr, BFIntLvRgnSwapEn, 1); - } -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * - * This function converts MemClk frequency in MHz to MemClkFreq value - * - * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK - * @param[in] Speed - MemClk frequency in MHz - * - * @return MemClkFreq value - */ -UINT8 -MemNGetMemClkFreqIdClientNb ( - IN OUT MEM_NB_BLOCK *NBPtr, - IN UINT16 Speed - ) -{ - return (UINT8) ((Speed > DDR400_FREQUENCY) ? ((Speed / 33) - 6) : ((Speed == DDR400_FREQUENCY) ? 2 : (Speed / 55))); -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * - * This function converts MemClk frequency in MHz to MemClkFreq value - * - * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK - * @param[in] Speed - MemClk frequency in MHz - * - * @return MemClkFreq value - */ -UINT8 -MemNGetMemClkFreqIdUnb ( - IN OUT MEM_NB_BLOCK *NBPtr, - IN UINT16 Speed - ) -{ - return (UINT8) ((Speed > DDR400_FREQUENCY) ? ((Speed / 33) - 6) : ((Speed == DDR400_FREQUENCY) ? 2 : (Speed / 55))); -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * - * This function converts MemClkFreq Id value to MemClk frequency in MHz - * - * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK - * @param[in] FreqId - FreqId from Register - * - * @return MemClk frequency in MHz - */ -UINT16 -MemNGetMemClkFreqUnb ( - IN OUT MEM_NB_BLOCK *NBPtr, - IN UINT8 FreqId - ) -{ - UINT16 MemClkFreq; - if (FreqId > 2) { - MemClkFreq = (FreqId == 14) ? 667 : (300 + ((FreqId - 3) * 33) + (FreqId - 3) / 3); - } else if (FreqId == 2) { - MemClkFreq = 200; - } else { - MemClkFreq = 50 + (50 * FreqId); - } - return MemClkFreq; -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * This function change MemClk frequency to the value that is specified by DCTPtr->Timings.Speed - * for client NB. - * - * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK - * - */ - -VOID -MemNChangeFrequencyClientNb ( - IN OUT MEM_NB_BLOCK *NBPtr - ) -{ - MEM_TECH_BLOCK *TechPtr; - UINT8 Dct; - UINT8 ChipSel; - UINT16 FinalPllLockTime; - UINT32 Dummy; - BOOLEAN FrequencyChangeSuccess; - UINT64 OrgMMIOCfgBase; - UINT64 NewMMIOCfgBase; - - TechPtr = NBPtr->TechPtr; - - // Disable MMIO to prevent speculative DRAM reads during self refresh - LibAmdMsrRead (MSR_MMIO_Cfg_Base, &OrgMMIOCfgBase, &(NBPtr->MemPtr->StdHeader)); - NewMMIOCfgBase = OrgMMIOCfgBase & (~(BIT0)); - LibAmdMsrWrite (MSR_MMIO_Cfg_Base, &NewMMIOCfgBase, &(NBPtr->MemPtr->StdHeader)); - - MemNBrdcstSetNb (NBPtr, BFDisDllShutdownSR, 1); - - //Program F2x[1,0]90[EnterSelfRefresh]=1. - //Wait until the hardware resets F2x[1,0]90[EnterSelfRefresh]=0. - MemNBrdcstSetNb (NBPtr, BFEnterSelfRef, 1); - MemNPollBitFieldNb (NBPtr, BFEnterSelfRef, 0, PCI_ACCESS_TIMEOUT, TRUE); - - if (NBPtr->ChangeNbFrequency (NBPtr)) { - // Reprogram Twr, Tcwl, and Tcl based on the new MEMCLK frequency. - for (Dct = 0; Dct < NBPtr->DctCount; Dct++) { - MemNSwitchDCTNb (NBPtr, Dct); - if (NBPtr->DCTPtr->Timings.DctMemSize != 0) { - TechPtr->AutoCycTiming (TechPtr); - if (!MemNPlatformSpecUnb (NBPtr)) { - IDS_ERROR_TRAP; - } - } - } - - // 1. Program PllLockTime to Family-specific value - MemNBrdcstSetNb (NBPtr, BFPllLockTime, NBPtr->FreqChangeParam->PllLockTimeDefault); - - // 2. Program D18F2x[1,0]94[MemClkFreqVal] = 0. - MemNBrdcstSetNb (NBPtr, BFMemClkFreqVal, 0); - - // 3. Program D18F2x[1,0]94[MemClkFreq] to the desired DRAM frequency. - MemNBrdcstSetNb (NBPtr, BFMemClkFreq, NBPtr->GetMemClkFreqId (NBPtr, NBPtr->DCTPtr->Timings.Speed)); - - // 4. Program D18F2x[1,0]F4_x30[DbeGskFifoNumerator] and D18F2x[1,0]F4_x31[DbeGskFifoDenominator]. - // 5. Program D18F2x[1,0]F4_x32[DataTxFifoSchedDlyNegSlot1, DataTxFifoSchedDlySlot1, - // DataTxFifoSchedDlyNegSlot0, DataTxFifoSchedDlySlot0]. See 2.10.3.2.2.1 [DCT Transmit Fifo Schedule - // Delay Programming]. - // 6. D18F2x[1,0]78[RdPtrInit] = IF (D18F2x[1,0]94[MemClkFreq] >= 667 MHz) THEN 7 ELSE 8 ENDIF (Llano) - // THEN 2 ELSE 3 ENDIF (Ontario) - NBPtr->ProgramNbPsDependentRegs (NBPtr); - - NBPtr->FamilySpecificHook[BeforeMemClkFreqVal] (NBPtr, NBPtr); - IDS_OPTION_HOOK (IDS_BEFORE_MEM_FREQ_CHG, NBPtr, &(NBPtr->MemPtr->StdHeader)); - // 7. Program D18F2x[1,0]94[MemClkFreqVal] = 1. - MemNBrdcstSetNb (NBPtr, BFMemClkFreqVal, 1); - MemNPollBitFieldNb (NBPtr, BFFreqChgInProg, 0, PCI_ACCESS_TIMEOUT, TRUE); - FinalPllLockTime = 0xF; - NBPtr->FamilySpecificHook[AfterMemClkFreqVal] (NBPtr, &FinalPllLockTime); - - // 8. IF (D18F2x[1,0]9C_x0D0F_E00A[CsrPhySrPllPdMode]==0) THEN program - // D18F2x[1,0]9C_x0D0F_E006[PllLockTime] = 0Fh. - if (!NBPtr->IsSupported[CsrPhyPllPdEn]) { - MemNBrdcstSetNb (NBPtr, BFPllLockTime, FinalPllLockTime); - } - - FrequencyChangeSuccess = TRUE; - } else { - // If NB frequency cannot be updated, use the current speed as the target speed - for (Dct = 0; Dct < NBPtr->DctCount; Dct++) { - MemNSwitchDCTNb (NBPtr, Dct); - NBPtr->DCTPtr->Timings.Speed = NBPtr->TechPtr->PrevSpeed; - NBPtr->DCTPtr->Timings.TargetSpeed = NBPtr->TechPtr->PrevSpeed; - } - FrequencyChangeSuccess = FALSE; - } - - //Program F2x[1,0]90[ExitSelfRef]=1 for both DCTs. - //Wait until the hardware resets F2x[1, 0]90[ExitSelfRef]=0. - MemNBrdcstSetNb (NBPtr, BFExitSelfRef, 1); - MemNPollBitFieldNb (NBPtr, BFExitSelfRef, 0, PCI_ACCESS_TIMEOUT, TRUE); - MemNBrdcstSetNb (NBPtr, BFDisDllShutdownSR, 0); - - if (FrequencyChangeSuccess) { - NBPtr->FamilySpecificHook[AfterMemClkFreqChg] (NBPtr, NULL); - - // Perform Phy Fence training and Phy comp init after frequency change - for (Dct = 0; Dct < NBPtr->DctCount; Dct++) { - MemNSwitchDCTNb (NBPtr, Dct); - if (NBPtr->DCTPtr->Timings.DctMemSize != 0) { - IDS_HDT_CONSOLE (MEM_STATUS, "\tDct %d\n", Dct); - - // Phy fence programming - AGESA_TESTPOINT (TpProcMemPhyFenceTraining, &(NBPtr->MemPtr->StdHeader)); - NBPtr->PhyFenceTraining (NBPtr); - - // Phy compensation initialization - AGESA_TESTPOINT (TPProcMemPhyCompensation, &(NBPtr->MemPtr->StdHeader)); - NBPtr->MemNInitPhyComp (NBPtr); - MemProcessConditionalOverrides (NBPtr->RefPtr->PlatformMemoryConfiguration, NBPtr, PSO_ACTION_SLEWRATE, ALL_DIMMS); - } - } - - //====================================================================== - // Calculate and program DRAM Timings at new frequency - //====================================================================== - // - for (Dct = 0; Dct < NBPtr->DctCount; Dct++) { - IDS_HDT_CONSOLE (MEM_STATUS, "\tDct %d\n", Dct); - MemNSwitchDCTNb (NBPtr, Dct); - if (NBPtr->DCTPtr->Timings.DctMemSize != 0) { - for (ChipSel = 0; ChipSel < MAX_CS_PER_CHANNEL; ChipSel++) { - if (MemNGetMCTSysAddrNb (NBPtr, ChipSel, &Dummy)) { - // if chip select present - if (!(TechPtr->TechnologySpecificHook[LrdimmSendAllMRCmds] (TechPtr, &ChipSel))) { - TechPtr->SendAllMRCmds (TechPtr, ChipSel); - } - } - } - // Wait 512 clocks for DLL-relock - MemNWaitXMemClksNb (NBPtr, 512); - } - } - } - - // Restore MMIO setting - LibAmdMsrWrite (MSR_MMIO_Cfg_Base, &OrgMMIOCfgBase, &(NBPtr->MemPtr->StdHeader)); - - MemFInitTableDrive (NBPtr, MTAfterFreqChg); -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * This function change MemClk frequency to the value that is specified by DCTPtr->Timings.Speed - * for UNB. - * - * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK - * - */ - -VOID -MemNChangeFrequencyUnb ( - IN OUT MEM_NB_BLOCK *NBPtr - ) -{ - MEM_TECH_BLOCK *TechPtr; - UINT8 Dct; - UINT8 ChipSel; - UINT16 FinalPllLockTime; - UINT32 Dummy; - BOOLEAN FrequencyChangeSuccess; - UINT64 OrgMMIOCfgBase; - UINT64 NewMMIOCfgBase; - - TechPtr = NBPtr->TechPtr; - - // Disable MMIO to prevent speculative DRAM reads during self refresh - LibAmdMsrRead (MSR_MMIO_Cfg_Base, &OrgMMIOCfgBase, &(NBPtr->MemPtr->StdHeader)); - NewMMIOCfgBase = OrgMMIOCfgBase & (~(BIT0)); - LibAmdMsrWrite (MSR_MMIO_Cfg_Base, &NewMMIOCfgBase, &(NBPtr->MemPtr->StdHeader)); - - MemNBrdcstSetNb (NBPtr, BFDisDllShutdownSR, 1); - - //Program F2x[1,0]90[EnterSelfRefresh]=1. - //Wait until the hardware resets F2x[1,0]90[EnterSelfRefresh]=0. - MemNBrdcstSetNb (NBPtr, BFEnterSelfRef, 1); - MemNPollBitFieldNb (NBPtr, BFEnterSelfRef, 0, PCI_ACCESS_TIMEOUT, TRUE); - - if (NBPtr->ChangeNbFrequency (NBPtr)) { - // Reprogram Twr, Tcwl, and Tcl based on the new MEMCLK frequency. - for (Dct = 0; Dct < NBPtr->DctCount; Dct++) { - MemNSwitchDCTNb (NBPtr, Dct); - if (NBPtr->DCTPtr->Timings.DctMemSize != 0) { - TechPtr->AutoCycTiming (TechPtr); - if (!MemNPlatformSpecUnb (NBPtr)) { - IDS_ERROR_TRAP; - } - } - } - - // 1. Program PllLockTime to Family-specific value - MemNBrdcstSetNb (NBPtr, BFPllLockTime, NBPtr->FreqChangeParam->PllLockTimeDefault); - - // 2. Program D18F2x[1,0]94[MemClkFreqVal] = 0. - MemNBrdcstSetNb (NBPtr, BFMemClkFreqVal, 0); - - // 3. Program D18F2x[1,0]94[MemClkFreq] to the desired DRAM frequency. - MemNBrdcstSetNb (NBPtr, BFMemClkFreq, NBPtr->GetMemClkFreqId (NBPtr, NBPtr->DCTPtr->Timings.Speed)); - - // 4. Program D18F2x[1,0]F4_x30[DbeGskFifoNumerator] and D18F2x[1,0]F4_x31[DbeGskFifoDenominator]. - // 5. Program D18F2x[1,0]F4_x32[DataTxFifoSchedDlyNegSlot1, DataTxFifoSchedDlySlot1, - // DataTxFifoSchedDlyNegSlot0, DataTxFifoSchedDlySlot0]. See 2.10.3.2.2.1 [DCT Transmit Fifo Schedule - // Delay Programming]. - // 6. D18F2x[1,0]78[RdPtrInit] = IF (D18F2x[1,0]94[MemClkFreq] >= 667 MHz) THEN 7 ELSE 8 ENDIF (Llano) - // THEN 2 ELSE 3 ENDIF (Ontario) - NBPtr->ProgramNbPsDependentRegs (NBPtr); - - IDS_OPTION_HOOK (IDS_BEFORE_MEM_FREQ_CHG, NBPtr, &(NBPtr->MemPtr->StdHeader)); - // 7. Program D18F2x[1,0]94[MemClkFreqVal] = 1. - MemNBrdcstSetNb (NBPtr, BFMemClkFreqVal, 1); - MemNPollBitFieldNb (NBPtr, BFFreqChgInProg, 0, PCI_ACCESS_TIMEOUT, TRUE); - FinalPllLockTime = 0xF; - NBPtr->FamilySpecificHook[AfterMemClkFreqVal] (NBPtr, &FinalPllLockTime); - - // 8. IF (D18F2x[1,0]9C_x0D0F_E00A[CsrPhySrPllPdMode]==0) THEN program - // D18F2x[1,0]9C_x0D0F_E006[PllLockTime] = 0Fh. - if (!NBPtr->IsSupported[CsrPhyPllPdEn]) { - MemNBrdcstSetNb (NBPtr, BFPllLockTime, FinalPllLockTime); - } - - FrequencyChangeSuccess = TRUE; - } else { - // If NB frequency cannot be updated, use the current speed as the target speed - for (Dct = 0; Dct < NBPtr->DctCount; Dct++) { - MemNSwitchDCTNb (NBPtr, Dct); - NBPtr->DCTPtr->Timings.Speed = NBPtr->TechPtr->PrevSpeed; - NBPtr->DCTPtr->Timings.TargetSpeed = NBPtr->TechPtr->PrevSpeed; - } - FrequencyChangeSuccess = FALSE; - } - - if (FrequencyChangeSuccess) { - // Perform Phy Fence training and Phy comp init after frequency change - for (Dct = 0; Dct < NBPtr->DctCount; Dct++) { - MemNSwitchDCTNb (NBPtr, Dct); - if (NBPtr->DCTPtr->Timings.DctMemSize != 0) { - IDS_HDT_CONSOLE (MEM_STATUS, "\tDct %d\n", Dct); - - // Phy fence programming - AGESA_TESTPOINT (TpProcMemPhyFenceTraining, &(NBPtr->MemPtr->StdHeader)); - NBPtr->PhyFenceTraining (NBPtr); - - // Phy compensation initialization - AGESA_TESTPOINT (TPProcMemPhyCompensation, &(NBPtr->MemPtr->StdHeader)); - NBPtr->MemNInitPhyComp (NBPtr); - MemProcessConditionalOverrides (NBPtr->RefPtr->PlatformMemoryConfiguration, NBPtr, PSO_ACTION_SLEWRATE, ALL_DIMMS); - } - } - } - - //Program F2x[1,0]90[ExitSelfRef]=1 for both DCTs. - //Wait until the hardware resets F2x[1, 0]90[ExitSelfRef]=0. - MemNBrdcstSetNb (NBPtr, BFExitSelfRef, 1); - MemNPollBitFieldNb (NBPtr, BFExitSelfRef, 0, PCI_ACCESS_TIMEOUT, TRUE); - MemNBrdcstSetNb (NBPtr, BFDisDllShutdownSR, 0); - - if (FrequencyChangeSuccess) { - NBPtr->FamilySpecificHook[AfterMemClkFreqChg] (NBPtr, NULL); - - //====================================================================== - // Calculate and program DRAM Timings at new frequency - //====================================================================== - // - for (Dct = 0; Dct < NBPtr->DctCount; Dct++) { - IDS_HDT_CONSOLE (MEM_STATUS, "\tDct %d\n", Dct); - MemNSwitchDCTNb (NBPtr, Dct); - if (NBPtr->DCTPtr->Timings.DctMemSize != 0) { - for (ChipSel = 0; ChipSel < MAX_CS_PER_CHANNEL; ChipSel++) { - if (MemNGetMCTSysAddrNb (NBPtr, ChipSel, &Dummy)) { - // if chip select present - if (!(TechPtr->TechnologySpecificHook[LrdimmSendAllMRCmds] (TechPtr, &ChipSel))) { - TechPtr->SendAllMRCmds (TechPtr, ChipSel); - } - } - } - // Wait 512 clocks for DLL-relock - MemNWaitXMemClksNb (NBPtr, 512); - } - } - } - - // Restore MMIO setting - LibAmdMsrWrite (MSR_MMIO_Cfg_Base, &OrgMMIOCfgBase, &(NBPtr->MemPtr->StdHeader)); - - MemFInitTableDrive (NBPtr, MTAfterFreqChg); -} - - -/* -----------------------------------------------------------------------------*/ -/** - * - * This function calculates and programs NB P-state dependent registers - * - * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK - * - */ - -VOID -MemNProgramNbPstateDependentRegistersUnb ( - IN OUT MEM_NB_BLOCK *NBPtr - ) -{ - UINT8 RdPtrInit; - - RdPtrInit = (NBPtr->DCTPtr->Timings.Speed <= DDR1600_FREQUENCY) ? 6 : 4; - MemNBrdcstSetNb (NBPtr, BFRdPtrInit, RdPtrInit); - IDS_HDT_CONSOLE (MEM_FLOW, "\t\tRdPtr: %d\n", RdPtrInit); - - MemFInitTableDrive (NBPtr, MTAfterNbPstateChange); - - IDS_HDT_CONSOLE_DEBUG_CODE ( - RdPtrInit = (UINT8) MemNGetBitFieldNb (NBPtr, BFRdPtrInit); - ); - - switch (RdPtrInit) { - case 4: - if (MemNGetBitFieldNb (NBPtr, BFNbPsSel) == 0) { - MemNBrdcstSetNb (NBPtr, BFDataTxFifoWrDly, 2); - } else { - MemNBrdcstSetNb (NBPtr, BFDataTxFifoWrDly, 1); - } - break; - case 5: - MemNBrdcstSetNb (NBPtr, BFDataTxFifoWrDly, 1); - break; - case 6: - MemNBrdcstSetNb (NBPtr, BFDataTxFifoWrDly, 0); - break; - default: - ASSERT (FALSE); - } - - NBPtr->FamilySpecificHook[OverrideDataTxFifoWrDly] (NBPtr, NBPtr); - IDS_OPTION_HOOK (IDS_NBPS_REG_OVERRIDE, NBPtr, &NBPtr->MemPtr->StdHeader); -} - -/* -----------------------------------------------------------------------------*/ -CONST UINT8 PllDivTab[] = {0, 0, 0, 2, 3, 3, 2, 3}; -CONST UINT8 PllMultTab[] = {0, 0, 0, 16, 32, 40, 32, 56}; - -/** - * - * This function calculates and programs NB P-state dependent registers - * - * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK - * - */ - -VOID -MemNProgramNbPstateDependentRegistersClientNb ( - IN OUT MEM_NB_BLOCK *NBPtr - ) -{ - UINT8 i; - UINT8 Dct; - UINT8 NclkFid; - UINT16 MemClkDid; - UINT8 PllMult; - UINT8 NclkDiv; - UINT8 RdPtrInitMin; - UINT8 RdPtrInit; - UINT32 NclkPeriod; - UINT32 MemClkPeriod; - INT32 PartialSum2x; - INT32 PartialSumSlotI2x; - INT32 RdPtrInitRmdr2x; - INT32 TDataProp; - UINT8 NbPstate; - UINT8 SlowMode; - - NclkFid = (UINT8) (MemNGetBitFieldNb (NBPtr, BFMainPllOpFreqId) + 0x10); // NclkFid is in 100MHz - - MemClkDid = PllDivTab[NBPtr->DCTPtr->Timings.Speed / 133]; - NBPtr->FamilySpecificHook[OverridePllDiv] (NBPtr, &MemClkDid); - PllMult = PllMultTab[NBPtr->DCTPtr->Timings.Speed / 133]; - NBPtr->FamilySpecificHook[OverridePllMult] (NBPtr, &PllMult); - - if (NBPtr->NbFreqChgState == 2) { - MemNSetBitFieldNb (NBPtr, BFNbPsCsrAccSel, 1); - MemNSetBitFieldNb (NBPtr, BFNbPsDbgEn, 1); - NclkDiv = (UINT8) MemNGetBitFieldNb (NBPtr, BFNbPs1NclkDiv); - // Divisors less than 8 are undefined. Maybe the CPU does not support NB P-states. - if (NclkDiv < 8) { - // Set a dummy divisor to prevent divide by zero exception below. - NclkDiv = 8; - } - NbPstate = 1; - } else { - NclkDiv = (UINT8) MemNGetBitFieldNb (NBPtr, BFNbPs0NclkDiv); - NbPstate = 0; - } - NclkPeriod = (2500 * NclkDiv) / NclkFid; // (1,000,000 * 0.25 * NclkDiv) / (NclkFid * 100MHz) = ps - MemClkPeriod = 1000000 / NBPtr->DCTPtr->Timings.Speed; - NBPtr->NBClkFreq = ((UINT32) NclkFid * 400) / NclkDiv; - - IDS_HDT_CONSOLE (MEM_FLOW, "\n\tNB P%d Freq: %dMHz\n", NbPstate, NBPtr->NBClkFreq); - IDS_HDT_CONSOLE (MEM_FLOW, "\tMemClk Freq: %dMHz\n", NBPtr->DCTPtr->Timings.Speed); - // D18F2x[1,0]78[RdPtrInit] = IF (D18F2x[1,0]94[MemClkFreq] >= 667 MHz) THEN 7 ELSE 8 ENDIF (Llano) - // THEN 2 ELSE 3 ENDIF (Ontario) - RdPtrInit = RdPtrInitMin = (NBPtr->DCTPtr->Timings.Speed >= DDR1333_FREQUENCY) ? NBPtr->FreqChangeParam->RdPtrInit667orHigher : NBPtr->FreqChangeParam->RdPtrInitLower667; - MemNBrdcstSetNb (NBPtr, BFRdPtrInit, RdPtrInit); - IDS_HDT_CONSOLE (MEM_FLOW, "\t\tRdPtr: %d\n", RdPtrInit); - - // Program D18F2x[1,0]F4_x30[DbeGskFifoNumerator] and D18F2x[1,0]F4_x31[DbeGskFifoDenominator]. - MemNBrdcstSetNb (NBPtr, BFDbeGskFifoNumerator, NclkFid * MemClkDid * 16); - MemNBrdcstSetNb (NBPtr, BFDbeGskFifoDenominator, PllMult * NclkDiv); - IDS_HDT_CONSOLE (MEM_FLOW, "\t\tDbeGskFifoNumerator: %d\n", NclkFid * MemClkDid * 16); - IDS_HDT_CONSOLE (MEM_FLOW, "\t\tDbeGskFifoDenominator: %d\n", PllMult * NclkDiv); - - // Program D18F2x[1,0]F4_x32[DataTxFifoSchedDlyNegSlot1, DataTxFifoSchedDlySlot1, - // DataTxFifoSchedDlyNegSlot0, DataTxFifoSchedDlySlot0]. - // PartialSum = ((7 * NclkPeriod) + (1.5 * MemClkPeriod) + 520ps)*MemClkFrequency - tCWL - - // CmdSetup - PtrSeparation - 1. (Llano) - // PartialSum = ((5 * NclkPeriod) + MemClkPeriod) + 520ps)*MemClkFrequency - tCWL - - // CmdSetup - PtrSeparation - 1. (Ontario) - for (Dct = 0; Dct < NBPtr->DctCount; Dct++) { - MemNSwitchDCTNb (NBPtr, Dct); - if (NBPtr->DCTPtr->Timings.DctMemSize != 0) { - PartialSum2x = NBPtr->FreqChangeParam->NclkPeriodMul2x * NclkPeriod; - PartialSum2x += NBPtr->FreqChangeParam->MemClkPeriodMul2x * MemClkPeriod; - PartialSum2x += 520 * 2; - - // PtrSeparation = ((16 + RdPtrInitMin - D18F2x[1,0]78[RdPtrInit]) MOD 16)/2 + RdPtrInitRmdr - // If (D18F2x[1,0]94[MemClkFreq] >= 800 MHz) - // then RdPtrInitRmdr = (((4.5 * MemClkPeriod) - 990ps) MOD MemClkPeriod)/MemClkPeriod - // else RdPtrInitRmdr = (((4.5 * MemClkPeriod) - 1466ps) MOD MemClkPeriod)/MemClkPeriod - TDataProp = (NBPtr->DCTPtr->Timings.Speed >= DDR1600_FREQUENCY) ? - NBPtr->FreqChangeParam->TDataProp800orHigher : NBPtr->FreqChangeParam->TDataPropLower800; - RdPtrInitRmdr2x = ((NBPtr->FreqChangeParam->SyncTimeMul4x * MemClkPeriod) / 2) - 2 * (TDataProp + 520); - RdPtrInitRmdr2x %= MemClkPeriod; - PartialSum2x -= ((16 + RdPtrInitMin - RdPtrInit) % 16) * MemClkPeriod + RdPtrInitRmdr2x; - - // Convert PartialSum2x to PCLK - PartialSum2x = (PartialSum2x + MemClkPeriod - 1) / MemClkPeriod; // round-up here - PartialSum2x -= 2 * (MemNGetBitFieldNb (NBPtr, BFTcwl) + 5); - if ((MemNGetBitFieldNb (NBPtr, BFAddrTmgControl) & 0x0202020) == 0) { - PartialSum2x -= 1; - } else { - PartialSum2x -= 2; - } - PartialSum2x -= 2; - - // If PartialSumSlotN is positive: - // DataTxFifoSchedDlySlotN=CEIL(PartialSumSlotN). - // DataTxFifoSchedDlyNegSlotN=0. - // Else if PartialSumSlotN is negative: - // DataTxFifoSchedDlySlotN=ABS(CEIL(PartialSumSlotN*MemClkPeriod/NclkPeriod)). - // DataTxFifoSchedDlyNegSlotN=1. - for (i = 0; i < 2; i++) { - PartialSumSlotI2x = PartialSum2x; - SlowMode = (UINT8) MemNGetBitFieldNb (NBPtr, BFSlowAccessMode); - if ((i == 0) && (SlowMode == 0)) { - PartialSumSlotI2x += 2; - } - if (NBPtr->IsSupported[SchedDlySlot1Extra] && (i == 1) && (SlowMode != 0)) { - PartialSumSlotI2x -= 2; - } - if (PartialSumSlotI2x > 0) { - MemNSetBitFieldNb (NBPtr, BFDataTxFifoSchedDlyNegSlot0 + i, 0); - MemNSetBitFieldNb (NBPtr, BFDataTxFifoSchedDlySlot0 + i, (PartialSumSlotI2x + 1) / 2); - IDS_HDT_CONSOLE (MEM_FLOW, "\t\tDataTxFifoSchedDlySlot%d: %d\n", i, (PartialSumSlotI2x + 1) / 2); - } else { - MemNSetBitFieldNb (NBPtr, BFDataTxFifoSchedDlyNegSlot0 + i, 1); - PartialSumSlotI2x = ((-PartialSumSlotI2x) * MemClkPeriod) / (2 * NclkPeriod); - MemNSetBitFieldNb (NBPtr, BFDataTxFifoSchedDlySlot0 + i, PartialSumSlotI2x); - IDS_HDT_CONSOLE (MEM_FLOW, "\t\tDataTxFifoSchedDlySlot%d: -%d\n", i, PartialSumSlotI2x); - } - } - - // Set ProcOdtAdv - if ((NBPtr->DCTPtr->Timings.Speed <= DDR1333_FREQUENCY) && - ((!(NBPtr->IsSupported[EnProcOdtAdvForUDIMM])) || (NBPtr->ChannelPtr->SODimmPresent != 0))) { - MemNSetBitFieldNb (NBPtr, BFProcOdtAdv, 0); - } else { - MemNSetBitFieldNb (NBPtr, BFProcOdtAdv, 0x4000); - } - } - } - - MemFInitTableDrive (NBPtr, MTAfterNbPstateChange); - if (NBPtr->NbFreqChgState == 2) { - MemNSetBitFieldNb (NBPtr, BFNbPsDbgEn, 0); - MemNSetBitFieldNb (NBPtr, BFNbPsCsrAccSel, 0); - } -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * - * This function gets the total of sync components for Max Read Latency calculation - * - * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK - * - * @return Total in ps - */ - -UINT32 -MemNTotalSyncComponentsClientNb ( - IN OUT MEM_NB_BLOCK *NBPtr - ) -{ - UINT32 P; - UINT32 T; - UINT8 RdPtrInitMin; - UINT8 RdPtrInit; - UINT32 AddrTmgCtl; - UINT8 DbeGskMemClkAlignMode; - UINT32 MemClkPeriod; - - // P = P + ((16 + RdPtrInitMin - D18F2x[1,0]78[RdPtrInit]) MOD 16) - RdPtrInitMin = (NBPtr->DCTPtr->Timings.Speed >= DDR1333_FREQUENCY) ? NBPtr->FreqChangeParam->RdPtrInit667orHigher : NBPtr->FreqChangeParam->RdPtrInitLower667; - RdPtrInit = (UINT8) MemNGetBitFieldNb (NBPtr, BFRdPtrInit); - P = (16 + RdPtrInitMin - RdPtrInit) % 16; - - // IF (AddrCmdSetup != CkeSetup) THEN P = P + 1 - AddrTmgCtl = MemNGetBitFieldNb (NBPtr, BFAddrTmgControl); - if (((AddrTmgCtl >> 16) & 0x20) != (AddrTmgCtl & 0x20)) { - P += 1; - } - - // IF (DbeGskMemClkAlignMode==01b || (DbeGskMemClkAlignMode==00b && !(AddrCmdSetup==CsOdtSetup==CkeSetup))) - // THEN P = P + 1 - DbeGskMemClkAlignMode = (UINT8) MemNGetBitFieldNb (NBPtr, BFDbeGskMemClkAlignMode); - if ((DbeGskMemClkAlignMode == 1) || ((DbeGskMemClkAlignMode == 0) && - !((((AddrTmgCtl >> 16) & 0x20) == (AddrTmgCtl & 0x20)) && (((AddrTmgCtl >> 8) & 0x20) == (AddrTmgCtl & 0x20))))) { - P += 1; - } - - // IF (SlowAccessMode==1) THEN P = P + 2 - if (MemNGetBitFieldNb (NBPtr, BFSlowAccessMode) == 1) { - P += 2; - } - - // P = P + 2 - P += 2; - T = 0; - - // If (AddrCmdSetup==0 && CsOdtSetup==0 && CkeSetup==0) - // then P = P + 1 - // else P = P + 2 - if ((AddrTmgCtl & 0x0202020) == 0) { - P += 1; - } else { - P += 2; - } - - // P = P + (2 * (D18F2x[1,0]88[Tcl] clocks - 1)) - P += 2 * (NBPtr->DCTPtr->Timings.CasL - 1); - - // If (DisCutThroughMode==0) - // then P = P + 3 - // else P = P + 7 - if (MemNGetBitFieldNb (NBPtr, BFDisCutThroughMode) == 0) { - P += 3; - } else { - P += 7; - } - - MemClkPeriod = 1000000 / NBPtr->DCTPtr->Timings.Speed; - return (((P * MemClkPeriod + 1) / 2) + T); -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * - * This function sets up phy power saving for client NB - * - * - * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK - * - */ -VOID -MemNPhyPowerSavingClientNb ( - IN OUT MEM_NB_BLOCK *NBPtr - ) -{ - // 4. Program D18F2x[1,0]9C_x0D0F_0[F,7:0]13[DllDisEarlyU] = 1b. - // 5. Program D18F2x[1,0]9C_x0D0F_0[F,7:0]13[DllDisEarlyL] = 1b. - // 6. Program D18F2x[1,0]9C_x0D0F_0[F,7:0]13[7:4] = 1010b. - MemNSetBitFieldNb (NBPtr, BFPhy0x0D0F0F13Bit0to7, 0xA3); - // 7. Program D18F2x[1,0]9C_x0D0F_812F[7, 5, 0] = {1b, 1b, 1b} to disable unused PAR and A[17:16] pins. - MemNSetBitFieldNb (NBPtr, BFAddrCmdTri, MemNGetBitFieldNb (NBPtr, BFAddrCmdTri) | 0xA1); - // 8. Program D18F2x[1,0]9C_x0D0F_C000[LowPowerDrvStrengthEn] = 1. - if (!NBPtr->FamilySpecificHook[DisLowPwrDrvStr] (NBPtr, NULL)) { - MemNSetBitFieldNb (NBPtr, BFLowPowerDrvStrengthEn, 0x100); - } - // 9. Program D18F2x[1,0]9C_x0D0F_0[F,7:0]10[EnRxPadStandby]= IF (D18F2x[1,0]94[MemClkFreq] <= - // 800 MHz) THEN 1 ELSE 0 ENDIF. - MemNSetBitFieldNb (NBPtr, BFEnRxPadStandby, (NBPtr->DCTPtr->Timings.Speed <= DDR1600_FREQUENCY) ? 0x1000 : 0); - // 10. Program D18F2x[1,0]9C_x0000_000D as follows: - // TxMaxDurDllNoLock/RxMaxDurDllNoLock = 7h. - MemNSetBitFieldNb (NBPtr, BFRxMaxDurDllNoLock, 7); - MemNSetBitFieldNb (NBPtr, BFTxMaxDurDllNoLock, 7); - // TxCPUpdPeriod/RxCPUpdPeriod = 011b. - MemNSetBitFieldNb (NBPtr, BFTxCPUpdPeriod, 3); - MemNSetBitFieldNb (NBPtr, BFRxCPUpdPeriod, 3); - // TxDLLWakeupTime/RxDLLWakeupTime = 11b. - MemNSetBitFieldNb (NBPtr, BFTxDLLWakeupTime, 3); - MemNSetBitFieldNb (NBPtr, BFRxDLLWakeupTime, 3); - - IDS_OPTION_HOOK (IDS_PHY_DLL_STANDBY_CTRL, NBPtr, &NBPtr->MemPtr->StdHeader); -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * - * This function sets up phy power saving for UNB - * - * - * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK - * - */ -VOID -MemNPhyPowerSavingUnb ( - IN OUT MEM_NB_BLOCK *NBPtr - ) -{ - UINT16 MixedX4AndX8Dimms; - - // 4. Program D18F2x9C_x0D0F_0[F,8:0]13_dct[1:0][DllDisEarlyU] = 1b. - // 5. Program D18F2x9C_x0D0F_0[F,8:0]13_dct[1:0][DllDisEarlyL] = 1b. - MemNSetBitFieldNb (NBPtr, BFPhy0x0D0F0F13, MemNGetBitFieldNb (NBPtr, BFPhy0x0D0F0F13) | 3); - // 6. D18F2x9C_x0D0F_0[F,8:0]13_dct[1:0][RxDqsUDllPowerDown] = (D18F2x90_dct[1:0][X4Dimm]!=0). - MemNSetBitFieldNb (NBPtr, BFPhy0x0D0F0F13, MemNGetBitFieldNb (NBPtr, BFX4Dimm) == 0 ? (MemNGetBitFieldNb (NBPtr, BFPhy0x0D0F0F13) | 0x80) : (MemNGetBitFieldNb (NBPtr, BFPhy0x0D0F0F13) & 0xFF7F)); - // 7. D18F2x9C_x0D0F_812F_dct[1:0][PARTri] = ~D18F2x90_dct[1:0][ParEn]. - MemNSetBitFieldNb (NBPtr, BFAddrCmdTri, MemNGetBitFieldNb (NBPtr, BFParEn) == 0 ? (MemNGetBitFieldNb (NBPtr, BFAddrCmdTri) | 1) : (MemNGetBitFieldNb (NBPtr, BFAddrCmdTri) & 0xFFFE)); - // 8. D18F2x9C_x0D0F_812F_dct[1:0][Add17Tri, Add16Tri] = {1b, 1b} - MemNSetBitFieldNb (NBPtr, BFAddrCmdTri, MemNGetBitFieldNb (NBPtr, BFAddrCmdTri) | 0xA0); - // 9. IF (D18F2x94_dct[1:0][MemClkFreq] <= 800 MHz && ~(mixed channel of x4 and x8 DIMMs)) THEN - // Program D18F2x9C_x0D0F_0[F,8:0]10_dct[1:0][EnRxPadStandby] = 1. - // ELSE - // Program D18F2x9C_x0D0F_0[F,8:0]10_dct[1:0][EnRxPadStandby] = 0. - // ENDIF. - MixedX4AndX8Dimms = NBPtr->DCTPtr->Timings.Dimmx4Present != 0 && NBPtr->DCTPtr->Timings.Dimmx8Present != 0; - MemNSetBitFieldNb (NBPtr, BFEnRxPadStandby, (NBPtr->DCTPtr->Timings.Speed <= DDR1600_FREQUENCY) && !MixedX4AndX8Dimms ? 0x1000 : 0); - // 10. IF (~(mixed channel of x4 and x8 DIMMs)) THEN - if (MixedX4AndX8Dimms == FALSE) { - // Program D18F2x9C_x0000_000D_dct[1:0] as follows: - // TxMaxDurDllNoLock = RxMaxDurDllNoLock = 7h. - MemNSetBitFieldNb (NBPtr, BFTxMaxDurDllNoLock, 7); - MemNSetBitFieldNb (NBPtr, BFRxMaxDurDllNoLock, 7); - // TxCPUpdPeriod = RxCPUpdPeriod = 011b. - MemNSetBitFieldNb (NBPtr, BFTxCPUpdPeriod, 3); - MemNSetBitFieldNb (NBPtr, BFRxCPUpdPeriod, 3); - // TxDLLWakeupTime = RxDLLWakeupTime = 11b. - MemNSetBitFieldNb (NBPtr, BFTxDLLWakeupTime, 3); - MemNSetBitFieldNb (NBPtr, BFRxDLLWakeupTime, 3); - } else { - // ELSE - // Program D18F2x9C_x0000_000D_dct[1:0][TxMaxDurDllNoLock, RxMaxDurDllNoLock, TxCPUpdPeriod, - // RxCPUpdPeriod, TxDLLWakeupTime, RxDLLWakeupTime] = {0, 0, 0, 0, 0, 0}. - MemNSetBitFieldNb (NBPtr, BFTxMaxDurDllNoLock, 0); - MemNSetBitFieldNb (NBPtr, BFRxMaxDurDllNoLock, 0); - MemNSetBitFieldNb (NBPtr, BFTxCPUpdPeriod, 0); - MemNSetBitFieldNb (NBPtr, BFRxCPUpdPeriod, 0); - MemNSetBitFieldNb (NBPtr, BFTxDLLWakeupTime, 0); - MemNSetBitFieldNb (NBPtr, BFRxDLLWakeupTime, 0); - } - // 11. Program D18F2x9C_x0D0F_0[F,8:0]30_dct[1:0][PwrDn] to disable unused ECC byte lane. - if (NBPtr->IsSupported[CheckEccDLLPwrDnConfig]) { - if (!NBPtr->MCTPtr->Status[SbEccDimms]) { - MemNSetBitFieldNb (NBPtr, BFEccDLLPwrDnConf, 0x0010); - } - } - - // 12. Program D18F2x9C_x0D0F_0[F,8:0]04_dct[1:0][TriDM] = IF (LRDIMM & (D18F2x90_dct[1:0][X4Dimm] == 0)) THEN 1 ELSE 0. - if (NBPtr->MCTPtr->Status[SbLrdimms]) { - MemNSetBitFieldNb (NBPtr, BFDataByteDMConf, (MemNGetBitFieldNb (NBPtr, BFX4Dimm) == 0) ? 0x2000 : 0); - } - - IDS_OPTION_HOOK (IDS_PHY_DLL_STANDBY_CTRL, NBPtr, &NBPtr->MemPtr->StdHeader); -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * - * This function overrides the ASR and SRT value in MRS command - * - * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK - * - */ -VOID -MemNSetASRSRTNb ( - IN OUT MEM_NB_BLOCK *NBPtr - ) -{ - UINT32 MrsAddress; - UINT8 Dimm; - UINT8 *SpdBufferPtr; - - // Look for MR2 - if (NBPtr->GetBitField (NBPtr, BFMrsBank) == 2) { - MrsAddress = NBPtr->GetBitField (NBPtr, BFMrsAddress); - // Clear A6(ASR) and A7(SRT) - MrsAddress &= (UINT32) ~0xC0; - Dimm = (UINT8) (NBPtr->GetBitField (NBPtr, BFMrsChipSel) >> 1); - // Make sure we access SPD of the second logical dimm of QR dimm correctly - if ((Dimm >= 2) && ((NBPtr->ChannelPtr->DimmQrPresent & (UINT8) (1 << Dimm)) != 0)) { - Dimm -= 2; - } - if (NBPtr->TechPtr->GetDimmSpdBuffer (NBPtr->TechPtr, &SpdBufferPtr, Dimm)) { - // Bit 2 is ASR - if (SpdBufferPtr[THERMAL_OPT] & 0x4) { - // when ASR is 1, set SRT to 0 - MrsAddress |= 0x40; - } else { - // Set SRT based on bit on of thermal byte - MrsAddress |= ((SpdBufferPtr[THERMAL_OPT] & 1) << 7); - } - NBPtr->SetBitField (NBPtr, BFMrsAddress, MrsAddress); - } - } -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * This function changes NB frequency as below: - * NBP0-DDR800 -> NBP0-DDR1066 -> ... -> NBP0-DDRTarget -> NBP1-DDRTarget -> NBP0-DDRTarget - * - * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK - * - */ - -BOOLEAN -MemNChangeNbFrequencyNb ( - IN OUT MEM_NB_BLOCK *NBPtr - ) -{ - BOOLEAN Status; - - Status = FALSE; - - // State machine to change NB frequency and NB Pstate - switch (NBPtr->NbFreqChgState) { - case 0: - // Starting up by not changing NB P state, but only updating NB frequency based on current MemClk frequency - Status = NBPtr->ChangeNbFrequencyWrap (NBPtr, 0); - ASSERT (Status); - - if (NBPtr->DCTPtr->Timings.Speed == NBPtr->DCTPtr->Timings.TargetSpeed) { - // When MemClk has been ramped up to its max, transition to next state, which changes NBPstate to P1 - NBPtr->NbFreqChgState = 1; - IDS_OPTION_HOOK (IDS_NB_PSTATE_DIDVID, NBPtr, &(NBPtr->MemPtr->StdHeader)); - } - break; - - case 1: - // Clear ForceCasToSlot0 after MaxRdLatency training is completed for NB-P0 - MemNBrdcstSetNb (NBPtr, BFForceCasToSlot0, 0); - - // Next state would be to change NBPstate back to P0 - NBPtr->NbFreqChgState = 2; - - // Update NB freq dependent registers - NBPtr->ProgramNbPsDependentRegs (NBPtr); - - // Change NB P-State to NBP1 for MaxRdLat training - if (NBPtr->ChangeNbFrequencyWrap (NBPtr, 1)) { - // Enable cut through mode for NB P1 - MemNBrdcstSetNb (NBPtr, BFDisCutThroughMode, 0); - - // Return TRUE to repeat MaxRdLat training - Status = TRUE; - - } else { - // If transition to NB-P1 fails, transition to exit state machine - NBPtr->NbFreqChgState = 3; - } - break; - - case 2: - // Clear ForceCasToSlot0 after MaxRdLatency training is completed for NB-P1 - MemNBrdcstSetNb (NBPtr, BFForceCasToSlot0, 0); - - // Change NB P-State back to NBP0 - Status = NBPtr->ChangeNbFrequencyWrap (NBPtr, 0); - ASSERT (Status); - - // Return FALSE to get out of MaxRdLat training loop - Status = FALSE; - - // Exit state machine - NBPtr->NbFreqChgState = 3; - break; - - default: - break; - } - - return Status; -} - -/*----------------------------------------------------------------------------- - * - * - * This function programs registers before phy fence training for CNB - * - * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK - * @param[in,out] OptParam - Optional parameter - * - * @return TRUE - * ---------------------------------------------------------------------------- - */ -BOOLEAN -MemNBeforePhyFenceTrainingClientNb ( - IN OUT MEM_NB_BLOCK *NBPtr, - IN OUT VOID *OptParam - ) -{ - IDS_HDT_CONSOLE (MEM_FLOW, "\tMemClkAlign=0\n"); - MemNBrdcstSetNb (NBPtr, BFDbeGskMemClkAlignMode, 0); - - IDS_HDT_CONSOLE (MEM_FLOW, "\tEnDramInit = 1 for both DCTs\n"); - MemNBrdcstSetNb (NBPtr, BFEnDramInit, 1); - - return TRUE; -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * This function changes NB frequency foras below: - * NBP0-DDR800 -> NBP0-DDR1066 -> ... -> NBP0-DDRTarget -> NBP1-DDRTarget -> NBP2-DDRTarget -> NBP3-DDRTarget -> NBP0-DDRTarget - * - * - * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK - * - */ - -BOOLEAN -MemNChangeNbFrequencyUnb ( - IN OUT MEM_NB_BLOCK *NBPtr - ) -{ - BOOLEAN Status; - - Status = FALSE; - - // State machine to change NB frequency and NB Pstate - switch (NBPtr->NbFreqChgState) { - case 0: - // Do not change NB Pstate, just to save initial NB Pstate value - Status = NBPtr->ChangeNbFrequencyWrap (NBPtr, 0); - if (NBPtr->DCTPtr->Timings.Speed == NBPtr->DCTPtr->Timings.TargetSpeed) { - // When MemClk has been ramped up to its max, transition to next state, which changes NBPstate to P1 - NBPtr->NbFreqChgState = 1; - IDS_OPTION_HOOK (IDS_NB_PSTATE_DIDVID, NBPtr, &(NBPtr->MemPtr->StdHeader)); - } - break; - - case 1: - case 2: - case 3: - // Change NB P-State to NBP1 for MaxRdLat training - if (NBPtr->ChangeNbFrequencyWrap (NBPtr, NBPtr->NbFreqChgState)) { - NBPtr->ProgramNbPsDependentRegs (NBPtr); - - // Next state is to try all NBPstates - NBPtr->NbFreqChgState++; - - // Return TRUE to repeat MaxRdLat training - Status = TRUE; - } else { - // If transition to any NBPs fails, transition to exit state machine - NBPtr->NbFreqChgState = 4; - } - break; - - case 4: - // Change NB P-State back to NBP0 - Status = NBPtr->ChangeNbFrequencyWrap (NBPtr, 0); - ASSERT (Status); - - // Return FALSE to get out of MaxRdLat training loop - Status = FALSE; - - // Exit state machine - NBPtr->NbFreqChgState = 5; - break; - - default: - break; - } - - return Status; -} - - -/* -----------------------------------------------------------------------------*/ -/** - * - * - * This function gets "Dram Term" value from data structure - * - * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK - * @param[in] ChipSel - Targeted chipsel - * - * @return Dram Term value - */ -UINT8 -MemNGetDramTermNb ( - IN OUT MEM_NB_BLOCK *NBPtr, - IN UINT8 ChipSel - ) -{ - UINT8 DramTerm; - - if ((NBPtr->ChannelPtr->DimmQrPresent & ((UINT16) (1 << (ChipSel >> 1)))) != 0) { - DramTerm = NBPtr->PsPtr->QR_DramTerm; - } else { - DramTerm = NBPtr->PsPtr->DramTerm; - } - - return DramTerm; -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * - * This function gets "Dram Term" value from data structure for Unb - * - * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK - * @param[in] ChipSel - Targeted chipsel - * - * @return Dram Term value - */ -UINT8 -MemNGetDramTermTblDrvNb ( - IN OUT MEM_NB_BLOCK *NBPtr, - IN UINT8 ChipSel - ) -{ - UINT8 RttNom; - RttNom = NBPtr->PsPtr->RttNom[ChipSel]; - IDS_OPTION_HOOK (IDS_MEM_DRAM_TERM, &RttNom, &NBPtr->MemPtr->StdHeader); - return RttNom; -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * - * This function gets "Dynamic Dram Term" value from data structure - * - * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK - * @param[in] ChipSel - Targeted chipsel - * - * @return Dynamic Dram Term value - */ -UINT8 -MemNGetDynDramTermNb ( - IN OUT MEM_NB_BLOCK *NBPtr, - IN UINT8 ChipSel - ) -{ - return (NBPtr->PsPtr->DynamicDramTerm); -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * - * This function gets "Dynamic Dram Term" value from data structure - * - * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK - * @param[in] ChipSel - Targeted chipsel - * - * @return Dynamic Dram Term value - */ -UINT8 -MemNGetDynDramTermTblDrvNb ( - IN OUT MEM_NB_BLOCK *NBPtr, - IN UINT8 ChipSel - ) -{ - UINT8 RttWr; - RttWr = NBPtr->PsPtr->RttWr[ChipSel]; - IDS_OPTION_HOOK (IDS_MEM_DYN_DRAM_TERM, &RttWr, &NBPtr->MemPtr->StdHeader); - return RttWr; -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * - * This function returns MR0[CL] value - * - * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK - * - * @return MR0[CL] value - */ -UINT32 -MemNGetMR0CLNb ( - IN OUT MEM_NB_BLOCK *NBPtr - ) -{ - UINT8 Tcl; - UINT32 Value32; - - Tcl = (UINT8) MemNGetBitFieldNb (NBPtr, BFTcl); - Value32 = (UINT32) ((Tcl < 8) ? (Tcl << 4) : (((Tcl - 8) << 4) | 4)); - - return Value32; -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * - * This function returns MR0[WR] value - * - * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK - * - * @return MR0[WR] value - */ -UINT32 -MemNGetMR0WRNb ( - IN OUT MEM_NB_BLOCK *NBPtr - ) -{ - UINT32 Value32; - - Value32 = MemNGetBitFieldNb (NBPtr, BFTwrDDR3) << 9; - - return Value32; -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * - * This function returns MR0[WR] value - * - * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK - * - * @return MR0[WR] value - */ -UINT32 -MemNGetMR0WRTblDrvNb ( - IN OUT MEM_NB_BLOCK *NBPtr - ) -{ - return (UINT32) (NBPtr->PsPtr->MR0WR << 9); -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * - * This function returns MR2[CWL] value - * - * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK - * - * @return MR0[CWL] value - */ -UINT32 -MemNGetMR2CWLNb ( - IN OUT MEM_NB_BLOCK *NBPtr - ) -{ - UINT32 Value32; - - Value32 = MemNGetBitFieldNb (NBPtr, BFTcwl) << 3; - - return Value32; -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * This function returns MR2[CWL] value for UNB - * - * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK - * - * @return MR0[CWL] value - */ -UINT32 -MemNGetMR2CWLUnb ( - IN OUT MEM_NB_BLOCK *NBPtr - ) -{ - UINT32 Value32; - - Value32 = (MemNGetBitFieldNb (NBPtr, BFTcwl) - 5) << 3; - - return Value32; -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * This function sets Txp and Txpdll - * - * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK - * - * @return none - */ -VOID -MemNSetTxpNb ( - IN OUT MEM_NB_BLOCK *NBPtr - ) -{ - CONST UINT8 Txp[] = {0xFF, 0xFF, 3, 3, 4, 4, 5, 6, 7}; - CONST UINT8 Txpdll[] = {0xFF, 0xFF, 0xA, 0xA, 0xD, 0x10, 0x14, 0x17, 0x1A}; - UINT8 i; - UINT8 TxpVal; - UINT8 TxpdllVal; - UINT16 Speed; - - Speed = NBPtr->DCTPtr->Timings.Speed; - i = (UINT8) ((Speed < DDR800_FREQUENCY) ? ((Speed / 66) - 3) : (Speed / 133)); - ASSERT (i < sizeof (Txp)); - ASSERT (i < sizeof (Txpdll)); - - TxpdllVal = Txpdll[i]; - - if ((NBPtr->MCTPtr->Status[SbLrdimms] || NBPtr->MCTPtr->Status[SbRegistered]) && - ((NBPtr->DCTPtr->Timings.Speed == DDR667_FREQUENCY) || (NBPtr->DCTPtr->Timings.Speed == DDR800_FREQUENCY)) && - (NBPtr->RefPtr->DDR3Voltage == VOLT1_25)) { - TxpVal = 4; - } else { - TxpVal = Txp[i]; - } - - if (TxpVal != 0xFF) { - MemNSetBitFieldNb (NBPtr, BFTxp, TxpVal); - } - if (TxpdllVal != 0xFF) { - NBPtr->FamilySpecificHook[AdjustTxpdll] (NBPtr, &TxpdllVal); - MemNSetBitFieldNb (NBPtr, BFTxpdll, TxpdllVal); - } -} - -/*----------------------------------------------------------------------------- - * - * - * This function adjust value of Txpdll to encoded value. - * - * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK - * @param[in,out] OptParam - Optional parameter - * - * @return TRUE - * ---------------------------------------------------------------------------- - */ -BOOLEAN -MemNAdjustTxpdllClientNb ( - IN OUT MEM_NB_BLOCK *NBPtr, - IN OUT VOID *OptParam - ) -{ - *(UINT8 *) OptParam -= 10; - return TRUE; -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * This function is a wrapper to handle or switch NB Pstate for UNB - * - * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK - * @param[in] *NBPstate - NB Pstate - * - * @return TRUE - Succeed - * @return FALSE - Fail - */ - -BOOLEAN -MemNChangeNbFrequencyWrapUnb ( - IN OUT MEM_NB_BLOCK *NBPtr, - IN UINT32 NBPstate - ) -{ - UINT8 TargetNbPs; - UINT32 FreqNumeratorInMHz; - UINT32 FreqDivisor; - UINT32 VoltageInuV; - UINT8 NbPstateMaxVal; - CPU_SPECIFIC_SERVICES *FamilySpecificServices; - - if (NBPtr->NbFreqChgState == 0) { - // While in state 0, keep NB Pstate at the highest supported - TargetNbPs = 0; - if (NBPtr->NbPsCtlReg == 0) { - // Save NbPsCtl register on the first run - NBPtr->NbPsCtlReg = MemNGetBitFieldNb (NBPtr, BFNbPstateCtlReg); - } else { - // Do not need to switch NB Pstate again if it is already at highest - return TRUE; - } - } else if (NBPtr->NbFreqChgState < 4) { - // While in other states, go to the next lower NB Pstate - TargetNbPs = (UINT8) MemNGetBitFieldNb (NBPtr, BFCurNbPstate) + 1; - } else { - // When done with training, release NB Pstate force by restoring NbPsCtl register - NBPtr->FamilySpecificHook[ReleaseNbPstate] (NBPtr, NBPtr); - IDS_HDT_CONSOLE (MEM_FLOW, "\tRelease NB Pstate force\n"); - return TRUE; - } - - // Make sure target NB Pstate is enabled, else find next enabled NB Pstate - GetCpuServicesOfCurrentCore ((const CPU_SPECIFIC_SERVICES **) &FamilySpecificServices, &NBPtr->MemPtr->StdHeader); - for (; TargetNbPs < 4; TargetNbPs++) { - if (FamilySpecificServices->GetNbPstateInfo (FamilySpecificServices, - NBPtr->MemPtr->PlatFormConfig, - &NBPtr->PciAddr, - (UINT32) TargetNbPs, - &FreqNumeratorInMHz, - &FreqDivisor, - &VoltageInuV, - &(NBPtr->MemPtr->StdHeader))) { - // Record NCLK speed - NBPtr->NBClkFreq = FreqNumeratorInMHz / FreqDivisor; - break; - } - } - - if (TargetNbPs < 4) { - IDS_HDT_CONSOLE (MEM_FLOW, "\tNB P%d: %dMHz\n", TargetNbPs, NBPtr->NBClkFreq); - - // 1.Program the configuration registers which contain multiple internal copies for each NB P-state. See - // D18F1x10C[NbPsSel]. - MemNSetBitFieldNb (NBPtr, BFNbPsSel, TargetNbPs); - - // Check to see if NB P-states have been disabled. @todo This should only be needed for - // bring up, but must be included in any releases that occur before NB P-state operation - // has been debugged/fixed. - if ((NBPtr->NbPsCtlReg & 0x00004000) == 0) { - // 2.Program D18F5x170 to transition the NB P-state: - // NbPstateLo = NbPstateMaxVal. (HW requires an intermediate transition to low) - // SwNbPstateLoDis = NbPstateDisOnP0 = NbPstateThreshold = 0. - NbPstateMaxVal = (UINT8) MemNGetBitFieldNb (NBPtr, BFNbPstateMaxVal); - MemNSetBitFieldNb (NBPtr, BFNbPstateLo, NbPstateMaxVal); - MemNSetBitFieldNb (NBPtr, BFNbPstateCtlReg, MemNGetBitFieldNb (NBPtr, BFNbPstateCtlReg) & 0xFFFF91FF); - - // 3.Wait for D18F5x174[CurNbPstate] to equal NbPstateLo. - MemNPollBitFieldNb (NBPtr, BFCurNbPstate, NbPstateMaxVal, PCI_ACCESS_TIMEOUT, TRUE); - - // 4.Program D18F5x170 to force the NB P-state: - // NbPstateHi = target NB P-state. - // SwNbPstateLoDis = 1 (triggers the transition) - MemNSetBitFieldNb (NBPtr, BFNbPstateHi, TargetNbPs); - MemNSetBitFieldNb (NBPtr, BFSwNbPstateLoDis, 1); - - // 5.Wait for D18F5x174[CurNbPstate] to equal the target NB P-state. - MemNPollBitFieldNb (NBPtr, BFCurNbPstate, TargetNbPs, PCI_ACCESS_TIMEOUT, TRUE); - } - - // When NB frequency change succeeds, TSC rate may have changed. - // We need to update TSC rate - FamilySpecificServices->GetTscRate (FamilySpecificServices, &NBPtr->MemPtr->TscRate, &NBPtr->MemPtr->StdHeader); - } else { - // Cannot find a supported NB Pstate to switch to - // Release NB Pstate force by restoring NbPsCtl register - NBPtr->FamilySpecificHook[ReleaseNbPstate] (NBPtr, NBPtr); - IDS_HDT_CONSOLE (MEM_FLOW, "\tRelease NB Pstate force\n"); - return FALSE; - } - return TRUE; -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * - * This function sends an MRS command for Unb - * - * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK - * - */ - -VOID -MemNSendMrsCmdUnb ( - IN OUT MEM_NB_BLOCK *NBPtr - ) -{ - MemNSwapBitsUnb (NBPtr); - - IDS_HDT_CONSOLE (MEM_FLOW, "\t\t\tCS%d MR%d %05x\n", - (MemNGetBitFieldNb (NBPtr, BFMrsChipSel) & 0x7), - (MemNGetBitFieldNb (NBPtr, BFMrsBank) & 0x7), - (MemNGetBitFieldNb (NBPtr, BFMrsAddress) & 0x3FFFF)); - - // 1.Set SendMrsCmd=1 - MemNSetBitFieldNb (NBPtr, BFSendMrsCmd, 1); - - // 2.Wait for SendMrsCmd=0 - MemNPollBitFieldNb (NBPtr, BFSendMrsCmd, 0, PCI_ACCESS_TIMEOUT, FALSE); -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * - * This function returns MR0[CL] value with table driven support - * - * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK - * - * @return MR0[CL] value - */ -UINT32 -MemNGetMR0CLTblDrvNb ( - IN OUT MEM_NB_BLOCK *NBPtr - ) -{ - return (UINT32) ((NBPtr->PsPtr->MR0CL31 << 4) | (NBPtr->PsPtr->MR0CL0 << 2)); -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * - * This function performs MaxRdLat training for slot 1 - * - * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK - * @param[in,out] TestAddrRJ16 - Test address - * - * @return TRUE - * ---------------------------------------------------------------------------- - */ -BOOLEAN -MemNSlot1MaxRdLatTrainClientNb ( - IN OUT MEM_NB_BLOCK *NBPtr, - IN OUT VOID *TestAddrRJ16 - ) -{ - UINT8 DummyBuffer[8]; - UINT16 MaxLatDly; - UINT8 i; - - // Perform slot1 specific training: - // A.Program D18F2x[1,0]78[SlotSel]=1. Force read CAS to fifo slot1 for training. - // B.Program D18F2x[1,0]78[MaxRdLatency] = TrainedMaxRdLatency. Set to last slot0 value that passed. - // C.Read the DIMM test addresses. - // D.Compare the values read against the pattern written. - - IDS_HDT_CONSOLE (MEM_FLOW, "\n\t\tTrain Slot 1: \n"); - MemNSetBitFieldNb (NBPtr, BFSlotSel, 1); - - MaxLatDly = (UINT16) (MemNGetBitFieldNb (NBPtr, BFMaxLatency) + 1); // Add 1 to get back to the last passing value - MemNSetBitFieldNb (NBPtr, BFMaxLatency, MaxLatDly); - - for (i = 0; i < 100; i++) { - IDS_HDT_CONSOLE (MEM_FLOW, "\t\t\tDly %3x", MaxLatDly); - - NBPtr->ReadPattern (NBPtr, DummyBuffer, *(UINT32*)TestAddrRJ16, 6); - - if (NBPtr->CompareTestPattern (NBPtr, DummyBuffer, DummyBuffer, 6 * 64) == 0xFFFF) { - IDS_HDT_CONSOLE (MEM_FLOW, " P"); - break; - } - IDS_HDT_CONSOLE (MEM_FLOW, "\n"); - } - - if (i < 100) { - MemNSetBitFieldNb (NBPtr, BFSlot1ExtraClkEn, 0); - } else { - MemNSetBitFieldNb (NBPtr, BFSlot1ExtraClkEn, 1); - } - - MemNSetBitFieldNb (NBPtr, BFMaxSkipErrTrain, 0); - - return TRUE; -} - - -/* -----------------------------------------------------------------------------*/ -/** - * - * - * This function programs dram power management timing related registers - * - * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK - * - * @return none - * ---------------------------------------------------------------------------- - */ -VOID -MemNDramPowerMngTimingNb ( - IN OUT MEM_NB_BLOCK *NBPtr - ) -{ - STATIC CONST UINT8 Tckesr[] = {4, 4, 5, 5, 6, 7, 2, 2}; - UINT8 Tck; - - // These timings are based on DDR3 spec - // Tcksrx = max(5 nCK, 10 ns) - Tck = (UINT8) MAX (5, (MemUnsToMemClk (NBPtr->DCTPtr->Timings.Speed, 10))); - MemNSetBitFieldNb (NBPtr, BFTcksrx, MIN (0xE, MAX (Tck, 2))); - - // Tcksre = max(5 nCK, 10 ns) - MemNSetBitFieldNb (NBPtr, BFTcksre, MIN (0x27, MAX (Tck, 5))); - - // Tckesr = tCKE(min) + 1 nCK - // tCKE(min) - // DDR-800 7,5ns = 3nCk max(3nCK, 7.5ns) + 1 = 3nCK + 1nCK = 4nCK - // DDR-1066 5.625ns = 3nCK max(3nCK, 5.625ns) + 1 = 3nCL + 1nCK = 4nCK - // DDR-1333 5.625ns = 4nCK max(3nCK, 4nCK) + 1 = 4nCK + 1nCK = 5nCK - // DDR-1600 5ns = 4nCK max(3nCK, 4nCK) + 1 = 4nCK + 1nCK = 5nCK - // DDR-1866 5ns = 5nCK max(3nCK, 5nCK) + 1 = 5nCK + 1nCK = 6nCK - // DDR-2133 5ns = 6nCK max(3nCK, 6nCK) + 1 = 6nCK + 1nCK = 7nCK - MemNSetBitFieldNb (NBPtr, BFTckesr, Tckesr[(NBPtr->DCTPtr->Timings.Speed / 133) - 3]); - - // Tpd = tCKE(min) - MemNSetBitFieldNb (NBPtr, BFTpd, Tckesr[(NBPtr->DCTPtr->Timings.Speed / 133) - 3] - 1); -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * The function resets Rcv Fifo - * - * @param[in,out] *TechPtr - Pointer to the MEM_TECH_BLOCK - * @param[in] Dummy - Dummy parameter - * - */ - -VOID -MemTResetRcvFifoUnb ( - IN OUT struct _MEM_TECH_BLOCK *TechPtr, - IN UINT8 Dummy - ) -{ - // Program D18F2x9C_x0000_0050_dct[1:0]=00000000h - MemNSetBitFieldNb (TechPtr->NBPtr, BFRstRcvFifo, 0); -} \ No newline at end of file diff --git a/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/mnfeat.c b/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/mnfeat.c deleted file mode 100644 index 99d8a16aeb..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/mnfeat.c +++ /dev/null @@ -1,1293 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * mnfeat.c - * - * Common Northbridge features - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: (Mem/NB) - * @e \$Revision: 49104 $ @e \$Date: 2011-03-17 06:54:25 +0800 (Thu, 17 Mar 2011) $ - * - **/ -/***************************************************************************** -* -* Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* *************************************************************************** -* -*/ - -/* - *---------------------------------------------------------------------------- - * MODULES USED - * - *---------------------------------------------------------------------------- - */ - -#include "AGESA.h" -#include "AdvancedApi.h" -#include "amdlib.h" -#include "Ids.h" -#include "OptionMemory.h" -#include "mm.h" -#include "mn.h" -#include "mu.h" -#include "PlatformMemoryConfiguration.h" -#include "merrhdl.h" -#include "Filecode.h" -CODE_GROUP (G1_PEICC) -RDATA_GROUP (G1_PEICC) - -#define FILECODE PROC_MEM_NB_MNFEAT_FILECODE -/*---------------------------------------------------------------------------- - * DEFINITIONS AND MACROS - * - *---------------------------------------------------------------------------- - */ -#define MAX_CL_CONT_READ 32 -#define MAX_CL_CONT_WRITE 32 - -/*---------------------------------------------------------------------------- - * TYPEDEFS AND STRUCTURES - * - *---------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------- - * PROTOTYPES OF LOCAL FUNCTIONS - * - *---------------------------------------------------------------------------- - */ -VOID -MemNInitCPGNb ( - IN OUT MEM_NB_BLOCK *NBPtr - ); - -VOID -MemNInitDqsTrainRcvrEnHwNb ( - IN OUT MEM_NB_BLOCK *NBPtr - ); - -VOID -MemNDisableDqsTrainRcvrEnHwNb ( - IN OUT MEM_NB_BLOCK *NBPtr - ); - -VOID -STATIC -MemNContWritePatternNb ( - IN OUT MEM_NB_BLOCK *NBPtr, - IN UINT32 Address, - IN UINT8 Pattern[], - IN UINT16 ClCount - ); - -VOID -STATIC -MemNContReadPatternNb ( - IN OUT MEM_NB_BLOCK *NBPtr, - IN UINT8 Buffer[], - IN UINT32 Address, - IN UINT16 ClCount - ); - -VOID -STATIC -MemNGenHwRcvEnReadsNb ( - IN OUT MEM_NB_BLOCK *NBPtr, - IN UINT32 Address - ); - -VOID -MemNInitCPGClientNb ( - IN OUT MEM_NB_BLOCK *NBPtr - ); - -UINT16 -STATIC -MemNCompareTestPatternClientNb ( - IN OUT MEM_NB_BLOCK *NBPtr, - IN UINT8 Buffer[], - IN UINT8 Pattern[], - IN UINT16 ByteCount - ); - -UINT16 -STATIC -MemNInsDlyCompareTestPatternClientNb ( - IN OUT MEM_NB_BLOCK *NBPtr, - IN UINT8 Buffer[], - IN UINT8 Pattern[], - IN UINT16 ByteCount - ); - -VOID -STATIC -MemNContWritePatternClientNb ( - IN OUT MEM_NB_BLOCK *NBPtr, - IN UINT32 Address, - IN UINT8 Pattern[], - IN UINT16 ClCount - ); - -VOID -STATIC -MemNContReadPatternClientNb ( - IN OUT MEM_NB_BLOCK *NBPtr, - IN UINT8 Buffer[], - IN UINT32 Address, - IN UINT16 ClCount - ); - -VOID -STATIC -MemNGenHwRcvEnReadsClientNb ( - IN OUT MEM_NB_BLOCK *NBPtr, - IN UINT32 Address - ); - -BOOLEAN -STATIC -MemNBeforeMemClrClientNb ( - IN OUT MEM_NB_BLOCK *NBPtr, - IN VOID *UnUsed - ); - -VOID -STATIC -MemNGenHwRcvEnReadsUnb ( - IN OUT MEM_NB_BLOCK *NBPtr, - IN UINT32 Address - ); - -VOID -STATIC -MemNRrwActivateCmd ( - IN OUT MEM_NB_BLOCK *NBPtr, - IN UINT8 ChipSelect, - IN UINT8 Bank, - IN UINT32 RowAddress - ); - -VOID -STATIC -MemNRrwPrechargeCmd ( - IN OUT MEM_NB_BLOCK *NBPtr, - IN UINT8 ChipSelect, - IN UINT8 Bank - ); - -VOID -STATIC -MemNContReadPatternUnb ( - IN OUT MEM_NB_BLOCK *NBPtr, - IN UINT8 Buffer[], - IN UINT32 Address, - IN UINT16 ClCount - ); - -VOID -STATIC -MemNContWritePatternUnb ( - IN OUT MEM_NB_BLOCK *NBPtr, - IN UINT32 Address, - IN UINT8 Pattern[], - IN UINT16 ClCount - ); - -VOID -MemNInitCPGUnb ( - IN OUT MEM_NB_BLOCK *NBPtr - ); - -/*---------------------------------------------------------------------------- - * EXPORTED FUNCTIONS - * - *---------------------------------------------------------------------------- - */ - -/* -----------------------------------------------------------------------------*/ -/** - * - * This function assigns read/write function pointers to CPG read/write modules. - * - * @param[in,out] NBPtr - Pointer to the MEM_NB_BLOCK - * - */ -VOID -MemNInitCPGNb ( - IN OUT MEM_NB_BLOCK *NBPtr - ) -{ - NBPtr->WritePattern = MemNContWritePatternNb; - NBPtr->ReadPattern = MemNContReadPatternNb; - NBPtr->GenHwRcvEnReads = MemNGenHwRcvEnReadsNb; -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * This function initializes member functions of HW Rx En Training. - * - * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK - * - */ - -VOID -MemNInitDqsTrainRcvrEnHwNb ( - IN OUT MEM_NB_BLOCK *NBPtr - ) -{ - NBPtr->MemNPrepareRcvrEnDlySeed = MemNPrepareRcvrEnDlySeedNb; -} -/* -----------------------------------------------------------------------------*/ -/** - * - * This function disables member functions of Hw Rx En Training. - * - * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK - * - */ - -VOID -MemNDisableDqsTrainRcvrEnHwNb ( - IN OUT MEM_NB_BLOCK *NBPtr - ) -{ - NBPtr->MemNPrepareRcvrEnDlySeed = (VOID (*) (MEM_NB_BLOCK *)) memDefRet; -} - -/*---------------------------------------------------------------------------- - * LOCAL FUNCTIONS - * - *---------------------------------------------------------------------------- - */ - -/* -----------------------------------------------------------------------------*/ -/** - * - * This function writes 9 or 18 cache lines continuously using GH CPG engine - * - * @param[in,out] NBPtr - Pointer to the MEM_NB_BLOCK - * @param[in] Pattern - Array of bytes that will be written to DRAM - * @param[in] Address - System Address [47:16] - * @param[in] ClCount - Number of cache lines - * - */ -VOID -STATIC -MemNContWritePatternNb ( - IN OUT MEM_NB_BLOCK *NBPtr, - IN UINT32 Address, - IN UINT8 Pattern[], - IN UINT16 ClCount - ) -{ - UINT16 ClDiff; - if (ClCount > MAX_CL_CONT_WRITE) { - ClDiff = ClCount - MAX_CL_CONT_WRITE; - ClCount = MAX_CL_CONT_WRITE; - } else { - ClDiff = 0; - } - - // Set F2x11C[MctWrLimit] to desired number of cachelines in the burst. - MemNSetBitFieldNb (NBPtr, BFMctWrLimit, MAX_CL_CONT_WRITE - ClCount); - - // Issue the stream of writes. When F2x11C[MctWrLimit] is reached (or when F2x11C[FlushWr] is set - // again), all the writes are written to DRAM. - Address = MemUSetUpperFSbase (Address, NBPtr->MemPtr); - MemUWriteCachelines (Address, Pattern, ClCount); - - // Flush out prior writes by setting F2x11C[FlushWr]. - MemNSetBitFieldNb (NBPtr, BFFlushWr, 1); - // Wait for F2x11C[FlushWr] to clear, indicating prior writes have been flushed. - while (MemNGetBitFieldNb (NBPtr, BFFlushWr) != 0) {} - - // Set F2x11C[MctWrLimit] to 1Fh to disable write bursting. - MemNSetBitFieldNb (NBPtr, BFMctWrLimit, 0x1F); - - if (ClDiff > 0) { - MemNContWritePatternNb (NBPtr, Address + (MAX_CL_CONT_WRITE * 64), Pattern + (MAX_CL_CONT_WRITE * 64), ClDiff); - } -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * - * This function reads 9 or 18 cache lines continuously using GH CPG engine - * - * @param[in,out] NBPtr - Pointer to the MEM_NB_BLOCK - * @param[in,out] Buffer - Array of bytes to be filled with data read from DRAM - * @param[in] Address - System Address [47:16] - * @param[in] ClCount - Number of cache lines - * - */ - -VOID -STATIC -MemNContReadPatternNb ( - IN OUT MEM_NB_BLOCK *NBPtr, - IN UINT8 Buffer[], - IN UINT32 Address, - IN UINT16 ClCount - ) -{ - BOOLEAN DisAutoRefresh; - UINT16 ClDiff; - if (ClCount > MAX_CL_CONT_READ) { - ClDiff = ClCount - MAX_CL_CONT_READ; - ClCount = MAX_CL_CONT_READ; - } else { - ClDiff = 0; - } - - Address = MemUSetUpperFSbase (Address, NBPtr->MemPtr); - - // 1. BIOS ensures that the only accesses outstanding to the MCT are training reads. - // 2. If F2x[1, 0]90[BurstLength32]=1, then BIOS ensures that the DCTs and DRAMs are configured for 64 - // byte bursts (8-beat burst length). This requires that BIOS issue MRS commands to the devices - // to change to an 8-beat burst length and then to restore the desired burst length after training - // is complete. - - if (MemNGetBitFieldNb (NBPtr, BFDisAutoRefresh) == 0) { - DisAutoRefresh = FALSE; - // 3. BIOS programs F2x[1, 0]90[ForceAutoPchg] = 0 and F2x[1, 0]8C[DisAutoRefresh] = 1. - // 4. If necessary, BIOS programs F2x[1, 0]78[EarlyArbEn] = 1 at this time. See register description. - MemNSetBitFieldNb (NBPtr, BFDisAutoRefresh, 1); - // MemNSetBitFieldNb (NBPtr, BFForceAutoPchg, 0); // ForceAutoPchg is 0 by default. - MemNSetBitFieldNb (NBPtr, BFZqcsInterval, 0); - } else { - DisAutoRefresh = TRUE; - } - - MemNSetBitFieldNb (NBPtr, BFPrefCpuDis, 0); - - // 5. BIOS sets F2x11C[MctPrefReqLimit] to the number of training reads (Ntrain) it wishes to generate in the - // training sequence. - MemNSetBitFieldNb (NBPtr, BFMctPrefReqLimit, ClCount - 1); - - // 6. BIOS sets F2x11C[PrefDramTrainMode] bit. - // 7. The act of setting F2x11C[PrefDramTrainMode] causes the MCT to flush out the prefetch stride predictor - // table (removing any existing prefetch stride patterns). - MemNSetBitFieldNb (NBPtr, BFPrefDramTrainMode, 1); - - // 8. BIOS issues an SFENCE (or other serializing instruction) to ensure that the prior write completes. - // 9. For revision C and earlier processors, BIOS generates two training reads. For revision D processors BIOS - // generates three training reads. Three are required to detect the stride with DCQ buddy enabled. These must - // be to consecutive cache lines (i.e. 64 bytes apart) and must not cross a naturally aligned 4 Kbyte boundary. - // 10. These reads set up a stride pattern which is detected by the prefetcher. The prefetcher then continues to - // issue prefetches until F2x11C[MctPrefReqLimit] is reached, at which point the MCT clears - // F2x11C[PrefDramTrainMode]. - MemUDummyCLRead (Address); - MemUDummyCLRead (Address + 0x40); - if (NBPtr->IsSupported[CheckDummyCLRead]) { - MemUDummyCLRead (Address + 0x80); - } - // 11. BIOS issues the remaining (Ntrain - 2 for revisions C and earlier or Ntrain - 3 for revision D) reads after - // checking that F2x11C[PrefDramTrainMode] is cleared. These reads must be to consecutive cache lines - // (i.e., 64 bytes apart) and must not cross a naturally aligned 4KB boundary. These reads hit the prefetches - // and read the data from the prefetch buffer. - while (MemNGetBitFieldNb (NBPtr, BFPrefDramTrainMode) != 0) {} - MemUReadCachelines (Buffer, Address, ClCount); - - // 14. BIOS restores the target values for F2x[1, 0]90[ForceAutoPchg], F2x[1, 0]8C[DisAutoRefresh] and - // F2x[1, 0]90[BurstLength32]. - if (!DisAutoRefresh) { - MemNSetBitFieldNb (NBPtr, BFDisAutoRefresh, 0); - MemNSetBitFieldNb (NBPtr, BFZqcsInterval, 2); - } - - if (ClDiff > 0) { - MemNContReadPatternNb (NBPtr, Buffer + (MAX_CL_CONT_READ * 64), Address + (MAX_CL_CONT_READ * 64), ClDiff); - } -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * - * This function generates a continuous burst of reads during HW RcvEn training. - * - * @param[in,out] NBPtr - Pointer to the MEM_NB_BLOCK - * @param[in] Address - System Address [47:16] - * - */ -VOID -STATIC -MemNGenHwRcvEnReadsNb ( - IN OUT MEM_NB_BLOCK *NBPtr, - IN UINT32 Address - ) -{ - UINT8 TempBuffer[12 * 64]; - UINT8 BurstCount; - - for (BurstCount = 0; BurstCount < 10; BurstCount++) { - NBPtr->ReadPattern (NBPtr, TempBuffer, Address, 12); - NBPtr->FlushPattern (NBPtr, Address, 12); - } -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * This function writes cache lines continuously using TCB CPG engine - * - * @param[in,out] NBPtr - Pointer to the MEM_NB_BLOCK - * @param[in] Pattern - Array of bytes that will be written to DRAM - * @param[in] Address - System Address [47:16] - * @param[in] ClCount - Number of cache lines - * - */ -VOID -STATIC -MemNContWritePatternClientNb ( - IN OUT MEM_NB_BLOCK *NBPtr, - IN UINT32 Address, - IN UINT8 Pattern[], - IN UINT16 ClCount - ) -{ - UINT32 PatternHash; - UINT32 *DwordPtr; - UINT16 i; - UINT16 j; - UINT16 Multiplier; - - Multiplier = 1; - - // 1. Program D18F2x1C0[WrDramTrainMode]=1. - MemNSetBitFieldNb (NBPtr, BFWrDramTrainMode, 1); - - PatternHash = ClCount << 24; - for (i = 0; i < 3; i ++) { - PatternHash |= (Pattern[i * ClCount * 24 + 9] << (8 * i)); - } - if (NBPtr->CPGInit != PatternHash) { - - if (ClCount == 3) { - // Double pattern length for MaxRdLat training - Multiplier = 2; - } - - // If write training buffer has not been initialized, initialize it - // 2. Program D18F2x1C0[TrainLength] to the appropriate number of cache lines. - MemNSetBitFieldNb (NBPtr, BFTrainLength, ClCount * Multiplier); - - // 3. Program D18F2x1D0[WrTrainBufAddr]=000h. - MemNSetBitFieldNb (NBPtr, BFWrTrainBufAddr, 0); - - // 4. Successively write each dword of the training pattern to D18F2x1D4. - DwordPtr = (UINT32 *) Pattern; - for (j = 0; j < Multiplier; j++) { - for (i = 0; i < (ClCount * 16); i++) { - MemNSetBitFieldNb (NBPtr, BFWrTrainBufDat, DwordPtr[i]); - } - } - - NBPtr->CPGInit = PatternHash; - } - - // 5. Program D18F2x1D0[WrTrainBufAddr]=000h - MemNSetBitFieldNb (NBPtr, BFWrTrainBufAddr, 0); - - // 6. Program the DRAM training address - MemNSetBitFieldNb (NBPtr, BFWrTrainAdrPtrLo, Address << (16 - 6)); - MemNSetBitFieldNb (NBPtr, BFWrTrainAdrPtrHi, (Address >> (38 - 16)) & 3); - - // 7. Program D18F2x1C0[WrTrainGo]=1. - MemNSetBitFieldNb (NBPtr, BFWrTrainGo, 1); - - // 8. Wait for D18F2x1C0[WrTrainGo]=0. - while (MemNGetBitFieldNb (NBPtr, BFWrTrainGo) != 0) {} - - // 9. Program D18F2x1C0[WrDramTrainMode]=0. - MemNSetBitFieldNb (NBPtr, BFWrDramTrainMode, 0); -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * - * This function reads cache lines continuously using TCB CPG engine - * - * @param[in,out] NBPtr - Pointer to the MEM_NB_BLOCK - * @param[in,out] Buffer - Array of bytes to be filled with data read from DRAM - * @param[in] Address - System Address [47:16] - * @param[in] ClCount - Number of cache lines - * - */ - -VOID -STATIC -MemNContReadPatternClientNb ( - IN OUT MEM_NB_BLOCK *NBPtr, - IN UINT8 Buffer[], - IN UINT32 Address, - IN UINT16 ClCount - ) -{ - UINT16 Multiplier; - - Multiplier = 1; - if (ClCount == 3) { - // Double pattern length for MaxRdLat training - Multiplier = 2; - } - - // 1. Program D18F2x1C0[RdDramTrainMode]=1. - MemNSetBitFieldNb (NBPtr, BFRdDramTrainMode, 1); - - // 2. Program D18F2x1C0[TrainLength] to the appropriate number of cache lines. - MemNSetBitFieldNb (NBPtr, BFTrainLength, ClCount * Multiplier); - - // 3. Program the DRAM training address as follows: - MemNSetBitFieldNb (NBPtr, BFWrTrainAdrPtrLo, Address << (16 - 6)); - MemNSetBitFieldNb (NBPtr, BFWrTrainAdrPtrHi, (Address >> (38 - 16)) & 3); - - // 4. Program D18F2x1D0[WrTrainBufAddr]=000h - MemNSetBitFieldNb (NBPtr, BFWrTrainBufAddr, 0); - - // 5. Program D18F2x1C0[RdTrainGo]=1. - MemNSetBitFieldNb (NBPtr, BFRdTrainGo, 1); - - // 6. Wait for D18F2x1C0[RdTrainGo]=0. - while (MemNGetBitFieldNb (NBPtr, BFRdTrainGo) != 0) {} - - // 7. Read D18F2x1E8[TrainCmpSts] and D18F2x1E8[TrainCmpSts2]. - // This step will be accomplished in Compare routine. - - // 8. Program D18F2x1C0[RdDramTrainMode]=0. - MemNSetBitFieldNb (NBPtr, BFRdDramTrainMode, 0); -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * - * This function generates a continuous burst of reads during HW RcvEn training. - * - * @param[in,out] NBPtr - Pointer to the MEM_NB_BLOCK - * @param[in] Address - System Address [47:16] - * - */ -VOID -STATIC -MemNGenHwRcvEnReadsClientNb ( - IN OUT MEM_NB_BLOCK *NBPtr, - IN UINT32 Address - ) -{ - UINT8 TempBuffer[64]; - UINT8 Count; - - for (Count = 0; Count < 3; Count++) { - NBPtr->ReadPattern (NBPtr, TempBuffer, Address, 64); - } -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * This function assigns read/write function pointers to CPG read/write modules. - * - * @param[in,out] NBPtr - Pointer to the MEM_NB_BLOCK - * - */ -VOID -MemNInitCPGClientNb ( - IN OUT MEM_NB_BLOCK *NBPtr - ) -{ - NBPtr->WritePattern = MemNContWritePatternClientNb; - NBPtr->ReadPattern = MemNContReadPatternClientNb; - NBPtr->GenHwRcvEnReads = MemNGenHwRcvEnReadsClientNb; - NBPtr->FlushPattern = (VOID (*) (MEM_NB_BLOCK *, UINT32, UINT16)) memDefRet; - NBPtr->CompareTestPattern = MemNCompareTestPatternClientNb; - NBPtr->InsDlyCompareTestPattern = MemNInsDlyCompareTestPatternClientNb; - NBPtr->FamilySpecificHook[BeforeMemClr] = MemNBeforeMemClrClientNb; - NBPtr->CPGInit = 0; -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * This function compares test pattern with data in buffer and - * return a pass/fail bitmap for 8 bytelanes (upper 8 bits are reserved) - * - * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK - * @param[in] Buffer[] - Buffer data from DRAM (Measured data from DRAM) to compare - * @param[in] Pattern[] - Pattern (Expected data in ROM/CACHE) to compare against - * @param[in] ByteCount - Byte count - * - * @return PASS - Bitmap of results of comparison - */ - -UINT16 -STATIC -MemNCompareTestPatternClientNb ( - IN OUT MEM_NB_BLOCK *NBPtr, - IN UINT8 Buffer[], - IN UINT8 Pattern[], - IN UINT16 ByteCount - ) -{ - return ~((UINT16) MemNGetBitFieldNb (NBPtr, BFTrainCmpSts)); -} - -/*-----------------------------------------------------------------------------*/ -/** - * - * This function compares test pattern with data in buffer and - * return a pass/fail bitmap for 8 bytelanes (upper 8 bits are reserved) - * - * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK - * @param[in] Buffer[] - Buffer data from DRAM (Measured data from DRAM) to compare - * @param[in] Pattern[] - Pattern (Expected data in ROM/CACHE) to compare against - * @param[in] ByteCount - Byte count - * - * @retval Bitmap of results of comparison - */ -UINT16 -STATIC -MemNInsDlyCompareTestPatternClientNb ( - IN OUT MEM_NB_BLOCK *NBPtr, - IN UINT8 Buffer[], - IN UINT8 Pattern[], - IN UINT16 ByteCount - ) -{ - return ~((UINT16) MemNGetBitFieldNb (NBPtr, BFTrainCmpSts2)); -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * This function calculates RcvEn seed value for each rank - * - * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK - * - */ -VOID -MemNPrepareRcvrEnDlySeedNb ( - IN OUT MEM_NB_BLOCK *NBPtr - ) -{ - MEM_TECH_BLOCK *TechPtr; - CH_DEF_STRUCT *ChannelPtr; - DIE_STRUCT *MCTPtr; - UINT16 SeedTotal; - UINT16 SeedFine; - UINT16 SeedGross; - UINT16 SeedPreGross; - UINT16 SeedTotalPreScaling; - UINT8 ByteLane; - UINT16 Speed; - UINT16 PlatEst; - UINT8 ChipSel; - UINT8 Pass; - UINT16 *PlatEstSeed; - UINT16 SeedValue[9]; - UINT16 SeedTtl[9]; - UINT16 SeedPre[9]; - - TechPtr = NBPtr->TechPtr; - MCTPtr = NBPtr->MCTPtr; - ChannelPtr = TechPtr->NBPtr->ChannelPtr; - Speed = NBPtr->DCTPtr->Timings.Speed; - SeedTotalPreScaling = 0; - ChipSel = TechPtr->ChipSel; - Pass = TechPtr->Pass; - - for (ByteLane = 0; ByteLane < (MCTPtr->Status[SbEccDimms] ? 9 : 8); ByteLane++) { - TechPtr->Bytelane = ByteLane; - if (Pass == 1) { - // Get platform override seed - PlatEstSeed = (UINT16 *) FindPSOverrideEntry (NBPtr->RefPtr->PlatformMemoryConfiguration, PSO_RXEN_SEED, MCTPtr->SocketId, ChannelPtr->ChannelID); - // For Pass1, BIOS starts with the delay value obtained from the first pass of write - // levelization training that was done in DDR3 Training and add a delay value of 3Bh. - PlatEst = 0x3B; - NBPtr->FamilySpecificHook[OverrideRcvEnSeed] (NBPtr, &PlatEst); - PlatEst = ((PlatEstSeed != NULL) ? PlatEstSeed[ByteLane] : PlatEst); - SeedTotal = ChannelPtr->WrDqsDlys[(ChipSel >> 1) * TechPtr->DlyTableWidth () + ByteLane] + PlatEst; - SeedValue[ByteLane] = PlatEst; - } else { - // For Pass2 - // SeedTotalPreScaling = (the total delay values in D18F2x[1,0]9C_x0000_00[24:10] from pass 1 of - // DQS receiver enable training) - 20h. Subtract 1UI to get back to preamble left edge. - if (((ChipSel & 1) == 0) && NBPtr->FamilySpecificHook[TrainingNibbleZero] (NBPtr, &ChipSel)) { - // Save Seed for odd CS SeedTotalPreScaling RxEn Value - TechPtr->PrevPassRcvEnDly[ByteLane] = ChannelPtr->RcvEnDlys[(ChipSel >> 1) * TechPtr->DlyTableWidth () + ByteLane]; - } - NBPtr->FamilySpecificHook[OverridePrevPassRcvEnDly] (NBPtr, &TechPtr->PrevPassRcvEnDly[ByteLane]); - SeedTotalPreScaling = TechPtr->PrevPassRcvEnDly[ByteLane] - 0x20; - // SeedTotal = SeedTotalPreScaling*target frequency/lowest supported frequency. - SeedTotal = (UINT16) (((UINT32) SeedTotalPreScaling * Speed) / TechPtr->PrevSpeed); - NBPtr->FamilySpecificHook[OverrideRcvEnSeedPassN] (NBPtr, &SeedTotal); - } - SeedTtl[ByteLane] = SeedTotal; - - // SeedGross = SeedTotal DIV 32. - SeedGross = SeedTotal >> 5; - // SeedFine = SeedTotal MOD 32. - SeedFine = SeedTotal & 0x1F; - // Next, determine the gross component of SeedTotal. SeedGrossPass1=SeedTotal DIV 32. - // Then, determine the fine delay component of SeedTotal. SeedFinePass1=SeedTotal MOD 32. - // Use SeedGrossPass1 to determine SeedPreGrossPass1: - - if ((SeedGross & 0x1) != 0) { - //if SeedGross is odd - SeedPreGross = 1; - } else { - //if SeedGross is even - SeedPreGross = 2; - } - // (SeedGross - SeedPreGross) - TechPtr->DiffSeedGrossSeedPreGross[ByteLane] = (SeedGross - SeedPreGross) << 5; - - //BIOS programs registers F2x[1, 0]9C_x[51:50] and F2x[1, 0]9C_x52 with SeedPreGrossPass1 - //and SeedFinePass1 from the preceding steps. - - NBPtr->SetTrainDly (NBPtr, AccessPhRecDly, DIMM_BYTE_ACCESS (ChipSel >> 1, ByteLane), (SeedPreGross << 5) | SeedFine); - SeedPre[ByteLane] = (SeedPreGross << 5) | SeedFine; - - // 202688: Program seed value to RcvEnDly also. - NBPtr->SetTrainDly (NBPtr, AccessRcvEnDly, DIMM_BYTE_ACCESS (ChipSel >> 1, ByteLane), SeedGross << 5); - } - - IDS_HDT_CONSOLE_DEBUG_CODE ( - if (Pass == 1) { - IDS_HDT_CONSOLE (MEM_FLOW, "\t\t\tSeedValue: "); - for (ByteLane = 0; ByteLane < (MCTPtr->Status[SbEccDimms] ? 9 : 8); ByteLane++) { - IDS_HDT_CONSOLE (MEM_FLOW, "%03x ", SeedValue[ByteLane]); - } - IDS_HDT_CONSOLE (MEM_FLOW, "\n"); - } - IDS_HDT_CONSOLE (MEM_FLOW, "\t\t\tSeedTotal: "); - for (ByteLane = 0; ByteLane < (MCTPtr->Status[SbEccDimms] ? 9 : 8); ByteLane++) { - IDS_HDT_CONSOLE (MEM_FLOW, "%03x ", SeedTtl[ByteLane]); - } - IDS_HDT_CONSOLE (MEM_FLOW, "\n\t\t\t SeedPRE: "); - for (ByteLane = 0; ByteLane < (MCTPtr->Status[SbEccDimms] ? 9 : 8); ByteLane++) { - IDS_HDT_CONSOLE (MEM_FLOW, "%03x ", SeedPre[ByteLane]); - } - IDS_HDT_CONSOLE (MEM_FLOW, "\n"); - ); -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * Waits specified number of MEMCLKs - * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK - * @param[in] MemClkCount - Number of MEMCLKs - * - * ---------------------------------------------------------------------------- - */ -VOID -MemNWaitXMemClksNb ( - IN OUT MEM_NB_BLOCK *NBPtr, - IN UINT32 MemClkCount - ) -{ - MemUWait10ns ((MemClkCount * 100 + NBPtr->DCTPtr->Timings.Speed - 1) / NBPtr->DCTPtr->Timings.Speed, NBPtr->MemPtr); -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * Issues dummy TCB write read to zero out CL that is used for MemClr - * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK - * @param[in,out] *UnUsed - unused - * - * ---------------------------------------------------------------------------- - */ -BOOLEAN -STATIC -MemNBeforeMemClrClientNb ( - IN OUT MEM_NB_BLOCK *NBPtr, - IN VOID *UnUsed - ) -{ - UINT8 Pattern[64]; - UINT8 i; - - for (i = 0; i < 64; i++) { - Pattern[i] = 0; - } - - MemNContWritePatternClientNb (NBPtr, 0x20, Pattern, 1); - MemNContReadPatternClientNb (NBPtr, Pattern, 0x20, 1); - return TRUE; -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * This function uses the PRBS generator in the DCT to send a DDR Activate command - * - * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK - * @param[in] ChipSelect - Chip select 0-7 - * @param[in] Bank - Bank Address 0-7 - * @param[in] RowAddress - Row Address [17:0] - * - */ - -VOID -STATIC -MemNRrwActivateCmd ( - IN OUT MEM_NB_BLOCK *NBPtr, - IN UINT8 ChipSelect, - IN UINT8 Bank, - IN UINT32 RowAddress - ) -{ - // Set Chip select - MemNSetBitFieldNb (NBPtr, BFCmdChipSelect, (1 << ChipSelect)); - // Set Bank Address - MemNSetBitFieldNb (NBPtr, BFCmdBank, Bank); - // Set Row Address - MemNSetBitFieldNb (NBPtr, BFCmdAddress, RowAddress); - // Send the command - MemNSetBitFieldNb (NBPtr, BFSendActCmd, 1); - // Wait for command complete - MemNPollBitFieldNb (NBPtr, BFSendActCmd, 0, PCI_ACCESS_TIMEOUT, FALSE); - // Wait 75 MEMCLKs - NBPtr->WaitXMemClks (NBPtr, 75); -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * This function uses the PRBS generator in the DCT to send a DDR Precharge - * or Precharge All command - * - * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK - * @param[in] ChipSelect - Chip select 0-7 - * @param[in] Bank - Bank Address 0-7, PRECHARGE_ALL_BANKS = Precharge All - * - * - */ - -VOID -STATIC -MemNRrwPrechargeCmd ( - IN OUT MEM_NB_BLOCK *NBPtr, - IN UINT8 ChipSelect, - IN UINT8 Bank - ) -{ - // Wait 25 MEMCLKs - NBPtr->WaitXMemClks (NBPtr, 25); - // Set Chip select - NBPtr->SetBitField (NBPtr, BFCmdChipSelect, (1 << ChipSelect)); - if (Bank == PRECHARGE_ALL_BANKS) { - // Set Row Address, bit 10 - NBPtr->SetBitField (NBPtr, BFCmdAddress, NBPtr->GetBitField (NBPtr, BFCmdAddress) | (1 << 10) ); - } else { - // Clear Row Address, bit 10 - NBPtr->SetBitField (NBPtr, BFCmdAddress, NBPtr->GetBitField (NBPtr, BFCmdAddress) & (~(1 << 10)) ); - // Set Bank Address - NBPtr->SetBitField (NBPtr, BFCmdBank, Bank); - } - // Send the command - NBPtr->SetBitField (NBPtr, BFSendPchgCmd, 1); - // Wait for command complete - NBPtr->PollBitField (NBPtr, BFSendPchgCmd, 0, PCI_ACCESS_TIMEOUT, FALSE); - // Wait 25 MEMCLKs - NBPtr->WaitXMemClks (NBPtr, 25); -} -/* -----------------------------------------------------------------------------*/ -/** - * - * - * This function generates a continuous burst of reads for HW RcvEn - * training using the Unified Northbridge Reliable Read/Write Engine. - * - * @param[in,out] NBPtr - Pointer to the MEM_NB_BLOCK - * @param[in] Address - Unused by this function - * - */ -VOID -STATIC -MemNGenHwRcvEnReadsUnb ( - IN OUT MEM_NB_BLOCK *NBPtr, - IN UINT32 Address - ) -{ - VOID *DummyPtr; - DummyPtr = NULL; - // - // Issue Stream of Reads from the Target Rank - // - NBPtr->ReadPattern (NBPtr, DummyPtr, 0, NBPtr->TechPtr->PatternLength); -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * This function generates a continuous stream of reads from DRAM using the - * Unified Northbridge Reliable Read/Write Engine. - * - * @param[in,out] NBPtr - Pointer to the MEM_NB_BLOCK - * @param[in,out] Buffer - Unused by this function - * @param[in] Address - Unused by this function - * @param[in] ClCount - Number of cache lines to read - * - * Assumptions: - * - * - * - */ - -VOID -STATIC -MemNContReadPatternUnb ( - IN OUT MEM_NB_BLOCK *NBPtr, - IN UINT8 Buffer[], - IN UINT32 Address, - IN UINT16 ClCount - ) -{ - MEM_TECH_BLOCK *TechPtr; - RRW_SETTINGS *Rrw; - UINT8 CmdTgt; - UINT8 ChipSel; - - TechPtr = NBPtr->TechPtr; - Rrw = &NBPtr->RrwSettings; - - ChipSel = TechPtr->ChipSel; - CmdTgt = Rrw->CmdTgt; - // - // Wait for RRW Engine to be ready and turn it on - // - NBPtr->PollBitField (NBPtr, BFCmdSendInProg, 0, PCI_ACCESS_TIMEOUT, FALSE); - NBPtr->SetBitField (NBPtr, BFCmdTestEnable, 1); - // - // Depending upon the Cmd Target, send Row Activate and set Chipselect - // for the Row or Rows that will be used - // - MemNRrwActivateCmd (NBPtr, ChipSel, Rrw->TgtBankAddressA, Rrw->TgtRowAddressA); - NBPtr->SetBitField (NBPtr, BFTgtChipSelectA, ChipSel); - if (CmdTgt == CMD_TGT_AB) { - MemNRrwActivateCmd (NBPtr, ChipSel, Rrw->TgtBankAddressB, Rrw->TgtRowAddressB); - NBPtr->SetBitField (NBPtr, BFTgtChipSelectB, ChipSel); - } - // Set Comparison Masks - NBPtr->SetBitField (NBPtr, BFDramDqMaskLow, Rrw->CompareMaskLow); - NBPtr->SetBitField (NBPtr, BFDramDqMaskHigh, Rrw->CompareMaskHigh); - // - // If All Dimms are ECC Capable Test ECC. Otherwise, mask it off - // - NBPtr->SetBitField (NBPtr, BFDramEccMask, (NBPtr->MCTPtr->Status[SbEccDimms] == TRUE) ? Rrw->CompareMaskEcc : 0xFF); - // - // Program the PRBS Seed - // - NBPtr->SetBitField (NBPtr, BFDataPrbsSeed, Rrw->DataPrbsSeed); - // - // Set the Command Count - // - NBPtr->SetBitField (NBPtr, BFCmdCount, ClCount); - // - // Program the Bubble Count and CmdStreamLen - // - NBPtr->SetBitField (NBPtr, BFBubbleCnt, 0); - NBPtr->SetBitField (NBPtr, BFBubbleCnt2, 0); - NBPtr->SetBitField (NBPtr, BFCmdStreamLen, 1); - // - // Program the Starting Address - // - NBPtr->SetBitField (NBPtr, BFTgtBankA, Rrw->TgtBankAddressA); - NBPtr->SetBitField (NBPtr, BFTgtAddressA, Rrw->TgtColAddressA); - if (CmdTgt == CMD_TGT_AB) { - NBPtr->SetBitField (NBPtr, BFTgtBankB, Rrw->TgtBankAddressB); - NBPtr->SetBitField (NBPtr, BFTgtAddressB, Rrw->TgtColAddressB); - } - // - // Reset All Errors and Disable StopOnErr - // - NBPtr->SetBitField (NBPtr, BFResetAllErr, 1); - NBPtr->SetBitField (NBPtr, BFStopOnErr, 0); - // - // Program the CmdTarget - // - NBPtr->SetBitField (NBPtr, BFCmdTgt, CmdTgt); - // - // Set CmdType to read - // - NBPtr->SetBitField (NBPtr, BFCmdType, CMD_TYPE_READ); - // - // Start the Commands - // - AGESA_TESTPOINT (TpProcMemContinPatternGenRead, &(NBPtr->MemPtr->StdHeader)); - NBPtr->SetBitField (NBPtr, BFSendCmd, 1); - // - // Commands have started, wait for the reads to complete then clear the command - // - NBPtr->PollBitField (NBPtr, BFTestStatus, 1, PCI_ACCESS_TIMEOUT, FALSE); - NBPtr->PollBitField (NBPtr, BFCmdSendInProg, 0, PCI_ACCESS_TIMEOUT, FALSE); - NBPtr->SetBitField (NBPtr, BFSendCmd, 0); - // - // Send the Precharge All Command - // - MemNRrwPrechargeCmd (NBPtr, ChipSel, PRECHARGE_ALL_BANKS); - // - // Turn Off the RRW Engine - // - NBPtr->SetBitField (NBPtr, BFCmdTestEnable, 0); -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * This function generates a continuous stream of writes to DRAM using the - * Unified Northbridge Reliable Read/Write Engine. - * - * @param[in,out] NBPtr - Pointer to the MEM_NB_BLOCK - * @param[in,out] Address - Unused by this function - * @param[in] Pattern - Unused by this function - * @param[in] ClCount - Number of cache lines to write - * - */ - -VOID -STATIC -MemNContWritePatternUnb ( - IN OUT MEM_NB_BLOCK *NBPtr, - IN UINT32 Address, - IN UINT8 Pattern[], - IN UINT16 ClCount - ) -{ - MEM_TECH_BLOCK *TechPtr; - RRW_SETTINGS *Rrw; - UINT8 CmdTgt; - UINT8 ChipSel; - - TechPtr = NBPtr->TechPtr; - Rrw = &NBPtr->RrwSettings; - - ChipSel = TechPtr->ChipSel; - CmdTgt = Rrw->CmdTgt; - // - // Wait for RRW Engine to be ready and turn it on - // - NBPtr->PollBitField (NBPtr, BFCmdSendInProg, 0, PCI_ACCESS_TIMEOUT, FALSE); - NBPtr->SetBitField (NBPtr, BFCmdTestEnable, 1); - - // - // Depending upon the Cmd Target, send Row Activate and set Chipselect - // for the Row or Rows that will be used - // - MemNRrwActivateCmd (NBPtr, ChipSel, Rrw->TgtBankAddressA, Rrw->TgtRowAddressA); - NBPtr->SetBitField (NBPtr, BFTgtChipSelectA, ChipSel); - if (CmdTgt == CMD_TGT_AB) { - MemNRrwActivateCmd (NBPtr, ChipSel, Rrw->TgtBankAddressB, Rrw->TgtRowAddressB); - NBPtr->SetBitField (NBPtr, BFTgtChipSelectB, ChipSel); - } - // - // Program the PRBS Seed - // - NBPtr->SetBitField (NBPtr, BFDataPrbsSeed, Rrw->DataPrbsSeed); - // - // Set the Command Count - // - NBPtr->SetBitField (NBPtr, BFCmdCount, ClCount); - // - // Program the Bubble Count and CmdStreamLen - // - NBPtr->SetBitField (NBPtr, BFBubbleCnt, 0); - NBPtr->SetBitField (NBPtr, BFBubbleCnt2, 0); - NBPtr->SetBitField (NBPtr, BFCmdStreamLen, 1); - // - // Program the Starting Address - // - NBPtr->SetBitField (NBPtr, BFTgtBankA, Rrw->TgtBankAddressA); - NBPtr->SetBitField (NBPtr, BFTgtAddressA, Rrw->TgtColAddressA); - if (CmdTgt == CMD_TGT_AB) { - NBPtr->SetBitField (NBPtr, BFTgtBankB, Rrw->TgtBankAddressB); - NBPtr->SetBitField (NBPtr, BFTgtAddressB, Rrw->TgtColAddressB); - } - // - // Program the CmdTarget - // - NBPtr->SetBitField (NBPtr, BFCmdTgt, CmdTgt); - // - // Set CmdType to Write - // - NBPtr->SetBitField (NBPtr, BFCmdType, CMD_TYPE_WRITE); - // - // Start the Commands - // - AGESA_TESTPOINT (TpProcMemContinPatternGenWrite, &(NBPtr->MemPtr->StdHeader)); - NBPtr->SetBitField (NBPtr, BFSendCmd, 1); - // - // Commands have started, wait for the writes to complete then clear the command - // - NBPtr->PollBitField (NBPtr, BFTestStatus, 1, PCI_ACCESS_TIMEOUT, FALSE); - NBPtr->PollBitField (NBPtr, BFCmdSendInProg, 0, PCI_ACCESS_TIMEOUT, FALSE); - NBPtr->SetBitField (NBPtr, BFSendCmd, 0); - // - // Send the Precharge All Command - // - MemNRrwPrechargeCmd (NBPtr, ChipSel, PRECHARGE_ALL_BANKS); - // - // Turn Off the RRW Engine - // - NBPtr->SetBitField (NBPtr, BFCmdTestEnable, 0); -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * This function checks the Error status bits for comparison results - * - * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK - * @param[in] Buffer[] - Not used in this implementation - * @param[in] Pattern[] - Not used in this implementation - * @param[in] ByteCount - Not used in this implementation - * - * @return PASS - Bitmap of results of comparison - */ - -UINT16 -STATIC -MemNCompareTestPatternUnb ( - IN OUT MEM_NB_BLOCK *NBPtr, - IN UINT8 Buffer[], - IN UINT8 Pattern[], - IN UINT16 ByteCount - ) -{ - - - UINT16 i; - UINT16 Pass; - UINT8 ChipSel; - UINT8 ColumnCount; - UINT8* FailingBitMaskPtr; - UINT8 FailingBitMask[9]; - UINT32 NibbleErrSts; - - ChipSel = NBPtr->TechPtr->ChipSel; - ColumnCount = NBPtr->ChannelPtr->ColumnCount; - // Calculate Failing Bitmask pointer - FailingBitMaskPtr = &(NBPtr->ChannelPtr->FailingBitMask[(ColumnCount * NBPtr->TechPtr->ChipSel)]); - - // - // Get Failing bit data - // - *((UINT32*)FailingBitMask) = NBPtr->GetBitField (NBPtr, BFDQErrLow); - *((UINT32*)&FailingBitMask[4]) = NBPtr->GetBitField (NBPtr, BFDQErrHigh); - FailingBitMask[8] = (UINT8)NBPtr->GetBitField (NBPtr, BFEccErr); - - Pass = 0x0000; - // - // Get Comparison Results - Convert Nibble Masks to Byte Masks - // - NibbleErrSts = NBPtr->GetBitField (NBPtr, BFNibbleErrSts); - - for (i = 0; i < ColumnCount ; i++) { - Pass |= ((NibbleErrSts & 0x03) > 0 ) ? (1 << i) : 0; - NibbleErrSts >>= 2; - FailingBitMaskPtr[i] = FailingBitMask[i]; - } - Pass = ~Pass; - return Pass; -} - -/*-----------------------------------------------------------------------------*/ -/** - * - * This function checks the Error status bits for offset comparison results - * - * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK - * @param[in] Buffer[] - Buffer data from DRAM (Measured data from DRAM) to compare - * @param[in] Pattern[] - Pattern (Expected data in ROM/CACHE) to compare against - * @param[in] ByteCount - Byte count - * - * @retval Bitmap of results of comparison - */ -UINT16 -STATIC -MemNInsDlyCompareTestPatternUnb ( - IN OUT MEM_NB_BLOCK *NBPtr, - IN UINT8 Buffer[], - IN UINT8 Pattern[], - IN UINT16 ByteCount - ) -{ - UINT16 i; - UINT16 Pass; - UINT8 ColumnCount; - UINT32 NibbleErr180Sts; - - ColumnCount = NBPtr->ChannelPtr->ColumnCount; - Pass = 0x0000; - // - // Get Comparison Results - Convert Nibble Masks to Byte Masks - // - NibbleErr180Sts = NBPtr->GetBitField (NBPtr, BFNibbleErr180Sts); - - for (i = 0; i < ColumnCount ; i++) { - Pass |= ((NibbleErr180Sts & 0x03) > 0 ) ? (1 << i) : 0; - NibbleErr180Sts >>= 2; - } - Pass = ~Pass; - - return Pass; -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * This function assigns read/write function pointers to CPG read/write modules. - * - * @param[in,out] NBPtr - Pointer to the MEM_NB_BLOCK - * - */ -VOID -MemNInitCPGUnb ( - IN OUT MEM_NB_BLOCK *NBPtr - ) -{ - NBPtr->WritePattern = MemNContWritePatternUnb; - NBPtr->ReadPattern = MemNContReadPatternUnb; - NBPtr->GenHwRcvEnReads = MemNGenHwRcvEnReadsUnb; - NBPtr->FlushPattern = (VOID (*) (MEM_NB_BLOCK *, UINT32, UINT16)) memDefRet; - NBPtr->TrainingPatternInit = (AGESA_STATUS (*) (MEM_NB_BLOCK *)) memDefRetSuccess; - NBPtr->TrainingPatternFinalize = (AGESA_STATUS (*) (MEM_NB_BLOCK *)) memDefRetSuccess; - NBPtr->CompareTestPattern = MemNCompareTestPatternUnb; - NBPtr->InsDlyCompareTestPattern = MemNInsDlyCompareTestPatternUnb; - NBPtr->FamilySpecificHook[SetupHwTrainingEngine] = MemNSetupHwTrainingEngineUnb; - NBPtr->CPGInit = 0; -} - diff --git a/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/mnflow.c b/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/mnflow.c deleted file mode 100644 index 352f4d1c83..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/mnflow.c +++ /dev/null @@ -1,331 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * mnflow.c - * - * Common Northbridge initializer flow for MCT and DCT - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: (Mem/NB) - * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $ - * - **/ -/***************************************************************************** -* -* Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* *************************************************************************** -* -*/ - -/* - *---------------------------------------------------------------------------- - * MODULES USED - * - *---------------------------------------------------------------------------- - */ - - - -#include "AGESA.h" -#include "amdlib.h" -#include "Ids.h" -#include "OptionMemory.h" -#include "mm.h" -#include "mn.h" -#include "mt.h" -#include "Filecode.h" -CODE_GROUP (G1_PEICC) -RDATA_GROUP (G1_PEICC) - -#define FILECODE PROC_MEM_NB_MNFLOW_FILECODE -/* features */ -#include "mftds.h" - -extern MEM_PSC_FLOW_BLOCK* memPlatSpecFlowArray[]; -/*---------------------------------------------------------------------------- - * DEFINITIONS AND MACROS - * - *---------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------- - * TYPEDEFS AND STRUCTURES - * - *---------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------- - * PROTOTYPES OF LOCAL FUNCTIONS - * - *---------------------------------------------------------------------------- - */ - -BOOLEAN -STATIC -MemNInitDCTNb ( - IN OUT MEM_NB_BLOCK *NBPtr - ); - -VOID -STATIC -MemNCleanupDctRegsNb ( - IN OUT MEM_NB_BLOCK *NBPtr - ); - -VOID -STATIC -MemNGetPORFreqLimitTblDrvNb ( - IN OUT MEM_NB_BLOCK *NBPtr - ); -/*---------------------------------------------------------------------------- - * EXPORTED FUNCTIONS - * - *---------------------------------------------------------------------------- - */ - -/* -----------------------------------------------------------------------------*/ -/** - * - * - * This function programs the MCT with initial values - * - * - * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK - * - * @return TRUE - AGESA_FATAL error did not occur (it is possible to have an Error that is not AGESA_SUCCESS) - * @return FALSE - AGESA_FATAL error occurred - */ - -BOOLEAN -MemNInitMCTNb ( - IN OUT MEM_NB_BLOCK *NBPtr - ) -{ - MEM_TECH_BLOCK *TechPtr; - UINT8 Dct; - BOOLEAN Flag; - ID_INFO CallOutIdInfo; - - TechPtr = NBPtr->TechPtr; - // Switch Tech functions for Nb - NBPtr->TechBlockSwitch (NBPtr); - // Start Memory controller initialization sequence - Flag = FALSE; - if (TechPtr->DimmPresence (TechPtr)) { - AGESA_TESTPOINT (TpProcMemPlatformSpecificInit, &(NBPtr->MemPtr->StdHeader)); - if (NBPtr->MemNPlatformSpecificFormFactorInitNb (NBPtr)) { - AGESA_TESTPOINT (TpProcMemSpdTiming, &(NBPtr->MemPtr->StdHeader)); - if (TechPtr->SpdCalcWidth (TechPtr)) { - AGESA_TESTPOINT (TpProcMemSpeedTclConfig, &(NBPtr->MemPtr->StdHeader)); - if (TechPtr->SpdGetTargetSpeed (TechPtr)) { - for (Dct = 0; Dct < NBPtr->DctCount; Dct++) { - NBPtr->SwitchDCT (NBPtr, Dct); - - Flag |= MemNInitDCTNb (NBPtr); - } - - if (Flag && !NBPtr->IsSupported[TwoStageDramInit] && (NBPtr->MCTPtr->ErrCode != AGESA_FATAL)) { - MemFInitTableDrive (NBPtr, MTBeforeDInit); - AGESA_TESTPOINT (TpProcMemBeforeAgesaHookBeforeDramInit, &(NBPtr->MemPtr->StdHeader)); - CallOutIdInfo.IdField.SocketId = NBPtr->MCTPtr->SocketId; - CallOutIdInfo.IdField.ModuleId = NBPtr->MCTPtr->DieId; - IDS_HDT_CONSOLE (MEM_FLOW, "\nCalling out to Platform BIOS on Socket %d Module %d...\n", CallOutIdInfo.IdField.SocketId, CallOutIdInfo.IdField.ModuleId); - AgesaHookBeforeDramInit ((UINTN) CallOutIdInfo.IdInformation, NBPtr->MemPtr); - IDS_HDT_CONSOLE (MEM_FLOW, "\nVDDIO = 1.%dV\n", (NBPtr->RefPtr->DDR3Voltage == VOLT1_5) ? 5 : - (NBPtr->RefPtr->DDR3Voltage == VOLT1_35) ? 35 : - (NBPtr->RefPtr->DDR3Voltage == VOLT1_25) ? 25 : 999); - AGESA_TESTPOINT (TpProcMemAfterAgesaHookBeforeDramInit, &(NBPtr->MemPtr->StdHeader)); - IDS_OPTION_HOOK (IDS_BEFORE_DRAM_INIT, NBPtr, &(NBPtr->MemPtr->StdHeader)); - NBPtr->StartupDCT (NBPtr); - } - } - } - } - } - return (BOOLEAN) (NBPtr->MCTPtr->ErrCode != AGESA_FATAL); -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * - * This function initializes the platform specific block for families that support - * table driven form factor - * - * - * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK - * - * @return TRUE - AGESA_SUCCESS - */ - -BOOLEAN -MemNPlatformSpecificFormFactorInitTblDrvNb ( - IN OUT MEM_NB_BLOCK *NBPtr - ) -{ - UINT8 Dct; - - for (Dct = 0; Dct < NBPtr->DctCount; Dct++) { - NBPtr->SwitchDCT (NBPtr, Dct); - NBPtr->PsPtr->MemPDoPs = MemPPSCFlow; - NBPtr->PsPtr->MemPGetPORFreqLimit = MemNGetPORFreqLimitTblDrvNb; - } - - return TRUE; -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * This function selects appropriate Tech functions for the NB. - * - * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK - * - */ - -VOID -MemNTechBlockSwitchNb ( - IN OUT MEM_NB_BLOCK *NBPtr - ) -{ - MEM_TECH_BLOCK *TechPtr; - - TechPtr = NBPtr->TechPtr; - - // Specify Dimm-Byte training for Nb - MemTDimmByteTrainInit (TechPtr); - - // Filter included for RcvrEn training. - // note: If you'd like to drop the filter, you have to comment out these two lines together. - TechPtr->MaxFilterDly = MAX_FILTER_DLY_DDR3; - TechPtr->SaveRcvrEnDly = MemTSaveRcvrEnDlyByteFilter; -} - -/*---------------------------------------------------------------------------- - * LOCAL FUNCTIONS - * - *---------------------------------------------------------------------------- - */ - -/* -----------------------------------------------------------------------------*/ -/** - * - * - * This function programs the DCT with initial values - * - * - * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK - * - * @return TRUE - Error did not occur - * @return FALSE - Error occurred - */ - -BOOLEAN -STATIC -MemNInitDCTNb ( - IN OUT MEM_NB_BLOCK *NBPtr - ) -{ - MEM_TECH_BLOCK *TechPtr; - TechPtr = NBPtr->TechPtr; - TechPtr->SetDramMode (TechPtr); - - if (!NBPtr->MCTPtr->GangedMode || (NBPtr->MCTPtr->Dct == 0)) { - if (NBPtr->DCTPtr->Timings.DctDimmValid == 0) { - NBPtr->DisableDCT (NBPtr); - } else { - MemNCleanupDctRegsNb (NBPtr); - if (TechPtr->AutoCycTiming (TechPtr)) { - if (TechPtr->SpdSetBanks (TechPtr)) { - if (NBPtr->StitchMemory (NBPtr)) { - // if all dimms on a DCT are disabled, the DCT needs to be disabled. - if (NBPtr->DCTPtr->Timings.CsEnabled != 0) { - if (NBPtr->AutoConfig (NBPtr)) { - if (NBPtr->PlatformSpec (NBPtr)) { - return TRUE; - } - } - } else { - NBPtr->DisableDCT (NBPtr); - } - } - } - } - } - } - return FALSE; -} - -/*-----------------------------------------------------------------------------*/ -/** - * - * This function clears DCT registers - * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK - * - */ - -VOID -STATIC -MemNCleanupDctRegsNb ( - IN OUT MEM_NB_BLOCK *NBPtr - ) -{ - BIT_FIELD_NAME BitField; - - for (BitField = BFCSBaseAddr0Reg; BitField <= BFCSBaseAddr7Reg; BitField++) { - MemNSetBitFieldNb (NBPtr, BitField, 0); - } -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * - * This is function gets the POR speed limit for families supports table driven form factor - * - * - * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK - * - */ - -VOID -STATIC -MemNGetPORFreqLimitTblDrvNb ( - IN OUT MEM_NB_BLOCK *NBPtr - ) -{ - UINT8 i; - - i = 0; - while (memPlatSpecFlowArray[i] != NULL) { - if ((memPlatSpecFlowArray[i])->MaxFrequency (NBPtr, (memPlatSpecFlowArray[i])->EntryOfTables)) { - break; - } - i++; - } -} \ No newline at end of file diff --git a/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/mnmct.c b/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/mnmct.c deleted file mode 100644 index 5ace03c3e7..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/mnmct.c +++ /dev/null @@ -1,1263 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * mnmct.c - * - * Northbridge Common MCT supporting functions - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: (Mem/NB) - * @e \$Revision: 47509 $ @e \$Date: 2011-02-23 06:15:32 +0800 (Wed, 23 Feb 2011) $ - * - **/ -/***************************************************************************** -* -* Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* *************************************************************************** -* -*/ - -/* - *---------------------------------------------------------------------------- - * MODULES USED - * - *---------------------------------------------------------------------------- - */ - - - -#include "AGESA.h" -#include "amdlib.h" -#include "Ids.h" -#include "mport.h" -#include "mm.h" -#include "mn.h" -#include "mu.h" -#include "OptionMemory.h" -#include "PlatformMemoryConfiguration.h" -#include "GeneralServices.h" -#include "cpuFeatures.h" -#include "merrhdl.h" -#include "Filecode.h" -CODE_GROUP (G1_PEICC) -RDATA_GROUP (G1_PEICC) - -#define FILECODE PROC_MEM_NB_MNMCT_FILECODE -/*---------------------------------------------------------------------------- - * DEFINITIONS AND MACROS - * - *---------------------------------------------------------------------------- - */ -#define _16MB_RJ16 0x0100 - -/*---------------------------------------------------------------------------- - * TYPEDEFS AND STRUCTURES - * - *---------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------- - * PROTOTYPES OF LOCAL FUNCTIONS - * - *---------------------------------------------------------------------------- - */ -BOOLEAN -STATIC -MemNSetMTRRrangeNb ( - IN OUT MEM_NB_BLOCK *NBPtr, - IN UINT32 Base, - IN OUT UINT32 *LimitPtr, - IN UINT32 MtrrAddr, - IN UINT8 MtrrType - ); - -/*---------------------------------------------------------------------------- - * EXPORTED FUNCTIONS - * - *---------------------------------------------------------------------------- - */ -extern BUILD_OPT_CFG UserOptions; - -/* -----------------------------------------------------------------------------*/ -/** - * - * Get max frequency from OEM platform definition, from - * any user override (limiting) of max frequency, and - * from any Si Revision Specific information. Return - * the least of these three in DIE_STRUCT.Timings.TargetSpeed. - * - * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK - * - */ - -VOID -MemNSyncTargetSpeedNb ( - IN OUT MEM_NB_BLOCK *NBPtr - ) -{ - CONST UINT16 DdrMaxRateTab[] = { - UNSUPPORTED_DDR_FREQUENCY, - DDR1600_FREQUENCY, - DDR1333_FREQUENCY, - DDR1066_FREQUENCY, - DDR800_FREQUENCY, - DDR667_FREQUENCY, - DDR533_FREQUENCY, - DDR400_FREQUENCY - }; - - UINT8 Dct; - UINT8 Channel; - UINT16 MinSpeed; - UINT16 DdrMaxRate; - DCT_STRUCT *DCTPtr; - USER_MEMORY_TIMING_MODE *ChnlTmgMod; - USER_MEMORY_TIMING_MODE Mode[MAX_CHANNELS_PER_SOCKET]; - MEMORY_BUS_SPEED MemClkFreq; - MEMORY_BUS_SPEED ProposedFreq; - - ASSERT (NBPtr->DctCount <= sizeof (Mode)); - MinSpeed = 16000; - DdrMaxRate = 16000; - if (NBPtr->IsSupported[CheckMaxDramRate]) { - // Check maximum DRAM data rate that the processor is designed to support. - DdrMaxRate = DdrMaxRateTab[MemNGetBitFieldNb (NBPtr, BFDdrMaxRate)]; - NBPtr->FamilySpecificHook[GetDdrMaxRate] (NBPtr, &DdrMaxRate); - IDS_OPTION_HOOK (IDS_SKIP_FUSED_MAX_RATE, &DdrMaxRate, &NBPtr->MemPtr->StdHeader); - } - - for (Dct = 0; Dct < NBPtr->DctCount; Dct++) { - MemNSwitchDCTNb (NBPtr, Dct); - DCTPtr = NBPtr->DCTPtr; - - // Check if input user time mode is valid or not - ASSERT ((NBPtr->RefPtr->UserTimingMode == TIMING_MODE_SPECIFIC) || - (NBPtr->RefPtr->UserTimingMode == TIMING_MODE_LIMITED) || - (NBPtr->RefPtr->UserTimingMode == TIMING_MODE_AUTO)); - Mode[Dct] = NBPtr->RefPtr->UserTimingMode; - // Check if input clock value is valid or not - ASSERT ((NBPtr->ChannelPtr->TechType == DDR3_TECHNOLOGY) ? - (NBPtr->RefPtr->MemClockValue >= DDR667_FREQUENCY) : - (NBPtr->RefPtr->MemClockValue <= DDR1066_FREQUENCY)); - MemClkFreq = NBPtr->RefPtr->MemClockValue; - if (DCTPtr->Timings.DctDimmValid != 0) { - Channel = MemNGetSocketRelativeChannelNb (NBPtr, Dct, 0); - ChnlTmgMod = (USER_MEMORY_TIMING_MODE *) FindPSOverrideEntry (NBPtr->RefPtr->PlatformMemoryConfiguration, PSO_BUS_SPEED, NBPtr->MCTPtr->SocketId, Channel); - if (ChnlTmgMod != NULL) { - // Check if input user timing mode is valid or not - ASSERT ((ChnlTmgMod[0] == TIMING_MODE_SPECIFIC) || (ChnlTmgMod[0] == TIMING_MODE_LIMITED) || - (ChnlTmgMod[0] != TIMING_MODE_AUTO)); - if (ChnlTmgMod[0] != TIMING_MODE_AUTO) { - Mode[Dct] = ChnlTmgMod[0]; - // Check if input clock value is valid or not -// ASSERT ((NBPtr->ChannelPtr->TechType == DDR3_TECHNOLOGY) ? -// (ChnlTmgMod[1] >= DDR667_FREQUENCY) : -// (ChnlTmgMod[1] <= DDR1066_FREQUENCY)); - MemClkFreq = (MEMORY_BUS_SPEED) ChnlTmgMod[1]; - } - } - - ProposedFreq = UserOptions.CfgMemoryBusFrequencyLimit; - if (Mode[Dct] == TIMING_MODE_LIMITED) { - if (MemClkFreq < ProposedFreq) { - ProposedFreq = MemClkFreq; - } - } else if (Mode[Dct] == TIMING_MODE_SPECIFIC) { - ProposedFreq = MemClkFreq; - } - - if (Mode[Dct] == TIMING_MODE_SPECIFIC) { - DCTPtr->Timings.TargetSpeed = (UINT16) ProposedFreq; - } else { - // "limit" mode - if (DCTPtr->Timings.TargetSpeed > ProposedFreq) { - DCTPtr->Timings.TargetSpeed = (UINT16) ProposedFreq; - } - } - - NBPtr->MemNCapSpeedBatteryLife (NBPtr); - - if (DCTPtr->Timings.TargetSpeed > DdrMaxRate) { - if (Mode[Dct] == TIMING_MODE_SPECIFIC) { - PutEventLog (AGESA_ALERT, MEM_ALERT_USER_TMG_MODE_OVERRULED, NBPtr->Node, NBPtr->Dct, NBPtr->Channel, 0, &NBPtr->MemPtr->StdHeader); - SetMemError (AGESA_ALERT, NBPtr->MCTPtr); - } - DCTPtr->Timings.TargetSpeed = DdrMaxRate; - } - - IDS_SKIP_HOOK (IDS_POR_MEM_FREQ, NBPtr, &NBPtr->MemPtr->StdHeader) { - // - //Call Platform POR Frequency Override - // - if (!MemProcessConditionalOverrides (NBPtr->RefPtr->PlatformMemoryConfiguration, NBPtr, PSO_ACTION_SPEEDLIMIT, ALL_DIMMS)) { - // - // Get the POR frequency limit - // - NBPtr->PsPtr->MemPGetPORFreqLimit (NBPtr); - } - } - - if (MinSpeed > DCTPtr->Timings.TargetSpeed) { - MinSpeed = DCTPtr->Timings.TargetSpeed; - } - } - } - - if (MinSpeed == DDR667_FREQUENCY) { - NBPtr->StartupSpeed = DDR667_FREQUENCY; - } - - // Sync all DCTs to the same speed - for (Dct = 0; Dct < NBPtr->DctCount; Dct++) { - MemNSwitchDCTNb (NBPtr, Dct); - NBPtr->DCTPtr->Timings.TargetSpeed = MinSpeed; - } -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * - * This function waits for all DCTs to be ready - * - * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK - * - * @return TRUE - No fatal error occurs. - * @return FALSE - Fatal error occurs. - */ - -BOOLEAN -MemNSyncDctsReadyNb ( - IN OUT MEM_NB_BLOCK *NBPtr - ) -{ - if (NBPtr->MCTPtr->DimmValid) { - MemNPollBitFieldNb (NBPtr, BFDramEnabled, 1, PCI_ACCESS_TIMEOUT, FALSE); - // Re-enable phy compensation engine after Dram init has completed - MemNSwitchDCTNb (NBPtr, 0); - MemNSetBitFieldNb (NBPtr, BFDisAutoComp, 0); - } - // Wait 750 us for the phy compensation engine to reinitialize. - MemUWait10ns (75000, NBPtr->MemPtr); - - MemNSyncAddrMapToAllNodesNb (NBPtr); - return (BOOLEAN) (NBPtr->MCTPtr->ErrCode < AGESA_FATAL); -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * - * This function create the HT memory map - * - * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK - * - * @return TRUE - No fatal error occurs. - * @return FALSE - Fatal error occurs. - */ - -BOOLEAN -MemNHtMemMapInitNb ( - IN OUT MEM_NB_BLOCK *NBPtr - ) -{ - UINT32 BottomIo; - UINT32 HoleOffset; - UINT32 DctSelBaseAddr; - UINT32 NodeSysBase; - UINT32 NodeSysLimit; - MEM_PARAMETER_STRUCT *RefPtr; - DIE_STRUCT *MCTPtr; - - RefPtr = NBPtr->RefPtr; - MCTPtr = NBPtr->MCTPtr; - // - // Physical addresses in this function are right adjusted by 16 bits ([47:16]) - // They are BottomIO, HoleOffset, DctSelBaseAddr, NodeSysBase, NodeSysLimit. - // - - // Enforce bottom of IO be be 128MB aligned - ASSERT ((RefPtr->BottomIo < (_4GB_RJ16 >> 8)) && (RefPtr->BottomIo != 0)); - BottomIo = (RefPtr->BottomIo & 0xF8) << 8; - - if (!MCTPtr->GangedMode) { - DctSelBaseAddr = MCTPtr->DctData[0].Timings.DctMemSize; - } else { - DctSelBaseAddr = 0; - } - - if (MCTPtr->NodeMemSize) { - NodeSysBase = NBPtr->SharedPtr->CurrentNodeSysBase; - NodeSysLimit = NodeSysBase + MCTPtr->NodeMemSize - 1; - DctSelBaseAddr += NodeSysBase; - - if ((NBPtr->IsSupported[ForceEnMemHoleRemapping]) || (RefPtr->MemHoleRemapping)) { - if ((NodeSysBase < BottomIo) && (NodeSysLimit >= BottomIo)) { - // HW Dram Remap - MCTPtr->Status[SbHWHole] = TRUE; - RefPtr->GStatus[GsbHWHole] = TRUE; - MCTPtr->NodeHoleBase = BottomIo; - RefPtr->HoleBase = BottomIo; - - HoleOffset = _4GB_RJ16 - BottomIo; - - NodeSysLimit += HoleOffset; - - if ((DctSelBaseAddr > 0) && (DctSelBaseAddr < BottomIo)) { - HoleOffset += DctSelBaseAddr; - } else { - if (DctSelBaseAddr >= BottomIo) { - DctSelBaseAddr += HoleOffset; - } - HoleOffset += NodeSysBase; - } - - MemNSetBitFieldNb (NBPtr, BFDramHoleBase, BottomIo >> 8); - MemNSetBitFieldNb (NBPtr, BFDramHoleOffset, HoleOffset >> 7); - MemNSetBitFieldNb (NBPtr, BFDramHoleValid, 1); - - } else if (NodeSysBase == BottomIo) { - // SW Node Hoist - MCTPtr->Status[SbSWNodeHole] = TRUE; - RefPtr->GStatus[GsbSpIntRemapHole] = TRUE; - RefPtr->GStatus[GsbSoftHole] = TRUE; - - RefPtr->HoleBase = NodeSysBase; - DctSelBaseAddr = _4GB_RJ16 + (DctSelBaseAddr - NodeSysBase); - NodeSysLimit = _4GB_RJ16 + (NodeSysLimit - NodeSysBase); - NodeSysBase = _4GB_RJ16; - - } else if ((NodeSysBase < HT_REGION_BASE_RJ16) && (NodeSysLimit >= HT_REGION_BASE_RJ16)) { - if (!NBPtr->SharedPtr->UndoHoistingAbove1TB) { - // SW Hoisting above 1TB to avoid HT Reserved region - DctSelBaseAddr = _1TB_RJ16 + (DctSelBaseAddr - NodeSysBase); - NodeSysLimit = _1TB_RJ16 + (NodeSysLimit - NodeSysBase); - NodeSysBase = _1TB_RJ16; - - if (RefPtr->LimitMemoryToBelow1Tb) { - // Flag to undo 1TB hoisting after training - NBPtr->SharedPtr->UndoHoistingAbove1TB = TRUE; - } - } - - } else { - // No Remapping. Normal Contiguous mapping - } - } else { - // No Remapping. Normal Contiguous mapping - } - - if (NBPtr->IsSupported[Check1GAlign]) { - if (UserOptions.CfgNodeMem1GBAlign) { - NBPtr->MemPNodeMemBoundaryNb (NBPtr, (UINT32 *)&NodeSysLimit); - } - } - - MCTPtr->NodeSysBase = NodeSysBase; - MCTPtr->NodeSysLimit = NodeSysLimit; - RefPtr->SysLimit = NodeSysLimit; - RefPtr->Sub1THoleBase = (NodeSysLimit < HT_REGION_BASE_RJ16) ? (NodeSysLimit + 1) : RefPtr->Sub1THoleBase; - IDS_OPTION_HOOK (IDS_MEM_SIZE_OVERLAY, NBPtr, &NBPtr->MemPtr->StdHeader); - - NBPtr->SharedPtr->TopNode = NBPtr->Node; - - NBPtr->SharedPtr->NodeMap[NBPtr->Node].IsValid = TRUE; - NBPtr->SharedPtr->NodeMap[NBPtr->Node].SysBase = NodeSysBase; - NBPtr->SharedPtr->NodeMap[NBPtr->Node].SysLimit = NodeSysLimit & 0xFFFFFF00; - - MemNSetBitFieldNb (NBPtr, BFDramBaseAddr, NodeSysBase >> (27 - 16)); - MemNSetBitFieldNb (NBPtr, BFDramLimitAddr, NodeSysLimit >> (27 - 16)); - - if ((MCTPtr->DctData[1].Timings.DctMemSize != 0) && (!NBPtr->Ganged)) { - MemNSetBitFieldNb (NBPtr, BFDctSelBaseAddr, DctSelBaseAddr >> 11); - MemNSetBitFieldNb (NBPtr, BFDctSelHiRngEn, 1); - MemNSetBitFieldNb (NBPtr, BFDctSelHi, 1); - MemNSetBitFieldNb (NBPtr, BFDctSelBaseOffset, DctSelBaseAddr >> 10); - } - - NBPtr->SharedPtr->CurrentNodeSysBase = (NodeSysLimit + 1) & 0xFFFFFFF0; - } - return (BOOLEAN) (MCTPtr->ErrCode < AGESA_FATAL); -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * - * Program system DRAM map to this node - * - * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK - * - */ - -VOID -MemNSyncAddrMapToAllNodesNb ( - IN OUT MEM_NB_BLOCK *NBPtr - ) -{ - UINT8 Node; - UINT32 NodeSysBase; - UINT32 NodeSysLimit; - UINT8 WeReMask; - MEM_PARAMETER_STRUCT *RefPtr; - - RefPtr = NBPtr->RefPtr; - for (Node = 0; Node < NBPtr->NodeCount; Node++) { - NodeSysBase = NBPtr->SharedPtr->NodeMap[Node].SysBase; - NodeSysLimit = NBPtr->SharedPtr->NodeMap[Node].SysLimit; - if (NBPtr->SharedPtr->NodeMap[Node].IsValid) { - WeReMask = 3; - } else { - WeReMask = 0; - } - // Set the Dram base and set the WE and RE flags in the base. - MemNSetBitFieldNb (NBPtr, BFDramBaseReg0 + Node, (NodeSysBase << 8) | WeReMask); - MemNSetBitFieldNb (NBPtr, BFDramBaseHiReg0 + Node, NodeSysBase >> 24); - // Set the Dram limit and set DstNode. - MemNSetBitFieldNb (NBPtr, BFDramLimitReg0 + Node, (NodeSysLimit << 8) | Node); - MemNSetBitFieldNb (NBPtr, BFDramLimitHiReg0 + Node, NodeSysLimit >> 24); - - if (RefPtr->GStatus[GsbHWHole]) { - MemNSetBitFieldNb (NBPtr, BFDramMemHoistValid, 1); - MemNSetBitFieldNb (NBPtr, BFDramHoleBase, (RefPtr->HoleBase >> 8)); - } - } - - NBPtr->FamilySpecificHook[InitExtMMIOAddr] (NBPtr, NULL); -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * - * This function enables power down mode - * - * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK - * - */ - -VOID -MemNPowerDownCtlNb ( - IN OUT MEM_NB_BLOCK *NBPtr - ) -{ - MEM_PARAMETER_STRUCT *RefPtr; - UINT8 PowerDownMode; - - RefPtr = NBPtr->RefPtr; - - // we can't enable powerdown mode when doing WL - if (RefPtr->EnablePowerDown) { - MemNSetBitFieldNb (NBPtr, BFPowerDownEn, 1); - PowerDownMode = (UINT8) ((UserOptions.CfgPowerDownMode == POWER_DOWN_MODE_AUTO) ? POWER_DOWN_BY_CHANNEL : UserOptions.CfgPowerDownMode); - IDS_OPTION_HOOK (IDS_POWERDOWN_MODE, &PowerDownMode, &(NBPtr->MemPtr->StdHeader)); - if (PowerDownMode) { - MemNSetBitFieldNb (NBPtr, BFPowerDownMode, 1); - } - } -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * - * This function gets the Optimal Critical Gross Delay Difference between - * the delay parameters across all Dimms on each bytelane. Then takes the - * largest of all the bytelanes. - * - * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK - * @param[in] TrnDly1 - Type of first Gross Delay parameter - * @param[in] TrnDly2 - Type of second Gross Delay parameter - * - * @return The largest difference between the largest and smallest - * of the two Gross delay types within a single bytelane - */ -INT8 -MemNGetOptimalCGDDNb ( - IN OUT MEM_NB_BLOCK *NBPtr, - IN TRN_DLY_TYPE TrnDly1, - IN TRN_DLY_TYPE TrnDly2 - ) -{ - INT8 CGDD; - INT8 GDD; - UINT8 Dimm1; - UINT8 Dimm2; - UINT8 ByteLane; - UINT16 CsEnabled; - BOOLEAN CGDDInit; - BOOLEAN SameDelayType; - - CGDD = 0; - CGDDInit = FALSE; - SameDelayType = (BOOLEAN) (TrnDly1 == TrnDly2); - CsEnabled = NBPtr->DCTPtr->Timings.CsEnabled; - - // If the two delay types compared are the same type, then no need to compare the same - // pair twice. Adjustments are made in the upper bound and lower bound of the loop to - // handle this. - for (Dimm1 = 0; Dimm1 < (SameDelayType ? (MAX_DIMMS_PER_CHANNEL - 1) : MAX_DIMMS_PER_CHANNEL); Dimm1 ++) { - if (CsEnabled & (UINT16) (3 << (Dimm1 << 1))) { - for (Dimm2 = (SameDelayType ? (Dimm1 + 1) : 0); Dimm2 < MAX_DIMMS_PER_CHANNEL; Dimm2 ++) { - if ((CsEnabled & (UINT16) (3 << (Dimm2 << 1)))) { - for (ByteLane = 0 ; ByteLane < 8 ; ByteLane++) { - // check each byte lane delay pair - GDD = (UINT8) (NBPtr->GetTrainDly (NBPtr, TrnDly1, DIMM_BYTE_ACCESS (Dimm1, ByteLane)) >> 5) - - (UINT8) (NBPtr->GetTrainDly (NBPtr, TrnDly2, DIMM_BYTE_ACCESS (Dimm2, ByteLane)) >> 5); - // If the 2 delay types to be compared are the same, then keep the absolute difference - if (SameDelayType && (GDD < 0)) { - GDD = (-GDD); - } - - // If CGDD is yet to be initialized, initialize it - // Otherwise, keep the largest difference so far - CGDD = (!CGDDInit) ? GDD : ((CGDD > GDD) ? CGDD : GDD); - if (!CGDDInit) { - CGDDInit = TRUE; - } - } - } - } - } - } - return CGDD; -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * This function calculates the critical delay difference (CDD) - * - * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK - * @param[in] TrnDlyType1 - Type of first Gross Delay parameter - * @param[in] TrnDlyType2 - Type of second Gross Delay parameter - * @param[in] SameDimm - CDD of same DIMMs - * @param[in] DiffDimm - CDD of different DIMMs - * - * @return CDD term - in 1/2 MEMCLK - */ -INT16 -MemNCalcCDDNb ( - IN OUT MEM_NB_BLOCK *NBPtr, - IN TRN_DLY_TYPE TrnDlyType1, - IN TRN_DLY_TYPE TrnDlyType2, - IN BOOLEAN SameDimm, - IN BOOLEAN DiffDimm - ) -{ - INT16 CDD; - INT16 CDDtemp; - UINT16 TrnDly1; - UINT16 TrnDly2; - UINT8 i; - UINT8 j; - UINT8 ByteLane; - UINT16 CsEnabled; - BOOLEAN SameDlyType; - - SameDlyType = (BOOLEAN) (TrnDlyType1 == TrnDlyType2); - CsEnabled = NBPtr->DCTPtr->Timings.CsEnabled; - CDD = -32000; - // If the two delay types compared are the same type, then no need to compare the same - // pair twice. Adjustments are made in the upper bound and lower bound of the loop to - // handle this. - for (i = 0; i < (SameDlyType ? (MAX_DIMMS_PER_CHANNEL - 1) : MAX_DIMMS_PER_CHANNEL); i++) { - if ((CsEnabled & (UINT16) (3 << (i << 1))) != 0) { - for (j = SameDlyType ? (i + 1) : 0; j < MAX_DIMMS_PER_CHANNEL; j++) { - if (((CsEnabled & (UINT16) (3 << (j << 1))) != 0) && ((SameDimm && (i == j)) || (DiffDimm && (i != j)))) { - for (ByteLane = 0; ByteLane < ((NBPtr->MCTPtr->Status[SbEccDimms] && NBPtr->IsSupported[EccByteTraining]) ? 9 : 8); ByteLane++) { - /// @todo: Gross delay mask should not be constant. - TrnDly1 = GetTrainDlyFromHeapNb (NBPtr, TrnDlyType1, DIMM_BYTE_ACCESS (i, ByteLane)) >> 5; // Gross delay only - TrnDly2 = GetTrainDlyFromHeapNb (NBPtr, TrnDlyType2, DIMM_BYTE_ACCESS (j, ByteLane)) >> 5; // Gross delay only - - CDDtemp = TrnDly1 - TrnDly2; - // If the 2 delay types to be compared are the same, then keep the absolute difference - if ((SameDlyType) && (CDDtemp < 0)) { - CDDtemp = (-CDDtemp); - } - - CDD = (CDD < CDDtemp) ? CDDtemp : CDD; - } - } - } - } - } - - return CDD; -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * - * This function gets DQS timing from data saved in heap. - * - * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK - * @param[in] TrnDlyType - type of delay to be set - * @param[in] Drbn - encoding of Dimm-Rank-Byte-Nibble to be accessed - * (use either DIMM_BYTE_ACCESS(dimm,byte) or CS_NBBL_ACCESS(cs,nibble) to use this encoding - * - * @return value of the target timing. - */ -UINT16 -GetTrainDlyFromHeapNb ( - IN OUT MEM_NB_BLOCK *NBPtr, - IN TRN_DLY_TYPE TrnDlyType, - IN DRBN Drbn - ) -{ - UINT8 Dimm; - UINT8 Byte; - UINT16 TrainDly; - CH_DEF_STRUCT *ChannelPtr; - MEM_TECH_BLOCK *TechPtr; - - Dimm = DRBN_DIMM (Drbn); - Byte = DRBN_BYTE (Drbn); - ChannelPtr = NBPtr->ChannelPtr; - TechPtr = NBPtr->TechPtr; - - ASSERT (Dimm < 4); - ASSERT (Byte <= ECC_DLY); - - switch (TrnDlyType) { - case AccessRcvEnDly: - TrainDly = ChannelPtr->RcvEnDlys[Dimm * TechPtr->DlyTableWidth () + Byte]; - break; - case AccessWrDqsDly: - TrainDly = ChannelPtr->WrDqsDlys[Dimm * TechPtr->DlyTableWidth () + Byte]; - break; - case AccessWrDatDly: - TrainDly = ChannelPtr->WrDatDlys[Dimm * TechPtr->DlyTableWidth () + Byte]; - break; - case AccessRdDqsDly: - TrainDly = ChannelPtr->RdDqsDlys[Dimm * TechPtr->DlyTableWidth () + Byte]; - break; - default: - TrainDly = 0; - IDS_ERROR_TRAP; - } - - return TrainDly; -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * - * This function sets the fixed MTRRs for common legacy ranges. - * It sets TOP_MEM and TOM2 and some variable MTRRs with WB Uncacheable type. - * - * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK - * - * @return TRUE - An Error value lower than AGESA_FATAL may have occurred - * @return FALSE - An Error value greater than or equal to AGESA_FATAL may have occurred - */ - -BOOLEAN -MemNCPUMemTypingNb ( - IN OUT MEM_NB_BLOCK *NBPtr - ) -{ - UINT32 Bottom32bIO; - UINT32 Bottom40bIO; - UINT32 Cache32bTOP; - S_UINT64 SMsr; - - MEM_DATA_STRUCT *MemPtr; - MEM_PARAMETER_STRUCT *RefPtr; - RefPtr = NBPtr->RefPtr; - MemPtr = NBPtr->MemPtr; - - // - //====================================================================== - // Set temporary top of memory from Node structure data. - // Adjust temp top of memory down to accommodate 32-bit IO space. - //====================================================================== - //Bottom40bIO=top of memory, right justified 16 bits (defines dram versus IO space type) - //Bottom32bIO=sub 4GB top of memory, right justified 16 bits (defines dram versus IO space type) - //Cache32bTOP=sub 4GB top of WB cacheable memory, right justified 16 bits - // - if (RefPtr->HoleBase != 0) { - Bottom32bIO = RefPtr->HoleBase; - } else if (RefPtr->BottomIo != 0) { - Bottom32bIO = (UINT32)RefPtr->BottomIo << (24 - 16); - } else { - Bottom32bIO = (UINT32)1 << (24 - 16); - } - - Cache32bTOP = RefPtr->SysLimit + 1; - if (Cache32bTOP < _4GB_RJ16) { - Bottom40bIO = 0; - if (Bottom32bIO >= Cache32bTOP) { - Bottom32bIO = Cache32bTOP; - } - } else { - Bottom40bIO = Cache32bTOP; - } - - Cache32bTOP = Bottom32bIO; - - - // - //====================================================================== - // Set default values for CPU registers - //====================================================================== - // - LibAmdMsrRead (SYS_CFG, (UINT64 *)&SMsr, &MemPtr->StdHeader); - SMsr.lo |= 0x1C0000; // turn on modification enable bit and - // mtrr enable bits - LibAmdMsrWrite (SYS_CFG, (UINT64 *)&SMsr, &MemPtr->StdHeader); - - SMsr.lo = SMsr.hi = 0x1E1E1E1E; - LibAmdMsrWrite (0x250, (UINT64 *)&SMsr, &MemPtr->StdHeader); // 0 - 512K = WB Mem - LibAmdMsrWrite (0x258, (UINT64 *)&SMsr, &MemPtr->StdHeader); // 512K - 640K = WB Mem - - // - //====================================================================== - // Set variable MTRR values - //====================================================================== - // - MemNSetMTRRrangeNb (NBPtr, 0, &Cache32bTOP, 0x200, 6); - - RefPtr->Sub4GCacheTop = Cache32bTOP << 16; - - // - //====================================================================== - // Set TOP_MEM and TOM2 CPU registers - //====================================================================== - // - SMsr.hi = Bottom32bIO >> (32 - 16); - SMsr.lo = Bottom32bIO << 16; - LibAmdMsrWrite (TOP_MEM, (UINT64 *)&SMsr, &MemPtr->StdHeader); - IDS_HDT_CONSOLE (MEM_FLOW, "TOP_MEM: %08x0000\n", Bottom32bIO); - - if (Bottom40bIO) { - SMsr.hi = Bottom40bIO >> (32 - 16); - SMsr.lo = Bottom40bIO << 16; - } else { - SMsr.hi = 0; - SMsr.lo = 0; - } - LibAmdMsrWrite (TOP_MEM2, (UINT64 *)&SMsr, &MemPtr->StdHeader); - - LibAmdMsrRead (SYS_CFG, (UINT64 *)&SMsr, &MemPtr->StdHeader); - if (Bottom40bIO) { - IDS_HDT_CONSOLE (MEM_FLOW, "TOP_MEM2: %08x0000\n", Bottom40bIO); - IDS_HDT_CONSOLE (MEM_FLOW, "Sub1THoleBase: %08x0000\n", RefPtr->Sub1THoleBase); - // Enable TOM2 - SMsr.lo |= 0x00600000; - } else { - // Disable TOM2 - SMsr.lo &= ~0x00600000; - } - SMsr.lo &= 0xFFF7FFFF; // turn off modification enable bit - LibAmdMsrWrite (SYS_CFG, (UINT64 *)&SMsr, &MemPtr->StdHeader); - - return (BOOLEAN) (NBPtr->MCTPtr->ErrCode < AGESA_FATAL); -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * - * This function runs on the BSP only, it sets the fixed MTRRs for common legacy ranges. - * It sets TOP_MEM and TOM2 and some variable MTRRs with WB Uncacheable type. - * - * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK - * - */ - -VOID -MemNUMAMemTypingNb ( - IN OUT MEM_NB_BLOCK *NBPtr - ) -{ - UINT32 Bottom32bIO; - UINT32 Bottom32bUMA; - UINT32 Cache32bTOP; - UINT32 Value32; - UINT8 BitCount; - UINT8 i; - - MEM_PARAMETER_STRUCT *RefPtr; - RefPtr = NBPtr->RefPtr; - BitCount = 0; - // - //====================================================================== - // Adjust temp top of memory down to accommodate UMA memory start - //====================================================================== - // Bottom32bIO=sub 4GB top of memory, right justified 16 bits (defines dram versus IO space type) - // Cache32bTOP=sub 4GB top of WB cacheable memory, right justified 16 bits - // - Bottom32bIO = RefPtr->Sub4GCacheTop >> 16; - Bottom32bUMA = RefPtr->UmaBase; - - if (Bottom32bUMA < Bottom32bIO) { - Cache32bTOP = Bottom32bUMA; - RefPtr->Sub4GCacheTop = Bottom32bUMA << 16; - // - //====================================================================== - //Set variable MTRR values - //====================================================================== - // - Value32 = Cache32bTOP; - //Pre-check the bit count of bottom Uma to see if it is potentially running out of Mtrr while typing. - while (Value32 != 0) { - i = LibAmdBitScanForward (Value32); - Value32 &= ~ (1 << i); - BitCount++; - } - - if (BitCount > 5) { - NBPtr->RefPtr->GStatus[GsbMTRRshort] = TRUE; - MemNSetMTRRUmaRegionUCNb (NBPtr, &Cache32bTOP, &Bottom32bIO); - } else { - MemNSetMTRRrangeNb (NBPtr, 0, &Cache32bTOP, 0x200, 6); - } - } -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * - * Program MTRRs to describe given range as given cache type. Use MTRR pairs - * starting with the given MTRRphys Base address, and use as many as is - * required up to (excluding) MSR 020C, which is reserved for OS. - * - * "Limit" in the context of this procedure is not the numerically correct - * limit, but rather the Last address+1, for purposes of coding efficiency - * and readability. Size of a region is then Limit-Base. - * - * 1. Size of each range must be a power of two - * 2. Each range must be naturally aligned (Base is same as size) - * - * There are two code paths: the ascending path and descending path (analogous - * to bsf and bsr), where the next limit is a function of the next set bit in - * a forward or backward sequence of bits (as a function of the Limit). We - * start with the ascending path, to ensure that regions are naturally aligned, - * then we switch to the descending path to maximize MTRR usage efficiency. - * Base=0 is a special case where we start with the descending path. - * Correct Mask for region is 2comp(Size-1)-1, - * which is 2comp(Limit-Base-1)-1 * - * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK - * @param[in] Base - Base address[47:16] of specified range. - * @param[in] *LimitPtr - Limit address[47:16] of specified range. - * @param[in] MtrrAddr - address of var MTRR pair to start using. - * @param[in] MtrrType - Cache type for the range. - * - * @return TRUE - No failure occurred - * @return FALSE - Failure occurred because run out of variable-size MTRRs before completion. - */ - -BOOLEAN -STATIC -MemNSetMTRRrangeNb ( - IN OUT MEM_NB_BLOCK *NBPtr, - IN UINT32 Base, - IN OUT UINT32 *LimitPtr, - IN UINT32 MtrrAddr, - IN UINT8 MtrrType - ) -{ - S_UINT64 SMsr; - UINT32 CurBase; - UINT32 CurLimit; - UINT32 CurSize; - UINT32 CurAddr; - UINT32 Value32; - - CurBase = Base; - CurLimit = *LimitPtr; - CurAddr = MtrrAddr; - - while ((CurAddr >= 0x200) && (CurAddr < 0x20A) && (CurBase < *LimitPtr)) { - CurSize = CurLimit = (UINT32)1 << LibAmdBitScanForward (CurBase); - CurLimit += CurBase; - if ((CurBase == 0) || (*LimitPtr < CurLimit)) { - CurLimit = *LimitPtr - CurBase; - CurSize = CurLimit = (UINT32)1 << LibAmdBitScanReverse (CurLimit); - CurLimit += CurBase; - } - - // prog. MTRR with current region Base - SMsr.lo = (CurBase << 16) | (UINT32)MtrrType; - SMsr.hi = CurBase >> (32 - 16); - LibAmdMsrWrite (CurAddr, (UINT64 *)&SMsr, &NBPtr->MemPtr->StdHeader); - - // prog. MTRR with current region Mask - CurAddr++; // other half of MSR pair - Value32 = CurSize - (UINT32)1; - Value32 = ~Value32; - SMsr.hi = (Value32 >> (32 - 16)) & NBPtr->VarMtrrHiMsk; - SMsr.lo = (Value32 << 16) | ((UINT32)1 << MTRR_VALID); - LibAmdMsrWrite (CurAddr, (UINT64 *)&SMsr, &NBPtr->MemPtr->StdHeader); - - CurBase = CurLimit; - CurAddr++; // next MSR pair - } - - if (CurLimit < *LimitPtr) { - // Announce failure - *LimitPtr = CurLimit; - IDS_ERROR_TRAP; - } - - while ((CurAddr >= 0x200) && (CurAddr < 0x20C)) { - SMsr.lo = SMsr.hi = 0; - LibAmdMsrWrite (CurAddr, (UINT64 *)&SMsr, &NBPtr->MemPtr->StdHeader); - CurAddr++; - } - - return TRUE; -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * - * Program one MTRR to describe Uma region as UC cache type if we detect running out of - * Mtrr circumstance. - * - * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK - * @param[in] *BasePtr - Base address[47:24] of specified range. - * @param[in] *LimitPtr - Limit address[47:24] of specified range. - * - * @return TRUE - No fatal error occurs. - * @return FALSE - Fatal error occurs. - */ -BOOLEAN -MemNSetMTRRUmaRegionUCNb ( - IN OUT MEM_NB_BLOCK *NBPtr, - IN UINT32 *BasePtr, - IN OUT UINT32 *LimitPtr - ) -{ - S_UINT64 SMsr; - UINT32 Mtrr; - UINT32 Size; - UINT32 Value32; - - Size = *LimitPtr - *BasePtr; - // Check if Size is a power of 2 - if ((Size & (Size - 1)) != 0) { - for (Mtrr = 0x200; Mtrr < 0x20A; Mtrr += 2) { - LibAmdMsrRead (Mtrr + 1, (UINT64 *)&SMsr, &NBPtr->MemPtr->StdHeader); - if ((SMsr.lo & ((UINT32) 1 << 11)) == 0) { - MemNSetMTRRrangeNb (NBPtr, *BasePtr, LimitPtr, Mtrr, 0); - break; - } - } - if (Mtrr == 0x20A) { - // Run out of MTRRs - IDS_ERROR_TRAP; - } - } else { - Mtrr = 0x20A; //Reserved pair of MTRR for UMA region. - - // prog. MTRR with current region Base - SMsr.lo = *BasePtr << 16; - SMsr.hi = *BasePtr >> (32 - 16); - LibAmdMsrWrite (Mtrr, (UINT64 *)&SMsr, &NBPtr->MemPtr->StdHeader); - - // prog. MTRR with current region Mask - Mtrr++; // other half of MSR pair - Value32 = Size - (UINT32)1; - Value32 = ~Value32; - SMsr.hi = (Value32 >> (32 - 16)) & NBPtr->VarMtrrHiMsk; - SMsr.lo = (Value32 << 16) | ((UINT32)1 << MTRR_VALID); - LibAmdMsrWrite (Mtrr, (UINT64 *)&SMsr, &NBPtr->MemPtr->StdHeader); - } - - return TRUE; -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * - * Report the Uma size that is going to be allocated. - * - * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK - * - * @return Uma size [31:0] = Addr [47:16] - */ -UINT32 -MemNGetUmaSizeNb ( - IN OUT MEM_NB_BLOCK *NBPtr - ) -{ - return 0; -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * This function allocates 16MB of memory for C6 storage when it is requested to be enabled - * - * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK - * - */ -VOID -MemNAllocateC6StorageClientNb ( - IN OUT MEM_NB_BLOCK *NBPtr - ) -{ - UINT32 SysLimit; - - if (IsFeatureEnabled (C6Cstate, NBPtr->MemPtr->PlatFormConfig, &(NBPtr->MemPtr->StdHeader))) { - SysLimit = NBPtr->RefPtr->SysLimit; - SysLimit -= _16MB_RJ16; - - // Set Dram Limit - NBPtr->MCTPtr->NodeSysLimit = SysLimit; - NBPtr->RefPtr->SysLimit = SysLimit; - MemNSetBitFieldNb (NBPtr, BFDramLimitReg0, ((SysLimit << 8) & 0xFFFF0000)); - - // Set TOPMEM and MTRRs - MemNC6AdjustMSRs (NBPtr); - - // Set C6Base - MemNSetBitFieldNb (NBPtr, BFC6Base, (SysLimit + 1) >> (24 - 16)); - - // C6DramLock will be set in FinalizeMCT - } -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * This function allocates 16MB of memory for C6 storage when it is requested to be enabled - * - * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK - * - */ -VOID -MemNAllocateC6StorageUnb ( - IN OUT MEM_NB_BLOCK *NBPtr - ) -{ - UINT8 Node; - UINT32 SysLimit; - UINT32 DramLimitReg; - - if (NBPtr->SharedPtr->C6Enabled || IsFeatureEnabled (C6Cstate, NBPtr->MemPtr->PlatFormConfig, &(NBPtr->MemPtr->StdHeader))) { - - SysLimit = NBPtr->RefPtr->SysLimit; - - // Calculate new SysLimit - if (!NBPtr->SharedPtr->C6Enabled) { - if (NBPtr->SharedPtr->NodeIntlv.NodeCnt >= 2) { - // Node Interleave is enabled, system memory available is reduced by 16MB * number of nodes - SysLimit -= _16MB_RJ16 * NBPtr->SharedPtr->NodeIntlv.NodeCnt; - } else { - // Otherwise, system memory available is reduced by 16MB - SysLimit -= _16MB_RJ16; - } - NBPtr->RefPtr->SysLimit = SysLimit; - NBPtr->SharedPtr->C6Enabled = TRUE; - - // Set TOPMEM and MTRRs (only need to be done once for BSC) - MemNC6AdjustMSRs (NBPtr); - } - - // Set Dram Limit - if (NBPtr->SharedPtr->NodeIntlv.NodeCnt >= 2) { - for (Node = 0; Node < NBPtr->NodeCount; Node++) { - DramLimitReg = MemNGetBitFieldNb (NBPtr, BFDramLimitReg0 + Node); - if ((DramLimitReg & 0xFFFF0000) != 0) { - MemNSetBitFieldNb (NBPtr, BFDramLimitReg0 + Node, ((SysLimit << 8) & 0xFFFF0000) | (DramLimitReg & 0xFFFF)); - MemNSetBitFieldNb (NBPtr, BFDramLimitHiReg0 + Node, SysLimit >> 24); - } - } - // Node Interleave is enabled, CoreStateSaveDestNode points to its own node - MemNSetBitFieldNb (NBPtr, BFCoreStateSaveDestNode, NBPtr->Node); - NBPtr->MCTPtr->NodeSysLimit = SysLimit; - } else { - DramLimitReg = MemNGetBitFieldNb (NBPtr, BFDramLimitReg0 + NBPtr->SharedPtr->TopNode) & 0x0000FFFF; - MemNSetBitFieldNb (NBPtr, BFDramLimitReg0 + NBPtr->SharedPtr->TopNode, ((SysLimit << 8) & 0xFFFF0000) | DramLimitReg); - MemNSetBitFieldNb (NBPtr, BFDramLimitHiReg0 + NBPtr->SharedPtr->TopNode, SysLimit >> 24); - - // Node Interleave is not enabled, CoreStateSaveDestNode points to the node that contains top memory - MemNSetBitFieldNb (NBPtr, BFCoreStateSaveDestNode, NBPtr->SharedPtr->TopNode); - - if (NBPtr->Node == NBPtr->SharedPtr->TopNode) { - NBPtr->MCTPtr->NodeSysLimit = SysLimit; - } - } - - // Set BFCC6SaveEn - MemNSetBitFieldNb (NBPtr, BFCC6SaveEn, 1); - - // LockDramCfg will be set in FinalizeMCT - } -} - - -/* -----------------------------------------------------------------------------*/ -/** - * - * This function readjusts TOPMEM and MTRRs after allocating storage for C6 - * - * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK - * - */ -VOID -MemNC6AdjustMSRs ( - IN OUT MEM_NB_BLOCK *NBPtr - ) -{ - UINT32 SysLimit; - UINT32 CurAddr; - S_UINT64 SMsr; - - SysLimit = NBPtr->RefPtr->SysLimit + 1; - SMsr.hi = SysLimit >> (32 - 16); - SMsr.lo = SysLimit << 16; - if (SysLimit < _4GB_RJ16) { - LibAmdMsrWrite (TOP_MEM, (UINT64 *)&SMsr, &(NBPtr->MemPtr->StdHeader)); - IDS_HDT_CONSOLE (MEM_FLOW, "TOP_MEM: %08x0000\n", SysLimit); - // If there is no UMA buffer, then set top of cache and MTRR. - // Otherwise, top of cache and MTRR will be set when UMA buffer is set up. - if (NBPtr->RefPtr->UmaMode == UMA_NONE) { - NBPtr->RefPtr->Sub4GCacheTop = (SysLimit << 16); - // Find unused MTRR to set C6 region to UC - for (CurAddr = 0x200; CurAddr < 0x20C; CurAddr += 2) { - LibAmdMsrRead (CurAddr + 1, (UINT64 *)&SMsr, &NBPtr->MemPtr->StdHeader); - if ((SMsr.lo & ((UINT32) 1 << 11)) == 0) { - // Set region base as TOM - SMsr.hi = SysLimit >> (32 - 16); - SMsr.lo = SysLimit << 16; - LibAmdMsrWrite (CurAddr, (UINT64 *)&SMsr, &NBPtr->MemPtr->StdHeader); - - // set region mask to 16MB - SMsr.hi = NBPtr->VarMtrrHiMsk; - SMsr.lo = 0xFF000800; - LibAmdMsrWrite (CurAddr + 1, (UINT64 *)&SMsr, &NBPtr->MemPtr->StdHeader); - - break; - } - } - } - } else { - LibAmdMsrWrite (TOP_MEM2, (UINT64 *)&SMsr, &(NBPtr->MemPtr->StdHeader)); - IDS_HDT_CONSOLE (MEM_FLOW, "TOP_MEM2: %08x0000\n", SysLimit); - } -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * Family-specific hook to override the DdrMaxRate value for families with a - * non-GH-compatible encoding for BFDdrMaxRate - * - * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK - * @param[in,out] *DdrMaxRate - Void pointer to DdrMaxRate. Used as INT16. - * - * @return TRUE - * - */ -BOOLEAN -MemNGetMaxDdrRateUnb ( - IN OUT MEM_NB_BLOCK *NBPtr, - IN VOID *DdrMaxRate - ) -{ - UINT8 DdrMaxRateEncoded; - - DdrMaxRateEncoded = (UINT8) MemNGetBitFieldNb (NBPtr, BFDdrMaxRate); - - if (DdrMaxRateEncoded == 0) { - * (UINT16 *) DdrMaxRate = UNSUPPORTED_DDR_FREQUENCY; - } else { - * (UINT16 *) DdrMaxRate = MemNGetMemClkFreqUnb (NBPtr, DdrMaxRateEncoded); - } - return TRUE; -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * - * This function performs the action after save/restore execution - * - * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK - * @param[in,out] OptParam - Optional parameter - * - * @return TRUE - * - */ - -BOOLEAN -MemNAfterSaveRestoreUnb ( - IN OUT MEM_NB_BLOCK *NBPtr, - IN OUT VOID *OptParam - ) -{ - // Sync. up DctCfgSel value with NBPtr->Dct - MemNSetBitFieldNb (NBPtr, BFDctCfgSel, NBPtr->Dct); - - return TRUE; -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * - * This function performs the action before and after excluding dimms on CNB - * - * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK - * @param[in,out] *IsBefore - If the function is called before excluding dimms - * - * @return TRUE - * - */ - -BOOLEAN -MemNBfAfExcludeDimmClientNb ( - IN OUT MEM_NB_BLOCK *NBPtr, - IN OUT VOID *IsBefore - ) -{ - if (*(BOOLEAN *) IsBefore == TRUE) { - NBPtr->BrdcstSet (NBPtr, BFEnterSelfRef, 1); - NBPtr->PollBitField (NBPtr, BFEnterSelfRef, 0, PCI_ACCESS_TIMEOUT, TRUE); - } else { - NBPtr->BrdcstSet (NBPtr, BFExitSelfRef, 1); - NBPtr->PollBitField (NBPtr, BFExitSelfRef, 0, PCI_ACCESS_TIMEOUT, TRUE); - } - - return TRUE; -} - -/*---------------------------------------------------------------------------- - * LOCAL FUNCTIONS - * - *---------------------------------------------------------------------------- - */ diff --git a/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/mnphy.c b/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/mnphy.c deleted file mode 100644 index d84e4172ff..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/mnphy.c +++ /dev/null @@ -1,1967 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * mnphy.c - * - * Common Northbridge Phy support - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: (Mem/NB) - * @e \$Revision: 52411 $ @e \$Date: 2011-05-06 08:09:07 +0800 (Fri, 06 May 2011) $ - * - **/ -/***************************************************************************** -* -* Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* *************************************************************************** -* -*/ - - -/* - *---------------------------------------------------------------------------- - * MODULES USED - * - *---------------------------------------------------------------------------- - */ - - - -#include "AGESA.h" -#include "amdlib.h" -#include "Ids.h" -#include "mport.h" -#include "mm.h" -#include "mn.h" -#include "mt.h" -#include "mu.h" -#include "PlatformMemoryConfiguration.h" -#include "heapManager.h" -#include "merrhdl.h" -#include "Filecode.h" -CODE_GROUP (G1_PEICC) -RDATA_GROUP (G1_PEICC) -#define FILECODE PROC_MEM_NB_MNPHY_FILECODE -/*---------------------------------------------------------------------------- - * DEFINITIONS AND MACROS - * - *---------------------------------------------------------------------------- - */ -#define UNUSED_CLK 4 - -/*---------------------------------------------------------------------------- - * TYPEDEFS AND STRUCTURES - * - *---------------------------------------------------------------------------- - */ -/// Type of an entry for processing phy init compensation for client NB -typedef struct { - BIT_FIELD_NAME IndexBitField; ///< Bit field on which the value is decided - BIT_FIELD_NAME StartTargetBitField; ///< First bit field to be modified - BIT_FIELD_NAME EndTargetBitField; ///< Last bit field to be modified - UINT16 ExtraValue; ///< Extra value needed to be written to bit field - CONST UINT16 (*TxPrePN)[3][5]; ///< Pointer to slew rate table -} PHY_COMP_INIT_CLIENTNB; - -/*---------------------------------------------------------------------------- - * PROTOTYPES OF LOCAL FUNCTIONS - * - *---------------------------------------------------------------------------- - */ - - - -/*---------------------------------------------------------------------------- - * EXPORTED FUNCTIONS - * - *---------------------------------------------------------------------------- - */ -/* -----------------------------------------------------------------------------*/ -/** - * - * - * This function gets a delay value a PCI register during training - * - * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK - * @param[in] TrnDly - type of delay to be set - * @param[in] DrbnVar - encoding of Dimm-Rank-Byte-Nibble to be accessed - * (use either DIMM_BYTE_ACCESS(dimm,byte) or CS_NBBL_ACCESS(cs,nibble) to use this encoding - * - * @return Value read - */ - -UINT32 -MemNGetTrainDlyNb ( - IN OUT MEM_NB_BLOCK *NBPtr, - IN TRN_DLY_TYPE TrnDly, - IN DRBN DrbnVar - ) -{ - return NBPtr->MemNcmnGetSetTrainDly (NBPtr, 0, TrnDly, DrbnVar, 0); -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * - * This function sets a delay value a PCI register during training - * - * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK - * @param[in] TrnDly - type of delay to be set - * @param[in] DrbnVar - encoding of Dimm-Rank-Byte-Nibble to be accessed - * (use either DIMM_BYTE_ACCESS(dimm,byte) or CS_NBBL_ACCESS(cs,nibble) to use this encoding - * @param[in] Field - Value to be programmed - * - */ - -VOID -MemNSetTrainDlyNb ( - IN OUT MEM_NB_BLOCK *NBPtr, - IN TRN_DLY_TYPE TrnDly, - IN DRBN DrbnVar, - IN UINT16 Field - ) -{ - NBPtr->MemNcmnGetSetTrainDly (NBPtr, 1, TrnDly, DrbnVar, Field); -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * - * This function executes prototypical Phy fence training function. - * - * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK - * - */ - -VOID -MemNPhyFenceTrainingNb ( - IN OUT MEM_NB_BLOCK *NBPtr - ) -{ - NBPtr->MemPPhyFenceTrainingNb (NBPtr); -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * - * This function executes prototypical Phy fence training function. - * - * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK - * - */ - -VOID -MemNPhyFenceTrainingUnb ( - IN OUT MEM_NB_BLOCK *NBPtr - ) -{ - UINT8 FenceThresholdTxDll; - UINT8 FenceThresholdRxDll; - UINT8 FenceThresholdTxPad; - UINT16 Fence2Data; - - // 1. Program D18F2x[1,0]9C_x0000_0008[FenceTrSel]=10b. - // 2. Perform phy fence training. - // 3. Write the calculated fence value to D18F2x[1,0]9C_x0000_000C[FenceThresholdTxDll]. - MemNSetBitFieldNb (NBPtr, BFFenceTrSel, 2); - MAKE_TSEFO (NBPtr->NBRegTable, DCT_PHY_ACCESS, 0x0C, 30, 26, BFPhyFence); - IDS_HDT_CONSOLE (MEM_FLOW, "\t\tFenceThresholdTxDll\n"); - MemNTrainPhyFenceNb (NBPtr); - FenceThresholdTxDll = (UINT8) MemNGetBitFieldNb (NBPtr, BFPhyFence); - NBPtr->FamilySpecificHook[DetectMemPllError] (NBPtr, &FenceThresholdTxDll); - - // 4. Program D18F2x[1,0]9C_x0D0F_0[F,7:0]0F[AlwaysEnDllClks]=001b. - MemNSetBitFieldNb (NBPtr, BFAlwaysEnDllClks, 0x1000); - - // 5. Program D18F2x[1,0]9C_x0000_0008[FenceTrSel]=01b. - // 6. Perform phy fence training. - // 7. Write the calculated fence value to D18F2x[1,0]9C_x0000_000C[FenceThresholdRxDll]. - MemNSetBitFieldNb (NBPtr, BFFenceTrSel, 1); - MAKE_TSEFO (NBPtr->NBRegTable, DCT_PHY_ACCESS, 0x0C, 25, 21, BFPhyFence); - IDS_HDT_CONSOLE (MEM_FLOW, "\n\t\tFenceThresholdRxDll\n"); - MemNTrainPhyFenceNb (NBPtr); - FenceThresholdRxDll = (UINT8) MemNGetBitFieldNb (NBPtr, BFPhyFence); - NBPtr->FamilySpecificHook[DetectMemPllError] (NBPtr, &FenceThresholdRxDll); - - // 8. Program D18F2x[1,0]9C_x0D0F_0[F,7:0]0F[AlwaysEnDllClks]=000b. - MemNSetBitFieldNb (NBPtr, BFAlwaysEnDllClks, 0x0000); - - // 9. Program D18F2x[1,0]9C_x0000_0008[FenceTrSel]=11b. - // 10. Perform phy fence training. - // 11. Write the calculated fence value to D18F2x[1,0]9C_x0000_000C[FenceThresholdTxPad]. - MemNSetBitFieldNb (NBPtr, BFFenceTrSel, 3); - MAKE_TSEFO (NBPtr->NBRegTable, DCT_PHY_ACCESS, 0x0C, 20, 16, BFPhyFence); - IDS_HDT_CONSOLE (MEM_FLOW, "\n\t\tFenceThresholdTxPad\n"); - MemNTrainPhyFenceNb (NBPtr); - FenceThresholdTxPad = (UINT8) MemNGetBitFieldNb (NBPtr, BFPhyFence); - NBPtr->FamilySpecificHook[DetectMemPllError] (NBPtr, &FenceThresholdTxPad); - - // Program Fence2 threshold for Clk, Cmd, and Addr - if (FenceThresholdTxPad < 16) { - MemNSetBitFieldNb (NBPtr, BFClkFence2, FenceThresholdTxPad | 0x10); - MemNSetBitFieldNb (NBPtr, BFCmdFence2, FenceThresholdTxPad | 0x10); - MemNSetBitFieldNb (NBPtr, BFAddrFence2, FenceThresholdTxPad | 0x10); - } else { - MemNSetBitFieldNb (NBPtr, BFClkFence2, 0); - MemNSetBitFieldNb (NBPtr, BFCmdFence2, 0); - MemNSetBitFieldNb (NBPtr, BFAddrFence2, 0); - } - - // Program Fence2 threshold for data - Fence2Data = 0; - if (FenceThresholdTxPad < 16) { - Fence2Data |= FenceThresholdTxPad | 0x10; - } - if (FenceThresholdRxDll < 16) { - Fence2Data |= (FenceThresholdRxDll | 0x10) << 10; - } - if (FenceThresholdTxDll < 16) { - Fence2Data |= (FenceThresholdTxDll | 0x10) << 5; - } - MemNSetBitFieldNb (NBPtr, BFDataFence2, Fence2Data); - NBPtr->FamilySpecificHook[ProgramFence2RxDll] (NBPtr, &Fence2Data); - - if (NBPtr->MCTPtr->Status[SbLrdimms]) { - // 18. If motherboard routing requires CS[7:6] to adopt address timings, e.g. 3 LRDIMMs/ch with CS[7:6] - // routed across all DIMM sockets, BIOS performs the following: - if (FindPSOverrideEntry (NBPtr->RefPtr->PlatformMemoryConfiguration, PSO_NO_LRDIMM_CS67_ROUTING, NBPtr->MCTPtr->SocketId, NBPtr->ChannelPtr->ChannelID) != NULL) { - // A. Program D18F2xA8_dct[1:0][CSTimingMux67] = 1. - MemNSetBitFieldNb (NBPtr, BFCSTimingMux67, 1); - // B. Program D18F2x9C_x0D0F_8021_dct[1:0]: - // - DiffTimingEn = 1. - // - IF (D18F2x9C_x0000_0004_dct[1:0][AddrCmdFineDelay] >= - // D18F2x9C_x0D0F_E008_dct[1:0][FenceValue]) THEN Fence = 1 ELSE Fence = 0. - // - Delay = D18F2x9C_x0000_0004_dct[1:0][AddrCmdFineDelay]. - // - MemNSetBitFieldNb (NBPtr, BFDiffTimingEn, 1); - MemNSetBitFieldNb (NBPtr, BFFence, (MemNGetBitFieldNb (NBPtr, BFAddrCmdFineDelay) >= MemNGetBitFieldNb (NBPtr, BFFenceValue)) ? 1 : 0); - MemNSetBitFieldNb (NBPtr, BFDelay, (MemNGetBitFieldNb (NBPtr, BFAddrCmdFineDelay))); - } - } - - // 19. Reprogram F2x9C_04. - MemNSetBitFieldNb (NBPtr, BFAddrTmgControl, MemNGetBitFieldNb (NBPtr, BFAddrTmgControl)); - -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * - * This function executes Phy fence training - * - * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK - * - */ - -VOID -MemNTrainPhyFenceNb ( - IN OUT MEM_NB_BLOCK *NBPtr - ) -{ - UINT8 Byte; - INT16 Avg; - UINT8 PREvalue; - - if (MemNGetBitFieldNb (NBPtr, BFDisDramInterface)) { - return; - } - - // 1. BIOS first programs a seed value to the phase recovery - // engine registers. - // - IDS_HDT_CONSOLE (MEM_FLOW, "\t\tSeeds: "); - for (Byte = 0; Byte < MAX_BYTELANES_PER_CHANNEL; Byte++) { - // This includes ECC as byte 8 - MemNSetTrainDlyNb (NBPtr, AccessPhRecDly, DIMM_BYTE_ACCESS (0, Byte), 19); - IDS_HDT_CONSOLE (MEM_FLOW, "%02x ", 19); - } - - IDS_HDT_CONSOLE (MEM_FLOW, "\n\t\tPhyFenceTrEn = 1"); - // 2. Set F2x[1, 0]9C_x08[PhyFenceTrEn]=1. - MemNSetBitFieldNb (NBPtr, BFPhyFenceTrEn, 1); - - if (!NBPtr->IsSupported[UnifiedNbFence]) { - // 3. Wait 200 MEMCLKs. - MemNWaitXMemClksNb (NBPtr, 200); - } else { - // 3. Wait 2000 MEMCLKs. - MemNWaitXMemClksNb (NBPtr, 2000); - } - - // 4. Clear F2x[1, 0]9C_x08[PhyFenceTrEn]=0. - MemNSetBitFieldNb (NBPtr, BFPhyFenceTrEn, 0); - - // 5. BIOS reads the phase recovery engine registers - // F2x[1, 0]9C_x[51:50] and F2x[1, 0]9C_x52. - // 6. Calculate the average value of the fine delay and subtract 8. - // - Avg = 0; - IDS_HDT_CONSOLE (MEM_FLOW, "\n\t\t PRE: "); - for (Byte = 0; Byte < MAX_BYTELANES_PER_CHANNEL; Byte++) { - // - // This includes ECC as byte 8. ECC Byte lane (8) is ignored by MemNGetTrainDlyNb function where - // ECC is not supported. - // - PREvalue = (UINT8) (0x1F & MemNGetTrainDlyNb (NBPtr, AccessPhRecDly, DIMM_BYTE_ACCESS (0, Byte))); - Avg = Avg + ((INT16) PREvalue); - IDS_HDT_CONSOLE (MEM_FLOW, "%02x ", PREvalue); - } - Avg = ((Avg + 8) / 9); // round up - - Avg -= 8; - NBPtr->MemNPFenceAdjustNb (NBPtr, &Avg); - - IDS_HDT_CONSOLE (MEM_FLOW, "\n\t\tFence: %02x\n", Avg); - - // 7. Write the value to F2x[1, 0]9C_x0C[PhyFence]. - MemNSetBitFieldNb (NBPtr, BFPhyFence, Avg); - - // 8. BIOS rewrites F2x[1, 0]9C_x04, DRAM Address/Command Timing Control - // Register delays for both channels. This forces the phy to recompute - // the fence. - // - MemNSetBitFieldNb (NBPtr, BFAddrTmgControl, MemNGetBitFieldNb (NBPtr, BFAddrTmgControl)); -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * - * This function initializes the DDR phy compensation logic - * - * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK - * - */ - -VOID -MemNInitPhyCompNb ( - IN OUT MEM_NB_BLOCK *NBPtr - ) -{ - CONST UINT8 TableCompRiseSlew20x[] = {7, 3, 2, 2}; - CONST UINT8 TableCompRiseSlew15x[] = {7, 7, 3, 2}; - CONST UINT8 TableCompFallSlew20x[] = {7, 5, 3, 2}; - CONST UINT8 TableCompFallSlew15x[] = {7, 7, 5, 3}; - UINT8 i; - UINT8 j; - UINT8 CurrDct; - UINT8 CurrChannel; - BOOLEAN MarginImprv; - MarginImprv = FALSE; - CurrDct = NBPtr->Dct; - CurrChannel = NBPtr->Channel; - if (NBPtr->IsSupported[CheckSlewWithMarginImprv]) { - if (NBPtr->MCTPtr->GangedMode == FALSE) { - for (i = 0; i < NBPtr->DctCount; i++) { - MemNSwitchDCTNb (NBPtr, i); - for (j = 0; j < NBPtr->ChannelCount; j++) { - NBPtr->SwitchChannel (NBPtr, j); - if ((NBPtr->ChannelPtr->Dimms == 4) && ((NBPtr->DCTPtr->Timings.Speed == DDR533_FREQUENCY) || (NBPtr->DCTPtr->Timings.Speed == DDR667_FREQUENCY))) { - MarginImprv = TRUE; - } - } - } - MemNSwitchDCTNb (NBPtr, CurrDct); - NBPtr->SwitchChannel (NBPtr, CurrChannel); - } - } - - // 1. BIOS disables the phy compensation register by programming F2x9C_x08[DisAutoComp]=1 - // 2. BIOS waits 5 us for the disabling of the compensation engine to complete. - // DisAutoComp will be cleared after Dram init has completed - // - MemNSwitchDCTNb (NBPtr, 0); - MemNSetBitFieldNb (NBPtr, BFDisAutoComp, 1); - MemUWait10ns (500, NBPtr->MemPtr); - MemNSwitchDCTNb (NBPtr, CurrDct); - - // 3. For each normalized driver strength code read from - // F2x[1, 0]9C_x00[AddrCmdDrvStren], program the - // corresponding 3 bit predriver code in F2x9C_x0A[D3Cmp1NCal, D3Cmp1PCal]. - // - // 4. For each normalized driver strength code read from - // F2x[1, 0]9C_x00[DataDrvStren], program the corresponding - // 3 bit predriver code in F2x9C_x0A[D3Cmp0NCal, D3Cmp0PCal, D3Cmp2NCal, - // D3Cmp2PCal]. - // - j = (UINT8) MemNGetBitFieldNb (NBPtr, BFAddrCmdDrvStren); - i = (UINT8) MemNGetBitFieldNb (NBPtr, BFDataDrvStren); - - MemNSwitchDCTNb (NBPtr, 0); - MemNSetBitFieldNb (NBPtr, BFD3Cmp1NCal, TableCompRiseSlew20x[j]); - MemNSetBitFieldNb (NBPtr, BFD3Cmp1PCal, TableCompFallSlew20x[j]); - - if (NBPtr->IsSupported[CheckSlewWithMarginImprv]) { - MemNSetBitFieldNb (NBPtr, BFD3Cmp0NCal, (MarginImprv) ? 0 : TableCompRiseSlew15x[i]); - MemNSetBitFieldNb (NBPtr, BFD3Cmp0PCal, (MarginImprv) ? 0 : TableCompFallSlew15x[i]); - MemNSetBitFieldNb (NBPtr, BFD3Cmp2NCal, (MarginImprv) ? 0 : TableCompRiseSlew15x[i]); - MemNSetBitFieldNb (NBPtr, BFD3Cmp2PCal, (MarginImprv) ? 0 : TableCompFallSlew15x[i]); - } - if (NBPtr->IsSupported[CheckSlewWithoutMarginImprv]) { - ASSERT (i <= 3); - MemNSetBitFieldNb (NBPtr, BFD3Cmp0NCal, TableCompRiseSlew15x[i]); - MemNSetBitFieldNb (NBPtr, BFD3Cmp0PCal, TableCompFallSlew15x[i]); - MemNSetBitFieldNb (NBPtr, BFD3Cmp2NCal, TableCompRiseSlew15x[i]); - MemNSetBitFieldNb (NBPtr, BFD3Cmp2PCal, TableCompFallSlew15x[i]); - } - MemNSwitchDCTNb (NBPtr, CurrDct); -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * - * This is a general purpose function that executes before DRAM training - * - * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK - * - */ - -VOID -MemNBeforeDQSTrainingNb ( - IN OUT MEM_NB_BLOCK *NBPtr - ) -{ - UINT8 Dct; - UINT8 ChipSel; - UINT32 TestAddrRJ16; - UINT32 RealAddr; - - MemTBeginTraining (NBPtr->TechPtr); - - for (Dct = 0; Dct < NBPtr->DctCount; Dct++) { - MemNSwitchDCTNb (NBPtr, Dct); - if (NBPtr->DCTPtr->Timings.DctMemSize != 0) { - for (ChipSel = 0; ChipSel < MAX_CS_PER_CHANNEL; ChipSel += 2) { - if (MemNGetMCTSysAddrNb (NBPtr, ChipSel, &TestAddrRJ16)) { - - RealAddr = MemUSetUpperFSbase (TestAddrRJ16, NBPtr->MemPtr); - - MemUDummyCLRead (RealAddr); - - MemNSetBitFieldNb (NBPtr, BFErr350, 0x8000); - MemUWait10ns (60, NBPtr->MemPtr); // Wait 300ns - MemNSetBitFieldNb (NBPtr, BFErr350, 0x0000); - MemUWait10ns (400, NBPtr->MemPtr); // Wait 2us - MemUProcIOClFlush (TestAddrRJ16, 1, NBPtr->MemPtr); - break; - } - } - } - if (NBPtr->IsSupported[CheckEccDLLPwrDnConfig]) { - if (!NBPtr->MCTPtr->Status[SbEccDimms]) { - MemNSetBitFieldNb (NBPtr, BFEccDLLPwrDnConf, 0x0010); - } - if (NBPtr->DCTPtr->Timings.Dimmx4Present == 0) { - MemNSetBitFieldNb (NBPtr, BFEccDLLConf, 0x0080); - } - } - } - - MemTEndTraining (NBPtr->TechPtr); -} - -/*-----------------------------------------------------------------------------*/ -/** - * - * Returns the parameters for a requested delay value to be used in training - * The correct Min, Max and Mask are determined based on the type of Delay, - * and the frequency - * - * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK - * @param[in] TrnDly - Type of delay - * @param[in,out] *Parms - Pointer to the TRN_DLY-PARMS struct - * - */ - -VOID -MemNGetTrainDlyParmsNb ( - IN OUT MEM_NB_BLOCK *NBPtr, - IN TRN_DLY_TYPE TrnDly, - IN OUT TRN_DLY_PARMS *Parms - ) -{ - Parms->Min = 0; - - if (TrnDly == AccessWrDatDly) { - Parms->Max = 0x1F; - Parms->Mask = 0x01F; - } else if (TrnDly == AccessRdDqsDly) { - if ( (NBPtr->IsSupported[CheckMaxRdDqsDlyPtr]) && (NBPtr->DCTPtr->Timings.Speed > DDR667_FREQUENCY) ) { - Parms->Max = 0x3E; - Parms->Mask = 0x03E; - } else { - Parms->Max = 0x1F; - Parms->Mask = 0x01F; - } - } -} - -/*-----------------------------------------------------------------------------*/ -/** - * - * Returns the parameters for a requested delay value to be used in training - * The correct Min, Max and Mask are determined based on the type of Delay, - * and the frequency - * - * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK - * @param[in] TrnDly - Type of delay - * @param[in,out] *Parms - Pointer to the TRN_DLY-PARMS struct - * - */ - -VOID -MemNGetTrainDlyParmsClientNb ( - IN OUT MEM_NB_BLOCK *NBPtr, - IN TRN_DLY_TYPE TrnDly, - IN OUT TRN_DLY_PARMS *Parms - ) -{ - Parms->Min = 0; - - if (TrnDly == AccessWrDatDly) { - Parms->Max = 0x1F; - Parms->Mask = 0x01F; - } else if (TrnDly == AccessRdDqsDly) { - Parms->Max = 0x3E; - Parms->Mask = 0x03E; - } -} -/*-----------------------------------------------------------------------------*/ -/** - * - * Returns the parameters for a requested delay value to be used in training - * The correct Min, Max and Mask are determined based on the type of Delay, - * and the frequency - * - * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK - * @param[in] TrnDly - Type of delay - * @param[in,out] *Parms - Pointer to the TRN_DLY-PARMS struct - * - */ - -VOID -MemNGetTrainDlyParmsUnb ( - IN OUT MEM_NB_BLOCK *NBPtr, - IN TRN_DLY_TYPE TrnDly, - IN OUT TRN_DLY_PARMS *Parms - ) -{ - Parms->Min = 0; - - if ((TrnDly == AccessWrDatDly) || (TrnDly == AccessRdDqsDly)) { - Parms->Max = 0x1F; - Parms->Mask = 0x01F; - } -} -/*---------------------------------------------------------------------------- - * LOCAL FUNCTIONS - * - *---------------------------------------------------------------------------- - */ -/* -----------------------------------------------------------------------------*/ -/** - * - * - * This function gets or set DQS timing during training. - * - * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK - * @param[in] TrnDly - type of delay to be set - * @param[in] DrbnVar - encoding of Dimm-Rank-Byte-Nibble to be accessed - * (use either DIMM_BYTE_ACCESS(dimm,byte) or CS_NBBL_ACCESS(cs,nibble) to use this encoding - * @param[in] Field - Value to be programmed - * @param[in] IsSet - Indicates if the function will set or get - * - * @return value read, if the function is used as a "get" - */ - -UINT32 -MemNcmnGetSetTrainDlyNb ( - IN OUT MEM_NB_BLOCK *NBPtr, - IN UINT8 IsSet, - IN TRN_DLY_TYPE TrnDly, - IN DRBN DrbnVar, - IN UINT16 Field - ) -{ - UINT16 Index; - UINT16 Offset; - UINT32 Value; - UINT32 Address; - UINT8 Dimm; - UINT8 Rank; - UINT8 Byte; - UINT8 Nibble; - - Dimm = DRBN_DIMM (DrbnVar); - Rank = DRBN_RANK (DrbnVar); - Byte = DRBN_BYTE (DrbnVar); - Nibble = DRBN_NBBL (DrbnVar); - - ASSERT (Dimm < 4); - ASSERT (Byte <= ECC_DLY); - - switch (TrnDly) { - case AccessRcvEnDly: - Index = 0x10; - break; - case AccessWrDqsDly: - Index = 0x30; - break; - case AccessWrDatDly: - Index = 0x01; - break; - case AccessRdDqsDly: - Index = 0x05; - break; - case AccessPhRecDly: - Index = 0x50; - break; - default: - Index = 0; - IDS_ERROR_TRAP; - } - - switch (TrnDly) { - case AccessRcvEnDly: - case AccessWrDqsDly: - Index += (Dimm * 3); - if (Byte & 0x04) { - // if byte 4,5,6,7 - Index += 0x10; - } - if (Byte & 0x02) { - // if byte 2,3,6,7 - Index++; - } - if (Byte > 7) { - Index += 2; - } - Offset = 16 * (Byte % 2); - Index |= (Rank << 8); - Index |= (Nibble << 9); - break; - - case AccessRdDqsDly: - case AccessWrDatDly: - - if (NBPtr->IsSupported[DimmBasedOnSpeed]) { - if (NBPtr->DCTPtr->Timings.Speed < DDR800_FREQUENCY) { - // if DDR speed is below 800, use DIMM 0 delays for all DIMMs. - Dimm = 0; - } - } - - Index += (Dimm * 0x100); - if (Nibble) { - if (Rank) { - Index += 0xA0; - } else { - Index += 0x70; - } - } else if (Rank) { - Index += 0x60; - } - // fall through - AccessRdDqsDly and AccessWrDatDly also need to run AccessPhRecDly sequence - case AccessPhRecDly: - Index += (Byte / 4); - Offset = 8 * (Byte % 4); - break; - default: - Offset = 0; - IDS_ERROR_TRAP; - } - - Address = Index; - MemNSetBitFieldNb (NBPtr, BFDctAddlOffsetReg, Address); - MemNPollBitFieldNb (NBPtr, BFDctAccessDone, 1, PCI_ACCESS_TIMEOUT, FALSE); - Value = MemNGetBitFieldNb (NBPtr, BFDctAddlDataReg); - - if (TrnDly == AccessRdDqsDly) { - NBPtr->FamilySpecificHook[AdjustRdDqsDlyOffset] (NBPtr, &Offset); - } - - if (IsSet) { - if (TrnDly == AccessPhRecDly) { - Value = NBPtr->DctCachePtr->PhRecReg[Index & 0x03]; - } - - Value = ((UINT32)Field << Offset) | (Value & (~((UINT32) ((TrnDly == AccessRcvEnDly) ? 0x1FF : 0xFF) << Offset))); - MemNSetBitFieldNb (NBPtr, BFDctAddlDataReg, Value); - Address |= DCT_ACCESS_WRITE; - MemNSetBitFieldNb (NBPtr, BFDctAddlOffsetReg, Address); - MemNPollBitFieldNb (NBPtr, BFDctAccessDone, 1, PCI_ACCESS_TIMEOUT, FALSE); - - if (TrnDly == AccessPhRecDly) { - NBPtr->DctCachePtr->PhRecReg[Index & 0x03] = Value; - } - } else { - Value = (Value >> Offset) & (UINT32) ((TrnDly == AccessRcvEnDly) ? 0x1FF : 0xFF); - } - - return Value; -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * This function gets or set DQS timing during training. - * - * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK - * @param[in] IsSet - Indicates if the function will set or get - * @param[in] TrnDly - type of delay to be set - * @param[in] DrbnVar - encoding of Dimm-Rank-Byte-Nibble to be accessed - * (use either DIMM_BYTE_ACCESS(dimm,byte) or CS_NBBL_ACCESS(cs,nibble) to use this encoding - * @param[in] Field - Value to be programmed - * - * @return value read, if the function is used as a "get" - */ -UINT32 -MemNcmnGetSetTrainDlyClientNb ( - IN OUT MEM_NB_BLOCK *NBPtr, - IN UINT8 IsSet, - IN TRN_DLY_TYPE TrnDly, - IN DRBN DrbnVar, - IN UINT16 Field - ) -{ - UINT16 Index; - UINT16 Offset; - UINT32 Value; - UINT32 Address; - UINT8 Dimm; - UINT8 Byte; - - Dimm = DRBN_DIMM (DrbnVar); - Byte = DRBN_BYTE (DrbnVar); - - ASSERT (Dimm < 2); - ASSERT (Byte <= ECC_DLY); - - if ((Byte > 7)) { - // Llano does not support ECC delay, so: - if (IsSet) { - // On write, ignore - return 0; - } else { - // On read, redirect to byte 0 to correct fence averaging - Byte = 0; - } - } - - switch (TrnDly) { - case AccessRcvEnDly: - Index = 0x10; - break; - case AccessWrDqsDly: - Index = 0x30; - break; - case AccessWrDatDly: - Index = 0x01; - break; - case AccessRdDqsDly: - Index = 0x05; - break; - case AccessPhRecDly: - Index = 0x50; - break; - default: - Index = 0; - IDS_ERROR_TRAP; - } - - switch (TrnDly) { - case AccessRcvEnDly: - case AccessWrDqsDly: - Index += (Dimm * 3); - if (Byte & 0x04) { - // if byte 4,5,6,7 - Index += 0x10; - } - if (Byte & 0x02) { - // if byte 2,3,6,7 - Index++; - } - Offset = 16 * (Byte % 2); - break; - - case AccessRdDqsDly: - case AccessWrDatDly: - Index += (Dimm * 0x100); - // fall through - AccessRdDqsDly and AccessWrDatDly also need to run AccessPhRecDly sequence - case AccessPhRecDly: - Index += (Byte / 4); - Offset = 8 * (Byte % 4); - break; - default: - Offset = 0; - IDS_ERROR_TRAP; - } - - Address = Index; - MemNSetBitFieldNb (NBPtr, BFDctAddlOffsetReg, Address); - Value = MemNGetBitFieldNb (NBPtr, BFDctAddlDataReg); - - if (IsSet) { - if (TrnDly == AccessPhRecDly) { - Value = NBPtr->DctCachePtr->PhRecReg[Index & 0x03]; - } - - Value = ((UINT32)Field << Offset) | (Value & (~((UINT32) ((TrnDly == AccessRcvEnDly) ? 0x1FF : 0xFF) << Offset))); - MemNSetBitFieldNb (NBPtr, BFDctAddlDataReg, Value); - Address |= DCT_ACCESS_WRITE; - MemNSetBitFieldNb (NBPtr, BFDctAddlOffsetReg, Address); - - if (TrnDly == AccessPhRecDly) { - NBPtr->DctCachePtr->PhRecReg[Index & 0x03] = Value; - } - // Gross WrDatDly and WrDqsDly cannot be larger than 4 - ASSERT (((TrnDly == AccessWrDatDly) || (TrnDly == AccessWrDqsDly)) ? (NBPtr->IsSupported[WLNegativeDelay] || (Field < 0xA0)) : TRUE); - } else { - Value = (Value >> Offset) & (UINT32) ((TrnDly == AccessRcvEnDly) ? 0x1FF : 0xFF); - } - - return Value; -} -/* -----------------------------------------------------------------------------*/ -/** - * - * - * This function gets or set DQS timing during training. - * - * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK - * @param[in] TrnDly - type of delay to be set - * @param[in] DrbnVar - encoding of Dimm-Rank-Byte-Nibble to be accessed - * (use either DIMM_BYTE_ACCESS(dimm,byte) or CS_NBBL_ACCESS(cs,nibble) to use this encoding - * @param[in] Field - Value to be programmed - * @param[in] IsSet - Indicates if the function will set or get - * - * @return value read, if the function is used as a "get" - */ - -UINT32 -MemNcmnGetSetTrainDlyUnb ( - IN OUT MEM_NB_BLOCK *NBPtr, - IN UINT8 IsSet, - IN TRN_DLY_TYPE TrnDly, - IN DRBN DrbnVar, - IN UINT16 Field - ) -{ - UINT16 Index; - UINT16 Offset; - UINT32 Value; - UINT32 Address; - UINT8 Dimm; - UINT8 Rank; - UINT8 Byte; - UINT8 Nibble; - - Dimm = DRBN_DIMM (DrbnVar); - Rank = DRBN_RANK (DrbnVar); - Byte = DRBN_BYTE (DrbnVar); - Nibble = DRBN_NBBL (DrbnVar); - - ASSERT (Dimm < 4); - ASSERT (Byte <= ECC_DLY); - if ((Byte == ECC_DLY) && !NBPtr->MCTPtr->Status[SbEccDimms]) { - // When ECC is not enabled - if (IsSet) { - // On write, ignore - return 0; - } else { - // On read, redirect to byte 0 to correct fence averaging - Byte = 0; - } - } - - switch (TrnDly) { - case AccessRcvEnDly: - Index = 0x10; - break; - case AccessWrDqsDly: - Index = 0x30; - break; - case AccessWrDatDly: - Index = 0x01; - break; - case AccessRdDqsDly: - Index = 0x05; - break; - case AccessPhRecDly: - Index = 0x50; - break; - default: - Index = 0; - IDS_ERROR_TRAP; - } - - switch (TrnDly) { - case AccessRcvEnDly: - case AccessWrDqsDly: - Index += (Dimm * 3); - if (Byte & 0x04) { - // if byte 4,5,6,7 - Index += 0x10; - } - if (Byte & 0x02) { - // if byte 2,3,6,7 - Index++; - } - if (Byte > 7) { - Index += 2; - } - Offset = 16 * (Byte % 2); - Index |= (Rank << 8); - Index |= (Nibble << 9); - break; - - case AccessRdDqsDly: - case AccessWrDatDly: - - if (NBPtr->IsSupported[DimmBasedOnSpeed]) { - if (NBPtr->DCTPtr->Timings.Speed < DDR800_FREQUENCY) { - // if DDR speed is below 800, use DIMM 0 delays for all DIMMs. - Dimm = 0; - } - } - - Index += (Dimm * 0x100); - if (Nibble) { - if (Rank) { - Index += 0xA0; - } else { - Index += 0x70; - } - } else if (Rank) { - Index += 0x60; - } - // fall through - AccessRdDqsDly and AccessWrDatDly also need to run AccessPhRecDly sequence - case AccessPhRecDly: - Index += (Byte / 4); - Offset = 8 * (Byte % 4); - break; - default: - Offset = 0; - IDS_ERROR_TRAP; - } - - Address = Index; - MemNSetBitFieldNb (NBPtr, BFDctAddlOffsetReg, Address); - MemNPollBitFieldNb (NBPtr, BFDctAccessDone, 1, PCI_ACCESS_TIMEOUT, FALSE); - Value = MemNGetBitFieldNb (NBPtr, BFDctAddlDataReg); - - if (TrnDly == AccessRdDqsDly) { - NBPtr->FamilySpecificHook[AdjustRdDqsDlyOffset] (NBPtr, &Offset); - } - - if (IsSet) { - if (TrnDly == AccessPhRecDly) { - Value = NBPtr->DctCachePtr->PhRecReg[Index & 0x03]; - } - - Value = ((UINT32)Field << Offset) | (Value & (~((UINT32) ((TrnDly == AccessRcvEnDly) ? 0x3FF : 0xFF) << Offset))); - MemNSetBitFieldNb (NBPtr, BFDctAddlDataReg, Value); - Address |= DCT_ACCESS_WRITE; - MemNSetBitFieldNb (NBPtr, BFDctAddlOffsetReg, Address); - MemNPollBitFieldNb (NBPtr, BFDctAccessDone, 1, PCI_ACCESS_TIMEOUT, FALSE); - - if (TrnDly == AccessPhRecDly) { - NBPtr->DctCachePtr->PhRecReg[Index & 0x03] = Value; - } - } else { - Value = (Value >> Offset) & (UINT32) ((TrnDly == AccessRcvEnDly) ? 0x3FF : 0xFF); - } - - return Value; -} -/* -----------------------------------------------------------------------------*/ -/** - * - * This function initializes the training pattern. - * - * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK - * - * @return AGESA_STATUS - Result - * AGESA_SUCCESS - Training pattern is ready to use - * AGESA_ERROR - Unable to initialize the pattern. - */ - -AGESA_STATUS -MemNTrainingPatternInitNb ( - IN OUT MEM_NB_BLOCK *NBPtr - ) -{ - MEM_TECH_BLOCK *TechPtr; - ALLOCATE_HEAP_PARAMS AllocHeapParams; - TRAIN_PATTERN TrainPattern; - AGESA_STATUS Status; - - TechPtr = NBPtr->TechPtr; - TrainPattern = 0; - // - // Check the training type - // - if (TechPtr->TrainingType == TRN_DQS_POSITION) { - // - // DQS Position Training - // - if (NBPtr->PosTrnPattern == POS_PATTERN_256B) { - // - // 256 Bit pattern - // - if (NBPtr->MCTPtr->Status[Sb128bitmode]) { - TrainPattern = TestPatternJD256B; - TechPtr->PatternLength = 64; - } else { - TrainPattern = TestPatternJD256A; - TechPtr->PatternLength = 32; - } - } else { - // - // 72 bit pattern will be used if PosTrnPattern is not specified - // - if (NBPtr->MCTPtr->Status[Sb128bitmode]) { - TrainPattern = TestPatternJD1B; - TechPtr->PatternLength = 18; - } else { - TrainPattern = TestPatternJD1A; - TechPtr->PatternLength = 9; - } - } - } else if (TechPtr->TrainingType == TRN_MAX_READ_LATENCY) { - // - // Max Read Latency Training - // - TrainPattern = TestPatternML; - TechPtr->PatternLength = (NBPtr->MCTPtr->Status[Sb128bitmode]) ? 6 : 3; - } else { - // - // Error - TechPtr->Training Type must be set to one of the types handled in this function - // - ASSERT (FALSE); - } - // - // Allocate training buffer - // - AllocHeapParams.RequestedBufferSize = (TechPtr->PatternLength * 64 * 2) + 16; - AllocHeapParams.BufferHandle = AMD_MEM_TRAIN_BUFFER_HANDLE; - AllocHeapParams.Persist = HEAP_LOCAL_CACHE; - Status = HeapAllocateBuffer (&AllocHeapParams, &NBPtr->MemPtr->StdHeader); - ASSERT (Status == AGESA_SUCCESS); - if (Status != AGESA_SUCCESS) { - return Status; - } - TechPtr->PatternBufPtr = AllocHeapParams.BufferPtr; - AlignPointerTo16Byte (&TechPtr->PatternBufPtr); - TechPtr->TestBufPtr = TechPtr->PatternBufPtr + (TechPtr->PatternLength * 64); - - // Prepare training pattern - MemUFillTrainPattern (TrainPattern, TechPtr->PatternBufPtr, TechPtr->PatternLength * 64); - - return Status; -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * This function determined the settings for the Reliable Read/Write engine - * for each specific type of training - * - * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK - * @param[in] *OptParam - Pointer to an Enum of TRAINING_TYPE - * - * @return TRUE - */ - -BOOLEAN -MemNSetupHwTrainingEngineUnb ( - IN OUT MEM_NB_BLOCK *NBPtr, - IN VOID *OptParam - ) -{ - TRAINING_TYPE TrnType; - RRW_SETTINGS *Rrw; - - TrnType = *(TRAINING_TYPE*) OptParam; - Rrw = &NBPtr->RrwSettings; - // - // Common Settings - // - Rrw->TgtBankAddressA = CPG_BANK_ADDRESS_A; - Rrw->TgtRowAddressA = CPG_ROW_ADDRESS_A; - Rrw->TgtColAddressA = CPG_COL_ADDRESS_A; - Rrw->TgtBankAddressB = CPG_BANK_ADDRESS_B; - Rrw->TgtRowAddressB = CPG_ROW_ADDRESS_B; - Rrw->TgtColAddressB = CPG_COL_ADDRESS_B; - Rrw->CompareMaskHigh = CPG_COMPARE_MASK_HI; - Rrw->CompareMaskLow = CPG_COMPARE_MASK_LOW; - Rrw->CompareMaskEcc = CPG_COMPARE_MASK_ECC; - - switch (TrnType) { - case TRN_RCVR_ENABLE: - // - // Receiver Enable Training - // - NBPtr->TechPtr->PatternLength = 192; - break; - case TRN_MAX_READ_LATENCY: - // - // Max Read Latency Training - // - Rrw->CmdTgt = CMD_TGT_A; - NBPtr->TechPtr->PatternLength = 32; - Rrw->DataPrbsSeed = PRBS_SEED_32; - break; - case TRN_DQS_POSITION: - // - // Read/Write DQS Position training - // - Rrw->CmdTgt = CMD_TGT_AB; - NBPtr->TechPtr->PatternLength = 256; - Rrw->DataPrbsSeed = PRBS_SEED_256; - break; - default: - ASSERT (FALSE); - } - return TRUE; -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * This function finalizes the training pattern. - * - * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK - * @param[in] Index - Index of Write Data Delay Value - * @param[in,out] *Value - Write Data Delay Value - * @return BOOLEAN - TRUE - Use the value returned. - * FALSE - No more values in table. - */ - -BOOLEAN -MemNGetApproximateWriteDatDelayNb ( - IN OUT MEM_NB_BLOCK *NBPtr, - IN UINT8 Index, - IN OUT UINT8 *Value - ) -{ - CONST UINT8 WriteDatDelayValue[] = {0x10, 0x4, 0x8, 0xC, 0x14, 0x18, 0x1C, 0x1F}; - if (Index < GET_SIZE_OF (WriteDatDelayValue)) { - *Value = WriteDatDelayValue[Index]; - return TRUE; - } - return FALSE; -} - - -/* -----------------------------------------------------------------------------*/ -/** - * - * This function finalizes the training pattern. - * - * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK - * - * @return AGESA_STATUS - Result - * AGESA_SUCCESS - Training pattern has been finalized. - * AGESA_ERROR - Unable to initialize the pattern. - */ - -AGESA_STATUS -MemNTrainingPatternFinalizeNb ( - IN OUT MEM_NB_BLOCK *NBPtr - ) -{ - AGESA_STATUS Status; - // - // Deallocate training buffer - // - Status = HeapDeallocateBuffer (AMD_MEM_TRAIN_BUFFER_HANDLE, &NBPtr->MemPtr->StdHeader); - ASSERT (Status == AGESA_SUCCESS); - return Status; -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * This function returns the number of chipselects per channel. - * - * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK - * - * @return - */ - -UINT8 -MemNCSPerChannelNb ( - IN OUT MEM_NB_BLOCK *NBPtr - ) -{ - return MAX_CS_PER_CHANNEL; -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * This function returns the number of Chipselects controlled by each set - * of Delay registers under current conditions. - * - * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK - * - * @return - */ - -UINT8 -MemNCSPerDelayNb ( - IN OUT MEM_NB_BLOCK *NBPtr - ) -{ - return MAX_CS_PER_DELAY; -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * This function returns the minimum data eye width in 32nds of a UI for - * the type of data eye(Rd/Wr) that is being trained. This value will - * be the minimum number of consecutive delays that yield valid data. - * Uses TechPtr->Direction to determine read or write. - * - * - * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK - * - * @return - */ - -UINT8 -MemNMinDataEyeWidthNb ( - IN OUT MEM_NB_BLOCK *NBPtr - ) -{ - if (NBPtr->TechPtr->Direction == DQS_READ_DIR) { - return MIN_RD_DATAEYE_WIDTH_NB; - } else { - return MIN_WR_DATAEYE_WIDTH_NB; - } -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * This function programs the phy registers according to the desired phy VDDIO voltage level - * - * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK - * - */ - -VOID -MemNPhyVoltageLevelNb ( - IN OUT MEM_NB_BLOCK *NBPtr - ) -{ - BIT_FIELD_NAME BitField; - BIT_FIELD_NAME BFEnd; - UINT16 BFValue; - UINT16 RegValue; - - BFValue = (UINT16) CONVERT_VDDIO_TO_ENCODED (NBPtr->RefPtr->DDR3Voltage) << 3; - BFEnd = NBPtr->IsSupported[ProgramCsrComparator] ? BFCsrComparator : BFCmpVioLvl; - - for (BitField = BFDataRxVioLvl; BitField <= BFEnd; BitField++) { - RegValue = BFValue; - if (BitField == BFCsrComparator) { - RegValue >>= (3 - 2); - // Setting this bit in DCT0 adjusts the comparator for DCT0 and DCT1. Setting this bit in DCT1 has no effect. - NBPtr->SwitchDCT (NBPtr, 0); - MemNSetBitFieldNb (NBPtr, BitField, RegValue); - break; - } else if (BitField == BFCmpVioLvl) { - RegValue <<= (14 - 3); - } - MemNBrdcstSetNb (NBPtr, BitField, RegValue); - } -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * - * This function adjusts Avg PRE value of Phy fence training according to specific CPU family. - * - * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK - * @param[in,out] *Value16 - Pointer to the value that we want to adjust - * - */ -VOID -MemNPFenceAdjustUnb ( - IN OUT MEM_NB_BLOCK *NBPtr, - IN OUT INT16 *Value16 - ) -{ - *Value16 += 2; //The Avg PRE value is subtracted by 6 only. -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * - * This function initializes the DDR phy compensation logic - * - * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK - * - */ - -VOID -MemNInitPhyCompClientNb ( - IN OUT MEM_NB_BLOCK *NBPtr - ) -{ - // Slew rate table array [x][y][z] - // array[0]: slew rate for VDDIO 1.5V - // array[1]: slew rate for VDDIO 1.35V - // array[2]: slew rate for VDDIO 1.25V - // array[x][y]: slew rate for a certain frequency - // array[x][y][0]: frequency mask for current entry - CONST STATIC UINT16 TxPrePNDataDqs[3][3][5] = { - {{ (UINT16) DDR800, 0x924, 0x924, 0x924, 0x924}, - { (UINT16) (DDR1066 + DDR1333), 0xFF6, 0xFF6, 0xFF6, 0xFF6}, - { (UINT16) (DDR1600 + DDR1866), 0xFF6, 0xFF6, 0xFF6, 0xFF6}}, - {{ (UINT16) DDR800, 0xFF6, 0xB6D, 0xB6D, 0x924}, - { (UINT16) (DDR1066 + DDR1333), 0xFF6, 0xFF6, 0xFF6, 0xFF6}, - { (UINT16) (DDR1600 + DDR1866), 0xFF6, 0xFF6, 0xFF6, 0xFF6}}, - {{ (UINT16) DDR800, 0xFF6, 0xDAD, 0xDAD, 0x924}, - { (UINT16) (DDR1066 + DDR1333), 0xFF6, 0xFF6, 0xFF6, 0xFF6}, - { (UINT16) (DDR1600 + DDR1866), 0xFF6, 0xFF6, 0xFF6, 0xFF6}} - }; - CONST STATIC UINT16 TxPrePNCmdAddr[3][3][5] = { - {{ (UINT16) DDR800, 0x492, 0x492, 0x492, 0x492}, - { (UINT16) (DDR1066 + DDR1333), 0x6DB, 0x6DB, 0x6DB, 0x6DB}, - { (UINT16) (DDR1600 + DDR1866), 0xB6D, 0xB6D, 0xB6D, 0xB6D}}, - {{ (UINT16) DDR800, 0x492, 0x492, 0x492, 0x492}, - { (UINT16) (DDR1066 + DDR1333), 0x924, 0x6DB, 0x6DB, 0x6DB}, - { (UINT16) (DDR1600 + DDR1866), 0xB6D, 0xB6D, 0x924, 0x924}}, - {{ (UINT16) DDR800, 0x492, 0x492, 0x492, 0x492}, - { (UINT16) (DDR1066 + DDR1333), 0xDAD, 0x924, 0x6DB, 0x492}, - { (UINT16) (DDR1600 + DDR1866), 0xFF6, 0xDAD, 0xB64, 0xB64}} - }; - CONST STATIC UINT16 TxPrePNClock[3][3][5] = { - {{ (UINT16) DDR800, 0x924, 0x924, 0x924, 0x924}, - { (UINT16) (DDR1066 + DDR1333), 0xFF6, 0xFF6, 0xFF6, 0xB6D}, - { (UINT16) (DDR1600 + DDR1866), 0xFF6, 0xFF6, 0xFF6, 0xFF6}}, - {{ (UINT16) DDR800, 0xDAD, 0xDAD, 0x924, 0x924}, - { (UINT16) (DDR1066 + DDR1333), 0xFF6, 0xFF6, 0xFF6, 0xDAD}, - { (UINT16) (DDR1600 + DDR1866), 0xFF6, 0xFF6, 0xFF6, 0xDAD}}, - {{ (UINT16) DDR800, 0xDAD, 0xDAD, 0x924, 0x924}, - { (UINT16) (DDR1066 + DDR1333), 0xFF6, 0xFF6, 0xFF6, 0xFF6}, - { (UINT16) (DDR1600 + DDR1866), 0xFF6, 0xFF6, 0xFF6, 0xFF6}} - }; - - CONST PHY_COMP_INIT_CLIENTNB PhyCompInitBitField[] = { - // 3. Program TxPreP/TxPreN for Data and DQS according toTable 14 if VDDIO is 1.5V or Table 15 if 1.35V. - // A. Program D18F2x[1,0]9C_x0D0F_0[F,7:0]0[A,6]={0000b, TxPreP, TxPreN}. - // B. Program D18F2x[1,0]9C_x0D0F_0[F,7:0]02={1000b, TxPreP, TxPreN}. - {BFDqsDrvStren, BFDataByteTxPreDriverCal2Pad1, BFDataByteTxPreDriverCal2Pad1, 0, TxPrePNDataDqs}, - {BFDataDrvStren, BFDataByteTxPreDriverCal2Pad2, BFDataByteTxPreDriverCal2Pad2, 0, TxPrePNDataDqs}, - {BFDataDrvStren, BFDataByteTxPreDriverCal, BFDataByteTxPreDriverCal, 8, TxPrePNDataDqs}, - // 4. Program TxPreP/TxPreN for Cmd/Addr according toTable 16 if VDDIO is 1.5V or Table 17 if 1.35V. - // A. Program D18F2x[1,0]9C_x0D0F_[C,8][1:0][12,0E,0A,06]={0000b, TxPreP, TxPreN}. - // B. Program D18F2x[1,0]9C_x0D0F_[C,8][1:0]02={1000b, TxPreP, TxPreN}. - {BFCsOdtDrvStren, BFCmdAddr0TxPreDriverCal2Pad1, BFCmdAddr0TxPreDriverCal2Pad2, 0, TxPrePNCmdAddr}, - {BFAddrCmdDrvStren, BFCmdAddr1TxPreDriverCal2Pad1, BFAddrTxPreDriverCal2Pad4, 0, TxPrePNCmdAddr}, - {BFCsOdtDrvStren, BFCmdAddr0TxPreDriverCalPad0, BFCmdAddr0TxPreDriverCalPad0, 8, TxPrePNCmdAddr}, - {BFCkeDrvStren, BFAddrTxPreDriverCalPad0, BFAddrTxPreDriverCalPad0, 8, TxPrePNCmdAddr}, - {BFAddrCmdDrvStren, BFCmdAddr1TxPreDriverCalPad0, BFCmdAddr1TxPreDriverCalPad0, 8, TxPrePNCmdAddr}, - // 5. Program TxPreP/TxPreN for Clock according toTable 18 if VDDIO is 1.5V or Table 19 if 1.35V. - // A. Program D18F2x[1,0]9C_x0D0F_2[1:0]02={1000b, TxPreP, TxPreN}. - {BFClkDrvStren, BFClock0TxPreDriverCalPad0, BFClock1TxPreDriverCalPad0, 8, TxPrePNClock} - }; - - BIT_FIELD_NAME CurrentBitField; - UINT16 SpeedMask; - CONST UINT16 (*TxPrePNArray)[5]; - UINT8 Voltage; - UINT8 i; - UINT8 j; - UINT8 k; - UINT8 Dct; - - Dct = NBPtr->Dct; - NBPtr->SwitchDCT (NBPtr, 0); - // 1. Program D18F2x[1,0]9C_x0D0F_E003[DisAutoComp, DisablePreDriverCal] = {1b, 1b}. - MemNSetBitFieldNb (NBPtr, BFDisablePredriverCal, 0x6000); - NBPtr->SwitchDCT (NBPtr, Dct); - - SpeedMask = (UINT16) 1 << (NBPtr->DCTPtr->Timings.Speed / 66); - Voltage = (UINT8) CONVERT_VDDIO_TO_ENCODED (NBPtr->RefPtr->DDR3Voltage); - - for (j = 0; j < GET_SIZE_OF (PhyCompInitBitField); j ++) { - i = (UINT8) MemNGetBitFieldNb (NBPtr, PhyCompInitBitField[j].IndexBitField); - TxPrePNArray = PhyCompInitBitField[j].TxPrePN[Voltage]; - for (k = 0; k < 3; k ++) { - if ((TxPrePNArray[k][0] & SpeedMask) != 0) { - for (CurrentBitField = PhyCompInitBitField[j].StartTargetBitField; CurrentBitField <= PhyCompInitBitField[j].EndTargetBitField; CurrentBitField ++) { - MemNSetBitFieldNb (NBPtr, CurrentBitField, ((PhyCompInitBitField[j].ExtraValue << 12) | TxPrePNArray[k][i + 1])); - } - break; - } - } - ASSERT (k < 3); - } - - NBPtr->FamilySpecificHook[ForceAutoComp] (NBPtr, NBPtr); -} - -/*----------------------------------------------------------------------------- - * - * - * This function re-enable phy compensation. - * - * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK - * @param[in,out] OptParam - Optional parameter - * - * @return TRUE - * ---------------------------------------------------------------------------- - */ -BOOLEAN -MemNReEnablePhyCompNb ( - IN OUT MEM_NB_BLOCK *NBPtr, - IN OUT VOID *OptParam - ) -{ - UINT8 Dct; - - Dct = NBPtr->Dct; - - NBPtr->SwitchDCT (NBPtr, 0); - // Clear DisableCal and set DisablePredriverCal - MemNSetBitFieldNb (NBPtr, BFDisablePredriverCal, 0x2000); - NBPtr->SwitchDCT (NBPtr, Dct); - - return TRUE; -} - -/*----------------------------------------------------------------------------- - * - * - * This function calculates the value of WrDqDqsEarly and programs it into - * the DCT and adds it to the WrDqsGrossDelay of each byte lane on each - * DIMM of the channel. - * - * - * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK - * @param[in,out] OptParam - Optional parameter - * - * @return TRUE - * ---------------------------------------------------------------------------- - */ -BOOLEAN -MemNCalcWrDqDqsEarlyUnb ( - IN OUT MEM_NB_BLOCK *NBPtr, - IN OUT VOID *OptParam - ) -{ - MEM_TECH_BLOCK *TechPtr; - DCT_STRUCT *DCTPtr; - CH_DEF_STRUCT *ChannelPtr; - UINT8 Dimm; - UINT8 ByteLane; - UINT8 *WrDqsDlysPtr; - UINT8 WrDqDqsEarly; - - ASSERT ((NBPtr->IsSupported[WLSeedAdjust]) && (NBPtr->IsSupported[WLNegativeDelay])); - - TechPtr = NBPtr->TechPtr; - ChannelPtr = NBPtr->ChannelPtr; - DCTPtr = NBPtr->DCTPtr; - - ASSERT (NBPtr != NULL); - ASSERT (ChannelPtr != NULL); - ASSERT (DCTPtr != NULL); - // - // For each DIMM: - // - The Critical Gross Delay (CGD) is the minimum GrossDly of all byte lanes and all DIMMs. - // - If (CGD < 0) Then - // - D18F2xA8_dct[1:0][WrDqDqsEarly] = ABS(CGD) - // - WrDqsGrossDly = GrossDly + WrDqDqsEarly - // - Else - // - D18F2xA8_dct[1:0][WrDqDqsEarly] = 0. - // - WrDqsGrossDly = GrossDly - // - WrDqDqsEarly = 0; - if (TechPtr->WLCriticalDelay < 0) { - IDS_HDT_CONSOLE (MEM_FLOW, "\t\tCalculating WrDqDqsEarly, adjusting WrDqs.\n"); - // We've saved the entire negative delay value, so take the ABS and convert to GrossDly. - WrDqDqsEarly = (UINT8) (0x00FF &((((ABS (TechPtr->WLCriticalDelay)) + 0x1F) / 0x20))); - // - // Loop through All WrDqsDlys on all DIMMs - // - for (Dimm = 0; Dimm < MAX_DIMMS_PER_CHANNEL; Dimm++) { - if ((DCTPtr->Timings.CsEnabled & ((UINT16)3 << (Dimm << 1))) != 0) { - IDS_HDT_CONSOLE (MEM_FLOW, "\t\t\tDimm %x:", Dimm); - WrDqsDlysPtr = &(ChannelPtr->WrDqsDlys[(Dimm * TechPtr->DlyTableWidth ())]); - for (ByteLane = 0; ByteLane < TechPtr->DlyTableWidth (); ByteLane++) { - WrDqsDlysPtr[ByteLane] += (WrDqDqsEarly << 5); - NBPtr->SetTrainDly (NBPtr, AccessWrDqsDly, DIMM_BYTE_ACCESS (Dimm, ByteLane), WrDqsDlysPtr[ByteLane]); - IDS_HDT_CONSOLE (MEM_FLOW, " %02x", WrDqsDlysPtr[ByteLane]); - } - IDS_HDT_CONSOLE (MEM_FLOW, "\n"); - } - } - } - MemNSetBitFieldNb (NBPtr, BFWrDqDqsEarly, WrDqDqsEarly); - IDS_HDT_CONSOLE (MEM_FLOW, "\t\tWrDqDqsEarly : %02x\n", WrDqDqsEarly); - return TRUE; -} - -/*----------------------------------------------------------------------------- - * - * - * This function forces phy to M0 state - * - * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK - * @param[in,out] *OptParam - Optional parameter - * - * @return FALSE - always - * ---------------------------------------------------------------------------- - */ -BOOLEAN -MemNForcePhyToM0Unb ( - IN OUT MEM_NB_BLOCK *NBPtr, - IN OUT VOID *OptParam - ) -{ - // 1. Program D18F2x9C_x0D0F_E013_dct[1:0] = 0118h. - MemNBrdcstSetNb (NBPtr, BFPllRegWaitTime, 0x118); - // 2. Force the phy to M0 with the following sequence: - // A. Program D18F2x9C_x0D0F_E006_dct[1:0][PllLockTime] = 190h. Restore the default PLL lock time. - MemNBrdcstSetNb (NBPtr, BFPllLockTime, NBPtr->FreqChangeParam->PllLockTimeDefault); - // B. For each DCT: Program D18F2x9C_x0000_000B_dct[1:0] = 80800000h. - MemNBrdcstSetNb (NBPtr, BFDramPhyStatusReg, 0x80800000); - NBPtr->SwitchDCT (NBPtr, 0); - // C. Program D18F2x9C_x0D0F_E018_dct[0][PhyPSMasterChannel] = 0. - MemNSetBitFieldNb (NBPtr, BFPhyPSMasterChannel, 0); - // D. Program D18F2x9C_x0000_000B_dct[0] = 40000000h. CH0 only; - MemNSetBitFieldNb (NBPtr, BFDramPhyStatusReg, 0x40000000); - // E. For each DCT: Program D18F2x9C_x0000_000B_dct[1:0] = 80000000h. - MemNBrdcstSetNb (NBPtr, BFDramPhyStatusReg, 0x80000000); - - return FALSE; -} - -/*----------------------------------------------------------------------------- - * - * - * This function sets SkewMemClk before enabling MemClk - * - * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK - * @param[in,out] *OptParam - Optional parameter - * - * @return TRUE - always - * ---------------------------------------------------------------------------- - */ -BOOLEAN -MemNSetSkewMemClkUnb ( - IN OUT MEM_NB_BLOCK *NBPtr, - IN OUT VOID *OptParam - ) -{ - UINT8 Dct; - - // SkewMemClk is set to 1 if all DCTs are enabled, else 0. - for (Dct = 0; Dct < NBPtr->DctCount; Dct++) { - MemNSwitchDCTNb (NBPtr, Dct); - if (NBPtr->DCTPtr->Timings.DctMemSize == 0) { - break; - } - } - MemNSwitchDCTNb (NBPtr, 0); - if (Dct == NBPtr->DctCount) { - MemNSetBitFieldNb (NBPtr, BFSkewMemClk, 0x10); - } else { - MemNSetBitFieldNb (NBPtr, BFSkewMemClk, 0); - } - - return TRUE; -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * This function masks the RdDqsDly Bit 0 before writing to register for UNB. - * - * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK - * @param[in,out] *Offset - Bit offset of the field to be programmed - * - * @return TRUE - */ -BOOLEAN -MemNAdjustRdDqsDlyOffsetUnb ( - IN OUT MEM_NB_BLOCK *NBPtr, - IN OUT VOID *Offset - ) -{ - *(UINT16*) Offset = *(UINT16*) Offset + 1; - return TRUE; -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * - * This function delays MEMCLK to prevent WrDqs skew due to negative PRE result. - * - * - * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK - * @param[in,out] OptParam - Optional parameter - * - * @return TRUE - * ---------------------------------------------------------------------------- - */ -BOOLEAN -MemNCalcWrDqDqsEarlyClientNb ( - IN OUT MEM_NB_BLOCK *NBPtr, - IN OUT VOID *OptParam - ) -{ - MEM_TECH_BLOCK *TechPtr; - DCT_STRUCT *DCTPtr; - CH_DEF_STRUCT *ChannelPtr; - UINT8 Dimm; - UINT8 ByteLane; - UINT8 *WrDqsDlysPtr; - UINT8 NewClkDllDelay; - UINT16 ClkDllFineDly; - UINT32 AddrCmdTmg; - - TechPtr = NBPtr->TechPtr; - ChannelPtr = NBPtr->ChannelPtr; - DCTPtr = NBPtr->DCTPtr; - - ASSERT (NBPtr != NULL); - ASSERT (ChannelPtr != NULL); - ASSERT (DCTPtr != NULL); - - if (NBPtr->IsSupported[WLNegativeDelay]) { - if (TechPtr->WLCriticalDelay < 0) { - NewClkDllDelay = (UINT8) ABS (TechPtr->WLCriticalDelay); - - // Prepare new delay for MEMCLK - ClkDllFineDly = (UINT16) ((MemNGetBitFieldNb (NBPtr, BFPhyClkDllFine0) & 0x3F60) | NewClkDllDelay); - - // Program bit 7(FenceBit) = 1 if NewClkDllDelay >= > F2x9C[FenceThresholdTxPad], else 0. - ClkDllFineDly |= (NewClkDllDelay >= MemNGetBitFieldNb (NBPtr, BFPhyFence)) ? 0x80 : 0; - - // Apply new delay to both chiplets - MemNSetBitFieldNb (NBPtr, BFPhyClkDllFine0, ClkDllFineDly | 0x4000); - MemNSetBitFieldNb (NBPtr, BFPhyClkDllFine0, ClkDllFineDly); - MemNSetBitFieldNb (NBPtr, BFPhyClkDllFine1, ClkDllFineDly | 0x4000); - MemNSetBitFieldNb (NBPtr, BFPhyClkDllFine1, ClkDllFineDly); - IDS_HDT_CONSOLE (MEM_FLOW, "\n\t\tShift MemClk, AddrCmd, CsOdt, Cke by %d to eliminate negative WL\n", NewClkDllDelay); - - // - // Adjust AddrCmd/CsOdt/Cke timing by amount MemClk was delayed - // - AddrCmdTmg = MemNGetBitFieldNb (NBPtr, BFAddrTmgControl); - AddrCmdTmg += (NewClkDllDelay << 16) | (NewClkDllDelay << 8) | NewClkDllDelay; - AddrCmdTmg &= 0x003F3F3F; - MemNSetBitFieldNb (NBPtr, BFAddrTmgControl, AddrCmdTmg); - - // - // Adjust all WrDqsDlys on all DIMMs of the current channel - // - for (Dimm = 0; Dimm < MAX_DIMMS_PER_CHANNEL; Dimm++) { - if ((DCTPtr->Timings.CsEnabled & ((UINT16)3 << (Dimm << 1))) != 0) { - IDS_HDT_CONSOLE (MEM_FLOW, "\t\tCS%d\n\t\t\tWrDqs:", Dimm << 1); - WrDqsDlysPtr = &(ChannelPtr->WrDqsDlys[(Dimm * TechPtr->DlyTableWidth ())]); - for (ByteLane = 0; ByteLane < 8; ByteLane++) { - WrDqsDlysPtr[ByteLane] = (UINT8) (WrDqsDlysPtr[ByteLane] + NewClkDllDelay); - NBPtr->SetTrainDly (NBPtr, AccessWrDqsDly, DIMM_BYTE_ACCESS (Dimm, ByteLane), WrDqsDlysPtr[ByteLane]); - IDS_HDT_CONSOLE (MEM_FLOW, " %02x", WrDqsDlysPtr[ByteLane]); - } - IDS_HDT_CONSOLE (MEM_FLOW, "\n"); - } - } - } - } - - return TRUE; -} -/* -----------------------------------------------------------------------------*/ -/** - * - * - * This function initializes RxEn Delays for RxEn seedless training - * - * - * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK - * @param[in,out] OptParam - Optional parameter - * - * @return TRUE - * ---------------------------------------------------------------------------- - */ -BOOLEAN -MemNInitializeRxEnSeedlessTrainingUnb ( - IN OUT MEM_NB_BLOCK *NBPtr, - IN OUT VOID *OptParam - ) -{ - UINT8 ByteLane; - // Save original PRE based RxEnDly for RxEn Seedless training - for (ByteLane = 0; ByteLane < (NBPtr->MCTPtr->Status[SbEccDimms] ? 9 : 8); ByteLane++) { - NBPtr->TechPtr->RxOrig[ByteLane] = NBPtr->ChannelPtr->RcvEnDlys[(NBPtr->TechPtr->ChipSel >> 1) * NBPtr->TechPtr->DlyTableWidth () + ByteLane]; - } - return TRUE; -} -/*----------------------------------------------------------------------------- - * - * - * This function checks each bytelane for no window error. - * - * - * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK - * @param[in,out] OptParam - Optional parameter - * - * @return TRUE - * ---------------------------------------------------------------------------- - */ -BOOLEAN -MemNTrackRxEnSeedlessRdWrNoWindBLErrorUnb ( - IN OUT MEM_NB_BLOCK *NBPtr, - IN OUT VOID *OptParam - ) -{ - MemTTrackRxEnSeedlessRdWrNoWindBLError (NBPtr->TechPtr, OptParam); - return TRUE; -} -/*----------------------------------------------------------------------------- - * - * - * This function checks each bytelane for small window error. - * - * - * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK - * @param[in,out] OptParam - Optional parameter - * - * @return TRUE - * ---------------------------------------------------------------------------- - */ -BOOLEAN -MemNTrackRxEnSeedlessRdWrSmallWindBLErrorUnb ( - IN OUT MEM_NB_BLOCK *NBPtr, - IN OUT VOID *OptParam - ) -{ - MemTTrackRxEnSeedlessRdWrSmallWindBLError (NBPtr->TechPtr, OptParam); - return TRUE; -} -/*----------------------------------------------------------------------------- - * - * - * This function initializes a ByteLaneError error. - * - * - * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK - * @param[in,out] OptParam - Optional parameter - * - * @return TRUE - * ---------------------------------------------------------------------------- - */ -BOOLEAN -MemNInitialzeRxEnSeedlessByteLaneErrorUnb ( - IN OUT MEM_NB_BLOCK *NBPtr, - IN OUT VOID *OptParam - ) -{ - UINT8 ByteLane; - for (ByteLane = 0; ByteLane < (NBPtr->MCTPtr->Status[SbEccDimms] ? 9 : 8); ByteLane++) { - NBPtr->TechPtr->ByteLaneError[ByteLane] = FALSE; // All Bytelanes have no errors - } - return TRUE; -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * - * This function sets phy power saving related settings in different MPstate context. - * - * - * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK - * - * @return none - * ---------------------------------------------------------------------------- - */ -VOID -MemNPhyPowerSavingMPstateUnb ( - IN OUT MEM_NB_BLOCK *NBPtr - ) -{ - STATIC UINT8 Sequence[] = {8, 4, 3, 5, 2, 6, 1, 7, 0}; - UINT16 DllPower[9]; - UINT8 NumLanes; - UINT8 DllWakeTime; - UINT8 MaxRxStggrDly; - UINT8 MinRcvEnGrossDly; - UINT8 MinWrDatGrossDly; - UINT8 dRxStggrDly; - UINT8 dTxStggrDly; - UINT8 TempStggrDly; - UINT8 MaxTxStggrDly; - UINT8 Tcwl; - UINT8 i; - - IDS_HDT_CONSOLE (MEM_FLOW, "Start Phy power saving setting for memory Pstate %d\n", NBPtr->MemPstate); - // 4. Program D18F2x9C_x0D0F_0[F,8:0]13_dct[1:0][DllDisEarlyU] = 1b. - // 5. Program D18F2x9C_x0D0F_0[F,8:0]13_dct[1:0][DllDisEarlyL] = 1b. - // 6. D18F2x9C_x0D0F_0[F,7:0][53,13]_dct[1:0][RxDqsUDllPowerDown] = 1. - MemNSetBitFieldNb (NBPtr, BFPhy0x0D0F0F13, MemNGetBitFieldNb (NBPtr, BFPhy0x0D0F0F13) | 0x83); - // 7. D18F2x9C_x0D0F_812F_dct[1:0][PARTri] = ~D18F2x90_dct[1:0][ParEn]. - // 8. D18F2x9C_x0D0F_812F_dct[1:0][Add17Tri, Add16Tri] = {1b, 1b} - if (NBPtr->MemPstate == MEMORY_PSTATE0) { - MemNSetBitFieldNb (NBPtr, BFAddrCmdTri, MemNGetBitFieldNb (NBPtr, BFAddrCmdTri) | 0xA1); - } - // 9. IF (DimmsPopulated == 1) THEN - // program D18F2x9C_x0D0F_C0[40,00]_dct[1:0][LowPowerDrvStrengthEn] = 1 - // ELSE program D18F2x9C_x0D0F_C0[40,00]_dct[1:0][LowPowerDrvStrengthEn] = 0 ENDIF. - if (NBPtr->ChannelPtr->Dimms == 1) { - MemNSetBitFieldNb (NBPtr, BFLowPowerDrvStrengthEn, 0x100); - } - // 10. Program D18F2x9C_x0D0F_0[F,7:0][50,10]_dct[1:0][EnRxPadStandby] = IF - // (D18F2x94_dct[1:0][MemClkFreq] <= 800 MHz) THEN 1 ELSE 0 ENDIF. - MemNSetBitFieldNb (NBPtr, BFEnRxPadStandby, (NBPtr->DCTPtr->Timings.Speed <= DDR1600_FREQUENCY) ? 0x1000 : 0); - // 11. Program D18F2x9C_x0000_000D_dct[1:0]_mp[1:0] as follows: - // If (DDR rate < = 1600) TxMaxDurDllNoLock = RxMaxDurDllNoLock = 8h - // else TxMaxDurDllNoLock = RxMaxDurDllNoLock = 7h. - if (NBPtr->DCTPtr->Timings.Speed <= DDR1600_FREQUENCY) { - MemNSetBitFieldNb (NBPtr, BFTxMaxDurDllNoLock, 8); - MemNSetBitFieldNb (NBPtr, BFRxMaxDurDllNoLock, 8); - } else { - MemNSetBitFieldNb (NBPtr, BFTxMaxDurDllNoLock, 7); - MemNSetBitFieldNb (NBPtr, BFRxMaxDurDllNoLock, 7); - } - // TxCPUpdPeriod = RxCPUpdPeriod = 000b. - MemNSetBitFieldNb (NBPtr, BFTxCPUpdPeriod, 0); - MemNSetBitFieldNb (NBPtr, BFRxCPUpdPeriod, 0); - // TxDLLWakeupTime = RxDLLWakeupTime = 11b. - MemNSetBitFieldNb (NBPtr, BFTxDLLWakeupTime, 3); - MemNSetBitFieldNb (NBPtr, BFRxDLLWakeupTime, 3); - // 12. Program D18F2x9C_x0D0F_0[F,7:0][5C,1C]_dct[1:0] as follows. - // Let Numlanes = 8. = 9 with ECC. - NumLanes = (NBPtr->MCTPtr->Status[SbEccDimms] && NBPtr->IsSupported[EccByteTraining]) ? 9 : 8; - // RxDllStggrEn = TxDllStggrEn = 1. - for (i = 0; i < 9; i ++) { - DllPower[i] = 0x8080; - } - // If (DDR rate > = 1866) DllWakeTime = 1, Else DllWakeTime = 0. - DllWakeTime = (NBPtr->DCTPtr->Timings.Speed >= DDR1866_FREQUENCY) ? 1 : 0; - // Let MaxRxStggrDly = (Tcl*2) + MIN(DqsRcvEnGrossDelay for all byte lanes (see D18F2x9C_x0000_00[2A:10]_dct[1:0]_mp[1:0])) - 4. - MinRcvEnGrossDly = NBPtr->TechPtr->GetMinMaxGrossDly (NBPtr->TechPtr, AccessRcvEnDly, FALSE); - ASSERT ((NBPtr->DCTPtr->Timings.CasL * 2 + MinRcvEnGrossDly) >= 4); - MaxRxStggrDly = NBPtr->DCTPtr->Timings.CasL * 2 + MinRcvEnGrossDly - 4; - // Let (real) dRxStggrDly = (MaxRxStggrDly - DllWakeTime) / (Numlanes - 1). - ASSERT (MaxRxStggrDly >= DllWakeTime); - dRxStggrDly = (MaxRxStggrDly - DllWakeTime) / (NumLanes - 1); - IDS_HDT_CONSOLE (MEM_FLOW, "\tMinimum RcvEnGrossDly: 0x%02x MaxRxStggrDly: 0x%02x dRxStggrDly: 0x%02x\n", MinRcvEnGrossDly, MaxRxStggrDly, dRxStggrDly); - // For each byte lane in the ordered sequence {8, 4, 3, 5, 2, 6, 1, 7, 0}, program RxDllStggrDly[5:0] = an - // increasing value, starting with 0 for the first byte lane in the sequence and increasing at a rate of dRxStggrDly - // for each subsequent byte lane. Convert the real to integer by rounding down or using C (int) typecast after linearization. - i = 9 - NumLanes; - TempStggrDly = 0; - for (; i < 9; i ++) { - DllPower[Sequence[i]] |= ((TempStggrDly & 0x3F) << 8); - TempStggrDly = TempStggrDly + dRxStggrDly; - } - - // Let MaxTxStggrDly = (Tcwl*2) + MIN(MIN (WrDatGrossDly for all byte lanes (see - // D18F2x9C_x0000_0[3:0]0[2:1]_dct[1:0]_mp[1:0])), MIN(DqsRcvEnGrossDelay for all byte lanes (see - // D18F2x9C_x0000_00[2A:10]_dct[1:0]_mp[1:0])) - 4. - Tcwl = (UINT8) MemNGetBitFieldNb (NBPtr, BFTcwl); - MinWrDatGrossDly = NBPtr->TechPtr->GetMinMaxGrossDly (NBPtr->TechPtr, AccessWrDatDly, FALSE); - MaxTxStggrDly = Tcwl * 2 + MIN (MinRcvEnGrossDly, MinWrDatGrossDly) - 4; - // Let dTxStggrDly = (MaxTxStggrDly - DllWakeTime) / (Numlanes - 1). - ASSERT (MaxTxStggrDly >= DllWakeTime); - dTxStggrDly = (MaxTxStggrDly - DllWakeTime) / (NumLanes - 1); - // For each byte lane in the ordered sequence {8, 4, 3, 5, 2, 6, 1, 7, 0}, program TxDllStggrDly[5:0] = an - // increasing integer value, starting with 0 for the first byte lane in the sequence and increasing at a rate of - // dTxStggrDly for each subsequent byte lane. - IDS_HDT_CONSOLE (MEM_FLOW, "\tMinimum WrDatGrossDly: 0x%02x MaxTxStggrDly: 0x%02x dTxStggrDly: 0x%02x\n", MinWrDatGrossDly, MaxTxStggrDly, dTxStggrDly); - i = 9 - NumLanes; - TempStggrDly = 0; - for (; i < 9; i ++) { - DllPower[Sequence[i]] |= (TempStggrDly & 0x3F); - TempStggrDly = TempStggrDly + dTxStggrDly; - } - - IDS_HDT_CONSOLE (MEM_FLOW, "\t\t\t\tByte Lane : ECC 07 06 05 04 03 02 01 00\n"); - IDS_HDT_CONSOLE (MEM_FLOW, "\t\t\t\tDll Power : %04x %04x %04x %04x %04x %04x %04x %04x %04x\n", - DllPower[8], DllPower[7], DllPower[6], DllPower[5], DllPower[4], DllPower[3], DllPower[2], DllPower[1], DllPower[0]); - - for (i = 0; i < NumLanes; i ++) { - MemNSetBitFieldNb (NBPtr, BFDataByteDllPowerMgnByte0 + i, ((MemNGetBitFieldNb (NBPtr, BFDataByteDllPowerMgnByte0 + i) & 0x4040) | DllPower[i])); - } - // 13. Program D18F2x248_dct[1:0]_mp[1:0] and then D18F2x9C_x0D0F_0[F,7:0][53,13]_dct[1:0] as follows: - // For M1 context program RxChMntClkEn=RxSsbMntClkEn=0. - // For M0 context program RxChMntClkEn=RxSsbMntClkEn=1. - if (NBPtr->MemPstate == MEMORY_PSTATE1) { - MemNSetBitFieldNb (NBPtr, BFRxChMntClkEn, 0); - MemNSetBitFieldNb (NBPtr, BFRxSsbMntClkEn, 0); - } else { - MemNSetBitFieldNb (NBPtr, BFRxChMntClkEn, 1); - MemNSetBitFieldNb (NBPtr, BFRxSsbMntClkEn, 0x100); - } - - IDS_OPTION_HOOK (IDS_PHY_DLL_STANDBY_CTRL, NBPtr, &NBPtr->MemPtr->StdHeader); -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * This function resets RxFifo pointer during Read DQS training - * - * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK - * @param[in,out] *OptParam - Optional parameter - * - * @return TRUE - */ - -BOOLEAN -MemNResetRxFifoPtrClientNb ( - IN OUT MEM_NB_BLOCK *NBPtr, - IN OUT VOID *OptParam - ) -{ - if (NBPtr->TechPtr->Direction == DQS_READ_DIR) { - MemNSetBitFieldNb (NBPtr, BFRxPtrInitReq, 1); - MemNPollBitFieldNb (NBPtr, BFRxPtrInitReq, 0, PCI_ACCESS_TIMEOUT, FALSE); - } - return TRUE; -} - diff --git a/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/mnreg.c b/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/mnreg.c deleted file mode 100644 index abbc7515ea..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/mnreg.c +++ /dev/null @@ -1,514 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * mnreg.c - * - * Common Northbridge register access functions - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: (Mem/NB/) - * @e \$Revision: 49210 $ @e \$Date: 2011-03-19 06:56:00 +0800 (Sat, 19 Mar 2011) $ - * - **/ -/***************************************************************************** -* -* Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* *************************************************************************** -* -*/ -/* - *---------------------------------------------------------------------------- - * MODULES USED - * - *---------------------------------------------------------------------------- - */ - - - -#include "AGESA.h" -#include "AdvancedApi.h" -#include "amdlib.h" -#include "Ids.h" -#include "mm.h" -#include "mn.h" -#include "merrhdl.h" -#include "heapManager.h" -#include "Filecode.h" -#include "GeneralServices.h" -CODE_GROUP (G1_PEICC) -RDATA_GROUP (G1_PEICC) - -#define FILECODE PROC_MEM_NB_MNREG_FILECODE - - -/*---------------------------------------------------------------------------- - * DEFINITIONS AND MACROS - * - *---------------------------------------------------------------------------- - */ -/*---------------------------------------------------------------------------- - * TYPEDEFS AND STRUCTURES - * - *---------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------- - * PROTOTYPES OF LOCAL FUNCTIONS - * - *---------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------- - * EXPORTED FUNCTIONS - * - *---------------------------------------------------------------------------- - */ - -/* -----------------------------------------------------------------------------*/ -/** - * - * - * This function sets the current DCT to work on. - * Should be called before accessing a certain DCT - * All data structures will be updated to point to the current DCT - * - * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK - * @param[in] Dct - ID of the target DCT - * - */ - -VOID -MemNSwitchDCTNb ( - IN OUT MEM_NB_BLOCK *NBPtr, - IN UINT8 Dct - ) -{ - ASSERT (NBPtr->DctCount > Dct); - // - // Set the DctCfgSel to new DCT - // - NBPtr->FamilySpecificHook[DCTSelectSwitch] (NBPtr, &Dct); - NBPtr->Dct = Dct ? 1 : 0; - NBPtr->MCTPtr->Dct = NBPtr->Dct; - NBPtr->DCTPtr = &(NBPtr->MCTPtr->DctData[NBPtr->Dct]); - NBPtr->PsPtr = &(NBPtr->PSBlock[NBPtr->Dct]); - NBPtr->DctCachePtr = &(NBPtr->DctCache[NBPtr->Dct]); - - MemNSwitchChannelNb (NBPtr, NBPtr->Channel); -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * This function is used by families that use a separate DctCfgSel bit to - * select the current DCT which will be accessed by function 2. - * NOTE: This function must be called BEFORE the NBPtr->Dct variable is - * updated. - * - * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK - * @param[in] *Dct - Pointer to ID of the target DCT - * - */ - -BOOLEAN -MemNDctCfgSelectUnb ( - IN OUT MEM_NB_BLOCK *NBPtr, - IN VOID *Dct - ) -{ - // - // Sanity check the current DctCfgSel setting - // - ASSERT (NBPtr->Dct == NBPtr->GetBitField (NBPtr, BFDctCfgSel)); - // - // Set the DctCfgSel to new DCT - // - NBPtr->SetBitField (NBPtr, BFDctCfgSel, *(UINT8*)Dct); - - return TRUE; -} - - -/* -----------------------------------------------------------------------------*/ -/** - * - * - * This function sets the current channel to work on. - * Should be called before accessing a certain channel - * All data structures will be updated to point to the current channel - * - * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK - * @param[in] Channel - ID of the target channel - * - */ - -VOID -MemNSwitchChannelNb ( - IN OUT MEM_NB_BLOCK *NBPtr, - IN UINT8 Channel - ) -{ - NBPtr->Channel = Channel ? 1 : 0; - NBPtr->ChannelPtr = &(NBPtr->DCTPtr->ChData[NBPtr->Channel]); -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * - * This function gets a bit field from PCI register - * - * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK - * @param[in] FieldName - Field name - * - * @return Bit field value - */ - -UINT32 -MemNGetBitFieldNb ( - IN OUT MEM_NB_BLOCK *NBPtr, - IN BIT_FIELD_NAME FieldName - ) -{ - UINT32 Value; - - ASSERT (FieldName < BFEndOfList); - Value = NBPtr->MemNCmnGetSetFieldNb (NBPtr, 0, FieldName, 0); - return Value; -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * - * This function sets a bit field from PCI register - * - * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK - * @param[in] FieldName - Field name - * @param[in] Field - Value to be stored in PCT register - * - */ - -VOID -MemNSetBitFieldNb ( - IN OUT MEM_NB_BLOCK *NBPtr, - IN BIT_FIELD_NAME FieldName, - IN UINT32 Field - ) -{ - ASSERT (FieldName < BFEndOfList); - NBPtr->MemNCmnGetSetFieldNb (NBPtr, 1, FieldName, Field); -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * Check if bitfields of all enabled DCTs on a die have the expected value. Ignore - * DCTs that are disabled. - * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK - * @param[in] FieldName - Bit Field name - * @param[in] Field - Value to be checked - * - * @return TRUE - All enabled DCTs have the expected value on the bitfield. - * @return FALSE - Not all enabled DCTs have the expected value on the bitfield. - * - * ---------------------------------------------------------------------------- - */ -BOOLEAN -MemNBrdcstCheckNb ( - IN OUT MEM_NB_BLOCK *NBPtr, - IN BIT_FIELD_NAME FieldName, - IN UINT32 Field - ) -{ - UINT8 Dct; - UINT8 CurrentDCT; - Dct = NBPtr->Dct; - for (CurrentDCT = 0; CurrentDCT < NBPtr->DctCount; CurrentDCT++) { - MemNSwitchDCTNb (NBPtr, CurrentDCT); - if ((NBPtr->DCTPtr->Timings.DctMemSize != 0) && !((CurrentDCT == 1) && NBPtr->Ganged)) { - if (MemNGetBitFieldNb (NBPtr, FieldName) != Field) { - MemNSwitchDCTNb (NBPtr, Dct); - return FALSE; - } - } - } - MemNSwitchDCTNb (NBPtr, Dct); - return TRUE; -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * Set bitfields of all enabled DCTs on a die to a value. Ignore - * DCTs that are disabled. - * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK - * @param[in] FieldName - Bit Field name - * @param[in] Field - Value to be set - * - * ---------------------------------------------------------------------------- - */ -VOID -MemNBrdcstSetNb ( - IN OUT MEM_NB_BLOCK *NBPtr, - IN BIT_FIELD_NAME FieldName, - IN UINT32 Field - ) -{ - UINT8 Dct; - UINT8 CurrentDCT; - Dct = NBPtr->Dct; - for (CurrentDCT = 0; CurrentDCT < NBPtr->DctCount; CurrentDCT++) { - MemNSwitchDCTNb (NBPtr, CurrentDCT); - if ((NBPtr->DCTPtr->Timings.DctMemSize != 0) && !((CurrentDCT == 1) && NBPtr->Ganged)) { - MemNSetBitFieldNb (NBPtr, FieldName, Field); - } - } - MemNSwitchDCTNb (NBPtr, Dct); -} - -/*-----------------------------------------------------------------------------*/ -/** - * This function calculates the memory channel index relative to the - * socket, taking the Die number, the Dct, and the channel. - * - * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK - * @param[in] Dct - * @param[in] Channel - * - */ -UINT8 -MemNGetSocketRelativeChannelNb ( - IN OUT MEM_NB_BLOCK *NBPtr, - IN UINT8 Dct, - IN UINT8 Channel - ) -{ - return ((NBPtr->MCTPtr->DieId * NBPtr->DctCount) + Dct); -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * Poll a bitfield. If the bitfield does not get set to the target value within - * specified microseconds, it times out. - * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK - * @param[in] FieldName - Bit Field name - * @param[in] Field - Value to be set - * @param[in] MicroSecond - Number of microsecond to wait - * @param[in] IfBroadCast - Need to broadcast to both DCT or not - * - * ---------------------------------------------------------------------------- - */ -VOID -MemNPollBitFieldNb ( - IN OUT MEM_NB_BLOCK *NBPtr, - IN BIT_FIELD_NAME FieldName, - IN UINT32 Field, - IN UINT32 MicroSecond, - IN BOOLEAN IfBroadCast - ) -{ - UINT8 ExcludeDCT; - UINT16 ExcludeChipSelMask; - UINT32 EventInfo; - UINT64 InitTSC; - UINT64 CurrentTSC; - UINT64 TimeOut; - AGESA_STATUS EventClass; - MEM_DATA_STRUCT *MemPtr; - DIE_STRUCT *MCTPtr; - BOOLEAN TimeoutEn; - - MemPtr = NBPtr->MemPtr; - MCTPtr = NBPtr->MCTPtr; - ExcludeDCT = EXCLUDE_ALL_DCT; - ExcludeChipSelMask = EXCLUDE_ALL_CHIPSEL; - TimeoutEn = TRUE; - IDS_TIMEOUT_CTL (&TimeoutEn); - - CurrentTSC = 0; - LibAmdMsrRead (TSC, &InitTSC, &MemPtr->StdHeader); - TimeOut = InitTSC + ((UINT64) MicroSecond * MemPtr->TscRate); - - while ((CurrentTSC < TimeOut) || !TimeoutEn) { - if (IfBroadCast) { - if (NBPtr->BrdcstCheck (NBPtr, FieldName, Field)) { - break; - } - } else { - if (MemNGetBitFieldNb (NBPtr, FieldName) == Field) { - break; - } - } - LibAmdMsrRead (TSC, &CurrentTSC, &MemPtr->StdHeader); - } - - if ((CurrentTSC >= TimeOut) && TimeoutEn) { - // Default event class - // If different event class is needed in one entry, override it. - EventClass = AGESA_ERROR; - switch (FieldName) { - case BFDramEnabled: - EventInfo = MEM_ERROR_DRAM_ENABLED_TIME_OUT; - break; - case BFDctAccessDone: - EventInfo = MEM_ERROR_DCT_ACCESS_DONE_TIME_OUT; - ExcludeDCT = NBPtr->Dct; - break; - case BFSendCtrlWord: - EventInfo = MEM_ERROR_SEND_CTRL_WORD_TIME_OUT; - ExcludeDCT = NBPtr->Dct; - break; - case BFPrefDramTrainMode: - EventInfo = MEM_ERROR_PREF_DRAM_TRAIN_MODE_TIME_OUT; - ExcludeDCT = NBPtr->Dct; - break; - case BFEnterSelfRef: - EventInfo = MEM_ERROR_ENTER_SELF_REF_TIME_OUT; - break; - case BFFreqChgInProg: - EventInfo = MEM_ERROR_FREQ_CHG_IN_PROG_TIME_OUT; - ExcludeDCT = NBPtr->Dct; - break; - case BFExitSelfRef: - EventInfo = MEM_ERROR_EXIT_SELF_REF_TIME_OUT; - break; - case BFSendMrsCmd: - EventInfo = MEM_ERROR_SEND_MRS_CMD_TIME_OUT; - ExcludeDCT = NBPtr->Dct; - break; - case BFSendZQCmd: - EventInfo = MEM_ERROR_SEND_ZQ_CMD_TIME_OUT; - ExcludeDCT = NBPtr->Dct; - break; - case BFDctExtraAccessDone: - EventInfo = MEM_ERROR_DCT_EXTRA_ACCESS_DONE_TIME_OUT; - ExcludeDCT = NBPtr->Dct; - break; - case BFMemClrBusy: - EventInfo = MEM_ERROR_MEM_CLR_BUSY_TIME_OUT; - break; - case BFMemCleared: - EventInfo = MEM_ERROR_MEM_CLEARED_TIME_OUT; - break; - case BFFlushWr: - EventInfo = MEM_ERROR_FLUSH_WR_TIME_OUT; - ExcludeDCT = NBPtr->Dct; - break; - default: - EventClass = 0; - EventInfo = 0; - IDS_ERROR_TRAP; - } - - PutEventLog (EventClass, EventInfo, NBPtr->Node, NBPtr->Dct, NBPtr->Channel, 0, &MemPtr->StdHeader); - SetMemError (EventClass, MCTPtr); - MemPtr->ErrorHandling (MCTPtr, ExcludeDCT, ExcludeChipSelMask, &MemPtr->StdHeader); - } -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * - * This function changes memory Pstate context - * - * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK - * @param[in] MemPstate - Target Memory Pstate - * - * @return TRUE - * ---------------------------------------------------------------------------- - */ -VOID -MemNChangeMemPStateContextNb ( - IN OUT MEM_NB_BLOCK *NBPtr, - IN MEM_PSTATE MemPstate - ) -{ - UINT8 PSMasterChannel; - UINT8 Dct; - - ASSERT ((MemPstate == 0) || (MemPstate == 1)); - ASSERT (NBPtr->MemPstate == ((MemNGetBitFieldNb (NBPtr, BFMemPsSel) == 0) ? MEMORY_PSTATE0 : MEMORY_PSTATE1)); - - IDS_HDT_CONSOLE (MEM_FLOW, "\nGo to Memory Pstate Conext %d\n", MemPstate); - Dct = NBPtr->Dct; - MemNSwitchDCTNb (NBPtr, 0); - // Figure out what is the master channel - PSMasterChannel = (UINT8) (MemNGetBitFieldNb (NBPtr, BFPhyPSMasterChannel) >> 8); - - // Switch to the master channel to change PStateToAccess - // PStateToAccess is only effective on the master channel - MemNSwitchDCTNb (NBPtr, PSMasterChannel); - MemNSetBitFieldNb (NBPtr, BFMemPsSel, MemPstate); - MemNSetBitFieldNb (NBPtr, BFPStateToAccess, MemPstate << 8); - - NBPtr->MemPstate = (MemPstate == 0) ? MEMORY_PSTATE0 : MEMORY_PSTATE1; - MemNSwitchDCTNb (NBPtr, Dct); -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * This function allocates buffer for NB register table - * - * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK - * @param[in] Handle - Handle for heap allocation for NBRegTable - * - * @return TRUE - Successfully allocates buffer the first time - * @return FALSE - Buffer already allocated or fails to allocate - */ - -BOOLEAN -MemNAllocateNBRegTableNb ( - IN OUT MEM_NB_BLOCK *NBPtr, - IN NB_REG_TAB_HANDLE Handle - ) -{ - ALLOCATE_HEAP_PARAMS AllocHeapParams; - LOCATE_HEAP_PTR LocHeap; - - // If NBRegTable for this family exists, use it - LocHeap.BufferHandle = GENERATE_MEM_HANDLE (ALLOC_NB_REG_TABLE, Handle, 0, 0); - if (HeapLocateBuffer (&LocHeap, &(NBPtr->MemPtr->StdHeader)) == AGESA_SUCCESS) { - NBPtr->NBRegTable = (TSEFO *) LocHeap.BufferPtr; - return FALSE; - } - - // Allocate new buffer for NBRegTable if it has not been allocated - AllocHeapParams.RequestedBufferSize = sizeof (TSEFO) * BFEndOfList; - AllocHeapParams.BufferHandle = GENERATE_MEM_HANDLE (ALLOC_NB_REG_TABLE, Handle, 0, 0); - AllocHeapParams.Persist = HEAP_SYSTEM_MEM; - if (AGESA_SUCCESS != HeapAllocateBuffer (&AllocHeapParams, &(NBPtr->MemPtr->StdHeader))) { - ASSERT(FALSE); // NB and Tech Block Heap allocate error - return FALSE; - } - NBPtr->NBRegTable = (TSEFO *)AllocHeapParams.BufferPtr; - return TRUE; -} diff --git a/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/mntrain2.c b/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/mntrain2.c deleted file mode 100644 index 8e7c9b8892..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/mntrain2.c +++ /dev/null @@ -1,131 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * mntrain2.c - * - * Common Northbridge function for training flow for DDR2 - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: (Mem/NB) - * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $ - * - **/ -/***************************************************************************** -* -* Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* *************************************************************************** -* -*/ - -/* - *---------------------------------------------------------------------------- - * MODULES USED - * - *---------------------------------------------------------------------------- - */ - - - -#include "AGESA.h" -#include "amdlib.h" -#include "Ids.h" -#include "OptionMemory.h" -#include "mm.h" -#include "mn.h" -#include "mt.h" -#include "Filecode.h" -CODE_GROUP (G1_PEICC) -RDATA_GROUP (G1_PEICC) - -#define FILECODE PROC_MEM_NB_MNTRAIN2_FILECODE -/* features */ -#include "mftds.h" -/*---------------------------------------------------------------------------- - * DEFINITIONS AND MACROS - * - *---------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------- - * TYPEDEFS AND STRUCTURES - * - *---------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------- - * PROTOTYPES OF LOCAL FUNCTIONS - * - *---------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------- - * EXPORTED FUNCTIONS - * - *---------------------------------------------------------------------------- - */ -extern MEM_TECH_FEAT_BLOCK memTechTrainingFeatDDR2; - -/* -----------------------------------------------------------------------------*/ -/** - * - * This function initiates DQS training - * - * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK - * - */ - -BOOLEAN -MemNDQSTiming2Nb ( - IN OUT MEM_NB_BLOCK *NBPtr - ) -{ - MEM_TECH_BLOCK *TechPtr; - - TechPtr = NBPtr->TechPtr; - if (TechPtr->NBPtr->MCTPtr->NodeMemSize) { - AGESA_TESTPOINT (TpProcMemBeforeAgesaHookBeforeDQSTraining, &NBPtr->MemPtr->StdHeader); - AgesaHookBeforeDQSTraining (NBPtr->MCTPtr->SocketId, TechPtr->NBPtr->MemPtr); - AGESA_TESTPOINT (TpProcMemAfterAgesaHookBeforeDQSTraining, &NBPtr->MemPtr->StdHeader); - //Execute Technology specific training features - if (memTechTrainingFeatDDR2.NonOptimizedSWDQSRecEnTrainingPart1 (TechPtr)) { - if (memTechTrainingFeatDDR2.OptimizedSwDqsRecEnTrainingPart1 (TechPtr)) { - MemFInitTableDrive (NBPtr, MTAfterSwRxEnTrn); - if (memTechTrainingFeatDDR2.NonOptimizedSRdWrPosTraining (TechPtr)) { - if (memTechTrainingFeatDDR2.OptimizedSRdWrPosTraining (TechPtr)) { - MemFInitTableDrive (NBPtr, MTAfterDqsRwPosTrn); - if (memTechTrainingFeatDDR2.MaxRdLatencyTraining (TechPtr)) { - MemFInitTableDrive (NBPtr, MTAfterMaxRdLatTrn); - } - } - } - } - } - MemTMarkTrainFail (TechPtr); - } - return TRUE; -} diff --git a/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/mntrain3.c b/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/mntrain3.c deleted file mode 100644 index a161b2cd25..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/mntrain3.c +++ /dev/null @@ -1,239 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * mntrain3.c - * - * Common Northbridge function for training flow for DDR3 - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: (Mem/NB) - * @e \$Revision: 45375 $ @e \$Date: 2011-01-15 12:01:53 +0800 (Sat, 15 Jan 2011) $ - * - **/ -/***************************************************************************** -* -* Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* *************************************************************************** -* -*/ - -/* - *---------------------------------------------------------------------------- - * MODULES USED - * - *---------------------------------------------------------------------------- - */ - - - -#include "AGESA.h" -#include "amdlib.h" -#include "Ids.h" -#include "OptionMemory.h" -#include "mm.h" -#include "mn.h" -#include "mt.h" -#include "Filecode.h" -CODE_GROUP (G1_PEICC) -RDATA_GROUP (G1_PEICC) - -#define FILECODE PROC_MEM_NB_MNTRAIN3_FILECODE -/* features */ -#include "mftds.h" -/*---------------------------------------------------------------------------- - * DEFINITIONS AND MACROS - * - *---------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------- - * TYPEDEFS AND STRUCTURES - * - *---------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------- - * PROTOTYPES OF LOCAL FUNCTIONS - * - *---------------------------------------------------------------------------- - */ - -BOOLEAN -STATIC -MemNHwWlPart2Nb ( - IN OUT MEM_TECH_BLOCK *TechPtr - ); -/*---------------------------------------------------------------------------- - * EXPORTED FUNCTIONS - * - *---------------------------------------------------------------------------- - */ -extern MEM_FEAT_TRAIN_SEQ memTrainSequenceDDR3[]; -/* -----------------------------------------------------------------------------*/ -/** - * - * This function initiates DQS training - * - * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK - * - */ - -BOOLEAN -MemNDQSTiming3Nb ( - IN OUT MEM_NB_BLOCK *NBPtr - ) -{ - MEM_TECH_BLOCK *TechPtr; - UINT8 i; - BOOLEAN Retval; - TechPtr = NBPtr->TechPtr; - Retval = TRUE; - if (TechPtr->NBPtr->MCTPtr->NodeMemSize) { - //Execute Technology specific training features - i = 0; - while (memTrainSequenceDDR3[i].TrainingSequenceEnabled != 0) { - if (memTrainSequenceDDR3[i].TrainingSequenceEnabled (NBPtr)) { - NBPtr->TrainingSequenceIndex = i; - Retval = memTrainSequenceDDR3[i].TrainingSequence (NBPtr); - break; - } - i++; - } - } - return Retval; -} -/* -----------------------------------------------------------------------------*/ -/** - * - * This function initiates DQS training for Server NB - * - * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK - * - */ - -BOOLEAN -memNSequenceDDR3Nb ( - IN OUT MEM_NB_BLOCK *NBPtr - ) -{ - MEM_TECH_BLOCK *TechPtr; - UINT8 i; - TechPtr = NBPtr->TechPtr; - i = NBPtr->TrainingSequenceIndex; - if (TechPtr->NBPtr->MCTPtr->NodeMemSize != 0) { - AGESA_TESTPOINT (TpProcMemBeforeAgesaHookBeforeDQSTraining, &NBPtr->MemPtr->StdHeader); - IDS_HDT_CONSOLE (MEM_FLOW, "\nCalling out to Platform BIOS...\n"); - if (AgesaHookBeforeDQSTraining (NBPtr->MCTPtr->SocketId, TechPtr->NBPtr->MemPtr) == AGESA_SUCCESS) { - // Right now we do not have anything to do if the callout is implemented - } - AGESA_TESTPOINT (TpProcMemAfterAgesaHookBeforeDQSTraining, &NBPtr->MemPtr->StdHeader); - //Execute Technology specific training features - if (memTrainSequenceDDR3[i].MemTechFeatBlock->EnterHardwareTraining (TechPtr)) { - TechPtr->TechnologySpecificHook[LrdimmBuf2DramTrain] (TechPtr, NULL); - if (memTrainSequenceDDR3[i].MemTechFeatBlock->SwWLTraining (TechPtr)) { - MemFInitTableDrive (NBPtr, MTAfterSwWLTrn); - if (memTrainSequenceDDR3[i].MemTechFeatBlock->HwBasedWLTrainingPart1 (TechPtr)) { - MemFInitTableDrive (NBPtr, MTAfterHwWLTrnP1); - if (memTrainSequenceDDR3[i].MemTechFeatBlock->HwBasedDQSReceiverEnableTrainingPart1 (TechPtr)) { - MemFInitTableDrive (NBPtr, MTAfterHwRxEnTrnP1); - // If target speed is higher than start-up speed, do frequency change and second pass of WL - do { - if (MemNHwWlPart2Nb (TechPtr)) { - if (memTrainSequenceDDR3[i].MemTechFeatBlock->TrainExitHwTrn (TechPtr)) { - IDS_OPTION_HOOK (IDS_PHY_DLL_STANDBY_CTRL, NBPtr, &(NBPtr->MemPtr->StdHeader)); - if (memTrainSequenceDDR3[i].MemTechFeatBlock->NonOptimizedSWDQSRecEnTrainingPart1 (TechPtr)) { - if (memTrainSequenceDDR3[i].MemTechFeatBlock->OptimizedSwDqsRecEnTrainingPart1 (TechPtr)) { - MemFInitTableDrive (NBPtr, MTAfterSwRxEnTrn); - if (memTrainSequenceDDR3[i].MemTechFeatBlock->NonOptimizedSRdWrPosTraining (TechPtr)) { - if (memTrainSequenceDDR3[i].MemTechFeatBlock->OptimizedSRdWrPosTraining (TechPtr)) { - MemFInitTableDrive (NBPtr, MTAfterDqsRwPosTrn); - if (!NBPtr->FamilySpecificHook[MemPstateStageChange] (NBPtr, NULL)) { - continue; - } - do { - if (memTrainSequenceDDR3[i].MemTechFeatBlock->MaxRdLatencyTraining (TechPtr)) { - MemFInitTableDrive (NBPtr, MTAfterMaxRdLatTrn); - } - } while (NBPtr->ChangeNbFrequency (NBPtr)); - } - } - } - } - } - } - } while (NBPtr->MemPstateStage == MEMORY_PSTATE_2ND_STAGE); - } - } - } - } - TechPtr->TechnologySpecificHook[LrdimmSyncTrainedDlys] (TechPtr, NULL); - MemTMarkTrainFail (TechPtr); - } - return TRUE; -} -/* -----------------------------------------------------------------------------*/ -/** - * - * This function executes HW WL at multiple speeds - * - * @param[in,out] *TechPtr - Pointer to the MEM_TECH_BLOCK - * @return TRUE - No errors occurred - * FALSE - errors occurred - */ - -BOOLEAN -STATIC -MemNHwWlPart2Nb ( - IN OUT MEM_TECH_BLOCK *TechPtr - ) -{ - BOOLEAN retVal; - UINT8 i; - retVal = TRUE; - i = TechPtr->NBPtr->TrainingSequenceIndex; - while ((TechPtr->NBPtr->DCTPtr->Timings.TargetSpeed > TechPtr->NBPtr->DCTPtr->Timings.Speed) && (TechPtr->NBPtr->MemPstateStage != MEMORY_PSTATE_1ST_STAGE)) { - TechPtr->PrevSpeed = TechPtr->NBPtr->DCTPtr->Timings.Speed; - if (TechPtr->NBPtr->RampUpFrequency (TechPtr->NBPtr)) { - TechPtr->TechnologySpecificHook[LrdimmBuf2DramTrain] (TechPtr, NULL); - if (!memTrainSequenceDDR3[i].MemTechFeatBlock->HwBasedWLTrainingPart2 (TechPtr)) { - retVal = FALSE; - break; - } - MemFInitTableDrive (TechPtr->NBPtr, MTAfterHwWLTrnP2); - if (!memTrainSequenceDDR3[i].MemTechFeatBlock->HwBasedDQSReceiverEnableTrainingPart2 (TechPtr)) { - retVal = FALSE; - break; - } - MemFInitTableDrive (TechPtr->NBPtr, MTAfterHwRxEnTrnP2); - } else { - retVal = FALSE; - break; - } - } - return retVal; -} diff --git a/src/vendorcode/amd/agesa/f12/Proc/Mem/Ps/LN/Makefile.inc b/src/vendorcode/amd/agesa/f12/Proc/Mem/Ps/LN/Makefile.inc deleted file mode 100644 index 9283b173be..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/Mem/Ps/LN/Makefile.inc +++ /dev/null @@ -1,3 +0,0 @@ -libagesa-y += mprln3.c -libagesa-y += mpsln3.c -libagesa-y += mpuln3.c diff --git a/src/vendorcode/amd/agesa/f12/Proc/Mem/Ps/LN/mprln3.c b/src/vendorcode/amd/agesa/f12/Proc/Mem/Ps/LN/mprln3.c deleted file mode 100644 index 130b4682c0..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/Mem/Ps/LN/mprln3.c +++ /dev/null @@ -1,146 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * mprln3.c - * - * Platform specific settings for LN DDR3 R-DIMM system - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: (Mem/Ps) - * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $ - * - **/ -/***************************************************************************** - * - * Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * *************************************************************************** - * - */ - -/* This file contains routine that add platform specific support L1 */ - - -#include "AGESA.h" -#include "AdvancedApi.h" -#include "ma.h" -#include "Ids.h" -#include "cpuFamRegisters.h" -#include "mm.h" -#include "mn.h" -#include "mp.h" -#include "Filecode.h" -CODE_GROUP (G2_PEI) -RDATA_GROUP (G2_PEI) - -#define FILECODE PROC_MEM_PS_LN_MPRLN3_FILECODE -/*---------------------------------------------------------------------------- - * DEFINITIONS AND MACROS - * - *---------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------- - * TYPEDEFS AND STRUCTURES - * - *---------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------- - * PROTOTYPES OF LOCAL FUNCTIONS - * - *---------------------------------------------------------------------------- - */ -BOOLEAN -STATIC -MemPDoPsRLN3 ( - IN OUT MEM_NB_BLOCK *NBPtr - ); -/* - *----------------------------------------------------------------------------- - * EXPORTED FUNCTIONS - * - *----------------------------------------------------------------------------- - */ -/* -----------------------------------------------------------------------------*/ -/** - * - * This function is the constructor platform specific settings for R DIMM-DDR3 LN DDR3 - * - * @param[in,out] *MemPtr Pointer to MEM_DATA_STRUCTURE - * @param[in,out] *ChannelPtr Pointer to CH_DEF_STRUCT - * @param[in,out] *PsPtr Pointer to MEM_PS_BLOCK - * - * @return AGESA_SUCCESS - * - */ - -AGESA_STATUS -MemPConstructPsRLN3 ( - IN OUT MEM_DATA_STRUCT *MemPtr, - IN OUT CH_DEF_STRUCT *ChannelPtr, - IN OUT MEM_PS_BLOCK *PsPtr - ) -{ - ASSERT (MemPtr != 0); - ASSERT (ChannelPtr != 0); - - - if ((ChannelPtr->MCTPtr->LogicalCpuid.Family & AMD_FAMILY_12_LN) == 0) { - return AGESA_UNSUPPORTED; - } - if (ChannelPtr->TechType != DDR3_TECHNOLOGY) { - return AGESA_UNSUPPORTED; - } - if (ChannelPtr->RegDimmPresent != ChannelPtr->ChDimmValid) { - return AGESA_UNSUPPORTED; - } - PsPtr->MemPDoPs = MemPDoPsRLN3; - PsPtr->MemPGetPORFreqLimit = MemPGetPORFreqLimitDef; - return AGESA_SUCCESS; -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * This is function sets the platform specific settings for R-DDR3 LN DDR3 - * - * @param[in,out] *NBPtr Pointer to MEM_NB_BLOCK - * - * @return TRUE - Find settings for corresponding platform and dimm population. - * @return FALSE - Fail to find settings for corresponding platform and dimm population. - * - */ - -BOOLEAN -STATIC -MemPDoPsRLN3 ( - IN OUT MEM_NB_BLOCK *NBPtr - ) -{ - return TRUE; -} diff --git a/src/vendorcode/amd/agesa/f12/Proc/Mem/Ps/LN/mpsln3.c b/src/vendorcode/amd/agesa/f12/Proc/Mem/Ps/LN/mpsln3.c deleted file mode 100644 index 2803a3910c..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/Mem/Ps/LN/mpsln3.c +++ /dev/null @@ -1,165 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * mpsln3.c - * - * Platform specific settings for LN DDR3 SO-DIMM system - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: (Mem/Ps) - * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $ - * - **/ -/***************************************************************************** - * - * Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * *************************************************************************** - * - */ - -/* This file contains routine that add platform specific support L1 */ - - -#include "AGESA.h" -#include "AdvancedApi.h" -#include "mport.h" -#include "ma.h" -#include "Ids.h" -#include "cpuFamRegisters.h" -#include "mm.h" -#include "mn.h" -#include "mp.h" -#include "mu.h" -#include "OptionMemory.h" -#include "PlatformMemoryConfiguration.h" -#include "Filecode.h" -CODE_GROUP (G2_PEI) -RDATA_GROUP (G2_PEI) - -#define FILECODE PROC_MEM_PS_LN_MPSLN3_FILECODE -/*---------------------------------------------------------------------------- - * DEFINITIONS AND MACROS - * - *---------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------- - * TYPEDEFS AND STRUCTURES - * - *---------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------- - * PROTOTYPES OF LOCAL FUNCTIONS - * - *---------------------------------------------------------------------------- - */ -BOOLEAN -STATIC -MemPDoPsSLN3 ( - IN OUT MEM_NB_BLOCK *NBPtr - ); - -/* - *----------------------------------------------------------------------------- - * EXPORTED FUNCTIONS - * - *----------------------------------------------------------------------------- - */ -STATIC CONST DRAM_TERM_ENTRY LnSDdr3DramTerm[] = { - {DDR800, ONE_DIMM, NO_DIMM, 2, 0, 0}, - {DDR1066, ONE_DIMM, NO_DIMM, 2, 0, 0}, - {DDR1333, ONE_DIMM, NO_DIMM, 1, 0, 0}, - {DDR1600 + DDR1866, ONE_DIMM, NO_DIMM, 3, 0, 0}, - - {DDR800, TWO_DIMM, NO_DIMM, 3, 0, 2}, - {DDR1066 + DDR1333, TWO_DIMM, NO_DIMM, 5, 0, 2}, - {DDR1600 + DDR1866, TWO_DIMM, NO_DIMM, 4, 0, 1} -}; -/* -----------------------------------------------------------------------------*/ -/** - * - * This function is the constructor the platform specific settings for SO SIMM-DDR3 LN DDR3 - * - * @param[in,out] *MemPtr Pointer to MEM_DATA_STRUCTURE - * @param[in,out] *ChannelPtr Pointer to CH_DEF_STRUCT - * @param[in,out] *PsPtr Pointer to MEM_PS_BLOCK - * - * @return AGESA_SUCCESS - * - */ - -AGESA_STATUS -MemPConstructPsSLN3 ( - IN OUT MEM_DATA_STRUCT *MemPtr, - IN OUT CH_DEF_STRUCT *ChannelPtr, - IN OUT MEM_PS_BLOCK *PsPtr - ) -{ - ASSERT (MemPtr != 0); - ASSERT (ChannelPtr != 0); - - if ((ChannelPtr->MCTPtr->LogicalCpuid.Family & AMD_FAMILY_12_LN) == 0) { - return AGESA_UNSUPPORTED; - } - if (ChannelPtr->TechType != DDR3_TECHNOLOGY) { - return AGESA_UNSUPPORTED; - } - if (ChannelPtr->SODimmPresent != ChannelPtr->ChDimmValid) { - return AGESA_UNSUPPORTED; - } - PsPtr->MemPDoPs = MemPDoPsSLN3; - PsPtr->MemPGetPORFreqLimit = MemPGetPORFreqLimitDef; - return AGESA_SUCCESS; -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * This is function sets the platform specific settings for S-DDR3 LN DDR3 - * - * @param[in,out] *NBPtr Pointer to MEM_NB_BLOCK - * - * @return TRUE - Find settings for corresponding platform and dimm population. - * @return FALSE - Fail to find settings for corresponding platform and dimm population. - * - */ - -BOOLEAN -STATIC -MemPDoPsSLN3 ( - IN OUT MEM_NB_BLOCK *NBPtr - ) -{ - if (!MemPGetDramTerm (NBPtr, GET_SIZE_OF (LnSDdr3DramTerm), LnSDdr3DramTerm)) { - return FALSE; - } - - return TRUE; -} - diff --git a/src/vendorcode/amd/agesa/f12/Proc/Mem/Ps/LN/mpuln3.c b/src/vendorcode/amd/agesa/f12/Proc/Mem/Ps/LN/mpuln3.c deleted file mode 100644 index 0afab69c7b..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/Mem/Ps/LN/mpuln3.c +++ /dev/null @@ -1,164 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * mpuln3.c - * - * Platform specific settings for LN DDR3 U-DIMM system - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: (Mem/Ps) - * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $ - * - **/ -/***************************************************************************** - * - * Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * *************************************************************************** - * - */ - -/* This file contains routine that add platform specific support L1 */ - - -#include "AGESA.h" -#include "Ids.h" -#include "AdvancedApi.h" -#include "mport.h" -#include "ma.h" -#include "cpuFamRegisters.h" -#include "mm.h" -#include "mn.h" -#include "mp.h" -#include "mu.h" -#include "OptionMemory.h" -#include "PlatformMemoryConfiguration.h" -#include "Filecode.h" -CODE_GROUP (G2_PEI) -RDATA_GROUP (G2_PEI) - -#define FILECODE PROC_MEM_PS_LN_MPULN3_FILECODE -/*---------------------------------------------------------------------------- - * DEFINITIONS AND MACROS - * - *---------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------- - * TYPEDEFS AND STRUCTURES - * - *---------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------- - * PROTOTYPES OF LOCAL FUNCTIONS - * - *---------------------------------------------------------------------------- - */ -BOOLEAN -STATIC -MemPDoPsULN3 ( - IN OUT MEM_NB_BLOCK *NBPtr - ); -/* - *----------------------------------------------------------------------------- - * EXPORTED FUNCTIONS - * - *----------------------------------------------------------------------------- - */ -STATIC CONST DRAM_TERM_ENTRY LnUDdr3DramTerm[] = { - {DDR800, ONE_DIMM, NO_DIMM, 2, 0, 0}, - {DDR1066, ONE_DIMM, NO_DIMM, 2, 0, 0}, - {DDR1333, ONE_DIMM, NO_DIMM, 1, 0, 0}, - {DDR1600 + DDR1866, ONE_DIMM, NO_DIMM, 3, 0, 0}, - - {DDR800 + DDR1066, TWO_DIMM, NO_DIMM, 3, 0, 2}, - {DDR1333, TWO_DIMM, NO_DIMM, 5, 0, 2}, - {DDR1600 + DDR1866, TWO_DIMM, NO_DIMM, 4, 0, 1} -}; - -/* -----------------------------------------------------------------------------*/ -/** - * - * This function is the constructor for the platform specific settings for U-DDR3 LN DDR3 - * - * @param[in,out] *MemPtr Pointer to MEM_DATA_STRUCTURE - * @param[in,out] *ChannelPtr Pointer to CH_DEF_STRUCT - * @param[in,out] *PsPtr Pointer to MEM_PS_BLOCK - * - * @return AGESA_SUCCESS - * - */ - -AGESA_STATUS -MemPConstructPsULN3 ( - IN OUT MEM_DATA_STRUCT *MemPtr, - IN OUT CH_DEF_STRUCT *ChannelPtr, - IN OUT MEM_PS_BLOCK *PsPtr - ) -{ - ASSERT (MemPtr != 0); - ASSERT (ChannelPtr != 0); - - if ((ChannelPtr->MCTPtr->LogicalCpuid.Family & AMD_FAMILY_12_LN) == 0) { - return AGESA_UNSUPPORTED; - } - if (ChannelPtr->TechType != DDR3_TECHNOLOGY) { - return AGESA_UNSUPPORTED; - } - if ((ChannelPtr->RegDimmPresent != 0) || (ChannelPtr->SODimmPresent != 0)) { - return AGESA_UNSUPPORTED; - } - PsPtr->MemPDoPs = MemPDoPsULN3; - PsPtr->MemPGetPORFreqLimit = MemPGetPORFreqLimitDef; - return AGESA_SUCCESS; -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * This is function sets the platform specific settings for U-DDR3 LN DDR3 - * - * @param[in,out] *NBPtr Pointer to MEM_NB_BLOCK - * - * @return TRUE - Find settings for corresponding platform and dimm population. - * @return FALSE - Fail to find settings for corresponding platform and dimm population. - * - */ - -BOOLEAN -STATIC -MemPDoPsULN3 ( - IN OUT MEM_NB_BLOCK *NBPtr - ) -{ - if (!MemPGetDramTerm (NBPtr, GET_SIZE_OF (LnUDdr3DramTerm), LnUDdr3DramTerm)) { - return FALSE; - } - - return TRUE; -} diff --git a/src/vendorcode/amd/agesa/f12/Proc/Mem/Ps/Makefile.inc b/src/vendorcode/amd/agesa/f12/Proc/Mem/Ps/Makefile.inc deleted file mode 100644 index 5f2e596093..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/Mem/Ps/Makefile.inc +++ /dev/null @@ -1,11 +0,0 @@ -libagesa-y += mp.c -libagesa-y += mplribt.c -libagesa-y += mplrnlr.c -libagesa-y += mplrnpr.c -libagesa-y += mpmaxfreq.c -libagesa-y += mpmr0.c -libagesa-y += mpodtpat.c -libagesa-y += mprc10opspd.c -libagesa-y += mprc2ibt.c -libagesa-y += mprtt.c -libagesa-y += mpsao.c diff --git a/src/vendorcode/amd/agesa/f12/Proc/Mem/Ps/mp.c b/src/vendorcode/amd/agesa/f12/Proc/Mem/Ps/mp.c deleted file mode 100644 index 2d261f8c2d..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/Mem/Ps/mp.c +++ /dev/null @@ -1,523 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * mp.c - * - * Common platform specific configuration. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: (Mem/Ps) - * @e \$Revision: 49545 $ @e \$Date: 2011-03-25 05:58:58 +0800 (Fri, 25 Mar 2011) $ - * - **/ -/***************************************************************************** -* -* Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* *************************************************************************** -* -*/ -/* - *---------------------------------------------------------------------------- - * MODULES USED - * - *---------------------------------------------------------------------------- - */ - - - -#include "AGESA.h" -#include "AdvancedApi.h" -#include "amdlib.h" -#include "Ids.h" -#include "cpuFamRegisters.h" -#include "cpuRegisters.h" -#include "OptionMemory.h" -#include "PlatformMemoryConfiguration.h" -#include "mu.h" -#include "ma.h" -#include "mp.h" -#include "Filecode.h" -CODE_GROUP (G2_PEI) -RDATA_GROUP (G2_PEI) - -#define FILECODE PROC_MEM_PS_MP_FILECODE - - -/*---------------------------------------------------------------------------- - * DEFINITIONS AND MACROS - * - *---------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------- - * TYPEDEFS AND STRUCTURES - * - *---------------------------------------------------------------------------- - */ -/*---------------------------------------------------------------------------- - * PROTOTYPES OF LOCAL FUNCTIONS - * - *---------------------------------------------------------------------------- - */ -BOOLEAN -STATIC -MemPPSCGen ( - IN OUT MEM_NB_BLOCK *NBPtr, - IN MEM_PSC_TABLE_BLOCK *EntryOfTables - ); - -/*---------------------------------------------------------------------------- - * EXPORTED FUNCTIONS - * - *---------------------------------------------------------------------------- - */ -extern MEM_PSC_FLOW_BLOCK* memPlatSpecFlowArray[]; - -/* -----------------------------------------------------------------------------*/ -/** - * - * This is the default return function of the Platform Specific block. The function always - * returns AGESA_UNSUPPORTED - * - * @param[in,out] *MemPtr Pointer to MEM_DATA_STRUCTURE - * @param[in] *ChannelPtr Pointer to CH_DEF_STRUCT - * @param[in] *PsPtr Pointer to MEM_PS_BLOCK - * - * @return AGESA_UNSUPPORTED AGESA status indicating that default is unsupported - * - */ - -AGESA_STATUS -MemPConstructPsUDef ( - IN OUT MEM_DATA_STRUCT *MemPtr, - IN OUT CH_DEF_STRUCT *ChannelPtr, - IN OUT MEM_PS_BLOCK *PsPtr - ) -{ - return AGESA_UNSUPPORTED; -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * This function will set the DramTerm and DramTermDyn in the structure of a channel. - * - * @param[in,out] *NBPtr Pointer to MEM_NB_BLOCK - * @param[in] ArraySize Size of the array of DramTerm - * @param[in] *DramTermPtr Address the array of DramTerm - * - * @return TRUE - Find DramTerm and DramTermDyn for corresponding platform and dimm population. - * @return FALSE - Fail to find DramTerm and DramTermDyn for corresponding platform and dimm population. - * - */ -BOOLEAN -MemPGetDramTerm ( - IN OUT MEM_NB_BLOCK *NBPtr, - IN UINT8 ArraySize, - IN CONST DRAM_TERM_ENTRY *DramTermPtr - ) -{ - UINT8 Dimms; - UINT8 QR_Dimms; - UINT8 i; - Dimms = NBPtr->ChannelPtr->Dimms; - QR_Dimms = 0; - for (i = 0; i < MAX_DIMMS_PER_CHANNEL; i ++) { - if (((NBPtr->ChannelPtr->DimmQrPresent & (UINT16) (1 << i)) != 0) && (i < 2)) { - QR_Dimms ++; - } - } - - for (i = 0; i < ArraySize; i ++) { - if ((DramTermPtr[i].Speed & ((UINT32) 1 << (NBPtr->DCTPtr->Timings.Speed / 66))) != 0) { - if ((((UINT8) (1 << (Dimms - 1)) & DramTermPtr[i].Dimms) != 0) || (DramTermPtr[i].Dimms == ANY_NUM)) { - if (((QR_Dimms == 0) && (DramTermPtr[i].QR_Dimms == NO_DIMM)) || - ((QR_Dimms > 0) && (((UINT8) (1 << (QR_Dimms - 1)) & DramTermPtr[i].QR_Dimms) != 0)) || - (DramTermPtr[i].QR_Dimms == ANY_NUM)) { - NBPtr->PsPtr->DramTerm = DramTermPtr[i].DramTerm; - NBPtr->PsPtr->QR_DramTerm = DramTermPtr[i].QR_DramTerm; - NBPtr->PsPtr->DynamicDramTerm = DramTermPtr[i].DynamicDramTerm; - break; - } - } - } - } - return TRUE; -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * This function gets the highest POR supported speed. - * - * @param[in,out] *NBPtr Pointer to MEM_NB_BLOCK - * @param[in] FreqLimitSize Size of the array of Frequency Limit - * @param[in] *FreqLimitPtr Address the array of Frequency Limit - * - * @return UINT8 - frequency limit - * - */ -UINT16 -MemPGetPorFreqLimit ( - IN OUT MEM_NB_BLOCK *NBPtr, - IN UINT8 FreqLimitSize, - IN CONST POR_SPEED_LIMIT *FreqLimitPtr - ) -{ - UINT8 i; - UINT8 j; - UINT8 DimmTpMatch; - UINT16 SpeedLimit; - UINT16 DIMMRankType; - UINT16 _DIMMRankType; - - SpeedLimit = 0; - DIMMRankType = MemAGetPsRankType (NBPtr->ChannelPtr); - for (i = 0; i < FreqLimitSize; i++, FreqLimitPtr++) { - if (NBPtr->ChannelPtr->Dimms != FreqLimitPtr->Dimms) { - continue; - } - DimmTpMatch = 0; - _DIMMRankType = DIMMRankType & FreqLimitPtr->DIMMRankType; - for (j = 0; j < MAX_DIMMS_PER_CHANNEL; j ++) { - if ((_DIMMRankType & (UINT16) 0x0F << (j << 2)) != 0) { - DimmTpMatch++; - } - } - if (DimmTpMatch == FreqLimitPtr->Dimms) { - if (NBPtr->RefPtr->DDR3Voltage == VOLT1_5) { - SpeedLimit = FreqLimitPtr->SpeedLimit_1_5V; - break; - } else if (NBPtr->RefPtr->DDR3Voltage == VOLT1_25) { - SpeedLimit = FreqLimitPtr->SpeedLimit_1_25V; - break; - } else { - SpeedLimit = FreqLimitPtr->SpeedLimit_1_35V; - break; - } - } - } - - return SpeedLimit; -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * This function is the default function for getting POR speed limit. When a - * package does not need to cap the speed, it should use this function to initialize - * the corresponding function pointer. - * - * @param[in,out] *NBPtr Pointer to MEM_NB_BLOCK - * - */ -VOID -MemPGetPORFreqLimitDef ( - IN OUT MEM_NB_BLOCK *NBPtr - ) -{ -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * This function gets platform specific configuration such as Max Freq., Slow Mode, Dram Term, - * and so on. - * - * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK - * - * @return TRUE - Successfully execute platform specific configuration flow. - * @return FALSE - Fail to execute platform specific configuration flow. - * - */ -BOOLEAN -MemPPSCFlow ( - IN OUT MEM_NB_BLOCK *NBPtr - ) -{ - UINT8 i; - BOOLEAN Result; - - Result = TRUE; - i = 0; - while (memPlatSpecFlowArray[i] != NULL) { - if ((memPlatSpecFlowArray[i])->DramTerm (NBPtr, (memPlatSpecFlowArray[i])->EntryOfTables)) { - if ((memPlatSpecFlowArray[i])->ODTPattern (NBPtr, (memPlatSpecFlowArray[i])->EntryOfTables)) { - if ((memPlatSpecFlowArray[i])->SAO (NBPtr, (memPlatSpecFlowArray[i])->EntryOfTables)) { - if ((memPlatSpecFlowArray[i])->MR0WrCL (NBPtr, (memPlatSpecFlowArray[i])->EntryOfTables)) { - if ((memPlatSpecFlowArray[i])->RC2IBT (NBPtr, (memPlatSpecFlowArray[i])->EntryOfTables)) { - if ((memPlatSpecFlowArray[i])->RC10OpSpeed (NBPtr, (memPlatSpecFlowArray[i])->EntryOfTables)) { - if ((memPlatSpecFlowArray[i])->LRIBT (NBPtr, (memPlatSpecFlowArray[i])->EntryOfTables)) { - if ((memPlatSpecFlowArray[i])->LRNPR (NBPtr, (memPlatSpecFlowArray[i])->EntryOfTables)) { - if ((memPlatSpecFlowArray[i])->LRNLR (NBPtr, (memPlatSpecFlowArray[i])->EntryOfTables)) { - if (MemPPSCGen (NBPtr, (memPlatSpecFlowArray[i])->EntryOfTables)) { - break; - } - } - } - } - } - } - } - } - } - } - i++; - } - - IDS_SKIP_HOOK (IDS_ENFORCE_PLAT_TABLES, NBPtr, &(NBPtr->MemPtr->StdHeader)) { - if (memPlatSpecFlowArray[i] == NULL) { - Result = FALSE; - } - } - return Result; -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * This function constructs the rank type map of Dimm0, Dimm1, Dimm2. Also it counts the number - * of dimm in the table. - * - * @param[in] Dimm0 Rank type of Dimm0 - * @param[in] Dimm1 Rank type of Dimm1 - * @param[in] Dimm2 Rank type of Dimm2 - * @param[in, out] *RankTypeInTable Pointer to RankTypeInTable variable - * - * - */ -VOID -MemPConstructRankTypeMap ( - IN UINT16 Dimm0, - IN UINT16 Dimm1, - IN UINT16 Dimm2, - IN OUT UINT16 *RankTypeInTable - ) -{ - UINT8 i; - UINT16 RT; - UINT8 BitShift; - - *RankTypeInTable = 0; - RT = 0; - BitShift = 0; - - for (i = 0; i < MAX_DIMMS_PER_CHANNEL; i++) { - switch (i) { - case 0: - RT = (Dimm0 == 0) ? NP : Dimm0; - BitShift = 0; - break; - case 1: - RT = (Dimm1 == 0) ? NP : Dimm1; - BitShift = 4; - break; - case 2: - RT = (Dimm2 == 0) ? NP : Dimm2; - BitShift = 8; - break; - default: - // dimm3 is not used, fills nibble3 with "NP" - RT = NP; - BitShift = 12; - } - *RankTypeInTable |= RT << BitShift; - } -} - -/*-----------------------------------------------------------------------------*/ -/** - * MemPIsIdSupported - * This function matches the CPU_LOGICAL_ID and PackageType with certain criteria to - * determine if it is supported by this NB type. - * - * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK - * @param[in] LogicalId - CPU_LOGICAL_ID - * @param[in] PackageType - Package Type - * - * @return TRUE - NB type is matched ! - * @return FALSE - NB type is not matched ! - * - */ -BOOLEAN -MemPIsIdSupported ( - IN OUT MEM_NB_BLOCK *NBPtr, - IN CPU_LOGICAL_ID LogicalId, - IN UINT8 PackageType - ) -{ - CPUID_DATA CpuId; - UINT8 PkgType; - - LibAmdCpuidRead (AMD_CPUID_FMF, &CpuId, &(NBPtr->MemPtr->StdHeader)); - PkgType = (UINT8) (CpuId.EBX_Reg >> 28) & 0xF; // bit 31:28 - - if (((NBPtr->MCTPtr->LogicalCpuid.Family & LogicalId.Family) != 0) - && ((NBPtr->MCTPtr->LogicalCpuid.Revision & LogicalId.Revision) != 0)) { - if ((PackageType == PT_DONT_CARE) || (PackageType == PkgType)) { - return TRUE; - } - } - return FALSE; -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * This function returns the rank type map of a channel. - * - * @param[in] *CurrentChannel Pointer to CH_DEF_STRUCT - * - * @return UINT16 - The map of rank type. - * - */ -UINT16 -MemPGetPsRankType ( - IN CH_DEF_STRUCT *CurrentChannel - ) -{ - UINT8 i; - UINT16 DIMMRankType; - - DIMMRankType = 0; - for (i = 0; i < MAX_DIMMS_PER_CHANNEL; i++) { - if (CurrentChannel->MCTPtr->Status[SbLrdimms]) { - // For LrDimm, we construct the map according to Dimm present bits rather than rank type bits - if ((CurrentChannel->LrDimmPresent & (UINT8) 1 << i) != 0) { - DIMMRankType |= (UINT16) DIMM_LR << (i << 2); - } else { - DIMMRankType |= (UINT16) NP << (i << 2); - } - } else { - if ((CurrentChannel->DimmQrPresent & (UINT8) 1 << i) != 0) { - if (i < 2) { - DIMMRankType |= (UINT16) DIMM_QR << (i << 2); - } - } else if ((CurrentChannel->DimmDrPresent & (UINT8) 1 << i) != 0) { - DIMMRankType |= (UINT16) DIMM_DR << (i << 2); - } else if ((CurrentChannel->DimmSRPresent & (UINT8) 1 << i) != 0) { - DIMMRankType |= (UINT16) DIMM_SR << (i << 2); - } else { - DIMMRankType |= (UINT16) NP << (i << 2); - } - } - } - - return DIMMRankType; -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * This function performs the action for the rest of platform specific configuration such as - * tri-state stuff - * - * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK - * @param[in] *EntryOfTables Pointer to MEM_PSC_TABLE_BLOCK - * - * @return TRUE - No error occurred. - * @return FALSE - Error occurred. - * - */ -BOOLEAN -STATIC -MemPPSCGen ( - IN OUT MEM_NB_BLOCK *NBPtr, - IN MEM_PSC_TABLE_BLOCK *EntryOfTables - ) -{ - UINT8 i; - PSCFG_TYPE PSCType; - DIMM_TYPE DimmType; - UINT8 MaxDimmPerCh; - UINT8 NOD; - CPU_LOGICAL_ID LogicalCpuid; - UINT8 PackageType; - CH_DEF_STRUCT *CurrentChannel; - - CurrentChannel = NBPtr->ChannelPtr; - - PackageType = 0; - LogicalCpuid.Family = (UINT64) AMD_FAMILY_UNKNOWN; - MaxDimmPerCh = GetMaxDimmsPerChannel (NBPtr->RefPtr->PlatformMemoryConfiguration, NBPtr->MCTPtr->SocketId, CurrentChannel->ChannelID); - NOD = (UINT8) 1 << (MaxDimmPerCh - 1); - - if (CurrentChannel->RegDimmPresent != 0) { - DimmType = RDIMM_TYPE; - } else if (CurrentChannel->SODimmPresent != 0) { - DimmType = SODIMM_TYPE; - } else if (CurrentChannel->LrDimmPresent != 0) { - DimmType = LRDIMM_TYPE; - } else { - DimmType = UDIMM_TYPE; - } - - for (PSCType = PSCFG_GEN_START + 1; PSCType < PSCFG_GEN_END; PSCType++) { - i = 0; - while (EntryOfTables->TblEntryOfGen[i] != NULL) { - if ((EntryOfTables->TblEntryOfGen[i])->Header.PSCType == PSCType) { - if (((EntryOfTables->TblEntryOfGen[i])->Header.DimmType & DimmType) != 0) { - if (((EntryOfTables->TblEntryOfGen[i])->Header.NumOfDimm & NOD) != 0) { - // - // Determine if this is the expected NB Type - // - LogicalCpuid = (EntryOfTables->TblEntryOfGen[i])->Header.LogicalCpuid; - PackageType = (EntryOfTables->TblEntryOfGen[i])->Header.PackageType; - if (MemPIsIdSupported (NBPtr, LogicalCpuid, PackageType)) { - break; - } - } - } - } - i++; - } - - // Check whether no table entry is found. - if (EntryOfTables->TblEntryOfGen[i] == NULL) { - IDS_HDT_CONSOLE (MEM_FLOW, "\nNo %s Table\n", (PSCType == PSCFG_CLKDIS) ? "ClkDis" : ((PSCType == PSCFG_CKETRI) ? "CkeTri" : ((PSCType == PSCFG_ODTTRI) ? "OdtTri" : "CsTri"))); - return FALSE; - } - - // Perform the action for specific PSCType. - if (PSCType == PSCFG_CLKDIS) { - CurrentChannel->MemClkDisMap = (UINT8 *) (EntryOfTables->TblEntryOfGen[i])->TBLPtr; - } else if (PSCType == PSCFG_CKETRI) { - CurrentChannel->CKETriMap = (UINT8 *) (EntryOfTables->TblEntryOfGen[i])->TBLPtr; - } else if (PSCType == PSCFG_ODTTRI) { - CurrentChannel->ODTTriMap = (UINT8 *) (EntryOfTables->TblEntryOfGen[i])->TBLPtr; - } else if (PSCType == PSCFG_CSTRI) { - CurrentChannel->ChipSelTriMap = (UINT8 *) (EntryOfTables->TblEntryOfGen[i])->TBLPtr; - } - } - - CurrentChannel->DctEccDqsLike = 0x0403; - CurrentChannel->DctEccDqsScale = 0x70; - - return TRUE; -} - diff --git a/src/vendorcode/amd/agesa/f12/Proc/Mem/Ps/mplribt.c b/src/vendorcode/amd/agesa/f12/Proc/Mem/Ps/mplribt.c deleted file mode 100644 index 91cfeee575..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/Mem/Ps/mplribt.c +++ /dev/null @@ -1,193 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * mplribt.c - * - * A sub-engine which extracts F0RC8, F1RC0, F1RC1 and F1RC2 value for LRDIMM configuration. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: (Mem/Ps) - * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $ - * - **/ -/***************************************************************************** -* -* Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* *************************************************************************** -* -*/ -/* - *---------------------------------------------------------------------------- - * MODULES USED - * - *---------------------------------------------------------------------------- - */ - - - -#include "AGESA.h" -#include "AdvancedApi.h" -#include "amdlib.h" -#include "Ids.h" -#include "cpuFamRegisters.h" -#include "cpuRegisters.h" -#include "OptionMemory.h" -#include "PlatformMemoryConfiguration.h" -#include "mu.h" -#include "ma.h" -#include "mp.h" -#include "Filecode.h" -CODE_GROUP (G2_PEI) -RDATA_GROUP (G2_PEI) -#define FILECODE PROC_MEM_PS_MPLRIBT_FILECODE - - -/*---------------------------------------------------------------------------- - * DEFINITIONS AND MACROS - * - *---------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------- - * TYPEDEFS AND STRUCTURES - * - *---------------------------------------------------------------------------- - */ -/*---------------------------------------------------------------------------- - * PROTOTYPES OF LOCAL FUNCTIONS - * - *---------------------------------------------------------------------------- - */ -BOOLEAN -MemPGetLRIBT ( - IN OUT MEM_NB_BLOCK *NBPtr, - IN MEM_PSC_TABLE_BLOCK *EntryOfTables - ); - -/*---------------------------------------------------------------------------- - * EXPORTED FUNCTIONS - * - *---------------------------------------------------------------------------- - */ -/* -----------------------------------------------------------------------------*/ -/** - * - * A sub-function which extracts LRDIMM F0RC8, F1RC0, F1RC1 and F1RC2 value from a input - * table and stores extracted value to a specific address. - * - * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK - * @param[in] *EntryOfTables - Pointer to MEM_PSC_TABLE_BLOCK - * - * @return TRUE - Succeed in extracting the table value - * @return FALSE - Fail to extract the table value - * - */ -BOOLEAN -MemPGetLRIBT ( - IN OUT MEM_NB_BLOCK *NBPtr, - IN MEM_PSC_TABLE_BLOCK *EntryOfTables - ) -{ - UINT8 i; - UINT8 MaxDimmPerCh; - UINT8 NOD; - UINT8 TableSize; - UINT32 CurDDRrate; - UINT8 DDR3Voltage; - UINT16 RankTypeOfPopulatedDimm; - UINT16 RankTypeInTable; - CPU_LOGICAL_ID LogicalCpuid; - UINT8 PackageType; - PSCFG_L_IBT_ENTRY *TblPtr; - CH_DEF_STRUCT *CurrentChannel; - - CurrentChannel = NBPtr->ChannelPtr; - - if (CurrentChannel->LrDimmPresent == 0) { - return TRUE; - } - - TblPtr = NULL; - TableSize = 0; - PackageType = 0; - LogicalCpuid.Family = (UINT64) AMD_FAMILY_UNKNOWN; - MaxDimmPerCh = GetMaxDimmsPerChannel (NBPtr->RefPtr->PlatformMemoryConfiguration, NBPtr->MCTPtr->SocketId, CurrentChannel->ChannelID); - NOD = (UINT8) 1 << (MaxDimmPerCh - 1); - - i = 0; - // Obtain table pointer, table size, Logical Cpuid and PSC type according to NB type and package type. - while (EntryOfTables->TblEntryOfLRIBT[i] != NULL) { - if (((EntryOfTables->TblEntryOfLRIBT[i])->Header.NumOfDimm & NOD) != 0) { - LogicalCpuid = (EntryOfTables->TblEntryOfLRIBT[i])->Header.LogicalCpuid; - PackageType = (EntryOfTables->TblEntryOfLRIBT[i])->Header.PackageType; - // - // Determine if this is the expected NB Type - // - if (MemPIsIdSupported (NBPtr, LogicalCpuid, PackageType)) { - TblPtr = (PSCFG_L_IBT_ENTRY *) ((EntryOfTables->TblEntryOfLRIBT[i])->TBLPtr); - TableSize = (EntryOfTables->TblEntryOfLRIBT[i])->TableSize; - break; - } - } - i++; - } - - // Check whether no table entry is found. - if (EntryOfTables->TblEntryOfLRIBT[i] == NULL) { - IDS_HDT_CONSOLE (MEM_FLOW, "\nNo LRDIMM IBT table\n"); - return FALSE; - } - - CurDDRrate = (UINT32) (1 << (CurrentChannel->DCTPtr->Timings.Speed / 66)); - DDR3Voltage = (UINT8) (1 << CONVERT_VDDIO_TO_ENCODED (NBPtr->RefPtr->DDR3Voltage)); - RankTypeOfPopulatedDimm = MemPGetPsRankType (CurrentChannel); - - for (i = 0; i < TableSize; i++) { - MemPConstructRankTypeMap ((UINT16) TblPtr->Dimm0, (UINT16) TblPtr->Dimm1, (UINT16) TblPtr->Dimm2, &RankTypeInTable); - if (TblPtr->DimmPerCh == MaxDimmPerCh) { - if ((TblPtr->DDRrate & CurDDRrate) != 0) { - if ((TblPtr->VDDIO & DDR3Voltage) != 0) { - if ((RankTypeInTable & RankTypeOfPopulatedDimm) == RankTypeOfPopulatedDimm) { - NBPtr->PsPtr->F0RC8 = (UINT8) TblPtr->F0RC8; - NBPtr->PsPtr->F1RC0 = (UINT8) TblPtr->F1RC0; - NBPtr->PsPtr->F1RC1 = (UINT8) TblPtr->F1RC1; - NBPtr->PsPtr->F1RC2 = (UINT8) TblPtr->F1RC2; - break; - } - } - } - } - TblPtr++; - } - if (i == TableSize) { - IDS_HDT_CONSOLE (MEM_FLOW, "\nNo LRDIMM IBT entries\n"); - return FALSE; - } - - return TRUE; -} diff --git a/src/vendorcode/amd/agesa/f12/Proc/Mem/Ps/mplrnlr.c b/src/vendorcode/amd/agesa/f12/Proc/Mem/Ps/mplrnlr.c deleted file mode 100644 index 2c69768398..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/Mem/Ps/mplrnlr.c +++ /dev/null @@ -1,115 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * mplrnlr.c - * - * A sub-engine which extracts F0RC13[NumLogicalRanks] value for LRDIMM configuration. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: (Mem/Ps) - * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $ - * - **/ -/***************************************************************************** -* -* Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* *************************************************************************** -* -*/ -/* - *---------------------------------------------------------------------------- - * MODULES USED - * - *---------------------------------------------------------------------------- - */ - - - -#include "AGESA.h" -#include "AdvancedApi.h" -#include "amdlib.h" -#include "Ids.h" -#include "OptionMemory.h" -#include "PlatformMemoryConfiguration.h" -#include "mu.h" -#include "ma.h" -#include "mp.h" -#include "Filecode.h" -CODE_GROUP (G2_PEI) -RDATA_GROUP (G2_PEI) -#define FILECODE PROC_MEM_PS_MPLRNLR_FILECODE - - -/*---------------------------------------------------------------------------- - * DEFINITIONS AND MACROS - * - *---------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------- - * TYPEDEFS AND STRUCTURES - * - *---------------------------------------------------------------------------- - */ -/*---------------------------------------------------------------------------- - * PROTOTYPES OF LOCAL FUNCTIONS - * - *---------------------------------------------------------------------------- - */ -BOOLEAN -MemPGetLRNLR ( - IN OUT MEM_NB_BLOCK *NBPtr, - IN MEM_PSC_TABLE_BLOCK *EntryOfTables - ); - -/*---------------------------------------------------------------------------- - * EXPORTED FUNCTIONS - * - *---------------------------------------------------------------------------- - */ -/* -----------------------------------------------------------------------------*/ -/** - * - * A sub-function which extracts LRDIMM F0RC13[NumLogicalRanks] value from a input - * table and stores extracted value to a specific address. - * - * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK - * @param[in] *EntryOfTables - Pointer to MEM_PSC_TABLE_BLOCK - * - * @return TRUE - Succeed in extracting the table value - * @return FALSE - Fail to extract the table value - * - */ -BOOLEAN -MemPGetLRNLR ( - IN OUT MEM_NB_BLOCK *NBPtr, - IN MEM_PSC_TABLE_BLOCK *EntryOfTables - ) -{ - return TRUE; -} \ No newline at end of file diff --git a/src/vendorcode/amd/agesa/f12/Proc/Mem/Ps/mplrnpr.c b/src/vendorcode/amd/agesa/f12/Proc/Mem/Ps/mplrnpr.c deleted file mode 100644 index 25186e3a3f..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/Mem/Ps/mplrnpr.c +++ /dev/null @@ -1,115 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * mplrnpr.c - * - * A sub-engine which extracts F0RC13[NumPhysicalRanks] value for LRDIMM configuration. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: (Mem/Ps) - * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $ - * - **/ -/***************************************************************************** -* -* Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* *************************************************************************** -* -*/ -/* - *---------------------------------------------------------------------------- - * MODULES USED - * - *---------------------------------------------------------------------------- - */ - - - -#include "AGESA.h" -#include "AdvancedApi.h" -#include "amdlib.h" -#include "Ids.h" -#include "OptionMemory.h" -#include "PlatformMemoryConfiguration.h" -#include "mu.h" -#include "ma.h" -#include "mp.h" -#include "Filecode.h" -CODE_GROUP (G2_PEI) -RDATA_GROUP (G2_PEI) -#define FILECODE PROC_MEM_PS_MPLRNPR_FILECODE - - -/*---------------------------------------------------------------------------- - * DEFINITIONS AND MACROS - * - *---------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------- - * TYPEDEFS AND STRUCTURES - * - *---------------------------------------------------------------------------- - */ -/*---------------------------------------------------------------------------- - * PROTOTYPES OF LOCAL FUNCTIONS - * - *---------------------------------------------------------------------------- - */ -BOOLEAN -MemPGetLRNPR ( - IN OUT MEM_NB_BLOCK *NBPtr, - IN MEM_PSC_TABLE_BLOCK *EntryOfTables - ); - -/*---------------------------------------------------------------------------- - * EXPORTED FUNCTIONS - * - *---------------------------------------------------------------------------- - */ -/* -----------------------------------------------------------------------------*/ -/** - * - * A sub-function which extracts LRDIMM F0RC13[NumPhysicalRanks] value from a input - * table and stores extracted value to a specific address. - * - * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK - * @param[in] *EntryOfTables - Pointer to MEM_PSC_TABLE_BLOCK - * - * @return TRUE - Succeed in extracting the table value - * @return FALSE - Fail to extract the table value - * - */ -BOOLEAN -MemPGetLRNPR ( - IN OUT MEM_NB_BLOCK *NBPtr, - IN MEM_PSC_TABLE_BLOCK *EntryOfTables - ) -{ - return TRUE; -} \ No newline at end of file diff --git a/src/vendorcode/amd/agesa/f12/Proc/Mem/Ps/mpmaxfreq.c b/src/vendorcode/amd/agesa/f12/Proc/Mem/Ps/mpmaxfreq.c deleted file mode 100644 index f6f90f9ffd..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/Mem/Ps/mpmaxfreq.c +++ /dev/null @@ -1,260 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * mpmaxfreq.c - * - * A sub-engine which extracts max. frequency limit value. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: (Mem/Ps) - * @e \$Revision: 45233 $ @e \$Date: 2011-01-14 11:58:29 +0800 (Fri, 14 Jan 2011) $ - * - **/ -/***************************************************************************** -* -* Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* *************************************************************************** -* -*/ -/* - *---------------------------------------------------------------------------- - * MODULES USED - * - *---------------------------------------------------------------------------- - */ - - - -#include "AGESA.h" -#include "AdvancedApi.h" -#include "amdlib.h" -#include "Ids.h" -#include "cpuFamRegisters.h" -#include "cpuRegisters.h" -#include "OptionMemory.h" -#include "PlatformMemoryConfiguration.h" -#include "mu.h" -#include "ma.h" -#include "mp.h" -#include "Filecode.h" -CODE_GROUP (G2_PEI) -RDATA_GROUP (G2_PEI) -#define FILECODE PROC_MEM_PS_MPMAXFREQ_FILECODE - - -/*---------------------------------------------------------------------------- - * DEFINITIONS AND MACROS - * - *---------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------- - * TYPEDEFS AND STRUCTURES - * - *---------------------------------------------------------------------------- - */ -typedef struct { - UINT16 DimmPerCh:3; - UINT16 Dimms:3; - UINT16 SR:3; - UINT16 DR:3; - UINT16 QR:4; -} CDNMaxFreq; - -typedef struct { - UINT16 DimmPerCh:3; - UINT16 Dimms:3; - UINT16 LR:10; -} CDNLMaxFreq; -/*---------------------------------------------------------------------------- - * PROTOTYPES OF LOCAL FUNCTIONS - * - *---------------------------------------------------------------------------- - */ -BOOLEAN -MemPGetMaxFreqSupported ( - IN OUT MEM_NB_BLOCK *NBPtr, - IN MEM_PSC_TABLE_BLOCK *EntryOfTables - ); - -/*---------------------------------------------------------------------------- - * EXPORTED FUNCTIONS - * - *---------------------------------------------------------------------------- - */ - -/* -----------------------------------------------------------------------------*/ -/** - * - * A sub-function which extracts the value of max frequency supported from a input table and - * compares it with DCTPtr->Timings.TargetSpeed - * - * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK - * @param[in] *EntryOfTables - Pointer to MEM_PSC_TABLE_BLOCK - * - * @return TRUE - Succeed in extracting the table value - * @return FALSE - Fail to extract the table value - * - */ -BOOLEAN -MemPGetMaxFreqSupported ( - IN OUT MEM_NB_BLOCK *NBPtr, - IN MEM_PSC_TABLE_BLOCK *EntryOfTables - ) -{ - UINT8 i; - UINT8 MaxDimmPerCh; - UINT8 NOD; - UINT8 TableSize; - PSCFG_TYPE Type; - UINT16 CDN; - UINT16 MaxFreqSupported; - UINT16 *SpeedArray; - UINT8 DDR3Voltage; - UINT8 CurrentVoltage; - DIMM_TYPE DimmType; - CPU_LOGICAL_ID LogicalCpuid; - UINT8 PackageType; - PSCFG_MAXFREQ_ENTRY *TblPtr; - CH_DEF_STRUCT *CurrentChannel; - - CurrentChannel = NBPtr->ChannelPtr; - - Type = PSCFG_MAXFREQ; - TblPtr = NULL; - TableSize = 0; - PackageType = 0; - LogicalCpuid.Family = (UINT64) AMD_FAMILY_UNKNOWN; - - MaxDimmPerCh = GetMaxDimmsPerChannel (NBPtr->RefPtr->PlatformMemoryConfiguration, NBPtr->MCTPtr->SocketId, CurrentChannel->ChannelID); - NOD = (UINT8) 1 << (MaxDimmPerCh - 1); - - if (CurrentChannel->RegDimmPresent != 0) { - DimmType = RDIMM_TYPE; - } else if (CurrentChannel->SODimmPresent != 0) { - DimmType = SODIMM_TYPE; - if (FindPSOverrideEntry (NBPtr->RefPtr->PlatformMemoryConfiguration, PSO_SOLDERED_DOWN_SODIMM_TYPE, NBPtr->MCTPtr->SocketId, NBPtr->ChannelPtr->ChannelID) != NULL) { - DimmType = SODWN_SODIMM_TYPE; - } - } else if (CurrentChannel->LrDimmPresent != 0) { - DimmType = LRDIMM_TYPE; - } else { - DimmType = UDIMM_TYPE; - } - - i = 0; - // Obtain table pointer, table size, Logical Cpuid and PSC type according to Dimm, NB and package type. - while (EntryOfTables->TblEntryOfMaxFreq[i] != NULL) { - if (((EntryOfTables->TblEntryOfMaxFreq[i])->Header.DimmType & DimmType) != 0) { - if (((EntryOfTables->TblEntryOfMaxFreq[i])->Header.NumOfDimm & NOD) != 0) { - // - // Determine if this is the expected NB Type - // - LogicalCpuid = (EntryOfTables->TblEntryOfMaxFreq[i])->Header.LogicalCpuid; - PackageType = (EntryOfTables->TblEntryOfMaxFreq[i])->Header.PackageType; - if (MemPIsIdSupported (NBPtr, LogicalCpuid, PackageType)) { - TblPtr = (PSCFG_MAXFREQ_ENTRY *) ((EntryOfTables->TblEntryOfMaxFreq[i])->TBLPtr); - TableSize = (EntryOfTables->TblEntryOfMaxFreq[i])->TableSize; - Type = (EntryOfTables->TblEntryOfMaxFreq[i])->Header.PSCType; - break; - } - } - } - i++; - } - - // Check whether no table entry is found. - if (EntryOfTables->TblEntryOfMaxFreq[i] == NULL) { - IDS_HDT_CONSOLE (MEM_FLOW, "\nNo MaxFreq table\n"); - return FALSE; - } - - MaxFreqSupported = DDR1866_FREQUENCY; - CDN = 0; - DDR3Voltage = (UINT8) CONVERT_VDDIO_TO_ENCODED (NBPtr->RefPtr->DDR3Voltage); - - // Construct the condition value - ((CDNMaxFreq *)&CDN)->DimmPerCh = MaxDimmPerCh; - ((CDNMaxFreq *)&CDN)->Dimms = CurrentChannel->Dimms; - if (Type == PSCFG_MAXFREQ) { - for (i = 0; i < MAX_DIMMS_PER_CHANNEL; i++) { - if ((CurrentChannel->DimmSRPresent & (UINT8) (1 << i)) != 0) { - ((CDNMaxFreq *)&CDN)->SR += 1; - } - if ((CurrentChannel->DimmDrPresent & (UINT16) (1 << i)) != 0) { - ((CDNMaxFreq *)&CDN)->DR += 1; - } - if ((CurrentChannel->DimmQrPresent & (UINT16) (1 << i)) != 0) { - if (i < 2) { - ((CDNMaxFreq *)&CDN)->QR += 1; - } - } - } - } else { - ((CDNLMaxFreq *)&CDN)->LR = CurrentChannel->Dimms; - } - - for (i = 0; i < TableSize; i++) { - if (CDN == ((Type == PSCFG_MAXFREQ) ? TblPtr->MAXFREQ_ENTRY.CDN : - ((PSCFG_LR_MAXFREQ_ENTRY *)TblPtr)->LR_MAXFREQ_ENTRY.CDN)) { - if (Type == PSCFG_MAXFREQ) { - SpeedArray = TblPtr->MAXFREQ_ENTRY.Speed; - } else { - SpeedArray = ((PSCFG_LR_MAXFREQ_ENTRY *)TblPtr)->LR_MAXFREQ_ENTRY.Speed; - } - if (NBPtr->SharedPtr->VoltageMap != VDDIO_DETERMINED) { - IDS_HDT_CONSOLE (MEM_FLOW, "\nCheck speed supported for each VDDIO for Node%d DCT%d: ", NBPtr->Node, NBPtr->Dct); - for (CurrentVoltage = VOLT1_5_ENCODED_VAL; CurrentVoltage <= VOLT1_25_ENCODED_VAL; CurrentVoltage ++) { - if (NBPtr->SharedPtr->VoltageMap & (1 << CurrentVoltage)) { - IDS_HDT_CONSOLE (MEM_FLOW, "%s -> %dMHz ", (CurrentVoltage == VOLT1_5_ENCODED_VAL) ? "1.5V" : ((CurrentVoltage == VOLT1_35_ENCODED_VAL) ? "1.35V" : "1.25V"), SpeedArray[CurrentVoltage]); - if (NBPtr->DCTPtr->Timings.TargetSpeed > SpeedArray[CurrentVoltage]) { - MaxFreqSupported = SpeedArray[CurrentVoltage]; - } else { - MaxFreqSupported = NBPtr->DCTPtr->Timings.TargetSpeed; - } - if (NBPtr->MaxFreqVDDIO[CurrentVoltage] > MaxFreqSupported) { - NBPtr->MaxFreqVDDIO[CurrentVoltage] = MaxFreqSupported; - } - } else { - NBPtr->MaxFreqVDDIO[CurrentVoltage] = 0; - } - } - IDS_HDT_CONSOLE (MEM_FLOW, "\n"); - } - ASSERT (DDR3Voltage <= VOLT1_25_ENCODED_VAL); - MaxFreqSupported = SpeedArray[DDR3Voltage]; - break; - } - TblPtr++; - } - - if (NBPtr->DCTPtr->Timings.TargetSpeed > MaxFreqSupported) { - NBPtr->DCTPtr->Timings.TargetSpeed = MaxFreqSupported; - } - return TRUE; -} \ No newline at end of file diff --git a/src/vendorcode/amd/agesa/f12/Proc/Mem/Ps/mpmr0.c b/src/vendorcode/amd/agesa/f12/Proc/Mem/Ps/mpmr0.c deleted file mode 100644 index a6c8b40f9c..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/Mem/Ps/mpmr0.c +++ /dev/null @@ -1,183 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * mpmr0.c - * - * A sub-engine which extracts MR0[WR] and MR0[CL] value. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: (Mem/Ps) - * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $ - * - **/ -/***************************************************************************** -* -* Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* *************************************************************************** -* -*/ -/* - *---------------------------------------------------------------------------- - * MODULES USED - * - *---------------------------------------------------------------------------- - */ - - - -#include "AGESA.h" -#include "AdvancedApi.h" -#include "amdlib.h" -#include "Ids.h" -#include "OptionMemory.h" -#include "PlatformMemoryConfiguration.h" -#include "mu.h" -#include "ma.h" -#include "mp.h" -#include "Filecode.h" -CODE_GROUP (G2_PEI) -RDATA_GROUP (G2_PEI) -#define FILECODE PROC_MEM_PS_MPMR0_FILECODE - - -/*---------------------------------------------------------------------------- - * DEFINITIONS AND MACROS - * - *---------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------- - * TYPEDEFS AND STRUCTURES - * - *---------------------------------------------------------------------------- - */ -/*---------------------------------------------------------------------------- - * PROTOTYPES OF LOCAL FUNCTIONS - * - *---------------------------------------------------------------------------- - */ -BOOLEAN -MemPGetMR0WrCL ( - IN OUT MEM_NB_BLOCK *NBPtr, - IN MEM_PSC_TABLE_BLOCK *EntryOfTables - ); - -/*---------------------------------------------------------------------------- - * EXPORTED FUNCTIONS - * - *---------------------------------------------------------------------------- - */ -/* -----------------------------------------------------------------------------*/ -/** - * - * A sub-function which extracts MR0[WR] or MR0[CL] value from a input table and store the - * value to a specific address. - * - * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK - * @param[in] *EntryOfTables - Pointer to MEM_PSC_TABLE_BLOCK - * - * @return TRUE - Succeed in extracting the table value - * @return FALSE - Fail to extract the table value - * - */ -BOOLEAN -MemPGetMR0WrCL ( - IN OUT MEM_NB_BLOCK *NBPtr, - IN MEM_PSC_TABLE_BLOCK *EntryOfTables - ) -{ - - UINT8 i; - UINT8 j; - UINT8 p; - UINT32 Value32; - UINT8 TableSize; - PSCFG_TYPE Type; - CPU_LOGICAL_ID LogicalCpuid; - UINT8 PackageType; - PSCFG_MR0CL_ENTRY *TblPtr; - PSC_TBL_ENTRY **ptr; - CH_DEF_STRUCT *CurrentChannel; - - CurrentChannel = NBPtr->ChannelPtr; - TblPtr = NULL; - TableSize = 0; - - // Extract MR0[WR] value, then MR0[CL] value - for (i = 0; i < 2; i++) { - if (i == 0) { - ptr = EntryOfTables->TblEntryOfMR0WR; - Type = PSCFG_MR0WR; - } else { - ptr = EntryOfTables->TblEntryOfMR0CL; - Type = PSCFG_MR0CL; - } - - p = 0; - // Obtain table pointer, table size, Logical Cpuid and PSC type according to Dimm, NB and package type. - while (ptr[p] != NULL) { - // - // Determine if this is the expected NB Type - // - LogicalCpuid = (ptr[p])->Header.LogicalCpuid; - PackageType = (ptr[p])->Header.PackageType; - if (MemPIsIdSupported (NBPtr, LogicalCpuid, PackageType)) { - TblPtr = (PSCFG_MR0CL_ENTRY *) ((ptr[p])->TBLPtr); - TableSize = (ptr[p])->TableSize; - break; - } - p++; - } - - // Check whether no table entry is found. - if (ptr[p] == NULL) { - IDS_HDT_CONSOLE (MEM_FLOW, "\nNo MR0 table\n"); - return FALSE; - } - - Value32 = (Type == PSCFG_MR0WR) ? NBPtr->GetBitField (NBPtr, BFTwrDDR3) : NBPtr->GetBitField (NBPtr, BFTcl); - for (j = 0; j < TableSize; j++, TblPtr++) { - if (Value32 == (UINT32) TblPtr->Timing) { - if (Type == PSCFG_MR0WR) { - NBPtr->PsPtr->MR0WR = (UINT8) TblPtr->Value; - break; - } else { - NBPtr->PsPtr->MR0CL31 = (UINT8) TblPtr->Value; - NBPtr->PsPtr->MR0CL0 = (UINT8) TblPtr->Value1; - break; - } - } - } - if (j == TableSize) { - IDS_HDT_CONSOLE (MEM_FLOW, "\nNo MR0 entries\n"); - return FALSE; - } - } - - return TRUE; -} \ No newline at end of file diff --git a/src/vendorcode/amd/agesa/f12/Proc/Mem/Ps/mpodtpat.c b/src/vendorcode/amd/agesa/f12/Proc/Mem/Ps/mpodtpat.c deleted file mode 100644 index 0f1a4a99fb..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/Mem/Ps/mpodtpat.c +++ /dev/null @@ -1,195 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * mpodtpat.c - * - * A sub-engine which extracts ODT pattern value. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: (Mem/Ps) - * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $ - * - **/ -/***************************************************************************** -* -* Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* *************************************************************************** -* -*/ -/* - *---------------------------------------------------------------------------- - * MODULES USED - * - *---------------------------------------------------------------------------- - */ - - - -#include "AGESA.h" -#include "AdvancedApi.h" -#include "amdlib.h" -#include "Ids.h" -#include "cpuFamRegisters.h" -#include "cpuRegisters.h" -#include "OptionMemory.h" -#include "PlatformMemoryConfiguration.h" -#include "mu.h" -#include "ma.h" -#include "mp.h" -#include "Filecode.h" -CODE_GROUP (G2_PEI) -RDATA_GROUP (G2_PEI) -#define FILECODE PROC_MEM_PS_MPODTPAT_FILECODE - - -/*---------------------------------------------------------------------------- - * DEFINITIONS AND MACROS - * - *---------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------- - * TYPEDEFS AND STRUCTURES - * - *---------------------------------------------------------------------------- - */ -/*---------------------------------------------------------------------------- - * PROTOTYPES OF LOCAL FUNCTIONS - * - *---------------------------------------------------------------------------- - */ -BOOLEAN -MemPGetODTPattern ( - IN OUT MEM_NB_BLOCK *NBPtr, - IN MEM_PSC_TABLE_BLOCK *EntryOfTables - ); - -/*---------------------------------------------------------------------------- - * EXPORTED FUNCTIONS - * - *---------------------------------------------------------------------------- - */ -/* -----------------------------------------------------------------------------*/ -/** - * - * A sub-function which extracts ODT Pattern value from a input table and stores extracted - * value to a specific address. - * - * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK - * @param[in] *EntryOfTables - Pointer to MEM_PSC_TABLE_BLOCK - * - * @return TRUE - Table values can be extracted per dimm population and ranks type. - * @return FALSE - Table values cannot be extracted per dimm population and ranks type. - * - */ -BOOLEAN -MemPGetODTPattern ( - IN OUT MEM_NB_BLOCK *NBPtr, - IN MEM_PSC_TABLE_BLOCK *EntryOfTables - ) -{ - UINT8 i; - UINT16 RankTypeInTable; - UINT16 RankTypeOfPopulatedDimm; - UINT8 MaxDimmPerCh; - UINT8 NOD; - UINT8 TableSize; - DIMM_TYPE DimmType; - CPU_LOGICAL_ID LogicalCpuid; - UINT8 PackageType; - PSCFG_3D_ODTPAT_ENTRY *TblPtr; - CH_DEF_STRUCT *CurrentChannel; - - CurrentChannel = NBPtr->ChannelPtr; - - TblPtr = NULL; - TableSize = 0; - PackageType = 0; - LogicalCpuid.Family = (UINT64) AMD_FAMILY_UNKNOWN; - MaxDimmPerCh = GetMaxDimmsPerChannel (NBPtr->RefPtr->PlatformMemoryConfiguration, NBPtr->MCTPtr->SocketId, CurrentChannel->ChannelID); - NOD = (UINT8) 1 << (MaxDimmPerCh - 1); - - if (CurrentChannel->RegDimmPresent != 0) { - DimmType = RDIMM_TYPE; - } else if (CurrentChannel->SODimmPresent != 0) { - DimmType = SODIMM_TYPE; - } else if (CurrentChannel->LrDimmPresent != 0) { - DimmType = LRDIMM_TYPE; - } else { - DimmType = UDIMM_TYPE; - } - - i = 0; - // Obtain table pointer, table size, Logical Cpuid and PSC type according to Dimm, NB and package type. - while (EntryOfTables->TblEntryOfODTPattern[i] != NULL) { - if (((EntryOfTables->TblEntryOfODTPattern[i])->Header.DimmType & DimmType) != 0) { - if (((EntryOfTables->TblEntryOfODTPattern[i])->Header.NumOfDimm & NOD) != 0) { - // - // Determine if this is the expected NB Type - // - LogicalCpuid = (EntryOfTables->TblEntryOfODTPattern[i])->Header.LogicalCpuid; - PackageType = (EntryOfTables->TblEntryOfODTPattern[i])->Header.PackageType; - if (MemPIsIdSupported (NBPtr, LogicalCpuid, PackageType)) { - TblPtr = (PSCFG_3D_ODTPAT_ENTRY *) ((EntryOfTables->TblEntryOfODTPattern[i])->TBLPtr); - TableSize = (EntryOfTables->TblEntryOfODTPattern[i])->TableSize; - break; - } - } - } - i++; - } - - // Check whether no table entry is found. - if (EntryOfTables->TblEntryOfODTPattern[i] == NULL) { - IDS_HDT_CONSOLE (MEM_FLOW, "\nNo ODT table\n"); - return FALSE; - } - - RankTypeOfPopulatedDimm = MemPGetPsRankType (CurrentChannel); - - for (i = 0; i < TableSize; i++) { - MemPConstructRankTypeMap ((UINT16) TblPtr->Dimm0, (UINT16) TblPtr->Dimm1, (UINT16) TblPtr->Dimm2, &RankTypeInTable); - if ((RankTypeInTable & RankTypeOfPopulatedDimm) == RankTypeOfPopulatedDimm) { - CurrentChannel->PhyRODTCSHigh = TblPtr->RdODTCSHigh; - CurrentChannel->PhyRODTCSLow = TblPtr->RdODTCSLow; - CurrentChannel->PhyWODTCSHigh = TblPtr->WrODTCSHigh; - CurrentChannel->PhyWODTCSLow = TblPtr->WrODTCSLow; - - //WL ODT - CurrentChannel->PhyWLODT[0] = (UINT8) (CurrentChannel->PhyWODTCSLow & 0x0F); - CurrentChannel->PhyWLODT[1] = (UINT8) ((CurrentChannel->PhyWODTCSLow >> 16) & 0x0F); - CurrentChannel->PhyWLODT[2] = (UINT8) (CurrentChannel->PhyWODTCSHigh & 0x0F); - CurrentChannel->PhyWLODT[3] = (UINT8) ((CurrentChannel->PhyWODTCSHigh >> 16) & 0x0F); - - return TRUE; - } - TblPtr++; - } - IDS_HDT_CONSOLE (MEM_FLOW, "\nNo ODT entries\n"); - return FALSE; -} \ No newline at end of file diff --git a/src/vendorcode/amd/agesa/f12/Proc/Mem/Ps/mprc10opspd.c b/src/vendorcode/amd/agesa/f12/Proc/Mem/Ps/mprc10opspd.c deleted file mode 100644 index df92a4b535..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/Mem/Ps/mprc10opspd.c +++ /dev/null @@ -1,167 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * mprc10opspd.c - * - * A sub-engine which extracts RC10 operating speed value for RDIMM configuration. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: (Mem/Ps) - * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $ - * - **/ -/***************************************************************************** -* -* Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* *************************************************************************** -* -*/ -/* - *---------------------------------------------------------------------------- - * MODULES USED - * - *---------------------------------------------------------------------------- - */ - - - -#include "AGESA.h" -#include "AdvancedApi.h" -#include "amdlib.h" -#include "Ids.h" -#include "cpuFamRegisters.h" -#include "cpuRegisters.h" -#include "OptionMemory.h" -#include "PlatformMemoryConfiguration.h" -#include "mu.h" -#include "ma.h" -#include "mp.h" -#include "Filecode.h" -CODE_GROUP (G2_PEI) -RDATA_GROUP (G2_PEI) -#define FILECODE PROC_MEM_PS_MPRC10OPSPD_FILECODE - - -/*---------------------------------------------------------------------------- - * DEFINITIONS AND MACROS - * - *---------------------------------------------------------------------------- - */ -/*---------------------------------------------------------------------------- - * TYPEDEFS AND STRUCTURES - * - *---------------------------------------------------------------------------- - */ -/*---------------------------------------------------------------------------- - * PROTOTYPES OF LOCAL FUNCTIONS - * - *---------------------------------------------------------------------------- - */ -BOOLEAN -MemPGetRC10OpSpd ( - IN OUT MEM_NB_BLOCK *NBPtr, - IN MEM_PSC_TABLE_BLOCK *EntryOfTables - ); - -/*---------------------------------------------------------------------------- - * EXPORTED FUNCTIONS - * - *---------------------------------------------------------------------------- - */ -/* -----------------------------------------------------------------------------*/ -/** - * - * A sub-function which extracts RC10 operating speed value from a input table and stores extracted - * value to a specific address. - * - * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK - * @param[in] *EntryOfTables - Pointer to MEM_PSC_TABLE_BLOCK - * - * @return TRUE - Succeed in extracting the table value - * @return FALSE - Fail to extract the table value - * - */ -BOOLEAN -MemPGetRC10OpSpd ( - IN OUT MEM_NB_BLOCK *NBPtr, - IN MEM_PSC_TABLE_BLOCK *EntryOfTables - ) -{ - UINT8 i; - UINT8 TableSize; - UINT32 CurDDRrate; - CPU_LOGICAL_ID LogicalCpuid; - UINT8 PackageType; - PSCFG_OPSPD_ENTRY *TblPtr; - CH_DEF_STRUCT *CurrentChannel; - - CurrentChannel = NBPtr->ChannelPtr; - - if (CurrentChannel->RegDimmPresent == 0) { - return TRUE; - } - - TblPtr = NULL; - TableSize = 0; - PackageType = 0; - LogicalCpuid.Family = (UINT64) AMD_FAMILY_UNKNOWN; - - i = 0; - // Obtain table pointer, table size, Logical Cpuid and PSC type according to NB type and package type. - while (EntryOfTables->TblEntryOfRC10OpSpeed[i] != NULL) { - LogicalCpuid = (EntryOfTables->TblEntryOfRC10OpSpeed[i])->Header.LogicalCpuid; - PackageType = (EntryOfTables->TblEntryOfRC10OpSpeed[i])->Header.PackageType; - // - // Determine if this is the expected NB Type - // - if (MemPIsIdSupported (NBPtr, LogicalCpuid, PackageType)) { - TblPtr = (PSCFG_OPSPD_ENTRY *) ((EntryOfTables->TblEntryOfRC10OpSpeed[i])->TBLPtr); - TableSize = (EntryOfTables->TblEntryOfRC10OpSpeed[i])->TableSize; - break; - } - i++; - } - - // Check whether no table entry is found. - if (EntryOfTables->TblEntryOfRC10OpSpeed[i] == NULL) { - IDS_HDT_CONSOLE (MEM_FLOW, "\nNo RC10 Op Speed table\n"); - return FALSE; - } - - CurDDRrate = (UINT32) (1 << (CurrentChannel->DCTPtr->Timings.Speed / 66)); - - for (i = 0; i < TableSize; i++) { - if ((TblPtr->DDRrate & CurDDRrate) != 0) { - NBPtr->PsPtr->RC10OpSpd = TblPtr->OPSPD; - return TRUE; - } - TblPtr++; - } - IDS_HDT_CONSOLE (MEM_FLOW, "\nNo RC10 Op Speed entries\n"); - return FALSE; -} \ No newline at end of file diff --git a/src/vendorcode/amd/agesa/f12/Proc/Mem/Ps/mprc2ibt.c b/src/vendorcode/amd/agesa/f12/Proc/Mem/Ps/mprc2ibt.c deleted file mode 100644 index ac4e345e8e..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/Mem/Ps/mprc2ibt.c +++ /dev/null @@ -1,214 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * mprc2ibt.c - * - * A sub-engine which extracts RC2[IBT] value for RDIMM configuration. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: (Mem/Ps) - * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $ - * - **/ -/***************************************************************************** -* -* Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* *************************************************************************** -* -*/ -/* - *---------------------------------------------------------------------------- - * MODULES USED - * - *---------------------------------------------------------------------------- - */ - - - -#include "AGESA.h" -#include "AdvancedApi.h" -#include "amdlib.h" -#include "Ids.h" -#include "cpuFamRegisters.h" -#include "cpuRegisters.h" -#include "OptionMemory.h" -#include "PlatformMemoryConfiguration.h" -#include "mu.h" -#include "ma.h" -#include "mp.h" -#include "Filecode.h" -CODE_GROUP (G2_PEI) -RDATA_GROUP (G2_PEI) -#define FILECODE PROC_MEM_PS_MPRC2IBT_FILECODE - - -/*---------------------------------------------------------------------------- - * DEFINITIONS AND MACROS - * - *---------------------------------------------------------------------------- - */ -/*---------------------------------------------------------------------------- - * TYPEDEFS AND STRUCTURES - * - *---------------------------------------------------------------------------- - */ -/*---------------------------------------------------------------------------- - * PROTOTYPES OF LOCAL FUNCTIONS - * - *---------------------------------------------------------------------------- - */ -BOOLEAN -MemPGetRC2IBT ( - IN OUT MEM_NB_BLOCK *NBPtr, - IN MEM_PSC_TABLE_BLOCK *EntryOfTables - ); - -/*---------------------------------------------------------------------------- - * EXPORTED FUNCTIONS - * - *---------------------------------------------------------------------------- - */ -/* -----------------------------------------------------------------------------*/ -/** - * - * A sub-function which extracts RC2[IBT] value from a input table and stores extracted - * value to a specific address. - * - * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK - * @param[in] *EntryOfTables Pointer to MEM_PSC_TABLE_BLOCK - * - * @return TRUE - Table values can be extracted for all present dimms/ranks - * @return FALSE - Table values cannot be extracted for all present dimms/ranks - * - */ -BOOLEAN -MemPGetRC2IBT ( - IN OUT MEM_NB_BLOCK *NBPtr, - IN MEM_PSC_TABLE_BLOCK *EntryOfTables - ) -{ - UINT8 i; - UINT8 MaxDimmPerCh; - UINT8 NOD; - UINT8 DimmIndex; - UINT8 TableSize; - UINT32 CurDDRrate; - UINT8 DDR3Voltage; - UINT16 RankTypeOfPopulatedDimm; - UINT16 RankTypeInTable; - CPU_LOGICAL_ID LogicalCpuid; - UINT8 PackageType; - UINT8 TgtDimmType; - UINT8 NumOfReg; - PSCFG_MR2IBT_ENTRY *TblPtr; - PSCFG_MR2IBT_ENTRY *OrgTblPtr; - CH_DEF_STRUCT *CurrentChannel; - - CurrentChannel = NBPtr->ChannelPtr; - - if (CurrentChannel->RegDimmPresent == 0) { - return TRUE; - } - - TblPtr = NULL; - TableSize = 0; - PackageType = 0; - LogicalCpuid.Family = (UINT64) AMD_FAMILY_UNKNOWN; - MaxDimmPerCh = GetMaxDimmsPerChannel (NBPtr->RefPtr->PlatformMemoryConfiguration, NBPtr->MCTPtr->SocketId, CurrentChannel->ChannelID); - NOD = (UINT8) 1 << (MaxDimmPerCh - 1); - - i = 0; - // Obtain table pointer, table size, Logical Cpuid and PSC type according to NB type and package type. - while (EntryOfTables->TblEntryOfRC2IBT[i] != NULL) { - if (((EntryOfTables->TblEntryOfRC2IBT[i])->Header.NumOfDimm & NOD) != 0) { - LogicalCpuid = (EntryOfTables->TblEntryOfRC2IBT[i])->Header.LogicalCpuid; - PackageType = (EntryOfTables->TblEntryOfRC2IBT[i])->Header.PackageType; - // - // Determine if this is the expected NB Type - // - if (MemPIsIdSupported (NBPtr, LogicalCpuid, PackageType)) { - TblPtr = (PSCFG_MR2IBT_ENTRY *) ((EntryOfTables->TblEntryOfRC2IBT[i])->TBLPtr); - TableSize = (EntryOfTables->TblEntryOfRC2IBT[i])->TableSize; - break; - } - } - i++; - } - - // Check whether no table entry is found. - if (EntryOfTables->TblEntryOfRC2IBT[i] == NULL) { - IDS_HDT_CONSOLE (MEM_FLOW, "\nNo RC2 IBT table\n"); - return FALSE; - } - - CurDDRrate = (UINT32) (1 << (CurrentChannel->DCTPtr->Timings.Speed / 66)); - DDR3Voltage = (UINT8) (1 << CONVERT_VDDIO_TO_ENCODED (NBPtr->RefPtr->DDR3Voltage)); - RankTypeOfPopulatedDimm = MemPGetPsRankType (CurrentChannel); - - OrgTblPtr = TblPtr; - for (DimmIndex = 0; DimmIndex < MAX_DIMMS_PER_CHANNEL; DimmIndex++) { - TblPtr = OrgTblPtr; - NumOfReg = NBPtr->PsPtr->NumOfReg[DimmIndex]; - if ((CurrentChannel->ChDimmValid& (UINT8) (1 << DimmIndex)) != 0) { - if ((CurrentChannel->DimmQrPresent & (UINT8) (1 << DimmIndex)) != 0) { - TgtDimmType = DIMM_QR; - } else if ((CurrentChannel->DimmDrPresent & (UINT8) (1 << DimmIndex)) != 0) { - TgtDimmType = DIMM_DR; - } else { - TgtDimmType = DIMM_SR; - } - - for (i = 0; i < TableSize; i++) { - MemPConstructRankTypeMap ((UINT16) TblPtr->Dimm0, (UINT16) TblPtr->Dimm1, (UINT16) TblPtr->Dimm2, &RankTypeInTable); - if (TblPtr->DimmPerCh == MaxDimmPerCh) { - if ((TblPtr->DDRrate & CurDDRrate) != 0) { - if ((TblPtr->VDDIO & DDR3Voltage) != 0) { - if ((RankTypeInTable & RankTypeOfPopulatedDimm) == RankTypeOfPopulatedDimm) { - if ((TblPtr->Dimm & TgtDimmType) != 0) { - // If TblPtr->NumOfReg == 0x0F, that means the condition will be TRUE regardless of NumRegisters in DIMM - if ((TblPtr->NumOfReg == 0xF) || (TblPtr->NumOfReg == NumOfReg)) { - CurrentChannel->CtrlWrd02[DimmIndex] = (UINT8) ((TblPtr->IBT & 0x1) << 2); - CurrentChannel->CtrlWrd08[DimmIndex] = (UINT8) ((TblPtr->IBT & 0xE) >> 1); - break; - } - } - } - } - } - } - TblPtr++; - } - if (i == TableSize) { - IDS_HDT_CONSOLE (MEM_FLOW, "\nNo RC2 IBT entries\n"); - return FALSE; - } - } - } - - return TRUE; -} \ No newline at end of file diff --git a/src/vendorcode/amd/agesa/f12/Proc/Mem/Ps/mprtt.c b/src/vendorcode/amd/agesa/f12/Proc/Mem/Ps/mprtt.c deleted file mode 100644 index 338f2a0301..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/Mem/Ps/mprtt.c +++ /dev/null @@ -1,235 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * mprtt.c - * - * A sub-engine which extracts RttNom and RttWr (Dram Term and Dynamic Dram Term) value. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: (Mem/Ps) - * @e \$Revision: 45233 $ @e \$Date: 2011-01-14 11:58:29 +0800 (Fri, 14 Jan 2011) $ - * - **/ -/***************************************************************************** -* -* Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* *************************************************************************** -* -*/ -/* - *---------------------------------------------------------------------------- - * MODULES USED - * - *---------------------------------------------------------------------------- - */ - - - -#include "AGESA.h" -#include "AdvancedApi.h" -#include "amdlib.h" -#include "Ids.h" -#include "cpuFamRegisters.h" -#include "cpuRegisters.h" -#include "OptionMemory.h" -#include "PlatformMemoryConfiguration.h" -#include "mu.h" -#include "ma.h" -#include "mp.h" -#include "Filecode.h" -CODE_GROUP (G2_PEI) -RDATA_GROUP (G2_PEI) - -#define FILECODE PROC_MEM_PS_MPRTT_FILECODE - - -/*---------------------------------------------------------------------------- - * DEFINITIONS AND MACROS - * - *---------------------------------------------------------------------------- - */ -#define _DONT_CARE 0xFF - -/*---------------------------------------------------------------------------- - * TYPEDEFS AND STRUCTURES - * - *---------------------------------------------------------------------------- - */ -/*---------------------------------------------------------------------------- - * PROTOTYPES OF LOCAL FUNCTIONS - * - *---------------------------------------------------------------------------- - */ -BOOLEAN -MemPGetRttNomWr ( - IN OUT MEM_NB_BLOCK *NBPtr, - IN MEM_PSC_TABLE_BLOCK *EntryOfTables - ); - -/*---------------------------------------------------------------------------- - * EXPORTED FUNCTIONS - * - *---------------------------------------------------------------------------- - */ - -/* -----------------------------------------------------------------------------*/ -/** - * - * A sub-function which extracts RttNom and RttWr value from a input table and stores extracted - * value to a specific address. - * - * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK - * @param[in] *EntryOfTables - Pointer to MEM_PSC_TABLE_BLOCK - * - * @return TRUE - Table values can be extracted for all present dimms/ranks - * @return FALSE - Table values cannot be extracted for all present dimms/ranks - * - */ -BOOLEAN -MemPGetRttNomWr ( - IN OUT MEM_NB_BLOCK *NBPtr, - IN MEM_PSC_TABLE_BLOCK *EntryOfTables - ) -{ - UINT8 i; - UINT8 MaxDimmPerCh; - UINT8 NOD; - UINT8 TableSize; - UINT32 CurDDRrate; - UINT8 DDR3Voltage; - UINT16 RankTypeOfPopulatedDimm; - UINT16 RankTypeInTable; - DIMM_TYPE DimmType; - CPU_LOGICAL_ID LogicalCpuid; - UINT8 PackageType; - UINT8 TgtDimmType; - UINT8 TgtRank; - UINT8 Chipsel; - PSCFG_RTT_ENTRY *TblPtr; - PSCFG_RTT_ENTRY *OrgTblPtr; - CH_DEF_STRUCT *CurrentChannel; - - CurrentChannel = NBPtr->ChannelPtr; - - TblPtr = NULL; - TableSize = 0; - PackageType = 0; - LogicalCpuid.Family = (UINT64) AMD_FAMILY_UNKNOWN; - MaxDimmPerCh = GetMaxDimmsPerChannel (NBPtr->RefPtr->PlatformMemoryConfiguration, NBPtr->MCTPtr->SocketId, CurrentChannel->ChannelID); - NOD = (UINT8) 1 << (MaxDimmPerCh - 1); - - if (CurrentChannel->RegDimmPresent != 0) { - DimmType = RDIMM_TYPE; - } else if (CurrentChannel->SODimmPresent != 0) { - DimmType = SODIMM_TYPE; - if (FindPSOverrideEntry (NBPtr->RefPtr->PlatformMemoryConfiguration, PSO_SOLDERED_DOWN_SODIMM_TYPE, NBPtr->MCTPtr->SocketId, NBPtr->ChannelPtr->ChannelID) != NULL) { - DimmType = SODWN_SODIMM_TYPE; - } - } else if (CurrentChannel->LrDimmPresent != 0) { - DimmType = LRDIMM_TYPE; - } else { - DimmType = UDIMM_TYPE; - } - - i = 0; - // Obtain table pointer, table size, Logical Cpuid and PSC type according to Dimm, NB and package type. - while (EntryOfTables->TblEntryOfDramTerm[i] != NULL) { - if (((EntryOfTables->TblEntryOfDramTerm[i])->Header.DimmType & DimmType) != 0) { - if (((EntryOfTables->TblEntryOfDramTerm[i])->Header.NumOfDimm & NOD) != 0) { - // - // Determine if this is the expected NB Type - // - LogicalCpuid = (EntryOfTables->TblEntryOfDramTerm[i])->Header.LogicalCpuid; - PackageType = (EntryOfTables->TblEntryOfDramTerm[i])->Header.PackageType; - if (MemPIsIdSupported (NBPtr, LogicalCpuid, PackageType)) { - TblPtr = (PSCFG_RTT_ENTRY *) ((EntryOfTables->TblEntryOfDramTerm[i])->TBLPtr); - TableSize = (EntryOfTables->TblEntryOfDramTerm[i])->TableSize; - break; - } - } - } - i++; - } - - // Check whether no table entry is found. - if (EntryOfTables->TblEntryOfDramTerm[i] == NULL) { - IDS_HDT_CONSOLE (MEM_FLOW, "\nNo RTT table\n"); - return FALSE; - } - - CurDDRrate = (UINT32) (1 << (CurrentChannel->DCTPtr->Timings.Speed / 66)); - DDR3Voltage = (UINT8) (1 << CONVERT_VDDIO_TO_ENCODED (NBPtr->RefPtr->DDR3Voltage)); - RankTypeOfPopulatedDimm = MemPGetPsRankType (CurrentChannel); - - OrgTblPtr = TblPtr; - for (Chipsel = 0; Chipsel < MAX_CS_PER_CHANNEL; Chipsel++) { - TblPtr = OrgTblPtr; - if ((NBPtr->DCTPtr->Timings.CsEnabled & (UINT16) (1 << Chipsel)) != 0) { - if ((CurrentChannel->DimmQrPresent & (UINT8) (1 << (Chipsel >> 1))) != 0) { - TgtDimmType = DIMM_QR; - TgtRank = (UINT8) ((Chipsel < 4) ? 1 << (Chipsel & 1) : 4 << (Chipsel & 1)); - } else if ((CurrentChannel->DimmDrPresent & (UINT8) (1 << (Chipsel >> 1))) != 0) { - TgtDimmType = DIMM_DR; - TgtRank = (UINT8) 1 << (Chipsel & 1); - } else { - TgtDimmType = DIMM_SR; - TgtRank = (UINT8) 1 << (Chipsel & 1); - } - - if (DimmType == LRDIMM_TYPE) { - TgtDimmType = _DONT_CARE; - TgtRank = _DONT_CARE; - } - - for (i = 0; i < TableSize; i++) { - MemPConstructRankTypeMap ((UINT16) TblPtr->Dimm0, (UINT16) TblPtr->Dimm1, (UINT16) TblPtr->Dimm2, &RankTypeInTable); - if (TblPtr->DimmPerCh == MaxDimmPerCh) { - if ((TblPtr->DDRrate & CurDDRrate) != 0) { - if ((TblPtr->VDDIO & DDR3Voltage) != 0) { - if ((RankTypeInTable & RankTypeOfPopulatedDimm) == RankTypeOfPopulatedDimm) { - if (((TblPtr->Dimm & TgtDimmType) != 0) || (TgtDimmType == _DONT_CARE)) { - if (((TblPtr->Rank & TgtRank) != 0) || (TgtRank == _DONT_CARE)) { - NBPtr->PsPtr->RttNom[Chipsel] = (UINT8) TblPtr->RttNom; - NBPtr->PsPtr->RttWr[Chipsel] = (UINT8) TblPtr->RttWr; - break; - } - } - } - } - } - } - TblPtr++; - } - if ((i == TableSize) && (NBPtr->SharedPtr->VoltageMap == VDDIO_DETERMINED)) { - IDS_HDT_CONSOLE (MEM_FLOW, "\nNo Rtt entries\n"); - return FALSE; - } - } - } - return TRUE; -} diff --git a/src/vendorcode/amd/agesa/f12/Proc/Mem/Ps/mpsao.c b/src/vendorcode/amd/agesa/f12/Proc/Mem/Ps/mpsao.c deleted file mode 100644 index 95030610f7..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/Mem/Ps/mpsao.c +++ /dev/null @@ -1,206 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * mpsao.c - * - * A sub-engine which extracts Slow access mode, Address timing and Output driver compensation value. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: (Mem/Ps) - * @e \$Revision: 45233 $ @e \$Date: 2011-01-14 11:58:29 +0800 (Fri, 14 Jan 2011) $ - * - **/ -/***************************************************************************** -* -* Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* *************************************************************************** -* -*/ -/* - *---------------------------------------------------------------------------- - * MODULES USED - * - *---------------------------------------------------------------------------- - */ - - - -#include "AGESA.h" -#include "AdvancedApi.h" -#include "amdlib.h" -#include "Ids.h" -#include "cpuFamRegisters.h" -#include "cpuRegisters.h" -#include "OptionMemory.h" -#include "PlatformMemoryConfiguration.h" -#include "mu.h" -#include "ma.h" -#include "mp.h" -#include "Filecode.h" -CODE_GROUP (G2_PEI) -RDATA_GROUP (G2_PEI) - -#define FILECODE PROC_MEM_PS_MPSAO_FILECODE - - -/*---------------------------------------------------------------------------- - * DEFINITIONS AND MACROS - * - *---------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------- - * TYPEDEFS AND STRUCTURES - * - *---------------------------------------------------------------------------- - */ -/*---------------------------------------------------------------------------- - * PROTOTYPES OF LOCAL FUNCTIONS - * - *---------------------------------------------------------------------------- - */ -BOOLEAN -MemPGetSAO ( - IN OUT MEM_NB_BLOCK *NBPtr, - IN MEM_PSC_TABLE_BLOCK *EntryOfTables - ); - -/*---------------------------------------------------------------------------- - * EXPORTED FUNCTIONS - * - *---------------------------------------------------------------------------- - */ -/* -----------------------------------------------------------------------------*/ -/** - * - * A sub-function which extracts Slow mode, Address timing and Output driver compensation value - * from a input table and store those value to a specific address. - * - * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK - * @param[in] *EntryOfTables - Pointer to MEM_PSC_TABLE_BLOCK - * - * @return TRUE - Table values can be extracted per dimm population and ranks type. - * @return FALSE - Table values cannot be extracted per dimm population and ranks type. - * - */ -BOOLEAN -MemPGetSAO ( - IN OUT MEM_NB_BLOCK *NBPtr, - IN MEM_PSC_TABLE_BLOCK *EntryOfTables - ) -{ - - UINT8 i; - UINT8 MaxDimmPerCh; - UINT8 NOD; - UINT8 TableSize; - UINT32 CurDDRrate; - UINT8 DDR3Voltage; - UINT16 RankTypeOfPopulatedDimm; - UINT16 RankTypeInTable; - DIMM_TYPE DimmType; - CPU_LOGICAL_ID LogicalCpuid; - UINT8 PackageType; - PSCFG_SAO_ENTRY *TblPtr; - CH_DEF_STRUCT *CurrentChannel; - - CurrentChannel = NBPtr->ChannelPtr; - - TblPtr = NULL; - TableSize = 0; - PackageType = 0; - LogicalCpuid.Family = (UINT64) AMD_FAMILY_UNKNOWN; - MaxDimmPerCh = GetMaxDimmsPerChannel (NBPtr->RefPtr->PlatformMemoryConfiguration, NBPtr->MCTPtr->SocketId, CurrentChannel->ChannelID); - NOD = (UINT8) 1 << (MaxDimmPerCh - 1); - - if (CurrentChannel->RegDimmPresent != 0) { - DimmType = RDIMM_TYPE; - } else if (CurrentChannel->SODimmPresent != 0) { - DimmType = SODIMM_TYPE; - if (FindPSOverrideEntry (NBPtr->RefPtr->PlatformMemoryConfiguration, PSO_SOLDERED_DOWN_SODIMM_TYPE, NBPtr->MCTPtr->SocketId, NBPtr->ChannelPtr->ChannelID) != NULL) { - DimmType = SODWN_SODIMM_TYPE; - } - } else if (CurrentChannel->LrDimmPresent != 0) { - DimmType = LRDIMM_TYPE; - } else { - DimmType = UDIMM_TYPE; - } - - i = 0; - // Obtain table pointer, table size, Logical Cpuid and PSC type according to Dimm, NB and package type. - while (EntryOfTables->TblEntryOfSAO[i] != NULL) { - if (((EntryOfTables->TblEntryOfSAO[i])->Header.DimmType & DimmType) != 0) { - if (((EntryOfTables->TblEntryOfSAO[i])->Header.NumOfDimm & NOD) != 0) { - // - // Determine if this is the expected NB Type - // - LogicalCpuid = (EntryOfTables->TblEntryOfSAO[i])->Header.LogicalCpuid; - PackageType = (EntryOfTables->TblEntryOfSAO[i])->Header.PackageType; - if (MemPIsIdSupported (NBPtr, LogicalCpuid, PackageType)) { - TblPtr = (PSCFG_SAO_ENTRY *) ((EntryOfTables->TblEntryOfSAO[i])->TBLPtr); - TableSize = (EntryOfTables->TblEntryOfSAO[i])->TableSize; - break; - } - } - } - i++; - } - - // Check whether no table entry is found. - if (EntryOfTables->TblEntryOfSAO[i] == NULL) { - IDS_HDT_CONSOLE (MEM_FLOW, "\nNo SlowMode table\n"); - return FALSE; - } - - CurDDRrate = (UINT32) (1 << (CurrentChannel->DCTPtr->Timings.Speed / 66)); - DDR3Voltage = (UINT8) (1 << CONVERT_VDDIO_TO_ENCODED (NBPtr->RefPtr->DDR3Voltage)); - RankTypeOfPopulatedDimm = MemPGetPsRankType (CurrentChannel); - - for (i = 0; i < TableSize; i++) { - MemPConstructRankTypeMap ((UINT16) TblPtr->Dimm0, (UINT16) TblPtr->Dimm1, (UINT16) TblPtr->Dimm2, &RankTypeInTable); - if (TblPtr->DimmPerCh == MaxDimmPerCh) { - if ((TblPtr->DDRrate & CurDDRrate) != 0) { - if ((TblPtr->VDDIO & DDR3Voltage) != 0) { - if ((RankTypeInTable & RankTypeOfPopulatedDimm) == RankTypeOfPopulatedDimm) { - CurrentChannel->DctAddrTmg = TblPtr->AddTmgCtl; - CurrentChannel->DctOdcCtl = TblPtr->ODC; - CurrentChannel->SlowMode = (TblPtr->SlowMode == 1) ? TRUE : FALSE; - return TRUE; - } - } - } - } - TblPtr++; - } - IDS_HDT_CONSOLE (MEM_FLOW, "\nNo SlowMode entries\n"); - if (NBPtr->SharedPtr->VoltageMap != VDDIO_DETERMINED) { - return TRUE; - } - - return FALSE; -} \ No newline at end of file diff --git a/src/vendorcode/amd/agesa/f12/Proc/Mem/Tech/DDR3/Makefile.inc b/src/vendorcode/amd/agesa/f12/Proc/Mem/Tech/DDR3/Makefile.inc deleted file mode 100644 index e2af37d663..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/Mem/Tech/DDR3/Makefile.inc +++ /dev/null @@ -1,8 +0,0 @@ -libagesa-y += mt3.c -libagesa-y += mtlrdimm3.c -libagesa-y += mtot3.c -libagesa-y += mtrci3.c -libagesa-y += mtsdi3.c -libagesa-y += mtspd3.c -libagesa-y += mttecc3.c -libagesa-y += mttwl3.c diff --git a/src/vendorcode/amd/agesa/f12/Proc/Mem/Tech/DDR3/mt3.c b/src/vendorcode/amd/agesa/f12/Proc/Mem/Tech/DDR3/mt3.c deleted file mode 100644 index a18befdaf5..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/Mem/Tech/DDR3/mt3.c +++ /dev/null @@ -1,235 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * mt3.c - * - * Common Technology functions for DDR3 - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: (Mem/Tech/DDR3) - * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $ - * - **/ -/***************************************************************************** -* -* Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* *************************************************************************** -* -*/ - -/* - *---------------------------------------------------------------------------- - * MODULES USED - * - *---------------------------------------------------------------------------- - */ - - - -#include "AGESA.h" -#include "Ids.h" -#include "mm.h" -#include "mn.h" -#include "mu.h" -#include "mt.h" -#include "mt3.h" -#include "mtspd3.h" -#include "mtot3.h" -#include "OptionMemory.h" -#include "PlatformMemoryConfiguration.h" -#include "Filecode.h" -CODE_GROUP (G1_PEICC) -RDATA_GROUP (G1_PEICC) - -/* features */ -#define FILECODE PROC_MEM_TECH_DDR3_MT3_FILECODE -/*---------------------------------------------------------------------------- - * DEFINITIONS AND MACROS - * - *---------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------- - * TYPEDEFS AND STRUCTURES - * - *---------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------- - * PROTOTYPES OF LOCAL FUNCTIONS - * - *---------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------- - * EXPORTED FUNCTIONS - * - *---------------------------------------------------------------------------- - */ -/* -----------------------------------------------------------------------------*/ -/** - * - * This function Constructs the technology block - * - * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK - * @param[in,out] *TechPtr - Pointer to the MEM_TECH_BLOCK - * - */ - -BOOLEAN -MemConstructTechBlock3 ( - IN OUT MEM_TECH_BLOCK *TechPtr, - IN OUT MEM_NB_BLOCK *NBPtr - ) -{ - TECHNOLOGY_TYPE *TechTypePtr; - UINT8 Dct; - UINT8 Channel; - UINT8 i; - DIE_STRUCT *MCTPtr; - DCT_STRUCT *DCTPtr; - CH_DEF_STRUCT *ChannelPtr; - UINT8 DimmSlots; - - - TechTypePtr = (TECHNOLOGY_TYPE *) FindPSOverrideEntry (NBPtr->RefPtr->PlatformMemoryConfiguration, PSO_MEM_TECH, NBPtr->MCTPtr->SocketId, 0); - if (TechTypePtr != NULL) { - // Ensure the platform override value is valid - ASSERT ((*TechTypePtr == DDR3_TECHNOLOGY) || (*TechTypePtr == DDR2_TECHNOLOGY)); - if (*TechTypePtr != DDR3_TECHNOLOGY) { - return FALSE; - } - } - - TechPtr->NBPtr = NBPtr; - TechPtr->RefPtr = NBPtr->RefPtr; - MCTPtr = NBPtr->MCTPtr; - - TechPtr->SendAllMRCmds = MemTSendAllMRCmds3; - TechPtr->FreqChgCtrlWrd = FreqChgCtrlWrd3; - TechPtr->SetDramMode = MemTSetDramMode3; - TechPtr->DimmPresence = MemTDIMMPresence3; - TechPtr->SpdCalcWidth = MemTSPDCalcWidth3; - TechPtr->SpdGetTargetSpeed = MemTSPDGetTargetSpeed3; - TechPtr->AutoCycTiming = MemTAutoCycTiming3; - TechPtr->SpdSetBanks = MemTSPDSetBanks3; - TechPtr->SetDqsEccTmgs = MemTSetDQSEccTmgs; - TechPtr->GetCSIntLvAddr = MemTGetCSIntLvAddr3; - TechPtr->AdjustTwrwr = MemTAdjustTwrwr3; - TechPtr->AdjustTwrrd = MemTAdjustTwrrd3; - TechPtr->GetDimmSpdBuffer = MemTGetDimmSpdBuffer3; - TechPtr->GetLD = MemTGetLD3; - TechPtr->MaxFilterDly = 0; - - // - // Map the Logical Dimms on this channel to the SPD that should be used for that logical DIMM. - // The pointers to the DIMM SPD information is as follows (2 Dimm/Ch and 3 Dimm/Ch examples). - // - // DIMM Spd Buffer Current Channel DimmSpdPtr[MAX_DIMMS_PER_CHANNEL] array - // (Number of dimms varies by platform) (Array size is determined in AGESA.H) Dimm operations loop - // on this array only) - // 2 DIMMS PER CHANNEL - // - // Socket N Channel N Dimm 0 SR/DR DIMM <--------------DimmSpdPtr[0] - // Dimm 1 SR/DR DIMM <--------------DimmSpdPtr[1] - // DimmSpdPtr[2]------->NULL - // DimmSpdPtr[3]------->NULL - // - // Socket N Channel N Dimm 0 SR/DR DIMM <--------------DimmSpdPtr[0] - // Dimm 1 QR DIMM <---------+----DimmSpdPtr[1] - // | DimmSpdPtr[2]------->NULL - // +----DimmSpdPtr[3] - // - // Socket N Channel N Dimm 0 QR DIMM <-----+--------DimmSpdPtr[0] - // Dimm 1 QR DIMM <-----|---+----DimmSpdPtr[1] - // +-- | ---DimmSpdPtr[2] - // +----DimmSpdPtr[3] - // - // 3 DIMMS PER CHANNEL - // - // Socket N Channel N Dimm 0 SR/DR DIMM <--------------DimmSpdPtr[0] - // Dimm 1 SR/DR DIMM <--------------DimmSpdPtr[1] - // Dimm 3 SR/DR DIMM <--------------DimmSpdPtr[2] - // DimmSpdPtr[3]------->NULL - // - // Socket N Channel N Dimm 0 SR/DR DIMM <--------------DimmSpdPtr[0] - // Dimm 1 QR DIMM <---------+----DimmSpdPtr[1] - // Dimm 3 SR/DR DIMM <-------- | ---DimmSpdPtr[2] - // +----DimmSpdPtr[3] - // - // - // FOR LRDIMMS - // - // This code will assign SPD pointers on the basis of Physical ranks, even though - // an LRDIMM may only use one or two logical ranks, that determination will have to - // be made from downstream code. An LRDIMM with greater than 2 Physical ranks will have - // its DimmSpdPtr[] mapped as if it were a QR in the above diagrams. - - for (Dct = 0; Dct < NBPtr->DctCount; Dct++) { - NBPtr->SwitchDCT (NBPtr, Dct); - DCTPtr = NBPtr->DCTPtr; - for (Channel = 0; Channel < NBPtr->ChannelCount; Channel++) { - NBPtr->SwitchChannel (NBPtr, Channel); - ChannelPtr = NBPtr->ChannelPtr; - ChannelPtr->TechType = DDR3_TECHNOLOGY; - ChannelPtr->MCTPtr = MCTPtr; - ChannelPtr->DCTPtr = DCTPtr; - - DimmSlots = GetMaxDimmsPerChannel (NBPtr->RefPtr->PlatformMemoryConfiguration, - MCTPtr->SocketId, - NBPtr->GetSocketRelativeChannel (NBPtr, Dct, Channel) - ); - // - // Initialize the SPD pointers for each Dimm - // - for (i = 0 ; i < (sizeof (ChannelPtr->DimmSpdPtr) / sizeof (ChannelPtr->DimmSpdPtr[0])) ; i++) { - ChannelPtr->DimmSpdPtr[i] = NULL; - } - for (i = 0 ; i < DimmSlots; i++) { - ChannelPtr->DimmSpdPtr[i] = &(ChannelPtr->SpdPtr[i]); - if ( (i + 2) < (sizeof (ChannelPtr->DimmSpdPtr) / sizeof (ChannelPtr->DimmSpdPtr[0]))) { - if (ChannelPtr->DimmSpdPtr[i]->DimmPresent) { - if ((((ChannelPtr->DimmSpdPtr[i]->Data[SPD_RANKS] >> 3) & 0x07) + 1) > 2) { - ChannelPtr->DimmSpdPtr[i + 2] = &(ChannelPtr->SpdPtr[i]); - } - } - } - } - } - } - // Initialize Common technology functions - MemTCommonTechInit (TechPtr); - - return TRUE; -} - -/*---------------------------------------------------------------------------- - * LOCAL FUNCTIONS - * - *---------------------------------------------------------------------------- - */ diff --git a/src/vendorcode/amd/agesa/f12/Proc/Mem/Tech/DDR3/mt3.h b/src/vendorcode/amd/agesa/f12/Proc/Mem/Tech/DDR3/mt3.h deleted file mode 100644 index 4eed7eb666..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/Mem/Tech/DDR3/mt3.h +++ /dev/null @@ -1,134 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * mt3.h - * - * Common Technology - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: (Mem/Tech/DDR3) - * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $ - * - **/ -/***************************************************************************** - * - * Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * *************************************************************************** - * - */ - -#ifndef _MT3_H_ -#define _MT3_H_ - -/*---------------------------------------------------------------------------- - * Mixed (DEFINITIONS AND MACROS / TYPEDEFS, STRUCTURES, ENUMS) - * - *---------------------------------------------------------------------------- - */ - -/*----------------------------------------------------------------------------- - * DEFINITIONS AND MACROS - * - *----------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------- - * TYPEDEFS, STRUCTURES, ENUMS - * - *---------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------- - * FUNCTIONS PROTOTYPE - * - *---------------------------------------------------------------------------- - */ - -BOOLEAN -MemConstructTechBlock3 ( - IN OUT MEM_TECH_BLOCK *TechPtr, - IN OUT MEM_NB_BLOCK *NBPtr - ); -BOOLEAN -MemTSetDramMode3 ( - IN OUT MEM_TECH_BLOCK *TechPtr - ); - -BOOLEAN -MemTDIMMPresence3 ( - IN OUT MEM_TECH_BLOCK *TechPtr - ); - -BOOLEAN -MemTSPDCalcWidth3 ( - IN OUT MEM_TECH_BLOCK *TechPtr - ); - -BOOLEAN -MemTSPDGetTargetSpeed3 ( - IN OUT MEM_TECH_BLOCK *TechPtr - ); - -BOOLEAN -MemTAutoCycTiming3 ( - IN OUT MEM_TECH_BLOCK *TechPtr - ); - -BOOLEAN -MemTSPDSetBanks3 ( - IN OUT MEM_TECH_BLOCK *TechPtr - ); - -VOID -MemTGetCSIntLvAddr3 ( - IN UINT8 BankEnc, - OUT UINT8 *LowBit, - OUT UINT8 *HiBit - ); - -VOID -MemTSendAllMRCmds3 ( - IN OUT MEM_TECH_BLOCK *TechPtr, - IN UINT8 ChipSel - ); - -VOID -FreqChgCtrlWrd3 ( - IN OUT MEM_TECH_BLOCK *TechPtr - ); - - -BOOLEAN -MemTGetDimmSpdBuffer3 ( - IN OUT MEM_TECH_BLOCK *TechPtr, - IN OUT UINT8 **SpdBuffer, - IN UINT8 Dimm - ); -#endif /* _MT3_H_ */ - - diff --git a/src/vendorcode/amd/agesa/f12/Proc/Mem/Tech/DDR3/mtlrdimm3.c b/src/vendorcode/amd/agesa/f12/Proc/Mem/Tech/DDR3/mtlrdimm3.c deleted file mode 100644 index e7a76dcf28..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/Mem/Tech/DDR3/mtlrdimm3.c +++ /dev/null @@ -1,1107 +0,0 @@ -/** - * @file - * - * mtlrdimm3.c - * - * Technology initialization and control workd support for DDR3 LRDIMMS - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: (Mem/Tech/DDR3) - * @e \$Revision: 23714 $ @e \$Date: 2009-12-09 17:28:37 -0600 (Wed, 09 Dec 2009) $ - * - **/ -/***************************************************************************** -* -* Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* *************************************************************************** -* -*/ - -/* - *---------------------------------------------------------------------------- - * MODULES USED - * - *---------------------------------------------------------------------------- - */ - - - -#include "AGESA.h" -#include "amdlib.h" -#include "Ids.h" -#include "mm.h" -#include "mn.h" -#include "mu.h" -#include "mt.h" -#include "mt3.h" -#include "mtspd3.h" -#include "mtrci3.h" -#include "mtsdi3.h" -#include "mtlrdimm3.h" -#include "merrhdl.h" -#include "Filecode.h" -CODE_GROUP (G1_PEICC) -RDATA_GROUP (G1_PEICC) -#define FILECODE PROC_MEM_TECH_DDR3_MTLRDIMM3_FILECODE -/*---------------------------------------------------------------------------- - * DEFINITIONS AND MACROS - * - *---------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------- - * TYPEDEFS AND STRUCTURES - * - *---------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------- - * PROTOTYPES OF LOCAL FUNCTIONS - * - *---------------------------------------------------------------------------- - */ - -VOID -STATIC -MemTSendMBCtlWord3 ( - IN OUT MEM_TECH_BLOCK *TechPtr, - IN UINT8 Fn, - IN UINT8 Rcw, - IN UINT8 Value - ); - -UINT8 -STATIC -MemTGetSpecialMBCtlWord3 ( - IN OUT MEM_TECH_BLOCK *TechPtr, - IN UINT8 Dimm, - IN UINT8 Fn, - IN UINT8 Rc - ); - -BOOLEAN -STATIC -MemTLrDimmControlRegInit3 ( - IN OUT MEM_TECH_BLOCK *TechPtr, - IN OUT VOID *OptParam - ); - -BOOLEAN -STATIC -MemTLrDimmFreqChgCtrlWrd3 ( - IN OUT MEM_TECH_BLOCK *TechPtr, - IN OUT VOID *OptParam - ); - -BOOLEAN -STATIC -MemTWLPrepareLrdimm3 ( - IN OUT MEM_TECH_BLOCK *TechPtr, - IN OUT VOID *Wl - ); - -BOOLEAN -STATIC -MemTSendAllMRCmdsLR3 ( - IN OUT MEM_TECH_BLOCK *TechPtr, - IN OUT VOID *CsPtr - ); - -VOID -STATIC -MemTEMRS1Lr3 ( - IN OUT MEM_TECH_BLOCK *TechPtr, - IN UINT8 ChipSel, - IN UINT8 PhyRank - ); - -VOID -STATIC -MemTEMRS2Lr3 ( - IN OUT MEM_TECH_BLOCK *TechPtr, - IN UINT8 ChipSel - ); - - -BOOLEAN -STATIC -MemTLrdimmRankMultiplication ( - IN OUT MEM_TECH_BLOCK *TechPtr, - IN OUT VOID *DimmID - ); - -BOOLEAN -STATIC -MemTLrdimmBuf2DramTrain3 ( - IN OUT MEM_TECH_BLOCK *TechPtr, - IN OUT VOID *OptParam - ); - -BOOLEAN -STATIC -MemTLrdimmSyncTrainedDlys ( - IN OUT MEM_TECH_BLOCK *TechPtr, - IN OUT VOID *OptParam - ); - -/*---------------------------------------------------------------------------- - * EXPORTED FUNCTIONS - * - *---------------------------------------------------------------------------- - */ - -/* -----------------------------------------------------------------------------*/ -/** - * - * This function initializes LRDIMM functions. - * - * @param[in,out] *TechPtr - Pointer to the MEM_TECH_BLOCK - * - */ - -BOOLEAN -MemTLrdimmConstructor3 ( - IN OUT MEM_TECH_BLOCK *TechPtr - ) -{ - TechPtr->TechnologySpecificHook[LrdimmSendAllMRCmds] = MemTSendAllMRCmdsLR3; - TechPtr->TechnologySpecificHook[LrdimmControlRegInit] = MemTLrDimmControlRegInit3; - TechPtr->TechnologySpecificHook[LrdimmFreqChgCtrlWrd] = MemTLrDimmFreqChgCtrlWrd3; - TechPtr->TechnologySpecificHook[WlTrainingPrepareLrdimm] = MemTWLPrepareLrdimm3; - TechPtr->TechnologySpecificHook[LrdimmRankMultiplication] = MemTLrdimmRankMultiplication; - TechPtr->TechnologySpecificHook[LrdimmBuf2DramTrain] = MemTLrdimmBuf2DramTrain3; - TechPtr->TechnologySpecificHook[LrdimmSyncTrainedDlys] = MemTLrdimmSyncTrainedDlys; - return TRUE; -} - -/*---------------------------------------------------------------------------- - * LOCAL FUNCTIONS - * - *---------------------------------------------------------------------------- - */ - -/* -----------------------------------------------------------------------------*/ -/** - * - * This function sends a Control word command to an LRDIMM Memory Buffer - * - * @param[in,out] *TechPtr - Pointer to the MEM_TECH_BLOCK - * @param[in] Fn - control word function - * @param[in] Rcw - control word number - * @param[in] Value - value to send - * - */ - -VOID -STATIC -MemTSendMBCtlWord3 ( - IN OUT MEM_TECH_BLOCK *TechPtr, - IN UINT8 Fn, - IN UINT8 Rcw, - IN UINT8 Value - ) -{ - MEM_NB_BLOCK *NBPtr; - - NBPtr = TechPtr->NBPtr; - - ASSERT (Rcw != RCW_FN_SELECT); // RC7 can only be used for function select - IDS_HDT_CONSOLE (MEM_FLOW, "\t\tF%dRC%d = %x\n", Fn, Rcw, Value); - // - // Select the MB Function by sending the Fn number - // to the Function Select Control Word - // - MemUWait10ns (800, NBPtr->MemPtr); - MemTSendCtlWord3 (TechPtr, RCW_FN_SELECT, Fn); - // - // Send the value to the control word - // - MemUWait10ns (800, NBPtr->MemPtr); - MemTSendCtlWord3 (TechPtr, Rcw, Value); - - -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * This function gets the value of special RCW - * - * @param[in,out] *TechPtr - Pointer to the MEM_TECH_BLOCK - * @param[in] Dimm - Physical LR DIMM number - * @param[in] Fn - control word function - * @param[in] Rc - control word number - * - * @return Special RCW value - * - */ - -UINT8 -STATIC -MemTGetSpecialMBCtlWord3 ( - IN OUT MEM_TECH_BLOCK *TechPtr, - IN UINT8 Dimm, - IN UINT8 Fn, - IN UINT8 Rc - ) -{ - CONST UINT8 F0RC13PhyRankTab[] = {3, 2, 0, 1, 0}; - UINT8 PhyRanks; - UINT8 LogRanks; - UINT8 DramCap; - UINT8 Value8; - UINT8 *SpdBufferPtr; - MEM_NB_BLOCK *NBPtr; - - NBPtr = TechPtr->NBPtr; - - MemTGetDimmSpdBuffer3 (TechPtr, &SpdBufferPtr, Dimm); - - Value8 = 0; - switch (Fn) { - case 0: - switch (Rc) { - case 8: - // F0RC8 - Value8 = NBPtr->PsPtr->F0RC8; - break; - case 10: - // F0RC10 - // 2:0 OperatingSpeed: operating speed. BIOS: Table 88. - if (NBPtr->DCTPtr->Timings.Speed == DDR667_FREQUENCY) { - Value8 = 0; - } else { - Value8 = (UINT8) (NBPtr->DCTPtr->Timings.Speed / 133) - 3; - } - break; - case 11: - // F0RC11 - // 3:2 ParityCalculation: partiy calculation. BIOS: Table. - // 1:0 OperatingVoltage: operating voltage. BIOS: IF(VDDIO == 1.5) THEN 00b ELSEIF (VDDIO == - // 1.35) THEN 01b ELSE 10b ENDIF. - DramCap = SpdBufferPtr[SPD_DENSITY] & 0xF; - if ((NBPtr->ChannelPtr->LrDimmRankMult[Dimm] + DramCap * 2) > 8) { - Value8 = 8; - } else { - Value8 = 4; - } - Value8 |= CONVERT_VDDIO_TO_ENCODED (NBPtr->RefPtr->DDR3Voltage); - break; - case 13: - // F0RC13 - // 3:2 NumLogicalRanks: partiy calculation. BIOS: Table 90. - // 1:0 NumPhysicalRanks: operating voltage. BIOS: Table 89. - LogRanks = NBPtr->ChannelPtr->LrDimmLogicalRanks[Dimm] >> 1; - PhyRanks = F0RC13PhyRankTab[(SpdBufferPtr[SPD_RANKS] >> 3) & 7]; - Value8 = (LogRanks << 2) | PhyRanks; - break; - case 14: - // F0RC14 - // 3 DramBusWidth: DRAM bus width. BIOS: IF (DeviceWidth==0) THEN 0 ELSE 1 ENDIF. - // 2 MRSCommandControl: MRS command control. BIOS: IF (F0RC15[RankMultiplicationControl] - // > 0) THEN 1 ELSE 0 ENDIF. - // 1 RefreshPrechargeCommandControl: refresh and precharge command control. BIOS: IF - // (F0RC15[RankMultiplicationControl] > 0) THEN D18F2xA8_dct[1:0][LrDimmEnhRefEn] ELSE 0 ENDIF. - // 0 AddressMirror: address mirror. BIOS: RankMap. See D18F2x[5C:40]_dct[1:0][OnDimmMirror]. - if ((SpdBufferPtr[SPD_DEV_WIDTH] & 7) != 0) { - Value8 |= 8; - } - if (NBPtr->ChannelPtr->LrDimmRankMult[Dimm] > 1) { - Value8 |= 4; - if (NBPtr->GetBitField (NBPtr, BFLrDimmEnhRefEn) == 1) { - Value8 |= 2; - } - } - if ((SpdBufferPtr[SPD_ADDRMAP] & 1) != 0) { - Value8 |= 1; - } - break; - case 15: - // F0RC15 - // 3:0 RankMultiplicationControl: rank multiplication control. BIOS: Table 91. - DramCap = SpdBufferPtr[SPD_DENSITY] & 0xF; - ASSERT ((DramCap >= 2) && (DramCap <= 4)); // BKDG only lists 1Gb, 2Gb, and 4Gb - switch (NBPtr->ChannelPtr->LrDimmRankMult[Dimm]) { - case 1: - Value8 = 0; - break; - case 2: - Value8 = DramCap - 1; - break; - case 4: - Value8 = DramCap + 3; - break; - default: - ASSERT (FALSE); - } - break; - default: - ASSERT (FALSE); - } - break; - case 1: - switch (Rc) { - case 0: - // F1RC0 - Value8 = NBPtr->PsPtr->F1RC0; - Value8 |= (UINT8) NBPtr->GetBitField (NBPtr, BFCSTimingMux67) << 3; - break; - case 1: - // F1RC1 - Value8 = NBPtr->PsPtr->F1RC1; - break; - case 2: - // F1RC2 - Value8 = NBPtr->PsPtr->F1RC2; - break; - case 9: - // F1RC9 - if (NBPtr->GetBitField (NBPtr, BFLrDimmEnhRefEn) == 0) { - Value8 = 1; - } - break; - default: - ASSERT (FALSE); - } - break; - case 3: - switch (Rc) { - case 0: - // F3RC0 - // 3 TDQSControl: TDQS control. BIOS: 0. - // 2:0 RttNom: RttNom. BIOS: Table 57, Table 60 - Value8 = NBPtr->PsPtr->RttNom[Dimm << 1]; - break; - case 1: - // F3RC1 - // 3 Vref: Vref. BIOS: 0. - // 2:0 RttWr: RttWr. BIOS: Table 57, Table 60. - Value8 = NBPtr->PsPtr->RttWr[Dimm << 1]; - break; - case 6: - // F3RC6 - // IF (D18F2x90_dct[1:0][X4Dimm] == 0) THEN 1 ELSE 0 - if (NBPtr->GetBitField (NBPtr, BFX4Dimm) == 0) { - Value8 = 8; - } - break; - default: - ASSERT (FALSE); - } - break; - default: - ASSERT (FALSE); - } - - return Value8; -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * This function sends LRDIMM Control Words to all LRDIMMS - * - * @param[in,out] *TechPtr - Pointer to the MEM_TECH_BLOCK - * @param[in,out] OptParam - Optional parameter - * - * @return TRUE - */ - -BOOLEAN -STATIC -MemTLrDimmControlRegInit3 ( - IN OUT MEM_TECH_BLOCK *TechPtr, - IN OUT VOID *OptParam - ) -{ - CONST UINT8 RCWInitTable[] = { - // RCW, Mask, SPD - F0, RC0, 0x00, SPD_NONE, - F0, RC1, 0x00, SPD_NONE, - F0, RC2, 0x03, SPD_67, - F0, RC10, 0x00, SPECIAL_CASE, - F0, RC11, 0x00, SPECIAL_CASE, - - F1, RC8, 0x0F, SPD_69, - F1, RC11, 0xF0, SPD_69, - F1, RC12, 0x0F, SPD_70, - F1, RC13, 0xF0, SPD_70, - F1, RC14, 0x0F, SPD_71, - F1, RC15, 0xF0, SPD_71, - - WAIT_6US, 0, 0, 0, - - F0, RC3, 0xF0, SPD_67, - F0, RC4, 0x0F, SPD_68, - F0, RC5, 0xF0, SPD_68, - - F0, RC6, 0x00, SPD_NONE, - F0, RC8, 0x00, SPECIAL_CASE, - F0, RC9, 0x0C, SPD_NONE, - F0, RC13, 0x00, SPECIAL_CASE, - F0, RC14, 0x00, SPECIAL_CASE, - F0, RC15, 0x00, SPECIAL_CASE, - - F1, RC0, 0x00, SPECIAL_CASE, - F1, RC1, 0x00, SPECIAL_CASE, - F1, RC2, 0x00, SPECIAL_CASE, - F1, RC3, 0x00, SPD_NONE, - F1, RC9, 0x00, SPECIAL_CASE, - F1, RC10, 0x00, SPD_NONE, - - F2, RC0, 0x00, SPD_NONE, - F2, RC1, 0x00, SPD_NONE, - F2, RC2, 0x0F, SPD_NONE, - F2, RC3, 0x00, SPD_NONE, - - F3, RC0, 0x00, SPECIAL_CASE, - F3, RC1, 0x00, SPECIAL_CASE, - F3, RC2, 0x01, SPD_NONE, - F3, RC6, 0x00, SPECIAL_CASE - - // F3 RC[8,9] are programmed in MDQ RC loop - - // F[10:3] RC[11,10] are programmed in QxODT RC loop - - // F[15,14] RC[15:0] are programmed in personality RC loop - }; - - UINT8 Dimm; - UINT16 i; - UINT16 DimmMask; - UINT8 Fn; - UINT8 Rc; - UINT8 Mask; - UINT8 Spd; - UINT8 *SpdBufferPtr; - UINT8 FreqDiffOffset; - UINT8 Value8; - MEM_DATA_STRUCT *MemPtr; - MEM_NB_BLOCK *NBPtr; - - NBPtr = TechPtr->NBPtr; - MemPtr = NBPtr->MemPtr; - - if (NBPtr->MCTPtr->Status[SbLrdimms]) { - for (Dimm = 0; Dimm < MAX_DIMMS_PER_CHANNEL; Dimm++) { - DimmMask = (UINT16)1 << Dimm; - if ((NBPtr->ChannelPtr->LrDimmPresent & DimmMask) != 0) { - IDS_HDT_CONSOLE (MEM_FLOW, "\t\tSending LRDIMM Control Words: Dimm %02x\n", Dimm); - // - // Select the Target Chipselects - // - NBPtr->SetBitField (NBPtr, BFMrsChipSel, (Dimm << 1)); - NBPtr->SetBitField (NBPtr, BFCtrlWordCS, 3 << (Dimm << 1)); - - MemTGetDimmSpdBuffer3 (TechPtr, &SpdBufferPtr, Dimm); - for (i = 0; i < sizeof (RCWInitTable) ; i += 4) { - Fn = RCWInitTable[i]; - Rc = RCWInitTable[i + 1]; - Mask = RCWInitTable[i + 2]; - Spd = RCWInitTable[i + 3]; - - if (Fn == WAIT_6US) { - MemUWait10ns (600, MemPtr); // wait 6us for TSTAB - } else { - if (Spd == SPD_NONE) { - Value8 = Mask; - } else if (Spd == SPECIAL_CASE) { - Value8 = MemTGetSpecialMBCtlWord3 (TechPtr, Dimm, Fn, Rc); - } else { - Value8 = (Mask > 0x0F) ? ((SpdBufferPtr[Spd] & Mask) >> 4) : (SpdBufferPtr[Spd] & Mask); - } - MemTSendMBCtlWord3 (TechPtr, Fn, Rc, Value8); - } - } - - FreqDiffOffset = (UINT8) (SPD_FREQ_DIFF_OFFSET * (((NBPtr->DCTPtr->Timings.Speed / 133) - 3) / 2)); - // - // Send RCW to program MDQ termination and drive strength - // - for (Rc = 8; Rc <= 9; Rc++) { - Value8 = SpdBufferPtr[SPD_MDQ_800_1066 + FreqDiffOffset]; - Value8 = (Rc == 9) ? (Value8 >> 4) : Value8; - MemTSendMBCtlWord3 (TechPtr, 3, Rc, Value8 & 0x07); - } - - // - // Send RCW to program QxODT - // - for (Fn = 3; Fn <= 10; Fn ++) { - for (Rc = 10; Rc <= 11; Rc++) { - Value8 = SpdBufferPtr[SPD_QXODT_800_1066 + FreqDiffOffset + ((Fn - 3) >> 1)]; - Value8 = (Rc == 11) ? (Value8 >> 4) : (Value8 & 0x0F); - Value8 = ((Fn & 1) == 0) ? (Value8 >> 2) : (Value8 & 0x03); - MemTSendMBCtlWord3 (TechPtr, Fn, Rc, Value8); - } - } - - // - // Send Personality bytes from SPD - // - for (Fn = 14; Fn < 16; Fn ++) { - for (Rc = 0; Rc < 16 ; Rc++) { - Value8 = SpdBufferPtr[SPD_PERSONALITY_BYTE + ((Fn - 14) << 3) + (Rc >> 1)]; - if ((Fn == 14) && (Rc == 0)) { - Value8 |= 0x01; // Write global enable - } - if (Rc != 0x07) { - MemTSendMBCtlWord3 (TechPtr, Fn, Rc, ((Rc & 1) != 0) ? (Value8 >> 4) : (Value8 & 0x0F)); - } - } - } - } - } - } - return TRUE; -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * This function sends LRDIMM Control Words to all LRDIMMS - * - * @param[in,out] *TechPtr - Pointer to the MEM_TECH_BLOCK - * @param[in,out] OptParam - Optional parameter - * - * @return FALSE - The current channel does not have LRDIMM populated - * TRUE - The current channel has LRDIMM populated - */ - -BOOLEAN -STATIC -MemTLrDimmFreqChgCtrlWrd3 ( - IN OUT MEM_TECH_BLOCK *TechPtr, - IN OUT VOID *OptParam - ) -{ - UINT8 Dct; - MEM_NB_BLOCK *NBPtr; - - NBPtr = TechPtr->NBPtr; - - if (NBPtr->MCTPtr->Status[SbLrdimms]) { - for (Dct = 0; Dct < NBPtr->DctCount; Dct++) { - MemNSwitchDCTNb (NBPtr, Dct); - if (NBPtr->DCTPtr->Timings.DctMemSize != 0) { - MemTLrDimmControlRegInit3 (TechPtr, NULL); - } - } - return TRUE; - } - return FALSE; -} - -/*----------------------------------------------------------------------------- - * - * - * This function prepares LRDIMMs for WL training. - * - * @param[in,out] *TechPtr - Pointer to the MEM_TECH_BLOCK - * @param[in,out] *Wl - Indicates if WL mode should be enabled - * - * @return TRUE - LRDIMMs present - * ---------------------------------------------------------------------------- - */ -BOOLEAN -STATIC -MemTWLPrepareLrdimm3 ( - IN OUT MEM_TECH_BLOCK *TechPtr, - IN OUT VOID *Wl - ) -{ - UINT8 Dimm; - UINT8 Value8; - UINT16 MrsAddress; - MEM_NB_BLOCK *NBPtr; - NBPtr = TechPtr->NBPtr; - MrsAddress = 0; - if (NBPtr->MCTPtr->Status[SbLrdimms]) { - for (Dimm = 0; Dimm < MAX_DIMMS_PER_CHANNEL; Dimm++) { - if (*(BOOLEAN *) Wl == TRUE) { - // Program WrLvOdt - NBPtr->SetBitField (NBPtr, BFWrLvOdt, NBPtr->ChannelPtr->PhyWLODT[Dimm]); - } - if ((NBPtr->ChannelPtr->LrDimmPresent & ((UINT8) 1 << Dimm)) != 0) { - if (Dimm == TechPtr->TargetDIMM) { - if (*(BOOLEAN *) Wl == TRUE) { - // - // Select the Target Chipselects - // - NBPtr->SetBitField (NBPtr, BFMrsChipSel, (Dimm << 1)); - NBPtr->SetBitField (NBPtr, BFCtrlWordCS, 3 << (Dimm << 1)); - - // Program F0RC12 to 1h - MemTSendMBCtlWord3 (TechPtr, F0, RC12, 0x01); - if (NBPtr->ChannelPtr->Dimms >= 2) { - // For two or more LRDIMMs per channel program the buffer RttNom to the - // corresponding specifed RttWr termination - Value8 = NBPtr->MemNGetDynDramTerm (NBPtr, Dimm << 2); - } else { - // Program RttNom as normal - Value8 = NBPtr->MemNGetDramTerm (NBPtr, Dimm << 2); - } - if ((Value8 & ((UINT8) 1 << 2)) != 0) { - MrsAddress |= ((UINT16) 1 << 9); - } - if ((Value8 & ((UINT8) 1 << 1)) != 0) { - MrsAddress |= ((UINT16) 1 << 6); - } - if ((Value8 & ((UINT8) 1 << 0)) != 0) { - MrsAddress |= ((UINT16) 1 << 2); - } - NBPtr->SetBitField (NBPtr, BFMrsAddress, MrsAddress); - } else { - // Program F0RC12 to 0h - MemTSendMBCtlWord3 (TechPtr, F0, RC12, 0x00); - } - } - } - } - return TRUE; - } else { - return FALSE; - } -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * This send all MR commands to all physical ranks of an LRDIMM - * - * @param[in,out] *TechPtr - Pointer to the MEM_TECH_BLOCK - * @param[in] *CsPtr - Target Chip Select - * - * @return FALSE - The current channel does not have LRDIMM populated - * TRUE - The current channel has LRDIMM populated - */ - -BOOLEAN -STATIC -MemTSendAllMRCmdsLR3 ( - IN OUT MEM_TECH_BLOCK *TechPtr, - IN OUT VOID *CsPtr - ) -{ - UINT8 *SpdBufferPtr; - BOOLEAN Skip; - UINT8 Rank; - UINT8 PhyRank; - UINT8 ChipSel; - MEM_NB_BLOCK *NBPtr; - - NBPtr = TechPtr->NBPtr; - ChipSel = *((UINT8 *) CsPtr); - - if (NBPtr->MCTPtr->Status[SbLrdimms]) { - // - // LRDIMM: MR0, MR2, and MR3 can be broadcasted. - // MR1[Rtt_Nom] needs to be programmed differently per physical ranks. - // - // CS 0 1 2 3 4 5 6 7 - // MR[0,2,3] x x ? - // MR1 x x x x x x x x - // - // ? If 3 DIMMs/ch, need to send to CS4 since it is on the 3rd physical DIMM. - // - Skip = TRUE; - switch (ChipSel) { - case 0: - case 2: - Skip = FALSE; - break; - case 4: - if (GetMaxDimmsPerChannel (NBPtr->RefPtr->PlatformMemoryConfiguration, - NBPtr->MCTPtr->SocketId, - NBPtr->ChannelPtr->ChannelID) == 3) { - Skip = FALSE; - } - break; - } - - // Select target chip select - NBPtr->SetBitField (NBPtr, BFMrsChipSel, ChipSel); - - if (!Skip) { - // 13.Send EMRS(2) - MemTEMRS2Lr3 (TechPtr, ChipSel); - NBPtr->SetBitField (NBPtr, BFMrsAddressHi, 1); // Set Address bit 13 to broadcast - NBPtr->SendMrsCmd (NBPtr); - - // 14.Send EMRS(3). Ordinarily at this time, MrsAddress[2:0]=000b - MemTEMRS33 (TechPtr); - NBPtr->SetBitField (NBPtr, BFMrsAddressHi, 1); // Set Address bit 13 to broadcast - NBPtr->SendMrsCmd (NBPtr); - } - - // 15.Send EMRS(1). Send to each physical rank. - MemTGetDimmSpdBuffer3 (TechPtr, &SpdBufferPtr, ChipSel >> 1); - for (Rank = 0; Rank < NBPtr->ChannelPtr->LrDimmRankMult[ChipSel >> 1]; Rank++) { - PhyRank = (((ChipSel >> 1) & 2) | (ChipSel & 1)) + (Rank * NBPtr->ChannelPtr->LrDimmLogicalRanks[ChipSel >> 1]); - MemTEMRS1Lr3 (TechPtr, ChipSel, PhyRank); - // Set Address bit 14, 15, 16, or 17 to select physical rank according to the device size - NBPtr->SetBitField (NBPtr, BFMrsAddressHi, Rank << (SpdBufferPtr[SPD_DENSITY] & 0xF)); - NBPtr->SendMrsCmd (NBPtr); - } - - if (!Skip) { - // 16.Send MRS with MrsAddress[8]=1(reset the DLL) - MemTMRS3 (TechPtr); - NBPtr->SetBitField (NBPtr, BFMrsAddressHi, 1); // Set Address bit 13 to broadcast - NBPtr->SendMrsCmd (NBPtr); - } - - // If LRDIMM, return TRUE to skip sending regular MR commands. - return TRUE; - } - // If not LRDIMM, send regular MR commands. - return FALSE; -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * This function calculates the EMRS1 value for an LRDIMM - * - * @param[in,out] *TechPtr - Pointer to the MEM_TECH_BLOCK - * @param[in] ChipSel - Chip select number - * @param[in] PhyRank - Physical rank number - */ - -VOID -STATIC -MemTEMRS1Lr3 ( - IN OUT MEM_TECH_BLOCK *TechPtr, - IN UINT8 ChipSel, - IN UINT8 PhyRank - ) -{ - UINT16 MrsAddress; - UINT8 Value8; - UINT8 *SpdBufferPtr; - UINT8 FreqDiffOffset; - MEM_NB_BLOCK *NBPtr; - - NBPtr = TechPtr->NBPtr; - - MemTGetDimmSpdBuffer3 (TechPtr, &SpdBufferPtr, ChipSel >> 1); - FreqDiffOffset = (UINT8) (SPD_FREQ_DIFF_OFFSET * (((NBPtr->DCTPtr->Timings.Speed / 133) - 3) / 2)); - - // BA2=0,BA1=0,BA0=1 - NBPtr->SetBitField (NBPtr, BFMrsBank, 1); - - MrsAddress = 0; - - // program MrsAddress[5,1]=output driver impedance control (DIC): 01b - MrsAddress |= ((UINT16) 1 << 1); - - // program MrsAddress[5,1]=output driver impedance control (DIC): - // DIC is read from SPD byte 77, 83, or 89 depending on DDR speed - Value8 = SpdBufferPtr[SPD_MR1_MR2_800_1066 + FreqDiffOffset] & 3; - if ((Value8 & ((UINT8) 1 << 1)) != 0) { - MrsAddress |= ((UINT16) 1 << 5); - } - if ((Value8 & ((UINT8) 1 << 0)) != 0) { - MrsAddress |= ((UINT16) 1 << 1); - } - - // program MrsAddress[9,6,2]=nominal termination resistance of ODT (RTT): - // RttNom is read from SPD byte 77, 83, or 89 depending on DDR speed - if (PhyRank <= 1) { - Value8 = (SpdBufferPtr[SPD_MR1_MR2_800_1066 + FreqDiffOffset] >> 2) & 7; - if ((Value8 & ((UINT8) 1 << 2)) != 0) { - MrsAddress |= ((UINT16) 1 << 9); - } - if ((Value8 & ((UINT8) 1 << 1)) != 0) { - MrsAddress |= ((UINT16) 1 << 6); - } - if ((Value8 & ((UINT8) 1 << 0)) != 0) { - MrsAddress |= ((UINT16) 1 << 2); - } - } - - NBPtr->SetBitField (NBPtr, BFMrsAddress, MrsAddress); -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * This function calculates the EMRS2 value for an LRDIMM - * - * @param[in,out] *TechPtr - Pointer to the MEM_TECH_BLOCK - * @param[in] ChipSel - Chip select number - */ - -VOID -STATIC -MemTEMRS2Lr3 ( - IN OUT MEM_TECH_BLOCK *TechPtr, - IN UINT8 ChipSel - ) -{ - UINT8 RttWr; - UINT8 *SpdBufferPtr; - UINT8 FreqDiffOffset; - MEM_NB_BLOCK *NBPtr; - - NBPtr = TechPtr->NBPtr; - - // Save default RttWr - RttWr = NBPtr->PsPtr->RttWr[ChipSel]; - - // Override RttWr with the value read from SPD byte 77, 83, or 89 depending on DDR speed - MemTGetDimmSpdBuffer3 (TechPtr, &SpdBufferPtr, ChipSel >> 1); - FreqDiffOffset = (UINT8) (SPD_FREQ_DIFF_OFFSET * (((NBPtr->DCTPtr->Timings.Speed / 133) - 3) / 2)); - NBPtr->PsPtr->RttWr[ChipSel] = SpdBufferPtr[SPD_MR1_MR2_800_1066 + FreqDiffOffset] >> 6; - - // Call EMRS2 calculation - MemTEMRS23 (TechPtr); - - // Restore RttWr - NBPtr->PsPtr->RttWr[ChipSel] = RttWr; -} - -/*----------------------------------------------------------------------------- - * - * - * This function to determine the Rank Multiplication to use for an LRDIMM - * - * @param[in,out] *TechPtr - Pointer to the MEM_TECH_BLOCK - * @param[in,out] *DimmID - Dimm ID - * - * @return TRUE - LRDIMM Support is installed and LRDIMMs are present - * ---------------------------------------------------------------------------- - */ -BOOLEAN -STATIC -MemTLrdimmRankMultiplication ( - IN OUT MEM_TECH_BLOCK *TechPtr, - IN OUT VOID *DimmID - ) -{ - BOOLEAN RetVal; - UINT8 *SpdBufferPtr; - UINT8 Dimm; - UINT8 NumDimmslots; - UINT8 DramCapacity; - UINT8 Ranks; - UINT8 Rows; - UINT8 RankMult; - MEM_NB_BLOCK *NBPtr; - CH_DEF_STRUCT *ChannelPtr; - - ASSERT (TechPtr != NULL); - ASSERT (DimmID != NULL); - - Dimm = *(UINT8*)DimmID; - ASSERT (Dimm < MAX_DIMMS_PER_CHANNEL); - - NBPtr = TechPtr->NBPtr; - ChannelPtr = NBPtr->ChannelPtr; - RetVal = FALSE; - RankMult = 0; - - if (!MemTGetDimmSpdBuffer3 (TechPtr, &SpdBufferPtr, Dimm)) { - ASSERT (FALSE); - } - - NumDimmslots = GetMaxDimmsPerChannel (NBPtr->RefPtr->PlatformMemoryConfiguration, - NBPtr->MCTPtr->SocketId, - ChannelPtr->ChannelID); - - if (NBPtr->MCTPtr->Status[SbLrdimms]) { - RetVal = TRUE; - // - // Determine LRDIMM Rank Multiplication - // - Ranks = ((SpdBufferPtr[SPD_RANKS] >> 3) & 0x07) + 1; - if (Ranks == 5) { - Ranks = 8; - } - DramCapacity = (SpdBufferPtr[SPD_DENSITY] & 0x0F); - Rows = 12 + ((SpdBufferPtr[SPD_ROW_SZ] >> 3) & 0x7); - - if (Ranks < 4) { - RankMult = 1; - } else if (Ranks == 4) { - RankMult = (NumDimmslots < 3) ? 1 : 2; - } else if (Ranks == 8) { - RankMult = ((NumDimmslots < 3) && (DramCapacity < 4)) ? 2 : 4; - } - // - // Save Rank Information - // - ChannelPtr->LrDimmRankMult[Dimm] = RankMult; - ChannelPtr->LrDimmLogicalRanks[Dimm] = Ranks / RankMult; - NBPtr->PsPtr->LrdimmRowAddrBits[Dimm] = Rows + (RankMult >> 1); - // - // Program RankDef - // - NBPtr->SetBitField (NBPtr, BFRankDef0 + Dimm, (RankMult == 4) ? 3 : RankMult); - // - // If LrdimmRowAddressBits > 16, then we must be useing some CS signals for rank - // multiplication. If this is the case, then we want to clear the CSPresent bits - // that correspond to those chipselects. - // If there are 3 DIMMs per channel, then it will always be CS67, if there are - // 2DPCH, then DIMM0 will use CS45, adn DIMM1 will use CS67. - // - if (NBPtr->PsPtr->LrdimmRowAddrBits[Dimm] > 16) { - NBPtr->DCTPtr->Timings.CsPresent &= ~(0x30 << ((NumDimmslots > 2) ? 1 : Dimm) ); - } - } - - return RetVal; - -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * This function performs buffer to DRAM training for LRDIMMs - * - * @param[in,out] *TechPtr - Pointer to the MEM_TECH_BLOCK - * @param[in,out] OptParam - Optional parameter - * - * @return TRUE - */ - -BOOLEAN -STATIC -MemTLrdimmBuf2DramTrain3 ( - IN OUT MEM_TECH_BLOCK *TechPtr, - IN OUT VOID *OptParam - ) -{ - UINT8 Dct; - UINT8 Dimm; - UINT8 ChipSel; - UINT16 DimmMask; - UINT8 i; - MEM_DATA_STRUCT *MemPtr; - MEM_NB_BLOCK *NBPtr; - - NBPtr = TechPtr->NBPtr; - MemPtr = NBPtr->MemPtr; - - if (NBPtr->MCTPtr->Status[SbLrdimms]) { - IDS_HDT_CONSOLE (MEM_FLOW, "\nStart Buffer to DRAM training\n"); - - for (Dct = 0; Dct < NBPtr->DctCount; Dct++) { - IDS_HDT_CONSOLE (MEM_STATUS, "\tDct %d\n", Dct); - NBPtr->SwitchDCT (NBPtr, Dct); - - // - // ODM needs to be set after Dram Init - // - if (NBPtr->StartupSpeed == NBPtr->DCTPtr->Timings.Speed) { - for (ChipSel = 1; ChipSel < MAX_CS_PER_CHANNEL; ChipSel += 2) { - if ((NBPtr->DCTPtr->Timings.CsPresent & ((UINT16)1 << ChipSel)) != 0) { - if ((NBPtr->DCTPtr->Timings.DimmMirrorPresent & (1 << (ChipSel >> 1))) != 0) { - NBPtr->SetBitField (NBPtr, BFCSBaseAddr0Reg + ChipSel, ((NBPtr->GetBitField (NBPtr, BFCSBaseAddr0Reg + ChipSel)) | ((UINT32)1 << BFOnDimmMirror ))); - } - } - } - } - - // - // Buffer to DRAM training - // - for (Dimm = 0; Dimm < MAX_DIMMS_PER_CHANNEL; Dimm++) { - DimmMask = (UINT16)1 << Dimm; - if ((NBPtr->ChannelPtr->LrDimmPresent & DimmMask) != 0) { - IDS_HDT_CONSOLE (MEM_STATUS, "\t\nDimm %d\n", Dimm); - // Select the Target Chipselects - NBPtr->SetBitField (NBPtr, BFMrsChipSel, (Dimm << 1)); - NBPtr->SetBitField (NBPtr, BFCtrlWordCS, 3 << (Dimm << 1)); - - // Send F0RC12 with data = 0010b. - MemTSendMBCtlWord3 (TechPtr, F0, RC12, 2); - - // Wait until D18F2xA0_dct[1:0][RcvParErr]=0 or tCAL * the number of physical ranks expires. - IDS_HDT_CONSOLE (MEM_FLOW, "\t\tWaiting %d ms...\n", 10 * NBPtr->ChannelPtr->LrDimmRankMult[Dimm]); - for (i = 0; i < (NBPtr->ChannelPtr->LrdimmPhysicalRanks[Dimm] * 10); i++) { - MemUWait10ns (1000000, MemPtr); - } - - // Configure for normal operation: Send F0RC12 with data = 0000b. - MemTSendMBCtlWord3 (TechPtr, F0, RC12, 0); - } - } - } - IDS_HDT_CONSOLE (MEM_FLOW, "\nEnd Buffer to DRAM training\n"); - } - return TRUE; -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * This function copies trained delays of the first rank of a QR LRDIMM to the third rank - * - * @param[in,out] *TechPtr - Pointer to the MEM_TECH_BLOCK - * @param[in,out] OptParam - Optional parameter - * - * @return TRUE - */ - -BOOLEAN -STATIC -MemTLrdimmSyncTrainedDlys ( - IN OUT MEM_TECH_BLOCK *TechPtr, - IN OUT VOID *OptParam - ) -{ - UINT8 i; - UINT8 Dimm; - MEM_NB_BLOCK *NBPtr; - CH_DEF_STRUCT *ChannelPtr; - - NBPtr = TechPtr->NBPtr; - ChannelPtr = NBPtr->ChannelPtr; - - if (NBPtr->MCTPtr->Status[SbLrdimms]) { - for (Dimm = 0; Dimm < MAX_DIMMS_PER_CHANNEL; Dimm++) { - for (i = 0; i < TechPtr->DlyTableWidth (); i++) { - if (ChannelPtr->LrDimmLogicalRanks[Dimm] > 2) { - // If logical QR LRDIMM, copy trained delays from first rank to third rank - NBPtr->SetTrainDly (NBPtr, AccessWrDqsDly, DIMM_BYTE_ACCESS (Dimm + 2, i), - ChannelPtr->WrDqsDlys[Dimm * TechPtr->DlyTableWidth () + i]); - NBPtr->SetTrainDly (NBPtr, AccessRcvEnDly, DIMM_BYTE_ACCESS (Dimm + 2, i), - ChannelPtr->RcvEnDlys[Dimm * TechPtr->DlyTableWidth () + i]); - NBPtr->SetTrainDly (NBPtr, AccessRdDqsDly, DIMM_BYTE_ACCESS (Dimm + 2, i), - ChannelPtr->RdDqsDlys[Dimm * TechPtr->DlyTableWidth () + i]); - NBPtr->SetTrainDly (NBPtr, AccessWrDqsDly, DIMM_BYTE_ACCESS (Dimm + 2, i), - ChannelPtr->WrDatDlys[Dimm * TechPtr->DlyTableWidth () + i]); - } - } - } - return TRUE; - } else { - return FALSE; - } -} - diff --git a/src/vendorcode/amd/agesa/f12/Proc/Mem/Tech/DDR3/mtlrdimm3.h b/src/vendorcode/amd/agesa/f12/Proc/Mem/Tech/DDR3/mtlrdimm3.h deleted file mode 100644 index cb3fc2f9c0..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/Mem/Tech/DDR3/mtlrdimm3.h +++ /dev/null @@ -1,125 +0,0 @@ -/** - * @file - * - * mtlrdimm3.h - * - * Definitions and declarations for DDR3 LRDIMM support - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: (Mem) - * @e \$Revision: 27045 $ @e \$Date: 2010-02-22 17:21:31 -0600 (Mon, 22 Feb 2010) $ - * - **/ -/***************************************************************************** - * - * Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * *************************************************************************** - * - */ - -#ifndef _MTLRDIMM3_H_ -#define _MTLRDIMM3_H_ - -/*---------------------------------------------------------------------------- - * Mixed (DEFINITIONS AND MACROS / TYPEDEFS, STRUCTURES, ENUMS) - * - *---------------------------------------------------------------------------- - */ - -/*----------------------------------------------------------------------------- - * DEFINITIONS AND MACROS - * - *----------------------------------------------------------------------------- - */ -#define RCW_FN_SELECT 7 - -#define F0 0 -#define F1 1 -#define F2 2 -#define F3 3 -#define F4 4 -#define F5 5 -#define F6 6 -#define F7 7 -#define F8 8 -#define F9 9 -#define F10 10 -#define F11 11 -#define F12 12 -#define F13 13 -#define F14 14 -#define F15 15 - -#define RC0 0 -#define RC1 1 -#define RC2 2 -#define RC3 3 -#define RC4 4 -#define RC5 5 -#define RC6 6 -#define RC7 7 -#define RC8 8 -#define RC9 9 -#define RC10 10 -#define RC11 11 -#define RC12 12 -#define RC13 13 -#define RC14 14 -#define RC15 15 - -#define SPD_NONE 0 -#define SPD_67 67 -#define SPD_68 68 -#define SPD_69 69 -#define SPD_70 70 -#define SPD_71 71 - -#define SPD_MDQ_800_1066 72 -#define SPD_QXODT_800_1066 73 -#define SPD_MR1_MR2_800_1066 77 -#define SPD_PERSONALITY_BYTE 150 - -#define SPD_FREQ_DIFF_OFFSET 6 - -#define SPECIAL_CASE 0xFF - -#define WAIT_6US 0xF6 - -/*---------------------------------------------------------------------------- - * TYPEDEFS, STRUCTURES, ENUMS - * - *---------------------------------------------------------------------------- - */ - - -/*---------------------------------------------------------------------------- - * FUNCTIONS PROTOTYPE - * - *---------------------------------------------------------------------------- - */ - -#endif /* _MTLRDIMM3_H_ */ diff --git a/src/vendorcode/amd/agesa/f12/Proc/Mem/Tech/DDR3/mtot3.c b/src/vendorcode/amd/agesa/f12/Proc/Mem/Tech/DDR3/mtot3.c deleted file mode 100644 index 29359a4be7..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/Mem/Tech/DDR3/mtot3.c +++ /dev/null @@ -1,168 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * mtot3.c - * - * Technology Non-SPD Timings for DDR3 - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: (Mem/Tech/DDR3) - * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $ - * - **/ -/***************************************************************************** -* -* Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* *************************************************************************** -* -*/ - -/* - *---------------------------------------------------------------------------- - * MODULES USED - * - *---------------------------------------------------------------------------- - */ - - - -#include "AGESA.h" -#include "Ids.h" -#include "mm.h" -#include "mn.h" -#include "mu.h" -#include "mt.h" -#include "mtot3.h" -#include "Filecode.h" -CODE_GROUP (G1_PEICC) -RDATA_GROUP (G1_PEICC) - -#define FILECODE PROC_MEM_TECH_DDR3_MTOT3_FILECODE -/*---------------------------------------------------------------------------- - * DEFINITIONS AND MACROS - * - *---------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------- - * TYPEDEFS AND STRUCTURES - * - *---------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------- - * PROTOTYPES OF LOCAL FUNCTIONS - * - *---------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------- - * EXPORTED FUNCTIONS - * - *---------------------------------------------------------------------------- - */ - -/* -----------------------------------------------------------------------------*/ -/** - * - * This function adjusts the Twrwr value for DDR3. - * - * @param[in,out] *TechPtr - Pointer to the MEM_TECH_BLOCK - * - */ - -VOID -MemTAdjustTwrwr3 ( - IN OUT MEM_TECH_BLOCK *TechPtr - ) -{ - DCT_STRUCT *DCTPtr; - - DCTPtr = TechPtr->NBPtr->DCTPtr; - - // For DDR3, value 0000b-0001b and >= 1011b of Twrwr is reserved. - if (DCTPtr->Timings.Twrwr < 2) { - DCTPtr->Timings.Twrwr = 2; - } else if (DCTPtr->Timings.Twrwr > 10) { - DCTPtr->Timings.Twrwr = 10; - } -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * This function adjusts the Twrrd value for DDR3. - * - * @param[in,out] *TechPtr - Pointer to the MEM_TECH_BLOCK - * - */ - -VOID -MemTAdjustTwrrd3 ( - IN OUT MEM_TECH_BLOCK *TechPtr - ) -{ - DCT_STRUCT *DCTPtr; - - DCTPtr = TechPtr->NBPtr->DCTPtr; - - // For DDR3, value 0000b, 0001b, and > 1010b of Twrrd is reserved. - if (DCTPtr->Timings.Twrrd < 2) { - DCTPtr->Timings.Twrrd = 2; - } else if (DCTPtr->Timings.Twrrd > 10) { - DCTPtr->Timings.Twrrd = 10; - } -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * This function gets the LD value for DDR3. - * - * @param[in,out] *TechPtr - Pointer to the MEM_TECH_BLOCK - * - * @return Value of LD - */ - -INT8 -MemTGetLD3 ( - IN OUT MEM_TECH_BLOCK *TechPtr - ) -{ - INT8 LD; - MEM_NB_BLOCK *NBPtr; - NBPtr = TechPtr->NBPtr; - // - // For DDR3, BIOS calculates the latency difference (Ld) as equal to read CAS latency minus write CAS - // latency, in MEMCLKs (see F2x[1, 0]88[Tcl] and F2x[1, 0]84[Tcwl]) which can be a negative or positive - // value. - // - LD = ((INT8) NBPtr->GetBitField (NBPtr, BFTcl) + 4) - ((INT8) NBPtr->GetBitField (NBPtr, BFTcwl) + 5); - - return LD; -} diff --git a/src/vendorcode/amd/agesa/f12/Proc/Mem/Tech/DDR3/mtot3.h b/src/vendorcode/amd/agesa/f12/Proc/Mem/Tech/DDR3/mtot3.h deleted file mode 100644 index bb047b20e4..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/Mem/Tech/DDR3/mtot3.h +++ /dev/null @@ -1,90 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * mtot3.h - * - * Technology Non-SPD timings for DDR3 - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: (Mem/Tech/DDR3) - * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $ - * - **/ -/***************************************************************************** - * - * Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * *************************************************************************** - * - */ - -#ifndef _MTOT3_H_ -#define _MTOT3_H_ - -/*---------------------------------------------------------------------------- - * Mixed (DEFINITIONS AND MACROS / TYPEDEFS, STRUCTURES, ENUMS) - * - *---------------------------------------------------------------------------- - */ - -/*----------------------------------------------------------------------------- - * DEFINITIONS AND MACROS - * - *----------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------- - * TYPEDEFS, STRUCTURES, ENUMS - * - *---------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------- - * FUNCTIONS PROTOTYPE - * - *---------------------------------------------------------------------------- - */ - - -VOID -MemTAdjustTwrwr3 ( - IN OUT MEM_TECH_BLOCK *TechPtr - ); - -VOID -MemTAdjustTwrrd3 ( - IN OUT MEM_TECH_BLOCK *TechPtr - ); - -INT8 -MemTGetLD3 ( - IN OUT MEM_TECH_BLOCK *TechPtr - ); - -#endif /* _MTOT3_H_ */ - - diff --git a/src/vendorcode/amd/agesa/f12/Proc/Mem/Tech/DDR3/mtrci3.c b/src/vendorcode/amd/agesa/f12/Proc/Mem/Tech/DDR3/mtrci3.c deleted file mode 100644 index b1d5994499..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/Mem/Tech/DDR3/mtrci3.c +++ /dev/null @@ -1,305 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * mtrci3.c - * - * Technology Control word initialization for DDR3 - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: (Mem/Tech/DDR3) - * @e \$Revision: 49617 $ @e \$Date: 2011-03-26 03:10:42 +0800 (Sat, 26 Mar 2011) $ - * - **/ -/***************************************************************************** -* -* Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* *************************************************************************** -* -*/ - -/* - *---------------------------------------------------------------------------- - * MODULES USED - * - *---------------------------------------------------------------------------- - */ - - - -#include "AGESA.h" -#include "Ids.h" -#include "mm.h" -#include "mn.h" -#include "mu.h" -#include "mt.h" -#include "mt3.h" -#include "mtrci3.h" -#include "merrhdl.h" -#include "Filecode.h" -CODE_GROUP (G1_PEICC) -RDATA_GROUP (G1_PEICC) - -#define FILECODE PROC_MEM_TECH_DDR3_MTRCI3_FILECODE -/*---------------------------------------------------------------------------- - * DEFINITIONS AND MACROS - * - *---------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------- - * TYPEDEFS AND STRUCTURES - * - *---------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------- - * PROTOTYPES OF LOCAL FUNCTIONS - * - *---------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------- - * EXPORTED FUNCTIONS - * - *---------------------------------------------------------------------------- - */ - -/* -----------------------------------------------------------------------------*/ -/** - * - * This function sends control words - * - * @param[in,out] *TechPtr - Pointer to the MEM_TECH_BLOCK - * - */ - -VOID -MemTDramControlRegInit3 ( - IN OUT MEM_TECH_BLOCK *TechPtr - ) -{ - UINT8 ChipSel; - UINT8 i; - UINT8 RawCard; - UINT8 Data; - UINT16 CsPresent; - - MEM_DATA_STRUCT *MemPtr; - MEM_NB_BLOCK *NBPtr; - - NBPtr = TechPtr->NBPtr; - MemPtr = NBPtr->MemPtr; - CsPresent = NBPtr->DCTPtr->Timings.CsPresent; - - MemUWait10ns (800, MemPtr); // wait 8us TACT must be changed to optimize to 8 MEM CLKs - - // Set EnDramInit to start DRAM initialization - - MemUWait10ns (600, MemPtr); // wait 6us for PLL LOCK - - for (ChipSel = 0; ChipSel < MAX_CS_PER_CHANNEL; ChipSel += 2) { - // - // If chip select present - // - if ((CsPresent & ((UINT16)3 << ChipSel)) != 0) { - NBPtr->SetBitField (NBPtr, BFMrsChipSel, ChipSel); - - // 2. Program F2x[1, 0]A8[CtrlWordCS]=bit mask for target chip selects. - NBPtr->SetBitField (NBPtr, BFCtrlWordCS, 3 << (ChipSel & 0xFE)); - - RawCard = NBPtr->ChannelPtr->RefRawCard[ChipSel >> 1]; - - for (i = 0; i <= 15; i++) { - // wait 8us for TMRD, must be changed to optimize to 8 MEM CLKs - MemUWait10ns (800, MemPtr); - if ((i != 6) && (i != 7)) { - Data = MemTGetCtlWord3 (TechPtr, i, RawCard, ChipSel); - MemTSendCtlWord3 (TechPtr, i, Data); - } - } - } - } - MemUWait10ns (600, MemPtr); // wait 6us for TSTAB -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * This function calculates the ControlRC value - * - * @param[in,out] *TechPtr - Pointer to the MEM_TECH_BLOCK - * @param[in] CtrlWordNum - control Word number. - * @param[in] RawCard - Raw Card - * @param[in] ChipSel - Target Chip Select - * @return Control Word value - */ - -UINT8 -MemTGetCtlWord3 ( - IN OUT MEM_TECH_BLOCK *TechPtr, - IN UINT8 CtrlWordNum, - IN UINT8 RawCard, - IN UINT8 ChipSel - ) -{ - UINT8 Data; - DCT_STRUCT *DCTPtr; - CH_DEF_STRUCT *ChannelPtr; - - DCTPtr = TechPtr->NBPtr->DCTPtr; - ChannelPtr = TechPtr->NBPtr->ChannelPtr; - - Data = 0; //Default value for all control words is 0 - switch (CtrlWordNum) { - case 0: - Data = 0x02; // DA4=1 - break; - case 1: - if (DCTPtr->Timings.DimmSRPresent & ((UINT16) 1 << (ChipSel >> 1))) { - Data = 0x0C; // if single rank, set DBA1 and DBA0 - } - break; - case 2: - Data = ChannelPtr->CtrlWrd02[ChipSel >> 1]; - break; - case 3: - Data = ChannelPtr->CtrlWrd03[ChipSel >> 1]; - break; - case 4: - Data = ChannelPtr->CtrlWrd04[ChipSel >> 1]; - break; - case 5: - Data = ChannelPtr->CtrlWrd05[ChipSel >> 1]; - break; - case 8: - Data = ChannelPtr->CtrlWrd08[ChipSel >> 1]; - break; - case 9: - Data = 0x0D; - break; - case 11: - Data = CONVERT_VDDIO_TO_ENCODED (TechPtr->RefPtr->DDR3Voltage); - break; - default:; - } - - return (Data & 0x0F); -} -/* -----------------------------------------------------------------------------*/ -/** - * - * This function sends control word command - * - * @param[in,out] *TechPtr - Pointer to the MEM_TECH_BLOCK - * @param[in] CmdNum - control number. - * @param[in] Value - value to send - * - */ - -VOID -MemTSendCtlWord3 ( - IN OUT MEM_TECH_BLOCK *TechPtr, - IN UINT8 CmdNum, - IN UINT8 Value - ) -{ - MEM_NB_BLOCK *NBPtr; - - NBPtr = TechPtr->NBPtr; - - // 1. Program MrsBank and MrsAddress. - // n = [BA2, A2, A1, A0]. - // data = [BA1, BA0, A4, A3]. - // Set all other bits in MrsAddress to zero. - // - NBPtr->SetBitField (NBPtr, BFMrsBank, ((CmdNum & 8) >> 1) | (Value >> 2)); - NBPtr->SetBitField (NBPtr, BFMrsAddress, ((Value & 3) << 3) | (CmdNum & 7)); - IDS_HDT_CONSOLE (MEM_FLOW, "\t\t\tCS%d RC%02d %04x\n", (MemNGetBitFieldNb (NBPtr, BFMrsChipSel) & 7), CmdNum, Value); - - // 2.Set SendCtrlWord=1 - NBPtr->SetBitField (NBPtr, BFSendCtrlWord, 1); - // 3.Wait for BFSendCtrlWord=0 - NBPtr->PollBitField (NBPtr, BFSendCtrlWord, 0, PCI_ACCESS_TIMEOUT, FALSE); -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * This function sends specific control words commands before frequency change for certain DRAM buffers. - * - * @param[in,out] *TechPtr - Pointer to the MEM_TECH_BLOCK - * - */ - -VOID -FreqChgCtrlWrd3 ( - IN OUT MEM_TECH_BLOCK *TechPtr - ) -{ - UINT8 ChipSel; - UINT16 Speed; - UINT16 CsPresent; - - MEM_DATA_STRUCT *MemPtr; - MEM_NB_BLOCK *NBPtr; - - NBPtr = TechPtr->NBPtr; - MemPtr = NBPtr->MemPtr; - Speed = NBPtr->DCTPtr->Timings.Speed; - CsPresent = NBPtr->DCTPtr->Timings.CsPresent; - - - for (ChipSel = 0; ChipSel < MAX_CS_PER_CHANNEL; ChipSel += 2) { - // - // If chip select present. - // - if ((CsPresent & ((UINT16)3 << ChipSel)) != 0) { - - NBPtr->SetBitField (NBPtr, BFMrsChipSel, ChipSel); - // program F2x[1, 0]A8[CtrlWordCS]=bit mask for target chip selects. - NBPtr->SetBitField (NBPtr, BFCtrlWordCS, 3 << (ChipSel & 0xFE)); - - //wait 8us for TMRD, must be changed to optimize to 8 MEM CLKs - MemUWait10ns (800, MemPtr); - if (Speed == DDR800_FREQUENCY) { - MemTSendCtlWord3 (TechPtr, 0x0A, 0); - } else if (Speed == DDR1066_FREQUENCY) { - MemTSendCtlWord3 (TechPtr, 0x0A, 1); - } else if (Speed == DDR1333_FREQUENCY) { - MemTSendCtlWord3 (TechPtr, 0x0A, 2); - } else if (Speed == DDR1600_FREQUENCY) { - MemTSendCtlWord3 (TechPtr, 0x0A, 3); - } else if (Speed == DDR1866_FREQUENCY) { - MemTSendCtlWord3 (TechPtr, 0x0A, 4); - } else { - ASSERT (FALSE); - } - } - } -} - diff --git a/src/vendorcode/amd/agesa/f12/Proc/Mem/Tech/DDR3/mtrci3.h b/src/vendorcode/amd/agesa/f12/Proc/Mem/Tech/DDR3/mtrci3.h deleted file mode 100644 index e70d934626..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/Mem/Tech/DDR3/mtrci3.h +++ /dev/null @@ -1,87 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * mtrci3.h - * - * Technology control word init for DDR3 - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: (Mem/Tech/DDR3) - * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $ - * - **/ -/***************************************************************************** - * - * Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * *************************************************************************** - * - */ - -#ifndef _MTRCI3_H_ -#define _MTRCI3_H_ - -/*---------------------------------------------------------------------------- - * Mixed (DEFINITIONS AND MACROS / TYPEDEFS, STRUCTURES, ENUMS) - * - *---------------------------------------------------------------------------- - */ - -/*----------------------------------------------------------------------------- - * DEFINITIONS AND MACROS - * - *----------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------- - * TYPEDEFS, STRUCTURES, ENUMS - * - *---------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------- - * FUNCTIONS PROTOTYPE - * - *---------------------------------------------------------------------------- - */ - -UINT8 -MemTGetCtlWord3 ( - IN OUT MEM_TECH_BLOCK *TechPtr, - IN UINT8 CtrlWordNum, - IN UINT8 RawCard, - IN UINT8 ChipSel - ); - -VOID -MemTDramControlRegInit3 ( - IN OUT MEM_TECH_BLOCK *TechPtr - ); - -#endif /* _MTRCI3_H_ */ - - diff --git a/src/vendorcode/amd/agesa/f12/Proc/Mem/Tech/DDR3/mtsdi3.c b/src/vendorcode/amd/agesa/f12/Proc/Mem/Tech/DDR3/mtsdi3.c deleted file mode 100644 index ea86205229..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/Mem/Tech/DDR3/mtsdi3.c +++ /dev/null @@ -1,503 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * mtsdi3.c - * - * Technology Software DRAM Init for DDR3 - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: (Mem/Tech/DDR3) - * @e \$Revision: 49104 $ @e \$Date: 2011-03-17 06:54:25 +0800 (Thu, 17 Mar 2011) $ - * - **/ -/***************************************************************************** -* -* Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* *************************************************************************** -* -*/ - - -/* - *---------------------------------------------------------------------------- - * MODULES USED - * - *---------------------------------------------------------------------------- - */ - - - -#include "AGESA.h" -#include "Ids.h" -#include "mm.h" -#include "mn.h" -#include "mu.h" -#include "mt.h" -#include "mt3.h" -#include "mtsdi3.h" -#include "mtrci3.h" -#include "merrhdl.h" -#include "Filecode.h" -CODE_GROUP (G1_PEICC) -RDATA_GROUP (G1_PEICC) -#define FILECODE PROC_MEM_TECH_DDR3_MTSDI3_FILECODE -/*---------------------------------------------------------------------------- - * DEFINITIONS AND MACROS - * - *---------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------- - * TYPEDEFS AND STRUCTURES - * - *---------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------- - * PROTOTYPES OF LOCAL FUNCTIONS - * - *---------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------- - * EXPORTED FUNCTIONS - * - *---------------------------------------------------------------------------- - */ - - - -/* -----------------------------------------------------------------------------*/ -/** - * - * This function initiates software DRAM init for both DCTs - * at the same time. - * - * @param[in,out] *TechPtr - Pointer to the MEM_TECH_BLOCK - * - */ - -BOOLEAN -MemTDramInitSw3 ( - IN OUT MEM_TECH_BLOCK *TechPtr - ) -{ - UINT8 Dct; - UINT8 ChipSel; - UINT32 Dummy; - - MEM_DATA_STRUCT *MemPtr; - DIE_STRUCT *MCTPtr; - MEM_NB_BLOCK *NBPtr; - - NBPtr = TechPtr->NBPtr; - MemPtr = NBPtr->MemPtr; - MCTPtr = NBPtr->MCTPtr; - - IDS_HDT_CONSOLE (MEM_STATUS, "\nStart Dram Init\n"); - // 3.Program F2x[1,0]7C[EnDramInit]=1 - IDS_HDT_CONSOLE (MEM_FLOW, "\tEnDramInit = 1 for both DCTs\n"); - NBPtr->BrdcstSet (NBPtr, BFEnDramInit, 1); - NBPtr->PollBitField (NBPtr, BFDctAccessDone, 1, PCI_ACCESS_TIMEOUT, TRUE); - - // 4.wait 200us - MemUWait10ns (20000, MemPtr); - - // 5.Program F2x[1, 0]7C[DeassertMemRstX] = 1. - NBPtr->BrdcstSet (NBPtr, BFDeassertMemRstX, 1); - - // 6.wait 500us - MemUWait10ns (50000, MemPtr); - - // Do Phy Fence training before sending MRS commands - if (!NBPtr->IsSupported[FenceTrnBeforeDramInit]) { - AGESA_TESTPOINT (TpProcMemPhyFenceTraining, &(NBPtr->MemPtr->StdHeader)); - for (Dct = 0; Dct < NBPtr->DctCount; Dct++) { - NBPtr->SwitchDCT (NBPtr, Dct); - if (NBPtr->DCTPtr->Timings.DctMemSize != 0) { - IDS_HDT_CONSOLE (MEM_STATUS, "\tDct %d\n", Dct); - NBPtr->PhyFenceTraining (NBPtr); - } - } - } - - // 7.NOP or deselect & take CKE high - NBPtr->BrdcstSet (NBPtr, BFAssertCke, 1); - - // 8.wait 360ns - MemUWait10ns (36, MemPtr); - - // The following steps are performed once for each channel with unbuffered DIMMs - // and once for each chip select on registered DIMMs: - for (Dct = 0; Dct < NBPtr->DctCount; Dct++) { - NBPtr->SwitchDCT (NBPtr, Dct); - if (NBPtr->DCTPtr->Timings.DctMemSize != 0) { - IDS_HDT_CONSOLE (MEM_STATUS, "\tDct %d\n", Dct); - - // Enable Dram Parity if appropriate. - NBPtr->FamilySpecificHook[EnableParityAfterMemRst] (NBPtr, NULL); - - // The following steps are performed with registered DIMMs only and - // must be done for each chip select pair: - if (MCTPtr->Status[SbRegistered]) { - MemTDramControlRegInit3 (TechPtr); - } - - // Initialize LRDIMM's register - TechPtr->TechnologySpecificHook[LrdimmControlRegInit] (TechPtr, NULL); - - for (ChipSel = 0; ChipSel < MAX_CS_PER_CHANNEL; ChipSel++) { - if (NBPtr->GetSysAddr (NBPtr, ChipSel, &Dummy)) { - IDS_HDT_CONSOLE (MEM_STATUS, "\t\tCS %d\n", ChipSel); - // if chip select present - if (!(TechPtr->TechnologySpecificHook[LrdimmSendAllMRCmds] (TechPtr, &ChipSel))) { - MemTSendAllMRCmds3 (TechPtr, ChipSel); - } - // NOTE: wait 512 clocks for DLL-relock - MemUWait10ns (50000, NBPtr->MemPtr); // wait 500us - if (!(MCTPtr->Status[SbRegistered] || MCTPtr->Status[SbLrdimms])) { - break; - } - } - } - - // 17.Send two ZQCL commands (to even then odd chip select) - NBPtr->sendZQCmd (NBPtr); - NBPtr->sendZQCmd (NBPtr); - } - } - - // 18.Program F2x[1,0]7C[EnDramInit]=0 - NBPtr->BrdcstSet (NBPtr, BFEnDramInit, 0); - NBPtr->PollBitField (NBPtr, BFDctAccessDone, 1, PCI_ACCESS_TIMEOUT, TRUE); - // - // For Unbuffered Dimms, Issue MRS for remaining CS without EnDramInit - // - NBPtr->FamilySpecificHook[SendMrsCmdsPerCs] (NBPtr, NBPtr); - - IDS_HDT_CONSOLE (MEM_FLOW, "End Dram Init\n\n"); - return (BOOLEAN) (MCTPtr->ErrCode < AGESA_FATAL); -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * This function calculates the EMRS1 value - * - * @param[in,out] *TechPtr - Pointer to the MEM_TECH_BLOCK - * @param[in] Wl - Indicates if WL mode should be enabled - * @param[in] TargetDIMM - DIMM target for WL - */ - -VOID -MemTEMRS13 ( - IN OUT MEM_TECH_BLOCK *TechPtr, - IN BOOLEAN Wl, - IN UINT8 TargetDIMM - ) -{ - UINT16 MrsAddress; - UINT8 MaxDimmPerCH; - UINT8 ChipSel; - UINT8 Value8; - - MEM_NB_BLOCK *NBPtr; - - NBPtr = TechPtr->NBPtr; - MaxDimmPerCH = GetMaxDimmsPerChannel (NBPtr->RefPtr->PlatformMemoryConfiguration, - NBPtr->MCTPtr->SocketId, - NBPtr->ChannelPtr->ChannelID); - ChipSel = (UINT8) (0x0FF & NBPtr->GetBitField (NBPtr, BFMrsChipSel)); - - // BA2=0,BA1=0,BA0=1 - NBPtr->SetBitField (NBPtr, BFMrsBank, 1); - - MrsAddress = 0; - - // program MrsAddress[5,1]=output driver impedance control (DIC): - // based on F2x[1,0]84[DrvImpCtrl] - if (!(NBPtr->IsSupported[CheckDrvImpCtrl])) { - Value8 = (UINT8)NBPtr->GetBitField (NBPtr, BFDrvImpCtrl); - if ((Value8 & ((UINT8) 1 << 1)) != 0) { - MrsAddress |= ((UINT16) 1 << 5); - } - if ((Value8 & ((UINT8) 1 << 0)) != 0) { - MrsAddress |= ((UINT16) 1 << 1); - } - } else { - MrsAddress |= ((UINT16) 1 << 1); - } - // program MrsAddress[9,6,2]=nominal termination resistance of ODT (RTT): - // Different CS may have different RTT. - // - Value8 = NBPtr->MemNGetDramTerm (NBPtr, ChipSel); - - // - // If Write Leveling this DIMM - // - if (Wl) { - if ((ChipSel >> 1) == TargetDIMM) { - // Program MrsAddress[7] = 1 for Write leveling enable - MrsAddress |= ((UINT16) 1 << 7); - if (ChipSel & 1) { - // Output buffer disabled, MrsAddress[7] (Qoff = 1) - MrsAddress |= ((UINT16) 1 << 12); - } - // Set Rtt_Nom = Rtt_Wr if there are 2 or more dimms - if ((NBPtr->ChannelPtr->DimmQrPresent != 0) || (NBPtr->ChannelPtr->Dimms >= 2)) { - Value8 = NBPtr->MemNGetDynDramTerm (NBPtr, ChipSel); - } else if (NBPtr->IsSupported[WlRttNomFor1of3Cfg] && (MaxDimmPerCH == 3)) { - // For some family, set Rtt_Nom = Rtt_Wr in one of three DIMMs per channel configurations - Value8 = NBPtr->MemNGetDynDramTerm (NBPtr, ChipSel); - } - } - } - // - // Turn off Rtt_Nom (DramTerm=0) for certain CS in certain configs. - // - // All odd CS for 4 Dimm Systems - if (MaxDimmPerCH == 4) { - if (ChipSel & 0x01) { - Value8 = 0; - } - // CS 1 and 5 for 3 Dimm configs - } else if (MaxDimmPerCH == 3) { - if ((ChipSel == 1) || (ChipSel == 5)) { - Value8 = 0; - } - } - // All odd CS of any QR Dimms - if ((NBPtr->ChannelPtr->DimmQrPresent & ((UINT8) (1 << (ChipSel >> 1)))) != 0) { - if (ChipSel & 0x01) { - Value8 = 0; - } - } - if ((Value8 & ((UINT8) 1 << 2)) != 0) { - MrsAddress |= ((UINT16) 1 << 9); - } - if ((Value8 & ((UINT8) 1 << 1)) != 0) { - MrsAddress |= ((UINT16) 1 << 6); - } - if ((Value8 & ((UINT8) 1 << 0)) != 0) { - MrsAddress |= ((UINT16) 1 << 2); - } - - // program MrsAddress[12]=output disable (QOFF): - // based on F2x[1,0]84[Qoff] - - if (!NBPtr->IsSupported[CheckQoff]) { - if (NBPtr->GetBitField (NBPtr, BFQoff) != 0) { - MrsAddress |= ((UINT16) 1 << 12); - } - } - - // program MrsAddress[11]=TDQS: - // based on F2x[1,0]94[RDqsEn] - - if ((NBPtr->DCTPtr->Timings.Dimmx4Present != 0) && (NBPtr->DCTPtr->Timings.Dimmx8Present != 0)) { - if (!(NBPtr->IsSupported[SetTDqsForx8DimmOnly]) || ((NBPtr->DCTPtr->Timings.Dimmx8Present & ((UINT8) 1 << (ChipSel >> 1))) != 0)) { - MrsAddress |= ((UINT16) 1 << 11); - } - } - - NBPtr->SetBitField (NBPtr, BFMrsAddress, MrsAddress); -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * This function calculates the EMRS2 value - * - * @param[in,out] *TechPtr - Pointer to the MEM_TECH_BLOCK - * - */ - -VOID -MemTEMRS23 ( - IN OUT MEM_TECH_BLOCK *TechPtr - ) -{ - UINT32 MrsAddress; - UINT8 DramTermDyn; - UINT8 MaxDimmPerCH; - UINT8 ChipSel; - MEM_NB_BLOCK *NBPtr; - - NBPtr = TechPtr->NBPtr; - - MaxDimmPerCH = GetMaxDimmsPerChannel (NBPtr->RefPtr->PlatformMemoryConfiguration, NBPtr->MCTPtr->SocketId, NBPtr->ChannelPtr->ChannelID ); - ChipSel = (UINT8) (0x0FF & NBPtr->GetBitField (NBPtr, BFMrsChipSel)); - - // BA2=0,BA1=1,BA0=0 - NBPtr->SetBitField (NBPtr, BFMrsBank, 2); - - // program MrsAddress[5:3]=CAS write latency (CWL): - MrsAddress = NBPtr->MemNGetMR2CWL (NBPtr); - - // program MrsAddress[6]=auto self refresh method (ASR): - // program MrsAddress[7]=self refresh temperature range (SRT): - MrsAddress |= 1 << 6; - MrsAddress &= ( ~ (1 << 7)); - - // program MrsAddress[10:9]=dynamic termination during writes (RTT_WR): - DramTermDyn = NBPtr->MemNGetDynDramTerm (NBPtr, ChipSel); - // Special Case for 1 DR Unbuffered Dimm in 3 Dimm/Ch - if (!(NBPtr->MCTPtr->Status[SbRegistered])) { - if (MaxDimmPerCH == 3) { - if (NBPtr->ChannelPtr->Dimms == 1) { - if ((NBPtr->ChannelPtr->DimmDrPresent & ((UINT8) (1 << (ChipSel >> 1)))) != 0) { - DramTermDyn = 1; - } - } - } - } - MrsAddress |= (UINT16) DramTermDyn << 9; - - NBPtr->SetBitField (NBPtr, BFMrsAddress, MrsAddress); -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * This function calculates the EMRS3 value - * - * @param[in,out] *TechPtr - Pointer to the MEM_TECH_BLOCK - * - */ - -VOID -MemTEMRS33 ( - IN OUT MEM_TECH_BLOCK *TechPtr - ) -{ - MEM_NB_BLOCK *NBPtr; - - NBPtr = TechPtr->NBPtr; - - // BA2=0,BA1=1,BA0=1 - NBPtr->SetBitField (NBPtr, BFMrsBank, 3); - - // program MrsAddress[1:0]=multi purpose register address location - // (MPR Location):based on F2x[1,0]84[MprLoc] - // program MrsAddress[2]=multi purpose register - // (MPR):based on F2x[1,0]84[MprEn] - NBPtr->SetBitField (NBPtr, BFMrsAddress, (NBPtr->GetBitField (NBPtr, BFDramMRSReg) >> 24) & 0x0007); -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * This sets MRS value - * - * @param[in,out] *TechPtr - Pointer to the MEM_TECH_BLOCK - * - */ - -VOID -MemTMRS3 ( - IN OUT MEM_TECH_BLOCK *TechPtr - ) -{ - UINT32 MrsAddress; - MEM_NB_BLOCK *NBPtr; - UINT32 Ppd; - - NBPtr = TechPtr->NBPtr; - - // BA2=0,BA1=0,BA0=0 - NBPtr->SetBitField (NBPtr, BFMrsBank, 0); - - // program MrsAddress[1:0]=burst length and control method - // (BL):based on F2x[1,0]84[BurstCtrl] - MrsAddress = NBPtr->GetBitField (NBPtr, BFBurstCtrl); - - // program MrsAddress[3]=1 (BT):interleaved - MrsAddress |= (UINT16) 1 << 3; - - // program MrsAddress[6:4,2]=read CAS latency - MrsAddress |= NBPtr->MemNGetMR0CL (NBPtr); - - // program MrsAddress[11:9]=write recovery for auto-precharge - MrsAddress |= NBPtr->MemNGetMR0WR (NBPtr); - - // program MrsAddress[12] (PPD):based on F2x[1,0]84[PChgPDModeSel] - Ppd = NBPtr->GetBitField (NBPtr, BFPchgPDModeSel); - NBPtr->FamilySpecificHook[MR0_PPD] (NBPtr, &Ppd); - IDS_OPTION_HOOK (IDS_MEM_MR0, &Ppd, &TechPtr->NBPtr->MemPtr->StdHeader); - MrsAddress |= Ppd << 12; - - // program MrsAddress[8]=1 (DLL):DLL reset - MrsAddress |= (UINT32) 1 << 8; - - // During memory initialization, the value sent to MR0 is saved for S3 resume - NBPtr->MemNSaveMR0 (NBPtr, MrsAddress); - - NBPtr->SetBitField (NBPtr, BFMrsAddress, MrsAddress); -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * This send all MR commands to a rank in sequence 2-3-1-0 - * - * @param[in,out] *TechPtr - Pointer to the MEM_TECH_BLOCK - * @param[in] ChipSel - Target Chip Select - */ - -VOID -MemTSendAllMRCmds3 ( - IN OUT MEM_TECH_BLOCK *TechPtr, - IN UINT8 ChipSel - ) -{ - MEM_NB_BLOCK *NBPtr; - - NBPtr = TechPtr->NBPtr; - - NBPtr->SetBitField (NBPtr, BFMrsChipSel, ChipSel); - - // 13.Send EMRS(2) - MemTEMRS23 (TechPtr); - AGESA_TESTPOINT (TpProcMemSendMRS2, &(NBPtr->MemPtr->StdHeader)); - NBPtr->SendMrsCmd (NBPtr); - - // 14.Send EMRS(3). Ordinarily at this time, MrsAddress[2:0]=000b - MemTEMRS33 (TechPtr); - AGESA_TESTPOINT (TpProcMemSendMRS3, &(NBPtr->MemPtr->StdHeader)); - NBPtr->SendMrsCmd (NBPtr); - - // 15.Send EMRS(1). - MemTEMRS13 (TechPtr, FALSE, (ChipSel >> 1)); - AGESA_TESTPOINT (TpProcMemSendMRS1, &(NBPtr->MemPtr->StdHeader)); - NBPtr->SendMrsCmd (NBPtr); - - // 16.Send MRS with MrsAddress[8]=1(reset the DLL) - MemTMRS3 (TechPtr); - AGESA_TESTPOINT (TpProcMemSendMRS0, &(NBPtr->MemPtr->StdHeader)); - NBPtr->SendMrsCmd (NBPtr); -} diff --git a/src/vendorcode/amd/agesa/f12/Proc/Mem/Tech/DDR3/mtsdi3.h b/src/vendorcode/amd/agesa/f12/Proc/Mem/Tech/DDR3/mtsdi3.h deleted file mode 100644 index 883546ebf8..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/Mem/Tech/DDR3/mtsdi3.h +++ /dev/null @@ -1,96 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * mtsdi3.h - * - * Technology software DRAM init for DDR3 - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: (Mem/Tech/DDR3) - * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $ - * - **/ -/***************************************************************************** - * - * Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * *************************************************************************** - * - */ - -#ifndef _MTSDI3_H_ -#define _MTSDI3_H_ - -/*---------------------------------------------------------------------------- - * Mixed (DEFINITIONS AND MACROS / TYPEDEFS, STRUCTURES, ENUMS) - * - *---------------------------------------------------------------------------- - */ - -/*----------------------------------------------------------------------------- - * DEFINITIONS AND MACROS - * - *----------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------- - * TYPEDEFS, STRUCTURES, ENUMS - * - *---------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------- - * FUNCTIONS PROTOTYPE - * - *---------------------------------------------------------------------------- - */ - -VOID -MemTEMRS33 ( - IN OUT MEM_TECH_BLOCK *TechPtr - ); - -VOID -MemTMRS3 ( - IN OUT MEM_TECH_BLOCK *TechPtr - ); - -VOID -MemTEMRS13 ( - IN OUT MEM_TECH_BLOCK *TechPtr, - IN BOOLEAN Wl, - IN UINT8 TargetDIMM - ); - -VOID -MemTEMRS23 ( - IN OUT MEM_TECH_BLOCK *TechPtr - ); - -#endif /* _MTSDI3_H_ */ - - diff --git a/src/vendorcode/amd/agesa/f12/Proc/Mem/Tech/DDR3/mtspd3.c b/src/vendorcode/amd/agesa/f12/Proc/Mem/Tech/DDR3/mtspd3.c deleted file mode 100644 index e0a1850ddc..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/Mem/Tech/DDR3/mtspd3.c +++ /dev/null @@ -1,1156 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * mtspd3.c - * - * Technology SPD supporting functions for DDR3 - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: (Mem/Tech/DDR3) - * @e \$Revision: 49133 $ @e \$Date: 2011-03-17 16:54:42 +0800 (Thu, 17 Mar 2011) $ - * - **/ -/***************************************************************************** -* -* Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* *************************************************************************** -* -*/ - -/* - *---------------------------------------------------------------------------- - * MODULES USED - * - *---------------------------------------------------------------------------- - */ - - - -#include "AGESA.h" -#include "AdvancedApi.h" -#include "Ids.h" -#include "mport.h" -#include "mm.h" -#include "mn.h" -#include "mt.h" -#include "mt3.h" -#include "mu.h" -#include "mtspd3.h" -#include "mftds.h" -#include "GeneralServices.h" -#include "Filecode.h" -CODE_GROUP (G1_PEICC) -RDATA_GROUP (G1_PEICC) - -#define FILECODE PROC_MEM_TECH_DDR3_MTSPD3_FILECODE - -/*---------------------------------------------------------------------------- - * DEFINITIONS AND MACROS - * - *---------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------- - * TYPEDEFS AND STRUCTURES - * - *---------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------- - * PROTOTYPES OF LOCAL FUNCTIONS - * - *---------------------------------------------------------------------------- - */ -BOOLEAN -STATIC -MemTCRCCheck3 ( - IN OUT UINT8 *SPDPtr - ); - -UINT8 -STATIC -MemTSPDGetTCL3 ( - IN OUT MEM_TECH_BLOCK *TechPtr - ); - -BOOLEAN -STATIC -MemTCheckBankAddr3 ( - IN UINT8 Encode, - OUT UINT8 *Index - ); - -/*---------------------------------------------------------------------------- - * EXPORTED FUNCTIONS - * - *---------------------------------------------------------------------------- - */ - -extern BUILD_OPT_CFG UserOptions; - -/* -----------------------------------------------------------------------------*/ -/** - * - * This function sets the DRAM mode - * - * @param[in,out] *TechPtr - Pointer to the MEM_TECH_BLOCK - * - * @return TRUE - indicates that the DRAM mode is set to DDR3 - */ - -BOOLEAN -MemTSetDramMode3 ( - IN OUT MEM_TECH_BLOCK *TechPtr - ) -{ - TechPtr->NBPtr->SetBitField (TechPtr->NBPtr, BFLegacyBiosMode, 0); - TechPtr->NBPtr->SetBitField (TechPtr->NBPtr, BFDdr3Mode, 1); - return TRUE; -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * This function determines if DIMMs are present. It checks checksum and interrogates the SPDs - * - * @param[in,out] *TechPtr - Pointer to the MEM_TECH_BLOCK - * - * @return TRUE - indicates that a FATAL error has not occurred - * @return FALSE - indicates that a FATAL error has occurred - */ - -BOOLEAN -MemTDIMMPresence3 ( - IN OUT MEM_TECH_BLOCK *TechPtr - ) -{ - UINT8 Dct; - UINT8 Channel; - UINT8 i; - MEM_PARAMETER_STRUCT *RefPtr; - UINT8 *SpdBufferPtr = NULL; - DIE_STRUCT *MCTPtr; - DCT_STRUCT *DCTPtr; - CH_DEF_STRUCT *ChannelPtr; - MEM_NB_BLOCK *NBPtr; - BOOLEAN SPDCtrl; - UINT8 Devwidth; - UINT8 MaxDimms; - UINT8 Value8; - UINT16 DimmMask; - - NBPtr = TechPtr->NBPtr; - RefPtr = NBPtr->RefPtr; - MCTPtr = NBPtr->MCTPtr; - - SPDCtrl = UserOptions.CfgIgnoreSpdChecksum; - for (Dct = 0; Dct < NBPtr->DctCount; Dct++) { - NBPtr->SwitchDCT (NBPtr, Dct); - DCTPtr = NBPtr->DCTPtr; - for (Channel = 0; Channel < NBPtr->ChannelCount; Channel++) { - NBPtr->SwitchChannel (NBPtr, Channel); - ChannelPtr = NBPtr->ChannelPtr; - ChannelPtr->DimmQrPresent = 0; - // - // Get the maximum number of DIMMs - // - MaxDimms = MAX_DIMMS_PER_CHANNEL; - for (i = 0; i < MaxDimms; i++) { - // Bitmask representing dimm #i. - DimmMask = (UINT16)1 << i; - // - if (MemTGetDimmSpdBuffer3 (TechPtr, &SpdBufferPtr, i)) { - MCTPtr->DimmPresent |= DimmMask; - // - // Check for valid checksum value - // - AGESA_TESTPOINT (TpProcMemSPDChecking, &(NBPtr->MemPtr->StdHeader)); - if (SpdBufferPtr[SPD_TYPE] == JED_DDR3SDRAM) { - ChannelPtr->ChDimmValid |= DimmMask; - MCTPtr->DimmValid |= DimmMask; - } else { - // Current socket is set up to only support DDR3 dimms. - IDS_ERROR_TRAP; - } - if (!MemTCRCCheck3 (SpdBufferPtr) && !SPDCtrl) { - // - // NV_SPDCHK_RESTRT is set to 0, - // cannot ignore faulty SPD checksum - // - // Indicate checksum error - ChannelPtr->DimmSpdCse |= DimmMask; - PutEventLog (AGESA_ERROR, MEM_ERROR_CHECKSUM_NV_SPDCHK_RESTRT_ERROR, NBPtr->Node, NBPtr->Dct, NBPtr->Channel, 0, &NBPtr->MemPtr->StdHeader); - SetMemError (AGESA_ERROR, MCTPtr); - } - // - // Check module type information. - // - if (SpdBufferPtr[SPD_DIMM_TYPE] == JED_LRDIMM) { - // - // LRDIMMS - // - ChannelPtr->LrDimmPresent |= DimmMask; - MCTPtr->LrDimmPresent |= DimmMask; - if (!UserOptions.CfgMemoryLRDimmCapable) { - PutEventLog (AGESA_WARNING, MEM_WARNING_UNSUPPORTED_LRDIMM, NBPtr->Node, NBPtr->Dct, NBPtr->Channel, 0, &NBPtr->MemPtr->StdHeader); - IDS_ERROR_TRAP; - } - } - if (SpdBufferPtr[SPD_DIMM_TYPE] == JED_RDIMM || SpdBufferPtr[SPD_DIMM_TYPE] == JED_MINIRDIMM) { - // - // RDIMMS - // - ChannelPtr->RegDimmPresent |= DimmMask; - MCTPtr->RegDimmPresent |= DimmMask; - if (!UserOptions.CfgMemoryRDimmCapable) { - PutEventLog (AGESA_WARNING, MEM_WARNING_UNSUPPORTED_RDIMM, NBPtr->Node, NBPtr->Dct, NBPtr->Channel, 0, &NBPtr->MemPtr->StdHeader); - IDS_ERROR_TRAP; - } - } - if ((SpdBufferPtr[SPD_DIMM_TYPE] == JED_UDIMM) && !UserOptions.CfgMemoryUDimmCapable) { - PutEventLog (AGESA_WARNING, MEM_WARNING_UNSUPPORTED_UDIMM, NBPtr->Node, NBPtr->Dct, NBPtr->Channel, 0, &NBPtr->MemPtr->StdHeader); - IDS_ERROR_TRAP; - } - if (SpdBufferPtr[SPD_DIMM_TYPE] == JED_SODIMM) { - ChannelPtr->SODimmPresent |= DimmMask; - if (!UserOptions.CfgMemorySODimmCapable) { - PutEventLog (AGESA_WARNING, MEM_WARNING_UNSUPPORTED_SODIMM, NBPtr->Node, NBPtr->Dct, NBPtr->Channel, 0, &NBPtr->MemPtr->StdHeader); - IDS_ERROR_TRAP; - } - } - // - // Check error correction type - // - if ((SpdBufferPtr[SPD_ECCBITS] & JED_ECC) != 0) { - MCTPtr->DimmEccPresent |= DimmMask; // Dimm has ECC - } - // - // Get the Dimm width data - // - Devwidth = SpdBufferPtr[SPD_DEV_WIDTH] & 0x7; - switch (Devwidth) { - case 0: - ChannelPtr->Dimmx4Present |= DimmMask; - Devwidth = 4; - break; - case 1: - ChannelPtr->Dimmx8Present |= DimmMask; - Devwidth = 8; - break; - case 2: - ChannelPtr->Dimmx16Present |= DimmMask; - Devwidth = 16; - break; - default: - IDS_ERROR_TRAP; - } - // - // Check for 'analysis probe installed' - // if (SpdBufferPtr[SPD_ATTRIB] & JED_PROBE_MSK) - // - // Determine the geometry of the DIMM module - // if (SpdBufferPtr[SPD_DM_BANKS] & SP_DPL_BIT) - // - // specify the number of ranks - // - Value8 = ((SpdBufferPtr[SPD_RANKS] >> 3) & 0x07) + 1; - if (Value8 == 5) { - // Octal Rank - Value8 = 8; - } - // - // For LRDIMMS we will assume that if there are at least 4 Physical ranks, then it Could be used - // as a QR RDIMM with a rank Mux of x1 and therefore all four CS will be used. So an 8R LRDIMM will - // be marked as a QR even if Rank multiplication allows it to use only 2 logical ranks. - // - if ((ChannelPtr->LrDimmPresent & DimmMask) != 0) { - // - // LRDIMM Physical Ranks - // - ChannelPtr->LrdimmPhysicalRanks[i] = Value8; - } - if (Value8 > 2) { - if (!UserOptions.CfgMemoryQuadRankCapable) { - PutEventLog (AGESA_WARNING, MEM_WARNING_UNSUPPORTED_QRDIMM, NBPtr->Node, NBPtr->Dct, NBPtr->Channel, 0, &NBPtr->MemPtr->StdHeader); - } - // - // Mark this Dimm as Quad Rank - // - ChannelPtr->DimmQrPresent |= DimmMask; - Value8 = 2; - } else if (Value8 == 2) { - ChannelPtr->DimmDrPresent |= DimmMask; // Dual rank dimms - } else { - ChannelPtr->DimmSRPresent |= DimmMask; // Single rank dimms - } - // - // Calculate bus loading per Channel - if (Devwidth == 16) { - Devwidth = 4; - } else if (Devwidth == 4) { - Devwidth = 16; - } - // - // Double Addr bus load value for dual rank DIMMs (Unless LRDIMM) - // - if (((ChannelPtr->LrDimmPresent & DimmMask) == 0) && (Value8 == 2) ) { - Devwidth = Devwidth << 1; - } - // - ChannelPtr->Ranks = ChannelPtr->Ranks + Value8; - ChannelPtr->Loads = ChannelPtr->Loads + Devwidth; - if ((i < 2) || ((ChannelPtr->DimmQrPresent & DimmMask) == 0)) { - ChannelPtr->Dimms++; - } - // - // Check address mirror support for Unbuffered Dimms or LRDimms - // - if ((ChannelPtr->RegDimmPresent & DimmMask) == 0) { - if ((SpdBufferPtr[SPD_ADDRMAP] & 1) != 0) { - ChannelPtr->DimmMirrorPresent |= DimmMask; - } - } - // - // Get byte62: Reference Raw Card information - // - ChannelPtr->RefRawCard[i] = SpdBufferPtr[SPD_RAWCARD] & 0x1F; - // - // Get control word values for RC3, RC4 and RC5 - // - ChannelPtr->CtrlWrd03[i] = SpdBufferPtr[SPD_CTLWRD03] >> 4; - ChannelPtr->CtrlWrd04[i] = SpdBufferPtr[SPD_CTLWRD04] & 0x0F; - ChannelPtr->CtrlWrd05[i] = SpdBufferPtr[SPD_CTLWRD05] >> 4; - // - // Temporarily store info. of SPD byte 63 into CtrlWrd02(s), - // and they will be used late to calculate real RC2 and RC8 value - // - ChannelPtr->CtrlWrd02[i] = SpdBufferPtr[SPD_ADDRMAP] & 0x03; - // - // Copy the number of registers to the Ps Block to persist across frequency changes - // - NBPtr->PsPtr->NumOfReg[i] = SpdBufferPtr[SPD_ADDRMAP] & 0x03; - // - // Workaround for early revisions of DIMMs which SPD byte 63 is 0 - // - if (NBPtr->PsPtr->NumOfReg[i] == JED_UNDEFINED) { - NBPtr->PsPtr->NumOfReg[i] = 1; - } - } // if DIMM present - } // Dimm loop - - if (Channel == 0) { - DCTPtr->Timings.DctDimmValid = ChannelPtr->ChDimmValid; - DCTPtr->Timings.DimmMirrorPresent = ChannelPtr->DimmMirrorPresent; - DCTPtr->Timings.DimmSpdCse = ChannelPtr->DimmSpdCse; - DCTPtr->Timings.DimmQrPresent = ChannelPtr->DimmQrPresent; - DCTPtr->Timings.DimmDrPresent = ChannelPtr->DimmDrPresent; - DCTPtr->Timings.DimmSRPresent = ChannelPtr->DimmSRPresent; - DCTPtr->Timings.Dimmx4Present = ChannelPtr->Dimmx4Present; - DCTPtr->Timings.Dimmx8Present = ChannelPtr->Dimmx8Present; - DCTPtr->Timings.Dimmx16Present = ChannelPtr->Dimmx16Present; - } - if ((Channel != 1) || (Dct != 1)) { - MCTPtr->DimmPresent <<= 8; - MCTPtr->DimmValid <<= 8; - MCTPtr->RegDimmPresent <<= 8; - MCTPtr->LrDimmPresent <<= 8; - MCTPtr->DimmEccPresent <<= 8; - MCTPtr->DimmParPresent <<= 8; - } - } // Channel loop - } // DCT loop - - // If we have DIMMs, some further general characteristics checking - if (MCTPtr->DimmValid != 0) { - // If there are registered dimms, all the dimms must be registered - if (MCTPtr->RegDimmPresent == MCTPtr->DimmValid) { - // All dimms registered - MCTPtr->Status[SbRegistered] = TRUE; - MCTPtr->Status[SbParDimms] = TRUE; // All DDR3 RDIMMs are parity capable - TechPtr->SetDqsEccTmgs = MemTSetDQSEccTmgsRDdr3; // Change the function pointer for DQS ECC timing - } else if (MCTPtr->RegDimmPresent != 0) { - // We have an illegal DIMM mismatch - PutEventLog (AGESA_FATAL, MEM_ERROR_MODULE_TYPE_MISMATCH_DIMM, NBPtr->Node, NBPtr->Dct, NBPtr->Channel, 0, &NBPtr->MemPtr->StdHeader); - SetMemError (AGESA_FATAL, MCTPtr); - } - // If there are LrDimms, all the dimms must be LrDimms - if (MCTPtr->LrDimmPresent == MCTPtr->DimmValid) { - // All dimms LRDIMMs - MCTPtr->Status[SbLrdimms] = TRUE; - } else if (MCTPtr->LrDimmPresent != 0) { - // We have an illegal DIMM mismatch - PutEventLog (AGESA_FATAL, MEM_ERROR_MODULE_TYPE_MISMATCH_DIMM, NBPtr->Node, NBPtr->Dct, NBPtr->Channel, 0, &NBPtr->MemPtr->StdHeader); - SetMemError (AGESA_FATAL, MCTPtr); - } - - // check the ECC capability of the DIMMs - if (MCTPtr->DimmEccPresent == MCTPtr->DimmValid) { - MCTPtr->Status[SbEccDimms] = TRUE; // All dimms ECC capable - } - } else { - } - - NBPtr->SwitchDCT (NBPtr, 0); - NBPtr->SwitchChannel (NBPtr, 0); - return (BOOLEAN) (MCTPtr->ErrCode < AGESA_FATAL); -} - - -/* -----------------------------------------------------------------------------*/ -/** - * - * This function finds the maximum frequency that each channel is capable to run at. - * - * @param[in,out] *TechPtr - Pointer to the MEM_TECH_BLOCK - * - * @return TRUE - indicates that a FATAL error has not occurred - * @return FALSE - indicates that a FATAL error has occurred - */ - -BOOLEAN -MemTSPDGetTargetSpeed3 ( - IN OUT MEM_TECH_BLOCK *TechPtr - ) -{ - UINT8 *SpdBufferPtr = NULL; - UINT8 Dimm; - UINT8 Dct; - UINT8 Channel; - INT32 MTB_ps; - INT32 FTB_ps; - INT32 TCKmin_ps; - INT32 Value32; - MEM_NB_BLOCK *NBPtr; - DCT_STRUCT *DCTPtr; - CH_DEF_STRUCT *ChannelPtr; - - NBPtr = TechPtr->NBPtr; - for (Dct = 0; Dct < NBPtr->DctCount; Dct++) { - NBPtr->SwitchDCT (NBPtr, Dct); - DCTPtr = NBPtr->DCTPtr; - TCKmin_ps = 0; - for (Channel = 0; Channel < NBPtr->ChannelCount; Channel++) { - NBPtr->SwitchChannel (NBPtr, Channel); - ChannelPtr = NBPtr->ChannelPtr; - for (Dimm = 0; Dimm < MAX_DIMMS_PER_CHANNEL; Dimm++) { - if ((ChannelPtr->ChDimmValid & ((UINT8)1 << Dimm)) != 0) { - MemTGetDimmSpdBuffer3 (TechPtr, &SpdBufferPtr, Dimm); - - // Determine tCKmin(all) which is the largest tCKmin - // value for all modules on the memory Channel (SPD byte 12). - // - MTB_ps = ((INT32) SpdBufferPtr[SPD_DIVIDENT] * 1000) / SpdBufferPtr[SPD_DIVISOR]; - FTB_ps = (SpdBufferPtr[SPD_FTB] >> 4) / (SpdBufferPtr[SPD_FTB] & 0xF); - Value32 = (MTB_ps * SpdBufferPtr[SPD_TCK]) + (FTB_ps * (INT8) SpdBufferPtr[SPD_TCK_FTB]) ; - if (TCKmin_ps < Value32) { - TCKmin_ps = Value32; - } - } - } - } - if (TCKmin_ps <= 1071) { - DCTPtr->Timings.TargetSpeed = DDR1866_FREQUENCY; - } else if (TCKmin_ps <= 1250) { - DCTPtr->Timings.TargetSpeed = DDR1600_FREQUENCY; - } else if (TCKmin_ps <= 1500) { - DCTPtr->Timings.TargetSpeed = DDR1333_FREQUENCY; - } else if (TCKmin_ps <= 1875) { - DCTPtr->Timings.TargetSpeed = DDR1066_FREQUENCY; - } else if (TCKmin_ps <= 2500) { - DCTPtr->Timings.TargetSpeed = DDR800_FREQUENCY; - } else { - DCTPtr->Timings.TargetSpeed = DDR667_FREQUENCY; - } - } - - // Ensure the target speed can be applied to all channels of the current node - NBPtr->SyncTargetSpeed (NBPtr); - - // Set the start-up frequency - for (Dct = 0; Dct < NBPtr->DctCount; Dct++) { - NBPtr->SwitchDCT (NBPtr, Dct); - NBPtr->DCTPtr->Timings.Speed = TechPtr->NBPtr->StartupSpeed; - } - return (BOOLEAN) (NBPtr->MCTPtr->ErrCode < AGESA_FATAL); -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * This function check the symmetry of DIMM pairs (DIMM on Channel A matching with - * DIMM on Channel B), the overall DIMM population, and determine the width mode: - * 64-bit, 64-bit muxed, 128-bit. - * - * @param[in,out] *TechPtr - Pointer to the MEM_TECH_BLOCK - * - * @return TRUE - indicates that a FATAL error has not occurred - * @return FALSE - indicates that a FATAL error has occurred - */ - -BOOLEAN -MemTSPDCalcWidth3 ( - IN OUT MEM_TECH_BLOCK *TechPtr - ) -{ - UINT8 *SpdBufferAPtr = NULL; - UINT8 *SpdBufferBPtr = NULL; - MEM_NB_BLOCK *NBPtr; - DIE_STRUCT *MCTPtr; - DCT_STRUCT *DCTPtr; - UINT8 i; - UINT16 DimmMask; - UINT8 UngangMode; - - NBPtr = TechPtr->NBPtr; - MCTPtr = NBPtr->MCTPtr; - DCTPtr = NBPtr->DCTPtr; - UngangMode = UserOptions.CfgMemoryModeUnganged; - // Does not support ganged mode for DDR3 dimms - ASSERT (UngangMode); - IDS_OPTION_HOOK (IDS_GANGING_MODE, &UngangMode, &(NBPtr->MemPtr->StdHeader)); - - // Check symmetry of channel A and channel B dimms for 128-bit mode - // capability. - // - AGESA_TESTPOINT (TpProcMemModeChecking, &(NBPtr->MemPtr->StdHeader)); - i = 0; - if (!UngangMode) { - if (MCTPtr->DctData[0].Timings.DctDimmValid == MCTPtr->DctData[1].Timings.DctDimmValid) { - for (; i < MAX_DIMMS_PER_CHANNEL; i++) { - DimmMask = (UINT16)1 << i; - if ((DCTPtr->Timings.DctDimmValid & DimmMask) != 0) { - NBPtr->SwitchDCT (NBPtr, 0); - MemTGetDimmSpdBuffer3 (TechPtr, &SpdBufferAPtr, i); - NBPtr->SwitchDCT (NBPtr, 1); - MemTGetDimmSpdBuffer3 (TechPtr, &SpdBufferBPtr, i); - // compare rows and columns - if ((SpdBufferAPtr[SPD_ROW_SZ]&0x3F) != (SpdBufferBPtr[SPD_ROW_SZ]&0x3F)) { - break; - } - if ((SpdBufferAPtr[SPD_DENSITY]&0x0F) != (SpdBufferBPtr[SPD_DENSITY]&0x0F)) { - break; - } - // compare ranks and devwidth - if ((SpdBufferAPtr[SPD_DEV_WIDTH]&0x7F) != (SpdBufferBPtr[SPD_DEV_WIDTH]&0x7F)) { - break; - } - } - } - } - if (i < MAX_DIMMS_PER_CHANNEL) { - PutEventLog (AGESA_ALERT, MEM_ALERT_ORG_MISMATCH_DIMM, NBPtr->Node, NBPtr->Dct, NBPtr->Channel, 0, &NBPtr->MemPtr->StdHeader); - SetMemError (AGESA_ALERT, MCTPtr); - } else { - NBPtr->Ganged = TRUE; - MCTPtr->GangedMode = TRUE; - MCTPtr->Status[Sb128bitmode] = TRUE; - NBPtr->SetBitField (NBPtr, BFDctGangEn, 1); - } - } - - return (BOOLEAN) (MCTPtr->ErrCode < AGESA_FATAL); -} - - -/* -----------------------------------------------------------------------------*/ -/** - * - * Initialize DCT Timing registers as per DIMM SPD. - * For primary timing (T, CL) use best case T value. - * For secondary timing params., use most aggressive settings - * of slowest DIMM. - * - * Note: - * There are three components to determining "maximum frequency": SPD component, - * Bus load component, and "Preset" max frequency component. - * The SPD component is a function of the min cycle time specified by each DIMM, - * and the interaction of cycle times from all DIMMs in conjunction with CAS - * latency. The SPD component only applies when user timing mode is 'Auto'. - * - * The Bus load component is a limiting factor determined by electrical - * characteristics on the bus as a result of varying number of device loads. The - * Bus load component is specific to each platform but may also be a function of - * other factors. The bus load component only applies when user timing mode is - * ' Auto'. - * - * The Preset component is subdivided into three items and is the minimum of - * the set: Silicon revision, user limit setting when user timing mode is 'Auto' and - * memclock mode is 'Limit', OEM build specification of the maximum frequency. - * The Preset component only applies when user timing mode is 'Auto'. - * - * @param[in,out] *TechPtr - Pointer to the MEM_TECH_BLOCK - * - * @return TRUE - indicates that a FATAL error has not occurred - * @return FALSE - indicates that a FATAL error has occurred - */ - -BOOLEAN -MemTAutoCycTiming3 ( - IN OUT MEM_TECH_BLOCK *TechPtr - ) -{ - CONST UINT8 SpdIndexes[] = { - SPD_TRCD, - SPD_TRP, - SPD_TRTP, - SPD_TRAS, - SPD_TRC, - SPD_TWR, - SPD_TRRD, - SPD_TWTR, - SPD_TFAW - }; - - CONST UINT8 SpdFTBIndexes[] = { - SPD_TRCD_FTB, - SPD_TRP_FTB, - 0, - 0, - SPD_TRC_FTB, - 0, - 0, - 0, - 0 - }; - - UINT8 *SpdBufferPtr = NULL; - INT32 MiniMaxTmg[GET_SIZE_OF (SpdIndexes)]; - UINT8 MiniMaxTrfc[4]; - - DIE_STRUCT *MCTPtr; - DCT_STRUCT *DCTPtr; - MEM_NB_BLOCK *NBPtr; - UINT16 DimmMask; - INT32 Value32; - INT32 MTB_ps; - INT32 FTB_ps; - INT32 TCK_ps; - UINT8 i; - UINT8 j; - UINT8 Value8; - UINT8 *StatTmgPtr; - UINT16 *StatDimmTmgPtr; - - NBPtr = TechPtr->NBPtr; - MCTPtr = NBPtr->MCTPtr; - DCTPtr = NBPtr->DCTPtr; - // initialize mini-max arrays - for (j = 0; j < GET_SIZE_OF (MiniMaxTmg); j++) { - MiniMaxTmg[j] = 0; - } - for (j = 0; j < GET_SIZE_OF (MiniMaxTrfc); j++) { - MiniMaxTrfc[j] = 0; - } - - // ====================================================================== - // Get primary timing (CAS Latency and Cycle Time) - // ====================================================================== - // Get OEM specific load variant max - // - - //====================================================================== - // Gather all DIMM mini-max values for cycle timing data - //====================================================================== - // - DimmMask = 1; - for (i = 0; i < (MAX_CS_PER_CHANNEL / 2); i++) { - if ((DCTPtr->Timings.DctDimmValid & DimmMask) != 0) { - MemTGetDimmSpdBuffer3 (TechPtr, &SpdBufferPtr, i); - MTB_ps = ((INT32) SpdBufferPtr[SPD_DIVIDENT] * 1000) / SpdBufferPtr[SPD_DIVISOR]; - FTB_ps = (SpdBufferPtr[SPD_FTB] >> 4) / (SpdBufferPtr[SPD_FTB] & 0xF); - - for (j = 0; j < GET_SIZE_OF (SpdIndexes); j++) { - Value32 = (UINT16)SpdBufferPtr[SpdIndexes[j]]; - if (SpdIndexes[j] == SPD_TRC) { - Value32 |= ((UINT16)SpdBufferPtr[SPD_UPPER_TRC] & 0xF0) << 4; - } else if (SpdIndexes[j] == SPD_TRAS) { - Value32 |= ((UINT16)SpdBufferPtr[SPD_UPPER_TRAS] & 0x0F) << 8; - } else if (SpdIndexes[j] == SPD_TFAW) { - Value32 |= ((UINT16)SpdBufferPtr[SPD_UPPER_TFAW] & 0x0F) << 8; - } - - Value32 *= MTB_ps; - if (SpdFTBIndexes[j] != 0) { - Value32 += (FTB_ps * (INT8) SpdBufferPtr[SpdFTBIndexes[j]]) ; - } - if (MiniMaxTmg[j] < Value32) { - MiniMaxTmg[j] = Value32; - } - } - - // get Trfc0 - Trfc3 values - Value8 = SpdBufferPtr[SPD_DENSITY] & 0x0F; - if (MiniMaxTrfc[i] < Value8) { - MiniMaxTrfc[i] = Value8; - } - } - DimmMask <<= 1; - } - - // ====================================================================== - // Convert DRAM CycleTiming values and store into DCT structure - // ====================================================================== - // - TCK_ps = 1000500 / DCTPtr->Timings.Speed; - - StatDimmTmgPtr = &DCTPtr->Timings.DIMMTrcd; - StatTmgPtr = &DCTPtr->Timings.Trcd; - for (j = 0; j < GET_SIZE_OF (SpdIndexes); j++) { - Value32 = MiniMaxTmg[j]; - - MiniMaxTmg[j] = (MiniMaxTmg[j] + TCK_ps - 1) / TCK_ps; - - StatDimmTmgPtr[j] = (UINT16) (Value32 / (1000 / 40)); - StatTmgPtr[j] = (UINT8) MiniMaxTmg[j]; - } - DCTPtr->Timings.Trfc0 = MiniMaxTrfc[0]; - DCTPtr->Timings.Trfc1 = MiniMaxTrfc[1]; - DCTPtr->Timings.Trfc2 = MiniMaxTrfc[2]; - DCTPtr->Timings.Trfc3 = MiniMaxTrfc[3]; - - DCTPtr->Timings.CasL = MemTSPDGetTCL3 (TechPtr); - - //====================================================================== - // Program DRAM Timing values - //====================================================================== - // - NBPtr->ProgramCycTimings (NBPtr); - - MemFInitTableDrive (NBPtr, MTAfterAutoCycTiming); - - return (BOOLEAN) (MCTPtr->ErrCode < AGESA_FATAL); -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * This function sets the bank addressing, program Mask values and build a chip-select population map. - * This routine programs PCI 0:24N:2x80 config register. - * This routine programs PCI 0:24N:2x60,64,68,6C config registers (CS Mask 0-3) - * - * @param[in,out] *TechPtr - Pointer to the MEM_TECH_BLOCK - * - * @return TRUE - indicates that a FATAL error has not occurred - * @return FALSE - indicates that a FATAL error has occurred - */ - -BOOLEAN -MemTSPDSetBanks3 ( - IN OUT MEM_TECH_BLOCK *TechPtr - ) -{ - UINT8 *SpdBufferPtr = NULL; - UINT8 i; - UINT8 ChipSel; - UINT8 DimmID; - UINT8 Value8; - UINT8 Rows; - UINT8 Cols; - UINT8 Ranks; - UINT8 Banks; - UINT32 BankAddrReg; - UINT32 CsMask; - UINT16 CSSpdCSE; - UINT16 CSExclude; - UINT16 DimmQRDR; - DIE_STRUCT *MCTPtr; - DCT_STRUCT *DCTPtr; - MEM_NB_BLOCK *NBPtr; - - NBPtr = TechPtr->NBPtr; - MCTPtr = NBPtr->MCTPtr; - DCTPtr = NBPtr->DCTPtr; - BankAddrReg = 0; - CSSpdCSE = 0; - CSExclude = 0; - - for (ChipSel = 0; ChipSel < MAX_CS_PER_CHANNEL; ChipSel += 2) { - DimmID = ChipSel >> 1; - - DimmQRDR = (DCTPtr->Timings.DimmQrPresent) | (DCTPtr->Timings.DimmDrPresent); - if ((DCTPtr->Timings.DimmSpdCse & ((UINT16) 1 << DimmID)) != 0) { - CSSpdCSE |= (UINT16) ((DimmQRDR & (UINT16) 1 << DimmID) ? 3 : 1) << ChipSel; - } - if ((DCTPtr->Timings.DimmExclude & ((UINT16) 1 << DimmID)) != 0) { - CSExclude |= (UINT16) ((DimmQRDR & (UINT16) 1 << DimmID) ? 3: 1) << ChipSel; - } - - if ((DCTPtr->Timings.DctDimmValid & ((UINT16)1 << DimmID)) != 0) { - MemTGetDimmSpdBuffer3 (TechPtr, &SpdBufferPtr, DimmID); - - // Get the basic data - Rows = (SpdBufferPtr[SPD_ROW_SZ] >> 3) & 0x7; - Cols = SpdBufferPtr[SPD_COL_SZ] & 0x7; - Banks = (SpdBufferPtr[SPD_L_BANKS] >> 4) & 0x7; - Ranks = ((SpdBufferPtr[SPD_RANKS] >> 3) & 0x07) + 1; - if (Ranks == 5) { - Ranks = 8; - } - - // - // Configure the bank encoding - // Use a 6-bit key into a lookup table. - // Key (index) = RRRBCC, where CC is the number of Columns minus 9, - // RRR is the number of Rows minus 12, and B is the number of banks - // minus 3. - // - Value8 = Cols; - Value8 |= (Banks == 1) ? 4 : 0; - Value8 |= Rows << 3; - - if (MemTCheckBankAddr3 (Value8, &i)) { - BankAddrReg |= ((UINT32)i << (ChipSel << 1)); - - // Mask value=(2pow(rows+cols+banks+3)-1)>>8, - // or 2pow(rows+cols+banks-5)-1 - // - Value8 = (Rows + 12) + (Cols + 9) + (Banks + 3) + 3 - 8; - if (MCTPtr->Status[Sb128bitmode]) { - Value8++; - } - - DCTPtr->Timings.CsPresent |= (UINT16)1 << ChipSel; - - if (Ranks >= 2) { - DCTPtr->Timings.CsPresent |= (UINT16)1 << (ChipSel + 1); - } - // - // Determine LRDIMM Rank Multiplication - // - if (TechPtr->TechnologySpecificHook[LrdimmRankMultiplication] (TechPtr, &DimmID)) { - // - // Increase the CS Size by the rank multiplication factor - // - Value8 += ((NBPtr->ChannelPtr->LrDimmRankMult[DimmID]) >> 1); - } - - CsMask = ((UINT32)1 << Value8) - 1; - // Update the DRAM CS Mask for this chipselect - NBPtr->SetBitField (NBPtr, BFCSMask0Reg + (ChipSel >> 1), (CsMask & NBPtr->CsRegMsk)); - } else { - // Dimm is not supported, as no address mapping is found. - DCTPtr->Timings.CsPresent |= (UINT16)1 << ChipSel; - DCTPtr->Timings.CsTestFail |= (UINT16)1 << ChipSel; - if (Ranks >= 2) { - DCTPtr->Timings.CsPresent |= (UINT16)1 << (ChipSel + 1); - DCTPtr->Timings.CsTestFail |= (UINT16)1 << (ChipSel + 1); - } - PutEventLog (AGESA_ERROR, MEM_ERROR_NO_ADDRESS_MAPPING, NBPtr->Node, NBPtr->Dct, NBPtr->Channel, DimmID, &NBPtr->MemPtr->StdHeader); - SetMemError (AGESA_ERROR, MCTPtr); - } - } - } - // For ranks that need to be excluded, the loading of this rank should be considered - // in timing, so need to set CsPresent before setting CsTestFail - if ((CSSpdCSE != 0) || (CSExclude != 0)) { - NBPtr->MemPtr->ErrorHandling (MCTPtr, NBPtr->Dct, (CSSpdCSE | CSExclude), &NBPtr->MemPtr->StdHeader); - } - - // If there are no chip selects, we have an error situation. - if (DCTPtr->Timings.CsPresent == 0) { - PutEventLog (AGESA_ERROR, MEM_ERROR_NO_CHIPSELECT, NBPtr->Node, NBPtr->Dct, NBPtr->Channel, 0, &NBPtr->MemPtr->StdHeader); - SetMemError (AGESA_ERROR, MCTPtr); - } - - NBPtr->SetBitField (NBPtr, BFDramBankAddrReg, BankAddrReg); - - return (BOOLEAN) (MCTPtr->ErrCode < AGESA_FATAL); -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * This function returns the low bit that will be swapped to enable CS interleaving - * - * @param[in] BankEnc - AddrMap Bank encoding from F2x80 - * @param[in] *LowBit - pointer to low bit - * @param[in] *HiBit - pointer hight bit - * - */ - -VOID -MemTGetCSIntLvAddr3 ( - IN UINT8 BankEnc, - OUT UINT8 *LowBit, - OUT UINT8 *HiBit - ) -{ - CONST UINT8 ArrCodesLo[] = {0, 8, 8, 0, 0, 8, 9, 8, 9, 9, 8, 9}; - CONST UINT8 ArrCodesHi[] = {0, 20, 21, 0, 0, 22, 22, 23, 23, 24, 24, 25}; - ASSERT (BankEnc < GET_SIZE_OF (ArrCodesLo)); - ASSERT (BankEnc < GET_SIZE_OF (ArrCodesHi)); - // return ArrCodes[BankEnc]; - *LowBit = ArrCodesLo[BankEnc]; - *HiBit = ArrCodesHi[BankEnc]; -} - -/*---------------------------------------------------------------------------- - * LOCAL FUNCTIONS - * - *---------------------------------------------------------------------------- - */ - -/* -----------------------------------------------------------------------------*/ -/** - * - * This function determines if the checksum is correct - * - * @param[in] *SPDPtr - Pointer to SPD data - * - * @return TRUE - CRC check passes - * @return FALSE - CRC check fails - */ - -BOOLEAN -STATIC -MemTCRCCheck3 ( - IN OUT UINT8 *SPDPtr - ) -{ - UINT16 Crc; - INT16 i; - INT16 j; - INT16 Count; - - if (SPDPtr[SPD_TYPE] == JED_DDR3SDRAM) { - Count = (SPDPtr[SPD_BYTE_USED] & 0x80) ? 117 : 126; - Crc = 0; - for (j = 0; j < Count; j++) { - Crc = Crc ^ ((UINT16)SPDPtr[j] << 8); - for (i = 0; i < 8; i++) { - if (Crc & 0x8000) { - Crc = (Crc << 1) ^ 0x1021; - } else { - Crc = (Crc << 1); - } - } - } - if (*(UINT16 *) (SPDPtr + 126) == Crc) { - return TRUE; - } - } - - return FALSE; -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * This function returns the CAS latency of the current frequency (DCTPtr->Timings.Speed). - * - * @param[in,out] *TechPtr - Pointer to the MEM_TECH_BLOCK - * - * @return CAS Latency - */ - -UINT8 -STATIC -MemTSPDGetTCL3 ( - IN OUT MEM_TECH_BLOCK *TechPtr - ) -{ - UINT8 *SpdBufferPtr = NULL; - UINT8 CLdesired; - UINT8 CLactual; - UINT8 Dimm; - UINT8 Channel; - UINT16 CASLat; - UINT16 Mask16; - INT32 MTB_ps; - INT32 FTB_ps; - INT32 TAAmin_ps; - INT32 TCKproposed_ps; - INT32 Value32; - BOOLEAN CltFail; - MEM_NB_BLOCK *NBPtr; - DCT_STRUCT *DCTPtr; - CH_DEF_STRUCT *ChannelPtr; - - NBPtr = TechPtr->NBPtr; - DCTPtr = NBPtr->DCTPtr; - - CASLat = 0xFFFF; - TAAmin_ps = 0; - CltFail = FALSE; - - for (Channel = 0; Channel < NBPtr->ChannelCount; Channel++) { - NBPtr->SwitchChannel (NBPtr, Channel); - ChannelPtr = NBPtr->ChannelPtr; - for (Dimm = 0; Dimm < MAX_DIMMS_PER_CHANNEL; Dimm++) { - if ((ChannelPtr->ChDimmValid & ((UINT8)1 << Dimm)) != 0) { - MemTGetDimmSpdBuffer3 (TechPtr, &SpdBufferPtr, Dimm); - - // Step 1: Determine the common set of supported CAS Latency - // values for all modules on the memory Channel using the CAS - // Latencies Supported in SPD bytes 14 and 15. - // - CASLat &= ((UINT16)SpdBufferPtr[SPD_CASHI] << 8) | SpdBufferPtr[SPD_CASLO]; - - // Step 2: Determine tAAmin(all) which is the largest tAAmin - // value for all modules on the memory Channel (SPD byte 16). - // - MTB_ps = ((INT32) SpdBufferPtr[SPD_DIVIDENT] * 1000) / SpdBufferPtr[SPD_DIVISOR]; - FTB_ps = (SpdBufferPtr[SPD_FTB] >> 4) / (SpdBufferPtr[SPD_FTB] & 0xF); - Value32 = (MTB_ps * SpdBufferPtr[SPD_TAA]) + (FTB_ps * (INT8) SpdBufferPtr[SPD_TAA_FTB]) ; - if (TAAmin_ps < Value32) { - TAAmin_ps = Value32; - } - - // Step 3: Determine tCKmin(all) which is the largest tCKmin - // value for all modules on the memory Channel (SPD byte 12). - // * This step has been done in SPDGetTargetSpeed - } - } - } - - TCKproposed_ps = 1000500 / DCTPtr->Timings.Speed; - - // Step 4: For a proposed tCK value (tCKproposed) between tCKmin(all) and tCKmax, - // determine the desired CAS Latency. If tCKproposed is not a standard JEDEC - // value (2.5, 1.875, 1.5, or 1.25 ns) then tCKproposed must be adjusted to the - // next lower standard tCK value for calculating CLdesired. - // CLdesired = ceiling ( tAAmin(all) / tCKproposed ) - // where tAAmin is defined in Byte 16. The ceiling function requires that the - // quotient be rounded up always. - // - CLdesired = (UINT8) ((TAAmin_ps + TCKproposed_ps - 1) / TCKproposed_ps); - - // Step 5: Choose an actual CAS Latency (CLactual) that is greater than or equal - // to CLdesired and is supported by all modules on the memory Channel as - // determined in step 1. If no such value exists, choose a higher tCKproposed - // value and repeat steps 4 and 5 until a solution is found. - // - CLactual = 4; - for (Mask16 = 1; Mask16 < 0x8000; Mask16 <<= 1) { - if (CASLat & Mask16) { - if (CLdesired <= CLactual) { - break; - } - } - CLactual++; - } - if (Mask16 == 0x8000) { - CltFail = TRUE; - } - - // Step 6: Once the calculation of CLactual is completed, the BIOS must also - // verify that this CAS Latency value does not exceed tAAmax, which is 20 ns - // for all DDR3 speed grades, by multiplying CLactual times tCKproposed. If - // not, choose a lower CL value and repeat steps 5 and 6 until a solution is found. - // - if ((TCKproposed_ps * CLactual) > 20000) { - CltFail = TRUE; - } - - if (!CltFail) { - DCTPtr->Timings.CasL = CLactual; - } else { - // Fail to find supported Tcl, use 6 clocks since it is required for all DDR3 speed bin. - DCTPtr->Timings.CasL = 6; - } - - return DCTPtr->Timings.CasL; -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * This function returns the encoded value of bank address. - * - * @param[in] Encode - RRRBCC, where CC is the number of Columns minus 9, - * RRR is the number of Rows minus 12, and B is the number of banks - * minus 3. - * @param[out] *Index - index in bank address table - * @return TRUE - encoded value is found. - * FALSE - encoded value is not found. - */ - -BOOLEAN -STATIC -MemTCheckBankAddr3 ( - IN UINT8 Encode, - OUT UINT8 *Index - ) -{ - UINT8 i; - CONST UINT8 TabBankAddr[] = { - 0x3F, 0x01, 0x09, 0x3F, 0x3F, 0x11, - 0x0A, 0x19, 0x12, 0x1A, 0x21, 0x22 - }; - - for (i = 0; i < GET_SIZE_OF (TabBankAddr); i++) { - if (Encode == TabBankAddr[i]) { - *Index = i; - return TRUE; - } - } - return FALSE; -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * This function returns a pointer to the SPD Buffer of a specific dimm on - * the current channel. - * - * @param[in,out] *TechPtr - Pointer to the MEM_TECH_BLOCK - * @param[in,out] **SpdBuffer - Pointer to a pointer to a UINT8 Buffer - * @param[in] Dimm - Dimm number - * - * - * @return BOOLEAN - Value of DimmPresent - * TRUE = Dimm is present, pointer is valid - * FALSE = Dimm is not present, pointer has not been modified. - */ - -BOOLEAN -MemTGetDimmSpdBuffer3 ( - IN OUT MEM_TECH_BLOCK *TechPtr, - IN OUT UINT8 **SpdBuffer, - IN UINT8 Dimm - ) -{ - CH_DEF_STRUCT *ChannelPtr; - SPD_DEF_STRUCT *SPDPtr; - BOOLEAN DimmPresent; - - DimmPresent = FALSE; - ChannelPtr = TechPtr->NBPtr->ChannelPtr; - ASSERT (Dimm < (sizeof (ChannelPtr->DimmSpdPtr) / sizeof (ChannelPtr->DimmSpdPtr[0]))) - SPDPtr = ChannelPtr->DimmSpdPtr[Dimm]; - - - if (SPDPtr != NULL) { - DimmPresent = SPDPtr->DimmPresent; - if (DimmPresent) { - *SpdBuffer = SPDPtr->Data; - } - } - return DimmPresent; -} - diff --git a/src/vendorcode/amd/agesa/f12/Proc/Mem/Tech/DDR3/mtspd3.h b/src/vendorcode/amd/agesa/f12/Proc/Mem/Tech/DDR3/mtspd3.h deleted file mode 100644 index aaa6285c76..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/Mem/Tech/DDR3/mtspd3.h +++ /dev/null @@ -1,176 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * mtspd3.h - * - * Technology SPD support for DDR3 - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: (Mem/Tech/DDR3) - * @e \$Revision: 49133 $ @e \$Date: 2011-03-17 16:54:42 +0800 (Thu, 17 Mar 2011) $ - * - **/ -/***************************************************************************** - * - * Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * *************************************************************************** - * - */ - -#ifndef _MTSPD3_H_ -#define _MTSPD3_H_ - -/*---------------------------------------------------------------------------- - * Mixed (DEFINITIONS AND MACROS / TYPEDEFS, STRUCTURES, ENUMS) - * - *---------------------------------------------------------------------------- - */ - -/*----------------------------------------------------------------------------- - * DEFINITIONS AND MACROS - * - *----------------------------------------------------------------------------- - */ - -/*=============================================================================== - * Jedec DDR III - *=============================================================================== - */ -#define SPD_BYTE_USED 0 -#define SPD_TYPE 2 /* SPD byte read location */ -#define JED_DDR_SDRAM 7 /* Jedec defined bit field */ -#define JED_DDR2_SDRAM 8 /* Jedec defined bit field */ -#define JED_DDR3SDRAM 0xB /* Jedec defined bit field */ - -#define SPD_DIMM_TYPE 3 -#define SPD_ATTRIB 21 -#define JED_DIF_CK_MSK 0x20 /* Differential Clock Input */ -#define JED_RDIMM 1 -#define JED_MINIRDIMM 5 -#define JED_UDIMM 2 -#define JED_SODIMM 3 -#define JED_LRDIMM 0xB -#define JED_UNDEFINED 0 /* Undefined value */ - -#define SPD_L_BANKS 4 /* [7:4] number of [logical] banks on each device */ -#define SPD_DENSITY 4 /* bit 3:0 */ -#define SPD_ROW_SZ 5 /* bit 5:3 */ -#define SPD_COL_SZ 5 /* bit 2:0 */ -#define SPD_RANKS 7 /* bit 5:3 */ -#define SPD_DEV_WIDTH 7 /* bit 2:0 */ -#define SPD_ECCBITS 8 /* bit 4:3 */ -#define JED_ECC 8 -#define SPD_RAWCARD 62 /* bit 2:0 */ -#define SPD_ADDRMAP 63 /* bit 0 */ - -#define SPD_CTLWRD03 70 /* bit 7:4 */ -#define SPD_CTLWRD04 71 /* bit 3:0 */ -#define SPD_CTLWRD05 71 /* bit 7:4 */ - -#define SPD_FTB 9 - -#define SPD_DIVIDENT 10 -#define SPD_DIVISOR 11 - -#define SPD_TCK 12 -#define SPD_CASLO 14 -#define SPD_CASHI 15 -#define SPD_TAA 16 - -#define SPD_TRP 20 -#define SPD_TRRD 19 -#define SPD_TRCD 18 -#define SPD_TRAS 22 -#define SPD_TWR 17 -#define SPD_TWTR 26 -#define SPD_TRTP 27 -#define SPD_TRC 23 -#define SPD_UPPER_TRC 21 /* bit 7:4 */ -#define SPD_UPPER_TRAS 21 /* bit 3:0 */ -#define SPD_TFAW 29 -#define SPD_UPPER_TFAW 28 /* bit 3:0 */ - -#define SPD_TCK_FTB 34 -#define SPD_TAA_FTB 35 -#define SPD_TRCD_FTB 36 -#define SPD_TRP_FTB 37 -#define SPD_TRC_FTB 38 - -/*----------------------------- - * Jedec DDR II related equates - *----------------------------- - */ - -#define CL_DEF 4 /* Default value for failsafe operation. 4=CL 6.0 T */ -#define T_DEF 4 /* Default value for failsafe operation. 4=2.5ns (cycle time) */ - -#define BIAS_TRTP_T 4 -#define BIAS_TRCD_T 5 -#define BIAS_TRAS_T 15 -#define BIAS_TRC_T 11 -#define BIAS_TRRD_T 4 -#define BIAS_TWR_T 4 -#define BIAS_TRP_T 5 -#define BIAS_TWTR_T 4 -#define BIAS_TFAW_T 14 - -#define MIN_TRTP_T 4 -#define MAX_TRTP_T 7 -#define MIN_TRCD_T 5 -#define MAX_TRCD_T 12 -#define MIN_TRAS_T 15 -#define MAX_TRAS_T 30 -#define MIN_TRC_T 11 -#define MAX_TRC_T 42 -#define MIN_TRRD_T 4 -#define MAX_TRRD_T 7 -#define MIN_TWR_T 5 -#define MAX_TWR_T 12 -#define MIN_TRP_T 5 -#define MAX_TRP_T 12 -#define MIN_TWTR_T 4 -#define MAX_TWTR_T 7 -#define MIN_TFAW_T 16 -#define MAX_TFAW_T 32 - -/*---------------------------------------------------------------------------- - * TYPEDEFS, STRUCTURES, ENUMS - * - *---------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------- - * FUNCTIONS PROTOTYPE - * - *---------------------------------------------------------------------------- - */ - - -#endif /* _MTSPD3_H_ */ - - diff --git a/src/vendorcode/amd/agesa/f12/Proc/Mem/Tech/DDR3/mttecc3.c b/src/vendorcode/amd/agesa/f12/Proc/Mem/Tech/DDR3/mttecc3.c deleted file mode 100644 index 0313763bd4..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/Mem/Tech/DDR3/mttecc3.c +++ /dev/null @@ -1,164 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * mttecc3.c - * - * Technology ECC byte support for registered DDR3 - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: (Mem/Tech/DDR3) - * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $ - * - **/ -/***************************************************************************** -* -* Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* *************************************************************************** -* -*/ - -/* - *---------------------------------------------------------------------------- - * MODULES USED - * - *---------------------------------------------------------------------------- - */ - - -#include "AGESA.h" -#include "mm.h" -#include "mn.h" -#include "mu.h" -#include "mt.h" -#include "Filecode.h" -CODE_GROUP (G1_PEICC) -RDATA_GROUP (G1_PEICC) - -#define FILECODE PROC_MEM_TECH_DDR3_MTTECC3_FILECODE -/*---------------------------------------------------------------------------- - * DEFINITIONS AND MACROS - * - *---------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------- - * TYPEDEFS AND STRUCTURES - * - *---------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------- - * PROTOTYPES OF LOCAL FUNCTIONS - * - *---------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------- - * EXPORTED FUNCTIONS - * - *---------------------------------------------------------------------------- - */ - -/* -----------------------------------------------------------------------------*/ -/** - * - * This function sets the DQS ECC timings for registered DDR3 - * - * @param[in,out] *TechPtr - Pointer to the MEM_TECH_BLOCK - * - * @return TRUE - No fatal error occurs. - * @return FALSE - Fatal error occurs. - */ - -BOOLEAN -MemTSetDQSEccTmgsRDdr3 ( - IN OUT MEM_TECH_BLOCK *TechPtr - ) -{ - UINT8 Dct; - UINT8 Dimm; - UINT8 i; - UINT8 *WrDqsDly; - UINT16 *RcvEnDly; - UINT8 *RdDqsDly; - UINT8 *WrDatDly; - UINT8 EccByte; - INT16 TempValue; - - MEM_NB_BLOCK *NBPtr; - CH_DEF_STRUCT *ChannelPtr; - - EccByte = TechPtr->MaxByteLanes (); - NBPtr = TechPtr->NBPtr; - - if (NBPtr->MCTPtr->NodeMemSize) { - for (Dct = 0; Dct < NBPtr->DctCount; Dct++) { - NBPtr->SwitchDCT (NBPtr, Dct); - if (NBPtr->DCTPtr->Timings.DctMemSize != 0) { - ChannelPtr = NBPtr->ChannelPtr; - for (Dimm = 0; Dimm < MAX_DIMMS_PER_CHANNEL; Dimm++) { - if (NBPtr->DCTPtr->Timings.CsEnabled & ((UINT16)3 << (Dimm * 2))) { - i = Dimm * TechPtr->DlyTableWidth (); - WrDqsDly = &ChannelPtr->WrDqsDlys[i]; - RcvEnDly = &ChannelPtr->RcvEnDlys[i]; - RdDqsDly = &ChannelPtr->RdDqsDlys[i]; - WrDatDly = &ChannelPtr->WrDatDlys[i]; - // Receiver DQS Enable: - // Receiver DQS enable for ECC bytelane = Receiver DQS enable for bytelane 3 - - // [write DQS for bytelane 3 - write DQS for ECC] - - TempValue = (INT16) RcvEnDly[3] - (INT16) (WrDqsDly[3] - WrDqsDly[EccByte]); - if (TempValue < 0) { - TempValue = 0; - } - RcvEnDly[EccByte] = (UINT16) TempValue; - - // Read DQS: - // Read DQS for ECC bytelane = read DQS of byte lane 3 - // - RdDqsDly[EccByte] = RdDqsDly[3]; - - // Write Data: - // Write Data for ECC bytelane = Write DQS for ECC + - // [write data for bytelane 3 - Write DQS for bytelane 3] - TempValue = (INT16) (WrDqsDly[EccByte] + (INT8) (WrDatDly[3] - WrDqsDly[3])); - if (TempValue < 0) { - TempValue = 0; - } - WrDatDly[EccByte] = (UINT8) TempValue; - - NBPtr->SetTrainDly (NBPtr, AccessRcvEnDly, DIMM_BYTE_ACCESS (Dimm, EccByte), RcvEnDly[EccByte]); - NBPtr->SetTrainDly (NBPtr, AccessRdDqsDly, DIMM_BYTE_ACCESS (Dimm, EccByte), RdDqsDly[EccByte]); - NBPtr->SetTrainDly (NBPtr, AccessWrDatDly, DIMM_BYTE_ACCESS (Dimm, EccByte), WrDatDly[EccByte]); - } - } - } - } - } - return (BOOLEAN) (NBPtr->MCTPtr->ErrCode < AGESA_FATAL); -} \ No newline at end of file diff --git a/src/vendorcode/amd/agesa/f12/Proc/Mem/Tech/DDR3/mttwl3.c b/src/vendorcode/amd/agesa/f12/Proc/Mem/Tech/DDR3/mttwl3.c deleted file mode 100644 index da42c638be..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/Mem/Tech/DDR3/mttwl3.c +++ /dev/null @@ -1,700 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * mttwl3.c - * - * Technology Phy assisted write levelization for DDR3 - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: (Mem/Tech/DDR3) - * @e \$Revision: 49104 $ @e \$Date: 2011-03-17 06:54:25 +0800 (Thu, 17 Mar 2011) $ - * - **/ -/***************************************************************************** -* -* Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* *************************************************************************** -* -*/ - -/* - *---------------------------------------------------------------------------- - * MODULES USED - * - *---------------------------------------------------------------------------- - */ - - - -#include "AGESA.h" -#include "Ids.h" -#include "mm.h" -#include "mn.h" -#include "mu.h" -#include "mt.h" -#include "mtsdi3.h" -#include "merrhdl.h" -#include "OptionMemory.h" -#include "PlatformMemoryConfiguration.h" -#include "GeneralServices.h" -#include "Filecode.h" -#include "mtlrdimm3.h" -CODE_GROUP (G1_PEICC) -RDATA_GROUP (G1_PEICC) - -#define FILECODE PROC_MEM_TECH_DDR3_MTTWL3_FILECODE -/*---------------------------------------------------------------------------- - * DEFINITIONS AND MACROS - * - *---------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------- - * TYPEDEFS AND STRUCTURES - * - *---------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------- - * PROTOTYPES OF LOCAL FUNCTIONS - * - *---------------------------------------------------------------------------- - */ - -BOOLEAN -STATIC -MemTWriteLevelizationHw3 ( - IN OUT MEM_TECH_BLOCK *TechPtr, - IN UINT8 Pass - ); - -VOID -STATIC -MemTWLPerDimmHw3 ( - IN OUT MEM_TECH_BLOCK *TechPtr, - IN UINT8 Dimm, - IN UINT8 Pass - ); - -VOID -STATIC -MemTPrepareDIMMs3 ( - IN OUT MEM_TECH_BLOCK *TechPtr, - IN UINT8 TargetDIMM, - IN BOOLEAN Wl - ); - -VOID -STATIC -MemTProcConfig3 ( - IN OUT MEM_TECH_BLOCK *TechPtr, - IN UINT8 Dimm, - IN UINT8 Pass - ); - -VOID -STATIC -MemTBeginWLTrain3 ( - IN OUT MEM_TECH_BLOCK *TechPtr, - IN UINT8 Dimm - ); - -/*---------------------------------------------------------------------------- - * EXPORTED FUNCTIONS - * - *---------------------------------------------------------------------------- - */ - - -/* -----------------------------------------------------------------------------*/ -/** - * - * This function executes first pass of Phy assisted write levelization - * for a specific node (DDR800). - * - * @param[in,out] *TechPtr - Pointer to the MEM_TECH_BLOCK - * - * @return TRUE - No fatal error occurs. - * @return FALSE - Fatal error occurs. - */ - -BOOLEAN -MemTWriteLevelizationHw3Pass1 ( - IN OUT MEM_TECH_BLOCK *TechPtr - ) -{ - return MemTWriteLevelizationHw3 (TechPtr, 1); -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * This function executes second pass of Phy assisted write levelization - * for a specific node (DDR1066 and above). - * - * @param[in,out] *TechPtr - Pointer to the MEM_TECH_BLOCK - * - * @return TRUE - No fatal error occurs. - * @return FALSE - Fatal error occurs. - */ - -BOOLEAN -MemTWriteLevelizationHw3Pass2 ( - IN OUT MEM_TECH_BLOCK *TechPtr - ) -{ - // If current speed is higher than start-up speed, do second pass of WL - if (TechPtr->NBPtr->DCTPtr->Timings.Speed > TechPtr->NBPtr->StartupSpeed) { - return MemTWriteLevelizationHw3 (TechPtr, 2); - } - return TRUE; -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * This function prepares for Phy assisted training. - * - * @param[in,out] *TechPtr - Pointer to the MEM_TECH_BLOCK - * - * @return TRUE - No fatal error occurs. - * @return FALSE - Fatal error occurs. - */ - -BOOLEAN -MemTPreparePhyAssistedTraining ( - IN OUT MEM_TECH_BLOCK *TechPtr - ) -{ - // Disable auto refresh by configuring F2x[1, 0]8C[DisAutoRefresh] = 1. - TechPtr->NBPtr->BrdcstSet (TechPtr->NBPtr, BFDisAutoRefresh, 1); - // Disable ZQ calibration short command by configuring F2x[1, 0]94[ZqcsInterval] = 00b. - TechPtr->NBPtr->BrdcstSet (TechPtr->NBPtr, BFZqcsInterval, 0); - return (BOOLEAN) (TechPtr->NBPtr->MCTPtr->ErrCode < AGESA_FATAL); -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * This function revert to normal settings when exiting from Phy assisted training. - * - * @param[in,out] *TechPtr - Pointer to the MEM_TECH_BLOCK - * - * @return TRUE - No fatal error occurs. - * @return FALSE - Fatal error occurs. - */ - -BOOLEAN -MemTExitPhyAssistedTraining ( - IN OUT MEM_TECH_BLOCK *TechPtr - ) -{ - MEM_NB_BLOCK *NBPtr; - NBPtr = TechPtr->NBPtr; - - // 13.Program F2x[1, 0]8C[DisAutoRefresh] = 0. - NBPtr->BrdcstSet (NBPtr, BFDisAutoRefresh, 0); - // 14.Program F2x[1, 0]94[ZqcsInterval] to the proper interval for the current memory configuration. - NBPtr->BrdcstSet (NBPtr, BFZqcsInterval, 2); - NBPtr->FamilySpecificHook[ExitPhyAssistedTraining] (NBPtr, NBPtr); - - return (BOOLEAN) (NBPtr->MCTPtr->ErrCode < AGESA_FATAL); -} - -/*---------------------------------------------------------------------------- - * LOCAL FUNCTIONS - * - *---------------------------------------------------------------------------- - */ - -/* -----------------------------------------------------------------------------*/ -/** - * - * This function executed hardware based write levelization for a specific die - * - * @param[in,out] *TechPtr - Pointer to the MEM_TECH_BLOCK - * @param[in] Pass - Pass number (1 (400Mhz) or 2 (>400Mhz)) - * - * @pre Auto refresh and ZQCL must be disabled - * - * @return TRUE - No fatal error occurs. - * @return FALSE - Fatal error occurs. - */ - -BOOLEAN -STATIC -MemTWriteLevelizationHw3 ( - IN OUT MEM_TECH_BLOCK *TechPtr, - IN UINT8 Pass - ) -{ - MEM_NB_BLOCK *NBPtr; - DCT_STRUCT *DCTPtr; - UINT8 Dct; - UINT8 Dimm; - - NBPtr = TechPtr->NBPtr; - - IDS_HDT_CONSOLE (MEM_STATUS, "\nStart write leveling\n"); - AGESA_TESTPOINT (TpProcMemWriteLevelizationTraining, &(NBPtr->MemPtr->StdHeader)); - // Begin DQS Write timing training - for (Dct = 0; Dct < NBPtr->DctCount; Dct++) { - NBPtr->SwitchDCT (NBPtr, Dct); - IDS_HDT_CONSOLE (MEM_STATUS, "\tDct %d\n", Dct); - DCTPtr = NBPtr->DCTPtr; - - TechPtr->WLCriticalDelay = 0x00; - - //training for each Dimm - for (Dimm = 0; Dimm < MAX_DIMMS_PER_CHANNEL; Dimm++) { - if ((DCTPtr->Timings.CsEnabled & ((UINT16)3 << (Dimm << 1))) != 0) { - if (!(NBPtr->MCTPtr->Status[SbLrdimms]) || ((NBPtr->ChannelPtr->LrDimmPresent & ((UINT8) 1 << Dimm)) != 0)) { - IDS_HDT_CONSOLE (MEM_STATUS, "\t\tCS %d\n", Dimm << 1); - MemTWLPerDimmHw3 (TechPtr, Dimm, Pass); - } - } - } - - NBPtr->FamilySpecificHook[CalcWrDqDqsEarly] (NBPtr, NULL); - } - IDS_HDT_CONSOLE (MEM_FLOW, "End write leveling\n\n"); - return (BOOLEAN) (NBPtr->MCTPtr->ErrCode < AGESA_FATAL); -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * This function initializes per DIMM write levelization - * - * @param[in,out] *TechPtr - Pointer to the MEM_TECH_BLOCK - * @param[in] Dimm - DIMM to be trained - * @param[in] Pass - Pass number (1 (400Mhz) or 2 (>400Mhz)) - * - */ - -VOID -STATIC -MemTWLPerDimmHw3 ( - IN OUT MEM_TECH_BLOCK *TechPtr, - IN UINT8 Dimm, - IN UINT8 Pass - ) -{ - MEM_DATA_STRUCT *MemPtr; - MEM_NB_BLOCK *NBPtr; - - NBPtr = TechPtr->NBPtr; - MemPtr = NBPtr->MemPtr; - - ASSERT (Dimm < MAX_DIMMS_PER_CHANNEL); - - // 1. A. Specify the target Dimm that is to be trained by programming - // F2x[1, 0]9C_x08[TrDimmSel]. - NBPtr->SetBitField (NBPtr, BFTrDimmSel, Dimm); - - TechPtr->TargetDIMM = Dimm; - NBPtr->FamilySpecificHook[InitPerNibbleTrn] (NBPtr, NULL); - for (TechPtr->TrnNibble = NIBBLE_0; TechPtr->TrnNibble <= (NBPtr->FamilySpecificHook[TrainWlPerNibble] (NBPtr, &Dimm)? NIBBLE_0 : NIBBLE_1); TechPtr->TrnNibble++) { - // 2. Prepare the DIMMs for write levelization using DDR3-defined - // MR commands. - MemTPrepareDIMMs3 (TechPtr, Dimm, TRUE); - - // 3. After the DIMMs are configured, BIOS waits 40 MEMCLKs to - // satisfy DDR3-defined internal DRAM timing. - NBPtr->WaitXMemClks (NBPtr, 40); - - // 4. Configure the processor's DDR phy for write levelization training: - MemTProcConfig3 (TechPtr, Dimm, Pass); - - // 5. Begin write levelization training - MemTBeginWLTrain3 (TechPtr, Dimm); - } - // 7. Program the target Dimm back to normal operation - MemTPrepareDIMMs3 (TechPtr, Dimm, FALSE); -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * This function prepares the DIMMS for Write Levelization - * - * @param[in,out] *TechPtr - Pointer to the MEM_TECH_BLOCK - * @param[in] TargetDIMM - DIMM to be trained - * @param[in] Wl - Indicates if WL mode should be enabled - * - */ - -VOID -STATIC -MemTPrepareDIMMs3 ( - IN OUT MEM_TECH_BLOCK *TechPtr, - IN UINT8 TargetDIMM, - IN BOOLEAN Wl - ) -{ - MEM_NB_BLOCK *NBPtr; - UINT8 ChipSel; - - NBPtr = TechPtr->NBPtr; - - AGESA_TESTPOINT (TpProcMemWlPrepDimms, &(NBPtr->MemPtr->StdHeader)); - ASSERT (TargetDIMM < MAX_DIMMS_PER_CHANNEL); - TechPtr->TargetDIMM = TargetDIMM; - if (!(TechPtr->TechnologySpecificHook[WlTrainingPrepareLrdimm] (TechPtr, &Wl))) { - for (ChipSel = 0; ChipSel < MAX_CS_PER_CHANNEL; ChipSel++) { - if ((NBPtr->DCTPtr->Timings.CsPresent & ((UINT16)1 << ChipSel)) != 0) { - if (Wl) { - // Program WrLvOdt - NBPtr->SetBitField (NBPtr, BFWrLvOdt, NBPtr->ChannelPtr->PhyWLODT[ChipSel >> 1]); - } - NBPtr->SetBitField (NBPtr, BFMrsChipSel, ChipSel); - // Set MR1 to F2x7C[MrsAddress], F2x7C[MrsBank]=1 - MemTEMRS13 (TechPtr, Wl, TargetDIMM); - NBPtr->SendMrsCmd (NBPtr); - // Set MR2 to F2x7C[MrsAddress], F2x7C[MrsBank]=1 - MemTEMRS23 (TechPtr); - // Send command - NBPtr->SendMrsCmd (NBPtr); - } - } - } -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * This function programs seed values for Write Levelization - * - * @param[in,out] *TechPtr - Pointer to the MEM_TECH_BLOCK - * @param[in] Dimm - DIMM to be trained - * @param[in] Pass - Pass for WL training (1 - 400Mhz or 2 - >400Mhz) - * - */ - -VOID -STATIC -MemTProcConfig3 ( - IN OUT MEM_TECH_BLOCK *TechPtr, - IN UINT8 Dimm, - IN UINT8 Pass - ) -{ - DIE_STRUCT *MCTPtr; - CH_DEF_STRUCT *ChannelPtr; - MEM_NB_BLOCK *NBPtr; - UINT16 WrDqsDly; - // Memclk Delay incurred by register. - UINT8 MemClkRegDly; - UINT8 ByteLane; - UINT8 DefaultSeed; - UINT8 CurrentSeed; - UINT8 *Seed; - UINT8 RCW2; - UINT16 Speed; - INT16 WrDqsBias; - - NBPtr = TechPtr->NBPtr; - MCTPtr = NBPtr->MCTPtr; - ChannelPtr = TechPtr->NBPtr->ChannelPtr; - - AGESA_TESTPOINT (TpProcMemWlConfigDimms, &(NBPtr->MemPtr->StdHeader)); - RCW2 = ChannelPtr->CtrlWrd02[Dimm]; - Speed = TechPtr->NBPtr->DCTPtr->Timings.Speed; - - IDS_HDT_CONSOLE (MEM_FLOW, "\n\t\t\t Byte: 00 01 02 03 04 05 06 07 ECC\n"); - IDS_HDT_CONSOLE (MEM_FLOW, "\t\t\tSeeds: "); - // Program an initialization Value to registers F2x[1, 0]9C_x[51:50] and F2x[1, 0]9C_x52 to set - // the gross and fine delay for all the byte lane fields. If the target frequency is different than 400MHz, - // BIOS must execute two training passes for each Dimm. For pass 1 at a 400MHz MEMCLK frequency, - // use an initial total delay value. - if (Pass == 1) { - // - // Get the default value of seed - // - if (MCTPtr->Status[SbRegistered]) { - // - // RDIMM - // - if (Speed == DDR667_FREQUENCY) { - DefaultSeed = ((RCW2 & BIT0) == 0) ? 0x3B : 0x4B; - } else { - DefaultSeed = ((RCW2 & BIT0) == 0) ? 0x41 : 0x51; - } - } else if (ChannelPtr->SODimmPresent != 0) { - // - // SODIMMM - // - DefaultSeed = 0x12; - } else if (MCTPtr->Status[SbLrdimms]) { - // - // LRDIMM - // - DefaultSeed = 0x0; - } else { - // - // UDIMMM - // - DefaultSeed = 0x1A; - } - - NBPtr->FamilySpecificHook[OverrideWLSeed] (NBPtr, &DefaultSeed); - ASSERT (Speed >= DDR667_FREQUENCY); - - // Get platform override seed - Seed = (UINT8 *) FindPSOverrideEntry (NBPtr->RefPtr->PlatformMemoryConfiguration, PSO_WL_SEED, MCTPtr->SocketId, ChannelPtr->ChannelID); - - for (ByteLane = 0; ByteLane < TechPtr->DlyTableWidth (); ByteLane++) { - // This includes ECC as byte 8 - CurrentSeed = ((Seed != NULL) ? Seed[ByteLane] : DefaultSeed); - ChannelPtr->WrDqsDlys[Dimm * TechPtr->DlyTableWidth () + ByteLane] = CurrentSeed; - - if (NBPtr->IsSupported[WLSeedAdjust]) { - if ((CurrentSeed & 0x20) != 0) { - // If (SeedGross is odd) then SeedPreGross = 1 - CurrentSeed = (CurrentSeed & 0x1F) | 0x20; - } else { - // If (SeedGross is even) then SeedPreGross = 2 - CurrentSeed = (CurrentSeed & 0x1F) | 0x40; - } - } - - NBPtr->SetTrainDly (NBPtr, AccessPhRecDly, DIMM_BYTE_ACCESS (Dimm, ByteLane), CurrentSeed); - IDS_HDT_CONSOLE (MEM_FLOW, "%02x ", CurrentSeed); - } - } else { - //10.Multiply the previously saved delay values in Pass 1, step #5 by (target frequency)/400 to find - //the gross and fine delay initialization values at the target frequency. Use these values as the initial - //seed values when executing Pass 2, step #4. - for (ByteLane = 0; ByteLane < TechPtr->DlyTableWidth (); ByteLane++) { - // This includes ECC as byte 8 - WrDqsDly = ChannelPtr->WrDqsDlys[Dimm * TechPtr->DlyTableWidth () + ByteLane]; - TechPtr->Bytelane = ByteLane; - NBPtr->FamilySpecificHook[TrainWlPerNibbleSeed] (NBPtr, &WrDqsDly); - - if (MCTPtr->Status[SbRegistered]) { - // - // For Registered Dimms - // - MemClkRegDly = ((RCW2 & BIT0) == 0) ? 0x20 : 0x30; - } else { - // - // Unbuffered Dimms and LRDIMMs - // - MemClkRegDly = 0; - } - - WrDqsBias = 0; - NBPtr->FamilySpecificHook[AdjustWrDqsBeforeSeedScaling] (NBPtr, &WrDqsBias); - - // Scale WrDqsDly to the next speed - WrDqsDly = (UINT16) (MemClkRegDly + ((((INT32) WrDqsDly - MemClkRegDly - WrDqsBias) * Speed) / TechPtr->PrevSpeed)); - - ChannelPtr->WrDqsDlys[Dimm * TechPtr->DlyTableWidth () + ByteLane] = (UINT8) WrDqsDly; - - if (NBPtr->IsSupported[WLSeedAdjust]) { - if ((WrDqsDly & 0x20) != 0) { - // If (SeedGross is odd) then SeedPreGross = 1 - WrDqsDly = (WrDqsDly & 0x1F) | 0x20; - } else { - // If (SeedGross is even) then SeedPreGross = 2 - WrDqsDly = (WrDqsDly & 0x1F) | 0x40; - } - } - NBPtr->SetTrainDly (NBPtr, AccessPhRecDly, DIMM_BYTE_ACCESS (Dimm, ByteLane), WrDqsDly); - IDS_HDT_CONSOLE (MEM_FLOW, "%02x ", WrDqsDly); - } - } - IDS_HDT_CONSOLE (MEM_FLOW, "\n"); -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * This function begins WL training for a specific DIMM - * - * @param[in,out] *TechPtr - Pointer to the MEM_TECH_BLOCK - * @param[in] Dimm - DIMM to be trained - * - */ - -VOID -STATIC -MemTBeginWLTrain3 ( - IN OUT MEM_TECH_BLOCK *TechPtr, - IN UINT8 Dimm - ) -{ - MEM_DATA_STRUCT *MemPtr; - DIE_STRUCT *MCTPtr; - MEM_NB_BLOCK *NBPtr; - UINT8 ByteLane; - UINT8 Seed; - UINT8 Delay; - - NBPtr = TechPtr->NBPtr; - MemPtr = NBPtr->MemPtr; - MCTPtr = NBPtr->MCTPtr; - - AGESA_TESTPOINT (TpProcMemWlTrainTargetDimm, &(MemPtr->StdHeader)); - // Assert ODT pins for write leveling - NBPtr->SetBitField (NBPtr, BFWrLvOdtEn, 1); - - // Wait 10 MEMCLKs to allow for ODT signal settling. - NBPtr->WaitXMemClks (NBPtr, 10); - - IDS_HDT_CONSOLE (MEM_FLOW, "\t\t\tWrtLvTrEn = 1\n"); - // Program F2x[1, 0]9C_x08[WrtLlTrEn]=1. - NBPtr->SetBitField (NBPtr, BFWrtLvTrEn, 1); - - // Wait 200 MEMCLKs. - NBPtr->WaitXMemClks (NBPtr, 200); - - // Program F2x[1, 0]9C_x08[WrtLlTrEn]=0. - NBPtr->SetBitField (NBPtr, BFWrtLvTrEn, 0); - - // Read from registers F2x[1, 0]9C_x[51:50] and F2x[1, 0]9C_x52 to get the gross and fine Delay settings - // for the target Dimm and save these values. - IDS_HDT_CONSOLE (MEM_FLOW, "\t\t\t PRE: "); - for (ByteLane = 0; ByteLane < (MCTPtr->Status[SbEccDimms] ? 9 : 8); ByteLane++) { - // This includes ECC as byte 8 - Seed = NBPtr->ChannelPtr->WrDqsDlys[(Dimm * TechPtr->DlyTableWidth ()) + ByteLane]; - Delay = (UINT8)NBPtr->GetTrainDly (NBPtr, AccessPhRecDly, DIMM_BYTE_ACCESS (Dimm, ByteLane)); - IDS_HDT_CONSOLE (MEM_FLOW, "%02x ", Delay); - - if (NBPtr->IsSupported[WLSeedAdjust]) { - // Recover WrDqsGrossDly: - // WrDqsGrossDly = SeedGross + PhRecGrossDlyByte - SeedPreGross - if ((Seed & 0x20) != 0) { - // If (SeedGross is odd) then SeedPreGross = 1 - if ((NBPtr->IsSupported[WLNegativeDelay]) && ((Seed & 0x80) != 0)) { - // If the seed was negative, save the most negative delay in WLCriticalDelay - TechPtr->WLCriticalDelay = MIN (TechPtr->WLCriticalDelay, (INT16)Delay - 0x40); - Delay -= 0x40; - } else { - Delay += (Seed & 0xE0) - 0x20; - } - } else { - // If (SeedGross is even) then SeedPreGross = 2 - if (((Seed & 0xE0) == 0) && (Delay < 0x40)) { - // If SeedGross is 0 and PhRecGrossDlyByte is less than SeedPreGross, - // we have a negative result and need to program the delay to 0 - if (NBPtr->IsSupported[WLNegativeDelay]) { - // - // Save the lowest negative delay value across all Dimms and Bytelanes - // - TechPtr->WLCriticalDelay = MIN (TechPtr->WLCriticalDelay, (INT16)Delay - 0x40); - Delay -= 0x40; - } else { - Delay = 0; - } - } else { - Delay += (Seed & 0xE0) - 0x40; - } - } - } else if (((Seed >> 5) == 0) && ((Delay >> 5) == 3)) { - IDS_OPTION_HOOK (IDS_CHECK_NEGATIVE_WL, &Delay, &(TechPtr->NBPtr->MemPtr->StdHeader)); - // If seed has gross delay of 0 and PRE has gross delay of 3, - // then round the total delay of TxDqs to 0. - Delay = 0; - } - - if ((!NBPtr->IsSupported[WLNegativeDelay]) && ((Delay > (Seed + 0x20)) || (Seed > (Delay + 0x20)))) { - // - // If PRE comes back with more than Seed +/- 0x20, then this is an - // unexpected condition. Log the condition. - // - PutEventLog (AGESA_ERROR, MEM_ERROR_WL_PRE_OUT_OF_RANGE, NBPtr->Node, NBPtr->Dct, NBPtr->Channel, ((Seed << 8) + Delay), &NBPtr->MemPtr->StdHeader); - } - - TechPtr->Bytelane = ByteLane; - TechPtr->TargetDIMM = Dimm; - NBPtr->FamilySpecificHook[TrainWlPerNibbleAdjustWLDly] (NBPtr, &Delay); - NBPtr->SetTrainDly (NBPtr, AccessWrDqsDly, DIMM_BYTE_ACCESS (Dimm, ByteLane), Delay); - NBPtr->ChannelPtr->WrDqsDlys[(Dimm * TechPtr->DlyTableWidth ()) + ByteLane] = Delay; - } - - IDS_HDT_CONSOLE_DEBUG_CODE ( - IDS_HDT_CONSOLE (MEM_FLOW, "\n\t\t\tWrDqs: "); - for (ByteLane = 0; ByteLane < (MCTPtr->Status[SbEccDimms] ? 9 : 8); ByteLane++) { - IDS_HDT_CONSOLE (MEM_FLOW, "%02x ", NBPtr->ChannelPtr->WrDqsDlys[(Dimm * TechPtr->DlyTableWidth ()) + ByteLane]); - } - IDS_HDT_CONSOLE (MEM_FLOW, "\n\n"); - ); - - // Disable write leveling ODT pins - NBPtr->SetBitField (NBPtr, BFWrLvOdtEn, 0); - - // Wait 10 MEMCLKs to allow for ODT signal settling. - NBPtr->WaitXMemClks (NBPtr, 10); - -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * This function programs register after Phy assisted training is finish. - * - * @param[in,out] *TechPtr - Pointer to the MEM_TECH_BLOCK - * - * @return TRUE - No fatal error occurs. - * @return FALSE - Fatal error occurs. - */ - -BOOLEAN -MemTExitPhyAssistedTrainingClient3 ( - IN OUT MEM_TECH_BLOCK *TechPtr - ) -{ - MEM_NB_BLOCK *NBPtr; - UINT8 Dct; - UINT8 ChipSel; - NBPtr = TechPtr->NBPtr; - - NBPtr->FamilySpecificHook[ReEnablePhyComp] (NBPtr, NBPtr); - NBPtr->BrdcstSet (NBPtr, BFRxPtrInitReq, 1); - NBPtr->PollBitField (NBPtr, BFRxPtrInitReq, 0, PCI_ACCESS_TIMEOUT, TRUE); - NBPtr->BrdcstSet (NBPtr, BFDisDllShutdownSR, 1); - NBPtr->BrdcstSet (NBPtr, BFEnterSelfRef, 1); - NBPtr->PollBitField (NBPtr, BFEnterSelfRef, 0, PCI_ACCESS_TIMEOUT, TRUE); - IDS_HDT_CONSOLE (MEM_FLOW, "\tMemClkAlign = 2\n"); - NBPtr->BrdcstSet (NBPtr, BFDbeGskMemClkAlignMode, 2); - NBPtr->BrdcstSet (NBPtr, BFExitSelfRef, 1); - NBPtr->PollBitField (NBPtr, BFExitSelfRef, 0, PCI_ACCESS_TIMEOUT, TRUE); - NBPtr->BrdcstSet (NBPtr, BFDisDllShutdownSR, 0); - - // Calculate Max Latency for both channels to prepare for position training - for (Dct = 0; Dct < NBPtr->DctCount; Dct++) { - IDS_HDT_CONSOLE (MEM_STATUS, "\tDct %d\n", Dct); - NBPtr->SwitchDCT (NBPtr, Dct); - if (TechPtr->FindMaxDlyForMaxRdLat (TechPtr, &ChipSel)) { - NBPtr->SetMaxLatency (NBPtr, TechPtr->MaxDlyForMaxRdLat); - } - } - return (BOOLEAN) (NBPtr->MCTPtr->ErrCode < AGESA_FATAL); -} - diff --git a/src/vendorcode/amd/agesa/f12/Proc/Mem/Tech/Makefile.inc b/src/vendorcode/amd/agesa/f12/Proc/Mem/Tech/Makefile.inc deleted file mode 100644 index fa6a130a16..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/Mem/Tech/Makefile.inc +++ /dev/null @@ -1,10 +0,0 @@ -libagesa-y += mt.c -libagesa-y += mthdi.c -libagesa-y += mttEdgeDetect.c -libagesa-y += mttdimbt.c -libagesa-y += mttecc.c -libagesa-y += mtthrc.c -libagesa-y += mtthrcSeedTrain.c -libagesa-y += mttml.c -libagesa-y += mttoptsrc.c -libagesa-y += mttsrc.c diff --git a/src/vendorcode/amd/agesa/f12/Proc/Mem/Tech/mt.c b/src/vendorcode/amd/agesa/f12/Proc/Mem/Tech/mt.c deleted file mode 100644 index 624a8b92cf..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/Mem/Tech/mt.c +++ /dev/null @@ -1,262 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * mt.c - * - * Common Technology file - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: (Mem/Tech) - * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $ - * - **/ -/***************************************************************************** -* -* Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* *************************************************************************** -* -*/ - -/* - *---------------------------------------------------------------------------- - * MODULES USED - * - *---------------------------------------------------------------------------- - */ - - -#include "AGESA.h" -#include "amdlib.h" -#include "mport.h" -#include "mm.h" -#include "mn.h" -#include "mu.h" -#include "mt.h" -#include "Filecode.h" -CODE_GROUP (G1_PEICC) -RDATA_GROUP (G1_PEICC) - -#define FILECODE PROC_MEM_TECH_MT_FILECODE -/*---------------------------------------------------------------------------- - * DEFINITIONS AND MACROS - * - *---------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------- - * TYPEDEFS AND STRUCTURES - * - *---------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------- - * PROTOTYPES OF LOCAL FUNCTIONS - * - *---------------------------------------------------------------------------- - */ -BOOLEAN -STATIC -MemTDefaultTechnologyHook ( - IN OUT MEM_TECH_BLOCK *TechPtr, - IN OUT VOID *OptParam - ); -/*---------------------------------------------------------------------------- - * EXPORTED FUNCTIONS - * - *---------------------------------------------------------------------------- - */ - -/* -----------------------------------------------------------------------------*/ -/** - * - * This function is the default return for non-training technology features - * - * @param[in,out] *TechPtr - Pointer to the MEM_TECH_BLOCK - */ -BOOLEAN -MemTFeatDef ( - IN OUT MEM_TECH_BLOCK *TechPtr - ) -{ - return TRUE; -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * This function sets the TestFail bit for all CS that fail training. - * - * @param[in,out] *TechPtr - Pointer to the MEM_TECH_BLOCK - */ -VOID -MemTMarkTrainFail ( - IN OUT MEM_TECH_BLOCK *TechPtr - ) -{ - MEM_NB_BLOCK *NBPtr; - UINT8 Dct; - UINT8 ChipSel; - - NBPtr = TechPtr->NBPtr; - for (Dct = 0; Dct < NBPtr->DctCount; Dct ++) { - NBPtr->SwitchDCT (NBPtr, Dct); - NBPtr->DCTPtr->Timings.CsEnabled &= ~NBPtr->DCTPtr->Timings.CsTrainFail; - for (ChipSel = 0; ChipSel < MAX_CS_PER_CHANNEL; ChipSel ++) { - if ((NBPtr->DCTPtr->Timings.CsTrainFail & ((UINT16)1 << ChipSel)) != 0) { - NBPtr->SetBitField (NBPtr, (BFCSBaseAddr0Reg + ChipSel), (UINT32)1 << BFTestFail); - } - } - } -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * This function sets the initial controller environment before training. - * - * @param[in,out] *TechPtr - Pointer to the MEM_TECH_BLOCK - * - */ - -VOID -MemTBeginTraining ( - IN OUT MEM_TECH_BLOCK *TechPtr - ) -{ - S_UINT64 SMsr; - MEM_DATA_STRUCT *MemPtr; - MEM_NB_BLOCK *NBPtr; - - NBPtr = TechPtr->NBPtr; - MemPtr = NBPtr->MemPtr; - - LibAmdReadCpuReg (CR4_REG, &TechPtr->CR4reg); - LibAmdWriteCpuReg (CR4_REG, TechPtr->CR4reg | ((UINT32)1 << 9)); // enable SSE2 - - LibAmdMsrRead (HWCR, (UINT64 *) (&SMsr), &MemPtr->StdHeader); // HWCR - TechPtr->HwcrLo = SMsr.lo; - SMsr.lo |= 0x00020000; // turn on HWCR.wrap32dis - SMsr.lo &= 0xFFFF7FFF; // turn off HWCR.SSEDIS - LibAmdMsrWrite (HWCR, (UINT64 *) (&SMsr), &MemPtr->StdHeader); - - TechPtr->DramEcc = (UINT8) NBPtr->GetBitField (NBPtr, BFDramEccEn); - NBPtr->SetBitField (NBPtr, BFDramEccEn, 0); // Disable ECC -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * This function sets the final controller environment after training. - * - * @param[in,out] *TechPtr - Pointer to the MEM_TECH_BLOCK - * - */ - -VOID -MemTEndTraining ( - IN OUT MEM_TECH_BLOCK *TechPtr - ) -{ - S_UINT64 SMsr; - MEM_DATA_STRUCT *MemPtr; - MEM_NB_BLOCK *NBPtr; - - NBPtr = TechPtr->NBPtr; - MemPtr = NBPtr->MemPtr; - - LibAmdWriteCpuReg (CR4_REG, TechPtr->CR4reg); - - LibAmdMsrRead (HWCR, (UINT64 *)&SMsr, &MemPtr->StdHeader); - SMsr.lo = TechPtr->HwcrLo; - LibAmdMsrWrite (HWCR, (UINT64 *)&SMsr, &MemPtr->StdHeader); - - NBPtr->SetBitField (NBPtr, BFDramEccEn, TechPtr->DramEcc); -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * This function sets all the bytelanes/nibbles to the same delay value - * - * @param[in,out] *TechPtr - Pointer to the MEM_TECH_BLOCK - * @param[in] Dly - Delay value to set - * - */ - -VOID -MemTSetDQSDelayAllCSR ( - IN OUT MEM_TECH_BLOCK *TechPtr, - IN UINT8 Dly - ) -{ - UINT8 i; - UINT8 MaxBytelanes; - MaxBytelanes = (TechPtr->NBPtr->MCTPtr->Status[SbEccDimms] && TechPtr->NBPtr->IsSupported[EccByteTraining]) ? 9 : 8; - - for (i = 0; i < MaxBytelanes; i++) { - TechPtr->SetDQSDelayCSR (TechPtr, i, Dly); - } -} -/*----------------------------------------------------------------------------- - * - * - * This function is used to intialize common technology functions - * - * @param[in,out] *TechPtr - Pointer to the MEM_TECH_BLOCK - * ---------------------------------------------------------------------------- - */ -VOID -MemTCommonTechInit ( - IN OUT MEM_TECH_BLOCK *TechPtr - ) -{ - UINT8 i; - for (i = 0; i < NumberOfTechHooks; i++) { - TechPtr->TechnologySpecificHook[i] = MemTDefaultTechnologyHook; - } -} -/*----------------------------------------------------------------------------- - * - * - * This function is an empty function used to intialize TechnologySpecificHook array - * - * @param[in,out] *TechPtr - Pointer to the MEM_NB_BLOCK - * @param[in,out] OptParam - Optional parameter - * - * @return FALSE - always - * ---------------------------------------------------------------------------- - */ -BOOLEAN -STATIC -MemTDefaultTechnologyHook ( - IN OUT MEM_TECH_BLOCK *TechPtr, - IN OUT VOID *OptParam - ) -{ - return FALSE; -} diff --git a/src/vendorcode/amd/agesa/f12/Proc/Mem/Tech/mthdi.c b/src/vendorcode/amd/agesa/f12/Proc/Mem/Tech/mthdi.c deleted file mode 100644 index a2d666e28f..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/Mem/Tech/mthdi.c +++ /dev/null @@ -1,125 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * mthdi.c - * - * Common technology hardware dram init support functions - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: (Mem/Tech) - * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $ - * - **/ -/***************************************************************************** -* -* Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* *************************************************************************** -* -*/ - -/* - *---------------------------------------------------------------------------- - * MODULES USED - * - *---------------------------------------------------------------------------- - */ - - - -#include "AGESA.h" -#include "Ids.h" -#include "mm.h" -#include "mn.h" -#include "mu.h" -#include "mt.h" -#include "Filecode.h" -CODE_GROUP (G1_PEICC) -RDATA_GROUP (G1_PEICC) - -#define FILECODE PROC_MEM_TECH_MTHDI_FILECODE -/*---------------------------------------------------------------------------- - * DEFINITIONS AND MACROS - * - *---------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------- - * TYPEDEFS AND STRUCTURES - * - *---------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------- - * PROTOTYPES OF LOCAL FUNCTIONS - * - *---------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------- - * EXPORTED FUNCTIONS - * - *---------------------------------------------------------------------------- - */ - -/* -----------------------------------------------------------------------------*/ -/** - * - * This function initiates Hardware based dram initialization for both DCTs - * at the same time. - * - * @param[in,out] *TechPtr - Pointer to the MEM_TECH_BLOCK - * - */ - -VOID -MemTDramInitHw ( - IN OUT MEM_TECH_BLOCK *TechPtr - ) -{ - UINT8 Dct; - MEM_NB_BLOCK *NBPtr; - - NBPtr = TechPtr->NBPtr; - - NBPtr->BrdcstSet (NBPtr, BFInitDram, 1); - // Phy fence training - AGESA_TESTPOINT (TpProcMemPhyFenceTraining, &(NBPtr->MemPtr->StdHeader)); - for (Dct = 0; Dct < NBPtr->DctCount; Dct++) { - NBPtr->SwitchDCT (NBPtr, Dct); - if (NBPtr->DCTPtr->Timings.DctMemSize != 0) { - IDS_HDT_CONSOLE (MEM_STATUS, "\tDct %d\n", Dct); - NBPtr->PhyFenceTraining (NBPtr); - } - } -} - -/*---------------------------------------------------------------------------- - * LOCAL FUNCTIONS - * - *---------------------------------------------------------------------------- - */ diff --git a/src/vendorcode/amd/agesa/f12/Proc/Mem/Tech/mttEdgeDetect.c b/src/vendorcode/amd/agesa/f12/Proc/Mem/Tech/mttEdgeDetect.c deleted file mode 100644 index 9ae5fe0b2f..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/Mem/Tech/mttEdgeDetect.c +++ /dev/null @@ -1,910 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * mttEdgeDetect.c - * - * DQS R/W position training utilizing Data Eye Edge Detection for optimization - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: (Mem/Tech) - * @e \$Revision: 49045 $ @e \$Date: 2011-03-16 13:16:58 +0800 (Wed, 16 Mar 2011) $ - * - **/ -/***************************************************************************** -* -* Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* *************************************************************************** -* -*/ - -/* - *---------------------------------------------------------------------------- - * MODULES USED - * - *---------------------------------------------------------------------------- - */ - - - - - -#include "AGESA.h" -#include "amdlib.h" -#include "AdvancedApi.h" -#include "GeneralServices.h" -#include "Ids.h" -#include "heapManager.h" -#include "mm.h" -#include "mn.h" -#include "mu.h" -#include "mt.h" -#include "mport.h" -#include "mttEdgeDetect.h" -#include "OptionMemory.h" -#include "merrhdl.h" -#include "Filecode.h" -CODE_GROUP (G1_PEICC) -RDATA_GROUP (G1_PEICC) - -#define FILECODE PROC_MEM_TECH_MTTEDGEDETECT_FILECODE -/*---------------------------------------------------------------------------- - * DEFINITIONS AND MACROS - * - *---------------------------------------------------------------------------- - */ - - -#define LAST_DELAY (-128) -#define INC_DELAY 1 -#define DEC_DELAY 0 - - - -/*---------------------------------------------------------------------------- - * TYPEDEFS AND STRUCTURES - * - *---------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------- - * PROTOTYPES OF LOCAL FUNCTIONS - * - *---------------------------------------------------------------------------- - */ - -/** - * Sweep Table For Byte Training without insertion delay - * -*/ -DQS_POS_SWEEP_TABLE SweepTableByte[] = -{ - // Begin End Inc/Dec Step EndResult Edge - { 0x00, 0x1F, INC_DELAY, 4, 0xFFFF, LEFT_EDGE}, /// For Left Edge, start from 0 and Increment to 0x1F by 4 until all PASS - { LAST_DELAY, 0x00, DEC_DELAY, -1, 0xFE00, LEFT_EDGE}, /// Then go back down to 0x00 by 1 until all FAIL - { 0x1F, 0x00, DEC_DELAY, -4, 0xFFFF, RIGHT_EDGE}, /// For Right Edge, start from 0x1F down to 0 until all PASS. - { LAST_DELAY, 0x1F, INC_DELAY, 1, 0xFE00, RIGHT_EDGE} /// Then go back up by 1 until all FAIL. -}; -/** - * Sweep Table For Byte Training with insertion delay - * -*/ -DQS_POS_SWEEP_TABLE InsSweepTableByte[] = -{ - // Begin End Inc/Dec Step EndResult Edge - { 0x00, -0x20, DEC_DELAY, -4, 0xFE00, LEFT_EDGE}, /// For Left Edge, start from 0 and Decrement to -0x20 by -4 until all FAIL - { LAST_DELAY, 0x1F, INC_DELAY, 1, 0xFFFF, LEFT_EDGE}, /// Then go back up to 0x1F by 1 until all PASS - { 0x1F, 0x00, DEC_DELAY, -4, 0xFFFF, RIGHT_EDGE}, /// For Right Edge, start from 0x1F down to 0 until all PASS. - { LAST_DELAY, 0x1F, INC_DELAY, 1, 0xFE00, RIGHT_EDGE} /// Then go back up by 1 until all FAIL. -}; - -BOOLEAN -STATIC -MemTTrainDQSRdWrEdgeDetect ( - IN OUT MEM_TECH_BLOCK *TechPtr - ); - -BOOLEAN -STATIC -MemTInitTestPatternAddress ( - IN OUT MEM_TECH_BLOCK *TechPtr, - IN OUT SWEEP_INFO *SweepPtr - ); - -BOOLEAN -STATIC -MemTContinueSweep ( - IN OUT MEM_TECH_BLOCK *TechPtr, - IN OUT SWEEP_INFO *SweepPtr - ); - -BOOLEAN -STATIC -MemTSetNextDelay ( - IN OUT MEM_TECH_BLOCK *TechPtr, - IN OUT SWEEP_INFO *SweepPtr - ); - -UINT8 -STATIC -MemTScaleDelayVal ( - IN OUT MEM_TECH_BLOCK *TechPtr, - IN INT8 Delay - ); - -BOOLEAN -STATIC -MemTDataEyeSave ( - IN OUT MEM_TECH_BLOCK *TechPtr, - IN OUT SWEEP_INFO *SweepPtr, - IN UINT8 ByteLane - ); - -/*---------------------------------------------------------------------------- - * EXPORTED FUNCTIONS - * - *---------------------------------------------------------------------------- - */ -extern MEM_FEAT_TRAIN_SEQ memTrainSequenceDDR3[]; -/* -----------------------------------------------------------------------------*/ -/** - * - * This function executes DQS position training for all a Memory channel using - * the Edge Detection algorithm. - * - * @param[in,out] *TechPtr - Pointer to the MEM_TECH_BLOCK - * - */ - -BOOLEAN -MemTTrainDQSEdgeDetectSw ( - IN OUT MEM_TECH_BLOCK *TechPtr - ) -{ - MEM_NB_BLOCK *NBPtr; - BOOLEAN Status; - - Status = FALSE; - NBPtr = TechPtr->NBPtr; - TechPtr->TrainingType = TRN_DQS_POSITION; - // - // Initialize the Pattern - // - if (AGESA_SUCCESS == NBPtr->TrainingPatternInit (NBPtr)) { - // - // Setup hardware training engine (if applicable) - // - NBPtr->FamilySpecificHook[SetupHwTrainingEngine] (NBPtr, &TechPtr->TrainingType); - // - // Start Edge Detection - // - Status |= MemTTrainDQSRdWrEdgeDetect (TechPtr); - // - // Finalize the Pattern - // - Status &= (AGESA_SUCCESS == NBPtr->TrainingPatternFinalize (NBPtr)); - } - return Status; -} - -/*---------------------------------------------------------------------------- - * LOCAL FUNCTIONS - * - *---------------------------------------------------------------------------- - */ - -/* -----------------------------------------------------------------------------*/ -/** - * - * This Executes Read DQS and Write Data Position training on a chip select pair - * using the Edge Detection algorithm. - * - * @param[in,out] *TechPtr - Pointer to the MEM_TECH_BLOCK - * - * @return TRUE - No Errors occurred - * @return FALSE - Errors occurred - - */ - -BOOLEAN -STATIC -MemTTrainDQSRdWrEdgeDetect ( - IN OUT MEM_TECH_BLOCK *TechPtr - ) -{ - MEM_DATA_STRUCT *MemPtr; - MEM_NB_BLOCK *NBPtr; - UINT8 WrDqDelay; - UINT8 Dct; - UINT8 CSPerChannel; - UINT8 CsPerDelay; - UINT8 ChipSel; - UINT8 i; - BOOLEAN Status; - UINT8 TimesFail; - UINT8 TimesRetrain; - - NBPtr = TechPtr->NBPtr; - MemPtr = NBPtr->MemPtr; - TimesRetrain = DEFAULT_TRAINING_TIMES; - IDS_OPTION_HOOK (IDS_MEM_RETRAIN_TIMES, &TimesRetrain, &MemPtr->StdHeader); - // - // Set environment settings before training - // - IDS_HDT_CONSOLE (MEM_STATUS, "\nStart Read/Write Data Eye Edge Detection.\n"); - MemTBeginTraining (TechPtr); - // - // Do Rd DQS /Wr Data Position training for all Dcts/Chipselects - // - for (Dct = 0; Dct < NBPtr->DctCount; Dct++) { - IDS_HDT_CONSOLE (MEM_STATUS, "\tDct %d\n", Dct); - NBPtr->SwitchDCT (NBPtr, Dct); - // - // Chip Select Loop - // - CSPerChannel = NBPtr->CSPerChannel (NBPtr); - CsPerDelay = NBPtr->CSPerDelay (NBPtr); - for (ChipSel = 0; ChipSel < CSPerChannel; ChipSel = ChipSel + CsPerDelay ) { - // - // Init Bit Error Masks - // - LibAmdMemFill (&NBPtr->ChannelPtr->FailingBitMask[ (ChipSel * MAX_BYTELANES_PER_CHANNEL) ], - 0xFF, - (MAX_BYTELANES_PER_CHANNEL * CsPerDelay), - &MemPtr->StdHeader); - if ((NBPtr->DCTPtr->Timings.CsEnabled & ((UINT16) 1 << ChipSel)) != 0) { - TechPtr->ChipSel = ChipSel; - IDS_HDT_CONSOLE (MEM_STATUS, "\t\tCS %d\n", ChipSel); - IDS_HDT_CONSOLE (MEM_FLOW, "\t\t\tIncrease WrDat, Train RdDqs:\n"); - - TechPtr->DqsRdWrPosSaved = 0; - // - // Use a list of Approximate Write Data delay values and train Read DQS Position for - // each until a valid Data eye is found. - // - Status = FALSE; - TimesFail = 0; - NBPtr->FamilySpecificHook[InitializeRxEnSeedlessTraining] (NBPtr, NBPtr); - ERROR_HANDLE_RETRAIN_BEGIN (TimesFail, TimesRetrain) { - i = 0; - while (NBPtr->GetApproximateWriteDatDelay (NBPtr, i, &WrDqDelay)) { - TechPtr->SmallDqsPosWindow = FALSE; - // - // Set Write Delay approximation - // - TechPtr->Direction = DQS_WRITE_DIR; - IDS_HDT_CONSOLE (MEM_FLOW, "\n\t\t\tWrite Delay: %02x", WrDqDelay); - MemTSetDQSDelayAllCSR (TechPtr, WrDqDelay); - // - // Attempt Read Training - // - TechPtr->Direction = DQS_READ_DIR; - Status = memTrainSequenceDDR3[NBPtr->TrainingSequenceIndex].MemTechFeatBlock->RdPosTraining (TechPtr); - if (Status) { - // - // If Read DQS Training was successful, Train Write Data (DQ) Position - // - TechPtr->DqsRdWrPosSaved = 0; - IDS_HDT_CONSOLE (MEM_FLOW, "\n\t\t\tTrain WrDat:\n\n"); - TechPtr->Direction = DQS_WRITE_DIR; - if (NBPtr->FamilySpecificHook[BeforeWrDatTrn] (NBPtr, &ChipSel)) { - Status = MemTTrainDQSEdgeDetect (TechPtr); - } - break; - } - i++; - } - ERROR_HANDLE_RETRAIN_END ((Status == FALSE), TimesFail) - } - - // - // If we went through the table, Fail. - // - if (Status == FALSE) { - // On training failure, check and record whether training fails due to small window or no window - if (TechPtr->SmallDqsPosWindow) { - NBPtr->MCTPtr->ErrStatus[EsbSmallDqs] = TRUE; - } else { - NBPtr->MCTPtr->ErrStatus[EsbNoDqsPos] = TRUE; - } - - SetMemError (AGESA_ERROR, NBPtr->MCTPtr); - if (TechPtr->Direction == DQS_READ_DIR) { - PutEventLog (AGESA_ERROR, MEM_ERROR_NO_DQS_POS_RD_WINDOW, NBPtr->Node, NBPtr->Dct, NBPtr->Channel, 0, &NBPtr->MemPtr->StdHeader); - } else { - PutEventLog (AGESA_ERROR, MEM_ERROR_NO_DQS_POS_WR_WINDOW, NBPtr->Node, NBPtr->Dct, NBPtr->Channel, 0, &NBPtr->MemPtr->StdHeader); - } - NBPtr->DCTPtr->Timings.CsTrainFail |= (UINT16)1 << ChipSel; - // If the even chip select failed training always fail the odd, if present. - if ((ChipSel & 0x01) == 0) { - if (NBPtr->DCTPtr->Timings.CsPresent & ((UINT16)1 << (ChipSel + 1))) { - NBPtr->DCTPtr->Timings.CsTrainFail |= (UINT16)1 << (ChipSel + 1); - } - } - NBPtr->MemPtr->ErrorHandling (NBPtr->MCTPtr, NBPtr->Dct, NBPtr->DCTPtr->Timings.CsTrainFail, &NBPtr->MemPtr->StdHeader); - } - } else { - // - // Clear Bit Error Masks if these CS will not be trained. - // - LibAmdMemFill (&NBPtr->ChannelPtr->FailingBitMask[ (ChipSel * MAX_BYTELANES_PER_CHANNEL) ], - 0x00, - (MAX_BYTELANES_PER_CHANNEL * CsPerDelay), - &NBPtr->MemPtr->StdHeader); - } - } - } - // - // Restore environment settings after training - // - MemTEndTraining (TechPtr); - IDS_HDT_CONSOLE (MEM_FLOW, "End Read/Write Data Eye Edge Detection\n\n"); - return (BOOLEAN) (NBPtr->MCTPtr->ErrCode < AGESA_FATAL); -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * This function executes DQS position training for both read and write, using - * the Edge Detection Algorithm. This method searches for the beginning and end - * of the Data Eye with out scanning every DSQ delay value. The following is a - * detailed description of the algorithm: - * - * Four-Stage Data Eye Sweep - * - * -Search starts at Delay value of 0. - * -Search left in steps of 4/32UI looking for all Byte lanes Passing. Left from zero rolls over to a negative value. - * -Negative values are translated to the high end of the delay range, but using Insertion delay comparison. - * -For each passing byte lane, freeze delay at first passing value, but set mask so next steps will not compare for byte lanes that previously passed - * -Switch to search right in steps of 1/32UI looking for fail. - * -For each lane, starting delay for 1/32 sweep right is first passing delay from 4/32 sweep left. - * -For each failing byte lane, freeze delay at first failing value, but set mask so next steps will not compare for byte lanes that previously failed - * -Search right until all byte lanes have failed - * -For each lane, right edge used by BIOS will be first failing delay value minus 1/32 - - * - * @param[in,out] *TechPtr - Pointer to the MEM_TECH_BLOCK - * - * @return TRUE - All bytelanes pass - * @return FALSE - Some bytelanes fail -*/ -BOOLEAN -MemTTrainDQSEdgeDetect ( - IN OUT MEM_TECH_BLOCK *TechPtr - ) -{ - MEM_NB_BLOCK *NBPtr; - DIE_STRUCT *MCTPtr; - DQS_POS_SWEEP_TABLE *SweepTablePtr; - UINT8 SweepTableSize; - SWEEP_INFO SweepData; - BOOLEAN Status; - UINT16 CurrentResult; - UINT16 AlignedResult; - UINT16 OffsetResult; - UINT8 StageIndex; - UINT8 CsIndex; - UINT8 CsPerDelay; - UINT8 i; - - Status = TRUE; - // - // Initialize Object Pointers - // - NBPtr = TechPtr->NBPtr; - MCTPtr = NBPtr->MCTPtr; - // - // Initialize stack variables - // - LibAmdMemFill (&SweepData, 0, sizeof (SWEEP_INFO), &NBPtr->MemPtr->StdHeader); - // - /// Get Pointer to Sweep Table - // - if (TechPtr->Direction == DQS_READ_DIR) { - SweepTablePtr = InsSweepTableByte; - SweepTableSize = GET_SIZE_OF (InsSweepTableByte); - } else { - SweepTablePtr = SweepTableByte; - SweepTableSize = GET_SIZE_OF (SweepTableByte); - } - // - // Get number of CS to train - // - CsPerDelay = NBPtr->CSPerDelay (NBPtr); - // - /// Set up the test Pattern, exit if no Memory - // - if (MemTInitTestPatternAddress (TechPtr, &SweepData) == FALSE) { - LibAmdMemFill (&NBPtr->ChannelPtr->FailingBitMask[ (TechPtr->ChipSel * MAX_BYTELANES_PER_CHANNEL) ], - 0, - (MAX_BYTELANES_PER_CHANNEL * CsPerDelay), - &NBPtr->MemPtr->StdHeader); - return FALSE; - } - // - // Clear Error Flag - // - SweepData.Error = FALSE; - NBPtr->FamilySpecificHook[InitialzeRxEnSeedlessByteLaneError] (NBPtr, NBPtr); - // - /// Process Sweep table, using entries from the table to determine Starting and Ending Delays - /// as well as the Step size and criteria for evaluating whether the correct result is found. - /// - /// Delay values at this level are an abstract range of values which gets scaled to the actual value - /// before it is written to the hardware. This allows NB specific code to handle the scaling as a - /// function of frequency or other conditions. - // - for (StageIndex = 0; (StageIndex < SweepTableSize) && (SweepData.Error == FALSE); StageIndex++) { - - IDS_HDT_CONSOLE (MEM_FLOW, "\t\t\tSTAGE: %d\t", StageIndex); - // - /// Initialize SweepData variables - // - SweepData.BeginDelay = SweepTablePtr->BeginDelay; - SweepData.EndDelay = SweepTablePtr->EndDelay; - SweepData.Step = 0; /// Step Value will be 0 to start. - SweepData.EndResult = SweepTablePtr->EndResult; - if (!(MCTPtr->Status[SbEccDimms] && NBPtr->IsSupported[EccByteTraining])) { - SweepData.EndResult |= 0x0100; - } - SweepData.Edge = SweepTablePtr->MinMax; - SweepData.InsertionDelayMsk = 0; - SweepData.ResultFound = 0x0000; - // - // Set Training Delays Pointer. - // - if (TechPtr->Direction == DQS_READ_DIR) { - SweepData.TrnDelays = (INT8 *) ((SweepData.Edge == RIGHT_EDGE) ? NBPtr->ChannelPtr->RdDqsMaxDlys : NBPtr->ChannelPtr->RdDqsMinDlys); - } else { - SweepData.TrnDelays = (INT8 *) ((SweepData.Edge == RIGHT_EDGE) ? NBPtr->ChannelPtr->WrDatMaxDlys : NBPtr->ChannelPtr->WrDatMinDlys); - }; - // - /// Set initial TrnDelay Values if necessary - // - IDS_HDT_CONSOLE (MEM_FLOW, "Sweeping %s DQS, %s from ", (TechPtr->Direction == DQS_READ_DIR) ?"Read":"Write", (SweepTablePtr->ScanDir == INC_DELAY) ? "incrementing":"decrementing"); - if (SweepData.BeginDelay != LAST_DELAY) { - IDS_HDT_CONSOLE (MEM_FLOW, "%02x", (UINT16) MemTScaleDelayVal (TechPtr, SweepData.BeginDelay)); - for (i = 0; i < ((MCTPtr->Status[SbEccDimms] && NBPtr->IsSupported[EccByteTraining]) ? 9 : 8); i++) { - SweepData.TrnDelays[i] = SweepData.BeginDelay; - } - } else { - IDS_HDT_CONSOLE (MEM_FLOW, "Current Delay"); - SweepData.Step = SweepTablePtr->Step; - } - IDS_HDT_CONSOLE (MEM_FLOW, " by %02x, until all bytelanes %s.\n\n", (UINT16) MemTScaleDelayVal (TechPtr, ABS (SweepTablePtr->Step)), (SweepData.EndResult == 0xFFFF)?"PASS":"FAIL"); - - //------------------------------------------------------------------- - // Sweep DQS Delays - // MemTContinueSweep function returns false to break out of loop. - // There are no other breaks out of this loop. - //------------------------------------------------------------------- - while (MemTContinueSweep (TechPtr, &SweepData)) { - IDS_HDT_CONSOLE (MEM_FLOW, "\t\t\t\tByte Lane : 08 07 06 05 04 03 02 01 00\n"); - IDS_HDT_CONSOLE (MEM_FLOW, "\t\t\t\tDQS Delays : %02x %02x %02x %02x %02x %02x %02x %02x %02x\n", - (UINT16) MemTScaleDelayVal (TechPtr, SweepData.TrnDelays[8]), - (UINT16) MemTScaleDelayVal (TechPtr, SweepData.TrnDelays[7]), (UINT16) MemTScaleDelayVal (TechPtr, SweepData.TrnDelays[6]), - (UINT16) MemTScaleDelayVal (TechPtr, SweepData.TrnDelays[5]), (UINT16) MemTScaleDelayVal (TechPtr, SweepData.TrnDelays[4]), - (UINT16) MemTScaleDelayVal (TechPtr, SweepData.TrnDelays[3]), (UINT16) MemTScaleDelayVal (TechPtr, SweepData.TrnDelays[2]), - (UINT16) MemTScaleDelayVal (TechPtr, SweepData.TrnDelays[1]), (UINT16) MemTScaleDelayVal (TechPtr, SweepData.TrnDelays[0]) - ); - // - /// Set Step Value - // - SweepData.Step = SweepTablePtr->Step; - CurrentResult = 0xFFFF; - // - /// Chip Select Loop: Test the Pattern for all populated CS that are controlled by the current delay registers - // - for (CsIndex = 0; CsIndex < CsPerDelay ; CsIndex++, TechPtr->ChipSel++) { - ASSERT (CsIndex < MAX_CS_PER_CHANNEL); - ASSERT (TechPtr->ChipSel < MAX_CS_PER_CHANNEL); - if (SweepData.CsAddrValid[CsIndex] == TRUE) { - // - /// If this is a Write Dqs sweep, Write the pattern now. - // - if (TechPtr->Direction == DQS_WRITE_DIR) { - NBPtr->WritePattern (NBPtr, SweepData.TestAddrRJ16[CsIndex], TechPtr->PatternBufPtr, TechPtr->PatternLength); - } - // - /// Read the Pattern Back - // - NBPtr->ReadPattern (NBPtr, TechPtr->TestBufPtr, SweepData.TestAddrRJ16[CsIndex], TechPtr->PatternLength); - // - /// Compare the Pattern and Merge the results using InsertionDelayMsk - // - AlignedResult = NBPtr->CompareTestPattern (NBPtr, TechPtr->TestBufPtr, TechPtr->PatternBufPtr, TechPtr->PatternLength * 64); - CurrentResult &= AlignedResult | SweepData.InsertionDelayMsk; - if (SweepData.InsertionDelayMsk != 0) { - OffsetResult = NBPtr->InsDlyCompareTestPattern (NBPtr, TechPtr->TestBufPtr, TechPtr->PatternBufPtr, TechPtr->PatternLength * 64); - CurrentResult &= (OffsetResult | (~SweepData.InsertionDelayMsk)); - } - // - /// Flush the Test Pattern - // - NBPtr->FlushPattern (NBPtr, SweepData.TestAddrRJ16[CsIndex], TechPtr->PatternLength); - NBPtr->FamilySpecificHook[ResetRxFifoPtr] (NBPtr, NBPtr); - } - } /// End Chip Select Loop - TechPtr->ChipSel = TechPtr->ChipSel - CsIndex; - IDS_HDT_CONSOLE (MEM_FLOW, "\t\t\t\tResult : %c %c %c %c %c %c %c %c %c \n", - (SweepData.ResultFound & ((UINT16) 1 << (8))) ? ' ':(CurrentResult & ((UINT16) 1 << (8))) ? 'P':'.', - (SweepData.ResultFound & ((UINT16) 1 << (7))) ? ' ':(CurrentResult & ((UINT16) 1 << (7))) ? 'P':'.', - (SweepData.ResultFound & ((UINT16) 1 << (6))) ? ' ':(CurrentResult & ((UINT16) 1 << (6))) ? 'P':'.', - (SweepData.ResultFound & ((UINT16) 1 << (5))) ? ' ':(CurrentResult & ((UINT16) 1 << (5))) ? 'P':'.', - (SweepData.ResultFound & ((UINT16) 1 << (4))) ? ' ':(CurrentResult & ((UINT16) 1 << (4))) ? 'P':'.', - (SweepData.ResultFound & ((UINT16) 1 << (3))) ? ' ':(CurrentResult & ((UINT16) 1 << (3))) ? 'P':'.', - (SweepData.ResultFound & ((UINT16) 1 << (2))) ? ' ':(CurrentResult & ((UINT16) 1 << (2))) ? 'P':'.', - (SweepData.ResultFound & ((UINT16) 1 << (1))) ? ' ':(CurrentResult & ((UINT16) 1 << (1))) ? 'P':'.', - (SweepData.ResultFound & ((UINT16) 1 << (0))) ? ' ':(CurrentResult & ((UINT16) 1 << (0))) ? 'P':'.' - ); - // - /// Merge current result into cumulative result and make it positive. - // - SweepData.ResultFound |= ~(CurrentResult ^ SweepData.EndResult); - - IDS_HDT_CONSOLE (MEM_FLOW, "\t\t\t\tResultFound : %c %c %c %c %c %c %c %c %c \n\n", - (SweepData.ResultFound & ((UINT16) 1 << (8))) ? 'Y':' ', - (SweepData.ResultFound & ((UINT16) 1 << (7))) ? 'Y':' ', - (SweepData.ResultFound & ((UINT16) 1 << (6))) ? 'Y':' ', - (SweepData.ResultFound & ((UINT16) 1 << (5))) ? 'Y':' ', - (SweepData.ResultFound & ((UINT16) 1 << (4))) ? 'Y':' ', - (SweepData.ResultFound & ((UINT16) 1 << (3))) ? 'Y':' ', - (SweepData.ResultFound & ((UINT16) 1 << (2))) ? 'Y':' ', - (SweepData.ResultFound & ((UINT16) 1 << (1))) ? 'Y':' ', - (SweepData.ResultFound & ((UINT16) 1 << (0))) ? 'Y':' ' - ); - } /// End of Delay Sweep - // - /// Place Final delay values at last passing delay. - // - if (SweepData.ResultFound == 0xFFFF) { - if ( ABS (SweepData.Step) == 1) { - for (i = 0; i < ((MCTPtr->Status[SbEccDimms] && NBPtr->IsSupported[EccByteTraining]) ? 9 : 8) ; i++) { - if ((SweepData.EndResult & ((UINT16) (1 << i))) == 0) { - SweepData.TrnDelays[i] = SweepData.TrnDelays[i] - SweepData.Step; - } - } - } - } - // - // Update Pointer to Sweep Table - // - SweepTablePtr++; - }///End of Edge Detect loop - // - /// If No Errors are detected, Calculate Data Eye Width and Center - // - if (SweepData.Error == FALSE) { - IDS_HDT_CONSOLE (MEM_FLOW, "\t\tData Eye Results:\n\n"); - IDS_HDT_CONSOLE (MEM_FLOW, "\t\tByte Left Right\n"); - IDS_HDT_CONSOLE (MEM_FLOW, "\t\tLane Edge Edge Width Center\n"); - for (i = 0; i < ((MCTPtr->Status[SbEccDimms] && NBPtr->IsSupported[EccByteTraining]) ? 9 : 8) ; i++) { - IDS_HDT_CONSOLE (MEM_FLOW, "\t\t %0d", i); - TechPtr->Bytelane = i; - if (!MemTDataEyeSave (TechPtr, &SweepData, i)) { - break; - } - IDS_HDT_CONSOLE (MEM_FLOW, "\n"); - if (SweepData.Error == TRUE) { - Status = FALSE; - } - NBPtr->FamilySpecificHook[TrackRxEnSeedlessRdWrSmallWindBLError] (NBPtr, &SweepData); - } - } else { - Status = FALSE; - IDS_HDT_CONSOLE (MEM_FLOW, "\t\t--DATA EYE NOT FOUND--\n\n"); - NBPtr->FamilySpecificHook[TrackRxEnSeedlessRdWrNoWindBLError] (NBPtr, &SweepData); - } - return Status; -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * Initialize the Test Pattern Address for two chip selects and, if this - * is a Write Data Eye, write the initial test pattern. - * - * Test Address is stored in the Sweep info struct. If Memory is not present - * then return with False. - * - * @param[in,out] *TechPtr - Pointer to the MEM_TECH_BLOCK - * @param[in,out] *SweepPtr - Pointer to SWEEP_INFO structure. - * - * @return BOOLEAN - * TRUE - Memory is present - * FALSE - No memory present on this Chip Select pair. - * -** - */ -BOOLEAN -STATIC -MemTInitTestPatternAddress ( - IN OUT MEM_TECH_BLOCK *TechPtr, - IN OUT SWEEP_INFO *SweepPtr - ) -{ - MEM_NB_BLOCK *NBPtr; - UINT8 ChipSel; - UINT8 CsPerDelay; - UINT8 CsIndex; - BOOLEAN BanksPresent; - - NBPtr = TechPtr->NBPtr; - BanksPresent = FALSE; - CsPerDelay = NBPtr->CSPerDelay (NBPtr); - ChipSel = TechPtr->ChipSel; - for (CsIndex = 0; CsIndex < CsPerDelay; ChipSel++, CsIndex++, TechPtr->ChipSel++) { - ASSERT (CsIndex < MAX_CS_PER_CHANNEL); - ASSERT (ChipSel < MAX_CS_PER_CHANNEL); - ASSERT (TechPtr->ChipSel < MAX_CS_PER_CHANNEL); - // - /// If memory is present on this cs, get the test addr - // - if (NBPtr->GetSysAddr (NBPtr, ChipSel, &(SweepPtr->TestAddrRJ16[CsIndex]))) { - if (!(NBPtr->MCTPtr->Status[SbLrdimms]) || ((NBPtr->ChannelPtr->LrDimmPresent & ((UINT8) 1 << (ChipSel >> 1))) != 0)) { - BanksPresent = TRUE; - SweepPtr->CsAddrValid[CsIndex] = TRUE; - // - /// If this is a Read Dqs sweep, Write the pattern now. - // - if (TechPtr->Direction == DQS_READ_DIR) { - IDS_HDT_CONSOLE (MEM_FLOW, "\tTestAddr: %x0000\n", SweepPtr->TestAddrRJ16[CsIndex]); - NBPtr->WritePattern (NBPtr, SweepPtr->TestAddrRJ16[CsIndex], TechPtr->PatternBufPtr, TechPtr->PatternLength); - } - } - } else { - SweepPtr->CsAddrValid[CsIndex] = FALSE; - } - } /// End Chip Select Loop - TechPtr->ChipSel = TechPtr->ChipSel - CsIndex; - // - /// return FALSE if no ChipSelects present. - // - return BanksPresent; -} - -/* -----------------------------------------------------------------------------*/ -/** - * Test Conditions for exiting the training loop, set the next delay value, - * and return status - * - * @param[in,out] *TechPtr - Pointer to the MEM_TECH_BLOCK - * @param[in,out] *SweepPtr - Pointer to SWEEP_INFO structure. - * - * @return BOOLEAN - * TRUE - Continue to test with next delay setting - * FALSE - Exit training loop. Either the result has been found or - * end of delay range has been reached. -*/ -BOOLEAN -STATIC -MemTContinueSweep ( - IN OUT MEM_TECH_BLOCK *TechPtr, - IN OUT SWEEP_INFO *SweepPtr - ) -{ - BOOLEAN Status; - Status = FALSE; - if (SweepPtr->ResultFound != 0xFFFF) { - Status = MemTSetNextDelay (TechPtr, SweepPtr); - } - return Status; -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * This function sets the next delay value for each bytelane that needs to - * be advanced. It checks the bounds of the delay to see if we are at the - * end of the range. If we are to close to advance a whole step value, but - * not at the boundary, then we set the delay to the boundary. - * - * @param[in,out] *TechPtr - Pointer to the MEM_TECH_BLOCK - * @param[in,out] *SweepPtr - Pointer to SWEEP_INFO structure. - * - */ - -BOOLEAN -STATIC -MemTSetNextDelay ( - IN OUT MEM_TECH_BLOCK *TechPtr, - IN OUT SWEEP_INFO *SweepPtr - ) -{ - DIE_STRUCT *MCTPtr; - UINT8 i; - - MCTPtr = TechPtr->NBPtr->MCTPtr; - // - ///< Loop through bytelanes - // - for (i = 0; i < ((MCTPtr->Status[SbEccDimms] && TechPtr->NBPtr->IsSupported[EccByteTraining]) ? 9 : 8) ; i++) { - // - /// Skip Bytelanes that have already reached the desired result - // - if ( (SweepPtr->ResultFound & ((UINT16)1 << i)) == 0) { - // - /// If a bytelane has reached the end, flag an error and exit - // - if (SweepPtr->TrnDelays[i] == SweepPtr->EndDelay) { - if ((SweepPtr->EndResult & ((UINT16) (1 << i))) != 0) { - MCTPtr->ErrStatus[EsbNoDqsPos] = TRUE; - SweepPtr->Error = TRUE; - } - return FALSE; - } - // - /// If the Current delay value is less than a step away from EndDelay, - // - if ( ABS (SweepPtr->EndDelay - SweepPtr->TrnDelays[i]) < ABS (SweepPtr->Step)) { - /// set to EndDelay. - // - SweepPtr->TrnDelays[i] = SweepPtr->EndDelay; - } else { - // - /// Otherwise, add the step value to it - SweepPtr->TrnDelays[i] = SweepPtr->TrnDelays[i] + SweepPtr->Step; - } - // - /// Set InsertionDelayMsk bit if Delay < 0 for this bytelane - // - if (SweepPtr->TrnDelays[i] < 0) { - SweepPtr->InsertionDelayMsk |= ((UINT16) 1 << i); - } else { - SweepPtr->InsertionDelayMsk &= ~((UINT16) 1 << i); - } - // - /// Write the scaled value to the Delay Register - // - TechPtr->SetDQSDelayCSR (TechPtr, i, MemTScaleDelayVal (TechPtr, SweepPtr->TrnDelays[i])); - } - } - return TRUE; -} -/* -----------------------------------------------------------------------------*/ -/** - * - * This function accepts a delay value in 32nd of a UI and converts it to an - * actual register value, taking into consideration NB type, rd/wr, - * and frequency. - * - * Delay = (Min + (Delay * ( (Max - Min) / TRN_DELAY_MAX) )) & Mask - * - * @param[in,out] *TechPtr - Pointer to the MEM_TECH_BLOCK - * @param[in] *Delay - INT8 of delay value; - * - * @return UINT8 of the adjusted delay value -*/ -UINT8 -STATIC -MemTScaleDelayVal ( - IN OUT MEM_TECH_BLOCK *TechPtr, - IN INT8 Delay - ) -{ - MEM_NB_BLOCK *NBPtr; - TRN_DLY_PARMS Parms; - TRN_DLY_TYPE DelayType; - UINT8 NewDelay; - INT8 Factor; - INT8 ScaledDelay; - - NBPtr = TechPtr->NBPtr; - // - // Determine Delay Type, Get Delay Parameters, and return scaled Delay value - // - DelayType = (TechPtr->Direction == DQS_WRITE_DIR) ? AccessWrDatDly : AccessRdDqsDly; - NBPtr->GetTrainDlyParms (NBPtr, DelayType, &Parms); - Factor = ((Parms.Max - Parms.Min) / TRN_DELAY_MAX); - ScaledDelay = Delay * Factor; - NewDelay = (Parms.Min + ScaledDelay) & Parms.Mask; - return NewDelay; -} - - - - - -/* -----------------------------------------------------------------------------*/ -/** - * - * This function calculates the Center of the Data eye for the specified byte lane - * and stores its DQS Delay value for reference. - * - * @param[in,out] *TechPtr - Pointer to the MEM_TECH_BLOCK - * @param[in,out] *SweepPtr - Pointer to SWEEP_INFO structure. - * @param[in] ByteLane - Bytelane number being targeted - * - */ -BOOLEAN -STATIC -MemTDataEyeSave ( - IN OUT MEM_TECH_BLOCK *TechPtr, - IN OUT SWEEP_INFO *SweepPtr, - IN UINT8 ByteLane - ) -{ - MEM_NB_BLOCK *NBPtr; - UINT8 EyeCenter; - UINT8 DlyMin; - UINT8 DlyMax; - UINT8 EyeWidth; - UINT8 Dimm; - CH_DEF_STRUCT *ChanPtr; - - NBPtr = TechPtr->NBPtr; - ChanPtr = NBPtr->ChannelPtr; - - ASSERT (ByteLane < ((NBPtr->MCTPtr->Status[SbEccDimms] && NBPtr->IsSupported[EccByteTraining]) ? 9 : 8)); - // - // Calculate Data Eye edges, Width, and Center in real terms. - // - if (TechPtr->Direction == DQS_READ_DIR) { - DlyMin = MemTScaleDelayVal (TechPtr, ChanPtr->RdDqsMinDlys[ByteLane]); - DlyMax = MemTScaleDelayVal (TechPtr, ChanPtr->RdDqsMaxDlys[ByteLane]); - EyeWidth = MemTScaleDelayVal (TechPtr, (ChanPtr->RdDqsMaxDlys[ByteLane] - ChanPtr->RdDqsMinDlys[ByteLane])); - EyeCenter = MemTScaleDelayVal (TechPtr, ((ChanPtr->RdDqsMinDlys[ByteLane] + ChanPtr->RdDqsMaxDlys[ByteLane] + 1) / 2)); - if (!NBPtr->FamilySpecificHook[RdDqsDlyRestartChk] (NBPtr, &EyeCenter)) { - return FALSE; - } - ChanPtr->RdDqsMinDlys[ByteLane] = DlyMin; - ChanPtr->RdDqsMaxDlys[ByteLane] = DlyMax; - NBPtr->FamilySpecificHook[ForceRdDqsPhaseB] (NBPtr, &EyeCenter); - } else { - DlyMin = MemTScaleDelayVal (TechPtr, ChanPtr->WrDatMinDlys[ByteLane]); - DlyMax = MemTScaleDelayVal (TechPtr, ChanPtr->WrDatMaxDlys[ByteLane]); - EyeWidth = MemTScaleDelayVal (TechPtr, (ChanPtr->WrDatMaxDlys[ByteLane] - ChanPtr->WrDatMinDlys[ByteLane])); - EyeCenter = MemTScaleDelayVal (TechPtr, ((ChanPtr->WrDatMinDlys[ByteLane] + ChanPtr->WrDatMaxDlys[ByteLane] + 1) / 2)); - ChanPtr->WrDatMinDlys[ByteLane] = DlyMin; - ChanPtr->WrDatMaxDlys[ByteLane] = DlyMax; - } - // - // Flag error for small window. - // - if (EyeWidth < MemTScaleDelayVal (TechPtr, NBPtr->MinDataEyeWidth (NBPtr))) { - TechPtr->SmallDqsPosWindow = TRUE; - SweepPtr->Error = TRUE; - } - - IDS_HDT_CONSOLE (MEM_FLOW, " %02x %02x %02x %02x", DlyMin, DlyMax, EyeWidth, EyeCenter); - - TechPtr->SetDQSDelayCSR (TechPtr, ByteLane, EyeCenter); - if (!SweepPtr->Error) { - TechPtr->DqsRdWrPosSaved |= (UINT8)1 << ByteLane; - } - TechPtr->DqsRdWrPosSaved |= 0xFE00; - - Dimm = (TechPtr->ChipSel / 2) * TechPtr->DlyTableWidth () + ByteLane; - if (TechPtr->Direction == DQS_READ_DIR) { - ChanPtr->RdDqsDlys[Dimm] = EyeCenter; - } else { - ChanPtr->WrDatDlys[Dimm] = EyeCenter + ChanPtr->WrDqsDlys[Dimm]; - } - - return TRUE; -} - diff --git a/src/vendorcode/amd/agesa/f12/Proc/Mem/Tech/mttEdgeDetect.h b/src/vendorcode/amd/agesa/f12/Proc/Mem/Tech/mttEdgeDetect.h deleted file mode 100644 index 590eafde1f..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/Mem/Tech/mttEdgeDetect.h +++ /dev/null @@ -1,117 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * mttEdgeDetect.h - * - * Technology Common Training Header file - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: (Mem) - * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $ - * - **/ -/***************************************************************************** - * - * Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * *************************************************************************** - * - */ - -#ifndef _MTTEDGEDETECT_H_ -#define _MTTEDGEDETECT_H_ - -/*---------------------------------------------------------------------------- - * Mixed (DEFINITIONS AND MACROS / TYPEDEFS, STRUCTURES, ENUMS) - * - *---------------------------------------------------------------------------- - */ - -/*----------------------------------------------------------------------------- - * DEFINITIONS AND MACROS - * - *----------------------------------------------------------------------------- - */ - - -#define SCAN_LEFT 0 ///< Scan Down -#define SCAN_RIGHT 1 ///< Scan Up -#define LEFT_EDGE 0 ///< searching for the left edge -#define RIGHT_EDGE 1 ///< searching for the right edge - -#define SweepStages 4 -#define TRN_DELAY_MAX 31 ///< Max Virtual delay value for DQS Position Training - -/*---------------------------------------------------------------------------- - * TYPEDEFS, STRUCTURES, ENUMS - * - *---------------------------------------------------------------------------- - */ - -/** - * Sweep Table Structure. ROM based table defining parameters for DQS position - * training delay sweep. -*/ -typedef struct { - INT8 BeginDelay; ///< Starting Delay Value - INT8 EndDelay; ///< Ending Delay Value - BOOLEAN ScanDir; ///< Scan Direction. 0 = down, 1 = up - INT8 Step; ///< Amount to increment delay value - UINT16 EndResult; ///< Result value to stop sweeping (to compare with failure mask) - BOOLEAN MinMax; ///< Flag indicating lower (left edge) or higher(right edge) -} DQS_POS_SWEEP_TABLE; - -/** - * Sweep Information Struct - Used to track data through the DQS Delay Sweep - * -*/ -typedef struct _SWEEP_INFO { - BOOLEAN Error; ///< Indicates an Error has been found - UINT32 TestAddrRJ16[MAX_CS_PER_CHANNEL]; ///< System address of chipselects RJ 16 bits (Addr[47:16]) - BOOLEAN CsAddrValid[MAX_CS_PER_CHANNEL]; ///< Indicates which chipselects to test - INT8 BeginDelay; ///< Beginning Delay value (Virtual) - INT8 EndDelay; ///< Ending Delay value (Virtual) - INT8 Step; ///< Amount to Inc or Dec Virtual Delay value - BOOLEAN Edge; ///< Left or right edge (0 = LEFT, 1= RIGHT) - UINT16 EndResult; ///< Result value that will stop a Dqs Sweep - UINT16 InsertionDelayMsk; ///< Mask of Byte Lanes that should use ins. dly. comparison - UINT16 LaneMsk; ///< Mask indicating byte lanes to update - UINT16 ResultFound; ///< Mask indicating byte lanes where desired result was found on a sweep - INT8 *TrnDelays; ///< Delay Values for each byte (Virtual). Points into the delay values -} SWEEP_INFO; ///< stored in the CH_DEF_STRUCT. - -/*---------------------------------------------------------------------------- - * FUNCTIONS PROTOTYPE - * - *---------------------------------------------------------------------------- - */ - - - -#endif /* _MTTEDGEDETECT_H_ */ - - diff --git a/src/vendorcode/amd/agesa/f12/Proc/Mem/Tech/mttdimbt.c b/src/vendorcode/amd/agesa/f12/Proc/Mem/Tech/mttdimbt.c deleted file mode 100644 index 480cc5c0f4..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/Mem/Tech/mttdimbt.c +++ /dev/null @@ -1,1330 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * mttdimmbt.c - * - * Technology Dimm Based Training - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: (Mem/Tech) - * @e \$Revision: 45101 $ @e \$Date: 2011-01-13 00:59:16 +0800 (Thu, 13 Jan 2011) $ - * - **/ -/***************************************************************************** -* -* Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* *************************************************************************** -* -*/ - -/* - *---------------------------------------------------------------------------- - * MODULES USED - * - *---------------------------------------------------------------------------- - */ - - - -#include "AGESA.h" -#include "Ids.h" -#include "mm.h" -#include "mn.h" -#include "mu.h" -#include "mt.h" -#include "GeneralServices.h" -#include "heapManager.h" -#include "Filecode.h" -CODE_GROUP (G1_PEICC) -RDATA_GROUP (G1_PEICC) - -#define FILECODE PROC_MEM_TECH_MTTDIMBT_FILECODE - -/*---------------------------------------------------------------------------- - * DEFINITIONS AND MACROS - * - *---------------------------------------------------------------------------- - */ -#define MAX_BYTELANES 8 /* 8 byte lanes */ -#define MAX_DELAYS 9 /* 8 data bytes + 1 ECC byte */ -#define MAX_DIMMS 4 /* 4 DIMMs per channel */ - -/*---------------------------------------------------------------------------- - * TYPEDEFS AND STRUCTURES - * - *---------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------- - * PROTOTYPES OF LOCAL FUNCTIONS - * - *---------------------------------------------------------------------------- - */ - -VOID -STATIC -MemTInitDqsPos4RcvrEnByte ( - IN OUT MEM_TECH_BLOCK *TechPtr - ); - -VOID -STATIC -MemTSetRcvrEnDlyByte ( - IN OUT MEM_TECH_BLOCK *TechPtr, - IN UINT8 Receiver, - IN UINT16 RcvEnDly - ); - -VOID -STATIC -MemTLoadRcvrEnDlyByte ( - IN OUT MEM_TECH_BLOCK *TechPtr, - IN UINT8 Receiver - ); - -BOOLEAN -STATIC -MemTSaveRcvrEnDlyByte ( - IN OUT MEM_TECH_BLOCK *TechPtr, - IN UINT8 Receiver, - IN UINT16 RcvEnDly, - IN UINT16 CmpResultRank0, - IN UINT16 CmpResultRank1 - ); - -VOID -STATIC -MemTResetDctWrPtrByte ( - IN OUT MEM_TECH_BLOCK *TechPtr, - IN UINT8 Receiver - ); - -UINT16 -STATIC -MemTCompare1ClPatternByte ( - IN OUT MEM_TECH_BLOCK *TechPtr, - IN UINT8 Buffer[], - IN UINT8 Pattern[] - ); - -VOID -STATIC -MemTSkipChipSelPass1Byte ( - IN OUT MEM_TECH_BLOCK *TechPtr, - IN OUT UINT8 *ChipSelPtr - ); - -VOID -STATIC -MemTSkipChipSelPass2Byte ( - IN OUT MEM_TECH_BLOCK *TechPtr, - IN OUT UINT8 *ChipSelPtr - ); - -UINT8 -STATIC -MemTMaxByteLanesByte (VOID); - -UINT8 -STATIC -MemTDlyTableWidthByte (VOID); - -VOID -STATIC -MemTSetDqsDelayCsrByte ( - IN OUT MEM_TECH_BLOCK *TechPtr, - IN UINT8 ByteLane, - IN UINT8 Dly - ); - -VOID -STATIC -MemTDqsWindowSaveByte ( - IN OUT MEM_TECH_BLOCK *TechPtr, - IN UINT8 ByteLane, - IN UINT8 DlyMin, - IN UINT8 DlyMax - ); - -BOOLEAN -STATIC -MemTFindMaxRcvrEnDlyByte ( - IN OUT MEM_TECH_BLOCK *TechPtr, - OUT UINT8 *ChipSel - ); - -UINT16 -STATIC -MemTCompare1ClPatternOptByte ( - IN OUT MEM_TECH_BLOCK *TechPtr, - IN UINT8 Buffer[], - IN UINT8 Pattern[], - IN UINT8 Side, - IN UINT8 Receiver, - IN BOOLEAN Side1En - ); - -VOID -STATIC -MemTLoadRcvrEnDlyOptByte ( - IN OUT MEM_TECH_BLOCK *TechPtr, - IN UINT8 Receiver - ); - -VOID -STATIC -MemTSetRcvrEnDlyOptByte ( - IN OUT MEM_TECH_BLOCK *TechPtr, - IN UINT8 Receiver, - IN UINT16 RcvEnDly - ); - -VOID -STATIC -MemTLoadInitialRcvEnDlyOptByte ( - IN OUT MEM_TECH_BLOCK *TechPtr, - IN UINT8 Receiver - ); - -UINT8 -STATIC -MemTFindMinMaxGrossDlyByte ( - IN OUT MEM_TECH_BLOCK *TechPtr, - IN TRN_DLY_TYPE TrnDlyType, - IN BOOLEAN IfMax - ); -/*---------------------------------------------------------------------------- - * EXPORTED FUNCTIONS - * - *---------------------------------------------------------------------------- - */ - - -/* -----------------------------------------------------------------------------*/ -/** - * - * This function enables byte based training if called - * - * @param[in,out] *TechPtr - Pointer to the MEM_TECH_BLOCK - * - */ - -VOID -MemTDimmByteTrainInit ( - IN OUT MEM_TECH_BLOCK *TechPtr - ) -{ - UINT8 Dct; - UINT8 Channel; - UINT8 DctCount; - UINT8 ChannelCount; - DIE_STRUCT *MCTPtr; - ALLOCATE_HEAP_PARAMS AllocHeapParams; - MEM_NB_BLOCK *NBPtr; - - NBPtr = TechPtr->NBPtr; - MCTPtr = NBPtr->MCTPtr; - - TechPtr->InitDQSPos4RcvrEn = MemTInitDqsPos4RcvrEnByte; - TechPtr->SetRcvrEnDly = MemTSetRcvrEnDlyByte; - TechPtr->LoadRcvrEnDly = MemTLoadRcvrEnDlyByte; - TechPtr->SaveRcvrEnDly = MemTSaveRcvrEnDlyByte; - TechPtr->SaveRcvrEnDlyFilter = MemTSaveRcvrEnDlyByteFilterOpt; - TechPtr->ResetDCTWrPtr = MemTResetDctWrPtrByte; - TechPtr->Compare1ClPattern = MemTCompare1ClPatternByte; - TechPtr->SkipChipSelPass1 = MemTSkipChipSelPass1Byte; - TechPtr->SkipChipSelPass2 = MemTSkipChipSelPass2Byte; - TechPtr->MaxByteLanes = MemTMaxByteLanesByte; - TechPtr->DlyTableWidth = MemTDlyTableWidthByte; - TechPtr->SetDQSDelayCSR = MemTSetDqsDelayCsrByte; - TechPtr->DQSWindowSave = MemTDqsWindowSaveByte; - TechPtr->FindMaxDlyForMaxRdLat = MemTFindMaxRcvrEnDlyByte; - TechPtr->Compare1ClPatternOpt = MemTCompare1ClPatternOptByte; - TechPtr->LoadRcvrEnDlyOpt = MemTLoadRcvrEnDlyOptByte; - TechPtr->SetRcvrEnDlyOpt = MemTSetRcvrEnDlyOptByte; - TechPtr->InitializeVariablesOpt = MemTInitializeVariablesOptByte; - TechPtr->GetMaxValueOpt = MemTGetMaxValueOptByte; - TechPtr->SetSweepErrorOpt = MemTSetSweepErrorOptByte; - TechPtr->CheckRcvrEnDlyLimitOpt = MemTCheckRcvrEnDlyLimitOptByte; - TechPtr->LoadInitialRcvrEnDlyOpt = MemTLoadInitialRcvEnDlyOptByte; - TechPtr->GetMinMaxGrossDly = MemTFindMinMaxGrossDlyByte; - // Dynamically allocate buffers for storing trained timings. - DctCount = MCTPtr->DctCount; - ChannelCount = MCTPtr->DctData[0].ChannelCount; - AllocHeapParams.RequestedBufferSize = ((DctCount * ChannelCount) * - ((MAX_DIMMS * MAX_DELAYS * NUMBER_OF_DELAY_TABLES) + - (MAX_DELAYS * MAX_CS_PER_CHANNEL * NUMBER_OF_FAILURE_MASK_TABLES) - ) - ); - AllocHeapParams.BufferHandle = GENERATE_MEM_HANDLE (ALLOC_TRN_DATA_HANDLE, MCTPtr->NodeId, 0, 0); - AllocHeapParams.Persist = HEAP_LOCAL_CACHE; - if (HeapAllocateBuffer (&AllocHeapParams, &NBPtr->MemPtr->StdHeader) == AGESA_SUCCESS) { - for (Dct = 0; Dct < DctCount; Dct++) { - for (Channel = 0; Channel < ChannelCount; Channel++) { - MCTPtr->DctData[Dct].ChData[Channel].RowCount = MAX_DIMMS; - MCTPtr->DctData[Dct].ChData[Channel].ColumnCount = MAX_DELAYS; - - MCTPtr->DctData[Dct].ChData[Channel].RcvEnDlys = (UINT16 *) AllocHeapParams.BufferPtr; - AllocHeapParams.BufferPtr += (MAX_DIMMS * MAX_DELAYS) * 2; - MCTPtr->DctData[Dct].ChData[Channel].WrDqsDlys = AllocHeapParams.BufferPtr; - AllocHeapParams.BufferPtr += (MAX_DIMMS * MAX_DELAYS); - MCTPtr->DctData[Dct].ChData[Channel].RdDqsDlys = AllocHeapParams.BufferPtr; - AllocHeapParams.BufferPtr += (MAX_DIMMS * MAX_DELAYS); - MCTPtr->DctData[Dct].ChData[Channel].WrDatDlys = AllocHeapParams.BufferPtr; - AllocHeapParams.BufferPtr += (MAX_DIMMS * MAX_DELAYS); - MCTPtr->DctData[Dct].ChData[Channel].RdDqsMinDlys = AllocHeapParams.BufferPtr; - AllocHeapParams.BufferPtr += (MAX_DIMMS * MAX_DELAYS); - MCTPtr->DctData[Dct].ChData[Channel].RdDqsMaxDlys = AllocHeapParams.BufferPtr; - AllocHeapParams.BufferPtr += (MAX_DIMMS * MAX_DELAYS); - MCTPtr->DctData[Dct].ChData[Channel].WrDatMinDlys = AllocHeapParams.BufferPtr; - AllocHeapParams.BufferPtr += (MAX_DIMMS * MAX_DELAYS); - MCTPtr->DctData[Dct].ChData[Channel].WrDatMaxDlys = AllocHeapParams.BufferPtr; - AllocHeapParams.BufferPtr += (MAX_DIMMS * MAX_DELAYS); - MCTPtr->DctData[Dct].ChData[Channel].FailingBitMask = AllocHeapParams.BufferPtr; - AllocHeapParams.BufferPtr += (MAX_CS_PER_CHANNEL * MAX_DELAYS); - } - } - } else { - PutEventLog (AGESA_FATAL, MEM_ERROR_HEAP_ALLOCATE_DYN_STORING_OF_TRAINED_TIMINGS, NBPtr->Node, NBPtr->Dct, NBPtr->Channel, 0, &NBPtr->MemPtr->StdHeader); - SetMemError (AGESA_FATAL, MCTPtr); - ASSERT(FALSE); // Could not dynamically allocate buffers for storing trained timings - } -} - - -/* -----------------------------------------------------------------------------*/ -/** - * - * This function initializes the DQS Positions in preparation for Receiver Enable Training. - * Write Position is no delay, Read Position is 1/2 Memclock delay - * - * @param[in,out] *TechPtr - Pointer to the MEM_TECH_BLOCK - * - */ - -VOID -STATIC -MemTInitDqsPos4RcvrEnByte ( - IN OUT MEM_TECH_BLOCK *TechPtr - ) -{ - UINT8 Dimm; - UINT8 ByteLane; - UINT8 WrDqs; - - for (Dimm = 0; Dimm < MAX_DIMMS_PER_CHANNEL; Dimm++) { - for (ByteLane = 0; ByteLane < MAX_DELAYS; ByteLane++) { - WrDqs = TechPtr->NBPtr->ChannelPtr->WrDqsDlys[(Dimm * MAX_DELAYS) + ByteLane]; - TechPtr->NBPtr->SetTrainDly (TechPtr->NBPtr, AccessWrDatDly, DIMM_BYTE_ACCESS (Dimm, ByteLane), WrDqs); - TechPtr->NBPtr->SetTrainDly (TechPtr->NBPtr, AccessRdDqsDly, DIMM_BYTE_ACCESS (Dimm, ByteLane), 0x3F); - } - } -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * This function programs DqsRcvEnDly to additional index for DQS receiver enabled training - * - * @param[in,out] *TechPtr - Pointer to the MEM_TECH_BLOCK - * @param[in] Receiver - Current Chip select value - * @param[in] RcvEnDly - receiver enable delay to be saved - */ - -VOID -STATIC -MemTSetRcvrEnDlyByte ( - IN OUT MEM_TECH_BLOCK *TechPtr, - IN UINT8 Receiver, - IN UINT16 RcvEnDly - ) -{ - UINT8 ByteLane; - - ASSERT (Receiver < MAX_CS_PER_CHANNEL); - for (ByteLane = 0; ByteLane < MAX_BYTELANES; ByteLane++) { - TechPtr->NBPtr->SetTrainDly (TechPtr->NBPtr, AccessRcvEnDly, DIMM_BYTE_ACCESS (Receiver >> 1, ByteLane), RcvEnDly); - } -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * This function loads the DqsRcvEnDly from saved data and program to additional index - * for DQS receiver enabled training - * - * @param[in,out] *TechPtr - Pointer to the MEM_TECH_BLOCK - * @param[in] Receiver - Current Chip select value - * - */ - -VOID -STATIC -MemTLoadRcvrEnDlyByte ( - IN OUT MEM_TECH_BLOCK *TechPtr, - IN UINT8 Receiver - ) -{ - UINT8 i; - UINT8 Dimm; - UINT16 Saved; - CH_DEF_STRUCT *ChannelPtr; - - ASSERT (Receiver < MAX_CS_PER_CHANNEL); - ChannelPtr = TechPtr->NBPtr->ChannelPtr; - - Dimm = Receiver >> 1; - Saved = TechPtr->DqsRcvEnSaved; - for (i = 0; i < MAX_BYTELANES; i++) { - if (Saved & 1) { - TechPtr->NBPtr->SetTrainDly (TechPtr->NBPtr, AccessRcvEnDly, DIMM_BYTE_ACCESS (Receiver >> 1, i), - ChannelPtr->RcvEnDlys[Dimm * MAX_DELAYS + i]); - } - Saved >>= 1; - } -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * This function saves passing DqsRcvEnDly values to the stack - * - * @param[in,out] *TechPtr - Pointer to the MEM_TECH_BLOCK - * @param[in] Receiver - Current Chip select value - * @param[in] RcvEnDly - receiver enable delay to be saved - * @param[in] CmpResultRank0 - compare result for Rank 0 - * @param[in] CmpResultRank1 - compare result for Rank 1 - * - * @return TRUE - All bytelanes pass - * @return FALSE - Some bytelanes fail - */ - -BOOLEAN -STATIC -MemTSaveRcvrEnDlyByte ( - IN OUT MEM_TECH_BLOCK *TechPtr, - IN UINT8 Receiver, - IN UINT16 RcvEnDly, - IN UINT16 CmpResultRank0, - IN UINT16 CmpResultRank1 - ) -{ - UINT8 i; - UINT8 Passed; - UINT8 Saved; - UINT8 Mask; - UINT8 Dimm; - CH_DEF_STRUCT *ChannelPtr; - - ASSERT (Receiver < MAX_CS_PER_CHANNEL); - ChannelPtr = TechPtr->NBPtr->ChannelPtr; - - Passed = (UINT8) ((CmpResultRank0 & CmpResultRank1) & 0xFF); - - Saved = (UINT8) (TechPtr->DqsRcvEnSaved & Passed); //@attention - false passes filter (subject to be replaced with a better solution) - Dimm = Receiver >> 1; - Mask = 1; - for (i = 0; i < MAX_BYTELANES; i++) { - if (Passed & Mask) { - if (!(Saved & Mask)) { - ChannelPtr->RcvEnDlys[Dimm * MAX_DELAYS + i] = RcvEnDly + 0x20; // @attention -1 pass only - IDS_HDT_CONSOLE (MEM_FLOW, "\t\t\tBL %d = %02x", i, RcvEnDly + 0x20); - } - Saved |= Mask; - } - Mask <<= 1; - } - TechPtr->DqsRcvEnSaved = Saved; - - if (Saved == 0xFF) { - return TRUE; - } else { - return FALSE; - } -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * This function performs a filtering functionality and saves passing DqsRcvEnDly - * values to the stack - * - * @param[in,out] *TechPtr - Pointer to the MEM_TECH_BLOCK - * @param[in] Receiver - Current Chip select value - * @param[in] RcvEnDly - receiver enable delay to be saved - * @param[in] CmpResultRank0 - compare result for Rank 0 - * @param[in] CmpResultRank1 - compare result for Rank 1 - * - * @return TRUE - All bytelanes pass - * @return FALSE - Some bytelanes fail - */ - -BOOLEAN -MemTSaveRcvrEnDlyByteFilter ( - IN OUT MEM_TECH_BLOCK *TechPtr, - IN UINT8 Receiver, - IN UINT16 RcvEnDly, - IN UINT16 CmpResultRank0, - IN UINT16 CmpResultRank1 - ) -{ - UINT8 i; - UINT8 Passed; - UINT8 Saved; - UINT8 Mask; - UINT8 Dimm; - UINT8 MaxFilterDly; - CH_DEF_STRUCT *ChannelPtr; - MEM_DCT_CACHE *DctCachePtr; - - ASSERT (Receiver < MAX_CS_PER_CHANNEL); - ChannelPtr = TechPtr->NBPtr->ChannelPtr; - DctCachePtr = TechPtr->NBPtr->DctCachePtr; - - MaxFilterDly = TechPtr->MaxFilterDly; - Passed = (UINT8) ((CmpResultRank0 & CmpResultRank1) & 0xFF); - - Dimm = Receiver >> 1; - Saved = (UINT8) TechPtr->DqsRcvEnSaved; - Mask = 1; - for (i = 0; i < MAX_BYTELANES; i++) { - if ((Passed & Mask) != 0) { - DctCachePtr->RcvEnDlyCounts [i] += 1; - if ((Saved & Mask) == 0) { - ChannelPtr->RcvEnDlys[Dimm * MAX_DELAYS + i] = RcvEnDly + 0x20; - Saved |= Mask; - IDS_HDT_CONSOLE (MEM_FLOW, "\t\t\tBL %d = %02x", i, RcvEnDly + 0x20); - } - } else { - if (DctCachePtr->RcvEnDlyCounts [i] <= MaxFilterDly) { - DctCachePtr->RcvEnDlyCounts [i] = 0; - Saved &= ~Mask; - } - } - Mask <<= 1; - } - - //----------------------- - TechPtr->DqsRcvEnSaved = (UINT16) Saved; - - Saved = 0; - for (i = 0; i < MAX_BYTELANES; i++) { - if (DctCachePtr->RcvEnDlyCounts [i] >= MaxFilterDly) { - Saved |= (UINT8) 1 << i; - } - } - - if (Saved == 0xFF) { - return TRUE; - } else { - return FALSE; - } -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * This function compares test pattern with data in buffer and return a pass/fail bitmap - * for 8 Bytes - * - * @param[in,out] *TechPtr - Pointer to the MEM_TECH_BLOCK - * @param[in] Buffer[] - Buffer data from DRAM (Measured data from DRAM) to compare - * @param[in] Pattern[] - Pattern (Expected data in ROM/CACHE) to compare against - * - * @return PASS - Bit map of results of comparison - */ - -UINT16 -STATIC -MemTCompare1ClPatternByte ( - IN OUT MEM_TECH_BLOCK *TechPtr, - IN UINT8 Buffer[], - IN UINT8 Pattern[] - ) -{ - UINT16 i; - UINT16 j; - UINT16 Pass; - DIE_STRUCT *MCTPtr; - - MCTPtr = TechPtr->NBPtr->MCTPtr; - if (MCTPtr->GangedMode && MCTPtr->Dct) { - j = 8; - } else { - j = 0; - } - - Pass = 0xFFFF; - IDS_HDT_CONSOLE (MEM_FLOW, " -"); - for (i = 0; i < 8; i++) { - if (Buffer[j] != Pattern[j]) { - // if bytelane n fails - Pass &= ~((UINT16)1 << (j % 8)); // clear bit n - } - IDS_HDT_CONSOLE (MEM_FLOW, " %c", (Buffer[j] == Pattern[j]) ? 'P' : '.'); - j++; - } - - IDS_HDT_CONSOLE_DEBUG_CODE ( - IDS_HDT_CONSOLE (MEM_FLOW, "\n\t\t\t -"); - for (i = 0, j -= 8; i < 8; i++, j++) { - IDS_HDT_CONSOLE (MEM_FLOW, " %02x", Buffer[j]); - } - IDS_HDT_CONSOLE (MEM_FLOW, "\n\t\t\t -"); - for (i = 0, j -= 8; i < 8; i++, j++) { - IDS_HDT_CONSOLE (MEM_FLOW, " %02x", Pattern[j]); - } - IDS_HDT_CONSOLE (MEM_FLOW, "\n\n"); - ); - - return Pass; -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * The function resets the DCT input buffer write pointer. - * - * @param[in,out] *TechPtr - Pointer to the MEM_TECH_BLOCK - * @param[in] Receiver - Chip select - * - */ - -VOID -STATIC -MemTResetDctWrPtrByte ( - IN OUT MEM_TECH_BLOCK *TechPtr, - IN UINT8 Receiver - ) -{ - UINT8 i; - UINT16 RcvEnDly; - - ASSERT (Receiver < MAX_CS_PER_CHANNEL); - for (i = 0; i < MAX_BYTELANES; i++) { - RcvEnDly = (UINT16) TechPtr->NBPtr->GetTrainDly (TechPtr->NBPtr, AccessRcvEnDly, DIMM_BYTE_ACCESS (Receiver / 2, i)); - TechPtr->NBPtr->SetTrainDly (TechPtr->NBPtr, AccessRcvEnDly, DIMM_BYTE_ACCESS (Receiver / 2, i), RcvEnDly); - } -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * This function skips odd chip select if training at 800MT or above. - * - * @param[in,out] *TechPtr - Pointer to the MEM_TECH_BLOCK - * @param[in] *ChipSelPtr - Pointer to variable contains Chip select index - * - */ - -VOID -STATIC -MemTSkipChipSelPass1Byte ( - IN OUT MEM_TECH_BLOCK *TechPtr, - IN OUT UINT8 *ChipSelPtr - ) -{ - MEM_NB_BLOCK *NBPtr; - - NBPtr = TechPtr->NBPtr; - // if the even chip select failed training, need to set CsTrainFail for odd chip select if present. - if (NBPtr->DCTPtr->Timings.CsPresent & ((UINT16)1 << ((*ChipSelPtr) + 1))) { - if (NBPtr->DCTPtr->Timings.CsTrainFail & ((UINT16)1 << *ChipSelPtr)) { - NBPtr->DCTPtr->Timings.CsTrainFail |= (UINT16)1 << ((*ChipSelPtr) + 1); - NBPtr->MemPtr->ErrorHandling (NBPtr->MCTPtr, NBPtr->Dct, NBPtr->DCTPtr->Timings.CsTrainFail, &NBPtr->MemPtr->StdHeader); - } - } - (*ChipSelPtr)++; -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * MemTSkipChipSelPass2Byte: - * - * This function skips odd chip select if training at 800MT or above. - * - * @param[in,out] *TechPtr - Pointer to the MEM_TECH_BLOCK - * @param[in,out] *ChipSelPtr - Pointer to variable contains Chip select index - * - */ - -VOID -STATIC -MemTSkipChipSelPass2Byte ( - IN OUT MEM_TECH_BLOCK *TechPtr, - IN OUT UINT8 *ChipSelPtr - ) -{ - if (*ChipSelPtr & 1) { - *ChipSelPtr = MAX_CS_PER_CHANNEL; // skip all successions - } -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * This function determines the maximum number of byte lanes - * - * @return Max number of Bytelanes - */ - -UINT8 -STATIC -MemTMaxByteLanesByte (VOID) -{ - return MAX_BYTELANES; -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * This function determines the width of the delay tables (eg. RcvEnDlys, WrDqsDlys,...) - * - * @return Delay table width in bytes - */ - -UINT8 -STATIC -MemTDlyTableWidthByte (VOID) -{ - return MAX_DELAYS; -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * This function writes the Delay value to a certain byte lane - * - * @param[in,out] *TechPtr - Pointer to the MEM_TECH_BLOCK - * @param[in] ByteLane - Bytelane number being targeted - * @param[in] Dly - Delay value - * - */ - -VOID -STATIC -MemTSetDqsDelayCsrByte ( - IN OUT MEM_TECH_BLOCK *TechPtr, - IN UINT8 ByteLane, - IN UINT8 Dly - ) -{ - UINT8 Reg; - UINT8 Dimm; - - ASSERT (ByteLane <= MAX_BYTELANES); - - if (!(TechPtr->DqsRdWrPosSaved & ((UINT8)1 << ByteLane))) { - Dimm = (TechPtr->ChipSel >> 1); - - if (TechPtr->Direction == DQS_WRITE_DIR) { - Dly = Dly + ((UINT8) TechPtr->NBPtr->ChannelPtr->WrDqsDlys[(Dimm * MAX_DELAYS) + ByteLane]); - Reg = AccessWrDatDly; - } else { - Reg = AccessRdDqsDly; - } - - TechPtr->NBPtr->SetTrainDly (TechPtr->NBPtr, Reg, DIMM_BYTE_ACCESS (Dimm, ByteLane), Dly); - } -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * This function programs the trained DQS delay for the specified byte lane - * and stores its DQS window for reference. - * - * @param[in,out] *TechPtr - Pointer to the MEM_TECH_BLOCK - * @param[in] ByteLane - Bytelane number being targeted - * @param[in] DlyMin - Minimum delay value - * @param[in] DlyMax- Maximum delay value - * - */ - -VOID -STATIC -MemTDqsWindowSaveByte ( - IN OUT MEM_TECH_BLOCK *TechPtr, - IN UINT8 ByteLane, - IN UINT8 DlyMin, - IN UINT8 DlyMax - ) -{ - UINT8 DqsDelay; - UINT8 Dimm; - CH_DEF_STRUCT *ChanPtr; - - ASSERT (ByteLane <= MAX_BYTELANES); - ChanPtr = TechPtr->NBPtr->ChannelPtr; - - DqsDelay = ((DlyMin + DlyMax + 1) / 2) & 0x3F; - MemTSetDqsDelayCsrByte (TechPtr, ByteLane, DqsDelay); - TechPtr->DqsRdWrPosSaved |= (UINT8)1 << ByteLane; - TechPtr->DqsRdWrPosSaved |= 0xFF00; - - Dimm = (TechPtr->ChipSel / 2) * MAX_DELAYS + ByteLane; - if (TechPtr->Direction == DQS_READ_DIR) { - ChanPtr->RdDqsDlys[Dimm] = DqsDelay; - } else { - ChanPtr->WrDatDlys[Dimm] = DqsDelay + ChanPtr->WrDqsDlys[Dimm]; - } - - if (TechPtr->Direction == DQS_READ_DIR) { - ChanPtr->RdDqsMinDlys[ByteLane] = DlyMin; - ChanPtr->RdDqsMaxDlys[ByteLane] = DlyMax; - } else { - ChanPtr->WrDatMinDlys[ByteLane] = DlyMin; - ChanPtr->WrDatMaxDlys[ByteLane] = DlyMax; - } - -} - - -/* -----------------------------------------------------------------------------*/ -/** - * - * This function finds the DIMM that has the largest receiver enable delay. - * - * @param[in,out] *TechPtr - Pointer to the MEM_TECH_BLOCK - * @param[out] *ChipSel - Pointer to the Chip select that has the largest receiver enable delay. - * - * @return TRUE - A chip select can be found. - * @return FALSE - A chip select cannot be found. - */ - -BOOLEAN -STATIC -MemTFindMaxRcvrEnDlyByte ( - IN OUT MEM_TECH_BLOCK *TechPtr, - OUT UINT8 *ChipSel - ) -{ - UINT8 Dimm; - UINT8 ByteLane; - UINT16 RcvEnDly; - UINT16 MaxDly; - UINT8 MaxDlyDimm; - BOOLEAN RetVal; - - MEM_NB_BLOCK *NBPtr; - CH_DEF_STRUCT *ChannelPtr; - - NBPtr = TechPtr->NBPtr; - ChannelPtr = NBPtr->ChannelPtr; - - RetVal = FALSE; - MaxDly = 0; - MaxDlyDimm = 0; - for (Dimm = 0; Dimm < MAX_DIMMS_PER_CHANNEL; Dimm++) { - if ((NBPtr->DCTPtr->Timings.CsTrainFail & ((UINT16) 3 << (Dimm << 1))) == 0) { - // Only choose the dimm that does not fail training - for (ByteLane = 0; ByteLane < ((NBPtr->MCTPtr->Status[SbEccDimms] && NBPtr->IsSupported[EccByteTraining]) ? 9 : 8); ByteLane++) { - RcvEnDly = ChannelPtr->RcvEnDlys[Dimm * MAX_DELAYS + ByteLane]; - if (RcvEnDly > MaxDly) { - MaxDly = RcvEnDly; - MaxDlyDimm = Dimm; - RetVal = TRUE; - } - } - } - } - - if (NBPtr->MCTPtr->Status[Sb128bitmode] != 0) { - //The RcvrEnDlys of DCT1 DIMMs should also be considered while ganging. - NBPtr->SwitchDCT (NBPtr, 1); - ChannelPtr = NBPtr->ChannelPtr; - for (Dimm = 0; Dimm < MAX_DIMMS_PER_CHANNEL; Dimm++) { - for (ByteLane = 0; ByteLane < ((NBPtr->MCTPtr->Status[SbEccDimms] && NBPtr->IsSupported[EccByteTraining]) ? 9 : 8); ByteLane++) { - RcvEnDly = ChannelPtr->RcvEnDlys[Dimm * MAX_DELAYS + ByteLane]; - if (RcvEnDly > MaxDly) { - MaxDly = RcvEnDly; - MaxDlyDimm = Dimm; - } - } - } - NBPtr->SwitchDCT (NBPtr, 0); - } - - TechPtr->MaxDlyForMaxRdLat = MaxDly; - *ChipSel = (MaxDlyDimm * 2); - return RetVal; -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * This function finds the DIMM that has the largest receiver enable delay + Read DQS Delay. - * - * @param[in,out] *TechPtr - Pointer to the MEM_TECH_BLOCK - * @param[out] *ChipSel - Pointer to the Chip select that has the largest receiver enable delay - * + Read DQS Delay. - * - * @return TRUE - A chip select can be found. - * @return FALSE - A chip select cannot be found. - */ - -BOOLEAN -MemTFindMaxRcvrEnDlyRdDqsDlyByte ( - IN OUT MEM_TECH_BLOCK *TechPtr, - OUT UINT8 *ChipSel - ) -{ - UINT8 Dimm; - UINT8 ByteLane; - UINT16 RcvEnDly; - UINT16 RdDqsDly; - UINT16 TotalDly; - UINT16 MaxDly; - UINT8 MaxDlyDimm; - BOOLEAN RetVal; - - MEM_NB_BLOCK *NBPtr; - CH_DEF_STRUCT *ChannelPtr; - - NBPtr = TechPtr->NBPtr; - ChannelPtr = NBPtr->ChannelPtr; - - RetVal = FALSE; - MaxDly = 0; - MaxDlyDimm = 0; - for (Dimm = 0; Dimm < MAX_DIMMS_PER_CHANNEL; Dimm++) { - if ((NBPtr->DCTPtr->Timings.CsTrainFail & ((UINT16) 3 << (Dimm << 1))) == 0) { - // Only choose the dimm that does not fail training - for (ByteLane = 0; ByteLane < MAX_BYTELANES; ByteLane++) { - RcvEnDly = ChannelPtr->RcvEnDlys[Dimm * MAX_DELAYS + ByteLane]; - // Before Dqs Position Training, this value is 0. So the maximum value for - // RdDqsDly needs to be added later when calculating the MaxRdLatency value - // after RcvEnDly training but before DQS Position Training. - RdDqsDly = ChannelPtr->RdDqsDlys[Dimm * MAX_DELAYS + ByteLane]; - TotalDly = RcvEnDly + (RdDqsDly >> 1); - if (TotalDly > MaxDly) { - MaxDly = TotalDly; - MaxDlyDimm = Dimm; - RetVal = TRUE; - } - } - } - } - - TechPtr->MaxDlyForMaxRdLat = MaxDly; - *ChipSel = (MaxDlyDimm * 2); - return RetVal; -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * This function finds the minimum or maximum gross dly among all the bytes. - * - * @param[in,out] *TechPtr - Pointer to the MEM_TECH_BLOCK - * @param[in] TrnDlyType - Target Dly type - * @param[in] IfMax - If this is for maximum value or minimum - * - * @return minimum gross dly - */ -UINT8 -STATIC -MemTFindMinMaxGrossDlyByte ( - IN OUT MEM_TECH_BLOCK *TechPtr, - IN TRN_DLY_TYPE TrnDlyType, - IN BOOLEAN IfMax - ) -{ - UINT8 i; - UINT8 ByteLane; - UINT16 CsEnabled; - UINT8 MinMaxGrossDly; - UINT8 TrnDly; - MEM_NB_BLOCK *NBPtr; - - NBPtr = TechPtr->NBPtr; - CsEnabled = NBPtr->DCTPtr->Timings.CsEnabled; - MinMaxGrossDly = IfMax ? 0 : 0xFF; - - for (i = 0; i < MAX_DIMMS_PER_CHANNEL; i++) { - if ((CsEnabled & (UINT16) (3 << (i << 1))) != 0) { - for (ByteLane = 0; ByteLane < ((NBPtr->MCTPtr->Status[SbEccDimms] && NBPtr->IsSupported[EccByteTraining]) ? 9 : 8); ByteLane++) { - TrnDly = (UINT8) (GetTrainDlyFromHeapNb (NBPtr, TrnDlyType, DIMM_BYTE_ACCESS (i, ByteLane)) >> 5); - if ((IfMax && (TrnDly > MinMaxGrossDly)) || (!IfMax && (TrnDly < MinMaxGrossDly))) { - MinMaxGrossDly = TrnDly; - } - } - } - } - - return MinMaxGrossDly; -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * This function compares test pattern with data in buffer and return a pass/fail bitmap - * for 8 Bytes for optimized receiver enable training - * - * @param[in,out] *TechPtr - Pointer to the MEM_TECH_BLOCK - * @param[in] Buffer[] - Buffer data from DRAM (Measured data from DRAM) to compare - * @param[in] Pattern[] - Pattern (Expected data in ROM/CACHE) to compare against - * @param[in] Side - current side being targeted - * @param[in] Receiver - Current receiver value - * @param[in] Side1En - Indicates if the second side of the DIMM is being used - * @return PASS - Bit map of results of comparison - */ - -UINT16 -STATIC -MemTCompare1ClPatternOptByte ( - IN OUT MEM_TECH_BLOCK *TechPtr, - IN UINT8 Buffer[], - IN UINT8 Pattern[], - IN UINT8 Side, - IN UINT8 Receiver, - IN BOOLEAN Side1En - ) -{ - UINT16 i; - UINT16 j; - UINT16 Pass; - DIE_STRUCT *MCTPtr; - CH_DEF_STRUCT *ChannelPtr; - - ASSERT (Receiver < MAX_CS_PER_CHANNEL); - ChannelPtr = TechPtr->NBPtr->ChannelPtr; - MCTPtr = TechPtr->NBPtr->MCTPtr; - - if (MCTPtr->GangedMode && MCTPtr->Dct) { - j = 8; - } else { - j = 0; - } - - Pass = 0xFFFF; - IDS_HDT_CONSOLE (MEM_FLOW, "\t\t\tDelay[BL] -"); - for (i = 0; i < 8; i++) { - IDS_HDT_CONSOLE (MEM_FLOW, " %02x", TechPtr->RcvrEnDlyOpt[i] & 0xFF); - if (Buffer[j] != Pattern[j]) { - // if bytelane n fails - Pass &= ~((UINT16)1 << (j % 8)); // clear bit n - TechPtr->DqsRcvEnFirstPassValOpt[i] = 0; - TechPtr->GetFirstPassValOpt[i] = FALSE; - TechPtr->IncBy1ForNextCountOpt[i] = FALSE; - TechPtr->DqsRcvEnSavedOpt[i] = FALSE; - if (TechPtr->FilterStatusOpt[i] != DONE_FILTER) { - if (Side == ((Side1En ? 4 : 2) - 1)) { - TechPtr->RcvrEnDlyOpt[i] += FILTER_FIRST_STAGE_COUNT; - } - } - } else { - if (TechPtr->FilterSidePassCountOpt[i] == ((Side1En ? 4 : 2) - 1)) { - //Only apply filter if all sides have passed - if (TechPtr->FilterStatusOpt[i] != DONE_FILTER) { - if (TechPtr->GetFirstPassValOpt[i] == FALSE) { - // This is the first Pass, mark the start of filter check - TechPtr->DqsRcvEnFirstPassValOpt[i] = TechPtr->RcvrEnDlyOpt[i]; - TechPtr->GetFirstPassValOpt[i] = TRUE; - TechPtr->IncBy1ForNextCountOpt[i] = FALSE; - TechPtr->RcvrEnDlyOpt[i]++; - } else { - if ((TechPtr->RcvrEnDlyOpt[i] - TechPtr->DqsRcvEnFirstPassValOpt[i]) < FILTER_WINDOW_SIZE) { - if (TechPtr->IncBy1ForNextCountOpt[i] == FALSE) { - TechPtr->RcvrEnDlyOpt[i] += FILTER_SECOND_STAGE_COUNT; - TechPtr->IncBy1ForNextCountOpt[i] = TRUE; - } else { - TechPtr->RcvrEnDlyOpt[i]++; - TechPtr->IncBy1ForNextCountOpt[i] = FALSE; - } - } else { - // End sweep and add offset to first pass - TechPtr->MaxRcvrEnDlyBlOpt[i] = TechPtr->DqsRcvEnFirstPassValOpt[i]; - TechPtr->RcvrEnDlyOpt[i] = TechPtr->DqsRcvEnFirstPassValOpt[i] + FILTER_OFFSET_VALUE; - TechPtr->FilterStatusOpt[i] = DONE_FILTER; - TechPtr->FilterCountOpt++; - } - } - } else { - TechPtr->FilterSidePassCountOpt[i]++; - } - } else { - if (TechPtr->GetFirstPassValOpt[i] == FALSE) { - if (Side == ((Side1En ? 4 : 2) - 1)) { - TechPtr->RcvrEnDlyOpt[i] += FILTER_FIRST_STAGE_COUNT; - } - } - TechPtr->FilterSidePassCountOpt[i]++; - } - TechPtr->DqsRcvEnSavedOpt[i] = TRUE; - ChannelPtr->RcvEnDlys[(Receiver >> 1) * MAX_DELAYS + i] = TechPtr->RcvrEnDlyOpt[i]; - } - if (Side == ((Side1En ? 4 : 2) - 1)) { - TechPtr->FilterSidePassCountOpt[i] = 0; - } - if (TechPtr->RcvrEnDlyOpt[i] >= TechPtr->RcvrEnDlyLimitOpt[i]) { - TechPtr->FilterCountOpt++; - } - - j++; - } - - IDS_HDT_CONSOLE_DEBUG_CODE ( - IDS_HDT_CONSOLE (MEM_FLOW, "\n\t\t\tPass/Fail -"); - for (i = 0, j -= 8; i < 8; i++, j++) { - IDS_HDT_CONSOLE (MEM_FLOW, " %c", (Buffer[j] == Pattern[j]) ? 'P' : '.'); - } - IDS_HDT_CONSOLE (MEM_FLOW, "\n\t\t\t Measured -"); - for (i = 0, j -= 8; i < 8; i++, j++) { - IDS_HDT_CONSOLE (MEM_FLOW, " %02x", Buffer[j]); - } - IDS_HDT_CONSOLE (MEM_FLOW, "\n\t\t\t Expected -"); - for (i = 0, j -= 8; i < 8; i++, j++) { - IDS_HDT_CONSOLE (MEM_FLOW, " %02x", Pattern[j]); - } - IDS_HDT_CONSOLE (MEM_FLOW, "\n\n"); - ); - - return Pass; -} -/*----------------------------------------------------------------------------- - * - * This function initializes variables for optimized training. - * - * @param[in,out] *TechPtr - Pointer to the MEM_TECH_BLOCK - * - * ---------------------------------------------------------------------------- - */ -VOID -MemTInitializeVariablesOptByte ( - IN OUT MEM_TECH_BLOCK *TechPtr - ) -{ - UINT8 ByteLane; - for (ByteLane = 0; ByteLane < MAX_BYTELANES_PER_CHANNEL; ByteLane++) { - TechPtr->RcvrEnDlyLimitOpt[ByteLane] = FILTER_MAX_REC_EN_DLY_VALUE; // @attention - limit depends on proc type - TechPtr->DqsRcvEnSavedOpt[ByteLane] = FALSE; - TechPtr->RcvrEnDlyOpt[ByteLane] = FILTER_NEW_RECEIVER_START_VALUE; - TechPtr->GetFirstPassValOpt[ByteLane] = FALSE; - TechPtr->DqsRcvEnFirstPassValOpt[ByteLane] = 0; - TechPtr->RevertPassValOpt[ByteLane] = FALSE; - TechPtr->MaxRcvrEnDlyBlOpt[ByteLane] = 0; - TechPtr->FilterStatusOpt[ByteLane] = START_FILTER; - TechPtr->FilterCountOpt = 0; - TechPtr->FilterSidePassCountOpt[ByteLane] = 0; - TechPtr->IncBy1ForNextCountOpt[ByteLane] = FALSE; - } -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * This function loads the DqsRcvEnDly from saved data and program to additional index - * for optimized DQS receiver enabled training - * - * @param[in,out] *TechPtr - Pointer to the MEM_TECH_BLOCK - * @param[in] Receiver - Current Chip select value - * - */ - -VOID -STATIC -MemTLoadRcvrEnDlyOptByte ( - IN OUT MEM_TECH_BLOCK *TechPtr, - IN UINT8 Receiver - ) -{ - UINT8 i; - UINT8 Dimm; - CH_DEF_STRUCT *ChannelPtr; - - ASSERT (Receiver < MAX_CS_PER_CHANNEL); - ChannelPtr = TechPtr->NBPtr->ChannelPtr; - - Dimm = Receiver >> 1; - for (i = 0; i < 8; i++) { - if (TechPtr->DqsRcvEnSavedOpt[i]) { - TechPtr->NBPtr->SetTrainDly (TechPtr->NBPtr, AccessRcvEnDly, DIMM_BYTE_ACCESS (Receiver >> 1, i), - ChannelPtr->RcvEnDlys[Dimm * MAX_DELAYS + i]); - } - } -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * This function programs DqsRcvEnDly to additional index for DQS receiver enabled training - * - * @param[in,out] *TechPtr - Pointer to the MEM_TECH_BLOCK - * @param[in] Receiver - Current Chip select value - * @param[in] RcvEnDly - receiver enable delay to be saved - */ - -VOID -STATIC -MemTSetRcvrEnDlyOptByte ( - IN OUT MEM_TECH_BLOCK *TechPtr, - IN UINT8 Receiver, - IN UINT16 RcvEnDly - ) -{ - UINT8 ByteLane; - - ASSERT (Receiver < MAX_CS_PER_CHANNEL); - - for (ByteLane = 0; ByteLane < 8; ByteLane++) { - if (TechPtr->FilterStatusOpt[ByteLane] != DONE_FILTER) { - TechPtr->NBPtr->SetTrainDly (TechPtr->NBPtr, AccessRcvEnDly, DIMM_BYTE_ACCESS (Receiver >> 1, ByteLane), TechPtr->RcvrEnDlyOpt[ByteLane]); - } - } -} -/*----------------------------------------------------------------------------- - * - * This sets any Errors generated from Dly sweep - * - * @param[in,out] *TechPtr - Pointer to the MEM_TECH_BLOCK - * @param[in] DCT - current DCT - * @param[in] Receiver - current receiver - * - * @return FALSE - Fatal error occurs. - * @return TRUE - No fatal error occurs. - * ---------------------------------------------------------------------------- - */ -BOOLEAN -MemTSetSweepErrorOptByte ( - IN OUT MEM_TECH_BLOCK *TechPtr, - IN UINT8 Receiver, - IN UINT8 Dct, - IN BOOLEAN ErrorCheck - ) -{ - UINT8 ByteLane; - MEM_DATA_STRUCT *MemPtr; - DIE_STRUCT *MCTPtr; - DCT_STRUCT *DCTPtr; - MEM_NB_BLOCK *NBPtr; - - NBPtr = TechPtr->NBPtr; - MemPtr = NBPtr->MemPtr; - MCTPtr = NBPtr->MCTPtr; - DCTPtr = NBPtr->DCTPtr; - for (ByteLane = 0; ByteLane < MAX_BYTELANES_PER_CHANNEL; ByteLane++) { - if (TechPtr->RcvrEnDlyOpt[ByteLane] == TechPtr->RcvrEnDlyLimitOpt[ByteLane]) { - // no passing window - if (ErrorCheck) { - return FALSE; - } - PutEventLog (AGESA_ERROR, MEM_ERROR_RCVR_EN_NO_PASSING_WINDOW, NBPtr->Node, NBPtr->Dct, NBPtr->Channel, ByteLane, &NBPtr->MemPtr->StdHeader); - SetMemError (AGESA_ERROR, MCTPtr); - } - if (TechPtr->RcvrEnDlyOpt[ByteLane] > (TechPtr->RcvrEnDlyLimitOpt[ByteLane] - 1)) { - // passing window too narrow, too far delayed - if (ErrorCheck) { - return FALSE; - } - PutEventLog (AGESA_ERROR, MEM_ERROR_RCVR_EN_VALUE_TOO_LARGE, NBPtr->Node, NBPtr->Dct, NBPtr->Channel, ByteLane, &NBPtr->MemPtr->StdHeader); - SetMemError (AGESA_ERROR, MCTPtr); - DCTPtr->Timings.CsTrainFail |= (UINT16) (3 << Receiver) & DCTPtr->Timings.CsPresent; - MCTPtr->ChannelTrainFail |= (UINT32)1 << Dct; - if (!NBPtr->MemPtr->ErrorHandling (MCTPtr, NBPtr->Dct, DCTPtr->Timings.CsTrainFail, &MemPtr->StdHeader)) { - return FALSE; - } - } - } - return TRUE; -} - -/*----------------------------------------------------------------------------- - * - * This function determines the maximum receiver delay value - * - * @param[in,out] *TechPtr - Pointer to the MEM_TECH_BLOCK - * - * @retval MaxRcvrValue - Maximum receiver delay value for all bytelanes - * ---------------------------------------------------------------------------- - */ - -UINT16 -MemTGetMaxValueOptByte ( - IN OUT MEM_TECH_BLOCK *TechPtr - ) -{ - UINT8 ByteLane; - UINT16 MaxRcvrValue; - MaxRcvrValue = 0; - for (ByteLane = 0; ByteLane < MAX_BYTELANES_PER_CHANNEL; ByteLane++) { - if (TechPtr->MaxRcvrEnDlyBlOpt[ByteLane] > MaxRcvrValue) { - MaxRcvrValue = TechPtr->MaxRcvrEnDlyBlOpt[ByteLane]; - } - } - MaxRcvrValue += FILTER_OFFSET_VALUE; - return MaxRcvrValue; -} -/*----------------------------------------------------------------------------- - * - * This function determines if the sweep loop should complete. - * - * @param[in,out] *TechPtr - Pointer to the MEM_TECH_BLOCK - * - * @retval TRUE - All bytelanes pass - * FALSE - Some bytelanes fail - * ---------------------------------------------------------------------------- - */ - -BOOLEAN -MemTCheckRcvrEnDlyLimitOptByte ( - IN OUT MEM_TECH_BLOCK *TechPtr - ) -{ - if (TechPtr->FilterCountOpt >= (UINT16)MAX_CS_PER_CHANNEL) { - return TRUE; - } else { - return FALSE; - } -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * This function load the result of write levelization training into RcvrEnDlyOpt, - * using it as the initial value for Receiver DQS training. - * - * @param[in,out] *TechPtr - Pointer to the MEM_TECH_BLOCK - * @param[in] Receiver - Current Chip select value - */ -VOID -STATIC -MemTLoadInitialRcvEnDlyOptByte ( - IN OUT MEM_TECH_BLOCK *TechPtr, - IN UINT8 Receiver - ) -{ - UINT8 ByteLane; - MEM_NB_BLOCK *NBPtr; - - NBPtr = TechPtr->NBPtr; - for (ByteLane = 0; ByteLane < MAX_BYTELANES_PER_CHANNEL; ByteLane++) { - TechPtr->RcvrEnDlyOpt[ByteLane] = NBPtr->ChannelPtr->WrDqsDlys[((Receiver >> 1) * TechPtr->DlyTableWidth ()) + ByteLane]; - } -} diff --git a/src/vendorcode/amd/agesa/f12/Proc/Mem/Tech/mttecc.c b/src/vendorcode/amd/agesa/f12/Proc/Mem/Tech/mttecc.c deleted file mode 100644 index a7fd6b50f0..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/Mem/Tech/mttecc.c +++ /dev/null @@ -1,226 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * mttecc.c - * - * Technology ECC byte support - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: (Mem/Tech) - * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $ - * - **/ -/***************************************************************************** -* -* Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* *************************************************************************** -* -*/ - -/* - *---------------------------------------------------------------------------- - * MODULES USED - * - *---------------------------------------------------------------------------- - */ - - -#include "AGESA.h" -#include "Ids.h" -#include "mm.h" -#include "mn.h" -#include "mu.h" -#include "mt.h" -#include "Filecode.h" -CODE_GROUP (G1_PEICC) -RDATA_GROUP (G1_PEICC) - -#define FILECODE PROC_MEM_TECH_MTTECC_FILECODE -/*---------------------------------------------------------------------------- - * DEFINITIONS AND MACROS - * - *---------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------- - * TYPEDEFS AND STRUCTURES - * - *---------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------- - * PROTOTYPES OF LOCAL FUNCTIONS - * - *---------------------------------------------------------------------------- - */ - -VOID -STATIC -MemTCalcDQSEccTmg ( - IN OUT MEM_TECH_BLOCK *TechPtr, - IN UINT8 Dimm, - IN UINT8 Type, - IN OUT VOID *DlyArray - ); - -/*---------------------------------------------------------------------------- - * EXPORTED FUNCTIONS - * - *---------------------------------------------------------------------------- - */ - -/* -----------------------------------------------------------------------------*/ -/** - * - * This function sets the DQS ECC timings - * - * @param[in,out] *TechPtr - Pointer to the MEM_TECH_BLOCK - * - * @return TRUE - No fatal error occurs. - * @return FALSE - Fatal error occurs. - */ - -BOOLEAN -MemTSetDQSEccTmgs ( - IN OUT MEM_TECH_BLOCK *TechPtr - ) -{ - UINT8 Dct; - UINT8 Dimm; - UINT8 i; - - MEM_NB_BLOCK *NBPtr; - CH_DEF_STRUCT *ChannelPtr; - - NBPtr = TechPtr->NBPtr; - if (NBPtr->MCTPtr->NodeMemSize) { - for (Dct = 0; Dct < NBPtr->DctCount; Dct++) { - NBPtr->SwitchDCT (NBPtr, Dct); - if (NBPtr->DCTPtr->Timings.DctMemSize != 0) { - ChannelPtr = NBPtr->ChannelPtr; - for (Dimm = 0; Dimm < MAX_DIMMS_PER_CHANNEL; Dimm++) { - if (NBPtr->DCTPtr->Timings.CsEnabled & ((UINT16)1 << (Dimm * 2))) { - i = Dimm * TechPtr->DlyTableWidth (); - MemTCalcDQSEccTmg (TechPtr, Dimm, AccessRcvEnDly, &ChannelPtr->RcvEnDlys[i]); - MemTCalcDQSEccTmg (TechPtr, Dimm, AccessRdDqsDly, &ChannelPtr->RdDqsDlys[i]); - MemTCalcDQSEccTmg (TechPtr, Dimm, AccessWrDatDly, &ChannelPtr->WrDatDlys[i]); - } - } - } - } - } - return (BOOLEAN) (NBPtr->MCTPtr->ErrCode < AGESA_FATAL); -} - -/*---------------------------------------------------------------------------- - * LOCAL FUNCTIONS - * - *---------------------------------------------------------------------------- - */ - -/* -----------------------------------------------------------------------------*/ -/** - * - * This function calculates the DQS ECC timings - * - * @param[in,out] *TechPtr - Pointer to the MEM_TECH_BLOCK - * @param[in] Dimm - Dimm number - * @param[in] Type - Type of DQS timing - * @param[in,out] *DlyArray - Pointer to the array of delays per this Dimm - * - */ - -VOID -STATIC -MemTCalcDQSEccTmg ( - IN OUT MEM_TECH_BLOCK *TechPtr, - IN UINT8 Dimm, - IN UINT8 Type, - IN OUT VOID *DlyArray - ) -{ - UINT8 i; - UINT8 j; - UINT8 Scale; - UINT8 EccByte; - UINT16 ByteiDly; - UINT16 BytejDly; - UINT16 EccDly; - UINT8 *WrDqsDly; - MEM_NB_BLOCK *NBPtr; - CH_DEF_STRUCT *ChannelPtr; - - NBPtr = TechPtr->NBPtr; - ChannelPtr = NBPtr->ChannelPtr; - - EccByte = TechPtr->MaxByteLanes (); - i = (UINT8) (ChannelPtr->DctEccDqsLike & 0xFF); - j = (UINT8) (ChannelPtr->DctEccDqsLike >> 8); - Scale = ChannelPtr->DctEccDqsScale; - WrDqsDly = &ChannelPtr->WrDqsDlys[Dimm * TechPtr->DlyTableWidth ()]; - - if (Type == AccessRcvEnDly) { - ByteiDly = ((UINT16 *) DlyArray)[i]; - BytejDly = ((UINT16 *) DlyArray)[j]; - } else { - ByteiDly = ((UINT8 *) DlyArray)[i]; - BytejDly = ((UINT8 *) DlyArray)[j]; - } - - // - // For WrDatDly, Subtract TxDqs Delay to get - // TxDq-TxDqs Delta, which is what should be averaged. - // - if (Type == AccessWrDatDly) { - ByteiDly = ByteiDly - WrDqsDly[i]; - BytejDly = BytejDly - WrDqsDly[j]; - } - - if (BytejDly > ByteiDly) { - EccDly = ByteiDly + (UINT8) (((UINT16) (BytejDly - ByteiDly) * Scale + 0x77) / 0xFF); - // Round up --^ - } else { - EccDly = BytejDly + (UINT8) (((UINT16) (ByteiDly - BytejDly) * (0xFF - Scale) + 0x77) / 0xFF); - // Round up --^ - } - - if (Type == AccessRcvEnDly) { - ((UINT16 *) DlyArray)[EccByte] = EccDly; - } else { - ((UINT8 *) DlyArray)[EccByte] = (UINT8) EccDly; - } - - // - // For WrDatDly, Add back the TxDqs value for ECC bytelane - // - if (Type == AccessWrDatDly) { - EccDly = EccDly + WrDqsDly[EccByte]; - } - - NBPtr->SetTrainDly (NBPtr, Type, DIMM_BYTE_ACCESS (Dimm, EccByte), EccDly); -} diff --git a/src/vendorcode/amd/agesa/f12/Proc/Mem/Tech/mtthrc.c b/src/vendorcode/amd/agesa/f12/Proc/Mem/Tech/mtthrc.c deleted file mode 100644 index 82b895ca45..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/Mem/Tech/mtthrc.c +++ /dev/null @@ -1,311 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * mtthrc.c - * - * Phy assisted DQS receiver enable training - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: (Mem/Tech) - * @e \$Revision: 49104 $ @e \$Date: 2011-03-17 06:54:25 +0800 (Thu, 17 Mar 2011) $ - * - **/ -/***************************************************************************** -* -* Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* *************************************************************************** -* -*/ - -/* - *---------------------------------------------------------------------------- - * MODULES USED - * - *---------------------------------------------------------------------------- - */ - - - -#include "AGESA.h" -#include "amdlib.h" -#include "Ids.h" -#include "mm.h" -#include "mn.h" -#include "mu.h" -#include "mt.h" -#include "Filecode.h" -CODE_GROUP (G1_PEICC) -RDATA_GROUP (G1_PEICC) - -#define FILECODE PROC_MEM_TECH_MTTHRC_FILECODE -/*---------------------------------------------------------------------------- - * DEFINITIONS AND MACROS - * - *---------------------------------------------------------------------------- - */ -#define TpProcMemRcvrSetSeed TpProcMemRcvrSetDelay -#define TpProcMemRcvrInitPRE TpProcMemRcvrStartSweep -#define TpProcMemRcvrBackToBackRead TpProcMemRcvrTestPattern - -/*---------------------------------------------------------------------------- - * TYPEDEFS AND STRUCTURES - * - *---------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------- - * PROTOTYPES OF LOCAL FUNCTIONS - * - *---------------------------------------------------------------------------- - */ - -VOID -STATIC -MemTProgramRcvrEnDly ( - IN OUT MEM_TECH_BLOCK *TechPtr, - IN UINT8 ChipSel, - IN UINT8 Pass - ); - -BOOLEAN -STATIC -MemTDqsTrainRcvrEnHw ( - IN OUT MEM_TECH_BLOCK *TechPtr, - IN UINT8 Pass - ); - -/*---------------------------------------------------------------------------- - * EXPORTED FUNCTIONS - * - *---------------------------------------------------------------------------- - */ -extern UINT16 T1minToFreq[]; - -/* -----------------------------------------------------------------------------*/ -/** - * - * This function executes first pass of Phy assisted receiver enable training - * for current node at DDR800 and below. - * - * @param[in,out] *TechPtr - Pointer to the MEM_TECH_BLOCK - * - * @pre Auto refresh and ZQCL must be disabled - * - * @return TRUE - No fatal error occurs. - * @return FALSE - Fatal error occurs. - */ -BOOLEAN -MemTDqsTrainRcvrEnHwPass1 ( - IN OUT MEM_TECH_BLOCK *TechPtr - ) -{ - return MemTDqsTrainRcvrEnHw (TechPtr, 1); -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * This function executes second pass of Phy assisted receiver enable training - * for current node at DDR1066 and above. - * - * @param[in,out] *TechPtr - Pointer to the MEM_TECH_BLOCK - * - * @pre Auto refresh and ZQCL must be disabled - * - * @return TRUE - No fatal error occurs. - * @return FALSE - Fatal error occurs. - */ -BOOLEAN -MemTDqsTrainRcvrEnHwPass2 ( - IN OUT MEM_TECH_BLOCK *TechPtr - ) -{ - // If current speed is higher than start-up speed, do second pass of WL - if (TechPtr->NBPtr->DCTPtr->Timings.Speed > TechPtr->NBPtr->StartupSpeed) { - return MemTDqsTrainRcvrEnHw (TechPtr, 2); - } - return TRUE; -} - -/*---------------------------------------------------------------------------- - * LOCAL FUNCTIONS - * - *---------------------------------------------------------------------------- - */ - -/* -----------------------------------------------------------------------------*/ -/** - * - * This function executes Phy assisted receiver enable training for current node. - * - * @param[in,out] *TechPtr - Pointer to the MEM_TECH_BLOCK - * @param[in] Pass - Pass of the receiver training - * - * @pre Auto refresh and ZQCL must be disabled - * - */ -BOOLEAN -STATIC -MemTDqsTrainRcvrEnHw ( - IN OUT MEM_TECH_BLOCK *TechPtr, - IN UINT8 Pass - ) -{ - MEM_NB_BLOCK *NBPtr; - UINT32 TestAddrRJ16; - UINT8 Dct; - UINT8 ChipSel; - NBPtr = TechPtr->NBPtr; - - TechPtr->TrainingType = TRN_RCVR_ENABLE; - - AGESA_TESTPOINT (TpProcMemReceiverEnableTraining , &(NBPtr->MemPtr->StdHeader)); - IDS_HDT_CONSOLE (MEM_STATUS, "\nStart HW RxEn training\n"); - - // Set environment settings before training - MemTBeginTraining (TechPtr); - // - // Setup hardware training engine (if applicable) - // - NBPtr->FamilySpecificHook[SetupHwTrainingEngine] (NBPtr, &TechPtr->TrainingType); - - for (Dct = 0; Dct < NBPtr->DctCount; Dct++) { - IDS_HDT_CONSOLE (MEM_STATUS, "\tDct %d\n", Dct); - NBPtr->SwitchDCT (NBPtr, Dct); - //training for each rank - for (ChipSel = 0; ChipSel < MAX_CS_PER_CHANNEL; ChipSel++) { - if (NBPtr->GetSysAddr (NBPtr, ChipSel, &TestAddrRJ16)) { - if (!(NBPtr->MCTPtr->Status[SbLrdimms]) || ((NBPtr->ChannelPtr->LrDimmPresent & ((UINT8) 1 << (ChipSel >> 1))) != 0)) { - // 1.Prepare the DIMMs for training - NBPtr->SetBitField (NBPtr, BFTrDimmSel, ChipSel >> 1); - - TechPtr->ChipSel = ChipSel; - TechPtr->Pass = Pass; - NBPtr->FamilySpecificHook[InitPerNibbleTrn] (NBPtr, NULL); - for (TechPtr->TrnNibble = NIBBLE_0; TechPtr->TrnNibble <= (NBPtr->FamilySpecificHook[TrainRxEnPerNibble] (NBPtr, &ChipSel)? NIBBLE_0 : NIBBLE_1); TechPtr->TrnNibble++) { - // 2.Prepare the phy for DQS receiver enable training. - IDS_HDT_CONSOLE (MEM_STATUS, "\t\tCS %d\n", ChipSel); - IDS_HDT_CONSOLE (MEM_FLOW, "\t\tTestAddr %x0000\n", TestAddrRJ16); - IDS_HDT_CONSOLE (MEM_FLOW, "\t\t\t Byte: 00 01 02 03 04 05 06 07 ECC\n"); - - AGESA_TESTPOINT (TpProcMemRcvrSetSeed, &(NBPtr->MemPtr->StdHeader)); - NBPtr->MemNPrepareRcvrEnDlySeed (NBPtr); - - AGESA_TESTPOINT (TpProcMemRcvrInitPRE, &(NBPtr->MemPtr->StdHeader)); - // 3.BIOS initiates the phy assisted receiver enable training - NBPtr->SetBitField (NBPtr, BFDqsRcvTrEn, 1); - - // 4.BIOS begins sending out of back-to-back reads to create - // a continuous stream of DQS edges on the DDR interface - AGESA_TESTPOINT (TpProcMemRcvrBackToBackRead, &(NBPtr->MemPtr->StdHeader)); - NBPtr->GenHwRcvEnReads (NBPtr, TestAddrRJ16); - - // 7.Program [DqsRcvTrEn]=0 to stop the DQS receive enable training. - NBPtr->SetBitField (NBPtr, BFDqsRcvTrEn, 0); - - // 8.Get the gross and fine delay values. - // 9.Calculate the corresponding final delay values - MemTProgramRcvrEnDly (TechPtr, ChipSel, Pass); - } - } - } - } - } - // Restore environment settings after training - MemTEndTraining (TechPtr); - IDS_HDT_CONSOLE (MEM_FLOW, "End HW RxEn training\n\n"); - - return (BOOLEAN) (NBPtr->MCTPtr->ErrCode < AGESA_FATAL); -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * This function calculates final RcvrEnDly for each rank - * - * @param[in,out] *TechPtr - Pointer to the MEM_TECH_BLOCK - * @param[in] ChipSel - Rank to be trained - * @param[in] Pass - Pass of the receiver training - * - */ -VOID -STATIC -MemTProgramRcvrEnDly ( - IN OUT MEM_TECH_BLOCK *TechPtr, - IN UINT8 ChipSel, - IN UINT8 Pass - ) -{ - MEM_NB_BLOCK *NBPtr; - CH_DEF_STRUCT *ChannelPtr; - UINT8 ByteLane; - UINT16 RcvEnDly; - UINT16 CsPairRcvEnDly; - UINT16 RankRcvEnDly[9]; - NBPtr = TechPtr->NBPtr; - ChannelPtr = TechPtr->NBPtr->ChannelPtr; - IDS_HDT_CONSOLE (MEM_FLOW, "\t\t\t PRE: "); - for (ByteLane = 0; ByteLane < (NBPtr->MCTPtr->Status[SbEccDimms] ? 9 : 8) ; ByteLane++) { - RcvEnDly = (UINT8) NBPtr->GetTrainDly (NBPtr, AccessPhRecDly, DIMM_BYTE_ACCESS (ChipSel >> 1, ByteLane)); - IDS_HDT_CONSOLE (MEM_FLOW, "%03x ", RcvEnDly); - - RcvEnDly = RcvEnDly + TechPtr->DiffSeedGrossSeedPreGross[ByteLane]; - - // Add 1 UI to get to the midpoint of preamble - RcvEnDly += 0x20; - TechPtr->Bytelane = ByteLane; - RankRcvEnDly[ByteLane] = RcvEnDly; - if (NBPtr->FamilySpecificHook[TrainRxEnAdjustDlyPerNibble] (NBPtr, &RcvEnDly)) { - if ((ChipSel & 1) == 1) { - // For each rank pair on a dual-rank DIMM, compute the average value of the total delays saved during the - // training of each rank and program the result in D18F2x[1,0]9C_x0000_00[24:10][DqsRcvEnGrossDelay, - // DqsRcvEnFineDelay]. - CsPairRcvEnDly = ChannelPtr->RcvEnDlys[(ChipSel >> 1) * TechPtr->DlyTableWidth () + ByteLane]; - RcvEnDly = (CsPairRcvEnDly + RcvEnDly + 1) / 2; - } - } - ChannelPtr->RcvEnDlys[(ChipSel >> 1) * TechPtr->DlyTableWidth () + ByteLane] = RcvEnDly; - NBPtr->SetTrainDly (NBPtr, AccessRcvEnDly, DIMM_BYTE_ACCESS ((ChipSel >> 1), ByteLane), RcvEnDly); - } - - IDS_HDT_CONSOLE_DEBUG_CODE ( - IDS_HDT_CONSOLE (MEM_FLOW, "\n\t\t\t RxEn: "); - for (ByteLane = 0; ByteLane < (NBPtr->MCTPtr->Status[SbEccDimms] ? 9 : 8); ByteLane++) { - IDS_HDT_CONSOLE (MEM_FLOW, "%03x ", RankRcvEnDly[ByteLane]); - } - if (NBPtr->FamilySpecificHook[TrainRxEnGetAvgDlyPerNibble] (NBPtr, NULL)) { - if ((ChipSel & 1) == 1) { - IDS_HDT_CONSOLE (MEM_FLOW, "\n\t\t\t Avg: "); - for (ByteLane = 0; ByteLane < (NBPtr->MCTPtr->Status[SbEccDimms] ? 9 : 8); ByteLane++) { - IDS_HDT_CONSOLE (MEM_FLOW, "%03x ", ChannelPtr->RcvEnDlys[(ChipSel >> 1) * TechPtr->DlyTableWidth () + ByteLane]); - } - } - } - IDS_HDT_CONSOLE (MEM_FLOW, "\n\n"); - ); -} diff --git a/src/vendorcode/amd/agesa/f12/Proc/Mem/Tech/mtthrcSeedTrain.c b/src/vendorcode/amd/agesa/f12/Proc/Mem/Tech/mtthrcSeedTrain.c deleted file mode 100644 index c2ebc9bfbd..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/Mem/Tech/mtthrcSeedTrain.c +++ /dev/null @@ -1,629 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * mtthrcSt.c - * - * Phy assisted DQS receiver enable seedless training - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: (Mem/Tech) - * @e \$Revision: 42643 $ @e \$Date: 2010-11-24 13:51:41 -0600 (Wed, 24 Nov 2010) $ - * - **/ -/***************************************************************************** -* -* Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* *************************************************************************** -* -*/ - -/* - *---------------------------------------------------------------------------- - * MODULES USED - * - *---------------------------------------------------------------------------- - */ - - - -#include "AGESA.h" -#include "amdlib.h" -#include "Ids.h" -#include "mm.h" -#include "mn.h" -#include "mt.h" -#include "mttEdgeDetect.h" -#include "Filecode.h" -CODE_GROUP (G1_PEICC) -RDATA_GROUP (G1_PEICC) - -#define FILECODE PROC_MEM_TECH_MTTHRCSEEDTRAIN_FILECODE -/*---------------------------------------------------------------------------- -3 * DEFINITIONS AND MACROS - * - *---------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------- - * TYPEDEFS AND STRUCTURES - * - *---------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------- - * PROTOTYPES OF LOCAL FUNCTIONS - * - *---------------------------------------------------------------------------- - */ - -VOID -STATIC -MemTRdPosRxEnSeedSetDly3 ( - IN OUT MEM_TECH_BLOCK *TechPtr, - IN OUT UINT16 RcvEnDly, - IN OUT UINT8 ByteLane - ); - -VOID -STATIC -MemTRdPosRxEnSeedCheckRxEndly3 ( - IN OUT MEM_TECH_BLOCK *TechPtr - ); -/*---------------------------------------------------------------------------- - * EXPORTED FUNCTIONS - * - *---------------------------------------------------------------------------- - */ -/*---------------------------------------------------------------------------- - * LOCAL FUNCTIONS - * - *---------------------------------------------------------------------------- - */ -/*----------------------------------------------------------------------------- - * - * - * This function checks each bytelane for no window error. - * - * - * @param[in,out] *TechPtr - Pointer to the MEM_TECH_BLOCK - * @param[in,out] OptParam - Optional parameter - * - * @return TRUE - * ---------------------------------------------------------------------------- - */ -BOOLEAN -MemTTrackRxEnSeedlessRdWrNoWindBLError ( - IN OUT MEM_TECH_BLOCK *TechPtr, - IN OUT VOID *OptParam - ) -{ - UINT8 i; - SWEEP_INFO SweepData; - SweepData = *(SWEEP_INFO*)OptParam; - for (i = 0; i < ((TechPtr->NBPtr->MCTPtr->Status[SbEccDimms] && TechPtr->NBPtr->IsSupported[EccByteTraining]) ? 9 : 8) ; i++) { - // - /// Skip Bytelanes that have already reached the desired result - // - if ((SweepData.ResultFound & ((UINT16)1 << i)) == 0) { - if (SweepData.TrnDelays[i] == SweepData.EndDelay) { - if ((SweepData.EndResult & ((UINT16) (1 << i))) != 0) { - TechPtr->ByteLaneError[i] = TRUE; - } else { - TechPtr->ByteLaneError[i] = FALSE; - } - } - } - } - return TRUE; -} -/*----------------------------------------------------------------------------- - * - * - * This function checks each bytelane for small window error. - * - * - * @param[in,out] *TechPtr - Pointer to the MEM_TECH_BLOCK - * @param[in,out] OptParam - Optional parameter - * - * @return TRUE - * ---------------------------------------------------------------------------- - */ -BOOLEAN -MemTTrackRxEnSeedlessRdWrSmallWindBLError ( - IN OUT MEM_TECH_BLOCK *TechPtr, - IN OUT VOID *OptParam - ) -{ - SWEEP_INFO SweepData; - SweepData = *(SWEEP_INFO*)OptParam; - if (SweepData.Error == TRUE) { - TechPtr->ByteLaneError[TechPtr->Bytelane] = TRUE; - } else { - TechPtr->ByteLaneError[TechPtr->Bytelane] = FALSE; - } - return TRUE; -} -/* -----------------------------------------------------------------------------*/ -/** - * - * This function sets the RxEn delay - * - * @param[in,out] *TechPtr - Pointer to the MEM_TECH_BLOCK - * @param[in,out] *RcvEnDly - Receiver Enable Delay - * @param[in,out] *ByteLane - Bytelane - * -*/ -VOID -STATIC -MemTRdPosRxEnSeedSetDly3 ( - IN OUT MEM_TECH_BLOCK *TechPtr, - IN OUT UINT16 RcvEnDly, - IN OUT UINT8 ByteLane - ) -{ - TechPtr->NBPtr->ChannelPtr->RcvEnDlys[(TechPtr->ChipSel >> 1) * TechPtr->DlyTableWidth () + ByteLane] = RcvEnDly; - TechPtr->NBPtr->SetTrainDly (TechPtr->NBPtr, AccessRcvEnDly, DIMM_BYTE_ACCESS ((TechPtr->ChipSel >> 1), ByteLane), RcvEnDly); - TechPtr->NBPtr->FamilySpecificHook[ResetRxFifoPtr] (TechPtr->NBPtr, TechPtr->NBPtr); -} -/* -----------------------------------------------------------------------------*/ -/** - * - * This function determines if the currert RxEn delay settings have failed - * - * @param[in,out] *TechPtr - Pointer to the MEM_TECH_BLOCK - * -*/ -VOID -STATIC -MemTRdPosRxEnSeedCheckRxEndly3 ( - IN OUT MEM_TECH_BLOCK *TechPtr - ) -{ - UINT8 MaxDlyDimm; - TechPtr->FindMaxDlyForMaxRdLat (TechPtr, &MaxDlyDimm); - TechPtr->NBPtr->SetMaxLatency (TechPtr->NBPtr, TechPtr->MaxDlyForMaxRdLat); - TechPtr->DqsRdWrPosSaved = 0; - MemTTrainDQSEdgeDetect (TechPtr); -} -/* -----------------------------------------------------------------------------*/ -/** - * - * This function executes RdDQS training and if fails adjusts the RxEn Gross results for - * each bytelane - * - * @param[in,out] *TechPtr - Pointer to the MEM_TECH_BLOCK - * - * @return TRUE - All bytelanes pass - * @return FALSE - Some bytelanes fail -*/ -BOOLEAN -MemTRdPosWithRxEnDlySeeds3 ( - IN OUT MEM_TECH_BLOCK *TechPtr - ) -{ - UINT8 ByteLane; - UINT16 PassTestRxEnDly[MAX_BYTELANES_PER_CHANNEL + 1]; - UINT16 FailTestRxEnDly[MAX_BYTELANES_PER_CHANNEL + 1]; - UINT16 FinalRxEnCycle[MAX_BYTELANES_PER_CHANNEL + 1]; - UINT16 RxOrig[MAX_BYTELANES_PER_CHANNEL]; - UINT8 i; - UINT8 j; - UINT8 NumBLWithTargetFound; - UINT8 MaxByteLanes; - INT16 RxEn; - BOOLEAN status; - BOOLEAN EsbNoDqsPosSave; - BOOLEAN OutOfRange[MAX_BYTELANES_PER_CHANNEL]; - BOOLEAN ByteLanePass[MAX_BYTELANES_PER_CHANNEL]; - BOOLEAN ByteLaneFail[MAX_BYTELANES_PER_CHANNEL]; - BOOLEAN RxEnMemClkTested[MAX_BYTELANES_PER_CHANNEL][MAX_POS_RX_EN_SEED_GROSS_RANGE]; - BOOLEAN RxEnMemClkSt[MAX_BYTELANES_PER_CHANNEL][MAX_POS_RX_EN_SEED_GROSS_RANGE]; - BOOLEAN RxEnDlyTargetFound[MAX_BYTELANES_PER_CHANNEL]; - BOOLEAN DlyWrittenToReg[MAX_BYTELANES_PER_CHANNEL]; - UINT16 RxEnDlyTargetValue[MAX_BYTELANES_PER_CHANNEL]; - UINT8 AllByteLanesOutOfRange; - UINT8 AllByteLanesSaved; - UINT8 TotalByteLanesCheckedForSaved; - UINT8 MemClkCycle; - MEM_NB_BLOCK *NBPtr; - CH_DEF_STRUCT *ChannelPtr; - NBPtr = TechPtr->NBPtr; - ChannelPtr = TechPtr->NBPtr->ChannelPtr; - NumBLWithTargetFound = 0; - status = FALSE; - EsbNoDqsPosSave = TechPtr->NBPtr->MCTPtr->ErrStatus[EsbNoDqsPos]; - NBPtr->RdDqsDlyRetrnStat = RDDQSDLY_RTN_SUSPEND; - IDS_HDT_CONSOLE (MEM_FLOW, "\n\nStart HW RxEn Seedless training\n\n"); - // 1. Program D18F2x9C_x0D0F_0[F,8:0]30_dct[1:0][BlockRxDqsLock] = 1. - NBPtr->SetBitField (NBPtr, BFBlockRxDqsLock, 0x0100); - IDS_HDT_CONSOLE (MEM_FLOW, "\tChip Select: %02x \n", TechPtr->ChipSel); - IDS_HDT_CONSOLE (MEM_FLOW, "\t\t\t Byte: 00 01 02 03 04 05 06 07 ECC\n"); - IDS_HDT_CONSOLE (MEM_FLOW, "\t\t\t\tRxEn Orig: "); - // - // Start sweep loops for RxEn Seedless Training - // - MaxByteLanes = (TechPtr->NBPtr->MCTPtr->Status[SbEccDimms] && TechPtr->NBPtr->IsSupported[EccByteTraining]) ? 9 : 8; //dmach - // - //Initialialize BL variables - // - for (ByteLane = 0; ByteLane < MaxByteLanes; ByteLane++) { - OutOfRange[ByteLane] = FALSE; - ByteLanePass[ByteLane] = FALSE; - ByteLaneFail[ByteLane] = FALSE; - // 2. RxEnOrig = D18F2x9C_x0000_00[2A:10]_dct[1:0][DqsRcvEnGrossDelay, DqsRcvEnFineDelay] result - // from 2.10.6.8.2 [Phy Assisted DQS Receiver Enable Training] - RxOrig[ByteLane] = TechPtr->RxOrig[ByteLane]; // Original RxEn Dly based on PRE results - RxEnDlyTargetFound[ByteLane] = FALSE; - RxEnDlyTargetValue[ByteLane] = 0; - IDS_HDT_CONSOLE (MEM_FLOW, "%03x ", RxOrig[ByteLane]); - for (i = 0; i < MAX_POS_RX_EN_SEED_GROSS_RANGE; i++) { - RxEnMemClkTested[ByteLane][i] = FALSE; - } - } - // Start MemClk delay sweep - for (i = 0; i < MAX_POS_RX_EN_SEED_GROSS_RANGE; i++) { - IDS_HDT_CONSOLE (MEM_FLOW, "\n\t\ti: %02x\n", i); - // Start direction sweep (0, - Positive, 1 - negative) - for (j = 0; j < MAX_POS_RX_EN_SEED_GROSS_DIR; j++) { - // Edge detect may run twice to see Pass to fail transition - // It is not run if the value are already saved - // Fail test is only done if pass is found - IDS_HDT_CONSOLE (MEM_FLOW, "\n\t\tj: %02x\n", j); - // Reset Bytelane Flags for next sweep - for (ByteLane = 0; ByteLane < MaxByteLanes; ByteLane++) { - ByteLaneFail[ByteLane] = FALSE; - ByteLanePass[ByteLane] = FALSE; - OutOfRange[ByteLane] = FALSE; - } - if (i == 0 && j == 1) { - continue; // Since i & j are the same skip - } - IDS_HDT_CONSOLE_DEBUG_CODE ( - IDS_HDT_CONSOLE (MEM_FLOW, "\t Byte: 00 01 02 03 04 05 06 07 ECC\n"); - IDS_HDT_CONSOLE (MEM_FLOW, "\t Target BL Found: "); - for (ByteLane = 0; ByteLane < MaxByteLanes; ByteLane++) { - IDS_HDT_CONSOLE (MEM_FLOW, " %c ", ((RxEnDlyTargetFound[ByteLane] == TRUE) ? 'Y' : 'N')); - } - IDS_HDT_CONSOLE (MEM_FLOW, "\n\t Target BL Value: "); - for (ByteLane = 0; ByteLane < MaxByteLanes; ByteLane++) { - IDS_HDT_CONSOLE (MEM_FLOW, "%03x ", RxEnDlyTargetValue[ByteLane]); - } - ); - // - // Find the RxEn Delay for the Pass condition in the Pass to Fail transition - // "PassTestRxEnDly" - // - IDS_HDT_CONSOLE (MEM_FLOW, "\n\t\t Setting PassTestRxEnDly\n"); - IDS_HDT_CONSOLE (MEM_FLOW, "\t PassTestRxEnDly: "); - PassTestRxEnDly[ByteLane] = RxOrig[ByteLane]; - for (ByteLane = 0; ByteLane < MaxByteLanes; ByteLane++) { - if (RxEnDlyTargetFound[ByteLane] == FALSE) { - // Calculate "PassTestRxEnDly" from current "RxEnDly" - // 3. RxEnOffset = MOD(RxEnOrig + 0x10, 0x40) - RxEn = (j == 0) ? ((INT16)RxOrig[ByteLane] + 0x10 + (0x40*i)) : ((INT16)RxOrig[ByteLane] + 0x10 - (0x40*i)); - // Check if RxEnDly is in a valid range - if ((RxEn >= NBPtr->MinRxEnSeedGross) && (RxEn <= NBPtr->MaxRxEnSeedTotal)) { - PassTestRxEnDly[ByteLane] = (UINT16)RxEn; - // 4. For each DqsRcvEn value beginning from RxEnOffset incrementing by 1 MEMCLK: - // A. Program D18F2x9C_x0000_00[2A:10]_dct[1:0][DqsRcvEnGrossDelay, DqsRcvEnFineDelay] with - // the current value. - MemTRdPosRxEnSeedSetDly3 (TechPtr, PassTestRxEnDly[ByteLane], ByteLane); - OutOfRange[ByteLane] = FALSE; - } else { - OutOfRange[ByteLane] = TRUE; - } - } else { - PassTestRxEnDly[ByteLane] = RxEnDlyTargetValue[ByteLane]; - } - IDS_HDT_CONSOLE (MEM_FLOW, "%03x ", PassTestRxEnDly[ByteLane]); - } - // Check if all BLs out of Range at "PassTestRxEnDly" - IDS_HDT_CONSOLE (MEM_FLOW, "\n\t OutOfRange: "); - AllByteLanesOutOfRange = 0; - for (ByteLane = 0; ByteLane < MaxByteLanes; ByteLane++) { - if (OutOfRange[ByteLane]) { - AllByteLanesOutOfRange++; - } - IDS_HDT_CONSOLE (MEM_FLOW, " %c ", (OutOfRange[ByteLane] == TRUE) ? 'Y' : 'N'); - } - if (AllByteLanesOutOfRange == MaxByteLanes) { - continue; // All BLs out of range, so skip - } - // Check if all BLs saved Results at "PassTestRxEnDly" - AllByteLanesSaved = 0; - for (ByteLane = 0; ByteLane < MaxByteLanes; ByteLane++) { - MemClkCycle = (UINT8) (PassTestRxEnDly[ByteLane] >> 5); - if (RxEnDlyTargetFound[ByteLane] == FALSE) { - if (!RxEnMemClkTested[ByteLane][MemClkCycle]) { - AllByteLanesSaved++; - } - } - } - // Check if "RxEnDlyValueForPassCond" passed - if (AllByteLanesSaved != 0) { - // At least one BL has not been saved, so check if "PassTestRxEnDly" passed - IDS_HDT_CONSOLE (MEM_FLOW, "\n\t\t Checking if PassTestRxEnDly Passes?\n\n"); - // 4B. Perform 2.10.6.8.5 [DQS Position Training]. - // Record the result for the current DqsRcvEn setting as a pass or fail depending if a data eye is found. - MemTRdPosRxEnSeedCheckRxEndly3 (TechPtr); - IDS_HDT_CONSOLE_DEBUG_CODE ( - IDS_HDT_CONSOLE (MEM_FLOW, "\n\t Byte: 00 01 02 03 04 05 06 07 ECC\n"); - IDS_HDT_CONSOLE (MEM_FLOW, "\t\t Err Status: "); - for (ByteLane = 0; ByteLane < MaxByteLanes; ByteLane++) { - IDS_HDT_CONSOLE (MEM_FLOW, " %c ", (TechPtr->ByteLaneError[ByteLane] == TRUE) ? 'F' : 'P'); - } - ); - } else { - // All BLs saved, so use saved results for "PassTestRxEnDly" - IDS_HDT_CONSOLE (MEM_FLOW, "\n\t\tAll BLs Saved at PassTestRxEnDly\n"); - IDS_HDT_CONSOLE_DEBUG_CODE ( - IDS_HDT_CONSOLE (MEM_FLOW, "\t Byte: 00 01 02 03 04 05 06 07 ECC\n"); - IDS_HDT_CONSOLE (MEM_FLOW, "\t Save Err Stat: "); - for (ByteLane = 0; ByteLane < MaxByteLanes; ByteLane++) { - MemClkCycle = (UINT8) (PassTestRxEnDly[ByteLane] >> 5); - IDS_HDT_CONSOLE (MEM_FLOW, " %c ", ((RxEnMemClkSt[ByteLane][MemClkCycle] == TRUE) ? 'F' : 'P')); - } - ); - } - // Update Saved values for "PassTestRxEnDly" - for (ByteLane = 0; ByteLane < MaxByteLanes; ByteLane++) { - if (RxEnDlyTargetFound[ByteLane] == FALSE) { - if (OutOfRange[ByteLane] == FALSE) { - MemClkCycle = (UINT8) (PassTestRxEnDly[ByteLane] >> 5); - if (!RxEnMemClkTested[ByteLane][MemClkCycle]) { - RxEnMemClkTested[ByteLane][MemClkCycle] = TRUE; - RxEnMemClkSt[ByteLane][MemClkCycle] = TechPtr->ByteLaneError[ByteLane]; - } - } - } - } - // - // Find the RxEn Delay for the Fail condition in the Pass to Fail transition - // "FailTestRxEnDly" - // - for (ByteLane = 0; ByteLane < MaxByteLanes; ByteLane++) { - DlyWrittenToReg[ByteLane] = FALSE; - } - for (ByteLane = 0; ByteLane < MaxByteLanes; ByteLane++) { - FailTestRxEnDly[ByteLane] = PassTestRxEnDly[ByteLane] + 0x40; - } - IDS_HDT_CONSOLE_DEBUG_CODE ( - IDS_HDT_CONSOLE (MEM_FLOW, "\n\t Byte: 00 01 02 03 04 05 06 07 ECC\n"); - IDS_HDT_CONSOLE (MEM_FLOW, "\t FailTestRxEnDly: "); - for (ByteLane = 0; ByteLane < MaxByteLanes; ByteLane++) { - IDS_HDT_CONSOLE (MEM_FLOW, "%03x ", FailTestRxEnDly[ByteLane]); - } - ); - // Check if all BLs Saved Results at FailTestRxEnDly - IDS_HDT_CONSOLE (MEM_FLOW, "\n\t\tSetting FailTestRxEnDly"); - AllByteLanesSaved = 0; - TotalByteLanesCheckedForSaved = 0; - for (ByteLane = 0; ByteLane < MaxByteLanes; ByteLane++) { - if (RxEnDlyTargetFound[ByteLane] == FALSE) { - MemClkCycle = (UINT8) (FailTestRxEnDly[ByteLane] >> 5); - // Check if RxEnDly + 40 is valid - if ((FailTestRxEnDly[ByteLane] >= NBPtr->MinRxEnSeedGross) && (FailTestRxEnDly[ByteLane] <= NBPtr->MaxRxEnSeedTotal)) { - if (RxEnMemClkTested[ByteLane][MemClkCycle]) { - AllByteLanesSaved++; - } - OutOfRange[ByteLane] = FALSE; - } else { - OutOfRange[ByteLane] = TRUE; - } - TotalByteLanesCheckedForSaved++; - } - } - // Check if all BLs out of Range condition at FailTestRxEnDly - AllByteLanesOutOfRange = 0; - IDS_HDT_CONSOLE (MEM_FLOW, "\n\t OutOfRange: "); - for (ByteLane = 0; ByteLane < MaxByteLanes; ByteLane++) { - if (OutOfRange[ByteLane]) { - AllByteLanesOutOfRange++; - } - IDS_HDT_CONSOLE (MEM_FLOW, " %c ", (OutOfRange[ByteLane] == TRUE) ? 'Y' : 'N'); - } - if (AllByteLanesOutOfRange == MaxByteLanes) { - continue; // All BLs out of range, so skip - } - // Setting FailTestRxEnDly for any BL that was not saved - IDS_HDT_CONSOLE (MEM_FLOW, "\n\t FailTestRxEnDly: "); - for (ByteLane = 0; ByteLane < MaxByteLanes; ByteLane++) { - if (RxEnDlyTargetFound[ByteLane] == FALSE) { - MemClkCycle = (UINT8) (PassTestRxEnDly[ByteLane] >> 5); - // Check if New RxEnDly has Passed - if ((RxEnMemClkTested[ByteLane][MemClkCycle] ? RxEnMemClkSt[ByteLane][MemClkCycle] : TechPtr->ByteLaneError[ByteLane]) == FALSE) { - if (OutOfRange[ByteLane] == FALSE) { - // BL has passed at "New RxEnDly", so check if "New RxEnDly" + 0x40 fails - MemClkCycle = (UINT8) (FailTestRxEnDly[ByteLane] >> 5); - if (!RxEnMemClkTested[ByteLane][MemClkCycle]) { - // Only Set Delays for ByteLanes that have not been already tested - MemTRdPosRxEnSeedSetDly3 (TechPtr, FailTestRxEnDly[ByteLane], ByteLane); - DlyWrittenToReg[ByteLane] = TRUE; - IDS_HDT_CONSOLE (MEM_FLOW, " %c ", 'Y'); - } else { - IDS_HDT_CONSOLE (MEM_FLOW, " %c ", 'N'); - } - ByteLanePass[ByteLane] = TRUE; - } else { - IDS_HDT_CONSOLE (MEM_FLOW, " %c ", 'O'); - } - } else { - IDS_HDT_CONSOLE (MEM_FLOW, " %c ", 'F'); - } - } else { - IDS_HDT_CONSOLE (MEM_FLOW, " %c ", 'N'); - } - } - // Check if BLs that passed at PassTestRxEnDly fail at FailTestRxEnDly - if (AllByteLanesSaved != TotalByteLanesCheckedForSaved) { - // At least one BL has not been saved, so check if FailTestRxEnDly passed - IDS_HDT_CONSOLE (MEM_FLOW, "\n\n\t\t Checking if FailTestRxEnDly Fails?\n"); - MemTRdPosRxEnSeedCheckRxEndly3 (TechPtr); - IDS_HDT_CONSOLE_DEBUG_CODE ( - IDS_HDT_CONSOLE (MEM_FLOW, "\n\t Byte: 00 01 02 03 04 05 06 07 ECC\n"); - IDS_HDT_CONSOLE (MEM_FLOW, "\t Err Status: "); - for (ByteLane = 0; ByteLane < MaxByteLanes; ByteLane++) { - IDS_HDT_CONSOLE (MEM_FLOW, " %c ", (TechPtr->ByteLaneError[ByteLane] == TRUE) ? 'F' : 'P'); - } - ); - } else { - // All BLs saved, so use saved results for FailTestRxEnDly - IDS_HDT_CONSOLE (MEM_FLOW, "\n\t\tAll BLs Saved at PassTestRxEnDly\n"); - IDS_HDT_CONSOLE_DEBUG_CODE ( - IDS_HDT_CONSOLE (MEM_FLOW, "\t Byte: 00 01 02 03 04 05 06 07 ECC\n"); - IDS_HDT_CONSOLE (MEM_FLOW, "\t Save Err Stat: "); - for (ByteLane = 0; ByteLane < MaxByteLanes; ByteLane++) { - MemClkCycle = (UINT8) (FailTestRxEnDly[ByteLane] >> 5); - IDS_HDT_CONSOLE (MEM_FLOW, " %c ", (RxEnMemClkSt[ByteLane][MemClkCycle] == TRUE) ? 'F' : 'P'); - } - ); - } - // - // If BL failes at "FailTestRxEnDly" set FinalRxEnCycle - // - // Setting FinalRxEnCycle for any BL that Failed at FailTestRxEnDly - IDS_HDT_CONSOLE (MEM_FLOW, "\n Set FinalRxEnCycle: "); - for (ByteLane = 0; ByteLane < MaxByteLanes; ByteLane++) { - if (RxEnDlyTargetFound[ByteLane] == FALSE) { - MemClkCycle = (UINT8) (FailTestRxEnDly[ByteLane] >> 5); - if (RxEnMemClkTested[ByteLane][MemClkCycle] ? RxEnMemClkSt[ByteLane][MemClkCycle] == TRUE : (TechPtr->ByteLaneError[ByteLane] && DlyWrittenToReg[ByteLane])) { - FinalRxEnCycle[ByteLane] = PassTestRxEnDly[ByteLane] - 0x10; - if (((UINT16) FinalRxEnCycle[ByteLane] >= NBPtr->MinRxEnSeedGross) && ((UINT16) FinalRxEnCycle[ByteLane] <= NBPtr->MaxRxEnSeedTotal)) { - // Since FailTestRxEnDly, we can set FinalRxEnCycle - MemTRdPosRxEnSeedSetDly3 (TechPtr, (UINT16) FinalRxEnCycle[ByteLane], ByteLane); - ByteLaneFail[ByteLane] = TRUE; - OutOfRange[ByteLane] = FALSE; - IDS_HDT_CONSOLE (MEM_FLOW, " %c ", 'Y'); - } else { - OutOfRange[ByteLane] = TRUE; - IDS_HDT_CONSOLE (MEM_FLOW, " %c ", 'N'); - } - } else { - IDS_HDT_CONSOLE (MEM_FLOW, " %c ", 'F'); - OutOfRange[ByteLane] = FALSE; - } - } else { - IDS_HDT_CONSOLE (MEM_FLOW, " %c ", 'Y'); - } - } - // Update Saved values for FailTestRxEnDly - for (ByteLane = 0; ByteLane < MaxByteLanes; ByteLane++) { - if (RxEnDlyTargetFound[ByteLane] == FALSE) { - if (OutOfRange[ByteLane] == FALSE) { - MemClkCycle = (UINT8) (FailTestRxEnDly[ByteLane] >> 5); - if (!RxEnMemClkTested[ByteLane][MemClkCycle] && DlyWrittenToReg[ByteLane]) { - RxEnMemClkTested[ByteLane][MemClkCycle] = TRUE; - RxEnMemClkSt[ByteLane][MemClkCycle] = TechPtr->ByteLaneError[ByteLane]; - } - } - } - } - // Check for out of Range condition - AllByteLanesOutOfRange = 0; - IDS_HDT_CONSOLE (MEM_FLOW, "\n\t OutOfRange: "); - for (ByteLane = 0; ByteLane < MaxByteLanes; ByteLane++) { - if (OutOfRange[ByteLane]) { - AllByteLanesOutOfRange++; - } - IDS_HDT_CONSOLE (MEM_FLOW, " %c ", (OutOfRange[ByteLane] == TRUE) ? 'Y' : 'N'); - } - if (AllByteLanesOutOfRange == MaxByteLanes) { - continue; // All BLs out of range so skip - } - IDS_HDT_CONSOLE_DEBUG_CODE ( - IDS_HDT_CONSOLE (MEM_FLOW, "\n FinalRxEnCycle: "); - for (ByteLane = 0; ByteLane < MaxByteLanes; ByteLane++) { - IDS_HDT_CONSOLE (MEM_FLOW, "%03x ", (UINT16) FinalRxEnCycle[ByteLane]); - } - IDS_HDT_CONSOLE (MEM_FLOW, "\n ByteLaneFail: "); - for (ByteLane = 0; ByteLane < MaxByteLanes; ByteLane++) { - IDS_HDT_CONSOLE (MEM_FLOW, " %c ", (ByteLaneFail[ByteLane] == TRUE) ? 'Y' : 'N'); - } - IDS_HDT_CONSOLE (MEM_FLOW, "\n ByteLanePass: "); - for (ByteLane = 0; ByteLane < MaxByteLanes; ByteLane++) { - IDS_HDT_CONSOLE (MEM_FLOW, " %c ", (ByteLanePass[ByteLane] == TRUE) ? 'Y' : 'N'); - } - ); - // - // Check for exit condition - // PassTestRxEnDly = Pass and FailTestRxEnDly[ByteLane] = Fail - // If found, use "FinalRxEnCycle" as final RxEnDly value - // - // 5. Process the array of results and determine a pass-to-fail transition. - NumBLWithTargetFound = 0; - for (ByteLane = 0; ByteLane < MaxByteLanes; ByteLane++) { - if (RxEnDlyTargetFound[ByteLane] == FALSE) { - // Check if the current BL has found its target - if (ByteLanePass[ByteLane] == TRUE && ByteLaneFail[ByteLane] == TRUE) { - RxEnDlyTargetFound[ByteLane] = TRUE; - NumBLWithTargetFound++; - RxEnDlyTargetValue[ByteLane] = FinalRxEnCycle[ByteLane]; - } else { - RxEnDlyTargetFound[ByteLane] = FALSE; - } - } else { - // BL has already failed and passed, so increment both flags - NumBLWithTargetFound++; - } - } - IDS_HDT_CONSOLE (MEM_FLOW, "\n"); - // Check for exit condition - if (NumBLWithTargetFound == MaxByteLanes) { - // Exit condition found, so setting new RDQS based on RxEn-0x10 \n\n - IDS_HDT_CONSOLE (MEM_FLOW, "\n\t\t\t Setting new RDQS based on FinalRxEnCycle \n\n"); - // 5 A. DqsRcvEnCycle = the total delay value of the pass result. - // B. Program D18F2x9C_x0000_00[2A:10]_dct[1:0][DqsRcvEnGrossDelay, DqsRcvEnFineDelay] = - // DqsRcvEnCycle - 0x10. - NBPtr->RdDqsDlyRetrnStat = RDDQSDLY_RTN_NEEDED; - MemTRdPosRxEnSeedCheckRxEndly3 (TechPtr); - IDS_HDT_CONSOLE (MEM_FLOW, "\n"); - status = TRUE; - break; - } else { - status = FALSE; - } - } - // Check for exit condition - if (NumBLWithTargetFound == MaxByteLanes) { - status = TRUE; - break; - } else { - status = FALSE; - } - IDS_HDT_CONSOLE (MEM_FLOW, "\n"); - } - TechPtr->NBPtr->MCTPtr->ErrStatus[EsbNoDqsPos] = EsbNoDqsPosSave; - if (i == MAX_POS_RX_EN_SEED_GROSS_RANGE) { - TechPtr->NBPtr->MCTPtr->ErrStatus[EsbNoDqsPos] = TRUE; - } - - // 6. Program D18F2x9C_x0D0F_0[F,8:0]30_dct[1:0][BlockRxDqsLock] = 0. - NBPtr->SetBitField (NBPtr, BFBlockRxDqsLock, 0); - IDS_HDT_CONSOLE (MEM_FLOW, "\nEnd HW RxEn Seedless training\n\n"); - return status; -} diff --git a/src/vendorcode/amd/agesa/f12/Proc/Mem/Tech/mttml.c b/src/vendorcode/amd/agesa/f12/Proc/Mem/Tech/mttml.c deleted file mode 100644 index 9acbc90ef7..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/Mem/Tech/mttml.c +++ /dev/null @@ -1,253 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * mttml.c - * - * Technology Max Latency Training support - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: (Mem/Tech) - * @e \$Revision: 48371 $ @e \$Date: 2011-03-08 07:37:52 +0800 (Tue, 08 Mar 2011) $ - * - **/ -/***************************************************************************** -* -* Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* *************************************************************************** -* -*/ - -/* - *---------------------------------------------------------------------------- - * MODULES USED - * - *---------------------------------------------------------------------------- - */ - - - -#include "AGESA.h" -#include "Ids.h" -#include "mm.h" -#include "mn.h" -#include "mu.h" -#include "mt.h" -#include "merrhdl.h" -#include "GeneralServices.h" -#include "Filecode.h" -CODE_GROUP (G1_PEICC) -RDATA_GROUP (G1_PEICC) - -#define FILECODE PROC_MEM_TECH_MTTML_FILECODE -/*---------------------------------------------------------------------------- - * DEFINITIONS AND MACROS - * - *---------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------- - * TYPEDEFS AND STRUCTURES - * - *---------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------- - * PROTOTYPES OF LOCAL FUNCTIONS - * - *---------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------- - * EXPORTED FUNCTIONS - * - *---------------------------------------------------------------------------- - */ -/* -----------------------------------------------------------------------------*/ -/** - * - * This function trains Max latency for all dies - * - * @param[in,out] *TechPtr - Pointer to the MEM_TECH_BLOCK - * - * @return TRUE - No fatal error occurs. - * @return FALSE - Fatal error occurs. - */ - -BOOLEAN -MemTTrainMaxLatency ( - IN OUT MEM_TECH_BLOCK *TechPtr - ) -{ - UINT32 TestAddrRJ16; - UINT8 Dct; - UINT8 ChipSel; - UINT8 *PatternBufPtr; - UINT8 *TestBufferPtr; - UINT16 CalcMaxLatDly; - UINT16 MaxLatDly; - UINT16 MaxLatLimit; - UINT16 Margin; - UINT16 CurTest; - UINT16 _CL_; - UINT8 TimesFail; - UINT8 TimesRetrain; - UINT16 i; - - MEM_DATA_STRUCT *MemPtr; - DIE_STRUCT *MCTPtr; - MEM_NB_BLOCK *NBPtr; - - NBPtr = TechPtr->NBPtr; - MCTPtr = NBPtr->MCTPtr; - MemPtr = NBPtr->MemPtr; - TechPtr->TrainingType = TRN_MAX_READ_LATENCY; - TimesRetrain = DEFAULT_TRAINING_TIMES; - IDS_OPTION_HOOK (IDS_MEM_RETRAIN_TIMES, &TimesRetrain, &MemPtr->StdHeader); - - IDS_HDT_CONSOLE (MEM_STATUS, "\nStart MaxRdLat training\n"); - // Set environment settings before training - AGESA_TESTPOINT (TpProcMemMaxRdLatencyTraining, &(MemPtr->StdHeader)); - MemTBeginTraining (TechPtr); - // - // Initialize the Training Pattern - // - if (AGESA_SUCCESS != NBPtr->TrainingPatternInit (NBPtr)) { - return (BOOLEAN) (MCTPtr->ErrCode < AGESA_FATAL); - } - TechPtr->PatternLength = (MCTPtr->Status[Sb128bitmode]) ? 6 : 3; - // - // Setup hardware training engine (if applicable) - // - NBPtr->FamilySpecificHook[SetupHwTrainingEngine] (NBPtr, &TechPtr->TrainingType); - - MaxLatDly = 0; - _CL_ = TechPtr->PatternLength; - PatternBufPtr = TechPtr->PatternBufPtr; - TestBufferPtr = TechPtr->TestBufPtr; - // - // Begin max latency training - // - for (Dct = 0; Dct < NBPtr->DctCount; Dct++) { - if (MCTPtr->Status[Sb128bitmode] && (Dct != 0)) { - break; - } - - IDS_HDT_CONSOLE (MEM_STATUS, "\tDct %d\n", Dct); - NBPtr->SwitchDCT (NBPtr, Dct); - - if (NBPtr->DCTPtr->Timings.DctMemSize != 0) { - if (TechPtr->FindMaxDlyForMaxRdLat (TechPtr, &ChipSel)) { - TechPtr->ChipSel = ChipSel; - if (NBPtr->GetSysAddr (NBPtr, ChipSel, &TestAddrRJ16)) { - IDS_HDT_CONSOLE (MEM_STATUS, "\t\tCS %d\n", ChipSel); - IDS_HDT_CONSOLE (MEM_FLOW, "\t\t\tWrite to address: %04x0000\n", TestAddrRJ16); - - // Write the test patterns - AGESA_TESTPOINT (TpProcMemMaxRdLatWritePattern, &(MemPtr->StdHeader)); - NBPtr->WritePattern (NBPtr, TestAddrRJ16, PatternBufPtr, _CL_); - - // Sweep max latency delays - NBPtr->getMaxLatParams (NBPtr, TechPtr->MaxDlyForMaxRdLat, &CalcMaxLatDly, &MaxLatLimit, &Margin); - AGESA_TESTPOINT (TpProcMemMaxRdLatStartSweep, &(MemPtr->StdHeader)); - - TimesFail = 0; - ERROR_HANDLE_RETRAIN_BEGIN (TimesFail, TimesRetrain) - { - MaxLatDly = CalcMaxLatDly; - for (i = 0; i < (MaxLatLimit - CalcMaxLatDly); i++) { - NBPtr->SetBitField (NBPtr, BFMaxLatency, MaxLatDly); - IDS_HDT_CONSOLE (MEM_FLOW, "\t\t\tDly %3x", MaxLatDly); - TechPtr->ResetDCTWrPtr (TechPtr, 6); - - AGESA_TESTPOINT (TpProcMemMaxRdLatReadPattern, &(MemPtr->StdHeader)); - NBPtr->ReadPattern (NBPtr, TestBufferPtr, TestAddrRJ16, _CL_); - AGESA_TESTPOINT (TpProcMemMaxRdLatTestPattern, &(MemPtr->StdHeader)); - CurTest = NBPtr->CompareTestPattern (NBPtr, TestBufferPtr, PatternBufPtr, _CL_ * 64); - NBPtr->FlushPattern (NBPtr, TestAddrRJ16, _CL_); - - if (NBPtr->IsSupported[ReverseMaxRdLatTrain]) { - // Reverse training decrements MaxLatDly whenever the test passes - // and uses the last passing MaxLatDly as left edge - if (CurTest == 0xFFFF) { - IDS_HDT_CONSOLE (MEM_FLOW, " P"); - if (MaxLatDly == 0) { - break; - } else { - MaxLatDly--; - } - } - } else { - // Traditional training increments MaxLatDly until the test passes - // and uses it as left edge - if (CurTest == 0xFFFF) { - IDS_HDT_CONSOLE (MEM_FLOW, " P"); - break; - } else { - MaxLatDly++; - } - } - IDS_HDT_CONSOLE (MEM_FLOW, "\n"); - }// End of delay sweep - ERROR_HANDLE_RETRAIN_END ((MaxLatDly >= MaxLatLimit), TimesFail) - } - - AGESA_TESTPOINT (TpProcMemMaxRdLatSetDelay, &(MemPtr->StdHeader)); - - if (MaxLatDly >= MaxLatLimit) { - PutEventLog (AGESA_ERROR, MEM_ERROR_MAX_LAT_NO_WINDOW, NBPtr->Node, NBPtr->Dct, NBPtr->Channel, 0, &NBPtr->MemPtr->StdHeader); - SetMemError (AGESA_ERROR, MCTPtr); - NBPtr->DCTPtr->Timings.CsTrainFail |= NBPtr->DCTPtr->Timings.CsPresent; - MCTPtr->ChannelTrainFail |= (UINT32)1 << Dct; - if (!NBPtr->MemPtr->ErrorHandling (MCTPtr, NBPtr->Dct, EXCLUDE_ALL_CHIPSEL, &NBPtr->MemPtr->StdHeader)) { - return FALSE; - } - } else { - NBPtr->FamilySpecificHook[AddlMaxRdLatTrain] (NBPtr, &TestAddrRJ16); - - MaxLatDly = MaxLatDly + Margin; - if (NBPtr->IsSupported[ReverseMaxRdLatTrain]) { - MaxLatDly++; // Add 1 to get back to the last passing value - } - // Set final delays - NBPtr->SetBitField (NBPtr, BFMaxLatency, MaxLatDly); - IDS_HDT_CONSOLE (MEM_FLOW, "\t\tFinal MaxRdLat: %03x\n", MaxLatDly); - } - } - } - } - } - - // Restore environment settings after training - MemTEndTraining (TechPtr); - IDS_HDT_CONSOLE (MEM_FLOW, "End MaxRdLat training\n\n"); - // - // Finalize the Pattern - // - NBPtr->TrainingPatternFinalize (NBPtr); - return (BOOLEAN) (MCTPtr->ErrCode < AGESA_FATAL); -} diff --git a/src/vendorcode/amd/agesa/f12/Proc/Mem/Tech/mttoptsrc.c b/src/vendorcode/amd/agesa/f12/Proc/Mem/Tech/mttoptsrc.c deleted file mode 100644 index fb162c35c7..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/Mem/Tech/mttoptsrc.c +++ /dev/null @@ -1,425 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * mttoptsrc.c - * - * New Technology Software based DQS receiver enable training - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: (Mem/Tech) - * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $ - * - **/ -/***************************************************************************** -* -* Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* *************************************************************************** -* -*/ - -/* - *---------------------------------------------------------------------------- - * MODULES USED - * - *---------------------------------------------------------------------------- - */ - - - -#include "AGESA.h" -#include "AdvancedApi.h" -#include "Ids.h" -#include "mm.h" -#include "mn.h" -#include "mu.h" -#include "mt.h" -#include "merrhdl.h" -#include "Filecode.h" -CODE_GROUP (G1_PEICC) -RDATA_GROUP (G1_PEICC) - -#define FILECODE PROC_MEM_TECH_MTTOPTSRC_FILECODE -/*---------------------------------------------------------------------------- - * DEFINITIONS AND MACROS - * - *---------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------- - * TYPEDEFS AND STRUCTURES - * - *---------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------- - * PROTOTYPES OF LOCAL FUNCTIONS - * - *---------------------------------------------------------------------------- - */ - -BOOLEAN -STATIC -MemTDqsTrainOptRcvrEnSw ( - IN OUT MEM_TECH_BLOCK *TechPtr, - IN UINT8 Pass - ); - -BOOLEAN -MemTNewRevTrainingSupport ( - IN OUT MEM_TECH_BLOCK *TechPtr - ) -{ - return TRUE; -} - -/*---------------------------------------------------------------------------- - * EXPORTED FUNCTIONS - * - *---------------------------------------------------------------------------- - */ - -/* -----------------------------------------------------------------------------*/ -/** - * - * This function executes first pass of receiver enable training for all dies - * - * @param[in,out] *TechPtr - Pointer to the MEM_TECH_BLOCK - * - * @return TRUE - No fatal error occurs. - * @return FALSE - Fatal error occurs. - */ - -BOOLEAN -MemTTrainOptRcvrEnSwPass1 ( - IN OUT MEM_TECH_BLOCK *TechPtr - ) -{ - return MemTDqsTrainOptRcvrEnSw (TechPtr, 1); -} - -/*---------------------------------------------------------------------------- - * LOCAL FUNCTIONS - * - *---------------------------------------------------------------------------- - */ - -/* -----------------------------------------------------------------------------*/ -/** - * - * This function executes receiver enable training for a specific die - * - * @param[in,out] *TechPtr - Pointer to the MEM_TECH_BLOCK - * @param[in] Pass - Pass of the receiver training - * - * @return TRUE - No fatal error occurs. - * @return FALSE - Fatal error occurs. - */ -BOOLEAN -STATIC -MemTDqsTrainOptRcvrEnSw ( - IN OUT MEM_TECH_BLOCK *TechPtr, - IN UINT8 Pass - ) -{ - _16BYTE_ALIGN UINT8 PatternBuffer[6 * 64]; - UINT8 TestBuffer[256]; - UINT8 *PatternBufPtr[6]; - UINT8 *TempPtr; - UINT32 TestAddrRJ16[4]; - UINT32 TempAddrRJ16; - UINT32 RealAddr; - UINT16 CurTest[4]; - UINT8 Dct; - UINT8 Receiver; - UINT8 i; - UINT8 TimesFail; - UINT8 TimesRetrain; - UINT16 RcvrEnDly; - UINT16 MaxRcvrEnDly; - UINT16 RcvrEnDlyLimit; - UINT16 MaxDelayCha; - BOOLEAN IsDualRank; - BOOLEAN S0En; - BOOLEAN S1En; - - - MEM_DATA_STRUCT *MemPtr; - DIE_STRUCT *MCTPtr; - DCT_STRUCT *DCTPtr; - MEM_NB_BLOCK *NBPtr; - - NBPtr = TechPtr->NBPtr; - MemPtr = NBPtr->MemPtr; - MCTPtr = NBPtr->MCTPtr; - TechPtr->TrainingType = TRN_RCVR_ENABLE; - - - TempAddrRJ16 = 0; - TempPtr = NULL; - MaxDelayCha = 0; - TimesRetrain = DEFAULT_TRAINING_TIMES; - IDS_OPTION_HOOK (IDS_MEM_RETRAIN_TIMES, &TimesRetrain, &MemPtr->StdHeader); - - IDS_HDT_CONSOLE (MEM_STATUS, "\nStart Optimized SW RxEn training\n"); - // Set environment settings before training - MemTBeginTraining (TechPtr); - - PatternBufPtr[0] = PatternBufPtr[2] = PatternBuffer; - // These two patterns used for first Test Address - MemUFillTrainPattern (TestPattern0, PatternBufPtr[0], 64); - // Second Cacheline used for Dummy Read is the inverse of - // the first so that is is not mistaken for the real read - MemUFillTrainPattern (TestPattern1, PatternBufPtr[0] + 64, 64); - PatternBufPtr[1] = PatternBufPtr[3] = PatternBufPtr[0] + 128; - // These two patterns used for second Test Address - MemUFillTrainPattern (TestPattern1, PatternBufPtr[1], 64); - // Second Cacheline used for Dummy Read is the inverse of - // the first so that is is not mistaken for the real read - MemUFillTrainPattern (TestPattern0, PatternBufPtr[1] + 64, 64); - - // Fill pattern for flush after every sweep - PatternBufPtr[4] = PatternBufPtr[0] + 256; - MemUFillTrainPattern (TestPattern3, PatternBufPtr[4], 64); - - // Fill pattern for initial dummy read - PatternBufPtr[5] = PatternBufPtr[0] + 320; - MemUFillTrainPattern (TestPattern4, PatternBufPtr[5], 64); - - - // Begin receiver enable training - AGESA_TESTPOINT (TpProcMemReceiverEnableTraining, &(MemPtr->StdHeader)); - for (Dct = 0; Dct < NBPtr->DctCount; Dct++) { - IDS_HDT_CONSOLE (MEM_STATUS, "\tDct %d\n", Dct); - NBPtr->SwitchDCT (NBPtr, Dct); - DCTPtr = NBPtr->DCTPtr; - - // Set training bit - NBPtr->SetBitField (NBPtr, BFDqsRcvEnTrain, 1); - - // Relax Max Latency before training - NBPtr->SetMaxLatency (NBPtr, 0xFFFF); - - if (Pass == FIRST_PASS) { - TechPtr->InitDQSPos4RcvrEn (TechPtr); - } - - // there are four receiver pairs, loosely associated with chipselects. - Receiver = DCTPtr->Timings.CsEnabled ? 0 : 8; - for (; Receiver < 8; Receiver += 2) { - S0En = NBPtr->GetSysAddr (NBPtr, Receiver, &TestAddrRJ16[0]); - S1En = NBPtr->GetSysAddr (NBPtr, Receiver + 1, &TestAddrRJ16[2]); - if (S0En) { - TestAddrRJ16[1] = TestAddrRJ16[0] + BIGPAGE_X8_RJ16; - } - if (S1En) { - TestAddrRJ16[3] = TestAddrRJ16[2] + BIGPAGE_X8_RJ16; - } - if (S0En && S1En) { - IsDualRank = TRUE; - } else { - IsDualRank = FALSE; - } - if (S0En || S1En) { - IDS_HDT_CONSOLE (MEM_STATUS, "\t\tCS %d\n", Receiver); - - RcvrEnDlyLimit = 0x1FF; // @attention - limit depends on proc type - TechPtr->DqsRcvEnSaved = 0; - RcvrEnDly = RcvrEnDlyLimit; - RealAddr = 0; - - TechPtr->GetFirstPassVal = FALSE; - TechPtr->DqsRcvEnFirstPassVal = 0; - TechPtr->RevertPassVal = FALSE; - TechPtr->InitializeVariablesOpt (TechPtr); - - // Write the test patterns - AGESA_TESTPOINT (TpProcMemRcvrWritePattern, &(MemPtr->StdHeader)); - IDS_HDT_CONSOLE (MEM_FLOW, "\t\t\tWrite to addresses: "); - for (i = (S0En ? 0 : 2); i < (S1En ? 4 : 2); i++) { - RealAddr = MemUSetUpperFSbase (TestAddrRJ16[i], MemPtr); - // One cacheline of data to be tested and one of dummy data - MemUWriteCachelines (RealAddr, PatternBufPtr[i], 2); - // This is dummy data with a different pattern used for the first dummy read. - MemUWriteCachelines (RealAddr + 128, PatternBufPtr[5], 1); - IDS_HDT_CONSOLE (MEM_FLOW, " %04x0000 ", TestAddrRJ16[i]); - } - IDS_HDT_CONSOLE (MEM_FLOW, "\n"); - - // Sweep receiver enable delays - AGESA_TESTPOINT (TpProcMemRcvrStartSweep, &(MemPtr->StdHeader)); - TimesFail = 0; - ERROR_HANDLE_RETRAIN_BEGIN (TimesFail, TimesRetrain) - { - TechPtr->LoadInitialRcvrEnDlyOpt (TechPtr, Receiver); - while (!TechPtr->CheckRcvrEnDlyLimitOpt (TechPtr)) { - AGESA_TESTPOINT (TpProcMemRcvrSetDelay, &(MemPtr->StdHeader)); - TechPtr->SetRcvrEnDlyOpt (TechPtr, Receiver, RcvrEnDly); - // Read and compare the first beat of data - for (i = (S0En ? 0 : 2); i < (S1En ? 4 : 2); i++) { - AGESA_TESTPOINT (TpProcMemRcvrReadPattern, &(MemPtr->StdHeader)); - RealAddr = MemUSetUpperFSbase (TestAddrRJ16[i], MemPtr); - // - // Issue dummy cacheline reads - // - MemUReadCachelines (TestBuffer + 128, RealAddr + 128, 1); - MemUReadCachelines (TestBuffer, RealAddr, 1); - MemUProcIOClFlush (TestAddrRJ16[i], 2, MemPtr); - // - // Perform actual read which will be compared - // - MemUReadCachelines (TestBuffer + 64, RealAddr + 64, 1); - AGESA_TESTPOINT (TpProcMemRcvrTestPattern, &(MemPtr->StdHeader)); - CurTest[i] = TechPtr->Compare1ClPatternOpt (TechPtr, TestBuffer + 64 , PatternBufPtr[i] + 64, i, Receiver, S1En); - // Due to speculative execution during MemUReadCachelines, we must - // flush one more cache line than we read. - MemUProcIOClFlush (TestAddrRJ16[i], 4, MemPtr); - TechPtr->ResetDCTWrPtr (TechPtr, Receiver); - - // - // Swap the test pointers such that even and odd steps alternate. - // - if ((i % 2) == 0) { - TempPtr = PatternBufPtr[i]; - PatternBufPtr[i] = PatternBufPtr[i + 1]; - - TempAddrRJ16 = TestAddrRJ16[i]; - TestAddrRJ16[i] = TestAddrRJ16[i + 1]; - } else { - PatternBufPtr[i] = TempPtr; - TestAddrRJ16[i] = TempAddrRJ16; - } - } - } // End of delay sweep - ERROR_HANDLE_RETRAIN_END (!TechPtr->SetSweepErrorOpt (TechPtr, Receiver, Dct, TRUE), TimesFail) - } - - if (!TechPtr->SetSweepErrorOpt (TechPtr, Receiver, Dct, FALSE)) { - return FALSE; - } - - TechPtr->LoadRcvrEnDlyOpt (TechPtr, Receiver); // set final delays - // - // Flush AA and 55 patterns by reading a dummy pattern to fill in FIFO - // - // Aquire a new FSBase, based on the last test address that we stored. - RealAddr = MemUSetUpperFSbase (TempAddrRJ16, MemPtr); - ASSERT (RealAddr != 0); - MemUWriteCachelines (RealAddr, PatternBufPtr[4], 1); - MemUWriteCachelines (RealAddr + 64, PatternBufPtr[4], 1); - MemUReadCachelines (TestBuffer, RealAddr, 2); - // Due to speculative execution during MemUReadCachelines, we must - // flush one more cache line than we read. - MemUProcIOClFlush (TempAddrRJ16, 3, MemPtr); - } - } // End while Receiver < 8 - - // Clear training bit when done - NBPtr->SetBitField (NBPtr, BFDqsRcvEnTrain, 0); - - // Set Max Latency for both channels - MaxRcvrEnDly = TechPtr->GetMaxValueOpt (TechPtr); - IDS_HDT_CONSOLE (MEM_FLOW, "\t\tMaxRcvrEnDly: %03x\n", MaxRcvrEnDly); - if (MCTPtr->GangedMode) { - if (Dct == 0) { - MaxDelayCha = MaxRcvrEnDly; - } else if (MaxRcvrEnDly > MaxDelayCha) { - NBPtr->SwitchDCT (NBPtr, 0); - NBPtr->SetMaxLatency (NBPtr, MaxRcvrEnDly); - } - } else { - NBPtr->SetMaxLatency (NBPtr, MaxRcvrEnDly); - } - TechPtr->ResetDCTWrPtr (TechPtr, 6); - } - - // Restore environment settings after training - MemTEndTraining (TechPtr); - IDS_HDT_CONSOLE (MEM_FLOW, "End Optimized SW RxEn training\n\n"); - return (BOOLEAN) (MCTPtr->ErrCode < AGESA_FATAL); -} - -/*----------------------------------------------------------------------------- - * - * This function saves passing DqsRcvEnDly values to the stack - * - * @param[in,out] *TechPtr - Pointer to the MEM_TECH_BLOCK - * @param[in] Receiver - Current Chip select value - * @param[in] RcvEnDly - receiver enable delay to be saved - * @param[in] cmpResultRank0 - compare result for Rank 0 - * @param[in] cmpResultRank0 - compare result for Rank 1 - * - * @retval TRUE - All bytelanes pass - * FALSE - Some bytelanes fail - * ---------------------------------------------------------------------------- - */ - -BOOLEAN -MemTSaveRcvrEnDlyByteFilterOpt ( - IN OUT MEM_TECH_BLOCK *TechPtr, - IN UINT8 Receiver, - IN UINT16 RcvEnDly, - IN UINT16 CmpResultRank0, - IN UINT16 CmpResultRank1 - ) -{ - UINT8 i; - UINT8 Passed; - UINT8 Dimm; - CH_DEF_STRUCT *ChannelPtr; - - ASSERT (Receiver < MAX_CS_PER_CHANNEL); - ChannelPtr = TechPtr->NBPtr->ChannelPtr; - - Passed = (UINT8) ((CmpResultRank0 & CmpResultRank1) & 0xFF); - - Dimm = Receiver >> 1; - - if (TechPtr->GetFirstPassVal && (RcvEnDly - TechPtr->DqsRcvEnFirstPassVal) >= 0x30) { - for (i = 0; i < 8; i++) { - ChannelPtr->RcvEnDlys[Dimm * TechPtr->DlyTableWidth () + i] = TechPtr->DqsRcvEnFirstPassVal + NEW_RECEIVER_FINAL_OFFSETVALUE; - } - TechPtr->DqsRcvEnSaved = 0xFF; - } - - if (Passed == 0xFF) { - if (!TechPtr->GetFirstPassVal) { - TechPtr->DqsRcvEnFirstPassVal = RcvEnDly; - TechPtr->GetFirstPassVal = TRUE; - } - return TRUE; - } else { - TechPtr->DqsRcvEnFirstPassVal = 0; - - // We have got first passing value, but later, we meet with glitch - if (TechPtr->GetFirstPassVal) { - TechPtr->DqsRcvEnFirstPassVal = 0xFF; - TechPtr->GetFirstPassVal = FALSE; - } - return FALSE; - } -} diff --git a/src/vendorcode/amd/agesa/f12/Proc/Mem/Tech/mttsrc.c b/src/vendorcode/amd/agesa/f12/Proc/Mem/Tech/mttsrc.c deleted file mode 100644 index 2f301786dc..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/Mem/Tech/mttsrc.c +++ /dev/null @@ -1,344 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * mttsrc.c - * - * Technology Software based DQS receiver enable training - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: (Mem/Tech) - * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $ - * - **/ -/***************************************************************************** -* -* Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* *************************************************************************** -* -*/ - -/* - *---------------------------------------------------------------------------- - * MODULES USED - * - *---------------------------------------------------------------------------- - */ - - - -#include "AGESA.h" -#include "AdvancedApi.h" -#include "Ids.h" -#include "mm.h" -#include "mn.h" -#include "mu.h" -#include "mt.h" -#include "GeneralServices.h" -#include "merrhdl.h" -#include "Filecode.h" -CODE_GROUP (G1_PEICC) -RDATA_GROUP (G1_PEICC) - -#define FILECODE PROC_MEM_TECH_MTTSRC_FILECODE -/*---------------------------------------------------------------------------- - * DEFINITIONS AND MACROS - * - *---------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------- - * TYPEDEFS AND STRUCTURES - * - *---------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------- - * PROTOTYPES OF LOCAL FUNCTIONS - * - *---------------------------------------------------------------------------- - */ - -BOOLEAN -STATIC -MemTDqsTrainRcvrEnSw ( - IN OUT MEM_TECH_BLOCK *TechPtr, - IN UINT8 Pass - ); - -/*---------------------------------------------------------------------------- - * EXPORTED FUNCTIONS - * - *---------------------------------------------------------------------------- - */ - -/* -----------------------------------------------------------------------------*/ -/** - * - * This function executes first pass of receiver enable training for all dies - * - * @param[in,out] *TechPtr - Pointer to the MEM_TECH_BLOCK - * - * @return TRUE - No fatal error occurs. - * @return FALSE - Fatal error occurs. - */ - -BOOLEAN -MemTTrainRcvrEnSwPass1 ( - IN OUT MEM_TECH_BLOCK *TechPtr - ) -{ - return MemTDqsTrainRcvrEnSw (TechPtr, 1); -} - -/*---------------------------------------------------------------------------- - * LOCAL FUNCTIONS - * - *---------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------- - * LOCAL FUNCTIONS - * - *---------------------------------------------------------------------------- - */ - -/* -----------------------------------------------------------------------------*/ -/** - * - * This function executes receiver enable training for a specific die - * - * @param[in,out] *TechPtr - Pointer to the MEM_TECH_BLOCK - * @param[in] Pass - Pass of the receiver training - * - * @return TRUE - No fatal error occurs. - * @return FALSE - Fatal error occurs. - */ -BOOLEAN -STATIC -MemTDqsTrainRcvrEnSw ( - IN OUT MEM_TECH_BLOCK *TechPtr, - IN UINT8 Pass - ) -{ - _16BYTE_ALIGN UINT8 PatternBuffer[3 * 64]; - UINT8 TestBuffer[120]; - UINT8 *PatternBufPtr[4]; - UINT8 *TempPtr; - UINT32 TestAddrRJ16[4]; - UINT32 TempAddrRJ16; - UINT32 RealAddr; - UINT16 CurTest[4]; - UINT8 Dct; - UINT8 Receiver; - UINT8 i; - UINT8 TimesFail; - UINT8 TimesRetrain; - UINT16 RcvrEnDly; - UINT16 MaxRcvrEnDly; - UINT16 RcvrEnDlyLimit; - UINT16 MaxDelayCha; - BOOLEAN IsDualRank; - BOOLEAN S0En; - BOOLEAN S1En; - UINT8 MaxFilterDly; - - MEM_DATA_STRUCT *MemPtr; - DIE_STRUCT *MCTPtr; - DCT_STRUCT *DCTPtr; - MEM_NB_BLOCK *NBPtr; - - NBPtr = TechPtr->NBPtr; - MemPtr = NBPtr->MemPtr; - MCTPtr = NBPtr->MCTPtr; - TechPtr->TrainingType = TRN_RCVR_ENABLE; - - - TempAddrRJ16 = 0; - TempPtr = NULL; - MaxDelayCha = 0; - MaxFilterDly = TechPtr->MaxFilterDly; - RcvrEnDlyLimit = NBPtr->RcvrEnDlyLimit; - TimesRetrain = DEFAULT_TRAINING_TIMES; - IDS_OPTION_HOOK (IDS_MEM_RETRAIN_TIMES, &TimesRetrain, &MemPtr->StdHeader); - - IDS_HDT_CONSOLE (MEM_STATUS, "\nStart SW RxEn training\n"); - // Set environment settings before training - MemTBeginTraining (TechPtr); - - PatternBufPtr[0] = PatternBufPtr[2] = PatternBuffer; - MemUFillTrainPattern (TestPattern0, PatternBufPtr[0], 64); - PatternBufPtr[1] = PatternBufPtr[3] = PatternBufPtr[0] + 128; - MemUFillTrainPattern (TestPattern1, PatternBufPtr[1], 64); - - // Begin receiver enable training - AGESA_TESTPOINT (TpProcMemReceiverEnableTraining, &(MemPtr->StdHeader)); - MaxRcvrEnDly = 0; - for (Dct = 0; Dct < NBPtr->DctCount; Dct++) { - IDS_HDT_CONSOLE (MEM_STATUS, "\tDct %d\n", Dct); - NBPtr->SwitchDCT (NBPtr, Dct); - DCTPtr = NBPtr->DCTPtr; - - // Set training bit - NBPtr->SetBitField (NBPtr, BFDqsRcvEnTrain, 1); - - // Relax Max Latency before training - NBPtr->SetMaxLatency (NBPtr, 0xFFFF); - - if (Pass == FIRST_PASS) { - TechPtr->InitDQSPos4RcvrEn (TechPtr); - } - - // there are four receiver pairs, loosely associated with chipselects. - Receiver = DCTPtr->Timings.CsEnabled ? 0 : 8; - for (; Receiver < 8; Receiver += 2) { - TechPtr->DqsRcvEnSaved = 0; - RcvrEnDly = RcvrEnDlyLimit; - S0En = NBPtr->GetSysAddr (NBPtr, Receiver, &TestAddrRJ16[0]); - S1En = NBPtr->GetSysAddr (NBPtr, Receiver + 1, &TestAddrRJ16[2]); - if (S0En) { - TestAddrRJ16[1] = TestAddrRJ16[0] + BIGPAGE_X8_RJ16; - } - if (S1En) { - TestAddrRJ16[3] = TestAddrRJ16[2] + BIGPAGE_X8_RJ16; - } - if (S0En && S1En) { - IsDualRank = TRUE; - } else { - IsDualRank = FALSE; - } - - if (S0En || S1En) { - IDS_HDT_CONSOLE (MEM_STATUS, "\t\tCS %d\n", Receiver); - - // Write the test patterns - AGESA_TESTPOINT (TpProcMemRcvrWritePattern, &(MemPtr->StdHeader)); - IDS_HDT_CONSOLE (MEM_FLOW, "\t\t\tWrite to addresses: "); - for (i = (S0En ? 0 : 2); i < (S1En ? 4 : 2); i++) { - RealAddr = MemUSetUpperFSbase (TestAddrRJ16[i], MemPtr); - MemUWriteCachelines (RealAddr, PatternBufPtr[i], 1); - IDS_HDT_CONSOLE (MEM_FLOW, " %04x0000 ", TestAddrRJ16[i]); - } - IDS_HDT_CONSOLE (MEM_FLOW, "\n"); - - // Initialize RcvrEnDly value and other DCT stored values - // MCTPtr->DqsRcvEnPass = Pass ? 0xFF : 0; - - // Sweep receiver enable delays - AGESA_TESTPOINT (TpProcMemRcvrStartSweep, &(MemPtr->StdHeader)); - TimesFail = 0; - ERROR_HANDLE_RETRAIN_BEGIN (TimesFail, TimesRetrain) - { - for (RcvrEnDly = 0; RcvrEnDly < RcvrEnDlyLimit; RcvrEnDly++) { - AGESA_TESTPOINT (TpProcMemRcvrSetDelay, &(MemPtr->StdHeader)); - TechPtr->SetRcvrEnDly (TechPtr, Receiver, RcvrEnDly); - IDS_HDT_CONSOLE (MEM_FLOW, "\t\t\tDly %3x", RcvrEnDly); - - // Read and compare the first beat of data - for (i = (S0En ? 0 : 2); i < (S1En ? 4 : 2); i++) { - AGESA_TESTPOINT (TpProcMemRcvrReadPattern, &(MemPtr->StdHeader)); - RealAddr = MemUSetUpperFSbase (TestAddrRJ16[i], MemPtr); - MemUReadCachelines (TestBuffer, RealAddr, 1); - AGESA_TESTPOINT (TpProcMemRcvrTestPattern, &(MemPtr->StdHeader)); - CurTest[i] = TechPtr->Compare1ClPattern (TechPtr, TestBuffer, PatternBufPtr[i]); - // Due to speculative execution during MemUReadCachelines, we must - // flush one more cache line than we read. - MemUProcIOClFlush (TestAddrRJ16[i], 2, MemPtr); - TechPtr->ResetDCTWrPtr (TechPtr, Receiver); - - // - // Swap the test pointers such that even and odd steps alternate. - // - if ((i % 2) == 0) { - TempPtr = PatternBufPtr[i]; - PatternBufPtr[i] = PatternBufPtr[i + 1]; - - TempAddrRJ16 = TestAddrRJ16[i]; - TestAddrRJ16[i] = TestAddrRJ16[i + 1]; - } else { - PatternBufPtr[i] = TempPtr; - TestAddrRJ16[i] = TempAddrRJ16; - } - } - - if (TechPtr->SaveRcvrEnDly (TechPtr, Receiver, RcvrEnDly, S0En ? (CurTest[0] & CurTest[1]) : 0xFFFF, S1En ? (CurTest[2] & CurTest[3]) : 0xFFFF)) { - // if all bytelanes pass - if (MaxRcvrEnDly < (RcvrEnDly - MaxFilterDly)) { - MaxRcvrEnDly = RcvrEnDly - MaxFilterDly; - } - break; - } - } // End of delay sweep - ERROR_HANDLE_RETRAIN_END ((RcvrEnDly > (RcvrEnDlyLimit - 1)), TimesFail) - } - - if (RcvrEnDly == RcvrEnDlyLimit) { - // no passing window - PutEventLog (AGESA_ERROR, MEM_ERROR_RCVR_EN_NO_PASSING_WINDOW_EQUAL_LIMIT, NBPtr->Node, NBPtr->Dct, NBPtr->Channel, 0, &NBPtr->MemPtr->StdHeader); - SetMemError (AGESA_ERROR, MCTPtr); - } - - if (RcvrEnDly > (RcvrEnDlyLimit - 1)) { - // passing window too narrow, too far delayed - PutEventLog (AGESA_ERROR, MEM_ERROR_RCVR_EN_VALUE_TOO_LARGE_LIMIT_LESS_ONE, NBPtr->Node, NBPtr->Dct, NBPtr->Channel, 0, &NBPtr->MemPtr->StdHeader); - SetMemError (AGESA_ERROR, MCTPtr); - DCTPtr->Timings.CsTrainFail |= DCTPtr->Timings.CsPresent & (UINT16) (3 << Receiver); - MCTPtr->ChannelTrainFail |= (UINT32)1 << Dct; - if (!NBPtr->MemPtr->ErrorHandling (MCTPtr, NBPtr->Dct, DCTPtr->Timings.CsTrainFail, &NBPtr->MemPtr->StdHeader)) { - return FALSE; - } - } - } - - TechPtr->LoadRcvrEnDly (TechPtr, Receiver); // set final delays - } // End while Receiver < 8 - - // Clear training bit when done - NBPtr->SetBitField (NBPtr, BFDqsRcvEnTrain, 0); - - // Set Max Latency for both channels - MaxRcvrEnDly += 0x20; // @attention - - IDS_HDT_CONSOLE (MEM_FLOW, "\t\tMaxRcvrEnDly: %03x\n", MaxRcvrEnDly); - if (MCTPtr->GangedMode) { - if (Dct == 0) { - MaxDelayCha = MaxRcvrEnDly; - } else if (MaxRcvrEnDly > MaxDelayCha) { - NBPtr->SwitchDCT (NBPtr, 0); - NBPtr->SetMaxLatency (NBPtr, MaxRcvrEnDly); - } - } else { - NBPtr->SetMaxLatency (NBPtr, MaxRcvrEnDly); - } - TechPtr->ResetDCTWrPtr (TechPtr, 6); - } - - // Restore environment settings after training - MemTEndTraining (TechPtr); - IDS_HDT_CONSOLE (MEM_FLOW, "End SW RxEn training\n\n"); - return (BOOLEAN) (MCTPtr->ErrCode < AGESA_FATAL); -} - diff --git a/src/vendorcode/amd/agesa/f12/Proc/Mem/ma.h b/src/vendorcode/amd/agesa/f12/Proc/Mem/ma.h deleted file mode 100644 index eb48535ac4..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/Mem/ma.h +++ /dev/null @@ -1,316 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * ma.h - * - * ARDK common header file - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: (Mem) - * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $ - * - **/ -/***************************************************************************** -* -* Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* *************************************************************************** -* -*/ - -#ifndef _MA_H_ -#define _MA_H_ - -/*---------------------------------------------------------------------------- - * Mixed (DEFINITIONS AND MACROS / TYPEDEFS, STRUCTURES, ENUMS) - * - *---------------------------------------------------------------------------- - */ - -/*----------------------------------------------------------------------------- - * DEFINITIONS AND MACROS - * - *----------------------------------------------------------------------------- - */ - - -#define MAX_CS_PER_CHANNEL 8 ///< Max CS per channel -/*---------------------------------------------------------------------------- - * TYPEDEFS, STRUCTURES, ENUMS - * - *---------------------------------------------------------------------------- - */ - -/** MARDK Structure*/ -typedef struct { - UINT16 Speed; ///< Dram speed in MHz - UINT8 Loads; ///< Number of Data Loads - UINT32 AddrTmg; ///< Address Timing value - UINT32 Odc; ///< Output Driver Compensation Value -} PSCFG_ENTRY; - -/** MARDK Structure*/ -typedef struct { - UINT16 Speed; ///< Dram speed in MHz - UINT8 Loads; ///< Number of Data Loads - UINT32 AddrTmg; ///< Address Timing value - UINT32 Odc; ///< Output Driver Compensation Value - UINT8 Dimms; ///< Number of Dimms -} ADV_PSCFG_ENTRY; - -/** MARDK Structure for RDIMMs*/ -typedef struct { - UINT16 Speed; ///< Dram speed in MHz - UINT16 DIMMRankType; ///< Bitmap of Ranks //Bit0-3:DIMM0(1:SR, 2:DR, 4:QR, 0:No Dimm, 0xF:Any), Bit4-7:DIMM1, Bit8-11:DIMM2, Bit12-16:DIMM3 - UINT32 AddrTmg; ///< Address Timing value - UINT16 RC2RC8; ///< RC2 and RC8 value //High byte: 1st pair value, Low byte: 2nd pair value - UINT8 Dimms; ///< Number of Dimms -} ADV_R_PSCFG_ENTRY; - -/** MARDK Structure*/ -typedef struct { - UINT16 DIMMRankType; ///< Bitmap of Ranks //Bit0-3:DIMM0(1:SR, 2:DR, 4:QR, 0:No Dimm, 0xF:Any), Bit4-7:DIMM1, Bit8-11:DIMM2, Bit12-16:DIMM3 - UINT32 PhyRODTCSLow; ///< Fn2_9C 180 - UINT32 PhyRODTCSHigh; ///< Fn2_9C 181 - UINT32 PhyWODTCSLow; ///< Fn2_9C 182 - UINT32 PhyWODTCSHigh; ///< Fn2_9C 183 - UINT8 Dimms; ///< Number of Dimms -} ADV_PSCFG_ODT_ENTRY; - -/** MARDK Structure for Write Levelization ODT*/ -typedef struct { - UINT16 DIMMRankType; ///< Bitmap of Ranks //Bit0-3:DIMM0(1:SR, 2:DR, 4:QR, 0:No Dimm, 0xF:Any), Bit4-7:DIMM1, Bit8-11:DIMM2, Bit12-16:DIMM3 - UINT8 PhyWrLvOdt[MAX_CS_PER_CHANNEL/2]; ///< WrLvOdt (Fn2_9C_0x08[11:8]) Value for each Dimm - UINT8 Dimms; ///< Number of Dimms -} ADV_R_PSCFG_WL_ODT_ENTRY; - -/*---------------------------------------------------------------------------- - * FUNCTIONS PROTOTYPE - * - *---------------------------------------------------------------------------- - */ - -AGESA_STATUS -MemAGetPsCfgDef ( - IN OUT MEM_DATA_STRUCT *MemData, - IN UINT8 SocketID, - IN OUT CH_DEF_STRUCT *CurrentChannel - ); - -AGESA_STATUS -MemAGetPsCfgRDr2 ( - IN OUT MEM_DATA_STRUCT *MemData, - IN UINT8 SocketID, - IN OUT CH_DEF_STRUCT *CurrentChannel - ); - -AGESA_STATUS -MemAGetPsCfgRDr3 ( - IN OUT MEM_DATA_STRUCT *MemData, - IN UINT8 SocketID, - IN OUT CH_DEF_STRUCT *CurrentChannel - ); - -AGESA_STATUS -MemAGetPsCfgUDr3 ( - IN OUT MEM_DATA_STRUCT *MemData, - IN UINT8 SocketID, - IN OUT CH_DEF_STRUCT *CurrentChannel - ); - -AGESA_STATUS -MemAGetPsCfgSDA2 ( - IN OUT MEM_DATA_STRUCT *MemData, - IN UINT8 SocketID, - IN OUT CH_DEF_STRUCT *CurrentChannel - ); - -AGESA_STATUS -MemAGetPsCfgSDA3 ( - IN OUT MEM_DATA_STRUCT *MemData, - IN UINT8 SocketID, - IN OUT CH_DEF_STRUCT *CurrentChannel - ); - -AGESA_STATUS -MemAGetPsCfgSNi3 ( - IN OUT MEM_DATA_STRUCT *MemData, - IN UINT8 SocketID, - IN OUT CH_DEF_STRUCT *CurrentChannel - ); - -AGESA_STATUS -MemAGetPsCfgUNi3 ( - IN OUT MEM_DATA_STRUCT *MemData, - IN UINT8 SocketID, - IN OUT CH_DEF_STRUCT *CurrentChannel - ); - -AGESA_STATUS -MemAGetPsCfgSRb3 ( - IN OUT MEM_DATA_STRUCT *MemData, - IN UINT8 SocketID, - IN OUT CH_DEF_STRUCT *CurrentChannel - ); - -AGESA_STATUS -MemAGetPsCfgURb3 ( - IN OUT MEM_DATA_STRUCT *MemData, - IN UINT8 SocketID, - IN OUT CH_DEF_STRUCT *CurrentChannel - ); - -AGESA_STATUS -MemAGetPsCfgSPh3 ( - IN OUT MEM_DATA_STRUCT *MemData, - IN UINT8 SocketID, - IN OUT CH_DEF_STRUCT *CurrentChannel - ); - -AGESA_STATUS -MemAGetPsCfgUPh3 ( - IN OUT MEM_DATA_STRUCT *MemData, - IN UINT8 SocketID, - IN OUT CH_DEF_STRUCT *CurrentChannel - ); - -AGESA_STATUS -MemAGetPsCfgUDA3 ( - IN OUT MEM_DATA_STRUCT *MemData, - IN UINT8 SocketID, - IN OUT CH_DEF_STRUCT *CurrentChannel - ); - -AGESA_STATUS -MemAGetPsCfgRHy3 ( - IN OUT MEM_DATA_STRUCT *MemData, - IN UINT8 SocketID, - IN OUT CH_DEF_STRUCT *CurrentChannel - ); - -AGESA_STATUS -MemAGetPsCfgUHy3 ( - IN OUT MEM_DATA_STRUCT *MemData, - IN UINT8 SocketID, - IN OUT CH_DEF_STRUCT *CurrentChannel - ); - -AGESA_STATUS -MemAGetPsCfgRC32_3 ( - IN OUT MEM_DATA_STRUCT *MemData, - IN UINT8 SocketID, - IN OUT CH_DEF_STRUCT *CurrentChannel - ); - -AGESA_STATUS -MemAGetPsCfgUC32_3 ( - IN OUT MEM_DATA_STRUCT *MemData, - IN UINT8 SocketID, - IN OUT CH_DEF_STRUCT *CurrentChannel - ); - -AGESA_STATUS -MemAGetPsCfgSLN3 ( - IN OUT MEM_DATA_STRUCT *MemData, - IN UINT8 SocketID, - IN OUT CH_DEF_STRUCT *CurrentChannel - ); - -AGESA_STATUS -MemAGetPsCfgULN3 ( - IN OUT MEM_DATA_STRUCT *MemData, - IN UINT8 SocketID, - IN OUT CH_DEF_STRUCT *CurrentChannel - ); - -AGESA_STATUS -MemAGetPsCfgSON3 ( - IN OUT MEM_DATA_STRUCT *MemData, - IN UINT8 SocketID, - IN OUT CH_DEF_STRUCT *CurrentChannel - ); - -AGESA_STATUS -MemAGetPsCfgUON3 ( - IN OUT MEM_DATA_STRUCT *MemData, - IN UINT8 SocketID, - IN OUT CH_DEF_STRUCT *CurrentChannel - ); - -AGESA_STATUS -MemAGetPsCfgROr3 ( - IN OUT MEM_DATA_STRUCT *MemData, - IN UINT8 SocketID, - IN OUT CH_DEF_STRUCT *CurrentChannel - ); - -AGESA_STATUS -MemAGetPsCfgUOr3 ( - IN OUT MEM_DATA_STRUCT *MemData, - IN UINT8 SocketID, - IN OUT CH_DEF_STRUCT *CurrentChannel - ); - -UINT16 -MemAGetPsRankType ( - IN CH_DEF_STRUCT *CurrentChannel - ); - -AGESA_STATUS -MemRecNGetPsCfgDef ( - IN OUT MEM_DATA_STRUCT *MemData, - IN UINT8 SocketID, - IN OUT CH_DEF_STRUCT *CurrentChannel - ); - -UINT16 -MemRecNGetPsRankType ( - IN CH_DEF_STRUCT *CurrentChannel - ); - -AGESA_STATUS -MemRecNGetPsCfgUDIMM3Nb ( - IN OUT MEM_DATA_STRUCT *MemData, - IN UINT8 SocketID, - IN OUT CH_DEF_STRUCT *CurrentChannel - ); - -AGESA_STATUS -MemRecNGetPsCfgSODIMM3Nb ( - IN OUT MEM_DATA_STRUCT *MemData, - IN UINT8 SocketID, - IN OUT CH_DEF_STRUCT *CurrentChannel - ); - -AGESA_STATUS -MemRecNGetPsCfgRDIMM3Nb ( - IN OUT MEM_DATA_STRUCT *MemData, - IN UINT8 SocketID, - IN OUT CH_DEF_STRUCT *CurrentChannel - ); - -#endif /* _MA_H_ */ diff --git a/src/vendorcode/amd/agesa/f12/Proc/Mem/memPage.h b/src/vendorcode/amd/agesa/f12/Proc/Mem/memPage.h deleted file mode 100644 index c1efba0189..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/Mem/memPage.h +++ /dev/null @@ -1,57 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * Create outline and references for Memory Component mainpage documentation. - * - * Design guides, maintenance guides, and general documentation, are - * collected using this file onto the documentation mainpage. - * This file contains doxygen comment blocks, only. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: Documentation - * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $ - * - */ -/* - ****************************************************************************** - * - * Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - ****************************************************************************** - */ - -/** - * @page memmain Memory Component Documentation - * - * Additional documentation for the Memory component consists of - * - * - Maintenance Guides: - * - add here >>> - * - Design Guides: - * - add here >>> - * - */ diff --git a/src/vendorcode/amd/agesa/f12/Proc/Mem/merrhdl.h b/src/vendorcode/amd/agesa/f12/Proc/Mem/merrhdl.h deleted file mode 100644 index 0d309ce122..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/Mem/merrhdl.h +++ /dev/null @@ -1,103 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * mmerrhdl.h - * - * main error handling - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: (Mem) - * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $ - * - **/ -/***************************************************************************** - * - * Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * *************************************************************************** - * - */ - -#ifndef _MMERRHDL_H_ -#define _MMERRHDL_H_ - -/*---------------------------------------------------------------------------- - * Mixed (DEFINITIONS AND MACROS / TYPEDEFS, STRUCTURES, ENUMS) - * - *---------------------------------------------------------------------------- - */ - -/*----------------------------------------------------------------------------- - * DEFINITIONS AND MACROS - * - *----------------------------------------------------------------------------- - */ -#define EXCLUDE_ALL_DCT 0xFF -#define EXCLUDE_ALL_CHIPSEL 0xFF - -/// default times of training -#define DEFAULT_TRAINING_TIMES 1 - -/// number of us to wait in parallel training -#define PARALLEL_TRAINING_TIMEOUT 60000000 - -/// number of us to wait in PCI space access -#define PCI_ACCESS_TIMEOUT 10000000 -/// number of us to wait in special PCI space access which takes much longer than others -#define SPECIAL_PCI_ACCESS_TIMEOUT 20000000 - -/// Beginning of retrain handling, must be ended with the ending of the handling -#define ERROR_HANDLE_RETRAIN_BEGIN(counter, limit) while (counter < limit) - -/// Ending of retrain handling -#define ERROR_HANDLE_RETRAIN_END(condition, counter) \ -if (condition) { \ - counter ++; \ -} else { \ - break; \ -} - -/*---------------------------------------------------------------------------- - * TYPEDEFS, STRUCTURES, ENUMS - * - *---------------------------------------------------------------------------- - */ -/*---------------------------------------------------------------------------- - * FUNCTIONS PROTOTYPE - * - *---------------------------------------------------------------------------- - */ - -BOOLEAN -MemErrHandle ( - IN DIE_STRUCT *MCTPtr, - IN UINT8 DCT, - IN UINT16 ChipSelMask, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -#endif /* _MMERRHDL_H_ */ diff --git a/src/vendorcode/amd/agesa/f12/Proc/Mem/mfParallelTraining.h b/src/vendorcode/amd/agesa/f12/Proc/Mem/mfParallelTraining.h deleted file mode 100644 index 32ce395fc1..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/Mem/mfParallelTraining.h +++ /dev/null @@ -1,113 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * mfParallelTraining.h - * - * Header file for the parallel training feature - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: (Mem) - * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $ - * - **/ -/***************************************************************************** - * - * Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * *************************************************************************** - * - */ - - -#ifndef _MFPARALLELTRAINING_H_ -#define _MFPARALLELTRAINING_H_ - -/*---------------------------------------------------------------------------- - * Mixed (DEFINITIONS AND MACROS / TYPEDEFS, STRUCTURES, ENUMS) - * - *---------------------------------------------------------------------------- - */ - -/*----------------------------------------------------------------------------- - * DEFINITIONS AND MACROS - * - *----------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------- - * TYPEDEFS, STRUCTURES, ENUMS - * - *---------------------------------------------------------------------------- - */ - -typedef BOOLEAN (*REMOTE_NBBLOCK_CONSTRUCTOR) ( - IN OUT MEM_NB_BLOCK *NBPtr, - IN DIE_STRUCT *MCTPtr, - IN MEM_FEAT_BLOCK_NB *FeatPtr -); - -///< This structure defines the environment on the AP for parallel training -typedef struct _REMOTE_TRAINING_ENV { - IN OUT AMD_CONFIG_PARAMS StdHeader; ///< Config pointer of BSP - IN OUT AGESA_STATUS (*GetPlatformCfg[MAX_PLATFORM_TYPES]) (struct _MEM_DATA_STRUCT *MemData, UINT8 SocketID, CH_DEF_STRUCT *CurrentChannel); ///< look-up platform info - IN OUT BOOLEAN (*ErrorHandling)(struct _DIE_STRUCT *MCTPtr, UINT8 DCT, UINT16 ChipSelMask, AMD_CONFIG_PARAMS *StdHeader); ///< Error Handling - IN REMOTE_NBBLOCK_CONSTRUCTOR NBBlockCtor; ///< NB Block constructor - IN MEM_FEAT_BLOCK_NB *FeatPtr; ///< Feature block pointer - IN UINT8 *TableBasedAlterations; ///< Point to an array of data bytes describing desired modifications to register settings - IN PSO_TABLE *PlatformMemoryConfiguration; ///< Point to platform config table - IN UINT32 HoleBase; ///< Used for Memtyping - IN UINT32 UmaSize; ///< Used for Memtyping - IN UINT16 BottomIo; ///< Used for Memtyping - IN UINT32 SysLimit; ///< Used for Memtyping - IN UINT8 BspSocket; ///< Socket number of BSP - IN UINT8 BspCore; ///< Core number of BSP - IN DIE_STRUCT DieStruct; ///< Remote copy of Die Struct -} REMOTE_TRAINING_ENV; - -///< This structure defines Die information -typedef struct _DIE_INFO { - IN OUT UINT8 Socket; ///< Socket number - IN OUT UINT8 Core; ///< Core number - IN OUT BOOLEAN Training; ///< Training Flag, 1 = Training has been started on this core -} DIE_INFO; - - -/*---------------------------------------------------------------------------- - * FUNCTIONS PROTOTYPE - * - *---------------------------------------------------------------------------- - */ - -BOOLEAN -MemFParallelTraining ( - IN OUT REMOTE_TRAINING_ENV *EnvPtr, - IN OUT AMD_CONFIG_PARAMS *StdHeader - ); - -#endif /* _MFPARALLELTRAINING_H_ */ - - diff --git a/src/vendorcode/amd/agesa/f12/Proc/Mem/mfStandardTraining.h b/src/vendorcode/amd/agesa/f12/Proc/Mem/mfStandardTraining.h deleted file mode 100644 index 36edf96e27..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/Mem/mfStandardTraining.h +++ /dev/null @@ -1,81 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * mfStandardTraining.h - * - * Feature implementation of standard function which performs memory training - * from the BSP only - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: (Mem) - * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $ - * - **/ -/***************************************************************************** - * - * Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * *************************************************************************** - * - */ - - -#ifndef _MFSTANDARDTRAINING_H_ -#define _MFSTANDARDTRAINING_H_ - -/*---------------------------------------------------------------------------- - * Mixed (DEFINITIONS AND MACROS / TYPEDEFS, STRUCTURES, ENUMS) - * - *---------------------------------------------------------------------------- - */ - -/*----------------------------------------------------------------------------- - * DEFINITIONS AND MACROS - * - *----------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------- - * TYPEDEFS, STRUCTURES, ENUMS - * - *---------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------- - * FUNCTIONS PROTOTYPE - * - *---------------------------------------------------------------------------- - */ - -BOOLEAN -MemFStandardTraining ( - IN OUT MEM_NB_BLOCK *NBPtr - ); - -#endif /* _MFSTANDARDTRAINING_H_ */ - - diff --git a/src/vendorcode/amd/agesa/f12/Proc/Mem/mfmemclr.h b/src/vendorcode/amd/agesa/f12/Proc/Mem/mfmemclr.h deleted file mode 100644 index 6c134c30e2..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/Mem/mfmemclr.h +++ /dev/null @@ -1,83 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * mfmemclr.h - * - * Feature Functions For Memory Clear Operation - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: (Mem) - * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $ - * - **/ -/***************************************************************************** - * - * Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * *************************************************************************** - * - */ - -#ifndef _MFMEMCLR_H_ -#define _MFMEMCLR_H_ - -/*---------------------------------------------------------------------------- - * Mixed (DEFINITIONS AND MACROS / TYPEDEFS, STRUCTURES, ENUMS) - * - *---------------------------------------------------------------------------- - */ - -/*----------------------------------------------------------------------------- - * DEFINITIONS AND MACROS - * - *----------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------- - * TYPEDEFS, STRUCTURES, ENUMS - * - *---------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------- - * FUNCTIONS PROTOTYPE - * - *---------------------------------------------------------------------------- - */ -BOOLEAN -MemFMctMemClr_Init ( - IN OUT MEM_NB_BLOCK *NBPtr - ); - -BOOLEAN -MemFMctMemClr_Sync ( - IN OUT MEM_NB_BLOCK *NBPtr - ); - -#endif /* _MFMEMCLR_H_ */ - - diff --git a/src/vendorcode/amd/agesa/f12/Proc/Mem/mfs3.h b/src/vendorcode/amd/agesa/f12/Proc/Mem/mfs3.h deleted file mode 100644 index 1ea8aefeec..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/Mem/mfs3.h +++ /dev/null @@ -1,355 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * mfS3.h - * - * S3 resume memory related functions. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: (Mem/Feat/S3) - * @e \$Revision: 51670 $ @e \$Date: 2011-04-27 03:26:02 +0800 (Wed, 27 Apr 2011) $ - * - **/ -/***************************************************************************** -* -* Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* *************************************************************************** -* -*/ - -#ifndef _MFS3_H_ -#define _MFS3_H_ - -/*---------------------------------------------------------------------------- - * Mixed (DEFINITIONS AND MACROS / TYPEDEFS, STRUCTURES, ENUMS) - * - *---------------------------------------------------------------------------- - */ - -/*----------------------------------------------------------------------------- - * DEFINITIONS AND MACROS - * - *----------------------------------------------------------------------------- - */ -#define PRESELFREF 0 -#define POSTSELFREF 1 -#define DCT0 0 -#define DCT1 1 -#define DCT0_MASK 0x1 -#define DCT1_MASK 0x2 -#define DCT0_NBPSTATE_SUPPORT_MASK 0x4 -#define DCT1_NBPSTATE_SUPPORT_MASK 0x8 -#define DCT0_DDR3_MASK 0x10 -#define DCT1_DDR3_MASK 0x20 -#define NODE_WITHOUT_DIMM_MASK 0x80 -#define DCT0_ANY_DIMM_MASK 0x55 -#define DCT1_ANY_DIMM_MASK 0xAA -#define ANY_DIMM_MASK 0xFF - -#define DCT_PHY_FLAG 0 -#define DCT_EXTRA_FLAG 1 -#define SET_S3_SPECIAL_OFFSET(AccessType, Dct, Offset) ((AccessType << 11) | (Dct << 10) | Offset) - -/*---------------------------------------------------------------------------- - * TYPEDEFS, STRUCTURES, ENUMS - * - *---------------------------------------------------------------------------- - */ -/// struct for all the descriptor for pre exit self refresh and post exit self refresh -typedef struct _DESCRIPTOR_GROUP { - PCI_DEVICE_DESCRIPTOR PCIDevice[2]; ///< PCI device descriptor - CONDITIONAL_PCI_DEVICE_DESCRIPTOR CPCIDevice[2]; ///< Conditional PCI device descriptor - MSR_DEVICE_DESCRIPTOR MSRDevice[2]; ///< MSR device descriptor - CONDITIONAL_MSR_DEVICE_DESCRIPTOR CMSRDevice[2]; ///< Conditional MSR device descriptor -} DESCRIPTOR_GROUP; - -/// Northbridge block to be used in S3 resume and save. -typedef struct _S3_MEM_NB_BLOCK { - UINT8 MemS3SpecialCaseHeapSize; ///< Heap size for the special case register heap. - struct _MEM_NB_BLOCK *NBPtr; ///< Pointer to the north bridge block. - VOID (*MemS3ExitSelfRefReg) (MEM_NB_BLOCK *NBPtr, AMD_CONFIG_PARAMS *StdHeaderPtr); ///< S3 Exit self refresh register - VOID (*MemS3GetConPCIMask) (MEM_NB_BLOCK *NBPtr, DESCRIPTOR_GROUP *DescriptPtr); ///< Get conditional mask for PCI register setting - VOID (*MemS3GetConMSRMask) (MEM_NB_BLOCK *NBPtr, DESCRIPTOR_GROUP *DescriptPtr); ///< Get conditional mask for MSR register setting - UINT16 (*MemS3GetRegLstPtr) (MEM_NB_BLOCK *NBPtr, DESCRIPTOR_GROUP *DescriptPtr); ///< Get register list pointer for both PCI and MSR register - BOOLEAN (*MemS3Resume) (struct _S3_MEM_NB_BLOCK *S3NBPtr, UINT8 NodeID);///< Exit Self Refresh - VOID (*MemS3RestoreScrub) (MEM_NB_BLOCK *NBPtr, UINT8 NodeID);///< Restore scrubber base - AGESA_STATUS (*MemS3GetDeviceRegLst) (UINT32 ReigsterLstID, VOID **RegisterHeader); ///< Get register list for a device -} S3_MEM_NB_BLOCK; - -/// Header for heap space to store the special case register. -typedef struct _S3_SPECIAL_CASE_HEAP_HEADER { - UINT8 Node; ///< Node ID for the header - UINT8 Offset; ///< Offset for the target node -} S3_SPECIAL_CASE_HEAP_HEADER; -/*---------------------------------------------------------------------------- - * FUNCTIONS PROTOTYPE - * - *---------------------------------------------------------------------------- - */ -AGESA_STATUS -AmdMemS3Resume ( - IN AMD_CONFIG_PARAMS *StdHeader - ); - -AGESA_STATUS -MemS3ResumeInitNB ( - IN AMD_CONFIG_PARAMS *StdHeader - ); - -AGESA_STATUS -MemS3Deallocate ( - IN AMD_CONFIG_PARAMS *StdHeader - ); - -AGESA_STATUS -MemFS3GetPciDeviceRegisterList ( - IN PCI_DEVICE_DESCRIPTOR *Device, - OUT PCI_REGISTER_BLOCK_HEADER **RegisterHdr, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -AGESA_STATUS -MemFS3GetCPciDeviceRegisterList ( - IN CONDITIONAL_PCI_DEVICE_DESCRIPTOR *Device, - OUT CPCI_REGISTER_BLOCK_HEADER **RegisterHdr, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -AGESA_STATUS -MemFS3GetMsrDeviceRegisterList ( - IN MSR_DEVICE_DESCRIPTOR *Device, - OUT MSR_REGISTER_BLOCK_HEADER **RegisterHdr, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -AGESA_STATUS -MemFS3GetCMsrDeviceRegisterList ( - IN CONDITIONAL_MSR_DEVICE_DESCRIPTOR *Device, - OUT CMSR_REGISTER_BLOCK_HEADER **RegisterHdr, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -AGESA_STATUS -MemFS3GetDeviceList ( - IN OUT DEVICE_BLOCK_HEADER **DeviceBlockHdrPtr, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -VOID -MemFS3Wait10ns ( - IN UINT32 Count, - IN OUT MEM_DATA_STRUCT *MemPtr - ); - -BOOLEAN -MemNS3ResumeNb ( - IN OUT S3_MEM_NB_BLOCK *S3NBPtr, - IN UINT8 NodeID - ); - -BOOLEAN -MemNS3ResumeClientNb ( - IN OUT S3_MEM_NB_BLOCK *S3NBPtr, - IN UINT8 NodeID - ); - -BOOLEAN -MemNS3ResumeUNb ( - IN OUT S3_MEM_NB_BLOCK *S3NBPtr, - IN UINT8 NodeID - ); - -VOID -MemNS3GetConPCIMaskNb ( - IN OUT MEM_NB_BLOCK *NBPtr, - IN OUT DESCRIPTOR_GROUP *DescriptPtr - ); - -VOID -MemNS3GetConPCIMaskUnb ( - IN OUT MEM_NB_BLOCK *NBPtr, - IN OUT DESCRIPTOR_GROUP *DescriptPtr - ); - -VOID -MemNS3GetCSRNb ( - IN ACCESS_WIDTH AccessWidth, - IN PCI_ADDR Address, - IN VOID *Value, - IN OUT VOID *ConfigPtr - ); - -VOID -MemNS3SetCSRNb ( - IN ACCESS_WIDTH AccessWidth, - IN PCI_ADDR Address, - IN OUT VOID *Value, - IN OUT VOID *ConfigPtr - ); - -VOID -MemNS3GetBitFieldNb ( - IN ACCESS_WIDTH AccessWidth, - IN PCI_ADDR Address, - IN OUT VOID *Value, - IN OUT VOID *ConfigPtr - ); - -VOID -MemNS3SetBitFieldNb ( - IN ACCESS_WIDTH AccessWidth, - IN PCI_ADDR Address, - IN OUT VOID *Value, - IN OUT VOID *ConfigPtr - ); - -VOID -MemNS3RestoreScrubNb ( - IN OUT MEM_NB_BLOCK *NBPtr, - IN UINT8 Node - ); - -AGESA_STATUS -MemS3InitNB ( - IN OUT S3_MEM_NB_BLOCK **S3NBPtr, - IN OUT MEM_DATA_STRUCT **MemPtr, - IN OUT MEM_MAIN_DATA_BLOCK *mmData, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -VOID -MemNS3DisNbPsDbgNb ( - IN ACCESS_WIDTH AccessWidth, - IN PCI_ADDR Address, - IN OUT VOID *Value, - IN OUT VOID *ConfigPtr - ); - -VOID -MemNS3EnNbPsDbg1Nb ( - IN ACCESS_WIDTH AccessWidth, - IN PCI_ADDR Address, - IN OUT VOID *Value, - IN OUT VOID *ConfigPtr - ); - -VOID -MemNS3SetDynModeChangeNb ( - IN ACCESS_WIDTH AccessWidth, - IN PCI_ADDR Address, - IN OUT VOID *Value, - IN OUT VOID *ConfigPtr - ); - -VOID -MemNS3DisableChannelNb ( - IN ACCESS_WIDTH AccessWidth, - IN PCI_ADDR Address, - IN OUT VOID *Value, - IN OUT VOID *ConfigPtr - ); - -VOID -MemNS3SetDisAutoCompUnb ( - IN ACCESS_WIDTH AccessWidth, - IN PCI_ADDR Address, - IN OUT VOID *Value, - IN OUT VOID *ConfigPtr - ); - -VOID -MemNS3SetPreDriverCalUnb ( - IN ACCESS_WIDTH AccessWidth, - IN PCI_ADDR Address, - IN OUT VOID *Value, - IN OUT VOID *ConfigPtr - ); - -BOOLEAN -MemNS3DctCfgSelectUnb ( - IN OUT MEM_NB_BLOCK *NBPtr, - IN VOID *Dct - ); - -VOID -MemNS3GetNBPStateDepRegUnb ( - IN ACCESS_WIDTH AccessWidth, - IN PCI_ADDR Address, - IN OUT VOID *Value, - IN OUT VOID *ConfigPtr - ); - -VOID -MemNS3SetNBPStateDepRegUnb ( - IN ACCESS_WIDTH AccessWidth, - IN PCI_ADDR Address, - IN OUT VOID *Value, - IN OUT VOID *ConfigPtr - ); - -VOID -MemNS3SaveNBRegiserUnb ( - IN ACCESS_WIDTH AccessWidth, - IN PCI_ADDR Address, - IN OUT VOID *Value, - IN OUT VOID *ConfigPtr - ); - -VOID -MemNS3RestoreNBRegiserUnb ( - IN ACCESS_WIDTH AccessWidth, - IN PCI_ADDR Address, - IN OUT VOID *Value, - IN OUT VOID *ConfigPtr - ); - -VOID -MemNS3SetMemClkFreqValUnb ( - IN ACCESS_WIDTH AccessWidth, - IN PCI_ADDR Address, - IN OUT VOID *Value, - IN OUT VOID *ConfigPtr - ); - -VOID -MemNS3ChangeMemPStateContextNb ( - IN ACCESS_WIDTH AccessWidth, - IN PCI_ADDR Address, - IN OUT VOID *Value, - IN OUT VOID *ConfigPtr - ); - -VOID -MemNS3SetPhyClkDllFineClientNb ( - IN ACCESS_WIDTH AccessWidth, - IN PCI_ADDR Address, - IN OUT VOID *Value, - IN OUT VOID *ConfigPtr - ); - -#endif //_MFS3_H_ diff --git a/src/vendorcode/amd/agesa/f12/Proc/Mem/mftds.h b/src/vendorcode/amd/agesa/f12/Proc/Mem/mftds.h deleted file mode 100644 index 089ba5f1c1..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/Mem/mftds.h +++ /dev/null @@ -1,80 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * mftds.h - * - * Memory Controller - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: (Mem) - * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $ - * - **/ -/***************************************************************************** - * - * Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * *************************************************************************** - * - */ - - -#ifndef _MFTDS_H_ -#define _MFTDS_H_ - -/*---------------------------------------------------------------------------- - * Mixed (DEFINITIONS AND MACROS / TYPEDEFS, STRUCTURES, ENUMS) - * - *---------------------------------------------------------------------------- - */ - -/*----------------------------------------------------------------------------- - * DEFINITIONS AND MACROS - * - *----------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------- - * TYPEDEFS, STRUCTURES, ENUMS - * - *---------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------- - * FUNCTIONS PROTOTYPE - * - *---------------------------------------------------------------------------- - */ - -VOID -MemFInitTableDrive ( - IN OUT MEM_NB_BLOCK *NBPtr, - IN UINT8 time - ); -#endif /* _MFTDS_H_ */ - - diff --git a/src/vendorcode/amd/agesa/f12/Proc/Mem/mm.h b/src/vendorcode/amd/agesa/f12/Proc/Mem/mm.h deleted file mode 100644 index 93476c4fc2..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/Mem/mm.h +++ /dev/null @@ -1,1129 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * mm.h - * - * Common main functions - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: (Mem) - * @e \$Revision: 49794 $ @e \$Date: 2011-03-29 13:59:05 +0800 (Tue, 29 Mar 2011) $ - * - **/ -/***************************************************************************** - * - * Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * *************************************************************************** - * - */ - -#ifndef _MM_H_ -#define _MM_H_ - -/*---------------------------------------------------------------------------- - * Mixed (DEFINITIONS AND MACROS / TYPEDEFS, STRUCTURES, ENUMS) - * - *---------------------------------------------------------------------------- - */ - -/*----------------------------------------------------------------------------- - * DEFINITIONS AND MACROS - * - *----------------------------------------------------------------------------- - */ - -#define ALLOC_SOCKET_STRUCT_HANDLE 0 -#define ALLOC_DIE_STRUCT_HANDLE 1 -#define ALLOC_DCT_STRUCT_HANDLE 2 -#define ALLOC_CHL_STRUCT_HANDLE 3 -#define ALLOC_PLATFORM_PTR_HANDLE 4 -#define ALLOC_FORM_FACTOR_HANDLE 5 -#define ALLOC_TRN_DATA_HANDLE 6 -#define ALLOC_DIMM_DATA_HANDLE 7 -#define ALLOC_PAR_TRN_HANDLE 8 -#define ALLOC_NB_REG_TABLE 9 - -#define GENERATE_MEM_HANDLE(type, x, y, z) (\ - AMD_MEM_MISC_HANDLES_START + (((type) << 18) + ((x) << 12) + ((y) << 6) + (z)) \ -) - -/// Heap handle for each supported family's NB register table -typedef enum { - NbRegTabDR, ///< Heap handle for DR NB register table - NbRegTabDA, ///< Heap handle for DA NB register table - NbRegTabC32, ///< Heap handle for C32 NB register table - NbRegTabHY, ///< Heap handle for HY NB register table - NbRegTabKR, ///< Heap handle for KR NB register table - NbRegTabLN, ///< Heap handle for LN NB register table - NbRegTabON, ///< Heap handle for ON NB register table - NbRegTabOR, ///< Heap handle for OR NB register table - NbRegTabTN, ///< Heap handle for TN NB register table - NumberOfNbRegTables ///< Number of families that have NB register tables -} NB_REG_TAB_HANDLE; - - -#define VOLT1_5_ENCODED_VAL 0 -#define VOLT1_35_ENCODED_VAL 1 -#define VOLT1_25_ENCODED_VAL 2 -#define CONVERT_VDDIO_TO_ENCODED(VddIo) (\ - (VddIo == VOLT1_5) ? VOLT1_5_ENCODED_VAL : ((VddIo == VOLT1_35) ? VOLT1_35_ENCODED_VAL : ((VddIo == VOLT1_25) ? VOLT1_25_ENCODED_VAL : 0xFF)) \ -) -#define CONVERT_ENCODED_TO_VDDIO(EncodedVal) (\ - (EncodedVal == VOLT1_5_ENCODED_VAL) ? VOLT1_5 : ((EncodedVal == VOLT1_35_ENCODED_VAL) ? VOLT1_35 : ((EncodedVal == VOLT1_25_ENCODED_VAL) ? VOLT1_25 : VOLT_UNSUPPORTED)) \ -) -/*---------------------------------------------------------------------------- - * TYPEDEFS, STRUCTURES, ENUMS - * - *---------------------------------------------------------------------------- - */ - -/// Bit field names used in memory initialization -typedef enum { - BFDevVendorIDReg, ///< Bit field DevVendorIDReg - BFNodeID, ///< Bit field NodeID - BFNodeCnt, ///< Bit field NodeCnt - - BFDramBaseReg0, ///< Bit field DramBaseReg0 - BFDramBaseReg1, ///< Bit field DramBaseReg1 - BFDramBaseReg2, ///< Bit field DramBaseReg2 - BFDramBaseReg3, ///< Bit field DramBaseReg3 - BFDramBaseReg4, ///< Bit field DramBaseReg4 - BFDramBaseReg5, ///< Bit field DramBaseReg5 - BFDramBaseReg6, ///< Bit field DramBaseReg6 - BFDramBaseReg7, ///< Bit field DramBaseReg7 - - BFDramLimitReg0, ///< Bit field DramLimitReg0 - BFDramLimitReg1, ///< Bit field DramLimitReg1 - BFDramLimitReg2, ///< Bit field DramLimitReg2 - BFDramLimitReg3, ///< Bit field DramLimitReg3 - BFDramLimitReg4, ///< Bit field DramLimitReg4 - BFDramLimitReg5, ///< Bit field DramLimitReg5 - BFDramLimitReg6, ///< Bit field DramLimitReg6 - BFDramLimitReg7, ///< Bit field DramLimitReg7 - - BFDramBaseHiReg0, ///< Bit field DramBaseHiReg0 - BFDramBaseHiReg1, ///< Bit field DramBaseHiReg1 - BFDramBaseHiReg2, ///< Bit field DramBaseHiReg2 - BFDramBaseHiReg3, ///< Bit field DramBaseHiReg3 - BFDramBaseHiReg4, ///< Bit field DramBaseHiReg4 - BFDramBaseHiReg5, ///< Bit field DramBaseHiReg5 - BFDramBaseHiReg6, ///< Bit field DramBaseHiReg6 - BFDramBaseHiReg7, ///< Bit field DramBaseHiReg7 - - BFDramLimitHiReg0, ///< Bit field DramLimitHiReg0 - BFDramLimitHiReg1, ///< Bit field DramLimitHiReg1 - BFDramLimitHiReg2, ///< Bit field DramLimitHiReg2 - BFDramLimitHiReg3, ///< Bit field DramLimitHiReg3 - BFDramLimitHiReg4, ///< Bit field DramLimitHiReg4 - BFDramLimitHiReg5, ///< Bit field DramLimitHiReg5 - BFDramLimitHiReg6, ///< Bit field DramLimitHiReg6 - BFDramLimitHiReg7, ///< Bit field DramLimitHiReg7 - - BFDramHoleAddrReg, ///< Bit field DramHoleAddrReg - - BFCSBaseAddr0Reg, ///< Bit field CSBaseAddr0Reg - BFCSBaseAddr1Reg, ///< Bit field CSBaseAddr1Reg - BFCSBaseAddr2Reg, ///< Bit field CSBaseAddr2Reg - BFCSBaseAddr3Reg, ///< Bit field CSBaseAddr3Reg - BFCSBaseAddr4Reg, ///< Bit field CSBaseAddr4Reg - BFCSBaseAddr5Reg, ///< Bit field CSBaseAddr5Reg - BFCSBaseAddr6Reg, ///< Bit field CSBaseAddr6Reg - BFCSBaseAddr7Reg, ///< Bit field CSBaseAddr7Reg - - BFCSMask0Reg, ///< Bit field CSMask0Reg - BFCSMask1Reg, ///< Bit field CSMask1Reg - BFCSMask2Reg, ///< Bit field CSMask2Reg - BFCSMask3Reg, ///< Bit field CSMask3Reg - - BFRankDef0, ///< Bit field RankDef 0 - BFRankDef1, ///< Bit field RankDef 1 - BFRankDef2, ///< Bit field RankDef 2 - BFRankDef3, ///< Bit field RankDef 3 - - BFDramControlReg, ///< Bit field DramControlReg - BFDramInitRegReg, ///< Bit field DramInitRegReg - BFDramBankAddrReg, ///< Bit field DramBankAddrReg - BFDramMRSReg, ///< Bit field DramMRSReg - BFDramTimingLoReg, ///< Bit field DramTimingLoReg - BFDramTimingHiReg, ///< Bit field DramTimingHiReg - BFDramConfigLoReg, ///< Bit field DramConfigLoReg - BFDramConfigHiReg, ///< Bit field DramConfigHiReg - BFDctAddlOffsetReg, ///< Bit field DctAddlOffsetReg - BFDctAddlDataReg, ///< Bit field DctAddlDataReg - BFDctAccessDone, ///< Bit field DctAccessDone - BFDctAccessError, ///< Bit field DctAccessError - BFDctExtraOffsetReg, ///< Bit field DctExtraOffsetReg - BFDctExtraDataReg, ///< Bit field DctExtraDataReg - BFDctExtraAccessDone, ///< Bit field DctExtraAccessDone - BFDramConfigMiscReg, ///< Bit field DramConfigMiscReg - BFDramCtrlMiscReg2, ///< Bit field DramCtrlMiscReg2 - BFMctCfgHiReg, ///< Bit field MctCfgHiReg - BFMctCfgLoReg, ///< Bit field MctCfgLoReg - BFExtMctCfgLoReg, ///< Bit field ExtMctCfgLoReg - BFExtMctCfgHiReg, ///< Bit field ExtMctCfgHiReg - - BFDramHoleBase, ///< Bit field DramHoleBase - BFDramHoleOffset, ///< Bit field DramHoleOffset - BFDramMemHoistValid, ///< Bit field DramMemHoistValid - BFDramHtHoleValid, ///< Bit field BFDramHtHoleValid - Orochi - BFDramHoleValid, ///< Bit field DramHoleValid - BFDramBaseAddr, ///< Bit field DramBaseAddr - BFDramIntlvSel, ///< Bit field DramIntlvSel - BFDramLimitAddr, ///< Bit field DramLimitAddr - BFDramIntlvEn, ///< Bit field DramIntlvEn - BFMemPsSel, ///< Bit field MemPsSel - BFDctCfgSel, ///< Bit field DctCfgSel - - BFMcaNbCtlReg, ///< Bit field McaNbCtlReg - BFDramEccEn, ///< Bit field DramEccEn - BFSyncOnUcEccEn, ///< Bit field SyncOnUcEccEn - BFEccSymbolSize, ///< Bit field EccSymbolSize - BFMcaNbStatusLoReg, ///< Bit field McaNbStatusLoReg - BFMcaNbStatusHiReg, ///< Bit field McaNbStatusHiReg - BFDramScrub, ///< Bit field DramScrub - BFL2Scrub, ///< Bit field L2Scrub - BFDcacheScrub, ///< Bit field DcacheScrub - BFL3Scrub, ///< Bit field L3Scrub - BFScrubReDirEn, ///< Bit field ScrubReDirEn - BFScrubAddrLoReg, ///< Bit field ScrubAddrLoReg - BFScrubAddrHiReg, ///< Bit field ScrubAddrHiReg - BFC1ClkDivisor, ///< Bit field C1ClkDivisor - BFDisDatMsk, ///< Bit field DisDatMsk - BFNbFid, ///< Bit field NbFid - BFMTC1eEn, ///< Bit field MTC1eEn - BFL3Capable, ///< Bit field L3Capable - BFDisableL3, ///< Bit field DisableL3 - BFEnhMemProtCap, ///< Bit field EnhMemProtCap - BFNbPsForceReq, ///< Bit field NbPsForceReq - BFNbPsCtrlDis, ///< Bit field NbPsCtrlDis - BFNbPsCap, ///< Bit field NbPsCap - - BFNonSPDHi, ///< Bit field NonSPDHi - BFRdPtrInit, ///< Bit field RdPtrInit - BFAltVidC3MemClkTriEn, ///< Bit field AltVidC3MemClkTriEn - BFDqsRcvEnTrain, ///< Bit field DqsRcvEnTrain - BFEarlyArbEn, ///< Bit field EarlyArbEn - BFMaxLatency, ///< Bit field either MaxRdLat or MaxAsyncLat - - BFMrsAddress, ///< Bit field MrsAddress - BFMrsBank, ///< Bit field MrsBank - BFMrsChipSel, ///< Bit field MrsChipSel - BFSendPchgAll, ///< Bit field SendPchgAll - BFSendAutoRefresh, ///< Bit field SendAutoRefresh - BFSendMrsCmd, ///< Bit field SendMrsCmd - BFDeassertMemRstX, ///< Bit field DeassertMemRstX - BFAssertCke, ///< Bit field AssertCke - BFSendZQCmd, ///< Bit field SendZQCmd - BFSendCtrlWord, ///< Bit field SendCtrlWord - BFEnDramInit, ///< Bit field EnDramInit - BFMrsLevel, ///< Bit field MrsLevel - BFMrsQoff, ///< Bit field MrsQoff - BFMrsAddressHi, ///< Bit field MrsAddress [17:13] - - BFBurstCtrl, ///< Bit field BurstCtrl - BFDrvImpCtrl, ///< Bit field DrvImpCtrl - BFDramTerm_DDR3, ///< Bit field DramTerm_DDR3 - BFDramTermDyn, ///< Bit field DramTermDyn - BFQoff, ///< Bit field Qoff - BFASR, ///< Bit field ASR - BFSRT, ///< Bit field SRT - BFTcwl, ///< Bit field Tcwl - BFPchgPDModeSel, ///< Bit field PchgPDModeSel - BFLowPowerDefault, ///< Bit field LowPowerDefault - - BFTwrDDR3, ///< Bit field TwrDDR3 - BFTcl, ///< Bit field Tcl - BFTrcd, ///< Bit field Trcd - BFTrp, ///< Bit field Trp - BFTrtp, ///< Bit field Trtp - BFTras, ///< Bit field Tras - BFTrc, ///< Bit field Trc - BFTwr, ///< Bit field Twr - BFTrrd, ///< Bit field Trrd - BFMemClkDis, ///< Bit field MemClkDis - BFDramTiming0, ///< Bit field BFDramTiming0 - BFDramTiming1, ///< Bit field BFDramTiming1 - BFDramTiming2, ///< Bit field BFDramTiming2 - BFDramTiming3, ///< Bit field BFDramTiming3 - BFDramTiming4, ///< Bit field BFDramTiming4 - BFDramTiming5, ///< Bit field BFDramTiming5 - BFDramTiming6, ///< Bit field BFDramTiming6 - BFDramTiming10, ///< Bit field BFDramTiming10 - BFDramNBP0, ///< Bit field BFDramNBP0 - - BFNonSPD, ///< Bit field NonSPD - BFTrwtWB, ///< Bit field TrwtWB - BFTrwtTO, ///< Bit field TrwtTO - BFTwtr, ///< Bit field Twtr - BFTwrrd, ///< Bit field Twrrd - BFTwrrdHi, ///< Bit field TwrrdHi - BFTwrwr, ///< Bit field Twrwr - BFTwrwrHi, ///< Bit field TwrwrHi - BFTrdrdSD, ///< Bit field TrdrdSD - BFTwrwrSD, ///< Bit field TwrwrSD - BFTwrrdSD, ///< Bit field TwrrdSD - BFTmod, ///< Bit field Tmod - BFTmrd, ///< Bit field Tmrd - BFRdOdtTrnOnDly, ///< Bit field RdOdtTrnOnDly - BFRdOdtOnDuration, ///< Bit field RdOdtOnDuration - BFWrOdtTrnOnDly, ///< Bit field WrOdtTrnOnDly - BFWrOdtOnDuration, ///< Bit field WrOdtOnDuration - BFPrtlChPDDynDly, ///< Bit field PrtlChPDDynDly - - BFAggrPDDelay, ///< Bit field AggrPDDelay - BFPchgPDEnDelay, ///< Bit field PchgPDEnDelay - - BFTrdrd, ///< Bit field Trdrd - BFTrdrdHi, ///< Bit field TrdrdHi - BFTref, ///< Bit field Tref - BFDisAutoRefresh, ///< Bit field DisAutoRefresh - BFTrfc0, ///< Bit field Trfc0 - BFTrfc1, ///< Bit field Trfc1 - BFTrfc2, ///< Bit field Trfc2 - BFTrfc3, ///< Bit field Trfc3 - - BFInitDram, ///< Bit field InitDram - BFExitSelfRef, ///< Bit field ExitSelfRef - BFDramTerm, ///< Bit field DramTerm - BFParEn, ///< Bit field ParEn - BFBurstLength32, ///< Bit field BurstLength32 - BFWidth128, ///< Bit field Width128 - BFX4Dimm, ///< Bit field X4Dimm - BFDimmEccEn, ///< Bit field DimmEccEn - BFUnBuffDimm, ///< Bit field UnBuffDimm - BFEnterSelfRef, ///< Bit field EnterSelfRef - BFDynPageCloseEn, ///< Bit field DynPageCloseEn - BFIdleCycInit, ///< Bit field IdleCycInit - BFFreqChgInProg, ///< Bit field FreqChgInProg - BFForceAutoPchg, ///< Bit field ForceAutoPchg - BFStagRefEn, ///< Bit field StagRefEn - BFPendRefPaybackS3En, ///< Bit field PendRefPaybackS3En - BFEnDispAutoPrecharge, ///< Bit field EnDispAutoPrecharge - BFDisDllShutdownSR, ///< Bit field DisDllShutdownSR - BFDisSscClkGateData, ///< Bit field DisSscClkGateData - BFDisSscClkGateCmdAddr, ///< Bit field DisSscClkGateCmdAddr - BFDisSimulRdWr, ///< Bit field DisSimulRdWr - - BFMemClkFreq, ///< Bit field MemClkFreq - BFMemClkFreqVal, ///< Bit field MemClkFreqVal - BFDdr3Mode, ///< Bit field Ddr3Mode - BFLegacyBiosMode, ///< Bit field LegacyBiosMode - BFZqcsInterval, ///< Bit field ZqcsInterval - BFRDqsEn, ///< Bit field RDqsEn - BFDisDramInterface, ///< Bit field DisDramInterface - BFPowerDownEn, ///< Bit field PowerDownEn - BFPowerDownMode, ///< Bit field PowerDownMode - BFFourRankSoDimm, ///< Bit field FourRankSoDimm - BFDcqArbBypassEn, ///< Bit field DcqArbBypassEn - BFFourRankRDimm, ///< Bit field FourRankRDimm - BFSlowAccessMode, ///< Bit field SlowAccessMode - BFBankSwizzleMode, ///< Bit field BankSwizzleMode - BFDcqBypassMax, ///< Bit field DcqBypassMax - BFFourActWindow, ///< Bit field FourActWindow - BFDphyMemPsSelEn, ///< Bit field BFDphyMemPsSelEn - - BFODTSEn, ///< Bit field ODTSEn - BFCmdThrottleMode, ///< Bit field CmdThrottleMode - BFBwCapEn, ///< Bit field BwCapEn - - BFDdr3FourSocketCh, ///< Bit field Ddr3FourSocketCh - BFSubMemclkRegDly, ///< Bit field SubMemclkRegDly - BFOdtSwizzle, ///< Bit field OdtSwizzle - BFProgOdtEn, ///< Bit field ProgOdtEn - BFCtrlWordCS, ///< Bit field CtrlWordCS - BFRefChCmdMgtDis, ///< Bit field RefChCmdMgtDis - BFFastSelfRefEntryDis, ///< Bit field FastSelfRefEntryDis - BFPrtlChPDEnhEn, ///< Bit field PrtlChPDEnhEn - BFAggrPDEn, ///< Bit field AggrPDEn - BFDataTxFifoWrDly, ///< Bit field DataTxFifoWrDly - BFWrDqDqsEarly, ///< Bit field WrDqDqsEarly - BFCSMux45, ///< Bit field CSMux45 - BFCSMux67, ///< Bit field CSMux67 - BFLrDimmMrsCtrl, ///< Bit field LrDimmMrsCtrl - BFExtendedParityEn, ///< Bit field ExtendedParityEn - BFLrDimmEnhRefEn, ///< Bit field LrDimmEnhRefEn - BFCSTimingMux67, ///< Bit field CSTimingMux67 - - BFIntLvRgnSwapEn, ///< Bit field IntLvRgnSwapEn - BFIntLvRgnBaseAddr, ///< Bit field IntLvRgnBaseAddr - BFIntLvRgnLmtAddr, ///< Bit field IntLvRgnLmtAddr - BFIntLvRgnSize, ///< Bit field IntLvRgnSize - - BFDctSelHiRngEn, ///< Bit field DctSelHiRngEn - BFDctSelHi, ///< Bit field DctSelHi - BFDctSelIntLvEn, ///< Bit field DctSelIntLvEn - BFMemClrInit, ///< Bit field MemClrInit - BFDctGangEn, ///< Bit field DctGangEn - BFDctDatIntLv, ///< Bit field DctDatIntLv - BFDctSelIntLvAddr, ///< Bit field DctSelIntLvAddr - BFDctSelIntLvAddrHi, ///< Bit field DctSelIntLvAddrHi - BFDramEnabled, ///< Bit field DramEnabled - BFMemClrBusy, ///< Bit field MemClrBusy - BFMemCleared, ///< Bit field MemCleared - BFDctSelBaseAddr, ///< Bit field DctSelBaseAddr - BFDctSelBaseOffset, ///< Bit field DctSelBaseOffset - BFDctSelBankSwap, ///< Bit field DctSelBankSwap - - BFAdapPrefMissRatio, ///< Bit field AdapPrefMissRatio - BFAdapPrefPosStep, ///< Bit field AdapPrefPosStep - BFAdapPrefNegStep, ///< Bit field AdapPrefNegStep - BFCohPrefPrbLmt, ///< Bit field CohPrefPrbLmt - - BFFlushWrOnS3StpGnt, ///< Bit field FlushWrOnS3StpGnt - - BFPrefDramTrainDone, ///< Bit field PrefDramTrainDone - BFWrDramTrainMode, ///< Bit field WrDramTrainMode - BFMctPrefReqLimit, ///< Bit field MctPrefReqLimit - BFPrefDramTrainMode, ///< Bit field PrefDramTrainMode - BFDctWrLimit, ///< Bit field DctWrLimit - BFMctWrLimit, ///< Bit field MctWrLimit - BFDramTrainPdbDis, ///< Bit field DramTrainPdbDis - BFTrainLength, ///< Bit field TrainLength - BFRdTrainGo, ///< Bit field RdTrainGo - BFWrTrainGo, ///< Bit field WrTrainGo - BFWrTrainAdrPtrLo, ///< Bit field WrTrainAdrPtrLo - BFWrTrainAdrPtrHi, ///< Bit field WrTrainAdrPtrHi - BFWrTrainBufAddr, ///< Bit field WrTrainBufAddr - BFWrTrainBufDat, ///< Bit field WrTrainBufDat - BFFlushWr, ///< Bit field FlushWr - BFFlushWrOnStpGnt, ///< Bit field FlushWrOnStpGnt - BFPrefCpuDis, ///< Bit field PrefCpuDis - BFPrefIoDis, ///< Bit field PrefIoDis - BFTrainCmpSts, ///< Bit field TrainCmpSts - BFTrainCmpSts2, ///< Bit field TrainCmpSts2 - BFTraceModeEn, ///< Bit field TraceModeEn - - BFAddrCmdDrvStren, ///< Bit field AddrCmdDrvStren - BFDataDrvStren, ///< Bit field DataDrvStren - BFCkeDrvStren, ///< Bit field CkeDrvStren - BFCsOdtDrvStren, ///< Bit field CsOdtDrvStren - BFClkDrvStren, ///< Bit field ClkDrvStren - BFDqsDrvStren, ///< Bit field DqsDrvStren - BFProcOdt, ///< Bit field ProcOdt - BFODCControl, ///< Bit field ODCControl - BFAddrTmgControl, ///< Bit field AddrTmgControl - BFAddrCmdFineDelay, ///< Bit field AddrCmdFineDelay - - BFWrtLvTrEn, ///< Bit field WrtLvTrEn - BFWrtLvTrMode, ///< Bit field WrtLvTrMode - BFPhyFenceTrEn, ///< Bit field PhyFenceTrEn - BFTrDimmSel, ///< Bit field TrDimmSel - BFTrNibbleSel, ///< Bit field TrNibbleSel - BFFenceTrSel, ///< Bit field FenceTrSel - BFWrLvOdt, ///< Bit field WrLvOdt - BFWrLvOdtEn, ///< Bit field WrLvOdtEn - BFDqsRcvTrEn, ///< Bit field DqsRcvTrEn - BFDisAutoComp, ///< Bit field DisAutoComp - BFWrtLvErr, ///< Bit field WrtLvErr - BFODTAssertionCtl, ///< Bit field ODTAssertionCtl - BFNibbleTrainModeEn, ///< Bit field NibbleTrainModeEn - BFRankTrainModeEn, ///< Bit field RankTrainModeEn - BFPllMult, ///< Bit field PllMult - BFPllDiv, ///< Bit field PllDiv - BFDramPhyCtlReg, ///< Bit field Dram Phy Control Register - - BFDramPhyStatusReg, ///< Bit field DramPhyStatusReg - - BFD3Cmp2PCal, ///< Bit field D3Cmp2PCal - BFD3Cmp2NCal, ///< Bit field D3Cmp2NCal - BFD3Cmp1PCal, ///< Bit field D3Cmp1PCal - BFD3Cmp1NCal, ///< Bit field D3Cmp1NCal - BFD3Cmp0PCal, ///< Bit field D3Cmp0PCal - BFD3Cmp0NCal, ///< Bit field D3Cmp0NCal - - BFPhyFence, ///< Bit field PhyFence - BFODTTri, ///< Bit field ODTTri - BFCKETri, ///< Bit field CKETri - BFChipSelTri, ///< Bit field ChipSelTri - BFPhyRODTCSLow, ///< Bit field PhyRODTCSLow - BFPhyRODTCSHigh, ///< Bit field PhyRODTCSHigh - BFPhyWODTCSLow, ///< Bit field PhyWODTCSLow - BFPhyWODTCSHigh, ///< Bit field PhyWODTCSHigh - BFUSPLLCtlAll, ///< Bit field USPLLCtlAll - BFDSPLLCtlAll, ///< Bit field DSPLLCtlAll - BFUSNibbleAlignEn, ///< Bit field USNibbleAlignEn - BFChnLinitClkEn, ///< Bit field ChnLinitClkEn - - BFTSLinkSelect, ///< Bit field TSLinkSelect - BFTS2BitLockEn, ///< Bit field TS2BitLockEn - BFTS2En, ///< Bit field TS2En - BFTS1En, ///< Bit field TS1En - BFTS0LinkStarEn, ///< Bit field TS0LinkStarEn - BFTS0En, ///< Bit field TS0En - - BFLinkTrainData, ///< Bit field LinkTrainData - - BFRstRxFifoPtrs, ///< Bit field RstRxFifoPtrs - BFRxFifoPtrInit, ///< Bit field RxFifoPtrInit - BFRstTxFifoPtrs, ///< Bit field RstTxFifoPtrs - BFTxFifoPtrInit, ///< Bit field TxFifoPtrInit - - BFLpbkCount, ///< Bit field LpbkCount - BFLpbkMap, ///< Bit field LpbkMap - BFSendLpbkMaintCmd, ///< Bit field SendLpbkMaintCmd - BFLpbkData, ///< Bit field LpbkData - - BFMbRdPtrEn, ///< Bit field MbRdPtrEn - BFLnkLpBkLat, ///< Bit field LnkLpBkLat - BFLpbkRndTripLatDone, ///< Bit field LpbkRndTripLatDone - BFLnkLatTrainEn, ///< Bit field LnkLatTrainEn - - BFDsPhyReset, ///< Bit field DsPhyReset - BFLinkReset, ///< Bit field LinkReset - - BFPllLockTime, ///< Bit field PllLockTime - BFPllRegWaitTime, ///< Bit field PllRegWaitTime - BFNclkFreqDone, ///< Bit field NclkFreqDone - BFNbPs0NclkDiv, ///< Bit field NbPs0NclkDiv - BFNbPs1NclkDiv, ///< Bit field NbPs1NclkDiv - BFNbPsCsrAccSel, ///< Bit field NbPsCsrAccSel - BFNbPsDbgEn, ///< Bit field NbPsDbgEn - BFNclkRampWithDllRelock, ///< Bit field NclkRampWithDllRelock - - BFOnLineSpareControl, ///< Bit field OnLineSpareControl - BFDdrMaxRate, ///< Bit field DdrMaxRate - - BFNbPstateDis, ///< Bit field NbPstateDis - BFNbPsSel, ///< Bit field NbPsSel - BFNbPstateCtlReg, ///< Bit field NB Pstate Control register - BFSwNbPstateLoDis, ///< Bit field SwNbPstateLoDis - BFNbPstateLo, ///< Bit field NbPstateLo - BFNbPstateHi, ///< Bit field NbPstateHi - BFNbPstateMaxVal, ///< Bit field NbPstateMaxVal - BFCurNbPstate, ///< Bit field NbCurNbPstate - - BFC6Base, ///< Bit field C6Base - BFC6DramLock, ///< Bit field C6DramLock - BFCC6SaveEn, ///< Bit field CC6SaveEn - BFCoreStateSaveDestNode, ///< Bit field CoreStateSaveDestNode - - BFRxPtrInitReq, ///< Bit field RxPtrInitReq - BFAddrCmdTriEn, ///< Bit field AddrCmdTriEn - BFForceCasToSlot0, ///< Bit field ForceCasToSlot0 - BFDisCutThroughMode, ///< Bit field DisCutThroughMode - BFDbeSkidBufDis, ///< Bit field DbeSkidBufDis - BFDbeGskMemClkAlignMode, ///< Bit field DbeGskMemClkAlignMode - BFEnCpuSerRdBehindNpIoWr, ///< Bit field EnCpuSerRdBehindNpIoWr - BFDRAMPhyDLLControl, ///< Bit field DRAMPhyDLLControl - BFRxDLLWakeupTime, ///< Bit field RxDllWakeupTime - BFRxCPUpdPeriod, ///< Bit field RxCPUpdPeriod - BFRxMaxDurDllNoLock, ///< Bit field RxMaxDurDllNoLock - BFTxDLLWakeupTime, ///< Bit field TxDllWakeupTime - BFTxCPUpdPeriod, ///< Bit field TxCPUpdPeriod - BFTxMaxDurDllNoLock, ///< Bit field TxMaxDurDllNoLock - BFEnRxPadStandby, ///< Bit field EnRxPadStandby - BFMaxSkipErrTrain, ///< Bit field MaxSkipErrTrain - BFSlotSel, ///< Bit field SlotSel - BFSlot1ExtraClkEn, ///< Bit field Slot1ExtraClkEn - - BFMemTempHot, ///< Bit field MemTempHot - BFDoubleTrefRateEn, ///< Bit field DoubleTrefRateEn - - BFAcpiPwrStsCtrlHi, ///< Bit field BFAcpiPwrStsCtrlHi - BFDramSrHysEn, ///< Bit field BFDramSrHysEn - BFDramSrHys, ///< Bit field BFDramSrHys - BFMemTriStateEn, ///< Bit field BFMemTriStateEn - BFDramSrEn, ///< Bit field BFDramSrEn - - BFDeassertCke, ///< Bit field BFDeassertCke - BFFourRankRDimm0, ///< Bit field BFFourRankRDimm0 - BFFourRankRDimm1, ///< Bit field BFFourRankRDimm1 - BFTwrwrSdSc, ///< Bit field BFTwrwrSdSc - BFTwrwrSdDc, ///< Bit field BFTwrwrSdDc - BFTwrwrDd, ///< Bit field BFTwrwrDd - BFTrdrdSdSc, ///< Bit field BFTrdrdSdSc - BFTrdrdSdDc, ///< Bit field BFTrdrdSdDc - BFTrdrdDd, ///< Bit field BFTrdrdDd - BFTstag0, ///< Bit field BFTstag0 - BFTstag1, ///< Bit field BFTstag1 - BFTstag2, ///< Bit field BFTstag2 - BFTstag3, ///< Bit field BFTstag3 - - BFCmdSendInProg, ///< Bit field BFCmdSendInProg - BFSendCmd, ///< Bit field BFSendCmd - BFTestStatus, ///< Bit field BFTestStatus - BFCmdTgt, ///< Bit field BFCmdTgt - BFCmdType, ///< Bit field BFCmdType - BFStopOnErr, ///< Bit field BFStopOnErr - BFResetAllErr, ///< Bit field BFResetAllErr - BFCmdTestEnable, ///< Bit field BFCmdTestEnable - BFTgtChipSelectA, ///< Bit field BFTgtChipSelectA - BFTgtBankA, ///< Bit field BFTgtBankA - BFTgtAddressA, ///< Bit field BFTgtAddressA - BFTgtChipSelectB, ///< Bit field BFTgtChipSelectB - BFTgtBankB, ///< Bit field BFTgtBankB - BFTgtAddressB, ///< Bit field BFTgtAddressB - BFBubbleCnt2, ///< Bit field BFBubbleCnt2 - BFBubbleCnt, ///< Bit field BFBubbleCnt - BFCmdStreamLen, ///< Bit field BFCmdStreamLen - BFCmdCount, ///< Bit field BFCmdCount - BFErrDqNum, ///< Bit field BFErrDQNum - BFErrCnt, ///< Bit field BFErrCnt - BFNibbleErrSts, ///< Bit field BFNibbleErrSts - BFNibbleErr180Sts, ///< Bit field BFNibbleErr180Sts - BFDataPrbsSeed, ///< Bit field BFDataPrbsSeed - BFDramDqMaskLow, ///< Bit field BFDramDqMaskLow - BFDramDqMaskHigh, ///< Bit field BFDramDqMaskHigh - BFDramEccMask, ///< Bit field BFDramEccMask - BFSendActCmd, ///< Bit field BFSendActCmd - BFSendPchgCmd, ///< Bit field BFSendPchgCmd - BFCmdChipSelect, ///< Bit field BFCmdChipSelect - BFCmdBank, ///< Bit field BFCmdBank - BFCmdAddress, ///< Bit field BFCmdAddress - BFErrBeatNum, ///< Bit Field BFErrBeatNum - BFErrCmdNum, ///< Bit field BFBFErrCmdNum - BFDQErrLow, ///< Bit field BFDQSErrLow - BFDQErrHigh, ///< Bit field BFDQSErrHigh - BFEccErr, ///< Bit field BFEccErr - BFFastMstateDis, ///< Bit field BFFastMstateDis - - /* Bit fields for workarounds */ - BFErr263, ///< Bit field Err263 - BFErr350, ///< Bit field Err350 - BFErr322I, ///< Bit field Err322I - BFErr322II, ///< Bit field Err322II - BFErratum468WorkaroundNotRequired, ///< Bit field Erratum468WorkaroundNotRequired - - /* Bit fields for Phy */ - BFEccDLLConf, ///< Bit field EccDLLConf - BFProcOdtAdv, ///< Bit field ProcOdtAdv - BFEccDLLPwrDnConf, ///< Bit field EccDLLPwrDnConf - BFPhyPLLLockTime, ///< Bit field PhyPLLLockTime - BFPhyDLLLockTime, ///< Bit field PhyDLLLockTime - BFSkewMemClk, ///< Bit field SkewMemClk - BFPhyDLLControl, ///< Bit field BFPhyDLLControl - BFPhy0x0D080F0C, ///< Bit field BFPhy0x0D080F0C - BFPhy0x0D080F10, ///< Bit field BFPhy0x0D080F10 - BFPhy0x0D080F11, ///< Bit field BFPhy0x0D080F11 - BFPhy0x0D088F30, ///< Bit field BFPhy0x0D088F30 - BFPhy0x0D08C030, ///< Bit field BFPhy0x0D08C030 - BFPhy0x0D082F30, ///< Bit field BFPhy0x0D082F30 - BFDiffTimingEn, ///< Bit Field DiffTimingEn - BFFence, ///< Bit Field Fence - BFDelay, ///< Bit Field Delay - BFFenceValue, ///< Bit Field FenceValue - - BFPhy0x0D040F3E, ///< Bit field BFPhy0x0D040F3E - BFPhy0x0D042F3E, ///< Bit field BFPhy0x0D042F3E - BFPhy0x0D048F3E, ///< Bit field BFPhy0x0D048F3E - BFPhy0x0D04DF3E, ///< Bit field BFPhy0x0D04DF3E - - BFPhyClkDllFine0, ///< Bit field ClkDllFineDly 0 - BFPhyClkDllFine1, ///< Bit field ClkDllFineDly 1 - - BFPhyClkConfig0, ///< Bit field ClkConfig0 - BFPhyClkConfig1, ///< Bit field ClkConfig1 - BFPhyClkConfig2, ///< Bit field ClkConfig2 - BFPhyClkConfig3, ///< Bit field ClkConfig3 - - BFPhy0x0D0F0F13, ///< Bit field BFPhy0x0D0F0F13 - BFPhy0x0D0F0F13Bit0to7, ///< Bit field BFPhy0x0D0F0F13Bit0to7 - BFPhy0x0D0F0830, ///< Bit field BFPhy0x0D0F0830 - BFPhy0x0D07812F, ///< Bit field BFPhy0x0D0F8108 - - BFDataRxVioLvl, ///< Bit field DataRxVioLvl - BFClkRxVioLvl, ///< Bit field ClkRxVioLvl - BFCmdRxVioLvl, ///< Bit field CmdRxVioLvl - BFAddrRxVioLvl, ///< Bit field AddrRxVioLvl - BFCmpVioLvl, ///< Bit field CmpVioLvl - BFCsrComparator, ///< Bit field CsrComparator - BFAlwaysEnDllClks, ///< Bit field AlwaysEnDllClks - BFPhy0x0D0FE00A, ///< Bit field Phy0x0D0FE00A - BFPllPdMode, ///< Bit fields SelCsrPllPdMode and CsrPhySrPllPdMode - - BFDataFence2, ///< Bit field DataFence2 - BFClkFence2, ///< Bit field ClkFence2 - BFCmdFence2, ///< Bit field CmdFence2 - BFAddrFence2, ///< Bit field AddrFence2 - - BFDataByteDMConf, ///< Bit field DataByteDMConf - - BFAddrCmdTri, ///< Bit field BFAddrCmdTri - BFLowPowerDrvStrengthEn, ///< Bit field BFLowPowerDrvStrengthEn - BFLevel, ///< Bit field Level - - BFDbeGskFifoNumerator, ///< Bit field DbeGskFifoNumerator - BFDbeGskFifoDenominator, ///< Bit field DbeGskFifoDenominator - BFDataTxFifoSchedDlyNegSlot0, ///< Bit field DataTxFifoSchedDlyNegSlot0 - BFDataTxFifoSchedDlyNegSlot1, ///< Bit field DataTxFifoSchedDlyNegSlot1 - BFDataTxFifoSchedDlySlot0, ///< Bit field DataTxFifoSchedDlySlot0 - BFDataTxFifoSchedDlySlot1, ///< Bit field DataTxFifoSchedDlySlot1 - - BFDisablePredriverCal, ///< Bit field DisablePredriverCal - BFDataByteTxPreDriverCal, ///< Bit field DataByteTxPreDriverCal - BFDataByteTxPreDriverCal2Pad1, ///< Bit field DataByteTxPreDriverCal2Pad1 - BFDataByteTxPreDriverCal2Pad2, ///< Bit field DataByteTxPreDriverCal2Pad2 - BFCmdAddr0TxPreDriverCal2Pad1, ///< Bit field CmdAddr0TxPreDriverCal2Pad1 - BFCmdAddr0TxPreDriverCal2Pad2, ///< Bit field CmdAddr0TxPreDriverCal2Pad2 - BFCmdAddr1TxPreDriverCal2Pad1, ///< Bit field CmdAddr1TxPreDriverCal2Pad1 - BFCmdAddr1TxPreDriverCal2Pad2, ///< Bit field CmdAddr1TxPreDriverCal2Pad2 - BFAddrTxPreDriverCal2Pad1, ///< Bit field AddrTxPreDriverCal2Pad1 - BFAddrTxPreDriverCal2Pad2, ///< Bit field AddrTxPreDriverCal2Pad2 - BFAddrTxPreDriverCal2Pad3, ///< Bit field AddrTxPreDriverCal2Pad3 - BFAddrTxPreDriverCal2Pad4, ///< Bit field AddrTxPreDriverCal2Pad4 - BFCmdAddr0TxPreDriverCalPad0, ///< Bit field CmdAddr0TxPreDriverCalPad0 - BFCmdAddr1TxPreDriverCalPad0, ///< Bit field CmdAddr1TxPreDriverCalPad0 - BFAddrTxPreDriverCalPad0, ///< Bit field AddrTxPreDriverCalPad0 - BFClock0TxPreDriverCalPad0, ///< Bit field Clock0TxPreDriverCalPad0 - BFClock1TxPreDriverCalPad0, ///< Bit field Clock1TxPreDriverCalPad0 - BFClock2TxPreDriverCalPad0, ///< Bit field Clock2TxPreDriverCalPad0 - BFPNOdtCal, ///< Bit field P/NOdtCal - BFPNDrvCal, ///< Bit field P/NDrvCal - BFCalVal, ///< Bit field CalVal - BFPStateToAccess, ///< Bit field PStateToAccess - - BFTxp, ///< Bit field Txp - BFTxpdll, ///< Bit field Txpdll - BFDramPwrMngm1Reg, ///< Bit field DRAM Power Management 1 register - BFL3ScrbRedirDis, ///< Bit field L3ScrbRedirDis - BFDQOdt03, ///< Bit field DQ Odt 0-3 - BFDQOdt47, ///< Bit field DQ Odt 4-7 - BFTriDM, ///< Bit field TriDM - - BFTcksrx, ///< Bit field Tcksrx - BFTcksre, ///< Bit field Tcksre - BFTckesr, ///< Bit field Tckesr - BFTpd, ///< Bit field Tpd - - BFFixedErrataSkipPorFreqCap, ///< Bit field FixedErrataSkipPorFreqCap - BFPerRankTimingEn, ///< Bit field PerRankTimingEn - BFMemPhyPllPdMode, ///< Bit field MemPhyPllPdMode - BFBankSwap, ///< Bit field BankSwap - BFBwCapCmdThrottleMode, ///< Bit field BwCapCmdThrottleMode - BFRxChMntClkEn, ///< Bit field RxChMntClkEn - BFBlockRxDqsLock, ///< Bit field BlockRxDqsLock - BFRxSsbMntClkEn, ///< Bit field RxSsbMntClkEn - BFPhyPSMasterChannel, ///< Bit field PhyPSMasterChannel - - BFDataByteDllPowerMgnByte0, ///< Bit field DataByteDllPowerManagement for Byte 0 - BFDataByteDllPowerMgnByte1, ///< Bit field DataByteDllPowerManagement for Byte 1 - BFDataByteDllPowerMgnByte2, ///< Bit field DataByteDllPowerManagement for Byte 2 - BFDataByteDllPowerMgnByte3, ///< Bit field DataByteDllPowerManagement for Byte 3 - BFDataByteDllPowerMgnByte4, ///< Bit field DataByteDllPowerManagement for Byte 4 - BFDataByteDllPowerMgnByte5, ///< Bit field DataByteDllPowerManagement for Byte 5 - BFDataByteDllPowerMgnByte6, ///< Bit field DataByteDllPowerManagement for Byte 6 - BFDataByteDllPowerMgnByte7, ///< Bit field DataByteDllPowerManagement for Byte 7 - BFDataByteDllPowerMgnByte8, ///< Bit field DataByteDllPowerManagement for Byte ECC - BFDataByteDllPowerMgnByteAll, ///< Bit field DataByteDllPowerManagement for all bytes - - BFM1MemClkFreq, ///< Bit field M1MemClkFreq - BFRate, ///< Bit field Rate - BFFence2, ///< Bit field Fence2 - - BFNbVid0, ///< Bit field NbVid for NB Pstate 0 - BFNbVid0Hi, ///< Bit field 7th bit of NbVid for NB Pstate 0 - BFNbVid1, ///< Bit field NbVid for NB Pstate 1 - BFNbVid1Hi, ///< Bit field 7th bit of NbVid for NB Pstate 1 - BFNbVid2, ///< Bit field NbVid for NB Pstate 2 - BFNbVid2Hi, ///< Bit field 7th bit of NbVid for NB Pstate 2 - BFNbVid3, ///< Bit field NbVid for NB Pstate 3 - BFNbVid3Hi, ///< Bit field 7th bit of NbVid for NB Pstate 3 - - BFMemPstate0, ///< Bit field MemPstate for NB Pstate 0 - BFMemPstate1, ///< Bit field MemPstate for NB Pstate 1 - BFMemPstate2, ///< Bit field MemPstate for NB Pstate 2 - BFMemPstate3, ///< Bit field MemPstate for NB Pstate 3 - BFMemPstateDis, ///< Bit field MemPstateDis - - BFRxBypass3rd4thStg, ///< Bit field RxBypass3rd4thStg - BFRx4thStgEn, ///< Bit field Rx4thStgEn - BFDllNoLock, ///< Bit field DllNoLock - BFEnSplitMctDatBuffers, ///< Bit field EnSplitMctDatBuffers - BFGmcTokenLimit, ///< Bit fieid GmcTokenLimit - BFMctTokenLimit, ///< Bit field MctTokenLimit - BFGmcToDctControl1, ///< Bit field GmcToDctControl1 - BFDllCSRBisaTrimDByte, ///< Bit field DllCSRBisaTrimDByte - BFDllCSRBisaTrimClk, ///< Bit field DllCSRBisaTrimClk - BFDllCSRBisaTrimCsOdt, ///< Bit field DllCSRBisaTrimCsOdt - BFDllCSRBisaTrimAByte2, ///< Bit field DllCSRBisaTrimAByte2 - BFReduceLoop, ///< Bit field ReduceLoop - BFEffArbDis, ///< Bit field EffArbDis - - // Reserved - BFReserved01, ///< Reserved 01 - BFReserved02, ///< Reserved 02 - BFReserved03, ///< Reserved 03 - BFReserved04, ///< Reserved 04 - BFReserved05, ///< Reserved 05 - BFReserved06, ///< Reserved 06 - BFReserved07, ///< Reserved 07 - BFReserved08, ///< Reserved 08 - BFReserved09, ///< Reserved 09 - BFReserved10, ///< Reserved 10 - - BFReserved11, ///< Reserved 11 - BFReserved12, ///< Reserved 12 - BFReserved13, ///< Reserved 13 - BFReserved14, ///< Reserved 14 - BFReserved15, ///< Reserved 15 - BFReserved16, ///< Reserved 16 - BFReserved17, ///< Reserved 17 - BFReserved18, ///< Reserved 18 - BFReserved19, ///< Reserved 19 - BFReserved20, ///< Reserved 20 - - BFDctSelBaseAddrReg, ///< Bit field DctSelBaseAddrReg - BFDctSelBaseOffsetReg, ///< Bit field DctSelBaseOffsetReg - - /* End of accessible list --- entries below this line are for private use ------------*/ - BFEndOfList, ///< End of bit field list - - // Only for Table Drive Support define. - BFRcvEnDly, ///< F2x[1,0]9C_x[2B:10] Dram DQS Receiver Enable Timing Control Registers - BFWrDatDly, ///< F2x[1, 0]9C_x[302:301, 202:201, 102:101, 02:01] DRAM Write Data Timing [High:Low] Registers - BFRdDqsDly, ///< F2x[1, 0]9C_x[306:305, 206:205, 106:105, 06:05] DRAM Read DQS Timing Control [High:Low] Registers - BFWrDqsDly, ///< F2x[1, 0]9C_x[4A:30] DRAM DQS Write Timing Control Registers - BFPhRecDly, ///< F2x[1, 0]9C_x[51:50] DRAM Phase Recovery Control Register [High:Low] Registers - - /* Do not define any entries beyond this point */ - BFAbsLimit ///< Beyond this point is reserved for bit field manipulation - -} BIT_FIELD_NAME; - -/// Bit field aliases -#define BFMainPllOpFreqId BFNbFid -#define BFNbDid BFNbPs0NclkDiv -#define BFRdDramTrainMode BFPrefDramTrainMode -#define BFThrottleEn BFCmdThrottleMode -#define BFIntlvRegionEn BFIntLvRgnSwapEn -#define BFIntlvRegionBase BFIntLvRgnBaseAddr -#define BFIntlvRegionLimit BFIntLvRgnLmtAddr -#define BFRdOdtPatReg BFPhyRODTCSLow -#define BFWrOdtPatReg BFPhyWODTCSLow -#define BFLockDramCfg BFC6DramLock -#define BFRstRcvFifo BFTwr -#define BFDramCmd2Reg BFCmdBank -#define BFDramODTCtlReg BFRdOdtTrnOnDly - -/// Bit field names per DRAM CS base address register -typedef enum { - BFCSEnable = 0, ///< Chip select enable - BFSpare = 1, ///< Spare rank - BFTestFail = 2, ///< Memory test failed - BFOnDimmMirror = 3 ///< on-DIMM mirroring enable -} CS_BASE_BIT_FIELD; - -/// Flag for exclude dimm -typedef enum { - NORMAL, ///< Normal mode, exclude the dimm if there is new dimm failure - TRAINING, ///< Training mode, exclude dimms that fail during training after training is done - END_TRAINING ///< End training mode, exclude all dimms that failed during training -} DIMM_EXCLUDE_FLAG; - -#define BSP_DIE 0 -#define MAX_NODES_SUPPORTED 8 ///< Maximum number of nodes in the system. -#define MAX_CS_PER_CHANNEL 8 ///< Max CS per channel -#define MAX_CS_PER_DELAY 2 ///< Max Chip Select Controlled by a set of delays. - -#define VDDIO_DETERMINED 0xFF ///< VDDIO has been determined yet. Further processing is not needed. - -/// -/// MEM_SHARED_DATA -/// This structure defines the shared data area that is used by the memory -/// code to share data between different northbridge objects. Each substructure -/// in the data area defines how this data area is used by a different purpose. -/// -/// There should only be one instance of this struct created for all of the memory -/// code to use. -/// -typedef struct _MEM_SHARED_DATA { - - // System memory map data - UINT32 CurrentNodeSysBase; ///< Base[47:16] (system address) DRAM base address for current node. - /// Memory map data for each node - BOOLEAN AllECC; ///< ECC support on the system - DIMM_EXCLUDE_FLAG DimmExcludeFlag; ///< Control the exclude dimm behavior - UINT8 VoltageMap; ///< The commonly supported voltage map in the system - - UINT8 TopNode; ///< Node that has its memory mapped to TOPMEM/TOPMEM2 - BOOLEAN C6Enabled; ///< TRUE if C6 is enabled - - /// Data structure for NB register table - struct { - UINT64 FamilyId; ///< LogicalCpuid.Family - UINT32 *NBRegTable; ///< Pointer to allocated buffer for NBRegTable - } NBRegMap[MAX_NODES_SUPPORTED]; - - /// Data structure for node map - struct { - BOOLEAN IsValid; ///< TRUE if this node contains memory. - UINT32 SysBase; ///< Base[47:16] (system address) DRAM base address of this node. - UINT32 SysLimit; ///< Base[47:16] (system address) DRAM limit address of this node. - } NodeMap[MAX_NODES_SUPPORTED]; - BOOLEAN UndoHoistingAbove1TB; ///< Undo hoisting above 1TB - - /// Data structure for node interleave feature - struct { - BOOLEAN IsValid; ///< TRUE if the data in this structure is valid. - UINT8 NodeCnt; ///< Number of nodes in the system. - UINT32 NodeMemSize; ///< Total memory of this node. - UINT32 Dct0MemSize; ///< Total memory of this DCT 0. - UINT8 NodeIntlvSel; ///< Index to each node. - } NodeIntlv; -} MEM_SHARED_DATA; - -/// -/// MEM_MAIN_DATA_BLOCK -/// -typedef struct _MEM_MAIN_DATA_BLOCK { - struct _MEM_DATA_STRUCT *MemPtr; ///< Pointer to customer shared data - struct _MEM_NB_BLOCK *NBPtr; ///< Pointer to array of NB Blocks - struct _MEM_TECH_BLOCK *TechPtr; ///< Pointer to array of Tech Blocks - struct _MEM_SHARED_DATA *mmSharedPtr; ///< Pointer to shared data area. - UINT8 DieCount; ///< Total number of Dies installed -} MEM_MAIN_DATA_BLOCK; - -/*---------------------------------------------------------------------------- - * FUNCTIONS PROTOTYPE - * - *---------------------------------------------------------------------------- - */ - - -/* -node: Indicates the Node -- Value ranges from 0-7, 0xF: for all nodes -- Size - 4 Bits - -dct: Indicate the DRAM Controller -- Value is 0, 1 (0xF: apply setting to all DCTs) -- Size - 4 Bits - -dimm: This values specifies which DIMM register will be applied -- The value varies from 0 to 3, 0xF: all DIMMs -- Size - 4 Bits - -attr - Indicates if the value needs to be added, subtracted, overridden or Auto (not changed) -- 0: Do not change the current value in the register -- 1: Use the value provided in the table to override the current value in the register (the one that AGESA initially determined) -- 2: Add the value provided in the table as an offset to the current value in the register (the one that AGESA initially determined) -- 3: Subtract the value provided in the table as an offset to the current value in the register (the one that AGESA initially determined) -- Size - 2 Bits - -time - Indicate the timing for the register which is written. -- 0: Write register value before Dram init -- 1: Write register value before memory training -- 2: Write register value after memory training -- Size - 1 Bits - -bytelane: bytelane number -- This determines specifies which bytelane register will be applied -- Bit0 =1 - set value into Bytelane0 -- Bit1 =1 - set value into Bytelane1 -- Bit2 =1 - set value into Bytelane2 -... -... -- 0xFFFF: all bytelane -- Size - 16 Bits. - -bfIndex: Indicate the bitfield index -- Size - 16 Bits - -value - Value to be used -- This can be an offset (sub or Add) or an override value. -- Size - DWORD -*/ - -// Sample code -// NBACCESS (MTBeforeDInit, MTNodes, MTDct0, BFCSBaseAddr5Reg, MTOverride, 0x400001), -// NBACCESS (MTBeforeTrn, MTNodes, MTDct1, BFCSBaseAddr7Reg, MTOverride, 0xFFFFFFFF), -// DQSACCESS (MTAfterTrn, MTNodes, MTDcts, MTDIMM0, MTBL1+MTBL2, BFRcvEnDly, MTSubtract, 2), -// DQSACCESS (MTAfterTrn, MTNodes, MTDct1, MTDIMM1, MTBLNOECC, BFRcvEnDly, MTAdd, 1), - -#define ENDMEMTDS 0, 0, 0, 0, 0, 0, 0xFFFFFFFF, 0 - -#define NBACCESS(time, node, dct, bitfield, attr, value) \ -{ (time), \ - ((node) & 0x0F) | ((dct) << 4), \ - (((attr) & 0x07) << 4) | (VT_MSK_VALUE << 7) , \ - (UINT8)((bitfield) & 0x000000FF), \ - (UINT8)(((bitfield) >> 8) & 0x000000FF), \ - (UINT8)(((bitfield) >> 16) & 0x000000FF), \ - (UINT8)(((bitfield) >> 24) & 0x000000FF), \ - 0, 0, \ - (UINT8)((value) & 0x000000FF), \ - (UINT8)(((value) >> 8) & 0x000000FF), \ - (UINT8)(((value) >> 16) & 0x000000FF), \ - (UINT8)(((value) >> 24) & 0x000000FF), \ - 0, 0, 0 \ -} - -#define DQSACCESS(time, node, dct, dimm, bitfield, attr, b0, b1, b2, b3, b4, b5, b6, b7, b8) \ -{ (time), \ - ((node) & 0x0F) | ((dct) << 4), \ - (((dimm) & 0x0F) | ((attr) & 0x07) << 4) | (VT_ARRAY << 7) , \ - (UINT8)((bitfield) & 0x000000FF), \ - (UINT8)(((bitfield) >> 8) & 0x000000FF), \ - (UINT8)(((bitfield) >> 16) & 0x000000FF), \ - (UINT8)(((bitfield) >> 24) & 0x000000FF), \ - (b0), (b1), (b2), (b3), (b4), (b5), (b6), (b7), (b8) \ -} - -/// Type of modification supported by table driven support. -typedef enum { - MTAuto, ///< Do not change the current value in the register - MTOverride, ///< Use the value provided in the table to override the current value in the register - MTSubtract, ///< Subtract the value provided in the table as an offset to the current value in the register - MTAdd, ///< Add the value provided in the table as an offset to the current value in the reg - MTAnd, ///< And the value provided in the table as an offset to the current value in the reg - MTOr ///< Or the value provided in the table as an offset to the current value in the reg -} MTAttr; - -/// Time for table driven support to make modification. -typedef enum { - MTBeforeInitializeMCT, ///< Before InitializeMCT - MTAfterAutoCycTiming, ///< After Auto Cycle Timing - MTAfterPlatformSpec, ///< After Platform Specific Configuration - MTBeforeDInit, ///< Before Dram init - MTBeforeTrn, ///< Before memory training - MTAfterTrn, ///< After memory training - MTAfterSwWLTrn, ///< After SW Based WL Training - MTAfterHwWLTrnP1, ///< After HW Based WL Training Part 1 - MTAfterHwRxEnTrnP1, ///< After HW Based Receiver Enable Training Part 1 - MTAfterFreqChg, ///< After each frequency change - MTAfterHwWLTrnP2, ///< After HW Based WL Training Part 2 - MTAfterHwRxEnTrnP2, ///< After HW Based Receiver Enable Training Part 2 - MTAfterSwRxEnTrn, ///< After SW Based Receiver Enable Training - MTAfterDqsRwPosTrn, ///< After DQS Read/Write Position Training - MTAfterMaxRdLatTrn, ///< After Max Read Latency Training - MTAfterNbPstateChange, ///< After programming NB Pstate dependent registers - MTAfterInterleave, ///< After Programming Interleave registers - MTAfterFinalizeMCT, ///< After Finalize MCT Programming - - MTValidTimePointLimit, ///< Mark the upper bound of the supported time points - MTEnd = 0xFF ///< End of enum define. -} MTTime; - -/// Node on which modification should be made by table driven support. -typedef enum { - MTNode0, ///< Node 0. - MTNode1, ///< Node 1. - MTNode2, ///< Node 2. - MTNode3, ///< Node 3. - MTNode4, ///< Node 4. - MTNode5, ///< Node 5. - MTNode6, ///< Node 6. - MTNode7, ///< Node 7. - MTNodes = 0xF ///< all nodes -} MTNode; - -/// DCT on which modification should be made by table driven support. -typedef enum { - MTDct0, ///< DCT 0. - MTDct1, ///< DCT 1. - MTDcts = 0xF, ///< all dcts -} MTDct; - -/// Dimm on which modification should be made by table driven support. -typedef enum { - MTDIMM0, ///< Dimm 0. - MTDIMM1, ///< Dimm 1. - MTDIMM2, ///< Dimm 2. - MTDIMM3, ///< Dimm 3. - MTDIMMs = 0xF, ///< all Dimms -} MTDIMM; - -/// Bytelane on which modification should be made by table driven support. -typedef enum { - MTBL0 = 0x1, ///< set the value into Bytelane0 - MTBL1 = 0x2, ///< set the value into Bytelane1 - MTBL2 = 0x4, ///< set the value into Bytelane2 - MTBL3 = 0x8, ///< set the value into Bytelane3 - MTBL4 = 0x10, ///< set the value into Bytelane4 - MTBL5 = 0x20, ///< set the value into Bytelane5 - MTBL6 = 0x40, ///< set the value into Bytelane6 - MTBL7 = 0x80, ///< set the value into Bytelane7 - MTBL8 = 0x100, ///< set the value into ECC - MTBLNOECC = 0xFF, ///< all Bytelanes except ECC - MTBLs = 0xFFFF, ///< all Bytelanes -} MTBL; - -/// Values used to indicate which type of training is being done. -typedef enum { - TRN_RCVR_ENABLE, ///< Reciever Enable Training - TRN_DQS_POSITION, ///< Read/Write DQS Position training - TRN_MAX_READ_LATENCY ///< Max read Latency training -} TRAINING_TYPE; - -/// Memory Pstate -typedef enum { - MEMORY_PSTATE0, ///< Memory Pstate 0 - MEMORY_PSTATE1, ///< Memory Pstate 1 -} MEM_PSTATE; - -/// Memory Pstate Training Stage -typedef enum { - MEMORY_PSTATE_1ST_STAGE = 0xF1, ///< Memory Pstate processing stage 1, in which full training is done at DDR667 - MEMORY_PSTATE_2ND_STAGE, ///< Memory Pstate processing stage 2, in which partial trainig will be done at DDR800 - target speed - MEMORY_PSTATE_3RD_STAGE ///< Memory Pstate processing stage 3, in which full training will be done at target frequency and MaxRdLatency training will start -} MEM_PSTATE_STAGE; - -/// RdDqsDly Retrain status -typedef enum { - RDDQSDLY_RTN_NEEDED = 0xF1, ///< RdDqsDly retrain may be needed - RDDQSDLY_RTN_SUSPEND, ///< RdDqsDly retrain is suspected - RDDQSDLY_RTN_ONGOING ///< RdDqsDly retrain condition is just detected -} RDDQSDLY_RTN_STAT; -/*---------------------------------------------------------------------------- - * FUNCTIONS PROTOTYPE - * - *---------------------------------------------------------------------------- - */ -AGESA_STATUS -MemAmdFinalize ( - IN OUT MEM_DATA_STRUCT *MemPtr - ); - -AGESA_STATUS -MemSocketScan ( - IN OUT MEM_MAIN_DATA_BLOCK *mmPtr - ); - -VOID -SetMemError ( - IN AGESA_STATUS Errorval, - IN OUT DIE_STRUCT *MCTPtr - ); - -VOID -AmdMemInitDataStructDefRecovery ( - IN OUT MEM_DATA_STRUCT *MemPtr - ); - -VOID -SetMemRecError ( - IN AGESA_STATUS Errorval, - IN OUT DIE_STRUCT *MCTPtr - ); - -AGESA_STATUS -memDefRetSuccess (VOID); - -#endif /* _MM_H_ */ - - diff --git a/src/vendorcode/amd/agesa/f12/Proc/Mem/mn.h b/src/vendorcode/amd/agesa/f12/Proc/Mem/mn.h deleted file mode 100644 index f211bd856a..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/Mem/mn.h +++ /dev/null @@ -1,1631 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * mn.h - * - * Common Northbridge - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: (Mem) - * @e \$Revision: 49896 $ @e \$Date: 2011-03-30 16:18:18 +0800 (Wed, 30 Mar 2011) $ - * - **/ -/***************************************************************************** - * - * Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * *************************************************************************** - * - */ - -#ifndef _MN_H_ -#define _MN_H_ - -/*---------------------------------------------------------------------------- - * Mixed (DEFINITIONS AND MACROS / TYPEDEFS, STRUCTURES, ENUMS) - * - *---------------------------------------------------------------------------- - */ - -/*----------------------------------------------------------------------------- - * DEFINITIONS AND MACROS - * - *----------------------------------------------------------------------------- - */ -#define _4GB_RJ16 (((UINT32) 4) << (30 - 16)) -#define _1TB_RJ16 (((UINT32) 1) << (40 - 16)) -#define HT_REGION_BASE_RJ16 ((UINT32)0x00FD0000) - -#define DCT_ACCESS_WRITE (UINT32) 0x40000000 -#define MTRR_VALID 11 -#define THERMAL_OPT 31 - -#define NB_ACCESS 0 -#define DCT_PHY_ACCESS 1 -#define DCT_EXTRA 2 - -#define DCT_PHY_DIRECT 0xF1 - -#define VT_MSK_VALUE 0 -#define VT_ARRAY 1 -/*--------------------------------------------- - * TSEFO - Type Start End Function Offset - * - * 31:30 Type of access (2-bits) - * 29:29 Special (1-bit) - * 28:28 Phy Direct (1-bit) - * 27:27 Whole Register Access (1-bit) - * 26:26 Linked (1-bit) - * 25:21 Start bit (5-bits) - * 20:16 End bit (5-bits) - * 15:00 Function_Offset/Index (16-bits) - *--------------------------------------------- - */ -typedef UINT32 TSEFO; - -/** - MAKE_TSEFO(TableName, a, b, c, d, BitFieldIndex): - - @param[in] TableName - @param[in] BitFieldIndex - @param[in] a Type of access. - @param[in] b Index of register (can be in Function_Offset format). - @param[in] c Highest bit of the bit field. - @param[in] d Lowest bit of the bit field. - - @return TSEFO Access params encrypted in TSEFO format. ---*/ -#define MAKE_TSEFO(TableName, a, b, c, d, BitFieldIndex) \ -TableName[BitFieldIndex] = ( \ - (a == DCT_PHY_DIRECT) ? ( \ - (((UINT32) DCT_PHY_ACCESS) << 30) | (((UINT32) 1) << 28) | (((UINT32) b) & 0xFFFF) | (\ - ((c == 15) && (d == 0)) ? ( \ - (((UINT32) 1) << 27) | (((UINT32) b) & 0xF0000) \ - ) : ( \ - (c >= d) ? ( \ - (((UINT32) c) << 21) | (((UINT32) d) << 16) \ - ) : ( \ - (((UINT32) d) << 21) | (((UINT32) c) << 16) \ - ) \ - ) \ - ) \ - ) : ( \ - (((UINT32) a) << 30) | (((UINT32) b) & 0xFFFFFFF) | ( \ - (((UINT32) b) >> 16) ? ( \ - (((UINT32) 1) << 29) \ - ) : ( \ - (c >= d) ? ( \ - (((UINT32) c) << 21) | (((UINT32) d) << 16) \ - ) : ( \ - (((UINT32) d) << 21) | (((UINT32) c) << 16) \ - ) \ - ) \ - ) \ - ) \ -) - -/** - LINK_TSEFO(TableName, LowerBitFieldIndex, HigherBitFieldIndex): - This is one way link: any write to LowerBitFieldIndex would write to HigherBitFieldIndex, - but NOT the other way around. - Requirement: LowerBitFieldIndex must be declared *right* before HigherBitFieldIndex. - - @param[in] TableName - @param[in] LowerBitFieldIndex - @param[in] HigherBitFieldIndex - - @return TSEFO Access params encrypted in TSEFO format. ---*/ -#define LINK_TSEFO(TableName, LowerBitFieldIndex, HigherBitFieldIndex) { \ - ASSERT (LowerBitFieldIndex == (HigherBitFieldIndex - 1)) ; \ - TableName[LowerBitFieldIndex] = TableName[LowerBitFieldIndex] | (((UINT32) 1) << 26); \ -} - -// Indicate when a bitfield has multiple memory Pstate copy -#define MULTI_MPSTATE_COPY_TSEFO(TableName, BitFieldName) \ - TableName[BitFieldName] = TableName[BitFieldName] | (((UINT32) 1) << 29) - -#define TSEFO_TYPE(x) ((UINT8) (((UINT32) (x) >> 30) & 0x03)) -#define TSEFO_START(x) ((UINT8) (((UINT32) (x) >> 21) & 0x1F)) -#define TSEFO_END(x) ((UINT8) (((UINT32) (x) >> 16) & 0x1F)) -#define TSEFO_OFFSET(x) ((UINT32) (x) & 0xFFFF) -#define TSEFO_LINKED(x) ((UINT8) (((UINT32) (x) >> 26) & 0x01)) -#define TSEFO_DIRECT_EN(x) ((UINT8) (((UINT32) (x) >> 28) & 0x01)) -#define TSEFO_WHOLE_REG_ACCESS(x) ((UINT8) (((UINT32) (x) >> 27) & 0x01)) -#define _FN(x, y) (((UINT32) (x) << 12) + (UINT32) (y)) -#define TSEFO_MULTI_MPSTATE_COPY(x) ((UINT8) (((UINT32) (x) >> 29) & 1)) -#define _NOT_USED_ 0 - -/* */ -#define B0_DLY 0 -#define B1_DLY 1 -#define B2_DLY 2 -#define B3_DLY 3 -#define B4_DLY 4 -#define B5_DLY 5 -#define B6_DLY 6 -#define B7_DLY 7 -#define ECC_DLY 8 - -#define DDR2_TRAIN_FLOW 0 -#define DDR3_TRAIN_FLOW 1 - -// -// Minimum Data Eye width in consecutive 32nds of a UI of -// valid data -// -#define MIN_RD_DATAEYE_WIDTH_NB 4 -#define MIN_WR_DATAEYE_WIDTH_NB 4 - -// -// RELIABLE READ/WRITE MODE DEFINITIONS -// -#define PRECHARGE_ALL_BANKS 0xFF ///< Use to specify PrechargeAll Command to Precharge Cmd Function -#define CMD_TGT_A 0x00 ///< Issue Commands to Command Target A -#define CMD_TGT_AB 0x01 ///< Issue Commands to Command Targets A and B -#define CMD_TYPE_READ 0x00 ///< Read Command -#define CMD_TYPE_WRITE 0x01 ///< Write Command -#define CMD_TYPE_WR_RD 0x02 ///< Alternating Write and Read Commands -#define CPG_BANK_ADDRESS_A 0x0 ///< Dimm Bank address used in Reliable RD/RW mode training -#define CPG_BANK_ADDRESS_B 0x1 ///< Dimm Bank address used in Reliable RD/RW mode training -#define CPG_ROW_ADDRESS_A 0x0 ///< Dimm Row address used in Reliable RD/RW mode training -#define CPG_ROW_ADDRESS_B 0x0 ///< Dimm Row address used in Reliable RD/RW mode training -#define CPG_COL_ADDRESS_A 0x0 ///< Dimm Column address used in Reliable RD/RW mode training -#define CPG_COL_ADDRESS_B 0x0 ///< Dimm Column address used in Reliable RD/RW mode training -#define CPG_COMPARE_MASK_LOW 0x00000000 ///< Dram DQMask[31:0] used to mask comparison on reads. 1=ignore -#define CPG_COMPARE_MASK_HI 0x00000000 ///< Dram DQMask[63:32] used to mask comparison on reads. 1=ignore -#define CPG_COMPARE_MASK_ECC 0x00 ///< Dram EccMask used to mask comparison on reads. 1=ignore -#define PRBS_SEED_32 0x062221 ///< Data PRBS Seed -#define PRBS_SEED_64 0x066665 ///< Data PRBS Seed -#define PRBS_SEED_128 0x026666 ///< Data PRBS Seed -#define PRBS_SEED_256 0x044443 ///< Data PRBS Seed - - -/*---------------------------------------------------------------------------- - * TYPEDEFS, STRUCTURES, ENUMS - * - *---------------------------------------------------------------------------- - */ - -/// Structure for Reliable Read/Write Mode Data -/// These are values that may need to be referenced by the low level functions -/// during training and are initialized at the begining of a particular type of training. -typedef struct _RRW_SETTINGS { - UINT8 CmdTgt; ///< Value to program into CmdTgt - UINT8 TgtBankAddressA; ///< Target A Bank address - UINT32 TgtRowAddressA; ///< Target A Row address - UINT32 TgtColAddressA; ///< Target A Column address - UINT8 TgtBankAddressB; ///< Target B Bank address - UINT32 TgtRowAddressB; ///< Target B Row address - UINT32 TgtColAddressB; ///< Target B Column address - UINT32 CompareMaskLow; ///< Compare Mask Bits 31:0 - UINT32 CompareMaskHigh; ///< Compare Mask Bits 63:32 - UINT8 CompareMaskEcc; ///< Compare Mask Ecc - UINT32 DataPrbsSeed; ///< PRBS Seed value -} RRW_SETTINGS; - -/// DQS training related delays -typedef enum { - AccessRcvEnDly, ///< Receiver enable delay - AccessWrDatDly, ///< Write data delay - AccessRdDqsDly, ///< Read DQS delay - AccessWrDqsDly, ///< Write DQS delay - AccessPhRecDly ///< Phase recovery delay -} TRN_DLY_TYPE; - -/// Training patterns for position training -typedef enum { - POS_PATTERN_72B, ///< 72 bit pattern - POS_PATTERN_256B, ///< 256 bit pattern -} POS_TRN_PATTERN_TYPE; - -/// ODT mode -typedef enum { - MISSION_MODE, ///< ODT during mission mode - WRITE_LEVELING_MODE ///< ODT during write leveling -} ODT_MODE; - -/* - * DRBN - Dimm-Rank-Byte-Nibble - * 31:12 Reserved - * 11:09 Dimm (3-bits) - * 08 Rank (1-bit) - * 07:05 Reserved - * 04:01 Byte (4-bits) - * 00 Nibble (1-bit) - */ -typedef UINT32 DRBN; -#define MAKE_DRBN(dimm, rank, byte, nibble) ((((UINT32) (dimm)) << 9) | (((UINT32) (rank)) << 8) | \ -(((UINT32) (byte)) << 1) | ((UINT32) (nibble)) ) -#define DIMM_BYTE_ACCESS(dimm, byte) ((((UINT32) (dimm)) << 9) | (((UINT32) (byte)) << 1)) -#define CS_NBBL_ACCESS(cs, nibble) ((((UINT32) (cs)) << 8) | ((UINT32) (nibble))) -#define DRBN_DIMM(x) ((UINT8) (((UINT32) (x) >> 9) & 0x07)) -#define DRBN_RANK(x) ((UINT8) (((UINT32) (x) >> 8) & 0x01)) -#define DRBN_BYTE(x) ((UINT8) (((UINT32) (x) >> 1) & 0x0F)) -#define DRBN_NBBL(x) ((UINT8) (((UINT32) (x)) & 0x01)) - -/* Dimm Type mask */ -#define DT_X4 0x01 -#define DT_X8 0x02 -#define DT_X16 0x04 -#define DT_SR 0x10 -#define DT_DR 0x20 -#define DT_QR 0x40 - -#define DT_ANY_X4 0x71 -#define DT_ANY_X8 0x72 -#define DT_ANY_X16 0x74 -#define DT_ANY_SR 0x17 -#define DT_ANY_DR 0x27 -#define DT_ANY_QR 0x47 -#define DT_ANY_SR_DR (DT_ANY_SR | DT_ANY_DR) -#define DT_ANY (DT_ANY_SR | DT_ANY_DR | DT_ANY_QR) - -/// Delay Scaling Info Struct - Describes number of delay increments per UI of a delay type -/// -typedef struct _TRN_DLY_PARMS { - UINT8 Min; ///< Minimum Value - UINT8 Max; ///< Maximum Value - UINT8 Mask; ///< Mask to be applied (i.e. 0xFF if adjustable by one, 0xFE if adjustable by 2, etc.) -} TRN_DLY_PARMS; - -/// Structure for certain data saving needed for DCT. -typedef struct { - UINT8 RcvEnDlyCounts[8]; ///< DQS Receiver Enable Delay counts - UINT32 PhRecReg[3]; ///< 3 Phase recovery control registers -} MEM_DCT_CACHE; - -/// Structure for table driven support. -typedef struct _MEM_TBL_ALIAS { - UINT8 time; ///< Modification time. - UINT8 node:4; ///< Node on which to make modification. - UINT8 dct:4; ///< DCT on which to make modification. - UINT8 dimm:4; ///< Dimm on which to make modification. - UINT8 attr:3; ///< Attribute of modification. - UINT8 vtype:1; ///< Flag indicating value type. - UINT32 bfindex; ///< Bit field index that need to be modified. - union { ///< Union is defined to easy select between single and multiple bytelane cases. - struct { ///< Sub-struct used for one bytelane value. - UINT16 bytelane:16; ///< Bytelane on which to make modification. - UINT32 value; ///< Modified value. - UINT8 reserved[3]; ///< Reserved for this purpose - } s; ///< single value to one or multiple bytelanes - UINT8 bytelanevalue[9]; ///< Array to specify individual bytelane values - } data; -} MEM_TABLE_ALIAS; - -/// Structure for Platform Specific Block. -typedef struct _MEM_PS_BLOCK { - UINT8 DramTerm; ///< Dram Term - UINT8 QR_DramTerm; ///< Dram Term for QR - UINT8 DynamicDramTerm; ///< Dynamic Dram Term - UINT8 NumOfReg[MAX_DIMMS_PER_CHANNEL]; ///< Number of registers on each RDIMM (From SPD) - UINT8 MR0WR; ///< MR0WR - UINT8 MR0CL31; ///< MR0[CL][3:1] - UINT8 MR0CL0; ///< MR0CL[0] - UINT8 RttNom[8]; ///< RttNom value for maximum 8 chipsels per channel - UINT8 RttWr[8]; ///< RttWr value for maximum 8 chipsels per channel - UINT8 F0RC8; ///< F0RC8 - UINT8 F1RC0; ///< F1RC0 - UINT8 F1RC1; ///< F1RC1 - UINT8 F1RC2; ///< F1RC2 - UINT8 RC10OpSpd; ///< RC10[OperatingSpeed] - UINT8 LrdimmRowAddrBits[MAX_DIMMS_PER_CHANNEL]; ///< Effective Row address bits used by LRDIMMS - /* PUBLIC functions */ - BOOLEAN (*MemPDoPs) (struct _MEM_NB_BLOCK *NBPtr); ///< Function that gets Form factor info. - VOID (*MemPGetPORFreqLimit) (struct _MEM_NB_BLOCK *NBPtr); ///< Function that gets the speed limit of a dimm population. -} MEM_PS_BLOCK; - -/// Structure parameters needed in frequency change of client NB. -typedef struct _MEM_FREQ_CHANGE_PARAM { - UINT16 PllLockTimeDefault; ///< Default PllLockTime - UINT8 RdPtrInit667orHigher; ///< RdPtrInit for frequency 667MHz and higher - UINT8 RdPtrInitLower667; ///< RdPtrInit for frequency lower than 667MHz - UINT8 NclkPeriodMul2x; ///< Multiplier for NclkPeriod in parial sum calculation x 2 - UINT8 MemClkPeriodMul2x; ///< Multiplier for MemClkPeriod in parial sum calculation x 2 - UINT8 SyncTimeMul4x; ///< Multiplier for SyncTime - UINT16 TDataProp800orHigher; ///< TDataProp for frequency 800MHz or higher - UINT16 TDataPropLower800; ///< TDataProp for frequency lower than 800MHz -} MEM_FREQ_CHANGE_PARAM; - -/// List for NB items that are supported -typedef enum { - SetSpareEn, ///< Sets spare enable - CheckSpareEn, ///< Spare enabled - SetDllShutDown, ///< Sets DllShutDown - CheckEccDLLPwrDnConfig, ///< Checks to determine if EccDLLPwrDnConf needs to be adjusted - DimmBasedOnSpeed, ///< Checks to determine if Dimm number needs to be adjusted based on speed - CheckMaxDramRate, ///< Checks to determine the maximum rate - Check1GAlign, ///< Checks to determine if 1 GB alignment is supported - DramModeBeforeDimmPres, ///< Check to determine if DRAM mode needs to be set before dimm presence - DramModeAfterDimmPres, ///< Check to determine if DRAM mode needs to be set after dimm presence - CheckClearOnDimmMirror, ///< Check to determine if we need to clear on DIMM mirror - CheckDisDllShutdownSR, ///< Check to determine if DisDllShutdown needs to be set - CheckMemClkCSPresent, ///< Check to determine if chipselect needs to be set based on disabled memclocks - CheckChangeAvgValue, ///< Check to determine if we need to change average value - CheckMaxRdDqsDlyPtr, ///< Check to determine change Max Rd Dqs Delay - CheckPhyFenceTraining, ///< Check to determine if we need to Phy Fence training - CheckGetMCTSysAddr, ///< Check to determine if we need to GetMCTSysAddr - CheckSendAllMRCmds, ///< Check to determine if we need to SendAllMRCmds - CheckFindPSOverideWithSocket, ///< Check to determine if we need to Find PSOveride With Socket - CheckFindPSDct, ///< Check to determine if we need to Find PSOveride With DCT - CheckODTControls, ///< Check to determine if we need to set ODT controls - CheckDummyCLRead, ///< Check to determine if an extra dummy read is required - CheckDllStdBy, ///< Check to determine if setting DLL stand by is required - CheckSlewWithMarginImprv, ///< Check to determine if setting of Slew With MarginImprv is required - CheckSlewWithoutMarginImprv, ///< Check to determine if setting of Slew Without MarginImprv is required - CheckDllSpeedUp, ///< Check to determine if setting of Dll SpeedUp is required - CheckDllRegDis, ///< Check to determine if setting of DLL Regulator Disable is required - FenceTrnBeforeDramInit, ///< Check to determine if fence training has been done before Dram init - WLSeedAdjust, ///< Check to determine if WL seed needs to be adjusted - UnifiedNbFence, ///< Check to determine if Phy fence is of Unified NB - AdjustTwr, ///< Check to determine if Twr needs to be adjusted - ChannelPDMode, ///< Check to determine if channel power down mode is the only that is supported - ForceEnMemHoleRemapping, ///< Check to determine if we need to force enabling memory hole remapping - AdjustTrdrdSD, ///< Check to determine if we need to adjust TrdrdSD - ReverseMaxRdLatTrain, ///< Check to determine if reverse (pass to fail) algorithm is supported for MaxRdLat training - SkipErrTrain, ///< Check to determine if skip error training is supported - DramSrHys, ///< Check to determine if DRAM SR hysteresis is supported - PchgPDMode, ///< Check to determine if Precharge powerdown mode is supported - EccByteTraining, ///< Check to determine if DRAM ECC Byte training - CheckDrvImpCtrl, ///< Check to determine if we need to set DrvImpCtrl - CheckDramTerm, ///< Check to determine if we need to set DramTerm - CheckDramTermDyn, ///< Check to determine if we need to set DramTermDyn - CheckQoff, ///< Check to determine if we need to set Qoff - CheckSetSameDctODTsEn, ///< Check to defermine if we need to set "ODTsEn" the same on each DCT - WLNegativeDelay, ///< Check to determine if the NB can tolerate a negtive WL delay value - SchedDlySlot1Extra, ///< Check to determine if DataTxSchedDly Slot1 equation in slowMode to subtract an extra MEMCLK - TwoStageDramInit, ///< Check to determine if we need to seperate Draminit into 2 stages. The first one processes info on all nodes. The second one does Dram Init. - ExtraPclkInMaxRdLat, ///< Check to determine if an extra PCLK is needed for MaxRdLat - CsrPhyPllPdEn, ///< Check to determine if CSR Phy PLL Powerdown is enabled or not - AdjustTrc, ///< Check to determine if we need to adjust Trc - ProgramCsrComparator, ///< Check to determine if we need to program CsrComparator with the same value as D18F2x09C_x0D0F_0[7:0]1F[RxVioLvl] - EnProcOdtAdvForUDIMM, ///< Check to determine if we need to always enable ProcOdtAdv for UDIMM - SetTDqsForx8DimmOnly, ///< Only set MR1[TDQS] for x8 DIMMs when x4 and x8 DIMMs are both present on a channel - WlRttNomFor1of3Cfg, ///< Set Rtt_Nom = Rtt_Wr in one of three DIMMs per channel configurations - PerformanceOnly, ///< Only support performance policy, does not support battery life policy - - EnumSize ///< Size of list -} NB_SUPPORTED; - -/// List for family specific functions that are supported -typedef enum { - BeforePhyFenceTraining, ///< Family specific tasks before Phy Fence Training - BeforeMemClkFreqVal, ///< hook before setting MemClkFreqVal bit - AfterMemClkFreqVal, ///< Override PllMult and PllDiv - OverridePllMult, ///< Override PllMult - OverridePllDiv, ///< Override PllDiv - BeforeMemClr, ///< Before MemClr - SendMrsCmdsPerCs, ///< Send MRS commands per CS - SetupHwTrainingEngine, ///< Setup Hardware training engine for specific training type - OverrideRcvEnSeed, ///< Override seed for hardware based RcvEn training - AddlMaxRdLatTrain, ///< Perform additional MaxRdLat training if needed - ForceAutoComp, ///< Force Auto Comp - DetectMemPllError, ///< Detect MemPll Divide by 3 bug - ReEnablePhyComp, ///< Re-Enable Phy Compensation after RcvEn Training - ExtractWLODT, ///< Extract WL ODT value thr given ODT pattern - DCTSelectSwitch, ///< Select DCT when we switch DCT - ScrubberErratum, ///< Erratum for setting scrubber rate - MR0_PPD, ///< Override MR0[PPD] - GetDdrMaxRate, ///< Interpret DdrMaxRate with Familiy-specific encoding - ExitPhyAssistedTraining, ///< Perform family specific tasks when exiting phy assisted training - AfterSaveRestore, ///< Action after save/restore execution - OverrideDataTxFifoWrDly, ///< Override DataTxFifoWrDly based on training result of WrDatDly - OverrideRcvEnSeedPassN, ///< Override seed for hardware based RcvEn training where N greater than 0 - AfterMemClkFreqChg, ///< Reprogram DIMMs' buffers after MEMCLK frequency change - AdjustTxpdll, ///< Adjust Txpdll value to encoded register value - CalcWrDqDqsEarly, ///< Calculate WrDqDqsEarly - TrainWlPerNibble, ///< Train Write Leveling per nibble - TrainWlPerNibbleAdjustWLDly, ///< Train WL per nibble and adjust the WL delay - TrainWlPerNibbleSeed, ///< Save the seed for WL nibble based training - TrainRxEnPerNibble, ///< Train Rx Enable Training per nibble - TrainRxEnAdjustDlyPerNibble, ///< Train Rx Enable Training nibble and adjust the RxEn delay - TrainRxEnGetAvgDlyPerNibble, ///< Display Rx Enable Training average nibble value for each BL - InitPerNibbleTrn, ///< Initiates Per Nibble Training. - BeforeSetCsTri, ///< Modify CS tri-state bit map. - ForceRdDqsPhaseB, ///< Force RdDqsDly to phase B - SetDqsODT, ///< Set DQS ODT - DisLowPwrDrvStr, ///< Hook to skip setting LowPowerDriveStrengthEn - AdjustRdDqsDlyOffset, ///< Adjust the bit offset of the RdDqsDly Bit Bitfield before writing and after reading - ResetRxFifoPtr, ///< Reset RxFifo pointer during Read DQS training - EnableParityAfterMemRst, ///< Enable DRAM Address Parity after memory reset. - FinalizeVDDIO, ///< Finalize VDDIO - TrainingNibbleZero, ///< Check for see Nibble zero is being trained (individually or with x8 training) - CalRdOdtTrnOnDlyLrDimm, ///< Calculate RdOdtTrnOnDly for LrDimm - SetSkewMemClk, ///< Set SkewMemClk - OverrideWLSeed, ///< Override WL seed - ForcePhyToM0, ///< Force Phy to M0 - AdjustCSIntLvLowAddr, ///< Adjust CS interleaving low address - ReleaseNbPstate, ///< Release NB P-state - InitializeRxEnSeedlessTraining, ///< Initializes RxEn Seedless Training - TrackRxEnSeedlessRdWrNoWindBLError, ///< Track Bytelane Errors resulting from No window for RxEn Seedless Training - TrackRxEnSeedlessRdWrSmallWindBLError, ///< Track Bytelane Errors resulting from Small window for RxEn Seedless Training - InitialzeRxEnSeedlessByteLaneError, ///< Initializes ByteLaneError to False for RxEn Seedless Training - InitExtMMIOAddr, ///< Initializes extended MMIO address space - MemPstateStageChange, ///< handle training when multiple memory pstate is supported - ProgramFence2RxDll, ///< program RxDll in a different register - RdDqsDlyRestartChk, ///< Check to see if we need to restart RdDqsDly - BeforeWrDatTrn, ///< Check to see if special handling is needed before WrDatDly Training - ForceLvDimmVoltage, ///< Force LVDIMM voltage to 1.5V - BfAfExcludeDimm, ///< Workaround before and after excluding dimms - AdjustWrDqsBeforeSeedScaling, ///< For some family, negative WL is compensated and WrDqs needs to be adjusted before seed scaling - OverridePrevPassRcvEnDly, ///< Check to determine if we need override PrevPassRcvEnDly - - NumberOfHooks ///< Size of list -} FAMILY_SPECIFIC_FUNC_INDEX; - -///< Entry for SPD Timing -typedef struct { - BIT_FIELD_NAME BitField; ///< Bit field name of the timing - UINT8 Min; ///< Minimum value for timing - UINT8 Max; ///< Maximum value for timing - UINT8 Bias; ///< Bias from actual value - UINT8 Ratio_x2; ///< Actual value will be multiplied by (Ratio_x2/2) -} CTENTRY; - -/// Structure for northbridge block. -typedef struct _MEM_NB_BLOCK { - MEM_DATA_STRUCT *MemPtr; ///< Point to MEM_DATA_STRUCT. - MEM_PARAMETER_STRUCT *RefPtr; ///< Point to MEM_PARAMETER_STRUCT. - DIE_STRUCT *MCTPtr; ///< point to current Node's MCT struct - DCT_STRUCT *DCTPtr; ///< point to current Node's DCT struct - DCT_STRUCT *AllDCTPtr; ///< point to all Node's DCT structs - CH_DEF_STRUCT *ChannelPtr; ///< point to current channel data - SPD_DEF_STRUCT *SPDPtr; ///< Point to SPD data for current DCT. - struct _MEM_TECH_BLOCK *TechPtr; ///< point to technology block. - struct _MEM_FEAT_BLOCK_NB *FeatPtr; ///< point to NB Specific feature block. - struct _MEM_SHARED_DATA *SharedPtr; ///< Pointer to Memory scratchpad area - SPD_DEF_STRUCT *AllNodeSPDPtr; ///< Point to SPD data for the system. - DIE_STRUCT *AllNodeMCTPtr; ///< point to all Node's MCT structs - UINT8 DimmToBeUsed; ///< Dimm to be used in recovery mode. - MEM_PS_BLOCK *PsPtr; ///< point to platform specific block - MEM_PS_BLOCK *PSBlock; ///< point to the first platform specific block on this node. - MEM_FREQ_CHANGE_PARAM *FreqChangeParam; ///< pointer to parameter of frequency change. - - PCI_ADDR PciAddr; ///< PCI address for this node - TSEFO *NBRegTable; ///< contains all bit field definitions - - UINT8 Node; ///< current node. - UINT8 Dct; ///< current DCT. - UINT8 Channel; ///< current channel. - UINT8 DctCount; ///< number of DCTs on the current NB. - UINT8 ChannelCount; ///< number of channels per DCT of the current NB. - UINT8 NodeCount; ///< number of Nodes supported - BOOLEAN Ganged; ///< mode for current MCT controller. - POS_TRN_PATTERN_TYPE PosTrnPattern; ///< specifies the pattern that should be used for position training. - BOOLEAN MemCleared; ///< memory clear flag. - UINT32 CPGInit; ///< continuous pattern generation flag. - UINT16 StartupSpeed; ///< startup speed for DDR3. - UINT16 RcvrEnDlyLimit; ///< maximum value that RcvrEnDly field can take. - UINT32 McaNbCtlReg; ///< reserve MCA reports. - UINT32 VarMtrrHiMsk; ///< variable MTRR mask for upper 32 bits. - UINT32 CsRegMsk; ///< mask for CS base register - UINT32 NBClkFreq; ///< Current NB Clock frequency - UINT8 DefDctSelIntLvAddr; ///< Default DctSelIntLvAddr - UINT8 TrainingSequenceIndex; ///< Index into the Training Sequence - RRW_SETTINGS RrwSettings; /// - -/*---------------------------------------------------------------------------- - * TYPEDEFS, STRUCTURES, ENUMS - * - *---------------------------------------------------------------------------- - */ - -/// Test patterns for DQS training -typedef enum { - TestPattern0, ///< Test pattern used in first pass of receiver enable training - TestPattern1, ///< Test pattern used in first pass of receiver enable training - TestPattern2, ///< Test pattern used in second pass of receiver enable training - TestPatternJD1B, ///< 72-bit test pattern used in position training (ganged mode) - TestPatternJD1A, ///< 72-bit test pattern used in position training - TestPatternJD256B, ///< 256-bit test pattern used in position training (ganged mode) - TestPatternJD256A, ///< 256-bit test pattern used in position training - TestPatternML, ///< Test pattern used in first pass of max latency training - TestPattern3, ///< Test pattern used in first pass of receiver enable training - TestPattern4 ///< Test pattern used in first pass of receiver enable training -} TRAIN_PATTERN; - -/*---------------------------------------------------------------------------- - * FUNCTIONS PROTOTYPE - * - *---------------------------------------------------------------------------- - */ - -VOID -MemUWriteCachelines ( - IN UINT32 Address, - IN UINT8 Pattern[], - IN UINT16 ClCount - ); - -VOID -MemUReadCachelines ( - IN UINT8 Buffer[], - IN UINT32 Address, - IN UINT16 ClCount - ); - -VOID -MemUDummyCLRead ( - IN UINT32 Address - ); - -VOID -MemUFlushPattern ( - IN UINT32 Address, - IN UINT16 ClCount - ); - - -VOID -MemUFillTrainPattern ( - IN TRAIN_PATTERN Pattern, - IN UINT8 Buffer[], - IN UINT16 Size - ); - -UINT32 -MemUSetUpperFSbase ( - IN UINT32 Address, - IN OUT MEM_DATA_STRUCT *MemPtr - ); - -VOID -MemUSetTargetWTIO ( - IN UINT32 Address, - IN OUT MEM_DATA_STRUCT *MemPtr - ); - -VOID -MemUResetTargetWTIO ( - IN OUT MEM_DATA_STRUCT *MemPtr - ); - -VOID -MemUProcIOClFlush ( - IN UINT32 Address, - IN UINT16 ClCount, - IN OUT MEM_DATA_STRUCT *MemPtr - ); - -VOID -MemUWait10ns ( - IN UINT32 Count, - IN OUT MEM_DATA_STRUCT *MemPtr - ); - -VOID -MemUGetWrLvNblErr ( - IN OUT UINT16 *ErrBitmap, - IN UINT32 TestAddr, - IN UINT16 ClCount - ); - -VOID -AlignPointerTo16Byte ( - IN OUT UINT8 **BufferPtrPtr - ); - -VOID * -FindPSOverrideEntry ( - IN PSO_TABLE *PlatformMemoryConfiguration, - IN PSO_ENTRY EntryType, - IN UINT8 SocketID, - IN UINT8 ChannelID - ); - -UINT8 -GetMaxDimmsPerChannel ( - IN PSO_TABLE *PlatformMemoryConfiguration, - IN UINT8 SocketID, - IN UINT8 ChannelID - ); - -UINT8 -GetMaxChannelsPerSocket ( - IN PSO_TABLE *PlatformMemoryConfiguration, - IN UINT8 SocketID, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -UINT8 -GetMaxCSPerChannel ( - IN PSO_TABLE *PlatformMemoryConfiguration, - IN UINT8 SocketID, - IN UINT8 ChannelID - ); - -UINT8 -GetSpdSocketIndex ( - IN PSO_TABLE *PlatformMemoryConfiguration, - IN UINT8 SocketID, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -UINT8 -GetSpdChannelIndex ( - IN PSO_TABLE *PlatformMemoryConfiguration, - IN UINT8 SocketID, - IN UINT8 ChannelID, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -UINT32 -GetVarMtrrHiMsk ( - IN CPU_LOGICAL_ID *LogicalIdPtr, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -VOID -MemUMFenceInstr ( - VOID - ); - -UINT32 -MemUnsToMemClk ( - IN MEMORY_BUS_SPEED Speed, - IN UINT32 NumberOfns - ); -#endif /* _MU_H_ */ - - diff --git a/src/vendorcode/amd/agesa/f12/errno.h b/src/vendorcode/amd/agesa/f12/errno.h deleted file mode 100644 index 40cf072cb5..0000000000 --- a/src/vendorcode/amd/agesa/f12/errno.h +++ /dev/null @@ -1,38 +0,0 @@ -/* - ***************************************************************************** - * - * Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * *************************************************************************** - * - */ - -// this dummy errno.h prevents an agesa build failure when the gcc -// cross compiler target is i386-elf. In this case, mm_malloc.h -// includes errno.h, but the gcc cross compiler does not supply it. - -extern int errno; -#define EINVAL 1 diff --git a/src/vendorcode/amd/agesa/f12/gcccar.inc b/src/vendorcode/amd/agesa/f12/gcccar.inc deleted file mode 100644 index 95dd74d6cb..0000000000 --- a/src/vendorcode/amd/agesa/f12/gcccar.inc +++ /dev/null @@ -1,1611 +0,0 @@ -/* - * Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - */ - -/****************************************************************************** -* AMD Generic Encapsulated Software Architecture -* -* $Workfile:: GccCar.inc $Revision:: 32932 $ -* -* Description: GccCar.inc - AGESA cache-as-RAM setup Include File for GCC complier -* -******************************************************************************/ - -.altmacro - -BSP_STACK_BASE_ADDR = 0x30000 /* Base address for primary cores stack */ -BSP_STACK_SIZE = 0x10000 /* 64KB for BSP core */ -CORE0_STACK_BASE_ADDR = 0x80000 /* Base address for primary cores stack */ -CORE0_STACK_SIZE = 0x4000 /* 16KB for primary cores */ -CORE1_STACK_BASE_ADDR = 0x40000 /* Base address for AP cores */ - -#ifdef __x86_64__ -CORE1_STACK_SIZE = 0x2000 /* 8KB for each AP cores */ -#else -CORE1_STACK_SIZE = 0x1000 /* 4KB for each AP cores */ -#endif - -APIC_BASE_ADDRESS = 0x0000001B - APIC_BSC = 8 /* Boot Strap Core */ - -AMD_MTRR_VARIABLE_BASE0 = 0x0200 -AMD_MTRR_VARIABLE_BASE6 = 0x020C -AMD_MTRR_FIX64k_00000 = 0x0250 -AMD_MTRR_FIX16k_80000 = 0x0258 -AMD_MTRR_FIX16k_A0000 = 0x0259 -AMD_MTRR_FIX4k_C0000 = 0x0268 -AMD_MTRR_FIX4k_C8000 = 0x0269 -AMD_MTRR_FIX4k_D0000 = 0x026A -AMD_MTRR_FIX4k_D8000 = 0x026B -AMD_MTRR_FIX4k_E0000 = 0x026C -AMD_MTRR_FIX4k_E8000 = 0x026D -AMD_MTRR_FIX4k_F0000 = 0x026E -AMD_MTRR_FIX4k_F8000 = 0x026F - -/* Reproduced from AGESA.h */ -AMD_AP_MTRR_FIX64k_00000 = 0x00000250 -AMD_AP_MTRR_FIX16k_80000 = 0x00000258 -AMD_AP_MTRR_FIX16k_A0000 = 0x00000259 -AMD_AP_MTRR_FIX4k_C0000 = 0x00000268 -AMD_AP_MTRR_FIX4k_C8000 = 0x00000269 -AMD_AP_MTRR_FIX4k_D0000 = 0x0000026A -AMD_AP_MTRR_FIX4k_D8000 = 0x0000026B -AMD_AP_MTRR_FIX4k_E0000 = 0x0000026C -AMD_AP_MTRR_FIX4k_E8000 = 0x0000026D -AMD_AP_MTRR_FIX4k_F0000 = 0x0000026E -AMD_AP_MTRR_FIX4k_F8000 = 0x0000026F -CPU_LIST_TERMINAL = 0xFFFFFFFF - -AMD_MTRR_DEFTYPE = 0x02FF - WB_DRAM_TYPE = 0x1E /* MemType - memory type */ - MTRR_DEF_TYPE_EN = 11 /* MtrrDefTypeEn - variable and fixed MTRRs default enabled */ - MTRR_DEF_TYPE_FIX_EN = 10 /* MtrrDefTypeEn - fixed MTRRs default enabled */ - -HWCR = 0x0C0010015 /* Hardware Configuration */ - INVD_WBINVD = 0x04 /* INVD to WBINVD conversion */ - -IORR_BASE = 0x0C0010016 /* IO Range Regusters Base/Mask, 2 pairs */ - /* uses 16h - 19h */ -TOP_MEM = 0x0C001001A /* Top of Memory */ -TOP_MEM2 = 0x0C001001D /* Top of Memory2 */ - -LS_CFG = 0x0C0011020 /* Load-Store Configuration */ - DIS_SS = 28 /* Family 10h,12h,15h:Disable Streng Store functionality */ - DIS_STREAM_ST = 28 /* Family 14h:DisStreamSt - Disable Streaming Store functionality */ - -IC_CFG = 0x0C0011021 /* Instruction Cache Config Register */ - IC_DIS_SPEC_TLB_RLD = 9 /* Disable speculative TLB reloads */ - DIS_IND = 14 /* Family 10-14h:Disable Indirect Branch Predictor */ - DIS_I_CACHE = 14 /* Family 15h:DisICache - Disable Indirect Branch Predictor */ - -DC_CFG = 0x0C0011022 /* Data Cache Configuration */ - DC_DIS_SPEC_TLB_RLD = 4 /* Disable speculative TLB reloads */ - DIS_CLR_WBTOL2_SMC_HIT = 8 /* self modifying code check buffer bit */ - DIS_HW_PF = 13 /* Hardware prefetches bit */ - -DE_CFG = 0x0C0011029 /* Decode Configuration */ - CL_FLUSH_SERIALIZE = 23 /* Family 12h,15h: CL Flush Serialization */ - -BU_CFG2 = 0x0C001102A /* Family 10h: Bus Unit Configuration 2 */ -CU_CFG2 = 0x0C001102A /* Family 15h: Combined Unit Configuration 2 */ - F10_CL_LINES_TO_NB_DIS = 15 /* ClLinesToNbDis - allows WP code to be cached in L2 */ - IC_DIS_SPEC_TLB_WR = 35 /* IcDisSpecTlbWr - ITLB speculative writes */ - -CU_CFG3 = 0x0C001102B /* Combined Unit Configuration 3 */ - COMBINE_CR0_CD = 49 /* Combine CR0.CD for both cores of a compute unit */ - - -CR0_PE = 0 # Protection Enable -CR0_NW = 29 # Not Write-through -CR0_CD = 30 # Cache Disable -CR0_PG = 31 # Paging Enable - -/* CPUID Functions */ - -CPUID_MODEL = 1 -AMD_CPUID_FMF = 0x80000001 /* Family Model Features information */ -AMD_CPUID_APIC = 0x80000008 /* Long Mode and APIC info., core count */ - -NB_CFG = 0x0C001001F /* Northbridge Configuration Register */ - INIT_APIC_ID_CPU_ID_LO = 54 /* InitApicIdCpuIdLo - is core# in high or low half of APIC ID? */ - -MTRR_SYS_CFG = 0x0C0010010 /* System Configuration Register */ - CHX_TO_DIRTY_DIS = 16 /* ChxToDirtyDis Change to dirty disable */ - SYS_UC_LOCK_EN = 17 /* SysUcLockEn System lock command enable */ - MTRR_FIX_DRAM_EN = 18 /* MtrrFixDramEn MTRR fixed RdDram and WrDram attributes enable */ - MTRR_FIX_DRAM_MOD_EN = 19 /* MtrrFixDramModEn MTRR fixed RdDram and WrDram modification enable */ - MTRR_VAR_DRAM_EN = 20 /* MtrrVarDramEn MTRR variable DRAM enable */ - MTRR_TOM2_EN = 21 /* MtrrTom2En MTRR top of memory 2 enable */ - -PERF_CONTROL3 = 0x0C0010003 /* Performance event control three */ - PERF_CONTROL3_RESERVE_L = 0x00200000 /* Preserve the reserved bits */ - PERF_CONTROL3_RESERVE_H = 0x0FCF0 /* Preserve the reserved bits */ - CONFIG_EVENT_L = 0x0F0E2 /* All cores with level detection */ - CONFIG_EVENT_H = 4 /* Increment count by number of event */ - /* occured in clock cycle */ - EVENT_ENABLE = 22 /* Enable the event */ -PERF_COUNTER3 = 0x0C0010007 /* Performance event counter three */ - -# Local use flags, in upper most byte if ESI -FLAG_UNKNOWN_FAMILY = 24 # Signals that the family# of the installed processor is not recognized -FLAG_STACK_REENTRY = 25 # Signals that the environment has made a re-entry (2nd) call to set up the stack -FLAG_IS_PRIMARY = 26 # Signals that this core is the primary within the comoute unit - -CR0_MASK = ((1 << CR0_CD) | (1 << CR0_NW)) -MSR_MASK = ((1 << MTRR_DEF_TYPE_EN)+(1 << MTRR_DEF_TYPE_FIX_EN)) - -/**************************************************************************** - * - * CPU MACROS - PUBLIC - * - ****************************************************************************/ -.macro _WRMSR - .byte 0x0f, 0x30 -.endm - -.macro _RDMSR - .byte 0x0F, 0x32 -.endm - -.macro AMD_CPUID arg0 - .ifb \arg0 - mov $0x1, %eax - .byte 0x0F, 0x0A2 /* Execute instruction */ - bswap %eax - xchg %ah, %al /* Ext model in al now */ - rol $0x08, %eax /* Ext model in ah, model in al */ - and $0x0FFCF, ax /* Keep 23:16, 7:6, 3:0 */ - .else - mov \arg0, %eax - .byte 0x0F, 0x0A2 - .endif -.endm - -/**************************************************************************** -* -* AMD_ENABLE_STACK_FAMILY_HOOK Macro - Stackless -* -* Set any family specific controls needed to enable the use of -* cache as general storage before main memory is available. -* -* Inputs: -* none -* Outputs: -* none - ****************************************************************************/ -.macro AMD_ENABLE_STACK_FAMILY_HOOK - - AMD_ENABLE_STACK_FAMILY_HOOK_F10 - AMD_ENABLE_STACK_FAMILY_HOOK_F12 - AMD_ENABLE_STACK_FAMILY_HOOK_F14 - AMD_ENABLE_STACK_FAMILY_HOOK_F15 -.endm - -/**************************************************************************** -* -* AMD_DISABLE_STACK_FAMILY_HOOK Macro - Stackless -* -* Return any family specific controls to their 'standard' -* settings for using cache with main memory. -* -* Inputs: -* none -* Outputs: -* none - ****************************************************************************/ -.macro AMD_DISABLE_STACK_FAMILY_HOOK - - AMD_DISABLE_STACK_FAMILY_HOOK_F10 - AMD_DISABLE_STACK_FAMILY_HOOK_F12 - AMD_DISABLE_STACK_FAMILY_HOOK_F14 - AMD_DISABLE_STACK_FAMILY_HOOK_F15 - -.endm - -/**************************************************************************** -* -* GET_NODE_ID_CORE_ID Macro - Stackless -* -* Read family specific values to determine the node and core -* numbers for the core executing this code. -* -* Inputs: -* none -* Outputs: -* SI[7:0] = Core# (0..N, relative to node) -* SI[15:8]= Node# (0..N) -* SI[23:16]= reserved -* SI[24]= flag: 1=Family Unrecognized -* SI[25]= flag: 1=Interface re-entry call -* SI[26]= flag: 1=Core is primary of compute unit -* SI[31:27]= reserved, =0 -****************************************************************************/ -.macro GET_NODE_ID_CORE_ID - LOCAL node_core_exit - - mov $-1, %si - GET_NODE_ID_CORE_ID_F10 - GET_NODE_ID_CORE_ID_F12 - GET_NODE_ID_CORE_ID_F14 - GET_NODE_ID_CORE_ID_F15 - /* - * Check for unrecognized Family - */ - cmp $-1, %si # Has family (node/core) already been discovered? - jnz node_core_exit # Br if yes - - mov $((1 << FLAG_UNKNOWN_FAMILY)+(1 << FLAG_IS_PRIMARY)), %esi # No, Set error code, Only let BSP continue - - mov $APIC_BASE_ADDRESS, %ecx # MSR:0000_001B - _RDMSR - bt $APIC_BSC, %eax # Is this the BSC? - jc node_core_exit # Br if yes - hlt # Kill APs -node_core_exit: - -.endm - -/**************************************************************************** -## Family 10h MACROS -##*************************************************************************** -#--------------------------------------------------- -# -# AMD_ENABLE_STACK_FAMILY_HOOK_F10 Macro - Stackless -# -# Set any family specific controls needed to enable the use of -# cache as general storage before main memory is available. -# -# Inputs: -# ESI - node#, core#, flags from GET_NODE_ID_CORE_ID -# Outputs: -# none -# -# Family 10h requirements (BKDG section 2.3.3): -# * Paging disabled -# * MSRC001_0015[INVDWBINVD]=0 -# * MSRC001_1021[DIS_IND]=1 -# * MSRC001_1021[DIS_SPEC_TLB_RLD]=1 -# * MSRC001_1022[DIS_SPEC_TLB_RLD]=1 -# * MSRC001_1022[DIS_CLR_WBTOL2_SMC_HIT]=1 -# * MSRC001_1022[DIS_HW_PF]=1 -# * MSRC001_102A[IcDisSpecTlbWr]=1 -# * MSRC001_102A[ClLinesToNbDis]=1 -# * No INVD or WBINVD, no exceptions, page faults or interrupts -****************************************************************************/ -.macro AMD_ENABLE_STACK_FAMILY_HOOK_F10 - LOCAL fam10_enable_stack_hook_exit - - AMD_CPUID $CPUID_MODEL - shr $20, %eax # AL = cpu extended family - cmp $0x01, %al # Is this family 10h? - jnz fam10_enable_stack_hook_exit # Br if no - - mov $DC_CFG, %ecx # MSR:C001_1022 - _RDMSR - bts $DC_DIS_SPEC_TLB_RLD, %eax # Turn on Disable speculative DTLB reloads bit - bts $DIS_CLR_WBTOL2_SMC_HIT, %eax # Turn on Disable the self modifying code check buffer bit - bts $DIS_HW_PF, %eax # Turn on Disable hardware prefetches bit - _WRMSR - - dec %cx # MSR:C001_1021 - _RDMSR - bts $IC_DIS_SPEC_TLB_RLD, %eax # Turn on Disable speculative TLB reloads bit - bts $DIS_IND, %eax # Turn on Disable indirect branch predictor - _WRMSR - - mov $BU_CFG2, %ecx # MSR C001_102A - _RDMSR - bts $F10_CL_LINES_TO_NB_DIS, %eax # Allow BIOS ROM to be cached in the IC - bts $(IC_DIS_SPEC_TLB_WR-32), %edx #Disable speculative writes to the ITLB - _WRMSR - - mov $HWCR, %ecx # MSR C001_0015 - _RDMSR - bt $FLAG_STACK_REENTRY, %esi # Check if stack has already been set - jc fam10_skipClearingBit4 - btr $INVD_WBINVD, %eax # disable INVD -> WBINVD conversion - _WRMSR - -fam10_skipClearingBit4: - mov %esi, %eax # load core# - or %al, %al # If (BSP) - jne fam10_enable_stack_hook_exit - mov $PERF_COUNTER3, %ecx # Select performance counter three - # to count number of CAR evictions - xor %eax, %eax # Initialize the lower part of the counter to zero - xor %edx, %edx # Initializa the upper part of the counter to zero - _WRMSR # Save it - mov $PERF_CONTROL3, %ecx # Select the event control three - _RDMSR # Get the current setting - and $PERF_CONTROL3_RESERVE_L, %eax # Preserve the reserved bits - or $CONFIG_EVENT_L, %eax # Set the lower part of event register to - # select CAR Corruption occurred by any cores - and $PERF_CONTROL3_RESERVE_H, %dx # Preserve the reserved bits - or $CONFIG_EVENT_H, %dx # Set the upper part of event register - _WRMSR # Save it - bts $EVENT_ENABLE, %eax # Enable it - _WRMSR # Save it - -fam10_enable_stack_hook_exit: -.endm - -/**************************************************************************** -* -* AMD_DISABLE_STACK_FAMILY_HOOK_F10 Macro - Stackless -* -* Return any family specific controls to their 'standard' -* settings for using cache with main memory. -* -* Inputs: -* ESI - [31:24] flags; [15,8]= Node#; [7,0]= core# -* Outputs: -* none -* -* Family 10h requirements: -* * INVD or WBINVD -* * MSRC001_0015[INVD_WBINVD]=1 -* * MSRC001_1021[DIS_IND]=0 -* * MSRC001_1021[DIS_SPEC_TLB_RLD]=0 -* * MSRC001_1022[DIS_SPEC_TLB_RLD]=0 -* * MSRC001_1022[DIS_CLR_WBTOL2_SMC_HIT]=0 -* * MSRC001_1022[DIS_HW_PF]=0 -* * MSRC001_102A[IcDisSpecTlbWr]=0 -* * MSRC001_102A[ClLinesToNbDis]=0 -*****************************************************************************/ - -.macro AMD_DISABLE_STACK_FAMILY_HOOK_F10 - LOCAL fam10_disable_stack_hook_exit - - AMD_CPUID $CPUID_MODEL - shr $20, %eax # AL = cpu extended family - cmp $0x01, %al # Is this family 10h? - jnz fam10_disable_stack_hook_exit # Br if no - - mov $DC_CFG, %ecx # MSR:C001_1022 - _RDMSR - btr $DC_DIS_SPEC_TLB_RLD, %eax # Enable speculative TLB reloads - btr $DIS_CLR_WBTOL2_SMC_HIT, %eax # Allow self modifying code check buffer - btr $DIS_HW_PF, %eax # Allow hardware prefetches - _WRMSR - - dec %cx # MSR:C001_1021 - _RDMSR - btr $DIS_IND, %eax # Turn on indirect branch predictor - btr $IC_DIS_SPEC_TLB_RLD, %eax # Turn on speculative TLB reloads - _WRMSR - - mov $BU_CFG2, %ecx # MSR:C001_102A - _RDMSR - btr $F10_CL_LINES_TO_NB_DIS, %eax # Return L3 to normal mode - btr $(IC_DIS_SPEC_TLB_WR-32), %edx #Re-enable speculative writes to the ITLB - _WRMSR - - #-------------------------------------------------------------------------- - # Begin critical sequence in which EAX, BX, ECX, and EDX must be preserved. - #-------------------------------------------------------------------------- - - mov $HWCR, %ecx # MSR:0000_0015 - _RDMSR - mov %ax, %bx # Save INVD -> WBINVD bit - btr $INVD_WBINVD, %eax # Disable INVD -> WBINVD conversion for the invd instruction. - _WRMSR - invd # Clear the cache tag RAMs - mov %bx, %ax # Restore INVD -> WBINVD bit - _WRMSR - - #-------------------------------------------------------------------------- - # End critical sequence in which EAX, BX, ECX, and EDX must be preserved. - #-------------------------------------------------------------------------- - - mov $PERF_CONTROL3, %ecx # Select the event control three - _RDMSR # Retrieve the current value - btc $EVENT_ENABLE, %eax # Is event enable, complement it as well - jnc fam10_disable_stack_hook_exit # No - cmp $CONFIG_EVENT_L, %ax # Is the lower part of event set to capture the CAR Corruption - jne fam10_disable_stack_hook_exit # No - cmp $CONFIG_EVENT_H, %dl # Is the upper part of event set to capture the CAR Corruption - jne fam10_disable_stack_hook_exit # No - _WRMSR # Disable the event - -fam10_disable_stack_hook_exit: -.endm - -/**************************************************************************** -* -* GET_NODE_ID_CORE_ID_F10 Macro - Stackless -* -* Read family specific values to determine the node and core -* numbers for the core executing this code. -* -* Inputs: -* none -* Outputs: -* SI = core#, node# & flags (see GET_NODE_ID_CORE_ID macro above) -*****************************************************************************/ -.macro GET_NODE_ID_CORE_ID_F10 - - LOCAL node_core_f10_exit - LOCAL node_core_f10_AP - - cmp $-1, %si # Has node/core already been discovered? - jnz node_core_f10_exit # Br if yes - - AMD_CPUID $CPUID_MODEL - shr $20, %eax # AL = cpu extended family - cmp $0x01, %al # Is this family 10h? - jnz node_core_f10_exit # Br if no - - xor %esi, %esi # Assume BSC, clear flags - mov $APIC_BASE_ADDRESS, %ecx # MSR:0000_001B - _RDMSR - bt $APIC_BSC, %eax # Is this the BSC? - jnc node_core_f10_AP # Br if no - - # This is the BSP. - # Enable routing tables on BSP (just in case the HT init code has not yet enabled them) - mov $0x8000C06C, %eax # PCI address for D18F0x6C Link Initialization Control Register - mov $0x0CF8, %dx - out %eax, %dx - add $4, %dx - in %dx, %eax - btr $0, %eax # Set LinkInitializationControl[RouteTblDis] = 0 - out %eax, %dx - jmp 1f # - -node_core_f10_AP: - # - # This is an AP. Routing tables have been enabled by the HT Init process. - # Also, the MailBox register was set by the BSP during early init - # The Mailbox register content is formatted as follows: - # UINT32 Node:4# // The node id of Core's node. - # UINT32 Socket:4# // The socket of this Core's node. - # UINT32 Module:2# // The internal module number for Core's node. - # UINT32 ModuleType:2# // Single Module = 0, Multi-module = 1. - # UINT32 :20# // Reserved - # - mov $0x0C0000408, %ecx # Read the family 10h mailbox - _RDMSR # MC4_MISC1[63:32] - mov %dx, %si # SI = raw mailbox contents (will extract node# from this) - shr $24, %ebx # BL = CPUID Fn0000_0001_EBX[LocalApicId] - mov %bx, %di # DI = Initial APIC ID (will extract core# from this) - - AMD_CPUID $AMD_CPUID_APIC # - shr $4, %ch # CH = ApicIdSize, #bits in APIC ID that show core# - inc %cl # CL = Number of enabled cores in the socket - mov %cx, %bx - - mov $NB_CFG, %ecx # MSR:C001_001F - _RDMSR # EDX has InitApicIdCpuIdLo bit - - mov %bh, %cl # CL = APIC ID size - mov $1, %al # Convert APIC ID size to an AND mask - shl %cl, %al # AL = 2^APIC ID size - dec %al # AL = mask for relative core number - xor %ah, %ah # AX = mask for relative core number - bt $(INIT_APIC_ID_CPU_ID_LO-32), %edx # InitApicIdCpuIdLo == 1? - #.if (!carry?) # Br if yes - jc 0f - mov $8, %ch # Calculate core number shift count - sub %cl, %ch # CH = core shift count - mov %ch, %cl - shr %cl, %di # Right justify core number - #.endif - 0: - and %ax, %di # DI = socket-relative core number - - mov %si, %cx # CX = raw mailbox value - shr $10, %cx # CL[1:0] = ModuleType or #nodes per socket (0-SCM, 1-MCM) - and $3, %cl # Isolate ModuleType - xor %bh, %bh # BX = Number of enabled cores in the socket - shr %cl, %bx # BX = Number of enabled cores per node - xor %dx, %dx # Clear upper word for div - mov %di, %ax # AX = socket-relative core number - div %bx # DX = node-relative core number - movzx %si, %eax # prepare return value, [23:16]=shared Core# (=0, not shared) - and $0x000F, %ax # AX = node number - shl $8, %ax # [15:8]=node# - mov %dl, %al # [7:0]=core# (relative to node) - mov %eax, %esi # ESI = return value -1: - bts $FLAG_IS_PRIMARY, %esi # all Family 10h cores are primary -node_core_f10_exit: -.endm - - -/***************************************************************************** -** Family 12h MACROS -*****************************************************************************/ -/***************************************************************************** -* -* AMD_ENABLE_STACK_FAMILY_HOOK_F12 Macro - Stackless -* -* Set any family specific controls needed to enable the use of -* cache as general storage before main memory is available. -* -* Inputs: -* ESI - node#, core#, flags from GET_NODE_ID_CORE_ID -* Outputs: -* none -* -* Family 12h requirements (BKDG section 2.3.3): -* The following requirements must be satisfied prior to using the cache as general storage: -* * Paging must be disabled. -* * MSRC001_0015[INVD_WBINVD]=0 -* * MSRC001_1020[DIS_SS]=1 -* * MSRC001_1021[DIS_SPEC_TLB_RLD]=1 -* * MSRC001_1022[DIS_SPEC_TLB_RLD]=1 -* * MSRC001_1022[DIS_CLR_WBTOL2_SMC_HIT]=1 -* * MSRC001_1022[DIS_HW_PF]=1 -* * MSRC001_1029[ClflushSerialize]=1 -* * No INVD or WBINVD, no exceptions, page faults or interrupts -*****************************************************************************/ -.macro AMD_ENABLE_STACK_FAMILY_HOOK_F12 - LOCAL fam12_enable_stack_hook_exit - - AMD_CPUID $CPUID_MODEL - shr $20, %eax # AL = cpu extended family - cmp $0x03, %al # Is this family 12h? - jnz fam12_enable_stack_hook_exit # Br if no - - mov $DC_CFG, %ecx # MSR:C001_1022 - _RDMSR - bts $DC_DIS_SPEC_TLB_RLD, %eax # Disable speculative DC-TLB reloads - bts $DIS_CLR_WBTOL2_SMC_HIT, %eax # Disable self modifying code check buffer - bts $DIS_HW_PF, %eax # Disable hardware prefetches - _WRMSR - - dec %cx #IC_CFG # MSR:C001_1021 - _RDMSR - bts $IC_DIS_SPEC_TLB_RLD, %eax # Disable speculative IC-TLB reloads - _WRMSR - - dec %cx #LS_CFG # MSR:C001_1020 - _RDMSR - bts $DIS_SS, %eax # Disabled Streaming store functionality - _WRMSR - - mov $HWCR, %ecx # MSR C001_0015 - _RDMSR - bt $FLAG_STACK_REENTRY , %esi # Check if stack has already been set - jc fam12_skipClearingBit4 - btr $INVD_WBINVD, %eax # disable INVD -> WBINVD conversion - _WRMSR - -fam12_skipClearingBit4: - mov $DE_CFG, %ecx # MSR:C001_1029 - _RDMSR - bts $CL_FLUSH_SERIALIZE, %eax # Serialize all CL Flush actions - _WRMSR - -fam12_enable_stack_hook_exit: -.endm - -/***************************************************************************** -* -* AMD_DISABLE_STACK_FAMILY_HOOK_F12 Macro - Stackless -* -* Return any family specific controls to their 'standard' -* settings for using cache with main memory. -* -* Inputs: -* ESI - [31:24] flags; [15,8]= Node#; [7,0]= core# -* Outputs: -* none -* -* Family 12h requirements: -* * INVD or WBINVD -* * MSRC001_0015[INVD_WBINVD]=1 -* * MSRC001_1020[DIS_SS]=0 -* * MSRC001_1021[IC_DIS_SPEC_TLB_RLD]=0 -* * MSRC001_1022[DC_DIS_SPEC_TLB_RLD]=0 -* * MSRC001_1022[DIS_CLR_WBTOL2_SMC_HIT]=0 -* * MSRC001_1022[DIS_HW_PF]=0 -* * MSRC001_1029[ClflushSerialize]=0 -*****************************************************************************/ -.macro AMD_DISABLE_STACK_FAMILY_HOOK_F12 - LOCAL fam12_disable_stack_hook_exit - - AMD_CPUID $CPUID_MODEL - shr $20, %eax # AL = cpu extended family - cmp $0x03, %al # Is this family 12h? - jnz fam12_disable_stack_hook_exit # Br if no - - mov $DC_CFG, %ecx # MSR:C001_1022 - _RDMSR - btr $DC_DIS_SPEC_TLB_RLD, %eax # Turn on speculative DC-TLB reloads - btr $DIS_CLR_WBTOL2_SMC_HIT, %eax # Enable self modifying code check buffer - btr $DIS_HW_PF, %eax # Enable Hardware prefetches - _WRMSR - - dec %cx #IC_CFG # MSR:C001_1021 - _RDMSR - btr $IC_DIS_SPEC_TLB_RLD, %eax # Turn on speculative IC-TLB reloads - _WRMSR - - dec %cx #LS_CFG # MSR:C001_1020 - _RDMSR - btr $DIS_SS, %eax # Turn on Streaming store functionality - _WRMSR - - mov $DE_CFG, %ecx # MSR:C001_1029 - _RDMSR - btr $CL_FLUSH_SERIALIZE, %eax - _WRMSR - - #-------------------------------------------------------------------------- - # Begin critical sequence in which EAX, BX, ECX, and EDX must be preserved. - #-------------------------------------------------------------------------- - - mov $HWCR, %ecx # MSR:0000_0015h - _RDMSR - mov %ax, %bx # Save INVD -> WBINVD bit - btr $INVD_WBINVD, %eax # Disable INVD -> WBINVD conversion - _WRMSR - invd # Clear the cache tag RAMs - mov %bx, %ax # Restore INVD -> WBINVD bit - _WRMSR - - #-------------------------------------------------------------------------- - # End critical sequence in which EAX, BX, ECX, and EDX must be preserved. - #-------------------------------------------------------------------------- - -fam12_disable_stack_hook_exit: -.endm - -/***************************************************************************** -* -* GET_NODE_ID_CORE_ID_F12 Macro - Stackless -* -* Read family specific values to determine the node and core -* numbers for the core executing this code. -* -* Inputs: -* none -* Outputs: -* SI = core#, node# & flags (see GET_NODE_ID_CORE_ID macro above) -*****************************************************************************/ -.macro GET_NODE_ID_CORE_ID_F12 - - LOCAL node_core_f12_exit - - cmp $-1, %si # Has node/core already been discovered? - jnz node_core_f12_exit # Br if yes - - AMD_CPUID $CPUID_MODEL - shr $20, %eax # AL = cpu extended family - cmp $0x03, %al # Is this family 12h? - jnz node_core_f12_exit # Br if no - - shr $24, %ebx # CPUID_0000_0001_EBX[31:24]: initial local APIC physical ID - bts $FLAG_IS_PRIMARY, %ebx # all family 12h cores are primary - mov %ebx, %esi # ESI = Node#=0, core number -node_core_f12_exit: -.endm - -/***************************************************************************** -** Family 14h MACROS -*****************************************************************************/ -/***************************************************************************** -* -* AMD_ENABLE_STACK_FAMILY_HOOK_F14 Macro - Stackless -* -* Set any family specific controls needed to enable the use of -* cache as general storage before main memory is available. -* -* Inputs: -* ESI - node#, core#, flags from GET_NODE_ID_CORE_ID -* Outputs: -* none -* -* Family 14h requirements (BKDG section 2.3.3): -* * Paging must be disabled. -* * MSRC001_0015[INVD_WBINVD]=0. -* * MSRC001_1020[DisStreamSt]=1. -* * MSRC001_1021[DIS_SPEC_TLB_RLD]=1. Disable speculative ITLB reloads. -* * MSRC001_1022[DIS_HW_PF]=1. -* * No INVD or WBINVD, no exceptions, page faults or interrupts -*****************************************************************************/ -.macro AMD_ENABLE_STACK_FAMILY_HOOK_F14 - LOCAL fam14_enable_stack_hook_exit - - AMD_CPUID $CPUID_MODEL - shr $20, %eax # AL = cpu extended family - cmp $0x05, %al # Is this family 14h? - jnz fam14_enable_stack_hook_exit # Br if no - - mov $DC_CFG, %ecx # MSR:C001_1022 - _RDMSR - bts $DIS_HW_PF, %eax # Disable hardware prefetches - _WRMSR - - dec %cx #IC_CFG # MSR:C001_1021 - _RDMSR - bts $IC_DIS_SPEC_TLB_RLD, %eax # Disable speculative TLB reloads - _WRMSR - - dec %cx #LS_CFG # MSR:C001_1020 - _RDMSR - bts $DIS_STREAM_ST, %eax # Disabled Streaming store functionality - _WRMSR - - mov $HWCR, %ecx # MSR C001_0015 - _RDMSR - bt $FLAG_STACK_REENTRY, %esi # Check if stack has already been set - jc fam14_skipClearingBit4 - btr $INVD_WBINVD, %eax # Disable INVD -> WBINVD conversion - _WRMSR -fam14_skipClearingBit4: # Keeping this label - -fam14_enable_stack_hook_exit: -.endm - -/***************************************************************************** -* -* AMD_DISABLE_STACK_FAMILY_HOOK_F14 Macro - Stackless -* -* Return any family specific controls to their 'standard' -* settings for using cache with main memory. -* -* Inputs: -* ESI - [31:24] flags; [15,8]= Node#; [7,0]= core# -* Outputs: -* none -* -* Family 14h requirements: -* * INVD or WBINVD -* * MSRC001_0015[INVD_WBINVD]=1. -* * MSRC001_1020[DisStreamSt]=0. -* * MSRC001_1021[DIS_SPEC_TLB_RLD]=0. -* * MSRC001_1022[DIS_HW_PF]=0. -*****************************************************************************/ -.macro AMD_DISABLE_STACK_FAMILY_HOOK_F14 - LOCAL fam14_disable_stack_hook_exit - - AMD_CPUID $CPUID_MODEL - shr $20, %eax # AL = cpu extended family - cmp $0x05, %al # Is this family 14h? - jnz fam14_disable_stack_hook_exit # Br if no - - mov $LS_CFG, %ecx # MSR:C001_1020 - _RDMSR - btr $DIS_STREAM_ST, %eax # Turn on Streaming store functionality - _WRMSR - - inc %cx #IC_CFG # MSR:C001_1021 - _RDMSR - btr $IC_DIS_SPEC_TLB_RLD, %eax # Turn on speculative DC-TLB reloads - _WRMSR - - inc %cx #DC_CFG # MSR:C001_1022 - _RDMSR - btr $DIS_HW_PF, %eax # Turn on hardware prefetches - _WRMSR - - #-------------------------------------------------------------------------- - # Begin critical sequence in which EAX, BX, ECX, and EDX must be preserved. - #-------------------------------------------------------------------------- - - mov $HWCR, %ecx # MSR:C001_0015h - _RDMSR - btr $INVD_WBINVD, %eax # Disable INVD -> WBINVD conversion - _WRMSR - invd # Clear the cache tag RAMs - bts $INVD_WBINVD, %eax # Turn on Conversion of INVD to WBINVD - _WRMSR - - #-------------------------------------------------------------------------- - # End critical sequence in which EAX, BX, ECX, and EDX must be preserved. - #-------------------------------------------------------------------------- - -fam14_disable_stack_hook_exit: -.endm - -/***************************************************************************** -* -* GET_NODE_ID_CORE_ID_F14 Macro - Stackless -* -* Read family specific values to determine the node and core -* numbers for the core executing this code. -* -* Inputs: -* none -* Outputs: -* SI = core#, node# & flags (see GET_NODE_ID_CORE_ID macro above) -*****************************************************************************/ -.macro GET_NODE_ID_CORE_ID_F14 - - LOCAL node_core_f14_exit - - cmp $-1, %si # Has node/core already been discovered? - jnz node_core_f14_exit # Br if yes - - AMD_CPUID $CPUID_MODEL - shr $20, %eax # AL = cpu extended family - cmp $0x05, %al # Is this family 14h? - jnz node_core_f14_exit # Br if no - - xor %esi, %esi # Node must be 0 - bts $FLAG_IS_PRIMARY, %esi # all family 14h cores are primary - mov $APIC_BASE_ADDRESS, %ecx # MSR:0000_001B - _RDMSR - bt $APIC_BSC, %eax # Is this the BSC? - jc node_core_f14_exit # Br if yes - inc %si # Set core to 1 -node_core_f14_exit: -.endm - - - -/***************************************************************************** -** Family 15h MACROS -*****************************************************************************/ -/***************************************************************************** -* -* AMD_ENABLE_STACK_FAMILY_HOOK_F15 Macro - Stackless -* -* Set any family specific controls needed to enable the use of -* cache as general storage before main memory is available. -* -* Inputs: -* ESI - node#, core#, flags from GET_NODE_ID_CORE_ID -* Outputs: -* none -* -* Family 15h requirements (BKDG #42301 section 2.3.3): -* * Paging must be disabled. -* * MSRC001_0015[INVD_WBINVD]=0 -* * MSRC001_1020[DisSS]=1 -* * MSRC001_1021[DIS_SPEC_TLB_RLD]=1 -* * MSRC001_1022[DIS_SPEC_TLB_RLD]=1 -* * MSRC001_1022[DisHwPf]=1 -* * No INVD or WBINVD, no exceptions, page faults or interrupts -*****************************************************************************/ -.macro AMD_ENABLE_STACK_FAMILY_HOOK_F15 - LOCAL fam15_enable_stack_hook_exit - - AMD_CPUID $CPUID_MODEL - shr $20, %eax # AL = cpu extended family - cmp $0x06, %al # Is this family 15h? - jnz fam15_enable_stack_hook_exit # Br if no - - bt $FLAG_STACK_REENTRY , %esi # Check if stack has already been set - jc fam15_skipClearingBit4 - mov $HWCR, %ecx # MSR C001_0015 - _RDMSR - btr $INVD_WBINVD, %eax # disable INVD -> WBINVD conversion - _WRMSR - -fam15_skipClearingBit4: - mov $LS_CFG, %ecx # MSR:C001_1020 - _RDMSR - bts $DIS_SS, %eax # Turn on Streaming store functionality disabled bit - _WRMSR - - inc %ecx #IC_CFG # MSR:C001_1021 - _RDMSR - bts $IC_DIS_SPEC_TLB_RLD, %eax # Turn on Disable speculative IC-TLB reloads bit - _WRMSR - - inc %ecx #DC_CFG # MSR:C001_1022 - _RDMSR - bts $DC_DIS_SPEC_TLB_RLD, %eax # Turn on Disable speculative DC-TLB reloads bit - bts $DIS_HW_PF, %eax # Turn on Disable hardware prefetches bit - _WRMSR - - mov $CU_CFG3, %ecx # MSR:C001_102B - _RDMSR - btr $(COMBINE_CR0_CD - 32), %edx # Clear CombineCr0Cd bit - _WRMSR - -fam15_enable_stack_hook_exit: -.endm - - -/***************************************************************************** -* -* AMD_DISABLE_STACK_FAMILY_HOOK_F15 Macro - Stackless -* -* Return any family specific controls to their 'standard' -* settings for using cache with main memory. -* -* Inputs: -* ESI - [31:24] flags; [15,8]= Node#; [7,0]= core# -* Outputs: -* none -* -* Family 15h requirements: -* * INVD or WBINVD -* * MSRC001_0015[INVD_WBINVD]=1 -* * MSRC001_1020[DisSS]=0 -* * MSRC001_1021[DIS_SPEC_TLB_RLD]=0 -* * MSRC001_1022[DIS_SPEC_TLB_RLD]=0 -* * MSRC001_1022[DIS_HW_PF]=0 -*****************************************************************************/ -.macro AMD_DISABLE_STACK_FAMILY_HOOK_F15 - LOCAL fam15_disable_stack_hook_exit - - AMD_CPUID $CPUID_MODEL - mov %eax, %ebx # Save revision info to EBX - shr $20, %eax # AL = cpu extended family - cmp $0x06, %al # Is this family 15h? - jnz fam15_disable_stack_hook_exit # Br if no - - mov $LS_CFG, %ecx # MSR:C001_1020 - #.if (ebx != 00600F00h) ; Is this rev A0? - cmp $0x00600F00, %ebx - jz 0f - _RDMSR - btr $DIS_SS, %eax # Turn on Streaming store functionality - _WRMSR - #.endif - 0: # End workaround for errata 495 and 496 - - inc %ecx #IC_CFG # MSR:C001_1021 - _RDMSR - btr $IC_DIS_SPEC_TLB_RLD, %eax # Turn on speculative TLB reloads - _WRMSR - - inc %ecx #DC_CFG # MSR:C001_1022 - _RDMSR - btr $DC_DIS_SPEC_TLB_RLD, %eax # Turn on speculative TLB reloads - #.if (ebx != 00600F00h) # Is this rev A0? - cmp $0x00600F00, %ebx - jz 0f - btr $DIS_HW_PF, %eax # Turn on hardware prefetches - #.endif # End workaround for erratum 498 - 0: - _WRMSR - #-------------------------------------------------------------------------- - # Begin critical sequence in which EAX, BX, ECX, and EDX must be preserved. - #-------------------------------------------------------------------------- - - bt $FLAG_IS_PRIMARY, %esi - #.if (carry?) # Only clear cache from primary core - jnc 0f - mov $HWCR, %ecx # MSR:C001_0015h - _RDMSR - btr $INVD_WBINVD, %eax # Disable INVD -> WBINVD conversion - _WRMSR - invd # Clear the cache tag RAMs - bts $INVD_WBINVD, %eax # Turn on Conversion of INVD to WBINVD - _WRMSR - #.endif # end - 0: - - #-------------------------------------------------------------------------- - # End critical sequence in which EAX, BX, ECX, and EDX must be preserved. - #-------------------------------------------------------------------------- - - mov $CU_CFG3, %ecx # MSR:C001_102B - _RDMSR - bts $(COMBINE_CR0_CD - 32), %edx # Set CombineCr0Cd bit - _WRMSR - -fam15_disable_stack_hook_exit: -.endm - - -/***************************************************************************** -* -* GET_NODE_ID_CORE_ID_F15 Macro - Stackless -* -* Read family specific values to determine the node and core -* numbers for the core executing this code. -* -* Inputs: -* none -* Outputs: -* SI = core#, node# & flags (see GET_NODE_ID_CORE_ID macro above) -*****************************************************************************/ -.macro GET_NODE_ID_CORE_ID_F15 - - LOCAL node_core_f15_exit - LOCAL node_core_f15_AP - LOCAL node_core_f15_shared - - cmp $-1, %si # Has node/core already been discovered? - jnz node_core_f15_exit # Br if yes - - AMD_CPUID $CPUID_MODEL - shr $20, %eax # AL = cpu extended family - cmp $06, %al # Is this family 15h? - jnz node_core_f15_exit # Br if no - - xor %esi, %esi # Assume BSC, clear local flags - mov $APIC_BASE_ADDRESS, %ecx # MSR:0000_001B - _RDMSR - bt $APIC_BSC, %eax # Is this the BSC? - jnc node_core_f15_AP # Br if no - - # This is the BSP. - # Enable routing tables on BSP (just in case the HT init code has not yet enabled them) - mov $0x8000C06C, %eax # PCI address for D18F0x6C Link Initialization Control Register - mov $0x0CF8, %dx - out %eax, %dx - add $4, %dx - in %dx, %eax - btr $0, %eax # Set LinkInitializationControl[RouteTblDis] = 0 - out %eax, %dx - jmp node_core_f15_shared # - -node_core_f15_AP: - # - # This is an AP. Routing tables have been enabled by the HT Init process. - # Also, the MailBox register was set by the BSP during early init - # The Mailbox register content is formatted as follows: - # UINT32 Node:4; // The node id of Core's node. - # UINT32 Socket:4; // The socket of this Core's node. - # UINT32 Module:2; // The internal module number for Core's node. - # UINT32 ModuleType:2; // Single Module = 0, Multi-module = 1. - # UINT32 :20; // Reserved - # - mov $0x0C0000408, %ecx # Read the family 15h mailbox - _RDMSR # MC4_MISC1[63:32] - mov %dx, %si # SI = raw mailbox contents (will extract node# from this) - shr $24, %ebx # BL = CPUID Fn0000_0001_EBX[LocalApicId] - mov %bx, %di # DI = Initial APIC ID (will extract core# from this) - - AMD_CPUID $AMD_CPUID_APIC # - shr $4, %ch # CH = ApicIdSize, #bits in APIC ID that show core# - inc %cl # CL = Number of enabled cores in the socket - mov %cx, %bx - - mov $NB_CFG, %ecx - _RDMSR # EDX has InitApicIdCpuIdLo bit - - mov %bh, %cl # CL = APIC ID size - mov $1, %al # Convert APIC ID size to an AND mask - shl %cl, %al # AL = 2^APIC ID size - dec %al # AL = mask for relative core number - xor %ah, %ah # AX = mask for relative core number - bt $(INIT_APIC_ID_CPU_ID_LO-32), %edx # InitApicIdCpuIdLo == 1? - #.if (!carry?) # Br if yes - jc 0f - mov $8, %ch # Calculate core number shift count - sub %cl, %ch # CH = core shift count - mov %ch, %cl - shr %cl, %di # Right justify core number - #.endif - 0: - and %ax, %di # DI = socket-relative core number - - mov %si, %cx # CX = raw mailbox value - shr $10, %cx # CL[1:0] = ModuleType or #nodes per socket (0-SCM, 1-MCM) - and $3, %cl # Isolate ModuleType - xor %bh, %bh # BX = Number of enabled cores in the socket - shr %cl, %bx # BX = Number of enabled cores per node - xor %dx, %dx # Clear upper word for div - mov %di, %ax # AX = socket-relative core number - div %bx # DX = node-relative core number - movzx %si, %eax # Prepare return value - and $0x000F, %ax # AX = node number - shl $8,%ax # [15:8]=node# - mov %dl, %al # [7:0]=core# (relative to node) - mov %eax, %esi # ESI = node-relative core number - - # - # determine if this core shares MTRRs - # -node_core_f15_shared: - mov $0x8000C580, %eax # Compute Unit Status - mov %si, %bx - shl $3, %bh # Move node# to PCI Dev# field - add %bh, %ah # Adjust for node number - mov $0x0CF8, %dx - out %eax, %dx - add $4, %dx - in %dx, %eax # [3:0]=Enabled# [19:16]=DualCore - - # BL is MyCore# - mov $0x06, %cx # Use CH as 'first of pair' core# - #.while (cl > 0) - jmp 0f - 8: - bt $0, %eax # Is pair enabled? - #.if (carry?) # - jnc 1f - mov $0x01, %bh # flag core as primary - bt $16, %eax # Is there a 2nd in the pair? - #.if (carry?) # - jnc 4f - #.break .if (ch == bl) # Does 1st match MyCore#? - cmp %bl, %ch - je 9f - inc %ch - xor %bh, %bh # flag core as NOT primary - #.break .if (ch == bl) # Does 2nd match MyCore#? - cmp %bl, %ch - je 9f - jmp 2f - #.else # No 2nd core - 4: - #.break .if (ch == bl) # Does 1st match MyCore#? - cmp %bl, %ch - je 9f - #.endif - 2: - inc %ch - #.endif - 1: - shr $1, %eax - dec %cl - #.endw - 0: - #.if (cl == 0) - cmp $0x0, %cl - ja 8b - 9: - or %cl, %cl - jne 1f - #Error - core# didn't match Compute Unit Status content - bts $FLAG_UNKNOWN_FAMILY, %esi - bts $FLAG_IS_PRIMARY, %esi # Set Is_Primary for unknowns - #.endif - 1: - #.if (bh != 0) # Check state of primary for the matched core - or %bh, %bh - je 2f - bts $FLAG_IS_PRIMARY, %esi # Set shared flag into return value - #.endif - 2: - -node_core_f15_exit: - -.endm - -/***************************************************************************** -* AMD_ENABLE_STACK: Setup a stack -* -* In: -* No inputs -* -* Out: -* SS:ESP - Our new private stack location -* -* EAX = AGESA_STATUS -* -* ECX = Stack size in bytes -* -* Requirements: -* * This routine presently is limited to a max of 64 processor cores -* Destroyed: -* EBX, EDX, EDI, ESI, EBP, DS, ES -* -* Description: -* Fixed MTRR address allocation to cores: -* The BSP gets 64K of stack, Core0 of each node gets 16K of stack, all other cores get 4K. -* There is a max of 1 BSP, 7 core0s and 56 other cores. -* Although each core has it's own cache storage, they share the address space. Each core must -* be assigned a private and unique address space for its stack. To support legacy systems, -* the stack needs to be within the legacy address space (1st 1Meg). Room must also be reserved -* for the other legacy elements (Interrupt vectors, BIOS ROM, video buffer, etc.) -* -* 80000h 40000h 00000h -* +----------+----------+----------+----------+----------+----------+----------+----------+ -* 64K | | | | | | | | | 64K ea -* ea +----------+----------+----------+----------+----------+----------+----------+----------+ -* | MTRR 0000_0250 MTRRfix64K_00000 | -* +----------+----------+----------+----------+----------+----------+----------+----------+ -* | 7 , 6 | 5 , 4 | 3 , 2 | 1 , 0 | 0 | | | | <-node -* |7..1,7..1 |7..1,7..1 |7..1,7..1 |7..1,7..1 | 0 | | | | <-core -* +----------+----------+----------+----------+----------+----------+----------+----------+ -* -* C0000h B0000h A0000h 90000h 80000h -* +------+------+------+------+------+------+------+------+------+------+------+------+------+------+------+------+ -*16K | | | | | | | | | | | | | | | | | -* ea +------+------+------+------+------+------+------+------+------+------+------+------+------+------+------+------+ -* | MTRR 0259 MTRRfix16K_A0000 | MTRR 0258 MTRRfix16K_80000 | -* +------+------+------+------+------+------+------+------+------+------+------+------+------+------+------+------+ -* | > Dis|play B|uffer | < | | | | | 7 | 6 | 5 | 4 | 3 | 2 | 1 | | <-node -* | > T| e m |p o r |a r y | B u |f f e |r A |r e a<| 0 | 0 | 0 | 0 | 0 | 0 | 0 | | <-core -* +------+------+------+------+------+------+------+------+------+------+------+------+------+------+------+------+ -* -* E0000h D0000h C0000h -* +--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+ -* 4K | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | 4K ea -* ea +--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+ -* | 026B MTRRfix4K_D8000 | 026A MTRRfix4K_D0000 | 0269 MTRRfix4K_C8000 | 0268 MTRRfix4K_C0000 | -* +--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+ -* | | | | | | | | | | | | | | | | | >| V| I| D| E| O| |B |I |O |S | |A |r |e |a<| -* +--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+ -* -* 100000h F0000h E0000h -* +--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+ -* | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | 4K ea -* +--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+ -* | 026F MTRRfix4K_F8000 | 026E MTRRfix4K_F0000 | 026D MTRRfix4K_E8000 | 026C MTRRfix4K_E0000 | -* +--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+ -* | >|MA|IN| B|IO|S |RA|NG|E | | | | | | |< | >|EX|TE|ND|ED| B|IO|S |ZO|NE| | | | | |< | -* +--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+ -*****************************************************************************/ -.macro AMD_ENABLE_STACK - -# These are local labels. Declared so linker doesn't cause 'redefined label' errors - LOCAL SetupStack - LOCAL Real16bMode - LOCAL Protected32Mode - LOCAL ClearTheStack - -# Note that SS:ESP will be default stack. Note that this stack -# routine will not be used after memory has been initialized. Because -# of its limited lifetime, it will not conflict with typical PCI devices. - - # get node id and core id of current executing core - GET_NODE_ID_CORE_ID # Sets ESI[23:16]=Shared core## SI[15,8]= Node## SI[7,0]= core# (relative to node) - # Note: ESI[31:24] are used for flags: Unrecognized Family, Is_Primary core, Stack already established - - # determine if stack is already enabled. We are using the DefType MSR for this determination. - # It is =0 after reset; CAR setup sets it to enable the MTRRs - mov %cr0, %eax - test $CR0_MASK, %eax # Is cache disabled? (CD & NW bits) - jnz SetupStack # Jump if yes - mov $AMD_MTRR_DEFTYPE, %ecx # MSR:0000_02FF - _RDMSR - test $MSR_MASK, %eax # Are the default types enabled? (MTRR_DEF_TYPE_EN + MTRR_DEF_TYPE_FIX_EN) - jz SetupStack # Jump if no - or $FLAG_STACK_REENTRY, %esi # Bit25, indicate stack has already been initialized - -SetupStack: - # Set node to map the first 16MB to node 0# 0000_0000 to 00FF_FFFF as DRAM - mov %esi, %ebx # Get my Node/Core info - xor %bl, %bl - shl $3, %bh # Isolate my node#, match alignment for PCI Dev# - mov $0x8000C144, %eax # D18F1x44:DRAM Base/Limit# N is Base, N+4 is Limit - add %bh, %ah - mov %eax, %ebx # Save PCI address for Base/Limit pair - - mov $0x0CF8, %dx - out %eax, %dx - add $4, %dx - xor %eax, %eax # Least Significant bit is AD24 so 0 sets mask of 00FF_FFFF (16MB) - out %eax, %dx # DRAM Limit = node0, no interleave - - mov %ebx, %eax - sub $4, %eax # Now point to the Base register - mov $0x0CF8, %dx - out %eax, %dx - add $4, %dx - mov $0x00000003, %eax # Set the read and write enable bits - out %eax, %dx # DRAM Base = 0x0000, R/W - - AMD_ENABLE_STACK_FAMILY_HOOK - - # Init CPU MSRs for our init routines - mov $MTRR_SYS_CFG, %ecx # SYS_CFG - _RDMSR - bts $MTRR_FIX_DRAM_MOD_EN, %eax # Turn on modification enable bit - _WRMSR - - mov %esi, %eax - bt $FLAG_STACK_REENTRY, %eax # Is this a 2nd entry? - #.if (!carry?) # On a re-entry, do not clear MTRRs or reset TOM; just reset the stack SS:ESP - jc 0f - bt $FLAG_IS_PRIMARY, %eax # Is this core the primary in a compute unit? - #.if (carry?) # Families using shared groups do not need to clear the MTRRs since that is done at power-on reset - # Note: Relying on MSRs to be cleared to 0's at reset for families w/shared cores - # Clear all variable and Fixed MTRRs for non-shared cores - jnc 0f - mov $AMD_MTRR_VARIABLE_BASE0, %ecx - xor %eax, %eax - xor %edx, %edx - #.while (cl != 10h) # Variable MTRRphysBase[n] and MTRRphysMask[n] - jmp 1f - 2: - _WRMSR - inc %cl - #.endw - 1: - cmp $0x10, %cl - jne 2b - mov $AMD_MTRR_FIX64k_00000, %cx # MSR:0000_0250 - _WRMSR - mov $AMD_MTRR_FIX16k_80000, %cx # MSR:0000_0258 - _WRMSR - mov $AMD_MTRR_FIX16k_A0000, %cx # MSR:0000_0259 - _WRMSR - mov $AMD_MTRR_FIX4k_C0000, %cx # Fixed 4Ks: MTRRfix4K_C0000 to MTRRfix4K_F8000 - #.while (cl != 70h) - jmp 3f - 4: - _WRMSR - inc %cl - #.endw - 3: - cmp $0x70, %cl - jne 4b - # Set TOP_MEM (C001_001A) for non-shared cores to 16M. This will be increased at heap init. - # - not strictly needed since the FixedMTRRs take presedence. - mov $(16 * 1024 * 1024), %eax - mov $TOP_MEM, %ecx # MSR:C001_001A - _WRMSR - #.endif # End Is_Primary - #.endif # End Stack_ReEntry - 0: - # Clear IORRs (C001_0016-19) and TOM2(C001_001D) for all cores - xor %eax, %eax - xor %edx, %edx - mov $IORR_BASE, %ecx # MSR:C001_0016 - 0019 - #.while (cl != 1Ah) - jmp 1f - 2: - _WRMSR - inc %cl - #.endw - 1: - cmp $0x1A, %cl - jne 2b - mov $TOP_MEM2, %ecx # MSR:C001_001D - _WRMSR - - # setup MTRRs for stacks - # A speculative read can be generated by a speculative fetch mis-aligned in a code zone - # or due to a data zone being interpreted as code. When a speculative read occurs outside a - # controlled region (intentionally used by software), it could cause an unwanted cache eviction. - # To prevent speculative reads from causing an eviction, the unused cache ranges are set - # to UC type. Only the actively used regions (stack, heap) are reflected in the MTRRs. - # Note: some core stack regions will share an MTRR since the control granularity is much - # larger than the allocated stack zone. The allocation algorithm must account for this 'extra' - # space covered by the MTRR when parseling out cache space for the various uses. In some cases - # this could reduce the amount of EXE cache available to a core. see cpuCacheInit.c - # - # Outcome of this block is that: (Note the MTRR map at the top of the file) - # ebp - start address of stack block - # ebx - [31:16] - MTRR MSR address - # - [15:8] - slot# in MTRR register - # - [7:0] - block size in #4K blocks - # review: ESI[31:24]=Flags; SI[15,8]= Node#; SI[7,0]= core# (relative to node) - # - - mov %si, %ax # Load node, core - #.if (al == 0) # Is a core 0? - or %al, %al - jne 1f - #.if (ah == 0) # Is Node 0? (BSP) - or %ah, %ah - jne 2f - # Is BSP, assign a 64K stack - mov $((AMD_MTRR_FIX64k_00000 << 16) + (3 << 8) + (BSP_STACK_SIZE >> 12)), %ebx - mov $BSP_STACK_BASE_ADDR, %ebp - jmp 0f - #.else # node 1 to 7, core0 - 2: - # Is a Core0 of secondary node, assign 16K stacks - mov $AMD_MTRR_FIX16k_80000, %bx - shl $16, %ebx # - mov %ah, %bh # Node# is used as slot# - mov $(CORE0_STACK_SIZE >> 12), %bl - mov %ah, %al # Base = (Node# * Size)# - mul %bl # - movzx %ax, %eax # - shl $12, %eax # Expand back to full byte count (* 4K) - add $CORE0_STACK_BASE_ADDR, %eax - mov %eax, %ebp - #.endif - jmp 0f - #.else #core 1 thru core 7 - 1: - # Is core 1-7 of any node, assign 4K stacks - mov $8, %al # CoreIndex = ( (Node# * 8) ... - mul %ah # - mov %si, %bx # - add %bl, %al # ... + Core#)# - - mov $AMD_MTRR_FIX64k_00000, %bx - shl $16, %ebx # - mov %al, %bh # Slot# = (CoreIndex / 16) + 4# - shr $4, %bh # - add $4, %bh # - mov $(CORE1_STACK_SIZE >> 12), %bl - - mul %bl # Base = ( (CoreIndex * Size) ... - movzx %ax, %eax # - shl $12, %eax # Expand back to full byte count (* 4K) - add $CORE1_STACK_BASE_ADDR, %eax # ... + Base_Addr)# - mov %eax, %ebp - #.endif - 0: - - # Now set the MTRR. Add this to already existing settings (don't clear any MTRR) - mov $WB_DRAM_TYPE, %edi # Load Cache type in 1st slot - mov %bh, %cl # ShiftCount = ((slot# ... - and $0x03, %cl # ... % 4) ... - shl $0x03, %cl # ... * 8)# - shl %cl, %edi # Cache type is now in correct position - ror $16, %ebx # Get the MTRR address - movzx %bx, %ecx # - rol $16, %ebx # Put slot# & size back in BX - _RDMSR # Read-modify-write the MSR - #.if (bh < 4) # Is value in lower or upper half of MSR? - cmp $4, %bh - jae 1f - or %edi, %eax # - jmp 0f - #.else - 1: # - or %edi, %edx # - #.endif # - 0: - _WRMSR # - - # Enable MTRR defaults as UC type - mov $AMD_MTRR_DEFTYPE, %ecx # MSR:0000_02FF - _RDMSR # Read-modify-write the MSR - bts $MTRR_DEF_TYPE_EN, %eax # MtrrDefTypeEn - bts $MTRR_DEF_TYPE_FIX_EN, %eax # MtrrDefTypeFixEn - _WRMSR - - # Close the modification window on the Fixed MTRRs - mov $MTRR_SYS_CFG, %ecx # MSR:0C001_0010 - _RDMSR - bts $MTRR_FIX_DRAM_EN, %eax # MtrrFixDramEn - bts $MTRR_VAR_DRAM_EN, %eax # variable MTRR enable bit - btr $MTRR_FIX_DRAM_MOD_EN, %eax # Turn off modification enable bit - _WRMSR - - # Enable caching in CR0 - mov %cr0, %eax # Enable WT/WB cache - btr $CR0_PG, %eax # Make sure paging is disabled - btr $CR0_CD, %eax # Clear CR0 NW and CD - btr $CR0_NW, %eax - mov %eax, %cr0 - - # Use the Stack Base & size to calculate SS and ESP values - # review: - # esi[31:24]=Flags; esi[15,8]= Node#; esi[7,0]= core# (relative to node) - # ebp - start address of stack block - # ebx - [31:16] - MTRR MSR address - # - [15:8] - slot# in MTRR register - # - [7:0] - block size in #4K blocks - # - mov %ebp, %esp # Initialize the stack pointer - mov %esp, %edi # Copy the stack start to edi - movzx %bl, %bx - movzx %bx, %ebx # Clear upper ebx, don't need MSR addr anymore - shl $12, %ebx # Make size full byte count (* 4K) - add %ebx, %esp # Set the Stack Pointer as full linear address - sub $4, %esp - # - # review: - # esi[31:24]=Flags; esi[15,8]= Node#; esi[7,0]= core# (relative to node) - # edi - 32b start address of stack block - # ebx - size of stack block - # esp - 32b linear stack pointer - # - - # Determine mode for SS base; - mov %cr0, %ecx # Check for 32-bit protect mode - bt $CR0_PE, %ecx # - #.if (!carry?) # PE=0 means real mode - jc Protected32Mode - mov %cs, %cx # PE=1 - cmp $0x0D000, %cx # Check for CS - jb Protected32Mode # If CS < D000, it is a selector instead of a segment - # alter SS:ESP for 16b Real Mode: -Real16bMode: - mov %edi, %eax - shr $4, %eax # Create a Real Mode segment for ss, ds, es - mov %ax, %ss - mov %ax, %ds - mov %ax, %es - shl $4, %eax - sub %eax, %edi # Adjust the clearing pointer for Seg:Offset mode - mov %ebx, %esp # Make SP an offset from SS - sub $4, %esp # - # .endif # endif - # #else - # Default is to use Protected 32b Mode - #.endif - ; -Protected32Mode: - # - # Clear The Stack - # Now that we have set the location and the MTRRs, initialize the cache by - # reading then writing to zero all of the stack area. - # review: - # ss - Stack base - # esp - stack pointer - # ebx - size of stack block - # esi[31:24]=Flags; esi[15,8]= Node#; esi[7,0]= core# (relative to node) - # edi - address of start of stack block - # - -ClearTheStack: # Stack base is in SS, stack pointer is in ESP - shr $2, %ebx # ebx = stack block size in dwords - mov %bx, %cx # - # Check our flags - Don't clear an existing stack - #.if ( !(esi & 0FF000000h)) # Check our flags - test $(1 << FLAG_STACK_REENTRY), %esi - jne 1f - cld - mov %edi, %esi - rep lodsl (%esi) # Pre-load the range - xor %eax, %eax - mov %bx, %cx - mov %edi, %esi # Preserve base for push on stack - rep stosl (%edi) # Clear the range - movl $0x0ABCDDCBA, (%esp) # Put marker in top stack dword - shl $2, %ebx # Put stack size and base - push %ebx # in top of stack - push %esi - - mov %ebx, %ecx # Return size of stack in bytes - xor %eax, %eax # eax = 0 : no error return code - jmp 0f - #.else - 1: - movzx %cx, %ecx - shl $2, %ecx # Return size of stack in bytes - mov %esi, %eax - shr $24, %eax # Keep the flags as part of the error report - or $0x40000000, %eax # eax = AGESA_WARNING (Stack has already been set up) - #.endif - 0: -.endm - -/***************************************************************************** -* AMD_DISABLE_STACK: Destroy the stack inside the cache. This routine -* should only be executed on the BSP -* -* In: -* none -* -* Out: -* none -* -* Preserved: -* ESP -* Destroyed: -* EAX, EBX, ECX, EDX, EDI, ESI -*****************************************************************************/ -.macro AMD_DISABLE_STACK - - # get node/core/flags of current executing core - GET_NODE_ID_CORE_ID # Sets ESI[15,8]= Node#; ESI[7,0]= core# (relative to node) - - # Turn on modification enable bit - mov $MTRR_SYS_CFG, %ecx # MSR:C001_0010 - _RDMSR - bts $MTRR_FIX_DRAM_MOD_EN, %eax # Enable modifications - _WRMSR - - # Set lower 640K MTRRs for Write-Back memory caching - mov $AMD_MTRR_FIX64k_00000, %ecx - mov $0x1E1E1E1E, %eax - mov %eax, %edx - _WRMSR # 0 - 512K = WB Mem - mov $AMD_MTRR_FIX16k_80000, %ecx - _WRMSR # 512K - 640K = WB Mem - - # Turn off modification enable bit - mov $MTRR_SYS_CFG, %ecx # MSR:C001_0010 - _RDMSR - btr $MTRR_FIX_DRAM_MOD_EN, %eax # Disable modification - _WRMSR - - AMD_DISABLE_STACK_FAMILY_HOOK # Re-Enable 'normal' cache operations - -.endm From ea544574d06e8a149c447b35c5e8fba96e61152a Mon Sep 17 00:00:00 2001 From: Yu-Ping Wu Date: Thu, 14 Nov 2019 11:38:44 +0800 Subject: [PATCH 0267/1242] security/vboot: Remove buffer_size from struct vboot_working_data Since buffer_size is no longer used, remove it from struct vboot_working_data. BRANCH=none BUG=chromium:1021452 TEST=emerge-kukui coreboot Change-Id: Ie770e89b4a45e0ec703d5bbb8fb6a298ce915056 Signed-off-by: Yu-Ping Wu Reviewed-on: https://review.coreboot.org/c/coreboot/+/36844 Tested-by: build bot (Jenkins) Reviewed-by: Julius Werner --- src/lib/coreboot_table.c | 9 ++++++++- src/security/vboot/common.c | 14 +++----------- src/security/vboot/misc.h | 1 - 3 files changed, 11 insertions(+), 13 deletions(-) diff --git a/src/lib/coreboot_table.c b/src/lib/coreboot_table.c index d3576e6a32..241d8e1550 100644 --- a/src/lib/coreboot_table.c +++ b/src/lib/coreboot_table.c @@ -227,7 +227,14 @@ static void lb_vboot_workbuf(struct lb_header *header) vbwb->tag = LB_TAG_VBOOT_WORKBUF; vbwb->size = sizeof(*vbwb); vbwb->range_start = (uintptr_t)wd + wd->buffer_offset; - vbwb->range_size = wd->buffer_size; + /* + * TODO(chromium:1021452): Since cbmem size of vboot workbuf is now + * always a known value, we hardcode the value of range_size here. + * Ultimately we'll want to move this to add_cbmem_pointers() below, + * but we'll have to get rid of the vboot_working_data struct first. + */ + vbwb->range_size = VB2_KERNEL_WORKBUF_RECOMMENDED_SIZE - + wd->buffer_offset; } __weak uint32_t board_id(void) { return UNDEFINED_STRAPPING_ID; } diff --git a/src/security/vboot/common.c b/src/security/vboot/common.c index 043748cbef..3f57602cb1 100644 --- a/src/security/vboot/common.c +++ b/src/security/vboot/common.c @@ -73,11 +73,11 @@ struct vb2_context *vboot_get_context(void) */ memset(wd, 0, sizeof(*wd)); wd->buffer_offset = ALIGN_UP(sizeof(*wd), 16); - wd->buffer_size = VB2_FIRMWARE_WORKBUF_RECOMMENDED_SIZE - - wd->buffer_offset; /* Initialize vb2_shared_data and friends. */ - assert(vb2api_init(vboot_get_workbuf(wd), wd->buffer_size, + assert(vb2api_init(vboot_get_workbuf(wd), + VB2_FIRMWARE_WORKBUF_RECOMMENDED_SIZE - + wd->buffer_offset, vboot_ctx_ptr) == VB2_SUCCESS); return *vboot_ctx_ptr; @@ -137,14 +137,6 @@ static void vboot_migrate_cbmem(int unused) cbmem_add(CBMEM_ID_VBOOT_WORKBUF, cbmem_size); assert(wd_cbmem != NULL); memcpy(wd_cbmem, wd_preram, sizeof(struct vboot_working_data)); - /* - * TODO(chromium:1021452): buffer_size is uint16_t and not large enough - * to hold the kernel verification workbuf size. The only code which - * reads this value is in lb_vboot_workbuf() for lb_range->range_size. - * This value being zero doesn't cause any problems, since it is never - * read downstream. Fix or deprecate vboot_working_data. - */ - wd_cbmem->buffer_size = 0; vb2api_relocate(vboot_get_workbuf(wd_cbmem), vboot_get_workbuf(wd_preram), cbmem_size - wd_cbmem->buffer_offset, diff --git a/src/security/vboot/misc.h b/src/security/vboot/misc.h index 812bbe7267..e438848635 100644 --- a/src/security/vboot/misc.h +++ b/src/security/vboot/misc.h @@ -39,7 +39,6 @@ struct vboot_working_data { struct selected_region selected_region; /* offset of the buffer from the start of this struct */ uint16_t buffer_offset; - uint16_t buffer_size; }; /* From aeb652a4a04226f467eb8e850b2096d772c6e31e Mon Sep 17 00:00:00 2001 From: Yu-Ping Wu Date: Thu, 14 Nov 2019 15:42:25 +0800 Subject: [PATCH 0268/1242] security/vboot: Remove selected_region from struct vboot_working_data Since we already have pre-RAM cache for FMAP (CB:36657), calling load_firmware() multiple times is no longer a problem. This patch replaces vboot_get_selected_region() usage with vboot_locate_firmware(), which locates the firmware by reading from the CBMEM cache. In addition, returning false from vboot_is_slot_selected() implies the recovery path was requested, i.e., vb2_shared_data.recovery_reason was set. Therefore, we simply remove the vboot_is_slot_selected() check from vboot_check_recovery_request(). BRANCH=none BUG=chromium:1021452 TEST=emerge-kukui coreboot Change-Id: I27cb1a2175beb189053fc3e44b17b60aba474bb0 Signed-off-by: Yu-Ping Wu Reviewed-on: https://review.coreboot.org/c/coreboot/+/36845 Tested-by: build bot (Jenkins) Reviewed-by: Julius Werner --- src/security/vboot/bootmode.c | 12 +++------ src/security/vboot/common.c | 42 +++++++------------------------ src/security/vboot/misc.h | 22 ++++++++-------- src/security/vboot/vboot_loader.c | 14 ++++++++--- src/security/vboot/vboot_logic.c | 26 +++---------------- 5 files changed, 39 insertions(+), 77 deletions(-) diff --git a/src/security/vboot/bootmode.c b/src/security/vboot/bootmode.c index 0cab0c8559..83baa815c7 100644 --- a/src/security/vboot/bootmode.c +++ b/src/security/vboot/bootmode.c @@ -71,9 +71,8 @@ BOOT_STATE_INIT_ENTRY(BS_DEV_INIT, BS_ON_EXIT, * VB2_RECOVERY_RO_MANUAL. * 2. Checks if recovery request is present in VBNV and returns the code read * from it. - * 3. Checks if vboot verification is done and looks up selected region - * to identify if vboot_reference library has requested recovery path. - * If yes, return the reason code from shared data. + * 3. Checks if vboot verification is done. If yes, return the reason code from + * shared data. * 4. If nothing applies, return 0 indicating no recovery request. */ int vboot_check_recovery_request(void) @@ -88,11 +87,8 @@ int vboot_check_recovery_request(void) if ((reason = get_recovery_mode_from_vbnv()) != 0) return reason; - /* - * Identify if vboot verification is already complete and no slot - * was selected i.e. recovery path was requested. - */ - if (vboot_logic_executed() && !vboot_is_slot_selected()) + /* Identify if vboot verification is already complete. */ + if (vboot_logic_executed()) return vboot_get_recovery_reason_shared_data(); return 0; diff --git a/src/security/vboot/common.c b/src/security/vboot/common.c index 3f57602cb1..bad01ff57f 100644 --- a/src/security/vboot/common.c +++ b/src/security/vboot/common.c @@ -16,6 +16,7 @@ #include #include #include +#include #include #include #include @@ -83,42 +84,17 @@ struct vb2_context *vboot_get_context(void) return *vboot_ctx_ptr; } -int vboot_get_selected_region(struct region *region) +int vboot_locate_firmware(const struct vb2_context *ctx, + struct region_device *fw) { - const struct selected_region *reg = - &vboot_get_working_data()->selected_region; + const char *name; - if (reg == NULL) - return -1; + if (vboot_is_firmware_slot_a(ctx)) + name = "FW_MAIN_A"; + else + name = "FW_MAIN_B"; - if (reg->offset == 0 && reg->size == 0) - return -1; - - region->offset = reg->offset; - region->size = reg->size; - - return 0; -} - -void vboot_set_selected_region(const struct region *region) -{ - struct selected_region *reg = - &vboot_get_working_data()->selected_region; - - assert(reg != NULL); - - reg->offset = region_offset(region); - reg->size = region_sz(region); -} - -int vboot_is_slot_selected(void) -{ - struct selected_region *reg = - &vboot_get_working_data()->selected_region; - - assert(reg != NULL); - - return reg->size > 0; + return fmap_locate_area_as_rdev(name, fw); } #if CONFIG(VBOOT_STARTS_IN_BOOTBLOCK) diff --git a/src/security/vboot/misc.h b/src/security/vboot/misc.h index e438848635..1b147992d8 100644 --- a/src/security/vboot/misc.h +++ b/src/security/vboot/misc.h @@ -23,11 +23,6 @@ struct vb2_context; struct vb2_shared_data; -struct selected_region { - uint32_t offset; - uint32_t size; -}; - /* * Stores vboot-related information. selected_region is used by verstage to * store the location of the selected slot. buffer is used by vboot to store @@ -36,7 +31,6 @@ struct selected_region { * Keep the struct CPU architecture agnostic as it crosses stage boundaries. */ struct vboot_working_data { - struct selected_region selected_region; /* offset of the buffer from the start of this struct */ uint16_t buffer_offset; }; @@ -47,11 +41,19 @@ struct vboot_working_data { struct vboot_working_data *vboot_get_working_data(void); struct vb2_context *vboot_get_context(void); -/* Returns 0 on success. < 0 on failure. */ -int vboot_get_selected_region(struct region *region); +/* + * Returns 1 if firmware slot A is used, 0 if slot B is used. + */ +static inline int vboot_is_firmware_slot_a(const struct vb2_context *ctx) +{ + return !(ctx->flags & VB2_CONTEXT_FW_SLOT_B); +} -void vboot_set_selected_region(const struct region *region); -int vboot_is_slot_selected(void); +/* + * Locates firmware as a region device. Returns 0 on success, -1 on failure. + */ +int vboot_locate_firmware(const struct vb2_context *ctx, + struct region_device *fw); /* * Source: security/vboot/vboot_handoff.c diff --git a/src/security/vboot/vboot_loader.c b/src/security/vboot/vboot_loader.c index 2b7ba83503..3903f18f6b 100644 --- a/src/security/vboot/vboot_loader.c +++ b/src/security/vboot/vboot_loader.c @@ -73,17 +73,23 @@ void vboot_run_logic(void) static int vboot_locate(struct cbfs_props *props) { - struct region selected_region; + const struct vb2_context *ctx; + struct region_device fw_main; /* Don't honor vboot results until the vboot logic has run. */ if (!vboot_logic_executed()) return -1; - if (vboot_get_selected_region(&selected_region)) + ctx = vboot_get_context(); + + if (ctx->flags & VB2_CONTEXT_RECOVERY_MODE) return -1; - props->offset = region_offset(&selected_region); - props->size = region_sz(&selected_region); + if (vboot_locate_firmware(ctx, &fw_main)) + return -1; + + props->offset = region_device_offset(&fw_main); + props->size = region_device_sz(&fw_main); return 0; } diff --git a/src/security/vboot/vboot_logic.c b/src/security/vboot/vboot_logic.c index 71371cdb75..6ee4d948f3 100644 --- a/src/security/vboot/vboot_logic.c +++ b/src/security/vboot/vboot_logic.c @@ -35,11 +35,6 @@ #define TODO_BLOCK_SIZE 1024 -static int is_slot_a(struct vb2_context *ctx) -{ - return !(ctx->flags & VB2_CONTEXT_FW_SLOT_B); -} - /* exports */ void vb2ex_printf(const char *func, const char *fmt, ...) @@ -70,7 +65,7 @@ vb2_error_t vb2ex_read_resource(struct vb2_context *ctx, name = "GBB"; break; case VB2_RES_FW_VBLOCK: - if (is_slot_a(ctx)) + if (vboot_is_firmware_slot_a(ctx)) name = "VBLOCK_A"; else name = "VBLOCK_B"; @@ -256,19 +251,6 @@ static vb2_error_t hash_body(struct vb2_context *ctx, return VB2_SUCCESS; } -static int locate_firmware(struct vb2_context *ctx, - struct region_device *fw_main) -{ - const char *name; - - if (is_slot_a(ctx)) - name = "FW_MAIN_A"; - else - name = "FW_MAIN_B"; - - return fmap_locate_area_as_rdev(name, fw_main); -} - /** * Save non-volatile and/or secure data if needed. */ @@ -417,7 +399,7 @@ void verstage_main(void) } printk(BIOS_INFO, "Phase 4\n"); - rv = locate_firmware(ctx, &fw_main); + rv = vboot_locate_firmware(ctx, &fw_main); if (rv) die_with_post_code(POST_INVALID_ROM, "Failed to read FMAP to locate firmware"); @@ -468,8 +450,8 @@ void verstage_main(void) } } - printk(BIOS_INFO, "Slot %c is selected\n", is_slot_a(ctx) ? 'A' : 'B'); - vboot_set_selected_region(region_device_region(&fw_main)); + printk(BIOS_INFO, "Slot %c is selected\n", + vboot_is_firmware_slot_a(ctx) ? 'A' : 'B'); verstage_main_exit: /* If CBMEM is not up yet, let the ROMSTAGE_CBMEM_INIT_HOOK take care From fe338e2319f40a22f1c64aef3df95e015ab8b90b Mon Sep 17 00:00:00 2001 From: Aaron Durbin Date: Mon, 18 Nov 2019 12:35:21 -0700 Subject: [PATCH 0269/1242] cbfs: switch to region_device for location APIs Drop struct cbfs_props and replace with struct region_device object. The goal of the cbfs locator APIs are to determine the correct region device to find the cbfs files. Therefore, start directly using struct region_device in the cbfs location paths. Update the users of the API and leverage the default boot region device implementation for apollolake. Change-Id: I0158a095cc64c9900d8738f8ffd45ae4040575ea Signed-off-by: Aaron Durbin Reviewed-on: https://review.coreboot.org/c/coreboot/+/36939 Tested-by: build bot (Jenkins) Reviewed-by: Julius Werner --- src/include/cbfs.h | 14 ++++++---- src/lib/cbfs.c | 40 +++++++--------------------- src/lib/coreboot_table.c | 8 +++--- src/security/vboot/vboot_loader.c | 12 +++------ src/soc/intel/apollolake/mmap_boot.c | 17 +++++------- 5 files changed, 32 insertions(+), 59 deletions(-) diff --git a/src/include/cbfs.h b/src/include/cbfs.h index 60129d3bb2..7a984b8570 100644 --- a/src/include/cbfs.h +++ b/src/include/cbfs.h @@ -73,18 +73,22 @@ struct cbfs_props { size_t size; }; -/* Default CBFS locator .locate() callback that locates "COREBOOT" region. */ -int cbfs_default_props(struct cbfs_props *props); +/* Default CBFS locator .locate() callback that locates "COREBOOT" region. This + function is exposed to reduce code duplication in other parts of the code + base. To obtain the correct region device the selection process is required + by way of cbfs_boot_region_device(). */ +int cbfs_default_region_device(struct region_device *rdev); -/* Return < 0 on error otherwise props are filled out accordingly. */ -int cbfs_boot_region_properties(struct cbfs_props *props); +/* Select the boot region device from the cbfs locators. + Return < 0 on error, 0 on success. */ +int cbfs_boot_region_device(struct region_device *rdev); /* Object used to identify location of current cbfs to use for cbfs_boot_* * operations. It's used by cbfs_boot_region_properties(). */ struct cbfs_locator { const char *name; /* Returns 0 on successful fill of cbfs properties. */ - int (*locate)(struct cbfs_props *props); + int (*locate)(struct region_device *rdev); }; #endif diff --git a/src/lib/cbfs.c b/src/lib/cbfs.c index fbe6e43496..636ff70de8 100644 --- a/src/lib/cbfs.c +++ b/src/lib/cbfs.c @@ -39,26 +39,9 @@ int cbfs_boot_locate(struct cbfsf *fh, const char *name, uint32_t *type) { struct region_device rdev; - const struct region_device *boot_dev; - struct cbfs_props props; - if (cbfs_boot_region_properties(&props)) { - printk(BIOS_ALERT, "ERROR: Failed to locate boot region\n"); + if (cbfs_boot_region_device(&rdev)) return -1; - } - - /* All boot CBFS operations are performed using the RO device. */ - boot_dev = boot_device_ro(); - - if (boot_dev == NULL) { - printk(BIOS_ALERT, "ERROR: Failed to find boot device\n"); - return -1; - } - - if (rdev_chain(&rdev, boot_dev, props.offset, props.size)) { - printk(BIOS_ALERT, "ERROR: Failed to access boot region inside boot device\n"); - return -1; - } int ret = cbfs_locate(fh, &rdev, name, type); @@ -297,17 +280,13 @@ out: } /* The default locator to find the CBFS in the "COREBOOT" FMAP region. */ -int cbfs_default_props(struct cbfs_props *props) +int cbfs_default_region_device(struct region_device *rdev) { - struct region region; - - if (fmap_locate_area("COREBOOT", ®ion)) + if (fmap_locate_area_as_rdev("COREBOOT", rdev)) return -1; - props->offset = region_offset(®ion); - props->size = region_sz(®ion); - - printk(BIOS_SPEW, "CBFS @ %zx size %zx\n", props->offset, props->size); + printk(BIOS_SPEW, "CBFS @ %zx size %zx\n", + region_device_offset(rdev), region_device_sz(rdev)); return 0; } @@ -317,7 +296,7 @@ int cbfs_default_props(struct cbfs_props *props) * devices. */ const struct cbfs_locator __weak cbfs_default_locator = { .name = "COREBOOT Locator", - .locate = cbfs_default_props, + .locate = cbfs_default_region_device, }; extern const struct cbfs_locator vboot_locator; @@ -334,7 +313,7 @@ static const struct cbfs_locator *locators[] = { &cbfs_default_locator, }; -int cbfs_boot_region_properties(struct cbfs_props *props) +int cbfs_boot_region_device(struct region_device *rdev) { int i; @@ -348,11 +327,12 @@ int cbfs_boot_region_properties(struct cbfs_props *props) if (ops->locate == NULL) continue; - if (ops->locate(props)) + if (ops->locate(rdev)) continue; LOG("'%s' located CBFS at [%zx:%zx)\n", - ops->name, props->offset, props->offset + props->size); + ops->name, region_device_offset(rdev), + region_device_end(rdev)); return 0; } diff --git a/src/lib/coreboot_table.c b/src/lib/coreboot_table.c index 241d8e1550..7245a63893 100644 --- a/src/lib/coreboot_table.c +++ b/src/lib/coreboot_table.c @@ -261,12 +261,12 @@ static void lb_board_id(struct lb_header *header) static void lb_boot_media_params(struct lb_header *header) { struct lb_boot_media_params *bmp; - struct cbfs_props props; const struct region_device *boot_dev; + struct region_device cbfs_dev; boot_device_init(); - if (cbfs_boot_region_properties(&props)) + if (cbfs_boot_region_device(&cbfs_dev)) return; boot_dev = boot_device_ro(); @@ -277,8 +277,8 @@ static void lb_boot_media_params(struct lb_header *header) bmp->tag = LB_TAG_BOOT_MEDIA_PARAMS; bmp->size = sizeof(*bmp); - bmp->cbfs_offset = props.offset; - bmp->cbfs_size = props.size; + bmp->cbfs_offset = region_device_offset(&cbfs_dev); + bmp->cbfs_size = region_device_sz(&cbfs_dev); bmp->boot_media_size = region_device_sz(boot_dev); bmp->fmap_offset = get_fmap_flash_offset(); diff --git a/src/security/vboot/vboot_loader.c b/src/security/vboot/vboot_loader.c index 3903f18f6b..3e491a7200 100644 --- a/src/security/vboot/vboot_loader.c +++ b/src/security/vboot/vboot_loader.c @@ -14,6 +14,7 @@ */ #include +#include #include #include #include @@ -71,10 +72,9 @@ void vboot_run_logic(void) } } -static int vboot_locate(struct cbfs_props *props) +static int vboot_locate(struct region_device *rdev) { const struct vb2_context *ctx; - struct region_device fw_main; /* Don't honor vboot results until the vboot logic has run. */ if (!vboot_logic_executed()) @@ -85,13 +85,7 @@ static int vboot_locate(struct cbfs_props *props) if (ctx->flags & VB2_CONTEXT_RECOVERY_MODE) return -1; - if (vboot_locate_firmware(ctx, &fw_main)) - return -1; - - props->offset = region_device_offset(&fw_main); - props->size = region_device_sz(&fw_main); - - return 0; + return vboot_locate_firmware(ctx, rdev); } const struct cbfs_locator vboot_locator = { diff --git a/src/soc/intel/apollolake/mmap_boot.c b/src/soc/intel/apollolake/mmap_boot.c index 631a834160..96ddc0560e 100644 --- a/src/soc/intel/apollolake/mmap_boot.c +++ b/src/soc/intel/apollolake/mmap_boot.c @@ -99,28 +99,23 @@ const struct region_device *boot_device_ro(void) return &real_dev.rdev; } -static int iafw_boot_region_properties(struct cbfs_props *props) +static int iafw_boot_region_device(struct region_device *rdev) { struct region *real_dev_reg; - struct region regn; - /* use fmap to locate CBFS area */ - if (fmap_locate_area("COREBOOT", ®n)) + if (cbfs_default_region_device(rdev)) return -1; - props->offset = region_offset(®n); - props->size = region_sz(®n); - /* Check that we are within the memory mapped area. It's too easy to forget the SRAM mapping when crafting an FMAP file. */ real_dev_reg = &real_dev.sub_region; - if (region_is_subregion(real_dev_reg, ®n)) { + if (region_is_subregion(real_dev_reg, region_device_region(rdev))) { printk(BIOS_DEBUG, "CBFS @ %zx size %zx\n", - props->offset, props->size); + region_device_offset(rdev), region_device_sz(rdev)); } else { printk(BIOS_CRIT, "ERROR: CBFS @ %zx size %zx exceeds mem-mapped area @ %zx size %zx\n", - props->offset, props->size, + region_device_offset(rdev), region_device_sz(rdev), region_offset(real_dev_reg), region_sz(real_dev_reg)); } @@ -133,5 +128,5 @@ static int iafw_boot_region_properties(struct cbfs_props *props) */ const struct cbfs_locator cbfs_default_locator = { .name = "IAFW Locator", - .locate = iafw_boot_region_properties, + .locate = iafw_boot_region_device, }; From d6fc557b9344cf466122ebe7bd7382e9d247c77c Mon Sep 17 00:00:00 2001 From: Tim Wawrzynczak Date: Fri, 25 Oct 2019 14:58:15 -0600 Subject: [PATCH 0270/1242] security/vboot: Add vboot callbacks to support EC software sync Use the new functions introduced into the EC driver to support performing EC software sync via vboot callbacks. NOTE: This patch assumes that the EC image is added to CBFS uncompressed. Streaming decompression of the image will be added in a future patch. Also adds a new Kconfig option VBOOT_EARLY_EC_SYNC. The new Kconfig option compiles EC software sync into romstage, dependent upon having a CrOS EC. BUG=b:112198832 BRANCH=none TEST=Successful EC software sync Change-Id: I9b1458a45ab3ed5623af50f78036c4f88461b226 Signed-off-by: Tim Wawrzynczak Reviewed-on: https://review.coreboot.org/c/coreboot/+/36208 Reviewed-by: Julius Werner Tested-by: build bot (Jenkins) --- src/security/vboot/Kconfig | 12 + src/security/vboot/Makefile.inc | 2 + src/security/vboot/ec_sync.c | 549 ++++++++++++++++++++++++++++++ src/security/vboot/vboot_common.h | 9 + src/security/vboot/vboot_logic.c | 30 +- 5 files changed, 590 insertions(+), 12 deletions(-) create mode 100644 src/security/vboot/ec_sync.c diff --git a/src/security/vboot/Kconfig b/src/security/vboot/Kconfig index 89e12323b6..df1b7e478a 100644 --- a/src/security/vboot/Kconfig +++ b/src/security/vboot/Kconfig @@ -242,6 +242,18 @@ config VBOOT_ENABLE_CBFS_FALLBACK When this option is enabled cbfs_boot_locate will look for a file in the RO (COREBOOT) region if it isn't available in the active RW region. +config VBOOT_EARLY_EC_SYNC + bool + default n + depends on EC_GOOGLE_CHROMEEC + help + Enables CrOS EC software sync in romstage, before memory training + runs. This is useful mainly as a way to achieve full USB-PD + negotiation earlier in the boot flow, as the EC will only do this once + it has made the sysjump to its RW firmware. It should not + significantly impact boot time, as this operation will be performed + later in the boot flow if it is disabled here. + menu "GBB configuration" config GBB_HWID diff --git a/src/security/vboot/Makefile.inc b/src/security/vboot/Makefile.inc index 3e5956cb10..87cd91cbf6 100644 --- a/src/security/vboot/Makefile.inc +++ b/src/security/vboot/Makefile.inc @@ -37,6 +37,8 @@ verstage-y += vbnv.c romstage-y += vbnv.c ramstage-y += vbnv.c +romstage-$(CONFIG_VBOOT_EARLY_EC_SYNC) += ec_sync.c + bootblock-$(CONFIG_VBOOT_VBNV_CMOS) += vbnv_cmos.c verstage-$(CONFIG_VBOOT_VBNV_CMOS) += vbnv_cmos.c romstage-$(CONFIG_VBOOT_VBNV_CMOS) += vbnv_cmos.c diff --git a/src/security/vboot/ec_sync.c b/src/security/vboot/ec_sync.c new file mode 100644 index 0000000000..ec048aa91c --- /dev/null +++ b/src/security/vboot/ec_sync.c @@ -0,0 +1,549 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define _EC_FILENAME(select, suffix) \ + (select == VB_SELECT_FIRMWARE_READONLY ? "ecro" suffix : "ecrw" suffix) +#define EC_IMAGE_FILENAME(select) _EC_FILENAME(select, "") +#define EC_HASH_FILENAME(select) _EC_FILENAME(select, ".hash") + +/* Wait 10 ms between attempts to check if EC's hash is ready */ +#define CROS_EC_HASH_CHECK_DELAY_MS 10 +/* Give the EC 2 seconds to finish calculating its hash */ +#define CROS_EC_HASH_TIMEOUT_MS 2000 + +/* Wait 3 seconds after software sync for EC to clear the limit power flag. */ +#define LIMIT_POWER_WAIT_TIMEOUT_MS 3000 +/* Check the limit power flag every 10 ms while waiting. */ +#define LIMIT_POWER_POLL_SLEEP_MS 10 + +/* Wait 3 seconds for EC to sysjump to RW */ +#define CROS_EC_SYSJUMP_TIMEOUT_MS 3000 + +/* + * The external API for EC software sync. This function calls into + * vboot, which kicks off the process. Vboot runs the verified boot + * logic, and requires the client program to provide callbacks which + * perform the work. + */ +void vboot_sync_ec(void) +{ + vb2_error_t retval = VB2_SUCCESS; + struct vb2_context *ctx; + + ctx = vboot_get_context(); + ctx->flags |= VB2_CONTEXT_EC_SYNC_SUPPORTED; + + retval = vb2api_ec_sync(ctx); + vboot_save_nvdata_only(ctx); + + if (retval != VB2_SUCCESS) { + printk(BIOS_ERR, "EC software sync failed (%#x), rebooting\n", retval); + vboot_reboot(); + } +} + +/* Convert firmware image type into a flash offset */ +static uint32_t get_vboot_hash_offset(enum vb2_firmware_selection select) +{ + switch (select) { + case VB_SELECT_FIRMWARE_READONLY: + return EC_VBOOT_HASH_OFFSET_RO; + case VB_SELECT_FIRMWARE_EC_UPDATE: + return EC_VBOOT_HASH_OFFSET_UPDATE; + default: + return EC_VBOOT_HASH_OFFSET_ACTIVE; + } +} + +/* + * Asks the EC to calculate a hash of the specified firmware image, and + * returns the information in **hash and *hash_size. + */ +static vb2_error_t ec_hash_image(enum vb2_firmware_selection select, + const uint8_t **hash, int *hash_size) +{ + static struct ec_response_vboot_hash resp; + uint32_t hash_offset; + int recalc_requested = 0; + struct stopwatch sw; + + hash_offset = get_vboot_hash_offset(select); + + stopwatch_init_msecs_expire(&sw, CROS_EC_HASH_TIMEOUT_MS); + do { + if (google_chromeec_get_vboot_hash(hash_offset, &resp)) + return VB2_ERROR_UNKNOWN; + + switch (resp.status) { + case EC_VBOOT_HASH_STATUS_NONE: + /* + * There is no hash available right now. + * Request a recalc if it hasn't been done yet. + */ + if (recalc_requested) + break; + + printk(BIOS_WARNING, + "%s: No valid hash (status=%d size=%d). " + "Computing...\n", __func__, resp.status, + resp.size); + + if (google_chromeec_start_vboot_hash( + EC_VBOOT_HASH_TYPE_SHA256, hash_offset, &resp)) + return VB2_ERROR_UNKNOWN; + + recalc_requested = 1; + + /* + * Expect status to be busy since we just sent + * a recalc request. + */ + resp.status = EC_VBOOT_HASH_STATUS_BUSY; + + /* Hash just started calculating, let it go for a bit */ + mdelay(CROS_EC_HASH_CHECK_DELAY_MS); + break; + + case EC_VBOOT_HASH_STATUS_BUSY: + /* Hash is still calculating. */ + mdelay(CROS_EC_HASH_CHECK_DELAY_MS); + break; + + case EC_VBOOT_HASH_STATUS_DONE: /* intentional fallthrough */ + default: + /* Hash is ready! */ + break; + } + } while (resp.status == EC_VBOOT_HASH_STATUS_BUSY && + !stopwatch_expired(&sw)); + + if (resp.status != EC_VBOOT_HASH_STATUS_DONE) { + printk(BIOS_ERR, "%s: Hash status not done: %d\n", __func__, + resp.status); + return VB2_ERROR_UNKNOWN; + } + if (resp.hash_type != EC_VBOOT_HASH_TYPE_SHA256) { + printk(BIOS_ERR, "EC hash was the wrong type.\n"); + return VB2_ERROR_UNKNOWN; + } + + printk(BIOS_INFO, "EC took %luus to calculate image hash\n", + stopwatch_duration_usecs(&sw)); + + *hash = resp.hash_digest; + *hash_size = resp.digest_size; + + return VB2_SUCCESS; +} + +/* + * Asks the EC to protect or unprotect the specified flash region. + */ +static vb2_error_t ec_protect_flash(enum vb2_firmware_selection select, int enable) +{ + struct ec_response_flash_protect resp; + uint32_t protected_region = EC_FLASH_PROTECT_ALL_NOW; + const uint32_t mask = EC_FLASH_PROTECT_ALL_NOW | EC_FLASH_PROTECT_ALL_AT_BOOT; + + if (select == VB_SELECT_FIRMWARE_READONLY) + protected_region = EC_FLASH_PROTECT_RO_NOW; + + if (google_chromeec_flash_protect(mask, enable ? mask : 0, &resp) != 0) + return VB2_ERROR_UNKNOWN; + + if (!enable) { + /* If protection is still enabled, need reboot */ + if (resp.flags & protected_region) + return VBERROR_EC_REBOOT_TO_RO_REQUIRED; + + return VB2_SUCCESS; + } + + /* + * If write protect and ro-at-boot aren't both asserted, don't expect + * protection enabled. + */ + if ((~resp.flags) & (EC_FLASH_PROTECT_GPIO_ASSERTED | + EC_FLASH_PROTECT_RO_AT_BOOT)) + return VB2_SUCCESS; + + /* If flash is protected now, success */ + if (resp.flags & EC_FLASH_PROTECT_ALL_NOW) + return VB2_SUCCESS; + + /* If RW will be protected at boot but not now, need a reboot */ + if (resp.flags & EC_FLASH_PROTECT_ALL_AT_BOOT) + return VBERROR_EC_REBOOT_TO_RO_REQUIRED; + + /* Otherwise, it's an error */ + return VB2_ERROR_UNKNOWN; +} + +/* Convert a firmware image type to an EC flash region */ +static enum ec_flash_region vboot_to_ec_region(enum vb2_firmware_selection select) +{ + switch (select) { + case VB_SELECT_FIRMWARE_READONLY: + return EC_FLASH_REGION_WP_RO; + case VB_SELECT_FIRMWARE_EC_UPDATE: + return EC_FLASH_REGION_UPDATE; + default: + return EC_FLASH_REGION_ACTIVE; + } +} + +/* + * Read the EC's burst size bytes at a time from CBFS, and then send + * the chunk to the EC for it to write into its flash. + */ +static vb2_error_t ec_flash_write(struct region_device *image_region, + uint32_t region_offset, int image_size) +{ + struct ec_response_get_protocol_info resp_proto; + struct ec_response_flash_info resp_flash; + ssize_t pdata_max_size; + ssize_t burst; + uint8_t *file_buf; + struct ec_params_flash_write *params; + uint32_t end, off; + + /* + * Get EC's protocol information, so that we can figure out how much + * data can be sent in one message. + */ + if (google_chromeec_get_protocol_info(&resp_proto)) { + printk(BIOS_ERR, "Failed to get EC protocol information; " + "skipping flash write\n"); + return VB2_ERROR_UNKNOWN; + } + + /* + * Determine burst size. This must be a multiple of the write block + * size, and must also fit into the host parameter buffer. + */ + if (google_chromeec_flash_info(&resp_flash)) { + printk(BIOS_ERR, "Failed to get EC flash information; " + "skipping flash write\n"); + return VB2_ERROR_UNKNOWN; + } + + /* Limit the potential buffer stack allocation to 1K */ + pdata_max_size = MIN(1024, resp_proto.max_request_packet_size - + sizeof(struct ec_host_request)); + + /* Round burst to a multiple of the flash write block size */ + burst = pdata_max_size - sizeof(*params); + burst = (burst / resp_flash.write_block_size) * + resp_flash.write_block_size; + + /* Buffer too small */ + if (burst <= 0) { + printk(BIOS_ERR, "Flash write buffer too small! skipping " + "flash write\n"); + return VB2_ERROR_UNKNOWN; + } + + /* Allocate buffer on the stack */ + params = alloca(burst + sizeof(*params)); + + /* Fill up the buffer */ + end = region_offset + image_size; + for (off = region_offset; off < end; off += burst) { + uint32_t todo = MIN(end - off, burst); + uint32_t xfer_size = todo + sizeof(*params); + + /* Map 'todo' bytes into memory */ + file_buf = rdev_mmap(image_region, off - region_offset, todo); + if (file_buf == NULL) + return VB2_ERROR_UNKNOWN; + + params->offset = off; + params->size = todo; + + /* Read todo bytes into the buffer */ + memcpy(params + 1, file_buf, todo); + + if (rdev_munmap(image_region, file_buf)) + return VB2_ERROR_UNKNOWN; + + /* Make sure to add back in the size of the parameters */ + if (google_chromeec_flash_write_block( + (const uint8_t *)params, xfer_size)) { + printk(BIOS_ERR, "EC failed flash write command, " + "relative offset %u!\n", off - region_offset); + return VB2_ERROR_UNKNOWN; + } + } + + return VB2_SUCCESS; +} + +/* + * The logic for updating an EC firmware image. + */ +static vb2_error_t ec_update_image(enum vb2_firmware_selection select) +{ + uint32_t region_offset, region_size; + enum ec_flash_region region; + vb2_error_t rv; + size_t image_size; + struct cbfsf fh; + const char *filename; + struct region_device image_region; + + /* Un-protect the flash region */ + rv = ec_protect_flash(select, 0); + if (rv != VB2_SUCCESS) + return rv; + + /* Convert vboot region into an EC region */ + region = vboot_to_ec_region(select); + + /* Get information about the flash region */ + if (google_chromeec_flash_region_info(region, ®ion_offset, + ®ion_size)) + return VB2_ERROR_UNKNOWN; + + /* Locate the CBFS file */ + filename = EC_IMAGE_FILENAME(select); + if (cbfs_boot_locate(&fh, filename, NULL)) + return VB2_ERROR_UNKNOWN; + + /* Get the file size and the region struct */ + image_size = region_device_sz(&fh.data); + cbfs_file_data(&image_region, &fh); + + /* Bail if the image is too large */ + if (image_size > region_size) + return VB2_ERROR_INVALID_PARAMETER; + + /* Erase the region */ + if (google_chromeec_flash_erase(region_offset, region_size)) + return VB2_ERROR_UNKNOWN; + + /* Write the image into the region */ + if (ec_flash_write(&image_region, region_offset, image_size)) + return VB2_ERROR_UNKNOWN; + + /* Verify the image */ + if (google_chromeec_efs_verify(region)) + return VB2_ERROR_UNKNOWN; + + return VB2_SUCCESS; +} + +static vb2_error_t ec_get_expected_hash(enum vb2_firmware_selection select, + const uint8_t **hash, + int *hash_size) +{ + size_t size; + const char *filename = EC_HASH_FILENAME(select); + const uint8_t *file = cbfs_boot_map_with_leak(filename, CBFS_TYPE_RAW, &size); + + if (file == NULL) + return VB2_ERROR_UNKNOWN; + + *hash = file; + *hash_size = (int)size; + + return VB2_SUCCESS; +} + +/*********************************************************************** + * Vboot Callbacks + ***********************************************************************/ + +/* + * Unsupported. + * + * coreboot does not support the graphics initialization needed to + * display the vboot "wait" screens, etc., because the use case for + * supporting software sync early in the boot flow is to be able to + * quickly update the EC and/or sysjump to RW earlier so that USB-PD + * power (> 15 W) can be negotiated for earlier. + */ +vb2_error_t VbExDisplayScreen(uint32_t screen_type, uint32_t locale, + const VbScreenData *data) +{ + return VB2_ERROR_UNKNOWN; +} + +/* + * Write opaque data into NV storage region. + */ +vb2_error_t VbExNvStorageWrite(const uint8_t *buf) +{ + save_vbnv(buf); + return VB2_SUCCESS; +} + +/* + * Report whether the EC is in RW or not. + */ +vb2_error_t vb2ex_ec_running_rw(int *in_rw) +{ + *in_rw = !google_ec_running_ro(); + return VB2_SUCCESS; +} + +/* + * Callback for when Vboot is finished. + */ +vb2_error_t vb2ex_ec_vboot_done(struct vb2_context *ctx) +{ + int limit_power = 0; + bool message_printed = false; + struct stopwatch sw; + vb2_error_t rv = VB2_SUCCESS; + int in_recovery = !!(ctx->flags & VB2_CONTEXT_RECOVERY_MODE); + + /* + * Do not wait for the limit power flag to be cleared in + * recovery mode since we didn't just sysjump. + */ + if (in_recovery) + return VB2_SUCCESS; + + stopwatch_init_msecs_expire(&sw, LIMIT_POWER_WAIT_TIMEOUT_MS); + + /* Ensure we have enough power to continue booting */ + while (1) { + if (google_chromeec_read_limit_power_request(&limit_power)) { + printk(BIOS_ERR, "Failed to check EC limit power" + "flag.\n"); + rv = VB2_ERROR_UNKNOWN; + break; + } + + if (!limit_power || stopwatch_expired(&sw)) + break; + + if (!message_printed) { + printk(BIOS_SPEW, + "Waiting for EC to clear limit power flag.\n"); + message_printed = true; + } + + mdelay(LIMIT_POWER_POLL_SLEEP_MS); + } + + if (limit_power) { + printk(BIOS_INFO, + "EC requests limited power usage. Request shutdown.\n"); + rv = VBERROR_SHUTDOWN_REQUESTED; + } else { + printk(BIOS_INFO, "Waited %luus to clear limit power flag.\n", + stopwatch_duration_usecs(&sw)); + } + + return rv; +} + +/* + * Support battery cutoff if required. + */ +vb2_error_t vb2ex_ec_battery_cutoff(void) +{ + if (google_chromeec_battery_cutoff(EC_BATTERY_CUTOFF_FLAG_AT_SHUTDOWN)) + return VB2_ERROR_UNKNOWN; + + return VB2_SUCCESS; +} + +/* + * Vboot callback for calculating an EC image's hash. + */ +vb2_error_t vb2ex_ec_hash_image(enum vb2_firmware_selection select, + const uint8_t **hash, int *hash_size) +{ + return ec_hash_image(select, hash, hash_size); +} + +/* + * Vboot callback for EC flash protection. + */ +vb2_error_t vb2ex_ec_protect(enum vb2_firmware_selection select) +{ + return ec_protect_flash(select, 1); +} + +/* + * Get hash for image. + */ +vb2_error_t vb2ex_ec_get_expected_image_hash(enum vb2_firmware_selection select, + const uint8_t **hash, + int *hash_size) +{ + return ec_get_expected_hash(select, hash, hash_size); +} + +/* + * Disable further sysjumps (i.e., stay in RW until next reboot) + */ +vb2_error_t vb2ex_ec_disable_jump(void) +{ + if (google_chromeec_reboot(0, EC_REBOOT_DISABLE_JUMP, 0)) + return VB2_ERROR_UNKNOWN; + + return VB2_SUCCESS; +} + +/* + * Update EC image. + */ +vb2_error_t vb2ex_ec_update_image(enum vb2_firmware_selection select) +{ + return ec_update_image(select); +} + +/* + * Vboot callback for commanding EC to sysjump to RW. + */ +vb2_error_t vb2ex_ec_jump_to_rw(void) +{ + struct stopwatch sw; + + if (google_chromeec_reboot(0, EC_REBOOT_JUMP_RW, 0)) + return VB2_ERROR_UNKNOWN; + + /* Give the EC 3 seconds to sysjump */ + stopwatch_init_msecs_expire(&sw, CROS_EC_SYSJUMP_TIMEOUT_MS); + + /* Default delay to wait after EC reboot */ + mdelay(50); + while (google_chromeec_hello()) { + if (stopwatch_expired(&sw)) { + printk(BIOS_ERR, "EC did not return from reboot after %luus\n", + stopwatch_duration_usecs(&sw)); + return VB2_ERROR_UNKNOWN; + } + + mdelay(5); + } + + printk(BIOS_INFO, "\nEC returned from reboot after %luus\n", + stopwatch_duration_usecs(&sw)); + + return VB2_SUCCESS; +} diff --git a/src/security/vboot/vboot_common.h b/src/security/vboot/vboot_common.h index a20ab62bd4..d296574eaf 100644 --- a/src/security/vboot/vboot_common.h +++ b/src/security/vboot/vboot_common.h @@ -80,4 +80,13 @@ static inline int vboot_can_enable_udc(void) { return 1; } static inline void vboot_run_logic(void) {} #endif +void vboot_save_nvdata_only(struct vb2_context *ctx); +void vboot_save_data(struct vb2_context *ctx); + +/* + * The API for performing EC software sync. Does not support + * "slow" updates or Auxiliary FW sync. + */ +void vboot_sync_ec(void); + #endif /* __VBOOT_VBOOT_COMMON_H__ */ diff --git a/src/security/vboot/vboot_logic.c b/src/security/vboot/vboot_logic.c index 6ee4d948f3..ccce148882 100644 --- a/src/security/vboot/vboot_logic.c +++ b/src/security/vboot/vboot_logic.c @@ -251,21 +251,27 @@ static vb2_error_t hash_body(struct vb2_context *ctx, return VB2_SUCCESS; } -/** - * Save non-volatile and/or secure data if needed. - */ -static void save_if_needed(struct vb2_context *ctx) +void vboot_save_nvdata_only(struct vb2_context *ctx) { + assert(!(ctx->flags & (VB2_CONTEXT_SECDATA_FIRMWARE_CHANGED | + VB2_CONTEXT_SECDATA_KERNEL_CHANGED))); + if (ctx->flags & VB2_CONTEXT_NVDATA_CHANGED) { printk(BIOS_INFO, "Saving nvdata\n"); save_vbnv(ctx->nvdata); ctx->flags &= ~VB2_CONTEXT_NVDATA_CHANGED; } +} + +void vboot_save_data(struct vb2_context *ctx) +{ if (ctx->flags & VB2_CONTEXT_SECDATA_CHANGED) { printk(BIOS_INFO, "Saving secdata\n"); antirollback_write_space_firmware(ctx); ctx->flags &= ~VB2_CONTEXT_SECDATA_CHANGED; } + + vboot_save_nvdata_only(ctx); } static uint32_t extend_pcrs(struct vb2_context *ctx) @@ -368,13 +374,13 @@ void verstage_main(void) */ if (rv == VB2_ERROR_API_PHASE1_RECOVERY) { printk(BIOS_INFO, "Recovery requested (%x)\n", rv); - save_if_needed(ctx); + vboot_save_data(ctx); extend_pcrs(ctx); /* ignore failures */ goto verstage_main_exit; } printk(BIOS_INFO, "Reboot requested (%x)\n", rv); - save_if_needed(ctx); + vboot_save_data(ctx); vboot_reboot(); } @@ -383,7 +389,7 @@ void verstage_main(void) rv = vb2api_fw_phase2(ctx); if (rv) { printk(BIOS_INFO, "Reboot requested (%x)\n", rv); - save_if_needed(ctx); + vboot_save_data(ctx); vboot_reboot(); } @@ -394,7 +400,7 @@ void verstage_main(void) timestamp_add_now(TS_END_VERIFY_SLOT); if (rv) { printk(BIOS_INFO, "Reboot requested (%x)\n", rv); - save_if_needed(ctx); + vboot_save_data(ctx); vboot_reboot(); } @@ -405,7 +411,7 @@ void verstage_main(void) "Failed to read FMAP to locate firmware"); rv = hash_body(ctx, &fw_main); - save_if_needed(ctx); + vboot_save_data(ctx); if (rv) { printk(BIOS_INFO, "Reboot requested (%x)\n", rv); vboot_reboot(); @@ -419,7 +425,7 @@ void verstage_main(void) printk(BIOS_WARNING, "Failed to extend TPM PCRs (%#x)\n", rv); vb2api_fail(ctx, VB2_RECOVERY_RO_TPM_U_ERROR, rv); - save_if_needed(ctx); + vboot_save_data(ctx); vboot_reboot(); } timestamp_add_now(TS_END_TPMPCR); @@ -432,7 +438,7 @@ void verstage_main(void) if (rv) { printk(BIOS_INFO, "Failed to lock TPM (%x)\n", rv); vb2api_fail(ctx, VB2_RECOVERY_RO_TPM_L_ERROR, 0); - save_if_needed(ctx); + vboot_save_data(ctx); vboot_reboot(); } timestamp_add_now(TS_END_TPMLOCK); @@ -445,7 +451,7 @@ void verstage_main(void) rv); vb2api_fail(ctx, VB2_RECOVERY_RO_TPM_REC_HASH_L_ERROR, 0); - save_if_needed(ctx); + vboot_save_data(ctx); vboot_reboot(); } } From f9e74991d3f5dc62709b4591567156b45649018b Mon Sep 17 00:00:00 2001 From: Tim Wawrzynczak Date: Fri, 25 Oct 2019 14:59:43 -0600 Subject: [PATCH 0271/1242] security/vboot/sync_ec: Add timestamps Add 4 new timestamps to the EC software sync flow: 1) Beginning of EC software sync 2) EC finished calculating Vboot hash 3) EC is no longer requesting power limiting 4) End of EC software sync BUG=none BRANCH=none TEST=verified timestamps show up in cbmem log Change-Id: I6e5703c146b5ec27d01700fdb39cb3d2092ea8a8 Signed-off-by: Tim Wawrzynczak Reviewed-on: https://review.coreboot.org/c/coreboot/+/36209 Tested-by: build bot (Jenkins) Reviewed-by: Julius Werner --- .../include/commonlib/timestamp_serialized.h | 9 +++++++++ src/security/vboot/ec_sync.c | 19 +++++++++++++------ 2 files changed, 22 insertions(+), 6 deletions(-) diff --git a/src/commonlib/include/commonlib/timestamp_serialized.h b/src/commonlib/include/commonlib/timestamp_serialized.h index 7b1a7301c7..d7d636e6a4 100644 --- a/src/commonlib/include/commonlib/timestamp_serialized.h +++ b/src/commonlib/include/commonlib/timestamp_serialized.h @@ -79,6 +79,10 @@ enum timestamp_id { TS_END_TPMPCR = 512, TS_START_TPMLOCK = 513, TS_END_TPMLOCK = 514, + TS_START_EC_SYNC = 515, + TS_EC_HASH_READY = 516, + TS_EC_POWER_LIMIT_WAIT = 517, + TS_END_EC_SYNC = 518, TS_START_COPYVPD = 550, TS_END_COPYVPD_RO = 551, TS_END_COPYVPD_RW = 552, @@ -202,6 +206,11 @@ static const struct timestamp_id_to_name { { TS_END_COPYVPD_RO, "finished loading Chrome OS VPD (RO)" }, { TS_END_COPYVPD_RW, "finished loading Chrome OS VPD (RW)" }, + { TS_START_EC_SYNC, "starting EC software sync" }, + { TS_EC_HASH_READY, "EC vboot hash ready" }, + { TS_EC_POWER_LIMIT_WAIT, "waiting for EC to allow higher power draw" }, + { TS_END_EC_SYNC, "finished EC software sync" }, + { TS_DC_START, "depthcharge start" }, { TS_RO_PARAMS_INIT, "RO parameter init" }, { TS_RO_VB_INIT, "RO vboot init" }, diff --git a/src/security/vboot/ec_sync.c b/src/security/vboot/ec_sync.c index ec048aa91c..c2a6b25f90 100644 --- a/src/security/vboot/ec_sync.c +++ b/src/security/vboot/ec_sync.c @@ -20,6 +20,7 @@ #include #include #include +#include #include #define _EC_FILENAME(select, suffix) \ @@ -51,6 +52,8 @@ void vboot_sync_ec(void) vb2_error_t retval = VB2_SUCCESS; struct vb2_context *ctx; + timestamp_add_now(TS_START_EC_SYNC); + ctx = vboot_get_context(); ctx->flags |= VB2_CONTEXT_EC_SYNC_SUPPORTED; @@ -61,6 +64,8 @@ void vboot_sync_ec(void) printk(BIOS_ERR, "EC software sync failed (%#x), rebooting\n", retval); vboot_reboot(); } + + timestamp_add_now(TS_END_EC_SYNC); } /* Convert firmware image type into a flash offset */ @@ -138,6 +143,8 @@ static vb2_error_t ec_hash_image(enum vb2_firmware_selection select, } while (resp.status == EC_VBOOT_HASH_STATUS_BUSY && !stopwatch_expired(&sw)); + timestamp_add_now(TS_EC_HASH_READY); + if (resp.status != EC_VBOOT_HASH_STATUS_DONE) { printk(BIOS_ERR, "%s: Hash status not done: %d\n", __func__, resp.status); @@ -415,7 +422,6 @@ vb2_error_t vb2ex_ec_vboot_done(struct vb2_context *ctx) int limit_power = 0; bool message_printed = false; struct stopwatch sw; - vb2_error_t rv = VB2_SUCCESS; int in_recovery = !!(ctx->flags & VB2_CONTEXT_RECOVERY_MODE); /* @@ -425,15 +431,16 @@ vb2_error_t vb2ex_ec_vboot_done(struct vb2_context *ctx) if (in_recovery) return VB2_SUCCESS; + timestamp_add_now(TS_EC_POWER_LIMIT_WAIT); + stopwatch_init_msecs_expire(&sw, LIMIT_POWER_WAIT_TIMEOUT_MS); - /* Ensure we have enough power to continue booting */ + /* Ensure we have enough power to continue booting. */ while (1) { if (google_chromeec_read_limit_power_request(&limit_power)) { printk(BIOS_ERR, "Failed to check EC limit power" "flag.\n"); - rv = VB2_ERROR_UNKNOWN; - break; + return VB2_ERROR_UNKNOWN; } if (!limit_power || stopwatch_expired(&sw)) @@ -451,13 +458,13 @@ vb2_error_t vb2ex_ec_vboot_done(struct vb2_context *ctx) if (limit_power) { printk(BIOS_INFO, "EC requests limited power usage. Request shutdown.\n"); - rv = VBERROR_SHUTDOWN_REQUESTED; + return VBERROR_SHUTDOWN_REQUESTED; } else { printk(BIOS_INFO, "Waited %luus to clear limit power flag.\n", stopwatch_duration_usecs(&sw)); } - return rv; + return VB2_SUCCESS; } /* From a4a512c68a4b20412f1ca133f0d10c8561502da1 Mon Sep 17 00:00:00 2001 From: Tim Wawrzynczak Date: Tue, 19 Nov 2019 08:15:29 -0700 Subject: [PATCH 0272/1242] Update vboot submodule to upstream master Updating from commit id ecdca931: 2019-11-13 06:14:05 +0000 - (vboot: move vb2_context inside vb2_shared_data (persistent context)) to commit id 1c4dbaa0: 2019-11-19 06:31:23 +0000 - (Makefile: Fix typo for MOCK_TPM) This brings in 17 new commits. Signed-off-by: Tim Wawrzynczak Change-Id: I1952d7a26725e2c008b5009705b2e78ac0bb82df Reviewed-on: https://review.coreboot.org/c/coreboot/+/36936 Reviewed-by: Aaron Durbin Tested-by: build bot (Jenkins) --- 3rdparty/vboot | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/3rdparty/vboot b/3rdparty/vboot index ecdca931ae..1c4dbaa084 160000 --- a/3rdparty/vboot +++ b/3rdparty/vboot @@ -1 +1 @@ -Subproject commit ecdca931ae0637d1a9498f64862939bd5bb99e0b +Subproject commit 1c4dbaa08419e13366db32ed20244f63c34388a0 From baeced336a2b0474b4396cd5e6be31c7c39c7a8e Mon Sep 17 00:00:00 2001 From: Tim Wawrzynczak Date: Fri, 25 Oct 2019 15:04:03 -0600 Subject: [PATCH 0273/1242] security/vboot: Build vboot library with same .a that depthcharge uses Currently, depthcharge and coreboot are using two different vboot libraries. coreboot is using "fwlib20", while depthcharge uses "fwlib". The only difference between the two libraries is the inclusion of vboot1-only compilation units in fwlib, which are now deprecated. Therefore, coreboot may as well use fwlib too. Vboot is expected to converge on a single firmware library soon. BUG=none BRANCH=none TEST=compiles and runs verstage correctly Change-Id: I905b781c3596965ec7ef45a2a7eafe15fdd4d9cc Signed-off-by: Tim Wawrzynczak Reviewed-on: https://review.coreboot.org/c/coreboot/+/36341 Reviewed-by: Julius Werner Tested-by: build bot (Jenkins) --- src/security/vboot/Makefile.inc | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/src/security/vboot/Makefile.inc b/src/security/vboot/Makefile.inc index 87cd91cbf6..30c947c34d 100644 --- a/src/security/vboot/Makefile.inc +++ b/src/security/vboot/Makefile.inc @@ -110,24 +110,24 @@ vboot-fixup-includes = $(patsubst -I%,-I$(top)/%,\ # call with $1 = stage name to create rules for building the library # for the stage and adding it to the stage's set of object files. define vboot-for-stage -VB2_LIB_$(1) = $(obj)/external/vboot_reference-$(1)/vboot_fw20.a +VBOOT_LIB_$(1) = $(obj)/external/vboot_reference-$(1)/vboot_fw.a VBOOT_CFLAGS_$(1) += $$(call vboot-fixup-includes,$$(CPPFLAGS_$(1))) VBOOT_CFLAGS_$(1) += $$(CFLAGS_$(1)) VBOOT_CFLAGS_$(1) += $$(call vboot-fixup-includes,$$($(1)-c-ccopts)) VBOOT_CFLAGS_$(1) += -I$(abspath $(obj)) -Wno-missing-prototypes VBOOT_CFLAGS_$(1) += -DVBOOT_DEBUG -$$(VB2_LIB_$(1)): $(obj)/config.h +$$(VBOOT_LIB_$(1)): $(obj)/config.h printf " MAKE $(subst $(obj)/,,$(@))\n" +FIRMWARE_ARCH=$$(ARCHDIR-$$(ARCH-$(1)-y)) \ CC="$$(CC_$(1))" \ CFLAGS="$$(VBOOT_CFLAGS_$(1))" VBOOT2="y" \ $(MAKE) -C $(VBOOT_SOURCE) \ - BUILD=$$(abspath $$(dir $$(VB2_LIB_$(1)))) \ + BUILD=$$(abspath $$(dir $$(VBOOT_LIB_$(1)))) \ V=$(V) \ - fwlib20 + fwlib -$(1)-srcs += $$(VB2_LIB_$(1)) +$(1)-srcs += $$(VBOOT_LIB_$(1)) endef # vboot-for-stage From f2cae5085c49904b827d867dbf8d1a8b0d284c74 Mon Sep 17 00:00:00 2001 From: Tim Wawrzynczak Date: Fri, 25 Oct 2019 15:13:04 -0600 Subject: [PATCH 0274/1242] cpu/intel/car: Add EC software sync to Intel romstage Perform EC software sync in romstage, before memory training is started. Because the ChromeOS EC will not currently perform USB-PD negotiation until it jumps to running its RW code, this allows the system to get access to more power earlier in the boot flow. This is guarded by CONFIG_VBOOT_EARLY_EC_SYNC. BUG=b:112198832 BRANCH=none TEST=EC software sync works in update and non-update case. No significant effect on boot time (~6 ms). Change-Id: I31f3407a2afcbf288461fab1397f965f025bc07c Signed-off-by: Tim Wawrzynczak Reviewed-on: https://review.coreboot.org/c/coreboot/+/36211 Reviewed-by: Aaron Durbin Reviewed-by: Patrick Georgi Tested-by: build bot (Jenkins) --- src/cpu/intel/car/romstage.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/src/cpu/intel/car/romstage.c b/src/cpu/intel/car/romstage.c index 1525233e39..9d196356e3 100644 --- a/src/cpu/intel/car/romstage.c +++ b/src/cpu/intel/car/romstage.c @@ -21,6 +21,7 @@ #include #include #include +#include /* If we do not have a constrained _car_stack region size, use the following as a guideline for acceptable stack usage. */ @@ -51,6 +52,9 @@ static void romstage_main(unsigned long bist) for (i = 0; i < num_guards; i++) stack_base[i] = stack_guard; + if (CONFIG(VBOOT_EARLY_EC_SYNC)) + vboot_sync_ec(); + mainboard_romstage_entry(); /* Check the stack. */ From 3bc70228a2edbf9ee4283515307d8d44dd512192 Mon Sep 17 00:00:00 2001 From: Wisley Chen Date: Fri, 8 Nov 2019 23:51:00 +0800 Subject: [PATCH 0275/1242] /mb/google/hatch: Create jinlon variant Create new variant for jinlon BUG=b:144150654 TEST=emerge-hatch coreboot chromeos-bootimage and boot on jinlon proto board Change-Id: I8deb29041475e38cbbf2f54519940f62b9f21822 Signed-off-by: Wisley Chen Reviewed-on: https://review.coreboot.org/c/coreboot/+/36681 Reviewed-by: Paul Fagerburg Tested-by: build bot (Jenkins) --- src/mainboard/google/hatch/Kconfig | 2 + src/mainboard/google/hatch/Kconfig.name | 5 + .../google/hatch/variants/jinlon/Makefile.inc | 27 +++ .../google/hatch/variants/jinlon/gpio.c | 110 ++++++++++++ .../jinlon/include/variant/acpi/dptf.asl | 16 ++ .../variants/jinlon/include/variant/ec.h | 21 +++ .../variants/jinlon/include/variant/gpio.h | 27 +++ .../hatch/variants/jinlon/overridetree.cb | 159 ++++++++++++++++++ 8 files changed, 367 insertions(+) create mode 100644 src/mainboard/google/hatch/variants/jinlon/Makefile.inc create mode 100644 src/mainboard/google/hatch/variants/jinlon/gpio.c create mode 100644 src/mainboard/google/hatch/variants/jinlon/include/variant/acpi/dptf.asl create mode 100644 src/mainboard/google/hatch/variants/jinlon/include/variant/ec.h create mode 100644 src/mainboard/google/hatch/variants/jinlon/include/variant/gpio.h create mode 100644 src/mainboard/google/hatch/variants/jinlon/overridetree.cb diff --git a/src/mainboard/google/hatch/Kconfig b/src/mainboard/google/hatch/Kconfig index 6c0a94afe6..943ec612a4 100644 --- a/src/mainboard/google/hatch/Kconfig +++ b/src/mainboard/google/hatch/Kconfig @@ -92,6 +92,7 @@ config MAINBOARD_PART_NUMBER default "Hatch" if BOARD_GOOGLE_HATCH default "Helios" if BOARD_GOOGLE_HELIOS default "Helios_Diskswap" if BOARD_GOOGLE_HELIOS_DISKSWAP + default "Jinlon" if BOARD_GOOGLE_JINLON default "Kindred" if BOARD_GOOGLE_KINDRED default "Kohaku" if BOARD_GOOGLE_KOHAKU default "Puff" if BOARD_GOOGLE_PUFF @@ -120,6 +121,7 @@ config VARIANT_DIR default "hatch" if BOARD_GOOGLE_HATCH default "helios" if BOARD_GOOGLE_HELIOS default "helios" if BOARD_GOOGLE_HELIOS_DISKSWAP + default "jinlon" if BOARD_GOOGLE_JINLON default "kindred" if BOARD_GOOGLE_KINDRED default "kohaku" if BOARD_GOOGLE_KOHAKU default "puff" if BOARD_GOOGLE_PUFF diff --git a/src/mainboard/google/hatch/Kconfig.name b/src/mainboard/google/hatch/Kconfig.name index ec12096269..82da88324c 100644 --- a/src/mainboard/google/hatch/Kconfig.name +++ b/src/mainboard/google/hatch/Kconfig.name @@ -15,6 +15,11 @@ config BOARD_GOOGLE_HATCH select BOARD_GOOGLE_BASEBOARD_HATCH select BOARD_ROMSIZE_KB_32768 +config BOARD_GOOGLE_JINLON + bool "-> Jinlon" + select BOARD_GOOGLE_BASEBOARD_HATCH + select BOARD_ROMSIZE_KB_16384 + config BOARD_GOOGLE_KOHAKU bool "-> Kohaku" select BOARD_GOOGLE_BASEBOARD_HATCH diff --git a/src/mainboard/google/hatch/variants/jinlon/Makefile.inc b/src/mainboard/google/hatch/variants/jinlon/Makefile.inc new file mode 100644 index 0000000000..6e5d8835db --- /dev/null +++ b/src/mainboard/google/hatch/variants/jinlon/Makefile.inc @@ -0,0 +1,27 @@ +## This file is part of the coreboot project. +## +## Copyright 2019 Google LLC +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +SPD_SOURCES = 4G_2400 # 0b000 +SPD_SOURCES += empty_ddr4 # 0b001 +SPD_SOURCES += 8G_2400 # 0b010 +SPD_SOURCES += 8G_2666 # 0b011 +SPD_SOURCES += 16G_2400 # 0b100 +SPD_SOURCES += 16G_2666 # 0b101 +SPD_SOURCES += 8G_3200 # 0b110 +SPD_SOURCES += 16G_3200 # 0b111 +SPD_SOURCES += 16G_2666_2bg # 0b1000 +SPD_SOURCES += 16G_3200_4bg # 0b1001 + +bootblock-y += gpio.c +ramstage-y += gpio.c diff --git a/src/mainboard/google/hatch/variants/jinlon/gpio.c b/src/mainboard/google/hatch/variants/jinlon/gpio.c new file mode 100644 index 0000000000..7e475fa6a2 --- /dev/null +++ b/src/mainboard/google/hatch/variants/jinlon/gpio.c @@ -0,0 +1,110 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2019 Google LLC + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the + * GNU General Public License for more details. + */ + +#include +#include +#include +#include + +static const struct pad_config gpio_table[] = { + /* A0 : NC */ + PAD_NC(GPP_A0, NONE), + /* A6 : NC */ + PAD_NC(GPP_A6, NONE), + /* A8 : NC */ + PAD_NC(GPP_A8, NONE), + /* A10 : NC */ + PAD_NC(GPP_A10, NONE), + /* C12 : FPMCU_PCH_BOOT1 */ + PAD_CFG_GPO(GPP_C12, 0, DEEP), + /* F1 : NC */ + PAD_NC(GPP_F1, NONE), + /* F3 : MEM_STRAP_3 */ + PAD_CFG_GPI(GPP_F3, NONE, PLTRST), + /* F10 : MEM_STRAP_2 */ + PAD_CFG_GPI(GPP_F10, NONE, PLTRST), + /* F11 : EMMC_CMD ==> NC */ + PAD_NC(GPP_F11, NONE), + /* F12 : EMMC_DATA0 ==> NC */ + PAD_NC(GPP_F12, NONE), + /* F13 : EMMC_DATA1 ==> NC */ + PAD_NC(GPP_F13, NONE), + /* F14 : EMMC_DATA2 ==> NC */ + PAD_NC(GPP_F14, NONE), + /* F15 : EMMC_DATA3 ==> NC */ + PAD_NC(GPP_F15, NONE), + /* F16 : EMMC_DATA4 ==> NC */ + PAD_NC(GPP_F16, NONE), + /* F17 : EMMC_DATA5 ==> NC */ + PAD_NC(GPP_F17, NONE), + /* F18 : EMMC_DATA6 ==> NC */ + PAD_NC(GPP_F18, NONE), + /* F19 : EMMC_DATA7 ==> NC */ + PAD_NC(GPP_F19, NONE), + /* F20 : EMMC_RCLK ==> NC */ + PAD_NC(GPP_F20, NONE), + /* F21 : EMMC_CLK ==> NC */ + PAD_NC(GPP_F21, NONE), + /* F22 : EMMC_RESET# ==> NC */ + PAD_NC(GPP_F22, NONE), + /* H19 : MEM_STRAP_0 */ + PAD_CFG_GPI(GPP_H19, NONE, PLTRST), + /* H22 : MEM_STRAP_1 */ + PAD_CFG_GPI(GPP_H22, NONE, PLTRST), +}; + +const struct pad_config *override_gpio_table(size_t *num) +{ + *num = ARRAY_SIZE(gpio_table); + return gpio_table; +} + +/* + * GPIOs configured before ramstage + * Note: the Hatch platform's romstage will configure + * the MEM_STRAP_* (a.k.a GPIO_MEM_CONFIG_*) pins + * as inputs before it reads them, so they are not + * needed in this table. + */ +static const struct pad_config early_gpio_table[] = { + /* B15 : H1_SLAVE_SPI_CS_L */ + PAD_CFG_NF(GPP_B15, NONE, DEEP, NF1), + /* B16 : H1_SLAVE_SPI_CLK */ + PAD_CFG_NF(GPP_B16, NONE, DEEP, NF1), + /* B17 : H1_SLAVE_SPI_MISO_R */ + PAD_CFG_NF(GPP_B17, NONE, DEEP, NF1), + /* B18 : H1_SLAVE_SPI_MOSI_R */ + PAD_CFG_NF(GPP_B18, NONE, DEEP, NF1), + /* C14 : BT_DISABLE_L */ + PAD_CFG_GPO(GPP_C14, 0, DEEP), + /* PCH_WP_OD */ + PAD_CFG_GPI(GPP_C20, NONE, DEEP), + /* C21 : H1_PCH_INT_ODL */ + PAD_CFG_GPI_APIC(GPP_C21, NONE, PLTRST, LEVEL, INVERT), + /* C23 : WLAN_PE_RST# */ + PAD_CFG_GPO(GPP_C23, 1, DEEP), + /* E1 : M2_SSD_PEDET */ + PAD_CFG_NF(GPP_E1, NONE, DEEP, NF1), + /* E5 : SATA_DEVSLP1 */ + PAD_CFG_NF(GPP_E5, NONE, PLTRST, NF1), + /* F2 : MEM_CH_SEL */ + PAD_CFG_GPI(GPP_F2, NONE, PLTRST), +}; + +const struct pad_config *variant_early_gpio_table(size_t *num) +{ + *num = ARRAY_SIZE(early_gpio_table); + return early_gpio_table; +} diff --git a/src/mainboard/google/hatch/variants/jinlon/include/variant/acpi/dptf.asl b/src/mainboard/google/hatch/variants/jinlon/include/variant/acpi/dptf.asl new file mode 100644 index 0000000000..f1f09438fa --- /dev/null +++ b/src/mainboard/google/hatch/variants/jinlon/include/variant/acpi/dptf.asl @@ -0,0 +1,16 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2019 Google LLC + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include diff --git a/src/mainboard/google/hatch/variants/jinlon/include/variant/ec.h b/src/mainboard/google/hatch/variants/jinlon/include/variant/ec.h new file mode 100644 index 0000000000..768987d225 --- /dev/null +++ b/src/mainboard/google/hatch/variants/jinlon/include/variant/ec.h @@ -0,0 +1,21 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2019 Google LLC + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef VARIANT_EC_H +#define VARIANT_EC_H + +#include + +#endif diff --git a/src/mainboard/google/hatch/variants/jinlon/include/variant/gpio.h b/src/mainboard/google/hatch/variants/jinlon/include/variant/gpio.h new file mode 100644 index 0000000000..92f9d412fd --- /dev/null +++ b/src/mainboard/google/hatch/variants/jinlon/include/variant/gpio.h @@ -0,0 +1,27 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2019 Google LLC + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the + * GNU General Public License for more details. + */ + +#ifndef VARIANT_GPIO_H +#define VARIANT_GPIO_H + +#include + +/* Memory configuration board straps */ +#define GPIO_MEM_CONFIG_0 GPP_H19 +#define GPIO_MEM_CONFIG_1 GPP_H22 +#define GPIO_MEM_CONFIG_2 GPP_F10 +#define GPIO_MEM_CONFIG_3 GPP_F3 + +#endif diff --git a/src/mainboard/google/hatch/variants/jinlon/overridetree.cb b/src/mainboard/google/hatch/variants/jinlon/overridetree.cb new file mode 100644 index 0000000000..28b18b8b7f --- /dev/null +++ b/src/mainboard/google/hatch/variants/jinlon/overridetree.cb @@ -0,0 +1,159 @@ +chip soc/intel/cannonlake + + register "SerialIoDevMode" = "{ + [PchSerialIoIndexI2C0] = PchSerialIoPci, + [PchSerialIoIndexI2C1] = PchSerialIoPci, + [PchSerialIoIndexI2C2] = PchSerialIoPci, + [PchSerialIoIndexI2C3] = PchSerialIoPci, + [PchSerialIoIndexI2C4] = PchSerialIoPci, + [PchSerialIoIndexI2C5] = PchSerialIoPci, + [PchSerialIoIndexSPI0] = PchSerialIoPci, + [PchSerialIoIndexSPI1] = PchSerialIoPci, + [PchSerialIoIndexSPI2] = PchSerialIoDisabled, + [PchSerialIoIndexUART0] = PchSerialIoSkipInit, + [PchSerialIoIndexUART1] = PchSerialIoDisabled, + [PchSerialIoIndexUART2] = PchSerialIoDisabled, + }" + + # Intel Common SoC Config + #+-------------------+---------------------------+ + #| Field | Value | + #+-------------------+---------------------------+ + #| GSPI0 | cr50 TPM. Early init is | + #| | required to set up a BAR | + #| | for TPM communication | + #| | before memory is up | + #| GSPI1 | FP MCU | + #| I2C0 | Touchpad | + #| I2C1 | Touch screen | + #| I2C4 | Audio | + #+-------------------+---------------------------+ + register "common_soc_config" = "{ + .gspi[0] = { + .speed_mhz = 1, + .early_init = 1, + }, + .i2c[0] = { + .speed = I2C_SPEED_FAST, + }, + .i2c[1] = { + .speed = I2C_SPEED_FAST, + }, + .i2c[3] = { + .speed = I2C_SPEED_FAST, + }, + .i2c[4] = { + .speed = I2C_SPEED_FAST, + }, + }" + + # GPIO for SD card detect + register "sdcard_cd_gpio" = "vSD3_CD_B" + + # Enable eMMC HS400 + register "ScsEmmcHs400Enabled" = "1" + + device domain 0 on + device pci 15.0 on + chip drivers/i2c/generic + register "hid" = ""ELAN0000"" + register "desc" = ""ELAN Touchpad"" + register "irq" = "ACPI_IRQ_WAKE_EDGE_LOW(GPP_A21_IRQ)" + register "wake" = "GPE0_DW0_21" + register "probed" = "1" + device i2c 15 on end + end + end # I2C #0 + device pci 15.1 on + chip drivers/i2c/hid + register "generic.hid" = ""GTCH7503"" + register "generic.desc" = ""G2TOUCH Touchscreen"" + register "generic.irq" = "ACPI_IRQ_EDGE_LOW(GPP_D16_IRQ)" + register "generic.probed" = "1" + register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D15)" + register "generic.reset_delay_ms" = "50" + register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D9)" + register "generic.enable_delay_ms" = "1" + register "generic.has_power_resource" = "1" + register "generic.disable_gpio_export_in_crs" = "1" + register "hid_desc_reg_offset" = "0x01" + device i2c 40 on end + end + chip drivers/i2c/generic + register "hid" = ""ELAN0001"" + register "desc" = ""ELAN Touchscreen"" + register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_D16_IRQ)" + register "probed" = "1" + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D15)" + register "reset_delay_ms" = "100" + register "reset_off_delay_ms" = "5" + register "has_power_resource" = "1" + register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D9)" + register "enable_delay_ms" = "10" + register "enable_off_delay_ms" = "1" + device i2c 10 on end + end + chip drivers/i2c/hid + register "generic.hid" = ""GDIX0000"" + register "generic.desc" = ""Goodix Touchscreen"" + register "generic.irq" = "ACPI_IRQ_EDGE_LOW(GPP_D16_IRQ)" + register "generic.probed" = "1" + register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D15)" + register "generic.reset_delay_ms" = "120" + register "generic.reset_off_delay_ms" = "3" + register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D9)" + register "generic.enable_delay_ms" = "10" + register "generic.stop_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C4)" + register "generic.stop_off_delay_ms" = "20" + register "generic.has_power_resource" = "1" + register "hid_desc_reg_offset" = "0x01" + device i2c 5d on end + end + chip drivers/i2c/hid + register "generic.hid" = ""ELAN2513"" + register "generic.desc" = ""ELAN Touchscreen"" + register "generic.irq" = "ACPI_IRQ_EDGE_LOW(GPP_D16_IRQ)" + register "generic.probed" = "1" + register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D15)" + register "generic.reset_delay_ms" = "20" + register "generic.reset_off_delay_ms" = "2" + register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D9)" + register "generic.enable_delay_ms" = "10" + register "generic.stop_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C4)" + register "generic.stop_delay_ms" = "130" + register "generic.has_power_resource" = "1" + register "hid_desc_reg_offset" = "0x01" + device i2c 15 on end + end + end # I2C #1 + device pci 15.2 off end # I2C #2 + device pci 15.3 off end # I2C #3 + device pci 19.0 on + chip drivers/i2c/generic + register "hid" = ""10EC5682"" + register "name" = ""RT58"" + register "desc" = ""Realtek RT5682"" + register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_BOTH(GPP_H0)" + register "property_count" = "1" + # Set the jd_src to RT5668_JD1 for jack detection + register "property_list[0].type" = "ACPI_DP_TYPE_INTEGER" + register "property_list[0].name" = ""realtek,jd-src"" + register "property_list[0].integer" = "1" + device i2c 1a on end + end + end #I2C #4 + device pci 1a.0 on end # eMMC + device pci 1e.3 on + chip drivers/spi/acpi + register "name" = ""CRFP"" + register "hid" = "ACPI_DT_NAMESPACE_HID" + register "uid" = "1" + register "compat_string" = ""google,cros-ec-spi"" + register "irq" = "ACPI_IRQ_WAKE_LEVEL_LOW(GPP_A23_IRQ)" + register "wake" = "GPE0_DW0_23" + device spi 1 on end + end # FPMCU + end # GSPI #1 + end + +end From 941f2a9c0c29ab42e4d2c9e6f8f058a1ec9278d3 Mon Sep 17 00:00:00 2001 From: Arthur Heymans Date: Sun, 17 Nov 2019 16:55:41 +0100 Subject: [PATCH 0276/1242] mb/lenovo/x201: Remove unnecessary GPIO settings GPIO49 is strapped high, so setting it low likely increases power usage. GPIO53 is hooked to a testpad so there is no reason to set it here. Change-Id: I00fb38c90417b673c2b36191c20279474eb0dc21 Signed-off-by: Arthur Heymans Reviewed-on: https://review.coreboot.org/c/coreboot/+/36910 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Rudolph Reviewed-by: Nico Huber --- src/mainboard/lenovo/x201/romstage.c | 2 -- 1 file changed, 2 deletions(-) diff --git a/src/mainboard/lenovo/x201/romstage.c b/src/mainboard/lenovo/x201/romstage.c index 99875ed65a..c8e8afbb30 100644 --- a/src/mainboard/lenovo/x201/romstage.c +++ b/src/mainboard/lenovo/x201/romstage.c @@ -55,8 +55,6 @@ static void set_fsb_frequency(void) void mainboard_pre_raminit(void) { - outb((inb(DEFAULT_GPIOBASE | 0x3a) & ~0x2) | 0x20, - DEFAULT_GPIOBASE | 0x3a); outb(0x50, 0x15ec); outb(inb(0x15ee) & 0x70, 0x15ee); From 12487319913e8b8c9ea4acc946e37ccbcd6e3909 Mon Sep 17 00:00:00 2001 From: Matt DeVillier Date: Sun, 17 Nov 2019 17:51:02 -0600 Subject: [PATCH 0277/1242] purism/librem_bdw: add/use VBT file Add VBT file extracted from vendor (AMI) firmware, use by default to ensure functional display after resume from S3 when using libgfxinit. Test: build/boot Librem 13v1/15v2 boards, verify functional display after resume from S3 when using libgfxinit. Signed-off-by: Matt DeVillier Change-Id: I44d75486da3083cd1f07ea82dc18688db84a621e Reviewed-on: https://review.coreboot.org/c/coreboot/+/36916 Reviewed-by: Nico Huber Tested-by: build bot (Jenkins) --- src/mainboard/purism/librem_bdw/Kconfig | 6 ++++++ src/mainboard/purism/librem_bdw/data.vbt | Bin 0 -> 4608 bytes 2 files changed, 6 insertions(+) create mode 100644 src/mainboard/purism/librem_bdw/data.vbt diff --git a/src/mainboard/purism/librem_bdw/Kconfig b/src/mainboard/purism/librem_bdw/Kconfig index 339d7012f7..224bde0e67 100644 --- a/src/mainboard/purism/librem_bdw/Kconfig +++ b/src/mainboard/purism/librem_bdw/Kconfig @@ -5,6 +5,7 @@ config BOARD_PURISM_BASEBOARD_LIBREM_BDW select EC_PURISM_LIBREM select HAVE_ACPI_RESUME select HAVE_ACPI_TABLES + select INTEL_GMA_HAVE_VBT select INTEL_INT15 select MAINBOARD_HAS_LIBGFXINIT select SOC_INTEL_BROADWELL @@ -73,6 +74,11 @@ config VGA_BIOS_ID default "8086,1616" if BOARD_PURISM_LIBREM13_V1 default "8086,162b" if BOARD_PURISM_LIBREM15_V2 +# Override the default variant behavior, since the data.vbt is the same +# for both variants. +config INTEL_GMA_VBT_FILE + default "src/mainboard/$(MAINBOARDDIR)/data.vbt" + # This platform has limited means to display POST codes config NO_POST default y diff --git a/src/mainboard/purism/librem_bdw/data.vbt b/src/mainboard/purism/librem_bdw/data.vbt new file mode 100644 index 0000000000000000000000000000000000000000..ad9fb6557ab6ea047f4f6cef1db41d17ff66b0d3 GIT binary patch literal 4608 zcmdT{U2GFa5T3m|+voG$**PdUZb&B(fs-cTVnRxzR6QpSwSytf4Yjp+2DYr9yo|RH{(LLxm{r?A^r#g1~~( zmO1Ut?Cjikv$MOid-cOzLzs*YZsn_r14&&lqO9QyAa2EkBwc z-?BfS!@=P<;>a;IrR%`X(HyQjuxo36yaPE9Sz~Kk%ZfIn=JM7R%VTD1jAXN;wY_8I ztD2JN>F!&bNu}dMslIjCH-L%MV0>_}XKh#dP0S4RB~x9gp`L`M%#5RZ&)ECpJKx!{ zAEVt37&A??nJ`KxEuj=Tux)Q6Cz3I%r(D2B{O@$9X`gk$|cg~Va_K-Pa zoB(uYLQ1KHaWM)fMFGAQSHW8868z>z(3KF>QE8*H*(bv{J_Ej^a*@iq$msjdd zspRv)-O}YSluGhz+yjdcC{!%rA|+j(wz()~-1ZQ09^VnST`Kvr)Qr*d>}ur)zUCb& zm7aGga1rVXGzfQJAs-L(j4k54Oa+o=8wj59M;nyioDm*Gn9-N{(;KMspqCPfD0fcQ z*s$vXN+&fDCP2~sz;y3Mc-Pwu!B4?op1|_=|1rVuCc6p&t0?=qWT-RA!dA>b0p5ty z)tw9K)2j;8kX@`-Exk)_tiu^CPBb<5m39kZBh?4A_iC@+TD6-vNYe7D%)dH+v|2P*WK zhuhHZC{?-Sw4bi7X@{%+LJ_Ym3dz~U4pwa?nni8oEn|LJ@JMRe2bol8N%8rr%tb+x z!}Akdlw?*{pH=1BDt?=}pI+KTPyz!#$RN&jH3Z% zDu5RP#!ms|*8s|@5mA+T6?;`|UysR46RON<>Aj$Bnu%sw)R|JgysOb>*Cnzv#wIUAe6z28~!y z=?rR(f~O!{V}&Z(xU@awag~<$h@jg177G#g1eeibnLC%XqugDF;)w8ggsC7x>qreo z3-g@_)wUlJC|*P=g<5<(!rTnuFlM3Py1w z0#g}WXsTv6f6I=8Sfu@EM{E*rP?F}u1ku$xQ=zoIOo>}s2{S(Wj2dL=<_+&M? fk)r>J^^k!aG_j*_U2K^KI9#UZL%ctl|3>R?*pdJ) literal 0 HcmV?d00001 From efe3cfb476b39da5ece2583000e0f24b5daf560b Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Michael=20Niew=C3=B6hner?= Date: Fri, 15 Nov 2019 22:47:33 +0100 Subject: [PATCH 0278/1242] include/device: add a comment to pci mmio cfg addr helpers and caching MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add a comment to the newly introduced MMIO address helpers for PCI config registers, that the pointer returned may change during the boot processs and, thus, must not be cached. Change-Id: Ieb90ae9d67a3b944d35587dec54756a17c27c86f Signed-off-by: Michael Niewöhner Reviewed-on: https://review.coreboot.org/c/coreboot/+/36875 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin --- src/include/device/pci_mmio_cfg.h | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/src/include/device/pci_mmio_cfg.h b/src/include/device/pci_mmio_cfg.h index 8f26ff29b0..30945f4c27 100644 --- a/src/include/device/pci_mmio_cfg.h +++ b/src/include/device/pci_mmio_cfg.h @@ -86,6 +86,12 @@ void pci_mmio_write_config32(pci_devfn_t dev, uint16_t reg, uint32_t value) pcicfg(dev)->reg32[reg / sizeof(uint32_t)] = value; } +/* + * The functions pci_mmio_config*_addr provide a way to determine the MMIO address of a PCI + * config register. The address returned is dependent of both the MMCONF base address and the + * assigned PCI bus number of the requested device, which both can change during the boot + * process. Thus, the pointer returned here must not be cached! + */ static __always_inline uint8_t *pci_mmio_config8_addr(pci_devfn_t dev, uint16_t reg) { From 35e76dde7708d0646c56eaf3b5c063b27d2add62 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Michael=20Niew=C3=B6hner?= Date: Sat, 2 Nov 2019 12:14:06 +0100 Subject: [PATCH 0279/1242] soc/intel/skylake: add soc implementation for ETR address API MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add soc implementation for the new ETR address API. Change-Id: Iae54af09347d693620b631721576e4b916ea0f0f Signed-off-by: Michael Niewöhner Reviewed-on: https://review.coreboot.org/c/coreboot/+/36569 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin --- src/soc/intel/skylake/pmutil.c | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/src/soc/intel/skylake/pmutil.c b/src/soc/intel/skylake/pmutil.c index 329cea9621..eb36e48ace 100644 --- a/src/soc/intel/skylake/pmutil.c +++ b/src/soc/intel/skylake/pmutil.c @@ -173,6 +173,16 @@ uintptr_t soc_read_pmc_base(void) return (uintptr_t) (pmc_mmio_regs()); } +uint32_t *soc_pmc_etr_addr(void) +{ + /* + * The pointer returned must not be cached, because the address depends on the + * MMCONF base address and the assigned PCI bus number, which both may change + * during the boot process! + */ + return pci_mmio_config32_addr(PCH_DEVFN_PMC << 12, ETR); +} + void soc_get_gpi_gpe_configs(uint8_t *dw0, uint8_t *dw1, uint8_t *dw2) { DEVTREE_CONST struct soc_intel_skylake_config *config; From 1c6ea92e6fcee21aa01a20500594a09ab14caa74 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Michael=20Niew=C3=B6hner?= Date: Sat, 2 Nov 2019 12:20:53 +0100 Subject: [PATCH 0280/1242] soc/intel/common: pmclib: make use of the new ETR address API MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Make use of the new ETR address API in the ETR3 register related functions. Further, disabling and locking of global reset is now done at once to save one read-modify-write cycle, thus the function was renamed accordingly and the now redundant disabling in soc/apl got removed. Change-Id: I49f59efb4a7c7d3d629ac54a7922bbcc8a87714d Signed-off-by: Michael Niewöhner Reviewed-on: https://review.coreboot.org/c/coreboot/+/36570 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber Reviewed-by: Aaron Durbin --- src/soc/intel/apollolake/chip.c | 4 +-- .../common/block/include/intelblocks/pmclib.h | 11 +++++-- src/soc/intel/common/block/pmc/pmclib.c | 29 +++++-------------- 3 files changed, 17 insertions(+), 27 deletions(-) diff --git a/src/soc/intel/apollolake/chip.c b/src/soc/intel/apollolake/chip.c index 1aab8a1b7a..6c195bb6fd 100644 --- a/src/soc/intel/apollolake/chip.c +++ b/src/soc/intel/apollolake/chip.c @@ -418,10 +418,8 @@ static void soc_init(void *data) static void soc_final(void *data) { - /* Disable global reset, just in case */ - pmc_global_reset_enable(0); /* Make sure payload/OS can't trigger global reset */ - pmc_global_reset_lock(); + pmc_global_reset_disable_and_lock(); } static void disable_dev(struct device *dev, FSP_S_CONFIG *silconfig) diff --git a/src/soc/intel/common/block/include/intelblocks/pmclib.h b/src/soc/intel/common/block/include/intelblocks/pmclib.h index 7cc501df7e..b622a74b9b 100644 --- a/src/soc/intel/common/block/include/intelblocks/pmclib.h +++ b/src/soc/intel/common/block/include/intelblocks/pmclib.h @@ -133,10 +133,15 @@ void pmc_clear_prsts(void); */ void pmc_global_reset_enable(bool enable); /* - * If possible, lock 0xcf9. Once the register is locked, it can't be changed. - * This lock is reset on cold boot, hard reset, soft reset and Sx. + * Disable global reset and lock the CF9 global reset register in accordance to PCH ME BWG + * sections 4.4.1, 4.5.1 and 18.4 and the PCH datasheet(s) (Intel doc e.g. 332691-002EN, + * 332996-002EN). Deviate from the BGW we don't depend on the Intel ME state because Intel + * FPT (Flash Programming Tool) normally is not used with coreboot. + * + * Once the register is locked, it can't be changed. This lock is reset on cold boot, hard + * reset, soft reset and Sx. */ -void pmc_global_reset_lock(void); +void pmc_global_reset_disable_and_lock(void); /* Returns the power state structure */ struct chipset_power_state *pmc_get_power_state(void); diff --git a/src/soc/intel/common/block/pmc/pmclib.c b/src/soc/intel/common/block/pmc/pmclib.c index d7362b6dc4..82b391b958 100644 --- a/src/soc/intel/common/block/pmc/pmclib.c +++ b/src/soc/intel/common/block/pmc/pmclib.c @@ -420,37 +420,24 @@ int pmc_fill_power_state(struct chipset_power_state *ps) } #if CONFIG(PMC_GLOBAL_RESET_ENABLE_LOCK) -/* - * If possible, lock 0xcf9. Once the register is locked, it can't be changed. - * This lock is reset on cold boot, hard reset, soft reset and Sx. - */ -void pmc_global_reset_lock(void) +void pmc_global_reset_disable_and_lock(void) { - /* Read PMC base address from soc */ - uintptr_t etr = soc_read_pmc_base() + ETR; + uint32_t *etr = soc_pmc_etr_addr(); uint32_t reg; - reg = read32((void *)etr); - if (reg & CF9_LOCK) - return; - reg |= CF9_LOCK; - write32((void *)etr, reg); + reg = read32(etr); + reg = (reg & ~CF9_GLB_RST) | CF9_LOCK; + write32(etr, reg); } -/* - * Enable or disable global reset. If global reset is enabled, hard reset and - * soft reset will trigger global reset, where both host and TXE are reset. - * This is cleared on cold boot, hard reset, soft reset and Sx. - */ void pmc_global_reset_enable(bool enable) { - /* Read PMC base address from soc */ - uintptr_t etr = soc_read_pmc_base() + ETR; + uint32_t *etr = soc_pmc_etr_addr(); uint32_t reg; - reg = read32((void *)etr); + reg = read32(etr); reg = enable ? reg | CF9_GLB_RST : reg & ~CF9_GLB_RST; - write32((void *)etr, reg); + write32(etr, reg); } #endif // CONFIG_PMC_GLOBAL_RESET_ENABLE_LOCK From dce635977381ff293f7f74c5cdfae142f36412d8 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Michael=20Niew=C3=B6hner?= Date: Tue, 17 Sep 2019 18:48:00 +0200 Subject: [PATCH 0281/1242] soc/intel/cannonlake: lockdown: lock global reset MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit There are four chipsets selecting PMC_GLOBAL_RESET_ENABLE_LOCK but only one (apollolake) is actually calling the code. Add the missing call. Change-Id: I6aba9bcb2ad09e6ae0e02d8c0b552e34bdb3fa72 Signed-off-by: Michael Niewöhner Reviewed-on: https://review.coreboot.org/c/coreboot/+/36571 Reviewed-by: Aaron Durbin Tested-by: build bot (Jenkins) --- src/soc/intel/cannonlake/lockdown.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/src/soc/intel/cannonlake/lockdown.c b/src/soc/intel/cannonlake/lockdown.c index ba68aa385c..c556839d18 100644 --- a/src/soc/intel/cannonlake/lockdown.c +++ b/src/soc/intel/cannonlake/lockdown.c @@ -15,6 +15,7 @@ #include #include +#include #include #include @@ -60,6 +61,8 @@ static void pmc_lockdown_cfg(int chipset_lockdown) pmc_lock_pmsync(); /* Lock down ABASE and sleep stretching policy */ pmc_lock_abase(); + /* Make sure payload/OS can't trigger global reset */ + pmc_global_reset_disable_and_lock(); if (chipset_lockdown == CHIPSET_LOCKDOWN_COREBOOT) pmc_lock_smi(); From 8370f6b79c06bcea1a04f53e9028d0aa447e3583 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Michael=20Niew=C3=B6hner?= Date: Tue, 17 Sep 2019 18:48:00 +0200 Subject: [PATCH 0282/1242] soc/intel/icelake: lockdown: lock global reset MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit There are four chipsets selecting PMC_GLOBAL_RESET_ENABLE_LOCK but only one (apollolake) is actually calling the code. Add the missing call. Change-Id: I3e450a473ccdf99221e82e0f857879039d78991b Signed-off-by: Michael Niewöhner Reviewed-on: https://review.coreboot.org/c/coreboot/+/36572 Reviewed-by: Aaron Durbin Tested-by: build bot (Jenkins) --- src/soc/intel/icelake/lockdown.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/src/soc/intel/icelake/lockdown.c b/src/soc/intel/icelake/lockdown.c index 85a93c7c8e..b92d1c52f9 100644 --- a/src/soc/intel/icelake/lockdown.c +++ b/src/soc/intel/icelake/lockdown.c @@ -15,6 +15,7 @@ #include #include +#include #include #include @@ -60,6 +61,8 @@ static void pmc_lockdown_cfg(int chipset_lockdown) pmc_lock_pmsync(); /* Lock down ABASE and sleep stretching policy */ pmc_lock_abase(); + /* Make sure payload/OS can't trigger global reset */ + pmc_global_reset_disable_and_lock(); if (chipset_lockdown == CHIPSET_LOCKDOWN_COREBOOT) pmc_lock_smi(); From 43d2527203121be776d3e532c09ca46c2a8afaf9 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Michael=20Niew=C3=B6hner?= Date: Tue, 17 Sep 2019 18:48:00 +0200 Subject: [PATCH 0283/1242] soc/intel/skylake: lockdown: lock global reset MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit There are four chipsets selecting PMC_GLOBAL_RESET_ENABLE_LOCK but only one (apollolake) is actually calling the code. Add the missing call. Also fix the register offset in a comment in reset code. Tested successfully on X11SSM-F by reading ETR3. Change-Id: If190c3c66889ede105d958b423b38ebdcb698332 Signed-off-by: Michael Niewöhner Reviewed-on: https://review.coreboot.org/c/coreboot/+/36573 Reviewed-by: Aaron Durbin Tested-by: build bot (Jenkins) --- src/soc/intel/skylake/lockdown.c | 4 ++++ src/soc/intel/skylake/reset.c | 2 +- 2 files changed, 5 insertions(+), 1 deletion(-) diff --git a/src/soc/intel/skylake/lockdown.c b/src/soc/intel/skylake/lockdown.c index 69459e7e03..66dae8c73c 100644 --- a/src/soc/intel/skylake/lockdown.c +++ b/src/soc/intel/skylake/lockdown.c @@ -16,6 +16,7 @@ #include #include #include +#include #include #include @@ -38,6 +39,9 @@ static void pmc_lockdown_config(void) pmsyncreg = read32(pmcbase + PMSYNC_TPR_CFG); pmsyncreg |= PMSYNC_LOCK; write32(pmcbase + PMSYNC_TPR_CFG, pmsyncreg); + + /* Make sure payload/OS can't trigger global reset */ + pmc_global_reset_disable_and_lock(); } void soc_lockdown_config(int chipset_lockdown) diff --git a/src/soc/intel/skylake/reset.c b/src/soc/intel/skylake/reset.c index ff1a959194..8f5bf30946 100644 --- a/src/soc/intel/skylake/reset.c +++ b/src/soc/intel/skylake/reset.c @@ -26,7 +26,7 @@ static void do_force_global_reset(void) /* * BIOS should ensure it does a global reset * to reset both host and Intel ME by setting - * PCH PMC [B0:D31:F2 register offset 0x1048 bit 20] + * PCH PMC [B0:D31:F2 register offset 0xAC bit 20] */ pmc_global_reset_enable(true); From fbc59ffb64579fa161decd6ab82d50f67877f3a0 Mon Sep 17 00:00:00 2001 From: Arthur Heymans Date: Tue, 19 Nov 2019 15:42:55 +0100 Subject: [PATCH 0284/1242] mb/via/epia-m850: Drop support MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Relocatable ramstage, postcar stage and C_ENVIRONMENT_BOOTBLOCK are now mandatory features, which this platform lacks. Change-Id: Id6aa669542bcfd774fa5571d790f59f156a39a4b Signed-off-by: Arthur Heymans Reviewed-on: https://review.coreboot.org/c/coreboot/+/36949 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki Reviewed-by: HAOUAS Elyes Reviewed-by: Nico Huber --- src/mainboard/via/Kconfig | 16 --- src/mainboard/via/Kconfig.name | 2 - src/mainboard/via/epia-m850/Kconfig | 45 --------- src/mainboard/via/epia-m850/Kconfig.name | 2 - src/mainboard/via/epia-m850/board_info.txt | 7 -- src/mainboard/via/epia-m850/devicetree.cb | 108 --------------------- src/mainboard/via/epia-m850/irq_tables.c | 71 -------------- src/mainboard/via/epia-m850/mainboard.c | 107 -------------------- src/mainboard/via/epia-m850/romstage.c | 98 ------------------- 9 files changed, 456 deletions(-) delete mode 100644 src/mainboard/via/Kconfig delete mode 100644 src/mainboard/via/Kconfig.name delete mode 100644 src/mainboard/via/epia-m850/Kconfig delete mode 100644 src/mainboard/via/epia-m850/Kconfig.name delete mode 100644 src/mainboard/via/epia-m850/board_info.txt delete mode 100644 src/mainboard/via/epia-m850/devicetree.cb delete mode 100644 src/mainboard/via/epia-m850/irq_tables.c delete mode 100644 src/mainboard/via/epia-m850/mainboard.c delete mode 100644 src/mainboard/via/epia-m850/romstage.c diff --git a/src/mainboard/via/Kconfig b/src/mainboard/via/Kconfig deleted file mode 100644 index d14c758176..0000000000 --- a/src/mainboard/via/Kconfig +++ /dev/null @@ -1,16 +0,0 @@ -if VENDOR_VIA - -choice - prompt "Mainboard model" - -source "src/mainboard/via/*/Kconfig.name" - -endchoice - -source "src/mainboard/via/*/Kconfig" - -config MAINBOARD_VENDOR - string - default "VIA" - -endif # VENDOR_VIA diff --git a/src/mainboard/via/Kconfig.name b/src/mainboard/via/Kconfig.name deleted file mode 100644 index 901538962d..0000000000 --- a/src/mainboard/via/Kconfig.name +++ /dev/null @@ -1,2 +0,0 @@ -config VENDOR_VIA - bool "VIA" diff --git a/src/mainboard/via/epia-m850/Kconfig b/src/mainboard/via/epia-m850/Kconfig deleted file mode 100644 index f6c06217e6..0000000000 --- a/src/mainboard/via/epia-m850/Kconfig +++ /dev/null @@ -1,45 +0,0 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2011-2012 Alexandru Gagniuc -## -## This program is free software: you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation, either version 2 of the License, or -## (at your option) any later version. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## - -if BOARD_VIA_EPIA_M850 - -config BOARD_SPECIFIC_OPTIONS - def_bool y - select CPU_VIA_NANO - select NORTHBRIDGE_VIA_VX900 - select SUPERIO_FINTEK_F81865F - select HAVE_PIRQ_TABLE - select PIRQ_ROUTE - select HAVE_MP_TABLE - #select HAVE_OPTION_TABLE - #select HAVE_ACPI_TABLES - #select HAVE_ACPI_RESUME - #select BOARD_HAS_FADT - select BOARD_ROMSIZE_KB_512 - -config MAINBOARD_DIR - string - default via/epia-m850 - -config MAINBOARD_PART_NUMBER - string - default "EPIA-M850" - -config IRQ_SLOT_COUNT - int - default 13 - -endif # BOARD_VIA_EPIA_M850 diff --git a/src/mainboard/via/epia-m850/Kconfig.name b/src/mainboard/via/epia-m850/Kconfig.name deleted file mode 100644 index 5d6ed61060..0000000000 --- a/src/mainboard/via/epia-m850/Kconfig.name +++ /dev/null @@ -1,2 +0,0 @@ -config BOARD_VIA_EPIA_M850 - bool "EPIA-M850" diff --git a/src/mainboard/via/epia-m850/board_info.txt b/src/mainboard/via/epia-m850/board_info.txt deleted file mode 100644 index ba9ecf1a9e..0000000000 --- a/src/mainboard/via/epia-m850/board_info.txt +++ /dev/null @@ -1,7 +0,0 @@ -Category: mini -Board URL: http://www.viaembedded.com/en/products/boards/1290/1/EPIA-M850.html -ROM package: SOIC8 -ROM protocol: SPI -ROM socketed: n -Flashrom support: y -Release year: 2010 diff --git a/src/mainboard/via/epia-m850/devicetree.cb b/src/mainboard/via/epia-m850/devicetree.cb deleted file mode 100644 index 4dc7c278e5..0000000000 --- a/src/mainboard/via/epia-m850/devicetree.cb +++ /dev/null @@ -1,108 +0,0 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2011-2013 Alexandru Gagniuc -## -## This program is free software: you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation, either version 2 of the License, or -## (at your option) any later version. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## - -chip northbridge/via/vx900 # Northbridge - register "assign_pex_to_dp" = "0" - register "pcie_port1_2_lane_wide" = "1" - register "ext_int_route_to_pirq" = "'H'" - - device cpu_cluster 0 on # APIC cluster - chip cpu/via/nano # VIA NANO - device lapic 0 on end # APIC - end - end - device domain 0 on - device pci 0.0 on end # [0410] Host controller - device pci 0.1 on end # [1410] Error Reporting - device pci 0.2 on end # [2410] CPU Bus Control - device pci 0.3 on end # [3410] DRAM Bus Control - device pci 0.4 on end # [4410] Power Management - device pci 0.5 on # [5410] APIC+Traffic Control - chip drivers/generic/ioapic - register "have_isa_interrupts" = "0" - register "irq_on_fsb" = "1" - register "enable_virtual_wire" = "1" - register "base" = "(void *)0xfecc0000" - device ioapic 2 on end - end - end - device pci 0.6 off end # [6410] Scratch Registers - device pci 0.7 on end # [7410] V4 Link Control - device pci 1.0 on # [7122] VGA Chrome9 HD - ioapic_irq 2 INTA 0x28 - end - device pci 1.1 on # [9170] Audio Device - ioapic_irq 2 INTA 0x29 - end - device pci 3.0 on end # [a410] PEX1 - device pci 3.1 on end # [b410] PEX2 - device pci 3.2 on end # [c410] PEX3 - device pci 3.3 on end # [d410] PEX4 - device pci 3.4 on end # [e410] PCIE bridge - device pci b.0 on end # [a409] USB Device - device pci c.0 off end # [95d0] SDIO Host Controller - device pci d.0 off end # [9530] Memory Card controller - device pci f.0 on # [9001] SATA Controller - ioapic_irq 1 INTA 0x15 - end - device pci 10.0 on end # [3038] USB 1.1 - device pci 10.1 on end # [3038] USB 1.1 - device pci 10.2 on end # [3038] USB 1.1 - device pci 10.3 on end # [3038] USB 1.1 - device pci 10.4 on end # [3104] USB 2.0 - device pci 11.0 on # [8410] LPC Bus Control - chip drivers/generic/ioapic - register "have_isa_interrupts" = "1" - register "irq_on_fsb" = "1" - register "enable_virtual_wire" = "1" - register "base" = "(void *)0xfec00000" - device ioapic 1 on end - end - #chip drivers/generic/generic # DIMM 0 channel 1 - # device i2c 50 on end - #end - #chip drivers/generic/generic # DIMM 1 channel 1 - # device i2c 51 on end - #end - chip superio/fintek/f81865f # Super duper IO - device pnp 4e.0 off end # Floppy - device pnp 4e.3 off end # Parallel Port - device pnp 4e.4 off end # Hardware Monitor - device pnp 4e.5 off end # Keyboard not here - device pnp 4e.6 off end # GPIO - device pnp 4e.a off end # PME - device pnp 4e.10 on # COM1 - io 0x60 = 0x3f8 - irq 0x70 = 4 - end - device pnp 4e.11 on # COM2 - io 0x60 = 0x2f8 - irq 0x70 = 3 - end - device pnp 4e.12 on # COM3 - io 0x60 = 0x3e8 - irq 0x70 = 10 - end - device pnp 4e.13 on # COM4 - io 0x60 = 0x2e8 - irq 0x70 = 11 - end - end # superio/fintek/f81865f - end # LPC - device pci 11.7 on end # [a353] North-South control - device pci 14.0 on end # [3288] Azalia HDAC - end -end diff --git a/src/mainboard/via/epia-m850/irq_tables.c b/src/mainboard/via/epia-m850/irq_tables.c deleted file mode 100644 index 7aefc57b8e..0000000000 --- a/src/mainboard/via/epia-m850/irq_tables.c +++ /dev/null @@ -1,71 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2012 Alexandru Gagniuc - * - * This program is free software: you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include /* <- For memset */ - -#define _OFF 0x00 -#define ___OFF 0x0000 -#define LNKA 1 -#define LNKB 2 -#define LNKC 3 -#define LNKD 4 -#define LNKE 5 -#define LNKF 6 -#define LNKG 7 -#define LNKH 8 -#define BITMAP 0xdce0 -/* The link that carries the SATA interrupt has its own mask, just in case - * we want to make sure our SATA controller gets mapped to IRQ 14 */ -#define B_SATA BITMAP - -const struct irq_routing_table intel_irq_routing_table = { - PIRQ_SIGNATURE, /* u32 signature */ - PIRQ_VERSION, /* u16 version */ - 32 + 16 * 13, /* Max. number of devices on the bus */ - 0x00, /* Interrupt router bus */ - (0x11 << 3) | 0x0, /* Interrupt router dev */ - 0, /* IRQs devoted exclusively for PCI */ - PCI_VENDOR_ID_VIA, /* Vendor */ - PCI_DEVICE_ID_VIA_VX900_LPC, /* Device */ - 0, /* Miniport */ - { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */ - 0x19, /* Checksum (has to be set to some value that - * would give 0 after the sum of all bytes - * for this structure (including checksum). */ - { - /* bus, dev | fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */ - {0x00, (0x01 << 3) | 0x0, {{LNKH, BITMAP}, {LNKH, BITMAP}, {_OFF, ___OFF}, {_OFF, ___OFF}}, 0x0, 0x0}, - {0x00, (0x03 << 3) | 0x0, {{LNKH, BITMAP}, {LNKH, BITMAP}, {LNKH, BITMAP}, {LNKH, BITMAP}}, 0x0, 0x0}, - {0x00, (0x0a << 3) | 0x0, {{LNKA, BITMAP}, {LNKB, B_SATA}, {LNKC, BITMAP}, {LNKD, BITMAP}}, 0x0, 0x0}, - {0x00, (0x0b << 3) | 0x0, {{LNKA, BITMAP}, {_OFF, ___OFF}, {_OFF, ___OFF}, {_OFF, ___OFF}}, 0x0, 0x0}, - {0x00, (0x0c << 3) | 0x0, {{LNKA, BITMAP}, {_OFF, ___OFF}, {_OFF, ___OFF}, {_OFF, ___OFF}}, 0x0, 0x0}, - {0x00, (0x0d << 3) | 0x0, {{LNKA, BITMAP}, {_OFF, ___OFF}, {_OFF, ___OFF}, {_OFF, ___OFF}}, 0x0, 0x0}, - {0x00, (0x0f << 3) | 0x0, {{LNKB, B_SATA}, {_OFF, ___OFF}, {_OFF, ___OFF}, {_OFF, ___OFF}}, 0x0, 0x0}, - {0x00, (0x10 << 3) | 0x0, {{LNKA, BITMAP}, {LNKB, B_SATA}, {LNKC, BITMAP}, {LNKD, BITMAP}}, 0x0, 0x0}, - {0x00, (0x14 << 3) | 0x0, {{LNKB, B_SATA}, {_OFF, ___OFF}, {_OFF, ___OFF}, {_OFF, ___OFF}}, 0x0, 0x0}, - {0x01, (0x00 << 3) | 0x0, {{LNKH, BITMAP}, {LNKH, BITMAP}, {LNKH, BITMAP}, {LNKH, BITMAP}}, 0x1, 0x0}, - {0x02, (0x00 << 3) | 0x0, {{LNKH, BITMAP}, {LNKH, BITMAP}, {LNKH, BITMAP}, {LNKH, BITMAP}}, 0x2, 0x0}, - {0x03, (0x00 << 3) | 0x0, {{LNKH, BITMAP}, {LNKH, BITMAP}, {LNKH, BITMAP}, {LNKH, BITMAP}}, 0x0, 0x0}, - {0x04, (0x00 << 3) | 0x0, {{LNKH, BITMAP}, {LNKH, BITMAP}, {LNKH, BITMAP}, {LNKH, BITMAP}}, 0x0, 0x0}, - } -}; - -unsigned long write_pirq_routing_table(unsigned long addr) -{ - return copy_pirq_routing_table(addr, &intel_irq_routing_table); -} diff --git a/src/mainboard/via/epia-m850/mainboard.c b/src/mainboard/via/epia-m850/mainboard.c deleted file mode 100644 index 03699dba9f..0000000000 --- a/src/mainboard/via/epia-m850/mainboard.c +++ /dev/null @@ -1,107 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 Alexandru Gagniuc - * - * This program is free software: you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include - -#if CONFIG(VGA_ROM_RUN) - -#include -#include - -#include - -static int vx900_int15_handler(void) -{ - int res; - - printk(BIOS_DEBUG, "%s %0x\n", __func__, X86_AX & 0xffff); - /* Set AX return value here so we don't set it every time. Just set it - * to something else if the callback is unsupported */ - res = -1; - switch (X86_AX & 0xffff) { -#if 0 - case 0x5f01: - /* VGA POST - panel type */ - /* FIXME: Don't hardcode panel type */ - /* Panel Type Number */ - X86_CX = 0; - res = 0; - break; - case 0x5f02: - { - /* Boot device selection */ - X86_BL = INT15_5F02_BL_HWOPT_CRTCONN; - /* FIXME: or 0 ? */ - X86_BH = 0; // INT15_5F02_BH_TV_CONN_DEFAULT; - X86_EBX = 0; // INT15_5F02_EBX_HDTV_RGB; - X86_ECX = INT15_5F02_ECX_DISPLAY_CRT; - //X86_ECX |= INT15_5F02_ECX_TV_MODE_RGB; - //X86_ECX |= INT15_5F02_ECX_HDTV_1080P; - X86_DL = INT15_5F02_DL_TV_LAYOUT_DEFAULT; - res = 0; - break; - } -#endif - case 0x5f18: - X86_BL = vx900_int15_get_5f18_bl(); - res = 0; - break; -#if 0 - case 0x5f2a: - /* Get SSC Control Settings */ - /* FIXME: No idea what this does. Just disable this feature - * for now */ - X86_CX = INT15_5F2A_CX_SSC_ENABLE; - res = 0; - break; - case 0x5f2b: - /* Engine clock setting */ - /* FIXME: ECLK fixed 250MHz ? */ - X86_EBX = INT15_5F2B_EBX_ECLK_250MHZ; - break; -#endif - default: - printk(BIOS_DEBUG, "Unsupported INT15 call %04x!\n", - X86_AX & 0xffff); - X86_AX = 0; - res = -1; - break; - } - - if (res == 0) - X86_AX = 0x5f; - else - X86_AX = 0; - return X86_AX; -} -#endif - -static void mainboard_enable(struct device *dev) -{ - (void)dev; - -#if CONFIG(VGA_ROM_RUN) - printk(BIOS_DEBUG, "Installing INT15 handler...\n"); - mainboard_interrupt_handlers(0x15, &vx900_int15_handler); -#endif -} - -struct chip_operations mainboard_ops = { - CHIP_NAME("VIA EPIA-M850 Mainboard") - .enable_dev = mainboard_enable, -}; diff --git a/src/mainboard/via/epia-m850/romstage.c b/src/mainboard/via/epia-m850/romstage.c deleted file mode 100644 index 80693cde46..0000000000 --- a/src/mainboard/via/epia-m850/romstage.c +++ /dev/null @@ -1,98 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011-2012 Alexandru Gagniuc - * - * This program is free software: you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -/* - * Inspired from the EPIA-M700 - */ -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include -#include - -#define SERIAL_DEV PNP_DEV(0x4e, F81865F_SP1) - -/* cache_as_ram.inc jumps to here. */ -void main(unsigned long bist) -{ - u32 tolm; - - timestamp_init(timestamp_get()); - timestamp_add_now(TS_START_ROMSTAGE); - - /* First thing we need to do on the VX900, before anything else */ - vx900_enable_pci_config_space(); - - /* Serial console is easy to take care of */ - fintek_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); - console_init(); - printk(BIOS_DEBUG, "Console initialized.\n"); - - vx900_cpu_bus_interface_setup(); - - /* Be smart. Get this info */ - vx900_print_strapping_info(); - /* DEVEL helper */ - vx900_disable_auto_reboot(); - /* Halt if there was a built-in self test failure. */ - report_bist_failure(bist); - - /* Oh, almighty, give us the SMBUS */ - enable_smbus(); - - timestamp_add_now(TS_BEFORE_INITRAM); - /* Now we can worry about raminit. - * This board only has DDR3, so no need to worry about which DRAM type - * to use */ - dimm_layout dimms = { {0x50, 0x51, SPD_END_LIST} }; - vx900_init_dram_ddr3(&dimms); - timestamp_add_now(TS_AFTER_INITRAM); - - /* TODO: All these ram_checks are here to ensure we test most of the RAM - * below 4G. They should not be needed once VX900 raminit is stable */ - ram_check(0, 0x80); - ram_check(512 << 10, 0x80); - ram_check((1 << 20) - (1 << 10), 0x80); - ram_check((1 << 24), 0x80); - ram_check((512 + 256 - 1) << 20, 0x80); - ram_check(0x80c0000, 0x80); - tolm = vx900_get_tolm () << 20; - if (tolm > (1 * (u32) GiB)) - ram_check(1024 << 10, 0x80); - if (tolm > (2 * (u32) GiB)) - ram_check(2048 << 20, 0x80); - - printk(BIOS_DEBUG, "We passed RAM verify\n"); - - /* FIXME: read fb_size from CMOS, but until that is implemented, start - * from 512MB */ - vx900_set_chrome9hd_fb_size (512); - - /* We got RAM working, now we can write the timestamps to RAM */ - cbmem_recovery(0); - - /* FIXME: See if this is needed or take this out please */ - /* Disable Memcard and SDIO */ - pci_or_config8(LPC, 0x51, (1 << 7) | (1 << 4)); -} From 4c38ed3c38ac5ef0136bf5d5c893d8b71d82b531 Mon Sep 17 00:00:00 2001 From: Arthur Heymans Date: Tue, 19 Nov 2019 15:40:52 +0100 Subject: [PATCH 0285/1242] cpu/via/nano: Drop support MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Relocatable ramstage, postcar stage and C_ENVIRONMENT_BOOTBLOCK are now mandatory features, which this platform lacks. Change-Id: I6d9771e97619c3775f8325daf4b8453cd51d6571 Signed-off-by: Arthur Heymans Reviewed-on: https://review.coreboot.org/c/coreboot/+/36950 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki Reviewed-by: Angel Pons Reviewed-by: HAOUAS Elyes Reviewed-by: Nico Huber --- src/cpu/Makefile.inc | 1 - src/cpu/via/Kconfig | 1 - src/cpu/via/Makefile.inc | 1 - src/cpu/via/car/cache_as_ram.inc | 227 ------------------------------ src/cpu/via/nano/Kconfig | 42 ------ src/cpu/via/nano/Makefile.inc | 26 ---- src/cpu/via/nano/microcode_blob.c | 4 - src/cpu/via/nano/nano_init.c | 196 -------------------------- src/cpu/via/nano/update_ucode.c | 143 ------------------- src/cpu/via/nano/update_ucode.h | 65 --------- 10 files changed, 706 deletions(-) delete mode 100644 src/cpu/via/Kconfig delete mode 100644 src/cpu/via/Makefile.inc delete mode 100644 src/cpu/via/car/cache_as_ram.inc delete mode 100644 src/cpu/via/nano/Kconfig delete mode 100644 src/cpu/via/nano/Makefile.inc delete mode 100644 src/cpu/via/nano/microcode_blob.c delete mode 100644 src/cpu/via/nano/nano_init.c delete mode 100644 src/cpu/via/nano/update_ucode.c delete mode 100644 src/cpu/via/nano/update_ucode.h diff --git a/src/cpu/Makefile.inc b/src/cpu/Makefile.inc index bf857f8ffe..b80c30d72b 100644 --- a/src/cpu/Makefile.inc +++ b/src/cpu/Makefile.inc @@ -6,7 +6,6 @@ subdirs-y += amd subdirs-y += armltd subdirs-y += intel subdirs-y += ti -subdirs-y += via subdirs-$(CONFIG_ARCH_X86) += x86 subdirs-$(CONFIG_CPU_QEMU_X86) += qemu-x86 diff --git a/src/cpu/via/Kconfig b/src/cpu/via/Kconfig deleted file mode 100644 index d9a92300ca..0000000000 --- a/src/cpu/via/Kconfig +++ /dev/null @@ -1 +0,0 @@ -source src/cpu/via/nano/Kconfig diff --git a/src/cpu/via/Makefile.inc b/src/cpu/via/Makefile.inc deleted file mode 100644 index d68ff6501f..0000000000 --- a/src/cpu/via/Makefile.inc +++ /dev/null @@ -1 +0,0 @@ -subdirs-$(CONFIG_CPU_VIA_NANO) += nano diff --git a/src/cpu/via/car/cache_as_ram.inc b/src/cpu/via/car/cache_as_ram.inc deleted file mode 100644 index e4ca008f8b..0000000000 --- a/src/cpu/via/car/cache_as_ram.inc +++ /dev/null @@ -1,227 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include - -#define CacheSize CONFIG_DCACHE_RAM_SIZE -#define CacheBase CONFIG_DCACHE_RAM_BASE - - /* Save the BIST result. */ - movl %eax, %ebp - -CacheAsRam: - - /* Disable cache. */ - movl %cr0, %eax - orl $CR0_CacheDisable, %eax - movl %eax, %cr0 - invd - - /* Set the default memory type and enable fixed and variable MTRRs. */ - movl $MTRR_DEF_TYPE_MSR, %ecx - xorl %edx, %edx - movl $(MTRR_DEF_TYPE_EN | MTRR_DEF_TYPE_FIX_EN), %eax - wrmsr - - /* Clear all MTRRs. */ - xorl %edx, %edx - movl $all_mtrr_msrs, %esi - -clear_fixed_var_mtrr: - lodsl (%esi), %eax - testl %eax, %eax - jz clear_fixed_var_mtrr_out - - movl %eax, %ecx - xorl %eax, %eax - wrmsr - - jmp clear_fixed_var_mtrr - -all_mtrr_msrs: - /* fixed MTRR MSRs */ - .long MTRR_FIX_64K_00000 - .long MTRR_FIX_16K_80000 - .long MTRR_FIX_16K_A0000 - .long MTRR_FIX_4K_C0000 - .long MTRR_FIX_4K_C8000 - .long MTRR_FIX_4K_D0000 - .long MTRR_FIX_4K_D8000 - .long MTRR_FIX_4K_E0000 - .long MTRR_FIX_4K_E8000 - .long MTRR_FIX_4K_F0000 - .long MTRR_FIX_4K_F8000 - - /* var MTRR MSRs */ - .long MTRR_PHYS_BASE(0) - .long MTRR_PHYS_MASK(0) - .long MTRR_PHYS_BASE(1) - .long MTRR_PHYS_MASK(1) - .long MTRR_PHYS_BASE(2) - .long MTRR_PHYS_MASK(2) - .long MTRR_PHYS_BASE(3) - .long MTRR_PHYS_MASK(3) - .long MTRR_PHYS_BASE(4) - .long MTRR_PHYS_MASK(4) - .long MTRR_PHYS_BASE(5) - .long MTRR_PHYS_MASK(5) - .long MTRR_PHYS_BASE(6) - .long MTRR_PHYS_MASK(6) - .long MTRR_PHYS_BASE(7) - .long MTRR_PHYS_MASK(7) - - .long 0x000 /* NULL, end of table */ - -clear_fixed_var_mtrr_out: - movl $MTRR_PHYS_BASE(0), %ecx - xorl %edx, %edx - movl $(CacheBase | MTRR_TYPE_WRBACK), %eax - wrmsr - - movl $MTRR_PHYS_MASK(0), %ecx - /* This assumes we never access addresses above 2^36 in CAR. */ - movl $0x0000000f, %edx - movl $(~(CacheSize - 1) | MTRR_PHYS_MASK_VALID), %eax - wrmsr - - /* - * Enable write base caching so we can do execute in place (XIP) - * on the flash ROM. - */ - movl $MTRR_PHYS_BASE(1), %ecx - xorl %edx, %edx - /* - * IMPORTANT: The following calculation _must_ be done at runtime. See - * https://mail.coreboot.org/pipermail/coreboot/2010-October/060922.html - */ - movl $_program, %eax - andl $(~(CONFIG_XIP_ROM_SIZE - 1)), %eax - orl $MTRR_TYPE_WRBACK, %eax - wrmsr - - movl $MTRR_PHYS_MASK(1), %ecx - movl $0x0000000f, %edx - movl $(~(CONFIG_XIP_ROM_SIZE - 1) | MTRR_PHYS_MASK_VALID), %eax - wrmsr - - /* Set the default memory type and enable fixed and variable MTRRs. */ - /* TODO: Or also enable fixed MTRRs? Bug in the code? */ - movl $MTRR_DEF_TYPE_MSR, %ecx - xorl %edx, %edx - movl $(MTRR_DEF_TYPE_EN), %eax - wrmsr - - /* Enable cache. */ - movl %cr0, %eax - andl $(~(CR0_CacheDisable | CR0_NoWriteThrough)), %eax - movl %eax, %cr0 - - /* Read the range with lodsl. */ - cld - movl $CacheBase, %esi - movl %esi, %edi - movl $(CacheSize >> 2), %ecx - rep lodsl - - movl $CacheBase, %esi - movl %esi, %edi - movl $(CacheSize >> 2), %ecx - - /* Zero out the cache-as-ram area. */ - xorl %eax, %eax - rep stosl - - /* - * The key point of this CAR code is C7 cache does not turn into - * "no fill" mode, which is not compatible with general CAR code. - */ - - movl $(CacheBase + CacheSize - 4), %eax - movl %eax, %esp - - /* Restore the BIST result. */ - movl %ebp, %eax - - /* We need to set EBP? No need. */ - movl %esp, %ebp - pushl %eax /* BIST */ - call main - - /* - * TODO: Backup stack in CACHE_AS_RAM into MMX and SSE and after we - * get STACK up, we restore that. It is only needed if we - * want to go back. - */ - - /* We don't need CAR from now on. */ - - /* Disable cache. */ - movl %cr0, %eax - orl $CR0_CacheDisable, %eax - movl %eax, %cr0 - - /* Set the default memory type and enable variable MTRRs. */ - /* TODO: Or also enable fixed MTRRs? Bug in the code? */ - movl $MTRR_DEF_TYPE_MSR, %ecx - xorl %edx, %edx - movl $(MTRR_DEF_TYPE_EN), %eax - wrmsr - - /* Enable caching for 0..CACHE_TMP_RAMTOP. */ - movl $MTRR_PHYS_BASE(0), %ecx - xorl %edx, %edx - movl $(0x0 | MTRR_TYPE_WRBACK), %eax - wrmsr - - movl $MTRR_PHYS_MASK(0), %ecx - movl $0x0000000f, %edx /* AMD 40 bit 0xff */ - movl $(~(CACHE_TMP_RAMTOP - 1) | MTRR_PHYS_MASK_VALID), %eax - wrmsr - - /* Cache XIP_ROM area to speedup coreboot code. */ - movl $MTRR_PHYS_BASE(1), %ecx - xorl %edx, %edx - /* - * IMPORTANT: The following calculation _must_ be done at runtime. See - * https://mail.coreboot.org/pipermail/coreboot/2010-October/060922.html - */ - movl $_program, %eax - andl $(~(CONFIG_XIP_ROM_SIZE - 1)), %eax - orl $MTRR_TYPE_WRBACK, %eax - wrmsr - - movl $MTRR_PHYS_MASK(1), %ecx - xorl %edx, %edx - movl $(~(CONFIG_XIP_ROM_SIZE - 1) | MTRR_PHYS_MASK_VALID), %eax - wrmsr - - /* Enable cache. */ - movl %cr0, %eax - andl $(~(CR0_CacheDisable | CR0_NoWriteThrough)), %eax - movl %eax, %cr0 - invd - -__main: - post_code(POST_PREPARE_RAMSTAGE) - cld /* Clear direction flag. */ - - movl $CONFIG_RAMTOP, %esp - movl %esp, %ebp - call copy_and_run - -.Lhlt: - post_code(POST_DEAD_CODE) - hlt - jmp .Lhlt diff --git a/src/cpu/via/nano/Kconfig b/src/cpu/via/nano/Kconfig deleted file mode 100644 index 14acfd5662..0000000000 --- a/src/cpu/via/nano/Kconfig +++ /dev/null @@ -1,42 +0,0 @@ -## -## This file is part of the coreboot project. -## -## This program is free software: you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation, either version 2 of the License, or -## (at your option) any later version. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## - -config CPU_VIA_NANO - bool - -if CPU_VIA_NANO - -config CPU_SPECIFIC_OPTIONS - def_bool y - select ARCH_BOOTBLOCK_X86_32 - select ARCH_VERSTAGE_X86_32 - select ARCH_ROMSTAGE_X86_32 - select ARCH_RAMSTAGE_X86_32 - select UDELAY_TSC - select TSC_MONOTONIC_TIMER - select UNKNOWN_TSC_RATE - select MMX - select SSE2 - select SUPPORT_CPU_UCODE_IN_CBFS - select CAR_GLOBAL_MIGRATION - -config DCACHE_RAM_BASE - hex - default 0xffe00000 - -config DCACHE_RAM_SIZE - hex - default 0x8000 - -endif # CPU_VIA_NANO diff --git a/src/cpu/via/nano/Makefile.inc b/src/cpu/via/nano/Makefile.inc deleted file mode 100644 index 6fb699bee0..0000000000 --- a/src/cpu/via/nano/Makefile.inc +++ /dev/null @@ -1,26 +0,0 @@ -## -## This file is part of the coreboot project. -## -## This program is free software: you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation, either version 2 of the License, or -## (at your option) any later version. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## - -subdirs-y += ../../x86/tsc -subdirs-y += ../../x86/mtrr -subdirs-y += ../../x86/lapic -subdirs-y += ../../x86/cache -subdirs-y += ../../x86/smm - -ramstage-y += nano_init.c -ramstage-y += update_ucode.c - -cpu_microcode_bins += 3rdparty/blobs/cpu/via/nano/microcode.bin - -cpu_incs-y += $(src)/cpu/via/car/cache_as_ram.inc diff --git a/src/cpu/via/nano/microcode_blob.c b/src/cpu/via/nano/microcode_blob.c deleted file mode 100644 index 49866428d5..0000000000 --- a/src/cpu/via/nano/microcode_blob.c +++ /dev/null @@ -1,4 +0,0 @@ -unsigned int array[3588] = -{ -#include "../../../../3rdparty/blobs/cpu/via/nano/microcode.h" -}; diff --git a/src/cpu/via/nano/nano_init.c b/src/cpu/via/nano/nano_init.c deleted file mode 100644 index 61d82f12f2..0000000000 --- a/src/cpu/via/nano/nano_init.c +++ /dev/null @@ -1,196 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software: you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include "update_ucode.h" -#include -#include -#include -#include -#include -#include -#include -#include - -#define MODEL_NANO 0x2 -#define MODEL_NANO_3000_B0 0x8 -#define MODEL_NANO_3000_B2 0xa - -#define NANO_MYSTERIOUS_MSR 0x120e - -static void nano_finish_fid_vid_transition(void) -{ - - msr_t msr; - /* Wait until the power transition ends */ - int cnt = 0; - do { - udelay(16); - msr = rdmsr(IA32_PERF_STATUS); - cnt++; - if (cnt > 128) { - printk(BIOS_WARNING, - "Error while updating multiplier and voltage\n"); - break; - } - } while (msr.lo & ((1 << 16) | (1 << 17))); - - /* Print the new FID and Voltage */ - u8 cur_vid = (msr.lo >> 0) & 0xff; - u8 cur_fid = (msr.lo >> 8) & 0xff; - printk(BIOS_INFO, "New CPU multiplier: %dx\n", cur_fid); - printk(BIOS_INFO, "New Voltage ID : %dx\n", cur_vid); -} - -static void nano_set_max_fid_vid(void) -{ - msr_t msr; - /* Get voltage and frequency info */ - msr = rdmsr(IA32_PERF_STATUS); - u8 min_fid = (msr.hi >> 24); - u8 max_fid = (msr.hi >> 8) & 0xff; - u8 min_vid = (msr.hi >> 16) & 0xff; - u8 max_vid = (msr.hi >> 0) & 0xff; - u8 cur_vid = (msr.lo >> 0) & 0xff; - u8 cur_fid = (msr.lo >> 8) & 0xff; - - printk(BIOS_INFO, "CPU multiplier: %dx (min %dx; max %dx)\n", - cur_fid, min_fid, max_fid); - printk(BIOS_INFO, "Voltage ID : %dx (min %dx; max %dx)\n", - cur_vid, min_vid, max_vid); - - if ((cur_fid != max_fid) || (cur_vid != max_vid)) { - /* Set highest frequency and VID */ - msr.lo = msr.hi; - msr.hi = 0; - wrmsr(IA32_PERF_CTL, msr); - /* Wait for the transition to complete, otherwise, the CPU - * might reset itself repeatedly */ - nano_finish_fid_vid_transition(); - } - /* As a side note, if we didn't update the microcode by this point, the - * second PLL will not lock correctly. The clock will still be provided - * by the first PLL, and execution will continue normally, ___until___ - * the CPU switches PLL. Once that happens we will no longer have a - * working clock source, and the CPU will hang - * Moral of the story: update the microcode, or don't change FID - * This check is handled before calling nano_power() */ -} - -static void nano_power(void) -{ - msr_t msr; - /* Enable Powersaver */ - msr = rdmsr(IA32_MISC_ENABLE); - msr.lo |= (1 << 16); - wrmsr(IA32_MISC_ENABLE, msr); - - /* Enable 6 bit or 7-bit VRM support - * This MSR is not documented by VIA docs, other than setting these - * bits */ - msr = rdmsr(NANO_MYSTERIOUS_MSR); - msr.lo |= ((1 << 7) | (1 << 4)); - /* FIXME: Do we have a 6-bit or 7-bit VRM? - * set bit [5] for 7-bit, or don't set it for 6 bit VRM - * This will probably require a Kconfig option - * My board has a 7-bit VRM, so I can't test the 6-bit VRM stuff */ - msr.lo |= (1 << 5); - wrmsr(NANO_MYSTERIOUS_MSR, msr); - - /* Set the maximum frequency and voltage */ - nano_set_max_fid_vid(); - - /* Enable TM3 */ - msr = rdmsr(IA32_MISC_ENABLE); - msr.lo |= ((1 << 3) | (1 << 13)); - wrmsr(IA32_MISC_ENABLE, msr); - - u8 stepping = (cpuid_eax(0x1)) & 0xf; - if (stepping >= MODEL_NANO_3000_B0) { - /* Hello Nano 3000. The Terminator needs a CPU upgrade */ - /* Enable C1e, C2e, C3e, and C4e states */ - msr = rdmsr(IA32_MISC_ENABLE); - msr.lo |= ((1 << 25) | (1 << 26) | (1 << 31)); /* C1e, C2e, C3e */ - msr.hi |= (1 << 0); /* C4e */ - wrmsr(IA32_MISC_ENABLE, msr); - } - - /* Lock on Powersaver */ - msr = rdmsr(IA32_MISC_ENABLE); - msr.lo |= (1 << 20); - wrmsr(IA32_MISC_ENABLE, msr); -} - -static void nano_init(struct device *dev) -{ - struct cpuinfo_x86 c; - - get_fms(&c, dev->device); - - /* We didn't test this on the Nano 1000/2000 series, so warn the user */ - if (c.x86_mask < MODEL_NANO_3000_B0) { - printk(BIOS_EMERG, "WARNING: This CPU has not been tested. " - "Please report any issues encountered.\n"); - } - switch (c.x86_mask) { - case MODEL_NANO: - printk(BIOS_INFO, "VIA Nano"); - break; - case MODEL_NANO_3000_B0: - printk(BIOS_INFO, "VIA Nano 3000 rev B0"); - break; - case MODEL_NANO_3000_B2: - printk(BIOS_INFO, "VIA Nano 3000 rev B2"); - break; - default: - printk(BIOS_EMERG, "Stepping not recognized: %x\n", c.x86_mask); - } - printk(BIOS_INFO, "\n"); - - /* We only read microcode from CBFS. If we don't have any microcode in - * CBFS, we'll just get back with 0 updates. User choice FTW. */ - unsigned int n_updates = nano_update_ucode(); - - if (n_updates != 0){ - nano_power(); - } else { - /* Changing the frequency or voltage without first updating the - * microcode will hang the CPU, so just don't do it */ - printk(BIOS_EMERG, "WARNING: CPU Microcode not updated.\n" - " Will not change frequency, as this may hang the CPU.\n"); - } - - /* Turn on cache */ - x86_enable_cache(); - /* Set up Memory Type Range Registers */ - x86_setup_mtrrs(); - x86_mtrr_check(); - /* Enable the local CPU APICs */ - setup_lapic(); -} - -static struct device_operations cpu_dev_ops = { - .init = nano_init, -}; - -static const struct cpu_device_id cpu_table[] = { - {X86_VENDOR_CENTAUR, 0x06f2}, // VIA NANO 1000/2000 Series - {X86_VENDOR_CENTAUR, 0x06f8}, // VIA NANO 3000 rev B0 - {X86_VENDOR_CENTAUR, 0x06fa}, // VIA NANO 3000 rev B2 - {0, 0}, -}; - -static const struct cpu_driver driver __cpu_driver = { - .ops = &cpu_dev_ops, - .id_table = cpu_table, -}; diff --git a/src/cpu/via/nano/update_ucode.c b/src/cpu/via/nano/update_ucode.c deleted file mode 100644 index 373a7d8db8..0000000000 --- a/src/cpu/via/nano/update_ucode.c +++ /dev/null @@ -1,143 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software: you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include "update_ucode.h" -#include -#include -#include -#include -#include - -static ucode_update_status nano_apply_ucode(const nano_ucode_header *ucode) -{ - printk(BIOS_SPEW, "Attempting to apply microcode update\n"); - - msr_t msr; - /* Address of ucode block goes in msr.lo for 32-bit mode - * Now remember, we need to pass the address of the actual microcode, - * not the header. The header is just there to help us. */ - msr.lo = (unsigned int)(&(ucode->ucode_start)); - msr.hi = 0; - wrmsr(IA32_BIOS_UPDT_TRIG, msr); - - /* Let's see if we updated successfully */ - msr = rdmsr(MSR_UCODE_UPDATE_STATUS); - - return msr.lo & 0x07; -} - -static void nano_print_ucode_info(const nano_ucode_header *ucode) -{ - printk(BIOS_SPEW, "Microcode update information:\n"); - printk(BIOS_SPEW, "Name: %8s\n", ucode->name); - printk(BIOS_SPEW, "Date: %u/%u/%u\n", ucode->month, - ucode->day, ucode->year); -} - -static ucode_validity nano_ucode_is_valid(const nano_ucode_header *ucode) -{ - /* We must have a valid signature */ - if (ucode->signature != NANO_UCODE_SIGNATURE) - return NANO_UCODE_SIGNATURE_ERROR; - /* The size of the head must be exactly 12 double words */ - if ((ucode->total_size - ucode->payload_size) != NANO_UCODE_HEADER_SIZE) - return NANO_UCODE_WRONG_SIZE; - - /* How about a checksum ? Checksum must be 0 - * Two's complement done over the entire file, including the header */ - int i; - u32 check = 0; - u32 *raw = (void *) ucode; - for (i = 0; i < ((ucode->total_size) >> 2); i++) { - check += raw[i]; - } - if (check != 0) - return NANO_UCODE_CHECKSUM_FAIL; - /* Made it here huh? Then it looks valid to us. - * If there's anything else wrong, the CPU will reject the update */ - return NANO_UCODE_VALID; -} - -static void nano_print_ucode_status(ucode_update_status stat) -{ - switch (stat) - { - case UCODE_UPDATE_SUCCESS: - printk(BIOS_INFO, "Microcode update successful.\n"); - break; - case UCODE_UPDATE_FAIL: - printk(BIOS_ALERT, "Microcode update failed, bad environment." - "Update was not applied.\n"); - break; - case UCODE_UPDATE_WRONG_CPU: - printk(BIOS_ALERT, "Update not applicable to this CPU.\n"); - break; - case UCODE_INVALID_UPDATE_BLOCK: - printk(BIOS_ALERT, "Microcode block invalid." - "Update was not applied.\n"); - break; - default: - printk(BIOS_ALERT, "Unknown status. No update applied.\n"); - } -} - -unsigned int nano_update_ucode(void) -{ - size_t i; - unsigned int n_updates = 0; - u32 fms = cpuid_eax(0x1); - /* Considering we are running with eXecute-In-Place (XIP), there's no - * need to worry that accessing data from ROM will slow us down. - * Microcode data should be aligned to a 4-byte boundary, but CBFS - * already does that for us (Do you, CBFS?) */ - u32 *ucode_data; - size_t ucode_len; - - ucode_data = cbfs_boot_map_with_leak("cpu_microcode_blob.bin", - CBFS_TYPE_MICROCODE, &ucode_len); - /* Oops, did you forget to include the microcode ? */ - if (ucode_data == NULL) { - printk(BIOS_ALERT, "WARNING: No microcode file found in CBFS. " - "Aborting microcode updates\n"); - return 0; - } - - /* We might do a lot of loops searching for the microcode updates, but - * keep in mind, nano_ucode_is_valid searches for the signature before - * doing anything else. */ - for (i = 0; i < (ucode_len >> 2); /* don't increment i here */) - { - ucode_update_status stat; - const nano_ucode_header * ucode = (void *)(&ucode_data[i]); - if (nano_ucode_is_valid(ucode) != NANO_UCODE_VALID) { - i++; - continue; - } - /* Since we have a valid microcode, there's no need to search - * in this region, so we restart our search at the end of this - * microcode */ - i += (ucode->total_size >> 2); - /* Is the microcode compatible with our CPU? */ - if (ucode->applicable_fms != fms) continue; - /* For our most curious users */ - nano_print_ucode_info(ucode); - /* The meat of the pie */ - stat = nano_apply_ucode(ucode); - /* The user might want to know how the update went */ - nano_print_ucode_status(stat); - if (stat == UCODE_UPDATE_SUCCESS) n_updates++; - } - - return n_updates; -} diff --git a/src/cpu/via/nano/update_ucode.h b/src/cpu/via/nano/update_ucode.h deleted file mode 100644 index 7cf3f2871c..0000000000 --- a/src/cpu/via/nano/update_ucode.h +++ /dev/null @@ -1,65 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software: you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ -#ifndef __UPDATE_UCODE_H -#define __UPDATE_UCODE_H - -#include - -#define MSR_UCODE_UPDATE_STATUS 0x00001205 - -#define NANO_UCODE_SIGNATURE 0x53415252 -#define NANO_UCODE_HEADER_SIZE 0x30 - -/* These are values returned by the CPU after we attempt microcode updates. - * We care what these values are exactly, so we define them to be sure */ -typedef enum { - UCODE_UPDATE_NOT_ATTEMPTED = 0x0, - UCODE_UPDATE_SUCCESS = 0x1, - UCODE_UPDATE_FAIL = 0x2, - UCODE_UPDATE_WRONG_CPU = 0x3, - UCODE_INVALID_UPDATE_BLOCK = 0x4, -} ucode_update_status; - - -typedef enum { - NANO_UCODE_VALID = 0, /* We only care that valid == 0 */ - NANO_UCODE_SIGNATURE_ERROR, - NANO_UCODE_WRONG_SIZE, - NANO_UCODE_CHECKSUM_FAIL, -} ucode_validity; - -typedef struct { - u32 signature; /* NANO_UCODE_SIGNATURE */ - u32 update_revision; /* Revision of the update header */ - u16 year; /* Year of patch release */ - u8 day; /* Day of patch release */ - u8 month; /* Month of patch release */ - u32 applicable_fms; /* Fam/model/stepping to which ucode applies */ - u32 checksum; /* Two's complement checksum of ucode+header */ - u32 loader_revision; /* Revision of hardware ucode update loader*/ - u32 rfu_1; /* Reserved for future use */ - u32 payload_size; /* Size of the ucode payload only */ - u32 total_size; /* Size of the ucode, including header */ - char name[8]; /* ASCII string of ucode filename */ - u32 rfu_2; /* Reserved for future use */ - /* First double-word of the ucode payload - * Its address represents the beginning of the ucode update we need to - * send to the CPU */ - u32 ucode_start; - -} nano_ucode_header; - -unsigned int nano_update_ucode(void); - -#endif /* __UPDATE_UCODE_H */ From 0fd398a5a151fec4b3e5f257322b21a84ca48e87 Mon Sep 17 00:00:00 2001 From: Arthur Heymans Date: Tue, 19 Nov 2019 15:42:02 +0100 Subject: [PATCH 0286/1242] nb/via/vx900: Drop support MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Relocatable ramstage, postcar stage and C_ENVIRONMENT_BOOTBLOCK are now mandatory features, which this platform lacks. Change-Id: Ie971893da06fd3b1ac41dda398b1caeec3ee32db Signed-off-by: Arthur Heymans Reviewed-on: https://review.coreboot.org/c/coreboot/+/36951 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki Reviewed-by: Angel Pons Reviewed-by: HAOUAS Elyes Reviewed-by: Nico Huber --- src/northbridge/via/vx900/Kconfig | 48 - src/northbridge/via/vx900/Makefile.inc | 50 - src/northbridge/via/vx900/bootblock.c | 46 - src/northbridge/via/vx900/chip.h | 54 - src/northbridge/via/vx900/chrome9hd.c | 277 --- .../via/vx900/early_host_bus_ctl.c | 68 - src/northbridge/via/vx900/early_smbus.c | 193 -- src/northbridge/via/vx900/early_vx900.c | 130 -- src/northbridge/via/vx900/early_vx900.h | 74 - src/northbridge/via/vx900/lpc.c | 266 --- src/northbridge/via/vx900/memmap.c | 135 -- src/northbridge/via/vx900/northbridge.c | 345 ---- src/northbridge/via/vx900/pci_util.c | 39 - src/northbridge/via/vx900/pcie.c | 120 -- src/northbridge/via/vx900/raminit.h | 98 - src/northbridge/via/vx900/raminit_ddr3.c | 1671 ----------------- src/northbridge/via/vx900/romstrap.S | 56 - src/northbridge/via/vx900/romstrap.ld | 24 - src/northbridge/via/vx900/sata.c | 275 --- src/northbridge/via/vx900/traf_ctrl.c | 142 -- src/northbridge/via/vx900/vx900.h | 44 - 21 files changed, 4155 deletions(-) delete mode 100644 src/northbridge/via/vx900/Kconfig delete mode 100644 src/northbridge/via/vx900/Makefile.inc delete mode 100644 src/northbridge/via/vx900/bootblock.c delete mode 100644 src/northbridge/via/vx900/chip.h delete mode 100644 src/northbridge/via/vx900/chrome9hd.c delete mode 100644 src/northbridge/via/vx900/early_host_bus_ctl.c delete mode 100644 src/northbridge/via/vx900/early_smbus.c delete mode 100644 src/northbridge/via/vx900/early_vx900.c delete mode 100644 src/northbridge/via/vx900/early_vx900.h delete mode 100644 src/northbridge/via/vx900/lpc.c delete mode 100644 src/northbridge/via/vx900/memmap.c delete mode 100644 src/northbridge/via/vx900/northbridge.c delete mode 100644 src/northbridge/via/vx900/pci_util.c delete mode 100644 src/northbridge/via/vx900/pcie.c delete mode 100644 src/northbridge/via/vx900/raminit.h delete mode 100644 src/northbridge/via/vx900/raminit_ddr3.c delete mode 100644 src/northbridge/via/vx900/romstrap.S delete mode 100644 src/northbridge/via/vx900/romstrap.ld delete mode 100644 src/northbridge/via/vx900/sata.c delete mode 100644 src/northbridge/via/vx900/traf_ctrl.c delete mode 100644 src/northbridge/via/vx900/vx900.h diff --git a/src/northbridge/via/vx900/Kconfig b/src/northbridge/via/vx900/Kconfig deleted file mode 100644 index 8d95942866..0000000000 --- a/src/northbridge/via/vx900/Kconfig +++ /dev/null @@ -1,48 +0,0 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2011 Alexandru Gagniuc -## -## This program is free software: you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation, either version 2 of the License, or -## (at your option) any later version. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## - -config NORTHBRIDGE_VIA_VX900 - bool - select IOAPIC - select DRIVERS_GENERIC_IOAPIC - select HAVE_DEBUG_RAM_SETUP - select HAVE_DEBUG_SMBUS - select HAVE_CF9_RESET - select NO_RELOCATABLE_RAMSTAGE - -if NORTHBRIDGE_VIA_VX900 - -config MAX_PIRQ_LINKS - int - default 8 - -config MMCONF_BASE_ADDRESS - hex - default 0xe0000000 - -config MMCONF_BUS_NUMBER - int - default 256 - -config VGA_BIOS_ID - string - default "1106,7122" - -config BOOTBLOCK_NORTHBRIDGE_INIT - string - default "northbridge/via/vx900/bootblock.c" - -endif diff --git a/src/northbridge/via/vx900/Makefile.inc b/src/northbridge/via/vx900/Makefile.inc deleted file mode 100644 index 247cc249bf..0000000000 --- a/src/northbridge/via/vx900/Makefile.inc +++ /dev/null @@ -1,50 +0,0 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2011-2013 Alexandru Gagniuc -## -## This program is free software: you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation, either version 2 of the License, or -## (at your option) any later version. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## - -ifeq ($(CONFIG_NORTHBRIDGE_VIA_VX900),y) - -romstage-y += pci_util.c -romstage-y += early_smbus.c -romstage-y += early_vx900.c -romstage-y += early_host_bus_ctl.c -romstage-y += raminit_ddr3.c -romstage-y += memmap.c -romstage-y += ./../../../device/dram/ddr3.c -romstage-y += ./../../../southbridge/via/common/early_smbus_delay.c -romstage-y += ./../../../southbridge/via/common/early_smbus_is_busy.c -romstage-y += ./../../../southbridge/via/common/early_smbus_print_error.c -romstage-y += ./../../../southbridge/via/common/early_smbus_reset.c -romstage-y += ./../../../southbridge/via/common/early_smbus_wait_until_ready.c - -ramstage-y += pci_util.c -ramstage-y += pcie.c -ramstage-y += northbridge.c -ramstage-y += chrome9hd.c -ramstage-y += traf_ctrl.c -ramstage-y += sata.c -ramstage-y += lpc.c -ramstage-y += memmap.c - -# The buildsystem only includes this file if CONFIG_VGA is selected. -# We need to do some VGA I/O before the VGA can be initialized. We can make good -# use of some of the functions there, so include them unconditionally -ramstage-y += ./../../../drivers/pc80/vga/vga_io.c - - -bootblock-y += romstrap.ld -bootblock-y += romstrap.S - -endif diff --git a/src/northbridge/via/vx900/bootblock.c b/src/northbridge/via/vx900/bootblock.c deleted file mode 100644 index 6679cdb31b..0000000000 --- a/src/northbridge/via/vx900/bootblock.c +++ /dev/null @@ -1,46 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2017 Lubomir Rintel - * - * This program is free software: you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include - -#if CONFIG_ROM_SIZE == 0x80000 -# define ROM_DECODE_MAP 0x00 -#elif CONFIG_ROM_SIZE == 0x100000 -# define ROM_DECODE_MAP 0x40 -#elif CONFIG_ROM_SIZE == 0x180000 -# define ROM_DECODE_MAP 0x60 -#elif CONFIG_ROM_SIZE == 0x200000 -# define ROM_DECODE_MAP 0x70 -#elif CONFIG_ROM_SIZE == 0x280000 -# define ROM_DECODE_MAP 0x78 -#elif CONFIG_ROM_SIZE == 0x300000 -# define ROM_DECODE_MAP 0x7c -#elif CONFIG_ROM_SIZE == 0x380000 -# define ROM_DECODE_MAP 0x7e -#elif CONFIG_ROM_SIZE == 0x400000 -# define ROM_DECODE_MAP 0x7f -#else -# error "Bad CONFIG_ROM_SIZE" -#endif - -static void bootblock_northbridge_init(void) -{ - u8 reg; - - pci_io_read_config8(PCI_DEV(0, 0x11, 0), 0x41); - reg |= ROM_DECODE_MAP; - pci_io_write_config8(PCI_DEV(0, 0x11, 0), 0x41, reg); -} diff --git a/src/northbridge/via/vx900/chip.h b/src/northbridge/via/vx900/chip.h deleted file mode 100644 index 91a7a3d119..0000000000 --- a/src/northbridge/via/vx900/chip.h +++ /dev/null @@ -1,54 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2012 Alexandru Gagniuc - * - * This program is free software: you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef __VIA_VX900_CHIP_H__ -#define __VIA_VX900_CHIP_H__ - -struct northbridge_via_vx900_config { - /** - * \brief PCIe Lane[3:0] Function Select - * - * PCIe Lane3~Lane0 (PEXTX[3:0]P/VCC) can be used by the integrated - * graphic controller to output its display data. The PCIe lanes will - * be used to output DisplayPort data. - */ - u8 assign_pex_to_dp; - - /** - * \brief Lane Width for Root Port 1 - * - * Two PCIe lanes are used for Root port 1. Root port 2 is disabled. - */ - u8 pcie_port1_2_lane_wide; - - /** - * \brief PIRQ line to which to route the external interrupt - * - * The VX900 features an external interrupt which can be routed to any - * of the PIRQA->PIRQH lines. Usually, on-board devices are connected - * to the external interrupt. In some vendor BIOS's pirq table, this - * appears as link 9. - * - * Setting this line only affects the behavior of the integrated PIC. It - * has no effect on the IOAPIC. - * - * The value of this register must be a literal upper-case character - * from 'A' to 'H'. - */ - char ext_int_route_to_pirq; -}; - -#endif diff --git a/src/northbridge/via/vx900/chrome9hd.c b/src/northbridge/via/vx900/chrome9hd.c deleted file mode 100644 index fef53502f8..0000000000 --- a/src/northbridge/via/vx900/chrome9hd.c +++ /dev/null @@ -1,277 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2012 Alexandru Gagniuc - * - * This program is free software: you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include -#include -#include -#include - -#include "vx900.h" - -/** - * @file chrome9hd.c - * - * \brief Initialization for Chrome9HD integrated graphics adapters - * - * This takes care of the initialization we need to do before calling the VGA - * BIOS. The device is not documented in the VX900 datasheet. - * - * The device is documented in: - * Open Graphics Programming Manual - * Chrome9GraphicsHD Processor - * VX900 Series System Processor - * Part I: Graphics Core / 2D - * - * This document was released by VIA to the Xorg project, and is available at: - * - * - * STATUS: - * We do the minimal initialization described in VIA documents. Running the VGA - * option ROM does not get us a usable display. We configure the framebuffer and - * the IGP is able to use it. GRUB2 and linux are capable of getting a usable - * text console, which uses the monitor's native resolution (even 1920x1080). - * The graphical console (linux) does not work properly. - * @todo - * 1. Figure out what sequence we need to do to get the VGA BIOS running - * properly. Use the code provided by VIA and compare their sequence to ours, - * fill in any missing steps, etc. - * 2. Make BAR2 and the framebuffer use the same memory space. This is a feature - * called "Direct framebuffer access" which allows us to save memory space by - * setting BAR2 of the VGA to the location in memory of the framebuffer. This - * reduces the amount of PCI MMIO space we need below 4G, and is especially - * useful considering we only have 8GB (33 bits) of memory-mapped space. - */ - -/** - * vx900_int15 - * - * \brief INT15 helpers for Chrome9HD IGP - * - * The following are helpers for INT15 handlers for the VGA BIOS. The full set - * of INT15 callbacks is described in - * - * VIA/S3Graphics - * Video BIOS External Interface Specification for Chrome9 Series IGP - * VX900 Series - * - * This document is only available under NDA, however, the callbacks are very - * similar to other VIA/Intel IGP callbacks. - * - * Callback 0x5f18 is the most important one. It informs the VGA BIOS of the - * RAM speed and framebuffer size. The other callbacks seem to be optional. - * @{ - */ - -/** - * \brief Get X86_BL value for VGA INT15 function 5f18 - * - * Int15 5f18 lets the VGA BIOS know the framebuffer size and the memory speed. - * This handler is very important. If it is not implemented, the VGA BIOS will - * not work correctly. - * - * To use, just call this from the 15f18 handler, and place the return value in - * X86_BL - * - * @code{.c} - * case 0x5f18: - * X86_BX = vx900_int15_get_5f18_bl(); - * res = 0; - * break; - * @endcode - * - */ -u8 vx900_int15_get_5f18_bl(void) -{ - u8 reg8, ret; - struct device *dev; - /* - * BL Bit[7:4] - * Memory Data Rate (not to be confused with fCLK) - * 0000: 66MHz - * 0001: 100MHz - * 0010: 133MHz - * 0011: 200MHz (DDR200) - * 0100: 266MHz (DDR266) - * 0101: 333MHz (DDR333) - * 0110: 400MHz (DDR400) - * 0111: 533MHz (DDR I/II 533) - * 1000: 667MHz (DDR I/II 667) - * 1001: 800MHz (DDR3 800) - * 1010: 1066MHz (DDR3 1066) - * 1011: 1333MHz (DDR3 1333) - * Bit[3:0] - * N: Frame Buffer Size 2^N MB - */ - dev = pcidev_on_root(0, 3); - reg8 = pci_read_config8(dev, 0xa1); - ret = (u32) ((reg8 & 0x70) >> 4) + 2; - reg8 = pci_read_config8(dev, 0x90); - reg8 = ((reg8 & 0x07) + 3) << 4; - ret |= (u32) reg8; - - return ret; -} - -/** @} */ - -static void chrome9hd_set_sid_vid(u16 vendor, u16 device) -{ - vga_sr_write(0x36, vendor >> 8); /* SVID high byte */ - vga_sr_write(0x35, vendor & 0xff); /* SVID low byte */ - vga_sr_write(0x38, device >> 8); /* SID high byte */ - vga_sr_write(0x37, device & 0xff); /* SID low byte */ -} - -static void chrome9hd_handle_uma(struct device *dev) -{ - u8 fb_pow = vx900_get_chrome9hd_fb_pow(); - - if (fb_pow == 0) - return; - - /* Step 7 - Let GFX know the framebuffer size (through PCI and IOCTL) - * The size we set here affects the behavior of BAR2, and the amount of - * MMIO space it requests. The default is 512MB, so if we don't set this - * before reading the resources, we could waste space below 4G */ - pci_write_config8(dev, 0xb2, ((0xff << (fb_pow - 2)) & ~(1 << 7))); - vga_sr_write(0x68, (0xff << (fb_pow - 1))); - /* And also that the framebuffer is in the system, RAM */ - pci_or_config8(dev, 0xb0, 1 << 0); -} - -/** - * \brief Initialization sequence before running the VGA BIOS - * - * This is the initialization sequence described in: - * - * BIOS Porting Guide - * VX900 Series - * All-in-One System Processor - * - * This document is only available under NDA. - */ -static void chrome9hd_biosguide_init_seq(struct device *dev) -{ - struct device *mcu = dev_find_device(PCI_VENDOR_ID_VIA, - PCI_DEVICE_ID_VIA_VX900_MEMCTRL, 0); - struct device *host = dev_find_device(PCI_VENDOR_ID_VIA, - PCI_DEVICE_ID_VIA_VX900_HOST_BR, 0); - - /* Step 1 - Enable VGA controller */ - /* FIXME: This is the VGA hole @ 640k-768k, and the vga port io - * We need the port IO, but can we disable the memory hole? */ - pci_or_config8(mcu, 0xa4, (1 << 7)); /* VGA memory hole */ - - /* Step 2 - Forward MDA cycles to GFX */ - pci_or_config8(host, 0x4e, (1 << 1)); - - /* Step 3 - Enable GFX I/O space */ - pci_or_config8(dev, PCI_COMMAND, PCI_COMMAND_IO); - - /* Step 4 - Enable video subsystem */ - vga_enable_mask((1 << 0), (1 << 0)); - - /* FIXME: VGA IO Address Select. 3B5 or 3D5? */ - vga_misc_mask((1 << 0), (1 << 0)); - - /* Step 5 - Unlock accessing of IO space */ - vga_sr_write(0x10, 0x01); - - chrome9hd_handle_uma(dev); - - uint64_t gfx_base = get_uma_memory_base(); - if (gfx_base == 0) - die("uma_memory_base not set. Abandon ship!\n"); - - /* Step 8 - Enable memory base register on the GFX */ - vga_sr_write(0x6d, (gfx_base >> 21) & 0xff); /* base 28:21 */ - vga_sr_write(0x6e, (gfx_base >> 29) & 0xff); /* base 36:29 */ - vga_sr_write(0x6f, 0x00); /* base 43:37 */ - - /* Step 9 - Set SID/VID */ - chrome9hd_set_sid_vid(0x1106, 0x7122); - -} - -static void chrome9hd_init(struct device *dev) -{ - printk(BIOS_DEBUG, "======================================================\n"); - printk(BIOS_DEBUG, "== Chrome9 HD INIT\n"); - printk(BIOS_DEBUG, "======================================================\n"); - - chrome9hd_biosguide_init_seq(dev); - - /* Prime PLL FIXME: bad comment */ - vga_sr_mask(0x3c, 1 << 2, 1 << 2); - - /* FIXME: recheck; VGA IO Address Select. 3B5 or 3D5? */ - vga_misc_mask(1 << 0, 1 << 0); - - /* FIXME: recheck; Enable Base VGA 16 Bits Decode */ - - u32 fb_address = pci_read_config32(dev, PCI_BASE_ADDRESS_2); - fb_address &= ~0x0F; - if (!fb_address) { - printk(BIOS_WARNING, "Chrome9HD: No FB BAR assigned!\n"); - return; - } - - printk(BIOS_INFO, "Chrome: Using %dMB Framebuffer at 0x%08X.\n", - 256, fb_address); - - printk(BIOS_DEBUG, "Initializing VGA...\n"); - - pci_dev_init(dev); - - printk(BIOS_DEBUG, "Enable VGA console\n"); - - dump_pci_device(PCI_BDF(dev)); -} - -static void chrome9hd_enable(struct device *dev) -{ - struct device *mcu = dev_find_device(PCI_VENDOR_ID_VIA, - PCI_DEVICE_ID_VIA_VX900_MEMCTRL, 0); - /* FIXME: here? -=- ACLK 250MHz */ - pci_or_config8(mcu, 0xbb, 0x01); -} - -static void chrome9hd_disable(struct device *dev) -{ - struct device *mcu = dev_find_device(PCI_VENDOR_ID_VIA, - PCI_DEVICE_ID_VIA_VX900_MEMCTRL, 0); - /* Disable GFX - This step effectively renders the GFX inert - * It won't even show up as a PCI device during enumeration */ - pci_update_config8(mcu, 0xa1, (u8)~(1 << 7), 0); -} - -static struct device_operations chrome9hd_operations = { - .read_resources = pci_dev_read_resources, - .set_resources = pci_dev_set_resources, - .enable_resources = pci_dev_enable_resources, - .init = chrome9hd_init, - .disable = chrome9hd_disable, - .enable = chrome9hd_enable, - .ops_pci = 0, -}; - -static const struct pci_driver chrome9hd_driver __pci_driver = { - .ops = &chrome9hd_operations, - .vendor = PCI_VENDOR_ID_VIA, - .device = PCI_DEVICE_ID_VIA_VX900_VGA, -}; diff --git a/src/northbridge/via/vx900/early_host_bus_ctl.c b/src/northbridge/via/vx900/early_host_bus_ctl.c deleted file mode 100644 index 1ef29449fd..0000000000 --- a/src/northbridge/via/vx900/early_host_bus_ctl.c +++ /dev/null @@ -1,68 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2012 Alexandru Gagniuc - * - * This program is free software: you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include - -#include "early_vx900.h" - -static void vx900_cpu_bus_preram_setup(void) -{ - /* Faster CPU to DRAM Cycle */ - pci_update_config8(HOST_BUS, 0x50, ~0x0f, 0x08); - /* CPU Interface Control - Basic Options */ - pci_or_config8(HOST_BUS, 0x51, 0x6c); - /*CPU Interface Control - Advanced Options */ - pci_write_config8(HOST_BUS, 0x52, 0xc7); - /* Enable 8QW burst and 4QW request merging [4] and [2] - * and special mode for read cycles bit[3] */ - pci_or_config8(HOST_BUS, 0x54, (1 << 4) | (1 << 2) | (1 << 3)); - /* High priority upstream requests on V4 bus */ - pci_write_config8(HOST_BUS, 0x56, 0x03); - /* CPU to DRAM extra 1T access control */ - pci_or_config8(HOST_BUS, 0x59, (1 << 2)); - /* Queue reordering */ - pci_or_config8(HOST_BUS, 0x5f, (1 << 6)); - /* Only Write cycle of CPU->GFXCTL will flush the CPU->Memory FIFO */ - pci_or_config8(HOST_BUS, 0x98, 0x60); - /* 1T delay for data on CPU bus */ - pci_write_config8(HOST_BUS, 0x9e, 0x0e); - /* Arbitrate ownership of DRAM controller a few cycles earlier */ - pci_or_config8(HOST_BUS, 0x9f, (1 << 7)); - /* Write retire policy */ - pci_write_config8(HOST_BUS, 0x5d, 0xa2); - /* Occupancy timer */ - pci_write_config8(HOST_BUS, 0x53, 0x44); - /* Medium Threshold for Write Retire Policy - 6 requests */ - pci_or_config8(HOST_BUS, 0x56, 0x60); - /* Bandwidth timer */ - pci_write_config8(HOST_BUS, 0x5e, 0x44); -} - -/** - * \brief Configure the CPU to northbridge bus (formerly, FSB) - * - * Configure the CPU <-> host interface. This interface is complex and needs to - * be set up to operate properly. Configured parameters include bandwidth - * arbitration. This function does not, however, change the physical interface - * parameters, such as drive strength and signal timing. Instead, it assumes - * that those parameters were already configured correctly from the ROMSTRAP. - */ -void vx900_cpu_bus_interface_setup(void) -{ - vx900_cpu_bus_preram_setup(); - - dump_pci_device(HOST_BUS); -} diff --git a/src/northbridge/via/vx900/early_smbus.c b/src/northbridge/via/vx900/early_smbus.c deleted file mode 100644 index 5816926f59..0000000000 --- a/src/northbridge/via/vx900/early_smbus.c +++ /dev/null @@ -1,193 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 Alexandru Gagniuc - * - * This program is free software: you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include "early_vx900.h" -#include - -#include -#include -#include - -/** - * \brief SMBUS IO ports in relation to the base IO port - */ -#define SMBHSTSTAT(base) (u16)(u32)base + 0x0 -#define SMBSLVSTAT(base) (u16)(u32)base + 0x1 -#define SMBHSTCTL(base) (u16)(u32)base + 0x2 -#define SMBHSTCMD(base) (u16)(u32)base + 0x3 -#define SMBXMITADD(base) (u16)(u32)base + 0x4 -#define SMBHSTDAT0(base) (u16)(u32)base + 0x5 -#define SMBHSTDAT1(base) (u16)(u32)base + 0x6 -#define SMBBLKDAT(base) (u16)(u32)base + 0x7 -#define SMBSLVCTL(base) (u16)(u32)base + 0x8 -#define SMBTRNSADD(base) (u16)(u32)base + 0x9 -#define SMBSLVDATA (base) (u16)(u32)base + 0xa - -static void smbus_delays(int delays) -{ - while (delays--) - smbus_delay(); -} - -/** - * Read a byte from the SMBus. - * - * @param smbus_dev The PCI address of the SMBus device . - * @param addr The address location of the DIMM on the SMBus. - * @param offset The offset the data is located at. - */ -u8 smbus_read_byte(u32 smbus_dev, u8 addr, u8 offset) -{ - u8 val; - - /* Initialize SMBUS sequence */ - smbus_reset(smbus_dev); - /* Clear host data port. */ - outb(0x00, SMBHSTDAT0(smbus_dev)); - - smbus_wait_until_ready(smbus_dev); - smbus_delays(50); - - /* Actual addr to reg format. */ - addr = (addr << 1); - addr |= 1; /* read command */ - outb(addr, SMBXMITADD(smbus_dev)); - outb(offset, SMBHSTCMD(smbus_dev)); - /* Start transaction, byte data read. */ - outb(0x48, SMBHSTCTL(smbus_dev)); - smbus_wait_until_ready(smbus_dev); - - val = inb(SMBHSTDAT0(smbus_dev)); - return val; -} - -void enable_smbus(void) -{ - pci_devfn_t dev; - u8 reg8; - u32 smbus_dev = (u32) SMBUS_IO_BASE; - - /* Locate the Power Management control */ - dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_VIA, - PCI_DEVICE_ID_VIA_VX900_LPC), 0); - - if (dev == PCI_DEV_INVALID) { - die("Power Management Controller not found\n"); - } - - /* - * To use SMBus to manage devices on the system board, it is a must to - * enable SMBus function by setting - * PMU_RXD2[0] (SMBus Controller Enable) to 1. - * And set PMU_RXD0 and PMU_RXD1 (SMBus I/O Base) to an appropriate - * I/O port address, so that all registers in SMBus I/O port can be - * accessed. - */ - - reg8 = pci_read_config8(dev, 0xd2); - /* Enable SMBus controller */ - reg8 |= 1; - /* Set SMBUS clock from 128k source */ - reg8 |= 1 << 2; - pci_write_config8(dev, 0xd2, reg8); - - reg8 = pci_read_config8(dev, 0x94); - /* SMBUS clock from divider of 14.318 MHz */ - reg8 &= ~(1 << 7); - pci_write_config8(dev, 0x94, reg8); - - /* Set SMBus IO base */ - pci_write_config16(dev, 0xd0, SMBUS_IO_BASE); - - /* - * Initialize the SMBus sequence: - */ - /* Clear SMBus host status register */ - smbus_reset(smbus_dev); - /* Clear SMBus host data 0 register */ - outb(0x00, SMBHSTDAT0(smbus_dev)); - - /* Wait for SMBUS */ - smbus_wait_until_ready(smbus_dev); - -} - -static int spd_get_length(u8 spd_byte0) -{ - spd_byte0 &= 0xf; - - switch (spd_byte0) { - case 0x3: - return 256; - case 0x2: - return 176; - case 0x1: - return 128; - default: - break; - } - return 0; -} - -void spd_read(u8 addr, spd_raw_data spd) -{ - u8 reg; - int i, regs; - u32 smbus_dev = SMBUS_IO_BASE; - - reg = smbus_read_byte(smbus_dev, addr, 2); - if (reg != 0x0b) { - printk(BIOS_DEBUG, "SMBUS device %x not a DDR3 module\n", addr); - spd[2] = 0; - return; - } - - reg = smbus_read_byte(smbus_dev, addr, 0); - if ((regs = spd_get_length(reg)) == 0) { - printk(BIOS_INFO, "No DIMM present at %x\n", addr); - spd[2] = 0; - return; - } - - for (i = 0; i < regs; i++) - spd[i] = smbus_read_byte(smbus_dev, addr, i); -} - -void dump_spd_data(spd_raw_data spd) -{ - int len, i; - u8 reg; - - if ((len = spd_get_length(spd[0])) == 0) { - printk(BIOS_DEBUG, "Invalid SPD\n"); - return; - } - - /* - * I originally saw this way to present SPD data in code from VIA. I - * really liked the idea, so here it goes. - */ - printk(BIOS_DEBUG, " 00 01 02 03 04 05 06 07 07 09 0A 0B 0C 0D 0E 0F\n"); - printk(BIOS_DEBUG, "---+------------------------------------------------"); - for (i = 0; i < len; i++) { - reg = spd[i]; - if ((i & 0x0f) == 0) - printk(BIOS_DEBUG, "\n%.2x |", i); - printk(BIOS_DEBUG, " %.2x", reg); - } - printk(BIOS_DEBUG, "\n"); -} diff --git a/src/northbridge/via/vx900/early_vx900.c b/src/northbridge/via/vx900/early_vx900.c deleted file mode 100644 index e50b96812d..0000000000 --- a/src/northbridge/via/vx900/early_vx900.c +++ /dev/null @@ -1,130 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2012 Alexandru Gagniuc - * - * This program is free software: you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include "early_vx900.h" -#include -#include - -/** - * \brief Enable accessing of PCI configuration space for all devices. - * - * Enable accessing of D0F1 through D0F7, which would otherwise not be - * accessible. If MMCONF is enabled, configure it here. This is the first - * function that should be called in romstage. - */ -void vx900_enable_pci_config_space(void) -{ - /* MMCONF is not yet enabled, so we'll need to specify we want to do - * pci_io. We don't want to do pci_mmio until we enable it */ - /* Enable multifunction bit for northbridge. - * This enables the PCI configuration spaces of D0F1 to D0F7 to be - * accessed */ - pci_io_write_config8(HOST_CTR, 0x4f, 0x01); - - /* COOL, now enable MMCONF */ - u8 reg8 = pci_io_read_config8(TRAF_CTR, 0x60); - reg8 |= 3; - pci_io_write_config8(TRAF_CTR, 0x60, reg8); - - reg8 = CONFIG_MMCONF_BASE_ADDRESS >> 28; - pci_io_write_config8(TRAF_CTR, 0x61, reg8); -} - -/** - *\brief Prints information regarding the hardware strapping on VX900 - * - * Certain features on the VX900 are controlled by strapping pins which are - * hardwired on the mainboard. These values determine whether the ROM is on the - * SPI or LPC bus, or whether auto-reset is enabled. - * \n - * Having a feel for these values is important when trying to fix obscure - * problems found when porting a mainboard based on the VX900. - * \n - * These values are decoded and printed to the terminal. - */ -void vx900_print_strapping_info(void) -{ - u8 strap = pci_read_config8(SNMIC, 0x56); - - printk(BIOS_DEBUG, "VX900 strapping pins indicate that:\n"); - printk(BIOS_DEBUG, " ROM is on %s bus\n", - (strap & (1 << 0)) ? "SPI" : "LPC"); - printk(BIOS_DEBUG, " Auto reset is %s\n", - (strap & (1 << 1)) ? "disabled" : "enabled"); - printk(BIOS_DEBUG, " LPC FWH command is %s\n", - (strap & (1 << 2)) ? "enabled" : "disabled"); - printk(BIOS_DEBUG, " Debug link is is %s\n", - (strap & (1 << 4)) ? "enabled" : "disabled"); - printk(BIOS_DEBUG, " PCI master mode is %s\n", - (strap & (1 << 5)) ? "enabled" : "disabled"); -} - -/** - *\brief Disables the auto-reboot mechanism on VX900 - * - * The VX900 has an auto-reboot mechanism that can be enabled by a hardware - * strap. This mechanism can make development annoying, since we don't know if - * the reset was caused by a bug in coreboot, or by this mechanism. - */ -void vx900_disable_auto_reboot(void) -{ - if (pci_read_config8(SNMIC, 0x56) & (1 << 1)) { - printk(BIOS_DEBUG, "Auto-reboot is disabled in hardware\n"); - return; - } - /* Disable the GP3 timer, which is the root of all evil */ - pci_write_config8(LPC, 0x98, 0); - /* Yep, that's all it takes */ - printk(BIOS_DEBUG, "GP3 timer disabled." - " Auto-reboot should not give you any more trouble.\n"); -} - -/** - * \brief Disables 'shadowing' of system ROM - * - * Disable unnecessary shadowing of the ROM in the first 1MB of address space. - * coreboot runs in 32-bit mode from the start. Shadowing only gets in the way. - * This function frees the entire 640k-1M range for DRAM. VGA may still use - * the 640k-768k range, if enabled later. - */ -void vx900_disable_legacy_rom_shadow(void) -{ - pci_write_config8(MCU, 0x80, 0xff); /* LPC ROM 768k - 832k */ - pci_write_config8(MCU, 0x81, 0xff); /* LPC ROM 832k - 896k */ - pci_write_config8(MCU, 0x82, 0xff); /* LPC ROM 896k - 960k */ - /* LPC ROM 960k - 1M * SMRAM: 640k - 768k */ - pci_write_config8(MCU, 0x83, 0x31); - - /* Bits 6:0 are the ROM shadow on top of 4G, so leave those untouched */ - pci_update_config8(LPC, 0x41, (u8)~(1 << 7), 0); /* LPC ROM 896k - 960k */ - - pci_write_config8(SNMIC, 0x61, 0); /* 768k - 832k */ - pci_write_config8(SNMIC, 0x62, 0); /* 832k - 896k */ - pci_write_config8(SNMIC, 0x63, 0); /* 896k - 1M */ - pci_write_config8(SNMIC, 0x64, 0); /* 896k - 960k */ -} - -/** - * \brief Disables the VX900 integrated graphics controller - * - * Disable the graphics controller entirely. It will no longer be visible as a - * PCI device. - */ -void vx900_disable_gfx(void) -{ - /* Disable GFX */ - pci_update_config8(MCU, 0xa1, (u8)~(1 << 7), 0); -} diff --git a/src/northbridge/via/vx900/early_vx900.h b/src/northbridge/via/vx900/early_vx900.h deleted file mode 100644 index c1a823beaa..0000000000 --- a/src/northbridge/via/vx900/early_vx900.h +++ /dev/null @@ -1,74 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011-2012 Alexandru Gagniuc - * - * This program is free software: you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef EARLY_VX900_H -#define EARLY_VX900_H - -#include "raminit.h" -#include "vx900.h" - -#include - -/* North Module devices */ -#define HOST_CTR PCI_DEV(0, 0, 0) -#define ERR_REP PCI_DEV(0, 0, 1) -#define HOST_BUS PCI_DEV(0, 0, 2) -#define MCU PCI_DEV(0, 0, 3) -#define POWERMAN PCI_DEV(0, 0, 4) -#define TRAF_CTR PCI_DEV(0, 0, 5) -#define NSBIC PCI_DEV(0, 0, 7) - -#define GFX PCI_DEV(0, 1, 0) -#define HDMI PCI_DEV(0, 1, 0) - -#define PEXx PCI_DEV(0, 3, x) -#define PEX_CTR PCI_DEV(0, 3, 4) - -/* South Module devices */ -#define UARTx PCI_DEV(0, 0x0a, x) -#define USB_MASS PCI_DEV(0, 0x0b, 0) -#define SDIO PCI_DEV(0, 0x0c, 0) -#define CARD_RD PCI_DEV(0, 0x0d, 0) -#define SATA PCI_DEV(0, 0x0d, 0) -#define USBx PCI_DEV(0, 0x10, x) -#define USB_EHCI PCI_DEV(0, 0x10, 4) -#define LPC PCI_DEV(0, 0x11, 0) -#define PMU LPC -#define SNMIC PCI_DEV(0, 0x11, 7) -#define P2P PCI_DEV(0, 0x13, 0) -#define HDAC PCI_DEV(0, 0x14, 0) - -/* These control the behavior of raminit */ -#define RAMINIT_USE_HW_RXCR_CALIB 0 -#define RAMINIT_USE_HW_MRS_SEQ 0 - - -void enable_smbus(void); -void dump_spd_data(spd_raw_data spd); -void spd_read(u8 addr, spd_raw_data spd); - -void vx900_enable_pci_config_space(void); -void vx900_disable_legacy_rom_shadow(void); - -void vx900_print_strapping_info(void); -void vx900_disable_auto_reboot(void); - -void vx900_cpu_bus_interface_setup(void); - -void vx900_dram_set_gfx_resources(void); -void vx900_disable_gfx(void); - -#endif /* EARLY_VX900_H */ diff --git a/src/northbridge/via/vx900/lpc.c b/src/northbridge/via/vx900/lpc.c deleted file mode 100644 index fd4d5ad2a2..0000000000 --- a/src/northbridge/via/vx900/lpc.c +++ /dev/null @@ -1,266 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2012-2013 Alexandru Gagniuc - * - * This program is free software: you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include -#include -#include -#include -#include - -#include "vx900.h" -#include "chip.h" - -/** - * @file vx900/lpc.c - * - * STATUS: - * We do a fair bit of setup, and most of it seems to work fairly well. There - * are still a few FIXME items here and there, but overall, this code hasn't - * been touched much from its initial 2012 version to 2013, when it was revived. - * - * We do the IOAPIC setup with the assumption that it is declared in the - * mainboard's devicetree.cb. We cannot use the IOAPIC however. The interrupts - * do not make it to the CPU. This issue is still under investigation. - * - * We also route PIRQs with CONFIG_PIRQ_ROUTE. This is currently the only way to - * get interrupts working. - * - * On the VX900, the keyboard can be connected directly to the chipset - * (referenced as "internal keyboard" in the documents). As long as that is the - * case (not connected to the superIO), and we disable the superIO keyboard LDN, - * it will work, but perhaps this should be more configurable. - */ - -static void vx900_lpc_misc_stuff(struct device *dev) -{ - char extint; - u8 val; - struct northbridge_via_vx900_config *nb = (void *)dev->chip_info; - - /* GPIO 11,10 to SATALED [1,0] */ - pci_or_config8(dev, 0xe4, 1 << 0); - - /* Route the external interrupt line */ - extint = nb->ext_int_route_to_pirq; - if (extint < 'A' || extint > 'H') { - printk(BIOS_WARNING, "Invalid PIRQ%c for external interrupt\n", - extint); - } else { - printk(BIOS_INFO, "Routing external interrupt to PIRQ%c\n", - extint); - val = extint - 'A'; - val |= (1 << 3); /* bit3 enables the external int */ - pci_update_config8(dev, 0x55, ~0xf, val); - - } -} - -static void vx900_lpc_dma_setup(struct device *dev) -{ - /* These are the steps recommended by VIA in order to get DMA running */ - - /* Enable Positive South Module PCI Cycle Decoding */ - /* FIXME: Setting this seems to hang our system */ - - /* Positive decoding for ROM + APIC + On-board IO ports */ - pci_or_config8(dev, 0x6c, (1 << 2) | (1 << 3) | (1 << 7)); - /* Enable DMA channels. BIOS guide recommends DMA channel 2 off */ - pci_write_config8(dev, 0x53, 0xfb); - /* Disable PCI/DMA Memory Cycles Output to PCI Bus */ - pci_update_config8(dev, 0x5b, ~(1 << 5), 0); - /* DMA bandwidth control - Improved bandwidth */ - pci_write_config8(dev, 0x53, 0xff); - /* ISA Positive Decoding control */ - pci_write_config8(dev, 0x6d, 0xdf); - pci_write_config8(dev, 0x6e, 0x98); - pci_write_config8(dev, 0x6f, 0x30); -} - -/** - *\brief VX900: Set up the south module IOAPIC (for the ISA/LPC bus) - * - * Enable the IOAPIC in the south module, and properly set it up. - * \n - * This is the hardware specific initialization for the IOAPIC, and complements - * the setup done by the generic IOAPIC driver. In order for the IOAPIC to work - * properly, it _must_ be declared in devicetree.cb . - * \n - * We are assuming this is called before the drivers/generic/ioapic code, - * which should be the case if devicetree.cb is set up properly. - */ -static void vx900_lpc_ioapic_setup(struct device *dev) -{ - /* Find the IOAPIC, and make sure it's set up correctly in devicetree.cb - * If it's not, then the generic ioapic driver will not set it up - * correctly, and the MP table will not be correctly generated */ - struct device *ioapic; - for (ioapic = dev->next; ioapic; ioapic = ioapic->next) { - if (ioapic->path.type == DEVICE_PATH_IOAPIC) - break; - } - - /* You did put an IOAPIC in devicetree.cb, didn't you? */ - if (ioapic == 0) { - /* We don't have enough info to set up the IOAPIC */ - printk(BIOS_ERR, "ERROR: South module IOAPIC not found. " - "Check your devicetree.cb\n"); - return; - } - - /* Found an IOAPIC, now we need to make sure it's the right one */ - ioapic_config_t *config = (ioapic_config_t *) ioapic->chip_info; - if (!config->have_isa_interrupts) { - /* Umh, is this the right IOAPIC ? */ - printk(BIOS_ERR, "ERROR: South module IOAPIC not carrying ISA " - "interrupts. Check your devicetree.cb\n"); - printk(BIOS_ERR, "Will not initialize this IOAPIC.\n"); - return; - } - - /* The base address of this IOAPIC _must_ be at 0xfec00000. - * Don't move this value to a #define, as people might think it's - * configurable. It is not. */ - const void *base = config->base; - if (base != (void *)0xfec00000) { - printk(BIOS_ERR, "ERROR: South module IOAPIC base should be at " - "0xfec00000\n but we found it at %p\n", base); - return; - } - - printk(BIOS_DEBUG, "VX900 LPC: Setting up the south module IOAPIC.\n"); - /* Enable IOAPIC - * So much work for one line of code. Talk about bloat :) - * The 8259 PIC should still work even if the IOAPIC is enabled, so - * there's no crime in enabling the IOAPIC here. */ - pci_or_config8(dev, 0x58, 1 << 6); -} - -static void vx900_lpc_interrupt_stuff(struct device *dev) -{ - /* Enable setting trigger mode through 0x4d0, and 0x4d1 ports - * And enable I/O recovery time */ - pci_or_config8(dev, 0x40, (1 << 2) | (1 << 6)); - /* Set serial IRQ frame width to 6 PCI cycles (recommended by VIA) - * And enable serial IRQ */ - pci_update_config8(dev, 0x52, ~(3 << 0), (1 << 3) | (1 << 0)); - - /* Disable IRQ12 storm FIXME: bad comment */ - pci_update_config8(dev, 0x51, ~(1 << 2), 0); - - pci_write_config8(dev, 0x4c, (1 << 6)); - - /* FIXME: Do we really need this? SeaBIOS/linux runs fine without it. - * Is this something the payload/OS should do, or is it safe for us to - * do it? */ - /* Get the IRQs up and running */ - setup_i8259(); - - vx900_lpc_dma_setup(dev); - - /* The IOAPIC is special, and we treat it separately */ - vx900_lpc_ioapic_setup(dev); -} - -static void vx900_lpc_init(struct device *dev) -{ - vx900_lpc_interrupt_stuff(dev); - vx900_lpc_misc_stuff(dev); - dump_pci_device(PCI_BDF(dev)); -} - -static void vx900_lpc_read_resources(struct device *dev) -{ - struct resource *res; - pci_dev_read_resources(dev); - - /* MMIO space */ - res = new_resource(dev, VX900_MMCONFIG_MBAR); - res->size = 0x1000; - res->align = 12; - res->gran = 12; - res->limit = 0xffffffff; - res->flags = IORESOURCE_MEM | IORESOURCE_RESERVE; - - /* SPI controller */ - res = new_resource(dev, IOINDEX_SUBTRACTIVE(0, 0)); - res->size = 0x8; - res->align = 12; - res->gran = 12; - res->limit = 0xffffffff; - res->flags = IORESOURCE_MEM | IORESOURCE_RESERVE; -} - -static void vx900_lpc_set_resources(struct device *dev) -{ - struct resource *mmio, *spi; - u32 reg; - - mmio = find_resource(dev, VX900_MMCONFIG_MBAR); - if (mmio) { - report_resource_stored(dev, mmio, ""); - mmio->flags |= IORESOURCE_STORED; - reg = pci_read_config32(dev, VX900_MMCONFIG_MBAR); - reg &= 0xff000000; - reg |= mmio->base >> 8; - pci_write_config32(dev, VX900_MMCONFIG_MBAR, reg); - - spi = find_resource(dev, IOINDEX_SUBTRACTIVE(0, 0)); - if (spi) { - report_resource_stored(dev, spi, ""); - spi->flags |= IORESOURCE_STORED; - /* Set base and the enable bit. */ - ((u32*)(uintptr_t)mmio->base)[0] = (spi->base | 0x01); - } - } - pci_dev_set_resources(dev); -} - -static struct device_operations vx900_lpc_ops = { - .read_resources = vx900_lpc_read_resources, - .set_resources = vx900_lpc_set_resources, - .enable_resources = pci_dev_enable_resources, - .init = vx900_lpc_init, - .scan_bus = scan_static_bus, -}; - -static const struct pci_driver lpc_driver __pci_driver = { - .ops = &vx900_lpc_ops, - .vendor = PCI_VENDOR_ID_VIA, - .device = PCI_DEVICE_ID_VIA_VX900_LPC, -}; - -#if CONFIG(PIRQ_ROUTE) -void pirq_assign_irqs(const u8 *pirq) -{ - struct device *lpc; - - lpc = dev_find_device(PCI_VENDOR_ID_VIA, - PCI_DEVICE_ID_VIA_VX900_LPC, 0); - - /* Take care of INTA -> INTD */ - pci_update_config8(lpc, 0x55, (u8)~(0xf << 4), pirq[0] << 4); - pci_write_config8(lpc, 0x56, pirq[1] | (pirq[2] << 4)); - pci_write_config8(lpc, 0x57, pirq[3] << 4); - - /* Enable INTE -> INTH to be on separate IRQs */ - pci_or_config8(lpc, 0x46, 1 << 4); - /* Now do INTE -> INTH */ - pci_write_config8(lpc, 0x44, pirq[4] | (pirq[5] << 4)); - pci_write_config8(lpc, 0x45, pirq[6] | (pirq[7] << 4)); -} -#endif diff --git a/src/northbridge/via/vx900/memmap.c b/src/northbridge/via/vx900/memmap.c deleted file mode 100644 index 3121d7406e..0000000000 --- a/src/northbridge/via/vx900/memmap.c +++ /dev/null @@ -1,135 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2012 Alexandru Gagniuc - * Copyright (C) 2018 Lubomir Rintel - * - * This program is free software: you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#define __SIMPLE_DEVICE__ - -#include -#include -#include -#include -#include - -#include "vx900.h" - -#define MCU PCI_DEV(0, 0, 3) - -#define CHROME_9_HD_MIN_FB_SIZE 8 -#define CHROME_9_HD_MAX_FB_SIZE 512 - -/* Helper to determine the framebuffer size */ -void vx900_set_chrome9hd_fb_size(u32 size_mb) -{ - u8 reg8, ranksize; - u32 tom_mb, max_size_mb; - int i; - - /* The minimum framebuffer size is 8MB. */ - size_mb = MAX(size_mb, CHROME_9_HD_MIN_FB_SIZE); - - /* - * We have two limitations on the maximum framebuffer size: - * 1) (Sanity) No more that 1/4 of system RAM - * 2) (Hardware limitation) No larger than DRAM in last rank - * Check both of these limitations and apply them to our framebuffer */ - tom_mb = (pci_read_config16(MCU, 0x88) & 0x07ff) << (24 - 20); - max_size_mb = tom_mb >> 2; - if (size_mb > max_size_mb) { - printk(BIOS_ALERT, "The framebuffer size of %dMB is larger" - " than 1/4 of available memory.\n" - " Limiting framebuffer to %dMB\n", size_mb, max_size_mb); - size_mb = max_size_mb; - } - - /* Now handle limitation #2 - * Look at the ending address of the memory ranks, from last to first, - * until we find one that is not zero. That is our last rank, and its - * size is the limit of our framebuffer. */ - /* FIXME: This has a bug. If we remap memory above 4G, we consider the - * memory hole as part of our RAM. Thus if we install 3G, with a TOLM of - * 2.5G, our TOM will be at 5G and we'll assume we have 5G RAM instead - * of the actual 3.5G */ - for (i = VX900_MAX_MEM_RANKS - 1; i > -1; i--) { - reg8 = pci_read_config8(MCU, 0x40 + i); - if (reg8 == 0) - continue; - /* We've reached the last populated rank */ - ranksize = reg8 - pci_read_config8(MCU, 0x48 + i); - max_size_mb = ranksize << 6; - /* That's it. We got what we needed. */ - break; - } - if (size_mb > max_size_mb) { - printk(BIOS_ALERT, "The framebuffer size of %dMB is larger" - " than size of the last DRAM rank.\n" - " Limiting framebuffer to %dMB\n", size_mb, max_size_mb); - size_mb = max_size_mb; - } - - /* Now round down the framebuffer size to the closest power of 2 */ - if (size_mb == 0) - die("Framebuffer size is 0\n"); - - int fb_pow = log2(size_mb); - - size_mb = 1U << fb_pow; - - if (size_mb < CHROME_9_HD_MIN_FB_SIZE || size_mb > CHROME_9_HD_MAX_FB_SIZE) - die("Framebuffer size %u is out of range\n", size_mb); - - pci_update_config8(MCU, 0xa1, ~(7 << 4), (fb_pow - 2) << 4); -} - -/* Gets the configured framebuffer size as a power of 2 */ -u8 vx900_get_chrome9hd_fb_pow(void) -{ - u8 fb_pow = (pci_read_config8(MCU, 0xa1) >> 4) & 7; - - if (fb_pow > 0) - fb_pow += 2; - - return fb_pow; -} - -/* Gets the configured framebuffer size in MB */ -u32 vx900_get_chrome9hd_fb_size(void) -{ - u8 size = vx900_get_chrome9hd_fb_pow(); - - if (size == 0) - return 0; - - return 1 << size; -} - -u32 vx900_get_tolm(void) -{ - return (pci_read_config16(MCU, 0x84) & 0xfff0) >> 4; -} - -void *cbmem_top_chipset(void) -{ - uintptr_t tolm; - uintptr_t fb_size; - - tolm = vx900_get_tolm (); - fb_size = vx900_get_chrome9hd_fb_size (); - - if (tolm > 0xfc0 || tolm <= 0x3ff || fb_size == 0x0) - return NULL; - - return (void *)((tolm - fb_size) << 20); -} diff --git a/src/northbridge/via/vx900/northbridge.c b/src/northbridge/via/vx900/northbridge.c deleted file mode 100644 index 260bd3de05..0000000000 --- a/src/northbridge/via/vx900/northbridge.c +++ /dev/null @@ -1,345 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2012 Alexandru Gagniuc - * - * This program is free software: you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include "vx900.h" -#include "chip.h" - -#include -#include -#include -#include -#include -#include -#include -#include - -#define RAM_4GB (((u64)1) << 32) - -static uint64_t uma_memory_base = 0; -static uint64_t uma_memory_size = 0; - -/** - * @file vx900/northbridge.c - * - * STATUS: Pretty good - * One thing that needs to be thoroughly tested is the remap above 4G logic. - * Unfortunately, while we cannot initialize odd ranks, our testing - * possibilities are somewhat limited. A point of failure that is not covered is - * when the amount of RAM and PCI config space added up exceeds 8GB. The - * remapping mechanism will overflow, the effects of which are unknown. - */ - -void do_board_reset(void) -{ - system_reset(); -} - -uint64_t get_uma_memory_base(void) -{ - printk(BIOS_DEBUG, "UMA base 0x%.8llx (%lluMB)\n", uma_memory_base, - uma_memory_base >> 20); - printk(BIOS_DEBUG, "UMA size 0x%.8llx (%lluMB)\n", uma_memory_size, - uma_memory_size >> 20); - return uma_memory_base; -} - -static u64 vx900_get_top_of_ram(struct device *mcu) -{ - u16 reg16; - /* The last valid DRAM address is computed by the MCU - * One issue might be if we have a hole in the rank mappings, so that - * virtual ranks are not mapped successively in the linear address space - * (Ex: rank 0 mapped 0-1G, rank 1 mapped 2G-3G) - * We don't do this awkward mapping in RAM init, so we don't worry about - * it here, but it is something to keep in mind if having RAM issues */ - reg16 = pci_read_config16(mcu, 0x88) & 0x07ff; - return (u64) reg16 << 24; -} - -/* - * This guy is meant to go away, but for now, leave it in so that we can see - * if the logic to remap RAM above 4G has errors. - */ -static void killme_debug_4g_remap_reg(u32 reg32) -{ - if (reg32 & (1 << 0)) - printk(BIOS_DEBUG, "Mem remapping enabled\n"); - u64 remapstart = (reg32 >> 2) & 0x3ff; - u64 remapend = (reg32 >> 14) & 0x3ff; - remapstart <<= 26; - remapend <<= 26; - printk(BIOS_DEBUG, "Remapstart %lld(MB)\n", remapstart >> 20); - printk(BIOS_DEBUG, "Remapend %lld(MB)\n", remapend >> 20); -} - -/** - * \brief Remap low memory colliding with PCI MMIO space, above 4G - * - * @param mcu The memory controller - * @param tolm Top of low memory. - * - * @return The new top of memory. - */ -static u64 vx900_remap_above_4g(struct device *mcu, u32 tolm) -{ - size_t i; - u8 reg8, start8, end8, start, end; - u16 reg16; - u32 reg32; - u64 tor, newtor, chunk; - - /* - * The remapping mechanism works like this: - * - * - Choose the top of low memory. - * This becomes the "remap from" - * - Choose a chunk above 4G where to remap. - * This becomes "remap to" - * - Choose a chunk above 4G where to end the remapping. - * This becomes "remap until" - * - * This remaps a "chunk" of memory where we want to. - * sizeof(chunk) = until - to; - * - * Therefore the memory region from "from" to " from + sizeof(chunk)" - * becomes accessible at "to" to "until" - */ - if (tolm >= vx900_get_top_of_ram(mcu)) { - printk(BIOS_DEBUG, "Nothing to remap\n"); - return 0; - } - - /* This is how the Vendor BIOS. Keep it for comparison for now */ - killme_debug_4g_remap_reg(0x00180141); - /* We can remap with a granularity of 64MB, so align tolm */ - tolm &= ~((64 * MiB) - 1); - - /* The "start remapping from where ?" register */ - reg16 = ((tolm >> 20) & 0xfff) << 4; - pci_update_config16(mcu, 0x84, (u16)~0xfff0, reg16); - - /* Find the chunk size */ - tor = vx900_get_top_of_ram(mcu); - printk(BIOS_DEBUG, "Top of RAM %lldMB\n", tor >> 20); - - if (tor < RAM_4GB) { - chunk = tor - tolm; - newtor = RAM_4GB + chunk; - } else { - chunk = (RAM_4GB - tolm); - newtor = tor + chunk; - } - printk(BIOS_DEBUG, "New top of RAM %lldMB\n", newtor >> 20); - - reg8 = tolm >> 26; - /* Which rank does the PCI TOLM fall on? */ - for (i = 0; i < VX900_MAX_MEM_RANKS; i++) { - end8 = pci_read_config8(mcu, 0x40 + i); - if (reg8 > end8) - continue; - start8 = pci_read_config8(mcu, 0x48 + i); - if (reg8 <= start8) - continue; - printk(BIOS_DEBUG, "Address %x falls on rank %zu\n", tolm, i); - break; - } - - for (; i < VX900_MAX_MEM_RANKS; i++) { - start = pci_read_config8(mcu, 0x48 + i); - end = pci_read_config8(mcu, 0x40 + i); - - if (end == 0) { - printk(BIOS_DEBUG, "Huh? rank %zu empty?\n", i); - continue; - } - - if (end < (tolm >> 26)) { - printk(BIOS_DEBUG, "Huh? rank %zu don't need remap?\n", - i); - continue; - } - - printk(BIOS_DEBUG, "Physical rank %u is mapped to\n" - " Start address: 0x%.10llx (%dMB)\n" - " End address: 0x%.10llx (%dMB)\n", - (int)i, - ((u64) start << 26), (start << (26 - 20)), - ((u64) end << 26), (end << (26 - 20))); - - if (end < (RAM_4GB >> 26)) - end = (RAM_4GB >> 26); - - if (end >= (tolm >> 26)) - end += chunk >> 26; - - if (start > (tolm >> 26)) - start += chunk >> 26; - - pci_write_config8(mcu, 0x48 + i, start); - pci_write_config8(mcu, 0x40 + i, end); - - printk(BIOS_DEBUG, "ReMapped Physical rank %u, to\n" - " Start address: 0x%.10llx (%dMB)\n" - " End address: 0x%.10llx (%dMB)\n", - (int)i, - ((u64) start << 26), (start << (26 - 20)), - ((u64) end << 26), (end << (26 - 20))); - } - - /* The "remap to where?" register */ - reg32 = ((MAX(tor, RAM_4GB) >> 26) & 0x3ff) << 2; - /* The "remap until where?" register */ - reg32 |= ((newtor >> 26) & 0x3ff) << 14; - /* Now enable the goodies */ - reg32 |= (1 << 0); - pci_write_config32(mcu, 0xf8, reg32); - printk(BIOS_DEBUG, "Wrote remap map %x\n", reg32); - killme_debug_4g_remap_reg(reg32); - - printk(BIOS_DEBUG, "New top of memory is at %lldMB\n", newtor >> 20); - return newtor; -} - -static void vx900_set_resources(struct device *dev) -{ - u32 pci_tolm, tomk, vx900_tolm, full_tolmk, fbufk, tolmk; - - printk(BIOS_DEBUG, "========================================" - "========================================\n"); - printk(BIOS_DEBUG, "============= VX900 memory sizing & Co. " - "========================================\n"); - printk(BIOS_DEBUG, "========================================" - "========================================\n"); - - int idx = 10; - struct device *const mcu = dev_find_device(PCI_VENDOR_ID_VIA, - PCI_DEVICE_ID_VIA_VX900_MEMCTRL, - 0); - if (!mcu) { - die("Something is terribly wrong.\n" - " We tried locating the MCU on the PCI bus, " - "but couldn't find it. Halting.\n"); - } - - /* How much low adrress space do we have? */ - pci_tolm = find_pci_tolm(dev->link_list); - printk(BIOS_SPEW, "Found PCI tolm at %.8x\n", pci_tolm); - printk(BIOS_SPEW, "Found PCI tolm at %dMB\n", pci_tolm >> 20); - - /* Figure out the total amount of RAM */ - tomk = vx900_get_top_of_ram(mcu) >> 10; - printk(BIOS_SPEW, "Found top of memory at %dMB\n", tomk >> 10); - - /* Do the same for top of low RAM */ - vx900_tolm = vx900_get_tolm(); - full_tolmk = vx900_tolm << (20 - 10); - /* Remap above 4G if needed */ - full_tolmk = MIN(full_tolmk, pci_tolm >> 10); - printk(BIOS_SPEW, "Found top of low memory at %dMB\n", - full_tolmk >> 10); - - /* What about the framebuffer for the integrated GPU? */ - fbufk = vx900_get_chrome9hd_fb_size() << (20 - 10); - printk(BIOS_SPEW, "Integrated graphics buffer: %dMB\n", fbufk >> 10); - - /* Can't use the framebuffer as system RAM, sorry */ - tolmk = MIN(full_tolmk, tomk); - tolmk -= fbufk; - ram_resource(dev, idx++, 0, 640); - printk(BIOS_SPEW, "System RAM left: %dMB\n", tolmk >> 10); - /* FIXME: how can we avoid leaving this hole? - * Leave a hole for VGA, 0xa0000 - 0xc0000 ?? */ - /* TODO: VGA Memory hole can be disabled in SNMIC. Upper 64k of ROM seem - * to be always mapped to the top of 1M, but this can be overcome with - * some smart positive/subtractive resource decoding */ - ram_resource(dev, idx++, 768, (tolmk - 768)); - - uma_memory_size = (uint64_t)fbufk << 10; - uma_memory_base = (uint64_t)tolmk << 10; - - if (uma_memory_size > UINT32_MAX) - die("uma_memory_size %llu exceeds 32-bit address range\n", uma_memory_size); - - if (uma_memory_base > UINT32_MAX) - die("uma_memory_base %llu exceeds 32-bit address range\n", uma_memory_base); - - //uma_resource(dev, idx++, uma_memory_base>>10, uma_memory_size>>10); - - printk(BIOS_DEBUG, "UMA @ %lldMB + %lldMB\n", uma_memory_base >> 20, - uma_memory_size >> 20); - /* FIXME: How do we handle remapping above 4G? */ - u64 tor = vx900_remap_above_4g(mcu, pci_tolm); - if (tor) - ram_resource(dev, idx++, RAM_4GB >> 10, (tor - RAM_4GB) >> 10); - - printk(BIOS_DEBUG, "======================================================\n"); - assign_resources(dev->link_list); -} - -static void vx900_read_resources(struct device *dev) -{ - /* Our fixed resources start at 0 */ - int idx = 0; - /* Reserve our ROM mapped space */ - struct resource *res; - res = new_resource(dev, idx++); - res->size = CONFIG_ROM_SIZE; - res->base = 0xffffffff - (res->size - 1); - res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; - - /* Now do the same for our MMCONF - * We always run with MMCONF enabled. We need to access the extended - * config space when configuring PCI-Express links */ - mmconf_resource(dev, idx++); - - pci_domain_read_resources(dev); -} - -static struct device_operations pci_domain_ops = { - .read_resources = vx900_read_resources, - .set_resources = vx900_set_resources, - .enable_resources = NULL, - .init = NULL, - .scan_bus = pci_domain_scan_bus, -}; - -static void cpu_bus_init(struct device *dev) -{ - initialize_cpus(dev->link_list); -} - -static struct device_operations cpu_bus_ops = { - .read_resources = DEVICE_NOOP, - .set_resources = DEVICE_NOOP, - .enable_resources = DEVICE_NOOP, - .init = cpu_bus_init, - .scan_bus = 0, -}; - -static void enable_dev(struct device *dev) -{ - /* Set the operations if it is a special bus type */ - if (dev->path.type == DEVICE_PATH_DOMAIN) { - dev->ops = &pci_domain_ops; - } else if (dev->path.type == DEVICE_PATH_CPU_CLUSTER) { - dev->ops = &cpu_bus_ops; - } -} - -struct chip_operations northbridge_via_vx900_ops = { - CHIP_NAME("VIA VX900 Chipset") - .enable_dev = enable_dev, -}; diff --git a/src/northbridge/via/vx900/pci_util.c b/src/northbridge/via/vx900/pci_util.c deleted file mode 100644 index 57b08e7586..0000000000 --- a/src/northbridge/via/vx900/pci_util.c +++ /dev/null @@ -1,39 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2013 Alexandru Gagniuc - * - * This program is free software: you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include - -#include "vx900.h" - -void dump_pci_device(pci_devfn_t dev) -{ - int i; - for (i = 0; i <= 0xff; i++) { - unsigned char val; - if ((i & 0x0f) == 0) - printk(BIOS_DEBUG, "%.2x:", i); - - if ((i & 0x0f) == 0x08) - printk(BIOS_DEBUG, " |"); - - val = pci_s_read_config8(dev, i); - printk(BIOS_DEBUG, " %.2x", val); - - if ((i & 0x0f) == 0x0f) - printk(BIOS_DEBUG, "\n"); - } -} diff --git a/src/northbridge/via/vx900/pcie.c b/src/northbridge/via/vx900/pcie.c deleted file mode 100644 index ef157d8a02..0000000000 --- a/src/northbridge/via/vx900/pcie.c +++ /dev/null @@ -1,120 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2013 Alexandru Gagniuc - * - * This program is free software: you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include -#include -#include - -#include "vx900.h" - -/** - * @file vx900/pcie.c - * - * STATUS: - * We do part of the sequence to initialize the PCIE link. The problem is that - * the reset signal for each slot is connected to a GPO pin, but We don't know - * which GPO pin. We need to figure out which GPIO pin is hooked to which slot, - * and have a mechanism to specify this per-mainboard (devicetree.cb). - * - * There is currently no timeout detection mechanism for when a link comes up. - * If the link never comes up, we hang. - */ - -static void vx900_pcie_link_init(struct device *dev) -{ - u8 reg8; - u32 reg32; - - u8 fn = dev->path.pci.devfn & 0x07; - - /* Step 1 : Check for presence of PCIE device */ - reg8 = pci_read_config8(dev, 0x5a); - - if (reg8 & (1 << 6)) - printk(BIOS_DEBUG, "Card detected in PEX%i\n", fn); - else - return; - - /* Step 2: Wait for device to enter L0 state */ - /* FIXME: implement timeout detection */ - while (0x8a != pci_read_config8(dev, 0x1c3)); - - /* Step 3: Clear PCIe error status, then check for failures */ - pci_write_config32(dev, 0x104, 0xffffffff); - reg32 = pci_read_config32(dev, 0x104); - if (0 != reg32) { - printk(BIOS_DEBUG, "PEX init error. flags 0x%.8x\n", reg32); - return; - } - - pci_write_config32(dev, 0x110, 0xffffffff); - reg32 = pci_read_config32(dev, 0x110); - if (0 != reg32) - printk(BIOS_DEBUG, "PEX errors. flags 0x%.8x\n", reg32); - - pci_write_config8(dev, 0xa4, 0xff); - if (pci_read_config8(dev, 0x4a) & (1 << 3)) - printk(BIOS_DEBUG, "Unsupported request detected.\n"); - - pci_write_config8(dev, 0x15a, 0xff); - if (pci_read_config8(dev, 0x15a) & (1 << 1)) - printk(BIOS_DEBUG, "Negotiation pending.\n"); - - /* Step 4: Read vendor ID */ - /* FIXME: Do we want to run through the whole sequence and delay boot - * by several seconds if the device does not respond properly the first - * time? */ -} - -static void vx900_pex_dev_set_resources(struct device *dev) -{ - assign_resources(dev->link_list); -} - -static void vx900_pex_init(struct device *dev) -{ - /* FIXME: For some reason, PEX0 hangs on init. Find issue, fix it. */ - if ((dev->path.pci.devfn & 0x7) == 0) - return; - - vx900_pcie_link_init(dev); -} - -static struct device_operations vx900_pex_ops = { - .read_resources = pci_bus_read_resources, - .set_resources = vx900_pex_dev_set_resources, - .enable_resources = pci_bus_enable_resources, - .init = vx900_pex_init, - .scan_bus = pciexp_scan_bridge, - .reset_bus = pci_bus_reset, -}; - -static const unsigned short pci_device_ids[] = { - PCI_DEVICE_ID_VIA_VX900_PEX1, - PCI_DEVICE_ID_VIA_VX900_PEX2, - PCI_DEVICE_ID_VIA_VX900_PEX3, - PCI_DEVICE_ID_VIA_VX900_PEX4, - 0, -}; - -static const struct pci_driver pex_driver __pci_driver = { - .ops = &vx900_pex_ops, - .vendor = PCI_VENDOR_ID_VIA, - .devices = pci_device_ids, - -}; diff --git a/src/northbridge/via/vx900/raminit.h b/src/northbridge/via/vx900/raminit.h deleted file mode 100644 index 4c53d52d8c..0000000000 --- a/src/northbridge/via/vx900/raminit.h +++ /dev/null @@ -1,98 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 Alexandru Gagniuc - * - * This program is free software: you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef RAMINIT_VX900_H -#define RAMINIT_VX900_H - -#include -#include "vx900.h" - -#define SPD_END_LIST 0xff - -typedef struct dimm_layout_st -{ - /* The address of the DIMM on the SMBUS * - * 0xFF to terminate the array*/ - u8 spd_addr[VX900_MAX_DIMM_SLOTS + 1]; -} dimm_layout; - -typedef struct dimm_info_st -{ - dimm_attr dimm[VX900_MAX_DIMM_SLOTS]; -} dimm_info; - -typedef struct mem_rank_st { - u16 start_addr; - u16 end_addr; -} mem_rank; - -typedef struct rank_layout_st { - u32 phys_rank_size_mb[VX900_MAX_MEM_RANKS]; - mem_rank virt[VX900_MAX_MEM_RANKS]; - dimm_flags_t flags[VX900_MAX_MEM_RANKS]; -} rank_layout; - -typedef struct pci_reg8_st { - u8 addr; - u8 val; -} pci_reg8; - -typedef u8 timing_dly[8]; - -typedef struct delay_range_st { - timing_dly low; - timing_dly avg; - timing_dly high; -} delay_range; - -typedef struct vx900_delay_calib_st { - delay_range rx_dq_cr; - delay_range rx_dqs; - /* Transmit delays are calibrated for each dimm */ - delay_range tx_dq[VX900_MAX_DIMM_SLOTS]; - delay_range tx_dqs[VX900_MAX_DIMM_SLOTS]; -} vx900_delay_calib; - -typedef struct ramctr_timing_st { - enum spd_memory_type dram_type; - enum spd_dimm_type dimm_type; - u16 cas_supported; - /* tLatencies are in units of ns, scaled by x256 */ - u32 tCK; - u32 tAA; - u32 tWR; - u32 tRCD; - u32 tRRD; - u32 tRP; - u32 tRAS; - u32 tRC; - u32 tRFC; - u32 tWTR; - u32 tRTP; - u32 tFAW; - /* Latencies in terms of clock cycles - * They are saved separately as they are needed for DRAM MRS commands*/ - u8 CAS; /* CAS read latency */ - u8 CWL; /* CAS write latency */ - u8 WR; /* write recovery time */ - /* Number of dimms currently connected */ - u8 n_dimms; - -} ramctr_timing; - -void vx900_init_dram_ddr3(const dimm_layout *dimms); - -#endif /* RAMINIT_VX900_H */ diff --git a/src/northbridge/via/vx900/raminit_ddr3.c b/src/northbridge/via/vx900/raminit_ddr3.c deleted file mode 100644 index 4f79ed35b0..0000000000 --- a/src/northbridge/via/vx900/raminit_ddr3.c +++ /dev/null @@ -1,1671 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011-2012 Alexandru Gagniuc - * - * This program is free software: you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include "early_vx900.h" -#include "raminit.h" -#include -#include -#include -#include -#include -#include -#include - -/** - * @file raminit_ddr3.c - * - * \brief DDR3 initialization for VIA VX900 chipset - * - * Rather than explain the DDR3 init algorithm, it is better to focus on what - * works and what doesn't. Familiarity with the DDR3 spec does not hurt. - * - * 1 DIMMs and 2 DIMMs with one rank each works. - * 1 rank DIMM with 2 rank DIMM works, but the odd ranks are disabled. - * (2) 2-rank DIMMs will not work. - * - * It is not yet clear if odd ranks do not work because of faulty timing - * calibration, or a misconfiguration of the MCU. I have seen this with DIMMS - * which mirror pins on the odd rank. That could also be the issue. - * - * The capture window is not calibrated, but preset. Whether that preset is - * universal or frequency dependent, and whether it is board-specific or not is - * not yet clear. @see vx900_dram_calibrate_receive_delays(). - * - * 4GBit and 8GBit modules may not work. This is untested. Modules with 11 - * column address bits are not tested. @see vx900_dram_map_row_col_bank() - * - * Everything else should be in a more or less usable state. FIXME s are placed - * all over as a reminder that either something really needs fixing, or as a - * reminder to double-check. - */ - -/* Map BA0 <-> A17, BA1 <-> A18 */ -/* Map BA2 <-> A19, RA0/RA1 must not overlap BA[0:2] */ -#define VX900_MRS_MA_MAP 0x4b33 /* MA Pin Mapping for MRS commands */ -#define VX900_CALIB_MA_MAP 0x5911 /* MA Pin mapping for calibrations */ - -/* - * Registers 0x78 -> 0x7f contain the calibration settings for DRAM IO timing - * The dataset in these registers is selected from 0x70. - * Once the correct dataset is selected the delays can be altered. - * delay_type refers to TxDQS, TxDQ, RxDQS, or RxCR - * bound refers to either manual, average, upper bound, or lower bound - */ -#define CALIB_TxDQS 0 -#define CALIB_TxDQ 1 -#define CALIB_RxDQS 2 -#define CALIB_RxDQ_CR 3 - -#define CALIB_AVERAGE 0 -#define CALIB_LOWER 1 -#define CALIB_UPPER 2 -#define CALIB_MANUAL 4 /* We want this & 3 to overflow to 0 */ - -static void vx900_delay_calib_mode_select(u8 delay_type, u8 bound) -{ - /* Which calibration setting */ - u8 reg8 = (delay_type & 0x03) << 2; - /* Upper, lower, average, or manual setting */ - reg8 |= (bound & 0x03); - pci_write_config8(MCU, 0x70, reg8); -} - -/* - * The vendor BIOS does something similar to vx900_delay_calib_mode_select(), - * then reads or write a byte, and repeats the process for all 8 bytes. This is - * annoyingly inefficient, and we can achieve the same result in a much more - * elegant manner. - */ -static void vx900_read_0x78_0x7f(timing_dly dly) -{ - *((u32 *) (&(dly[0]))) = pci_read_config32(MCU, 0x78); - *((u32 *) (&(dly[4]))) = pci_read_config32(MCU, 0x7c); -} - -static void vx900_write_0x78_0x7f(const timing_dly dly) -{ - pci_write_config32(MCU, 0x78, *((u32 *) (&(dly[0])))); - pci_write_config32(MCU, 0x7c, *((u32 *) (&(dly[4])))); -} - -static void vx900_read_delay_range(delay_range * d_range, u8 mode) -{ - vx900_delay_calib_mode_select(mode, CALIB_LOWER); - vx900_read_0x78_0x7f(d_range->low); - vx900_delay_calib_mode_select(mode, CALIB_AVERAGE); - vx900_read_0x78_0x7f(d_range->avg); - vx900_delay_calib_mode_select(mode, CALIB_UPPER); - vx900_read_0x78_0x7f(d_range->high); -} - -static void dump_delay(const timing_dly dly) -{ - u8 i; - for (i = 0; i < 8; i++) { - printram(" %.2x", dly[i]); - } - printram("\n"); -} - -static void dump_delay_range(const delay_range d_range) -{ - printram("Lower limit: "); - dump_delay(d_range.low); - printram("Average: "); - dump_delay(d_range.avg); - printram("Upper limit: "); - dump_delay(d_range.high); -} - -/* - * These are some "safe" values that can be used for memory initialization. - * Some will stay untouched, and others will be overwritten later on - */ -static pci_reg8 mcu_init_config[] = { - {0x40, 0x01}, /* Virtual rank 0 ending address = 64M - 1 */ - {0x41, 0x00}, {0x42, 0x00}, {0x43, 0x00}, /* Virtual Ranks ending */ - {0x48, 0x00}, /* Virtual rank 0 starting address = 0 */ - {0x49, 0x00}, {0x4a, 0x00}, {0x4b, 0x00}, /* Virtual Ranks beginning */ - {0x50, 0xd8}, /* Set ranks 0-3 to 11 col bits, 16 row bits */ - /* Disable all virtual ranks */ - {0x54, 0x00}, {0x55, 0x00}, {0x56, 0x00}, {0x57, 0x00}, - /* Disable rank interleaving in ranks 0-3 */ - {0x58, 0x00}, {0x59, 0x00}, {0x5a, 0x00}, {0x5b, 0x00}, - {0x6c, 0xA0}, /* Memory type: DDR3, VDIMM: 1.5V, 64-bit DRAM */ - {0xc4, 0x80}, /* Enable 8 memory banks */ - {0xc6, 0x80}, /* Minimum latency from self-refresh. Bit [7] must be 1 */ - /* FIXME: do it here or in Final config? */ - {0xc8, 0x80}, /* Enable automatic triggering of short ZQ calibration */ - {0x99, 0xf0}, /* Power Management and Bypass Reorder Queue */ - /* Enable differential DQS; MODT assertion values suggested in DS */ - {0x9e, 0xa1}, {0x9f, 0x51}, - /* DQ/DQM Duty Control - Do not put any extra delays */ - {0xe9, 0x00}, {0xea, 0x00}, {0xeb, 0x00}, {0xec, 0x00}, - {0xed, 0x00}, {0xee, 0x00}, {0xef, 0x00}, - {0xfc, 0x00}, {0xfd, 0x00}, {0xfe, 0x00}, {0xff, 0x00}, - /* The following parameters we may or may not change */ - {0x61, 0x2e}, /* DRAMC Pipeline Control */ - {0x77, 0x10}, /* MDQS Output Control */ - - /* The following are parameters we'll most likely never change again */ - {0x60, 0xf4}, /* DRAM Pipeline Turn-Around Setting */ - {0x65, 0x49}, /* DRAM Arbitration Bandwidth Timer - I */ - {0x66, 0x80}, /* DRAM Queue / Arbitration */ - {0x69, 0xc6}, /* Bank Control: 8 banks, high priority refresh */ - {0x6a, 0xfc}, /* DRAMC Request Reorder Control */ - {0x6e, 0x38}, /* Burst length: 8, burst-chop: enable */ - {0x73, 0x04}, /* Close All Pages Threshold */ - - /* The following need to be dynamically asserted */ - /* See: check_special_registers.c */ - {0x74, 0xa0}, /* Yes, same 0x74; add one more T */ - {0x76, 0x60}, /* Write Data Phase Control */ - -}; - -/* - * This table keeps the driving strength control setting that we can safely use - * during initialization. This settings come in part from SerialICE, and in part - * from code provided by VIA. - */ -static pci_reg8 mcu_drv_ctrl_config[] = { - {0xd3, 0x03}, /* Enable auto-compensation circuit for ODT strength */ - {0xd4, 0x80}, /* Set internal ODT to dynamically turn on or off */ - {0xd6, 0x20}, /* Enable strong driving for MA and DRAM commands */ - {0xd0, 0x88}, /* (ODT) Strength ?has effect? */ - {0xe0, 0x88}, /* DRAM Driving - Group DQS (MDQS) */ - {0xe1, 0x00}, /* Disable offset mode for driving strength control */ - {0xe2, 0x88}, /* DRAM Driving - Group DQ (MD, MDQM) */ - {0xe4, 0xcc}, /* DRAM Driving - Group CSA (MCS, MCKE, MODT) */ - {0xe8, 0x88}, /* DRAM Driving - Group MA (MA, MBA, MSRAS, MSCAS, MSWE) */ - {0xe6, 0xff}, /* DRAM Driving - Group DCLK0 (DCLK[2:0] for DIMM0) */ - {0xe7, 0xff}, /* DRAM Driving - Group DCLK1 (DCLK[5:3] for DIMM1) */ - {0xe4, 0xcc}, /* DRAM Driving - Group CSA (MCS, MCKE, MODT) */ - {0x91, 0x08}, /* MCLKO Output Phase Delay - I */ - {0x92, 0x08}, /* MCLKO Output Phase Delay - II */ - {0x93, 0x16}, /* CS/CKE Output Phase Delay */ - {0x95, 0x16}, /* SCMD/MA Output Phase Delay */ - {0x9b, 0x3f}, /* Memory Clock Output Enable */ -}; - -static void vx900_dram_set_ma_pin_map(u16 map) -{ - pci_write_config16(MCU, 0x52, map); -} - -/* - * FIXME: This function is a complete waste of space. All we really need is a - * MA MAP table based on either row address bits or column address bits. - * The problem is, I do not know if this mapping is applied during the column - * access or during the row access. At least the religiously verbose output - * makes pretty console output. - */ -static void vx900_dram_map_pins(u8 ba0, u8 ba1, u8 ba2, u8 ra0, u8 ra1) -{ - u16 map = 0; - - printram("Mapping address pins to DRAM pins:\n"); - printram(" BA0 -> A%u\n", ba0); - printram(" BA1 -> A%u\n", ba1); - printram(" BA2 -> A%u\n", ba2); - printram(" RA0 -> A%u\n", ra0); - printram(" RA1 -> A%u\n", ra1); - /* Make sure BA2 is enabled */ - map |= (1 << 11); - - /* - * Find RA1 (15:14) - * 00: A14 - * 01: A16 - * 10: A18 - * 11: A20 - */ - if ((ra1 & 0x01) || (ra1 < 14) || (ra1 > 20)) { - printram("Illegal mapping RA1 -> A%u\n", ra1); - return; - } - map |= (((ra1 - 14) >> 1) & 0x03) << 14; - - /* - * Find RA0 (13:12) - * 00: A15 - * 01: A17 - * 10: A19 - * 11: A21 - */ - if ((!(ra0 & 0x01)) || (ra0 < 15) || (ra0 > 21)) { - printram("Illegal mapping RA0 -> A%u\n", ra0); - return; - } - map |= (((ra0 - 15) >> 1) & 0x03) << 12; - - /* - * Find BA2 (10:8) - * x00: A14 - * x01: A15 - * x10: A18 - * x11: A19 - */ - switch (ba2) { - case 14: - map |= (0 << 8); - break; - case 15: - map |= (1 << 8); - break; - case 18: - map |= (2 << 8); - break; - case 19: - map |= (3 << 8); - break; - default: - printram("Illegal mapping BA2 -> A%u\n", ba2); - break; - } - - /* - * Find BA1 (6:4) - * 000: A12 - * 001: A14 - * 010: A16 - * 011: A18 - * 1xx: A20 - */ - if (((ba1 & 0x01)) || (ba1 < 12) || (ba1 > 20)) { - printram("Illegal mapping BA1 -> A%u\n", ba1); - return; - } - map |= (((ba1 - 12) >> 1) & 0x07) << 4; - - /* - * Find BA0 (2:0) - * 000: A11 - * 001: A13 - * 010: A15 - * 011: A17 - * 1xx: A19 - */ - if ((!(ba0 & 0x01)) || (ba0 < 11) || (ba0 > 19)) { - printram("Illegal mapping BA0 -> A%u\n", ba0); - return; - } - map |= (((ba0 - 11) >> 1) & 0x07) << 0; - - printram("Setting map mask (rx52) to %.4x\n", map); - vx900_dram_set_ma_pin_map(map); -} - -static void vx900_dram_write_init_config(void) -{ - /* Keep our RAM space free of legacy stuff */ - vx900_disable_legacy_rom_shadow(); - - /* Now worry about the real RAM init */ - size_t i; - for (i = 0; i < (sizeof(mcu_init_config) / sizeof(pci_reg8)); i++) { - pci_write_config8(MCU, mcu_init_config[i].addr, - mcu_init_config[i].val); - } - vx900_dram_set_ma_pin_map(VX900_CALIB_MA_MAP); - - /* FIXME: Slowing stuff down. Does this really help? */ - - /* Fast cycle control for CPU-to-DRAM Read Cycle 0:Disabled. - * This CPU bus controller will wait for all data */ - - /* Memory to CPU bus Controller Conversion Mode 1: Synchronous mode */ -} - -static void dram_find_spds_ddr3(const dimm_layout * addr, dimm_info * dimm) -{ - size_t i = 0; - int dimms = 0; - do { - spd_raw_data spd; - spd_read(addr->spd_addr[i], spd); - spd_decode_ddr3(&dimm->dimm[i], spd); - if (dimm->dimm[i].dram_type != SPD_MEMORY_TYPE_SDRAM_DDR3) - continue; - dimms++; - dram_print_spd_ddr3(&dimm->dimm[i]); - } while (addr->spd_addr[++i] != SPD_END_LIST - && i < VX900_MAX_DIMM_SLOTS); - - if (!dimms) - die("No DIMMs were found"); -} - -static void dram_find_common_params(const dimm_info * dimms, - ramctr_timing * ctrl) -{ - size_t i, valid_dimms; - memset(ctrl, 0, sizeof(ramctr_timing)); - ctrl->cas_supported = 0xff; - valid_dimms = 0; - for (i = 0; i < VX900_MAX_DIMM_SLOTS; i++) { - const dimm_attr *dimm = &dimms->dimm[i]; - if (dimm->dram_type == SPD_MEMORY_TYPE_UNDEFINED) - continue; - valid_dimms++; - - if (valid_dimms == 1) { - /* First DIMM defines the type of DIMM */ - ctrl->dram_type = dimm->dram_type; - ctrl->dimm_type = dimm->dimm_type; - } else { - /* Check if we have mismatched DIMMs */ - if (ctrl->dram_type != dimm->dram_type - || ctrl->dimm_type != dimm->dimm_type) - die("Mismatched DIMM Types"); - } - /* Find all possible CAS combinations */ - ctrl->cas_supported &= dimm->cas_supported; - - /* Find the smallest common latencies supported by all DIMMs */ - ctrl->tCK = MAX(ctrl->tCK, dimm->tCK); - ctrl->tAA = MAX(ctrl->tAA, dimm->tAA); - ctrl->tWR = MAX(ctrl->tWR, dimm->tWR); - ctrl->tRCD = MAX(ctrl->tRCD, dimm->tRCD); - ctrl->tRRD = MAX(ctrl->tRRD, dimm->tRRD); - ctrl->tRP = MAX(ctrl->tRP, dimm->tRP); - ctrl->tRAS = MAX(ctrl->tRAS, dimm->tRAS); - ctrl->tRC = MAX(ctrl->tRC, dimm->tRC); - ctrl->tRFC = MAX(ctrl->tRFC, dimm->tRFC); - ctrl->tWTR = MAX(ctrl->tWTR, dimm->tWTR); - ctrl->tRTP = MAX(ctrl->tRTP, dimm->tRTP); - ctrl->tFAW = MAX(ctrl->tFAW, dimm->tFAW); - - } - - ctrl->n_dimms = valid_dimms; - if (!ctrl->cas_supported) - die("Unsupported DIMM combination. " - "DIMMS do not support common CAS latency"); - if (!valid_dimms) - die("No valid DIMMs found"); -} - -static void vx900_dram_phys_bank_range(const dimm_info * dimms, - rank_layout * ranks) -{ - size_t i; - for (i = 0; i < VX900_MAX_DIMM_SLOTS; i++) { - if (dimms->dimm[i].dram_type == SPD_MEMORY_TYPE_UNDEFINED) - continue; - u8 nranks = dimms->dimm[i].ranks; - /* Make sure we save the flags */ - ranks->flags[i * 2 + 1] = ranks->flags[i * 2] = - dimms->dimm[i].flags; - /* Only Rank1 has a mirrored pin mapping */ - ranks->flags[i * 2].pins_mirrored = 0; - if (nranks > 2) - die("Found DIMM with more than two ranks, which is not " - "supported by this chipset"); - u32 size = dimms->dimm[i].size_mb; - if (nranks == 2) { - /* Each rank holds half the capacity of the DIMM */ - size >>= 1; - ranks->phys_rank_size_mb[i << 1] = size; - ranks->phys_rank_size_mb[(i << 1) | 1] = size; - } else { - /* Otherwise, everything is held in the first bank */ - ranks->phys_rank_size_mb[i << 1] = size; - ranks->phys_rank_size_mb[(i << 1) | 1] = 0; - } - } -} - -#define ODT_R0 0 -#define ODT_R1 1 -#define ODT_R2 2 -#define ODT_R3 3 -/* - * This is the table that tells us which MODT pin to map to which rank. - * - * This table is taken from code provided by VIA, but no explanation was - * provided as to why it is done this way. It may be possible that this table is - * not suitable for the way we map ranks later on. - */ -static const u8 odt_lookup_table[][2] = { - /* RankMAP Rank 3 Rank 2 Rank 1 Rank 0 */ - {0x01, (ODT_R3 << 6) | (ODT_R2 << 4) | (ODT_R1 << 2) | (ODT_R0 << 0)}, - {0x03, (ODT_R3 << 6) | (ODT_R2 << 4) | (ODT_R0 << 2) | (ODT_R1 << 0)}, - {0x04, (ODT_R3 << 6) | (ODT_R2 << 4) | (ODT_R1 << 2) | (ODT_R0 << 0)}, - {0x05, (ODT_R3 << 6) | (ODT_R0 << 4) | (ODT_R1 << 2) | (ODT_R2 << 0)}, - {0x07, (ODT_R3 << 6) | (ODT_R0 << 4) | (ODT_R2 << 2) | (ODT_R2 << 0)}, - {0x0c, (ODT_R2 << 6) | (ODT_R3 << 4) | (ODT_R1 << 2) | (ODT_R0 << 0)}, - {0x0d, (ODT_R0 << 6) | (ODT_R0 << 4) | (ODT_R1 << 2) | (ODT_R2 << 0)}, - {0x0f, (ODT_R0 << 6) | (ODT_R0 << 4) | (ODT_R2 << 2) | (ODT_R2 << 0)}, - {0, 0}, -}; - -static void vx900_dram_driving_ctrl(const dimm_info * dimm) -{ - size_t i, ndimms; - u8 reg8, regxd5, rank_mask; - - rank_mask = 0; - /* For ODT range selection, datasheet recommends - * when 1 DIMM present: 60 Ohm - * when 2 DIMMs present: 120 Ohm */ - ndimms = 0; - for (i = 0; i < VX900_MAX_DIMM_SLOTS; i++) { - if (dimm->dimm[i].dram_type != SPD_MEMORY_TYPE_SDRAM_DDR3) - continue; - ndimms++; - rank_mask |= (1 << (i * 2)); - if (dimm->dimm[i].ranks > 1) - rank_mask |= (2 << (i * 2)); - } - /* ODT strength and MD/MDQM/MDQS driving strength */ - if (ndimms > 1) { - /* Enable 1 ODT block (120 Ohm ODT) */ - regxd5 = 0 << 2; - /* Enable strong driving for MD/MDQM/MDQS */ - regxd5 |= (1 << 7); - } else { - /* Enable 2 ODT blocks (60 Ohm ODT) */ - regxd5 = 1 << 2; - /* Leave MD/MDQM/MDQS driving weak */ - } - pci_write_config8(MCU, 0xd5, regxd5); - - /* Enable strong CLK driving for DIMMs with more than one rank */ - if (dimm->dimm[0].ranks > 1) - pci_or_config8(MCU, 0xd6, (1 << 7)); - if (dimm->dimm[1].ranks > 1) - pci_or_config8(MCU, 0xd6, (1 << 6)); - - /* DRAM ODT Lookup Table */ - for (i = 0;; i++) { - if (odt_lookup_table[i][0] == 0) { - printram("No ODT entry for rank mask %x\n", rank_mask); - die("Aborting"); - } - if (odt_lookup_table[i][0] != rank_mask) - continue; - - reg8 = odt_lookup_table[i][1]; - break; - } - - printram("Mapping rank mask %x to ODT entry %.2x\n", rank_mask, reg8); - pci_write_config8(MCU, 0x9c, reg8); - - for (i = 0; i < (sizeof(mcu_drv_ctrl_config) / sizeof(pci_reg8)); i++) { - pci_write_config8(MCU, mcu_drv_ctrl_config[i].addr, - mcu_drv_ctrl_config[i].val); - } -} - -static void vx900_pr_map_all_vr3(void) -{ - /* Enable all ranks and set them to VR3 */ - pci_write_config16(MCU, 0x54, 0xbbbb); -} - -/* Map physical rank pr to virtual rank vr */ -static void vx900_map_pr_vr(u8 pr, u8 vr) -{ - u16 val; - - pr &= 0x3; - vr &= 0x3; - /* Enable rank (bit [3], and set the VR number bits [1:0] */ - val = 0x8 | vr; - /* Now move the value to the appropriate PR */ - val <<= (pr * 4); - pci_update_config16(MCU, 0x54, ~(0xf << (pr * 4)), val); - printram("Mapping PR %u to VR %u\n", pr, vr); -} - -static u8 vx900_get_CWL(u8 CAS) -{ - /* Get CWL based on CAS using the following rule: - * _________________________________________ - * CAS: | 4T | 5T | 6T | 7T | 8T | 9T | 10T | 11T | - * CWL: | 5T | 5T | 5T | 6T | 6T | 7T | 7T | 8T | - */ - static const u8 cas_cwl_map[] = { 5, 5, 5, 6, 6, 7, 7, 8 }; - if (CAS > 11) - return 8; - return cas_cwl_map[CAS - 4]; -} - -/* - * Here we are calculating latencies, and writing them to the appropriate - * registers. Note that some registers do not take latencies from 0 = 0T, - * 1 = 1T, so each register gets its own math formula. - */ -static void vx900_dram_timing(ramctr_timing * ctrl) -{ - u8 reg8, val, tFAW, tRRD; - - /* Maximum supported DDR3 frequency is 533MHz (DDR3 1066) so make sure - * we cap it if we have faster DIMMs. - * Then, align it to the closest JEDEC standard frequency */ - if (ctrl->tCK <= TCK_533MHZ) { - ctrl->tCK = TCK_533MHZ; - } else if (ctrl->tCK <= TCK_400MHZ) { - ctrl->tCK = TCK_400MHZ; - } else if (ctrl->tCK <= TCK_333MHZ) { - ctrl->tCK = TCK_333MHZ; - } else { - ctrl->tCK = TCK_266MHZ; - } - - printram("Selected DRAM frequency: %u MHz\n", (1000 << 8) / ctrl->tCK); - - /* Find CAS and CWL latencies */ - val = DIV_ROUND_UP(ctrl->tAA, ctrl->tCK); - printram("Minimum CAS latency : %uT\n", val); - /* Find lowest supported CAS latency that satisfies the minimum value */ - while (!((ctrl->cas_supported >> (val - 4)) & 1) - && (ctrl->cas_supported >> (val - 4))) { - val++; - } - /* Is CAS supported */ - if (!(ctrl->cas_supported & (1 << (val - 4)))) - printram("CAS not supported\n"); - printram("Selected CAS latency : %uT\n", val); - ctrl->CAS = val; - ctrl->CWL = vx900_get_CWL(ctrl->CAS); - printram("Selected CWL latency : %uT\n", ctrl->CWL); - /* Write CAS and CWL */ - reg8 = (((ctrl->CWL - 4) & 0x07) << 4) | ((ctrl->CAS - 4) & 0x07); - pci_write_config8(MCU, 0xc0, reg8); - - /* Find tRCD */ - val = DIV_ROUND_UP(ctrl->tRCD, ctrl->tCK); - printram("Selected tRCD : %uT\n", val); - reg8 = ((val - 4) & 0x7) << 4; - /* Find tRP */ - val = DIV_ROUND_UP(ctrl->tRP, ctrl->tCK); - printram("Selected tRP : %uT\n", val); - reg8 |= ((val - 4) & 0x7); - pci_write_config8(MCU, 0xc1, reg8); - - /* Find tRAS */ - val = DIV_ROUND_UP(ctrl->tRAS, ctrl->tCK); - printram("Selected tRAS : %uT\n", val); - reg8 = ((val - 15) & 0x7) << 4; - /* Find tWR */ - ctrl->WR = DIV_ROUND_UP(ctrl->tWR, ctrl->tCK); - printram("Selected tWR : %uT\n", ctrl->WR); - reg8 |= ((ctrl->WR - 4) & 0x7); - pci_write_config8(MCU, 0xc2, reg8); - - /* Find tFAW */ - tFAW = DIV_ROUND_UP(ctrl->tFAW, ctrl->tCK); - printram("Selected tFAW : %uT\n", tFAW); - /* Find tRRD */ - tRRD = DIV_ROUND_UP(ctrl->tRRD, ctrl->tCK); - printram("Selected tRRD : %uT\n", tRRD); - val = tFAW - 4 * tRRD; /* number of cycles above 4*tRRD */ - reg8 = ((val - 0) & 0x7) << 4; - reg8 |= ((tRRD - 2) & 0x7); - pci_write_config8(MCU, 0xc3, reg8); - - /* Find tRTP */ - val = DIV_ROUND_UP(ctrl->tRTP, ctrl->tCK); - printram("Selected tRTP : %uT\n", val); - reg8 = ((val & 0x3) << 4); - /* Find tWTR */ - val = DIV_ROUND_UP(ctrl->tWTR, ctrl->tCK); - printram("Selected tWTR : %uT\n", val); - reg8 |= ((val - 2) & 0x7); - pci_update_config8(MCU, 0xc4, ~0x3f, reg8); - - /* DRAM Timing for All Ranks - VI - * [7:6] CKE Assertion Minimum Pulse Width - * We probably don't want to mess with this just yet. - * [5:0] Refresh-to-Active or Refresh-to-Refresh (tRFC) - * tRFC = (30 + 2 * [5:0])T - * Since we previously set RxC4[7] - */ - reg8 = pci_read_config8(MCU, 0xc5); - val = DIV_ROUND_UP(ctrl->tRFC, ctrl->tCK); - printram("Minimum tRFC : %uT\n", val); - if (val < 30) { - val = 0; - } else { - val = (val - 30 + 1) / 2; - } - ; - printram("Selected tRFC : %uT\n", 30 + 2 * val); - reg8 |= (val & 0x3f); - pci_write_config8(MCU, 0xc5, reg8); - - /* Where does this go??? */ - val = DIV_ROUND_UP(ctrl->tRC, ctrl->tCK); - printram("Required tRC : %uT\n", val); -} - -/* Program the DRAM frequency */ -static void vx900_dram_freq(ramctr_timing * ctrl) -{ - u8 val; - - /* Step 1 - Reset the PLL */ - pci_or_config8(MCU, 0x90, 0x0f); - /* Wait at least 10 ns; VIA code delays by 640us */ - udelay(640); - - /* Step 2 - Set target frequency */ - if (ctrl->tCK <= TCK_533MHZ) { - val = 0x07; - ctrl->tCK = TCK_533MHZ; - } else if (ctrl->tCK <= TCK_400MHZ) { - val = 0x06; - ctrl->tCK = TCK_400MHZ; - } else if (ctrl->tCK <= TCK_333MHZ) { - val = 0x05; - ctrl->tCK = TCK_333MHZ; - } else { /*ctrl->tCK <= TCK_266MHZ */ - val = 0x04; - ctrl->tCK = TCK_266MHZ; - } - /* Restart the PLL with the desired frequency */ - pci_update_config8(MCU, 0x90, ~0x0f, val); - - /* Step 3 - Wait for PLL to stabilize */ - udelay(2000); - - /* Step 4 - Reset the DLL - Clear [7,4] */ - pci_update_config8(MCU, 0x6b, (u8)~0x90, 0x00); - udelay(2000); - - /* Step 5 - Enable the DLL - Set bits [7,4] to 01b */ - pci_or_config8(MCU, 0x6b, 0x10); - udelay(2000); - - /* Step 6 - Start DLL Calibration - Set bit [7] */ - pci_or_config8(MCU, 0x6b, 0x80); - udelay(5); - - /* Step 7 - Finish DLL Calibration - Clear bit [7] */ - pci_update_config8(MCU, 0x6b, (u8)~0x80, 0x00); - - /* Step 8 - If we have registered DIMMs, we need to set bit[0] */ - if (spd_dimm_is_registered_ddr3(ctrl->dimm_type)) { - printram("Enabling RDIMM support in memory controller\n"); - pci_or_config8(MCU, 0x6c, 0x01); - } -} - -/* - * The VX900 can send the MRS commands directly through hardware - * It does the MR2->MR3->MR1->MR0->LongZQ JEDEC dance - * The parameters that we don't worry about are extracted from the timing - * registers we have programmed earlier. - */ -static void vx900_dram_ddr3_do_hw_mrs(u8 ma_swap, u8 rtt_nom, - u8 ods, u8 rtt_wr, u8 srt, u8 asr) -{ - u16 reg16 = 0; - - printram("Using Hardware method for DRAM MRS commands.\n"); - - reg16 |= ((rtt_wr & 0x03) << 12); - if (srt) - reg16 |= (1 << 9); - if (asr) - reg16 |= (1 << 8); - reg16 |= ((rtt_nom & 0x7) << 4); - reg16 |= ((ods & 0x03) << 2); - if (ma_swap) - reg16 |= (1 << 1); - reg16 |= (1 << 14); - reg16 |= (1 << 0); /* This is the trigger bit */ - printram("Hw MRS set is 0x%4x\n", reg16); - pci_write_config16(MCU, 0xcc, reg16); - /* Wait for MRS commands to be sent */ - while (pci_read_config8(MCU, 0xcc) & 1); -} - -/* - * Translate the MRS command into an address on the CPU bus - * - * Take an MRS command (mrs_cmd_t) and translate it to a read address on the CPU - * bus. Thus, reading from the returned address, will issue the correct MRS - * command, assuming we are in MRS mode, of course. - * - * A read from the returned address will produce the correct MRS command - * provided the following conditions are met: - * - The MA pin mapping is set to VX900_MRS_MA_MAP - * - The memory controller's Fun3_RX6B[2:0] is set to 011b (MSR Enable) - */ -static u32 vx900_get_mrs_addr(mrs_cmd_t cmd) -{ - u32 addr = 0; - u8 mrs_type = (cmd >> 16) & 0x07; - /* MA[9:0] <-> A[12:3] */ - addr |= ((cmd & 0x3ff) << 3); - /* MA10 <-> A20 */ - addr |= (((cmd >> 10) & 0x1) << 20); - /* MA[12:11] <-> A[14:13] */ - addr |= (((cmd >> 11) & 0x3) << 13); - /* BA[2:0] <-> A[19:17] */ - addr |= mrs_type << 17; - return addr; -} - -/* - * Here, we do the MR2->MR3->MR1->MR0->LongZQ JEDEC dance manually - * - * Why would we do this in software, when the VX900 can do it in hardware? The - * problem is the hardware sequence seems to be buggy on ranks with mirrored - * pins. Is this a hardware bug or a misconfigured MCU? No idea. - * - * To maintain API compatibility with the function that implements the hardware - * sequence, we don't ask for all parameters. To keep an overall cleaner code - * structure, we don't try to pass down all that information. Instead, we - * extract the extra parameters from the timing registers we have programmed - * earlier. - */ -static void vx900_dram_ddr3_do_sw_mrs(u8 ma_swap, enum ddr3_mr1_rtt_nom rtt_nom, - enum ddr3_mr1_ods ods, - enum ddr3_mr2_rttwr rtt_wr, - enum ddr3_mr2_srt_range srt, - enum ddr3_mr2_asr asr) -{ - mrs_cmd_t mrs; - u8 reg8, cas, cwl, twr; - - printram("Using Software method for DRAM MRS commands.\n"); - - /* Get CAS, CWL, and tWR that we programmed earlier */ - reg8 = pci_read_config8(MCU, 0xc0); - cas = (reg8 & 0x07) + 4; - cwl = ((reg8 >> 4) & 0x07) + 4; - reg8 = pci_read_config8(MCU, 0xc2); - twr = (reg8 & 0x07) + 4; - - /* Step 06 - Set Fun3_RX6B[2:0] to 001b (NOP Command Enable). */ - /* Was already done for us before calling us */ - - /* Step 07 - Read a double word from any address of the DIMM. */ - /* Was already done for us before calling us */ - - /* Step 08 - Set Fun3_RX6B[2:0] to 011b (MSR Enable). */ - pci_update_config8(MCU, 0x6b, ~0x07, 0x03); /* MSR Enable */ - - /* Step 09 - Issue MR2 cycle. Read a double word from the address - * depended on DRAM's Rtt_WR and CWL settings. */ - mrs = ddr3_get_mr2(rtt_wr, srt, asr, cwl); - if (ma_swap) - mrs = ddr3_mrs_mirror_pins(mrs); - volatile_read(vx900_get_mrs_addr(mrs)); - printram("MR2: %.5x\n", mrs); - udelay(1000); - - /* Step 10 - Issue MR3 cycle. Read a double word from the address 60000h - * to set DRAM to normal operation mode. */ - mrs = ddr3_get_mr3(0); - if (ma_swap) - mrs = ddr3_mrs_mirror_pins(mrs); - volatile_read(vx900_get_mrs_addr(mrs)); - printram("MR3: %.5x\n", mrs); - udelay(1000); - - /* Step 11 -Issue MR1 cycle. Read a double word from the address - * depended on DRAM's output driver impedance and Rtt_Nom settings. - * The DLL enable field, TDQS field, write leveling enable field, - * additive latency field and Qoff field should be set to 0. */ - mrs = ddr3_get_mr1(DDR3_MR1_QOFF_ENABLE, DDR3_MR1_TQDS_DISABLE, rtt_nom, - DDR3_MR1_WRLVL_DISABLE, ods, DDR3_MR1_AL_DISABLE, - DDR3_MR1_DLL_ENABLE); - if (ma_swap) - mrs = ddr3_mrs_mirror_pins(mrs); - volatile_read(vx900_get_mrs_addr(mrs)); - printram("MR1: %.5x\n", mrs); - udelay(1000); - - /* Step 12 - Issue MR0 cycle. Read a double word from the address - * depended on DRAM's burst length, CAS latency and write recovery time - * settings. - * The read burst type field should be set to interleave. - * The mode field should be set to normal mode. - * The DLL reset field should be set to No. - * The DLL control for precharge PD field should be set to Fast exit. - */ - mrs = ddr3_get_mr0(DDR3_MR0_PRECHARGE_FAST, twr, - DDR3_MR0_DLL_RESET_NO, DDR3_MR0_MODE_NORMAL, cas, - DDR3_MR0_BURST_TYPE_INTERLEAVED, - DDR3_MR0_BURST_LENGTH_CHOP); - volatile_read(vx900_get_mrs_addr(mrs)); - printram("MR0: %.5x\n", mrs); - udelay(1000); - - /* Step 13 - Set Fun3_RX6B[2:0] to 110b (Long ZQ calibration cmd) */ - pci_update_config8(MCU, 0x6b, ~0x07, 0x06); /* Long ZQ */ - /* Step 14 - Read a double word from any address of the DIMM. */ - volatile_read(0); - udelay(1000); -} - -/* - * This is where we take the DIMMs out of reset and do the JEDEC dance for each - * individual physical rank. - */ -static void vx900_dram_ddr3_dimm_init(const ramctr_timing * ctrl, - const rank_layout * ranks) -{ - size_t i; - u8 rtt_nom, rtt_wr, ods, pinswap; - - /* Set BA[0/1/2] to [A17/18/19] */ - vx900_dram_set_ma_pin_map(VX900_MRS_MA_MAP); - - /* Step 01 - Set Fun3_Rx6E[5] to 1b to support burst length. */ - pci_or_config8(MCU, 0x6e, 1 << 5); - /* Step 02 - Set Fun3_RX69[0] to 0b (Disable Multiple Page Mode). */ - pci_update_config8(MCU, 0x69, ~(1 << 0), 0x00); - /* And set [7:6] to 10b ? */ - pci_write_config8(MCU, 0x69, 0x87); - - /* Step 03 - Set the target physical rank to virtual rank0 and other - * ranks to virtual rank3. */ - vx900_pr_map_all_vr3(); - - /* Step 04 - Set Fun3_Rx50 to D8h. */ - pci_write_config8(MCU, 0x50, 0xd8); - /* Step 05 - Set Fun3_RX6B[5] to 1b to de-assert RESET# and wait for at - * least 500 us. */ - pci_or_config8(MCU, 0x6b, (1 << 5)); - udelay(500); - - /* Step 6 -> 15 - Set the target physical rank to virtual rank 0 and - * other ranks to virtual rank 3. - * Repeat Step 6 to 14 for every rank present, then jump to Step 16. */ - for (i = 0; i < VX900_MAX_MEM_RANKS; i++) { - if (ranks->phys_rank_size_mb[i] == 0) - continue; - printram("Initializing rank %zu\n", i); - - /* Set target physical rank to virtual rank 0 - * other ranks to virtual rank 3*/ - vx900_map_pr_vr(i, 0); - - /* FIXME: Is this needed on HW init? */ - pci_update_config8(MCU, 0x6b, ~0x07, 0x01); /* Enable NOP */ - volatile_read(0x0); /* Do NOP */ - pci_update_config8(MCU, 0x6b, ~0x07, 0x03); /* MSR Enable */ - - /* See init_dram_by_rank.c and get_basic_information.c - * in the VIA provided code */ - if (ctrl->n_dimms == 1) { - rtt_nom = DDR3_MR1_RTT_NOM_RZQ2; - rtt_wr = DDR3_MR2_RTTWR_OFF; - } else { - rtt_nom = DDR3_MR1_RTT_NOM_RZQ8; - rtt_wr = DDR3_MR2_RTTWR_RZQ2; - } - ods = ranks->flags[i].rzq7_supported ? - DDR3_MR1_ODS_RZQ7 : DDR3_MR1_ODS_RZQ6; - - pinswap = (ranks->flags[i].pins_mirrored); - if (pinswap) - printram("Pins mirrored\n"); - printram(" Swap : %x\n", pinswap); - printram(" rtt_nom : %x\n", rtt_nom); - printram(" ods : %x\n", ods); - printram(" rtt_wr : %x\n", rtt_wr); - if (RAMINIT_USE_HW_MRS_SEQ) - vx900_dram_ddr3_do_hw_mrs(pinswap, rtt_nom, ods, rtt_wr, - 0, 0); - else - vx900_dram_ddr3_do_sw_mrs(pinswap, rtt_nom, ods, rtt_wr, - 0, 0); - - /* Normal SDRAM Mode */ - pci_update_config8(MCU, 0x6b, ~0x07, 0x00); - - /* Step 15, set the rank to virtual rank 3 */ - vx900_map_pr_vr(i, 3); - } - - /* Step 16 - Set Fun3_Rx6B[2:0] to 000b (Normal SDRAM Mode). */ - pci_update_config8(MCU, 0x6b, ~0x07, 0x00); - - /* Set BA[0/1/2] to [A13/14/15] */ - vx900_dram_set_ma_pin_map(VX900_CALIB_MA_MAP); - - /* Step 17 - Set Fun3_Rx69[0] to 1b (Enable Multiple Page Mode). */ - pci_or_config8(MCU, 0x69, (1 << 0)); - - printram("DIMM initialization sequence complete\n"); -} - -/* - * This a small utility to send a single MRS command, but where we don't want to - * have to worry about changing the MCU mode. It gives the MCU back to us in - * normal operating mode. - */ -static void vx900_dram_send_soft_mrs(mrs_cmd_t cmd, u8 pin_swap) -{ - u32 addr; - /* Set Fun3_RX6B[2:0] to 011b (MSR Enable). */ - pci_update_config8(MCU, 0x6b, ~0x07, (3 << 0)); - /* Is this a funky rank with Address pins swapped? */ - if (pin_swap) - cmd = ddr3_mrs_mirror_pins(cmd); - /* Find the address corresponding to the MRS */ - addr = vx900_get_mrs_addr(cmd); - /* Execute the MRS */ - volatile_read(addr); - /* Set Fun3_Rx6B[2:0] to 000b (Normal SDRAM Mode). */ - pci_update_config8(MCU, 0x6b, ~0x07, 0x00); -} - -static void vx900_dram_enter_read_leveling(u8 pinswap) -{ - /* Precharge all before issuing read leveling MRS to DRAM */ - pci_update_config8(MCU, 0x06b, ~0x07, 0x02); - volatile_read(0x0); - udelay(1000); - - /* Enable read leveling: Set D0F3Rx71[7]=1 */ - pci_or_config8(MCU, 0x71, (1 << 7)); - - /* Put DRAM in read leveling mode */ - mrs_cmd_t cmd = ddr3_get_mr3(1); - vx900_dram_send_soft_mrs(cmd, pinswap); -} - -static void vx900_dram_exit_read_leveling(u8 pinswap) -{ - /* Disable read leveling, and put dram in normal operation mode */ - mrs_cmd_t cmd = ddr3_get_mr3(0); - vx900_dram_send_soft_mrs(cmd, pinswap); - - /* Disable read leveling: Set D0F3Rx71[7]=0 */ - pci_update_config8(MCU, 0x71, (u8)~(1 << 7), 0); -} - -/* - * We need to see if the delay window (difference between minimum and maximum) - * is large enough so that we actually have a valid window. The signal should be - * valid for at least 1/2T in general. If the window is significantly smaller, - * then chances are our window does not latch at the correct time, and the - * calibration will not work. - */ -#define DQSI_THRESHOLD 0x10 -#define DQO_THRESHOLD 0x09 -#define DQSO_THRESHOLD 0x12 -#define DELAY_RANGE_GOOD 0 -#define DELAY_RANGE_BAD -1 -static u8 vx900_dram_check_calib_range(const delay_range * dly, u8 window) -{ - size_t i; - for (i = 0; i < 8; i++) { - if (dly->high[i] - dly->low[i] < window) - return DELAY_RANGE_BAD; - /* When our maximum value is lower than our min, both values - * have overshot, and the window is definitely invalid */ - if (dly->high[i] < dly->low[i]) - return DELAY_RANGE_BAD; - } - return DELAY_RANGE_GOOD; -} - -static void vx900_dram_find_avg_delays(vx900_delay_calib * delays) -{ - size_t i; - u16 dq_low, dq_high, dqs_low, dqs_high, dq_final, dqs_final; - /* - * At this point, we have transmit delays for both DIMMA and DIMMB, each - * with a slightly different window We want to find the intersection of - * those windows, so that we have a constrained window which both - * DIMMA and DIMMB can use. The center of our constrained window will - * also be the safest setting for the transmit delays - * - * DIMMA window t:|xxxxxxxxxxxxxx---------------xxxxxxxxxxxxxxxxxxxxxxx| - * DIMMB window t:|xxxxxxxxxxxxxxxxxxx---------------xxxxxxxxxxxxxxxxxx| - * Safe window t:|xxxxxxxxxxxxxxxxxxx----------xxxxxxxxxxxxxxxxxxxxxxx| - */ - delay_range *tx_dq_a = &(delays->tx_dq[0]); - delay_range *tx_dq_b = &(delays->tx_dq[1]); - delay_range *tx_dqs_a = &(delays->tx_dqs[0]); - delay_range *tx_dqs_b = &(delays->tx_dqs[1]); - - for (i = 0; i < 8; i++) { - dq_low = MAX(tx_dq_a->low[i], tx_dq_b->low[i]); - dq_high = MIN(tx_dq_a->high[i], tx_dq_b->high[i]); - dqs_low = MAX(tx_dqs_a->low[i], tx_dqs_b->low[i]); - dqs_high = MIN(tx_dqs_a->high[i], tx_dqs_b->high[i]); - - /* Find the average */ - dq_final = ((dq_low + dq_high) / 2); - dqs_final = ((dqs_low + dqs_high) / 2); - - /* - * These adjustments are done in code provided by VIA. - * There is no explanation as to why this is done. - * - * We can get away without doing the DQS adjustment, but doing - * it, brings the values closer to what the vendor BIOS - * calibrates to. - */ - if ((dqs_final & 0x1f) >= 0x1c) - dqs_final -= 0x1c; - else - dqs_final += 0x04; - /* - * The DQ adjustment is more critical. If we don't do this - * adjustment our MCU won't be configured properly, and - * ram_check() will fail. - */ - if ((dq_final & 0x1f) >= 0x14) - dq_final -= 0x14; - else - dq_final += 0x0c; - - /* Store our values in the first delay */ - delays->tx_dq[0].avg[i] = dq_final; - delays->tx_dqs[0].avg[i] = dqs_final; - - } -} - -/* - * First calibration: When to receive data from the DRAM - * (MD and MDQS input delay) - * - * This calibration unfortunately does not seem to work. Whether this is due to - * a misconfigured MCU or hardware bug is unknown. - */ -static void vx900_rx_capture_range_calib(u8 pinswap) -{ - u8 reg8; - const u32 cal_addr = 0x20; - - /* Set IO calibration address */ - pci_update_config16(MCU, 0x8c, (u16)~0xfff0, cal_addr & (0xfff0)); - /* Data pattern must be 0x00 for this calibration - * See paragraph describing Rx8e */ - pci_write_config8(MCU, 0x8e, 0x00); - - /* Need to put DRAM and MCU in read leveling */ - vx900_dram_enter_read_leveling(pinswap); - - /* Data pattern must be 0x00 for this calibration - * See paragraph describing Rx8e */ - pci_write_config8(MCU, 0x8e, 0x00); - /* Trigger calibration */ - reg8 = 0xa0; - pci_write_config8(MCU, 0x71, reg8); - - /* Wait for it */ - while (pci_read_config8(MCU, 0x71) & 0x10); - vx900_dram_exit_read_leveling(pinswap); -} - -/* - * Second calibration: How much to delay DQS signal by - * (MDQS input delay) - */ -static void vx900_rx_dqs_delay_calib(u8 pinswap) -{ - const u32 cal_addr = 0x30; - - /* We need to disable refresh commands so that they don't interfere */ - const u8 ref_cnt = pci_read_config8(MCU, 0xc7); - pci_write_config8(MCU, 0xc7, 0); - /* Set IO calibration address */ - pci_update_config16(MCU, 0x8c, (u16)~0xfff0, cal_addr & (0xfff0)); - /* Data pattern must be 0x00 for this calibration - * See paragraph describing Rx8e */ - pci_write_config8(MCU, 0x8e, 0x00); - - /* Need to put DRAM and MCU in read leveling */ - vx900_dram_enter_read_leveling(pinswap); - - /* From VIA code; Undocumented - * In theory this enables MODT[3:0] to be asserted */ - pci_or_config8(MCU, 0x9e, 0x80); - - /* Trigger calibration: Set D0F3Rx71[1:0]=10b */ - pci_update_config8(MCU, 0x71, ~0x03, 0x02); - - /* Wait for calibration to complete */ - while (pci_read_config8(MCU, 0x71) & 0x02); - vx900_dram_exit_read_leveling(pinswap); - - /* Restore the refresh counter */ - pci_write_config8(MCU, 0xc7, ref_cnt); - - /* FIXME: should we save it before, or should we just set it as is */ - vx900_dram_set_ma_pin_map(VX900_CALIB_MA_MAP); -} - -static void vx900_tx_dqs_trigger_calib(u8 pattern) -{ - /* Data pattern for calibration */ - pci_write_config8(MCU, 0x8e, pattern); - /* Trigger calibration */ - pci_or_config8(MCU, 0x75, 0x20); - /* Wait for calibration */ - while (pci_read_config8(MCU, 0x75) & 0x20); -} - -/* - * Third calibration: How much to wait before asserting DQS - */ -static void vx900_tx_dqs_delay_calib(void) -{ - const u32 cal_addr = 0x00; - /* Set IO calibration address */ - pci_update_config16(MCU, 0x8c, (u16)~0xfff0, cal_addr & (0xfff0)); - /* Set circuit to use calibration results - Clear Rx75[0] */ - pci_update_config8(MCU, 0x75, ~0x01, 0); - /* Run calibration with first data pattern */ - vx900_tx_dqs_trigger_calib(0x5a); - /* Run again with different pattern */ - vx900_tx_dqs_trigger_calib(0xa5); -} - -/* - * Fourt calibration: How much to wait before putting data on DQ lines - */ -static void vx900_tx_dq_delay_calib(void) -{ - /* Data pattern for calibration */ - pci_write_config8(MCU, 0x8e, 0x5a); - /* Trigger calibration */ - pci_or_config8(MCU, 0x75, 0x02); - /* Wait for calibration */ - while (pci_read_config8(MCU, 0x75) & 0x02); -} - -static void vx900_rxdqs_adjust(delay_range * dly) -{ - /* Adjust Rx DQS delay after calibration has been run. This is - * recommended by VIA, but no explanation was provided as to why */ - size_t i; - for (i = 0; i < 8; i++) { - if (dly->low[i] < 3) { - if (i == 2 || i == 4) - dly->avg[i] += 4; - else - dly->avg[i] += 3; - - } - - if (dly->high[i] > 0x38) - dly->avg[i] -= 6; - else if (dly->high[i] > 0x30) - dly->avg[i] -= 4; - - if (dly->avg[i] > 0x20) - dly->avg[i] = 0x20; - } - - /* Put Rx DQS delay into manual mode (Set Rx[2,0] to 01) */ - pci_update_config8(MCU, 0x71, ~0x05, 0x01); - /* Now write the new settings */ - vx900_delay_calib_mode_select(CALIB_RxDQS, CALIB_MANUAL); - vx900_write_0x78_0x7f(dly->avg); -} - -static void vx900_dram_calibrate_receive_delays(vx900_delay_calib * delays, - u8 pinswap) -{ - size_t n_tries = 0; - delay_range *rx_dq_cr = &(delays->rx_dq_cr); - delay_range *rx_dqs = &(delays->rx_dqs); - /* We really should be able to finish this in a single pass, but it may - * in very rare circumstances not work the first time. We define a limit - * on the number of tries so that we have a way of warning the user */ - const size_t max_tries = 100; - for (;;) { - if (n_tries++ >= max_tries) { - die("Could not calibrate receive delays. Giving up"); - } - u8 result; - /* Run calibrations */ - if (RAMINIT_USE_HW_RXCR_CALIB) { - vx900_rx_capture_range_calib(pinswap); - vx900_read_delay_range(rx_dq_cr, CALIB_RxDQ_CR); - dump_delay_range(*rx_dq_cr); - - } else { - /*FIXME: Cheating with Rx CR setting\ - * We need to either use Rx CR calibration - * or set up a table for the calibration */ - u8 *override = &(rx_dq_cr->avg[0]); - override[0] = 0x28; - override[1] = 0x1c; - override[2] = 0x28; - override[3] = 0x28; - override[4] = 0x2c; - override[5] = 0x30; - override[6] = 0x30; - override[7] = 0x34; - printram("Bypassing RxCR 78-7f calibration with:\n"); - dump_delay(rx_dq_cr->avg); - } - /* We need to put the setting on manual mode */ - pci_or_config8(MCU, 0x71, 1 << 4); - vx900_delay_calib_mode_select(CALIB_RxDQ_CR, CALIB_MANUAL); - vx900_write_0x78_0x7f(rx_dq_cr->avg); - - /************* RxDQS *************/ - vx900_rx_dqs_delay_calib(pinswap); - vx900_read_delay_range(rx_dqs, CALIB_RxDQS); - vx900_rxdqs_adjust(rx_dqs); - - result = vx900_dram_check_calib_range(rx_dqs, DQSI_THRESHOLD); - if (result != DELAY_RANGE_GOOD) - continue; - - /* We're good to go. Switch to manual and write the manual - * setting */ - pci_or_config8(MCU, 0x71, 1 << 0); - vx900_delay_calib_mode_select(CALIB_RxDQS, CALIB_MANUAL); - vx900_write_0x78_0x7f(rx_dqs->avg); - break; - } - if (n_tries > 1) - printram("Hmm, we had to try %zu times before our calibration " - "was good.\n", n_tries); -} - -static void vx900_dram_calibrate_transmit_delays(delay_range * tx_dq, - delay_range * tx_dqs) -{ - /* Same timeout reasoning as in receive delays */ - size_t n_tries = 0; - int dq_tries = 0, dqs_tries = 0; - const size_t max_tries = 100; - for (;;) { - if (n_tries++ >= max_tries) { - printram("Tried DQS %i times and DQ %i times\n", - dqs_tries, dq_tries); - printram("Tx DQS calibration results\n"); - dump_delay_range(*tx_dqs); - printram("TX DQ delay calibration results:\n"); - dump_delay_range(*tx_dq); - die("Could not calibrate transmit delays. Giving up"); - } - u8 result; - /************* TxDQS *************/ - dqs_tries++; - vx900_tx_dqs_delay_calib(); - vx900_read_delay_range(tx_dqs, CALIB_TxDQS); - - result = vx900_dram_check_calib_range(tx_dqs, DQSO_THRESHOLD); - if (result != DELAY_RANGE_GOOD) - continue; - - /************* TxDQ *************/ - /* FIXME: not sure if multiple page mode should be enabled here - * Vendor BIOS does it */ - pci_or_config8(MCU, 0x69, 0x01); - - dq_tries++; - vx900_tx_dq_delay_calib(); - vx900_read_delay_range(tx_dq, CALIB_TxDQ); - - result = vx900_dram_check_calib_range(tx_dq, DQO_THRESHOLD); - if (result != DELAY_RANGE_GOOD) - continue; - - /* At this point, our RAM should give correct read-backs for - * addresses under 64 MB. If it doesn't, it won't work */ - if (ram_check_noprint_nodie(1 << 20, 1 << 20)) { - /* No, our RAM is not working, try again */ - /* FIXME: Except that we have not yet told the MCU what - * the geometry of the DIMM is, hence we don't trust - * this test for now */ - } - /* Good. We should be able to use this DIMM */ - /* That's it. We're done */ - break; - } - if (n_tries > 1) - printram("Hmm, we had to try %zu times before our calibration " - "was good.\n", n_tries); -} - -/* - * The meat and potatoes of getting our MCU to operate the DIMMs properly. - * - * Thank you JEDEC for making us need configurable delays for each set of MD - * signals. - */ -static void vx900_dram_calibrate_delays(const ramctr_timing * ctrl, - const rank_layout * ranks) -{ - size_t i; - u8 val; - u8 dimm; - vx900_delay_calib delay_cal; - memset(&delay_cal, 0, sizeof(delay_cal)); - printram("Starting delay calibration\n"); - - /**** Read delay control ****/ - /* MD Input Data Push Timing Control; - * use values recommended in datasheet - * Setting this too low causes the Rx window to move below the range we - * need it so we can capture it with Rx_78_7f - * This causes Rx calibrations to be too close to 0, and Tx - * calibrations will fail. - * Setting this too high causes the window to move above the range. - */ - if (ctrl->tCK <= TCK_533MHZ) - val = 2; - else if (ctrl->tCK <= TCK_333MHZ) - val = 1; - else - val = 0; - val++; /* FIXME: vendor BIOS sets this to 3 */ - pci_update_config8(MCU, 0x74, ~(0x03 << 1), ((val & 0x03) << 1)); - - /* FIXME: The vendor BIOS increases the MD input delay - WHY ? */ - pci_update_config8(MCU, 0xef, ~(3 << 4), 3 << 4); - - /**** Write delay control ****/ - /* FIXME: The vendor BIOS does this, but WHY? - * See check_special_registers in VIA provided code. This value seems - * to depend on the DRAM frequency. - */ - /* Early DQ/DQS for write cycles */ - pci_update_config8(MCU, 0x76, ~(3 << 2), 2 << 2); - /* FIXME: The vendor BIOS does this - Output preamble ? */ - pci_write_config8(MCU, 0x77, 0x10); - - /* Set BA[0/1/2] to [A17/18/19] */ - vx900_dram_set_ma_pin_map(VX900_MRS_MA_MAP); - /* Disable Multiple Page Mode - Set Rx69[0] to 0 */ - pci_update_config8(MCU, 0x69, ~(1 << 0), 0x00); - - /* It's very important that we keep all ranks which are not calibrated - * mapped to VR3. Even if we disable them, if they are mapped to VR0 - * (the rank we use for calibrations), the calibrations may fail in - * unexpected ways. */ - vx900_pr_map_all_vr3(); - - /* We only really need to run the receive calibrations once. They are - * meant to account for signal travel differences in the internal paths - * of the MCU, so it doesn't really matter which rank we use for this. - * Differences between ranks will be accounted for in the transmit - * calibration. */ - for (i = 0; i < VX900_MAX_DIMM_SLOTS; i += 2) { - /* Do we have a valid DIMM? */ - if (ranks->phys_rank_size_mb[i] + - ranks->phys_rank_size_mb[i + 1] == 0) - continue; - /* Map the first rank of the DIMM to VR0 */ - vx900_map_pr_vr(2 * i, 0); - /* Only run on first rank, remember? */ - break; - } - vx900_dram_calibrate_receive_delays(&delay_cal, - ranks->flags[i].pins_mirrored); - printram("RX DQS calibration results\n"); - dump_delay_range(delay_cal.rx_dqs); - - /* Enable multiple page mode for when calibrating transmit delays */ - pci_or_config8(MCU, 0x69, 1 << 1); - - /* - * Unlike the receive delays, we need to run the transmit calibration - * for each DIMM (not rank). We run the calibration on the even rank. - * The odd rank may have memory pins swapped, and this, it seems, - * confuses the calibration circuit. - */ - dimm = 0; - for (i = 0; i < VX900_MAX_DIMM_SLOTS; i++) { - /* Do we have a valid DIMM? */ - u32 dimm_size_mb = ranks->phys_rank_size_mb[2 * i] - + ranks->phys_rank_size_mb[2 * i + 1]; - if (dimm_size_mb == 0) - continue; - /* Map the first rank of the DIMM to VR0 */ - vx900_map_pr_vr(2 * i, 0); - vx900_dram_calibrate_transmit_delays(&(delay_cal.tx_dq[dimm]), - &(delay_cal.tx_dqs[dimm])); - /* We run this more than once, so dump delays for each DIMM */ - printram("Tx DQS calibration results\n"); - dump_delay_range(delay_cal.tx_dqs[dimm]); - printram("TX DQ delay calibration results:\n"); - dump_delay_range(delay_cal.tx_dq[dimm]); - /* Now move the DIMM back to VR3 */ - vx900_map_pr_vr(2 * i, 3); - /* We use dimm as a counter so that we fill tx_dq[] and tx_dqs[] - * results in order from 0, and do not leave any gaps */ - dimm++; - } - - /* When we have more dimms, we need to find a tx window with which all - * dimms can safely work */ - if (dimm > 1) { - vx900_dram_find_avg_delays(&delay_cal); - printram("Final delay values\n"); - printram("Tx DQS: "); - dump_delay(delay_cal.tx_dqs[0].avg); - printram("Tx DQ: "); - dump_delay(delay_cal.tx_dq[0].avg); - } - /* Write manual settings */ - pci_or_config8(MCU, 0x75, 0x01); - vx900_delay_calib_mode_select(CALIB_TxDQS, CALIB_MANUAL); - vx900_write_0x78_0x7f(delay_cal.tx_dqs[0].avg); - vx900_delay_calib_mode_select(CALIB_TxDQ, CALIB_MANUAL); - vx900_write_0x78_0x7f(delay_cal.tx_dq[0].avg); -} - -static void vx900_dram_set_refresh_counter(ramctr_timing * ctrl) -{ - u8 reg8; - /* Set DRAM refresh counter - * Based on a refresh counter of 0x61 at 400MHz */ - reg8 = (TCK_400MHZ * 0x61) / ctrl->tCK; - pci_write_config8(MCU, 0xc7, reg8); -} - -/* - * Here, we map each rank somewhere in our address space. We don't really care - * at this point if this will overlap the PCI config space. If needed, remapping - * is done in ramstage, where we actually know how much PCI space we actually - * need. - */ -static void vx900_dram_range(ramctr_timing * ctrl, rank_layout * ranks) -{ - size_t i, vrank = 0; - u8 reg8; - u32 ramsize_mb = 0, tolm_mb; - const u32 TOLM_3_5G = (7 << 29); - /* All unused physical ranks go to VR3. Otherwise, the MCU might be - * trying to read or write from unused ranks, or even worse, write some - * bits to the rank we want, and some to the unused ranks, even though - * they are disabled. Since VR3 is the last virtual rank to be used, we - * eliminate any ambiguities that the MCU may face. */ - vx900_pr_map_all_vr3(); - for (i = 0; i < VX900_MAX_MEM_RANKS; i++) { - u32 rank_size_mb = ranks->phys_rank_size_mb[i]; - if (!rank_size_mb) - continue; - - /* vvvvvvvvvv FIXME: Fix odd rank init vvvvvvvvvv */ - if ((i & 1)) { - printk(BIOS_EMERG, "I cannot initialize rank %zu\n", i); - printk(BIOS_EMERG, "I have to disable it\n"); - continue; - } - /* ^^^^^^^^^^ FIXME: Fix odd rank init ^^^^^^^^^^ */ - - ranks->virt[vrank].start_addr = ramsize_mb; - ramsize_mb += rank_size_mb; - ranks->virt[vrank].end_addr = ramsize_mb; - - /* Rank memory range */ - reg8 = (ranks->virt[vrank].start_addr >> 6); - pci_write_config8(MCU, 0x48 + vrank, reg8); - reg8 = (ranks->virt[vrank].end_addr >> 6); - pci_write_config8(MCU, 0x40 + vrank, reg8); - - vx900_map_pr_vr(i, vrank); - - printram("Mapped Physical rank %u, to virtual rank %u\n" - " Start address: 0x%.10llx\n" - " End address: 0x%.10llx\n", - (int)i, (int)vrank, - (u64) ranks->virt[vrank].start_addr << 20, - (u64) ranks->virt[vrank].end_addr << 20); - /* Move on to next virtual rank */ - vrank++; - } - - /* Limit the Top of Low memory at 3.5G - * Not to worry, we'll set tolm in ramstage, once we have initialized - * all devices and know pci_tolm. */ - tolm_mb = MIN(ramsize_mb, TOLM_3_5G >> 20); - u16 reg_tolm = (tolm_mb << 4) & 0xfff0; - pci_update_config16(MCU, 0x84, (u16)~0xfff0, reg_tolm); - - printram("Initialized %u virtual ranks, with a total size of %u MB\n", - (int)vrank, ramsize_mb); -} - -/* - * Here, we tell the memory controller how to treat a DIMM. This is an extremely - * important step. It tells the MCU how many address bits we have in each DIMM, - * and how to use them. This information is essential for the controller to - * understand the DIMM addressing, and write and read data in the correct place. - */ -static void vx900_dram_map_row_col_bank(dimm_info * dimms) -{ - u8 reg8, rcb_val, col_bits, max_row_bits; - size_t i; - /* Do we have 4Gbit chips? */ - /* FIXME: Implement this */ - - /* Do we have 8Gbit chips? */ - /* FIXME: Implement this */ - - max_row_bits = rcb_val = reg8 = 0; - for (i = 0; i < VX900_MAX_DIMM_SLOTS; i++) { - if (dimms->dimm[i].dram_type == SPD_MEMORY_TYPE_UNDEFINED) - continue; - - col_bits = dimms->dimm[i].col_bits; - - /* - * DDR3 always uses 3 bank address bits, and MA type 111b cannot - * be used due to chipset limitation. We are left with only two - * options, which we can choose based solely on the number of - * column address bits. - */ - if ((col_bits < 10) || (col_bits > 11)) { - printram("DIMM %zd has %d column address bits.\n", - i, col_bits); - die("Unsupported DIMM. Try booting without this DIMM"); - } - - rcb_val = col_bits - 5; - reg8 |= (rcb_val << ((i * 3) + 2)); - - /* */ - max_row_bits = MAX(max_row_bits, dimms->dimm[i].row_bits); - } - - printram("RCBA map (rx50) <- %.2x\n", reg8); - pci_write_config8(MCU, 0x50, reg8); - - printram("Houston, we have %d row address bits\n", max_row_bits); - /* FIXME: Do this properly */ - vx900_dram_map_pins(13, 14, 15, 17, 16); - -} - -/* - * Here, we set some final configuration bits, which should improve the - * performance of the memory slightly (arbitration, expiration counters, etc.) - * - * FIXME: We don't really do much else than the minimum to get the MCU properly - * configured. We don't yet do set the "performance-enhancing" bits referenced - * in the comment above. - */ -static void vx900_dram_write_final_config(ramctr_timing * ctrl) -{ - /* FIXME: These are quick cheats */ - - /* FIXME: Why are we doing this? */ - /* Tri-state MCSi# when rank is in self-refresh */ - pci_or_config8(MCU, 0x99, 0x0f); - - /* Enable paging mode and 8 page registers */ - pci_or_config8(MCU, 0x69, 0xe5); - - /* Enable automatic triggering of short ZQ calibration */ - pci_write_config8(MCU, 0xc8, 0x80); - - /* And last but not least, Enable A20 line */ - outb(inb(0x92) | (1 << 1), 0x92); -} - -void vx900_init_dram_ddr3(const dimm_layout * dimm_addr) -{ - dimm_info dimm_prop; - ramctr_timing ctrl_prop; - rank_layout ranks; - pci_devfn_t mcu; - - if (!ram_check_noprint_nodie(1 << 20, 1 << 20)) { - printram("RAM is already initialized. Skipping init\n"); - return; - } - /* Locate the Memory controller */ - mcu = pci_locate_device(PCI_ID(PCI_VENDOR_ID_VIA, - PCI_DEVICE_ID_VIA_VX900_MEMCTRL), 0); - - if (mcu == PCI_DEV_INVALID) { - die("Memory Controller not found\n"); - } - memset(&dimm_prop, 0, sizeof(dimm_prop)); - memset(&ctrl_prop, 0, sizeof(ctrl_prop)); - memset(&ranks, 0, sizeof(ranks)); - /* 1) Write some initial "safe" parameters */ - vx900_dram_write_init_config(); - /* 2) Get timing information from SPDs */ - dram_find_spds_ddr3(dimm_addr, &dimm_prop); - /* 3) Find lowest common denominator for all modules */ - dram_find_common_params(&dimm_prop, &ctrl_prop); - /* 4) Find the size of each memory rank */ - vx900_dram_phys_bank_range(&dimm_prop, &ranks); - /* 5) Set DRAM driving strength */ - vx900_dram_driving_ctrl(&dimm_prop); - /* 6) Set DRAM frequency and latencies */ - vx900_dram_timing(&ctrl_prop); - vx900_dram_freq(&ctrl_prop); - /* 7) Initialize the modules themselves */ - vx900_dram_ddr3_dimm_init(&ctrl_prop, &ranks); - /* 8) Set refresh counter based on DRAM frequency */ - vx900_dram_set_refresh_counter(&ctrl_prop); - /* 9) Calibrate receive and transmit delays */ - vx900_dram_calibrate_delays(&ctrl_prop, &ranks); - /* 10) Enable Physical to Virtual Rank mapping */ - vx900_dram_range(&ctrl_prop, &ranks); - /* 11) Map address bits to DRAM pins */ - vx900_dram_map_row_col_bank(&dimm_prop); - /* 99) Some final adjustments */ - vx900_dram_write_final_config(&ctrl_prop); - /* Take a dump */ - dump_pci_device(mcu); -} diff --git a/src/northbridge/via/vx900/romstrap.S b/src/northbridge/via/vx900/romstrap.S deleted file mode 100644 index 26c1ee694a..0000000000 --- a/src/northbridge/via/vx900/romstrap.S +++ /dev/null @@ -1,56 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2004 Tyan Computer - * (Written by Yinghai Lu for Tyan Computer) - * Copyright (C) 2007 Rudolf Marek - * Copyright (C) 2009 One Laptop per Child, Association, Inc. - * Copyright (C) 2011-2012 Alexandru Gagniuc - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -/* As extracted from the manufacturer's ROM, the romstrap table looks like: - * .long 0x77886047 .long 0x00777777 - * .long 0x00000000 .long 0x00000000 - * .long 0x00888888 .long 0x00AA1111 - * .long 0x00000000 .long 0x00000000 - * - * The vendor BIOS then adjusts some of these settings very early on. Instead of - * adjusting those settings in code, we work them in the romstrap table. - * - */ -/* This file constructs the ROM strap table for VX900 */ - - .section ".romstrap", "a", @progbits - - .globl __romstrap_start -__romstrap_start: -tblpointer: - .long 0x77886047 - .long 0x00777777 - .long 0x00000000 - .long 0x00000000 - .long 0x00888888 - .long 0x00AA1111 - .long 0x00000000 - .long 0x00000000 - -/* - * The pointer to above table should be at 0xffffffd0, - * the table itself MUST be aligned to 128B it seems! - */ -rspointers: - .long tblpointer // It will be 0xffffffd0 - - .globl __romstrap_end - -__romstrap_end: -.previous diff --git a/src/northbridge/via/vx900/romstrap.ld b/src/northbridge/via/vx900/romstrap.ld deleted file mode 100644 index 0217f41b87..0000000000 --- a/src/northbridge/via/vx900/romstrap.ld +++ /dev/null @@ -1,24 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007 AMD - * (Written by Yinghai Lu for AMD) - * Copyright (C) 2011 Alexandru Gagniuc - * - * This program is free software: you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -SECTIONS { - . = (0x100000000 - 0x2c) - (__romstrap_end - __romstrap_start); - .romstrap (.): { - KEEP(*(.romstrap)) - } -} diff --git a/src/northbridge/via/vx900/sata.c b/src/northbridge/via/vx900/sata.c deleted file mode 100644 index 791133142f..0000000000 --- a/src/northbridge/via/vx900/sata.c +++ /dev/null @@ -1,275 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2012 Alexandru Gagniuc - * - * This program is free software: you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include -#include - -#include "vx900.h" - -/** - * @file vx900/sata.c - * - * STATUS: Pretty good - * The only issue is the SATA EPHY configuration. We do not know if it is board - * specific or not. Otherwise, the SATA controller works without issues. - */ - -static void vx900_print_sata_errors(u32 flags) -{ - /* Status flags */ - printk(BIOS_DEBUG, "\tPhyRdy %s\n", - (flags & (1 << 16)) ? "changed" : "not changed"); - printk(BIOS_DEBUG, "\tCOMWAKE %s\n", - (flags & (1 << 16)) ? "detected" : "not detected"); - printk(BIOS_DEBUG, "\tExchange as determined by COMINIT %s\n", - (flags & (1 << 26)) ? "occurred" : "not occurred"); - printk(BIOS_DEBUG, "\tPort selector presence %s\n", - (flags & (1 << 27)) ? "detected" : "not detected"); - /* Errors */ - if (flags & (1 << 0)) - printk(BIOS_DEBUG, "\tRecovered data integrity ERROR\n"); - if (flags & (1 << 1)) - printk(BIOS_DEBUG, "\tRecovered data communication ERROR\n"); - if (flags & (1 << 8)) - printk(BIOS_DEBUG, "\tNon-recovered Transient Data Integrity ERROR\n"); - if (flags & (1 << 9)) - printk(BIOS_DEBUG, "\tNon-recovered Persistent Communication or" - "\tData Integrity ERROR\n"); - if (flags & (1 << 10)) - printk(BIOS_DEBUG, "\tProtocol ERROR\n"); - if (flags & (1 << 11)) - printk(BIOS_DEBUG, "\tInternal ERROR\n"); - if (flags & (1 << 17)) - printk(BIOS_DEBUG, "\tPHY Internal ERROR\n"); - if (flags & (1 << 19)) - printk(BIOS_DEBUG, "\t10B to 8B Decode ERROR\n"); - if (flags & (1 << 20)) - printk(BIOS_DEBUG, "\tDisparity ERROR\n"); - if (flags & (1 << 21)) - printk(BIOS_DEBUG, "\tCRC ERROR\n"); - if (flags & (1 << 22)) - printk(BIOS_DEBUG, "\tHandshake ERROR\n"); - if (flags & (1 << 23)) - printk(BIOS_DEBUG, "\tLink Sequence ERROR\n"); - if (flags & (1 << 24)) - printk(BIOS_DEBUG, "\tTransport State Transition ERROR\n"); - if (flags & (1 << 25)) - printk(BIOS_DEBUG, "\tUNRECOGNIZED FIS type\n"); -} - -static void vx900_dbg_sata_errors(struct device *dev) -{ - /* Port 0 */ - if (pci_read_config8(dev, 0xa0) & (1 << 0)) { - printk(BIOS_DEBUG, "Device detected in SATA port 0.\n"); - u32 flags = pci_read_config32(dev, 0xa8); - vx900_print_sata_errors(flags); - }; - /* Port 1 */ - if (pci_read_config8(dev, 0xa1) & (1 << 0)) { - printk(BIOS_DEBUG, "Device detected in SATA port 1.\n"); - u32 flags = pci_read_config32(dev, 0xac); - vx900_print_sata_errors(flags); - }; -} - -typedef u8 sata_phy_config[64]; - -static sata_phy_config reference_ephy = { - 0x80, 0xb8, 0xf0, 0xfe, 0x40, 0x7e, 0xf6, 0xdd, - 0x1a, 0x22, 0xa0, 0x10, 0x02, 0xa9, 0x7c, 0x7e, - 0x00, 0x00, 0x00, 0x00, 0x40, 0x30, 0x84, 0x8c, - 0x75, 0x26, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x20, 0x40, 0xd0, 0x41, 0x40, 0x00, 0x00, 0x08, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x20, 0x40, 0x50, 0x41, 0x40, 0x00, 0x00, 0x00, - 0x00, 0x18, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -}; - -static u32 sata_phy_read32(struct device *dev, u8 index) -{ - /* The SATA PHY control registers are accessed by a funny index/value - * scheme. Each byte (0,1,2,3) has its own 4-bit index */ - index = (index >> 2) & 0xf; - u16 i16 = index | (index << 4) | (index << 8) | (index << 12); - /* The index */ - pci_write_config16(dev, 0x68, i16); - /* The value */ - return pci_read_config32(dev, 0x64); -} - -static void sata_phy_write32(struct device *dev, u8 index, u32 val) -{ - /* The SATA PHY control registers are accessed by a funny index/value - * scheme. Each byte (0,1,2,3) has its own 4-bit index */ - index = (index >> 2) & 0xf; - u16 i16 = index | (index << 4) | (index << 8) | (index << 12); - /* The index */ - pci_write_config16(dev, 0x68, i16); - /* The value */ - pci_write_config32(dev, 0x64, val); -} - -static void vx900_sata_read_phy_config(struct device *dev, sata_phy_config cfg) -{ - size_t i; - u32 *data = (u32 *) cfg; - for (i = 0; i < (sizeof(sata_phy_config)) >> 2; i++) { - data[i] = sata_phy_read32(dev, i << 2); - } -} - -static void vx900_sata_write_phy_config(struct device *dev, sata_phy_config cfg) -{ - size_t i; - u32 *data = (u32 *) cfg; - for (i = 0; i < (sizeof(sata_phy_config)) >> 2; i++) { - sata_phy_write32(dev, i << 2, data[i]); - } -} - -static void vx900_sata_dump_phy_config(sata_phy_config cfg) -{ - printk(BIOS_DEBUG, "SATA PHY config:\n"); - int i; - for (i = 0; i < sizeof(sata_phy_config); i++) { - unsigned char val; - if ((i & 0x0f) == 0) - printk(BIOS_DEBUG, "%02x:", i); - val = cfg[i]; - if ((i & 7) == 0) - printk(BIOS_DEBUG, " |"); - printk(BIOS_DEBUG, " %02x", val); - if ((i & 0x0f) == 0x0f) { - printk(BIOS_DEBUG, "\n"); - } - } -} - -/** - * \brief VX900: Place the onboard SATA controller in Native IDE mode - * - * AHCI mode requires a sub-class of 0x06, and Interface of 0x0 - * SATA mode requires a sub-class of 0x06, and Interface of 0x00 - * Unfortunately, setting the class to SATA, will prevent us from modyfing the - * interface register to an AHCI/SATA compliant value. Thus, payloads or OS may - * not properly identify this as a SATA controller. - * We could set the class code to 0x04, which would cause the interface register - * to become 0x00, which represents a RAID controller. Unfortunately, when we do - * this, SeaBIOS will skip this as a storage device, and we will not be able to - * boot. - * Our only option is to operate in IDE mode. We choose native IDE so that we - * can freely assign an IRQ, and are not forced to use IRQ14 - */ -static void vx900_native_ide_mode(struct device *dev) -{ - /* Disable subclass write protect */ - pci_update_config8(dev, 0x45, (u8)~(1 << 7), 0); - /* Change the device class to IDE */ - pci_write_config16(dev, PCI_CLASS_DEVICE, PCI_CLASS_STORAGE_IDE); - /* Re-enable subclass write protect */ - pci_or_config8(dev, 0x45, 1 << 7); - /* Put it in native IDE mode */ - pci_write_config8(dev, PCI_CLASS_PROG, 0x8f); -} - -static void vx900_sata_init(struct device *dev) -{ - /* Enable SATA primary channel IO access */ - pci_or_config8(dev, 0x40, 1 << 1); - /* Just SATA, so it makes sense to be in native SATA mode */ - vx900_native_ide_mode(dev); - - /* TP Layer Idle at least 20us before the Following Command */ - pci_or_config8(dev, 0x53, 1 << 7); - /* Resend COMRESET When Recovering SATA Gen2 Device Error */ - pci_update_config8(dev, 0x62, ~(1 << 1), 1 << 7); - - /* Fix "PMP Device Can't Detect HDD Normally" (VIA Porting Guide) - * SATA device detection will not work unless we clear these bits. - * Without doing this, SeaBIOS (and potentially other payloads) will - * timeout when detecting SATA devices */ - pci_update_config8(dev, 0x89, ~(1 << 3) | (1 << 6), 0); - - /* 12.7 Two Software Resets May Affect the System - * When the software does the second reset before the first reset - * finishes, it may cause the system hang. It would do one software - * reset and check the BSY bit of one port only, and the BSY bit of - * other port would be 1, then it does another software reset - * immediately and causes the system hang. - * This is because the first software reset doesn't finish, and the - * state machine of the host controller conflicts, it can't finish the - * second one anymore. The BSY bit of slave port would be always 1 after - * the second software reset issues. BIOS should set the following - * bit to avoid this issue. */ - pci_or_config8(dev, 0x80, 1 << 6); - - /* We need to set the EPHY values before doing anything with the link */ - sata_phy_config ephy; - vx900_sata_read_phy_config(dev, ephy); - if (1) { - vx900_sata_dump_phy_config(ephy); - vx900_sata_write_phy_config(dev, reference_ephy); - } else { - /* Enable TX and RX driving resistance */ - /* TX - 50 Ohm */ - ephy[1] &= ~(0x1f << 3); - ephy[1] |= (1 << 7) | (8 << 3); - /* RX - 50 Ohm */ - ephy[2] &= ~(0x1f << 3); - ephy[2] |= (1 << 7) | (8 << 3); - vx900_sata_write_phy_config(dev, ephy); - } - - vx900_sata_read_phy_config(dev, ephy); - vx900_sata_dump_phy_config(ephy); - - /* Clear error flags */ - pci_write_config32(dev, 0xa8, 0xffffffff); - pci_write_config32(dev, 0xac, 0xffffffff); - - /* Start OOB link negotiation sequence */ - pci_or_config8(dev, 0xb9, 3 << 4); - - /* FIXME: From now on, we are just doing DEBUG stuff - * Wait until PHY communication is enabled */ - u32 wloops = 0; - while (!(pci_read_config8(dev, 0xa0) & (1 << 1))) - wloops++; - printk(BIOS_SPEW, "SATA wait loops: %u\n", wloops); - - vx900_dbg_sata_errors(dev); -} - -static void vx900_sata_read_resources(struct device *dev) -{ - pci_dev_read_resources(dev); -} - -static struct device_operations vga_operations = { - .read_resources = vx900_sata_read_resources, - .set_resources = pci_dev_set_resources, - .enable_resources = pci_dev_enable_resources, - .init = vx900_sata_init, -}; - -static const struct pci_driver chrome9hd_driver __pci_driver = { - .ops = &vga_operations, - .vendor = PCI_VENDOR_ID_VIA, - .device = PCI_DEVICE_ID_VIA_VX900_SATA, -}; diff --git a/src/northbridge/via/vx900/traf_ctrl.c b/src/northbridge/via/vx900/traf_ctrl.c deleted file mode 100644 index 2ef542afb8..0000000000 --- a/src/northbridge/via/vx900/traf_ctrl.c +++ /dev/null @@ -1,142 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2012 Alexandru Gagniuc - * - * This program is free software: you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include -#include -#include - -#include "vx900.h" -#include "chip.h" - -/** - * @file vx900/traf_ctrl.c - * - * STATUS: - * The same issues with the IOAPIC pointe in lpc.c also apply here. - * - * We need to check if the current PCIE lane configuration mechanism is sane. - */ - -/** - * \brief VX900: Set up the north module IOAPIC (for PCIE and VGA) - * - * Enable the IOAPIC in the south module, and properly set it up. - * \n - * This is the hardware specific initialization for the IOAPIC, and complements - * the setup done by the generic IOAPIC driver. In order for the IOAPIC to work - * properly, it _must_ be declared in devicetree.cb . - * \n - * We are assuming this is called before the drivers/generic/ioapic code, - * which should be the case if devicetree.cb is set up properly. - */ -static void vx900_north_ioapic_setup(struct device *dev) -{ - u8 base_val; - struct device *ioapic; - ioapic_config_t *config; - /* Find the IOAPIC, and make sure it's set up correctly in devicetree.cb - * If it's not, then the generic ioapic driver will not set it up - * correctly, and the MP table will not be correctly generated */ - for (ioapic = dev->next; ioapic; ioapic = ioapic->next) { - if (ioapic->path.type == DEVICE_PATH_IOAPIC) - break; - } - /* You did put an IOAPIC in devicetree.cb, didn't you? */ - if (ioapic == 0) { - /* We don't have enough info to set up the IOAPIC */ - printk(BIOS_ERR, "ERROR: North module IOAPIC not found. " - "Check your devicetree.cb\n"); - return; - } - /* Found our IOAPIC, and it should not carry ISA interrupts */ - config = (ioapic_config_t *) ioapic->chip_info; - if (config->have_isa_interrupts) { - /* Umh, is this the right IOAPIC ? */ - printk(BIOS_ERR, "ERROR: North module IOAPIC should not carry " - "ISA interrupts.\n" "Check your devicetree.cb\n"); - printk(BIOS_ERR, "Will not initialize this IOAPIC.\n"); - return; - } - /* The base address of this IOAPIC _must_ - * be between 0xfec00000 and 0xfecfff00 - * be 256-byte aligned - */ - if ((config->base < (void *)0xfec0000 || config->base > (void *)0xfecfff00) - || (((uintptr_t)config->base & 0xff) != 0)) { - printk(BIOS_ERR, "ERROR: North module IOAPIC base should be " - "between 0xfec00000 and 0xfecfff00\n" - "and must be aligned to a 256-byte boundary, " - "but we found it at 0x%p\n", config->base); - return; - } - - printk(BIOS_DEBUG, "VX900 TRAF_CTR: Setting up the north module IOAPIC " - "at %p\n", config->base); - - /* First register of the IOAPIC base */ - base_val = (((uintptr_t)config->base) >> 8) & 0xff; - pci_write_config8(dev, 0x41, base_val); - /* Second register of the base. - * Bit[7] also enables the IOAPIC and bit[5] enables MSI cycles */ - base_val = (((uintptr_t)config->base) >> 16) & 0xf; - pci_or_config8(dev, 0x40, base_val | (1 << 7) | (1 << 5)); -} - -/* - * Configures the PCI-express ports - * - * FIXME: triple-quadruple-check this - */ -static void vx900_pex_link_setup(struct device *dev) -{ - u8 reg8; - struct northbridge_via_vx900_config *nb = (void *)dev->chip_info; - - reg8 = pci_read_config8(dev, 0xb0); - reg8 &= ~((1 << 7) | (1 << 3)); - - if (nb->assign_pex_to_dp) - reg8 |= (1 << 7); - - if (!nb->pcie_port1_2_lane_wide) - reg8 |= (1 << 3); - - pci_write_config8(dev, 0xb0, reg8); -} - -static void vx900_traf_ctr_init(struct device *dev) -{ - vx900_north_ioapic_setup(dev); - vx900_pex_link_setup(dev); -} - -static struct device_operations traf_ctrl_ops = { - .read_resources = pci_dev_read_resources, - .set_resources = pci_dev_set_resources, - .enable_resources = pci_dev_enable_resources, - .init = vx900_traf_ctr_init, - /* Need this here, or the IOAPIC driver won't be called. - * FIXME: Technically not a LPC bus. */ - .scan_bus = scan_static_bus, -}; - -static const struct pci_driver traf_ctrl_driver __pci_driver = { - .ops = &traf_ctrl_ops, - .vendor = PCI_VENDOR_ID_VIA, - .device = PCI_DEVICE_ID_VIA_VX900_TRAF, -}; diff --git a/src/northbridge/via/vx900/vx900.h b/src/northbridge/via/vx900/vx900.h deleted file mode 100644 index 1f611535aa..0000000000 --- a/src/northbridge/via/vx900/vx900.h +++ /dev/null @@ -1,44 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 Alexandru Gagniuc - * - * This program is free software: you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ -#ifndef __VX900_H -#define __VX900_H - -#define VX900_ACPI_IO_BASE 0x0400 - -#define SMBUS_IO_BASE 0x500 - -#define VX900_MMCONFIG_MBAR 0xbc - -/* The maximum number of DIMM slots that the VX900 supports */ -#define VX900_MAX_DIMM_SLOTS 2 -#define VX900_MAX_MEM_RANKS 4 - -#include -#include - -u32 vx900_get_tolm(void); -void vx900_set_chrome9hd_fb_size(u32 size_mb); -u8 vx900_get_chrome9hd_fb_pow(void); -u32 vx900_get_chrome9hd_fb_size(void); -u8 vx900_int15_get_5f18_bl(void); -uint64_t get_uma_memory_base(void); - -/* We use these throughout the code. They really belong in a generic part of - * coreboot, but until bureaucracy gets them there, we still need them */ - -void dump_pci_device(pci_devfn_t dev); - -#endif /* __VX900_H */ From e8fd6e9c6fa84f0c50970b378a6fd35977cb7c2b Mon Sep 17 00:00:00 2001 From: Arthur Heymans Date: Tue, 19 Nov 2019 17:25:34 +0100 Subject: [PATCH 0287/1242] sb/via/common: Drop unused code MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Change-Id: I803b9bba4067435e471e9565d3286f11a0a361a3 Signed-off-by: Arthur Heymans Reviewed-on: https://review.coreboot.org/c/coreboot/+/36960 Reviewed-by: Kyösti Mälkki Reviewed-by: Angel Pons Reviewed-by: HAOUAS Elyes Reviewed-by: Nico Huber Tested-by: build bot (Jenkins) --- .../via/common/early_smbus_delay.c | 26 ---------- .../via/common/early_smbus_is_busy.c | 31 ----------- .../via/common/early_smbus_print_error.c | 51 ------------------- .../via/common/early_smbus_read_byte.c | 51 ------------------- .../via/common/early_smbus_reset.c | 30 ----------- .../via/common/early_smbus_wait_until_ready.c | 42 --------------- src/southbridge/via/common/via_early_smbus.h | 51 ------------------- 7 files changed, 282 deletions(-) delete mode 100644 src/southbridge/via/common/early_smbus_delay.c delete mode 100644 src/southbridge/via/common/early_smbus_is_busy.c delete mode 100644 src/southbridge/via/common/early_smbus_print_error.c delete mode 100644 src/southbridge/via/common/early_smbus_read_byte.c delete mode 100644 src/southbridge/via/common/early_smbus_reset.c delete mode 100644 src/southbridge/via/common/early_smbus_wait_until_ready.c delete mode 100644 src/southbridge/via/common/via_early_smbus.h diff --git a/src/southbridge/via/common/early_smbus_delay.c b/src/southbridge/via/common/early_smbus_delay.c deleted file mode 100644 index c75152c3a7..0000000000 --- a/src/southbridge/via/common/early_smbus_delay.c +++ /dev/null @@ -1,26 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011-2013 Alexandru Gagniuc - * - * This program is free software: you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include - -/** - * \brief Brief delay for SMBus transactions - */ -void smbus_delay(void) -{ - inb(0x80); -} diff --git a/src/southbridge/via/common/early_smbus_is_busy.c b/src/southbridge/via/common/early_smbus_is_busy.c deleted file mode 100644 index 8321a55bd5..0000000000 --- a/src/southbridge/via/common/early_smbus_is_busy.c +++ /dev/null @@ -1,31 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2013 Alexandru Gagniuc - * - * This program is free software: you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include - -#include "via_early_smbus.h" - -/** - * \brief Checks if the SMBus is currently busy with a transaction - * - * @param smbus_dev The base SMBus IO port - */ -int smbus_is_busy(u32 smbus_dev) -{ - /* Check if bit 0 of the status register is 1 (busy) or 0 (ready) */ - return ((inb(SMBHSTSTAT(smbus_dev)) & (1 << 0)) == 1); -} diff --git a/src/southbridge/via/common/early_smbus_print_error.c b/src/southbridge/via/common/early_smbus_print_error.c deleted file mode 100644 index cf65b2ec59..0000000000 --- a/src/southbridge/via/common/early_smbus_print_error.c +++ /dev/null @@ -1,51 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2013 Alexandru Gagniuc - * - * This program is free software: you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include - -#include "via_early_smbus.h" - -/** - * \brief Print an error, should it occur. If no error, just exit. - * - * @param smbus_dev The base SMBus IO port - * @param host_status The data returned on the host status register after - * a transaction is processed. - * @param loops The number of times a transaction was attempted. - * @return 0 if no error occurred - * 1 if an error was detected - */ -int smbus_print_error(u32 smbus_dev, u8 host_status, int loops) -{ - /* Check if there actually was an error. */ - if ((host_status == 0x00 || host_status == 0x40 || - host_status == 0x42) && (loops < SMBUS_TIMEOUT)) - return 0; - - if (loops >= SMBUS_TIMEOUT) - printsmbus("SMBus timeout\n"); - if (host_status & (1 << 4)) - printsmbus("Interrupt/SMI# was Failed Bus Transaction\n"); - if (host_status & (1 << 3)) - printsmbus("Bus error\n"); - if (host_status & (1 << 2)) - printsmbus("Device error\n"); - if (host_status & (1 << 1)) - printsmbus("Interrupt/SMI# completed successfully\n"); - if (host_status & (1 << 0)) - printsmbus("Host busy\n"); - return 1; -} diff --git a/src/southbridge/via/common/early_smbus_read_byte.c b/src/southbridge/via/common/early_smbus_read_byte.c deleted file mode 100644 index 4f6e29e71b..0000000000 --- a/src/southbridge/via/common/early_smbus_read_byte.c +++ /dev/null @@ -1,51 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2013 Alexandru Gagniuc - * - * This program is free software: you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include - -#include "via_early_smbus.h" - -/** - * \brief Read a byte from the SMBus. - * - * @param smbus_dev The base SMBus IO port - * @param addr The address location of the DIMM on the SMBus. - * @param offset The offset the data is located at. - */ -u8 smbus_read_byte(u32 smbus_dev, u8 addr, u8 offset) -{ - u8 val; - - /* Initialize SMBus sequence */ - smbus_reset(smbus_dev); - /* Clear host data port. */ - outb(0x00, SMBHSTDAT0(smbus_dev)); - - smbus_wait_until_ready(smbus_dev); - - /* Actual addr to reg format. */ - addr = (addr << 1); - addr |= 1; /* read command */ - outb(addr, SMBXMITADD(smbus_dev)); - outb(offset, SMBHSTCMD(smbus_dev)); - /* Start transaction, byte data read. */ - outb(0x48, SMBHSTCTL(smbus_dev)); - smbus_wait_until_ready(smbus_dev); - - val = inb(SMBHSTDAT0(smbus_dev)); - return val; -} diff --git a/src/southbridge/via/common/early_smbus_reset.c b/src/southbridge/via/common/early_smbus_reset.c deleted file mode 100644 index 44975408cb..0000000000 --- a/src/southbridge/via/common/early_smbus_reset.c +++ /dev/null @@ -1,30 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2013 Alexandru Gagniuc - * - * This program is free software: you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include - -#include "via_early_smbus.h" - -/** - * \brief Clear the SMBus host status register - * - * @param smbus_dev The base SMBus IO port - */ -void smbus_reset(u32 smbus_dev) -{ - outb(0xdf, SMBHSTSTAT(smbus_dev)); -} diff --git a/src/southbridge/via/common/early_smbus_wait_until_ready.c b/src/southbridge/via/common/early_smbus_wait_until_ready.c deleted file mode 100644 index 6b189362ec..0000000000 --- a/src/southbridge/via/common/early_smbus_wait_until_ready.c +++ /dev/null @@ -1,42 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2013 Alexandru Gagniuc - * - * This program is free software: you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include - -#include "via_early_smbus.h" - -/** - * \brief Wait for the SMBus to become ready to process a new transaction. - * - * @param smbus_dev The base SMBus IO port - */ -int smbus_wait_until_ready(u32 smbus_dev) -{ - int loops; - - printsmbus("Waiting until SMBus ready\n"); - - /* Loop up to SMBUS_TIMEOUT times, waiting for bit 0 of the - * SMBus Host Status register to go to 0, indicating the operation - * was completed successfully. I don't remember why I did it this way, - * but I think it was because ROMCC was running low on registers */ - loops = 0; - while (smbus_is_busy(smbus_dev) && loops < SMBUS_TIMEOUT) - ++loops; - - return smbus_print_error(smbus_dev, inb(SMBHSTSTAT(smbus_dev)), loops); -} diff --git a/src/southbridge/via/common/via_early_smbus.h b/src/southbridge/via/common/via_early_smbus.h deleted file mode 100644 index 1dce9b6049..0000000000 --- a/src/southbridge/via/common/via_early_smbus.h +++ /dev/null @@ -1,51 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2013 Alexandru Gagniuc - * - * This program is free software: you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -/** - * @file via_early_smbus.h - * - * This file contains generic definitions used in VIA SMBus controllers. - * - * Functions defined in device/early/smbus.h are each implemented in a separate - * early_smbus_[func_name].c file. This makes it possible to override any of - * these functions by not including them in your build, via Makefile.c. This is - * useful when there is a need to work around chipset bugs. - * - * These implementations work with most via chipsets. Any VIA port should try - * to use these. Makefile.inc needs to be adapted to link against the files - * providing SMBus functionality: - * @code - * romstage-y += ./../../../southbridge/via/common/early_smbus_func.c - * @endcode - */ - -/** - * \brief SMBus IO ports in relation to the base IO port - */ - -#define SMBHSTSTAT(base) ((u16)base + 0x0) -#define SMBSLVSTAT(base) ((u16)base + 0x1) -#define SMBHSTCTL(base) ((u16)base + 0x2) -#define SMBHSTCMD(base) ((u16)base + 0x3) -#define SMBXMITADD(base) ((u16)base + 0x4) -#define SMBHSTDAT0(base) ((u16)base + 0x5) -#define SMBHSTDAT1(base) ((u16)base + 0x6) -#define SMBBLKDAT(base) ((u16)base + 0x7) -#define SMBSLVCTL(base) ((u16)base + 0x8) -#define SMBTRNSADD(base) ((u16)base + 0x9) -#define SMBSLVDATA (base) ((u16)base + 0xa) - -#define SMBUS_TIMEOUT (100*1000*10) From ad983eeec76ecdb2aff4fb47baeee95ade012225 Mon Sep 17 00:00:00 2001 From: Arthur Heymans Date: Wed, 20 Nov 2019 05:22:15 +0100 Subject: [PATCH 0288/1242] MAINTAINERS: Remove unsupported VIA platform MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Change-Id: I2965de2318cdc160ef5ab56f7f52a76775c1e200 Signed-off-by: Arthur Heymans Reviewed-on: https://review.coreboot.org/c/coreboot/+/36989 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki Reviewed-by: Angel Pons --- MAINTAINERS | 5 ----- 1 file changed, 5 deletions(-) diff --git a/MAINTAINERS b/MAINTAINERS index 8e03c13102..a792673347 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -502,11 +502,6 @@ F: src/northbridge/amd/ F: src/southbridge/amd/ F: src/include/cpu/amd/ -VIA SUPPORT -F: src/cpu/via/ -F: src/northbridge/via/ -F: src/southbridge/via/ - LINT SCRIPTS M: Patrick Georgi M: Martin Roth From f2e42c4a8ec75c162251c72df8ac3da12e8a3eb9 Mon Sep 17 00:00:00 2001 From: Arthur Heymans Date: Tue, 19 Nov 2019 15:55:05 +0100 Subject: [PATCH 0289/1242] mb/*/*: Drop AMDFAM10 mainboards MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Relocatable ramstage, postcar stage and C_ENVIRONMENT_BOOTBLOCK are now mandatory features, which this platform lacks. Change-Id: Ic00ca18de3d73a17041a3a2839307149ad7902b2 Signed-off-by: Arthur Heymans Reviewed-on: https://review.coreboot.org/c/coreboot/+/36961 Reviewed-by: Kyösti Mälkki Reviewed-by: Angel Pons Reviewed-by: HAOUAS Elyes Tested-by: build bot (Jenkins) --- src/mainboard/advansus/Kconfig | 30 - src/mainboard/advansus/Kconfig.name | 2 - src/mainboard/advansus/a785e-i/Kconfig | 65 - src/mainboard/advansus/a785e-i/Kconfig.name | 2 - src/mainboard/advansus/a785e-i/Makefile.inc | 16 - .../advansus/a785e-i/acpi/cpstate.asl | 80 - .../advansus/a785e-i/acpi/routing.asl | 395 ---- src/mainboard/advansus/a785e-i/acpi/sata.asl | 145 -- src/mainboard/advansus/a785e-i/acpi/usb.asl | 158 -- src/mainboard/advansus/a785e-i/acpi_tables.c | 44 - src/mainboard/advansus/a785e-i/board_info.txt | 5 - src/mainboard/advansus/a785e-i/cmos.layout | 52 - src/mainboard/advansus/a785e-i/devicetree.cb | 124 -- src/mainboard/advansus/a785e-i/dsdt.asl | 1613 --------------- src/mainboard/advansus/a785e-i/get_bus_conf.c | 44 - src/mainboard/advansus/a785e-i/irq_tables.c | 101 - src/mainboard/advansus/a785e-i/mainboard.c | 64 - src/mainboard/advansus/a785e-i/mptable.c | 79 - src/mainboard/advansus/a785e-i/platform_cfg.h | 215 -- src/mainboard/advansus/a785e-i/resourcemap.c | 273 --- src/mainboard/advansus/a785e-i/romstage.c | 223 --- src/mainboard/amd/bimini_fam10/Kconfig | 60 - src/mainboard/amd/bimini_fam10/Kconfig.name | 2 - src/mainboard/amd/bimini_fam10/Makefile.inc | 16 - .../amd/bimini_fam10/acpi/cpstate.asl | 80 - src/mainboard/amd/bimini_fam10/acpi/ide.asl | 240 --- .../amd/bimini_fam10/acpi/routing.asl | 395 ---- src/mainboard/amd/bimini_fam10/acpi/sata.asl | 145 -- src/mainboard/amd/bimini_fam10/acpi/usb.asl | 158 -- src/mainboard/amd/bimini_fam10/acpi_tables.c | 44 - src/mainboard/amd/bimini_fam10/board_info.txt | 1 - src/mainboard/amd/bimini_fam10/cmos.layout | 52 - src/mainboard/amd/bimini_fam10/devicetree.cb | 95 - src/mainboard/amd/bimini_fam10/dsdt.asl | 1619 --------------- src/mainboard/amd/bimini_fam10/get_bus_conf.c | 43 - src/mainboard/amd/bimini_fam10/irq_tables.c | 101 - src/mainboard/amd/bimini_fam10/mainboard.c | 79 - src/mainboard/amd/bimini_fam10/mptable.c | 84 - src/mainboard/amd/bimini_fam10/resourcemap.c | 274 --- src/mainboard/amd/bimini_fam10/romstage.c | 219 -- src/mainboard/amd/mahogany_fam10/Kconfig | 58 - src/mainboard/amd/mahogany_fam10/Kconfig.name | 2 - src/mainboard/amd/mahogany_fam10/Makefile.inc | 16 - .../amd/mahogany_fam10/acpi/cpstate.asl | 80 - src/mainboard/amd/mahogany_fam10/acpi/ide.asl | 240 --- .../amd/mahogany_fam10/acpi/routing.asl | 334 ---- .../amd/mahogany_fam10/acpi/sata.asl | 145 -- src/mainboard/amd/mahogany_fam10/acpi/usb.asl | 158 -- .../amd/mahogany_fam10/acpi_tables.c | 44 - .../amd/mahogany_fam10/board_info.txt | 1 - src/mainboard/amd/mahogany_fam10/cmos.layout | 52 - .../amd/mahogany_fam10/devicetree.cb | 129 -- src/mainboard/amd/mahogany_fam10/dsdt.asl | 1736 ---------------- .../amd/mahogany_fam10/get_bus_conf.c | 44 - src/mainboard/amd/mahogany_fam10/irq_tables.c | 102 - src/mainboard/amd/mahogany_fam10/mainboard.c | 103 - src/mainboard/amd/mahogany_fam10/mptable.c | 102 - .../amd/mahogany_fam10/resourcemap.c | 279 --- src/mainboard/amd/mahogany_fam10/romstage.c | 223 --- .../amd/serengeti_cheetah_fam10/Kconfig | 56 - .../amd/serengeti_cheetah_fam10/Kconfig.name | 2 - .../amd/serengeti_cheetah_fam10/Makefile.inc | 8 - .../serengeti_cheetah_fam10/acpi/amd8111.asl | 175 -- .../acpi/amd8111_isa.asl | 190 -- .../acpi/amd8111_pic.asl | 366 ---- .../acpi/amd8131_2.asl | 122 -- .../serengeti_cheetah_fam10/acpi/amd8132.asl | 130 -- .../acpi/amd8132_2.asl | 187 -- .../serengeti_cheetah_fam10/acpi/amd8151.asl | 43 - .../acpi/htx_no_ioapic.asl | 30 - .../serengeti_cheetah_fam10/acpi/pci0_hc.asl | 16 - .../serengeti_cheetah_fam10/acpi/pci2_hc.asl | 16 - .../serengeti_cheetah_fam10/acpi/pci3_hc.asl | 16 - .../serengeti_cheetah_fam10/acpi/pci4_hc.asl | 16 - .../serengeti_cheetah_fam10/acpi/pci5_hc.asl | 16 - .../serengeti_cheetah_fam10/acpi/superio.asl | 16 - .../amd/serengeti_cheetah_fam10/acpi_tables.c | 179 -- .../serengeti_cheetah_fam10/board_info.txt | 1 - .../amd/serengeti_cheetah_fam10/cmos.layout | 102 - .../amd/serengeti_cheetah_fam10/devicetree.cb | 137 -- .../amd/serengeti_cheetah_fam10/dsdt.asl | 244 --- .../amd/serengeti_cheetah_fam10/fadt.c | 159 -- .../serengeti_cheetah_fam10/get_bus_conf.c | 167 -- .../amd/serengeti_cheetah_fam10/irq_tables.c | 141 -- .../amd/serengeti_cheetah_fam10/mainboard.c | 25 - .../amd/serengeti_cheetah_fam10/mainboard.h | 14 - .../amd/serengeti_cheetah_fam10/mb_sysconf.h | 38 - .../amd/serengeti_cheetah_fam10/mptable.c | 192 -- .../amd/serengeti_cheetah_fam10/resourcemap.c | 273 --- .../amd/serengeti_cheetah_fam10/romstage.c | 334 ---- .../amd/serengeti_cheetah_fam10/ssdt2.asl | 79 - .../amd/serengeti_cheetah_fam10/ssdt3.asl | 79 - .../amd/serengeti_cheetah_fam10/ssdt4.asl | 79 - .../amd/serengeti_cheetah_fam10/ssdt5.asl | 80 - src/mainboard/amd/tilapia_fam10/Kconfig | 63 - src/mainboard/amd/tilapia_fam10/Kconfig.name | 2 - src/mainboard/amd/tilapia_fam10/Makefile.inc | 16 - .../amd/tilapia_fam10/acpi/cpstate.asl | 80 - src/mainboard/amd/tilapia_fam10/acpi/ide.asl | 240 --- .../amd/tilapia_fam10/acpi/routing.asl | 297 --- src/mainboard/amd/tilapia_fam10/acpi/sata.asl | 145 -- src/mainboard/amd/tilapia_fam10/acpi/usb.asl | 158 -- src/mainboard/amd/tilapia_fam10/acpi_tables.c | 44 - .../amd/tilapia_fam10/board_info.txt | 1 - src/mainboard/amd/tilapia_fam10/cmos.layout | 52 - src/mainboard/amd/tilapia_fam10/devicetree.cb | 130 -- src/mainboard/amd/tilapia_fam10/dsdt.asl | 1739 ---------------- .../amd/tilapia_fam10/get_bus_conf.c | 53 - src/mainboard/amd/tilapia_fam10/irq_tables.c | 102 - src/mainboard/amd/tilapia_fam10/mainboard.c | 232 --- src/mainboard/amd/tilapia_fam10/mptable.c | 102 - src/mainboard/amd/tilapia_fam10/resourcemap.c | 273 --- src/mainboard/amd/tilapia_fam10/romstage.c | 224 --- src/mainboard/asus/kcma-d8/Kconfig | 96 - src/mainboard/asus/kcma-d8/Kconfig.name | 2 - src/mainboard/asus/kcma-d8/Makefile.inc | 16 - src/mainboard/asus/kcma-d8/acpi/pm_ctrl.asl | 368 ---- src/mainboard/asus/kcma-d8/acpi_tables.c | 103 - src/mainboard/asus/kcma-d8/board_info.txt | 5 - src/mainboard/asus/kcma-d8/bootblock.c | 52 - src/mainboard/asus/kcma-d8/cmos.default | 29 - src/mainboard/asus/kcma-d8/cmos.layout | 149 -- src/mainboard/asus/kcma-d8/devicetree.cb | 239 --- src/mainboard/asus/kcma-d8/dsdt.asl | 769 ------- src/mainboard/asus/kcma-d8/get_bus_conf.c | 29 - src/mainboard/asus/kcma-d8/irq_tables.c | 123 -- src/mainboard/asus/kcma-d8/mainboard.c | 113 -- src/mainboard/asus/kcma-d8/mptable.c | 219 -- src/mainboard/asus/kcma-d8/resourcemap.c | 553 ------ src/mainboard/asus/kcma-d8/romstage.c | 606 ------ src/mainboard/asus/kcma-d8/spd_notes.txt | 46 - src/mainboard/asus/kfsn4-dre/Kconfig | 88 - src/mainboard/asus/kfsn4-dre/Kconfig.name | 2 - src/mainboard/asus/kfsn4-dre/Makefile.inc | 16 - src/mainboard/asus/kfsn4-dre/acpi/pm_ctrl.asl | 241 --- src/mainboard/asus/kfsn4-dre/acpi_tables.c | 74 - src/mainboard/asus/kfsn4-dre/board_info.txt | 6 - src/mainboard/asus/kfsn4-dre/bootblock.c | 83 - src/mainboard/asus/kfsn4-dre/cmos.default | 13 - src/mainboard/asus/kfsn4-dre/cmos.layout | 119 -- src/mainboard/asus/kfsn4-dre/devicetree.cb | 194 -- src/mainboard/asus/kfsn4-dre/dsdt.asl | 948 --------- src/mainboard/asus/kfsn4-dre/get_bus_conf.c | 85 - src/mainboard/asus/kfsn4-dre/irq_tables.c | 175 -- src/mainboard/asus/kfsn4-dre/mptable.c | 151 -- src/mainboard/asus/kfsn4-dre/resourcemap.c | 283 --- src/mainboard/asus/kfsn4-dre/romstage.c | 372 ---- src/mainboard/asus/kfsn4-dre/spd_notes.txt | 69 - src/mainboard/asus/kgpe-d16/Kconfig | 102 - src/mainboard/asus/kgpe-d16/Kconfig.name | 2 - src/mainboard/asus/kgpe-d16/Makefile.inc | 16 - src/mainboard/asus/kgpe-d16/acpi/pm_ctrl.asl | 368 ---- src/mainboard/asus/kgpe-d16/acpi_tables.c | 103 - src/mainboard/asus/kgpe-d16/board_info.txt | 5 - src/mainboard/asus/kgpe-d16/bootblock.c | 52 - src/mainboard/asus/kgpe-d16/cmos.default | 30 - src/mainboard/asus/kgpe-d16/cmos.layout | 150 -- src/mainboard/asus/kgpe-d16/devicetree.cb | 259 --- src/mainboard/asus/kgpe-d16/dsdt.asl | 809 -------- src/mainboard/asus/kgpe-d16/get_bus_conf.c | 30 - src/mainboard/asus/kgpe-d16/irq_tables.c | 122 -- src/mainboard/asus/kgpe-d16/mainboard.c | 114 -- src/mainboard/asus/kgpe-d16/mptable.c | 219 -- src/mainboard/asus/kgpe-d16/resourcemap.c | 553 ------ src/mainboard/asus/kgpe-d16/romstage.c | 720 ------- src/mainboard/asus/kgpe-d16/spd_notes.txt | 46 - src/mainboard/asus/m4a78-em/Kconfig | 53 - src/mainboard/asus/m4a78-em/Kconfig.name | 2 - src/mainboard/asus/m4a78-em/Makefile.inc | 16 - src/mainboard/asus/m4a78-em/acpi/cpstate.asl | 80 - src/mainboard/asus/m4a78-em/acpi/ide.asl | 240 --- src/mainboard/asus/m4a78-em/acpi/routing.asl | 297 --- src/mainboard/asus/m4a78-em/acpi/sata.asl | 145 -- src/mainboard/asus/m4a78-em/acpi/usb.asl | 158 -- src/mainboard/asus/m4a78-em/acpi_tables.c | 44 - src/mainboard/asus/m4a78-em/board_info.txt | 7 - src/mainboard/asus/m4a78-em/cmos.layout | 52 - src/mainboard/asus/m4a78-em/devicetree.cb | 106 - src/mainboard/asus/m4a78-em/dsdt.asl | 1718 ---------------- src/mainboard/asus/m4a78-em/get_bus_conf.c | 44 - src/mainboard/asus/m4a78-em/irq_tables.c | 60 - src/mainboard/asus/m4a78-em/mainboard.c | 116 -- src/mainboard/asus/m4a78-em/mptable.c | 103 - src/mainboard/asus/m4a78-em/resourcemap.c | 279 --- src/mainboard/asus/m4a78-em/romstage.c | 227 --- src/mainboard/asus/m4a785-m/Kconfig | 58 - src/mainboard/asus/m4a785-m/Kconfig.name | 2 - src/mainboard/asus/m4a785-m/Makefile.inc | 16 - src/mainboard/asus/m4a785-m/acpi/cpstate.asl | 80 - src/mainboard/asus/m4a785-m/acpi/ide.asl | 240 --- src/mainboard/asus/m4a785-m/acpi/routing.asl | 297 --- src/mainboard/asus/m4a785-m/acpi/sata.asl | 145 -- src/mainboard/asus/m4a785-m/acpi/usb.asl | 158 -- src/mainboard/asus/m4a785-m/acpi_tables.c | 44 - src/mainboard/asus/m4a785-m/board_info.txt | 7 - src/mainboard/asus/m4a785-m/cmos.layout | 52 - src/mainboard/asus/m4a785-m/devicetree.cb | 106 - src/mainboard/asus/m4a785-m/dsdt.asl | 1718 ---------------- src/mainboard/asus/m4a785-m/get_bus_conf.c | 44 - src/mainboard/asus/m4a785-m/irq_tables.c | 61 - src/mainboard/asus/m4a785-m/mainboard.c | 189 -- src/mainboard/asus/m4a785-m/mptable.c | 101 - src/mainboard/asus/m4a785-m/resourcemap.c | 279 --- src/mainboard/asus/m4a785-m/romstage.c | 236 --- src/mainboard/asus/m4a785t-m/Kconfig | 56 - src/mainboard/asus/m4a785t-m/Kconfig.name | 2 - src/mainboard/asus/m4a785t-m/Makefile.inc | 16 - src/mainboard/asus/m4a785t-m/acpi/cpstate.asl | 100 - src/mainboard/asus/m4a785t-m/acpi/ide.asl | 240 --- src/mainboard/asus/m4a785t-m/acpi/routing.asl | 297 --- src/mainboard/asus/m4a785t-m/acpi/sata.asl | 145 -- src/mainboard/asus/m4a785t-m/acpi/usb.asl | 158 -- src/mainboard/asus/m4a785t-m/acpi_tables.c | 17 - src/mainboard/asus/m4a785t-m/board_info.txt | 7 - src/mainboard/asus/m4a785t-m/cmos.default | 11 - src/mainboard/asus/m4a785t-m/cmos.layout | 52 - src/mainboard/asus/m4a785t-m/devicetree.cb | 108 - src/mainboard/asus/m4a785t-m/dsdt.asl | 1641 --------------- src/mainboard/asus/m4a785t-m/get_bus_conf.c | 17 - src/mainboard/asus/m4a785t-m/irq_tables.c | 17 - src/mainboard/asus/m4a785t-m/mainboard.c | 17 - src/mainboard/asus/m4a785t-m/mptable.c | 17 - src/mainboard/asus/m4a785t-m/romstage.c | 17 - src/mainboard/asus/m5a88-v/Kconfig | 64 - src/mainboard/asus/m5a88-v/Kconfig.name | 2 - src/mainboard/asus/m5a88-v/Makefile.inc | 16 - src/mainboard/asus/m5a88-v/acpi/cpstate.asl | 80 - src/mainboard/asus/m5a88-v/acpi/ide.asl | 240 --- src/mainboard/asus/m5a88-v/acpi/routing.asl | 395 ---- src/mainboard/asus/m5a88-v/acpi/sata.asl | 145 -- src/mainboard/asus/m5a88-v/acpi/usb.asl | 158 -- src/mainboard/asus/m5a88-v/acpi_tables.c | 44 - src/mainboard/asus/m5a88-v/board_info.txt | 7 - src/mainboard/asus/m5a88-v/cmos.layout | 52 - src/mainboard/asus/m5a88-v/devicetree.cb | 124 -- src/mainboard/asus/m5a88-v/dsdt.asl | 1619 --------------- src/mainboard/asus/m5a88-v/get_bus_conf.c | 44 - src/mainboard/asus/m5a88-v/irq_tables.c | 101 - src/mainboard/asus/m5a88-v/mainboard.c | 63 - src/mainboard/asus/m5a88-v/mptable.c | 78 - src/mainboard/asus/m5a88-v/platform_cfg.h | 217 -- src/mainboard/asus/m5a88-v/resourcemap.c | 277 --- src/mainboard/asus/m5a88-v/romstage.c | 223 --- src/mainboard/avalue/Kconfig | 30 - src/mainboard/avalue/Kconfig.name | 2 - src/mainboard/avalue/eax-785e/Kconfig | 65 - src/mainboard/avalue/eax-785e/Kconfig.name | 2 - src/mainboard/avalue/eax-785e/Makefile.inc | 16 - .../avalue/eax-785e/acpi/cpstate.asl | 80 - .../avalue/eax-785e/acpi/routing.asl | 395 ---- src/mainboard/avalue/eax-785e/acpi/sata.asl | 145 -- src/mainboard/avalue/eax-785e/acpi/usb.asl | 158 -- src/mainboard/avalue/eax-785e/acpi_tables.c | 44 - src/mainboard/avalue/eax-785e/board_info.txt | 5 - src/mainboard/avalue/eax-785e/cmos.layout | 52 - src/mainboard/avalue/eax-785e/devicetree.cb | 111 -- src/mainboard/avalue/eax-785e/dsdt.asl | 1613 --------------- src/mainboard/avalue/eax-785e/get_bus_conf.c | 44 - src/mainboard/avalue/eax-785e/irq_tables.c | 101 - src/mainboard/avalue/eax-785e/mainboard.c | 62 - src/mainboard/avalue/eax-785e/mptable.c | 81 - src/mainboard/avalue/eax-785e/platform_cfg.h | 215 -- src/mainboard/avalue/eax-785e/resourcemap.c | 273 --- src/mainboard/avalue/eax-785e/romstage.c | 223 --- src/mainboard/gigabyte/ma785gm/Kconfig | 54 - src/mainboard/gigabyte/ma785gm/Kconfig.name | 2 - src/mainboard/gigabyte/ma785gm/Makefile.inc | 16 - .../gigabyte/ma785gm/acpi/cpstate.asl | 80 - src/mainboard/gigabyte/ma785gm/acpi/ide.asl | 240 --- .../gigabyte/ma785gm/acpi/routing.asl | 297 --- src/mainboard/gigabyte/ma785gm/acpi/sata.asl | 145 -- src/mainboard/gigabyte/ma785gm/acpi/usb.asl | 158 -- src/mainboard/gigabyte/ma785gm/acpi_tables.c | 44 - src/mainboard/gigabyte/ma785gm/board_info.txt | 3 - src/mainboard/gigabyte/ma785gm/cmos.layout | 52 - src/mainboard/gigabyte/ma785gm/devicetree.cb | 115 -- src/mainboard/gigabyte/ma785gm/dsdt.asl | 1718 ---------------- src/mainboard/gigabyte/ma785gm/get_bus_conf.c | 44 - src/mainboard/gigabyte/ma785gm/irq_tables.c | 102 - src/mainboard/gigabyte/ma785gm/mainboard.c | 139 -- src/mainboard/gigabyte/ma785gm/mptable.c | 101 - src/mainboard/gigabyte/ma785gm/resourcemap.c | 279 --- src/mainboard/gigabyte/ma785gm/romstage.c | 226 --- src/mainboard/gigabyte/ma785gmt/Kconfig | 54 - src/mainboard/gigabyte/ma785gmt/Kconfig.name | 2 - src/mainboard/gigabyte/ma785gmt/Makefile.inc | 16 - .../gigabyte/ma785gmt/acpi/cpstate.asl | 80 - src/mainboard/gigabyte/ma785gmt/acpi/ide.asl | 240 --- .../gigabyte/ma785gmt/acpi/routing.asl | 297 --- src/mainboard/gigabyte/ma785gmt/acpi/sata.asl | 145 -- src/mainboard/gigabyte/ma785gmt/acpi/usb.asl | 158 -- src/mainboard/gigabyte/ma785gmt/acpi_tables.c | 44 - .../gigabyte/ma785gmt/board_info.txt | 3 - src/mainboard/gigabyte/ma785gmt/cmos.layout | 52 - src/mainboard/gigabyte/ma785gmt/devicetree.cb | 115 -- src/mainboard/gigabyte/ma785gmt/dsdt.asl | 1718 ---------------- .../gigabyte/ma785gmt/get_bus_conf.c | 42 - src/mainboard/gigabyte/ma785gmt/irq_tables.c | 102 - src/mainboard/gigabyte/ma785gmt/mainboard.c | 244 --- src/mainboard/gigabyte/ma785gmt/mptable.c | 103 - src/mainboard/gigabyte/ma785gmt/resourcemap.c | 279 --- src/mainboard/gigabyte/ma785gmt/romstage.c | 226 --- src/mainboard/gigabyte/ma78gm/Kconfig | 54 - src/mainboard/gigabyte/ma78gm/Kconfig.name | 2 - src/mainboard/gigabyte/ma78gm/Makefile.inc | 16 - .../gigabyte/ma78gm/acpi/cpstate.asl | 80 - src/mainboard/gigabyte/ma78gm/acpi/ide.asl | 240 --- .../gigabyte/ma78gm/acpi/routing.asl | 308 --- src/mainboard/gigabyte/ma78gm/acpi/sata.asl | 145 -- src/mainboard/gigabyte/ma78gm/acpi/usb.asl | 158 -- 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src/mainboard/tyan/s2912_fam10/romstage.c diff --git a/src/mainboard/advansus/Kconfig b/src/mainboard/advansus/Kconfig deleted file mode 100644 index 5f227afa3d..0000000000 --- a/src/mainboard/advansus/Kconfig +++ /dev/null @@ -1,30 +0,0 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2011 Advanced Micro Devices, Inc. -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; version 2 of the License. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## -if VENDOR_ADVANSUS - -choice - prompt "Mainboard model" - -source "src/mainboard/advansus/*/Kconfig.name" - -endchoice - -source "src/mainboard/advansus/*/Kconfig" - -config MAINBOARD_VENDOR - string - default "Advansus" - -endif # VENDOR_ADVANSUS diff --git a/src/mainboard/advansus/Kconfig.name b/src/mainboard/advansus/Kconfig.name deleted file mode 100644 index f610ef93bf..0000000000 --- a/src/mainboard/advansus/Kconfig.name +++ /dev/null @@ -1,2 +0,0 @@ -config VENDOR_ADVANSUS - bool "Advansus" diff --git a/src/mainboard/advansus/a785e-i/Kconfig b/src/mainboard/advansus/a785e-i/Kconfig deleted file mode 100644 index 06c126e465..0000000000 --- a/src/mainboard/advansus/a785e-i/Kconfig +++ /dev/null @@ -1,65 +0,0 @@ -if BOARD_ADVANSUS_A785E_I - -config BOARD_SPECIFIC_OPTIONS - def_bool y - select CPU_AMD_SOCKET_ASB2 - select DIMM_DDR3 - select DIMM_REGISTERED - select NORTHBRIDGE_AMD_AMDFAM10 - select SOUTHBRIDGE_AMD_RS780 - select SOUTHBRIDGE_AMD_SB800 - select SUPERIO_WINBOND_W83627HF #COM1, COM2 - #select SUPERIO_FINTEK_F81216AD #COM3, COM4 - select HAVE_OPTION_TABLE - select HAVE_PIRQ_TABLE - select SB_HT_CHAIN_UNITID_OFFSET_ONLY - select LIFT_BSP_APIC_ID - select HAVE_MP_TABLE - select HAVE_ACPI_TABLES - select BOARD_ROMSIZE_KB_1024 - select ENABLE_APIC_EXT_ID - select GFXUMA - select HAVE_DEBUG_CAR - select SET_FIDVID - -config MAINBOARD_DIR - string - default advansus/a785e-i - -config APIC_ID_OFFSET - hex - default 0x0 - -config MAINBOARD_PART_NUMBER - string - default "A785E-I" - -config HW_MEM_HOLE_SIZEK - hex - default 0x100000 - -config MAX_CPUS - int - default 8 - -config MAX_PHYSICAL_CPUS - int - default 1 - -config HT_CHAIN_END_UNITID_BASE - hex - default 0x1 - -config HT_CHAIN_UNITID_BASE - hex - default 0x0 - -config IRQ_SLOT_COUNT - int - default 11 - -config VGA_BIOS_ID - string - default "1002,9712" - -endif #BOARD_ADVANSUS_A785E_I diff --git a/src/mainboard/advansus/a785e-i/Kconfig.name b/src/mainboard/advansus/a785e-i/Kconfig.name deleted file mode 100644 index 8e15765424..0000000000 --- a/src/mainboard/advansus/a785e-i/Kconfig.name +++ /dev/null @@ -1,2 +0,0 @@ -config BOARD_ADVANSUS_A785E_I - bool "A785E-I" diff --git a/src/mainboard/advansus/a785e-i/Makefile.inc b/src/mainboard/advansus/a785e-i/Makefile.inc deleted file mode 100644 index 91d4b39c32..0000000000 --- a/src/mainboard/advansus/a785e-i/Makefile.inc +++ /dev/null @@ -1,16 +0,0 @@ -# -# This file is part of the coreboot project. -# -# This program is free software; you can redistribute it and/or modify -# it under the terms of the GNU General Public License as published by -# the Free Software Foundation; version 2 of the License. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# - -romstage-y += resourcemap.c - -ramstage-y += get_bus_conf.c diff --git a/src/mainboard/advansus/a785e-i/acpi/cpstate.asl b/src/mainboard/advansus/a785e-i/acpi/cpstate.asl deleted file mode 100644 index eb4eac1027..0000000000 --- a/src/mainboard/advansus/a785e-i/acpi/cpstate.asl +++ /dev/null @@ -1,80 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -/* This file defines the processor and performance state capability - * for each core in the system. It is included into the DSDT for each - * core. It assumes that each core of the system has the same performance - * characteristics. -*/ -/* -#include -DefinitionBlock ("DSDT.AML", "DSDT", 0x01, OEM_ID, ACPI_TABLE_CREATOR, 0x00010001) - { - Scope (\_PR) { - Device (CPU0) { - Name (_HID, "ACPI0007") - Name (_UID, 0) - #include "cpstate.asl" - } - Device (CPU1) { - Name (_HID, "ACPI0007") - Name (_UID, 1) - #include "cpstate.asl" - } - Device (CPU2) { - Name (_HID, "ACPI0007") - Name (_UID, 2) - #include "cpstate.asl" - } - Device (CPU3) { - Name (_HID, "ACPI0007") - Name (_UID, 3) - #include "cpstate.asl" - } - } -*/ - /* P-state support: The maximum number of P-states supported by the */ - /* CPUs we'll use is 6. */ - /* Get from AMI BIOS. */ - Name(_PSS, Package(){ - Package () - { - 0x00000AF0, - 0x0000BF81, - 0x00000002, - 0x00000002, - 0x00000000, - 0x00000000 - }, - - Package () - { - 0x00000578, - 0x000076F2, - 0x00000002, - 0x00000002, - 0x00000001, - 0x00000001 - } - }) - - Name(_PCT, Package(){ - ResourceTemplate(){Register(FFixedHW, 0, 0, 0)}, - ResourceTemplate(){Register(FFixedHW, 0, 0, 0)} - }) - - Method(_PPC, 0){ - Return(0) - } diff --git a/src/mainboard/advansus/a785e-i/acpi/routing.asl b/src/mainboard/advansus/a785e-i/acpi/routing.asl deleted file mode 100644 index 46920552e7..0000000000 --- a/src/mainboard/advansus/a785e-i/acpi/routing.asl +++ /dev/null @@ -1,395 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -/* -#include -DefinitionBlock ("DSDT.AML", "DSDT", 0x01, OEM_ID, ACPI_TABLE_CREATOR, 0x00010001 - ) - { - #include "routing.asl" - } -*/ - -/* Routing is in System Bus scope */ -Scope(\_SB) { - Name(PR0, Package(){ - /* NB devices */ - /* Bus 0, Dev 0 - RS780 Host Controller */ - /* Bus 0, Dev 1 - PCI Bridge for Internal Graphics */ - /* Bus 0, Dev 2 - PCIe Bridge for x8 PCIe Slot (GFX0) */ - Package(){0x0002FFFF, 0, INTC, 0 }, - Package(){0x0002FFFF, 1, INTD, 0 }, - Package(){0x0002FFFF, 2, INTA, 0 }, - Package(){0x0002FFFF, 3, INTB, 0 }, - /* Bus 0, Dev 3 - PCIe graphics port 1 bridge */ - /* Bus 0, Dev 4 - PCIe Bridge for Express Card Slot */ - Package(){0x0004FFFF, 0, INTA, 0 }, - Package(){0x0004FFFF, 1, INTB, 0 }, - Package(){0x0004FFFF, 2, INTC, 0 }, - Package(){0x0004FFFF, 3, INTD, 0 }, - /* Bus 0, Dev 5 - General purpose PCIe bridge 5 */ - /* Package(){0x0005FFFF, 0, INTB, 0 }, */ - /* Package(){0x0005FFFF, 1, INTC, 0 }, */ - /* Package(){0x0005FFFF, 2, INTD, 0 }, */ - /* Package(){0x0005FFFF, 3, INTA, 0 }, */ - /* Bus 0, Dev 6 - PCIe Bridge for Ethernet Chip */ - Package(){0x0006FFFF, 0, INTC, 0 }, - Package(){0x0006FFFF, 1, INTD, 0 }, - Package(){0x0006FFFF, 2, INTA, 0 }, - Package(){0x0006FFFF, 3, INTB, 0 }, - /* Bus 0, Dev 7 - PCIe Bridge for x1 PCIe Slot */ - Package(){0x0007FFFF, 0, INTD, 0 }, - Package(){0x0007FFFF, 1, INTA, 0 }, - Package(){0x0007FFFF, 2, INTB, 0 }, - Package(){0x0007FFFF, 3, INTC, 0 }, - - Package(){0x0009FFFF, 0, INTB, 0 }, - Package(){0x0009FFFF, 1, INTC, 0 }, - Package(){0x0009FFFF, 2, INTD, 0 }, - Package(){0x0009FFFF, 3, INTA, 0 }, - - Package(){0x000AFFFF, 0, INTC, 0 }, - Package(){0x000AFFFF, 1, INTD, 0 }, - Package(){0x000AFFFF, 2, INTA, 0 }, - Package(){0x000AFFFF, 3, INTB, 0 }, - - Package(){0x000BFFFF, 0, INTD, 0 }, - Package(){0x000BFFFF, 1, INTA, 0 }, - Package(){0x000BFFFF, 2, INTB, 0 }, - Package(){0x000BFFFF, 3, INTC, 0 }, - - Package(){0x000CFFFF, 0, INTA, 0 }, - Package(){0x000CFFFF, 1, INTB, 0 }, - Package(){0x000CFFFF, 2, INTC, 0 }, - Package(){0x000CFFFF, 3, INTD, 0 }, - - /* Bus 0, Funct 8 - Southbridge port (normally hidden) */ - - /* SB devices */ - /* Bus 0, Dev 17 - SATA controller #2 */ - /* Bus 0, Dev 18 - SATA controller #1 */ - Package(){0x0011FFFF, 0, INTD, 0 }, - - /* Bus 0, Dev 19 - USB: OHCI, dev 18,19 func 0-2, dev 20 func 5; - * EHCI, dev 18, 19 func 2 */ - Package(){0x0012FFFF, 0, INTC, 0 }, - Package(){0x0012FFFF, 1, INTB, 0 }, - - Package(){0x0013FFFF, 0, INTC, 0 }, - Package(){0x0013FFFF, 1, INTB, 0 }, - - Package(){0x0016FFFF, 0, INTC, 0 }, - Package(){0x0016FFFF, 1, INTB, 0 }, - - /* Package(){0x0014FFFF, 1, INTA, 0 }, */ - - /* Bus 0, Dev 20 - F0:SMBus/ACPI,F1:IDE;F2:HDAudio;F3:LPC;F4:PCIBridge;F5:USB */ - Package(){0x0014FFFF, 0, INTA, 0 }, - Package(){0x0014FFFF, 1, INTB, 0 }, - Package(){0x0014FFFF, 2, INTC, 0 }, - Package(){0x0014FFFF, 3, INTD, 0 }, - - Package(){0x0015FFFF, 0, INTA, 0 }, - Package(){0x0015FFFF, 1, INTB, 0 }, - Package(){0x0015FFFF, 2, INTC, 0 }, - Package(){0x0015FFFF, 3, INTD, 0 }, - }) - - Name(APR0, Package(){ - /* NB devices in APIC mode */ - /* Bus 0, Dev 0 - RS780 Host Controller */ - - /* Bus 0, Dev 1 - PCI Bridge for Internal Graphics */ - Package(){0x0001FFFF, 0, 0, 18 }, - Package(){0x0001FFFF, 1, 0, 19 }, - - /* Bus 0, Dev 2 - PCIe Bridge for x8 PCIe Slot (GFX0) */ - Package(){0x0002FFFF, 0, 0, 18 }, - /* Package(){0x0002FFFF, 1, 0, 19 }, */ - /* Package(){0x0002FFFF, 2, 0, 16 }, */ - /* Package(){0x0002FFFF, 3, 0, 17 }, */ - - /* Bus 0, Dev 3 - PCIe graphics port 1 bridge */ - Package(){0x0003FFFF, 0, 0, 19 }, - - /* Bus 0, Dev 4 - PCIe Bridge for Express Card Slot */ - Package(){0x0004FFFF, 0, 0, 16 }, - /* Package(){0x0004FFFF, 1, 0, 17 }, */ - /* Package(){0x0004FFFF, 2, 0, 18 }, */ - /* Package(){0x0004FFFF, 3, 0, 19 }, */ - - /* Bus 0, Dev 5 - General purpose PCIe bridge 5 */ - /* Package(){0x0005FFFF, 0, 0, 17 }, */ - /* Package(){0x0005FFFF, 1, 0, 18 }, */ - /* Package(){0x0005FFFF, 2, 0, 19 }, */ - /* Package(){0x0005FFFF, 3, 0, 16 }, */ - - /* Bus 0, Dev 6 - General purpose PCIe bridge 6 */ - /* Package(){0x0006FFFF, 0, 0, 18 }, */ - /* Package(){0x0006FFFF, 1, 0, 19 }, */ - /* Package(){0x0006FFFF, 2, 0, 16 }, */ - /* Package(){0x0006FFFF, 3, 0, 17 }, */ - - /* Bus 0, Dev 7 - PCIe Bridge for network card */ - /* Package(){0x0007FFFF, 0, 0, 19 }, */ - /* Package(){0x0007FFFF, 1, 0, 16 }, */ - /* Package(){0x0007FFFF, 2, 0, 17 }, */ - /* Package(){0x0007FFFF, 3, 0, 18 }, */ - - /* Bus 0, Dev 9 - PCIe Bridge for network card */ - Package(){0x0009FFFF, 0, 0, 17 }, - /* Package(){0x0009FFFF, 1, 0, 16 }, */ - /* Package(){0x0009FFFF, 2, 0, 17 }, */ - /* Package(){0x0009FFFF, 3, 0, 18 }, */ - /* Bus 0, Dev A - PCIe Bridge for network card */ - Package(){0x000AFFFF, 0, 0, 18 }, - /* Package(){0x000AFFFF, 1, 0, 16 }, */ - /* Package(){0x000AFFFF, 2, 0, 17 }, */ - /* Package(){0x000AFFFF, 3, 0, 18 }, */ - /* Bus 0, Funct 8 - Southbridge port (normally hidden) */ - - /* SB devices in APIC mode */ - /* Bus 0, Dev 17 - SATA controller #2 */ - /* Bus 0, Dev 18 - SATA controller #1 */ - Package(){0x0011FFFF, 0, 0, 19 }, - - /* Bus 0, Dev 19 - USB: OHCI, dev 18,19 func 0-2, dev 20 func 5; - * EHCI, dev 18, 19 func 2 */ - Package(){0x0012FFFF, 0, 0, 18 }, - Package(){0x0012FFFF, 1, 0, 17 }, - /* Package(){0x0012FFFF, 2, 0, 18 }, */ - - Package(){0x0013FFFF, 0, 0, 18 }, - Package(){0x0013FFFF, 1, 0, 17 }, - /* Package(){0x0013FFFF, 2, 0, 16 }, */ - - /* Package(){0x00140000, 0, 0, 16 }, */ - - Package(){0x0016FFFF, 0, 0, 18 }, - Package(){0x0016FFFF, 1, 0, 17 }, - - /* Bus 0, Dev 20 - F0:SMBus/ACPI, F1:IDE; F2:HDAudio; F3:LPC; F4:PCIBridge; F5:USB */ - Package(){0x0014FFFF, 0, 0, 16 }, - Package(){0x0014FFFF, 1, 0, 17 }, - Package(){0x0014FFFF, 2, 0, 18 }, - Package(){0x0014FFFF, 3, 0, 19 }, - /* Package(){0x00140004, 2, 0, 18 }, */ - /* Package(){0x00140004, 3, 0, 19 }, */ - /* Package(){0x00140005, 1, 0, 17 }, */ - /* Package(){0x00140006, 1, 0, 17 }, */ - - /* TODO: pcie */ - Package(){0x0015FFFF, 0, 0, 16 }, - Package(){0x0015FFFF, 1, 0, 17 }, - Package(){0x0015FFFF, 2, 0, 18 }, - Package(){0x0015FFFF, 3, 0, 19 }, - }) - - Name(PR1, Package(){ - /* Internal graphics - RS780 VGA, Bus1, Dev5 */ - Package(){0x0005FFFF, 0, INTA, 0 }, - Package(){0x0005FFFF, 1, INTB, 0 }, - Package(){0x0005FFFF, 2, INTC, 0 }, - Package(){0x0005FFFF, 3, INTD, 0 }, - }) - Name(APR1, Package(){ - /* Internal graphics - RS780 VGA, Bus1, Dev5 */ - Package(){0x0005FFFF, 0, 0, 18 }, - Package(){0x0005FFFF, 1, 0, 19 }, - /* Package(){0x0005FFFF, 2, 0, 20 }, */ - /* Package(){0x0005FFFF, 3, 0, 17 }, */ - }) - - Name(PS2, Package(){ - /* The external GFX - Hooked to PCIe slot 2 */ - Package(){0x0000FFFF, 0, INTC, 0 }, - Package(){0x0000FFFF, 1, INTD, 0 }, - Package(){0x0000FFFF, 2, INTA, 0 }, - Package(){0x0000FFFF, 3, INTB, 0 }, - }) - Name(APS2, Package(){ - /* The external GFX - Hooked to PCIe slot 2 */ - Package(){0x0000FFFF, 0, 0, 18 }, - Package(){0x0000FFFF, 1, 0, 19 }, - Package(){0x0000FFFF, 2, 0, 16 }, - Package(){0x0000FFFF, 3, 0, 17 }, - }) - - Name(PS4, Package(){ - /* PCIe slot - Hooked to PCIe slot 4 */ - Package(){0x0000FFFF, 0, INTA, 0 }, - Package(){0x0000FFFF, 1, INTB, 0 }, - Package(){0x0000FFFF, 2, INTC, 0 }, - Package(){0x0000FFFF, 3, INTD, 0 }, - }) - Name(APS4, Package(){ - /* PCIe slot - Hooked to PCIe slot 4 */ - Package(){0x0000FFFF, 0, 0, 16 }, - Package(){0x0000FFFF, 1, 0, 17 }, - Package(){0x0000FFFF, 2, 0, 18 }, - Package(){0x0000FFFF, 3, 0, 19 }, - }) - - Name(PS5, Package(){ - /* PCIe slot - Hooked to PCIe slot 5 */ - Package(){0x0000FFFF, 0, INTB, 0 }, - Package(){0x0000FFFF, 1, INTC, 0 }, - Package(){0x0000FFFF, 2, INTD, 0 }, - Package(){0x0000FFFF, 3, INTA, 0 }, - }) - Name(APS5, Package(){ - /* PCIe slot - Hooked to PCIe slot 5 */ - Package(){0x0000FFFF, 0, 0, 17 }, - Package(){0x0000FFFF, 1, 0, 18 }, - Package(){0x0000FFFF, 2, 0, 19 }, - Package(){0x0000FFFF, 3, 0, 16 }, - }) - - Name(PS6, Package(){ - /* PCIe slot - Hooked to PCIe slot 6 */ - Package(){0x0000FFFF, 0, INTC, 0 }, - Package(){0x0000FFFF, 1, INTD, 0 }, - Package(){0x0000FFFF, 2, INTA, 0 }, - Package(){0x0000FFFF, 3, INTB, 0 }, - }) - Name(APS6, Package(){ - /* PCIe slot - Hooked to PCIe slot 6 */ - Package(){0x0000FFFF, 0, 0, 18 }, - Package(){0x0000FFFF, 1, 0, 19 }, - Package(){0x0000FFFF, 2, 0, 16 }, - Package(){0x0000FFFF, 3, 0, 17 }, - }) - - Name(PS7, Package(){ - /* The onboard Ethernet chip - Hooked to PCIe slot 7 */ - Package(){0x0000FFFF, 0, INTD, 0 }, - Package(){0x0000FFFF, 1, INTA, 0 }, - Package(){0x0000FFFF, 2, INTB, 0 }, - Package(){0x0000FFFF, 3, INTC, 0 }, - }) - Name(APS7, Package(){ - /* The onboard Ethernet chip - Hooked to PCIe slot 7 */ - Package(){0x0000FFFF, 0, 0, 19 }, - Package(){0x0000FFFF, 1, 0, 16 }, - Package(){0x0000FFFF, 2, 0, 17 }, - Package(){0x0000FFFF, 3, 0, 18 }, - }) - - Name(PS9, Package(){ - /* PCIe slot - Hooked to PCIe slot 9 */ - Package(){0x0000FFFF, 0, INTD, 0 }, - Package(){0x0000FFFF, 1, INTA, 0 }, - Package(){0x0000FFFF, 2, INTB, 0 }, - Package(){0x0000FFFF, 3, INTC, 0 }, - }) - Name(APS9, Package(){ - /* PCIe slot - Hooked to PCIe slot 9 */ - Package(){0x0000FFFF, 0, 0, 17 }, - Package(){0x0000FFFF, 1, 0, 18 }, - Package(){0x0000FFFF, 2, 0, 19 }, - Package(){0x0000FFFF, 3, 0, 16 }, - }) - - Name(PSa, Package(){ - /* PCIe slot - Hooked to PCIe slot 10 */ - Package(){0x0000FFFF, 0, INTD, 0 }, - Package(){0x0000FFFF, 1, INTA, 0 }, - Package(){0x0000FFFF, 2, INTB, 0 }, - Package(){0x0000FFFF, 3, INTC, 0 }, - }) - Name(APSa, Package(){ - /* PCIe slot - Hooked to PCIe slot 10 */ - Package(){0x0000FFFF, 0, 0, 18 }, - Package(){0x0000FFFF, 1, 0, 19 }, - Package(){0x0000FFFF, 2, 0, 16 }, - Package(){0x0000FFFF, 3, 0, 17 }, - }) - - Name(PE0, Package(){ - /* PCIe slot - Hooked to PCIe slot 10 */ - Package(){0x0000FFFF, 0, INTA, 0 }, - Package(){0x0000FFFF, 1, INTB, 0 }, - Package(){0x0000FFFF, 2, INTC, 0 }, - Package(){0x0000FFFF, 3, INTD, 0 }, - }) - Name(APE0, Package(){ - /* PCIe slot - Hooked to PCIe */ - Package(){0x0000FFFF, 0, 0, 16 }, - Package(){0x0000FFFF, 1, 0, 17 }, - Package(){0x0000FFFF, 2, 0, 18 }, - Package(){0x0000FFFF, 3, 0, 19 }, - }) - - Name(PE1, Package(){ - /* PCIe slot - Hooked to PCIe slot 10 */ - Package(){0x0000FFFF, 0, INTB, 0 }, - Package(){0x0000FFFF, 1, INTC, 0 }, - Package(){0x0000FFFF, 2, INTD, 0 }, - Package(){0x0000FFFF, 3, INTA, 0 }, - }) - Name(APE1, Package(){ - /* PCIe slot - Hooked to PCIe */ - Package(){0x0000FFFF, 0, 0, 17 }, - Package(){0x0000FFFF, 1, 0, 18 }, - Package(){0x0000FFFF, 2, 0, 19 }, - Package(){0x0000FFFF, 3, 0, 16 }, - }) - - Name(PE2, Package(){ - /* PCIe slot - Hooked to PCIe slot 10 */ - Package(){0x0000FFFF, 0, INTC, 0 }, - Package(){0x0000FFFF, 1, INTD, 0 }, - Package(){0x0000FFFF, 2, INTA, 0 }, - Package(){0x0000FFFF, 3, INTB, 0 }, - }) - Name(APE2, Package(){ - /* PCIe slot - Hooked to PCIe */ - Package(){0x0000FFFF, 0, 0, 18 }, - Package(){0x0000FFFF, 1, 0, 19 }, - Package(){0x0000FFFF, 2, 0, 16 }, - Package(){0x0000FFFF, 3, 0, 17 }, - }) - - Name(PE3, Package(){ - /* PCIe slot - Hooked to PCIe slot 10 */ - Package(){0x0000FFFF, 0, INTD, 0 }, - Package(){0x0000FFFF, 1, INTA, 0 }, - Package(){0x0000FFFF, 2, INTB, 0 }, - Package(){0x0000FFFF, 3, INTC, 0 }, - }) - Name(APE3, Package(){ - /* PCIe slot - Hooked to PCIe */ - Package(){0x0000FFFF, 0, 0, 19 }, - Package(){0x0000FFFF, 1, 0, 16 }, - Package(){0x0000FFFF, 2, 0, 17 }, - Package(){0x0000FFFF, 3, 0, 18 }, - }) - - Name(PCIB, Package(){ - /* PCI slots: slot 0, slot 1, slot 2 behind Dev14, Fun4. */ - Package(){0x0005FFFF, 0, 0, 0x14 }, - Package(){0x0005FFFF, 1, 0, 0x15 }, - Package(){0x0005FFFF, 2, 0, 0x16 }, - Package(){0x0005FFFF, 3, 0, 0x17 }, - Package(){0x0006FFFF, 0, 0, 0x15 }, - Package(){0x0006FFFF, 1, 0, 0x16 }, - Package(){0x0006FFFF, 2, 0, 0x17 }, - Package(){0x0006FFFF, 3, 0, 0x14 }, - Package(){0x0007FFFF, 0, 0, 0x16 }, - Package(){0x0007FFFF, 1, 0, 0x17 }, - Package(){0x0007FFFF, 2, 0, 0x14 }, - Package(){0x0007FFFF, 3, 0, 0x15 }, - }) -} diff --git a/src/mainboard/advansus/a785e-i/acpi/sata.asl b/src/mainboard/advansus/a785e-i/acpi/sata.asl deleted file mode 100644 index 9e0e535da6..0000000000 --- a/src/mainboard/advansus/a785e-i/acpi/sata.asl +++ /dev/null @@ -1,145 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -/* simple name description */ - -/* -Scope (_SB) { - Device(PCI0) { - Device(SATA) { - Name(_ADR, 0x00110000) - #include "sata.asl" - } - } -} -*/ - -Name(STTM, Buffer(20) { - 0x78, 0x00, 0x00, 0x00, 0x0f, 0x00, 0x00, 0x00, - 0x78, 0x00, 0x00, 0x00, 0x0f, 0x00, 0x00, 0x00, - 0x1f, 0x00, 0x00, 0x00 -}) - -/* Start by clearing the PhyRdyChg bits */ -Method(_INI) { - \_GPE._L1F() -} - -Device(PMRY) -{ - Name(_ADR, 0) - Method(_GTM, 0x0, NotSerialized) { - Return(STTM) - } - Method(_STM, 0x3, NotSerialized) {} - - Device(PMST) { - Name(_ADR, 0) - Method(_STA,0) { - if (LGreater(P0IS,0)) { - return (0x0F) /* sata is visible */ - } - else { - return (0x00) /* sata is missing */ - } - } - }/* end of PMST */ - - Device(PSLA) - { - Name(_ADR, 1) - Method(_STA,0) { - if (LGreater(P1IS,0)) { - return (0x0F) /* sata is visible */ - } - else { - return (0x00) /* sata is missing */ - } - } - } /* end of PSLA */ -} /* end of PMRY */ - - -Device(SEDY) -{ - Name(_ADR, 1) /* IDE Scondary Channel */ - Method(_GTM, 0x0, NotSerialized) { - Return(STTM) - } - Method(_STM, 0x3, NotSerialized) {} - - Device(SMST) - { - Name(_ADR, 0) - Method(_STA,0) { - if (LGreater(P2IS,0)) { - return (0x0F) /* sata is visible */ - } - else { - return (0x00) /* sata is missing */ - } - } - } /* end of SMST */ - - Device(SSLA) - { - Name(_ADR, 1) - Method(_STA,0) { - if (LGreater(P3IS,0)) { - return (0x0F) /* sata is visible */ - } - else { - return (0x00) /* sata is missing */ - } - } - } /* end of SSLA */ -} /* end of SEDY */ - -/* SATA Hot Plug Support */ -Scope(\_GPE) { - Method(_L1F,0x0,NotSerialized) { - if (\_SB.P0PR) { - if (LGreater(\_SB.P0IS,0)) { - sleep(32) - } - Notify(\_SB.PCI0.STCR.PMRY.PMST, 0x01) /* NOTIFY_DEVICE_CHECK */ - store(one, \_SB.P0PR) - } - - if (\_SB.P1PR) { - if (LGreater(\_SB.P1IS,0)) { - sleep(32) - } - Notify(\_SB.PCI0.STCR.PMRY.PSLA, 0x01) /* NOTIFY_DEVICE_CHECK */ - store(one, \_SB.P1PR) - } - - if (\_SB.P2PR) { - if (LGreater(\_SB.P2IS,0)) { - sleep(32) - } - Notify(\_SB.PCI0.STCR.SEDY.SMST, 0x01) /* NOTIFY_DEVICE_CHECK */ - store(one, \_SB.P2PR) - } - - if (\_SB.P3PR) { - if (LGreater(\_SB.P3IS,0)) { - sleep(32) - } - Notify(\_SB.PCI0.STCR.SEDY.SSLA, 0x01) /* NOTIFY_DEVICE_CHECK */ - store(one, \_SB.P3PR) - } - } -} diff --git a/src/mainboard/advansus/a785e-i/acpi/usb.asl b/src/mainboard/advansus/a785e-i/acpi/usb.asl deleted file mode 100644 index cd76bf1f94..0000000000 --- a/src/mainboard/advansus/a785e-i/acpi/usb.asl +++ /dev/null @@ -1,158 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -/* simple name description */ -/* -#include -DefinitionBlock ("DSDT.AML", "DSDT", 0x01, OEM_ID, ACPI_TABLE_CREATOR, 0x00010001 - ) - { - #include "usb.asl" - } -*/ -Method(UCOC, 0) { - Sleep(20) - Store(0x13,CMTI) - Store(0,GPSL) -} - -/* USB Port 0 overcurrent uses Gpm 0 */ -If(LLessEqual(UOM0,9)) { - Scope (\_GPE) { - Method (_L13) { - UCOC() - if(LEqual(GPB0,PLC0)) { - Not(PLC0,PLC0) - Store(PLC0, \_SB.PT0D) - } - } - } -} - -/* USB Port 1 overcurrent uses Gpm 1 */ -If (LLessEqual(UOM1,9)) { - Scope (\_GPE) { - Method (_L14) { - UCOC() - if (LEqual(GPB1,PLC1)) { - Not(PLC1,PLC1) - Store(PLC1, \_SB.PT1D) - } - } - } -} - -/* USB Port 2 overcurrent uses Gpm 2 */ -If (LLessEqual(UOM2,9)) { - Scope (\_GPE) { - Method (_L15) { - UCOC() - if (LEqual(GPB2,PLC2)) { - Not(PLC2,PLC2) - Store(PLC2, \_SB.PT2D) - } - } - } -} - -/* USB Port 3 overcurrent uses Gpm 3 */ -If (LLessEqual(UOM3,9)) { - Scope (\_GPE) { - Method (_L16) { - UCOC() - if (LEqual(GPB3,PLC3)) { - Not(PLC3,PLC3) - Store(PLC3, \_SB.PT3D) - } - } - } -} - -/* USB Port 4 overcurrent uses Gpm 4 */ -If (LLessEqual(UOM4,9)) { - Scope (\_GPE) { - Method (_L19) { - UCOC() - if (LEqual(GPB4,PLC4)) { - Not(PLC4,PLC4) - Store(PLC4, \_SB.PT4D) - } - } - } -} - -/* USB Port 5 overcurrent uses Gpm 5 */ -If (LLessEqual(UOM5,9)) { - Scope (\_GPE) { - Method (_L1A) { - UCOC() - if (LEqual(GPB5,PLC5)) { - Not(PLC5,PLC5) - Store(PLC5, \_SB.PT5D) - } - } - } -} - -/* USB Port 6 overcurrent uses Gpm 6 */ -If (LLessEqual(UOM6,9)) { - Scope (\_GPE) { - /* Method (_L1C) { */ - Method (_L06) { - UCOC() - if (LEqual(GPB6,PLC6)) { - Not(PLC6,PLC6) - Store(PLC6, \_SB.PT6D) - } - } - } -} - -/* USB Port 7 overcurrent uses Gpm 7 */ -If (LLessEqual(UOM7,9)) { - Scope (\_GPE) { - /* Method (_L1D) { */ - Method (_L07) { - UCOC() - if (LEqual(GPB7,PLC7)) { - Not(PLC7,PLC7) - Store(PLC7, \_SB.PT7D) - } - } - } -} - -/* USB Port 8 overcurrent uses Gpm 8 */ -If (LLessEqual(UOM8,9)) { - Scope (\_GPE) { - Method (_L17) { - if (LEqual(G8IS,PLC8)) { - Not(PLC8,PLC8) - Store(PLC8, \_SB.PT8D) - } - } - } -} - -/* USB Port 9 overcurrent uses Gpm 9 */ -If (LLessEqual(UOM9,9)) { - Scope (\_GPE) { - Method (_L0E) { - if (LEqual(G9IS,0)) { - Store(1,\_SB.PT9D) - } - } - } -} diff --git a/src/mainboard/advansus/a785e-i/acpi_tables.c b/src/mainboard/advansus/a785e-i/acpi_tables.c deleted file mode 100644 index 7f429996fd..0000000000 --- a/src/mainboard/advansus/a785e-i/acpi_tables.c +++ /dev/null @@ -1,44 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include -#include - -unsigned long acpi_fill_madt(unsigned long current) -{ - /* create all subtables for processors */ - current = acpi_create_madt_lapics(current); - - /* Write SB800 IOAPIC, only one */ - current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, 2, - IO_APIC_ADDR, 0); - - current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) - current, 0, 0, 2, 0); - current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) - current, 0, 9, 9, 0xF); - /* 0: mean bus 0--->ISA */ - /* 0: PIC 0 */ - /* 2: APIC 2 */ - /* 5 mean: 0101 --> Edge-triggered, Active high */ - - /* create all subtables for processors */ - /* current = acpi_create_madt_lapic_nmis(current, 5, 1); */ - /* 1: LINT1 connect to NMI */ - - return current; -} diff --git a/src/mainboard/advansus/a785e-i/board_info.txt b/src/mainboard/advansus/a785e-i/board_info.txt deleted file mode 100644 index 3c865ec331..0000000000 --- a/src/mainboard/advansus/a785e-i/board_info.txt +++ /dev/null @@ -1,5 +0,0 @@ -Category: mini -Board URL: http://www.advansus.com.tw/products/247/A785E-I -ROM package: SOIC-8 -ROM protocol: SPI -ROM socketed: n diff --git a/src/mainboard/advansus/a785e-i/cmos.layout b/src/mainboard/advansus/a785e-i/cmos.layout deleted file mode 100644 index 6c3d3f6c9e..0000000000 --- a/src/mainboard/advansus/a785e-i/cmos.layout +++ /dev/null @@ -1,52 +0,0 @@ -entries - -0 384 r 0 reserved_memory -384 1 e 4 boot_option -388 4 h 0 reboot_counter -#392 3 r 0 unused -395 1 e 1 hw_scrubber -396 1 e 1 interleave_chip_selects -397 2 e 8 max_mem_clock -399 1 e 2 multi_core -400 1 e 1 power_on_after_fail -412 4 e 6 debug_level -440 4 e 9 slow_cpu -444 1 e 1 nmi -445 1 e 1 gart -456 1 e 1 ECC_memory -728 256 h 0 user_data -984 16 h 0 check_sum -# Reserve the extended AMD configuration registers -1000 24 r 0 amd_reserved - - - -enumerations - -#ID value text -1 0 Disable -1 1 Enable -2 0 Enable -2 1 Disable -4 0 Fallback -4 1 Normal -6 5 Notice -6 6 Info -6 7 Debug -6 8 Spew -8 0 400Mhz -8 1 333Mhz -8 2 266Mhz -8 3 200Mhz -9 0 off -9 1 87.5% -9 2 75.0% -9 3 62.5% -9 4 50.0% -9 5 37.5% -9 6 25.0% -9 7 12.5% - -checksums - -checksum 392 983 984 diff --git a/src/mainboard/advansus/a785e-i/devicetree.cb b/src/mainboard/advansus/a785e-i/devicetree.cb deleted file mode 100644 index c78c508474..0000000000 --- a/src/mainboard/advansus/a785e-i/devicetree.cb +++ /dev/null @@ -1,124 +0,0 @@ -# sample config for advansus/A785E-I -chip northbridge/amd/amdfam10/root_complex - device cpu_cluster 0 on - chip cpu/amd/socket_ASB2 #L1 and DDR3 - device lapic 0 on end - end - end - device domain 0 on - subsystemid 0x1612 0x3060 inherit #TODO: Set the correctly subsystem id. - chip northbridge/amd/amdfam10 - device pci 18.0 on # northbridge - chip southbridge/amd/rs780 - device pci 0.0 on end # HT 0x9600 - device pci 1.0 on end # Internal Graphics P2P bridge 0x9712 - device pci 2.0 on end # PCIE P2P bridge (external graphics) 0x9603 - device pci 3.0 off end # PCIE P2P bridge 0x960b - device pci 4.0 on end # PCIE P2P bridge 0x9604 wireless - device pci 5.0 off end # PCIE P2P bridge 0x9605 - device pci 6.0 off end # PCIE P2P bridge 0x9606 - device pci 7.0 off end # PCIE P2P bridge 0x9607 - device pci 8.0 off end # NB/SB Link P2P bridge - device pci 9.0 on end # Ethernet - device pci a.0 on end # Ethernet - register "gppsb_configuration" = "4" # Configuration E - register "gpp_configuration" = "3" # Configuration D - register "port_enable" = "0x6f6" - register "gfx_dev2_dev3" = "0" - register "gfx_dual_slot" = "0" - register "gfx_lane_reversal" = "0" - register "gfx_compliance" = "0" - register "gfx_reconfiguration" = "1" - register "gfx_link_width" = "0" - register "gfx_tmds" = "1" - register "gfx_pcie_config" = "3" # 1x8 GFX on Lanes 8-15 - register "gfx_ddi_config" = "1" # Lanes 0-3 DDI_SL - end - chip southbridge/amd/cimx/sb800 # it is under NB/SB Link, but on the same pci bus - device pci 11.0 on end # SATA - device pci 12.0 on end # USB - device pci 12.2 on end # USB - device pci 13.0 on end # USB - device pci 13.2 on end # USB - device pci 14.0 on # SM - chip drivers/generic/generic #dimm 0-0-0 - device i2c 50 on end - end - chip drivers/generic/generic #dimm 0-0-1 - device i2c 51 on end - end - chip drivers/generic/generic #dimm 0-1-0 - device i2c 52 on end - end - chip drivers/generic/generic #dimm 0-1-1 - device i2c 53 on end - end - end # SM - device pci 14.1 on end # IDE 0x439c - device pci 14.2 on end # HDA 0x4383 - device pci 14.3 on - chip superio/winbond/w83627hf - device pnp 2e.0 off # Floppy - io 0x60 = 0x3f0 - irq 0x70 = 6 - drq 0x74 = 2 - end - device pnp 2e.1 off # Parallel Port - io 0x60 = 0x378 - irq 0x70 = 7 - end - device pnp 2e.2 on # Com1 - io 0x60 = 0x3f8 - irq 0x70 = 4 - end - device pnp 2e.3 on # Com2 - io 0x60 = 0x2f8 - irq 0x70 = 3 - end - device pnp 2e.5 on # Keyboard - io 0x60 = 0x60 - io 0x62 = 0x64 - irq 0x70 = 1 - irq 0x72 = 12 - end - device pnp 2e.6 off # SFI - io 0x62 = 0x100 - end - device pnp 2e.7 off # GPIO_GAME_MIDI - io 0x60 = 0x220 - io 0x62 = 0x300 - irq 0x70 = 9 - end - device pnp 2e.8 off end # WDTO_PLED - device pnp 2e.9 off end # GPIO_SUSLED - device pnp 2e.a off end # ACPI - device pnp 2e.b on # HW Monitor - io 0x60 = 0x290 - irq 0x70 = 5 - end - end #superio/winbond/w83627hf - end # LPC 0x439d - device pci 14.4 off end # PCIB 0x4384, NOTE: PCI interface pins shared with GPIO {GPIO 35:0} - device pci 14.5 on end # USB 2 - device pci 14.6 off end # Gec - device pci 15.0 on end # PCIe 0 - device pci 15.1 on end # PCIe 1 - device pci 15.2 on end # PCIe 2 - device pci 15.3 on end # PCIe 3 - device pci 16.0 on end # USB - device pci 16.2 on end # USB - #register "gpp_configuration" = "0" #4:0:0:0 - #register "gpp_configuration" = "2" #2:2:0:0 - #register "gpp_configuration" = "3" #2:1:1:0 - register "gpp_configuration" = "4" #1:1:1:1 - register "boot_switch_sata_ide" = "0" # 0: boot from SATA. 1: IDE - end #southbridge/amd/cimx/sb800 - end # device pci 18.0 - - device pci 18.1 on end - device pci 18.2 on end - device pci 18.3 on end - device pci 18.4 on end - end - end #domain -end diff --git a/src/mainboard/advansus/a785e-i/dsdt.asl b/src/mainboard/advansus/a785e-i/dsdt.asl deleted file mode 100644 index 8015ec6f32..0000000000 --- a/src/mainboard/advansus/a785e-i/dsdt.asl +++ /dev/null @@ -1,1613 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -/* DefinitionBlock Statement */ -#include -DefinitionBlock ( - "DSDT.AML", /* Output filename */ - "DSDT", /* Signature */ - 0x02, /* DSDT Revision, needs to be 2 for 64bit */ - OEM_ID, - ACPI_TABLE_CREATOR, - 0x00010001 /* OEM Revision */ - ) -{ /* Start of ASL file */ - /* #include */ /* Include global debug methods if needed */ - - /* Data to be patched by the BIOS during POST */ - /* FIXME the patching is not done yet! */ - /* Memory related values */ - Name(LOMH, 0x0) /* Start of unused memory in C0000-E0000 range */ - Name(PBAD, 0x0) /* Address of BIOS area (If TOM2 != 0, Addr >> 16) */ - Name(PBLN, 0x0) /* Length of BIOS area */ - - Name(PCBA, 0xE0000000) /* Base address of PCIe config space */ - Name(HPBA, 0xFED00000) /* Base address of HPET table */ - - /* USB overcurrent mapping pins. */ - Name(UOM0, 0) - Name(UOM1, 2) - Name(UOM2, 0) - Name(UOM3, 7) - Name(UOM4, 2) - Name(UOM5, 2) - Name(UOM6, 6) - Name(UOM7, 2) - Name(UOM8, 6) - Name(UOM9, 6) - - /* Some global data */ - Name(OSVR, 3) /* Assume nothing. WinXp = 1, Vista = 2, Linux = 3, WinCE = 4 */ - Name(OSV, Ones) /* Assume nothing */ - Name(PMOD, One) /* Assume APIC */ - - /* - * Processor Object - * - */ - Scope (\_PR) { /* define processor scope */ - Device (CPU0) { - Name (_HID, "ACPI0007") - Name (_UID, 0) - #include "acpi/cpstate.asl" - } - Device (CPU1) { - Name (_HID, "ACPI0007") - Name (_UID, 1) - #include "acpi/cpstate.asl" - } - Device (CPU2) { - Name (_HID, "ACPI0007") - Name (_UID, 2) - #include "acpi/cpstate.asl" - } - Device (CPU3) { - Name (_HID, "ACPI0007") - Name (_UID, 3) - #include "acpi/cpstate.asl" - } - } /* End _PR scope */ - - /* PIC IRQ mapping registers, C00h-C01h. */ - OperationRegion(PRQM, SystemIO, 0x00000C00, 0x00000002) - Field(PRQM, ByteAcc, NoLock, Preserve) { - PRQI, 0x00000008, - PRQD, 0x00000008, /* Offset: 1h */ - } - IndexField(PRQI, PRQD, ByteAcc, NoLock, Preserve) { - PIRA, 0x00000008, /* Index 0 */ - PIRB, 0x00000008, /* Index 1 */ - PIRC, 0x00000008, /* Index 2 */ - PIRD, 0x00000008, /* Index 3 */ - PIRE, 0x00000008, /* Index 4 */ - PIRF, 0x00000008, /* Index 5 */ - PIRG, 0x00000008, /* Index 6 */ - PIRH, 0x00000008, /* Index 7 */ - } - - /* PCI Error control register */ - OperationRegion(PERC, SystemIO, 0x00000C14, 0x00000001) - Field(PERC, ByteAcc, NoLock, Preserve) { - SENS, 0x00000001, - PENS, 0x00000001, - SENE, 0x00000001, - PENE, 0x00000001, - } - - /* Client Management index/data registers */ - OperationRegion(CMT, SystemIO, 0x00000C50, 0x00000002) - Field(CMT, ByteAcc, NoLock, Preserve) { - CMTI, 8, - /* Client Management Data register */ - G64E, 1, - G64O, 1, - G32O, 2, - , 2, - GPSL, 2, - } - - /* GPM Port register */ - OperationRegion(GPT, SystemIO, 0x00000C52, 0x00000001) - Field(GPT, ByteAcc, NoLock, Preserve) { - GPB0,1, - GPB1,1, - GPB2,1, - GPB3,1, - GPB4,1, - GPB5,1, - GPB6,1, - GPB7,1, - } - - /* Flash ROM program enable register */ - OperationRegion(FRE, SystemIO, 0x00000C6F, 0x00000001) - Field(FRE, ByteAcc, NoLock, Preserve) { - , 0x00000006, - FLRE, 0x00000001, - } - - /* PM2 index/data registers */ - OperationRegion(PM2R, SystemIO, 0x00000CD0, 0x00000002) - Field(PM2R, ByteAcc, NoLock, Preserve) { - PM2I, 0x00000008, - PM2D, 0x00000008, - } - - /* Power Management I/O registers, TODO:PMIO is quite different in SB800. */ - OperationRegion(PIOR, SystemIO, 0x00000CD6, 0x00000002) - Field(PIOR, ByteAcc, NoLock, Preserve) { - PIOI, 0x00000008, - PIOD, 0x00000008, - } - IndexField (PIOI, PIOD, ByteAcc, NoLock, Preserve) { - Offset(0x00), /* MiscControl */ - , 1, - T1EE, 1, - T2EE, 1, - Offset(0x01), /* MiscStatus */ - , 1, - T1E, 1, - T2E, 1, - Offset(0x04), /* SmiWakeUpEventEnable3 */ - , 7, - SSEN, 1, - Offset(0x07), /* SmiWakeUpEventStatus3 */ - , 7, - CSSM, 1, - Offset(0x10), /* AcpiEnable */ - , 6, - PWDE, 1, - Offset(0x1C), /* ProgramIoEnable */ - , 3, - MKME, 1, - IO3E, 1, - IO2E, 1, - IO1E, 1, - IO0E, 1, - Offset(0x1D), /* IOMonitorStatus */ - , 3, - MKMS, 1, - IO3S, 1, - IO2S, 1, - IO1S, 1, - IO0S,1, - Offset(0x20), /* AcpiPmEvtBlk. TODO: should be 0x60 */ - APEB, 16, - Offset(0x36), /* GEvtLevelConfig */ - , 6, - ELC6, 1, - ELC7, 1, - Offset(0x37), /* GPMLevelConfig0 */ - , 3, - PLC0, 1, - PLC1, 1, - PLC2, 1, - PLC3, 1, - PLC8, 1, - Offset(0x38), /* GPMLevelConfig1 */ - , 1, - PLC4, 1, - PLC5, 1, - , 1, - PLC6, 1, - PLC7, 1, - Offset(0x3B), /* PMEStatus1 */ - GP0S, 1, - GM4S, 1, - GM5S, 1, - APS, 1, - GM6S, 1, - GM7S, 1, - GP2S, 1, - STSS, 1, - Offset(0x55), /* SoftPciRst */ - SPRE, 1, - , 1, - , 1, - PNAT, 1, - PWMK, 1, - PWNS, 1, - - /* Offset(0x61), */ /* Options_1 */ - /* ,7, */ - /* R617,1, */ - - Offset(0x65), /* UsbPMControl */ - , 4, - URRE, 1, - Offset(0x68), /* MiscEnable68 */ - , 3, - TMTE, 1, - , 1, - Offset(0x92), /* GEVENTIN */ - , 7, - E7IS, 1, - Offset(0x96), /* GPM98IN */ - G8IS, 1, - G9IS, 1, - Offset(0x9A), /* EnhanceControl */ - ,7, - HPDE, 1, - Offset(0xA8), /* PIO7654Enable */ - IO4E, 1, - IO5E, 1, - IO6E, 1, - IO7E, 1, - Offset(0xA9), /* PIO7654Status */ - IO4S, 1, - IO5S, 1, - IO6S, 1, - IO7S, 1, - } - - /* PM1 Event Block - * First word is PM1_Status, Second word is PM1_Enable - */ - OperationRegion(P1EB, SystemIO, APEB, 0x04) - Field(P1EB, ByteAcc, NoLock, Preserve) { - TMST, 1, - , 3, - BMST, 1, - GBST, 1, - Offset(0x01), - PBST, 1, - , 1, - RTST, 1, - , 3, - PWST, 1, - SPWS, 1, - Offset(0x02), - TMEN, 1, - , 4, - GBEN, 1, - Offset(0x03), - PBEN, 1, - , 1, - RTEN, 1, - , 3, - PWDA, 1, - } - - Scope(\_SB) { - /* PCIe Configuration Space for 16 busses */ - OperationRegion(PCFG, SystemMemory, PCBA, 0x01000000) /* Each bus consumes 1MB */ - Field(PCFG, ByteAcc, NoLock, Preserve) { - /* Byte offsets are computed using the following technique: - * ((bus number + 1) * ((device number * 8) * 4096)) + register offset - * The 8 comes from 8 functions per device, and 4096 bytes per function config space - */ - Offset(0x00088024), /* Byte offset to SATA register 24h - Bus 0, Device 17, Function 0 */ - STB5, 32, - Offset(0x00098042), /* Byte offset to OHCI0 register 42h - Bus 0, Device 19, Function 0 */ - PT0D, 1, - PT1D, 1, - PT2D, 1, - PT3D, 1, - PT4D, 1, - PT5D, 1, - PT6D, 1, - PT7D, 1, - PT8D, 1, - PT9D, 1, - Offset(0x000A0004), /* Byte offset to SMBUS register 4h - Bus 0, Device 20, Function 0 */ - SBIE, 1, - SBME, 1, - Offset(0x000A0008), /* Byte offset to SMBUS register 8h - Bus 0, Device 20, Function 0 */ - SBRI, 8, - Offset(0x000A0014), /* Byte offset to SMBUS register 14h - Bus 0, Device 20, Function 0 */ - SBB1, 32, - Offset(0x000A0078), /* Byte offset to SMBUS register 78h - Bus 0, Device 20, Function 0 */ - ,14, - P92E, 1, /* Port92 decode enable */ - } - - OperationRegion(SB5, SystemMemory, STB5, 0x1000) - Field(SB5, AnyAcc, NoLock, Preserve){ - /* Port 0 */ - Offset(0x120), /* Port 0 Task file status */ - P0ER, 1, - , 2, - P0DQ, 1, - , 3, - P0BY, 1, - Offset(0x128), /* Port 0 Serial ATA status */ - P0DD, 4, - , 4, - P0IS, 4, - Offset(0x12C), /* Port 0 Serial ATA control */ - P0DI, 4, - Offset(0x130), /* Port 0 Serial ATA error */ - , 16, - P0PR, 1, - - /* Port 1 */ - offset(0x1A0), /* Port 1 Task file status */ - P1ER, 1, - , 2, - P1DQ, 1, - , 3, - P1BY, 1, - Offset(0x1A8), /* Port 1 Serial ATA status */ - P1DD, 4, - , 4, - P1IS, 4, - Offset(0x1AC), /* Port 1 Serial ATA control */ - P1DI, 4, - Offset(0x1B0), /* Port 1 Serial ATA error */ - , 16, - P1PR, 1, - - /* Port 2 */ - Offset(0x220), /* Port 2 Task file status */ - P2ER, 1, - , 2, - P2DQ, 1, - , 3, - P2BY, 1, - Offset(0x228), /* Port 2 Serial ATA status */ - P2DD, 4, - , 4, - P2IS, 4, - Offset(0x22C), /* Port 2 Serial ATA control */ - P2DI, 4, - Offset(0x230), /* Port 2 Serial ATA error */ - , 16, - P2PR, 1, - - /* Port 3 */ - Offset(0x2A0), /* Port 3 Task file status */ - P3ER, 1, - , 2, - P3DQ, 1, - , 3, - P3BY, 1, - Offset(0x2A8), /* Port 3 Serial ATA status */ - P3DD, 4, - , 4, - P3IS, 4, - Offset(0x2AC), /* Port 3 Serial ATA control */ - P3DI, 4, - Offset(0x2B0), /* Port 3 Serial ATA error */ - , 16, - P3PR, 1, - } - } - - - #include "acpi/routing.asl" - - Scope(\_SB) { - - Method(OSFL, 0){ - - if(LNotEqual(OSVR, Ones)) {Return(OSVR)} /* OS version was already detected */ - - if(CondRefOf(\_OSI)) - { - Store(1, OSVR) /* Assume some form of XP */ - if (\_OSI("Windows 2006")) /* Vista */ - { - Store(2, OSVR) - } - } else { - If(WCMP(\_OS,"Linux")) { - Store(3, OSVR) /* Linux */ - } Else { - Store(4, OSVR) /* Gotta be WinCE */ - } - } - Return(OSVR) - } - - Method(_PIC, 0x01, NotSerialized) - { - If (Arg0) - { - \_SB.CIRQ() - } - Store(Arg0, PMOD) - } - Method(CIRQ, 0x00, NotSerialized){ - Store(0, PIRA) - Store(0, PIRB) - Store(0, PIRC) - Store(0, PIRD) - Store(0, PIRE) - Store(0, PIRF) - Store(0, PIRG) - Store(0, PIRH) - } - - Name(IRQB, ResourceTemplate(){ - IRQ(Level,ActiveLow,Shared){15} - }) - - Name(IRQP, ResourceTemplate(){ - IRQ(Level,ActiveLow,Exclusive){3, 4, 5, 7, 10, 11, 12, 15} - }) - - Name(PITF, ResourceTemplate(){ - IRQ(Level,ActiveLow,Exclusive){9} - }) - - Device(INTA) { - Name(_HID, EISAID("PNP0C0F")) - Name(_UID, 1) - - Method(_STA, 0) { - if (PIRA) { - Return(0x0B) /* sata is invisible */ - } else { - Return(0x09) /* sata is disabled */ - } - } /* End Method(_SB.INTA._STA) */ - - Method(_DIS ,0) { - /* DBGO("\\_SB\\LNKA\\_DIS\n") */ - Store(0, PIRA) - } /* End Method(_SB.INTA._DIS) */ - - Method(_PRS ,0) { - /* DBGO("\\_SB\\LNKA\\_PRS\n") */ - Return(IRQP) - } /* Method(_SB.INTA._PRS) */ - - Method(_CRS ,0) { - /* DBGO("\\_SB\\LNKA\\_CRS\n") */ - CreateWordField(IRQB, 0x1, IRQN) - ShiftLeft(1, PIRA, IRQN) - Return(IRQB) - } /* Method(_SB.INTA._CRS) */ - - Method(_SRS, 1) { - /* DBGO("\\_SB\\LNKA\\_CRS\n") */ - CreateWordField(ARG0, 1, IRQM) - - /* Use lowest available IRQ */ - FindSetRightBit(IRQM, Local0) - if (Local0) { - Decrement(Local0) - } - Store(Local0, PIRA) - } /* End Method(_SB.INTA._SRS) */ - } /* End Device(INTA) */ - - Device(INTB) { - Name(_HID, EISAID("PNP0C0F")) - Name(_UID, 2) - - Method(_STA, 0) { - if (PIRB) { - Return(0x0B) /* sata is invisible */ - } else { - Return(0x09) /* sata is disabled */ - } - } /* End Method(_SB.INTB._STA) */ - - Method(_DIS ,0) { - /* DBGO("\\_SB\\LNKB\\_DIS\n") */ - Store(0, PIRB) - } /* End Method(_SB.INTB._DIS) */ - - Method(_PRS ,0) { - /* DBGO("\\_SB\\LNKB\\_PRS\n") */ - Return(IRQP) - } /* Method(_SB.INTB._PRS) */ - - Method(_CRS ,0) { - /* DBGO("\\_SB\\LNKB\\_CRS\n") */ - CreateWordField(IRQB, 0x1, IRQN) - ShiftLeft(1, PIRB, IRQN) - Return(IRQB) - } /* Method(_SB.INTB._CRS) */ - - Method(_SRS, 1) { - /* DBGO("\\_SB\\LNKB\\_CRS\n") */ - CreateWordField(ARG0, 1, IRQM) - - /* Use lowest available IRQ */ - FindSetRightBit(IRQM, Local0) - if (Local0) { - Decrement(Local0) - } - Store(Local0, PIRB) - } /* End Method(_SB.INTB._SRS) */ - } /* End Device(INTB) */ - - Device(INTC) { - Name(_HID, EISAID("PNP0C0F")) - Name(_UID, 3) - - Method(_STA, 0) { - if (PIRC) { - Return(0x0B) /* sata is invisible */ - } else { - Return(0x09) /* sata is disabled */ - } - } /* End Method(_SB.INTC._STA) */ - - Method(_DIS ,0) { - /* DBGO("\\_SB\\LNKC\\_DIS\n") */ - Store(0, PIRC) - } /* End Method(_SB.INTC._DIS) */ - - Method(_PRS ,0) { - /* DBGO("\\_SB\\LNKC\\_PRS\n") */ - Return(IRQP) - } /* Method(_SB.INTC._PRS) */ - - Method(_CRS ,0) { - /* DBGO("\\_SB\\LNKC\\_CRS\n") */ - CreateWordField(IRQB, 0x1, IRQN) - ShiftLeft(1, PIRC, IRQN) - Return(IRQB) - } /* Method(_SB.INTC._CRS) */ - - Method(_SRS, 1) { - /* DBGO("\\_SB\\LNKC\\_CRS\n") */ - CreateWordField(ARG0, 1, IRQM) - - /* Use lowest available IRQ */ - FindSetRightBit(IRQM, Local0) - if (Local0) { - Decrement(Local0) - } - Store(Local0, PIRC) - } /* End Method(_SB.INTC._SRS) */ - } /* End Device(INTC) */ - - Device(INTD) { - Name(_HID, EISAID("PNP0C0F")) - Name(_UID, 4) - - Method(_STA, 0) { - if (PIRD) { - Return(0x0B) /* sata is invisible */ - } else { - Return(0x09) /* sata is disabled */ - } - } /* End Method(_SB.INTD._STA) */ - - Method(_DIS ,0) { - /* DBGO("\\_SB\\LNKD\\_DIS\n") */ - Store(0, PIRD) - } /* End Method(_SB.INTD._DIS) */ - - Method(_PRS ,0) { - /* DBGO("\\_SB\\LNKD\\_PRS\n") */ - Return(IRQP) - } /* Method(_SB.INTD._PRS) */ - - Method(_CRS ,0) { - /* DBGO("\\_SB\\LNKD\\_CRS\n") */ - CreateWordField(IRQB, 0x1, IRQN) - ShiftLeft(1, PIRD, IRQN) - Return(IRQB) - } /* Method(_SB.INTD._CRS) */ - - Method(_SRS, 1) { - /* DBGO("\\_SB\\LNKD\\_CRS\n") */ - CreateWordField(ARG0, 1, IRQM) - - /* Use lowest available IRQ */ - FindSetRightBit(IRQM, Local0) - if (Local0) { - Decrement(Local0) - } - Store(Local0, PIRD) - } /* End Method(_SB.INTD._SRS) */ - } /* End Device(INTD) */ - - Device(INTE) { - Name(_HID, EISAID("PNP0C0F")) - Name(_UID, 5) - - Method(_STA, 0) { - if (PIRE) { - Return(0x0B) /* sata is invisible */ - } else { - Return(0x09) /* sata is disabled */ - } - } /* End Method(_SB.INTE._STA) */ - - Method(_DIS ,0) { - /* DBGO("\\_SB\\LNKE\\_DIS\n") */ - Store(0, PIRE) - } /* End Method(_SB.INTE._DIS) */ - - Method(_PRS ,0) { - /* DBGO("\\_SB\\LNKE\\_PRS\n") */ - Return(IRQP) - } /* Method(_SB.INTE._PRS) */ - - Method(_CRS ,0) { - /* DBGO("\\_SB\\LNKE\\_CRS\n") */ - CreateWordField(IRQB, 0x1, IRQN) - ShiftLeft(1, PIRE, IRQN) - Return(IRQB) - } /* Method(_SB.INTE._CRS) */ - - Method(_SRS, 1) { - /* DBGO("\\_SB\\LNKE\\_CRS\n") */ - CreateWordField(ARG0, 1, IRQM) - - /* Use lowest available IRQ */ - FindSetRightBit(IRQM, Local0) - if (Local0) { - Decrement(Local0) - } - Store(Local0, PIRE) - } /* End Method(_SB.INTE._SRS) */ - } /* End Device(INTE) */ - - Device(INTF) { - Name(_HID, EISAID("PNP0C0F")) - Name(_UID, 6) - - Method(_STA, 0) { - if (PIRF) { - Return(0x0B) /* sata is invisible */ - } else { - Return(0x09) /* sata is disabled */ - } - } /* End Method(_SB.INTF._STA) */ - - Method(_DIS ,0) { - /* DBGO("\\_SB\\LNKF\\_DIS\n") */ - Store(0, PIRF) - } /* End Method(_SB.INTF._DIS) */ - - Method(_PRS ,0) { - /* DBGO("\\_SB\\LNKF\\_PRS\n") */ - Return(PITF) - } /* Method(_SB.INTF._PRS) */ - - Method(_CRS ,0) { - /* DBGO("\\_SB\\LNKF\\_CRS\n") */ - CreateWordField(IRQB, 0x1, IRQN) - ShiftLeft(1, PIRF, IRQN) - Return(IRQB) - } /* Method(_SB.INTF._CRS) */ - - Method(_SRS, 1) { - /* DBGO("\\_SB\\LNKF\\_CRS\n") */ - CreateWordField(ARG0, 1, IRQM) - - /* Use lowest available IRQ */ - FindSetRightBit(IRQM, Local0) - if (Local0) { - Decrement(Local0) - } - Store(Local0, PIRF) - } /* End Method(_SB.INTF._SRS) */ - } /* End Device(INTF) */ - - Device(INTG) { - Name(_HID, EISAID("PNP0C0F")) - Name(_UID, 7) - - Method(_STA, 0) { - if (PIRG) { - Return(0x0B) /* sata is invisible */ - } else { - Return(0x09) /* sata is disabled */ - } - } /* End Method(_SB.INTG._STA) */ - - Method(_DIS ,0) { - /* DBGO("\\_SB\\LNKG\\_DIS\n") */ - Store(0, PIRG) - } /* End Method(_SB.INTG._DIS) */ - - Method(_PRS ,0) { - /* DBGO("\\_SB\\LNKG\\_PRS\n") */ - Return(IRQP) - } /* Method(_SB.INTG._CRS) */ - - Method(_CRS ,0) { - /* DBGO("\\_SB\\LNKG\\_CRS\n") */ - CreateWordField(IRQB, 0x1, IRQN) - ShiftLeft(1, PIRG, IRQN) - Return(IRQB) - } /* Method(_SB.INTG._CRS) */ - - Method(_SRS, 1) { - /* DBGO("\\_SB\\LNKG\\_CRS\n") */ - CreateWordField(ARG0, 1, IRQM) - - /* Use lowest available IRQ */ - FindSetRightBit(IRQM, Local0) - if (Local0) { - Decrement(Local0) - } - Store(Local0, PIRG) - } /* End Method(_SB.INTG._SRS) */ - } /* End Device(INTG) */ - - Device(INTH) { - Name(_HID, EISAID("PNP0C0F")) - Name(_UID, 8) - - Method(_STA, 0) { - if (PIRH) { - Return(0x0B) /* sata is invisible */ - } else { - Return(0x09) /* sata is disabled */ - } - } /* End Method(_SB.INTH._STA) */ - - Method(_DIS ,0) { - /* DBGO("\\_SB\\LNKH\\_DIS\n") */ - Store(0, PIRH) - } /* End Method(_SB.INTH._DIS) */ - - Method(_PRS ,0) { - /* DBGO("\\_SB\\LNKH\\_PRS\n") */ - Return(IRQP) - } /* Method(_SB.INTH._CRS) */ - - Method(_CRS ,0) { - /* DBGO("\\_SB\\LNKH\\_CRS\n") */ - CreateWordField(IRQB, 0x1, IRQN) - ShiftLeft(1, PIRH, IRQN) - Return(IRQB) - } /* Method(_SB.INTH._CRS) */ - - Method(_SRS, 1) { - /* DBGO("\\_SB\\LNKH\\_CRS\n") */ - CreateWordField(ARG0, 1, IRQM) - - /* Use lowest available IRQ */ - FindSetRightBit(IRQM, Local0) - if (Local0) { - Decrement(Local0) - } - Store(Local0, PIRH) - } /* End Method(_SB.INTH._SRS) */ - } /* End Device(INTH) */ - - } /* End Scope(_SB) */ - - #include - - /* Wake status package */ - Name(WKST,Package(){Zero, Zero}) - - /* - * \_PTS - Prepare to Sleep method - * - * Entry: - * Arg0=The value of the sleeping state S1=1, S2=2, etc - * - * Exit: - * -none- - * - * The _PTS control method is executed at the beginning of the sleep process - * for S1-S5. The sleeping value is passed to the _PTS control method. This - * control method may be executed a relatively long time before entering the - * sleep state and the OS may abort the operation without notification to - * the ACPI driver. This method cannot modify the configuration or power - * state of any device in the system. - */ - Method(\_PTS, 1) { - /* DBGO("\\_PTS\n") */ - /* DBGO("From S0 to S") */ - /* DBGO(Arg0) */ - /* DBGO("\n") */ - - /* Don't allow PCIRST# to reset USB */ - if (LEqual(Arg0,3)){ - Store(0,URRE) - } - - /* Clear sleep SMI status flag and enable sleep SMI trap. */ - /*Store(One, CSSM) - Store(One, SSEN)*/ - - /* On older chips, clear PciExpWakeDisEn */ - /*if (LLessEqual(\_SB.SBRI, 0x13)) { - * Store(0,\_SB.PWDE) - *} - */ - - /* Clear wake status structure. */ - Store(0, Index(WKST,0)) - Store(0, Index(WKST,1)) - } /* End Method(\_PTS) */ - - /* - * The following method results in a "not a valid reserved NameSeg" - * warning so I have commented it out for the duration. It isn't - * used, so it could be removed. - * - * - * \_GTS OEM Going To Sleep method - * - * Entry: - * Arg0=The value of the sleeping state S1=1, S2=2 - * - * Exit: - * -none- - * - * Method(\_GTS, 1) { - * DBGO("\\_GTS\n") - * DBGO("From S0 to S") - * DBGO(Arg0) - * DBGO("\n") - * } - */ - - /* - * \_BFS OEM Back From Sleep method - * - * Entry: - * Arg0=The value of the sleeping state S1=1, S2=2 - * - * Exit: - * -none- - */ - Method(\_BFS, 1) { - /* DBGO("\\_BFS\n") */ - /* DBGO("From S") */ - /* DBGO(Arg0) */ - /* DBGO(" to S0\n") */ - } - - /* - * \_WAK System Wake method - * - * Entry: - * Arg0=The value of the sleeping state S1=1, S2=2 - * - * Exit: - * Return package of 2 DWords - * Dword 1 - Status - * 0x00000000 wake succeeded - * 0x00000001 Wake was signaled but failed due to lack of power - * 0x00000002 Wake was signaled but failed due to thermal condition - * Dword 2 - Power Supply state - * if non-zero the effective S-state the power supply entered - */ - Method(\_WAK, 1) { - /* DBGO("\\_WAK\n") */ - /* DBGO("From S") */ - /* DBGO(Arg0) */ - /* DBGO(" to S0\n") */ - - /* Re-enable HPET */ - Store(1,HPDE) - - /* Restore PCIRST# so it resets USB */ - if (LEqual(Arg0,3)){ - Store(1,URRE) - } - - /* Arbitrarily clear PciExpWakeStatus */ - Store(PWST, Local1) - Store(Local1, PWST) - - /* if (DeRefOf(Index(WKST,0))) { - * Store(0, Index(WKST,1)) - * } else { - * Store(Arg0, Index(WKST,1)) - * } - */ - Return(WKST) - } /* End Method(\_WAK) */ - - Scope(\_GPE) { /* Start Scope GPE */ - /* General event 0 */ - /* Method(_L00) { - * DBGO("\\_GPE\\_L00\n") - * } - */ - - /* General event 1 */ - /* Method(_L01) { - * DBGO("\\_GPE\\_L00\n") - * } - */ - - /* General event 2 */ - /* Method(_L02) { - * DBGO("\\_GPE\\_L00\n") - * } - */ - - /* General event 3 */ - Method(_L03) { - /* DBGO("\\_GPE\\_L00\n") */ - Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ - } - - /* General event 4 */ - /* Method(_L04) { - * DBGO("\\_GPE\\_L00\n") - * } - */ - - /* General event 5 */ - /* Method(_L05) { - * DBGO("\\_GPE\\_L00\n") - * } - */ - - /* General event 6 - Used for GPM6, moved to USB.asl */ - /* Method(_L06) { - * DBGO("\\_GPE\\_L00\n") - * } - */ - - /* General event 7 - Used for GPM7, moved to USB.asl */ - /* Method(_L07) { - * DBGO("\\_GPE\\_L07\n") - * } - */ - - /* Legacy PM event */ - Method(_L08) { - /* DBGO("\\_GPE\\_L08\n") */ - } - - /* Temp warning (TWarn) event */ - Method(_L09) { - /* DBGO("\\_GPE\\_L09\n") */ - /* Notify (\_TZ.TZ00, 0x80) */ - } - - /* Reserved */ - /* Method(_L0A) { - * DBGO("\\_GPE\\_L0A\n") - * } - */ - - /* USB controller PME# */ - Method(_L0B) { - /* DBGO("\\_GPE\\_L0B\n") */ - Notify(\_SB.PCI0.UOH1, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(\_SB.PCI0.UOH2, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(\_SB.PCI0.UOH3, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(\_SB.PCI0.UOH4, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(\_SB.PCI0.UOH5, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(\_SB.PCI0.UOH6, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(\_SB.PCI0.UEH1, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ - } - - /* AC97 controller PME# */ - /* Method(_L0C) { - * DBGO("\\_GPE\\_L0C\n") - * } - */ - - /* OtherTherm PME# */ - /* Method(_L0D) { - * DBGO("\\_GPE\\_L0D\n") - * } - */ - - /* GPM9 SCI event - Moved to USB.asl */ - /* Method(_L0E) { - * DBGO("\\_GPE\\_L0E\n") - * } - */ - - /* PCIe HotPlug event */ - /* Method(_L0F) { - * DBGO("\\_GPE\\_L0F\n") - * } - */ - - /* ExtEvent0 SCI event */ - Method(_L10) { - /* DBGO("\\_GPE\\_L10\n") */ - } - - - /* ExtEvent1 SCI event */ - Method(_L11) { - /* DBGO("\\_GPE\\_L11\n") */ - } - - /* PCIe PME# event */ - /* Method(_L12) { - * DBGO("\\_GPE\\_L12\n") - * } - */ - - /* GPM0 SCI event - Moved to USB.asl */ - /* Method(_L13) { - * DBGO("\\_GPE\\_L13\n") - * } - */ - - /* GPM1 SCI event - Moved to USB.asl */ - /* Method(_L14) { - * DBGO("\\_GPE\\_L14\n") - * } - */ - - /* GPM2 SCI event - Moved to USB.asl */ - /* Method(_L15) { - * DBGO("\\_GPE\\_L15\n") - * } - */ - - /* GPM3 SCI event - Moved to USB.asl */ - /* Method(_L16) { - * DBGO("\\_GPE\\_L16\n") - * } - */ - - /* GPM8 SCI event - Moved to USB.asl */ - /* Method(_L17) { - * DBGO("\\_GPE\\_L17\n") - * } - */ - - /* GPIO0 or GEvent8 event */ - Method(_L18) { - /* DBGO("\\_GPE\\_L18\n") */ - Notify(\_SB.PCI0.PBR2, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(\_SB.PCI0.PBR4, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(\_SB.PCI0.PBR5, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(\_SB.PCI0.PBR6, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(\_SB.PCI0.PBR7, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ - } - - /* GPM4 SCI event - Moved to USB.asl */ - /* Method(_L19) { - * DBGO("\\_GPE\\_L19\n") - * } - */ - - /* GPM5 SCI event - Moved to USB.asl */ - /* Method(_L1A) { - * DBGO("\\_GPE\\_L1A\n") - * } - */ - - /* Azalia SCI event */ - Method(_L1B) { - /* DBGO("\\_GPE\\_L1B\n") */ - Notify(\_SB.PCI0.AZHD, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ - } - - /* GPM6 SCI event - Reassigned to _L06 */ - /* Method(_L1C) { - * DBGO("\\_GPE\\_L1C\n") - * } - */ - - /* GPM7 SCI event - Reassigned to _L07 */ - /* Method(_L1D) { - * DBGO("\\_GPE\\_L1D\n") - * } - */ - - /* GPIO2 or GPIO66 SCI event */ - /* Method(_L1E) { - * DBGO("\\_GPE\\_L1E\n") - * } - */ - - /* SATA SCI event - Moved to sata.asl */ - /* Method(_L1F) { - * DBGO("\\_GPE\\_L1F\n") - * } - */ - - } /* End Scope GPE */ - - #include "acpi/usb.asl" - - /* System Bus */ - Scope(\_SB) { /* Start \_SB scope */ - #include /* global utility methods expected within the \_SB scope */ - - /* _SB.PCI0 */ - /* Note: Only need HID on Primary Bus */ - Device(PCI0) { - External (TOM1) - External (TOM2) - Name(_HID, EISAID("PNP0A03")) - Name(_ADR, 0x00180000) /* Dev# = BSP Dev#, Func# = 0 */ - Method(_BBN, 0) { /* Bus number = 0 */ - Return(0) - } - Method(_STA, 0) { - /* DBGO("\\_SB\\PCI0\\_STA\n") */ - Return(0x0B) /* Status is visible */ - } - - Method(_PRT,0) { - If(PMOD){ Return(APR0) } /* APIC mode */ - Return (PR0) /* PIC Mode */ - } /* end _PRT */ - - /* Describe the Northbridge devices */ - Device(AMRT) { - Name(_ADR, 0x00000000) - } /* end AMRT */ - - /* The internal GFX bridge */ - Device(AGPB) { - Name(_ADR, 0x00010000) - Name(_PRW, Package() {0x18, 4}) - Method(_PRT,0) { - Return (APR1) - } - } /* end AGPB */ - - /* The external GFX bridge */ - Device(PBR2) { - Name(_ADR, 0x00020000) - Name(_PRW, Package() {0x18, 4}) - Method(_PRT,0) { - If(PMOD){ Return(APS2) } /* APIC mode */ - Return (PS2) /* PIC Mode */ - } /* end _PRT */ - } /* end PBR2 */ - - /* Dev3 is also an external GFX bridge, not used in Herring */ - - Device(PBR4) { - Name(_ADR, 0x00040000) - Name(_PRW, Package() {0x18, 4}) - Method(_PRT,0) { - If(PMOD){ Return(APS4) } /* APIC mode */ - Return (PS4) /* PIC Mode */ - } /* end _PRT */ - } /* end PBR4 */ - - Device(PBR5) { - Name(_ADR, 0x00050000) - Name(_PRW, Package() {0x18, 4}) - Method(_PRT,0) { - If(PMOD){ Return(APS5) } /* APIC mode */ - Return (PS5) /* PIC Mode */ - } /* end _PRT */ - } /* end PBR5 */ - - Device(PBR6) { - Name(_ADR, 0x00060000) - Name(_PRW, Package() {0x18, 4}) - Method(_PRT,0) { - If(PMOD){ Return(APS6) } /* APIC mode */ - Return (PS6) /* PIC Mode */ - } /* end _PRT */ - } /* end PBR6 */ - - /* The onboard EtherNet chip */ - Device(PBR7) { - Name(_ADR, 0x00070000) - Name(_PRW, Package() {0x18, 4}) - Method(_PRT,0) { - If(PMOD){ Return(APS7) } /* APIC mode */ - Return (PS7) /* PIC Mode */ - } /* end _PRT */ - } /* end PBR7 */ - - /* GPP */ - Device(PBR9) { - Name(_ADR, 0x00090000) - Name(_PRW, Package() {0x18, 4}) - Method(_PRT,0) { - If(PMOD){ Return(APS9) } /* APIC mode */ - Return (PS9) /* PIC Mode */ - } /* end _PRT */ - } /* end PBR9 */ - - Device(PBRa) { - Name(_ADR, 0x000A0000) - Name(_PRW, Package() {0x18, 4}) - Method(_PRT,0) { - If(PMOD){ Return(APSa) } /* APIC mode */ - Return (PSa) /* PIC Mode */ - } /* end _PRT */ - } /* end PBRa */ - - Device(PE20) { - Name(_ADR, 0x00150000) - Name(_PRW, Package() {0x18, 4}) - Method(_PRT,0) { - If(PMOD){ Return(APE0) } /* APIC mode */ - Return (PE0) /* PIC Mode */ - } /* end _PRT */ - } /* end PE20 */ - Device(PE21) { - Name(_ADR, 0x00150001) - Name(_PRW, Package() {0x18, 4}) - Method(_PRT,0) { - If(PMOD){ Return(APE1) } /* APIC mode */ - Return (PE1) /* PIC Mode */ - } /* end _PRT */ - } /* end PE21 */ - Device(PE22) { - Name(_ADR, 0x00150002) - Name(_PRW, Package() {0x18, 4}) - Method(_PRT,0) { - If(PMOD){ Return(APE2) } /* APIC mode */ - Return (APE2) /* PIC Mode */ - } /* end _PRT */ - } /* end PE22 */ - Device(PE23) { - Name(_ADR, 0x00150003) - Name(_PRW, Package() {0x18, 4}) - Method(_PRT,0) { - If(PMOD){ Return(APE3) } /* APIC mode */ - Return (PE3) /* PIC Mode */ - } /* end _PRT */ - } /* end PE23 */ - - /* PCI slot 1, 2, 3 */ - Device(PIBR) { - Name(_ADR, 0x00140004) - Name(_PRW, Package() {0x18, 4}) - - Method(_PRT, 0) { - Return (PCIB) - } - } - - /* Describe the Southbridge devices */ - Device(STCR) { - Name(_ADR, 0x00110000) - #include "acpi/sata.asl" - } /* end STCR */ - - Device(UOH1) { - Name(_ADR, 0x00120000) - Name(_PRW, Package() {0x0B, 3}) - } /* end UOH1 */ - - Device(UOH2) { - Name(_ADR, 0x00120002) - Name(_PRW, Package() {0x0B, 3}) - } /* end UOH2 */ - - Device(UOH3) { - Name(_ADR, 0x00130000) - Name(_PRW, Package() {0x0B, 3}) - } /* end UOH3 */ - - Device(UOH4) { - Name(_ADR, 0x00130002) - Name(_PRW, Package() {0x0B, 3}) - } /* end UOH4 */ - - Device(UOH5) { - Name(_ADR, 0x00160000) - Name(_PRW, Package() {0x0B, 3}) - } /* end UOH5 */ - - Device(UOH6) { - Name(_ADR, 0x00160002) - Name(_PRW, Package() {0x0B, 3}) - } /* end UOH5 */ - - Device(UEH1) { - Name(_ADR, 0x00140005) - Name(_PRW, Package() {0x0B, 3}) - } /* end UEH1 */ - - Device(SBUS) { - Name(_ADR, 0x00140000) - } /* end SBUS */ - - Device(AZHD) { - Name(_ADR, 0x00140002) - OperationRegion(AZPD, PCI_Config, 0x00, 0x100) - Field(AZPD, AnyAcc, NoLock, Preserve) { - offset (0x42), - NSDI, 1, - NSDO, 1, - NSEN, 1, - offset (0x44), - IPCR, 4, - offset (0x54), - PWST, 2, - , 6, - PMEB, 1, - , 6, - PMST, 1, - offset (0x62), - MMCR, 1, - offset (0x64), - MMLA, 32, - offset (0x68), - MMHA, 32, - offset (0x6C), - MMDT, 16, - } - - Method(_INI) { - If(LEqual(OSVR,3)){ /* If we are running Linux */ - Store(zero, NSEN) - Store(one, NSDO) - Store(one, NSDI) - } - } - } /* end AZHD */ - - Device(LIBR) { - Name(_ADR, 0x00140003) - /* Method(_INI) { - * DBGO("\\_SB\\PCI0\\LpcIsaBr\\_INI\n") - } */ /* End Method(_SB.SBRDG._INI) */ - - /* Real Time Clock Device */ - Device(RTC0) { - Name(_HID, EISAID("PNP0B01")) /* AT Real Time Clock */ - Name(_CRS, ResourceTemplate() { - IRQNoFlags(){8} - IO(Decode16,0x0070, 0x0070, 0, 2) - /* IO(Decode16,0x0070, 0x0070, 0, 4) */ - }) - } /* End Device(_SB.PCI0.LpcIsaBr.RTC0) */ - - Device(TMR) { /* Timer */ - Name(_HID,EISAID("PNP0100")) /* System Timer */ - Name(_CRS, ResourceTemplate() { - IRQNoFlags(){0} - IO(Decode16, 0x0040, 0x0040, 0, 4) - /* IO(Decode16, 0x0048, 0x0048, 0, 4) */ - }) - } /* End Device(_SB.PCI0.LpcIsaBr.TMR) */ - - Device(SPKR) { /* Speaker */ - Name(_HID,EISAID("PNP0800")) /* AT style speaker */ - Name(_CRS, ResourceTemplate() { - IO(Decode16, 0x0061, 0x0061, 0, 1) - }) - } /* End Device(_SB.PCI0.LpcIsaBr.SPKR) */ - - Device(PIC) { - Name(_HID,EISAID("PNP0000")) /* AT Interrupt Controller */ - Name(_CRS, ResourceTemplate() { - IRQNoFlags(){2} - IO(Decode16,0x0020, 0x0020, 0, 2) - IO(Decode16,0x00A0, 0x00A0, 0, 2) - /* IO(Decode16, 0x00D0, 0x00D0, 0x10, 0x02) */ - /* IO(Decode16, 0x04D0, 0x04D0, 0x10, 0x02) */ - }) - } /* End Device(_SB.PCI0.LpcIsaBr.PIC) */ - - Device(MAD) { /* 8257 DMA */ - Name(_HID,EISAID("PNP0200")) /* Hardware Device ID */ - Name(_CRS, ResourceTemplate() { - DMA(Compatibility,BusMaster,Transfer8){4} - IO(Decode16, 0x0000, 0x0000, 0x10, 0x10) - IO(Decode16, 0x0081, 0x0081, 0x00, 0x03) - IO(Decode16, 0x0087, 0x0087, 0x00, 0x01) - IO(Decode16, 0x0089, 0x0089, 0x00, 0x03) - IO(Decode16, 0x008F, 0x008F, 0x00, 0x01) - IO(Decode16, 0x00C0, 0x00C0, 0x10, 0x20) - }) /* End Name(_SB.PCI0.LpcIsaBr.MAD._CRS) */ - } /* End Device(_SB.PCI0.LpcIsaBr.MAD) */ - - Device(COPR) { - Name(_HID,EISAID("PNP0C04")) /* Math Coprocessor */ - Name(_CRS, ResourceTemplate() { - IO(Decode16, 0x00F0, 0x00F0, 0, 0x10) - IRQNoFlags(){13} - }) - } /* End Device(_SB.PCI0.LpcIsaBr.COPR) */ -#if 0 - Device(HPTM) { - Name(_HID,EISAID("PNP0103")) - Name(CRS,ResourceTemplate() { - Memory32Fixed(ReadOnly,0xFED00000, 0x00000400, HPT) /* 1kb reserved space */ - }) - Method(_STA, 0) { - Return(0x0F) /* sata is visible */ - } - Method(_CRS, 0) { - CreateDwordField(CRS, ^HPT._BAS, HPBX) - Store(HPBA, HPBX) - Return(CRS) - } - } /* End Device(_SB.PCI0.LpcIsaBr.COPR) */ -#endif - } /* end LIBR */ - - Device(HPBR) { - Name(_ADR, 0x00140004) - } /* end HostPciBr */ - - Device(ACAD) { - Name(_ADR, 0x00140005) - } /* end Ac97audio */ - - Device(ACMD) { - Name(_ADR, 0x00140006) - } /* end Ac97modem */ - - Name(CRES, ResourceTemplate() { - IO(Decode16, 0x0CF8, 0x0CF8, 1, 8) - - WORDIO(ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, - 0x0000, /* address granularity */ - 0x0000, /* range minimum */ - 0x0CF7, /* range maximum */ - 0x0000, /* translation */ - 0x0CF8 /* length */ - ) - - WORDIO(ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, - 0x0000, /* address granularity */ - 0x0D00, /* range minimum */ - 0xFFFF, /* range maximum */ - 0x0000, /* translation */ - 0xF300 /* length */ - ) -#if 0 - Memory32Fixed(READWRITE, 0, 0xA0000, BSMM) - Memory32Fixed(READONLY, 0x000A0000, 0x00020000, VGAM) /* VGA memory space */ - Memory32Fixed(READONLY, 0x000C0000, 0x00020000, EMM1) /* Assume C0000-E0000 empty */ - Memory32Fixed(READONLY, 0x000E0000, 0x00020000, RDBS) /* BIOS ROM area */ - - /* DRAM Memory from 1MB to TopMem */ - Memory32Fixed(READWRITE, 0x00100000, 0, DMLO) /* 1MB to TopMem */ - - /* BIOS space just below 4GB */ - DWORDMemory( - ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite, - 0x00, /* Granularity */ - 0x00000000, /* Min */ - 0x00000000, /* Max */ - 0x00000000, /* Translation */ - 0x00000000, /* Max-Min, RLEN */ - ,, - PCBM - ) - - /* DRAM memory from 4GB to TopMem2 */ - QWORDMemory(ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite, - 0xFFFFFFFF, /* Granularity */ - 0x00000000, /* Min */ - 0x00000000, /* Max */ - 0x00000000, /* Translation */ - 0x00000000, /* Max-Min, RLEN */ - ,, - DMHI - ) - - /* BIOS space just below 16EB */ - QWORDMemory(ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite, - 0xFFFFFFFF, /* Granularity */ - 0x00000000, /* Min */ - 0x00000000, /* Max */ - 0x00000000, /* Translation */ - 0x00000000, /* Max-Min, RLEN */ - ,, - PEBM - ) -#endif - /* memory space for PCI BARs below 4GB */ - Memory32Fixed(ReadOnly, 0x00000000, 0x00000000, MMIO) - }) /* End Name(_SB.PCI0.CRES) */ - - Method(_CRS, 0) { - /* DBGO("\\_SB\\PCI0\\_CRS\n") */ -#if 0 - CreateDWordField(CRES, ^EMM1._BAS, EM1B) - CreateDWordField(CRES, ^EMM1._LEN, EM1L) - CreateDWordField(CRES, ^DMLO._BAS, DMLB) - CreateDWordField(CRES, ^DMLO._LEN, DMLL) - CreateDWordField(CRES, ^PCBM._MIN, PBMB) - CreateDWordField(CRES, ^PCBM._LEN, PBML) - - CreateQWordField(CRES, ^DMHI._MIN, DMHB) - CreateQWordField(CRES, ^DMHI._LEN, DMHL) - CreateQWordField(CRES, ^PEBM._MIN, EBMB) - CreateQWordField(CRES, ^PEBM._LEN, EBML) - - If(LGreater(LOMH, 0xC0000)){ - Store(0xC0000, EM1B) /* Hole above C0000 and below E0000 */ - Subtract(LOMH, 0xC0000, EM1L) /* subtract start, assumes allocation from C0000 going up */ - } - - /* Set size of memory from 1MB to TopMem */ - Subtract(TOM1, 0x100000, DMLL) - - /* - * If(LNotEqual(TOM2, 0x00000000)){ - * Store(0x100000000,DMHB) DRAM from 4GB to TopMem2 - * Subtract(TOM2, 0x100000000, DMHL) - * } - */ - - /* If there is no memory above 4GB, put the BIOS just below 4GB */ - If(LEqual(TOM2, 0x00000000)){ - Store(PBAD,PBMB) /* Reserve the "BIOS" space */ - Store(PBLN,PBML) - } - Else { /* Otherwise, put the BIOS just below 16EB */ - ShiftLeft(PBAD,16,EBMB) /* Reserve the "BIOS" space */ - Store(PBLN,EBML) - } -#endif - CreateDWordField(CRES, ^MMIO._BAS, MM1B) - CreateDWordField(CRES, ^MMIO._LEN, MM1L) - /* - * Declare memory between TOM1 and 4GB as available - * for PCI MMIO. - * Use ShiftLeft to avoid 64bit constant (for XP). - * This will work even if the OS does 32bit arithmetic, as - * 32bit (0x00000000 - TOM1) will wrap and give the same - * result as 64bit (0x100000000 - TOM1). - */ - Store(TOM1, MM1B) - ShiftLeft(0x10000000, 4, Local0) - Subtract(Local0, TOM1, Local0) - Store(Local0, MM1L) - - Return(CRES) /* note to change the Name buffer */ - } /* end of Method(_SB.PCI0._CRS) */ - - /* - * - * FIRST METHOD CALLED UPON BOOT - * - * 1. If debugging, print current OS and ACPI interpreter. - * 2. Get PCI Interrupt routing from ACPI VSM, this - * value is based on user choice in BIOS setup. - */ - Method(_INI, 0) { - /* DBGO("\\_SB\\_INI\n") */ - /* DBGO(" DSDT.ASL code from ") */ - /* DBGO(__DATE__) */ - /* DBGO(" ") */ - /* DBGO(__TIME__) */ - /* DBGO("\n Sleep states supported: ") */ - /* DBGO("\n") */ - /* DBGO(" \\_OS=") */ - /* DBGO(\_OS) */ - /* DBGO("\n \\_REV=") */ - /* DBGO(\_REV) */ - /* DBGO("\n") */ - - /* Determine the OS we're running on */ - OSFL() - - /* On older chips, clear PciExpWakeDisEn */ - /*if (LLessEqual(\SBRI, 0x13)) { - * Store(0,\PWDE) - * } - */ - } /* End Method(_SB._INI) */ - } /* End Device(PCI0) */ - - Device(PWRB) { /* Start Power button device */ - Name(_HID, EISAID("PNP0C0C")) - Name(_UID, 0xAA) - Name(_PRW, Package () {3, 0x04}) /* wake from S1-S4 */ - Name(_STA, 0x0B) /* sata is invisible */ - } - } /* End \_SB scope */ - - Scope(\_SI) { - Method(_SST, 1) { - /* DBGO("\\_SI\\_SST\n") */ - /* DBGO(" New Indicator state: ") */ - /* DBGO(Arg0) */ - /* DBGO("\n") */ - } - } /* End Scope SI */ -} -/* End of ASL file */ diff --git a/src/mainboard/advansus/a785e-i/get_bus_conf.c b/src/mainboard/advansus/a785e-i/get_bus_conf.c deleted file mode 100644 index 6b5ae68bc6..0000000000 --- a/src/mainboard/advansus/a785e-i/get_bus_conf.c +++ /dev/null @@ -1,44 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include -#include -#include - -/* Global variables for MB layouts and these will be shared by irqtable mptable -* and acpi_tables busnum is default. -*/ -u32 apicid_sb800; - -void get_bus_conf(void) -{ - u32 apicid_base; - - get_default_pci1234(1); - - sysconf.sbdn = (sysconf.hcdn[0] & 0xff); - - - pirq_router_bus = (sysconf.pci1234[0] >> 16) & 0xff; - - /* I/O APICs: APIC ID Version State Address */ - if (CONFIG(LOGICAL_CPUS)) - apicid_base = get_apicid_base(1); - else - apicid_base = CONFIG_MAX_PHYSICAL_CPUS; - apicid_sb800 = apicid_base + 0; -} diff --git a/src/mainboard/advansus/a785e-i/irq_tables.c b/src/mainboard/advansus/a785e-i/irq_tables.c deleted file mode 100644 index a453c766bd..0000000000 --- a/src/mainboard/advansus/a785e-i/irq_tables.c +++ /dev/null @@ -1,101 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include -#include -#include -#include - -static void write_pirq_info(struct irq_info *pirq_info, u8 bus, u8 devfn, - u8 link0, u16 bitmap0, u8 link1, u16 bitmap1, - u8 link2, u16 bitmap2, u8 link3, u16 bitmap3, - u8 slot, u8 rfu) -{ - pirq_info->bus = bus; - pirq_info->devfn = devfn; - pirq_info->irq[0].link = link0; - pirq_info->irq[0].bitmap = bitmap0; - pirq_info->irq[1].link = link1; - pirq_info->irq[1].bitmap = bitmap1; - pirq_info->irq[2].link = link2; - pirq_info->irq[2].bitmap = bitmap2; - pirq_info->irq[3].link = link3; - pirq_info->irq[3].bitmap = bitmap3; - pirq_info->slot = slot; - pirq_info->rfu = rfu; -} - - -unsigned long write_pirq_routing_table(unsigned long addr) -{ - struct irq_routing_table *pirq; - struct irq_info *pirq_info; - u32 slot_num; - u8 *v; - - u8 sum = 0; - int i; - - /* Align the table to be 16 byte aligned. */ - addr += 15; - addr &= ~15; - - /* This table must be between 0xf0000 & 0x100000 */ - printk(BIOS_INFO, "Writing IRQ routing tables to 0x%lx...", addr); - - pirq = (void *)(addr); - v = (u8 *) (addr); - - pirq->signature = PIRQ_SIGNATURE; - pirq->version = PIRQ_VERSION; - - pirq->rtr_bus = pirq_router_bus; - pirq->rtr_devfn = PCI_DEVFN(0x14, 4); - - pirq->exclusive_irqs = 0; - - pirq->rtr_vendor = 0x1002; - pirq->rtr_device = 0x4384; - - pirq->miniport_data = 0; - - memset(pirq->rfu, 0, sizeof(pirq->rfu)); - - pirq_info = (void *)(&pirq->checksum + 1); - slot_num = 0; - - /* pci bridge */ - write_pirq_info(pirq_info, pirq_router_bus, PCI_DEVFN(0x14, 4), - 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, - 0); - pirq_info++; - slot_num++; - - pirq->size = 32 + 16 * slot_num; - - for (i = 0; i < pirq->size; i++) - sum += v[i]; - - sum = pirq->checksum - sum; - if (sum != pirq->checksum) { - pirq->checksum = sum; - } - - printk(BIOS_INFO, "write_pirq_routing_table done.\n"); - - return (unsigned long)pirq_info; -} diff --git a/src/mainboard/advansus/a785e-i/mainboard.c b/src/mainboard/advansus/a785e-i/mainboard.c deleted file mode 100644 index d6372aaa7f..0000000000 --- a/src/mainboard/advansus/a785e-i/mainboard.c +++ /dev/null @@ -1,64 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include -#include -#include -#include -#include -#include - -/* GPIO6. */ -static void enable_int_gfx(void) -{ - volatile u8 *gpio_reg; - - /* make sure the Acpi MMIO(fed80000) is accessible */ - // XXX Redo this RWPMIO(SB_PMIOA_REG24, AccWidthUint8, ~(BIT0), BIT0); - - gpio_reg = (volatile u8 *)AMD_SB_ACPI_MMIO_ADDR + 0xD00; /* IoMux Register */ - - *(gpio_reg + 0x6) = 0x1; /* Int_vga_en */ - *(gpio_reg + 170) = 0x1; /* gpio_gate */ - - gpio_reg = (volatile u8 *)AMD_SB_ACPI_MMIO_ADDR + 0x100; /* GPIO Registers */ - - *(gpio_reg + 0x6) = 0x8; - *(gpio_reg + 170) = 0x0; -} - -int is_dev3_present(void) -{ - return 0; -} - - -/************************************************* -* enable the dedicated function in A785E-I board. -* This function called early than rs780_enable. -*************************************************/ -static void mainboard_enable(struct device *dev) -{ - printk(BIOS_INFO, "Mainboard A785E-I Enable. dev=0x%p\n", dev); - - set_pcie_dereset(); - enable_int_gfx(); -} - -struct chip_operations mainboard_ops = { - .enable_dev = mainboard_enable, -}; diff --git a/src/mainboard/advansus/a785e-i/mptable.c b/src/mainboard/advansus/a785e-i/mptable.c deleted file mode 100644 index cc66ce8266..0000000000 --- a/src/mainboard/advansus/a785e-i/mptable.c +++ /dev/null @@ -1,79 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include -#include -#include - -extern u32 apicid_sb800; - -u8 intr_data[] = { - [0x00] = 0x10,0x11,0x12,0x13,0x14,0x15,0x16,0x17, /* INTA# - INTH# */ - [0x08] = 0x00,0x00,0x00,0x00,0x1F,0x1F,0x1F,0x1F, /* Misc-nil,0,1,2, INT from Serial irq */ - [0x10] = 0x1F,0x1F,0x1F,0x10,0x1F,0x12,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, - 0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, - 0x12,0x11,0x12,0x11,0x12,0x11,0x12,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, - 0x11,0x13,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, - 0x10,0x11,0x12,0x13 -}; - -static void *smp_write_config_table(void *v) -{ - struct mp_config_table *mc; - int bus_isa; - u32 dword = 0; - u8 byte; - - mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); - - mptable_init(mc, LOCAL_APIC_ADDR); - - smp_write_processors(mc); - - mptable_write_buses(mc, NULL, &bus_isa); - - /* I/O APICs: APIC ID Version State Address */ - // XXX Redo this: ReadPMIO(SB_PMIOA_REG34, AccWidthUint32, &dword); - dword &= 0xFFFFFFF0; - smp_write_ioapic(mc, apicid_sb800, 0x11,(void *) dword); - - for (byte = 0x0; byte < sizeof(intr_data); byte ++) { - outb(byte | 0x80, 0xC00); - outb(intr_data[byte], 0xC01); - } - - /* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ -#define IO_LOCAL_INT(type, intr, apicid, pin) \ - smp_write_intsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin)); - - mptable_add_isa_interrupts(mc, bus_isa, apicid_sb800, 0); - - /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ - IO_LOCAL_INT(mp_ExtINT, 0x0, MP_APIC_ALL, 0x0); - IO_LOCAL_INT(mp_NMI, 0x0, MP_APIC_ALL, 0x1); - /* There is no extension information... */ - - /* Compute the checksums */ - return mptable_finalize(mc); -} - -unsigned long write_smp_table(unsigned long addr) -{ - void *v; - v = smp_write_floating_table(addr, 0); - return (unsigned long)smp_write_config_table(v); -} diff --git a/src/mainboard/advansus/a785e-i/platform_cfg.h b/src/mainboard/advansus/a785e-i/platform_cfg.h deleted file mode 100644 index 3f31f9f19c..0000000000 --- a/src/mainboard/advansus/a785e-i/platform_cfg.h +++ /dev/null @@ -1,215 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef _PLATFORM_CFG_H_ -#define _PLATFORM_CFG_H_ - -/** - * @def BIOS_SIZE - * BIOS_SIZE_{1,2,4,8,16}M - * - * In SB800, default ROM size is 1M Bytes, if your platform ROM - * bigger than 1M you have to set the ROM size outside CIMx module and - * before AGESA module get call. - */ -#ifndef BIOS_SIZE -#define BIOS_SIZE ((CONFIG_COREBOOT_ROMSIZE_KB >> 10) - 1) -#endif /* BIOS_SIZE */ - -/** - * @def SPREAD_SPECTRUM - * @brief - * 0 - Disable Spread Spectrum function - * 1 - Enable Spread Spectrum function - */ -#define SPREAD_SPECTRUM 0 - -/** - * @def SB_HPET_TIMER - * @brief - * 0 - Disable hpet - * 1 - Enable hpet - */ -#define HPET_TIMER 1 - -/** - * @def USB_CONFIG - * @brief bit[0-6] used to control USB - * 0 - Disable - * 1 - Enable - * Usb Ohci1 Controller (Bus 0 Dev 18 Func0) is define at BIT0 - * Usb Ehci1 Controller (Bus 0 Dev 18 Func2) is define at BIT1 - * Usb Ohci2 Controller (Bus 0 Dev 19 Func0) is define at BIT2 - * Usb Ehci2 Controller (Bus 0 Dev 19 Func2) is define at BIT3 - * Usb Ohci3 Controller (Bus 0 Dev 22 Func0) is define at BIT4 - * Usb Ehci3 Controller (Bus 0 Dev 22 Func2) is define at BIT5 - * Usb Ohci4 Controller (Bus 0 Dev 20 Func5) is define at BIT6 - */ -#define USB_CONFIG 0x7F - -/** - * @def PCI_CLOCK_CTRL - * @brief bit[0-4] used for PCI Slots Clock Control, - * 0 - disable - * 1 - enable - * PCI SLOT 0 define at BIT0 - * PCI SLOT 1 define at BIT1 - * PCI SLOT 2 define at BIT2 - * PCI SLOT 3 define at BIT3 - * PCI SLOT 4 define at BIT4 - */ -#define PCI_CLOCK_CTRL 0x1F - -/** - * @def SATA_CONTROLLER - * @brief INCHIP Sata Controller - */ -#define SATA_CONTROLLER CIMX_OPTION_ENABLED - -/** - * @def SATA_MODE - * @brief INCHIP Sata Controller Mode - * NOTE: DO NOT ALLOW SATA & IDE use same mode - */ -#define SATA_MODE CONFIG_SB800_SATA_MODE - -/** - * @brief INCHIP Sata IDE Controller Mode - */ -#define IDE_LEGACY_MODE 0 -#define IDE_NATIVE_MODE 1 - -/** - * @def SATA_IDE_MODE - * @brief INCHIP Sata IDE Controller Mode - * NOTE: DO NOT ALLOW SATA & IDE use same mode - */ -#define SATA_IDE_MODE IDE_LEGACY_MODE - -/** - * @def EXTERNAL_CLOCK - * @brief 00/10: Reference clock from crystal oscillator via - * PAD_XTALI and PAD_XTALO - * - * @def INTERNAL_CLOCK - * @brief 01/11: Reference clock from internal clock through - * CP_PLL_REFCLK_P and CP_PLL_REFCLK_N via RDL - */ -#define EXTERNAL_CLOCK 0x00 -#define INTERNAL_CLOCK 0x01 - -/* NOTE: inagua have to using internal clock, - * otherwise can not detect sata drive - */ -#define SATA_CLOCK_SOURCE INTERNAL_CLOCK - -/** - * @def SATA_PORT_MULT_CAP_RESERVED - * @brief 1 ON, 0 0FF - */ -#define SATA_PORT_MULT_CAP_RESERVED 1 - - -/** - * @def AZALIA_AUTO - * @brief Detect Azalia controller automatically. - * - * @def AZALIA_DISABLE - * @brief Disable Azalia controller. - - * @def AZALIA_ENABLE - * @brief Enable Azalia controller. - */ -#define AZALIA_AUTO 0 -#define AZALIA_DISABLE 1 -#define AZALIA_ENABLE 2 - -/** - * @brief INCHIP HDA controller - */ -#define AZALIA_CONTROLLER AZALIA_AUTO - -/** - * @def AZALIA_PIN_CONFIG - * @brief - * 0 - disable - * 1 - enable - */ -#define AZALIA_PIN_CONFIG 1 - -/** - * @def AZALIA_SDIN_PIN - * @brief - * SDIN0 is define at BIT0 & BIT1 - * 00 - GPIO PIN - * 01 - Reserved - * 10 - As a Azalia SDIN pin - * SDIN1 is define at BIT2 & BIT3 - * SDIN2 is define at BIT4 & BIT5 - * SDIN3 is define at BIT6 & BIT7 - */ -#define AZALIA_SDIN_PIN 0x2A - -/** - * @def GPP_CONTROLLER - */ -#define GPP_CONTROLLER CIMX_OPTION_ENABLED - -/** - * @def GPP_CFGMODE - * @brief GPP Link Configuration - * four possible configuration: - * GPP_CFGMODE_X4000 - * GPP_CFGMODE_X2200 - * GPP_CFGMODE_X2110 - * GPP_CFGMODE_X1111 - */ -#define GPP_CFGMODE GPP_CFGMODE_X1111 - -/** - * @def NB_SB_GEN2 - * 0 - Disable - * 1 - Enable - */ -#define NB_SB_GEN2 TRUE - -/** - * @def SB_GPP_GEN2 - * 0 - Disable - * 1 - Enable - */ -#define SB_GPP_GEN2 TRUE - -/** - * @def SB_GPP_UNHIDE_PORTS - * TRUE - ports visible always, even port empty - * FALSE - ports invisible if port empty - */ -#define SB_GPP_UNHIDE_PORTS FALSE - -/** - * @def GEC_CONFIG - * 0 - Enable - * 1 - Disable - */ -#define GEC_CONFIG 0 - -/** - * @def SIO_HWM_BASE_ADDRESS - * Super IO HWM base address - */ -#define SIO_HWM_BASE_ADDRESS 0x290 - -#endif diff --git a/src/mainboard/advansus/a785e-i/resourcemap.c b/src/mainboard/advansus/a785e-i/resourcemap.c deleted file mode 100644 index b46866add5..0000000000 --- a/src/mainboard/advansus/a785e-i/resourcemap.c +++ /dev/null @@ -1,273 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include - -void setup_mb_resource_map(void) -{ - static const unsigned int register_values[] = { - /* Careful set limit registers before base registers which contain the enables */ - /* DRAM Limit i Registers - * F1:0x44 i = 0 - * F1:0x4C i = 1 - * F1:0x54 i = 2 - * F1:0x5C i = 3 - * F1:0x64 i = 4 - * F1:0x6C i = 5 - * F1:0x74 i = 6 - * F1:0x7C i = 7 - * [ 2: 0] Destination Node ID - * 000 = Node 0 - * 001 = Node 1 - * 010 = Node 2 - * 011 = Node 3 - * 100 = Node 4 - * 101 = Node 5 - * 110 = Node 6 - * 111 = Node 7 - * [ 7: 3] Reserved - * [10: 8] Interleave select - * specifies the values of A[14:12] to use with interleave enable. - * [15:11] Reserved - * [31:16] DRAM Limit Address i Bits 39-24 - * This field defines the upper address bits of a 40 bit address - * that define the end of the DRAM region. - */ - /* Don't touch it, we need it for CONFIG_CAR_FAM10 */ - ADDRMAP_REG(0x4C), 0x0000f8f8, 0x00000001, - ADDRMAP_REG(0x54), 0x0000f8f8, 0x00000002, - ADDRMAP_REG(0x5C), 0x0000f8f8, 0x00000003, - ADDRMAP_REG(0x64), 0x0000f8f8, 0x00000004, - ADDRMAP_REG(0x6C), 0x0000f8f8, 0x00000005, - ADDRMAP_REG(0x74), 0x0000f8f8, 0x00000006, - ADDRMAP_REG(0x7C), 0x0000f8f8, 0x00000007, - /* DRAM Base i Registers - * F1:0x40 i = 0 - * F1:0x48 i = 1 - * F1:0x50 i = 2 - * F1:0x58 i = 3 - * F1:0x60 i = 4 - * F1:0x68 i = 5 - * F1:0x70 i = 6 - * F1:0x78 i = 7 - * [ 0: 0] Read Enable - * 0 = Reads Disabled - * 1 = Reads Enabled - * [ 1: 1] Write Enable - * 0 = Writes Disabled - * 1 = Writes Enabled - * [ 7: 2] Reserved - * [10: 8] Interleave Enable - * 000 = No interleave - * 001 = Interleave on A[12] (2 nodes) - * 010 = reserved - * 011 = Interleave on A[12] and A[14] (4 nodes) - * 100 = reserved - * 101 = reserved - * 110 = reserved - * 111 = Interleve on A[12] and A[13] and A[14] (8 nodes) - * [15:11] Reserved - * [13:16] DRAM Base Address i Bits 39-24 - * This field defines the upper address bits of a 40-bit address - * that define the start of the DRAM region. - */ - /* don't touch it, we need it for CONFIG_CAR_FAM10 */ - ADDRMAP_REG(0x48), 0x0000f8fc, 0x00000000, - ADDRMAP_REG(0x50), 0x0000f8fc, 0x00000000, - ADDRMAP_REG(0x58), 0x0000f8fc, 0x00000000, - ADDRMAP_REG(0x60), 0x0000f8fc, 0x00000000, - ADDRMAP_REG(0x68), 0x0000f8fc, 0x00000000, - ADDRMAP_REG(0x70), 0x0000f8fc, 0x00000000, - ADDRMAP_REG(0x78), 0x0000f8fc, 0x00000000, - - /* Memory-Mapped I/O Limit i Registers - * F1:0x84 i = 0 - * F1:0x8C i = 1 - * F1:0x94 i = 2 - * F1:0x9C i = 3 - * F1:0xA4 i = 4 - * F1:0xAC i = 5 - * F1:0xB4 i = 6 - * F1:0xBC i = 7 - * [ 2: 0] Destination Node ID - * 000 = Node 0 - * 001 = Node 1 - * 010 = Node 2 - * 011 = Node 3 - * 100 = Node 4 - * 101 = Node 5 - * 110 = Node 6 - * 111 = Node 7 - * [ 3: 3] Reserved - * [ 5: 4] Destination Link ID - * 00 = Link 0 - * 01 = Link 1 - * 10 = Link 2 - * 11 = Reserved - * [ 6: 6] Reserved - * [ 7: 7] Non-Posted - * 0 = CPU writes may be posted - * 1 = CPU writes must be non-posted - * [31: 8] Memory-Mapped I/O Limit Address i (39-16) - * This field defines the upp address bits of a 40-bit address that - * defines the end of a memory-mapped I/O region n - */ - ADDRMAP_REG(0x84), 0x00000048, 0x00000000, - ADDRMAP_REG(0x8C), 0x00000048, 0x00000000, - ADDRMAP_REG(0x94), 0x00000048, 0x00000000, - ADDRMAP_REG(0x9C), 0x00000048, 0x00000000, - ADDRMAP_REG(0xA4), 0x00000048, 0x00000000, - ADDRMAP_REG(0xAC), 0x00000048, 0x00000000, - ADDRMAP_REG(0xB4), 0x00000048, 0x00000000, - - /* Memory-Mapped I/O Base i Registers - * F1:0x80 i = 0 - * F1:0x88 i = 1 - * F1:0x90 i = 2 - * F1:0x98 i = 3 - * F1:0xA0 i = 4 - * F1:0xA8 i = 5 - * F1:0xB0 i = 6 - * F1:0xB8 i = 7 - * [ 0: 0] Read Enable - * 0 = Reads disabled - * 1 = Reads Enabled - * [ 1: 1] Write Enable - * 0 = Writes disabled - * 1 = Writes Enabled - * [ 2: 2] Cpu Disable - * 0 = Cpu can use this I/O range - * 1 = Cpu requests do not use this I/O range - * [ 3: 3] Lock - * 0 = base/limit registers i are read/write - * 1 = base/limit registers i are read-only - * [ 7: 4] Reserved - * [31: 8] Memory-Mapped I/O Base Address i (39-16) - * This field defines the upper address bits of a 40bit address - * that defines the start of memory-mapped I/O region i - */ - ADDRMAP_REG(0x80), 0x000000f0, 0x00000000, - ADDRMAP_REG(0x88), 0x000000f0, 0x00000000, - ADDRMAP_REG(0x90), 0x000000f0, 0x00000000, - ADDRMAP_REG(0x98), 0x000000f0, 0x00000000, - ADDRMAP_REG(0xA0), 0x000000f0, 0x00000000, - ADDRMAP_REG(0xA8), 0x000000f0, 0x00000000, - ADDRMAP_REG(0xB0), 0x000000f0, 0x00000000, - - /* PCI I/O Limit i Registers - * F1:0xC4 i = 0 - * F1:0xCC i = 1 - * F1:0xD4 i = 2 - * F1:0xDC i = 3 - * [ 2: 0] Destination Node ID - * 000 = Node 0 - * 001 = Node 1 - * 010 = Node 2 - * 011 = Node 3 - * 100 = Node 4 - * 101 = Node 5 - * 110 = Node 6 - * 111 = Node 7 - * [ 3: 3] Reserved - * [ 5: 4] Destination Link ID - * 00 = Link 0 - * 01 = Link 1 - * 10 = Link 2 - * 11 = reserved - * [11: 6] Reserved - * [24:12] PCI I/O Limit Address i - * This field defines the end of PCI I/O region n - * [31:25] Reserved - */ - ADDRMAP_REG(0xCC), 0xFE000FC8, 0x00000000, - ADDRMAP_REG(0xD4), 0xFE000FC8, 0x00000000, - ADDRMAP_REG(0xDC), 0xFE000FC8, 0x00000000, - - /* PCI I/O Base i Registers - * F1:0xC0 i = 0 - * F1:0xC8 i = 1 - * F1:0xD0 i = 2 - * F1:0xD8 i = 3 - * [ 0: 0] Read Enable - * 0 = Reads Disabled - * 1 = Reads Enabled - * [ 1: 1] Write Enable - * 0 = Writes Disabled - * 1 = Writes Enabled - * [ 3: 2] Reserved - * [ 4: 4] VGA Enable - * 0 = VGA matches Disabled - * 1 = matches all address < 64K and where A[9:0] is in the - * range 3B0-3BB or 3C0-3DF independen of the base & limit registers - * [ 5: 5] ISA Enable - * 0 = ISA matches Disabled - * 1 = Blocks address < 64K and in the last 768 bytes of eack 1K block - * from matching agains this base/limit pair - * [11: 6] Reserved - * [24:12] PCI I/O Base i - * This field defines the start of PCI I/O region n - * [31:25] Reserved - */ - ADDRMAP_REG(0xC8), 0xFE000FCC, 0x00000000, - ADDRMAP_REG(0xD0), 0xFE000FCC, 0x00000000, - ADDRMAP_REG(0xD8), 0xFE000FCC, 0x00000000, - - /* Config Base and Limit i Registers - * F1:0xE0 i = 0 - * F1:0xE4 i = 1 - * F1:0xE8 i = 2 - * F1:0xEC i = 3 - * [ 0: 0] Read Enable - * 0 = Reads Disabled - * 1 = Reads Enabled - * [ 1: 1] Write Enable - * 0 = Writes Disabled - * 1 = Writes Enabled - * [ 2: 2] Device Number Compare Enable - * 0 = The ranges are based on bus number - * 1 = The ranges are ranges of devices on bus 0 - * [ 3: 3] Reserved - * [ 6: 4] Destination Node - * 000 = Node 0 - * 001 = Node 1 - * 010 = Node 2 - * 011 = Node 3 - * 100 = Node 4 - * 101 = Node 5 - * 110 = Node 6 - * 111 = Node 7 - * [ 7: 7] Reserved - * [ 9: 8] Destination Link - * 00 = Link 0 - * 01 = Link 1 - * 10 = Link 2 - * 11 - Reserved - * [15:10] Reserved - * [23:16] Bus Number Base i - * This field defines the lowest bus number in configuration region i - * [31:24] Bus Number Limit i - * This field defines the highest bus number in configuration regin i - */ - /* AMD 8111 on link0 of CPU 0 */ - ADDRMAP_REG(0xE4), 0x0000FC88, 0x00000000, - ADDRMAP_REG(0xE8), 0x0000FC88, 0x00000000, - ADDRMAP_REG(0xEC), 0x0000FC88, 0x00000000, - }; - - int max; - max = ARRAY_SIZE(register_values); - setup_resource_map(register_values, max); -} diff --git a/src/mainboard/advansus/a785e-i/romstage.c b/src/mainboard/advansus/a785e-i/romstage.c deleted file mode 100644 index 0589a0be77..0000000000 --- a/src/mainboard/advansus/a785e-i/romstage.c +++ /dev/null @@ -1,223 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#define SYSTEM_TYPE 1 /* SERVER=0, DESKTOP=1, MOBILE=2 */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include "southbridge/amd/sb800/early_setup.c" -#include -#include - -#include "cpu/amd/quadcore/quadcore.c" -#include "spd.h" - -#define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1) - -int spd_read_byte(unsigned int device, unsigned int address); - - -int spd_read_byte(u32 device, u32 address) -{ - return do_smbus_read_byte(SMBUS_IO_BASE, device, address); -} - -void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) -{ - struct sys_info *sysinfo = get_sysinfo(); - static const u8 spd_addr[] = {RC00, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, }; - u32 bsp_apicid = 0, val; - msr_t msr; - - timestamp_init(timestamp_get()); - timestamp_add_now(TS_START_ROMSTAGE); - - if (!cpu_init_detectedx && boot_cpu()) { - /* Nothing special needs to be done to find bus 0 */ - /* Allow the HT devices to be found */ - /* mov bsp to bus 0xff when > 8 nodes */ - set_bsp_node_CHtExtNodeCfgEn(); - enumerate_ht_chain(); - - /* enable port80 decoding and southbridge poweron init */ - sb800_lpc_init(); - sb800_pci_port80(); - } - - post_code(0x30); - - if (bist == 0) { - bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo); /* mmconf is inited in init_cpus */ - /* All cores run this but the BSP(node0,core0) is the only core that returns. */ - } - - post_code(0x32); - - enable_rs780_dev8(); - sb800_clk_output_48Mhz(); - - winbond_set_clksel_48(PNP_DEV(0x2e, 0)); - winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); - - console_init(); - printk(BIOS_DEBUG, "\n"); - - /* Halt if there was a built in self test failure */ - report_bist_failure(bist); - - /* Load MPB */ - val = cpuid_eax(1); - printk(BIOS_DEBUG, "BSP Family_Model: %08x\n", val); - printk(BIOS_DEBUG, "*sysinfo range: [%p,%p]\n",sysinfo,sysinfo+1); - printk(BIOS_DEBUG, "bsp_apicid = %02x\n", bsp_apicid); - printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx); - - /* Setup sysinfo defaults */ - set_sysinfo_in_ram(0); - - update_microcode(val); - - post_code(0x33); - - cpuSetAMDMSR(0); - post_code(0x34); - - amd_ht_init(sysinfo); - post_code(0x35); - - /* Setup nodes PCI space and start core 0 AP init. */ - finalize_node_setup(sysinfo); - - /* Setup any mainboard PCI settings etc. */ - setup_mb_resource_map(); - post_code(0x36); - - /* wait for all the APs core0 started by finalize_node_setup. */ - /* FIXME: A bunch of cores are going to start output to serial at once. - It would be nice to fixup prink spinlocks for ROM XIP mode. - I think it could be done by putting the spinlock flag in the cache - of the BSP located right after sysinfo. - */ - wait_all_core0_started(); - -#if CONFIG(LOGICAL_CPUS) - /* Core0 on each node is configured. Now setup any additional cores. */ - printk(BIOS_DEBUG, "start_other_cores()\n"); - start_other_cores(bsp_apicid); - post_code(0x37); - wait_all_other_cores_started(bsp_apicid); -#endif - - post_code(0x38); - - /* run _early_setup before soft-reset. */ - rs780_early_setup(); - sb800_early_setup(); - -#if CONFIG(SET_FIDVID) - msr = rdmsr(MSR_COFVID_STS); - printk(BIOS_DEBUG, "\nBegin FIDVID MSR 0xc0010071 0x%08x 0x%08x\n", msr.hi, msr.lo); - post_code(0x39); - - enable_fid_change_on_sb(sysinfo->sbbusn, sysinfo->sbdn); - - if (!warm_reset_detect(0)) { /* BSP is node 0 */ - init_fidvid_bsp(bsp_apicid, sysinfo->nodes); - } else { - init_fidvid_stage2(bsp_apicid, 0); /* BSP is node 0 */ - } - - post_code(0x3A); - - /* show final fid and vid */ - msr = rdmsr(MSR_COFVID_STS); - printk(BIOS_DEBUG, "End FIDVIDMSR 0xc0010071 0x%08x 0x%08x\n", msr.hi, msr.lo); -#endif - - rs780_htinit(); - - /* Reset for HT, FIDVID, PLL and errata changes to take affect. */ - if (!warm_reset_detect(0)) { - printk(BIOS_INFO, "...WARM RESET...\n\n\n"); - soft_reset(); - die("After soft_reset - shouldn't see this message!!!\n"); - } - - post_code(0x3B); - - /* It's the time to set ctrl in sysinfo now; */ - printk(BIOS_DEBUG, "fill_mem_ctrl()\n"); - fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr); - - post_code(0x40); - - raminit_amdmct(sysinfo); - - cbmem_initialize_empty(); - post_code(0x41); - - amdmct_cbmem_store_info(sysinfo); - - sb800_before_pci_init(); - - post_code(0x42); -} - -/** - * BOOL AMD_CB_ManualBUIDSwapList(u8 Node, u8 Link, u8 **List) - * Description: - * This routine is called every time a non-coherent chain is processed. - * BUID assignment may be controlled explicitly on a non-coherent chain. Provide a - * swap list. The first part of the list controls the BUID assignment and the - * second part of the list provides the device to device linking. Device orientation - * can be detected automatically, or explicitly. See documentation for more details. - * - * Automatic non-coherent init assigns BUIDs starting at 1 and incrementing sequentially - * based on each device's unit count. - * - * Parameters: - * @param[in] node = The node on which this chain is located - * @param[in] link = The link on the host for this chain - * @param[out] List = supply a pointer to a list - */ -BOOL AMD_CB_ManualBUIDSwapList (u8 node, u8 link, const u8 **List) -{ - static const u8 swaplist[] = {0, 1, 0xFF, 0, 0xFF}; - /* If the BUID was adjusted in early_ht we need to do the manual override */ - if ((node == 0) && (link == 0)) { /* BSP SB link */ - *List = swaplist; - return 1; - } - - return 0; -} diff --git a/src/mainboard/amd/bimini_fam10/Kconfig b/src/mainboard/amd/bimini_fam10/Kconfig deleted file mode 100644 index eda98c8c0f..0000000000 --- a/src/mainboard/amd/bimini_fam10/Kconfig +++ /dev/null @@ -1,60 +0,0 @@ -if BOARD_AMD_BIMINI_FAM10 - -config BOARD_SPECIFIC_OPTIONS - def_bool y - select CPU_AMD_SOCKET_ASB2 - select DIMM_DDR3 - select DIMM_REGISTERED - select NORTHBRIDGE_AMD_AMDFAM10 - select SOUTHBRIDGE_AMD_RS780 - select SOUTHBRIDGE_AMD_SB800 - select SUPERIO_ITE_IT8718F - select HAVE_OPTION_TABLE - select HAVE_PIRQ_TABLE - select HAVE_MP_TABLE - select HAVE_ACPI_TABLES - select SB_HT_CHAIN_UNITID_OFFSET_ONLY - select LIFT_BSP_APIC_ID - select BOARD_ROMSIZE_KB_2048 - select ENABLE_APIC_EXT_ID - select GFXUMA - select HAVE_DEBUG_CAR - select SET_FIDVID - -config MAINBOARD_DIR - string - default amd/bimini_fam10 - -config APIC_ID_OFFSET - hex - default 0x0 - -config MAINBOARD_PART_NUMBER - string - default "Bimini (Fam10)" - -config HW_MEM_HOLE_SIZEK - hex - default 0x100000 - -config MAX_CPUS - int - default 8 - -config MAX_PHYSICAL_CPUS - int - default 2 - -config HT_CHAIN_END_UNITID_BASE - hex - default 0x1 - -config HT_CHAIN_UNITID_BASE - hex - default 0x0 - -config IRQ_SLOT_COUNT - int - default 11 - -endif #BOARD_AMD_BIMINI_FAM10 diff --git a/src/mainboard/amd/bimini_fam10/Kconfig.name b/src/mainboard/amd/bimini_fam10/Kconfig.name deleted file mode 100644 index 8382656066..0000000000 --- a/src/mainboard/amd/bimini_fam10/Kconfig.name +++ /dev/null @@ -1,2 +0,0 @@ -config BOARD_AMD_BIMINI_FAM10 - bool "Bimini (Fam10)" diff --git a/src/mainboard/amd/bimini_fam10/Makefile.inc b/src/mainboard/amd/bimini_fam10/Makefile.inc deleted file mode 100644 index 91d4b39c32..0000000000 --- a/src/mainboard/amd/bimini_fam10/Makefile.inc +++ /dev/null @@ -1,16 +0,0 @@ -# -# This file is part of the coreboot project. -# -# This program is free software; you can redistribute it and/or modify -# it under the terms of the GNU General Public License as published by -# the Free Software Foundation; version 2 of the License. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# - -romstage-y += resourcemap.c - -ramstage-y += get_bus_conf.c diff --git a/src/mainboard/amd/bimini_fam10/acpi/cpstate.asl b/src/mainboard/amd/bimini_fam10/acpi/cpstate.asl deleted file mode 100644 index acaa5bae32..0000000000 --- a/src/mainboard/amd/bimini_fam10/acpi/cpstate.asl +++ /dev/null @@ -1,80 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2010 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -/* This file defines the processor and performance state capability - * for each core in the system. It is included into the DSDT for each - * core. It assumes that each core of the system has the same performance - * characteristics. -*/ -/* -#include -DefinitionBlock ("DSDT.AML", "DSDT", 0x01, OEM_ID, ACPI_TABLE_CREATOR, 0x00010001) - { - Scope (\_PR) { - Device (CPU0) { - Name (_HID, "ACPI0007") - Name (_UID, 0) - #include "cpstate.asl" - } - Device (CPU1) { - Name (_HID, "ACPI0007") - Name (_UID, 1) - #include "cpstate.asl" - } - Device (CPU2) { - Name (_HID, "ACPI0007") - Name (_UID, 2) - #include "cpstate.asl" - } - Device (CPU3) { - Name (_HID, "ACPI0007") - Name (_UID, 3) - #include "cpstate.asl" - } - } -*/ - /* P-state support: The maximum number of P-states supported by the */ - /* CPUs we'll use is 6. */ - /* Get from AMI BIOS. */ - Name(_PSS, Package(){ - Package () - { - 0x00000AF0, - 0x0000BF81, - 0x00000002, - 0x00000002, - 0x00000000, - 0x00000000 - }, - - Package () - { - 0x00000578, - 0x000076F2, - 0x00000002, - 0x00000002, - 0x00000001, - 0x00000001 - } - }) - - Name(_PCT, Package(){ - ResourceTemplate(){Register(FFixedHW, 0, 0, 0)}, - ResourceTemplate(){Register(FFixedHW, 0, 0, 0)} - }) - - Method(_PPC, 0){ - Return(0) - } diff --git a/src/mainboard/amd/bimini_fam10/acpi/ide.asl b/src/mainboard/amd/bimini_fam10/acpi/ide.asl deleted file mode 100644 index 5c155cf301..0000000000 --- a/src/mainboard/amd/bimini_fam10/acpi/ide.asl +++ /dev/null @@ -1,240 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2010 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -/* -Scope (_SB) { - Device(PCI0) { - Device(IDEC) { - Name(_ADR, 0x00140001) - #include "ide.asl" - } - } -} -*/ - -/* Some timing tables */ -Name(UDTT, Package(){ /* Udma timing table */ - 120, 90, 60, 45, 30, 20, 15, 0 /* UDMA modes 0 -> 6 */ -}) - -Name(MDTT, Package(){ /* MWDma timing table */ - 480, 150, 120, 0 /* Legacy DMA modes 0 -> 2 */ -}) - -Name(POTT, Package(){ /* Pio timing table */ - 600, 390, 270, 180, 120, 0 /* PIO modes 0 -> 4 */ -}) - -/* Some timing register value tables */ -Name(MDRT, Package(){ /* MWDma timing register table */ - 0x77, 0x21, 0x20, 0xFF /* Legacy DMA modes 0 -> 2 */ -}) - -Name(PORT, Package(){ - 0x99, 0x47, 0x34, 0x22, 0x20, 0x99 /* PIO modes 0 -> 4 */ -}) - -OperationRegion(ICRG, PCI_Config, 0x40, 0x20) /* ide control registers */ - Field(ICRG, AnyAcc, NoLock, Preserve) -{ - PPTS, 8, /* Primary PIO Slave Timing */ - PPTM, 8, /* Primary PIO Master Timing */ - OFFSET(0x04), PMTS, 8, /* Primary MWDMA Slave Timing */ - PMTM, 8, /* Primary MWDMA Master Timing */ - OFFSET(0x08), PPCR, 8, /* Primary PIO Control */ - OFFSET(0x0A), PPMM, 4, /* Primary PIO master Mode */ - PPSM, 4, /* Primary PIO slave Mode */ - OFFSET(0x14), PDCR, 2, /* Primary UDMA Control */ - OFFSET(0x16), PDMM, 4, /* Primary UltraDMA Mode */ - PDSM, 4, /* Primary UltraDMA Mode */ -} - -Method(GTTM, 1) /* get total time*/ -{ - Store(And(Arg0, 0x0F), Local0) /* Recovery Width */ - Increment(Local0) - Store(ShiftRight(Arg0, 4), Local1) /* Command Width */ - Increment(Local1) - Return(Multiply(30, Add(Local0, Local1))) -} - -Device(PRID) -{ - Name (_ADR, Zero) - Method(_GTM, 0) - { - NAME(OTBF, Buffer(20) { /* out buffer */ - 0xFF, 0xFF, 0xFF, 0xFF, - 0xFF, 0xFF, 0xFF, 0xFF, - 0xFF, 0xFF, 0xFF, 0xFF, - 0xFF, 0xFF, 0xFF, 0xFF, 0x00, 0x00, 0x00, 0x00 - }) - - CreateDwordField(OTBF, 0, PSD0) /* PIO spd0 */ - CreateDwordField(OTBF, 4, DSD0) /* DMA spd0 */ - CreateDwordField(OTBF, 8, PSD1) /* PIO spd1 */ - CreateDwordField(OTBF, 12, DSD1) /* DMA spd1 */ - CreateDwordField(OTBF, 16, BFFG) /* buffer flags */ - - /* Just return if the channel is disabled */ - If(And(PPCR, 0x01)) { /* primary PIO control */ - Return(OTBF) - } - - /* Always tell them independent timing available and IOChannelReady used on both drives */ - Or(BFFG, 0x1A, BFFG) - - Store(GTTM(PPTM), PSD0) /* save total time of primary PIO master timming to PIO spd0 */ - Store(GTTM(PPTS), PSD1) /* save total time of primary PIO slave Timing to PIO spd1 */ - - If(And(PDCR, 0x01)) { /* It's under UDMA mode */ - Or(BFFG, 0x01, BFFG) - Store(DerefOf(Index(UDTT, PDMM)), DSD0) - } - Else { - Store(GTTM(PMTM), DSD0) /* Primary MWDMA Master Timing, DmaSpd0 */ - } - - If(And(PDCR, 0x02)) { /* It's under UDMA mode */ - Or(BFFG, 0x04, BFFG) - Store(DerefOf(Index(UDTT, PDSM)), DSD1) - } - Else { - Store(GTTM(PMTS), DSD1) /* Primary MWDMA Slave Timing, DmaSpd0 */ - } - - Return(OTBF) /* out buffer */ - } /* End Method(_GTM) */ - - Method(_STM, 3, NotSerialized) - { - NAME(INBF, Buffer(20) { /* in buffer */ - 0xFF, 0xFF, 0xFF, 0xFF, - 0xFF, 0xFF, 0xFF, 0xFF, - 0xFF, 0xFF, 0xFF, 0xFF, - 0xFF, 0xFF, 0xFF, 0xFF, 0x00, 0x00, 0x00, 0x00 - }) - - CreateDwordField(INBF, 0, PSD0) /* PIO spd0 */ - CreateDwordField(INBF, 4, DSD0) /* PIO spd0 */ - CreateDwordField(INBF, 8, PSD1) /* PIO spd1 */ - CreateDwordField(INBF, 12, DSD1) /* DMA spd1 */ - CreateDwordField(INBF, 16, BFFG) /*buffer flag */ - - Store(Match(POTT, MLE, PSD0, MTR, 0, 0), Local0) - Divide(Local0, 5, PPMM,) /* Primary PIO master Mode */ - Store(Match(POTT, MLE, PSD1, MTR, 0, 0), Local1) - Divide(Local1, 5, PPSM,) /* Primary PIO slave Mode */ - - Store(DerefOf(Index(PORT, Local0)), PPTM) /* Primary PIO Master Timing */ - Store(DerefOf(Index(PORT, Local1)), PPTS) /* Primary PIO Slave Timing */ - - If(And(BFFG, 0x01)) { /* Drive 0 is under UDMA mode */ - Store(Match(UDTT, MLE, DSD0, MTR, 0, 0), Local0) - Divide(Local0, 7, PDMM,) - Or(PDCR, 0x01, PDCR) - } - Else { - If(LNotEqual(DSD0, 0xFFFFFFFF)) { - Store(Match(MDTT, MLE, DSD0, MTR, 0, 0), Local0) - Store(DerefOf(Index(MDRT, Local0)), PMTM) - } - } - - If(And(BFFG, 0x04)) { /* Drive 1 is under UDMA mode */ - Store(Match(UDTT, MLE, DSD1, MTR, 0, 0), Local0) - Divide(Local0, 7, PDSM,) - Or(PDCR, 0x02, PDCR) - } - Else { - If(LNotEqual(DSD1, 0xFFFFFFFF)) { - Store(Match(MDTT, MLE, DSD1, MTR, 0, 0), Local0) - Store(DerefOf(Index(MDRT, Local0)), PMTS) - } - } - /* Return(INBF) */ - } /*End Method(_STM) */ - Device(MST) - { - Name(_ADR, 0) - Method(_GTF) { - Name(CMBF, Buffer(21) { - 0x03, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xEF, - 0x03, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xEF, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xF5 - }) - CreateByteField(CMBF, 1, POMD) - CreateByteField(CMBF, 8, DMMD) - CreateByteField(CMBF, 5, CMDA) - CreateByteField(CMBF, 12, CMDB) - CreateByteField(CMBF, 19, CMDC) - - Store(0xA0, CMDA) - Store(0xA0, CMDB) - Store(0xA0, CMDC) - - Or(PPMM, 0x08, POMD) - - If(And(PDCR, 0x01)) { - Or(PDMM, 0x40, DMMD) - } - Else { - Store(Match - (MDTT, MLE, GTTM(PMTM), - MTR, 0, 0), Local0) - If(LLess(Local0, 3)) { - Or(0x20, Local0, DMMD) - } - } - Return(CMBF) - } - } /* End Device(MST) */ - - Device(SLAV) - { - Name(_ADR, 1) - Method(_GTF) { - Name(CMBF, Buffer(21) { - 0x03, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xEF, - 0x03, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xEF, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xF5 - }) - CreateByteField(CMBF, 1, POMD) - CreateByteField(CMBF, 8, DMMD) - CreateByteField(CMBF, 5, CMDA) - CreateByteField(CMBF, 12, CMDB) - CreateByteField(CMBF, 19, CMDC) - - Store(0xB0, CMDA) - Store(0xB0, CMDB) - Store(0xB0, CMDC) - - Or(PPSM, 0x08, POMD) - - If(And(PDCR, 0x02)) { - Or(PDSM, 0x40, DMMD) - } - Else { - Store(Match - (MDTT, MLE, GTTM(PMTS), - MTR, 0, 0), Local0) - If(LLess(Local0, 3)) { - Or(0x20, Local0, DMMD) - } - } - Return(CMBF) - } - } /* End Device(SLAV) */ -} diff --git a/src/mainboard/amd/bimini_fam10/acpi/routing.asl b/src/mainboard/amd/bimini_fam10/acpi/routing.asl deleted file mode 100644 index 0c18e25eea..0000000000 --- a/src/mainboard/amd/bimini_fam10/acpi/routing.asl +++ /dev/null @@ -1,395 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2010 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -/* -#include -DefinitionBlock ("DSDT.AML", "DSDT", 0x01, OEM_ID, ACPI_TABLE_CREATOR, 0x00010001 - ) - { - #include "routing.asl" - } -*/ - -/* Routing is in System Bus scope */ -Scope(\_SB) { - Name(PR0, Package(){ - /* NB devices */ - /* Bus 0, Dev 0 - RS780 Host Controller */ - /* Bus 0, Dev 1 - PCI Bridge for Internal Graphics */ - /* Bus 0, Dev 2 - PCIe Bridge for x8 PCIe Slot (GFX0) */ - Package(){0x0002FFFF, 0, INTC, 0 }, - Package(){0x0002FFFF, 1, INTD, 0 }, - Package(){0x0002FFFF, 2, INTA, 0 }, - Package(){0x0002FFFF, 3, INTB, 0 }, - /* Bus 0, Dev 3 - PCIe graphics port 1 bridge */ - /* Bus 0, Dev 4 - PCIe Bridge for Express Card Slot */ - Package(){0x0004FFFF, 0, INTA, 0 }, - Package(){0x0004FFFF, 1, INTB, 0 }, - Package(){0x0004FFFF, 2, INTC, 0 }, - Package(){0x0004FFFF, 3, INTD, 0 }, - /* Bus 0, Dev 5 - General purpose PCIe bridge 5 */ - /* Package(){0x0005FFFF, 0, INTB, 0 }, */ - /* Package(){0x0005FFFF, 1, INTC, 0 }, */ - /* Package(){0x0005FFFF, 2, INTD, 0 }, */ - /* Package(){0x0005FFFF, 3, INTA, 0 }, */ - /* Bus 0, Dev 6 - PCIe Bridge for Ethernet Chip */ - Package(){0x0006FFFF, 0, INTC, 0 }, - Package(){0x0006FFFF, 1, INTD, 0 }, - Package(){0x0006FFFF, 2, INTA, 0 }, - Package(){0x0006FFFF, 3, INTB, 0 }, - /* Bus 0, Dev 7 - PCIe Bridge for x1 PCIe Slot */ - Package(){0x0007FFFF, 0, INTD, 0 }, - Package(){0x0007FFFF, 1, INTA, 0 }, - Package(){0x0007FFFF, 2, INTB, 0 }, - Package(){0x0007FFFF, 3, INTC, 0 }, - - Package(){0x0009FFFF, 0, INTB, 0 }, - Package(){0x0009FFFF, 1, INTC, 0 }, - Package(){0x0009FFFF, 2, INTD, 0 }, - Package(){0x0009FFFF, 3, INTA, 0 }, - - Package(){0x000AFFFF, 0, INTC, 0 }, - Package(){0x000AFFFF, 1, INTD, 0 }, - Package(){0x000AFFFF, 2, INTA, 0 }, - Package(){0x000AFFFF, 3, INTB, 0 }, - - Package(){0x000BFFFF, 0, INTD, 0 }, - Package(){0x000BFFFF, 1, INTA, 0 }, - Package(){0x000BFFFF, 2, INTB, 0 }, - Package(){0x000BFFFF, 3, INTC, 0 }, - - Package(){0x000CFFFF, 0, INTA, 0 }, - Package(){0x000CFFFF, 1, INTB, 0 }, - Package(){0x000CFFFF, 2, INTC, 0 }, - Package(){0x000CFFFF, 3, INTD, 0 }, - - /* Bus 0, Funct 8 - Southbridge port (normally hidden) */ - - /* SB devices */ - /* Bus 0, Dev 17 - SATA controller #2 */ - /* Bus 0, Dev 18 - SATA controller #1 */ - Package(){0x0011FFFF, 0, INTD, 0 }, - - /* Bus 0, Dev 19 - USB: OHCI, dev 18,19 func 0-2, dev 20 func 5; - * EHCI, dev 18, 19 func 2 */ - Package(){0x0012FFFF, 0, INTC, 0 }, - Package(){0x0012FFFF, 1, INTB, 0 }, - - Package(){0x0013FFFF, 0, INTC, 0 }, - Package(){0x0013FFFF, 1, INTB, 0 }, - - Package(){0x0016FFFF, 0, INTC, 0 }, - Package(){0x0016FFFF, 1, INTB, 0 }, - - /* Package(){0x0014FFFF, 1, INTA, 0 }, */ - - /* Bus 0, Dev 20 - F0:SMBus/ACPI,F1:IDE;F2:HDAudio;F3:LPC;F4:PCIBridge;F5:USB */ - Package(){0x0014FFFF, 0, INTA, 0 }, - Package(){0x0014FFFF, 1, INTB, 0 }, - Package(){0x0014FFFF, 2, INTC, 0 }, - Package(){0x0014FFFF, 3, INTD, 0 }, - - Package(){0x0015FFFF, 0, INTA, 0 }, - Package(){0x0015FFFF, 1, INTB, 0 }, - Package(){0x0015FFFF, 2, INTC, 0 }, - Package(){0x0015FFFF, 3, INTD, 0 }, - }) - - Name(APR0, Package(){ - /* NB devices in APIC mode */ - /* Bus 0, Dev 0 - RS780 Host Controller */ - - /* Bus 0, Dev 1 - PCI Bridge for Internal Graphics */ - Package(){0x0001FFFF, 0, 0, 18 }, - Package(){0x0001FFFF, 1, 0, 19 }, - - /* Bus 0, Dev 2 - PCIe Bridge for x8 PCIe Slot (GFX0) */ - Package(){0x0002FFFF, 0, 0, 18 }, - /* Package(){0x0002FFFF, 1, 0, 19 }, */ - /* Package(){0x0002FFFF, 2, 0, 16 }, */ - /* Package(){0x0002FFFF, 3, 0, 17 }, */ - - /* Bus 0, Dev 3 - PCIe graphics port 1 bridge */ - Package(){0x0003FFFF, 0, 0, 19 }, - - /* Bus 0, Dev 4 - PCIe Bridge for Express Card Slot */ - Package(){0x0004FFFF, 0, 0, 16 }, - /* Package(){0x0004FFFF, 1, 0, 17 }, */ - /* Package(){0x0004FFFF, 2, 0, 18 }, */ - /* Package(){0x0004FFFF, 3, 0, 19 }, */ - - /* Bus 0, Dev 5 - General purpose PCIe bridge 5 */ - /* Package(){0x0005FFFF, 0, 0, 17 }, */ - /* Package(){0x0005FFFF, 1, 0, 18 }, */ - /* Package(){0x0005FFFF, 2, 0, 19 }, */ - /* Package(){0x0005FFFF, 3, 0, 16 }, */ - - /* Bus 0, Dev 6 - General purpose PCIe bridge 6 */ - /* Package(){0x0006FFFF, 0, 0, 18 }, */ - /* Package(){0x0006FFFF, 1, 0, 19 }, */ - /* Package(){0x0006FFFF, 2, 0, 16 }, */ - /* Package(){0x0006FFFF, 3, 0, 17 }, */ - - /* Bus 0, Dev 7 - PCIe Bridge for network card */ - /* Package(){0x0007FFFF, 0, 0, 19 }, */ - /* Package(){0x0007FFFF, 1, 0, 16 }, */ - /* Package(){0x0007FFFF, 2, 0, 17 }, */ - /* Package(){0x0007FFFF, 3, 0, 18 }, */ - - /* Bus 0, Dev 9 - PCIe Bridge for network card */ - Package(){0x0009FFFF, 0, 0, 17 }, - /* Package(){0x0009FFFF, 1, 0, 16 }, */ - /* Package(){0x0009FFFF, 2, 0, 17 }, */ - /* Package(){0x0009FFFF, 3, 0, 18 }, */ - /* Bus 0, Dev A - PCIe Bridge for network card */ - Package(){0x000AFFFF, 0, 0, 18 }, - /* Package(){0x000AFFFF, 1, 0, 16 }, */ - /* Package(){0x000AFFFF, 2, 0, 17 }, */ - /* Package(){0x000AFFFF, 3, 0, 18 }, */ - /* Bus 0, Funct 8 - Southbridge port (normally hidden) */ - - /* SB devices in APIC mode */ - /* Bus 0, Dev 17 - SATA controller #2 */ - /* Bus 0, Dev 18 - SATA controller #1 */ - Package(){0x0011FFFF, 0, 0, 19 }, - - /* Bus 0, Dev 19 - USB: OHCI, dev 18,19 func 0-2, dev 20 func 5; - * EHCI, dev 18, 19 func 2 */ - Package(){0x0012FFFF, 0, 0, 18 }, - Package(){0x0012FFFF, 1, 0, 17 }, - /* Package(){0x0012FFFF, 2, 0, 18 }, */ - - Package(){0x0013FFFF, 0, 0, 18 }, - Package(){0x0013FFFF, 1, 0, 17 }, - /* Package(){0x0013FFFF, 2, 0, 16 }, */ - - /* Package(){0x00140000, 0, 0, 16 }, */ - - Package(){0x0016FFFF, 0, 0, 18 }, - Package(){0x0016FFFF, 1, 0, 17 }, - - /* Bus 0, Dev 20 - F0:SMBus/ACPI, F1:IDE; F2:HDAudio; F3:LPC; F4:PCIBridge; F5:USB */ - Package(){0x0014FFFF, 0, 0, 16 }, - Package(){0x0014FFFF, 1, 0, 17 }, - Package(){0x0014FFFF, 2, 0, 18 }, - Package(){0x0014FFFF, 3, 0, 19 }, - /* Package(){0x00140004, 2, 0, 18 }, */ - /* Package(){0x00140004, 3, 0, 19 }, */ - /* Package(){0x00140005, 1, 0, 17 }, */ - /* Package(){0x00140006, 1, 0, 17 }, */ - - /* TODO: pcie */ - Package(){0x0015FFFF, 0, 0, 16 }, - Package(){0x0015FFFF, 1, 0, 17 }, - Package(){0x0015FFFF, 2, 0, 18 }, - Package(){0x0015FFFF, 3, 0, 19 }, - }) - - Name(PR1, Package(){ - /* Internal graphics - RS780 VGA, Bus1, Dev5 */ - Package(){0x0005FFFF, 0, INTA, 0 }, - Package(){0x0005FFFF, 1, INTB, 0 }, - Package(){0x0005FFFF, 2, INTC, 0 }, - Package(){0x0005FFFF, 3, INTD, 0 }, - }) - Name(APR1, Package(){ - /* Internal graphics - RS780 VGA, Bus1, Dev5 */ - Package(){0x0005FFFF, 0, 0, 18 }, - Package(){0x0005FFFF, 1, 0, 19 }, - /* Package(){0x0005FFFF, 2, 0, 20 }, */ - /* Package(){0x0005FFFF, 3, 0, 17 }, */ - }) - - Name(PS2, Package(){ - /* The external GFX - Hooked to PCIe slot 2 */ - Package(){0x0000FFFF, 0, INTC, 0 }, - Package(){0x0000FFFF, 1, INTD, 0 }, - Package(){0x0000FFFF, 2, INTA, 0 }, - Package(){0x0000FFFF, 3, INTB, 0 }, - }) - Name(APS2, Package(){ - /* The external GFX - Hooked to PCIe slot 2 */ - Package(){0x0000FFFF, 0, 0, 18 }, - Package(){0x0000FFFF, 1, 0, 19 }, - Package(){0x0000FFFF, 2, 0, 16 }, - Package(){0x0000FFFF, 3, 0, 17 }, - }) - - Name(PS4, Package(){ - /* PCIe slot - Hooked to PCIe slot 4 */ - Package(){0x0000FFFF, 0, INTA, 0 }, - Package(){0x0000FFFF, 1, INTB, 0 }, - Package(){0x0000FFFF, 2, INTC, 0 }, - Package(){0x0000FFFF, 3, INTD, 0 }, - }) - Name(APS4, Package(){ - /* PCIe slot - Hooked to PCIe slot 4 */ - Package(){0x0000FFFF, 0, 0, 16 }, - Package(){0x0000FFFF, 1, 0, 17 }, - Package(){0x0000FFFF, 2, 0, 18 }, - Package(){0x0000FFFF, 3, 0, 19 }, - }) - - Name(PS5, Package(){ - /* PCIe slot - Hooked to PCIe slot 5 */ - Package(){0x0000FFFF, 0, INTB, 0 }, - Package(){0x0000FFFF, 1, INTC, 0 }, - Package(){0x0000FFFF, 2, INTD, 0 }, - Package(){0x0000FFFF, 3, INTA, 0 }, - }) - Name(APS5, Package(){ - /* PCIe slot - Hooked to PCIe slot 5 */ - Package(){0x0000FFFF, 0, 0, 17 }, - Package(){0x0000FFFF, 1, 0, 18 }, - Package(){0x0000FFFF, 2, 0, 19 }, - Package(){0x0000FFFF, 3, 0, 16 }, - }) - - Name(PS6, Package(){ - /* PCIe slot - Hooked to PCIe slot 6 */ - Package(){0x0000FFFF, 0, INTC, 0 }, - Package(){0x0000FFFF, 1, INTD, 0 }, - Package(){0x0000FFFF, 2, INTA, 0 }, - Package(){0x0000FFFF, 3, INTB, 0 }, - }) - Name(APS6, Package(){ - /* PCIe slot - Hooked to PCIe slot 6 */ - Package(){0x0000FFFF, 0, 0, 18 }, - Package(){0x0000FFFF, 1, 0, 19 }, - Package(){0x0000FFFF, 2, 0, 16 }, - Package(){0x0000FFFF, 3, 0, 17 }, - }) - - Name(PS7, Package(){ - /* The onboard Ethernet chip - Hooked to PCIe slot 7 */ - Package(){0x0000FFFF, 0, INTD, 0 }, - Package(){0x0000FFFF, 1, INTA, 0 }, - Package(){0x0000FFFF, 2, INTB, 0 }, - Package(){0x0000FFFF, 3, INTC, 0 }, - }) - Name(APS7, Package(){ - /* The onboard Ethernet chip - Hooked to PCIe slot 7 */ - Package(){0x0000FFFF, 0, 0, 19 }, - Package(){0x0000FFFF, 1, 0, 16 }, - Package(){0x0000FFFF, 2, 0, 17 }, - Package(){0x0000FFFF, 3, 0, 18 }, - }) - - Name(PS9, Package(){ - /* PCIe slot - Hooked to PCIe slot 9 */ - Package(){0x0000FFFF, 0, INTD, 0 }, - Package(){0x0000FFFF, 1, INTA, 0 }, - Package(){0x0000FFFF, 2, INTB, 0 }, - Package(){0x0000FFFF, 3, INTC, 0 }, - }) - Name(APS9, Package(){ - /* PCIe slot - Hooked to PCIe slot 9 */ - Package(){0x0000FFFF, 0, 0, 17 }, - Package(){0x0000FFFF, 1, 0, 18 }, - Package(){0x0000FFFF, 2, 0, 19 }, - Package(){0x0000FFFF, 3, 0, 16 }, - }) - - Name(PSa, Package(){ - /* PCIe slot - Hooked to PCIe slot 10 */ - Package(){0x0000FFFF, 0, INTD, 0 }, - Package(){0x0000FFFF, 1, INTA, 0 }, - Package(){0x0000FFFF, 2, INTB, 0 }, - Package(){0x0000FFFF, 3, INTC, 0 }, - }) - Name(APSa, Package(){ - /* PCIe slot - Hooked to PCIe slot 10 */ - Package(){0x0000FFFF, 0, 0, 18 }, - Package(){0x0000FFFF, 1, 0, 19 }, - Package(){0x0000FFFF, 2, 0, 16 }, - Package(){0x0000FFFF, 3, 0, 17 }, - }) - - Name(PE0, Package(){ - /* PCIe slot - Hooked to PCIe slot 10 */ - Package(){0x0000FFFF, 0, INTA, 0 }, - Package(){0x0000FFFF, 1, INTB, 0 }, - Package(){0x0000FFFF, 2, INTC, 0 }, - Package(){0x0000FFFF, 3, INTD, 0 }, - }) - Name(APE0, Package(){ - /* PCIe slot - Hooked to PCIe */ - Package(){0x0000FFFF, 0, 0, 16 }, - Package(){0x0000FFFF, 1, 0, 17 }, - Package(){0x0000FFFF, 2, 0, 18 }, - Package(){0x0000FFFF, 3, 0, 19 }, - }) - - Name(PE1, Package(){ - /* PCIe slot - Hooked to PCIe slot 10 */ - Package(){0x0000FFFF, 0, INTB, 0 }, - Package(){0x0000FFFF, 1, INTC, 0 }, - Package(){0x0000FFFF, 2, INTD, 0 }, - Package(){0x0000FFFF, 3, INTA, 0 }, - }) - Name(APE1, Package(){ - /* PCIe slot - Hooked to PCIe */ - Package(){0x0000FFFF, 0, 0, 17 }, - Package(){0x0000FFFF, 1, 0, 18 }, - Package(){0x0000FFFF, 2, 0, 19 }, - Package(){0x0000FFFF, 3, 0, 16 }, - }) - - Name(PE2, Package(){ - /* PCIe slot - Hooked to PCIe slot 10 */ - Package(){0x0000FFFF, 0, INTC, 0 }, - Package(){0x0000FFFF, 1, INTD, 0 }, - Package(){0x0000FFFF, 2, INTA, 0 }, - Package(){0x0000FFFF, 3, INTB, 0 }, - }) - Name(APE2, Package(){ - /* PCIe slot - Hooked to PCIe */ - Package(){0x0000FFFF, 0, 0, 18 }, - Package(){0x0000FFFF, 1, 0, 19 }, - Package(){0x0000FFFF, 2, 0, 16 }, - Package(){0x0000FFFF, 3, 0, 17 }, - }) - - Name(PE3, Package(){ - /* PCIe slot - Hooked to PCIe slot 10 */ - Package(){0x0000FFFF, 0, INTD, 0 }, - Package(){0x0000FFFF, 1, INTA, 0 }, - Package(){0x0000FFFF, 2, INTB, 0 }, - Package(){0x0000FFFF, 3, INTC, 0 }, - }) - Name(APE3, Package(){ - /* PCIe slot - Hooked to PCIe */ - Package(){0x0000FFFF, 0, 0, 19 }, - Package(){0x0000FFFF, 1, 0, 16 }, - Package(){0x0000FFFF, 2, 0, 17 }, - Package(){0x0000FFFF, 3, 0, 18 }, - }) - - Name(PCIB, Package(){ - /* PCI slots: slot 0, slot 1, slot 2 behind Dev14, Fun4. */ - Package(){0x0005FFFF, 0, 0, 0x14 }, - Package(){0x0005FFFF, 1, 0, 0x15 }, - Package(){0x0005FFFF, 2, 0, 0x16 }, - Package(){0x0005FFFF, 3, 0, 0x17 }, - Package(){0x0006FFFF, 0, 0, 0x15 }, - Package(){0x0006FFFF, 1, 0, 0x16 }, - Package(){0x0006FFFF, 2, 0, 0x17 }, - Package(){0x0006FFFF, 3, 0, 0x14 }, - Package(){0x0007FFFF, 0, 0, 0x16 }, - Package(){0x0007FFFF, 1, 0, 0x17 }, - Package(){0x0007FFFF, 2, 0, 0x14 }, - Package(){0x0007FFFF, 3, 0, 0x15 }, - }) -} diff --git a/src/mainboard/amd/bimini_fam10/acpi/sata.asl b/src/mainboard/amd/bimini_fam10/acpi/sata.asl deleted file mode 100644 index cb9b221ba3..0000000000 --- a/src/mainboard/amd/bimini_fam10/acpi/sata.asl +++ /dev/null @@ -1,145 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2010 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -/* simple name description */ - -/* -Scope (_SB) { - Device(PCI0) { - Device(SATA) { - Name(_ADR, 0x00110000) - #include "sata.asl" - } - } -} -*/ - -Name(STTM, Buffer(20) { - 0x78, 0x00, 0x00, 0x00, 0x0f, 0x00, 0x00, 0x00, - 0x78, 0x00, 0x00, 0x00, 0x0f, 0x00, 0x00, 0x00, - 0x1f, 0x00, 0x00, 0x00 -}) - -/* Start by clearing the PhyRdyChg bits */ -Method(_INI) { - \_GPE._L1F() -} - -Device(PMRY) -{ - Name(_ADR, 0) - Method(_GTM, 0x0, NotSerialized) { - Return(STTM) - } - Method(_STM, 0x3, NotSerialized) {} - - Device(PMST) { - Name(_ADR, 0) - Method(_STA,0) { - if (LGreater(P0IS,0)) { - return (0x0F) /* sata is visible */ - } - else { - return (0x00) /* sata is missing */ - } - } - }/* end of PMST */ - - Device(PSLA) - { - Name(_ADR, 1) - Method(_STA,0) { - if (LGreater(P1IS,0)) { - return (0x0F) /* sata is visible */ - } - else { - return (0x00) /* sata is missing */ - } - } - } /* end of PSLA */ -} /* end of PMRY */ - - -Device(SEDY) -{ - Name(_ADR, 1) /* IDE Scondary Channel */ - Method(_GTM, 0x0, NotSerialized) { - Return(STTM) - } - Method(_STM, 0x3, NotSerialized) {} - - Device(SMST) - { - Name(_ADR, 0) - Method(_STA,0) { - if (LGreater(P2IS,0)) { - return (0x0F) /* sata is visible */ - } - else { - return (0x00) /* sata is missing */ - } - } - } /* end of SMST */ - - Device(SSLA) - { - Name(_ADR, 1) - Method(_STA,0) { - if (LGreater(P3IS,0)) { - return (0x0F) /* sata is visible */ - } - else { - return (0x00) /* sata is missing */ - } - } - } /* end of SSLA */ -} /* end of SEDY */ - -/* SATA Hot Plug Support */ -Scope(\_GPE) { - Method(_L1F,0x0,NotSerialized) { - if (\_SB.P0PR) { - if (LGreater(\_SB.P0IS,0)) { - sleep(32) - } - Notify(\_SB.PCI0.STCR.PMRY.PMST, 0x01) /* NOTIFY_DEVICE_CHECK */ - store(one, \_SB.P0PR) - } - - if (\_SB.P1PR) { - if (LGreater(\_SB.P1IS,0)) { - sleep(32) - } - Notify(\_SB.PCI0.STCR.PMRY.PSLA, 0x01) /* NOTIFY_DEVICE_CHECK */ - store(one, \_SB.P1PR) - } - - if (\_SB.P2PR) { - if (LGreater(\_SB.P2IS,0)) { - sleep(32) - } - Notify(\_SB.PCI0.STCR.SEDY.SMST, 0x01) /* NOTIFY_DEVICE_CHECK */ - store(one, \_SB.P2PR) - } - - if (\_SB.P3PR) { - if (LGreater(\_SB.P3IS,0)) { - sleep(32) - } - Notify(\_SB.PCI0.STCR.SEDY.SSLA, 0x01) /* NOTIFY_DEVICE_CHECK */ - store(one, \_SB.P3PR) - } - } -} diff --git a/src/mainboard/amd/bimini_fam10/acpi/usb.asl b/src/mainboard/amd/bimini_fam10/acpi/usb.asl deleted file mode 100644 index a3ccb97ff9..0000000000 --- a/src/mainboard/amd/bimini_fam10/acpi/usb.asl +++ /dev/null @@ -1,158 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2010 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -/* simple name description */ -/* -#include -DefinitionBlock ("DSDT.AML", "DSDT", 0x01, OEM_ID, ACPI_TABLE_CREATOR, 0x00010001 - ) - { - #include "usb.asl" - } -*/ -Method(UCOC, 0) { - Sleep(20) - Store(0x13,CMTI) - Store(0,GPSL) -} - -/* USB Port 0 overcurrent uses Gpm 0 */ -If(LLessEqual(UOM0,9)) { - Scope (\_GPE) { - Method (_L13) { - UCOC() - if(LEqual(GPB0,PLC0)) { - Not(PLC0,PLC0) - Store(PLC0, \_SB.PT0D) - } - } - } -} - -/* USB Port 1 overcurrent uses Gpm 1 */ -If (LLessEqual(UOM1,9)) { - Scope (\_GPE) { - Method (_L14) { - UCOC() - if (LEqual(GPB1,PLC1)) { - Not(PLC1,PLC1) - Store(PLC1, \_SB.PT1D) - } - } - } -} - -/* USB Port 2 overcurrent uses Gpm 2 */ -If (LLessEqual(UOM2,9)) { - Scope (\_GPE) { - Method (_L15) { - UCOC() - if (LEqual(GPB2,PLC2)) { - Not(PLC2,PLC2) - Store(PLC2, \_SB.PT2D) - } - } - } -} - -/* USB Port 3 overcurrent uses Gpm 3 */ -If (LLessEqual(UOM3,9)) { - Scope (\_GPE) { - Method (_L16) { - UCOC() - if (LEqual(GPB3,PLC3)) { - Not(PLC3,PLC3) - Store(PLC3, \_SB.PT3D) - } - } - } -} - -/* USB Port 4 overcurrent uses Gpm 4 */ -If (LLessEqual(UOM4,9)) { - Scope (\_GPE) { - Method (_L19) { - UCOC() - if (LEqual(GPB4,PLC4)) { - Not(PLC4,PLC4) - Store(PLC4, \_SB.PT4D) - } - } - } -} - -/* USB Port 5 overcurrent uses Gpm 5 */ -If (LLessEqual(UOM5,9)) { - Scope (\_GPE) { - Method (_L1A) { - UCOC() - if (LEqual(GPB5,PLC5)) { - Not(PLC5,PLC5) - Store(PLC5, \_SB.PT5D) - } - } - } -} - -/* USB Port 6 overcurrent uses Gpm 6 */ -If (LLessEqual(UOM6,9)) { - Scope (\_GPE) { - /* Method (_L1C) { */ - Method (_L06) { - UCOC() - if (LEqual(GPB6,PLC6)) { - Not(PLC6,PLC6) - Store(PLC6, \_SB.PT6D) - } - } - } -} - -/* USB Port 7 overcurrent uses Gpm 7 */ -If (LLessEqual(UOM7,9)) { - Scope (\_GPE) { - /* Method (_L1D) { */ - Method (_L07) { - UCOC() - if (LEqual(GPB7,PLC7)) { - Not(PLC7,PLC7) - Store(PLC7, \_SB.PT7D) - } - } - } -} - -/* USB Port 8 overcurrent uses Gpm 8 */ -If (LLessEqual(UOM8,9)) { - Scope (\_GPE) { - Method (_L17) { - if (LEqual(G8IS,PLC8)) { - Not(PLC8,PLC8) - Store(PLC8, \_SB.PT8D) - } - } - } -} - -/* USB Port 9 overcurrent uses Gpm 9 */ -If (LLessEqual(UOM9,9)) { - Scope (\_GPE) { - Method (_L0E) { - if (LEqual(G9IS,0)) { - Store(1,\_SB.PT9D) - } - } - } -} diff --git a/src/mainboard/amd/bimini_fam10/acpi_tables.c b/src/mainboard/amd/bimini_fam10/acpi_tables.c deleted file mode 100644 index e7659d145f..0000000000 --- a/src/mainboard/amd/bimini_fam10/acpi_tables.c +++ /dev/null @@ -1,44 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2010 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include -#include - -unsigned long acpi_fill_madt(unsigned long current) -{ - /* create all subtables for processors */ - current = acpi_create_madt_lapics(current); - - /* Write SB800 IOAPIC, only one */ - current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, 2, - IO_APIC_ADDR, 0); - - current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) - current, 0, 0, 2, 0); - current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) - current, 0, 9, 9, 0xF); - /* 0: mean bus 0--->ISA */ - /* 0: PIC 0 */ - /* 2: APIC 2 */ - /* 5 mean: 0101 --> Edge-triggered, Active high */ - - /* create all subtables for processors */ - /* current = acpi_create_madt_lapic_nmis(current, 5, 1); */ - /* 1: LINT1 connect to NMI */ - - return current; -} diff --git a/src/mainboard/amd/bimini_fam10/board_info.txt b/src/mainboard/amd/bimini_fam10/board_info.txt deleted file mode 100644 index b351b8e696..0000000000 --- a/src/mainboard/amd/bimini_fam10/board_info.txt +++ /dev/null @@ -1 +0,0 @@ -Category: eval diff --git a/src/mainboard/amd/bimini_fam10/cmos.layout b/src/mainboard/amd/bimini_fam10/cmos.layout deleted file mode 100644 index 6c3d3f6c9e..0000000000 --- a/src/mainboard/amd/bimini_fam10/cmos.layout +++ /dev/null @@ -1,52 +0,0 @@ -entries - -0 384 r 0 reserved_memory -384 1 e 4 boot_option -388 4 h 0 reboot_counter -#392 3 r 0 unused -395 1 e 1 hw_scrubber -396 1 e 1 interleave_chip_selects -397 2 e 8 max_mem_clock -399 1 e 2 multi_core -400 1 e 1 power_on_after_fail -412 4 e 6 debug_level -440 4 e 9 slow_cpu -444 1 e 1 nmi -445 1 e 1 gart -456 1 e 1 ECC_memory -728 256 h 0 user_data -984 16 h 0 check_sum -# Reserve the extended AMD configuration registers -1000 24 r 0 amd_reserved - - - -enumerations - -#ID value text -1 0 Disable -1 1 Enable -2 0 Enable -2 1 Disable -4 0 Fallback -4 1 Normal -6 5 Notice -6 6 Info -6 7 Debug -6 8 Spew -8 0 400Mhz -8 1 333Mhz -8 2 266Mhz -8 3 200Mhz -9 0 off -9 1 87.5% -9 2 75.0% -9 3 62.5% -9 4 50.0% -9 5 37.5% -9 6 25.0% -9 7 12.5% - -checksums - -checksum 392 983 984 diff --git a/src/mainboard/amd/bimini_fam10/devicetree.cb b/src/mainboard/amd/bimini_fam10/devicetree.cb deleted file mode 100644 index ba6a0fafcf..0000000000 --- a/src/mainboard/amd/bimini_fam10/devicetree.cb +++ /dev/null @@ -1,95 +0,0 @@ - # sample config for amd/bimini_fam10 -chip northbridge/amd/amdfam10/root_complex - device cpu_cluster 0 on - chip cpu/amd/socket_ASB2 #L1 and DDR3 - device lapic 0 on end - end - end - device domain 0 on - subsystemid 0x1022 0x3060 inherit - chip northbridge/amd/amdfam10 - device pci 18.0 on # northbridge - chip southbridge/amd/rs780 - device pci 0.0 on end # HT 0x9600 - device pci 1.0 on end # Internal Graphics P2P bridge 0x9602 - device pci 2.0 off end # PCIE P2P bridge (external graphics) 0x9603 - device pci 3.0 off end # PCIE P2P bridge 0x960b - device pci 4.0 on end # PCIE P2P bridge 0x9604 - device pci 5.0 on end # PCIE P2P bridge 0x9605 - device pci 6.0 on end # PCIE P2P bridge 0x9606 - device pci 7.0 on end # PCIE P2P bridge 0x9607 - device pci 8.0 off end # NB/SB Link P2P bridge - device pci 9.0 on end # - device pci a.0 off end # - register "gppsb_configuration" = "4" # Configuration E - register "gpp_configuration" = "2" # Configuration C - register "port_enable" = "0x6fc" - register "gfx_dev2_dev3" = "1" - register "gfx_dual_slot" = "0" - register "gfx_lane_reversal" = "0" - register "gfx_tmds" = "0" - register "gfx_compliance" = "0" - register "gfx_reconfiguration" = "1" - register "gfx_link_width" = "0" - end - chip southbridge/amd/sb800 # it is under NB/SB Link, but on the same pci bus - device pci 11.0 on end # SATA - device pci 12.0 on end # USB - device pci 12.2 on end # USB - device pci 13.0 on end # USB - device pci 13.2 on end # USB - device pci 14.0 on # SM - chip drivers/generic/generic #dimm 0-0-0 - device i2c 50 on end - end - chip drivers/generic/generic #dimm 0-0-1 - device i2c 51 on end - end - chip drivers/generic/generic #dimm 0-1-0 - device i2c 52 on end - end - chip drivers/generic/generic #dimm 0-1-1 - device i2c 53 on end - end - end # SM - device pci 14.1 on end # IDE 0x439c - device pci 14.2 on end # HDA 0x4383 - device pci 14.3 on end # LPC 0x439d - device pci 14.4 off end # PCI 0x4384 # PCI-b conflict with GPIO. - device pci 14.5 on end # USB 2 - device pci 14.6 on end # Gec - device pci 15.0 on end # PCIe 0 - device pci 15.1 on end # PCIe 1 - device pci 15.2 on end # PCIe 2 - device pci 15.3 on end # PCIe 3 - device pci 16.0 on end # USB - device pci 16.2 on end # USB - register "boot_switch_sata_ide" = "0" # 0: boot from SATA. 1: IDE - register "gpp_configuration" = "4" - end #southbridge/amd/sb800 - end # device pci 18.0 - - device pci 18.0 on end - device pci 18.0 on end - device pci 18.1 on end - device pci 18.2 on end - device pci 18.3 on end - device pci 18.4 on end - end - end #domain - #for node 32 to node 63 -# device domain 0 on -# chip northbridge/amd/amdfam10 -# device pci 00.0 on end# northbridge -# device pci 00.0 on end -# device pci 00.0 on end -# device pci 00.0 on end -# device pci 00.1 on end -# device pci 00.2 on end -# device pci 00.3 on end -# device pci 00.4 on end -# device pci 00.5 on end -# end -# end #domain - -end diff --git a/src/mainboard/amd/bimini_fam10/dsdt.asl b/src/mainboard/amd/bimini_fam10/dsdt.asl deleted file mode 100644 index c7196229fd..0000000000 --- a/src/mainboard/amd/bimini_fam10/dsdt.asl +++ /dev/null @@ -1,1619 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2010 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -/* DefinitionBlock Statement */ -#include -DefinitionBlock ( - "DSDT.AML", /* Output filename */ - "DSDT", /* Signature */ - 0x02, /* DSDT Revision, needs to be 2 for 64bit */ - OEM_ID, - ACPI_TABLE_CREATOR, - 0x00010001 /* OEM Revision */ - ) -{ /* Start of ASL file */ - /* #include */ /* Include global debug methods if needed */ - - /* Data to be patched by the BIOS during POST */ - /* FIXME the patching is not done yet! */ - /* Memory related values */ - Name(LOMH, 0x0) /* Start of unused memory in C0000-E0000 range */ - Name(PBAD, 0x0) /* Address of BIOS area (If TOM2 != 0, Addr >> 16) */ - Name(PBLN, 0x0) /* Length of BIOS area */ - - Name(PCBA, 0xE0000000) /* Base address of PCIe config space */ - Name(HPBA, 0xFED00000) /* Base address of HPET table */ - - /* USB overcurrent mapping pins. */ - Name(UOM0, 0) - Name(UOM1, 2) - Name(UOM2, 0) - Name(UOM3, 7) - Name(UOM4, 2) - Name(UOM5, 2) - Name(UOM6, 6) - Name(UOM7, 2) - Name(UOM8, 6) - Name(UOM9, 6) - - /* Some global data */ - Name(OSVR, 3) /* Assume nothing. WinXp = 1, Vista = 2, Linux = 3, WinCE = 4 */ - Name(OSV, Ones) /* Assume nothing */ - Name(PMOD, One) /* Assume APIC */ - - /* - * Processor Object - * - */ - Scope (\_PR) { /* define processor scope */ - Device (CPU0) { - Name (_HID, "ACPI0007") - Name (_UID, 0) - #include "acpi/cpstate.asl" - } - Device (CPU1) { - Name (_HID, "ACPI0007") - Name (_UID, 1) - #include "acpi/cpstate.asl" - } - Device (CPU2) { - Name (_HID, "ACPI0007") - Name (_UID, 2) - #include "acpi/cpstate.asl" - } - Device (CPU3) { - Name (_HID, "ACPI0007") - Name (_UID, 3) - #include "acpi/cpstate.asl" - } - } /* End _PR scope */ - - /* PIC IRQ mapping registers, C00h-C01h. */ - OperationRegion(PRQM, SystemIO, 0x00000C00, 0x00000002) - Field(PRQM, ByteAcc, NoLock, Preserve) { - PRQI, 0x00000008, - PRQD, 0x00000008, /* Offset: 1h */ - } - IndexField(PRQI, PRQD, ByteAcc, NoLock, Preserve) { - PIRA, 0x00000008, /* Index 0 */ - PIRB, 0x00000008, /* Index 1 */ - PIRC, 0x00000008, /* Index 2 */ - PIRD, 0x00000008, /* Index 3 */ - PIRE, 0x00000008, /* Index 4 */ - PIRF, 0x00000008, /* Index 5 */ - PIRG, 0x00000008, /* Index 6 */ - PIRH, 0x00000008, /* Index 7 */ - } - - /* PCI Error control register */ - OperationRegion(PERC, SystemIO, 0x00000C14, 0x00000001) - Field(PERC, ByteAcc, NoLock, Preserve) { - SENS, 0x00000001, - PENS, 0x00000001, - SENE, 0x00000001, - PENE, 0x00000001, - } - - /* Client Management index/data registers */ - OperationRegion(CMT, SystemIO, 0x00000C50, 0x00000002) - Field(CMT, ByteAcc, NoLock, Preserve) { - CMTI, 8, - /* Client Management Data register */ - G64E, 1, - G64O, 1, - G32O, 2, - , 2, - GPSL, 2, - } - - /* GPM Port register */ - OperationRegion(GPT, SystemIO, 0x00000C52, 0x00000001) - Field(GPT, ByteAcc, NoLock, Preserve) { - GPB0,1, - GPB1,1, - GPB2,1, - GPB3,1, - GPB4,1, - GPB5,1, - GPB6,1, - GPB7,1, - } - - /* Flash ROM program enable register */ - OperationRegion(FRE, SystemIO, 0x00000C6F, 0x00000001) - Field(FRE, ByteAcc, NoLock, Preserve) { - , 0x00000006, - FLRE, 0x00000001, - } - - /* PM2 index/data registers */ - OperationRegion(PM2R, SystemIO, 0x00000CD0, 0x00000002) - Field(PM2R, ByteAcc, NoLock, Preserve) { - PM2I, 0x00000008, - PM2D, 0x00000008, - } - - /* Power Management I/O registers, TODO:PMIO is quite different in SB800. */ - OperationRegion(PIOR, SystemIO, 0x00000CD6, 0x00000002) - Field(PIOR, ByteAcc, NoLock, Preserve) { - PIOI, 0x00000008, - PIOD, 0x00000008, - } - IndexField (PIOI, PIOD, ByteAcc, NoLock, Preserve) { - Offset(0x00), /* MiscControl */ - , 1, - T1EE, 1, - T2EE, 1, - Offset(0x01), /* MiscStatus */ - , 1, - T1E, 1, - T2E, 1, - Offset(0x04), /* SmiWakeUpEventEnable3 */ - , 7, - SSEN, 1, - Offset(0x07), /* SmiWakeUpEventStatus3 */ - , 7, - CSSM, 1, - Offset(0x10), /* AcpiEnable */ - , 6, - PWDE, 1, - Offset(0x1C), /* ProgramIoEnable */ - , 3, - MKME, 1, - IO3E, 1, - IO2E, 1, - IO1E, 1, - IO0E, 1, - Offset(0x1D), /* IOMonitorStatus */ - , 3, - MKMS, 1, - IO3S, 1, - IO2S, 1, - IO1S, 1, - IO0S,1, - Offset(0x20), /* AcpiPmEvtBlk. TODO: should be 0x60 */ - APEB, 16, - Offset(0x36), /* GEvtLevelConfig */ - , 6, - ELC6, 1, - ELC7, 1, - Offset(0x37), /* GPMLevelConfig0 */ - , 3, - PLC0, 1, - PLC1, 1, - PLC2, 1, - PLC3, 1, - PLC8, 1, - Offset(0x38), /* GPMLevelConfig1 */ - , 1, - PLC4, 1, - PLC5, 1, - , 1, - PLC6, 1, - PLC7, 1, - Offset(0x3B), /* PMEStatus1 */ - GP0S, 1, - GM4S, 1, - GM5S, 1, - APS, 1, - GM6S, 1, - GM7S, 1, - GP2S, 1, - STSS, 1, - Offset(0x55), /* SoftPciRst */ - SPRE, 1, - , 1, - , 1, - PNAT, 1, - PWMK, 1, - PWNS, 1, - - /* Offset(0x61), */ /* Options_1 */ - /* ,7, */ - /* R617,1, */ - - Offset(0x65), /* UsbPMControl */ - , 4, - URRE, 1, - Offset(0x68), /* MiscEnable68 */ - , 3, - TMTE, 1, - , 1, - Offset(0x92), /* GEVENTIN */ - , 7, - E7IS, 1, - Offset(0x96), /* GPM98IN */ - G8IS, 1, - G9IS, 1, - Offset(0x9A), /* EnhanceControl */ - ,7, - HPDE, 1, - Offset(0xA8), /* PIO7654Enable */ - IO4E, 1, - IO5E, 1, - IO6E, 1, - IO7E, 1, - Offset(0xA9), /* PIO7654Status */ - IO4S, 1, - IO5S, 1, - IO6S, 1, - IO7S, 1, - } - - /* PM1 Event Block - * First word is PM1_Status, Second word is PM1_Enable - */ - OperationRegion(P1EB, SystemIO, APEB, 0x04) - Field(P1EB, ByteAcc, NoLock, Preserve) { - TMST, 1, - , 3, - BMST, 1, - GBST, 1, - Offset(0x01), - PBST, 1, - , 1, - RTST, 1, - , 3, - PWST, 1, - SPWS, 1, - Offset(0x02), - TMEN, 1, - , 4, - GBEN, 1, - Offset(0x03), - PBEN, 1, - , 1, - RTEN, 1, - , 3, - PWDA, 1, - } - - Scope(\_SB) { - /* PCIe Configuration Space for 16 busses */ - OperationRegion(PCFG, SystemMemory, PCBA, 0x01000000) /* Each bus consumes 1MB */ - Field(PCFG, ByteAcc, NoLock, Preserve) { - /* Byte offsets are computed using the following technique: - * ((bus number + 1) * ((device number * 8) * 4096)) + register offset - * The 8 comes from 8 functions per device, and 4096 bytes per function config space - */ - Offset(0x00088024), /* Byte offset to SATA register 24h - Bus 0, Device 17, Function 0 */ - STB5, 32, - Offset(0x00098042), /* Byte offset to OHCI0 register 42h - Bus 0, Device 19, Function 0 */ - PT0D, 1, - PT1D, 1, - PT2D, 1, - PT3D, 1, - PT4D, 1, - PT5D, 1, - PT6D, 1, - PT7D, 1, - PT8D, 1, - PT9D, 1, - Offset(0x000A0004), /* Byte offset to SMBUS register 4h - Bus 0, Device 20, Function 0 */ - SBIE, 1, - SBME, 1, - Offset(0x000A0008), /* Byte offset to SMBUS register 8h - Bus 0, Device 20, Function 0 */ - SBRI, 8, - Offset(0x000A0014), /* Byte offset to SMBUS register 14h - Bus 0, Device 20, Function 0 */ - SBB1, 32, - Offset(0x000A0078), /* Byte offset to SMBUS register 78h - Bus 0, Device 20, Function 0 */ - ,14, - P92E, 1, /* Port92 decode enable */ - } - - OperationRegion(SB5, SystemMemory, STB5, 0x1000) - Field(SB5, AnyAcc, NoLock, Preserve){ - /* Port 0 */ - Offset(0x120), /* Port 0 Task file status */ - P0ER, 1, - , 2, - P0DQ, 1, - , 3, - P0BY, 1, - Offset(0x128), /* Port 0 Serial ATA status */ - P0DD, 4, - , 4, - P0IS, 4, - Offset(0x12C), /* Port 0 Serial ATA control */ - P0DI, 4, - Offset(0x130), /* Port 0 Serial ATA error */ - , 16, - P0PR, 1, - - /* Port 1 */ - offset(0x1A0), /* Port 1 Task file status */ - P1ER, 1, - , 2, - P1DQ, 1, - , 3, - P1BY, 1, - Offset(0x1A8), /* Port 1 Serial ATA status */ - P1DD, 4, - , 4, - P1IS, 4, - Offset(0x1AC), /* Port 1 Serial ATA control */ - P1DI, 4, - Offset(0x1B0), /* Port 1 Serial ATA error */ - , 16, - P1PR, 1, - - /* Port 2 */ - Offset(0x220), /* Port 2 Task file status */ - P2ER, 1, - , 2, - P2DQ, 1, - , 3, - P2BY, 1, - Offset(0x228), /* Port 2 Serial ATA status */ - P2DD, 4, - , 4, - P2IS, 4, - Offset(0x22C), /* Port 2 Serial ATA control */ - P2DI, 4, - Offset(0x230), /* Port 2 Serial ATA error */ - , 16, - P2PR, 1, - - /* Port 3 */ - Offset(0x2A0), /* Port 3 Task file status */ - P3ER, 1, - , 2, - P3DQ, 1, - , 3, - P3BY, 1, - Offset(0x2A8), /* Port 3 Serial ATA status */ - P3DD, 4, - , 4, - P3IS, 4, - Offset(0x2AC), /* Port 3 Serial ATA control */ - P3DI, 4, - Offset(0x2B0), /* Port 3 Serial ATA error */ - , 16, - P3PR, 1, - } - } - - - #include "acpi/routing.asl" - - Scope(\_SB) { - - Method(OSFL, 0){ - - if(LNotEqual(OSVR, Ones)) {Return(OSVR)} /* OS version was already detected */ - - if(CondRefOf(\_OSI)) - { - Store(1, OSVR) /* Assume some form of XP */ - if (\_OSI("Windows 2006")) /* Vista */ - { - Store(2, OSVR) - } - } else { - If(WCMP(\_OS,"Linux")) { - Store(3, OSVR) /* Linux */ - } Else { - Store(4, OSVR) /* Gotta be WinCE */ - } - } - Return(OSVR) - } - - Method(_PIC, 0x01, NotSerialized) - { - If (Arg0) - { - \_SB.CIRQ() - } - Store(Arg0, PMOD) - } - Method(CIRQ, 0x00, NotSerialized){ - Store(0, PIRA) - Store(0, PIRB) - Store(0, PIRC) - Store(0, PIRD) - Store(0, PIRE) - Store(0, PIRF) - Store(0, PIRG) - Store(0, PIRH) - } - - Name(IRQB, ResourceTemplate(){ - IRQ(Level,ActiveLow,Shared){15} - }) - - Name(IRQP, ResourceTemplate(){ - IRQ(Level,ActiveLow,Exclusive){3, 4, 5, 7, 10, 11, 12, 15} - }) - - Name(PITF, ResourceTemplate(){ - IRQ(Level,ActiveLow,Exclusive){9} - }) - - Device(INTA) { - Name(_HID, EISAID("PNP0C0F")) - Name(_UID, 1) - - Method(_STA, 0) { - if (PIRA) { - Return(0x0B) /* sata is invisible */ - } else { - Return(0x09) /* sata is disabled */ - } - } /* End Method(_SB.INTA._STA) */ - - Method(_DIS ,0) { - /* DBGO("\\_SB\\LNKA\\_DIS\n") */ - Store(0, PIRA) - } /* End Method(_SB.INTA._DIS) */ - - Method(_PRS ,0) { - /* DBGO("\\_SB\\LNKA\\_PRS\n") */ - Return(IRQP) - } /* Method(_SB.INTA._PRS) */ - - Method(_CRS ,0) { - /* DBGO("\\_SB\\LNKA\\_CRS\n") */ - CreateWordField(IRQB, 0x1, IRQN) - ShiftLeft(1, PIRA, IRQN) - Return(IRQB) - } /* Method(_SB.INTA._CRS) */ - - Method(_SRS, 1) { - /* DBGO("\\_SB\\LNKA\\_CRS\n") */ - CreateWordField(ARG0, 1, IRQM) - - /* Use lowest available IRQ */ - FindSetRightBit(IRQM, Local0) - if (Local0) { - Decrement(Local0) - } - Store(Local0, PIRA) - } /* End Method(_SB.INTA._SRS) */ - } /* End Device(INTA) */ - - Device(INTB) { - Name(_HID, EISAID("PNP0C0F")) - Name(_UID, 2) - - Method(_STA, 0) { - if (PIRB) { - Return(0x0B) /* sata is invisible */ - } else { - Return(0x09) /* sata is disabled */ - } - } /* End Method(_SB.INTB._STA) */ - - Method(_DIS ,0) { - /* DBGO("\\_SB\\LNKB\\_DIS\n") */ - Store(0, PIRB) - } /* End Method(_SB.INTB._DIS) */ - - Method(_PRS ,0) { - /* DBGO("\\_SB\\LNKB\\_PRS\n") */ - Return(IRQP) - } /* Method(_SB.INTB._PRS) */ - - Method(_CRS ,0) { - /* DBGO("\\_SB\\LNKB\\_CRS\n") */ - CreateWordField(IRQB, 0x1, IRQN) - ShiftLeft(1, PIRB, IRQN) - Return(IRQB) - } /* Method(_SB.INTB._CRS) */ - - Method(_SRS, 1) { - /* DBGO("\\_SB\\LNKB\\_CRS\n") */ - CreateWordField(ARG0, 1, IRQM) - - /* Use lowest available IRQ */ - FindSetRightBit(IRQM, Local0) - if (Local0) { - Decrement(Local0) - } - Store(Local0, PIRB) - } /* End Method(_SB.INTB._SRS) */ - } /* End Device(INTB) */ - - Device(INTC) { - Name(_HID, EISAID("PNP0C0F")) - Name(_UID, 3) - - Method(_STA, 0) { - if (PIRC) { - Return(0x0B) /* sata is invisible */ - } else { - Return(0x09) /* sata is disabled */ - } - } /* End Method(_SB.INTC._STA) */ - - Method(_DIS ,0) { - /* DBGO("\\_SB\\LNKC\\_DIS\n") */ - Store(0, PIRC) - } /* End Method(_SB.INTC._DIS) */ - - Method(_PRS ,0) { - /* DBGO("\\_SB\\LNKC\\_PRS\n") */ - Return(IRQP) - } /* Method(_SB.INTC._PRS) */ - - Method(_CRS ,0) { - /* DBGO("\\_SB\\LNKC\\_CRS\n") */ - CreateWordField(IRQB, 0x1, IRQN) - ShiftLeft(1, PIRC, IRQN) - Return(IRQB) - } /* Method(_SB.INTC._CRS) */ - - Method(_SRS, 1) { - /* DBGO("\\_SB\\LNKC\\_CRS\n") */ - CreateWordField(ARG0, 1, IRQM) - - /* Use lowest available IRQ */ - FindSetRightBit(IRQM, Local0) - if (Local0) { - Decrement(Local0) - } - Store(Local0, PIRC) - } /* End Method(_SB.INTC._SRS) */ - } /* End Device(INTC) */ - - Device(INTD) { - Name(_HID, EISAID("PNP0C0F")) - Name(_UID, 4) - - Method(_STA, 0) { - if (PIRD) { - Return(0x0B) /* sata is invisible */ - } else { - Return(0x09) /* sata is disabled */ - } - } /* End Method(_SB.INTD._STA) */ - - Method(_DIS ,0) { - /* DBGO("\\_SB\\LNKD\\_DIS\n") */ - Store(0, PIRD) - } /* End Method(_SB.INTD._DIS) */ - - Method(_PRS ,0) { - /* DBGO("\\_SB\\LNKD\\_PRS\n") */ - Return(IRQP) - } /* Method(_SB.INTD._PRS) */ - - Method(_CRS ,0) { - /* DBGO("\\_SB\\LNKD\\_CRS\n") */ - CreateWordField(IRQB, 0x1, IRQN) - ShiftLeft(1, PIRD, IRQN) - Return(IRQB) - } /* Method(_SB.INTD._CRS) */ - - Method(_SRS, 1) { - /* DBGO("\\_SB\\LNKD\\_CRS\n") */ - CreateWordField(ARG0, 1, IRQM) - - /* Use lowest available IRQ */ - FindSetRightBit(IRQM, Local0) - if (Local0) { - Decrement(Local0) - } - Store(Local0, PIRD) - } /* End Method(_SB.INTD._SRS) */ - } /* End Device(INTD) */ - - Device(INTE) { - Name(_HID, EISAID("PNP0C0F")) - Name(_UID, 5) - - Method(_STA, 0) { - if (PIRE) { - Return(0x0B) /* sata is invisible */ - } else { - Return(0x09) /* sata is disabled */ - } - } /* End Method(_SB.INTE._STA) */ - - Method(_DIS ,0) { - /* DBGO("\\_SB\\LNKE\\_DIS\n") */ - Store(0, PIRE) - } /* End Method(_SB.INTE._DIS) */ - - Method(_PRS ,0) { - /* DBGO("\\_SB\\LNKE\\_PRS\n") */ - Return(IRQP) - } /* Method(_SB.INTE._PRS) */ - - Method(_CRS ,0) { - /* DBGO("\\_SB\\LNKE\\_CRS\n") */ - CreateWordField(IRQB, 0x1, IRQN) - ShiftLeft(1, PIRE, IRQN) - Return(IRQB) - } /* Method(_SB.INTE._CRS) */ - - Method(_SRS, 1) { - /* DBGO("\\_SB\\LNKE\\_CRS\n") */ - CreateWordField(ARG0, 1, IRQM) - - /* Use lowest available IRQ */ - FindSetRightBit(IRQM, Local0) - if (Local0) { - Decrement(Local0) - } - Store(Local0, PIRE) - } /* End Method(_SB.INTE._SRS) */ - } /* End Device(INTE) */ - - Device(INTF) { - Name(_HID, EISAID("PNP0C0F")) - Name(_UID, 6) - - Method(_STA, 0) { - if (PIRF) { - Return(0x0B) /* sata is invisible */ - } else { - Return(0x09) /* sata is disabled */ - } - } /* End Method(_SB.INTF._STA) */ - - Method(_DIS ,0) { - /* DBGO("\\_SB\\LNKF\\_DIS\n") */ - Store(0, PIRF) - } /* End Method(_SB.INTF._DIS) */ - - Method(_PRS ,0) { - /* DBGO("\\_SB\\LNKF\\_PRS\n") */ - Return(PITF) - } /* Method(_SB.INTF._PRS) */ - - Method(_CRS ,0) { - /* DBGO("\\_SB\\LNKF\\_CRS\n") */ - CreateWordField(IRQB, 0x1, IRQN) - ShiftLeft(1, PIRF, IRQN) - Return(IRQB) - } /* Method(_SB.INTF._CRS) */ - - Method(_SRS, 1) { - /* DBGO("\\_SB\\LNKF\\_CRS\n") */ - CreateWordField(ARG0, 1, IRQM) - - /* Use lowest available IRQ */ - FindSetRightBit(IRQM, Local0) - if (Local0) { - Decrement(Local0) - } - Store(Local0, PIRF) - } /* End Method(_SB.INTF._SRS) */ - } /* End Device(INTF) */ - - Device(INTG) { - Name(_HID, EISAID("PNP0C0F")) - Name(_UID, 7) - - Method(_STA, 0) { - if (PIRG) { - Return(0x0B) /* sata is invisible */ - } else { - Return(0x09) /* sata is disabled */ - } - } /* End Method(_SB.INTG._STA) */ - - Method(_DIS ,0) { - /* DBGO("\\_SB\\LNKG\\_DIS\n") */ - Store(0, PIRG) - } /* End Method(_SB.INTG._DIS) */ - - Method(_PRS ,0) { - /* DBGO("\\_SB\\LNKG\\_PRS\n") */ - Return(IRQP) - } /* Method(_SB.INTG._CRS) */ - - Method(_CRS ,0) { - /* DBGO("\\_SB\\LNKG\\_CRS\n") */ - CreateWordField(IRQB, 0x1, IRQN) - ShiftLeft(1, PIRG, IRQN) - Return(IRQB) - } /* Method(_SB.INTG._CRS) */ - - Method(_SRS, 1) { - /* DBGO("\\_SB\\LNKG\\_CRS\n") */ - CreateWordField(ARG0, 1, IRQM) - - /* Use lowest available IRQ */ - FindSetRightBit(IRQM, Local0) - if (Local0) { - Decrement(Local0) - } - Store(Local0, PIRG) - } /* End Method(_SB.INTG._SRS) */ - } /* End Device(INTG) */ - - Device(INTH) { - Name(_HID, EISAID("PNP0C0F")) - Name(_UID, 8) - - Method(_STA, 0) { - if (PIRH) { - Return(0x0B) /* sata is invisible */ - } else { - Return(0x09) /* sata is disabled */ - } - } /* End Method(_SB.INTH._STA) */ - - Method(_DIS ,0) { - /* DBGO("\\_SB\\LNKH\\_DIS\n") */ - Store(0, PIRH) - } /* End Method(_SB.INTH._DIS) */ - - Method(_PRS ,0) { - /* DBGO("\\_SB\\LNKH\\_PRS\n") */ - Return(IRQP) - } /* Method(_SB.INTH._CRS) */ - - Method(_CRS ,0) { - /* DBGO("\\_SB\\LNKH\\_CRS\n") */ - CreateWordField(IRQB, 0x1, IRQN) - ShiftLeft(1, PIRH, IRQN) - Return(IRQB) - } /* Method(_SB.INTH._CRS) */ - - Method(_SRS, 1) { - /* DBGO("\\_SB\\LNKH\\_CRS\n") */ - CreateWordField(ARG0, 1, IRQM) - - /* Use lowest available IRQ */ - FindSetRightBit(IRQM, Local0) - if (Local0) { - Decrement(Local0) - } - Store(Local0, PIRH) - } /* End Method(_SB.INTH._SRS) */ - } /* End Device(INTH) */ - - } /* End Scope(_SB) */ - - #include - - /* Wake status package */ - Name(WKST,Package(){Zero, Zero}) - - /* - * \_PTS - Prepare to Sleep method - * - * Entry: - * Arg0=The value of the sleeping state S1=1, S2=2, etc - * - * Exit: - * -none- - * - * The _PTS control method is executed at the beginning of the sleep process - * for S1-S5. The sleeping value is passed to the _PTS control method. This - * control method may be executed a relatively long time before entering the - * sleep state and the OS may abort the operation without notification to - * the ACPI driver. This method cannot modify the configuration or power - * state of any device in the system. - */ - Method(\_PTS, 1) { - /* DBGO("\\_PTS\n") */ - /* DBGO("From S0 to S") */ - /* DBGO(Arg0) */ - /* DBGO("\n") */ - - /* Don't allow PCIRST# to reset USB */ - if (LEqual(Arg0,3)){ - Store(0,URRE) - } - - /* Clear sleep SMI status flag and enable sleep SMI trap. */ - /*Store(One, CSSM) - Store(One, SSEN)*/ - - /* On older chips, clear PciExpWakeDisEn */ - /*if (LLessEqual(\_SB.SBRI, 0x13)) { - * Store(0,\_SB.PWDE) - *} - */ - - /* Clear wake status structure. */ - Store(0, Index(WKST,0)) - Store(0, Index(WKST,1)) - } /* End Method(\_PTS) */ - - /* - * The following method results in a "not a valid reserved NameSeg" - * warning so I have commented it out for the duration. It isn't - * used, so it could be removed. - * - * - * \_GTS OEM Going To Sleep method - * - * Entry: - * Arg0=The value of the sleeping state S1=1, S2=2 - * - * Exit: - * -none- - * - * Method(\_GTS, 1) { - * DBGO("\\_GTS\n") - * DBGO("From S0 to S") - * DBGO(Arg0) - * DBGO("\n") - * } - */ - - /* - * \_BFS OEM Back From Sleep method - * - * Entry: - * Arg0=The value of the sleeping state S1=1, S2=2 - * - * Exit: - * -none- - */ - Method(\_BFS, 1) { - /* DBGO("\\_BFS\n") */ - /* DBGO("From S") */ - /* DBGO(Arg0) */ - /* DBGO(" to S0\n") */ - } - - /* - * \_WAK System Wake method - * - * Entry: - * Arg0=The value of the sleeping state S1=1, S2=2 - * - * Exit: - * Return package of 2 DWords - * Dword 1 - Status - * 0x00000000 wake succeeded - * 0x00000001 Wake was signaled but failed due to lack of power - * 0x00000002 Wake was signaled but failed due to thermal condition - * Dword 2 - Power Supply state - * if non-zero the effective S-state the power supply entered - */ - Method(\_WAK, 1) { - /* DBGO("\\_WAK\n") */ - /* DBGO("From S") */ - /* DBGO(Arg0) */ - /* DBGO(" to S0\n") */ - - /* Re-enable HPET */ - Store(1,HPDE) - - /* Restore PCIRST# so it resets USB */ - if (LEqual(Arg0,3)){ - Store(1,URRE) - } - - /* Arbitrarily clear PciExpWakeStatus */ - Store(PWST, Local1) - Store(Local1, PWST) - - /* if (DeRefOf(Index(WKST,0))) { - * Store(0, Index(WKST,1)) - * } else { - * Store(Arg0, Index(WKST,1)) - * } - */ - Return(WKST) - } /* End Method(\_WAK) */ - - Scope(\_GPE) { /* Start Scope GPE */ - /* General event 0 */ - /* Method(_L00) { - * DBGO("\\_GPE\\_L00\n") - * } - */ - - /* General event 1 */ - /* Method(_L01) { - * DBGO("\\_GPE\\_L00\n") - * } - */ - - /* General event 2 */ - /* Method(_L02) { - * DBGO("\\_GPE\\_L00\n") - * } - */ - - /* General event 3 */ - Method(_L03) { - /* DBGO("\\_GPE\\_L00\n") */ - Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ - } - - /* General event 4 */ - /* Method(_L04) { - * DBGO("\\_GPE\\_L00\n") - * } - */ - - /* General event 5 */ - /* Method(_L05) { - * DBGO("\\_GPE\\_L00\n") - * } - */ - - /* General event 6 - Used for GPM6, moved to USB.asl */ - /* Method(_L06) { - * DBGO("\\_GPE\\_L00\n") - * } - */ - - /* General event 7 - Used for GPM7, moved to USB.asl */ - /* Method(_L07) { - * DBGO("\\_GPE\\_L07\n") - * } - */ - - /* Legacy PM event */ - Method(_L08) { - /* DBGO("\\_GPE\\_L08\n") */ - } - - /* Temp warning (TWarn) event */ - Method(_L09) { - /* DBGO("\\_GPE\\_L09\n") */ - /* Notify (\_TZ.TZ00, 0x80) */ - } - - /* Reserved */ - /* Method(_L0A) { - * DBGO("\\_GPE\\_L0A\n") - * } - */ - - /* USB controller PME# */ - Method(_L0B) { - /* DBGO("\\_GPE\\_L0B\n") */ - Notify(\_SB.PCI0.UOH1, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(\_SB.PCI0.UOH2, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(\_SB.PCI0.UOH3, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(\_SB.PCI0.UOH4, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(\_SB.PCI0.UOH5, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(\_SB.PCI0.UOH6, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(\_SB.PCI0.UEH1, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ - } - - /* AC97 controller PME# */ - /* Method(_L0C) { - * DBGO("\\_GPE\\_L0C\n") - * } - */ - - /* OtherTherm PME# */ - /* Method(_L0D) { - * DBGO("\\_GPE\\_L0D\n") - * } - */ - - /* GPM9 SCI event - Moved to USB.asl */ - /* Method(_L0E) { - * DBGO("\\_GPE\\_L0E\n") - * } - */ - - /* PCIe HotPlug event */ - /* Method(_L0F) { - * DBGO("\\_GPE\\_L0F\n") - * } - */ - - /* ExtEvent0 SCI event */ - Method(_L10) { - /* DBGO("\\_GPE\\_L10\n") */ - } - - - /* ExtEvent1 SCI event */ - Method(_L11) { - /* DBGO("\\_GPE\\_L11\n") */ - } - - /* PCIe PME# event */ - /* Method(_L12) { - * DBGO("\\_GPE\\_L12\n") - * } - */ - - /* GPM0 SCI event - Moved to USB.asl */ - /* Method(_L13) { - * DBGO("\\_GPE\\_L13\n") - * } - */ - - /* GPM1 SCI event - Moved to USB.asl */ - /* Method(_L14) { - * DBGO("\\_GPE\\_L14\n") - * } - */ - - /* GPM2 SCI event - Moved to USB.asl */ - /* Method(_L15) { - * DBGO("\\_GPE\\_L15\n") - * } - */ - - /* GPM3 SCI event - Moved to USB.asl */ - /* Method(_L16) { - * DBGO("\\_GPE\\_L16\n") - * } - */ - - /* GPM8 SCI event - Moved to USB.asl */ - /* Method(_L17) { - * DBGO("\\_GPE\\_L17\n") - * } - */ - - /* GPIO0 or GEvent8 event */ - Method(_L18) { - /* DBGO("\\_GPE\\_L18\n") */ - Notify(\_SB.PCI0.PBR2, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(\_SB.PCI0.PBR4, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(\_SB.PCI0.PBR5, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(\_SB.PCI0.PBR6, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(\_SB.PCI0.PBR7, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ - } - - /* GPM4 SCI event - Moved to USB.asl */ - /* Method(_L19) { - * DBGO("\\_GPE\\_L19\n") - * } - */ - - /* GPM5 SCI event - Moved to USB.asl */ - /* Method(_L1A) { - * DBGO("\\_GPE\\_L1A\n") - * } - */ - - /* Azalia SCI event */ - Method(_L1B) { - /* DBGO("\\_GPE\\_L1B\n") */ - Notify(\_SB.PCI0.AZHD, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ - } - - /* GPM6 SCI event - Reassigned to _L06 */ - /* Method(_L1C) { - * DBGO("\\_GPE\\_L1C\n") - * } - */ - - /* GPM7 SCI event - Reassigned to _L07 */ - /* Method(_L1D) { - * DBGO("\\_GPE\\_L1D\n") - * } - */ - - /* GPIO2 or GPIO66 SCI event */ - /* Method(_L1E) { - * DBGO("\\_GPE\\_L1E\n") - * } - */ - - /* SATA SCI event - Moved to sata.asl */ - /* Method(_L1F) { - * DBGO("\\_GPE\\_L1F\n") - * } - */ - - } /* End Scope GPE */ - - #include "acpi/usb.asl" - - /* System Bus */ - Scope(\_SB) { /* Start \_SB scope */ - #include /* global utility methods expected within the \_SB scope */ - - /* _SB.PCI0 */ - /* Note: Only need HID on Primary Bus */ - Device(PCI0) { - External (TOM1) - External (TOM2) - Name(_HID, EISAID("PNP0A03")) - Name(_ADR, 0x00180000) /* Dev# = BSP Dev#, Func# = 0 */ - Method(_BBN, 0) { /* Bus number = 0 */ - Return(0) - } - Method(_STA, 0) { - /* DBGO("\\_SB\\PCI0\\_STA\n") */ - Return(0x0B) /* Status is visible */ - } - - Method(_PRT,0) { - If(PMOD){ Return(APR0) } /* APIC mode */ - Return (PR0) /* PIC Mode */ - } /* end _PRT */ - - /* Describe the Northbridge devices */ - Device(AMRT) { - Name(_ADR, 0x00000000) - } /* end AMRT */ - - /* The internal GFX bridge */ - Device(AGPB) { - Name(_ADR, 0x00010000) - Name(_PRW, Package() {0x18, 4}) - Method(_PRT,0) { - Return (APR1) - } - } /* end AGPB */ - - /* The external GFX bridge */ - Device(PBR2) { - Name(_ADR, 0x00020000) - Name(_PRW, Package() {0x18, 4}) - Method(_PRT,0) { - If(PMOD){ Return(APS2) } /* APIC mode */ - Return (PS2) /* PIC Mode */ - } /* end _PRT */ - } /* end PBR2 */ - - /* Dev3 is also an external GFX bridge, not used in Herring */ - - Device(PBR4) { - Name(_ADR, 0x00040000) - Name(_PRW, Package() {0x18, 4}) - Method(_PRT,0) { - If(PMOD){ Return(APS4) } /* APIC mode */ - Return (PS4) /* PIC Mode */ - } /* end _PRT */ - } /* end PBR4 */ - - Device(PBR5) { - Name(_ADR, 0x00050000) - Name(_PRW, Package() {0x18, 4}) - Method(_PRT,0) { - If(PMOD){ Return(APS5) } /* APIC mode */ - Return (PS5) /* PIC Mode */ - } /* end _PRT */ - } /* end PBR5 */ - - Device(PBR6) { - Name(_ADR, 0x00060000) - Name(_PRW, Package() {0x18, 4}) - Method(_PRT,0) { - If(PMOD){ Return(APS6) } /* APIC mode */ - Return (PS6) /* PIC Mode */ - } /* end _PRT */ - } /* end PBR6 */ - - /* The onboard EtherNet chip */ - Device(PBR7) { - Name(_ADR, 0x00070000) - Name(_PRW, Package() {0x18, 4}) - Method(_PRT,0) { - If(PMOD){ Return(APS7) } /* APIC mode */ - Return (PS7) /* PIC Mode */ - } /* end _PRT */ - } /* end PBR7 */ - - /* GPP */ - Device(PBR9) { - Name(_ADR, 0x00090000) - Name(_PRW, Package() {0x18, 4}) - Method(_PRT,0) { - If(PMOD){ Return(APS9) } /* APIC mode */ - Return (PS9) /* PIC Mode */ - } /* end _PRT */ - } /* end PBR9 */ - - Device(PBRa) { - Name(_ADR, 0x000A0000) - Name(_PRW, Package() {0x18, 4}) - Method(_PRT,0) { - If(PMOD){ Return(APSa) } /* APIC mode */ - Return (PSa) /* PIC Mode */ - } /* end _PRT */ - } /* end PBRa */ - - Device(PE20) { - Name(_ADR, 0x00150000) - Name(_PRW, Package() {0x18, 4}) - Method(_PRT,0) { - If(PMOD){ Return(APE0) } /* APIC mode */ - Return (PE0) /* PIC Mode */ - } /* end _PRT */ - } /* end PE20 */ - Device(PE21) { - Name(_ADR, 0x00150001) - Name(_PRW, Package() {0x18, 4}) - Method(_PRT,0) { - If(PMOD){ Return(APE1) } /* APIC mode */ - Return (PE1) /* PIC Mode */ - } /* end _PRT */ - } /* end PE21 */ - Device(PE22) { - Name(_ADR, 0x00150002) - Name(_PRW, Package() {0x18, 4}) - Method(_PRT,0) { - If(PMOD){ Return(APE2) } /* APIC mode */ - Return (APE2) /* PIC Mode */ - } /* end _PRT */ - } /* end PE22 */ - Device(PE23) { - Name(_ADR, 0x00150003) - Name(_PRW, Package() {0x18, 4}) - Method(_PRT,0) { - If(PMOD){ Return(APE3) } /* APIC mode */ - Return (PE3) /* PIC Mode */ - } /* end _PRT */ - } /* end PE23 */ - - /* PCI slot 1, 2, 3 */ - Device(PIBR) { - Name(_ADR, 0x00140004) - Name(_PRW, Package() {0x18, 4}) - - Method(_PRT, 0) { - Return (PCIB) - } - } - - /* Describe the Southbridge devices */ - Device(STCR) { - Name(_ADR, 0x00110000) - #include "acpi/sata.asl" - } /* end STCR */ - - Device(UOH1) { - Name(_ADR, 0x00120000) - Name(_PRW, Package() {0x0B, 3}) - } /* end UOH1 */ - - Device(UOH2) { - Name(_ADR, 0x00120002) - Name(_PRW, Package() {0x0B, 3}) - } /* end UOH2 */ - - Device(UOH3) { - Name(_ADR, 0x00130000) - Name(_PRW, Package() {0x0B, 3}) - } /* end UOH3 */ - - Device(UOH4) { - Name(_ADR, 0x00130002) - Name(_PRW, Package() {0x0B, 3}) - } /* end UOH4 */ - - Device(UOH5) { - Name(_ADR, 0x00160000) - Name(_PRW, Package() {0x0B, 3}) - } /* end UOH5 */ - - Device(UOH6) { - Name(_ADR, 0x00160002) - Name(_PRW, Package() {0x0B, 3}) - } /* end UOH5 */ - - Device(UEH1) { - Name(_ADR, 0x00140005) - Name(_PRW, Package() {0x0B, 3}) - } /* end UEH1 */ - - Device(SBUS) { - Name(_ADR, 0x00140000) - } /* end SBUS */ - - /* Primary (and only) IDE channel */ - Device(IDEC) { - Name(_ADR, 0x00140001) - #include "acpi/ide.asl" - } /* end IDEC */ - - Device(AZHD) { - Name(_ADR, 0x00140002) - OperationRegion(AZPD, PCI_Config, 0x00, 0x100) - Field(AZPD, AnyAcc, NoLock, Preserve) { - offset (0x42), - NSDI, 1, - NSDO, 1, - NSEN, 1, - offset (0x44), - IPCR, 4, - offset (0x54), - PWST, 2, - , 6, - PMEB, 1, - , 6, - PMST, 1, - offset (0x62), - MMCR, 1, - offset (0x64), - MMLA, 32, - offset (0x68), - MMHA, 32, - offset (0x6C), - MMDT, 16, - } - - Method(_INI) { - If(LEqual(OSVR,3)){ /* If we are running Linux */ - Store(zero, NSEN) - Store(one, NSDO) - Store(one, NSDI) - } - } - } /* end AZHD */ - - Device(LIBR) { - Name(_ADR, 0x00140003) - /* Method(_INI) { - * DBGO("\\_SB\\PCI0\\LpcIsaBr\\_INI\n") - } */ /* End Method(_SB.SBRDG._INI) */ - - /* Real Time Clock Device */ - Device(RTC0) { - Name(_HID, EISAID("PNP0B01")) /* AT Real Time Clock */ - Name(_CRS, ResourceTemplate() { - IRQNoFlags(){8} - IO(Decode16,0x0070, 0x0070, 0, 2) - /* IO(Decode16,0x0070, 0x0070, 0, 4) */ - }) - } /* End Device(_SB.PCI0.LpcIsaBr.RTC0) */ - - Device(TMR) { /* Timer */ - Name(_HID,EISAID("PNP0100")) /* System Timer */ - Name(_CRS, ResourceTemplate() { - IRQNoFlags(){0} - IO(Decode16, 0x0040, 0x0040, 0, 4) - /* IO(Decode16, 0x0048, 0x0048, 0, 4) */ - }) - } /* End Device(_SB.PCI0.LpcIsaBr.TMR) */ - - Device(SPKR) { /* Speaker */ - Name(_HID,EISAID("PNP0800")) /* AT style speaker */ - Name(_CRS, ResourceTemplate() { - IO(Decode16, 0x0061, 0x0061, 0, 1) - }) - } /* End Device(_SB.PCI0.LpcIsaBr.SPKR) */ - - Device(PIC) { - Name(_HID,EISAID("PNP0000")) /* AT Interrupt Controller */ - Name(_CRS, ResourceTemplate() { - IRQNoFlags(){2} - IO(Decode16,0x0020, 0x0020, 0, 2) - IO(Decode16,0x00A0, 0x00A0, 0, 2) - /* IO(Decode16, 0x00D0, 0x00D0, 0x10, 0x02) */ - /* IO(Decode16, 0x04D0, 0x04D0, 0x10, 0x02) */ - }) - } /* End Device(_SB.PCI0.LpcIsaBr.PIC) */ - - Device(MAD) { /* 8257 DMA */ - Name(_HID,EISAID("PNP0200")) /* Hardware Device ID */ - Name(_CRS, ResourceTemplate() { - DMA(Compatibility,BusMaster,Transfer8){4} - IO(Decode16, 0x0000, 0x0000, 0x10, 0x10) - IO(Decode16, 0x0081, 0x0081, 0x00, 0x03) - IO(Decode16, 0x0087, 0x0087, 0x00, 0x01) - IO(Decode16, 0x0089, 0x0089, 0x00, 0x03) - IO(Decode16, 0x008F, 0x008F, 0x00, 0x01) - IO(Decode16, 0x00C0, 0x00C0, 0x10, 0x20) - }) /* End Name(_SB.PCI0.LpcIsaBr.MAD._CRS) */ - } /* End Device(_SB.PCI0.LpcIsaBr.MAD) */ - - Device(COPR) { - Name(_HID,EISAID("PNP0C04")) /* Math Coprocessor */ - Name(_CRS, ResourceTemplate() { - IO(Decode16, 0x00F0, 0x00F0, 0, 0x10) - IRQNoFlags(){13} - }) - } /* End Device(_SB.PCI0.LpcIsaBr.COPR) */ -#if 0 - Device(HPTM) { - Name(_HID,EISAID("PNP0103")) - Name(CRS,ResourceTemplate() { - Memory32Fixed(ReadOnly,0xFED00000, 0x00000400, HPT) /* 1kb reserved space */ - }) - Method(_STA, 0) { - Return(0x0F) /* sata is visible */ - } - Method(_CRS, 0) { - CreateDwordField(CRS, ^HPT._BAS, HPBX) - Store(HPBA, HPBX) - Return(CRS) - } - } /* End Device(_SB.PCI0.LpcIsaBr.COPR) */ -#endif - } /* end LIBR */ - - Device(HPBR) { - Name(_ADR, 0x00140004) - } /* end HostPciBr */ - - Device(ACAD) { - Name(_ADR, 0x00140005) - } /* end Ac97audio */ - - Device(ACMD) { - Name(_ADR, 0x00140006) - } /* end Ac97modem */ - - Name(CRES, ResourceTemplate() { - IO(Decode16, 0x0CF8, 0x0CF8, 1, 8) - - WORDIO(ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, - 0x0000, /* address granularity */ - 0x0000, /* range minimum */ - 0x0CF7, /* range maximum */ - 0x0000, /* translation */ - 0x0CF8 /* length */ - ) - - WORDIO(ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, - 0x0000, /* address granularity */ - 0x0D00, /* range minimum */ - 0xFFFF, /* range maximum */ - 0x0000, /* translation */ - 0xF300 /* length */ - ) -#if 0 - Memory32Fixed(READWRITE, 0, 0xA0000, BSMM) - Memory32Fixed(READONLY, 0x000A0000, 0x00020000, VGAM) /* VGA memory space */ - Memory32Fixed(READONLY, 0x000C0000, 0x00020000, EMM1) /* Assume C0000-E0000 empty */ - Memory32Fixed(READONLY, 0x000E0000, 0x00020000, RDBS) /* BIOS ROM area */ - - /* DRAM Memory from 1MB to TopMem */ - Memory32Fixed(READWRITE, 0x00100000, 0, DMLO) /* 1MB to TopMem */ - - /* BIOS space just below 4GB */ - DWORDMemory( - ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite, - 0x00, /* Granularity */ - 0x00000000, /* Min */ - 0x00000000, /* Max */ - 0x00000000, /* Translation */ - 0x00000000, /* Max-Min, RLEN */ - ,, - PCBM - ) - - /* DRAM memory from 4GB to TopMem2 */ - QWORDMemory(ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite, - 0xFFFFFFFF, /* Granularity */ - 0x00000000, /* Min */ - 0x00000000, /* Max */ - 0x00000000, /* Translation */ - 0x00000000, /* Max-Min, RLEN */ - ,, - DMHI - ) - - /* BIOS space just below 16EB */ - QWORDMemory(ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite, - 0xFFFFFFFF, /* Granularity */ - 0x00000000, /* Min */ - 0x00000000, /* Max */ - 0x00000000, /* Translation */ - 0x00000000, /* Max-Min, RLEN */ - ,, - PEBM - ) -#endif - /* memory space for PCI BARs below 4GB */ - Memory32Fixed(ReadOnly, 0x00000000, 0x00000000, MMIO) - }) /* End Name(_SB.PCI0.CRES) */ - - Method(_CRS, 0) { - /* DBGO("\\_SB\\PCI0\\_CRS\n") */ -#if 0 - CreateDWordField(CRES, ^EMM1._BAS, EM1B) - CreateDWordField(CRES, ^EMM1._LEN, EM1L) - CreateDWordField(CRES, ^DMLO._BAS, DMLB) - CreateDWordField(CRES, ^DMLO._LEN, DMLL) - CreateDWordField(CRES, ^PCBM._MIN, PBMB) - CreateDWordField(CRES, ^PCBM._LEN, PBML) - - CreateQWordField(CRES, ^DMHI._MIN, DMHB) - CreateQWordField(CRES, ^DMHI._LEN, DMHL) - CreateQWordField(CRES, ^PEBM._MIN, EBMB) - CreateQWordField(CRES, ^PEBM._LEN, EBML) - - If(LGreater(LOMH, 0xC0000)){ - Store(0xC0000, EM1B) /* Hole above C0000 and below E0000 */ - Subtract(LOMH, 0xC0000, EM1L) /* subtract start, assumes allocation from C0000 going up */ - } - - /* Set size of memory from 1MB to TopMem */ - Subtract(TOM1, 0x100000, DMLL) - - /* - * If(LNotEqual(TOM2, 0x00000000)){ - * Store(0x100000000,DMHB) DRAM from 4GB to TopMem2 - * Subtract(TOM2, 0x100000000, DMHL) - * } - */ - - /* If there is no memory above 4GB, put the BIOS just below 4GB */ - If(LEqual(TOM2, 0x00000000)){ - Store(PBAD,PBMB) /* Reserve the "BIOS" space */ - Store(PBLN,PBML) - } - Else { /* Otherwise, put the BIOS just below 16EB */ - ShiftLeft(PBAD,16,EBMB) /* Reserve the "BIOS" space */ - Store(PBLN,EBML) - } -#endif - CreateDWordField(CRES, ^MMIO._BAS, MM1B) - CreateDWordField(CRES, ^MMIO._LEN, MM1L) - /* - * Declare memory between TOM1 and 4GB as available - * for PCI MMIO. - * Use ShiftLeft to avoid 64bit constant (for XP). - * This will work even if the OS does 32bit arithmetic, as - * 32bit (0x00000000 - TOM1) will wrap and give the same - * result as 64bit (0x100000000 - TOM1). - */ - Store(TOM1, MM1B) - ShiftLeft(0x10000000, 4, Local0) - Subtract(Local0, TOM1, Local0) - Store(Local0, MM1L) - - Return(CRES) /* note to change the Name buffer */ - } /* end of Method(_SB.PCI0._CRS) */ - - /* - * - * FIRST METHOD CALLED UPON BOOT - * - * 1. If debugging, print current OS and ACPI interpreter. - * 2. Get PCI Interrupt routing from ACPI VSM, this - * value is based on user choice in BIOS setup. - */ - Method(_INI, 0) { - /* DBGO("\\_SB\\_INI\n") */ - /* DBGO(" DSDT.ASL code from ") */ - /* DBGO(__DATE__) */ - /* DBGO(" ") */ - /* DBGO(__TIME__) */ - /* DBGO("\n Sleep states supported: ") */ - /* DBGO("\n") */ - /* DBGO(" \\_OS=") */ - /* DBGO(\_OS) */ - /* DBGO("\n \\_REV=") */ - /* DBGO(\_REV) */ - /* DBGO("\n") */ - - /* Determine the OS we're running on */ - OSFL() - - /* On older chips, clear PciExpWakeDisEn */ - /*if (LLessEqual(\SBRI, 0x13)) { - * Store(0,\PWDE) - * } - */ - } /* End Method(_SB._INI) */ - } /* End Device(PCI0) */ - - Device(PWRB) { /* Start Power button device */ - Name(_HID, EISAID("PNP0C0C")) - Name(_UID, 0xAA) - Name(_PRW, Package () {3, 0x04}) /* wake from S1-S4 */ - Name(_STA, 0x0B) /* sata is invisible */ - } - } /* End \_SB scope */ - - Scope(\_SI) { - Method(_SST, 1) { - /* DBGO("\\_SI\\_SST\n") */ - /* DBGO(" New Indicator state: ") */ - /* DBGO(Arg0) */ - /* DBGO("\n") */ - } - } /* End Scope SI */ -} -/* End of ASL file */ diff --git a/src/mainboard/amd/bimini_fam10/get_bus_conf.c b/src/mainboard/amd/bimini_fam10/get_bus_conf.c deleted file mode 100644 index 4021c51ff9..0000000000 --- a/src/mainboard/amd/bimini_fam10/get_bus_conf.c +++ /dev/null @@ -1,43 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2010 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include -#include -#include - -/* Global variables for MB layouts and these will be shared by irqtable mptable -* and acpi_tables busnum is default. -*/ -u32 apicid_sb800; - -void get_bus_conf(void) -{ - u32 apicid_base; - - get_default_pci1234(1); - - sysconf.sbdn = (sysconf.hcdn[0] & 0xff); - - pirq_router_bus = (sysconf.pci1234[0] >> 16) & 0xff; - - /* I/O APICs: APIC ID Version State Address */ - if (CONFIG(LOGICAL_CPUS)) - apicid_base = get_apicid_base(1); - else - apicid_base = CONFIG_MAX_PHYSICAL_CPUS; - apicid_sb800 = apicid_base + 0; -} diff --git a/src/mainboard/amd/bimini_fam10/irq_tables.c b/src/mainboard/amd/bimini_fam10/irq_tables.c deleted file mode 100644 index 58adb0d90e..0000000000 --- a/src/mainboard/amd/bimini_fam10/irq_tables.c +++ /dev/null @@ -1,101 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2010 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include -#include -#include -#include - -static void write_pirq_info(struct irq_info *pirq_info, u8 bus, u8 devfn, - u8 link0, u16 bitmap0, u8 link1, u16 bitmap1, - u8 link2, u16 bitmap2, u8 link3, u16 bitmap3, - u8 slot, u8 rfu) -{ - pirq_info->bus = bus; - pirq_info->devfn = devfn; - pirq_info->irq[0].link = link0; - pirq_info->irq[0].bitmap = bitmap0; - pirq_info->irq[1].link = link1; - pirq_info->irq[1].bitmap = bitmap1; - pirq_info->irq[2].link = link2; - pirq_info->irq[2].bitmap = bitmap2; - pirq_info->irq[3].link = link3; - pirq_info->irq[3].bitmap = bitmap3; - pirq_info->slot = slot; - pirq_info->rfu = rfu; -} - - -unsigned long write_pirq_routing_table(unsigned long addr) -{ - struct irq_routing_table *pirq; - struct irq_info *pirq_info; - u32 slot_num; - u8 *v; - - u8 sum = 0; - int i; - - /* Align the table to be 16 byte aligned. */ - addr += 15; - addr &= ~15; - - /* This table must be between 0xf0000 & 0x100000 */ - printk(BIOS_INFO, "Writing IRQ routing tables to 0x%lx...", addr); - - pirq = (void *)(addr); - v = (u8 *) (addr); - - pirq->signature = PIRQ_SIGNATURE; - pirq->version = PIRQ_VERSION; - - pirq->rtr_bus = pirq_router_bus; - pirq->rtr_devfn = PCI_DEVFN(0x14, 4); - - pirq->exclusive_irqs = 0; - - pirq->rtr_vendor = 0x1002; - pirq->rtr_device = 0x4384; - - pirq->miniport_data = 0; - - memset(pirq->rfu, 0, sizeof(pirq->rfu)); - - pirq_info = (void *)(&pirq->checksum + 1); - slot_num = 0; - - /* pci bridge */ - write_pirq_info(pirq_info, pirq_router_bus, PCI_DEVFN(0x14, 4), - 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, - 0); - pirq_info++; - slot_num++; - - pirq->size = 32 + 16 * slot_num; - - for (i = 0; i < pirq->size; i++) - sum += v[i]; - - sum = pirq->checksum - sum; - if (sum != pirq->checksum) { - pirq->checksum = sum; - } - - printk(BIOS_INFO, "write_pirq_routing_table done.\n"); - - return (unsigned long)pirq_info; -} diff --git a/src/mainboard/amd/bimini_fam10/mainboard.c b/src/mainboard/amd/bimini_fam10/mainboard.c deleted file mode 100644 index c8b4f63c36..0000000000 --- a/src/mainboard/amd/bimini_fam10/mainboard.c +++ /dev/null @@ -1,79 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2010 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include -#include -#include -#include -#include - -/* GPIO6. */ -static void enable_int_gfx(void) -{ - u8 byte; - - volatile u8 *gpio_reg; - - pm_iowrite(0xEA, 0x01); /* disable the PCIB */ - /* Disable Gec */ - byte = pm_ioread(0xF6); - byte |= 1; - pm_iowrite(0xF6, byte); - /* make sure the fed80000 is accessible */ - byte = pm_ioread(0x24); - byte |= 1; - pm_iowrite(0x24, byte); - - gpio_reg = (volatile u8 *)AMD_SB_ACPI_MMIO_ADDR + 0xD00; /* IoMux Register */ - - *(gpio_reg + 0x6) = 0x1; /* Int_vga_en */ - *(gpio_reg + 170) = 0x1; /* gpio_gate */ - - gpio_reg = (volatile u8 *)AMD_SB_ACPI_MMIO_ADDR + 0x100; /* GPIO Registers */ - - *(gpio_reg + 0x6) = 0x8; - *(gpio_reg + 170) = 0x0; -} - -/* - * Bimini uses GPIO 6 as PCIe slot reset, GPIO4 as GFX slot reset. We need to - * pull it up before training the slot. - * - * Old comment says: GPIO 50h to reset PCIe slot. - ***/ - -int is_dev3_present(void) -{ - return 0; -} - - -/************************************************* -* enable the dedicated function in bimini board. -* This function called early than rs780_enable. -*************************************************/ -static void mainboard_enable(struct device *dev) -{ - printk(BIOS_INFO, "Mainboard BIMINI Enable. dev=0x%p\n", dev); - - set_pcie_dereset(); - enable_int_gfx(); -} - -struct chip_operations mainboard_ops = { - .enable_dev = mainboard_enable, -}; diff --git a/src/mainboard/amd/bimini_fam10/mptable.c b/src/mainboard/amd/bimini_fam10/mptable.c deleted file mode 100644 index 84c4eda9f8..0000000000 --- a/src/mainboard/amd/bimini_fam10/mptable.c +++ /dev/null @@ -1,84 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2010 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include -#include -#include -#include - -extern u32 apicid_sb800; - -u8 intr_data[] = { - [0x00] = 0x10,0x11,0x12,0x13,0x14,0x15,0x16,0x17, /* INTA# - INTH# */ - [0x08] = 0x00,0x00,0x00,0x00,0x1F,0x1F,0x1F,0x1F, /* Misc-nil,0,1,2, INT from Serial irq */ - [0x10] = 0x1F,0x1F,0x1F,0x10,0x1F,0x12,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, - 0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, - 0x12,0x11,0x12,0x11,0x12,0x11,0x12,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, - 0x11,0x13,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, - 0x10,0x11,0x12,0x13 -}; - -static void *smp_write_config_table(void *v) -{ - struct mp_config_table *mc; - int bus_isa; - u32 dword; - u8 byte; - - mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); - - mptable_init(mc, LOCAL_APIC_ADDR); - - smp_write_processors(mc); - - mptable_write_buses(mc, NULL, &bus_isa); - - /* I/O APICs: APIC ID Version State Address */ - - dword = 0; - dword = pm_ioread(0x34) & 0xF0; - dword |= (pm_ioread(0x35) & 0xFF) << 8; - dword |= (pm_ioread(0x36) & 0xFF) << 16; - dword |= (pm_ioread(0x37) & 0xFF) << 24; - smp_write_ioapic(mc, apicid_sb800, 0x11,(void *) dword); - - for (byte = 0x0; byte < sizeof(intr_data); byte ++) { - outb(byte | 0x80, 0xC00); - outb(intr_data[byte], 0xC01); - } - - /* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ -#define IO_LOCAL_INT(type, intr, apicid, pin) \ - smp_write_intsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin)); - - mptable_add_isa_interrupts(mc, bus_isa, apicid_sb800, 0); - - /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ - IO_LOCAL_INT(mp_ExtINT, 0x0, MP_APIC_ALL, 0x0); - IO_LOCAL_INT(mp_NMI, 0x0, MP_APIC_ALL, 0x1); - /* There is no extension information... */ - - /* Compute the checksums */ - return mptable_finalize(mc); -} - -unsigned long write_smp_table(unsigned long addr) -{ - void *v; - v = smp_write_floating_table(addr, 0); - return (unsigned long)smp_write_config_table(v); -} diff --git a/src/mainboard/amd/bimini_fam10/resourcemap.c b/src/mainboard/amd/bimini_fam10/resourcemap.c deleted file mode 100644 index 47a118bbf8..0000000000 --- a/src/mainboard/amd/bimini_fam10/resourcemap.c +++ /dev/null @@ -1,274 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2010 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include - -void setup_mb_resource_map(void) -{ - static const unsigned int register_values[] = { - /* Careful set limit registers before base registers which contain the enables */ - /* DRAM Limit i Registers - * F1:0x44 i = 0 - * F1:0x4C i = 1 - * F1:0x54 i = 2 - * F1:0x5C i = 3 - * F1:0x64 i = 4 - * F1:0x6C i = 5 - * F1:0x74 i = 6 - * F1:0x7C i = 7 - * [ 2: 0] Destination Node ID - * 000 = Node 0 - * 001 = Node 1 - * 010 = Node 2 - * 011 = Node 3 - * 100 = Node 4 - * 101 = Node 5 - * 110 = Node 6 - * 111 = Node 7 - * [ 7: 3] Reserved - * [10: 8] Interleave select - * specifies the values of A[14:12] to use with interleave enable. - * [15:11] Reserved - * [31:16] DRAM Limit Address i Bits 39-24 - * This field defines the upper address bits of a 40 bit address - * that define the end of the DRAM region. - */ - /* Don't touch it, we need it for CONFIG_CAR_FAM10 */ - ADDRMAP_REG(0x4C), 0x0000f8f8, 0x00000001, - ADDRMAP_REG(0x54), 0x0000f8f8, 0x00000002, - ADDRMAP_REG(0x5C), 0x0000f8f8, 0x00000003, - ADDRMAP_REG(0x64), 0x0000f8f8, 0x00000004, - ADDRMAP_REG(0x6C), 0x0000f8f8, 0x00000005, - ADDRMAP_REG(0x74), 0x0000f8f8, 0x00000006, - ADDRMAP_REG(0x7C), 0x0000f8f8, 0x00000007, - /* DRAM Base i Registers - * F1:0x40 i = 0 - * F1:0x48 i = 1 - * F1:0x50 i = 2 - * F1:0x58 i = 3 - * F1:0x60 i = 4 - * F1:0x68 i = 5 - * F1:0x70 i = 6 - * F1:0x78 i = 7 - * [ 0: 0] Read Enable - * 0 = Reads Disabled - * 1 = Reads Enabled - * [ 1: 1] Write Enable - * 0 = Writes Disabled - * 1 = Writes Enabled - * [ 7: 2] Reserved - * [10: 8] Interleave Enable - * 000 = No interleave - * 001 = Interleave on A[12] (2 nodes) - * 010 = reserved - * 011 = Interleave on A[12] and A[14] (4 nodes) - * 100 = reserved - * 101 = reserved - * 110 = reserved - * 111 = Interleve on A[12] and A[13] and A[14] (8 nodes) - * [15:11] Reserved - * [13:16] DRAM Base Address i Bits 39-24 - * This field defines the upper address bits of a 40-bit address - * that define the start of the DRAM region. - */ - - /* don't touch it, we need it for CONFIG_CAR_FAM10 */ - ADDRMAP_REG(0x48), 0x0000f8fc, 0x00000000, - ADDRMAP_REG(0x50), 0x0000f8fc, 0x00000000, - ADDRMAP_REG(0x58), 0x0000f8fc, 0x00000000, - ADDRMAP_REG(0x60), 0x0000f8fc, 0x00000000, - ADDRMAP_REG(0x68), 0x0000f8fc, 0x00000000, - ADDRMAP_REG(0x70), 0x0000f8fc, 0x00000000, - ADDRMAP_REG(0x78), 0x0000f8fc, 0x00000000, - - /* Memory-Mapped I/O Limit i Registers - * F1:0x84 i = 0 - * F1:0x8C i = 1 - * F1:0x94 i = 2 - * F1:0x9C i = 3 - * F1:0xA4 i = 4 - * F1:0xAC i = 5 - * F1:0xB4 i = 6 - * F1:0xBC i = 7 - * [ 2: 0] Destination Node ID - * 000 = Node 0 - * 001 = Node 1 - * 010 = Node 2 - * 011 = Node 3 - * 100 = Node 4 - * 101 = Node 5 - * 110 = Node 6 - * 111 = Node 7 - * [ 3: 3] Reserved - * [ 5: 4] Destination Link ID - * 00 = Link 0 - * 01 = Link 1 - * 10 = Link 2 - * 11 = Reserved - * [ 6: 6] Reserved - * [ 7: 7] Non-Posted - * 0 = CPU writes may be posted - * 1 = CPU writes must be non-posted - * [31: 8] Memory-Mapped I/O Limit Address i (39-16) - * This field defines the upp address bits of a 40-bit address that - * defines the end of a memory-mapped I/O region n - */ - ADDRMAP_REG(0x84), 0x00000048, 0x00000000, - ADDRMAP_REG(0x8C), 0x00000048, 0x00000000, - ADDRMAP_REG(0x94), 0x00000048, 0x00000000, - ADDRMAP_REG(0x9C), 0x00000048, 0x00000000, - ADDRMAP_REG(0xA4), 0x00000048, 0x00000000, - ADDRMAP_REG(0xAC), 0x00000048, 0x00000000, - ADDRMAP_REG(0xB4), 0x00000048, 0x00000000, - - /* Memory-Mapped I/O Base i Registers - * F1:0x80 i = 0 - * F1:0x88 i = 1 - * F1:0x90 i = 2 - * F1:0x98 i = 3 - * F1:0xA0 i = 4 - * F1:0xA8 i = 5 - * F1:0xB0 i = 6 - * F1:0xB8 i = 7 - * [ 0: 0] Read Enable - * 0 = Reads disabled - * 1 = Reads Enabled - * [ 1: 1] Write Enable - * 0 = Writes disabled - * 1 = Writes Enabled - * [ 2: 2] Cpu Disable - * 0 = Cpu can use this I/O range - * 1 = Cpu requests do not use this I/O range - * [ 3: 3] Lock - * 0 = base/limit registers i are read/write - * 1 = base/limit registers i are read-only - * [ 7: 4] Reserved - * [31: 8] Memory-Mapped I/O Base Address i (39-16) - * This field defines the upper address bits of a 40bit address - * that defines the start of memory-mapped I/O region i - */ - ADDRMAP_REG(0x80), 0x000000f0, 0x00000000, - ADDRMAP_REG(0x88), 0x000000f0, 0x00000000, - ADDRMAP_REG(0x90), 0x000000f0, 0x00000000, - ADDRMAP_REG(0x98), 0x000000f0, 0x00000000, - ADDRMAP_REG(0xA0), 0x000000f0, 0x00000000, - ADDRMAP_REG(0xA8), 0x000000f0, 0x00000000, - ADDRMAP_REG(0xB0), 0x000000f0, 0x00000000, - - /* PCI I/O Limit i Registers - * F1:0xC4 i = 0 - * F1:0xCC i = 1 - * F1:0xD4 i = 2 - * F1:0xDC i = 3 - * [ 2: 0] Destination Node ID - * 000 = Node 0 - * 001 = Node 1 - * 010 = Node 2 - * 011 = Node 3 - * 100 = Node 4 - * 101 = Node 5 - * 110 = Node 6 - * 111 = Node 7 - * [ 3: 3] Reserved - * [ 5: 4] Destination Link ID - * 00 = Link 0 - * 01 = Link 1 - * 10 = Link 2 - * 11 = reserved - * [11: 6] Reserved - * [24:12] PCI I/O Limit Address i - * This field defines the end of PCI I/O region n - * [31:25] Reserved - */ - ADDRMAP_REG(0xCC), 0xFE000FC8, 0x00000000, - ADDRMAP_REG(0xD4), 0xFE000FC8, 0x00000000, - ADDRMAP_REG(0xDC), 0xFE000FC8, 0x00000000, - - /* PCI I/O Base i Registers - * F1:0xC0 i = 0 - * F1:0xC8 i = 1 - * F1:0xD0 i = 2 - * F1:0xD8 i = 3 - * [ 0: 0] Read Enable - * 0 = Reads Disabled - * 1 = Reads Enabled - * [ 1: 1] Write Enable - * 0 = Writes Disabled - * 1 = Writes Enabled - * [ 3: 2] Reserved - * [ 4: 4] VGA Enable - * 0 = VGA matches Disabled - * 1 = matches all address < 64K and where A[9:0] is in the - * range 3B0-3BB or 3C0-3DF independen of the base & limit registers - * [ 5: 5] ISA Enable - * 0 = ISA matches Disabled - * 1 = Blocks address < 64K and in the last 768 bytes of eack 1K block - * from matching agains this base/limit pair - * [11: 6] Reserved - * [24:12] PCI I/O Base i - * This field defines the start of PCI I/O region n - * [31:25] Reserved - */ - ADDRMAP_REG(0xC8), 0xFE000FCC, 0x00000000, - ADDRMAP_REG(0xD0), 0xFE000FCC, 0x00000000, - ADDRMAP_REG(0xD8), 0xFE000FCC, 0x00000000, - - /* Config Base and Limit i Registers - * F1:0xE0 i = 0 - * F1:0xE4 i = 1 - * F1:0xE8 i = 2 - * F1:0xEC i = 3 - * [ 0: 0] Read Enable - * 0 = Reads Disabled - * 1 = Reads Enabled - * [ 1: 1] Write Enable - * 0 = Writes Disabled - * 1 = Writes Enabled - * [ 2: 2] Device Number Compare Enable - * 0 = The ranges are based on bus number - * 1 = The ranges are ranges of devices on bus 0 - * [ 3: 3] Reserved - * [ 6: 4] Destination Node - * 000 = Node 0 - * 001 = Node 1 - * 010 = Node 2 - * 011 = Node 3 - * 100 = Node 4 - * 101 = Node 5 - * 110 = Node 6 - * 111 = Node 7 - * [ 7: 7] Reserved - * [ 9: 8] Destination Link - * 00 = Link 0 - * 01 = Link 1 - * 10 = Link 2 - * 11 - Reserved - * [15:10] Reserved - * [23:16] Bus Number Base i - * This field defines the lowest bus number in configuration region i - * [31:24] Bus Number Limit i - * This field defines the highest bus number in configuration regin i - */ - /* AMD 8111 on link0 of CPU 0 */ - ADDRMAP_REG(0xE4), 0x0000FC88, 0x00000000, - ADDRMAP_REG(0xE8), 0x0000FC88, 0x00000000, - ADDRMAP_REG(0xEC), 0x0000FC88, 0x00000000, - }; - - int max; - max = ARRAY_SIZE(register_values); - setup_resource_map(register_values, max); -} diff --git a/src/mainboard/amd/bimini_fam10/romstage.c b/src/mainboard/amd/bimini_fam10/romstage.c deleted file mode 100644 index 909f33ec93..0000000000 --- a/src/mainboard/amd/bimini_fam10/romstage.c +++ /dev/null @@ -1,219 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2010 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#define SYSTEM_TYPE 1 /* SERVER = 0, DESKTOP = 1, MOBILE = 2 */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include "southbridge/amd/sb800/early_setup.c" -#include - -#include "cpu/amd/quadcore/quadcore.c" - -int spd_read_byte(unsigned int device, unsigned int address); - - -int spd_read_byte(u32 device, u32 address) -{ - return do_smbus_read_byte(SMBUS_IO_BASE, device, address); -} - -void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) -{ - struct sys_info *sysinfo = get_sysinfo(); - static const u8 spd_addr[] = {RC00, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, }; - u32 bsp_apicid = 0, val; - msr_t msr; - - timestamp_init(timestamp_get()); - timestamp_add_now(TS_START_ROMSTAGE); - - if (!cpu_init_detectedx && boot_cpu()) { - /* Nothing special needs to be done to find bus 0 */ - /* Allow the HT devices to be found */ - /* mov bsp to bus 0xff when > 8 nodes */ - set_bsp_node_CHtExtNodeCfgEn(); - enumerate_ht_chain(); - - /* enable port80 decoding and southbridge poweron init */ - sb800_lpc_port80(); - inb(0x80); /* Wait sometime before post to port80, otherwise reset was needed. */ - } - - post_code(0x30); - - if (bist == 0) { - bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo); /* mmconf is inited in init_cpus */ - /* All cores run this but the BSP(node0,core0) is the only core that returns. */ - } - - post_code(0x32); - - enable_rs780_dev8(); - sb800_lpc_init(); - - console_init(); - - - /* Halt if there was a built in self test failure */ - report_bist_failure(bist); - - /* Load MPB */ - val = cpuid_eax(1); - printk(BIOS_DEBUG, "BSP Family_Model: %08x\n", val); - printk(BIOS_DEBUG, "*sysinfo range: [%p,%p]\n",sysinfo,sysinfo+1); - printk(BIOS_DEBUG, "bsp_apicid = %02x\n", bsp_apicid); - printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx); - - /* Setup sysinfo defaults */ - set_sysinfo_in_ram(0); - - update_microcode(val); - - post_code(0x33); - - cpuSetAMDMSR(0); - post_code(0x34); - - amd_ht_init(sysinfo); - post_code(0x35); - - /* Setup nodes PCI space and start core 0 AP init. */ - finalize_node_setup(sysinfo); - - /* Setup any mainboard PCI settings etc. */ - setup_mb_resource_map(); - post_code(0x36); - - /* wait for all the APs core0 started by finalize_node_setup. */ - /* FIXME: A bunch of cores are going to start output to serial at once. - It would be nice to fixup prink spinlocks for ROM XIP mode. - I think it could be done by putting the spinlock flag in the cache - of the BSP located right after sysinfo. - */ - wait_all_core0_started(); - -#if CONFIG(LOGICAL_CPUS) - /* Core0 on each node is configured. Now setup any additional cores. */ - printk(BIOS_DEBUG, "start_other_cores()\n"); - start_other_cores(bsp_apicid); - post_code(0x37); - wait_all_other_cores_started(bsp_apicid); -#endif - - post_code(0x38); - - /* run _early_setup before soft-reset. */ - rs780_early_setup(); - sb800_early_setup(); - -#if CONFIG(SET_FIDVID) - msr = rdmsr(MSR_COFVID_STS); - printk(BIOS_DEBUG, "\nBegin FIDVID MSR 0xc0010071 0x%08x 0x%08x\n", msr.hi, msr.lo); - - /* FIXME: The sb fid change may survive the warm reset and only - need to be done once.*/ - enable_fid_change_on_sb(sysinfo->sbbusn, sysinfo->sbdn); - - post_code(0x39); - - if (!warm_reset_detect(0)) { /* BSP is node 0 */ - init_fidvid_bsp(bsp_apicid, sysinfo->nodes); - } else { - init_fidvid_stage2(bsp_apicid, 0); /* BSP is node 0 */ - } - - post_code(0x3A); - - /* show final fid and vid */ - msr = rdmsr(MSR_COFVID_STS); - printk(BIOS_DEBUG, "End FIDVIDMSR 0xc0010071 0x%08x 0x%08x\n", msr.hi, msr.lo); -#endif - - rs780_htinit(); - - /* Reset for HT, FIDVID, PLL and errata changes to take affect. */ - if (!warm_reset_detect(0)) { - printk(BIOS_INFO, "...WARM RESET...\n\n\n"); - soft_reset(); - die("After soft_reset - shouldn't see this message!!!\n"); - } - - post_code(0x3B); - - /* It's the time to set ctrl in sysinfo now; */ - printk(BIOS_DEBUG, "fill_mem_ctrl()\n"); - fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr); - - post_code(0x40); - - raminit_amdmct(sysinfo); - - cbmem_initialize_empty(); - post_code(0x41); - - amdmct_cbmem_store_info(sysinfo); - - sb800_before_pci_init(); - - post_code(0x42); -} - -/** - * BOOL AMD_CB_ManualBUIDSwapList(u8 Node, u8 Link, u8 **List) - * Description: - * This routine is called every time a non-coherent chain is processed. - * BUID assignment may be controlled explicitly on a non-coherent chain. Provide a - * swap list. The first part of the list controls the BUID assignment and the - * second part of the list provides the device to device linking. Device orientation - * can be detected automatically, or explicitly. See documentation for more details. - * - * Automatic non-coherent init assigns BUIDs starting at 1 and incrementing sequentially - * based on each device's unit count. - * - * Parameters: - * @param[in] node = The node on which this chain is located - * @param[in] link = The link on the host for this chain - * @param[out] List = supply a pointer to a list - */ -BOOL AMD_CB_ManualBUIDSwapList (u8 node, u8 link, const u8 **List) -{ - static const u8 swaplist[] = { 0xFF, CONFIG_HT_CHAIN_UNITID_BASE, CONFIG_HT_CHAIN_END_UNITID_BASE, 0xFF }; - /* If the BUID was adjusted in early_ht we need to do the manual override */ - if ((node == 0) && (link == 0)) { /* BSP SB link */ - *List = swaplist; - return 1; - } - - return 0; -} diff --git a/src/mainboard/amd/mahogany_fam10/Kconfig b/src/mainboard/amd/mahogany_fam10/Kconfig deleted file mode 100644 index afe98fa93f..0000000000 --- a/src/mainboard/amd/mahogany_fam10/Kconfig +++ /dev/null @@ -1,58 +0,0 @@ -if BOARD_AMD_MAHOGANY_FAM10 - -config BOARD_SPECIFIC_OPTIONS - def_bool y - select CPU_AMD_SOCKET_AM2R2 - select DIMM_DDR2 - select DIMM_REGISTERED - select NORTHBRIDGE_AMD_AMDFAM10 - select SOUTHBRIDGE_AMD_RS780 - select SOUTHBRIDGE_AMD_SB700 - select SUPERIO_ITE_IT8718F - select HAVE_OPTION_TABLE - select HAVE_PIRQ_TABLE - select HAVE_MP_TABLE - select SB_HT_CHAIN_UNITID_OFFSET_ONLY - select LIFT_BSP_APIC_ID - select HAVE_ACPI_TABLES - select BOARD_ROMSIZE_KB_1024 - select ENABLE_APIC_EXT_ID - select GFXUMA - -config MAINBOARD_DIR - string - default amd/mahogany_fam10 - -config APIC_ID_OFFSET - hex - default 0x0 - -config MAINBOARD_PART_NUMBER - string - default "Mahogany (Fam10)" - -config MAX_CPUS - int - default 8 - -config MAX_PHYSICAL_CPUS - int - default 2 - -config HT_CHAIN_END_UNITID_BASE - hex - default 0x1 - -config HT_CHAIN_UNITID_BASE - hex - default 0x0 - -config IRQ_SLOT_COUNT - int - default 11 - -config VGA_BIOS_ID - string - default "1002,9615" - -endif # BOARD_AMD_MAHOGANY_FAM10 diff --git a/src/mainboard/amd/mahogany_fam10/Kconfig.name b/src/mainboard/amd/mahogany_fam10/Kconfig.name deleted file mode 100644 index c2d42a9e4e..0000000000 --- a/src/mainboard/amd/mahogany_fam10/Kconfig.name +++ /dev/null @@ -1,2 +0,0 @@ -config BOARD_AMD_MAHOGANY_FAM10 - bool "Mahogany (Fam10)" diff --git a/src/mainboard/amd/mahogany_fam10/Makefile.inc b/src/mainboard/amd/mahogany_fam10/Makefile.inc deleted file mode 100644 index 91d4b39c32..0000000000 --- a/src/mainboard/amd/mahogany_fam10/Makefile.inc +++ /dev/null @@ -1,16 +0,0 @@ -# -# This file is part of the coreboot project. -# -# This program is free software; you can redistribute it and/or modify -# it under the terms of the GNU General Public License as published by -# the Free Software Foundation; version 2 of the License. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# - -romstage-y += resourcemap.c - -ramstage-y += get_bus_conf.c diff --git a/src/mainboard/amd/mahogany_fam10/acpi/cpstate.asl b/src/mainboard/amd/mahogany_fam10/acpi/cpstate.asl deleted file mode 100644 index acaa5bae32..0000000000 --- a/src/mainboard/amd/mahogany_fam10/acpi/cpstate.asl +++ /dev/null @@ -1,80 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2010 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -/* This file defines the processor and performance state capability - * for each core in the system. It is included into the DSDT for each - * core. It assumes that each core of the system has the same performance - * characteristics. -*/ -/* -#include -DefinitionBlock ("DSDT.AML", "DSDT", 0x01, OEM_ID, ACPI_TABLE_CREATOR, 0x00010001) - { - Scope (\_PR) { - Device (CPU0) { - Name (_HID, "ACPI0007") - Name (_UID, 0) - #include "cpstate.asl" - } - Device (CPU1) { - Name (_HID, "ACPI0007") - Name (_UID, 1) - #include "cpstate.asl" - } - Device (CPU2) { - Name (_HID, "ACPI0007") - Name (_UID, 2) - #include "cpstate.asl" - } - Device (CPU3) { - Name (_HID, "ACPI0007") - Name (_UID, 3) - #include "cpstate.asl" - } - } -*/ - /* P-state support: The maximum number of P-states supported by the */ - /* CPUs we'll use is 6. */ - /* Get from AMI BIOS. */ - Name(_PSS, Package(){ - Package () - { - 0x00000AF0, - 0x0000BF81, - 0x00000002, - 0x00000002, - 0x00000000, - 0x00000000 - }, - - Package () - { - 0x00000578, - 0x000076F2, - 0x00000002, - 0x00000002, - 0x00000001, - 0x00000001 - } - }) - - Name(_PCT, Package(){ - ResourceTemplate(){Register(FFixedHW, 0, 0, 0)}, - ResourceTemplate(){Register(FFixedHW, 0, 0, 0)} - }) - - Method(_PPC, 0){ - Return(0) - } diff --git a/src/mainboard/amd/mahogany_fam10/acpi/ide.asl b/src/mainboard/amd/mahogany_fam10/acpi/ide.asl deleted file mode 100644 index 5c155cf301..0000000000 --- a/src/mainboard/amd/mahogany_fam10/acpi/ide.asl +++ /dev/null @@ -1,240 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2010 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -/* -Scope (_SB) { - Device(PCI0) { - Device(IDEC) { - Name(_ADR, 0x00140001) - #include "ide.asl" - } - } -} -*/ - -/* Some timing tables */ -Name(UDTT, Package(){ /* Udma timing table */ - 120, 90, 60, 45, 30, 20, 15, 0 /* UDMA modes 0 -> 6 */ -}) - -Name(MDTT, Package(){ /* MWDma timing table */ - 480, 150, 120, 0 /* Legacy DMA modes 0 -> 2 */ -}) - -Name(POTT, Package(){ /* Pio timing table */ - 600, 390, 270, 180, 120, 0 /* PIO modes 0 -> 4 */ -}) - -/* Some timing register value tables */ -Name(MDRT, Package(){ /* MWDma timing register table */ - 0x77, 0x21, 0x20, 0xFF /* Legacy DMA modes 0 -> 2 */ -}) - -Name(PORT, Package(){ - 0x99, 0x47, 0x34, 0x22, 0x20, 0x99 /* PIO modes 0 -> 4 */ -}) - -OperationRegion(ICRG, PCI_Config, 0x40, 0x20) /* ide control registers */ - Field(ICRG, AnyAcc, NoLock, Preserve) -{ - PPTS, 8, /* Primary PIO Slave Timing */ - PPTM, 8, /* Primary PIO Master Timing */ - OFFSET(0x04), PMTS, 8, /* Primary MWDMA Slave Timing */ - PMTM, 8, /* Primary MWDMA Master Timing */ - OFFSET(0x08), PPCR, 8, /* Primary PIO Control */ - OFFSET(0x0A), PPMM, 4, /* Primary PIO master Mode */ - PPSM, 4, /* Primary PIO slave Mode */ - OFFSET(0x14), PDCR, 2, /* Primary UDMA Control */ - OFFSET(0x16), PDMM, 4, /* Primary UltraDMA Mode */ - PDSM, 4, /* Primary UltraDMA Mode */ -} - -Method(GTTM, 1) /* get total time*/ -{ - Store(And(Arg0, 0x0F), Local0) /* Recovery Width */ - Increment(Local0) - Store(ShiftRight(Arg0, 4), Local1) /* Command Width */ - Increment(Local1) - Return(Multiply(30, Add(Local0, Local1))) -} - -Device(PRID) -{ - Name (_ADR, Zero) - Method(_GTM, 0) - { - NAME(OTBF, Buffer(20) { /* out buffer */ - 0xFF, 0xFF, 0xFF, 0xFF, - 0xFF, 0xFF, 0xFF, 0xFF, - 0xFF, 0xFF, 0xFF, 0xFF, - 0xFF, 0xFF, 0xFF, 0xFF, 0x00, 0x00, 0x00, 0x00 - }) - - CreateDwordField(OTBF, 0, PSD0) /* PIO spd0 */ - CreateDwordField(OTBF, 4, DSD0) /* DMA spd0 */ - CreateDwordField(OTBF, 8, PSD1) /* PIO spd1 */ - CreateDwordField(OTBF, 12, DSD1) /* DMA spd1 */ - CreateDwordField(OTBF, 16, BFFG) /* buffer flags */ - - /* Just return if the channel is disabled */ - If(And(PPCR, 0x01)) { /* primary PIO control */ - Return(OTBF) - } - - /* Always tell them independent timing available and IOChannelReady used on both drives */ - Or(BFFG, 0x1A, BFFG) - - Store(GTTM(PPTM), PSD0) /* save total time of primary PIO master timming to PIO spd0 */ - Store(GTTM(PPTS), PSD1) /* save total time of primary PIO slave Timing to PIO spd1 */ - - If(And(PDCR, 0x01)) { /* It's under UDMA mode */ - Or(BFFG, 0x01, BFFG) - Store(DerefOf(Index(UDTT, PDMM)), DSD0) - } - Else { - Store(GTTM(PMTM), DSD0) /* Primary MWDMA Master Timing, DmaSpd0 */ - } - - If(And(PDCR, 0x02)) { /* It's under UDMA mode */ - Or(BFFG, 0x04, BFFG) - Store(DerefOf(Index(UDTT, PDSM)), DSD1) - } - Else { - Store(GTTM(PMTS), DSD1) /* Primary MWDMA Slave Timing, DmaSpd0 */ - } - - Return(OTBF) /* out buffer */ - } /* End Method(_GTM) */ - - Method(_STM, 3, NotSerialized) - { - NAME(INBF, Buffer(20) { /* in buffer */ - 0xFF, 0xFF, 0xFF, 0xFF, - 0xFF, 0xFF, 0xFF, 0xFF, - 0xFF, 0xFF, 0xFF, 0xFF, - 0xFF, 0xFF, 0xFF, 0xFF, 0x00, 0x00, 0x00, 0x00 - }) - - CreateDwordField(INBF, 0, PSD0) /* PIO spd0 */ - CreateDwordField(INBF, 4, DSD0) /* PIO spd0 */ - CreateDwordField(INBF, 8, PSD1) /* PIO spd1 */ - CreateDwordField(INBF, 12, DSD1) /* DMA spd1 */ - CreateDwordField(INBF, 16, BFFG) /*buffer flag */ - - Store(Match(POTT, MLE, PSD0, MTR, 0, 0), Local0) - Divide(Local0, 5, PPMM,) /* Primary PIO master Mode */ - Store(Match(POTT, MLE, PSD1, MTR, 0, 0), Local1) - Divide(Local1, 5, PPSM,) /* Primary PIO slave Mode */ - - Store(DerefOf(Index(PORT, Local0)), PPTM) /* Primary PIO Master Timing */ - Store(DerefOf(Index(PORT, Local1)), PPTS) /* Primary PIO Slave Timing */ - - If(And(BFFG, 0x01)) { /* Drive 0 is under UDMA mode */ - Store(Match(UDTT, MLE, DSD0, MTR, 0, 0), Local0) - Divide(Local0, 7, PDMM,) - Or(PDCR, 0x01, PDCR) - } - Else { - If(LNotEqual(DSD0, 0xFFFFFFFF)) { - Store(Match(MDTT, MLE, DSD0, MTR, 0, 0), Local0) - Store(DerefOf(Index(MDRT, Local0)), PMTM) - } - } - - If(And(BFFG, 0x04)) { /* Drive 1 is under UDMA mode */ - Store(Match(UDTT, MLE, DSD1, MTR, 0, 0), Local0) - Divide(Local0, 7, PDSM,) - Or(PDCR, 0x02, PDCR) - } - Else { - If(LNotEqual(DSD1, 0xFFFFFFFF)) { - Store(Match(MDTT, MLE, DSD1, MTR, 0, 0), Local0) - Store(DerefOf(Index(MDRT, Local0)), PMTS) - } - } - /* Return(INBF) */ - } /*End Method(_STM) */ - Device(MST) - { - Name(_ADR, 0) - Method(_GTF) { - Name(CMBF, Buffer(21) { - 0x03, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xEF, - 0x03, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xEF, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xF5 - }) - CreateByteField(CMBF, 1, POMD) - CreateByteField(CMBF, 8, DMMD) - CreateByteField(CMBF, 5, CMDA) - CreateByteField(CMBF, 12, CMDB) - CreateByteField(CMBF, 19, CMDC) - - Store(0xA0, CMDA) - Store(0xA0, CMDB) - Store(0xA0, CMDC) - - Or(PPMM, 0x08, POMD) - - If(And(PDCR, 0x01)) { - Or(PDMM, 0x40, DMMD) - } - Else { - Store(Match - (MDTT, MLE, GTTM(PMTM), - MTR, 0, 0), Local0) - If(LLess(Local0, 3)) { - Or(0x20, Local0, DMMD) - } - } - Return(CMBF) - } - } /* End Device(MST) */ - - Device(SLAV) - { - Name(_ADR, 1) - Method(_GTF) { - Name(CMBF, Buffer(21) { - 0x03, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xEF, - 0x03, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xEF, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xF5 - }) - CreateByteField(CMBF, 1, POMD) - CreateByteField(CMBF, 8, DMMD) - CreateByteField(CMBF, 5, CMDA) - CreateByteField(CMBF, 12, CMDB) - CreateByteField(CMBF, 19, CMDC) - - Store(0xB0, CMDA) - Store(0xB0, CMDB) - Store(0xB0, CMDC) - - Or(PPSM, 0x08, POMD) - - If(And(PDCR, 0x02)) { - Or(PDSM, 0x40, DMMD) - } - Else { - Store(Match - (MDTT, MLE, GTTM(PMTS), - MTR, 0, 0), Local0) - If(LLess(Local0, 3)) { - Or(0x20, Local0, DMMD) - } - } - Return(CMBF) - } - } /* End Device(SLAV) */ -} diff --git a/src/mainboard/amd/mahogany_fam10/acpi/routing.asl b/src/mainboard/amd/mahogany_fam10/acpi/routing.asl deleted file mode 100644 index 4c3075c368..0000000000 --- a/src/mainboard/amd/mahogany_fam10/acpi/routing.asl +++ /dev/null @@ -1,334 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2010 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -/* -#include -DefinitionBlock ("DSDT.AML", "DSDT", 0x01, OEM_ID, ACPI_TABLE_CREATOR, 0x00010001 - ) - { - #include "routing.asl" - } -*/ - -/* Routing is in System Bus scope */ -Scope(\_SB) { - Name(PR0, Package(){ - /* NB devices */ - /* Bus 0, Dev 0 - RS780 Host Controller */ - /* Bus 0, Dev 1 - PCI Bridge for Internal Graphics */ - Package(){0x0001FFFF, 0, INTC, 0 }, - Package(){0x0001FFFF, 1, INTD, 0 }, - /* Bus 0, Dev 2 - PCIe Bridge for x8 PCIe Slot (GFX0) */ - Package(){0x0002FFFF, 0, INTC, 0 }, - Package(){0x0002FFFF, 1, INTD, 0 }, - Package(){0x0002FFFF, 2, INTA, 0 }, - Package(){0x0002FFFF, 3, INTB, 0 }, - /* Bus 0, Dev 3 - PCIe graphics port 1 bridge */ - /* Bus 0, Dev 4 - PCIe Bridge for Express Card Slot */ - Package(){0x0004FFFF, 0, INTA, 0 }, - Package(){0x0004FFFF, 1, INTB, 0 }, - Package(){0x0004FFFF, 2, INTC, 0 }, - Package(){0x0004FFFF, 3, INTD, 0 }, - /* Bus 0, Dev 5 - General purpose PCIe bridge 5 */ - /* Package(){0x0005FFFF, 0, INTB, 0 }, */ - /* Package(){0x0005FFFF, 1, INTC, 0 }, */ - /* Package(){0x0005FFFF, 2, INTD, 0 }, */ - /* Package(){0x0005FFFF, 3, INTA, 0 }, */ - /* Bus 0, Dev 6 - PCIe Bridge for Ethernet Chip */ - Package(){0x0006FFFF, 0, INTC, 0 }, - Package(){0x0006FFFF, 1, INTD, 0 }, - Package(){0x0006FFFF, 2, INTA, 0 }, - Package(){0x0006FFFF, 3, INTB, 0 }, - /* Bus 0, Dev 7 - PCIe Bridge for x1 PCIe Slot */ - Package(){0x0007FFFF, 0, INTD, 0 }, - Package(){0x0007FFFF, 1, INTA, 0 }, - Package(){0x0007FFFF, 2, INTB, 0 }, - Package(){0x0007FFFF, 3, INTC, 0 }, - - Package(){0x0009FFFF, 0, INTB, 0 }, - Package(){0x0009FFFF, 1, INTC, 0 }, - Package(){0x0009FFFF, 2, INTD, 0 }, - Package(){0x0009FFFF, 3, INTA, 0 }, - - Package(){0x000AFFFF, 0, INTC, 0 }, - Package(){0x000AFFFF, 1, INTD, 0 }, - Package(){0x000AFFFF, 2, INTA, 0 }, - Package(){0x000AFFFF, 3, INTB, 0 }, - - Package(){0x000BFFFF, 0, INTD, 0 }, - Package(){0x000BFFFF, 1, INTA, 0 }, - Package(){0x000BFFFF, 2, INTB, 0 }, - Package(){0x000BFFFF, 3, INTC, 0 }, - - Package(){0x000CFFFF, 0, INTA, 0 }, - Package(){0x000CFFFF, 1, INTB, 0 }, - Package(){0x000CFFFF, 2, INTC, 0 }, - Package(){0x000CFFFF, 3, INTD, 0 }, - - /* Bus 0, Funct 8 - Southbridge port (normally hidden) */ - - /* SB devices */ - /* Bus 0, Dev 17 - SATA controller #2 */ - /* Bus 0, Dev 18 - SATA controller #1 */ - Package(){0x0011FFFF, 0, INTG, 0 }, - - /* Bus 0, Dev 19 - USB: OHCI, dev 18,19 func 0-2, dev 20 func 5; - * EHCI, dev 18, 19 func 2 */ - Package(){0x0012FFFF, 0, INTA, 0 }, - Package(){0x0012FFFF, 1, INTB, 0 }, - Package(){0x0012FFFF, 2, INTC, 0 }, - Package(){0x0012FFFF, 3, INTD, 0 }, - - Package(){0x0013FFFF, 0, INTC, 0 }, - Package(){0x0013FFFF, 1, INTD, 0 }, - Package(){0x0013FFFF, 2, INTA, 0 }, - Package(){0x0013FFFF, 3, INTB, 0 }, - - /* Package(){0x0014FFFF, 1, INTA, 0 }, */ - - /* Bus 0, Dev 20 - F0:SMBus/ACPI,F1:IDE;F2:HDAudio;F3:LPC;F4:PCIBridge;F5:USB */ - Package(){0x0014FFFF, 0, INTA, 0 }, - Package(){0x0014FFFF, 1, INTB, 0 }, - Package(){0x0014FFFF, 2, INTC, 0 }, - Package(){0x0014FFFF, 3, INTD, 0 }, - -/* Package(){0x0015FFFF, 0, INTA, 0 }, - Package(){0x0015FFFF, 1, INTB, 0 }, - Package(){0x0015FFFF, 2, INTC, 0 }, - Package(){0x0015FFFF, 3, INTD, 0 }, -*/ - }) - - Name(APR0, Package(){ - /* NB devices in APIC mode */ - /* Bus 0, Dev 0 - RS780 Host Controller */ - - /* Bus 0, Dev 1 - PCI Bridge for Internal Graphics */ - /* Package(){0x0001FFFF, 0, 0, 18 }, */ - /* Package(){0x0001FFFF, 1, 0, 19 }, */ - - /* Bus 0, Dev 2 - PCIe Bridge for x8 PCIe Slot (GFX0) */ - Package(){0x0002FFFF, 0, 0, 18 }, - /* Package(){0x0002FFFF, 1, 0, 19 }, */ - /* Package(){0x0002FFFF, 2, 0, 16 }, */ - /* Package(){0x0002FFFF, 3, 0, 17 }, */ - - /* Bus 0, Dev 3 - PCIe graphics port 1 bridge */ - Package(){0x0003FFFF, 0, 0, 19 }, - - /* Bus 0, Dev 4 - PCIe Bridge for Express Card Slot */ - Package(){0x0004FFFF, 0, 0, 16 }, - /* Package(){0x0004FFFF, 1, 0, 17 }, */ - /* Package(){0x0004FFFF, 2, 0, 18 }, */ - /* Package(){0x0004FFFF, 3, 0, 19 }, */ - - /* Bus 0, Dev 5 - General purpose PCIe bridge 5 */ - /* Package(){0x0005FFFF, 0, 0, 17 }, */ - /* Package(){0x0005FFFF, 1, 0, 18 }, */ - /* Package(){0x0005FFFF, 2, 0, 19 }, */ - /* Package(){0x0005FFFF, 3, 0, 16 }, */ - - /* Bus 0, Dev 6 - General purpose PCIe bridge 6 */ - /* Package(){0x0006FFFF, 0, 0, 18 }, */ - /* Package(){0x0006FFFF, 1, 0, 19 }, */ - /* Package(){0x0006FFFF, 2, 0, 16 }, */ - /* Package(){0x0006FFFF, 3, 0, 17 }, */ - - /* Bus 0, Dev 7 - PCIe Bridge for network card */ - /* Package(){0x0007FFFF, 0, 0, 19 }, */ - /* Package(){0x0007FFFF, 1, 0, 16 }, */ - /* Package(){0x0007FFFF, 2, 0, 17 }, */ - /* Package(){0x0007FFFF, 3, 0, 18 }, */ - - /* Bus 0, Dev 9 - PCIe Bridge for network card */ - Package(){0x0009FFFF, 0, 0, 17 }, - /* Package(){0x0009FFFF, 1, 0, 16 }, */ - /* Package(){0x0009FFFF, 2, 0, 17 }, */ - /* Package(){0x0009FFFF, 3, 0, 18 }, */ - - /* Bus 0, Dev A - PCIe Bridge for network card */ - Package(){0x000AFFFF, 0, 0, 18 }, - /* Package(){0x000AFFFF, 1, 0, 16 }, */ - /* Package(){0x000AFFFF, 2, 0, 17 }, */ - /* Package(){0x000AFFFF, 3, 0, 18 }, */ - - /* Bus 0, Funct 8 - Southbridge port (normally hidden) */ - - /* SB devices in APIC mode */ - /* Bus 0, Dev 17 - SATA controller #2 */ - /* Bus 0, Dev 18 - SATA controller #1 */ - Package(){0x0011FFFF, 0, 0, 22 }, - - /* Bus 0, Dev 19 - USB: OHCI, dev 18,19 func 0-2, dev 20 func 5; - * EHCI, dev 18, 19 func 2 */ - Package(){0x0012FFFF, 0, 0, 16 }, - Package(){0x0012FFFF, 1, 0, 17 }, - Package(){0x0012FFFF, 2, 0, 18 }, - Package(){0x0012FFFF, 3, 0, 19 }, - - Package(){0x0013FFFF, 0, 0, 18 }, - Package(){0x0013FFFF, 1, 0, 19 }, - Package(){0x0013FFFF, 2, 0, 16 }, - Package(){0x0013FFFF, 3, 0, 17 }, - - /* Bus 0, Dev 20 - F0:SMBus/ACPI, F1:IDE; F2:HDAudio; F3:LPC; F4:PCIBridge; F5:USB */ - Package(){0x0014FFFF, 0, 0, 16 }, - Package(){0x0014FFFF, 1, 0, 17 }, - Package(){0x0014FFFF, 2, 0, 18 }, - Package(){0x0014FFFF, 3, 0, 19 }, - }) - - Name(PR1, Package(){ - /* Internal graphics - RS780 VGA, Bus1, Dev5 */ - Package(){0x0005FFFF, 0, INTC, 0 }, - Package(){0x0005FFFF, 1, INTD, 0 }, - Package(){0x0005FFFF, 2, INTA, 0 }, - Package(){0x0005FFFF, 3, INTB, 0 }, - }) - - Name(APR1, Package(){ - /* Internal graphics - RS780 VGA, Bus1, Dev5 */ - Package(){0x0005FFFF, 0, 0, 18 }, - Package(){0x0005FFFF, 1, 0, 19 }, - Package(){0x0005FFFF, 2, 0, 16 }, - Package(){0x0005FFFF, 3, 0, 17 }, - }) - - Name(PS2, Package(){ - /* The external GFX - Hooked to PCIe slot 2 */ - Package(){0x0000FFFF, 0, INTC, 0 }, - Package(){0x0000FFFF, 1, INTD, 0 }, - Package(){0x0000FFFF, 2, INTA, 0 }, - Package(){0x0000FFFF, 3, INTB, 0 }, - }) - - Name(APS2, Package(){ - /* The external GFX - Hooked to PCIe slot 2 */ - Package(){0x0000FFFF, 0, 0, 18 }, - Package(){0x0000FFFF, 1, 0, 19 }, - Package(){0x0000FFFF, 2, 0, 16 }, - Package(){0x0000FFFF, 3, 0, 17 }, - }) - - Name(PS4, Package(){ - /* PCIe slot - Hooked to PCIe slot 4 */ - Package(){0x0000FFFF, 0, INTD, 0 }, - Package(){0x0000FFFF, 1, INTA, 0 }, - Package(){0x0000FFFF, 2, INTB, 0 }, - Package(){0x0000FFFF, 3, INTC, 0 }, - }) - - Name(APS4, Package(){ - /* PCIe slot - Hooked to PCIe slot 4 */ - Package(){0x0000FFFF, 0, 0, 16 }, - Package(){0x0000FFFF, 1, 0, 17 }, - Package(){0x0000FFFF, 2, 0, 18 }, - Package(){0x0000FFFF, 3, 0, 19 }, - }) - - Name(PS5, Package(){ - /* PCIe slot - Hooked to PCIe slot 5 */ - Package(){0x0000FFFF, 0, INTB, 0 }, - Package(){0x0000FFFF, 1, INTC, 0 }, - Package(){0x0000FFFF, 2, INTD, 0 }, - Package(){0x0000FFFF, 3, INTA, 0 }, - }) - - Name(APS5, Package(){ - /* PCIe slot - Hooked to PCIe slot 5 */ - Package(){0x0000FFFF, 0, 0, 17 }, - Package(){0x0000FFFF, 1, 0, 18 }, - Package(){0x0000FFFF, 2, 0, 19 }, - Package(){0x0000FFFF, 3, 0, 16 }, - }) - - Name(PS6, Package(){ - /* PCIe slot - Hooked to PCIe slot 6 */ - Package(){0x0000FFFF, 0, INTC, 0 }, - Package(){0x0000FFFF, 1, INTD, 0 }, - Package(){0x0000FFFF, 2, INTA, 0 }, - Package(){0x0000FFFF, 3, INTB, 0 }, - }) - - Name(APS6, Package(){ - /* PCIe slot - Hooked to PCIe slot 6 */ - Package(){0x0000FFFF, 0, 0, 18 }, - Package(){0x0000FFFF, 1, 0, 19 }, - Package(){0x0000FFFF, 2, 0, 16 }, - Package(){0x0000FFFF, 3, 0, 17 }, - }) - - Name(PS7, Package(){ - /* The onboard Ethernet chip - Hooked to PCIe slot 7 */ - Package(){0x0000FFFF, 0, INTD, 0 }, - Package(){0x0000FFFF, 1, INTA, 0 }, - Package(){0x0000FFFF, 2, INTB, 0 }, - Package(){0x0000FFFF, 3, INTC, 0 }, - }) - - Name(APS7, Package(){ - /* The onboard Ethernet chip - Hooked to PCIe slot 7 */ - Package(){0x0000FFFF, 0, 0, 19 }, - Package(){0x0000FFFF, 1, 0, 16 }, - Package(){0x0000FFFF, 2, 0, 17 }, - Package(){0x0000FFFF, 3, 0, 18 }, - }) - Name(PS9, Package(){ - /* PCIe slot - Hooked to PCIe slot 9 */ - Package(){0x0000FFFF, 0, INTD, 0 }, - Package(){0x0000FFFF, 1, INTA, 0 }, - Package(){0x0000FFFF, 2, INTB, 0 }, - Package(){0x0000FFFF, 3, INTC, 0 }, - }) - - Name(APS9, Package(){ - /* PCIe slot - Hooked to PCIe slot 9 */ - Package(){0x0000FFFF, 0, 0, 19 }, - Package(){0x0000FFFF, 1, 0, 16 }, - Package(){0x0000FFFF, 2, 0, 17 }, - Package(){0x0000FFFF, 3, 0, 18 }, - }) - Name(PSa, Package(){ - /* PCIe slot - Hooked to PCIe slot 10 */ - Package(){0x0000FFFF, 0, INTD, 0 }, - Package(){0x0000FFFF, 1, INTA, 0 }, - Package(){0x0000FFFF, 2, INTB, 0 }, - Package(){0x0000FFFF, 3, INTC, 0 }, - }) - - Name(APSa, Package(){ - /* PCIe slot - Hooked to PCIe slot 10 */ - Package(){0x0000FFFF, 0, 0, 18 }, - Package(){0x0000FFFF, 1, 0, 16 }, - Package(){0x0000FFFF, 2, 0, 17 }, - Package(){0x0000FFFF, 3, 0, 18 }, - }) - - Name(PCIB, Package(){ - /* PCI slots: slot 0, slot 1, slot 2 behind Dev14, Fun4. */ - Package(){0x0005FFFF, 0, 0, 0x14 }, - Package(){0x0005FFFF, 1, 0, 0x15 }, - Package(){0x0005FFFF, 2, 0, 0x16 }, - Package(){0x0005FFFF, 3, 0, 0x17 }, - Package(){0x0006FFFF, 0, 0, 0x15 }, - Package(){0x0006FFFF, 1, 0, 0x16 }, - Package(){0x0006FFFF, 2, 0, 0x17 }, - Package(){0x0006FFFF, 3, 0, 0x14 }, - Package(){0x0007FFFF, 0, 0, 0x16 }, - Package(){0x0007FFFF, 1, 0, 0x17 }, - Package(){0x0007FFFF, 2, 0, 0x14 }, - Package(){0x0007FFFF, 3, 0, 0x15 }, - }) -} diff --git a/src/mainboard/amd/mahogany_fam10/acpi/sata.asl b/src/mainboard/amd/mahogany_fam10/acpi/sata.asl deleted file mode 100644 index cb9b221ba3..0000000000 --- a/src/mainboard/amd/mahogany_fam10/acpi/sata.asl +++ /dev/null @@ -1,145 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2010 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -/* simple name description */ - -/* -Scope (_SB) { - Device(PCI0) { - Device(SATA) { - Name(_ADR, 0x00110000) - #include "sata.asl" - } - } -} -*/ - -Name(STTM, Buffer(20) { - 0x78, 0x00, 0x00, 0x00, 0x0f, 0x00, 0x00, 0x00, - 0x78, 0x00, 0x00, 0x00, 0x0f, 0x00, 0x00, 0x00, - 0x1f, 0x00, 0x00, 0x00 -}) - -/* Start by clearing the PhyRdyChg bits */ -Method(_INI) { - \_GPE._L1F() -} - -Device(PMRY) -{ - Name(_ADR, 0) - Method(_GTM, 0x0, NotSerialized) { - Return(STTM) - } - Method(_STM, 0x3, NotSerialized) {} - - Device(PMST) { - Name(_ADR, 0) - Method(_STA,0) { - if (LGreater(P0IS,0)) { - return (0x0F) /* sata is visible */ - } - else { - return (0x00) /* sata is missing */ - } - } - }/* end of PMST */ - - Device(PSLA) - { - Name(_ADR, 1) - Method(_STA,0) { - if (LGreater(P1IS,0)) { - return (0x0F) /* sata is visible */ - } - else { - return (0x00) /* sata is missing */ - } - } - } /* end of PSLA */ -} /* end of PMRY */ - - -Device(SEDY) -{ - Name(_ADR, 1) /* IDE Scondary Channel */ - Method(_GTM, 0x0, NotSerialized) { - Return(STTM) - } - Method(_STM, 0x3, NotSerialized) {} - - Device(SMST) - { - Name(_ADR, 0) - Method(_STA,0) { - if (LGreater(P2IS,0)) { - return (0x0F) /* sata is visible */ - } - else { - return (0x00) /* sata is missing */ - } - } - } /* end of SMST */ - - Device(SSLA) - { - Name(_ADR, 1) - Method(_STA,0) { - if (LGreater(P3IS,0)) { - return (0x0F) /* sata is visible */ - } - else { - return (0x00) /* sata is missing */ - } - } - } /* end of SSLA */ -} /* end of SEDY */ - -/* SATA Hot Plug Support */ -Scope(\_GPE) { - Method(_L1F,0x0,NotSerialized) { - if (\_SB.P0PR) { - if (LGreater(\_SB.P0IS,0)) { - sleep(32) - } - Notify(\_SB.PCI0.STCR.PMRY.PMST, 0x01) /* NOTIFY_DEVICE_CHECK */ - store(one, \_SB.P0PR) - } - - if (\_SB.P1PR) { - if (LGreater(\_SB.P1IS,0)) { - sleep(32) - } - Notify(\_SB.PCI0.STCR.PMRY.PSLA, 0x01) /* NOTIFY_DEVICE_CHECK */ - store(one, \_SB.P1PR) - } - - if (\_SB.P2PR) { - if (LGreater(\_SB.P2IS,0)) { - sleep(32) - } - Notify(\_SB.PCI0.STCR.SEDY.SMST, 0x01) /* NOTIFY_DEVICE_CHECK */ - store(one, \_SB.P2PR) - } - - if (\_SB.P3PR) { - if (LGreater(\_SB.P3IS,0)) { - sleep(32) - } - Notify(\_SB.PCI0.STCR.SEDY.SSLA, 0x01) /* NOTIFY_DEVICE_CHECK */ - store(one, \_SB.P3PR) - } - } -} diff --git a/src/mainboard/amd/mahogany_fam10/acpi/usb.asl b/src/mainboard/amd/mahogany_fam10/acpi/usb.asl deleted file mode 100644 index a3ccb97ff9..0000000000 --- a/src/mainboard/amd/mahogany_fam10/acpi/usb.asl +++ /dev/null @@ -1,158 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2010 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -/* simple name description */ -/* -#include -DefinitionBlock ("DSDT.AML", "DSDT", 0x01, OEM_ID, ACPI_TABLE_CREATOR, 0x00010001 - ) - { - #include "usb.asl" - } -*/ -Method(UCOC, 0) { - Sleep(20) - Store(0x13,CMTI) - Store(0,GPSL) -} - -/* USB Port 0 overcurrent uses Gpm 0 */ -If(LLessEqual(UOM0,9)) { - Scope (\_GPE) { - Method (_L13) { - UCOC() - if(LEqual(GPB0,PLC0)) { - Not(PLC0,PLC0) - Store(PLC0, \_SB.PT0D) - } - } - } -} - -/* USB Port 1 overcurrent uses Gpm 1 */ -If (LLessEqual(UOM1,9)) { - Scope (\_GPE) { - Method (_L14) { - UCOC() - if (LEqual(GPB1,PLC1)) { - Not(PLC1,PLC1) - Store(PLC1, \_SB.PT1D) - } - } - } -} - -/* USB Port 2 overcurrent uses Gpm 2 */ -If (LLessEqual(UOM2,9)) { - Scope (\_GPE) { - Method (_L15) { - UCOC() - if (LEqual(GPB2,PLC2)) { - Not(PLC2,PLC2) - Store(PLC2, \_SB.PT2D) - } - } - } -} - -/* USB Port 3 overcurrent uses Gpm 3 */ -If (LLessEqual(UOM3,9)) { - Scope (\_GPE) { - Method (_L16) { - UCOC() - if (LEqual(GPB3,PLC3)) { - Not(PLC3,PLC3) - Store(PLC3, \_SB.PT3D) - } - } - } -} - -/* USB Port 4 overcurrent uses Gpm 4 */ -If (LLessEqual(UOM4,9)) { - Scope (\_GPE) { - Method (_L19) { - UCOC() - if (LEqual(GPB4,PLC4)) { - Not(PLC4,PLC4) - Store(PLC4, \_SB.PT4D) - } - } - } -} - -/* USB Port 5 overcurrent uses Gpm 5 */ -If (LLessEqual(UOM5,9)) { - Scope (\_GPE) { - Method (_L1A) { - UCOC() - if (LEqual(GPB5,PLC5)) { - Not(PLC5,PLC5) - Store(PLC5, \_SB.PT5D) - } - } - } -} - -/* USB Port 6 overcurrent uses Gpm 6 */ -If (LLessEqual(UOM6,9)) { - Scope (\_GPE) { - /* Method (_L1C) { */ - Method (_L06) { - UCOC() - if (LEqual(GPB6,PLC6)) { - Not(PLC6,PLC6) - Store(PLC6, \_SB.PT6D) - } - } - } -} - -/* USB Port 7 overcurrent uses Gpm 7 */ -If (LLessEqual(UOM7,9)) { - Scope (\_GPE) { - /* Method (_L1D) { */ - Method (_L07) { - UCOC() - if (LEqual(GPB7,PLC7)) { - Not(PLC7,PLC7) - Store(PLC7, \_SB.PT7D) - } - } - } -} - -/* USB Port 8 overcurrent uses Gpm 8 */ -If (LLessEqual(UOM8,9)) { - Scope (\_GPE) { - Method (_L17) { - if (LEqual(G8IS,PLC8)) { - Not(PLC8,PLC8) - Store(PLC8, \_SB.PT8D) - } - } - } -} - -/* USB Port 9 overcurrent uses Gpm 9 */ -If (LLessEqual(UOM9,9)) { - Scope (\_GPE) { - Method (_L0E) { - if (LEqual(G9IS,0)) { - Store(1,\_SB.PT9D) - } - } - } -} diff --git a/src/mainboard/amd/mahogany_fam10/acpi_tables.c b/src/mainboard/amd/mahogany_fam10/acpi_tables.c deleted file mode 100644 index 6cdf89ac26..0000000000 --- a/src/mainboard/amd/mahogany_fam10/acpi_tables.c +++ /dev/null @@ -1,44 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2010-2011 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include -#include - -unsigned long acpi_fill_madt(unsigned long current) -{ - /* create all subtables for processors */ - current = acpi_create_madt_lapics(current); - - /* Write SB700 IOAPIC, only one */ - current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, - CONFIG_MAX_CPUS, IO_APIC_ADDR, 0); - - current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) - current, 0, 0, 2, 0); - current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) - current, 0, 9, 9, 0xF); - /* 0: mean bus 0--->ISA */ - /* 0: PIC 0 */ - /* 2: APIC 2 */ - /* 5 mean: 0101 --> Edge-triggered, Active high */ - - /* create all subtables for processors */ - /* current = acpi_create_madt_lapic_nmis(current, 5, 1); */ - /* 1: LINT1 connect to NMI */ - - return current; -} diff --git a/src/mainboard/amd/mahogany_fam10/board_info.txt b/src/mainboard/amd/mahogany_fam10/board_info.txt deleted file mode 100644 index b351b8e696..0000000000 --- a/src/mainboard/amd/mahogany_fam10/board_info.txt +++ /dev/null @@ -1 +0,0 @@ -Category: eval diff --git a/src/mainboard/amd/mahogany_fam10/cmos.layout b/src/mainboard/amd/mahogany_fam10/cmos.layout deleted file mode 100644 index 6c3d3f6c9e..0000000000 --- a/src/mainboard/amd/mahogany_fam10/cmos.layout +++ /dev/null @@ -1,52 +0,0 @@ -entries - -0 384 r 0 reserved_memory -384 1 e 4 boot_option -388 4 h 0 reboot_counter -#392 3 r 0 unused -395 1 e 1 hw_scrubber -396 1 e 1 interleave_chip_selects -397 2 e 8 max_mem_clock -399 1 e 2 multi_core -400 1 e 1 power_on_after_fail -412 4 e 6 debug_level -440 4 e 9 slow_cpu -444 1 e 1 nmi -445 1 e 1 gart -456 1 e 1 ECC_memory -728 256 h 0 user_data -984 16 h 0 check_sum -# Reserve the extended AMD configuration registers -1000 24 r 0 amd_reserved - - - -enumerations - -#ID value text -1 0 Disable -1 1 Enable -2 0 Enable -2 1 Disable -4 0 Fallback -4 1 Normal -6 5 Notice -6 6 Info -6 7 Debug -6 8 Spew -8 0 400Mhz -8 1 333Mhz -8 2 266Mhz -8 3 200Mhz -9 0 off -9 1 87.5% -9 2 75.0% -9 3 62.5% -9 4 50.0% -9 5 37.5% -9 6 25.0% -9 7 12.5% - -checksums - -checksum 392 983 984 diff --git a/src/mainboard/amd/mahogany_fam10/devicetree.cb b/src/mainboard/amd/mahogany_fam10/devicetree.cb deleted file mode 100644 index dba1470f33..0000000000 --- a/src/mainboard/amd/mahogany_fam10/devicetree.cb +++ /dev/null @@ -1,129 +0,0 @@ -# sample config for amd/mahogany_fam10 -chip northbridge/amd/amdfam10/root_complex - device cpu_cluster 0 on - chip cpu/amd/socket_AM2r2 #L1 and DDR2 - device lapic 0 on end - end - end - device domain 0 on - subsystemid 0x1022 0x3060 inherit - chip northbridge/amd/amdfam10 - device pci 18.0 on # northbridge - chip southbridge/amd/rs780 - device pci 0.0 on end # HT 0x9600 - device pci 1.0 on end # Internal Graphics P2P bridge 0x9602 - device pci 2.0 on end # PCIE P2P bridge (external graphics) 0x9603 - device pci 3.0 on end # PCIE P2P bridge 0x960b - device pci 4.0 on end # PCIE P2P bridge 0x9604 - device pci 5.0 off end # PCIE P2P bridge 0x9605 - device pci 6.0 off end # PCIE P2P bridge 0x9606 - device pci 7.0 off end # PCIE P2P bridge 0x9607 - device pci 8.0 off end # NB/SB Link P2P bridge - device pci 9.0 on end # - device pci a.0 on end # - register "gppsb_configuration" = "1" # Configuration B - register "gpp_configuration" = "3" # Configuration D default - register "port_enable" = "0x6fc" - register "gfx_dev2_dev3" = "1" - register "gfx_dual_slot" = "1" - register "gfx_lane_reversal" = "0" - register "gfx_tmds" = "0" - register "gfx_compliance" = "0" - register "gfx_reconfiguration" = "1" - register "gfx_link_width" = "0" - end - chip southbridge/amd/sb700 # it is under NB/SB Link, but on the same pri bus - device pci 11.0 on end # SATA - device pci 12.0 on end # USB - device pci 12.1 on end # USB - device pci 12.2 on end # USB - device pci 13.0 on end # USB - device pci 13.1 on end # USB - device pci 13.2 on end # USB - device pci 14.0 on # SM - chip drivers/generic/generic #dimm 0-0-0 - device i2c 50 on end - end - chip drivers/generic/generic #dimm 0-0-1 - device i2c 51 on end - end - chip drivers/generic/generic #dimm 0-1-0 - device i2c 52 on end - end - chip drivers/generic/generic #dimm 0-1-1 - device i2c 53 on end - end - end # SM - device pci 14.1 on end # IDE 0x439c - device pci 14.2 on end # HDA 0x4383 - device pci 14.3 on # LPC 0x439d - chip superio/ite/it8718f - device pnp 2e.0 off # Floppy - io 0x60 = 0x3f0 - irq 0x70 = 6 - drq 0x74 = 2 - end - device pnp 2e.1 on # Com1 - io 0x60 = 0x3f8 - irq 0x70 = 4 - end - device pnp 2e.2 off # Com2 - io 0x60 = 0x2f8 - irq 0x70 = 3 - end - device pnp 2e.3 off # Parallel Port - io 0x60 = 0x378 - irq 0x70 = 7 - end - device pnp 2e.4 off end # EC - device pnp 2e.5 on # Keyboard - io 0x60 = 0x60 - io 0x62 = 0x64 - irq 0x70 = 1 - end - device pnp 2e.6 on # Mouse - irq 0x70 = 12 - end - device pnp 2e.7 off # GPIO, must be closed for unresolved reason. - end - device pnp 2e.8 off # MIDI - io 0x60 = 0x300 - irq 0x70 = 9 - end - device pnp 2e.9 off # GAME - io 0x60 = 0x220 - end - device pnp 2e.a off end # CIR - end #superio/ite/it8718f - end #LPC - device pci 14.4 on end # PCI 0x4384 - device pci 14.5 on end # USB 2 - register "boot_switch_sata_ide" = "0" # 0: boot from SATA. 1: IDE - end #southbridge/amd/sb700 - end # device pci 18.0 - - device pci 18.0 on end - device pci 18.0 on end - device pci 18.1 on end - device pci 18.2 on end - device pci 18.3 on end - device pci 18.4 on end -# device pci 00.5 on end - end - end #domain - #for node 32 to node 63 -# device domain 0 on -# chip northbridge/amd/amdfam10 -# device pci 00.0 on end# northbridge -# device pci 00.0 on end -# device pci 00.0 on end -# device pci 00.0 on end -# device pci 00.1 on end -# device pci 00.2 on end -# device pci 00.3 on end -# device pci 00.4 on end -# device pci 00.5 on end -# end -# end #domain - -end diff --git a/src/mainboard/amd/mahogany_fam10/dsdt.asl b/src/mainboard/amd/mahogany_fam10/dsdt.asl deleted file mode 100644 index 63748d7e01..0000000000 --- a/src/mainboard/amd/mahogany_fam10/dsdt.asl +++ /dev/null @@ -1,1736 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2010 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -/* DefinitionBlock Statement */ -#include -DefinitionBlock ( - "DSDT.AML", /* Output filename */ - "DSDT", /* Signature */ - 0x02, /* DSDT Revision, needs to be 2 for 64bit */ - OEM_ID, - ACPI_TABLE_CREATOR, - 0x00010001 /* OEM Revision */ - ) -{ /* Start of ASL file */ - /* #include */ /* Include global debug methods if needed */ - - /* Data to be patched by the BIOS during POST */ - /* FIXME the patching is not done yet! */ - /* Memory related values */ - Name(LOMH, 0x0) /* Start of unused memory in C0000-E0000 range */ - Name(PBAD, 0x0) /* Address of BIOS area (If TOM2 != 0, Addr >> 16) */ - Name(PBLN, 0x0) /* Length of BIOS area */ - - Name(PCBA, CONFIG_MMCONF_BASE_ADDRESS) /* Base address of PCIe config space */ - Name(HPBA, 0xFED00000) /* Base address of HPET table */ - - /* USB overcurrent mapping pins. */ - Name(UOM0, 0) - Name(UOM1, 2) - Name(UOM2, 0) - Name(UOM3, 7) - Name(UOM4, 2) - Name(UOM5, 2) - Name(UOM6, 6) - Name(UOM7, 2) - Name(UOM8, 6) - Name(UOM9, 6) - - /* Some global data */ - Name(OSVR, 3) /* Assume nothing. WinXp = 1, Vista = 2, Linux = 3, WinCE = 4 */ - Name(OSV, Ones) /* Assume nothing */ - Name(PMOD, One) /* Assume APIC */ - - /* - * Processor Object - * - */ - Scope (\_PR) { /* define processor scope */ - Device (CPU0) { - Name (_HID, "ACPI0007") - Name (_UID, 0) - #include "acpi/cpstate.asl" - } - Device (CPU1) { - Name (_HID, "ACPI0007") - Name (_UID, 1) - #include "acpi/cpstate.asl" - } - Device (CPU2) { - Name (_HID, "ACPI0007") - Name (_UID, 2) - #include "acpi/cpstate.asl" - } - Device (CPU3) { - Name (_HID, "ACPI0007") - Name (_UID, 3) - #include "acpi/cpstate.asl" - } - } /* End _PR scope */ - - /* PIC IRQ mapping registers, C00h-C01h */ - OperationRegion(PRQM, SystemIO, 0x00000C00, 0x00000002) - Field(PRQM, ByteAcc, NoLock, Preserve) { - PRQI, 0x00000008, - PRQD, 0x00000008, /* Offset: 1h */ - } - IndexField(PRQI, PRQD, ByteAcc, NoLock, Preserve) { - PINA, 0x00000008, /* Index 0 */ - PINB, 0x00000008, /* Index 1 */ - PINC, 0x00000008, /* Index 2 */ - PIND, 0x00000008, /* Index 3 */ - AINT, 0x00000008, /* Index 4 */ - SINT, 0x00000008, /* Index 5 */ - , 0x00000008, /* Index 6 */ - AAUD, 0x00000008, /* Index 7 */ - AMOD, 0x00000008, /* Index 8 */ - PINE, 0x00000008, /* Index 9 */ - PINF, 0x00000008, /* Index A */ - PING, 0x00000008, /* Index B */ - PINH, 0x00000008, /* Index C */ - } - - /* PCI Error control register */ - OperationRegion(PERC, SystemIO, 0x00000C14, 0x00000001) - Field(PERC, ByteAcc, NoLock, Preserve) { - SENS, 0x00000001, - PENS, 0x00000001, - SENE, 0x00000001, - PENE, 0x00000001, - } - - /* Client Management index/data registers */ - OperationRegion(CMT, SystemIO, 0x00000C50, 0x00000002) - Field(CMT, ByteAcc, NoLock, Preserve) { - CMTI, 8, - /* Client Management Data register */ - G64E, 1, - G64O, 1, - G32O, 2, - , 2, - GPSL, 2, - } - - /* GPM Port register */ - OperationRegion(GPT, SystemIO, 0x00000C52, 0x00000001) - Field(GPT, ByteAcc, NoLock, Preserve) { - GPB0,1, - GPB1,1, - GPB2,1, - GPB3,1, - GPB4,1, - GPB5,1, - GPB6,1, - GPB7,1, - } - - /* Flash ROM program enable register */ - OperationRegion(FRE, SystemIO, 0x00000C6F, 0x00000001) - Field(FRE, ByteAcc, NoLock, Preserve) { - , 0x00000006, - FLRE, 0x00000001, - } - - /* PM2 index/data registers */ - OperationRegion(PM2R, SystemIO, 0x00000CD0, 0x00000002) - Field(PM2R, ByteAcc, NoLock, Preserve) { - PM2I, 0x00000008, - PM2D, 0x00000008, - } - - /* Power Management I/O registers */ - OperationRegion(PIOR, SystemIO, 0x00000CD6, 0x00000002) - Field(PIOR, ByteAcc, NoLock, Preserve) { - PIOI, 0x00000008, - PIOD, 0x00000008, - } - IndexField (PIOI, PIOD, ByteAcc, NoLock, Preserve) { - Offset(0x00), /* MiscControl */ - , 1, - T1EE, 1, - T2EE, 1, - Offset(0x01), /* MiscStatus */ - , 1, - T1E, 1, - T2E, 1, - Offset(0x04), /* SmiWakeUpEventEnable3 */ - , 7, - SSEN, 1, - Offset(0x07), /* SmiWakeUpEventStatus3 */ - , 7, - CSSM, 1, - Offset(0x10), /* AcpiEnable */ - , 6, - PWDE, 1, - Offset(0x1C), /* ProgramIoEnable */ - , 3, - MKME, 1, - IO3E, 1, - IO2E, 1, - IO1E, 1, - IO0E, 1, - Offset(0x1D), /* IOMonitorStatus */ - , 3, - MKMS, 1, - IO3S, 1, - IO2S, 1, - IO1S, 1, - IO0S,1, - Offset(0x20), /* AcpiPmEvtBlk */ - APEB, 16, - Offset(0x36), /* GEvtLevelConfig */ - , 6, - ELC6, 1, - ELC7, 1, - Offset(0x37), /* GPMLevelConfig0 */ - , 3, - PLC0, 1, - PLC1, 1, - PLC2, 1, - PLC3, 1, - PLC8, 1, - Offset(0x38), /* GPMLevelConfig1 */ - , 1, - PLC4, 1, - PLC5, 1, - , 1, - PLC6, 1, - PLC7, 1, - Offset(0x3B), /* PMEStatus1 */ - GP0S, 1, - GM4S, 1, - GM5S, 1, - APS, 1, - GM6S, 1, - GM7S, 1, - GP2S, 1, - STSS, 1, - Offset(0x55), /* SoftPciRst */ - SPRE, 1, - , 1, - , 1, - PNAT, 1, - PWMK, 1, - PWNS, 1, - - /* Offset(0x61), */ /* Options_1 */ - /* ,7, */ - /* R617,1, */ - - Offset(0x65), /* UsbPMControl */ - , 4, - URRE, 1, - Offset(0x68), /* MiscEnable68 */ - , 3, - TMTE, 1, - , 1, - Offset(0x92), /* GEVENTIN */ - , 7, - E7IS, 1, - Offset(0x96), /* GPM98IN */ - G8IS, 1, - G9IS, 1, - Offset(0x9A), /* EnhanceControl */ - ,7, - HPDE, 1, - Offset(0xA8), /* PIO7654Enable */ - IO4E, 1, - IO5E, 1, - IO6E, 1, - IO7E, 1, - Offset(0xA9), /* PIO7654Status */ - IO4S, 1, - IO5S, 1, - IO6S, 1, - IO7S, 1, - } - - /* PM1 Event Block - * First word is PM1_Status, Second word is PM1_Enable - */ - OperationRegion(P1EB, SystemIO, APEB, 0x04) - Field(P1EB, ByteAcc, NoLock, Preserve) { - TMST, 1, - , 3, - BMST, 1, - GBST, 1, - Offset(0x01), - PBST, 1, - , 1, - RTST, 1, - , 3, - PWST, 1, - SPWS, 1, - Offset(0x02), - TMEN, 1, - , 4, - GBEN, 1, - Offset(0x03), - PBEN, 1, - , 1, - RTEN, 1, - , 3, - PWDA, 1, - } - - Scope(\_SB) { - /* PCIe Configuration Space for 16 busses */ - OperationRegion(PCFG, SystemMemory, PCBA, 0x01000000) /* Each bus consumes 1MB */ - Field(PCFG, ByteAcc, NoLock, Preserve) { - /* Byte offsets are computed using the following technique: - * ((bus number + 1) * ((device number * 8) * 4096)) + register offset - * The 8 comes from 8 functions per device, and 4096 bytes per function config space - */ - Offset(0x00088024), /* Byte offset to SATA register 24h - Bus 0, Device 17, Function 0 */ - STB5, 32, - Offset(0x00098042), /* Byte offset to OHCI0 register 42h - Bus 0, Device 19, Function 0 */ - PT0D, 1, - PT1D, 1, - PT2D, 1, - PT3D, 1, - PT4D, 1, - PT5D, 1, - PT6D, 1, - PT7D, 1, - PT8D, 1, - PT9D, 1, - Offset(0x000A0004), /* Byte offset to SMBUS register 4h - Bus 0, Device 20, Function 0 */ - SBIE, 1, - SBME, 1, - Offset(0x000A0008), /* Byte offset to SMBUS register 8h - Bus 0, Device 20, Function 0 */ - SBRI, 8, - Offset(0x000A0014), /* Byte offset to SMBUS register 14h - Bus 0, Device 20, Function 0 */ - SBB1, 32, - Offset(0x000A0078), /* Byte offset to SMBUS register 78h - Bus 0, Device 20, Function 0 */ - ,14, - P92E, 1, /* Port92 decode enable */ - } - - OperationRegion(SB5, SystemMemory, STB5, 0x1000) - Field(SB5, AnyAcc, NoLock, Preserve){ - /* Port 0 */ - Offset(0x120), /* Port 0 Task file status */ - P0ER, 1, - , 2, - P0DQ, 1, - , 3, - P0BY, 1, - Offset(0x128), /* Port 0 Serial ATA status */ - P0DD, 4, - , 4, - P0IS, 4, - Offset(0x12C), /* Port 0 Serial ATA control */ - P0DI, 4, - Offset(0x130), /* Port 0 Serial ATA error */ - , 16, - P0PR, 1, - - /* Port 1 */ - offset(0x1A0), /* Port 1 Task file status */ - P1ER, 1, - , 2, - P1DQ, 1, - , 3, - P1BY, 1, - Offset(0x1A8), /* Port 1 Serial ATA status */ - P1DD, 4, - , 4, - P1IS, 4, - Offset(0x1AC), /* Port 1 Serial ATA control */ - P1DI, 4, - Offset(0x1B0), /* Port 1 Serial ATA error */ - , 16, - P1PR, 1, - - /* Port 2 */ - Offset(0x220), /* Port 2 Task file status */ - P2ER, 1, - , 2, - P2DQ, 1, - , 3, - P2BY, 1, - Offset(0x228), /* Port 2 Serial ATA status */ - P2DD, 4, - , 4, - P2IS, 4, - Offset(0x22C), /* Port 2 Serial ATA control */ - P2DI, 4, - Offset(0x230), /* Port 2 Serial ATA error */ - , 16, - P2PR, 1, - - /* Port 3 */ - Offset(0x2A0), /* Port 3 Task file status */ - P3ER, 1, - , 2, - P3DQ, 1, - , 3, - P3BY, 1, - Offset(0x2A8), /* Port 3 Serial ATA status */ - P3DD, 4, - , 4, - P3IS, 4, - Offset(0x2AC), /* Port 3 Serial ATA control */ - P3DI, 4, - Offset(0x2B0), /* Port 3 Serial ATA error */ - , 16, - P3PR, 1, - } - } - - - #include "acpi/routing.asl" - - Scope(\_SB) { - - Method(OSFL, 0){ - - if(LNotEqual(OSVR, Ones)) {Return(OSVR)} /* OS version was already detected */ - - if(CondRefOf(\_OSI)) - { - Store(1, OSVR) /* Assume some form of XP */ - if (\_OSI("Windows 2006")) /* Vista */ - { - Store(2, OSVR) - } - } else { - If(WCMP(\_OS,"Linux")) { - Store(3, OSVR) /* Linux */ - } Else { - Store(4, OSVR) /* Gotta be WinCE */ - } - } - Return(OSVR) - } - - Method(_PIC, 0x01, NotSerialized) - { - If (Arg0) - { - \_SB.CIRQ() - } - Store(Arg0, PMOD) - } - Method(CIRQ, 0x00, NotSerialized){ - Store(0, PINA) - Store(0, PINB) - Store(0, PINC) - Store(0, PIND) - Store(0, PINE) - Store(0, PINF) - Store(0, PING) - Store(0, PINH) - } - - Name(IRQB, ResourceTemplate(){ - IRQ(Level,ActiveLow,Shared){15} - }) - - Name(IRQP, ResourceTemplate(){ - IRQ(Level,ActiveLow,Exclusive){3, 4, 5, 7, 10, 11, 12, 15} - }) - - Name(PITF, ResourceTemplate(){ - IRQ(Level,ActiveLow,Exclusive){9} - }) - - Device(INTA) { - Name(_HID, EISAID("PNP0C0F")) - Name(_UID, 1) - - Method(_STA, 0) { - if (PINA) { - Return(0x0B) /* sata is invisible */ - } else { - Return(0x09) /* sata is disabled */ - } - } /* End Method(_SB.INTA._STA) */ - - Method(_DIS ,0) { - /* DBGO("\\_SB\\LNKA\\_DIS\n") */ - Store(0, PINA) - } /* End Method(_SB.INTA._DIS) */ - - Method(_PRS ,0) { - /* DBGO("\\_SB\\LNKA\\_PRS\n") */ - Return(IRQP) - } /* Method(_SB.INTA._PRS) */ - - Method(_CRS ,0) { - /* DBGO("\\_SB\\LNKA\\_CRS\n") */ - CreateWordField(IRQB, 0x1, IRQN) - ShiftLeft(1, PINA, IRQN) - Return(IRQB) - } /* Method(_SB.INTA._CRS) */ - - Method(_SRS, 1) { - /* DBGO("\\_SB\\LNKA\\_CRS\n") */ - CreateWordField(ARG0, 1, IRQM) - - /* Use lowest available IRQ */ - FindSetRightBit(IRQM, Local0) - if (Local0) { - Decrement(Local0) - } - Store(Local0, PINA) - } /* End Method(_SB.INTA._SRS) */ - } /* End Device(INTA) */ - - Device(INTB) { - Name(_HID, EISAID("PNP0C0F")) - Name(_UID, 2) - - Method(_STA, 0) { - if (PINB) { - Return(0x0B) /* sata is invisible */ - } else { - Return(0x09) /* sata is disabled */ - } - } /* End Method(_SB.INTB._STA) */ - - Method(_DIS ,0) { - /* DBGO("\\_SB\\LNKB\\_DIS\n") */ - Store(0, PINB) - } /* End Method(_SB.INTB._DIS) */ - - Method(_PRS ,0) { - /* DBGO("\\_SB\\LNKB\\_PRS\n") */ - Return(IRQP) - } /* Method(_SB.INTB._PRS) */ - - Method(_CRS ,0) { - /* DBGO("\\_SB\\LNKB\\_CRS\n") */ - CreateWordField(IRQB, 0x1, IRQN) - ShiftLeft(1, PINB, IRQN) - Return(IRQB) - } /* Method(_SB.INTB._CRS) */ - - Method(_SRS, 1) { - /* DBGO("\\_SB\\LNKB\\_CRS\n") */ - CreateWordField(ARG0, 1, IRQM) - - /* Use lowest available IRQ */ - FindSetRightBit(IRQM, Local0) - if (Local0) { - Decrement(Local0) - } - Store(Local0, PINB) - } /* End Method(_SB.INTB._SRS) */ - } /* End Device(INTB) */ - - Device(INTC) { - Name(_HID, EISAID("PNP0C0F")) - Name(_UID, 3) - - Method(_STA, 0) { - if (PINC) { - Return(0x0B) /* sata is invisible */ - } else { - Return(0x09) /* sata is disabled */ - } - } /* End Method(_SB.INTC._STA) */ - - Method(_DIS ,0) { - /* DBGO("\\_SB\\LNKC\\_DIS\n") */ - Store(0, PINC) - } /* End Method(_SB.INTC._DIS) */ - - Method(_PRS ,0) { - /* DBGO("\\_SB\\LNKC\\_PRS\n") */ - Return(IRQP) - } /* Method(_SB.INTC._PRS) */ - - Method(_CRS ,0) { - /* DBGO("\\_SB\\LNKC\\_CRS\n") */ - CreateWordField(IRQB, 0x1, IRQN) - ShiftLeft(1, PINC, IRQN) - Return(IRQB) - } /* Method(_SB.INTC._CRS) */ - - Method(_SRS, 1) { - /* DBGO("\\_SB\\LNKC\\_CRS\n") */ - CreateWordField(ARG0, 1, IRQM) - - /* Use lowest available IRQ */ - FindSetRightBit(IRQM, Local0) - if (Local0) { - Decrement(Local0) - } - Store(Local0, PINC) - } /* End Method(_SB.INTC._SRS) */ - } /* End Device(INTC) */ - - Device(INTD) { - Name(_HID, EISAID("PNP0C0F")) - Name(_UID, 4) - - Method(_STA, 0) { - if (PIND) { - Return(0x0B) /* sata is invisible */ - } else { - Return(0x09) /* sata is disabled */ - } - } /* End Method(_SB.INTD._STA) */ - - Method(_DIS ,0) { - /* DBGO("\\_SB\\LNKD\\_DIS\n") */ - Store(0, PIND) - } /* End Method(_SB.INTD._DIS) */ - - Method(_PRS ,0) { - /* DBGO("\\_SB\\LNKD\\_PRS\n") */ - Return(IRQP) - } /* Method(_SB.INTD._PRS) */ - - Method(_CRS ,0) { - /* DBGO("\\_SB\\LNKD\\_CRS\n") */ - CreateWordField(IRQB, 0x1, IRQN) - ShiftLeft(1, PIND, IRQN) - Return(IRQB) - } /* Method(_SB.INTD._CRS) */ - - Method(_SRS, 1) { - /* DBGO("\\_SB\\LNKD\\_CRS\n") */ - CreateWordField(ARG0, 1, IRQM) - - /* Use lowest available IRQ */ - FindSetRightBit(IRQM, Local0) - if (Local0) { - Decrement(Local0) - } - Store(Local0, PIND) - } /* End Method(_SB.INTD._SRS) */ - } /* End Device(INTD) */ - - Device(INTE) { - Name(_HID, EISAID("PNP0C0F")) - Name(_UID, 5) - - Method(_STA, 0) { - if (PINE) { - Return(0x0B) /* sata is invisible */ - } else { - Return(0x09) /* sata is disabled */ - } - } /* End Method(_SB.INTE._STA) */ - - Method(_DIS ,0) { - /* DBGO("\\_SB\\LNKE\\_DIS\n") */ - Store(0, PINE) - } /* End Method(_SB.INTE._DIS) */ - - Method(_PRS ,0) { - /* DBGO("\\_SB\\LNKE\\_PRS\n") */ - Return(IRQP) - } /* Method(_SB.INTE._PRS) */ - - Method(_CRS ,0) { - /* DBGO("\\_SB\\LNKE\\_CRS\n") */ - CreateWordField(IRQB, 0x1, IRQN) - ShiftLeft(1, PINE, IRQN) - Return(IRQB) - } /* Method(_SB.INTE._CRS) */ - - Method(_SRS, 1) { - /* DBGO("\\_SB\\LNKE\\_CRS\n") */ - CreateWordField(ARG0, 1, IRQM) - - /* Use lowest available IRQ */ - FindSetRightBit(IRQM, Local0) - if (Local0) { - Decrement(Local0) - } - Store(Local0, PINE) - } /* End Method(_SB.INTE._SRS) */ - } /* End Device(INTE) */ - - Device(INTF) { - Name(_HID, EISAID("PNP0C0F")) - Name(_UID, 6) - - Method(_STA, 0) { - if (PINF) { - Return(0x0B) /* sata is invisible */ - } else { - Return(0x09) /* sata is disabled */ - } - } /* End Method(_SB.INTF._STA) */ - - Method(_DIS ,0) { - /* DBGO("\\_SB\\LNKF\\_DIS\n") */ - Store(0, PINF) - } /* End Method(_SB.INTF._DIS) */ - - Method(_PRS ,0) { - /* DBGO("\\_SB\\LNKF\\_PRS\n") */ - Return(PITF) - } /* Method(_SB.INTF._PRS) */ - - Method(_CRS ,0) { - /* DBGO("\\_SB\\LNKF\\_CRS\n") */ - CreateWordField(IRQB, 0x1, IRQN) - ShiftLeft(1, PINF, IRQN) - Return(IRQB) - } /* Method(_SB.INTF._CRS) */ - - Method(_SRS, 1) { - /* DBGO("\\_SB\\LNKF\\_CRS\n") */ - CreateWordField(ARG0, 1, IRQM) - - /* Use lowest available IRQ */ - FindSetRightBit(IRQM, Local0) - if (Local0) { - Decrement(Local0) - } - Store(Local0, PINF) - } /* End Method(_SB.INTF._SRS) */ - } /* End Device(INTF) */ - - Device(INTG) { - Name(_HID, EISAID("PNP0C0F")) - Name(_UID, 7) - - Method(_STA, 0) { - if (PING) { - Return(0x0B) /* sata is invisible */ - } else { - Return(0x09) /* sata is disabled */ - } - } /* End Method(_SB.INTG._STA) */ - - Method(_DIS ,0) { - /* DBGO("\\_SB\\LNKG\\_DIS\n") */ - Store(0, PING) - } /* End Method(_SB.INTG._DIS) */ - - Method(_PRS ,0) { - /* DBGO("\\_SB\\LNKG\\_PRS\n") */ - Return(IRQP) - } /* Method(_SB.INTG._CRS) */ - - Method(_CRS ,0) { - /* DBGO("\\_SB\\LNKG\\_CRS\n") */ - CreateWordField(IRQB, 0x1, IRQN) - ShiftLeft(1, PING, IRQN) - Return(IRQB) - } /* Method(_SB.INTG._CRS) */ - - Method(_SRS, 1) { - /* DBGO("\\_SB\\LNKG\\_CRS\n") */ - CreateWordField(ARG0, 1, IRQM) - - /* Use lowest available IRQ */ - FindSetRightBit(IRQM, Local0) - if (Local0) { - Decrement(Local0) - } - Store(Local0, PING) - } /* End Method(_SB.INTG._SRS) */ - } /* End Device(INTG) */ - - Device(INTH) { - Name(_HID, EISAID("PNP0C0F")) - Name(_UID, 8) - - Method(_STA, 0) { - if (PINH) { - Return(0x0B) /* sata is invisible */ - } else { - Return(0x09) /* sata is disabled */ - } - } /* End Method(_SB.INTH._STA) */ - - Method(_DIS ,0) { - /* DBGO("\\_SB\\LNKH\\_DIS\n") */ - Store(0, PINH) - } /* End Method(_SB.INTH._DIS) */ - - Method(_PRS ,0) { - /* DBGO("\\_SB\\LNKH\\_PRS\n") */ - Return(IRQP) - } /* Method(_SB.INTH._CRS) */ - - Method(_CRS ,0) { - /* DBGO("\\_SB\\LNKH\\_CRS\n") */ - CreateWordField(IRQB, 0x1, IRQN) - ShiftLeft(1, PINH, IRQN) - Return(IRQB) - } /* Method(_SB.INTH._CRS) */ - - Method(_SRS, 1) { - /* DBGO("\\_SB\\LNKH\\_CRS\n") */ - CreateWordField(ARG0, 1, IRQM) - - /* Use lowest available IRQ */ - FindSetRightBit(IRQM, Local0) - if (Local0) { - Decrement(Local0) - } - Store(Local0, PINH) - } /* End Method(_SB.INTH._SRS) */ - } /* End Device(INTH) */ - - } /* End Scope(_SB) */ - - #include - - /* Wake status package */ - Name(WKST,Package(){Zero, Zero}) - - /* - * \_PTS - Prepare to Sleep method - * - * Entry: - * Arg0=The value of the sleeping state S1=1, S2=2, etc - * - * Exit: - * -none- - * - * The _PTS control method is executed at the beginning of the sleep process - * for S1-S5. The sleeping value is passed to the _PTS control method. This - * control method may be executed a relatively long time before entering the - * sleep state and the OS may abort the operation without notification to - * the ACPI driver. This method cannot modify the configuration or power - * state of any device in the system. - */ - Method(\_PTS, 1) { - /* DBGO("\\_PTS\n") */ - /* DBGO("From S0 to S") */ - /* DBGO(Arg0) */ - /* DBGO("\n") */ - - /* Don't allow PCIRST# to reset USB */ - if (LEqual(Arg0,3)){ - Store(0,URRE) - } - - /* Clear sleep SMI status flag and enable sleep SMI trap. */ - /*Store(One, CSSM) - Store(One, SSEN)*/ - - /* On older chips, clear PciExpWakeDisEn */ - /*if (LLessEqual(\_SB.SBRI, 0x13)) { - * Store(0,\_SB.PWDE) - *} - */ - - /* Clear wake status structure. */ - Store(0, Index(WKST,0)) - Store(0, Index(WKST,1)) - \_SB.PCI0.SIOS (Arg0) - } /* End Method(\_PTS) */ - - /* - * The following method results in a "not a valid reserved NameSeg" - * warning so I have commented it out for the duration. It isn't - * used, so it could be removed. - * - * - * \_GTS OEM Going To Sleep method - * - * Entry: - * Arg0=The value of the sleeping state S1=1, S2=2 - * - * Exit: - * -none- - * - * Method(\_GTS, 1) { - * DBGO("\\_GTS\n") - * DBGO("From S0 to S") - * DBGO(Arg0) - * DBGO("\n") - * } - */ - - /* - * \_BFS OEM Back From Sleep method - * - * Entry: - * Arg0=The value of the sleeping state S1=1, S2=2 - * - * Exit: - * -none- - */ - Method(\_BFS, 1) { - /* DBGO("\\_BFS\n") */ - /* DBGO("From S") */ - /* DBGO(Arg0) */ - /* DBGO(" to S0\n") */ - } - - /* - * \_WAK System Wake method - * - * Entry: - * Arg0=The value of the sleeping state S1=1, S2=2 - * - * Exit: - * Return package of 2 DWords - * Dword 1 - Status - * 0x00000000 wake succeeded - * 0x00000001 Wake was signaled but failed due to lack of power - * 0x00000002 Wake was signaled but failed due to thermal condition - * Dword 2 - Power Supply state - * if non-zero the effective S-state the power supply entered - */ - Method(\_WAK, 1) { - /* DBGO("\\_WAK\n") */ - /* DBGO("From S") */ - /* DBGO(Arg0) */ - /* DBGO(" to S0\n") */ - - /* Re-enable HPET */ - Store(1,HPDE) - - /* Restore PCIRST# so it resets USB */ - if (LEqual(Arg0,3)){ - Store(1,URRE) - } - - /* Arbitrarily clear PciExpWakeStatus */ - Store(PWST, Local1) - Store(Local1, PWST) - - /* if (DeRefOf(Index(WKST,0))) { - * Store(0, Index(WKST,1)) - * } else { - * Store(Arg0, Index(WKST,1)) - * } - */ - \_SB.PCI0.SIOW () - Return(WKST) - } /* End Method(\_WAK) */ - - Scope(\_GPE) { /* Start Scope GPE */ - /* General event 0 */ - /* Method(_L00) { - * DBGO("\\_GPE\\_L00\n") - * } - */ - - /* General event 1 */ - /* Method(_L01) { - * DBGO("\\_GPE\\_L00\n") - * } - */ - - /* General event 2 */ - /* Method(_L02) { - * DBGO("\\_GPE\\_L00\n") - * } - */ - - /* General event 3 */ - Method(_L03) { - /* DBGO("\\_GPE\\_L00\n") */ - Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ - } - - /* General event 4 */ - /* Method(_L04) { - * DBGO("\\_GPE\\_L00\n") - * } - */ - - /* General event 5 */ - /* Method(_L05) { - * DBGO("\\_GPE\\_L00\n") - * } - */ - - /* General event 6 - Used for GPM6, moved to USB.asl */ - /* Method(_L06) { - * DBGO("\\_GPE\\_L00\n") - * } - */ - - /* General event 7 - Used for GPM7, moved to USB.asl */ - /* Method(_L07) { - * DBGO("\\_GPE\\_L07\n") - * } - */ - - /* Legacy PM event */ - Method(_L08) { - /* DBGO("\\_GPE\\_L08\n") */ - } - - /* Temp warning (TWarn) event */ - Method(_L09) { - /* DBGO("\\_GPE\\_L09\n") */ - Notify (\_TZ.TZ00, 0x80) - } - - /* Reserved */ - /* Method(_L0A) { - * DBGO("\\_GPE\\_L0A\n") - * } - */ - - /* USB controller PME# */ - Method(_L0B) { - /* DBGO("\\_GPE\\_L0B\n") */ - Notify(\_SB.PCI0.UOH1, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(\_SB.PCI0.UOH2, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(\_SB.PCI0.UOH3, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(\_SB.PCI0.UOH4, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(\_SB.PCI0.UOH5, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(\_SB.PCI0.UEH1, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ - } - - /* AC97 controller PME# */ - /* Method(_L0C) { - * DBGO("\\_GPE\\_L0C\n") - * } - */ - - /* OtherTherm PME# */ - /* Method(_L0D) { - * DBGO("\\_GPE\\_L0D\n") - * } - */ - - /* GPM9 SCI event - Moved to USB.asl */ - /* Method(_L0E) { - * DBGO("\\_GPE\\_L0E\n") - * } - */ - - /* PCIe HotPlug event */ - /* Method(_L0F) { - * DBGO("\\_GPE\\_L0F\n") - * } - */ - - /* ExtEvent0 SCI event */ - Method(_L10) { - /* DBGO("\\_GPE\\_L10\n") */ - } - - - /* ExtEvent1 SCI event */ - Method(_L11) { - /* DBGO("\\_GPE\\_L11\n") */ - } - - /* PCIe PME# event */ - /* Method(_L12) { - * DBGO("\\_GPE\\_L12\n") - * } - */ - - /* GPM0 SCI event - Moved to USB.asl */ - /* Method(_L13) { - * DBGO("\\_GPE\\_L13\n") - * } - */ - - /* GPM1 SCI event - Moved to USB.asl */ - /* Method(_L14) { - * DBGO("\\_GPE\\_L14\n") - * } - */ - - /* GPM2 SCI event - Moved to USB.asl */ - /* Method(_L15) { - * DBGO("\\_GPE\\_L15\n") - * } - */ - - /* GPM3 SCI event - Moved to USB.asl */ - /* Method(_L16) { - * DBGO("\\_GPE\\_L16\n") - * } - */ - - /* GPM8 SCI event - Moved to USB.asl */ - /* Method(_L17) { - * DBGO("\\_GPE\\_L17\n") - * } - */ - - /* GPIO0 or GEvent8 event */ - Method(_L18) { - /* DBGO("\\_GPE\\_L18\n") */ - Notify(\_SB.PCI0.PBR2, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(\_SB.PCI0.PBR4, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(\_SB.PCI0.PBR5, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(\_SB.PCI0.PBR6, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(\_SB.PCI0.PBR7, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ - } - - /* GPM4 SCI event - Moved to USB.asl */ - /* Method(_L19) { - * DBGO("\\_GPE\\_L19\n") - * } - */ - - /* GPM5 SCI event - Moved to USB.asl */ - /* Method(_L1A) { - * DBGO("\\_GPE\\_L1A\n") - * } - */ - - /* Azalia SCI event */ - Method(_L1B) { - /* DBGO("\\_GPE\\_L1B\n") */ - Notify(\_SB.PCI0.AZHD, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ - } - - /* GPM6 SCI event - Reassigned to _L06 */ - /* Method(_L1C) { - * DBGO("\\_GPE\\_L1C\n") - * } - */ - - /* GPM7 SCI event - Reassigned to _L07 */ - /* Method(_L1D) { - * DBGO("\\_GPE\\_L1D\n") - * } - */ - - /* GPIO2 or GPIO66 SCI event */ - /* Method(_L1E) { - * DBGO("\\_GPE\\_L1E\n") - * } - */ - - /* SATA SCI event - Moved to sata.asl */ - /* Method(_L1F) { - * DBGO("\\_GPE\\_L1F\n") - * } - */ - - } /* End Scope GPE */ - - #include "acpi/usb.asl" - - /* System Bus */ - Scope(\_SB) { /* Start \_SB scope */ - #include /* global utility methods expected within the \_SB scope */ - - /* _SB.PCI0 */ - /* Note: Only need HID on Primary Bus */ - Device(PCI0) { - External (TOM1) - External (TOM2) - Name(_HID, EISAID("PNP0A03")) - Name(_ADR, 0x00180000) /* Dev# = BSP Dev#, Func# = 0 */ - Method(_BBN, 0) { /* Bus number = 0 */ - Return(0) - } - Method(_STA, 0) { - /* DBGO("\\_SB\\PCI0\\_STA\n") */ - Return(0x0B) /* Status is visible */ - } - - Method(_PRT,0) { - If(PMOD){ Return(APR0) } /* APIC mode */ - Return (PR0) /* PIC Mode */ - } /* end _PRT */ - - /* Describe the Northbridge devices */ - Device(AMRT) { - Name(_ADR, 0x00000000) - } /* end AMRT */ - - /* The internal GFX bridge */ - Device(AGPB) { - Name(_ADR, 0x00010000) - Name(_PRW, Package() {0x18, 4}) - Method(_PRT,0) { - Return (APR1) - } - } /* end AGPB */ - - /* The external GFX bridge */ - Device(PBR2) { - Name(_ADR, 0x00020000) - Name(_PRW, Package() {0x18, 4}) - Method(_PRT,0) { - If(PMOD){ Return(APS2) } /* APIC mode */ - Return (PS2) /* PIC Mode */ - } /* end _PRT */ - } /* end PBR2 */ - - /* Dev3 is also an external GFX bridge, not used in Herring */ - - Device(PBR4) { - Name(_ADR, 0x00040000) - Name(_PRW, Package() {0x18, 4}) - Method(_PRT,0) { - If(PMOD){ Return(APS4) } /* APIC mode */ - Return (PS4) /* PIC Mode */ - } /* end _PRT */ - } /* end PBR4 */ - - Device(PBR5) { - Name(_ADR, 0x00050000) - Name(_PRW, Package() {0x18, 4}) - Method(_PRT,0) { - If(PMOD){ Return(APS5) } /* APIC mode */ - Return (PS5) /* PIC Mode */ - } /* end _PRT */ - } /* end PBR5 */ - - Device(PBR6) { - Name(_ADR, 0x00060000) - Name(_PRW, Package() {0x18, 4}) - Method(_PRT,0) { - If(PMOD){ Return(APS6) } /* APIC mode */ - Return (PS6) /* PIC Mode */ - } /* end _PRT */ - } /* end PBR6 */ - - /* The onboard EtherNet chip */ - Device(PBR7) { - Name(_ADR, 0x00070000) - Name(_PRW, Package() {0x18, 4}) - Method(_PRT,0) { - If(PMOD){ Return(APS7) } /* APIC mode */ - Return (PS7) /* PIC Mode */ - } /* end _PRT */ - } /* end PBR7 */ - - /* GPP */ - Device(PBR9) { - Name(_ADR, 0x00090000) - Name(_PRW, Package() {0x18, 4}) - Method(_PRT,0) { - If(PMOD){ Return(APS9) } /* APIC mode */ - Return (PS9) /* PIC Mode */ - } /* end _PRT */ - } /* end PBR9 */ - - Device(PBRa) { - Name(_ADR, 0x000A0000) - Name(_PRW, Package() {0x18, 4}) - Method(_PRT,0) { - If(PMOD){ Return(APSa) } /* APIC mode */ - Return (PSa) /* PIC Mode */ - } /* end _PRT */ - } /* end PBRa */ - - - /* PCI slot 1, 2, 3 */ - Device(PIBR) { - Name(_ADR, 0x00140004) - Name(_PRW, Package() {0x18, 4}) - - Method(_PRT, 0) { - Return (PCIB) - } - } - - /* Describe the Southbridge devices */ - Device(STCR) { - Name(_ADR, 0x00110000) - #include "acpi/sata.asl" - } /* end STCR */ - - Device(UOH1) { - Name(_ADR, 0x00130000) - Name(_PRW, Package() {0x0B, 3}) - } /* end UOH1 */ - - Device(UOH2) { - Name(_ADR, 0x00130001) - Name(_PRW, Package() {0x0B, 3}) - } /* end UOH2 */ - - Device(UOH3) { - Name(_ADR, 0x00130002) - Name(_PRW, Package() {0x0B, 3}) - } /* end UOH3 */ - - Device(UOH4) { - Name(_ADR, 0x00130003) - Name(_PRW, Package() {0x0B, 3}) - } /* end UOH4 */ - - Device(UOH5) { - Name(_ADR, 0x00130004) - Name(_PRW, Package() {0x0B, 3}) - } /* end UOH5 */ - - Device(UEH1) { - Name(_ADR, 0x00130005) - Name(_PRW, Package() {0x0B, 3}) - } /* end UEH1 */ - - Device(SBUS) { - Name(_ADR, 0x00140000) - } /* end SBUS */ - - /* Primary (and only) IDE channel */ - Device(IDEC) { - Name(_ADR, 0x00140001) - #include "acpi/ide.asl" - } /* end IDEC */ - - Device(AZHD) { - Name(_ADR, 0x00140002) - OperationRegion(AZPD, PCI_Config, 0x00, 0x100) - Field(AZPD, AnyAcc, NoLock, Preserve) { - offset (0x42), - NSDI, 1, - NSDO, 1, - NSEN, 1, - offset (0x44), - IPCR, 4, - offset (0x54), - PWST, 2, - , 6, - PMEB, 1, - , 6, - PMST, 1, - offset (0x62), - MMCR, 1, - offset (0x64), - MMLA, 32, - offset (0x68), - MMHA, 32, - offset (0x6C), - MMDT, 16, - } - - Method(_INI) { - If(LEqual(OSVR,3)){ /* If we are running Linux */ - Store(zero, NSEN) - Store(one, NSDO) - Store(one, NSDI) - } - } - } /* end AZHD */ - - Device(LIBR) { - Name(_ADR, 0x00140003) - /* Method(_INI) { - * DBGO("\\_SB\\PCI0\\LpcIsaBr\\_INI\n") - } */ /* End Method(_SB.SBRDG._INI) */ - - /* Real Time Clock Device */ - Device(RTC0) { - Name(_HID, EISAID("PNP0B00")) /* AT Real Time Clock (not PIIX4 compatible) */ - Name(_CRS, ResourceTemplate() { - IRQNoFlags(){8} - IO(Decode16,0x0070, 0x0070, 0, 2) - /* IO(Decode16,0x0070, 0x0070, 0, 4) */ - }) - } /* End Device(_SB.PCI0.LpcIsaBr.RTC0) */ - - Device(TMR) { /* Timer */ - Name(_HID,EISAID("PNP0100")) /* System Timer */ - Name(_CRS, ResourceTemplate() { - IRQNoFlags(){0} - IO(Decode16, 0x0040, 0x0040, 0, 4) - /* IO(Decode16, 0x0048, 0x0048, 0, 4) */ - }) - } /* End Device(_SB.PCI0.LpcIsaBr.TMR) */ - - Device(SPKR) { /* Speaker */ - Name(_HID,EISAID("PNP0800")) /* AT style speaker */ - Name(_CRS, ResourceTemplate() { - IO(Decode16, 0x0061, 0x0061, 0, 1) - }) - } /* End Device(_SB.PCI0.LpcIsaBr.SPKR) */ - - Device(PIC) { - Name(_HID,EISAID("PNP0000")) /* AT Interrupt Controller */ - Name(_CRS, ResourceTemplate() { - IRQNoFlags(){2} - IO(Decode16,0x0020, 0x0020, 0, 2) - IO(Decode16,0x00A0, 0x00A0, 0, 2) - /* IO(Decode16, 0x00D0, 0x00D0, 0x10, 0x02) */ - /* IO(Decode16, 0x04D0, 0x04D0, 0x10, 0x02) */ - }) - } /* End Device(_SB.PCI0.LpcIsaBr.PIC) */ - - Device(MAD) { /* 8257 DMA */ - Name(_HID,EISAID("PNP0200")) /* Hardware Device ID */ - Name(_CRS, ResourceTemplate() { - DMA(Compatibility,BusMaster,Transfer8){4} - IO(Decode16, 0x0000, 0x0000, 0x10, 0x10) - IO(Decode16, 0x0081, 0x0081, 0x01, 0x03) - IO(Decode16, 0x0087, 0x0087, 0x01, 0x01) - IO(Decode16, 0x0089, 0x0089, 0x01, 0x03) - IO(Decode16, 0x008F, 0x008F, 0x01, 0x01) - IO(Decode16, 0x00C0, 0x00C0, 0x10, 0x20) - }) /* End Name(_SB.PCI0.LpcIsaBr.MAD._CRS) */ - } /* End Device(_SB.PCI0.LpcIsaBr.MAD) */ - - Device(COPR) { - Name(_HID,EISAID("PNP0C04")) /* Math Coprocessor */ - Name(_CRS, ResourceTemplate() { - IO(Decode16, 0x00F0, 0x00F0, 0, 0x10) - IRQNoFlags(){13} - }) - } /* End Device(_SB.PCI0.LpcIsaBr.COPR) */ -#if 0 /* defined by HPET table? */ - Device(HPTM) { - Name(_HID,EISAID("PNP0103")) - Name(CRS,ResourceTemplate() { - Memory32Fixed(ReadOnly,0xFED00000, 0x00000400, HPT) /* 1kb reserved space */ - }) - Method(_STA, 0) { - Return(0x0F) /* sata is visible */ - } - Method(_CRS, 0) { - CreateDwordField(CRS, ^HPT._BAS, HPBX) - Store(HPBA, HPBX) - Return(CRS) - } - } /* End Device(_SB.PCI0.LpcIsaBr.COPR) */ -#endif - } /* end LIBR */ - - Device(HPBR) { - Name(_ADR, 0x00140004) - } /* end HostPciBr */ - - Device(ACAD) { - Name(_ADR, 0x00140005) - } /* end Ac97audio */ - - Device(ACMD) { - Name(_ADR, 0x00140006) - } /* end Ac97modem */ - - /* ITE8718 Support */ - OperationRegion (IOID, SystemIO, 0x2E, 0x02) /* sometimes it is 0x4E */ - Field (IOID, ByteAcc, NoLock, Preserve) - { - SIOI, 8, SIOD, 8 /* 0x2E and 0x2F */ - } - - IndexField (SIOI, SIOD, ByteAcc, NoLock, Preserve) - { - Offset (0x07), - LDN, 8, /* Logical Device Number */ - Offset (0x20), - CID1, 8, /* Chip ID Byte 1, 0x87 */ - CID2, 8, /* Chip ID Byte 2, 0x12 */ - Offset (0x30), - ACTR, 8, /* Function activate */ - Offset (0xF0), - APC0, 8, /* APC/PME Event Enable Register */ - APC1, 8, /* APC/PME Status Register */ - APC2, 8, /* APC/PME Control Register 1 */ - APC3, 8, /* Environment Controller Special Configuration Register */ - APC4, 8 /* APC/PME Control Register 2 */ - } - - /* Enter the 8718 MB PnP Mode */ - Method (EPNP) - { - Store(0x87, SIOI) - Store(0x01, SIOI) - Store(0x55, SIOI) - Store(0x55, SIOI) /* 8718 magic number */ - } - /* Exit the 8718 MB PnP Mode */ - Method (XPNP) - { - Store (0x02, SIOI) - Store (0x02, SIOD) - } - /* - * Keyboard PME is routed to SB700 Gevent3. We can wake - * up the system by pressing the key. - */ - Method (SIOS, 1) - { - /* We only enable KBD PME for S5. */ - If (LLess (Arg0, 0x05)) - { - EPNP() - /* DBGO("8718F\n") */ - - Store (0x4, LDN) - Store (One, ACTR) /* Enable EC */ - /* - Store (0x4, LDN) - Store (0x04, APC4) - */ /* falling edge. which mode? Not sure. */ - - Store (0x4, LDN) - Store (0x08, APC1) /* clear PME status, Use 0x18 for mouse & KBD */ - Store (0x4, LDN) - Store (0x08, APC0) /* enable PME, Use 0x18 for mouse & KBD */ - - XPNP() - } - } - Method (SIOW, 0) - { - EPNP() - Store (0x4, LDN) - Store (Zero, APC0) /* disable keyboard PME */ - Store (0x4, LDN) - Store (0xFF, APC1) /* clear keyboard PME status */ - XPNP() - } - - Name(CRES, ResourceTemplate() { - IO(Decode16, 0x0CF8, 0x0CF8, 1, 8) - - WORDIO(ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, - 0x0000, /* address granularity */ - 0x0000, /* range minimum */ - 0x0CF7, /* range maximum */ - 0x0000, /* translation */ - 0x0CF8 /* length */ - ) - - WORDIO(ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, - 0x0000, /* address granularity */ - 0x0D00, /* range minimum */ - 0xFFFF, /* range maximum */ - 0x0000, /* translation */ - 0xF300 /* length */ - ) - - Memory32Fixed(READONLY, 0x000A0000, 0x00020000, VGAM) /* VGA memory space */ -#if 0 - Memory32Fixed(READWRITE, 0, 0xA0000, BSMM) - Memory32Fixed(READONLY, 0x000C0000, 0x00020000, EMM1) /* Assume C0000-E0000 empty */ - Memory32Fixed(READONLY, 0x000E0000, 0x00020000, RDBS) /* BIOS ROM area */ - - /* DRAM Memory from 1MB to TopMem */ - Memory32Fixed(READWRITE, 0x00100000, 0, DMLO) /* 1MB to TopMem */ - - /* BIOS space just below 4GB */ - DWORDMemory( - ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite, - 0x00, /* Granularity */ - 0x00000000, /* Min */ - 0x00000000, /* Max */ - 0x00000000, /* Translation */ - 0x00000001, /* Max-Min, RLEN */ - ,, - PCBM - ) - - /* DRAM memory from 4GB to TopMem2 */ - QWORDMemory(ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite, - 0x00000000, /* Granularity */ - 0x00000000, /* Min */ - 0x00000000, /* Max */ - 0x00000000, /* Translation */ - 0x00000001, /* Max-Min, RLEN */ - ,, - DMHI - ) - - /* BIOS space just below 16EB */ - QWORDMemory(ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite, - 0x00000000, /* Granularity */ - 0x00000000, /* Min */ - 0x00000000, /* Max */ - 0x00000000, /* Translation */ - 0x00000001, /* Max-Min, RLEN */ - ,, - PEBM - ) -#endif - /* memory space for PCI BARs below 4GB */ - Memory32Fixed(ReadOnly, 0x00000000, 0x00000000, MMIO) - }) /* End Name(_SB.PCI0.CRES) */ - - Method(_CRS, 0) { - /* DBGO("\\_SB\\PCI0\\_CRS\n") */ -#if 0 - CreateDWordField(CRES, ^EMM1._BAS, EM1B) - CreateDWordField(CRES, ^EMM1._LEN, EM1L) - CreateDWordField(CRES, ^DMLO._BAS, DMLB) - CreateDWordField(CRES, ^DMLO._LEN, DMLL) - CreateDWordField(CRES, ^PCBM._MIN, PBMB) - CreateDWordField(CRES, ^PCBM._LEN, PBML) - - CreateQWordField(CRES, ^DMHI._MIN, DMHB) - CreateQWordField(CRES, ^DMHI._LEN, DMHL) - CreateQWordField(CRES, ^PEBM._MIN, EBMB) - CreateQWordField(CRES, ^PEBM._LEN, EBML) - - If(LGreater(LOMH, 0xC0000)){ - Store(0xC0000, EM1B) /* Hole above C0000 and below E0000 */ - Subtract(LOMH, 0xC0000, EM1L) /* subtract start, assumes allocation from C0000 going up */ - } - - /* Set size of memory from 1MB to TopMem */ - Subtract(TOM1, 0x100000, DMLL) - - /* - * If(LNotEqual(TOM2, 0x00000000)){ - * Store(0x100000000,DMHB) DRAM from 4GB to TopMem2 - * Subtract(TOM2, 0x100000000, DMHL) - * } - */ - - /* If there is no memory above 4GB, put the BIOS just below 4GB */ - If(LEqual(TOM2, 0x00000000)){ - Store(PBAD,PBMB) /* Reserve the "BIOS" space */ - Store(PBLN,PBML) - } - Else { /* Otherwise, put the BIOS just below 16EB */ - ShiftLeft(PBAD,16,EBMB) /* Reserve the "BIOS" space */ - Store(PBLN,EBML) - } -#endif - CreateDWordField(CRES, ^MMIO._BAS, MM1B) - CreateDWordField(CRES, ^MMIO._LEN, MM1L) - /* - * Declare memory between TOM1 and 4GB as available - * for PCI MMIO. - * Use ShiftLeft to avoid 64bit constant (for XP). - * This will work even if the OS does 32bit arithmetic, as - * 32bit (0x00000000 - TOM1) will wrap and give the same - * result as 64bit (0x100000000 - TOM1). - */ - Store(TOM1, MM1B) - ShiftLeft(0x10000000, 4, Local0) - Subtract(Local0, TOM1, Local0) - Store(Local0, MM1L) - - Return(CRES) /* note to change the Name buffer */ - } /* end of Method(_SB.PCI0._CRS) */ - - /* - * - * FIRST METHOD CALLED UPON BOOT - * - * 1. If debugging, print current OS and ACPI interpreter. - * 2. Get PCI Interrupt routing from ACPI VSM, this - * value is based on user choice in BIOS setup. - */ - Method(_INI, 0) { - /* DBGO("\\_SB\\_INI\n") */ - /* DBGO(" DSDT.ASL code from ") */ - /* DBGO(__DATE__) */ - /* DBGO(" ") */ - /* DBGO(__TIME__) */ - /* DBGO("\n Sleep states supported: ") */ - /* DBGO("\n") */ - /* DBGO(" \\_OS=") */ - /* DBGO(\_OS) */ - /* DBGO("\n \\_REV=") */ - /* DBGO(\_REV) */ - /* DBGO("\n") */ - - /* Determine the OS we're running on */ - OSFL() - - /* On older chips, clear PciExpWakeDisEn */ - /*if (LLessEqual(\SBRI, 0x13)) { - * Store(0,\PWDE) - * } - */ - } /* End Method(_SB._INI) */ - } /* End Device(PCI0) */ - - Device(PWRB) { /* Start Power button device */ - Name(_HID, EISAID("PNP0C0C")) - Name(_UID, 0xAA) - Name(_PRW, Package () {3, 0x04}) /* wake from S1-S4 */ - Name(_STA, 0x0B) /* sata is invisible */ - } - } /* End \_SB scope */ - - Scope(\_SI) { - Method(_SST, 1) { - /* DBGO("\\_SI\\_SST\n") */ - /* DBGO(" New Indicator state: ") */ - /* DBGO(Arg0) */ - /* DBGO("\n") */ - } - } /* End Scope SI */ - - #include - - /* THERMAL */ - Scope(\_TZ) { - Name (KELV, 2732) - Name (THOT, 800) - Name (TCRT, 850) - - ThermalZone(TZ00) { - Method(_AC0,0) { /* Active Cooling 0 (0=highest fan speed) */ - /* DBGO("\\_TZ\\TZ00\\_AC0\n") */ - Return(Add(0, 2730)) - } - Method(_AL0,0) { /* Returns package of cooling device to turn on */ - /* DBGO("\\_TZ\\TZ00\\_AL0\n") */ - Return(Package() {\_TZ.TZ00.FAN0}) - } - Device (FAN0) { - Name(_HID, EISAID("PNP0C0B")) - Name(_PR0, Package() {PFN0}) - } - - PowerResource(PFN0,0,0) { - Method(_STA) { - Store(0xF,Local0) - Return(Local0) - } - Method(_ON) { - /* DBGO("\\_TZ\\TZ00\\FAN0 _ON\n") */ - } - Method(_OFF) { - /* DBGO("\\_TZ\\TZ00\\FAN0 _OFF\n") */ - } - } - - Method(_HOT,0) { /* return hot temp in tenths degree Kelvin */ - /* DBGO("\\_TZ\\TZ00\\_HOT\n") */ - Return (Add (THOT, KELV)) - } - Method(_CRT,0) { /* return critical temp in tenths degree Kelvin */ - /* DBGO("\\_TZ\\TZ00\\_CRT\n") */ - Return (Add (TCRT, KELV)) - } - Method(_TMP,0) { /* return current temp of this zone */ - Store (SMBR (0x07, 0x4C,, 0x00), Local0) - If (LGreater (Local0, 0x10)) { - Store (Local0, Local1) - } - Else { - Add (Local0, THOT, Local0) - Return (Add (400, KELV)) - } - - Store (SMBR (0x07, 0x4C, 0x01), Local0) - /* only the two MSBs in the external temperature low byte are used, resolution 0.25. We ignore it */ - /* Store (SMBR (0x07, 0x4C, 0x10), Local2) */ - If (LGreater (Local0, 0x10)) { - If (LGreater (Local0, Local1)) { - Store (Local0, Local1) - } - - Multiply (Local1, 10, Local1) - Return (Add (Local1, KELV)) - } - Else { - Add (Local0, THOT, Local0) - Return (Add (400 , KELV)) - } - } /* end of _TMP */ - } /* end of TZ00 */ - } -} -/* End of ASL file */ diff --git a/src/mainboard/amd/mahogany_fam10/get_bus_conf.c b/src/mainboard/amd/mahogany_fam10/get_bus_conf.c deleted file mode 100644 index ee2a6caeb9..0000000000 --- a/src/mainboard/amd/mahogany_fam10/get_bus_conf.c +++ /dev/null @@ -1,44 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2010 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include -#include - -#include - -/* Global variables for MB layouts and these will be shared by irqtable mptable -* and acpi_tables busnum is default. -*/ -u32 apicid_sb700; - -void get_bus_conf(void) -{ - u32 apicid_base; - - get_default_pci1234(1); - - sysconf.sbdn = (sysconf.hcdn[0] & 0xff); - - pirq_router_bus = (sysconf.pci1234[0] >> 16) & 0xff; - - /* I/O APICs: APIC ID Version State Address */ - if (CONFIG(LOGICAL_CPUS)) - apicid_base = get_apicid_base(1); - else - apicid_base = CONFIG_MAX_PHYSICAL_CPUS; - apicid_sb700 = apicid_base + 0; -} diff --git a/src/mainboard/amd/mahogany_fam10/irq_tables.c b/src/mainboard/amd/mahogany_fam10/irq_tables.c deleted file mode 100644 index 0f7192514e..0000000000 --- a/src/mainboard/amd/mahogany_fam10/irq_tables.c +++ /dev/null @@ -1,102 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2010 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include -#include -#include - -#include - -static void write_pirq_info(struct irq_info *pirq_info, u8 bus, u8 devfn, - u8 link0, u16 bitmap0, u8 link1, u16 bitmap1, - u8 link2, u16 bitmap2, u8 link3, u16 bitmap3, - u8 slot, u8 rfu) -{ - pirq_info->bus = bus; - pirq_info->devfn = devfn; - pirq_info->irq[0].link = link0; - pirq_info->irq[0].bitmap = bitmap0; - pirq_info->irq[1].link = link1; - pirq_info->irq[1].bitmap = bitmap1; - pirq_info->irq[2].link = link2; - pirq_info->irq[2].bitmap = bitmap2; - pirq_info->irq[3].link = link3; - pirq_info->irq[3].bitmap = bitmap3; - pirq_info->slot = slot; - pirq_info->rfu = rfu; -} - - -unsigned long write_pirq_routing_table(unsigned long addr) -{ - struct irq_routing_table *pirq; - struct irq_info *pirq_info; - u32 slot_num; - u8 *v; - - u8 sum = 0; - int i; - - /* Align the table to be 16 byte aligned. */ - addr += 15; - addr &= ~15; - - /* This table must be between 0xf0000 & 0x100000 */ - printk(BIOS_INFO, "Writing IRQ routing tables to 0x%lx...", addr); - - pirq = (void *)(addr); - v = (u8 *) (addr); - - pirq->signature = PIRQ_SIGNATURE; - pirq->version = PIRQ_VERSION; - - pirq->rtr_bus = pirq_router_bus; - pirq->rtr_devfn = PCI_DEVFN(0x14, 4); - - pirq->exclusive_irqs = 0; - - pirq->rtr_vendor = 0x1002; - pirq->rtr_device = 0x4384; - - pirq->miniport_data = 0; - - memset(pirq->rfu, 0, sizeof(pirq->rfu)); - - pirq_info = (void *)(&pirq->checksum + 1); - slot_num = 0; - - /* pci bridge */ - write_pirq_info(pirq_info, pirq_router_bus, PCI_DEVFN(0x14, 4), - 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, - 0); - pirq_info++; - slot_num++; - - pirq->size = 32 + 16 * slot_num; - - for (i = 0; i < pirq->size; i++) - sum += v[i]; - - sum = pirq->checksum - sum; - if (sum != pirq->checksum) { - pirq->checksum = sum; - } - - printk(BIOS_INFO, "write_pirq_routing_table done.\n"); - - return (unsigned long)pirq_info; -} diff --git a/src/mainboard/amd/mahogany_fam10/mainboard.c b/src/mainboard/amd/mahogany_fam10/mainboard.c deleted file mode 100644 index 4120338e41..0000000000 --- a/src/mainboard/amd/mahogany_fam10/mainboard.c +++ /dev/null @@ -1,103 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2010 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include -#include -#include -#include -#include -#include - -/* - * Mahogany uses GPIO 6 as PCIe slot reset, GPIO4 as GFX slot reset. We need to - * pull it up before training the slot. - ***/ -void set_pcie_dereset(void) -{ - u16 word; - struct device *sm_dev; - /* GPIO 6 reset PCIe slot, GPIO 4 reset GFX PCIe */ - sm_dev = pcidev_on_root(0x14, 0); - - word = pci_read_config16(sm_dev, 0xA8); - word |= (1 << 0) | (1 << 2); /* Set Gpio6,4 as output */ - word &= ~((1 << 8) | (1 << 10)); - pci_write_config16(sm_dev, 0xA8, word); -} - -void set_pcie_reset(void) -{ - u16 word; - struct device *sm_dev; - /* GPIO 6 reset PCIe slot, GPIO 4 reset GFX PCIe */ - sm_dev = pcidev_on_root(0x14, 0); - - word = pci_read_config16(sm_dev, 0xA8); - word &= ~((1 << 0) | (1 << 2)); /* Set Gpio6,4 as output */ - word &= ~((1 << 8) | (1 << 10)); - pci_write_config16(sm_dev, 0xA8, word); -} - -#if 0 /* not tested yet. */ -/******************************************************** -* mahogany uses SB700 GPIO9 to detect IDE_DMA66. -* IDE_DMA66 is routed to GPIO 9. So we read Gpio 9 to -* get the cable type, 40 pin or 80 pin? -********************************************************/ -static void get_ide_dma66(void) -{ - u8 byte; - /*u32 sm_dev, ide_dev; */ - struct device *sm_dev, ide_dev; - - sm_dev = pcidev_on_root(0x14, 0); - - byte = pci_read_config8(sm_dev, 0xA9); - byte |= (1 << 5); /* Set Gpio9 as input */ - pci_write_config8(sm_dev, 0xA9, byte); - - ide_dev = pcidev_on_root(0x14, 1); - byte = pci_read_config8(ide_dev, 0x56); - byte &= ~(7 << 0); - if ((1 << 5) & pci_read_config8(sm_dev, 0xAA)) - byte |= 2 << 0; /* mode 2 */ - else - byte |= 5 << 0; /* mode 5 */ - pci_write_config8(ide_dev, 0x56, byte); -} -#endif /* get_ide_dma66() */ - -int is_dev3_present(void) -{ - return 0; -} - -/************************************************* -* enable the dedicated function in mahogany board. -* This function called early than rs780_enable. -*************************************************/ -static void mainboard_enable(struct device *dev) -{ - printk(BIOS_INFO, "Mainboard MAHOGANY Enable. dev=0x%p\n", dev); - - set_pcie_dereset(); - /* get_ide_dma66(); */ -} - -struct chip_operations mainboard_ops = { - .enable_dev = mainboard_enable, -}; diff --git a/src/mainboard/amd/mahogany_fam10/mptable.c b/src/mainboard/amd/mahogany_fam10/mptable.c deleted file mode 100644 index 090fd54331..0000000000 --- a/src/mainboard/amd/mahogany_fam10/mptable.c +++ /dev/null @@ -1,102 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2010 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include -#include -#include - -extern u32 apicid_sb700; - - -static void *smp_write_config_table(void *v) -{ - struct mp_config_table *mc; - int bus_isa; - - mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); - - mptable_init(mc, LOCAL_APIC_ADDR); - - smp_write_processors(mc); - - mptable_write_buses(mc, NULL, &bus_isa); - - /* I/O APICs: APIC ID Version State Address */ - { - struct device *dev; - u32 dword; - u8 byte; - - dev = - dev_find_slot(pirq_router_bus, - PCI_DEVFN(0x14, 0)); - if (dev) { - dword = pci_read_config32(dev, 0x74) & 0xfffffff0; - smp_write_ioapic(mc, apicid_sb700, - 0x11,(void *) dword); - - /* Initialize interrupt mapping */ - /* aza */ - byte = pci_read_config8(dev, 0x63); - byte &= 0xf8; - byte |= 0; /* 0: INTA, ...., 7: INTH */ - pci_write_config8(dev, 0x63, byte); - - /* SATA */ - dword = pci_read_config32(dev, 0xac); - dword &= ~(7 << 26); - dword |= 6 << 26; /* 0: INTA, ...., 7: INTH */ - /* dword |= 1 << 22; PIC and APIC co exists */ - pci_write_config32(dev, 0xac, dword); - - /* - * 00:12.0: PROG SATA : INT F - * 00:13.0: INTA USB_0 - * 00:13.1: INTB USB_1 - * 00:13.2: INTC USB_2 - * 00:13.3: INTD USB_3 - * 00:13.4: INTC USB_4 - * 00:13.5: INTD USB2 - * 00:14.1: INTA IDE - * 00:14.2: Prog HDA : INT E - * 00:14.5: INTB ACI - * 00:14.6: INTB MCI - */ - } - } - - /* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ -#define IO_LOCAL_INT(type, intr, apicid, pin) \ - smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin)); - - mptable_add_isa_interrupts(mc, bus_isa, apicid_sb700, 0); - - /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ - IO_LOCAL_INT(mp_ExtINT, 0x0, MP_APIC_ALL, 0x0); - IO_LOCAL_INT(mp_NMI, 0x0, MP_APIC_ALL, 0x1); - /* There is no extension information... */ - - /* Compute the checksums */ - return mptable_finalize(mc); -} - -unsigned long write_smp_table(unsigned long addr) -{ - void *v; - v = smp_write_floating_table(addr, 0); - return (unsigned long)smp_write_config_table(v); -} diff --git a/src/mainboard/amd/mahogany_fam10/resourcemap.c b/src/mainboard/amd/mahogany_fam10/resourcemap.c deleted file mode 100644 index 80d2d9d05c..0000000000 --- a/src/mainboard/amd/mahogany_fam10/resourcemap.c +++ /dev/null @@ -1,279 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2010 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - - - -#include -#include - -void setup_mb_resource_map(void) -{ - static const unsigned int register_values[] = { - /* Careful set limit registers before base registers which contain the enables */ - /* DRAM Limit i Registers - * F1:0x44 i = 0 - * F1:0x4C i = 1 - * F1:0x54 i = 2 - * F1:0x5C i = 3 - * F1:0x64 i = 4 - * F1:0x6C i = 5 - * F1:0x74 i = 6 - * F1:0x7C i = 7 - * [ 2: 0] Destination Node ID - * 000 = Node 0 - * 001 = Node 1 - * 010 = Node 2 - * 011 = Node 3 - * 100 = Node 4 - * 101 = Node 5 - * 110 = Node 6 - * 111 = Node 7 - * [ 7: 3] Reserved - * [10: 8] Interleave select - * specifies the values of A[14:12] to use with interleave enable. - * [15:11] Reserved - * [31:16] DRAM Limit Address i Bits 39-24 - * This field defines the upper address bits of a 40 bit address - * that define the end of the DRAM region. - */ -// ADDRMAP_REG(0x44), 0x0000f8f8, 0x00000000, // Don't touch it, we need it for CONFIG_CAR_FAM10 - ADDRMAP_REG(0x4C), 0x0000f8f8, 0x00000001, - ADDRMAP_REG(0x54), 0x0000f8f8, 0x00000002, - ADDRMAP_REG(0x5C), 0x0000f8f8, 0x00000003, - ADDRMAP_REG(0x64), 0x0000f8f8, 0x00000004, - ADDRMAP_REG(0x6C), 0x0000f8f8, 0x00000005, - ADDRMAP_REG(0x74), 0x0000f8f8, 0x00000006, - ADDRMAP_REG(0x7C), 0x0000f8f8, 0x00000007, - /* DRAM Base i Registers - * F1:0x40 i = 0 - * F1:0x48 i = 1 - * F1:0x50 i = 2 - * F1:0x58 i = 3 - * F1:0x60 i = 4 - * F1:0x68 i = 5 - * F1:0x70 i = 6 - * F1:0x78 i = 7 - * [ 0: 0] Read Enable - * 0 = Reads Disabled - * 1 = Reads Enabled - * [ 1: 1] Write Enable - * 0 = Writes Disabled - * 1 = Writes Enabled - * [ 7: 2] Reserved - * [10: 8] Interleave Enable - * 000 = No interleave - * 001 = Interleave on A[12] (2 nodes) - * 010 = reserved - * 011 = Interleave on A[12] and A[14] (4 nodes) - * 100 = reserved - * 101 = reserved - * 110 = reserved - * 111 = Interleve on A[12] and A[13] and A[14] (8 nodes) - * [15:11] Reserved - * [13:16] DRAM Base Address i Bits 39-24 - * This field defines the upper address bits of a 40-bit address - * that define the start of the DRAM region. - */ -// ADDRMAP_REG(0x40), 0x0000f8fc, 0x00000000,// don't touch it, we need it for CONFIG_CAR_FAM10 - ADDRMAP_REG(0x48), 0x0000f8fc, 0x00000000, - ADDRMAP_REG(0x50), 0x0000f8fc, 0x00000000, - ADDRMAP_REG(0x58), 0x0000f8fc, 0x00000000, - ADDRMAP_REG(0x60), 0x0000f8fc, 0x00000000, - ADDRMAP_REG(0x68), 0x0000f8fc, 0x00000000, - ADDRMAP_REG(0x70), 0x0000f8fc, 0x00000000, - ADDRMAP_REG(0x78), 0x0000f8fc, 0x00000000, - - /* Memory-Mapped I/O Limit i Registers - * F1:0x84 i = 0 - * F1:0x8C i = 1 - * F1:0x94 i = 2 - * F1:0x9C i = 3 - * F1:0xA4 i = 4 - * F1:0xAC i = 5 - * F1:0xB4 i = 6 - * F1:0xBC i = 7 - * [ 2: 0] Destination Node ID - * 000 = Node 0 - * 001 = Node 1 - * 010 = Node 2 - * 011 = Node 3 - * 100 = Node 4 - * 101 = Node 5 - * 110 = Node 6 - * 111 = Node 7 - * [ 3: 3] Reserved - * [ 5: 4] Destination Link ID - * 00 = Link 0 - * 01 = Link 1 - * 10 = Link 2 - * 11 = Reserved - * [ 6: 6] Reserved - * [ 7: 7] Non-Posted - * 0 = CPU writes may be posted - * 1 = CPU writes must be non-posted - * [31: 8] Memory-Mapped I/O Limit Address i (39-16) - * This field defines the upp address bits of a 40-bit address that - * defines the end of a memory-mapped I/O region n - */ - ADDRMAP_REG(0x84), 0x00000048, 0x00000000, - ADDRMAP_REG(0x8C), 0x00000048, 0x00000000, - ADDRMAP_REG(0x94), 0x00000048, 0x00000000, - ADDRMAP_REG(0x9C), 0x00000048, 0x00000000, - ADDRMAP_REG(0xA4), 0x00000048, 0x00000000, - ADDRMAP_REG(0xAC), 0x00000048, 0x00000000, - ADDRMAP_REG(0xB4), 0x00000048, 0x00000000, -// ADDRMAP_REG(0xBC), 0x00000048, 0x00ffff00, - - /* Memory-Mapped I/O Base i Registers - * F1:0x80 i = 0 - * F1:0x88 i = 1 - * F1:0x90 i = 2 - * F1:0x98 i = 3 - * F1:0xA0 i = 4 - * F1:0xA8 i = 5 - * F1:0xB0 i = 6 - * F1:0xB8 i = 7 - * [ 0: 0] Read Enable - * 0 = Reads disabled - * 1 = Reads Enabled - * [ 1: 1] Write Enable - * 0 = Writes disabled - * 1 = Writes Enabled - * [ 2: 2] Cpu Disable - * 0 = Cpu can use this I/O range - * 1 = Cpu requests do not use this I/O range - * [ 3: 3] Lock - * 0 = base/limit registers i are read/write - * 1 = base/limit registers i are read-only - * [ 7: 4] Reserved - * [31: 8] Memory-Mapped I/O Base Address i (39-16) - * This field defines the upper address bits of a 40bit address - * that defines the start of memory-mapped I/O region i - */ - ADDRMAP_REG(0x80), 0x000000f0, 0x00000000, - ADDRMAP_REG(0x88), 0x000000f0, 0x00000000, - ADDRMAP_REG(0x90), 0x000000f0, 0x00000000, - ADDRMAP_REG(0x98), 0x000000f0, 0x00000000, - ADDRMAP_REG(0xA0), 0x000000f0, 0x00000000, - ADDRMAP_REG(0xA8), 0x000000f0, 0x00000000, - ADDRMAP_REG(0xB0), 0x000000f0, 0x00000000, -// ADDRMAP_REG(0xB8), 0x000000f0, 0x00fc0003, - - /* PCI I/O Limit i Registers - * F1:0xC4 i = 0 - * F1:0xCC i = 1 - * F1:0xD4 i = 2 - * F1:0xDC i = 3 - * [ 2: 0] Destination Node ID - * 000 = Node 0 - * 001 = Node 1 - * 010 = Node 2 - * 011 = Node 3 - * 100 = Node 4 - * 101 = Node 5 - * 110 = Node 6 - * 111 = Node 7 - * [ 3: 3] Reserved - * [ 5: 4] Destination Link ID - * 00 = Link 0 - * 01 = Link 1 - * 10 = Link 2 - * 11 = reserved - * [11: 6] Reserved - * [24:12] PCI I/O Limit Address i - * This field defines the end of PCI I/O region n - * [31:25] Reserved - */ -// ADDRMAP_REG(0xC4), 0xFE000FC8, 0x01fff000, - ADDRMAP_REG(0xCC), 0xFE000FC8, 0x00000000, - ADDRMAP_REG(0xD4), 0xFE000FC8, 0x00000000, - ADDRMAP_REG(0xDC), 0xFE000FC8, 0x00000000, - - /* PCI I/O Base i Registers - * F1:0xC0 i = 0 - * F1:0xC8 i = 1 - * F1:0xD0 i = 2 - * F1:0xD8 i = 3 - * [ 0: 0] Read Enable - * 0 = Reads Disabled - * 1 = Reads Enabled - * [ 1: 1] Write Enable - * 0 = Writes Disabled - * 1 = Writes Enabled - * [ 3: 2] Reserved - * [ 4: 4] VGA Enable - * 0 = VGA matches Disabled - * 1 = matches all address < 64K and where A[9:0] is in the - * range 3B0-3BB or 3C0-3DF independen of the base & limit registers - * [ 5: 5] ISA Enable - * 0 = ISA matches Disabled - * 1 = Blocks address < 64K and in the last 768 bytes of eack 1K block - * from matching agains this base/limit pair - * [11: 6] Reserved - * [24:12] PCI I/O Base i - * This field defines the start of PCI I/O region n - * [31:25] Reserved - */ -// ADDRMAP_REG(0xC0), 0xFE000FCC, 0x00000003, - ADDRMAP_REG(0xC8), 0xFE000FCC, 0x00000000, - ADDRMAP_REG(0xD0), 0xFE000FCC, 0x00000000, - ADDRMAP_REG(0xD8), 0xFE000FCC, 0x00000000, - - /* Config Base and Limit i Registers - * F1:0xE0 i = 0 - * F1:0xE4 i = 1 - * F1:0xE8 i = 2 - * F1:0xEC i = 3 - * [ 0: 0] Read Enable - * 0 = Reads Disabled - * 1 = Reads Enabled - * [ 1: 1] Write Enable - * 0 = Writes Disabled - * 1 = Writes Enabled - * [ 2: 2] Device Number Compare Enable - * 0 = The ranges are based on bus number - * 1 = The ranges are ranges of devices on bus 0 - * [ 3: 3] Reserved - * [ 6: 4] Destination Node - * 000 = Node 0 - * 001 = Node 1 - * 010 = Node 2 - * 011 = Node 3 - * 100 = Node 4 - * 101 = Node 5 - * 110 = Node 6 - * 111 = Node 7 - * [ 7: 7] Reserved - * [ 9: 8] Destination Link - * 00 = Link 0 - * 01 = Link 1 - * 10 = Link 2 - * 11 - Reserved - * [15:10] Reserved - * [23:16] Bus Number Base i - * This field defines the lowest bus number in configuration region i - * [31:24] Bus Number Limit i - * This field defines the highest bus number in configuration regin i - */ -// ADDRMAP_REG(0xE0), 0x0000FC88, 0x06000003, // AMD 8111 on link0 of CPU 0 - ADDRMAP_REG(0xE4), 0x0000FC88, 0x00000000, - ADDRMAP_REG(0xE8), 0x0000FC88, 0x00000000, - ADDRMAP_REG(0xEC), 0x0000FC88, 0x00000000, - }; - - int max; - max = ARRAY_SIZE(register_values); - setup_resource_map(register_values, max); -} diff --git a/src/mainboard/amd/mahogany_fam10/romstage.c b/src/mainboard/amd/mahogany_fam10/romstage.c deleted file mode 100644 index 3397d26d96..0000000000 --- a/src/mainboard/amd/mahogany_fam10/romstage.c +++ /dev/null @@ -1,223 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2010 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -//#define SYSTEM_TYPE 0 /* SERVER */ -#define SYSTEM_TYPE 1 /* DESKTOP */ -//#define SYSTEM_TYPE 2 /* MOBILE */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#define SERIAL_DEV PNP_DEV(0x2e, IT8718F_SP1) - -#include "cpu/amd/quadcore/quadcore.c" - -int spd_read_byte(unsigned int device, unsigned int address); - - -int spd_read_byte(u32 device, u32 address) -{ - return do_smbus_read_byte(SMBUS_IO_BASE, device, address); -} - - -void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) -{ - struct sys_info *sysinfo = get_sysinfo(); - static const u8 spd_addr[] = {RC00, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, }; - u32 bsp_apicid = 0, val; - msr_t msr; - - timestamp_init(timestamp_get()); - timestamp_add_now(TS_START_ROMSTAGE); - - if (!cpu_init_detectedx && boot_cpu()) { - /* Nothing special needs to be done to find bus 0 */ - /* Allow the HT devices to be found */ - /* mov bsp to bus 0xff when > 8 nodes */ - set_bsp_node_CHtExtNodeCfgEn(); - enumerate_ht_chain(); - sb7xx_51xx_pci_port80(); - } - - post_code(0x30); - - if (bist == 0) { - bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo); /* mmconf is inited in init_cpus */ - /* All cores run this but the BSP(node0,core0) is the only core that returns. */ - } - - post_code(0x32); - - enable_rs780_dev8(); - sb7xx_51xx_lpc_init(); - - ite_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); - - console_init(); - - /* Halt if there was a built in self test failure */ - report_bist_failure(bist); - - // Load MPB - val = cpuid_eax(1); - printk(BIOS_DEBUG, "BSP Family_Model: %08x\n", val); - printk(BIOS_DEBUG, "*sysinfo range: [%p,%p]\n",sysinfo,sysinfo+1); - printk(BIOS_DEBUG, "bsp_apicid = %02x\n", bsp_apicid); - printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx); - - /* Setup sysinfo defaults */ - set_sysinfo_in_ram(0); - - update_microcode(val); - - post_code(0x33); - - cpuSetAMDMSR(0); - post_code(0x34); - - amd_ht_init(sysinfo); - post_code(0x35); - - /* Setup nodes PCI space and start core 0 AP init. */ - finalize_node_setup(sysinfo); - - /* Setup any mainboard PCI settings etc. */ - setup_mb_resource_map(); - post_code(0x36); - - /* wait for all the APs core0 started by finalize_node_setup. */ - /* FIXME: A bunch of cores are going to start output to serial at once. - It would be nice to fixup prink spinlocks for ROM XIP mode. - I think it could be done by putting the spinlock flag in the cache - of the BSP located right after sysinfo. - */ - wait_all_core0_started(); - - #if CONFIG(LOGICAL_CPUS) - /* Core0 on each node is configured. Now setup any additional cores. */ - printk(BIOS_DEBUG, "start_other_cores()\n"); - start_other_cores(bsp_apicid); - post_code(0x37); - wait_all_other_cores_started(bsp_apicid); - #endif - - post_code(0x38); - - /* run _early_setup before soft-reset. */ - rs780_early_setup(); - sb7xx_51xx_early_setup(); - - #if CONFIG(SET_FIDVID) - msr = rdmsr(MSR_COFVID_STS); - printk(BIOS_DEBUG, "\nBegin FIDVID MSR 0xc0010071 0x%08x 0x%08x\n", msr.hi, msr.lo); - - /* FIXME: The sb fid change may survive the warm reset and only - need to be done once.*/ - enable_fid_change_on_sb(sysinfo->sbbusn, sysinfo->sbdn); - - post_code(0x39); - - if (!warm_reset_detect(0)) { // BSP is node 0 - init_fidvid_bsp(bsp_apicid, sysinfo->nodes); - } else { - init_fidvid_stage2(bsp_apicid, 0); // BSP is node 0 - } - - post_code(0x3A); - - /* show final fid and vid */ - msr = rdmsr(MSR_COFVID_STS); - printk(BIOS_DEBUG, "End FIDVIDMSR 0xc0010071 0x%08x 0x%08x\n", msr.hi, msr.lo); - #endif - - rs780_htinit(); - - /* Reset for HT, FIDVID, PLL and errata changes to take affect. */ - if (!warm_reset_detect(0)) { - printk(BIOS_INFO, "...WARM RESET...\n\n\n"); - soft_reset(); - die("After soft_reset - shouldn't see this message!!!\n"); - } - - post_code(0x3B); - - /* It's the time to set ctrl in sysinfo now; */ - printk(BIOS_DEBUG, "fill_mem_ctrl()\n"); - fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr); - - post_code(0x40); - - raminit_amdmct(sysinfo); - - cbmem_initialize_empty(); - post_code(0x41); - - amdmct_cbmem_store_info(sysinfo); - - sb7xx_51xx_before_pci_init(); - - post_code(0x42); -} - -/** - * BOOL AMD_CB_ManualBUIDSwapList(u8 Node, u8 Link, u8 **List) - * Description: - * This routine is called every time a non-coherent chain is processed. - * BUID assignment may be controlled explicitly on a non-coherent chain. Provide a - * swap list. The first part of the list controls the BUID assignment and the - * second part of the list provides the device to device linking. Device orientation - * can be detected automatically, or explicitly. See documentation for more details. - * - * Automatic non-coherent init assigns BUIDs starting at 1 and incrementing sequentially - * based on each device's unit count. - * - * Parameters: - * @param[in] node = The node on which this chain is located - * @param[in] link = The link on the host for this chain - * @param[out] List = supply a pointer to a list - */ -BOOL AMD_CB_ManualBUIDSwapList (u8 node, u8 link, const u8 **List) -{ - static const u8 swaplist[] = {0, 1, 0xFF, 0, 0xFF}; - /* If the BUID was adjusted in early_ht we need to do the manual override */ - if ((node == 0) && (link == 0)) { /* BSP SB link */ - *List = swaplist; - return 1; - } - - return 0; -} diff --git a/src/mainboard/amd/serengeti_cheetah_fam10/Kconfig b/src/mainboard/amd/serengeti_cheetah_fam10/Kconfig deleted file mode 100644 index 9d01f2bd6d..0000000000 --- a/src/mainboard/amd/serengeti_cheetah_fam10/Kconfig +++ /dev/null @@ -1,56 +0,0 @@ -if BOARD_AMD_SERENGETI_CHEETAH_FAM10 - -config BOARD_SPECIFIC_OPTIONS - def_bool y - select CPU_AMD_SOCKET_F_1207 - select DIMM_DDR2 - select DIMM_REGISTERED - select NORTHBRIDGE_AMD_AMDFAM10 - select SOUTHBRIDGE_AMD_AMD8111 - select SOUTHBRIDGE_AMD_AMD8132 - select HT_CHAIN_DISTRIBUTE - select SUPERIO_WINBOND_W83627HF - select HAVE_OPTION_TABLE - select HAVE_PIRQ_TABLE - select HAVE_MP_TABLE - select SB_HT_CHAIN_UNITID_OFFSET_ONLY - select HAVE_ACPI_TABLES - select BOARD_ROMSIZE_KB_1024 - select ENABLE_APIC_EXT_ID - select LIFT_BSP_APIC_ID - select DRIVERS_I2C_I2CMUX2 - -config MAINBOARD_DIR - string - default amd/serengeti_cheetah_fam10 - -config APIC_ID_OFFSET - hex - default 0x0 - -config MAINBOARD_PART_NUMBER - string - default "Serengeti Cheetah (Fam10)" - -# 6 * MAX_PHYSICAL_CPUS -config MAX_CPUS - int - default 48 - -config MAX_PHYSICAL_CPUS - int - default 8 - -config HT_CHAIN_END_UNITID_BASE - hex - default 0x6 - -config HT_CHAIN_UNITID_BASE - hex - default 0xa - -config IRQ_SLOT_COUNT - int - default 11 - -endif # BOARD_AMD_SERENGETI_CHEETAH_FAM10 diff --git a/src/mainboard/amd/serengeti_cheetah_fam10/Kconfig.name b/src/mainboard/amd/serengeti_cheetah_fam10/Kconfig.name deleted file mode 100644 index 66b7c395ab..0000000000 --- a/src/mainboard/amd/serengeti_cheetah_fam10/Kconfig.name +++ /dev/null @@ -1,2 +0,0 @@ -config BOARD_AMD_SERENGETI_CHEETAH_FAM10 - bool "Serengeti Cheetah (Fam10)" diff --git a/src/mainboard/amd/serengeti_cheetah_fam10/Makefile.inc b/src/mainboard/amd/serengeti_cheetah_fam10/Makefile.inc deleted file mode 100644 index c9a38fab7e..0000000000 --- a/src/mainboard/amd/serengeti_cheetah_fam10/Makefile.inc +++ /dev/null @@ -1,8 +0,0 @@ -$(eval $(call asl_template,ssdt2)) -$(eval $(call asl_template,ssdt3)) -$(eval $(call asl_template,ssdt4)) -$(eval $(call asl_template,ssdt5)) - -romstage-y += resourcemap.c - -ramstage-y += get_bus_conf.c diff --git a/src/mainboard/amd/serengeti_cheetah_fam10/acpi/amd8111.asl b/src/mainboard/amd/serengeti_cheetah_fam10/acpi/amd8111.asl deleted file mode 100644 index f6a1954aa1..0000000000 --- a/src/mainboard/amd/serengeti_cheetah_fam10/acpi/amd8111.asl +++ /dev/null @@ -1,175 +0,0 @@ -// -// This file is part of the coreboot project. -// -// Copyright (C) 2007 Advanced Micro Devices, Inc. -// -// This program is free software; you can redistribute it and/or modify -// it under the terms of the GNU General Public License as published by -// the Free Software Foundation; version 2 of the License. -// -// This program is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. -// - -//AMD8111 - Name (APIC, Package (0x04) - { - Package (0x04) { 0x0004FFFF, 0x00, 0x00, 0x10},// 0x0004ffff : assusme 8131 is present - Package (0x04) { 0x0004FFFF, 0x01, 0x00, 0x11}, - Package (0x04) { 0x0004FFFF, 0x02, 0x00, 0x12}, - Package (0x04) { 0x0004FFFF, 0x03, 0x00, 0x13} - }) - - Name (PICM, Package (0x04) - { - Package (0x04) { 0x0004FFFF, 0x00, \_SB.PCI0.LNKA, 0x00}, - Package (0x04) { 0x0004FFFF, 0x01, \_SB.PCI0.LNKB, 0x00}, - Package (0x04) { 0x0004FFFF, 0x02, \_SB.PCI0.LNKC, 0x00}, - Package (0x04) { 0x0004FFFF, 0x03, \_SB.PCI0.LNKD, 0x00} - }) - - Name (DNCG, Ones) - - Method (_PRT, 0, NotSerialized) - { - If (LEqual (^DNCG, Ones)) { - Store (DADD(\_SB.PCI0.SBDN, 0x0001ffff), Local0) - // Update the Device Number according to SBDN - Store(Local0, Index (DeRefOf (Index (PICM, 0)), 0)) - Store(Local0, Index (DeRefOf (Index (PICM, 1)), 0)) - Store(Local0, Index (DeRefOf (Index (PICM, 2)), 0)) - Store(Local0, Index (DeRefOf (Index (PICM, 3)), 0)) - Store(Local0, Index (DeRefOf (Index (APIC, 0)), 0)) - Store(Local0, Index (DeRefOf (Index (APIC, 1)), 0)) - Store(Local0, Index (DeRefOf (Index (APIC, 2)), 0)) - Store(Local0, Index (DeRefOf (Index (APIC, 3)), 0)) - Store (0x00, ^DNCG) - } - If (LNot (PICF)) {Return (PICM)} - Else {Return (APIC)} - } - - Device (SBC3) - { - // ACPI smbus it should be 0x00040003 if 8131 present - Method (_ADR, 0, NotSerialized) - { - Return (DADD(\_SB.PCI0.SBDN, 0x00010003)) - } - OperationRegion (PIRQ, PCI_Config, 0x56, 0x02) - Field (PIRQ, ByteAcc, Lock, Preserve) - { - PIBA, 8, - PIDC, 8 - } -// -// OperationRegion (TS3_, PCI_Config, 0xC4, 0x02) -// Field (TS3_, DWordAcc, NoLock, Preserve) -// { -// PTS3, 16 -// } -// - } - - Device (HPET) - { - Name (HPT, 0x00) - Name (_HID, EisaId ("PNP0103")) - Name (_UID, 0x00) - Method (_STA, 0, NotSerialized) - { - Return (0x0F) - } - - Method (_CRS, 0, NotSerialized) - { - Name (BUF0, ResourceTemplate () - { - Memory32Fixed (ReadWrite, 0xFED00000, 0x00000400) - }) - Return (BUF0) - } - } - - #include "amd8111_pic.asl" - - #include "amd8111_isa.asl" - - Device (TP2P) - { - // 8111 P2P and it should 0x00030000 when 8131 present - Method (_ADR, 0, NotSerialized) - { - Return (DADD(\_SB.PCI0.SBDN, 0x00000000)) - } - - Method (_PRW, 0, NotSerialized) - { - If (CondRefOf (\_S3)) { Return (Package (0x02) { 0x08, 0x03 }) } - Else { Return (Package (0x02) { 0x08, 0x01 }) } - } - - Device (USB0) - { - Name (_ADR, 0x00000000) - Method (_PRW, 0, NotSerialized) - { - If (CondRefOf (\_S3)) { Return (Package (0x02) { 0x0F, 0x03 }) } - Else { Return (Package (0x02) { 0x0F, 0x01 }) } - } - } - - Device (USB1) - { - Name (_ADR, 0x00000001) - Method (_PRW, 0, NotSerialized) - { - If (CondRefOf (\_S3)) { Return (Package (0x02) { 0x0F, 0x03 }) } - Else { Return (Package (0x02) { 0x0F, 0x01 }) } - } - } - - Name (APIC, Package (0x0C) - { - Package (0x04) { 0x0000FFFF, 0x00, 0x00, 0x10 }, //USB - Package (0x04) { 0x0000FFFF, 0x01, 0x00, 0x11 }, - Package (0x04) { 0x0000FFFF, 0x02, 0x00, 0x12 }, - Package (0x04) { 0x0000FFFF, 0x03, 0x00, 0x13 }, - - Package (0x04) { 0x0004FFFF, 0x00, 0x00, 0x10 }, //Slot 4 - Package (0x04) { 0x0004FFFF, 0x01, 0x00, 0x11 }, - Package (0x04) { 0x0004FFFF, 0x02, 0x00, 0x12 }, - Package (0x04) { 0x0004FFFF, 0x03, 0x00, 0x13 }, - - Package (0x04) { 0x0005FFFF, 0x00, 0x00, 0x11 }, //Slot 3 - Package (0x04) { 0x0005FFFF, 0x01, 0x00, 0x12 }, - Package (0x04) { 0x0005FFFF, 0x02, 0x00, 0x13 }, - Package (0x04) { 0x0005FFFF, 0x03, 0x00, 0x10 } - }) - - Name (PICM, Package (0x0C) - { - Package (0x04) { 0x0000FFFF, 0x00, \_SB.PCI0.LNKA, 0x00 }, //USB - Package (0x04) { 0x0000FFFF, 0x01, \_SB.PCI0.LNKB, 0x00 }, - Package (0x04) { 0x0000FFFF, 0x02, \_SB.PCI0.LNKC, 0x00 }, - Package (0x04) { 0x0000FFFF, 0x03, \_SB.PCI0.LNKD, 0x00 }, - - Package (0x04) { 0x0004FFFF, 0x00, \_SB.PCI0.LNKA, 0x00 }, //Slot 4 - Package (0x04) { 0x0004FFFF, 0x01, \_SB.PCI0.LNKB, 0x00 }, - Package (0x04) { 0x0004FFFF, 0x02, \_SB.PCI0.LNKC, 0x00 }, - Package (0x04) { 0x0004FFFF, 0x03, \_SB.PCI0.LNKD, 0x00 }, - - Package (0x04) { 0x0005FFFF, 0x00, \_SB.PCI0.LNKB, 0x00 }, //Slot 3 - Package (0x04) { 0x0005FFFF, 0x01, \_SB.PCI0.LNKC, 0x00 }, - Package (0x04) { 0x0005FFFF, 0x02, \_SB.PCI0.LNKD, 0x00 }, - Package (0x04) { 0x0005FFFF, 0x03, \_SB.PCI0.LNKA, 0x00 } - }) - - Method (_PRT, 0, NotSerialized) - { - If (LNot (PICF)) { Return (PICM) } - Else { Return (APIC) } - } - } diff --git a/src/mainboard/amd/serengeti_cheetah_fam10/acpi/amd8111_isa.asl b/src/mainboard/amd/serengeti_cheetah_fam10/acpi/amd8111_isa.asl deleted file mode 100644 index d7c8d81cc8..0000000000 --- a/src/mainboard/amd/serengeti_cheetah_fam10/acpi/amd8111_isa.asl +++ /dev/null @@ -1,190 +0,0 @@ -// -// This file is part of the coreboot project. -// -// Copyright (C) 2007 Advanced Micro Devices, Inc. -// -// This program is free software; you can redistribute it and/or modify -// it under the terms of the GNU General Public License as published by -// the Free Software Foundation; version 2 of the License. -// -// This program is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. -// - -#include -#include - -//AMD8111 isa - - Device (ISA) - { - // lpc 0x00040000 - Method (_ADR, 0, NotSerialized) - { - Return (DADD(\_SB.PCI0.SBDN, 0x00010000)) - } - - OperationRegion (PIRY, PCI_Config, 0x51, 0x02) // LPC Decode Registers - Field (PIRY, ByteAcc, NoLock, Preserve) - { - Z000, 2, // Parallel Port Range - , 1, - ECP, 1, // ECP Enable - FDC1, 1, // Floppy Drive Controller 1 - FDC2, 1, // Floppy Drive Controller 2 - Offset (0x01), - Z001, 3, // Serial Port A Range - SAEN, 1, // Serial Post A Enabled - Z002, 3, // Serial Port B Range - SBEN, 1 // Serial Post B Enabled - } - - Device (PIC) - { - Name (_HID, EisaId ("PNP0000")) - Name (_CRS, ResourceTemplate () - { - IO (Decode16, 0x0020, 0x0020, 0x01, 0x02) - IO (Decode16, 0x00A0, 0x00A0, 0x01, 0x02) - IRQ (Edge, ActiveHigh, Exclusive) {2} - }) - } - - Device (DMA1) - { - Name (_HID, EisaId ("PNP0200")) - Name (_CRS, ResourceTemplate () - { - IO (Decode16, 0x0000, 0x0000, 0x01, 0x10) - IO (Decode16, 0x0080, 0x0080, 0x01, 0x10) - IO (Decode16, 0x00C0, 0x00C0, 0x01, 0x20) - DMA (Compatibility, NotBusMaster, Transfer16) {4} - }) - } - - Device (TMR) - { - Name (_HID, EisaId ("PNP0100")) - Name (_CRS, ResourceTemplate () - { - IO (Decode16, 0x0040, 0x0040, 0x01, 0x04) - IRQ (Edge, ActiveHigh, Exclusive) {0} - }) - } - - Device (RTC) - { - Name (_HID, EisaId ("PNP0B00")) - Name (_CRS, ResourceTemplate () - { - IO (Decode16, 0x0070, 0x0070, 0x01, 0x06) - IRQ (Edge, ActiveHigh, Exclusive) {8} - }) - } - - Device (SPKR) - { - Name (_HID, EisaId ("PNP0800")) - Name (_CRS, ResourceTemplate () - { - IO (Decode16, 0x0061, 0x0061, 0x01, 0x01) - }) - } - - Device (COPR) - { - Name (_HID, EisaId ("PNP0C04")) - Name (_CRS, ResourceTemplate () - { - IO (Decode16, 0x00F0, 0x00F0, 0x01, 0x10) - IRQ (Edge, ActiveHigh, Exclusive) {13} - }) - } - - Device (SYSR) - { - Name (_HID, EisaId ("PNP0C02")) - Name (_UID, 0x00) - Name (SYR1, ResourceTemplate () - { - IO (Decode16, 0x04D0, 0x04D0, 0x01, 0x02) //report Thor NVRAM - IO (Decode16, 0x1100, 0x117F, 0x01, 0x80) //report Thor NVRAM - IO (Decode16, 0x1180, 0x11FF, 0x01, 0x80) - IO (Decode16, 0x0010, 0x0010, 0x01, 0x10) - IO (Decode16, 0x0022, 0x0022, 0x01, 0x1E) - IO (Decode16, 0x0044, 0x0044, 0x01, 0x1C) - IO (Decode16, 0x0062, 0x0062, 0x01, 0x02) - IO (Decode16, 0x0065, 0x0065, 0x01, 0x0B) - IO (Decode16, 0x0076, 0x0076, 0x01, 0x0A) - IO (Decode16, 0x0090, 0x0090, 0x01, 0x10) - IO (Decode16, 0x00A2, 0x00A2, 0x01, 0x1E) - IO (Decode16, 0x00E0, 0x00E0, 0x01, 0x10) - IO (Decode16, 0x0B78, 0x0B78, 0x01, 0x04) // Added this to remove ACPI Unrepoted IO Error - IO (Decode16, 0x0190, 0x0190, 0x01, 0x04) // Added this to remove ACPI Unrepoted IO Error - }) - Method (_CRS, 0, NotSerialized) - { - Return (SYR1) - } - } - - Device (MEM) - { - Name (_HID, EisaId ("PNP0C02")) - Name (_UID, 0x01) - Method (_CRS, 0, NotSerialized) - { - Name (BUF0, ResourceTemplate () - { - Memory32Fixed (ReadWrite, 0x000E0000, 0x00020000) // BIOS E4000-FFFFF - Memory32Fixed (ReadWrite, 0x000C0000, 0x00010000) // video BIOS c0000-c8404 - Memory32Fixed (ReadWrite, IO_APIC_ADDR, 0x00001000) - Memory32Fixed (ReadWrite, 0xFFC00000, 0x00380000) // LPC forwarded, 4 MB w/ROM - Memory32Fixed (ReadWrite, LOCAL_APIC_ADDR, 0x00001000) - Memory32Fixed (ReadWrite, 0xFFF80000, 0x00080000) // Overlay BIOS - Memory32Fixed (ReadWrite, 0x00000000, 0x00000000) // Overlay BIOS - Memory32Fixed (ReadWrite, 0x00000000, 0x00000000) // Overlay BIOS - Memory32Fixed (ReadWrite, 0x00000000, 0x00000000) // Overlay BIOS - Memory32Fixed (ReadWrite, 0x00000000, 0x00000000) // Overlay BIOS - }) - // Read the Video Memory length - CreateDWordField (BUF0, 0x14, CLEN) - CreateDWordField (BUF0, 0x10, CBAS) - - ShiftLeft (VGA1, 0x09, Local0) - Store (Local0, CLEN) - - Return (BUF0) - } - } - - Device (PS2M) - { - Name (_HID, EisaId ("PNP0F13")) - Name (_CRS, ResourceTemplate () - { - IRQNoFlags () {12} - }) - Method (_STA, 0, NotSerialized) - { - And (FLG0, 0x04, Local0) - If (LEqual (Local0, 0x04)) { Return (0x0F) } - Else { Return (0x00) } - } - } - - Device (PS2K) - { - Name (_HID, EisaId ("PNP0303")) - Name (_CRS, ResourceTemplate () - { - IO (Decode16, 0x0060, 0x0060, 0x01, 0x01) - IO (Decode16, 0x0064, 0x0064, 0x01, 0x01) - IRQNoFlags () {1} - }) - } - #include "superio.asl" - - } diff --git a/src/mainboard/amd/serengeti_cheetah_fam10/acpi/amd8111_pic.asl b/src/mainboard/amd/serengeti_cheetah_fam10/acpi/amd8111_pic.asl deleted file mode 100644 index 982fb39740..0000000000 --- a/src/mainboard/amd/serengeti_cheetah_fam10/acpi/amd8111_pic.asl +++ /dev/null @@ -1,366 +0,0 @@ -// -// This file is part of the coreboot project. -// -// Copyright (C) 2007 Advanced Micro Devices, Inc. -// -// This program is free software; you can redistribute it and/or modify -// it under the terms of the GNU General Public License as published by -// the Free Software Foundation; version 2 of the License. -// -// This program is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. -// - -//AMD8111 pic LNKA B C D - - Device (LNKA) - { - Name (_HID, EisaId ("PNP0C0F")) - Name (_UID, 0x01) - Method (_STA, 0, NotSerialized) - { - And (\_SB.PCI0.SBC3.PIBA, 0x0F, Local0) - If (LEqual (Local0, 0x00)) { Return (0x09) } //Disabled - Else { Return (0x0B) } //Enabled - } - - Method (_PRS, 0, NotSerialized) - { - Name (BUFA, ResourceTemplate () - { - IRQ (Level, ActiveLow, Shared) {3,5,10,11} - }) - Return (BUFA) - } - - Method (_DIS, 0, NotSerialized) - { - Store (0x01, Local3) - And (\_SB.PCI0.SBC3.PIBA, 0x0F, Local1) - If (LGreater (Local1, 0x07)) - { - Subtract (Local1, 0x08, Local1) - } - - ShiftLeft (Local3, Local1, Local3) - Not (Local3, Local3) - And (\_SB.PCI0.SBC3.PIBA, 0xF0, \_SB.PCI0.SBC3.PIBA) - } - - Method (_CRS, 0, NotSerialized) - { - Name (BUFA, ResourceTemplate () - { - IRQ (Level, ActiveLow, Shared) {} - }) - CreateByteField (BUFA, 0x01, IRA1) - CreateByteField (BUFA, 0x02, IRA2) - Store (0x00, Local3) - Store (0x00, Local4) - And (\_SB.PCI0.SBC3.PIBA, 0x0F, Local1) - If (LNot (LEqual (Local1, 0x00))) - { // Routing enable - If (LGreater (Local1, 0x07)) - { - Subtract (Local1, 0x08, Local2) - ShiftLeft (One, Local2, Local4) - } - Else - { - If (LGreater (Local1, 0x00)) - { - ShiftLeft (One, Local1, Local3) - } - } - - Store (Local3, IRA1) - Store (Local4, IRA2) - } - - Return (BUFA) - } - - Method (_SRS, 1, NotSerialized) - { - CreateByteField (Arg0, 0x01, IRA1) - CreateByteField (Arg0, 0x02, IRA2) - ShiftLeft (IRA2, 0x08, Local0) - Or (Local0, IRA1, Local0) - Store (0x00, Local1) - ShiftRight (Local0, 0x01, Local0) - While (LGreater (Local0, 0x00)) - { - Increment (Local1) - ShiftRight (Local0, 0x01, Local0) - } - - And (\_SB.PCI0.SBC3.PIBA, 0xF0, \_SB.PCI0.SBC3.PIBA) - Or (\_SB.PCI0.SBC3.PIBA, Local1, \_SB.PCI0.SBC3.PIBA) - } - } - - Device (LNKB) - { - Name (_HID, EisaId ("PNP0C0F")) - Name (_UID, 0x02) - Method (_STA, 0, NotSerialized) - { - And (\_SB.PCI0.SBC3.PIBA, 0xF0, Local0) - If (LEqual (Local0, 0x00)) { Return (0x09) } - Else { Return (0x0B) } - } - - Method (_PRS, 0, NotSerialized) - { - Name (BUFB, ResourceTemplate () - { - IRQ (Level, ActiveLow, Shared) {3,5,10,11} - }) - Return (BUFB) - } - - Method (_DIS, 0, NotSerialized) - { - Store (0x01, Local3) - And (\_SB.PCI0.SBC3.PIBA, 0xF0, Local1) - ShiftRight (Local1, 0x04, Local1) - If (LGreater (Local1, 0x07)) - { - Subtract (Local1, 0x08, Local1) - } - - ShiftLeft (Local3, Local1, Local3) - Not (Local3, Local3) - And (\_SB.PCI0.SBC3.PIBA, 0x0F, \_SB.PCI0.SBC3.PIBA) - } - - Method (_CRS, 0, NotSerialized) - { - Name (BUFB, ResourceTemplate () - { - IRQ (Level, ActiveLow, Shared) {} - }) - CreateByteField (BUFB, 0x01, IRB1) - CreateByteField (BUFB, 0x02, IRB2) - Store (0x00, Local3) - Store (0x00, Local4) - And (\_SB.PCI0.SBC3.PIBA, 0xF0, Local1) - ShiftRight (Local1, 0x04, Local1) - If (LNot (LEqual (Local1, 0x00))) - { - If (LGreater (Local1, 0x07)) - { - Subtract (Local1, 0x08, Local2) - ShiftLeft (One, Local2, Local4) - } - Else - { - If (LGreater (Local1, 0x00)) - { - ShiftLeft (One, Local1, Local3) - } - } - - Store (Local3, IRB1) - Store (Local4, IRB2) - } - - Return (BUFB) - } - - Method (_SRS, 1, NotSerialized) - { - CreateByteField (Arg0, 0x01, IRB1) - CreateByteField (Arg0, 0x02, IRB2) - ShiftLeft (IRB2, 0x08, Local0) - Or (Local0, IRB1, Local0) - Store (0x00, Local1) - ShiftRight (Local0, 0x01, Local0) - While (LGreater (Local0, 0x00)) - { - Increment (Local1) - ShiftRight (Local0, 0x01, Local0) - } - - And (\_SB.PCI0.SBC3.PIBA, 0x0F, \_SB.PCI0.SBC3.PIBA) - ShiftLeft (Local1, 0x04, Local1) - Or (\_SB.PCI0.SBC3.PIBA, Local1, \_SB.PCI0.SBC3.PIBA) - } - } - - Device (LNKC) - { - Name (_HID, EisaId ("PNP0C0F")) - Name (_UID, 0x03) - Method (_STA, 0, NotSerialized) - { - And (\_SB.PCI0.SBC3.PIDC, 0x0F, Local0) - If (LEqual (Local0, 0x00)) { Return (0x09) } - Else { Return (0x0B) } - } - - Method (_PRS, 0, NotSerialized) - { - Name (BUFA, ResourceTemplate () - { - IRQ (Level, ActiveLow, Shared) {3,5,10,11} - }) - Return (BUFA) - } - - Method (_DIS, 0, NotSerialized) - { - Store (0x01, Local3) - And (\_SB.PCI0.SBC3.PIDC, 0x0F, Local1) - If (LGreater (Local1, 0x07)) - { - Subtract (Local1, 0x08, Local1) - } - - ShiftLeft (Local3, Local1, Local3) - Not (Local3, Local3) - And (\_SB.PCI0.SBC3.PIDC, 0xF0, \_SB.PCI0.SBC3.PIDC) - } - - Method (_CRS, 0, NotSerialized) - { - Name (BUFA, ResourceTemplate () - { - IRQ (Level, ActiveLow, Shared) {} - }) - CreateByteField (BUFA, 0x01, IRA1) - CreateByteField (BUFA, 0x02, IRA2) - Store (0x00, Local3) - Store (0x00, Local4) - And (\_SB.PCI0.SBC3.PIDC, 0x0F, Local1) - If (LNot (LEqual (Local1, 0x00))) - { - If (LGreater (Local1, 0x07)) - { - Subtract (Local1, 0x08, Local2) - ShiftLeft (One, Local2, Local4) - } - Else - { - If (LGreater (Local1, 0x00)) - { - ShiftLeft (One, Local1, Local3) - } - } - - Store (Local3, IRA1) - Store (Local4, IRA2) - } - - Return (BUFA) - } - - Method (_SRS, 1, NotSerialized) - { - CreateByteField (Arg0, 0x01, IRA1) - CreateByteField (Arg0, 0x02, IRA2) - ShiftLeft (IRA2, 0x08, Local0) - Or (Local0, IRA1, Local0) - Store (0x00, Local1) - ShiftRight (Local0, 0x01, Local0) - While (LGreater (Local0, 0x00)) - { - Increment (Local1) - ShiftRight (Local0, 0x01, Local0) - } - - And (\_SB.PCI0.SBC3.PIDC, 0xF0, \_SB.PCI0.SBC3.PIDC) - Or (\_SB.PCI0.SBC3.PIDC, Local1, \_SB.PCI0.SBC3.PIDC) - } - } - - Device (LNKD) - { - Name (_HID, EisaId ("PNP0C0F")) - Name (_UID, 0x04) - Method (_STA, 0, NotSerialized) - { - And (\_SB.PCI0.SBC3.PIDC, 0xF0, Local0) - If (LEqual (Local0, 0x00)) { Return (0x09) } - Else { Return (0x0B) } - } - - Method (_PRS, 0, NotSerialized) - { - Name (BUFB, ResourceTemplate () - { - IRQ (Level, ActiveLow, Shared) {3,5,10,11} - }) - Return (BUFB) - } - - Method (_DIS, 0, NotSerialized) - { - Store (0x01, Local3) - And (\_SB.PCI0.SBC3.PIDC, 0xF0, Local1) - ShiftRight (Local1, 0x04, Local1) - If (LGreater (Local1, 0x07)) - { - Subtract (Local1, 0x08, Local1) - } - - ShiftLeft (Local3, Local1, Local3) - Not (Local3, Local3) - And (\_SB.PCI0.SBC3.PIDC, 0x0F, \_SB.PCI0.SBC3.PIDC) - } - - Method (_CRS, 0, NotSerialized) - { - Name (BUFB, ResourceTemplate () - { - IRQ (Level, ActiveLow, Shared) {} - }) - CreateByteField (BUFB, 0x01, IRB1) - CreateByteField (BUFB, 0x02, IRB2) - Store (0x00, Local3) - Store (0x00, Local4) - And (\_SB.PCI0.SBC3.PIDC, 0xF0, Local1) - ShiftRight (Local1, 0x04, Local1) - If (LNot (LEqual (Local1, 0x00))) - { - If (LGreater (Local1, 0x07)) - { - Subtract (Local1, 0x08, Local2) - ShiftLeft (One, Local2, Local4) - } - Else - { - If (LGreater (Local1, 0x00)) - { - ShiftLeft (One, Local1, Local3) - } - } - - Store (Local3, IRB1) - Store (Local4, IRB2) - } - - Return (BUFB) - } - - Method (_SRS, 1, NotSerialized) - { - CreateByteField (Arg0, 0x01, IRB1) - CreateByteField (Arg0, 0x02, IRB2) - ShiftLeft (IRB2, 0x08, Local0) - Or (Local0, IRB1, Local0) - Store (0x00, Local1) - ShiftRight (Local0, 0x01, Local0) - While (LGreater (Local0, 0x00)) - { - Increment (Local1) - ShiftRight (Local0, 0x01, Local0) - } - - And (\_SB.PCI0.SBC3.PIDC, 0x0F, \_SB.PCI0.SBC3.PIDC) - ShiftLeft (Local1, 0x04, Local1) - Or (\_SB.PCI0.SBC3.PIDC, Local1, \_SB.PCI0.SBC3.PIDC) - } - } diff --git a/src/mainboard/amd/serengeti_cheetah_fam10/acpi/amd8131_2.asl b/src/mainboard/amd/serengeti_cheetah_fam10/acpi/amd8131_2.asl deleted file mode 100644 index 8e40ab0101..0000000000 --- a/src/mainboard/amd/serengeti_cheetah_fam10/acpi/amd8131_2.asl +++ /dev/null @@ -1,122 +0,0 @@ -// -// This file is part of the coreboot project. -// -// Copyright (C) 2007 Advanced Micro Devices, Inc. -// -// This program is free software; you can redistribute it and/or modify -// it under the terms of the GNU General Public License as published by -// the Free Software Foundation; version 2 of the License. -// -// This program is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. -// - Device (PG0A) - { - // 8132 pcix bridge - Method (_ADR, 0, NotSerialized) - { - Return (DADD(GHCD(HCIN, 0), 0x00000000)) - } - - Method (_PRW, 0, NotSerialized) - { - If (CondRefOf (\_S3)) { Return (Package (0x02) { 0x29, 0x03 }) } - Else { Return (Package (0x02) { 0x29, 0x01 }) } - } - - Name (APIC, Package (0x04) - { - // Slot A - PIRQ BCDA - Package (0x04) { 0x0001FFFF, 0x00, 0x00, 0x0018 }, //Slot 2 - Package (0x04) { 0x0001FFFF, 0x01, 0x00, 0x0019 }, - Package (0x04) { 0x0001FFFF, 0x02, 0x00, 0x001A }, - Package (0x04) { 0x0001FFFF, 0x03, 0x00, 0x001B }, - }) - Name (PICM, Package (0x04) - { - Package (0x04) { 0x0001FFFF, 0x00, \_SB.PCI0.LNKA, 0x00 },//Slot 2 - Package (0x04) { 0x0001FFFF, 0x01, \_SB.PCI0.LNKB, 0x00 }, - Package (0x04) { 0x0001FFFF, 0x02, \_SB.PCI0.LNKC, 0x00 }, - Package (0x04) { 0x0001FFFF, 0x03, \_SB.PCI0.LNKD, 0x00 }, - }) - - Name (DNCG, Ones) - - Method (_PRT, 0, NotSerialized) - { - If (LEqual (^DNCG, Ones)) - { - Multiply (HCIN, 0x0008, Local2) // GSI for 8132 is 4 so we get 8 - Store (0x00, Local1) - While (LLess (Local1, 0x04)) - { - // Update the GSI according to HCIN - Store(DeRefOf(Index (DeRefOf (Index (APIC, Local1)), 3)), Local0) - Add(Local2, Local0, Local0) - Store(Local0, Index (DeRefOf (Index (APIC, Local1)), 3)) - Increment (Local1) - } - Store (0x00, ^DNCG) - } - If (LNot (PICF)) { Return (PICM) } - Else { Return (APIC) } - } - } - - Device (PG0B) - { - // 8132 pcix bridge 2 - Method (_ADR, 0, NotSerialized) - { - Return (DADD(GHCD(HCIN, 0), 0x00010000)) - } - - Method (_PRW, 0, NotSerialized) - { - If (CondRefOf (\_S3)) { Return (Package (0x02) { 0x22, 0x03 }) } - Else { Return (Package (0x02) { 0x22, 0x01 }) } - } - - Name (APIC, Package (0x04) - { - // Slot A - PIRQ ABCD - Package (0x04) { 0x0001FFFF, 0x00, 0x00, 0x001F },// Slot 1 - Package (0x04) { 0x0001FFFF, 0x01, 0x00, 0x0020 }, - Package (0x04) { 0x0001FFFF, 0x02, 0x00, 0x0021 }, - Package (0x04) { 0x0001FFFF, 0x03, 0x00, 0x0022 } - }) - Name (PICM, Package (0x04) - { - Package (0x04) { 0x0001FFFF, 0x00, \_SB.PCI0.LNKA, 0x00 },//Slot 1 - Package (0x04) { 0x0001FFFF, 0x01, \_SB.PCI0.LNKB, 0x00 }, - Package (0x04) { 0x0001FFFF, 0x02, \_SB.PCI0.LNKC, 0x00 }, - Package (0x04) { 0x0001FFFF, 0x03, \_SB.PCI0.LNKD, 0x00 } - }) - - Name (DNCG, Ones) - - Method (_PRT, 0, NotSerialized) - { - If (LEqual (^DNCG, Ones)) - { - Multiply (HCIN, 0x0008, Local2) // GSI for 8132 is 4 so we get 8 - Store (0x00, Local1) - While (LLess (Local1, 0x04)) - { - // Update the GSI according to HCIN - Store(DeRefOf(Index (DeRefOf (Index (APIC, Local1)), 3)), Local0) - Add(Local2, Local0, Local0) - Store(Local0, Index (DeRefOf (Index (APIC, Local1)), 3)) - Increment (Local1) - } - - Store (0x00, ^DNCG) - - } - - If (LNot (PICF)) { Return (PICM) } - Else { Return (APIC) } - } - } diff --git a/src/mainboard/amd/serengeti_cheetah_fam10/acpi/amd8132.asl b/src/mainboard/amd/serengeti_cheetah_fam10/acpi/amd8132.asl deleted file mode 100644 index e4167e21a8..0000000000 --- a/src/mainboard/amd/serengeti_cheetah_fam10/acpi/amd8132.asl +++ /dev/null @@ -1,130 +0,0 @@ -// -// This file is part of the coreboot project. -// -// Copyright (C) 2007 Advanced Micro Devices, Inc. -// -// This program is free software; you can redistribute it and/or modify -// it under the terms of the GNU General Public License as published by -// the Free Software Foundation; version 2 of the License. -// -// This program is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. -// - - Device (PG0A) - { - // 8132 pcix bridge - Method (_ADR, 0, NotSerialized) - { - Return (DADD(GHCD(HCIN, 0), 0x00000000)) - } - - Method (_PRW, 0, NotSerialized) - { - If (CondRefOf (\_S3)) { Return (Package (0x02) { 0x29, 0x03 }) } - Else { Return (Package (0x02) { 0x29, 0x01 }) } - } - - Name (APIC, Package (0x14) - { - // Slot A - PIRQ BCDA - Package (0x04) { 0x0001FFFF, 0x00, 0x00, 0x19 }, //Slot 2 - Package (0x04) { 0x0001FFFF, 0x01, 0x00, 0x1A }, - Package (0x04) { 0x0001FFFF, 0x02, 0x00, 0x1B }, - Package (0x04) { 0x0001FFFF, 0x03, 0x00, 0x18 }, - - //Cypress Slot A - PIRQ BCDA - Package (0x04) { 0x0003FFFF, 0x00, 0x00, 0x19 }, //? - Package (0x04) { 0x0003FFFF, 0x01, 0x00, 0x1A }, - Package (0x04) { 0x0003FFFF, 0x02, 0x00, 0x1B }, - Package (0x04) { 0x0003FFFF, 0x03, 0x00, 0x18 }, - - //Cypress Slot B - PIRQ CDAB - Package (0x04) { 0x0004FFFF, 0x00, 0x00, 0x1A }, //? - Package (0x04) { 0x0004FFFF, 0x01, 0x00, 0x1B }, - Package (0x04) { 0x0004FFFF, 0x02, 0x00, 0x18 }, - Package (0x04) { 0x0004FFFF, 0x03, 0x00, 0x19 }, - - //Cypress Slot C - PIRQ DABC - Package (0x04) { 0x0005FFFF, 0x00, 0x00, 0x1B }, //? - Package (0x04) { 0x0005FFFF, 0x01, 0x00, 0x18 }, - Package (0x04) { 0x0005FFFF, 0x02, 0x00, 0x19 }, - Package (0x04) { 0x0005FFFF, 0x03, 0x00, 0x1A }, - - //Cypress Slot D - PIRQ ABCD - Package (0x04) { 0x0006FFFF, 0x00, 0x00, 0x18 }, //? - Package (0x04) { 0x0006FFFF, 0x01, 0x00, 0x19 }, - Package (0x04) { 0x0006FFFF, 0x02, 0x00, 0x1A }, - Package (0x04) { 0x0006FFFF, 0x03, 0x00, 0x1B } - }) - Name (PICM, Package (0x14) - { - Package (0x04) { 0x0001FFFF, 0x00, \_SB.PCI0.LNKB, 0x00 },//Slot 2 - Package (0x04) { 0x0001FFFF, 0x01, \_SB.PCI0.LNKC, 0x00 }, - Package (0x04) { 0x0001FFFF, 0x02, \_SB.PCI0.LNKD, 0x00 }, - Package (0x04) { 0x0001FFFF, 0x03, \_SB.PCI0.LNKA, 0x00 }, - - Package (0x04) { 0x0003FFFF, 0x00, \_SB.PCI0.LNKB, 0x00 }, - Package (0x04) { 0x0003FFFF, 0x01, \_SB.PCI0.LNKC, 0x00 }, - Package (0x04) { 0x0003FFFF, 0x02, \_SB.PCI0.LNKD, 0x00 }, - Package (0x04) { 0x0003FFFF, 0x03, \_SB.PCI0.LNKA, 0x00 }, - - Package (0x04) { 0x0004FFFF, 0x00, \_SB.PCI0.LNKC, 0x00 }, - Package (0x04) { 0x0004FFFF, 0x01, \_SB.PCI0.LNKD, 0x00 }, - Package (0x04) { 0x0004FFFF, 0x02, \_SB.PCI0.LNKA, 0x00 }, - Package (0x04) { 0x0004FFFF, 0x03, \_SB.PCI0.LNKB, 0x00 }, - - Package (0x04) { 0x0005FFFF, 0x00, \_SB.PCI0.LNKD, 0x00 }, - Package (0x04) { 0x0005FFFF, 0x01, \_SB.PCI0.LNKA, 0x00 }, - Package (0x04) { 0x0005FFFF, 0x02, \_SB.PCI0.LNKB, 0x00 }, - Package (0x04) { 0x0005FFFF, 0x03, \_SB.PCI0.LNKC, 0x00 }, - - Package (0x04) { 0x0006FFFF, 0x00, \_SB.PCI0.LNKA, 0x00 }, - Package (0x04) { 0x0006FFFF, 0x01, \_SB.PCI0.LNKB, 0x00 }, - Package (0x04) { 0x0006FFFF, 0x02, \_SB.PCI0.LNKC, 0x00 }, - Package (0x04) { 0x0006FFFF, 0x03, \_SB.PCI0.LNKD, 0x00 } - }) - Method (_PRT, 0, NotSerialized) - { - If (LNot (PICF)) { Return (PICM) } - Else { Return (APIC) } - } - } - - Device (PG0B) - { - // 8132 pcix bridge 2 - Method (_ADR, 0, NotSerialized) - { - Return (DADD(GHCD(HCIN, 0), 0x00010000)) - } - - Method (_PRW, 0, NotSerialized) - { - If (CondRefOf (\_S3)) { Return (Package (0x02) { 0x22, 0x03 }) } - Else { Return (Package (0x02) { 0x22, 0x01 }) } - } - - Name (APIC, Package (0x04) - { - // Slot A - PIRQ ABCD - Package (0x04) { 0x0001FFFF, 0x00, 0x00, 0x1F },// Slot 1 - Package (0x04) { 0x0001FFFF, 0x01, 0x00, 0x20 }, - Package (0x04) { 0x0001FFFF, 0x02, 0x00, 0x21 }, - Package (0x04) { 0x0001FFFF, 0x03, 0x00, 0x22 } - }) - Name (PICM, Package (0x04) - { - Package (0x04) { 0x0001FFFF, 0x00, \_SB.PCI0.LNKA, 0x00 },//Slot 1 - Package (0x04) { 0x0001FFFF, 0x01, \_SB.PCI0.LNKB, 0x00 }, - Package (0x04) { 0x0001FFFF, 0x02, \_SB.PCI0.LNKC, 0x00 }, - Package (0x04) { 0x0001FFFF, 0x03, \_SB.PCI0.LNKD, 0x00 } - }) - Method (_PRT, 0, NotSerialized) - { - If (LNot (PICF)) { Return (PICM) } - Else { Return (APIC) } - } - } diff --git a/src/mainboard/amd/serengeti_cheetah_fam10/acpi/amd8132_2.asl b/src/mainboard/amd/serengeti_cheetah_fam10/acpi/amd8132_2.asl deleted file mode 100644 index 30a3fcf9ac..0000000000 --- a/src/mainboard/amd/serengeti_cheetah_fam10/acpi/amd8132_2.asl +++ /dev/null @@ -1,187 +0,0 @@ -// -// This file is part of the coreboot project. -// -// Copyright (C) 2007 Advanced Micro Devices, Inc. -// -// This program is free software; you can redistribute it and/or modify -// it under the terms of the GNU General Public License as published by -// the Free Software Foundation; version 2 of the License. -// -// This program is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. -// - - Device (PG0A) - { - // 8132 pcix bridge - Method (_ADR, 0, NotSerialized) - { - Return (DADD(GHCD(HCIN, 0), 0x00000000)) - } - - Method (_PRW, 0, NotSerialized) - { - If (CondRefOf (\_S3)) { Return (Package (0x02) { 0x29, 0x03 }) } - Else { Return (Package (0x02) { 0x29, 0x01 }) } - } - - Name (APIC, Package (0x10) - { - // Slot 1 - PIRQ ABCD - Package (0x04) { 0x0000FFFF, 0x00, 0x00, 0x0018 }, - Package (0x04) { 0x0000FFFF, 0x01, 0x00, 0x0019 }, - Package (0x04) { 0x0000FFFF, 0x02, 0x00, 0x001A }, - Package (0x04) { 0x0000FFFF, 0x03, 0x00, 0x001B }, - // Slot 2 - PIRQ BCDA - Package (0x04) { 0x0001FFFF, 0x00, 0x00, 0x0019 }, - Package (0x04) { 0x0001FFFF, 0x01, 0x00, 0x001A }, - Package (0x04) { 0x0001FFFF, 0x02, 0x00, 0x001B }, - Package (0x04) { 0x0001FFFF, 0x03, 0x00, 0x0018 }, - // Slot 3 - PIRQ CDAB - Package (0x04) { 0x0002FFFF, 0x00, 0x00, 0x001A }, - Package (0x04) { 0x0002FFFF, 0x01, 0x00, 0x001B }, - Package (0x04) { 0x0002FFFF, 0x02, 0x00, 0x0018 }, - Package (0x04) { 0x0002FFFF, 0x03, 0x00, 0x0019 }, - // Slot 4 - PIRQ DABC - Package (0x04) { 0x0003FFFF, 0x00, 0x00, 0x001B }, - Package (0x04) { 0x0003FFFF, 0x01, 0x00, 0x0018 }, - Package (0x04) { 0x0003FFFF, 0x02, 0x00, 0x0019 }, - Package (0x04) { 0x0003FFFF, 0x03, 0x00, 0x001A }, - - }) - Name (PICM, Package (0x04) - { - Package (0x04) { 0x0000FFFF, 0x00, \_SB.PCI0.LNKA, 0x00 },//Slot 2 - Package (0x04) { 0x0000FFFF, 0x01, \_SB.PCI0.LNKB, 0x00 }, - Package (0x04) { 0x0000FFFF, 0x02, \_SB.PCI0.LNKC, 0x00 }, - Package (0x04) { 0x0000FFFF, 0x03, \_SB.PCI0.LNKD, 0x00 }, -// -// Package (0x04) { 0x0001FFFF, 0x00, \_SB.PCI0.LNKB, 0x00 },//Slot 2 -// Package (0x04) { 0x0001FFFF, 0x01, \_SB.PCI0.LNKC, 0x00 }, -// Package (0x04) { 0x0001FFFF, 0x02, \_SB.PCI0.LNKD, 0x00 }, -// Package (0x04) { 0x0001FFFF, 0x03, \_SB.PCI0.LNKA, 0x00 }, -// -// Package (0x04) { 0x0002FFFF, 0x00, \_SB.PCI0.LNKC, 0x00 },//Slot 2 -// Package (0x04) { 0x0002FFFF, 0x01, \_SB.PCI0.LNKD, 0x00 }, -// Package (0x04) { 0x0002FFFF, 0x02, \_SB.PCI0.LNKA, 0x00 }, -// Package (0x04) { 0x0002FFFF, 0x03, \_SB.PCI0.LNKB, 0x00 }, -// -// Package (0x04) { 0x0003FFFF, 0x00, \_SB.PCI0.LNKD, 0x00 },//Slot 2 -// Package (0x04) { 0x0003FFFF, 0x01, \_SB.PCI0.LNKA, 0x00 }, -// Package (0x04) { 0x0003FFFF, 0x02, \_SB.PCI0.LNKB, 0x00 }, -// Package (0x04) { 0x0003FFFF, 0x03, \_SB.PCI0.LNKC, 0x00 }, -// - }) - - Name (DNCG, Ones) - - Method (_PRT, 0, NotSerialized) - { - If (LEqual (^DNCG, Ones)) { - Multiply (HCIN, 0x000e, Local2) // GSI for 8132 is 7 so we get 14 - Store (0x00, Local1) - While (LLess (Local1, 0x10)) - { - // Update the GSI according to HCIN - Store(DeRefOf(Index (DeRefOf (Index (APIC, Local1)), 3)), Local0) - Add(Local2, Local0, Local0) - Store(Local0, Index (DeRefOf (Index (APIC, Local1)), 3)) - Increment (Local1) - } - - Store (0x00, ^DNCG) - - } - - If (LNot (PICF)) { Return (PICM) } - Else { Return (APIC) } - } - } - - Device (PG0B) - { - // 8132 pcix bridge 2 - Method (_ADR, 0, NotSerialized) - { - Return (DADD(GHCD(HCIN, 0), 0x00010000)) - } - - Method (_PRW, 0, NotSerialized) - { - If (CondRefOf (\_S3)) { Return (Package (0x02) { 0x22, 0x03 }) } - Else { Return (Package (0x02) { 0x22, 0x01 }) } - } - - Name (APIC, Package (0x10) - { - // Slot A - PIRQ ABCD - Package (0x04) { 0x0000FFFF, 0x00, 0x00, 0x001F },// Slot 1 - Package (0x04) { 0x0000FFFF, 0x01, 0x00, 0x0020 }, - Package (0x04) { 0x0000FFFF, 0x02, 0x00, 0x0021 }, - Package (0x04) { 0x0000FFFF, 0x03, 0x00, 0x0022 }, - // Slot A - PIRQ BCDA - Package (0x04) { 0x0001FFFF, 0x00, 0x00, 0x0020 },// Slot 1 - Package (0x04) { 0x0001FFFF, 0x01, 0x00, 0x0021 }, - Package (0x04) { 0x0001FFFF, 0x02, 0x00, 0x0022 }, - Package (0x04) { 0x0001FFFF, 0x03, 0x00, 0x001F }, - // Slot A - PIRQ CDAB - Package (0x04) { 0x0002FFFF, 0x00, 0x00, 0x0021 },// Slot 1 - Package (0x04) { 0x0002FFFF, 0x01, 0x00, 0x0022 }, - Package (0x04) { 0x0002FFFF, 0x02, 0x00, 0x001F }, - Package (0x04) { 0x0002FFFF, 0x03, 0x00, 0x0020 }, - // Slot A - PIRQ DABC - Package (0x04) { 0x0003FFFF, 0x00, 0x00, 0x0022 },// Slot 1 - Package (0x04) { 0x0003FFFF, 0x01, 0x00, 0x001F }, - Package (0x04) { 0x0003FFFF, 0x02, 0x00, 0x0020 }, - Package (0x04) { 0x0003FFFF, 0x03, 0x00, 0x0021 }, - }) - Name (PICM, Package (0x04) - { - Package (0x04) { 0x0000FFFF, 0x00, \_SB.PCI0.LNKA, 0x00 },//Slot 1 - Package (0x04) { 0x0000FFFF, 0x01, \_SB.PCI0.LNKB, 0x00 }, - Package (0x04) { 0x0000FFFF, 0x02, \_SB.PCI0.LNKC, 0x00 }, - Package (0x04) { 0x0000FFFF, 0x03, \_SB.PCI0.LNKD, 0x00 }, - -// Package (0x04) { 0x0001FFFF, 0x00, \_SB.PCI0.LNKB, 0x00 },//Slot 1 -// Package (0x04) { 0x0001FFFF, 0x01, \_SB.PCI0.LNKC, 0x00 }, -// Package (0x04) { 0x0001FFFF, 0x02, \_SB.PCI0.LNKD, 0x00 }, -// Package (0x04) { 0x0001FFFF, 0x03, \_SB.PCI0.LNKA, 0x00 }, -// -// Package (0x04) { 0x0002FFFF, 0x00, \_SB.PCI0.LNKC, 0x00 },//Slot 1 -// Package (0x04) { 0x0002FFFF, 0x01, \_SB.PCI0.LNKD, 0x00 }, -// Package (0x04) { 0x0002FFFF, 0x02, \_SB.PCI0.LNKA, 0x00 }, -// Package (0x04) { 0x0002FFFF, 0x03, \_SB.PCI0.LNKB, 0x00 }, -// -// Package (0x04) { 0x0003FFFF, 0x00, \_SB.PCI0.LNKD, 0x00 },//Slot 1 -// Package (0x04) { 0x0003FFFF, 0x01, \_SB.PCI0.LNKA, 0x00 }, -// Package (0x04) { 0x0003FFFF, 0x02, \_SB.PCI0.LNKB, 0x00 }, -// Package (0x04) { 0x0003FFFF, 0x03, \_SB.PCI0.LNKC, 0x00 }, -// - }) - - Name (DNCG, Ones) - - Method (_PRT, 0, NotSerialized) - { - If (LEqual (^DNCG, Ones)) { - Multiply (HCIN, 0x000e, Local2) // GSI for 8132 is 7 so we get 14 - Store (0x00, Local1) - While (LLess (Local1, 0x10)) - { - // Update the GSI according to HCIN - Store(DeRefOf(Index (DeRefOf (Index (APIC, Local1)), 3)), Local0) - Add(Local2, Local0, Local0) - Store(Local0, Index (DeRefOf (Index (APIC, Local1)), 3)) - Increment (Local1) - } - - Store (0x00, ^DNCG) - - } - - If (LNot (PICF)) { Return (PICM) } - Else { Return (APIC) } - } - } diff --git a/src/mainboard/amd/serengeti_cheetah_fam10/acpi/amd8151.asl b/src/mainboard/amd/serengeti_cheetah_fam10/acpi/amd8151.asl deleted file mode 100644 index 081712b70d..0000000000 --- a/src/mainboard/amd/serengeti_cheetah_fam10/acpi/amd8151.asl +++ /dev/null @@ -1,43 +0,0 @@ -// -// This file is part of the coreboot project. -// -// Copyright (C) 2007 Advanced Micro Devices, Inc. -// -// This program is free software; you can redistribute it and/or modify -// it under the terms of the GNU General Public License as published by -// the Free Software Foundation; version 2 of the License. -// -// This program is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. -// - -// AMD8151 - Device (AGPB) - { - Method (_ADR, 0, NotSerialized) - { - Return (DADD(GHCD(HCIN, 0), 0x00010000)) - } - - Name (APIC, Package (0x04) - { - Package (0x04) { 0x0000FFFF, 0x00, 0x00, 0x10 }, - Package (0x04) { 0x0000FFFF, 0x01, 0x00, 0x11 }, - Package (0x04) { 0x0000FFFF, 0x02, 0x00, 0x12 }, - Package (0x04) { 0x0000FFFF, 0x03, 0x00, 0x13 } - }) - Name (PICM, Package (0x04) - { - Package (0x04) { 0x0000FFFF, 0x00, \_SB.PCI0.LNKA, 0x00 }, - Package (0x04) { 0x0000FFFF, 0x01, \_SB.PCI0.LNKB, 0x00 }, - Package (0x04) { 0x0000FFFF, 0x02, \_SB.PCI0.LNKC, 0x00 }, - Package (0x04) { 0x0000FFFF, 0x03, \_SB.PCI0.LNKD, 0x00 } - }) - Method (_PRT, 0, NotSerialized) - { - If (LNot (PICF)) { Return (PICM) } - Else { Return (APIC) } - } - } diff --git a/src/mainboard/amd/serengeti_cheetah_fam10/acpi/htx_no_ioapic.asl b/src/mainboard/amd/serengeti_cheetah_fam10/acpi/htx_no_ioapic.asl deleted file mode 100644 index 9caa3b2466..0000000000 --- a/src/mainboard/amd/serengeti_cheetah_fam10/acpi/htx_no_ioapic.asl +++ /dev/null @@ -1,30 +0,0 @@ -// -// This file is part of the coreboot project. -// -// Copyright (C) 2007 Advanced Micro Devices, Inc. -// -// This program is free software; you can redistribute it and/or modify -// it under the terms of the GNU General Public License as published by -// the Free Software Foundation; version 2 of the License. -// -// This program is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. -// - - Device (HTXA) - { - // HTX - Method (_ADR, 0, NotSerialized) - { - Return (DADD(GHCD(HCIN, 0), 0x00000000)) - } - - Method (_PRW, 0, NotSerialized) - { - If (CondRefOf (\_S3)) { Return (Package (0x02) { 0x29, 0x03 }) } - Else { Return (Package (0x02) { 0x29, 0x01 }) } - } - - } diff --git a/src/mainboard/amd/serengeti_cheetah_fam10/acpi/pci0_hc.asl b/src/mainboard/amd/serengeti_cheetah_fam10/acpi/pci0_hc.asl deleted file mode 100644 index 16b494a3cc..0000000000 --- a/src/mainboard/amd/serengeti_cheetah_fam10/acpi/pci0_hc.asl +++ /dev/null @@ -1,16 +0,0 @@ -// -// This file is part of the coreboot project. -// -// Copyright (C) 2007 Advanced Micro Devices, Inc. -// -// This program is free software; you can redistribute it and/or modify -// it under the terms of the GNU General Public License as published by -// the Free Software Foundation; version 2 of the License. -// -// This program is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. -// - #include "amd8111.asl" //real SB at first - #include "amd8132.asl" diff --git a/src/mainboard/amd/serengeti_cheetah_fam10/acpi/pci2_hc.asl b/src/mainboard/amd/serengeti_cheetah_fam10/acpi/pci2_hc.asl deleted file mode 100644 index cf4ebf96eb..0000000000 --- a/src/mainboard/amd/serengeti_cheetah_fam10/acpi/pci2_hc.asl +++ /dev/null @@ -1,16 +0,0 @@ -// -// This file is part of the coreboot project. -// -// Copyright (C) 2007 Advanced Micro Devices, Inc. -// -// This program is free software; you can redistribute it and/or modify -// it under the terms of the GNU General Public License as published by -// the Free Software Foundation; version 2 of the License. -// -// This program is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. -// - - #include "amd8132_2.asl" diff --git a/src/mainboard/amd/serengeti_cheetah_fam10/acpi/pci3_hc.asl b/src/mainboard/amd/serengeti_cheetah_fam10/acpi/pci3_hc.asl deleted file mode 100644 index 05ff345d0a..0000000000 --- a/src/mainboard/amd/serengeti_cheetah_fam10/acpi/pci3_hc.asl +++ /dev/null @@ -1,16 +0,0 @@ -// -// This file is part of the coreboot project. -// -// Copyright (C) 2007 Advanced Micro Devices, Inc. -// -// This program is free software; you can redistribute it and/or modify -// it under the terms of the GNU General Public License as published by -// the Free Software Foundation; version 2 of the License. -// -// This program is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. -// - - #include "amd8151.asl" diff --git a/src/mainboard/amd/serengeti_cheetah_fam10/acpi/pci4_hc.asl b/src/mainboard/amd/serengeti_cheetah_fam10/acpi/pci4_hc.asl deleted file mode 100644 index 0614a2de71..0000000000 --- a/src/mainboard/amd/serengeti_cheetah_fam10/acpi/pci4_hc.asl +++ /dev/null @@ -1,16 +0,0 @@ -// -// This file is part of the coreboot project. -// -// Copyright (C) 2007 Advanced Micro Devices, Inc. -// -// This program is free software; you can redistribute it and/or modify -// it under the terms of the GNU General Public License as published by -// the Free Software Foundation; version 2 of the License. -// -// This program is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. -// - - #include "amd8131_2.asl" diff --git a/src/mainboard/amd/serengeti_cheetah_fam10/acpi/pci5_hc.asl b/src/mainboard/amd/serengeti_cheetah_fam10/acpi/pci5_hc.asl deleted file mode 100644 index 62a1faa417..0000000000 --- a/src/mainboard/amd/serengeti_cheetah_fam10/acpi/pci5_hc.asl +++ /dev/null @@ -1,16 +0,0 @@ -// -// This file is part of the coreboot project. -// -// Copyright (C) 2007 Advanced Micro Devices, Inc. -// -// This program is free software; you can redistribute it and/or modify -// it under the terms of the GNU General Public License as published by -// the Free Software Foundation; version 2 of the License. -// -// This program is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. -// - - #include "htx_no_ioapic.asl" diff --git a/src/mainboard/amd/serengeti_cheetah_fam10/acpi/superio.asl b/src/mainboard/amd/serengeti_cheetah_fam10/acpi/superio.asl deleted file mode 100644 index a1a2101a86..0000000000 --- a/src/mainboard/amd/serengeti_cheetah_fam10/acpi/superio.asl +++ /dev/null @@ -1,16 +0,0 @@ -// -// This file is part of the coreboot project. -// -// Copyright (C) 2007 Advanced Micro Devices, Inc. -// -// This program is free software; you can redistribute it and/or modify -// it under the terms of the GNU General Public License as published by -// the Free Software Foundation; version 2 of the License. -// -// This program is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. -// - -// #include "w83627hf.asl" diff --git a/src/mainboard/amd/serengeti_cheetah_fam10/acpi_tables.c b/src/mainboard/amd/serengeti_cheetah_fam10/acpi_tables.c deleted file mode 100644 index 3b3ad5b9f3..0000000000 --- a/src/mainboard/amd/serengeti_cheetah_fam10/acpi_tables.c +++ /dev/null @@ -1,179 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include -#include -#include -#include -#include - -#include "mb_sysconf.h" -#include "mainboard.h" - -unsigned long acpi_fill_madt(unsigned long current) -{ - u32 gsi_base = 0x18; - - struct mb_sysconf_t *m; - - m = sysconf.mb; - - /* create all subtables for processors */ - current = acpi_create_madt_lapics(current); - - /* Write 8111 IOAPIC */ - current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *)current, m->apicid_8111, - IO_APIC_ADDR, 0); - - /* Write all 8131 IOAPICs */ - { - struct device *dev; - struct resource *res; - dev = dev_find_slot(m->bus_8132_0, PCI_DEVFN((sysconf.hcdn[0]&0xff), 1)); - if (dev) { - res = find_resource(dev, PCI_BASE_ADDRESS_0); - if (res) { - current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *)current, m->apicid_8132_1, - res->base, gsi_base); - gsi_base+=7; - } - } - dev = dev_find_slot(m->bus_8132_0, PCI_DEVFN((sysconf.hcdn[0] & 0xff)+1, 1)); - if (dev) { - res = find_resource(dev, PCI_BASE_ADDRESS_0); - if (res) { - current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *)current, m->apicid_8132_2, - res->base, gsi_base); - gsi_base+=7; - } - } - - int i; - int j = 0; - - for (i = 1; i < sysconf.hc_possible_num; i++) { - u32 d = 0; - if (!(sysconf.pci1234[i] & 0x1)) - continue; - /* 8131 need to use +4 */ - switch (sysconf.hcid[i]) { - case 1: - d = 7; - break; - case 3: - d = 4; - break; - } - switch (sysconf.hcid[i]) { - case 1: - case 3: - dev = dev_find_slot(m->bus_8132a[j][0], PCI_DEVFN(m->sbdn3a[j], 1)); - if (dev) { - res = find_resource(dev, PCI_BASE_ADDRESS_0); - if (res) { - current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *)current, m->apicid_8132a[j][0], - res->base, gsi_base); - gsi_base+=d; - } - } - dev = dev_find_slot(m->bus_8132a[j][0], PCI_DEVFN(m->sbdn3a[j]+1, 1)); - if (dev) { - res = find_resource(dev, PCI_BASE_ADDRESS_0); - if (res) { - current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *)current, m->apicid_8132a[j][1], - res->base, gsi_base); - gsi_base+=d; - } - } - break; - } - j++; - } - } - - current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) current, 0, 0, 2, 5); - /* 0: mean bus 0--->ISA */ - /* 0: PIC 0 */ - /* 2: APIC 2 */ - /* 5 mean: 0101 --> Edge-triggered, Active high*/ - - - /* create all subtables for processors */ - current = acpi_create_madt_lapic_nmis(current, 5, 1); - /* 1: LINT1 connect to NMI */ - - return current; -} - -unsigned long mainboard_write_acpi_tables(struct device *device, - unsigned long current, - acpi_rsdp_t *rsdp) -{ - acpi_header_t *ssdtx; - const void *p; - size_t p_size; - - int i; - - /* same htio, but different possition? We may have to copy, - * change HCIN, and recalculate the checknum and add_table - */ - - for (i = 1; i < sysconf.hc_possible_num; i++) { /* 0: is hc sblink */ - const char *file_name; - if ((sysconf.pci1234[i] & 1) != 1) - continue; - u8 c; - if (i < 7) { - c = (u8) ('4' + i - 1); - } - else { - c = (u8) ('A' + i - 1 - 6); - } - current = ALIGN(current, 8); - printk(BIOS_DEBUG, "ACPI: * SSDT for PCI%c at %lx\n", c, current); /* pci0 and pci1 are in dsdt */ - ssdtx = (acpi_header_t *)current; - switch (sysconf.hcid[i]) { - case 1: - file_name = CONFIG_CBFS_PREFIX "/ssdt2.aml"; - break; - case 2: - file_name = CONFIG_CBFS_PREFIX "/ssdt3.aml"; - break; - case 3: /* 8131 */ - file_name = CONFIG_CBFS_PREFIX "/ssdt4.aml"; - break; - default: - /* HTX no io apic */ - file_name = CONFIG_CBFS_PREFIX "/ssdt5.aml"; - } - p = cbfs_boot_map_with_leak( - file_name, - CBFS_TYPE_RAW, &p_size); - if (!p || p_size < sizeof(acpi_header_t)) - continue; - memcpy(ssdtx, p, sizeof(acpi_header_t)); - current += ssdtx->length; - memcpy(ssdtx, p, ssdtx->length); - update_ssdtx((void *)ssdtx, i); - ssdtx->checksum = 0; - ssdtx->checksum = acpi_checksum((u8 *)ssdtx, ssdtx->length); - acpi_add_table(rsdp, ssdtx); - } - - return current; -} diff --git a/src/mainboard/amd/serengeti_cheetah_fam10/board_info.txt b/src/mainboard/amd/serengeti_cheetah_fam10/board_info.txt deleted file mode 100644 index 3d902b640a..0000000000 --- a/src/mainboard/amd/serengeti_cheetah_fam10/board_info.txt +++ /dev/null @@ -1 +0,0 @@ -Category: server diff --git a/src/mainboard/amd/serengeti_cheetah_fam10/cmos.layout b/src/mainboard/amd/serengeti_cheetah_fam10/cmos.layout deleted file mode 100644 index 1bc969ea4e..0000000000 --- a/src/mainboard/amd/serengeti_cheetah_fam10/cmos.layout +++ /dev/null @@ -1,102 +0,0 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2015 Timothy Pearson , Raptor Engineering -## Copyright (C) 2007 AMD -## Written by Yinghai Lu for AMD. -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; either version 2 of the License, or -## (at your option) any later version. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## - -entries - -0 384 r 0 reserved_memory -384 1 e 4 boot_option -388 4 h 0 reboot_counter -393 3 r 0 unused -#394 7 unused -401 1 e 1 interleave_chip_selects -402 1 e 1 interleave_nodes -403 1 e 1 interleave_memory_channels -404 2 e 8 max_mem_clock -406 1 e 2 multi_core -412 4 e 6 debug_level -416 5 e 10 ecc_scrub_rate -440 4 e 9 slow_cpu -444 1 e 1 nmi -445 1 e 1 gart -446 1 e 1 power_on_after_fail -456 1 e 1 ECC_memory -457 1 e 1 ECC_redirection -728 256 h 0 user_data -984 16 h 0 check_sum -# Reserve the extended AMD configuration registers -1000 24 r 0 amd_reserved - - - -enumerations - -#ID value text -1 0 Disable -1 1 Enable -2 0 Enable -2 1 Disable -4 0 Fallback -4 1 Normal -6 0 Emergency -6 1 Alert -6 2 Critical -6 3 Error -6 4 Warning -6 5 Notice -6 6 Information -6 7 Debug -6 8 Spew -8 0 DDR2-800 -8 1 DDR2-667 -8 2 DDR2-533 -8 3 DDR2-400 -9 0 off -9 1 87.5% -9 2 75.0% -9 3 62.5% -9 4 50.0% -9 5 37.5% -9 6 25.0% -9 7 12.5% -10 0 Disabled -10 1 40ns -10 2 80ns -10 3 160ns -10 4 320ns -10 5 640ns -10 6 1.28us -10 7 2.56us -10 8 5.12us -10 9 10.2us -10 10 20.5us -10 11 41us -10 12 81.9us -10 13 163.8us -10 14 327.7us -10 15 655.4us -10 16 1.31ms -10 17 2.62ms -10 18 5.24ms -10 19 10.49ms -10 20 20.97sms -10 21 42ms -10 22 84ms - -checksums - -checksum 392 983 984 diff --git a/src/mainboard/amd/serengeti_cheetah_fam10/devicetree.cb b/src/mainboard/amd/serengeti_cheetah_fam10/devicetree.cb deleted file mode 100644 index 54c34f8bec..0000000000 --- a/src/mainboard/amd/serengeti_cheetah_fam10/devicetree.cb +++ /dev/null @@ -1,137 +0,0 @@ -chip northbridge/amd/amdfam10/root_complex - device cpu_cluster 0 on - chip cpu/amd/socket_F_1207 #L1 and DDR2 - device lapic 0 on end - end - end - device domain 0 on - subsystemid 0x1022 0x2b80 inherit - chip northbridge/amd/amdfam10 - device pci 18.0 on # northbridge - # devices on link 0, link 0 == LDT 0 - chip southbridge/amd/amd8132 - # the on/off keyword is mandatory - device pci 0.0 on end - device pci 0.1 on end - device pci 1.0 on end - device pci 1.1 on end - end - chip southbridge/amd/amd8111 - # this "device pci 0.0" is the parent the next one - # PCI bridge - device pci 0.0 on - device pci 0.0 on end - device pci 0.1 on end - device pci 0.2 off end - device pci 1.0 off end - end - device pci 1.0 on - chip superio/winbond/w83627hf - device pnp 2e.0 off # Floppy - io 0x60 = 0x3f0 - irq 0x70 = 6 - drq 0x74 = 2 - end - device pnp 2e.1 off # Parallel Port - io 0x60 = 0x378 - irq 0x70 = 7 - end - device pnp 2e.2 on # Com1 - io 0x60 = 0x3f8 - irq 0x70 = 4 - end - device pnp 2e.3 off # Com2 - io 0x60 = 0x2f8 - irq 0x70 = 3 - end - device pnp 2e.5 on # Keyboard - io 0x60 = 0x60 - io 0x62 = 0x64 - irq 0x70 = 1 - irq 0x72 = 12 - end - device pnp 2e.6 off # CIR - io 0x60 = 0x100 - end - device pnp 2e.7 off # GAME_MIDI_GIPO1 - io 0x60 = 0x220 - io 0x62 = 0x300 - irq 0x70 = 9 - end - device pnp 2e.8 off end # GPIO2 - device pnp 2e.9 off end # GPIO3 - device pnp 2e.a off end # ACPI - device pnp 2e.b on # HW Monitor - io 0x60 = 0x290 - irq 0x70 = 5 - end - end - end - device pci 1.1 on end - device pci 1.2 on end - device pci 1.3 on - chip drivers/i2c/i2cmux2 # pca9556 smbus mux - chip drivers/i2c/i2cmux2 # pca9556 smbus mux - device i2c 18 on #0 pca9516 1 - chip drivers/generic/generic #dimm 0-0-0 - device i2c 50 on end - end - chip drivers/generic/generic #dimm 0-0-1 - device i2c 51 on end - end - chip drivers/generic/generic #dimm 0-1-0 - device i2c 52 on end - end - chip drivers/generic/generic #dimm 0-1-1 - device i2c 53 on end - end - end - device i2c 18 on #1 pca9516 2 - chip drivers/generic/generic #dimm 1-0-0 - device i2c 50 on end - end - chip drivers/generic/generic #dimm 1-0-1 - device i2c 51 on end - end - chip drivers/generic/generic #dimm 1-1-0 - device i2c 52 on end - end - chip drivers/generic/generic #dimm 1-1-1 - device i2c 53 on end - end - end - end - end - end # acpi - device pci 1.5 off end - device pci 1.6 off end - register "ide0_enable" = "1" - register "ide1_enable" = "1" - end - end # device pci 18.0 - - device pci 18.0 on end - device pci 18.0 on end - device pci 18.1 on end - device pci 18.2 on end - device pci 18.3 on end - device pci 18.4 on end -# device pci 00.5 on end - end - end #domain - #for node 32 to node 63 -# device domain 0 on -# chip northbridge/amd/amdfam10 -# device pci 00.0 on end# northbridge -# device pci 00.0 on end -# device pci 00.0 on end -# device pci 00.0 on end -# device pci 00.1 on end -# device pci 00.2 on end -# device pci 00.3 on end -# device pci 00.4 on end -# device pci 00.5 on end -# end -# end #domain - -end diff --git a/src/mainboard/amd/serengeti_cheetah_fam10/dsdt.asl b/src/mainboard/amd/serengeti_cheetah_fam10/dsdt.asl deleted file mode 100644 index 29b146b0d0..0000000000 --- a/src/mainboard/amd/serengeti_cheetah_fam10/dsdt.asl +++ /dev/null @@ -1,244 +0,0 @@ -// -// This file is part of the coreboot project. -// -// Copyright (C) 2007 Advanced Micro Devices, Inc. -// -// This program is free software; you can redistribute it and/or modify -// it under the terms of the GNU General Public License as published by -// the Free Software Foundation; version 2 of the License. -// -// This program is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. -// -#include -DefinitionBlock ("DSDT.aml", "DSDT", 1, OEM_ID, ACPI_TABLE_CREATOR, 100925440) -{ - -// Scope (_PR) -// { -// Device (CPU0) { -// Name (_HID, "ACPI0007") -// Name (_UID, 0) -// } -// Device (CPU1) { -// Name (_HID, "ACPI0007") -// Name (_UID, 1) -// } -// Device (CPU2) { -// Name (_HID, "ACPI0007") -// Name (_UID, 2) -// } -// Device (CPU3) { -// Name (_HID, "ACPI0007") -// Name (_UID, 3) -// } -// } - - Method (FWSO, 0, NotSerialized) { } - - - Scope (_SB) - { - Device (PCI0) - { - // BUS0 root bus - External (BUSN) - External (MMIO) - External (PCIO) - External (SBLK) - External (TOM1) - External (HCLK) - External (SBDN) - External (HCDN) - External (CBST) - External (CBB) - External (CBS2) - External (CBB2) - - Name (_HID, EisaId ("PNP0A03")) - Name (_UID, 0x01) - - Name (HCIN, 0x00) // HC1 - - Method (_BBN, 0, NotSerialized) - { - Return (GBUS (GHCN(HCIN), GHCL(HCIN))) - } - - Method (_CRS, 0, NotSerialized) - { - Name (BUF0, ResourceTemplate () - { - IO (Decode16, 0x0CF8, 0x0CF8, 0x01, 0x08) //CF8-CFFh - IO (Decode16, 0xC000, 0xC000, 0x01, 0x80) //8000h - IO (Decode16, 0xC080, 0xC080, 0x01, 0x80) //8080h - - WordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, - 0x0000, // Address Space Granularity - 0x8100, // Address Range Minimum - 0xFFFF, // Address Range Maximum - 0x0000, // Address Translation Offset - 0x7F00,,, - , TypeStatic) //8100h-FFFFh - - DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite, - 0x00000000, // Address Space Granularity - 0x000C0000, // Address Range Minimum - 0x000CFFFF, // Address Range Maximum - 0x00000000, // Address Translation Offset - 0x00010000,,, - , AddressRangeMemory, TypeStatic) //Video BIOS A0000h-C7FFFh - - Memory32Fixed (ReadWrite, 0x000D8000, 0x00004000)//USB HC D8000-DBFFF - - WordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, - 0x0000, // Address Space Granularity - 0x0000, // Address Range Minimum - 0x03AF, // Address Range Maximum - 0x0000, // Address Translation Offset - 0x03B0,,, - , TypeStatic) //0-CF7h - - WordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, - 0x0000, // Address Space Granularity - 0x03E0, // Address Range Minimum - 0x0CF7, // Address Range Maximum - 0x0000, // Address Translation Offset - 0x0918,,, - , TypeStatic) //0-CF7h - }) - \_SB.OSVR () - CreateDWordField (BUF0, 0x3E, VLEN) - CreateDWordField (BUF0, 0x36, VMAX) - CreateDWordField (BUF0, 0x32, VMIN) - ShiftLeft (VGA1, 0x09, Local0) - Add (VMIN, Local0, VMAX) - Decrement (VMAX) - Store (Local0, VLEN) - Concatenate (\_SB.GMEM (0x00, \_SB.PCI0.SBLK), BUF0, Local1) - Concatenate (\_SB.GIOR (0x00, \_SB.PCI0.SBLK), Local1, Local2) - Concatenate (\_SB.GWBN (0x00, \_SB.PCI0.SBLK), Local2, Local3) - Return (Local3) - } - - #include "acpi/pci0_hc.asl" - - } - Device (PCI1) - { - Name (_HID, "PNP0A03") - Name (_UID, 0x02) - Method (_STA, 0, NotSerialized) - { - Return (\_SB.PCI0.CBST) - } - Method (_BBN, 0, NotSerialized) - { - Return (\_SB.PCI0.CBB) // 0 or 0xff - } - - } - Device (PCI2) - { - Name (_HID, "PNP0A03") - Name (_UID, 0x02) - Method (_STA, 0, NotSerialized) - { - Return (\_SB.PCI0.CBS2) - } - Method (_BBN, 0, NotSerialized) - { - Return (\_SB.PCI0.CBB2)// 0xfe - } - } - } - - Scope (_GPE) - { - Method (_L08, 0, NotSerialized) - { - Notify (\_SB.PCI0, 0x02) //PME# Wakeup - } - - Method (_L0F, 0, NotSerialized) - { - Notify (\_SB.PCI0.TP2P.USB0, 0x02) //USB Wakeup - } - - Method (_L22, 0, NotSerialized) // GPIO18 (LID) - Pogo 0 Bridge B - { - Notify (\_SB.PCI0.PG0B, 0x02) - } - - Method (_L29, 0, NotSerialized) // GPIO25 (Suspend) - Pogo 0 Bridge A - { - Notify (\_SB.PCI0.PG0A, 0x02) - } - } - - Method (_PTS, 1, NotSerialized) - { - Or (Arg0, 0xF0, Local0) - Store (Local0, DBG1) - } -// -// Method (_WAK, 1, NotSerialized) -// { -// Or (Arg0, 0xE0, Local0) -// Store (Local0, DBG1) -// } - - Name (PICF, 0x00) //Flag Variable for PIC vs. I/O APIC Mode - Method (_PIC, 1, NotSerialized) //PIC Flag and Interface Method - { - Store (Arg0, PICF) - } - - OperationRegion (DEBG, SystemIO, 0x80, 0x01) - Field (DEBG, ByteAcc, Lock, Preserve) - { - DBG1, 8 - } - - OperationRegion (EXTM, SystemMemory, 0x000FF83C, 0x04) - Field (EXTM, WordAcc, Lock, Preserve) - { - AMEM, 32 - } - - OperationRegion (VGAM, SystemMemory, 0x000C0002, 0x01) - Field (VGAM, ByteAcc, Lock, Preserve) - { - VGA1, 8 - } - - OperationRegion (GRAM, SystemMemory, 0x0400, 0x0100) - Field (GRAM, ByteAcc, Lock, Preserve) - { - Offset (0x10), - FLG0, 8 - } - - OperationRegion (GSTS, SystemIO, 0xC028, 0x02) - Field (GSTS, ByteAcc, NoLock, Preserve) - { - , 4, - IRQR, 1 - } - - OperationRegion (Z007, SystemIO, 0x21, 0x01) - Field (Z007, ByteAcc, NoLock, Preserve) - { - Z008, 8 - } - - OperationRegion (Z009, SystemIO, 0xA1, 0x01) - Field (Z009, ByteAcc, NoLock, Preserve) - { - Z00A, 8 - } - - #include -} diff --git a/src/mainboard/amd/serengeti_cheetah_fam10/fadt.c b/src/mainboard/amd/serengeti_cheetah_fam10/fadt.c deleted file mode 100644 index 9f6d48c151..0000000000 --- a/src/mainboard/amd/serengeti_cheetah_fam10/fadt.c +++ /dev/null @@ -1,159 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2005 Stefan Reinauer - * Copyright (C) 2007 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -/* - * ACPI - create the Fixed ACPI Description Tables (FADT) - */ - - -#include -#include -#include -#include - -extern u32 pm_base; /* pm_base should be set in sb ACPI */ - -void acpi_create_fadt(acpi_fadt_t *fadt,acpi_facs_t *facs,void *dsdt){ - - acpi_header_t *header=&(fadt->header); - - printk(BIOS_DEBUG, "pm_base: 0x%04x\n", pm_base); - - /* Prepare the header */ - memset((void *)fadt,0,sizeof(acpi_fadt_t)); - memcpy(header->signature,"FACP",4); - header->length = sizeof(acpi_fadt_t); - header->revision = get_acpi_table_revision(FADT); - memcpy(header->oem_id,OEM_ID,6); - memcpy(header->oem_table_id, ACPI_TABLE_CREATOR, 8); - memcpy(header->asl_compiler_id,ASLC,4); - header->asl_compiler_revision = asl_revision; - - fadt->firmware_ctrl=(u32)facs; - fadt->dsdt= (u32)dsdt; - /* 3 = Workstation, 4 = Enterprise Server, 7 = Performance Server */ - fadt->preferred_pm_profile = 0x03; - fadt->sci_int = 9; - /* disable system management mode by setting to 0: */ - fadt->smi_cmd = 0;/* pm_base+0x2f */ - fadt->acpi_enable = 0xf0; - fadt->acpi_disable = 0xf1; - fadt->s4bios_req = 0x0; - fadt->pstate_cnt = 0x00; /* SMM is not used for p-state control */ - - fadt->pm1a_evt_blk = pm_base; - fadt->pm1b_evt_blk = 0x0000; - fadt->pm1a_cnt_blk = pm_base+0x04; - fadt->pm1b_cnt_blk = 0x0000; - fadt->pm2_cnt_blk = 0x0000; - fadt->pm_tmr_blk = pm_base+0x08; - fadt->gpe0_blk = pm_base+0x20; - fadt->gpe1_blk = pm_base+0xb0; - - fadt->pm1_evt_len = 4; - fadt->pm1_cnt_len = 2; - fadt->pm2_cnt_len = 0; - fadt->pm_tmr_len = 4; - fadt->gpe0_blk_len = 4; - fadt->gpe1_blk_len = 8; - fadt->gpe1_base = 16; - - fadt->cst_cnt = 0x00;/* SMM is not used for p-state control */ - fadt->p_lvl2_lat = 101; - fadt->p_lvl3_lat = 1001; - fadt->flush_size = 0; - fadt->flush_stride = 0; - fadt->duty_offset = 1; - fadt->duty_width = 3; - fadt->day_alrm = 0; /* 0x7d these have to be */ - fadt->mon_alrm = 0; /* 0x7e added to cmos.layout */ - fadt->century = 0; /* 0x7f to make rtc alrm work */ - fadt->iapc_boot_arch = 0x3; /* See table 5-11 */ - fadt->flags = 0x25; - - fadt->res2 = 0; - - fadt->reset_reg.space_id = 1; - fadt->reset_reg.bit_width = 8; - fadt->reset_reg.bit_offset = 0; - fadt->reset_reg.access_size = 0; - fadt->reset_reg.addrl = 0xcf9; - fadt->reset_reg.addrh = 0x0; - - fadt->reset_value = 6; - fadt->x_firmware_ctl_l = (u32)facs; - fadt->x_firmware_ctl_h = 0; - fadt->x_dsdt_l = (u32)dsdt; - fadt->x_dsdt_h = 0; - - fadt->x_pm1a_evt_blk.space_id = 1; - fadt->x_pm1a_evt_blk.bit_width = 32; - fadt->x_pm1a_evt_blk.bit_offset = 0; - fadt->x_pm1a_evt_blk.access_size = 0; - fadt->x_pm1a_evt_blk.addrl = pm_base; - fadt->x_pm1a_evt_blk.addrh = 0x0; - - fadt->x_pm1b_evt_blk.space_id = 1; - fadt->x_pm1b_evt_blk.bit_width = 4; - fadt->x_pm1b_evt_blk.bit_offset = 0; - fadt->x_pm1b_evt_blk.access_size = 0; - fadt->x_pm1b_evt_blk.addrl = 0x0; - fadt->x_pm1b_evt_blk.addrh = 0x0; - - fadt->x_pm1a_cnt_blk.space_id = 1; - fadt->x_pm1a_cnt_blk.bit_width = 16; - fadt->x_pm1a_cnt_blk.bit_offset = 0; - fadt->x_pm1a_cnt_blk.access_size = 0; - fadt->x_pm1a_cnt_blk.addrl = pm_base+4; - fadt->x_pm1a_cnt_blk.addrh = 0x0; - - fadt->x_pm1b_cnt_blk.space_id = 1; - fadt->x_pm1b_cnt_blk.bit_width = 2; - fadt->x_pm1b_cnt_blk.bit_offset = 0; - fadt->x_pm1b_cnt_blk.access_size = 0; - fadt->x_pm1b_cnt_blk.addrl = 0x0; - fadt->x_pm1b_cnt_blk.addrh = 0x0; - - fadt->x_pm2_cnt_blk.space_id = 1; - fadt->x_pm2_cnt_blk.bit_width = 0; - fadt->x_pm2_cnt_blk.bit_offset = 0; - fadt->x_pm2_cnt_blk.access_size = 0; - fadt->x_pm2_cnt_blk.addrl = 0x0; - fadt->x_pm2_cnt_blk.addrh = 0x0; - - fadt->x_pm_tmr_blk.space_id = 1; - fadt->x_pm_tmr_blk.bit_width = 32; - fadt->x_pm_tmr_blk.bit_offset = 0; - fadt->x_pm_tmr_blk.access_size = 0; - fadt->x_pm_tmr_blk.addrl = pm_base+0x08; - fadt->x_pm_tmr_blk.addrh = 0x0; - - fadt->x_gpe0_blk.space_id = 1; - fadt->x_gpe0_blk.bit_width = 32; - fadt->x_gpe0_blk.bit_offset = 0; - fadt->x_gpe0_blk.access_size = 0; - fadt->x_gpe0_blk.addrl = pm_base+0x20; - fadt->x_gpe0_blk.addrh = 0x0; - - fadt->x_gpe1_blk.space_id = 1; - fadt->x_gpe1_blk.bit_width = 64; - fadt->x_gpe1_blk.bit_offset = 16; - fadt->x_gpe1_blk.access_size = 0; - fadt->x_gpe1_blk.addrl = pm_base+0xb0; - fadt->x_gpe1_blk.addrh = 0x0; - - header->checksum = acpi_checksum((void *)fadt, sizeof(acpi_fadt_t)); -} diff --git a/src/mainboard/amd/serengeti_cheetah_fam10/get_bus_conf.c b/src/mainboard/amd/serengeti_cheetah_fam10/get_bus_conf.c deleted file mode 100644 index 82670bd586..0000000000 --- a/src/mainboard/amd/serengeti_cheetah_fam10/get_bus_conf.c +++ /dev/null @@ -1,167 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include -#include -#include - -#include - -#include -#include "mb_sysconf.h" - -/* Global variables for MB layouts and these will be shared by irqtable mptable and acpi_tables */ -struct mb_sysconf_t mb_sysconf; - - -static u32 get_hcid(u32 i) -{ - u32 id = 0; - u32 busn = (sysconf.pci1234[i] >> 12) & 0xff; - u32 devn = sysconf.hcdn[i] & 0xff; - struct device *dev; - - dev = dev_find_slot(busn, PCI_DEVFN(devn,0)); - - if (dev == NULL) - die("ERROR - could not find PCI %02x:%02x.0\n", busn, PCI_DEVFN(devn, 0)); - - switch (dev->device) { - case 0x7458: /* 8132 */ - id = 1; - break; - case 0x7454: /* 8151 */ - id = 2; - break; - case 0x7450: /* 8131 */ - id = 3; - break; - } - /* we may need more way to find out hcid: subsystem id? GPIO read ? */ - /* we need use id for 1. bus num, 2. mptable, 3. ACPI table */ - return id; -} - -void get_bus_conf(void) -{ - u32 apicid_base; - - struct device *dev; - int i, j; - struct mb_sysconf_t *m; - - sysconf.mb = &mb_sysconf; - - m = sysconf.mb; - - get_default_pci1234(32); - - sysconf.sbdn = (sysconf.hcdn[0] >> 8) & 0xff; - m->sbdn3 = sysconf.hcdn[0] & 0xff; - - m->bus_8132_0 = (sysconf.pci1234[0] >> 12) & 0xff; - m->bus_8111_0 = m->bus_8132_0; - - /* 8111 */ - dev = dev_find_slot(m->bus_8111_0, PCI_DEVFN(sysconf.sbdn,0)); - if (dev) { - m->bus_8111_1 = pci_read_config8(dev, PCI_SECONDARY_BUS); - } else { - printk(BIOS_DEBUG, "ERROR - could not find PCI %02x:%02x.0, using defaults\n", m->bus_8111_0, sysconf.sbdn); - } - - /* 8132-1 */ - dev = dev_find_slot(m->bus_8132_0, PCI_DEVFN(m->sbdn3,0)); - if (dev) { - m->bus_8132_1 = pci_read_config8(dev, PCI_SECONDARY_BUS); - } else { - printk(BIOS_DEBUG, "ERROR - could not find PCI %02x:%02x.0, using defaults\n", m->bus_8132_0, m->sbdn3); - } - - /* 8132-2 */ - dev = dev_find_slot(m->bus_8132_0, PCI_DEVFN(m->sbdn3+1,0)); - if (dev) { - m->bus_8132_2 = pci_read_config8(dev, PCI_SECONDARY_BUS); - } else { - printk(BIOS_DEBUG, "ERROR - could not find PCI %02x:%02x.0, using defaults\n", m->bus_8132_0, m->sbdn3+1); - } - - /* HT chain 1 */ - j = 0; - for (i = 1; i < sysconf.hc_possible_num; i++) { - if (!(sysconf.pci1234[i] & 0x1)) - continue; - - /* check hcid type here */ - sysconf.hcid[i] = get_hcid(i); - - switch (sysconf.hcid[i]) { - - case 1: /* 8132 */ - case 3: /* 8131 */ - - m->bus_8132a[j][0] = (sysconf.pci1234[i] >> 12) & 0xff; - - m->sbdn3a[j] = sysconf.hcdn[i] & 0xff; - - /* 8132-1 */ - dev = dev_find_slot(m->bus_8132a[j][0], PCI_DEVFN(m->sbdn3a[j],0)); - if (dev) { - m->bus_8132a[j][1] = pci_read_config8(dev, PCI_SECONDARY_BUS); - } else { - printk(BIOS_DEBUG, "ERROR - could not find PCI %02x:%02x.0, using defaults\n", m->bus_8132a[j][0], m->sbdn3a[j]); - } - - /* 8132-2 */ - dev = dev_find_slot(m->bus_8132a[j][0], PCI_DEVFN(m->sbdn3a[j]+1,0)); - if (dev) { - m->bus_8132a[j][2] = pci_read_config8(dev, PCI_SECONDARY_BUS); - } else { - printk(BIOS_DEBUG, "ERROR - could not find PCI %02x:%02x.0, using defaults\n", m->bus_8132a[j][0], m->sbdn3a[j]+1); - } - - break; - - case 2: /* 8151 */ - - m->bus_8151[j][0] = (sysconf.pci1234[i] >> 12) & 0xff; - m->sbdn5[j] = sysconf.hcdn[i] & 0xff; - /* 8151 */ - dev = dev_find_slot(m->bus_8151[j][0], PCI_DEVFN(m->sbdn5[j]+1, 0)); - - if (dev) { - m->bus_8151[j][1] = pci_read_config8(dev, PCI_SECONDARY_BUS); - } else { - printk(BIOS_DEBUG, "ERROR - could not find PCI %02x:%02x.0, using defaults\n", m->bus_8151[j][0], m->sbdn5[j]+1); - } - - break; - } - - j++; - } - -/*I/O APICs: APIC ID Version State Address*/ - apicid_base = 0; - m->apicid_8111 = apicid_base + 0; - m->apicid_8132_1 = apicid_base + 1; - m->apicid_8132_2 = apicid_base + 2; - for (i = 0; i < j; i++) { - m->apicid_8132a[i][0] = apicid_base + 3 + i * 2; - m->apicid_8132a[i][1] = apicid_base + 3 + i * 2 + 1; - } -} diff --git a/src/mainboard/amd/serengeti_cheetah_fam10/irq_tables.c b/src/mainboard/amd/serengeti_cheetah_fam10/irq_tables.c deleted file mode 100644 index 8fc7153f68..0000000000 --- a/src/mainboard/amd/serengeti_cheetah_fam10/irq_tables.c +++ /dev/null @@ -1,141 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include -#include -#include -#include - -#include "mb_sysconf.h" - -static void write_pirq_info(struct irq_info *pirq_info, u8 bus, u8 devfn, - u8 link0, u16 bitmap0, u8 link1, u16 bitmap1, - u8 link2, u16 bitmap2, u8 link3, u16 bitmap3, - u8 slot, u8 rfu) -{ - pirq_info->bus = bus; - pirq_info->devfn = devfn; - pirq_info->irq[0].link = link0; - pirq_info->irq[0].bitmap = bitmap0; - pirq_info->irq[1].link = link1; - pirq_info->irq[1].bitmap = bitmap1; - pirq_info->irq[2].link = link2; - pirq_info->irq[2].bitmap = bitmap2; - pirq_info->irq[3].link = link3; - pirq_info->irq[3].bitmap = bitmap3; - pirq_info->slot = slot; - pirq_info->rfu = rfu; -} - -unsigned long write_pirq_routing_table(unsigned long addr) -{ - - struct irq_routing_table *pirq; - struct irq_info *pirq_info; - u32 slot_num; - u8 *v; - - u8 sum = 0; - int i; - - struct mb_sysconf_t *m; - - m = sysconf.mb; - - /* Align the table to be 16 byte aligned. */ - addr += 15; - addr &= ~15; - - /* This table must be between 0xf0000 & 0x100000 */ - printk(BIOS_INFO, "Writing IRQ routing tables to 0x%lx...", addr); - - pirq = (void *)(addr); - v = (u8 *) (addr); - - pirq->signature = PIRQ_SIGNATURE; - pirq->version = PIRQ_VERSION; - - pirq->rtr_bus = m->bus_8111_0; - pirq->rtr_devfn = ((sysconf.sbdn + 1) << 3) | 0; - - pirq->exclusive_irqs = 0; - - pirq->rtr_vendor = 0x1022; - pirq->rtr_device = 0x746b; - - pirq->miniport_data = 0; - - memset(pirq->rfu, 0, sizeof(pirq->rfu)); - - pirq_info = (void *)(&pirq->checksum + 1); - slot_num = 0; - - /* pci bridge */ - write_pirq_info(pirq_info, m->bus_8111_0, ((sysconf.sbdn + 1) << 3) | 0, - 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, - 0); - pirq_info++; - slot_num++; - - /* pcix bridge */ - - int j = 0; - - for (i = 1; i < sysconf.hc_possible_num; i++) { - if (!(sysconf.pci1234[i] & 0x1)) - continue; - u32 busn = (sysconf.pci1234[i] >> 12) & 0xff; - u32 devn = sysconf.hcdn[i] & 0xff; - - write_pirq_info(pirq_info, busn, PCI_DEVFN(devn, 0), 0x1, 0xdef8, - 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, 0); - pirq_info++; - slot_num++; - j++; - - } - -#if CONFIG_CBB - write_pirq_info(pirq_info, CONFIG_CBB, PCI_DEVFN(0, 0), 0x1, 0xdef8, 0x2, - 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, 0); - pirq_info++; - slot_num++; - if (sysconf.nodes > 32) { - write_pirq_info(pirq_info, CONFIG_CBB - 1, PCI_DEVFN(0, 0), 0x1, - 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, - 0, 0); - pirq_info++; - slot_num++; - } -#endif - - pirq->size = 32 + 16 * slot_num; - - for (i = 0; i < pirq->size; i++) { - sum += v[i]; - } - - sum = pirq->checksum - sum; - - if (sum != pirq->checksum) { - pirq->checksum = sum; - } - - printk(BIOS_INFO, "done.\n"); - - return (unsigned long)pirq_info; -} diff --git a/src/mainboard/amd/serengeti_cheetah_fam10/mainboard.c b/src/mainboard/amd/serengeti_cheetah_fam10/mainboard.c deleted file mode 100644 index ac91940b85..0000000000 --- a/src/mainboard/amd/serengeti_cheetah_fam10/mainboard.c +++ /dev/null @@ -1,25 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include "mainboard.h" - -static void mainboard_enable(struct device *dev) -{ - dev->ops->write_acpi_tables = mainboard_write_acpi_tables; -} - -struct chip_operations mainboard_ops = { - .enable_dev = mainboard_enable, -}; diff --git a/src/mainboard/amd/serengeti_cheetah_fam10/mainboard.h b/src/mainboard/amd/serengeti_cheetah_fam10/mainboard.h deleted file mode 100644 index 2613374e3c..0000000000 --- a/src/mainboard/amd/serengeti_cheetah_fam10/mainboard.h +++ /dev/null @@ -1,14 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -unsigned long mainboard_write_acpi_tables(struct device *device, unsigned long start, acpi_rsdp_t *rsdp); diff --git a/src/mainboard/amd/serengeti_cheetah_fam10/mb_sysconf.h b/src/mainboard/amd/serengeti_cheetah_fam10/mb_sysconf.h deleted file mode 100644 index 7d8cf00390..0000000000 --- a/src/mainboard/amd/serengeti_cheetah_fam10/mb_sysconf.h +++ /dev/null @@ -1,38 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef MB_SYSCONF_H - -#define MB_SYSCONF_H - -struct mb_sysconf_t { - u8 bus_8132_0; - u8 bus_8132_1; - u8 bus_8132_2; - u8 bus_8111_0; - u8 bus_8111_1; - u8 bus_8132a[31][3]; - u8 bus_8151[31][2]; - - u32 apicid_8111; - u32 apicid_8132_1; - u32 apicid_8132_2; - u32 apicid_8132a[31][2]; - u32 sbdn3; - u32 sbdn3a[31]; - u32 sbdn5[31]; -}; - -#endif diff --git a/src/mainboard/amd/serengeti_cheetah_fam10/mptable.c b/src/mainboard/amd/serengeti_cheetah_fam10/mptable.c deleted file mode 100644 index d65b82abf2..0000000000 --- a/src/mainboard/amd/serengeti_cheetah_fam10/mptable.c +++ /dev/null @@ -1,192 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include -#include -#if CONFIG(LOGICAL_CPUS) -#include -#endif -#include -#include "mb_sysconf.h" - -static void *smp_write_config_table(void *v) -{ - int i, j, bus_isa; - struct mp_config_table *mc; - struct mb_sysconf_t *m; - - mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); - - mptable_init(mc, LOCAL_APIC_ADDR); - - smp_write_processors(mc); - - m = sysconf.mb; - - mptable_write_buses(mc, NULL, &bus_isa); - - /* I/O APICs: APIC ID Version State Address*/ - smp_write_ioapic(mc, m->apicid_8111, 0x11, VIO_APIC_VADDR); /* 8111 */ - { - struct device *dev; - struct resource *res; - dev = dev_find_slot(m->bus_8132_0, PCI_DEVFN(m->sbdn3, 1)); - if (dev) { - res = find_resource(dev, PCI_BASE_ADDRESS_0); - if (res) { - smp_write_ioapic(mc, m->apicid_8132_1, 0x11, - res2mmio(res, 0, 0)); - } - } - dev = dev_find_slot(m->bus_8132_0, PCI_DEVFN(m->sbdn3+1, 1)); - if (dev) { - res = find_resource(dev, PCI_BASE_ADDRESS_0); - if (res) { - smp_write_ioapic(mc, m->apicid_8132_2, 0x11, - res2mmio(res, 0, 0)); - } - } - - j = 0; - - for (i = 1; i < sysconf.hc_possible_num; i++) { - if (!(sysconf.pci1234[i] & 0x1)) - continue; - - switch (sysconf.hcid[i]) { - case 1: - case 3: - dev = dev_find_slot(m->bus_8132a[j][0], PCI_DEVFN(m->sbdn3a[j], 1)); - if (dev) { - res = find_resource(dev, PCI_BASE_ADDRESS_0); - if (res) { - smp_write_ioapic(mc, m->apicid_8132a[j][0], 0x11, - res2mmio(res, 0, 0)); - } - } - dev = dev_find_slot(m->bus_8132a[j][0], PCI_DEVFN(m->sbdn3a[j]+1, 1)); - if (dev) { - res = find_resource(dev, PCI_BASE_ADDRESS_0); - if (res) { - smp_write_ioapic(mc, m->apicid_8132a[j][1], 0x11, - res2mmio(res, 0, 0)); - } - } - break; - } - j++; - } - - } - - mptable_add_isa_interrupts(mc, bus_isa, m->apicid_8111, 0); - - /* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN#*/ -/* ??? What */ - smp_write_pci_intsrc(mc, mp_INT, m->bus_8111_0, sysconf.sbdn+1, 3, m->apicid_8111, 0x13); - - /* Onboard AMD USB */ - smp_write_pci_intsrc(mc, mp_INT, m->bus_8111_1, 0, 3, m->apicid_8111, 0x13); - - /* Slot 3 PCI 32 */ - for (i = 0; i < 4; i++) { - smp_write_pci_intsrc(mc, mp_INT, m->bus_8111_1, 5, i, m->apicid_8111, 0x10 + (1+i)%4); /* 16 */ - } - - - /* Slot 4 PCI 32 */ - for (i = 0; i < 4; i++) { - smp_write_pci_intsrc(mc, mp_INT, m->bus_8111_1, 4, i, m->apicid_8111, 0x10 + (0+i)%4); /* 16 */ - } - - - /* Slot 1 PCI-X 133/100/66 */ - for (i = 0; i < 4; i++) { - smp_write_pci_intsrc(mc, mp_INT, m->bus_8132_2, 1, i, m->apicid_8132_2, (0+i)%4); - } - - - /* Slot 2 PCI-X 133/100/66 */ - for (i = 0; i < 4; i++) { - smp_write_pci_intsrc(mc, mp_INT, m->bus_8132_1, 1, i, m->apicid_8132_1, (1+i)%4); /* 25 */ - } - - j = 0; - - for (i = 1; i < sysconf.hc_possible_num; i++) { - if (!(sysconf.pci1234[i] & 0x1)) - continue; - int ii; - int jj; - struct device *dev; - struct resource *res; - switch (sysconf.hcid[i]) { - case 1: - case 3: - dev = dev_find_slot(m->bus_8132a[j][0], PCI_DEVFN(m->sbdn3a[j], 1)); - if (dev) { - res = find_resource(dev, PCI_BASE_ADDRESS_0); - if (res) { - for (jj = 0; jj < 4; jj++) { - /* Slot 1 PCI-X 133/100/66 */ - for (ii = 0; ii < 4; ii++) { - smp_write_pci_intsrc(mc, mp_INT, m->bus_8132a[j][1], jj, ii, m->apicid_8132a[j][0], (jj+ii)%4); - } - } - } - } - - dev = dev_find_slot(m->bus_8132a[j][0], PCI_DEVFN(m->sbdn3a[j]+1, 1)); - if (dev) { - res = find_resource(dev, PCI_BASE_ADDRESS_0); - if (res) { - for (jj = 0; jj < 4; jj++) { - /* Slot 2 PCI-X 133/100/66 */ - for (ii = 0; ii < 4; ii++) { - smp_write_pci_intsrc(mc, mp_INT, m->bus_8132a[j][2], jj, ii, m->apicid_8132a[j][1], (jj+ii)%4); /* 25 */ - } - } - } - } - - break; - case 2: - - /* Slot AGP */ - smp_write_pci_intsrc(mc, mp_INT, m->bus_8151[j][1], 0x0, 0, m->apicid_8111, 0x11); - break; - } - - j++; - } - - - - /* Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN#*/ - mptable_lintsrc(mc, bus_isa); - /* There is no extension information... */ - - /* Compute the checksums */ - return mptable_finalize(mc); -} - -unsigned long write_smp_table(unsigned long addr) -{ - void *v; - v = smp_write_floating_table(addr, 0); - return (unsigned long)smp_write_config_table(v); -} diff --git a/src/mainboard/amd/serengeti_cheetah_fam10/resourcemap.c b/src/mainboard/amd/serengeti_cheetah_fam10/resourcemap.c deleted file mode 100644 index ad99aa835f..0000000000 --- a/src/mainboard/amd/serengeti_cheetah_fam10/resourcemap.c +++ /dev/null @@ -1,273 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include - -void setup_mb_resource_map(void) -{ - static const unsigned int register_values[] = { - /* Careful set limit registers before base registers which contain the enables */ - /* DRAM Limit i Registers - * F1:0x44 i = 0 - * F1:0x4C i = 1 - * F1:0x54 i = 2 - * F1:0x5C i = 3 - * F1:0x64 i = 4 - * F1:0x6C i = 5 - * F1:0x74 i = 6 - * F1:0x7C i = 7 - * [ 2: 0] Destination Node ID - * 000 = Node 0 - * 001 = Node 1 - * 010 = Node 2 - * 011 = Node 3 - * 100 = Node 4 - * 101 = Node 5 - * 110 = Node 6 - * 111 = Node 7 - * [ 7: 3] Reserved - * [10: 8] Interleave select - * specifies the values of A[14:12] to use with interleave enable. - * [15:11] Reserved - * [31:16] DRAM Limit Address i Bits 39-24 - * This field defines the upper address bits of a 40 bit address - * that define the end of the DRAM region. - */ - /* Don't touch it, we need it for CAR with FAM10 */ - ADDRMAP_REG(0x4C), 0x0000f8f8, 0x00000001, - ADDRMAP_REG(0x54), 0x0000f8f8, 0x00000002, - ADDRMAP_REG(0x5C), 0x0000f8f8, 0x00000003, - ADDRMAP_REG(0x64), 0x0000f8f8, 0x00000004, - ADDRMAP_REG(0x6C), 0x0000f8f8, 0x00000005, - ADDRMAP_REG(0x74), 0x0000f8f8, 0x00000006, - ADDRMAP_REG(0x7C), 0x0000f8f8, 0x00000007, - /* DRAM Base i Registers - * F1:0x40 i = 0 - * F1:0x48 i = 1 - * F1:0x50 i = 2 - * F1:0x58 i = 3 - * F1:0x60 i = 4 - * F1:0x68 i = 5 - * F1:0x70 i = 6 - * F1:0x78 i = 7 - * [ 0: 0] Read Enable - * 0 = Reads Disabled - * 1 = Reads Enabled - * [ 1: 1] Write Enable - * 0 = Writes Disabled - * 1 = Writes Enabled - * [ 7: 2] Reserved - * [10: 8] Interleave Enable - * 000 = No interleave - * 001 = Interleave on A[12] (2 nodes) - * 010 = reserved - * 011 = Interleave on A[12] and A[14] (4 nodes) - * 100 = reserved - * 101 = reserved - * 110 = reserved - * 111 = Interleve on A[12] and A[13] and A[14] (8 nodes) - * [15:11] Reserved - * [13:16] DRAM Base Address i Bits 39-24 - * This field defines the upper address bits of a 40-bit address - * that define the start of the DRAM region. - */ - /* don't touch it, we need it for CAR with FAM10 */ - ADDRMAP_REG(0x48), 0x0000f8fc, 0x00000000, - ADDRMAP_REG(0x50), 0x0000f8fc, 0x00000000, - ADDRMAP_REG(0x58), 0x0000f8fc, 0x00000000, - ADDRMAP_REG(0x60), 0x0000f8fc, 0x00000000, - ADDRMAP_REG(0x68), 0x0000f8fc, 0x00000000, - ADDRMAP_REG(0x70), 0x0000f8fc, 0x00000000, - ADDRMAP_REG(0x78), 0x0000f8fc, 0x00000000, - - /* Memory-Mapped I/O Limit i Registers - * F1:0x84 i = 0 - * F1:0x8C i = 1 - * F1:0x94 i = 2 - * F1:0x9C i = 3 - * F1:0xA4 i = 4 - * F1:0xAC i = 5 - * F1:0xB4 i = 6 - * F1:0xBC i = 7 - * [ 2: 0] Destination Node ID - * 000 = Node 0 - * 001 = Node 1 - * 010 = Node 2 - * 011 = Node 3 - * 100 = Node 4 - * 101 = Node 5 - * 110 = Node 6 - * 111 = Node 7 - * [ 3: 3] Reserved - * [ 5: 4] Destination Link ID - * 00 = Link 0 - * 01 = Link 1 - * 10 = Link 2 - * 11 = Reserved - * [ 6: 6] Reserved - * [ 7: 7] Non-Posted - * 0 = CPU writes may be posted - * 1 = CPU writes must be non-posted - * [31: 8] Memory-Mapped I/O Limit Address i (39-16) - * This field defines the upp address bits of a 40-bit address that - * defines the end of a memory-mapped I/O region n - */ - ADDRMAP_REG(0x84), 0x00000048, 0x00000000, - ADDRMAP_REG(0x8C), 0x00000048, 0x00000000, - ADDRMAP_REG(0x94), 0x00000048, 0x00000000, - ADDRMAP_REG(0x9C), 0x00000048, 0x00000000, - ADDRMAP_REG(0xA4), 0x00000048, 0x00000000, - ADDRMAP_REG(0xAC), 0x00000048, 0x00000000, - ADDRMAP_REG(0xB4), 0x00000048, 0x00000000, - - /* Memory-Mapped I/O Base i Registers - * F1:0x80 i = 0 - * F1:0x88 i = 1 - * F1:0x90 i = 2 - * F1:0x98 i = 3 - * F1:0xA0 i = 4 - * F1:0xA8 i = 5 - * F1:0xB0 i = 6 - * F1:0xB8 i = 7 - * [ 0: 0] Read Enable - * 0 = Reads disabled - * 1 = Reads Enabled - * [ 1: 1] Write Enable - * 0 = Writes disabled - * 1 = Writes Enabled - * [ 2: 2] Cpu Disable - * 0 = Cpu can use this I/O range - * 1 = Cpu requests do not use this I/O range - * [ 3: 3] Lock - * 0 = base/limit registers i are read/write - * 1 = base/limit registers i are read-only - * [ 7: 4] Reserved - * [31: 8] Memory-Mapped I/O Base Address i (39-16) - * This field defines the upper address bits of a 40bit address - * that defines the start of memory-mapped I/O region i - */ - ADDRMAP_REG(0x80), 0x000000f0, 0x00000000, - ADDRMAP_REG(0x88), 0x000000f0, 0x00000000, - ADDRMAP_REG(0x90), 0x000000f0, 0x00000000, - ADDRMAP_REG(0x98), 0x000000f0, 0x00000000, - ADDRMAP_REG(0xA0), 0x000000f0, 0x00000000, - ADDRMAP_REG(0xA8), 0x000000f0, 0x00000000, - ADDRMAP_REG(0xB0), 0x000000f0, 0x00000000, - - /* PCI I/O Limit i Registers - * F1:0xC4 i = 0 - * F1:0xCC i = 1 - * F1:0xD4 i = 2 - * F1:0xDC i = 3 - * [ 2: 0] Destination Node ID - * 000 = Node 0 - * 001 = Node 1 - * 010 = Node 2 - * 011 = Node 3 - * 100 = Node 4 - * 101 = Node 5 - * 110 = Node 6 - * 111 = Node 7 - * [ 3: 3] Reserved - * [ 5: 4] Destination Link ID - * 00 = Link 0 - * 01 = Link 1 - * 10 = Link 2 - * 11 = reserved - * [11: 6] Reserved - * [24:12] PCI I/O Limit Address i - * This field defines the end of PCI I/O region n - * [31:25] Reserved - */ - ADDRMAP_REG(0xCC), 0xFE000FC8, 0x00000000, - ADDRMAP_REG(0xD4), 0xFE000FC8, 0x00000000, - ADDRMAP_REG(0xDC), 0xFE000FC8, 0x00000000, - - /* PCI I/O Base i Registers - * F1:0xC0 i = 0 - * F1:0xC8 i = 1 - * F1:0xD0 i = 2 - * F1:0xD8 i = 3 - * [ 0: 0] Read Enable - * 0 = Reads Disabled - * 1 = Reads Enabled - * [ 1: 1] Write Enable - * 0 = Writes Disabled - * 1 = Writes Enabled - * [ 3: 2] Reserved - * [ 4: 4] VGA Enable - * 0 = VGA matches Disabled - * 1 = matches all address < 64K and where A[9:0] is in the - * range 3B0-3BB or 3C0-3DF independen of the base & limit registers - * [ 5: 5] ISA Enable - * 0 = ISA matches Disabled - * 1 = Blocks address < 64K and in the last 768 bytes of eack 1K block - * from matching agains this base/limit pair - * [11: 6] Reserved - * [24:12] PCI I/O Base i - * This field defines the start of PCI I/O region n - * [31:25] Reserved - */ - ADDRMAP_REG(0xC8), 0xFE000FCC, 0x00000000, - ADDRMAP_REG(0xD0), 0xFE000FCC, 0x00000000, - ADDRMAP_REG(0xD8), 0xFE000FCC, 0x00000000, - - /* Config Base and Limit i Registers - * F1:0xE0 i = 0 - * F1:0xE4 i = 1 - * F1:0xE8 i = 2 - * F1:0xEC i = 3 - * [ 0: 0] Read Enable - * 0 = Reads Disabled - * 1 = Reads Enabled - * [ 1: 1] Write Enable - * 0 = Writes Disabled - * 1 = Writes Enabled - * [ 2: 2] Device Number Compare Enable - * 0 = The ranges are based on bus number - * 1 = The ranges are ranges of devices on bus 0 - * [ 3: 3] Reserved - * [ 6: 4] Destination Node - * 000 = Node 0 - * 001 = Node 1 - * 010 = Node 2 - * 011 = Node 3 - * 100 = Node 4 - * 101 = Node 5 - * 110 = Node 6 - * 111 = Node 7 - * [ 7: 7] Reserved - * [ 9: 8] Destination Link - * 00 = Link 0 - * 01 = Link 1 - * 10 = Link 2 - * 11 - Reserved - * [15:10] Reserved - * [23:16] Bus Number Base i - * This field defines the lowest bus number in configuration region i - * [31:24] Bus Number Limit i - * This field defines the highest bus number in configuration regin i - */ - /* AMD 8111 on link0 of CPU 0 */ - ADDRMAP_REG(0xE4), 0x0000FC88, 0x00000000, - ADDRMAP_REG(0xE8), 0x0000FC88, 0x00000000, - ADDRMAP_REG(0xEC), 0x0000FC88, 0x00000000, - }; - - int max; - max = ARRAY_SIZE(register_values); - setup_resource_map(register_values, max); -} diff --git a/src/mainboard/amd/serengeti_cheetah_fam10/romstage.c b/src/mainboard/amd/serengeti_cheetah_fam10/romstage.c deleted file mode 100644 index 3871c592d5..0000000000 --- a/src/mainboard/amd/serengeti_cheetah_fam10/romstage.c +++ /dev/null @@ -1,334 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007-2008 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#define SYSTEM_TYPE 0 /* SERVER */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include "southbridge/amd/amd8111/early_smbus.c" -#include "southbridge/amd/amd8111/early_ctrl.c" - -#include "cpu/amd/quadcore/quadcore.c" - -#define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1) - -int spd_read_byte(unsigned int device, unsigned int address); - -static void memreset_setup(void) -{ - /* GPIO on amd8111 to enable MEMRST ???? */ - outb((1 << 2)|(1 << 0), SMBUS_IO_BASE + 0xc0 + 16); /* REVC_MEMRST_EN = 1 */ - outb((1 << 2)|(0 << 0), SMBUS_IO_BASE + 0xc0 + 17); -} - -void activate_spd_rom(const struct mem_controller *ctrl) -{ -#define SMBUS_HUB 0x18 - int ret,i; - u8 device = ctrl->spd_switch_addr; - - printk(BIOS_DEBUG, "switch i2c to : %02x for node %02x\n", device, ctrl->node_id); - - /* the very first write always get COL_STS = 1 and ABRT_STS = 1, so try another time*/ - i = 2; - do { - ret = smbus_write_byte(SMBUS_HUB, 0x01, (1<<(device & 0x7))); - } while ((ret != 0) && (i-->0)); - smbus_write_byte(SMBUS_HUB, 0x03, 0); -} - -int spd_read_byte(u32 device, u32 address) -{ - return smbus_read_byte(device, address); -} - -static const u8 spd_addr[] = { - /* first node */ - RC00, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, -#if CONFIG_MAX_PHYSICAL_CPUS > 1 - /* second node */ - RC01, DIMM0, DIMM2, DIMM4, DIMM6, DIMM1, DIMM3, DIMM5, DIMM7, -#endif -#if CONFIG_MAX_PHYSICAL_CPUS > 2 - /* third node */ - RC02, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, - /* forth node */ - RC03, DIMM0, DIMM2, DIMM4, DIMM6, DIMM1, DIMM3, DIMM5, DIMM7, -#endif -#if CONFIG_MAX_PHYSICAL_CPUS > 4 - RC04, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, - RC05, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, -#endif -#if CONFIG_MAX_PHYSICAL_CPUS > 6 - RC06, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, - RC07, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, -#endif -#if CONFIG_MAX_PHYSICAL_CPUS > 8 - RC08, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, - RC09, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, - RC10, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, - RC11, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, -#endif -#if CONFIG_MAX_PHYSICAL_CPUS > 12 - RC12, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, - RC13, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, - RC14, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, - RC15, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, -#endif -#if CONFIG_MAX_PHYSICAL_CPUS > 16 - RC16, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, - RC17, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, - RC18, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, - RC19, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, -#endif -#if CONFIG_MAX_PHYSICAL_CPUS > 20 - RC20, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, - RC21, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, - RC22, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, - RC23, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, -#endif -#if CONFIG_MAX_PHYSICAL_CPUS > 24 - RC24, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, - RC25, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, - RC26, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, - RC27, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, - RC28, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, - RC29, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, - RC30, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, - RC31, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, -#endif -#if CONFIG_MAX_PHYSICAL_CPUS > 32 - RC32, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, - RC33, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, - RC34, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, - RC35, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, - RC36, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, - RC37, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, - RC38, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, - RC39, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, - RC40, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, - RC41, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, - RC42, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, - RC43, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, - RC44, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, - RC45, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, - RC46, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, - RC47, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, -#endif -#if CONFIG_MAX_PHYSICAL_CPUS > 48 - RC48, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, - RC49, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, - RC50, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, - RC51, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, - RC52, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, - RC53, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, - RC54, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, - RC55, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, - RC56, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, - RC57, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, - RC58, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, - RC59, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, - RC60, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, - RC61, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, - RC62, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, - RC63, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, -#endif -}; - -void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) -{ - struct sys_info *sysinfo = get_sysinfo(); - u32 bsp_apicid = 0, val; - msr_t msr; - - timestamp_init(timestamp_get()); - timestamp_add_now(TS_START_ROMSTAGE); - - if (!cpu_init_detectedx && boot_cpu()) { - /* Nothing special needs to be done to find bus 0 */ - /* Allow the HT devices to be found */ - /* mov bsp to bus 0xff when > 8 nodes */ - set_bsp_node_CHtExtNodeCfgEn(); - enumerate_ht_chain(); - } - - post_code(0x30); - - if (bist == 0) { - bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo); /* mmconf is inited in init_cpus */ - /* All cores run this but the BSP(node0,core0) is the only core that returns. */ - } - - post_code(0x32); - - winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); - console_init(); - - /* Halt if there was a built in self test failure */ - report_bist_failure(bist); - - /* Load MPB */ - val = cpuid_eax(1); - printk(BIOS_DEBUG, "BSP Family_Model: %08x\n", val); - printk(BIOS_DEBUG, "*sysinfo range: [%p,%p]\n",sysinfo,sysinfo+1); - printk(BIOS_DEBUG, "bsp_apicid = %02x\n", bsp_apicid); - printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx); - - /* Setup sysinfo defaults */ - set_sysinfo_in_ram(0); - - update_microcode(val); - - post_code(0x33); - - cpuSetAMDMSR(0); - post_code(0x34); - - amd_ht_init(sysinfo); - post_code(0x35); - - /* Setup nodes PCI space and start core 0 AP init. */ - finalize_node_setup(sysinfo); - - /* Setup any mainboard PCI settings etc. */ - setup_mb_resource_map(); - post_code(0x36); - - /* wait for all the APs core0 started by finalize_node_setup. */ - /* FIXME: A bunch of cores are going to start output to serial at once. - It would be nice to fixup prink spinlocks for ROM XIP mode. - I think it could be done by putting the spinlock flag in the cache - of the BSP located right after sysinfo. - */ - wait_all_core0_started(); - - #if CONFIG(LOGICAL_CPUS) - /* Core0 on each node is configured. Now setup any additional cores. */ - printk(BIOS_DEBUG, "start_other_cores()\n"); - start_other_cores(bsp_apicid); - post_code(0x37); - wait_all_other_cores_started(bsp_apicid); - #endif - - post_code(0x38); - - #if CONFIG(SET_FIDVID) - msr = rdmsr(MSR_COFVID_STS); - printk(BIOS_DEBUG, "\nBegin FIDVID MSR 0xc0010071 0x%08x 0x%08x\n", msr.hi, msr.lo); - - /* FIXME: The sb fid change may survive the warm reset and only - need to be done once.*/ - enable_fid_change_on_sb(sysinfo->sbbusn, sysinfo->sbdn); - - post_code(0x39); - - if (!warm_reset_detect(0)) { /* BSP is node 0 */ - init_fidvid_bsp(bsp_apicid, sysinfo->nodes); - } else { - init_fidvid_stage2(bsp_apicid, 0); /* BSP is node 0 */ - } - - post_code(0x3A); - - /* show final fid and vid */ - msr = rdmsr(MSR_COFVID_STS); - printk(BIOS_DEBUG, "End FIDVIDMSR 0xc0010071 0x%08x 0x%08x\n", msr.hi, msr.lo); - #endif - - /* Reset for HT, FIDVID, PLL and errata changes to take affect. */ - if (!warm_reset_detect(0)) { - printk(BIOS_INFO, "...WARM RESET...\n\n\n"); - soft_reset_x(sysinfo->sbbusn, sysinfo->sbdn); - die("After soft_reset_x - shouldn't see this message!!!\n"); - } - - post_code(0x3B); - - /* FIXME: Move this to chipset init. - enable cf9 for hard reset */ - printk(BIOS_DEBUG, "enable_cf9_x()\n"); - enable_cf9_x(sysinfo->sbbusn, sysinfo->sbdn); - post_code(0x3C); - - /* It's the time to set ctrl in sysinfo now; */ - printk(BIOS_DEBUG, "fill_mem_ctrl()\n"); - fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr); - post_code(0x3D); - - printk(BIOS_DEBUG, "enable_smbus()\n"); - enable_smbus(); - post_code(0x3E); - - memreset_setup(); - post_code(0x40); - - raminit_amdmct(sysinfo); - - cbmem_initialize_empty(); - post_code(0x41); - - amdmct_cbmem_store_info(sysinfo); - - post_code(0x42); -} - -/** - * BOOL AMD_CB_ManualBUIDSwapList(u8 Node, u8 Link, u8 **List) - * Description: - * This routine is called every time a non-coherent chain is processed. - * BUID assignment may be controlled explicitly on a non-coherent chain. Provide a - * swap list. The first part of the list controls the BUID assignment and the - * second part of the list provides the device to device linking. Device orientation - * can be detected automatically, or explicitly. See documentation for more details. - * - * Automatic non-coherent init assigns BUIDs starting at 1 and incrementing sequentially - * based on each device's unit count. - * - * Parameters: - * @param[in] node = The node on which this chain is located - * @param[in] link = The link on the host for this chain - * @param[out] List = supply a pointer to a list - */ -BOOL AMD_CB_ManualBUIDSwapList (u8 node, u8 link, const u8 **List) -{ - static const u8 swaplist[] = { 0xFF, CONFIG_HT_CHAIN_UNITID_BASE, CONFIG_HT_CHAIN_END_UNITID_BASE, 0xFF }; - /* If the BUID was adjusted in early_ht we need to do the manual override */ - if ((CONFIG_HT_CHAIN_UNITID_BASE != 0) && (CONFIG_HT_CHAIN_END_UNITID_BASE != 0)) { - printk(BIOS_DEBUG, "AMD_CB_ManualBUIDSwapList()\n"); - if ((node == 0) && (link == 0)) { /* BSP SB link */ - *List = swaplist; - return 1; - } - } - - return 0; -} diff --git a/src/mainboard/amd/serengeti_cheetah_fam10/ssdt2.asl b/src/mainboard/amd/serengeti_cheetah_fam10/ssdt2.asl deleted file mode 100644 index 264e962371..0000000000 --- a/src/mainboard/amd/serengeti_cheetah_fam10/ssdt2.asl +++ /dev/null @@ -1,79 +0,0 @@ -// -// This file is part of the coreboot project. -// -// Copyright (C) 2007 Advanced Micro Devices, Inc. -// -// This program is free software; you can redistribute it and/or modify -// it under the terms of the GNU General Public License as published by -// the Free Software Foundation; version 2 of the License. -// -// This program is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. -// -#include -DefinitionBlock ("SSDT2.aml", "SSDT", 1, OEM_ID, ACPI_TABLE_CREATOR, 100925440) -{ - Scope (_SB) - { - External (DADD, MethodObj) - External (GHCE, MethodObj) - External (GHCN, MethodObj) - External (GHCL, MethodObj) - External (GHCD, MethodObj) - External (GNUS, MethodObj) - External (GIOR, MethodObj) - External (GMEM, MethodObj) - External (GWBN, MethodObj) - External (GBUS, MethodObj) - - External (PICF) - - External (\_SB.PCI0.LNKA, DeviceObj) - External (\_SB.PCI0.LNKB, DeviceObj) - External (\_SB.PCI0.LNKC, DeviceObj) - External (\_SB.PCI0.LNKD, DeviceObj) - - Device (PCIX) - { - - // BUS ? Second HT Chain - Name (HCIN, 0xcc) // HC2 0x01 - - Name (_UID, 0xdd) // HC 0x03 - - Name (_HID, "PNP0A03") - - Method (_ADR, 0, NotSerialized) //Fake bus should be 0 - { - Return (DADD(GHCN(HCIN), 0x00000000)) - } - - Method (_BBN, 0, NotSerialized) - { - Return (GBUS (GHCN(HCIN), GHCL(HCIN))) - } - - Method (_STA, 0, NotSerialized) - { - Return (\_SB.GHCE(HCIN)) - } - - Method (_CRS, 0, NotSerialized) - { - Name (BUF0, ResourceTemplate () { }) - Store( GHCN(HCIN), Local4) - Store( GHCL(HCIN), Local5) - - Concatenate (\_SB.GIOR (Local4, Local5), BUF0, Local1) - Concatenate (\_SB.GMEM (Local4, Local5), Local1, Local2) - Concatenate (\_SB.GWBN (Local4, Local5), Local2, Local3) - Return (Local3) - } - - #include "acpi/pci2_hc.asl" - } - } - -} diff --git a/src/mainboard/amd/serengeti_cheetah_fam10/ssdt3.asl b/src/mainboard/amd/serengeti_cheetah_fam10/ssdt3.asl deleted file mode 100644 index 776ea95722..0000000000 --- a/src/mainboard/amd/serengeti_cheetah_fam10/ssdt3.asl +++ /dev/null @@ -1,79 +0,0 @@ -// -// This file is part of the coreboot project. -// -// Copyright (C) 2007 Advanced Micro Devices, Inc. -// -// This program is free software; you can redistribute it and/or modify -// it under the terms of the GNU General Public License as published by -// the Free Software Foundation; version 2 of the License. -// -// This program is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. -// -#include -DefinitionBlock ("SSDT3.aml", "SSDT", 1, OEM_ID, ACPI_TABLE_CREATOR, 100925440) -{ - Scope (_SB) - { - External (DADD, MethodObj) - External (GHCE, MethodObj) - External (GHCN, MethodObj) - External (GHCL, MethodObj) - External (GHCD, MethodObj) - External (GNUS, MethodObj) - External (GIOR, MethodObj) - External (GMEM, MethodObj) - External (GWBN, MethodObj) - External (GBUS, MethodObj) - - External (PICF) - - External (\_SB.PCI0.LNKA, DeviceObj) - External (\_SB.PCI0.LNKB, DeviceObj) - External (\_SB.PCI0.LNKC, DeviceObj) - External (\_SB.PCI0.LNKD, DeviceObj) - - Device (PCIX) - { - - // BUS ? Second HT Chain - Name (HCIN, 0xcc) // HC2 0x01 - - Name (_UID, 0xdd) // HC 0x03 - - Name (_HID, "PNP0A03") - - Method (_ADR, 0, NotSerialized) //Fake bus should be 0 - { - Return (DADD(GHCN(HCIN), 0x00000000)) - } - - Method (_BBN, 0, NotSerialized) - { - Return (GBUS (GHCN(HCIN), GHCL(HCIN))) - } - - Method (_STA, 0, NotSerialized) - { - Return (\_SB.GHCE(HCIN)) - } - - Method (_CRS, 0, NotSerialized) - { - Name (BUF0, ResourceTemplate () { }) - Store( GHCN(HCIN), Local4) - Store( GHCL(HCIN), Local5) - - Concatenate (\_SB.GIOR (Local4, Local5), BUF0, Local1) - Concatenate (\_SB.GMEM (Local4, Local5), Local1, Local2) - Concatenate (\_SB.GWBN (Local4, Local5), Local2, Local3) - Return (Local3) - } - - #include "acpi/pci3_hc.asl" - } - } - -} diff --git a/src/mainboard/amd/serengeti_cheetah_fam10/ssdt4.asl b/src/mainboard/amd/serengeti_cheetah_fam10/ssdt4.asl deleted file mode 100644 index 78fc3b2922..0000000000 --- a/src/mainboard/amd/serengeti_cheetah_fam10/ssdt4.asl +++ /dev/null @@ -1,79 +0,0 @@ -// -// This file is part of the coreboot project. -// -// Copyright (C) 2007 Advanced Micro Devices, Inc. -// -// This program is free software; you can redistribute it and/or modify -// it under the terms of the GNU General Public License as published by -// the Free Software Foundation; version 2 of the License. -// -// This program is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. -// -#include -DefinitionBlock ("SSDT4.aml", "SSDT", 1, OEM_ID, ACPI_TABLE_CREATOR, 100925440) -{ - Scope (_SB) - { - External (DADD, MethodObj) - External (GHCE, MethodObj) - External (GHCN, MethodObj) - External (GHCL, MethodObj) - External (GHCD, MethodObj) - External (GNUS, MethodObj) - External (GIOR, MethodObj) - External (GMEM, MethodObj) - External (GWBN, MethodObj) - External (GBUS, MethodObj) - - External (PICF) - - External (\_SB.PCI0.LNKA, DeviceObj) - External (\_SB.PCI0.LNKB, DeviceObj) - External (\_SB.PCI0.LNKC, DeviceObj) - External (\_SB.PCI0.LNKD, DeviceObj) - - Device (PCIX) - { - - // BUS ? Second HT Chain - Name (HCIN, 0xcc) // HC2 0x01 - - Name (_UID, 0xdd) // HC 0x03 - - Name (_HID, "PNP0A03") - - Method (_ADR, 0, NotSerialized) //Fake bus should be 0 - { - Return (DADD(GHCN(HCIN), 0x00000000)) - } - - Method (_BBN, 0, NotSerialized) - { - Return (GBUS (GHCN(HCIN), GHCL(HCIN))) - } - - Method (_STA, 0, NotSerialized) - { - Return (\_SB.GHCE(HCIN)) - } - - Method (_CRS, 0, NotSerialized) - { - Name (BUF0, ResourceTemplate () { }) - Store( GHCN(HCIN), Local4) - Store( GHCL(HCIN), Local5) - - Concatenate (\_SB.GIOR (Local4, Local5), BUF0, Local1) - Concatenate (\_SB.GMEM (Local4, Local5), Local1, Local2) - Concatenate (\_SB.GWBN (Local4, Local5), Local2, Local3) - Return (Local3) - } - - #include "acpi/pci4_hc.asl" - } - } - -} diff --git a/src/mainboard/amd/serengeti_cheetah_fam10/ssdt5.asl b/src/mainboard/amd/serengeti_cheetah_fam10/ssdt5.asl deleted file mode 100644 index b44346fd44..0000000000 --- a/src/mainboard/amd/serengeti_cheetah_fam10/ssdt5.asl +++ /dev/null @@ -1,80 +0,0 @@ -// -// This file is part of the coreboot project. -// -// Copyright (C) 2007 Advanced Micro Devices, Inc. -// -// This program is free software; you can redistribute it and/or modify -// it under the terms of the GNU General Public License as published by -// the Free Software Foundation; version 2 of the License. -// -// This program is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. -// - -#include -DefinitionBlock ("SSDT5.aml", "SSDT", 1, OEM_ID, ACPI_TABLE_CREATOR, 100925440) -{ - Scope (_SB) - { - External (DADD, MethodObj) - External (GHCE, MethodObj) - External (GHCN, MethodObj) - External (GHCL, MethodObj) - External (GHCD, MethodObj) - External (GNUS, MethodObj) - External (GIOR, MethodObj) - External (GMEM, MethodObj) - External (GWBN, MethodObj) - External (GBUS, MethodObj) - - External (PICF) - - External (\_SB.PCI0.LNKA, DeviceObj) - External (\_SB.PCI0.LNKB, DeviceObj) - External (\_SB.PCI0.LNKC, DeviceObj) - External (\_SB.PCI0.LNKD, DeviceObj) - - Device (PCIX) - { - - // BUS ? Second HT Chain - Name (HCIN, 0xcc) // HC2 0x01 - - Name (_UID, 0xdd) // HC 0x03 - - Name (_HID, "PNP0A03") - - Method (_ADR, 0, NotSerialized) //Fake bus should be 0 - { - Return (DADD(GHCN(HCIN), 0x00000000)) - } - - Method (_BBN, 0, NotSerialized) - { - Return (GBUS (GHCN(HCIN), GHCL(HCIN))) - } - - Method (_STA, 0, NotSerialized) - { - Return (\_SB.GHCE(HCIN)) - } - - Method (_CRS, 0, NotSerialized) - { - Name (BUF0, ResourceTemplate () { }) - Store( GHCN(HCIN), Local4) - Store( GHCL(HCIN), Local5) - - Concatenate (\_SB.GIOR (Local4, Local5), BUF0, Local1) - Concatenate (\_SB.GMEM (Local4, Local5), Local1, Local2) - Concatenate (\_SB.GWBN (Local4, Local5), Local2, Local3) - Return (Local3) - } - - #include "acpi/pci5_hc.asl" - } - } - -} diff --git a/src/mainboard/amd/tilapia_fam10/Kconfig b/src/mainboard/amd/tilapia_fam10/Kconfig deleted file mode 100644 index 4f8c492892..0000000000 --- a/src/mainboard/amd/tilapia_fam10/Kconfig +++ /dev/null @@ -1,63 +0,0 @@ -if BOARD_AMD_TILAPIA_FAM10 - -config BOARD_SPECIFIC_OPTIONS - def_bool y - select CPU_AMD_SOCKET_AM3 - select DIMM_DDR3 - select DIMM_REGISTERED - select NORTHBRIDGE_AMD_AMDFAM10 - select SOUTHBRIDGE_AMD_RS780 - select SOUTHBRIDGE_AMD_SB700 - select SUPERIO_ITE_IT8718F - select HAVE_OPTION_TABLE - select HAVE_PIRQ_TABLE - select HAVE_MP_TABLE - select SB_HT_CHAIN_UNITID_OFFSET_ONLY - select LIFT_BSP_APIC_ID - select HAVE_ACPI_TABLES - select BOARD_ROMSIZE_KB_1024 - select ENABLE_APIC_EXT_ID - select GFXUMA - -config MAINBOARD_DIR - string - default amd/tilapia_fam10 - -config APIC_ID_OFFSET - hex - default 0x0 - -config MAINBOARD_PART_NUMBER - string - default "Tilapia (Fam10)" - -config MAX_CPUS - int - default 8 - -config MAX_PHYSICAL_CPUS - int - default 2 - -config HT_CHAIN_END_UNITID_BASE - hex - default 0x1 - -config HT_CHAIN_UNITID_BASE - hex - default 0x0 - -config IRQ_SLOT_COUNT - int - default 11 - -config VGA_BIOS - bool - default n - -config VGA_BIOS_ID - string - depends on VGA_BIOS - default "1002,9615" - -endif # BOARD_AMD_TILAPIA_FAM10 diff --git a/src/mainboard/amd/tilapia_fam10/Kconfig.name b/src/mainboard/amd/tilapia_fam10/Kconfig.name deleted file mode 100644 index 6e290c1d6c..0000000000 --- a/src/mainboard/amd/tilapia_fam10/Kconfig.name +++ /dev/null @@ -1,2 +0,0 @@ -config BOARD_AMD_TILAPIA_FAM10 - bool "Tilapia (Fam10)" diff --git a/src/mainboard/amd/tilapia_fam10/Makefile.inc b/src/mainboard/amd/tilapia_fam10/Makefile.inc deleted file mode 100644 index 91d4b39c32..0000000000 --- a/src/mainboard/amd/tilapia_fam10/Makefile.inc +++ /dev/null @@ -1,16 +0,0 @@ -# -# This file is part of the coreboot project. -# -# This program is free software; you can redistribute it and/or modify -# it under the terms of the GNU General Public License as published by -# the Free Software Foundation; version 2 of the License. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# - -romstage-y += resourcemap.c - -ramstage-y += get_bus_conf.c diff --git a/src/mainboard/amd/tilapia_fam10/acpi/cpstate.asl b/src/mainboard/amd/tilapia_fam10/acpi/cpstate.asl deleted file mode 100644 index acaa5bae32..0000000000 --- a/src/mainboard/amd/tilapia_fam10/acpi/cpstate.asl +++ /dev/null @@ -1,80 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2010 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -/* This file defines the processor and performance state capability - * for each core in the system. It is included into the DSDT for each - * core. It assumes that each core of the system has the same performance - * characteristics. -*/ -/* -#include -DefinitionBlock ("DSDT.AML", "DSDT", 0x01, OEM_ID, ACPI_TABLE_CREATOR, 0x00010001) - { - Scope (\_PR) { - Device (CPU0) { - Name (_HID, "ACPI0007") - Name (_UID, 0) - #include "cpstate.asl" - } - Device (CPU1) { - Name (_HID, "ACPI0007") - Name (_UID, 1) - #include "cpstate.asl" - } - Device (CPU2) { - Name (_HID, "ACPI0007") - Name (_UID, 2) - #include "cpstate.asl" - } - Device (CPU3) { - Name (_HID, "ACPI0007") - Name (_UID, 3) - #include "cpstate.asl" - } - } -*/ - /* P-state support: The maximum number of P-states supported by the */ - /* CPUs we'll use is 6. */ - /* Get from AMI BIOS. */ - Name(_PSS, Package(){ - Package () - { - 0x00000AF0, - 0x0000BF81, - 0x00000002, - 0x00000002, - 0x00000000, - 0x00000000 - }, - - Package () - { - 0x00000578, - 0x000076F2, - 0x00000002, - 0x00000002, - 0x00000001, - 0x00000001 - } - }) - - Name(_PCT, Package(){ - ResourceTemplate(){Register(FFixedHW, 0, 0, 0)}, - ResourceTemplate(){Register(FFixedHW, 0, 0, 0)} - }) - - Method(_PPC, 0){ - Return(0) - } diff --git a/src/mainboard/amd/tilapia_fam10/acpi/ide.asl b/src/mainboard/amd/tilapia_fam10/acpi/ide.asl deleted file mode 100644 index 5c155cf301..0000000000 --- a/src/mainboard/amd/tilapia_fam10/acpi/ide.asl +++ /dev/null @@ -1,240 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2010 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -/* -Scope (_SB) { - Device(PCI0) { - Device(IDEC) { - Name(_ADR, 0x00140001) - #include "ide.asl" - } - } -} -*/ - -/* Some timing tables */ -Name(UDTT, Package(){ /* Udma timing table */ - 120, 90, 60, 45, 30, 20, 15, 0 /* UDMA modes 0 -> 6 */ -}) - -Name(MDTT, Package(){ /* MWDma timing table */ - 480, 150, 120, 0 /* Legacy DMA modes 0 -> 2 */ -}) - -Name(POTT, Package(){ /* Pio timing table */ - 600, 390, 270, 180, 120, 0 /* PIO modes 0 -> 4 */ -}) - -/* Some timing register value tables */ -Name(MDRT, Package(){ /* MWDma timing register table */ - 0x77, 0x21, 0x20, 0xFF /* Legacy DMA modes 0 -> 2 */ -}) - -Name(PORT, Package(){ - 0x99, 0x47, 0x34, 0x22, 0x20, 0x99 /* PIO modes 0 -> 4 */ -}) - -OperationRegion(ICRG, PCI_Config, 0x40, 0x20) /* ide control registers */ - Field(ICRG, AnyAcc, NoLock, Preserve) -{ - PPTS, 8, /* Primary PIO Slave Timing */ - PPTM, 8, /* Primary PIO Master Timing */ - OFFSET(0x04), PMTS, 8, /* Primary MWDMA Slave Timing */ - PMTM, 8, /* Primary MWDMA Master Timing */ - OFFSET(0x08), PPCR, 8, /* Primary PIO Control */ - OFFSET(0x0A), PPMM, 4, /* Primary PIO master Mode */ - PPSM, 4, /* Primary PIO slave Mode */ - OFFSET(0x14), PDCR, 2, /* Primary UDMA Control */ - OFFSET(0x16), PDMM, 4, /* Primary UltraDMA Mode */ - PDSM, 4, /* Primary UltraDMA Mode */ -} - -Method(GTTM, 1) /* get total time*/ -{ - Store(And(Arg0, 0x0F), Local0) /* Recovery Width */ - Increment(Local0) - Store(ShiftRight(Arg0, 4), Local1) /* Command Width */ - Increment(Local1) - Return(Multiply(30, Add(Local0, Local1))) -} - -Device(PRID) -{ - Name (_ADR, Zero) - Method(_GTM, 0) - { - NAME(OTBF, Buffer(20) { /* out buffer */ - 0xFF, 0xFF, 0xFF, 0xFF, - 0xFF, 0xFF, 0xFF, 0xFF, - 0xFF, 0xFF, 0xFF, 0xFF, - 0xFF, 0xFF, 0xFF, 0xFF, 0x00, 0x00, 0x00, 0x00 - }) - - CreateDwordField(OTBF, 0, PSD0) /* PIO spd0 */ - CreateDwordField(OTBF, 4, DSD0) /* DMA spd0 */ - CreateDwordField(OTBF, 8, PSD1) /* PIO spd1 */ - CreateDwordField(OTBF, 12, DSD1) /* DMA spd1 */ - CreateDwordField(OTBF, 16, BFFG) /* buffer flags */ - - /* Just return if the channel is disabled */ - If(And(PPCR, 0x01)) { /* primary PIO control */ - Return(OTBF) - } - - /* Always tell them independent timing available and IOChannelReady used on both drives */ - Or(BFFG, 0x1A, BFFG) - - Store(GTTM(PPTM), PSD0) /* save total time of primary PIO master timming to PIO spd0 */ - Store(GTTM(PPTS), PSD1) /* save total time of primary PIO slave Timing to PIO spd1 */ - - If(And(PDCR, 0x01)) { /* It's under UDMA mode */ - Or(BFFG, 0x01, BFFG) - Store(DerefOf(Index(UDTT, PDMM)), DSD0) - } - Else { - Store(GTTM(PMTM), DSD0) /* Primary MWDMA Master Timing, DmaSpd0 */ - } - - If(And(PDCR, 0x02)) { /* It's under UDMA mode */ - Or(BFFG, 0x04, BFFG) - Store(DerefOf(Index(UDTT, PDSM)), DSD1) - } - Else { - Store(GTTM(PMTS), DSD1) /* Primary MWDMA Slave Timing, DmaSpd0 */ - } - - Return(OTBF) /* out buffer */ - } /* End Method(_GTM) */ - - Method(_STM, 3, NotSerialized) - { - NAME(INBF, Buffer(20) { /* in buffer */ - 0xFF, 0xFF, 0xFF, 0xFF, - 0xFF, 0xFF, 0xFF, 0xFF, - 0xFF, 0xFF, 0xFF, 0xFF, - 0xFF, 0xFF, 0xFF, 0xFF, 0x00, 0x00, 0x00, 0x00 - }) - - CreateDwordField(INBF, 0, PSD0) /* PIO spd0 */ - CreateDwordField(INBF, 4, DSD0) /* PIO spd0 */ - CreateDwordField(INBF, 8, PSD1) /* PIO spd1 */ - CreateDwordField(INBF, 12, DSD1) /* DMA spd1 */ - CreateDwordField(INBF, 16, BFFG) /*buffer flag */ - - Store(Match(POTT, MLE, PSD0, MTR, 0, 0), Local0) - Divide(Local0, 5, PPMM,) /* Primary PIO master Mode */ - Store(Match(POTT, MLE, PSD1, MTR, 0, 0), Local1) - Divide(Local1, 5, PPSM,) /* Primary PIO slave Mode */ - - Store(DerefOf(Index(PORT, Local0)), PPTM) /* Primary PIO Master Timing */ - Store(DerefOf(Index(PORT, Local1)), PPTS) /* Primary PIO Slave Timing */ - - If(And(BFFG, 0x01)) { /* Drive 0 is under UDMA mode */ - Store(Match(UDTT, MLE, DSD0, MTR, 0, 0), Local0) - Divide(Local0, 7, PDMM,) - Or(PDCR, 0x01, PDCR) - } - Else { - If(LNotEqual(DSD0, 0xFFFFFFFF)) { - Store(Match(MDTT, MLE, DSD0, MTR, 0, 0), Local0) - Store(DerefOf(Index(MDRT, Local0)), PMTM) - } - } - - If(And(BFFG, 0x04)) { /* Drive 1 is under UDMA mode */ - Store(Match(UDTT, MLE, DSD1, MTR, 0, 0), Local0) - Divide(Local0, 7, PDSM,) - Or(PDCR, 0x02, PDCR) - } - Else { - If(LNotEqual(DSD1, 0xFFFFFFFF)) { - Store(Match(MDTT, MLE, DSD1, MTR, 0, 0), Local0) - Store(DerefOf(Index(MDRT, Local0)), PMTS) - } - } - /* Return(INBF) */ - } /*End Method(_STM) */ - Device(MST) - { - Name(_ADR, 0) - Method(_GTF) { - Name(CMBF, Buffer(21) { - 0x03, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xEF, - 0x03, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xEF, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xF5 - }) - CreateByteField(CMBF, 1, POMD) - CreateByteField(CMBF, 8, DMMD) - CreateByteField(CMBF, 5, CMDA) - CreateByteField(CMBF, 12, CMDB) - CreateByteField(CMBF, 19, CMDC) - - Store(0xA0, CMDA) - Store(0xA0, CMDB) - Store(0xA0, CMDC) - - Or(PPMM, 0x08, POMD) - - If(And(PDCR, 0x01)) { - Or(PDMM, 0x40, DMMD) - } - Else { - Store(Match - (MDTT, MLE, GTTM(PMTM), - MTR, 0, 0), Local0) - If(LLess(Local0, 3)) { - Or(0x20, Local0, DMMD) - } - } - Return(CMBF) - } - } /* End Device(MST) */ - - Device(SLAV) - { - Name(_ADR, 1) - Method(_GTF) { - Name(CMBF, Buffer(21) { - 0x03, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xEF, - 0x03, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xEF, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xF5 - }) - CreateByteField(CMBF, 1, POMD) - CreateByteField(CMBF, 8, DMMD) - CreateByteField(CMBF, 5, CMDA) - CreateByteField(CMBF, 12, CMDB) - CreateByteField(CMBF, 19, CMDC) - - Store(0xB0, CMDA) - Store(0xB0, CMDB) - Store(0xB0, CMDC) - - Or(PPSM, 0x08, POMD) - - If(And(PDCR, 0x02)) { - Or(PDSM, 0x40, DMMD) - } - Else { - Store(Match - (MDTT, MLE, GTTM(PMTS), - MTR, 0, 0), Local0) - If(LLess(Local0, 3)) { - Or(0x20, Local0, DMMD) - } - } - Return(CMBF) - } - } /* End Device(SLAV) */ -} diff --git a/src/mainboard/amd/tilapia_fam10/acpi/routing.asl b/src/mainboard/amd/tilapia_fam10/acpi/routing.asl deleted file mode 100644 index 072aa2117f..0000000000 --- a/src/mainboard/amd/tilapia_fam10/acpi/routing.asl +++ /dev/null @@ -1,297 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2010 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -/* -#include -DefinitionBlock ("DSDT.AML", "DSDT", 0x01, OEM_ID, ACPI_TABLE_CREATOR, 0x00010001 - ) - { - #include "routing.asl" - } -*/ - -/* Routing is in System Bus scope */ -Scope(\_SB) { - Name(PR0, Package(){ - /* NB devices */ - /* Bus 0, Dev 0 - RS780 Host Controller */ - /* Bus 0, Dev 1 - PCI Bridge for Internal Graphics */ - /* Bus 0, Dev 2 - PCIe Bridge for x8 PCIe Slot (GFX0) */ - Package(){0x0002FFFF, 0, INTC, 0 }, - Package(){0x0002FFFF, 1, INTD, 0 }, - Package(){0x0002FFFF, 2, INTA, 0 }, - Package(){0x0002FFFF, 3, INTB, 0 }, - /* Bus 0, Dev 3 - PCIe graphics port 1 bridge */ - /* Bus 0, Dev 4 - PCIe Bridge for Express Card Slot */ - Package(){0x0004FFFF, 0, INTA, 0 }, - Package(){0x0004FFFF, 1, INTB, 0 }, - Package(){0x0004FFFF, 2, INTC, 0 }, - Package(){0x0004FFFF, 3, INTD, 0 }, - /* Bus 0, Dev 5 - General purpose PCIe bridge 5 */ - /* Package(){0x0005FFFF, 0, INTB, 0 }, */ - /* Package(){0x0005FFFF, 1, INTC, 0 }, */ - /* Package(){0x0005FFFF, 2, INTD, 0 }, */ - /* Package(){0x0005FFFF, 3, INTA, 0 }, */ - /* Bus 0, Dev 6 - PCIe Bridge for Ethernet Chip */ - Package(){0x0006FFFF, 0, INTC, 0 }, - Package(){0x0006FFFF, 1, INTD, 0 }, - Package(){0x0006FFFF, 2, INTA, 0 }, - Package(){0x0006FFFF, 3, INTB, 0 }, - /* Bus 0, Dev 7 - PCIe Bridge for x1 PCIe Slot */ - Package(){0x0007FFFF, 0, INTD, 0 }, - Package(){0x0007FFFF, 1, INTA, 0 }, - Package(){0x0007FFFF, 2, INTB, 0 }, - Package(){0x0007FFFF, 3, INTC, 0 }, - /* Bus 0, Funct 8 - Southbridge port (normally hidden) */ - - /* SB devices */ - /* Bus 0, Dev 17 - SATA controller #2 */ - /* Bus 0, Dev 18 - SATA controller #1 */ - Package(){0x0011FFFF, 1, INTA, 0 }, - - /* Bus 0, Dev 19 - USB: OHCI, funct 0-4; EHCI, funct 5 */ - Package(){0x0012FFFF, 0, INTA, 0 }, - Package(){0x0012FFFF, 1, INTB, 0 }, - Package(){0x0013FFFF, 0, INTA, 0 }, - Package(){0x0013FFFF, 1, INTB, 0 }, - Package(){0x0014FFFF, 2, INTA, 0 }, - - /* Bus 0, Dev 20 - F0:SMBus/ACPI,F1:IDE;F2:HDAudio;F3:LPC;F4:PCIBridge;F5:AC97 Audio;F6:AC97 Modem */ - Package(){0x0014FFFF, 0, INTA, 0 }, - Package(){0x0014FFFF, 1, INTB, 0 }, - Package(){0x0014FFFF, 2, INTC, 0 }, - Package(){0x0014FFFF, 3, INTD, 0 }, - }) - - Name(APR0, Package(){ - /* NB devices in APIC mode */ - /* Bus 0, Dev 0 - RS780 Host Controller */ - - /* Bus 0, Dev 1 - PCI Bridge for Internal Graphics */ - /* Package(){0x0001FFFF, 0, 0, 18 }, */ - /* Package(){0x0001FFFF, 1, 0, 19 }, */ - - /* Bus 0, Dev 2 - PCIe Bridge for x8 PCIe Slot (GFX0) */ - Package(){0x0002FFFF, 0, 0, 18 }, - /* Package(){0x0002FFFF, 1, 0, 19 }, */ - /* Package(){0x0002FFFF, 2, 0, 16 }, */ - /* Package(){0x0002FFFF, 3, 0, 17 }, */ - - /* Bus 0, Dev 3 - PCIe graphics port 1 bridge */ - Package(){0x0003FFFF, 0, 0, 19 }, - - /* Bus 0, Dev 4 - PCIe Bridge for Express Card Slot */ - Package(){0x0004FFFF, 0, 0, 16 }, - /* Package(){0x0004FFFF, 1, 0, 17 }, */ - /* Package(){0x0004FFFF, 2, 0, 18 }, */ - /* Package(){0x0004FFFF, 3, 0, 19 }, */ - - /* Bus 0, Dev 5 - General purpose PCIe bridge 5 */ - /* Package(){0x0005FFFF, 0, 0, 17 }, */ - /* Package(){0x0005FFFF, 1, 0, 18 }, */ - /* Package(){0x0005FFFF, 2, 0, 19 }, */ - /* Package(){0x0005FFFF, 3, 0, 16 }, */ - - /* Bus 0, Dev 6 - General purpose PCIe bridge 6 */ - /* Package(){0x0006FFFF, 0, 0, 18 }, */ - /* Package(){0x0006FFFF, 1, 0, 19 }, */ - /* Package(){0x0006FFFF, 2, 0, 16 }, */ - /* Package(){0x0006FFFF, 3, 0, 17 }, */ - - /* Bus 0, Dev 7 - PCIe Bridge for network card */ - /* Package(){0x0007FFFF, 0, 0, 19 }, */ - /* Package(){0x0007FFFF, 1, 0, 16 }, */ - /* Package(){0x0007FFFF, 2, 0, 17 }, */ - /* Package(){0x0007FFFF, 3, 0, 18 }, */ - - /* Bus 0, Dev 9 - PCIe Bridge for network card */ - Package(){0x0009FFFF, 0, 0, 17 }, - /* Package(){0x0009FFFF, 1, 0, 16 }, */ - /* Package(){0x0009FFFF, 2, 0, 17 }, */ - /* Package(){0x0009FFFF, 3, 0, 18 }, */ - /* Bus 0, Dev A - PCIe Bridge for network card */ - Package(){0x000AFFFF, 0, 0, 18 }, - /* Package(){0x000AFFFF, 1, 0, 16 }, */ - /* Package(){0x000AFFFF, 2, 0, 17 }, */ - /* Package(){0x000AFFFF, 3, 0, 18 }, */ - /* Bus 0, Funct 8 - Southbridge port (normally hidden) */ - - /* SB devices in APIC mode */ - /* Bus 0, Dev 17 - SATA controller #2 */ - /* Bus 0, Dev 18 - SATA controller #1 */ - Package(){0x0011FFFF, 0, 0, 22 }, - - /* Bus 0, Dev 19 - USB: OHCI, funct 0-4; EHCI, funct 5 */ - Package(){0x0012FFFF, 0, 0, 16 }, - Package(){0x0012FFFF, 1, 0, 17 }, - Package(){0x0013FFFF, 0, 0, 18 }, - Package(){0x0013FFFF, 1, 0, 19 }, - Package(){0x0014FFFF, 0, 0, 16 }, - /* Package(){0x00130004, 2, 0, 18 }, */ - /* Package(){0x00130005, 3, 0, 19 }, */ - - /* Bus 0, Dev 20 - F0:SMBus/ACPI, F1:IDE; F2:HDAudio; F3:LPC; F4:PCIBridge; F5:AC97 Audio; F6:AC97 Modem */ - Package(){0x0014FFFF, 0, 0, 16 }, - Package(){0x0014FFFF, 1, 0, 17 }, - Package(){0x0014FFFF, 2, 0, 18 }, - Package(){0x0014FFFF, 3, 0, 19 }, - /* Package(){0x00140004, 2, 0, 18 }, */ - /* Package(){0x00140004, 3, 0, 19 }, */ - /* Package(){0x00140005, 1, 0, 17 }, */ - /* Package(){0x00140006, 1, 0, 17 }, */ - }) - - Name(PR1, Package(){ - /* Internal graphics - RS780 VGA, Bus1, Dev5 */ - Package(){0x0005FFFF, 0, INTA, 0 }, - Package(){0x0005FFFF, 1, INTB, 0 }, - Package(){0x0005FFFF, 2, INTC, 0 }, - Package(){0x0005FFFF, 3, INTD, 0 }, - }) - - Name(APR1, Package(){ - /* Internal graphics - RS780 VGA, Bus1, Dev5 */ - Package(){0x0005FFFF, 0, 0, 18 }, - Package(){0x0005FFFF, 1, 0, 19 }, - /* Package(){0x0005FFFF, 2, 0, 20 }, */ - /* Package(){0x0005FFFF, 3, 0, 17 }, */ - }) - - Name(PS2, Package(){ - /* The external GFX - Hooked to PCIe slot 2 */ - Package(){0x0000FFFF, 0, INTC, 0 }, - Package(){0x0000FFFF, 1, INTD, 0 }, - Package(){0x0000FFFF, 2, INTA, 0 }, - Package(){0x0000FFFF, 3, INTB, 0 }, - }) - - Name(APS2, Package(){ - /* The external GFX - Hooked to PCIe slot 2 */ - Package(){0x0000FFFF, 0, 0, 18 }, - Package(){0x0000FFFF, 1, 0, 19 }, - Package(){0x0000FFFF, 2, 0, 16 }, - Package(){0x0000FFFF, 3, 0, 17 }, - }) - - Name(PS4, Package(){ - /* PCIe slot - Hooked to PCIe slot 4 */ - Package(){0x0000FFFF, 0, INTA, 0 }, - Package(){0x0000FFFF, 1, INTB, 0 }, - Package(){0x0000FFFF, 2, INTC, 0 }, - Package(){0x0000FFFF, 3, INTD, 0 }, - }) - - Name(APS4, Package(){ - /* PCIe slot - Hooked to PCIe slot 4 */ - Package(){0x0000FFFF, 0, 0, 16 }, - Package(){0x0000FFFF, 1, 0, 17 }, - Package(){0x0000FFFF, 2, 0, 18 }, - Package(){0x0000FFFF, 3, 0, 19 }, - }) - - Name(PS5, Package(){ - /* PCIe slot - Hooked to PCIe slot 5 */ - Package(){0x0000FFFF, 0, INTB, 0 }, - Package(){0x0000FFFF, 1, INTC, 0 }, - Package(){0x0000FFFF, 2, INTD, 0 }, - Package(){0x0000FFFF, 3, INTA, 0 }, - }) - - Name(APS5, Package(){ - /* PCIe slot - Hooked to PCIe slot 5 */ - Package(){0x0000FFFF, 0, 0, 17 }, - Package(){0x0000FFFF, 1, 0, 18 }, - Package(){0x0000FFFF, 2, 0, 19 }, - Package(){0x0000FFFF, 3, 0, 16 }, - }) - - Name(PS6, Package(){ - /* PCIe slot - Hooked to PCIe slot 6 */ - Package(){0x0000FFFF, 0, INTC, 0 }, - Package(){0x0000FFFF, 1, INTD, 0 }, - Package(){0x0000FFFF, 2, INTA, 0 }, - Package(){0x0000FFFF, 3, INTB, 0 }, - }) - - Name(APS6, Package(){ - /* PCIe slot - Hooked to PCIe slot 6 */ - Package(){0x0000FFFF, 0, 0, 18 }, - Package(){0x0000FFFF, 1, 0, 19 }, - Package(){0x0000FFFF, 2, 0, 16 }, - Package(){0x0000FFFF, 3, 0, 17 }, - }) - - Name(PS7, Package(){ - /* The onboard Ethernet chip - Hooked to PCIe slot 7 */ - Package(){0x0000FFFF, 0, INTD, 0 }, - Package(){0x0000FFFF, 1, INTA, 0 }, - Package(){0x0000FFFF, 2, INTB, 0 }, - Package(){0x0000FFFF, 3, INTC, 0 }, - }) - - Name(APS7, Package(){ - /* The onboard Ethernet chip - Hooked to PCIe slot 7 */ - Package(){0x0000FFFF, 0, 0, 19 }, - Package(){0x0000FFFF, 1, 0, 16 }, - Package(){0x0000FFFF, 2, 0, 17 }, - Package(){0x0000FFFF, 3, 0, 18 }, - }) - Name(PS9, Package(){ - /* PCIe slot - Hooked to PCIe slot 9 */ - Package(){0x0000FFFF, 0, INTD, 0 }, - Package(){0x0000FFFF, 1, INTA, 0 }, - Package(){0x0000FFFF, 2, INTB, 0 }, - Package(){0x0000FFFF, 3, INTC, 0 }, - }) - - Name(APS9, Package(){ - /* PCIe slot - Hooked to PCIe slot 9 */ - Package(){0x0000FFFF, 0, 0, 17 }, - Package(){0x0000FFFF, 1, 0, 18 }, - Package(){0x0000FFFF, 2, 0, 19 }, - Package(){0x0000FFFF, 3, 0, 16 }, - }) - Name(PSa, Package(){ - /* PCIe slot - Hooked to PCIe slot 10 */ - Package(){0x0000FFFF, 0, INTD, 0 }, - Package(){0x0000FFFF, 1, INTA, 0 }, - Package(){0x0000FFFF, 2, INTB, 0 }, - Package(){0x0000FFFF, 3, INTC, 0 }, - }) - - Name(APSa, Package(){ - /* PCIe slot - Hooked to PCIe slot 10 */ - Package(){0x0000FFFF, 0, 0, 18 }, - Package(){0x0000FFFF, 1, 0, 19 }, - Package(){0x0000FFFF, 2, 0, 16 }, - Package(){0x0000FFFF, 3, 0, 17 }, - }) - - Name(PCIB, Package(){ - /* PCI slots: slot 0, slot 1, slot 2 behind Dev14, Fun4. */ - Package(){0x0005FFFF, 0, 0, 0x14 }, - Package(){0x0005FFFF, 1, 0, 0x15 }, - Package(){0x0005FFFF, 2, 0, 0x16 }, - Package(){0x0005FFFF, 3, 0, 0x17 }, - Package(){0x0006FFFF, 0, 0, 0x15 }, - Package(){0x0006FFFF, 1, 0, 0x16 }, - Package(){0x0006FFFF, 2, 0, 0x17 }, - Package(){0x0006FFFF, 3, 0, 0x14 }, - Package(){0x0007FFFF, 0, 0, 0x16 }, - Package(){0x0007FFFF, 1, 0, 0x17 }, - Package(){0x0007FFFF, 2, 0, 0x14 }, - Package(){0x0007FFFF, 3, 0, 0x15 }, - }) -} diff --git a/src/mainboard/amd/tilapia_fam10/acpi/sata.asl b/src/mainboard/amd/tilapia_fam10/acpi/sata.asl deleted file mode 100644 index cb9b221ba3..0000000000 --- a/src/mainboard/amd/tilapia_fam10/acpi/sata.asl +++ /dev/null @@ -1,145 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2010 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -/* simple name description */ - -/* -Scope (_SB) { - Device(PCI0) { - Device(SATA) { - Name(_ADR, 0x00110000) - #include "sata.asl" - } - } -} -*/ - -Name(STTM, Buffer(20) { - 0x78, 0x00, 0x00, 0x00, 0x0f, 0x00, 0x00, 0x00, - 0x78, 0x00, 0x00, 0x00, 0x0f, 0x00, 0x00, 0x00, - 0x1f, 0x00, 0x00, 0x00 -}) - -/* Start by clearing the PhyRdyChg bits */ -Method(_INI) { - \_GPE._L1F() -} - -Device(PMRY) -{ - Name(_ADR, 0) - Method(_GTM, 0x0, NotSerialized) { - Return(STTM) - } - Method(_STM, 0x3, NotSerialized) {} - - Device(PMST) { - Name(_ADR, 0) - Method(_STA,0) { - if (LGreater(P0IS,0)) { - return (0x0F) /* sata is visible */ - } - else { - return (0x00) /* sata is missing */ - } - } - }/* end of PMST */ - - Device(PSLA) - { - Name(_ADR, 1) - Method(_STA,0) { - if (LGreater(P1IS,0)) { - return (0x0F) /* sata is visible */ - } - else { - return (0x00) /* sata is missing */ - } - } - } /* end of PSLA */ -} /* end of PMRY */ - - -Device(SEDY) -{ - Name(_ADR, 1) /* IDE Scondary Channel */ - Method(_GTM, 0x0, NotSerialized) { - Return(STTM) - } - Method(_STM, 0x3, NotSerialized) {} - - Device(SMST) - { - Name(_ADR, 0) - Method(_STA,0) { - if (LGreater(P2IS,0)) { - return (0x0F) /* sata is visible */ - } - else { - return (0x00) /* sata is missing */ - } - } - } /* end of SMST */ - - Device(SSLA) - { - Name(_ADR, 1) - Method(_STA,0) { - if (LGreater(P3IS,0)) { - return (0x0F) /* sata is visible */ - } - else { - return (0x00) /* sata is missing */ - } - } - } /* end of SSLA */ -} /* end of SEDY */ - -/* SATA Hot Plug Support */ -Scope(\_GPE) { - Method(_L1F,0x0,NotSerialized) { - if (\_SB.P0PR) { - if (LGreater(\_SB.P0IS,0)) { - sleep(32) - } - Notify(\_SB.PCI0.STCR.PMRY.PMST, 0x01) /* NOTIFY_DEVICE_CHECK */ - store(one, \_SB.P0PR) - } - - if (\_SB.P1PR) { - if (LGreater(\_SB.P1IS,0)) { - sleep(32) - } - Notify(\_SB.PCI0.STCR.PMRY.PSLA, 0x01) /* NOTIFY_DEVICE_CHECK */ - store(one, \_SB.P1PR) - } - - if (\_SB.P2PR) { - if (LGreater(\_SB.P2IS,0)) { - sleep(32) - } - Notify(\_SB.PCI0.STCR.SEDY.SMST, 0x01) /* NOTIFY_DEVICE_CHECK */ - store(one, \_SB.P2PR) - } - - if (\_SB.P3PR) { - if (LGreater(\_SB.P3IS,0)) { - sleep(32) - } - Notify(\_SB.PCI0.STCR.SEDY.SSLA, 0x01) /* NOTIFY_DEVICE_CHECK */ - store(one, \_SB.P3PR) - } - } -} diff --git a/src/mainboard/amd/tilapia_fam10/acpi/usb.asl b/src/mainboard/amd/tilapia_fam10/acpi/usb.asl deleted file mode 100644 index a3ccb97ff9..0000000000 --- a/src/mainboard/amd/tilapia_fam10/acpi/usb.asl +++ /dev/null @@ -1,158 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2010 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -/* simple name description */ -/* -#include -DefinitionBlock ("DSDT.AML", "DSDT", 0x01, OEM_ID, ACPI_TABLE_CREATOR, 0x00010001 - ) - { - #include "usb.asl" - } -*/ -Method(UCOC, 0) { - Sleep(20) - Store(0x13,CMTI) - Store(0,GPSL) -} - -/* USB Port 0 overcurrent uses Gpm 0 */ -If(LLessEqual(UOM0,9)) { - Scope (\_GPE) { - Method (_L13) { - UCOC() - if(LEqual(GPB0,PLC0)) { - Not(PLC0,PLC0) - Store(PLC0, \_SB.PT0D) - } - } - } -} - -/* USB Port 1 overcurrent uses Gpm 1 */ -If (LLessEqual(UOM1,9)) { - Scope (\_GPE) { - Method (_L14) { - UCOC() - if (LEqual(GPB1,PLC1)) { - Not(PLC1,PLC1) - Store(PLC1, \_SB.PT1D) - } - } - } -} - -/* USB Port 2 overcurrent uses Gpm 2 */ -If (LLessEqual(UOM2,9)) { - Scope (\_GPE) { - Method (_L15) { - UCOC() - if (LEqual(GPB2,PLC2)) { - Not(PLC2,PLC2) - Store(PLC2, \_SB.PT2D) - } - } - } -} - -/* USB Port 3 overcurrent uses Gpm 3 */ -If (LLessEqual(UOM3,9)) { - Scope (\_GPE) { - Method (_L16) { - UCOC() - if (LEqual(GPB3,PLC3)) { - Not(PLC3,PLC3) - Store(PLC3, \_SB.PT3D) - } - } - } -} - -/* USB Port 4 overcurrent uses Gpm 4 */ -If (LLessEqual(UOM4,9)) { - Scope (\_GPE) { - Method (_L19) { - UCOC() - if (LEqual(GPB4,PLC4)) { - Not(PLC4,PLC4) - Store(PLC4, \_SB.PT4D) - } - } - } -} - -/* USB Port 5 overcurrent uses Gpm 5 */ -If (LLessEqual(UOM5,9)) { - Scope (\_GPE) { - Method (_L1A) { - UCOC() - if (LEqual(GPB5,PLC5)) { - Not(PLC5,PLC5) - Store(PLC5, \_SB.PT5D) - } - } - } -} - -/* USB Port 6 overcurrent uses Gpm 6 */ -If (LLessEqual(UOM6,9)) { - Scope (\_GPE) { - /* Method (_L1C) { */ - Method (_L06) { - UCOC() - if (LEqual(GPB6,PLC6)) { - Not(PLC6,PLC6) - Store(PLC6, \_SB.PT6D) - } - } - } -} - -/* USB Port 7 overcurrent uses Gpm 7 */ -If (LLessEqual(UOM7,9)) { - Scope (\_GPE) { - /* Method (_L1D) { */ - Method (_L07) { - UCOC() - if (LEqual(GPB7,PLC7)) { - Not(PLC7,PLC7) - Store(PLC7, \_SB.PT7D) - } - } - } -} - -/* USB Port 8 overcurrent uses Gpm 8 */ -If (LLessEqual(UOM8,9)) { - Scope (\_GPE) { - Method (_L17) { - if (LEqual(G8IS,PLC8)) { - Not(PLC8,PLC8) - Store(PLC8, \_SB.PT8D) - } - } - } -} - -/* USB Port 9 overcurrent uses Gpm 9 */ -If (LLessEqual(UOM9,9)) { - Scope (\_GPE) { - Method (_L0E) { - if (LEqual(G9IS,0)) { - Store(1,\_SB.PT9D) - } - } - } -} diff --git a/src/mainboard/amd/tilapia_fam10/acpi_tables.c b/src/mainboard/amd/tilapia_fam10/acpi_tables.c deleted file mode 100644 index 967343da67..0000000000 --- a/src/mainboard/amd/tilapia_fam10/acpi_tables.c +++ /dev/null @@ -1,44 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2010 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include -#include - -unsigned long acpi_fill_madt(unsigned long current) -{ - /* create all subtables for processors */ - current = acpi_create_madt_lapics(current); - - /* Write SB700 IOAPIC, only one */ - current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, 2, - IO_APIC_ADDR, 0); - - current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) - current, 0, 0, 2, 0); - current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) - current, 0, 9, 9, 0xF); - /* 0: mean bus 0--->ISA */ - /* 0: PIC 0 */ - /* 2: APIC 2 */ - /* 5 mean: 0101 --> Edge-triggered, Active high */ - - /* create all subtables for processors */ - /* current = acpi_create_madt_lapic_nmis(current, 5, 1); */ - /* 1: LINT1 connect to NMI */ - - return current; -} diff --git a/src/mainboard/amd/tilapia_fam10/board_info.txt b/src/mainboard/amd/tilapia_fam10/board_info.txt deleted file mode 100644 index b351b8e696..0000000000 --- a/src/mainboard/amd/tilapia_fam10/board_info.txt +++ /dev/null @@ -1 +0,0 @@ -Category: eval diff --git a/src/mainboard/amd/tilapia_fam10/cmos.layout b/src/mainboard/amd/tilapia_fam10/cmos.layout deleted file mode 100644 index 6c3d3f6c9e..0000000000 --- a/src/mainboard/amd/tilapia_fam10/cmos.layout +++ /dev/null @@ -1,52 +0,0 @@ -entries - -0 384 r 0 reserved_memory -384 1 e 4 boot_option -388 4 h 0 reboot_counter -#392 3 r 0 unused -395 1 e 1 hw_scrubber -396 1 e 1 interleave_chip_selects -397 2 e 8 max_mem_clock -399 1 e 2 multi_core -400 1 e 1 power_on_after_fail -412 4 e 6 debug_level -440 4 e 9 slow_cpu -444 1 e 1 nmi -445 1 e 1 gart -456 1 e 1 ECC_memory -728 256 h 0 user_data -984 16 h 0 check_sum -# Reserve the extended AMD configuration registers -1000 24 r 0 amd_reserved - - - -enumerations - -#ID value text -1 0 Disable -1 1 Enable -2 0 Enable -2 1 Disable -4 0 Fallback -4 1 Normal -6 5 Notice -6 6 Info -6 7 Debug -6 8 Spew -8 0 400Mhz -8 1 333Mhz -8 2 266Mhz -8 3 200Mhz -9 0 off -9 1 87.5% -9 2 75.0% -9 3 62.5% -9 4 50.0% -9 5 37.5% -9 6 25.0% -9 7 12.5% - -checksums - -checksum 392 983 984 diff --git a/src/mainboard/amd/tilapia_fam10/devicetree.cb b/src/mainboard/amd/tilapia_fam10/devicetree.cb deleted file mode 100644 index 06e33f728d..0000000000 --- a/src/mainboard/amd/tilapia_fam10/devicetree.cb +++ /dev/null @@ -1,130 +0,0 @@ -# sample config for amd/tilapia_fam10 -chip northbridge/amd/amdfam10/root_complex - device cpu_cluster 0 on - chip cpu/amd/socket_AM3 #L1 and DDR3 - device lapic 0 on end - end - end - device domain 0 on - subsystemid 0x1022 0x3060 inherit - chip northbridge/amd/amdfam10 - device pci 18.0 on # northbridge - chip southbridge/amd/rs780 - device pci 0.0 on end # HT 0x9600 - device pci 1.0 on end # Internal Graphics P2P bridge 0x9602 - device pci 2.0 on end # PCIE P2P bridge (external graphics) 0x9603 - device pci 3.0 on end # PCIE P2P bridge 0x960b - device pci 4.0 on end # PCIE P2P bridge 0x9604 - device pci 5.0 off end # PCIE P2P bridge 0x9605 - device pci 6.0 off end # PCIE P2P bridge 0x9606 - device pci 7.0 off end # PCIE P2P bridge 0x9607 - device pci 8.0 off end # NB/SB Link P2P bridge - device pci 9.0 on end # - device pci a.0 on end # - register "gppsb_configuration" = "1" # Configuration B - register "gpp_configuration" = "3" # Configuration D default - register "port_enable" = "0x6fc" - register "gfx_dev2_dev3" = "1" - register "gfx_dual_slot" = "2" - - register "gfx_lane_reversal" = "0" - register "gfx_tmds" = "0" - register "gfx_compliance" = "0" - register "gfx_reconfiguration" = "1" - register "gfx_link_width" = "0" - end - chip southbridge/amd/sb700 # it is under NB/SB Link, but on the same pri bus - device pci 11.0 on end # SATA - device pci 12.0 on end # USB - device pci 12.1 on end # USB - device pci 12.2 on end # USB - device pci 13.0 on end # USB - device pci 13.1 on end # USB - device pci 13.2 on end # USB - device pci 14.0 on # SM - chip drivers/generic/generic #dimm 0-0-0 - device i2c 50 on end - end - chip drivers/generic/generic #dimm 0-0-1 - device i2c 51 on end - end - chip drivers/generic/generic #dimm 0-1-0 - device i2c 52 on end - end - chip drivers/generic/generic #dimm 0-1-1 - device i2c 53 on end - end - end # SM - device pci 14.1 on end # IDE 0x439c - device pci 14.2 on end # HDA 0x4383 - device pci 14.3 on # LPC 0x439d - chip superio/ite/it8718f - device pnp 2e.0 off # Floppy - io 0x60 = 0x3f0 - irq 0x70 = 6 - drq 0x74 = 2 - end - device pnp 2e.1 on # Com1 - io 0x60 = 0x3f8 - irq 0x70 = 4 - end - device pnp 2e.2 off # Com2 - io 0x60 = 0x2f8 - irq 0x70 = 3 - end - device pnp 2e.3 off # Parallel Port - io 0x60 = 0x378 - irq 0x70 = 7 - end - device pnp 2e.4 off end # EC - device pnp 2e.5 on # Keyboard - io 0x60 = 0x60 - io 0x62 = 0x64 - irq 0x70 = 1 - end - device pnp 2e.6 on # Mouse - irq 0x70 = 12 - end - device pnp 2e.7 off # GPIO, must be closed for unresolved reason. - end - device pnp 2e.8 off # MIDI - io 0x60 = 0x300 - irq 0x70 = 9 - end - device pnp 2e.9 off # GAME - io 0x60 = 0x220 - end - device pnp 2e.a off end # CIR - end #superio/ite/it8718f - end #LPC - device pci 14.4 on end # PCI 0x4384 - device pci 14.5 on end # USB 2 - register "boot_switch_sata_ide" = "0" # 0: boot from SATA. 1: IDE - end #southbridge/amd/sb700 - end # device pci 18.0 - - device pci 18.0 on end - device pci 18.0 on end - device pci 18.1 on end - device pci 18.2 on end - device pci 18.3 on end - device pci 18.4 on end -# device pci 00.5 on end - end - end #domain - #for node 32 to node 63 -# device domain 0 on -# chip northbridge/amd/amdfam10 -# device pci 00.0 on end# northbridge -# device pci 00.0 on end -# device pci 00.0 on end -# device pci 00.0 on end -# device pci 00.1 on end -# device pci 00.2 on end -# device pci 00.3 on end -# device pci 00.4 on end -# device pci 00.5 on end -# end -# end #domain - -end diff --git a/src/mainboard/amd/tilapia_fam10/dsdt.asl b/src/mainboard/amd/tilapia_fam10/dsdt.asl deleted file mode 100644 index f9f7e18abb..0000000000 --- a/src/mainboard/amd/tilapia_fam10/dsdt.asl +++ /dev/null @@ -1,1739 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2010 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -/* DefinitionBlock Statement */ -#include -DefinitionBlock ( - "DSDT.AML", /* Output filename */ - "DSDT", /* Signature */ - 0x02, /* DSDT Revision, needs to be 2 for 64bit */ - OEM_ID, - ACPI_TABLE_CREATOR, - 0x00010001 /* OEM Revision */ - ) -{ /* Start of ASL file */ - /* #include */ /* Include global debug methods if needed */ - - /* Data to be patched by the BIOS during POST */ - /* FIXME the patching is not done yet! */ - /* Memory related values */ - Name(LOMH, 0x0) /* Start of unused memory in C0000-E0000 range */ - Name(PBAD, 0x0) /* Address of BIOS area (If TOM2 != 0, Addr >> 16) */ - Name(PBLN, 0x0) /* Length of BIOS area */ - - Name(PCBA, 0xE0000000) /* Base address of PCIe config space */ - Name(HPBA, 0xFED00000) /* Base address of HPET table */ - - /* USB overcurrent mapping pins. */ - Name(UOM0, 0) - Name(UOM1, 2) - Name(UOM2, 0) - Name(UOM3, 7) - Name(UOM4, 2) - Name(UOM5, 2) - Name(UOM6, 6) - Name(UOM7, 2) - Name(UOM8, 6) - Name(UOM9, 6) - - /* Some global data */ - Name(OSVR, 3) /* Assume nothing. WinXp = 1, Vista = 2, Linux = 3, WinCE = 4 */ - Name(OSV, Ones) /* Assume nothing */ - Name(PMOD, One) /* Assume APIC */ - - /* - * Processor Object - * - */ - Scope (\_PR) { /* define processor scope */ - Device (CPU0) { - Name (_HID, "ACPI0007") - Name (_UID, 0) - #include "acpi/cpstate.asl" - } - Device (CPU1) { - Name (_HID, "ACPI0007") - Name (_UID, 1) - #include "acpi/cpstate.asl" - } - Device (CPU2) { - Name (_HID, "ACPI0007") - Name (_UID, 2) - #include "acpi/cpstate.asl" - } - Device (CPU3) { - Name (_HID, "ACPI0007") - Name (_UID, 3) - #include "acpi/cpstate.asl" - } - } /* End _PR scope */ - - /* PIC IRQ mapping registers, C00h-C01h */ - OperationRegion(PRQM, SystemIO, 0x00000C00, 0x00000002) - Field(PRQM, ByteAcc, NoLock, Preserve) { - PRQI, 0x00000008, - PRQD, 0x00000008, /* Offset: 1h */ - } - IndexField(PRQI, PRQD, ByteAcc, NoLock, Preserve) { - PINA, 0x00000008, /* Index 0 */ - PINB, 0x00000008, /* Index 1 */ - PINC, 0x00000008, /* Index 2 */ - PIND, 0x00000008, /* Index 3 */ - AINT, 0x00000008, /* Index 4 */ - SINT, 0x00000008, /* Index 5 */ - , 0x00000008, /* Index 6 */ - AAUD, 0x00000008, /* Index 7 */ - AMOD, 0x00000008, /* Index 8 */ - PINE, 0x00000008, /* Index 9 */ - PINF, 0x00000008, /* Index A */ - PING, 0x00000008, /* Index B */ - PINH, 0x00000008, /* Index C */ - } - - /* PCI Error control register */ - OperationRegion(PERC, SystemIO, 0x00000C14, 0x00000001) - Field(PERC, ByteAcc, NoLock, Preserve) { - SENS, 0x00000001, - PENS, 0x00000001, - SENE, 0x00000001, - PENE, 0x00000001, - } - - /* Client Management index/data registers */ - OperationRegion(CMT, SystemIO, 0x00000C50, 0x00000002) - Field(CMT, ByteAcc, NoLock, Preserve) { - CMTI, 8, - /* Client Management Data register */ - G64E, 1, - G64O, 1, - G32O, 2, - , 2, - GPSL, 2, - } - - /* GPM Port register */ - OperationRegion(GPT, SystemIO, 0x00000C52, 0x00000001) - Field(GPT, ByteAcc, NoLock, Preserve) { - GPB0,1, - GPB1,1, - GPB2,1, - GPB3,1, - GPB4,1, - GPB5,1, - GPB6,1, - GPB7,1, - } - - /* Flash ROM program enable register */ - OperationRegion(FRE, SystemIO, 0x00000C6F, 0x00000001) - Field(FRE, ByteAcc, NoLock, Preserve) { - , 0x00000006, - FLRE, 0x00000001, - } - - /* PM2 index/data registers */ - OperationRegion(PM2R, SystemIO, 0x00000CD0, 0x00000002) - Field(PM2R, ByteAcc, NoLock, Preserve) { - PM2I, 0x00000008, - PM2D, 0x00000008, - } - - /* Power Management I/O registers */ - OperationRegion(PIOR, SystemIO, 0x00000CD6, 0x00000002) - Field(PIOR, ByteAcc, NoLock, Preserve) { - PIOI, 0x00000008, - PIOD, 0x00000008, - } - IndexField (PIOI, PIOD, ByteAcc, NoLock, Preserve) { - Offset(0x00), /* MiscControl */ - , 1, - T1EE, 1, - T2EE, 1, - Offset(0x01), /* MiscStatus */ - , 1, - T1E, 1, - T2E, 1, - Offset(0x04), /* SmiWakeUpEventEnable3 */ - , 7, - SSEN, 1, - Offset(0x07), /* SmiWakeUpEventStatus3 */ - , 7, - CSSM, 1, - Offset(0x10), /* AcpiEnable */ - , 6, - PWDE, 1, - Offset(0x1C), /* ProgramIoEnable */ - , 3, - MKME, 1, - IO3E, 1, - IO2E, 1, - IO1E, 1, - IO0E, 1, - Offset(0x1D), /* IOMonitorStatus */ - , 3, - MKMS, 1, - IO3S, 1, - IO2S, 1, - IO1S, 1, - IO0S,1, - Offset(0x20), /* AcpiPmEvtBlk */ - APEB, 16, - Offset(0x36), /* GEvtLevelConfig */ - , 6, - ELC6, 1, - ELC7, 1, - Offset(0x37), /* GPMLevelConfig0 */ - , 3, - PLC0, 1, - PLC1, 1, - PLC2, 1, - PLC3, 1, - PLC8, 1, - Offset(0x38), /* GPMLevelConfig1 */ - , 1, - PLC4, 1, - PLC5, 1, - , 1, - PLC6, 1, - PLC7, 1, - Offset(0x3B), /* PMEStatus1 */ - GP0S, 1, - GM4S, 1, - GM5S, 1, - APS, 1, - GM6S, 1, - GM7S, 1, - GP2S, 1, - STSS, 1, - Offset(0x55), /* SoftPciRst */ - SPRE, 1, - , 1, - , 1, - PNAT, 1, - PWMK, 1, - PWNS, 1, - - /* Offset(0x61), */ /* Options_1 */ - /* ,7, */ - /* R617,1, */ - - Offset(0x65), /* UsbPMControl */ - , 4, - URRE, 1, - Offset(0x68), /* MiscEnable68 */ - , 3, - TMTE, 1, - , 1, - Offset(0x92), /* GEVENTIN */ - , 7, - E7IS, 1, - Offset(0x96), /* GPM98IN */ - G8IS, 1, - G9IS, 1, - Offset(0x9A), /* EnhanceControl */ - ,7, - HPDE, 1, - Offset(0xA8), /* PIO7654Enable */ - IO4E, 1, - IO5E, 1, - IO6E, 1, - IO7E, 1, - Offset(0xA9), /* PIO7654Status */ - IO4S, 1, - IO5S, 1, - IO6S, 1, - IO7S, 1, - } - - /* PM1 Event Block - * First word is PM1_Status, Second word is PM1_Enable - */ - OperationRegion(P1EB, SystemIO, APEB, 0x04) - Field(P1EB, ByteAcc, NoLock, Preserve) { - TMST, 1, - , 3, - BMST, 1, - GBST, 1, - Offset(0x01), - PBST, 1, - , 1, - RTST, 1, - , 3, - PWST, 1, - SPWS, 1, - Offset(0x02), - TMEN, 1, - , 4, - GBEN, 1, - Offset(0x03), - PBEN, 1, - , 1, - RTEN, 1, - , 3, - PWDA, 1, - } - - Scope(\_SB) { - /* PCIe Configuration Space for 16 busses */ - OperationRegion(PCFG, SystemMemory, PCBA, 0x01000000) /* Each bus consumes 1MB */ - Field(PCFG, ByteAcc, NoLock, Preserve) { - /* Byte offsets are computed using the following technique: - * ((bus number + 1) * ((device number * 8) * 4096)) + register offset - * The 8 comes from 8 functions per device, and 4096 bytes per function config space - */ - Offset(0x00088024), /* Byte offset to SATA register 24h - Bus 0, Device 17, Function 0 */ - STB5, 32, - Offset(0x00098042), /* Byte offset to OHCI0 register 42h - Bus 0, Device 19, Function 0 */ - PT0D, 1, - PT1D, 1, - PT2D, 1, - PT3D, 1, - PT4D, 1, - PT5D, 1, - PT6D, 1, - PT7D, 1, - PT8D, 1, - PT9D, 1, - Offset(0x000A0004), /* Byte offset to SMBUS register 4h - Bus 0, Device 20, Function 0 */ - SBIE, 1, - SBME, 1, - Offset(0x000A0008), /* Byte offset to SMBUS register 8h - Bus 0, Device 20, Function 0 */ - SBRI, 8, - Offset(0x000A0014), /* Byte offset to SMBUS register 14h - Bus 0, Device 20, Function 0 */ - SBB1, 32, - Offset(0x000A0078), /* Byte offset to SMBUS register 78h - Bus 0, Device 20, Function 0 */ - ,14, - P92E, 1, /* Port92 decode enable */ - } - - OperationRegion(SB5, SystemMemory, STB5, 0x1000) - Field(SB5, AnyAcc, NoLock, Preserve){ - /* Port 0 */ - Offset(0x120), /* Port 0 Task file status */ - P0ER, 1, - , 2, - P0DQ, 1, - , 3, - P0BY, 1, - Offset(0x128), /* Port 0 Serial ATA status */ - P0DD, 4, - , 4, - P0IS, 4, - Offset(0x12C), /* Port 0 Serial ATA control */ - P0DI, 4, - Offset(0x130), /* Port 0 Serial ATA error */ - , 16, - P0PR, 1, - - /* Port 1 */ - offset(0x1A0), /* Port 1 Task file status */ - P1ER, 1, - , 2, - P1DQ, 1, - , 3, - P1BY, 1, - Offset(0x1A8), /* Port 1 Serial ATA status */ - P1DD, 4, - , 4, - P1IS, 4, - Offset(0x1AC), /* Port 1 Serial ATA control */ - P1DI, 4, - Offset(0x1B0), /* Port 1 Serial ATA error */ - , 16, - P1PR, 1, - - /* Port 2 */ - Offset(0x220), /* Port 2 Task file status */ - P2ER, 1, - , 2, - P2DQ, 1, - , 3, - P2BY, 1, - Offset(0x228), /* Port 2 Serial ATA status */ - P2DD, 4, - , 4, - P2IS, 4, - Offset(0x22C), /* Port 2 Serial ATA control */ - P2DI, 4, - Offset(0x230), /* Port 2 Serial ATA error */ - , 16, - P2PR, 1, - - /* Port 3 */ - Offset(0x2A0), /* Port 3 Task file status */ - P3ER, 1, - , 2, - P3DQ, 1, - , 3, - P3BY, 1, - Offset(0x2A8), /* Port 3 Serial ATA status */ - P3DD, 4, - , 4, - P3IS, 4, - Offset(0x2AC), /* Port 3 Serial ATA control */ - P3DI, 4, - Offset(0x2B0), /* Port 3 Serial ATA error */ - , 16, - P3PR, 1, - } - } - - - #include "acpi/routing.asl" - - Scope(\_SB) { - - Method(OSFL, 0){ - - if(LNotEqual(OSVR, Ones)) {Return(OSVR)} /* OS version was already detected */ - - if(CondRefOf(\_OSI)) - { - Store(1, OSVR) /* Assume some form of XP */ - if (\_OSI("Windows 2006")) /* Vista */ - { - Store(2, OSVR) - } - } else { - If(WCMP(\_OS,"Linux")) { - Store(3, OSVR) /* Linux */ - } Else { - Store(4, OSVR) /* Gotta be WinCE */ - } - } - Return(OSVR) - } - - Method(_PIC, 0x01, NotSerialized) - { - If (Arg0) - { - \_SB.CIRQ() - } - Store(Arg0, PMOD) - } - Method(CIRQ, 0x00, NotSerialized){ - Store(0, PINA) - Store(0, PINB) - Store(0, PINC) - Store(0, PIND) - Store(0, PINE) - Store(0, PINF) - Store(0, PING) - Store(0, PINH) - } - - Name(IRQB, ResourceTemplate(){ - IRQ(Level,ActiveLow,Shared){15} - }) - - Name(IRQP, ResourceTemplate(){ - IRQ(Level,ActiveLow,Exclusive){3, 4, 5, 7, 10, 11, 12, 15} - }) - - Name(PITF, ResourceTemplate(){ - IRQ(Level,ActiveLow,Exclusive){9} - }) - - Device(INTA) { - Name(_HID, EISAID("PNP0C0F")) - Name(_UID, 1) - - Method(_STA, 0) { - if (PINA) { - Return(0x0B) /* sata is invisible */ - } else { - Return(0x09) /* sata is disabled */ - } - } /* End Method(_SB.INTA._STA) */ - - Method(_DIS ,0) { - /* DBGO("\\_SB\\LNKA\\_DIS\n") */ - Store(0, PINA) - } /* End Method(_SB.INTA._DIS) */ - - Method(_PRS ,0) { - /* DBGO("\\_SB\\LNKA\\_PRS\n") */ - Return(IRQP) - } /* Method(_SB.INTA._PRS) */ - - Method(_CRS ,0) { - /* DBGO("\\_SB\\LNKA\\_CRS\n") */ - CreateWordField(IRQB, 0x1, IRQN) - ShiftLeft(1, PINA, IRQN) - Return(IRQB) - } /* Method(_SB.INTA._CRS) */ - - Method(_SRS, 1) { - /* DBGO("\\_SB\\LNKA\\_CRS\n") */ - CreateWordField(ARG0, 1, IRQM) - - /* Use lowest available IRQ */ - FindSetRightBit(IRQM, Local0) - if (Local0) { - Decrement(Local0) - } - Store(Local0, PINA) - } /* End Method(_SB.INTA._SRS) */ - } /* End Device(INTA) */ - - Device(INTB) { - Name(_HID, EISAID("PNP0C0F")) - Name(_UID, 2) - - Method(_STA, 0) { - if (PINB) { - Return(0x0B) /* sata is invisible */ - } else { - Return(0x09) /* sata is disabled */ - } - } /* End Method(_SB.INTB._STA) */ - - Method(_DIS ,0) { - /* DBGO("\\_SB\\LNKB\\_DIS\n") */ - Store(0, PINB) - } /* End Method(_SB.INTB._DIS) */ - - Method(_PRS ,0) { - /* DBGO("\\_SB\\LNKB\\_PRS\n") */ - Return(IRQP) - } /* Method(_SB.INTB._PRS) */ - - Method(_CRS ,0) { - /* DBGO("\\_SB\\LNKB\\_CRS\n") */ - CreateWordField(IRQB, 0x1, IRQN) - ShiftLeft(1, PINB, IRQN) - Return(IRQB) - } /* Method(_SB.INTB._CRS) */ - - Method(_SRS, 1) { - /* DBGO("\\_SB\\LNKB\\_CRS\n") */ - CreateWordField(ARG0, 1, IRQM) - - /* Use lowest available IRQ */ - FindSetRightBit(IRQM, Local0) - if (Local0) { - Decrement(Local0) - } - Store(Local0, PINB) - } /* End Method(_SB.INTB._SRS) */ - } /* End Device(INTB) */ - - Device(INTC) { - Name(_HID, EISAID("PNP0C0F")) - Name(_UID, 3) - - Method(_STA, 0) { - if (PINC) { - Return(0x0B) /* sata is invisible */ - } else { - Return(0x09) /* sata is disabled */ - } - } /* End Method(_SB.INTC._STA) */ - - Method(_DIS ,0) { - /* DBGO("\\_SB\\LNKC\\_DIS\n") */ - Store(0, PINC) - } /* End Method(_SB.INTC._DIS) */ - - Method(_PRS ,0) { - /* DBGO("\\_SB\\LNKC\\_PRS\n") */ - Return(IRQP) - } /* Method(_SB.INTC._PRS) */ - - Method(_CRS ,0) { - /* DBGO("\\_SB\\LNKC\\_CRS\n") */ - CreateWordField(IRQB, 0x1, IRQN) - ShiftLeft(1, PINC, IRQN) - Return(IRQB) - } /* Method(_SB.INTC._CRS) */ - - Method(_SRS, 1) { - /* DBGO("\\_SB\\LNKC\\_CRS\n") */ - CreateWordField(ARG0, 1, IRQM) - - /* Use lowest available IRQ */ - FindSetRightBit(IRQM, Local0) - if (Local0) { - Decrement(Local0) - } - Store(Local0, PINC) - } /* End Method(_SB.INTC._SRS) */ - } /* End Device(INTC) */ - - Device(INTD) { - Name(_HID, EISAID("PNP0C0F")) - Name(_UID, 4) - - Method(_STA, 0) { - if (PIND) { - Return(0x0B) /* sata is invisible */ - } else { - Return(0x09) /* sata is disabled */ - } - } /* End Method(_SB.INTD._STA) */ - - Method(_DIS ,0) { - /* DBGO("\\_SB\\LNKD\\_DIS\n") */ - Store(0, PIND) - } /* End Method(_SB.INTD._DIS) */ - - Method(_PRS ,0) { - /* DBGO("\\_SB\\LNKD\\_PRS\n") */ - Return(IRQP) - } /* Method(_SB.INTD._PRS) */ - - Method(_CRS ,0) { - /* DBGO("\\_SB\\LNKD\\_CRS\n") */ - CreateWordField(IRQB, 0x1, IRQN) - ShiftLeft(1, PIND, IRQN) - Return(IRQB) - } /* Method(_SB.INTD._CRS) */ - - Method(_SRS, 1) { - /* DBGO("\\_SB\\LNKD\\_CRS\n") */ - CreateWordField(ARG0, 1, IRQM) - - /* Use lowest available IRQ */ - FindSetRightBit(IRQM, Local0) - if (Local0) { - Decrement(Local0) - } - Store(Local0, PIND) - } /* End Method(_SB.INTD._SRS) */ - } /* End Device(INTD) */ - - Device(INTE) { - Name(_HID, EISAID("PNP0C0F")) - Name(_UID, 5) - - Method(_STA, 0) { - if (PINE) { - Return(0x0B) /* sata is invisible */ - } else { - Return(0x09) /* sata is disabled */ - } - } /* End Method(_SB.INTE._STA) */ - - Method(_DIS ,0) { - /* DBGO("\\_SB\\LNKE\\_DIS\n") */ - Store(0, PINE) - } /* End Method(_SB.INTE._DIS) */ - - Method(_PRS ,0) { - /* DBGO("\\_SB\\LNKE\\_PRS\n") */ - Return(IRQP) - } /* Method(_SB.INTE._PRS) */ - - Method(_CRS ,0) { - /* DBGO("\\_SB\\LNKE\\_CRS\n") */ - CreateWordField(IRQB, 0x1, IRQN) - ShiftLeft(1, PINE, IRQN) - Return(IRQB) - } /* Method(_SB.INTE._CRS) */ - - Method(_SRS, 1) { - /* DBGO("\\_SB\\LNKE\\_CRS\n") */ - CreateWordField(ARG0, 1, IRQM) - - /* Use lowest available IRQ */ - FindSetRightBit(IRQM, Local0) - if (Local0) { - Decrement(Local0) - } - Store(Local0, PINE) - } /* End Method(_SB.INTE._SRS) */ - } /* End Device(INTE) */ - - Device(INTF) { - Name(_HID, EISAID("PNP0C0F")) - Name(_UID, 6) - - Method(_STA, 0) { - if (PINF) { - Return(0x0B) /* sata is invisible */ - } else { - Return(0x09) /* sata is disabled */ - } - } /* End Method(_SB.INTF._STA) */ - - Method(_DIS ,0) { - /* DBGO("\\_SB\\LNKF\\_DIS\n") */ - Store(0, PINF) - } /* End Method(_SB.INTF._DIS) */ - - Method(_PRS ,0) { - /* DBGO("\\_SB\\LNKF\\_PRS\n") */ - Return(PITF) - } /* Method(_SB.INTF._PRS) */ - - Method(_CRS ,0) { - /* DBGO("\\_SB\\LNKF\\_CRS\n") */ - CreateWordField(IRQB, 0x1, IRQN) - ShiftLeft(1, PINF, IRQN) - Return(IRQB) - } /* Method(_SB.INTF._CRS) */ - - Method(_SRS, 1) { - /* DBGO("\\_SB\\LNKF\\_CRS\n") */ - CreateWordField(ARG0, 1, IRQM) - - /* Use lowest available IRQ */ - FindSetRightBit(IRQM, Local0) - if (Local0) { - Decrement(Local0) - } - Store(Local0, PINF) - } /* End Method(_SB.INTF._SRS) */ - } /* End Device(INTF) */ - - Device(INTG) { - Name(_HID, EISAID("PNP0C0F")) - Name(_UID, 7) - - Method(_STA, 0) { - if (PING) { - Return(0x0B) /* sata is invisible */ - } else { - Return(0x09) /* sata is disabled */ - } - } /* End Method(_SB.INTG._STA) */ - - Method(_DIS ,0) { - /* DBGO("\\_SB\\LNKG\\_DIS\n") */ - Store(0, PING) - } /* End Method(_SB.INTG._DIS) */ - - Method(_PRS ,0) { - /* DBGO("\\_SB\\LNKG\\_PRS\n") */ - Return(IRQP) - } /* Method(_SB.INTG._CRS) */ - - Method(_CRS ,0) { - /* DBGO("\\_SB\\LNKG\\_CRS\n") */ - CreateWordField(IRQB, 0x1, IRQN) - ShiftLeft(1, PING, IRQN) - Return(IRQB) - } /* Method(_SB.INTG._CRS) */ - - Method(_SRS, 1) { - /* DBGO("\\_SB\\LNKG\\_CRS\n") */ - CreateWordField(ARG0, 1, IRQM) - - /* Use lowest available IRQ */ - FindSetRightBit(IRQM, Local0) - if (Local0) { - Decrement(Local0) - } - Store(Local0, PING) - } /* End Method(_SB.INTG._SRS) */ - } /* End Device(INTG) */ - - Device(INTH) { - Name(_HID, EISAID("PNP0C0F")) - Name(_UID, 8) - - Method(_STA, 0) { - if (PINH) { - Return(0x0B) /* sata is invisible */ - } else { - Return(0x09) /* sata is disabled */ - } - } /* End Method(_SB.INTH._STA) */ - - Method(_DIS ,0) { - /* DBGO("\\_SB\\LNKH\\_DIS\n") */ - Store(0, PINH) - } /* End Method(_SB.INTH._DIS) */ - - Method(_PRS ,0) { - /* DBGO("\\_SB\\LNKH\\_PRS\n") */ - Return(IRQP) - } /* Method(_SB.INTH._CRS) */ - - Method(_CRS ,0) { - /* DBGO("\\_SB\\LNKH\\_CRS\n") */ - CreateWordField(IRQB, 0x1, IRQN) - ShiftLeft(1, PINH, IRQN) - Return(IRQB) - } /* Method(_SB.INTH._CRS) */ - - Method(_SRS, 1) { - /* DBGO("\\_SB\\LNKH\\_CRS\n") */ - CreateWordField(ARG0, 1, IRQM) - - /* Use lowest available IRQ */ - FindSetRightBit(IRQM, Local0) - if (Local0) { - Decrement(Local0) - } - Store(Local0, PINH) - } /* End Method(_SB.INTH._SRS) */ - } /* End Device(INTH) */ - - } /* End Scope(_SB) */ - - #include - - /* Wake status package */ - Name(WKST,Package(){Zero, Zero}) - - /* - * \_PTS - Prepare to Sleep method - * - * Entry: - * Arg0=The value of the sleeping state S1=1, S2=2, etc - * - * Exit: - * -none- - * - * The _PTS control method is executed at the beginning of the sleep process - * for S1-S5. The sleeping value is passed to the _PTS control method. This - * control method may be executed a relatively long time before entering the - * sleep state and the OS may abort the operation without notification to - * the ACPI driver. This method cannot modify the configuration or power - * state of any device in the system. - */ - Method(\_PTS, 1) { - /* DBGO("\\_PTS\n") */ - /* DBGO("From S0 to S") */ - /* DBGO(Arg0) */ - /* DBGO("\n") */ - - /* Don't allow PCIRST# to reset USB */ - if (LEqual(Arg0,3)){ - Store(0,URRE) - } - - /* Clear sleep SMI status flag and enable sleep SMI trap. */ - /*Store(One, CSSM) - Store(One, SSEN)*/ - - /* On older chips, clear PciExpWakeDisEn */ - /*if (LLessEqual(\_SB.SBRI, 0x13)) { - * Store(0,\_SB.PWDE) - *} - */ - - /* Clear wake status structure. */ - Store(0, Index(WKST,0)) - Store(0, Index(WKST,1)) - \_SB.PCI0.SIOS (Arg0) - } /* End Method(\_PTS) */ - - /* - * The following method results in a "not a valid reserved NameSeg" - * warning so I have commented it out for the duration. It isn't - * used, so it could be removed. - * - * - * \_GTS OEM Going To Sleep method - * - * Entry: - * Arg0=The value of the sleeping state S1=1, S2=2 - * - * Exit: - * -none- - * - * Method(\_GTS, 1) { - * DBGO("\\_GTS\n") - * DBGO("From S0 to S") - * DBGO(Arg0) - * DBGO("\n") - * } - */ - - /* - * \_BFS OEM Back From Sleep method - * - * Entry: - * Arg0=The value of the sleeping state S1=1, S2=2 - * - * Exit: - * -none- - */ - Method(\_BFS, 1) { - /* DBGO("\\_BFS\n") */ - /* DBGO("From S") */ - /* DBGO(Arg0) */ - /* DBGO(" to S0\n") */ - } - - /* - * \_WAK System Wake method - * - * Entry: - * Arg0=The value of the sleeping state S1=1, S2=2 - * - * Exit: - * Return package of 2 DWords - * Dword 1 - Status - * 0x00000000 wake succeeded - * 0x00000001 Wake was signaled but failed due to lack of power - * 0x00000002 Wake was signaled but failed due to thermal condition - * Dword 2 - Power Supply state - * if non-zero the effective S-state the power supply entered - */ - Method(\_WAK, 1) { - /* DBGO("\\_WAK\n") */ - /* DBGO("From S") */ - /* DBGO(Arg0) */ - /* DBGO(" to S0\n") */ - - /* Re-enable HPET */ - Store(1,HPDE) - - /* Restore PCIRST# so it resets USB */ - if (LEqual(Arg0,3)){ - Store(1,URRE) - } - - /* Arbitrarily clear PciExpWakeStatus */ - Store(PWST, Local1) - Store(Local1, PWST) - - /* if (DeRefOf(Index(WKST,0))) { - * Store(0, Index(WKST,1)) - * } else { - * Store(Arg0, Index(WKST,1)) - * } - */ - \_SB.PCI0.SIOW () - Return(WKST) - } /* End Method(\_WAK) */ - - Scope(\_GPE) { /* Start Scope GPE */ - /* General event 0 */ - /* Method(_L00) { - * DBGO("\\_GPE\\_L00\n") - * } - */ - - /* General event 1 */ - /* Method(_L01) { - * DBGO("\\_GPE\\_L00\n") - * } - */ - - /* General event 2 */ - /* Method(_L02) { - * DBGO("\\_GPE\\_L00\n") - * } - */ - - /* General event 3 */ - Method(_L03) { - /* DBGO("\\_GPE\\_L00\n") */ - Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ - } - - /* General event 4 */ - /* Method(_L04) { - * DBGO("\\_GPE\\_L00\n") - * } - */ - - /* General event 5 */ - /* Method(_L05) { - * DBGO("\\_GPE\\_L00\n") - * } - */ - - /* General event 6 - Used for GPM6, moved to USB.asl */ - /* Method(_L06) { - * DBGO("\\_GPE\\_L00\n") - * } - */ - - /* General event 7 - Used for GPM7, moved to USB.asl */ - /* Method(_L07) { - * DBGO("\\_GPE\\_L07\n") - * } - */ - - /* Legacy PM event */ - Method(_L08) { - /* DBGO("\\_GPE\\_L08\n") */ - } - - /* Temp warning (TWarn) event */ - Method(_L09) { - /* DBGO("\\_GPE\\_L09\n") */ - Notify (\_TZ.TZ00, 0x80) - } - - /* Reserved */ - /* Method(_L0A) { - * DBGO("\\_GPE\\_L0A\n") - * } - */ - - /* USB controller PME# */ - Method(_L0B) { - /* DBGO("\\_GPE\\_L0B\n") */ - Notify(\_SB.PCI0.UOH1, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(\_SB.PCI0.UOH2, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(\_SB.PCI0.UOH3, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(\_SB.PCI0.UOH4, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(\_SB.PCI0.UOH5, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(\_SB.PCI0.UEH1, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ - } - - /* AC97 controller PME# */ - /* Method(_L0C) { - * DBGO("\\_GPE\\_L0C\n") - * } - */ - - /* OtherTherm PME# */ - /* Method(_L0D) { - * DBGO("\\_GPE\\_L0D\n") - * } - */ - - /* GPM9 SCI event - Moved to USB.asl */ - /* Method(_L0E) { - * DBGO("\\_GPE\\_L0E\n") - * } - */ - - /* PCIe HotPlug event */ - /* Method(_L0F) { - * DBGO("\\_GPE\\_L0F\n") - * } - */ - - /* ExtEvent0 SCI event */ - Method(_L10) { - /* DBGO("\\_GPE\\_L10\n") */ - } - - - /* ExtEvent1 SCI event */ - Method(_L11) { - /* DBGO("\\_GPE\\_L11\n") */ - } - - /* PCIe PME# event */ - /* Method(_L12) { - * DBGO("\\_GPE\\_L12\n") - * } - */ - - /* GPM0 SCI event - Moved to USB.asl */ - /* Method(_L13) { - * DBGO("\\_GPE\\_L13\n") - * } - */ - - /* GPM1 SCI event - Moved to USB.asl */ - /* Method(_L14) { - * DBGO("\\_GPE\\_L14\n") - * } - */ - - /* GPM2 SCI event - Moved to USB.asl */ - /* Method(_L15) { - * DBGO("\\_GPE\\_L15\n") - * } - */ - - /* GPM3 SCI event - Moved to USB.asl */ - /* Method(_L16) { - * DBGO("\\_GPE\\_L16\n") - * } - */ - - /* GPM8 SCI event - Moved to USB.asl */ - /* Method(_L17) { - * DBGO("\\_GPE\\_L17\n") - * } - */ - - /* GPIO0 or GEvent8 event */ - Method(_L18) { - /* DBGO("\\_GPE\\_L18\n") */ - Notify(\_SB.PCI0.PBR2, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(\_SB.PCI0.PBR4, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(\_SB.PCI0.PBR5, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(\_SB.PCI0.PBR6, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(\_SB.PCI0.PBR7, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ - } - - /* GPM4 SCI event - Moved to USB.asl */ - /* Method(_L19) { - * DBGO("\\_GPE\\_L19\n") - * } - */ - - /* GPM5 SCI event - Moved to USB.asl */ - /* Method(_L1A) { - * DBGO("\\_GPE\\_L1A\n") - * } - */ - - /* Azalia SCI event */ - Method(_L1B) { - /* DBGO("\\_GPE\\_L1B\n") */ - Notify(\_SB.PCI0.AZHD, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ - } - - /* GPM6 SCI event - Reassigned to _L06 */ - /* Method(_L1C) { - * DBGO("\\_GPE\\_L1C\n") - * } - */ - - /* GPM7 SCI event - Reassigned to _L07 */ - /* Method(_L1D) { - * DBGO("\\_GPE\\_L1D\n") - * } - */ - - /* GPIO2 or GPIO66 SCI event */ - /* Method(_L1E) { - * DBGO("\\_GPE\\_L1E\n") - * } - */ - - /* SATA SCI event - Moved to sata.asl */ - /* Method(_L1F) { - * DBGO("\\_GPE\\_L1F\n") - * } - */ - - } /* End Scope GPE */ - - #include "acpi/usb.asl" - - /* System Bus */ - Scope(\_SB) { /* Start \_SB scope */ - #include /* global utility methods expected within the \_SB scope */ - - /* _SB.PCI0 */ - /* Note: Only need HID on Primary Bus */ - Device(PCI0) { - External (TOM1) - External (TOM2) /* ( >> 20) to make it fit into 32 bit for XP */ - Name(_HID, EISAID("PNP0A03")) - Name(_ADR, 0x00180000) /* Dev# = BSP Dev#, Func# = 0 */ - Method(_BBN, 0) { /* Bus number = 0 */ - Return(0) - } - Method(_STA, 0) { - /* DBGO("\\_SB\\PCI0\\_STA\n") */ - Return(0x0B) /* Status is visible */ - } - - Method(_PRT,0) { - If(PMOD){ Return(APR0) } /* APIC mode */ - Return (PR0) /* PIC Mode */ - } /* end _PRT */ - - /* Describe the Northbridge devices */ - Device(AMRT) { - Name(_ADR, 0x00000000) - } /* end AMRT */ - - /* The internal GFX bridge */ - Device(AGPB) { - Name(_ADR, 0x00010000) - Name(_PRW, Package() {0x18, 4}) - Method(_PRT,0) { - Return (APR1) - } - } /* end AGPB */ - - /* The external GFX bridge */ - Device(PBR2) { - Name(_ADR, 0x00020000) - Name(_PRW, Package() {0x18, 4}) - Method(_PRT,0) { - If(PMOD){ Return(APS2) } /* APIC mode */ - Return (PS2) /* PIC Mode */ - } /* end _PRT */ - } /* end PBR2 */ - - /* Dev3 is also an external GFX bridge, not used in Herring */ - - Device(PBR4) { - Name(_ADR, 0x00040000) - Name(_PRW, Package() {0x18, 4}) - Method(_PRT,0) { - If(PMOD){ Return(APS4) } /* APIC mode */ - Return (PS4) /* PIC Mode */ - } /* end _PRT */ - } /* end PBR4 */ - - Device(PBR5) { - Name(_ADR, 0x00050000) - Name(_PRW, Package() {0x18, 4}) - Method(_PRT,0) { - If(PMOD){ Return(APS5) } /* APIC mode */ - Return (PS5) /* PIC Mode */ - } /* end _PRT */ - } /* end PBR5 */ - - Device(PBR6) { - Name(_ADR, 0x00060000) - Name(_PRW, Package() {0x18, 4}) - Method(_PRT,0) { - If(PMOD){ Return(APS6) } /* APIC mode */ - Return (PS6) /* PIC Mode */ - } /* end _PRT */ - } /* end PBR6 */ - - /* The onboard EtherNet chip */ - Device(PBR7) { - Name(_ADR, 0x00070000) - Name(_PRW, Package() {0x18, 4}) - Method(_PRT,0) { - If(PMOD){ Return(APS7) } /* APIC mode */ - Return (PS7) /* PIC Mode */ - } /* end _PRT */ - } /* end PBR7 */ - - /* GPP */ - Device(PBR9) { - Name(_ADR, 0x00090000) - Name(_PRW, Package() {0x18, 4}) - Method(_PRT,0) { - If(PMOD){ Return(APS9) } /* APIC mode */ - Return (PS9) /* PIC Mode */ - } /* end _PRT */ - } /* end PBR9 */ - - Device(PBRa) { - Name(_ADR, 0x000A0000) - Name(_PRW, Package() {0x18, 4}) - Method(_PRT,0) { - If(PMOD){ Return(APSa) } /* APIC mode */ - Return (PSa) /* PIC Mode */ - } /* end _PRT */ - } /* end PBRa */ - - - /* PCI slot 1, 2, 3 */ - Device(PIBR) { - Name(_ADR, 0x00140004) - Name(_PRW, Package() {0x18, 4}) - - Method(_PRT, 0) { - Return (PCIB) - } - } - - /* Describe the Southbridge devices */ - Device(STCR) { - Name(_ADR, 0x00110000) - #include "acpi/sata.asl" - } /* end STCR */ - - Device(UOH1) { - Name(_ADR, 0x00130000) - Name(_PRW, Package() {0x0B, 3}) - } /* end UOH1 */ - - Device(UOH2) { - Name(_ADR, 0x00130001) - Name(_PRW, Package() {0x0B, 3}) - } /* end UOH2 */ - - Device(UOH3) { - Name(_ADR, 0x00130002) - Name(_PRW, Package() {0x0B, 3}) - } /* end UOH3 */ - - Device(UOH4) { - Name(_ADR, 0x00130003) - Name(_PRW, Package() {0x0B, 3}) - } /* end UOH4 */ - - Device(UOH5) { - Name(_ADR, 0x00130004) - Name(_PRW, Package() {0x0B, 3}) - } /* end UOH5 */ - - Device(UEH1) { - Name(_ADR, 0x00130005) - Name(_PRW, Package() {0x0B, 3}) - } /* end UEH1 */ - - Device(SBUS) { - Name(_ADR, 0x00140000) - } /* end SBUS */ - - /* Primary (and only) IDE channel */ - Device(IDEC) { - Name(_ADR, 0x00140001) - #include "acpi/ide.asl" - } /* end IDEC */ - - Device(AZHD) { - Name(_ADR, 0x00140002) - OperationRegion(AZPD, PCI_Config, 0x00, 0x100) - Field(AZPD, AnyAcc, NoLock, Preserve) { - offset (0x42), - NSDI, 1, - NSDO, 1, - NSEN, 1, - offset (0x44), - IPCR, 4, - offset (0x54), - PWST, 2, - , 6, - PMEB, 1, - , 6, - PMST, 1, - offset (0x62), - MMCR, 1, - offset (0x64), - MMLA, 32, - offset (0x68), - MMHA, 32, - offset (0x6C), - MMDT, 16, - } - - Method(_INI) { - If(LEqual(OSVR,3)){ /* If we are running Linux */ - Store(zero, NSEN) - Store(one, NSDO) - Store(one, NSDI) - } - } - } /* end AZHD */ - - Device(LIBR) { - Name(_ADR, 0x00140003) - /* Method(_INI) { - * DBGO("\\_SB\\PCI0\\LpcIsaBr\\_INI\n") - } */ /* End Method(_SB.SBRDG._INI) */ - - /* Real Time Clock Device */ - Device(RTC0) { - Name(_HID, EISAID("PNP0B00")) /* AT Real Time Clock (not PIIX4 compatible) */ - Name(_CRS, ResourceTemplate() { - IRQNoFlags(){8} - IO(Decode16,0x0070, 0x0070, 0, 2) - /* IO(Decode16,0x0070, 0x0070, 0, 4) */ - }) - } /* End Device(_SB.PCI0.LpcIsaBr.RTC0) */ - - Device(TMR) { /* Timer */ - Name(_HID,EISAID("PNP0100")) /* System Timer */ - Name(_CRS, ResourceTemplate() { - IRQNoFlags(){0} - IO(Decode16, 0x0040, 0x0040, 0, 4) - /* IO(Decode16, 0x0048, 0x0048, 0, 4) */ - }) - } /* End Device(_SB.PCI0.LpcIsaBr.TMR) */ - - Device(SPKR) { /* Speaker */ - Name(_HID,EISAID("PNP0800")) /* AT style speaker */ - Name(_CRS, ResourceTemplate() { - IO(Decode16, 0x0061, 0x0061, 0, 1) - }) - } /* End Device(_SB.PCI0.LpcIsaBr.SPKR) */ - - Device(PIC) { - Name(_HID,EISAID("PNP0000")) /* AT Interrupt Controller */ - Name(_CRS, ResourceTemplate() { - IRQNoFlags(){2} - IO(Decode16,0x0020, 0x0020, 0, 2) - IO(Decode16,0x00A0, 0x00A0, 0, 2) - /* IO(Decode16, 0x00D0, 0x00D0, 0x10, 0x02) */ - /* IO(Decode16, 0x04D0, 0x04D0, 0x10, 0x02) */ - }) - } /* End Device(_SB.PCI0.LpcIsaBr.PIC) */ - - Device(MAD) { /* 8257 DMA */ - Name(_HID,EISAID("PNP0200")) /* Hardware Device ID */ - Name(_CRS, ResourceTemplate() { - DMA(Compatibility,BusMaster,Transfer8){4} - IO(Decode16, 0x0000, 0x0000, 0x10, 0x10) - IO(Decode16, 0x0081, 0x0081, 0x01, 0x03) - IO(Decode16, 0x0087, 0x0087, 0x01, 0x01) - IO(Decode16, 0x0089, 0x0089, 0x01, 0x03) - IO(Decode16, 0x008F, 0x008F, 0x01, 0x01) - IO(Decode16, 0x00C0, 0x00C0, 0x10, 0x20) - }) /* End Name(_SB.PCI0.LpcIsaBr.MAD._CRS) */ - } /* End Device(_SB.PCI0.LpcIsaBr.MAD) */ - - Device(COPR) { - Name(_HID,EISAID("PNP0C04")) /* Math Coprocessor */ - Name(_CRS, ResourceTemplate() { - IO(Decode16, 0x00F0, 0x00F0, 0, 0x10) - IRQNoFlags(){13} - }) - } /* End Device(_SB.PCI0.LpcIsaBr.COPR) */ - - Device(HPTM) { - Name(_HID,EISAID("PNP0103")) - Name(CRS,ResourceTemplate() { - Memory32Fixed(ReadOnly,0xFED00000, 0x00000400, HPT) /* 1kb reserved space */ - }) - Method(_STA, 0) { - Return(0x0F) /* sata is visible */ - } - Method(_CRS, 0) { - CreateDwordField(CRS, ^HPT._BAS, HPBX) - Store(HPBA, HPBX) - Return(CRS) - } - } /* End Device(_SB.PCI0.LpcIsaBr.COPR) */ - } /* end LIBR */ - - Device(HPBR) { - Name(_ADR, 0x00140004) - } /* end HostPciBr */ - - Device(ACAD) { - Name(_ADR, 0x00140005) - } /* end Ac97audio */ - - Device(ACMD) { - Name(_ADR, 0x00140006) - } /* end Ac97modem */ - - /* ITE8718 Support */ - OperationRegion (IOID, SystemIO, 0x2E, 0x02) /* sometimes it is 0x4E */ - Field (IOID, ByteAcc, NoLock, Preserve) - { - SIOI, 8, SIOD, 8 /* 0x2E and 0x2F */ - } - - IndexField (SIOI, SIOD, ByteAcc, NoLock, Preserve) - { - Offset (0x07), - LDN, 8, /* Logical Device Number */ - Offset (0x20), - CID1, 8, /* Chip ID Byte 1, 0x87 */ - CID2, 8, /* Chip ID Byte 2, 0x12 */ - Offset (0x30), - ACTR, 8, /* Function activate */ - Offset (0xF0), - APC0, 8, /* APC/PME Event Enable Register */ - APC1, 8, /* APC/PME Status Register */ - APC2, 8, /* APC/PME Control Register 1 */ - APC3, 8, /* Environment Controller Special Configuration Register */ - APC4, 8 /* APC/PME Control Register 2 */ - } - - /* Enter the 8718 MB PnP Mode */ - Method (EPNP) - { - Store(0x87, SIOI) - Store(0x01, SIOI) - Store(0x55, SIOI) - Store(0x55, SIOI) /* 8718 magic number */ - } - /* Exit the 8718 MB PnP Mode */ - Method (XPNP) - { - Store (0x02, SIOI) - Store (0x02, SIOD) - } - /* - * Keyboard PME is routed to SB700 Gevent3. We can wake - * up the system by pressing the key. - */ - Method (SIOS, 1) - { - /* We only enable KBD PME for S5. */ - If (LLess (Arg0, 0x05)) - { - EPNP() - /* DBGO("8718F\n") */ - - Store (0x4, LDN) - Store (One, ACTR) /* Enable EC */ - /* - Store (0x4, LDN) - Store (0x04, APC4) - */ /* falling edge. which mode? Not sure. */ - - Store (0x4, LDN) - Store (0x08, APC1) /* clear PME status, Use 0x18 for mouse & KBD */ - Store (0x4, LDN) - Store (0x08, APC0) /* enable PME, Use 0x18 for mouse & KBD */ - - XPNP() - } - } - Method (SIOW, 0) - { - EPNP() - Store (0x4, LDN) - Store (Zero, APC0) /* disable keyboard PME */ - Store (0x4, LDN) - Store (0xFF, APC1) /* clear keyboard PME status */ - XPNP() - } - - Name(CRES, ResourceTemplate() { - IO(Decode16, 0x0CF8, 0x0CF8, 1, 8) - - WORDIO(ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, - 0x0000, /* address granularity */ - 0x0000, /* range minimum */ - 0x0CF7, /* range maximum */ - 0x0000, /* translation */ - 0x0CF8 /* length */ - ) - - WORDIO(ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, - 0x0000, /* address granularity */ - 0x0D00, /* range minimum */ - 0xFFFF, /* range maximum */ - 0x0000, /* translation */ - 0xF300 /* length */ - ) - -#if 0 - Memory32Fixed(READWRITE, 0, 0xA0000, BSMM) - Memory32Fixed(READONLY, 0x000A0000, 0x00020000, VGAM) /* VGA memory space */ - Memory32Fixed(READONLY, 0x000C0000, 0x00020000, EMM1) /* Assume C0000-E0000 empty */ - Memory32Fixed(READONLY, 0x000E0000, 0x00020000, RDBS) /* BIOS ROM area */ - - /* DRAM Memory from 1MB to TopMem */ - Memory32Fixed(READWRITE, 0x00100000, 0, DMLO) /* 1MB to TopMem */ - - /* BIOS space just below 4GB */ - DWORDMemory( - ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite, - 0x00, /* Granularity */ - 0x00000000, /* Min */ - 0x00000000, /* Max */ - 0x00000000, /* Translation */ - 0x00000001, /* Max-Min, RLEN */ - ,, - PCBM - ) - - /* DRAM memory from 4GB to TopMem2 */ - QWORDMemory(ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite, - 0x00000000, /* Granularity */ - 0x00000000, /* Min */ - 0x00000000, /* Max */ - 0x00000000, /* Translation */ - 0x00000001, /* Max-Min, RLEN */ - ,, - DMHI - ) - - /* BIOS space just below 16EB */ - QWORDMemory(ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite, - 0x00000000, /* Granularity */ - 0x00000000, /* Min */ - 0x00000000, /* Max */ - 0x00000000, /* Translation */ - 0x00000001, /* Max-Min, RLEN */ - ,, - PEBM - ) -#endif - - /* memory space for PCI BARs below 4GB */ - Memory32Fixed(ReadOnly, 0x00000000, 0x00000000, MMIO) - }) /* End Name(_SB.PCI0.CRES) */ - - Method(_CRS, 0) { - /* DBGO("\\_SB\\PCI0\\_CRS\n") */ - -#if 0 - CreateDWordField(CRES, ^EMM1._BAS, EM1B) - CreateDWordField(CRES, ^EMM1._LEN, EM1L) - CreateDWordField(CRES, ^DMLO._BAS, DMLB) - CreateDWordField(CRES, ^DMLO._LEN, DMLL) - CreateDWordField(CRES, ^PCBM._MIN, PBMB) - CreateDWordField(CRES, ^PCBM._LEN, PBML) - - CreateQWordField(CRES, ^DMHI._MIN, DMHB) - CreateQWordField(CRES, ^DMHI._LEN, DMHL) - CreateQWordField(CRES, ^PEBM._MIN, EBMB) - CreateQWordField(CRES, ^PEBM._LEN, EBML) - - If(LGreater(LOMH, 0xC0000)){ - Store(0xC0000, EM1B) /* Hole above C0000 and below E0000 */ - Subtract(LOMH, 0xC0000, EM1L) /* subtract start, assumes allocation from C0000 going up */ - } - - /* Set size of memory from 1MB to TopMem */ - Subtract(TOM1, 0x100000, DMLL) - - /* - * If(LNotEqual(TOM2, 0x00000000)){ - * Store(0x100000000,DMHB) DRAM from 4GB to TopMem2 - * ShiftLeft(TOM2, 20, Local0) - * Subtract(Local0, 0x100000000, DMHL) - * } - */ - - /* If there is no memory above 4GB, put the BIOS just below 4GB */ - If(LEqual(TOM2, 0x00000000)){ - Store(PBAD,PBMB) /* Reserve the "BIOS" space */ - Store(PBLN,PBML) - } - Else { /* Otherwise, put the BIOS just below 16EB */ - ShiftLeft(PBAD,16,EBMB) /* Reserve the "BIOS" space */ - Store(PBLN,EBML) - } -#endif - - CreateDWordField(CRES, ^MMIO._BAS, MM1B) - CreateDWordField(CRES, ^MMIO._LEN, MM1L) - /* - * Declare memory between TOM1 and 4GB as available - * for PCI MMIO. - * Use ShiftLeft to avoid 64bit constant (for XP). - * This will work even if the OS does 32bit arithmetic, as - * 32bit (0x00000000 - TOM1) will wrap and give the same - * result as 64bit (0x100000000 - TOM1). - */ - Store(TOM1, MM1B) - ShiftLeft(0x10000000, 4, Local0) - Subtract(Local0, TOM1, Local0) - Store(Local0, MM1L) - - Return(CRES) /* note to change the Name buffer */ - } /* end of Method(_SB.PCI0._CRS) */ - - /* - * - * FIRST METHOD CALLED UPON BOOT - * - * 1. If debugging, print current OS and ACPI interpreter. - * 2. Get PCI Interrupt routing from ACPI VSM, this - * value is based on user choice in BIOS setup. - */ - Method(_INI, 0) { - /* DBGO("\\_SB\\_INI\n") */ - /* DBGO(" DSDT.ASL code from ") */ - /* DBGO(__DATE__) */ - /* DBGO(" ") */ - /* DBGO(__TIME__) */ - /* DBGO("\n Sleep states supported: ") */ - /* DBGO("\n") */ - /* DBGO(" \\_OS=") */ - /* DBGO(\_OS) */ - /* DBGO("\n \\_REV=") */ - /* DBGO(\_REV) */ - /* DBGO("\n") */ - - /* Determine the OS we're running on */ - OSFL() - - /* On older chips, clear PciExpWakeDisEn */ - /*if (LLessEqual(\SBRI, 0x13)) { - * Store(0,\PWDE) - * } - */ - } /* End Method(_SB._INI) */ - } /* End Device(PCI0) */ - - Device(PWRB) { /* Start Power button device */ - Name(_HID, EISAID("PNP0C0C")) - Name(_UID, 0xAA) - Name(_PRW, Package () {3, 0x04}) /* wake from S1-S4 */ - Name(_STA, 0x0B) /* sata is invisible */ - } - } /* End \_SB scope */ - - Scope(\_SI) { - Method(_SST, 1) { - /* DBGO("\\_SI\\_SST\n") */ - /* DBGO(" New Indicator state: ") */ - /* DBGO(Arg0) */ - /* DBGO("\n") */ - } - } /* End Scope SI */ - - #include - - /* THERMAL */ - Scope(\_TZ) { - Name (KELV, 2732) - Name (THOT, 800) - Name (TCRT, 850) - - ThermalZone(TZ00) { - Method(_AC0,0) { /* Active Cooling 0 (0=highest fan speed) */ - /* DBGO("\\_TZ\\TZ00\\_AC0\n") */ - Return(Add(0, 2730)) - } - Method(_AL0,0) { /* Returns package of cooling device to turn on */ - /* DBGO("\\_TZ\\TZ00\\_AL0\n") */ - Return(Package() {\_TZ.TZ00.FAN0}) - } - Device (FAN0) { - Name(_HID, EISAID("PNP0C0B")) - Name(_PR0, Package() {PFN0}) - } - - PowerResource(PFN0,0,0) { - Method(_STA) { - Store(0xF,Local0) - Return(Local0) - } - Method(_ON) { - /* DBGO("\\_TZ\\TZ00\\FAN0 _ON\n") */ - } - Method(_OFF) { - /* DBGO("\\_TZ\\TZ00\\FAN0 _OFF\n") */ - } - } - - Method(_HOT,0) { /* return hot temp in tenths degree Kelvin */ - /* DBGO("\\_TZ\\TZ00\\_HOT\n") */ - Return (Add (THOT, KELV)) - } - Method(_CRT,0) { /* return critical temp in tenths degree Kelvin */ - /* DBGO("\\_TZ\\TZ00\\_CRT\n") */ - Return (Add (TCRT, KELV)) - } - Method(_TMP,0) { /* return current temp of this zone */ - Store (SMBR (0x07, 0x4C,, 0x00), Local0) - If (LGreater (Local0, 0x10)) { - Store (Local0, Local1) - } - Else { - Add (Local0, THOT, Local0) - Return (Add (400, KELV)) - } - - Store (SMBR (0x07, 0x4C, 0x01), Local0) - /* only the two MSBs in the external temperature low byte are used, resolution 0.25. We ignore it */ - /* Store (SMBR (0x07, 0x4C, 0x10), Local2) */ - If (LGreater (Local0, 0x10)) { - If (LGreater (Local0, Local1)) { - Store (Local0, Local1) - } - - Multiply (Local1, 10, Local1) - Return (Add (Local1, KELV)) - } - Else { - Add (Local0, THOT, Local0) - Return (Add (400 , KELV)) - } - } /* end of _TMP */ - } /* end of TZ00 */ - } -} -/* End of ASL file */ diff --git a/src/mainboard/amd/tilapia_fam10/get_bus_conf.c b/src/mainboard/amd/tilapia_fam10/get_bus_conf.c deleted file mode 100644 index 37a3774e46..0000000000 --- a/src/mainboard/amd/tilapia_fam10/get_bus_conf.c +++ /dev/null @@ -1,53 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2010 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include -#include - -#include - -/* Global variables for MB layouts and these will be shared by irqtable mptable -* and acpi_tables busnum is default. -*/ -u32 apicid_sb700; - -/* -* HT Chain device num, actually it is unit id base of every ht device in chain, -* assume every chain only have 4 ht device at most -*/ -u32 hcdnx[] = { - 0x20202020, -}; - - -void get_bus_conf(void) -{ - u32 apicid_base; - - get_default_pci1234(1); - - sysconf.sbdn = (sysconf.hcdn[0] & 0xff); - - pirq_router_bus = (sysconf.pci1234[0] >> 16) & 0xff; - - /* I/O APICs: APIC ID Version State Address */ - if (CONFIG(LOGICAL_CPUS)) - apicid_base = get_apicid_base(1); - else - apicid_base = CONFIG_MAX_PHYSICAL_CPUS; - apicid_sb700 = apicid_base + 0; -} diff --git a/src/mainboard/amd/tilapia_fam10/irq_tables.c b/src/mainboard/amd/tilapia_fam10/irq_tables.c deleted file mode 100644 index 0f7192514e..0000000000 --- a/src/mainboard/amd/tilapia_fam10/irq_tables.c +++ /dev/null @@ -1,102 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2010 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include -#include -#include - -#include - -static void write_pirq_info(struct irq_info *pirq_info, u8 bus, u8 devfn, - u8 link0, u16 bitmap0, u8 link1, u16 bitmap1, - u8 link2, u16 bitmap2, u8 link3, u16 bitmap3, - u8 slot, u8 rfu) -{ - pirq_info->bus = bus; - pirq_info->devfn = devfn; - pirq_info->irq[0].link = link0; - pirq_info->irq[0].bitmap = bitmap0; - pirq_info->irq[1].link = link1; - pirq_info->irq[1].bitmap = bitmap1; - pirq_info->irq[2].link = link2; - pirq_info->irq[2].bitmap = bitmap2; - pirq_info->irq[3].link = link3; - pirq_info->irq[3].bitmap = bitmap3; - pirq_info->slot = slot; - pirq_info->rfu = rfu; -} - - -unsigned long write_pirq_routing_table(unsigned long addr) -{ - struct irq_routing_table *pirq; - struct irq_info *pirq_info; - u32 slot_num; - u8 *v; - - u8 sum = 0; - int i; - - /* Align the table to be 16 byte aligned. */ - addr += 15; - addr &= ~15; - - /* This table must be between 0xf0000 & 0x100000 */ - printk(BIOS_INFO, "Writing IRQ routing tables to 0x%lx...", addr); - - pirq = (void *)(addr); - v = (u8 *) (addr); - - pirq->signature = PIRQ_SIGNATURE; - pirq->version = PIRQ_VERSION; - - pirq->rtr_bus = pirq_router_bus; - pirq->rtr_devfn = PCI_DEVFN(0x14, 4); - - pirq->exclusive_irqs = 0; - - pirq->rtr_vendor = 0x1002; - pirq->rtr_device = 0x4384; - - pirq->miniport_data = 0; - - memset(pirq->rfu, 0, sizeof(pirq->rfu)); - - pirq_info = (void *)(&pirq->checksum + 1); - slot_num = 0; - - /* pci bridge */ - write_pirq_info(pirq_info, pirq_router_bus, PCI_DEVFN(0x14, 4), - 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, - 0); - pirq_info++; - slot_num++; - - pirq->size = 32 + 16 * slot_num; - - for (i = 0; i < pirq->size; i++) - sum += v[i]; - - sum = pirq->checksum - sum; - if (sum != pirq->checksum) { - pirq->checksum = sum; - } - - printk(BIOS_INFO, "write_pirq_routing_table done.\n"); - - return (unsigned long)pirq_info; -} diff --git a/src/mainboard/amd/tilapia_fam10/mainboard.c b/src/mainboard/amd/tilapia_fam10/mainboard.c deleted file mode 100644 index 8e50114cab..0000000000 --- a/src/mainboard/amd/tilapia_fam10/mainboard.c +++ /dev/null @@ -1,232 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2010 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include -#include -#include -#include -#include -#include - -#define ADT7461_ADDRESS 0x4C -#define ARA_ADDRESS 0x0C /* Alert Response Address */ - -#define ADT7461_read_byte(address) \ - do_smbus_read_byte(SMBUS_IO_BASE, ADT7461_ADDRESS, address) -#define ARA_read_byte(address) \ - do_smbus_read_byte(SMBUS_IO_BASE, ARA_ADDRESS, address) -#define ADT7461_write_byte(address, val) \ - do_smbus_write_byte(SMBUS_IO_BASE, ADT7461_ADDRESS, address, val) - -void set_pcie_dereset(void) -{ - u8 byte; - u16 word; - struct device *sm_dev; - /* set 0 to bit1 :disable GPM9 as SLP_S2 output */ - /* set 0 to bit2 :disable GPM8 as AZ_RST output */ - byte = pm_ioread(0x8d); - byte &= ~((1 << 1) | (1 << 2)); - pm_iowrite(0x8d, byte); - - /* set the GPM8 and GPM9 output enable and the value to 1 */ - byte = pm_ioread(0x94); - byte &= ~((1 << 2) | (1 << 3)); - byte |= ((1 << 0) | (1 << 1)); - pm_iowrite(0x94, byte); - - /* set the GPIO65 output enable and the value is 1 */ - sm_dev = pcidev_on_root(0x14, 0); - word = pci_read_config16(sm_dev, 0x7e); - word |= (1 << 0); - word &= ~(1 << 4); - pci_write_config16(sm_dev, 0x7e, word); -} - -void set_pcie_reset(void) -{ - u8 byte; - u16 word; - struct device *sm_dev; - - /* set 0 to bit1 :disable GPM9 as SLP_S2 output */ - /* set 0 to bit2 :disable GPM8 as AZ_RST output */ - byte = pm_ioread(0x8d); - byte &= ~((1 << 1) | (1 << 2)); - pm_iowrite(0x8d, byte); - - /* set the GPM8 and GPM9 output enable and the value to 0 */ - byte = pm_ioread(0x94); - byte &= ~((1 << 2) | (1 << 3)); - byte &= ~((1 << 0) | (1 << 1)); - pm_iowrite(0x94, byte); - - /* set the GPIO65 output enable and the value is 0 */ - sm_dev = pcidev_on_root(0x14, 0); - word = pci_read_config16(sm_dev, 0x7e); - word &= ~(1 << 0); - word &= ~(1 << 4); - pci_write_config16(sm_dev, 0x7e, word); -} - -/* - * justify the dev3 is exist or not - */ -int is_dev3_present(void) -{ - u16 word; - struct device *sm_dev; - - /* access the smbus extended register */ - sm_dev = pcidev_on_root(0x14, 0); - - /* put the GPIO68 output to tristate */ - word = pci_read_config16(sm_dev, 0x7e); - word |= 1 << 6; - pci_write_config16(sm_dev, 0x7e,word); - - /* read the GPIO68 input status */ - word = pci_read_config16(sm_dev, 0x7e); - - return !(word & (1 << 10)); -} - - -/* - * set gpio40 gfx - */ -static void set_gpio40_gfx(void) -{ - u8 byte; - u32 dword; - struct device *sm_dev; - /* disable the GPIO40 as CLKREQ2# function */ - byte = pm_ioread(0xd3); - byte &= ~(1 << 7); - pm_iowrite(0xd3, byte); - - /* disable the GPIO40 as CLKREQ3# function */ - byte = pm_ioread(0xd4); - byte &= ~(1 << 0); - pm_iowrite(0xd4, byte); - - /* enable pull up for GPIO68 */ - byte = pm2_ioread(0xf1); - byte &= ~(1 << 4); - pm2_iowrite(0xf1, byte); - - /* access the smbus extended register */ - sm_dev = pcidev_on_root(0x14, 0); - - /*if the dev3 is present, set the gfx to 2x8 lanes*/ - /*otherwise set the gfx to 1x16 lanes*/ - if(is_dev3_present()){ - - printk(BIOS_INFO, "Dev3 is present. GFX Configuration is Two x8 slots\n"); - /* when the gpio40 is configured as GPIO, this will enable the output */ - pci_write_config32(sm_dev, 0xf8, 0x4); - dword = pci_read_config32(sm_dev, 0xfc); - dword &= ~(1 << 10); - - /* When the gpio40 is configured as GPIO, this will represent the output value*/ - /* 1: enable two x8, 0: master slot enable only */ - dword |= (1 << 26); - pci_write_config32(sm_dev, 0xfc, dword); - - }else{ - printk(BIOS_INFO, "Dev3 is not present. GFX Configuration is One x16 slot\n"); - /* when the gpio40 is configured as GPIO, this will enable the output */ - pci_write_config32(sm_dev, 0xf8, 0x4); - dword = pci_read_config32(sm_dev, 0xfc); - dword &= ~(1 << 10); - - /* When the gpio40 is configured as GPIO, this will represent the output value*/ - /* 1: enable two x8, 0: master slot enable only */ - dword &= ~(1 << 26); - pci_write_config32(sm_dev, 0xfc, dword); - } -} - -/* - * set thermal config - */ -static void set_thermal_config(void) -{ - u8 byte; - u16 word; - struct device *sm_dev; - - /* set ADT 7461 */ - ADT7461_write_byte(0x0B, 0x50); /* Local Temperature Hight limit */ - ADT7461_write_byte(0x0C, 0x00); /* Local Temperature Low limit */ - ADT7461_write_byte(0x0D, 0x50); /* External Temperature Hight limit High Byte */ - ADT7461_write_byte(0x0E, 0x00); /* External Temperature Low limit High Byte */ - - ADT7461_write_byte(0x19, 0x55); /* External THERM limit */ - ADT7461_write_byte(0x20, 0x55); /* Local THERM limit */ - - byte = ADT7461_read_byte(0x02); /* read status register to clear it */ - ARA_read_byte(0x05); /* A hardware alert can only be cleared by the master sending an ARA as a read command */ - printk(BIOS_INFO, "Init adt7461 end, status 0x02 %02x\n", byte); - - /* sb700 settings for thermal config */ - /* set SB700 GPIO 64 to GPIO with pull-up */ - byte = pm2_ioread(0x42); - byte &= 0x3f; - pm2_iowrite(0x42, byte); - - /* set GPIO 64 to input */ - sm_dev = pcidev_on_root(0x14, 0); - word = pci_read_config16(sm_dev, 0x56); - word |= 1 << 7; - pci_write_config16(sm_dev, 0x56, word); - - /* set GPIO 64 internal pull-up */ - byte = pm2_ioread(0xf0); - byte &= 0xee; - pm2_iowrite(0xf0, byte); - - /* set Talert to be active low */ - byte = pm_ioread(0x67); - byte &= ~(1 << 5); - pm_iowrite(0x67, byte); - - /* set Talert to generate ACPI event */ - byte = pm_ioread(0x3c); - byte &= 0xf3; - pm_iowrite(0x3c, byte); - - /* THERMTRIP pin */ - -} - -/************************************************* -* enable the dedicated function in tilapia board. -* This function called early than rs780_enable. -*************************************************/ -static void mainboard_enable(struct device *dev) -{ - printk(BIOS_INFO, "Mainboard TILAPIA Enable. dev=0x%p\n", dev); - - set_pcie_dereset(); - set_thermal_config(); - set_gpio40_gfx(); -} - -struct chip_operations mainboard_ops = { - .enable_dev = mainboard_enable, -}; diff --git a/src/mainboard/amd/tilapia_fam10/mptable.c b/src/mainboard/amd/tilapia_fam10/mptable.c deleted file mode 100644 index 090fd54331..0000000000 --- a/src/mainboard/amd/tilapia_fam10/mptable.c +++ /dev/null @@ -1,102 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2010 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include -#include -#include - -extern u32 apicid_sb700; - - -static void *smp_write_config_table(void *v) -{ - struct mp_config_table *mc; - int bus_isa; - - mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); - - mptable_init(mc, LOCAL_APIC_ADDR); - - smp_write_processors(mc); - - mptable_write_buses(mc, NULL, &bus_isa); - - /* I/O APICs: APIC ID Version State Address */ - { - struct device *dev; - u32 dword; - u8 byte; - - dev = - dev_find_slot(pirq_router_bus, - PCI_DEVFN(0x14, 0)); - if (dev) { - dword = pci_read_config32(dev, 0x74) & 0xfffffff0; - smp_write_ioapic(mc, apicid_sb700, - 0x11,(void *) dword); - - /* Initialize interrupt mapping */ - /* aza */ - byte = pci_read_config8(dev, 0x63); - byte &= 0xf8; - byte |= 0; /* 0: INTA, ...., 7: INTH */ - pci_write_config8(dev, 0x63, byte); - - /* SATA */ - dword = pci_read_config32(dev, 0xac); - dword &= ~(7 << 26); - dword |= 6 << 26; /* 0: INTA, ...., 7: INTH */ - /* dword |= 1 << 22; PIC and APIC co exists */ - pci_write_config32(dev, 0xac, dword); - - /* - * 00:12.0: PROG SATA : INT F - * 00:13.0: INTA USB_0 - * 00:13.1: INTB USB_1 - * 00:13.2: INTC USB_2 - * 00:13.3: INTD USB_3 - * 00:13.4: INTC USB_4 - * 00:13.5: INTD USB2 - * 00:14.1: INTA IDE - * 00:14.2: Prog HDA : INT E - * 00:14.5: INTB ACI - * 00:14.6: INTB MCI - */ - } - } - - /* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ -#define IO_LOCAL_INT(type, intr, apicid, pin) \ - smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin)); - - mptable_add_isa_interrupts(mc, bus_isa, apicid_sb700, 0); - - /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ - IO_LOCAL_INT(mp_ExtINT, 0x0, MP_APIC_ALL, 0x0); - IO_LOCAL_INT(mp_NMI, 0x0, MP_APIC_ALL, 0x1); - /* There is no extension information... */ - - /* Compute the checksums */ - return mptable_finalize(mc); -} - -unsigned long write_smp_table(unsigned long addr) -{ - void *v; - v = smp_write_floating_table(addr, 0); - return (unsigned long)smp_write_config_table(v); -} diff --git a/src/mainboard/amd/tilapia_fam10/resourcemap.c b/src/mainboard/amd/tilapia_fam10/resourcemap.c deleted file mode 100644 index 2e5c391301..0000000000 --- a/src/mainboard/amd/tilapia_fam10/resourcemap.c +++ /dev/null @@ -1,273 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2010 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include - -void setup_mb_resource_map(void) -{ - static const unsigned int register_values[] = { - /* Careful set limit registers before base registers which contain the enables */ - /* DRAM Limit i Registers - * F1:0x44 i = 0 - * F1:0x4C i = 1 - * F1:0x54 i = 2 - * F1:0x5C i = 3 - * F1:0x64 i = 4 - * F1:0x6C i = 5 - * F1:0x74 i = 6 - * F1:0x7C i = 7 - * [ 2: 0] Destination Node ID - * 000 = Node 0 - * 001 = Node 1 - * 010 = Node 2 - * 011 = Node 3 - * 100 = Node 4 - * 101 = Node 5 - * 110 = Node 6 - * 111 = Node 7 - * [ 7: 3] Reserved - * [10: 8] Interleave select - * specifies the values of A[14:12] to use with interleave enable. - * [15:11] Reserved - * [31:16] DRAM Limit Address i Bits 39-24 - * This field defines the upper address bits of a 40 bit address - * that define the end of the DRAM region. - */ - /* Don't touch it, we need it for CONFIG_CAR_FAM10 */ - ADDRMAP_REG(0x4C), 0x0000f8f8, 0x00000001, - ADDRMAP_REG(0x54), 0x0000f8f8, 0x00000002, - ADDRMAP_REG(0x5C), 0x0000f8f8, 0x00000003, - ADDRMAP_REG(0x64), 0x0000f8f8, 0x00000004, - ADDRMAP_REG(0x6C), 0x0000f8f8, 0x00000005, - ADDRMAP_REG(0x74), 0x0000f8f8, 0x00000006, - ADDRMAP_REG(0x7C), 0x0000f8f8, 0x00000007, - /* DRAM Base i Registers - * F1:0x40 i = 0 - * F1:0x48 i = 1 - * F1:0x50 i = 2 - * F1:0x58 i = 3 - * F1:0x60 i = 4 - * F1:0x68 i = 5 - * F1:0x70 i = 6 - * F1:0x78 i = 7 - * [ 0: 0] Read Enable - * 0 = Reads Disabled - * 1 = Reads Enabled - * [ 1: 1] Write Enable - * 0 = Writes Disabled - * 1 = Writes Enabled - * [ 7: 2] Reserved - * [10: 8] Interleave Enable - * 000 = No interleave - * 001 = Interleave on A[12] (2 nodes) - * 010 = reserved - * 011 = Interleave on A[12] and A[14] (4 nodes) - * 100 = reserved - * 101 = reserved - * 110 = reserved - * 111 = Interleve on A[12] and A[13] and A[14] (8 nodes) - * [15:11] Reserved - * [13:16] DRAM Base Address i Bits 39-24 - * This field defines the upper address bits of a 40-bit address - * that define the start of the DRAM region. - */ - /* don't touch it, we need it for CONFIG_CAR_FAM10 */ - ADDRMAP_REG(0x48), 0x0000f8fc, 0x00000000, - ADDRMAP_REG(0x50), 0x0000f8fc, 0x00000000, - ADDRMAP_REG(0x58), 0x0000f8fc, 0x00000000, - ADDRMAP_REG(0x60), 0x0000f8fc, 0x00000000, - ADDRMAP_REG(0x68), 0x0000f8fc, 0x00000000, - ADDRMAP_REG(0x70), 0x0000f8fc, 0x00000000, - ADDRMAP_REG(0x78), 0x0000f8fc, 0x00000000, - - /* Memory-Mapped I/O Limit i Registers - * F1:0x84 i = 0 - * F1:0x8C i = 1 - * F1:0x94 i = 2 - * F1:0x9C i = 3 - * F1:0xA4 i = 4 - * F1:0xAC i = 5 - * F1:0xB4 i = 6 - * F1:0xBC i = 7 - * [ 2: 0] Destination Node ID - * 000 = Node 0 - * 001 = Node 1 - * 010 = Node 2 - * 011 = Node 3 - * 100 = Node 4 - * 101 = Node 5 - * 110 = Node 6 - * 111 = Node 7 - * [ 3: 3] Reserved - * [ 5: 4] Destination Link ID - * 00 = Link 0 - * 01 = Link 1 - * 10 = Link 2 - * 11 = Reserved - * [ 6: 6] Reserved - * [ 7: 7] Non-Posted - * 0 = CPU writes may be posted - * 1 = CPU writes must be non-posted - * [31: 8] Memory-Mapped I/O Limit Address i (39-16) - * This field defines the upp address bits of a 40-bit address that - * defines the end of a memory-mapped I/O region n - */ - ADDRMAP_REG(0x84), 0x00000048, 0x00000000, - ADDRMAP_REG(0x8C), 0x00000048, 0x00000000, - ADDRMAP_REG(0x94), 0x00000048, 0x00000000, - ADDRMAP_REG(0x9C), 0x00000048, 0x00000000, - ADDRMAP_REG(0xA4), 0x00000048, 0x00000000, - ADDRMAP_REG(0xAC), 0x00000048, 0x00000000, - ADDRMAP_REG(0xB4), 0x00000048, 0x00000000, - - /* Memory-Mapped I/O Base i Registers - * F1:0x80 i = 0 - * F1:0x88 i = 1 - * F1:0x90 i = 2 - * F1:0x98 i = 3 - * F1:0xA0 i = 4 - * F1:0xA8 i = 5 - * F1:0xB0 i = 6 - * F1:0xB8 i = 7 - * [ 0: 0] Read Enable - * 0 = Reads disabled - * 1 = Reads Enabled - * [ 1: 1] Write Enable - * 0 = Writes disabled - * 1 = Writes Enabled - * [ 2: 2] Cpu Disable - * 0 = Cpu can use this I/O range - * 1 = Cpu requests do not use this I/O range - * [ 3: 3] Lock - * 0 = base/limit registers i are read/write - * 1 = base/limit registers i are read-only - * [ 7: 4] Reserved - * [31: 8] Memory-Mapped I/O Base Address i (39-16) - * This field defines the upper address bits of a 40bit address - * that defines the start of memory-mapped I/O region i - */ - ADDRMAP_REG(0x80), 0x000000f0, 0x00000000, - ADDRMAP_REG(0x88), 0x000000f0, 0x00000000, - ADDRMAP_REG(0x90), 0x000000f0, 0x00000000, - ADDRMAP_REG(0x98), 0x000000f0, 0x00000000, - ADDRMAP_REG(0xA0), 0x000000f0, 0x00000000, - ADDRMAP_REG(0xA8), 0x000000f0, 0x00000000, - ADDRMAP_REG(0xB0), 0x000000f0, 0x00000000, - - /* PCI I/O Limit i Registers - * F1:0xC4 i = 0 - * F1:0xCC i = 1 - * F1:0xD4 i = 2 - * F1:0xDC i = 3 - * [ 2: 0] Destination Node ID - * 000 = Node 0 - * 001 = Node 1 - * 010 = Node 2 - * 011 = Node 3 - * 100 = Node 4 - * 101 = Node 5 - * 110 = Node 6 - * 111 = Node 7 - * [ 3: 3] Reserved - * [ 5: 4] Destination Link ID - * 00 = Link 0 - * 01 = Link 1 - * 10 = Link 2 - * 11 = reserved - * [11: 6] Reserved - * [24:12] PCI I/O Limit Address i - * This field defines the end of PCI I/O region n - * [31:25] Reserved - */ - ADDRMAP_REG(0xCC), 0xFE000FC8, 0x00000000, - ADDRMAP_REG(0xD4), 0xFE000FC8, 0x00000000, - ADDRMAP_REG(0xDC), 0xFE000FC8, 0x00000000, - - /* PCI I/O Base i Registers - * F1:0xC0 i = 0 - * F1:0xC8 i = 1 - * F1:0xD0 i = 2 - * F1:0xD8 i = 3 - * [ 0: 0] Read Enable - * 0 = Reads Disabled - * 1 = Reads Enabled - * [ 1: 1] Write Enable - * 0 = Writes Disabled - * 1 = Writes Enabled - * [ 3: 2] Reserved - * [ 4: 4] VGA Enable - * 0 = VGA matches Disabled - * 1 = matches all address < 64K and where A[9:0] is in the - * range 3B0-3BB or 3C0-3DF independen of the base & limit registers - * [ 5: 5] ISA Enable - * 0 = ISA matches Disabled - * 1 = Blocks address < 64K and in the last 768 bytes of eack 1K block - * from matching agains this base/limit pair - * [11: 6] Reserved - * [24:12] PCI I/O Base i - * This field defines the start of PCI I/O region n - * [31:25] Reserved - */ - ADDRMAP_REG(0xC8), 0xFE000FCC, 0x00000000, - ADDRMAP_REG(0xD0), 0xFE000FCC, 0x00000000, - ADDRMAP_REG(0xD8), 0xFE000FCC, 0x00000000, - - /* Config Base and Limit i Registers - * F1:0xE0 i = 0 - * F1:0xE4 i = 1 - * F1:0xE8 i = 2 - * F1:0xEC i = 3 - * [ 0: 0] Read Enable - * 0 = Reads Disabled - * 1 = Reads Enabled - * [ 1: 1] Write Enable - * 0 = Writes Disabled - * 1 = Writes Enabled - * [ 2: 2] Device Number Compare Enable - * 0 = The ranges are based on bus number - * 1 = The ranges are ranges of devices on bus 0 - * [ 3: 3] Reserved - * [ 6: 4] Destination Node - * 000 = Node 0 - * 001 = Node 1 - * 010 = Node 2 - * 011 = Node 3 - * 100 = Node 4 - * 101 = Node 5 - * 110 = Node 6 - * 111 = Node 7 - * [ 7: 7] Reserved - * [ 9: 8] Destination Link - * 00 = Link 0 - * 01 = Link 1 - * 10 = Link 2 - * 11 - Reserved - * [15:10] Reserved - * [23:16] Bus Number Base i - * This field defines the lowest bus number in configuration region i - * [31:24] Bus Number Limit i - * This field defines the highest bus number in configuration regin i - */ - /* AMD 8111 on link0 of CPU 0 */ - ADDRMAP_REG(0xE4), 0x0000FC88, 0x00000000, - ADDRMAP_REG(0xE8), 0x0000FC88, 0x00000000, - ADDRMAP_REG(0xEC), 0x0000FC88, 0x00000000, - }; - - int max; - max = ARRAY_SIZE(register_values); - setup_resource_map(register_values, max); -} diff --git a/src/mainboard/amd/tilapia_fam10/romstage.c b/src/mainboard/amd/tilapia_fam10/romstage.c deleted file mode 100644 index 702e9db9df..0000000000 --- a/src/mainboard/amd/tilapia_fam10/romstage.c +++ /dev/null @@ -1,224 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2010 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#define SYSTEM_TYPE 1 /* DESKTOP */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include "cpu/amd/quadcore/quadcore.c" - -#define SERIAL_DEV PNP_DEV(0x2e, IT8718F_SP1) - -int spd_read_byte(unsigned int device, unsigned int address); - - -int spd_read_byte(u32 device, u32 address) -{ - return do_smbus_read_byte(SMBUS_IO_BASE, device, address); -} - - -void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) -{ - struct sys_info *sysinfo = get_sysinfo(); - static const u8 spd_addr[] = {RC00, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, }; - u32 bsp_apicid = 0, val; - msr_t msr; - - timestamp_init(timestamp_get()); - timestamp_add_now(TS_START_ROMSTAGE); - - if (!cpu_init_detectedx && boot_cpu()) { - /* Nothing special needs to be done to find bus 0 */ - /* Allow the HT devices to be found */ - /* mov bsp to bus 0xff when > 8 nodes */ - set_bsp_node_CHtExtNodeCfgEn(); - enumerate_ht_chain(); - sb7xx_51xx_pci_port80(); - } - - post_code(0x30); - - if (bist == 0) { - bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo); /* mmconf is inited in init_cpus */ - /* All cores run this but the BSP(node0,core0) is the only core that returns. */ - } - - post_code(0x32); - - enable_rs780_dev8(); - sb7xx_51xx_lpc_init(); - - ite_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); - - console_init(); - - /* Halt if there was a built in self test failure */ - report_bist_failure(bist); - - /* Load MPB */ - val = cpuid_eax(1); - printk(BIOS_DEBUG, "BSP Family_Model: %08x\n", val); - printk(BIOS_DEBUG, "*sysinfo range: [%p,%p]\n",sysinfo,sysinfo+1); - printk(BIOS_DEBUG, "bsp_apicid = %02x\n", bsp_apicid); - printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx); - - /* Setup sysinfo defaults */ - set_sysinfo_in_ram(0); - - update_microcode(val); - - post_code(0x33); - - cpuSetAMDMSR(0); - post_code(0x34); - - amd_ht_init(sysinfo); - post_code(0x35); - - /* Setup nodes PCI space and start core 0 AP init. */ - finalize_node_setup(sysinfo); - - /* Setup any mainboard PCI settings etc. */ - setup_mb_resource_map(); - post_code(0x36); - - /* wait for all the APs core0 started by finalize_node_setup. */ - /* FIXME: A bunch of cores are going to start output to serial at once. - It would be nice to fixup prink spinlocks for ROM XIP mode. - I think it could be done by putting the spinlock flag in the cache - of the BSP located right after sysinfo. - */ - wait_all_core0_started(); - -#if CONFIG(LOGICAL_CPUS) - /* Core0 on each node is configured. Now setup any additional cores. */ - printk(BIOS_DEBUG, "start_other_cores()\n"); - start_other_cores(bsp_apicid); - post_code(0x37); - wait_all_other_cores_started(bsp_apicid); -#endif - - post_code(0x38); - - /* run _early_setup before soft-reset. */ - rs780_early_setup(); - sb7xx_51xx_early_setup(); - -#if CONFIG(SET_FIDVID) - msr = rdmsr(MSR_COFVID_STS); - printk(BIOS_DEBUG, "\nBegin FIDVID MSR 0xc0010071 0x%08x 0x%08x\n", msr.hi, msr.lo); - - /* FIXME: The sb fid change may survive the warm reset and only - need to be done once.*/ - enable_fid_change_on_sb(sysinfo->sbbusn, sysinfo->sbdn); - - post_code(0x39); - - if (!warm_reset_detect(0)) { /* BSP is node 0 */ - init_fidvid_bsp(bsp_apicid, sysinfo->nodes); - } else { - init_fidvid_stage2(bsp_apicid, 0); /* BSP is node 0 */ - } - - post_code(0x3A); - - /* show final fid and vid */ - msr = rdmsr(MSR_COFVID_STS); - printk(BIOS_DEBUG, "End FIDVIDMSR 0xc0010071 0x%08x 0x%08x\n", msr.hi, msr.lo); -#endif - - rs780_htinit(); - - /* Reset for HT, FIDVID, PLL and errata changes to take affect. */ - if (!warm_reset_detect(0)) { - printk(BIOS_INFO, "...WARM RESET...\n\n\n"); - soft_reset(); - die("After soft_reset - shouldn't see this message!!!\n"); - } - - post_code(0x3B); - - /* It's the time to set ctrl in sysinfo now; */ - printk(BIOS_DEBUG, "fill_mem_ctrl()\n"); - fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr); - - post_code(0x40); - - raminit_amdmct(sysinfo); - - cbmem_initialize_empty(); - post_code(0x41); - - amdmct_cbmem_store_info(sysinfo); - - sb7xx_51xx_before_pci_init(); - - post_code(0x42); -} - -/** - * BOOL AMD_CB_ManualBUIDSwapList(u8 Node, u8 Link, u8 **List) - * Description: - * This routine is called every time a non-coherent chain is processed. - * BUID assignment may be controlled explicitly on a non-coherent chain. Provide a - * swap list. The first part of the list controls the BUID assignment and the - * second part of the list provides the device to device linking. Device orientation - * can be detected automatically, or explicitly. See documentation for more details. - * - * Automatic non-coherent init assigns BUIDs starting at 1 and incrementing sequentially - * based on each device's unit count. - * - * Parameters: - * @param[in] node = The node on which this chain is located - * @param[in] link = The link on the host for this chain - * @param[out] List = supply a pointer to a list - */ -BOOL AMD_CB_ManualBUIDSwapList (u8 node, u8 link, const u8 **List) -{ - static const u8 swaplist[] = { 0xFF, CONFIG_HT_CHAIN_UNITID_BASE, CONFIG_HT_CHAIN_END_UNITID_BASE, 0xFF }; - /* If the BUID was adjusted in early_ht we need to do the manual override */ - if ((CONFIG_HT_CHAIN_UNITID_BASE != 0) && (CONFIG_HT_CHAIN_END_UNITID_BASE != 0)) { - printk(BIOS_DEBUG, "AMD_CB_ManualBUIDSwapList()\n"); - if ((node == 0) && (link == 0)) { /* BSP SB link */ - *List = swaplist; - return 1; - } - } - - return 0; -} diff --git a/src/mainboard/asus/kcma-d8/Kconfig b/src/mainboard/asus/kcma-d8/Kconfig deleted file mode 100644 index d568ff579b..0000000000 --- a/src/mainboard/asus/kcma-d8/Kconfig +++ /dev/null @@ -1,96 +0,0 @@ -if BOARD_ASUS_KCMA_D8 - -config BOARD_SPECIFIC_OPTIONS - def_bool y - select CPU_AMD_SOCKET_C32_NON_AGESA - select DIMM_DDR3 - select DIMM_REGISTERED - # select QRANK_DIMM_SUPPORT - select DIMM_VOLTAGE_SET_SUPPORT - select NORTHBRIDGE_AMD_AMDFAM10 - select SOUTHBRIDGE_AMD_SR5650 - select SOUTHBRIDGE_AMD_SB700 - select SOUTHBRIDGE_AMD_SB700_DISABLE_ISA_DMA - select SOUTHBRIDGE_AMD_SUBTYPE_SP5100 - select SUPERIO_WINBOND_W83667HG_A - select PARALLEL_CPU_INIT - select HAVE_ROMSTAGE_CONSOLE_SPINLOCK - select HAVE_ROMSTAGE_NVRAM_CBFS_SPINLOCK - select HAVE_ROMSTAGE_MICROCODE_CBFS_SPINLOCK - select HAVE_OPTION_TABLE - select HAVE_CMOS_DEFAULT - select HAVE_PIRQ_TABLE - select HAVE_MP_TABLE - select HAVE_ACPI_TABLES - select SB_HT_CHAIN_UNITID_OFFSET_ONLY - select LIFT_BSP_APIC_ID - select BOARD_ROMSIZE_KB_2048 - select ENABLE_APIC_EXT_ID - select SPI_FLASH - select DRIVERS_I2C_W83795 - select DRIVERS_ASPEED_AST2050 - select MAINBOARD_FORCE_NATIVE_VGA_INIT - select POWER_STATE_DEFAULT_ON_AFTER_FAILURE - -config MAINBOARD_DIR - string - default "asus/kcma-d8" - -config BOOTBLOCK_MAINBOARD_INIT - string - default "mainboard/asus/kcma-d8/bootblock.c" - -config DCACHE_RAM_BASE - hex - default 0xc2000 - -config DCACHE_RAM_SIZE - hex - default 0x1e000 - -config APIC_ID_OFFSET - hex - default 0x0 - -config MAINBOARD_PART_NUMBER - string - default "KCMA-D8" - -config HW_MEM_HOLE_SIZEK - hex - default 0x100000 - -config MAX_CPUS - int - default 16 - -# 1 (internal) processor per C32 socket -config MAX_PHYSICAL_CPUS - int - default 2 - -config HT_CHAIN_UNITID_BASE - hex - default 0x0 - -config HT_CHAIN_END_UNITID_BASE - hex - default 0x20 - -config IRQ_SLOT_COUNT - int - default 13 - -config SOUTHBRIDGE_AMD_SB700_SATA_PORT_COUNT_BITFIELD - hex - default 0x3f - -config ONBOARD_VGA_IS_PRIMARY - bool - default y - -config MAX_REBOOT_CNT - int - default 10 - -endif # BOARD_ASUS_KCMA_D8 diff --git a/src/mainboard/asus/kcma-d8/Kconfig.name b/src/mainboard/asus/kcma-d8/Kconfig.name deleted file mode 100644 index 69b63ead39..0000000000 --- a/src/mainboard/asus/kcma-d8/Kconfig.name +++ /dev/null @@ -1,2 +0,0 @@ -config BOARD_ASUS_KCMA_D8 - bool "KCMA-D8" diff --git a/src/mainboard/asus/kcma-d8/Makefile.inc b/src/mainboard/asus/kcma-d8/Makefile.inc deleted file mode 100644 index 91d4b39c32..0000000000 --- a/src/mainboard/asus/kcma-d8/Makefile.inc +++ /dev/null @@ -1,16 +0,0 @@ -# -# This file is part of the coreboot project. -# -# This program is free software; you can redistribute it and/or modify -# it under the terms of the GNU General Public License as published by -# the Free Software Foundation; version 2 of the License. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# - -romstage-y += resourcemap.c - -ramstage-y += get_bus_conf.c diff --git a/src/mainboard/asus/kcma-d8/acpi/pm_ctrl.asl b/src/mainboard/asus/kcma-d8/acpi/pm_ctrl.asl deleted file mode 100644 index ee49daeaab..0000000000 --- a/src/mainboard/asus/kcma-d8/acpi/pm_ctrl.asl +++ /dev/null @@ -1,368 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2015 Raptor Engineering - * Copyright (C) 2009 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -/* Port 80 POST card debug */ -OperationRegion (DBG0, SystemIO, 0x80, One) - Field (DBG0, ByteAcc, NoLock, Preserve) { - DBG8, 8 -} - -/* SuperIO control port */ -Name (SPIO, 0x2E) - -/* SuperIO control map */ -OperationRegion (SPIM, SystemIO, SPIO, 0x02) - Field (SPIM, ByteAcc, NoLock, Preserve) { - INDX, 8, - DATA, 8 -} - -/* SuperIO control registers */ -IndexField (INDX, DATA, ByteAcc, NoLock, Preserve) { - Offset (0x07), - CR07, 8, /* Logical device number */ - Offset (0x2C), - CR2C, 8, /* GPIO3 multiplexed pin selection */ - Offset (0x30), - CR30, 8, /* Logical device activation control register */ - Offset (0xE0), - CRE0, 8, /* Wake control register */ - Offset (0xE4), - CRE4, 8, /* Standby power control register */ - Offset (0xE6), - CRE6, 8, /* Mouse wake event configuration register */ - Offset (0xF1), - CRF1, 8, /* GPIO3 data register */ - Offset (0xF3), - CRF3, 8, /* SUSLED mode register */ - Offset (0xF6), - CRF6, 8, /* SMI/PME event generation control register */ - Offset (0xF9), - CRF9, 8, /* ACPI PME configuration register */ -} - -/* Power Management I/O registers */ -OperationRegion(PIOR, SystemIO, 0x00000CD6, 0x00000002) - Field(PIOR, ByteAcc, NoLock, Preserve) { - PIOI, 0x00000008, - PIOD, 0x00000008, -} -IndexField (PIOI, PIOD, ByteAcc, NoLock, Preserve) { - Offset(0x00), /* MiscControl */ - , 1, - T1EE, 1, - T2EE, 1, - Offset(0x01), /* MiscStatus */ - , 1, - T1E, 1, - T2E, 1, - Offset(0x04), /* SmiWakeUpEventEnable3 */ - , 7, - SSEN, 1, - Offset(0x07), /* SmiWakeUpEventStatus3 */ - , 7, - CSSM, 1, - Offset(0x10), /* AcpiEnable */ - , 6, - PWDE, 1, - Offset(0x1C), /* ProgramIoEnable */ - , 3, - MKME, 1, - IO3E, 1, - IO2E, 1, - IO1E, 1, - IO0E, 1, - Offset(0x1D), /* IOMonitorStatus */ - , 3, - MKMS, 1, - IO3S, 1, - IO2S, 1, - IO1S, 1, - IO0S,1, - Offset(0x20), /* AcpiPmEvtBlk */ - APEB, 16, - Offset(0x36), /* GEvtLevelConfig */ - , 6, - ELC6, 1, - ELC7, 1, - Offset(0x37), /* GPMLevelConfig0 */ - , 3, - PLC0, 1, - PLC1, 1, - PLC2, 1, - PLC3, 1, - PLC8, 1, - Offset(0x38), /* GPMLevelConfig1 */ - , 1, - PLC4, 1, - PLC5, 1, - , 1, - PLC6, 1, - PLC7, 1, - Offset(0x3B), /* PMEStatus1 */ - GP0S, 1, - GM4S, 1, - GM5S, 1, - APS, 1, - GM6S, 1, - GM7S, 1, - GP2S, 1, - STSS, 1, - Offset(0x55), /* SoftPciRst */ - SPRE, 1, - , 1, - , 1, - PNAT, 1, - PWMK, 1, - PWNS, 1, - - /* Offset(0x61), */ /* Options_1 */ - /* ,7, */ - /* R617,1, */ - - Offset(0x65), /* UsbPMControl */ - , 4, - URRE, 1, - , 2, - BCDL, 1, - Offset(0x68), /* MiscEnable68 */ - , 2, - MAPC, 1, - TMTE, 1, - , 1, - Offset(0x7C), /* MiscEnable7C */ - , 2, - BLNK, 2, - Offset(0x92), /* GEVENTIN */ - , 7, - E7IS, 1, - Offset(0x96), /* GPM98IN */ - G8IS, 1, - G9IS, 1, - Offset(0x9A), /* EnhanceControl */ - ,7, - HPDE, 1, - Offset(0xA8), /* PIO7654Enable */ - IO4E, 1, - IO5E, 1, - IO6E, 1, - IO7E, 1, - Offset(0xA9), /* PIO7654Status */ - IO4S, 1, - IO5S, 1, - IO6S, 1, - IO7S, 1, -} - -/* PM1 Event Block - * First word is PM1_Status, Second word is PM1_Enable - */ -OperationRegion(P1EB, SystemIO, APEB, 0x04) - Field(P1EB, ByteAcc, NoLock, Preserve) { - TMST, 1, - , 3, - BMST, 1, - GBST, 1, - Offset(0x01), - PBST, 1, - , 1, - RTST, 1, - , 3, - PWST, 1, - SPWS, 1, - Offset(0x02), - TMEN, 1, - , 4, - GBEN, 1, - Offset(0x03), - PBEN, 1, - , 1, - RTEN, 1, - , 3, - PWDA, 1, -} - -/* Wake status package */ -Name(WKST,Package() {Zero, Zero}) - -/* - * \_WAK System Wake method - * - * Entry: - * Arg0=The value of the sleeping state S1=1, S2=2 - * - * Exit: - * Return package of 2 DWords - * Dword 1 - Status - * 0x00000000 wake succeeded - * 0x00000001 Wake was signaled but failed due to lack of power - * 0x00000002 Wake was signaled but failed due to thermal condition - * Dword 2 - Power Supply state - * if non-zero the effective S-state the power supply entered - */ -Method(\_WAK, 1) { - Store (0x20, DBG8) - - /* Set up LEDs */ - /* Set power LED to steady on */ - Store(0x0, BLNK) - - /* Configure SuperIO for wake */ - /* Access SuperIO ACPI device */ - Store(0x87, INDX) - Store(0x87, INDX) - Store(0x0A, CR07) - - if (LEqual(Arg0, One)) /* Resuming from power state S1 */ - { - /* Deactivate the ACPI device */ - Store(Zero, CR30) - - /* Disable PS/2 SMI/PME events */ - And(CRF6, 0xCF, CRF6) - } - if (Lor(LEqual(Arg0, 0x03), LEqual(Arg0, 0x04))) /* Resuming from power state S3 or S4 */ - { - /* Disable PS/2 wake */ - And(CRE0, 0x1D, CRE0) - And(CRE6, 0x7F, CRE6) - } - - /* Restore default SuperIO access */ - Store(0xAA, INDX) - - Store (0x21, DBG8) - - /* Re-enable HPET */ - Store(1, HPDE) - - /* Restore PCIRST# so it resets USB */ - if (LEqual(Arg0, 3)){ - Store(1, URRE) - } - - /* Configure southbridge for wake */ - /* Arbitrarily clear PciExpWakeStatus */ - Store(PWST, Local1) - Store(Local1, PWST) - - Store (0x22, DBG8) - - Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ - - Return(WKST) -} - -/* - * \_PTS - Prepare to Sleep method - * - * Entry: - * Arg0=The value of the sleeping state S1=1, S2=2, etc - * - * Exit: - * -none- - * - * The _PTS control method is executed at the beginning of the sleep process - * for S1-S5. The sleeping value is passed to the _PTS control method. This - * control method may be executed a relatively long time before entering the - * sleep state and the OS may abort the operation without notification to - * the ACPI driver. This method cannot modify the configuration or power - * state of any device in the system. - */ -Method(\_PTS, 1) { - Store (Arg0, DBG8) - - /* Set up LEDs */ - if (LEqual(Arg0, One)) /* Power state S1 requested */ - { - /* Set suspend LED to 0.25Hz toggle pulse with 50% duty cycle */ - Store(0x2, BLNK) - } - - /* Configure SuperIO for sleep */ - /* Access SuperIO ACPI device */ - Store(0x87, INDX) - Store(0x87, INDX) - Store(0x0A, CR07) - - /* Disable PS/2 wakeup and connect PANSW_IN to PANSW_OUT */ - And(CRE0, 0x1F, CRE0) - - if (LEqual(Arg0, One)) /* Power state S1 requested */ - { - /* Activate the ACPI device */ - Store(One, CR30) - - /* Disable SMI/PME events for: - * LPT - * FDC - * UART - */ - Store(0x00, CRF6) - - /* Enable PS/2 keyboard SMI/PME events */ - Or(CRF6, 0x10, CRF6) - - /* Enable PS/2 keyboard wake */ - Or(CRE0, 0x40, CRE0) - - /* Enable PS/2 mouse SMI/PME events */ - Or(CRF6, 0x20, CRF6) - - /* Enable PS/2 mouse wake */ - Or(CRE0, 0x20, CRE0) - } else { - /* Enable PS/2 keyboard wake on any keypress */ - Or(CRE0, 0x41, CRE0) - - /* Enable PS/2 mouse wake on any click */ - Or(CRE0, 0x22, CRE0) - Or(CRE6, 0x80, CRE6) - - if (LEqual(Arg0, 0x03)) /* Power state S3 requested */ - { - /* Set VSBGATE# to provide standby power during S3 */ - Or(CRE4, 0x10, CRE4) - } - } - - /* Restore default SuperIO access */ - Store(0xAA, INDX) - - Store (0x10, DBG8) - - /* Don't allow PCIRST# to reset USB */ - if (LEqual(Arg0, 3)){ - Store(0, URRE) - } - - /* Configure southbridge for sleep */ - /* Use bus clock for delay timebase */ - Store(0, BCDL) - /* Defer APIC interrupts until first ACPI access */ - Store(One, MAPC) - - /* On older chips, clear PciExpWakeDisEn */ - // if (LLessEqual(SBRI, 0x13)) { - // Store(0, PWDE) - // } - - Store (0x11, DBG8) - - /* Clear wake status structure. */ - Store(0, Index(WKST,0)) - Store(0, Index(WKST,1)) -} diff --git a/src/mainboard/asus/kcma-d8/acpi_tables.c b/src/mainboard/asus/kcma-d8/acpi_tables.c deleted file mode 100644 index 53622bae0c..0000000000 --- a/src/mainboard/asus/kcma-d8/acpi_tables.c +++ /dev/null @@ -1,103 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2010 Advanced Micro Devices, Inc. - * Copyright (C) 2015 Timothy Pearson , Raptor Engineering - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include -#include -#include - -unsigned long acpi_fill_madt(unsigned long current) -{ - struct device *dev; - u32 dword; - u32 gsi_base = 0; - uint32_t apicid_sp5100; - uint32_t apicid_sr5650; - /* create all subtables for processors */ - current = acpi_create_madt_lapics(current); - - if (CONFIG(ENABLE_APIC_EXT_ID) && (CONFIG_APIC_ID_OFFSET > 0)) - apicid_sp5100 = 0x0; - else - apicid_sp5100 = 0x20; - apicid_sr5650 = apicid_sp5100 + 1; - - /* Write SB700 IOAPIC, only one */ - current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, apicid_sp5100, - IO_APIC_ADDR, gsi_base); - /* IOAPIC on rs5690 */ - gsi_base += 24; /* SB700 has 24 IOAPIC entries. */ - dev = pcidev_on_root(0, 0); - if (dev) { - pci_write_config32(dev, 0xF8, 0x1); - dword = pci_read_config32(dev, 0xFC) & 0xfffffff0; - current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, apicid_sr5650, - dword, gsi_base); - } - - /* bus, source, gsirq, flags */ - current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) - current, 0, 0, 2, 0); - current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) - current, 0, 9, 9, 0xf); - - /* create all subtables for processors */ - current += acpi_create_madt_lapic_nmi((acpi_madt_lapic_nmi_t *)current, 0xff, 0, 1); - /* 1: LINT1 connect to NMI */ - - return current; -} - -unsigned long acpi_fill_ivrs_ioapic(acpi_ivrs_t *ivrs, unsigned long current) -{ - uint8_t *p; - - uint32_t apicid_sp5100; - uint32_t apicid_sr5650; - - if (CONFIG(ENABLE_APIC_EXT_ID) && (CONFIG_APIC_ID_OFFSET > 0)) - apicid_sp5100 = 0x0; - else - apicid_sp5100 = 0x20; - apicid_sr5650 = apicid_sp5100 + 1; - - /* Describe NB IOAPIC */ - p = (uint8_t *)current; - p[0] = 0x48; /* Entry type */ - p[1] = 0; /* Device */ - p[2] = 0; /* Bus */ - p[3] = 0x0; /* Data */ - p[4] = apicid_sr5650; /* IOAPIC ID */ - p[5] = 0x1; /* Device 0 Function 1 */ - p[6] = 0x0; /* Northbridge bus */ - p[7] = 0x1; /* Variety */ - current += 8; - - /* Describe SB IOAPIC */ - p = (uint8_t *)current; - p[0] = 0x48; /* Entry type */ - p[1] = 0; /* Device */ - p[2] = 0; /* Bus */ - p[3] = 0xd7; /* Data */ - p[4] = apicid_sp5100; /* IOAPIC ID */ - p[5] = 0x14 << 3; /* Device 0x14 Function 0 */ - p[6] = 0x0; /* Southbridge bus */ - p[7] = 0x1; /* Variety */ - current += 8; - - return current; -} diff --git a/src/mainboard/asus/kcma-d8/board_info.txt b/src/mainboard/asus/kcma-d8/board_info.txt deleted file mode 100644 index e69d31aab1..0000000000 --- a/src/mainboard/asus/kcma-d8/board_info.txt +++ /dev/null @@ -1,5 +0,0 @@ -Category: server -ROM package: DIP-8 -ROM protocol: SPI -ROM socketed: y -Flashrom support: y diff --git a/src/mainboard/asus/kcma-d8/bootblock.c b/src/mainboard/asus/kcma-d8/bootblock.c deleted file mode 100644 index 543ffed9c7..0000000000 --- a/src/mainboard/asus/kcma-d8/bootblock.c +++ /dev/null @@ -1,52 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2015 Timothy Pearson , Raptor Engineering - * Copyright (C) 2014 Edward O'Callaghan - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include - -void bootblock_mainboard_init(void) -{ - uint8_t recovery_enabled; - unsigned char addr; - unsigned char byte; - - bootblock_northbridge_init(); - bootblock_southbridge_init(); - - /* Recovery jumper is connected to SP5100 GPIO61, and clears the GPIO when placed in the Recovery position */ - byte = pci_io_read_config8(PCI_DEV(0, 0x14, 0), 0x56); - byte |= 0x1 << 4; /* Set GPIO61 to input mode */ - pci_io_write_config8(PCI_DEV(0, 0x14, 0), 0x56, byte); - recovery_enabled = (!(pci_io_read_config8(PCI_DEV(0, 0x14, 0), 0x57) & 0x1)); - if (recovery_enabled) { -#if CONFIG(USE_OPTION_TABLE) - /* Clear NVRAM checksum */ - for (addr = LB_CKS_RANGE_START; addr <= LB_CKS_RANGE_END; addr++) { - cmos_write(0x0, addr); - } - - /* Set fallback boot */ - byte = cmos_read(RTC_BOOT_BYTE); - byte &= 0xfc; - cmos_write(byte, RTC_BOOT_BYTE); -#else - /* FIXME - * Figure out how to recover if the option table is not available - */ -#endif - } -} diff --git a/src/mainboard/asus/kcma-d8/cmos.default b/src/mainboard/asus/kcma-d8/cmos.default deleted file mode 100644 index 306687157f..0000000000 --- a/src/mainboard/asus/kcma-d8/cmos.default +++ /dev/null @@ -1,29 +0,0 @@ -debug_level=Debug -multi_core=Enable -slow_cpu=off -compute_unit_siblings=Enable -iommu=Enable -nmi=Disable -hypertransport_speed_limit=Auto -max_mem_clock=DDR3-1600 -minimum_memory_voltage=1.5V -dimm_spd_checksum=Enforce -ECC_memory=Enable -ECC_redirection=Enable -ecc_scrub_rate=1.28us -interleave_chip_selects=Enable -interleave_nodes=Disable -interleave_memory_channels=Enable -cpu_c_states=Enable -cpu_cc6_state=Enable -cpu_core_boost=Enable -sata_ahci_mode=Enable -sata_alpm=Disable -maximum_p_state_limit=0xf -probe_filter=Auto -l3_cache_partitioning=Disable -gart=Enable -ehci_async_data_cache=Enable -experimental_memory_speed_boost=Disable -power_on_after_fail=On -boot_option=Fallback diff --git a/src/mainboard/asus/kcma-d8/cmos.layout b/src/mainboard/asus/kcma-d8/cmos.layout deleted file mode 100644 index 4ce870f70e..0000000000 --- a/src/mainboard/asus/kcma-d8/cmos.layout +++ /dev/null @@ -1,149 +0,0 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2015 Timothy Pearson , Raptor Engineering -## Copyright (C) 2007 AMD -## Written by Yinghai Lu for AMD. -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; either version 2 of the License, or -## (at your option) any later version. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## - -entries - -0 384 r 0 reserved_memory -384 1 e 4 boot_option -388 4 h 0 reboot_counter -393 3 r 0 unused -#394 7 unused -401 1 e 1 interleave_chip_selects -402 1 e 1 interleave_nodes -403 1 e 1 interleave_memory_channels -404 4 e 8 max_mem_clock -408 1 e 2 multi_core -412 4 e 6 debug_level -416 5 e 10 ecc_scrub_rate -440 4 e 9 slow_cpu -444 1 e 1 nmi -445 1 e 1 gart -446 2 e 3 power_on_after_fail -456 1 e 1 ECC_memory -457 1 e 1 ECC_redirection -458 4 e 11 hypertransport_speed_limit -462 2 e 12 minimum_memory_voltage -464 1 e 2 compute_unit_siblings -465 1 e 1 cpu_c_states -466 1 e 1 cpu_cc6_state -467 1 e 1 sata_ahci_mode -468 1 e 1 sata_alpm -#469 4 unused -473 2 e 13 dimm_spd_checksum -475 1 e 14 probe_filter -476 1 e 1 l3_cache_partitioning -478 1 e 1 iommu -479 1 e 1 cpu_core_boost -480 1 e 2 ehci_async_data_cache -481 1 e 1 experimental_memory_speed_boost -482 1 r 0 allow_spd_nvram_cache_restore -483 4 h 0 maximum_p_state_limit -728 256 h 0 user_data -984 16 h 0 check_sum -# Reserve the extended AMD configuration registers -1000 24 r 0 amd_reserved - - - -enumerations - -#ID value text -1 0 Disable -1 1 Enable -2 0 Enable -2 1 Disable -3 0 Off -3 1 On -3 2 Last -4 0 Fallback -4 1 Normal -6 0 Emergency -6 1 Alert -6 2 Critical -6 3 Error -6 4 Warning -6 5 Notice -6 6 Information -6 7 Debug -6 8 Spew -8 0 DDR3-1866 -8 1 DDR3-1600 -8 2 DDR3-1333 -8 3 DDR3-1066 -8 4 DDR3-800 -8 5 DDR3-667 -9 0 off -9 1 87.5% -9 2 75.0% -9 3 62.5% -9 4 50.0% -9 5 37.5% -9 6 25.0% -9 7 12.5% -10 0 Disabled -10 1 40ns -10 2 80ns -10 3 160ns -10 4 320ns -10 5 640ns -10 6 1.28us -10 7 2.56us -10 8 5.12us -10 9 10.2us -10 10 20.5us -10 11 41us -10 12 81.9us -10 13 163.8us -10 14 327.7us -10 15 655.4us -10 16 1.31ms -10 17 2.62ms -10 18 5.24ms -10 19 10.49ms -10 20 20.97ms -10 21 42ms -10 22 84ms -11 0 Auto -11 1 3.2GHz -11 2 3.0GHz -11 3 2.8GHz -11 4 2.6GHz -11 5 2.4GHz -11 6 2.2GHz -11 7 2.0GHz -11 8 1.8GHz -11 9 1.6GHz -11 10 1.4GHz -11 11 1.2GHz -11 12 1.0GHz -11 13 800MHz -11 14 600MHz -11 15 500MHz -12 0 1.5V -12 1 1.35V -12 2 1.25V -12 3 1.15V -13 0 Enforce -13 1 Ignore -13 2 Override -14 0 Disable -14 1 Auto - -checksums - -checksum 392 983 984 diff --git a/src/mainboard/asus/kcma-d8/devicetree.cb b/src/mainboard/asus/kcma-d8/devicetree.cb deleted file mode 100644 index f8a2d832d3..0000000000 --- a/src/mainboard/asus/kcma-d8/devicetree.cb +++ /dev/null @@ -1,239 +0,0 @@ -chip northbridge/amd/amdfam10/root_complex # Root complex - device cpu_cluster 0 on # (L)APIC cluster - chip cpu/amd/socket_F_1207 # CPU socket - device lapic 0 on end # Local APIC of the CPU - end - end - device domain 0 on # PCI domain - subsystemid 0x1043 0x8163 inherit - chip northbridge/amd/amdfam10 # Northbridge / RAM controller - register "maximum_memory_capacity" = "0x2000000000" # 128GB - device pci 18.0 on end # Link 0 == LDT 0 - device pci 18.0 on end # Link 1 == LDT 1 - device pci 18.0 on # Link 2 == LDT 2 [SB on link 2] - chip southbridge/amd/sr5650 # Primary southbridge - device pci 0.0 on end # HT Root Complex 0x9600 - device pci 0.1 on end # CLKCONFIG - device pci 0.2 on end # IOMMU - device pci 2.0 on # PCIE P2P bridge 0x9603 (GPP1 Port0) - # Slot # PCI E 1 / PCI E 2 - end - device pci 3.0 off end # PCIE P2P bridge 0x960b (GPP1 Port1) - device pci 4.0 on # PCIE P2P bridge 0x9604 (GPP3a Port0) - # PIKE SAS - end - device pci 5.0 off end # PCIE P2P bridge 0x9605 (GPP3a Port1) - device pci 6.0 off end # PCIE P2P bridge 0x9606 (GPP3a Port2) - device pci 7.0 off end # PCIE P2P bridge 0x9607 (GPP3a Port3) - device pci 8.0 off end # NB/SB Link P2P bridge - device pci 9.0 on # Bridge (GPP3a Port4) - # Onboard # NIC A - end - device pci a.0 on # Bridge (GPP3a Port5) - # Onboard # NIC B - end - device pci b.0 on # Bridge (GPP2 Port0) - # Slot # PCI E 4 - end - register "gpp1_configuration" = "0" # Configuration 16:0 default - register "gpp2_configuration" = "1" # Configuration 8:8 - register "gpp3a_configuration" = "2" # Configuration 4:1:1:0:0:0 - register "port_enable" = "0x0f1c" # Enable all ports except 0, 1, 5, 6, and 7 - register "pcie_settling_time" = "1000000" # Allow PIKE to be detected / configured - end - chip southbridge/amd/sb700 # Secondary southbridge - device pci 11.0 on end # SATA - device pci 12.0 on end # USB - device pci 12.1 on end # USB - device pci 12.2 on end # USB - device pci 13.0 on end # USB - device pci 13.1 on end # USB - device pci 13.2 on end # USB - device pci 14.0 on # SM - chip drivers/generic/generic # DIMM n-0-0-0 - device i2c 50 on end - end - chip drivers/generic/generic # DIMM n-0-0-1 - device i2c 51 on end - end - chip drivers/generic/generic # DIMM n-0-1-0 - device i2c 52 on end - end - chip drivers/generic/generic # DIMM n-0-1-1 - device i2c 53 on end - end - chip drivers/generic/generic # DIMM n-1-0-0 - device i2c 54 on end - end - chip drivers/generic/generic # DIMM n-1-0-1 - device i2c 55 on end - end - chip drivers/generic/generic # DIMM n-1-1-0 - device i2c 56 on end - end - chip drivers/generic/generic # DIMM n-1-1-1 - device i2c 57 on end - end - chip drivers/i2c/w83795 - register "fanin_ctl1" = "0xff" # Enable monitoring of FANIN1 - FANIN8 - register "fanin_ctl2" = "0x00" # Connect FANIN11 - FANIN14 to alternate functions - register "temp_ctl1" = "0x2a" # Enable monitoring of DTS, VSEN12, and VSEN13 - register "temp_ctl2" = "0x01" # Enable monitoring of TD1/TR1 - register "temp_dtse" = "0x03" # Enable DTS1 and DTS2 - register "volt_ctl1" = "0xff" # Enable monitoring of VSEN1 - VSEN8 - register "volt_ctl2" = "0xf7" # Enable monitoring of VSEN9 - VSEN11, 3VDD, 3VSB, and VBAT - register "temp1_fan_select" = "0x00" # All fans to manual mode (no dependence on Temp1) - register "temp2_fan_select" = "0x00" # All fans to manual mode (no dependence on Temp2) - register "temp3_fan_select" = "0x00" # All fans to manual mode (no dependence on Temp3) - register "temp4_fan_select" = "0x00" # All fans to manual mode (no dependence on Temp4) - register "temp5_fan_select" = "0x00" # All fans to manual mode (no dependence on Temp5) - register "temp6_fan_select" = "0x00" # All fans to manual mode (no dependence on Temp6) - register "temp1_source_select" = "0x00" # Use TD1/TR1 as data source for Temp1 - register "temp2_source_select" = "0x00" # Use TD2/TR2 as data source for Temp2 - register "temp3_source_select" = "0x00" # Use TD3/TR3 as data source for Temp3 - register "temp4_source_select" = "0x00" # Use TD4/TR4 as data source for Temp4 - register "temp5_source_select" = "0x00" # Use TR5 as data source for Temp5 - register "temp6_source_select" = "0x00" # Use TR6 as data source for Temp6 - register "tr1_critical_temperature" = "85" # Set TD1/TR1 critical temperature to 85°C - register "tr1_critical_hysteresis" = "80" # Set TD1/TR1 critical hysteresis temperature to 80°C - register "tr1_warning_temperature" = "70" # Set TD1/TR1 warning temperature to 70°C - register "tr1_warning_hysteresis" = "65" # Set TD1/TR1 warning hysteresis temperature to 65°C - register "dts_critical_temperature" = "85" # Set DTS (CPU) critical temperature to 85°C - register "dts_critical_hysteresis" = "80" # Set DTS (CPU) critical hysteresis temperature to 80°C - register "dts_warning_temperature" = "70" # Set DTS (CPU) warning temperature to 70°C - register "dts_warning_hysteresis" = "65" # Set DTS (CPU) warning hysteresis temperature to 65°C - register "temp1_critical_temperature" = "80" # Set Temp1 critical temperature to 80°C - register "temp2_critical_temperature" = "80" # Set Temp1 critical temperature to 80°C - register "temp3_critical_temperature" = "80" # Set Temp1 critical temperature to 80°C - register "temp4_critical_temperature" = "80" # Set Temp1 critical temperature to 80°C - register "temp5_critical_temperature" = "80" # Set Temp1 critical temperature to 80°C - register "temp6_critical_temperature" = "80" # Set Temp1 critical temperature to 80°C - register "temp1_target_temperature" = "80" # Set Temp1 target temperature to 80°C - register "temp2_target_temperature" = "80" # Set Temp1 target temperature to 80°C - register "temp3_target_temperature" = "80" # Set Temp1 target temperature to 80°C - register "temp4_target_temperature" = "80" # Set Temp1 target temperature to 80°C - register "temp5_target_temperature" = "80" # Set Temp1 target temperature to 80°C - register "temp6_target_temperature" = "80" # Set Temp1 target temperature to 80°C - register "fan1_nonstop" = "7" # Set Fan 1 minimum speed - register "fan2_nonstop" = "7" # Set Fan 2 minimum speed - register "fan3_nonstop" = "7" # Set Fan 3 minimum speed - register "fan4_nonstop" = "7" # Set Fan 4 minimum speed - register "fan5_nonstop" = "7" # Set Fan 5 minimum speed - register "fan6_nonstop" = "7" # Set Fan 6 minimum speed - register "fan7_nonstop" = "7" # Set Fan 7 minimum speed - register "fan8_nonstop" = "7" # Set Fan 8 minimum speed - register "default_speed" = "100" # All fans to full speed on power up - register "fan1_duty" = "100" # Fan 1 to full speed - register "fan2_duty" = "100" # Fan 2 to full speed - register "fan3_duty" = "100" # Fan 3 to full speed - register "fan4_duty" = "100" # Fan 4 to full speed - register "fan5_duty" = "100" # Fan 5 to full speed - register "fan6_duty" = "100" # Fan 6 to full speed - register "fan7_duty" = "100" # Fan 7 to full speed - register "fan8_duty" = "100" # Fan 8 to full speed - register "vcore1_high_limit_mv" = "1500" # VCORE1 (Node 0) high limit to 1.5V - register "vcore1_low_limit_mv" = "900" # VCORE1 (Node 0) low limit to 0.9V - register "vcore2_high_limit_mv" = "1500" # VCORE2 (Node 1) high limit to 1.5V - register "vcore2_low_limit_mv" = "900" # VCORE2 (Node 1) low limit to 0.9V - register "vsen3_high_limit_mv" = "1600" # VSEN1 (Node 0 RAM voltage) high limit to 1.6V - register "vsen3_low_limit_mv" = "1100" # VSEN1 (Node 0 RAM voltage) low limit to 1.1V - register "vsen4_high_limit_mv" = "1600" # VSEN2 (Node 1 RAM voltage) high limit to 1.6V - register "vsen4_low_limit_mv" = "1100" # VSEN2 (Node 1 RAM voltage) low limit to 1.1V - register "vsen5_high_limit_mv" = "1250" # VSEN5 (Node 0 HT link voltage) high limit to 1.25V - register "vsen5_low_limit_mv" = "1150" # VSEN5 (Node 0 HT link voltage) low limit to 1.15V - register "vsen6_high_limit_mv" = "1250" # VSEN6 (Node 1 HT link voltage) high limit to 1.25V - register "vsen6_low_limit_mv" = "1150" # VSEN6 (Node 1 HT link voltage) low limit to 1.15V - register "vsen7_high_limit_mv" = "1150" # VSEN7 (Northbridge core voltage) high limit to 1.15V - register "vsen7_low_limit_mv" = "1050" # VSEN7 (Northbridge core voltage) low limit to 1.05V - register "vsen8_high_limit_mv" = "1900" # VSEN8 (+1.8V) high limit to 1.9V - register "vsen8_low_limit_mv" = "1700" # VSEN8 (+1.8V) low limit to 1.7V - register "vsen9_high_limit_mv" = "1250" # VSEN9 (+1.2V) high limit to 1.25V - register "vsen9_low_limit_mv" = "1150" # VSEN9 (+1.2V) low limit to 1.15V - register "vsen10_high_limit_mv" = "1150" # VSEN10 (+1.1V) high limit to 1.15V - register "vsen10_low_limit_mv" = "1050" # VSEN10 (+1.1V) low limit to 1.05V - register "vsen11_high_limit_mv" = "1625" # VSEN11 (5VSB, scaling factor ~3.2) high limit to 5.2V - register "vsen11_low_limit_mv" = "1500" # VSEN11 (5VSB, scaling factor ~3.2) low limit to 4.8V - register "vsen12_high_limit_mv" = "1083" # VSEN12 (+12V, scaling factor ~12) high limit to 13V - register "vsen12_low_limit_mv" = "917" # VSEN12 (+12V, scaling factor ~12) low limit to 11V - register "vsen13_high_limit_mv" = "1625" # VSEN13 (+5V, scaling factor ~3.2) high limit to 5.2V - register "vsen13_low_limit_mv" = "1500" # VSEN13 (+5V, scaling factor ~3.2) low limit to 4.8V - register "vdd_high_limit_mv" = "3500" # 3VDD high limit to 3.5V - register "vdd_low_limit_mv" = "3100" # 3VDD low limit to 3.1V - register "vsb_high_limit_mv" = "3500" # 3VSB high limit to 3.5V - register "vsb_low_limit_mv" = "3100" # 3VSB low limit to 3.1V - register "vbat_high_limit_mv" = "3500" # VBAT (+3V) high limit to 3.5V - register "vbat_low_limit_mv" = "2500" # VBAT (+3V) low limit to 2.5V - register "smbus_aux" = "1" # Device located on auxiliary SMBUS controller - device i2c 0x2f on end - end - end - device pci 14.1 on end # IDE 0x439c - device pci 14.2 on end # HDA 0x4383 (ASUS MIO add-on card) - device pci 14.3 on # LPC 0x439d (SMBUS primary controller) - chip superio/winbond/w83667hg-a # Super I/O - device pnp 2e.0 off end # FDC; Not available on the KCMA-D8 - device pnp 2e.1 off end # LPT1; Not available on the KCMA-D8 - device pnp 2e.2 on # COM1 - io 0x60 = 0x3f8 - irq 0x70 = 4 - end - device pnp 2e.3 on # COM2 - io 0x60 = 0x2f8 - irq 0x70 = 3 - end - device pnp 2e.5 on # PS/2 keyboard & mouse - io 0x60 = 0x60 - io 0x62 = 0x64 - irq 0x70 = 1 - irq 0x72 = 12 - end - device pnp 2e.106 off end # SPI: Not available on the KCMA-D8 - device pnp 2e.107 off end # GIPO6 - device pnp 2e.207 off end # GIPO7 - device pnp 2e.307 off end # GIPO8 - device pnp 2e.407 off end # GIPO9 - device pnp 2e.8 off end # WDT - device pnp 2e.108 off end # GPIO 1 - device pnp 2e.9 off end # GPIO2 - device pnp 2e.109 off end # GPIO3 - device pnp 2e.209 off end # GPIO4 - device pnp 2e.309 off end # GPIO5 - device pnp 2e.a on end # ACPI - device pnp 2e.b on # HW Monitor - io 0x60 = 0x290 - # IRQ purposefully not assigned to prevent lockups - end - device pnp 2e.c off end # PECI - device pnp 2e.d off end # VID_BUSSEL - device pnp 2e.f off end # GPIO_PP_OD - end - end - device pci 14.4 on # Bridge - device pci 1.0 on # Slot - # Slot # PCI 0 - end - device pci 2.0 on # Slot - # Slot # PCI 1 - end - device pci 3.0 on # Slot - # Slot # PCI 2 - end - device pci 5.0 on end # VGA - end - device pci 14.5 on end # USB OHCI2 0x4399 - end - end - device pci 18.1 on end - device pci 18.2 on end - device pci 18.3 on end - device pci 18.4 on end - device pci 18.5 on end - device pci 19.0 on end # Socket 1 node 0 - device pci 19.1 on end - device pci 19.2 on end - device pci 19.3 on end - device pci 19.4 on end - device pci 19.5 on end - end - end -end diff --git a/src/mainboard/asus/kcma-d8/dsdt.asl b/src/mainboard/asus/kcma-d8/dsdt.asl deleted file mode 100644 index fedcad0869..0000000000 --- a/src/mainboard/asus/kcma-d8/dsdt.asl +++ /dev/null @@ -1,769 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2015 Raptor Engineering - * Copyright (C) 2005 - 2012 Advanced Micro Devices, Inc. - * Copyright (C) 2007-2009 coresystems GmbH - * Copyright (C) 2004 Nick Barker - * Copyright (C) 2007, 2008 Rudolf Marek - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -/* - * WARNING: Sleep/Wake is a work in progress and is still somewhat flaky! - * Everything else does to the best of my knowledge... (T.P. 01/26/2015) - */ - -/* - * ISA portions taken from QEMU acpi-dsdt.dsl. - */ - -/* - * PCI link routing templates taken from ck804.asl and modified for this board - */ - -#include -DefinitionBlock ( - "DSDT.AML", /* Output filename */ - "DSDT", /* Signature */ - 0x02, /* DSDT Revision, needs to be 2 or higher for 64bit */ - OEM_ID, - ACPI_TABLE_CREATOR, - 0x00000001 /* OEM Revision */ - ) -{ - #include - #include - - /* Some global data */ - Name(OSVR, 3) /* Assume nothing. WinXp = 1, Vista = 2, Linux = 3, WinCE = 4 */ - Name(OSV, Ones) /* Assume nothing */ - Name(PICM, One) /* Assume APIC */ - - /* HPET enable */ - Name (HPTE, 0x1) - - #include - - /* The _PIC method is called by the OS to choose between interrupt - * routing via the i8259 interrupt controller or the APIC. - * - * _PIC is called with a parameter of 0 for i8259 configuration and - * with a parameter of 1 for Local Apic/IOAPIC configuration. - */ - Method (_PIC, 1, Serialized) { - If (Arg0) - { - \_SB.CIRQ() - } - Store (Arg0, PICM) - } - - /* _PR CPU0 is dynamically supplied by SSDT */ - /* CPU objects and _PSS entries are dynamically supplied by SSDT */ - - Scope(\_GPE) { /* Start Scope GPE */ - /* General event 3 */ - Method(_L03) { - /* Level-Triggered GPE */ - Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ - } - - /* General event 4 */ - Method(_L04) { - /* Level-Triggered GPE */ - Notify (\_SB.PCI0.PBR0, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify (\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ - } - - /* Keyboard controller PME# */ - Method(_L08) { - /* Level-Triggered GPE */ - Notify(\_SB.PCI0.LPC.PS2K, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(\_SB.PCI0.LPC.PS2M, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ - } - - /* USB controller PME# */ - Method(_L0B) { - /* Level-Triggered GPE */ - Notify (\_SB.PCI0.USB0, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify (\_SB.PCI0.USB1, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify (\_SB.PCI0.USB2, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify (\_SB.PCI0.USB3, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify (\_SB.PCI0.USB4, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify (\_SB.PCI0.USB5, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify (\_SB.PCI0.USB6, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify (\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ - } - - /* GPIO0 or GEvent8 event */ - Method(_L18) { - /* Level-Triggered GPE */ - Notify (\_SB.PCI0.PCE1, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify (\_SB.PCI0.NICA, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify (\_SB.PCI0.NICB, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify (\_SB.PCI0.PCE4, 0x02) /* NOTIFY_DEVICE_WAKE */ - } - - } /* End Scope GPE */ - - /* Root of the bus hierarchy */ - Scope (\_SB) - { - /* Top southbridge PCI device (SR5670 + SP5100) */ - Device (PCI0) - { - /* BUS0 root bus */ - - Name (_HID, EisaId ("PNP0A08")) /* PCI-e root bus (SR5670) */ - Name (_CID, EisaId ("PNP0A03")) /* PCI root bus (SP5100) */ - Name (_ADR, 0x00180001) - Name (_UID, 0x00) - - Name (HCIN, 0x00) // HC1 - - Method (_BBN, 0, NotSerialized) - { - Return (GBUS (GHCN(HCIN), GHCL(HCIN))) - } - - /* Operating System Capabilities Method */ - Method(_OSC,4) - { - /* Let OS control everything */ - Return (Arg3) - } - - External (BUSN) - External (MMIO) - External (PCIO) - External (SBLK) - External (TOM1) - External (HCLK) - External (SBDN) - External (HCDN) - External (CBST) - - /* PCI Routing Tables */ - Name (PR00, Package () { - /* PIC */ - /* Top southbridge device (SR5670) */ - /* HT Link */ - Package (0x04) { 0x0000FFFF, 0x00, LNKA, 0x00 }, - - /* PCI-E Slot 1 (Bridge) */ - Package (0x04) { 0x0002FFFF, 0x00, LNKE, 0x00 }, - - /* NIC A (Bridge) */ - Package (0x04) { 0x0009FFFF, 0x00, LNKF, 0x00 }, - - /* NIC B (Bridge) */ - Package (0x04) { 0x000AFFFF, 0x00, LNKG, 0x00 }, - - /* PCI-E Slot 4 (Bridge) */ - Package (0x04) { 0x000BFFFF, 0x00, LNKG, 0x00 }, - - /* Bottom southbridge device (SP5100) */ - /* SATA 0 */ - Package (0x04) { 0x0011FFFF, 0x00, LNKG, 0x00 }, - - /* USB 0 */ - Package (0x04) { 0x0012FFFF, 0x00, LNKA, 0x00 }, - Package (0x04) { 0x0012FFFF, 0x01, LNKB, 0x00 }, - Package (0x04) { 0x0012FFFF, 0x02, LNKC, 0x00 }, - Package (0x04) { 0x0012FFFF, 0x03, LNKD, 0x00 }, - - /* USB 1 */ - Package (0x04) { 0x0013FFFF, 0x00, LNKC, 0x00 }, - Package (0x04) { 0x0013FFFF, 0x01, LNKD, 0x00 }, - Package (0x04) { 0x0013FFFF, 0x02, LNKA, 0x00 }, - Package (0x04) { 0x0013FFFF, 0x03, LNKB, 0x00 }, - - /* SMBUS / IDE / LPC / VGA / PCI Slots 0 - 2 */ - Package (0x04) { 0x0014FFFF, 0x00, LNKA, 0x00 }, - Package (0x04) { 0x0014FFFF, 0x01, LNKB, 0x00 }, - Package (0x04) { 0x0014FFFF, 0x02, LNKC, 0x00 }, - Package (0x04) { 0x0014FFFF, 0x03, LNKD, 0x00 }, - }) - - Name (AR00, Package () { - /* APIC */ - /* Top southbridge device (SR5670) */ - /* HT Link */ - Package (0x04) { 0x0000FFFF, 0x00, 0x00, 55 }, - - /* PCI-E Slot 1 (Bridge) */ - Package (0x04) { 0x0002FFFF, 0x00, 0x00, 52 }, - - /* NIC A (Bridge) */ - Package (0x04) { 0x0009FFFF, 0x00, 0x00, 53 }, - - /* NIC B (Bridge) */ - Package (0x04) { 0x000AFFFF, 0x00, 0x00, 54 }, - - /* PCI-E Slot 4 (Bridge) */ - Package (0x04) { 0x000BFFFF, 0x00, 0x00, 54 }, - - /* Bottom southbridge device (SP5100) */ - /* SATA 0 */ - Package (0x04) { 0x0011FFFF, 0x00, 0x00, 22 }, - - /* USB 0 */ - Package (0x04) { 0x0012FFFF, 0x00, 0x00, 16 }, - Package (0x04) { 0x0012FFFF, 0x01, 0x00, 17 }, - Package (0x04) { 0x0012FFFF, 0x02, 0x00, 18 }, - Package (0x04) { 0x0012FFFF, 0x03, 0x00, 19 }, - - /* USB 1 */ - Package (0x04) { 0x0013FFFF, 0x00, 0x00, 18 }, - Package (0x04) { 0x0013FFFF, 0x01, 0x00, 19 }, - Package (0x04) { 0x0013FFFF, 0x02, 0x00, 16 }, - Package (0x04) { 0x0013FFFF, 0x03, 0x00, 17 }, - - /* SMBUS / IDE / LPC / VGA / PCI Slots 0 - 2 */ - Package (0x04) { 0x0014FFFF, 0x00, 0x00, 16 }, - Package (0x04) { 0x0014FFFF, 0x01, 0x00, 17 }, - Package (0x04) { 0x0014FFFF, 0x02, 0x00, 18 }, - Package (0x04) { 0x0014FFFF, 0x03, 0x00, 19 }, - }) - - Name (PR01, Package () { - /* PIC */ - Package (0x04) { 0x1FFFF, 0x00, LNKE, 0x00 }, - Package (0x04) { 0x1FFFF, 0x01, LNKF, 0x00 }, - Package (0x04) { 0x1FFFF, 0x02, LNKG, 0x00 }, - Package (0x04) { 0x1FFFF, 0x03, LNKH, 0x00 }, - Package (0x04) { 0x2FFFF, 0x00, LNKF, 0x00 }, - Package (0x04) { 0x2FFFF, 0x01, LNKG, 0x00 }, - Package (0x04) { 0x2FFFF, 0x02, LNKH, 0x00 }, - Package (0x04) { 0x2FFFF, 0x03, LNKE, 0x00 }, - Package (0x04) { 0x3FFFF, 0x00, LNKG, 0x00 }, - Package (0x04) { 0x3FFFF, 0x01, LNKH, 0x00 }, - Package (0x04) { 0x3FFFF, 0x02, LNKE, 0x00 }, - Package (0x04) { 0x3FFFF, 0x03, LNKF, 0x00 }, - Package (0x04) { 0x5FFFF, 0x00, LNKH, 0x00 }, - }) - - Name (AR01, Package () { - /* APIC */ - Package (0x04) { 0x1FFFF, 0x00, 0x00, 20 }, - Package (0x04) { 0x1FFFF, 0x01, 0x00, 21 }, - Package (0x04) { 0x1FFFF, 0x02, 0x00, 22 }, - Package (0x04) { 0x1FFFF, 0x03, 0x00, 23 }, - Package (0x04) { 0x2FFFF, 0x00, 0x00, 21 }, - Package (0x04) { 0x2FFFF, 0x01, 0x00, 22 }, - Package (0x04) { 0x2FFFF, 0x02, 0x00, 23 }, - Package (0x04) { 0x2FFFF, 0x03, 0x00, 20 }, - Package (0x04) { 0x3FFFF, 0x00, 0x00, 22 }, - Package (0x04) { 0x3FFFF, 0x01, 0x00, 23 }, - Package (0x04) { 0x3FFFF, 0x02, 0x00, 20 }, - Package (0x04) { 0x3FFFF, 0x03, 0x00, 21 }, - Package (0x04) { 0x5FFFF, 0x00, 0x00, 23 }, - }) - - Name (PR02, Package () { - /* PIC */ - Package (0x04) { 0xFFFF, 0x00, LNKA, 0x00 }, - Package (0x04) { 0xFFFF, 0x01, LNKB, 0x00 }, - Package (0x04) { 0xFFFF, 0x02, LNKC, 0x00 }, - Package (0x04) { 0xFFFF, 0x03, LNKD, 0x00 }, - }) - - Name (AR02, Package () { - /* APIC */ - Package (0x04) { 0xFFFF, 0x00, 0x00, 24 }, - Package (0x04) { 0xFFFF, 0x01, 0x00, 25 }, - Package (0x04) { 0xFFFF, 0x02, 0x00, 26 }, - Package (0x04) { 0xFFFF, 0x03, 0x00, 27 }, - }) - - Name (PR03, Package () { - /* PIC */ - Package (0x04) { 0xFFFF, 0x00, LNKE, 0x00 }, - Package (0x04) { 0xFFFF, 0x01, LNKF, 0x00 }, - Package (0x04) { 0xFFFF, 0x02, LNKG, 0x00 }, - Package (0x04) { 0xFFFF, 0x03, LNKH, 0x00 }, - }) - - Name (AR03, Package () { - /* APIC */ - Package (0x04) { 0xFFFF, 0x00, 0x00, 44 }, - Package (0x04) { 0xFFFF, 0x01, 0x00, 45 }, - Package (0x04) { 0xFFFF, 0x02, 0x00, 46 }, - Package (0x04) { 0xFFFF, 0x03, 0x00, 47 }, - }) - - Name (PR04, Package () { - /* PIC */ - Package (0x04) { 0xFFFF, 0x00, LNKA, 0x00 }, - Package (0x04) { 0xFFFF, 0x01, LNKB, 0x00 }, - Package (0x04) { 0xFFFF, 0x02, LNKC, 0x00 }, - Package (0x04) { 0xFFFF, 0x03, LNKD, 0x00 }, - }) - - Name (AR04, Package () { - /* APIC */ - Package (0x04) { 0xFFFF, 0x00, 0x00, 48 }, - Package (0x04) { 0xFFFF, 0x01, 0x00, 49 }, - Package (0x04) { 0xFFFF, 0x02, 0x00, 50 }, - Package (0x04) { 0xFFFF, 0x03, 0x00, 51 }, - }) - - Name (PR05, Package () { - /* PIC */ - Package (0x04) { 0xFFFF, 0x00, LNKH, 0x00 }, - Package (0x04) { 0xFFFF, 0x01, LNKE, 0x00 }, - Package (0x04) { 0xFFFF, 0x02, LNKF, 0x00 }, - Package (0x04) { 0xFFFF, 0x03, LNKG, 0x00 }, - }) - - Name (AR05, Package () { - /* APIC */ - Package (0x04) { 0xFFFF, 0x00, 0x00, 47 }, - Package (0x04) { 0xFFFF, 0x01, 0x00, 44 }, - Package (0x04) { 0xFFFF, 0x02, 0x00, 45 }, - Package (0x04) { 0xFFFF, 0x03, 0x00, 46 }, - }) - - Name (PR06, Package () { - /* PIC */ - Package (0x04) { 0xFFFF, 0x00, LNKA, 0x00 }, - Package (0x04) { 0xFFFF, 0x01, LNKB, 0x00 }, - Package (0x04) { 0xFFFF, 0x02, LNKC, 0x00 }, - Package (0x04) { 0xFFFF, 0x03, LNKD, 0x00 }, - }) - - Name (AR06, Package () { - /* APIC */ - Package (0x04) { 0xFFFF, 0x00, 0x00, 32 }, - Package (0x04) { 0xFFFF, 0x01, 0x00, 33 }, - Package (0x04) { 0xFFFF, 0x02, 0x00, 34 }, - Package (0x04) { 0xFFFF, 0x03, 0x00, 35 }, - }) - - Name (PR07, Package () { - /* PIC */ - Package (0x04) { 0xFFFF, 0x00, LNKE, 0x00 }, - Package (0x04) { 0xFFFF, 0x01, LNKF, 0x00 }, - Package (0x04) { 0xFFFF, 0x02, LNKG, 0x00 }, - Package (0x04) { 0xFFFF, 0x03, LNKH, 0x00 }, - }) - - Name (AR07, Package () { - /* APIC */ - Package (0x04) { 0xFFFF, 0x00, 0x00, 36 }, - Package (0x04) { 0xFFFF, 0x01, 0x00, 37 }, - Package (0x04) { 0xFFFF, 0x02, 0x00, 38 }, - Package (0x04) { 0xFFFF, 0x03, 0x00, 39 }, - }) - - Name (PR08, Package () { - /* PIC */ - Package (0x04) { 0xFFFF, 0x00, LNKA, 0x00 }, - Package (0x04) { 0xFFFF, 0x01, LNKB, 0x00 }, - Package (0x04) { 0xFFFF, 0x02, LNKC, 0x00 }, - Package (0x04) { 0xFFFF, 0x03, LNKD, 0x00 }, - }) - - Name (AR08, Package () { - /* APIC */ - Package (0x04) { 0xFFFF, 0x00, 0x00, 40 }, - Package (0x04) { 0xFFFF, 0x01, 0x00, 41 }, - Package (0x04) { 0xFFFF, 0x02, 0x00, 42 }, - Package (0x04) { 0xFFFF, 0x03, 0x00, 43 }, - }) - - /* PCI Resource Tables */ - - /* PCI Resource Settings Access */ - Method (_CRS, 0, Serialized) - { - Name (BUF0, ResourceTemplate () - { - IO (Decode16, - 0x0CF8, // Address Range Minimum - 0x0CF8, // Address Range Maximum - 0x01, // Address Alignment - 0x08, // Address Length - ) - WordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, - 0x0000, // Address Space Granularity - 0x0000, // Address Range Minimum - 0x0CF7, // Address Range Maximum - 0x0000, // Address Translation Offset - 0x0CF8, // Address Length - ,, , TypeStatic) - }) - /* Methods below use SSDT to get actual MMIO regs - The IO ports are from 0xd00, optionally an VGA, - otherwise the info from MMIO is used. - \_SB.GXXX(node, link) - */ - Concatenate (\_SB.GMEM (0x00, \_SB.PCI0.SBLK), BUF0, Local1) - Concatenate (\_SB.GIOR (0x00, \_SB.PCI0.SBLK), Local1, Local2) - Concatenate (\_SB.GWBN (0x00, \_SB.PCI0.SBLK), Local2, Local3) - Return (Local3) - } - - /* PCI Routing Table Access */ - Method (_PRT, 0, NotSerialized) { - If (PICM) { - Return (AR00) - } Else { - Return (PR00) - } - } - - /* 0:11.0 SP5100 SATA 0 */ - Device(SAT0) - { - Name (_ADR, 0x00110000) // _ADR: Address - Name(_PRW, Package () {0x05, 0x04}) // Wake from S1-S4 - #include - } - - /* 0:12.0 SP5100 USB 0 */ - Device (USB0) - { - Name (_ADR, 0x00120000) // _ADR: Address - Name(_PRW, Package () {0x05, 0x04}) // Wake from S1-S4 - } - - /* 0:12.1 SP5100 USB 1 */ - Device (USB1) - { - Name (_ADR, 0x00120001) // _ADR: Address - Name(_PRW, Package () {0x05, 0x04}) // Wake from S1-S4 - } - - /* 0:12.2 SP5100 USB 2 */ - Device (USB2) - { - Name (_ADR, 0x00120002) // _ADR: Address - Name(_PRW, Package () {0x05, 0x04}) // Wake from S1-S4 - } - - /* 0:13.0 SP5100 USB 3 */ - Device (USB3) - { - Name (_ADR, 0x00130000) // _ADR: Address - Name(_PRW, Package () {0x05, 0x04}) // Wake from S1-S4 - } - - /* 0:13.1 SP5100 USB 4 */ - Device (USB4) - { - Name (_ADR, 0x00130001) // _ADR: Address - Name(_PRW, Package () {0x05, 0x04}) // Wake from S1-S4 - } - - /* 0:13.2 SP5100 USB 5 */ - Device (USB5) - { - Name (_ADR, 0x00130002) // _ADR: Address - Name(_PRW, Package () {0x05, 0x04}) // Wake from S1-S4 - } - - /* 0:14.1 SP5100 IDE Controller */ - Device (IDEC) - { - Name (_ADR, 0x00140001) // _ADR: Address - Name(_PRW, Package () {0x05, 0x04}) // Wake from S1-S4 - #include - } - - /* 0:14.3 SP5100 LPC */ - Device (LPC) { - Name (_HID, EisaId ("PNP0A05")) - Name (_ADR, 0x00140003) - - /* Real Time Clock Device */ - Device(RTC0) { - Name(_HID, EISAID("PNP0B00")) /* AT Real Time Clock (not PIIX4 compatible) */ - Name(BUF0, ResourceTemplate() { - IO(Decode16, 0x0070, 0x0070, 0x01, 0x02) - }) - Name(BUF1, ResourceTemplate() { - IRQNoFlags() { 8 } - IO(Decode16, 0x0070, 0x0070, 0x01, 0x02) - }) - Method(_CRS, 0) { - If(HPTE) { - Return(BUF0) - } - Return(BUF1) - } - } - - Device(TMR) { /* Timer */ - Name(_HID,EISAID("PNP0100")) /* System Timer */ - Name(BUF0, ResourceTemplate() { - IO(Decode16, 0x0040, 0x0040, 0x01, 0x04) - }) - Name(BUF1, ResourceTemplate() { - IRQNoFlags() { 0 } - IO(Decode16, 0x0040, 0x0040, 0x01, 0x04) - }) - Method(_CRS, 0) { - If(HPTE) { - Return(BUF0) - } - Return(BUF1) - } - } - - Device(SPKR) { /* Speaker */ - Name(_HID,EISAID("PNP0800")) /* AT style speaker */ - Name(_CRS, ResourceTemplate() { - IO(Decode16, 0x0061, 0x0061, 0, 1) - }) - } - - Device(PIC) { - Name(_HID,EISAID("PNP0000")) /* AT Interrupt Controller */ - Name(_CRS, ResourceTemplate() { - IRQNoFlags() { 2 } - IO(Decode16,0x0020, 0x0020, 0, 2) - IO(Decode16,0x00A0, 0x00A0, 0, 2) - }) - } - - Device(MAD) { /* 8257 DMA */ - Name(_HID,EISAID("PNP0200")) /* Hardware Device ID */ - Name(_CRS, ResourceTemplate() { - DMA(Compatibility,BusMaster,Transfer8){4} - IO(Decode16, 0x0000, 0x0000, 0x10, 0x10) - IO(Decode16, 0x0081, 0x0081, 0x01, 0x03) - IO(Decode16, 0x0087, 0x0087, 0x01, 0x01) - IO(Decode16, 0x0089, 0x0089, 0x01, 0x03) - IO(Decode16, 0x008F, 0x008F, 0x01, 0x01) - IO(Decode16, 0x00C0, 0x00C0, 0x10, 0x20) - }) /* End Name(_SB.PCI0.LpcIsaBr.MAD._CRS) */ - } - - Device(COPR) { - Name(_HID,EISAID("PNP0C04")) /* Math Coprocessor */ - Name(_CRS, ResourceTemplate() { - IO(Decode16, 0x00F0, 0x00F0, 0, 0x10) - IRQNoFlags(){13} - }) - } - - #include - - /* UART 1 */ - Device (URT1) - { - Name (_HID, EisaId ("PNP0501")) // "PNP0501" for UART - Name(_PRW, Package () {0x03, 0x04}) // Wake from S1-S4 - Method (_STA, 0, NotSerialized) - { - Return (0x0f) // Always enable - } - Name (_PRS, ResourceTemplate() { - StartDependentFn(0, 1) { - IO(Decode16, 0x3f8, 0x3f8, 0x8, 0x8) - IRQNoFlags() { 4 } - } EndDependentFn() - }) - Method (_CRS, 0) - { - Return(ResourceTemplate() { - IO(Decode16, 0x3f8, 0x3f8, 0x8, 0x8) - IRQNoFlags() { 4 } - }) - } - } - - /* UART 2 */ - Device (URT2) - { - Name (_HID, EisaId ("PNP0501")) // "PNP0501" for UART - Name(_PRW, Package () {0x03, 0x04}) // Wake from S1-S4 - Method (_STA, 0, NotSerialized) - { - Return (0x0f) // Always enable - } - Name (_PRS, ResourceTemplate() { - StartDependentFn(0, 1) { - IO(Decode16, 0x2f8, 0x2f8, 0x8, 0x8) - IRQNoFlags() { 3 } - } EndDependentFn() - }) - Method (_CRS, 0) - { - Return(ResourceTemplate() { - IO(Decode16, 0x2f8, 0x2f8, 0x8, 0x8) - IRQNoFlags() { 3 } - }) - } - } - } - - /* High Precision Event Timer */ - Device (HPET) - { - Name (_HID, EisaId ("PNP0103")) - Name (CRS, ResourceTemplate () - { - Memory32Fixed(ReadOnly, 0xFED00000, 0x00000400) - }) - Method (_STA, 0) - { - If(HPTE) { - Return (0x0F) - } - Return (0x0) - } - Method(_CRS, 0) - { - Return(CRS) - } - } - - /* 0:14.4 PCI Bridge */ - Device (PBR0) - { - Name (_ADR, 0x00140004) // _ADR: Address - Name(_PRW, Package () {0x11, 0x04}) // Wake from S1-S4 - Method (_PRT, 0, NotSerialized) // _PRT: PCI Routing Table - { - If (PICM) { - Return (AR01) - } Else { - Return (PR01) - } - } - Device (SLT1) - { - Name (_ADR, 0xFFFF) // _ADR: Address - Name(_PRW, Package () {0x0B, 0x04}) // Wake from S1-S4 - } - } - - /* 0:14.5 SP5100 USB 6 */ - Device (USB6) - { - Name (_ADR, 0x00140005) // _ADR: Address - Name(_PRW, Package () {0x05, 0x04}) // Wake from S1-S4 - } - - /* 2:00.0 PCIe x16 */ - Device (PCE1) - { - Name (_ADR, 0x00020000) // _ADR: Address - Name(_PRW, Package () {0x11, 0x04}) // Wake from S1-S4 - Method (_PRT, 0, NotSerialized) // _PRT: PCI Routing Table - { - If (PICM) { - Return (AR02) - } Else { - Return (PR02) - } - } - Device (SLT1) - { - Name (_ADR, 0xFFFF) // _ADR: Address - Name(_PRW, Package () {0x0B, 0x04}) // Wake from S1-S4 - } - } - - /* 1:00.0 PIKE */ - Device (PIKE) - { - Name (_ADR, 0x00040000) // _ADR: Address - Name(_PRW, Package () {0x11, 0x04}) // Wake from S1-S4 - Method (_PRT, 0, NotSerialized) // _PRT: PCI Routing Table - { - If (PICM) { - Return (AR03) - } Else { - Return (PR03) - } - } - Device (SLT1) - { - Name (_ADR, 0xFFFF) // _ADR: Address - Name(_PRW, Package () {0x0B, 0x04}) // Wake from S1-S4 - } - } - - /* 3:00.0 PCIe NIC A */ - Device (NICA) - { - Name (_ADR, 0x00090000) // _ADR: Address - Name(_PRW, Package () {0x11, 0x04}) // Wake from S1-S4 - Method (_PRT, 0, NotSerialized) // _PRT: PCI Routing Table - { - If (PICM) { - Return (AR04) - } Else { - Return (PR04) - } - } - Device (BDC1) - { - Name (_ADR, Zero) // _ADR: Address - } - } - - /* 4:00.0 PCIe NIC B */ - Device (NICB) - { - Name (_ADR, 0x000A0000) // _ADR: Address - Name(_PRW, Package () {0x11, 0x04}) // Wake from S1-S4 - Method (_PRT, 0, NotSerialized) // _PRT: PCI Routing Table - { - If (PICM) { - Return (AR05) - } Else { - Return (PR05) - } - } - Device (BDC2) - { - Name (_ADR, Zero) // _ADR: Address - } - } - - /* 5:00.0 PCIe x16 */ - Device (PCE4) - { - Name (_ADR, 0x000B0000) // _ADR: Address - Name(_PRW, Package () {0x11, 0x04}) // Wake from S1-S4 - Method (_PRT, 0, NotSerialized) // _PRT: PCI Routing Table - { - If (PICM) { - Return (AR06) - } Else { - Return (PR06) - } - } - Device (SLT1) - { - Name (_ADR, 0xFFFF) // _ADR: Address - Name(_PRW, Package () {0x0B, 0x04}) // Wake from S1-S4 - } - } - } - - Device (PWRB) { /* Start Power button device */ - Name(_HID, EISAID("PNP0C0C")) - Name(_UID, 0xAA) - Name(_PRW, Package () {3, 0x04}) /* wake from S1-S4 */ - Name(_STA, 0x0B) /* sata is invisible */ - } - } - -#include "acpi/pm_ctrl.asl" - -} diff --git a/src/mainboard/asus/kcma-d8/get_bus_conf.c b/src/mainboard/asus/kcma-d8/get_bus_conf.c deleted file mode 100644 index cc64dea2d3..0000000000 --- a/src/mainboard/asus/kcma-d8/get_bus_conf.c +++ /dev/null @@ -1,29 +0,0 @@ - /* - * This file is part of the coreboot project. - * - * Copyright (C) 2010 Advanced Micro Devices, Inc. - * Copyright (C) 2015 Timothy Pearson , Raptor Engineering - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include -#include -#include - -void get_bus_conf(void) -{ - get_default_pci1234(1); - sysconf.sbdn = (sysconf.hcdn[0] & 0xff); - - pirq_router_bus = (sysconf.pci1234[0] >> 16) & 0xff; -} diff --git a/src/mainboard/asus/kcma-d8/irq_tables.c b/src/mainboard/asus/kcma-d8/irq_tables.c deleted file mode 100644 index 06e842a09b..0000000000 --- a/src/mainboard/asus/kcma-d8/irq_tables.c +++ /dev/null @@ -1,123 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2010 Advanced Micro Devices, Inc. - * Copyright (C) 2015 Raptor Engineering - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include -#include -#include -#include - -#include - -/* Free irqs are 3, 4, 5, 6, 7, 9, 10, 11, 12, 14, and 15 */ -#define IRQBM ((1 << 3)|(1 << 4)|(1 << 5)|(1 << 6)|(1 << 7)|(1 << 9)|(1 << 10)|(1 << 11)|(1 << 12)|(1 << 14)|(1 << 15)) - -#define LNKA 1 -#define LNKB 2 -#define LNKC 3 -#define LNKD 4 - -/* - * For simplicity map LNK[E-H] to LNK[A-D]. - * This also means we are 82C596 compatible. - * Needs 0:11.0 0x46[4] set to 0. - */ -#define LNKE 1 -#define LNKF 2 -#define LNKG 3 -#define LNKH 4 - -static void write_pirq_info(struct irq_info *pirq_info, u8 bus, u8 devfn, - u8 link0, u16 bitmap0, u8 link1, u16 bitmap1, - u8 link2, u16 bitmap2, u8 link3, u16 bitmap3, - u8 slot, u8 rfu) -{ - pirq_info->bus = bus; - pirq_info->devfn = devfn; - pirq_info->irq[0].link = link0; - pirq_info->irq[0].bitmap = bitmap0; - pirq_info->irq[1].link = link1; - pirq_info->irq[1].bitmap = bitmap1; - pirq_info->irq[2].link = link2; - pirq_info->irq[2].bitmap = bitmap2; - pirq_info->irq[3].link = link3; - pirq_info->irq[3].bitmap = bitmap3; - pirq_info->slot = slot; - pirq_info->rfu = rfu; -} - - -unsigned long write_pirq_routing_table(unsigned long addr) -{ - struct irq_routing_table *pirq; - struct irq_info *pirq_info; - u32 slot_num; - u8 *v; - - u8 sum = 0; - int i; - - /* Align the table to be 16 byte aligned. */ - addr += 15; - addr &= ~15; - - /* This table must be between 0xf0000 & 0x100000 */ - printk(BIOS_INFO, "Writing IRQ routing tables to 0x%lx...", addr); - - pirq = (void *)(addr); - v = (u8 *) (addr); - - pirq->signature = PIRQ_SIGNATURE; - pirq->version = PIRQ_VERSION; - - /* Where the interrupt router resides */ - pirq->rtr_bus = pirq_router_bus; - pirq->rtr_devfn = PCI_DEVFN(0x14, 4); - - pirq->exclusive_irqs = 0; - - pirq->rtr_vendor = PCI_VENDOR_ID_ATI; - pirq->rtr_device = PCI_DEVICE_ID_ATI_SB700_PCI; - - pirq->miniport_data = 0; - - memset(pirq->rfu, 0, sizeof(pirq->rfu)); - - pirq_info = (void *)(&pirq->checksum + 1); - slot_num = 0; - - /* pci bridge */ - write_pirq_info(pirq_info, pirq_router_bus, - PCI_DEVFN(0x14, 4), LNKA, IRQBM, LNKB, - IRQBM, LNKC, IRQBM, LNKD, IRQBM, 0, 0); - pirq_info++; - slot_num++; - - pirq->size = 32 + 16 * slot_num; - - for (i = 0; i < pirq->size; i++) - sum += v[i]; - - sum = pirq->checksum - sum; - if (sum != pirq->checksum) { - pirq->checksum = sum; - } - - printk(BIOS_INFO, "done.\n"); - - return (unsigned long)pirq_info; -} diff --git a/src/mainboard/asus/kcma-d8/mainboard.c b/src/mainboard/asus/kcma-d8/mainboard.c deleted file mode 100644 index 145d9573b1..0000000000 --- a/src/mainboard/asus/kcma-d8/mainboard.c +++ /dev/null @@ -1,113 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2015 Timothy Pearson , Raptor Engineering - * Copyright (C) 2010 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -void set_pcie_reset(void) -{ - struct device *pcie_core_dev; - - pcie_core_dev = pcidev_on_root(0, 0); - set_htiu_enable_bits(pcie_core_dev, 0xA8, 0xFFFFFFFF, 0x28282828); - set_htiu_enable_bits(pcie_core_dev, 0xA9, 0x000000FF, 0x00000028); -} - -void set_pcie_dereset(void) -{ - struct device *pcie_core_dev; - - pcie_core_dev = pcidev_on_root(0, 0); - set_htiu_enable_bits(pcie_core_dev, 0xA8, 0xFFFFFFFF, 0x6F6F6F6F); - set_htiu_enable_bits(pcie_core_dev, 0xA9, 0x000000FF, 0x0000006F); -} - -/************************************************* -* enable the dedicated function in kgpe-d16 board. -* This function is called earlier than sr5650_enable. -*************************************************/ -static void mainboard_enable(struct device *dev) -{ - printk(BIOS_INFO, "Mainboard KCMA-D8 initializing, dev=0x%p\n", dev); - - msr_t msr, msr2; - - /* TOP_MEM: the top of DRAM below 4G */ - msr = rdmsr(TOP_MEM); - printk - (BIOS_INFO, "%s, TOP MEM: msr.lo = 0x%08x, msr.hi = 0x%08x\n", - __func__, msr.lo, msr.hi); - - /* TOP_MEM2: the top of DRAM above 4G */ - msr2 = rdmsr(TOP_MEM2); - printk - (BIOS_INFO, "%s, TOP MEM2: msr2.lo = 0x%08x, msr2.hi = 0x%08x\n", - __func__, msr2.lo, msr2.hi); - - set_pcie_dereset(); - /* get_ide_dma66(); */ -} - -/* override the default SATA PHY setup */ -void sb7xx_51xx_setup_sata_phys(struct device *dev) -{ - /* RPR7.6.1 Program the PHY Global Control to 0x2C00 */ - pci_write_config16(dev, 0x86, 0x2c00); - - /* RPR7.6.2 SATA GENI PHY ports setting */ - pci_write_config32(dev, 0x88, 0x01b48016); - pci_write_config32(dev, 0x8c, 0x01b48016); - pci_write_config32(dev, 0x90, 0x01b48016); - pci_write_config32(dev, 0x94, 0x01b48016); - pci_write_config32(dev, 0x98, 0x01b48016); - pci_write_config32(dev, 0x9c, 0x01b48016); - - /* RPR7.6.3 SATA GEN II PHY port setting for port [0~5]. */ - pci_write_config16(dev, 0xa0, 0xa07a); - pci_write_config16(dev, 0xa2, 0xa07a); - pci_write_config16(dev, 0xa4, 0xa07a); - pci_write_config16(dev, 0xa6, 0xa07a); - pci_write_config16(dev, 0xa8, 0xa07a); - pci_write_config16(dev, 0xaa, 0xa07a); -} - -/* override the default SATA port setup */ -void sb7xx_51xx_setup_sata_port_indication(void *sata_bar5) -{ - uint32_t dword; - - /* RPR7.9 Program Port Indication Registers */ - dword = read32(sata_bar5 + 0xf8); - dword &= ~(0x3f << 12); /* All ports are iSATA */ - dword &= ~0x3f; - write32(sata_bar5 + 0xf8, dword); - - dword = read32(sata_bar5 + 0xfc); - dword &= ~(0x1 << 20); /* No eSATA ports are present */ - write32(sata_bar5 + 0xfc, dword); -} - -struct chip_operations mainboard_ops = { - .enable_dev = mainboard_enable, -}; diff --git a/src/mainboard/asus/kcma-d8/mptable.c b/src/mainboard/asus/kcma-d8/mptable.c deleted file mode 100644 index 65be183ce9..0000000000 --- a/src/mainboard/asus/kcma-d8/mptable.c +++ /dev/null @@ -1,219 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2010 Advanced Micro Devices, Inc. - * Copyright (C) 2015 Raptor Engineering - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include -#include -#include - -static void *smp_write_config_table(void *v) -{ - struct mp_config_table *mc; - int bus_isa; - u32 apicid_sp5100; - u32 apicid_sr5650; - struct device *dev; - uint8_t sp5100_bus_number; - - mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); - - mptable_init(mc, LOCAL_APIC_ADDR); - - smp_write_processors(mc); - - if (CONFIG(ENABLE_APIC_EXT_ID) && (CONFIG_APIC_ID_OFFSET > 0)) - apicid_sp5100 = 0x0; - else - apicid_sp5100 = 0x20; - apicid_sr5650 = apicid_sp5100 + 1; - - mptable_write_buses(mc, NULL, &bus_isa); - /* I/O APICs: APIC ID Version State Address */ - { - uint32_t *dword_ptr; - uint32_t dword; - uint16_t word; - uint8_t byte; - - sp5100_bus_number = 0; //bus_sp5100[0]; TODO: why bus_sp5100[0] use same value of bus_sr5650[0] assigned by get_pci1234(), instead of 0. - - dev = dev_find_slot(sp5100_bus_number, PCI_DEVFN(0x14, 0)); - if (dev) { - dword_ptr = (u32 *)(pci_read_config32(dev, 0x74) & 0xfffffff0); - smp_write_ioapic(mc, apicid_sp5100, 0x11, dword_ptr); - - /* Initialize interrupt mapping */ - /* USB 1 & 2 */ - word = pci_read_config16(dev, 0xbe); - word &= ~0x3f3f; - word |= 0x0; /* 0: INTA, ...., 7: INTH */ - word |= (0x1 << 3); /* 0: INTA, ...., 7: INTH */ - word |= (0x2 << 8); /* 0: INTA, ...., 7: INTH */ - word |= (0x3 << 11); /* 0: INTA, ...., 7: INTH */ - pci_write_config16(dev, 0xbe, word); - - /* USB 3 */ - byte = pci_read_config8(dev, 0x63); - byte &= 0xf8; - byte |= (0x2 << 4); /* 0: INTA, ...., 7: INTH */ - pci_write_config8(dev, 0x63, byte); - - dword = pci_read_config32(dev, 0xac); - - /* SATA */ - dword &= ~(7 << 26); - dword |= (0x6 << 26); /* 0: INTA, ...., 7: INTH */ - - /* Hide IDE */ - dword &= ~(0x00080000); - - /* dword_ptr |= 1 << 22; PIC and APIC co exists */ - pci_write_config32(dev, 0xac, dword); - - /* - * 00:12.0: PROG SATA : INT F - * 00:13.0: INTA USB_0 - * 00:13.1: INTB USB_1 - * 00:13.2: INTC USB_2 - * 00:13.3: INTD USB_3 - * 00:13.4: INTC USB_4 - * 00:13.5: INTD USB2 - * 00:14.1: INTA IDE - * 00:14.2: Prog HDA : INT E - * 00:14.5: INTB ACI - * 00:14.6: INTB MCI - */ - } - dev = pcidev_on_root(0, 0); - if (dev) { - pci_write_config32(dev, 0xF8, 0x1); - dword_ptr = (u32 *)(pci_read_config32(dev, 0xFC) & 0xfffffff0); - smp_write_ioapic(mc, apicid_sr5650, 0x11, dword_ptr); - } - } - - /* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ -#define IO_LOCAL_INT(type, intr, apicid, pin) \ - smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin)); - - mptable_add_isa_interrupts(mc, bus_isa, apicid_sp5100, 0); - - /* SR5650 devices */ - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0, (((0)<<2)|(2)), apicid_sr5650, 31); /* Device 0 Function 2 (LNKA, APIC pin 31) */ - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0, (((2)<<2)|(0)), apicid_sr5650, 28); /* Device 2 (LNKE, APIC pin 28) */ - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0, (((4)<<2)|(0)), apicid_sr5650, 28); /* Device 4 (LNKF, APIC pin 28) */ - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0, (((9)<<2)|(0)), apicid_sr5650, 29); /* Device 9 (LNKG, APIC pin 29) */ - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0, (((10)<<2)|(0)), apicid_sr5650, 30); /* Device 10 (LNKG, APIC pin 30) */ - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0, (((11)<<2)|(0)), apicid_sr5650, 30); /* Device 11 (LNKG, APIC pin 30) */ - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0, (((12)<<2)|(0)), apicid_sr5650, 30); /* Device 12 (LNKG, APIC pin 30) */ - - dev = pcidev_on_root(0x2, 0); - if (dev && dev->enabled) { - uint8_t bus_pci = dev->link_list->secondary; - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_pci, (((0)<<0x2)|(0)), apicid_sr5650, 0); /* card behind dev2 */ - } - dev = pcidev_on_root(0x4, 0); - if (dev && dev->enabled) { - uint8_t bus_pci = dev->link_list->secondary; - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_pci, (((0)<<0x4)|(0)), apicid_sr5650, 0); /* PIKE */ - } - dev = pcidev_on_root(0x9, 0); - if (dev && dev->enabled) { - uint8_t bus_pci = dev->link_list->secondary; - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_pci, (((0)<<0x9)|(0)), apicid_sr5650, 23); /* NIC A */ - } - dev = pcidev_on_root(0xa, 0); - if (dev && dev->enabled) { - uint8_t bus_pci = dev->link_list->secondary; - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_pci, (((0)<<0xa)|(0)), apicid_sr5650, 24); /* NIC B */ - } - dev = pcidev_on_root(0xb, 0); - if (dev && dev->enabled) { - uint8_t bus_pci = dev->link_list->secondary; - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_pci, (((0)<<0xb)|(0)), apicid_sr5650, 0); /* card behind dev11 */ - } - dev = pcidev_on_root(0xc, 0); - if (dev && dev->enabled) { - uint8_t bus_pci = dev->link_list->secondary; - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_pci, (((0)<<0xc)|(0)), apicid_sr5650, 0); /* card behind dev12 */ - } - - /* PCI interrupts are level triggered, and are - * associated with a specific bus/device/function tuple. - */ -#define PCI_INT(bus, dev, interrupt_signal, pin) \ - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(interrupt_signal)), apicid_sp5100, (pin)) - - /* USB1 */ - PCI_INT(sp5100_bus_number, 0x12, 0x0, 0x10); /* OHCI0 Port 0~2 */ - PCI_INT(sp5100_bus_number, 0x12, 0x1, 0x11); /* OHCI1 Port 3~5 */ - - /* USB2 */ - PCI_INT(sp5100_bus_number, 0x13, 0x0, 0x12); /* OHCI0 Port 6~8 */ - PCI_INT(sp5100_bus_number, 0x13, 0x1, 0x13); /* EHCI Port 6~11 */ - - /* USB3 */ - PCI_INT(sp5100_bus_number, 0x14, 0x3, 0x12); /* OHCI0 Port 12~13 */ - - /* SATA */ - PCI_INT(sp5100_bus_number, 0x11, 0x0, 0x16); /* 6, INTG */ - - /* PCI slots */ - dev = pcidev_on_root(0x14, 4); - if (dev && dev->enabled) { - u8 bus_pci = dev->link_list->secondary; - - /* PCI_SLOT 0 */ - PCI_INT(bus_pci, 0x1, 0x0, 0x14); - PCI_INT(bus_pci, 0x1, 0x1, 0x15); - PCI_INT(bus_pci, 0x1, 0x2, 0x16); - PCI_INT(bus_pci, 0x1, 0x3, 0x17); - - /* PCI_SLOT 1 */ - PCI_INT(bus_pci, 0x2, 0x0, 0x15); - PCI_INT(bus_pci, 0x2, 0x1, 0x16); - PCI_INT(bus_pci, 0x2, 0x2, 0x17); - PCI_INT(bus_pci, 0x2, 0x3, 0x14); - - /* PCI_SLOT 2 */ - PCI_INT(bus_pci, 0x3, 0x0, 0x16); - PCI_INT(bus_pci, 0x3, 0x1, 0x17); - PCI_INT(bus_pci, 0x3, 0x2, 0x14); - PCI_INT(bus_pci, 0x3, 0x3, 0x15); - - /* VGA */ - PCI_INT(bus_pci, 0x5, 0x0, 0x17); - PCI_INT(bus_pci, 0x5, 0x1, 0x14); - PCI_INT(bus_pci, 0x5, 0x2, 0x15); - PCI_INT(bus_pci, 0x5, 0x3, 0x16); - } - - /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ - IO_LOCAL_INT(mp_ExtINT, 0x0, MP_APIC_ALL, 0x0); - IO_LOCAL_INT(mp_NMI, 0x0, MP_APIC_ALL, 0x1); - /* There is no extension information... */ - - /* Compute the checksums */ - return mptable_finalize(mc); -} - -unsigned long write_smp_table(unsigned long addr) -{ - void *v; - v = smp_write_floating_table(addr, 0); - return (unsigned long)smp_write_config_table(v); -} diff --git a/src/mainboard/asus/kcma-d8/resourcemap.c b/src/mainboard/asus/kcma-d8/resourcemap.c deleted file mode 100644 index bcef3e45f4..0000000000 --- a/src/mainboard/asus/kcma-d8/resourcemap.c +++ /dev/null @@ -1,553 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2015 Timothy Pearson , Raptor Engineering - * - * Copyright (C) 2007 AMD - * Written by Yinghai Lu for AMD. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include - -void setup_mb_resource_map(void) -{ - static const unsigned int fam15h_register_values[] = { - /* Careful set limit registers before base registers which contain the enables */ - /* DRAM Limit i Registers - * F1:0x44 i = 0 - * F1:0x4C i = 1 - * F1:0x54 i = 2 - * F1:0x5C i = 3 - * F1:0x64 i = 4 - * F1:0x6C i = 5 - * F1:0x74 i = 6 - * F1:0x7C i = 7 - * [ 2: 0] Destination Node ID - * 000 = Node 0 - * 001 = Node 1 - * 010 = Node 2 - * 011 = Node 3 - * 100 = Node 4 - * 101 = Node 5 - * 110 = Node 6 - * 111 = Node 7 - * [ 7: 3] Reserved - * [10: 8] Interleave select - * specifies the values of A[14:12] to use with interleave enable. - * [15:11] Reserved - * [31:16] DRAM Limit Address i Bits 39-24 - * This field defines the upper address bits of a 40 bit address - * that define the end of the DRAM region. - */ - // ADDRMAP_REG(0x44), 0x0000f8f8, 0x00000000, - ADDRMAP_REG(0x4C), 0x0000f8f8, 0x00000001, - ADDRMAP_REG(0x54), 0x0000f8f8, 0x00000002, - ADDRMAP_REG(0x5C), 0x0000f8f8, 0x00000003, - ADDRMAP_REG(0x64), 0x0000f8f8, 0x00000004, - ADDRMAP_REG(0x6C), 0x0000f8f8, 0x00000005, - ADDRMAP_REG(0x74), 0x0000f8f8, 0x00000006, - ADDRMAP_REG(0x7C), 0x0000f8f8, 0x00000007, - - /* DRAM Base i Registers - * F1:0x40 i = 0 - * F1:0x48 i = 1 - * F1:0x50 i = 2 - * F1:0x58 i = 3 - * F1:0x60 i = 4 - * F1:0x68 i = 5 - * F1:0x70 i = 6 - * F1:0x78 i = 7 - * [ 0: 0] Read Enable - * 0 = Reads Disabled - * 1 = Reads Enabled - * [ 1: 1] Write Enable - * 0 = Writes Disabled - * 1 = Writes Enabled - * [ 7: 2] Reserved - * [10: 8] Interleave Enable - * 000 = No interleave - * 001 = Interleave on A[12] (2 nodes) - * 010 = reserved - * 011 = Interleave on A[12] and A[14] (4 nodes) - * 100 = reserved - * 101 = reserved - * 110 = reserved - * 111 = Interleve on A[12] and A[13] and A[14] (8 nodes) - * [15:11] Reserved - * [31:16] DRAM Base Address i Bits 39-24 - * This field defines the upper address bits of a 40-bit address - * that define the start of the DRAM region. - */ - // ADDRMAP_REG(0x40), 0x0000f8fc, 0x00000000, - ADDRMAP_REG(0x48), 0x0000f8fc, 0x00000000, - ADDRMAP_REG(0x50), 0x0000f8fc, 0x00000000, - ADDRMAP_REG(0x58), 0x0000f8fc, 0x00000000, - ADDRMAP_REG(0x60), 0x0000f8fc, 0x00000000, - ADDRMAP_REG(0x68), 0x0000f8fc, 0x00000000, - ADDRMAP_REG(0x70), 0x0000f8fc, 0x00000000, - ADDRMAP_REG(0x78), 0x0000f8fc, 0x00000000, - - /* Memory-Mapped I/O Limit i Registers - * F1:0x84 i = 0 - * F1:0x8C i = 1 - * F1:0x94 i = 2 - * F1:0x9C i = 3 - * F1:0xA4 i = 4 - * F1:0xAC i = 5 - * F1:0xB4 i = 6 - * F1:0xBC i = 7 - * [ 2: 0] Destination Node ID - * 000 = Node 0 - * 001 = Node 1 - * 010 = Node 2 - * 011 = Node 3 - * 100 = Node 4 - * 101 = Node 5 - * 110 = Node 6 - * 111 = Node 7 - * [ 3: 3] Reserved - * [ 5: 4] Destination Link ID - * 00 = Link 0 - * 01 = Link 1 - * 10 = Link 2 - * 11 = Link 3 - * [ 6: 6] Reserved - * [ 7: 7] Non-Posted - * 0 = CPU writes may be posted - * 1 = CPU writes must be non-posted - * [31: 8] Memory-Mapped I/O Limit Address i (39-16) - * This field defines the upp address bits of a 40-bit address that - * defines the end of a memory-mapped I/O region n - */ - ADDRMAP_REG(0x84), 0x00000048, 0x00000000, - ADDRMAP_REG(0x8C), 0x00000048, 0x00000000, - ADDRMAP_REG(0x94), 0x00000048, 0x00000000, - ADDRMAP_REG(0x9C), 0x00000048, 0x00000000, - ADDRMAP_REG(0xA4), 0x00000048, 0x00000000, - ADDRMAP_REG(0xAC), 0x00000048, 0x00000000, - ADDRMAP_REG(0xB4), 0x00000048, 0x00000000, - ADDRMAP_REG(0xBC), 0x00000048, 0x00000000, - - /* Memory-Mapped I/O Base i Registers - * F1:0x80 i = 0 - * F1:0x88 i = 1 - * F1:0x90 i = 2 - * F1:0x98 i = 3 - * F1:0xA0 i = 4 - * F1:0xA8 i = 5 - * F1:0xB0 i = 6 - * F1:0xB8 i = 7 - * [ 0: 0] Read Enable - * 0 = Reads disabled - * 1 = Reads Enabled - * [ 1: 1] Write Enable - * 0 = Writes disabled - * 1 = Writes Enabled - * [ 2: 2] Cpu Disable - * 0 = Cpu can use this I/O range - * 1 = Cpu requests do not use this I/O range - * [ 3: 3] Lock - * 0 = base/limit registers i are read/write - * 1 = base/limit registers i are read-only - * [ 7: 4] Reserved - * [31: 8] Memory-Mapped I/O Base Address i (39-16) - * This field defines the upper address bits of a 40bit address - * that defines the start of memory-mapped I/O region i - */ - ADDRMAP_REG(0x80), 0x000000f0, 0x00000000, - ADDRMAP_REG(0x88), 0x000000f0, 0x00000000, - ADDRMAP_REG(0x90), 0x000000f0, 0x00000000, - ADDRMAP_REG(0x98), 0x000000f0, 0x00000000, - ADDRMAP_REG(0xA0), 0x000000f0, 0x00000000, - ADDRMAP_REG(0xA8), 0x000000f0, 0x00000000, - ADDRMAP_REG(0xB0), 0x000000f0, 0x00000000, - ADDRMAP_REG(0xB8), 0x000000f0, 0x00000000, - - /* PCI I/O Limit i Registers - * F1:0xC4 i = 0 - * F1:0xCC i = 1 - * F1:0xD4 i = 2 - * F1:0xDC i = 3 - * [ 2: 0] Destination Node ID - * 000 = Node 0 - * 001 = Node 1 - * 010 = Node 2 - * 011 = Node 3 - * 100 = Node 4 - * 101 = Node 5 - * 110 = Node 6 - * 111 = Node 7 - * [ 3: 3] Reserved - * [ 5: 4] Destination Link ID - * 00 = Link 0 - * 01 = Link 1 - * 10 = Link 2 - * 11 = Link 3 - * [11: 6] Reserved - * [24:12] PCI I/O Limit Address i - * This field defines the end of PCI I/O region n - * [31:25] Reserved - */ - ADDRMAP_REG(0xC4), 0xFE000FC8, 0x00fff020, /* link 2 of CPU 0 --> AMD SR5690 */ - ADDRMAP_REG(0xCC), 0xFE000FC8, 0x00000000, - ADDRMAP_REG(0xD4), 0xFE000FC8, 0x00000000, - ADDRMAP_REG(0xDC), 0xFE000FC8, 0x00000000, - - /* PCI I/O Base i Registers - * F1:0xC0 i = 0 - * F1:0xC8 i = 1 - * F1:0xD0 i = 2 - * F1:0xD8 i = 3 - * [ 0: 0] Read Enable - * 0 = Reads Disabled - * 1 = Reads Enabled - * [ 1: 1] Write Enable - * 0 = Writes Disabled - * 1 = Writes Enabled - * [ 3: 2] Reserved - * [ 4: 4] VGA Enable - * 0 = VGA matches Disabled - * 1 = matches all address < 64K and where A[9:0] is in the - * range 3B0-3BB or 3C0-3DF independent of the base & limit registers - * [ 5: 5] ISA Enable - * 0 = ISA matches Disabled - * 1 = Blocks address < 64K and in the last 768 bytes of eack 1K block - * from matching agains this base/limit pair - * [11: 6] Reserved - * [24:12] PCI I/O Base i - * This field defines the start of PCI I/O region n - * [31:25] Reserved - */ -// ADDRMAP_REG(0xC0), 0xFE000FCC, 0x00001013, - ADDRMAP_REG(0xC8), 0xFE000FCC, 0x00000000, - ADDRMAP_REG(0xD0), 0xFE000FCC, 0x00000000, - ADDRMAP_REG(0xD8), 0xFE000FCC, 0x00000000, - - /* Config Base and Limit i Registers - * F1:0xE0 i = 0 - * F1:0xE4 i = 1 - * F1:0xE8 i = 2 - * F1:0xEC i = 3 - * [ 0: 0] Read Enable - * 0 = Reads Disabled - * 1 = Reads Enabled - * [ 1: 1] Write Enable - * 0 = Writes Disabled - * 1 = Writes Enabled - * [ 2: 2] Device Number Compare Enable - * 0 = The ranges are based on bus number - * 1 = The ranges are ranges of devices on bus 0 - * [ 3: 3] Reserved - * [ 6: 4] Destination Node - * 000 = Node 0 - * 001 = Node 1 - * 010 = Node 2 - * 011 = Node 3 - * 100 = Node 4 - * 101 = Node 5 - * 110 = Node 6 - * 111 = Node 7 - * [ 7: 7] Reserved - * [ 9: 8] Destination Link - * 00 = Link 0 - * 01 = Link 1 - * 10 = Link 2 - * 11 - Link 3 - * [15:10] Reserved - * [23:16] Bus Number Base i - * This field defines the lowest bus number in configuration region i - * [31:24] Bus Number Limit i - * This field defines the highest bus number in configuration region i - */ - ADDRMAP_REG(0xE0), 0x0000FC88, 0x05000203, /* link 2 of CPU 0 --> AMD SR5690 */ - ADDRMAP_REG(0xE4), 0x0000FC88, 0x00000000, - ADDRMAP_REG(0xE8), 0x0000FC88, 0x00000000, - ADDRMAP_REG(0xEC), 0x0000FC88, 0x00000000, - - }; - - static const unsigned int fam10h_register_values[] = { - /* Careful set limit registers before base registers which contain the enables */ - /* DRAM Limit i Registers - * F1:0x44 i = 0 - * F1:0x4C i = 1 - * F1:0x54 i = 2 - * F1:0x5C i = 3 - * F1:0x64 i = 4 - * F1:0x6C i = 5 - * F1:0x74 i = 6 - * F1:0x7C i = 7 - * [ 2: 0] Destination Node ID - * 000 = Node 0 - * 001 = Node 1 - * 010 = Node 2 - * 011 = Node 3 - * 100 = Node 4 - * 101 = Node 5 - * 110 = Node 6 - * 111 = Node 7 - * [ 7: 3] Reserved - * [10: 8] Interleave select - * specifies the values of A[14:12] to use with interleave enable. - * [15:11] Reserved - * [31:16] DRAM Limit Address i Bits 39-24 - * This field defines the upper address bits of a 40 bit address - * that define the end of the DRAM region. - */ - // ADDRMAP_REG(0x44), 0x0000f8f8, 0x00000000, - ADDRMAP_REG(0x4C), 0x0000f8f8, 0x00000001, - ADDRMAP_REG(0x54), 0x0000f8f8, 0x00000002, - ADDRMAP_REG(0x5C), 0x0000f8f8, 0x00000003, - ADDRMAP_REG(0x64), 0x0000f8f8, 0x00000004, - ADDRMAP_REG(0x6C), 0x0000f8f8, 0x00000005, - ADDRMAP_REG(0x74), 0x0000f8f8, 0x00000006, - ADDRMAP_REG(0x7C), 0x0000f8f8, 0x00000007, - - /* DRAM Base i Registers - * F1:0x40 i = 0 - * F1:0x48 i = 1 - * F1:0x50 i = 2 - * F1:0x58 i = 3 - * F1:0x60 i = 4 - * F1:0x68 i = 5 - * F1:0x70 i = 6 - * F1:0x78 i = 7 - * [ 0: 0] Read Enable - * 0 = Reads Disabled - * 1 = Reads Enabled - * [ 1: 1] Write Enable - * 0 = Writes Disabled - * 1 = Writes Enabled - * [ 7: 2] Reserved - * [10: 8] Interleave Enable - * 000 = No interleave - * 001 = Interleave on A[12] (2 nodes) - * 010 = reserved - * 011 = Interleave on A[12] and A[14] (4 nodes) - * 100 = reserved - * 101 = reserved - * 110 = reserved - * 111 = Interleve on A[12] and A[13] and A[14] (8 nodes) - * [15:11] Reserved - * [31:16] DRAM Base Address i Bits 39-24 - * This field defines the upper address bits of a 40-bit address - * that define the start of the DRAM region. - */ - // ADDRMAP_REG(0x40), 0x0000f8fc, 0x00000000, - ADDRMAP_REG(0x48), 0x0000f8fc, 0x00000000, - ADDRMAP_REG(0x50), 0x0000f8fc, 0x00000000, - ADDRMAP_REG(0x58), 0x0000f8fc, 0x00000000, - ADDRMAP_REG(0x60), 0x0000f8fc, 0x00000000, - ADDRMAP_REG(0x68), 0x0000f8fc, 0x00000000, - ADDRMAP_REG(0x70), 0x0000f8fc, 0x00000000, - ADDRMAP_REG(0x78), 0x0000f8fc, 0x00000000, - - /* Memory-Mapped I/O Limit i Registers - * F1:0x84 i = 0 - * F1:0x8C i = 1 - * F1:0x94 i = 2 - * F1:0x9C i = 3 - * F1:0xA4 i = 4 - * F1:0xAC i = 5 - * F1:0xB4 i = 6 - * F1:0xBC i = 7 - * [ 2: 0] Destination Node ID - * 000 = Node 0 - * 001 = Node 1 - * 010 = Node 2 - * 011 = Node 3 - * 100 = Node 4 - * 101 = Node 5 - * 110 = Node 6 - * 111 = Node 7 - * [ 3: 3] Reserved - * [ 5: 4] Destination Link ID - * 00 = Link 0 - * 01 = Link 1 - * 10 = Link 2 - * 11 = Link 3 - * [ 6: 6] Reserved - * [ 7: 7] Non-Posted - * 0 = CPU writes may be posted - * 1 = CPU writes must be non-posted - * [31: 8] Memory-Mapped I/O Limit Address i (39-16) - * This field defines the upp address bits of a 40-bit address that - * defines the end of a memory-mapped I/O region n - */ - ADDRMAP_REG(0x84), 0x00000048, 0x00000000, - ADDRMAP_REG(0x8C), 0x00000048, 0x00000000, - ADDRMAP_REG(0x94), 0x00000048, 0x00000000, - ADDRMAP_REG(0x9C), 0x00000048, 0x00000000, - ADDRMAP_REG(0xA4), 0x00000048, 0x00000000, - ADDRMAP_REG(0xAC), 0x00000048, 0x00000000, - ADDRMAP_REG(0xB4), 0x00000048, 0x00000000, - ADDRMAP_REG(0xBC), 0x00000048, 0x00000000, - - /* Memory-Mapped I/O Base i Registers - * F1:0x80 i = 0 - * F1:0x88 i = 1 - * F1:0x90 i = 2 - * F1:0x98 i = 3 - * F1:0xA0 i = 4 - * F1:0xA8 i = 5 - * F1:0xB0 i = 6 - * F1:0xB8 i = 7 - * [ 0: 0] Read Enable - * 0 = Reads disabled - * 1 = Reads Enabled - * [ 1: 1] Write Enable - * 0 = Writes disabled - * 1 = Writes Enabled - * [ 2: 2] Cpu Disable - * 0 = Cpu can use this I/O range - * 1 = Cpu requests do not use this I/O range - * [ 3: 3] Lock - * 0 = base/limit registers i are read/write - * 1 = base/limit registers i are read-only - * [ 7: 4] Reserved - * [31: 8] Memory-Mapped I/O Base Address i (39-16) - * This field defines the upper address bits of a 40bit address - * that defines the start of memory-mapped I/O region i - */ - ADDRMAP_REG(0x80), 0x000000f0, 0x00000000, - ADDRMAP_REG(0x88), 0x000000f0, 0x00000000, - ADDRMAP_REG(0x90), 0x000000f0, 0x00000000, - ADDRMAP_REG(0x98), 0x000000f0, 0x00000000, - ADDRMAP_REG(0xA0), 0x000000f0, 0x00000000, - ADDRMAP_REG(0xA8), 0x000000f0, 0x00000000, - ADDRMAP_REG(0xB0), 0x000000f0, 0x00000000, - ADDRMAP_REG(0xB8), 0x000000f0, 0x00000000, - - /* PCI I/O Limit i Registers - * F1:0xC4 i = 0 - * F1:0xCC i = 1 - * F1:0xD4 i = 2 - * F1:0xDC i = 3 - * [ 2: 0] Destination Node ID - * 000 = Node 0 - * 001 = Node 1 - * 010 = Node 2 - * 011 = Node 3 - * 100 = Node 4 - * 101 = Node 5 - * 110 = Node 6 - * 111 = Node 7 - * [ 3: 3] Reserved - * [ 5: 4] Destination Link ID - * 00 = Link 0 - * 01 = Link 1 - * 10 = Link 2 - * 11 = Link 3 - * [11: 6] Reserved - * [24:12] PCI I/O Limit Address i - * This field defines the end of PCI I/O region n - * [31:25] Reserved - */ - ADDRMAP_REG(0xC4), 0xFE000FC8, 0x00fff020, /* link 2 of CPU 0 --> AMD SR5690 */ - ADDRMAP_REG(0xCC), 0xFE000FC8, 0x00000000, - ADDRMAP_REG(0xD4), 0xFE000FC8, 0x00000000, - ADDRMAP_REG(0xDC), 0xFE000FC8, 0x00000000, - - /* PCI I/O Base i Registers - * F1:0xC0 i = 0 - * F1:0xC8 i = 1 - * F1:0xD0 i = 2 - * F1:0xD8 i = 3 - * [ 0: 0] Read Enable - * 0 = Reads Disabled - * 1 = Reads Enabled - * [ 1: 1] Write Enable - * 0 = Writes Disabled - * 1 = Writes Enabled - * [ 3: 2] Reserved - * [ 4: 4] VGA Enable - * 0 = VGA matches Disabled - * 1 = matches all address < 64K and where A[9:0] is in the - * range 3B0-3BB or 3C0-3DF independent of the base & limit registers - * [ 5: 5] ISA Enable - * 0 = ISA matches Disabled - * 1 = Blocks address < 64K and in the last 768 bytes of eack 1K block - * from matching agains this base/limit pair - * [11: 6] Reserved - * [24:12] PCI I/O Base i - * This field defines the start of PCI I/O region n - * [31:25] Reserved - */ -// ADDRMAP_REG(0xC0), 0xFE000FCC, 0x00001013, - ADDRMAP_REG(0xC8), 0xFE000FCC, 0x00000000, - ADDRMAP_REG(0xD0), 0xFE000FCC, 0x00000000, - ADDRMAP_REG(0xD8), 0xFE000FCC, 0x00000000, - - /* Config Base and Limit i Registers - * F1:0xE0 i = 0 - * F1:0xE4 i = 1 - * F1:0xE8 i = 2 - * F1:0xEC i = 3 - * [ 0: 0] Read Enable - * 0 = Reads Disabled - * 1 = Reads Enabled - * [ 1: 1] Write Enable - * 0 = Writes Disabled - * 1 = Writes Enabled - * [ 2: 2] Device Number Compare Enable - * 0 = The ranges are based on bus number - * 1 = The ranges are ranges of devices on bus 0 - * [ 3: 3] Reserved - * [ 6: 4] Destination Node - * 000 = Node 0 - * 001 = Node 1 - * 010 = Node 2 - * 011 = Node 3 - * 100 = Node 4 - * 101 = Node 5 - * 110 = Node 6 - * 111 = Node 7 - * [ 7: 7] Reserved - * [ 9: 8] Destination Link - * 00 = Link 0 - * 01 = Link 1 - * 10 = Link 2 - * 11 - Link 3 - * [15:10] Reserved - * [23:16] Bus Number Base i - * This field defines the lowest bus number in configuration region i - * [31:24] Bus Number Limit i - * This field defines the highest bus number in configuration region i - */ - ADDRMAP_REG(0xE0), 0x0000FC88, 0x05000203, /* link 2 of CPU 0 --> AMD SR5690 */ - ADDRMAP_REG(0xE4), 0x0000FC88, 0x00000000, - ADDRMAP_REG(0xE8), 0x0000FC88, 0x00000000, - ADDRMAP_REG(0xEC), 0x0000FC88, 0x00000000, - - }; - - int max; - uint8_t fam15h = 0; - uint32_t family; - - family = cpuid_eax(0x80000001); - family = ((family & 0xf00000) >> 16) | ((family & 0xf00) >> 8); - - if (family >= 0x6f) - /* Family 15h or later */ - fam15h = 1; - - if (fam15h) { - max = ARRAY_SIZE(fam15h_register_values); - setup_resource_map(fam15h_register_values, max); - } else { - max = ARRAY_SIZE(fam10h_register_values); - setup_resource_map(fam10h_register_values, max); - } -} diff --git a/src/mainboard/asus/kcma-d8/romstage.c b/src/mainboard/asus/kcma-d8/romstage.c deleted file mode 100644 index 51d178fe88..0000000000 --- a/src/mainboard/asus/kcma-d8/romstage.c +++ /dev/null @@ -1,606 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2015 - 2016 Raptor Engineering, LLC - * - * Copyright (C) 2007 AMD - * Written by Yinghai Lu for AMD. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include "cpu/amd/quadcore/quadcore.c" - -#define SERIAL_0_DEV PNP_DEV(0x2e, W83667HG_A_SP1) -#define SERIAL_1_DEV PNP_DEV(0x2e, W83667HG_A_SP2) - -int spd_read_byte(unsigned int device, unsigned int address); - -inline int spd_read_byte(unsigned int device, unsigned int address) -{ - return do_smbus_read_byte(SMBUS_AUX_IO_BASE, device, address); -} - -/* - * ASUS KCMA-D8 specific SPD enable/disable magic. - * - * Setting SP5100 GPIOs 59 and 60 controls an SPI mux with four settings: - * 0: Disabled - * 1: Normal SPI access - * 2: CPU0 SPD - * 3: CPU1 SPD - * - * Disable SPD access after RAM init to allow access to standard SMBus/I2C offsets - * which is required e.g. by lm-sensors. - */ - -/* Relevant GPIO register information is available in the - * AMD SP5100 Register Reference Guide rev. 3.03, page 130 - */ -static void switch_spd_mux(uint8_t channel) -{ - uint8_t byte; - - byte = pci_read_config8(PCI_DEV(0, 0x14, 0), 0x54); - byte &= ~0xc; /* Clear SPD mux GPIOs */ - byte &= ~0xc0; /* Enable SPD mux GPIO output drivers */ - byte |= (channel << 2) & 0xc; /* Set SPD mux GPIOs */ - pci_write_config8(PCI_DEV(0, 0x14, 0), 0x54, byte); -} - -static const uint8_t spd_addr_fam15[] = { - // Socket 0 Node 0 ("Node 0") - RC00, DIMM0, DIMM1, 0, 0, DIMM2, DIMM3, 0, 0, - // Socket 1 Node 0 ("Node 1") - RC01, DIMM0, DIMM1, 0, 0, DIMM2, DIMM3, 0, 0, -}; - -static const uint8_t spd_addr_fam10[] = { - // Socket 0 Node 0 ("Node 0") - RC00, DIMM0, DIMM1, 0, 0, DIMM2, DIMM3, 0, 0, - // Socket 1 Node 0 ("Node 1") - RC01, DIMM0, DIMM1, 0, 0, DIMM2, DIMM3, 0, 0, -}; - -void activate_spd_rom(const struct mem_controller *ctrl) { - printk(BIOS_DEBUG, "activate_spd_rom() for node %02x\n", ctrl->node_id); - if (ctrl->node_id == 0) { - printk(BIOS_DEBUG, "enable_spd_node0()\n"); - switch_spd_mux(0x2); - } else if (ctrl->node_id == 1) { - printk(BIOS_DEBUG, "enable_spd_node1()\n"); - switch_spd_mux(0x3); - } -} - -/* Voltages are specified by index - * Valid indices for this platform are: - * 0: 1.5V - * 1: 1.35V - * 2: 1.25V - * 3: 1.15V - */ -static void set_ddr3_voltage(uint8_t node, uint8_t index) { - uint8_t byte; - uint8_t value = 0; - - if (index == 0) - value = 0x0; - else if (index == 1) - value = 0x1; - else if (index == 2) - value = 0x4; - else if (index == 3) - value = 0x5; - if (node == 1) - value <<= 1; - - /* Set GPIOs */ - byte = pci_read_config8(PCI_DEV(0, 0x14, 3), 0xd1); - if (node == 0) - byte &= ~0x5; - if (node == 1) - byte &= ~0xa; - byte |= value; - pci_write_config8(PCI_DEV(0, 0x14, 3), 0xd1, byte); - - /* Enable GPIO output drivers */ - byte = pci_read_config8(PCI_DEV(0, 0x14, 3), 0xd0); - byte &= 0x0f; - pci_write_config8(PCI_DEV(0, 0x14, 3), 0xd0, byte); - - printk(BIOS_DEBUG, "Node %02d DIMM voltage set to index %02x\n", node, index); -} - -void DIMMSetVoltages(struct MCTStatStruc *pMCTstat, - struct DCTStatStruc *pDCTstatA) { - /* This mainboard allows the DIMM voltage to be set per-socket. - * Therefore, for each socket, iterate over all DIMMs to find the - * lowest supported voltage common to all DIMMs on that socket. - */ - uint8_t nvram; - uint8_t dimm; - uint8_t node; - uint8_t socket; - uint8_t allowed_voltages = 0xf; /* The mainboard VRMs allow 1.15V, 1.25V, 1.35V, and 1.5V */ - uint8_t socket_allowed_voltages = allowed_voltages; - uint32_t set_voltage = 0; - - if (get_option(&nvram, "minimum_memory_voltage") == CB_SUCCESS) { - switch (nvram) { - case 2: - allowed_voltages = 0x7; /* Allow 1.25V, 1.35V, and 1.5V */ - break; - case 1: - allowed_voltages = 0x3; /* Allow 1.35V and 1.5V */ - break; - case 0: - default: - allowed_voltages = 0x1; /* Allow 1.5V only */ - break; - } - } - - for (node = 0; node < MAX_NODES_SUPPORTED; node++) { - socket = node; - struct DCTStatStruc *pDCTstat; - pDCTstat = pDCTstatA + node; - - /* reset socket_allowed_voltages before processing each socket */ - socket_allowed_voltages = allowed_voltages; - - if (pDCTstat->NodePresent) { - for (dimm = 0; dimm < MAX_DIMMS_SUPPORTED; dimm++) { - if (pDCTstat->DIMMValid & (1 << dimm)) { - socket_allowed_voltages &= pDCTstat->DimmSupportedVoltages[dimm]; - } - } - - /* Set voltages */ - if (socket_allowed_voltages & 0x8) { - set_voltage = 0x8; - set_ddr3_voltage(socket, 3); - } else if (socket_allowed_voltages & 0x4) { - set_voltage = 0x4; - set_ddr3_voltage(socket, 2); - } else if (socket_allowed_voltages & 0x2) { - set_voltage = 0x2; - set_ddr3_voltage(socket, 1); - } else { - set_voltage = 0x1; - set_ddr3_voltage(socket, 0); - } - - /* Save final DIMM voltages for MCT and SMBIOS use */ - for (dimm = 0; dimm < MAX_DIMMS_SUPPORTED; dimm++) { - pDCTstat->DimmConfiguredVoltage[dimm] = set_voltage; - } - } - } - - /* Allow the DDR supply voltages to settle */ - udelay(100000); -} - -static void set_peripheral_control_lines(void) { - uint8_t byte; - - /* Enable PCICLK5 */ - outb(0x41, 0xcd6); - outb(0x02, 0xcd7); - - /* Enable the RTC AltCentury register */ - outb(0x41, 0xcd6); - byte = inb(0xcd7); - byte |= 0x10; - outb(byte, 0xcd7); -} - -#ifdef TEST_MEMORY -static void execute_memory_test(void) -{ - /* Test DRAM functionality */ - uint32_t i; - uint32_t v; - uint32_t w; - uint32_t x; - uint32_t y; - uint32_t z; - uint32_t *dataptr; - uint32_t readback; - uint32_t start = 0x300000; - printk(BIOS_DEBUG, "Writing test pattern 1 to memory...\n"); - for (i = 0; i < 0x1000000; i = i + 8) { - dataptr = (void *)(start + i); - *dataptr = 0x55555555; - dataptr = (void *)(start + i + 4); - *dataptr = 0xaaaaaaaa; - } - printk(BIOS_DEBUG, "Done!\n"); - printk(BIOS_DEBUG, "Testing memory...\n"); - for (i = 0; i < 0x1000000; i = i + 8) { - dataptr = (void *)(start + i); - readback = *dataptr; - if (readback != 0x55555555) - printk(BIOS_DEBUG, "%p: INCORRECT VALUE %08x (should have been %08x)\n", dataptr, readback, 0x55555555); - dataptr = (void *)(start + i + 4); - readback = *dataptr; - if (readback != 0xaaaaaaaa) - printk(BIOS_DEBUG, "%p: INCORRECT VALUE %08x (should have been %08x)\n", dataptr, readback, 0xaaaaaaaa); - } - printk(BIOS_DEBUG, "Done!\n"); - printk(BIOS_DEBUG, "Writing test pattern 2 to memory...\n"); - /* Set up the PRNG seeds for initial write */ - w = 0x55555555; - x = 0xaaaaaaaa; - y = 0x12345678; - z = 0x87654321; - for (i = 0; i < 0x1000000; i = i + 4) { - /* Use Xorshift as a PRNG to stress test the bus */ - v = x; - v ^= v << 11; - v ^= v >> 8; - x = y; - y = z; - z = w; - w ^= w >> 19; - w ^= v; - dataptr = (void *)(start + i); - *dataptr = w; - } - printk(BIOS_DEBUG, "Done!\n"); - printk(BIOS_DEBUG, "Testing memory...\n"); - /* Reset the PRNG seeds for readback */ - w = 0x55555555; - x = 0xaaaaaaaa; - y = 0x12345678; - z = 0x87654321; - for (i = 0; i < 0x1000000; i = i + 4) { - /* Use Xorshift as a PRNG to stress test the bus */ - v = x; - v ^= v << 11; - v ^= v >> 8; - x = y; - y = z; - z = w; - w ^= w >> 19; - w ^= v; - dataptr = (void *)(start + i); - readback = *dataptr; - if (readback != w) - printk(BIOS_DEBUG, "%p: INCORRECT VALUE %08x (should have been %08x)\n", dataptr, readback, w); - } - printk(BIOS_DEBUG, "Done!\n"); -} -#endif - -static spinlock_t printk_spinlock CAR_GLOBAL; - -spinlock_t *romstage_console_lock(void) -{ - return car_get_var_ptr(&printk_spinlock); -} - -void initialize_romstage_console_lock(void) -{ - spin_unlock(romstage_console_lock()); -} - -static spinlock_t nvram_cbfs_spinlock CAR_GLOBAL; - -spinlock_t *romstage_nvram_cbfs_lock(void) -{ - return car_get_var_ptr(&nvram_cbfs_spinlock); -} - -void initialize_romstage_nvram_cbfs_lock(void) -{ - spin_unlock(romstage_nvram_cbfs_lock()); -} - -static spinlock_t microcode_cbfs_spinlock CAR_GLOBAL; - -spinlock_t *romstage_microcode_cbfs_lock(void) -{ - return car_get_var_ptr(µcode_cbfs_spinlock); -} - -void initialize_romstage_microcode_cbfs_lock(void) -{ - spin_unlock(romstage_microcode_cbfs_lock()); -} - -void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) -{ - uint32_t esp; - __asm__ volatile ( - "movl %%esp, %0" - : "=r" (esp) - ); - - struct sys_info *sysinfo = get_sysinfo(); - - /* Limit the maximum HT speed to 2.6GHz to prevent lockups - * due to HT CPU <--> CPU wiring not being validated to 3.2GHz - */ - sysinfo->ht_link_cfg.ht_speed_limit = 2600; - - uint32_t bsp_apicid = 0, val; - uint8_t byte; - uint8_t power_on_reset = 0; - msr_t msr; - - int s3resume = acpi_is_wakeup_s3(); - - if (!cpu_init_detectedx && boot_cpu()) { - /* Initial timestamp */ - timestamp_init(timestamp_get()); - timestamp_add_now(TS_START_ROMSTAGE); - - /* Initialize the printk, nvram CBFS, and microcode CBFS spinlocks */ - initialize_romstage_console_lock(); - initialize_romstage_nvram_cbfs_lock(); - initialize_romstage_microcode_cbfs_lock(); - - /* Nothing special needs to be done to find bus 0 */ - /* Allow the HT devices to be found */ - set_bsp_node_CHtExtNodeCfgEn(); - enumerate_ht_chain(); - - /* SR56x0 pcie bridges block pci_locate_device() before pcie training. - * disable all pcie bridges on SR56x0 to work around it - */ - sr5650_disable_pcie_bridge(); - - /* Initialize southbridge */ - sb7xx_51xx_pci_port80(); - - /* Configure secondary serial port pin mux */ - winbond_set_pinmux(SERIAL_1_DEV, 0x2a, W83667HG_SPI_PINMUX_GPIO4_SERIAL_B_MASK, W83667HG_SPI_PINMUX_SERIAL_B); - - /* Initialize early serial */ - winbond_enable_serial(SERIAL_0_DEV, CONFIG_TTYS0_BASE); - console_init(); - - /* Disable LPC legacy DMA support to prevent lockup */ - byte = pci_read_config8(PCI_DEV(0, 0x14, 3), 0x78); - byte &= ~(1 << 0); - pci_write_config8(PCI_DEV(0, 0x14, 3), 0x78, byte); - } - - printk(BIOS_SPEW, "Initial stack pointer: %08x\n", esp); - - post_code(0x30); - - if (bist == 0) - bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo); - - post_code(0x32); - - enable_sr5650_dev8(); - sb7xx_51xx_lpc_init(); - - if (CONFIG_MAX_PHYSICAL_CPUS != 2) - printk(BIOS_WARNING, "CONFIG_MAX_PHYSICAL_CPUS is %d, but this is a dual socket AMD C32 board!\n", CONFIG_MAX_PHYSICAL_CPUS); - - /* Halt if there was a built in self test failure */ - report_bist_failure(bist); - - val = cpuid_eax(1); - printk(BIOS_DEBUG, "BSP Family_Model: %08x\n", val); - printk(BIOS_DEBUG, "*sysinfo range: [%p,%p]\n",sysinfo,sysinfo+1); - printk(BIOS_DEBUG, "bsp_apicid = %02x\n", bsp_apicid); - printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx); - - /* Setup sysinfo defaults */ - set_sysinfo_in_ram(0); - - if (!sb7xx_51xx_decode_last_reset()) - power_on_reset = 1; - - initialize_mca(1, power_on_reset); - update_microcode(val); - - post_code(0x33); - - cpuSetAMDMSR(0); - post_code(0x34); - - amd_ht_init(sysinfo); - amd_ht_fixup(sysinfo); - post_code(0x35); - - /* Setup nodes PCI space and start core 0 AP init. */ - finalize_node_setup(sysinfo); - - /* Setup any mainboard PCI settings etc. */ - setup_mb_resource_map(); - initialize_mca(0, power_on_reset); - post_code(0x36); - - /* Wait for all the APs core0 started by finalize_node_setup. */ - wait_all_core0_started(); - - /* run _early_setup before soft-reset. */ - sr5650_early_setup(); - sb7xx_51xx_early_setup(); - - if (CONFIG(LOGICAL_CPUS)) { - /* Core0 on each node is configured. Now setup any additional cores. */ - printk(BIOS_DEBUG, "start_other_cores()\n"); - start_other_cores(bsp_apicid); - post_code(0x37); - wait_all_other_cores_started(bsp_apicid); - } - - if (CONFIG(SET_FIDVID)) { - msr = rdmsr(MSR_COFVID_STS); - printk(BIOS_DEBUG, "\nBegin FIDVID MSR 0xc0010071 0x%08x 0x%08x\n", msr.hi, msr.lo); - - /* FIXME: The sb fid change may survive the warm reset and only need to be done once */ - enable_fid_change_on_sb(sysinfo->sbbusn, sysinfo->sbdn); - - post_code(0x39); - - #if CONFIG(SET_FIDVID) - if (!warm_reset_detect(0)) { // BSP is node 0 - init_fidvid_bsp(bsp_apicid, sysinfo->nodes); - } else { - init_fidvid_stage2(bsp_apicid, 0); // BSP is node 0 - } - #endif - - post_code(0x3A); - - /* show final fid and vid */ - msr = rdmsr(MSR_COFVID_STS); - printk(BIOS_DEBUG, "End FIDVIDMSR 0xc0010071 0x%08x 0x%08x\n", msr.hi, msr.lo); - } - - post_code(0x38); - - init_timer(); // Need to use TMICT to synconize FID/VID - - sr5650_htinit(); - - /* Reset for HT, FIDVID, PLL and errata changes to take effect. */ - if (!warm_reset_detect(0)) { - printk(BIOS_INFO, "...WARM RESET...\n\n\n"); - soft_reset(); - die("After soft_reset - shouldn't see this message!!!\n"); - } - - sr5650_htinit_dect_and_enable_isochronous_link(); - - /* Set default DDR memory voltage - * This will be overridden later during RAM initialization - */ - set_lpc_sticky_ctl(1); /* Retain LPC/IMC GPIO configuration during S3 sleep */ - if (!s3resume) { /* Avoid supply voltage glitches while the DIMMs are retaining data */ - set_ddr3_voltage(0, 0); /* Node 0 */ - set_ddr3_voltage(1, 0); /* Node 1 */ - } - - /* Set up peripheral control lines */ - set_peripheral_control_lines(); - - post_code(0x3B); - - /* Wait for all APs to be stopped, otherwise RAM initialization may hang */ - if (CONFIG(LOGICAL_CPUS)) - wait_all_other_cores_stopped(bsp_apicid); - - /* It's the time to set ctrl in sysinfo now; */ - printk(BIOS_DEBUG, "fill_mem_ctrl() detected %d nodes\n", sysinfo->nodes); - if (is_fam15h()) - fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr_fam15); - else - fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr_fam10); - post_code(0x3D); - -#if 0 - /* FIXME - * After the AMD K10 code has been converted to use - * CONFIG(DEBUG_SMBUS) uncomment this block - */ - if (CONFIG(DEBUG_SMBUS)) { - dump_spd_registers(&cpu[0]); - dump_smbus_registers(); - } -#endif - - post_code(0x40); - - raminit_amdmct(sysinfo); - -#ifdef TEST_MEMORY - execute_memory_test(); -#endif - - if (s3resume) - cbmem_initialize(); - else - cbmem_initialize_empty(); - post_code(0x41); - - romstage_handoff_init(s3resume); - - amdmct_cbmem_store_info(sysinfo); - - printk(BIOS_DEBUG, "disable_spd()\n"); - switch_spd_mux(0x1); - - sr5650_before_pci_init(); - sb7xx_51xx_before_pci_init(); - - /* Configure SP5100 GPIOs to match vendor settings */ - pci_write_config16(PCI_DEV(0, 0x14, 0), 0x50, 0x0170); - pci_write_config16(PCI_DEV(0, 0x14, 0), 0x54, 0x0707); - pci_write_config16(PCI_DEV(0, 0x14, 0), 0x56, 0x0bb0); - pci_write_config16(PCI_DEV(0, 0x14, 0), 0x5a, 0x0ff0); -} - -/** - * BOOL AMD_CB_ManualBUIDSwapList(u8 Node, u8 Link, u8 **List) - * Description: - * This routine is called every time a non-coherent chain is processed. - * BUID assignment may be controlled explicitly on a non-coherent chain. Provide a - * swap list. The first part of the list controls the BUID assignment and the - * second part of the list provides the device to device linking. Device orientation - * can be detected automatically, or explicitly. See documentation for more details. - * - * Automatic non-coherent init assigns BUIDs starting at 1 and incrementing sequentially - * based on each device's unit count. - * - * Parameters: - * @param[in] node = The node on which this chain is located - * @param[in] link = The link on the host for this chain - * @param[out] List = supply a pointer to a list - */ -BOOL AMD_CB_ManualBUIDSwapList (u8 node, u8 link, const u8 **List) -{ - /* Force BUID to 0 */ - static const u8 swaplist[] = {0, 0, 0xFF, 0, 0xFF}; - if ((node == 0) && (link == 2)) { /* BSP SB link */ - *List = swaplist; - return 1; - } - - return 0; -} diff --git a/src/mainboard/asus/kcma-d8/spd_notes.txt b/src/mainboard/asus/kcma-d8/spd_notes.txt deleted file mode 100644 index d944229f00..0000000000 --- a/src/mainboard/asus/kcma-d8/spd_notes.txt +++ /dev/null @@ -1,46 +0,0 @@ -==================================================================================================== -SPD mux -==================================================================================================== - SP5100 - GPIO 60 GPIO 59 -Disabled 0 0 -Normal operation 0 1 -CPU 0 SPD 1 0 -CPU 1 SPD 1 1 - -==================================================================================================== -W83795 -==================================================================================================== - -Sensor mappings: -CPU_FAN1: FAN1 -CPU_FAN2: FAN2 -FRNT_FAN1: FAN3 -FRNT_FAN2: FAN4 -FRNT_FAN3: FAN5 -FRNT_FAN4: FAN6 -FRNT_FAN5: FAN7 -REAR_FAN1: FAN8 - -==================================================================================================== -Other hardware -==================================================================================================== - -RECOVERY1 middle pin is connected to southbridge (AMD SP5100) GPIO 61 -Normal is HIGH, recovery is LOW. - -+12VSB is generated using a charge pump attached to pin 7 of PU24 (APW7145). - -The +12VSB standby voltage to each bank of DIMMs is switched by a bank of small FETs located close to each RAM power regulator control chip. -The +12V primary voltage (lower left pin of the FET placed on the upper left of the control chip of the second node) is also connected to the 232GE located near the PCI slot. - -The control line running to the gates of the +12VSB control FETs is connected to the +5VSB power for the USB ports. -That line in turn is connected to +5VSB via the lone P06P03G PMOS transistor on the reverse side of the board, near the center on the lower half. -The gate of that transistor is connected via a resistor to the source of the P06P03G PMOS transistor located adjacent to the unpopulated SMA clock header. -The gate of that transistor is connected directly to the drain of the small FET directly below it. -After that, there's a cascade of small FETs and resistors in that region, eventually leading to SuperIO pin 81. - -SuperIO pin 81 (VSBGATE#) enables the standby voltage rails when set LOW. -VSBGATE# is reset on every assertion of PWRGOOD. - -Setting SuperIO LDN 9 CRF4 bits 1 or 0 (or both) to 0 disables NICB. diff --git a/src/mainboard/asus/kfsn4-dre/Kconfig b/src/mainboard/asus/kfsn4-dre/Kconfig deleted file mode 100644 index ff980807dd..0000000000 --- a/src/mainboard/asus/kfsn4-dre/Kconfig +++ /dev/null @@ -1,88 +0,0 @@ -if BOARD_ASUS_KFSN4_DRE - -config BOARD_SPECIFIC_OPTIONS - def_bool y - select CPU_AMD_SOCKET_F_1207 - select DIMM_DDR2 - select DIMM_REGISTERED - select NORTHBRIDGE_AMD_AMDFAM10 - select SOUTHBRIDGE_NVIDIA_CK804 - select SUPERIO_WINBOND_W83627THG - select PARALLEL_CPU_INIT - select HAVE_OPTION_TABLE - select HAVE_CMOS_DEFAULT - select HAVE_PIRQ_TABLE - select HAVE_MP_TABLE - select HAVE_ACPI_TABLES - select LIFT_BSP_APIC_ID - select BOARD_ROMSIZE_KB_1024 - select ENABLE_APIC_EXT_ID - select DRIVERS_I2C_W83793 - select DRIVERS_XGI_Z9S - select POWER_STATE_DEFAULT_ON_AFTER_FAILURE - -config MAINBOARD_DIR - string - default asus/kfsn4-dre - -config BOOTBLOCK_MAINBOARD_INIT - string - default "mainboard/asus/kfsn4-dre/bootblock.c" - -config DCACHE_RAM_BASE - hex - default 0xc4000 - -config DCACHE_RAM_SIZE - hex - default 0x0c000 - -config APIC_ID_OFFSET - hex - default 0x0 - -config MAINBOARD_PART_NUMBER - string - default "KFSN4-DRE" - -config HW_MEM_HOLE_SIZEK - hex - default 0x100000 - -config MAX_CPUS - int - default 12 - -config MAX_PHYSICAL_CPUS - int - default 2 - -config HT_CHAIN_UNITID_BASE - hex - default 0x0 - -config HT_CHAIN_END_UNITID_BASE - hex - default 0x20 - -config IRQ_SLOT_COUNT - int - default 13 - -config CK804_PCI_E_X - int - default 1 - -config CK804_PCIE_PME_WAKE - bool - default y - -config ONBOARD_VGA_IS_PRIMARY - bool - default y - -config MAX_REBOOT_CNT - int - default 10 - -endif # BOARD_ASUS_KFSN4_DRE diff --git a/src/mainboard/asus/kfsn4-dre/Kconfig.name b/src/mainboard/asus/kfsn4-dre/Kconfig.name deleted file mode 100644 index fc25c85a5b..0000000000 --- a/src/mainboard/asus/kfsn4-dre/Kconfig.name +++ /dev/null @@ -1,2 +0,0 @@ -config BOARD_ASUS_KFSN4_DRE - bool "KFSN4-DRE" diff --git a/src/mainboard/asus/kfsn4-dre/Makefile.inc b/src/mainboard/asus/kfsn4-dre/Makefile.inc deleted file mode 100644 index 91d4b39c32..0000000000 --- a/src/mainboard/asus/kfsn4-dre/Makefile.inc +++ /dev/null @@ -1,16 +0,0 @@ -# -# This file is part of the coreboot project. -# -# This program is free software; you can redistribute it and/or modify -# it under the terms of the GNU General Public License as published by -# the Free Software Foundation; version 2 of the License. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# - -romstage-y += resourcemap.c - -ramstage-y += get_bus_conf.c diff --git a/src/mainboard/asus/kfsn4-dre/acpi/pm_ctrl.asl b/src/mainboard/asus/kfsn4-dre/acpi/pm_ctrl.asl deleted file mode 100644 index bde6fb628d..0000000000 --- a/src/mainboard/asus/kfsn4-dre/acpi/pm_ctrl.asl +++ /dev/null @@ -1,241 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2015 Timothy Pearson , Raptor Engineering - * Copyright (C) 2010 - 2012 Advanced Micro Devices, Inc. - * Copyright (C) 2004 Nick Barker - * Copyright (C) 2007, 2008 Rudolf Marek - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -/* - * WARNING: Sleep/Wake is a work in progress and is still somewhat flaky! - */ - - /* SuperIO control port */ - Name (SPIO, 0x2E) - - /* SuperIO control map */ - OperationRegion (SPIM, SystemIO, SPIO, 0x02) - Field (SPIM, ByteAcc, NoLock, Preserve) { - INDX, 8, - DATA, 8 - } - - /* SuperIO control registers */ - IndexField (INDX, DATA, ByteAcc, NoLock, Preserve) { - Offset (0x07), - CR07, 8, /* Logical device number */ - Offset (0x2C), - CR2C, 8, /* GPIO3 multiplexed pin selection */ - Offset (0x30), - CR30, 8, /* Logical device activation control register */ - Offset (0xE0), - CRE0, 8, /* Wake control register */ - Offset (0xE6), - CRE6, 8, /* Mouse wake event configuration register */ - Offset (0xF1), - CRF1, 8, /* GPIO3 data register */ - Offset (0xF3), - CRF3, 8, /* SUSLED mode register */ - Offset (0xF6), - CRF6, 8, /* SMI/PME event generation control register */ - Offset (0xF9), - CRF9, 8, /* ACPI PME configuration register */ - } - - /* Southbridge control ports */ - /* Both are offsets from PM base address (0x2000) */ - Name (SBC1, 0x2090) /* Offset 0x90 */ - Name (SBC2, 0x2400) /* Offset 0x400 */ - - /* Southbridge control maps */ - OperationRegion (SBM1, SystemIO, SBC1, 0x10) - Field (SBM1, ByteAcc, NoLock, Preserve) { - S1CT, 2, - Offset (0x04), - S3CT, 2, - Offset (0x08), - S4CT, 2, - Offset (0x0C), - S5CT, 2, - } - OperationRegion (SBM2, SystemIO, SBC2, 0x08) - Field (SBM2, ByteAcc, NoLock, Preserve) { - , 15, - PS1S, 1, - , 31, - PS1E, 1, - } - - /* Wake status package */ - Name(WKST,Package(){Zero, Zero}) - - /* - * \_WAK System Wake method - * - * Entry: - * Arg0=The value of the sleeping state S1=1, S2=2 - * - * Exit: - * Return package of 2 DWords - * Dword 1 - Status - * 0x00000000 wake succeeded - * 0x00000001 Wake was signaled but failed due to lack of power - * 0x00000002 Wake was signaled but failed due to thermal condition - * Dword 2 - Power Supply state - * if non-zero the effective S-state the power supply entered - */ - Method(\_WAK, 1) { - /* Set up LEDs */ - /* Access SuperIO GPIO3/GPIO4 device */ - Store(0x87, INDX) - Store(0x87, INDX) - Store(0x09, CR07) - - /* Set GPIO3 pin 64 (power LED) to GP37 mode */ - And(CR2C, 0xF3, Local0) - Or(Local0, 0x04, CR2C) - - /* Set power LED to steady on */ - Or(CRF1, 0x80, CRF1) - - /* Restore default SuperIO access */ - Store(0xAA, INDX) - - /* Configure SuperIO for wake */ - /* Access SuperIO ACPI device */ - Store(0x87, INDX) - Store(0x87, INDX) - Store(0x0A, CR07) - - if (LEqual(Arg0, One)) /* Resuming from power state S1 */ - { - /* Set power management to SMI mode and disable SMI events */ - And(CRF9, 0xFA, CRF9) - - /* Deactivate the ACPI device */ - Store(Zero, CR30) - - /* Disable PS/2 SMI/PME events */ - And(CRF6, 0xCF, CRF6) - } - if (Lor(LEqual(Arg0, 0x03), LEqual(Arg0, 0x04))) /* Resuming from power state S3 or S4 */ - { - /* Disable PS/2 wake */ - And(CRE0, 0x1D, CRE0) - And(CRE6, 0x7F, CRE6) - } - - /* Restore default SuperIO access */ - Store(0xAA, INDX) - - /* Configure southbridge for wake */ - Store(Zero, PS1E) - Store(0x02, S1CT) - Store(0x02, S3CT) - Store(0x02, S4CT) - Store(0x02, S5CT) - Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ - - Return(WKST) - } /* End Method(\_WAK) */ - - /* - * \_PTS - Prepare to Sleep method - * - * Entry: - * Arg0=The value of the sleeping state S1=1, S2=2, etc - * - * Exit: - * -none- - * - * The _PTS control method is executed at the beginning of the sleep process - * for S1-S5. The sleeping value is passed to the _PTS control method. This - * control method may be executed a relatively long time before entering the - * sleep state and the OS may abort the operation without notification to - * the ACPI driver. This method cannot modify the configuration or power - * state of any device in the system. - */ - Method(\_PTS, 1) { - /* Set up LEDs */ - if (LEqual(Arg0, One)) /* Power state S1 requested */ - { - /* Access SuperIO GPIO3/GPIO4 device */ - Store(0x87, INDX) - Store(0x87, INDX) - Store(0x09, CR07) - - /* Set GPIO3 pin 64 (power LED) to SUSLED mode */ - And(CR2C, 0xF3, CR2C) - - /* Set suspend LED to 1Hz toggle pulse with 50% duty cycle */ - Or(CRF3, 0x80, CRF3) - - /* Restore default SuperIO access */ - Store(0xAA, INDX) - } - - /* Configure SuperIO for sleep */ - /* Access SuperIO ACPI device */ - Store(0x87, INDX) - Store(0x87, INDX) - Store(0x0A, CR07) - - /* Disable PS/2 wakeup and connect PANSW_IN to PANSW_OUT */ - And(CRE0, 0x1F, CRE0) - - if (LEqual(Arg0, One)) /* Power state S1 requested */ - { - /* Set power management to PME mode and enable PME events */ - Or(CRF9, 0x05, CRF9) - - /* Activate the ACPI device */ - Store(One, CR30) - - /* Enable PS/2 keyboard SMI/PME events */ - And(CRF6, 0xEF, CRF6) - - /* Enable PS/2 keyboard wake */ - Or(CRE0, 0x40, CRE0) - - /* Enable PS/2 mouse SMI/PME events */ - And(CRF6, 0xDF, CRF6) - - /* Enable PS/2 mouse wake */ - Or(CRE0, 0x20, CRE0) - } - else { - /* Enable PS/2 keyboard wake on any keypress */ - Or(CRE0, 0x41, CRE0) - - /* Enable PS/2 mouse wake on any click */ - Or(CRE0, 0x22, CRE0) - Or(CRE6, 0x80, CRE6) - } - - /* Restore default SuperIO access */ - Store(0xAA, INDX) - - /* Configure southbridge for sleep */ - Store(One, PS1S) - Store(One, PS1E) - - /* On older chips, clear PciExpWakeDisEn */ - /*if (LLessEqual(\_SB.SBRI, 0x13)) { - * Store(0,\_SB.PWDE) - *} - */ - - /* Clear wake status structure. */ - Store(0, Index(WKST,0)) - Store(0, Index(WKST,1)) - } /* End Method(\_PTS) */ diff --git a/src/mainboard/asus/kfsn4-dre/acpi_tables.c b/src/mainboard/asus/kfsn4-dre/acpi_tables.c deleted file mode 100644 index 615f8b33e9..0000000000 --- a/src/mainboard/asus/kfsn4-dre/acpi_tables.c +++ /dev/null @@ -1,74 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * ACPI support - * written by Stefan Reinauer - * (C) 2005 Stefan Reinauer - * - * Copyright 2005 AMD - * 2005.9 yhlu modify that to more dynamic for AMD Opteron Based MB - * - * Copyright (C) 2015 Timothy Pearson , Raptor Engineering - */ - -#include -#include -#include -#include -#include -#include - -/* APIC */ -unsigned long acpi_fill_madt(unsigned long current) -{ - struct device *dev; - struct resource *res; - - /* create all subtables for processors */ - current = acpi_create_madt_lapics(current); - - /* Write NVIDIA CK804 IOAPIC. */ - dev = pcidev_on_root(sysconf.sbdn + 0x1, 0); - ASSERT(dev != NULL); - - res = find_resource(dev, PCI_BASE_ADDRESS_1); - ASSERT(res != NULL); - - current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *)current, - CONFIG_MAX_CPUS * CONFIG_MAX_PHYSICAL_CPUS, res->base, 0); - - /* Initialize interrupt mapping if mptable.c didn't. */ - if (!CONFIG(GENERATE_MP_TABLE)) { - /* Copied from mptable.c */ - /* Enable interrupts for commonly used devices (USB, SATA, etc.) */ - pci_write_config32(dev, 0x7c, 0x0d800018); - pci_write_config32(dev, 0x80, 0xd8002009); - pci_write_config32(dev, 0x84, 0x00000001); - } - - /* IRQ9 */ - current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) - current, 0, 9, 9, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_HIGH); - /* IRQ14 */ - current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) - current, 0, 14, 14, MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH); - /* IRQ15 */ - current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) - current, 0, 15, 15, MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH); - - /* create all subtables for processors */ - /* acpi_create_madt_lapic_nmis returns current, not size. */ - current = acpi_create_madt_lapic_nmis(current, - MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, 1); - - return current; -} diff --git a/src/mainboard/asus/kfsn4-dre/board_info.txt b/src/mainboard/asus/kfsn4-dre/board_info.txt deleted file mode 100644 index 678373ad2c..0000000000 --- a/src/mainboard/asus/kfsn4-dre/board_info.txt +++ /dev/null @@ -1,6 +0,0 @@ -Category: server -ROM package: PLCC-32 -ROM protocol: LPC -ROM socketed: y -Flashrom support: y -Release year: 2007 diff --git a/src/mainboard/asus/kfsn4-dre/bootblock.c b/src/mainboard/asus/kfsn4-dre/bootblock.c deleted file mode 100644 index fd57538afa..0000000000 --- a/src/mainboard/asus/kfsn4-dre/bootblock.c +++ /dev/null @@ -1,83 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2015 Timothy Pearson , Raptor Engineering - * Copyright (C) 2014 Edward O'Callaghan - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include - -#include -#include - -#define GPIO_DEV PNP_DEV(0x2e, W83627THG_GPIO3) - -#define WINBOND_ENTRY_KEY 0x87 -#define WINBOND_EXIT_KEY 0xAA - -/* Enable configuration: pass entry key '0x87' into index port dev. */ -static void pnp_enter_conf_state(pnp_devfn_t dev) -{ - u16 port = dev >> 8; - outb(WINBOND_ENTRY_KEY, port); - outb(WINBOND_ENTRY_KEY, port); -} - -/* Disable configuration: pass exit key '0xAA' into index port dev. */ -static void pnp_exit_conf_state(pnp_devfn_t dev) -{ - u16 port = dev >> 8; - outb(WINBOND_EXIT_KEY, port); -} - -uint8_t bootblock_read_recovery_jumper(pnp_devfn_t dev) -{ - uint8_t recovery_enabled = 0; - - pnp_enter_conf_state(dev); - pnp_set_logical_device(dev); - pnp_set_enable(dev, 1); /* Enable GPIO3 */ - pnp_write_config(dev, 0xf0, 0xff); /* Set GPIO3 to input */ - recovery_enabled = !(pnp_read_config(dev, 0xf1) & 0x08); /* Read GP33 */ - pnp_exit_conf_state(dev); - - return recovery_enabled; -} - -void bootblock_mainboard_init(void) -{ - uint8_t recovery_enabled; - unsigned char addr; - unsigned char byte; - - recovery_enabled = bootblock_read_recovery_jumper(GPIO_DEV); - if (recovery_enabled) { -#if CONFIG(USE_OPTION_TABLE) - /* Clear NVRAM checksum */ - for (addr = LB_CKS_RANGE_START; addr <= LB_CKS_RANGE_END; addr++) { - cmos_write(0x0, addr); - } - - /* Set fallback boot */ - byte = cmos_read(RTC_BOOT_BYTE); - byte &= 0xfc; - cmos_write(byte, RTC_BOOT_BYTE); -#else - /* FIXME - * Figure out how to recover if the option table is not available - */ -#endif - } -} diff --git a/src/mainboard/asus/kfsn4-dre/cmos.default b/src/mainboard/asus/kfsn4-dre/cmos.default deleted file mode 100644 index 93e9571655..0000000000 --- a/src/mainboard/asus/kfsn4-dre/cmos.default +++ /dev/null @@ -1,13 +0,0 @@ -debug_level=Debug -multi_core=Enable -slow_cpu=off -hypertransport_speed_limit=Auto -max_mem_clock=DDR2-800 -ECC_memory=Enable -ECC_redirection=Disable -ecc_scrub_rate=1.28us -interleave_chip_selects=Enable -interleave_nodes=Disable -interleave_memory_channels=Enable -power_on_after_fail=Enable -boot_option=Fallback diff --git a/src/mainboard/asus/kfsn4-dre/cmos.layout b/src/mainboard/asus/kfsn4-dre/cmos.layout deleted file mode 100644 index 3c0757d5ea..0000000000 --- a/src/mainboard/asus/kfsn4-dre/cmos.layout +++ /dev/null @@ -1,119 +0,0 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2015 Timothy Pearson , Raptor Engineering -## Copyright (C) 2007 AMD -## Written by Yinghai Lu for AMD. -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; either version 2 of the License, or -## (at your option) any later version. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## - -entries - -0 384 r 0 reserved_memory -384 1 e 4 boot_option -388 4 h 0 reboot_counter -393 3 r 0 unused -#394 8 unused -401 1 e 1 interleave_chip_selects -402 1 e 1 interleave_nodes -403 1 e 1 interleave_memory_channels -404 2 e 8 max_mem_clock -406 1 e 2 multi_core -412 4 e 6 debug_level -416 5 e 10 ecc_scrub_rate -440 4 e 9 slow_cpu -444 1 e 1 nmi -445 1 e 1 gart -446 1 e 1 power_on_after_fail -456 1 e 1 ECC_memory -457 1 e 1 ECC_redirection -458 4 e 11 hypertransport_speed_limit -728 256 h 0 user_data -984 16 h 0 check_sum -# Reserve the extended AMD configuration registers -1000 24 r 0 amd_reserved - - - -enumerations - -#ID value text -1 0 Disable -1 1 Enable -2 0 Enable -2 1 Disable -4 0 Fallback -4 1 Normal -6 0 Emergency -6 1 Alert -6 2 Critical -6 3 Error -6 4 Warning -6 5 Notice -6 6 Information -6 7 Debug -6 8 Spew -8 0 DDR2-800 -8 1 DDR2-667 -8 2 DDR2-533 -8 3 DDR2-400 -9 0 off -9 1 87.5% -9 2 75.0% -9 3 62.5% -9 4 50.0% -9 5 37.5% -9 6 25.0% -9 7 12.5% -10 0 Disabled -10 1 40ns -10 2 80ns -10 3 160ns -10 4 320ns -10 5 640ns -10 6 1.28us -10 7 2.56us -10 8 5.12us -10 9 10.2us -10 10 20.5us -10 11 41us -10 12 81.9us -10 13 163.8us -10 14 327.7us -10 15 655.4us -10 16 1.31ms -10 17 2.62ms -10 18 5.24ms -10 19 10.49ms -10 20 20.97ms -10 21 42ms -10 22 84ms -11 0 Auto -11 1 2.6GHz -11 2 2.4GHz -11 3 2.2GHz -11 4 2.0GHz -11 5 1.8GHz -11 6 1.6GHz -11 7 1.4GHz -11 8 1.2GHz -11 9 1.0GHz -11 10 800MHz -11 11 600MHz -11 12 500MHz -11 13 400MHz -11 14 300MHz -11 15 200MHz - -checksums - -checksum 392 983 984 diff --git a/src/mainboard/asus/kfsn4-dre/devicetree.cb b/src/mainboard/asus/kfsn4-dre/devicetree.cb deleted file mode 100644 index 50e286272f..0000000000 --- a/src/mainboard/asus/kfsn4-dre/devicetree.cb +++ /dev/null @@ -1,194 +0,0 @@ -chip northbridge/amd/amdfam10/root_complex # Root complex - device cpu_cluster 0 on # (L)APIC cluster - chip cpu/amd/socket_F_1207 # CPU socket - device lapic 0 on end # Local APIC of the CPU - end - end - device domain 0 on # PCI domain - subsystemid 0x1043 0x8162 inherit - chip northbridge/amd/amdfam10 # Northbridge / RAM controller - register "maximum_memory_capacity" = "0x1000000000" # 64GB - device pci 18.0 on end # Link 0 == LDT 0 - device pci 18.0 on # Link 1 == LDT 1 [SB on link 1] - chip southbridge/nvidia/ck804 # Southbridge - device pci 0.0 on end # HT - device pci 1.0 on # LPC - chip superio/winbond/w83627thg # Super I/O - device pnp 2e.0 on # Floppy - # Set up interface resources - io 0x60 = 0x3f0 - irq 0x70 = 6 - drq 0x74 = 2 - end - device pnp 2e.1 off end # Parallel port - device pnp 2e.2 on # Com1 - # Set up interface resources - io 0x60 = 0x3f8 - irq 0x70 = 4 - end - device pnp 2e.3 on # Com2 - # Set up interface resources - io 0x60 = 0x2f8 - irq 0x70 = 3 - # Select correct package I/O pins - io 0xf1 = 0x04 - end - device pnp 2e.5 on # PS/2 keyboard & mouse - # Set up interface resources - io 0x60 = 0x60 - io 0x62 = 0x64 - irq 0x70 = 1 - irq 0x72 = 12 - end - device pnp 2e.7 off end # Game port, MIDI, GPIO 1 & 5 - device pnp 2e.8 off end # GPIO 2 - device pnp 2e.9 on end # GPIO 3, GPIO 4 - device pnp 2e.a off end # ACPI - device pnp 2e.b on # Hardware monitor - # Set up interface resources - io 0x60 = 0x290 - irq 0x70 = 5 - end - end - end - device pci 1.1 on # SM 0 - chip drivers/generic/generic # DIMM n-0-0-0 - device i2c 50 on end - end - chip drivers/generic/generic # DIMM n-0-0-1 - device i2c 51 on end - end - chip drivers/generic/generic # DIMM n-0-1-0 - device i2c 52 on end - end - chip drivers/generic/generic # DIMM n-0-1-1 - device i2c 53 on end - end - chip drivers/generic/generic # DIMM n-1-0-0 - device i2c 54 on end - end - chip drivers/generic/generic # DIMM n-1-0-1 - device i2c 55 on end - end - chip drivers/generic/generic # DIMM n-1-1-0 - device i2c 56 on end - end - chip drivers/generic/generic # DIMM n-1-1-1 - device i2c 57 on end - end - chip drivers/i2c/w83793 - register "mfc" = "0x29" # Enable FANIN1/FANIN12, FANIN9/FANIN10, and FANIN8/FANCTRL8 inputs - register "fanin" = "0x7f" # Enable monitoring of FANIN6 - FANIN12 - register "fanin_sel" = "0x0f" # Connect FANIN9 - FANIN12 to pins 37 - 40 - register "peci_agent_conf" = "0x33" # Set Intel CPU PECI agent domain (not used by AMD but may affect chip operation) - register "tcase0" = "94" # Set maximum Intel CPU case temperature to 94°C (not used by AMD but may affect chip operation) - register "tcase1" = "94" # Set maximum Intel CPU case temperature to 94°C (not used by AMD but may affect chip operation) - register "tcase2" = "94" # Set maximum Intel CPU case temperature to 94°C (not used by AMD but may affect chip operation) - register "tcase3" = "94" # Set maximum Intel CPU case temperature to 94°C (not used by AMD but may affect chip operation) - register "tr_enable" = "0x03" # Enable montoring of TR1 and TR2 - register "td_mode_select" = "0x05" # Use internal temperature sensors and disable unconnected TD3/TD4 - register "td1_critical_temperature" = "85" # Set TD1 (CPU0) critical temperature to 85°C - register "td1_critical_hysteresis" = "80" # Set TD1 (CPU0) critical hysteresis temperature to 80°C - register "td1_warning_temperature" = "70" # Set TD1 (CPU0) warning temperature to 70°C - register "td1_warning_hysteresis" = "65" # Set TD1 (CPU0) warning hysteresis temperature to 65°C - register "td2_critical_temperature" = "85" # Set TD2 (CPU1) critical temperature to 85°C - register "td2_critical_hysteresis" = "80" # Set TD2 (CPU1) critical hysteresis temperature to 80°C - register "td2_warning_temperature" = "70" # Set TD2 (CPU1) warning temperature to 70°C - register "td2_warning_hysteresis" = "65" # Set TD2 (CPU1) warning hysteresis temperature to 65°C - register "tr1_critical_temperature" = "60" # Set TR1 (mainboard) critical temperature to 60°C - register "tr1_critical_hysteresis" = "55" # Set TR1 (mainboard) critical hysteresis temperature to 55°C - register "tr1_warning_temperature" = "50" # Set TR1 (mainboard) warning temperature to 50°C - register "tr1_warning_hysteresis" = "45" # Set TR1 (mainboard) warning hysteresis temperature to 45°C - register "critical_temperature" = "80" # Set critical temperature to 80°C - register "fanctrl1" = "0x48" # Set Fan 4 and Fan 7 to output buffer mode, all others to open drain - register "fanctrl2" = "0x01" # Set Fan 4 to Fan 7 to output buffer mode, Fan 1 to DC mode - register "first_valid_fan_number" = "2" # Fan 1/Fan 2 controls and sensors are not connected to anything - register "td1_fan_select" = "0x00" # All fans to manual mode (no dependence on TD1) - register "td2_fan_select" = "0x00" # All fans to manual mode (no dependence on TD2) - register "td3_fan_select" = "0x00" # All fans to manual mode (no dependence on TD3) - register "td4_fan_select" = "0x00" # All fans to manual mode (no dependence on TD4) - register "tr1_fan_select" = "0x00" # All fans to manual mode (no dependence on TR1) - register "tr2_fan_select" = "0x00" # All fans to manual mode (no dependence on TR2) - register "fan1_nonstop" = "7" # Set Fan 1 minimum speed - register "fan2_nonstop" = "7" # Set Fan 2 minimum speed - register "fan3_nonstop" = "7" # Set Fan 3 minimum speed - register "fan4_nonstop" = "7" # Set Fan 4 minimum speed - register "fan5_nonstop" = "7" # Set Fan 5 minimum speed - register "fan6_nonstop" = "7" # Set Fan 6 minimum speed - register "fan7_nonstop" = "7" # Set Fan 7 minimum speed - register "fan8_nonstop" = "7" # Set Fan 8 minimum speed - register "default_speed" = "100" # All fans to full speed on power up - register "fan1_duty" = "100" # Fan 1 to full speed - register "fan2_duty" = "100" # Fan 2 to full speed - register "fan3_duty" = "100" # Fan 3 to full speed - register "fan4_duty" = "100" # Fan 4 to full speed - register "fan5_duty" = "100" # Fan 5 to full speed - register "fan6_duty" = "100" # Fan 6 to full speed - register "fan7_duty" = "100" # Fan 7 to full speed - register "fan8_duty" = "100" # Fan 8 to full speed - register "vcorea_high_limit_mv" = "1500" # VCOREA (Node 0) high limit to 1.5V - register "vcorea_low_limit_mv" = "900" # VCOREA (Node 0) low limit to 0.9V - register "vcoreb_high_limit_mv" = "1500" # VCOREB (Node 1) high limit to 1.5V - register "vcoreb_low_limit_mv" = "900" # VCOREB (Node 1) low limit to 0.9V - register "vtt_high_limit_mv" = "1250" # VTT (HT link voltage) high limit to 1.25V - register "vtt_low_limit_mv" = "1150" # VTT (HT link voltage) low limit to 1.15V - register "vsen1_high_limit_mv" = "1900" # VSEN1 (Node 0 RAM voltage) high limit to 1.9V - register "vsen1_low_limit_mv" = "1700" # VSEN1 (Node 0 RAM voltage) low limit to 1.7V - register "vsen2_high_limit_mv" = "1900" # VSEN2 (Node 1 RAM voltage) high limit to 1.9V - register "vsen2_low_limit_mv" = "1700" # VSEN2 (Node 1 RAM voltage) low limit to 1.7V - register "vsen3_high_limit_mv" = "3500" # VSEN3 (+3.3V) high limit to 3.5V - register "vsen3_low_limit_mv" = "3100" # VSEN3 (+3.3V) low limit to 3.1V - register "vsen4_high_limit_mv" = "1070" # VSEN4 (+12V, scaling factor ~12.15) high limit to 13V - register "vsen4_low_limit_mv" = "905" # VSEN4 (+12V, scaling factor ~12.15) low limit to 11V - register "vdd_high_limit_mv" = "5200" # 5VDD high limit to 5.2V - register "vdd_low_limit_mv" = "4800" # 5VDD low limit to 4.8V - register "vsb_high_limit_mv" = "5200" # 5VSB high limit to 5.2V - register "vsb_low_limit_mv" = "4800" # 5VSB low limit to 4.8V - register "vbat_high_limit_mv" = "3500" # VBAT (+3V) high limit to 3.5V - register "vbat_low_limit_mv" = "2500" # VBAT (+3V) low limit to 2.5V - device i2c 0x2f on end - end - end - device pci 1.1 on end # SM 1 - device pci 2.0 on end # USB 1.1 - device pci 2.1 on end # USB 2 - device pci 4.0 off end # AC'97 Audio (N/A) - device pci 4.1 off end # AC'97 Modem (N/A) - device pci 6.0 on end # IDE - device pci 7.0 on end # SATA 0 - device pci 8.0 on end # SATA 1 - device pci 9.0 on # Bridge - device pci 4.0 on end # VGA - end - device pci a.0 off end - device pci b.0 on # Bridge - device pci 0.0 on end # NIC A - end - device pci c.0 on # Bridge - device pci 0.0 on end # LSI SAS - end - device pci d.0 on # Bridge - device pci 0.0 on end # NIC B - end - device pci e.0 on # Bridge - # Slot # PCI E 0 - end - device pci f.0 off end - register "ide0_enable" = "1" - register "ide1_enable" = "1" - register "sata0_enable" = "1" - register "sata1_enable" = "1" - end - end - device pci 18.1 on end - device pci 18.2 on end - device pci 18.3 on end - device pci 18.4 on end - device pci 19.0 on end - device pci 19.1 on end - device pci 19.2 on end - device pci 19.3 on end - device pci 19.4 on end - end - end -end diff --git a/src/mainboard/asus/kfsn4-dre/dsdt.asl b/src/mainboard/asus/kfsn4-dre/dsdt.asl deleted file mode 100644 index 4296a81475..0000000000 --- a/src/mainboard/asus/kfsn4-dre/dsdt.asl +++ /dev/null @@ -1,948 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2015 Timothy Pearson , Raptor Engineering - * Copyright (C) 2005 - 2012 Advanced Micro Devices, Inc. - * Copyright (C) 2007-2009 coresystems GmbH - * Copyright (C) 2004 Nick Barker - * Copyright (C) 2007, 2008 Rudolf Marek - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -/* - * WARNING: Sleep/Wake is a work in progress and is still somewhat flaky! - * Everything else does to the best of my knowledge... (T.P. 01/26/2015) - */ - -/* - * ISA portions taken from QEMU acpi-dsdt.dsl. - */ - -/* - * PCI link routing templates taken from ck804.asl and modified for this board - */ - -#include -DefinitionBlock ( - "DSDT.AML", /* Output filename */ - "DSDT", /* Signature */ - 0x02, /* DSDT Revision, needs to be 2 for 64bit */ - OEM_ID, - ACPI_TABLE_CREATOR, - 0x00000001 /* OEM Revision */ - ) -{ - #include - - /* Some global data */ - Name(OSVR, 3) /* Assume nothing. WinXp = 1, Vista = 2, Linux = 3, WinCE = 4 */ - Name(OSV, Ones) /* Assume nothing */ - Name(PICM, One) /* Assume APIC */ - - /* HPET control */ - Name (SHPB, 0xFED00000) - Name (SHPL, 0x1000) - - /* Define power states */ - Name (\_S0, Package () { 0x00, 0x00, 0x00, 0x00 }) /* Normal operation */ - Name (_S1, Package () { 0x01, 0x00, 0x00, 0x00 }) /* Standby */ - /* Name (_S3, Package () { 0x05, 0x00, 0x00, 0x00 }) */ /* Not supported by hardware */ - /* Name (_S4, Package () { 0x06, 0x00, 0x00, 0x00 }) */ - Name (\_S5, Package () { 0x07, 0x00, 0x00, 0x00 }) /* Hard power off */ - - /* The _PIC method is called by the OS to choose between interrupt - * routing via the i8259 interrupt controller or the APIC. - * - * _PIC is called with a parameter of 0 for i8259 configuration and - * with a parameter of 1 for Local Apic/IOAPIC configuration. - */ - Method (_PIC, 1, Serialized) { - Store (Arg0, PICM) - } - - /* _PR CPU0 is dynamically supplied by SSDT */ - /* CPU objects and _PSS entries are dynamically supplied by SSDT */ - - Scope(\_GPE) { /* Start Scope GPE */ - /* VGA controller PME# */ - Method(_L00) { - /* Level-Triggered GPE */ - Notify(\_SB.PCI0.VGAC, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ - } - - /* Keyboard controller PME# */ - Method(_L03) { - /* Level-Triggered GPE */ - Notify(\_SB.PCI0.LPC.KBD, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(\_SB.PCI0.LPC.MOU, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ - } - - /* USB2 PME# */ - Method(_L05) { - /* Level-Triggered GPE */ - Notify (\_SB.PCI0.USB2, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify (\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ - } - - /* Slot PME# */ - Method(_L0B) { - /* Level-Triggered GPE */ - Notify (\_SB.PCI0.PCIE.SLT1, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify (\_SB.PCI0.LSIC.SLT2, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify (\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ - } - - /* USB0 PME# */ - Method(_L0D) { - /* Level-Triggered GPE */ - Notify (\_SB.PCI0.USB0, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify (\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ - } - - /* Keyboard controller PME# */ - Method(_L10) { - /* Level-Triggered GPE */ - Notify(\_SB.PCI0.LPC.KBD, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(\_SB.PCI0.LPC.MOU, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ - } - - /* PCIe PME# */ - Method(_L11) { - /* Level-Triggered GPE */ - Notify (\_SB.PCI0.NICB, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify (\_SB.PCI0.PCIE, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify (\_SB.PCI0.NICA, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify (\_SB.PCI0.LSIC, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify (\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ - } - - } /* End Scope GPE */ - - /* Root of the bus hierarchy */ - Scope (\_SB) - { - /* Top PCI device (CK804) */ - Device (PCI0) - { - /* BUS0 root bus */ - - Name (_HID, EisaId ("PNP0A03")) - Name (_ADR, 0x00180001) - Name (_UID, 0x00) - - Name (HCIN, 0x00) // HC1 - - Method (_BBN, 0, NotSerialized) - { - Return (GBUS (GHCN(HCIN), GHCL(HCIN))) - } - - /* Operating System Capabilities Method */ - Method(_OSC,4) - { - /* Let OS control everything */ - Return (Arg3) - } - - External (BUSN) - External (MMIO) - External (PCIO) - External (SBLK) - External (TOM1) - External (HCLK) - External (SBDN) - External (HCDN) - External (CBST) - - /* PCI Routing Tables */ - Name (PR00, Package () { - /* PIC */ - /* ISA Bridge */ - Package (0x04) { 0x0001FFFF, 0x00, LKSM, 0x00 }, - - /* USB */ - Package (0x04) { 0x0002FFFF, 0x00, LUB0, 0x00 }, - Package (0x04) { 0x0002FFFF, 0x01, LUB2, 0x00 }, - - /* SATA 0 */ - Package (0x04) { 0x0007FFFF, 0x00, LSA0, 0x00 }, - - /* SATA 1 */ - Package (0x04) { 0x0008FFFF, 0x00, LSA1, 0x00 }, - - /* NIC A (Bridge) */ - Package (0x04) { 0x000BFFFF, 0x00, LNKB, 0x00 }, - Package (0x04) { 0x000BFFFF, 0x01, LNKC, 0x00 }, - Package (0x04) { 0x000BFFFF, 0x02, LNKD, 0x00 }, - Package (0x04) { 0x000BFFFF, 0x03, LNKA, 0x00 }, - - /* NIC B (Bridge) */ - Package (0x04) { 0x000CFFFF, 0x00, LNKA, 0x00 }, - Package (0x04) { 0x000CFFFF, 0x01, LNKB, 0x00 }, - Package (0x04) { 0x000CFFFF, 0x02, LNKC, 0x00 }, - Package (0x04) { 0x000CFFFF, 0x03, LNKD, 0x00 }, - - /* LSI SAS Controller (Bridge) */ - Package (0x04) { 0x000DFFFF, 0x00, LNKD, 0x00 }, - Package (0x04) { 0x000DFFFF, 0x01, LNKA, 0x00 }, - Package (0x04) { 0x000DFFFF, 0x02, LNKB, 0x00 }, - Package (0x04) { 0x000DFFFF, 0x03, LNKC, 0x00 }, - - /* PCI-E Slot (Bridge) */ - Package (0x04) { 0x000EFFFF, 0x00, LNKC, 0x00 }, - Package (0x04) { 0x000EFFFF, 0x01, LNKD, 0x00 }, - Package (0x04) { 0x000EFFFF, 0x02, LNKA, 0x00 }, - Package (0x04) { 0x000EFFFF, 0x03, LNKB, 0x00 }, - }) - - Name (AR00, Package () { - /* APIC */ - /* ISA Bridge */ - Package (0x04) { 0x0001FFFF, 0x00, LKSM, 0x00 }, - - /* USB */ - Package (0x04) { 0x0002FFFF, 0x00, LUB0, 0x00 }, - Package (0x04) { 0x0002FFFF, 0x01, LUB2, 0x00 }, - - /* SATA 0 */ - Package (0x04) { 0x0007FFFF, 0x00, LSA0, 0x00 }, - - /* SATA 1 */ - Package (0x04) { 0x0008FFFF, 0x00, LSA1, 0x00 }, - - /* NIC A (Bridge) */ - Package (0x04) { 0x000BFFFF, 0x00, LNIB, 0x00 }, - Package (0x04) { 0x000BFFFF, 0x01, LNIC, 0x00 }, - Package (0x04) { 0x000BFFFF, 0x02, LNND, 0x00 }, - Package (0x04) { 0x000BFFFF, 0x03, LNIA, 0x00 }, - - /* NIC B (Bridge) */ - Package (0x04) { 0x000CFFFF, 0x00, LNIA, 0x00 }, - Package (0x04) { 0x000CFFFF, 0x01, LNIB, 0x00 }, - Package (0x04) { 0x000CFFFF, 0x02, LNIC, 0x00 }, - Package (0x04) { 0x000CFFFF, 0x03, LNND, 0x00 }, - - /* LSI SAS Controller (Bridge) */ - Package (0x04) { 0x000DFFFF, 0x00, LNND, 0x00 }, - Package (0x04) { 0x000DFFFF, 0x01, LNIA, 0x00 }, - Package (0x04) { 0x000DFFFF, 0x02, LNIB, 0x00 }, - Package (0x04) { 0x000DFFFF, 0x03, LNIC, 0x00 }, - - /* PCI-E Slot (Bridge) */ - Package (0x04) { 0x000EFFFF, 0x00, LNIC, 0x00 }, - Package (0x04) { 0x000EFFFF, 0x01, LNND, 0x00 }, - Package (0x04) { 0x000EFFFF, 0x02, LNIA, 0x00 }, - Package (0x04) { 0x000EFFFF, 0x03, LNIB, 0x00 }, - }) - - Name (PR01, Package () { - /* PIC */ - Package (0x04) { 0x0004FFFF, 0x00, LNKA, 0x00 }, - }) - - Name (AR01, Package () { - /* APIC */ - Package (0x04) { 0x0004FFFF, 0x00, LNIA, 0x00 }, - }) - - Name (PR02, Package () { - /* PIC */ - Package (0x04) { 0xFFFF, 0x00, LNKB, 0x00 }, - Package (0x04) { 0xFFFF, 0x01, LNKC, 0x00 }, - Package (0x04) { 0xFFFF, 0x02, LNKD, 0x00 }, - Package (0x04) { 0xFFFF, 0x03, LNKA, 0x00 }, - }) - - Name (AR02, Package () { - /* APIC */ - Package (0x04) { 0xFFFF, 0x00, LNIB, 0x00 }, - Package (0x04) { 0xFFFF, 0x01, LNIC, 0x00 }, - Package (0x04) { 0xFFFF, 0x02, LNND, 0x00 }, - Package (0x04) { 0xFFFF, 0x03, LNIA, 0x00 }, - }) - - Name (PR03, Package () { - /* PIC */ - Package (0x04) { 0xFFFF, 0x00, LNKA, 0x00 }, - Package (0x04) { 0xFFFF, 0x01, LNKB, 0x00 }, - Package (0x04) { 0xFFFF, 0x02, LNKC, 0x00 }, - Package (0x04) { 0xFFFF, 0x03, LNKD, 0x00 }, - }) - - Name (AR03, Package () { - /* APIC */ - Package (0x04) { 0xFFFF, 0x00, LNIA, 0x00 }, - Package (0x04) { 0xFFFF, 0x01, LNIB, 0x00 }, - Package (0x04) { 0xFFFF, 0x02, LNIC, 0x00 }, - Package (0x04) { 0xFFFF, 0x03, LNND, 0x00 }, - }) - - Name (PR04, Package () { - /* PIC */ - Package (0x04) { 0xFFFF, 0x00, LNKD, 0x00 }, - Package (0x04) { 0xFFFF, 0x01, LNKA, 0x00 }, - Package (0x04) { 0xFFFF, 0x02, LNKB, 0x00 }, - Package (0x04) { 0xFFFF, 0x03, LNKC, 0x00 }, - }) - - Name (AR04, Package () { - /* APIC */ - Package (0x04) { 0xFFFF, 0x00, LNND, 0x00 }, - Package (0x04) { 0xFFFF, 0x01, LNIA, 0x00 }, - Package (0x04) { 0xFFFF, 0x02, LNIB, 0x00 }, - Package (0x04) { 0xFFFF, 0x03, LNIC, 0x00 }, - }) - - Name (PR05, Package () { - /* PIC */ - Package (0x04) { 0xFFFF, 0x00, LNKC, 0x00 }, - Package (0x04) { 0xFFFF, 0x01, LNKD, 0x00 }, - Package (0x04) { 0xFFFF, 0x02, LNKA, 0x00 }, - Package (0x04) { 0xFFFF, 0x03, LNKB, 0x00 }, - }) - - Name (AR05, Package () { - /* APIC */ - Package (0x04) { 0xFFFF, 0x00, LNIC, 0x00 }, - Package (0x04) { 0xFFFF, 0x01, LNND, 0x00 }, - Package (0x04) { 0xFFFF, 0x02, LNIA, 0x00 }, - Package (0x04) { 0xFFFF, 0x03, LNIB, 0x00 }, - }) - - /* PCI Resource Tables */ - - Name (RSIA, ResourceTemplate () { - /* PIC */ - IRQ (Level, ActiveLow, Shared, ) {8} - }) - - Name (RSMA, ResourceTemplate () { - /* APIC */ - Interrupt (ResourceConsumer, Level, ActiveLow, Shared, ,, ) {16} - }) - - Name (RSIB, ResourceTemplate () { - /* PIC */ - IRQ (Level, ActiveLow, Shared, ) {1} - }) - - Name (RSMB, ResourceTemplate () { - /* APIC */ - Interrupt (ResourceConsumer, Level, ActiveLow, Shared, ,, ) {17} - }) - - Name (RSIC, ResourceTemplate () { - /* PIC */ - IRQ (Level, ActiveLow, Shared, ) {2} - }) - - Name (RSMC, ResourceTemplate () { - /* APIC */ - Interrupt (ResourceConsumer, Level, ActiveLow, Shared, ,, ) {18} - }) - - Name (RSND, ResourceTemplate () { - /* PIC */ - IRQ (Level, ActiveLow, Shared, ) {13} - }) - - Name (RSMD, ResourceTemplate () { - /* APIC */ - Interrupt (ResourceConsumer, Level, ActiveLow, Shared, ,, ) {19} - }) - - Name (RSS2, ResourceTemplate () - { - /* PIC */ - IRQ (Level, ActiveLow, Shared, ) - {3, 4, 5, 7, 9, 10, 11, 12, 14, 15} - }) - - Name (RSA1, ResourceTemplate () - { - /* APIC */ - IRQ (Level, ActiveLow, Shared, ) - {3, 4, 5, 6, 7, 10, 11, 12, 14, 15} - }) - - Method (_CRS, 0, Serialized) - { - Name (BUF0, ResourceTemplate () - { - IO (Decode16, - 0x0CF8, // Address Range Minimum - 0x0CF8, // Address Range Maximum - 0x01, // Address Alignment - 0x08, // Address Length - ) - WordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, - 0x0000, // Address Space Granularity - 0x0000, // Address Range Minimum - 0x0CF7, // Address Range Maximum - 0x0000, // Address Translation Offset - 0x0CF8, // Address Length - ,, , TypeStatic) - }) - /* Methods below use SSDT to get actual MMIO regs - The IO ports are from 0xd00, optionally an VGA, - otherwise the info from MMIO is used. - \_SB.GXXX(node, link) - */ - Concatenate (\_SB.GMEM (0x00, \_SB.PCI0.SBLK), BUF0, Local1) - Concatenate (\_SB.GIOR (0x00, \_SB.PCI0.SBLK), Local1, Local2) - Concatenate (\_SB.GWBN (0x00, \_SB.PCI0.SBLK), Local2, Local3) - Return (Local3) - } - -#include - - /* PCI Routing Table Access */ - Method (_PRT, 0, NotSerialized) { - If (PICM) { - Return (AR00) - } Else { - Return (PR00) - } - } - - /* USB0 */ - Device (LUB0) - { - Name (_HID, EisaId ("PNP0C0F")) // _HID: Hardware ID - Name (_UID, 0x05) // _UID: Unique ID - - Method (_STA, 0, Serialized) { - If (\_SB.PCI0.LPCB.INTQ) { - Return (0xb) - } Else { - Return (0x9) - } - } - Method (_DIS, 0, Serialized) { - Store (0, \_SB.PCI0.LPCB.INTQ) - } - Method (_PRS, 0, Serialized) { - If (PICM) { - Return (PRSC) - } Else { - Return (RSA1) - } - } - Method (_CRS, 0, Serialized) { - If (PICM) { - Return (CRSC(\_SB.PCI0.LPCB.INTQ)) - } Else { - Return (CRSA(\_SB.PCI0.LPCB.INTQ)) - } - } - Method (_SRS, 1, Serialized) { - If (PICM) { - Store (SRSC(Arg0), \_SB.PCI0.LPCB.INTQ) - } Else { - Store (SRSA(Arg0), \_SB.PCI0.LPCB.INTQ) - } - } - } - - /* USB2 */ - Device (LUB2) - { - Name (_HID, EisaId ("PNP0C0F")) // _HID: Hardware ID - Name (_UID, 0x07) // _UID: Unique ID - - Method (_STA, 0, Serialized) { - If (\_SB.PCI0.LPCB.INTL) { - Return (0xb) - } Else { - Return (0x9) - } - } - Method (_DIS, 0, Serialized) { - Store (0, \_SB.PCI0.LPCB.INTL) - } - Method (_PRS, 0, Serialized) { - If (PICM) { - Return (PRSC) - } Else { - Return (RSA1) - } - } - Method (_CRS, 0, Serialized) { - If (PICM) { - Return (CRSC(\_SB.PCI0.LPCB.INTL)) - } Else { - Return (CRSA(\_SB.PCI0.LPCB.INTL)) - } - } - Method (_SRS, 1, Serialized) { - If (PICM) { - Store (SRSC(Arg0), \_SB.PCI0.LPCB.INTL) - } Else { - Store (SRSA(Arg0), \_SB.PCI0.LPCB.INTL) - } - } - } - - /* ISA Bridge */ - Device (LKSM) - { - Name (_HID, EisaId ("PNP0C0F")) // _HID: Hardware ID - Name (_UID, 0x0C) // _UID: Unique ID - - Method (_STA, 0, Serialized) { - If (\_SB.PCI0.LPCB.INTK) { - Return (0xb) - } Else { - Return (0x9) - } - } - Method (_DIS, 0, Serialized) { - Store (0, \_SB.PCI0.LPCB.INTK) - } - Method (_PRS, 0, Serialized) { - If (PICM) { - Return (RSA1) - } Else { - Return (RSS2) - } - } - Method (_CRS, 0, Serialized) { - If (PICM) { - Return (CRSB(\_SB.PCI0.LPCB.INTK)) - } Else { - Return (CRSA(\_SB.PCI0.LPCB.INTK)) - } - } - Method (_SRS, 1, Serialized) { - If (PICM) { - Store (SRSB(Arg0), \_SB.PCI0.LPCB.INTK) - } Else { - Store (SRSA(Arg0), \_SB.PCI0.LPCB.INTK) - } - } - } - - /* Bridge device link (NIC A) */ - Device (LNIA) - { - Name (_HID, EisaId ("PNP0C0F")) // _HID: Hardware ID - Name (_UID, 0x10) // _UID: Unique ID - - Method (_STA, 0, Serialized) { - If (\_SB.PCI0.LPCB.INTA) { - Return (0xb) - } Else { - Return (0x9) - } - } - Method (_DIS, 0, Serialized) { - Store (0, \_SB.PCI0.LPCB.INTA) - } - Method (_PRS, 0, Serialized) { - If (PICM) { - Return (RSMA) - } Else { - Return (RSIA) - } - } - Method (_CRS, 0, Serialized) { - If (PICM) { - Return (CRSB(\_SB.PCI0.LPCB.INTA)) - } Else { - Return (CRSA(\_SB.PCI0.LPCB.INTA)) - } - } - Method (_SRS, 1, Serialized) { - If (PICM) { - Store (SRSB(Arg0), \_SB.PCI0.LPCB.INTA) - } Else { - Store (SRSA(Arg0), \_SB.PCI0.LPCB.INTA) - } - } - } - - /* Bridge device link (NIC B) */ - Device (LNIB) - { - Name (_HID, EisaId ("PNP0C0F")) // _HID: Hardware ID - Name (_UID, 0x11) // _UID: Unique ID - - Method (_STA, 0, Serialized) { - If (\_SB.PCI0.LPCB.INTB) { - Return (0xb) - } Else { - Return (0x9) - } - } - Method (_DIS, 0, Serialized) { - Store (0, \_SB.PCI0.LPCB.INTB) - } - Method (_PRS, 0, Serialized) { - If (PICM) { - Return (RSMB) - } Else { - Return (RSIB) - } - } - Method (_CRS, 0, Serialized) { - If (PICM) { - Return (CRSB(\_SB.PCI0.LPCB.INTB)) - } Else { - Return (CRSA(\_SB.PCI0.LPCB.INTB)) - } - } - Method (_SRS, 1, Serialized) { - If (PICM) { - Store (SRSB(Arg0), \_SB.PCI0.LPCB.INTB) - } Else { - Store (SRSA(Arg0), \_SB.PCI0.LPCB.INTB) - } - } - } - - /* Bridge device link */ - Device (LNIC) - { - Name (_HID, EisaId ("PNP0C0F")) // _HID: Hardware ID - Name (_UID, 0x12) // _UID: Unique ID - - Method (_STA, 0, Serialized) { - If (\_SB.PCI0.LPCB.INTC) { - Return (0xb) - } Else { - Return (0x9) - } - } - Method (_DIS, 0, Serialized) { - Store (0, \_SB.PCI0.LPCB.INTC) - } - Method (_PRS, 0, Serialized) { - If (PICM) { - Return (RSMC) - } Else { - Return (RSIC) - } - } - Method (_CRS, 0, Serialized) { - If (PICM) { - Return (CRSB(\_SB.PCI0.LPCB.INTC)) - } Else { - Return (CRSA(\_SB.PCI0.LPCB.INTC)) - } - } - Method (_SRS, 1, Serialized) { - If (PICM) { - Store (SRSB(Arg0), \_SB.PCI0.LPCB.INTC) - } Else { - Store (SRSA(Arg0), \_SB.PCI0.LPCB.INTC) - } - } - } - - /* Bridge device link */ - Device (LNND) - { - Name (_HID, EisaId ("PNP0C0F")) // _HID: Hardware ID - Name (_UID, 0x13) // _UID: Unique ID - - Method (_STA, 0, Serialized) { - If (\_SB.PCI0.LPCB.INTD) { - Return (0xb) - } Else { - Return (0x9) - } - } - Method (_DIS, 0, Serialized) { - Store (0, \_SB.PCI0.LPCB.INTD) - } - Method (_PRS, 0, Serialized) { - If (PICM) { - Return (RSMD) - } Else { - Return (RSND) - } - } - Method (_CRS, 0, Serialized) { - If (PICM) { - Return (CRSB(\_SB.PCI0.LPCB.INTD)) - } Else { - Return (CRSA(\_SB.PCI0.LPCB.INTD)) - } - } - Method (_SRS, 1, Serialized) { - If (PICM) { - Store (SRSB(Arg0), \_SB.PCI0.LPCB.INTD) - } Else { - Store (SRSA(Arg0), \_SB.PCI0.LPCB.INTD) - } - } - } - - /* 0:02.0 CK804 USB 0 */ - Device (USB0) - { - Name (_ADR, 0x00020000) // _ADR: Address - Name(_PRW, Package () {0x0D, 0x04}) // Wake from S1-S4 - } - - /* 0:02.0 CK804 USB 2 */ - Device (USB2) - { - Name (_ADR, 0x00020001) // _ADR: Address - Name(_PRW, Package () {0x05, 0x04}) // Wake from S1-S4 - } - - /* 1:04.0 VGA Controller */ - Device (VGAC) - { - Name (_ADR, 0x00090000) // _ADR: Address - Name(_PRW, Package () {0x00, 0x04}) // Wake from S1-S4 - Method (_PRT, 0, NotSerialized) // _PRT: PCI Routing Table - { - If (PICM) { - Return (AR01) - } Else { - Return (PR01) - } - } - } - - /* 2:00.0 PCIe NIC A */ - Device (NICA) - { - Name (_ADR, 0x000B0000) // _ADR: Address - Name(_PRW, Package () {0x11, 0x04}) // Wake from S1-S4 - Method (_PRT, 0, NotSerialized) // _PRT: PCI Routing Table - { - If (PICM) { - Return (AR02) - } Else { - Return (PR02) - } - } - Device (BDC1) - { - Name (_ADR, Zero) // _ADR: Address - } - } - - /* 3:00.0 PCIe NIC B */ - Device (NICB) - { - Name (_ADR, 0x000C0000) // _ADR: Address - Name(_PRW, Package () {0x11, 0x04}) // Wake from S1-S4 - Method (_PRT, 0, NotSerialized) // _PRT: PCI Routing Table - { - If (PICM) { - Return (AR03) - } Else { - Return (PR03) - } - } - Device (BDC2) - { - Name (_ADR, Zero) // _ADR: Address - } - } - - /* 4:00.0 PCIe LSI SAS Controller */ - Device (LSIC) - { - Name (_ADR, 0x000D0000) // _ADR: Address - Name(_PRW, Package () {0x11, 0x04}) // Wake from S1-S4 - Method (_PRT, 0, NotSerialized) // _PRT: PCI Routing Table - { - If (PICM) { - Return (AR04) - } Else { - Return (PR04) - } - } - - Device (SLT2) - { - Name (_ADR, 0xFFFF) // _ADR: Address - Name(_PRW, Package () {0x0B, 0x04}) // Wake from S1-S4 - } - } - - /* 5:00.0 PCIe x16 */ - Device (PCIE) - { - Name (_ADR, 0x000E0000) // _ADR: Address - Name(_PRW, Package () {0x11, 0x04}) // Wake from S1-S4 - Method (_PRT, 0, NotSerialized) // _PRT: PCI Routing Table - { - If (PICM) { - Return (AR05) - } Else { - Return (PR05) - } - } - Device (SLT1) - { - Name (_ADR, 0xFFFF) // _ADR: Address - Name(_PRW, Package () {0x0B, 0x04}) // Wake from S1-S4 - } - } - - Device (LPC) { - Name (_HID, EisaId ("PNP0A05")) - Name (_ADR, 0x00010000) - - /* PS/2 keyboard (seems to be important for WinXP install) */ - Device (KBD) - { - Name (_HID, EisaId ("PNP0303")) - Name (_CID, EisaId ("PNP030B")) - Method (_STA, 0, NotSerialized) - { - Return (0x0f) - } - Method (_CRS, 0, Serialized) - { - Name (TMP, ResourceTemplate () { - IO (Decode16, 0x0060, 0x0060, 0x01, 0x01) - IO (Decode16, 0x0064, 0x0064, 0x01, 0x01) - IRQNoFlags () {1} - }) - Return (TMP) - } - } - - /* PS/2 mouse */ - Device (MOU) - { - Name (_HID, EisaId ("PNP0F03")) - Name (_CID, EisaId ("PNP0F13")) - Method (_STA, 0, NotSerialized) - { - Return (0x0f) - } - Method (_CRS, 0, Serialized) - { - Name (TMP, ResourceTemplate () { - IRQNoFlags () {12} - }) - Return (TMP) - } - } - - - /* UART 1 */ - Device (URT1) - { - Name (_HID, EisaId ("PNP0501")) // "PNP0501" for UART - Name(_PRW, Package () {0x03, 0x04}) // Wake from S1-S4 - Method (_STA, 0, NotSerialized) - { - Return (0x0f) // Always enable - } - Name (_PRS, ResourceTemplate() { - StartDependentFn(0, 1) { - IO(Decode16, 0x3f8, 0x3f8, 0x8, 0x8) - IRQNoFlags() { 4 } - } EndDependentFn() - }) - Method (_CRS, 0) - { - Return(ResourceTemplate() { - IO(Decode16, 0x3f8, 0x3f8, 0x8, 0x8) - IRQNoFlags() { 4 } - }) - } - } - - /* UART 2 */ - Device (URT2) - { - Name (_HID, EisaId ("PNP0501")) // "PNP0501" for UART - Name(_PRW, Package () {0x03, 0x04}) // Wake from S1-S4 - Method (_STA, 0, NotSerialized) - { - Return (0x0f) // Always enable - } - Name (_PRS, ResourceTemplate() { - StartDependentFn(0, 1) { - IO(Decode16, 0x2f8, 0x2f8, 0x8, 0x8) - IRQNoFlags() { 3 } - } EndDependentFn() - }) - Method (_CRS, 0) - { - Return(ResourceTemplate() { - IO(Decode16, 0x2f8, 0x2f8, 0x8, 0x8) - IRQNoFlags() { 3 } - }) - } - } - - /* Floppy controller */ - Device (FDC0) - { - Name (_HID, EisaId ("PNP0700")) - Method (_STA, 0, NotSerialized) - { - Return (0x0f) - } - Method (_CRS, 0, Serialized) - { - Name (BUF0, ResourceTemplate () { - FixedIO (0x03F0, 0x08) - IRQNoFlags () {6} - DMA (Compatibility, NotBusMaster, Transfer8) {2} - }) - Return (BUF0) - } - } - Device (HPET) - { - Name (_HID, EisaId ("PNP0103")) - Name (CRS, ResourceTemplate () - { - Memory32Fixed (ReadOnly, - 0x00000000, - 0x00001000, - _Y02) - IRQNoFlags () {0} - IRQNoFlags () {8} - }) - Method (_STA, 0, NotSerialized) - { - Return (0x0F) - } - Method (_CRS, 0, NotSerialized) - { - CreateDWordField (CRS, \_SB.PCI0.LPC.HPET._Y02._BAS, HPT1) - CreateDWordField (CRS, \_SB.PCI0.LPC.HPET._Y02._LEN, HPT2) - Store (SHPB, HPT1) - Store (SHPL, HPT2) - Return (CRS) - } - - } - } - } - - Device (PWRB) { /* Start Power button device */ - Name(_HID, EISAID("PNP0C0C")) - Name(_UID, 0xAA) - Name(_PRW, Package () {3, 0x04}) /* wake from S1-S4 */ - Name(_STA, 0x0B) /* sata is invisible */ - } - } - -#include "acpi/pm_ctrl.asl" - -} diff --git a/src/mainboard/asus/kfsn4-dre/get_bus_conf.c b/src/mainboard/asus/kfsn4-dre/get_bus_conf.c deleted file mode 100644 index 62f1af6ac2..0000000000 --- a/src/mainboard/asus/kfsn4-dre/get_bus_conf.c +++ /dev/null @@ -1,85 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2015 Timothy Pearson , Raptor Engineering - * Copyright (C) 2007 AMD - * (Written by Yinghai Lu for AMD) - * Copyright (C) 2007 Philipp Degler - * (Thanks to LSRA University of Mannheim for their support) - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include -#include -#include -#include -#include - -/* - * Global variables for MB layouts and these will be shared by irqtable, - * mptable and acpi_tables. - */ -/* busnum is default */ -unsigned char bus_ck804[6]; -unsigned int apicid_ck804; - -void get_bus_conf(void) -{ - unsigned int apicid_base, sbdn; - struct device *dev; - int i; - - get_default_pci1234(32); - - sysconf.sbdn = (sysconf.hcdn[0] & 0xff); // first byte of first chain - sbdn = sysconf.sbdn; - - for (i = 0; i < 6; i++) - bus_ck804[i] = 0; - - /* CK804 */ - dev = dev_find_slot(bus_ck804[0], PCI_DEVFN(sbdn + 0x09, 0)); - if (dev) { - bus_ck804[1] = pci_read_config8(dev, PCI_SECONDARY_BUS); - bus_ck804[2] = pci_read_config8(dev, PCI_SUBORDINATE_BUS); - bus_ck804[2]++; - } else { - printk - (BIOS_DEBUG, "ERROR - could not find PCI 1:%02x.0, using defaults\n", - sbdn + 0x09); - bus_ck804[1] = 2; - bus_ck804[2] = 3; - } - - for (i = 2; i < 6; i++) { - dev = dev_find_slot(bus_ck804[0], - PCI_DEVFN(sbdn + 0x0b + i - 2, 0)); - if (dev) { - bus_ck804[i] = pci_read_config8(dev, PCI_SECONDARY_BUS); - } else { - printk(BIOS_DEBUG, "ERROR - could not find PCI %02x:%02x.0, using defaults\n", - bus_ck804[0], sbdn + 0x0b + i - 2); - } - } - - if (CONFIG(LOGICAL_CPUS)) { - apicid_base = get_apicid_base(1); - printk(BIOS_SPEW, "CONFIG_LOGICAL_CPUS == 1: apicid_base: %08x\n", apicid_base); - } - else { - apicid_base = CONFIG_MAX_PHYSICAL_CPUS; - printk(BIOS_SPEW, "CONFIG_LOGICAL_CPUS == 0: apicid_base: %08x\n", apicid_base); - } - apicid_ck804 = apicid_base + 0; -} diff --git a/src/mainboard/asus/kfsn4-dre/irq_tables.c b/src/mainboard/asus/kfsn4-dre/irq_tables.c deleted file mode 100644 index 3fa72d732c..0000000000 --- a/src/mainboard/asus/kfsn4-dre/irq_tables.c +++ /dev/null @@ -1,175 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2015 Timothy Pearson , Raptor Engineering - * - * Copyright (C) 2007 AMD - * (Written by Yinghai Lu for AMD) - * Copyright (C) 2007 Philipp Degler - * (Thanks to LSRA University of Mannheim for their support) - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -// WARNING -// These tables are INVALID for this mainboard! -// The ACPI tables are correct; a backport to these PIR tables is needed... - -#include -#include -#include -#include -#include -#include - -extern unsigned char bus_ck804[6]; - - -/** - * Add one line to IRQ table. - */ -static void write_pirq_info(struct irq_info *pirq_info, uint8_t bus, - uint8_t devfn, uint8_t link0, uint16_t bitmap0, - uint8_t link1, uint16_t bitmap1, uint8_t link2, - uint16_t bitmap2, uint8_t link3, uint16_t bitmap3, - uint8_t slot, uint8_t rfu) -{ - pirq_info->bus = bus; - pirq_info->devfn = devfn; - pirq_info->irq[0].link = link0; - pirq_info->irq[0].bitmap = bitmap0; - pirq_info->irq[1].link = link1; - pirq_info->irq[1].bitmap = bitmap1; - pirq_info->irq[2].link = link2; - pirq_info->irq[2].bitmap = bitmap2; - pirq_info->irq[3].link = link3; - pirq_info->irq[3].bitmap = bitmap3; - pirq_info->slot = slot; - pirq_info->rfu = rfu; -} - -/** - * Create the IRQ routing table. - * Values are derived from getpir generated code. - */ -unsigned long write_pirq_routing_table(unsigned long addr) -{ - struct irq_routing_table *pirq; - struct irq_info *pirq_info; - unsigned int slot_num, sbdn; - uint8_t *v, sum = 0; - int i; - - sbdn = sysconf.sbdn; - - /* Align the table to be 16 byte aligned. */ - addr += 15; - addr &= ~15; - - /* This table must be between 0xf0000 & 0x100000. */ - printk(BIOS_INFO, "Writing IRQ routing tables to 0x%lx...", addr); - - pirq = (void *)(addr); - v = (uint8_t *)(addr); - - pirq->signature = PIRQ_SIGNATURE; - pirq->version = PIRQ_VERSION; - pirq->rtr_bus = bus_ck804[0]; - pirq->rtr_devfn = PCI_DEVFN(sbdn + 9, 0); - pirq->exclusive_irqs = 0x828; - pirq->rtr_vendor = 0x10de; - pirq->rtr_device = 0x005c; - pirq->miniport_data = 0; - - memset(pirq->rfu, 0, sizeof(pirq->rfu)); - - pirq_info = (void *)(&pirq->checksum + 1); - slot_num = 0; - - /* Slot1 PCIE 16x */ - write_pirq_info(pirq_info, bus_ck804[1], PCI_DEVFN(0, 0), 0x3, 0xdeb8, 0x4, - 0xdeb8, 0x1, 0xdeb8, 0x2, 0xdeb8, 4, 0); - pirq_info++; - slot_num++; - - - /* Slot2 PCIE 1x */ - write_pirq_info(pirq_info, bus_ck804[2], PCI_DEVFN(0, 0), 0x4, 0xdeb8, 0x1, - 0xdeb8, 0x2, 0xdeb8, 0x3, 0xdeb8, 5, 0); - pirq_info++; - slot_num++; - - /* Slot3 PCIE 1x */ - write_pirq_info(pirq_info, bus_ck804[3], PCI_DEVFN(0, 0), 0x1, 0xdeb8, 0x2, - 0xdeb8, 0x3, 0xdeb8, 0x4, 0xdeb8, 6, 0); - pirq_info++; - slot_num++; - - /* Slot4 PCIE 4x */ - write_pirq_info(pirq_info, bus_ck804[4], PCI_DEVFN(0x4, 0), 0x2, - 0xdeb8, 0x3, 0xdeb8, 0x4, 0xdeb8, 0x1, 0xdeb8, 7, 0); - pirq_info++; - slot_num++; - - /* Slot5 - Slot7 PCI */ - for (i = 0; i < 3; i++) { - write_pirq_info(pirq_info, bus_ck804[5], (0 << (6 + i)) | 0, - ((i + 0) % 4) + 1, 0xdeb8, - ((i + 1) % 4) + 1, 0xdeb8, - ((i + 2) % 4) + 1, 0xdeb8, - ((i + 3) % 4) + 1, 0xdeb8, i, 0); - pirq_info++; - slot_num++; - } - - /* PCI bridge */ - write_pirq_info(pirq_info, bus_ck804[0], PCI_DEVFN(sbdn + 9, 0), 0x1, - 0xdeb8, 0x2, 0xdeb8, 0x3, 0xdeb8, 0x4, 0xdeb8, 0, 0); - pirq_info++; - slot_num++; - - /* SMBus */ - write_pirq_info(pirq_info, bus_ck804[0], PCI_DEVFN(sbdn + 1, 0), 0x2, - 0xdeb8, 0, 0, 0, 0, 0, 0, 0, 0); - pirq_info++; - slot_num++; - - /* USB */ - write_pirq_info(pirq_info, bus_ck804[0], PCI_DEVFN(sbdn + 2, 0), 0x1, - 0xdeb8, 0x2, 0xdeb8, 0, 0, 0, 0, 0, 0); - pirq_info++; - slot_num++; - - /* SATA */ - write_pirq_info(pirq_info, bus_ck804[0], PCI_DEVFN(sbdn + 7, 0), 0x1, - 0xdeb8, 0, 0, 0, 0, 0, 0, 0, 0); - pirq_info++; - slot_num++; - - /* SATA */ - write_pirq_info(pirq_info, bus_ck804[0], PCI_DEVFN(sbdn + 8, 0), 0x1, - 0xdeb8, 0, 0, 0, 0, 0, 0, 0, 0); - pirq_info++; - slot_num++; - - pirq->size = 32 + 16 * slot_num; - - for (i = 0; i < pirq->size; i++) - sum += v[i]; - - sum = pirq->checksum - sum; - if (sum != pirq->checksum) - pirq->checksum = sum; - - printk(BIOS_INFO, "done.\n"); - - return (unsigned long)pirq_info; -} diff --git a/src/mainboard/asus/kfsn4-dre/mptable.c b/src/mainboard/asus/kfsn4-dre/mptable.c deleted file mode 100644 index 7ceb72062a..0000000000 --- a/src/mainboard/asus/kfsn4-dre/mptable.c +++ /dev/null @@ -1,151 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2015 Timothy Pearson , Raptor Engineering - * Copyright (C) 2007 AMD - * (Written by Yinghai Lu for AMD) - * Copyright (C) 2007 Philipp Degler - * (Thanks to LSRA University of Mannheim for their support) - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -// WARNING -// These tables are INCOMPLETE for this mainboard! -// The ACPI tables are correct; a backport to these MP tables is needed... - -#include -#include -#include -#include -#include - -extern unsigned char bus_ck804[6]; -extern unsigned int apicid_ck804; - -static void *smp_write_config_table(void *v) -{ - struct mp_config_table *mc; - unsigned int sbdn; - int bus_isa; - - mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); - - mptable_init(mc, LOCAL_APIC_ADDR); - - smp_write_processors(mc); - - sbdn = sysconf.sbdn; - - mptable_write_buses(mc, NULL, &bus_isa); - - /* I/O APICs: APIC ID Version State Address */ - { - struct device *dev; - struct resource *res; - - dev = dev_find_slot(bus_ck804[0], PCI_DEVFN(sbdn + 0x1, 0)); - if (dev) { - res = find_resource(dev, PCI_BASE_ADDRESS_1); - if (res) { - smp_write_ioapic(mc, apicid_ck804, 0x11, - res2mmio(res, 0, 0)); - } - - /* Initialize interrupt mapping. */ - - /* - LPC bridge PCI config registers: - - 0x7c:0x0000ffff - - bitmap of masked pci irqs? - - PIRQ[ABCD] possibly? - - 0x7c:0x00f00000 - - sata at f8 - port 1 - - 0x7c:0x0f000000 - - sata at f7 - port 1 - - 0x80:0xf0000000 - - sata at f7 - port 0 - - 0x80:0x0f000000 - - sata at f8 - port 0 - - 0x80:0x0000f000 - - EHCI - - 0x84:0x00000f00 - - NIC - - 0x84:0x0000000f - - OHCI - - known values of nibbles: - - 0 - unrouted? - 1 - irq 23 - 8 - irq 20 - c - irq 12 - d - irq 21 - e - irq 14 - f - irq 15 - */ - - // Enable interrupts for commonly used devices (USB, SATA, etc.) - pci_write_config32(dev, 0x7c, 0x0d800018); - pci_write_config32(dev, 0x80, 0xd8002009); - pci_write_config32(dev, 0x84, 0x00000001); - } - } - - mptable_add_isa_interrupts(mc, bus_isa, apicid_ck804, 0); - - // Onboard ck804 smbus - smp_write_pci_intsrc(mc, mp_INT, - bus_ck804[0], sbdn + 1, 1, apicid_ck804, - 0xa); - - // Onboard ck804 USB 1.1 - smp_write_pci_intsrc(mc, mp_INT, - bus_ck804[0], sbdn + 2, 0, apicid_ck804, - 0x15); - - // Onboard ck804 USB 2 - smp_write_pci_intsrc(mc, mp_INT, - bus_ck804[0], sbdn + 2, 1, apicid_ck804, - 0x14); - - // Onboard ck804 SATA 0 - smp_write_pci_intsrc(mc, mp_INT, - bus_ck804[0], sbdn + 7, 0, apicid_ck804, - 0x17); - - // Onboard ck804 SATA 1 - smp_write_pci_intsrc(mc, mp_INT, - bus_ck804[0], sbdn + 8, 0, apicid_ck804, - 0x16); - - /* Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ - mptable_lintsrc(mc, bus_ck804[0]); - - /* There is no extension information... */ - - /* Compute the checksums. */ - return mptable_finalize(mc); -} - -unsigned long write_smp_table(unsigned long addr) -{ - void *v = smp_write_floating_table(addr, 0); - return (unsigned long)smp_write_config_table(v); -} diff --git a/src/mainboard/asus/kfsn4-dre/resourcemap.c b/src/mainboard/asus/kfsn4-dre/resourcemap.c deleted file mode 100644 index b48f8f1275..0000000000 --- a/src/mainboard/asus/kfsn4-dre/resourcemap.c +++ /dev/null @@ -1,283 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2015 Timothy Pearson , Raptor Engineering - * - * Copyright (C) 2007 AMD - * Written by Yinghai Lu for AMD. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include - -void setup_mb_resource_map(void) -{ - static const unsigned int register_values[] = { - /* Careful set limit registers before base registers which contain the enables */ - /* DRAM Limit i Registers - * F1:0x44 i = 0 - * F1:0x4C i = 1 - * F1:0x54 i = 2 - * F1:0x5C i = 3 - * F1:0x64 i = 4 - * F1:0x6C i = 5 - * F1:0x74 i = 6 - * F1:0x7C i = 7 - * [ 2: 0] Destination Node ID - * 000 = Node 0 - * 001 = Node 1 - * 010 = Node 2 - * 011 = Node 3 - * 100 = Node 4 - * 101 = Node 5 - * 110 = Node 6 - * 111 = Node 7 - * [ 7: 3] Reserved - * [10: 8] Interleave select - * specifies the values of A[14:12] to use with interleave enable. - * [15:11] Reserved - * [31:16] DRAM Limit Address i Bits 39-24 - * This field defines the upper address bits of a 40 bit address - * that define the end of the DRAM region. - */ - // ADDRMAP_REG(0x44), 0x0000f8f8, 0x00000000, - ADDRMAP_REG(0x4C), 0x0000f8f8, 0x00000001, - ADDRMAP_REG(0x54), 0x0000f8f8, 0x00000002, - ADDRMAP_REG(0x5C), 0x0000f8f8, 0x00000003, - ADDRMAP_REG(0x64), 0x0000f8f8, 0x00000004, - ADDRMAP_REG(0x6C), 0x0000f8f8, 0x00000005, - ADDRMAP_REG(0x74), 0x0000f8f8, 0x00000006, - ADDRMAP_REG(0x7C), 0x0000f8f8, 0x00000007, - - /* DRAM Base i Registers - * F1:0x40 i = 0 - * F1:0x48 i = 1 - * F1:0x50 i = 2 - * F1:0x58 i = 3 - * F1:0x60 i = 4 - * F1:0x68 i = 5 - * F1:0x70 i = 6 - * F1:0x78 i = 7 - * [ 0: 0] Read Enable - * 0 = Reads Disabled - * 1 = Reads Enabled - * [ 1: 1] Write Enable - * 0 = Writes Disabled - * 1 = Writes Enabled - * [ 7: 2] Reserved - * [10: 8] Interleave Enable - * 000 = No interleave - * 001 = Interleave on A[12] (2 nodes) - * 010 = reserved - * 011 = Interleave on A[12] and A[14] (4 nodes) - * 100 = reserved - * 101 = reserved - * 110 = reserved - * 111 = Interleve on A[12] and A[13] and A[14] (8 nodes) - * [15:11] Reserved - * [31:16] DRAM Base Address i Bits 39-24 - * This field defines the upper address bits of a 40-bit address - * that define the start of the DRAM region. - */ - // ADDRMAP_REG(0x40), 0x0000f8fc, 0x00000000, - ADDRMAP_REG(0x48), 0x0000f8fc, 0x00000000, - ADDRMAP_REG(0x50), 0x0000f8fc, 0x00000000, - ADDRMAP_REG(0x58), 0x0000f8fc, 0x00000000, - ADDRMAP_REG(0x60), 0x0000f8fc, 0x00000000, - ADDRMAP_REG(0x68), 0x0000f8fc, 0x00000000, - ADDRMAP_REG(0x70), 0x0000f8fc, 0x00000000, - ADDRMAP_REG(0x78), 0x0000f8fc, 0x00000000, - - /* Memory-Mapped I/O Limit i Registers - * F1:0x84 i = 0 - * F1:0x8C i = 1 - * F1:0x94 i = 2 - * F1:0x9C i = 3 - * F1:0xA4 i = 4 - * F1:0xAC i = 5 - * F1:0xB4 i = 6 - * F1:0xBC i = 7 - * [ 2: 0] Destination Node ID - * 000 = Node 0 - * 001 = Node 1 - * 010 = Node 2 - * 011 = Node 3 - * 100 = Node 4 - * 101 = Node 5 - * 110 = Node 6 - * 111 = Node 7 - * [ 3: 3] Reserved - * [ 5: 4] Destination Link ID - * 00 = Link 0 - * 01 = Link 1 - * 10 = Link 2 - * 11 = Reserved - * [ 6: 6] Reserved - * [ 7: 7] Non-Posted - * 0 = CPU writes may be posted - * 1 = CPU writes must be non-posted - * [31: 8] Memory-Mapped I/O Limit Address i (39-16) - * This field defines the upp address bits of a 40-bit address that - * defines the end of a memory-mapped I/O region n - */ - ADDRMAP_REG(0x84), 0x00000048, 0x00000000, - ADDRMAP_REG(0x8C), 0x00000048, 0x00000000, - ADDRMAP_REG(0x94), 0x00000048, 0x00000000, - ADDRMAP_REG(0x9C), 0x00000048, 0x00000000, - ADDRMAP_REG(0xA4), 0x00000048, 0x00000000, - ADDRMAP_REG(0xAC), 0x00000048, 0x00000000, - ADDRMAP_REG(0xB4), 0x00000048, 0x00000000, - ADDRMAP_REG(0xBC), 0x00000048, 0x00000000, - - /* Memory-Mapped I/O Base i Registers - * F1:0x80 i = 0 - * F1:0x88 i = 1 - * F1:0x90 i = 2 - * F1:0x98 i = 3 - * F1:0xA0 i = 4 - * F1:0xA8 i = 5 - * F1:0xB0 i = 6 - * F1:0xB8 i = 7 - * [ 0: 0] Read Enable - * 0 = Reads disabled - * 1 = Reads Enabled - * [ 1: 1] Write Enable - * 0 = Writes disabled - * 1 = Writes Enabled - * [ 2: 2] Cpu Disable - * 0 = Cpu can use this I/O range - * 1 = Cpu requests do not use this I/O range - * [ 3: 3] Lock - * 0 = base/limit registers i are read/write - * 1 = base/limit registers i are read-only - * [ 7: 4] Reserved - * [31: 8] Memory-Mapped I/O Base Address i (39-16) - * This field defines the upper address bits of a 40bit address - * that defines the start of memory-mapped I/O region i - */ - ADDRMAP_REG(0x80), 0x000000f0, 0x00000000, - ADDRMAP_REG(0x88), 0x000000f0, 0x00000000, - ADDRMAP_REG(0x90), 0x000000f0, 0x00000000, - ADDRMAP_REG(0x98), 0x000000f0, 0x00000000, - ADDRMAP_REG(0xA0), 0x000000f0, 0x00000000, - ADDRMAP_REG(0xA8), 0x000000f0, 0x00000000, - ADDRMAP_REG(0xB0), 0x000000f0, 0x00000000, - ADDRMAP_REG(0xB8), 0x000000f0, 0x00000000, - - /* PCI I/O Limit i Registers - * F1:0xC4 i = 0 - * F1:0xCC i = 1 - * F1:0xD4 i = 2 - * F1:0xDC i = 3 - * [ 2: 0] Destination Node ID - * 000 = Node 0 - * 001 = Node 1 - * 010 = Node 2 - * 011 = Node 3 - * 100 = Node 4 - * 101 = Node 5 - * 110 = Node 6 - * 111 = Node 7 - * [ 3: 3] Reserved - * [ 5: 4] Destination Link ID - * 00 = Link 0 - * 01 = Link 1 - * 10 = Link 2 - * 11 = reserved - * [11: 6] Reserved - * [24:12] PCI I/O Limit Address i - * This field defines the end of PCI I/O region n - * [31:25] Reserved - */ - ADDRMAP_REG(0xC4), 0xFE000FC8, 0x00fff010, /* link 1 of CPU 0 --> Nvidia CK 804 */ - ADDRMAP_REG(0xCC), 0xFE000FC8, 0x00000000, - ADDRMAP_REG(0xD4), 0xFE000FC8, 0x00000000, - ADDRMAP_REG(0xDC), 0xFE000FC8, 0x00000000, - - /* PCI I/O Base i Registers - * F1:0xC0 i = 0 - * F1:0xC8 i = 1 - * F1:0xD0 i = 2 - * F1:0xD8 i = 3 - * [ 0: 0] Read Enable - * 0 = Reads Disabled - * 1 = Reads Enabled - * [ 1: 1] Write Enable - * 0 = Writes Disabled - * 1 = Writes Enabled - * [ 3: 2] Reserved - * [ 4: 4] VGA Enable - * 0 = VGA matches Disabled - * 1 = matches all address < 64K and where A[9:0] is in the - * range 3B0-3BB or 3C0-3DF independent of the base & limit registers - * [ 5: 5] ISA Enable - * 0 = ISA matches Disabled - * 1 = Blocks address < 64K and in the last 768 bytes of eack 1K block - * from matching agains this base/limit pair - * [11: 6] Reserved - * [24:12] PCI I/O Base i - * This field defines the start of PCI I/O region n - * [31:25] Reserved - */ -// ADDRMAP_REG(0xC0), 0xFE000FCC, 0x00001013, - ADDRMAP_REG(0xC8), 0xFE000FCC, 0x00000000, - ADDRMAP_REG(0xD0), 0xFE000FCC, 0x00000000, - ADDRMAP_REG(0xD8), 0xFE000FCC, 0x00000000, - - /* Config Base and Limit i Registers - * F1:0xE0 i = 0 - * F1:0xE4 i = 1 - * F1:0xE8 i = 2 - * F1:0xEC i = 3 - * [ 0: 0] Read Enable - * 0 = Reads Disabled - * 1 = Reads Enabled - * [ 1: 1] Write Enable - * 0 = Writes Disabled - * 1 = Writes Enabled - * [ 2: 2] Device Number Compare Enable - * 0 = The ranges are based on bus number - * 1 = The ranges are ranges of devices on bus 0 - * [ 3: 3] Reserved - * [ 6: 4] Destination Node - * 000 = Node 0 - * 001 = Node 1 - * 010 = Node 2 - * 011 = Node 3 - * 100 = Node 4 - * 101 = Node 5 - * 110 = Node 6 - * 111 = Node 7 - * [ 7: 7] Reserved - * [ 9: 8] Destination Link - * 00 = Link 0 - * 01 = Link 1 - * 10 = Link 2 - * 11 - Reserved - * [15:10] Reserved - * [23:16] Bus Number Base i - * This field defines the lowest bus number in configuration region i - * [31:24] Bus Number Limit i - * This field defines the highest bus number in configuration region i - */ - ADDRMAP_REG(0xE0), 0x0000FC88, 0x05000103, /* link 1 of CPU 0 --> Nvidia CK 804 */ - ADDRMAP_REG(0xE4), 0x0000FC88, 0x00000000, - ADDRMAP_REG(0xE8), 0x0000FC88, 0x00000000, - ADDRMAP_REG(0xEC), 0x0000FC88, 0x00000000, - - }; - - int max; - max = ARRAY_SIZE(register_values); - setup_resource_map(register_values, max); -} diff --git a/src/mainboard/asus/kfsn4-dre/romstage.c b/src/mainboard/asus/kfsn4-dre/romstage.c deleted file mode 100644 index 7d710d73a2..0000000000 --- a/src/mainboard/asus/kfsn4-dre/romstage.c +++ /dev/null @@ -1,372 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2015 Timothy Pearson , Raptor Engineering - * - * Copyright (C) 2007 AMD - * Written by Yinghai Lu for AMD. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include "cpu/amd/quadcore/quadcore.c" - -#define SERIAL_DEV PNP_DEV(0x2e, W83627THG_SP1) - -#define CK804_MB_SETUP \ - RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+33, ~(0x0f),(0x04 | 0x01), /* -ENOINFO Proprietary BIOS sets this register; "When in Rome..."*/ - -#include -#include "southbridge/nvidia/ck804/early_setup_car.c" - -#define GPIO3_DEV PNP_DEV(0x2e, W83627THG_GPIO3) - -int spd_read_byte(unsigned int device, unsigned int address); - -int spd_read_byte(unsigned int device, unsigned int address) -{ - return smbus_read_byte(device, address); -} - -/** - * @brief Get SouthBridge device number - * @param[in] bus target bus number - * @return southbridge device number - */ -unsigned int get_sbdn(unsigned int bus) -{ - pci_devfn_t dev; - - dev = pci_locate_device_on_bus(PCI_ID(PCI_VENDOR_ID_NVIDIA, - PCI_DEVICE_ID_NVIDIA_CK804_PRO), bus); - return (dev >> 15) & 0x1f; -} - -/* - * ASUS KFSN4-DRE specific SPD enable/disable magic. - * - * Setting CK804 GPIO43 and GPIO44 to 0 and 0 respectively will make the - * board DIMMs accessible at SMBus/SPD offsets 0x50-0x53. Per default the SPD - * offsets 0x50-0x53 are _not_ readable (all SPD reads will return 0xff) which - * will make RAM init fail. - * - * Disable SPD access after RAM init to allow access to standard SMBus/I2C offsets - * which is required e.g. by lm-sensors. - */ - -#define CK804_BOARD_BOOT_BASE_UNIT_UID 1 - -static const unsigned int ctrl_conf_enable_spd_node0[] = { - RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+42, ~(0x0f),(0x04 | 0x00),/* W2,GPIO43, U6 input S0*/ - RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+43, ~(0x0f),(0x04 | 0x00),/* W3,GPIO44, U6 input S1*/ -}; - -static const unsigned int ctrl_conf_enable_spd_node1[] = { - RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+42, ~(0x0f),(0x04 | 0x00),/* W2,GPIO43, U6 input S0*/ - RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+43, ~(0x0f),(0x04 | 0x01),/* W3,GPIO44, U6 input S1*/ -}; - -static const unsigned int ctrl_conf_disable_spd[] = { - RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+42, ~(0x0f),(0x04 | 0x01),/* W2,GPIO43, U6 input S0*/ - RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+43, ~(0x0f),(0x04 | 0x00),/* W3,GPIO44, U6 input S1*/ -}; - -static const unsigned int ctrl_conf_fix_pci_numbering[] = { - RES_PCI_IO, PCI_ADDR(0, 0, 0, 0x44), ~(0x00010000), 0x00000000, /* Force CK804 to start its internal device numbering (Base Unit ID) at 0 instead of the power-on default of 1 */ -}; - -static const unsigned int ctrl_conf_enable_msi_mapping[] = { - RES_PCI_IO, PCI_ADDR(0, 0, 0, 0xe0), ~(0x00000000), 0x00010000, /* Enable MSI mapping on host bridge -- without this Linux cannot use the network device MSI interrupts! */ -}; - -static void ck804_control(const unsigned int *values, u32 size, - uint8_t bus_unit_id) -{ - unsigned int busn[4], io_base[4]; - int i, ck804_num = 0; - - for (i = 0; i < 4; i++) { - u32 id; - pci_devfn_t dev; - if (i == 0) /* SB chain */ - dev = PCI_DEV(i * 0x40, bus_unit_id, 0); - else - dev = 0; - id = pci_read_config32(dev, PCI_VENDOR_ID); - if (id == 0x005e10de) { - busn[ck804_num] = i * 0x40; - io_base[ck804_num] = i * 0x4000; - ck804_num++; - } - } - - if (ck804_num < 1) { - printk(BIOS_WARNING, "CK804 not found at device base unit id %02x!\n", bus_unit_id); - return; - } - - ck804_early_set_port(ck804_num, busn, io_base); - - setup_resource_map_x_offset(values, - size, - PCI_DEV(0, bus_unit_id, 0), io_base[0]); - - ck804_early_clear_port(ck804_num, busn, io_base); -} - -static void sio_setup(void) -{ - u32 dword; - u8 byte; - - /* Subject decoding */ - byte = pci_read_config8(PCI_DEV(0, CK804_BOARD_BOOT_BASE_UNIT_UID + 1, 0), 0x7b); - byte |= 0x20; - pci_write_config8(PCI_DEV(0, CK804_BOARD_BOOT_BASE_UNIT_UID + 1, 0), 0x7b, byte); - - /* LPC Positive Decode 0 */ - dword = pci_read_config32(PCI_DEV(0, CK804_BOARD_BOOT_BASE_UNIT_UID + 1, 0), 0xa0); - /* Serial 0, Serial 1 */ - dword |= (1 << 0) | (1 << 1); - pci_write_config32(PCI_DEV(0, CK804_BOARD_BOOT_BASE_UNIT_UID + 1, 0), 0xa0, dword); -} - -static const uint8_t spd_addr[] = { - // Node 0 - RC00, DIMM0, DIMM2, DIMM4, DIMM6, DIMM1, DIMM3, DIMM5, DIMM7, - // Node 1 - RC01, DIMM0, DIMM2, DIMM4, DIMM6, DIMM1, DIMM3, DIMM5, DIMM7, -}; - -void activate_spd_rom(const struct mem_controller *ctrl) -{ - printk(BIOS_DEBUG, "activate_spd_rom() for node %02x\n", ctrl->node_id); - if (ctrl->node_id == 0) { - printk(BIOS_DEBUG, "enable_spd_node0()\n"); - ck804_control(ctrl_conf_enable_spd_node0, ARRAY_SIZE(ctrl_conf_enable_spd_node0), CK804_DEVN_BASE); - } - else if (ctrl->node_id == 1) { - printk(BIOS_DEBUG, "enable_spd_node1()\n"); - ck804_control(ctrl_conf_enable_spd_node1, ARRAY_SIZE(ctrl_conf_enable_spd_node1), CK804_DEVN_BASE); - } -} - -void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) -{ - struct sys_info *sysinfo = get_sysinfo(); - - u32 bsp_apicid = 0, val, wants_reset; - msr_t msr; - - timestamp_init(timestamp_get()); - timestamp_add_now(TS_START_ROMSTAGE); - - if (!cpu_init_detectedx && boot_cpu()) { - /* Nothing special needs to be done to find bus 0 */ - /* Allow the HT devices to be found */ - set_bsp_node_CHtExtNodeCfgEn(); - enumerate_ht_chain(); - sio_setup(); - } - - post_code(0x30); - - if (bist == 0) - bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo); - - post_code(0x32); - - winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); - console_init(); - - if (CONFIG_MAX_PHYSICAL_CPUS != 2) - printk(BIOS_WARNING, "CONFIG_MAX_PHYSICAL_CPUS is %d, but this is a dual socket board!\n", CONFIG_MAX_PHYSICAL_CPUS); - - /* Halt if there was a built in self test failure */ - report_bist_failure(bist); - - val = cpuid_eax(1); - printk(BIOS_DEBUG, "BSP Family_Model: %08x\n", val); - printk(BIOS_DEBUG, "*sysinfo range: [%p,%p]\n",sysinfo,sysinfo+1); - printk(BIOS_DEBUG, "bsp_apicid = %02x\n", bsp_apicid); - printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx); - - /* Setup sysinfo defaults */ - set_sysinfo_in_ram(0); - - update_microcode(val); - - post_code(0x33); - - cpuSetAMDMSR(0); - post_code(0x34); - - amd_ht_init(sysinfo); - post_code(0x35); - - /* Setup nodes PCI space and start core 0 AP init. */ - finalize_node_setup(sysinfo); - - /* Setup any mainboard PCI settings etc. */ - setup_mb_resource_map(); - post_code(0x36); - - /* wait for all the APs core0 started by finalize_node_setup. */ - /* FIXME: A bunch of cores are going to start output to serial at once. - * It would be nice to fix up prink spinlocks for ROM XIP mode. - * I think it could be done by putting the spinlock flag in the cache - * of the BSP located right after sysinfo. - */ - wait_all_core0_started(); - - if (CONFIG(SET_FIDVID)) { - msr = rdmsr(MSR_COFVID_STS); - printk(BIOS_DEBUG, "\nBegin FIDVID MSR 0xc0010071 0x%08x 0x%08x\n", msr.hi, msr.lo); - - post_code(0x39); - - if (!warm_reset_detect(0)) { // BSP is node 0 - init_fidvid_bsp(bsp_apicid, sysinfo->nodes); - } else { - init_fidvid_stage2(bsp_apicid, 0); // BSP is node 0 - } - - post_code(0x3A); - - /* show final fid and vid */ - msr = rdmsr(MSR_COFVID_STS); - printk(BIOS_DEBUG, "End FIDVIDMSR 0xc0010071 0x%08x 0x%08x\n", msr.hi, msr.lo); - } - - if (CONFIG(LOGICAL_CPUS)) { - /* Core0 on each node is configured. Now setup any additional cores. */ - printk(BIOS_DEBUG, "start_other_cores()\n"); - start_other_cores(bsp_apicid); - post_code(0x37); - wait_all_other_cores_started(bsp_apicid); - } - - printk(BIOS_DEBUG, "set_ck804_base_unit_id()\n"); - ck804_control(ctrl_conf_fix_pci_numbering, ARRAY_SIZE(ctrl_conf_fix_pci_numbering), CK804_BOARD_BOOT_BASE_UNIT_UID); - - post_code(0x38); - - init_timer(); // Need to use TMICT to synconize FID/VID - - wants_reset = ck804_early_setup_x(); - - /* Reset for HT, FIDVID, PLL and errata changes to take affect. */ - if (!warm_reset_detect(0)) { - printk(BIOS_INFO, "...WARM RESET...\n\n\n"); - soft_reset(); - die("After soft_reset - shouldn't see this message!!!\n"); - } - - if (wants_reset) { - printk(BIOS_DEBUG, "ck804_early_setup_x wanted additional reset!\n"); - } - - post_code(0x3B); - - /* It's the time to set ctrl in sysinfo now; */ - printk(BIOS_DEBUG, "fill_mem_ctrl()\n"); - fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr); - post_code(0x3D); - - printk(BIOS_DEBUG, "enable_smbus()\n"); - enable_smbus(); - -#if 0 - /* FIXME - * After the AMD K10 code has been converted to use - * CONFIG(DEBUG_SMBUS) uncomment this block - */ - if (CONFIG(DEBUG_SMBUS)) { - dump_spd_registers(&cpu[0]); - dump_smbus_registers(); - } -#endif - - post_code(0x40); - - raminit_amdmct(sysinfo); - - cbmem_initialize_empty(); - post_code(0x41); - - amdmct_cbmem_store_info(sysinfo); - - printk(BIOS_DEBUG, "disable_spd()\n"); - ck804_control(ctrl_conf_disable_spd, ARRAY_SIZE(ctrl_conf_disable_spd), CK804_DEVN_BASE); - - printk(BIOS_DEBUG, "enable_msi_mapping()\n"); - ck804_control(ctrl_conf_enable_msi_mapping, ARRAY_SIZE(ctrl_conf_enable_msi_mapping), CK804_DEVN_BASE); - - /* Initialize GPIO */ - /* Access SuperIO GPI03 logical device */ - pnp_enter_conf_state(GPIO3_DEV); - pnp_set_logical_device(GPIO3_DEV); - /* Set GP37 (power LED) to output */ - pnp_write_config(GPIO3_DEV, 0xf0, 0x7f); - /* Set GP37 (power LED) on */ - pnp_write_config(GPIO3_DEV, 0xf1, 0x80); - /* Set pin 64 multiplex to GP37 */ - uint8_t cr2c = pnp_read_config(GPIO3_DEV, 0x2c); - pnp_write_config(GPIO3_DEV, 0x2c, (cr2c & 0xf3) | 0x04); - /* Restore default SuperIO access */ - pnp_exit_conf_state(GPIO3_DEV); -} - -/** - * BOOL AMD_CB_ManualBUIDSwapList(u8 Node, u8 Link, u8 **List) - * Description: - * This routine is called every time a non-coherent chain is processed. - * BUID assignment may be controlled explicitly on a non-coherent chain. Provide a - * swap list. The first part of the list controls the BUID assignment and the - * second part of the list provides the device to device linking. Device orientation - * can be detected automatically, or explicitly. See documentation for more details. - * - * Automatic non-coherent init assigns BUIDs starting at 1 and incrementing sequentially - * based on each device's unit count. - * - * Parameters: - * @param[in] node = The node on which this chain is located - * @param[in] link = The link on the host for this chain - * @param[out] List = supply a pointer to a list - */ -BOOL AMD_CB_ManualBUIDSwapList (u8 node, u8 link, const u8 **List) -{ - return 0; -} diff --git a/src/mainboard/asus/kfsn4-dre/spd_notes.txt b/src/mainboard/asus/kfsn4-dre/spd_notes.txt deleted file mode 100644 index 9287a5f75a..0000000000 --- a/src/mainboard/asus/kfsn4-dre/spd_notes.txt +++ /dev/null @@ -1,69 +0,0 @@ -==================================================================================================== -SPD mux -==================================================================================================== - -DIMM_A1 SDA signal traced to U6 pin 1 -Destructive testing of failed board (removal of U7 northbridge!) yielded the following information: -U6 S0 <--> U7 W2 -U6 S1 <--> U7 W3 - -Proprietary BIOS enables the SPD during POST with: -S0: LOW -S1: LOW - -then temporarily switches to: -S0: LOW -S1: HIGH - -then switches to runtime mode with: -S0: HIGH -S1: LOW - -After probing with a custom GPIO-flipping tool under Linux the following GPIO mappings were found: -CK804 pin W2 <--> GPIO43 -CK804 pin W3 <--> GPIO44 - -==================================================================================================== -W83793 (U46) -==================================================================================================== - -Sensor mappings: -FRNT_FAN1: FAN3 -FRNT_FAN2: FAN4 -FRNT_FAN3: FAN5 -FRNT_FAN4: FAN6 -FRNT_FAN5: FAN9 -FRNT_FAN6: FAN10 -REAR_FAN1: FAN7 -REAR_FAN2: FAN8 -REAR_FAN3: FAN11 -REAR_FAN4: FAN12 - -==================================================================================================== -Other hardware -==================================================================================================== - -Power LED (-) is connected to U15 (SuperIO) pin 64 via U4 pins 5,6 and a small MOSFET -ID LED (-) is connected to a ??? via U4 pins 1,2,3,4 and U77 pins 5,6 -It appears that setting U15 (SuperIO) pin 88 LOW will override the ID LED and force it ON - -RECOVERY2 middle pin is connected to U15 (SuperIO) pin 89 -Normal is HIGH, recovery is LOW. - -PCIe slot WAKE# connects to U7 pin E23 (PCIE_WAKE#) - -CPU_WARN1 is driven by (???) via a simple buffer (U13 pin 10) -MEM_WARN1 is driven by U7 pin AD3 (CPUVDD_EN) via a simple buffer (U101 pin 3) - -U7 pin AK3 is disconnected (routed to unpopulated capacitor/resistor) -PU1 pin 37 (VDDPWRGD) drives U7 pin AJ4 (CPU_VLD) -A small MOSFET directly above another small MOSFET directly above the right-hand edge of the PCIe slot drives U7 pin AK5 (HT_VLD) - -When > Barcelona CPU installed on PCB rev 1.04G: -U7 pin AK4 (MEM_VLD): HIGH -PU1 pin 37: LOW -U7 pin AK5: LOW - -HyperTransport 1.2V supply appears to be generated by a linear regulator containing Q191 and downconverting the CK804 1.5V supply -The enable pin appears to be tied to AUX_PANEL pin 1 (+5VSB) via a resistor -Through two MOSFETs the HT supply enable pin is tied to U7 pin AE3 (HTVDD_EN) diff --git a/src/mainboard/asus/kgpe-d16/Kconfig b/src/mainboard/asus/kgpe-d16/Kconfig deleted file mode 100644 index ffbfd53169..0000000000 --- a/src/mainboard/asus/kgpe-d16/Kconfig +++ /dev/null @@ -1,102 +0,0 @@ -if BOARD_ASUS_KGPE_D16 - -config BOARD_SPECIFIC_OPTIONS - def_bool y - select CPU_AMD_SOCKET_G34_NON_AGESA - select DIMM_DDR3 - select DIMM_REGISTERED - # select QRANK_DIMM_SUPPORT - select DIMM_VOLTAGE_SET_SUPPORT - select NORTHBRIDGE_AMD_AMDFAM10 - select SOUTHBRIDGE_AMD_SR5650 - select SOUTHBRIDGE_AMD_SB700 - select SOUTHBRIDGE_AMD_SB700_DISABLE_ISA_DMA - select SOUTHBRIDGE_AMD_SUBTYPE_SP5100 - select SUPERIO_WINBOND_W83667HG_A - select PARALLEL_CPU_INIT - select HAVE_ROMSTAGE_CONSOLE_SPINLOCK - select HAVE_ROMSTAGE_NVRAM_CBFS_SPINLOCK - select HAVE_ROMSTAGE_MICROCODE_CBFS_SPINLOCK - select HAVE_OPTION_TABLE - select HAVE_CMOS_DEFAULT - select HAVE_PIRQ_TABLE - select HAVE_MP_TABLE - select HAVE_ACPI_TABLES - select SB_HT_CHAIN_UNITID_OFFSET_ONLY - select LIFT_BSP_APIC_ID - select BOARD_ROMSIZE_KB_2048 - select ENABLE_APIC_EXT_ID - select SPI_FLASH - select MAINBOARD_HAS_LPC_TPM - select DRIVERS_I2C_W83795 - select DRIVERS_ASPEED_AST2050 - select MAINBOARD_FORCE_NATIVE_VGA_INIT - select POWER_STATE_DEFAULT_ON_AFTER_FAILURE - select IPMI_KCS - -config MAINBOARD_DIR - string - default "asus/kgpe-d16" - -config BOOTBLOCK_MAINBOARD_INIT - string - default "mainboard/asus/kgpe-d16/bootblock.c" - -config DCACHE_RAM_BASE - hex - default 0xc2000 - -config DCACHE_RAM_SIZE - hex - default 0x1e000 - -config APIC_ID_OFFSET - hex - default 0x0 - -config MAINBOARD_PART_NUMBER - string - default "KGPE-D16" - -config HW_MEM_HOLE_SIZEK - hex - default 0x100000 - -config MAX_CPUS - int - default 32 - -# 2 (internal) processors per G34 socket -config MAX_PHYSICAL_CPUS - int - default 4 - -config HT_CHAIN_UNITID_BASE - hex - default 0x0 - -config HT_CHAIN_END_UNITID_BASE - hex - default 0x20 - -config IRQ_SLOT_COUNT - int - default 13 - -config SOUTHBRIDGE_AMD_SB700_SATA_PORT_COUNT_BITFIELD - hex - default 0x3f - -config ONBOARD_VGA_IS_PRIMARY - bool - default y - -config VGA_BIOS_ID - string - default "1a03,2000" - -config MAX_REBOOT_CNT - int - default 10 - -endif # BOARD_ASUS_KGPE_D16 diff --git a/src/mainboard/asus/kgpe-d16/Kconfig.name b/src/mainboard/asus/kgpe-d16/Kconfig.name deleted file mode 100644 index bdfa31ad1c..0000000000 --- a/src/mainboard/asus/kgpe-d16/Kconfig.name +++ /dev/null @@ -1,2 +0,0 @@ -config BOARD_ASUS_KGPE_D16 - bool "KGPE-D16" diff --git a/src/mainboard/asus/kgpe-d16/Makefile.inc b/src/mainboard/asus/kgpe-d16/Makefile.inc deleted file mode 100644 index 91d4b39c32..0000000000 --- a/src/mainboard/asus/kgpe-d16/Makefile.inc +++ /dev/null @@ -1,16 +0,0 @@ -# -# This file is part of the coreboot project. -# -# This program is free software; you can redistribute it and/or modify -# it under the terms of the GNU General Public License as published by -# the Free Software Foundation; version 2 of the License. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# - -romstage-y += resourcemap.c - -ramstage-y += get_bus_conf.c diff --git a/src/mainboard/asus/kgpe-d16/acpi/pm_ctrl.asl b/src/mainboard/asus/kgpe-d16/acpi/pm_ctrl.asl deleted file mode 100644 index ee49daeaab..0000000000 --- a/src/mainboard/asus/kgpe-d16/acpi/pm_ctrl.asl +++ /dev/null @@ -1,368 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2015 Raptor Engineering - * Copyright (C) 2009 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -/* Port 80 POST card debug */ -OperationRegion (DBG0, SystemIO, 0x80, One) - Field (DBG0, ByteAcc, NoLock, Preserve) { - DBG8, 8 -} - -/* SuperIO control port */ -Name (SPIO, 0x2E) - -/* SuperIO control map */ -OperationRegion (SPIM, SystemIO, SPIO, 0x02) - Field (SPIM, ByteAcc, NoLock, Preserve) { - INDX, 8, - DATA, 8 -} - -/* SuperIO control registers */ -IndexField (INDX, DATA, ByteAcc, NoLock, Preserve) { - Offset (0x07), - CR07, 8, /* Logical device number */ - Offset (0x2C), - CR2C, 8, /* GPIO3 multiplexed pin selection */ - Offset (0x30), - CR30, 8, /* Logical device activation control register */ - Offset (0xE0), - CRE0, 8, /* Wake control register */ - Offset (0xE4), - CRE4, 8, /* Standby power control register */ - Offset (0xE6), - CRE6, 8, /* Mouse wake event configuration register */ - Offset (0xF1), - CRF1, 8, /* GPIO3 data register */ - Offset (0xF3), - CRF3, 8, /* SUSLED mode register */ - Offset (0xF6), - CRF6, 8, /* SMI/PME event generation control register */ - Offset (0xF9), - CRF9, 8, /* ACPI PME configuration register */ -} - -/* Power Management I/O registers */ -OperationRegion(PIOR, SystemIO, 0x00000CD6, 0x00000002) - Field(PIOR, ByteAcc, NoLock, Preserve) { - PIOI, 0x00000008, - PIOD, 0x00000008, -} -IndexField (PIOI, PIOD, ByteAcc, NoLock, Preserve) { - Offset(0x00), /* MiscControl */ - , 1, - T1EE, 1, - T2EE, 1, - Offset(0x01), /* MiscStatus */ - , 1, - T1E, 1, - T2E, 1, - Offset(0x04), /* SmiWakeUpEventEnable3 */ - , 7, - SSEN, 1, - Offset(0x07), /* SmiWakeUpEventStatus3 */ - , 7, - CSSM, 1, - Offset(0x10), /* AcpiEnable */ - , 6, - PWDE, 1, - Offset(0x1C), /* ProgramIoEnable */ - , 3, - MKME, 1, - IO3E, 1, - IO2E, 1, - IO1E, 1, - IO0E, 1, - Offset(0x1D), /* IOMonitorStatus */ - , 3, - MKMS, 1, - IO3S, 1, - IO2S, 1, - IO1S, 1, - IO0S,1, - Offset(0x20), /* AcpiPmEvtBlk */ - APEB, 16, - Offset(0x36), /* GEvtLevelConfig */ - , 6, - ELC6, 1, - ELC7, 1, - Offset(0x37), /* GPMLevelConfig0 */ - , 3, - PLC0, 1, - PLC1, 1, - PLC2, 1, - PLC3, 1, - PLC8, 1, - Offset(0x38), /* GPMLevelConfig1 */ - , 1, - PLC4, 1, - PLC5, 1, - , 1, - PLC6, 1, - PLC7, 1, - Offset(0x3B), /* PMEStatus1 */ - GP0S, 1, - GM4S, 1, - GM5S, 1, - APS, 1, - GM6S, 1, - GM7S, 1, - GP2S, 1, - STSS, 1, - Offset(0x55), /* SoftPciRst */ - SPRE, 1, - , 1, - , 1, - PNAT, 1, - PWMK, 1, - PWNS, 1, - - /* Offset(0x61), */ /* Options_1 */ - /* ,7, */ - /* R617,1, */ - - Offset(0x65), /* UsbPMControl */ - , 4, - URRE, 1, - , 2, - BCDL, 1, - Offset(0x68), /* MiscEnable68 */ - , 2, - MAPC, 1, - TMTE, 1, - , 1, - Offset(0x7C), /* MiscEnable7C */ - , 2, - BLNK, 2, - Offset(0x92), /* GEVENTIN */ - , 7, - E7IS, 1, - Offset(0x96), /* GPM98IN */ - G8IS, 1, - G9IS, 1, - Offset(0x9A), /* EnhanceControl */ - ,7, - HPDE, 1, - Offset(0xA8), /* PIO7654Enable */ - IO4E, 1, - IO5E, 1, - IO6E, 1, - IO7E, 1, - Offset(0xA9), /* PIO7654Status */ - IO4S, 1, - IO5S, 1, - IO6S, 1, - IO7S, 1, -} - -/* PM1 Event Block - * First word is PM1_Status, Second word is PM1_Enable - */ -OperationRegion(P1EB, SystemIO, APEB, 0x04) - Field(P1EB, ByteAcc, NoLock, Preserve) { - TMST, 1, - , 3, - BMST, 1, - GBST, 1, - Offset(0x01), - PBST, 1, - , 1, - RTST, 1, - , 3, - PWST, 1, - SPWS, 1, - Offset(0x02), - TMEN, 1, - , 4, - GBEN, 1, - Offset(0x03), - PBEN, 1, - , 1, - RTEN, 1, - , 3, - PWDA, 1, -} - -/* Wake status package */ -Name(WKST,Package() {Zero, Zero}) - -/* - * \_WAK System Wake method - * - * Entry: - * Arg0=The value of the sleeping state S1=1, S2=2 - * - * Exit: - * Return package of 2 DWords - * Dword 1 - Status - * 0x00000000 wake succeeded - * 0x00000001 Wake was signaled but failed due to lack of power - * 0x00000002 Wake was signaled but failed due to thermal condition - * Dword 2 - Power Supply state - * if non-zero the effective S-state the power supply entered - */ -Method(\_WAK, 1) { - Store (0x20, DBG8) - - /* Set up LEDs */ - /* Set power LED to steady on */ - Store(0x0, BLNK) - - /* Configure SuperIO for wake */ - /* Access SuperIO ACPI device */ - Store(0x87, INDX) - Store(0x87, INDX) - Store(0x0A, CR07) - - if (LEqual(Arg0, One)) /* Resuming from power state S1 */ - { - /* Deactivate the ACPI device */ - Store(Zero, CR30) - - /* Disable PS/2 SMI/PME events */ - And(CRF6, 0xCF, CRF6) - } - if (Lor(LEqual(Arg0, 0x03), LEqual(Arg0, 0x04))) /* Resuming from power state S3 or S4 */ - { - /* Disable PS/2 wake */ - And(CRE0, 0x1D, CRE0) - And(CRE6, 0x7F, CRE6) - } - - /* Restore default SuperIO access */ - Store(0xAA, INDX) - - Store (0x21, DBG8) - - /* Re-enable HPET */ - Store(1, HPDE) - - /* Restore PCIRST# so it resets USB */ - if (LEqual(Arg0, 3)){ - Store(1, URRE) - } - - /* Configure southbridge for wake */ - /* Arbitrarily clear PciExpWakeStatus */ - Store(PWST, Local1) - Store(Local1, PWST) - - Store (0x22, DBG8) - - Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ - - Return(WKST) -} - -/* - * \_PTS - Prepare to Sleep method - * - * Entry: - * Arg0=The value of the sleeping state S1=1, S2=2, etc - * - * Exit: - * -none- - * - * The _PTS control method is executed at the beginning of the sleep process - * for S1-S5. The sleeping value is passed to the _PTS control method. This - * control method may be executed a relatively long time before entering the - * sleep state and the OS may abort the operation without notification to - * the ACPI driver. This method cannot modify the configuration or power - * state of any device in the system. - */ -Method(\_PTS, 1) { - Store (Arg0, DBG8) - - /* Set up LEDs */ - if (LEqual(Arg0, One)) /* Power state S1 requested */ - { - /* Set suspend LED to 0.25Hz toggle pulse with 50% duty cycle */ - Store(0x2, BLNK) - } - - /* Configure SuperIO for sleep */ - /* Access SuperIO ACPI device */ - Store(0x87, INDX) - Store(0x87, INDX) - Store(0x0A, CR07) - - /* Disable PS/2 wakeup and connect PANSW_IN to PANSW_OUT */ - And(CRE0, 0x1F, CRE0) - - if (LEqual(Arg0, One)) /* Power state S1 requested */ - { - /* Activate the ACPI device */ - Store(One, CR30) - - /* Disable SMI/PME events for: - * LPT - * FDC - * UART - */ - Store(0x00, CRF6) - - /* Enable PS/2 keyboard SMI/PME events */ - Or(CRF6, 0x10, CRF6) - - /* Enable PS/2 keyboard wake */ - Or(CRE0, 0x40, CRE0) - - /* Enable PS/2 mouse SMI/PME events */ - Or(CRF6, 0x20, CRF6) - - /* Enable PS/2 mouse wake */ - Or(CRE0, 0x20, CRE0) - } else { - /* Enable PS/2 keyboard wake on any keypress */ - Or(CRE0, 0x41, CRE0) - - /* Enable PS/2 mouse wake on any click */ - Or(CRE0, 0x22, CRE0) - Or(CRE6, 0x80, CRE6) - - if (LEqual(Arg0, 0x03)) /* Power state S3 requested */ - { - /* Set VSBGATE# to provide standby power during S3 */ - Or(CRE4, 0x10, CRE4) - } - } - - /* Restore default SuperIO access */ - Store(0xAA, INDX) - - Store (0x10, DBG8) - - /* Don't allow PCIRST# to reset USB */ - if (LEqual(Arg0, 3)){ - Store(0, URRE) - } - - /* Configure southbridge for sleep */ - /* Use bus clock for delay timebase */ - Store(0, BCDL) - /* Defer APIC interrupts until first ACPI access */ - Store(One, MAPC) - - /* On older chips, clear PciExpWakeDisEn */ - // if (LLessEqual(SBRI, 0x13)) { - // Store(0, PWDE) - // } - - Store (0x11, DBG8) - - /* Clear wake status structure. */ - Store(0, Index(WKST,0)) - Store(0, Index(WKST,1)) -} diff --git a/src/mainboard/asus/kgpe-d16/acpi_tables.c b/src/mainboard/asus/kgpe-d16/acpi_tables.c deleted file mode 100644 index 53622bae0c..0000000000 --- a/src/mainboard/asus/kgpe-d16/acpi_tables.c +++ /dev/null @@ -1,103 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2010 Advanced Micro Devices, Inc. - * Copyright (C) 2015 Timothy Pearson , Raptor Engineering - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include -#include -#include - -unsigned long acpi_fill_madt(unsigned long current) -{ - struct device *dev; - u32 dword; - u32 gsi_base = 0; - uint32_t apicid_sp5100; - uint32_t apicid_sr5650; - /* create all subtables for processors */ - current = acpi_create_madt_lapics(current); - - if (CONFIG(ENABLE_APIC_EXT_ID) && (CONFIG_APIC_ID_OFFSET > 0)) - apicid_sp5100 = 0x0; - else - apicid_sp5100 = 0x20; - apicid_sr5650 = apicid_sp5100 + 1; - - /* Write SB700 IOAPIC, only one */ - current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, apicid_sp5100, - IO_APIC_ADDR, gsi_base); - /* IOAPIC on rs5690 */ - gsi_base += 24; /* SB700 has 24 IOAPIC entries. */ - dev = pcidev_on_root(0, 0); - if (dev) { - pci_write_config32(dev, 0xF8, 0x1); - dword = pci_read_config32(dev, 0xFC) & 0xfffffff0; - current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, apicid_sr5650, - dword, gsi_base); - } - - /* bus, source, gsirq, flags */ - current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) - current, 0, 0, 2, 0); - current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) - current, 0, 9, 9, 0xf); - - /* create all subtables for processors */ - current += acpi_create_madt_lapic_nmi((acpi_madt_lapic_nmi_t *)current, 0xff, 0, 1); - /* 1: LINT1 connect to NMI */ - - return current; -} - -unsigned long acpi_fill_ivrs_ioapic(acpi_ivrs_t *ivrs, unsigned long current) -{ - uint8_t *p; - - uint32_t apicid_sp5100; - uint32_t apicid_sr5650; - - if (CONFIG(ENABLE_APIC_EXT_ID) && (CONFIG_APIC_ID_OFFSET > 0)) - apicid_sp5100 = 0x0; - else - apicid_sp5100 = 0x20; - apicid_sr5650 = apicid_sp5100 + 1; - - /* Describe NB IOAPIC */ - p = (uint8_t *)current; - p[0] = 0x48; /* Entry type */ - p[1] = 0; /* Device */ - p[2] = 0; /* Bus */ - p[3] = 0x0; /* Data */ - p[4] = apicid_sr5650; /* IOAPIC ID */ - p[5] = 0x1; /* Device 0 Function 1 */ - p[6] = 0x0; /* Northbridge bus */ - p[7] = 0x1; /* Variety */ - current += 8; - - /* Describe SB IOAPIC */ - p = (uint8_t *)current; - p[0] = 0x48; /* Entry type */ - p[1] = 0; /* Device */ - p[2] = 0; /* Bus */ - p[3] = 0xd7; /* Data */ - p[4] = apicid_sp5100; /* IOAPIC ID */ - p[5] = 0x14 << 3; /* Device 0x14 Function 0 */ - p[6] = 0x0; /* Southbridge bus */ - p[7] = 0x1; /* Variety */ - current += 8; - - return current; -} diff --git a/src/mainboard/asus/kgpe-d16/board_info.txt b/src/mainboard/asus/kgpe-d16/board_info.txt deleted file mode 100644 index e69d31aab1..0000000000 --- a/src/mainboard/asus/kgpe-d16/board_info.txt +++ /dev/null @@ -1,5 +0,0 @@ -Category: server -ROM package: DIP-8 -ROM protocol: SPI -ROM socketed: y -Flashrom support: y diff --git a/src/mainboard/asus/kgpe-d16/bootblock.c b/src/mainboard/asus/kgpe-d16/bootblock.c deleted file mode 100644 index 543ffed9c7..0000000000 --- a/src/mainboard/asus/kgpe-d16/bootblock.c +++ /dev/null @@ -1,52 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2015 Timothy Pearson , Raptor Engineering - * Copyright (C) 2014 Edward O'Callaghan - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include - -void bootblock_mainboard_init(void) -{ - uint8_t recovery_enabled; - unsigned char addr; - unsigned char byte; - - bootblock_northbridge_init(); - bootblock_southbridge_init(); - - /* Recovery jumper is connected to SP5100 GPIO61, and clears the GPIO when placed in the Recovery position */ - byte = pci_io_read_config8(PCI_DEV(0, 0x14, 0), 0x56); - byte |= 0x1 << 4; /* Set GPIO61 to input mode */ - pci_io_write_config8(PCI_DEV(0, 0x14, 0), 0x56, byte); - recovery_enabled = (!(pci_io_read_config8(PCI_DEV(0, 0x14, 0), 0x57) & 0x1)); - if (recovery_enabled) { -#if CONFIG(USE_OPTION_TABLE) - /* Clear NVRAM checksum */ - for (addr = LB_CKS_RANGE_START; addr <= LB_CKS_RANGE_END; addr++) { - cmos_write(0x0, addr); - } - - /* Set fallback boot */ - byte = cmos_read(RTC_BOOT_BYTE); - byte &= 0xfc; - cmos_write(byte, RTC_BOOT_BYTE); -#else - /* FIXME - * Figure out how to recover if the option table is not available - */ -#endif - } -} diff --git a/src/mainboard/asus/kgpe-d16/cmos.default b/src/mainboard/asus/kgpe-d16/cmos.default deleted file mode 100644 index 7c496a50d7..0000000000 --- a/src/mainboard/asus/kgpe-d16/cmos.default +++ /dev/null @@ -1,30 +0,0 @@ -debug_level=Debug -multi_core=Enable -slow_cpu=off -compute_unit_siblings=Enable -iommu=Enable -nmi=Disable -hypertransport_speed_limit=Auto -max_mem_clock=DDR3-1600 -minimum_memory_voltage=1.5V -dimm_spd_checksum=Enforce -ECC_memory=Enable -ECC_redirection=Enable -ecc_scrub_rate=1.28us -interleave_chip_selects=Enable -interleave_nodes=Disable -interleave_memory_channels=Enable -cpu_c_states=Enable -cpu_cc6_state=Enable -cpu_core_boost=Enable -sata_ahci_mode=Enable -sata_alpm=Disable -maximum_p_state_limit=0xf -probe_filter=Auto -l3_cache_partitioning=Disable -ieee1394_controller=Enable -gart=Enable -ehci_async_data_cache=Enable -experimental_memory_speed_boost=Disable -power_on_after_fail=On -boot_option=Fallback diff --git a/src/mainboard/asus/kgpe-d16/cmos.layout b/src/mainboard/asus/kgpe-d16/cmos.layout deleted file mode 100644 index 1c8d4662c3..0000000000 --- a/src/mainboard/asus/kgpe-d16/cmos.layout +++ /dev/null @@ -1,150 +0,0 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2015 Timothy Pearson , Raptor Engineering -## Copyright (C) 2007 AMD -## Written by Yinghai Lu for AMD. -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; either version 2 of the License, or -## (at your option) any later version. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## - -entries - -0 384 r 0 reserved_memory -384 1 e 4 boot_option -388 4 h 0 reboot_counter -393 3 r 0 unused -#394 7 unused -401 1 e 1 interleave_chip_selects -402 1 e 1 interleave_nodes -403 1 e 1 interleave_memory_channels -404 4 e 8 max_mem_clock -408 1 e 2 multi_core -412 4 e 6 debug_level -416 5 e 10 ecc_scrub_rate -440 4 e 9 slow_cpu -444 1 e 1 nmi -445 1 e 1 gart -446 2 e 3 power_on_after_fail -456 1 e 1 ECC_memory -457 1 e 1 ECC_redirection -458 4 e 11 hypertransport_speed_limit -462 2 e 12 minimum_memory_voltage -464 1 e 2 compute_unit_siblings -465 1 e 1 cpu_c_states -466 1 e 1 cpu_cc6_state -467 1 e 1 sata_ahci_mode -468 1 e 1 sata_alpm -#469 4 unused -473 2 e 13 dimm_spd_checksum -475 1 e 14 probe_filter -476 1 e 1 l3_cache_partitioning -477 1 e 1 ieee1394_controller -478 1 e 1 iommu -479 1 e 1 cpu_core_boost -480 1 e 2 ehci_async_data_cache -481 1 e 1 experimental_memory_speed_boost -482 1 r 0 allow_spd_nvram_cache_restore -483 4 h 0 maximum_p_state_limit -728 256 h 0 user_data -984 16 h 0 check_sum -# Reserve the extended AMD configuration registers -1000 24 r 0 amd_reserved - - - -enumerations - -#ID value text -1 0 Disable -1 1 Enable -2 0 Enable -2 1 Disable -3 0 Off -3 1 On -3 2 Last -4 0 Fallback -4 1 Normal -6 0 Emergency -6 1 Alert -6 2 Critical -6 3 Error -6 4 Warning -6 5 Notice -6 6 Information -6 7 Debug -6 8 Spew -8 0 DDR3-1866 -8 1 DDR3-1600 -8 2 DDR3-1333 -8 3 DDR3-1066 -8 4 DDR3-800 -8 5 DDR3-667 -9 0 off -9 1 87.5% -9 2 75.0% -9 3 62.5% -9 4 50.0% -9 5 37.5% -9 6 25.0% -9 7 12.5% -10 0 Disabled -10 1 40ns -10 2 80ns -10 3 160ns -10 4 320ns -10 5 640ns -10 6 1.28us -10 7 2.56us -10 8 5.12us -10 9 10.2us -10 10 20.5us -10 11 41us -10 12 81.9us -10 13 163.8us -10 14 327.7us -10 15 655.4us -10 16 1.31ms -10 17 2.62ms -10 18 5.24ms -10 19 10.49ms -10 20 20.97ms -10 21 42ms -10 22 84ms -11 0 Auto -11 1 3.2GHz -11 2 3.0GHz -11 3 2.8GHz -11 4 2.6GHz -11 5 2.4GHz -11 6 2.2GHz -11 7 2.0GHz -11 8 1.8GHz -11 9 1.6GHz -11 10 1.4GHz -11 11 1.2GHz -11 12 1.0GHz -11 13 800MHz -11 14 600MHz -11 15 500MHz -12 0 1.5V -12 1 1.35V -12 2 1.25V -12 3 1.15V -13 0 Enforce -13 1 Ignore -13 2 Override -14 0 Disable -14 1 Auto - -checksums - -checksum 392 983 984 diff --git a/src/mainboard/asus/kgpe-d16/devicetree.cb b/src/mainboard/asus/kgpe-d16/devicetree.cb deleted file mode 100644 index 31bd3e349f..0000000000 --- a/src/mainboard/asus/kgpe-d16/devicetree.cb +++ /dev/null @@ -1,259 +0,0 @@ -chip northbridge/amd/amdfam10/root_complex # Root complex - device cpu_cluster 0 on # (L)APIC cluster - chip cpu/amd/socket_F_1207 # CPU socket - device lapic 0 on end # Local APIC of the CPU - end - end - device domain 0 on # PCI domain - subsystemid 0x1043 0x8163 inherit - chip northbridge/amd/amdfam10 # Northbridge / RAM controller - register "maximum_memory_capacity" = "0x4000000000" # 256GB - device pci 18.0 on end # Link 0 == LDT 0 - device pci 18.0 on end # Link 1 == LDT 1 - device pci 18.0 on end # Link 2 == LDT 2 - device pci 18.0 on # Link 3 == LDT 3 [SB on link 3] - chip southbridge/amd/sr5650 # Primary southbridge - device pci 0.0 on end # HT Root Complex 0x9600 - device pci 0.1 on end # CLKCONFIG - device pci 0.2 on end # IOMMU - device pci 2.0 on # PCIE P2P bridge 0x9603 (GPP1 Port0) - # Slot # PCI E 1 / PCI E 2 - end - device pci 3.0 off end # PCIE P2P bridge 0x960b (GPP1 Port1) - device pci 4.0 on # PCIE P2P bridge 0x9604 (GPP3a Port0) - # PIKE SAS - end - device pci 5.0 off end # PCIE P2P bridge 0x9605 (GPP3a Port1) - device pci 6.0 off end # PCIE P2P bridge 0x9606 (GPP3a Port2) - device pci 7.0 off end # PCIE P2P bridge 0x9607 (GPP3a Port3) - device pci 8.0 off end # NB/SB Link P2P bridge - device pci 9.0 on # Bridge (GPP3a Port4) - # Onboard # NIC A - end - device pci a.0 on # Bridge (GPP3a Port5) - # Onboard # NIC B - end - device pci b.0 on # Bridge (GPP2 Port0) - # Slot # PCI E 4 - end - device pci c.0 on # Bridge (GPP2 Port1) - # Slot # PCI E 5 - end - device pci d.0 on # Bridge (GPP3b Port0) - # Slot # PCI E 3 - end - register "gpp1_configuration" = "0" # Configuration 16:0 default - register "gpp2_configuration" = "1" # Configuration 8:8 - register "gpp3a_configuration" = "2" # Configuration 4:1:1:0:0:0 - register "port_enable" = "0x3f1c" # Enable all ports except 0, 1, 5, 6, and 7 - register "pcie_settling_time" = "1000000" # Allow PIKE to be detected / configured - end - chip southbridge/amd/sb700 # Secondary southbridge - device pci 11.0 on end # SATA - device pci 12.0 on end # USB - device pci 12.1 on end # USB - device pci 12.2 on end # USB - device pci 13.0 on end # USB - device pci 13.1 on end # USB - device pci 13.2 on end # USB - device pci 14.0 on # SM - chip drivers/generic/generic # DIMM n-0-0-0 - device i2c 50 on end - end - chip drivers/generic/generic # DIMM n-0-0-1 - device i2c 51 on end - end - chip drivers/generic/generic # DIMM n-0-1-0 - device i2c 52 on end - end - chip drivers/generic/generic # DIMM n-0-1-1 - device i2c 53 on end - end - chip drivers/generic/generic # DIMM n-1-0-0 - device i2c 54 on end - end - chip drivers/generic/generic # DIMM n-1-0-1 - device i2c 55 on end - end - chip drivers/generic/generic # DIMM n-1-1-0 - device i2c 56 on end - end - chip drivers/generic/generic # DIMM n-1-1-1 - device i2c 57 on end - end - chip drivers/i2c/w83795 - register "fanin_ctl1" = "0xff" # Enable monitoring of FANIN1 - FANIN8 - register "fanin_ctl2" = "0x00" # Connect FANIN11 - FANIN14 to alternate functions - register "temp_ctl1" = "0x2a" # Enable monitoring of DTS, VSEN12, and VSEN13 - register "temp_ctl2" = "0x01" # Enable monitoring of TD1/TR1 - register "temp_dtse" = "0x03" # Enable DTS1 and DTS2 - register "volt_ctl1" = "0xff" # Enable monitoring of VSEN1 - VSEN8 - register "volt_ctl2" = "0xf7" # Enable monitoring of VSEN9 - VSEN11, 3VDD, 3VSB, and VBAT - register "temp1_fan_select" = "0x00" # All fans to manual mode (no dependence on Temp1) - register "temp2_fan_select" = "0x00" # All fans to manual mode (no dependence on Temp2) - register "temp3_fan_select" = "0x00" # All fans to manual mode (no dependence on Temp3) - register "temp4_fan_select" = "0x00" # All fans to manual mode (no dependence on Temp4) - register "temp5_fan_select" = "0x00" # All fans to manual mode (no dependence on Temp5) - register "temp6_fan_select" = "0x00" # All fans to manual mode (no dependence on Temp6) - register "temp1_source_select" = "0x00" # Use TD1/TR1 as data source for Temp1 - register "temp2_source_select" = "0x00" # Use TD2/TR2 as data source for Temp2 - register "temp3_source_select" = "0x00" # Use TD3/TR3 as data source for Temp3 - register "temp4_source_select" = "0x00" # Use TD4/TR4 as data source for Temp4 - register "temp5_source_select" = "0x00" # Use TR5 as data source for Temp5 - register "temp6_source_select" = "0x00" # Use TR6 as data source for Temp6 - register "tr1_critical_temperature" = "85" # Set TD1/TR1 critical temperature to 85°C - register "tr1_critical_hysteresis" = "80" # Set TD1/TR1 critical hysteresis temperature to 80°C - register "tr1_warning_temperature" = "70" # Set TD1/TR1 warning temperature to 70°C - register "tr1_warning_hysteresis" = "65" # Set TD1/TR1 warning hysteresis temperature to 65°C - register "dts_critical_temperature" = "85" # Set DTS (CPU) critical temperature to 85°C - register "dts_critical_hysteresis" = "80" # Set DTS (CPU) critical hysteresis temperature to 80°C - register "dts_warning_temperature" = "70" # Set DTS (CPU) warning temperature to 70°C - register "dts_warning_hysteresis" = "65" # Set DTS (CPU) warning hysteresis temperature to 65°C - register "temp1_critical_temperature" = "80" # Set Temp1 critical temperature to 80°C - register "temp2_critical_temperature" = "80" # Set Temp1 critical temperature to 80°C - register "temp3_critical_temperature" = "80" # Set Temp1 critical temperature to 80°C - register "temp4_critical_temperature" = "80" # Set Temp1 critical temperature to 80°C - register "temp5_critical_temperature" = "80" # Set Temp1 critical temperature to 80°C - register "temp6_critical_temperature" = "80" # Set Temp1 critical temperature to 80°C - register "temp1_target_temperature" = "80" # Set Temp1 target temperature to 80°C - register "temp2_target_temperature" = "80" # Set Temp1 target temperature to 80°C - register "temp3_target_temperature" = "80" # Set Temp1 target temperature to 80°C - register "temp4_target_temperature" = "80" # Set Temp1 target temperature to 80°C - register "temp5_target_temperature" = "80" # Set Temp1 target temperature to 80°C - register "temp6_target_temperature" = "80" # Set Temp1 target temperature to 80°C - register "fan1_nonstop" = "7" # Set Fan 1 minimum speed - register "fan2_nonstop" = "7" # Set Fan 2 minimum speed - register "fan3_nonstop" = "7" # Set Fan 3 minimum speed - register "fan4_nonstop" = "7" # Set Fan 4 minimum speed - register "fan5_nonstop" = "7" # Set Fan 5 minimum speed - register "fan6_nonstop" = "7" # Set Fan 6 minimum speed - register "fan7_nonstop" = "7" # Set Fan 7 minimum speed - register "fan8_nonstop" = "7" # Set Fan 8 minimum speed - register "default_speed" = "100" # All fans to full speed on power up - register "fan1_duty" = "100" # Fan 1 to full speed - register "fan2_duty" = "100" # Fan 2 to full speed - register "fan3_duty" = "100" # Fan 3 to full speed - register "fan4_duty" = "100" # Fan 4 to full speed - register "fan5_duty" = "100" # Fan 5 to full speed - register "fan6_duty" = "100" # Fan 6 to full speed - register "fan7_duty" = "100" # Fan 7 to full speed - register "fan8_duty" = "100" # Fan 8 to full speed - register "vcore1_high_limit_mv" = "1500" # VCORE1 (Node 0) high limit to 1.5V - register "vcore1_low_limit_mv" = "900" # VCORE1 (Node 0) low limit to 0.9V - register "vcore2_high_limit_mv" = "1500" # VCORE2 (Node 1) high limit to 1.5V - register "vcore2_low_limit_mv" = "900" # VCORE2 (Node 1) low limit to 0.9V - register "vsen3_high_limit_mv" = "1600" # VSEN1 (Node 0 RAM voltage) high limit to 1.6V - register "vsen3_low_limit_mv" = "1100" # VSEN1 (Node 0 RAM voltage) low limit to 1.1V - register "vsen4_high_limit_mv" = "1600" # VSEN2 (Node 1 RAM voltage) high limit to 1.6V - register "vsen4_low_limit_mv" = "1100" # VSEN2 (Node 1 RAM voltage) low limit to 1.1V - register "vsen5_high_limit_mv" = "1250" # VSEN5 (Node 0 HT link voltage) high limit to 1.25V - register "vsen5_low_limit_mv" = "1150" # VSEN5 (Node 0 HT link voltage) low limit to 1.15V - register "vsen6_high_limit_mv" = "1250" # VSEN6 (Node 1 HT link voltage) high limit to 1.25V - register "vsen6_low_limit_mv" = "1150" # VSEN6 (Node 1 HT link voltage) low limit to 1.15V - register "vsen7_high_limit_mv" = "1250" # VSEN7 (Northbridge core voltage) high limit to 1.25V - register "vsen7_low_limit_mv" = "1050" # VSEN7 (Northbridge core voltage) low limit to 1.05V - register "vsen8_high_limit_mv" = "1900" # VSEN8 (+1.8V) high limit to 1.9V - register "vsen8_low_limit_mv" = "1700" # VSEN8 (+1.8V) low limit to 1.7V - register "vsen9_high_limit_mv" = "1250" # VSEN9 (+1.2V) high limit to 1.25V - register "vsen9_low_limit_mv" = "1150" # VSEN9 (+1.2V) low limit to 1.15V - register "vsen10_high_limit_mv" = "1150" # VSEN10 (+1.1V) high limit to 1.15V - register "vsen10_low_limit_mv" = "1050" # VSEN10 (+1.1V) low limit to 1.05V - register "vsen11_high_limit_mv" = "1625" # VSEN11 (5VSB, scaling factor ~3.2) high limit to 5.2V - register "vsen11_low_limit_mv" = "1500" # VSEN11 (5VSB, scaling factor ~3.2) low limit to 4.8V - register "vsen12_high_limit_mv" = "1083" # VSEN12 (+12V, scaling factor ~12) high limit to 13V - register "vsen12_low_limit_mv" = "917" # VSEN12 (+12V, scaling factor ~12) low limit to 11V - register "vsen13_high_limit_mv" = "1625" # VSEN13 (+5V, scaling factor ~3.2) high limit to 5.2V - register "vsen13_low_limit_mv" = "1500" # VSEN13 (+5V, scaling factor ~3.2) low limit to 4.8V - register "vdd_high_limit_mv" = "3500" # 3VDD high limit to 3.5V - register "vdd_low_limit_mv" = "3100" # 3VDD low limit to 3.1V - register "vsb_high_limit_mv" = "3500" # 3VSB high limit to 3.5V - register "vsb_low_limit_mv" = "3100" # 3VSB low limit to 3.1V - register "vbat_high_limit_mv" = "3500" # VBAT (+3V) high limit to 3.5V - register "vbat_low_limit_mv" = "2500" # VBAT (+3V) low limit to 2.5V - register "smbus_aux" = "1" # Device located on auxiliary SMBUS controller - device i2c 0x2f on end - end - end - device pci 14.1 on end # IDE 0x439c - device pci 14.2 on end # HDA 0x4383 (ASUS MIO add-on card) - device pci 14.3 on # LPC 0x439d (SMBUS primary controller) - chip superio/winbond/w83667hg-a # Super I/O - device pnp 2e.0 off end # FDC; Not available on the KGPE-D16 - device pnp 2e.1 off end # LPT1; Not available on the KGPE-D16 - device pnp 2e.2 on # COM1 - io 0x60 = 0x3f8 - irq 0x70 = 4 - end - device pnp 2e.3 on # COM2 - io 0x60 = 0x2f8 - irq 0x70 = 3 - end - device pnp 2e.5 on # PS/2 keyboard & mouse - io 0x60 = 0x60 - io 0x62 = 0x64 - irq 0x70 = 1 - irq 0x72 = 12 - end - device pnp 2e.106 off end # SPI: Not available on the KGPE-D16 - device pnp 2e.107 off end # GIPO6 - device pnp 2e.207 off end # GIPO7 - device pnp 2e.307 off end # GIPO8 - device pnp 2e.407 off end # GIPO9 - device pnp 2e.8 off end # WDT - device pnp 2e.108 off end # GPIO 1 - device pnp 2e.9 off end # GPIO2 - device pnp 2e.109 off end # GPIO3 - device pnp 2e.209 off end # GPIO4 - device pnp 2e.309 off end # GPIO5 - device pnp 2e.a on end # ACPI - device pnp 2e.b on # HW Monitor - io 0x60 = 0x290 - # IRQ purposefully not assigned to prevent lockups - end - device pnp 2e.c off end # PECI - device pnp 2e.d off end # VID_BUSSEL - device pnp 2e.f off end # GPIO_PP_OD - end - chip drivers/pc80/tpm - device pnp 4e.0 on end # TPM module - end - chip drivers/ipmi # BMC KCS - device pnp ca2.0 on end - end - end - device pci 14.4 on # Bridge - device pci 1.0 on end # VGA - device pci 2.0 on end # FireWire - device pci 3.0 on # Slot - # Slot # PCI 0 - end - end - device pci 14.5 on end # USB OHCI2 0x4399 - end - end - device pci 18.1 on end - device pci 18.2 on end - device pci 18.3 on end - device pci 18.4 on end - device pci 18.5 on end - device pci 19.0 on end # Socket 0 node 1 - device pci 19.1 on end - device pci 19.2 on end - device pci 19.3 on end - device pci 19.4 on end - device pci 19.5 on end - device pci 1a.0 on end # Socket 1 node 0 - device pci 1a.1 on end - device pci 1a.2 on end - device pci 1a.3 on end - device pci 1a.4 on end - device pci 1a.5 on end - device pci 1b.0 on end # Socket 1 node 1 - device pci 1b.1 on end - device pci 1b.2 on end - device pci 1b.3 on end - device pci 1b.4 on end - device pci 1b.5 on end - end - end -end diff --git a/src/mainboard/asus/kgpe-d16/dsdt.asl b/src/mainboard/asus/kgpe-d16/dsdt.asl deleted file mode 100644 index efb67a558c..0000000000 --- a/src/mainboard/asus/kgpe-d16/dsdt.asl +++ /dev/null @@ -1,809 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2015 Timothy Pearson , Raptor Engineering - * Copyright (C) 2005 - 2012 Advanced Micro Devices, Inc. - * Copyright (C) 2007-2009 coresystems GmbH - * Copyright (C) 2004 Nick Barker - * Copyright (C) 2007, 2008 Rudolf Marek - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -/* - * WARNING: Sleep/Wake is a work in progress and is still somewhat flaky! - * Everything else does to the best of my knowledge... (T.P. 01/26/2015) - */ - -/* - * ISA portions taken from QEMU acpi-dsdt.dsl. - */ - -/* - * PCI link routing templates taken from ck804.asl and modified for this board - */ - -#include -DefinitionBlock ( - "DSDT.AML", /* Output filename */ - "DSDT", /* Signature */ - 0x02, /* DSDT Revision, needs to be 2 or higher for 64bit */ - OEM_ID, - ACPI_TABLE_CREATOR, - 0x00000001 /* OEM Revision */ - ) -{ - #include - #include - - /* Some global data */ - Name(OSVR, 3) /* Assume nothing. WinXp = 1, Vista = 2, Linux = 3, WinCE = 4 */ - Name(OSV, Ones) /* Assume nothing */ - Name(PICM, One) /* Assume APIC */ - - /* HPET enable */ - Name (HPTE, 0x1) - - #include - - /* The _PIC method is called by the OS to choose between interrupt - * routing via the i8259 interrupt controller or the APIC. - * - * _PIC is called with a parameter of 0 for i8259 configuration and - * with a parameter of 1 for Local Apic/IOAPIC configuration. - */ - Method (_PIC, 1, Serialized) { - If (Arg0) - { - \_SB.CIRQ() - } - Store (Arg0, PICM) - } - - /* _PR CPU0 is dynamically supplied by SSDT */ - /* CPU objects and _PSS entries are dynamically supplied by SSDT */ - - Scope(\_GPE) { /* Start Scope GPE */ - /* General event 3 */ - Method(_L03) { - /* Level-Triggered GPE */ - Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ - } - - /* General event 4 */ - Method(_L04) { - /* Level-Triggered GPE */ - Notify (\_SB.PCI0.PBR0, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify (\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ - } - - /* Keyboard controller PME# */ - Method(_L08) { - /* Level-Triggered GPE */ - Notify(\_SB.PCI0.LPC.PS2K, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(\_SB.PCI0.LPC.PS2M, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ - } - - /* USB controller PME# */ - Method(_L0B) { - /* Level-Triggered GPE */ - Notify (\_SB.PCI0.USB0, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify (\_SB.PCI0.USB1, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify (\_SB.PCI0.USB2, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify (\_SB.PCI0.USB3, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify (\_SB.PCI0.USB4, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify (\_SB.PCI0.USB5, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify (\_SB.PCI0.USB6, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify (\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ - } - - /* GPIO0 or GEvent8 event */ - Method(_L18) { - /* Level-Triggered GPE */ - Notify (\_SB.PCI0.PCE1, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify (\_SB.PCI0.NICA, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify (\_SB.PCI0.NICB, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify (\_SB.PCI0.PCE4, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify (\_SB.PCI0.PCE5, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify (\_SB.PCI0.PCE3, 0x02) /* NOTIFY_DEVICE_WAKE */ - } - - } /* End Scope GPE */ - - /* Root of the bus hierarchy */ - Scope (\_SB) - { - /* Top southbridge PCI device (SR5690 + SP5100) */ - Device (PCI0) - { - /* BUS0 root bus */ - - Name (_HID, EisaId ("PNP0A08")) /* PCI-e root bus (SR5690) */ - Name (_CID, EisaId ("PNP0A03")) /* PCI root bus (SP5100) */ - Name (_ADR, 0x00180001) - Name (_UID, 0x00) - - Name (HCIN, 0x00) // HC1 - - Method (_BBN, 0, NotSerialized) - { - Return (GBUS (GHCN(HCIN), GHCL(HCIN))) - } - - /* Operating System Capabilities Method */ - Method(_OSC,4) - { - /* Let OS control everything */ - Return (Arg3) - } - - External (BUSN) - External (MMIO) - External (PCIO) - External (SBLK) - External (TOM1) - External (HCLK) - External (SBDN) - External (HCDN) - External (CBST) - - /* PCI Routing Tables */ - Name (PR00, Package () { - /* PIC */ - /* Top southbridge device (SR5690) */ - /* HT Link */ - Package (0x04) { 0x0000FFFF, 0x00, LNKA, 0x00 }, - - /* PCI-E Slot 1 (Bridge) */ - Package (0x04) { 0x0002FFFF, 0x00, LNKE, 0x00 }, - - /* NIC A (Bridge) */ - Package (0x04) { 0x0009FFFF, 0x00, LNKF, 0x00 }, - - /* NIC B (Bridge) */ - Package (0x04) { 0x000AFFFF, 0x00, LNKG, 0x00 }, - - /* PCI-E Slot 4 (Bridge) */ - Package (0x04) { 0x000BFFFF, 0x00, LNKG, 0x00 }, - - /* PCI-E Slot 5 (Bridge) */ - Package (0x04) { 0x000CFFFF, 0x00, LNKG, 0x00 }, - - /* PCI-E Slot 3 (Bridge) */ - Package (0x04) { 0x000DFFFF, 0x00, LNKG, 0x00 }, - - /* Bottom southbridge device (SP5100) */ - /* SATA 0 */ - Package (0x04) { 0x0011FFFF, 0x00, LNKG, 0x00 }, - - /* USB 0 */ - Package (0x04) { 0x0012FFFF, 0x00, LNKA, 0x00 }, - Package (0x04) { 0x0012FFFF, 0x01, LNKB, 0x00 }, - Package (0x04) { 0x0012FFFF, 0x02, LNKC, 0x00 }, - Package (0x04) { 0x0012FFFF, 0x03, LNKD, 0x00 }, - - /* USB 1 */ - Package (0x04) { 0x0013FFFF, 0x00, LNKC, 0x00 }, - Package (0x04) { 0x0013FFFF, 0x01, LNKD, 0x00 }, - Package (0x04) { 0x0013FFFF, 0x02, LNKA, 0x00 }, - Package (0x04) { 0x0013FFFF, 0x03, LNKB, 0x00 }, - - /* SMBUS / IDE / LPC / VGA / FireWire / PCI Slot 0 */ - Package (0x04) { 0x0014FFFF, 0x00, LNKA, 0x00 }, - Package (0x04) { 0x0014FFFF, 0x01, LNKB, 0x00 }, - Package (0x04) { 0x0014FFFF, 0x02, LNKC, 0x00 }, - Package (0x04) { 0x0014FFFF, 0x03, LNKD, 0x00 }, - }) - - Name (AR00, Package () { - /* APIC */ - /* Top southbridge device (SR5690) */ - /* HT Link */ - Package (0x04) { 0x0000FFFF, 0x00, 0x00, 55 }, - - /* PCI-E Slot 1 (Bridge) */ - Package (0x04) { 0x0002FFFF, 0x00, 0x00, 52 }, - - /* NIC A (Bridge) */ - Package (0x04) { 0x0009FFFF, 0x00, 0x00, 53 }, - - /* NIC B (Bridge) */ - Package (0x04) { 0x000AFFFF, 0x00, 0x00, 54 }, - - /* PCI-E Slot 4 (Bridge) */ - Package (0x04) { 0x000BFFFF, 0x00, 0x00, 54 }, - - /* PCI-E Slot 5 (Bridge) */ - Package (0x04) { 0x000CFFFF, 0x00, 0x00, 54 }, - - /* PCI-E Slot 3 (Bridge) */ - Package (0x04) { 0x000DFFFF, 0x00, 0x00, 54 }, - - /* Bottom southbridge device (SP5100) */ - /* SATA 0 */ - Package (0x04) { 0x0011FFFF, 0x00, 0x00, 22 }, - - /* USB 0 */ - Package (0x04) { 0x0012FFFF, 0x00, 0x00, 16 }, - Package (0x04) { 0x0012FFFF, 0x01, 0x00, 17 }, - Package (0x04) { 0x0012FFFF, 0x02, 0x00, 18 }, - Package (0x04) { 0x0012FFFF, 0x03, 0x00, 19 }, - - /* USB 1 */ - Package (0x04) { 0x0013FFFF, 0x00, 0x00, 18 }, - Package (0x04) { 0x0013FFFF, 0x01, 0x00, 19 }, - Package (0x04) { 0x0013FFFF, 0x02, 0x00, 16 }, - Package (0x04) { 0x0013FFFF, 0x03, 0x00, 17 }, - - /* SMBUS / IDE / LPC / VGA / FireWire / PCI Slot 0 */ - Package (0x04) { 0x0014FFFF, 0x00, 0x00, 16 }, - Package (0x04) { 0x0014FFFF, 0x01, 0x00, 17 }, - Package (0x04) { 0x0014FFFF, 0x02, 0x00, 18 }, - Package (0x04) { 0x0014FFFF, 0x03, 0x00, 19 }, - }) - - Name (PR01, Package () { - /* PIC */ - Package (0x04) { 0x1FFFF, 0x00, LNKF, 0x00 }, - Package (0x04) { 0x2FFFF, 0x00, LNKE, 0x00 }, - Package (0x04) { 0x3FFFF, 0x00, LNKG, 0x00 }, - Package (0x04) { 0x3FFFF, 0x01, LNKH, 0x00 }, - Package (0x04) { 0x3FFFF, 0x02, LNKE, 0x00 }, - Package (0x04) { 0x3FFFF, 0x03, LNKF, 0x00 }, - }) - - Name (AR01, Package () { - /* APIC */ - Package (0x04) { 0x1FFFF, 0x00, 0x00, 21 }, - Package (0x04) { 0x2FFFF, 0x00, 0x00, 20 }, - Package (0x04) { 0x3FFFF, 0x00, 0x00, 22 }, - Package (0x04) { 0x3FFFF, 0x01, 0x00, 23 }, - Package (0x04) { 0x3FFFF, 0x02, 0x00, 20 }, - Package (0x04) { 0x3FFFF, 0x03, 0x00, 21 }, - }) - - Name (PR02, Package () { - /* PIC */ - Package (0x04) { 0xFFFF, 0x00, LNKA, 0x00 }, - Package (0x04) { 0xFFFF, 0x01, LNKB, 0x00 }, - Package (0x04) { 0xFFFF, 0x02, LNKC, 0x00 }, - Package (0x04) { 0xFFFF, 0x03, LNKD, 0x00 }, - }) - - Name (AR02, Package () { - /* APIC */ - Package (0x04) { 0xFFFF, 0x00, 0x00, 24 }, - Package (0x04) { 0xFFFF, 0x01, 0x00, 25 }, - Package (0x04) { 0xFFFF, 0x02, 0x00, 26 }, - Package (0x04) { 0xFFFF, 0x03, 0x00, 27 }, - }) - - Name (PR03, Package () { - /* PIC */ - Package (0x04) { 0xFFFF, 0x00, LNKE, 0x00 }, - Package (0x04) { 0xFFFF, 0x01, LNKF, 0x00 }, - Package (0x04) { 0xFFFF, 0x02, LNKG, 0x00 }, - Package (0x04) { 0xFFFF, 0x03, LNKH, 0x00 }, - }) - - Name (AR03, Package () { - /* APIC */ - Package (0x04) { 0xFFFF, 0x00, 0x00, 44 }, - Package (0x04) { 0xFFFF, 0x01, 0x00, 45 }, - Package (0x04) { 0xFFFF, 0x02, 0x00, 46 }, - Package (0x04) { 0xFFFF, 0x03, 0x00, 47 }, - }) - - Name (PR04, Package () { - /* PIC */ - Package (0x04) { 0xFFFF, 0x00, LNKA, 0x00 }, - Package (0x04) { 0xFFFF, 0x01, LNKB, 0x00 }, - Package (0x04) { 0xFFFF, 0x02, LNKC, 0x00 }, - Package (0x04) { 0xFFFF, 0x03, LNKD, 0x00 }, - }) - - Name (AR04, Package () { - /* APIC */ - Package (0x04) { 0xFFFF, 0x00, 0x00, 48 }, - Package (0x04) { 0xFFFF, 0x01, 0x00, 49 }, - Package (0x04) { 0xFFFF, 0x02, 0x00, 50 }, - Package (0x04) { 0xFFFF, 0x03, 0x00, 51 }, - }) - - Name (PR05, Package () { - /* PIC */ - Package (0x04) { 0xFFFF, 0x00, LNKH, 0x00 }, - Package (0x04) { 0xFFFF, 0x01, LNKE, 0x00 }, - Package (0x04) { 0xFFFF, 0x02, LNKF, 0x00 }, - Package (0x04) { 0xFFFF, 0x03, LNKG, 0x00 }, - }) - - Name (AR05, Package () { - /* APIC */ - Package (0x04) { 0xFFFF, 0x00, 0x00, 47 }, - Package (0x04) { 0xFFFF, 0x01, 0x00, 44 }, - Package (0x04) { 0xFFFF, 0x02, 0x00, 45 }, - Package (0x04) { 0xFFFF, 0x03, 0x00, 46 }, - }) - - Name (PR06, Package () { - /* PIC */ - Package (0x04) { 0xFFFF, 0x00, LNKA, 0x00 }, - Package (0x04) { 0xFFFF, 0x01, LNKB, 0x00 }, - Package (0x04) { 0xFFFF, 0x02, LNKC, 0x00 }, - Package (0x04) { 0xFFFF, 0x03, LNKD, 0x00 }, - }) - - Name (AR06, Package () { - /* APIC */ - Package (0x04) { 0xFFFF, 0x00, 0x00, 32 }, - Package (0x04) { 0xFFFF, 0x01, 0x00, 33 }, - Package (0x04) { 0xFFFF, 0x02, 0x00, 34 }, - Package (0x04) { 0xFFFF, 0x03, 0x00, 35 }, - }) - - Name (PR07, Package () { - /* PIC */ - Package (0x04) { 0xFFFF, 0x00, LNKE, 0x00 }, - Package (0x04) { 0xFFFF, 0x01, LNKF, 0x00 }, - Package (0x04) { 0xFFFF, 0x02, LNKG, 0x00 }, - Package (0x04) { 0xFFFF, 0x03, LNKH, 0x00 }, - }) - - Name (AR07, Package () { - /* APIC */ - Package (0x04) { 0xFFFF, 0x00, 0x00, 36 }, - Package (0x04) { 0xFFFF, 0x01, 0x00, 37 }, - Package (0x04) { 0xFFFF, 0x02, 0x00, 38 }, - Package (0x04) { 0xFFFF, 0x03, 0x00, 39 }, - }) - - Name (PR08, Package () { - /* PIC */ - Package (0x04) { 0xFFFF, 0x00, LNKA, 0x00 }, - Package (0x04) { 0xFFFF, 0x01, LNKB, 0x00 }, - Package (0x04) { 0xFFFF, 0x02, LNKC, 0x00 }, - Package (0x04) { 0xFFFF, 0x03, LNKD, 0x00 }, - }) - - Name (AR08, Package () { - /* APIC */ - Package (0x04) { 0xFFFF, 0x00, 0x00, 40 }, - Package (0x04) { 0xFFFF, 0x01, 0x00, 41 }, - Package (0x04) { 0xFFFF, 0x02, 0x00, 42 }, - Package (0x04) { 0xFFFF, 0x03, 0x00, 43 }, - }) - - /* PCI Resource Tables */ - - /* PCI Resource Settings Access */ - Method (_CRS, 0, Serialized) - { - Name (BUF0, ResourceTemplate () - { - IO (Decode16, - 0x0CF8, // Address Range Minimum - 0x0CF8, // Address Range Maximum - 0x01, // Address Alignment - 0x08, // Address Length - ) - WordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, - 0x0000, // Address Space Granularity - 0x0000, // Address Range Minimum - 0x0CF7, // Address Range Maximum - 0x0000, // Address Translation Offset - 0x0CF8, // Address Length - ,, , TypeStatic) - }) - /* Methods below use SSDT to get actual MMIO regs - The IO ports are from 0xd00, optionally an VGA, - otherwise the info from MMIO is used. - \_SB.GXXX(node, link) - */ - Concatenate (\_SB.GMEM (0x00, \_SB.PCI0.SBLK), BUF0, Local1) - Concatenate (\_SB.GIOR (0x00, \_SB.PCI0.SBLK), Local1, Local2) - Concatenate (\_SB.GWBN (0x00, \_SB.PCI0.SBLK), Local2, Local3) - Return (Local3) - } - - /* PCI Routing Table Access */ - Method (_PRT, 0, NotSerialized) { - If (PICM) { - Return (AR00) - } Else { - Return (PR00) - } - } - - /* 0:11.0 SP5100 SATA 0 */ - Device(SAT0) - { - Name (_ADR, 0x00110000) // _ADR: Address - Name(_PRW, Package () {0x05, 0x04}) // Wake from S1-S4 - #include - } - - /* 0:12.0 SP5100 USB 0 */ - Device (USB0) - { - Name (_ADR, 0x00120000) // _ADR: Address - Name(_PRW, Package () {0x05, 0x04}) // Wake from S1-S4 - } - - /* 0:12.1 SP5100 USB 1 */ - Device (USB1) - { - Name (_ADR, 0x00120001) // _ADR: Address - Name(_PRW, Package () {0x05, 0x04}) // Wake from S1-S4 - } - - /* 0:12.2 SP5100 USB 2 */ - Device (USB2) - { - Name (_ADR, 0x00120002) // _ADR: Address - Name(_PRW, Package () {0x05, 0x04}) // Wake from S1-S4 - } - - /* 0:13.0 SP5100 USB 3 */ - Device (USB3) - { - Name (_ADR, 0x00130000) // _ADR: Address - Name(_PRW, Package () {0x05, 0x04}) // Wake from S1-S4 - } - - /* 0:13.1 SP5100 USB 4 */ - Device (USB4) - { - Name (_ADR, 0x00130001) // _ADR: Address - Name(_PRW, Package () {0x05, 0x04}) // Wake from S1-S4 - } - - /* 0:13.2 SP5100 USB 5 */ - Device (USB5) - { - Name (_ADR, 0x00130002) // _ADR: Address - Name(_PRW, Package () {0x05, 0x04}) // Wake from S1-S4 - } - - /* 0:14.1 SP5100 IDE Controller */ - Device (IDEC) - { - Name (_ADR, 0x00140001) // _ADR: Address - Name(_PRW, Package () {0x05, 0x04}) // Wake from S1-S4 - #include - } - - /* 0:14.3 SP5100 LPC */ - Device (LPC) { - Name (_HID, EisaId ("PNP0A05")) - Name (_ADR, 0x00140003) - - /* Real Time Clock Device */ - Device(RTC0) { - Name(_HID, EISAID("PNP0B00")) /* AT Real Time Clock (not PIIX4 compatible) */ - Name(BUF0, ResourceTemplate() { - IO(Decode16, 0x0070, 0x0070, 0x01, 0x02) - }) - Name(BUF1, ResourceTemplate() { - IRQNoFlags() { 8 } - IO(Decode16, 0x0070, 0x0070, 0x01, 0x02) - }) - Method(_CRS, 0) { - If(HPTE) { - Return(BUF0) - } - Return(BUF1) - } - } - - Device(TMR) { /* Timer */ - Name(_HID,EISAID("PNP0100")) /* System Timer */ - Name(BUF0, ResourceTemplate() { - IO(Decode16, 0x0040, 0x0040, 0x01, 0x04) - }) - Name(BUF1, ResourceTemplate() { - IRQNoFlags() { 0 } - IO(Decode16, 0x0040, 0x0040, 0x01, 0x04) - }) - Method(_CRS, 0) { - If(HPTE) { - Return(BUF0) - } - Return(BUF1) - } - } - - Device(SPKR) { /* Speaker */ - Name(_HID,EISAID("PNP0800")) /* AT style speaker */ - Name(_CRS, ResourceTemplate() { - IO(Decode16, 0x0061, 0x0061, 0, 1) - }) - } - - Device(PIC) { - Name(_HID,EISAID("PNP0000")) /* AT Interrupt Controller */ - Name(_CRS, ResourceTemplate() { - IRQNoFlags() { 2 } - IO(Decode16,0x0020, 0x0020, 0, 2) - IO(Decode16,0x00A0, 0x00A0, 0, 2) - }) - } - - Device(MAD) { /* 8257 DMA */ - Name(_HID,EISAID("PNP0200")) /* Hardware Device ID */ - Name(_CRS, ResourceTemplate() { - DMA(Compatibility,BusMaster,Transfer8){4} - IO(Decode16, 0x0000, 0x0000, 0x10, 0x10) - IO(Decode16, 0x0081, 0x0081, 0x01, 0x03) - IO(Decode16, 0x0087, 0x0087, 0x01, 0x01) - IO(Decode16, 0x0089, 0x0089, 0x01, 0x03) - IO(Decode16, 0x008F, 0x008F, 0x01, 0x01) - IO(Decode16, 0x00C0, 0x00C0, 0x10, 0x20) - }) /* End Name(_SB.PCI0.LpcIsaBr.MAD._CRS) */ - } - - Device(COPR) { - Name(_HID,EISAID("PNP0C04")) /* Math Coprocessor */ - Name(_CRS, ResourceTemplate() { - IO(Decode16, 0x00F0, 0x00F0, 0, 0x10) - IRQNoFlags(){13} - }) - } - - #include - - /* UART 1 */ - Device (URT1) - { - Name (_HID, EisaId ("PNP0501")) // "PNP0501" for UART - Name(_PRW, Package () {0x03, 0x04}) // Wake from S1-S4 - Method (_STA, 0, NotSerialized) - { - Return (0x0f) // Always enable - } - Name (_PRS, ResourceTemplate() { - StartDependentFn(0, 1) { - IO(Decode16, 0x3f8, 0x3f8, 0x8, 0x8) - IRQNoFlags() { 4 } - } EndDependentFn() - }) - Method (_CRS, 0) - { - Return(ResourceTemplate() { - IO(Decode16, 0x3f8, 0x3f8, 0x8, 0x8) - IRQNoFlags() { 4 } - }) - } - } - - /* UART 2 */ - Device (URT2) - { - Name (_HID, EisaId ("PNP0501")) // "PNP0501" for UART - Name(_PRW, Package () {0x03, 0x04}) // Wake from S1-S4 - Method (_STA, 0, NotSerialized) - { - Return (0x0f) // Always enable - } - Name (_PRS, ResourceTemplate() { - StartDependentFn(0, 1) { - IO(Decode16, 0x2f8, 0x2f8, 0x8, 0x8) - IRQNoFlags() { 3 } - } EndDependentFn() - }) - Method (_CRS, 0) - { - Return(ResourceTemplate() { - IO(Decode16, 0x2f8, 0x2f8, 0x8, 0x8) - IRQNoFlags() { 3 } - }) - } - } - } - - /* High Precision Event Timer */ - Device (HPET) - { - Name (_HID, EisaId ("PNP0103")) - Name (CRS, ResourceTemplate () - { - Memory32Fixed(ReadOnly, 0xFED00000, 0x00000400) - }) - Method (_STA, 0) - { - If(HPTE) { - Return (0x0F) - } - Return (0x0) - } - Method(_CRS, 0) - { - Return(CRS) - } - } - - /* 0:14.4 PCI Bridge */ - Device (PBR0) - { - Name (_ADR, 0x00140004) // _ADR: Address - Name(_PRW, Package () {0x11, 0x04}) // Wake from S1-S4 - Method (_PRT, 0, NotSerialized) // _PRT: PCI Routing Table - { - If (PICM) { - Return (AR01) - } Else { - Return (PR01) - } - } - Device (SLT1) - { - Name (_ADR, 0xFFFF) // _ADR: Address - Name(_PRW, Package () {0x0B, 0x04}) // Wake from S1-S4 - } - } - - /* 0:14.5 SP5100 USB 6 */ - Device (USB6) - { - Name (_ADR, 0x00140005) // _ADR: Address - Name(_PRW, Package () {0x05, 0x04}) // Wake from S1-S4 - } - - /* 2:00.0 PCIe x16 */ - Device (PCE1) - { - Name (_ADR, 0x00020000) // _ADR: Address - Name(_PRW, Package () {0x11, 0x04}) // Wake from S1-S4 - Method (_PRT, 0, NotSerialized) // _PRT: PCI Routing Table - { - If (PICM) { - Return (AR02) - } Else { - Return (PR02) - } - } - Device (SLT1) - { - Name (_ADR, 0xFFFF) // _ADR: Address - Name(_PRW, Package () {0x0B, 0x04}) // Wake from S1-S4 - } - } - - /* 1:00.0 PIKE */ - Device (PIKE) - { - Name (_ADR, 0x00040000) // _ADR: Address - Name(_PRW, Package () {0x11, 0x04}) // Wake from S1-S4 - Method (_PRT, 0, NotSerialized) // _PRT: PCI Routing Table - { - If (PICM) { - Return (AR03) - } Else { - Return (PR03) - } - } - Device (SLT1) - { - Name (_ADR, 0xFFFF) // _ADR: Address - Name(_PRW, Package () {0x0B, 0x04}) // Wake from S1-S4 - } - } - - /* 3:00.0 PCIe NIC A */ - Device (NICA) - { - Name (_ADR, 0x00090000) // _ADR: Address - Name(_PRW, Package () {0x11, 0x04}) // Wake from S1-S4 - Method (_PRT, 0, NotSerialized) // _PRT: PCI Routing Table - { - If (PICM) { - Return (AR04) - } Else { - Return (PR04) - } - } - Device (BDC1) - { - Name (_ADR, Zero) // _ADR: Address - } - } - - /* 4:00.0 PCIe NIC B */ - Device (NICB) - { - Name (_ADR, 0x000A0000) // _ADR: Address - Name(_PRW, Package () {0x11, 0x04}) // Wake from S1-S4 - Method (_PRT, 0, NotSerialized) // _PRT: PCI Routing Table - { - If (PICM) { - Return (AR05) - } Else { - Return (PR05) - } - } - Device (BDC2) - { - Name (_ADR, Zero) // _ADR: Address - } - } - - /* 5:00.0 PCIe x16 */ - Device (PCE4) - { - Name (_ADR, 0x000B0000) // _ADR: Address - Name(_PRW, Package () {0x11, 0x04}) // Wake from S1-S4 - Method (_PRT, 0, NotSerialized) // _PRT: PCI Routing Table - { - If (PICM) { - Return (AR06) - } Else { - Return (PR06) - } - } - Device (SLT1) - { - Name (_ADR, 0xFFFF) // _ADR: Address - Name(_PRW, Package () {0x0B, 0x04}) // Wake from S1-S4 - } - } - - /* 6:00.0 PCIe x16 */ - Device (PCE5) - { - Name (_ADR, 0x000C0000) // _ADR: Address - Name(_PRW, Package () {0x11, 0x04}) // Wake from S1-S4 - Method (_PRT, 0, NotSerialized) // _PRT: PCI Routing Table - { - If (PICM) { - Return (AR07) - } Else { - Return (PR07) - } - } - Device (SLT1) - { - Name (_ADR, 0xFFFF) // _ADR: Address - Name(_PRW, Package () {0x0B, 0x04}) // Wake from S1-S4 - } - } - - /* 7:00.0 PCIe x16 */ - Device (PCE3) - { - Name (_ADR, 0x000D0000) // _ADR: Address - Name(_PRW, Package () {0x11, 0x04}) // Wake from S1-S4 - Method (_PRT, 0, NotSerialized) // _PRT: PCI Routing Table - { - If (PICM) { - Return (AR08) - } Else { - Return (PR08) - } - } - Device (SLT1) - { - Name (_ADR, 0xFFFF) // _ADR: Address - Name(_PRW, Package () {0x0B, 0x04}) // Wake from S1-S4 - } - } - } - - Device (PWRB) { /* Start Power button device */ - Name(_HID, EISAID("PNP0C0C")) - Name(_UID, 0xAA) - Name(_PRW, Package () {3, 0x04}) /* wake from S1-S4 */ - Name(_STA, 0x0B) /* sata is invisible */ - } - } - -#include "acpi/pm_ctrl.asl" - -} diff --git a/src/mainboard/asus/kgpe-d16/get_bus_conf.c b/src/mainboard/asus/kgpe-d16/get_bus_conf.c deleted file mode 100644 index 81d0fc1b63..0000000000 --- a/src/mainboard/asus/kgpe-d16/get_bus_conf.c +++ /dev/null @@ -1,30 +0,0 @@ - /* - * This file is part of the coreboot project. - * - * Copyright (C) 2010 Advanced Micro Devices, Inc. - * Copyright (C) 2015 Timothy Pearson , Raptor Engineering - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include -#include -#include - -void get_bus_conf(void) -{ - get_default_pci1234(1); - - sysconf.sbdn = (sysconf.hcdn[0] & 0xff); - - pirq_router_bus = (sysconf.pci1234[0] >> 16) & 0xff; -} diff --git a/src/mainboard/asus/kgpe-d16/irq_tables.c b/src/mainboard/asus/kgpe-d16/irq_tables.c deleted file mode 100644 index 0819dee09e..0000000000 --- a/src/mainboard/asus/kgpe-d16/irq_tables.c +++ /dev/null @@ -1,122 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2010 Advanced Micro Devices, Inc. - * Copyright (C) 2015 Raptor Engineering - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include -#include -#include -#include - -#include - -/* Free irqs are 3, 4, 5, 6, 7, 9, 10, 11, 12, 14, and 15 */ -#define IRQBM ((1 << 3)|(1 << 4)|(1 << 5)|(1 << 6)|(1 << 7)|(1 << 9)|(1 << 10)|(1 << 11)|(1 << 12)|(1 << 14)|(1 << 15)) - -#define LNKA 1 -#define LNKB 2 -#define LNKC 3 -#define LNKD 4 - -/* - * For simplicity map LNK[E-H] to LNK[A-D]. - * This also means we are 82C596 compatible. - * Needs 0:11.0 0x46[4] set to 0. - */ -#define LNKE 1 -#define LNKF 2 -#define LNKG 3 -#define LNKH 4 - -static void write_pirq_info(struct irq_info *pirq_info, u8 bus, u8 devfn, - u8 link0, u16 bitmap0, u8 link1, u16 bitmap1, - u8 link2, u16 bitmap2, u8 link3, u16 bitmap3, - u8 slot, u8 rfu) -{ - pirq_info->bus = bus; - pirq_info->devfn = devfn; - pirq_info->irq[0].link = link0; - pirq_info->irq[0].bitmap = bitmap0; - pirq_info->irq[1].link = link1; - pirq_info->irq[1].bitmap = bitmap1; - pirq_info->irq[2].link = link2; - pirq_info->irq[2].bitmap = bitmap2; - pirq_info->irq[3].link = link3; - pirq_info->irq[3].bitmap = bitmap3; - pirq_info->slot = slot; - pirq_info->rfu = rfu; -} - -unsigned long write_pirq_routing_table(unsigned long addr) -{ - struct irq_routing_table *pirq; - struct irq_info *pirq_info; - u32 slot_num; - u8 *v; - - u8 sum = 0; - int i; - - /* Align the table to be 16 byte aligned. */ - addr += 15; - addr &= ~15; - - /* This table must be between 0xf0000 & 0x100000 */ - printk(BIOS_INFO, "Writing IRQ routing tables to 0x%lx...", addr); - - pirq = (void *)(addr); - v = (u8 *) (addr); - - pirq->signature = PIRQ_SIGNATURE; - pirq->version = PIRQ_VERSION; - - /* Where the interrupt router resides */ - pirq->rtr_bus = pirq_router_bus; - pirq->rtr_devfn = PCI_DEVFN(0x14, 4); - - pirq->exclusive_irqs = 0; - - pirq->rtr_vendor = PCI_VENDOR_ID_ATI; - pirq->rtr_device = PCI_DEVICE_ID_ATI_SB700_PCI; - - pirq->miniport_data = 0; - - memset(pirq->rfu, 0, sizeof(pirq->rfu)); - - pirq_info = (void *)(&pirq->checksum + 1); - slot_num = 0; - - /* pci bridge */ - write_pirq_info(pirq_info, pirq_router_bus, - PCI_DEVFN(0x14, 4), LNKA, IRQBM, LNKB, - IRQBM, LNKC, IRQBM, LNKD, IRQBM, 0, 0); - pirq_info++; - slot_num++; - - pirq->size = 32 + 16 * slot_num; - - for (i = 0; i < pirq->size; i++) - sum += v[i]; - - sum = pirq->checksum - sum; - if (sum != pirq->checksum) { - pirq->checksum = sum; - } - - printk(BIOS_INFO, "done.\n"); - - return (unsigned long)pirq_info; -} diff --git a/src/mainboard/asus/kgpe-d16/mainboard.c b/src/mainboard/asus/kgpe-d16/mainboard.c deleted file mode 100644 index a03953be77..0000000000 --- a/src/mainboard/asus/kgpe-d16/mainboard.c +++ /dev/null @@ -1,114 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2015 Timothy Pearson , Raptor Engineering - * Copyright (C) 2010 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -void set_pcie_reset(void) -{ - struct device *pcie_core_dev; - - pcie_core_dev = pcidev_on_root(0, 0); - set_htiu_enable_bits(pcie_core_dev, 0xA8, 0xFFFFFFFF, 0x28282828); - set_htiu_enable_bits(pcie_core_dev, 0xA9, 0x000000FF, 0x00000028); -} - -void set_pcie_dereset(void) -{ - struct device *pcie_core_dev; - - pcie_core_dev = pcidev_on_root(0, 0); - set_htiu_enable_bits(pcie_core_dev, 0xA8, 0xFFFFFFFF, 0x6F6F6F6F); - set_htiu_enable_bits(pcie_core_dev, 0xA9, 0x000000FF, 0x0000006F); -} - -/************************************************* -* enable the dedicated function in kgpe-d16 board. -* This function is called earlier than sr5650_enable. -*************************************************/ - -static void mainboard_enable(struct device *dev) -{ - printk(BIOS_INFO, "Mainboard KGPE-D16 Enable. dev=0x%p\n", dev); - - msr_t msr, msr2; - - /* TOP_MEM: the top of DRAM below 4G */ - msr = rdmsr(TOP_MEM); - printk - (BIOS_INFO, "%s, TOP MEM: msr.lo = 0x%08x, msr.hi = 0x%08x\n", - __func__, msr.lo, msr.hi); - - /* TOP_MEM2: the top of DRAM above 4G */ - msr2 = rdmsr(TOP_MEM2); - printk - (BIOS_INFO, "%s, TOP MEM2: msr2.lo = 0x%08x, msr2.hi = 0x%08x\n", - __func__, msr2.lo, msr2.hi); - - set_pcie_dereset(); - /* get_ide_dma66(); */ -} - -/* override the default SATA PHY setup */ -void sb7xx_51xx_setup_sata_phys(struct device *dev) -{ - /* RPR7.6.1 Program the PHY Global Control to 0x2C00 */ - pci_write_config16(dev, 0x86, 0x2c00); - - /* RPR7.6.2 SATA GENI PHY ports setting */ - pci_write_config32(dev, 0x88, 0x01b48016); - pci_write_config32(dev, 0x8c, 0x01b48016); - pci_write_config32(dev, 0x90, 0x01b48016); - pci_write_config32(dev, 0x94, 0x01b48016); - pci_write_config32(dev, 0x98, 0x01b48016); - pci_write_config32(dev, 0x9c, 0x01b48016); - - /* RPR7.6.3 SATA GEN II PHY port setting for port [0~5]. */ - pci_write_config16(dev, 0xa0, 0xa07a); - pci_write_config16(dev, 0xa2, 0xa07a); - pci_write_config16(dev, 0xa4, 0xa07a); - pci_write_config16(dev, 0xa6, 0xa07a); - pci_write_config16(dev, 0xa8, 0xa07a); - pci_write_config16(dev, 0xaa, 0xa07a); -} - -/* override the default SATA port setup */ -void sb7xx_51xx_setup_sata_port_indication(void *sata_bar5) -{ - uint32_t dword; - - /* RPR7.9 Program Port Indication Registers */ - dword = read32(sata_bar5 + 0xf8); - dword &= ~(0x3f << 12); /* All ports are iSATA */ - dword &= ~0x3f; - write32(sata_bar5 + 0xf8, dword); - - dword = read32(sata_bar5 + 0xfc); - dword &= ~(0x1 << 20); /* No eSATA ports are present */ - write32(sata_bar5 + 0xfc, dword); -} - -struct chip_operations mainboard_ops = { - .enable_dev = mainboard_enable, -}; diff --git a/src/mainboard/asus/kgpe-d16/mptable.c b/src/mainboard/asus/kgpe-d16/mptable.c deleted file mode 100644 index 6d7174da38..0000000000 --- a/src/mainboard/asus/kgpe-d16/mptable.c +++ /dev/null @@ -1,219 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2010 Advanced Micro Devices, Inc. - * Copyright (C) 2015 Raptor Engineering - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include -#include -#include - -static void *smp_write_config_table(void *v) -{ - struct mp_config_table *mc; - int bus_isa; - u32 apicid_sp5100; - u32 apicid_sr5650; - struct device *dev; - uint8_t sp5100_bus_number; - - mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); - - mptable_init(mc, LOCAL_APIC_ADDR); - - smp_write_processors(mc); - - if (CONFIG(ENABLE_APIC_EXT_ID) && (CONFIG_APIC_ID_OFFSET > 0)) - apicid_sp5100 = 0x0; - else - apicid_sp5100 = 0x20; - apicid_sr5650 = apicid_sp5100 + 1; - - mptable_write_buses(mc, NULL, &bus_isa); - /* I/O APICs: APIC ID Version State Address */ - { - uint32_t *dword_ptr; - uint32_t dword; - uint16_t word; - uint8_t byte; - - sp5100_bus_number = 0; //bus_sp5100[0]; TODO: why bus_sp5100[0] use same value of bus_sr5650[0] assigned by get_pci1234(), instead of 0. - - dev = dev_find_slot(sp5100_bus_number, PCI_DEVFN(0x14, 0)); - if (dev) { - dword_ptr = (u32 *)(pci_read_config32(dev, 0x74) & 0xfffffff0); - smp_write_ioapic(mc, apicid_sp5100, 0x11, dword_ptr); - - /* Initialize interrupt mapping */ - /* USB 1 & 2 */ - word = pci_read_config16(dev, 0xbe); - word &= ~0x3f3f; - word |= 0x0; /* 0: INTA, ...., 7: INTH */ - word |= (0x1 << 3); /* 0: INTA, ...., 7: INTH */ - word |= (0x2 << 8); /* 0: INTA, ...., 7: INTH */ - word |= (0x3 << 11); /* 0: INTA, ...., 7: INTH */ - pci_write_config16(dev, 0xbe, word); - - /* USB 3 */ - byte = pci_read_config8(dev, 0x63); - byte &= 0xf8; - byte |= (0x2 << 4); /* 0: INTA, ...., 7: INTH */ - pci_write_config8(dev, 0x63, byte); - - dword = pci_read_config32(dev, 0xac); - - /* SATA */ - dword &= ~(7 << 26); - dword |= (0x6 << 26); /* 0: INTA, ...., 7: INTH */ - - /* Hide IDE */ - dword &= ~(0x00080000); - - /* dword_ptr |= 1 << 22; PIC and APIC co exists */ - pci_write_config32(dev, 0xac, dword); - - /* - * 00:12.0: PROG SATA : INT F - * 00:13.0: INTA USB_0 - * 00:13.1: INTB USB_1 - * 00:13.2: INTC USB_2 - * 00:13.3: INTD USB_3 - * 00:13.4: INTC USB_4 - * 00:13.5: INTD USB2 - * 00:14.1: INTA IDE - * 00:14.2: Prog HDA : INT E - * 00:14.5: INTB ACI - * 00:14.6: INTB MCI - */ - } - dev = pcidev_on_root(0, 0); - if (dev) { - pci_write_config32(dev, 0xF8, 0x1); - dword_ptr = (u32 *)(pci_read_config32(dev, 0xFC) & 0xfffffff0); - smp_write_ioapic(mc, apicid_sr5650, 0x11, dword_ptr); - } - } - - /* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ -#define IO_LOCAL_INT(type, intr, apicid, pin) \ - smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin)); - - mptable_add_isa_interrupts(mc, bus_isa, apicid_sp5100, 0); - - /* SR5650 devices */ - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0, (((0)<<2)|(2)), apicid_sr5650, 31); /* Device 0 Function 2 (LNKA, APIC pin 31) */ - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0, (((2)<<2)|(0)), apicid_sr5650, 28); /* Device 2 (LNKE, APIC pin 28) */ - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0, (((4)<<2)|(0)), apicid_sr5650, 28); /* Device 4 (LNKF, APIC pin 28) */ - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0, (((9)<<2)|(0)), apicid_sr5650, 29); /* Device 9 (LNKG, APIC pin 29) */ - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0, (((10)<<2)|(0)), apicid_sr5650, 30); /* Device 10 (LNKG, APIC pin 30) */ - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0, (((11)<<2)|(0)), apicid_sr5650, 30); /* Device 11 (LNKG, APIC pin 30) */ - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0, (((12)<<2)|(0)), apicid_sr5650, 30); /* Device 12 (LNKG, APIC pin 30) */ - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0, (((13)<<2)|(0)), apicid_sr5650, 30); /* Device 13 (LNKG, APIC pin 30)) */ - - dev = pcidev_on_root(0x2, 0); - if (dev && dev->enabled) { - uint8_t bus_pci = dev->link_list->secondary; - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_pci, (((0)<<0x2)|(0)), apicid_sr5650, 0); /* card behind dev2 */ - } - dev = pcidev_on_root(0x4, 0); - if (dev && dev->enabled) { - uint8_t bus_pci = dev->link_list->secondary; - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_pci, (((0)<<0x4)|(0)), apicid_sr5650, 0); /* PIKE */ - } - dev = pcidev_on_root(0x9, 0); - if (dev && dev->enabled) { - uint8_t bus_pci = dev->link_list->secondary; - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_pci, (((0)<<0x9)|(0)), apicid_sr5650, 23); /* NIC A */ - } - dev = pcidev_on_root(0xa, 0); - if (dev && dev->enabled) { - uint8_t bus_pci = dev->link_list->secondary; - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_pci, (((0)<<0xa)|(0)), apicid_sr5650, 24); /* NIC B */ - } - dev = pcidev_on_root(0xb, 0); - if (dev && dev->enabled) { - uint8_t bus_pci = dev->link_list->secondary; - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_pci, (((0)<<0xb)|(0)), apicid_sr5650, 0); /* card behind dev11 */ - } - dev = pcidev_on_root(0xc, 0); - if (dev && dev->enabled) { - uint8_t bus_pci = dev->link_list->secondary; - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_pci, (((0)<<0xc)|(0)), apicid_sr5650, 0); /* card behind dev12 */ - } - dev = pcidev_on_root(0xd, 0); - if (dev && dev->enabled) { - uint8_t bus_pci = dev->link_list->secondary; - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_pci, (((0)<<0xd)|(0)), apicid_sr5650, 0); /* card behind dev13 */ - } - - /* PCI interrupts are level triggered, and are - * associated with a specific bus/device/function tuple. - */ -#define PCI_INT(bus, dev, interrupt_signal, pin) \ - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(interrupt_signal)), apicid_sp5100, (pin)) - - /* USB1 */ - PCI_INT(sp5100_bus_number, 0x12, 0x0, 0x10); /* OHCI0 Port 0~2 */ - PCI_INT(sp5100_bus_number, 0x12, 0x1, 0x11); /* OHCI1 Port 3~5 */ - - /* USB2 */ - PCI_INT(sp5100_bus_number, 0x13, 0x0, 0x12); /* OHCI0 Port 6~8 */ - PCI_INT(sp5100_bus_number, 0x13, 0x1, 0x13); /* EHCI Port 6~11 */ - - /* USB3 */ - PCI_INT(sp5100_bus_number, 0x14, 0x3, 0x12); /* OHCI0 Port 12~13 */ - - /* SATA */ - PCI_INT(sp5100_bus_number, 0x11, 0x0, 0x16); /* 6, INTG */ - - /* PCI slots */ - dev = pcidev_on_root(0x14, 4); - if (dev && dev->enabled) { - u8 bus_pci = dev->link_list->secondary; - - /* PCI_SLOT 0. */ - PCI_INT(bus_pci, 0x1, 0x0, 0x15); - PCI_INT(bus_pci, 0x1, 0x1, 0x16); - PCI_INT(bus_pci, 0x1, 0x2, 0x17); - PCI_INT(bus_pci, 0x1, 0x3, 0x14); - - /* PCI_SLOT 1. */ - PCI_INT(bus_pci, 0x2, 0x0, 0x14); - PCI_INT(bus_pci, 0x2, 0x1, 0x15); - PCI_INT(bus_pci, 0x2, 0x2, 0x16); - PCI_INT(bus_pci, 0x2, 0x3, 0x17); - - /* PCI_SLOT 2. */ - PCI_INT(bus_pci, 0x3, 0x0, 0x16); - PCI_INT(bus_pci, 0x3, 0x1, 0x17); - PCI_INT(bus_pci, 0x3, 0x2, 0x14); - PCI_INT(bus_pci, 0x3, 0x3, 0x15); - } - - /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ - IO_LOCAL_INT(mp_ExtINT, 0x0, MP_APIC_ALL, 0x0); - IO_LOCAL_INT(mp_NMI, 0x0, MP_APIC_ALL, 0x1); - /* There is no extension information... */ - - /* Compute the checksums */ - return mptable_finalize(mc); -} - -unsigned long write_smp_table(unsigned long addr) -{ - void *v; - v = smp_write_floating_table(addr, 0); - return (unsigned long)smp_write_config_table(v); -} diff --git a/src/mainboard/asus/kgpe-d16/resourcemap.c b/src/mainboard/asus/kgpe-d16/resourcemap.c deleted file mode 100644 index ce9add3ae1..0000000000 --- a/src/mainboard/asus/kgpe-d16/resourcemap.c +++ /dev/null @@ -1,553 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2015 Timothy Pearson , Raptor Engineering - * - * Copyright (C) 2007 AMD - * Written by Yinghai Lu for AMD. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include - -void setup_mb_resource_map(void) -{ - static const unsigned int fam15h_register_values[] = { - /* Careful set limit registers before base registers which contain the enables */ - /* DRAM Limit i Registers - * F1:0x44 i = 0 - * F1:0x4C i = 1 - * F1:0x54 i = 2 - * F1:0x5C i = 3 - * F1:0x64 i = 4 - * F1:0x6C i = 5 - * F1:0x74 i = 6 - * F1:0x7C i = 7 - * [ 2: 0] Destination Node ID - * 000 = Node 0 - * 001 = Node 1 - * 010 = Node 2 - * 011 = Node 3 - * 100 = Node 4 - * 101 = Node 5 - * 110 = Node 6 - * 111 = Node 7 - * [ 7: 3] Reserved - * [10: 8] Interleave select - * specifies the values of A[14:12] to use with interleave enable. - * [15:11] Reserved - * [31:16] DRAM Limit Address i Bits 39-24 - * This field defines the upper address bits of a 40 bit address - * that define the end of the DRAM region. - */ - // ADDRMAP_REG(0x44), 0x0000f8f8, 0x00000000, - ADDRMAP_REG(0x4C), 0x0000f8f8, 0x00000001, - ADDRMAP_REG(0x54), 0x0000f8f8, 0x00000002, - ADDRMAP_REG(0x5C), 0x0000f8f8, 0x00000003, - ADDRMAP_REG(0x64), 0x0000f8f8, 0x00000004, - ADDRMAP_REG(0x6C), 0x0000f8f8, 0x00000005, - ADDRMAP_REG(0x74), 0x0000f8f8, 0x00000006, - ADDRMAP_REG(0x7C), 0x0000f8f8, 0x00000007, - - /* DRAM Base i Registers - * F1:0x40 i = 0 - * F1:0x48 i = 1 - * F1:0x50 i = 2 - * F1:0x58 i = 3 - * F1:0x60 i = 4 - * F1:0x68 i = 5 - * F1:0x70 i = 6 - * F1:0x78 i = 7 - * [ 0: 0] Read Enable - * 0 = Reads Disabled - * 1 = Reads Enabled - * [ 1: 1] Write Enable - * 0 = Writes Disabled - * 1 = Writes Enabled - * [ 7: 2] Reserved - * [10: 8] Interleave Enable - * 000 = No interleave - * 001 = Interleave on A[12] (2 nodes) - * 010 = reserved - * 011 = Interleave on A[12] and A[14] (4 nodes) - * 100 = reserved - * 101 = reserved - * 110 = reserved - * 111 = Interleve on A[12] and A[13] and A[14] (8 nodes) - * [15:11] Reserved - * [31:16] DRAM Base Address i Bits 39-24 - * This field defines the upper address bits of a 40-bit address - * that define the start of the DRAM region. - */ - // ADDRMAP_REG(0x40), 0x0000f8fc, 0x00000000, - ADDRMAP_REG(0x48), 0x0000f8fc, 0x00000000, - ADDRMAP_REG(0x50), 0x0000f8fc, 0x00000000, - ADDRMAP_REG(0x58), 0x0000f8fc, 0x00000000, - ADDRMAP_REG(0x60), 0x0000f8fc, 0x00000000, - ADDRMAP_REG(0x68), 0x0000f8fc, 0x00000000, - ADDRMAP_REG(0x70), 0x0000f8fc, 0x00000000, - ADDRMAP_REG(0x78), 0x0000f8fc, 0x00000000, - - /* Memory-Mapped I/O Limit i Registers - * F1:0x84 i = 0 - * F1:0x8C i = 1 - * F1:0x94 i = 2 - * F1:0x9C i = 3 - * F1:0xA4 i = 4 - * F1:0xAC i = 5 - * F1:0xB4 i = 6 - * F1:0xBC i = 7 - * [ 2: 0] Destination Node ID - * 000 = Node 0 - * 001 = Node 1 - * 010 = Node 2 - * 011 = Node 3 - * 100 = Node 4 - * 101 = Node 5 - * 110 = Node 6 - * 111 = Node 7 - * [ 3: 3] Reserved - * [ 5: 4] Destination Link ID - * 00 = Link 0 - * 01 = Link 1 - * 10 = Link 2 - * 11 = Link 3 - * [ 6: 6] Reserved - * [ 7: 7] Non-Posted - * 0 = CPU writes may be posted - * 1 = CPU writes must be non-posted - * [31: 8] Memory-Mapped I/O Limit Address i (39-16) - * This field defines the upp address bits of a 40-bit address that - * defines the end of a memory-mapped I/O region n - */ - ADDRMAP_REG(0x84), 0x00000048, 0x00000000, - ADDRMAP_REG(0x8C), 0x00000048, 0x00000000, - ADDRMAP_REG(0x94), 0x00000048, 0x00000000, - ADDRMAP_REG(0x9C), 0x00000048, 0x00000000, - ADDRMAP_REG(0xA4), 0x00000048, 0x00000000, - ADDRMAP_REG(0xAC), 0x00000048, 0x00000000, - ADDRMAP_REG(0xB4), 0x00000048, 0x00000000, - ADDRMAP_REG(0xBC), 0x00000048, 0x00000000, - - /* Memory-Mapped I/O Base i Registers - * F1:0x80 i = 0 - * F1:0x88 i = 1 - * F1:0x90 i = 2 - * F1:0x98 i = 3 - * F1:0xA0 i = 4 - * F1:0xA8 i = 5 - * F1:0xB0 i = 6 - * F1:0xB8 i = 7 - * [ 0: 0] Read Enable - * 0 = Reads disabled - * 1 = Reads Enabled - * [ 1: 1] Write Enable - * 0 = Writes disabled - * 1 = Writes Enabled - * [ 2: 2] Cpu Disable - * 0 = Cpu can use this I/O range - * 1 = Cpu requests do not use this I/O range - * [ 3: 3] Lock - * 0 = base/limit registers i are read/write - * 1 = base/limit registers i are read-only - * [ 7: 4] Reserved - * [31: 8] Memory-Mapped I/O Base Address i (39-16) - * This field defines the upper address bits of a 40bit address - * that defines the start of memory-mapped I/O region i - */ - ADDRMAP_REG(0x80), 0x000000f0, 0x00000000, - ADDRMAP_REG(0x88), 0x000000f0, 0x00000000, - ADDRMAP_REG(0x90), 0x000000f0, 0x00000000, - ADDRMAP_REG(0x98), 0x000000f0, 0x00000000, - ADDRMAP_REG(0xA0), 0x000000f0, 0x00000000, - ADDRMAP_REG(0xA8), 0x000000f0, 0x00000000, - ADDRMAP_REG(0xB0), 0x000000f0, 0x00000000, - ADDRMAP_REG(0xB8), 0x000000f0, 0x00000000, - - /* PCI I/O Limit i Registers - * F1:0xC4 i = 0 - * F1:0xCC i = 1 - * F1:0xD4 i = 2 - * F1:0xDC i = 3 - * [ 2: 0] Destination Node ID - * 000 = Node 0 - * 001 = Node 1 - * 010 = Node 2 - * 011 = Node 3 - * 100 = Node 4 - * 101 = Node 5 - * 110 = Node 6 - * 111 = Node 7 - * [ 3: 3] Reserved - * [ 5: 4] Destination Link ID - * 00 = Link 0 - * 01 = Link 1 - * 10 = Link 2 - * 11 = Link 3 - * [11: 6] Reserved - * [24:12] PCI I/O Limit Address i - * This field defines the end of PCI I/O region n - * [31:25] Reserved - */ - ADDRMAP_REG(0xC4), 0xFE000FC8, 0x00fff010, /* link 1 of CPU 0 --> AMD SR5690 */ - ADDRMAP_REG(0xCC), 0xFE000FC8, 0x00000000, - ADDRMAP_REG(0xD4), 0xFE000FC8, 0x00000000, - ADDRMAP_REG(0xDC), 0xFE000FC8, 0x00000000, - - /* PCI I/O Base i Registers - * F1:0xC0 i = 0 - * F1:0xC8 i = 1 - * F1:0xD0 i = 2 - * F1:0xD8 i = 3 - * [ 0: 0] Read Enable - * 0 = Reads Disabled - * 1 = Reads Enabled - * [ 1: 1] Write Enable - * 0 = Writes Disabled - * 1 = Writes Enabled - * [ 3: 2] Reserved - * [ 4: 4] VGA Enable - * 0 = VGA matches Disabled - * 1 = matches all address < 64K and where A[9:0] is in the - * range 3B0-3BB or 3C0-3DF independent of the base & limit registers - * [ 5: 5] ISA Enable - * 0 = ISA matches Disabled - * 1 = Blocks address < 64K and in the last 768 bytes of eack 1K block - * from matching agains this base/limit pair - * [11: 6] Reserved - * [24:12] PCI I/O Base i - * This field defines the start of PCI I/O region n - * [31:25] Reserved - */ -// ADDRMAP_REG(0xC0), 0xFE000FCC, 0x00001013, - ADDRMAP_REG(0xC8), 0xFE000FCC, 0x00000000, - ADDRMAP_REG(0xD0), 0xFE000FCC, 0x00000000, - ADDRMAP_REG(0xD8), 0xFE000FCC, 0x00000000, - - /* Config Base and Limit i Registers - * F1:0xE0 i = 0 - * F1:0xE4 i = 1 - * F1:0xE8 i = 2 - * F1:0xEC i = 3 - * [ 0: 0] Read Enable - * 0 = Reads Disabled - * 1 = Reads Enabled - * [ 1: 1] Write Enable - * 0 = Writes Disabled - * 1 = Writes Enabled - * [ 2: 2] Device Number Compare Enable - * 0 = The ranges are based on bus number - * 1 = The ranges are ranges of devices on bus 0 - * [ 3: 3] Reserved - * [ 6: 4] Destination Node - * 000 = Node 0 - * 001 = Node 1 - * 010 = Node 2 - * 011 = Node 3 - * 100 = Node 4 - * 101 = Node 5 - * 110 = Node 6 - * 111 = Node 7 - * [ 7: 7] Reserved - * [ 9: 8] Destination Link - * 00 = Link 0 - * 01 = Link 1 - * 10 = Link 2 - * 11 - Link 3 - * [15:10] Reserved - * [23:16] Bus Number Base i - * This field defines the lowest bus number in configuration region i - * [31:24] Bus Number Limit i - * This field defines the highest bus number in configuration region i - */ - ADDRMAP_REG(0xE0), 0x0000FC88, 0x05000103, /* link 1 of CPU 0 --> AMD SR5690 */ - ADDRMAP_REG(0xE4), 0x0000FC88, 0x00000000, - ADDRMAP_REG(0xE8), 0x0000FC88, 0x00000000, - ADDRMAP_REG(0xEC), 0x0000FC88, 0x00000000, - - }; - - static const unsigned int fam10h_register_values[] = { - /* Careful set limit registers before base registers which contain the enables */ - /* DRAM Limit i Registers - * F1:0x44 i = 0 - * F1:0x4C i = 1 - * F1:0x54 i = 2 - * F1:0x5C i = 3 - * F1:0x64 i = 4 - * F1:0x6C i = 5 - * F1:0x74 i = 6 - * F1:0x7C i = 7 - * [ 2: 0] Destination Node ID - * 000 = Node 0 - * 001 = Node 1 - * 010 = Node 2 - * 011 = Node 3 - * 100 = Node 4 - * 101 = Node 5 - * 110 = Node 6 - * 111 = Node 7 - * [ 7: 3] Reserved - * [10: 8] Interleave select - * specifies the values of A[14:12] to use with interleave enable. - * [15:11] Reserved - * [31:16] DRAM Limit Address i Bits 39-24 - * This field defines the upper address bits of a 40 bit address - * that define the end of the DRAM region. - */ - // ADDRMAP_REG(0x44), 0x0000f8f8, 0x00000000, - ADDRMAP_REG(0x4C), 0x0000f8f8, 0x00000001, - ADDRMAP_REG(0x54), 0x0000f8f8, 0x00000002, - ADDRMAP_REG(0x5C), 0x0000f8f8, 0x00000003, - ADDRMAP_REG(0x64), 0x0000f8f8, 0x00000004, - ADDRMAP_REG(0x6C), 0x0000f8f8, 0x00000005, - ADDRMAP_REG(0x74), 0x0000f8f8, 0x00000006, - ADDRMAP_REG(0x7C), 0x0000f8f8, 0x00000007, - - /* DRAM Base i Registers - * F1:0x40 i = 0 - * F1:0x48 i = 1 - * F1:0x50 i = 2 - * F1:0x58 i = 3 - * F1:0x60 i = 4 - * F1:0x68 i = 5 - * F1:0x70 i = 6 - * F1:0x78 i = 7 - * [ 0: 0] Read Enable - * 0 = Reads Disabled - * 1 = Reads Enabled - * [ 1: 1] Write Enable - * 0 = Writes Disabled - * 1 = Writes Enabled - * [ 7: 2] Reserved - * [10: 8] Interleave Enable - * 000 = No interleave - * 001 = Interleave on A[12] (2 nodes) - * 010 = reserved - * 011 = Interleave on A[12] and A[14] (4 nodes) - * 100 = reserved - * 101 = reserved - * 110 = reserved - * 111 = Interleve on A[12] and A[13] and A[14] (8 nodes) - * [15:11] Reserved - * [31:16] DRAM Base Address i Bits 39-24 - * This field defines the upper address bits of a 40-bit address - * that define the start of the DRAM region. - */ - // ADDRMAP_REG(0x40), 0x0000f8fc, 0x00000000, - ADDRMAP_REG(0x48), 0x0000f8fc, 0x00000000, - ADDRMAP_REG(0x50), 0x0000f8fc, 0x00000000, - ADDRMAP_REG(0x58), 0x0000f8fc, 0x00000000, - ADDRMAP_REG(0x60), 0x0000f8fc, 0x00000000, - ADDRMAP_REG(0x68), 0x0000f8fc, 0x00000000, - ADDRMAP_REG(0x70), 0x0000f8fc, 0x00000000, - ADDRMAP_REG(0x78), 0x0000f8fc, 0x00000000, - - /* Memory-Mapped I/O Limit i Registers - * F1:0x84 i = 0 - * F1:0x8C i = 1 - * F1:0x94 i = 2 - * F1:0x9C i = 3 - * F1:0xA4 i = 4 - * F1:0xAC i = 5 - * F1:0xB4 i = 6 - * F1:0xBC i = 7 - * [ 2: 0] Destination Node ID - * 000 = Node 0 - * 001 = Node 1 - * 010 = Node 2 - * 011 = Node 3 - * 100 = Node 4 - * 101 = Node 5 - * 110 = Node 6 - * 111 = Node 7 - * [ 3: 3] Reserved - * [ 5: 4] Destination Link ID - * 00 = Link 0 - * 01 = Link 1 - * 10 = Link 2 - * 11 = Link 3 - * [ 6: 6] Reserved - * [ 7: 7] Non-Posted - * 0 = CPU writes may be posted - * 1 = CPU writes must be non-posted - * [31: 8] Memory-Mapped I/O Limit Address i (39-16) - * This field defines the upp address bits of a 40-bit address that - * defines the end of a memory-mapped I/O region n - */ - ADDRMAP_REG(0x84), 0x00000048, 0x00000000, - ADDRMAP_REG(0x8C), 0x00000048, 0x00000000, - ADDRMAP_REG(0x94), 0x00000048, 0x00000000, - ADDRMAP_REG(0x9C), 0x00000048, 0x00000000, - ADDRMAP_REG(0xA4), 0x00000048, 0x00000000, - ADDRMAP_REG(0xAC), 0x00000048, 0x00000000, - ADDRMAP_REG(0xB4), 0x00000048, 0x00000000, - ADDRMAP_REG(0xBC), 0x00000048, 0x00000000, - - /* Memory-Mapped I/O Base i Registers - * F1:0x80 i = 0 - * F1:0x88 i = 1 - * F1:0x90 i = 2 - * F1:0x98 i = 3 - * F1:0xA0 i = 4 - * F1:0xA8 i = 5 - * F1:0xB0 i = 6 - * F1:0xB8 i = 7 - * [ 0: 0] Read Enable - * 0 = Reads disabled - * 1 = Reads Enabled - * [ 1: 1] Write Enable - * 0 = Writes disabled - * 1 = Writes Enabled - * [ 2: 2] Cpu Disable - * 0 = Cpu can use this I/O range - * 1 = Cpu requests do not use this I/O range - * [ 3: 3] Lock - * 0 = base/limit registers i are read/write - * 1 = base/limit registers i are read-only - * [ 7: 4] Reserved - * [31: 8] Memory-Mapped I/O Base Address i (39-16) - * This field defines the upper address bits of a 40bit address - * that defines the start of memory-mapped I/O region i - */ - ADDRMAP_REG(0x80), 0x000000f0, 0x00000000, - ADDRMAP_REG(0x88), 0x000000f0, 0x00000000, - ADDRMAP_REG(0x90), 0x000000f0, 0x00000000, - ADDRMAP_REG(0x98), 0x000000f0, 0x00000000, - ADDRMAP_REG(0xA0), 0x000000f0, 0x00000000, - ADDRMAP_REG(0xA8), 0x000000f0, 0x00000000, - ADDRMAP_REG(0xB0), 0x000000f0, 0x00000000, - ADDRMAP_REG(0xB8), 0x000000f0, 0x00000000, - - /* PCI I/O Limit i Registers - * F1:0xC4 i = 0 - * F1:0xCC i = 1 - * F1:0xD4 i = 2 - * F1:0xDC i = 3 - * [ 2: 0] Destination Node ID - * 000 = Node 0 - * 001 = Node 1 - * 010 = Node 2 - * 011 = Node 3 - * 100 = Node 4 - * 101 = Node 5 - * 110 = Node 6 - * 111 = Node 7 - * [ 3: 3] Reserved - * [ 5: 4] Destination Link ID - * 00 = Link 0 - * 01 = Link 1 - * 10 = Link 2 - * 11 = Link 3 - * [11: 6] Reserved - * [24:12] PCI I/O Limit Address i - * This field defines the end of PCI I/O region n - * [31:25] Reserved - */ - ADDRMAP_REG(0xC4), 0xFE000FC8, 0x00fff110, /* link 3 of CPU 0 --> AMD SR5690 */ - ADDRMAP_REG(0xCC), 0xFE000FC8, 0x00000000, - ADDRMAP_REG(0xD4), 0xFE000FC8, 0x00000000, - ADDRMAP_REG(0xDC), 0xFE000FC8, 0x00000000, - - /* PCI I/O Base i Registers - * F1:0xC0 i = 0 - * F1:0xC8 i = 1 - * F1:0xD0 i = 2 - * F1:0xD8 i = 3 - * [ 0: 0] Read Enable - * 0 = Reads Disabled - * 1 = Reads Enabled - * [ 1: 1] Write Enable - * 0 = Writes Disabled - * 1 = Writes Enabled - * [ 3: 2] Reserved - * [ 4: 4] VGA Enable - * 0 = VGA matches Disabled - * 1 = matches all address < 64K and where A[9:0] is in the - * range 3B0-3BB or 3C0-3DF independent of the base & limit registers - * [ 5: 5] ISA Enable - * 0 = ISA matches Disabled - * 1 = Blocks address < 64K and in the last 768 bytes of eack 1K block - * from matching agains this base/limit pair - * [11: 6] Reserved - * [24:12] PCI I/O Base i - * This field defines the start of PCI I/O region n - * [31:25] Reserved - */ -// ADDRMAP_REG(0xC0), 0xFE000FCC, 0x00001013, - ADDRMAP_REG(0xC8), 0xFE000FCC, 0x00000000, - ADDRMAP_REG(0xD0), 0xFE000FCC, 0x00000000, - ADDRMAP_REG(0xD8), 0xFE000FCC, 0x00000000, - - /* Config Base and Limit i Registers - * F1:0xE0 i = 0 - * F1:0xE4 i = 1 - * F1:0xE8 i = 2 - * F1:0xEC i = 3 - * [ 0: 0] Read Enable - * 0 = Reads Disabled - * 1 = Reads Enabled - * [ 1: 1] Write Enable - * 0 = Writes Disabled - * 1 = Writes Enabled - * [ 2: 2] Device Number Compare Enable - * 0 = The ranges are based on bus number - * 1 = The ranges are ranges of devices on bus 0 - * [ 3: 3] Reserved - * [ 6: 4] Destination Node - * 000 = Node 0 - * 001 = Node 1 - * 010 = Node 2 - * 011 = Node 3 - * 100 = Node 4 - * 101 = Node 5 - * 110 = Node 6 - * 111 = Node 7 - * [ 7: 7] Reserved - * [ 9: 8] Destination Link - * 00 = Link 0 - * 01 = Link 1 - * 10 = Link 2 - * 11 - Link 3 - * [15:10] Reserved - * [23:16] Bus Number Base i - * This field defines the lowest bus number in configuration region i - * [31:24] Bus Number Limit i - * This field defines the highest bus number in configuration region i - */ - ADDRMAP_REG(0xE0), 0x0000FC88, 0x05000303, /* link 3 of CPU 0 --> AMD SR5690 */ - ADDRMAP_REG(0xE4), 0x0000FC88, 0x00000000, - ADDRMAP_REG(0xE8), 0x0000FC88, 0x00000000, - ADDRMAP_REG(0xEC), 0x0000FC88, 0x00000000, - - }; - - int max; - uint8_t fam15h = 0; - uint32_t family; - - family = cpuid_eax(0x80000001); - family = ((family & 0xf00000) >> 16) | ((family & 0xf00) >> 8); - - if (family >= 0x6f) - /* Family 15h or later */ - fam15h = 1; - - if (fam15h) { - max = ARRAY_SIZE(fam15h_register_values); - setup_resource_map(fam15h_register_values, max); - } else { - max = ARRAY_SIZE(fam10h_register_values); - setup_resource_map(fam10h_register_values, max); - } -} diff --git a/src/mainboard/asus/kgpe-d16/romstage.c b/src/mainboard/asus/kgpe-d16/romstage.c deleted file mode 100644 index 637ec42109..0000000000 --- a/src/mainboard/asus/kgpe-d16/romstage.c +++ /dev/null @@ -1,720 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2015 - 2017 Raptor Engineering, LLC - * - * Copyright (C) 2007 AMD - * Written by Yinghai Lu for AMD. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include "cpu/amd/quadcore/quadcore.c" - -#define SERIAL_0_DEV PNP_DEV(0x2e, W83667HG_A_SP1) -#define SERIAL_1_DEV PNP_DEV(0x2e, W83667HG_A_SP2) - -int spd_read_byte(unsigned int device, unsigned int address); - -int spd_read_byte(unsigned int device, unsigned int address) -{ - return do_smbus_read_byte(SMBUS_AUX_IO_BASE, device, address); -} - -/* - * ASUS KGPE-D16 specific SPD enable/disable magic. - * - * Setting SP5100 GPIOs 59 and 60 controls an SPI mux with four settings: - * 0: Disabled - * 1: Normal SPI access - * 2: CPU0 SPD - * 3: CPU1 SPD - * - * Disable SPD access after RAM init to allow access to standard SMBus/I2C offsets - * which is required e.g. by lm-sensors. - */ - -/* Relevant GPIO register information is available in the - * AMD SP5100 Register Reference Guide rev. 3.03, page 130 - */ -static void switch_spd_mux(uint8_t channel) -{ - uint8_t byte; - - byte = pci_read_config8(PCI_DEV(0, 0x14, 0), 0x54); - byte &= ~0xc; /* Clear SPD mux GPIOs */ - byte &= ~0xc0; /* Enable SPD mux GPIO output drivers */ - byte |= (channel << 2) & 0xc; /* Set SPD mux GPIOs */ - pci_write_config8(PCI_DEV(0, 0x14, 0), 0x54, byte); - - /* Temporary AST PCI mapping */ - const uint32_t memory_base = 0xfc000000; - const uint32_t memory_limit = 0xfc800000; - -#define TEMP_PCI_BUS 0x2 - /* Save S100 PCI bridge settings */ - uint16_t prev_sec_cfg = pci_read_config16(PCI_DEV(0, 0x14, 4), - PCI_COMMAND); - uint8_t prev_sec_bus = pci_read_config8(PCI_DEV(0, 0x14, 4), - PCI_SECONDARY_BUS); - uint8_t prev_sec_sub_bus = pci_read_config8(PCI_DEV(0, 0x14, 4), - PCI_SUBORDINATE_BUS); - uint16_t prev_sec_mem_base = pci_read_config16(PCI_DEV(0, 0x14, 4), - PCI_MEMORY_BASE); - uint16_t prev_sec_mem_limit = pci_read_config16(PCI_DEV(0, 0x14, 4), - PCI_MEMORY_LIMIT); - /* Temporarily enable the SP5100 PCI bridge */ - pci_write_config8(PCI_DEV(0, 0x14, 4), PCI_SECONDARY_BUS, TEMP_PCI_BUS); - pci_write_config8(PCI_DEV(0, 0x14, 4), PCI_SUBORDINATE_BUS, 0xff); - pci_write_config16(PCI_DEV(0, 0x14, 4), PCI_MEMORY_BASE, - (memory_base >> 20)); - pci_write_config16(PCI_DEV(0, 0x14, 4), PCI_MEMORY_LIMIT, - (memory_limit >> 20)); - pci_write_config16(PCI_DEV(0, 0x14, 4), PCI_COMMAND, - PCI_COMMAND_MEMORY); - - /* Temporarily enable AST BAR1 */ - uint16_t prev_ast_cmd = pci_read_config16(PCI_DEV(TEMP_PCI_BUS, 0x1, 0), - PCI_COMMAND); - uint16_t prev_ast_sts = pci_read_config16(PCI_DEV(TEMP_PCI_BUS, 0x1, 0), - PCI_STATUS); - uint32_t prev_ast_bar1 = pci_read_config32( - PCI_DEV(TEMP_PCI_BUS, 0x1, 0), PCI_BASE_ADDRESS_1); - pci_write_config32(PCI_DEV(TEMP_PCI_BUS, 0x1, 0), PCI_BASE_ADDRESS_1, - memory_base); - pci_write_config16(PCI_DEV(TEMP_PCI_BUS, 0x1, 0), PCI_COMMAND, - PCI_COMMAND_MEMORY); - pci_write_config16(PCI_DEV(TEMP_PCI_BUS, 0x1, 0), PCI_STATUS, - PCI_STATUS_CAP_LIST | PCI_STATUS_DEVSEL_MEDIUM); - - /* Use the P2A bridge to set ASpeed SPD mux GPIOs to the same values as the SP5100 */ - void* ast_bar1 = (void*)memory_base; - /* Enable access to GPIO controller */ - write32(ast_bar1 + 0xf004, 0x1e780000); - write32(ast_bar1 + 0xf000, 0x1); - /* Enable SPD mux GPIO output drivers */ - write32(ast_bar1 + 0x10024, read32(ast_bar1 + 0x10024) | 0x3000); - /* Set SPD mux GPIOs */ - write32(ast_bar1 + 0x10020, (read32(ast_bar1 + 0x10020) & ~0x3000) - | ((channel & 0x3) << 12)); - write32(ast_bar1 + 0xf000, 0x0); - - /* Deconfigure AST BAR1 */ - pci_write_config16(PCI_DEV(TEMP_PCI_BUS, 0x1, 0), PCI_COMMAND, - prev_ast_cmd); - pci_write_config16(PCI_DEV(TEMP_PCI_BUS, 0x1, 0), PCI_STATUS, - prev_ast_sts); - pci_write_config32(PCI_DEV(TEMP_PCI_BUS, 0x1, 0), PCI_BASE_ADDRESS_1, - prev_ast_bar1); - - /* Deconfigure SP5100 PCI bridge */ - pci_write_config16(PCI_DEV(0, 0x14, 4), PCI_COMMAND, prev_sec_cfg); - pci_write_config16(PCI_DEV(0, 0x14, 4), PCI_MEMORY_LIMIT, - prev_sec_mem_limit); - pci_write_config16(PCI_DEV(0, 0x14, 4), PCI_MEMORY_BASE, - prev_sec_mem_base); - pci_write_config8(PCI_DEV(0, 0x14, 4), PCI_SUBORDINATE_BUS, - prev_sec_sub_bus); - pci_write_config8(PCI_DEV(0, 0x14, 4), PCI_SECONDARY_BUS, prev_sec_bus); -} - -static const uint8_t spd_addr_fam15[] = { - // Socket 0 Node 0 ("Node 0") - RC00, DIMM0, DIMM1, 0, 0, DIMM2, DIMM3, 0, 0, - // Socket 0 Node 1 ("Node 1") - RC00, DIMM4, DIMM5, 0, 0, DIMM6, DIMM7, 0, 0, - // Socket 1 Node 0 ("Node 2") - RC01, DIMM0, DIMM1, 0, 0, DIMM2, DIMM3, 0, 0, - // Socket 1 Node 1 ("Node 3") - RC01, DIMM4, DIMM5, 0, 0, DIMM6, DIMM7, 0, 0, -}; - -static const uint8_t spd_addr_fam10[] = { - // Socket 0 Node 0 ("Node 0") - RC00, DIMM0, DIMM1, 0, 0, DIMM2, DIMM3, 0, 0, - // Socket 0 Node 1 ("Node 1") - RC00, DIMM4, DIMM5, 0, 0, DIMM6, DIMM7, 0, 0, - // Socket 1 Node 1 ("Node 2") - RC01, DIMM4, DIMM5, 0, 0, DIMM6, DIMM7, 0, 0, - // Socket 1 Node 0 ("Node 3") - RC01, DIMM0, DIMM1, 0, 0, DIMM2, DIMM3, 0, 0, -}; - -void activate_spd_rom(const struct mem_controller *ctrl) -{ - struct sys_info *sysinfo = get_sysinfo(); - printk(BIOS_DEBUG, "activate_spd_rom() for node %02x\n", ctrl->node_id); - if (ctrl->node_id == 0) { - printk(BIOS_DEBUG, "enable_spd_node0()\n"); - switch_spd_mux(0x2); - } else if (ctrl->node_id == 1) { - printk(BIOS_DEBUG, "enable_spd_node1()\n"); - switch_spd_mux((is_fam15h() || (sysinfo->nodes <= 2))?0x2:0x3); - } else if (ctrl->node_id == 2) { - printk(BIOS_DEBUG, "enable_spd_node2()\n"); - switch_spd_mux((is_fam15h() || (sysinfo->nodes <= 2))?0x3:0x2); - } else if (ctrl->node_id == 3) { - printk(BIOS_DEBUG, "enable_spd_node3()\n"); - switch_spd_mux(0x3); - } -} - -/* Voltages are specified by index - * Valid indices for this platform are: - * 0: 1.5V - * 1: 1.35V - * 2: 1.25V - * 3: 1.15V - */ -static void set_ddr3_voltage(uint8_t node, uint8_t index) { - uint8_t byte; - uint8_t value = 0; - - if (index == 0) - value = 0x0; - else if (index == 1) - value = 0x1; - else if (index == 2) - value = 0x4; - else if (index == 3) - value = 0x5; - if (node == 1) - value <<= 1; - - /* Set GPIOs */ - byte = pci_read_config8(PCI_DEV(0, 0x14, 3), 0xd1); - if (node == 0) - byte &= ~0x5; - if (node == 1) - byte &= ~0xa; - byte |= value; - pci_write_config8(PCI_DEV(0, 0x14, 3), 0xd1, byte); - - /* Enable GPIO output drivers */ - byte = pci_read_config8(PCI_DEV(0, 0x14, 3), 0xd0); - byte &= 0x0f; - pci_write_config8(PCI_DEV(0, 0x14, 3), 0xd0, byte); - - printk(BIOS_DEBUG, "Node %02d DIMM voltage set to index %02x\n", node, index); -} - -void DIMMSetVoltages(struct MCTStatStruc *pMCTstat, - struct DCTStatStruc *pDCTstatA) { - /* This mainboard allows the DIMM voltage to be set per-socket. - * Therefore, for each socket, iterate over all DIMMs to find the - * lowest supported voltage common to all DIMMs on that socket. - */ - uint8_t nvram; - uint8_t dimm; - uint8_t node; - uint8_t socket; - uint8_t allowed_voltages = 0xf; /* The mainboard VRMs allow 1.15V, 1.25V, 1.35V, and 1.5V */ - uint8_t socket_allowed_voltages = allowed_voltages; - uint32_t set_voltage = 0; - - if (get_option(&nvram, "minimum_memory_voltage") == CB_SUCCESS) { - switch (nvram) { - case 2: - allowed_voltages = 0x7; /* Allow 1.25V, 1.35V, and 1.5V */ - break; - case 1: - allowed_voltages = 0x3; /* Allow 1.35V and 1.5V */ - break; - case 0: - default: - allowed_voltages = 0x1; /* Allow 1.5V only */ - break; - } - } - - for (node = 0; node < MAX_NODES_SUPPORTED; node++) { - socket = node / 2; - struct DCTStatStruc *pDCTstat; - pDCTstat = pDCTstatA + node; - - /* reset socket_allowed_voltages before processing each socket */ - if (!(node % 2)) - socket_allowed_voltages = allowed_voltages; - - if (pDCTstat->NodePresent) { - for (dimm = 0; dimm < MAX_DIMMS_SUPPORTED; dimm++) { - if (pDCTstat->DIMMValid & (1 << dimm)) { - socket_allowed_voltages &= pDCTstat->DimmSupportedVoltages[dimm]; - } - } - } - - /* set voltage per socket after processing last contained node */ - if (pDCTstat->NodePresent && (node % 2)) { - /* Set voltages */ - if (socket_allowed_voltages & 0x8) { - set_voltage = 0x8; - set_ddr3_voltage(socket, 3); - } else if (socket_allowed_voltages & 0x4) { - set_voltage = 0x4; - set_ddr3_voltage(socket, 2); - } else if (socket_allowed_voltages & 0x2) { - set_voltage = 0x2; - set_ddr3_voltage(socket, 1); - } else { - set_voltage = 0x1; - set_ddr3_voltage(socket, 0); - } - - /* Save final DIMM voltages for MCT and SMBIOS use */ - if (pDCTstat->NodePresent) { - for (dimm = 0; dimm < MAX_DIMMS_SUPPORTED; dimm++) { - pDCTstat->DimmConfiguredVoltage[dimm] = set_voltage; - } - } - pDCTstat = pDCTstatA + (node - 1); - if (pDCTstat->NodePresent) { - for (dimm = 0; dimm < MAX_DIMMS_SUPPORTED; dimm++) { - pDCTstat->DimmConfiguredVoltage[dimm] = set_voltage; - } - } - } - } - - /* Allow the DDR supply voltages to settle */ - udelay(100000); -} - -static void set_peripheral_control_lines(void) { - uint8_t byte; - uint8_t nvram; - uint8_t enable_ieee1394; - - enable_ieee1394 = 1; - - if (get_option(&nvram, "ieee1394_controller") == CB_SUCCESS) - enable_ieee1394 = nvram & 0x1; - - if (enable_ieee1394) { - /* Enable PCICLK5 (onboard FireWire device) */ - outb(0x41, 0xcd6); - outb(0x02, 0xcd7); - } else { - /* Disable PCICLK5 (onboard FireWire device) */ - outb(0x41, 0xcd6); - outb(0x00, 0xcd7); - } - - /* Enable the RTC AltCentury register */ - outb(0x41, 0xcd6); - byte = inb(0xcd7); - byte |= 0x10; - outb(byte, 0xcd7); -} - -#ifdef TEST_MEMORY -static void execute_memory_test(void) -{ - /* Test DRAM functionality */ - uint32_t i; - uint32_t v; - uint32_t w; - uint32_t x; - uint32_t y; - uint32_t z; - uint32_t *dataptr; - uint32_t readback; - uint32_t start = 0x300000; - printk(BIOS_DEBUG, "Writing test pattern 1 to memory...\n"); - for (i = 0; i < 0x1000000; i = i + 8) { - dataptr = (void *)(start + i); - *dataptr = 0x55555555; - dataptr = (void *)(start + i + 4); - *dataptr = 0xaaaaaaaa; - } - printk(BIOS_DEBUG, "Done!\n"); - printk(BIOS_DEBUG, "Testing memory...\n"); - for (i = 0; i < 0x1000000; i = i + 8) { - dataptr = (void *)(start + i); - readback = *dataptr; - if (readback != 0x55555555) - printk(BIOS_DEBUG, "%p: INCORRECT VALUE %08x (should have been %08x)\n", dataptr, readback, 0x55555555); - dataptr = (void *)(start + i + 4); - readback = *dataptr; - if (readback != 0xaaaaaaaa) - printk(BIOS_DEBUG, "%p: INCORRECT VALUE %08x (should have been %08x)\n", dataptr, readback, 0xaaaaaaaa); - } - printk(BIOS_DEBUG, "Done!\n"); - printk(BIOS_DEBUG, "Writing test pattern 2 to memory...\n"); - /* Set up the PRNG seeds for initial write */ - w = 0x55555555; - x = 0xaaaaaaaa; - y = 0x12345678; - z = 0x87654321; - for (i = 0; i < 0x1000000; i = i + 4) { - /* Use Xorshift as a PRNG to stress test the bus */ - v = x; - v ^= v << 11; - v ^= v >> 8; - x = y; - y = z; - z = w; - w ^= w >> 19; - w ^= v; - dataptr = (void *)(start + i); - *dataptr = w; - } - printk(BIOS_DEBUG, "Done!\n"); - printk(BIOS_DEBUG, "Testing memory...\n"); - /* Reset the PRNG seeds for readback */ - w = 0x55555555; - x = 0xaaaaaaaa; - y = 0x12345678; - z = 0x87654321; - for (i = 0; i < 0x1000000; i = i + 4) { - /* Use Xorshift as a PRNG to stress test the bus */ - v = x; - v ^= v << 11; - v ^= v >> 8; - x = y; - y = z; - z = w; - w ^= w >> 19; - w ^= v; - dataptr = (void *)(start + i); - readback = *dataptr; - if (readback != w) - printk(BIOS_DEBUG, "%p: INCORRECT VALUE %08x (should have been %08x)\n", dataptr, readback, w); - } - printk(BIOS_DEBUG, "Done!\n"); -} -#endif - -static spinlock_t printk_spinlock CAR_GLOBAL; - -spinlock_t *romstage_console_lock(void) -{ - return car_get_var_ptr(&printk_spinlock); -} - -void initialize_romstage_console_lock(void) -{ - spin_unlock(romstage_console_lock()); -} - -static spinlock_t nvram_cbfs_spinlock CAR_GLOBAL; - -spinlock_t *romstage_nvram_cbfs_lock(void) -{ - return car_get_var_ptr(&nvram_cbfs_spinlock); -} - -void initialize_romstage_nvram_cbfs_lock(void) -{ - spin_unlock(romstage_nvram_cbfs_lock()); -} - -static spinlock_t microcode_cbfs_spinlock CAR_GLOBAL; - -spinlock_t *romstage_microcode_cbfs_lock(void) -{ - return car_get_var_ptr(µcode_cbfs_spinlock); -} - -void initialize_romstage_microcode_cbfs_lock(void) -{ - spin_unlock(romstage_microcode_cbfs_lock()); -} - -void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) -{ - uint32_t esp; - __asm__ volatile ( - "movl %%esp, %0" - : "=r" (esp) - ); - - struct sys_info *sysinfo = get_sysinfo(); - - /* Limit the maximum HT speed to 2.6GHz to prevent lockups - * due to HT CPU <--> CPU wiring not being validated to 3.2GHz - */ - sysinfo->ht_link_cfg.ht_speed_limit = 2600; - - uint32_t bsp_apicid = 0, val; - uint8_t byte; - uint8_t power_on_reset = 0; - msr_t msr; - - int s3resume = acpi_is_wakeup_s3(); - - if (!cpu_init_detectedx && boot_cpu()) { - /* Initial timestamp */ - timestamp_init(timestamp_get()); - timestamp_add_now(TS_START_ROMSTAGE); - - /* Initialize the printk, nvram CBFS, and microcode CBFS spinlocks */ - initialize_romstage_console_lock(); - initialize_romstage_nvram_cbfs_lock(); - initialize_romstage_microcode_cbfs_lock(); - - /* Nothing special needs to be done to find bus 0 */ - /* Allow the HT devices to be found */ - set_bsp_node_CHtExtNodeCfgEn(); - enumerate_ht_chain(); - - /* SR56x0 pcie bridges block pci_locate_device() before pcie training. - * disable all pcie bridges on SR56x0 to work around it - */ - sr5650_disable_pcie_bridge(); - - /* Initialize southbridge */ - sb7xx_51xx_pci_port80(); - - /* Configure secondary serial port pin mux */ - winbond_set_pinmux(SERIAL_1_DEV, 0x2a, W83667HG_SPI_PINMUX_GPIO4_SERIAL_B_MASK, W83667HG_SPI_PINMUX_SERIAL_B); - - /* Initialize early serial */ - winbond_enable_serial(SERIAL_0_DEV, CONFIG_TTYS0_BASE); - console_init(); - - /* Disable LPC legacy DMA support to prevent lockup */ - byte = pci_read_config8(PCI_DEV(0, 0x14, 3), 0x78); - byte &= ~(1 << 0); - pci_write_config8(PCI_DEV(0, 0x14, 3), 0x78, byte); - } - - printk(BIOS_SPEW, "Initial stack pointer: %08x\n", esp); - - post_code(0x30); - - if (bist == 0) - bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo); - - post_code(0x32); - - enable_sr5650_dev8(); - sb7xx_51xx_lpc_init(); - - if (CONFIG_MAX_PHYSICAL_CPUS != 4) - printk(BIOS_WARNING, "CONFIG_MAX_PHYSICAL_CPUS is %d, but this is a dual socket AMD G34 board!\n", CONFIG_MAX_PHYSICAL_CPUS); - - /* Halt if there was a built in self test failure */ - report_bist_failure(bist); - - val = cpuid_eax(1); - printk(BIOS_DEBUG, "BSP Family_Model: %08x\n", val); - printk(BIOS_DEBUG, "*sysinfo range: [%p,%p]\n",sysinfo,sysinfo+1); - printk(BIOS_DEBUG, "bsp_apicid = %02x\n", bsp_apicid); - printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx); - - /* Setup sysinfo defaults */ - set_sysinfo_in_ram(0); - - if (!sb7xx_51xx_decode_last_reset()) - power_on_reset = 1; - - initialize_mca(1, power_on_reset); - update_microcode(val); - - post_code(0x33); - - cpuSetAMDMSR(0); - post_code(0x34); - - amd_ht_init(sysinfo); - amd_ht_fixup(sysinfo); - post_code(0x35); - - /* Setup nodes PCI space and start core 0 AP init. */ - finalize_node_setup(sysinfo); - - /* Setup any mainboard PCI settings etc. */ - setup_mb_resource_map(); - initialize_mca(0, power_on_reset); - post_code(0x36); - - /* Wait for all the APs core0 started by finalize_node_setup. */ - wait_all_core0_started(); - - /* run _early_setup before soft-reset. */ - sr5650_early_setup(); - sb7xx_51xx_early_setup(); - - if (CONFIG(LOGICAL_CPUS)) { - /* Core0 on each node is configured. Now setup any additional cores. */ - printk(BIOS_DEBUG, "start_other_cores()\n"); - start_other_cores(bsp_apicid); - post_code(0x37); - wait_all_other_cores_started(bsp_apicid); - } - - if (CONFIG(SET_FIDVID)) { - msr = rdmsr(MSR_COFVID_STS); - printk(BIOS_DEBUG, "\nBegin FIDVID MSR 0xc0010071 0x%08x 0x%08x\n", msr.hi, msr.lo); - - /* FIXME: The sb fid change may survive the warm reset and only need to be done once */ - enable_fid_change_on_sb(sysinfo->sbbusn, sysinfo->sbdn); - - post_code(0x39); - - #if CONFIG(SET_FIDVID) - if (!warm_reset_detect(0)) { // BSP is node 0 - init_fidvid_bsp(bsp_apicid, sysinfo->nodes); - } else { - init_fidvid_stage2(bsp_apicid, 0); // BSP is node 0 - } - #endif - - post_code(0x3A); - - /* show final fid and vid */ - msr = rdmsr(MSR_COFVID_STS); - printk(BIOS_DEBUG, "End FIDVIDMSR 0xc0010071 0x%08x 0x%08x\n", msr.hi, msr.lo); - } - - post_code(0x38); - - init_timer(); // Need to use TMICT to synconize FID/VID - - sr5650_htinit(); - - /* Reset for HT, FIDVID, PLL and errata changes to take effect. */ - if (!warm_reset_detect(0)) { - printk(BIOS_INFO, "...WARM RESET...\n\n\n"); - soft_reset(); - die("After soft_reset - shouldn't see this message!!!\n"); - } - - sr5650_htinit_dect_and_enable_isochronous_link(); - - /* Set default DDR memory voltage - * This will be overridden later during RAM initialization - */ - set_lpc_sticky_ctl(1); /* Retain LPC/IMC GPIO configuration during S3 sleep */ - if (!s3resume) { /* Avoid supply voltage glitches while the DIMMs are retaining data */ - set_ddr3_voltage(0, 0); /* Node 0 */ - set_ddr3_voltage(1, 0); /* Node 1 */ - } - - /* Set up peripheral control lines */ - set_peripheral_control_lines(); - - post_code(0x3B); - - /* Wait for all APs to be stopped, otherwise RAM initialization may hang */ - if (CONFIG(LOGICAL_CPUS)) - wait_all_other_cores_stopped(bsp_apicid); - - /* It's the time to set ctrl in sysinfo now; */ - printk(BIOS_DEBUG, "fill_mem_ctrl() detected %d nodes\n", sysinfo->nodes); - if (is_fam15h()) - fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr_fam15); - else - fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr_fam10); - post_code(0x3D); - -#if 0 - /* FIXME - * After the AMD K10 code has been converted to use - * CONFIG(DEBUG_SMBUS) uncomment this block - */ - if (CONFIG(DEBUG_SMBUS)) { - dump_spd_registers(&cpu[0]); - dump_smbus_registers(); - } -#endif - - post_code(0x40); - - raminit_amdmct(sysinfo); - -#ifdef TEST_MEMORY - execute_memory_test(); -#endif - - if (s3resume) - cbmem_initialize(); - else - cbmem_initialize_empty(); - - romstage_handoff_init(s3resume); - - post_code(0x41); - - amdmct_cbmem_store_info(sysinfo); - - printk(BIOS_DEBUG, "disable_spd()\n"); - switch_spd_mux(0x1); - - sr5650_before_pci_init(); - sb7xx_51xx_before_pci_init(); - - /* Configure SP5100 GPIOs to match vendor settings */ - pci_write_config16(PCI_DEV(0, 0x14, 0), 0x50, 0x0170); - pci_write_config16(PCI_DEV(0, 0x14, 0), 0x54, 0x0707); - pci_write_config16(PCI_DEV(0, 0x14, 0), 0x56, 0x0bb0); - pci_write_config16(PCI_DEV(0, 0x14, 0), 0x5a, 0x0ff0); -} - -/** - * BOOL AMD_CB_ManualBUIDSwapList(u8 Node, u8 Link, u8 **List) - * Description: - * This routine is called every time a non-coherent chain is processed. - * BUID assignment may be controlled explicitly on a non-coherent chain. Provide a - * swap list. The first part of the list controls the BUID assignment and the - * second part of the list provides the device to device linking. Device orientation - * can be detected automatically, or explicitly. See documentation for more details. - * - * Automatic non-coherent init assigns BUIDs starting at 1 and incrementing sequentially - * based on each device's unit count. - * - * Parameters: - * @param[in] node = The node on which this chain is located - * @param[in] link = The link on the host for this chain - * @param[out] List = supply a pointer to a list - */ -BOOL AMD_CB_ManualBUIDSwapList (u8 node, u8 link, const u8 **List) -{ - /* Force BUID to 0 */ - static const u8 swaplist[] = {0, 0, 0xFF, 0, 0xFF}; - if ((is_fam15h() && (node == 0) && (link == 1)) /* Family 15h BSP SB link */ - || (!is_fam15h() && (node == 0) && (link == 3))) { /* Family 10h BSP SB link */ - *List = swaplist; - return 1; - } - - return 0; -} diff --git a/src/mainboard/asus/kgpe-d16/spd_notes.txt b/src/mainboard/asus/kgpe-d16/spd_notes.txt deleted file mode 100644 index d944229f00..0000000000 --- a/src/mainboard/asus/kgpe-d16/spd_notes.txt +++ /dev/null @@ -1,46 +0,0 @@ -==================================================================================================== -SPD mux -==================================================================================================== - SP5100 - GPIO 60 GPIO 59 -Disabled 0 0 -Normal operation 0 1 -CPU 0 SPD 1 0 -CPU 1 SPD 1 1 - -==================================================================================================== -W83795 -==================================================================================================== - -Sensor mappings: -CPU_FAN1: FAN1 -CPU_FAN2: FAN2 -FRNT_FAN1: FAN3 -FRNT_FAN2: FAN4 -FRNT_FAN3: FAN5 -FRNT_FAN4: FAN6 -FRNT_FAN5: FAN7 -REAR_FAN1: FAN8 - -==================================================================================================== -Other hardware -==================================================================================================== - -RECOVERY1 middle pin is connected to southbridge (AMD SP5100) GPIO 61 -Normal is HIGH, recovery is LOW. - -+12VSB is generated using a charge pump attached to pin 7 of PU24 (APW7145). - -The +12VSB standby voltage to each bank of DIMMs is switched by a bank of small FETs located close to each RAM power regulator control chip. -The +12V primary voltage (lower left pin of the FET placed on the upper left of the control chip of the second node) is also connected to the 232GE located near the PCI slot. - -The control line running to the gates of the +12VSB control FETs is connected to the +5VSB power for the USB ports. -That line in turn is connected to +5VSB via the lone P06P03G PMOS transistor on the reverse side of the board, near the center on the lower half. -The gate of that transistor is connected via a resistor to the source of the P06P03G PMOS transistor located adjacent to the unpopulated SMA clock header. -The gate of that transistor is connected directly to the drain of the small FET directly below it. -After that, there's a cascade of small FETs and resistors in that region, eventually leading to SuperIO pin 81. - -SuperIO pin 81 (VSBGATE#) enables the standby voltage rails when set LOW. -VSBGATE# is reset on every assertion of PWRGOOD. - -Setting SuperIO LDN 9 CRF4 bits 1 or 0 (or both) to 0 disables NICB. diff --git a/src/mainboard/asus/m4a78-em/Kconfig b/src/mainboard/asus/m4a78-em/Kconfig deleted file mode 100644 index d190e53c24..0000000000 --- a/src/mainboard/asus/m4a78-em/Kconfig +++ /dev/null @@ -1,53 +0,0 @@ -if BOARD_ASUS_M4A78_EM - -config BOARD_SPECIFIC_OPTIONS - def_bool y - select CPU_AMD_SOCKET_AM3 - select DIMM_DDR2 - select NORTHBRIDGE_AMD_AMDFAM10 - select SOUTHBRIDGE_AMD_RS780 - select SOUTHBRIDGE_AMD_SB700 - select SUPERIO_ITE_IT8712F - select HAVE_OPTION_TABLE - select HAVE_PIRQ_TABLE - select HAVE_MP_TABLE - select SB_HT_CHAIN_UNITID_OFFSET_ONLY - select LIFT_BSP_APIC_ID - select HAVE_ACPI_TABLES - select BOARD_ROMSIZE_KB_1024 - select ENABLE_APIC_EXT_ID - select GFXUMA - -config MAINBOARD_DIR - string - default asus/m4a78-em - -config APIC_ID_OFFSET - hex - default 0x0 - -config MAINBOARD_PART_NUMBER - string - default "M4A78-EM" - -config MAX_CPUS - int - default 8 - -config MAX_PHYSICAL_CPUS - int - default 2 - -config HT_CHAIN_END_UNITID_BASE - hex - default 0x1 - -config HT_CHAIN_UNITID_BASE - hex - default 0x0 - -config IRQ_SLOT_COUNT - int - default 18 - -endif diff --git a/src/mainboard/asus/m4a78-em/Kconfig.name b/src/mainboard/asus/m4a78-em/Kconfig.name deleted file mode 100644 index fdb9254f24..0000000000 --- a/src/mainboard/asus/m4a78-em/Kconfig.name +++ /dev/null @@ -1,2 +0,0 @@ -config BOARD_ASUS_M4A78_EM - bool "M4A78-EM" diff --git a/src/mainboard/asus/m4a78-em/Makefile.inc b/src/mainboard/asus/m4a78-em/Makefile.inc deleted file mode 100644 index 91d4b39c32..0000000000 --- a/src/mainboard/asus/m4a78-em/Makefile.inc +++ /dev/null @@ -1,16 +0,0 @@ -# -# This file is part of the coreboot project. -# -# This program is free software; you can redistribute it and/or modify -# it under the terms of the GNU General Public License as published by -# the Free Software Foundation; version 2 of the License. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# - -romstage-y += resourcemap.c - -ramstage-y += get_bus_conf.c diff --git a/src/mainboard/asus/m4a78-em/acpi/cpstate.asl b/src/mainboard/asus/m4a78-em/acpi/cpstate.asl deleted file mode 100644 index acaa5bae32..0000000000 --- a/src/mainboard/asus/m4a78-em/acpi/cpstate.asl +++ /dev/null @@ -1,80 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2010 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -/* This file defines the processor and performance state capability - * for each core in the system. It is included into the DSDT for each - * core. It assumes that each core of the system has the same performance - * characteristics. -*/ -/* -#include -DefinitionBlock ("DSDT.AML", "DSDT", 0x01, OEM_ID, ACPI_TABLE_CREATOR, 0x00010001) - { - Scope (\_PR) { - Device (CPU0) { - Name (_HID, "ACPI0007") - Name (_UID, 0) - #include "cpstate.asl" - } - Device (CPU1) { - Name (_HID, "ACPI0007") - Name (_UID, 1) - #include "cpstate.asl" - } - Device (CPU2) { - Name (_HID, "ACPI0007") - Name (_UID, 2) - #include "cpstate.asl" - } - Device (CPU3) { - Name (_HID, "ACPI0007") - Name (_UID, 3) - #include "cpstate.asl" - } - } -*/ - /* P-state support: The maximum number of P-states supported by the */ - /* CPUs we'll use is 6. */ - /* Get from AMI BIOS. */ - Name(_PSS, Package(){ - Package () - { - 0x00000AF0, - 0x0000BF81, - 0x00000002, - 0x00000002, - 0x00000000, - 0x00000000 - }, - - Package () - { - 0x00000578, - 0x000076F2, - 0x00000002, - 0x00000002, - 0x00000001, - 0x00000001 - } - }) - - Name(_PCT, Package(){ - ResourceTemplate(){Register(FFixedHW, 0, 0, 0)}, - ResourceTemplate(){Register(FFixedHW, 0, 0, 0)} - }) - - Method(_PPC, 0){ - Return(0) - } diff --git a/src/mainboard/asus/m4a78-em/acpi/ide.asl b/src/mainboard/asus/m4a78-em/acpi/ide.asl deleted file mode 100644 index 5c155cf301..0000000000 --- a/src/mainboard/asus/m4a78-em/acpi/ide.asl +++ /dev/null @@ -1,240 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2010 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -/* -Scope (_SB) { - Device(PCI0) { - Device(IDEC) { - Name(_ADR, 0x00140001) - #include "ide.asl" - } - } -} -*/ - -/* Some timing tables */ -Name(UDTT, Package(){ /* Udma timing table */ - 120, 90, 60, 45, 30, 20, 15, 0 /* UDMA modes 0 -> 6 */ -}) - -Name(MDTT, Package(){ /* MWDma timing table */ - 480, 150, 120, 0 /* Legacy DMA modes 0 -> 2 */ -}) - -Name(POTT, Package(){ /* Pio timing table */ - 600, 390, 270, 180, 120, 0 /* PIO modes 0 -> 4 */ -}) - -/* Some timing register value tables */ -Name(MDRT, Package(){ /* MWDma timing register table */ - 0x77, 0x21, 0x20, 0xFF /* Legacy DMA modes 0 -> 2 */ -}) - -Name(PORT, Package(){ - 0x99, 0x47, 0x34, 0x22, 0x20, 0x99 /* PIO modes 0 -> 4 */ -}) - -OperationRegion(ICRG, PCI_Config, 0x40, 0x20) /* ide control registers */ - Field(ICRG, AnyAcc, NoLock, Preserve) -{ - PPTS, 8, /* Primary PIO Slave Timing */ - PPTM, 8, /* Primary PIO Master Timing */ - OFFSET(0x04), PMTS, 8, /* Primary MWDMA Slave Timing */ - PMTM, 8, /* Primary MWDMA Master Timing */ - OFFSET(0x08), PPCR, 8, /* Primary PIO Control */ - OFFSET(0x0A), PPMM, 4, /* Primary PIO master Mode */ - PPSM, 4, /* Primary PIO slave Mode */ - OFFSET(0x14), PDCR, 2, /* Primary UDMA Control */ - OFFSET(0x16), PDMM, 4, /* Primary UltraDMA Mode */ - PDSM, 4, /* Primary UltraDMA Mode */ -} - -Method(GTTM, 1) /* get total time*/ -{ - Store(And(Arg0, 0x0F), Local0) /* Recovery Width */ - Increment(Local0) - Store(ShiftRight(Arg0, 4), Local1) /* Command Width */ - Increment(Local1) - Return(Multiply(30, Add(Local0, Local1))) -} - -Device(PRID) -{ - Name (_ADR, Zero) - Method(_GTM, 0) - { - NAME(OTBF, Buffer(20) { /* out buffer */ - 0xFF, 0xFF, 0xFF, 0xFF, - 0xFF, 0xFF, 0xFF, 0xFF, - 0xFF, 0xFF, 0xFF, 0xFF, - 0xFF, 0xFF, 0xFF, 0xFF, 0x00, 0x00, 0x00, 0x00 - }) - - CreateDwordField(OTBF, 0, PSD0) /* PIO spd0 */ - CreateDwordField(OTBF, 4, DSD0) /* DMA spd0 */ - CreateDwordField(OTBF, 8, PSD1) /* PIO spd1 */ - CreateDwordField(OTBF, 12, DSD1) /* DMA spd1 */ - CreateDwordField(OTBF, 16, BFFG) /* buffer flags */ - - /* Just return if the channel is disabled */ - If(And(PPCR, 0x01)) { /* primary PIO control */ - Return(OTBF) - } - - /* Always tell them independent timing available and IOChannelReady used on both drives */ - Or(BFFG, 0x1A, BFFG) - - Store(GTTM(PPTM), PSD0) /* save total time of primary PIO master timming to PIO spd0 */ - Store(GTTM(PPTS), PSD1) /* save total time of primary PIO slave Timing to PIO spd1 */ - - If(And(PDCR, 0x01)) { /* It's under UDMA mode */ - Or(BFFG, 0x01, BFFG) - Store(DerefOf(Index(UDTT, PDMM)), DSD0) - } - Else { - Store(GTTM(PMTM), DSD0) /* Primary MWDMA Master Timing, DmaSpd0 */ - } - - If(And(PDCR, 0x02)) { /* It's under UDMA mode */ - Or(BFFG, 0x04, BFFG) - Store(DerefOf(Index(UDTT, PDSM)), DSD1) - } - Else { - Store(GTTM(PMTS), DSD1) /* Primary MWDMA Slave Timing, DmaSpd0 */ - } - - Return(OTBF) /* out buffer */ - } /* End Method(_GTM) */ - - Method(_STM, 3, NotSerialized) - { - NAME(INBF, Buffer(20) { /* in buffer */ - 0xFF, 0xFF, 0xFF, 0xFF, - 0xFF, 0xFF, 0xFF, 0xFF, - 0xFF, 0xFF, 0xFF, 0xFF, - 0xFF, 0xFF, 0xFF, 0xFF, 0x00, 0x00, 0x00, 0x00 - }) - - CreateDwordField(INBF, 0, PSD0) /* PIO spd0 */ - CreateDwordField(INBF, 4, DSD0) /* PIO spd0 */ - CreateDwordField(INBF, 8, PSD1) /* PIO spd1 */ - CreateDwordField(INBF, 12, DSD1) /* DMA spd1 */ - CreateDwordField(INBF, 16, BFFG) /*buffer flag */ - - Store(Match(POTT, MLE, PSD0, MTR, 0, 0), Local0) - Divide(Local0, 5, PPMM,) /* Primary PIO master Mode */ - Store(Match(POTT, MLE, PSD1, MTR, 0, 0), Local1) - Divide(Local1, 5, PPSM,) /* Primary PIO slave Mode */ - - Store(DerefOf(Index(PORT, Local0)), PPTM) /* Primary PIO Master Timing */ - Store(DerefOf(Index(PORT, Local1)), PPTS) /* Primary PIO Slave Timing */ - - If(And(BFFG, 0x01)) { /* Drive 0 is under UDMA mode */ - Store(Match(UDTT, MLE, DSD0, MTR, 0, 0), Local0) - Divide(Local0, 7, PDMM,) - Or(PDCR, 0x01, PDCR) - } - Else { - If(LNotEqual(DSD0, 0xFFFFFFFF)) { - Store(Match(MDTT, MLE, DSD0, MTR, 0, 0), Local0) - Store(DerefOf(Index(MDRT, Local0)), PMTM) - } - } - - If(And(BFFG, 0x04)) { /* Drive 1 is under UDMA mode */ - Store(Match(UDTT, MLE, DSD1, MTR, 0, 0), Local0) - Divide(Local0, 7, PDSM,) - Or(PDCR, 0x02, PDCR) - } - Else { - If(LNotEqual(DSD1, 0xFFFFFFFF)) { - Store(Match(MDTT, MLE, DSD1, MTR, 0, 0), Local0) - Store(DerefOf(Index(MDRT, Local0)), PMTS) - } - } - /* Return(INBF) */ - } /*End Method(_STM) */ - Device(MST) - { - Name(_ADR, 0) - Method(_GTF) { - Name(CMBF, Buffer(21) { - 0x03, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xEF, - 0x03, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xEF, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xF5 - }) - CreateByteField(CMBF, 1, POMD) - CreateByteField(CMBF, 8, DMMD) - CreateByteField(CMBF, 5, CMDA) - CreateByteField(CMBF, 12, CMDB) - CreateByteField(CMBF, 19, CMDC) - - Store(0xA0, CMDA) - Store(0xA0, CMDB) - Store(0xA0, CMDC) - - Or(PPMM, 0x08, POMD) - - If(And(PDCR, 0x01)) { - Or(PDMM, 0x40, DMMD) - } - Else { - Store(Match - (MDTT, MLE, GTTM(PMTM), - MTR, 0, 0), Local0) - If(LLess(Local0, 3)) { - Or(0x20, Local0, DMMD) - } - } - Return(CMBF) - } - } /* End Device(MST) */ - - Device(SLAV) - { - Name(_ADR, 1) - Method(_GTF) { - Name(CMBF, Buffer(21) { - 0x03, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xEF, - 0x03, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xEF, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xF5 - }) - CreateByteField(CMBF, 1, POMD) - CreateByteField(CMBF, 8, DMMD) - CreateByteField(CMBF, 5, CMDA) - CreateByteField(CMBF, 12, CMDB) - CreateByteField(CMBF, 19, CMDC) - - Store(0xB0, CMDA) - Store(0xB0, CMDB) - Store(0xB0, CMDC) - - Or(PPSM, 0x08, POMD) - - If(And(PDCR, 0x02)) { - Or(PDSM, 0x40, DMMD) - } - Else { - Store(Match - (MDTT, MLE, GTTM(PMTS), - MTR, 0, 0), Local0) - If(LLess(Local0, 3)) { - Or(0x20, Local0, DMMD) - } - } - Return(CMBF) - } - } /* End Device(SLAV) */ -} diff --git a/src/mainboard/asus/m4a78-em/acpi/routing.asl b/src/mainboard/asus/m4a78-em/acpi/routing.asl deleted file mode 100644 index 072aa2117f..0000000000 --- a/src/mainboard/asus/m4a78-em/acpi/routing.asl +++ /dev/null @@ -1,297 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2010 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -/* -#include -DefinitionBlock ("DSDT.AML", "DSDT", 0x01, OEM_ID, ACPI_TABLE_CREATOR, 0x00010001 - ) - { - #include "routing.asl" - } -*/ - -/* Routing is in System Bus scope */ -Scope(\_SB) { - Name(PR0, Package(){ - /* NB devices */ - /* Bus 0, Dev 0 - RS780 Host Controller */ - /* Bus 0, Dev 1 - PCI Bridge for Internal Graphics */ - /* Bus 0, Dev 2 - PCIe Bridge for x8 PCIe Slot (GFX0) */ - Package(){0x0002FFFF, 0, INTC, 0 }, - Package(){0x0002FFFF, 1, INTD, 0 }, - Package(){0x0002FFFF, 2, INTA, 0 }, - Package(){0x0002FFFF, 3, INTB, 0 }, - /* Bus 0, Dev 3 - PCIe graphics port 1 bridge */ - /* Bus 0, Dev 4 - PCIe Bridge for Express Card Slot */ - Package(){0x0004FFFF, 0, INTA, 0 }, - Package(){0x0004FFFF, 1, INTB, 0 }, - Package(){0x0004FFFF, 2, INTC, 0 }, - Package(){0x0004FFFF, 3, INTD, 0 }, - /* Bus 0, Dev 5 - General purpose PCIe bridge 5 */ - /* Package(){0x0005FFFF, 0, INTB, 0 }, */ - /* Package(){0x0005FFFF, 1, INTC, 0 }, */ - /* Package(){0x0005FFFF, 2, INTD, 0 }, */ - /* Package(){0x0005FFFF, 3, INTA, 0 }, */ - /* Bus 0, Dev 6 - PCIe Bridge for Ethernet Chip */ - Package(){0x0006FFFF, 0, INTC, 0 }, - Package(){0x0006FFFF, 1, INTD, 0 }, - Package(){0x0006FFFF, 2, INTA, 0 }, - Package(){0x0006FFFF, 3, INTB, 0 }, - /* Bus 0, Dev 7 - PCIe Bridge for x1 PCIe Slot */ - Package(){0x0007FFFF, 0, INTD, 0 }, - Package(){0x0007FFFF, 1, INTA, 0 }, - Package(){0x0007FFFF, 2, INTB, 0 }, - Package(){0x0007FFFF, 3, INTC, 0 }, - /* Bus 0, Funct 8 - Southbridge port (normally hidden) */ - - /* SB devices */ - /* Bus 0, Dev 17 - SATA controller #2 */ - /* Bus 0, Dev 18 - SATA controller #1 */ - Package(){0x0011FFFF, 1, INTA, 0 }, - - /* Bus 0, Dev 19 - USB: OHCI, funct 0-4; EHCI, funct 5 */ - Package(){0x0012FFFF, 0, INTA, 0 }, - Package(){0x0012FFFF, 1, INTB, 0 }, - Package(){0x0013FFFF, 0, INTA, 0 }, - Package(){0x0013FFFF, 1, INTB, 0 }, - Package(){0x0014FFFF, 2, INTA, 0 }, - - /* Bus 0, Dev 20 - F0:SMBus/ACPI,F1:IDE;F2:HDAudio;F3:LPC;F4:PCIBridge;F5:AC97 Audio;F6:AC97 Modem */ - Package(){0x0014FFFF, 0, INTA, 0 }, - Package(){0x0014FFFF, 1, INTB, 0 }, - Package(){0x0014FFFF, 2, INTC, 0 }, - Package(){0x0014FFFF, 3, INTD, 0 }, - }) - - Name(APR0, Package(){ - /* NB devices in APIC mode */ - /* Bus 0, Dev 0 - RS780 Host Controller */ - - /* Bus 0, Dev 1 - PCI Bridge for Internal Graphics */ - /* Package(){0x0001FFFF, 0, 0, 18 }, */ - /* Package(){0x0001FFFF, 1, 0, 19 }, */ - - /* Bus 0, Dev 2 - PCIe Bridge for x8 PCIe Slot (GFX0) */ - Package(){0x0002FFFF, 0, 0, 18 }, - /* Package(){0x0002FFFF, 1, 0, 19 }, */ - /* Package(){0x0002FFFF, 2, 0, 16 }, */ - /* Package(){0x0002FFFF, 3, 0, 17 }, */ - - /* Bus 0, Dev 3 - PCIe graphics port 1 bridge */ - Package(){0x0003FFFF, 0, 0, 19 }, - - /* Bus 0, Dev 4 - PCIe Bridge for Express Card Slot */ - Package(){0x0004FFFF, 0, 0, 16 }, - /* Package(){0x0004FFFF, 1, 0, 17 }, */ - /* Package(){0x0004FFFF, 2, 0, 18 }, */ - /* Package(){0x0004FFFF, 3, 0, 19 }, */ - - /* Bus 0, Dev 5 - General purpose PCIe bridge 5 */ - /* Package(){0x0005FFFF, 0, 0, 17 }, */ - /* Package(){0x0005FFFF, 1, 0, 18 }, */ - /* Package(){0x0005FFFF, 2, 0, 19 }, */ - /* Package(){0x0005FFFF, 3, 0, 16 }, */ - - /* Bus 0, Dev 6 - General purpose PCIe bridge 6 */ - /* Package(){0x0006FFFF, 0, 0, 18 }, */ - /* Package(){0x0006FFFF, 1, 0, 19 }, */ - /* Package(){0x0006FFFF, 2, 0, 16 }, */ - /* Package(){0x0006FFFF, 3, 0, 17 }, */ - - /* Bus 0, Dev 7 - PCIe Bridge for network card */ - /* Package(){0x0007FFFF, 0, 0, 19 }, */ - /* Package(){0x0007FFFF, 1, 0, 16 }, */ - /* Package(){0x0007FFFF, 2, 0, 17 }, */ - /* Package(){0x0007FFFF, 3, 0, 18 }, */ - - /* Bus 0, Dev 9 - PCIe Bridge for network card */ - Package(){0x0009FFFF, 0, 0, 17 }, - /* Package(){0x0009FFFF, 1, 0, 16 }, */ - /* Package(){0x0009FFFF, 2, 0, 17 }, */ - /* Package(){0x0009FFFF, 3, 0, 18 }, */ - /* Bus 0, Dev A - PCIe Bridge for network card */ - Package(){0x000AFFFF, 0, 0, 18 }, - /* Package(){0x000AFFFF, 1, 0, 16 }, */ - /* Package(){0x000AFFFF, 2, 0, 17 }, */ - /* Package(){0x000AFFFF, 3, 0, 18 }, */ - /* Bus 0, Funct 8 - Southbridge port (normally hidden) */ - - /* SB devices in APIC mode */ - /* Bus 0, Dev 17 - SATA controller #2 */ - /* Bus 0, Dev 18 - SATA controller #1 */ - Package(){0x0011FFFF, 0, 0, 22 }, - - /* Bus 0, Dev 19 - USB: OHCI, funct 0-4; EHCI, funct 5 */ - Package(){0x0012FFFF, 0, 0, 16 }, - Package(){0x0012FFFF, 1, 0, 17 }, - Package(){0x0013FFFF, 0, 0, 18 }, - Package(){0x0013FFFF, 1, 0, 19 }, - Package(){0x0014FFFF, 0, 0, 16 }, - /* Package(){0x00130004, 2, 0, 18 }, */ - /* Package(){0x00130005, 3, 0, 19 }, */ - - /* Bus 0, Dev 20 - F0:SMBus/ACPI, F1:IDE; F2:HDAudio; F3:LPC; F4:PCIBridge; F5:AC97 Audio; F6:AC97 Modem */ - Package(){0x0014FFFF, 0, 0, 16 }, - Package(){0x0014FFFF, 1, 0, 17 }, - Package(){0x0014FFFF, 2, 0, 18 }, - Package(){0x0014FFFF, 3, 0, 19 }, - /* Package(){0x00140004, 2, 0, 18 }, */ - /* Package(){0x00140004, 3, 0, 19 }, */ - /* Package(){0x00140005, 1, 0, 17 }, */ - /* Package(){0x00140006, 1, 0, 17 }, */ - }) - - Name(PR1, Package(){ - /* Internal graphics - RS780 VGA, Bus1, Dev5 */ - Package(){0x0005FFFF, 0, INTA, 0 }, - Package(){0x0005FFFF, 1, INTB, 0 }, - Package(){0x0005FFFF, 2, INTC, 0 }, - Package(){0x0005FFFF, 3, INTD, 0 }, - }) - - Name(APR1, Package(){ - /* Internal graphics - RS780 VGA, Bus1, Dev5 */ - Package(){0x0005FFFF, 0, 0, 18 }, - Package(){0x0005FFFF, 1, 0, 19 }, - /* Package(){0x0005FFFF, 2, 0, 20 }, */ - /* Package(){0x0005FFFF, 3, 0, 17 }, */ - }) - - Name(PS2, Package(){ - /* The external GFX - Hooked to PCIe slot 2 */ - Package(){0x0000FFFF, 0, INTC, 0 }, - Package(){0x0000FFFF, 1, INTD, 0 }, - Package(){0x0000FFFF, 2, INTA, 0 }, - Package(){0x0000FFFF, 3, INTB, 0 }, - }) - - Name(APS2, Package(){ - /* The external GFX - Hooked to PCIe slot 2 */ - Package(){0x0000FFFF, 0, 0, 18 }, - Package(){0x0000FFFF, 1, 0, 19 }, - Package(){0x0000FFFF, 2, 0, 16 }, - Package(){0x0000FFFF, 3, 0, 17 }, - }) - - Name(PS4, Package(){ - /* PCIe slot - Hooked to PCIe slot 4 */ - Package(){0x0000FFFF, 0, INTA, 0 }, - Package(){0x0000FFFF, 1, INTB, 0 }, - Package(){0x0000FFFF, 2, INTC, 0 }, - Package(){0x0000FFFF, 3, INTD, 0 }, - }) - - Name(APS4, Package(){ - /* PCIe slot - Hooked to PCIe slot 4 */ - Package(){0x0000FFFF, 0, 0, 16 }, - Package(){0x0000FFFF, 1, 0, 17 }, - Package(){0x0000FFFF, 2, 0, 18 }, - Package(){0x0000FFFF, 3, 0, 19 }, - }) - - Name(PS5, Package(){ - /* PCIe slot - Hooked to PCIe slot 5 */ - Package(){0x0000FFFF, 0, INTB, 0 }, - Package(){0x0000FFFF, 1, INTC, 0 }, - Package(){0x0000FFFF, 2, INTD, 0 }, - Package(){0x0000FFFF, 3, INTA, 0 }, - }) - - Name(APS5, Package(){ - /* PCIe slot - Hooked to PCIe slot 5 */ - Package(){0x0000FFFF, 0, 0, 17 }, - Package(){0x0000FFFF, 1, 0, 18 }, - Package(){0x0000FFFF, 2, 0, 19 }, - Package(){0x0000FFFF, 3, 0, 16 }, - }) - - Name(PS6, Package(){ - /* PCIe slot - Hooked to PCIe slot 6 */ - Package(){0x0000FFFF, 0, INTC, 0 }, - Package(){0x0000FFFF, 1, INTD, 0 }, - Package(){0x0000FFFF, 2, INTA, 0 }, - Package(){0x0000FFFF, 3, INTB, 0 }, - }) - - Name(APS6, Package(){ - /* PCIe slot - Hooked to PCIe slot 6 */ - Package(){0x0000FFFF, 0, 0, 18 }, - Package(){0x0000FFFF, 1, 0, 19 }, - Package(){0x0000FFFF, 2, 0, 16 }, - Package(){0x0000FFFF, 3, 0, 17 }, - }) - - Name(PS7, Package(){ - /* The onboard Ethernet chip - Hooked to PCIe slot 7 */ - Package(){0x0000FFFF, 0, INTD, 0 }, - Package(){0x0000FFFF, 1, INTA, 0 }, - Package(){0x0000FFFF, 2, INTB, 0 }, - Package(){0x0000FFFF, 3, INTC, 0 }, - }) - - Name(APS7, Package(){ - /* The onboard Ethernet chip - Hooked to PCIe slot 7 */ - Package(){0x0000FFFF, 0, 0, 19 }, - Package(){0x0000FFFF, 1, 0, 16 }, - Package(){0x0000FFFF, 2, 0, 17 }, - Package(){0x0000FFFF, 3, 0, 18 }, - }) - Name(PS9, Package(){ - /* PCIe slot - Hooked to PCIe slot 9 */ - Package(){0x0000FFFF, 0, INTD, 0 }, - Package(){0x0000FFFF, 1, INTA, 0 }, - Package(){0x0000FFFF, 2, INTB, 0 }, - Package(){0x0000FFFF, 3, INTC, 0 }, - }) - - Name(APS9, Package(){ - /* PCIe slot - Hooked to PCIe slot 9 */ - Package(){0x0000FFFF, 0, 0, 17 }, - Package(){0x0000FFFF, 1, 0, 18 }, - Package(){0x0000FFFF, 2, 0, 19 }, - Package(){0x0000FFFF, 3, 0, 16 }, - }) - Name(PSa, Package(){ - /* PCIe slot - Hooked to PCIe slot 10 */ - Package(){0x0000FFFF, 0, INTD, 0 }, - Package(){0x0000FFFF, 1, INTA, 0 }, - Package(){0x0000FFFF, 2, INTB, 0 }, - Package(){0x0000FFFF, 3, INTC, 0 }, - }) - - Name(APSa, Package(){ - /* PCIe slot - Hooked to PCIe slot 10 */ - Package(){0x0000FFFF, 0, 0, 18 }, - Package(){0x0000FFFF, 1, 0, 19 }, - Package(){0x0000FFFF, 2, 0, 16 }, - Package(){0x0000FFFF, 3, 0, 17 }, - }) - - Name(PCIB, Package(){ - /* PCI slots: slot 0, slot 1, slot 2 behind Dev14, Fun4. */ - Package(){0x0005FFFF, 0, 0, 0x14 }, - Package(){0x0005FFFF, 1, 0, 0x15 }, - Package(){0x0005FFFF, 2, 0, 0x16 }, - Package(){0x0005FFFF, 3, 0, 0x17 }, - Package(){0x0006FFFF, 0, 0, 0x15 }, - Package(){0x0006FFFF, 1, 0, 0x16 }, - Package(){0x0006FFFF, 2, 0, 0x17 }, - Package(){0x0006FFFF, 3, 0, 0x14 }, - Package(){0x0007FFFF, 0, 0, 0x16 }, - Package(){0x0007FFFF, 1, 0, 0x17 }, - Package(){0x0007FFFF, 2, 0, 0x14 }, - Package(){0x0007FFFF, 3, 0, 0x15 }, - }) -} diff --git a/src/mainboard/asus/m4a78-em/acpi/sata.asl b/src/mainboard/asus/m4a78-em/acpi/sata.asl deleted file mode 100644 index cb9b221ba3..0000000000 --- a/src/mainboard/asus/m4a78-em/acpi/sata.asl +++ /dev/null @@ -1,145 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2010 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -/* simple name description */ - -/* -Scope (_SB) { - Device(PCI0) { - Device(SATA) { - Name(_ADR, 0x00110000) - #include "sata.asl" - } - } -} -*/ - -Name(STTM, Buffer(20) { - 0x78, 0x00, 0x00, 0x00, 0x0f, 0x00, 0x00, 0x00, - 0x78, 0x00, 0x00, 0x00, 0x0f, 0x00, 0x00, 0x00, - 0x1f, 0x00, 0x00, 0x00 -}) - -/* Start by clearing the PhyRdyChg bits */ -Method(_INI) { - \_GPE._L1F() -} - -Device(PMRY) -{ - Name(_ADR, 0) - Method(_GTM, 0x0, NotSerialized) { - Return(STTM) - } - Method(_STM, 0x3, NotSerialized) {} - - Device(PMST) { - Name(_ADR, 0) - Method(_STA,0) { - if (LGreater(P0IS,0)) { - return (0x0F) /* sata is visible */ - } - else { - return (0x00) /* sata is missing */ - } - } - }/* end of PMST */ - - Device(PSLA) - { - Name(_ADR, 1) - Method(_STA,0) { - if (LGreater(P1IS,0)) { - return (0x0F) /* sata is visible */ - } - else { - return (0x00) /* sata is missing */ - } - } - } /* end of PSLA */ -} /* end of PMRY */ - - -Device(SEDY) -{ - Name(_ADR, 1) /* IDE Scondary Channel */ - Method(_GTM, 0x0, NotSerialized) { - Return(STTM) - } - Method(_STM, 0x3, NotSerialized) {} - - Device(SMST) - { - Name(_ADR, 0) - Method(_STA,0) { - if (LGreater(P2IS,0)) { - return (0x0F) /* sata is visible */ - } - else { - return (0x00) /* sata is missing */ - } - } - } /* end of SMST */ - - Device(SSLA) - { - Name(_ADR, 1) - Method(_STA,0) { - if (LGreater(P3IS,0)) { - return (0x0F) /* sata is visible */ - } - else { - return (0x00) /* sata is missing */ - } - } - } /* end of SSLA */ -} /* end of SEDY */ - -/* SATA Hot Plug Support */ -Scope(\_GPE) { - Method(_L1F,0x0,NotSerialized) { - if (\_SB.P0PR) { - if (LGreater(\_SB.P0IS,0)) { - sleep(32) - } - Notify(\_SB.PCI0.STCR.PMRY.PMST, 0x01) /* NOTIFY_DEVICE_CHECK */ - store(one, \_SB.P0PR) - } - - if (\_SB.P1PR) { - if (LGreater(\_SB.P1IS,0)) { - sleep(32) - } - Notify(\_SB.PCI0.STCR.PMRY.PSLA, 0x01) /* NOTIFY_DEVICE_CHECK */ - store(one, \_SB.P1PR) - } - - if (\_SB.P2PR) { - if (LGreater(\_SB.P2IS,0)) { - sleep(32) - } - Notify(\_SB.PCI0.STCR.SEDY.SMST, 0x01) /* NOTIFY_DEVICE_CHECK */ - store(one, \_SB.P2PR) - } - - if (\_SB.P3PR) { - if (LGreater(\_SB.P3IS,0)) { - sleep(32) - } - Notify(\_SB.PCI0.STCR.SEDY.SSLA, 0x01) /* NOTIFY_DEVICE_CHECK */ - store(one, \_SB.P3PR) - } - } -} diff --git a/src/mainboard/asus/m4a78-em/acpi/usb.asl b/src/mainboard/asus/m4a78-em/acpi/usb.asl deleted file mode 100644 index a3ccb97ff9..0000000000 --- a/src/mainboard/asus/m4a78-em/acpi/usb.asl +++ /dev/null @@ -1,158 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2010 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -/* simple name description */ -/* -#include -DefinitionBlock ("DSDT.AML", "DSDT", 0x01, OEM_ID, ACPI_TABLE_CREATOR, 0x00010001 - ) - { - #include "usb.asl" - } -*/ -Method(UCOC, 0) { - Sleep(20) - Store(0x13,CMTI) - Store(0,GPSL) -} - -/* USB Port 0 overcurrent uses Gpm 0 */ -If(LLessEqual(UOM0,9)) { - Scope (\_GPE) { - Method (_L13) { - UCOC() - if(LEqual(GPB0,PLC0)) { - Not(PLC0,PLC0) - Store(PLC0, \_SB.PT0D) - } - } - } -} - -/* USB Port 1 overcurrent uses Gpm 1 */ -If (LLessEqual(UOM1,9)) { - Scope (\_GPE) { - Method (_L14) { - UCOC() - if (LEqual(GPB1,PLC1)) { - Not(PLC1,PLC1) - Store(PLC1, \_SB.PT1D) - } - } - } -} - -/* USB Port 2 overcurrent uses Gpm 2 */ -If (LLessEqual(UOM2,9)) { - Scope (\_GPE) { - Method (_L15) { - UCOC() - if (LEqual(GPB2,PLC2)) { - Not(PLC2,PLC2) - Store(PLC2, \_SB.PT2D) - } - } - } -} - -/* USB Port 3 overcurrent uses Gpm 3 */ -If (LLessEqual(UOM3,9)) { - Scope (\_GPE) { - Method (_L16) { - UCOC() - if (LEqual(GPB3,PLC3)) { - Not(PLC3,PLC3) - Store(PLC3, \_SB.PT3D) - } - } - } -} - -/* USB Port 4 overcurrent uses Gpm 4 */ -If (LLessEqual(UOM4,9)) { - Scope (\_GPE) { - Method (_L19) { - UCOC() - if (LEqual(GPB4,PLC4)) { - Not(PLC4,PLC4) - Store(PLC4, \_SB.PT4D) - } - } - } -} - -/* USB Port 5 overcurrent uses Gpm 5 */ -If (LLessEqual(UOM5,9)) { - Scope (\_GPE) { - Method (_L1A) { - UCOC() - if (LEqual(GPB5,PLC5)) { - Not(PLC5,PLC5) - Store(PLC5, \_SB.PT5D) - } - } - } -} - -/* USB Port 6 overcurrent uses Gpm 6 */ -If (LLessEqual(UOM6,9)) { - Scope (\_GPE) { - /* Method (_L1C) { */ - Method (_L06) { - UCOC() - if (LEqual(GPB6,PLC6)) { - Not(PLC6,PLC6) - Store(PLC6, \_SB.PT6D) - } - } - } -} - -/* USB Port 7 overcurrent uses Gpm 7 */ -If (LLessEqual(UOM7,9)) { - Scope (\_GPE) { - /* Method (_L1D) { */ - Method (_L07) { - UCOC() - if (LEqual(GPB7,PLC7)) { - Not(PLC7,PLC7) - Store(PLC7, \_SB.PT7D) - } - } - } -} - -/* USB Port 8 overcurrent uses Gpm 8 */ -If (LLessEqual(UOM8,9)) { - Scope (\_GPE) { - Method (_L17) { - if (LEqual(G8IS,PLC8)) { - Not(PLC8,PLC8) - Store(PLC8, \_SB.PT8D) - } - } - } -} - -/* USB Port 9 overcurrent uses Gpm 9 */ -If (LLessEqual(UOM9,9)) { - Scope (\_GPE) { - Method (_L0E) { - if (LEqual(G9IS,0)) { - Store(1,\_SB.PT9D) - } - } - } -} diff --git a/src/mainboard/asus/m4a78-em/acpi_tables.c b/src/mainboard/asus/m4a78-em/acpi_tables.c deleted file mode 100644 index 967343da67..0000000000 --- a/src/mainboard/asus/m4a78-em/acpi_tables.c +++ /dev/null @@ -1,44 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2010 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include -#include - -unsigned long acpi_fill_madt(unsigned long current) -{ - /* create all subtables for processors */ - current = acpi_create_madt_lapics(current); - - /* Write SB700 IOAPIC, only one */ - current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, 2, - IO_APIC_ADDR, 0); - - current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) - current, 0, 0, 2, 0); - current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) - current, 0, 9, 9, 0xF); - /* 0: mean bus 0--->ISA */ - /* 0: PIC 0 */ - /* 2: APIC 2 */ - /* 5 mean: 0101 --> Edge-triggered, Active high */ - - /* create all subtables for processors */ - /* current = acpi_create_madt_lapic_nmis(current, 5, 1); */ - /* 1: LINT1 connect to NMI */ - - return current; -} diff --git a/src/mainboard/asus/m4a78-em/board_info.txt b/src/mainboard/asus/m4a78-em/board_info.txt deleted file mode 100644 index 981255e1ce..0000000000 --- a/src/mainboard/asus/m4a78-em/board_info.txt +++ /dev/null @@ -1,7 +0,0 @@ -Category: desktop -Board URL: http://www.asus.com/Motherboards/AMD_AM2Plus/M4A78EM/ -ROM package: DIP8 -ROM protocol: SPI -ROM socketed: y -Flashrom support: y -Release year: 2009 diff --git a/src/mainboard/asus/m4a78-em/cmos.layout b/src/mainboard/asus/m4a78-em/cmos.layout deleted file mode 100644 index 6c3d3f6c9e..0000000000 --- a/src/mainboard/asus/m4a78-em/cmos.layout +++ /dev/null @@ -1,52 +0,0 @@ -entries - -0 384 r 0 reserved_memory -384 1 e 4 boot_option -388 4 h 0 reboot_counter -#392 3 r 0 unused -395 1 e 1 hw_scrubber -396 1 e 1 interleave_chip_selects -397 2 e 8 max_mem_clock -399 1 e 2 multi_core -400 1 e 1 power_on_after_fail -412 4 e 6 debug_level -440 4 e 9 slow_cpu -444 1 e 1 nmi -445 1 e 1 gart -456 1 e 1 ECC_memory -728 256 h 0 user_data -984 16 h 0 check_sum -# Reserve the extended AMD configuration registers -1000 24 r 0 amd_reserved - - - -enumerations - -#ID value text -1 0 Disable -1 1 Enable -2 0 Enable -2 1 Disable -4 0 Fallback -4 1 Normal -6 5 Notice -6 6 Info -6 7 Debug -6 8 Spew -8 0 400Mhz -8 1 333Mhz -8 2 266Mhz -8 3 200Mhz -9 0 off -9 1 87.5% -9 2 75.0% -9 3 62.5% -9 4 50.0% -9 5 37.5% -9 6 25.0% -9 7 12.5% - -checksums - -checksum 392 983 984 diff --git a/src/mainboard/asus/m4a78-em/devicetree.cb b/src/mainboard/asus/m4a78-em/devicetree.cb deleted file mode 100644 index f336c2bd82..0000000000 --- a/src/mainboard/asus/m4a78-em/devicetree.cb +++ /dev/null @@ -1,106 +0,0 @@ -chip northbridge/amd/amdfam10/root_complex - device cpu_cluster 0 on - chip cpu/amd/socket_AM3 #L1 and DDR2 - device lapic 0 on end - end - end - device domain 0 on - subsystemid 0x1043 0x83f1 inherit - chip northbridge/amd/amdfam10 - device pci 18.0 on # northbridge - chip southbridge/amd/rs780 - device pci 0.0 on end # HT 0x9600 - device pci 1.0 on end # Internal Graphics P2P bridge 0x9602 - device pci 2.0 on end # PCIE P2P bridge (external graphics) 0x9603 - device pci 3.0 on end # PCIE P2P bridge 0x960b - device pci 4.0 on end # PCIE P2P bridge 0x9604 - device pci 5.0 off end # PCIE P2P bridge 0x9605 - device pci 6.0 off end # PCIE P2P bridge 0x9606 - device pci 7.0 off end # PCIE P2P bridge 0x9607 - device pci 8.0 off end # NB/SB Link P2P bridge - device pci 9.0 on end # - device pci a.0 on end # bridge to RTL8112 PCI Express Gigabit Ethernet - register "gppsb_configuration" = "1" # Configuration B - register "gpp_configuration" = "3" # Configuration D default - register "port_enable" = "0x6fc" - register "gfx_dev2_dev3" = "1" - register "gfx_dual_slot" = "2" - - register "gfx_lane_reversal" = "0" - register "gfx_tmds" = "0" - register "gfx_compliance" = "0" - register "gfx_reconfiguration" = "1" - register "gfx_link_width" = "0" - end - chip southbridge/amd/sb700 # it is under NB/SB Link, but on the same pri bus - device pci 11.0 on end # SATA - device pci 12.0 on end # USB - device pci 12.1 on end # USB - device pci 12.2 on end # USB - device pci 13.0 on end # USB - device pci 13.1 on end # USB - device pci 13.2 on end # USB - device pci 14.0 on # SM - chip drivers/generic/generic #dimm 0-0-0 - device i2c 50 on end - end - chip drivers/generic/generic #dimm 0-0-1 - device i2c 51 on end - end - chip drivers/generic/generic #dimm 0-1-0 - device i2c 52 on end - end - chip drivers/generic/generic #dimm 0-1-1 - device i2c 53 on end - end - end # SM - device pci 14.1 on end # IDE 0x439c - device pci 14.2 on end # HDA 0x4383 - device pci 14.3 on # LPC 0x439d - chip superio/ite/it8712f - device pnp 2e.0 off end # Floppy - device pnp 2e.1 on # Com1 - io 0x60 = 0x3f8 - irq 0x70 = 4 - end - device pnp 2e.2 off # Com2 - io 0x60 = 0x2f8 - irq 0x70 = 3 - end - device pnp 2e.3 off # Parallel Port - io 0x60 = 0x378 - irq 0x70 = 7 - end - device pnp 2e.4 off end # Environment Controller - device pnp 2e.5 on # Keyboard - io 0x60 = 0x60 - io 0x62 = 0x64 - irq 0x70 = 1 - end - device pnp 2e.6 on # Mouse - irq 0x70 = 12 - end - device pnp 2e.7 off # GPIO, must be closed for unresolved reason. - end - device pnp 2e.8 off # MIDI - end - device pnp 2e.9 off # GAME - end - device pnp 2e.a off end # CIR - end #superio - end #LPC - device pci 14.4 on end # PCI to PCI Bridge [1002:4384] - device pci 14.5 on end # USB 2 - register "boot_switch_sata_ide" = "0" # 0: boot from SATA. 1: IDE - end #southbridge/amd/sb700 - end # device pci 18.0 - - device pci 18.0 on end - device pci 18.0 on end - device pci 18.1 on end - device pci 18.2 on end - device pci 18.3 on end - device pci 18.4 on end - end # chip northbridge - end #domain -end # northbridge/amd/amdfam10/root_complex diff --git a/src/mainboard/asus/m4a78-em/dsdt.asl b/src/mainboard/asus/m4a78-em/dsdt.asl deleted file mode 100644 index eec3093b8e..0000000000 --- a/src/mainboard/asus/m4a78-em/dsdt.asl +++ /dev/null @@ -1,1718 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2010 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -/* DefinitionBlock Statement */ -#include -DefinitionBlock ( - "DSDT.AML", /* Output filename */ - "DSDT", /* Signature */ - 0x02, /* DSDT Revision, needs to be 2 for 64bit */ - OEM_ID, - ACPI_TABLE_CREATOR, - 0x00010001 /* OEM Revision */ - ) -{ /* Start of ASL file */ - /* #include */ /* Include global debug methods if needed */ - - /* Data to be patched by the BIOS during POST */ - /* FIXME the patching is not done yet! */ - /* Memory related values */ - Name(LOMH, 0x0) /* Start of unused memory in C0000-E0000 range */ - Name(PBAD, 0x0) /* Address of BIOS area (If TOM2 != 0, Addr >> 16) */ - Name(PBLN, 0x0) /* Length of BIOS area */ - - Name(PCBA, 0xE0000000) /* Base address of PCIe config space */ - Name(HPBA, 0xFED00000) /* Base address of HPET table */ - - /* USB overcurrent mapping pins. */ - Name(UOM0, 0) - Name(UOM1, 2) - Name(UOM2, 0) - Name(UOM3, 7) - Name(UOM4, 2) - Name(UOM5, 2) - Name(UOM6, 6) - Name(UOM7, 2) - Name(UOM8, 6) - Name(UOM9, 6) - - /* Some global data */ - Name(OSVR, 3) /* Assume nothing. WinXp = 1, Vista = 2, Linux = 3, WinCE = 4 */ - Name(OSV, Ones) /* Assume nothing */ - Name(PMOD, One) /* Assume APIC */ - - /* - * Processor Object - * - */ - Scope (\_PR) { /* define processor scope */ - Device (CPU0) { - Name (_HID, "ACPI0007") - Name (_UID, 0) - #include "acpi/cpstate.asl" - } - Device (CPU1) { - Name (_HID, "ACPI0007") - Name (_UID, 1) - #include "acpi/cpstate.asl" - } - Device (CPU2) { - Name (_HID, "ACPI0007") - Name (_UID, 2) - #include "acpi/cpstate.asl" - } - Device (CPU3) { - Name (_HID, "ACPI0007") - Name (_UID, 3) - #include "acpi/cpstate.asl" - } - } /* End _PR scope */ - - /* PIC IRQ mapping registers, C00h-C01h */ - OperationRegion(PRQM, SystemIO, 0x00000C00, 0x00000002) - Field(PRQM, ByteAcc, NoLock, Preserve) { - PRQI, 0x00000008, - PRQD, 0x00000008, /* Offset: 1h */ - } - IndexField(PRQI, PRQD, ByteAcc, NoLock, Preserve) { - PINA, 0x00000008, /* Index 0 */ - PINB, 0x00000008, /* Index 1 */ - PINC, 0x00000008, /* Index 2 */ - PIND, 0x00000008, /* Index 3 */ - AINT, 0x00000008, /* Index 4 */ - SINT, 0x00000008, /* Index 5 */ - , 0x00000008, /* Index 6 */ - AAUD, 0x00000008, /* Index 7 */ - AMOD, 0x00000008, /* Index 8 */ - PINE, 0x00000008, /* Index 9 */ - PINF, 0x00000008, /* Index A */ - PING, 0x00000008, /* Index B */ - PINH, 0x00000008, /* Index C */ - } - - /* PCI Error control register */ - OperationRegion(PERC, SystemIO, 0x00000C14, 0x00000001) - Field(PERC, ByteAcc, NoLock, Preserve) { - SENS, 0x00000001, - PENS, 0x00000001, - SENE, 0x00000001, - PENE, 0x00000001, - } - - /* Client Management index/data registers */ - OperationRegion(CMT, SystemIO, 0x00000C50, 0x00000002) - Field(CMT, ByteAcc, NoLock, Preserve) { - CMTI, 8, - /* Client Management Data register */ - G64E, 1, - G64O, 1, - G32O, 2, - , 2, - GPSL, 2, - } - - /* GPM Port register */ - OperationRegion(GPT, SystemIO, 0x00000C52, 0x00000001) - Field(GPT, ByteAcc, NoLock, Preserve) { - GPB0,1, - GPB1,1, - GPB2,1, - GPB3,1, - GPB4,1, - GPB5,1, - GPB6,1, - GPB7,1, - } - - /* Flash ROM program enable register */ - OperationRegion(FRE, SystemIO, 0x00000C6F, 0x00000001) - Field(FRE, ByteAcc, NoLock, Preserve) { - , 0x00000006, - FLRE, 0x00000001, - } - - /* PM2 index/data registers */ - OperationRegion(PM2R, SystemIO, 0x00000CD0, 0x00000002) - Field(PM2R, ByteAcc, NoLock, Preserve) { - PM2I, 0x00000008, - PM2D, 0x00000008, - } - - /* Power Management I/O registers */ - OperationRegion(PIOR, SystemIO, 0x00000CD6, 0x00000002) - Field(PIOR, ByteAcc, NoLock, Preserve) { - PIOI, 0x00000008, - PIOD, 0x00000008, - } - IndexField (PIOI, PIOD, ByteAcc, NoLock, Preserve) { - Offset(0x00), /* MiscControl */ - , 1, - T1EE, 1, - T2EE, 1, - Offset(0x01), /* MiscStatus */ - , 1, - T1E, 1, - T2E, 1, - Offset(0x04), /* SmiWakeUpEventEnable3 */ - , 7, - SSEN, 1, - Offset(0x07), /* SmiWakeUpEventStatus3 */ - , 7, - CSSM, 1, - Offset(0x10), /* AcpiEnable */ - , 6, - PWDE, 1, - Offset(0x1C), /* ProgramIoEnable */ - , 3, - MKME, 1, - IO3E, 1, - IO2E, 1, - IO1E, 1, - IO0E, 1, - Offset(0x1D), /* IOMonitorStatus */ - , 3, - MKMS, 1, - IO3S, 1, - IO2S, 1, - IO1S, 1, - IO0S,1, - Offset(0x20), /* AcpiPmEvtBlk */ - APEB, 16, - Offset(0x36), /* GEvtLevelConfig */ - , 6, - ELC6, 1, - ELC7, 1, - Offset(0x37), /* GPMLevelConfig0 */ - , 3, - PLC0, 1, - PLC1, 1, - PLC2, 1, - PLC3, 1, - PLC8, 1, - Offset(0x38), /* GPMLevelConfig1 */ - , 1, - PLC4, 1, - PLC5, 1, - , 1, - PLC6, 1, - PLC7, 1, - Offset(0x3B), /* PMEStatus1 */ - GP0S, 1, - GM4S, 1, - GM5S, 1, - APS, 1, - GM6S, 1, - GM7S, 1, - GP2S, 1, - STSS, 1, - Offset(0x55), /* SoftPciRst */ - SPRE, 1, - , 1, - , 1, - PNAT, 1, - PWMK, 1, - PWNS, 1, - - /* Offset(0x61), */ /* Options_1 */ - /* ,7, */ - /* R617,1, */ - - Offset(0x65), /* UsbPMControl */ - , 4, - URRE, 1, - Offset(0x68), /* MiscEnable68 */ - , 3, - TMTE, 1, - , 1, - Offset(0x92), /* GEVENTIN */ - , 7, - E7IS, 1, - Offset(0x96), /* GPM98IN */ - G8IS, 1, - G9IS, 1, - Offset(0x9A), /* EnhanceControl */ - ,7, - HPDE, 1, - Offset(0xA8), /* PIO7654Enable */ - IO4E, 1, - IO5E, 1, - IO6E, 1, - IO7E, 1, - Offset(0xA9), /* PIO7654Status */ - IO4S, 1, - IO5S, 1, - IO6S, 1, - IO7S, 1, - } - - /* PM1 Event Block - * First word is PM1_Status, Second word is PM1_Enable - */ - OperationRegion(P1EB, SystemIO, APEB, 0x04) - Field(P1EB, ByteAcc, NoLock, Preserve) { - TMST, 1, - , 3, - BMST, 1, - GBST, 1, - Offset(0x01), - PBST, 1, - , 1, - RTST, 1, - , 3, - PWST, 1, - SPWS, 1, - Offset(0x02), - TMEN, 1, - , 4, - GBEN, 1, - Offset(0x03), - PBEN, 1, - , 1, - RTEN, 1, - , 3, - PWDA, 1, - } - - Scope(\_SB) { - /* PCIe Configuration Space for 16 busses */ - OperationRegion(PCFG, SystemMemory, PCBA, 0x01000000) /* Each bus consumes 1MB */ - Field(PCFG, ByteAcc, NoLock, Preserve) { - /* Byte offsets are computed using the following technique: - * ((bus number + 1) * ((device number * 8) * 4096)) + register offset - * The 8 comes from 8 functions per device, and 4096 bytes per function config space - */ - Offset(0x00088024), /* Byte offset to SATA register 24h - Bus 0, Device 17, Function 0 */ - STB5, 32, - Offset(0x00098042), /* Byte offset to OHCI0 register 42h - Bus 0, Device 19, Function 0 */ - PT0D, 1, - PT1D, 1, - PT2D, 1, - PT3D, 1, - PT4D, 1, - PT5D, 1, - PT6D, 1, - PT7D, 1, - PT8D, 1, - PT9D, 1, - Offset(0x000A0004), /* Byte offset to SMBUS register 4h - Bus 0, Device 20, Function 0 */ - SBIE, 1, - SBME, 1, - Offset(0x000A0008), /* Byte offset to SMBUS register 8h - Bus 0, Device 20, Function 0 */ - SBRI, 8, - Offset(0x000A0014), /* Byte offset to SMBUS register 14h - Bus 0, Device 20, Function 0 */ - SBB1, 32, - Offset(0x000A0078), /* Byte offset to SMBUS register 78h - Bus 0, Device 20, Function 0 */ - ,14, - P92E, 1, /* Port92 decode enable */ - } - - OperationRegion(SB5, SystemMemory, STB5, 0x1000) - Field(SB5, AnyAcc, NoLock, Preserve){ - /* Port 0 */ - Offset(0x120), /* Port 0 Task file status */ - P0ER, 1, - , 2, - P0DQ, 1, - , 3, - P0BY, 1, - Offset(0x128), /* Port 0 Serial ATA status */ - P0DD, 4, - , 4, - P0IS, 4, - Offset(0x12C), /* Port 0 Serial ATA control */ - P0DI, 4, - Offset(0x130), /* Port 0 Serial ATA error */ - , 16, - P0PR, 1, - - /* Port 1 */ - offset(0x1A0), /* Port 1 Task file status */ - P1ER, 1, - , 2, - P1DQ, 1, - , 3, - P1BY, 1, - Offset(0x1A8), /* Port 1 Serial ATA status */ - P1DD, 4, - , 4, - P1IS, 4, - Offset(0x1AC), /* Port 1 Serial ATA control */ - P1DI, 4, - Offset(0x1B0), /* Port 1 Serial ATA error */ - , 16, - P1PR, 1, - - /* Port 2 */ - Offset(0x220), /* Port 2 Task file status */ - P2ER, 1, - , 2, - P2DQ, 1, - , 3, - P2BY, 1, - Offset(0x228), /* Port 2 Serial ATA status */ - P2DD, 4, - , 4, - P2IS, 4, - Offset(0x22C), /* Port 2 Serial ATA control */ - P2DI, 4, - Offset(0x230), /* Port 2 Serial ATA error */ - , 16, - P2PR, 1, - - /* Port 3 */ - Offset(0x2A0), /* Port 3 Task file status */ - P3ER, 1, - , 2, - P3DQ, 1, - , 3, - P3BY, 1, - Offset(0x2A8), /* Port 3 Serial ATA status */ - P3DD, 4, - , 4, - P3IS, 4, - Offset(0x2AC), /* Port 3 Serial ATA control */ - P3DI, 4, - Offset(0x2B0), /* Port 3 Serial ATA error */ - , 16, - P3PR, 1, - } - } - - - #include "acpi/routing.asl" - - Scope(\_SB) { - - Method(OSFL, 0){ - - if(LNotEqual(OSVR, Ones)) {Return(OSVR)} /* OS version was already detected */ - - if(CondRefOf(\_OSI)) - { - Store(1, OSVR) /* Assume some form of XP */ - if (\_OSI("Windows 2006")) /* Vista */ - { - Store(2, OSVR) - } - } else { - If(WCMP(\_OS,"Linux")) { - Store(3, OSVR) /* Linux */ - } Else { - Store(4, OSVR) /* Gotta be WinCE */ - } - } - Return(OSVR) - } - - Method(_PIC, 0x01, NotSerialized) - { - If (Arg0) - { - \_SB.CIRQ() - } - Store(Arg0, PMOD) - } - Method(CIRQ, 0x00, NotSerialized){ - Store(0, PINA) - Store(0, PINB) - Store(0, PINC) - Store(0, PIND) - Store(0, PINE) - Store(0, PINF) - Store(0, PING) - Store(0, PINH) - } - - Name(IRQB, ResourceTemplate(){ - IRQ(Level,ActiveLow,Shared){15} - }) - - Name(IRQP, ResourceTemplate(){ - IRQ(Level,ActiveLow,Exclusive){3, 4, 5, 7, 10, 11, 12, 15} - }) - - Name(PITF, ResourceTemplate(){ - IRQ(Level,ActiveLow,Exclusive){9} - }) - - Device(INTA) { - Name(_HID, EISAID("PNP0C0F")) - Name(_UID, 1) - - Method(_STA, 0) { - if (PINA) { - Return(0x0B) /* sata is invisible */ - } else { - Return(0x09) /* sata is disabled */ - } - } /* End Method(_SB.INTA._STA) */ - - Method(_DIS ,0) { - /* DBGO("\\_SB\\LNKA\\_DIS\n") */ - Store(0, PINA) - } /* End Method(_SB.INTA._DIS) */ - - Method(_PRS ,0) { - /* DBGO("\\_SB\\LNKA\\_PRS\n") */ - Return(IRQP) - } /* Method(_SB.INTA._PRS) */ - - Method(_CRS ,0) { - /* DBGO("\\_SB\\LNKA\\_CRS\n") */ - CreateWordField(IRQB, 0x1, IRQN) - ShiftLeft(1, PINA, IRQN) - Return(IRQB) - } /* Method(_SB.INTA._CRS) */ - - Method(_SRS, 1) { - /* DBGO("\\_SB\\LNKA\\_CRS\n") */ - CreateWordField(ARG0, 1, IRQM) - - /* Use lowest available IRQ */ - FindSetRightBit(IRQM, Local0) - if (Local0) { - Decrement(Local0) - } - Store(Local0, PINA) - } /* End Method(_SB.INTA._SRS) */ - } /* End Device(INTA) */ - - Device(INTB) { - Name(_HID, EISAID("PNP0C0F")) - Name(_UID, 2) - - Method(_STA, 0) { - if (PINB) { - Return(0x0B) /* sata is invisible */ - } else { - Return(0x09) /* sata is disabled */ - } - } /* End Method(_SB.INTB._STA) */ - - Method(_DIS ,0) { - /* DBGO("\\_SB\\LNKB\\_DIS\n") */ - Store(0, PINB) - } /* End Method(_SB.INTB._DIS) */ - - Method(_PRS ,0) { - /* DBGO("\\_SB\\LNKB\\_PRS\n") */ - Return(IRQP) - } /* Method(_SB.INTB._PRS) */ - - Method(_CRS ,0) { - /* DBGO("\\_SB\\LNKB\\_CRS\n") */ - CreateWordField(IRQB, 0x1, IRQN) - ShiftLeft(1, PINB, IRQN) - Return(IRQB) - } /* Method(_SB.INTB._CRS) */ - - Method(_SRS, 1) { - /* DBGO("\\_SB\\LNKB\\_CRS\n") */ - CreateWordField(ARG0, 1, IRQM) - - /* Use lowest available IRQ */ - FindSetRightBit(IRQM, Local0) - if (Local0) { - Decrement(Local0) - } - Store(Local0, PINB) - } /* End Method(_SB.INTB._SRS) */ - } /* End Device(INTB) */ - - Device(INTC) { - Name(_HID, EISAID("PNP0C0F")) - Name(_UID, 3) - - Method(_STA, 0) { - if (PINC) { - Return(0x0B) /* sata is invisible */ - } else { - Return(0x09) /* sata is disabled */ - } - } /* End Method(_SB.INTC._STA) */ - - Method(_DIS ,0) { - /* DBGO("\\_SB\\LNKC\\_DIS\n") */ - Store(0, PINC) - } /* End Method(_SB.INTC._DIS) */ - - Method(_PRS ,0) { - /* DBGO("\\_SB\\LNKC\\_PRS\n") */ - Return(IRQP) - } /* Method(_SB.INTC._PRS) */ - - Method(_CRS ,0) { - /* DBGO("\\_SB\\LNKC\\_CRS\n") */ - CreateWordField(IRQB, 0x1, IRQN) - ShiftLeft(1, PINC, IRQN) - Return(IRQB) - } /* Method(_SB.INTC._CRS) */ - - Method(_SRS, 1) { - /* DBGO("\\_SB\\LNKC\\_CRS\n") */ - CreateWordField(ARG0, 1, IRQM) - - /* Use lowest available IRQ */ - FindSetRightBit(IRQM, Local0) - if (Local0) { - Decrement(Local0) - } - Store(Local0, PINC) - } /* End Method(_SB.INTC._SRS) */ - } /* End Device(INTC) */ - - Device(INTD) { - Name(_HID, EISAID("PNP0C0F")) - Name(_UID, 4) - - Method(_STA, 0) { - if (PIND) { - Return(0x0B) /* sata is invisible */ - } else { - Return(0x09) /* sata is disabled */ - } - } /* End Method(_SB.INTD._STA) */ - - Method(_DIS ,0) { - /* DBGO("\\_SB\\LNKD\\_DIS\n") */ - Store(0, PIND) - } /* End Method(_SB.INTD._DIS) */ - - Method(_PRS ,0) { - /* DBGO("\\_SB\\LNKD\\_PRS\n") */ - Return(IRQP) - } /* Method(_SB.INTD._PRS) */ - - Method(_CRS ,0) { - /* DBGO("\\_SB\\LNKD\\_CRS\n") */ - CreateWordField(IRQB, 0x1, IRQN) - ShiftLeft(1, PIND, IRQN) - Return(IRQB) - } /* Method(_SB.INTD._CRS) */ - - Method(_SRS, 1) { - /* DBGO("\\_SB\\LNKD\\_CRS\n") */ - CreateWordField(ARG0, 1, IRQM) - - /* Use lowest available IRQ */ - FindSetRightBit(IRQM, Local0) - if (Local0) { - Decrement(Local0) - } - Store(Local0, PIND) - } /* End Method(_SB.INTD._SRS) */ - } /* End Device(INTD) */ - - Device(INTE) { - Name(_HID, EISAID("PNP0C0F")) - Name(_UID, 5) - - Method(_STA, 0) { - if (PINE) { - Return(0x0B) /* sata is invisible */ - } else { - Return(0x09) /* sata is disabled */ - } - } /* End Method(_SB.INTE._STA) */ - - Method(_DIS ,0) { - /* DBGO("\\_SB\\LNKE\\_DIS\n") */ - Store(0, PINE) - } /* End Method(_SB.INTE._DIS) */ - - Method(_PRS ,0) { - /* DBGO("\\_SB\\LNKE\\_PRS\n") */ - Return(IRQP) - } /* Method(_SB.INTE._PRS) */ - - Method(_CRS ,0) { - /* DBGO("\\_SB\\LNKE\\_CRS\n") */ - CreateWordField(IRQB, 0x1, IRQN) - ShiftLeft(1, PINE, IRQN) - Return(IRQB) - } /* Method(_SB.INTE._CRS) */ - - Method(_SRS, 1) { - /* DBGO("\\_SB\\LNKE\\_CRS\n") */ - CreateWordField(ARG0, 1, IRQM) - - /* Use lowest available IRQ */ - FindSetRightBit(IRQM, Local0) - if (Local0) { - Decrement(Local0) - } - Store(Local0, PINE) - } /* End Method(_SB.INTE._SRS) */ - } /* End Device(INTE) */ - - Device(INTF) { - Name(_HID, EISAID("PNP0C0F")) - Name(_UID, 6) - - Method(_STA, 0) { - if (PINF) { - Return(0x0B) /* sata is invisible */ - } else { - Return(0x09) /* sata is disabled */ - } - } /* End Method(_SB.INTF._STA) */ - - Method(_DIS ,0) { - /* DBGO("\\_SB\\LNKF\\_DIS\n") */ - Store(0, PINF) - } /* End Method(_SB.INTF._DIS) */ - - Method(_PRS ,0) { - /* DBGO("\\_SB\\LNKF\\_PRS\n") */ - Return(PITF) - } /* Method(_SB.INTF._PRS) */ - - Method(_CRS ,0) { - /* DBGO("\\_SB\\LNKF\\_CRS\n") */ - CreateWordField(IRQB, 0x1, IRQN) - ShiftLeft(1, PINF, IRQN) - Return(IRQB) - } /* Method(_SB.INTF._CRS) */ - - Method(_SRS, 1) { - /* DBGO("\\_SB\\LNKF\\_CRS\n") */ - CreateWordField(ARG0, 1, IRQM) - - /* Use lowest available IRQ */ - FindSetRightBit(IRQM, Local0) - if (Local0) { - Decrement(Local0) - } - Store(Local0, PINF) - } /* End Method(_SB.INTF._SRS) */ - } /* End Device(INTF) */ - - Device(INTG) { - Name(_HID, EISAID("PNP0C0F")) - Name(_UID, 7) - - Method(_STA, 0) { - if (PING) { - Return(0x0B) /* sata is invisible */ - } else { - Return(0x09) /* sata is disabled */ - } - } /* End Method(_SB.INTG._STA) */ - - Method(_DIS ,0) { - /* DBGO("\\_SB\\LNKG\\_DIS\n") */ - Store(0, PING) - } /* End Method(_SB.INTG._DIS) */ - - Method(_PRS ,0) { - /* DBGO("\\_SB\\LNKG\\_PRS\n") */ - Return(IRQP) - } /* Method(_SB.INTG._CRS) */ - - Method(_CRS ,0) { - /* DBGO("\\_SB\\LNKG\\_CRS\n") */ - CreateWordField(IRQB, 0x1, IRQN) - ShiftLeft(1, PING, IRQN) - Return(IRQB) - } /* Method(_SB.INTG._CRS) */ - - Method(_SRS, 1) { - /* DBGO("\\_SB\\LNKG\\_CRS\n") */ - CreateWordField(ARG0, 1, IRQM) - - /* Use lowest available IRQ */ - FindSetRightBit(IRQM, Local0) - if (Local0) { - Decrement(Local0) - } - Store(Local0, PING) - } /* End Method(_SB.INTG._SRS) */ - } /* End Device(INTG) */ - - Device(INTH) { - Name(_HID, EISAID("PNP0C0F")) - Name(_UID, 8) - - Method(_STA, 0) { - if (PINH) { - Return(0x0B) /* sata is invisible */ - } else { - Return(0x09) /* sata is disabled */ - } - } /* End Method(_SB.INTH._STA) */ - - Method(_DIS ,0) { - /* DBGO("\\_SB\\LNKH\\_DIS\n") */ - Store(0, PINH) - } /* End Method(_SB.INTH._DIS) */ - - Method(_PRS ,0) { - /* DBGO("\\_SB\\LNKH\\_PRS\n") */ - Return(IRQP) - } /* Method(_SB.INTH._CRS) */ - - Method(_CRS ,0) { - /* DBGO("\\_SB\\LNKH\\_CRS\n") */ - CreateWordField(IRQB, 0x1, IRQN) - ShiftLeft(1, PINH, IRQN) - Return(IRQB) - } /* Method(_SB.INTH._CRS) */ - - Method(_SRS, 1) { - /* DBGO("\\_SB\\LNKH\\_CRS\n") */ - CreateWordField(ARG0, 1, IRQM) - - /* Use lowest available IRQ */ - FindSetRightBit(IRQM, Local0) - if (Local0) { - Decrement(Local0) - } - Store(Local0, PINH) - } /* End Method(_SB.INTH._SRS) */ - } /* End Device(INTH) */ - - } /* End Scope(_SB) */ - - #include - - /* Wake status package */ - Name(WKST,Package(){Zero, Zero}) - - /* - * \_PTS - Prepare to Sleep method - * - * Entry: - * Arg0=The value of the sleeping state S1=1, S2=2, etc - * - * Exit: - * -none- - * - * The _PTS control method is executed at the beginning of the sleep process - * for S1-S5. The sleeping value is passed to the _PTS control method. This - * control method may be executed a relatively long time before entering the - * sleep state and the OS may abort the operation without notification to - * the ACPI driver. This method cannot modify the configuration or power - * state of any device in the system. - */ - Method(\_PTS, 1) { - /* DBGO("\\_PTS\n") */ - /* DBGO("From S0 to S") */ - /* DBGO(Arg0) */ - /* DBGO("\n") */ - - /* Don't allow PCIRST# to reset USB */ - if (LEqual(Arg0,3)){ - Store(0,URRE) - } - - /* Clear sleep SMI status flag and enable sleep SMI trap. */ - /*Store(One, CSSM) - Store(One, SSEN)*/ - - /* On older chips, clear PciExpWakeDisEn */ - /*if (LLessEqual(\_SB.SBRI, 0x13)) { - * Store(0,\_SB.PWDE) - *} - */ - - /* Clear wake status structure. */ - Store(0, Index(WKST,0)) - Store(0, Index(WKST,1)) - \_SB.PCI0.SIOS (Arg0) - } /* End Method(\_PTS) */ - - /* - * The following method results in a "not a valid reserved NameSeg" - * warning so I have commented it out for the duration. It isn't - * used, so it could be removed. - * - * - * \_GTS OEM Going To Sleep method - * - * Entry: - * Arg0=The value of the sleeping state S1=1, S2=2 - * - * Exit: - * -none- - * - * Method(\_GTS, 1) { - * DBGO("\\_GTS\n") - * DBGO("From S0 to S") - * DBGO(Arg0) - * DBGO("\n") - * } - */ - - /* - * \_BFS OEM Back From Sleep method - * - * Entry: - * Arg0=The value of the sleeping state S1=1, S2=2 - * - * Exit: - * -none- - */ - Method(\_BFS, 1) { - /* DBGO("\\_BFS\n") */ - /* DBGO("From S") */ - /* DBGO(Arg0) */ - /* DBGO(" to S0\n") */ - } - - /* - * \_WAK System Wake method - * - * Entry: - * Arg0=The value of the sleeping state S1=1, S2=2 - * - * Exit: - * Return package of 2 DWords - * Dword 1 - Status - * 0x00000000 wake succeeded - * 0x00000001 Wake was signaled but failed due to lack of power - * 0x00000002 Wake was signaled but failed due to thermal condition - * Dword 2 - Power Supply state - * if non-zero the effective S-state the power supply entered - */ - Method(\_WAK, 1) { - /* DBGO("\\_WAK\n") */ - /* DBGO("From S") */ - /* DBGO(Arg0) */ - /* DBGO(" to S0\n") */ - - /* Re-enable HPET */ - Store(1,HPDE) - - /* Restore PCIRST# so it resets USB */ - if (LEqual(Arg0,3)){ - Store(1,URRE) - } - - /* Arbitrarily clear PciExpWakeStatus */ - Store(PWST, Local1) - Store(Local1, PWST) - - /* if (DeRefOf(Index(WKST,0))) { - * Store(0, Index(WKST,1)) - * } else { - * Store(Arg0, Index(WKST,1)) - * } - */ - \_SB.PCI0.SIOW () - Return(WKST) - } /* End Method(\_WAK) */ - - Scope(\_GPE) { /* Start Scope GPE */ - /* General event 0 */ - /* Method(_L00) { - * DBGO("\\_GPE\\_L00\n") - * } - */ - - /* General event 1 */ - /* Method(_L01) { - * DBGO("\\_GPE\\_L00\n") - * } - */ - - /* General event 2 */ - /* Method(_L02) { - * DBGO("\\_GPE\\_L00\n") - * } - */ - - /* General event 3 */ - Method(_L03) { - /* DBGO("\\_GPE\\_L00\n") */ - Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ - } - - /* General event 4 */ - /* Method(_L04) { - * DBGO("\\_GPE\\_L00\n") - * } - */ - - /* General event 5 */ - /* Method(_L05) { - * DBGO("\\_GPE\\_L00\n") - * } - */ - - /* General event 6 - Used for GPM6, moved to USB.asl */ - /* Method(_L06) { - * DBGO("\\_GPE\\_L00\n") - * } - */ - - /* General event 7 - Used for GPM7, moved to USB.asl */ - /* Method(_L07) { - * DBGO("\\_GPE\\_L07\n") - * } - */ - - /* Legacy PM event */ - Method(_L08) { - /* DBGO("\\_GPE\\_L08\n") */ - } - - /* Temp warning (TWarn) event */ - Method(_L09) { - /* DBGO("\\_GPE\\_L09\n") */ - Notify (\_TZ.TZ00, 0x80) - } - - /* Reserved */ - /* Method(_L0A) { - * DBGO("\\_GPE\\_L0A\n") - * } - */ - - /* USB controller PME# */ - Method(_L0B) { - /* DBGO("\\_GPE\\_L0B\n") */ - Notify(\_SB.PCI0.UOH1, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(\_SB.PCI0.UOH2, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(\_SB.PCI0.UOH3, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(\_SB.PCI0.UOH4, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(\_SB.PCI0.UOH5, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(\_SB.PCI0.UEH1, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ - } - - /* AC97 controller PME# */ - /* Method(_L0C) { - * DBGO("\\_GPE\\_L0C\n") - * } - */ - - /* OtherTherm PME# */ - /* Method(_L0D) { - * DBGO("\\_GPE\\_L0D\n") - * } - */ - - /* GPM9 SCI event - Moved to USB.asl */ - /* Method(_L0E) { - * DBGO("\\_GPE\\_L0E\n") - * } - */ - - /* PCIe HotPlug event */ - /* Method(_L0F) { - * DBGO("\\_GPE\\_L0F\n") - * } - */ - - /* ExtEvent0 SCI event */ - Method(_L10) { - /* DBGO("\\_GPE\\_L10\n") */ - } - - - /* ExtEvent1 SCI event */ - Method(_L11) { - /* DBGO("\\_GPE\\_L11\n") */ - } - - /* PCIe PME# event */ - /* Method(_L12) { - * DBGO("\\_GPE\\_L12\n") - * } - */ - - /* GPM0 SCI event - Moved to USB.asl */ - /* Method(_L13) { - * DBGO("\\_GPE\\_L13\n") - * } - */ - - /* GPM1 SCI event - Moved to USB.asl */ - /* Method(_L14) { - * DBGO("\\_GPE\\_L14\n") - * } - */ - - /* GPM2 SCI event - Moved to USB.asl */ - /* Method(_L15) { - * DBGO("\\_GPE\\_L15\n") - * } - */ - - /* GPM3 SCI event - Moved to USB.asl */ - /* Method(_L16) { - * DBGO("\\_GPE\\_L16\n") - * } - */ - - /* GPM8 SCI event - Moved to USB.asl */ - /* Method(_L17) { - * DBGO("\\_GPE\\_L17\n") - * } - */ - - /* GPIO0 or GEvent8 event */ - Method(_L18) { - /* DBGO("\\_GPE\\_L18\n") */ - Notify(\_SB.PCI0.PBR2, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(\_SB.PCI0.PBR4, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(\_SB.PCI0.PBR5, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(\_SB.PCI0.PBR6, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(\_SB.PCI0.PBR7, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ - } - - /* GPM4 SCI event - Moved to USB.asl */ - /* Method(_L19) { - * DBGO("\\_GPE\\_L19\n") - * } - */ - - /* GPM5 SCI event - Moved to USB.asl */ - /* Method(_L1A) { - * DBGO("\\_GPE\\_L1A\n") - * } - */ - - /* Azalia SCI event */ - Method(_L1B) { - /* DBGO("\\_GPE\\_L1B\n") */ - Notify(\_SB.PCI0.AZHD, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ - } - - /* GPM6 SCI event - Reassigned to _L06 */ - /* Method(_L1C) { - * DBGO("\\_GPE\\_L1C\n") - * } - */ - - /* GPM7 SCI event - Reassigned to _L07 */ - /* Method(_L1D) { - * DBGO("\\_GPE\\_L1D\n") - * } - */ - - /* GPIO2 or GPIO66 SCI event */ - /* Method(_L1E) { - * DBGO("\\_GPE\\_L1E\n") - * } - */ - - /* SATA SCI event - Moved to sata.asl */ - /* Method(_L1F) { - * DBGO("\\_GPE\\_L1F\n") - * } - */ - - } /* End Scope GPE */ - - #include "acpi/usb.asl" - - /* System Bus */ - Scope(\_SB) { /* Start \_SB scope */ - #include /* global utility methods expected within the \_SB scope */ - - /* _SB.PCI0 */ - /* Note: Only need HID on Primary Bus */ - Device(PCI0) { - External (TOM1) - External (TOM2) /* ( >> 20) to make it fit into 32 bit for XP */ - Name(_HID, EISAID("PNP0A03")) - Name(_ADR, 0x00180000) /* Dev# = BSP Dev#, Func# = 0 */ - Method(_BBN, 0) { /* Bus number = 0 */ - Return(0) - } - Method(_STA, 0) { - /* DBGO("\\_SB\\PCI0\\_STA\n") */ - Return(0x0B) /* Status is visible */ - } - - Method(_PRT,0) { - If(PMOD){ Return(APR0) } /* APIC mode */ - Return (PR0) /* PIC Mode */ - } /* end _PRT */ - - /* Describe the Northbridge devices */ - Device(AMRT) { - Name(_ADR, 0x00000000) - } /* end AMRT */ - - /* The internal GFX bridge */ - Device(AGPB) { - Name(_ADR, 0x00010000) - Name(_PRW, Package() {0x18, 4}) - Method(_PRT,0) { - Return (APR1) - } - } /* end AGPB */ - - /* The external GFX bridge */ - Device(PBR2) { - Name(_ADR, 0x00020000) - Name(_PRW, Package() {0x18, 4}) - Method(_PRT,0) { - If(PMOD){ Return(APS2) } /* APIC mode */ - Return (PS2) /* PIC Mode */ - } /* end _PRT */ - } /* end PBR2 */ - - /* Dev3 is also an external GFX bridge, not used in Herring */ - - Device(PBR4) { - Name(_ADR, 0x00040000) - Name(_PRW, Package() {0x18, 4}) - Method(_PRT,0) { - If(PMOD){ Return(APS4) } /* APIC mode */ - Return (PS4) /* PIC Mode */ - } /* end _PRT */ - } /* end PBR4 */ - - Device(PBR5) { - Name(_ADR, 0x00050000) - Name(_PRW, Package() {0x18, 4}) - Method(_PRT,0) { - If(PMOD){ Return(APS5) } /* APIC mode */ - Return (PS5) /* PIC Mode */ - } /* end _PRT */ - } /* end PBR5 */ - - Device(PBR6) { - Name(_ADR, 0x00060000) - Name(_PRW, Package() {0x18, 4}) - Method(_PRT,0) { - If(PMOD){ Return(APS6) } /* APIC mode */ - Return (PS6) /* PIC Mode */ - } /* end _PRT */ - } /* end PBR6 */ - - /* The onboard EtherNet chip */ - Device(PBR7) { - Name(_ADR, 0x00070000) - Name(_PRW, Package() {0x18, 4}) - Method(_PRT,0) { - If(PMOD){ Return(APS7) } /* APIC mode */ - Return (PS7) /* PIC Mode */ - } /* end _PRT */ - } /* end PBR7 */ - - /* GPP */ - Device(PBR9) { - Name(_ADR, 0x00090000) - Name(_PRW, Package() {0x18, 4}) - Method(_PRT,0) { - If(PMOD){ Return(APS9) } /* APIC mode */ - Return (PS9) /* PIC Mode */ - } /* end _PRT */ - } /* end PBR9 */ - - Device(PBRa) { - Name(_ADR, 0x000A0000) - Name(_PRW, Package() {0x18, 4}) - Method(_PRT,0) { - If(PMOD){ Return(APSa) } /* APIC mode */ - Return (PSa) /* PIC Mode */ - } /* end _PRT */ - } /* end PBRa */ - - - /* PCI slot 1, 2, 3 */ - Device(PIBR) { - Name(_ADR, 0x00140004) - Name(_PRW, Package() {0x18, 4}) - - Method(_PRT, 0) { - Return (PCIB) - } - } - - /* Describe the Southbridge devices */ - Device(STCR) { - Name(_ADR, 0x00110000) - #include "acpi/sata.asl" - } /* end STCR */ - - Device(UOH1) { - Name(_ADR, 0x00130000) - Name(_PRW, Package() {0x0B, 3}) - } /* end UOH1 */ - - Device(UOH2) { - Name(_ADR, 0x00130001) - Name(_PRW, Package() {0x0B, 3}) - } /* end UOH2 */ - - Device(UOH3) { - Name(_ADR, 0x00130002) - Name(_PRW, Package() {0x0B, 3}) - } /* end UOH3 */ - - Device(UOH4) { - Name(_ADR, 0x00130003) - Name(_PRW, Package() {0x0B, 3}) - } /* end UOH4 */ - - Device(UOH5) { - Name(_ADR, 0x00130004) - Name(_PRW, Package() {0x0B, 3}) - } /* end UOH5 */ - - Device(UEH1) { - Name(_ADR, 0x00130005) - Name(_PRW, Package() {0x0B, 3}) - } /* end UEH1 */ - - Device(SBUS) { - Name(_ADR, 0x00140000) - } /* end SBUS */ - - /* Primary (and only) IDE channel */ - Device(IDEC) { - Name(_ADR, 0x00140001) - #include "acpi/ide.asl" - } /* end IDEC */ - - Device(AZHD) { - Name(_ADR, 0x00140002) - OperationRegion(AZPD, PCI_Config, 0x00, 0x100) - Field(AZPD, AnyAcc, NoLock, Preserve) { - offset (0x42), - NSDI, 1, - NSDO, 1, - NSEN, 1, - offset (0x44), - IPCR, 4, - offset (0x54), - PWST, 2, - , 6, - PMEB, 1, - , 6, - PMST, 1, - offset (0x62), - MMCR, 1, - offset (0x64), - MMLA, 32, - offset (0x68), - MMHA, 32, - offset (0x6C), - MMDT, 16, - } - - Method(_INI) { - If(LEqual(OSVR,3)){ /* If we are running Linux */ - Store(zero, NSEN) - Store(one, NSDO) - Store(one, NSDI) - } - } - } /* end AZHD */ - - Device(LIBR) { - Name(_ADR, 0x00140003) - /* Method(_INI) { - * DBGO("\\_SB\\PCI0\\LpcIsaBr\\_INI\n") - } */ /* End Method(_SB.SBRDG._INI) */ - - /* Real Time Clock Device */ - Device(RTC0) { - Name(_HID, EISAID("PNP0B00")) /* AT Real Time Clock (not PIIX4 compatible) */ - Name(_CRS, ResourceTemplate() { - IRQNoFlags(){8} - IO(Decode16,0x0070, 0x0070, 0, 2) - /* IO(Decode16,0x0070, 0x0070, 0, 4) */ - }) - } /* End Device(_SB.PCI0.LpcIsaBr.RTC0) */ - - Device(TMR) { /* Timer */ - Name(_HID,EISAID("PNP0100")) /* System Timer */ - Name(_CRS, ResourceTemplate() { - IRQNoFlags(){0} - IO(Decode16, 0x0040, 0x0040, 0, 4) - /* IO(Decode16, 0x0048, 0x0048, 0, 4) */ - }) - } /* End Device(_SB.PCI0.LpcIsaBr.TMR) */ - - Device(SPKR) { /* Speaker */ - Name(_HID,EISAID("PNP0800")) /* AT style speaker */ - Name(_CRS, ResourceTemplate() { - IO(Decode16, 0x0061, 0x0061, 0, 1) - }) - } /* End Device(_SB.PCI0.LpcIsaBr.SPKR) */ - - Device(PIC) { - Name(_HID,EISAID("PNP0000")) /* AT Interrupt Controller */ - Name(_CRS, ResourceTemplate() { - IRQNoFlags(){2} - IO(Decode16,0x0020, 0x0020, 0, 2) - IO(Decode16,0x00A0, 0x00A0, 0, 2) - /* IO(Decode16, 0x00D0, 0x00D0, 0x10, 0x02) */ - /* IO(Decode16, 0x04D0, 0x04D0, 0x10, 0x02) */ - }) - } /* End Device(_SB.PCI0.LpcIsaBr.PIC) */ - - Device(MAD) { /* 8257 DMA */ - Name(_HID,EISAID("PNP0200")) /* Hardware Device ID */ - Name(_CRS, ResourceTemplate() { - DMA(Compatibility,BusMaster,Transfer8){4} - IO(Decode16, 0x0000, 0x0000, 0x10, 0x10) - IO(Decode16, 0x0081, 0x0081, 0x01, 0x03) - IO(Decode16, 0x0087, 0x0087, 0x01, 0x01) - IO(Decode16, 0x0089, 0x0089, 0x01, 0x03) - IO(Decode16, 0x008F, 0x008F, 0x01, 0x01) - IO(Decode16, 0x00C0, 0x00C0, 0x10, 0x20) - }) /* End Name(_SB.PCI0.LpcIsaBr.MAD._CRS) */ - } /* End Device(_SB.PCI0.LpcIsaBr.MAD) */ - - Device(COPR) { - Name(_HID,EISAID("PNP0C04")) /* Math Coprocessor */ - Name(_CRS, ResourceTemplate() { - IO(Decode16, 0x00F0, 0x00F0, 0, 0x10) - IRQNoFlags(){13} - }) - } /* End Device(_SB.PCI0.LpcIsaBr.COPR) */ - - Device(HPTM) { - Name(_HID,EISAID("PNP0103")) - Name(CRS,ResourceTemplate() { - Memory32Fixed(ReadOnly,0xFED00000, 0x00000400, HPT) /* 1kb reserved space */ - }) - Method(_STA, 0) { - Return(0x0F) /* sata is visible */ - } - Method(_CRS, 0) { - CreateDwordField(CRS, ^HPT._BAS, HPBX) - Store(HPBA, HPBX) - Return(CRS) - } - } /* End Device(_SB.PCI0.LpcIsaBr.COPR) */ - } /* end LIBR */ - - Device(HPBR) { - Name(_ADR, 0x00140004) - } /* end HostPciBr */ - - Device(ACAD) { - Name(_ADR, 0x00140005) - } /* end Ac97audio */ - - Device(ACMD) { - Name(_ADR, 0x00140006) - } /* end Ac97modem */ - - /* ITE8718 Support */ - OperationRegion (IOID, SystemIO, 0x2E, 0x02) /* sometimes it is 0x4E */ - Field (IOID, ByteAcc, NoLock, Preserve) - { - SIOI, 8, SIOD, 8 /* 0x2E and 0x2F */ - } - - IndexField (SIOI, SIOD, ByteAcc, NoLock, Preserve) - { - Offset (0x07), - LDN, 8, /* Logical Device Number */ - Offset (0x20), - CID1, 8, /* Chip ID Byte 1, 0x87 */ - CID2, 8, /* Chip ID Byte 2, 0x12 */ - Offset (0x30), - ACTR, 8, /* Function activate */ - Offset (0xF0), - APC0, 8, /* APC/PME Event Enable Register */ - APC1, 8, /* APC/PME Status Register */ - APC2, 8, /* APC/PME Control Register 1 */ - APC3, 8, /* Environment Controller Special Configuration Register */ - APC4, 8 /* APC/PME Control Register 2 */ - } - - /* Enter the 8718 MB PnP Mode */ - Method (EPNP) - { - Store(0x87, SIOI) - Store(0x01, SIOI) - Store(0x55, SIOI) - Store(0x55, SIOI) /* 8718 magic number */ - } - /* Exit the 8718 MB PnP Mode */ - Method (XPNP) - { - Store (0x02, SIOI) - Store (0x02, SIOD) - } - /* - * Keyboard PME is routed to SB700 Gevent3. We can wake - * up the system by pressing the key. - */ - Method (SIOS, 1) - { - /* We only enable KBD PME for S5. */ - If (LLess (Arg0, 0x05)) - { - EPNP() - /* DBGO("8718F\n") */ - - Store (0x4, LDN) - Store (One, ACTR) /* Enable EC */ - /* - Store (0x4, LDN) - Store (0x04, APC4) - */ /* falling edge. which mode? Not sure. */ - - Store (0x4, LDN) - Store (0x08, APC1) /* clear PME status, Use 0x18 for mouse & KBD */ - Store (0x4, LDN) - Store (0x08, APC0) /* enable PME, Use 0x18 for mouse & KBD */ - - XPNP() - } - } - Method (SIOW, 0) - { - EPNP() - Store (0x4, LDN) - Store (Zero, APC0) /* disable keyboard PME */ - Store (0x4, LDN) - Store (0xFF, APC1) /* clear keyboard PME status */ - XPNP() - } - - Name(CRES, ResourceTemplate() { - IO(Decode16, 0x0CF8, 0x0CF8, 1, 8) - - WORDIO(ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, - 0x0000, /* address granularity */ - 0x0000, /* range minimum */ - 0x0CF7, /* range maximum */ - 0x0000, /* translation */ - 0x0CF8 /* length */ - ) - - WORDIO(ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, - 0x0000, /* address granularity */ - 0x0D00, /* range minimum */ - 0xFFFF, /* range maximum */ - 0x0000, /* translation */ - 0xF300 /* length */ - ) - - Memory32Fixed(READWRITE, 0, 0xA0000, BSMM) - Memory32Fixed(READONLY, 0x000A0000, 0x00020000, VGAM) /* VGA memory space */ - Memory32Fixed(READONLY, 0x000C0000, 0x00020000, EMM1) /* Assume C0000-E0000 empty */ - Memory32Fixed(READONLY, 0x000E0000, 0x00020000, RDBS) /* BIOS ROM area */ - - /* DRAM Memory from 1MB to TopMem */ - Memory32Fixed(READWRITE, 0x00100000, 0, DMLO) /* 1MB to TopMem */ - - /* BIOS space just below 4GB */ - DWORDMemory( - ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite, - 0x00, /* Granularity */ - 0x00000000, /* Min */ - 0x00000000, /* Max */ - 0x00000000, /* Translation */ - 0x00000001, /* Max-Min, RLEN */ - ,, - PCBM - ) - - /* DRAM memory from 4GB to TopMem2 */ - QWORDMemory(ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite, - 0x00000000, /* Granularity */ - 0x00000000, /* Min */ - 0x00000000, /* Max */ - 0x00000000, /* Translation */ - 0x00000001, /* Max-Min, RLEN */ - ,, - DMHI - ) - - /* BIOS space just below 16EB */ - QWORDMemory(ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite, - 0x00000000, /* Granularity */ - 0x00000000, /* Min */ - 0x00000000, /* Max */ - 0x00000000, /* Translation */ - 0x00000001, /* Max-Min, RLEN */ - ,, - PEBM - ) - - }) /* End Name(_SB.PCI0.CRES) */ - - Method(_CRS, 0) { - /* DBGO("\\_SB\\PCI0\\_CRS\n") */ - - CreateDWordField(CRES, ^EMM1._BAS, EM1B) - CreateDWordField(CRES, ^EMM1._LEN, EM1L) - CreateDWordField(CRES, ^DMLO._BAS, DMLB) - CreateDWordField(CRES, ^DMLO._LEN, DMLL) - CreateDWordField(CRES, ^PCBM._MIN, PBMB) - CreateDWordField(CRES, ^PCBM._LEN, PBML) - - CreateQWordField(CRES, ^DMHI._MIN, DMHB) - CreateQWordField(CRES, ^DMHI._LEN, DMHL) - CreateQWordField(CRES, ^PEBM._MIN, EBMB) - CreateQWordField(CRES, ^PEBM._LEN, EBML) - - If(LGreater(LOMH, 0xC0000)){ - Store(0xC0000, EM1B) /* Hole above C0000 and below E0000 */ - Subtract(LOMH, 0xC0000, EM1L) /* subtract start, assumes allocation from C0000 going up */ - } - - /* Set size of memory from 1MB to TopMem */ - Subtract(TOM1, 0x100000, DMLL) - - /* - * If(LNotEqual(TOM2, 0x00000000)){ - * Store(0x100000000,DMHB) DRAM from 4GB to TopMem2 - * ShiftLeft(TOM2, 20, Local0) - * Subtract(Local0, 0x100000000, DMHL) - * } - */ - - /* If there is no memory above 4GB, put the BIOS just below 4GB */ - If(LEqual(TOM2, 0x00000000)){ - Store(PBAD,PBMB) /* Reserve the "BIOS" space */ - Store(PBLN,PBML) - } - Else { /* Otherwise, put the BIOS just below 16EB */ - ShiftLeft(PBAD,16,EBMB) /* Reserve the "BIOS" space */ - Store(PBLN,EBML) - } - - Return(CRES) /* note to change the Name buffer */ - } /* end of Method(_SB.PCI0._CRS) */ - - /* - * - * FIRST METHOD CALLED UPON BOOT - * - * 1. If debugging, print current OS and ACPI interpreter. - * 2. Get PCI Interrupt routing from ACPI VSM, this - * value is based on user choice in BIOS setup. - */ - Method(_INI, 0) { - /* DBGO("\\_SB\\_INI\n") */ - /* DBGO(" DSDT.ASL code from ") */ - /* DBGO(__DATE__) */ - /* DBGO(" ") */ - /* DBGO(__TIME__) */ - /* DBGO("\n Sleep states supported: ") */ - /* DBGO("\n") */ - /* DBGO(" \\_OS=") */ - /* DBGO(\_OS) */ - /* DBGO("\n \\_REV=") */ - /* DBGO(\_REV) */ - /* DBGO("\n") */ - - /* Determine the OS we're running on */ - OSFL() - - /* On older chips, clear PciExpWakeDisEn */ - /*if (LLessEqual(\SBRI, 0x13)) { - * Store(0,\PWDE) - * } - */ - } /* End Method(_SB._INI) */ - } /* End Device(PCI0) */ - - Device(PWRB) { /* Start Power button device */ - Name(_HID, EISAID("PNP0C0C")) - Name(_UID, 0xAA) - Name(_PRW, Package () {3, 0x04}) /* wake from S1-S4 */ - Name(_STA, 0x0B) /* sata is invisible */ - } - } /* End \_SB scope */ - - Scope(\_SI) { - Method(_SST, 1) { - /* DBGO("\\_SI\\_SST\n") */ - /* DBGO(" New Indicator state: ") */ - /* DBGO(Arg0) */ - /* DBGO("\n") */ - } - } /* End Scope SI */ - - #include - - /* THERMAL */ - Scope(\_TZ) { - Name (KELV, 2732) - Name (THOT, 800) - Name (TCRT, 850) - - ThermalZone(TZ00) { - Method(_AC0,0) { /* Active Cooling 0 (0=highest fan speed) */ - /* DBGO("\\_TZ\\TZ00\\_AC0\n") */ - Return(Add(0, 2730)) - } - Method(_AL0,0) { /* Returns package of cooling device to turn on */ - /* DBGO("\\_TZ\\TZ00\\_AL0\n") */ - Return(Package() {\_TZ.TZ00.FAN0}) - } - Device (FAN0) { - Name(_HID, EISAID("PNP0C0B")) - Name(_PR0, Package() {PFN0}) - } - - PowerResource(PFN0,0,0) { - Method(_STA) { - Store(0xF,Local0) - Return(Local0) - } - Method(_ON) { - /* DBGO("\\_TZ\\TZ00\\FAN0 _ON\n") */ - } - Method(_OFF) { - /* DBGO("\\_TZ\\TZ00\\FAN0 _OFF\n") */ - } - } - - Method(_HOT,0) { /* return hot temp in tenths degree Kelvin */ - /* DBGO("\\_TZ\\TZ00\\_HOT\n") */ - Return (Add (THOT, KELV)) - } - Method(_CRT,0) { /* return critical temp in tenths degree Kelvin */ - /* DBGO("\\_TZ\\TZ00\\_CRT\n") */ - Return (Add (TCRT, KELV)) - } - Method(_TMP,0) { /* return current temp of this zone */ - Store (SMBR (0x07, 0x4C,, 0x00), Local0) - If (LGreater (Local0, 0x10)) { - Store (Local0, Local1) - } - Else { - Add (Local0, THOT, Local0) - Return (Add (400, KELV)) - } - - Store (SMBR (0x07, 0x4C, 0x01), Local0) - /* only the two MSBs in the external temperature low byte are used, resolution 0.25. We ignore it */ - /* Store (SMBR (0x07, 0x4C, 0x10), Local2) */ - If (LGreater (Local0, 0x10)) { - If (LGreater (Local0, Local1)) { - Store (Local0, Local1) - } - - Multiply (Local1, 10, Local1) - Return (Add (Local1, KELV)) - } - Else { - Add (Local0, THOT, Local0) - Return (Add (400 , KELV)) - } - } /* end of _TMP */ - } /* end of TZ00 */ - } -} -/* End of ASL file */ diff --git a/src/mainboard/asus/m4a78-em/get_bus_conf.c b/src/mainboard/asus/m4a78-em/get_bus_conf.c deleted file mode 100644 index ee2a6caeb9..0000000000 --- a/src/mainboard/asus/m4a78-em/get_bus_conf.c +++ /dev/null @@ -1,44 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2010 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include -#include - -#include - -/* Global variables for MB layouts and these will be shared by irqtable mptable -* and acpi_tables busnum is default. -*/ -u32 apicid_sb700; - -void get_bus_conf(void) -{ - u32 apicid_base; - - get_default_pci1234(1); - - sysconf.sbdn = (sysconf.hcdn[0] & 0xff); - - pirq_router_bus = (sysconf.pci1234[0] >> 16) & 0xff; - - /* I/O APICs: APIC ID Version State Address */ - if (CONFIG(LOGICAL_CPUS)) - apicid_base = get_apicid_base(1); - else - apicid_base = CONFIG_MAX_PHYSICAL_CPUS; - apicid_sb700 = apicid_base + 0; -} diff --git a/src/mainboard/asus/m4a78-em/irq_tables.c b/src/mainboard/asus/m4a78-em/irq_tables.c deleted file mode 100644 index c74827544c..0000000000 --- a/src/mainboard/asus/m4a78-em/irq_tables.c +++ /dev/null @@ -1,60 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2010 Juhana Helovuo - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include - -static const struct irq_routing_table intel_irq_routing_table = { - PIRQ_SIGNATURE, /* u32 signature */ - PIRQ_VERSION, /* u16 version */ - 32 + 16 * CONFIG_IRQ_SLOT_COUNT, /* Max. number of devices on the bus */ - 0x00, /* Interrupt router bus */ - (0x14 << 3) | 0x3, /* Interrupt router dev */ - 0, /* IRQs devoted exclusively to PCI usage */ - 0x1002, /* Vendor */ - 0x439d, /* Device */ - 0, /* Miniport */ - { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */ - 0xca, /* Checksum (has to be set to some value that - * would give 0 after the sum of all bytes - * for this structure (including checksum). - */ - { - /* bus, dev | fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */ - {0x01, (0x05 << 3) | 0x0, {{0x03, 0xdc90}, {0x04, 0xdc90}, {0x01, 0xdc90}, {0x02, 0xdc90}}, 0x0, 0x0}, - {0x00, (0x02 << 3) | 0x0, {{0x03, 0xdc90}, {0x04, 0xdc90}, {0x01, 0xdc90}, {0x02, 0xdc90}}, 0x0, 0x0}, - {0x00, (0x03 << 3) | 0x0, {{0x04, 0xdc90}, {0x01, 0xdc90}, {0x02, 0xdc90}, {0x03, 0xdc90}}, 0x0, 0x0}, - {0x00, (0x04 << 3) | 0x0, {{0x01, 0xdc90}, {0x02, 0xdc90}, {0x03, 0xdc90}, {0x04, 0xdc90}}, 0x0, 0x0}, - {0x00, (0x05 << 3) | 0x0, {{0x02, 0xdc90}, {0x03, 0xdc90}, {0x04, 0xdc90}, {0x01, 0xdc90}}, 0x0, 0x0}, - {0x00, (0x06 << 3) | 0x0, {{0x03, 0xdc90}, {0x04, 0xdc90}, {0x01, 0xdc90}, {0x02, 0xdc90}}, 0x0, 0x0}, - {0x00, (0x07 << 3) | 0x0, {{0x04, 0xdc90}, {0x01, 0xdc90}, {0x02, 0xdc90}, {0x03, 0xdc90}}, 0x0, 0x0}, - {0x00, (0x09 << 3) | 0x0, {{0x02, 0xdc90}, {0x03, 0xdc90}, {0x04, 0xdc90}, {0x01, 0xdc90}}, 0x0, 0x0}, - {0x00, (0x0a << 3) | 0x0, {{0x03, 0xdc90}, {0x04, 0xdc90}, {0x01, 0xdc90}, {0x02, 0xdc90}}, 0x0, 0x0}, - {0x02, (0x00 << 3) | 0x0, {{0x03, 0xdc90}, {0x04, 0xdc90}, {0x01, 0xdc90}, {0x02, 0xdc90}}, 0xa, 0x0}, - {0x00, (0x0b << 3) | 0x0, {{0x04, 0xdc90}, {0x01, 0xdc90}, {0x02, 0xdc90}, {0x03, 0xdc90}}, 0x0, 0x0}, - {0x00, (0x0c << 3) | 0x0, {{0x01, 0xdc90}, {0x02, 0xdc90}, {0x03, 0xdc90}, {0x04, 0xdc90}}, 0x0, 0x0}, - {0x00, (0x14 << 3) | 0x0, {{0x01, 0xdc90}, {0x02, 0xdc90}, {0x03, 0xdc90}, {0x04, 0xdc90}}, 0x0, 0x0}, - {0x00, (0x12 << 3) | 0x0, {{0x01, 0xdc90}, {0x02, 0xdc90}, {0x03, 0xdc90}, {0x04, 0xdc90}}, 0x0, 0x0}, - {0x00, (0x13 << 3) | 0x0, {{0x03, 0xdc90}, {0x04, 0xdc90}, {0x01, 0xdc90}, {0x02, 0xdc90}}, 0x0, 0x0}, - {0x00, (0x11 << 3) | 0x0, {{0x0c, 0xdc90}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x0000}}, 0x0, 0x0}, - {0x03, (0x06 << 3) | 0x0, {{0x0a, 0xdc90}, {0x0b, 0xdc90}, {0x0c, 0xdc90}, {0x0d, 0xdc90}}, 0xd, 0x0}, - {0x03, (0x07 << 3) | 0x0, {{0x0b, 0xdc90}, {0x0c, 0xdc90}, {0x0d, 0xdc90}, {0x0a, 0xdc90}}, 0xe, 0x0}, - } -}; - -unsigned long write_pirq_routing_table(unsigned long addr) -{ - return copy_pirq_routing_table(addr, &intel_irq_routing_table); -} diff --git a/src/mainboard/asus/m4a78-em/mainboard.c b/src/mainboard/asus/m4a78-em/mainboard.c deleted file mode 100644 index 66da65baad..0000000000 --- a/src/mainboard/asus/m4a78-em/mainboard.c +++ /dev/null @@ -1,116 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2010 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include -#include -#include -#include -#include -#include - -void set_pcie_dereset(void) -{ - u8 byte; - u16 word; - struct device *sm_dev; - /* set 0 to bit1 :disable GPM9 as SLP_S2 output */ - /* set 0 to bit2 :disable GPM8 as AZ_RST output */ - byte = pm_ioread(0x8d); - byte &= ~((1 << 1) | (1 << 2)); - pm_iowrite(0x8d, byte); - - /* set the GPM8 and GPM9 output enable and the value to 1 */ - byte = pm_ioread(0x94); - byte &= ~((1 << 2) | (1 << 3)); - byte |= ((1 << 0) | (1 << 1)); - pm_iowrite(0x94, byte); - - /* set the GPIO65 output enable and the value is 1 */ - sm_dev = pcidev_on_root(0x14, 0); - word = pci_read_config16(sm_dev, 0x7e); - word |= (1 << 0); - word &= ~(1 << 4); - pci_write_config16(sm_dev, 0x7e, word); -} - -void set_pcie_reset(void) -{ - u8 byte; - u16 word; - struct device *sm_dev; - - /* set 0 to bit1 :disable GPM9 as SLP_S2 output */ - /* set 0 to bit2 :disable GPM8 as AZ_RST output */ - byte = pm_ioread(0x8d); - byte &= ~((1 << 1) | (1 << 2)); - pm_iowrite(0x8d, byte); - - /* set the GPM8 and GPM9 output enable and the value to 0 */ - byte = pm_ioread(0x94); - byte &= ~((1 << 2) | (1 << 3)); - byte &= ~((1 << 0) | (1 << 1)); - pm_iowrite(0x94, byte); - - /* set the GPIO65 output enable and the value is 0 */ - sm_dev = pcidev_on_root(0x14, 0); - word = pci_read_config16(sm_dev, 0x7e); - word &= ~(1 << 0); - word &= ~(1 << 4); - pci_write_config16(sm_dev, 0x7e, word); -} - -/* - * justify the dev3 is exist or not - * NOTE: This just copied from AMD Tilapia code. - * It is completely unknown if it will work at all for this board. - */ -int is_dev3_present(void) -{ - u16 word; - struct device *sm_dev; - - /* access the smbus extended register */ - sm_dev = pcidev_on_root(0x14, 0); - - /* put the GPIO68 output to tristate */ - word = pci_read_config16(sm_dev, 0x7e); - word |= 1 << 6; - pci_write_config16(sm_dev, 0x7e,word); - - /* read the GPIO68 input status */ - word = pci_read_config16(sm_dev, 0x7e); - - return !(word & (1 << 10)); -} - - -/************************************************* -* enable the dedicated function in this board. -* This function called early than rs780_enable. -*************************************************/ -static void mainboard_enable(struct device *dev) -{ - printk(BIOS_INFO, "Mainboard enable. dev=0x%p\n", dev); - - set_pcie_dereset(); - /* get_ide_dma66(); */ - /* set_thermal_config(); */ -} - -struct chip_operations mainboard_ops = { - .enable_dev = mainboard_enable, -}; diff --git a/src/mainboard/asus/m4a78-em/mptable.c b/src/mainboard/asus/m4a78-em/mptable.c deleted file mode 100644 index 876e7ee578..0000000000 --- a/src/mainboard/asus/m4a78-em/mptable.c +++ /dev/null @@ -1,103 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2010 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include -#include -#include - - -extern u32 apicid_sb700; - - -static void *smp_write_config_table(void *v) -{ - struct mp_config_table *mc; - int bus_isa; - - mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); - - mptable_init(mc, LOCAL_APIC_ADDR); - - smp_write_processors(mc); - - mptable_write_buses(mc, NULL, &bus_isa); - - /* I/O APICs: APIC ID Version State Address */ - { - struct device *dev; - u32 dword; - u8 byte; - - dev = - dev_find_slot(pirq_router_bus, - PCI_DEVFN(0x14, 0)); - if (dev) { - dword = pci_read_config32(dev, 0x74) & 0xfffffff0; - smp_write_ioapic(mc, apicid_sb700, - 0x11,(void *) dword); - - /* Initialize interrupt mapping */ - /* aza */ - byte = pci_read_config8(dev, 0x63); - byte &= 0xf8; - byte |= 0; /* 0: INTA, ...., 7: INTH */ - pci_write_config8(dev, 0x63, byte); - - /* SATA */ - dword = pci_read_config32(dev, 0xac); - dword &= ~(7 << 26); - dword |= 6 << 26; /* 0: INTA, ...., 7: INTH */ - /* dword |= 1 << 22; PIC and APIC co exists */ - pci_write_config32(dev, 0xac, dword); - - /* - * 00:12.0: PROG SATA : INT F - * 00:13.0: INTA USB_0 - * 00:13.1: INTB USB_1 - * 00:13.2: INTC USB_2 - * 00:13.3: INTD USB_3 - * 00:13.4: INTC USB_4 - * 00:13.5: INTD USB2 - * 00:14.1: INTA IDE - * 00:14.2: Prog HDA : INT E - * 00:14.5: INTB ACI - * 00:14.6: INTB MCI - */ - } - } - - /* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ -#define IO_LOCAL_INT(type, intr, apicid, pin) \ - smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin)); - - mptable_add_isa_interrupts(mc, bus_isa, apicid_sb700, 0); - - /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ - IO_LOCAL_INT(mp_ExtINT, 0x0, MP_APIC_ALL, 0x0); - IO_LOCAL_INT(mp_NMI, 0x0, MP_APIC_ALL, 0x1); - /* There is no extension information... */ - - /* Compute the checksums */ - return mptable_finalize(mc); -} - -unsigned long write_smp_table(unsigned long addr) -{ - void *v; - v = smp_write_floating_table(addr, 0); - return (unsigned long)smp_write_config_table(v); -} diff --git a/src/mainboard/asus/m4a78-em/resourcemap.c b/src/mainboard/asus/m4a78-em/resourcemap.c deleted file mode 100644 index 80d2d9d05c..0000000000 --- a/src/mainboard/asus/m4a78-em/resourcemap.c +++ /dev/null @@ -1,279 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2010 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - - - -#include -#include - -void setup_mb_resource_map(void) -{ - static const unsigned int register_values[] = { - /* Careful set limit registers before base registers which contain the enables */ - /* DRAM Limit i Registers - * F1:0x44 i = 0 - * F1:0x4C i = 1 - * F1:0x54 i = 2 - * F1:0x5C i = 3 - * F1:0x64 i = 4 - * F1:0x6C i = 5 - * F1:0x74 i = 6 - * F1:0x7C i = 7 - * [ 2: 0] Destination Node ID - * 000 = Node 0 - * 001 = Node 1 - * 010 = Node 2 - * 011 = Node 3 - * 100 = Node 4 - * 101 = Node 5 - * 110 = Node 6 - * 111 = Node 7 - * [ 7: 3] Reserved - * [10: 8] Interleave select - * specifies the values of A[14:12] to use with interleave enable. - * [15:11] Reserved - * [31:16] DRAM Limit Address i Bits 39-24 - * This field defines the upper address bits of a 40 bit address - * that define the end of the DRAM region. - */ -// ADDRMAP_REG(0x44), 0x0000f8f8, 0x00000000, // Don't touch it, we need it for CONFIG_CAR_FAM10 - ADDRMAP_REG(0x4C), 0x0000f8f8, 0x00000001, - ADDRMAP_REG(0x54), 0x0000f8f8, 0x00000002, - ADDRMAP_REG(0x5C), 0x0000f8f8, 0x00000003, - ADDRMAP_REG(0x64), 0x0000f8f8, 0x00000004, - ADDRMAP_REG(0x6C), 0x0000f8f8, 0x00000005, - ADDRMAP_REG(0x74), 0x0000f8f8, 0x00000006, - ADDRMAP_REG(0x7C), 0x0000f8f8, 0x00000007, - /* DRAM Base i Registers - * F1:0x40 i = 0 - * F1:0x48 i = 1 - * F1:0x50 i = 2 - * F1:0x58 i = 3 - * F1:0x60 i = 4 - * F1:0x68 i = 5 - * F1:0x70 i = 6 - * F1:0x78 i = 7 - * [ 0: 0] Read Enable - * 0 = Reads Disabled - * 1 = Reads Enabled - * [ 1: 1] Write Enable - * 0 = Writes Disabled - * 1 = Writes Enabled - * [ 7: 2] Reserved - * [10: 8] Interleave Enable - * 000 = No interleave - * 001 = Interleave on A[12] (2 nodes) - * 010 = reserved - * 011 = Interleave on A[12] and A[14] (4 nodes) - * 100 = reserved - * 101 = reserved - * 110 = reserved - * 111 = Interleve on A[12] and A[13] and A[14] (8 nodes) - * [15:11] Reserved - * [13:16] DRAM Base Address i Bits 39-24 - * This field defines the upper address bits of a 40-bit address - * that define the start of the DRAM region. - */ -// ADDRMAP_REG(0x40), 0x0000f8fc, 0x00000000,// don't touch it, we need it for CONFIG_CAR_FAM10 - ADDRMAP_REG(0x48), 0x0000f8fc, 0x00000000, - ADDRMAP_REG(0x50), 0x0000f8fc, 0x00000000, - ADDRMAP_REG(0x58), 0x0000f8fc, 0x00000000, - ADDRMAP_REG(0x60), 0x0000f8fc, 0x00000000, - ADDRMAP_REG(0x68), 0x0000f8fc, 0x00000000, - ADDRMAP_REG(0x70), 0x0000f8fc, 0x00000000, - ADDRMAP_REG(0x78), 0x0000f8fc, 0x00000000, - - /* Memory-Mapped I/O Limit i Registers - * F1:0x84 i = 0 - * F1:0x8C i = 1 - * F1:0x94 i = 2 - * F1:0x9C i = 3 - * F1:0xA4 i = 4 - * F1:0xAC i = 5 - * F1:0xB4 i = 6 - * F1:0xBC i = 7 - * [ 2: 0] Destination Node ID - * 000 = Node 0 - * 001 = Node 1 - * 010 = Node 2 - * 011 = Node 3 - * 100 = Node 4 - * 101 = Node 5 - * 110 = Node 6 - * 111 = Node 7 - * [ 3: 3] Reserved - * [ 5: 4] Destination Link ID - * 00 = Link 0 - * 01 = Link 1 - * 10 = Link 2 - * 11 = Reserved - * [ 6: 6] Reserved - * [ 7: 7] Non-Posted - * 0 = CPU writes may be posted - * 1 = CPU writes must be non-posted - * [31: 8] Memory-Mapped I/O Limit Address i (39-16) - * This field defines the upp address bits of a 40-bit address that - * defines the end of a memory-mapped I/O region n - */ - ADDRMAP_REG(0x84), 0x00000048, 0x00000000, - ADDRMAP_REG(0x8C), 0x00000048, 0x00000000, - ADDRMAP_REG(0x94), 0x00000048, 0x00000000, - ADDRMAP_REG(0x9C), 0x00000048, 0x00000000, - ADDRMAP_REG(0xA4), 0x00000048, 0x00000000, - ADDRMAP_REG(0xAC), 0x00000048, 0x00000000, - ADDRMAP_REG(0xB4), 0x00000048, 0x00000000, -// ADDRMAP_REG(0xBC), 0x00000048, 0x00ffff00, - - /* Memory-Mapped I/O Base i Registers - * F1:0x80 i = 0 - * F1:0x88 i = 1 - * F1:0x90 i = 2 - * F1:0x98 i = 3 - * F1:0xA0 i = 4 - * F1:0xA8 i = 5 - * F1:0xB0 i = 6 - * F1:0xB8 i = 7 - * [ 0: 0] Read Enable - * 0 = Reads disabled - * 1 = Reads Enabled - * [ 1: 1] Write Enable - * 0 = Writes disabled - * 1 = Writes Enabled - * [ 2: 2] Cpu Disable - * 0 = Cpu can use this I/O range - * 1 = Cpu requests do not use this I/O range - * [ 3: 3] Lock - * 0 = base/limit registers i are read/write - * 1 = base/limit registers i are read-only - * [ 7: 4] Reserved - * [31: 8] Memory-Mapped I/O Base Address i (39-16) - * This field defines the upper address bits of a 40bit address - * that defines the start of memory-mapped I/O region i - */ - ADDRMAP_REG(0x80), 0x000000f0, 0x00000000, - ADDRMAP_REG(0x88), 0x000000f0, 0x00000000, - ADDRMAP_REG(0x90), 0x000000f0, 0x00000000, - ADDRMAP_REG(0x98), 0x000000f0, 0x00000000, - ADDRMAP_REG(0xA0), 0x000000f0, 0x00000000, - ADDRMAP_REG(0xA8), 0x000000f0, 0x00000000, - ADDRMAP_REG(0xB0), 0x000000f0, 0x00000000, -// ADDRMAP_REG(0xB8), 0x000000f0, 0x00fc0003, - - /* PCI I/O Limit i Registers - * F1:0xC4 i = 0 - * F1:0xCC i = 1 - * F1:0xD4 i = 2 - * F1:0xDC i = 3 - * [ 2: 0] Destination Node ID - * 000 = Node 0 - * 001 = Node 1 - * 010 = Node 2 - * 011 = Node 3 - * 100 = Node 4 - * 101 = Node 5 - * 110 = Node 6 - * 111 = Node 7 - * [ 3: 3] Reserved - * [ 5: 4] Destination Link ID - * 00 = Link 0 - * 01 = Link 1 - * 10 = Link 2 - * 11 = reserved - * [11: 6] Reserved - * [24:12] PCI I/O Limit Address i - * This field defines the end of PCI I/O region n - * [31:25] Reserved - */ -// ADDRMAP_REG(0xC4), 0xFE000FC8, 0x01fff000, - ADDRMAP_REG(0xCC), 0xFE000FC8, 0x00000000, - ADDRMAP_REG(0xD4), 0xFE000FC8, 0x00000000, - ADDRMAP_REG(0xDC), 0xFE000FC8, 0x00000000, - - /* PCI I/O Base i Registers - * F1:0xC0 i = 0 - * F1:0xC8 i = 1 - * F1:0xD0 i = 2 - * F1:0xD8 i = 3 - * [ 0: 0] Read Enable - * 0 = Reads Disabled - * 1 = Reads Enabled - * [ 1: 1] Write Enable - * 0 = Writes Disabled - * 1 = Writes Enabled - * [ 3: 2] Reserved - * [ 4: 4] VGA Enable - * 0 = VGA matches Disabled - * 1 = matches all address < 64K and where A[9:0] is in the - * range 3B0-3BB or 3C0-3DF independen of the base & limit registers - * [ 5: 5] ISA Enable - * 0 = ISA matches Disabled - * 1 = Blocks address < 64K and in the last 768 bytes of eack 1K block - * from matching agains this base/limit pair - * [11: 6] Reserved - * [24:12] PCI I/O Base i - * This field defines the start of PCI I/O region n - * [31:25] Reserved - */ -// ADDRMAP_REG(0xC0), 0xFE000FCC, 0x00000003, - ADDRMAP_REG(0xC8), 0xFE000FCC, 0x00000000, - ADDRMAP_REG(0xD0), 0xFE000FCC, 0x00000000, - ADDRMAP_REG(0xD8), 0xFE000FCC, 0x00000000, - - /* Config Base and Limit i Registers - * F1:0xE0 i = 0 - * F1:0xE4 i = 1 - * F1:0xE8 i = 2 - * F1:0xEC i = 3 - * [ 0: 0] Read Enable - * 0 = Reads Disabled - * 1 = Reads Enabled - * [ 1: 1] Write Enable - * 0 = Writes Disabled - * 1 = Writes Enabled - * [ 2: 2] Device Number Compare Enable - * 0 = The ranges are based on bus number - * 1 = The ranges are ranges of devices on bus 0 - * [ 3: 3] Reserved - * [ 6: 4] Destination Node - * 000 = Node 0 - * 001 = Node 1 - * 010 = Node 2 - * 011 = Node 3 - * 100 = Node 4 - * 101 = Node 5 - * 110 = Node 6 - * 111 = Node 7 - * [ 7: 7] Reserved - * [ 9: 8] Destination Link - * 00 = Link 0 - * 01 = Link 1 - * 10 = Link 2 - * 11 - Reserved - * [15:10] Reserved - * [23:16] Bus Number Base i - * This field defines the lowest bus number in configuration region i - * [31:24] Bus Number Limit i - * This field defines the highest bus number in configuration regin i - */ -// ADDRMAP_REG(0xE0), 0x0000FC88, 0x06000003, // AMD 8111 on link0 of CPU 0 - ADDRMAP_REG(0xE4), 0x0000FC88, 0x00000000, - ADDRMAP_REG(0xE8), 0x0000FC88, 0x00000000, - ADDRMAP_REG(0xEC), 0x0000FC88, 0x00000000, - }; - - int max; - max = ARRAY_SIZE(register_values); - setup_resource_map(register_values, max); -} diff --git a/src/mainboard/asus/m4a78-em/romstage.c b/src/mainboard/asus/m4a78-em/romstage.c deleted file mode 100644 index c52b35b22f..0000000000 --- a/src/mainboard/asus/m4a78-em/romstage.c +++ /dev/null @@ -1,227 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2010 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -//#define SYSTEM_TYPE 0 /* SERVER */ -#define SYSTEM_TYPE 1 /* DESKTOP */ -//#define SYSTEM_TYPE 2 /* MOBILE */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include "cpu/amd/quadcore/quadcore.c" - -#define SERIAL_DEV PNP_DEV(0x2e, IT8712F_SP1) -#define GPIO_DEV PNP_DEV(0x2e, IT8712F_GPIO) - -int spd_read_byte(unsigned int device, unsigned int address); - - -int spd_read_byte(u32 device, u32 address) -{ - return do_smbus_read_byte(SMBUS_IO_BASE, device, address); -} - -void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) -{ - struct sys_info *sysinfo = get_sysinfo(); - static const u8 spd_addr[] = {RC00, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, }; - u32 bsp_apicid = 0, val; - msr_t msr; - - timestamp_init(timestamp_get()); - timestamp_add_now(TS_START_ROMSTAGE); - - if (!cpu_init_detectedx && boot_cpu()) { - /* Nothing special needs to be done to find bus 0 */ - /* Allow the HT devices to be found */ - /* mov bsp to bus 0xff when > 8 nodes */ - set_bsp_node_CHtExtNodeCfgEn(); - enumerate_ht_chain(); - sb7xx_51xx_pci_port80(); - } - - post_code(0x30); - - if (bist == 0) { - bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo); /* mmconf is inited in init_cpus */ - /* All cores run this but the BSP(node0,core0) is the only core that returns. */ - } - - post_code(0x32); - - enable_rs780_dev8(); - sb7xx_51xx_lpc_init(); - - ite_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); - ite_kill_watchdog(GPIO_DEV); - - console_init(); - - /* Halt if there was a built in self test failure */ - report_bist_failure(bist); - - // Load MPB - val = cpuid_eax(1); - printk(BIOS_DEBUG, "BSP Family_Model: %08x\n", val); - printk(BIOS_DEBUG, "*sysinfo range: [%p,%p]\n",sysinfo,sysinfo+1); - printk(BIOS_DEBUG, "bsp_apicid = %02x\n", bsp_apicid); - printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx); - - /* Setup sysinfo defaults */ - set_sysinfo_in_ram(0); - - update_microcode(val); - - post_code(0x33); - - cpuSetAMDMSR(0); - post_code(0x34); - - amd_ht_init(sysinfo); - post_code(0x35); - - /* Setup nodes PCI space and start core 0 AP init. */ - finalize_node_setup(sysinfo); - - /* Setup any mainboard PCI settings etc. */ - setup_mb_resource_map(); - post_code(0x36); - - /* wait for all the APs core0 started by finalize_node_setup. */ - /* FIXME: A bunch of cores are going to start output to serial at once. - It would be nice to fixup prink spinlocks for ROM XIP mode. - I think it could be done by putting the spinlock flag in the cache - of the BSP located right after sysinfo. - */ - wait_all_core0_started(); - - #if CONFIG(LOGICAL_CPUS) - /* Core0 on each node is configured. Now setup any additional cores. */ - printk(BIOS_DEBUG, "start_other_cores()\n"); - start_other_cores(bsp_apicid); - post_code(0x37); - wait_all_other_cores_started(bsp_apicid); - #endif - - post_code(0x38); - - /* run _early_setup before soft-reset. */ - rs780_early_setup(); - sb7xx_51xx_early_setup(); - - #if CONFIG(SET_FIDVID) - msr = rdmsr(MSR_COFVID_STS); - printk(BIOS_DEBUG, "\nBegin FIDVID MSR 0xc0010071 0x%08x 0x%08x\n", msr.hi, msr.lo); - - /* FIXME: The sb fid change may survive the warm reset and only - need to be done once.*/ - enable_fid_change_on_sb(sysinfo->sbbusn, sysinfo->sbdn); - - post_code(0x39); - - if (!warm_reset_detect(0)) { // BSP is node 0 - init_fidvid_bsp(bsp_apicid, sysinfo->nodes); - } else { - init_fidvid_stage2(bsp_apicid, 0); // BSP is node 0 - } - - post_code(0x3A); - - /* show final fid and vid */ - msr = rdmsr(MSR_COFVID_STS); - printk(BIOS_DEBUG, "End FIDVIDMSR 0xc0010071 0x%08x 0x%08x\n", msr.hi, msr.lo); - #endif - - rs780_htinit(); - - /* Reset for HT, FIDVID, PLL and errata changes to take affect. */ - if (!warm_reset_detect(0)) { - printk(BIOS_INFO, "...WARM RESET...\n\n\n"); - soft_reset(); - die("After soft_reset - shouldn't see this message!!!\n"); - } - - post_code(0x3B); - - /* It's the time to set ctrl in sysinfo now; */ - printk(BIOS_DEBUG, "fill_mem_ctrl()\n"); - fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr); - - post_code(0x40); - - raminit_amdmct(sysinfo); - - cbmem_initialize_empty(); - post_code(0x41); - - amdmct_cbmem_store_info(sysinfo); - - sb7xx_51xx_before_pci_init(); - - post_code(0x42); -} - -/** - * BOOL AMD_CB_ManualBUIDSwapList(u8 Node, u8 Link, u8 **List) - * Description: - * This routine is called every time a non-coherent chain is processed. - * BUID assignment may be controlled explicitly on a non-coherent chain. Provide a - * swap list. The first part of the list controls the BUID assignment and the - * second part of the list provides the device to device linking. Device orientation - * can be detected automatically, or explicitly. See documentation for more details. - * - * Automatic non-coherent init assigns BUIDs starting at 1 and incrementing sequentially - * based on each device's unit count. - * - * Parameters: - * @param[in] node = The node on which this chain is located - * @param[in] link = The link on the host for this chain - * @param[out] List = supply a pointer to a list - */ -BOOL AMD_CB_ManualBUIDSwapList (u8 node, u8 link, const u8 **List) -{ - static const u8 swaplist[] = { 0xFF, CONFIG_HT_CHAIN_UNITID_BASE, CONFIG_HT_CHAIN_END_UNITID_BASE, 0xFF }; - /* If the BUID was adjusted in early_ht we need to do the manual override */ - if ((CONFIG_HT_CHAIN_UNITID_BASE != 0) && (CONFIG_HT_CHAIN_END_UNITID_BASE != 0)) { - printk(BIOS_DEBUG, "AMD_CB_ManualBUIDSwapList()\n"); - if ((node == 0) && (link == 0)) { /* BSP SB link */ - *List = swaplist; - return 1; - } - } - - return 0; -} diff --git a/src/mainboard/asus/m4a785-m/Kconfig b/src/mainboard/asus/m4a785-m/Kconfig deleted file mode 100644 index 22665efe72..0000000000 --- a/src/mainboard/asus/m4a785-m/Kconfig +++ /dev/null @@ -1,58 +0,0 @@ -if BOARD_ASUS_M4A785M - -config BOARD_SPECIFIC_OPTIONS - def_bool y - select CPU_AMD_SOCKET_AM3 - select DIMM_DDR2 - select NORTHBRIDGE_AMD_AMDFAM10 - select SOUTHBRIDGE_AMD_RS780 - select SOUTHBRIDGE_AMD_SB700 - select SOUTHBRIDGE_AMD_SB700_SKIP_ISA_DMA_INIT - select SUPERIO_ITE_IT8712F - select HAVE_OPTION_TABLE - select HAVE_PIRQ_TABLE - select HAVE_MP_TABLE - select SB_HT_CHAIN_UNITID_OFFSET_ONLY - select LIFT_BSP_APIC_ID - select HAVE_ACPI_TABLES - select BOARD_ROMSIZE_KB_1024 - select ENABLE_APIC_EXT_ID - select GFXUMA - -config MAINBOARD_DIR - string - default asus/m4a785-m - -config APIC_ID_OFFSET - hex - default 0x0 - -config MAINBOARD_PART_NUMBER - string - default "M4A785-M" - -config MAX_CPUS - int - default 8 - -config MAX_PHYSICAL_CPUS - int - default 2 - -config HT_CHAIN_END_UNITID_BASE - hex - default 0x1 - -config HT_CHAIN_UNITID_BASE - hex - default 0x0 - -config IRQ_SLOT_COUNT - int - default 19 - -config VGA_BIOS_ID - string - default "1002,9710" - -endif diff --git a/src/mainboard/asus/m4a785-m/Kconfig.name b/src/mainboard/asus/m4a785-m/Kconfig.name deleted file mode 100644 index 1ab150ffb3..0000000000 --- a/src/mainboard/asus/m4a785-m/Kconfig.name +++ /dev/null @@ -1,2 +0,0 @@ -config BOARD_ASUS_M4A785M - bool "M4A785-M" diff --git a/src/mainboard/asus/m4a785-m/Makefile.inc b/src/mainboard/asus/m4a785-m/Makefile.inc deleted file mode 100644 index 91d4b39c32..0000000000 --- a/src/mainboard/asus/m4a785-m/Makefile.inc +++ /dev/null @@ -1,16 +0,0 @@ -# -# This file is part of the coreboot project. -# -# This program is free software; you can redistribute it and/or modify -# it under the terms of the GNU General Public License as published by -# the Free Software Foundation; version 2 of the License. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# - -romstage-y += resourcemap.c - -ramstage-y += get_bus_conf.c diff --git a/src/mainboard/asus/m4a785-m/acpi/cpstate.asl b/src/mainboard/asus/m4a785-m/acpi/cpstate.asl deleted file mode 100644 index acaa5bae32..0000000000 --- a/src/mainboard/asus/m4a785-m/acpi/cpstate.asl +++ /dev/null @@ -1,80 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2010 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -/* This file defines the processor and performance state capability - * for each core in the system. It is included into the DSDT for each - * core. It assumes that each core of the system has the same performance - * characteristics. -*/ -/* -#include -DefinitionBlock ("DSDT.AML", "DSDT", 0x01, OEM_ID, ACPI_TABLE_CREATOR, 0x00010001) - { - Scope (\_PR) { - Device (CPU0) { - Name (_HID, "ACPI0007") - Name (_UID, 0) - #include "cpstate.asl" - } - Device (CPU1) { - Name (_HID, "ACPI0007") - Name (_UID, 1) - #include "cpstate.asl" - } - Device (CPU2) { - Name (_HID, "ACPI0007") - Name (_UID, 2) - #include "cpstate.asl" - } - Device (CPU3) { - Name (_HID, "ACPI0007") - Name (_UID, 3) - #include "cpstate.asl" - } - } -*/ - /* P-state support: The maximum number of P-states supported by the */ - /* CPUs we'll use is 6. */ - /* Get from AMI BIOS. */ - Name(_PSS, Package(){ - Package () - { - 0x00000AF0, - 0x0000BF81, - 0x00000002, - 0x00000002, - 0x00000000, - 0x00000000 - }, - - Package () - { - 0x00000578, - 0x000076F2, - 0x00000002, - 0x00000002, - 0x00000001, - 0x00000001 - } - }) - - Name(_PCT, Package(){ - ResourceTemplate(){Register(FFixedHW, 0, 0, 0)}, - ResourceTemplate(){Register(FFixedHW, 0, 0, 0)} - }) - - Method(_PPC, 0){ - Return(0) - } diff --git a/src/mainboard/asus/m4a785-m/acpi/ide.asl b/src/mainboard/asus/m4a785-m/acpi/ide.asl deleted file mode 100644 index 5c155cf301..0000000000 --- a/src/mainboard/asus/m4a785-m/acpi/ide.asl +++ /dev/null @@ -1,240 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2010 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -/* -Scope (_SB) { - Device(PCI0) { - Device(IDEC) { - Name(_ADR, 0x00140001) - #include "ide.asl" - } - } -} -*/ - -/* Some timing tables */ -Name(UDTT, Package(){ /* Udma timing table */ - 120, 90, 60, 45, 30, 20, 15, 0 /* UDMA modes 0 -> 6 */ -}) - -Name(MDTT, Package(){ /* MWDma timing table */ - 480, 150, 120, 0 /* Legacy DMA modes 0 -> 2 */ -}) - -Name(POTT, Package(){ /* Pio timing table */ - 600, 390, 270, 180, 120, 0 /* PIO modes 0 -> 4 */ -}) - -/* Some timing register value tables */ -Name(MDRT, Package(){ /* MWDma timing register table */ - 0x77, 0x21, 0x20, 0xFF /* Legacy DMA modes 0 -> 2 */ -}) - -Name(PORT, Package(){ - 0x99, 0x47, 0x34, 0x22, 0x20, 0x99 /* PIO modes 0 -> 4 */ -}) - -OperationRegion(ICRG, PCI_Config, 0x40, 0x20) /* ide control registers */ - Field(ICRG, AnyAcc, NoLock, Preserve) -{ - PPTS, 8, /* Primary PIO Slave Timing */ - PPTM, 8, /* Primary PIO Master Timing */ - OFFSET(0x04), PMTS, 8, /* Primary MWDMA Slave Timing */ - PMTM, 8, /* Primary MWDMA Master Timing */ - OFFSET(0x08), PPCR, 8, /* Primary PIO Control */ - OFFSET(0x0A), PPMM, 4, /* Primary PIO master Mode */ - PPSM, 4, /* Primary PIO slave Mode */ - OFFSET(0x14), PDCR, 2, /* Primary UDMA Control */ - OFFSET(0x16), PDMM, 4, /* Primary UltraDMA Mode */ - PDSM, 4, /* Primary UltraDMA Mode */ -} - -Method(GTTM, 1) /* get total time*/ -{ - Store(And(Arg0, 0x0F), Local0) /* Recovery Width */ - Increment(Local0) - Store(ShiftRight(Arg0, 4), Local1) /* Command Width */ - Increment(Local1) - Return(Multiply(30, Add(Local0, Local1))) -} - -Device(PRID) -{ - Name (_ADR, Zero) - Method(_GTM, 0) - { - NAME(OTBF, Buffer(20) { /* out buffer */ - 0xFF, 0xFF, 0xFF, 0xFF, - 0xFF, 0xFF, 0xFF, 0xFF, - 0xFF, 0xFF, 0xFF, 0xFF, - 0xFF, 0xFF, 0xFF, 0xFF, 0x00, 0x00, 0x00, 0x00 - }) - - CreateDwordField(OTBF, 0, PSD0) /* PIO spd0 */ - CreateDwordField(OTBF, 4, DSD0) /* DMA spd0 */ - CreateDwordField(OTBF, 8, PSD1) /* PIO spd1 */ - CreateDwordField(OTBF, 12, DSD1) /* DMA spd1 */ - CreateDwordField(OTBF, 16, BFFG) /* buffer flags */ - - /* Just return if the channel is disabled */ - If(And(PPCR, 0x01)) { /* primary PIO control */ - Return(OTBF) - } - - /* Always tell them independent timing available and IOChannelReady used on both drives */ - Or(BFFG, 0x1A, BFFG) - - Store(GTTM(PPTM), PSD0) /* save total time of primary PIO master timming to PIO spd0 */ - Store(GTTM(PPTS), PSD1) /* save total time of primary PIO slave Timing to PIO spd1 */ - - If(And(PDCR, 0x01)) { /* It's under UDMA mode */ - Or(BFFG, 0x01, BFFG) - Store(DerefOf(Index(UDTT, PDMM)), DSD0) - } - Else { - Store(GTTM(PMTM), DSD0) /* Primary MWDMA Master Timing, DmaSpd0 */ - } - - If(And(PDCR, 0x02)) { /* It's under UDMA mode */ - Or(BFFG, 0x04, BFFG) - Store(DerefOf(Index(UDTT, PDSM)), DSD1) - } - Else { - Store(GTTM(PMTS), DSD1) /* Primary MWDMA Slave Timing, DmaSpd0 */ - } - - Return(OTBF) /* out buffer */ - } /* End Method(_GTM) */ - - Method(_STM, 3, NotSerialized) - { - NAME(INBF, Buffer(20) { /* in buffer */ - 0xFF, 0xFF, 0xFF, 0xFF, - 0xFF, 0xFF, 0xFF, 0xFF, - 0xFF, 0xFF, 0xFF, 0xFF, - 0xFF, 0xFF, 0xFF, 0xFF, 0x00, 0x00, 0x00, 0x00 - }) - - CreateDwordField(INBF, 0, PSD0) /* PIO spd0 */ - CreateDwordField(INBF, 4, DSD0) /* PIO spd0 */ - CreateDwordField(INBF, 8, PSD1) /* PIO spd1 */ - CreateDwordField(INBF, 12, DSD1) /* DMA spd1 */ - CreateDwordField(INBF, 16, BFFG) /*buffer flag */ - - Store(Match(POTT, MLE, PSD0, MTR, 0, 0), Local0) - Divide(Local0, 5, PPMM,) /* Primary PIO master Mode */ - Store(Match(POTT, MLE, PSD1, MTR, 0, 0), Local1) - Divide(Local1, 5, PPSM,) /* Primary PIO slave Mode */ - - Store(DerefOf(Index(PORT, Local0)), PPTM) /* Primary PIO Master Timing */ - Store(DerefOf(Index(PORT, Local1)), PPTS) /* Primary PIO Slave Timing */ - - If(And(BFFG, 0x01)) { /* Drive 0 is under UDMA mode */ - Store(Match(UDTT, MLE, DSD0, MTR, 0, 0), Local0) - Divide(Local0, 7, PDMM,) - Or(PDCR, 0x01, PDCR) - } - Else { - If(LNotEqual(DSD0, 0xFFFFFFFF)) { - Store(Match(MDTT, MLE, DSD0, MTR, 0, 0), Local0) - Store(DerefOf(Index(MDRT, Local0)), PMTM) - } - } - - If(And(BFFG, 0x04)) { /* Drive 1 is under UDMA mode */ - Store(Match(UDTT, MLE, DSD1, MTR, 0, 0), Local0) - Divide(Local0, 7, PDSM,) - Or(PDCR, 0x02, PDCR) - } - Else { - If(LNotEqual(DSD1, 0xFFFFFFFF)) { - Store(Match(MDTT, MLE, DSD1, MTR, 0, 0), Local0) - Store(DerefOf(Index(MDRT, Local0)), PMTS) - } - } - /* Return(INBF) */ - } /*End Method(_STM) */ - Device(MST) - { - Name(_ADR, 0) - Method(_GTF) { - Name(CMBF, Buffer(21) { - 0x03, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xEF, - 0x03, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xEF, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xF5 - }) - CreateByteField(CMBF, 1, POMD) - CreateByteField(CMBF, 8, DMMD) - CreateByteField(CMBF, 5, CMDA) - CreateByteField(CMBF, 12, CMDB) - CreateByteField(CMBF, 19, CMDC) - - Store(0xA0, CMDA) - Store(0xA0, CMDB) - Store(0xA0, CMDC) - - Or(PPMM, 0x08, POMD) - - If(And(PDCR, 0x01)) { - Or(PDMM, 0x40, DMMD) - } - Else { - Store(Match - (MDTT, MLE, GTTM(PMTM), - MTR, 0, 0), Local0) - If(LLess(Local0, 3)) { - Or(0x20, Local0, DMMD) - } - } - Return(CMBF) - } - } /* End Device(MST) */ - - Device(SLAV) - { - Name(_ADR, 1) - Method(_GTF) { - Name(CMBF, Buffer(21) { - 0x03, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xEF, - 0x03, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xEF, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xF5 - }) - CreateByteField(CMBF, 1, POMD) - CreateByteField(CMBF, 8, DMMD) - CreateByteField(CMBF, 5, CMDA) - CreateByteField(CMBF, 12, CMDB) - CreateByteField(CMBF, 19, CMDC) - - Store(0xB0, CMDA) - Store(0xB0, CMDB) - Store(0xB0, CMDC) - - Or(PPSM, 0x08, POMD) - - If(And(PDCR, 0x02)) { - Or(PDSM, 0x40, DMMD) - } - Else { - Store(Match - (MDTT, MLE, GTTM(PMTS), - MTR, 0, 0), Local0) - If(LLess(Local0, 3)) { - Or(0x20, Local0, DMMD) - } - } - Return(CMBF) - } - } /* End Device(SLAV) */ -} diff --git a/src/mainboard/asus/m4a785-m/acpi/routing.asl b/src/mainboard/asus/m4a785-m/acpi/routing.asl deleted file mode 100644 index 072aa2117f..0000000000 --- a/src/mainboard/asus/m4a785-m/acpi/routing.asl +++ /dev/null @@ -1,297 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2010 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -/* -#include -DefinitionBlock ("DSDT.AML", "DSDT", 0x01, OEM_ID, ACPI_TABLE_CREATOR, 0x00010001 - ) - { - #include "routing.asl" - } -*/ - -/* Routing is in System Bus scope */ -Scope(\_SB) { - Name(PR0, Package(){ - /* NB devices */ - /* Bus 0, Dev 0 - RS780 Host Controller */ - /* Bus 0, Dev 1 - PCI Bridge for Internal Graphics */ - /* Bus 0, Dev 2 - PCIe Bridge for x8 PCIe Slot (GFX0) */ - Package(){0x0002FFFF, 0, INTC, 0 }, - Package(){0x0002FFFF, 1, INTD, 0 }, - Package(){0x0002FFFF, 2, INTA, 0 }, - Package(){0x0002FFFF, 3, INTB, 0 }, - /* Bus 0, Dev 3 - PCIe graphics port 1 bridge */ - /* Bus 0, Dev 4 - PCIe Bridge for Express Card Slot */ - Package(){0x0004FFFF, 0, INTA, 0 }, - Package(){0x0004FFFF, 1, INTB, 0 }, - Package(){0x0004FFFF, 2, INTC, 0 }, - Package(){0x0004FFFF, 3, INTD, 0 }, - /* Bus 0, Dev 5 - General purpose PCIe bridge 5 */ - /* Package(){0x0005FFFF, 0, INTB, 0 }, */ - /* Package(){0x0005FFFF, 1, INTC, 0 }, */ - /* Package(){0x0005FFFF, 2, INTD, 0 }, */ - /* Package(){0x0005FFFF, 3, INTA, 0 }, */ - /* Bus 0, Dev 6 - PCIe Bridge for Ethernet Chip */ - Package(){0x0006FFFF, 0, INTC, 0 }, - Package(){0x0006FFFF, 1, INTD, 0 }, - Package(){0x0006FFFF, 2, INTA, 0 }, - Package(){0x0006FFFF, 3, INTB, 0 }, - /* Bus 0, Dev 7 - PCIe Bridge for x1 PCIe Slot */ - Package(){0x0007FFFF, 0, INTD, 0 }, - Package(){0x0007FFFF, 1, INTA, 0 }, - Package(){0x0007FFFF, 2, INTB, 0 }, - Package(){0x0007FFFF, 3, INTC, 0 }, - /* Bus 0, Funct 8 - Southbridge port (normally hidden) */ - - /* SB devices */ - /* Bus 0, Dev 17 - SATA controller #2 */ - /* Bus 0, Dev 18 - SATA controller #1 */ - Package(){0x0011FFFF, 1, INTA, 0 }, - - /* Bus 0, Dev 19 - USB: OHCI, funct 0-4; EHCI, funct 5 */ - Package(){0x0012FFFF, 0, INTA, 0 }, - Package(){0x0012FFFF, 1, INTB, 0 }, - Package(){0x0013FFFF, 0, INTA, 0 }, - Package(){0x0013FFFF, 1, INTB, 0 }, - Package(){0x0014FFFF, 2, INTA, 0 }, - - /* Bus 0, Dev 20 - F0:SMBus/ACPI,F1:IDE;F2:HDAudio;F3:LPC;F4:PCIBridge;F5:AC97 Audio;F6:AC97 Modem */ - Package(){0x0014FFFF, 0, INTA, 0 }, - Package(){0x0014FFFF, 1, INTB, 0 }, - Package(){0x0014FFFF, 2, INTC, 0 }, - Package(){0x0014FFFF, 3, INTD, 0 }, - }) - - Name(APR0, Package(){ - /* NB devices in APIC mode */ - /* Bus 0, Dev 0 - RS780 Host Controller */ - - /* Bus 0, Dev 1 - PCI Bridge for Internal Graphics */ - /* Package(){0x0001FFFF, 0, 0, 18 }, */ - /* Package(){0x0001FFFF, 1, 0, 19 }, */ - - /* Bus 0, Dev 2 - PCIe Bridge for x8 PCIe Slot (GFX0) */ - Package(){0x0002FFFF, 0, 0, 18 }, - /* Package(){0x0002FFFF, 1, 0, 19 }, */ - /* Package(){0x0002FFFF, 2, 0, 16 }, */ - /* Package(){0x0002FFFF, 3, 0, 17 }, */ - - /* Bus 0, Dev 3 - PCIe graphics port 1 bridge */ - Package(){0x0003FFFF, 0, 0, 19 }, - - /* Bus 0, Dev 4 - PCIe Bridge for Express Card Slot */ - Package(){0x0004FFFF, 0, 0, 16 }, - /* Package(){0x0004FFFF, 1, 0, 17 }, */ - /* Package(){0x0004FFFF, 2, 0, 18 }, */ - /* Package(){0x0004FFFF, 3, 0, 19 }, */ - - /* Bus 0, Dev 5 - General purpose PCIe bridge 5 */ - /* Package(){0x0005FFFF, 0, 0, 17 }, */ - /* Package(){0x0005FFFF, 1, 0, 18 }, */ - /* Package(){0x0005FFFF, 2, 0, 19 }, */ - /* Package(){0x0005FFFF, 3, 0, 16 }, */ - - /* Bus 0, Dev 6 - General purpose PCIe bridge 6 */ - /* Package(){0x0006FFFF, 0, 0, 18 }, */ - /* Package(){0x0006FFFF, 1, 0, 19 }, */ - /* Package(){0x0006FFFF, 2, 0, 16 }, */ - /* Package(){0x0006FFFF, 3, 0, 17 }, */ - - /* Bus 0, Dev 7 - PCIe Bridge for network card */ - /* Package(){0x0007FFFF, 0, 0, 19 }, */ - /* Package(){0x0007FFFF, 1, 0, 16 }, */ - /* Package(){0x0007FFFF, 2, 0, 17 }, */ - /* Package(){0x0007FFFF, 3, 0, 18 }, */ - - /* Bus 0, Dev 9 - PCIe Bridge for network card */ - Package(){0x0009FFFF, 0, 0, 17 }, - /* Package(){0x0009FFFF, 1, 0, 16 }, */ - /* Package(){0x0009FFFF, 2, 0, 17 }, */ - /* Package(){0x0009FFFF, 3, 0, 18 }, */ - /* Bus 0, Dev A - PCIe Bridge for network card */ - Package(){0x000AFFFF, 0, 0, 18 }, - /* Package(){0x000AFFFF, 1, 0, 16 }, */ - /* Package(){0x000AFFFF, 2, 0, 17 }, */ - /* Package(){0x000AFFFF, 3, 0, 18 }, */ - /* Bus 0, Funct 8 - Southbridge port (normally hidden) */ - - /* SB devices in APIC mode */ - /* Bus 0, Dev 17 - SATA controller #2 */ - /* Bus 0, Dev 18 - SATA controller #1 */ - Package(){0x0011FFFF, 0, 0, 22 }, - - /* Bus 0, Dev 19 - USB: OHCI, funct 0-4; EHCI, funct 5 */ - Package(){0x0012FFFF, 0, 0, 16 }, - Package(){0x0012FFFF, 1, 0, 17 }, - Package(){0x0013FFFF, 0, 0, 18 }, - Package(){0x0013FFFF, 1, 0, 19 }, - Package(){0x0014FFFF, 0, 0, 16 }, - /* Package(){0x00130004, 2, 0, 18 }, */ - /* Package(){0x00130005, 3, 0, 19 }, */ - - /* Bus 0, Dev 20 - F0:SMBus/ACPI, F1:IDE; F2:HDAudio; F3:LPC; F4:PCIBridge; F5:AC97 Audio; F6:AC97 Modem */ - Package(){0x0014FFFF, 0, 0, 16 }, - Package(){0x0014FFFF, 1, 0, 17 }, - Package(){0x0014FFFF, 2, 0, 18 }, - Package(){0x0014FFFF, 3, 0, 19 }, - /* Package(){0x00140004, 2, 0, 18 }, */ - /* Package(){0x00140004, 3, 0, 19 }, */ - /* Package(){0x00140005, 1, 0, 17 }, */ - /* Package(){0x00140006, 1, 0, 17 }, */ - }) - - Name(PR1, Package(){ - /* Internal graphics - RS780 VGA, Bus1, Dev5 */ - Package(){0x0005FFFF, 0, INTA, 0 }, - Package(){0x0005FFFF, 1, INTB, 0 }, - Package(){0x0005FFFF, 2, INTC, 0 }, - Package(){0x0005FFFF, 3, INTD, 0 }, - }) - - Name(APR1, Package(){ - /* Internal graphics - RS780 VGA, Bus1, Dev5 */ - Package(){0x0005FFFF, 0, 0, 18 }, - Package(){0x0005FFFF, 1, 0, 19 }, - /* Package(){0x0005FFFF, 2, 0, 20 }, */ - /* Package(){0x0005FFFF, 3, 0, 17 }, */ - }) - - Name(PS2, Package(){ - /* The external GFX - Hooked to PCIe slot 2 */ - Package(){0x0000FFFF, 0, INTC, 0 }, - Package(){0x0000FFFF, 1, INTD, 0 }, - Package(){0x0000FFFF, 2, INTA, 0 }, - Package(){0x0000FFFF, 3, INTB, 0 }, - }) - - Name(APS2, Package(){ - /* The external GFX - Hooked to PCIe slot 2 */ - Package(){0x0000FFFF, 0, 0, 18 }, - Package(){0x0000FFFF, 1, 0, 19 }, - Package(){0x0000FFFF, 2, 0, 16 }, - Package(){0x0000FFFF, 3, 0, 17 }, - }) - - Name(PS4, Package(){ - /* PCIe slot - Hooked to PCIe slot 4 */ - Package(){0x0000FFFF, 0, INTA, 0 }, - Package(){0x0000FFFF, 1, INTB, 0 }, - Package(){0x0000FFFF, 2, INTC, 0 }, - Package(){0x0000FFFF, 3, INTD, 0 }, - }) - - Name(APS4, Package(){ - /* PCIe slot - Hooked to PCIe slot 4 */ - Package(){0x0000FFFF, 0, 0, 16 }, - Package(){0x0000FFFF, 1, 0, 17 }, - Package(){0x0000FFFF, 2, 0, 18 }, - Package(){0x0000FFFF, 3, 0, 19 }, - }) - - Name(PS5, Package(){ - /* PCIe slot - Hooked to PCIe slot 5 */ - Package(){0x0000FFFF, 0, INTB, 0 }, - Package(){0x0000FFFF, 1, INTC, 0 }, - Package(){0x0000FFFF, 2, INTD, 0 }, - Package(){0x0000FFFF, 3, INTA, 0 }, - }) - - Name(APS5, Package(){ - /* PCIe slot - Hooked to PCIe slot 5 */ - Package(){0x0000FFFF, 0, 0, 17 }, - Package(){0x0000FFFF, 1, 0, 18 }, - Package(){0x0000FFFF, 2, 0, 19 }, - Package(){0x0000FFFF, 3, 0, 16 }, - }) - - Name(PS6, Package(){ - /* PCIe slot - Hooked to PCIe slot 6 */ - Package(){0x0000FFFF, 0, INTC, 0 }, - Package(){0x0000FFFF, 1, INTD, 0 }, - Package(){0x0000FFFF, 2, INTA, 0 }, - Package(){0x0000FFFF, 3, INTB, 0 }, - }) - - Name(APS6, Package(){ - /* PCIe slot - Hooked to PCIe slot 6 */ - Package(){0x0000FFFF, 0, 0, 18 }, - Package(){0x0000FFFF, 1, 0, 19 }, - Package(){0x0000FFFF, 2, 0, 16 }, - Package(){0x0000FFFF, 3, 0, 17 }, - }) - - Name(PS7, Package(){ - /* The onboard Ethernet chip - Hooked to PCIe slot 7 */ - Package(){0x0000FFFF, 0, INTD, 0 }, - Package(){0x0000FFFF, 1, INTA, 0 }, - Package(){0x0000FFFF, 2, INTB, 0 }, - Package(){0x0000FFFF, 3, INTC, 0 }, - }) - - Name(APS7, Package(){ - /* The onboard Ethernet chip - Hooked to PCIe slot 7 */ - Package(){0x0000FFFF, 0, 0, 19 }, - Package(){0x0000FFFF, 1, 0, 16 }, - Package(){0x0000FFFF, 2, 0, 17 }, - Package(){0x0000FFFF, 3, 0, 18 }, - }) - Name(PS9, Package(){ - /* PCIe slot - Hooked to PCIe slot 9 */ - Package(){0x0000FFFF, 0, INTD, 0 }, - Package(){0x0000FFFF, 1, INTA, 0 }, - Package(){0x0000FFFF, 2, INTB, 0 }, - Package(){0x0000FFFF, 3, INTC, 0 }, - }) - - Name(APS9, Package(){ - /* PCIe slot - Hooked to PCIe slot 9 */ - Package(){0x0000FFFF, 0, 0, 17 }, - Package(){0x0000FFFF, 1, 0, 18 }, - Package(){0x0000FFFF, 2, 0, 19 }, - Package(){0x0000FFFF, 3, 0, 16 }, - }) - Name(PSa, Package(){ - /* PCIe slot - Hooked to PCIe slot 10 */ - Package(){0x0000FFFF, 0, INTD, 0 }, - Package(){0x0000FFFF, 1, INTA, 0 }, - Package(){0x0000FFFF, 2, INTB, 0 }, - Package(){0x0000FFFF, 3, INTC, 0 }, - }) - - Name(APSa, Package(){ - /* PCIe slot - Hooked to PCIe slot 10 */ - Package(){0x0000FFFF, 0, 0, 18 }, - Package(){0x0000FFFF, 1, 0, 19 }, - Package(){0x0000FFFF, 2, 0, 16 }, - Package(){0x0000FFFF, 3, 0, 17 }, - }) - - Name(PCIB, Package(){ - /* PCI slots: slot 0, slot 1, slot 2 behind Dev14, Fun4. */ - Package(){0x0005FFFF, 0, 0, 0x14 }, - Package(){0x0005FFFF, 1, 0, 0x15 }, - Package(){0x0005FFFF, 2, 0, 0x16 }, - Package(){0x0005FFFF, 3, 0, 0x17 }, - Package(){0x0006FFFF, 0, 0, 0x15 }, - Package(){0x0006FFFF, 1, 0, 0x16 }, - Package(){0x0006FFFF, 2, 0, 0x17 }, - Package(){0x0006FFFF, 3, 0, 0x14 }, - Package(){0x0007FFFF, 0, 0, 0x16 }, - Package(){0x0007FFFF, 1, 0, 0x17 }, - Package(){0x0007FFFF, 2, 0, 0x14 }, - Package(){0x0007FFFF, 3, 0, 0x15 }, - }) -} diff --git a/src/mainboard/asus/m4a785-m/acpi/sata.asl b/src/mainboard/asus/m4a785-m/acpi/sata.asl deleted file mode 100644 index cb9b221ba3..0000000000 --- a/src/mainboard/asus/m4a785-m/acpi/sata.asl +++ /dev/null @@ -1,145 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2010 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -/* simple name description */ - -/* -Scope (_SB) { - Device(PCI0) { - Device(SATA) { - Name(_ADR, 0x00110000) - #include "sata.asl" - } - } -} -*/ - -Name(STTM, Buffer(20) { - 0x78, 0x00, 0x00, 0x00, 0x0f, 0x00, 0x00, 0x00, - 0x78, 0x00, 0x00, 0x00, 0x0f, 0x00, 0x00, 0x00, - 0x1f, 0x00, 0x00, 0x00 -}) - -/* Start by clearing the PhyRdyChg bits */ -Method(_INI) { - \_GPE._L1F() -} - -Device(PMRY) -{ - Name(_ADR, 0) - Method(_GTM, 0x0, NotSerialized) { - Return(STTM) - } - Method(_STM, 0x3, NotSerialized) {} - - Device(PMST) { - Name(_ADR, 0) - Method(_STA,0) { - if (LGreater(P0IS,0)) { - return (0x0F) /* sata is visible */ - } - else { - return (0x00) /* sata is missing */ - } - } - }/* end of PMST */ - - Device(PSLA) - { - Name(_ADR, 1) - Method(_STA,0) { - if (LGreater(P1IS,0)) { - return (0x0F) /* sata is visible */ - } - else { - return (0x00) /* sata is missing */ - } - } - } /* end of PSLA */ -} /* end of PMRY */ - - -Device(SEDY) -{ - Name(_ADR, 1) /* IDE Scondary Channel */ - Method(_GTM, 0x0, NotSerialized) { - Return(STTM) - } - Method(_STM, 0x3, NotSerialized) {} - - Device(SMST) - { - Name(_ADR, 0) - Method(_STA,0) { - if (LGreater(P2IS,0)) { - return (0x0F) /* sata is visible */ - } - else { - return (0x00) /* sata is missing */ - } - } - } /* end of SMST */ - - Device(SSLA) - { - Name(_ADR, 1) - Method(_STA,0) { - if (LGreater(P3IS,0)) { - return (0x0F) /* sata is visible */ - } - else { - return (0x00) /* sata is missing */ - } - } - } /* end of SSLA */ -} /* end of SEDY */ - -/* SATA Hot Plug Support */ -Scope(\_GPE) { - Method(_L1F,0x0,NotSerialized) { - if (\_SB.P0PR) { - if (LGreater(\_SB.P0IS,0)) { - sleep(32) - } - Notify(\_SB.PCI0.STCR.PMRY.PMST, 0x01) /* NOTIFY_DEVICE_CHECK */ - store(one, \_SB.P0PR) - } - - if (\_SB.P1PR) { - if (LGreater(\_SB.P1IS,0)) { - sleep(32) - } - Notify(\_SB.PCI0.STCR.PMRY.PSLA, 0x01) /* NOTIFY_DEVICE_CHECK */ - store(one, \_SB.P1PR) - } - - if (\_SB.P2PR) { - if (LGreater(\_SB.P2IS,0)) { - sleep(32) - } - Notify(\_SB.PCI0.STCR.SEDY.SMST, 0x01) /* NOTIFY_DEVICE_CHECK */ - store(one, \_SB.P2PR) - } - - if (\_SB.P3PR) { - if (LGreater(\_SB.P3IS,0)) { - sleep(32) - } - Notify(\_SB.PCI0.STCR.SEDY.SSLA, 0x01) /* NOTIFY_DEVICE_CHECK */ - store(one, \_SB.P3PR) - } - } -} diff --git a/src/mainboard/asus/m4a785-m/acpi/usb.asl b/src/mainboard/asus/m4a785-m/acpi/usb.asl deleted file mode 100644 index a3ccb97ff9..0000000000 --- a/src/mainboard/asus/m4a785-m/acpi/usb.asl +++ /dev/null @@ -1,158 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2010 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -/* simple name description */ -/* -#include -DefinitionBlock ("DSDT.AML", "DSDT", 0x01, OEM_ID, ACPI_TABLE_CREATOR, 0x00010001 - ) - { - #include "usb.asl" - } -*/ -Method(UCOC, 0) { - Sleep(20) - Store(0x13,CMTI) - Store(0,GPSL) -} - -/* USB Port 0 overcurrent uses Gpm 0 */ -If(LLessEqual(UOM0,9)) { - Scope (\_GPE) { - Method (_L13) { - UCOC() - if(LEqual(GPB0,PLC0)) { - Not(PLC0,PLC0) - Store(PLC0, \_SB.PT0D) - } - } - } -} - -/* USB Port 1 overcurrent uses Gpm 1 */ -If (LLessEqual(UOM1,9)) { - Scope (\_GPE) { - Method (_L14) { - UCOC() - if (LEqual(GPB1,PLC1)) { - Not(PLC1,PLC1) - Store(PLC1, \_SB.PT1D) - } - } - } -} - -/* USB Port 2 overcurrent uses Gpm 2 */ -If (LLessEqual(UOM2,9)) { - Scope (\_GPE) { - Method (_L15) { - UCOC() - if (LEqual(GPB2,PLC2)) { - Not(PLC2,PLC2) - Store(PLC2, \_SB.PT2D) - } - } - } -} - -/* USB Port 3 overcurrent uses Gpm 3 */ -If (LLessEqual(UOM3,9)) { - Scope (\_GPE) { - Method (_L16) { - UCOC() - if (LEqual(GPB3,PLC3)) { - Not(PLC3,PLC3) - Store(PLC3, \_SB.PT3D) - } - } - } -} - -/* USB Port 4 overcurrent uses Gpm 4 */ -If (LLessEqual(UOM4,9)) { - Scope (\_GPE) { - Method (_L19) { - UCOC() - if (LEqual(GPB4,PLC4)) { - Not(PLC4,PLC4) - Store(PLC4, \_SB.PT4D) - } - } - } -} - -/* USB Port 5 overcurrent uses Gpm 5 */ -If (LLessEqual(UOM5,9)) { - Scope (\_GPE) { - Method (_L1A) { - UCOC() - if (LEqual(GPB5,PLC5)) { - Not(PLC5,PLC5) - Store(PLC5, \_SB.PT5D) - } - } - } -} - -/* USB Port 6 overcurrent uses Gpm 6 */ -If (LLessEqual(UOM6,9)) { - Scope (\_GPE) { - /* Method (_L1C) { */ - Method (_L06) { - UCOC() - if (LEqual(GPB6,PLC6)) { - Not(PLC6,PLC6) - Store(PLC6, \_SB.PT6D) - } - } - } -} - -/* USB Port 7 overcurrent uses Gpm 7 */ -If (LLessEqual(UOM7,9)) { - Scope (\_GPE) { - /* Method (_L1D) { */ - Method (_L07) { - UCOC() - if (LEqual(GPB7,PLC7)) { - Not(PLC7,PLC7) - Store(PLC7, \_SB.PT7D) - } - } - } -} - -/* USB Port 8 overcurrent uses Gpm 8 */ -If (LLessEqual(UOM8,9)) { - Scope (\_GPE) { - Method (_L17) { - if (LEqual(G8IS,PLC8)) { - Not(PLC8,PLC8) - Store(PLC8, \_SB.PT8D) - } - } - } -} - -/* USB Port 9 overcurrent uses Gpm 9 */ -If (LLessEqual(UOM9,9)) { - Scope (\_GPE) { - Method (_L0E) { - if (LEqual(G9IS,0)) { - Store(1,\_SB.PT9D) - } - } - } -} diff --git a/src/mainboard/asus/m4a785-m/acpi_tables.c b/src/mainboard/asus/m4a785-m/acpi_tables.c deleted file mode 100644 index cb263f90f2..0000000000 --- a/src/mainboard/asus/m4a785-m/acpi_tables.c +++ /dev/null @@ -1,44 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2010 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include -#include - -unsigned long acpi_fill_madt(unsigned long current) -{ - /* create all subtables for processors */ - current = acpi_create_madt_lapics(current); - - /* Write SB700 IOAPIC, only one */ - current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, - CONFIG_MAX_CPUS, IO_APIC_ADDR, 0); - - current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) - current, 0, 0, 2, 0); - current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) - current, 0, 9, 9, 0xF); - /* 0: mean bus 0--->ISA */ - /* 0: PIC 0 */ - /* 2: APIC 2 */ - /* 5 mean: 0101 --> Edge-triggered, Active high */ - - /* create all subtables for processors */ - /* current = acpi_create_madt_lapic_nmis(current, 5, 1); */ - /* 1: LINT1 connect to NMI */ - - return current; -} diff --git a/src/mainboard/asus/m4a785-m/board_info.txt b/src/mainboard/asus/m4a785-m/board_info.txt deleted file mode 100644 index c95f6f188b..0000000000 --- a/src/mainboard/asus/m4a785-m/board_info.txt +++ /dev/null @@ -1,7 +0,0 @@ -Category: desktop -Board URL: http://www.asus.com/Motherboards/AMD_AM2Plus/M4A785M/ -ROM package: DIP8 -ROM protocol: SPI -ROM socketed: y -Flashrom support: y -Release year: 2009 diff --git a/src/mainboard/asus/m4a785-m/cmos.layout b/src/mainboard/asus/m4a785-m/cmos.layout deleted file mode 100644 index 6c3d3f6c9e..0000000000 --- a/src/mainboard/asus/m4a785-m/cmos.layout +++ /dev/null @@ -1,52 +0,0 @@ -entries - -0 384 r 0 reserved_memory -384 1 e 4 boot_option -388 4 h 0 reboot_counter -#392 3 r 0 unused -395 1 e 1 hw_scrubber -396 1 e 1 interleave_chip_selects -397 2 e 8 max_mem_clock -399 1 e 2 multi_core -400 1 e 1 power_on_after_fail -412 4 e 6 debug_level -440 4 e 9 slow_cpu -444 1 e 1 nmi -445 1 e 1 gart -456 1 e 1 ECC_memory -728 256 h 0 user_data -984 16 h 0 check_sum -# Reserve the extended AMD configuration registers -1000 24 r 0 amd_reserved - - - -enumerations - -#ID value text -1 0 Disable -1 1 Enable -2 0 Enable -2 1 Disable -4 0 Fallback -4 1 Normal -6 5 Notice -6 6 Info -6 7 Debug -6 8 Spew -8 0 400Mhz -8 1 333Mhz -8 2 266Mhz -8 3 200Mhz -9 0 off -9 1 87.5% -9 2 75.0% -9 3 62.5% -9 4 50.0% -9 5 37.5% -9 6 25.0% -9 7 12.5% - -checksums - -checksum 392 983 984 diff --git a/src/mainboard/asus/m4a785-m/devicetree.cb b/src/mainboard/asus/m4a785-m/devicetree.cb deleted file mode 100644 index 9dc937ccc7..0000000000 --- a/src/mainboard/asus/m4a785-m/devicetree.cb +++ /dev/null @@ -1,106 +0,0 @@ -chip northbridge/amd/amdfam10/root_complex - device cpu_cluster 0 on - chip cpu/amd/socket_AM3 #L1 and DDR2 - device lapic 0 on end - end - end - device domain 0 on - subsystemid 0x1043 0x83a2 inherit - chip northbridge/amd/amdfam10 - device pci 18.0 on # northbridge - chip southbridge/amd/rs780 - device pci 0.0 on end # HT 0x9600 - device pci 1.0 on end # Internal Graphics P2P bridge 0x9602 - device pci 2.0 off end # PCIE P2P bridge (external graphics) 0x9603 - device pci 3.0 off end # PCIE P2P bridge 0x960b - device pci 4.0 off end # PCIE P2P bridge 0x9604 - device pci 5.0 off end # PCIE P2P bridge 0x9605 - device pci 6.0 off end # PCIE P2P bridge 0x9606 - device pci 7.0 off end # PCIE P2P bridge 0x9607 - device pci 8.0 off end # NB/SB Link P2P bridge - device pci 9.0 off end # - device pci a.0 on end # bridge to RTL8111/8168B PCI Express Gigabit Ethernet - register "gppsb_configuration" = "1" # Configuration B - register "gpp_configuration" = "3" # Configuration D default - register "port_enable" = "0x6fc" - register "gfx_dev2_dev3" = "1" - register "gfx_dual_slot" = "2" - - register "gfx_lane_reversal" = "0" - register "gfx_tmds" = "0" - register "gfx_compliance" = "0" - register "gfx_reconfiguration" = "1" - register "gfx_link_width" = "0" - end - chip southbridge/amd/sb700 # it is under NB/SB Link, but on the same pri bus - device pci 11.0 on end # SATA - device pci 12.0 on end # USB - device pci 12.1 on end # USB - device pci 12.2 on end # USB - device pci 13.0 on end # USB - device pci 13.1 on end # USB - device pci 13.2 on end # USB - device pci 14.0 on # SM - chip drivers/generic/generic #dimm 0-0-0 - device i2c 50 on end - end - chip drivers/generic/generic #dimm 0-0-1 - device i2c 51 on end - end - chip drivers/generic/generic #dimm 0-1-0 - device i2c 52 on end - end - chip drivers/generic/generic #dimm 0-1-1 - device i2c 53 on end - end - end # SM - device pci 14.1 on end # IDE 0x439c - device pci 14.2 on end # HDA 0x4383 - device pci 14.3 on # LPC 0x439d - chip superio/ite/it8712f - device pnp 2e.0 off end # Floppy - device pnp 2e.1 on # Com1 - io 0x60 = 0x3f8 - irq 0x70 = 4 - end - device pnp 2e.2 off # Com2 - io 0x60 = 0x2f8 - irq 0x70 = 3 - end - device pnp 2e.3 off # Parallel Port - io 0x60 = 0x378 - irq 0x70 = 7 - end - device pnp 2e.4 off end # Environment Controller - device pnp 2e.5 on # Keyboard - io 0x60 = 0x60 - io 0x62 = 0x64 - irq 0x70 = 1 - end - device pnp 2e.6 on # Mouse - irq 0x70 = 12 - end - device pnp 2e.7 off # GPIO, must be closed for unresolved reason. - end - device pnp 2e.8 off # MIDI - end - device pnp 2e.9 off # GAME - end - device pnp 2e.a off end # CIR - end #superio - end #LPC - device pci 14.4 on end # PCI to PCI Bridge [1002:4384] - device pci 14.5 on end # USB 2 - register "boot_switch_sata_ide" = "0" # 0: boot from SATA. 1: IDE - end #southbridge/amd/sb700 - end # device pci 18.0 - - device pci 18.0 on end - device pci 18.0 on end - device pci 18.1 on end - device pci 18.2 on end - device pci 18.3 on end - device pci 18.4 on end - end # chip northbridge - end #domain -end # northbridge/amd/amdfam10/root_complex diff --git a/src/mainboard/asus/m4a785-m/dsdt.asl b/src/mainboard/asus/m4a785-m/dsdt.asl deleted file mode 100644 index eec3093b8e..0000000000 --- a/src/mainboard/asus/m4a785-m/dsdt.asl +++ /dev/null @@ -1,1718 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2010 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -/* DefinitionBlock Statement */ -#include -DefinitionBlock ( - "DSDT.AML", /* Output filename */ - "DSDT", /* Signature */ - 0x02, /* DSDT Revision, needs to be 2 for 64bit */ - OEM_ID, - ACPI_TABLE_CREATOR, - 0x00010001 /* OEM Revision */ - ) -{ /* Start of ASL file */ - /* #include */ /* Include global debug methods if needed */ - - /* Data to be patched by the BIOS during POST */ - /* FIXME the patching is not done yet! */ - /* Memory related values */ - Name(LOMH, 0x0) /* Start of unused memory in C0000-E0000 range */ - Name(PBAD, 0x0) /* Address of BIOS area (If TOM2 != 0, Addr >> 16) */ - Name(PBLN, 0x0) /* Length of BIOS area */ - - Name(PCBA, 0xE0000000) /* Base address of PCIe config space */ - Name(HPBA, 0xFED00000) /* Base address of HPET table */ - - /* USB overcurrent mapping pins. */ - Name(UOM0, 0) - Name(UOM1, 2) - Name(UOM2, 0) - Name(UOM3, 7) - Name(UOM4, 2) - Name(UOM5, 2) - Name(UOM6, 6) - Name(UOM7, 2) - Name(UOM8, 6) - Name(UOM9, 6) - - /* Some global data */ - Name(OSVR, 3) /* Assume nothing. WinXp = 1, Vista = 2, Linux = 3, WinCE = 4 */ - Name(OSV, Ones) /* Assume nothing */ - Name(PMOD, One) /* Assume APIC */ - - /* - * Processor Object - * - */ - Scope (\_PR) { /* define processor scope */ - Device (CPU0) { - Name (_HID, "ACPI0007") - Name (_UID, 0) - #include "acpi/cpstate.asl" - } - Device (CPU1) { - Name (_HID, "ACPI0007") - Name (_UID, 1) - #include "acpi/cpstate.asl" - } - Device (CPU2) { - Name (_HID, "ACPI0007") - Name (_UID, 2) - #include "acpi/cpstate.asl" - } - Device (CPU3) { - Name (_HID, "ACPI0007") - Name (_UID, 3) - #include "acpi/cpstate.asl" - } - } /* End _PR scope */ - - /* PIC IRQ mapping registers, C00h-C01h */ - OperationRegion(PRQM, SystemIO, 0x00000C00, 0x00000002) - Field(PRQM, ByteAcc, NoLock, Preserve) { - PRQI, 0x00000008, - PRQD, 0x00000008, /* Offset: 1h */ - } - IndexField(PRQI, PRQD, ByteAcc, NoLock, Preserve) { - PINA, 0x00000008, /* Index 0 */ - PINB, 0x00000008, /* Index 1 */ - PINC, 0x00000008, /* Index 2 */ - PIND, 0x00000008, /* Index 3 */ - AINT, 0x00000008, /* Index 4 */ - SINT, 0x00000008, /* Index 5 */ - , 0x00000008, /* Index 6 */ - AAUD, 0x00000008, /* Index 7 */ - AMOD, 0x00000008, /* Index 8 */ - PINE, 0x00000008, /* Index 9 */ - PINF, 0x00000008, /* Index A */ - PING, 0x00000008, /* Index B */ - PINH, 0x00000008, /* Index C */ - } - - /* PCI Error control register */ - OperationRegion(PERC, SystemIO, 0x00000C14, 0x00000001) - Field(PERC, ByteAcc, NoLock, Preserve) { - SENS, 0x00000001, - PENS, 0x00000001, - SENE, 0x00000001, - PENE, 0x00000001, - } - - /* Client Management index/data registers */ - OperationRegion(CMT, SystemIO, 0x00000C50, 0x00000002) - Field(CMT, ByteAcc, NoLock, Preserve) { - CMTI, 8, - /* Client Management Data register */ - G64E, 1, - G64O, 1, - G32O, 2, - , 2, - GPSL, 2, - } - - /* GPM Port register */ - OperationRegion(GPT, SystemIO, 0x00000C52, 0x00000001) - Field(GPT, ByteAcc, NoLock, Preserve) { - GPB0,1, - GPB1,1, - GPB2,1, - GPB3,1, - GPB4,1, - GPB5,1, - GPB6,1, - GPB7,1, - } - - /* Flash ROM program enable register */ - OperationRegion(FRE, SystemIO, 0x00000C6F, 0x00000001) - Field(FRE, ByteAcc, NoLock, Preserve) { - , 0x00000006, - FLRE, 0x00000001, - } - - /* PM2 index/data registers */ - OperationRegion(PM2R, SystemIO, 0x00000CD0, 0x00000002) - Field(PM2R, ByteAcc, NoLock, Preserve) { - PM2I, 0x00000008, - PM2D, 0x00000008, - } - - /* Power Management I/O registers */ - OperationRegion(PIOR, SystemIO, 0x00000CD6, 0x00000002) - Field(PIOR, ByteAcc, NoLock, Preserve) { - PIOI, 0x00000008, - PIOD, 0x00000008, - } - IndexField (PIOI, PIOD, ByteAcc, NoLock, Preserve) { - Offset(0x00), /* MiscControl */ - , 1, - T1EE, 1, - T2EE, 1, - Offset(0x01), /* MiscStatus */ - , 1, - T1E, 1, - T2E, 1, - Offset(0x04), /* SmiWakeUpEventEnable3 */ - , 7, - SSEN, 1, - Offset(0x07), /* SmiWakeUpEventStatus3 */ - , 7, - CSSM, 1, - Offset(0x10), /* AcpiEnable */ - , 6, - PWDE, 1, - Offset(0x1C), /* ProgramIoEnable */ - , 3, - MKME, 1, - IO3E, 1, - IO2E, 1, - IO1E, 1, - IO0E, 1, - Offset(0x1D), /* IOMonitorStatus */ - , 3, - MKMS, 1, - IO3S, 1, - IO2S, 1, - IO1S, 1, - IO0S,1, - Offset(0x20), /* AcpiPmEvtBlk */ - APEB, 16, - Offset(0x36), /* GEvtLevelConfig */ - , 6, - ELC6, 1, - ELC7, 1, - Offset(0x37), /* GPMLevelConfig0 */ - , 3, - PLC0, 1, - PLC1, 1, - PLC2, 1, - PLC3, 1, - PLC8, 1, - Offset(0x38), /* GPMLevelConfig1 */ - , 1, - PLC4, 1, - PLC5, 1, - , 1, - PLC6, 1, - PLC7, 1, - Offset(0x3B), /* PMEStatus1 */ - GP0S, 1, - GM4S, 1, - GM5S, 1, - APS, 1, - GM6S, 1, - GM7S, 1, - GP2S, 1, - STSS, 1, - Offset(0x55), /* SoftPciRst */ - SPRE, 1, - , 1, - , 1, - PNAT, 1, - PWMK, 1, - PWNS, 1, - - /* Offset(0x61), */ /* Options_1 */ - /* ,7, */ - /* R617,1, */ - - Offset(0x65), /* UsbPMControl */ - , 4, - URRE, 1, - Offset(0x68), /* MiscEnable68 */ - , 3, - TMTE, 1, - , 1, - Offset(0x92), /* GEVENTIN */ - , 7, - E7IS, 1, - Offset(0x96), /* GPM98IN */ - G8IS, 1, - G9IS, 1, - Offset(0x9A), /* EnhanceControl */ - ,7, - HPDE, 1, - Offset(0xA8), /* PIO7654Enable */ - IO4E, 1, - IO5E, 1, - IO6E, 1, - IO7E, 1, - Offset(0xA9), /* PIO7654Status */ - IO4S, 1, - IO5S, 1, - IO6S, 1, - IO7S, 1, - } - - /* PM1 Event Block - * First word is PM1_Status, Second word is PM1_Enable - */ - OperationRegion(P1EB, SystemIO, APEB, 0x04) - Field(P1EB, ByteAcc, NoLock, Preserve) { - TMST, 1, - , 3, - BMST, 1, - GBST, 1, - Offset(0x01), - PBST, 1, - , 1, - RTST, 1, - , 3, - PWST, 1, - SPWS, 1, - Offset(0x02), - TMEN, 1, - , 4, - GBEN, 1, - Offset(0x03), - PBEN, 1, - , 1, - RTEN, 1, - , 3, - PWDA, 1, - } - - Scope(\_SB) { - /* PCIe Configuration Space for 16 busses */ - OperationRegion(PCFG, SystemMemory, PCBA, 0x01000000) /* Each bus consumes 1MB */ - Field(PCFG, ByteAcc, NoLock, Preserve) { - /* Byte offsets are computed using the following technique: - * ((bus number + 1) * ((device number * 8) * 4096)) + register offset - * The 8 comes from 8 functions per device, and 4096 bytes per function config space - */ - Offset(0x00088024), /* Byte offset to SATA register 24h - Bus 0, Device 17, Function 0 */ - STB5, 32, - Offset(0x00098042), /* Byte offset to OHCI0 register 42h - Bus 0, Device 19, Function 0 */ - PT0D, 1, - PT1D, 1, - PT2D, 1, - PT3D, 1, - PT4D, 1, - PT5D, 1, - PT6D, 1, - PT7D, 1, - PT8D, 1, - PT9D, 1, - Offset(0x000A0004), /* Byte offset to SMBUS register 4h - Bus 0, Device 20, Function 0 */ - SBIE, 1, - SBME, 1, - Offset(0x000A0008), /* Byte offset to SMBUS register 8h - Bus 0, Device 20, Function 0 */ - SBRI, 8, - Offset(0x000A0014), /* Byte offset to SMBUS register 14h - Bus 0, Device 20, Function 0 */ - SBB1, 32, - Offset(0x000A0078), /* Byte offset to SMBUS register 78h - Bus 0, Device 20, Function 0 */ - ,14, - P92E, 1, /* Port92 decode enable */ - } - - OperationRegion(SB5, SystemMemory, STB5, 0x1000) - Field(SB5, AnyAcc, NoLock, Preserve){ - /* Port 0 */ - Offset(0x120), /* Port 0 Task file status */ - P0ER, 1, - , 2, - P0DQ, 1, - , 3, - P0BY, 1, - Offset(0x128), /* Port 0 Serial ATA status */ - P0DD, 4, - , 4, - P0IS, 4, - Offset(0x12C), /* Port 0 Serial ATA control */ - P0DI, 4, - Offset(0x130), /* Port 0 Serial ATA error */ - , 16, - P0PR, 1, - - /* Port 1 */ - offset(0x1A0), /* Port 1 Task file status */ - P1ER, 1, - , 2, - P1DQ, 1, - , 3, - P1BY, 1, - Offset(0x1A8), /* Port 1 Serial ATA status */ - P1DD, 4, - , 4, - P1IS, 4, - Offset(0x1AC), /* Port 1 Serial ATA control */ - P1DI, 4, - Offset(0x1B0), /* Port 1 Serial ATA error */ - , 16, - P1PR, 1, - - /* Port 2 */ - Offset(0x220), /* Port 2 Task file status */ - P2ER, 1, - , 2, - P2DQ, 1, - , 3, - P2BY, 1, - Offset(0x228), /* Port 2 Serial ATA status */ - P2DD, 4, - , 4, - P2IS, 4, - Offset(0x22C), /* Port 2 Serial ATA control */ - P2DI, 4, - Offset(0x230), /* Port 2 Serial ATA error */ - , 16, - P2PR, 1, - - /* Port 3 */ - Offset(0x2A0), /* Port 3 Task file status */ - P3ER, 1, - , 2, - P3DQ, 1, - , 3, - P3BY, 1, - Offset(0x2A8), /* Port 3 Serial ATA status */ - P3DD, 4, - , 4, - P3IS, 4, - Offset(0x2AC), /* Port 3 Serial ATA control */ - P3DI, 4, - Offset(0x2B0), /* Port 3 Serial ATA error */ - , 16, - P3PR, 1, - } - } - - - #include "acpi/routing.asl" - - Scope(\_SB) { - - Method(OSFL, 0){ - - if(LNotEqual(OSVR, Ones)) {Return(OSVR)} /* OS version was already detected */ - - if(CondRefOf(\_OSI)) - { - Store(1, OSVR) /* Assume some form of XP */ - if (\_OSI("Windows 2006")) /* Vista */ - { - Store(2, OSVR) - } - } else { - If(WCMP(\_OS,"Linux")) { - Store(3, OSVR) /* Linux */ - } Else { - Store(4, OSVR) /* Gotta be WinCE */ - } - } - Return(OSVR) - } - - Method(_PIC, 0x01, NotSerialized) - { - If (Arg0) - { - \_SB.CIRQ() - } - Store(Arg0, PMOD) - } - Method(CIRQ, 0x00, NotSerialized){ - Store(0, PINA) - Store(0, PINB) - Store(0, PINC) - Store(0, PIND) - Store(0, PINE) - Store(0, PINF) - Store(0, PING) - Store(0, PINH) - } - - Name(IRQB, ResourceTemplate(){ - IRQ(Level,ActiveLow,Shared){15} - }) - - Name(IRQP, ResourceTemplate(){ - IRQ(Level,ActiveLow,Exclusive){3, 4, 5, 7, 10, 11, 12, 15} - }) - - Name(PITF, ResourceTemplate(){ - IRQ(Level,ActiveLow,Exclusive){9} - }) - - Device(INTA) { - Name(_HID, EISAID("PNP0C0F")) - Name(_UID, 1) - - Method(_STA, 0) { - if (PINA) { - Return(0x0B) /* sata is invisible */ - } else { - Return(0x09) /* sata is disabled */ - } - } /* End Method(_SB.INTA._STA) */ - - Method(_DIS ,0) { - /* DBGO("\\_SB\\LNKA\\_DIS\n") */ - Store(0, PINA) - } /* End Method(_SB.INTA._DIS) */ - - Method(_PRS ,0) { - /* DBGO("\\_SB\\LNKA\\_PRS\n") */ - Return(IRQP) - } /* Method(_SB.INTA._PRS) */ - - Method(_CRS ,0) { - /* DBGO("\\_SB\\LNKA\\_CRS\n") */ - CreateWordField(IRQB, 0x1, IRQN) - ShiftLeft(1, PINA, IRQN) - Return(IRQB) - } /* Method(_SB.INTA._CRS) */ - - Method(_SRS, 1) { - /* DBGO("\\_SB\\LNKA\\_CRS\n") */ - CreateWordField(ARG0, 1, IRQM) - - /* Use lowest available IRQ */ - FindSetRightBit(IRQM, Local0) - if (Local0) { - Decrement(Local0) - } - Store(Local0, PINA) - } /* End Method(_SB.INTA._SRS) */ - } /* End Device(INTA) */ - - Device(INTB) { - Name(_HID, EISAID("PNP0C0F")) - Name(_UID, 2) - - Method(_STA, 0) { - if (PINB) { - Return(0x0B) /* sata is invisible */ - } else { - Return(0x09) /* sata is disabled */ - } - } /* End Method(_SB.INTB._STA) */ - - Method(_DIS ,0) { - /* DBGO("\\_SB\\LNKB\\_DIS\n") */ - Store(0, PINB) - } /* End Method(_SB.INTB._DIS) */ - - Method(_PRS ,0) { - /* DBGO("\\_SB\\LNKB\\_PRS\n") */ - Return(IRQP) - } /* Method(_SB.INTB._PRS) */ - - Method(_CRS ,0) { - /* DBGO("\\_SB\\LNKB\\_CRS\n") */ - CreateWordField(IRQB, 0x1, IRQN) - ShiftLeft(1, PINB, IRQN) - Return(IRQB) - } /* Method(_SB.INTB._CRS) */ - - Method(_SRS, 1) { - /* DBGO("\\_SB\\LNKB\\_CRS\n") */ - CreateWordField(ARG0, 1, IRQM) - - /* Use lowest available IRQ */ - FindSetRightBit(IRQM, Local0) - if (Local0) { - Decrement(Local0) - } - Store(Local0, PINB) - } /* End Method(_SB.INTB._SRS) */ - } /* End Device(INTB) */ - - Device(INTC) { - Name(_HID, EISAID("PNP0C0F")) - Name(_UID, 3) - - Method(_STA, 0) { - if (PINC) { - Return(0x0B) /* sata is invisible */ - } else { - Return(0x09) /* sata is disabled */ - } - } /* End Method(_SB.INTC._STA) */ - - Method(_DIS ,0) { - /* DBGO("\\_SB\\LNKC\\_DIS\n") */ - Store(0, PINC) - } /* End Method(_SB.INTC._DIS) */ - - Method(_PRS ,0) { - /* DBGO("\\_SB\\LNKC\\_PRS\n") */ - Return(IRQP) - } /* Method(_SB.INTC._PRS) */ - - Method(_CRS ,0) { - /* DBGO("\\_SB\\LNKC\\_CRS\n") */ - CreateWordField(IRQB, 0x1, IRQN) - ShiftLeft(1, PINC, IRQN) - Return(IRQB) - } /* Method(_SB.INTC._CRS) */ - - Method(_SRS, 1) { - /* DBGO("\\_SB\\LNKC\\_CRS\n") */ - CreateWordField(ARG0, 1, IRQM) - - /* Use lowest available IRQ */ - FindSetRightBit(IRQM, Local0) - if (Local0) { - Decrement(Local0) - } - Store(Local0, PINC) - } /* End Method(_SB.INTC._SRS) */ - } /* End Device(INTC) */ - - Device(INTD) { - Name(_HID, EISAID("PNP0C0F")) - Name(_UID, 4) - - Method(_STA, 0) { - if (PIND) { - Return(0x0B) /* sata is invisible */ - } else { - Return(0x09) /* sata is disabled */ - } - } /* End Method(_SB.INTD._STA) */ - - Method(_DIS ,0) { - /* DBGO("\\_SB\\LNKD\\_DIS\n") */ - Store(0, PIND) - } /* End Method(_SB.INTD._DIS) */ - - Method(_PRS ,0) { - /* DBGO("\\_SB\\LNKD\\_PRS\n") */ - Return(IRQP) - } /* Method(_SB.INTD._PRS) */ - - Method(_CRS ,0) { - /* DBGO("\\_SB\\LNKD\\_CRS\n") */ - CreateWordField(IRQB, 0x1, IRQN) - ShiftLeft(1, PIND, IRQN) - Return(IRQB) - } /* Method(_SB.INTD._CRS) */ - - Method(_SRS, 1) { - /* DBGO("\\_SB\\LNKD\\_CRS\n") */ - CreateWordField(ARG0, 1, IRQM) - - /* Use lowest available IRQ */ - FindSetRightBit(IRQM, Local0) - if (Local0) { - Decrement(Local0) - } - Store(Local0, PIND) - } /* End Method(_SB.INTD._SRS) */ - } /* End Device(INTD) */ - - Device(INTE) { - Name(_HID, EISAID("PNP0C0F")) - Name(_UID, 5) - - Method(_STA, 0) { - if (PINE) { - Return(0x0B) /* sata is invisible */ - } else { - Return(0x09) /* sata is disabled */ - } - } /* End Method(_SB.INTE._STA) */ - - Method(_DIS ,0) { - /* DBGO("\\_SB\\LNKE\\_DIS\n") */ - Store(0, PINE) - } /* End Method(_SB.INTE._DIS) */ - - Method(_PRS ,0) { - /* DBGO("\\_SB\\LNKE\\_PRS\n") */ - Return(IRQP) - } /* Method(_SB.INTE._PRS) */ - - Method(_CRS ,0) { - /* DBGO("\\_SB\\LNKE\\_CRS\n") */ - CreateWordField(IRQB, 0x1, IRQN) - ShiftLeft(1, PINE, IRQN) - Return(IRQB) - } /* Method(_SB.INTE._CRS) */ - - Method(_SRS, 1) { - /* DBGO("\\_SB\\LNKE\\_CRS\n") */ - CreateWordField(ARG0, 1, IRQM) - - /* Use lowest available IRQ */ - FindSetRightBit(IRQM, Local0) - if (Local0) { - Decrement(Local0) - } - Store(Local0, PINE) - } /* End Method(_SB.INTE._SRS) */ - } /* End Device(INTE) */ - - Device(INTF) { - Name(_HID, EISAID("PNP0C0F")) - Name(_UID, 6) - - Method(_STA, 0) { - if (PINF) { - Return(0x0B) /* sata is invisible */ - } else { - Return(0x09) /* sata is disabled */ - } - } /* End Method(_SB.INTF._STA) */ - - Method(_DIS ,0) { - /* DBGO("\\_SB\\LNKF\\_DIS\n") */ - Store(0, PINF) - } /* End Method(_SB.INTF._DIS) */ - - Method(_PRS ,0) { - /* DBGO("\\_SB\\LNKF\\_PRS\n") */ - Return(PITF) - } /* Method(_SB.INTF._PRS) */ - - Method(_CRS ,0) { - /* DBGO("\\_SB\\LNKF\\_CRS\n") */ - CreateWordField(IRQB, 0x1, IRQN) - ShiftLeft(1, PINF, IRQN) - Return(IRQB) - } /* Method(_SB.INTF._CRS) */ - - Method(_SRS, 1) { - /* DBGO("\\_SB\\LNKF\\_CRS\n") */ - CreateWordField(ARG0, 1, IRQM) - - /* Use lowest available IRQ */ - FindSetRightBit(IRQM, Local0) - if (Local0) { - Decrement(Local0) - } - Store(Local0, PINF) - } /* End Method(_SB.INTF._SRS) */ - } /* End Device(INTF) */ - - Device(INTG) { - Name(_HID, EISAID("PNP0C0F")) - Name(_UID, 7) - - Method(_STA, 0) { - if (PING) { - Return(0x0B) /* sata is invisible */ - } else { - Return(0x09) /* sata is disabled */ - } - } /* End Method(_SB.INTG._STA) */ - - Method(_DIS ,0) { - /* DBGO("\\_SB\\LNKG\\_DIS\n") */ - Store(0, PING) - } /* End Method(_SB.INTG._DIS) */ - - Method(_PRS ,0) { - /* DBGO("\\_SB\\LNKG\\_PRS\n") */ - Return(IRQP) - } /* Method(_SB.INTG._CRS) */ - - Method(_CRS ,0) { - /* DBGO("\\_SB\\LNKG\\_CRS\n") */ - CreateWordField(IRQB, 0x1, IRQN) - ShiftLeft(1, PING, IRQN) - Return(IRQB) - } /* Method(_SB.INTG._CRS) */ - - Method(_SRS, 1) { - /* DBGO("\\_SB\\LNKG\\_CRS\n") */ - CreateWordField(ARG0, 1, IRQM) - - /* Use lowest available IRQ */ - FindSetRightBit(IRQM, Local0) - if (Local0) { - Decrement(Local0) - } - Store(Local0, PING) - } /* End Method(_SB.INTG._SRS) */ - } /* End Device(INTG) */ - - Device(INTH) { - Name(_HID, EISAID("PNP0C0F")) - Name(_UID, 8) - - Method(_STA, 0) { - if (PINH) { - Return(0x0B) /* sata is invisible */ - } else { - Return(0x09) /* sata is disabled */ - } - } /* End Method(_SB.INTH._STA) */ - - Method(_DIS ,0) { - /* DBGO("\\_SB\\LNKH\\_DIS\n") */ - Store(0, PINH) - } /* End Method(_SB.INTH._DIS) */ - - Method(_PRS ,0) { - /* DBGO("\\_SB\\LNKH\\_PRS\n") */ - Return(IRQP) - } /* Method(_SB.INTH._CRS) */ - - Method(_CRS ,0) { - /* DBGO("\\_SB\\LNKH\\_CRS\n") */ - CreateWordField(IRQB, 0x1, IRQN) - ShiftLeft(1, PINH, IRQN) - Return(IRQB) - } /* Method(_SB.INTH._CRS) */ - - Method(_SRS, 1) { - /* DBGO("\\_SB\\LNKH\\_CRS\n") */ - CreateWordField(ARG0, 1, IRQM) - - /* Use lowest available IRQ */ - FindSetRightBit(IRQM, Local0) - if (Local0) { - Decrement(Local0) - } - Store(Local0, PINH) - } /* End Method(_SB.INTH._SRS) */ - } /* End Device(INTH) */ - - } /* End Scope(_SB) */ - - #include - - /* Wake status package */ - Name(WKST,Package(){Zero, Zero}) - - /* - * \_PTS - Prepare to Sleep method - * - * Entry: - * Arg0=The value of the sleeping state S1=1, S2=2, etc - * - * Exit: - * -none- - * - * The _PTS control method is executed at the beginning of the sleep process - * for S1-S5. The sleeping value is passed to the _PTS control method. This - * control method may be executed a relatively long time before entering the - * sleep state and the OS may abort the operation without notification to - * the ACPI driver. This method cannot modify the configuration or power - * state of any device in the system. - */ - Method(\_PTS, 1) { - /* DBGO("\\_PTS\n") */ - /* DBGO("From S0 to S") */ - /* DBGO(Arg0) */ - /* DBGO("\n") */ - - /* Don't allow PCIRST# to reset USB */ - if (LEqual(Arg0,3)){ - Store(0,URRE) - } - - /* Clear sleep SMI status flag and enable sleep SMI trap. */ - /*Store(One, CSSM) - Store(One, SSEN)*/ - - /* On older chips, clear PciExpWakeDisEn */ - /*if (LLessEqual(\_SB.SBRI, 0x13)) { - * Store(0,\_SB.PWDE) - *} - */ - - /* Clear wake status structure. */ - Store(0, Index(WKST,0)) - Store(0, Index(WKST,1)) - \_SB.PCI0.SIOS (Arg0) - } /* End Method(\_PTS) */ - - /* - * The following method results in a "not a valid reserved NameSeg" - * warning so I have commented it out for the duration. It isn't - * used, so it could be removed. - * - * - * \_GTS OEM Going To Sleep method - * - * Entry: - * Arg0=The value of the sleeping state S1=1, S2=2 - * - * Exit: - * -none- - * - * Method(\_GTS, 1) { - * DBGO("\\_GTS\n") - * DBGO("From S0 to S") - * DBGO(Arg0) - * DBGO("\n") - * } - */ - - /* - * \_BFS OEM Back From Sleep method - * - * Entry: - * Arg0=The value of the sleeping state S1=1, S2=2 - * - * Exit: - * -none- - */ - Method(\_BFS, 1) { - /* DBGO("\\_BFS\n") */ - /* DBGO("From S") */ - /* DBGO(Arg0) */ - /* DBGO(" to S0\n") */ - } - - /* - * \_WAK System Wake method - * - * Entry: - * Arg0=The value of the sleeping state S1=1, S2=2 - * - * Exit: - * Return package of 2 DWords - * Dword 1 - Status - * 0x00000000 wake succeeded - * 0x00000001 Wake was signaled but failed due to lack of power - * 0x00000002 Wake was signaled but failed due to thermal condition - * Dword 2 - Power Supply state - * if non-zero the effective S-state the power supply entered - */ - Method(\_WAK, 1) { - /* DBGO("\\_WAK\n") */ - /* DBGO("From S") */ - /* DBGO(Arg0) */ - /* DBGO(" to S0\n") */ - - /* Re-enable HPET */ - Store(1,HPDE) - - /* Restore PCIRST# so it resets USB */ - if (LEqual(Arg0,3)){ - Store(1,URRE) - } - - /* Arbitrarily clear PciExpWakeStatus */ - Store(PWST, Local1) - Store(Local1, PWST) - - /* if (DeRefOf(Index(WKST,0))) { - * Store(0, Index(WKST,1)) - * } else { - * Store(Arg0, Index(WKST,1)) - * } - */ - \_SB.PCI0.SIOW () - Return(WKST) - } /* End Method(\_WAK) */ - - Scope(\_GPE) { /* Start Scope GPE */ - /* General event 0 */ - /* Method(_L00) { - * DBGO("\\_GPE\\_L00\n") - * } - */ - - /* General event 1 */ - /* Method(_L01) { - * DBGO("\\_GPE\\_L00\n") - * } - */ - - /* General event 2 */ - /* Method(_L02) { - * DBGO("\\_GPE\\_L00\n") - * } - */ - - /* General event 3 */ - Method(_L03) { - /* DBGO("\\_GPE\\_L00\n") */ - Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ - } - - /* General event 4 */ - /* Method(_L04) { - * DBGO("\\_GPE\\_L00\n") - * } - */ - - /* General event 5 */ - /* Method(_L05) { - * DBGO("\\_GPE\\_L00\n") - * } - */ - - /* General event 6 - Used for GPM6, moved to USB.asl */ - /* Method(_L06) { - * DBGO("\\_GPE\\_L00\n") - * } - */ - - /* General event 7 - Used for GPM7, moved to USB.asl */ - /* Method(_L07) { - * DBGO("\\_GPE\\_L07\n") - * } - */ - - /* Legacy PM event */ - Method(_L08) { - /* DBGO("\\_GPE\\_L08\n") */ - } - - /* Temp warning (TWarn) event */ - Method(_L09) { - /* DBGO("\\_GPE\\_L09\n") */ - Notify (\_TZ.TZ00, 0x80) - } - - /* Reserved */ - /* Method(_L0A) { - * DBGO("\\_GPE\\_L0A\n") - * } - */ - - /* USB controller PME# */ - Method(_L0B) { - /* DBGO("\\_GPE\\_L0B\n") */ - Notify(\_SB.PCI0.UOH1, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(\_SB.PCI0.UOH2, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(\_SB.PCI0.UOH3, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(\_SB.PCI0.UOH4, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(\_SB.PCI0.UOH5, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(\_SB.PCI0.UEH1, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ - } - - /* AC97 controller PME# */ - /* Method(_L0C) { - * DBGO("\\_GPE\\_L0C\n") - * } - */ - - /* OtherTherm PME# */ - /* Method(_L0D) { - * DBGO("\\_GPE\\_L0D\n") - * } - */ - - /* GPM9 SCI event - Moved to USB.asl */ - /* Method(_L0E) { - * DBGO("\\_GPE\\_L0E\n") - * } - */ - - /* PCIe HotPlug event */ - /* Method(_L0F) { - * DBGO("\\_GPE\\_L0F\n") - * } - */ - - /* ExtEvent0 SCI event */ - Method(_L10) { - /* DBGO("\\_GPE\\_L10\n") */ - } - - - /* ExtEvent1 SCI event */ - Method(_L11) { - /* DBGO("\\_GPE\\_L11\n") */ - } - - /* PCIe PME# event */ - /* Method(_L12) { - * DBGO("\\_GPE\\_L12\n") - * } - */ - - /* GPM0 SCI event - Moved to USB.asl */ - /* Method(_L13) { - * DBGO("\\_GPE\\_L13\n") - * } - */ - - /* GPM1 SCI event - Moved to USB.asl */ - /* Method(_L14) { - * DBGO("\\_GPE\\_L14\n") - * } - */ - - /* GPM2 SCI event - Moved to USB.asl */ - /* Method(_L15) { - * DBGO("\\_GPE\\_L15\n") - * } - */ - - /* GPM3 SCI event - Moved to USB.asl */ - /* Method(_L16) { - * DBGO("\\_GPE\\_L16\n") - * } - */ - - /* GPM8 SCI event - Moved to USB.asl */ - /* Method(_L17) { - * DBGO("\\_GPE\\_L17\n") - * } - */ - - /* GPIO0 or GEvent8 event */ - Method(_L18) { - /* DBGO("\\_GPE\\_L18\n") */ - Notify(\_SB.PCI0.PBR2, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(\_SB.PCI0.PBR4, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(\_SB.PCI0.PBR5, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(\_SB.PCI0.PBR6, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(\_SB.PCI0.PBR7, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ - } - - /* GPM4 SCI event - Moved to USB.asl */ - /* Method(_L19) { - * DBGO("\\_GPE\\_L19\n") - * } - */ - - /* GPM5 SCI event - Moved to USB.asl */ - /* Method(_L1A) { - * DBGO("\\_GPE\\_L1A\n") - * } - */ - - /* Azalia SCI event */ - Method(_L1B) { - /* DBGO("\\_GPE\\_L1B\n") */ - Notify(\_SB.PCI0.AZHD, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ - } - - /* GPM6 SCI event - Reassigned to _L06 */ - /* Method(_L1C) { - * DBGO("\\_GPE\\_L1C\n") - * } - */ - - /* GPM7 SCI event - Reassigned to _L07 */ - /* Method(_L1D) { - * DBGO("\\_GPE\\_L1D\n") - * } - */ - - /* GPIO2 or GPIO66 SCI event */ - /* Method(_L1E) { - * DBGO("\\_GPE\\_L1E\n") - * } - */ - - /* SATA SCI event - Moved to sata.asl */ - /* Method(_L1F) { - * DBGO("\\_GPE\\_L1F\n") - * } - */ - - } /* End Scope GPE */ - - #include "acpi/usb.asl" - - /* System Bus */ - Scope(\_SB) { /* Start \_SB scope */ - #include /* global utility methods expected within the \_SB scope */ - - /* _SB.PCI0 */ - /* Note: Only need HID on Primary Bus */ - Device(PCI0) { - External (TOM1) - External (TOM2) /* ( >> 20) to make it fit into 32 bit for XP */ - Name(_HID, EISAID("PNP0A03")) - Name(_ADR, 0x00180000) /* Dev# = BSP Dev#, Func# = 0 */ - Method(_BBN, 0) { /* Bus number = 0 */ - Return(0) - } - Method(_STA, 0) { - /* DBGO("\\_SB\\PCI0\\_STA\n") */ - Return(0x0B) /* Status is visible */ - } - - Method(_PRT,0) { - If(PMOD){ Return(APR0) } /* APIC mode */ - Return (PR0) /* PIC Mode */ - } /* end _PRT */ - - /* Describe the Northbridge devices */ - Device(AMRT) { - Name(_ADR, 0x00000000) - } /* end AMRT */ - - /* The internal GFX bridge */ - Device(AGPB) { - Name(_ADR, 0x00010000) - Name(_PRW, Package() {0x18, 4}) - Method(_PRT,0) { - Return (APR1) - } - } /* end AGPB */ - - /* The external GFX bridge */ - Device(PBR2) { - Name(_ADR, 0x00020000) - Name(_PRW, Package() {0x18, 4}) - Method(_PRT,0) { - If(PMOD){ Return(APS2) } /* APIC mode */ - Return (PS2) /* PIC Mode */ - } /* end _PRT */ - } /* end PBR2 */ - - /* Dev3 is also an external GFX bridge, not used in Herring */ - - Device(PBR4) { - Name(_ADR, 0x00040000) - Name(_PRW, Package() {0x18, 4}) - Method(_PRT,0) { - If(PMOD){ Return(APS4) } /* APIC mode */ - Return (PS4) /* PIC Mode */ - } /* end _PRT */ - } /* end PBR4 */ - - Device(PBR5) { - Name(_ADR, 0x00050000) - Name(_PRW, Package() {0x18, 4}) - Method(_PRT,0) { - If(PMOD){ Return(APS5) } /* APIC mode */ - Return (PS5) /* PIC Mode */ - } /* end _PRT */ - } /* end PBR5 */ - - Device(PBR6) { - Name(_ADR, 0x00060000) - Name(_PRW, Package() {0x18, 4}) - Method(_PRT,0) { - If(PMOD){ Return(APS6) } /* APIC mode */ - Return (PS6) /* PIC Mode */ - } /* end _PRT */ - } /* end PBR6 */ - - /* The onboard EtherNet chip */ - Device(PBR7) { - Name(_ADR, 0x00070000) - Name(_PRW, Package() {0x18, 4}) - Method(_PRT,0) { - If(PMOD){ Return(APS7) } /* APIC mode */ - Return (PS7) /* PIC Mode */ - } /* end _PRT */ - } /* end PBR7 */ - - /* GPP */ - Device(PBR9) { - Name(_ADR, 0x00090000) - Name(_PRW, Package() {0x18, 4}) - Method(_PRT,0) { - If(PMOD){ Return(APS9) } /* APIC mode */ - Return (PS9) /* PIC Mode */ - } /* end _PRT */ - } /* end PBR9 */ - - Device(PBRa) { - Name(_ADR, 0x000A0000) - Name(_PRW, Package() {0x18, 4}) - Method(_PRT,0) { - If(PMOD){ Return(APSa) } /* APIC mode */ - Return (PSa) /* PIC Mode */ - } /* end _PRT */ - } /* end PBRa */ - - - /* PCI slot 1, 2, 3 */ - Device(PIBR) { - Name(_ADR, 0x00140004) - Name(_PRW, Package() {0x18, 4}) - - Method(_PRT, 0) { - Return (PCIB) - } - } - - /* Describe the Southbridge devices */ - Device(STCR) { - Name(_ADR, 0x00110000) - #include "acpi/sata.asl" - } /* end STCR */ - - Device(UOH1) { - Name(_ADR, 0x00130000) - Name(_PRW, Package() {0x0B, 3}) - } /* end UOH1 */ - - Device(UOH2) { - Name(_ADR, 0x00130001) - Name(_PRW, Package() {0x0B, 3}) - } /* end UOH2 */ - - Device(UOH3) { - Name(_ADR, 0x00130002) - Name(_PRW, Package() {0x0B, 3}) - } /* end UOH3 */ - - Device(UOH4) { - Name(_ADR, 0x00130003) - Name(_PRW, Package() {0x0B, 3}) - } /* end UOH4 */ - - Device(UOH5) { - Name(_ADR, 0x00130004) - Name(_PRW, Package() {0x0B, 3}) - } /* end UOH5 */ - - Device(UEH1) { - Name(_ADR, 0x00130005) - Name(_PRW, Package() {0x0B, 3}) - } /* end UEH1 */ - - Device(SBUS) { - Name(_ADR, 0x00140000) - } /* end SBUS */ - - /* Primary (and only) IDE channel */ - Device(IDEC) { - Name(_ADR, 0x00140001) - #include "acpi/ide.asl" - } /* end IDEC */ - - Device(AZHD) { - Name(_ADR, 0x00140002) - OperationRegion(AZPD, PCI_Config, 0x00, 0x100) - Field(AZPD, AnyAcc, NoLock, Preserve) { - offset (0x42), - NSDI, 1, - NSDO, 1, - NSEN, 1, - offset (0x44), - IPCR, 4, - offset (0x54), - PWST, 2, - , 6, - PMEB, 1, - , 6, - PMST, 1, - offset (0x62), - MMCR, 1, - offset (0x64), - MMLA, 32, - offset (0x68), - MMHA, 32, - offset (0x6C), - MMDT, 16, - } - - Method(_INI) { - If(LEqual(OSVR,3)){ /* If we are running Linux */ - Store(zero, NSEN) - Store(one, NSDO) - Store(one, NSDI) - } - } - } /* end AZHD */ - - Device(LIBR) { - Name(_ADR, 0x00140003) - /* Method(_INI) { - * DBGO("\\_SB\\PCI0\\LpcIsaBr\\_INI\n") - } */ /* End Method(_SB.SBRDG._INI) */ - - /* Real Time Clock Device */ - Device(RTC0) { - Name(_HID, EISAID("PNP0B00")) /* AT Real Time Clock (not PIIX4 compatible) */ - Name(_CRS, ResourceTemplate() { - IRQNoFlags(){8} - IO(Decode16,0x0070, 0x0070, 0, 2) - /* IO(Decode16,0x0070, 0x0070, 0, 4) */ - }) - } /* End Device(_SB.PCI0.LpcIsaBr.RTC0) */ - - Device(TMR) { /* Timer */ - Name(_HID,EISAID("PNP0100")) /* System Timer */ - Name(_CRS, ResourceTemplate() { - IRQNoFlags(){0} - IO(Decode16, 0x0040, 0x0040, 0, 4) - /* IO(Decode16, 0x0048, 0x0048, 0, 4) */ - }) - } /* End Device(_SB.PCI0.LpcIsaBr.TMR) */ - - Device(SPKR) { /* Speaker */ - Name(_HID,EISAID("PNP0800")) /* AT style speaker */ - Name(_CRS, ResourceTemplate() { - IO(Decode16, 0x0061, 0x0061, 0, 1) - }) - } /* End Device(_SB.PCI0.LpcIsaBr.SPKR) */ - - Device(PIC) { - Name(_HID,EISAID("PNP0000")) /* AT Interrupt Controller */ - Name(_CRS, ResourceTemplate() { - IRQNoFlags(){2} - IO(Decode16,0x0020, 0x0020, 0, 2) - IO(Decode16,0x00A0, 0x00A0, 0, 2) - /* IO(Decode16, 0x00D0, 0x00D0, 0x10, 0x02) */ - /* IO(Decode16, 0x04D0, 0x04D0, 0x10, 0x02) */ - }) - } /* End Device(_SB.PCI0.LpcIsaBr.PIC) */ - - Device(MAD) { /* 8257 DMA */ - Name(_HID,EISAID("PNP0200")) /* Hardware Device ID */ - Name(_CRS, ResourceTemplate() { - DMA(Compatibility,BusMaster,Transfer8){4} - IO(Decode16, 0x0000, 0x0000, 0x10, 0x10) - IO(Decode16, 0x0081, 0x0081, 0x01, 0x03) - IO(Decode16, 0x0087, 0x0087, 0x01, 0x01) - IO(Decode16, 0x0089, 0x0089, 0x01, 0x03) - IO(Decode16, 0x008F, 0x008F, 0x01, 0x01) - IO(Decode16, 0x00C0, 0x00C0, 0x10, 0x20) - }) /* End Name(_SB.PCI0.LpcIsaBr.MAD._CRS) */ - } /* End Device(_SB.PCI0.LpcIsaBr.MAD) */ - - Device(COPR) { - Name(_HID,EISAID("PNP0C04")) /* Math Coprocessor */ - Name(_CRS, ResourceTemplate() { - IO(Decode16, 0x00F0, 0x00F0, 0, 0x10) - IRQNoFlags(){13} - }) - } /* End Device(_SB.PCI0.LpcIsaBr.COPR) */ - - Device(HPTM) { - Name(_HID,EISAID("PNP0103")) - Name(CRS,ResourceTemplate() { - Memory32Fixed(ReadOnly,0xFED00000, 0x00000400, HPT) /* 1kb reserved space */ - }) - Method(_STA, 0) { - Return(0x0F) /* sata is visible */ - } - Method(_CRS, 0) { - CreateDwordField(CRS, ^HPT._BAS, HPBX) - Store(HPBA, HPBX) - Return(CRS) - } - } /* End Device(_SB.PCI0.LpcIsaBr.COPR) */ - } /* end LIBR */ - - Device(HPBR) { - Name(_ADR, 0x00140004) - } /* end HostPciBr */ - - Device(ACAD) { - Name(_ADR, 0x00140005) - } /* end Ac97audio */ - - Device(ACMD) { - Name(_ADR, 0x00140006) - } /* end Ac97modem */ - - /* ITE8718 Support */ - OperationRegion (IOID, SystemIO, 0x2E, 0x02) /* sometimes it is 0x4E */ - Field (IOID, ByteAcc, NoLock, Preserve) - { - SIOI, 8, SIOD, 8 /* 0x2E and 0x2F */ - } - - IndexField (SIOI, SIOD, ByteAcc, NoLock, Preserve) - { - Offset (0x07), - LDN, 8, /* Logical Device Number */ - Offset (0x20), - CID1, 8, /* Chip ID Byte 1, 0x87 */ - CID2, 8, /* Chip ID Byte 2, 0x12 */ - Offset (0x30), - ACTR, 8, /* Function activate */ - Offset (0xF0), - APC0, 8, /* APC/PME Event Enable Register */ - APC1, 8, /* APC/PME Status Register */ - APC2, 8, /* APC/PME Control Register 1 */ - APC3, 8, /* Environment Controller Special Configuration Register */ - APC4, 8 /* APC/PME Control Register 2 */ - } - - /* Enter the 8718 MB PnP Mode */ - Method (EPNP) - { - Store(0x87, SIOI) - Store(0x01, SIOI) - Store(0x55, SIOI) - Store(0x55, SIOI) /* 8718 magic number */ - } - /* Exit the 8718 MB PnP Mode */ - Method (XPNP) - { - Store (0x02, SIOI) - Store (0x02, SIOD) - } - /* - * Keyboard PME is routed to SB700 Gevent3. We can wake - * up the system by pressing the key. - */ - Method (SIOS, 1) - { - /* We only enable KBD PME for S5. */ - If (LLess (Arg0, 0x05)) - { - EPNP() - /* DBGO("8718F\n") */ - - Store (0x4, LDN) - Store (One, ACTR) /* Enable EC */ - /* - Store (0x4, LDN) - Store (0x04, APC4) - */ /* falling edge. which mode? Not sure. */ - - Store (0x4, LDN) - Store (0x08, APC1) /* clear PME status, Use 0x18 for mouse & KBD */ - Store (0x4, LDN) - Store (0x08, APC0) /* enable PME, Use 0x18 for mouse & KBD */ - - XPNP() - } - } - Method (SIOW, 0) - { - EPNP() - Store (0x4, LDN) - Store (Zero, APC0) /* disable keyboard PME */ - Store (0x4, LDN) - Store (0xFF, APC1) /* clear keyboard PME status */ - XPNP() - } - - Name(CRES, ResourceTemplate() { - IO(Decode16, 0x0CF8, 0x0CF8, 1, 8) - - WORDIO(ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, - 0x0000, /* address granularity */ - 0x0000, /* range minimum */ - 0x0CF7, /* range maximum */ - 0x0000, /* translation */ - 0x0CF8 /* length */ - ) - - WORDIO(ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, - 0x0000, /* address granularity */ - 0x0D00, /* range minimum */ - 0xFFFF, /* range maximum */ - 0x0000, /* translation */ - 0xF300 /* length */ - ) - - Memory32Fixed(READWRITE, 0, 0xA0000, BSMM) - Memory32Fixed(READONLY, 0x000A0000, 0x00020000, VGAM) /* VGA memory space */ - Memory32Fixed(READONLY, 0x000C0000, 0x00020000, EMM1) /* Assume C0000-E0000 empty */ - Memory32Fixed(READONLY, 0x000E0000, 0x00020000, RDBS) /* BIOS ROM area */ - - /* DRAM Memory from 1MB to TopMem */ - Memory32Fixed(READWRITE, 0x00100000, 0, DMLO) /* 1MB to TopMem */ - - /* BIOS space just below 4GB */ - DWORDMemory( - ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite, - 0x00, /* Granularity */ - 0x00000000, /* Min */ - 0x00000000, /* Max */ - 0x00000000, /* Translation */ - 0x00000001, /* Max-Min, RLEN */ - ,, - PCBM - ) - - /* DRAM memory from 4GB to TopMem2 */ - QWORDMemory(ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite, - 0x00000000, /* Granularity */ - 0x00000000, /* Min */ - 0x00000000, /* Max */ - 0x00000000, /* Translation */ - 0x00000001, /* Max-Min, RLEN */ - ,, - DMHI - ) - - /* BIOS space just below 16EB */ - QWORDMemory(ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite, - 0x00000000, /* Granularity */ - 0x00000000, /* Min */ - 0x00000000, /* Max */ - 0x00000000, /* Translation */ - 0x00000001, /* Max-Min, RLEN */ - ,, - PEBM - ) - - }) /* End Name(_SB.PCI0.CRES) */ - - Method(_CRS, 0) { - /* DBGO("\\_SB\\PCI0\\_CRS\n") */ - - CreateDWordField(CRES, ^EMM1._BAS, EM1B) - CreateDWordField(CRES, ^EMM1._LEN, EM1L) - CreateDWordField(CRES, ^DMLO._BAS, DMLB) - CreateDWordField(CRES, ^DMLO._LEN, DMLL) - CreateDWordField(CRES, ^PCBM._MIN, PBMB) - CreateDWordField(CRES, ^PCBM._LEN, PBML) - - CreateQWordField(CRES, ^DMHI._MIN, DMHB) - CreateQWordField(CRES, ^DMHI._LEN, DMHL) - CreateQWordField(CRES, ^PEBM._MIN, EBMB) - CreateQWordField(CRES, ^PEBM._LEN, EBML) - - If(LGreater(LOMH, 0xC0000)){ - Store(0xC0000, EM1B) /* Hole above C0000 and below E0000 */ - Subtract(LOMH, 0xC0000, EM1L) /* subtract start, assumes allocation from C0000 going up */ - } - - /* Set size of memory from 1MB to TopMem */ - Subtract(TOM1, 0x100000, DMLL) - - /* - * If(LNotEqual(TOM2, 0x00000000)){ - * Store(0x100000000,DMHB) DRAM from 4GB to TopMem2 - * ShiftLeft(TOM2, 20, Local0) - * Subtract(Local0, 0x100000000, DMHL) - * } - */ - - /* If there is no memory above 4GB, put the BIOS just below 4GB */ - If(LEqual(TOM2, 0x00000000)){ - Store(PBAD,PBMB) /* Reserve the "BIOS" space */ - Store(PBLN,PBML) - } - Else { /* Otherwise, put the BIOS just below 16EB */ - ShiftLeft(PBAD,16,EBMB) /* Reserve the "BIOS" space */ - Store(PBLN,EBML) - } - - Return(CRES) /* note to change the Name buffer */ - } /* end of Method(_SB.PCI0._CRS) */ - - /* - * - * FIRST METHOD CALLED UPON BOOT - * - * 1. If debugging, print current OS and ACPI interpreter. - * 2. Get PCI Interrupt routing from ACPI VSM, this - * value is based on user choice in BIOS setup. - */ - Method(_INI, 0) { - /* DBGO("\\_SB\\_INI\n") */ - /* DBGO(" DSDT.ASL code from ") */ - /* DBGO(__DATE__) */ - /* DBGO(" ") */ - /* DBGO(__TIME__) */ - /* DBGO("\n Sleep states supported: ") */ - /* DBGO("\n") */ - /* DBGO(" \\_OS=") */ - /* DBGO(\_OS) */ - /* DBGO("\n \\_REV=") */ - /* DBGO(\_REV) */ - /* DBGO("\n") */ - - /* Determine the OS we're running on */ - OSFL() - - /* On older chips, clear PciExpWakeDisEn */ - /*if (LLessEqual(\SBRI, 0x13)) { - * Store(0,\PWDE) - * } - */ - } /* End Method(_SB._INI) */ - } /* End Device(PCI0) */ - - Device(PWRB) { /* Start Power button device */ - Name(_HID, EISAID("PNP0C0C")) - Name(_UID, 0xAA) - Name(_PRW, Package () {3, 0x04}) /* wake from S1-S4 */ - Name(_STA, 0x0B) /* sata is invisible */ - } - } /* End \_SB scope */ - - Scope(\_SI) { - Method(_SST, 1) { - /* DBGO("\\_SI\\_SST\n") */ - /* DBGO(" New Indicator state: ") */ - /* DBGO(Arg0) */ - /* DBGO("\n") */ - } - } /* End Scope SI */ - - #include - - /* THERMAL */ - Scope(\_TZ) { - Name (KELV, 2732) - Name (THOT, 800) - Name (TCRT, 850) - - ThermalZone(TZ00) { - Method(_AC0,0) { /* Active Cooling 0 (0=highest fan speed) */ - /* DBGO("\\_TZ\\TZ00\\_AC0\n") */ - Return(Add(0, 2730)) - } - Method(_AL0,0) { /* Returns package of cooling device to turn on */ - /* DBGO("\\_TZ\\TZ00\\_AL0\n") */ - Return(Package() {\_TZ.TZ00.FAN0}) - } - Device (FAN0) { - Name(_HID, EISAID("PNP0C0B")) - Name(_PR0, Package() {PFN0}) - } - - PowerResource(PFN0,0,0) { - Method(_STA) { - Store(0xF,Local0) - Return(Local0) - } - Method(_ON) { - /* DBGO("\\_TZ\\TZ00\\FAN0 _ON\n") */ - } - Method(_OFF) { - /* DBGO("\\_TZ\\TZ00\\FAN0 _OFF\n") */ - } - } - - Method(_HOT,0) { /* return hot temp in tenths degree Kelvin */ - /* DBGO("\\_TZ\\TZ00\\_HOT\n") */ - Return (Add (THOT, KELV)) - } - Method(_CRT,0) { /* return critical temp in tenths degree Kelvin */ - /* DBGO("\\_TZ\\TZ00\\_CRT\n") */ - Return (Add (TCRT, KELV)) - } - Method(_TMP,0) { /* return current temp of this zone */ - Store (SMBR (0x07, 0x4C,, 0x00), Local0) - If (LGreater (Local0, 0x10)) { - Store (Local0, Local1) - } - Else { - Add (Local0, THOT, Local0) - Return (Add (400, KELV)) - } - - Store (SMBR (0x07, 0x4C, 0x01), Local0) - /* only the two MSBs in the external temperature low byte are used, resolution 0.25. We ignore it */ - /* Store (SMBR (0x07, 0x4C, 0x10), Local2) */ - If (LGreater (Local0, 0x10)) { - If (LGreater (Local0, Local1)) { - Store (Local0, Local1) - } - - Multiply (Local1, 10, Local1) - Return (Add (Local1, KELV)) - } - Else { - Add (Local0, THOT, Local0) - Return (Add (400 , KELV)) - } - } /* end of _TMP */ - } /* end of TZ00 */ - } -} -/* End of ASL file */ diff --git a/src/mainboard/asus/m4a785-m/get_bus_conf.c b/src/mainboard/asus/m4a785-m/get_bus_conf.c deleted file mode 100644 index ee2a6caeb9..0000000000 --- a/src/mainboard/asus/m4a785-m/get_bus_conf.c +++ /dev/null @@ -1,44 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2010 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include -#include - -#include - -/* Global variables for MB layouts and these will be shared by irqtable mptable -* and acpi_tables busnum is default. -*/ -u32 apicid_sb700; - -void get_bus_conf(void) -{ - u32 apicid_base; - - get_default_pci1234(1); - - sysconf.sbdn = (sysconf.hcdn[0] & 0xff); - - pirq_router_bus = (sysconf.pci1234[0] >> 16) & 0xff; - - /* I/O APICs: APIC ID Version State Address */ - if (CONFIG(LOGICAL_CPUS)) - apicid_base = get_apicid_base(1); - else - apicid_base = CONFIG_MAX_PHYSICAL_CPUS; - apicid_sb700 = apicid_base + 0; -} diff --git a/src/mainboard/asus/m4a785-m/irq_tables.c b/src/mainboard/asus/m4a785-m/irq_tables.c deleted file mode 100644 index 9e114a312b..0000000000 --- a/src/mainboard/asus/m4a785-m/irq_tables.c +++ /dev/null @@ -1,61 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2010 Juhana Helovuo - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include - -static const struct irq_routing_table intel_irq_routing_table = { - PIRQ_SIGNATURE, /* u32 signature */ - PIRQ_VERSION, /* u16 version */ - 32 + 16 * CONFIG_IRQ_SLOT_COUNT, /* Max. number of devices on the bus */ - 0x00, /* Interrupt router bus */ - (0x14 << 3) | 0x3, /* Interrupt router dev */ - 0, /* IRQs devoted exclusively to PCI usage */ - 0x1002, /* Vendor */ - 0x439d, /* Device */ - 0, /* Miniport */ - { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */ - 0x8, /* Checksum (has to be set to some value that - * would give 0 after the sum of all bytes - * for this structure (including checksum). - */ - { - /* bus, dev | fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */ - {0x01, (0x05 << 3) | 0x0, {{0x03, 0xdc90}, {0x04, 0xdc90}, {0x01, 0xdc90}, {0x02, 0xdc90}}, 0x0, 0x0}, - {0x00, (0x02 << 3) | 0x0, {{0x03, 0xdc90}, {0x04, 0xdc90}, {0x01, 0xdc90}, {0x02, 0xdc90}}, 0x0, 0x0}, - {0x00, (0x03 << 3) | 0x0, {{0x04, 0xdc90}, {0x01, 0xdc90}, {0x02, 0xdc90}, {0x03, 0xdc90}}, 0x0, 0x0}, - {0x00, (0x04 << 3) | 0x0, {{0x01, 0xdc90}, {0x02, 0xdc90}, {0x03, 0xdc90}, {0x04, 0xdc90}}, 0x0, 0x0}, - {0x00, (0x05 << 3) | 0x0, {{0x02, 0xdc90}, {0x03, 0xdc90}, {0x04, 0xdc90}, {0x01, 0xdc90}}, 0x0, 0x0}, - {0x00, (0x06 << 3) | 0x0, {{0x03, 0xdc90}, {0x04, 0xdc90}, {0x01, 0xdc90}, {0x02, 0xdc90}}, 0x0, 0x0}, - {0x00, (0x07 << 3) | 0x0, {{0x04, 0xdc90}, {0x01, 0xdc90}, {0x02, 0xdc90}, {0x03, 0xdc90}}, 0x0, 0x0}, - {0x00, (0x09 << 3) | 0x0, {{0x02, 0xdc90}, {0x03, 0xdc90}, {0x04, 0xdc90}, {0x01, 0xdc90}}, 0x0, 0x0}, - {0x00, (0x0a << 3) | 0x0, {{0x03, 0xdc90}, {0x04, 0xdc90}, {0x01, 0xdc90}, {0x02, 0xdc90}}, 0x0, 0x0}, - {0x02, (0x00 << 3) | 0x0, {{0x03, 0xdc90}, {0x04, 0xdc90}, {0x01, 0xdc90}, {0x02, 0xdc90}}, 0xa, 0x0}, - {0x00, (0x0b << 3) | 0x0, {{0x04, 0xdc90}, {0x01, 0xdc90}, {0x02, 0xdc90}, {0x03, 0xdc90}}, 0x0, 0x0}, - {0x00, (0x0c << 3) | 0x0, {{0x01, 0xdc90}, {0x02, 0xdc90}, {0x03, 0xdc90}, {0x04, 0xdc90}}, 0x0, 0x0}, - {0x00, (0x14 << 3) | 0x0, {{0x01, 0xdc90}, {0x02, 0xdc90}, {0x03, 0xdc90}, {0x04, 0xdc90}}, 0x0, 0x0}, - {0x00, (0x12 << 3) | 0x0, {{0x01, 0xdc90}, {0x02, 0xdc90}, {0x03, 0xdc90}, {0x04, 0xdc90}}, 0x0, 0x0}, - {0x00, (0x13 << 3) | 0x0, {{0x03, 0xdc90}, {0x04, 0xdc90}, {0x01, 0xdc90}, {0x02, 0xdc90}}, 0x0, 0x0}, - {0x00, (0x11 << 3) | 0x0, {{0x0c, 0xdc90}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x0000}}, 0x0, 0x0}, - {0x0a, (0x00 << 3) | 0x0, {{0x03, 0xdc90}, {0x04, 0xdc90}, {0x01, 0xdc90}, {0x02, 0xdc90}}, 0x0, 0x0}, - {0x03, (0x05 << 3) | 0x0, {{0x0a, 0xdc90}, {0x0b, 0xdc90}, {0x0c, 0xdc90}, {0x0d, 0xdc90}}, 0xc, 0x0}, - {0x03, (0x06 << 3) | 0x0, {{0x0b, 0xdc90}, {0x0c, 0xdc90}, {0x0d, 0xdc90}, {0x0a, 0xdc90}}, 0xd, 0x0}, - } -}; - -unsigned long write_pirq_routing_table(unsigned long addr) -{ - return copy_pirq_routing_table(addr, &intel_irq_routing_table); -} diff --git a/src/mainboard/asus/m4a785-m/mainboard.c b/src/mainboard/asus/m4a785-m/mainboard.c deleted file mode 100644 index aa6b920db2..0000000000 --- a/src/mainboard/asus/m4a785-m/mainboard.c +++ /dev/null @@ -1,189 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2010 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include -#include -#include -#include -#include -#include - -#define ADT7461_ADDRESS 0x4C -#define ARA_ADDRESS 0x0C /* Alert Response Address */ - -#define ADT7461_read_byte(address) \ - do_smbus_read_byte(SMBUS_IO_BASE, ADT7461_ADDRESS, address) -#define ARA_read_byte(address) \ - do_smbus_read_byte(SMBUS_IO_BASE, ARA_ADDRESS, address) -#define ADT7461_write_byte(address, val) \ - do_smbus_write_byte(SMBUS_IO_BASE, ADT7461_ADDRESS, address, val) - -void set_pcie_dereset(void) -{ - u8 byte; - u16 word; - struct device *sm_dev; - /* set 0 to bit1 :disable GPM9 as SLP_S2 output */ - /* set 0 to bit2 :disable GPM8 as AZ_RST output */ - byte = pm_ioread(0x8d); - byte &= ~((1 << 1) | (1 << 2)); - pm_iowrite(0x8d, byte); - - /* set the GPM8 and GPM9 output enable and the value to 1 */ - byte = pm_ioread(0x94); - byte &= ~((1 << 2) | (1 << 3)); - byte |= ((1 << 0) | (1 << 1)); - pm_iowrite(0x94, byte); - - /* set the GPIO65 output enable and the value is 1 */ - sm_dev = pcidev_on_root(0x14, 0); - word = pci_read_config16(sm_dev, 0x7e); - word |= (1 << 0); - word &= ~(1 << 4); - pci_write_config16(sm_dev, 0x7e, word); -} - -void set_pcie_reset(void) -{ - u8 byte; - u16 word; - struct device *sm_dev; - - /* set 0 to bit1 :disable GPM9 as SLP_S2 output */ - /* set 0 to bit2 :disable GPM8 as AZ_RST output */ - byte = pm_ioread(0x8d); - byte &= ~((1 << 1) | (1 << 2)); - pm_iowrite(0x8d, byte); - - /* set the GPM8 and GPM9 output enable and the value to 0 */ - byte = pm_ioread(0x94); - byte &= ~((1 << 2) | (1 << 3)); - byte &= ~((1 << 0) | (1 << 1)); - pm_iowrite(0x94, byte); - - /* set the GPIO65 output enable and the value is 0 */ - sm_dev = pcidev_on_root(0x14, 0); - word = pci_read_config16(sm_dev, 0x7e); - word &= ~(1 << 0); - word &= ~(1 << 4); - pci_write_config16(sm_dev, 0x7e, word); -} - -/* - * justify the dev3 is exist or not - * NOTE: This just copied from AMD Tilapia code. - * It is completely unknown it it will work at all for ASUS M4A785-M. - */ -int is_dev3_present(void) -{ - u16 word; - struct device *sm_dev; - - /* access the smbus extended register */ - sm_dev = pcidev_on_root(0x14, 0); - - /* put the GPIO68 output to tristate */ - word = pci_read_config16(sm_dev, 0x7e); - word |= 1 << 6; - pci_write_config16(sm_dev, 0x7e,word); - - /* read the GPIO68 input status */ - word = pci_read_config16(sm_dev, 0x7e); - - return !(word & (1 << 10)); -} - -/* - * set thermal config - */ -static void set_thermal_config(void) -{ - u8 byte; - u16 word; - struct device *sm_dev; - - /* set ADT 7461 */ - ADT7461_write_byte(0x0B, 0x50); /* Local Temperature Hight limit */ - ADT7461_write_byte(0x0C, 0x00); /* Local Temperature Low limit */ - ADT7461_write_byte(0x0D, 0x50); /* External Temperature Hight limit High Byte */ - ADT7461_write_byte(0x0E, 0x00); /* External Temperature Low limit High Byte */ - - ADT7461_write_byte(0x19, 0x55); /* External THERM limit */ - ADT7461_write_byte(0x20, 0x55); /* Local THERM limit */ - - byte = ADT7461_read_byte(0x02); /* read status register to clear it */ - ARA_read_byte(0x05); /* A hardware alert can only be cleared by the master sending an ARA as a read command */ - printk(BIOS_INFO, "Init adt7461 end, status 0x02 %02x\n", byte); - - /* sb700 settings for thermal config */ - /* set SB700 GPIO 64 to GPIO with pull-up */ - byte = pm2_ioread(0x42); - byte &= 0x3f; - pm2_iowrite(0x42, byte); - - /* set GPIO 64 to input */ - sm_dev = pcidev_on_root(0x14, 0); - word = pci_read_config16(sm_dev, 0x56); - word |= 1 << 7; - pci_write_config16(sm_dev, 0x56, word); - - /* set GPIO 64 internal pull-up */ - byte = pm2_ioread(0xf0); - byte &= 0xee; - pm2_iowrite(0xf0, byte); - - /* set Talert to be active low */ - byte = pm_ioread(0x67); - byte &= ~(1 << 5); - pm_iowrite(0x67, byte); - - /* set Talert to generate ACPI event */ - byte = pm_ioread(0x3c); - byte &= 0xf3; - pm_iowrite(0x3c, byte); - - /* THERMTRIP pin */ - /* byte = pm_ioread(0x68); - * byte |= 1 << 3; - * pm_iowrite(0x68, byte); - * - * byte = pm_ioread(0x55); - * byte |= 1 << 0; - * pm_iowrite(0x55, byte); - * - * byte = pm_ioread(0x67); - * byte &= ~(1 << 6); - * pm_iowrite(0x67, byte); - */ -} - -/************************************************* -* enable the dedicated function in this board. -* This function called early than rs780_enable. -*************************************************/ -static void mainboard_enable(struct device *dev) -{ - printk(BIOS_INFO, "Mainboard enable. dev=0x%p\n", dev); - - set_pcie_dereset(); - /* get_ide_dma66(); */ - set_thermal_config(); -} - -struct chip_operations mainboard_ops = { - .enable_dev = mainboard_enable, -}; diff --git a/src/mainboard/asus/m4a785-m/mptable.c b/src/mainboard/asus/m4a785-m/mptable.c deleted file mode 100644 index b04a315bb1..0000000000 --- a/src/mainboard/asus/m4a785-m/mptable.c +++ /dev/null @@ -1,101 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2010 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include -#include -#include - -extern u32 apicid_sb700; - -static void *smp_write_config_table(void *v) -{ - struct mp_config_table *mc; - int bus_isa; - - mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); - - mptable_init(mc, LOCAL_APIC_ADDR); - - smp_write_processors(mc); - - mptable_write_buses(mc, NULL, &bus_isa); - - /* I/O APICs: APIC ID Version State Address */ - { - struct device *dev; - u32 dword; - u8 byte; - - dev = - dev_find_slot(pirq_router_bus, - PCI_DEVFN(0x14, 0)); - if (dev) { - dword = pci_read_config32(dev, 0x74) & 0xfffffff0; - smp_write_ioapic(mc, apicid_sb700, - 0x11,(void *) dword); - - /* Initialize interrupt mapping */ - /* aza */ - byte = pci_read_config8(dev, 0x63); - byte &= 0xf8; - byte |= 0; /* 0: INTA, ...., 7: INTH */ - pci_write_config8(dev, 0x63, byte); - - /* SATA */ - dword = pci_read_config32(dev, 0xac); - dword &= ~(7 << 26); - dword |= 6 << 26; /* 0: INTA, ...., 7: INTH */ - /* dword |= 1 << 22; PIC and APIC co exists */ - pci_write_config32(dev, 0xac, dword); - - /* - * 00:12.0: PROG SATA : INT F - * 00:13.0: INTA USB_0 - * 00:13.1: INTB USB_1 - * 00:13.2: INTC USB_2 - * 00:13.3: INTD USB_3 - * 00:13.4: INTC USB_4 - * 00:13.5: INTD USB2 - * 00:14.1: INTA IDE - * 00:14.2: Prog HDA : INT E - * 00:14.5: INTB ACI - * 00:14.6: INTB MCI - */ - } - } - - /* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ -#define IO_LOCAL_INT(type, intr, apicid, pin) \ - smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin)); - - mptable_add_isa_interrupts(mc, bus_isa, apicid_sb700, 0); - - /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ - IO_LOCAL_INT(mp_ExtINT, 0x0, MP_APIC_ALL, 0x0); - IO_LOCAL_INT(mp_NMI, 0x0, MP_APIC_ALL, 0x1); - /* There is no extension information... */ - - /* Compute the checksums */ - return mptable_finalize(mc); -} - -unsigned long write_smp_table(unsigned long addr) -{ - void *v; - v = smp_write_floating_table(addr, 0); - return (unsigned long)smp_write_config_table(v); -} diff --git a/src/mainboard/asus/m4a785-m/resourcemap.c b/src/mainboard/asus/m4a785-m/resourcemap.c deleted file mode 100644 index 80d2d9d05c..0000000000 --- a/src/mainboard/asus/m4a785-m/resourcemap.c +++ /dev/null @@ -1,279 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2010 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - - - -#include -#include - -void setup_mb_resource_map(void) -{ - static const unsigned int register_values[] = { - /* Careful set limit registers before base registers which contain the enables */ - /* DRAM Limit i Registers - * F1:0x44 i = 0 - * F1:0x4C i = 1 - * F1:0x54 i = 2 - * F1:0x5C i = 3 - * F1:0x64 i = 4 - * F1:0x6C i = 5 - * F1:0x74 i = 6 - * F1:0x7C i = 7 - * [ 2: 0] Destination Node ID - * 000 = Node 0 - * 001 = Node 1 - * 010 = Node 2 - * 011 = Node 3 - * 100 = Node 4 - * 101 = Node 5 - * 110 = Node 6 - * 111 = Node 7 - * [ 7: 3] Reserved - * [10: 8] Interleave select - * specifies the values of A[14:12] to use with interleave enable. - * [15:11] Reserved - * [31:16] DRAM Limit Address i Bits 39-24 - * This field defines the upper address bits of a 40 bit address - * that define the end of the DRAM region. - */ -// ADDRMAP_REG(0x44), 0x0000f8f8, 0x00000000, // Don't touch it, we need it for CONFIG_CAR_FAM10 - ADDRMAP_REG(0x4C), 0x0000f8f8, 0x00000001, - ADDRMAP_REG(0x54), 0x0000f8f8, 0x00000002, - ADDRMAP_REG(0x5C), 0x0000f8f8, 0x00000003, - ADDRMAP_REG(0x64), 0x0000f8f8, 0x00000004, - ADDRMAP_REG(0x6C), 0x0000f8f8, 0x00000005, - ADDRMAP_REG(0x74), 0x0000f8f8, 0x00000006, - ADDRMAP_REG(0x7C), 0x0000f8f8, 0x00000007, - /* DRAM Base i Registers - * F1:0x40 i = 0 - * F1:0x48 i = 1 - * F1:0x50 i = 2 - * F1:0x58 i = 3 - * F1:0x60 i = 4 - * F1:0x68 i = 5 - * F1:0x70 i = 6 - * F1:0x78 i = 7 - * [ 0: 0] Read Enable - * 0 = Reads Disabled - * 1 = Reads Enabled - * [ 1: 1] Write Enable - * 0 = Writes Disabled - * 1 = Writes Enabled - * [ 7: 2] Reserved - * [10: 8] Interleave Enable - * 000 = No interleave - * 001 = Interleave on A[12] (2 nodes) - * 010 = reserved - * 011 = Interleave on A[12] and A[14] (4 nodes) - * 100 = reserved - * 101 = reserved - * 110 = reserved - * 111 = Interleve on A[12] and A[13] and A[14] (8 nodes) - * [15:11] Reserved - * [13:16] DRAM Base Address i Bits 39-24 - * This field defines the upper address bits of a 40-bit address - * that define the start of the DRAM region. - */ -// ADDRMAP_REG(0x40), 0x0000f8fc, 0x00000000,// don't touch it, we need it for CONFIG_CAR_FAM10 - ADDRMAP_REG(0x48), 0x0000f8fc, 0x00000000, - ADDRMAP_REG(0x50), 0x0000f8fc, 0x00000000, - ADDRMAP_REG(0x58), 0x0000f8fc, 0x00000000, - ADDRMAP_REG(0x60), 0x0000f8fc, 0x00000000, - ADDRMAP_REG(0x68), 0x0000f8fc, 0x00000000, - ADDRMAP_REG(0x70), 0x0000f8fc, 0x00000000, - ADDRMAP_REG(0x78), 0x0000f8fc, 0x00000000, - - /* Memory-Mapped I/O Limit i Registers - * F1:0x84 i = 0 - * F1:0x8C i = 1 - * F1:0x94 i = 2 - * F1:0x9C i = 3 - * F1:0xA4 i = 4 - * F1:0xAC i = 5 - * F1:0xB4 i = 6 - * F1:0xBC i = 7 - * [ 2: 0] Destination Node ID - * 000 = Node 0 - * 001 = Node 1 - * 010 = Node 2 - * 011 = Node 3 - * 100 = Node 4 - * 101 = Node 5 - * 110 = Node 6 - * 111 = Node 7 - * [ 3: 3] Reserved - * [ 5: 4] Destination Link ID - * 00 = Link 0 - * 01 = Link 1 - * 10 = Link 2 - * 11 = Reserved - * [ 6: 6] Reserved - * [ 7: 7] Non-Posted - * 0 = CPU writes may be posted - * 1 = CPU writes must be non-posted - * [31: 8] Memory-Mapped I/O Limit Address i (39-16) - * This field defines the upp address bits of a 40-bit address that - * defines the end of a memory-mapped I/O region n - */ - ADDRMAP_REG(0x84), 0x00000048, 0x00000000, - ADDRMAP_REG(0x8C), 0x00000048, 0x00000000, - ADDRMAP_REG(0x94), 0x00000048, 0x00000000, - ADDRMAP_REG(0x9C), 0x00000048, 0x00000000, - ADDRMAP_REG(0xA4), 0x00000048, 0x00000000, - ADDRMAP_REG(0xAC), 0x00000048, 0x00000000, - ADDRMAP_REG(0xB4), 0x00000048, 0x00000000, -// ADDRMAP_REG(0xBC), 0x00000048, 0x00ffff00, - - /* Memory-Mapped I/O Base i Registers - * F1:0x80 i = 0 - * F1:0x88 i = 1 - * F1:0x90 i = 2 - * F1:0x98 i = 3 - * F1:0xA0 i = 4 - * F1:0xA8 i = 5 - * F1:0xB0 i = 6 - * F1:0xB8 i = 7 - * [ 0: 0] Read Enable - * 0 = Reads disabled - * 1 = Reads Enabled - * [ 1: 1] Write Enable - * 0 = Writes disabled - * 1 = Writes Enabled - * [ 2: 2] Cpu Disable - * 0 = Cpu can use this I/O range - * 1 = Cpu requests do not use this I/O range - * [ 3: 3] Lock - * 0 = base/limit registers i are read/write - * 1 = base/limit registers i are read-only - * [ 7: 4] Reserved - * [31: 8] Memory-Mapped I/O Base Address i (39-16) - * This field defines the upper address bits of a 40bit address - * that defines the start of memory-mapped I/O region i - */ - ADDRMAP_REG(0x80), 0x000000f0, 0x00000000, - ADDRMAP_REG(0x88), 0x000000f0, 0x00000000, - ADDRMAP_REG(0x90), 0x000000f0, 0x00000000, - ADDRMAP_REG(0x98), 0x000000f0, 0x00000000, - ADDRMAP_REG(0xA0), 0x000000f0, 0x00000000, - ADDRMAP_REG(0xA8), 0x000000f0, 0x00000000, - ADDRMAP_REG(0xB0), 0x000000f0, 0x00000000, -// ADDRMAP_REG(0xB8), 0x000000f0, 0x00fc0003, - - /* PCI I/O Limit i Registers - * F1:0xC4 i = 0 - * F1:0xCC i = 1 - * F1:0xD4 i = 2 - * F1:0xDC i = 3 - * [ 2: 0] Destination Node ID - * 000 = Node 0 - * 001 = Node 1 - * 010 = Node 2 - * 011 = Node 3 - * 100 = Node 4 - * 101 = Node 5 - * 110 = Node 6 - * 111 = Node 7 - * [ 3: 3] Reserved - * [ 5: 4] Destination Link ID - * 00 = Link 0 - * 01 = Link 1 - * 10 = Link 2 - * 11 = reserved - * [11: 6] Reserved - * [24:12] PCI I/O Limit Address i - * This field defines the end of PCI I/O region n - * [31:25] Reserved - */ -// ADDRMAP_REG(0xC4), 0xFE000FC8, 0x01fff000, - ADDRMAP_REG(0xCC), 0xFE000FC8, 0x00000000, - ADDRMAP_REG(0xD4), 0xFE000FC8, 0x00000000, - ADDRMAP_REG(0xDC), 0xFE000FC8, 0x00000000, - - /* PCI I/O Base i Registers - * F1:0xC0 i = 0 - * F1:0xC8 i = 1 - * F1:0xD0 i = 2 - * F1:0xD8 i = 3 - * [ 0: 0] Read Enable - * 0 = Reads Disabled - * 1 = Reads Enabled - * [ 1: 1] Write Enable - * 0 = Writes Disabled - * 1 = Writes Enabled - * [ 3: 2] Reserved - * [ 4: 4] VGA Enable - * 0 = VGA matches Disabled - * 1 = matches all address < 64K and where A[9:0] is in the - * range 3B0-3BB or 3C0-3DF independen of the base & limit registers - * [ 5: 5] ISA Enable - * 0 = ISA matches Disabled - * 1 = Blocks address < 64K and in the last 768 bytes of eack 1K block - * from matching agains this base/limit pair - * [11: 6] Reserved - * [24:12] PCI I/O Base i - * This field defines the start of PCI I/O region n - * [31:25] Reserved - */ -// ADDRMAP_REG(0xC0), 0xFE000FCC, 0x00000003, - ADDRMAP_REG(0xC8), 0xFE000FCC, 0x00000000, - ADDRMAP_REG(0xD0), 0xFE000FCC, 0x00000000, - ADDRMAP_REG(0xD8), 0xFE000FCC, 0x00000000, - - /* Config Base and Limit i Registers - * F1:0xE0 i = 0 - * F1:0xE4 i = 1 - * F1:0xE8 i = 2 - * F1:0xEC i = 3 - * [ 0: 0] Read Enable - * 0 = Reads Disabled - * 1 = Reads Enabled - * [ 1: 1] Write Enable - * 0 = Writes Disabled - * 1 = Writes Enabled - * [ 2: 2] Device Number Compare Enable - * 0 = The ranges are based on bus number - * 1 = The ranges are ranges of devices on bus 0 - * [ 3: 3] Reserved - * [ 6: 4] Destination Node - * 000 = Node 0 - * 001 = Node 1 - * 010 = Node 2 - * 011 = Node 3 - * 100 = Node 4 - * 101 = Node 5 - * 110 = Node 6 - * 111 = Node 7 - * [ 7: 7] Reserved - * [ 9: 8] Destination Link - * 00 = Link 0 - * 01 = Link 1 - * 10 = Link 2 - * 11 - Reserved - * [15:10] Reserved - * [23:16] Bus Number Base i - * This field defines the lowest bus number in configuration region i - * [31:24] Bus Number Limit i - * This field defines the highest bus number in configuration regin i - */ -// ADDRMAP_REG(0xE0), 0x0000FC88, 0x06000003, // AMD 8111 on link0 of CPU 0 - ADDRMAP_REG(0xE4), 0x0000FC88, 0x00000000, - ADDRMAP_REG(0xE8), 0x0000FC88, 0x00000000, - ADDRMAP_REG(0xEC), 0x0000FC88, 0x00000000, - }; - - int max; - max = ARRAY_SIZE(register_values); - setup_resource_map(register_values, max); -} diff --git a/src/mainboard/asus/m4a785-m/romstage.c b/src/mainboard/asus/m4a785-m/romstage.c deleted file mode 100644 index b7af9e2cf5..0000000000 --- a/src/mainboard/asus/m4a785-m/romstage.c +++ /dev/null @@ -1,236 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2010 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -//#define SYSTEM_TYPE 0 /* SERVER */ -#define SYSTEM_TYPE 1 /* DESKTOP */ -//#define SYSTEM_TYPE 2 /* MOBILE */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include "cpu/amd/quadcore/quadcore.c" - -#define SERIAL_DEV PNP_DEV(0x2e, IT8712F_SP1) -#define GPIO_DEV PNP_DEV(0x2e, IT8712F_GPIO) - -int spd_read_byte(unsigned int device, unsigned int address); - - -int spd_read_byte(u32 device, u32 address) -{ - return do_smbus_read_byte(SMBUS_IO_BASE, device, address); -} - -void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) -{ - struct sys_info *sysinfo = get_sysinfo(); - static const u8 spd_addr[] = {RC00, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, }; - u32 bsp_apicid = 0, val; - msr_t msr; - - timestamp_init(timestamp_get()); - timestamp_add_now(TS_START_ROMSTAGE); - - if (!cpu_init_detectedx && boot_cpu()) { - /* Nothing special needs to be done to find bus 0 */ - /* Allow the HT devices to be found */ - /* mov bsp to bus 0xff when > 8 nodes */ - set_bsp_node_CHtExtNodeCfgEn(); - enumerate_ht_chain(); - sb7xx_51xx_pci_port80(); - } - - post_code(0x30); - - if (bist == 0) { - bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo); /* mmconf is inited in init_cpus */ - /* All cores run this but the BSP(node0,core0) is the only core that returns. */ - } - - post_code(0x32); - - enable_rs780_dev8(); - sb7xx_51xx_lpc_init(); - - ite_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); - ite_kill_watchdog(GPIO_DEV); - - console_init(); - - /* Halt if there was a built in self test failure */ - report_bist_failure(bist); - - // Load MPB - val = cpuid_eax(1); - printk(BIOS_DEBUG, "BSP Family_Model: %08x\n", val); - printk(BIOS_DEBUG, "*sysinfo range: [%p,%p]\n",sysinfo,sysinfo+1); - printk(BIOS_DEBUG, "bsp_apicid = %02x\n", bsp_apicid); - printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx); - - /* Setup sysinfo defaults */ - set_sysinfo_in_ram(0); - - update_microcode(val); - - post_code(0x33); - - cpuSetAMDMSR(0); - post_code(0x34); - - amd_ht_init(sysinfo); - post_code(0x35); - - /* Setup nodes PCI space and start core 0 AP init. */ - finalize_node_setup(sysinfo); - - /* Setup any mainboard PCI settings etc. */ - setup_mb_resource_map(); - post_code(0x36); - - /* wait for all the APs core0 started by finalize_node_setup. */ - /* FIXME: A bunch of cores are going to start output to serial at once. - It would be nice to fixup prink spinlocks for ROM XIP mode. - I think it could be done by putting the spinlock flag in the cache - of the BSP located right after sysinfo. - */ - wait_all_core0_started(); - - #if CONFIG(LOGICAL_CPUS) - /* Core0 on each node is configured. Now setup any additional cores. */ - printk(BIOS_DEBUG, "start_other_cores()\n"); - start_other_cores(bsp_apicid); - post_code(0x37); - wait_all_other_cores_started(bsp_apicid); - #endif - - post_code(0x38); - - /* run _early_setup before soft-reset. */ - rs780_early_setup(); - sb7xx_51xx_early_setup(); - - #if CONFIG(SET_FIDVID) - msr = rdmsr(MSR_COFVID_STS); - printk(BIOS_DEBUG, "\nBegin FIDVID MSR 0xc0010071 0x%08x 0x%08x\n", msr.hi, msr.lo); - - /* FIXME: The sb fid change may survive the warm reset and only - need to be done once.*/ - enable_fid_change_on_sb(sysinfo->sbbusn, sysinfo->sbdn); - - post_code(0x39); - - if (!warm_reset_detect(0)) { // BSP is node 0 - init_fidvid_bsp(bsp_apicid, sysinfo->nodes); - } else { - init_fidvid_stage2(bsp_apicid, 0); // BSP is node 0 - } - - post_code(0x3A); - - /* show final fid and vid */ - msr = rdmsr(MSR_COFVID_STS); - printk(BIOS_DEBUG, "End FIDVIDMSR 0xc0010071 0x%08x 0x%08x\n", msr.hi, msr.lo); - #endif - - rs780_htinit(); - - /* Reset for HT, FIDVID, PLL and errata changes to take affect. */ - if (!warm_reset_detect(0)) { - printk(BIOS_INFO, "...WARM RESET...\n\n\n"); - soft_reset(); - die("After soft_reset - shouldn't see this message!!!\n"); - } - - post_code(0x3B); - - /* It's the time to set ctrl in sysinfo now; */ - printk(BIOS_DEBUG, "fill_mem_ctrl()\n"); - fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr); - - post_code(0x40); - - raminit_amdmct(sysinfo); - - cbmem_initialize_empty(); - post_code(0x41); - - amdmct_cbmem_store_info(sysinfo); - - sb7xx_51xx_before_pci_init(); - - post_code(0x42); -} - -/** - * BOOL AMD_CB_ManualBUIDSwapList(u8 Node, u8 Link, u8 **List) - * Description: - * This routine is called every time a non-coherent chain is processed. - * BUID assignment may be controlled explicitly on a non-coherent chain. Provide a - * swap list. The first part of the list controls the BUID assignment and the - * second part of the list provides the device to device linking. Device orientation - * can be detected automatically, or explicitly. See documentation for more details. - * - * Automatic non-coherent init assigns BUIDs starting at 1 and incrementing sequentially - * based on each device's unit count. - * - * Parameters: - * @param[in] node = The node on which this chain is located - * @param[in] link = The link on the host for this chain - * @param[out] List = supply a pointer to a list - */ -BOOL AMD_CB_ManualBUIDSwapList (u8 node, u8 link, const u8 **List) -{ -#if !CONFIG(BOARD_ASUS_M4A785TM) - static const u8 swaplist[] = { 0xFF, CONFIG_HT_CHAIN_UNITID_BASE, CONFIG_HT_CHAIN_END_UNITID_BASE, 0xFF }; - /* If the BUID was adjusted in early_ht we need to do the manual override */ - if ((CONFIG_HT_CHAIN_UNITID_BASE != 0) && (CONFIG_HT_CHAIN_END_UNITID_BASE != 0)) { - printk(BIOS_DEBUG, "AMD_CB_ManualBUIDSwapList()\n"); - if ((node == 0) && (link == 0)) { /* BSP SB link */ - *List = swaplist; - return 1; - } - } -#else - static const u8 swaplist[] = {0, 1, 0xFF, 0, 0xFF}; - /* If the BUID was adjusted in early_ht we need to do the manual override */ - if ((node == 0) && (link == 0)) { /* BSP SB link */ - *List = swaplist; - return 1; - } -#endif - - return 0; -} diff --git a/src/mainboard/asus/m4a785t-m/Kconfig b/src/mainboard/asus/m4a785t-m/Kconfig deleted file mode 100644 index 5cff593127..0000000000 --- a/src/mainboard/asus/m4a785t-m/Kconfig +++ /dev/null @@ -1,56 +0,0 @@ -if BOARD_ASUS_M4A785TM - -config BOARD_SPECIFIC_OPTIONS - def_bool y - select CPU_AMD_SOCKET_AM3 - select DIMM_DDR3 - select DIMM_REGISTERED - select NORTHBRIDGE_AMD_AMDFAM10 - select SOUTHBRIDGE_AMD_RS780 - select SOUTHBRIDGE_AMD_SB700 - select SOUTHBRIDGE_AMD_SB700_SKIP_ISA_DMA_INIT - select SUPERIO_ITE_IT8712F - select HAVE_OPTION_TABLE - select HAVE_CMOS_DEFAULT - select HAVE_PIRQ_TABLE - select HAVE_MP_TABLE - select SB_HT_CHAIN_UNITID_OFFSET_ONLY - select LIFT_BSP_APIC_ID - select HAVE_ACPI_TABLES - select BOARD_ROMSIZE_KB_1024 - select ENABLE_APIC_EXT_ID - select GFXUMA - -config MAINBOARD_DIR - string - default asus/m4a785t-m - -config APIC_ID_OFFSET - hex - default 0x0 - -config MAINBOARD_PART_NUMBER - string - default "M4A785T-M" - -config MAX_CPUS - int - default 8 - -config MAX_PHYSICAL_CPUS - int - default 2 - -config HT_CHAIN_END_UNITID_BASE - hex - default 0x1 - -config HT_CHAIN_UNITID_BASE - hex - default 0x0 - -config IRQ_SLOT_COUNT - int - default 19 - -endif diff --git a/src/mainboard/asus/m4a785t-m/Kconfig.name b/src/mainboard/asus/m4a785t-m/Kconfig.name deleted file mode 100644 index cc1669ed12..0000000000 --- a/src/mainboard/asus/m4a785t-m/Kconfig.name +++ /dev/null @@ -1,2 +0,0 @@ -config BOARD_ASUS_M4A785TM - bool "M4A785T-M" diff --git a/src/mainboard/asus/m4a785t-m/Makefile.inc b/src/mainboard/asus/m4a785t-m/Makefile.inc deleted file mode 100644 index 7b6cdb0d73..0000000000 --- a/src/mainboard/asus/m4a785t-m/Makefile.inc +++ /dev/null @@ -1,16 +0,0 @@ -# -# This file is part of the coreboot project. -# -# This program is free software; you can redistribute it and/or modify -# it under the terms of the GNU General Public License as published by -# the Free Software Foundation; version 2 of the License. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# - -romstage-y += ../m4a785-m/resourcemap.c - -ramstage-y += ../m4a785-m/get_bus_conf.c diff --git a/src/mainboard/asus/m4a785t-m/acpi/cpstate.asl b/src/mainboard/asus/m4a785t-m/acpi/cpstate.asl deleted file mode 100644 index e9a93c0466..0000000000 --- a/src/mainboard/asus/m4a785t-m/acpi/cpstate.asl +++ /dev/null @@ -1,100 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2010 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -/* This file defines the processor and performance state capability - * for each core in the system. It is included into the DSDT for each - * core. It assumes that each core of the system has the same performance - * characteristics. -*/ -/* -#include -DefinitionBlock ("DSDT.AML", "DSDT", 0x01, OEM_ID, ACPI_TABLE_CREATOR, 0x00010001) - { - Scope (\_PR) { - Device (CPU0) { - Name (_HID, "ACPI0007") - Name (_UID, 0) - #include "cpstate.asl" - } - Device (CPU1) { - Name (_HID, "ACPI0007") - Name (_UID, 1) - #include "cpstate.asl" - } - Device (CPU2) { - Name (_HID, "ACPI0007") - Name (_UID, 2) - #include "cpstate.asl" - } - Device (CPU3) { - Name (_HID, "ACPI0007") - Name (_UID, 3) - #include "cpstate.asl" - } - } -*/ - /* P-state support: The maximum number of P-states supported by the */ - /* CPUs we'll use is 6. */ - /* Get from AMI BIOS. */ - Name(_PSS, Package(){ - Package () - { - 0x00000BB8, - 0x000078D9, - 0x00000004, - 0x00000004, - 0x00000000, - 0x00000000 - }, - - Package () - { - 0x000008FC, - 0x0000659A, - 0x00000004, - 0x00000004, - 0x00000001, - 0x00000001 - }, - - Package () - { - 0x00000708, - 0x000056BF, - 0x00000004, - 0x00000004, - 0x00000002, - 0x00000002 - }, - - Package () - { - 0x00000320, - 0x00001FA1, - 0x00000004, - 0x00000004, - 0x00000003, - 0x00000003 - } - }) - - Name(_PCT, Package(){ - ResourceTemplate(){Register(FFixedHW, 0, 0, 0)}, - ResourceTemplate(){Register(FFixedHW, 0, 0, 0)} - }) - - Method(_PPC, 0){ - Return(0) - } diff --git a/src/mainboard/asus/m4a785t-m/acpi/ide.asl b/src/mainboard/asus/m4a785t-m/acpi/ide.asl deleted file mode 100644 index 5c155cf301..0000000000 --- a/src/mainboard/asus/m4a785t-m/acpi/ide.asl +++ /dev/null @@ -1,240 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2010 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -/* -Scope (_SB) { - Device(PCI0) { - Device(IDEC) { - Name(_ADR, 0x00140001) - #include "ide.asl" - } - } -} -*/ - -/* Some timing tables */ -Name(UDTT, Package(){ /* Udma timing table */ - 120, 90, 60, 45, 30, 20, 15, 0 /* UDMA modes 0 -> 6 */ -}) - -Name(MDTT, Package(){ /* MWDma timing table */ - 480, 150, 120, 0 /* Legacy DMA modes 0 -> 2 */ -}) - -Name(POTT, Package(){ /* Pio timing table */ - 600, 390, 270, 180, 120, 0 /* PIO modes 0 -> 4 */ -}) - -/* Some timing register value tables */ -Name(MDRT, Package(){ /* MWDma timing register table */ - 0x77, 0x21, 0x20, 0xFF /* Legacy DMA modes 0 -> 2 */ -}) - -Name(PORT, Package(){ - 0x99, 0x47, 0x34, 0x22, 0x20, 0x99 /* PIO modes 0 -> 4 */ -}) - -OperationRegion(ICRG, PCI_Config, 0x40, 0x20) /* ide control registers */ - Field(ICRG, AnyAcc, NoLock, Preserve) -{ - PPTS, 8, /* Primary PIO Slave Timing */ - PPTM, 8, /* Primary PIO Master Timing */ - OFFSET(0x04), PMTS, 8, /* Primary MWDMA Slave Timing */ - PMTM, 8, /* Primary MWDMA Master Timing */ - OFFSET(0x08), PPCR, 8, /* Primary PIO Control */ - OFFSET(0x0A), PPMM, 4, /* Primary PIO master Mode */ - PPSM, 4, /* Primary PIO slave Mode */ - OFFSET(0x14), PDCR, 2, /* Primary UDMA Control */ - OFFSET(0x16), PDMM, 4, /* Primary UltraDMA Mode */ - PDSM, 4, /* Primary UltraDMA Mode */ -} - -Method(GTTM, 1) /* get total time*/ -{ - Store(And(Arg0, 0x0F), Local0) /* Recovery Width */ - Increment(Local0) - Store(ShiftRight(Arg0, 4), Local1) /* Command Width */ - Increment(Local1) - Return(Multiply(30, Add(Local0, Local1))) -} - -Device(PRID) -{ - Name (_ADR, Zero) - Method(_GTM, 0) - { - NAME(OTBF, Buffer(20) { /* out buffer */ - 0xFF, 0xFF, 0xFF, 0xFF, - 0xFF, 0xFF, 0xFF, 0xFF, - 0xFF, 0xFF, 0xFF, 0xFF, - 0xFF, 0xFF, 0xFF, 0xFF, 0x00, 0x00, 0x00, 0x00 - }) - - CreateDwordField(OTBF, 0, PSD0) /* PIO spd0 */ - CreateDwordField(OTBF, 4, DSD0) /* DMA spd0 */ - CreateDwordField(OTBF, 8, PSD1) /* PIO spd1 */ - CreateDwordField(OTBF, 12, DSD1) /* DMA spd1 */ - CreateDwordField(OTBF, 16, BFFG) /* buffer flags */ - - /* Just return if the channel is disabled */ - If(And(PPCR, 0x01)) { /* primary PIO control */ - Return(OTBF) - } - - /* Always tell them independent timing available and IOChannelReady used on both drives */ - Or(BFFG, 0x1A, BFFG) - - Store(GTTM(PPTM), PSD0) /* save total time of primary PIO master timming to PIO spd0 */ - Store(GTTM(PPTS), PSD1) /* save total time of primary PIO slave Timing to PIO spd1 */ - - If(And(PDCR, 0x01)) { /* It's under UDMA mode */ - Or(BFFG, 0x01, BFFG) - Store(DerefOf(Index(UDTT, PDMM)), DSD0) - } - Else { - Store(GTTM(PMTM), DSD0) /* Primary MWDMA Master Timing, DmaSpd0 */ - } - - If(And(PDCR, 0x02)) { /* It's under UDMA mode */ - Or(BFFG, 0x04, BFFG) - Store(DerefOf(Index(UDTT, PDSM)), DSD1) - } - Else { - Store(GTTM(PMTS), DSD1) /* Primary MWDMA Slave Timing, DmaSpd0 */ - } - - Return(OTBF) /* out buffer */ - } /* End Method(_GTM) */ - - Method(_STM, 3, NotSerialized) - { - NAME(INBF, Buffer(20) { /* in buffer */ - 0xFF, 0xFF, 0xFF, 0xFF, - 0xFF, 0xFF, 0xFF, 0xFF, - 0xFF, 0xFF, 0xFF, 0xFF, - 0xFF, 0xFF, 0xFF, 0xFF, 0x00, 0x00, 0x00, 0x00 - }) - - CreateDwordField(INBF, 0, PSD0) /* PIO spd0 */ - CreateDwordField(INBF, 4, DSD0) /* PIO spd0 */ - CreateDwordField(INBF, 8, PSD1) /* PIO spd1 */ - CreateDwordField(INBF, 12, DSD1) /* DMA spd1 */ - CreateDwordField(INBF, 16, BFFG) /*buffer flag */ - - Store(Match(POTT, MLE, PSD0, MTR, 0, 0), Local0) - Divide(Local0, 5, PPMM,) /* Primary PIO master Mode */ - Store(Match(POTT, MLE, PSD1, MTR, 0, 0), Local1) - Divide(Local1, 5, PPSM,) /* Primary PIO slave Mode */ - - Store(DerefOf(Index(PORT, Local0)), PPTM) /* Primary PIO Master Timing */ - Store(DerefOf(Index(PORT, Local1)), PPTS) /* Primary PIO Slave Timing */ - - If(And(BFFG, 0x01)) { /* Drive 0 is under UDMA mode */ - Store(Match(UDTT, MLE, DSD0, MTR, 0, 0), Local0) - Divide(Local0, 7, PDMM,) - Or(PDCR, 0x01, PDCR) - } - Else { - If(LNotEqual(DSD0, 0xFFFFFFFF)) { - Store(Match(MDTT, MLE, DSD0, MTR, 0, 0), Local0) - Store(DerefOf(Index(MDRT, Local0)), PMTM) - } - } - - If(And(BFFG, 0x04)) { /* Drive 1 is under UDMA mode */ - Store(Match(UDTT, MLE, DSD1, MTR, 0, 0), Local0) - Divide(Local0, 7, PDSM,) - Or(PDCR, 0x02, PDCR) - } - Else { - If(LNotEqual(DSD1, 0xFFFFFFFF)) { - Store(Match(MDTT, MLE, DSD1, MTR, 0, 0), Local0) - Store(DerefOf(Index(MDRT, Local0)), PMTS) - } - } - /* Return(INBF) */ - } /*End Method(_STM) */ - Device(MST) - { - Name(_ADR, 0) - Method(_GTF) { - Name(CMBF, Buffer(21) { - 0x03, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xEF, - 0x03, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xEF, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xF5 - }) - CreateByteField(CMBF, 1, POMD) - CreateByteField(CMBF, 8, DMMD) - CreateByteField(CMBF, 5, CMDA) - CreateByteField(CMBF, 12, CMDB) - CreateByteField(CMBF, 19, CMDC) - - Store(0xA0, CMDA) - Store(0xA0, CMDB) - Store(0xA0, CMDC) - - Or(PPMM, 0x08, POMD) - - If(And(PDCR, 0x01)) { - Or(PDMM, 0x40, DMMD) - } - Else { - Store(Match - (MDTT, MLE, GTTM(PMTM), - MTR, 0, 0), Local0) - If(LLess(Local0, 3)) { - Or(0x20, Local0, DMMD) - } - } - Return(CMBF) - } - } /* End Device(MST) */ - - Device(SLAV) - { - Name(_ADR, 1) - Method(_GTF) { - Name(CMBF, Buffer(21) { - 0x03, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xEF, - 0x03, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xEF, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xF5 - }) - CreateByteField(CMBF, 1, POMD) - CreateByteField(CMBF, 8, DMMD) - CreateByteField(CMBF, 5, CMDA) - CreateByteField(CMBF, 12, CMDB) - CreateByteField(CMBF, 19, CMDC) - - Store(0xB0, CMDA) - Store(0xB0, CMDB) - Store(0xB0, CMDC) - - Or(PPSM, 0x08, POMD) - - If(And(PDCR, 0x02)) { - Or(PDSM, 0x40, DMMD) - } - Else { - Store(Match - (MDTT, MLE, GTTM(PMTS), - MTR, 0, 0), Local0) - If(LLess(Local0, 3)) { - Or(0x20, Local0, DMMD) - } - } - Return(CMBF) - } - } /* End Device(SLAV) */ -} diff --git a/src/mainboard/asus/m4a785t-m/acpi/routing.asl b/src/mainboard/asus/m4a785t-m/acpi/routing.asl deleted file mode 100644 index 072aa2117f..0000000000 --- a/src/mainboard/asus/m4a785t-m/acpi/routing.asl +++ /dev/null @@ -1,297 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2010 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -/* -#include -DefinitionBlock ("DSDT.AML", "DSDT", 0x01, OEM_ID, ACPI_TABLE_CREATOR, 0x00010001 - ) - { - #include "routing.asl" - } -*/ - -/* Routing is in System Bus scope */ -Scope(\_SB) { - Name(PR0, Package(){ - /* NB devices */ - /* Bus 0, Dev 0 - RS780 Host Controller */ - /* Bus 0, Dev 1 - PCI Bridge for Internal Graphics */ - /* Bus 0, Dev 2 - PCIe Bridge for x8 PCIe Slot (GFX0) */ - Package(){0x0002FFFF, 0, INTC, 0 }, - Package(){0x0002FFFF, 1, INTD, 0 }, - Package(){0x0002FFFF, 2, INTA, 0 }, - Package(){0x0002FFFF, 3, INTB, 0 }, - /* Bus 0, Dev 3 - PCIe graphics port 1 bridge */ - /* Bus 0, Dev 4 - PCIe Bridge for Express Card Slot */ - Package(){0x0004FFFF, 0, INTA, 0 }, - Package(){0x0004FFFF, 1, INTB, 0 }, - Package(){0x0004FFFF, 2, INTC, 0 }, - Package(){0x0004FFFF, 3, INTD, 0 }, - /* Bus 0, Dev 5 - General purpose PCIe bridge 5 */ - /* Package(){0x0005FFFF, 0, INTB, 0 }, */ - /* Package(){0x0005FFFF, 1, INTC, 0 }, */ - /* Package(){0x0005FFFF, 2, INTD, 0 }, */ - /* Package(){0x0005FFFF, 3, INTA, 0 }, */ - /* Bus 0, Dev 6 - PCIe Bridge for Ethernet Chip */ - Package(){0x0006FFFF, 0, INTC, 0 }, - Package(){0x0006FFFF, 1, INTD, 0 }, - Package(){0x0006FFFF, 2, INTA, 0 }, - Package(){0x0006FFFF, 3, INTB, 0 }, - /* Bus 0, Dev 7 - PCIe Bridge for x1 PCIe Slot */ - Package(){0x0007FFFF, 0, INTD, 0 }, - Package(){0x0007FFFF, 1, INTA, 0 }, - Package(){0x0007FFFF, 2, INTB, 0 }, - Package(){0x0007FFFF, 3, INTC, 0 }, - /* Bus 0, Funct 8 - Southbridge port (normally hidden) */ - - /* SB devices */ - /* Bus 0, Dev 17 - SATA controller #2 */ - /* Bus 0, Dev 18 - SATA controller #1 */ - Package(){0x0011FFFF, 1, INTA, 0 }, - - /* Bus 0, Dev 19 - USB: OHCI, funct 0-4; EHCI, funct 5 */ - Package(){0x0012FFFF, 0, INTA, 0 }, - Package(){0x0012FFFF, 1, INTB, 0 }, - Package(){0x0013FFFF, 0, INTA, 0 }, - Package(){0x0013FFFF, 1, INTB, 0 }, - Package(){0x0014FFFF, 2, INTA, 0 }, - - /* Bus 0, Dev 20 - F0:SMBus/ACPI,F1:IDE;F2:HDAudio;F3:LPC;F4:PCIBridge;F5:AC97 Audio;F6:AC97 Modem */ - Package(){0x0014FFFF, 0, INTA, 0 }, - Package(){0x0014FFFF, 1, INTB, 0 }, - Package(){0x0014FFFF, 2, INTC, 0 }, - Package(){0x0014FFFF, 3, INTD, 0 }, - }) - - Name(APR0, Package(){ - /* NB devices in APIC mode */ - /* Bus 0, Dev 0 - RS780 Host Controller */ - - /* Bus 0, Dev 1 - PCI Bridge for Internal Graphics */ - /* Package(){0x0001FFFF, 0, 0, 18 }, */ - /* Package(){0x0001FFFF, 1, 0, 19 }, */ - - /* Bus 0, Dev 2 - PCIe Bridge for x8 PCIe Slot (GFX0) */ - Package(){0x0002FFFF, 0, 0, 18 }, - /* Package(){0x0002FFFF, 1, 0, 19 }, */ - /* Package(){0x0002FFFF, 2, 0, 16 }, */ - /* Package(){0x0002FFFF, 3, 0, 17 }, */ - - /* Bus 0, Dev 3 - PCIe graphics port 1 bridge */ - Package(){0x0003FFFF, 0, 0, 19 }, - - /* Bus 0, Dev 4 - PCIe Bridge for Express Card Slot */ - Package(){0x0004FFFF, 0, 0, 16 }, - /* Package(){0x0004FFFF, 1, 0, 17 }, */ - /* Package(){0x0004FFFF, 2, 0, 18 }, */ - /* Package(){0x0004FFFF, 3, 0, 19 }, */ - - /* Bus 0, Dev 5 - General purpose PCIe bridge 5 */ - /* Package(){0x0005FFFF, 0, 0, 17 }, */ - /* Package(){0x0005FFFF, 1, 0, 18 }, */ - /* Package(){0x0005FFFF, 2, 0, 19 }, */ - /* Package(){0x0005FFFF, 3, 0, 16 }, */ - - /* Bus 0, Dev 6 - General purpose PCIe bridge 6 */ - /* Package(){0x0006FFFF, 0, 0, 18 }, */ - /* Package(){0x0006FFFF, 1, 0, 19 }, */ - /* Package(){0x0006FFFF, 2, 0, 16 }, */ - /* Package(){0x0006FFFF, 3, 0, 17 }, */ - - /* Bus 0, Dev 7 - PCIe Bridge for network card */ - /* Package(){0x0007FFFF, 0, 0, 19 }, */ - /* Package(){0x0007FFFF, 1, 0, 16 }, */ - /* Package(){0x0007FFFF, 2, 0, 17 }, */ - /* Package(){0x0007FFFF, 3, 0, 18 }, */ - - /* Bus 0, Dev 9 - PCIe Bridge for network card */ - Package(){0x0009FFFF, 0, 0, 17 }, - /* Package(){0x0009FFFF, 1, 0, 16 }, */ - /* Package(){0x0009FFFF, 2, 0, 17 }, */ - /* Package(){0x0009FFFF, 3, 0, 18 }, */ - /* Bus 0, Dev A - PCIe Bridge for network card */ - Package(){0x000AFFFF, 0, 0, 18 }, - /* Package(){0x000AFFFF, 1, 0, 16 }, */ - /* Package(){0x000AFFFF, 2, 0, 17 }, */ - /* Package(){0x000AFFFF, 3, 0, 18 }, */ - /* Bus 0, Funct 8 - Southbridge port (normally hidden) */ - - /* SB devices in APIC mode */ - /* Bus 0, Dev 17 - SATA controller #2 */ - /* Bus 0, Dev 18 - SATA controller #1 */ - Package(){0x0011FFFF, 0, 0, 22 }, - - /* Bus 0, Dev 19 - USB: OHCI, funct 0-4; EHCI, funct 5 */ - Package(){0x0012FFFF, 0, 0, 16 }, - Package(){0x0012FFFF, 1, 0, 17 }, - Package(){0x0013FFFF, 0, 0, 18 }, - Package(){0x0013FFFF, 1, 0, 19 }, - Package(){0x0014FFFF, 0, 0, 16 }, - /* Package(){0x00130004, 2, 0, 18 }, */ - /* Package(){0x00130005, 3, 0, 19 }, */ - - /* Bus 0, Dev 20 - F0:SMBus/ACPI, F1:IDE; F2:HDAudio; F3:LPC; F4:PCIBridge; F5:AC97 Audio; F6:AC97 Modem */ - Package(){0x0014FFFF, 0, 0, 16 }, - Package(){0x0014FFFF, 1, 0, 17 }, - Package(){0x0014FFFF, 2, 0, 18 }, - Package(){0x0014FFFF, 3, 0, 19 }, - /* Package(){0x00140004, 2, 0, 18 }, */ - /* Package(){0x00140004, 3, 0, 19 }, */ - /* Package(){0x00140005, 1, 0, 17 }, */ - /* Package(){0x00140006, 1, 0, 17 }, */ - }) - - Name(PR1, Package(){ - /* Internal graphics - RS780 VGA, Bus1, Dev5 */ - Package(){0x0005FFFF, 0, INTA, 0 }, - Package(){0x0005FFFF, 1, INTB, 0 }, - Package(){0x0005FFFF, 2, INTC, 0 }, - Package(){0x0005FFFF, 3, INTD, 0 }, - }) - - Name(APR1, Package(){ - /* Internal graphics - RS780 VGA, Bus1, Dev5 */ - Package(){0x0005FFFF, 0, 0, 18 }, - Package(){0x0005FFFF, 1, 0, 19 }, - /* Package(){0x0005FFFF, 2, 0, 20 }, */ - /* Package(){0x0005FFFF, 3, 0, 17 }, */ - }) - - Name(PS2, Package(){ - /* The external GFX - Hooked to PCIe slot 2 */ - Package(){0x0000FFFF, 0, INTC, 0 }, - Package(){0x0000FFFF, 1, INTD, 0 }, - Package(){0x0000FFFF, 2, INTA, 0 }, - Package(){0x0000FFFF, 3, INTB, 0 }, - }) - - Name(APS2, Package(){ - /* The external GFX - Hooked to PCIe slot 2 */ - Package(){0x0000FFFF, 0, 0, 18 }, - Package(){0x0000FFFF, 1, 0, 19 }, - Package(){0x0000FFFF, 2, 0, 16 }, - Package(){0x0000FFFF, 3, 0, 17 }, - }) - - Name(PS4, Package(){ - /* PCIe slot - Hooked to PCIe slot 4 */ - Package(){0x0000FFFF, 0, INTA, 0 }, - Package(){0x0000FFFF, 1, INTB, 0 }, - Package(){0x0000FFFF, 2, INTC, 0 }, - Package(){0x0000FFFF, 3, INTD, 0 }, - }) - - Name(APS4, Package(){ - /* PCIe slot - Hooked to PCIe slot 4 */ - Package(){0x0000FFFF, 0, 0, 16 }, - Package(){0x0000FFFF, 1, 0, 17 }, - Package(){0x0000FFFF, 2, 0, 18 }, - Package(){0x0000FFFF, 3, 0, 19 }, - }) - - Name(PS5, Package(){ - /* PCIe slot - Hooked to PCIe slot 5 */ - Package(){0x0000FFFF, 0, INTB, 0 }, - Package(){0x0000FFFF, 1, INTC, 0 }, - Package(){0x0000FFFF, 2, INTD, 0 }, - Package(){0x0000FFFF, 3, INTA, 0 }, - }) - - Name(APS5, Package(){ - /* PCIe slot - Hooked to PCIe slot 5 */ - Package(){0x0000FFFF, 0, 0, 17 }, - Package(){0x0000FFFF, 1, 0, 18 }, - Package(){0x0000FFFF, 2, 0, 19 }, - Package(){0x0000FFFF, 3, 0, 16 }, - }) - - Name(PS6, Package(){ - /* PCIe slot - Hooked to PCIe slot 6 */ - Package(){0x0000FFFF, 0, INTC, 0 }, - Package(){0x0000FFFF, 1, INTD, 0 }, - Package(){0x0000FFFF, 2, INTA, 0 }, - Package(){0x0000FFFF, 3, INTB, 0 }, - }) - - Name(APS6, Package(){ - /* PCIe slot - Hooked to PCIe slot 6 */ - Package(){0x0000FFFF, 0, 0, 18 }, - Package(){0x0000FFFF, 1, 0, 19 }, - Package(){0x0000FFFF, 2, 0, 16 }, - Package(){0x0000FFFF, 3, 0, 17 }, - }) - - Name(PS7, Package(){ - /* The onboard Ethernet chip - Hooked to PCIe slot 7 */ - Package(){0x0000FFFF, 0, INTD, 0 }, - Package(){0x0000FFFF, 1, INTA, 0 }, - Package(){0x0000FFFF, 2, INTB, 0 }, - Package(){0x0000FFFF, 3, INTC, 0 }, - }) - - Name(APS7, Package(){ - /* The onboard Ethernet chip - Hooked to PCIe slot 7 */ - Package(){0x0000FFFF, 0, 0, 19 }, - Package(){0x0000FFFF, 1, 0, 16 }, - Package(){0x0000FFFF, 2, 0, 17 }, - Package(){0x0000FFFF, 3, 0, 18 }, - }) - Name(PS9, Package(){ - /* PCIe slot - Hooked to PCIe slot 9 */ - Package(){0x0000FFFF, 0, INTD, 0 }, - Package(){0x0000FFFF, 1, INTA, 0 }, - Package(){0x0000FFFF, 2, INTB, 0 }, - Package(){0x0000FFFF, 3, INTC, 0 }, - }) - - Name(APS9, Package(){ - /* PCIe slot - Hooked to PCIe slot 9 */ - Package(){0x0000FFFF, 0, 0, 17 }, - Package(){0x0000FFFF, 1, 0, 18 }, - Package(){0x0000FFFF, 2, 0, 19 }, - Package(){0x0000FFFF, 3, 0, 16 }, - }) - Name(PSa, Package(){ - /* PCIe slot - Hooked to PCIe slot 10 */ - Package(){0x0000FFFF, 0, INTD, 0 }, - Package(){0x0000FFFF, 1, INTA, 0 }, - Package(){0x0000FFFF, 2, INTB, 0 }, - Package(){0x0000FFFF, 3, INTC, 0 }, - }) - - Name(APSa, Package(){ - /* PCIe slot - Hooked to PCIe slot 10 */ - Package(){0x0000FFFF, 0, 0, 18 }, - Package(){0x0000FFFF, 1, 0, 19 }, - Package(){0x0000FFFF, 2, 0, 16 }, - Package(){0x0000FFFF, 3, 0, 17 }, - }) - - Name(PCIB, Package(){ - /* PCI slots: slot 0, slot 1, slot 2 behind Dev14, Fun4. */ - Package(){0x0005FFFF, 0, 0, 0x14 }, - Package(){0x0005FFFF, 1, 0, 0x15 }, - Package(){0x0005FFFF, 2, 0, 0x16 }, - Package(){0x0005FFFF, 3, 0, 0x17 }, - Package(){0x0006FFFF, 0, 0, 0x15 }, - Package(){0x0006FFFF, 1, 0, 0x16 }, - Package(){0x0006FFFF, 2, 0, 0x17 }, - Package(){0x0006FFFF, 3, 0, 0x14 }, - Package(){0x0007FFFF, 0, 0, 0x16 }, - Package(){0x0007FFFF, 1, 0, 0x17 }, - Package(){0x0007FFFF, 2, 0, 0x14 }, - Package(){0x0007FFFF, 3, 0, 0x15 }, - }) -} diff --git a/src/mainboard/asus/m4a785t-m/acpi/sata.asl b/src/mainboard/asus/m4a785t-m/acpi/sata.asl deleted file mode 100644 index cb9b221ba3..0000000000 --- a/src/mainboard/asus/m4a785t-m/acpi/sata.asl +++ /dev/null @@ -1,145 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2010 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -/* simple name description */ - -/* -Scope (_SB) { - Device(PCI0) { - Device(SATA) { - Name(_ADR, 0x00110000) - #include "sata.asl" - } - } -} -*/ - -Name(STTM, Buffer(20) { - 0x78, 0x00, 0x00, 0x00, 0x0f, 0x00, 0x00, 0x00, - 0x78, 0x00, 0x00, 0x00, 0x0f, 0x00, 0x00, 0x00, - 0x1f, 0x00, 0x00, 0x00 -}) - -/* Start by clearing the PhyRdyChg bits */ -Method(_INI) { - \_GPE._L1F() -} - -Device(PMRY) -{ - Name(_ADR, 0) - Method(_GTM, 0x0, NotSerialized) { - Return(STTM) - } - Method(_STM, 0x3, NotSerialized) {} - - Device(PMST) { - Name(_ADR, 0) - Method(_STA,0) { - if (LGreater(P0IS,0)) { - return (0x0F) /* sata is visible */ - } - else { - return (0x00) /* sata is missing */ - } - } - }/* end of PMST */ - - Device(PSLA) - { - Name(_ADR, 1) - Method(_STA,0) { - if (LGreater(P1IS,0)) { - return (0x0F) /* sata is visible */ - } - else { - return (0x00) /* sata is missing */ - } - } - } /* end of PSLA */ -} /* end of PMRY */ - - -Device(SEDY) -{ - Name(_ADR, 1) /* IDE Scondary Channel */ - Method(_GTM, 0x0, NotSerialized) { - Return(STTM) - } - Method(_STM, 0x3, NotSerialized) {} - - Device(SMST) - { - Name(_ADR, 0) - Method(_STA,0) { - if (LGreater(P2IS,0)) { - return (0x0F) /* sata is visible */ - } - else { - return (0x00) /* sata is missing */ - } - } - } /* end of SMST */ - - Device(SSLA) - { - Name(_ADR, 1) - Method(_STA,0) { - if (LGreater(P3IS,0)) { - return (0x0F) /* sata is visible */ - } - else { - return (0x00) /* sata is missing */ - } - } - } /* end of SSLA */ -} /* end of SEDY */ - -/* SATA Hot Plug Support */ -Scope(\_GPE) { - Method(_L1F,0x0,NotSerialized) { - if (\_SB.P0PR) { - if (LGreater(\_SB.P0IS,0)) { - sleep(32) - } - Notify(\_SB.PCI0.STCR.PMRY.PMST, 0x01) /* NOTIFY_DEVICE_CHECK */ - store(one, \_SB.P0PR) - } - - if (\_SB.P1PR) { - if (LGreater(\_SB.P1IS,0)) { - sleep(32) - } - Notify(\_SB.PCI0.STCR.PMRY.PSLA, 0x01) /* NOTIFY_DEVICE_CHECK */ - store(one, \_SB.P1PR) - } - - if (\_SB.P2PR) { - if (LGreater(\_SB.P2IS,0)) { - sleep(32) - } - Notify(\_SB.PCI0.STCR.SEDY.SMST, 0x01) /* NOTIFY_DEVICE_CHECK */ - store(one, \_SB.P2PR) - } - - if (\_SB.P3PR) { - if (LGreater(\_SB.P3IS,0)) { - sleep(32) - } - Notify(\_SB.PCI0.STCR.SEDY.SSLA, 0x01) /* NOTIFY_DEVICE_CHECK */ - store(one, \_SB.P3PR) - } - } -} diff --git a/src/mainboard/asus/m4a785t-m/acpi/usb.asl b/src/mainboard/asus/m4a785t-m/acpi/usb.asl deleted file mode 100644 index a3ccb97ff9..0000000000 --- a/src/mainboard/asus/m4a785t-m/acpi/usb.asl +++ /dev/null @@ -1,158 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2010 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -/* simple name description */ -/* -#include -DefinitionBlock ("DSDT.AML", "DSDT", 0x01, OEM_ID, ACPI_TABLE_CREATOR, 0x00010001 - ) - { - #include "usb.asl" - } -*/ -Method(UCOC, 0) { - Sleep(20) - Store(0x13,CMTI) - Store(0,GPSL) -} - -/* USB Port 0 overcurrent uses Gpm 0 */ -If(LLessEqual(UOM0,9)) { - Scope (\_GPE) { - Method (_L13) { - UCOC() - if(LEqual(GPB0,PLC0)) { - Not(PLC0,PLC0) - Store(PLC0, \_SB.PT0D) - } - } - } -} - -/* USB Port 1 overcurrent uses Gpm 1 */ -If (LLessEqual(UOM1,9)) { - Scope (\_GPE) { - Method (_L14) { - UCOC() - if (LEqual(GPB1,PLC1)) { - Not(PLC1,PLC1) - Store(PLC1, \_SB.PT1D) - } - } - } -} - -/* USB Port 2 overcurrent uses Gpm 2 */ -If (LLessEqual(UOM2,9)) { - Scope (\_GPE) { - Method (_L15) { - UCOC() - if (LEqual(GPB2,PLC2)) { - Not(PLC2,PLC2) - Store(PLC2, \_SB.PT2D) - } - } - } -} - -/* USB Port 3 overcurrent uses Gpm 3 */ -If (LLessEqual(UOM3,9)) { - Scope (\_GPE) { - Method (_L16) { - UCOC() - if (LEqual(GPB3,PLC3)) { - Not(PLC3,PLC3) - Store(PLC3, \_SB.PT3D) - } - } - } -} - -/* USB Port 4 overcurrent uses Gpm 4 */ -If (LLessEqual(UOM4,9)) { - Scope (\_GPE) { - Method (_L19) { - UCOC() - if (LEqual(GPB4,PLC4)) { - Not(PLC4,PLC4) - Store(PLC4, \_SB.PT4D) - } - } - } -} - -/* USB Port 5 overcurrent uses Gpm 5 */ -If (LLessEqual(UOM5,9)) { - Scope (\_GPE) { - Method (_L1A) { - UCOC() - if (LEqual(GPB5,PLC5)) { - Not(PLC5,PLC5) - Store(PLC5, \_SB.PT5D) - } - } - } -} - -/* USB Port 6 overcurrent uses Gpm 6 */ -If (LLessEqual(UOM6,9)) { - Scope (\_GPE) { - /* Method (_L1C) { */ - Method (_L06) { - UCOC() - if (LEqual(GPB6,PLC6)) { - Not(PLC6,PLC6) - Store(PLC6, \_SB.PT6D) - } - } - } -} - -/* USB Port 7 overcurrent uses Gpm 7 */ -If (LLessEqual(UOM7,9)) { - Scope (\_GPE) { - /* Method (_L1D) { */ - Method (_L07) { - UCOC() - if (LEqual(GPB7,PLC7)) { - Not(PLC7,PLC7) - Store(PLC7, \_SB.PT7D) - } - } - } -} - -/* USB Port 8 overcurrent uses Gpm 8 */ -If (LLessEqual(UOM8,9)) { - Scope (\_GPE) { - Method (_L17) { - if (LEqual(G8IS,PLC8)) { - Not(PLC8,PLC8) - Store(PLC8, \_SB.PT8D) - } - } - } -} - -/* USB Port 9 overcurrent uses Gpm 9 */ -If (LLessEqual(UOM9,9)) { - Scope (\_GPE) { - Method (_L0E) { - if (LEqual(G9IS,0)) { - Store(1,\_SB.PT9D) - } - } - } -} diff --git a/src/mainboard/asus/m4a785t-m/acpi_tables.c b/src/mainboard/asus/m4a785t-m/acpi_tables.c deleted file mode 100644 index 6bfcbabc5e..0000000000 --- a/src/mainboard/asus/m4a785t-m/acpi_tables.c +++ /dev/null @@ -1,17 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 Denis 'GNUtoo' Carikli - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include "../m4a785-m/acpi_tables.c" diff --git a/src/mainboard/asus/m4a785t-m/board_info.txt b/src/mainboard/asus/m4a785t-m/board_info.txt deleted file mode 100644 index f8deca67fe..0000000000 --- a/src/mainboard/asus/m4a785t-m/board_info.txt +++ /dev/null @@ -1,7 +0,0 @@ -Category: desktop -Board URL: http://www.asus.com/Motherboards/AMD_AM3/M4A785TM/ -ROM package: DIP8 -ROM protocol: SPI -ROM socketed: y -Flashrom support: y -Release year: 2009 diff --git a/src/mainboard/asus/m4a785t-m/cmos.default b/src/mainboard/asus/m4a785t-m/cmos.default deleted file mode 100644 index bb2db49d7d..0000000000 --- a/src/mainboard/asus/m4a785t-m/cmos.default +++ /dev/null @@ -1,11 +0,0 @@ -boot_option=Fallback -ECC_memory=Enable -hw_scrubber=Enable -interleave_chip_selects=Enable -max_mem_clock=400Mhz -multi_core=Enable -power_on_after_fail=Disable -debug_level=Debug -slow_cpu=off -nmi=Enable -gart=Enable diff --git a/src/mainboard/asus/m4a785t-m/cmos.layout b/src/mainboard/asus/m4a785t-m/cmos.layout deleted file mode 100644 index 6c3d3f6c9e..0000000000 --- a/src/mainboard/asus/m4a785t-m/cmos.layout +++ /dev/null @@ -1,52 +0,0 @@ -entries - -0 384 r 0 reserved_memory -384 1 e 4 boot_option -388 4 h 0 reboot_counter -#392 3 r 0 unused -395 1 e 1 hw_scrubber -396 1 e 1 interleave_chip_selects -397 2 e 8 max_mem_clock -399 1 e 2 multi_core -400 1 e 1 power_on_after_fail -412 4 e 6 debug_level -440 4 e 9 slow_cpu -444 1 e 1 nmi -445 1 e 1 gart -456 1 e 1 ECC_memory -728 256 h 0 user_data -984 16 h 0 check_sum -# Reserve the extended AMD configuration registers -1000 24 r 0 amd_reserved - - - -enumerations - -#ID value text -1 0 Disable -1 1 Enable -2 0 Enable -2 1 Disable -4 0 Fallback -4 1 Normal -6 5 Notice -6 6 Info -6 7 Debug -6 8 Spew -8 0 400Mhz -8 1 333Mhz -8 2 266Mhz -8 3 200Mhz -9 0 off -9 1 87.5% -9 2 75.0% -9 3 62.5% -9 4 50.0% -9 5 37.5% -9 6 25.0% -9 7 12.5% - -checksums - -checksum 392 983 984 diff --git a/src/mainboard/asus/m4a785t-m/devicetree.cb b/src/mainboard/asus/m4a785t-m/devicetree.cb deleted file mode 100644 index 6fce0f377c..0000000000 --- a/src/mainboard/asus/m4a785t-m/devicetree.cb +++ /dev/null @@ -1,108 +0,0 @@ -chip northbridge/amd/amdfam10/root_complex - device cpu_cluster 0 on - chip cpu/amd/socket_AM3 #L1 and DDR2 - device lapic 0 on end - end - end - device domain 0 on - subsystemid 0x1043 0x83a2 inherit - chip northbridge/amd/amdfam10 - device pci 18.0 on # northbridge - chip southbridge/amd/rs780 - device pci 0.0 on end # HT 0x9600 - device pci 1.0 on # Internal Graphics P2P bridge 0x9602 - device pci 5.0 on end # onboard VGA - end - device pci 2.0 on end # PCIE P2P bridge (external graphics) 0x9603 - device pci 3.0 off end # PCIE P2P bridge 0x960b - device pci 4.0 off end # PCIE P2P bridge 0x9604 - device pci 5.0 off end # PCIE P2P bridge 0x9605 - device pci 6.0 off end # PCIE P2P bridge 0x9606 - device pci 7.0 off end # PCIE P2P bridge 0x9607 - device pci 8.0 off end # NB/SB Link P2P bridge - device pci 9.0 off end # - device pci a.0 on end # bridge to RTL8111/8168B PCI Express Gigabit Ethernet - register "gppsb_configuration" = "1" # Configuration B - register "gpp_configuration" = "3" # Configuration D default - register "port_enable" = "0x6fc" - register "gfx_dev2_dev3" = "1" - register "gfx_dual_slot" = "0" - - register "gfx_lane_reversal" = "0" - register "gfx_tmds" = "0" - register "gfx_compliance" = "0" - register "gfx_reconfiguration" = "1" - register "gfx_link_width" = "0" - end - chip southbridge/amd/sb700 # it is under NB/SB Link, but on the same pri bus - device pci 11.0 on end # SATA - device pci 12.0 on end # USB - device pci 12.1 on end # USB - device pci 12.2 on end # USB - device pci 13.0 on end # USB - device pci 13.1 on end # USB - device pci 13.2 on end # USB - device pci 14.0 on # SM - chip drivers/generic/generic #dimm 0-0-0 - device i2c 50 on end - end - chip drivers/generic/generic #dimm 0-0-1 - device i2c 51 on end - end - chip drivers/generic/generic #dimm 0-1-0 - device i2c 52 on end - end - chip drivers/generic/generic #dimm 0-1-1 - device i2c 53 on end - end - end # SM - device pci 14.1 on end # IDE 0x439c - device pci 14.2 on end # HDA 0x4383 - device pci 14.3 on # LPC 0x439d - chip superio/ite/it8712f - device pnp 2e.0 off end # Floppy - device pnp 2e.1 on # Com1 - io 0x60 = 0x3f8 - irq 0x70 = 4 - end - device pnp 2e.2 off # Com2 - io 0x60 = 0x2f8 - irq 0x70 = 3 - end - device pnp 2e.3 off # Parallel Port - io 0x60 = 0x378 - irq 0x70 = 7 - end - device pnp 2e.4 off end # Environment Controller - device pnp 2e.5 on # Keyboard - io 0x60 = 0x60 - io 0x62 = 0x64 - irq 0x70 = 1 - end - device pnp 2e.6 on # Mouse - irq 0x70 = 12 - end - device pnp 2e.7 off # GPIO, must be closed for unresolved reason. - end - device pnp 2e.8 off # MIDI - end - device pnp 2e.9 off # GAME - end - device pnp 2e.a off end # CIR - end #superio - end #LPC - device pci 14.4 on end # PCI to PCI Bridge [1002:4384] - device pci 14.5 on end # USB 2 - register "boot_switch_sata_ide" = "0" # 0: boot from SATA. 1: IDE - end #southbridge/amd/sb700 - end # device pci 18.0 - - device pci 18.0 on end - device pci 18.0 on end - device pci 18.1 on end - device pci 18.2 on end - device pci 18.3 on end - device pci 18.4 on end - end # chip northbridge - end #domain -end # northbridge/amd/amdfam10/root_complex diff --git a/src/mainboard/asus/m4a785t-m/dsdt.asl b/src/mainboard/asus/m4a785t-m/dsdt.asl deleted file mode 100644 index 20d74d0426..0000000000 --- a/src/mainboard/asus/m4a785t-m/dsdt.asl +++ /dev/null @@ -1,1641 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2010 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -/* DefinitionBlock Statement */ -#include -DefinitionBlock ( - "DSDT.AML", /* Output filename */ - "DSDT", /* Signature */ - 0x02, /* DSDT Revision, needs to be 2 for 64bit */ - OEM_ID, - ACPI_TABLE_CREATOR, - 0x00010001 /* OEM Revision */ - ) -{ /* Start of ASL file */ - /* #include */ /* Include global debug methods if needed */ - - /* Data to be patched by the BIOS during POST */ - /* FIXME the patching is not done yet! */ - /* Memory related values */ - Name(LOMH, 0x0) /* Start of unused memory in C0000-E0000 range */ - Name(PBAD, 0x0) /* Address of BIOS area (If TOM2 != 0, Addr >> 16) */ - Name(PBLN, 0x0) /* Length of BIOS area */ - - Name(PCBA,CONFIG_MMCONF_BASE_ADDRESS) /* Base address of PCIe config space */ - Name(HPBA, 0xFED00000) /* Base address of HPET table */ - - /* USB overcurrent mapping pins. */ - Name(UOM0, 0) - Name(UOM1, 2) - Name(UOM2, 0) - Name(UOM3, 7) - Name(UOM4, 2) - Name(UOM5, 2) - Name(UOM6, 6) - Name(UOM7, 2) - Name(UOM8, 6) - Name(UOM9, 6) - - /* Some global data */ - Name(OSVR, 3) /* Assume nothing. WinXp = 1, Vista = 2, Linux = 3, WinCE = 4 */ - Name(OSV, Ones) /* Assume nothing */ - Name(PMOD, One) /* Assume APIC */ - - /* - * Processor Object - * - */ - Scope (\_PR) { /* define processor scope */ - Device (CPU0) { - Name (_HID, "ACPI0007") - Name (_UID, 0) - #include "acpi/cpstate.asl" - } - Device (CPU1) { - Name (_HID, "ACPI0007") - Name (_UID, 1) - #include "acpi/cpstate.asl" - } - Device (CPU2) { - Name (_HID, "ACPI0007") - Name (_UID, 2) - #include "acpi/cpstate.asl" - } - Device (CPU3) { - Name (_HID, "ACPI0007") - Name (_UID, 3) - #include "acpi/cpstate.asl" - } - } /* End _PR scope */ - - /* PIC IRQ mapping registers, C00h-C01h */ - OperationRegion(PRQM, SystemIO, 0x00000C00, 0x00000002) - Field(PRQM, ByteAcc, NoLock, Preserve) { - PRQI, 0x00000008, - PRQD, 0x00000008, /* Offset: 1h */ - } - IndexField(PRQI, PRQD, ByteAcc, NoLock, Preserve) { - PINA, 0x00000008, /* Index 0 */ - PINB, 0x00000008, /* Index 1 */ - PINC, 0x00000008, /* Index 2 */ - PIND, 0x00000008, /* Index 3 */ - AINT, 0x00000008, /* Index 4 */ - SINT, 0x00000008, /* Index 5 */ - , 0x00000008, /* Index 6 */ - AAUD, 0x00000008, /* Index 7 */ - AMOD, 0x00000008, /* Index 8 */ - PINE, 0x00000008, /* Index 9 */ - PINF, 0x00000008, /* Index A */ - PING, 0x00000008, /* Index B */ - PINH, 0x00000008, /* Index C */ - } - - /* PCI Error control register */ - OperationRegion(PERC, SystemIO, 0x00000C14, 0x00000001) - Field(PERC, ByteAcc, NoLock, Preserve) { - SENS, 0x00000001, - PENS, 0x00000001, - SENE, 0x00000001, - PENE, 0x00000001, - } - - /* Client Management index/data registers */ - OperationRegion(CMT, SystemIO, 0x00000C50, 0x00000002) - Field(CMT, ByteAcc, NoLock, Preserve) { - CMTI, 8, - /* Client Management Data register */ - G64E, 1, - G64O, 1, - G32O, 2, - , 2, - GPSL, 2, - } - - /* GPM Port register */ - OperationRegion(GPT, SystemIO, 0x00000C52, 0x00000001) - Field(GPT, ByteAcc, NoLock, Preserve) { - GPB0,1, - GPB1,1, - GPB2,1, - GPB3,1, - GPB4,1, - GPB5,1, - GPB6,1, - GPB7,1, - } - - /* Flash ROM program enable register */ - OperationRegion(FRE, SystemIO, 0x00000C6F, 0x00000001) - Field(FRE, ByteAcc, NoLock, Preserve) { - , 0x00000006, - FLRE, 0x00000001, - } - - /* PM2 index/data registers */ - OperationRegion(PM2R, SystemIO, 0x00000CD0, 0x00000002) - Field(PM2R, ByteAcc, NoLock, Preserve) { - PM2I, 0x00000008, - PM2D, 0x00000008, - } - - /* Power Management I/O registers */ - OperationRegion(PIOR, SystemIO, 0x00000CD6, 0x00000002) - Field(PIOR, ByteAcc, NoLock, Preserve) { - PIOI, 0x00000008, - PIOD, 0x00000008, - } - IndexField (PIOI, PIOD, ByteAcc, NoLock, Preserve) { - Offset(0x00), /* MiscControl */ - , 1, - T1EE, 1, - T2EE, 1, - Offset(0x01), /* MiscStatus */ - , 1, - T1E, 1, - T2E, 1, - Offset(0x04), /* SmiWakeUpEventEnable3 */ - , 7, - SSEN, 1, - Offset(0x07), /* SmiWakeUpEventStatus3 */ - , 7, - CSSM, 1, - Offset(0x10), /* AcpiEnable */ - , 6, - PWDE, 1, - Offset(0x1C), /* ProgramIoEnable */ - , 3, - MKME, 1, - IO3E, 1, - IO2E, 1, - IO1E, 1, - IO0E, 1, - Offset(0x1D), /* IOMonitorStatus */ - , 3, - MKMS, 1, - IO3S, 1, - IO2S, 1, - IO1S, 1, - IO0S,1, - Offset(0x20), /* AcpiPmEvtBlk */ - APEB, 16, - Offset(0x36), /* GEvtLevelConfig */ - , 6, - ELC6, 1, - ELC7, 1, - Offset(0x37), /* GPMLevelConfig0 */ - , 3, - PLC0, 1, - PLC1, 1, - PLC2, 1, - PLC3, 1, - PLC8, 1, - Offset(0x38), /* GPMLevelConfig1 */ - , 1, - PLC4, 1, - PLC5, 1, - , 1, - PLC6, 1, - PLC7, 1, - Offset(0x3B), /* PMEStatus1 */ - GP0S, 1, - GM4S, 1, - GM5S, 1, - APS, 1, - GM6S, 1, - GM7S, 1, - GP2S, 1, - STSS, 1, - Offset(0x55), /* SoftPciRst */ - SPRE, 1, - , 1, - , 1, - PNAT, 1, - PWMK, 1, - PWNS, 1, - - /* Offset(0x61), */ /* Options_1 */ - /* ,7, */ - /* R617,1, */ - - Offset(0x65), /* UsbPMControl */ - , 4, - URRE, 1, - Offset(0x68), /* MiscEnable68 */ - , 3, - TMTE, 1, - , 1, - Offset(0x92), /* GEVENTIN */ - , 7, - E7IS, 1, - Offset(0x96), /* GPM98IN */ - G8IS, 1, - G9IS, 1, - Offset(0x9A), /* EnhanceControl */ - ,7, - HPDE, 1, - Offset(0xA8), /* PIO7654Enable */ - IO4E, 1, - IO5E, 1, - IO6E, 1, - IO7E, 1, - Offset(0xA9), /* PIO7654Status */ - IO4S, 1, - IO5S, 1, - IO6S, 1, - IO7S, 1, - } - - /* PM1 Event Block - * First word is PM1_Status, Second word is PM1_Enable - */ - OperationRegion(P1EB, SystemIO, APEB, 0x04) - Field(P1EB, ByteAcc, NoLock, Preserve) { - TMST, 1, - , 3, - BMST, 1, - GBST, 1, - Offset(0x01), - PBST, 1, - , 1, - RTST, 1, - , 3, - PWST, 1, - SPWS, 1, - Offset(0x02), - TMEN, 1, - , 4, - GBEN, 1, - Offset(0x03), - PBEN, 1, - , 1, - RTEN, 1, - , 3, - PWDA, 1, - } - - Scope(\_SB) { - /* PCIe Configuration Space for 16 busses */ - OperationRegion(PCFG, SystemMemory, PCBA, 0x01000000) /* Each bus consumes 1MB */ - Field(PCFG, ByteAcc, NoLock, Preserve) { - /* Byte offsets are computed using the following technique: - * ((bus number + 1) * ((device number * 8) * 4096)) + register offset - * The 8 comes from 8 functions per device, and 4096 bytes per function config space - */ - Offset(0x00088024), /* Byte offset to SATA register 24h - Bus 0, Device 17, Function 0 */ - STB5, 32, - Offset(0x00098042), /* Byte offset to OHCI0 register 42h - Bus 0, Device 19, Function 0 */ - PT0D, 1, - PT1D, 1, - PT2D, 1, - PT3D, 1, - PT4D, 1, - PT5D, 1, - PT6D, 1, - PT7D, 1, - PT8D, 1, - PT9D, 1, - Offset(0x000A0004), /* Byte offset to SMBUS register 4h - Bus 0, Device 20, Function 0 */ - SBIE, 1, - SBME, 1, - Offset(0x000A0008), /* Byte offset to SMBUS register 8h - Bus 0, Device 20, Function 0 */ - SBRI, 8, - Offset(0x000A0014), /* Byte offset to SMBUS register 14h - Bus 0, Device 20, Function 0 */ - SBB1, 32, - Offset(0x000A0078), /* Byte offset to SMBUS register 78h - Bus 0, Device 20, Function 0 */ - ,14, - P92E, 1, /* Port92 decode enable */ - } - - OperationRegion(SB5, SystemMemory, STB5, 0x1000) - Field(SB5, AnyAcc, NoLock, Preserve){ - /* Port 0 */ - Offset(0x120), /* Port 0 Task file status */ - P0ER, 1, - , 2, - P0DQ, 1, - , 3, - P0BY, 1, - Offset(0x128), /* Port 0 Serial ATA status */ - P0DD, 4, - , 4, - P0IS, 4, - Offset(0x12C), /* Port 0 Serial ATA control */ - P0DI, 4, - Offset(0x130), /* Port 0 Serial ATA error */ - , 16, - P0PR, 1, - - /* Port 1 */ - offset(0x1A0), /* Port 1 Task file status */ - P1ER, 1, - , 2, - P1DQ, 1, - , 3, - P1BY, 1, - Offset(0x1A8), /* Port 1 Serial ATA status */ - P1DD, 4, - , 4, - P1IS, 4, - Offset(0x1AC), /* Port 1 Serial ATA control */ - P1DI, 4, - Offset(0x1B0), /* Port 1 Serial ATA error */ - , 16, - P1PR, 1, - - /* Port 2 */ - Offset(0x220), /* Port 2 Task file status */ - P2ER, 1, - , 2, - P2DQ, 1, - , 3, - P2BY, 1, - Offset(0x228), /* Port 2 Serial ATA status */ - P2DD, 4, - , 4, - P2IS, 4, - Offset(0x22C), /* Port 2 Serial ATA control */ - P2DI, 4, - Offset(0x230), /* Port 2 Serial ATA error */ - , 16, - P2PR, 1, - - /* Port 3 */ - Offset(0x2A0), /* Port 3 Task file status */ - P3ER, 1, - , 2, - P3DQ, 1, - , 3, - P3BY, 1, - Offset(0x2A8), /* Port 3 Serial ATA status */ - P3DD, 4, - , 4, - P3IS, 4, - Offset(0x2AC), /* Port 3 Serial ATA control */ - P3DI, 4, - Offset(0x2B0), /* Port 3 Serial ATA error */ - , 16, - P3PR, 1, - } - } - - - #include "acpi/routing.asl" - - Scope(\_SB) { - - Method(OSFL, 0){ - - if(LNotEqual(OSVR, Ones)) {Return(OSVR)} /* OS version was already detected */ - - if(CondRefOf(\_OSI)) - { - Store(1, OSVR) /* Assume some form of XP */ - if (\_OSI("Windows 2006")) /* Vista */ - { - Store(2, OSVR) - } - } else { - If(WCMP(\_OS,"Linux")) { - Store(3, OSVR) /* Linux */ - } Else { - Store(4, OSVR) /* Gotta be WinCE */ - } - } - Return(OSVR) - } - - Method(_PIC, 0x01, NotSerialized) - { - If (Arg0) - { - \_SB.CIRQ() - } - Store(Arg0, PMOD) - } - Method(CIRQ, 0x00, NotSerialized){ - Store(0, PINA) - Store(0, PINB) - Store(0, PINC) - Store(0, PIND) - Store(0, PINE) - Store(0, PINF) - Store(0, PING) - Store(0, PINH) - } - - Name(IRQB, ResourceTemplate(){ - IRQ(Level,ActiveLow,Shared){15} - }) - - Name(IRQP, ResourceTemplate(){ - IRQ(Level,ActiveLow,Exclusive){3, 4, 5, 7, 10, 11, 12, 15} - }) - - Name(PITF, ResourceTemplate(){ - IRQ(Level,ActiveLow,Exclusive){9} - }) - - Device(INTA) { - Name(_HID, EISAID("PNP0C0F")) - Name(_UID, 1) - - Method(_STA, 0) { - if (PINA) { - Return(0x0B) /* sata is invisible */ - } else { - Return(0x09) /* sata is disabled */ - } - } /* End Method(_SB.INTA._STA) */ - - Method(_DIS ,0) { - /* DBGO("\\_SB\\LNKA\\_DIS\n") */ - Store(0, PINA) - } /* End Method(_SB.INTA._DIS) */ - - Method(_PRS ,0) { - /* DBGO("\\_SB\\LNKA\\_PRS\n") */ - Return(IRQP) - } /* Method(_SB.INTA._PRS) */ - - Method(_CRS ,0) { - /* DBGO("\\_SB\\LNKA\\_CRS\n") */ - CreateWordField(IRQB, 0x1, IRQN) - ShiftLeft(1, PINA, IRQN) - Return(IRQB) - } /* Method(_SB.INTA._CRS) */ - - Method(_SRS, 1) { - /* DBGO("\\_SB\\LNKA\\_CRS\n") */ - CreateWordField(ARG0, 1, IRQM) - - /* Use lowest available IRQ */ - FindSetRightBit(IRQM, Local0) - if (Local0) { - Decrement(Local0) - } - Store(Local0, PINA) - } /* End Method(_SB.INTA._SRS) */ - } /* End Device(INTA) */ - - Device(INTB) { - Name(_HID, EISAID("PNP0C0F")) - Name(_UID, 2) - - Method(_STA, 0) { - if (PINB) { - Return(0x0B) /* sata is invisible */ - } else { - Return(0x09) /* sata is disabled */ - } - } /* End Method(_SB.INTB._STA) */ - - Method(_DIS ,0) { - /* DBGO("\\_SB\\LNKB\\_DIS\n") */ - Store(0, PINB) - } /* End Method(_SB.INTB._DIS) */ - - Method(_PRS ,0) { - /* DBGO("\\_SB\\LNKB\\_PRS\n") */ - Return(IRQP) - } /* Method(_SB.INTB._PRS) */ - - Method(_CRS ,0) { - /* DBGO("\\_SB\\LNKB\\_CRS\n") */ - CreateWordField(IRQB, 0x1, IRQN) - ShiftLeft(1, PINB, IRQN) - Return(IRQB) - } /* Method(_SB.INTB._CRS) */ - - Method(_SRS, 1) { - /* DBGO("\\_SB\\LNKB\\_CRS\n") */ - CreateWordField(ARG0, 1, IRQM) - - /* Use lowest available IRQ */ - FindSetRightBit(IRQM, Local0) - if (Local0) { - Decrement(Local0) - } - Store(Local0, PINB) - } /* End Method(_SB.INTB._SRS) */ - } /* End Device(INTB) */ - - Device(INTC) { - Name(_HID, EISAID("PNP0C0F")) - Name(_UID, 3) - - Method(_STA, 0) { - if (PINC) { - Return(0x0B) /* sata is invisible */ - } else { - Return(0x09) /* sata is disabled */ - } - } /* End Method(_SB.INTC._STA) */ - - Method(_DIS ,0) { - /* DBGO("\\_SB\\LNKC\\_DIS\n") */ - Store(0, PINC) - } /* End Method(_SB.INTC._DIS) */ - - Method(_PRS ,0) { - /* DBGO("\\_SB\\LNKC\\_PRS\n") */ - Return(IRQP) - } /* Method(_SB.INTC._PRS) */ - - Method(_CRS ,0) { - /* DBGO("\\_SB\\LNKC\\_CRS\n") */ - CreateWordField(IRQB, 0x1, IRQN) - ShiftLeft(1, PINC, IRQN) - Return(IRQB) - } /* Method(_SB.INTC._CRS) */ - - Method(_SRS, 1) { - /* DBGO("\\_SB\\LNKC\\_CRS\n") */ - CreateWordField(ARG0, 1, IRQM) - - /* Use lowest available IRQ */ - FindSetRightBit(IRQM, Local0) - if (Local0) { - Decrement(Local0) - } - Store(Local0, PINC) - } /* End Method(_SB.INTC._SRS) */ - } /* End Device(INTC) */ - - Device(INTD) { - Name(_HID, EISAID("PNP0C0F")) - Name(_UID, 4) - - Method(_STA, 0) { - if (PIND) { - Return(0x0B) /* sata is invisible */ - } else { - Return(0x09) /* sata is disabled */ - } - } /* End Method(_SB.INTD._STA) */ - - Method(_DIS ,0) { - /* DBGO("\\_SB\\LNKD\\_DIS\n") */ - Store(0, PIND) - } /* End Method(_SB.INTD._DIS) */ - - Method(_PRS ,0) { - /* DBGO("\\_SB\\LNKD\\_PRS\n") */ - Return(IRQP) - } /* Method(_SB.INTD._PRS) */ - - Method(_CRS ,0) { - /* DBGO("\\_SB\\LNKD\\_CRS\n") */ - CreateWordField(IRQB, 0x1, IRQN) - ShiftLeft(1, PIND, IRQN) - Return(IRQB) - } /* Method(_SB.INTD._CRS) */ - - Method(_SRS, 1) { - /* DBGO("\\_SB\\LNKD\\_CRS\n") */ - CreateWordField(ARG0, 1, IRQM) - - /* Use lowest available IRQ */ - FindSetRightBit(IRQM, Local0) - if (Local0) { - Decrement(Local0) - } - Store(Local0, PIND) - } /* End Method(_SB.INTD._SRS) */ - } /* End Device(INTD) */ - - Device(INTE) { - Name(_HID, EISAID("PNP0C0F")) - Name(_UID, 5) - - Method(_STA, 0) { - if (PINE) { - Return(0x0B) /* sata is invisible */ - } else { - Return(0x09) /* sata is disabled */ - } - } /* End Method(_SB.INTE._STA) */ - - Method(_DIS ,0) { - /* DBGO("\\_SB\\LNKE\\_DIS\n") */ - Store(0, PINE) - } /* End Method(_SB.INTE._DIS) */ - - Method(_PRS ,0) { - /* DBGO("\\_SB\\LNKE\\_PRS\n") */ - Return(IRQP) - } /* Method(_SB.INTE._PRS) */ - - Method(_CRS ,0) { - /* DBGO("\\_SB\\LNKE\\_CRS\n") */ - CreateWordField(IRQB, 0x1, IRQN) - ShiftLeft(1, PINE, IRQN) - Return(IRQB) - } /* Method(_SB.INTE._CRS) */ - - Method(_SRS, 1) { - /* DBGO("\\_SB\\LNKE\\_CRS\n") */ - CreateWordField(ARG0, 1, IRQM) - - /* Use lowest available IRQ */ - FindSetRightBit(IRQM, Local0) - if (Local0) { - Decrement(Local0) - } - Store(Local0, PINE) - } /* End Method(_SB.INTE._SRS) */ - } /* End Device(INTE) */ - - Device(INTF) { - Name(_HID, EISAID("PNP0C0F")) - Name(_UID, 6) - - Method(_STA, 0) { - if (PINF) { - Return(0x0B) /* sata is invisible */ - } else { - Return(0x09) /* sata is disabled */ - } - } /* End Method(_SB.INTF._STA) */ - - Method(_DIS ,0) { - /* DBGO("\\_SB\\LNKF\\_DIS\n") */ - Store(0, PINF) - } /* End Method(_SB.INTF._DIS) */ - - Method(_PRS ,0) { - /* DBGO("\\_SB\\LNKF\\_PRS\n") */ - Return(PITF) - } /* Method(_SB.INTF._PRS) */ - - Method(_CRS ,0) { - /* DBGO("\\_SB\\LNKF\\_CRS\n") */ - CreateWordField(IRQB, 0x1, IRQN) - ShiftLeft(1, PINF, IRQN) - Return(IRQB) - } /* Method(_SB.INTF._CRS) */ - - Method(_SRS, 1) { - /* DBGO("\\_SB\\LNKF\\_CRS\n") */ - CreateWordField(ARG0, 1, IRQM) - - /* Use lowest available IRQ */ - FindSetRightBit(IRQM, Local0) - if (Local0) { - Decrement(Local0) - } - Store(Local0, PINF) - } /* End Method(_SB.INTF._SRS) */ - } /* End Device(INTF) */ - - Device(INTG) { - Name(_HID, EISAID("PNP0C0F")) - Name(_UID, 7) - - Method(_STA, 0) { - if (PING) { - Return(0x0B) /* sata is invisible */ - } else { - Return(0x09) /* sata is disabled */ - } - } /* End Method(_SB.INTG._STA) */ - - Method(_DIS ,0) { - /* DBGO("\\_SB\\LNKG\\_DIS\n") */ - Store(0, PING) - } /* End Method(_SB.INTG._DIS) */ - - Method(_PRS ,0) { - /* DBGO("\\_SB\\LNKG\\_PRS\n") */ - Return(IRQP) - } /* Method(_SB.INTG._CRS) */ - - Method(_CRS ,0) { - /* DBGO("\\_SB\\LNKG\\_CRS\n") */ - CreateWordField(IRQB, 0x1, IRQN) - ShiftLeft(1, PING, IRQN) - Return(IRQB) - } /* Method(_SB.INTG._CRS) */ - - Method(_SRS, 1) { - /* DBGO("\\_SB\\LNKG\\_CRS\n") */ - CreateWordField(ARG0, 1, IRQM) - - /* Use lowest available IRQ */ - FindSetRightBit(IRQM, Local0) - if (Local0) { - Decrement(Local0) - } - Store(Local0, PING) - } /* End Method(_SB.INTG._SRS) */ - } /* End Device(INTG) */ - - Device(INTH) { - Name(_HID, EISAID("PNP0C0F")) - Name(_UID, 8) - - Method(_STA, 0) { - if (PINH) { - Return(0x0B) /* sata is invisible */ - } else { - Return(0x09) /* sata is disabled */ - } - } /* End Method(_SB.INTH._STA) */ - - Method(_DIS ,0) { - /* DBGO("\\_SB\\LNKH\\_DIS\n") */ - Store(0, PINH) - } /* End Method(_SB.INTH._DIS) */ - - Method(_PRS ,0) { - /* DBGO("\\_SB\\LNKH\\_PRS\n") */ - Return(IRQP) - } /* Method(_SB.INTH._CRS) */ - - Method(_CRS ,0) { - /* DBGO("\\_SB\\LNKH\\_CRS\n") */ - CreateWordField(IRQB, 0x1, IRQN) - ShiftLeft(1, PINH, IRQN) - Return(IRQB) - } /* Method(_SB.INTH._CRS) */ - - Method(_SRS, 1) { - /* DBGO("\\_SB\\LNKH\\_CRS\n") */ - CreateWordField(ARG0, 1, IRQM) - - /* Use lowest available IRQ */ - FindSetRightBit(IRQM, Local0) - if (Local0) { - Decrement(Local0) - } - Store(Local0, PINH) - } /* End Method(_SB.INTH._SRS) */ - } /* End Device(INTH) */ - - } /* End Scope(_SB) */ - - #include - - /* Wake status package */ - Name(WKST,Package(){Zero, Zero}) - - /* - * \_PTS - Prepare to Sleep method - * - * Entry: - * Arg0=The value of the sleeping state S1=1, S2=2, etc - * - * Exit: - * -none- - * - * The _PTS control method is executed at the beginning of the sleep process - * for S1-S5. The sleeping value is passed to the _PTS control method. This - * control method may be executed a relatively long time before entering the - * sleep state and the OS may abort the operation without notification to - * the ACPI driver. This method cannot modify the configuration or power - * state of any device in the system. - */ - Method(\_PTS, 1) { - /* DBGO("\\_PTS\n") */ - /* DBGO("From S0 to S") */ - /* DBGO(Arg0) */ - /* DBGO("\n") */ - - /* Don't allow PCIRST# to reset USB */ - if (LEqual(Arg0,3)){ - Store(0,URRE) - } - - /* Clear sleep SMI status flag and enable sleep SMI trap. */ - /*Store(One, CSSM) - Store(One, SSEN)*/ - - /* On older chips, clear PciExpWakeDisEn */ - /*if (LLessEqual(\_SB.SBRI, 0x13)) { - * Store(0,\_SB.PWDE) - *} - */ - - /* Clear wake status structure. */ - Store(0, Index(WKST,0)) - Store(0, Index(WKST,1)) - \_SB.PCI0.SIOS (Arg0) - } /* End Method(\_PTS) */ - - /* - * The following method results in a "not a valid reserved NameSeg" - * warning so I have commented it out for the duration. It isn't - * used, so it could be removed. - * - * - * \_GTS OEM Going To Sleep method - * - * Entry: - * Arg0=The value of the sleeping state S1=1, S2=2 - * - * Exit: - * -none- - * - * Method(\_GTS, 1) { - * DBGO("\\_GTS\n") - * DBGO("From S0 to S") - * DBGO(Arg0) - * DBGO("\n") - * } - */ - - /* - * \_BFS OEM Back From Sleep method - * - * Entry: - * Arg0=The value of the sleeping state S1=1, S2=2 - * - * Exit: - * -none- - */ - Method(\_BFS, 1) { - /* DBGO("\\_BFS\n") */ - /* DBGO("From S") */ - /* DBGO(Arg0) */ - /* DBGO(" to S0\n") */ - } - - /* - * \_WAK System Wake method - * - * Entry: - * Arg0=The value of the sleeping state S1=1, S2=2 - * - * Exit: - * Return package of 2 DWords - * Dword 1 - Status - * 0x00000000 wake succeeded - * 0x00000001 Wake was signaled but failed due to lack of power - * 0x00000002 Wake was signaled but failed due to thermal condition - * Dword 2 - Power Supply state - * if non-zero the effective S-state the power supply entered - */ - Method(\_WAK, 1) { - /* DBGO("\\_WAK\n") */ - /* DBGO("From S") */ - /* DBGO(Arg0) */ - /* DBGO(" to S0\n") */ - - /* Re-enable HPET */ - Store(1,HPDE) - - /* Restore PCIRST# so it resets USB */ - if (LEqual(Arg0,3)){ - Store(1,URRE) - } - - /* Arbitrarily clear PciExpWakeStatus */ - Store(PWST, Local1) - Store(Local1, PWST) - - /* if (DeRefOf(Index(WKST,0))) { - * Store(0, Index(WKST,1)) - * } else { - * Store(Arg0, Index(WKST,1)) - * } - */ - \_SB.PCI0.SIOW () - Return(WKST) - } /* End Method(\_WAK) */ - - Scope(\_GPE) { /* Start Scope GPE */ - /* General event 0 */ - /* Method(_L00) { - * DBGO("\\_GPE\\_L00\n") - * } - */ - - /* General event 1 */ - /* Method(_L01) { - * DBGO("\\_GPE\\_L00\n") - * } - */ - - /* General event 2 */ - /* Method(_L02) { - * DBGO("\\_GPE\\_L00\n") - * } - */ - - /* General event 3 */ - Method(_L03) { - /* DBGO("\\_GPE\\_L00\n") */ - Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ - } - - /* General event 4 */ - /* Method(_L04) { - * DBGO("\\_GPE\\_L00\n") - * } - */ - - /* General event 5 */ - /* Method(_L05) { - * DBGO("\\_GPE\\_L00\n") - * } - */ - - /* General event 6 - Used for GPM6, moved to USB.asl */ - /* Method(_L06) { - * DBGO("\\_GPE\\_L00\n") - * } - */ - - /* General event 7 - Used for GPM7, moved to USB.asl */ - /* Method(_L07) { - * DBGO("\\_GPE\\_L07\n") - * } - */ - - /* Legacy PM event */ - Method(_L08) { - /* DBGO("\\_GPE\\_L08\n") */ - } - - /* Temp warning (TWarn) event */ - Method(_L09) { - /* DBGO("\\_GPE\\_L09\n") */ - Notify (\_TZ.TZ00, 0x80) - } - - /* Reserved */ - /* Method(_L0A) { - * DBGO("\\_GPE\\_L0A\n") - * } - */ - - /* USB controller PME# */ - Method(_L0B) { - /* DBGO("\\_GPE\\_L0B\n") */ - Notify(\_SB.PCI0.UOH1, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(\_SB.PCI0.UOH2, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(\_SB.PCI0.UOH3, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(\_SB.PCI0.UOH4, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(\_SB.PCI0.UOH5, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(\_SB.PCI0.UEH1, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ - } - - /* AC97 controller PME# */ - /* Method(_L0C) { - * DBGO("\\_GPE\\_L0C\n") - * } - */ - - /* OtherTherm PME# */ - /* Method(_L0D) { - * DBGO("\\_GPE\\_L0D\n") - * } - */ - - /* GPM9 SCI event - Moved to USB.asl */ - /* Method(_L0E) { - * DBGO("\\_GPE\\_L0E\n") - * } - */ - - /* PCIe HotPlug event */ - /* Method(_L0F) { - * DBGO("\\_GPE\\_L0F\n") - * } - */ - - /* ExtEvent0 SCI event */ - Method(_L10) { - /* DBGO("\\_GPE\\_L10\n") */ - } - - - /* ExtEvent1 SCI event */ - Method(_L11) { - /* DBGO("\\_GPE\\_L11\n") */ - } - - /* PCIe PME# event */ - /* Method(_L12) { - * DBGO("\\_GPE\\_L12\n") - * } - */ - - /* GPM0 SCI event - Moved to USB.asl */ - /* Method(_L13) { - * DBGO("\\_GPE\\_L13\n") - * } - */ - - /* GPM1 SCI event - Moved to USB.asl */ - /* Method(_L14) { - * DBGO("\\_GPE\\_L14\n") - * } - */ - - /* GPM2 SCI event - Moved to USB.asl */ - /* Method(_L15) { - * DBGO("\\_GPE\\_L15\n") - * } - */ - - /* GPM3 SCI event - Moved to USB.asl */ - /* Method(_L16) { - * DBGO("\\_GPE\\_L16\n") - * } - */ - - /* GPM8 SCI event - Moved to USB.asl */ - /* Method(_L17) { - * DBGO("\\_GPE\\_L17\n") - * } - */ - - /* GPIO0 or GEvent8 event */ - Method(_L18) { - /* DBGO("\\_GPE\\_L18\n") */ - Notify(\_SB.PCI0.PBR2, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(\_SB.PCI0.PBR4, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(\_SB.PCI0.PBR5, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(\_SB.PCI0.PBR6, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(\_SB.PCI0.PBR7, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ - } - - /* GPM4 SCI event - Moved to USB.asl */ - /* Method(_L19) { - * DBGO("\\_GPE\\_L19\n") - * } - */ - - /* GPM5 SCI event - Moved to USB.asl */ - /* Method(_L1A) { - * DBGO("\\_GPE\\_L1A\n") - * } - */ - - /* Azalia SCI event */ - Method(_L1B) { - /* DBGO("\\_GPE\\_L1B\n") */ - Notify(\_SB.PCI0.AZHD, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ - } - - /* GPM6 SCI event - Reassigned to _L06 */ - /* Method(_L1C) { - * DBGO("\\_GPE\\_L1C\n") - * } - */ - - /* GPM7 SCI event - Reassigned to _L07 */ - /* Method(_L1D) { - * DBGO("\\_GPE\\_L1D\n") - * } - */ - - /* GPIO2 or GPIO66 SCI event */ - /* Method(_L1E) { - * DBGO("\\_GPE\\_L1E\n") - * } - */ - - /* SATA SCI event - Moved to sata.asl */ - /* Method(_L1F) { - * DBGO("\\_GPE\\_L1F\n") - * } - */ - - } /* End Scope GPE */ - - #include "acpi/usb.asl" - - /* System Bus */ - Scope(\_SB) { /* Start \_SB scope */ - #include /* global utility methods expected within the \_SB scope */ - - /* _SB.PCI0 */ - /* Note: Only need HID on Primary Bus */ - Device(PCI0) { - External (TOM1) - External (TOM2) /* ( >> 20) to make it fit into 32 bit for XP */ - Name(_HID, EISAID("PNP0A03")) - Name(_ADR, 0x00180000) /* Dev# = BSP Dev#, Func# = 0 */ - Method(_BBN, 0) { /* Bus number = 0 */ - Return(0) - } - Method(_STA, 0) { - /* DBGO("\\_SB\\PCI0\\_STA\n") */ - Return(0x0B) /* Status is visible */ - } - - Method(_PRT,0) { - If(PMOD){ Return(APR0) } /* APIC mode */ - Return (PR0) /* PIC Mode */ - } /* end _PRT */ - - /* Describe the Northbridge devices */ - Device(AMRT) { - Name(_ADR, 0x00000000) - } /* end AMRT */ - - /* The internal GFX bridge */ - Device(AGPB) { - Name(_ADR, 0x00010000) - Name(_PRW, Package() {0x18, 4}) - Method(_PRT,0) { - Return (APR1) - } - } /* end AGPB */ - - /* The external GFX bridge */ - Device(PBR2) { - Name(_ADR, 0x00020000) - Name(_PRW, Package() {0x18, 4}) - Method(_PRT,0) { - If(PMOD){ Return(APS2) } /* APIC mode */ - Return (PS2) /* PIC Mode */ - } /* end _PRT */ - } /* end PBR2 */ - - /* Dev3 is also an external GFX bridge, not used in Herring */ - - Device(PBR4) { - Name(_ADR, 0x00040000) - Name(_PRW, Package() {0x18, 4}) - Method(_PRT,0) { - If(PMOD){ Return(APS4) } /* APIC mode */ - Return (PS4) /* PIC Mode */ - } /* end _PRT */ - } /* end PBR4 */ - - Device(PBR5) { - Name(_ADR, 0x00050000) - Name(_PRW, Package() {0x18, 4}) - Method(_PRT,0) { - If(PMOD){ Return(APS5) } /* APIC mode */ - Return (PS5) /* PIC Mode */ - } /* end _PRT */ - } /* end PBR5 */ - - Device(PBR6) { - Name(_ADR, 0x00060000) - Name(_PRW, Package() {0x18, 4}) - Method(_PRT,0) { - If(PMOD){ Return(APS6) } /* APIC mode */ - Return (PS6) /* PIC Mode */ - } /* end _PRT */ - } /* end PBR6 */ - - /* The onboard EtherNet chip */ - Device(PBR7) { - Name(_ADR, 0x00070000) - Name(_PRW, Package() {0x18, 4}) - Method(_PRT,0) { - If(PMOD){ Return(APS7) } /* APIC mode */ - Return (PS7) /* PIC Mode */ - } /* end _PRT */ - } /* end PBR7 */ - - /* GPP */ - Device(PBR9) { - Name(_ADR, 0x00090000) - Name(_PRW, Package() {0x18, 4}) - Method(_PRT,0) { - If(PMOD){ Return(APS9) } /* APIC mode */ - Return (PS9) /* PIC Mode */ - } /* end _PRT */ - } /* end PBR9 */ - - Device(PBRa) { - Name(_ADR, 0x000A0000) - Name(_PRW, Package() {0x18, 4}) - Method(_PRT,0) { - If(PMOD){ Return(APSa) } /* APIC mode */ - Return (PSa) /* PIC Mode */ - } /* end _PRT */ - } /* end PBRa */ - - - /* PCI slot 1, 2, 3 */ - Device(PIBR) { - Name(_ADR, 0x00140004) - Name(_PRW, Package() {0x18, 4}) - - Method(_PRT, 0) { - Return (PCIB) - } - } - - /* Describe the Southbridge devices */ - Device(STCR) { - Name(_ADR, 0x00110000) - #include "acpi/sata.asl" - } /* end STCR */ - - Device(UOH1) { - Name(_ADR, 0x00130000) - Name(_PRW, Package() {0x0B, 3}) - } /* end UOH1 */ - - Device(UOH2) { - Name(_ADR, 0x00130001) - Name(_PRW, Package() {0x0B, 3}) - } /* end UOH2 */ - - Device(UOH3) { - Name(_ADR, 0x00130002) - Name(_PRW, Package() {0x0B, 3}) - } /* end UOH3 */ - - Device(UOH4) { - Name(_ADR, 0x00130003) - Name(_PRW, Package() {0x0B, 3}) - } /* end UOH4 */ - - Device(UOH5) { - Name(_ADR, 0x00130004) - Name(_PRW, Package() {0x0B, 3}) - } /* end UOH5 */ - - Device(UEH1) { - Name(_ADR, 0x00130005) - Name(_PRW, Package() {0x0B, 3}) - } /* end UEH1 */ - - Device(SBUS) { - Name(_ADR, 0x00140000) - } /* end SBUS */ - - /* Primary (and only) IDE channel */ - Device(IDEC) { - Name(_ADR, 0x00140001) - #include "acpi/ide.asl" - } /* end IDEC */ - - Device(AZHD) { - Name(_ADR, 0x00140002) - OperationRegion(AZPD, PCI_Config, 0x00, 0x100) - Field(AZPD, AnyAcc, NoLock, Preserve) { - offset (0x42), - NSDI, 1, - NSDO, 1, - NSEN, 1, - offset (0x44), - IPCR, 4, - offset (0x54), - PWST, 2, - , 6, - PMEB, 1, - , 6, - PMST, 1, - offset (0x62), - MMCR, 1, - offset (0x64), - MMLA, 32, - offset (0x68), - MMHA, 32, - offset (0x6C), - MMDT, 16, - } - - Method(_INI) { - If(LEqual(OSVR,3)){ /* If we are running Linux */ - Store(zero, NSEN) - Store(one, NSDO) - Store(one, NSDI) - } - } - } /* end AZHD */ - - Device(LIBR) { - Name(_ADR, 0x00140003) - /* Method(_INI) { - * DBGO("\\_SB\\PCI0\\LpcIsaBr\\_INI\n") - } */ /* End Method(_SB.SBRDG._INI) */ - - /* Real Time Clock Device */ - Device(RTC0) { - Name(_HID, EISAID("PNP0B00")) /* AT Real Time Clock (not PIIX4 compatible) */ - Name(_CRS, ResourceTemplate() { - IRQNoFlags(){8} - IO(Decode16,0x0070, 0x0070, 0, 2) - /* IO(Decode16,0x0070, 0x0070, 0, 4) */ - }) - } /* End Device(_SB.PCI0.LpcIsaBr.RTC0) */ - - Device(TMR) { /* Timer */ - Name(_HID,EISAID("PNP0100")) /* System Timer */ - Name(_CRS, ResourceTemplate() { - IRQNoFlags(){0} - IO(Decode16, 0x0040, 0x0040, 0, 4) - /* IO(Decode16, 0x0048, 0x0048, 0, 4) */ - }) - } /* End Device(_SB.PCI0.LpcIsaBr.TMR) */ - - Device(SPKR) { /* Speaker */ - Name(_HID,EISAID("PNP0800")) /* AT style speaker */ - Name(_CRS, ResourceTemplate() { - IO(Decode16, 0x0061, 0x0061, 0, 1) - }) - } /* End Device(_SB.PCI0.LpcIsaBr.SPKR) */ - - Device(PIC) { - Name(_HID,EISAID("PNP0000")) /* AT Interrupt Controller */ - Name(_CRS, ResourceTemplate() { - IRQNoFlags(){2} - IO(Decode16,0x0020, 0x0020, 0, 2) - IO(Decode16,0x00A0, 0x00A0, 0, 2) - /* IO(Decode16, 0x00D0, 0x00D0, 0x10, 0x02) */ - /* IO(Decode16, 0x04D0, 0x04D0, 0x10, 0x02) */ - }) - } /* End Device(_SB.PCI0.LpcIsaBr.PIC) */ - - Device(MAD) { /* 8257 DMA */ - Name(_HID,EISAID("PNP0200")) /* Hardware Device ID */ - Name(_CRS, ResourceTemplate() { - DMA(Compatibility,BusMaster,Transfer8){4} - IO(Decode16, 0x0000, 0x0000, 0x10, 0x10) - IO(Decode16, 0x0081, 0x0081, 0x01, 0x03) - IO(Decode16, 0x0087, 0x0087, 0x01, 0x01) - IO(Decode16, 0x0089, 0x0089, 0x01, 0x03) - IO(Decode16, 0x008F, 0x008F, 0x01, 0x01) - IO(Decode16, 0x00C0, 0x00C0, 0x10, 0x20) - }) /* End Name(_SB.PCI0.LpcIsaBr.MAD._CRS) */ - } /* End Device(_SB.PCI0.LpcIsaBr.MAD) */ - - Device(COPR) { - Name(_HID,EISAID("PNP0C04")) /* Math Coprocessor */ - Name(_CRS, ResourceTemplate() { - IO(Decode16, 0x00F0, 0x00F0, 0, 0x10) - IRQNoFlags(){13} - }) - } /* End Device(_SB.PCI0.LpcIsaBr.COPR) */ - } /* end LIBR */ - - Device(HPBR) { - Name(_ADR, 0x00140004) - } /* end HostPciBr */ - - Device(ACAD) { - Name(_ADR, 0x00140005) - } /* end Ac97audio */ - - Device(ACMD) { - Name(_ADR, 0x00140006) - } /* end Ac97modem */ - - /* ITE8718 Support */ - OperationRegion (IOID, SystemIO, 0x2E, 0x02) /* sometimes it is 0x4E */ - Field (IOID, ByteAcc, NoLock, Preserve) - { - SIOI, 8, SIOD, 8 /* 0x2E and 0x2F */ - } - - IndexField (SIOI, SIOD, ByteAcc, NoLock, Preserve) - { - Offset (0x07), - LDN, 8, /* Logical Device Number */ - Offset (0x20), - CID1, 8, /* Chip ID Byte 1, 0x87 */ - CID2, 8, /* Chip ID Byte 2, 0x12 */ - Offset (0x30), - ACTR, 8, /* Function activate */ - Offset (0xF0), - APC0, 8, /* APC/PME Event Enable Register */ - APC1, 8, /* APC/PME Status Register */ - APC2, 8, /* APC/PME Control Register 1 */ - APC3, 8, /* Environment Controller Special Configuration Register */ - APC4, 8 /* APC/PME Control Register 2 */ - } - - /* Enter the 8718 MB PnP Mode */ - Method (EPNP) - { - Store(0x87, SIOI) - Store(0x01, SIOI) - Store(0x55, SIOI) - Store(0x55, SIOI) /* 8718 magic number */ - } - /* Exit the 8718 MB PnP Mode */ - Method (XPNP) - { - Store (0x02, SIOI) - Store (0x02, SIOD) - } - /* - * Keyboard PME is routed to SB700 Gevent3. We can wake - * up the system by pressing the key. - */ - Method (SIOS, 1) - { - /* We only enable KBD PME for S5. */ - If (LLess (Arg0, 0x05)) - { - EPNP() - /* DBGO("8718F\n") */ - - Store (0x4, LDN) - Store (One, ACTR) /* Enable EC */ - /* - Store (0x4, LDN) - Store (0x04, APC4) - */ /* falling edge. which mode? Not sure. */ - - Store (0x4, LDN) - Store (0x08, APC1) /* clear PME status, Use 0x18 for mouse & KBD */ - Store (0x4, LDN) - Store (0x08, APC0) /* enable PME, Use 0x18 for mouse & KBD */ - - XPNP() - } - } - Method (SIOW, 0) - { - EPNP() - Store (0x4, LDN) - Store (Zero, APC0) /* disable keyboard PME */ - Store (0x4, LDN) - Store (0xFF, APC1) /* clear keyboard PME status */ - XPNP() - } - - Name(CRES, ResourceTemplate() { - IO(Decode16, 0x0CF8, 0x0CF8, 1, 8) - - WORDIO(ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, - 0x0000, /* address granularity */ - 0x0000, /* range minimum */ - 0x0CF7, /* range maximum */ - 0x0000, /* translation */ - 0x0CF8 /* length */ - ) - - WORDIO(ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, - 0x0000, /* address granularity */ - 0x0D00, /* range minimum */ - 0xFFFF, /* range maximum */ - 0x0000, /* translation */ - 0xF300 /* length */ - ) - - Memory32Fixed(READWRITE, 0, 0xA0000, BSMM) - Memory32Fixed(READONLY, 0x000A0000, 0x00020000, VGAM) /* VGA memory space */ - /* memory space for PCI BARs below 4GB */ - Memory32Fixed(ReadOnly, 0x00000000, 0x00000000, MMIO) - }) /* End Name(_SB.PCI0.CRES) */ - - Method(_CRS, 0) { - /* DBGO("\\_SB\\PCI0\\_CRS\n") */ - CreateDWordField(CRES, ^MMIO._BAS, MM1B) - CreateDWordField(CRES, ^MMIO._LEN, MM1L) - /* - * Declare memory between TOM1 and 4GB as available - * for PCI MMIO. - * Use ShiftLeft to avoid 64bit constant (for XP). - * This will work even if the OS does 32bit arithmetic, as - * 32bit (0x00000000 - TOM1) will wrap and give the same - * result as 64bit (0x100000000 - TOM1). - */ - Store(TOM1, MM1B) - ShiftLeft(0x10000000, 4, Local0) - Subtract(Local0, TOM1, Local0) - Store(Local0, MM1L) - - Return(CRES) /* note to change the Name buffer */ - } /* end of Method(_SB.PCI0._CRS) */ - - /* - * - * FIRST METHOD CALLED UPON BOOT - * - * 1. If debugging, print current OS and ACPI interpreter. - * 2. Get PCI Interrupt routing from ACPI VSM, this - * value is based on user choice in BIOS setup. - */ - Method(_INI, 0) { - /* DBGO("\\_SB\\_INI\n") */ - /* DBGO(" DSDT.ASL code from ") */ - /* DBGO(__DATE__) */ - /* DBGO(" ") */ - /* DBGO(__TIME__) */ - /* DBGO("\n Sleep states supported: ") */ - /* DBGO("\n") */ - /* DBGO(" \\_OS=") */ - /* DBGO(\_OS) */ - /* DBGO("\n \\_REV=") */ - /* DBGO(\_REV) */ - /* DBGO("\n") */ - - /* Determine the OS we're running on */ - OSFL() - - /* On older chips, clear PciExpWakeDisEn */ - /*if (LLessEqual(\SBRI, 0x13)) { - * Store(0,\PWDE) - * } - */ - } /* End Method(_SB._INI) */ - } /* End Device(PCI0) */ - - Device(PWRB) { /* Start Power button device */ - Name(_HID, EISAID("PNP0C0C")) - Name(_UID, 0xAA) - Name(_PRW, Package () {3, 0x04}) /* wake from S1-S4 */ - Name(_STA, 0x0B) /* sata is invisible */ - } - } /* End \_SB scope */ - - Scope(\_SI) { - Method(_SST, 1) { - /* DBGO("\\_SI\\_SST\n") */ - /* DBGO(" New Indicator state: ") */ - /* DBGO(Arg0) */ - /* DBGO("\n") */ - } - } /* End Scope SI */ - - #include - - /* THERMAL */ - Scope(\_TZ) { - Name (KELV, 2732) - Name (THOT, 800) - Name (TCRT, 850) - - ThermalZone(TZ00) { - Method(_AC0,0) { /* Active Cooling 0 (0=highest fan speed) */ - /* DBGO("\\_TZ\\TZ00\\_AC0\n") */ - Return(Add(0, 2730)) - } - Method(_AL0,0) { /* Returns package of cooling device to turn on */ - /* DBGO("\\_TZ\\TZ00\\_AL0\n") */ - Return(Package() {\_TZ.TZ00.FAN0}) - } - Device (FAN0) { - Name(_HID, EISAID("PNP0C0B")) - Name(_PR0, Package() {PFN0}) - } - - PowerResource(PFN0,0,0) { - Method(_STA) { - Store(0xF,Local0) - Return(Local0) - } - Method(_ON) { - /* DBGO("\\_TZ\\TZ00\\FAN0 _ON\n") */ - } - Method(_OFF) { - /* DBGO("\\_TZ\\TZ00\\FAN0 _OFF\n") */ - } - } - - Method(_HOT,0) { /* return hot temp in tenths degree Kelvin */ - /* DBGO("\\_TZ\\TZ00\\_HOT\n") */ - Return (Add (THOT, KELV)) - } - Method(_CRT,0) { /* return critical temp in tenths degree Kelvin */ - /* DBGO("\\_TZ\\TZ00\\_CRT\n") */ - Return (Add (TCRT, KELV)) - } - Method(_TMP,0) { /* return current temp of this zone */ - Store (SMBR (0x07, 0x4C,, 0x00), Local0) - If (LGreater (Local0, 0x10)) { - Store (Local0, Local1) - } - Else { - Add (Local0, THOT, Local0) - Return (Add (400, KELV)) - } - - Store (SMBR (0x07, 0x4C, 0x01), Local0) - /* only the two MSBs in the external temperature low byte are used, resolution 0.25. We ignore it */ - /* Store (SMBR (0x07, 0x4C, 0x10), Local2) */ - If (LGreater (Local0, 0x10)) { - If (LGreater (Local0, Local1)) { - Store (Local0, Local1) - } - - Multiply (Local1, 10, Local1) - Return (Add (Local1, KELV)) - } - Else { - Add (Local0, THOT, Local0) - Return (Add (400 , KELV)) - } - } /* end of _TMP */ - } /* end of TZ00 */ - } -} -/* End of ASL file */ diff --git a/src/mainboard/asus/m4a785t-m/get_bus_conf.c b/src/mainboard/asus/m4a785t-m/get_bus_conf.c deleted file mode 100644 index 7f7cc47e37..0000000000 --- a/src/mainboard/asus/m4a785t-m/get_bus_conf.c +++ /dev/null @@ -1,17 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 Denis 'GNUtoo' Carikli - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include "../m4a785-m/get_bus_conf.c" diff --git a/src/mainboard/asus/m4a785t-m/irq_tables.c b/src/mainboard/asus/m4a785t-m/irq_tables.c deleted file mode 100644 index ea09fc31f5..0000000000 --- a/src/mainboard/asus/m4a785t-m/irq_tables.c +++ /dev/null @@ -1,17 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 Denis 'GNUtoo' Carikli - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include "../m4a785-m/irq_tables.c" diff --git a/src/mainboard/asus/m4a785t-m/mainboard.c b/src/mainboard/asus/m4a785t-m/mainboard.c deleted file mode 100644 index 1d4e73c019..0000000000 --- a/src/mainboard/asus/m4a785t-m/mainboard.c +++ /dev/null @@ -1,17 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 Denis 'GNUtoo' Carikli - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include "../m4a785-m/mainboard.c" diff --git a/src/mainboard/asus/m4a785t-m/mptable.c b/src/mainboard/asus/m4a785t-m/mptable.c deleted file mode 100644 index 065db96725..0000000000 --- a/src/mainboard/asus/m4a785t-m/mptable.c +++ /dev/null @@ -1,17 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 Denis 'GNUtoo' Carikli - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include "../m4a785-m/mptable.c" diff --git a/src/mainboard/asus/m4a785t-m/romstage.c b/src/mainboard/asus/m4a785t-m/romstage.c deleted file mode 100644 index 50746adbd7..0000000000 --- a/src/mainboard/asus/m4a785t-m/romstage.c +++ /dev/null @@ -1,17 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 Denis 'GNUtoo' Carikli - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include "../m4a785-m/romstage.c" diff --git a/src/mainboard/asus/m5a88-v/Kconfig b/src/mainboard/asus/m5a88-v/Kconfig deleted file mode 100644 index bd131c34ab..0000000000 --- a/src/mainboard/asus/m5a88-v/Kconfig +++ /dev/null @@ -1,64 +0,0 @@ -if BOARD_ASUS_M5A88_V - -config BOARD_SPECIFIC_OPTIONS - def_bool y - select CPU_AMD_SOCKET_AM3 - select DIMM_DDR3 - select DIMM_REGISTERED - select NORTHBRIDGE_AMD_AMDFAM10 - select SOUTHBRIDGE_AMD_RS780 - select SOUTHBRIDGE_AMD_SB800 - select SUPERIO_ITE_IT8721F - select HAVE_OPTION_TABLE - select HAVE_PIRQ_TABLE - select SB_HT_CHAIN_UNITID_OFFSET_ONLY - select LIFT_BSP_APIC_ID - select HAVE_MP_TABLE - select HAVE_ACPI_TABLES - select BOARD_ROMSIZE_KB_2048 - select ENABLE_APIC_EXT_ID - select GFXUMA - select HAVE_DEBUG_CAR - select SET_FIDVID - -config MAINBOARD_DIR - string - default asus/m5a88-v - -config APIC_ID_OFFSET - hex - default 0x0 - -config MAINBOARD_PART_NUMBER - string - default "M5A88-V" - -config HW_MEM_HOLE_SIZEK - hex - default 0x100000 - -config MAX_CPUS - int - default 8 - -config MAX_PHYSICAL_CPUS - int - default 1 - -config HT_CHAIN_END_UNITID_BASE - hex - default 0x1 - -config HT_CHAIN_UNITID_BASE - hex - default 0x0 - -config IRQ_SLOT_COUNT - int - default 11 - -config VGA_BIOS_ID - string - default "1002,9715" - -endif #BOARD_ASUS_M5A88_V diff --git a/src/mainboard/asus/m5a88-v/Kconfig.name b/src/mainboard/asus/m5a88-v/Kconfig.name deleted file mode 100644 index 36b49e6894..0000000000 --- a/src/mainboard/asus/m5a88-v/Kconfig.name +++ /dev/null @@ -1,2 +0,0 @@ -config BOARD_ASUS_M5A88_V - bool "M5A88-V" diff --git a/src/mainboard/asus/m5a88-v/Makefile.inc b/src/mainboard/asus/m5a88-v/Makefile.inc deleted file mode 100644 index 91d4b39c32..0000000000 --- a/src/mainboard/asus/m5a88-v/Makefile.inc +++ /dev/null @@ -1,16 +0,0 @@ -# -# This file is part of the coreboot project. -# -# This program is free software; you can redistribute it and/or modify -# it under the terms of the GNU General Public License as published by -# the Free Software Foundation; version 2 of the License. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# - -romstage-y += resourcemap.c - -ramstage-y += get_bus_conf.c diff --git a/src/mainboard/asus/m5a88-v/acpi/cpstate.asl b/src/mainboard/asus/m5a88-v/acpi/cpstate.asl deleted file mode 100644 index eb4eac1027..0000000000 --- a/src/mainboard/asus/m5a88-v/acpi/cpstate.asl +++ /dev/null @@ -1,80 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -/* This file defines the processor and performance state capability - * for each core in the system. It is included into the DSDT for each - * core. It assumes that each core of the system has the same performance - * characteristics. -*/ -/* -#include -DefinitionBlock ("DSDT.AML", "DSDT", 0x01, OEM_ID, ACPI_TABLE_CREATOR, 0x00010001) - { - Scope (\_PR) { - Device (CPU0) { - Name (_HID, "ACPI0007") - Name (_UID, 0) - #include "cpstate.asl" - } - Device (CPU1) { - Name (_HID, "ACPI0007") - Name (_UID, 1) - #include "cpstate.asl" - } - Device (CPU2) { - Name (_HID, "ACPI0007") - Name (_UID, 2) - #include "cpstate.asl" - } - Device (CPU3) { - Name (_HID, "ACPI0007") - Name (_UID, 3) - #include "cpstate.asl" - } - } -*/ - /* P-state support: The maximum number of P-states supported by the */ - /* CPUs we'll use is 6. */ - /* Get from AMI BIOS. */ - Name(_PSS, Package(){ - Package () - { - 0x00000AF0, - 0x0000BF81, - 0x00000002, - 0x00000002, - 0x00000000, - 0x00000000 - }, - - Package () - { - 0x00000578, - 0x000076F2, - 0x00000002, - 0x00000002, - 0x00000001, - 0x00000001 - } - }) - - Name(_PCT, Package(){ - ResourceTemplate(){Register(FFixedHW, 0, 0, 0)}, - ResourceTemplate(){Register(FFixedHW, 0, 0, 0)} - }) - - Method(_PPC, 0){ - Return(0) - } diff --git a/src/mainboard/asus/m5a88-v/acpi/ide.asl b/src/mainboard/asus/m5a88-v/acpi/ide.asl deleted file mode 100644 index 59ea078593..0000000000 --- a/src/mainboard/asus/m5a88-v/acpi/ide.asl +++ /dev/null @@ -1,240 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -/* -Scope (_SB) { - Device(PCI0) { - Device(IDEC) { - Name(_ADR, 0x00140001) - #include "ide.asl" - } - } -} -*/ - -/* Some timing tables */ -Name(UDTT, Package(){ /* Udma timing table */ - 120, 90, 60, 45, 30, 20, 15, 0 /* UDMA modes 0 -> 6 */ -}) - -Name(MDTT, Package(){ /* MWDma timing table */ - 480, 150, 120, 0 /* Legacy DMA modes 0 -> 2 */ -}) - -Name(POTT, Package(){ /* Pio timing table */ - 600, 390, 270, 180, 120, 0 /* PIO modes 0 -> 4 */ -}) - -/* Some timing register value tables */ -Name(MDRT, Package(){ /* MWDma timing register table */ - 0x77, 0x21, 0x20, 0xFF /* Legacy DMA modes 0 -> 2 */ -}) - -Name(PORT, Package(){ - 0x99, 0x47, 0x34, 0x22, 0x20, 0x99 /* PIO modes 0 -> 4 */ -}) - -OperationRegion(ICRG, PCI_Config, 0x40, 0x20) /* ide control registers */ - Field(ICRG, AnyAcc, NoLock, Preserve) -{ - PPTS, 8, /* Primary PIO Slave Timing */ - PPTM, 8, /* Primary PIO Master Timing */ - OFFSET(0x04), PMTS, 8, /* Primary MWDMA Slave Timing */ - PMTM, 8, /* Primary MWDMA Master Timing */ - OFFSET(0x08), PPCR, 8, /* Primary PIO Control */ - OFFSET(0x0A), PPMM, 4, /* Primary PIO master Mode */ - PPSM, 4, /* Primary PIO slave Mode */ - OFFSET(0x14), PDCR, 2, /* Primary UDMA Control */ - OFFSET(0x16), PDMM, 4, /* Primary UltraDMA Mode */ - PDSM, 4, /* Primary UltraDMA Mode */ -} - -Method(GTTM, 1) /* get total time*/ -{ - Store(And(Arg0, 0x0F), Local0) /* Recovery Width */ - Increment(Local0) - Store(ShiftRight(Arg0, 4), Local1) /* Command Width */ - Increment(Local1) - Return(Multiply(30, Add(Local0, Local1))) -} - -Device(PRID) -{ - Name (_ADR, Zero) - Method(_GTM, 0, Serialized) - { - NAME(OTBF, Buffer(20) { /* out buffer */ - 0xFF, 0xFF, 0xFF, 0xFF, - 0xFF, 0xFF, 0xFF, 0xFF, - 0xFF, 0xFF, 0xFF, 0xFF, - 0xFF, 0xFF, 0xFF, 0xFF, 0x00, 0x00, 0x00, 0x00 - }) - - CreateDwordField(OTBF, 0, PSD0) /* PIO spd0 */ - CreateDwordField(OTBF, 4, DSD0) /* DMA spd0 */ - CreateDwordField(OTBF, 8, PSD1) /* PIO spd1 */ - CreateDwordField(OTBF, 12, DSD1) /* DMA spd1 */ - CreateDwordField(OTBF, 16, BFFG) /* buffer flags */ - - /* Just return if the channel is disabled */ - If(And(PPCR, 0x01)) { /* primary PIO control */ - Return(OTBF) - } - - /* Always tell them independent timing available and IOChannelReady used on both drives */ - Or(BFFG, 0x1A, BFFG) - - Store(GTTM(PPTM), PSD0) /* save total time of primary PIO master timming to PIO spd0 */ - Store(GTTM(PPTS), PSD1) /* save total time of primary PIO slave Timing to PIO spd1 */ - - If(And(PDCR, 0x01)) { /* It's under UDMA mode */ - Or(BFFG, 0x01, BFFG) - Store(DerefOf(Index(UDTT, PDMM)), DSD0) - } - Else { - Store(GTTM(PMTM), DSD0) /* Primary MWDMA Master Timing, DmaSpd0 */ - } - - If(And(PDCR, 0x02)) { /* It's under UDMA mode */ - Or(BFFG, 0x04, BFFG) - Store(DerefOf(Index(UDTT, PDSM)), DSD1) - } - Else { - Store(GTTM(PMTS), DSD1) /* Primary MWDMA Slave Timing, DmaSpd0 */ - } - - Return(OTBF) /* out buffer */ - } /* End Method(_GTM) */ - - Method(_STM, 3, Serialized) - { - NAME(INBF, Buffer(20) { /* in buffer */ - 0xFF, 0xFF, 0xFF, 0xFF, - 0xFF, 0xFF, 0xFF, 0xFF, - 0xFF, 0xFF, 0xFF, 0xFF, - 0xFF, 0xFF, 0xFF, 0xFF, 0x00, 0x00, 0x00, 0x00 - }) - - CreateDwordField(INBF, 0, PSD0) /* PIO spd0 */ - CreateDwordField(INBF, 4, DSD0) /* PIO spd0 */ - CreateDwordField(INBF, 8, PSD1) /* PIO spd1 */ - CreateDwordField(INBF, 12, DSD1) /* DMA spd1 */ - CreateDwordField(INBF, 16, BFFG) /*buffer flag */ - - Store(Match(POTT, MLE, PSD0, MTR, 0, 0), Local0) - Divide(Local0, 5, PPMM,) /* Primary PIO master Mode */ - Store(Match(POTT, MLE, PSD1, MTR, 0, 0), Local1) - Divide(Local1, 5, PPSM,) /* Primary PIO slave Mode */ - - Store(DerefOf(Index(PORT, Local0)), PPTM) /* Primary PIO Master Timing */ - Store(DerefOf(Index(PORT, Local1)), PPTS) /* Primary PIO Slave Timing */ - - If(And(BFFG, 0x01)) { /* Drive 0 is under UDMA mode */ - Store(Match(UDTT, MLE, DSD0, MTR, 0, 0), Local0) - Divide(Local0, 7, PDMM,) - Or(PDCR, 0x01, PDCR) - } - Else { - If(LNotEqual(DSD0, 0xFFFFFFFF)) { - Store(Match(MDTT, MLE, DSD0, MTR, 0, 0), Local0) - Store(DerefOf(Index(MDRT, Local0)), PMTM) - } - } - - If(And(BFFG, 0x04)) { /* Drive 1 is under UDMA mode */ - Store(Match(UDTT, MLE, DSD1, MTR, 0, 0), Local0) - Divide(Local0, 7, PDSM,) - Or(PDCR, 0x02, PDCR) - } - Else { - If(LNotEqual(DSD1, 0xFFFFFFFF)) { - Store(Match(MDTT, MLE, DSD1, MTR, 0, 0), Local0) - Store(DerefOf(Index(MDRT, Local0)), PMTS) - } - } - /* Return(INBF) */ - } /*End Method(_STM) */ - Device(MST) - { - Name(_ADR, 0) - Method(_GTF, 0, Serialized) { - Name(CMBF, Buffer(21) { - 0x03, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xEF, - 0x03, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xEF, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xF5 - }) - CreateByteField(CMBF, 1, POMD) - CreateByteField(CMBF, 8, DMMD) - CreateByteField(CMBF, 5, CMDA) - CreateByteField(CMBF, 12, CMDB) - CreateByteField(CMBF, 19, CMDC) - - Store(0xA0, CMDA) - Store(0xA0, CMDB) - Store(0xA0, CMDC) - - Or(PPMM, 0x08, POMD) - - If(And(PDCR, 0x01)) { - Or(PDMM, 0x40, DMMD) - } - Else { - Store(Match - (MDTT, MLE, GTTM(PMTM), - MTR, 0, 0), Local0) - If(LLess(Local0, 3)) { - Or(0x20, Local0, DMMD) - } - } - Return(CMBF) - } - } /* End Device(MST) */ - - Device(SLAV) - { - Name(_ADR, 1) - Method(_GTF, 0, Serialized) { - Name(CMBF, Buffer(21) { - 0x03, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xEF, - 0x03, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xEF, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xF5 - }) - CreateByteField(CMBF, 1, POMD) - CreateByteField(CMBF, 8, DMMD) - CreateByteField(CMBF, 5, CMDA) - CreateByteField(CMBF, 12, CMDB) - CreateByteField(CMBF, 19, CMDC) - - Store(0xB0, CMDA) - Store(0xB0, CMDB) - Store(0xB0, CMDC) - - Or(PPSM, 0x08, POMD) - - If(And(PDCR, 0x02)) { - Or(PDSM, 0x40, DMMD) - } - Else { - Store(Match - (MDTT, MLE, GTTM(PMTS), - MTR, 0, 0), Local0) - If(LLess(Local0, 3)) { - Or(0x20, Local0, DMMD) - } - } - Return(CMBF) - } - } /* End Device(SLAV) */ -} diff --git a/src/mainboard/asus/m5a88-v/acpi/routing.asl b/src/mainboard/asus/m5a88-v/acpi/routing.asl deleted file mode 100644 index 46920552e7..0000000000 --- a/src/mainboard/asus/m5a88-v/acpi/routing.asl +++ /dev/null @@ -1,395 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -/* -#include -DefinitionBlock ("DSDT.AML", "DSDT", 0x01, OEM_ID, ACPI_TABLE_CREATOR, 0x00010001 - ) - { - #include "routing.asl" - } -*/ - -/* Routing is in System Bus scope */ -Scope(\_SB) { - Name(PR0, Package(){ - /* NB devices */ - /* Bus 0, Dev 0 - RS780 Host Controller */ - /* Bus 0, Dev 1 - PCI Bridge for Internal Graphics */ - /* Bus 0, Dev 2 - PCIe Bridge for x8 PCIe Slot (GFX0) */ - Package(){0x0002FFFF, 0, INTC, 0 }, - Package(){0x0002FFFF, 1, INTD, 0 }, - Package(){0x0002FFFF, 2, INTA, 0 }, - Package(){0x0002FFFF, 3, INTB, 0 }, - /* Bus 0, Dev 3 - PCIe graphics port 1 bridge */ - /* Bus 0, Dev 4 - PCIe Bridge for Express Card Slot */ - Package(){0x0004FFFF, 0, INTA, 0 }, - Package(){0x0004FFFF, 1, INTB, 0 }, - Package(){0x0004FFFF, 2, INTC, 0 }, - Package(){0x0004FFFF, 3, INTD, 0 }, - /* Bus 0, Dev 5 - General purpose PCIe bridge 5 */ - /* Package(){0x0005FFFF, 0, INTB, 0 }, */ - /* Package(){0x0005FFFF, 1, INTC, 0 }, */ - /* Package(){0x0005FFFF, 2, INTD, 0 }, */ - /* Package(){0x0005FFFF, 3, INTA, 0 }, */ - /* Bus 0, Dev 6 - PCIe Bridge for Ethernet Chip */ - Package(){0x0006FFFF, 0, INTC, 0 }, - Package(){0x0006FFFF, 1, INTD, 0 }, - Package(){0x0006FFFF, 2, INTA, 0 }, - Package(){0x0006FFFF, 3, INTB, 0 }, - /* Bus 0, Dev 7 - PCIe Bridge for x1 PCIe Slot */ - Package(){0x0007FFFF, 0, INTD, 0 }, - Package(){0x0007FFFF, 1, INTA, 0 }, - Package(){0x0007FFFF, 2, INTB, 0 }, - Package(){0x0007FFFF, 3, INTC, 0 }, - - Package(){0x0009FFFF, 0, INTB, 0 }, - Package(){0x0009FFFF, 1, INTC, 0 }, - Package(){0x0009FFFF, 2, INTD, 0 }, - Package(){0x0009FFFF, 3, INTA, 0 }, - - Package(){0x000AFFFF, 0, INTC, 0 }, - Package(){0x000AFFFF, 1, INTD, 0 }, - Package(){0x000AFFFF, 2, INTA, 0 }, - Package(){0x000AFFFF, 3, INTB, 0 }, - - Package(){0x000BFFFF, 0, INTD, 0 }, - Package(){0x000BFFFF, 1, INTA, 0 }, - Package(){0x000BFFFF, 2, INTB, 0 }, - Package(){0x000BFFFF, 3, INTC, 0 }, - - Package(){0x000CFFFF, 0, INTA, 0 }, - Package(){0x000CFFFF, 1, INTB, 0 }, - Package(){0x000CFFFF, 2, INTC, 0 }, - Package(){0x000CFFFF, 3, INTD, 0 }, - - /* Bus 0, Funct 8 - Southbridge port (normally hidden) */ - - /* SB devices */ - /* Bus 0, Dev 17 - SATA controller #2 */ - /* Bus 0, Dev 18 - SATA controller #1 */ - Package(){0x0011FFFF, 0, INTD, 0 }, - - /* Bus 0, Dev 19 - USB: OHCI, dev 18,19 func 0-2, dev 20 func 5; - * EHCI, dev 18, 19 func 2 */ - Package(){0x0012FFFF, 0, INTC, 0 }, - Package(){0x0012FFFF, 1, INTB, 0 }, - - Package(){0x0013FFFF, 0, INTC, 0 }, - Package(){0x0013FFFF, 1, INTB, 0 }, - - Package(){0x0016FFFF, 0, INTC, 0 }, - Package(){0x0016FFFF, 1, INTB, 0 }, - - /* Package(){0x0014FFFF, 1, INTA, 0 }, */ - - /* Bus 0, Dev 20 - F0:SMBus/ACPI,F1:IDE;F2:HDAudio;F3:LPC;F4:PCIBridge;F5:USB */ - Package(){0x0014FFFF, 0, INTA, 0 }, - Package(){0x0014FFFF, 1, INTB, 0 }, - Package(){0x0014FFFF, 2, INTC, 0 }, - Package(){0x0014FFFF, 3, INTD, 0 }, - - Package(){0x0015FFFF, 0, INTA, 0 }, - Package(){0x0015FFFF, 1, INTB, 0 }, - Package(){0x0015FFFF, 2, INTC, 0 }, - Package(){0x0015FFFF, 3, INTD, 0 }, - }) - - Name(APR0, Package(){ - /* NB devices in APIC mode */ - /* Bus 0, Dev 0 - RS780 Host Controller */ - - /* Bus 0, Dev 1 - PCI Bridge for Internal Graphics */ - Package(){0x0001FFFF, 0, 0, 18 }, - Package(){0x0001FFFF, 1, 0, 19 }, - - /* Bus 0, Dev 2 - PCIe Bridge for x8 PCIe Slot (GFX0) */ - Package(){0x0002FFFF, 0, 0, 18 }, - /* Package(){0x0002FFFF, 1, 0, 19 }, */ - /* Package(){0x0002FFFF, 2, 0, 16 }, */ - /* Package(){0x0002FFFF, 3, 0, 17 }, */ - - /* Bus 0, Dev 3 - PCIe graphics port 1 bridge */ - Package(){0x0003FFFF, 0, 0, 19 }, - - /* Bus 0, Dev 4 - PCIe Bridge for Express Card Slot */ - Package(){0x0004FFFF, 0, 0, 16 }, - /* Package(){0x0004FFFF, 1, 0, 17 }, */ - /* Package(){0x0004FFFF, 2, 0, 18 }, */ - /* Package(){0x0004FFFF, 3, 0, 19 }, */ - - /* Bus 0, Dev 5 - General purpose PCIe bridge 5 */ - /* Package(){0x0005FFFF, 0, 0, 17 }, */ - /* Package(){0x0005FFFF, 1, 0, 18 }, */ - /* Package(){0x0005FFFF, 2, 0, 19 }, */ - /* Package(){0x0005FFFF, 3, 0, 16 }, */ - - /* Bus 0, Dev 6 - General purpose PCIe bridge 6 */ - /* Package(){0x0006FFFF, 0, 0, 18 }, */ - /* Package(){0x0006FFFF, 1, 0, 19 }, */ - /* Package(){0x0006FFFF, 2, 0, 16 }, */ - /* Package(){0x0006FFFF, 3, 0, 17 }, */ - - /* Bus 0, Dev 7 - PCIe Bridge for network card */ - /* Package(){0x0007FFFF, 0, 0, 19 }, */ - /* Package(){0x0007FFFF, 1, 0, 16 }, */ - /* Package(){0x0007FFFF, 2, 0, 17 }, */ - /* Package(){0x0007FFFF, 3, 0, 18 }, */ - - /* Bus 0, Dev 9 - PCIe Bridge for network card */ - Package(){0x0009FFFF, 0, 0, 17 }, - /* Package(){0x0009FFFF, 1, 0, 16 }, */ - /* Package(){0x0009FFFF, 2, 0, 17 }, */ - /* Package(){0x0009FFFF, 3, 0, 18 }, */ - /* Bus 0, Dev A - PCIe Bridge for network card */ - Package(){0x000AFFFF, 0, 0, 18 }, - /* Package(){0x000AFFFF, 1, 0, 16 }, */ - /* Package(){0x000AFFFF, 2, 0, 17 }, */ - /* Package(){0x000AFFFF, 3, 0, 18 }, */ - /* Bus 0, Funct 8 - Southbridge port (normally hidden) */ - - /* SB devices in APIC mode */ - /* Bus 0, Dev 17 - SATA controller #2 */ - /* Bus 0, Dev 18 - SATA controller #1 */ - Package(){0x0011FFFF, 0, 0, 19 }, - - /* Bus 0, Dev 19 - USB: OHCI, dev 18,19 func 0-2, dev 20 func 5; - * EHCI, dev 18, 19 func 2 */ - Package(){0x0012FFFF, 0, 0, 18 }, - Package(){0x0012FFFF, 1, 0, 17 }, - /* Package(){0x0012FFFF, 2, 0, 18 }, */ - - Package(){0x0013FFFF, 0, 0, 18 }, - Package(){0x0013FFFF, 1, 0, 17 }, - /* Package(){0x0013FFFF, 2, 0, 16 }, */ - - /* Package(){0x00140000, 0, 0, 16 }, */ - - Package(){0x0016FFFF, 0, 0, 18 }, - Package(){0x0016FFFF, 1, 0, 17 }, - - /* Bus 0, Dev 20 - F0:SMBus/ACPI, F1:IDE; F2:HDAudio; F3:LPC; F4:PCIBridge; F5:USB */ - Package(){0x0014FFFF, 0, 0, 16 }, - Package(){0x0014FFFF, 1, 0, 17 }, - Package(){0x0014FFFF, 2, 0, 18 }, - Package(){0x0014FFFF, 3, 0, 19 }, - /* Package(){0x00140004, 2, 0, 18 }, */ - /* Package(){0x00140004, 3, 0, 19 }, */ - /* Package(){0x00140005, 1, 0, 17 }, */ - /* Package(){0x00140006, 1, 0, 17 }, */ - - /* TODO: pcie */ - Package(){0x0015FFFF, 0, 0, 16 }, - Package(){0x0015FFFF, 1, 0, 17 }, - Package(){0x0015FFFF, 2, 0, 18 }, - Package(){0x0015FFFF, 3, 0, 19 }, - }) - - Name(PR1, Package(){ - /* Internal graphics - RS780 VGA, Bus1, Dev5 */ - Package(){0x0005FFFF, 0, INTA, 0 }, - Package(){0x0005FFFF, 1, INTB, 0 }, - Package(){0x0005FFFF, 2, INTC, 0 }, - Package(){0x0005FFFF, 3, INTD, 0 }, - }) - Name(APR1, Package(){ - /* Internal graphics - RS780 VGA, Bus1, Dev5 */ - Package(){0x0005FFFF, 0, 0, 18 }, - Package(){0x0005FFFF, 1, 0, 19 }, - /* Package(){0x0005FFFF, 2, 0, 20 }, */ - /* Package(){0x0005FFFF, 3, 0, 17 }, */ - }) - - Name(PS2, Package(){ - /* The external GFX - Hooked to PCIe slot 2 */ - Package(){0x0000FFFF, 0, INTC, 0 }, - Package(){0x0000FFFF, 1, INTD, 0 }, - Package(){0x0000FFFF, 2, INTA, 0 }, - Package(){0x0000FFFF, 3, INTB, 0 }, - }) - Name(APS2, Package(){ - /* The external GFX - Hooked to PCIe slot 2 */ - Package(){0x0000FFFF, 0, 0, 18 }, - Package(){0x0000FFFF, 1, 0, 19 }, - Package(){0x0000FFFF, 2, 0, 16 }, - Package(){0x0000FFFF, 3, 0, 17 }, - }) - - Name(PS4, Package(){ - /* PCIe slot - Hooked to PCIe slot 4 */ - Package(){0x0000FFFF, 0, INTA, 0 }, - Package(){0x0000FFFF, 1, INTB, 0 }, - Package(){0x0000FFFF, 2, INTC, 0 }, - Package(){0x0000FFFF, 3, INTD, 0 }, - }) - Name(APS4, Package(){ - /* PCIe slot - Hooked to PCIe slot 4 */ - Package(){0x0000FFFF, 0, 0, 16 }, - Package(){0x0000FFFF, 1, 0, 17 }, - Package(){0x0000FFFF, 2, 0, 18 }, - Package(){0x0000FFFF, 3, 0, 19 }, - }) - - Name(PS5, Package(){ - /* PCIe slot - Hooked to PCIe slot 5 */ - Package(){0x0000FFFF, 0, INTB, 0 }, - Package(){0x0000FFFF, 1, INTC, 0 }, - Package(){0x0000FFFF, 2, INTD, 0 }, - Package(){0x0000FFFF, 3, INTA, 0 }, - }) - Name(APS5, Package(){ - /* PCIe slot - Hooked to PCIe slot 5 */ - Package(){0x0000FFFF, 0, 0, 17 }, - Package(){0x0000FFFF, 1, 0, 18 }, - Package(){0x0000FFFF, 2, 0, 19 }, - Package(){0x0000FFFF, 3, 0, 16 }, - }) - - Name(PS6, Package(){ - /* PCIe slot - Hooked to PCIe slot 6 */ - Package(){0x0000FFFF, 0, INTC, 0 }, - Package(){0x0000FFFF, 1, INTD, 0 }, - Package(){0x0000FFFF, 2, INTA, 0 }, - Package(){0x0000FFFF, 3, INTB, 0 }, - }) - Name(APS6, Package(){ - /* PCIe slot - Hooked to PCIe slot 6 */ - Package(){0x0000FFFF, 0, 0, 18 }, - Package(){0x0000FFFF, 1, 0, 19 }, - Package(){0x0000FFFF, 2, 0, 16 }, - Package(){0x0000FFFF, 3, 0, 17 }, - }) - - Name(PS7, Package(){ - /* The onboard Ethernet chip - Hooked to PCIe slot 7 */ - Package(){0x0000FFFF, 0, INTD, 0 }, - Package(){0x0000FFFF, 1, INTA, 0 }, - Package(){0x0000FFFF, 2, INTB, 0 }, - Package(){0x0000FFFF, 3, INTC, 0 }, - }) - Name(APS7, Package(){ - /* The onboard Ethernet chip - Hooked to PCIe slot 7 */ - Package(){0x0000FFFF, 0, 0, 19 }, - Package(){0x0000FFFF, 1, 0, 16 }, - Package(){0x0000FFFF, 2, 0, 17 }, - Package(){0x0000FFFF, 3, 0, 18 }, - }) - - Name(PS9, Package(){ - /* PCIe slot - Hooked to PCIe slot 9 */ - Package(){0x0000FFFF, 0, INTD, 0 }, - Package(){0x0000FFFF, 1, INTA, 0 }, - Package(){0x0000FFFF, 2, INTB, 0 }, - Package(){0x0000FFFF, 3, INTC, 0 }, - }) - Name(APS9, Package(){ - /* PCIe slot - Hooked to PCIe slot 9 */ - Package(){0x0000FFFF, 0, 0, 17 }, - Package(){0x0000FFFF, 1, 0, 18 }, - Package(){0x0000FFFF, 2, 0, 19 }, - Package(){0x0000FFFF, 3, 0, 16 }, - }) - - Name(PSa, Package(){ - /* PCIe slot - Hooked to PCIe slot 10 */ - Package(){0x0000FFFF, 0, INTD, 0 }, - Package(){0x0000FFFF, 1, INTA, 0 }, - Package(){0x0000FFFF, 2, INTB, 0 }, - Package(){0x0000FFFF, 3, INTC, 0 }, - }) - Name(APSa, Package(){ - /* PCIe slot - Hooked to PCIe slot 10 */ - Package(){0x0000FFFF, 0, 0, 18 }, - Package(){0x0000FFFF, 1, 0, 19 }, - Package(){0x0000FFFF, 2, 0, 16 }, - Package(){0x0000FFFF, 3, 0, 17 }, - }) - - Name(PE0, Package(){ - /* PCIe slot - Hooked to PCIe slot 10 */ - Package(){0x0000FFFF, 0, INTA, 0 }, - Package(){0x0000FFFF, 1, INTB, 0 }, - Package(){0x0000FFFF, 2, INTC, 0 }, - Package(){0x0000FFFF, 3, INTD, 0 }, - }) - Name(APE0, Package(){ - /* PCIe slot - Hooked to PCIe */ - Package(){0x0000FFFF, 0, 0, 16 }, - Package(){0x0000FFFF, 1, 0, 17 }, - Package(){0x0000FFFF, 2, 0, 18 }, - Package(){0x0000FFFF, 3, 0, 19 }, - }) - - Name(PE1, Package(){ - /* PCIe slot - Hooked to PCIe slot 10 */ - Package(){0x0000FFFF, 0, INTB, 0 }, - Package(){0x0000FFFF, 1, INTC, 0 }, - Package(){0x0000FFFF, 2, INTD, 0 }, - Package(){0x0000FFFF, 3, INTA, 0 }, - }) - Name(APE1, Package(){ - /* PCIe slot - Hooked to PCIe */ - Package(){0x0000FFFF, 0, 0, 17 }, - Package(){0x0000FFFF, 1, 0, 18 }, - Package(){0x0000FFFF, 2, 0, 19 }, - Package(){0x0000FFFF, 3, 0, 16 }, - }) - - Name(PE2, Package(){ - /* PCIe slot - Hooked to PCIe slot 10 */ - Package(){0x0000FFFF, 0, INTC, 0 }, - Package(){0x0000FFFF, 1, INTD, 0 }, - Package(){0x0000FFFF, 2, INTA, 0 }, - Package(){0x0000FFFF, 3, INTB, 0 }, - }) - Name(APE2, Package(){ - /* PCIe slot - Hooked to PCIe */ - Package(){0x0000FFFF, 0, 0, 18 }, - Package(){0x0000FFFF, 1, 0, 19 }, - Package(){0x0000FFFF, 2, 0, 16 }, - Package(){0x0000FFFF, 3, 0, 17 }, - }) - - Name(PE3, Package(){ - /* PCIe slot - Hooked to PCIe slot 10 */ - Package(){0x0000FFFF, 0, INTD, 0 }, - Package(){0x0000FFFF, 1, INTA, 0 }, - Package(){0x0000FFFF, 2, INTB, 0 }, - Package(){0x0000FFFF, 3, INTC, 0 }, - }) - Name(APE3, Package(){ - /* PCIe slot - Hooked to PCIe */ - Package(){0x0000FFFF, 0, 0, 19 }, - Package(){0x0000FFFF, 1, 0, 16 }, - Package(){0x0000FFFF, 2, 0, 17 }, - Package(){0x0000FFFF, 3, 0, 18 }, - }) - - Name(PCIB, Package(){ - /* PCI slots: slot 0, slot 1, slot 2 behind Dev14, Fun4. */ - Package(){0x0005FFFF, 0, 0, 0x14 }, - Package(){0x0005FFFF, 1, 0, 0x15 }, - Package(){0x0005FFFF, 2, 0, 0x16 }, - Package(){0x0005FFFF, 3, 0, 0x17 }, - Package(){0x0006FFFF, 0, 0, 0x15 }, - Package(){0x0006FFFF, 1, 0, 0x16 }, - Package(){0x0006FFFF, 2, 0, 0x17 }, - Package(){0x0006FFFF, 3, 0, 0x14 }, - Package(){0x0007FFFF, 0, 0, 0x16 }, - Package(){0x0007FFFF, 1, 0, 0x17 }, - Package(){0x0007FFFF, 2, 0, 0x14 }, - Package(){0x0007FFFF, 3, 0, 0x15 }, - }) -} diff --git a/src/mainboard/asus/m5a88-v/acpi/sata.asl b/src/mainboard/asus/m5a88-v/acpi/sata.asl deleted file mode 100644 index 9e0e535da6..0000000000 --- a/src/mainboard/asus/m5a88-v/acpi/sata.asl +++ /dev/null @@ -1,145 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -/* simple name description */ - -/* -Scope (_SB) { - Device(PCI0) { - Device(SATA) { - Name(_ADR, 0x00110000) - #include "sata.asl" - } - } -} -*/ - -Name(STTM, Buffer(20) { - 0x78, 0x00, 0x00, 0x00, 0x0f, 0x00, 0x00, 0x00, - 0x78, 0x00, 0x00, 0x00, 0x0f, 0x00, 0x00, 0x00, - 0x1f, 0x00, 0x00, 0x00 -}) - -/* Start by clearing the PhyRdyChg bits */ -Method(_INI) { - \_GPE._L1F() -} - -Device(PMRY) -{ - Name(_ADR, 0) - Method(_GTM, 0x0, NotSerialized) { - Return(STTM) - } - Method(_STM, 0x3, NotSerialized) {} - - Device(PMST) { - Name(_ADR, 0) - Method(_STA,0) { - if (LGreater(P0IS,0)) { - return (0x0F) /* sata is visible */ - } - else { - return (0x00) /* sata is missing */ - } - } - }/* end of PMST */ - - Device(PSLA) - { - Name(_ADR, 1) - Method(_STA,0) { - if (LGreater(P1IS,0)) { - return (0x0F) /* sata is visible */ - } - else { - return (0x00) /* sata is missing */ - } - } - } /* end of PSLA */ -} /* end of PMRY */ - - -Device(SEDY) -{ - Name(_ADR, 1) /* IDE Scondary Channel */ - Method(_GTM, 0x0, NotSerialized) { - Return(STTM) - } - Method(_STM, 0x3, NotSerialized) {} - - Device(SMST) - { - Name(_ADR, 0) - Method(_STA,0) { - if (LGreater(P2IS,0)) { - return (0x0F) /* sata is visible */ - } - else { - return (0x00) /* sata is missing */ - } - } - } /* end of SMST */ - - Device(SSLA) - { - Name(_ADR, 1) - Method(_STA,0) { - if (LGreater(P3IS,0)) { - return (0x0F) /* sata is visible */ - } - else { - return (0x00) /* sata is missing */ - } - } - } /* end of SSLA */ -} /* end of SEDY */ - -/* SATA Hot Plug Support */ -Scope(\_GPE) { - Method(_L1F,0x0,NotSerialized) { - if (\_SB.P0PR) { - if (LGreater(\_SB.P0IS,0)) { - sleep(32) - } - Notify(\_SB.PCI0.STCR.PMRY.PMST, 0x01) /* NOTIFY_DEVICE_CHECK */ - store(one, \_SB.P0PR) - } - - if (\_SB.P1PR) { - if (LGreater(\_SB.P1IS,0)) { - sleep(32) - } - Notify(\_SB.PCI0.STCR.PMRY.PSLA, 0x01) /* NOTIFY_DEVICE_CHECK */ - store(one, \_SB.P1PR) - } - - if (\_SB.P2PR) { - if (LGreater(\_SB.P2IS,0)) { - sleep(32) - } - Notify(\_SB.PCI0.STCR.SEDY.SMST, 0x01) /* NOTIFY_DEVICE_CHECK */ - store(one, \_SB.P2PR) - } - - if (\_SB.P3PR) { - if (LGreater(\_SB.P3IS,0)) { - sleep(32) - } - Notify(\_SB.PCI0.STCR.SEDY.SSLA, 0x01) /* NOTIFY_DEVICE_CHECK */ - store(one, \_SB.P3PR) - } - } -} diff --git a/src/mainboard/asus/m5a88-v/acpi/usb.asl b/src/mainboard/asus/m5a88-v/acpi/usb.asl deleted file mode 100644 index cd76bf1f94..0000000000 --- a/src/mainboard/asus/m5a88-v/acpi/usb.asl +++ /dev/null @@ -1,158 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -/* simple name description */ -/* -#include -DefinitionBlock ("DSDT.AML", "DSDT", 0x01, OEM_ID, ACPI_TABLE_CREATOR, 0x00010001 - ) - { - #include "usb.asl" - } -*/ -Method(UCOC, 0) { - Sleep(20) - Store(0x13,CMTI) - Store(0,GPSL) -} - -/* USB Port 0 overcurrent uses Gpm 0 */ -If(LLessEqual(UOM0,9)) { - Scope (\_GPE) { - Method (_L13) { - UCOC() - if(LEqual(GPB0,PLC0)) { - Not(PLC0,PLC0) - Store(PLC0, \_SB.PT0D) - } - } - } -} - -/* USB Port 1 overcurrent uses Gpm 1 */ -If (LLessEqual(UOM1,9)) { - Scope (\_GPE) { - Method (_L14) { - UCOC() - if (LEqual(GPB1,PLC1)) { - Not(PLC1,PLC1) - Store(PLC1, \_SB.PT1D) - } - } - } -} - -/* USB Port 2 overcurrent uses Gpm 2 */ -If (LLessEqual(UOM2,9)) { - Scope (\_GPE) { - Method (_L15) { - UCOC() - if (LEqual(GPB2,PLC2)) { - Not(PLC2,PLC2) - Store(PLC2, \_SB.PT2D) - } - } - } -} - -/* USB Port 3 overcurrent uses Gpm 3 */ -If (LLessEqual(UOM3,9)) { - Scope (\_GPE) { - Method (_L16) { - UCOC() - if (LEqual(GPB3,PLC3)) { - Not(PLC3,PLC3) - Store(PLC3, \_SB.PT3D) - } - } - } -} - -/* USB Port 4 overcurrent uses Gpm 4 */ -If (LLessEqual(UOM4,9)) { - Scope (\_GPE) { - Method (_L19) { - UCOC() - if (LEqual(GPB4,PLC4)) { - Not(PLC4,PLC4) - Store(PLC4, \_SB.PT4D) - } - } - } -} - -/* USB Port 5 overcurrent uses Gpm 5 */ -If (LLessEqual(UOM5,9)) { - Scope (\_GPE) { - Method (_L1A) { - UCOC() - if (LEqual(GPB5,PLC5)) { - Not(PLC5,PLC5) - Store(PLC5, \_SB.PT5D) - } - } - } -} - -/* USB Port 6 overcurrent uses Gpm 6 */ -If (LLessEqual(UOM6,9)) { - Scope (\_GPE) { - /* Method (_L1C) { */ - Method (_L06) { - UCOC() - if (LEqual(GPB6,PLC6)) { - Not(PLC6,PLC6) - Store(PLC6, \_SB.PT6D) - } - } - } -} - -/* USB Port 7 overcurrent uses Gpm 7 */ -If (LLessEqual(UOM7,9)) { - Scope (\_GPE) { - /* Method (_L1D) { */ - Method (_L07) { - UCOC() - if (LEqual(GPB7,PLC7)) { - Not(PLC7,PLC7) - Store(PLC7, \_SB.PT7D) - } - } - } -} - -/* USB Port 8 overcurrent uses Gpm 8 */ -If (LLessEqual(UOM8,9)) { - Scope (\_GPE) { - Method (_L17) { - if (LEqual(G8IS,PLC8)) { - Not(PLC8,PLC8) - Store(PLC8, \_SB.PT8D) - } - } - } -} - -/* USB Port 9 overcurrent uses Gpm 9 */ -If (LLessEqual(UOM9,9)) { - Scope (\_GPE) { - Method (_L0E) { - if (LEqual(G9IS,0)) { - Store(1,\_SB.PT9D) - } - } - } -} diff --git a/src/mainboard/asus/m5a88-v/acpi_tables.c b/src/mainboard/asus/m5a88-v/acpi_tables.c deleted file mode 100644 index 7f429996fd..0000000000 --- a/src/mainboard/asus/m5a88-v/acpi_tables.c +++ /dev/null @@ -1,44 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include -#include - -unsigned long acpi_fill_madt(unsigned long current) -{ - /* create all subtables for processors */ - current = acpi_create_madt_lapics(current); - - /* Write SB800 IOAPIC, only one */ - current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, 2, - IO_APIC_ADDR, 0); - - current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) - current, 0, 0, 2, 0); - current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) - current, 0, 9, 9, 0xF); - /* 0: mean bus 0--->ISA */ - /* 0: PIC 0 */ - /* 2: APIC 2 */ - /* 5 mean: 0101 --> Edge-triggered, Active high */ - - /* create all subtables for processors */ - /* current = acpi_create_madt_lapic_nmis(current, 5, 1); */ - /* 1: LINT1 connect to NMI */ - - return current; -} diff --git a/src/mainboard/asus/m5a88-v/board_info.txt b/src/mainboard/asus/m5a88-v/board_info.txt deleted file mode 100644 index bacf493bc9..0000000000 --- a/src/mainboard/asus/m5a88-v/board_info.txt +++ /dev/null @@ -1,7 +0,0 @@ -Category: desktop -Board URL: http://www.asus.com/Motherboards/AMD_AM3Plus/M5A88V_EVO/ -ROM package: DIP8 -ROM protocol: SPI -ROM socketed: y -Flashrom support: y -Release year: 2011 diff --git a/src/mainboard/asus/m5a88-v/cmos.layout b/src/mainboard/asus/m5a88-v/cmos.layout deleted file mode 100644 index 6c3d3f6c9e..0000000000 --- a/src/mainboard/asus/m5a88-v/cmos.layout +++ /dev/null @@ -1,52 +0,0 @@ -entries - -0 384 r 0 reserved_memory -384 1 e 4 boot_option -388 4 h 0 reboot_counter -#392 3 r 0 unused -395 1 e 1 hw_scrubber -396 1 e 1 interleave_chip_selects -397 2 e 8 max_mem_clock -399 1 e 2 multi_core -400 1 e 1 power_on_after_fail -412 4 e 6 debug_level -440 4 e 9 slow_cpu -444 1 e 1 nmi -445 1 e 1 gart -456 1 e 1 ECC_memory -728 256 h 0 user_data -984 16 h 0 check_sum -# Reserve the extended AMD configuration registers -1000 24 r 0 amd_reserved - - - -enumerations - -#ID value text -1 0 Disable -1 1 Enable -2 0 Enable -2 1 Disable -4 0 Fallback -4 1 Normal -6 5 Notice -6 6 Info -6 7 Debug -6 8 Spew -8 0 400Mhz -8 1 333Mhz -8 2 266Mhz -8 3 200Mhz -9 0 off -9 1 87.5% -9 2 75.0% -9 3 62.5% -9 4 50.0% -9 5 37.5% -9 6 25.0% -9 7 12.5% - -checksums - -checksum 392 983 984 diff --git a/src/mainboard/asus/m5a88-v/devicetree.cb b/src/mainboard/asus/m5a88-v/devicetree.cb deleted file mode 100644 index d0efbdf6e5..0000000000 --- a/src/mainboard/asus/m5a88-v/devicetree.cb +++ /dev/null @@ -1,124 +0,0 @@ -# sample config for advansus/A785E-I -chip northbridge/amd/amdfam10/root_complex - device cpu_cluster 0 on - chip cpu/amd/socket_AM3 #L1 and DDR3 - device lapic 0 on end - end - end - device domain 0 on - subsystemid 0x1043 0x843e inherit #TODO: Set the correctly subsystem id. - chip northbridge/amd/amdfam10 - device pci 18.0 on # northbridge - chip southbridge/amd/rs780 - device pci 0.0 on end # HT 0x9600 - device pci 1.0 on end # Internal Graphics P2P bridge 0x9712 - device pci 2.0 on end # PCIE P2P bridge (external graphics) 0x9603 - device pci 3.0 off end # PCIE P2P bridge 0x960b - device pci 4.0 on end # PCIE P2P bridge 0x9604 wireless - device pci 5.0 off end # PCIE P2P bridge 0x9605 - device pci 6.0 off end # PCIE P2P bridge 0x9606 - device pci 7.0 off end # PCIE P2P bridge 0x9607 - device pci 8.0 off end # NB/SB Link P2P bridge - device pci 9.0 on end # Ethernet - device pci a.0 on end # Ethernet - register "gppsb_configuration" = "4" # Configuration E - register "gpp_configuration" = "3" # Configuration D - register "port_enable" = "0x6f6" - register "gfx_dev2_dev3" = "0" - register "gfx_dual_slot" = "0" - register "gfx_lane_reversal" = "0" - register "gfx_compliance" = "0" - register "gfx_reconfiguration" = "1" - register "gfx_link_width" = "0" - register "gfx_tmds" = "1" - register "gfx_pcie_config" = "3" # 1x8 GFX on Lanes 8-15 - register "gfx_ddi_config" = "1" # Lanes 0-3 DDI_SL - end - chip southbridge/amd/cimx/sb800 # it is under NB/SB Link, but on the same pci bus - device pci 11.0 on end # SATA - device pci 12.0 on end # USB - device pci 12.2 on end # USB - device pci 13.0 on end # USB - device pci 13.2 on end # USB - device pci 14.0 on # SM - chip drivers/generic/generic #dimm 0-0-0 - device i2c 50 on end - end - chip drivers/generic/generic #dimm 0-0-1 - device i2c 51 on end - end - chip drivers/generic/generic #dimm 0-1-0 - device i2c 52 on end - end - chip drivers/generic/generic #dimm 0-1-1 - device i2c 53 on end - end - end # SM - device pci 14.1 on end # IDE 0x439c - device pci 14.2 on end # HDA 0x4383 - device pci 14.3 on # LPC host controller [1002:439d] - chip superio/ite/it8721f - device pnp 2e.0 off # Floppy - io 0x60 = 0x3f0 - irq 0x70 = 6 - drq 0x74 = 2 - end - device pnp 2e.1 off # Parallel Port - io 0x60 = 0x378 - irq 0x70 = 7 - end - device pnp 2e.2 on # Com1 - io 0x60 = 0x3f8 - irq 0x70 = 4 - end - device pnp 2e.3 on # Com2 - io 0x60 = 0x2f8 - irq 0x70 = 3 - end - device pnp 2e.5 on # Keyboard - io 0x60 = 0x60 - io 0x62 = 0x64 - irq 0x70 = 1 - irq 0x72 = 12 - end - device pnp 2e.6 off # SFI - io 0x62 = 0x100 - end - device pnp 2e.7 off # GPIO_GAME_MIDI - io 0x60 = 0x220 - io 0x62 = 0x300 - irq 0x70 = 9 - end - device pnp 2e.8 off end # WDTO_PLED - device pnp 2e.9 off end # GPIO_SUSLED - device pnp 2e.a off end # ACPI - device pnp 2e.b on # HW Monitor - io 0x60 = 0x290 - irq 0x70 = 5 - end - end #superio/ite/it8721f - end # LPC host controller [1002:439d] - device pci 14.4 off end # PCIB 0x4384, NOTE: PCI interface pins shared with GPIO {GPIO 35:0} - device pci 14.5 on end # USB 2 - device pci 14.6 off end # Gec - device pci 15.0 on end # PCIe 0 - device pci 15.1 on end # PCIe 1 - device pci 15.2 on end # PCIe 2 - device pci 15.3 on end # PCIe 3 - device pci 16.0 on end # USB - device pci 16.2 on end # USB - #register "gpp_configuration" = "0" #4:0:0:0 - #register "gpp_configuration" = "2" #2:2:0:0 - #register "gpp_configuration" = "3" #2:1:1:0 - register "gpp_configuration" = "4" #1:1:1:1 - register "boot_switch_sata_ide" = "0" # 0: boot from SATA. 1: IDE - end #southbridge/amd/cimx/sb800 - end # device pci 18.0 - - device pci 18.1 on end - device pci 18.2 on end - device pci 18.3 on end - device pci 18.4 on end - end - end #domain -end diff --git a/src/mainboard/asus/m5a88-v/dsdt.asl b/src/mainboard/asus/m5a88-v/dsdt.asl deleted file mode 100644 index 3d2a781a9a..0000000000 --- a/src/mainboard/asus/m5a88-v/dsdt.asl +++ /dev/null @@ -1,1619 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -/* DefinitionBlock Statement */ -#include -DefinitionBlock ( - "DSDT.AML", /* Output filename */ - "DSDT", /* Signature */ - 0x02, /* DSDT Revision, needs to be 2 for 64bit */ - OEM_ID, - ACPI_TABLE_CREATOR, - 0x00010001 /* OEM Revision */ - ) -{ /* Start of ASL file */ - /* #include */ /* Include global debug methods if needed */ - - /* Data to be patched by the BIOS during POST */ - /* FIXME the patching is not done yet! */ - /* Memory related values */ - Name(LOMH, 0x0) /* Start of unused memory in C0000-E0000 range */ - Name(PBAD, 0x0) /* Address of BIOS area (If TOM2 != 0, Addr >> 16) */ - Name(PBLN, 0x0) /* Length of BIOS area */ - - Name(PCBA, 0xE0000000) /* Base address of PCIe config space */ - Name(HPBA, 0xFED00000) /* Base address of HPET table */ - - /* USB overcurrent mapping pins. */ - Name(UOM0, 0) - Name(UOM1, 2) - Name(UOM2, 0) - Name(UOM3, 7) - Name(UOM4, 2) - Name(UOM5, 2) - Name(UOM6, 6) - Name(UOM7, 2) - Name(UOM8, 6) - Name(UOM9, 6) - - /* Some global data */ - Name(OSVR, 3) /* Assume nothing. WinXp = 1, Vista = 2, Linux = 3, WinCE = 4 */ - Name(OSV, Ones) /* Assume nothing */ - Name(PMOD, One) /* Assume APIC */ - - /* - * Processor Object - * - */ - Scope (\_PR) { /* define processor scope */ - Device (CPU0) { - Name (_HID, "ACPI0007") - Name (_UID, 0) - #include "acpi/cpstate.asl" - } - Device (CPU1) { - Name (_HID, "ACPI0007") - Name (_UID, 1) - #include "acpi/cpstate.asl" - } - Device (CPU2) { - Name (_HID, "ACPI0007") - Name (_UID, 2) - #include "acpi/cpstate.asl" - } - Device (CPU3) { - Name (_HID, "ACPI0007") - Name (_UID, 3) - #include "acpi/cpstate.asl" - } - } /* End _PR scope */ - - /* PIC IRQ mapping registers, C00h-C01h. */ - OperationRegion(PRQM, SystemIO, 0x00000C00, 0x00000002) - Field(PRQM, ByteAcc, NoLock, Preserve) { - PRQI, 0x00000008, - PRQD, 0x00000008, /* Offset: 1h */ - } - IndexField(PRQI, PRQD, ByteAcc, NoLock, Preserve) { - PIRA, 0x00000008, /* Index 0 */ - PIRB, 0x00000008, /* Index 1 */ - PIRC, 0x00000008, /* Index 2 */ - PIRD, 0x00000008, /* Index 3 */ - PIRE, 0x00000008, /* Index 4 */ - PIRF, 0x00000008, /* Index 5 */ - PIRG, 0x00000008, /* Index 6 */ - PIRH, 0x00000008, /* Index 7 */ - } - - /* PCI Error control register */ - OperationRegion(PERC, SystemIO, 0x00000C14, 0x00000001) - Field(PERC, ByteAcc, NoLock, Preserve) { - SENS, 0x00000001, - PENS, 0x00000001, - SENE, 0x00000001, - PENE, 0x00000001, - } - - /* Client Management index/data registers */ - OperationRegion(CMT, SystemIO, 0x00000C50, 0x00000002) - Field(CMT, ByteAcc, NoLock, Preserve) { - CMTI, 8, - /* Client Management Data register */ - G64E, 1, - G64O, 1, - G32O, 2, - , 2, - GPSL, 2, - } - - /* GPM Port register */ - OperationRegion(GPT, SystemIO, 0x00000C52, 0x00000001) - Field(GPT, ByteAcc, NoLock, Preserve) { - GPB0,1, - GPB1,1, - GPB2,1, - GPB3,1, - GPB4,1, - GPB5,1, - GPB6,1, - GPB7,1, - } - - /* Flash ROM program enable register */ - OperationRegion(FRE, SystemIO, 0x00000C6F, 0x00000001) - Field(FRE, ByteAcc, NoLock, Preserve) { - , 0x00000006, - FLRE, 0x00000001, - } - - /* PM2 index/data registers */ - OperationRegion(PM2R, SystemIO, 0x00000CD0, 0x00000002) - Field(PM2R, ByteAcc, NoLock, Preserve) { - PM2I, 0x00000008, - PM2D, 0x00000008, - } - - /* Power Management I/O registers, TODO:PMIO is quite different in SB800. */ - OperationRegion(PIOR, SystemIO, 0x00000CD6, 0x00000002) - Field(PIOR, ByteAcc, NoLock, Preserve) { - PIOI, 0x00000008, - PIOD, 0x00000008, - } - IndexField (PIOI, PIOD, ByteAcc, NoLock, Preserve) { - Offset(0x00), /* MiscControl */ - , 1, - T1EE, 1, - T2EE, 1, - Offset(0x01), /* MiscStatus */ - , 1, - T1E, 1, - T2E, 1, - Offset(0x04), /* SmiWakeUpEventEnable3 */ - , 7, - SSEN, 1, - Offset(0x07), /* SmiWakeUpEventStatus3 */ - , 7, - CSSM, 1, - Offset(0x10), /* AcpiEnable */ - , 6, - PWDE, 1, - Offset(0x1C), /* ProgramIoEnable */ - , 3, - MKME, 1, - IO3E, 1, - IO2E, 1, - IO1E, 1, - IO0E, 1, - Offset(0x1D), /* IOMonitorStatus */ - , 3, - MKMS, 1, - IO3S, 1, - IO2S, 1, - IO1S, 1, - IO0S,1, - Offset(0x20), /* AcpiPmEvtBlk. TODO: should be 0x60 */ - APEB, 16, - Offset(0x36), /* GEvtLevelConfig */ - , 6, - ELC6, 1, - ELC7, 1, - Offset(0x37), /* GPMLevelConfig0 */ - , 3, - PLC0, 1, - PLC1, 1, - PLC2, 1, - PLC3, 1, - PLC8, 1, - Offset(0x38), /* GPMLevelConfig1 */ - , 1, - PLC4, 1, - PLC5, 1, - , 1, - PLC6, 1, - PLC7, 1, - Offset(0x3B), /* PMEStatus1 */ - GP0S, 1, - GM4S, 1, - GM5S, 1, - APS, 1, - GM6S, 1, - GM7S, 1, - GP2S, 1, - STSS, 1, - Offset(0x55), /* SoftPciRst */ - SPRE, 1, - , 1, - , 1, - PNAT, 1, - PWMK, 1, - PWNS, 1, - - /* Offset(0x61), */ /* Options_1 */ - /* ,7, */ - /* R617,1, */ - - Offset(0x65), /* UsbPMControl */ - , 4, - URRE, 1, - Offset(0x68), /* MiscEnable68 */ - , 3, - TMTE, 1, - , 1, - Offset(0x92), /* GEVENTIN */ - , 7, - E7IS, 1, - Offset(0x96), /* GPM98IN */ - G8IS, 1, - G9IS, 1, - Offset(0x9A), /* EnhanceControl */ - ,7, - HPDE, 1, - Offset(0xA8), /* PIO7654Enable */ - IO4E, 1, - IO5E, 1, - IO6E, 1, - IO7E, 1, - Offset(0xA9), /* PIO7654Status */ - IO4S, 1, - IO5S, 1, - IO6S, 1, - IO7S, 1, - } - - /* PM1 Event Block - * First word is PM1_Status, Second word is PM1_Enable - */ - OperationRegion(P1EB, SystemIO, APEB, 0x04) - Field(P1EB, ByteAcc, NoLock, Preserve) { - TMST, 1, - , 3, - BMST, 1, - GBST, 1, - Offset(0x01), - PBST, 1, - , 1, - RTST, 1, - , 3, - PWST, 1, - SPWS, 1, - Offset(0x02), - TMEN, 1, - , 4, - GBEN, 1, - Offset(0x03), - PBEN, 1, - , 1, - RTEN, 1, - , 3, - PWDA, 1, - } - - Scope(\_SB) { - /* PCIe Configuration Space for 16 busses */ - OperationRegion(PCFG, SystemMemory, PCBA, 0x01000000) /* Each bus consumes 1MB */ - Field(PCFG, ByteAcc, NoLock, Preserve) { - /* Byte offsets are computed using the following technique: - * ((bus number + 1) * ((device number * 8) * 4096)) + register offset - * The 8 comes from 8 functions per device, and 4096 bytes per function config space - */ - Offset(0x00088024), /* Byte offset to SATA register 24h - Bus 0, Device 17, Function 0 */ - STB5, 32, - Offset(0x00098042), /* Byte offset to OHCI0 register 42h - Bus 0, Device 19, Function 0 */ - PT0D, 1, - PT1D, 1, - PT2D, 1, - PT3D, 1, - PT4D, 1, - PT5D, 1, - PT6D, 1, - PT7D, 1, - PT8D, 1, - PT9D, 1, - Offset(0x000A0004), /* Byte offset to SMBUS register 4h - Bus 0, Device 20, Function 0 */ - SBIE, 1, - SBME, 1, - Offset(0x000A0008), /* Byte offset to SMBUS register 8h - Bus 0, Device 20, Function 0 */ - SBRI, 8, - Offset(0x000A0014), /* Byte offset to SMBUS register 14h - Bus 0, Device 20, Function 0 */ - SBB1, 32, - Offset(0x000A0078), /* Byte offset to SMBUS register 78h - Bus 0, Device 20, Function 0 */ - ,14, - P92E, 1, /* Port92 decode enable */ - } - - OperationRegion(SB5, SystemMemory, STB5, 0x1000) - Field(SB5, AnyAcc, NoLock, Preserve){ - /* Port 0 */ - Offset(0x120), /* Port 0 Task file status */ - P0ER, 1, - , 2, - P0DQ, 1, - , 3, - P0BY, 1, - Offset(0x128), /* Port 0 Serial ATA status */ - P0DD, 4, - , 4, - P0IS, 4, - Offset(0x12C), /* Port 0 Serial ATA control */ - P0DI, 4, - Offset(0x130), /* Port 0 Serial ATA error */ - , 16, - P0PR, 1, - - /* Port 1 */ - offset(0x1A0), /* Port 1 Task file status */ - P1ER, 1, - , 2, - P1DQ, 1, - , 3, - P1BY, 1, - Offset(0x1A8), /* Port 1 Serial ATA status */ - P1DD, 4, - , 4, - P1IS, 4, - Offset(0x1AC), /* Port 1 Serial ATA control */ - P1DI, 4, - Offset(0x1B0), /* Port 1 Serial ATA error */ - , 16, - P1PR, 1, - - /* Port 2 */ - Offset(0x220), /* Port 2 Task file status */ - P2ER, 1, - , 2, - P2DQ, 1, - , 3, - P2BY, 1, - Offset(0x228), /* Port 2 Serial ATA status */ - P2DD, 4, - , 4, - P2IS, 4, - Offset(0x22C), /* Port 2 Serial ATA control */ - P2DI, 4, - Offset(0x230), /* Port 2 Serial ATA error */ - , 16, - P2PR, 1, - - /* Port 3 */ - Offset(0x2A0), /* Port 3 Task file status */ - P3ER, 1, - , 2, - P3DQ, 1, - , 3, - P3BY, 1, - Offset(0x2A8), /* Port 3 Serial ATA status */ - P3DD, 4, - , 4, - P3IS, 4, - Offset(0x2AC), /* Port 3 Serial ATA control */ - P3DI, 4, - Offset(0x2B0), /* Port 3 Serial ATA error */ - , 16, - P3PR, 1, - } - } - - - #include "acpi/routing.asl" - - Scope(\_SB) { - - Method(OSFL, 0){ - - if(LNotEqual(OSVR, Ones)) {Return(OSVR)} /* OS version was already detected */ - - if(CondRefOf(\_OSI)) - { - Store(1, OSVR) /* Assume some form of XP */ - if (\_OSI("Windows 2006")) /* Vista */ - { - Store(2, OSVR) - } - } else { - If(WCMP(\_OS,"Linux")) { - Store(3, OSVR) /* Linux */ - } Else { - Store(4, OSVR) /* Gotta be WinCE */ - } - } - Return(OSVR) - } - - Method(_PIC, 0x01, NotSerialized) - { - If (Arg0) - { - \_SB.CIRQ() - } - Store(Arg0, PMOD) - } - Method(CIRQ, 0x00, NotSerialized){ - Store(0, PIRA) - Store(0, PIRB) - Store(0, PIRC) - Store(0, PIRD) - Store(0, PIRE) - Store(0, PIRF) - Store(0, PIRG) - Store(0, PIRH) - } - - Name(IRQB, ResourceTemplate(){ - IRQ(Level,ActiveLow,Shared){15} - }) - - Name(IRQP, ResourceTemplate(){ - IRQ(Level,ActiveLow,Exclusive){3, 4, 5, 7, 10, 11, 12, 15} - }) - - Name(PITF, ResourceTemplate(){ - IRQ(Level,ActiveLow,Exclusive){9} - }) - - Device(INTA) { - Name(_HID, EISAID("PNP0C0F")) - Name(_UID, 1) - - Method(_STA, 0) { - if (PIRA) { - Return(0x0B) /* sata is invisible */ - } else { - Return(0x09) /* sata is disabled */ - } - } /* End Method(_SB.INTA._STA) */ - - Method(_DIS ,0) { - /* DBGO("\\_SB\\LNKA\\_DIS\n") */ - Store(0, PIRA) - } /* End Method(_SB.INTA._DIS) */ - - Method(_PRS ,0) { - /* DBGO("\\_SB\\LNKA\\_PRS\n") */ - Return(IRQP) - } /* Method(_SB.INTA._PRS) */ - - Method(_CRS ,0) { - /* DBGO("\\_SB\\LNKA\\_CRS\n") */ - CreateWordField(IRQB, 0x1, IRQN) - ShiftLeft(1, PIRA, IRQN) - Return(IRQB) - } /* Method(_SB.INTA._CRS) */ - - Method(_SRS, 1) { - /* DBGO("\\_SB\\LNKA\\_CRS\n") */ - CreateWordField(ARG0, 1, IRQM) - - /* Use lowest available IRQ */ - FindSetRightBit(IRQM, Local0) - if (Local0) { - Decrement(Local0) - } - Store(Local0, PIRA) - } /* End Method(_SB.INTA._SRS) */ - } /* End Device(INTA) */ - - Device(INTB) { - Name(_HID, EISAID("PNP0C0F")) - Name(_UID, 2) - - Method(_STA, 0) { - if (PIRB) { - Return(0x0B) /* sata is invisible */ - } else { - Return(0x09) /* sata is disabled */ - } - } /* End Method(_SB.INTB._STA) */ - - Method(_DIS ,0) { - /* DBGO("\\_SB\\LNKB\\_DIS\n") */ - Store(0, PIRB) - } /* End Method(_SB.INTB._DIS) */ - - Method(_PRS ,0) { - /* DBGO("\\_SB\\LNKB\\_PRS\n") */ - Return(IRQP) - } /* Method(_SB.INTB._PRS) */ - - Method(_CRS ,0) { - /* DBGO("\\_SB\\LNKB\\_CRS\n") */ - CreateWordField(IRQB, 0x1, IRQN) - ShiftLeft(1, PIRB, IRQN) - Return(IRQB) - } /* Method(_SB.INTB._CRS) */ - - Method(_SRS, 1) { - /* DBGO("\\_SB\\LNKB\\_CRS\n") */ - CreateWordField(ARG0, 1, IRQM) - - /* Use lowest available IRQ */ - FindSetRightBit(IRQM, Local0) - if (Local0) { - Decrement(Local0) - } - Store(Local0, PIRB) - } /* End Method(_SB.INTB._SRS) */ - } /* End Device(INTB) */ - - Device(INTC) { - Name(_HID, EISAID("PNP0C0F")) - Name(_UID, 3) - - Method(_STA, 0) { - if (PIRC) { - Return(0x0B) /* sata is invisible */ - } else { - Return(0x09) /* sata is disabled */ - } - } /* End Method(_SB.INTC._STA) */ - - Method(_DIS ,0) { - /* DBGO("\\_SB\\LNKC\\_DIS\n") */ - Store(0, PIRC) - } /* End Method(_SB.INTC._DIS) */ - - Method(_PRS ,0) { - /* DBGO("\\_SB\\LNKC\\_PRS\n") */ - Return(IRQP) - } /* Method(_SB.INTC._PRS) */ - - Method(_CRS ,0) { - /* DBGO("\\_SB\\LNKC\\_CRS\n") */ - CreateWordField(IRQB, 0x1, IRQN) - ShiftLeft(1, PIRC, IRQN) - Return(IRQB) - } /* Method(_SB.INTC._CRS) */ - - Method(_SRS, 1) { - /* DBGO("\\_SB\\LNKC\\_CRS\n") */ - CreateWordField(ARG0, 1, IRQM) - - /* Use lowest available IRQ */ - FindSetRightBit(IRQM, Local0) - if (Local0) { - Decrement(Local0) - } - Store(Local0, PIRC) - } /* End Method(_SB.INTC._SRS) */ - } /* End Device(INTC) */ - - Device(INTD) { - Name(_HID, EISAID("PNP0C0F")) - Name(_UID, 4) - - Method(_STA, 0) { - if (PIRD) { - Return(0x0B) /* sata is invisible */ - } else { - Return(0x09) /* sata is disabled */ - } - } /* End Method(_SB.INTD._STA) */ - - Method(_DIS ,0) { - /* DBGO("\\_SB\\LNKD\\_DIS\n") */ - Store(0, PIRD) - } /* End Method(_SB.INTD._DIS) */ - - Method(_PRS ,0) { - /* DBGO("\\_SB\\LNKD\\_PRS\n") */ - Return(IRQP) - } /* Method(_SB.INTD._PRS) */ - - Method(_CRS ,0) { - /* DBGO("\\_SB\\LNKD\\_CRS\n") */ - CreateWordField(IRQB, 0x1, IRQN) - ShiftLeft(1, PIRD, IRQN) - Return(IRQB) - } /* Method(_SB.INTD._CRS) */ - - Method(_SRS, 1) { - /* DBGO("\\_SB\\LNKD\\_CRS\n") */ - CreateWordField(ARG0, 1, IRQM) - - /* Use lowest available IRQ */ - FindSetRightBit(IRQM, Local0) - if (Local0) { - Decrement(Local0) - } - Store(Local0, PIRD) - } /* End Method(_SB.INTD._SRS) */ - } /* End Device(INTD) */ - - Device(INTE) { - Name(_HID, EISAID("PNP0C0F")) - Name(_UID, 5) - - Method(_STA, 0) { - if (PIRE) { - Return(0x0B) /* sata is invisible */ - } else { - Return(0x09) /* sata is disabled */ - } - } /* End Method(_SB.INTE._STA) */ - - Method(_DIS ,0) { - /* DBGO("\\_SB\\LNKE\\_DIS\n") */ - Store(0, PIRE) - } /* End Method(_SB.INTE._DIS) */ - - Method(_PRS ,0) { - /* DBGO("\\_SB\\LNKE\\_PRS\n") */ - Return(IRQP) - } /* Method(_SB.INTE._PRS) */ - - Method(_CRS ,0) { - /* DBGO("\\_SB\\LNKE\\_CRS\n") */ - CreateWordField(IRQB, 0x1, IRQN) - ShiftLeft(1, PIRE, IRQN) - Return(IRQB) - } /* Method(_SB.INTE._CRS) */ - - Method(_SRS, 1) { - /* DBGO("\\_SB\\LNKE\\_CRS\n") */ - CreateWordField(ARG0, 1, IRQM) - - /* Use lowest available IRQ */ - FindSetRightBit(IRQM, Local0) - if (Local0) { - Decrement(Local0) - } - Store(Local0, PIRE) - } /* End Method(_SB.INTE._SRS) */ - } /* End Device(INTE) */ - - Device(INTF) { - Name(_HID, EISAID("PNP0C0F")) - Name(_UID, 6) - - Method(_STA, 0) { - if (PIRF) { - Return(0x0B) /* sata is invisible */ - } else { - Return(0x09) /* sata is disabled */ - } - } /* End Method(_SB.INTF._STA) */ - - Method(_DIS ,0) { - /* DBGO("\\_SB\\LNKF\\_DIS\n") */ - Store(0, PIRF) - } /* End Method(_SB.INTF._DIS) */ - - Method(_PRS ,0) { - /* DBGO("\\_SB\\LNKF\\_PRS\n") */ - Return(PITF) - } /* Method(_SB.INTF._PRS) */ - - Method(_CRS ,0) { - /* DBGO("\\_SB\\LNKF\\_CRS\n") */ - CreateWordField(IRQB, 0x1, IRQN) - ShiftLeft(1, PIRF, IRQN) - Return(IRQB) - } /* Method(_SB.INTF._CRS) */ - - Method(_SRS, 1) { - /* DBGO("\\_SB\\LNKF\\_CRS\n") */ - CreateWordField(ARG0, 1, IRQM) - - /* Use lowest available IRQ */ - FindSetRightBit(IRQM, Local0) - if (Local0) { - Decrement(Local0) - } - Store(Local0, PIRF) - } /* End Method(_SB.INTF._SRS) */ - } /* End Device(INTF) */ - - Device(INTG) { - Name(_HID, EISAID("PNP0C0F")) - Name(_UID, 7) - - Method(_STA, 0) { - if (PIRG) { - Return(0x0B) /* sata is invisible */ - } else { - Return(0x09) /* sata is disabled */ - } - } /* End Method(_SB.INTG._STA) */ - - Method(_DIS ,0) { - /* DBGO("\\_SB\\LNKG\\_DIS\n") */ - Store(0, PIRG) - } /* End Method(_SB.INTG._DIS) */ - - Method(_PRS ,0) { - /* DBGO("\\_SB\\LNKG\\_PRS\n") */ - Return(IRQP) - } /* Method(_SB.INTG._CRS) */ - - Method(_CRS ,0) { - /* DBGO("\\_SB\\LNKG\\_CRS\n") */ - CreateWordField(IRQB, 0x1, IRQN) - ShiftLeft(1, PIRG, IRQN) - Return(IRQB) - } /* Method(_SB.INTG._CRS) */ - - Method(_SRS, 1) { - /* DBGO("\\_SB\\LNKG\\_CRS\n") */ - CreateWordField(ARG0, 1, IRQM) - - /* Use lowest available IRQ */ - FindSetRightBit(IRQM, Local0) - if (Local0) { - Decrement(Local0) - } - Store(Local0, PIRG) - } /* End Method(_SB.INTG._SRS) */ - } /* End Device(INTG) */ - - Device(INTH) { - Name(_HID, EISAID("PNP0C0F")) - Name(_UID, 8) - - Method(_STA, 0) { - if (PIRH) { - Return(0x0B) /* sata is invisible */ - } else { - Return(0x09) /* sata is disabled */ - } - } /* End Method(_SB.INTH._STA) */ - - Method(_DIS ,0) { - /* DBGO("\\_SB\\LNKH\\_DIS\n") */ - Store(0, PIRH) - } /* End Method(_SB.INTH._DIS) */ - - Method(_PRS ,0) { - /* DBGO("\\_SB\\LNKH\\_PRS\n") */ - Return(IRQP) - } /* Method(_SB.INTH._CRS) */ - - Method(_CRS ,0) { - /* DBGO("\\_SB\\LNKH\\_CRS\n") */ - CreateWordField(IRQB, 0x1, IRQN) - ShiftLeft(1, PIRH, IRQN) - Return(IRQB) - } /* Method(_SB.INTH._CRS) */ - - Method(_SRS, 1) { - /* DBGO("\\_SB\\LNKH\\_CRS\n") */ - CreateWordField(ARG0, 1, IRQM) - - /* Use lowest available IRQ */ - FindSetRightBit(IRQM, Local0) - if (Local0) { - Decrement(Local0) - } - Store(Local0, PIRH) - } /* End Method(_SB.INTH._SRS) */ - } /* End Device(INTH) */ - - } /* End Scope(_SB) */ - - #include - - /* Wake status package */ - Name(WKST,Package(){Zero, Zero}) - - /* - * \_PTS - Prepare to Sleep method - * - * Entry: - * Arg0=The value of the sleeping state S1=1, S2=2, etc - * - * Exit: - * -none- - * - * The _PTS control method is executed at the beginning of the sleep process - * for S1-S5. The sleeping value is passed to the _PTS control method. This - * control method may be executed a relatively long time before entering the - * sleep state and the OS may abort the operation without notification to - * the ACPI driver. This method cannot modify the configuration or power - * state of any device in the system. - */ - Method(\_PTS, 1) { - /* DBGO("\\_PTS\n") */ - /* DBGO("From S0 to S") */ - /* DBGO(Arg0) */ - /* DBGO("\n") */ - - /* Don't allow PCIRST# to reset USB */ - if (LEqual(Arg0,3)){ - Store(0,URRE) - } - - /* Clear sleep SMI status flag and enable sleep SMI trap. */ - /*Store(One, CSSM) - Store(One, SSEN)*/ - - /* On older chips, clear PciExpWakeDisEn */ - /*if (LLessEqual(\_SB.SBRI, 0x13)) { - * Store(0,\_SB.PWDE) - *} - */ - - /* Clear wake status structure. */ - Store(0, Index(WKST,0)) - Store(0, Index(WKST,1)) - } /* End Method(\_PTS) */ - - /* - * The following method results in a "not a valid reserved NameSeg" - * warning so I have commented it out for the duration. It isn't - * used, so it could be removed. - * - * - * \_GTS OEM Going To Sleep method - * - * Entry: - * Arg0=The value of the sleeping state S1=1, S2=2 - * - * Exit: - * -none- - * - * Method(\_GTS, 1) { - * DBGO("\\_GTS\n") - * DBGO("From S0 to S") - * DBGO(Arg0) - * DBGO("\n") - * } - */ - - /* - * \_BFS OEM Back From Sleep method - * - * Entry: - * Arg0=The value of the sleeping state S1=1, S2=2 - * - * Exit: - * -none- - */ - Method(\_BFS, 1) { - /* DBGO("\\_BFS\n") */ - /* DBGO("From S") */ - /* DBGO(Arg0) */ - /* DBGO(" to S0\n") */ - } - - /* - * \_WAK System Wake method - * - * Entry: - * Arg0=The value of the sleeping state S1=1, S2=2 - * - * Exit: - * Return package of 2 DWords - * Dword 1 - Status - * 0x00000000 wake succeeded - * 0x00000001 Wake was signaled but failed due to lack of power - * 0x00000002 Wake was signaled but failed due to thermal condition - * Dword 2 - Power Supply state - * if non-zero the effective S-state the power supply entered - */ - Method(\_WAK, 1) { - /* DBGO("\\_WAK\n") */ - /* DBGO("From S") */ - /* DBGO(Arg0) */ - /* DBGO(" to S0\n") */ - - /* Re-enable HPET */ - Store(1,HPDE) - - /* Restore PCIRST# so it resets USB */ - if (LEqual(Arg0,3)){ - Store(1,URRE) - } - - /* Arbitrarily clear PciExpWakeStatus */ - Store(PWST, Local1) - Store(Local1, PWST) - - /* if (DeRefOf(Index(WKST,0))) { - * Store(0, Index(WKST,1)) - * } else { - * Store(Arg0, Index(WKST,1)) - * } - */ - Return(WKST) - } /* End Method(\_WAK) */ - - Scope(\_GPE) { /* Start Scope GPE */ - /* General event 0 */ - /* Method(_L00) { - * DBGO("\\_GPE\\_L00\n") - * } - */ - - /* General event 1 */ - /* Method(_L01) { - * DBGO("\\_GPE\\_L00\n") - * } - */ - - /* General event 2 */ - /* Method(_L02) { - * DBGO("\\_GPE\\_L00\n") - * } - */ - - /* General event 3 */ - Method(_L03) { - /* DBGO("\\_GPE\\_L00\n") */ - Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ - } - - /* General event 4 */ - /* Method(_L04) { - * DBGO("\\_GPE\\_L00\n") - * } - */ - - /* General event 5 */ - /* Method(_L05) { - * DBGO("\\_GPE\\_L00\n") - * } - */ - - /* General event 6 - Used for GPM6, moved to USB.asl */ - /* Method(_L06) { - * DBGO("\\_GPE\\_L00\n") - * } - */ - - /* General event 7 - Used for GPM7, moved to USB.asl */ - /* Method(_L07) { - * DBGO("\\_GPE\\_L07\n") - * } - */ - - /* Legacy PM event */ - Method(_L08) { - /* DBGO("\\_GPE\\_L08\n") */ - } - - /* Temp warning (TWarn) event */ - Method(_L09) { - /* DBGO("\\_GPE\\_L09\n") */ - /* Notify (\_TZ.TZ00, 0x80) */ - } - - /* Reserved */ - /* Method(_L0A) { - * DBGO("\\_GPE\\_L0A\n") - * } - */ - - /* USB controller PME# */ - Method(_L0B) { - /* DBGO("\\_GPE\\_L0B\n") */ - Notify(\_SB.PCI0.UOH1, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(\_SB.PCI0.UOH2, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(\_SB.PCI0.UOH3, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(\_SB.PCI0.UOH4, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(\_SB.PCI0.UOH5, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(\_SB.PCI0.UOH6, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(\_SB.PCI0.UEH1, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ - } - - /* AC97 controller PME# */ - /* Method(_L0C) { - * DBGO("\\_GPE\\_L0C\n") - * } - */ - - /* OtherTherm PME# */ - /* Method(_L0D) { - * DBGO("\\_GPE\\_L0D\n") - * } - */ - - /* GPM9 SCI event - Moved to USB.asl */ - /* Method(_L0E) { - * DBGO("\\_GPE\\_L0E\n") - * } - */ - - /* PCIe HotPlug event */ - /* Method(_L0F) { - * DBGO("\\_GPE\\_L0F\n") - * } - */ - - /* ExtEvent0 SCI event */ - Method(_L10) { - /* DBGO("\\_GPE\\_L10\n") */ - } - - - /* ExtEvent1 SCI event */ - Method(_L11) { - /* DBGO("\\_GPE\\_L11\n") */ - } - - /* PCIe PME# event */ - /* Method(_L12) { - * DBGO("\\_GPE\\_L12\n") - * } - */ - - /* GPM0 SCI event - Moved to USB.asl */ - /* Method(_L13) { - * DBGO("\\_GPE\\_L13\n") - * } - */ - - /* GPM1 SCI event - Moved to USB.asl */ - /* Method(_L14) { - * DBGO("\\_GPE\\_L14\n") - * } - */ - - /* GPM2 SCI event - Moved to USB.asl */ - /* Method(_L15) { - * DBGO("\\_GPE\\_L15\n") - * } - */ - - /* GPM3 SCI event - Moved to USB.asl */ - /* Method(_L16) { - * DBGO("\\_GPE\\_L16\n") - * } - */ - - /* GPM8 SCI event - Moved to USB.asl */ - /* Method(_L17) { - * DBGO("\\_GPE\\_L17\n") - * } - */ - - /* GPIO0 or GEvent8 event */ - Method(_L18) { - /* DBGO("\\_GPE\\_L18\n") */ - Notify(\_SB.PCI0.PBR2, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(\_SB.PCI0.PBR4, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(\_SB.PCI0.PBR5, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(\_SB.PCI0.PBR6, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(\_SB.PCI0.PBR7, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ - } - - /* GPM4 SCI event - Moved to USB.asl */ - /* Method(_L19) { - * DBGO("\\_GPE\\_L19\n") - * } - */ - - /* GPM5 SCI event - Moved to USB.asl */ - /* Method(_L1A) { - * DBGO("\\_GPE\\_L1A\n") - * } - */ - - /* Azalia SCI event */ - Method(_L1B) { - /* DBGO("\\_GPE\\_L1B\n") */ - Notify(\_SB.PCI0.AZHD, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ - } - - /* GPM6 SCI event - Reassigned to _L06 */ - /* Method(_L1C) { - * DBGO("\\_GPE\\_L1C\n") - * } - */ - - /* GPM7 SCI event - Reassigned to _L07 */ - /* Method(_L1D) { - * DBGO("\\_GPE\\_L1D\n") - * } - */ - - /* GPIO2 or GPIO66 SCI event */ - /* Method(_L1E) { - * DBGO("\\_GPE\\_L1E\n") - * } - */ - - /* SATA SCI event - Moved to sata.asl */ - /* Method(_L1F) { - * DBGO("\\_GPE\\_L1F\n") - * } - */ - - } /* End Scope GPE */ - - #include "acpi/usb.asl" - - /* System Bus */ - Scope(\_SB) { /* Start \_SB scope */ - #include /* global utility methods expected within the \_SB scope */ - - /* _SB.PCI0 */ - /* Note: Only need HID on Primary Bus */ - Device(PCI0) { - External (TOM1) - External (TOM2) - Name(_HID, EISAID("PNP0A03")) - Name(_ADR, 0x00180000) /* Dev# = BSP Dev#, Func# = 0 */ - Method(_BBN, 0) { /* Bus number = 0 */ - Return(0) - } - Method(_STA, 0) { - /* DBGO("\\_SB\\PCI0\\_STA\n") */ - Return(0x0B) /* Status is visible */ - } - - Method(_PRT,0) { - If(PMOD){ Return(APR0) } /* APIC mode */ - Return (PR0) /* PIC Mode */ - } /* end _PRT */ - - /* Describe the Northbridge devices */ - Device(AMRT) { - Name(_ADR, 0x00000000) - } /* end AMRT */ - - /* The internal GFX bridge */ - Device(AGPB) { - Name(_ADR, 0x00010000) - Name(_PRW, Package() {0x18, 4}) - Method(_PRT,0) { - Return (APR1) - } - } /* end AGPB */ - - /* The external GFX bridge */ - Device(PBR2) { - Name(_ADR, 0x00020000) - Name(_PRW, Package() {0x18, 4}) - Method(_PRT,0) { - If(PMOD){ Return(APS2) } /* APIC mode */ - Return (PS2) /* PIC Mode */ - } /* end _PRT */ - } /* end PBR2 */ - - /* Dev3 is also an external GFX bridge, not used in Herring */ - - Device(PBR4) { - Name(_ADR, 0x00040000) - Name(_PRW, Package() {0x18, 4}) - Method(_PRT,0) { - If(PMOD){ Return(APS4) } /* APIC mode */ - Return (PS4) /* PIC Mode */ - } /* end _PRT */ - } /* end PBR4 */ - - Device(PBR5) { - Name(_ADR, 0x00050000) - Name(_PRW, Package() {0x18, 4}) - Method(_PRT,0) { - If(PMOD){ Return(APS5) } /* APIC mode */ - Return (PS5) /* PIC Mode */ - } /* end _PRT */ - } /* end PBR5 */ - - Device(PBR6) { - Name(_ADR, 0x00060000) - Name(_PRW, Package() {0x18, 4}) - Method(_PRT,0) { - If(PMOD){ Return(APS6) } /* APIC mode */ - Return (PS6) /* PIC Mode */ - } /* end _PRT */ - } /* end PBR6 */ - - /* The onboard EtherNet chip */ - Device(PBR7) { - Name(_ADR, 0x00070000) - Name(_PRW, Package() {0x18, 4}) - Method(_PRT,0) { - If(PMOD){ Return(APS7) } /* APIC mode */ - Return (PS7) /* PIC Mode */ - } /* end _PRT */ - } /* end PBR7 */ - - /* GPP */ - Device(PBR9) { - Name(_ADR, 0x00090000) - Name(_PRW, Package() {0x18, 4}) - Method(_PRT,0) { - If(PMOD){ Return(APS9) } /* APIC mode */ - Return (PS9) /* PIC Mode */ - } /* end _PRT */ - } /* end PBR9 */ - - Device(PBRa) { - Name(_ADR, 0x000A0000) - Name(_PRW, Package() {0x18, 4}) - Method(_PRT,0) { - If(PMOD){ Return(APSa) } /* APIC mode */ - Return (PSa) /* PIC Mode */ - } /* end _PRT */ - } /* end PBRa */ - - Device(PE20) { - Name(_ADR, 0x00150000) - Name(_PRW, Package() {0x18, 4}) - Method(_PRT,0) { - If(PMOD){ Return(APE0) } /* APIC mode */ - Return (PE0) /* PIC Mode */ - } /* end _PRT */ - } /* end PE20 */ - Device(PE21) { - Name(_ADR, 0x00150001) - Name(_PRW, Package() {0x18, 4}) - Method(_PRT,0) { - If(PMOD){ Return(APE1) } /* APIC mode */ - Return (PE1) /* PIC Mode */ - } /* end _PRT */ - } /* end PE21 */ - Device(PE22) { - Name(_ADR, 0x00150002) - Name(_PRW, Package() {0x18, 4}) - Method(_PRT,0) { - If(PMOD){ Return(APE2) } /* APIC mode */ - Return (APE2) /* PIC Mode */ - } /* end _PRT */ - } /* end PE22 */ - Device(PE23) { - Name(_ADR, 0x00150003) - Name(_PRW, Package() {0x18, 4}) - Method(_PRT,0) { - If(PMOD){ Return(APE3) } /* APIC mode */ - Return (PE3) /* PIC Mode */ - } /* end _PRT */ - } /* end PE23 */ - - /* PCI slot 1, 2, 3 */ - Device(PIBR) { - Name(_ADR, 0x00140004) - Name(_PRW, Package() {0x18, 4}) - - Method(_PRT, 0) { - Return (PCIB) - } - } - - /* Describe the Southbridge devices */ - Device(STCR) { - Name(_ADR, 0x00110000) - #include "acpi/sata.asl" - } /* end STCR */ - - Device(UOH1) { - Name(_ADR, 0x00120000) - Name(_PRW, Package() {0x0B, 3}) - } /* end UOH1 */ - - Device(UOH2) { - Name(_ADR, 0x00120002) - Name(_PRW, Package() {0x0B, 3}) - } /* end UOH2 */ - - Device(UOH3) { - Name(_ADR, 0x00130000) - Name(_PRW, Package() {0x0B, 3}) - } /* end UOH3 */ - - Device(UOH4) { - Name(_ADR, 0x00130002) - Name(_PRW, Package() {0x0B, 3}) - } /* end UOH4 */ - - Device(UOH5) { - Name(_ADR, 0x00160000) - Name(_PRW, Package() {0x0B, 3}) - } /* end UOH5 */ - - Device(UOH6) { - Name(_ADR, 0x00160002) - Name(_PRW, Package() {0x0B, 3}) - } /* end UOH5 */ - - Device(UEH1) { - Name(_ADR, 0x00140005) - Name(_PRW, Package() {0x0B, 3}) - } /* end UEH1 */ - - Device(SBUS) { - Name(_ADR, 0x00140000) - } /* end SBUS */ - - /* Primary (and only) IDE channel */ - Device(IDEC) { - Name(_ADR, 0x00140001) - #include "acpi/ide.asl" - } /* end IDEC */ - - Device(AZHD) { - Name(_ADR, 0x00140002) - OperationRegion(AZPD, PCI_Config, 0x00, 0x100) - Field(AZPD, AnyAcc, NoLock, Preserve) { - offset (0x42), - NSDI, 1, - NSDO, 1, - NSEN, 1, - offset (0x44), - IPCR, 4, - offset (0x54), - PWST, 2, - , 6, - PMEB, 1, - , 6, - PMST, 1, - offset (0x62), - MMCR, 1, - offset (0x64), - MMLA, 32, - offset (0x68), - MMHA, 32, - offset (0x6C), - MMDT, 16, - } - - Method(_INI) { - If(LEqual(OSVR,3)){ /* If we are running Linux */ - Store(zero, NSEN) - Store(one, NSDO) - Store(one, NSDI) - } - } - } /* end AZHD */ - - Device(LIBR) { - Name(_ADR, 0x00140003) - /* Method(_INI) { - * DBGO("\\_SB\\PCI0\\LpcIsaBr\\_INI\n") - } */ /* End Method(_SB.SBRDG._INI) */ - - /* Real Time Clock Device */ - Device(RTC0) { - Name(_HID, EISAID("PNP0B01")) /* AT Real Time Clock */ - Name(_CRS, ResourceTemplate() { - IRQNoFlags(){8} - IO(Decode16,0x0070, 0x0070, 0, 2) - /* IO(Decode16,0x0070, 0x0070, 0, 4) */ - }) - } /* End Device(_SB.PCI0.LpcIsaBr.RTC0) */ - - Device(TMR) { /* Timer */ - Name(_HID,EISAID("PNP0100")) /* System Timer */ - Name(_CRS, ResourceTemplate() { - IRQNoFlags(){0} - IO(Decode16, 0x0040, 0x0040, 0, 4) - /* IO(Decode16, 0x0048, 0x0048, 0, 4) */ - }) - } /* End Device(_SB.PCI0.LpcIsaBr.TMR) */ - - Device(SPKR) { /* Speaker */ - Name(_HID,EISAID("PNP0800")) /* AT style speaker */ - Name(_CRS, ResourceTemplate() { - IO(Decode16, 0x0061, 0x0061, 0, 1) - }) - } /* End Device(_SB.PCI0.LpcIsaBr.SPKR) */ - - Device(PIC) { - Name(_HID,EISAID("PNP0000")) /* AT Interrupt Controller */ - Name(_CRS, ResourceTemplate() { - IRQNoFlags(){2} - IO(Decode16,0x0020, 0x0020, 0, 2) - IO(Decode16,0x00A0, 0x00A0, 0, 2) - /* IO(Decode16, 0x00D0, 0x00D0, 0x10, 0x02) */ - /* IO(Decode16, 0x04D0, 0x04D0, 0x10, 0x02) */ - }) - } /* End Device(_SB.PCI0.LpcIsaBr.PIC) */ - - Device(MAD) { /* 8257 DMA */ - Name(_HID,EISAID("PNP0200")) /* Hardware Device ID */ - Name(_CRS, ResourceTemplate() { - DMA(Compatibility,BusMaster,Transfer8){4} - IO(Decode16, 0x0000, 0x0000, 0x10, 0x10) - IO(Decode16, 0x0081, 0x0081, 0x00, 0x03) - IO(Decode16, 0x0087, 0x0087, 0x00, 0x01) - IO(Decode16, 0x0089, 0x0089, 0x00, 0x03) - IO(Decode16, 0x008F, 0x008F, 0x00, 0x01) - IO(Decode16, 0x00C0, 0x00C0, 0x10, 0x20) - }) /* End Name(_SB.PCI0.LpcIsaBr.MAD._CRS) */ - } /* End Device(_SB.PCI0.LpcIsaBr.MAD) */ - - Device(COPR) { - Name(_HID,EISAID("PNP0C04")) /* Math Coprocessor */ - Name(_CRS, ResourceTemplate() { - IO(Decode16, 0x00F0, 0x00F0, 0, 0x10) - IRQNoFlags(){13} - }) - } /* End Device(_SB.PCI0.LpcIsaBr.COPR) */ -#if 0 - Device(HPTM) { - Name(_HID,EISAID("PNP0103")) - Name(CRS,ResourceTemplate() { - Memory32Fixed(ReadOnly,0xFED00000, 0x00000400, HPT) /* 1kb reserved space */ - }) - Method(_STA, 0) { - Return(0x0F) /* sata is visible */ - } - Method(_CRS, 0) { - CreateDwordField(CRS, ^HPT._BAS, HPBX) - Store(HPBA, HPBX) - Return(CRS) - } - } /* End Device(_SB.PCI0.LpcIsaBr.COPR) */ -#endif - } /* end LIBR */ - - Device(HPBR) { - Name(_ADR, 0x00140004) - } /* end HostPciBr */ - - Device(ACAD) { - Name(_ADR, 0x00140005) - } /* end Ac97audio */ - - Device(ACMD) { - Name(_ADR, 0x00140006) - } /* end Ac97modem */ - - Name(CRES, ResourceTemplate() { - IO(Decode16, 0x0CF8, 0x0CF8, 1, 8) - - WORDIO(ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, - 0x0000, /* address granularity */ - 0x0000, /* range minimum */ - 0x0CF7, /* range maximum */ - 0x0000, /* translation */ - 0x0CF8 /* length */ - ) - - WORDIO(ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, - 0x0000, /* address granularity */ - 0x0D00, /* range minimum */ - 0xFFFF, /* range maximum */ - 0x0000, /* translation */ - 0xF300 /* length */ - ) -#if 0 - Memory32Fixed(READWRITE, 0, 0xA0000, BSMM) - Memory32Fixed(READONLY, 0x000A0000, 0x00020000, VGAM) /* VGA memory space */ - Memory32Fixed(READONLY, 0x000C0000, 0x00020000, EMM1) /* Assume C0000-E0000 empty */ - Memory32Fixed(READONLY, 0x000E0000, 0x00020000, RDBS) /* BIOS ROM area */ - - /* DRAM Memory from 1MB to TopMem */ - Memory32Fixed(READWRITE, 0x00100000, 0, DMLO) /* 1MB to TopMem */ - - /* BIOS space just below 4GB */ - DWORDMemory( - ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite, - 0x00, /* Granularity */ - 0x00000000, /* Min */ - 0x00000000, /* Max */ - 0x00000000, /* Translation */ - 0x00000000, /* Max-Min, RLEN */ - ,, - PCBM - ) - - /* DRAM memory from 4GB to TopMem2 */ - QWORDMemory(ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite, - 0xFFFFFFFF, /* Granularity */ - 0x00000000, /* Min */ - 0x00000000, /* Max */ - 0x00000000, /* Translation */ - 0x00000000, /* Max-Min, RLEN */ - ,, - DMHI - ) - - /* BIOS space just below 16EB */ - QWORDMemory(ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite, - 0xFFFFFFFF, /* Granularity */ - 0x00000000, /* Min */ - 0x00000000, /* Max */ - 0x00000000, /* Translation */ - 0x00000000, /* Max-Min, RLEN */ - ,, - PEBM - ) -#endif - /* memory space for PCI BARs below 4GB */ - Memory32Fixed(ReadOnly, 0x00000000, 0x00000000, MMIO) - }) /* End Name(_SB.PCI0.CRES) */ - - Method(_CRS, 0) { - /* DBGO("\\_SB\\PCI0\\_CRS\n") */ -#if 0 - CreateDWordField(CRES, ^EMM1._BAS, EM1B) - CreateDWordField(CRES, ^EMM1._LEN, EM1L) - CreateDWordField(CRES, ^DMLO._BAS, DMLB) - CreateDWordField(CRES, ^DMLO._LEN, DMLL) - CreateDWordField(CRES, ^PCBM._MIN, PBMB) - CreateDWordField(CRES, ^PCBM._LEN, PBML) - - CreateQWordField(CRES, ^DMHI._MIN, DMHB) - CreateQWordField(CRES, ^DMHI._LEN, DMHL) - CreateQWordField(CRES, ^PEBM._MIN, EBMB) - CreateQWordField(CRES, ^PEBM._LEN, EBML) - - If(LGreater(LOMH, 0xC0000)){ - Store(0xC0000, EM1B) /* Hole above C0000 and below E0000 */ - Subtract(LOMH, 0xC0000, EM1L) /* subtract start, assumes allocation from C0000 going up */ - } - - /* Set size of memory from 1MB to TopMem */ - Subtract(TOM1, 0x100000, DMLL) - - /* - * If(LNotEqual(TOM2, 0x00000000)){ - * Store(0x100000000,DMHB) DRAM from 4GB to TopMem2 - * Subtract(TOM2, 0x100000000, DMHL) - * } - */ - - /* If there is no memory above 4GB, put the BIOS just below 4GB */ - If(LEqual(TOM2, 0x00000000)){ - Store(PBAD,PBMB) /* Reserve the "BIOS" space */ - Store(PBLN,PBML) - } - Else { /* Otherwise, put the BIOS just below 16EB */ - ShiftLeft(PBAD,16,EBMB) /* Reserve the "BIOS" space */ - Store(PBLN,EBML) - } -#endif - CreateDWordField(CRES, ^MMIO._BAS, MM1B) - CreateDWordField(CRES, ^MMIO._LEN, MM1L) - /* - * Declare memory between TOM1 and 4GB as available - * for PCI MMIO. - * Use ShiftLeft to avoid 64bit constant (for XP). - * This will work even if the OS does 32bit arithmetic, as - * 32bit (0x00000000 - TOM1) will wrap and give the same - * result as 64bit (0x100000000 - TOM1). - */ - Store(TOM1, MM1B) - ShiftLeft(0x10000000, 4, Local0) - Subtract(Local0, TOM1, Local0) - Store(Local0, MM1L) - - Return(CRES) /* note to change the Name buffer */ - } /* end of Method(_SB.PCI0._CRS) */ - - /* - * - * FIRST METHOD CALLED UPON BOOT - * - * 1. If debugging, print current OS and ACPI interpreter. - * 2. Get PCI Interrupt routing from ACPI VSM, this - * value is based on user choice in BIOS setup. - */ - Method(_INI, 0) { - /* DBGO("\\_SB\\_INI\n") */ - /* DBGO(" DSDT.ASL code from ") */ - /* DBGO(__DATE__) */ - /* DBGO(" ") */ - /* DBGO(__TIME__) */ - /* DBGO("\n Sleep states supported: ") */ - /* DBGO("\n") */ - /* DBGO(" \\_OS=") */ - /* DBGO(\_OS) */ - /* DBGO("\n \\_REV=") */ - /* DBGO(\_REV) */ - /* DBGO("\n") */ - - /* Determine the OS we're running on */ - OSFL() - - /* On older chips, clear PciExpWakeDisEn */ - /*if (LLessEqual(\SBRI, 0x13)) { - * Store(0,\PWDE) - * } - */ - } /* End Method(_SB._INI) */ - } /* End Device(PCI0) */ - - Device(PWRB) { /* Start Power button device */ - Name(_HID, EISAID("PNP0C0C")) - Name(_UID, 0xAA) - Name(_PRW, Package () {3, 0x04}) /* wake from S1-S4 */ - Name(_STA, 0x0B) /* sata is invisible */ - } - } /* End \_SB scope */ - - Scope(\_SI) { - Method(_SST, 1) { - /* DBGO("\\_SI\\_SST\n") */ - /* DBGO(" New Indicator state: ") */ - /* DBGO(Arg0) */ - /* DBGO("\n") */ - } - } /* End Scope SI */ -} -/* End of ASL file */ diff --git a/src/mainboard/asus/m5a88-v/get_bus_conf.c b/src/mainboard/asus/m5a88-v/get_bus_conf.c deleted file mode 100644 index 6b5ae68bc6..0000000000 --- a/src/mainboard/asus/m5a88-v/get_bus_conf.c +++ /dev/null @@ -1,44 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include -#include -#include - -/* Global variables for MB layouts and these will be shared by irqtable mptable -* and acpi_tables busnum is default. -*/ -u32 apicid_sb800; - -void get_bus_conf(void) -{ - u32 apicid_base; - - get_default_pci1234(1); - - sysconf.sbdn = (sysconf.hcdn[0] & 0xff); - - - pirq_router_bus = (sysconf.pci1234[0] >> 16) & 0xff; - - /* I/O APICs: APIC ID Version State Address */ - if (CONFIG(LOGICAL_CPUS)) - apicid_base = get_apicid_base(1); - else - apicid_base = CONFIG_MAX_PHYSICAL_CPUS; - apicid_sb800 = apicid_base + 0; -} diff --git a/src/mainboard/asus/m5a88-v/irq_tables.c b/src/mainboard/asus/m5a88-v/irq_tables.c deleted file mode 100644 index a453c766bd..0000000000 --- a/src/mainboard/asus/m5a88-v/irq_tables.c +++ /dev/null @@ -1,101 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include -#include -#include -#include - -static void write_pirq_info(struct irq_info *pirq_info, u8 bus, u8 devfn, - u8 link0, u16 bitmap0, u8 link1, u16 bitmap1, - u8 link2, u16 bitmap2, u8 link3, u16 bitmap3, - u8 slot, u8 rfu) -{ - pirq_info->bus = bus; - pirq_info->devfn = devfn; - pirq_info->irq[0].link = link0; - pirq_info->irq[0].bitmap = bitmap0; - pirq_info->irq[1].link = link1; - pirq_info->irq[1].bitmap = bitmap1; - pirq_info->irq[2].link = link2; - pirq_info->irq[2].bitmap = bitmap2; - pirq_info->irq[3].link = link3; - pirq_info->irq[3].bitmap = bitmap3; - pirq_info->slot = slot; - pirq_info->rfu = rfu; -} - - -unsigned long write_pirq_routing_table(unsigned long addr) -{ - struct irq_routing_table *pirq; - struct irq_info *pirq_info; - u32 slot_num; - u8 *v; - - u8 sum = 0; - int i; - - /* Align the table to be 16 byte aligned. */ - addr += 15; - addr &= ~15; - - /* This table must be between 0xf0000 & 0x100000 */ - printk(BIOS_INFO, "Writing IRQ routing tables to 0x%lx...", addr); - - pirq = (void *)(addr); - v = (u8 *) (addr); - - pirq->signature = PIRQ_SIGNATURE; - pirq->version = PIRQ_VERSION; - - pirq->rtr_bus = pirq_router_bus; - pirq->rtr_devfn = PCI_DEVFN(0x14, 4); - - pirq->exclusive_irqs = 0; - - pirq->rtr_vendor = 0x1002; - pirq->rtr_device = 0x4384; - - pirq->miniport_data = 0; - - memset(pirq->rfu, 0, sizeof(pirq->rfu)); - - pirq_info = (void *)(&pirq->checksum + 1); - slot_num = 0; - - /* pci bridge */ - write_pirq_info(pirq_info, pirq_router_bus, PCI_DEVFN(0x14, 4), - 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, - 0); - pirq_info++; - slot_num++; - - pirq->size = 32 + 16 * slot_num; - - for (i = 0; i < pirq->size; i++) - sum += v[i]; - - sum = pirq->checksum - sum; - if (sum != pirq->checksum) { - pirq->checksum = sum; - } - - printk(BIOS_INFO, "write_pirq_routing_table done.\n"); - - return (unsigned long)pirq_info; -} diff --git a/src/mainboard/asus/m5a88-v/mainboard.c b/src/mainboard/asus/m5a88-v/mainboard.c deleted file mode 100644 index ee8ce5ea81..0000000000 --- a/src/mainboard/asus/m5a88-v/mainboard.c +++ /dev/null @@ -1,63 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 QingPei Wang - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include -#include -#include -#include - -/* GPIO6. */ -static void enable_int_gfx(void) -{ - volatile u8 *gpio_reg; - - /* make sure the MMIO(fed80000) is accessible */ - // FIXME: RWPMIO(SB_PMIOA_REG24, AccWidthUint8, ~(BIT0), BIT0); - - gpio_reg = (volatile u8 *)AMD_SB_ACPI_MMIO_ADDR + 0xD00; /* IoMux Register */ - - *(gpio_reg + 0x6) = 0x1; /* Int_vga_en */ - *(gpio_reg + 170) = 0x1; /* gpio_gate */ - - gpio_reg = (volatile u8 *)AMD_SB_ACPI_MMIO_ADDR + 0x100; /* GPIO Registers */ - - *(gpio_reg + 0x6) = 0x8; - *(gpio_reg + 170) = 0x0; -} - -int is_dev3_present(void) -{ - return 0; -} - - -/************************************************* -* enable the dedicated function in M5A88-V board. -* This function called early than rs780_enable. -*************************************************/ -static void mainboard_enable(struct device *dev) -{ - - printk(BIOS_INFO, "Mainboard ASUS M5A88-V Enable. dev=0x%p\n", dev); - - set_pcie_dereset(); - enable_int_gfx(); -} - -struct chip_operations mainboard_ops = { - .enable_dev = mainboard_enable, -}; diff --git a/src/mainboard/asus/m5a88-v/mptable.c b/src/mainboard/asus/m5a88-v/mptable.c deleted file mode 100644 index b4cd7e8589..0000000000 --- a/src/mainboard/asus/m5a88-v/mptable.c +++ /dev/null @@ -1,78 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include -#include -#include - -extern u32 apicid_sb800; - -u8 intr_data[] = { - [0x00] = 0x10,0x11,0x12,0x13,0x14,0x15,0x16,0x17, /* INTA# - INTH# */ - [0x08] = 0x00,0x00,0x00,0x00,0x1F,0x1F,0x1F,0x1F, /* Misc-nil,0,1,2, INT from Serial irq */ - [0x10] = 0x1F,0x1F,0x1F,0x10,0x1F,0x12,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, - 0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, - 0x12,0x11,0x12,0x11,0x12,0x11,0x12,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, - 0x11,0x13,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, - 0x10,0x11,0x12,0x13 -}; - -static void *smp_write_config_table(void *v) -{ - struct mp_config_table *mc; - int bus_isa; - u32 dword = 0; - u8 byte; - - mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); - - mptable_init(mc, LOCAL_APIC_ADDR); - - smp_write_processors(mc); - - mptable_write_buses(mc, NULL, &bus_isa); - - /* I/O APICs: APIC ID Version State Address */ - // FIXME: ReadPMIO(SB_PMIOA_REG34, AccWidthUint32, &dword); - dword &= 0xFFFFFFF0; - smp_write_ioapic(mc, apicid_sb800, 0x11,(void *) dword); - - for (byte = 0x0; byte < sizeof(intr_data); byte ++) { - outb(byte | 0x80, 0xC00); - outb(intr_data[byte], 0xC01); - } - - /* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ -#define IO_LOCAL_INT(type, intr, apicid, pin) \ - smp_write_intsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin)); - - mptable_add_isa_interrupts(mc, bus_isa, apicid_sb800, 0); - - /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ - IO_LOCAL_INT(mp_ExtINT, 0x0, MP_APIC_ALL, 0x0); - IO_LOCAL_INT(mp_NMI, 0x0, MP_APIC_ALL, 0x1); - /* There is no extension information... */ - - return mptable_finalize(mc); -} - -unsigned long write_smp_table(unsigned long addr) -{ - void *v; - v = smp_write_floating_table(addr, 0); - return (unsigned long)smp_write_config_table(v); -} diff --git a/src/mainboard/asus/m5a88-v/platform_cfg.h b/src/mainboard/asus/m5a88-v/platform_cfg.h deleted file mode 100644 index 161b106ece..0000000000 --- a/src/mainboard/asus/m5a88-v/platform_cfg.h +++ /dev/null @@ -1,217 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - - -#ifndef _PLATFORM_CFG_H_ -#define _PLATFORM_CFG_H_ - -/** - * @def BIOS_SIZE - * BIOS_SIZE_{1,2,4,8,16}M - * - * In SB800, default ROM size is 1M Bytes, if your platform ROM - * bigger than 1M you have to set the ROM size outside CIMx module and - * before AGESA module get call. - */ -#ifndef BIOS_SIZE -#define BIOS_SIZE ((CONFIG_COREBOOT_ROMSIZE_KB >> 10) - 1) -#endif /* BIOS_SIZE */ - -/** - * @def SPREAD_SPECTRUM - * @brief - * 0 - Disable Spread Spectrum function - * 1 - Enable Spread Spectrum function - */ -#define SPREAD_SPECTRUM 0 - -/** - * @def SB_HPET_TIMER - * @brief - * 0 - Disable hpet - * 1 - Enable hpet - */ -#define HPET_TIMER 1 - -/** - * @def USB_CONFIG - * @brief bit[0-6] used to control USB - * 0 - Disable - * 1 - Enable - * Usb Ohci1 Controller (Bus 0 Dev 18 Func0) is define at BIT0 - * Usb Ehci1 Controller (Bus 0 Dev 18 Func2) is define at BIT1 - * Usb Ohci2 Controller (Bus 0 Dev 19 Func0) is define at BIT2 - * Usb Ehci2 Controller (Bus 0 Dev 19 Func2) is define at BIT3 - * Usb Ohci3 Controller (Bus 0 Dev 22 Func0) is define at BIT4 - * Usb Ehci3 Controller (Bus 0 Dev 22 Func2) is define at BIT5 - * Usb Ohci4 Controller (Bus 0 Dev 20 Func5) is define at BIT6 - */ -#define USB_CONFIG 0x7F - -/** - * @def PCI_CLOCK_CTRL - * @brief bit[0-4] used for PCI Slots Clock Control, - * 0 - disable - * 1 - enable - * PCI SLOT 0 define at BIT0 - * PCI SLOT 1 define at BIT1 - * PCI SLOT 2 define at BIT2 - * PCI SLOT 3 define at BIT3 - * PCI SLOT 4 define at BIT4 - */ -#define PCI_CLOCK_CTRL 0x1F - -/** - * @def SATA_CONTROLLER - * @brief INCHIP Sata Controller - */ -#define SATA_CONTROLLER CIMX_OPTION_ENABLED - -/** - * @def SATA_MODE - * @brief INCHIP Sata Controller Mode - * NOTE: DO NOT ALLOW SATA & IDE use same mode - */ -#define SATA_MODE CONFIG_SB800_SATA_MODE - -/** - * @brief INCHIP Sata IDE Controller Mode - */ -#define IDE_LEGACY_MODE 0 -#define IDE_NATIVE_MODE 1 - -/** - * @def SATA_IDE_MODE - * @brief INCHIP Sata IDE Controller Mode - * NOTE: DO NOT ALLOW SATA & IDE use same mode - */ -#define SATA_IDE_MODE IDE_LEGACY_MODE - -/** - * @def EXTERNAL_CLOCK - * @brief 00/10: Reference clock from crystal oscillator via - * PAD_XTALI and PAD_XTALO - * - * @def INTERNAL_CLOCK - * @brief 01/11: Reference clock from internal clock through - * CP_PLL_REFCLK_P and CP_PLL_REFCLK_N via RDL - */ -#define EXTERNAL_CLOCK 0x00 -#define INTERNAL_CLOCK 0x01 - -/* NOTE: inagua have to using internal clock, - * otherwise can not detect sata drive - */ -#define SATA_CLOCK_SOURCE INTERNAL_CLOCK - -/** - * @def SATA_PORT_MULT_CAP_RESERVED - * @brief 1 ON, 0 0FF - */ -#define SATA_PORT_MULT_CAP_RESERVED 1 - - -/** - * @def AZALIA_AUTO - * @brief Detect Azalia controller automatically. - * - * @def AZALIA_DISABLE - * @brief Disable Azalia controller. - - * @def AZALIA_ENABLE - * @brief Enable Azalia controller. - */ -#define AZALIA_AUTO 0 -#define AZALIA_DISABLE 1 -#define AZALIA_ENABLE 2 - -/** - * @brief INCHIP HDA controller - */ -#define AZALIA_CONTROLLER AZALIA_AUTO - -/** - * @def AZALIA_PIN_CONFIG - * @brief - * 0 - disable - * 1 - enable - */ -#define AZALIA_PIN_CONFIG 1 - -/** - * @def AZALIA_SDIN_PIN - * @brief - * SDIN0 is define at BIT0 & BIT1 - * 00 - GPIO PIN - * 01 - Reserved - * 10 - As a Azalia SDIN pin - * SDIN1 is define at BIT2 & BIT3 - * SDIN2 is define at BIT4 & BIT5 - * SDIN3 is define at BIT6 & BIT7 - */ -//#define AZALIA_SDIN_PIN 0xAA -#define AZALIA_SDIN_PIN 0x2A - -/** - * @def GPP_CONTROLLER - */ -#define GPP_CONTROLLER CIMX_OPTION_ENABLED - -/** - * @def GPP_CFGMODE - * @brief GPP Link Configuration - * four possible configuration: - * GPP_CFGMODE_X4000 - * GPP_CFGMODE_X2200 - * GPP_CFGMODE_X2110 - * GPP_CFGMODE_X1111 - */ -#define GPP_CFGMODE GPP_CFGMODE_X1111 - -/** - * @def NB_SB_GEN2 - * 0 - Disable - * 1 - Enable - */ -#define NB_SB_GEN2 TRUE - -/** - * @def SB_GPP_GEN2 - * 0 - Disable - * 1 - Enable - */ -#define SB_GPP_GEN2 TRUE - -/** - * @def SB_GPP_UNHIDE_PORTS - * TRUE - ports visible always, even port empty - * FALSE - ports invisible if port empty - */ -#define SB_GPP_UNHIDE_PORTS FALSE - -/** - * @def GEC_CONFIG - * 0 - Enable - * 1 - Disable - */ -#define GEC_CONFIG 0 - -/** - * @def SIO_HWM_BASE_ADDRESS - * Super IO HWM base address - */ -#define SIO_HWM_BASE_ADDRESS 0x290 - -#endif diff --git a/src/mainboard/asus/m5a88-v/resourcemap.c b/src/mainboard/asus/m5a88-v/resourcemap.c deleted file mode 100644 index fe096a2c59..0000000000 --- a/src/mainboard/asus/m5a88-v/resourcemap.c +++ /dev/null @@ -1,277 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include - -void setup_mb_resource_map(void) -{ - static const unsigned int register_values[] = { - /* Careful set limit registers before base registers which contain the enables */ - /* DRAM Limit i Registers - * F1:0x44 i = 0 - * F1:0x4C i = 1 - * F1:0x54 i = 2 - * F1:0x5C i = 3 - * F1:0x64 i = 4 - * F1:0x6C i = 5 - * F1:0x74 i = 6 - * F1:0x7C i = 7 - * [ 2: 0] Destination Node ID - * 000 = Node 0 - * 001 = Node 1 - * 010 = Node 2 - * 011 = Node 3 - * 100 = Node 4 - * 101 = Node 5 - * 110 = Node 6 - * 111 = Node 7 - * [ 7: 3] Reserved - * [10: 8] Interleave select - * specifies the values of A[14:12] to use with interleave enable. - * [15:11] Reserved - * [31:16] DRAM Limit Address i Bits 39-24 - * This field defines the upper address bits of a 40 bit address - * that define the end of the DRAM region. - */ -// ADDRMAP_REG(0x44), 0x0000f8f8, 0x00000000, // Don't touch it, we need it for CONFIG_CAR_FAM10 - ADDRMAP_REG(0x4C), 0x0000f8f8, 0x00000001, - ADDRMAP_REG(0x54), 0x0000f8f8, 0x00000002, - ADDRMAP_REG(0x5C), 0x0000f8f8, 0x00000003, - ADDRMAP_REG(0x64), 0x0000f8f8, 0x00000004, - ADDRMAP_REG(0x6C), 0x0000f8f8, 0x00000005, - ADDRMAP_REG(0x74), 0x0000f8f8, 0x00000006, - ADDRMAP_REG(0x7C), 0x0000f8f8, 0x00000007, - /* DRAM Base i Registers - * F1:0x40 i = 0 - * F1:0x48 i = 1 - * F1:0x50 i = 2 - * F1:0x58 i = 3 - * F1:0x60 i = 4 - * F1:0x68 i = 5 - * F1:0x70 i = 6 - * F1:0x78 i = 7 - * [ 0: 0] Read Enable - * 0 = Reads Disabled - * 1 = Reads Enabled - * [ 1: 1] Write Enable - * 0 = Writes Disabled - * 1 = Writes Enabled - * [ 7: 2] Reserved - * [10: 8] Interleave Enable - * 000 = No interleave - * 001 = Interleave on A[12] (2 nodes) - * 010 = reserved - * 011 = Interleave on A[12] and A[14] (4 nodes) - * 100 = reserved - * 101 = reserved - * 110 = reserved - * 111 = Interleve on A[12] and A[13] and A[14] (8 nodes) - * [15:11] Reserved - * [13:16] DRAM Base Address i Bits 39-24 - * This field defines the upper address bits of a 40-bit address - * that define the start of the DRAM region. - */ -// ADDRMAP_REG(0x40), 0x0000f8fc, 0x00000000,// don't touch it, we need it for CONFIG_CAR_FAM10 - ADDRMAP_REG(0x48), 0x0000f8fc, 0x00000000, - ADDRMAP_REG(0x50), 0x0000f8fc, 0x00000000, - ADDRMAP_REG(0x58), 0x0000f8fc, 0x00000000, - ADDRMAP_REG(0x60), 0x0000f8fc, 0x00000000, - ADDRMAP_REG(0x68), 0x0000f8fc, 0x00000000, - ADDRMAP_REG(0x70), 0x0000f8fc, 0x00000000, - ADDRMAP_REG(0x78), 0x0000f8fc, 0x00000000, - - /* Memory-Mapped I/O Limit i Registers - * F1:0x84 i = 0 - * F1:0x8C i = 1 - * F1:0x94 i = 2 - * F1:0x9C i = 3 - * F1:0xA4 i = 4 - * F1:0xAC i = 5 - * F1:0xB4 i = 6 - * F1:0xBC i = 7 - * [ 2: 0] Destination Node ID - * 000 = Node 0 - * 001 = Node 1 - * 010 = Node 2 - * 011 = Node 3 - * 100 = Node 4 - * 101 = Node 5 - * 110 = Node 6 - * 111 = Node 7 - * [ 3: 3] Reserved - * [ 5: 4] Destination Link ID - * 00 = Link 0 - * 01 = Link 1 - * 10 = Link 2 - * 11 = Reserved - * [ 6: 6] Reserved - * [ 7: 7] Non-Posted - * 0 = CPU writes may be posted - * 1 = CPU writes must be non-posted - * [31: 8] Memory-Mapped I/O Limit Address i (39-16) - * This field defines the upp address bits of a 40-bit address that - * defines the end of a memory-mapped I/O region n - */ - ADDRMAP_REG(0x84), 0x00000048, 0x00000000, - ADDRMAP_REG(0x8C), 0x00000048, 0x00000000, - ADDRMAP_REG(0x94), 0x00000048, 0x00000000, - ADDRMAP_REG(0x9C), 0x00000048, 0x00000000, - ADDRMAP_REG(0xA4), 0x00000048, 0x00000000, - ADDRMAP_REG(0xAC), 0x00000048, 0x00000000, - ADDRMAP_REG(0xB4), 0x00000048, 0x00000000, -// ADDRMAP_REG(0xBC), 0x00000048, 0x00ffff00, - - /* Memory-Mapped I/O Base i Registers - * F1:0x80 i = 0 - * F1:0x88 i = 1 - * F1:0x90 i = 2 - * F1:0x98 i = 3 - * F1:0xA0 i = 4 - * F1:0xA8 i = 5 - * F1:0xB0 i = 6 - * F1:0xB8 i = 7 - * [ 0: 0] Read Enable - * 0 = Reads disabled - * 1 = Reads Enabled - * [ 1: 1] Write Enable - * 0 = Writes disabled - * 1 = Writes Enabled - * [ 2: 2] Cpu Disable - * 0 = Cpu can use this I/O range - * 1 = Cpu requests do not use this I/O range - * [ 3: 3] Lock - * 0 = base/limit registers i are read/write - * 1 = base/limit registers i are read-only - * [ 7: 4] Reserved - * [31: 8] Memory-Mapped I/O Base Address i (39-16) - * This field defines the upper address bits of a 40bit address - * that defines the start of memory-mapped I/O region i - */ - ADDRMAP_REG(0x80), 0x000000f0, 0x00000000, - ADDRMAP_REG(0x88), 0x000000f0, 0x00000000, - ADDRMAP_REG(0x90), 0x000000f0, 0x00000000, - ADDRMAP_REG(0x98), 0x000000f0, 0x00000000, - ADDRMAP_REG(0xA0), 0x000000f0, 0x00000000, - ADDRMAP_REG(0xA8), 0x000000f0, 0x00000000, - ADDRMAP_REG(0xB0), 0x000000f0, 0x00000000, -// ADDRMAP_REG(0xB8), 0x000000f0, 0x00fc0003, - - /* PCI I/O Limit i Registers - * F1:0xC4 i = 0 - * F1:0xCC i = 1 - * F1:0xD4 i = 2 - * F1:0xDC i = 3 - * [ 2: 0] Destination Node ID - * 000 = Node 0 - * 001 = Node 1 - * 010 = Node 2 - * 011 = Node 3 - * 100 = Node 4 - * 101 = Node 5 - * 110 = Node 6 - * 111 = Node 7 - * [ 3: 3] Reserved - * [ 5: 4] Destination Link ID - * 00 = Link 0 - * 01 = Link 1 - * 10 = Link 2 - * 11 = reserved - * [11: 6] Reserved - * [24:12] PCI I/O Limit Address i - * This field defines the end of PCI I/O region n - * [31:25] Reserved - */ -// ADDRMAP_REG(0xC4), 0xFE000FC8, 0x01fff000, - ADDRMAP_REG(0xCC), 0xFE000FC8, 0x00000000, - ADDRMAP_REG(0xD4), 0xFE000FC8, 0x00000000, - ADDRMAP_REG(0xDC), 0xFE000FC8, 0x00000000, - - /* PCI I/O Base i Registers - * F1:0xC0 i = 0 - * F1:0xC8 i = 1 - * F1:0xD0 i = 2 - * F1:0xD8 i = 3 - * [ 0: 0] Read Enable - * 0 = Reads Disabled - * 1 = Reads Enabled - * [ 1: 1] Write Enable - * 0 = Writes Disabled - * 1 = Writes Enabled - * [ 3: 2] Reserved - * [ 4: 4] VGA Enable - * 0 = VGA matches Disabled - * 1 = matches all address < 64K and where A[9:0] is in the - * range 3B0-3BB or 3C0-3DF independen of the base & limit registers - * [ 5: 5] ISA Enable - * 0 = ISA matches Disabled - * 1 = Blocks address < 64K and in the last 768 bytes of eack 1K block - * from matching agains this base/limit pair - * [11: 6] Reserved - * [24:12] PCI I/O Base i - * This field defines the start of PCI I/O region n - * [31:25] Reserved - */ -// ADDRMAP_REG(0xC0), 0xFE000FCC, 0x00000003, - ADDRMAP_REG(0xC8), 0xFE000FCC, 0x00000000, - ADDRMAP_REG(0xD0), 0xFE000FCC, 0x00000000, - ADDRMAP_REG(0xD8), 0xFE000FCC, 0x00000000, - - /* Config Base and Limit i Registers - * F1:0xE0 i = 0 - * F1:0xE4 i = 1 - * F1:0xE8 i = 2 - * F1:0xEC i = 3 - * [ 0: 0] Read Enable - * 0 = Reads Disabled - * 1 = Reads Enabled - * [ 1: 1] Write Enable - * 0 = Writes Disabled - * 1 = Writes Enabled - * [ 2: 2] Device Number Compare Enable - * 0 = The ranges are based on bus number - * 1 = The ranges are ranges of devices on bus 0 - * [ 3: 3] Reserved - * [ 6: 4] Destination Node - * 000 = Node 0 - * 001 = Node 1 - * 010 = Node 2 - * 011 = Node 3 - * 100 = Node 4 - * 101 = Node 5 - * 110 = Node 6 - * 111 = Node 7 - * [ 7: 7] Reserved - * [ 9: 8] Destination Link - * 00 = Link 0 - * 01 = Link 1 - * 10 = Link 2 - * 11 - Reserved - * [15:10] Reserved - * [23:16] Bus Number Base i - * This field defines the lowest bus number in configuration region i - * [31:24] Bus Number Limit i - * This field defines the highest bus number in configuration regin i - */ -// ADDRMAP_REG(0xE0), 0x0000FC88, 0x06000003, // AMD 8111 on link0 of CPU 0 - ADDRMAP_REG(0xE4), 0x0000FC88, 0x00000000, - ADDRMAP_REG(0xE8), 0x0000FC88, 0x00000000, - ADDRMAP_REG(0xEC), 0x0000FC88, 0x00000000, - }; - - int max; - max = ARRAY_SIZE(register_values); - setup_resource_map(register_values, max); -} diff --git a/src/mainboard/asus/m5a88-v/romstage.c b/src/mainboard/asus/m5a88-v/romstage.c deleted file mode 100644 index 52de343b95..0000000000 --- a/src/mainboard/asus/m5a88-v/romstage.c +++ /dev/null @@ -1,223 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -//#define SYSTEM_TYPE 0 /* SERVER */ -#define SYSTEM_TYPE 1 /* DESKTOP */ -//#define SYSTEM_TYPE 2 /* MOBILE */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include "southbridge/amd/sb800/early_setup.c" -#include "spd.h" - -#include "cpu/amd/quadcore/quadcore.c" - -#define SERIAL_DEV PNP_DEV(0x4e, IT8721F_SP1) - -int spd_read_byte(unsigned int device, unsigned int address); - - -int spd_read_byte(u32 device, u32 address) -{ - return do_smbus_read_byte(SMBUS_IO_BASE, device, address); -} - - -void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) -{ - struct sys_info *sysinfo = get_sysinfo(); - static const u8 spd_addr[] = {RC00, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, }; - u32 bsp_apicid = 0, val; - msr_t msr; - - timestamp_init(timestamp_get()); - timestamp_add_now(TS_START_ROMSTAGE); - - if (!cpu_init_detectedx && boot_cpu()) { - /* Nothing special needs to be done to find bus 0 */ - /* Allow the HT devices to be found */ - /* mov bsp to bus 0xff when > 8 nodes */ - set_bsp_node_CHtExtNodeCfgEn(); - enumerate_ht_chain(); - - //enable port80 decoding and southbridge poweron init - sb800_lpc_init(); - sb800_pci_port80(); - } - - post_code(0x30); - - if (bist == 0) { - bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo); /* mmconf is inited in init_cpus */ - /* All cores run this but the BSP(node0,core0) is the only core that returns. */ - } - - post_code(0x32); - - enable_rs780_dev8(); - sb800_clk_output_48Mhz(); - - ite_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); - console_init(); - printk(BIOS_DEBUG, "\n"); - - /* Halt if there was a built in self test failure */ - report_bist_failure(bist); - - // Load MPB - val = cpuid_eax(1); - printk(BIOS_DEBUG, "BSP Family_Model: %08x\n", val); - printk(BIOS_DEBUG, "*sysinfo range: [%p,%p]\n",sysinfo,sysinfo+1); - printk(BIOS_DEBUG, "bsp_apicid = %02x\n", bsp_apicid); - printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx); - - /* Setup sysinfo defaults */ - set_sysinfo_in_ram(0); - - update_microcode(val); - - post_code(0x33); - - cpuSetAMDMSR(0); - post_code(0x34); - - amd_ht_init(sysinfo); - post_code(0x35); - - /* Setup nodes PCI space and start core 0 AP init. */ - finalize_node_setup(sysinfo); - - /* Setup any mainboard PCI settings etc. */ - setup_mb_resource_map(); - post_code(0x36); - - /* wait for all the APs core0 started by finalize_node_setup. */ - /* FIXME: A bunch of cores are going to start output to serial at once. - It would be nice to fixup prink spinlocks for ROM XIP mode. - I think it could be done by putting the spinlock flag in the cache - of the BSP located right after sysinfo. - */ - wait_all_core0_started(); - -#if CONFIG(LOGICAL_CPUS) - /* Core0 on each node is configured. Now setup any additional cores. */ - printk(BIOS_DEBUG, "start_other_cores()\n"); - start_other_cores(bsp_apicid); - post_code(0x37); - wait_all_other_cores_started(bsp_apicid); -#endif - - post_code(0x38); - - /* run _early_setup before soft-reset. */ - rs780_early_setup(); - sb800_early_setup(); - -#if CONFIG(SET_FIDVID) - msr = rdmsr(MSR_COFVID_STS); - printk(BIOS_DEBUG, "\nBegin FIDVID MSR 0xc0010071 0x%08x 0x%08x\n", msr.hi, msr.lo); - post_code(0x39); - - enable_fid_change_on_sb(sysinfo->sbbusn, sysinfo->sbdn); - - if (!warm_reset_detect(0)) { // BSP is node 0 - init_fidvid_bsp(bsp_apicid, sysinfo->nodes); - } else { - init_fidvid_stage2(bsp_apicid, 0); // BSP is node 0 - } - - post_code(0x3A); - - /* show final fid and vid */ - msr = rdmsr(MSR_COFVID_STS); - printk(BIOS_DEBUG, "End FIDVIDMSR 0xc0010071 0x%08x 0x%08x\n", msr.hi, msr.lo); -#endif - - rs780_htinit(); - - /* Reset for HT, FIDVID, PLL and errata changes to take affect. */ - if (!warm_reset_detect(0)) { - printk(BIOS_INFO, "...WARM RESET...\n\n\n"); - soft_reset(); - die("After soft_reset - shouldn't see this message!!!\n"); - } - - post_code(0x3B); - - /* It's the time to set ctrl in sysinfo now; */ - printk(BIOS_DEBUG, "fill_mem_ctrl()\n"); - fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr); - - post_code(0x40); - - raminit_amdmct(sysinfo); - - cbmem_initialize_empty(); - post_code(0x41); - - amdmct_cbmem_store_info(sysinfo); - - sb800_before_pci_init(); - - post_code(0x42); -} - -/** - * BOOL AMD_CB_ManualBUIDSwapList(u8 Node, u8 Link, u8 **List) - * Description: - * This routine is called every time a non-coherent chain is processed. - * BUID assignment may be controlled explicitly on a non-coherent chain. Provide a - * swap list. The first part of the list controls the BUID assignment and the - * second part of the list provides the device to device linking. Device orientation - * can be detected automatically, or explicitly. See documentation for more details. - * - * Automatic non-coherent init assigns BUIDs starting at 1 and incrementing sequentially - * based on each device's unit count. - * - * Parameters: - * @param[in] node = The node on which this chain is located - * @param[in] link = The link on the host for this chain - * @param[out] List = supply a pointer to a list - */ -BOOL AMD_CB_ManualBUIDSwapList (u8 node, u8 link, const u8 **List) -{ - static const u8 swaplist[] = {0, 1, 0xFF, 0, 0xFF}; - /* If the BUID was adjusted in early_ht we need to do the manual override */ - if ((node == 0) && (link == 0)) { /* BSP SB link */ - *List = swaplist; - return 1; - } - - return 0; -} diff --git a/src/mainboard/avalue/Kconfig b/src/mainboard/avalue/Kconfig deleted file mode 100644 index b91259beae..0000000000 --- a/src/mainboard/avalue/Kconfig +++ /dev/null @@ -1,30 +0,0 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2011 Advanced Micro Devices, Inc. -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; version 2 of the License. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## -if VENDOR_AVALUE - -choice - prompt "Mainboard model" - -source "src/mainboard/avalue/*/Kconfig.name" - -endchoice - -source "src/mainboard/avalue/*/Kconfig" - -config MAINBOARD_VENDOR - string - default "AVALUE" - -endif # VENDOR_AVALUE diff --git a/src/mainboard/avalue/Kconfig.name b/src/mainboard/avalue/Kconfig.name deleted file mode 100644 index 27c551184b..0000000000 --- a/src/mainboard/avalue/Kconfig.name +++ /dev/null @@ -1,2 +0,0 @@ -config VENDOR_AVALUE - bool "AVALUE" diff --git a/src/mainboard/avalue/eax-785e/Kconfig b/src/mainboard/avalue/eax-785e/Kconfig deleted file mode 100644 index 0131db6c5b..0000000000 --- a/src/mainboard/avalue/eax-785e/Kconfig +++ /dev/null @@ -1,65 +0,0 @@ -if BOARD_AVALUE_EAX_785E - -config BOARD_SPECIFIC_OPTIONS - def_bool y - select CPU_AMD_SOCKET_AM3 - select DIMM_DDR3 - select DIMM_REGISTERED - select NORTHBRIDGE_AMD_AMDFAM10 - select SOUTHBRIDGE_AMD_RS780 - select SOUTHBRIDGE_AMD_SB800 - select SUPERIO_WINBOND_W83627HF #COM1, COM2 - #select SUPERIO_FINTEK_F81216AD #COM3, COM4 - select HAVE_OPTION_TABLE - select HAVE_PIRQ_TABLE - select SB_HT_CHAIN_UNITID_OFFSET_ONLY - select LIFT_BSP_APIC_ID - select HAVE_MP_TABLE - select HAVE_ACPI_TABLES - select BOARD_ROMSIZE_KB_2048 - select ENABLE_APIC_EXT_ID - select GFXUMA - select HAVE_DEBUG_CAR - select SET_FIDVID - -config MAINBOARD_DIR - string - default avalue/eax-785e - -config APIC_ID_OFFSET - hex - default 0x0 - -config MAINBOARD_PART_NUMBER - string - default "EAX-785E" - -config HW_MEM_HOLE_SIZEK - hex - default 0x100000 - -config MAX_CPUS - int - default 8 - -config MAX_PHYSICAL_CPUS - int - default 1 - -config HT_CHAIN_END_UNITID_BASE - hex - default 0x1 - -config HT_CHAIN_UNITID_BASE - hex - default 0x0 - -config IRQ_SLOT_COUNT - int - default 11 - -config VGA_BIOS_ID - string - default "1002,9712" - -endif #BOARD_AVALUE_EAX_785E diff --git a/src/mainboard/avalue/eax-785e/Kconfig.name b/src/mainboard/avalue/eax-785e/Kconfig.name deleted file mode 100644 index dab8b86553..0000000000 --- a/src/mainboard/avalue/eax-785e/Kconfig.name +++ /dev/null @@ -1,2 +0,0 @@ -config BOARD_AVALUE_EAX_785E - bool "EAX-785E" diff --git a/src/mainboard/avalue/eax-785e/Makefile.inc b/src/mainboard/avalue/eax-785e/Makefile.inc deleted file mode 100644 index 91d4b39c32..0000000000 --- a/src/mainboard/avalue/eax-785e/Makefile.inc +++ /dev/null @@ -1,16 +0,0 @@ -# -# This file is part of the coreboot project. -# -# This program is free software; you can redistribute it and/or modify -# it under the terms of the GNU General Public License as published by -# the Free Software Foundation; version 2 of the License. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# - -romstage-y += resourcemap.c - -ramstage-y += get_bus_conf.c diff --git a/src/mainboard/avalue/eax-785e/acpi/cpstate.asl b/src/mainboard/avalue/eax-785e/acpi/cpstate.asl deleted file mode 100644 index eb4eac1027..0000000000 --- a/src/mainboard/avalue/eax-785e/acpi/cpstate.asl +++ /dev/null @@ -1,80 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -/* This file defines the processor and performance state capability - * for each core in the system. It is included into the DSDT for each - * core. It assumes that each core of the system has the same performance - * characteristics. -*/ -/* -#include -DefinitionBlock ("DSDT.AML", "DSDT", 0x01, OEM_ID, ACPI_TABLE_CREATOR, 0x00010001) - { - Scope (\_PR) { - Device (CPU0) { - Name (_HID, "ACPI0007") - Name (_UID, 0) - #include "cpstate.asl" - } - Device (CPU1) { - Name (_HID, "ACPI0007") - Name (_UID, 1) - #include "cpstate.asl" - } - Device (CPU2) { - Name (_HID, "ACPI0007") - Name (_UID, 2) - #include "cpstate.asl" - } - Device (CPU3) { - Name (_HID, "ACPI0007") - Name (_UID, 3) - #include "cpstate.asl" - } - } -*/ - /* P-state support: The maximum number of P-states supported by the */ - /* CPUs we'll use is 6. */ - /* Get from AMI BIOS. */ - Name(_PSS, Package(){ - Package () - { - 0x00000AF0, - 0x0000BF81, - 0x00000002, - 0x00000002, - 0x00000000, - 0x00000000 - }, - - Package () - { - 0x00000578, - 0x000076F2, - 0x00000002, - 0x00000002, - 0x00000001, - 0x00000001 - } - }) - - Name(_PCT, Package(){ - ResourceTemplate(){Register(FFixedHW, 0, 0, 0)}, - ResourceTemplate(){Register(FFixedHW, 0, 0, 0)} - }) - - Method(_PPC, 0){ - Return(0) - } diff --git a/src/mainboard/avalue/eax-785e/acpi/routing.asl b/src/mainboard/avalue/eax-785e/acpi/routing.asl deleted file mode 100644 index 46920552e7..0000000000 --- a/src/mainboard/avalue/eax-785e/acpi/routing.asl +++ /dev/null @@ -1,395 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -/* -#include -DefinitionBlock ("DSDT.AML", "DSDT", 0x01, OEM_ID, ACPI_TABLE_CREATOR, 0x00010001 - ) - { - #include "routing.asl" - } -*/ - -/* Routing is in System Bus scope */ -Scope(\_SB) { - Name(PR0, Package(){ - /* NB devices */ - /* Bus 0, Dev 0 - RS780 Host Controller */ - /* Bus 0, Dev 1 - PCI Bridge for Internal Graphics */ - /* Bus 0, Dev 2 - PCIe Bridge for x8 PCIe Slot (GFX0) */ - Package(){0x0002FFFF, 0, INTC, 0 }, - Package(){0x0002FFFF, 1, INTD, 0 }, - Package(){0x0002FFFF, 2, INTA, 0 }, - Package(){0x0002FFFF, 3, INTB, 0 }, - /* Bus 0, Dev 3 - PCIe graphics port 1 bridge */ - /* Bus 0, Dev 4 - PCIe Bridge for Express Card Slot */ - Package(){0x0004FFFF, 0, INTA, 0 }, - Package(){0x0004FFFF, 1, INTB, 0 }, - Package(){0x0004FFFF, 2, INTC, 0 }, - Package(){0x0004FFFF, 3, INTD, 0 }, - /* Bus 0, Dev 5 - General purpose PCIe bridge 5 */ - /* Package(){0x0005FFFF, 0, INTB, 0 }, */ - /* Package(){0x0005FFFF, 1, INTC, 0 }, */ - /* Package(){0x0005FFFF, 2, INTD, 0 }, */ - /* Package(){0x0005FFFF, 3, INTA, 0 }, */ - /* Bus 0, Dev 6 - PCIe Bridge for Ethernet Chip */ - Package(){0x0006FFFF, 0, INTC, 0 }, - Package(){0x0006FFFF, 1, INTD, 0 }, - Package(){0x0006FFFF, 2, INTA, 0 }, - Package(){0x0006FFFF, 3, INTB, 0 }, - /* Bus 0, Dev 7 - PCIe Bridge for x1 PCIe Slot */ - Package(){0x0007FFFF, 0, INTD, 0 }, - Package(){0x0007FFFF, 1, INTA, 0 }, - Package(){0x0007FFFF, 2, INTB, 0 }, - Package(){0x0007FFFF, 3, INTC, 0 }, - - Package(){0x0009FFFF, 0, INTB, 0 }, - Package(){0x0009FFFF, 1, INTC, 0 }, - Package(){0x0009FFFF, 2, INTD, 0 }, - Package(){0x0009FFFF, 3, INTA, 0 }, - - Package(){0x000AFFFF, 0, INTC, 0 }, - Package(){0x000AFFFF, 1, INTD, 0 }, - Package(){0x000AFFFF, 2, INTA, 0 }, - Package(){0x000AFFFF, 3, INTB, 0 }, - - Package(){0x000BFFFF, 0, INTD, 0 }, - Package(){0x000BFFFF, 1, INTA, 0 }, - Package(){0x000BFFFF, 2, INTB, 0 }, - Package(){0x000BFFFF, 3, INTC, 0 }, - - Package(){0x000CFFFF, 0, INTA, 0 }, - Package(){0x000CFFFF, 1, INTB, 0 }, - Package(){0x000CFFFF, 2, INTC, 0 }, - Package(){0x000CFFFF, 3, INTD, 0 }, - - /* Bus 0, Funct 8 - Southbridge port (normally hidden) */ - - /* SB devices */ - /* Bus 0, Dev 17 - SATA controller #2 */ - /* Bus 0, Dev 18 - SATA controller #1 */ - Package(){0x0011FFFF, 0, INTD, 0 }, - - /* Bus 0, Dev 19 - USB: OHCI, dev 18,19 func 0-2, dev 20 func 5; - * EHCI, dev 18, 19 func 2 */ - Package(){0x0012FFFF, 0, INTC, 0 }, - Package(){0x0012FFFF, 1, INTB, 0 }, - - Package(){0x0013FFFF, 0, INTC, 0 }, - Package(){0x0013FFFF, 1, INTB, 0 }, - - Package(){0x0016FFFF, 0, INTC, 0 }, - Package(){0x0016FFFF, 1, INTB, 0 }, - - /* Package(){0x0014FFFF, 1, INTA, 0 }, */ - - /* Bus 0, Dev 20 - F0:SMBus/ACPI,F1:IDE;F2:HDAudio;F3:LPC;F4:PCIBridge;F5:USB */ - Package(){0x0014FFFF, 0, INTA, 0 }, - Package(){0x0014FFFF, 1, INTB, 0 }, - Package(){0x0014FFFF, 2, INTC, 0 }, - Package(){0x0014FFFF, 3, INTD, 0 }, - - Package(){0x0015FFFF, 0, INTA, 0 }, - Package(){0x0015FFFF, 1, INTB, 0 }, - Package(){0x0015FFFF, 2, INTC, 0 }, - Package(){0x0015FFFF, 3, INTD, 0 }, - }) - - Name(APR0, Package(){ - /* NB devices in APIC mode */ - /* Bus 0, Dev 0 - RS780 Host Controller */ - - /* Bus 0, Dev 1 - PCI Bridge for Internal Graphics */ - Package(){0x0001FFFF, 0, 0, 18 }, - Package(){0x0001FFFF, 1, 0, 19 }, - - /* Bus 0, Dev 2 - PCIe Bridge for x8 PCIe Slot (GFX0) */ - Package(){0x0002FFFF, 0, 0, 18 }, - /* Package(){0x0002FFFF, 1, 0, 19 }, */ - /* Package(){0x0002FFFF, 2, 0, 16 }, */ - /* Package(){0x0002FFFF, 3, 0, 17 }, */ - - /* Bus 0, Dev 3 - PCIe graphics port 1 bridge */ - Package(){0x0003FFFF, 0, 0, 19 }, - - /* Bus 0, Dev 4 - PCIe Bridge for Express Card Slot */ - Package(){0x0004FFFF, 0, 0, 16 }, - /* Package(){0x0004FFFF, 1, 0, 17 }, */ - /* Package(){0x0004FFFF, 2, 0, 18 }, */ - /* Package(){0x0004FFFF, 3, 0, 19 }, */ - - /* Bus 0, Dev 5 - General purpose PCIe bridge 5 */ - /* Package(){0x0005FFFF, 0, 0, 17 }, */ - /* Package(){0x0005FFFF, 1, 0, 18 }, */ - /* Package(){0x0005FFFF, 2, 0, 19 }, */ - /* Package(){0x0005FFFF, 3, 0, 16 }, */ - - /* Bus 0, Dev 6 - General purpose PCIe bridge 6 */ - /* Package(){0x0006FFFF, 0, 0, 18 }, */ - /* Package(){0x0006FFFF, 1, 0, 19 }, */ - /* Package(){0x0006FFFF, 2, 0, 16 }, */ - /* Package(){0x0006FFFF, 3, 0, 17 }, */ - - /* Bus 0, Dev 7 - PCIe Bridge for network card */ - /* Package(){0x0007FFFF, 0, 0, 19 }, */ - /* Package(){0x0007FFFF, 1, 0, 16 }, */ - /* Package(){0x0007FFFF, 2, 0, 17 }, */ - /* Package(){0x0007FFFF, 3, 0, 18 }, */ - - /* Bus 0, Dev 9 - PCIe Bridge for network card */ - Package(){0x0009FFFF, 0, 0, 17 }, - /* Package(){0x0009FFFF, 1, 0, 16 }, */ - /* Package(){0x0009FFFF, 2, 0, 17 }, */ - /* Package(){0x0009FFFF, 3, 0, 18 }, */ - /* Bus 0, Dev A - PCIe Bridge for network card */ - Package(){0x000AFFFF, 0, 0, 18 }, - /* Package(){0x000AFFFF, 1, 0, 16 }, */ - /* Package(){0x000AFFFF, 2, 0, 17 }, */ - /* Package(){0x000AFFFF, 3, 0, 18 }, */ - /* Bus 0, Funct 8 - Southbridge port (normally hidden) */ - - /* SB devices in APIC mode */ - /* Bus 0, Dev 17 - SATA controller #2 */ - /* Bus 0, Dev 18 - SATA controller #1 */ - Package(){0x0011FFFF, 0, 0, 19 }, - - /* Bus 0, Dev 19 - USB: OHCI, dev 18,19 func 0-2, dev 20 func 5; - * EHCI, dev 18, 19 func 2 */ - Package(){0x0012FFFF, 0, 0, 18 }, - Package(){0x0012FFFF, 1, 0, 17 }, - /* Package(){0x0012FFFF, 2, 0, 18 }, */ - - Package(){0x0013FFFF, 0, 0, 18 }, - Package(){0x0013FFFF, 1, 0, 17 }, - /* Package(){0x0013FFFF, 2, 0, 16 }, */ - - /* Package(){0x00140000, 0, 0, 16 }, */ - - Package(){0x0016FFFF, 0, 0, 18 }, - Package(){0x0016FFFF, 1, 0, 17 }, - - /* Bus 0, Dev 20 - F0:SMBus/ACPI, F1:IDE; F2:HDAudio; F3:LPC; F4:PCIBridge; F5:USB */ - Package(){0x0014FFFF, 0, 0, 16 }, - Package(){0x0014FFFF, 1, 0, 17 }, - Package(){0x0014FFFF, 2, 0, 18 }, - Package(){0x0014FFFF, 3, 0, 19 }, - /* Package(){0x00140004, 2, 0, 18 }, */ - /* Package(){0x00140004, 3, 0, 19 }, */ - /* Package(){0x00140005, 1, 0, 17 }, */ - /* Package(){0x00140006, 1, 0, 17 }, */ - - /* TODO: pcie */ - Package(){0x0015FFFF, 0, 0, 16 }, - Package(){0x0015FFFF, 1, 0, 17 }, - Package(){0x0015FFFF, 2, 0, 18 }, - Package(){0x0015FFFF, 3, 0, 19 }, - }) - - Name(PR1, Package(){ - /* Internal graphics - RS780 VGA, Bus1, Dev5 */ - Package(){0x0005FFFF, 0, INTA, 0 }, - Package(){0x0005FFFF, 1, INTB, 0 }, - Package(){0x0005FFFF, 2, INTC, 0 }, - Package(){0x0005FFFF, 3, INTD, 0 }, - }) - Name(APR1, Package(){ - /* Internal graphics - RS780 VGA, Bus1, Dev5 */ - Package(){0x0005FFFF, 0, 0, 18 }, - Package(){0x0005FFFF, 1, 0, 19 }, - /* Package(){0x0005FFFF, 2, 0, 20 }, */ - /* Package(){0x0005FFFF, 3, 0, 17 }, */ - }) - - Name(PS2, Package(){ - /* The external GFX - Hooked to PCIe slot 2 */ - Package(){0x0000FFFF, 0, INTC, 0 }, - Package(){0x0000FFFF, 1, INTD, 0 }, - Package(){0x0000FFFF, 2, INTA, 0 }, - Package(){0x0000FFFF, 3, INTB, 0 }, - }) - Name(APS2, Package(){ - /* The external GFX - Hooked to PCIe slot 2 */ - Package(){0x0000FFFF, 0, 0, 18 }, - Package(){0x0000FFFF, 1, 0, 19 }, - Package(){0x0000FFFF, 2, 0, 16 }, - Package(){0x0000FFFF, 3, 0, 17 }, - }) - - Name(PS4, Package(){ - /* PCIe slot - Hooked to PCIe slot 4 */ - Package(){0x0000FFFF, 0, INTA, 0 }, - Package(){0x0000FFFF, 1, INTB, 0 }, - Package(){0x0000FFFF, 2, INTC, 0 }, - Package(){0x0000FFFF, 3, INTD, 0 }, - }) - Name(APS4, Package(){ - /* PCIe slot - Hooked to PCIe slot 4 */ - Package(){0x0000FFFF, 0, 0, 16 }, - Package(){0x0000FFFF, 1, 0, 17 }, - Package(){0x0000FFFF, 2, 0, 18 }, - Package(){0x0000FFFF, 3, 0, 19 }, - }) - - Name(PS5, Package(){ - /* PCIe slot - Hooked to PCIe slot 5 */ - Package(){0x0000FFFF, 0, INTB, 0 }, - Package(){0x0000FFFF, 1, INTC, 0 }, - Package(){0x0000FFFF, 2, INTD, 0 }, - Package(){0x0000FFFF, 3, INTA, 0 }, - }) - Name(APS5, Package(){ - /* PCIe slot - Hooked to PCIe slot 5 */ - Package(){0x0000FFFF, 0, 0, 17 }, - Package(){0x0000FFFF, 1, 0, 18 }, - Package(){0x0000FFFF, 2, 0, 19 }, - Package(){0x0000FFFF, 3, 0, 16 }, - }) - - Name(PS6, Package(){ - /* PCIe slot - Hooked to PCIe slot 6 */ - Package(){0x0000FFFF, 0, INTC, 0 }, - Package(){0x0000FFFF, 1, INTD, 0 }, - Package(){0x0000FFFF, 2, INTA, 0 }, - Package(){0x0000FFFF, 3, INTB, 0 }, - }) - Name(APS6, Package(){ - /* PCIe slot - Hooked to PCIe slot 6 */ - Package(){0x0000FFFF, 0, 0, 18 }, - Package(){0x0000FFFF, 1, 0, 19 }, - Package(){0x0000FFFF, 2, 0, 16 }, - Package(){0x0000FFFF, 3, 0, 17 }, - }) - - Name(PS7, Package(){ - /* The onboard Ethernet chip - Hooked to PCIe slot 7 */ - Package(){0x0000FFFF, 0, INTD, 0 }, - Package(){0x0000FFFF, 1, INTA, 0 }, - Package(){0x0000FFFF, 2, INTB, 0 }, - Package(){0x0000FFFF, 3, INTC, 0 }, - }) - Name(APS7, Package(){ - /* The onboard Ethernet chip - Hooked to PCIe slot 7 */ - Package(){0x0000FFFF, 0, 0, 19 }, - Package(){0x0000FFFF, 1, 0, 16 }, - Package(){0x0000FFFF, 2, 0, 17 }, - Package(){0x0000FFFF, 3, 0, 18 }, - }) - - Name(PS9, Package(){ - /* PCIe slot - Hooked to PCIe slot 9 */ - Package(){0x0000FFFF, 0, INTD, 0 }, - Package(){0x0000FFFF, 1, INTA, 0 }, - Package(){0x0000FFFF, 2, INTB, 0 }, - Package(){0x0000FFFF, 3, INTC, 0 }, - }) - Name(APS9, Package(){ - /* PCIe slot - Hooked to PCIe slot 9 */ - Package(){0x0000FFFF, 0, 0, 17 }, - Package(){0x0000FFFF, 1, 0, 18 }, - Package(){0x0000FFFF, 2, 0, 19 }, - Package(){0x0000FFFF, 3, 0, 16 }, - }) - - Name(PSa, Package(){ - /* PCIe slot - Hooked to PCIe slot 10 */ - Package(){0x0000FFFF, 0, INTD, 0 }, - Package(){0x0000FFFF, 1, INTA, 0 }, - Package(){0x0000FFFF, 2, INTB, 0 }, - Package(){0x0000FFFF, 3, INTC, 0 }, - }) - Name(APSa, Package(){ - /* PCIe slot - Hooked to PCIe slot 10 */ - Package(){0x0000FFFF, 0, 0, 18 }, - Package(){0x0000FFFF, 1, 0, 19 }, - Package(){0x0000FFFF, 2, 0, 16 }, - Package(){0x0000FFFF, 3, 0, 17 }, - }) - - Name(PE0, Package(){ - /* PCIe slot - Hooked to PCIe slot 10 */ - Package(){0x0000FFFF, 0, INTA, 0 }, - Package(){0x0000FFFF, 1, INTB, 0 }, - Package(){0x0000FFFF, 2, INTC, 0 }, - Package(){0x0000FFFF, 3, INTD, 0 }, - }) - Name(APE0, Package(){ - /* PCIe slot - Hooked to PCIe */ - Package(){0x0000FFFF, 0, 0, 16 }, - Package(){0x0000FFFF, 1, 0, 17 }, - Package(){0x0000FFFF, 2, 0, 18 }, - Package(){0x0000FFFF, 3, 0, 19 }, - }) - - Name(PE1, Package(){ - /* PCIe slot - Hooked to PCIe slot 10 */ - Package(){0x0000FFFF, 0, INTB, 0 }, - Package(){0x0000FFFF, 1, INTC, 0 }, - Package(){0x0000FFFF, 2, INTD, 0 }, - Package(){0x0000FFFF, 3, INTA, 0 }, - }) - Name(APE1, Package(){ - /* PCIe slot - Hooked to PCIe */ - Package(){0x0000FFFF, 0, 0, 17 }, - Package(){0x0000FFFF, 1, 0, 18 }, - Package(){0x0000FFFF, 2, 0, 19 }, - Package(){0x0000FFFF, 3, 0, 16 }, - }) - - Name(PE2, Package(){ - /* PCIe slot - Hooked to PCIe slot 10 */ - Package(){0x0000FFFF, 0, INTC, 0 }, - Package(){0x0000FFFF, 1, INTD, 0 }, - Package(){0x0000FFFF, 2, INTA, 0 }, - Package(){0x0000FFFF, 3, INTB, 0 }, - }) - Name(APE2, Package(){ - /* PCIe slot - Hooked to PCIe */ - Package(){0x0000FFFF, 0, 0, 18 }, - Package(){0x0000FFFF, 1, 0, 19 }, - Package(){0x0000FFFF, 2, 0, 16 }, - Package(){0x0000FFFF, 3, 0, 17 }, - }) - - Name(PE3, Package(){ - /* PCIe slot - Hooked to PCIe slot 10 */ - Package(){0x0000FFFF, 0, INTD, 0 }, - Package(){0x0000FFFF, 1, INTA, 0 }, - Package(){0x0000FFFF, 2, INTB, 0 }, - Package(){0x0000FFFF, 3, INTC, 0 }, - }) - Name(APE3, Package(){ - /* PCIe slot - Hooked to PCIe */ - Package(){0x0000FFFF, 0, 0, 19 }, - Package(){0x0000FFFF, 1, 0, 16 }, - Package(){0x0000FFFF, 2, 0, 17 }, - Package(){0x0000FFFF, 3, 0, 18 }, - }) - - Name(PCIB, Package(){ - /* PCI slots: slot 0, slot 1, slot 2 behind Dev14, Fun4. */ - Package(){0x0005FFFF, 0, 0, 0x14 }, - Package(){0x0005FFFF, 1, 0, 0x15 }, - Package(){0x0005FFFF, 2, 0, 0x16 }, - Package(){0x0005FFFF, 3, 0, 0x17 }, - Package(){0x0006FFFF, 0, 0, 0x15 }, - Package(){0x0006FFFF, 1, 0, 0x16 }, - Package(){0x0006FFFF, 2, 0, 0x17 }, - Package(){0x0006FFFF, 3, 0, 0x14 }, - Package(){0x0007FFFF, 0, 0, 0x16 }, - Package(){0x0007FFFF, 1, 0, 0x17 }, - Package(){0x0007FFFF, 2, 0, 0x14 }, - Package(){0x0007FFFF, 3, 0, 0x15 }, - }) -} diff --git a/src/mainboard/avalue/eax-785e/acpi/sata.asl b/src/mainboard/avalue/eax-785e/acpi/sata.asl deleted file mode 100644 index 9e0e535da6..0000000000 --- a/src/mainboard/avalue/eax-785e/acpi/sata.asl +++ /dev/null @@ -1,145 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -/* simple name description */ - -/* -Scope (_SB) { - Device(PCI0) { - Device(SATA) { - Name(_ADR, 0x00110000) - #include "sata.asl" - } - } -} -*/ - -Name(STTM, Buffer(20) { - 0x78, 0x00, 0x00, 0x00, 0x0f, 0x00, 0x00, 0x00, - 0x78, 0x00, 0x00, 0x00, 0x0f, 0x00, 0x00, 0x00, - 0x1f, 0x00, 0x00, 0x00 -}) - -/* Start by clearing the PhyRdyChg bits */ -Method(_INI) { - \_GPE._L1F() -} - -Device(PMRY) -{ - Name(_ADR, 0) - Method(_GTM, 0x0, NotSerialized) { - Return(STTM) - } - Method(_STM, 0x3, NotSerialized) {} - - Device(PMST) { - Name(_ADR, 0) - Method(_STA,0) { - if (LGreater(P0IS,0)) { - return (0x0F) /* sata is visible */ - } - else { - return (0x00) /* sata is missing */ - } - } - }/* end of PMST */ - - Device(PSLA) - { - Name(_ADR, 1) - Method(_STA,0) { - if (LGreater(P1IS,0)) { - return (0x0F) /* sata is visible */ - } - else { - return (0x00) /* sata is missing */ - } - } - } /* end of PSLA */ -} /* end of PMRY */ - - -Device(SEDY) -{ - Name(_ADR, 1) /* IDE Scondary Channel */ - Method(_GTM, 0x0, NotSerialized) { - Return(STTM) - } - Method(_STM, 0x3, NotSerialized) {} - - Device(SMST) - { - Name(_ADR, 0) - Method(_STA,0) { - if (LGreater(P2IS,0)) { - return (0x0F) /* sata is visible */ - } - else { - return (0x00) /* sata is missing */ - } - } - } /* end of SMST */ - - Device(SSLA) - { - Name(_ADR, 1) - Method(_STA,0) { - if (LGreater(P3IS,0)) { - return (0x0F) /* sata is visible */ - } - else { - return (0x00) /* sata is missing */ - } - } - } /* end of SSLA */ -} /* end of SEDY */ - -/* SATA Hot Plug Support */ -Scope(\_GPE) { - Method(_L1F,0x0,NotSerialized) { - if (\_SB.P0PR) { - if (LGreater(\_SB.P0IS,0)) { - sleep(32) - } - Notify(\_SB.PCI0.STCR.PMRY.PMST, 0x01) /* NOTIFY_DEVICE_CHECK */ - store(one, \_SB.P0PR) - } - - if (\_SB.P1PR) { - if (LGreater(\_SB.P1IS,0)) { - sleep(32) - } - Notify(\_SB.PCI0.STCR.PMRY.PSLA, 0x01) /* NOTIFY_DEVICE_CHECK */ - store(one, \_SB.P1PR) - } - - if (\_SB.P2PR) { - if (LGreater(\_SB.P2IS,0)) { - sleep(32) - } - Notify(\_SB.PCI0.STCR.SEDY.SMST, 0x01) /* NOTIFY_DEVICE_CHECK */ - store(one, \_SB.P2PR) - } - - if (\_SB.P3PR) { - if (LGreater(\_SB.P3IS,0)) { - sleep(32) - } - Notify(\_SB.PCI0.STCR.SEDY.SSLA, 0x01) /* NOTIFY_DEVICE_CHECK */ - store(one, \_SB.P3PR) - } - } -} diff --git a/src/mainboard/avalue/eax-785e/acpi/usb.asl b/src/mainboard/avalue/eax-785e/acpi/usb.asl deleted file mode 100644 index cd76bf1f94..0000000000 --- a/src/mainboard/avalue/eax-785e/acpi/usb.asl +++ /dev/null @@ -1,158 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -/* simple name description */ -/* -#include -DefinitionBlock ("DSDT.AML", "DSDT", 0x01, OEM_ID, ACPI_TABLE_CREATOR, 0x00010001 - ) - { - #include "usb.asl" - } -*/ -Method(UCOC, 0) { - Sleep(20) - Store(0x13,CMTI) - Store(0,GPSL) -} - -/* USB Port 0 overcurrent uses Gpm 0 */ -If(LLessEqual(UOM0,9)) { - Scope (\_GPE) { - Method (_L13) { - UCOC() - if(LEqual(GPB0,PLC0)) { - Not(PLC0,PLC0) - Store(PLC0, \_SB.PT0D) - } - } - } -} - -/* USB Port 1 overcurrent uses Gpm 1 */ -If (LLessEqual(UOM1,9)) { - Scope (\_GPE) { - Method (_L14) { - UCOC() - if (LEqual(GPB1,PLC1)) { - Not(PLC1,PLC1) - Store(PLC1, \_SB.PT1D) - } - } - } -} - -/* USB Port 2 overcurrent uses Gpm 2 */ -If (LLessEqual(UOM2,9)) { - Scope (\_GPE) { - Method (_L15) { - UCOC() - if (LEqual(GPB2,PLC2)) { - Not(PLC2,PLC2) - Store(PLC2, \_SB.PT2D) - } - } - } -} - -/* USB Port 3 overcurrent uses Gpm 3 */ -If (LLessEqual(UOM3,9)) { - Scope (\_GPE) { - Method (_L16) { - UCOC() - if (LEqual(GPB3,PLC3)) { - Not(PLC3,PLC3) - Store(PLC3, \_SB.PT3D) - } - } - } -} - -/* USB Port 4 overcurrent uses Gpm 4 */ -If (LLessEqual(UOM4,9)) { - Scope (\_GPE) { - Method (_L19) { - UCOC() - if (LEqual(GPB4,PLC4)) { - Not(PLC4,PLC4) - Store(PLC4, \_SB.PT4D) - } - } - } -} - -/* USB Port 5 overcurrent uses Gpm 5 */ -If (LLessEqual(UOM5,9)) { - Scope (\_GPE) { - Method (_L1A) { - UCOC() - if (LEqual(GPB5,PLC5)) { - Not(PLC5,PLC5) - Store(PLC5, \_SB.PT5D) - } - } - } -} - -/* USB Port 6 overcurrent uses Gpm 6 */ -If (LLessEqual(UOM6,9)) { - Scope (\_GPE) { - /* Method (_L1C) { */ - Method (_L06) { - UCOC() - if (LEqual(GPB6,PLC6)) { - Not(PLC6,PLC6) - Store(PLC6, \_SB.PT6D) - } - } - } -} - -/* USB Port 7 overcurrent uses Gpm 7 */ -If (LLessEqual(UOM7,9)) { - Scope (\_GPE) { - /* Method (_L1D) { */ - Method (_L07) { - UCOC() - if (LEqual(GPB7,PLC7)) { - Not(PLC7,PLC7) - Store(PLC7, \_SB.PT7D) - } - } - } -} - -/* USB Port 8 overcurrent uses Gpm 8 */ -If (LLessEqual(UOM8,9)) { - Scope (\_GPE) { - Method (_L17) { - if (LEqual(G8IS,PLC8)) { - Not(PLC8,PLC8) - Store(PLC8, \_SB.PT8D) - } - } - } -} - -/* USB Port 9 overcurrent uses Gpm 9 */ -If (LLessEqual(UOM9,9)) { - Scope (\_GPE) { - Method (_L0E) { - if (LEqual(G9IS,0)) { - Store(1,\_SB.PT9D) - } - } - } -} diff --git a/src/mainboard/avalue/eax-785e/acpi_tables.c b/src/mainboard/avalue/eax-785e/acpi_tables.c deleted file mode 100644 index 7f429996fd..0000000000 --- a/src/mainboard/avalue/eax-785e/acpi_tables.c +++ /dev/null @@ -1,44 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include -#include - -unsigned long acpi_fill_madt(unsigned long current) -{ - /* create all subtables for processors */ - current = acpi_create_madt_lapics(current); - - /* Write SB800 IOAPIC, only one */ - current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, 2, - IO_APIC_ADDR, 0); - - current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) - current, 0, 0, 2, 0); - current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) - current, 0, 9, 9, 0xF); - /* 0: mean bus 0--->ISA */ - /* 0: PIC 0 */ - /* 2: APIC 2 */ - /* 5 mean: 0101 --> Edge-triggered, Active high */ - - /* create all subtables for processors */ - /* current = acpi_create_madt_lapic_nmis(current, 5, 1); */ - /* 1: LINT1 connect to NMI */ - - return current; -} diff --git a/src/mainboard/avalue/eax-785e/board_info.txt b/src/mainboard/avalue/eax-785e/board_info.txt deleted file mode 100644 index bf7e28ae1f..0000000000 --- a/src/mainboard/avalue/eax-785e/board_info.txt +++ /dev/null @@ -1,5 +0,0 @@ -Category: desktop -Board URL: http://www.avalue.com.tw/en/product/detail.aspx?ccid=2&cid=9&id=68&zid=245 -ROM package: SOIC-8 -ROM protocol: SPI -ROM socketed: n diff --git a/src/mainboard/avalue/eax-785e/cmos.layout b/src/mainboard/avalue/eax-785e/cmos.layout deleted file mode 100644 index 6c3d3f6c9e..0000000000 --- a/src/mainboard/avalue/eax-785e/cmos.layout +++ /dev/null @@ -1,52 +0,0 @@ -entries - -0 384 r 0 reserved_memory -384 1 e 4 boot_option -388 4 h 0 reboot_counter -#392 3 r 0 unused -395 1 e 1 hw_scrubber -396 1 e 1 interleave_chip_selects -397 2 e 8 max_mem_clock -399 1 e 2 multi_core -400 1 e 1 power_on_after_fail -412 4 e 6 debug_level -440 4 e 9 slow_cpu -444 1 e 1 nmi -445 1 e 1 gart -456 1 e 1 ECC_memory -728 256 h 0 user_data -984 16 h 0 check_sum -# Reserve the extended AMD configuration registers -1000 24 r 0 amd_reserved - - - -enumerations - -#ID value text -1 0 Disable -1 1 Enable -2 0 Enable -2 1 Disable -4 0 Fallback -4 1 Normal -6 5 Notice -6 6 Info -6 7 Debug -6 8 Spew -8 0 400Mhz -8 1 333Mhz -8 2 266Mhz -8 3 200Mhz -9 0 off -9 1 87.5% -9 2 75.0% -9 3 62.5% -9 4 50.0% -9 5 37.5% -9 6 25.0% -9 7 12.5% - -checksums - -checksum 392 983 984 diff --git a/src/mainboard/avalue/eax-785e/devicetree.cb b/src/mainboard/avalue/eax-785e/devicetree.cb deleted file mode 100644 index 2bf3ca9c00..0000000000 --- a/src/mainboard/avalue/eax-785e/devicetree.cb +++ /dev/null @@ -1,111 +0,0 @@ -# sample config for avalue/EAX-785E -chip northbridge/amd/amdfam10/root_complex - device cpu_cluster 0 on - chip cpu/amd/socket_AM3 #L1 and DDR3 - device lapic 0 on end - end - end - device domain 0 on - subsystemid 0x1612 0x3060 inherit #TODO: Set the correctly subsystem id. - chip northbridge/amd/amdfam10 - device pci 18.0 on # northbridge - chip southbridge/amd/rs780 - device pci 0.0 on end # HT 0x9600 - device pci 1.0 on end # Internal Graphics P2P bridge 0x9712 - device pci 2.0 on end # GFX_RX0-7/TX0-7 PCIEx16_1 slot - device pci 3.0 on end # GFX_RX8-15/TX8-15 PCIEx16_2 slot - device pci 4.0 on end # PortB GPP_RX/TX0 PCIEx1_1 slot - device pci 5.0 on end # PortC GPP_RX/TX1 PCIEx1_2 slot - device pci 6.0 on end # PortD GPP_RX/TX2 PCIEx1_3 slot - device pci 7.0 on end # PortE GPP_RX/TX3 PCIEx1_4 slot - device pci 8.0 off end # NB/SB Link P2P bridge - device pci 9.0 on end # Ethernet - device pci a.0 on end # Ethernet - register "gppsb_configuration" = "4" # Configuration E - register "gpp_configuration" = "3" # Configuration D - register "port_enable" = "0x6FE" - register "gfx_dev2_dev3" = "0" #no use - register "gfx_dual_slot" = "1" # 0 single slot, 1 dual slot - register "gfx_lane_reversal" = "0" - register "gfx_compliance" = "0" - register "gfx_reconfiguration" = "1" - register "gfx_link_width" = "0" - register "gfx_tmds" = "1" - register "gfx_pcie_config" = "4" # 2x8 GFX, one on Lanes 0-7, one on Lanes 8-15 - register "gfx_ddi_config" = "0" # no DDI_SL - end - chip southbridge/amd/cimx/sb800 # it is under NB/SB Link, but on the same pci bus - device pci 11.0 on end # SATA - device pci 12.0 on end # USB - device pci 12.2 on end # USB - device pci 13.0 on end # USB - device pci 13.2 on end # USB - device pci 14.0 on end # SM - device pci 14.1 on end # IDE 0x439c - device pci 14.2 on end # HDA 0x4383 - device pci 14.3 on - chip superio/winbond/w83627hf - device pnp 2e.0 off # Floppy - io 0x60 = 0x3f0 - irq 0x70 = 6 - drq 0x74 = 2 - end - device pnp 2e.1 off # Parallel Port - io 0x60 = 0x378 - irq 0x70 = 7 - end - device pnp 2e.2 on # Com1 - io 0x60 = 0x3f8 - irq 0x70 = 4 - end - device pnp 2e.3 on # Com2 - io 0x60 = 0x2f8 - irq 0x70 = 3 - end - device pnp 2e.5 on # PS/2 Keyboard & mouse - io 0x60 = 0x60 - io 0x62 = 0x64 - irq 0x70 = 1 - irq 0x72 = 12 - end - device pnp 2e.6 off # SFI - io 0x62 = 0x100 - end - device pnp 2e.7 off # GPIO_GAME_MIDI - io 0x60 = 0x220 - io 0x62 = 0x300 - irq 0x70 = 9 - end - device pnp 2e.8 off end # WDTO_PLED - device pnp 2e.9 off end # GPIO_SUSLED - device pnp 2e.a off end # ACPI - device pnp 2e.b on # HW Monitor - io 0x60 = 0x290 - irq 0x70 = 5 - end - end #superio/winbond/w83627hf - end # LPC 0x439d - device pci 14.4 on end # PCIB 0x4384, NOTE: PCI interface pins shared with GPIO {GPIO 35:0} - device pci 14.5 on end # USB 2 - device pci 14.6 off end # Gec - device pci 15.0 off end # PCIe 0 - device pci 15.1 off end # PCIe 1 - device pci 15.2 off end # PCIe 2 - device pci 15.3 on end # PCIe 3 - device pci 16.0 on end # USB - device pci 16.2 on end # USB - #register "gpp_configuration" = "0" #4:0:0:0 - #register "gpp_configuration" = "2" #2:2:0:0 - #register "gpp_configuration" = "3" #2:1:1:0 - register "gpp_configuration" = "4" #1:1:1:1 - register "boot_switch_sata_ide" = "0" # 0: boot from SATA. 1: IDE - end #southbridge/amd/cimx/sb800 - end # device pci 18.0 - - device pci 18.1 on end - device pci 18.2 on end - device pci 18.3 on end - device pci 18.4 on end - end - end #domain -end diff --git a/src/mainboard/avalue/eax-785e/dsdt.asl b/src/mainboard/avalue/eax-785e/dsdt.asl deleted file mode 100644 index 8015ec6f32..0000000000 --- a/src/mainboard/avalue/eax-785e/dsdt.asl +++ /dev/null @@ -1,1613 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -/* DefinitionBlock Statement */ -#include -DefinitionBlock ( - "DSDT.AML", /* Output filename */ - "DSDT", /* Signature */ - 0x02, /* DSDT Revision, needs to be 2 for 64bit */ - OEM_ID, - ACPI_TABLE_CREATOR, - 0x00010001 /* OEM Revision */ - ) -{ /* Start of ASL file */ - /* #include */ /* Include global debug methods if needed */ - - /* Data to be patched by the BIOS during POST */ - /* FIXME the patching is not done yet! */ - /* Memory related values */ - Name(LOMH, 0x0) /* Start of unused memory in C0000-E0000 range */ - Name(PBAD, 0x0) /* Address of BIOS area (If TOM2 != 0, Addr >> 16) */ - Name(PBLN, 0x0) /* Length of BIOS area */ - - Name(PCBA, 0xE0000000) /* Base address of PCIe config space */ - Name(HPBA, 0xFED00000) /* Base address of HPET table */ - - /* USB overcurrent mapping pins. */ - Name(UOM0, 0) - Name(UOM1, 2) - Name(UOM2, 0) - Name(UOM3, 7) - Name(UOM4, 2) - Name(UOM5, 2) - Name(UOM6, 6) - Name(UOM7, 2) - Name(UOM8, 6) - Name(UOM9, 6) - - /* Some global data */ - Name(OSVR, 3) /* Assume nothing. WinXp = 1, Vista = 2, Linux = 3, WinCE = 4 */ - Name(OSV, Ones) /* Assume nothing */ - Name(PMOD, One) /* Assume APIC */ - - /* - * Processor Object - * - */ - Scope (\_PR) { /* define processor scope */ - Device (CPU0) { - Name (_HID, "ACPI0007") - Name (_UID, 0) - #include "acpi/cpstate.asl" - } - Device (CPU1) { - Name (_HID, "ACPI0007") - Name (_UID, 1) - #include "acpi/cpstate.asl" - } - Device (CPU2) { - Name (_HID, "ACPI0007") - Name (_UID, 2) - #include "acpi/cpstate.asl" - } - Device (CPU3) { - Name (_HID, "ACPI0007") - Name (_UID, 3) - #include "acpi/cpstate.asl" - } - } /* End _PR scope */ - - /* PIC IRQ mapping registers, C00h-C01h. */ - OperationRegion(PRQM, SystemIO, 0x00000C00, 0x00000002) - Field(PRQM, ByteAcc, NoLock, Preserve) { - PRQI, 0x00000008, - PRQD, 0x00000008, /* Offset: 1h */ - } - IndexField(PRQI, PRQD, ByteAcc, NoLock, Preserve) { - PIRA, 0x00000008, /* Index 0 */ - PIRB, 0x00000008, /* Index 1 */ - PIRC, 0x00000008, /* Index 2 */ - PIRD, 0x00000008, /* Index 3 */ - PIRE, 0x00000008, /* Index 4 */ - PIRF, 0x00000008, /* Index 5 */ - PIRG, 0x00000008, /* Index 6 */ - PIRH, 0x00000008, /* Index 7 */ - } - - /* PCI Error control register */ - OperationRegion(PERC, SystemIO, 0x00000C14, 0x00000001) - Field(PERC, ByteAcc, NoLock, Preserve) { - SENS, 0x00000001, - PENS, 0x00000001, - SENE, 0x00000001, - PENE, 0x00000001, - } - - /* Client Management index/data registers */ - OperationRegion(CMT, SystemIO, 0x00000C50, 0x00000002) - Field(CMT, ByteAcc, NoLock, Preserve) { - CMTI, 8, - /* Client Management Data register */ - G64E, 1, - G64O, 1, - G32O, 2, - , 2, - GPSL, 2, - } - - /* GPM Port register */ - OperationRegion(GPT, SystemIO, 0x00000C52, 0x00000001) - Field(GPT, ByteAcc, NoLock, Preserve) { - GPB0,1, - GPB1,1, - GPB2,1, - GPB3,1, - GPB4,1, - GPB5,1, - GPB6,1, - GPB7,1, - } - - /* Flash ROM program enable register */ - OperationRegion(FRE, SystemIO, 0x00000C6F, 0x00000001) - Field(FRE, ByteAcc, NoLock, Preserve) { - , 0x00000006, - FLRE, 0x00000001, - } - - /* PM2 index/data registers */ - OperationRegion(PM2R, SystemIO, 0x00000CD0, 0x00000002) - Field(PM2R, ByteAcc, NoLock, Preserve) { - PM2I, 0x00000008, - PM2D, 0x00000008, - } - - /* Power Management I/O registers, TODO:PMIO is quite different in SB800. */ - OperationRegion(PIOR, SystemIO, 0x00000CD6, 0x00000002) - Field(PIOR, ByteAcc, NoLock, Preserve) { - PIOI, 0x00000008, - PIOD, 0x00000008, - } - IndexField (PIOI, PIOD, ByteAcc, NoLock, Preserve) { - Offset(0x00), /* MiscControl */ - , 1, - T1EE, 1, - T2EE, 1, - Offset(0x01), /* MiscStatus */ - , 1, - T1E, 1, - T2E, 1, - Offset(0x04), /* SmiWakeUpEventEnable3 */ - , 7, - SSEN, 1, - Offset(0x07), /* SmiWakeUpEventStatus3 */ - , 7, - CSSM, 1, - Offset(0x10), /* AcpiEnable */ - , 6, - PWDE, 1, - Offset(0x1C), /* ProgramIoEnable */ - , 3, - MKME, 1, - IO3E, 1, - IO2E, 1, - IO1E, 1, - IO0E, 1, - Offset(0x1D), /* IOMonitorStatus */ - , 3, - MKMS, 1, - IO3S, 1, - IO2S, 1, - IO1S, 1, - IO0S,1, - Offset(0x20), /* AcpiPmEvtBlk. TODO: should be 0x60 */ - APEB, 16, - Offset(0x36), /* GEvtLevelConfig */ - , 6, - ELC6, 1, - ELC7, 1, - Offset(0x37), /* GPMLevelConfig0 */ - , 3, - PLC0, 1, - PLC1, 1, - PLC2, 1, - PLC3, 1, - PLC8, 1, - Offset(0x38), /* GPMLevelConfig1 */ - , 1, - PLC4, 1, - PLC5, 1, - , 1, - PLC6, 1, - PLC7, 1, - Offset(0x3B), /* PMEStatus1 */ - GP0S, 1, - GM4S, 1, - GM5S, 1, - APS, 1, - GM6S, 1, - GM7S, 1, - GP2S, 1, - STSS, 1, - Offset(0x55), /* SoftPciRst */ - SPRE, 1, - , 1, - , 1, - PNAT, 1, - PWMK, 1, - PWNS, 1, - - /* Offset(0x61), */ /* Options_1 */ - /* ,7, */ - /* R617,1, */ - - Offset(0x65), /* UsbPMControl */ - , 4, - URRE, 1, - Offset(0x68), /* MiscEnable68 */ - , 3, - TMTE, 1, - , 1, - Offset(0x92), /* GEVENTIN */ - , 7, - E7IS, 1, - Offset(0x96), /* GPM98IN */ - G8IS, 1, - G9IS, 1, - Offset(0x9A), /* EnhanceControl */ - ,7, - HPDE, 1, - Offset(0xA8), /* PIO7654Enable */ - IO4E, 1, - IO5E, 1, - IO6E, 1, - IO7E, 1, - Offset(0xA9), /* PIO7654Status */ - IO4S, 1, - IO5S, 1, - IO6S, 1, - IO7S, 1, - } - - /* PM1 Event Block - * First word is PM1_Status, Second word is PM1_Enable - */ - OperationRegion(P1EB, SystemIO, APEB, 0x04) - Field(P1EB, ByteAcc, NoLock, Preserve) { - TMST, 1, - , 3, - BMST, 1, - GBST, 1, - Offset(0x01), - PBST, 1, - , 1, - RTST, 1, - , 3, - PWST, 1, - SPWS, 1, - Offset(0x02), - TMEN, 1, - , 4, - GBEN, 1, - Offset(0x03), - PBEN, 1, - , 1, - RTEN, 1, - , 3, - PWDA, 1, - } - - Scope(\_SB) { - /* PCIe Configuration Space for 16 busses */ - OperationRegion(PCFG, SystemMemory, PCBA, 0x01000000) /* Each bus consumes 1MB */ - Field(PCFG, ByteAcc, NoLock, Preserve) { - /* Byte offsets are computed using the following technique: - * ((bus number + 1) * ((device number * 8) * 4096)) + register offset - * The 8 comes from 8 functions per device, and 4096 bytes per function config space - */ - Offset(0x00088024), /* Byte offset to SATA register 24h - Bus 0, Device 17, Function 0 */ - STB5, 32, - Offset(0x00098042), /* Byte offset to OHCI0 register 42h - Bus 0, Device 19, Function 0 */ - PT0D, 1, - PT1D, 1, - PT2D, 1, - PT3D, 1, - PT4D, 1, - PT5D, 1, - PT6D, 1, - PT7D, 1, - PT8D, 1, - PT9D, 1, - Offset(0x000A0004), /* Byte offset to SMBUS register 4h - Bus 0, Device 20, Function 0 */ - SBIE, 1, - SBME, 1, - Offset(0x000A0008), /* Byte offset to SMBUS register 8h - Bus 0, Device 20, Function 0 */ - SBRI, 8, - Offset(0x000A0014), /* Byte offset to SMBUS register 14h - Bus 0, Device 20, Function 0 */ - SBB1, 32, - Offset(0x000A0078), /* Byte offset to SMBUS register 78h - Bus 0, Device 20, Function 0 */ - ,14, - P92E, 1, /* Port92 decode enable */ - } - - OperationRegion(SB5, SystemMemory, STB5, 0x1000) - Field(SB5, AnyAcc, NoLock, Preserve){ - /* Port 0 */ - Offset(0x120), /* Port 0 Task file status */ - P0ER, 1, - , 2, - P0DQ, 1, - , 3, - P0BY, 1, - Offset(0x128), /* Port 0 Serial ATA status */ - P0DD, 4, - , 4, - P0IS, 4, - Offset(0x12C), /* Port 0 Serial ATA control */ - P0DI, 4, - Offset(0x130), /* Port 0 Serial ATA error */ - , 16, - P0PR, 1, - - /* Port 1 */ - offset(0x1A0), /* Port 1 Task file status */ - P1ER, 1, - , 2, - P1DQ, 1, - , 3, - P1BY, 1, - Offset(0x1A8), /* Port 1 Serial ATA status */ - P1DD, 4, - , 4, - P1IS, 4, - Offset(0x1AC), /* Port 1 Serial ATA control */ - P1DI, 4, - Offset(0x1B0), /* Port 1 Serial ATA error */ - , 16, - P1PR, 1, - - /* Port 2 */ - Offset(0x220), /* Port 2 Task file status */ - P2ER, 1, - , 2, - P2DQ, 1, - , 3, - P2BY, 1, - Offset(0x228), /* Port 2 Serial ATA status */ - P2DD, 4, - , 4, - P2IS, 4, - Offset(0x22C), /* Port 2 Serial ATA control */ - P2DI, 4, - Offset(0x230), /* Port 2 Serial ATA error */ - , 16, - P2PR, 1, - - /* Port 3 */ - Offset(0x2A0), /* Port 3 Task file status */ - P3ER, 1, - , 2, - P3DQ, 1, - , 3, - P3BY, 1, - Offset(0x2A8), /* Port 3 Serial ATA status */ - P3DD, 4, - , 4, - P3IS, 4, - Offset(0x2AC), /* Port 3 Serial ATA control */ - P3DI, 4, - Offset(0x2B0), /* Port 3 Serial ATA error */ - , 16, - P3PR, 1, - } - } - - - #include "acpi/routing.asl" - - Scope(\_SB) { - - Method(OSFL, 0){ - - if(LNotEqual(OSVR, Ones)) {Return(OSVR)} /* OS version was already detected */ - - if(CondRefOf(\_OSI)) - { - Store(1, OSVR) /* Assume some form of XP */ - if (\_OSI("Windows 2006")) /* Vista */ - { - Store(2, OSVR) - } - } else { - If(WCMP(\_OS,"Linux")) { - Store(3, OSVR) /* Linux */ - } Else { - Store(4, OSVR) /* Gotta be WinCE */ - } - } - Return(OSVR) - } - - Method(_PIC, 0x01, NotSerialized) - { - If (Arg0) - { - \_SB.CIRQ() - } - Store(Arg0, PMOD) - } - Method(CIRQ, 0x00, NotSerialized){ - Store(0, PIRA) - Store(0, PIRB) - Store(0, PIRC) - Store(0, PIRD) - Store(0, PIRE) - Store(0, PIRF) - Store(0, PIRG) - Store(0, PIRH) - } - - Name(IRQB, ResourceTemplate(){ - IRQ(Level,ActiveLow,Shared){15} - }) - - Name(IRQP, ResourceTemplate(){ - IRQ(Level,ActiveLow,Exclusive){3, 4, 5, 7, 10, 11, 12, 15} - }) - - Name(PITF, ResourceTemplate(){ - IRQ(Level,ActiveLow,Exclusive){9} - }) - - Device(INTA) { - Name(_HID, EISAID("PNP0C0F")) - Name(_UID, 1) - - Method(_STA, 0) { - if (PIRA) { - Return(0x0B) /* sata is invisible */ - } else { - Return(0x09) /* sata is disabled */ - } - } /* End Method(_SB.INTA._STA) */ - - Method(_DIS ,0) { - /* DBGO("\\_SB\\LNKA\\_DIS\n") */ - Store(0, PIRA) - } /* End Method(_SB.INTA._DIS) */ - - Method(_PRS ,0) { - /* DBGO("\\_SB\\LNKA\\_PRS\n") */ - Return(IRQP) - } /* Method(_SB.INTA._PRS) */ - - Method(_CRS ,0) { - /* DBGO("\\_SB\\LNKA\\_CRS\n") */ - CreateWordField(IRQB, 0x1, IRQN) - ShiftLeft(1, PIRA, IRQN) - Return(IRQB) - } /* Method(_SB.INTA._CRS) */ - - Method(_SRS, 1) { - /* DBGO("\\_SB\\LNKA\\_CRS\n") */ - CreateWordField(ARG0, 1, IRQM) - - /* Use lowest available IRQ */ - FindSetRightBit(IRQM, Local0) - if (Local0) { - Decrement(Local0) - } - Store(Local0, PIRA) - } /* End Method(_SB.INTA._SRS) */ - } /* End Device(INTA) */ - - Device(INTB) { - Name(_HID, EISAID("PNP0C0F")) - Name(_UID, 2) - - Method(_STA, 0) { - if (PIRB) { - Return(0x0B) /* sata is invisible */ - } else { - Return(0x09) /* sata is disabled */ - } - } /* End Method(_SB.INTB._STA) */ - - Method(_DIS ,0) { - /* DBGO("\\_SB\\LNKB\\_DIS\n") */ - Store(0, PIRB) - } /* End Method(_SB.INTB._DIS) */ - - Method(_PRS ,0) { - /* DBGO("\\_SB\\LNKB\\_PRS\n") */ - Return(IRQP) - } /* Method(_SB.INTB._PRS) */ - - Method(_CRS ,0) { - /* DBGO("\\_SB\\LNKB\\_CRS\n") */ - CreateWordField(IRQB, 0x1, IRQN) - ShiftLeft(1, PIRB, IRQN) - Return(IRQB) - } /* Method(_SB.INTB._CRS) */ - - Method(_SRS, 1) { - /* DBGO("\\_SB\\LNKB\\_CRS\n") */ - CreateWordField(ARG0, 1, IRQM) - - /* Use lowest available IRQ */ - FindSetRightBit(IRQM, Local0) - if (Local0) { - Decrement(Local0) - } - Store(Local0, PIRB) - } /* End Method(_SB.INTB._SRS) */ - } /* End Device(INTB) */ - - Device(INTC) { - Name(_HID, EISAID("PNP0C0F")) - Name(_UID, 3) - - Method(_STA, 0) { - if (PIRC) { - Return(0x0B) /* sata is invisible */ - } else { - Return(0x09) /* sata is disabled */ - } - } /* End Method(_SB.INTC._STA) */ - - Method(_DIS ,0) { - /* DBGO("\\_SB\\LNKC\\_DIS\n") */ - Store(0, PIRC) - } /* End Method(_SB.INTC._DIS) */ - - Method(_PRS ,0) { - /* DBGO("\\_SB\\LNKC\\_PRS\n") */ - Return(IRQP) - } /* Method(_SB.INTC._PRS) */ - - Method(_CRS ,0) { - /* DBGO("\\_SB\\LNKC\\_CRS\n") */ - CreateWordField(IRQB, 0x1, IRQN) - ShiftLeft(1, PIRC, IRQN) - Return(IRQB) - } /* Method(_SB.INTC._CRS) */ - - Method(_SRS, 1) { - /* DBGO("\\_SB\\LNKC\\_CRS\n") */ - CreateWordField(ARG0, 1, IRQM) - - /* Use lowest available IRQ */ - FindSetRightBit(IRQM, Local0) - if (Local0) { - Decrement(Local0) - } - Store(Local0, PIRC) - } /* End Method(_SB.INTC._SRS) */ - } /* End Device(INTC) */ - - Device(INTD) { - Name(_HID, EISAID("PNP0C0F")) - Name(_UID, 4) - - Method(_STA, 0) { - if (PIRD) { - Return(0x0B) /* sata is invisible */ - } else { - Return(0x09) /* sata is disabled */ - } - } /* End Method(_SB.INTD._STA) */ - - Method(_DIS ,0) { - /* DBGO("\\_SB\\LNKD\\_DIS\n") */ - Store(0, PIRD) - } /* End Method(_SB.INTD._DIS) */ - - Method(_PRS ,0) { - /* DBGO("\\_SB\\LNKD\\_PRS\n") */ - Return(IRQP) - } /* Method(_SB.INTD._PRS) */ - - Method(_CRS ,0) { - /* DBGO("\\_SB\\LNKD\\_CRS\n") */ - CreateWordField(IRQB, 0x1, IRQN) - ShiftLeft(1, PIRD, IRQN) - Return(IRQB) - } /* Method(_SB.INTD._CRS) */ - - Method(_SRS, 1) { - /* DBGO("\\_SB\\LNKD\\_CRS\n") */ - CreateWordField(ARG0, 1, IRQM) - - /* Use lowest available IRQ */ - FindSetRightBit(IRQM, Local0) - if (Local0) { - Decrement(Local0) - } - Store(Local0, PIRD) - } /* End Method(_SB.INTD._SRS) */ - } /* End Device(INTD) */ - - Device(INTE) { - Name(_HID, EISAID("PNP0C0F")) - Name(_UID, 5) - - Method(_STA, 0) { - if (PIRE) { - Return(0x0B) /* sata is invisible */ - } else { - Return(0x09) /* sata is disabled */ - } - } /* End Method(_SB.INTE._STA) */ - - Method(_DIS ,0) { - /* DBGO("\\_SB\\LNKE\\_DIS\n") */ - Store(0, PIRE) - } /* End Method(_SB.INTE._DIS) */ - - Method(_PRS ,0) { - /* DBGO("\\_SB\\LNKE\\_PRS\n") */ - Return(IRQP) - } /* Method(_SB.INTE._PRS) */ - - Method(_CRS ,0) { - /* DBGO("\\_SB\\LNKE\\_CRS\n") */ - CreateWordField(IRQB, 0x1, IRQN) - ShiftLeft(1, PIRE, IRQN) - Return(IRQB) - } /* Method(_SB.INTE._CRS) */ - - Method(_SRS, 1) { - /* DBGO("\\_SB\\LNKE\\_CRS\n") */ - CreateWordField(ARG0, 1, IRQM) - - /* Use lowest available IRQ */ - FindSetRightBit(IRQM, Local0) - if (Local0) { - Decrement(Local0) - } - Store(Local0, PIRE) - } /* End Method(_SB.INTE._SRS) */ - } /* End Device(INTE) */ - - Device(INTF) { - Name(_HID, EISAID("PNP0C0F")) - Name(_UID, 6) - - Method(_STA, 0) { - if (PIRF) { - Return(0x0B) /* sata is invisible */ - } else { - Return(0x09) /* sata is disabled */ - } - } /* End Method(_SB.INTF._STA) */ - - Method(_DIS ,0) { - /* DBGO("\\_SB\\LNKF\\_DIS\n") */ - Store(0, PIRF) - } /* End Method(_SB.INTF._DIS) */ - - Method(_PRS ,0) { - /* DBGO("\\_SB\\LNKF\\_PRS\n") */ - Return(PITF) - } /* Method(_SB.INTF._PRS) */ - - Method(_CRS ,0) { - /* DBGO("\\_SB\\LNKF\\_CRS\n") */ - CreateWordField(IRQB, 0x1, IRQN) - ShiftLeft(1, PIRF, IRQN) - Return(IRQB) - } /* Method(_SB.INTF._CRS) */ - - Method(_SRS, 1) { - /* DBGO("\\_SB\\LNKF\\_CRS\n") */ - CreateWordField(ARG0, 1, IRQM) - - /* Use lowest available IRQ */ - FindSetRightBit(IRQM, Local0) - if (Local0) { - Decrement(Local0) - } - Store(Local0, PIRF) - } /* End Method(_SB.INTF._SRS) */ - } /* End Device(INTF) */ - - Device(INTG) { - Name(_HID, EISAID("PNP0C0F")) - Name(_UID, 7) - - Method(_STA, 0) { - if (PIRG) { - Return(0x0B) /* sata is invisible */ - } else { - Return(0x09) /* sata is disabled */ - } - } /* End Method(_SB.INTG._STA) */ - - Method(_DIS ,0) { - /* DBGO("\\_SB\\LNKG\\_DIS\n") */ - Store(0, PIRG) - } /* End Method(_SB.INTG._DIS) */ - - Method(_PRS ,0) { - /* DBGO("\\_SB\\LNKG\\_PRS\n") */ - Return(IRQP) - } /* Method(_SB.INTG._CRS) */ - - Method(_CRS ,0) { - /* DBGO("\\_SB\\LNKG\\_CRS\n") */ - CreateWordField(IRQB, 0x1, IRQN) - ShiftLeft(1, PIRG, IRQN) - Return(IRQB) - } /* Method(_SB.INTG._CRS) */ - - Method(_SRS, 1) { - /* DBGO("\\_SB\\LNKG\\_CRS\n") */ - CreateWordField(ARG0, 1, IRQM) - - /* Use lowest available IRQ */ - FindSetRightBit(IRQM, Local0) - if (Local0) { - Decrement(Local0) - } - Store(Local0, PIRG) - } /* End Method(_SB.INTG._SRS) */ - } /* End Device(INTG) */ - - Device(INTH) { - Name(_HID, EISAID("PNP0C0F")) - Name(_UID, 8) - - Method(_STA, 0) { - if (PIRH) { - Return(0x0B) /* sata is invisible */ - } else { - Return(0x09) /* sata is disabled */ - } - } /* End Method(_SB.INTH._STA) */ - - Method(_DIS ,0) { - /* DBGO("\\_SB\\LNKH\\_DIS\n") */ - Store(0, PIRH) - } /* End Method(_SB.INTH._DIS) */ - - Method(_PRS ,0) { - /* DBGO("\\_SB\\LNKH\\_PRS\n") */ - Return(IRQP) - } /* Method(_SB.INTH._CRS) */ - - Method(_CRS ,0) { - /* DBGO("\\_SB\\LNKH\\_CRS\n") */ - CreateWordField(IRQB, 0x1, IRQN) - ShiftLeft(1, PIRH, IRQN) - Return(IRQB) - } /* Method(_SB.INTH._CRS) */ - - Method(_SRS, 1) { - /* DBGO("\\_SB\\LNKH\\_CRS\n") */ - CreateWordField(ARG0, 1, IRQM) - - /* Use lowest available IRQ */ - FindSetRightBit(IRQM, Local0) - if (Local0) { - Decrement(Local0) - } - Store(Local0, PIRH) - } /* End Method(_SB.INTH._SRS) */ - } /* End Device(INTH) */ - - } /* End Scope(_SB) */ - - #include - - /* Wake status package */ - Name(WKST,Package(){Zero, Zero}) - - /* - * \_PTS - Prepare to Sleep method - * - * Entry: - * Arg0=The value of the sleeping state S1=1, S2=2, etc - * - * Exit: - * -none- - * - * The _PTS control method is executed at the beginning of the sleep process - * for S1-S5. The sleeping value is passed to the _PTS control method. This - * control method may be executed a relatively long time before entering the - * sleep state and the OS may abort the operation without notification to - * the ACPI driver. This method cannot modify the configuration or power - * state of any device in the system. - */ - Method(\_PTS, 1) { - /* DBGO("\\_PTS\n") */ - /* DBGO("From S0 to S") */ - /* DBGO(Arg0) */ - /* DBGO("\n") */ - - /* Don't allow PCIRST# to reset USB */ - if (LEqual(Arg0,3)){ - Store(0,URRE) - } - - /* Clear sleep SMI status flag and enable sleep SMI trap. */ - /*Store(One, CSSM) - Store(One, SSEN)*/ - - /* On older chips, clear PciExpWakeDisEn */ - /*if (LLessEqual(\_SB.SBRI, 0x13)) { - * Store(0,\_SB.PWDE) - *} - */ - - /* Clear wake status structure. */ - Store(0, Index(WKST,0)) - Store(0, Index(WKST,1)) - } /* End Method(\_PTS) */ - - /* - * The following method results in a "not a valid reserved NameSeg" - * warning so I have commented it out for the duration. It isn't - * used, so it could be removed. - * - * - * \_GTS OEM Going To Sleep method - * - * Entry: - * Arg0=The value of the sleeping state S1=1, S2=2 - * - * Exit: - * -none- - * - * Method(\_GTS, 1) { - * DBGO("\\_GTS\n") - * DBGO("From S0 to S") - * DBGO(Arg0) - * DBGO("\n") - * } - */ - - /* - * \_BFS OEM Back From Sleep method - * - * Entry: - * Arg0=The value of the sleeping state S1=1, S2=2 - * - * Exit: - * -none- - */ - Method(\_BFS, 1) { - /* DBGO("\\_BFS\n") */ - /* DBGO("From S") */ - /* DBGO(Arg0) */ - /* DBGO(" to S0\n") */ - } - - /* - * \_WAK System Wake method - * - * Entry: - * Arg0=The value of the sleeping state S1=1, S2=2 - * - * Exit: - * Return package of 2 DWords - * Dword 1 - Status - * 0x00000000 wake succeeded - * 0x00000001 Wake was signaled but failed due to lack of power - * 0x00000002 Wake was signaled but failed due to thermal condition - * Dword 2 - Power Supply state - * if non-zero the effective S-state the power supply entered - */ - Method(\_WAK, 1) { - /* DBGO("\\_WAK\n") */ - /* DBGO("From S") */ - /* DBGO(Arg0) */ - /* DBGO(" to S0\n") */ - - /* Re-enable HPET */ - Store(1,HPDE) - - /* Restore PCIRST# so it resets USB */ - if (LEqual(Arg0,3)){ - Store(1,URRE) - } - - /* Arbitrarily clear PciExpWakeStatus */ - Store(PWST, Local1) - Store(Local1, PWST) - - /* if (DeRefOf(Index(WKST,0))) { - * Store(0, Index(WKST,1)) - * } else { - * Store(Arg0, Index(WKST,1)) - * } - */ - Return(WKST) - } /* End Method(\_WAK) */ - - Scope(\_GPE) { /* Start Scope GPE */ - /* General event 0 */ - /* Method(_L00) { - * DBGO("\\_GPE\\_L00\n") - * } - */ - - /* General event 1 */ - /* Method(_L01) { - * DBGO("\\_GPE\\_L00\n") - * } - */ - - /* General event 2 */ - /* Method(_L02) { - * DBGO("\\_GPE\\_L00\n") - * } - */ - - /* General event 3 */ - Method(_L03) { - /* DBGO("\\_GPE\\_L00\n") */ - Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ - } - - /* General event 4 */ - /* Method(_L04) { - * DBGO("\\_GPE\\_L00\n") - * } - */ - - /* General event 5 */ - /* Method(_L05) { - * DBGO("\\_GPE\\_L00\n") - * } - */ - - /* General event 6 - Used for GPM6, moved to USB.asl */ - /* Method(_L06) { - * DBGO("\\_GPE\\_L00\n") - * } - */ - - /* General event 7 - Used for GPM7, moved to USB.asl */ - /* Method(_L07) { - * DBGO("\\_GPE\\_L07\n") - * } - */ - - /* Legacy PM event */ - Method(_L08) { - /* DBGO("\\_GPE\\_L08\n") */ - } - - /* Temp warning (TWarn) event */ - Method(_L09) { - /* DBGO("\\_GPE\\_L09\n") */ - /* Notify (\_TZ.TZ00, 0x80) */ - } - - /* Reserved */ - /* Method(_L0A) { - * DBGO("\\_GPE\\_L0A\n") - * } - */ - - /* USB controller PME# */ - Method(_L0B) { - /* DBGO("\\_GPE\\_L0B\n") */ - Notify(\_SB.PCI0.UOH1, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(\_SB.PCI0.UOH2, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(\_SB.PCI0.UOH3, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(\_SB.PCI0.UOH4, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(\_SB.PCI0.UOH5, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(\_SB.PCI0.UOH6, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(\_SB.PCI0.UEH1, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ - } - - /* AC97 controller PME# */ - /* Method(_L0C) { - * DBGO("\\_GPE\\_L0C\n") - * } - */ - - /* OtherTherm PME# */ - /* Method(_L0D) { - * DBGO("\\_GPE\\_L0D\n") - * } - */ - - /* GPM9 SCI event - Moved to USB.asl */ - /* Method(_L0E) { - * DBGO("\\_GPE\\_L0E\n") - * } - */ - - /* PCIe HotPlug event */ - /* Method(_L0F) { - * DBGO("\\_GPE\\_L0F\n") - * } - */ - - /* ExtEvent0 SCI event */ - Method(_L10) { - /* DBGO("\\_GPE\\_L10\n") */ - } - - - /* ExtEvent1 SCI event */ - Method(_L11) { - /* DBGO("\\_GPE\\_L11\n") */ - } - - /* PCIe PME# event */ - /* Method(_L12) { - * DBGO("\\_GPE\\_L12\n") - * } - */ - - /* GPM0 SCI event - Moved to USB.asl */ - /* Method(_L13) { - * DBGO("\\_GPE\\_L13\n") - * } - */ - - /* GPM1 SCI event - Moved to USB.asl */ - /* Method(_L14) { - * DBGO("\\_GPE\\_L14\n") - * } - */ - - /* GPM2 SCI event - Moved to USB.asl */ - /* Method(_L15) { - * DBGO("\\_GPE\\_L15\n") - * } - */ - - /* GPM3 SCI event - Moved to USB.asl */ - /* Method(_L16) { - * DBGO("\\_GPE\\_L16\n") - * } - */ - - /* GPM8 SCI event - Moved to USB.asl */ - /* Method(_L17) { - * DBGO("\\_GPE\\_L17\n") - * } - */ - - /* GPIO0 or GEvent8 event */ - Method(_L18) { - /* DBGO("\\_GPE\\_L18\n") */ - Notify(\_SB.PCI0.PBR2, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(\_SB.PCI0.PBR4, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(\_SB.PCI0.PBR5, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(\_SB.PCI0.PBR6, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(\_SB.PCI0.PBR7, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ - } - - /* GPM4 SCI event - Moved to USB.asl */ - /* Method(_L19) { - * DBGO("\\_GPE\\_L19\n") - * } - */ - - /* GPM5 SCI event - Moved to USB.asl */ - /* Method(_L1A) { - * DBGO("\\_GPE\\_L1A\n") - * } - */ - - /* Azalia SCI event */ - Method(_L1B) { - /* DBGO("\\_GPE\\_L1B\n") */ - Notify(\_SB.PCI0.AZHD, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ - } - - /* GPM6 SCI event - Reassigned to _L06 */ - /* Method(_L1C) { - * DBGO("\\_GPE\\_L1C\n") - * } - */ - - /* GPM7 SCI event - Reassigned to _L07 */ - /* Method(_L1D) { - * DBGO("\\_GPE\\_L1D\n") - * } - */ - - /* GPIO2 or GPIO66 SCI event */ - /* Method(_L1E) { - * DBGO("\\_GPE\\_L1E\n") - * } - */ - - /* SATA SCI event - Moved to sata.asl */ - /* Method(_L1F) { - * DBGO("\\_GPE\\_L1F\n") - * } - */ - - } /* End Scope GPE */ - - #include "acpi/usb.asl" - - /* System Bus */ - Scope(\_SB) { /* Start \_SB scope */ - #include /* global utility methods expected within the \_SB scope */ - - /* _SB.PCI0 */ - /* Note: Only need HID on Primary Bus */ - Device(PCI0) { - External (TOM1) - External (TOM2) - Name(_HID, EISAID("PNP0A03")) - Name(_ADR, 0x00180000) /* Dev# = BSP Dev#, Func# = 0 */ - Method(_BBN, 0) { /* Bus number = 0 */ - Return(0) - } - Method(_STA, 0) { - /* DBGO("\\_SB\\PCI0\\_STA\n") */ - Return(0x0B) /* Status is visible */ - } - - Method(_PRT,0) { - If(PMOD){ Return(APR0) } /* APIC mode */ - Return (PR0) /* PIC Mode */ - } /* end _PRT */ - - /* Describe the Northbridge devices */ - Device(AMRT) { - Name(_ADR, 0x00000000) - } /* end AMRT */ - - /* The internal GFX bridge */ - Device(AGPB) { - Name(_ADR, 0x00010000) - Name(_PRW, Package() {0x18, 4}) - Method(_PRT,0) { - Return (APR1) - } - } /* end AGPB */ - - /* The external GFX bridge */ - Device(PBR2) { - Name(_ADR, 0x00020000) - Name(_PRW, Package() {0x18, 4}) - Method(_PRT,0) { - If(PMOD){ Return(APS2) } /* APIC mode */ - Return (PS2) /* PIC Mode */ - } /* end _PRT */ - } /* end PBR2 */ - - /* Dev3 is also an external GFX bridge, not used in Herring */ - - Device(PBR4) { - Name(_ADR, 0x00040000) - Name(_PRW, Package() {0x18, 4}) - Method(_PRT,0) { - If(PMOD){ Return(APS4) } /* APIC mode */ - Return (PS4) /* PIC Mode */ - } /* end _PRT */ - } /* end PBR4 */ - - Device(PBR5) { - Name(_ADR, 0x00050000) - Name(_PRW, Package() {0x18, 4}) - Method(_PRT,0) { - If(PMOD){ Return(APS5) } /* APIC mode */ - Return (PS5) /* PIC Mode */ - } /* end _PRT */ - } /* end PBR5 */ - - Device(PBR6) { - Name(_ADR, 0x00060000) - Name(_PRW, Package() {0x18, 4}) - Method(_PRT,0) { - If(PMOD){ Return(APS6) } /* APIC mode */ - Return (PS6) /* PIC Mode */ - } /* end _PRT */ - } /* end PBR6 */ - - /* The onboard EtherNet chip */ - Device(PBR7) { - Name(_ADR, 0x00070000) - Name(_PRW, Package() {0x18, 4}) - Method(_PRT,0) { - If(PMOD){ Return(APS7) } /* APIC mode */ - Return (PS7) /* PIC Mode */ - } /* end _PRT */ - } /* end PBR7 */ - - /* GPP */ - Device(PBR9) { - Name(_ADR, 0x00090000) - Name(_PRW, Package() {0x18, 4}) - Method(_PRT,0) { - If(PMOD){ Return(APS9) } /* APIC mode */ - Return (PS9) /* PIC Mode */ - } /* end _PRT */ - } /* end PBR9 */ - - Device(PBRa) { - Name(_ADR, 0x000A0000) - Name(_PRW, Package() {0x18, 4}) - Method(_PRT,0) { - If(PMOD){ Return(APSa) } /* APIC mode */ - Return (PSa) /* PIC Mode */ - } /* end _PRT */ - } /* end PBRa */ - - Device(PE20) { - Name(_ADR, 0x00150000) - Name(_PRW, Package() {0x18, 4}) - Method(_PRT,0) { - If(PMOD){ Return(APE0) } /* APIC mode */ - Return (PE0) /* PIC Mode */ - } /* end _PRT */ - } /* end PE20 */ - Device(PE21) { - Name(_ADR, 0x00150001) - Name(_PRW, Package() {0x18, 4}) - Method(_PRT,0) { - If(PMOD){ Return(APE1) } /* APIC mode */ - Return (PE1) /* PIC Mode */ - } /* end _PRT */ - } /* end PE21 */ - Device(PE22) { - Name(_ADR, 0x00150002) - Name(_PRW, Package() {0x18, 4}) - Method(_PRT,0) { - If(PMOD){ Return(APE2) } /* APIC mode */ - Return (APE2) /* PIC Mode */ - } /* end _PRT */ - } /* end PE22 */ - Device(PE23) { - Name(_ADR, 0x00150003) - Name(_PRW, Package() {0x18, 4}) - Method(_PRT,0) { - If(PMOD){ Return(APE3) } /* APIC mode */ - Return (PE3) /* PIC Mode */ - } /* end _PRT */ - } /* end PE23 */ - - /* PCI slot 1, 2, 3 */ - Device(PIBR) { - Name(_ADR, 0x00140004) - Name(_PRW, Package() {0x18, 4}) - - Method(_PRT, 0) { - Return (PCIB) - } - } - - /* Describe the Southbridge devices */ - Device(STCR) { - Name(_ADR, 0x00110000) - #include "acpi/sata.asl" - } /* end STCR */ - - Device(UOH1) { - Name(_ADR, 0x00120000) - Name(_PRW, Package() {0x0B, 3}) - } /* end UOH1 */ - - Device(UOH2) { - Name(_ADR, 0x00120002) - Name(_PRW, Package() {0x0B, 3}) - } /* end UOH2 */ - - Device(UOH3) { - Name(_ADR, 0x00130000) - Name(_PRW, Package() {0x0B, 3}) - } /* end UOH3 */ - - Device(UOH4) { - Name(_ADR, 0x00130002) - Name(_PRW, Package() {0x0B, 3}) - } /* end UOH4 */ - - Device(UOH5) { - Name(_ADR, 0x00160000) - Name(_PRW, Package() {0x0B, 3}) - } /* end UOH5 */ - - Device(UOH6) { - Name(_ADR, 0x00160002) - Name(_PRW, Package() {0x0B, 3}) - } /* end UOH5 */ - - Device(UEH1) { - Name(_ADR, 0x00140005) - Name(_PRW, Package() {0x0B, 3}) - } /* end UEH1 */ - - Device(SBUS) { - Name(_ADR, 0x00140000) - } /* end SBUS */ - - Device(AZHD) { - Name(_ADR, 0x00140002) - OperationRegion(AZPD, PCI_Config, 0x00, 0x100) - Field(AZPD, AnyAcc, NoLock, Preserve) { - offset (0x42), - NSDI, 1, - NSDO, 1, - NSEN, 1, - offset (0x44), - IPCR, 4, - offset (0x54), - PWST, 2, - , 6, - PMEB, 1, - , 6, - PMST, 1, - offset (0x62), - MMCR, 1, - offset (0x64), - MMLA, 32, - offset (0x68), - MMHA, 32, - offset (0x6C), - MMDT, 16, - } - - Method(_INI) { - If(LEqual(OSVR,3)){ /* If we are running Linux */ - Store(zero, NSEN) - Store(one, NSDO) - Store(one, NSDI) - } - } - } /* end AZHD */ - - Device(LIBR) { - Name(_ADR, 0x00140003) - /* Method(_INI) { - * DBGO("\\_SB\\PCI0\\LpcIsaBr\\_INI\n") - } */ /* End Method(_SB.SBRDG._INI) */ - - /* Real Time Clock Device */ - Device(RTC0) { - Name(_HID, EISAID("PNP0B01")) /* AT Real Time Clock */ - Name(_CRS, ResourceTemplate() { - IRQNoFlags(){8} - IO(Decode16,0x0070, 0x0070, 0, 2) - /* IO(Decode16,0x0070, 0x0070, 0, 4) */ - }) - } /* End Device(_SB.PCI0.LpcIsaBr.RTC0) */ - - Device(TMR) { /* Timer */ - Name(_HID,EISAID("PNP0100")) /* System Timer */ - Name(_CRS, ResourceTemplate() { - IRQNoFlags(){0} - IO(Decode16, 0x0040, 0x0040, 0, 4) - /* IO(Decode16, 0x0048, 0x0048, 0, 4) */ - }) - } /* End Device(_SB.PCI0.LpcIsaBr.TMR) */ - - Device(SPKR) { /* Speaker */ - Name(_HID,EISAID("PNP0800")) /* AT style speaker */ - Name(_CRS, ResourceTemplate() { - IO(Decode16, 0x0061, 0x0061, 0, 1) - }) - } /* End Device(_SB.PCI0.LpcIsaBr.SPKR) */ - - Device(PIC) { - Name(_HID,EISAID("PNP0000")) /* AT Interrupt Controller */ - Name(_CRS, ResourceTemplate() { - IRQNoFlags(){2} - IO(Decode16,0x0020, 0x0020, 0, 2) - IO(Decode16,0x00A0, 0x00A0, 0, 2) - /* IO(Decode16, 0x00D0, 0x00D0, 0x10, 0x02) */ - /* IO(Decode16, 0x04D0, 0x04D0, 0x10, 0x02) */ - }) - } /* End Device(_SB.PCI0.LpcIsaBr.PIC) */ - - Device(MAD) { /* 8257 DMA */ - Name(_HID,EISAID("PNP0200")) /* Hardware Device ID */ - Name(_CRS, ResourceTemplate() { - DMA(Compatibility,BusMaster,Transfer8){4} - IO(Decode16, 0x0000, 0x0000, 0x10, 0x10) - IO(Decode16, 0x0081, 0x0081, 0x00, 0x03) - IO(Decode16, 0x0087, 0x0087, 0x00, 0x01) - IO(Decode16, 0x0089, 0x0089, 0x00, 0x03) - IO(Decode16, 0x008F, 0x008F, 0x00, 0x01) - IO(Decode16, 0x00C0, 0x00C0, 0x10, 0x20) - }) /* End Name(_SB.PCI0.LpcIsaBr.MAD._CRS) */ - } /* End Device(_SB.PCI0.LpcIsaBr.MAD) */ - - Device(COPR) { - Name(_HID,EISAID("PNP0C04")) /* Math Coprocessor */ - Name(_CRS, ResourceTemplate() { - IO(Decode16, 0x00F0, 0x00F0, 0, 0x10) - IRQNoFlags(){13} - }) - } /* End Device(_SB.PCI0.LpcIsaBr.COPR) */ -#if 0 - Device(HPTM) { - Name(_HID,EISAID("PNP0103")) - Name(CRS,ResourceTemplate() { - Memory32Fixed(ReadOnly,0xFED00000, 0x00000400, HPT) /* 1kb reserved space */ - }) - Method(_STA, 0) { - Return(0x0F) /* sata is visible */ - } - Method(_CRS, 0) { - CreateDwordField(CRS, ^HPT._BAS, HPBX) - Store(HPBA, HPBX) - Return(CRS) - } - } /* End Device(_SB.PCI0.LpcIsaBr.COPR) */ -#endif - } /* end LIBR */ - - Device(HPBR) { - Name(_ADR, 0x00140004) - } /* end HostPciBr */ - - Device(ACAD) { - Name(_ADR, 0x00140005) - } /* end Ac97audio */ - - Device(ACMD) { - Name(_ADR, 0x00140006) - } /* end Ac97modem */ - - Name(CRES, ResourceTemplate() { - IO(Decode16, 0x0CF8, 0x0CF8, 1, 8) - - WORDIO(ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, - 0x0000, /* address granularity */ - 0x0000, /* range minimum */ - 0x0CF7, /* range maximum */ - 0x0000, /* translation */ - 0x0CF8 /* length */ - ) - - WORDIO(ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, - 0x0000, /* address granularity */ - 0x0D00, /* range minimum */ - 0xFFFF, /* range maximum */ - 0x0000, /* translation */ - 0xF300 /* length */ - ) -#if 0 - Memory32Fixed(READWRITE, 0, 0xA0000, BSMM) - Memory32Fixed(READONLY, 0x000A0000, 0x00020000, VGAM) /* VGA memory space */ - Memory32Fixed(READONLY, 0x000C0000, 0x00020000, EMM1) /* Assume C0000-E0000 empty */ - Memory32Fixed(READONLY, 0x000E0000, 0x00020000, RDBS) /* BIOS ROM area */ - - /* DRAM Memory from 1MB to TopMem */ - Memory32Fixed(READWRITE, 0x00100000, 0, DMLO) /* 1MB to TopMem */ - - /* BIOS space just below 4GB */ - DWORDMemory( - ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite, - 0x00, /* Granularity */ - 0x00000000, /* Min */ - 0x00000000, /* Max */ - 0x00000000, /* Translation */ - 0x00000000, /* Max-Min, RLEN */ - ,, - PCBM - ) - - /* DRAM memory from 4GB to TopMem2 */ - QWORDMemory(ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite, - 0xFFFFFFFF, /* Granularity */ - 0x00000000, /* Min */ - 0x00000000, /* Max */ - 0x00000000, /* Translation */ - 0x00000000, /* Max-Min, RLEN */ - ,, - DMHI - ) - - /* BIOS space just below 16EB */ - QWORDMemory(ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite, - 0xFFFFFFFF, /* Granularity */ - 0x00000000, /* Min */ - 0x00000000, /* Max */ - 0x00000000, /* Translation */ - 0x00000000, /* Max-Min, RLEN */ - ,, - PEBM - ) -#endif - /* memory space for PCI BARs below 4GB */ - Memory32Fixed(ReadOnly, 0x00000000, 0x00000000, MMIO) - }) /* End Name(_SB.PCI0.CRES) */ - - Method(_CRS, 0) { - /* DBGO("\\_SB\\PCI0\\_CRS\n") */ -#if 0 - CreateDWordField(CRES, ^EMM1._BAS, EM1B) - CreateDWordField(CRES, ^EMM1._LEN, EM1L) - CreateDWordField(CRES, ^DMLO._BAS, DMLB) - CreateDWordField(CRES, ^DMLO._LEN, DMLL) - CreateDWordField(CRES, ^PCBM._MIN, PBMB) - CreateDWordField(CRES, ^PCBM._LEN, PBML) - - CreateQWordField(CRES, ^DMHI._MIN, DMHB) - CreateQWordField(CRES, ^DMHI._LEN, DMHL) - CreateQWordField(CRES, ^PEBM._MIN, EBMB) - CreateQWordField(CRES, ^PEBM._LEN, EBML) - - If(LGreater(LOMH, 0xC0000)){ - Store(0xC0000, EM1B) /* Hole above C0000 and below E0000 */ - Subtract(LOMH, 0xC0000, EM1L) /* subtract start, assumes allocation from C0000 going up */ - } - - /* Set size of memory from 1MB to TopMem */ - Subtract(TOM1, 0x100000, DMLL) - - /* - * If(LNotEqual(TOM2, 0x00000000)){ - * Store(0x100000000,DMHB) DRAM from 4GB to TopMem2 - * Subtract(TOM2, 0x100000000, DMHL) - * } - */ - - /* If there is no memory above 4GB, put the BIOS just below 4GB */ - If(LEqual(TOM2, 0x00000000)){ - Store(PBAD,PBMB) /* Reserve the "BIOS" space */ - Store(PBLN,PBML) - } - Else { /* Otherwise, put the BIOS just below 16EB */ - ShiftLeft(PBAD,16,EBMB) /* Reserve the "BIOS" space */ - Store(PBLN,EBML) - } -#endif - CreateDWordField(CRES, ^MMIO._BAS, MM1B) - CreateDWordField(CRES, ^MMIO._LEN, MM1L) - /* - * Declare memory between TOM1 and 4GB as available - * for PCI MMIO. - * Use ShiftLeft to avoid 64bit constant (for XP). - * This will work even if the OS does 32bit arithmetic, as - * 32bit (0x00000000 - TOM1) will wrap and give the same - * result as 64bit (0x100000000 - TOM1). - */ - Store(TOM1, MM1B) - ShiftLeft(0x10000000, 4, Local0) - Subtract(Local0, TOM1, Local0) - Store(Local0, MM1L) - - Return(CRES) /* note to change the Name buffer */ - } /* end of Method(_SB.PCI0._CRS) */ - - /* - * - * FIRST METHOD CALLED UPON BOOT - * - * 1. If debugging, print current OS and ACPI interpreter. - * 2. Get PCI Interrupt routing from ACPI VSM, this - * value is based on user choice in BIOS setup. - */ - Method(_INI, 0) { - /* DBGO("\\_SB\\_INI\n") */ - /* DBGO(" DSDT.ASL code from ") */ - /* DBGO(__DATE__) */ - /* DBGO(" ") */ - /* DBGO(__TIME__) */ - /* DBGO("\n Sleep states supported: ") */ - /* DBGO("\n") */ - /* DBGO(" \\_OS=") */ - /* DBGO(\_OS) */ - /* DBGO("\n \\_REV=") */ - /* DBGO(\_REV) */ - /* DBGO("\n") */ - - /* Determine the OS we're running on */ - OSFL() - - /* On older chips, clear PciExpWakeDisEn */ - /*if (LLessEqual(\SBRI, 0x13)) { - * Store(0,\PWDE) - * } - */ - } /* End Method(_SB._INI) */ - } /* End Device(PCI0) */ - - Device(PWRB) { /* Start Power button device */ - Name(_HID, EISAID("PNP0C0C")) - Name(_UID, 0xAA) - Name(_PRW, Package () {3, 0x04}) /* wake from S1-S4 */ - Name(_STA, 0x0B) /* sata is invisible */ - } - } /* End \_SB scope */ - - Scope(\_SI) { - Method(_SST, 1) { - /* DBGO("\\_SI\\_SST\n") */ - /* DBGO(" New Indicator state: ") */ - /* DBGO(Arg0) */ - /* DBGO("\n") */ - } - } /* End Scope SI */ -} -/* End of ASL file */ diff --git a/src/mainboard/avalue/eax-785e/get_bus_conf.c b/src/mainboard/avalue/eax-785e/get_bus_conf.c deleted file mode 100644 index 6b5ae68bc6..0000000000 --- a/src/mainboard/avalue/eax-785e/get_bus_conf.c +++ /dev/null @@ -1,44 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include -#include -#include - -/* Global variables for MB layouts and these will be shared by irqtable mptable -* and acpi_tables busnum is default. -*/ -u32 apicid_sb800; - -void get_bus_conf(void) -{ - u32 apicid_base; - - get_default_pci1234(1); - - sysconf.sbdn = (sysconf.hcdn[0] & 0xff); - - - pirq_router_bus = (sysconf.pci1234[0] >> 16) & 0xff; - - /* I/O APICs: APIC ID Version State Address */ - if (CONFIG(LOGICAL_CPUS)) - apicid_base = get_apicid_base(1); - else - apicid_base = CONFIG_MAX_PHYSICAL_CPUS; - apicid_sb800 = apicid_base + 0; -} diff --git a/src/mainboard/avalue/eax-785e/irq_tables.c b/src/mainboard/avalue/eax-785e/irq_tables.c deleted file mode 100644 index a453c766bd..0000000000 --- a/src/mainboard/avalue/eax-785e/irq_tables.c +++ /dev/null @@ -1,101 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include -#include -#include -#include - -static void write_pirq_info(struct irq_info *pirq_info, u8 bus, u8 devfn, - u8 link0, u16 bitmap0, u8 link1, u16 bitmap1, - u8 link2, u16 bitmap2, u8 link3, u16 bitmap3, - u8 slot, u8 rfu) -{ - pirq_info->bus = bus; - pirq_info->devfn = devfn; - pirq_info->irq[0].link = link0; - pirq_info->irq[0].bitmap = bitmap0; - pirq_info->irq[1].link = link1; - pirq_info->irq[1].bitmap = bitmap1; - pirq_info->irq[2].link = link2; - pirq_info->irq[2].bitmap = bitmap2; - pirq_info->irq[3].link = link3; - pirq_info->irq[3].bitmap = bitmap3; - pirq_info->slot = slot; - pirq_info->rfu = rfu; -} - - -unsigned long write_pirq_routing_table(unsigned long addr) -{ - struct irq_routing_table *pirq; - struct irq_info *pirq_info; - u32 slot_num; - u8 *v; - - u8 sum = 0; - int i; - - /* Align the table to be 16 byte aligned. */ - addr += 15; - addr &= ~15; - - /* This table must be between 0xf0000 & 0x100000 */ - printk(BIOS_INFO, "Writing IRQ routing tables to 0x%lx...", addr); - - pirq = (void *)(addr); - v = (u8 *) (addr); - - pirq->signature = PIRQ_SIGNATURE; - pirq->version = PIRQ_VERSION; - - pirq->rtr_bus = pirq_router_bus; - pirq->rtr_devfn = PCI_DEVFN(0x14, 4); - - pirq->exclusive_irqs = 0; - - pirq->rtr_vendor = 0x1002; - pirq->rtr_device = 0x4384; - - pirq->miniport_data = 0; - - memset(pirq->rfu, 0, sizeof(pirq->rfu)); - - pirq_info = (void *)(&pirq->checksum + 1); - slot_num = 0; - - /* pci bridge */ - write_pirq_info(pirq_info, pirq_router_bus, PCI_DEVFN(0x14, 4), - 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, - 0); - pirq_info++; - slot_num++; - - pirq->size = 32 + 16 * slot_num; - - for (i = 0; i < pirq->size; i++) - sum += v[i]; - - sum = pirq->checksum - sum; - if (sum != pirq->checksum) { - pirq->checksum = sum; - } - - printk(BIOS_INFO, "write_pirq_routing_table done.\n"); - - return (unsigned long)pirq_info; -} diff --git a/src/mainboard/avalue/eax-785e/mainboard.c b/src/mainboard/avalue/eax-785e/mainboard.c deleted file mode 100644 index 45779dd15b..0000000000 --- a/src/mainboard/avalue/eax-785e/mainboard.c +++ /dev/null @@ -1,62 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include -#include -#include -#include - -/* GPIO6. */ -static void enable_int_gfx(void) -{ - volatile u8 *gpio_reg; - - /* make sure the Acpi MMIO(fed80000) is accessible */ - // FIXME: RWPMIO(SB_PMIOA_REG24, AccWidthUint8, ~(BIT0), BIT0); - - gpio_reg = (volatile u8 *)AMD_SB_ACPI_MMIO_ADDR + 0xD00; /* IoMux Register */ - - *(gpio_reg + 0x6) = 0x1; /* Int_vga_en */ - *(gpio_reg + 170) = 0x1; /* gpio_gate */ - - gpio_reg = (volatile u8 *)AMD_SB_ACPI_MMIO_ADDR + 0x100; /* GPIO Registers */ - - *(gpio_reg + 0x6) = 0x8; - *(gpio_reg + 170) = 0x0; -} - -int is_dev3_present(void) -{ - return 1; -} - - -/************************************************* -* enable the dedicated function in EAX-785E board. -* This function called early than rs780_enable. -*************************************************/ -static void mainboard_enable(struct device *dev) -{ - printk(BIOS_INFO, "Mainboard " CONFIG_MAINBOARD_PART_NUMBER " Enable.\n"); - - set_pcie_dereset(); - enable_int_gfx(); -} - -struct chip_operations mainboard_ops = { - .enable_dev = mainboard_enable, -}; diff --git a/src/mainboard/avalue/eax-785e/mptable.c b/src/mainboard/avalue/eax-785e/mptable.c deleted file mode 100644 index 81763f99c7..0000000000 --- a/src/mainboard/avalue/eax-785e/mptable.c +++ /dev/null @@ -1,81 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include -#include -#include - -extern u32 apicid_sb800; - -u8 intr_data[] = { - [0x00] = 0x10,0x11,0x12,0x13,0x14,0x15,0x16,0x17, /* INTA# - INTH# */ - [0x08] = 0x00,0x00,0x00,0x00,0x1F,0x1F,0x1F,0x1F, /* Misc-nil,0,1,2, INT from Serial irq */ - [0x10] = 0x1F,0x1F,0x1F,0x10,0x1F,0x12,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, - 0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, - 0x12,0x11,0x12,0x11,0x12,0x11,0x12,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, - 0x11,0x13,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, - 0x10,0x11,0x12,0x13 -}; - -static void *smp_write_config_table(void *v) -{ - struct mp_config_table *mc; - int bus_isa; - u32 dword = 0; - u8 byte; - - mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); - - mptable_init(mc, LOCAL_APIC_ADDR); - - smp_write_processors(mc); - - mptable_write_buses(mc, NULL, &bus_isa); - - /* I/O APICs: APIC ID Version State Address */ - // FIXME: ReadPMIO(SB_PMIOA_REG34, AccWidthUint32, &dword); - dword &= 0xFFFFFFF0; - - smp_write_ioapic(mc, apicid_sb800, 0x11,(void *) dword); - - for (byte = 0x0; byte < sizeof(intr_data); byte ++) { - outb(byte | 0x80, 0xC00); - outb(intr_data[byte], 0xC01); - } - - /* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ -#define IO_LOCAL_INT(type, intr, apicid, pin) \ - smp_write_intsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin)); - - mptable_add_isa_interrupts(mc, bus_isa, apicid_sb800, 0); - - - /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ - IO_LOCAL_INT(mp_ExtINT, 0x0, MP_APIC_ALL, 0x0); - IO_LOCAL_INT(mp_NMI, 0x0, MP_APIC_ALL, 0x1); - /* There is no extension information... */ - - /* Compute the checksums */ - return mptable_finalize(mc); -} - -unsigned long write_smp_table(unsigned long addr) -{ - void *v; - v = smp_write_floating_table(addr, 0); - return (unsigned long)smp_write_config_table(v); -} diff --git a/src/mainboard/avalue/eax-785e/platform_cfg.h b/src/mainboard/avalue/eax-785e/platform_cfg.h deleted file mode 100644 index 2516e7a5ef..0000000000 --- a/src/mainboard/avalue/eax-785e/platform_cfg.h +++ /dev/null @@ -1,215 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef _PLATFORM_CFG_H_ -#define _PLATFORM_CFG_H_ - -/** - * @def BIOS_SIZE - * BIOS_SIZE_{1,2,4,8,16}M - * - * In SB800, default ROM size is 1M Bytes, if your platform ROM - * bigger than 1M you have to set the ROM size outside CIMx module and - * before AGESA module get call. - */ -#ifndef BIOS_SIZE -#define BIOS_SIZE ((CONFIG_COREBOOT_ROMSIZE_KB >> 10) - 1) -#endif /* BIOS_SIZE */ - -/** - * @def SPREAD_SPECTRUM - * @brief - * 0 - Disable Spread Spectrum function - * 1 - Enable Spread Spectrum function - */ -#define SPREAD_SPECTRUM 0 - -/** - * @def SB_HPET_TIMER - * @brief - * 0 - Disable hpet - * 1 - Enable hpet - */ -#define HPET_TIMER 1 - -/** - * @def USB_CONFIG - * @brief bit[0-6] used to control USB - * 0 - Disable - * 1 - Enable - * Usb Ohci1 Controller (Bus 0 Dev 18 Func0) is define at BIT0 - * Usb Ehci1 Controller (Bus 0 Dev 18 Func2) is define at BIT1 - * Usb Ohci2 Controller (Bus 0 Dev 19 Func0) is define at BIT2 - * Usb Ehci2 Controller (Bus 0 Dev 19 Func2) is define at BIT3 - * Usb Ohci3 Controller (Bus 0 Dev 22 Func0) is define at BIT4 - * Usb Ehci3 Controller (Bus 0 Dev 22 Func2) is define at BIT5 - * Usb Ohci4 Controller (Bus 0 Dev 20 Func5) is define at BIT6 - */ -#define USB_CONFIG 0x7F - -/** - * @def PCI_CLOCK_CTRL - * @brief bit[0-4] used for PCI Slots Clock Control, - * 0 - disable - * 1 - enable - * PCI SLOT 0 define at BIT0 - * PCI SLOT 1 define at BIT1 - * PCI SLOT 2 define at BIT2 - * PCI SLOT 3 define at BIT3 - * PCI SLOT 4 define at BIT4 - */ -#define PCI_CLOCK_CTRL 0x1F - -/** - * @def SATA_CONTROLLER - * @brief INCHIP Sata Controller - */ -#define SATA_CONTROLLER CIMX_OPTION_ENABLED - -/** - * @def SATA_MODE - * @brief INCHIP Sata Controller Mode - * NOTE: DO NOT ALLOW SATA & IDE use same mode - */ -#define SATA_MODE CONFIG_SB800_SATA_MODE - -/** - * @brief INCHIP Sata IDE Controller Mode - */ -#define IDE_LEGACY_MODE 0 -#define IDE_NATIVE_MODE 1 - -/** - * @def SATA_IDE_MODE - * @brief INCHIP Sata IDE Controller Mode - * NOTE: DO NOT ALLOW SATA & IDE use same mode - */ -#define SATA_IDE_MODE IDE_LEGACY_MODE - -/** - * @def EXTERNAL_CLOCK - * @brief 00/10: Reference clock from crystal oscillator via - * PAD_XTALI and PAD_XTALO - * - * @def INTERNAL_CLOCK - * @brief 01/11: Reference clock from internal clock through - * CP_PLL_REFCLK_P and CP_PLL_REFCLK_N via RDL - */ -#define EXTERNAL_CLOCK 0x00 -#define INTERNAL_CLOCK 0x01 - -/* NOTE: inagua have to using internal clock, - * otherwise can not detect sata drive - */ -#define SATA_CLOCK_SOURCE INTERNAL_CLOCK - -/** - * @def SATA_PORT_MULT_CAP_RESERVED - * @brief 1 ON, 0 0FF - */ -#define SATA_PORT_MULT_CAP_RESERVED 1 - - -/** - * @def AZALIA_AUTO - * @brief Detect Azalia controller automatically. - * - * @def AZALIA_DISABLE - * @brief Disable Azalia controller. - - * @def AZALIA_ENABLE - * @brief Enable Azalia controller. - */ -#define AZALIA_AUTO 0 -#define AZALIA_DISABLE 1 -#define AZALIA_ENABLE 2 - -/** - * @brief INCHIP HDA controller - */ -#define AZALIA_CONTROLLER AZALIA_AUTO - -/** - * @def AZALIA_PIN_CONFIG - * @brief - * 0 - disable - * 1 - enable - */ -#define AZALIA_PIN_CONFIG 1 - -/** - * @def AZALIA_SDIN_PIN - * @brief - * SDIN0 is define at BIT0 & BIT1 - * 00 - GPIO PIN - * 01 - Reserved - * 10 - As a Azalia SDIN pin - * SDIN1 is define at BIT2 & BIT3 - * SDIN2 is define at BIT4 & BIT5 - * SDIN3 is define at BIT6 & BIT7 - */ -#define AZALIA_SDIN_PIN 0x2A - -/** - * @def GPP_CONTROLLER - */ -#define GPP_CONTROLLER CIMX_OPTION_ENABLED - -/** - * @def GPP_CFGMODE - * @brief GPP Link Configuration - * four possible configuration: - * GPP_CFGMODE_X4000 - * GPP_CFGMODE_X2200 - * GPP_CFGMODE_X2110 - * GPP_CFGMODE_X1111 - */ -#define GPP_CFGMODE GPP_CFGMODE_X1111 - -/** - * @def NB_SB_GEN2 - * 0 - Disable - * 1 - Enable - */ -#define NB_SB_GEN2 TRUE - -/** - * @def SB_GPP_GEN2 - * 0 - Disable - * 1 - Enable - */ -#define SB_GPP_GEN2 TRUE - -/** - * @def SB_GPP_UNHIDE_PORTS - * TRUE - ports visible always, even port empty - * FALSE - ports invisible if port empty - */ -#define SB_GPP_UNHIDE_PORTS FALSE - -/** - * @def GEC_CONFIG - * 0 - Enable - * 1 - Disable - */ -#define GEC_CONFIG 0 - -/** - * @def SIO_HWM_BASE_ADDRESS - * Super IO HWM base address - */ -#define SIO_HWM_BASE_ADDRESS 0x290 - -#endif diff --git a/src/mainboard/avalue/eax-785e/resourcemap.c b/src/mainboard/avalue/eax-785e/resourcemap.c deleted file mode 100644 index b46866add5..0000000000 --- a/src/mainboard/avalue/eax-785e/resourcemap.c +++ /dev/null @@ -1,273 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include - -void setup_mb_resource_map(void) -{ - static const unsigned int register_values[] = { - /* Careful set limit registers before base registers which contain the enables */ - /* DRAM Limit i Registers - * F1:0x44 i = 0 - * F1:0x4C i = 1 - * F1:0x54 i = 2 - * F1:0x5C i = 3 - * F1:0x64 i = 4 - * F1:0x6C i = 5 - * F1:0x74 i = 6 - * F1:0x7C i = 7 - * [ 2: 0] Destination Node ID - * 000 = Node 0 - * 001 = Node 1 - * 010 = Node 2 - * 011 = Node 3 - * 100 = Node 4 - * 101 = Node 5 - * 110 = Node 6 - * 111 = Node 7 - * [ 7: 3] Reserved - * [10: 8] Interleave select - * specifies the values of A[14:12] to use with interleave enable. - * [15:11] Reserved - * [31:16] DRAM Limit Address i Bits 39-24 - * This field defines the upper address bits of a 40 bit address - * that define the end of the DRAM region. - */ - /* Don't touch it, we need it for CONFIG_CAR_FAM10 */ - ADDRMAP_REG(0x4C), 0x0000f8f8, 0x00000001, - ADDRMAP_REG(0x54), 0x0000f8f8, 0x00000002, - ADDRMAP_REG(0x5C), 0x0000f8f8, 0x00000003, - ADDRMAP_REG(0x64), 0x0000f8f8, 0x00000004, - ADDRMAP_REG(0x6C), 0x0000f8f8, 0x00000005, - ADDRMAP_REG(0x74), 0x0000f8f8, 0x00000006, - ADDRMAP_REG(0x7C), 0x0000f8f8, 0x00000007, - /* DRAM Base i Registers - * F1:0x40 i = 0 - * F1:0x48 i = 1 - * F1:0x50 i = 2 - * F1:0x58 i = 3 - * F1:0x60 i = 4 - * F1:0x68 i = 5 - * F1:0x70 i = 6 - * F1:0x78 i = 7 - * [ 0: 0] Read Enable - * 0 = Reads Disabled - * 1 = Reads Enabled - * [ 1: 1] Write Enable - * 0 = Writes Disabled - * 1 = Writes Enabled - * [ 7: 2] Reserved - * [10: 8] Interleave Enable - * 000 = No interleave - * 001 = Interleave on A[12] (2 nodes) - * 010 = reserved - * 011 = Interleave on A[12] and A[14] (4 nodes) - * 100 = reserved - * 101 = reserved - * 110 = reserved - * 111 = Interleve on A[12] and A[13] and A[14] (8 nodes) - * [15:11] Reserved - * [13:16] DRAM Base Address i Bits 39-24 - * This field defines the upper address bits of a 40-bit address - * that define the start of the DRAM region. - */ - /* don't touch it, we need it for CONFIG_CAR_FAM10 */ - ADDRMAP_REG(0x48), 0x0000f8fc, 0x00000000, - ADDRMAP_REG(0x50), 0x0000f8fc, 0x00000000, - ADDRMAP_REG(0x58), 0x0000f8fc, 0x00000000, - ADDRMAP_REG(0x60), 0x0000f8fc, 0x00000000, - ADDRMAP_REG(0x68), 0x0000f8fc, 0x00000000, - ADDRMAP_REG(0x70), 0x0000f8fc, 0x00000000, - ADDRMAP_REG(0x78), 0x0000f8fc, 0x00000000, - - /* Memory-Mapped I/O Limit i Registers - * F1:0x84 i = 0 - * F1:0x8C i = 1 - * F1:0x94 i = 2 - * F1:0x9C i = 3 - * F1:0xA4 i = 4 - * F1:0xAC i = 5 - * F1:0xB4 i = 6 - * F1:0xBC i = 7 - * [ 2: 0] Destination Node ID - * 000 = Node 0 - * 001 = Node 1 - * 010 = Node 2 - * 011 = Node 3 - * 100 = Node 4 - * 101 = Node 5 - * 110 = Node 6 - * 111 = Node 7 - * [ 3: 3] Reserved - * [ 5: 4] Destination Link ID - * 00 = Link 0 - * 01 = Link 1 - * 10 = Link 2 - * 11 = Reserved - * [ 6: 6] Reserved - * [ 7: 7] Non-Posted - * 0 = CPU writes may be posted - * 1 = CPU writes must be non-posted - * [31: 8] Memory-Mapped I/O Limit Address i (39-16) - * This field defines the upp address bits of a 40-bit address that - * defines the end of a memory-mapped I/O region n - */ - ADDRMAP_REG(0x84), 0x00000048, 0x00000000, - ADDRMAP_REG(0x8C), 0x00000048, 0x00000000, - ADDRMAP_REG(0x94), 0x00000048, 0x00000000, - ADDRMAP_REG(0x9C), 0x00000048, 0x00000000, - ADDRMAP_REG(0xA4), 0x00000048, 0x00000000, - ADDRMAP_REG(0xAC), 0x00000048, 0x00000000, - ADDRMAP_REG(0xB4), 0x00000048, 0x00000000, - - /* Memory-Mapped I/O Base i Registers - * F1:0x80 i = 0 - * F1:0x88 i = 1 - * F1:0x90 i = 2 - * F1:0x98 i = 3 - * F1:0xA0 i = 4 - * F1:0xA8 i = 5 - * F1:0xB0 i = 6 - * F1:0xB8 i = 7 - * [ 0: 0] Read Enable - * 0 = Reads disabled - * 1 = Reads Enabled - * [ 1: 1] Write Enable - * 0 = Writes disabled - * 1 = Writes Enabled - * [ 2: 2] Cpu Disable - * 0 = Cpu can use this I/O range - * 1 = Cpu requests do not use this I/O range - * [ 3: 3] Lock - * 0 = base/limit registers i are read/write - * 1 = base/limit registers i are read-only - * [ 7: 4] Reserved - * [31: 8] Memory-Mapped I/O Base Address i (39-16) - * This field defines the upper address bits of a 40bit address - * that defines the start of memory-mapped I/O region i - */ - ADDRMAP_REG(0x80), 0x000000f0, 0x00000000, - ADDRMAP_REG(0x88), 0x000000f0, 0x00000000, - ADDRMAP_REG(0x90), 0x000000f0, 0x00000000, - ADDRMAP_REG(0x98), 0x000000f0, 0x00000000, - ADDRMAP_REG(0xA0), 0x000000f0, 0x00000000, - ADDRMAP_REG(0xA8), 0x000000f0, 0x00000000, - ADDRMAP_REG(0xB0), 0x000000f0, 0x00000000, - - /* PCI I/O Limit i Registers - * F1:0xC4 i = 0 - * F1:0xCC i = 1 - * F1:0xD4 i = 2 - * F1:0xDC i = 3 - * [ 2: 0] Destination Node ID - * 000 = Node 0 - * 001 = Node 1 - * 010 = Node 2 - * 011 = Node 3 - * 100 = Node 4 - * 101 = Node 5 - * 110 = Node 6 - * 111 = Node 7 - * [ 3: 3] Reserved - * [ 5: 4] Destination Link ID - * 00 = Link 0 - * 01 = Link 1 - * 10 = Link 2 - * 11 = reserved - * [11: 6] Reserved - * [24:12] PCI I/O Limit Address i - * This field defines the end of PCI I/O region n - * [31:25] Reserved - */ - ADDRMAP_REG(0xCC), 0xFE000FC8, 0x00000000, - ADDRMAP_REG(0xD4), 0xFE000FC8, 0x00000000, - ADDRMAP_REG(0xDC), 0xFE000FC8, 0x00000000, - - /* PCI I/O Base i Registers - * F1:0xC0 i = 0 - * F1:0xC8 i = 1 - * F1:0xD0 i = 2 - * F1:0xD8 i = 3 - * [ 0: 0] Read Enable - * 0 = Reads Disabled - * 1 = Reads Enabled - * [ 1: 1] Write Enable - * 0 = Writes Disabled - * 1 = Writes Enabled - * [ 3: 2] Reserved - * [ 4: 4] VGA Enable - * 0 = VGA matches Disabled - * 1 = matches all address < 64K and where A[9:0] is in the - * range 3B0-3BB or 3C0-3DF independen of the base & limit registers - * [ 5: 5] ISA Enable - * 0 = ISA matches Disabled - * 1 = Blocks address < 64K and in the last 768 bytes of eack 1K block - * from matching agains this base/limit pair - * [11: 6] Reserved - * [24:12] PCI I/O Base i - * This field defines the start of PCI I/O region n - * [31:25] Reserved - */ - ADDRMAP_REG(0xC8), 0xFE000FCC, 0x00000000, - ADDRMAP_REG(0xD0), 0xFE000FCC, 0x00000000, - ADDRMAP_REG(0xD8), 0xFE000FCC, 0x00000000, - - /* Config Base and Limit i Registers - * F1:0xE0 i = 0 - * F1:0xE4 i = 1 - * F1:0xE8 i = 2 - * F1:0xEC i = 3 - * [ 0: 0] Read Enable - * 0 = Reads Disabled - * 1 = Reads Enabled - * [ 1: 1] Write Enable - * 0 = Writes Disabled - * 1 = Writes Enabled - * [ 2: 2] Device Number Compare Enable - * 0 = The ranges are based on bus number - * 1 = The ranges are ranges of devices on bus 0 - * [ 3: 3] Reserved - * [ 6: 4] Destination Node - * 000 = Node 0 - * 001 = Node 1 - * 010 = Node 2 - * 011 = Node 3 - * 100 = Node 4 - * 101 = Node 5 - * 110 = Node 6 - * 111 = Node 7 - * [ 7: 7] Reserved - * [ 9: 8] Destination Link - * 00 = Link 0 - * 01 = Link 1 - * 10 = Link 2 - * 11 - Reserved - * [15:10] Reserved - * [23:16] Bus Number Base i - * This field defines the lowest bus number in configuration region i - * [31:24] Bus Number Limit i - * This field defines the highest bus number in configuration regin i - */ - /* AMD 8111 on link0 of CPU 0 */ - ADDRMAP_REG(0xE4), 0x0000FC88, 0x00000000, - ADDRMAP_REG(0xE8), 0x0000FC88, 0x00000000, - ADDRMAP_REG(0xEC), 0x0000FC88, 0x00000000, - }; - - int max; - max = ARRAY_SIZE(register_values); - setup_resource_map(register_values, max); -} diff --git a/src/mainboard/avalue/eax-785e/romstage.c b/src/mainboard/avalue/eax-785e/romstage.c deleted file mode 100644 index 8d7366e534..0000000000 --- a/src/mainboard/avalue/eax-785e/romstage.c +++ /dev/null @@ -1,223 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#define SYSTEM_TYPE 1 /* SERVER=0, DESKTOP=1, MOBILE=2 */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include "spd.h" -#include -#include - -#include "cpu/amd/quadcore/quadcore.c" - -#define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1) -#define CLK_DEV PNP_DEV(0x2e, W83627HF_SP1) - -int spd_read_byte(unsigned int device, unsigned int address); - - -int spd_read_byte(u32 device, u32 address) -{ - return do_smbus_read_byte(SMBUS_IO_BASE, device, address); -} - -void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) -{ - struct sys_info *sysinfo = get_sysinfo(); - static const u8 spd_addr[] = {RC00, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, }; - u32 bsp_apicid = 0, val; - msr_t msr; - - timestamp_init(timestamp_get()); - timestamp_add_now(TS_START_ROMSTAGE); - - if (!cpu_init_detectedx && boot_cpu()) { - /* Nothing special needs to be done to find bus 0 */ - /* Allow the HT devices to be found */ - /* mov bsp to bus 0xff when > 8 nodes */ - set_bsp_node_CHtExtNodeCfgEn(); - enumerate_ht_chain(); - - /*enable port80 decoding and southbridge poweron init */ - sb800_lpc_init(); - sb800_pci_port80(); - } - - post_code(0x30); - - if (bist == 0) { - bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo); /* mmconf is inited in init_cpus */ - /* All cores run this but the BSP(node0,core0) is the only core that returns. */ - } - - post_code(0x32); - - enable_rs780_dev8(); - sb800_clk_output_48Mhz(); - - winbond_set_clksel_48(CLK_DEV); - winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); - - console_init(); - printk(BIOS_DEBUG, "\n"); - - /* Halt if there was a built in self test failure */ - report_bist_failure(bist); - - /* Load MPB */ - val = cpuid_eax(1); - printk(BIOS_DEBUG, "BSP Family_Model: %08x\n", val); - printk(BIOS_DEBUG, "*sysinfo range: [%p,%p]\n",sysinfo,sysinfo+1); - printk(BIOS_DEBUG, "bsp_apicid = %02x\n", bsp_apicid); - printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx); - - /* Setup sysinfo defaults */ - set_sysinfo_in_ram(0); - - update_microcode(val); - - post_code(0x33); - - cpuSetAMDMSR(0); - post_code(0x34); - - amd_ht_init(sysinfo); - post_code(0x35); - - /* Setup nodes PCI space and start core 0 AP init. */ - finalize_node_setup(sysinfo); - - /* Setup any mainboard PCI settings etc. */ - setup_mb_resource_map(); - post_code(0x36); - - /* wait for all the APs core0 started by finalize_node_setup. */ - /* FIXME: A bunch of cores are going to start output to serial at once. - It would be nice to fixup prink spinlocks for ROM XIP mode. - I think it could be done by putting the spinlock flag in the cache - of the BSP located right after sysinfo. - */ - wait_all_core0_started(); - -#if CONFIG(LOGICAL_CPUS) - /* Core0 on each node is configured. Now setup any additional cores. */ - printk(BIOS_DEBUG, "start_other_cores()\n"); - start_other_cores(bsp_apicid); - post_code(0x37); - wait_all_other_cores_started(bsp_apicid); -#endif - - post_code(0x38); - - /* run _early_setup before soft-reset. */ - rs780_early_setup(); - sb800_early_setup(); - -#if CONFIG(SET_FIDVID) - msr = rdmsr(MSR_COFVID_STS); - printk(BIOS_DEBUG, "\nBegin FIDVID MSR 0xc0010071 0x%08x 0x%08x\n", msr.hi, msr.lo); - post_code(0x39); - - enable_fid_change_on_sb(sysinfo->sbbusn, sysinfo->sbdn); - - if (!warm_reset_detect(0)) { /* BSP is node 0 */ - init_fidvid_bsp(bsp_apicid, sysinfo->nodes); - } else { - init_fidvid_stage2(bsp_apicid, 0); /* BSP is node 0 */ - } - - post_code(0x3A); - - /* show final fid and vid */ - msr = rdmsr(MSR_COFVID_STS); - printk(BIOS_DEBUG, "End FIDVIDMSR 0xc0010071 0x%08x 0x%08x\n", msr.hi, msr.lo); -#endif - - rs780_htinit(); - - /* Reset for HT, FIDVID, PLL and errata changes to take affect. */ - if (!warm_reset_detect(0)) { - printk(BIOS_INFO, "...WARM RESET...\n\n\n"); - soft_reset(); - die("After soft_reset - shouldn't see this message!!!\n"); - } - - post_code(0x3B); - - /* It's the time to set ctrl in sysinfo now; */ - printk(BIOS_DEBUG, "fill_mem_ctrl()\n"); - fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr); - - post_code(0x40); - - raminit_amdmct(sysinfo); - - cbmem_initialize_empty(); - post_code(0x41); - - amdmct_cbmem_store_info(sysinfo); - - sb800_before_pci_init(); - - post_code(0x42); -} - -/** - * BOOL AMD_CB_ManualBUIDSwapList(u8 Node, u8 Link, u8 **List) - * Description: - * This routine is called every time a non-coherent chain is processed. - * BUID assignment may be controlled explicitly on a non-coherent chain. Provide a - * swap list. The first part of the list controls the BUID assignment and the - * second part of the list provides the device to device linking. Device orientation - * can be detected automatically, or explicitly. See documentation for more details. - * - * Automatic non-coherent init assigns BUIDs starting at 1 and incrementing sequentially - * based on each device's unit count. - * - * Parameters: - * @param[in] node = The node on which this chain is located - * @param[in] link = The link on the host for this chain - * @param[out] List = supply a pointer to a list - */ -BOOL AMD_CB_ManualBUIDSwapList (u8 node, u8 link, const u8 **List) -{ - static const u8 swaplist[] = {0, 1, 0xFF, 0, 0xFF}; - /* If the BUID was adjusted in early_ht we need to do the manual override */ - if ((node == 0) && (link == 0)) { /* BSP SB link */ - *List = swaplist; - return 1; - } - - return 0; -} diff --git a/src/mainboard/gigabyte/ma785gm/Kconfig b/src/mainboard/gigabyte/ma785gm/Kconfig deleted file mode 100644 index bdd6cb9361..0000000000 --- a/src/mainboard/gigabyte/ma785gm/Kconfig +++ /dev/null @@ -1,54 +0,0 @@ -if BOARD_GIGABYTE_MA785GM - -config BOARD_SPECIFIC_OPTIONS - def_bool y - select CPU_AMD_SOCKET_AM3 - select DIMM_DDR2 - select DIMM_REGISTERED - select NORTHBRIDGE_AMD_AMDFAM10 - select SOUTHBRIDGE_AMD_RS780 - select SOUTHBRIDGE_AMD_SB700 - select SUPERIO_ITE_IT8718F - select HAVE_OPTION_TABLE - select HAVE_PIRQ_TABLE - select HAVE_MP_TABLE - select SB_HT_CHAIN_UNITID_OFFSET_ONLY - select LIFT_BSP_APIC_ID - select HAVE_ACPI_TABLES - select BOARD_ROMSIZE_KB_1024 - select ENABLE_APIC_EXT_ID - select GFXUMA - -config MAINBOARD_DIR - string - default gigabyte/ma785gm - -config APIC_ID_OFFSET - hex - default 0x0 - -config MAINBOARD_PART_NUMBER - string - default "GA-MA785GM-US2H" - -config MAX_CPUS - int - default 8 - -config MAX_PHYSICAL_CPUS - int - default 2 - -config HT_CHAIN_END_UNITID_BASE - hex - default 0x1 - -config HT_CHAIN_UNITID_BASE - hex - default 0x0 - -config IRQ_SLOT_COUNT - int - default 11 - -endif # BOARD_GIGABYTE_MA785GM diff --git a/src/mainboard/gigabyte/ma785gm/Kconfig.name b/src/mainboard/gigabyte/ma785gm/Kconfig.name deleted file mode 100644 index 79555faad5..0000000000 --- a/src/mainboard/gigabyte/ma785gm/Kconfig.name +++ /dev/null @@ -1,2 +0,0 @@ -config BOARD_GIGABYTE_MA785GM - bool "GA-MA785GM-US2H" diff --git a/src/mainboard/gigabyte/ma785gm/Makefile.inc b/src/mainboard/gigabyte/ma785gm/Makefile.inc deleted file mode 100644 index 91d4b39c32..0000000000 --- a/src/mainboard/gigabyte/ma785gm/Makefile.inc +++ /dev/null @@ -1,16 +0,0 @@ -# -# This file is part of the coreboot project. -# -# This program is free software; you can redistribute it and/or modify -# it under the terms of the GNU General Public License as published by -# the Free Software Foundation; version 2 of the License. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# - -romstage-y += resourcemap.c - -ramstage-y += get_bus_conf.c diff --git a/src/mainboard/gigabyte/ma785gm/acpi/cpstate.asl b/src/mainboard/gigabyte/ma785gm/acpi/cpstate.asl deleted file mode 100644 index acaa5bae32..0000000000 --- a/src/mainboard/gigabyte/ma785gm/acpi/cpstate.asl +++ /dev/null @@ -1,80 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2010 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -/* This file defines the processor and performance state capability - * for each core in the system. It is included into the DSDT for each - * core. It assumes that each core of the system has the same performance - * characteristics. -*/ -/* -#include -DefinitionBlock ("DSDT.AML", "DSDT", 0x01, OEM_ID, ACPI_TABLE_CREATOR, 0x00010001) - { - Scope (\_PR) { - Device (CPU0) { - Name (_HID, "ACPI0007") - Name (_UID, 0) - #include "cpstate.asl" - } - Device (CPU1) { - Name (_HID, "ACPI0007") - Name (_UID, 1) - #include "cpstate.asl" - } - Device (CPU2) { - Name (_HID, "ACPI0007") - Name (_UID, 2) - #include "cpstate.asl" - } - Device (CPU3) { - Name (_HID, "ACPI0007") - Name (_UID, 3) - #include "cpstate.asl" - } - } -*/ - /* P-state support: The maximum number of P-states supported by the */ - /* CPUs we'll use is 6. */ - /* Get from AMI BIOS. */ - Name(_PSS, Package(){ - Package () - { - 0x00000AF0, - 0x0000BF81, - 0x00000002, - 0x00000002, - 0x00000000, - 0x00000000 - }, - - Package () - { - 0x00000578, - 0x000076F2, - 0x00000002, - 0x00000002, - 0x00000001, - 0x00000001 - } - }) - - Name(_PCT, Package(){ - ResourceTemplate(){Register(FFixedHW, 0, 0, 0)}, - ResourceTemplate(){Register(FFixedHW, 0, 0, 0)} - }) - - Method(_PPC, 0){ - Return(0) - } diff --git a/src/mainboard/gigabyte/ma785gm/acpi/ide.asl b/src/mainboard/gigabyte/ma785gm/acpi/ide.asl deleted file mode 100644 index 5c155cf301..0000000000 --- a/src/mainboard/gigabyte/ma785gm/acpi/ide.asl +++ /dev/null @@ -1,240 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2010 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -/* -Scope (_SB) { - Device(PCI0) { - Device(IDEC) { - Name(_ADR, 0x00140001) - #include "ide.asl" - } - } -} -*/ - -/* Some timing tables */ -Name(UDTT, Package(){ /* Udma timing table */ - 120, 90, 60, 45, 30, 20, 15, 0 /* UDMA modes 0 -> 6 */ -}) - -Name(MDTT, Package(){ /* MWDma timing table */ - 480, 150, 120, 0 /* Legacy DMA modes 0 -> 2 */ -}) - -Name(POTT, Package(){ /* Pio timing table */ - 600, 390, 270, 180, 120, 0 /* PIO modes 0 -> 4 */ -}) - -/* Some timing register value tables */ -Name(MDRT, Package(){ /* MWDma timing register table */ - 0x77, 0x21, 0x20, 0xFF /* Legacy DMA modes 0 -> 2 */ -}) - -Name(PORT, Package(){ - 0x99, 0x47, 0x34, 0x22, 0x20, 0x99 /* PIO modes 0 -> 4 */ -}) - -OperationRegion(ICRG, PCI_Config, 0x40, 0x20) /* ide control registers */ - Field(ICRG, AnyAcc, NoLock, Preserve) -{ - PPTS, 8, /* Primary PIO Slave Timing */ - PPTM, 8, /* Primary PIO Master Timing */ - OFFSET(0x04), PMTS, 8, /* Primary MWDMA Slave Timing */ - PMTM, 8, /* Primary MWDMA Master Timing */ - OFFSET(0x08), PPCR, 8, /* Primary PIO Control */ - OFFSET(0x0A), PPMM, 4, /* Primary PIO master Mode */ - PPSM, 4, /* Primary PIO slave Mode */ - OFFSET(0x14), PDCR, 2, /* Primary UDMA Control */ - OFFSET(0x16), PDMM, 4, /* Primary UltraDMA Mode */ - PDSM, 4, /* Primary UltraDMA Mode */ -} - -Method(GTTM, 1) /* get total time*/ -{ - Store(And(Arg0, 0x0F), Local0) /* Recovery Width */ - Increment(Local0) - Store(ShiftRight(Arg0, 4), Local1) /* Command Width */ - Increment(Local1) - Return(Multiply(30, Add(Local0, Local1))) -} - -Device(PRID) -{ - Name (_ADR, Zero) - Method(_GTM, 0) - { - NAME(OTBF, Buffer(20) { /* out buffer */ - 0xFF, 0xFF, 0xFF, 0xFF, - 0xFF, 0xFF, 0xFF, 0xFF, - 0xFF, 0xFF, 0xFF, 0xFF, - 0xFF, 0xFF, 0xFF, 0xFF, 0x00, 0x00, 0x00, 0x00 - }) - - CreateDwordField(OTBF, 0, PSD0) /* PIO spd0 */ - CreateDwordField(OTBF, 4, DSD0) /* DMA spd0 */ - CreateDwordField(OTBF, 8, PSD1) /* PIO spd1 */ - CreateDwordField(OTBF, 12, DSD1) /* DMA spd1 */ - CreateDwordField(OTBF, 16, BFFG) /* buffer flags */ - - /* Just return if the channel is disabled */ - If(And(PPCR, 0x01)) { /* primary PIO control */ - Return(OTBF) - } - - /* Always tell them independent timing available and IOChannelReady used on both drives */ - Or(BFFG, 0x1A, BFFG) - - Store(GTTM(PPTM), PSD0) /* save total time of primary PIO master timming to PIO spd0 */ - Store(GTTM(PPTS), PSD1) /* save total time of primary PIO slave Timing to PIO spd1 */ - - If(And(PDCR, 0x01)) { /* It's under UDMA mode */ - Or(BFFG, 0x01, BFFG) - Store(DerefOf(Index(UDTT, PDMM)), DSD0) - } - Else { - Store(GTTM(PMTM), DSD0) /* Primary MWDMA Master Timing, DmaSpd0 */ - } - - If(And(PDCR, 0x02)) { /* It's under UDMA mode */ - Or(BFFG, 0x04, BFFG) - Store(DerefOf(Index(UDTT, PDSM)), DSD1) - } - Else { - Store(GTTM(PMTS), DSD1) /* Primary MWDMA Slave Timing, DmaSpd0 */ - } - - Return(OTBF) /* out buffer */ - } /* End Method(_GTM) */ - - Method(_STM, 3, NotSerialized) - { - NAME(INBF, Buffer(20) { /* in buffer */ - 0xFF, 0xFF, 0xFF, 0xFF, - 0xFF, 0xFF, 0xFF, 0xFF, - 0xFF, 0xFF, 0xFF, 0xFF, - 0xFF, 0xFF, 0xFF, 0xFF, 0x00, 0x00, 0x00, 0x00 - }) - - CreateDwordField(INBF, 0, PSD0) /* PIO spd0 */ - CreateDwordField(INBF, 4, DSD0) /* PIO spd0 */ - CreateDwordField(INBF, 8, PSD1) /* PIO spd1 */ - CreateDwordField(INBF, 12, DSD1) /* DMA spd1 */ - CreateDwordField(INBF, 16, BFFG) /*buffer flag */ - - Store(Match(POTT, MLE, PSD0, MTR, 0, 0), Local0) - Divide(Local0, 5, PPMM,) /* Primary PIO master Mode */ - Store(Match(POTT, MLE, PSD1, MTR, 0, 0), Local1) - Divide(Local1, 5, PPSM,) /* Primary PIO slave Mode */ - - Store(DerefOf(Index(PORT, Local0)), PPTM) /* Primary PIO Master Timing */ - Store(DerefOf(Index(PORT, Local1)), PPTS) /* Primary PIO Slave Timing */ - - If(And(BFFG, 0x01)) { /* Drive 0 is under UDMA mode */ - Store(Match(UDTT, MLE, DSD0, MTR, 0, 0), Local0) - Divide(Local0, 7, PDMM,) - Or(PDCR, 0x01, PDCR) - } - Else { - If(LNotEqual(DSD0, 0xFFFFFFFF)) { - Store(Match(MDTT, MLE, DSD0, MTR, 0, 0), Local0) - Store(DerefOf(Index(MDRT, Local0)), PMTM) - } - } - - If(And(BFFG, 0x04)) { /* Drive 1 is under UDMA mode */ - Store(Match(UDTT, MLE, DSD1, MTR, 0, 0), Local0) - Divide(Local0, 7, PDSM,) - Or(PDCR, 0x02, PDCR) - } - Else { - If(LNotEqual(DSD1, 0xFFFFFFFF)) { - Store(Match(MDTT, MLE, DSD1, MTR, 0, 0), Local0) - Store(DerefOf(Index(MDRT, Local0)), PMTS) - } - } - /* Return(INBF) */ - } /*End Method(_STM) */ - Device(MST) - { - Name(_ADR, 0) - Method(_GTF) { - Name(CMBF, Buffer(21) { - 0x03, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xEF, - 0x03, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xEF, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xF5 - }) - CreateByteField(CMBF, 1, POMD) - CreateByteField(CMBF, 8, DMMD) - CreateByteField(CMBF, 5, CMDA) - CreateByteField(CMBF, 12, CMDB) - CreateByteField(CMBF, 19, CMDC) - - Store(0xA0, CMDA) - Store(0xA0, CMDB) - Store(0xA0, CMDC) - - Or(PPMM, 0x08, POMD) - - If(And(PDCR, 0x01)) { - Or(PDMM, 0x40, DMMD) - } - Else { - Store(Match - (MDTT, MLE, GTTM(PMTM), - MTR, 0, 0), Local0) - If(LLess(Local0, 3)) { - Or(0x20, Local0, DMMD) - } - } - Return(CMBF) - } - } /* End Device(MST) */ - - Device(SLAV) - { - Name(_ADR, 1) - Method(_GTF) { - Name(CMBF, Buffer(21) { - 0x03, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xEF, - 0x03, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xEF, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xF5 - }) - CreateByteField(CMBF, 1, POMD) - CreateByteField(CMBF, 8, DMMD) - CreateByteField(CMBF, 5, CMDA) - CreateByteField(CMBF, 12, CMDB) - CreateByteField(CMBF, 19, CMDC) - - Store(0xB0, CMDA) - Store(0xB0, CMDB) - Store(0xB0, CMDC) - - Or(PPSM, 0x08, POMD) - - If(And(PDCR, 0x02)) { - Or(PDSM, 0x40, DMMD) - } - Else { - Store(Match - (MDTT, MLE, GTTM(PMTS), - MTR, 0, 0), Local0) - If(LLess(Local0, 3)) { - Or(0x20, Local0, DMMD) - } - } - Return(CMBF) - } - } /* End Device(SLAV) */ -} diff --git a/src/mainboard/gigabyte/ma785gm/acpi/routing.asl b/src/mainboard/gigabyte/ma785gm/acpi/routing.asl deleted file mode 100644 index 072aa2117f..0000000000 --- a/src/mainboard/gigabyte/ma785gm/acpi/routing.asl +++ /dev/null @@ -1,297 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2010 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -/* -#include -DefinitionBlock ("DSDT.AML", "DSDT", 0x01, OEM_ID, ACPI_TABLE_CREATOR, 0x00010001 - ) - { - #include "routing.asl" - } -*/ - -/* Routing is in System Bus scope */ -Scope(\_SB) { - Name(PR0, Package(){ - /* NB devices */ - /* Bus 0, Dev 0 - RS780 Host Controller */ - /* Bus 0, Dev 1 - PCI Bridge for Internal Graphics */ - /* Bus 0, Dev 2 - PCIe Bridge for x8 PCIe Slot (GFX0) */ - Package(){0x0002FFFF, 0, INTC, 0 }, - Package(){0x0002FFFF, 1, INTD, 0 }, - Package(){0x0002FFFF, 2, INTA, 0 }, - Package(){0x0002FFFF, 3, INTB, 0 }, - /* Bus 0, Dev 3 - PCIe graphics port 1 bridge */ - /* Bus 0, Dev 4 - PCIe Bridge for Express Card Slot */ - Package(){0x0004FFFF, 0, INTA, 0 }, - Package(){0x0004FFFF, 1, INTB, 0 }, - Package(){0x0004FFFF, 2, INTC, 0 }, - Package(){0x0004FFFF, 3, INTD, 0 }, - /* Bus 0, Dev 5 - General purpose PCIe bridge 5 */ - /* Package(){0x0005FFFF, 0, INTB, 0 }, */ - /* Package(){0x0005FFFF, 1, INTC, 0 }, */ - /* Package(){0x0005FFFF, 2, INTD, 0 }, */ - /* Package(){0x0005FFFF, 3, INTA, 0 }, */ - /* Bus 0, Dev 6 - PCIe Bridge for Ethernet Chip */ - Package(){0x0006FFFF, 0, INTC, 0 }, - Package(){0x0006FFFF, 1, INTD, 0 }, - Package(){0x0006FFFF, 2, INTA, 0 }, - Package(){0x0006FFFF, 3, INTB, 0 }, - /* Bus 0, Dev 7 - PCIe Bridge for x1 PCIe Slot */ - Package(){0x0007FFFF, 0, INTD, 0 }, - Package(){0x0007FFFF, 1, INTA, 0 }, - Package(){0x0007FFFF, 2, INTB, 0 }, - Package(){0x0007FFFF, 3, INTC, 0 }, - /* Bus 0, Funct 8 - Southbridge port (normally hidden) */ - - /* SB devices */ - /* Bus 0, Dev 17 - SATA controller #2 */ - /* Bus 0, Dev 18 - SATA controller #1 */ - Package(){0x0011FFFF, 1, INTA, 0 }, - - /* Bus 0, Dev 19 - USB: OHCI, funct 0-4; EHCI, funct 5 */ - Package(){0x0012FFFF, 0, INTA, 0 }, - Package(){0x0012FFFF, 1, INTB, 0 }, - Package(){0x0013FFFF, 0, INTA, 0 }, - Package(){0x0013FFFF, 1, INTB, 0 }, - Package(){0x0014FFFF, 2, INTA, 0 }, - - /* Bus 0, Dev 20 - F0:SMBus/ACPI,F1:IDE;F2:HDAudio;F3:LPC;F4:PCIBridge;F5:AC97 Audio;F6:AC97 Modem */ - Package(){0x0014FFFF, 0, INTA, 0 }, - Package(){0x0014FFFF, 1, INTB, 0 }, - Package(){0x0014FFFF, 2, INTC, 0 }, - Package(){0x0014FFFF, 3, INTD, 0 }, - }) - - Name(APR0, Package(){ - /* NB devices in APIC mode */ - /* Bus 0, Dev 0 - RS780 Host Controller */ - - /* Bus 0, Dev 1 - PCI Bridge for Internal Graphics */ - /* Package(){0x0001FFFF, 0, 0, 18 }, */ - /* Package(){0x0001FFFF, 1, 0, 19 }, */ - - /* Bus 0, Dev 2 - PCIe Bridge for x8 PCIe Slot (GFX0) */ - Package(){0x0002FFFF, 0, 0, 18 }, - /* Package(){0x0002FFFF, 1, 0, 19 }, */ - /* Package(){0x0002FFFF, 2, 0, 16 }, */ - /* Package(){0x0002FFFF, 3, 0, 17 }, */ - - /* Bus 0, Dev 3 - PCIe graphics port 1 bridge */ - Package(){0x0003FFFF, 0, 0, 19 }, - - /* Bus 0, Dev 4 - PCIe Bridge for Express Card Slot */ - Package(){0x0004FFFF, 0, 0, 16 }, - /* Package(){0x0004FFFF, 1, 0, 17 }, */ - /* Package(){0x0004FFFF, 2, 0, 18 }, */ - /* Package(){0x0004FFFF, 3, 0, 19 }, */ - - /* Bus 0, Dev 5 - General purpose PCIe bridge 5 */ - /* Package(){0x0005FFFF, 0, 0, 17 }, */ - /* Package(){0x0005FFFF, 1, 0, 18 }, */ - /* Package(){0x0005FFFF, 2, 0, 19 }, */ - /* Package(){0x0005FFFF, 3, 0, 16 }, */ - - /* Bus 0, Dev 6 - General purpose PCIe bridge 6 */ - /* Package(){0x0006FFFF, 0, 0, 18 }, */ - /* Package(){0x0006FFFF, 1, 0, 19 }, */ - /* Package(){0x0006FFFF, 2, 0, 16 }, */ - /* Package(){0x0006FFFF, 3, 0, 17 }, */ - - /* Bus 0, Dev 7 - PCIe Bridge for network card */ - /* Package(){0x0007FFFF, 0, 0, 19 }, */ - /* Package(){0x0007FFFF, 1, 0, 16 }, */ - /* Package(){0x0007FFFF, 2, 0, 17 }, */ - /* Package(){0x0007FFFF, 3, 0, 18 }, */ - - /* Bus 0, Dev 9 - PCIe Bridge for network card */ - Package(){0x0009FFFF, 0, 0, 17 }, - /* Package(){0x0009FFFF, 1, 0, 16 }, */ - /* Package(){0x0009FFFF, 2, 0, 17 }, */ - /* Package(){0x0009FFFF, 3, 0, 18 }, */ - /* Bus 0, Dev A - PCIe Bridge for network card */ - Package(){0x000AFFFF, 0, 0, 18 }, - /* Package(){0x000AFFFF, 1, 0, 16 }, */ - /* Package(){0x000AFFFF, 2, 0, 17 }, */ - /* Package(){0x000AFFFF, 3, 0, 18 }, */ - /* Bus 0, Funct 8 - Southbridge port (normally hidden) */ - - /* SB devices in APIC mode */ - /* Bus 0, Dev 17 - SATA controller #2 */ - /* Bus 0, Dev 18 - SATA controller #1 */ - Package(){0x0011FFFF, 0, 0, 22 }, - - /* Bus 0, Dev 19 - USB: OHCI, funct 0-4; EHCI, funct 5 */ - Package(){0x0012FFFF, 0, 0, 16 }, - Package(){0x0012FFFF, 1, 0, 17 }, - Package(){0x0013FFFF, 0, 0, 18 }, - Package(){0x0013FFFF, 1, 0, 19 }, - Package(){0x0014FFFF, 0, 0, 16 }, - /* Package(){0x00130004, 2, 0, 18 }, */ - /* Package(){0x00130005, 3, 0, 19 }, */ - - /* Bus 0, Dev 20 - F0:SMBus/ACPI, F1:IDE; F2:HDAudio; F3:LPC; F4:PCIBridge; F5:AC97 Audio; F6:AC97 Modem */ - Package(){0x0014FFFF, 0, 0, 16 }, - Package(){0x0014FFFF, 1, 0, 17 }, - Package(){0x0014FFFF, 2, 0, 18 }, - Package(){0x0014FFFF, 3, 0, 19 }, - /* Package(){0x00140004, 2, 0, 18 }, */ - /* Package(){0x00140004, 3, 0, 19 }, */ - /* Package(){0x00140005, 1, 0, 17 }, */ - /* Package(){0x00140006, 1, 0, 17 }, */ - }) - - Name(PR1, Package(){ - /* Internal graphics - RS780 VGA, Bus1, Dev5 */ - Package(){0x0005FFFF, 0, INTA, 0 }, - Package(){0x0005FFFF, 1, INTB, 0 }, - Package(){0x0005FFFF, 2, INTC, 0 }, - Package(){0x0005FFFF, 3, INTD, 0 }, - }) - - Name(APR1, Package(){ - /* Internal graphics - RS780 VGA, Bus1, Dev5 */ - Package(){0x0005FFFF, 0, 0, 18 }, - Package(){0x0005FFFF, 1, 0, 19 }, - /* Package(){0x0005FFFF, 2, 0, 20 }, */ - /* Package(){0x0005FFFF, 3, 0, 17 }, */ - }) - - Name(PS2, Package(){ - /* The external GFX - Hooked to PCIe slot 2 */ - Package(){0x0000FFFF, 0, INTC, 0 }, - Package(){0x0000FFFF, 1, INTD, 0 }, - Package(){0x0000FFFF, 2, INTA, 0 }, - Package(){0x0000FFFF, 3, INTB, 0 }, - }) - - Name(APS2, Package(){ - /* The external GFX - Hooked to PCIe slot 2 */ - Package(){0x0000FFFF, 0, 0, 18 }, - Package(){0x0000FFFF, 1, 0, 19 }, - Package(){0x0000FFFF, 2, 0, 16 }, - Package(){0x0000FFFF, 3, 0, 17 }, - }) - - Name(PS4, Package(){ - /* PCIe slot - Hooked to PCIe slot 4 */ - Package(){0x0000FFFF, 0, INTA, 0 }, - Package(){0x0000FFFF, 1, INTB, 0 }, - Package(){0x0000FFFF, 2, INTC, 0 }, - Package(){0x0000FFFF, 3, INTD, 0 }, - }) - - Name(APS4, Package(){ - /* PCIe slot - Hooked to PCIe slot 4 */ - Package(){0x0000FFFF, 0, 0, 16 }, - Package(){0x0000FFFF, 1, 0, 17 }, - Package(){0x0000FFFF, 2, 0, 18 }, - Package(){0x0000FFFF, 3, 0, 19 }, - }) - - Name(PS5, Package(){ - /* PCIe slot - Hooked to PCIe slot 5 */ - Package(){0x0000FFFF, 0, INTB, 0 }, - Package(){0x0000FFFF, 1, INTC, 0 }, - Package(){0x0000FFFF, 2, INTD, 0 }, - Package(){0x0000FFFF, 3, INTA, 0 }, - }) - - Name(APS5, Package(){ - /* PCIe slot - Hooked to PCIe slot 5 */ - Package(){0x0000FFFF, 0, 0, 17 }, - Package(){0x0000FFFF, 1, 0, 18 }, - Package(){0x0000FFFF, 2, 0, 19 }, - Package(){0x0000FFFF, 3, 0, 16 }, - }) - - Name(PS6, Package(){ - /* PCIe slot - Hooked to PCIe slot 6 */ - Package(){0x0000FFFF, 0, INTC, 0 }, - Package(){0x0000FFFF, 1, INTD, 0 }, - Package(){0x0000FFFF, 2, INTA, 0 }, - Package(){0x0000FFFF, 3, INTB, 0 }, - }) - - Name(APS6, Package(){ - /* PCIe slot - Hooked to PCIe slot 6 */ - Package(){0x0000FFFF, 0, 0, 18 }, - Package(){0x0000FFFF, 1, 0, 19 }, - Package(){0x0000FFFF, 2, 0, 16 }, - Package(){0x0000FFFF, 3, 0, 17 }, - }) - - Name(PS7, Package(){ - /* The onboard Ethernet chip - Hooked to PCIe slot 7 */ - Package(){0x0000FFFF, 0, INTD, 0 }, - Package(){0x0000FFFF, 1, INTA, 0 }, - Package(){0x0000FFFF, 2, INTB, 0 }, - Package(){0x0000FFFF, 3, INTC, 0 }, - }) - - Name(APS7, Package(){ - /* The onboard Ethernet chip - Hooked to PCIe slot 7 */ - Package(){0x0000FFFF, 0, 0, 19 }, - Package(){0x0000FFFF, 1, 0, 16 }, - Package(){0x0000FFFF, 2, 0, 17 }, - Package(){0x0000FFFF, 3, 0, 18 }, - }) - Name(PS9, Package(){ - /* PCIe slot - Hooked to PCIe slot 9 */ - Package(){0x0000FFFF, 0, INTD, 0 }, - Package(){0x0000FFFF, 1, INTA, 0 }, - Package(){0x0000FFFF, 2, INTB, 0 }, - Package(){0x0000FFFF, 3, INTC, 0 }, - }) - - Name(APS9, Package(){ - /* PCIe slot - Hooked to PCIe slot 9 */ - Package(){0x0000FFFF, 0, 0, 17 }, - Package(){0x0000FFFF, 1, 0, 18 }, - Package(){0x0000FFFF, 2, 0, 19 }, - Package(){0x0000FFFF, 3, 0, 16 }, - }) - Name(PSa, Package(){ - /* PCIe slot - Hooked to PCIe slot 10 */ - Package(){0x0000FFFF, 0, INTD, 0 }, - Package(){0x0000FFFF, 1, INTA, 0 }, - Package(){0x0000FFFF, 2, INTB, 0 }, - Package(){0x0000FFFF, 3, INTC, 0 }, - }) - - Name(APSa, Package(){ - /* PCIe slot - Hooked to PCIe slot 10 */ - Package(){0x0000FFFF, 0, 0, 18 }, - Package(){0x0000FFFF, 1, 0, 19 }, - Package(){0x0000FFFF, 2, 0, 16 }, - Package(){0x0000FFFF, 3, 0, 17 }, - }) - - Name(PCIB, Package(){ - /* PCI slots: slot 0, slot 1, slot 2 behind Dev14, Fun4. */ - Package(){0x0005FFFF, 0, 0, 0x14 }, - Package(){0x0005FFFF, 1, 0, 0x15 }, - Package(){0x0005FFFF, 2, 0, 0x16 }, - Package(){0x0005FFFF, 3, 0, 0x17 }, - Package(){0x0006FFFF, 0, 0, 0x15 }, - Package(){0x0006FFFF, 1, 0, 0x16 }, - Package(){0x0006FFFF, 2, 0, 0x17 }, - Package(){0x0006FFFF, 3, 0, 0x14 }, - Package(){0x0007FFFF, 0, 0, 0x16 }, - Package(){0x0007FFFF, 1, 0, 0x17 }, - Package(){0x0007FFFF, 2, 0, 0x14 }, - Package(){0x0007FFFF, 3, 0, 0x15 }, - }) -} diff --git a/src/mainboard/gigabyte/ma785gm/acpi/sata.asl b/src/mainboard/gigabyte/ma785gm/acpi/sata.asl deleted file mode 100644 index cb9b221ba3..0000000000 --- a/src/mainboard/gigabyte/ma785gm/acpi/sata.asl +++ /dev/null @@ -1,145 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2010 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -/* simple name description */ - -/* -Scope (_SB) { - Device(PCI0) { - Device(SATA) { - Name(_ADR, 0x00110000) - #include "sata.asl" - } - } -} -*/ - -Name(STTM, Buffer(20) { - 0x78, 0x00, 0x00, 0x00, 0x0f, 0x00, 0x00, 0x00, - 0x78, 0x00, 0x00, 0x00, 0x0f, 0x00, 0x00, 0x00, - 0x1f, 0x00, 0x00, 0x00 -}) - -/* Start by clearing the PhyRdyChg bits */ -Method(_INI) { - \_GPE._L1F() -} - -Device(PMRY) -{ - Name(_ADR, 0) - Method(_GTM, 0x0, NotSerialized) { - Return(STTM) - } - Method(_STM, 0x3, NotSerialized) {} - - Device(PMST) { - Name(_ADR, 0) - Method(_STA,0) { - if (LGreater(P0IS,0)) { - return (0x0F) /* sata is visible */ - } - else { - return (0x00) /* sata is missing */ - } - } - }/* end of PMST */ - - Device(PSLA) - { - Name(_ADR, 1) - Method(_STA,0) { - if (LGreater(P1IS,0)) { - return (0x0F) /* sata is visible */ - } - else { - return (0x00) /* sata is missing */ - } - } - } /* end of PSLA */ -} /* end of PMRY */ - - -Device(SEDY) -{ - Name(_ADR, 1) /* IDE Scondary Channel */ - Method(_GTM, 0x0, NotSerialized) { - Return(STTM) - } - Method(_STM, 0x3, NotSerialized) {} - - Device(SMST) - { - Name(_ADR, 0) - Method(_STA,0) { - if (LGreater(P2IS,0)) { - return (0x0F) /* sata is visible */ - } - else { - return (0x00) /* sata is missing */ - } - } - } /* end of SMST */ - - Device(SSLA) - { - Name(_ADR, 1) - Method(_STA,0) { - if (LGreater(P3IS,0)) { - return (0x0F) /* sata is visible */ - } - else { - return (0x00) /* sata is missing */ - } - } - } /* end of SSLA */ -} /* end of SEDY */ - -/* SATA Hot Plug Support */ -Scope(\_GPE) { - Method(_L1F,0x0,NotSerialized) { - if (\_SB.P0PR) { - if (LGreater(\_SB.P0IS,0)) { - sleep(32) - } - Notify(\_SB.PCI0.STCR.PMRY.PMST, 0x01) /* NOTIFY_DEVICE_CHECK */ - store(one, \_SB.P0PR) - } - - if (\_SB.P1PR) { - if (LGreater(\_SB.P1IS,0)) { - sleep(32) - } - Notify(\_SB.PCI0.STCR.PMRY.PSLA, 0x01) /* NOTIFY_DEVICE_CHECK */ - store(one, \_SB.P1PR) - } - - if (\_SB.P2PR) { - if (LGreater(\_SB.P2IS,0)) { - sleep(32) - } - Notify(\_SB.PCI0.STCR.SEDY.SMST, 0x01) /* NOTIFY_DEVICE_CHECK */ - store(one, \_SB.P2PR) - } - - if (\_SB.P3PR) { - if (LGreater(\_SB.P3IS,0)) { - sleep(32) - } - Notify(\_SB.PCI0.STCR.SEDY.SSLA, 0x01) /* NOTIFY_DEVICE_CHECK */ - store(one, \_SB.P3PR) - } - } -} diff --git a/src/mainboard/gigabyte/ma785gm/acpi/usb.asl b/src/mainboard/gigabyte/ma785gm/acpi/usb.asl deleted file mode 100644 index a3ccb97ff9..0000000000 --- a/src/mainboard/gigabyte/ma785gm/acpi/usb.asl +++ /dev/null @@ -1,158 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2010 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -/* simple name description */ -/* -#include -DefinitionBlock ("DSDT.AML", "DSDT", 0x01, OEM_ID, ACPI_TABLE_CREATOR, 0x00010001 - ) - { - #include "usb.asl" - } -*/ -Method(UCOC, 0) { - Sleep(20) - Store(0x13,CMTI) - Store(0,GPSL) -} - -/* USB Port 0 overcurrent uses Gpm 0 */ -If(LLessEqual(UOM0,9)) { - Scope (\_GPE) { - Method (_L13) { - UCOC() - if(LEqual(GPB0,PLC0)) { - Not(PLC0,PLC0) - Store(PLC0, \_SB.PT0D) - } - } - } -} - -/* USB Port 1 overcurrent uses Gpm 1 */ -If (LLessEqual(UOM1,9)) { - Scope (\_GPE) { - Method (_L14) { - UCOC() - if (LEqual(GPB1,PLC1)) { - Not(PLC1,PLC1) - Store(PLC1, \_SB.PT1D) - } - } - } -} - -/* USB Port 2 overcurrent uses Gpm 2 */ -If (LLessEqual(UOM2,9)) { - Scope (\_GPE) { - Method (_L15) { - UCOC() - if (LEqual(GPB2,PLC2)) { - Not(PLC2,PLC2) - Store(PLC2, \_SB.PT2D) - } - } - } -} - -/* USB Port 3 overcurrent uses Gpm 3 */ -If (LLessEqual(UOM3,9)) { - Scope (\_GPE) { - Method (_L16) { - UCOC() - if (LEqual(GPB3,PLC3)) { - Not(PLC3,PLC3) - Store(PLC3, \_SB.PT3D) - } - } - } -} - -/* USB Port 4 overcurrent uses Gpm 4 */ -If (LLessEqual(UOM4,9)) { - Scope (\_GPE) { - Method (_L19) { - UCOC() - if (LEqual(GPB4,PLC4)) { - Not(PLC4,PLC4) - Store(PLC4, \_SB.PT4D) - } - } - } -} - -/* USB Port 5 overcurrent uses Gpm 5 */ -If (LLessEqual(UOM5,9)) { - Scope (\_GPE) { - Method (_L1A) { - UCOC() - if (LEqual(GPB5,PLC5)) { - Not(PLC5,PLC5) - Store(PLC5, \_SB.PT5D) - } - } - } -} - -/* USB Port 6 overcurrent uses Gpm 6 */ -If (LLessEqual(UOM6,9)) { - Scope (\_GPE) { - /* Method (_L1C) { */ - Method (_L06) { - UCOC() - if (LEqual(GPB6,PLC6)) { - Not(PLC6,PLC6) - Store(PLC6, \_SB.PT6D) - } - } - } -} - -/* USB Port 7 overcurrent uses Gpm 7 */ -If (LLessEqual(UOM7,9)) { - Scope (\_GPE) { - /* Method (_L1D) { */ - Method (_L07) { - UCOC() - if (LEqual(GPB7,PLC7)) { - Not(PLC7,PLC7) - Store(PLC7, \_SB.PT7D) - } - } - } -} - -/* USB Port 8 overcurrent uses Gpm 8 */ -If (LLessEqual(UOM8,9)) { - Scope (\_GPE) { - Method (_L17) { - if (LEqual(G8IS,PLC8)) { - Not(PLC8,PLC8) - Store(PLC8, \_SB.PT8D) - } - } - } -} - -/* USB Port 9 overcurrent uses Gpm 9 */ -If (LLessEqual(UOM9,9)) { - Scope (\_GPE) { - Method (_L0E) { - if (LEqual(G9IS,0)) { - Store(1,\_SB.PT9D) - } - } - } -} diff --git a/src/mainboard/gigabyte/ma785gm/acpi_tables.c b/src/mainboard/gigabyte/ma785gm/acpi_tables.c deleted file mode 100644 index 967343da67..0000000000 --- a/src/mainboard/gigabyte/ma785gm/acpi_tables.c +++ /dev/null @@ -1,44 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2010 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include -#include - -unsigned long acpi_fill_madt(unsigned long current) -{ - /* create all subtables for processors */ - current = acpi_create_madt_lapics(current); - - /* Write SB700 IOAPIC, only one */ - current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, 2, - IO_APIC_ADDR, 0); - - current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) - current, 0, 0, 2, 0); - current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) - current, 0, 9, 9, 0xF); - /* 0: mean bus 0--->ISA */ - /* 0: PIC 0 */ - /* 2: APIC 2 */ - /* 5 mean: 0101 --> Edge-triggered, Active high */ - - /* create all subtables for processors */ - /* current = acpi_create_madt_lapic_nmis(current, 5, 1); */ - /* 1: LINT1 connect to NMI */ - - return current; -} diff --git a/src/mainboard/gigabyte/ma785gm/board_info.txt b/src/mainboard/gigabyte/ma785gm/board_info.txt deleted file mode 100644 index 66857bf1ce..0000000000 --- a/src/mainboard/gigabyte/ma785gm/board_info.txt +++ /dev/null @@ -1,3 +0,0 @@ -Category: desktop -Board URL: http://www.gigabyte.us/products/product-page.aspx?pid=3447#sp -Release year: 2009 diff --git a/src/mainboard/gigabyte/ma785gm/cmos.layout b/src/mainboard/gigabyte/ma785gm/cmos.layout deleted file mode 100644 index 6c3d3f6c9e..0000000000 --- a/src/mainboard/gigabyte/ma785gm/cmos.layout +++ /dev/null @@ -1,52 +0,0 @@ -entries - -0 384 r 0 reserved_memory -384 1 e 4 boot_option -388 4 h 0 reboot_counter -#392 3 r 0 unused -395 1 e 1 hw_scrubber -396 1 e 1 interleave_chip_selects -397 2 e 8 max_mem_clock -399 1 e 2 multi_core -400 1 e 1 power_on_after_fail -412 4 e 6 debug_level -440 4 e 9 slow_cpu -444 1 e 1 nmi -445 1 e 1 gart -456 1 e 1 ECC_memory -728 256 h 0 user_data -984 16 h 0 check_sum -# Reserve the extended AMD configuration registers -1000 24 r 0 amd_reserved - - - -enumerations - -#ID value text -1 0 Disable -1 1 Enable -2 0 Enable -2 1 Disable -4 0 Fallback -4 1 Normal -6 5 Notice -6 6 Info -6 7 Debug -6 8 Spew -8 0 400Mhz -8 1 333Mhz -8 2 266Mhz -8 3 200Mhz -9 0 off -9 1 87.5% -9 2 75.0% -9 3 62.5% -9 4 50.0% -9 5 37.5% -9 6 25.0% -9 7 12.5% - -checksums - -checksum 392 983 984 diff --git a/src/mainboard/gigabyte/ma785gm/devicetree.cb b/src/mainboard/gigabyte/ma785gm/devicetree.cb deleted file mode 100644 index 65c76fbfea..0000000000 --- a/src/mainboard/gigabyte/ma785gm/devicetree.cb +++ /dev/null @@ -1,115 +0,0 @@ -# sample config for gigabyte/ma785gm -chip northbridge/amd/amdfam10/root_complex - device cpu_cluster 0 on - chip cpu/amd/socket_AM3 #L1 and DDR2 - device lapic 0 on end - end - end - device domain 0 on - subsystemid 0x1022 0x3060 inherit - chip northbridge/amd/amdfam10 - device pci 18.0 on # northbridge - chip southbridge/amd/rs780 - device pci 0.0 on end # HT 0x9601 - device pci 1.0 on end # Internal Graphics P2P bridge 0x9602 - device pci 2.0 on end # PCIE P2P bridge (external graphics) 0x9603 - device pci 3.0 off end # PCIE P2P bridge 0x960b - device pci 4.0 off end # PCIE P2P bridge 0x9604 - device pci 5.0 off end # PCIE P2P bridge 0x9605 - device pci 6.0 off end # PCIE P2P bridge 0x9606 - device pci 7.0 off end # PCIE P2P bridge 0x9607 - device pci 8.0 off end # NB/SB Link P2P bridge - device pci 9.0 off end # - device pci a.0 on end # PCIE P2P bridge 0x9609 - register "gppsb_configuration" = "1" # Configuration B - register "gpp_configuration" = "3" # Configuration D default - register "port_enable" = "0x6fc" - register "gfx_dev2_dev3" = "1" - register "gfx_dual_slot" = "2" - - register "gfx_lane_reversal" = "0" - register "gfx_tmds" = "0" - register "gfx_compliance" = "0" - register "gfx_reconfiguration" = "1" - register "gfx_link_width" = "0" - end - chip southbridge/amd/sb700 # it is under NB/SB Link, but on the same pri bus - device pci 11.0 on end # SATA - device pci 12.0 on end # USB - device pci 12.1 on end # USB - device pci 12.2 on end # USB - device pci 13.0 on end # USB - device pci 13.1 on end # USB - device pci 13.2 on end # USB - device pci 14.0 on # SM - chip drivers/generic/generic #dimm 0-0-0 - device i2c 50 on end - end - chip drivers/generic/generic #dimm 0-0-1 - device i2c 51 on end - end - chip drivers/generic/generic #dimm 0-1-0 - device i2c 52 on end - end - chip drivers/generic/generic #dimm 0-1-1 - device i2c 53 on end - end - end # SM - device pci 14.1 on end # IDE 0x439c - device pci 14.2 on end # HDA 0x4383 - device pci 14.3 on # LPC 0x439d - chip superio/ite/it8718f - device pnp 2e.0 off # Floppy - io 0x60 = 0x3f0 - irq 0x70 = 6 - drq 0x74 = 2 - end - device pnp 2e.1 on # Com1 - io 0x60 = 0x3f8 - irq 0x70 = 4 - end - device pnp 2e.2 off # Com2 - io 0x60 = 0x2f8 - irq 0x70 = 3 - end - device pnp 2e.3 off # Parallel Port - io 0x60 = 0x378 - irq 0x70 = 7 - end - device pnp 2e.4 off end # EC - device pnp 2e.5 on # Keyboard - io 0x60 = 0x60 - io 0x62 = 0x64 - irq 0x70 = 1 - end - device pnp 2e.6 on # Mouse - irq 0x70 = 12 - end - device pnp 2e.7 off # GPIO, must be closed for unresolved reason. - end - device pnp 2e.8 off # MIDI - io 0x60 = 0x300 - irq 0x70 = 9 - end - device pnp 2e.9 off # GAME - io 0x60 = 0x220 - end - device pnp 2e.a off end # CIR - end #superio/ite/it8718f - end #LPC - device pci 14.4 on end # PCI 0x4384 - device pci 14.5 on end # USB 2 - register "boot_switch_sata_ide" = "0" # 0: boot from SATA. 1: IDE - end #southbridge/amd/sb700 - end # device pci 18.0 - - device pci 18.0 on end - device pci 18.0 on end - device pci 18.1 on end - device pci 18.2 on end - device pci 18.3 on end - device pci 18.4 on end - end - end #domain - #for node 32 to node 63 -end diff --git a/src/mainboard/gigabyte/ma785gm/dsdt.asl b/src/mainboard/gigabyte/ma785gm/dsdt.asl deleted file mode 100644 index eec3093b8e..0000000000 --- a/src/mainboard/gigabyte/ma785gm/dsdt.asl +++ /dev/null @@ -1,1718 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2010 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -/* DefinitionBlock Statement */ -#include -DefinitionBlock ( - "DSDT.AML", /* Output filename */ - "DSDT", /* Signature */ - 0x02, /* DSDT Revision, needs to be 2 for 64bit */ - OEM_ID, - ACPI_TABLE_CREATOR, - 0x00010001 /* OEM Revision */ - ) -{ /* Start of ASL file */ - /* #include */ /* Include global debug methods if needed */ - - /* Data to be patched by the BIOS during POST */ - /* FIXME the patching is not done yet! */ - /* Memory related values */ - Name(LOMH, 0x0) /* Start of unused memory in C0000-E0000 range */ - Name(PBAD, 0x0) /* Address of BIOS area (If TOM2 != 0, Addr >> 16) */ - Name(PBLN, 0x0) /* Length of BIOS area */ - - Name(PCBA, 0xE0000000) /* Base address of PCIe config space */ - Name(HPBA, 0xFED00000) /* Base address of HPET table */ - - /* USB overcurrent mapping pins. */ - Name(UOM0, 0) - Name(UOM1, 2) - Name(UOM2, 0) - Name(UOM3, 7) - Name(UOM4, 2) - Name(UOM5, 2) - Name(UOM6, 6) - Name(UOM7, 2) - Name(UOM8, 6) - Name(UOM9, 6) - - /* Some global data */ - Name(OSVR, 3) /* Assume nothing. WinXp = 1, Vista = 2, Linux = 3, WinCE = 4 */ - Name(OSV, Ones) /* Assume nothing */ - Name(PMOD, One) /* Assume APIC */ - - /* - * Processor Object - * - */ - Scope (\_PR) { /* define processor scope */ - Device (CPU0) { - Name (_HID, "ACPI0007") - Name (_UID, 0) - #include "acpi/cpstate.asl" - } - Device (CPU1) { - Name (_HID, "ACPI0007") - Name (_UID, 1) - #include "acpi/cpstate.asl" - } - Device (CPU2) { - Name (_HID, "ACPI0007") - Name (_UID, 2) - #include "acpi/cpstate.asl" - } - Device (CPU3) { - Name (_HID, "ACPI0007") - Name (_UID, 3) - #include "acpi/cpstate.asl" - } - } /* End _PR scope */ - - /* PIC IRQ mapping registers, C00h-C01h */ - OperationRegion(PRQM, SystemIO, 0x00000C00, 0x00000002) - Field(PRQM, ByteAcc, NoLock, Preserve) { - PRQI, 0x00000008, - PRQD, 0x00000008, /* Offset: 1h */ - } - IndexField(PRQI, PRQD, ByteAcc, NoLock, Preserve) { - PINA, 0x00000008, /* Index 0 */ - PINB, 0x00000008, /* Index 1 */ - PINC, 0x00000008, /* Index 2 */ - PIND, 0x00000008, /* Index 3 */ - AINT, 0x00000008, /* Index 4 */ - SINT, 0x00000008, /* Index 5 */ - , 0x00000008, /* Index 6 */ - AAUD, 0x00000008, /* Index 7 */ - AMOD, 0x00000008, /* Index 8 */ - PINE, 0x00000008, /* Index 9 */ - PINF, 0x00000008, /* Index A */ - PING, 0x00000008, /* Index B */ - PINH, 0x00000008, /* Index C */ - } - - /* PCI Error control register */ - OperationRegion(PERC, SystemIO, 0x00000C14, 0x00000001) - Field(PERC, ByteAcc, NoLock, Preserve) { - SENS, 0x00000001, - PENS, 0x00000001, - SENE, 0x00000001, - PENE, 0x00000001, - } - - /* Client Management index/data registers */ - OperationRegion(CMT, SystemIO, 0x00000C50, 0x00000002) - Field(CMT, ByteAcc, NoLock, Preserve) { - CMTI, 8, - /* Client Management Data register */ - G64E, 1, - G64O, 1, - G32O, 2, - , 2, - GPSL, 2, - } - - /* GPM Port register */ - OperationRegion(GPT, SystemIO, 0x00000C52, 0x00000001) - Field(GPT, ByteAcc, NoLock, Preserve) { - GPB0,1, - GPB1,1, - GPB2,1, - GPB3,1, - GPB4,1, - GPB5,1, - GPB6,1, - GPB7,1, - } - - /* Flash ROM program enable register */ - OperationRegion(FRE, SystemIO, 0x00000C6F, 0x00000001) - Field(FRE, ByteAcc, NoLock, Preserve) { - , 0x00000006, - FLRE, 0x00000001, - } - - /* PM2 index/data registers */ - OperationRegion(PM2R, SystemIO, 0x00000CD0, 0x00000002) - Field(PM2R, ByteAcc, NoLock, Preserve) { - PM2I, 0x00000008, - PM2D, 0x00000008, - } - - /* Power Management I/O registers */ - OperationRegion(PIOR, SystemIO, 0x00000CD6, 0x00000002) - Field(PIOR, ByteAcc, NoLock, Preserve) { - PIOI, 0x00000008, - PIOD, 0x00000008, - } - IndexField (PIOI, PIOD, ByteAcc, NoLock, Preserve) { - Offset(0x00), /* MiscControl */ - , 1, - T1EE, 1, - T2EE, 1, - Offset(0x01), /* MiscStatus */ - , 1, - T1E, 1, - T2E, 1, - Offset(0x04), /* SmiWakeUpEventEnable3 */ - , 7, - SSEN, 1, - Offset(0x07), /* SmiWakeUpEventStatus3 */ - , 7, - CSSM, 1, - Offset(0x10), /* AcpiEnable */ - , 6, - PWDE, 1, - Offset(0x1C), /* ProgramIoEnable */ - , 3, - MKME, 1, - IO3E, 1, - IO2E, 1, - IO1E, 1, - IO0E, 1, - Offset(0x1D), /* IOMonitorStatus */ - , 3, - MKMS, 1, - IO3S, 1, - IO2S, 1, - IO1S, 1, - IO0S,1, - Offset(0x20), /* AcpiPmEvtBlk */ - APEB, 16, - Offset(0x36), /* GEvtLevelConfig */ - , 6, - ELC6, 1, - ELC7, 1, - Offset(0x37), /* GPMLevelConfig0 */ - , 3, - PLC0, 1, - PLC1, 1, - PLC2, 1, - PLC3, 1, - PLC8, 1, - Offset(0x38), /* GPMLevelConfig1 */ - , 1, - PLC4, 1, - PLC5, 1, - , 1, - PLC6, 1, - PLC7, 1, - Offset(0x3B), /* PMEStatus1 */ - GP0S, 1, - GM4S, 1, - GM5S, 1, - APS, 1, - GM6S, 1, - GM7S, 1, - GP2S, 1, - STSS, 1, - Offset(0x55), /* SoftPciRst */ - SPRE, 1, - , 1, - , 1, - PNAT, 1, - PWMK, 1, - PWNS, 1, - - /* Offset(0x61), */ /* Options_1 */ - /* ,7, */ - /* R617,1, */ - - Offset(0x65), /* UsbPMControl */ - , 4, - URRE, 1, - Offset(0x68), /* MiscEnable68 */ - , 3, - TMTE, 1, - , 1, - Offset(0x92), /* GEVENTIN */ - , 7, - E7IS, 1, - Offset(0x96), /* GPM98IN */ - G8IS, 1, - G9IS, 1, - Offset(0x9A), /* EnhanceControl */ - ,7, - HPDE, 1, - Offset(0xA8), /* PIO7654Enable */ - IO4E, 1, - IO5E, 1, - IO6E, 1, - IO7E, 1, - Offset(0xA9), /* PIO7654Status */ - IO4S, 1, - IO5S, 1, - IO6S, 1, - IO7S, 1, - } - - /* PM1 Event Block - * First word is PM1_Status, Second word is PM1_Enable - */ - OperationRegion(P1EB, SystemIO, APEB, 0x04) - Field(P1EB, ByteAcc, NoLock, Preserve) { - TMST, 1, - , 3, - BMST, 1, - GBST, 1, - Offset(0x01), - PBST, 1, - , 1, - RTST, 1, - , 3, - PWST, 1, - SPWS, 1, - Offset(0x02), - TMEN, 1, - , 4, - GBEN, 1, - Offset(0x03), - PBEN, 1, - , 1, - RTEN, 1, - , 3, - PWDA, 1, - } - - Scope(\_SB) { - /* PCIe Configuration Space for 16 busses */ - OperationRegion(PCFG, SystemMemory, PCBA, 0x01000000) /* Each bus consumes 1MB */ - Field(PCFG, ByteAcc, NoLock, Preserve) { - /* Byte offsets are computed using the following technique: - * ((bus number + 1) * ((device number * 8) * 4096)) + register offset - * The 8 comes from 8 functions per device, and 4096 bytes per function config space - */ - Offset(0x00088024), /* Byte offset to SATA register 24h - Bus 0, Device 17, Function 0 */ - STB5, 32, - Offset(0x00098042), /* Byte offset to OHCI0 register 42h - Bus 0, Device 19, Function 0 */ - PT0D, 1, - PT1D, 1, - PT2D, 1, - PT3D, 1, - PT4D, 1, - PT5D, 1, - PT6D, 1, - PT7D, 1, - PT8D, 1, - PT9D, 1, - Offset(0x000A0004), /* Byte offset to SMBUS register 4h - Bus 0, Device 20, Function 0 */ - SBIE, 1, - SBME, 1, - Offset(0x000A0008), /* Byte offset to SMBUS register 8h - Bus 0, Device 20, Function 0 */ - SBRI, 8, - Offset(0x000A0014), /* Byte offset to SMBUS register 14h - Bus 0, Device 20, Function 0 */ - SBB1, 32, - Offset(0x000A0078), /* Byte offset to SMBUS register 78h - Bus 0, Device 20, Function 0 */ - ,14, - P92E, 1, /* Port92 decode enable */ - } - - OperationRegion(SB5, SystemMemory, STB5, 0x1000) - Field(SB5, AnyAcc, NoLock, Preserve){ - /* Port 0 */ - Offset(0x120), /* Port 0 Task file status */ - P0ER, 1, - , 2, - P0DQ, 1, - , 3, - P0BY, 1, - Offset(0x128), /* Port 0 Serial ATA status */ - P0DD, 4, - , 4, - P0IS, 4, - Offset(0x12C), /* Port 0 Serial ATA control */ - P0DI, 4, - Offset(0x130), /* Port 0 Serial ATA error */ - , 16, - P0PR, 1, - - /* Port 1 */ - offset(0x1A0), /* Port 1 Task file status */ - P1ER, 1, - , 2, - P1DQ, 1, - , 3, - P1BY, 1, - Offset(0x1A8), /* Port 1 Serial ATA status */ - P1DD, 4, - , 4, - P1IS, 4, - Offset(0x1AC), /* Port 1 Serial ATA control */ - P1DI, 4, - Offset(0x1B0), /* Port 1 Serial ATA error */ - , 16, - P1PR, 1, - - /* Port 2 */ - Offset(0x220), /* Port 2 Task file status */ - P2ER, 1, - , 2, - P2DQ, 1, - , 3, - P2BY, 1, - Offset(0x228), /* Port 2 Serial ATA status */ - P2DD, 4, - , 4, - P2IS, 4, - Offset(0x22C), /* Port 2 Serial ATA control */ - P2DI, 4, - Offset(0x230), /* Port 2 Serial ATA error */ - , 16, - P2PR, 1, - - /* Port 3 */ - Offset(0x2A0), /* Port 3 Task file status */ - P3ER, 1, - , 2, - P3DQ, 1, - , 3, - P3BY, 1, - Offset(0x2A8), /* Port 3 Serial ATA status */ - P3DD, 4, - , 4, - P3IS, 4, - Offset(0x2AC), /* Port 3 Serial ATA control */ - P3DI, 4, - Offset(0x2B0), /* Port 3 Serial ATA error */ - , 16, - P3PR, 1, - } - } - - - #include "acpi/routing.asl" - - Scope(\_SB) { - - Method(OSFL, 0){ - - if(LNotEqual(OSVR, Ones)) {Return(OSVR)} /* OS version was already detected */ - - if(CondRefOf(\_OSI)) - { - Store(1, OSVR) /* Assume some form of XP */ - if (\_OSI("Windows 2006")) /* Vista */ - { - Store(2, OSVR) - } - } else { - If(WCMP(\_OS,"Linux")) { - Store(3, OSVR) /* Linux */ - } Else { - Store(4, OSVR) /* Gotta be WinCE */ - } - } - Return(OSVR) - } - - Method(_PIC, 0x01, NotSerialized) - { - If (Arg0) - { - \_SB.CIRQ() - } - Store(Arg0, PMOD) - } - Method(CIRQ, 0x00, NotSerialized){ - Store(0, PINA) - Store(0, PINB) - Store(0, PINC) - Store(0, PIND) - Store(0, PINE) - Store(0, PINF) - Store(0, PING) - Store(0, PINH) - } - - Name(IRQB, ResourceTemplate(){ - IRQ(Level,ActiveLow,Shared){15} - }) - - Name(IRQP, ResourceTemplate(){ - IRQ(Level,ActiveLow,Exclusive){3, 4, 5, 7, 10, 11, 12, 15} - }) - - Name(PITF, ResourceTemplate(){ - IRQ(Level,ActiveLow,Exclusive){9} - }) - - Device(INTA) { - Name(_HID, EISAID("PNP0C0F")) - Name(_UID, 1) - - Method(_STA, 0) { - if (PINA) { - Return(0x0B) /* sata is invisible */ - } else { - Return(0x09) /* sata is disabled */ - } - } /* End Method(_SB.INTA._STA) */ - - Method(_DIS ,0) { - /* DBGO("\\_SB\\LNKA\\_DIS\n") */ - Store(0, PINA) - } /* End Method(_SB.INTA._DIS) */ - - Method(_PRS ,0) { - /* DBGO("\\_SB\\LNKA\\_PRS\n") */ - Return(IRQP) - } /* Method(_SB.INTA._PRS) */ - - Method(_CRS ,0) { - /* DBGO("\\_SB\\LNKA\\_CRS\n") */ - CreateWordField(IRQB, 0x1, IRQN) - ShiftLeft(1, PINA, IRQN) - Return(IRQB) - } /* Method(_SB.INTA._CRS) */ - - Method(_SRS, 1) { - /* DBGO("\\_SB\\LNKA\\_CRS\n") */ - CreateWordField(ARG0, 1, IRQM) - - /* Use lowest available IRQ */ - FindSetRightBit(IRQM, Local0) - if (Local0) { - Decrement(Local0) - } - Store(Local0, PINA) - } /* End Method(_SB.INTA._SRS) */ - } /* End Device(INTA) */ - - Device(INTB) { - Name(_HID, EISAID("PNP0C0F")) - Name(_UID, 2) - - Method(_STA, 0) { - if (PINB) { - Return(0x0B) /* sata is invisible */ - } else { - Return(0x09) /* sata is disabled */ - } - } /* End Method(_SB.INTB._STA) */ - - Method(_DIS ,0) { - /* DBGO("\\_SB\\LNKB\\_DIS\n") */ - Store(0, PINB) - } /* End Method(_SB.INTB._DIS) */ - - Method(_PRS ,0) { - /* DBGO("\\_SB\\LNKB\\_PRS\n") */ - Return(IRQP) - } /* Method(_SB.INTB._PRS) */ - - Method(_CRS ,0) { - /* DBGO("\\_SB\\LNKB\\_CRS\n") */ - CreateWordField(IRQB, 0x1, IRQN) - ShiftLeft(1, PINB, IRQN) - Return(IRQB) - } /* Method(_SB.INTB._CRS) */ - - Method(_SRS, 1) { - /* DBGO("\\_SB\\LNKB\\_CRS\n") */ - CreateWordField(ARG0, 1, IRQM) - - /* Use lowest available IRQ */ - FindSetRightBit(IRQM, Local0) - if (Local0) { - Decrement(Local0) - } - Store(Local0, PINB) - } /* End Method(_SB.INTB._SRS) */ - } /* End Device(INTB) */ - - Device(INTC) { - Name(_HID, EISAID("PNP0C0F")) - Name(_UID, 3) - - Method(_STA, 0) { - if (PINC) { - Return(0x0B) /* sata is invisible */ - } else { - Return(0x09) /* sata is disabled */ - } - } /* End Method(_SB.INTC._STA) */ - - Method(_DIS ,0) { - /* DBGO("\\_SB\\LNKC\\_DIS\n") */ - Store(0, PINC) - } /* End Method(_SB.INTC._DIS) */ - - Method(_PRS ,0) { - /* DBGO("\\_SB\\LNKC\\_PRS\n") */ - Return(IRQP) - } /* Method(_SB.INTC._PRS) */ - - Method(_CRS ,0) { - /* DBGO("\\_SB\\LNKC\\_CRS\n") */ - CreateWordField(IRQB, 0x1, IRQN) - ShiftLeft(1, PINC, IRQN) - Return(IRQB) - } /* Method(_SB.INTC._CRS) */ - - Method(_SRS, 1) { - /* DBGO("\\_SB\\LNKC\\_CRS\n") */ - CreateWordField(ARG0, 1, IRQM) - - /* Use lowest available IRQ */ - FindSetRightBit(IRQM, Local0) - if (Local0) { - Decrement(Local0) - } - Store(Local0, PINC) - } /* End Method(_SB.INTC._SRS) */ - } /* End Device(INTC) */ - - Device(INTD) { - Name(_HID, EISAID("PNP0C0F")) - Name(_UID, 4) - - Method(_STA, 0) { - if (PIND) { - Return(0x0B) /* sata is invisible */ - } else { - Return(0x09) /* sata is disabled */ - } - } /* End Method(_SB.INTD._STA) */ - - Method(_DIS ,0) { - /* DBGO("\\_SB\\LNKD\\_DIS\n") */ - Store(0, PIND) - } /* End Method(_SB.INTD._DIS) */ - - Method(_PRS ,0) { - /* DBGO("\\_SB\\LNKD\\_PRS\n") */ - Return(IRQP) - } /* Method(_SB.INTD._PRS) */ - - Method(_CRS ,0) { - /* DBGO("\\_SB\\LNKD\\_CRS\n") */ - CreateWordField(IRQB, 0x1, IRQN) - ShiftLeft(1, PIND, IRQN) - Return(IRQB) - } /* Method(_SB.INTD._CRS) */ - - Method(_SRS, 1) { - /* DBGO("\\_SB\\LNKD\\_CRS\n") */ - CreateWordField(ARG0, 1, IRQM) - - /* Use lowest available IRQ */ - FindSetRightBit(IRQM, Local0) - if (Local0) { - Decrement(Local0) - } - Store(Local0, PIND) - } /* End Method(_SB.INTD._SRS) */ - } /* End Device(INTD) */ - - Device(INTE) { - Name(_HID, EISAID("PNP0C0F")) - Name(_UID, 5) - - Method(_STA, 0) { - if (PINE) { - Return(0x0B) /* sata is invisible */ - } else { - Return(0x09) /* sata is disabled */ - } - } /* End Method(_SB.INTE._STA) */ - - Method(_DIS ,0) { - /* DBGO("\\_SB\\LNKE\\_DIS\n") */ - Store(0, PINE) - } /* End Method(_SB.INTE._DIS) */ - - Method(_PRS ,0) { - /* DBGO("\\_SB\\LNKE\\_PRS\n") */ - Return(IRQP) - } /* Method(_SB.INTE._PRS) */ - - Method(_CRS ,0) { - /* DBGO("\\_SB\\LNKE\\_CRS\n") */ - CreateWordField(IRQB, 0x1, IRQN) - ShiftLeft(1, PINE, IRQN) - Return(IRQB) - } /* Method(_SB.INTE._CRS) */ - - Method(_SRS, 1) { - /* DBGO("\\_SB\\LNKE\\_CRS\n") */ - CreateWordField(ARG0, 1, IRQM) - - /* Use lowest available IRQ */ - FindSetRightBit(IRQM, Local0) - if (Local0) { - Decrement(Local0) - } - Store(Local0, PINE) - } /* End Method(_SB.INTE._SRS) */ - } /* End Device(INTE) */ - - Device(INTF) { - Name(_HID, EISAID("PNP0C0F")) - Name(_UID, 6) - - Method(_STA, 0) { - if (PINF) { - Return(0x0B) /* sata is invisible */ - } else { - Return(0x09) /* sata is disabled */ - } - } /* End Method(_SB.INTF._STA) */ - - Method(_DIS ,0) { - /* DBGO("\\_SB\\LNKF\\_DIS\n") */ - Store(0, PINF) - } /* End Method(_SB.INTF._DIS) */ - - Method(_PRS ,0) { - /* DBGO("\\_SB\\LNKF\\_PRS\n") */ - Return(PITF) - } /* Method(_SB.INTF._PRS) */ - - Method(_CRS ,0) { - /* DBGO("\\_SB\\LNKF\\_CRS\n") */ - CreateWordField(IRQB, 0x1, IRQN) - ShiftLeft(1, PINF, IRQN) - Return(IRQB) - } /* Method(_SB.INTF._CRS) */ - - Method(_SRS, 1) { - /* DBGO("\\_SB\\LNKF\\_CRS\n") */ - CreateWordField(ARG0, 1, IRQM) - - /* Use lowest available IRQ */ - FindSetRightBit(IRQM, Local0) - if (Local0) { - Decrement(Local0) - } - Store(Local0, PINF) - } /* End Method(_SB.INTF._SRS) */ - } /* End Device(INTF) */ - - Device(INTG) { - Name(_HID, EISAID("PNP0C0F")) - Name(_UID, 7) - - Method(_STA, 0) { - if (PING) { - Return(0x0B) /* sata is invisible */ - } else { - Return(0x09) /* sata is disabled */ - } - } /* End Method(_SB.INTG._STA) */ - - Method(_DIS ,0) { - /* DBGO("\\_SB\\LNKG\\_DIS\n") */ - Store(0, PING) - } /* End Method(_SB.INTG._DIS) */ - - Method(_PRS ,0) { - /* DBGO("\\_SB\\LNKG\\_PRS\n") */ - Return(IRQP) - } /* Method(_SB.INTG._CRS) */ - - Method(_CRS ,0) { - /* DBGO("\\_SB\\LNKG\\_CRS\n") */ - CreateWordField(IRQB, 0x1, IRQN) - ShiftLeft(1, PING, IRQN) - Return(IRQB) - } /* Method(_SB.INTG._CRS) */ - - Method(_SRS, 1) { - /* DBGO("\\_SB\\LNKG\\_CRS\n") */ - CreateWordField(ARG0, 1, IRQM) - - /* Use lowest available IRQ */ - FindSetRightBit(IRQM, Local0) - if (Local0) { - Decrement(Local0) - } - Store(Local0, PING) - } /* End Method(_SB.INTG._SRS) */ - } /* End Device(INTG) */ - - Device(INTH) { - Name(_HID, EISAID("PNP0C0F")) - Name(_UID, 8) - - Method(_STA, 0) { - if (PINH) { - Return(0x0B) /* sata is invisible */ - } else { - Return(0x09) /* sata is disabled */ - } - } /* End Method(_SB.INTH._STA) */ - - Method(_DIS ,0) { - /* DBGO("\\_SB\\LNKH\\_DIS\n") */ - Store(0, PINH) - } /* End Method(_SB.INTH._DIS) */ - - Method(_PRS ,0) { - /* DBGO("\\_SB\\LNKH\\_PRS\n") */ - Return(IRQP) - } /* Method(_SB.INTH._CRS) */ - - Method(_CRS ,0) { - /* DBGO("\\_SB\\LNKH\\_CRS\n") */ - CreateWordField(IRQB, 0x1, IRQN) - ShiftLeft(1, PINH, IRQN) - Return(IRQB) - } /* Method(_SB.INTH._CRS) */ - - Method(_SRS, 1) { - /* DBGO("\\_SB\\LNKH\\_CRS\n") */ - CreateWordField(ARG0, 1, IRQM) - - /* Use lowest available IRQ */ - FindSetRightBit(IRQM, Local0) - if (Local0) { - Decrement(Local0) - } - Store(Local0, PINH) - } /* End Method(_SB.INTH._SRS) */ - } /* End Device(INTH) */ - - } /* End Scope(_SB) */ - - #include - - /* Wake status package */ - Name(WKST,Package(){Zero, Zero}) - - /* - * \_PTS - Prepare to Sleep method - * - * Entry: - * Arg0=The value of the sleeping state S1=1, S2=2, etc - * - * Exit: - * -none- - * - * The _PTS control method is executed at the beginning of the sleep process - * for S1-S5. The sleeping value is passed to the _PTS control method. This - * control method may be executed a relatively long time before entering the - * sleep state and the OS may abort the operation without notification to - * the ACPI driver. This method cannot modify the configuration or power - * state of any device in the system. - */ - Method(\_PTS, 1) { - /* DBGO("\\_PTS\n") */ - /* DBGO("From S0 to S") */ - /* DBGO(Arg0) */ - /* DBGO("\n") */ - - /* Don't allow PCIRST# to reset USB */ - if (LEqual(Arg0,3)){ - Store(0,URRE) - } - - /* Clear sleep SMI status flag and enable sleep SMI trap. */ - /*Store(One, CSSM) - Store(One, SSEN)*/ - - /* On older chips, clear PciExpWakeDisEn */ - /*if (LLessEqual(\_SB.SBRI, 0x13)) { - * Store(0,\_SB.PWDE) - *} - */ - - /* Clear wake status structure. */ - Store(0, Index(WKST,0)) - Store(0, Index(WKST,1)) - \_SB.PCI0.SIOS (Arg0) - } /* End Method(\_PTS) */ - - /* - * The following method results in a "not a valid reserved NameSeg" - * warning so I have commented it out for the duration. It isn't - * used, so it could be removed. - * - * - * \_GTS OEM Going To Sleep method - * - * Entry: - * Arg0=The value of the sleeping state S1=1, S2=2 - * - * Exit: - * -none- - * - * Method(\_GTS, 1) { - * DBGO("\\_GTS\n") - * DBGO("From S0 to S") - * DBGO(Arg0) - * DBGO("\n") - * } - */ - - /* - * \_BFS OEM Back From Sleep method - * - * Entry: - * Arg0=The value of the sleeping state S1=1, S2=2 - * - * Exit: - * -none- - */ - Method(\_BFS, 1) { - /* DBGO("\\_BFS\n") */ - /* DBGO("From S") */ - /* DBGO(Arg0) */ - /* DBGO(" to S0\n") */ - } - - /* - * \_WAK System Wake method - * - * Entry: - * Arg0=The value of the sleeping state S1=1, S2=2 - * - * Exit: - * Return package of 2 DWords - * Dword 1 - Status - * 0x00000000 wake succeeded - * 0x00000001 Wake was signaled but failed due to lack of power - * 0x00000002 Wake was signaled but failed due to thermal condition - * Dword 2 - Power Supply state - * if non-zero the effective S-state the power supply entered - */ - Method(\_WAK, 1) { - /* DBGO("\\_WAK\n") */ - /* DBGO("From S") */ - /* DBGO(Arg0) */ - /* DBGO(" to S0\n") */ - - /* Re-enable HPET */ - Store(1,HPDE) - - /* Restore PCIRST# so it resets USB */ - if (LEqual(Arg0,3)){ - Store(1,URRE) - } - - /* Arbitrarily clear PciExpWakeStatus */ - Store(PWST, Local1) - Store(Local1, PWST) - - /* if (DeRefOf(Index(WKST,0))) { - * Store(0, Index(WKST,1)) - * } else { - * Store(Arg0, Index(WKST,1)) - * } - */ - \_SB.PCI0.SIOW () - Return(WKST) - } /* End Method(\_WAK) */ - - Scope(\_GPE) { /* Start Scope GPE */ - /* General event 0 */ - /* Method(_L00) { - * DBGO("\\_GPE\\_L00\n") - * } - */ - - /* General event 1 */ - /* Method(_L01) { - * DBGO("\\_GPE\\_L00\n") - * } - */ - - /* General event 2 */ - /* Method(_L02) { - * DBGO("\\_GPE\\_L00\n") - * } - */ - - /* General event 3 */ - Method(_L03) { - /* DBGO("\\_GPE\\_L00\n") */ - Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ - } - - /* General event 4 */ - /* Method(_L04) { - * DBGO("\\_GPE\\_L00\n") - * } - */ - - /* General event 5 */ - /* Method(_L05) { - * DBGO("\\_GPE\\_L00\n") - * } - */ - - /* General event 6 - Used for GPM6, moved to USB.asl */ - /* Method(_L06) { - * DBGO("\\_GPE\\_L00\n") - * } - */ - - /* General event 7 - Used for GPM7, moved to USB.asl */ - /* Method(_L07) { - * DBGO("\\_GPE\\_L07\n") - * } - */ - - /* Legacy PM event */ - Method(_L08) { - /* DBGO("\\_GPE\\_L08\n") */ - } - - /* Temp warning (TWarn) event */ - Method(_L09) { - /* DBGO("\\_GPE\\_L09\n") */ - Notify (\_TZ.TZ00, 0x80) - } - - /* Reserved */ - /* Method(_L0A) { - * DBGO("\\_GPE\\_L0A\n") - * } - */ - - /* USB controller PME# */ - Method(_L0B) { - /* DBGO("\\_GPE\\_L0B\n") */ - Notify(\_SB.PCI0.UOH1, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(\_SB.PCI0.UOH2, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(\_SB.PCI0.UOH3, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(\_SB.PCI0.UOH4, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(\_SB.PCI0.UOH5, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(\_SB.PCI0.UEH1, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ - } - - /* AC97 controller PME# */ - /* Method(_L0C) { - * DBGO("\\_GPE\\_L0C\n") - * } - */ - - /* OtherTherm PME# */ - /* Method(_L0D) { - * DBGO("\\_GPE\\_L0D\n") - * } - */ - - /* GPM9 SCI event - Moved to USB.asl */ - /* Method(_L0E) { - * DBGO("\\_GPE\\_L0E\n") - * } - */ - - /* PCIe HotPlug event */ - /* Method(_L0F) { - * DBGO("\\_GPE\\_L0F\n") - * } - */ - - /* ExtEvent0 SCI event */ - Method(_L10) { - /* DBGO("\\_GPE\\_L10\n") */ - } - - - /* ExtEvent1 SCI event */ - Method(_L11) { - /* DBGO("\\_GPE\\_L11\n") */ - } - - /* PCIe PME# event */ - /* Method(_L12) { - * DBGO("\\_GPE\\_L12\n") - * } - */ - - /* GPM0 SCI event - Moved to USB.asl */ - /* Method(_L13) { - * DBGO("\\_GPE\\_L13\n") - * } - */ - - /* GPM1 SCI event - Moved to USB.asl */ - /* Method(_L14) { - * DBGO("\\_GPE\\_L14\n") - * } - */ - - /* GPM2 SCI event - Moved to USB.asl */ - /* Method(_L15) { - * DBGO("\\_GPE\\_L15\n") - * } - */ - - /* GPM3 SCI event - Moved to USB.asl */ - /* Method(_L16) { - * DBGO("\\_GPE\\_L16\n") - * } - */ - - /* GPM8 SCI event - Moved to USB.asl */ - /* Method(_L17) { - * DBGO("\\_GPE\\_L17\n") - * } - */ - - /* GPIO0 or GEvent8 event */ - Method(_L18) { - /* DBGO("\\_GPE\\_L18\n") */ - Notify(\_SB.PCI0.PBR2, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(\_SB.PCI0.PBR4, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(\_SB.PCI0.PBR5, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(\_SB.PCI0.PBR6, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(\_SB.PCI0.PBR7, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ - } - - /* GPM4 SCI event - Moved to USB.asl */ - /* Method(_L19) { - * DBGO("\\_GPE\\_L19\n") - * } - */ - - /* GPM5 SCI event - Moved to USB.asl */ - /* Method(_L1A) { - * DBGO("\\_GPE\\_L1A\n") - * } - */ - - /* Azalia SCI event */ - Method(_L1B) { - /* DBGO("\\_GPE\\_L1B\n") */ - Notify(\_SB.PCI0.AZHD, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ - } - - /* GPM6 SCI event - Reassigned to _L06 */ - /* Method(_L1C) { - * DBGO("\\_GPE\\_L1C\n") - * } - */ - - /* GPM7 SCI event - Reassigned to _L07 */ - /* Method(_L1D) { - * DBGO("\\_GPE\\_L1D\n") - * } - */ - - /* GPIO2 or GPIO66 SCI event */ - /* Method(_L1E) { - * DBGO("\\_GPE\\_L1E\n") - * } - */ - - /* SATA SCI event - Moved to sata.asl */ - /* Method(_L1F) { - * DBGO("\\_GPE\\_L1F\n") - * } - */ - - } /* End Scope GPE */ - - #include "acpi/usb.asl" - - /* System Bus */ - Scope(\_SB) { /* Start \_SB scope */ - #include /* global utility methods expected within the \_SB scope */ - - /* _SB.PCI0 */ - /* Note: Only need HID on Primary Bus */ - Device(PCI0) { - External (TOM1) - External (TOM2) /* ( >> 20) to make it fit into 32 bit for XP */ - Name(_HID, EISAID("PNP0A03")) - Name(_ADR, 0x00180000) /* Dev# = BSP Dev#, Func# = 0 */ - Method(_BBN, 0) { /* Bus number = 0 */ - Return(0) - } - Method(_STA, 0) { - /* DBGO("\\_SB\\PCI0\\_STA\n") */ - Return(0x0B) /* Status is visible */ - } - - Method(_PRT,0) { - If(PMOD){ Return(APR0) } /* APIC mode */ - Return (PR0) /* PIC Mode */ - } /* end _PRT */ - - /* Describe the Northbridge devices */ - Device(AMRT) { - Name(_ADR, 0x00000000) - } /* end AMRT */ - - /* The internal GFX bridge */ - Device(AGPB) { - Name(_ADR, 0x00010000) - Name(_PRW, Package() {0x18, 4}) - Method(_PRT,0) { - Return (APR1) - } - } /* end AGPB */ - - /* The external GFX bridge */ - Device(PBR2) { - Name(_ADR, 0x00020000) - Name(_PRW, Package() {0x18, 4}) - Method(_PRT,0) { - If(PMOD){ Return(APS2) } /* APIC mode */ - Return (PS2) /* PIC Mode */ - } /* end _PRT */ - } /* end PBR2 */ - - /* Dev3 is also an external GFX bridge, not used in Herring */ - - Device(PBR4) { - Name(_ADR, 0x00040000) - Name(_PRW, Package() {0x18, 4}) - Method(_PRT,0) { - If(PMOD){ Return(APS4) } /* APIC mode */ - Return (PS4) /* PIC Mode */ - } /* end _PRT */ - } /* end PBR4 */ - - Device(PBR5) { - Name(_ADR, 0x00050000) - Name(_PRW, Package() {0x18, 4}) - Method(_PRT,0) { - If(PMOD){ Return(APS5) } /* APIC mode */ - Return (PS5) /* PIC Mode */ - } /* end _PRT */ - } /* end PBR5 */ - - Device(PBR6) { - Name(_ADR, 0x00060000) - Name(_PRW, Package() {0x18, 4}) - Method(_PRT,0) { - If(PMOD){ Return(APS6) } /* APIC mode */ - Return (PS6) /* PIC Mode */ - } /* end _PRT */ - } /* end PBR6 */ - - /* The onboard EtherNet chip */ - Device(PBR7) { - Name(_ADR, 0x00070000) - Name(_PRW, Package() {0x18, 4}) - Method(_PRT,0) { - If(PMOD){ Return(APS7) } /* APIC mode */ - Return (PS7) /* PIC Mode */ - } /* end _PRT */ - } /* end PBR7 */ - - /* GPP */ - Device(PBR9) { - Name(_ADR, 0x00090000) - Name(_PRW, Package() {0x18, 4}) - Method(_PRT,0) { - If(PMOD){ Return(APS9) } /* APIC mode */ - Return (PS9) /* PIC Mode */ - } /* end _PRT */ - } /* end PBR9 */ - - Device(PBRa) { - Name(_ADR, 0x000A0000) - Name(_PRW, Package() {0x18, 4}) - Method(_PRT,0) { - If(PMOD){ Return(APSa) } /* APIC mode */ - Return (PSa) /* PIC Mode */ - } /* end _PRT */ - } /* end PBRa */ - - - /* PCI slot 1, 2, 3 */ - Device(PIBR) { - Name(_ADR, 0x00140004) - Name(_PRW, Package() {0x18, 4}) - - Method(_PRT, 0) { - Return (PCIB) - } - } - - /* Describe the Southbridge devices */ - Device(STCR) { - Name(_ADR, 0x00110000) - #include "acpi/sata.asl" - } /* end STCR */ - - Device(UOH1) { - Name(_ADR, 0x00130000) - Name(_PRW, Package() {0x0B, 3}) - } /* end UOH1 */ - - Device(UOH2) { - Name(_ADR, 0x00130001) - Name(_PRW, Package() {0x0B, 3}) - } /* end UOH2 */ - - Device(UOH3) { - Name(_ADR, 0x00130002) - Name(_PRW, Package() {0x0B, 3}) - } /* end UOH3 */ - - Device(UOH4) { - Name(_ADR, 0x00130003) - Name(_PRW, Package() {0x0B, 3}) - } /* end UOH4 */ - - Device(UOH5) { - Name(_ADR, 0x00130004) - Name(_PRW, Package() {0x0B, 3}) - } /* end UOH5 */ - - Device(UEH1) { - Name(_ADR, 0x00130005) - Name(_PRW, Package() {0x0B, 3}) - } /* end UEH1 */ - - Device(SBUS) { - Name(_ADR, 0x00140000) - } /* end SBUS */ - - /* Primary (and only) IDE channel */ - Device(IDEC) { - Name(_ADR, 0x00140001) - #include "acpi/ide.asl" - } /* end IDEC */ - - Device(AZHD) { - Name(_ADR, 0x00140002) - OperationRegion(AZPD, PCI_Config, 0x00, 0x100) - Field(AZPD, AnyAcc, NoLock, Preserve) { - offset (0x42), - NSDI, 1, - NSDO, 1, - NSEN, 1, - offset (0x44), - IPCR, 4, - offset (0x54), - PWST, 2, - , 6, - PMEB, 1, - , 6, - PMST, 1, - offset (0x62), - MMCR, 1, - offset (0x64), - MMLA, 32, - offset (0x68), - MMHA, 32, - offset (0x6C), - MMDT, 16, - } - - Method(_INI) { - If(LEqual(OSVR,3)){ /* If we are running Linux */ - Store(zero, NSEN) - Store(one, NSDO) - Store(one, NSDI) - } - } - } /* end AZHD */ - - Device(LIBR) { - Name(_ADR, 0x00140003) - /* Method(_INI) { - * DBGO("\\_SB\\PCI0\\LpcIsaBr\\_INI\n") - } */ /* End Method(_SB.SBRDG._INI) */ - - /* Real Time Clock Device */ - Device(RTC0) { - Name(_HID, EISAID("PNP0B00")) /* AT Real Time Clock (not PIIX4 compatible) */ - Name(_CRS, ResourceTemplate() { - IRQNoFlags(){8} - IO(Decode16,0x0070, 0x0070, 0, 2) - /* IO(Decode16,0x0070, 0x0070, 0, 4) */ - }) - } /* End Device(_SB.PCI0.LpcIsaBr.RTC0) */ - - Device(TMR) { /* Timer */ - Name(_HID,EISAID("PNP0100")) /* System Timer */ - Name(_CRS, ResourceTemplate() { - IRQNoFlags(){0} - IO(Decode16, 0x0040, 0x0040, 0, 4) - /* IO(Decode16, 0x0048, 0x0048, 0, 4) */ - }) - } /* End Device(_SB.PCI0.LpcIsaBr.TMR) */ - - Device(SPKR) { /* Speaker */ - Name(_HID,EISAID("PNP0800")) /* AT style speaker */ - Name(_CRS, ResourceTemplate() { - IO(Decode16, 0x0061, 0x0061, 0, 1) - }) - } /* End Device(_SB.PCI0.LpcIsaBr.SPKR) */ - - Device(PIC) { - Name(_HID,EISAID("PNP0000")) /* AT Interrupt Controller */ - Name(_CRS, ResourceTemplate() { - IRQNoFlags(){2} - IO(Decode16,0x0020, 0x0020, 0, 2) - IO(Decode16,0x00A0, 0x00A0, 0, 2) - /* IO(Decode16, 0x00D0, 0x00D0, 0x10, 0x02) */ - /* IO(Decode16, 0x04D0, 0x04D0, 0x10, 0x02) */ - }) - } /* End Device(_SB.PCI0.LpcIsaBr.PIC) */ - - Device(MAD) { /* 8257 DMA */ - Name(_HID,EISAID("PNP0200")) /* Hardware Device ID */ - Name(_CRS, ResourceTemplate() { - DMA(Compatibility,BusMaster,Transfer8){4} - IO(Decode16, 0x0000, 0x0000, 0x10, 0x10) - IO(Decode16, 0x0081, 0x0081, 0x01, 0x03) - IO(Decode16, 0x0087, 0x0087, 0x01, 0x01) - IO(Decode16, 0x0089, 0x0089, 0x01, 0x03) - IO(Decode16, 0x008F, 0x008F, 0x01, 0x01) - IO(Decode16, 0x00C0, 0x00C0, 0x10, 0x20) - }) /* End Name(_SB.PCI0.LpcIsaBr.MAD._CRS) */ - } /* End Device(_SB.PCI0.LpcIsaBr.MAD) */ - - Device(COPR) { - Name(_HID,EISAID("PNP0C04")) /* Math Coprocessor */ - Name(_CRS, ResourceTemplate() { - IO(Decode16, 0x00F0, 0x00F0, 0, 0x10) - IRQNoFlags(){13} - }) - } /* End Device(_SB.PCI0.LpcIsaBr.COPR) */ - - Device(HPTM) { - Name(_HID,EISAID("PNP0103")) - Name(CRS,ResourceTemplate() { - Memory32Fixed(ReadOnly,0xFED00000, 0x00000400, HPT) /* 1kb reserved space */ - }) - Method(_STA, 0) { - Return(0x0F) /* sata is visible */ - } - Method(_CRS, 0) { - CreateDwordField(CRS, ^HPT._BAS, HPBX) - Store(HPBA, HPBX) - Return(CRS) - } - } /* End Device(_SB.PCI0.LpcIsaBr.COPR) */ - } /* end LIBR */ - - Device(HPBR) { - Name(_ADR, 0x00140004) - } /* end HostPciBr */ - - Device(ACAD) { - Name(_ADR, 0x00140005) - } /* end Ac97audio */ - - Device(ACMD) { - Name(_ADR, 0x00140006) - } /* end Ac97modem */ - - /* ITE8718 Support */ - OperationRegion (IOID, SystemIO, 0x2E, 0x02) /* sometimes it is 0x4E */ - Field (IOID, ByteAcc, NoLock, Preserve) - { - SIOI, 8, SIOD, 8 /* 0x2E and 0x2F */ - } - - IndexField (SIOI, SIOD, ByteAcc, NoLock, Preserve) - { - Offset (0x07), - LDN, 8, /* Logical Device Number */ - Offset (0x20), - CID1, 8, /* Chip ID Byte 1, 0x87 */ - CID2, 8, /* Chip ID Byte 2, 0x12 */ - Offset (0x30), - ACTR, 8, /* Function activate */ - Offset (0xF0), - APC0, 8, /* APC/PME Event Enable Register */ - APC1, 8, /* APC/PME Status Register */ - APC2, 8, /* APC/PME Control Register 1 */ - APC3, 8, /* Environment Controller Special Configuration Register */ - APC4, 8 /* APC/PME Control Register 2 */ - } - - /* Enter the 8718 MB PnP Mode */ - Method (EPNP) - { - Store(0x87, SIOI) - Store(0x01, SIOI) - Store(0x55, SIOI) - Store(0x55, SIOI) /* 8718 magic number */ - } - /* Exit the 8718 MB PnP Mode */ - Method (XPNP) - { - Store (0x02, SIOI) - Store (0x02, SIOD) - } - /* - * Keyboard PME is routed to SB700 Gevent3. We can wake - * up the system by pressing the key. - */ - Method (SIOS, 1) - { - /* We only enable KBD PME for S5. */ - If (LLess (Arg0, 0x05)) - { - EPNP() - /* DBGO("8718F\n") */ - - Store (0x4, LDN) - Store (One, ACTR) /* Enable EC */ - /* - Store (0x4, LDN) - Store (0x04, APC4) - */ /* falling edge. which mode? Not sure. */ - - Store (0x4, LDN) - Store (0x08, APC1) /* clear PME status, Use 0x18 for mouse & KBD */ - Store (0x4, LDN) - Store (0x08, APC0) /* enable PME, Use 0x18 for mouse & KBD */ - - XPNP() - } - } - Method (SIOW, 0) - { - EPNP() - Store (0x4, LDN) - Store (Zero, APC0) /* disable keyboard PME */ - Store (0x4, LDN) - Store (0xFF, APC1) /* clear keyboard PME status */ - XPNP() - } - - Name(CRES, ResourceTemplate() { - IO(Decode16, 0x0CF8, 0x0CF8, 1, 8) - - WORDIO(ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, - 0x0000, /* address granularity */ - 0x0000, /* range minimum */ - 0x0CF7, /* range maximum */ - 0x0000, /* translation */ - 0x0CF8 /* length */ - ) - - WORDIO(ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, - 0x0000, /* address granularity */ - 0x0D00, /* range minimum */ - 0xFFFF, /* range maximum */ - 0x0000, /* translation */ - 0xF300 /* length */ - ) - - Memory32Fixed(READWRITE, 0, 0xA0000, BSMM) - Memory32Fixed(READONLY, 0x000A0000, 0x00020000, VGAM) /* VGA memory space */ - Memory32Fixed(READONLY, 0x000C0000, 0x00020000, EMM1) /* Assume C0000-E0000 empty */ - Memory32Fixed(READONLY, 0x000E0000, 0x00020000, RDBS) /* BIOS ROM area */ - - /* DRAM Memory from 1MB to TopMem */ - Memory32Fixed(READWRITE, 0x00100000, 0, DMLO) /* 1MB to TopMem */ - - /* BIOS space just below 4GB */ - DWORDMemory( - ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite, - 0x00, /* Granularity */ - 0x00000000, /* Min */ - 0x00000000, /* Max */ - 0x00000000, /* Translation */ - 0x00000001, /* Max-Min, RLEN */ - ,, - PCBM - ) - - /* DRAM memory from 4GB to TopMem2 */ - QWORDMemory(ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite, - 0x00000000, /* Granularity */ - 0x00000000, /* Min */ - 0x00000000, /* Max */ - 0x00000000, /* Translation */ - 0x00000001, /* Max-Min, RLEN */ - ,, - DMHI - ) - - /* BIOS space just below 16EB */ - QWORDMemory(ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite, - 0x00000000, /* Granularity */ - 0x00000000, /* Min */ - 0x00000000, /* Max */ - 0x00000000, /* Translation */ - 0x00000001, /* Max-Min, RLEN */ - ,, - PEBM - ) - - }) /* End Name(_SB.PCI0.CRES) */ - - Method(_CRS, 0) { - /* DBGO("\\_SB\\PCI0\\_CRS\n") */ - - CreateDWordField(CRES, ^EMM1._BAS, EM1B) - CreateDWordField(CRES, ^EMM1._LEN, EM1L) - CreateDWordField(CRES, ^DMLO._BAS, DMLB) - CreateDWordField(CRES, ^DMLO._LEN, DMLL) - CreateDWordField(CRES, ^PCBM._MIN, PBMB) - CreateDWordField(CRES, ^PCBM._LEN, PBML) - - CreateQWordField(CRES, ^DMHI._MIN, DMHB) - CreateQWordField(CRES, ^DMHI._LEN, DMHL) - CreateQWordField(CRES, ^PEBM._MIN, EBMB) - CreateQWordField(CRES, ^PEBM._LEN, EBML) - - If(LGreater(LOMH, 0xC0000)){ - Store(0xC0000, EM1B) /* Hole above C0000 and below E0000 */ - Subtract(LOMH, 0xC0000, EM1L) /* subtract start, assumes allocation from C0000 going up */ - } - - /* Set size of memory from 1MB to TopMem */ - Subtract(TOM1, 0x100000, DMLL) - - /* - * If(LNotEqual(TOM2, 0x00000000)){ - * Store(0x100000000,DMHB) DRAM from 4GB to TopMem2 - * ShiftLeft(TOM2, 20, Local0) - * Subtract(Local0, 0x100000000, DMHL) - * } - */ - - /* If there is no memory above 4GB, put the BIOS just below 4GB */ - If(LEqual(TOM2, 0x00000000)){ - Store(PBAD,PBMB) /* Reserve the "BIOS" space */ - Store(PBLN,PBML) - } - Else { /* Otherwise, put the BIOS just below 16EB */ - ShiftLeft(PBAD,16,EBMB) /* Reserve the "BIOS" space */ - Store(PBLN,EBML) - } - - Return(CRES) /* note to change the Name buffer */ - } /* end of Method(_SB.PCI0._CRS) */ - - /* - * - * FIRST METHOD CALLED UPON BOOT - * - * 1. If debugging, print current OS and ACPI interpreter. - * 2. Get PCI Interrupt routing from ACPI VSM, this - * value is based on user choice in BIOS setup. - */ - Method(_INI, 0) { - /* DBGO("\\_SB\\_INI\n") */ - /* DBGO(" DSDT.ASL code from ") */ - /* DBGO(__DATE__) */ - /* DBGO(" ") */ - /* DBGO(__TIME__) */ - /* DBGO("\n Sleep states supported: ") */ - /* DBGO("\n") */ - /* DBGO(" \\_OS=") */ - /* DBGO(\_OS) */ - /* DBGO("\n \\_REV=") */ - /* DBGO(\_REV) */ - /* DBGO("\n") */ - - /* Determine the OS we're running on */ - OSFL() - - /* On older chips, clear PciExpWakeDisEn */ - /*if (LLessEqual(\SBRI, 0x13)) { - * Store(0,\PWDE) - * } - */ - } /* End Method(_SB._INI) */ - } /* End Device(PCI0) */ - - Device(PWRB) { /* Start Power button device */ - Name(_HID, EISAID("PNP0C0C")) - Name(_UID, 0xAA) - Name(_PRW, Package () {3, 0x04}) /* wake from S1-S4 */ - Name(_STA, 0x0B) /* sata is invisible */ - } - } /* End \_SB scope */ - - Scope(\_SI) { - Method(_SST, 1) { - /* DBGO("\\_SI\\_SST\n") */ - /* DBGO(" New Indicator state: ") */ - /* DBGO(Arg0) */ - /* DBGO("\n") */ - } - } /* End Scope SI */ - - #include - - /* THERMAL */ - Scope(\_TZ) { - Name (KELV, 2732) - Name (THOT, 800) - Name (TCRT, 850) - - ThermalZone(TZ00) { - Method(_AC0,0) { /* Active Cooling 0 (0=highest fan speed) */ - /* DBGO("\\_TZ\\TZ00\\_AC0\n") */ - Return(Add(0, 2730)) - } - Method(_AL0,0) { /* Returns package of cooling device to turn on */ - /* DBGO("\\_TZ\\TZ00\\_AL0\n") */ - Return(Package() {\_TZ.TZ00.FAN0}) - } - Device (FAN0) { - Name(_HID, EISAID("PNP0C0B")) - Name(_PR0, Package() {PFN0}) - } - - PowerResource(PFN0,0,0) { - Method(_STA) { - Store(0xF,Local0) - Return(Local0) - } - Method(_ON) { - /* DBGO("\\_TZ\\TZ00\\FAN0 _ON\n") */ - } - Method(_OFF) { - /* DBGO("\\_TZ\\TZ00\\FAN0 _OFF\n") */ - } - } - - Method(_HOT,0) { /* return hot temp in tenths degree Kelvin */ - /* DBGO("\\_TZ\\TZ00\\_HOT\n") */ - Return (Add (THOT, KELV)) - } - Method(_CRT,0) { /* return critical temp in tenths degree Kelvin */ - /* DBGO("\\_TZ\\TZ00\\_CRT\n") */ - Return (Add (TCRT, KELV)) - } - Method(_TMP,0) { /* return current temp of this zone */ - Store (SMBR (0x07, 0x4C,, 0x00), Local0) - If (LGreater (Local0, 0x10)) { - Store (Local0, Local1) - } - Else { - Add (Local0, THOT, Local0) - Return (Add (400, KELV)) - } - - Store (SMBR (0x07, 0x4C, 0x01), Local0) - /* only the two MSBs in the external temperature low byte are used, resolution 0.25. We ignore it */ - /* Store (SMBR (0x07, 0x4C, 0x10), Local2) */ - If (LGreater (Local0, 0x10)) { - If (LGreater (Local0, Local1)) { - Store (Local0, Local1) - } - - Multiply (Local1, 10, Local1) - Return (Add (Local1, KELV)) - } - Else { - Add (Local0, THOT, Local0) - Return (Add (400 , KELV)) - } - } /* end of _TMP */ - } /* end of TZ00 */ - } -} -/* End of ASL file */ diff --git a/src/mainboard/gigabyte/ma785gm/get_bus_conf.c b/src/mainboard/gigabyte/ma785gm/get_bus_conf.c deleted file mode 100644 index ee2a6caeb9..0000000000 --- a/src/mainboard/gigabyte/ma785gm/get_bus_conf.c +++ /dev/null @@ -1,44 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2010 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include -#include - -#include - -/* Global variables for MB layouts and these will be shared by irqtable mptable -* and acpi_tables busnum is default. -*/ -u32 apicid_sb700; - -void get_bus_conf(void) -{ - u32 apicid_base; - - get_default_pci1234(1); - - sysconf.sbdn = (sysconf.hcdn[0] & 0xff); - - pirq_router_bus = (sysconf.pci1234[0] >> 16) & 0xff; - - /* I/O APICs: APIC ID Version State Address */ - if (CONFIG(LOGICAL_CPUS)) - apicid_base = get_apicid_base(1); - else - apicid_base = CONFIG_MAX_PHYSICAL_CPUS; - apicid_sb700 = apicid_base + 0; -} diff --git a/src/mainboard/gigabyte/ma785gm/irq_tables.c b/src/mainboard/gigabyte/ma785gm/irq_tables.c deleted file mode 100644 index 0f7192514e..0000000000 --- a/src/mainboard/gigabyte/ma785gm/irq_tables.c +++ /dev/null @@ -1,102 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2010 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include -#include -#include - -#include - -static void write_pirq_info(struct irq_info *pirq_info, u8 bus, u8 devfn, - u8 link0, u16 bitmap0, u8 link1, u16 bitmap1, - u8 link2, u16 bitmap2, u8 link3, u16 bitmap3, - u8 slot, u8 rfu) -{ - pirq_info->bus = bus; - pirq_info->devfn = devfn; - pirq_info->irq[0].link = link0; - pirq_info->irq[0].bitmap = bitmap0; - pirq_info->irq[1].link = link1; - pirq_info->irq[1].bitmap = bitmap1; - pirq_info->irq[2].link = link2; - pirq_info->irq[2].bitmap = bitmap2; - pirq_info->irq[3].link = link3; - pirq_info->irq[3].bitmap = bitmap3; - pirq_info->slot = slot; - pirq_info->rfu = rfu; -} - - -unsigned long write_pirq_routing_table(unsigned long addr) -{ - struct irq_routing_table *pirq; - struct irq_info *pirq_info; - u32 slot_num; - u8 *v; - - u8 sum = 0; - int i; - - /* Align the table to be 16 byte aligned. */ - addr += 15; - addr &= ~15; - - /* This table must be between 0xf0000 & 0x100000 */ - printk(BIOS_INFO, "Writing IRQ routing tables to 0x%lx...", addr); - - pirq = (void *)(addr); - v = (u8 *) (addr); - - pirq->signature = PIRQ_SIGNATURE; - pirq->version = PIRQ_VERSION; - - pirq->rtr_bus = pirq_router_bus; - pirq->rtr_devfn = PCI_DEVFN(0x14, 4); - - pirq->exclusive_irqs = 0; - - pirq->rtr_vendor = 0x1002; - pirq->rtr_device = 0x4384; - - pirq->miniport_data = 0; - - memset(pirq->rfu, 0, sizeof(pirq->rfu)); - - pirq_info = (void *)(&pirq->checksum + 1); - slot_num = 0; - - /* pci bridge */ - write_pirq_info(pirq_info, pirq_router_bus, PCI_DEVFN(0x14, 4), - 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, - 0); - pirq_info++; - slot_num++; - - pirq->size = 32 + 16 * slot_num; - - for (i = 0; i < pirq->size; i++) - sum += v[i]; - - sum = pirq->checksum - sum; - if (sum != pirq->checksum) { - pirq->checksum = sum; - } - - printk(BIOS_INFO, "write_pirq_routing_table done.\n"); - - return (unsigned long)pirq_info; -} diff --git a/src/mainboard/gigabyte/ma785gm/mainboard.c b/src/mainboard/gigabyte/ma785gm/mainboard.c deleted file mode 100644 index 1c5c1abc16..0000000000 --- a/src/mainboard/gigabyte/ma785gm/mainboard.c +++ /dev/null @@ -1,139 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 Alec Ari - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include -#include -#include -#include -#include -#include - -void set_pcie_dereset(void) -{ - u8 byte; - u16 word; - struct device *sm_dev; - /* set 0 to bit1 :disable GPM9 as SLP_S2 output */ - /* set 0 to bit2 :disable GPM8 as AZ_RST output */ - byte = pm_ioread(0x8d); - byte &= ~((1 << 1) | (1 << 2)); - pm_iowrite(0x8d, byte); - - /* set the GPM8 and GPM9 output enable and the value to 1 */ - byte = pm_ioread(0x94); - byte &= ~((1 << 2) | (1 << 3)); - byte |= ((1 << 0) | (1 << 1)); - pm_iowrite(0x94, byte); - - /* set the GPIO65 output enable and the value is 1 */ - sm_dev = pcidev_on_root(0x14, 0); - word = pci_read_config16(sm_dev, 0x7e); - word |= (1 << 0); - word &= ~(1 << 4); - pci_write_config16(sm_dev, 0x7e, word); -} - -void set_pcie_reset(void) -{ - u8 byte; - u16 word; - struct device *sm_dev; - - /* set 0 to bit1 :disable GPM9 as SLP_S2 output */ - /* set 0 to bit2 :disable GPM8 as AZ_RST output */ - byte = pm_ioread(0x8d); - byte &= ~((1 << 1) | (1 << 2)); - pm_iowrite(0x8d, byte); - - /* set the GPM8 and GPM9 output enable and the value to 0 */ - byte = pm_ioread(0x94); - byte &= ~((1 << 2) | (1 << 3)); - byte &= ~((1 << 0) | (1 << 1)); - pm_iowrite(0x94, byte); - - /* set the GPIO65 output enable and the value is 0 */ - sm_dev = pcidev_on_root(0x14, 0); - word = pci_read_config16(sm_dev, 0x7e); - word &= ~(1 << 0); - word &= ~(1 << 4); - pci_write_config16(sm_dev, 0x7e, word); -} - -/* - * dev3 does not exist on ma785gm - */ -int is_dev3_present(void) -{ - return 0; -} - -/* - * set gpio40 gfx - */ -static void set_gpio40_gfx(void) -{ - u8 byte; -// u16 word; - u32 dword; - struct device *sm_dev; - /* disable the GPIO40 as CLKREQ2# function */ - byte = pm_ioread(0xd3); - byte &= ~(1 << 7); - pm_iowrite(0xd3, byte); - - /* disable the GPIO40 as CLKREQ3# function */ - byte = pm_ioread(0xd4); - byte &= ~(1 << 0); - pm_iowrite(0xd4, byte); - - /* enable pull up for GPIO68 */ - byte = pm2_ioread(0xf1); - byte &= ~(1 << 4); - pm2_iowrite(0xf1, byte); - - /* access the smbus extended register */ - sm_dev = pcidev_on_root(0x14, 0); - - /* set the gfx to 1x16 lanes */ - printk(BIOS_INFO, "Dev3 is not present. GFX Configuration is One x16 slot\n"); - /* when the gpio40 is configured as GPIO, this will enable the output */ - pci_write_config32(sm_dev, 0xf8, 0x4); - dword = pci_read_config32(sm_dev, 0xfc); - dword &= ~(1 << 10); - - /* When the gpio40 is configured as GPIO, this will represent the output value*/ - /* 1 :enable two x8 , 0 : master slot enable only */ - dword &= ~(1 << 26); - pci_write_config32(sm_dev, 0xfc, dword); -} - -/************************************************* -* enable the dedicated function in ma785gm board. -* This function called early than rs780_enable. -*************************************************/ -static void mainboard_enable(struct device *dev) -{ - printk(BIOS_INFO, "Mainboard MA785GM-US2H Enable. dev=0x%p\n", dev); - - set_pcie_dereset(); - /* get_ide_dma66(); */ - set_gpio40_gfx(); -} - -struct chip_operations mainboard_ops = { - .enable_dev = mainboard_enable, -}; diff --git a/src/mainboard/gigabyte/ma785gm/mptable.c b/src/mainboard/gigabyte/ma785gm/mptable.c deleted file mode 100644 index b04a315bb1..0000000000 --- a/src/mainboard/gigabyte/ma785gm/mptable.c +++ /dev/null @@ -1,101 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2010 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include -#include -#include - -extern u32 apicid_sb700; - -static void *smp_write_config_table(void *v) -{ - struct mp_config_table *mc; - int bus_isa; - - mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); - - mptable_init(mc, LOCAL_APIC_ADDR); - - smp_write_processors(mc); - - mptable_write_buses(mc, NULL, &bus_isa); - - /* I/O APICs: APIC ID Version State Address */ - { - struct device *dev; - u32 dword; - u8 byte; - - dev = - dev_find_slot(pirq_router_bus, - PCI_DEVFN(0x14, 0)); - if (dev) { - dword = pci_read_config32(dev, 0x74) & 0xfffffff0; - smp_write_ioapic(mc, apicid_sb700, - 0x11,(void *) dword); - - /* Initialize interrupt mapping */ - /* aza */ - byte = pci_read_config8(dev, 0x63); - byte &= 0xf8; - byte |= 0; /* 0: INTA, ...., 7: INTH */ - pci_write_config8(dev, 0x63, byte); - - /* SATA */ - dword = pci_read_config32(dev, 0xac); - dword &= ~(7 << 26); - dword |= 6 << 26; /* 0: INTA, ...., 7: INTH */ - /* dword |= 1 << 22; PIC and APIC co exists */ - pci_write_config32(dev, 0xac, dword); - - /* - * 00:12.0: PROG SATA : INT F - * 00:13.0: INTA USB_0 - * 00:13.1: INTB USB_1 - * 00:13.2: INTC USB_2 - * 00:13.3: INTD USB_3 - * 00:13.4: INTC USB_4 - * 00:13.5: INTD USB2 - * 00:14.1: INTA IDE - * 00:14.2: Prog HDA : INT E - * 00:14.5: INTB ACI - * 00:14.6: INTB MCI - */ - } - } - - /* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ -#define IO_LOCAL_INT(type, intr, apicid, pin) \ - smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin)); - - mptable_add_isa_interrupts(mc, bus_isa, apicid_sb700, 0); - - /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ - IO_LOCAL_INT(mp_ExtINT, 0x0, MP_APIC_ALL, 0x0); - IO_LOCAL_INT(mp_NMI, 0x0, MP_APIC_ALL, 0x1); - /* There is no extension information... */ - - /* Compute the checksums */ - return mptable_finalize(mc); -} - -unsigned long write_smp_table(unsigned long addr) -{ - void *v; - v = smp_write_floating_table(addr, 0); - return (unsigned long)smp_write_config_table(v); -} diff --git a/src/mainboard/gigabyte/ma785gm/resourcemap.c b/src/mainboard/gigabyte/ma785gm/resourcemap.c deleted file mode 100644 index 80d2d9d05c..0000000000 --- a/src/mainboard/gigabyte/ma785gm/resourcemap.c +++ /dev/null @@ -1,279 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2010 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - - - -#include -#include - -void setup_mb_resource_map(void) -{ - static const unsigned int register_values[] = { - /* Careful set limit registers before base registers which contain the enables */ - /* DRAM Limit i Registers - * F1:0x44 i = 0 - * F1:0x4C i = 1 - * F1:0x54 i = 2 - * F1:0x5C i = 3 - * F1:0x64 i = 4 - * F1:0x6C i = 5 - * F1:0x74 i = 6 - * F1:0x7C i = 7 - * [ 2: 0] Destination Node ID - * 000 = Node 0 - * 001 = Node 1 - * 010 = Node 2 - * 011 = Node 3 - * 100 = Node 4 - * 101 = Node 5 - * 110 = Node 6 - * 111 = Node 7 - * [ 7: 3] Reserved - * [10: 8] Interleave select - * specifies the values of A[14:12] to use with interleave enable. - * [15:11] Reserved - * [31:16] DRAM Limit Address i Bits 39-24 - * This field defines the upper address bits of a 40 bit address - * that define the end of the DRAM region. - */ -// ADDRMAP_REG(0x44), 0x0000f8f8, 0x00000000, // Don't touch it, we need it for CONFIG_CAR_FAM10 - ADDRMAP_REG(0x4C), 0x0000f8f8, 0x00000001, - ADDRMAP_REG(0x54), 0x0000f8f8, 0x00000002, - ADDRMAP_REG(0x5C), 0x0000f8f8, 0x00000003, - ADDRMAP_REG(0x64), 0x0000f8f8, 0x00000004, - ADDRMAP_REG(0x6C), 0x0000f8f8, 0x00000005, - ADDRMAP_REG(0x74), 0x0000f8f8, 0x00000006, - ADDRMAP_REG(0x7C), 0x0000f8f8, 0x00000007, - /* DRAM Base i Registers - * F1:0x40 i = 0 - * F1:0x48 i = 1 - * F1:0x50 i = 2 - * F1:0x58 i = 3 - * F1:0x60 i = 4 - * F1:0x68 i = 5 - * F1:0x70 i = 6 - * F1:0x78 i = 7 - * [ 0: 0] Read Enable - * 0 = Reads Disabled - * 1 = Reads Enabled - * [ 1: 1] Write Enable - * 0 = Writes Disabled - * 1 = Writes Enabled - * [ 7: 2] Reserved - * [10: 8] Interleave Enable - * 000 = No interleave - * 001 = Interleave on A[12] (2 nodes) - * 010 = reserved - * 011 = Interleave on A[12] and A[14] (4 nodes) - * 100 = reserved - * 101 = reserved - * 110 = reserved - * 111 = Interleve on A[12] and A[13] and A[14] (8 nodes) - * [15:11] Reserved - * [13:16] DRAM Base Address i Bits 39-24 - * This field defines the upper address bits of a 40-bit address - * that define the start of the DRAM region. - */ -// ADDRMAP_REG(0x40), 0x0000f8fc, 0x00000000,// don't touch it, we need it for CONFIG_CAR_FAM10 - ADDRMAP_REG(0x48), 0x0000f8fc, 0x00000000, - ADDRMAP_REG(0x50), 0x0000f8fc, 0x00000000, - ADDRMAP_REG(0x58), 0x0000f8fc, 0x00000000, - ADDRMAP_REG(0x60), 0x0000f8fc, 0x00000000, - ADDRMAP_REG(0x68), 0x0000f8fc, 0x00000000, - ADDRMAP_REG(0x70), 0x0000f8fc, 0x00000000, - ADDRMAP_REG(0x78), 0x0000f8fc, 0x00000000, - - /* Memory-Mapped I/O Limit i Registers - * F1:0x84 i = 0 - * F1:0x8C i = 1 - * F1:0x94 i = 2 - * F1:0x9C i = 3 - * F1:0xA4 i = 4 - * F1:0xAC i = 5 - * F1:0xB4 i = 6 - * F1:0xBC i = 7 - * [ 2: 0] Destination Node ID - * 000 = Node 0 - * 001 = Node 1 - * 010 = Node 2 - * 011 = Node 3 - * 100 = Node 4 - * 101 = Node 5 - * 110 = Node 6 - * 111 = Node 7 - * [ 3: 3] Reserved - * [ 5: 4] Destination Link ID - * 00 = Link 0 - * 01 = Link 1 - * 10 = Link 2 - * 11 = Reserved - * [ 6: 6] Reserved - * [ 7: 7] Non-Posted - * 0 = CPU writes may be posted - * 1 = CPU writes must be non-posted - * [31: 8] Memory-Mapped I/O Limit Address i (39-16) - * This field defines the upp address bits of a 40-bit address that - * defines the end of a memory-mapped I/O region n - */ - ADDRMAP_REG(0x84), 0x00000048, 0x00000000, - ADDRMAP_REG(0x8C), 0x00000048, 0x00000000, - ADDRMAP_REG(0x94), 0x00000048, 0x00000000, - ADDRMAP_REG(0x9C), 0x00000048, 0x00000000, - ADDRMAP_REG(0xA4), 0x00000048, 0x00000000, - ADDRMAP_REG(0xAC), 0x00000048, 0x00000000, - ADDRMAP_REG(0xB4), 0x00000048, 0x00000000, -// ADDRMAP_REG(0xBC), 0x00000048, 0x00ffff00, - - /* Memory-Mapped I/O Base i Registers - * F1:0x80 i = 0 - * F1:0x88 i = 1 - * F1:0x90 i = 2 - * F1:0x98 i = 3 - * F1:0xA0 i = 4 - * F1:0xA8 i = 5 - * F1:0xB0 i = 6 - * F1:0xB8 i = 7 - * [ 0: 0] Read Enable - * 0 = Reads disabled - * 1 = Reads Enabled - * [ 1: 1] Write Enable - * 0 = Writes disabled - * 1 = Writes Enabled - * [ 2: 2] Cpu Disable - * 0 = Cpu can use this I/O range - * 1 = Cpu requests do not use this I/O range - * [ 3: 3] Lock - * 0 = base/limit registers i are read/write - * 1 = base/limit registers i are read-only - * [ 7: 4] Reserved - * [31: 8] Memory-Mapped I/O Base Address i (39-16) - * This field defines the upper address bits of a 40bit address - * that defines the start of memory-mapped I/O region i - */ - ADDRMAP_REG(0x80), 0x000000f0, 0x00000000, - ADDRMAP_REG(0x88), 0x000000f0, 0x00000000, - ADDRMAP_REG(0x90), 0x000000f0, 0x00000000, - ADDRMAP_REG(0x98), 0x000000f0, 0x00000000, - ADDRMAP_REG(0xA0), 0x000000f0, 0x00000000, - ADDRMAP_REG(0xA8), 0x000000f0, 0x00000000, - ADDRMAP_REG(0xB0), 0x000000f0, 0x00000000, -// ADDRMAP_REG(0xB8), 0x000000f0, 0x00fc0003, - - /* PCI I/O Limit i Registers - * F1:0xC4 i = 0 - * F1:0xCC i = 1 - * F1:0xD4 i = 2 - * F1:0xDC i = 3 - * [ 2: 0] Destination Node ID - * 000 = Node 0 - * 001 = Node 1 - * 010 = Node 2 - * 011 = Node 3 - * 100 = Node 4 - * 101 = Node 5 - * 110 = Node 6 - * 111 = Node 7 - * [ 3: 3] Reserved - * [ 5: 4] Destination Link ID - * 00 = Link 0 - * 01 = Link 1 - * 10 = Link 2 - * 11 = reserved - * [11: 6] Reserved - * [24:12] PCI I/O Limit Address i - * This field defines the end of PCI I/O region n - * [31:25] Reserved - */ -// ADDRMAP_REG(0xC4), 0xFE000FC8, 0x01fff000, - ADDRMAP_REG(0xCC), 0xFE000FC8, 0x00000000, - ADDRMAP_REG(0xD4), 0xFE000FC8, 0x00000000, - ADDRMAP_REG(0xDC), 0xFE000FC8, 0x00000000, - - /* PCI I/O Base i Registers - * F1:0xC0 i = 0 - * F1:0xC8 i = 1 - * F1:0xD0 i = 2 - * F1:0xD8 i = 3 - * [ 0: 0] Read Enable - * 0 = Reads Disabled - * 1 = Reads Enabled - * [ 1: 1] Write Enable - * 0 = Writes Disabled - * 1 = Writes Enabled - * [ 3: 2] Reserved - * [ 4: 4] VGA Enable - * 0 = VGA matches Disabled - * 1 = matches all address < 64K and where A[9:0] is in the - * range 3B0-3BB or 3C0-3DF independen of the base & limit registers - * [ 5: 5] ISA Enable - * 0 = ISA matches Disabled - * 1 = Blocks address < 64K and in the last 768 bytes of eack 1K block - * from matching agains this base/limit pair - * [11: 6] Reserved - * [24:12] PCI I/O Base i - * This field defines the start of PCI I/O region n - * [31:25] Reserved - */ -// ADDRMAP_REG(0xC0), 0xFE000FCC, 0x00000003, - ADDRMAP_REG(0xC8), 0xFE000FCC, 0x00000000, - ADDRMAP_REG(0xD0), 0xFE000FCC, 0x00000000, - ADDRMAP_REG(0xD8), 0xFE000FCC, 0x00000000, - - /* Config Base and Limit i Registers - * F1:0xE0 i = 0 - * F1:0xE4 i = 1 - * F1:0xE8 i = 2 - * F1:0xEC i = 3 - * [ 0: 0] Read Enable - * 0 = Reads Disabled - * 1 = Reads Enabled - * [ 1: 1] Write Enable - * 0 = Writes Disabled - * 1 = Writes Enabled - * [ 2: 2] Device Number Compare Enable - * 0 = The ranges are based on bus number - * 1 = The ranges are ranges of devices on bus 0 - * [ 3: 3] Reserved - * [ 6: 4] Destination Node - * 000 = Node 0 - * 001 = Node 1 - * 010 = Node 2 - * 011 = Node 3 - * 100 = Node 4 - * 101 = Node 5 - * 110 = Node 6 - * 111 = Node 7 - * [ 7: 7] Reserved - * [ 9: 8] Destination Link - * 00 = Link 0 - * 01 = Link 1 - * 10 = Link 2 - * 11 - Reserved - * [15:10] Reserved - * [23:16] Bus Number Base i - * This field defines the lowest bus number in configuration region i - * [31:24] Bus Number Limit i - * This field defines the highest bus number in configuration regin i - */ -// ADDRMAP_REG(0xE0), 0x0000FC88, 0x06000003, // AMD 8111 on link0 of CPU 0 - ADDRMAP_REG(0xE4), 0x0000FC88, 0x00000000, - ADDRMAP_REG(0xE8), 0x0000FC88, 0x00000000, - ADDRMAP_REG(0xEC), 0x0000FC88, 0x00000000, - }; - - int max; - max = ARRAY_SIZE(register_values); - setup_resource_map(register_values, max); -} diff --git a/src/mainboard/gigabyte/ma785gm/romstage.c b/src/mainboard/gigabyte/ma785gm/romstage.c deleted file mode 100644 index 0d1f45d7af..0000000000 --- a/src/mainboard/gigabyte/ma785gm/romstage.c +++ /dev/null @@ -1,226 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2010 Wang Qing Pei - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -//#define SYSTEM_TYPE 0 /* SERVER */ -#define SYSTEM_TYPE 1 /* DESKTOP */ -//#define SYSTEM_TYPE 2 /* MOBILE */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include "cpu/amd/quadcore/quadcore.c" - -#define SERIAL_DEV PNP_DEV(0x2e, IT8718F_SP1) -#define GPIO_DEV PNP_DEV(0x2e, IT8718F_GPIO) - -int spd_read_byte(unsigned int device, unsigned int address); - - -int spd_read_byte(u32 device, u32 address) -{ - return do_smbus_read_byte(SMBUS_IO_BASE, device, address); -} - -void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) -{ - struct sys_info *sysinfo = get_sysinfo(); - static const u8 spd_addr[] = {RC00, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, }; - u32 bsp_apicid = 0, val; - msr_t msr; - - timestamp_init(timestamp_get()); - timestamp_add_now(TS_START_ROMSTAGE); - - if (!cpu_init_detectedx && boot_cpu()) { - /* Nothing special needs to be done to find bus 0 */ - /* Allow the HT devices to be found */ - /* mov bsp to bus 0xff when > 8 nodes */ - set_bsp_node_CHtExtNodeCfgEn(); - enumerate_ht_chain(); - sb7xx_51xx_pci_port80(); - } - - post_code(0x30); - - if (bist == 0) { - bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo); /* mmconf is inited in init_cpus */ - /* All cores run this but the BSP(node0,core0) is the only core that returns. */ - } - - post_code(0x32); - - enable_rs780_dev8(); - sb7xx_51xx_lpc_init(); - - ite_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); - it8718f_disable_reboot(GPIO_DEV); - console_init(); - - /* Halt if there was a built in self test failure */ - report_bist_failure(bist); - - // Load MPB - val = cpuid_eax(1); - printk(BIOS_DEBUG, "BSP Family_Model: %08x\n", val); - printk(BIOS_DEBUG, "*sysinfo range: [%p,%p]\n",sysinfo,sysinfo+1); - printk(BIOS_DEBUG, "bsp_apicid = %02x\n", bsp_apicid); - printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx); - - /* Setup sysinfo defaults */ - set_sysinfo_in_ram(0); - - update_microcode(val); - - post_code(0x33); - - cpuSetAMDMSR(0); - post_code(0x34); - - amd_ht_init(sysinfo); - post_code(0x35); - - /* Setup nodes PCI space and start core 0 AP init. */ - finalize_node_setup(sysinfo); - - /* Setup any mainboard PCI settings etc. */ - setup_mb_resource_map(); - post_code(0x36); - - /* wait for all the APs core0 started by finalize_node_setup. */ - /* FIXME: A bunch of cores are going to start output to serial at once. - It would be nice to fixup prink spinlocks for ROM XIP mode. - I think it could be done by putting the spinlock flag in the cache - of the BSP located right after sysinfo. - */ - wait_all_core0_started(); - -#if CONFIG(LOGICAL_CPUS) - /* Core0 on each node is configured. Now setup any additional cores. */ - printk(BIOS_DEBUG, "start_other_cores()\n"); - start_other_cores(bsp_apicid); - post_code(0x37); - wait_all_other_cores_started(bsp_apicid); -#endif - - post_code(0x38); - - /* run _early_setup before soft-reset. */ - rs780_early_setup(); - sb7xx_51xx_early_setup(); - -#if CONFIG(SET_FIDVID) - msr = rdmsr(MSR_COFVID_STS); - printk(BIOS_DEBUG, "\nBegin FIDVID MSR 0xc0010071 0x%08x 0x%08x\n", msr.hi, msr.lo); - - /* FIXME: The sb fid change may survive the warm reset and only - need to be done once.*/ - enable_fid_change_on_sb(sysinfo->sbbusn, sysinfo->sbdn); - - post_code(0x39); - - if (!warm_reset_detect(0)) { // BSP is node 0 - init_fidvid_bsp(bsp_apicid, sysinfo->nodes); - } else { - init_fidvid_stage2(bsp_apicid, 0); // BSP is node 0 - } - - post_code(0x3A); - - /* show final fid and vid */ - msr = rdmsr(MSR_COFVID_STS); - printk(BIOS_DEBUG, "End FIDVIDMSR 0xc0010071 0x%08x 0x%08x\n", msr.hi, msr.lo); -#endif - - rs780_htinit(); - - /* Reset for HT, FIDVID, PLL and errata changes to take affect. */ - if (!warm_reset_detect(0)) { - printk(BIOS_INFO, "...WARM RESET...\n\n\n"); - soft_reset(); - die("After soft_reset - shouldn't see this message!!!\n"); - } - - post_code(0x3B); - - /* It's the time to set ctrl in sysinfo now; */ - printk(BIOS_DEBUG, "fill_mem_ctrl()\n"); - fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr); - - post_code(0x40); - - raminit_amdmct(sysinfo); - - cbmem_initialize_empty(); - post_code(0x41); - - amdmct_cbmem_store_info(sysinfo); - - sb7xx_51xx_before_pci_init(); - - post_code(0x42); -} - -/** - * BOOL AMD_CB_ManualBUIDSwapList(u8 Node, u8 Link, u8 **List) - * Description: - * This routine is called every time a non-coherent chain is processed. - * BUID assignment may be controlled explicitly on a non-coherent chain. Provide a - * swap list. The first part of the list controls the BUID assignment and the - * second part of the list provides the device to device linking. Device orientation - * can be detected automatically, or explicitly. See documentation for more details. - * - * Automatic non-coherent init assigns BUIDs starting at 1 and incrementing sequentially - * based on each device's unit count. - * - * Parameters: - * @param[in] node = The node on which this chain is located - * @param[in] link = The link on the host for this chain - * @param[out] List = supply a pointer to a list - */ -BOOL AMD_CB_ManualBUIDSwapList (u8 node, u8 link, const u8 **List) -{ - static const u8 swaplist[] = { 0xFF, CONFIG_HT_CHAIN_UNITID_BASE, CONFIG_HT_CHAIN_END_UNITID_BASE, 0xFF }; - /* If the BUID was adjusted in early_ht we need to do the manual override */ - if ((CONFIG_HT_CHAIN_UNITID_BASE != 0) && (CONFIG_HT_CHAIN_END_UNITID_BASE != 0)) { - printk(BIOS_DEBUG, "AMD_CB_ManualBUIDSwapList()\n"); - if ((node == 0) && (link == 0)) { /* BSP SB link */ - *List = swaplist; - return 1; - } - } - - return 0; -} diff --git a/src/mainboard/gigabyte/ma785gmt/Kconfig b/src/mainboard/gigabyte/ma785gmt/Kconfig deleted file mode 100644 index 39192107ff..0000000000 --- a/src/mainboard/gigabyte/ma785gmt/Kconfig +++ /dev/null @@ -1,54 +0,0 @@ -if BOARD_GIGABYTE_MA785GMT - -config BOARD_SPECIFIC_OPTIONS - def_bool y - select CPU_AMD_SOCKET_AM3 - select DIMM_DDR3 - select DIMM_REGISTERED - select NORTHBRIDGE_AMD_AMDFAM10 - select SOUTHBRIDGE_AMD_RS780 - select SOUTHBRIDGE_AMD_SB700 - select SUPERIO_ITE_IT8718F - select HAVE_OPTION_TABLE - select HAVE_PIRQ_TABLE - select HAVE_MP_TABLE - select SB_HT_CHAIN_UNITID_OFFSET_ONLY - select LIFT_BSP_APIC_ID - select HAVE_ACPI_TABLES - select BOARD_ROMSIZE_KB_1024 - select ENABLE_APIC_EXT_ID - select GFXUMA - -config MAINBOARD_DIR - string - default gigabyte/ma785gmt - -config APIC_ID_OFFSET - hex - default 0x0 - -config MAINBOARD_PART_NUMBER - string - default "GA-MA785GMT-UD2H" - -config MAX_CPUS - int - default 8 - -config MAX_PHYSICAL_CPUS - int - default 2 - -config HT_CHAIN_END_UNITID_BASE - hex - default 0x1 - -config HT_CHAIN_UNITID_BASE - hex - default 0x0 - -config IRQ_SLOT_COUNT - int - default 11 - -endif # BOARD_GIGABYTE_MA785GMT diff --git a/src/mainboard/gigabyte/ma785gmt/Kconfig.name b/src/mainboard/gigabyte/ma785gmt/Kconfig.name deleted file mode 100644 index 4700e2d5a4..0000000000 --- a/src/mainboard/gigabyte/ma785gmt/Kconfig.name +++ /dev/null @@ -1,2 +0,0 @@ -config BOARD_GIGABYTE_MA785GMT - bool "GA-MA785GMT-UD2H" diff --git a/src/mainboard/gigabyte/ma785gmt/Makefile.inc b/src/mainboard/gigabyte/ma785gmt/Makefile.inc deleted file mode 100644 index 91d4b39c32..0000000000 --- a/src/mainboard/gigabyte/ma785gmt/Makefile.inc +++ /dev/null @@ -1,16 +0,0 @@ -# -# This file is part of the coreboot project. -# -# This program is free software; you can redistribute it and/or modify -# it under the terms of the GNU General Public License as published by -# the Free Software Foundation; version 2 of the License. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# - -romstage-y += resourcemap.c - -ramstage-y += get_bus_conf.c diff --git a/src/mainboard/gigabyte/ma785gmt/acpi/cpstate.asl b/src/mainboard/gigabyte/ma785gmt/acpi/cpstate.asl deleted file mode 100644 index af0092ae73..0000000000 --- a/src/mainboard/gigabyte/ma785gmt/acpi/cpstate.asl +++ /dev/null @@ -1,80 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2010 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -/* This file defines the processor and performance state capability - * for each core in the system. It is included into the DSDT for each - * core. It assumes that each core of the system has the same performance - * charateristics. -*/ -/* -#include -DefinitionBlock ("DSDT.AML", "DSDT", 0x01, OEM_ID, ACPI_TABLE_CREATOR, 0x00010001) - { - Scope (\_PR) { - Device (CPU0) { - Name (_HID, "ACPI0007") - Name (_UID, 0) - #include "cpstate.asl" - } - Device (CPU1) { - Name (_HID, "ACPI0007") - Name (_UID, 1) - #include "cpstate.asl" - } - Device (CPU2) { - Name (_HID, "ACPI0007") - Name (_UID, 2) - #include "cpstate.asl" - } - Device (CPU3) { - Name (_HID, "ACPI0007") - Name (_UID, 3) - #include "cpstate.asl" - } - } -*/ - /* P-state support: The maximum number of P-states supported by the */ - /* CPUs we'll use is 6. */ - /* Get from AMI BIOS. */ - Name(_PSS, Package(){ - Package () - { - 0x00000AF0, - 0x0000BF81, - 0x00000002, - 0x00000002, - 0x00000000, - 0x00000000 - }, - - Package () - { - 0x00000578, - 0x000076F2, - 0x00000002, - 0x00000002, - 0x00000001, - 0x00000001 - } - }) - - Name(_PCT, Package(){ - ResourceTemplate(){Register(FFixedHW, 0, 0, 0)}, - ResourceTemplate(){Register(FFixedHW, 0, 0, 0)} - }) - - Method(_PPC, 0){ - Return(0) - } diff --git a/src/mainboard/gigabyte/ma785gmt/acpi/ide.asl b/src/mainboard/gigabyte/ma785gmt/acpi/ide.asl deleted file mode 100644 index 5c155cf301..0000000000 --- a/src/mainboard/gigabyte/ma785gmt/acpi/ide.asl +++ /dev/null @@ -1,240 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2010 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -/* -Scope (_SB) { - Device(PCI0) { - Device(IDEC) { - Name(_ADR, 0x00140001) - #include "ide.asl" - } - } -} -*/ - -/* Some timing tables */ -Name(UDTT, Package(){ /* Udma timing table */ - 120, 90, 60, 45, 30, 20, 15, 0 /* UDMA modes 0 -> 6 */ -}) - -Name(MDTT, Package(){ /* MWDma timing table */ - 480, 150, 120, 0 /* Legacy DMA modes 0 -> 2 */ -}) - -Name(POTT, Package(){ /* Pio timing table */ - 600, 390, 270, 180, 120, 0 /* PIO modes 0 -> 4 */ -}) - -/* Some timing register value tables */ -Name(MDRT, Package(){ /* MWDma timing register table */ - 0x77, 0x21, 0x20, 0xFF /* Legacy DMA modes 0 -> 2 */ -}) - -Name(PORT, Package(){ - 0x99, 0x47, 0x34, 0x22, 0x20, 0x99 /* PIO modes 0 -> 4 */ -}) - -OperationRegion(ICRG, PCI_Config, 0x40, 0x20) /* ide control registers */ - Field(ICRG, AnyAcc, NoLock, Preserve) -{ - PPTS, 8, /* Primary PIO Slave Timing */ - PPTM, 8, /* Primary PIO Master Timing */ - OFFSET(0x04), PMTS, 8, /* Primary MWDMA Slave Timing */ - PMTM, 8, /* Primary MWDMA Master Timing */ - OFFSET(0x08), PPCR, 8, /* Primary PIO Control */ - OFFSET(0x0A), PPMM, 4, /* Primary PIO master Mode */ - PPSM, 4, /* Primary PIO slave Mode */ - OFFSET(0x14), PDCR, 2, /* Primary UDMA Control */ - OFFSET(0x16), PDMM, 4, /* Primary UltraDMA Mode */ - PDSM, 4, /* Primary UltraDMA Mode */ -} - -Method(GTTM, 1) /* get total time*/ -{ - Store(And(Arg0, 0x0F), Local0) /* Recovery Width */ - Increment(Local0) - Store(ShiftRight(Arg0, 4), Local1) /* Command Width */ - Increment(Local1) - Return(Multiply(30, Add(Local0, Local1))) -} - -Device(PRID) -{ - Name (_ADR, Zero) - Method(_GTM, 0) - { - NAME(OTBF, Buffer(20) { /* out buffer */ - 0xFF, 0xFF, 0xFF, 0xFF, - 0xFF, 0xFF, 0xFF, 0xFF, - 0xFF, 0xFF, 0xFF, 0xFF, - 0xFF, 0xFF, 0xFF, 0xFF, 0x00, 0x00, 0x00, 0x00 - }) - - CreateDwordField(OTBF, 0, PSD0) /* PIO spd0 */ - CreateDwordField(OTBF, 4, DSD0) /* DMA spd0 */ - CreateDwordField(OTBF, 8, PSD1) /* PIO spd1 */ - CreateDwordField(OTBF, 12, DSD1) /* DMA spd1 */ - CreateDwordField(OTBF, 16, BFFG) /* buffer flags */ - - /* Just return if the channel is disabled */ - If(And(PPCR, 0x01)) { /* primary PIO control */ - Return(OTBF) - } - - /* Always tell them independent timing available and IOChannelReady used on both drives */ - Or(BFFG, 0x1A, BFFG) - - Store(GTTM(PPTM), PSD0) /* save total time of primary PIO master timming to PIO spd0 */ - Store(GTTM(PPTS), PSD1) /* save total time of primary PIO slave Timing to PIO spd1 */ - - If(And(PDCR, 0x01)) { /* It's under UDMA mode */ - Or(BFFG, 0x01, BFFG) - Store(DerefOf(Index(UDTT, PDMM)), DSD0) - } - Else { - Store(GTTM(PMTM), DSD0) /* Primary MWDMA Master Timing, DmaSpd0 */ - } - - If(And(PDCR, 0x02)) { /* It's under UDMA mode */ - Or(BFFG, 0x04, BFFG) - Store(DerefOf(Index(UDTT, PDSM)), DSD1) - } - Else { - Store(GTTM(PMTS), DSD1) /* Primary MWDMA Slave Timing, DmaSpd0 */ - } - - Return(OTBF) /* out buffer */ - } /* End Method(_GTM) */ - - Method(_STM, 3, NotSerialized) - { - NAME(INBF, Buffer(20) { /* in buffer */ - 0xFF, 0xFF, 0xFF, 0xFF, - 0xFF, 0xFF, 0xFF, 0xFF, - 0xFF, 0xFF, 0xFF, 0xFF, - 0xFF, 0xFF, 0xFF, 0xFF, 0x00, 0x00, 0x00, 0x00 - }) - - CreateDwordField(INBF, 0, PSD0) /* PIO spd0 */ - CreateDwordField(INBF, 4, DSD0) /* PIO spd0 */ - CreateDwordField(INBF, 8, PSD1) /* PIO spd1 */ - CreateDwordField(INBF, 12, DSD1) /* DMA spd1 */ - CreateDwordField(INBF, 16, BFFG) /*buffer flag */ - - Store(Match(POTT, MLE, PSD0, MTR, 0, 0), Local0) - Divide(Local0, 5, PPMM,) /* Primary PIO master Mode */ - Store(Match(POTT, MLE, PSD1, MTR, 0, 0), Local1) - Divide(Local1, 5, PPSM,) /* Primary PIO slave Mode */ - - Store(DerefOf(Index(PORT, Local0)), PPTM) /* Primary PIO Master Timing */ - Store(DerefOf(Index(PORT, Local1)), PPTS) /* Primary PIO Slave Timing */ - - If(And(BFFG, 0x01)) { /* Drive 0 is under UDMA mode */ - Store(Match(UDTT, MLE, DSD0, MTR, 0, 0), Local0) - Divide(Local0, 7, PDMM,) - Or(PDCR, 0x01, PDCR) - } - Else { - If(LNotEqual(DSD0, 0xFFFFFFFF)) { - Store(Match(MDTT, MLE, DSD0, MTR, 0, 0), Local0) - Store(DerefOf(Index(MDRT, Local0)), PMTM) - } - } - - If(And(BFFG, 0x04)) { /* Drive 1 is under UDMA mode */ - Store(Match(UDTT, MLE, DSD1, MTR, 0, 0), Local0) - Divide(Local0, 7, PDSM,) - Or(PDCR, 0x02, PDCR) - } - Else { - If(LNotEqual(DSD1, 0xFFFFFFFF)) { - Store(Match(MDTT, MLE, DSD1, MTR, 0, 0), Local0) - Store(DerefOf(Index(MDRT, Local0)), PMTS) - } - } - /* Return(INBF) */ - } /*End Method(_STM) */ - Device(MST) - { - Name(_ADR, 0) - Method(_GTF) { - Name(CMBF, Buffer(21) { - 0x03, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xEF, - 0x03, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xEF, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xF5 - }) - CreateByteField(CMBF, 1, POMD) - CreateByteField(CMBF, 8, DMMD) - CreateByteField(CMBF, 5, CMDA) - CreateByteField(CMBF, 12, CMDB) - CreateByteField(CMBF, 19, CMDC) - - Store(0xA0, CMDA) - Store(0xA0, CMDB) - Store(0xA0, CMDC) - - Or(PPMM, 0x08, POMD) - - If(And(PDCR, 0x01)) { - Or(PDMM, 0x40, DMMD) - } - Else { - Store(Match - (MDTT, MLE, GTTM(PMTM), - MTR, 0, 0), Local0) - If(LLess(Local0, 3)) { - Or(0x20, Local0, DMMD) - } - } - Return(CMBF) - } - } /* End Device(MST) */ - - Device(SLAV) - { - Name(_ADR, 1) - Method(_GTF) { - Name(CMBF, Buffer(21) { - 0x03, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xEF, - 0x03, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xEF, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xF5 - }) - CreateByteField(CMBF, 1, POMD) - CreateByteField(CMBF, 8, DMMD) - CreateByteField(CMBF, 5, CMDA) - CreateByteField(CMBF, 12, CMDB) - CreateByteField(CMBF, 19, CMDC) - - Store(0xB0, CMDA) - Store(0xB0, CMDB) - Store(0xB0, CMDC) - - Or(PPSM, 0x08, POMD) - - If(And(PDCR, 0x02)) { - Or(PDSM, 0x40, DMMD) - } - Else { - Store(Match - (MDTT, MLE, GTTM(PMTS), - MTR, 0, 0), Local0) - If(LLess(Local0, 3)) { - Or(0x20, Local0, DMMD) - } - } - Return(CMBF) - } - } /* End Device(SLAV) */ -} diff --git a/src/mainboard/gigabyte/ma785gmt/acpi/routing.asl b/src/mainboard/gigabyte/ma785gmt/acpi/routing.asl deleted file mode 100644 index 072aa2117f..0000000000 --- a/src/mainboard/gigabyte/ma785gmt/acpi/routing.asl +++ /dev/null @@ -1,297 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2010 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -/* -#include -DefinitionBlock ("DSDT.AML", "DSDT", 0x01, OEM_ID, ACPI_TABLE_CREATOR, 0x00010001 - ) - { - #include "routing.asl" - } -*/ - -/* Routing is in System Bus scope */ -Scope(\_SB) { - Name(PR0, Package(){ - /* NB devices */ - /* Bus 0, Dev 0 - RS780 Host Controller */ - /* Bus 0, Dev 1 - PCI Bridge for Internal Graphics */ - /* Bus 0, Dev 2 - PCIe Bridge for x8 PCIe Slot (GFX0) */ - Package(){0x0002FFFF, 0, INTC, 0 }, - Package(){0x0002FFFF, 1, INTD, 0 }, - Package(){0x0002FFFF, 2, INTA, 0 }, - Package(){0x0002FFFF, 3, INTB, 0 }, - /* Bus 0, Dev 3 - PCIe graphics port 1 bridge */ - /* Bus 0, Dev 4 - PCIe Bridge for Express Card Slot */ - Package(){0x0004FFFF, 0, INTA, 0 }, - Package(){0x0004FFFF, 1, INTB, 0 }, - Package(){0x0004FFFF, 2, INTC, 0 }, - Package(){0x0004FFFF, 3, INTD, 0 }, - /* Bus 0, Dev 5 - General purpose PCIe bridge 5 */ - /* Package(){0x0005FFFF, 0, INTB, 0 }, */ - /* Package(){0x0005FFFF, 1, INTC, 0 }, */ - /* Package(){0x0005FFFF, 2, INTD, 0 }, */ - /* Package(){0x0005FFFF, 3, INTA, 0 }, */ - /* Bus 0, Dev 6 - PCIe Bridge for Ethernet Chip */ - Package(){0x0006FFFF, 0, INTC, 0 }, - Package(){0x0006FFFF, 1, INTD, 0 }, - Package(){0x0006FFFF, 2, INTA, 0 }, - Package(){0x0006FFFF, 3, INTB, 0 }, - /* Bus 0, Dev 7 - PCIe Bridge for x1 PCIe Slot */ - Package(){0x0007FFFF, 0, INTD, 0 }, - Package(){0x0007FFFF, 1, INTA, 0 }, - Package(){0x0007FFFF, 2, INTB, 0 }, - Package(){0x0007FFFF, 3, INTC, 0 }, - /* Bus 0, Funct 8 - Southbridge port (normally hidden) */ - - /* SB devices */ - /* Bus 0, Dev 17 - SATA controller #2 */ - /* Bus 0, Dev 18 - SATA controller #1 */ - Package(){0x0011FFFF, 1, INTA, 0 }, - - /* Bus 0, Dev 19 - USB: OHCI, funct 0-4; EHCI, funct 5 */ - Package(){0x0012FFFF, 0, INTA, 0 }, - Package(){0x0012FFFF, 1, INTB, 0 }, - Package(){0x0013FFFF, 0, INTA, 0 }, - Package(){0x0013FFFF, 1, INTB, 0 }, - Package(){0x0014FFFF, 2, INTA, 0 }, - - /* Bus 0, Dev 20 - F0:SMBus/ACPI,F1:IDE;F2:HDAudio;F3:LPC;F4:PCIBridge;F5:AC97 Audio;F6:AC97 Modem */ - Package(){0x0014FFFF, 0, INTA, 0 }, - Package(){0x0014FFFF, 1, INTB, 0 }, - Package(){0x0014FFFF, 2, INTC, 0 }, - Package(){0x0014FFFF, 3, INTD, 0 }, - }) - - Name(APR0, Package(){ - /* NB devices in APIC mode */ - /* Bus 0, Dev 0 - RS780 Host Controller */ - - /* Bus 0, Dev 1 - PCI Bridge for Internal Graphics */ - /* Package(){0x0001FFFF, 0, 0, 18 }, */ - /* Package(){0x0001FFFF, 1, 0, 19 }, */ - - /* Bus 0, Dev 2 - PCIe Bridge for x8 PCIe Slot (GFX0) */ - Package(){0x0002FFFF, 0, 0, 18 }, - /* Package(){0x0002FFFF, 1, 0, 19 }, */ - /* Package(){0x0002FFFF, 2, 0, 16 }, */ - /* Package(){0x0002FFFF, 3, 0, 17 }, */ - - /* Bus 0, Dev 3 - PCIe graphics port 1 bridge */ - Package(){0x0003FFFF, 0, 0, 19 }, - - /* Bus 0, Dev 4 - PCIe Bridge for Express Card Slot */ - Package(){0x0004FFFF, 0, 0, 16 }, - /* Package(){0x0004FFFF, 1, 0, 17 }, */ - /* Package(){0x0004FFFF, 2, 0, 18 }, */ - /* Package(){0x0004FFFF, 3, 0, 19 }, */ - - /* Bus 0, Dev 5 - General purpose PCIe bridge 5 */ - /* Package(){0x0005FFFF, 0, 0, 17 }, */ - /* Package(){0x0005FFFF, 1, 0, 18 }, */ - /* Package(){0x0005FFFF, 2, 0, 19 }, */ - /* Package(){0x0005FFFF, 3, 0, 16 }, */ - - /* Bus 0, Dev 6 - General purpose PCIe bridge 6 */ - /* Package(){0x0006FFFF, 0, 0, 18 }, */ - /* Package(){0x0006FFFF, 1, 0, 19 }, */ - /* Package(){0x0006FFFF, 2, 0, 16 }, */ - /* Package(){0x0006FFFF, 3, 0, 17 }, */ - - /* Bus 0, Dev 7 - PCIe Bridge for network card */ - /* Package(){0x0007FFFF, 0, 0, 19 }, */ - /* Package(){0x0007FFFF, 1, 0, 16 }, */ - /* Package(){0x0007FFFF, 2, 0, 17 }, */ - /* Package(){0x0007FFFF, 3, 0, 18 }, */ - - /* Bus 0, Dev 9 - PCIe Bridge for network card */ - Package(){0x0009FFFF, 0, 0, 17 }, - /* Package(){0x0009FFFF, 1, 0, 16 }, */ - /* Package(){0x0009FFFF, 2, 0, 17 }, */ - /* Package(){0x0009FFFF, 3, 0, 18 }, */ - /* Bus 0, Dev A - PCIe Bridge for network card */ - Package(){0x000AFFFF, 0, 0, 18 }, - /* Package(){0x000AFFFF, 1, 0, 16 }, */ - /* Package(){0x000AFFFF, 2, 0, 17 }, */ - /* Package(){0x000AFFFF, 3, 0, 18 }, */ - /* Bus 0, Funct 8 - Southbridge port (normally hidden) */ - - /* SB devices in APIC mode */ - /* Bus 0, Dev 17 - SATA controller #2 */ - /* Bus 0, Dev 18 - SATA controller #1 */ - Package(){0x0011FFFF, 0, 0, 22 }, - - /* Bus 0, Dev 19 - USB: OHCI, funct 0-4; EHCI, funct 5 */ - Package(){0x0012FFFF, 0, 0, 16 }, - Package(){0x0012FFFF, 1, 0, 17 }, - Package(){0x0013FFFF, 0, 0, 18 }, - Package(){0x0013FFFF, 1, 0, 19 }, - Package(){0x0014FFFF, 0, 0, 16 }, - /* Package(){0x00130004, 2, 0, 18 }, */ - /* Package(){0x00130005, 3, 0, 19 }, */ - - /* Bus 0, Dev 20 - F0:SMBus/ACPI, F1:IDE; F2:HDAudio; F3:LPC; F4:PCIBridge; F5:AC97 Audio; F6:AC97 Modem */ - Package(){0x0014FFFF, 0, 0, 16 }, - Package(){0x0014FFFF, 1, 0, 17 }, - Package(){0x0014FFFF, 2, 0, 18 }, - Package(){0x0014FFFF, 3, 0, 19 }, - /* Package(){0x00140004, 2, 0, 18 }, */ - /* Package(){0x00140004, 3, 0, 19 }, */ - /* Package(){0x00140005, 1, 0, 17 }, */ - /* Package(){0x00140006, 1, 0, 17 }, */ - }) - - Name(PR1, Package(){ - /* Internal graphics - RS780 VGA, Bus1, Dev5 */ - Package(){0x0005FFFF, 0, INTA, 0 }, - Package(){0x0005FFFF, 1, INTB, 0 }, - Package(){0x0005FFFF, 2, INTC, 0 }, - Package(){0x0005FFFF, 3, INTD, 0 }, - }) - - Name(APR1, Package(){ - /* Internal graphics - RS780 VGA, Bus1, Dev5 */ - Package(){0x0005FFFF, 0, 0, 18 }, - Package(){0x0005FFFF, 1, 0, 19 }, - /* Package(){0x0005FFFF, 2, 0, 20 }, */ - /* Package(){0x0005FFFF, 3, 0, 17 }, */ - }) - - Name(PS2, Package(){ - /* The external GFX - Hooked to PCIe slot 2 */ - Package(){0x0000FFFF, 0, INTC, 0 }, - Package(){0x0000FFFF, 1, INTD, 0 }, - Package(){0x0000FFFF, 2, INTA, 0 }, - Package(){0x0000FFFF, 3, INTB, 0 }, - }) - - Name(APS2, Package(){ - /* The external GFX - Hooked to PCIe slot 2 */ - Package(){0x0000FFFF, 0, 0, 18 }, - Package(){0x0000FFFF, 1, 0, 19 }, - Package(){0x0000FFFF, 2, 0, 16 }, - Package(){0x0000FFFF, 3, 0, 17 }, - }) - - Name(PS4, Package(){ - /* PCIe slot - Hooked to PCIe slot 4 */ - Package(){0x0000FFFF, 0, INTA, 0 }, - Package(){0x0000FFFF, 1, INTB, 0 }, - Package(){0x0000FFFF, 2, INTC, 0 }, - Package(){0x0000FFFF, 3, INTD, 0 }, - }) - - Name(APS4, Package(){ - /* PCIe slot - Hooked to PCIe slot 4 */ - Package(){0x0000FFFF, 0, 0, 16 }, - Package(){0x0000FFFF, 1, 0, 17 }, - Package(){0x0000FFFF, 2, 0, 18 }, - Package(){0x0000FFFF, 3, 0, 19 }, - }) - - Name(PS5, Package(){ - /* PCIe slot - Hooked to PCIe slot 5 */ - Package(){0x0000FFFF, 0, INTB, 0 }, - Package(){0x0000FFFF, 1, INTC, 0 }, - Package(){0x0000FFFF, 2, INTD, 0 }, - Package(){0x0000FFFF, 3, INTA, 0 }, - }) - - Name(APS5, Package(){ - /* PCIe slot - Hooked to PCIe slot 5 */ - Package(){0x0000FFFF, 0, 0, 17 }, - Package(){0x0000FFFF, 1, 0, 18 }, - Package(){0x0000FFFF, 2, 0, 19 }, - Package(){0x0000FFFF, 3, 0, 16 }, - }) - - Name(PS6, Package(){ - /* PCIe slot - Hooked to PCIe slot 6 */ - Package(){0x0000FFFF, 0, INTC, 0 }, - Package(){0x0000FFFF, 1, INTD, 0 }, - Package(){0x0000FFFF, 2, INTA, 0 }, - Package(){0x0000FFFF, 3, INTB, 0 }, - }) - - Name(APS6, Package(){ - /* PCIe slot - Hooked to PCIe slot 6 */ - Package(){0x0000FFFF, 0, 0, 18 }, - Package(){0x0000FFFF, 1, 0, 19 }, - Package(){0x0000FFFF, 2, 0, 16 }, - Package(){0x0000FFFF, 3, 0, 17 }, - }) - - Name(PS7, Package(){ - /* The onboard Ethernet chip - Hooked to PCIe slot 7 */ - Package(){0x0000FFFF, 0, INTD, 0 }, - Package(){0x0000FFFF, 1, INTA, 0 }, - Package(){0x0000FFFF, 2, INTB, 0 }, - Package(){0x0000FFFF, 3, INTC, 0 }, - }) - - Name(APS7, Package(){ - /* The onboard Ethernet chip - Hooked to PCIe slot 7 */ - Package(){0x0000FFFF, 0, 0, 19 }, - Package(){0x0000FFFF, 1, 0, 16 }, - Package(){0x0000FFFF, 2, 0, 17 }, - Package(){0x0000FFFF, 3, 0, 18 }, - }) - Name(PS9, Package(){ - /* PCIe slot - Hooked to PCIe slot 9 */ - Package(){0x0000FFFF, 0, INTD, 0 }, - Package(){0x0000FFFF, 1, INTA, 0 }, - Package(){0x0000FFFF, 2, INTB, 0 }, - Package(){0x0000FFFF, 3, INTC, 0 }, - }) - - Name(APS9, Package(){ - /* PCIe slot - Hooked to PCIe slot 9 */ - Package(){0x0000FFFF, 0, 0, 17 }, - Package(){0x0000FFFF, 1, 0, 18 }, - Package(){0x0000FFFF, 2, 0, 19 }, - Package(){0x0000FFFF, 3, 0, 16 }, - }) - Name(PSa, Package(){ - /* PCIe slot - Hooked to PCIe slot 10 */ - Package(){0x0000FFFF, 0, INTD, 0 }, - Package(){0x0000FFFF, 1, INTA, 0 }, - Package(){0x0000FFFF, 2, INTB, 0 }, - Package(){0x0000FFFF, 3, INTC, 0 }, - }) - - Name(APSa, Package(){ - /* PCIe slot - Hooked to PCIe slot 10 */ - Package(){0x0000FFFF, 0, 0, 18 }, - Package(){0x0000FFFF, 1, 0, 19 }, - Package(){0x0000FFFF, 2, 0, 16 }, - Package(){0x0000FFFF, 3, 0, 17 }, - }) - - Name(PCIB, Package(){ - /* PCI slots: slot 0, slot 1, slot 2 behind Dev14, Fun4. */ - Package(){0x0005FFFF, 0, 0, 0x14 }, - Package(){0x0005FFFF, 1, 0, 0x15 }, - Package(){0x0005FFFF, 2, 0, 0x16 }, - Package(){0x0005FFFF, 3, 0, 0x17 }, - Package(){0x0006FFFF, 0, 0, 0x15 }, - Package(){0x0006FFFF, 1, 0, 0x16 }, - Package(){0x0006FFFF, 2, 0, 0x17 }, - Package(){0x0006FFFF, 3, 0, 0x14 }, - Package(){0x0007FFFF, 0, 0, 0x16 }, - Package(){0x0007FFFF, 1, 0, 0x17 }, - Package(){0x0007FFFF, 2, 0, 0x14 }, - Package(){0x0007FFFF, 3, 0, 0x15 }, - }) -} diff --git a/src/mainboard/gigabyte/ma785gmt/acpi/sata.asl b/src/mainboard/gigabyte/ma785gmt/acpi/sata.asl deleted file mode 100644 index cb9b221ba3..0000000000 --- a/src/mainboard/gigabyte/ma785gmt/acpi/sata.asl +++ /dev/null @@ -1,145 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2010 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -/* simple name description */ - -/* -Scope (_SB) { - Device(PCI0) { - Device(SATA) { - Name(_ADR, 0x00110000) - #include "sata.asl" - } - } -} -*/ - -Name(STTM, Buffer(20) { - 0x78, 0x00, 0x00, 0x00, 0x0f, 0x00, 0x00, 0x00, - 0x78, 0x00, 0x00, 0x00, 0x0f, 0x00, 0x00, 0x00, - 0x1f, 0x00, 0x00, 0x00 -}) - -/* Start by clearing the PhyRdyChg bits */ -Method(_INI) { - \_GPE._L1F() -} - -Device(PMRY) -{ - Name(_ADR, 0) - Method(_GTM, 0x0, NotSerialized) { - Return(STTM) - } - Method(_STM, 0x3, NotSerialized) {} - - Device(PMST) { - Name(_ADR, 0) - Method(_STA,0) { - if (LGreater(P0IS,0)) { - return (0x0F) /* sata is visible */ - } - else { - return (0x00) /* sata is missing */ - } - } - }/* end of PMST */ - - Device(PSLA) - { - Name(_ADR, 1) - Method(_STA,0) { - if (LGreater(P1IS,0)) { - return (0x0F) /* sata is visible */ - } - else { - return (0x00) /* sata is missing */ - } - } - } /* end of PSLA */ -} /* end of PMRY */ - - -Device(SEDY) -{ - Name(_ADR, 1) /* IDE Scondary Channel */ - Method(_GTM, 0x0, NotSerialized) { - Return(STTM) - } - Method(_STM, 0x3, NotSerialized) {} - - Device(SMST) - { - Name(_ADR, 0) - Method(_STA,0) { - if (LGreater(P2IS,0)) { - return (0x0F) /* sata is visible */ - } - else { - return (0x00) /* sata is missing */ - } - } - } /* end of SMST */ - - Device(SSLA) - { - Name(_ADR, 1) - Method(_STA,0) { - if (LGreater(P3IS,0)) { - return (0x0F) /* sata is visible */ - } - else { - return (0x00) /* sata is missing */ - } - } - } /* end of SSLA */ -} /* end of SEDY */ - -/* SATA Hot Plug Support */ -Scope(\_GPE) { - Method(_L1F,0x0,NotSerialized) { - if (\_SB.P0PR) { - if (LGreater(\_SB.P0IS,0)) { - sleep(32) - } - Notify(\_SB.PCI0.STCR.PMRY.PMST, 0x01) /* NOTIFY_DEVICE_CHECK */ - store(one, \_SB.P0PR) - } - - if (\_SB.P1PR) { - if (LGreater(\_SB.P1IS,0)) { - sleep(32) - } - Notify(\_SB.PCI0.STCR.PMRY.PSLA, 0x01) /* NOTIFY_DEVICE_CHECK */ - store(one, \_SB.P1PR) - } - - if (\_SB.P2PR) { - if (LGreater(\_SB.P2IS,0)) { - sleep(32) - } - Notify(\_SB.PCI0.STCR.SEDY.SMST, 0x01) /* NOTIFY_DEVICE_CHECK */ - store(one, \_SB.P2PR) - } - - if (\_SB.P3PR) { - if (LGreater(\_SB.P3IS,0)) { - sleep(32) - } - Notify(\_SB.PCI0.STCR.SEDY.SSLA, 0x01) /* NOTIFY_DEVICE_CHECK */ - store(one, \_SB.P3PR) - } - } -} diff --git a/src/mainboard/gigabyte/ma785gmt/acpi/usb.asl b/src/mainboard/gigabyte/ma785gmt/acpi/usb.asl deleted file mode 100644 index a3ccb97ff9..0000000000 --- a/src/mainboard/gigabyte/ma785gmt/acpi/usb.asl +++ /dev/null @@ -1,158 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2010 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -/* simple name description */ -/* -#include -DefinitionBlock ("DSDT.AML", "DSDT", 0x01, OEM_ID, ACPI_TABLE_CREATOR, 0x00010001 - ) - { - #include "usb.asl" - } -*/ -Method(UCOC, 0) { - Sleep(20) - Store(0x13,CMTI) - Store(0,GPSL) -} - -/* USB Port 0 overcurrent uses Gpm 0 */ -If(LLessEqual(UOM0,9)) { - Scope (\_GPE) { - Method (_L13) { - UCOC() - if(LEqual(GPB0,PLC0)) { - Not(PLC0,PLC0) - Store(PLC0, \_SB.PT0D) - } - } - } -} - -/* USB Port 1 overcurrent uses Gpm 1 */ -If (LLessEqual(UOM1,9)) { - Scope (\_GPE) { - Method (_L14) { - UCOC() - if (LEqual(GPB1,PLC1)) { - Not(PLC1,PLC1) - Store(PLC1, \_SB.PT1D) - } - } - } -} - -/* USB Port 2 overcurrent uses Gpm 2 */ -If (LLessEqual(UOM2,9)) { - Scope (\_GPE) { - Method (_L15) { - UCOC() - if (LEqual(GPB2,PLC2)) { - Not(PLC2,PLC2) - Store(PLC2, \_SB.PT2D) - } - } - } -} - -/* USB Port 3 overcurrent uses Gpm 3 */ -If (LLessEqual(UOM3,9)) { - Scope (\_GPE) { - Method (_L16) { - UCOC() - if (LEqual(GPB3,PLC3)) { - Not(PLC3,PLC3) - Store(PLC3, \_SB.PT3D) - } - } - } -} - -/* USB Port 4 overcurrent uses Gpm 4 */ -If (LLessEqual(UOM4,9)) { - Scope (\_GPE) { - Method (_L19) { - UCOC() - if (LEqual(GPB4,PLC4)) { - Not(PLC4,PLC4) - Store(PLC4, \_SB.PT4D) - } - } - } -} - -/* USB Port 5 overcurrent uses Gpm 5 */ -If (LLessEqual(UOM5,9)) { - Scope (\_GPE) { - Method (_L1A) { - UCOC() - if (LEqual(GPB5,PLC5)) { - Not(PLC5,PLC5) - Store(PLC5, \_SB.PT5D) - } - } - } -} - -/* USB Port 6 overcurrent uses Gpm 6 */ -If (LLessEqual(UOM6,9)) { - Scope (\_GPE) { - /* Method (_L1C) { */ - Method (_L06) { - UCOC() - if (LEqual(GPB6,PLC6)) { - Not(PLC6,PLC6) - Store(PLC6, \_SB.PT6D) - } - } - } -} - -/* USB Port 7 overcurrent uses Gpm 7 */ -If (LLessEqual(UOM7,9)) { - Scope (\_GPE) { - /* Method (_L1D) { */ - Method (_L07) { - UCOC() - if (LEqual(GPB7,PLC7)) { - Not(PLC7,PLC7) - Store(PLC7, \_SB.PT7D) - } - } - } -} - -/* USB Port 8 overcurrent uses Gpm 8 */ -If (LLessEqual(UOM8,9)) { - Scope (\_GPE) { - Method (_L17) { - if (LEqual(G8IS,PLC8)) { - Not(PLC8,PLC8) - Store(PLC8, \_SB.PT8D) - } - } - } -} - -/* USB Port 9 overcurrent uses Gpm 9 */ -If (LLessEqual(UOM9,9)) { - Scope (\_GPE) { - Method (_L0E) { - if (LEqual(G9IS,0)) { - Store(1,\_SB.PT9D) - } - } - } -} diff --git a/src/mainboard/gigabyte/ma785gmt/acpi_tables.c b/src/mainboard/gigabyte/ma785gmt/acpi_tables.c deleted file mode 100644 index 967343da67..0000000000 --- a/src/mainboard/gigabyte/ma785gmt/acpi_tables.c +++ /dev/null @@ -1,44 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2010 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include -#include - -unsigned long acpi_fill_madt(unsigned long current) -{ - /* create all subtables for processors */ - current = acpi_create_madt_lapics(current); - - /* Write SB700 IOAPIC, only one */ - current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, 2, - IO_APIC_ADDR, 0); - - current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) - current, 0, 0, 2, 0); - current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) - current, 0, 9, 9, 0xF); - /* 0: mean bus 0--->ISA */ - /* 0: PIC 0 */ - /* 2: APIC 2 */ - /* 5 mean: 0101 --> Edge-triggered, Active high */ - - /* create all subtables for processors */ - /* current = acpi_create_madt_lapic_nmis(current, 5, 1); */ - /* 1: LINT1 connect to NMI */ - - return current; -} diff --git a/src/mainboard/gigabyte/ma785gmt/board_info.txt b/src/mainboard/gigabyte/ma785gmt/board_info.txt deleted file mode 100644 index abd40af851..0000000000 --- a/src/mainboard/gigabyte/ma785gmt/board_info.txt +++ /dev/null @@ -1,3 +0,0 @@ -Category: desktop -Board URL: http://www.gigabyte.com/products/product-page.aspx?pid=3156#ov -Release year: 2009 diff --git a/src/mainboard/gigabyte/ma785gmt/cmos.layout b/src/mainboard/gigabyte/ma785gmt/cmos.layout deleted file mode 100644 index 6c3d3f6c9e..0000000000 --- a/src/mainboard/gigabyte/ma785gmt/cmos.layout +++ /dev/null @@ -1,52 +0,0 @@ -entries - -0 384 r 0 reserved_memory -384 1 e 4 boot_option -388 4 h 0 reboot_counter -#392 3 r 0 unused -395 1 e 1 hw_scrubber -396 1 e 1 interleave_chip_selects -397 2 e 8 max_mem_clock -399 1 e 2 multi_core -400 1 e 1 power_on_after_fail -412 4 e 6 debug_level -440 4 e 9 slow_cpu -444 1 e 1 nmi -445 1 e 1 gart -456 1 e 1 ECC_memory -728 256 h 0 user_data -984 16 h 0 check_sum -# Reserve the extended AMD configuration registers -1000 24 r 0 amd_reserved - - - -enumerations - -#ID value text -1 0 Disable -1 1 Enable -2 0 Enable -2 1 Disable -4 0 Fallback -4 1 Normal -6 5 Notice -6 6 Info -6 7 Debug -6 8 Spew -8 0 400Mhz -8 1 333Mhz -8 2 266Mhz -8 3 200Mhz -9 0 off -9 1 87.5% -9 2 75.0% -9 3 62.5% -9 4 50.0% -9 5 37.5% -9 6 25.0% -9 7 12.5% - -checksums - -checksum 392 983 984 diff --git a/src/mainboard/gigabyte/ma785gmt/devicetree.cb b/src/mainboard/gigabyte/ma785gmt/devicetree.cb deleted file mode 100644 index a38ebd859d..0000000000 --- a/src/mainboard/gigabyte/ma785gmt/devicetree.cb +++ /dev/null @@ -1,115 +0,0 @@ -# sample config for gigabyte/ma785gmt -chip northbridge/amd/amdfam10/root_complex - device cpu_cluster 0 on - chip cpu/amd/socket_AM3 #L1 and DDR3 - device lapic 0 on end - end - end - device domain 0 on - subsystemid 0x1022 0x3060 inherit - chip northbridge/amd/amdfam10 - device pci 18.0 on # northbridge - chip southbridge/amd/rs780 - device pci 0.0 on end # HT 0x9600 - device pci 1.0 on end # Internal Graphics P2P bridge 0x9602 - device pci 2.0 on end # PCIE P2P bridge (external graphics) 0x9603 - device pci 3.0 on end # PCIE P2P bridge 0x960b - device pci 4.0 on end # PCIE P2P bridge 0x9604 - device pci 5.0 off end # PCIE P2P bridge 0x9605 - device pci 6.0 off end # PCIE P2P bridge 0x9606 - device pci 7.0 off end # PCIE P2P bridge 0x9607 - device pci 8.0 off end # NB/SB Link P2P bridge - device pci 9.0 on end # - device pci a.0 on end # - register "gppsb_configuration" = "1" # Configuration B - register "gpp_configuration" = "3" # Configuration D default - register "port_enable" = "0x6fc" - register "gfx_dev2_dev3" = "1" - register "gfx_dual_slot" = "2" - - register "gfx_lane_reversal" = "0" - register "gfx_tmds" = "0" - register "gfx_compliance" = "0" - register "gfx_reconfiguration" = "1" - register "gfx_link_width" = "0" - end - chip southbridge/amd/sb700 # it is under NB/SB Link, but on the same pri bus - device pci 11.0 on end # SATA - device pci 12.0 on end # USB - device pci 12.1 on end # USB - device pci 12.2 on end # USB - device pci 13.0 on end # USB - device pci 13.1 on end # USB - device pci 13.2 on end # USB - device pci 14.0 on # SM - chip drivers/generic/generic #dimm 0-0-0 - device i2c 50 on end - end - chip drivers/generic/generic #dimm 0-0-1 - device i2c 51 on end - end - chip drivers/generic/generic #dimm 0-1-0 - device i2c 52 on end - end - chip drivers/generic/generic #dimm 0-1-1 - device i2c 53 on end - end - end # SM - device pci 14.1 on end # IDE 0x439c - device pci 14.2 on end # HDA 0x4383 - device pci 14.3 on # LPC 0x439d - chip superio/ite/it8718f - device pnp 2e.0 off # Floppy - io 0x60 = 0x3f0 - irq 0x70 = 6 - drq 0x74 = 2 - end - device pnp 2e.1 on # Com1 - io 0x60 = 0x3f8 - irq 0x70 = 4 - end - device pnp 2e.2 off # Com2 - io 0x60 = 0x2f8 - irq 0x70 = 3 - end - device pnp 2e.3 off # Parallel Port - io 0x60 = 0x378 - irq 0x70 = 7 - end - device pnp 2e.4 off end # EC - device pnp 2e.5 on # Keyboard - io 0x60 = 0x60 - io 0x62 = 0x64 - irq 0x70 = 1 - end - device pnp 2e.6 on # Mouse - irq 0x70 = 12 - end - device pnp 2e.7 off # GPIO, must be closed for unresolved reason. - end - device pnp 2e.8 off # MIDI - io 0x60 = 0x300 - irq 0x70 = 9 - end - device pnp 2e.9 off # GAME - io 0x60 = 0x220 - end - device pnp 2e.a off end # CIR - end #superio/ite/it8718f - end #LPC - device pci 14.4 on end # PCI 0x4384 - device pci 14.5 on end # USB 2 - register "boot_switch_sata_ide" = "0" # 0: boot from SATA. 1: IDE - end #southbridge/amd/sb700 - end # device pci 18.0 - - device pci 18.0 on end - device pci 18.0 on end - device pci 18.1 on end - device pci 18.2 on end - device pci 18.3 on end - device pci 18.4 on end - end - end #domain - #for node 32 to node 63 -end diff --git a/src/mainboard/gigabyte/ma785gmt/dsdt.asl b/src/mainboard/gigabyte/ma785gmt/dsdt.asl deleted file mode 100644 index eec3093b8e..0000000000 --- a/src/mainboard/gigabyte/ma785gmt/dsdt.asl +++ /dev/null @@ -1,1718 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2010 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -/* DefinitionBlock Statement */ -#include -DefinitionBlock ( - "DSDT.AML", /* Output filename */ - "DSDT", /* Signature */ - 0x02, /* DSDT Revision, needs to be 2 for 64bit */ - OEM_ID, - ACPI_TABLE_CREATOR, - 0x00010001 /* OEM Revision */ - ) -{ /* Start of ASL file */ - /* #include */ /* Include global debug methods if needed */ - - /* Data to be patched by the BIOS during POST */ - /* FIXME the patching is not done yet! */ - /* Memory related values */ - Name(LOMH, 0x0) /* Start of unused memory in C0000-E0000 range */ - Name(PBAD, 0x0) /* Address of BIOS area (If TOM2 != 0, Addr >> 16) */ - Name(PBLN, 0x0) /* Length of BIOS area */ - - Name(PCBA, 0xE0000000) /* Base address of PCIe config space */ - Name(HPBA, 0xFED00000) /* Base address of HPET table */ - - /* USB overcurrent mapping pins. */ - Name(UOM0, 0) - Name(UOM1, 2) - Name(UOM2, 0) - Name(UOM3, 7) - Name(UOM4, 2) - Name(UOM5, 2) - Name(UOM6, 6) - Name(UOM7, 2) - Name(UOM8, 6) - Name(UOM9, 6) - - /* Some global data */ - Name(OSVR, 3) /* Assume nothing. WinXp = 1, Vista = 2, Linux = 3, WinCE = 4 */ - Name(OSV, Ones) /* Assume nothing */ - Name(PMOD, One) /* Assume APIC */ - - /* - * Processor Object - * - */ - Scope (\_PR) { /* define processor scope */ - Device (CPU0) { - Name (_HID, "ACPI0007") - Name (_UID, 0) - #include "acpi/cpstate.asl" - } - Device (CPU1) { - Name (_HID, "ACPI0007") - Name (_UID, 1) - #include "acpi/cpstate.asl" - } - Device (CPU2) { - Name (_HID, "ACPI0007") - Name (_UID, 2) - #include "acpi/cpstate.asl" - } - Device (CPU3) { - Name (_HID, "ACPI0007") - Name (_UID, 3) - #include "acpi/cpstate.asl" - } - } /* End _PR scope */ - - /* PIC IRQ mapping registers, C00h-C01h */ - OperationRegion(PRQM, SystemIO, 0x00000C00, 0x00000002) - Field(PRQM, ByteAcc, NoLock, Preserve) { - PRQI, 0x00000008, - PRQD, 0x00000008, /* Offset: 1h */ - } - IndexField(PRQI, PRQD, ByteAcc, NoLock, Preserve) { - PINA, 0x00000008, /* Index 0 */ - PINB, 0x00000008, /* Index 1 */ - PINC, 0x00000008, /* Index 2 */ - PIND, 0x00000008, /* Index 3 */ - AINT, 0x00000008, /* Index 4 */ - SINT, 0x00000008, /* Index 5 */ - , 0x00000008, /* Index 6 */ - AAUD, 0x00000008, /* Index 7 */ - AMOD, 0x00000008, /* Index 8 */ - PINE, 0x00000008, /* Index 9 */ - PINF, 0x00000008, /* Index A */ - PING, 0x00000008, /* Index B */ - PINH, 0x00000008, /* Index C */ - } - - /* PCI Error control register */ - OperationRegion(PERC, SystemIO, 0x00000C14, 0x00000001) - Field(PERC, ByteAcc, NoLock, Preserve) { - SENS, 0x00000001, - PENS, 0x00000001, - SENE, 0x00000001, - PENE, 0x00000001, - } - - /* Client Management index/data registers */ - OperationRegion(CMT, SystemIO, 0x00000C50, 0x00000002) - Field(CMT, ByteAcc, NoLock, Preserve) { - CMTI, 8, - /* Client Management Data register */ - G64E, 1, - G64O, 1, - G32O, 2, - , 2, - GPSL, 2, - } - - /* GPM Port register */ - OperationRegion(GPT, SystemIO, 0x00000C52, 0x00000001) - Field(GPT, ByteAcc, NoLock, Preserve) { - GPB0,1, - GPB1,1, - GPB2,1, - GPB3,1, - GPB4,1, - GPB5,1, - GPB6,1, - GPB7,1, - } - - /* Flash ROM program enable register */ - OperationRegion(FRE, SystemIO, 0x00000C6F, 0x00000001) - Field(FRE, ByteAcc, NoLock, Preserve) { - , 0x00000006, - FLRE, 0x00000001, - } - - /* PM2 index/data registers */ - OperationRegion(PM2R, SystemIO, 0x00000CD0, 0x00000002) - Field(PM2R, ByteAcc, NoLock, Preserve) { - PM2I, 0x00000008, - PM2D, 0x00000008, - } - - /* Power Management I/O registers */ - OperationRegion(PIOR, SystemIO, 0x00000CD6, 0x00000002) - Field(PIOR, ByteAcc, NoLock, Preserve) { - PIOI, 0x00000008, - PIOD, 0x00000008, - } - IndexField (PIOI, PIOD, ByteAcc, NoLock, Preserve) { - Offset(0x00), /* MiscControl */ - , 1, - T1EE, 1, - T2EE, 1, - Offset(0x01), /* MiscStatus */ - , 1, - T1E, 1, - T2E, 1, - Offset(0x04), /* SmiWakeUpEventEnable3 */ - , 7, - SSEN, 1, - Offset(0x07), /* SmiWakeUpEventStatus3 */ - , 7, - CSSM, 1, - Offset(0x10), /* AcpiEnable */ - , 6, - PWDE, 1, - Offset(0x1C), /* ProgramIoEnable */ - , 3, - MKME, 1, - IO3E, 1, - IO2E, 1, - IO1E, 1, - IO0E, 1, - Offset(0x1D), /* IOMonitorStatus */ - , 3, - MKMS, 1, - IO3S, 1, - IO2S, 1, - IO1S, 1, - IO0S,1, - Offset(0x20), /* AcpiPmEvtBlk */ - APEB, 16, - Offset(0x36), /* GEvtLevelConfig */ - , 6, - ELC6, 1, - ELC7, 1, - Offset(0x37), /* GPMLevelConfig0 */ - , 3, - PLC0, 1, - PLC1, 1, - PLC2, 1, - PLC3, 1, - PLC8, 1, - Offset(0x38), /* GPMLevelConfig1 */ - , 1, - PLC4, 1, - PLC5, 1, - , 1, - PLC6, 1, - PLC7, 1, - Offset(0x3B), /* PMEStatus1 */ - GP0S, 1, - GM4S, 1, - GM5S, 1, - APS, 1, - GM6S, 1, - GM7S, 1, - GP2S, 1, - STSS, 1, - Offset(0x55), /* SoftPciRst */ - SPRE, 1, - , 1, - , 1, - PNAT, 1, - PWMK, 1, - PWNS, 1, - - /* Offset(0x61), */ /* Options_1 */ - /* ,7, */ - /* R617,1, */ - - Offset(0x65), /* UsbPMControl */ - , 4, - URRE, 1, - Offset(0x68), /* MiscEnable68 */ - , 3, - TMTE, 1, - , 1, - Offset(0x92), /* GEVENTIN */ - , 7, - E7IS, 1, - Offset(0x96), /* GPM98IN */ - G8IS, 1, - G9IS, 1, - Offset(0x9A), /* EnhanceControl */ - ,7, - HPDE, 1, - Offset(0xA8), /* PIO7654Enable */ - IO4E, 1, - IO5E, 1, - IO6E, 1, - IO7E, 1, - Offset(0xA9), /* PIO7654Status */ - IO4S, 1, - IO5S, 1, - IO6S, 1, - IO7S, 1, - } - - /* PM1 Event Block - * First word is PM1_Status, Second word is PM1_Enable - */ - OperationRegion(P1EB, SystemIO, APEB, 0x04) - Field(P1EB, ByteAcc, NoLock, Preserve) { - TMST, 1, - , 3, - BMST, 1, - GBST, 1, - Offset(0x01), - PBST, 1, - , 1, - RTST, 1, - , 3, - PWST, 1, - SPWS, 1, - Offset(0x02), - TMEN, 1, - , 4, - GBEN, 1, - Offset(0x03), - PBEN, 1, - , 1, - RTEN, 1, - , 3, - PWDA, 1, - } - - Scope(\_SB) { - /* PCIe Configuration Space for 16 busses */ - OperationRegion(PCFG, SystemMemory, PCBA, 0x01000000) /* Each bus consumes 1MB */ - Field(PCFG, ByteAcc, NoLock, Preserve) { - /* Byte offsets are computed using the following technique: - * ((bus number + 1) * ((device number * 8) * 4096)) + register offset - * The 8 comes from 8 functions per device, and 4096 bytes per function config space - */ - Offset(0x00088024), /* Byte offset to SATA register 24h - Bus 0, Device 17, Function 0 */ - STB5, 32, - Offset(0x00098042), /* Byte offset to OHCI0 register 42h - Bus 0, Device 19, Function 0 */ - PT0D, 1, - PT1D, 1, - PT2D, 1, - PT3D, 1, - PT4D, 1, - PT5D, 1, - PT6D, 1, - PT7D, 1, - PT8D, 1, - PT9D, 1, - Offset(0x000A0004), /* Byte offset to SMBUS register 4h - Bus 0, Device 20, Function 0 */ - SBIE, 1, - SBME, 1, - Offset(0x000A0008), /* Byte offset to SMBUS register 8h - Bus 0, Device 20, Function 0 */ - SBRI, 8, - Offset(0x000A0014), /* Byte offset to SMBUS register 14h - Bus 0, Device 20, Function 0 */ - SBB1, 32, - Offset(0x000A0078), /* Byte offset to SMBUS register 78h - Bus 0, Device 20, Function 0 */ - ,14, - P92E, 1, /* Port92 decode enable */ - } - - OperationRegion(SB5, SystemMemory, STB5, 0x1000) - Field(SB5, AnyAcc, NoLock, Preserve){ - /* Port 0 */ - Offset(0x120), /* Port 0 Task file status */ - P0ER, 1, - , 2, - P0DQ, 1, - , 3, - P0BY, 1, - Offset(0x128), /* Port 0 Serial ATA status */ - P0DD, 4, - , 4, - P0IS, 4, - Offset(0x12C), /* Port 0 Serial ATA control */ - P0DI, 4, - Offset(0x130), /* Port 0 Serial ATA error */ - , 16, - P0PR, 1, - - /* Port 1 */ - offset(0x1A0), /* Port 1 Task file status */ - P1ER, 1, - , 2, - P1DQ, 1, - , 3, - P1BY, 1, - Offset(0x1A8), /* Port 1 Serial ATA status */ - P1DD, 4, - , 4, - P1IS, 4, - Offset(0x1AC), /* Port 1 Serial ATA control */ - P1DI, 4, - Offset(0x1B0), /* Port 1 Serial ATA error */ - , 16, - P1PR, 1, - - /* Port 2 */ - Offset(0x220), /* Port 2 Task file status */ - P2ER, 1, - , 2, - P2DQ, 1, - , 3, - P2BY, 1, - Offset(0x228), /* Port 2 Serial ATA status */ - P2DD, 4, - , 4, - P2IS, 4, - Offset(0x22C), /* Port 2 Serial ATA control */ - P2DI, 4, - Offset(0x230), /* Port 2 Serial ATA error */ - , 16, - P2PR, 1, - - /* Port 3 */ - Offset(0x2A0), /* Port 3 Task file status */ - P3ER, 1, - , 2, - P3DQ, 1, - , 3, - P3BY, 1, - Offset(0x2A8), /* Port 3 Serial ATA status */ - P3DD, 4, - , 4, - P3IS, 4, - Offset(0x2AC), /* Port 3 Serial ATA control */ - P3DI, 4, - Offset(0x2B0), /* Port 3 Serial ATA error */ - , 16, - P3PR, 1, - } - } - - - #include "acpi/routing.asl" - - Scope(\_SB) { - - Method(OSFL, 0){ - - if(LNotEqual(OSVR, Ones)) {Return(OSVR)} /* OS version was already detected */ - - if(CondRefOf(\_OSI)) - { - Store(1, OSVR) /* Assume some form of XP */ - if (\_OSI("Windows 2006")) /* Vista */ - { - Store(2, OSVR) - } - } else { - If(WCMP(\_OS,"Linux")) { - Store(3, OSVR) /* Linux */ - } Else { - Store(4, OSVR) /* Gotta be WinCE */ - } - } - Return(OSVR) - } - - Method(_PIC, 0x01, NotSerialized) - { - If (Arg0) - { - \_SB.CIRQ() - } - Store(Arg0, PMOD) - } - Method(CIRQ, 0x00, NotSerialized){ - Store(0, PINA) - Store(0, PINB) - Store(0, PINC) - Store(0, PIND) - Store(0, PINE) - Store(0, PINF) - Store(0, PING) - Store(0, PINH) - } - - Name(IRQB, ResourceTemplate(){ - IRQ(Level,ActiveLow,Shared){15} - }) - - Name(IRQP, ResourceTemplate(){ - IRQ(Level,ActiveLow,Exclusive){3, 4, 5, 7, 10, 11, 12, 15} - }) - - Name(PITF, ResourceTemplate(){ - IRQ(Level,ActiveLow,Exclusive){9} - }) - - Device(INTA) { - Name(_HID, EISAID("PNP0C0F")) - Name(_UID, 1) - - Method(_STA, 0) { - if (PINA) { - Return(0x0B) /* sata is invisible */ - } else { - Return(0x09) /* sata is disabled */ - } - } /* End Method(_SB.INTA._STA) */ - - Method(_DIS ,0) { - /* DBGO("\\_SB\\LNKA\\_DIS\n") */ - Store(0, PINA) - } /* End Method(_SB.INTA._DIS) */ - - Method(_PRS ,0) { - /* DBGO("\\_SB\\LNKA\\_PRS\n") */ - Return(IRQP) - } /* Method(_SB.INTA._PRS) */ - - Method(_CRS ,0) { - /* DBGO("\\_SB\\LNKA\\_CRS\n") */ - CreateWordField(IRQB, 0x1, IRQN) - ShiftLeft(1, PINA, IRQN) - Return(IRQB) - } /* Method(_SB.INTA._CRS) */ - - Method(_SRS, 1) { - /* DBGO("\\_SB\\LNKA\\_CRS\n") */ - CreateWordField(ARG0, 1, IRQM) - - /* Use lowest available IRQ */ - FindSetRightBit(IRQM, Local0) - if (Local0) { - Decrement(Local0) - } - Store(Local0, PINA) - } /* End Method(_SB.INTA._SRS) */ - } /* End Device(INTA) */ - - Device(INTB) { - Name(_HID, EISAID("PNP0C0F")) - Name(_UID, 2) - - Method(_STA, 0) { - if (PINB) { - Return(0x0B) /* sata is invisible */ - } else { - Return(0x09) /* sata is disabled */ - } - } /* End Method(_SB.INTB._STA) */ - - Method(_DIS ,0) { - /* DBGO("\\_SB\\LNKB\\_DIS\n") */ - Store(0, PINB) - } /* End Method(_SB.INTB._DIS) */ - - Method(_PRS ,0) { - /* DBGO("\\_SB\\LNKB\\_PRS\n") */ - Return(IRQP) - } /* Method(_SB.INTB._PRS) */ - - Method(_CRS ,0) { - /* DBGO("\\_SB\\LNKB\\_CRS\n") */ - CreateWordField(IRQB, 0x1, IRQN) - ShiftLeft(1, PINB, IRQN) - Return(IRQB) - } /* Method(_SB.INTB._CRS) */ - - Method(_SRS, 1) { - /* DBGO("\\_SB\\LNKB\\_CRS\n") */ - CreateWordField(ARG0, 1, IRQM) - - /* Use lowest available IRQ */ - FindSetRightBit(IRQM, Local0) - if (Local0) { - Decrement(Local0) - } - Store(Local0, PINB) - } /* End Method(_SB.INTB._SRS) */ - } /* End Device(INTB) */ - - Device(INTC) { - Name(_HID, EISAID("PNP0C0F")) - Name(_UID, 3) - - Method(_STA, 0) { - if (PINC) { - Return(0x0B) /* sata is invisible */ - } else { - Return(0x09) /* sata is disabled */ - } - } /* End Method(_SB.INTC._STA) */ - - Method(_DIS ,0) { - /* DBGO("\\_SB\\LNKC\\_DIS\n") */ - Store(0, PINC) - } /* End Method(_SB.INTC._DIS) */ - - Method(_PRS ,0) { - /* DBGO("\\_SB\\LNKC\\_PRS\n") */ - Return(IRQP) - } /* Method(_SB.INTC._PRS) */ - - Method(_CRS ,0) { - /* DBGO("\\_SB\\LNKC\\_CRS\n") */ - CreateWordField(IRQB, 0x1, IRQN) - ShiftLeft(1, PINC, IRQN) - Return(IRQB) - } /* Method(_SB.INTC._CRS) */ - - Method(_SRS, 1) { - /* DBGO("\\_SB\\LNKC\\_CRS\n") */ - CreateWordField(ARG0, 1, IRQM) - - /* Use lowest available IRQ */ - FindSetRightBit(IRQM, Local0) - if (Local0) { - Decrement(Local0) - } - Store(Local0, PINC) - } /* End Method(_SB.INTC._SRS) */ - } /* End Device(INTC) */ - - Device(INTD) { - Name(_HID, EISAID("PNP0C0F")) - Name(_UID, 4) - - Method(_STA, 0) { - if (PIND) { - Return(0x0B) /* sata is invisible */ - } else { - Return(0x09) /* sata is disabled */ - } - } /* End Method(_SB.INTD._STA) */ - - Method(_DIS ,0) { - /* DBGO("\\_SB\\LNKD\\_DIS\n") */ - Store(0, PIND) - } /* End Method(_SB.INTD._DIS) */ - - Method(_PRS ,0) { - /* DBGO("\\_SB\\LNKD\\_PRS\n") */ - Return(IRQP) - } /* Method(_SB.INTD._PRS) */ - - Method(_CRS ,0) { - /* DBGO("\\_SB\\LNKD\\_CRS\n") */ - CreateWordField(IRQB, 0x1, IRQN) - ShiftLeft(1, PIND, IRQN) - Return(IRQB) - } /* Method(_SB.INTD._CRS) */ - - Method(_SRS, 1) { - /* DBGO("\\_SB\\LNKD\\_CRS\n") */ - CreateWordField(ARG0, 1, IRQM) - - /* Use lowest available IRQ */ - FindSetRightBit(IRQM, Local0) - if (Local0) { - Decrement(Local0) - } - Store(Local0, PIND) - } /* End Method(_SB.INTD._SRS) */ - } /* End Device(INTD) */ - - Device(INTE) { - Name(_HID, EISAID("PNP0C0F")) - Name(_UID, 5) - - Method(_STA, 0) { - if (PINE) { - Return(0x0B) /* sata is invisible */ - } else { - Return(0x09) /* sata is disabled */ - } - } /* End Method(_SB.INTE._STA) */ - - Method(_DIS ,0) { - /* DBGO("\\_SB\\LNKE\\_DIS\n") */ - Store(0, PINE) - } /* End Method(_SB.INTE._DIS) */ - - Method(_PRS ,0) { - /* DBGO("\\_SB\\LNKE\\_PRS\n") */ - Return(IRQP) - } /* Method(_SB.INTE._PRS) */ - - Method(_CRS ,0) { - /* DBGO("\\_SB\\LNKE\\_CRS\n") */ - CreateWordField(IRQB, 0x1, IRQN) - ShiftLeft(1, PINE, IRQN) - Return(IRQB) - } /* Method(_SB.INTE._CRS) */ - - Method(_SRS, 1) { - /* DBGO("\\_SB\\LNKE\\_CRS\n") */ - CreateWordField(ARG0, 1, IRQM) - - /* Use lowest available IRQ */ - FindSetRightBit(IRQM, Local0) - if (Local0) { - Decrement(Local0) - } - Store(Local0, PINE) - } /* End Method(_SB.INTE._SRS) */ - } /* End Device(INTE) */ - - Device(INTF) { - Name(_HID, EISAID("PNP0C0F")) - Name(_UID, 6) - - Method(_STA, 0) { - if (PINF) { - Return(0x0B) /* sata is invisible */ - } else { - Return(0x09) /* sata is disabled */ - } - } /* End Method(_SB.INTF._STA) */ - - Method(_DIS ,0) { - /* DBGO("\\_SB\\LNKF\\_DIS\n") */ - Store(0, PINF) - } /* End Method(_SB.INTF._DIS) */ - - Method(_PRS ,0) { - /* DBGO("\\_SB\\LNKF\\_PRS\n") */ - Return(PITF) - } /* Method(_SB.INTF._PRS) */ - - Method(_CRS ,0) { - /* DBGO("\\_SB\\LNKF\\_CRS\n") */ - CreateWordField(IRQB, 0x1, IRQN) - ShiftLeft(1, PINF, IRQN) - Return(IRQB) - } /* Method(_SB.INTF._CRS) */ - - Method(_SRS, 1) { - /* DBGO("\\_SB\\LNKF\\_CRS\n") */ - CreateWordField(ARG0, 1, IRQM) - - /* Use lowest available IRQ */ - FindSetRightBit(IRQM, Local0) - if (Local0) { - Decrement(Local0) - } - Store(Local0, PINF) - } /* End Method(_SB.INTF._SRS) */ - } /* End Device(INTF) */ - - Device(INTG) { - Name(_HID, EISAID("PNP0C0F")) - Name(_UID, 7) - - Method(_STA, 0) { - if (PING) { - Return(0x0B) /* sata is invisible */ - } else { - Return(0x09) /* sata is disabled */ - } - } /* End Method(_SB.INTG._STA) */ - - Method(_DIS ,0) { - /* DBGO("\\_SB\\LNKG\\_DIS\n") */ - Store(0, PING) - } /* End Method(_SB.INTG._DIS) */ - - Method(_PRS ,0) { - /* DBGO("\\_SB\\LNKG\\_PRS\n") */ - Return(IRQP) - } /* Method(_SB.INTG._CRS) */ - - Method(_CRS ,0) { - /* DBGO("\\_SB\\LNKG\\_CRS\n") */ - CreateWordField(IRQB, 0x1, IRQN) - ShiftLeft(1, PING, IRQN) - Return(IRQB) - } /* Method(_SB.INTG._CRS) */ - - Method(_SRS, 1) { - /* DBGO("\\_SB\\LNKG\\_CRS\n") */ - CreateWordField(ARG0, 1, IRQM) - - /* Use lowest available IRQ */ - FindSetRightBit(IRQM, Local0) - if (Local0) { - Decrement(Local0) - } - Store(Local0, PING) - } /* End Method(_SB.INTG._SRS) */ - } /* End Device(INTG) */ - - Device(INTH) { - Name(_HID, EISAID("PNP0C0F")) - Name(_UID, 8) - - Method(_STA, 0) { - if (PINH) { - Return(0x0B) /* sata is invisible */ - } else { - Return(0x09) /* sata is disabled */ - } - } /* End Method(_SB.INTH._STA) */ - - Method(_DIS ,0) { - /* DBGO("\\_SB\\LNKH\\_DIS\n") */ - Store(0, PINH) - } /* End Method(_SB.INTH._DIS) */ - - Method(_PRS ,0) { - /* DBGO("\\_SB\\LNKH\\_PRS\n") */ - Return(IRQP) - } /* Method(_SB.INTH._CRS) */ - - Method(_CRS ,0) { - /* DBGO("\\_SB\\LNKH\\_CRS\n") */ - CreateWordField(IRQB, 0x1, IRQN) - ShiftLeft(1, PINH, IRQN) - Return(IRQB) - } /* Method(_SB.INTH._CRS) */ - - Method(_SRS, 1) { - /* DBGO("\\_SB\\LNKH\\_CRS\n") */ - CreateWordField(ARG0, 1, IRQM) - - /* Use lowest available IRQ */ - FindSetRightBit(IRQM, Local0) - if (Local0) { - Decrement(Local0) - } - Store(Local0, PINH) - } /* End Method(_SB.INTH._SRS) */ - } /* End Device(INTH) */ - - } /* End Scope(_SB) */ - - #include - - /* Wake status package */ - Name(WKST,Package(){Zero, Zero}) - - /* - * \_PTS - Prepare to Sleep method - * - * Entry: - * Arg0=The value of the sleeping state S1=1, S2=2, etc - * - * Exit: - * -none- - * - * The _PTS control method is executed at the beginning of the sleep process - * for S1-S5. The sleeping value is passed to the _PTS control method. This - * control method may be executed a relatively long time before entering the - * sleep state and the OS may abort the operation without notification to - * the ACPI driver. This method cannot modify the configuration or power - * state of any device in the system. - */ - Method(\_PTS, 1) { - /* DBGO("\\_PTS\n") */ - /* DBGO("From S0 to S") */ - /* DBGO(Arg0) */ - /* DBGO("\n") */ - - /* Don't allow PCIRST# to reset USB */ - if (LEqual(Arg0,3)){ - Store(0,URRE) - } - - /* Clear sleep SMI status flag and enable sleep SMI trap. */ - /*Store(One, CSSM) - Store(One, SSEN)*/ - - /* On older chips, clear PciExpWakeDisEn */ - /*if (LLessEqual(\_SB.SBRI, 0x13)) { - * Store(0,\_SB.PWDE) - *} - */ - - /* Clear wake status structure. */ - Store(0, Index(WKST,0)) - Store(0, Index(WKST,1)) - \_SB.PCI0.SIOS (Arg0) - } /* End Method(\_PTS) */ - - /* - * The following method results in a "not a valid reserved NameSeg" - * warning so I have commented it out for the duration. It isn't - * used, so it could be removed. - * - * - * \_GTS OEM Going To Sleep method - * - * Entry: - * Arg0=The value of the sleeping state S1=1, S2=2 - * - * Exit: - * -none- - * - * Method(\_GTS, 1) { - * DBGO("\\_GTS\n") - * DBGO("From S0 to S") - * DBGO(Arg0) - * DBGO("\n") - * } - */ - - /* - * \_BFS OEM Back From Sleep method - * - * Entry: - * Arg0=The value of the sleeping state S1=1, S2=2 - * - * Exit: - * -none- - */ - Method(\_BFS, 1) { - /* DBGO("\\_BFS\n") */ - /* DBGO("From S") */ - /* DBGO(Arg0) */ - /* DBGO(" to S0\n") */ - } - - /* - * \_WAK System Wake method - * - * Entry: - * Arg0=The value of the sleeping state S1=1, S2=2 - * - * Exit: - * Return package of 2 DWords - * Dword 1 - Status - * 0x00000000 wake succeeded - * 0x00000001 Wake was signaled but failed due to lack of power - * 0x00000002 Wake was signaled but failed due to thermal condition - * Dword 2 - Power Supply state - * if non-zero the effective S-state the power supply entered - */ - Method(\_WAK, 1) { - /* DBGO("\\_WAK\n") */ - /* DBGO("From S") */ - /* DBGO(Arg0) */ - /* DBGO(" to S0\n") */ - - /* Re-enable HPET */ - Store(1,HPDE) - - /* Restore PCIRST# so it resets USB */ - if (LEqual(Arg0,3)){ - Store(1,URRE) - } - - /* Arbitrarily clear PciExpWakeStatus */ - Store(PWST, Local1) - Store(Local1, PWST) - - /* if (DeRefOf(Index(WKST,0))) { - * Store(0, Index(WKST,1)) - * } else { - * Store(Arg0, Index(WKST,1)) - * } - */ - \_SB.PCI0.SIOW () - Return(WKST) - } /* End Method(\_WAK) */ - - Scope(\_GPE) { /* Start Scope GPE */ - /* General event 0 */ - /* Method(_L00) { - * DBGO("\\_GPE\\_L00\n") - * } - */ - - /* General event 1 */ - /* Method(_L01) { - * DBGO("\\_GPE\\_L00\n") - * } - */ - - /* General event 2 */ - /* Method(_L02) { - * DBGO("\\_GPE\\_L00\n") - * } - */ - - /* General event 3 */ - Method(_L03) { - /* DBGO("\\_GPE\\_L00\n") */ - Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ - } - - /* General event 4 */ - /* Method(_L04) { - * DBGO("\\_GPE\\_L00\n") - * } - */ - - /* General event 5 */ - /* Method(_L05) { - * DBGO("\\_GPE\\_L00\n") - * } - */ - - /* General event 6 - Used for GPM6, moved to USB.asl */ - /* Method(_L06) { - * DBGO("\\_GPE\\_L00\n") - * } - */ - - /* General event 7 - Used for GPM7, moved to USB.asl */ - /* Method(_L07) { - * DBGO("\\_GPE\\_L07\n") - * } - */ - - /* Legacy PM event */ - Method(_L08) { - /* DBGO("\\_GPE\\_L08\n") */ - } - - /* Temp warning (TWarn) event */ - Method(_L09) { - /* DBGO("\\_GPE\\_L09\n") */ - Notify (\_TZ.TZ00, 0x80) - } - - /* Reserved */ - /* Method(_L0A) { - * DBGO("\\_GPE\\_L0A\n") - * } - */ - - /* USB controller PME# */ - Method(_L0B) { - /* DBGO("\\_GPE\\_L0B\n") */ - Notify(\_SB.PCI0.UOH1, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(\_SB.PCI0.UOH2, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(\_SB.PCI0.UOH3, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(\_SB.PCI0.UOH4, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(\_SB.PCI0.UOH5, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(\_SB.PCI0.UEH1, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ - } - - /* AC97 controller PME# */ - /* Method(_L0C) { - * DBGO("\\_GPE\\_L0C\n") - * } - */ - - /* OtherTherm PME# */ - /* Method(_L0D) { - * DBGO("\\_GPE\\_L0D\n") - * } - */ - - /* GPM9 SCI event - Moved to USB.asl */ - /* Method(_L0E) { - * DBGO("\\_GPE\\_L0E\n") - * } - */ - - /* PCIe HotPlug event */ - /* Method(_L0F) { - * DBGO("\\_GPE\\_L0F\n") - * } - */ - - /* ExtEvent0 SCI event */ - Method(_L10) { - /* DBGO("\\_GPE\\_L10\n") */ - } - - - /* ExtEvent1 SCI event */ - Method(_L11) { - /* DBGO("\\_GPE\\_L11\n") */ - } - - /* PCIe PME# event */ - /* Method(_L12) { - * DBGO("\\_GPE\\_L12\n") - * } - */ - - /* GPM0 SCI event - Moved to USB.asl */ - /* Method(_L13) { - * DBGO("\\_GPE\\_L13\n") - * } - */ - - /* GPM1 SCI event - Moved to USB.asl */ - /* Method(_L14) { - * DBGO("\\_GPE\\_L14\n") - * } - */ - - /* GPM2 SCI event - Moved to USB.asl */ - /* Method(_L15) { - * DBGO("\\_GPE\\_L15\n") - * } - */ - - /* GPM3 SCI event - Moved to USB.asl */ - /* Method(_L16) { - * DBGO("\\_GPE\\_L16\n") - * } - */ - - /* GPM8 SCI event - Moved to USB.asl */ - /* Method(_L17) { - * DBGO("\\_GPE\\_L17\n") - * } - */ - - /* GPIO0 or GEvent8 event */ - Method(_L18) { - /* DBGO("\\_GPE\\_L18\n") */ - Notify(\_SB.PCI0.PBR2, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(\_SB.PCI0.PBR4, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(\_SB.PCI0.PBR5, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(\_SB.PCI0.PBR6, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(\_SB.PCI0.PBR7, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ - } - - /* GPM4 SCI event - Moved to USB.asl */ - /* Method(_L19) { - * DBGO("\\_GPE\\_L19\n") - * } - */ - - /* GPM5 SCI event - Moved to USB.asl */ - /* Method(_L1A) { - * DBGO("\\_GPE\\_L1A\n") - * } - */ - - /* Azalia SCI event */ - Method(_L1B) { - /* DBGO("\\_GPE\\_L1B\n") */ - Notify(\_SB.PCI0.AZHD, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ - } - - /* GPM6 SCI event - Reassigned to _L06 */ - /* Method(_L1C) { - * DBGO("\\_GPE\\_L1C\n") - * } - */ - - /* GPM7 SCI event - Reassigned to _L07 */ - /* Method(_L1D) { - * DBGO("\\_GPE\\_L1D\n") - * } - */ - - /* GPIO2 or GPIO66 SCI event */ - /* Method(_L1E) { - * DBGO("\\_GPE\\_L1E\n") - * } - */ - - /* SATA SCI event - Moved to sata.asl */ - /* Method(_L1F) { - * DBGO("\\_GPE\\_L1F\n") - * } - */ - - } /* End Scope GPE */ - - #include "acpi/usb.asl" - - /* System Bus */ - Scope(\_SB) { /* Start \_SB scope */ - #include /* global utility methods expected within the \_SB scope */ - - /* _SB.PCI0 */ - /* Note: Only need HID on Primary Bus */ - Device(PCI0) { - External (TOM1) - External (TOM2) /* ( >> 20) to make it fit into 32 bit for XP */ - Name(_HID, EISAID("PNP0A03")) - Name(_ADR, 0x00180000) /* Dev# = BSP Dev#, Func# = 0 */ - Method(_BBN, 0) { /* Bus number = 0 */ - Return(0) - } - Method(_STA, 0) { - /* DBGO("\\_SB\\PCI0\\_STA\n") */ - Return(0x0B) /* Status is visible */ - } - - Method(_PRT,0) { - If(PMOD){ Return(APR0) } /* APIC mode */ - Return (PR0) /* PIC Mode */ - } /* end _PRT */ - - /* Describe the Northbridge devices */ - Device(AMRT) { - Name(_ADR, 0x00000000) - } /* end AMRT */ - - /* The internal GFX bridge */ - Device(AGPB) { - Name(_ADR, 0x00010000) - Name(_PRW, Package() {0x18, 4}) - Method(_PRT,0) { - Return (APR1) - } - } /* end AGPB */ - - /* The external GFX bridge */ - Device(PBR2) { - Name(_ADR, 0x00020000) - Name(_PRW, Package() {0x18, 4}) - Method(_PRT,0) { - If(PMOD){ Return(APS2) } /* APIC mode */ - Return (PS2) /* PIC Mode */ - } /* end _PRT */ - } /* end PBR2 */ - - /* Dev3 is also an external GFX bridge, not used in Herring */ - - Device(PBR4) { - Name(_ADR, 0x00040000) - Name(_PRW, Package() {0x18, 4}) - Method(_PRT,0) { - If(PMOD){ Return(APS4) } /* APIC mode */ - Return (PS4) /* PIC Mode */ - } /* end _PRT */ - } /* end PBR4 */ - - Device(PBR5) { - Name(_ADR, 0x00050000) - Name(_PRW, Package() {0x18, 4}) - Method(_PRT,0) { - If(PMOD){ Return(APS5) } /* APIC mode */ - Return (PS5) /* PIC Mode */ - } /* end _PRT */ - } /* end PBR5 */ - - Device(PBR6) { - Name(_ADR, 0x00060000) - Name(_PRW, Package() {0x18, 4}) - Method(_PRT,0) { - If(PMOD){ Return(APS6) } /* APIC mode */ - Return (PS6) /* PIC Mode */ - } /* end _PRT */ - } /* end PBR6 */ - - /* The onboard EtherNet chip */ - Device(PBR7) { - Name(_ADR, 0x00070000) - Name(_PRW, Package() {0x18, 4}) - Method(_PRT,0) { - If(PMOD){ Return(APS7) } /* APIC mode */ - Return (PS7) /* PIC Mode */ - } /* end _PRT */ - } /* end PBR7 */ - - /* GPP */ - Device(PBR9) { - Name(_ADR, 0x00090000) - Name(_PRW, Package() {0x18, 4}) - Method(_PRT,0) { - If(PMOD){ Return(APS9) } /* APIC mode */ - Return (PS9) /* PIC Mode */ - } /* end _PRT */ - } /* end PBR9 */ - - Device(PBRa) { - Name(_ADR, 0x000A0000) - Name(_PRW, Package() {0x18, 4}) - Method(_PRT,0) { - If(PMOD){ Return(APSa) } /* APIC mode */ - Return (PSa) /* PIC Mode */ - } /* end _PRT */ - } /* end PBRa */ - - - /* PCI slot 1, 2, 3 */ - Device(PIBR) { - Name(_ADR, 0x00140004) - Name(_PRW, Package() {0x18, 4}) - - Method(_PRT, 0) { - Return (PCIB) - } - } - - /* Describe the Southbridge devices */ - Device(STCR) { - Name(_ADR, 0x00110000) - #include "acpi/sata.asl" - } /* end STCR */ - - Device(UOH1) { - Name(_ADR, 0x00130000) - Name(_PRW, Package() {0x0B, 3}) - } /* end UOH1 */ - - Device(UOH2) { - Name(_ADR, 0x00130001) - Name(_PRW, Package() {0x0B, 3}) - } /* end UOH2 */ - - Device(UOH3) { - Name(_ADR, 0x00130002) - Name(_PRW, Package() {0x0B, 3}) - } /* end UOH3 */ - - Device(UOH4) { - Name(_ADR, 0x00130003) - Name(_PRW, Package() {0x0B, 3}) - } /* end UOH4 */ - - Device(UOH5) { - Name(_ADR, 0x00130004) - Name(_PRW, Package() {0x0B, 3}) - } /* end UOH5 */ - - Device(UEH1) { - Name(_ADR, 0x00130005) - Name(_PRW, Package() {0x0B, 3}) - } /* end UEH1 */ - - Device(SBUS) { - Name(_ADR, 0x00140000) - } /* end SBUS */ - - /* Primary (and only) IDE channel */ - Device(IDEC) { - Name(_ADR, 0x00140001) - #include "acpi/ide.asl" - } /* end IDEC */ - - Device(AZHD) { - Name(_ADR, 0x00140002) - OperationRegion(AZPD, PCI_Config, 0x00, 0x100) - Field(AZPD, AnyAcc, NoLock, Preserve) { - offset (0x42), - NSDI, 1, - NSDO, 1, - NSEN, 1, - offset (0x44), - IPCR, 4, - offset (0x54), - PWST, 2, - , 6, - PMEB, 1, - , 6, - PMST, 1, - offset (0x62), - MMCR, 1, - offset (0x64), - MMLA, 32, - offset (0x68), - MMHA, 32, - offset (0x6C), - MMDT, 16, - } - - Method(_INI) { - If(LEqual(OSVR,3)){ /* If we are running Linux */ - Store(zero, NSEN) - Store(one, NSDO) - Store(one, NSDI) - } - } - } /* end AZHD */ - - Device(LIBR) { - Name(_ADR, 0x00140003) - /* Method(_INI) { - * DBGO("\\_SB\\PCI0\\LpcIsaBr\\_INI\n") - } */ /* End Method(_SB.SBRDG._INI) */ - - /* Real Time Clock Device */ - Device(RTC0) { - Name(_HID, EISAID("PNP0B00")) /* AT Real Time Clock (not PIIX4 compatible) */ - Name(_CRS, ResourceTemplate() { - IRQNoFlags(){8} - IO(Decode16,0x0070, 0x0070, 0, 2) - /* IO(Decode16,0x0070, 0x0070, 0, 4) */ - }) - } /* End Device(_SB.PCI0.LpcIsaBr.RTC0) */ - - Device(TMR) { /* Timer */ - Name(_HID,EISAID("PNP0100")) /* System Timer */ - Name(_CRS, ResourceTemplate() { - IRQNoFlags(){0} - IO(Decode16, 0x0040, 0x0040, 0, 4) - /* IO(Decode16, 0x0048, 0x0048, 0, 4) */ - }) - } /* End Device(_SB.PCI0.LpcIsaBr.TMR) */ - - Device(SPKR) { /* Speaker */ - Name(_HID,EISAID("PNP0800")) /* AT style speaker */ - Name(_CRS, ResourceTemplate() { - IO(Decode16, 0x0061, 0x0061, 0, 1) - }) - } /* End Device(_SB.PCI0.LpcIsaBr.SPKR) */ - - Device(PIC) { - Name(_HID,EISAID("PNP0000")) /* AT Interrupt Controller */ - Name(_CRS, ResourceTemplate() { - IRQNoFlags(){2} - IO(Decode16,0x0020, 0x0020, 0, 2) - IO(Decode16,0x00A0, 0x00A0, 0, 2) - /* IO(Decode16, 0x00D0, 0x00D0, 0x10, 0x02) */ - /* IO(Decode16, 0x04D0, 0x04D0, 0x10, 0x02) */ - }) - } /* End Device(_SB.PCI0.LpcIsaBr.PIC) */ - - Device(MAD) { /* 8257 DMA */ - Name(_HID,EISAID("PNP0200")) /* Hardware Device ID */ - Name(_CRS, ResourceTemplate() { - DMA(Compatibility,BusMaster,Transfer8){4} - IO(Decode16, 0x0000, 0x0000, 0x10, 0x10) - IO(Decode16, 0x0081, 0x0081, 0x01, 0x03) - IO(Decode16, 0x0087, 0x0087, 0x01, 0x01) - IO(Decode16, 0x0089, 0x0089, 0x01, 0x03) - IO(Decode16, 0x008F, 0x008F, 0x01, 0x01) - IO(Decode16, 0x00C0, 0x00C0, 0x10, 0x20) - }) /* End Name(_SB.PCI0.LpcIsaBr.MAD._CRS) */ - } /* End Device(_SB.PCI0.LpcIsaBr.MAD) */ - - Device(COPR) { - Name(_HID,EISAID("PNP0C04")) /* Math Coprocessor */ - Name(_CRS, ResourceTemplate() { - IO(Decode16, 0x00F0, 0x00F0, 0, 0x10) - IRQNoFlags(){13} - }) - } /* End Device(_SB.PCI0.LpcIsaBr.COPR) */ - - Device(HPTM) { - Name(_HID,EISAID("PNP0103")) - Name(CRS,ResourceTemplate() { - Memory32Fixed(ReadOnly,0xFED00000, 0x00000400, HPT) /* 1kb reserved space */ - }) - Method(_STA, 0) { - Return(0x0F) /* sata is visible */ - } - Method(_CRS, 0) { - CreateDwordField(CRS, ^HPT._BAS, HPBX) - Store(HPBA, HPBX) - Return(CRS) - } - } /* End Device(_SB.PCI0.LpcIsaBr.COPR) */ - } /* end LIBR */ - - Device(HPBR) { - Name(_ADR, 0x00140004) - } /* end HostPciBr */ - - Device(ACAD) { - Name(_ADR, 0x00140005) - } /* end Ac97audio */ - - Device(ACMD) { - Name(_ADR, 0x00140006) - } /* end Ac97modem */ - - /* ITE8718 Support */ - OperationRegion (IOID, SystemIO, 0x2E, 0x02) /* sometimes it is 0x4E */ - Field (IOID, ByteAcc, NoLock, Preserve) - { - SIOI, 8, SIOD, 8 /* 0x2E and 0x2F */ - } - - IndexField (SIOI, SIOD, ByteAcc, NoLock, Preserve) - { - Offset (0x07), - LDN, 8, /* Logical Device Number */ - Offset (0x20), - CID1, 8, /* Chip ID Byte 1, 0x87 */ - CID2, 8, /* Chip ID Byte 2, 0x12 */ - Offset (0x30), - ACTR, 8, /* Function activate */ - Offset (0xF0), - APC0, 8, /* APC/PME Event Enable Register */ - APC1, 8, /* APC/PME Status Register */ - APC2, 8, /* APC/PME Control Register 1 */ - APC3, 8, /* Environment Controller Special Configuration Register */ - APC4, 8 /* APC/PME Control Register 2 */ - } - - /* Enter the 8718 MB PnP Mode */ - Method (EPNP) - { - Store(0x87, SIOI) - Store(0x01, SIOI) - Store(0x55, SIOI) - Store(0x55, SIOI) /* 8718 magic number */ - } - /* Exit the 8718 MB PnP Mode */ - Method (XPNP) - { - Store (0x02, SIOI) - Store (0x02, SIOD) - } - /* - * Keyboard PME is routed to SB700 Gevent3. We can wake - * up the system by pressing the key. - */ - Method (SIOS, 1) - { - /* We only enable KBD PME for S5. */ - If (LLess (Arg0, 0x05)) - { - EPNP() - /* DBGO("8718F\n") */ - - Store (0x4, LDN) - Store (One, ACTR) /* Enable EC */ - /* - Store (0x4, LDN) - Store (0x04, APC4) - */ /* falling edge. which mode? Not sure. */ - - Store (0x4, LDN) - Store (0x08, APC1) /* clear PME status, Use 0x18 for mouse & KBD */ - Store (0x4, LDN) - Store (0x08, APC0) /* enable PME, Use 0x18 for mouse & KBD */ - - XPNP() - } - } - Method (SIOW, 0) - { - EPNP() - Store (0x4, LDN) - Store (Zero, APC0) /* disable keyboard PME */ - Store (0x4, LDN) - Store (0xFF, APC1) /* clear keyboard PME status */ - XPNP() - } - - Name(CRES, ResourceTemplate() { - IO(Decode16, 0x0CF8, 0x0CF8, 1, 8) - - WORDIO(ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, - 0x0000, /* address granularity */ - 0x0000, /* range minimum */ - 0x0CF7, /* range maximum */ - 0x0000, /* translation */ - 0x0CF8 /* length */ - ) - - WORDIO(ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, - 0x0000, /* address granularity */ - 0x0D00, /* range minimum */ - 0xFFFF, /* range maximum */ - 0x0000, /* translation */ - 0xF300 /* length */ - ) - - Memory32Fixed(READWRITE, 0, 0xA0000, BSMM) - Memory32Fixed(READONLY, 0x000A0000, 0x00020000, VGAM) /* VGA memory space */ - Memory32Fixed(READONLY, 0x000C0000, 0x00020000, EMM1) /* Assume C0000-E0000 empty */ - Memory32Fixed(READONLY, 0x000E0000, 0x00020000, RDBS) /* BIOS ROM area */ - - /* DRAM Memory from 1MB to TopMem */ - Memory32Fixed(READWRITE, 0x00100000, 0, DMLO) /* 1MB to TopMem */ - - /* BIOS space just below 4GB */ - DWORDMemory( - ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite, - 0x00, /* Granularity */ - 0x00000000, /* Min */ - 0x00000000, /* Max */ - 0x00000000, /* Translation */ - 0x00000001, /* Max-Min, RLEN */ - ,, - PCBM - ) - - /* DRAM memory from 4GB to TopMem2 */ - QWORDMemory(ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite, - 0x00000000, /* Granularity */ - 0x00000000, /* Min */ - 0x00000000, /* Max */ - 0x00000000, /* Translation */ - 0x00000001, /* Max-Min, RLEN */ - ,, - DMHI - ) - - /* BIOS space just below 16EB */ - QWORDMemory(ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite, - 0x00000000, /* Granularity */ - 0x00000000, /* Min */ - 0x00000000, /* Max */ - 0x00000000, /* Translation */ - 0x00000001, /* Max-Min, RLEN */ - ,, - PEBM - ) - - }) /* End Name(_SB.PCI0.CRES) */ - - Method(_CRS, 0) { - /* DBGO("\\_SB\\PCI0\\_CRS\n") */ - - CreateDWordField(CRES, ^EMM1._BAS, EM1B) - CreateDWordField(CRES, ^EMM1._LEN, EM1L) - CreateDWordField(CRES, ^DMLO._BAS, DMLB) - CreateDWordField(CRES, ^DMLO._LEN, DMLL) - CreateDWordField(CRES, ^PCBM._MIN, PBMB) - CreateDWordField(CRES, ^PCBM._LEN, PBML) - - CreateQWordField(CRES, ^DMHI._MIN, DMHB) - CreateQWordField(CRES, ^DMHI._LEN, DMHL) - CreateQWordField(CRES, ^PEBM._MIN, EBMB) - CreateQWordField(CRES, ^PEBM._LEN, EBML) - - If(LGreater(LOMH, 0xC0000)){ - Store(0xC0000, EM1B) /* Hole above C0000 and below E0000 */ - Subtract(LOMH, 0xC0000, EM1L) /* subtract start, assumes allocation from C0000 going up */ - } - - /* Set size of memory from 1MB to TopMem */ - Subtract(TOM1, 0x100000, DMLL) - - /* - * If(LNotEqual(TOM2, 0x00000000)){ - * Store(0x100000000,DMHB) DRAM from 4GB to TopMem2 - * ShiftLeft(TOM2, 20, Local0) - * Subtract(Local0, 0x100000000, DMHL) - * } - */ - - /* If there is no memory above 4GB, put the BIOS just below 4GB */ - If(LEqual(TOM2, 0x00000000)){ - Store(PBAD,PBMB) /* Reserve the "BIOS" space */ - Store(PBLN,PBML) - } - Else { /* Otherwise, put the BIOS just below 16EB */ - ShiftLeft(PBAD,16,EBMB) /* Reserve the "BIOS" space */ - Store(PBLN,EBML) - } - - Return(CRES) /* note to change the Name buffer */ - } /* end of Method(_SB.PCI0._CRS) */ - - /* - * - * FIRST METHOD CALLED UPON BOOT - * - * 1. If debugging, print current OS and ACPI interpreter. - * 2. Get PCI Interrupt routing from ACPI VSM, this - * value is based on user choice in BIOS setup. - */ - Method(_INI, 0) { - /* DBGO("\\_SB\\_INI\n") */ - /* DBGO(" DSDT.ASL code from ") */ - /* DBGO(__DATE__) */ - /* DBGO(" ") */ - /* DBGO(__TIME__) */ - /* DBGO("\n Sleep states supported: ") */ - /* DBGO("\n") */ - /* DBGO(" \\_OS=") */ - /* DBGO(\_OS) */ - /* DBGO("\n \\_REV=") */ - /* DBGO(\_REV) */ - /* DBGO("\n") */ - - /* Determine the OS we're running on */ - OSFL() - - /* On older chips, clear PciExpWakeDisEn */ - /*if (LLessEqual(\SBRI, 0x13)) { - * Store(0,\PWDE) - * } - */ - } /* End Method(_SB._INI) */ - } /* End Device(PCI0) */ - - Device(PWRB) { /* Start Power button device */ - Name(_HID, EISAID("PNP0C0C")) - Name(_UID, 0xAA) - Name(_PRW, Package () {3, 0x04}) /* wake from S1-S4 */ - Name(_STA, 0x0B) /* sata is invisible */ - } - } /* End \_SB scope */ - - Scope(\_SI) { - Method(_SST, 1) { - /* DBGO("\\_SI\\_SST\n") */ - /* DBGO(" New Indicator state: ") */ - /* DBGO(Arg0) */ - /* DBGO("\n") */ - } - } /* End Scope SI */ - - #include - - /* THERMAL */ - Scope(\_TZ) { - Name (KELV, 2732) - Name (THOT, 800) - Name (TCRT, 850) - - ThermalZone(TZ00) { - Method(_AC0,0) { /* Active Cooling 0 (0=highest fan speed) */ - /* DBGO("\\_TZ\\TZ00\\_AC0\n") */ - Return(Add(0, 2730)) - } - Method(_AL0,0) { /* Returns package of cooling device to turn on */ - /* DBGO("\\_TZ\\TZ00\\_AL0\n") */ - Return(Package() {\_TZ.TZ00.FAN0}) - } - Device (FAN0) { - Name(_HID, EISAID("PNP0C0B")) - Name(_PR0, Package() {PFN0}) - } - - PowerResource(PFN0,0,0) { - Method(_STA) { - Store(0xF,Local0) - Return(Local0) - } - Method(_ON) { - /* DBGO("\\_TZ\\TZ00\\FAN0 _ON\n") */ - } - Method(_OFF) { - /* DBGO("\\_TZ\\TZ00\\FAN0 _OFF\n") */ - } - } - - Method(_HOT,0) { /* return hot temp in tenths degree Kelvin */ - /* DBGO("\\_TZ\\TZ00\\_HOT\n") */ - Return (Add (THOT, KELV)) - } - Method(_CRT,0) { /* return critical temp in tenths degree Kelvin */ - /* DBGO("\\_TZ\\TZ00\\_CRT\n") */ - Return (Add (TCRT, KELV)) - } - Method(_TMP,0) { /* return current temp of this zone */ - Store (SMBR (0x07, 0x4C,, 0x00), Local0) - If (LGreater (Local0, 0x10)) { - Store (Local0, Local1) - } - Else { - Add (Local0, THOT, Local0) - Return (Add (400, KELV)) - } - - Store (SMBR (0x07, 0x4C, 0x01), Local0) - /* only the two MSBs in the external temperature low byte are used, resolution 0.25. We ignore it */ - /* Store (SMBR (0x07, 0x4C, 0x10), Local2) */ - If (LGreater (Local0, 0x10)) { - If (LGreater (Local0, Local1)) { - Store (Local0, Local1) - } - - Multiply (Local1, 10, Local1) - Return (Add (Local1, KELV)) - } - Else { - Add (Local0, THOT, Local0) - Return (Add (400 , KELV)) - } - } /* end of _TMP */ - } /* end of TZ00 */ - } -} -/* End of ASL file */ diff --git a/src/mainboard/gigabyte/ma785gmt/get_bus_conf.c b/src/mainboard/gigabyte/ma785gmt/get_bus_conf.c deleted file mode 100644 index 5c53476a11..0000000000 --- a/src/mainboard/gigabyte/ma785gmt/get_bus_conf.c +++ /dev/null @@ -1,42 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2010 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include -#include -#include - -/* Global variables for MB layouts and these will be shared by irqtable mptable -* and acpi_tables busnum is default. -*/ -u32 apicid_sb700; - -void get_bus_conf(void) -{ - u32 apicid_base; - - get_default_pci1234(1); - - sysconf.sbdn = (sysconf.hcdn[0] & 0xff); - pirq_router_bus = (sysconf.pci1234[0] >> 16) & 0xff; - - /* I/O APICs: APIC ID Version State Address */ - if (CONFIG(LOGICAL_CPUS)) - apicid_base = get_apicid_base(1); - else - apicid_base = CONFIG_MAX_PHYSICAL_CPUS; - apicid_sb700 = apicid_base + 0; -} diff --git a/src/mainboard/gigabyte/ma785gmt/irq_tables.c b/src/mainboard/gigabyte/ma785gmt/irq_tables.c deleted file mode 100644 index 0f7192514e..0000000000 --- a/src/mainboard/gigabyte/ma785gmt/irq_tables.c +++ /dev/null @@ -1,102 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2010 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include -#include -#include - -#include - -static void write_pirq_info(struct irq_info *pirq_info, u8 bus, u8 devfn, - u8 link0, u16 bitmap0, u8 link1, u16 bitmap1, - u8 link2, u16 bitmap2, u8 link3, u16 bitmap3, - u8 slot, u8 rfu) -{ - pirq_info->bus = bus; - pirq_info->devfn = devfn; - pirq_info->irq[0].link = link0; - pirq_info->irq[0].bitmap = bitmap0; - pirq_info->irq[1].link = link1; - pirq_info->irq[1].bitmap = bitmap1; - pirq_info->irq[2].link = link2; - pirq_info->irq[2].bitmap = bitmap2; - pirq_info->irq[3].link = link3; - pirq_info->irq[3].bitmap = bitmap3; - pirq_info->slot = slot; - pirq_info->rfu = rfu; -} - - -unsigned long write_pirq_routing_table(unsigned long addr) -{ - struct irq_routing_table *pirq; - struct irq_info *pirq_info; - u32 slot_num; - u8 *v; - - u8 sum = 0; - int i; - - /* Align the table to be 16 byte aligned. */ - addr += 15; - addr &= ~15; - - /* This table must be between 0xf0000 & 0x100000 */ - printk(BIOS_INFO, "Writing IRQ routing tables to 0x%lx...", addr); - - pirq = (void *)(addr); - v = (u8 *) (addr); - - pirq->signature = PIRQ_SIGNATURE; - pirq->version = PIRQ_VERSION; - - pirq->rtr_bus = pirq_router_bus; - pirq->rtr_devfn = PCI_DEVFN(0x14, 4); - - pirq->exclusive_irqs = 0; - - pirq->rtr_vendor = 0x1002; - pirq->rtr_device = 0x4384; - - pirq->miniport_data = 0; - - memset(pirq->rfu, 0, sizeof(pirq->rfu)); - - pirq_info = (void *)(&pirq->checksum + 1); - slot_num = 0; - - /* pci bridge */ - write_pirq_info(pirq_info, pirq_router_bus, PCI_DEVFN(0x14, 4), - 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, - 0); - pirq_info++; - slot_num++; - - pirq->size = 32 + 16 * slot_num; - - for (i = 0; i < pirq->size; i++) - sum += v[i]; - - sum = pirq->checksum - sum; - if (sum != pirq->checksum) { - pirq->checksum = sum; - } - - printk(BIOS_INFO, "write_pirq_routing_table done.\n"); - - return (unsigned long)pirq_info; -} diff --git a/src/mainboard/gigabyte/ma785gmt/mainboard.c b/src/mainboard/gigabyte/ma785gmt/mainboard.c deleted file mode 100644 index 899ca28ab4..0000000000 --- a/src/mainboard/gigabyte/ma785gmt/mainboard.c +++ /dev/null @@ -1,244 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2010 Wang Qing Pei - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include -#include -#include -#include -#include -#include - -#define ADT7461_ADDRESS 0x4C -#define ARA_ADDRESS 0x0C /* Alert Response Address */ - -#define ADT7461_read_byte(address) \ - do_smbus_read_byte(SMBUS_IO_BASE, ADT7461_ADDRESS, address) -#define ARA_read_byte(address) \ - do_smbus_read_byte(SMBUS_IO_BASE, ARA_ADDRESS, address) -#define ADT7461_write_byte(address, val) \ - do_smbus_write_byte(SMBUS_IO_BASE, ADT7461_ADDRESS, address, val) - -void set_pcie_dereset(void) -{ - u8 byte; - u16 word; - struct device *sm_dev; - /* set 0 to bit1 :disable GPM9 as SLP_S2 output */ - /* set 0 to bit2 :disable GPM8 as AZ_RST output */ - byte = pm_ioread(0x8d); - byte &= ~((1 << 1) | (1 << 2)); - pm_iowrite(0x8d, byte); - - /* set the GPM8 and GPM9 output enable and the value to 1 */ - byte = pm_ioread(0x94); - byte &= ~((1 << 2) | (1 << 3)); - byte |= ((1 << 0) | (1 << 1)); - pm_iowrite(0x94, byte); - - /* set the GPIO65 output enable and the value is 1 */ - sm_dev = pcidev_on_root(0x14, 0); - word = pci_read_config16(sm_dev, 0x7e); - word |= (1 << 0); - word &= ~(1 << 4); - pci_write_config16(sm_dev, 0x7e, word); -} - -void set_pcie_reset(void) -{ - u8 byte; - u16 word; - struct device *sm_dev; - - /* set 0 to bit1 :disable GPM9 as SLP_S2 output */ - /* set 0 to bit2 :disable GPM8 as AZ_RST output */ - byte = pm_ioread(0x8d); - byte &= ~((1 << 1) | (1 << 2)); - pm_iowrite(0x8d, byte); - - /* set the GPM8 and GPM9 output enable and the value to 0 */ - byte = pm_ioread(0x94); - byte &= ~((1 << 2) | (1 << 3)); - byte &= ~((1 << 0) | (1 << 1)); - pm_iowrite(0x94, byte); - - /* set the GPIO65 output enable and the value is 0 */ - sm_dev = pcidev_on_root(0x14, 0); - word = pci_read_config16(sm_dev, 0x7e); - word &= ~(1 << 0); - word &= ~(1 << 4); - pci_write_config16(sm_dev, 0x7e, word); -} - -/* - * justify the dev3 is exist or not - */ -int is_dev3_present(void) -{ - u16 word; - struct device *sm_dev; - - /* access the smbus extended register */ - sm_dev = pcidev_on_root(0x14, 0); - - /* put the GPIO68 output to tristate */ - word = pci_read_config16(sm_dev, 0x7e); - word |= 1 << 6; - pci_write_config16(sm_dev, 0x7e,word); - - /* read the GPIO68 input status */ - word = pci_read_config16(sm_dev, 0x7e); - - return !(word & (1 << 10)); -} - -/* - * set gpio40 gfx - */ -static void set_gpio40_gfx(void) -{ - u8 byte; -// u16 word; - u32 dword; - struct device *sm_dev; - /* disable the GPIO40 as CLKREQ2# function */ - byte = pm_ioread(0xd3); - byte &= ~(1 << 7); - pm_iowrite(0xd3, byte); - - /* disable the GPIO40 as CLKREQ3# function */ - byte = pm_ioread(0xd4); - byte &= ~(1 << 0); - pm_iowrite(0xd4, byte); - - /* enable pull up for GPIO68 */ - byte = pm2_ioread(0xf1); - byte &= ~(1 << 4); - pm2_iowrite(0xf1, byte); - - /* access the smbus extended register */ - sm_dev = pcidev_on_root(0x14, 0); - - /*if the dev3 is present, set the gfx to 2x8 lanes*/ - /*otherwise set the gfx to 1x16 lanes*/ - if(is_dev3_present()){ - - printk(BIOS_INFO, "Dev3 is present. GFX Configuration is Two x8 slots\n"); - /* when the gpio40 is configured as GPIO, this will enable the output */ - pci_write_config32(sm_dev, 0xf8, 0x4); - dword = pci_read_config32(sm_dev, 0xfc); - dword &= ~(1 << 10); - - /* When the gpio40 is configured as GPIO, this will represent the output value*/ - /* 1 :enable two x8 , 0 : master slot enable only */ - dword |= (1 << 26); - pci_write_config32(sm_dev, 0xfc, dword); - - }else{ - printk(BIOS_INFO, "Dev3 is not present. GFX Configuration is One x16 slot\n"); - /* when the gpio40 is configured as GPIO, this will enable the output */ - pci_write_config32(sm_dev, 0xf8, 0x4); - dword = pci_read_config32(sm_dev, 0xfc); - dword &= ~(1 << 10); - - /* When the gpio40 is configured as GPIO, this will represent the output value*/ - /* 1 :enable two x8 , 0 : master slot enable only */ - dword &= ~(1 << 26); - pci_write_config32(sm_dev, 0xfc, dword); - } -} - -/* - * set thermal config - */ -static void set_thermal_config(void) -{ - u8 byte; - u16 word; - struct device *sm_dev; - - /* set ADT 7461 */ - ADT7461_write_byte(0x0B, 0x50); /* Local Temperature Hight limit */ - ADT7461_write_byte(0x0C, 0x00); /* Local Temperature Low limit */ - ADT7461_write_byte(0x0D, 0x50); /* External Temperature Hight limit High Byte */ - ADT7461_write_byte(0x0E, 0x00); /* External Temperature Low limit High Byte */ - - ADT7461_write_byte(0x19, 0x55); /* External THERM limit */ - ADT7461_write_byte(0x20, 0x55); /* Local THERM limit */ - - byte = ADT7461_read_byte(0x02); /* read status register to clear it */ - ARA_read_byte(0x05); /* A hardware alert can only be cleared by the master sending an ARA as a read command */ - printk(BIOS_INFO, "Init adt7461 end , status 0x02 %02x\n", byte); - - /* sb700 settings for thermal config */ - /* set SB700 GPIO 64 to GPIO with pull-up */ - byte = pm2_ioread(0x42); - byte &= 0x3f; - pm2_iowrite(0x42, byte); - - /* set GPIO 64 to input */ - sm_dev = pcidev_on_root(0x14, 0); - word = pci_read_config16(sm_dev, 0x56); - word |= 1 << 7; - pci_write_config16(sm_dev, 0x56, word); - - /* set GPIO 64 internal pull-up */ - byte = pm2_ioread(0xf0); - byte &= 0xee; - pm2_iowrite(0xf0, byte); - - /* set Talert to be active low */ - byte = pm_ioread(0x67); - byte &= ~(1 << 5); - pm_iowrite(0x67, byte); - - /* set Talert to generate ACPI event */ - byte = pm_ioread(0x3c); - byte &= 0xf3; - pm_iowrite(0x3c, byte); - - /* THERMTRIP pin */ - /* byte = pm_ioread(0x68); - * byte |= 1 << 3; - * pm_iowrite(0x68, byte); - * - * byte = pm_ioread(0x55); - * byte |= 1 << 0; - * pm_iowrite(0x55, byte); - * - * byte = pm_ioread(0x67); - * byte &= ~(1 << 6); - * pm_iowrite(0x67, byte); - */ -} - -/************************************************* -* enable the dedicated function in ma785gmt board. -* This function called early than rs780_enable. -*************************************************/ -static void mainboard_enable(struct device *dev) -{ - printk(BIOS_INFO, "Mainboard MA785GMT-UD2H Enable. dev=0x%p\n", dev); - - set_pcie_dereset(); - /* get_ide_dma66(); */ - set_thermal_config(); - set_gpio40_gfx(); -} - -struct chip_operations mainboard_ops = { - .enable_dev = mainboard_enable, -}; diff --git a/src/mainboard/gigabyte/ma785gmt/mptable.c b/src/mainboard/gigabyte/ma785gmt/mptable.c deleted file mode 100644 index 876e7ee578..0000000000 --- a/src/mainboard/gigabyte/ma785gmt/mptable.c +++ /dev/null @@ -1,103 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2010 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include -#include -#include - - -extern u32 apicid_sb700; - - -static void *smp_write_config_table(void *v) -{ - struct mp_config_table *mc; - int bus_isa; - - mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); - - mptable_init(mc, LOCAL_APIC_ADDR); - - smp_write_processors(mc); - - mptable_write_buses(mc, NULL, &bus_isa); - - /* I/O APICs: APIC ID Version State Address */ - { - struct device *dev; - u32 dword; - u8 byte; - - dev = - dev_find_slot(pirq_router_bus, - PCI_DEVFN(0x14, 0)); - if (dev) { - dword = pci_read_config32(dev, 0x74) & 0xfffffff0; - smp_write_ioapic(mc, apicid_sb700, - 0x11,(void *) dword); - - /* Initialize interrupt mapping */ - /* aza */ - byte = pci_read_config8(dev, 0x63); - byte &= 0xf8; - byte |= 0; /* 0: INTA, ...., 7: INTH */ - pci_write_config8(dev, 0x63, byte); - - /* SATA */ - dword = pci_read_config32(dev, 0xac); - dword &= ~(7 << 26); - dword |= 6 << 26; /* 0: INTA, ...., 7: INTH */ - /* dword |= 1 << 22; PIC and APIC co exists */ - pci_write_config32(dev, 0xac, dword); - - /* - * 00:12.0: PROG SATA : INT F - * 00:13.0: INTA USB_0 - * 00:13.1: INTB USB_1 - * 00:13.2: INTC USB_2 - * 00:13.3: INTD USB_3 - * 00:13.4: INTC USB_4 - * 00:13.5: INTD USB2 - * 00:14.1: INTA IDE - * 00:14.2: Prog HDA : INT E - * 00:14.5: INTB ACI - * 00:14.6: INTB MCI - */ - } - } - - /* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ -#define IO_LOCAL_INT(type, intr, apicid, pin) \ - smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin)); - - mptable_add_isa_interrupts(mc, bus_isa, apicid_sb700, 0); - - /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ - IO_LOCAL_INT(mp_ExtINT, 0x0, MP_APIC_ALL, 0x0); - IO_LOCAL_INT(mp_NMI, 0x0, MP_APIC_ALL, 0x1); - /* There is no extension information... */ - - /* Compute the checksums */ - return mptable_finalize(mc); -} - -unsigned long write_smp_table(unsigned long addr) -{ - void *v; - v = smp_write_floating_table(addr, 0); - return (unsigned long)smp_write_config_table(v); -} diff --git a/src/mainboard/gigabyte/ma785gmt/resourcemap.c b/src/mainboard/gigabyte/ma785gmt/resourcemap.c deleted file mode 100644 index 80d2d9d05c..0000000000 --- a/src/mainboard/gigabyte/ma785gmt/resourcemap.c +++ /dev/null @@ -1,279 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2010 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - - - -#include -#include - -void setup_mb_resource_map(void) -{ - static const unsigned int register_values[] = { - /* Careful set limit registers before base registers which contain the enables */ - /* DRAM Limit i Registers - * F1:0x44 i = 0 - * F1:0x4C i = 1 - * F1:0x54 i = 2 - * F1:0x5C i = 3 - * F1:0x64 i = 4 - * F1:0x6C i = 5 - * F1:0x74 i = 6 - * F1:0x7C i = 7 - * [ 2: 0] Destination Node ID - * 000 = Node 0 - * 001 = Node 1 - * 010 = Node 2 - * 011 = Node 3 - * 100 = Node 4 - * 101 = Node 5 - * 110 = Node 6 - * 111 = Node 7 - * [ 7: 3] Reserved - * [10: 8] Interleave select - * specifies the values of A[14:12] to use with interleave enable. - * [15:11] Reserved - * [31:16] DRAM Limit Address i Bits 39-24 - * This field defines the upper address bits of a 40 bit address - * that define the end of the DRAM region. - */ -// ADDRMAP_REG(0x44), 0x0000f8f8, 0x00000000, // Don't touch it, we need it for CONFIG_CAR_FAM10 - ADDRMAP_REG(0x4C), 0x0000f8f8, 0x00000001, - ADDRMAP_REG(0x54), 0x0000f8f8, 0x00000002, - ADDRMAP_REG(0x5C), 0x0000f8f8, 0x00000003, - ADDRMAP_REG(0x64), 0x0000f8f8, 0x00000004, - ADDRMAP_REG(0x6C), 0x0000f8f8, 0x00000005, - ADDRMAP_REG(0x74), 0x0000f8f8, 0x00000006, - ADDRMAP_REG(0x7C), 0x0000f8f8, 0x00000007, - /* DRAM Base i Registers - * F1:0x40 i = 0 - * F1:0x48 i = 1 - * F1:0x50 i = 2 - * F1:0x58 i = 3 - * F1:0x60 i = 4 - * F1:0x68 i = 5 - * F1:0x70 i = 6 - * F1:0x78 i = 7 - * [ 0: 0] Read Enable - * 0 = Reads Disabled - * 1 = Reads Enabled - * [ 1: 1] Write Enable - * 0 = Writes Disabled - * 1 = Writes Enabled - * [ 7: 2] Reserved - * [10: 8] Interleave Enable - * 000 = No interleave - * 001 = Interleave on A[12] (2 nodes) - * 010 = reserved - * 011 = Interleave on A[12] and A[14] (4 nodes) - * 100 = reserved - * 101 = reserved - * 110 = reserved - * 111 = Interleve on A[12] and A[13] and A[14] (8 nodes) - * [15:11] Reserved - * [13:16] DRAM Base Address i Bits 39-24 - * This field defines the upper address bits of a 40-bit address - * that define the start of the DRAM region. - */ -// ADDRMAP_REG(0x40), 0x0000f8fc, 0x00000000,// don't touch it, we need it for CONFIG_CAR_FAM10 - ADDRMAP_REG(0x48), 0x0000f8fc, 0x00000000, - ADDRMAP_REG(0x50), 0x0000f8fc, 0x00000000, - ADDRMAP_REG(0x58), 0x0000f8fc, 0x00000000, - ADDRMAP_REG(0x60), 0x0000f8fc, 0x00000000, - ADDRMAP_REG(0x68), 0x0000f8fc, 0x00000000, - ADDRMAP_REG(0x70), 0x0000f8fc, 0x00000000, - ADDRMAP_REG(0x78), 0x0000f8fc, 0x00000000, - - /* Memory-Mapped I/O Limit i Registers - * F1:0x84 i = 0 - * F1:0x8C i = 1 - * F1:0x94 i = 2 - * F1:0x9C i = 3 - * F1:0xA4 i = 4 - * F1:0xAC i = 5 - * F1:0xB4 i = 6 - * F1:0xBC i = 7 - * [ 2: 0] Destination Node ID - * 000 = Node 0 - * 001 = Node 1 - * 010 = Node 2 - * 011 = Node 3 - * 100 = Node 4 - * 101 = Node 5 - * 110 = Node 6 - * 111 = Node 7 - * [ 3: 3] Reserved - * [ 5: 4] Destination Link ID - * 00 = Link 0 - * 01 = Link 1 - * 10 = Link 2 - * 11 = Reserved - * [ 6: 6] Reserved - * [ 7: 7] Non-Posted - * 0 = CPU writes may be posted - * 1 = CPU writes must be non-posted - * [31: 8] Memory-Mapped I/O Limit Address i (39-16) - * This field defines the upp address bits of a 40-bit address that - * defines the end of a memory-mapped I/O region n - */ - ADDRMAP_REG(0x84), 0x00000048, 0x00000000, - ADDRMAP_REG(0x8C), 0x00000048, 0x00000000, - ADDRMAP_REG(0x94), 0x00000048, 0x00000000, - ADDRMAP_REG(0x9C), 0x00000048, 0x00000000, - ADDRMAP_REG(0xA4), 0x00000048, 0x00000000, - ADDRMAP_REG(0xAC), 0x00000048, 0x00000000, - ADDRMAP_REG(0xB4), 0x00000048, 0x00000000, -// ADDRMAP_REG(0xBC), 0x00000048, 0x00ffff00, - - /* Memory-Mapped I/O Base i Registers - * F1:0x80 i = 0 - * F1:0x88 i = 1 - * F1:0x90 i = 2 - * F1:0x98 i = 3 - * F1:0xA0 i = 4 - * F1:0xA8 i = 5 - * F1:0xB0 i = 6 - * F1:0xB8 i = 7 - * [ 0: 0] Read Enable - * 0 = Reads disabled - * 1 = Reads Enabled - * [ 1: 1] Write Enable - * 0 = Writes disabled - * 1 = Writes Enabled - * [ 2: 2] Cpu Disable - * 0 = Cpu can use this I/O range - * 1 = Cpu requests do not use this I/O range - * [ 3: 3] Lock - * 0 = base/limit registers i are read/write - * 1 = base/limit registers i are read-only - * [ 7: 4] Reserved - * [31: 8] Memory-Mapped I/O Base Address i (39-16) - * This field defines the upper address bits of a 40bit address - * that defines the start of memory-mapped I/O region i - */ - ADDRMAP_REG(0x80), 0x000000f0, 0x00000000, - ADDRMAP_REG(0x88), 0x000000f0, 0x00000000, - ADDRMAP_REG(0x90), 0x000000f0, 0x00000000, - ADDRMAP_REG(0x98), 0x000000f0, 0x00000000, - ADDRMAP_REG(0xA0), 0x000000f0, 0x00000000, - ADDRMAP_REG(0xA8), 0x000000f0, 0x00000000, - ADDRMAP_REG(0xB0), 0x000000f0, 0x00000000, -// ADDRMAP_REG(0xB8), 0x000000f0, 0x00fc0003, - - /* PCI I/O Limit i Registers - * F1:0xC4 i = 0 - * F1:0xCC i = 1 - * F1:0xD4 i = 2 - * F1:0xDC i = 3 - * [ 2: 0] Destination Node ID - * 000 = Node 0 - * 001 = Node 1 - * 010 = Node 2 - * 011 = Node 3 - * 100 = Node 4 - * 101 = Node 5 - * 110 = Node 6 - * 111 = Node 7 - * [ 3: 3] Reserved - * [ 5: 4] Destination Link ID - * 00 = Link 0 - * 01 = Link 1 - * 10 = Link 2 - * 11 = reserved - * [11: 6] Reserved - * [24:12] PCI I/O Limit Address i - * This field defines the end of PCI I/O region n - * [31:25] Reserved - */ -// ADDRMAP_REG(0xC4), 0xFE000FC8, 0x01fff000, - ADDRMAP_REG(0xCC), 0xFE000FC8, 0x00000000, - ADDRMAP_REG(0xD4), 0xFE000FC8, 0x00000000, - ADDRMAP_REG(0xDC), 0xFE000FC8, 0x00000000, - - /* PCI I/O Base i Registers - * F1:0xC0 i = 0 - * F1:0xC8 i = 1 - * F1:0xD0 i = 2 - * F1:0xD8 i = 3 - * [ 0: 0] Read Enable - * 0 = Reads Disabled - * 1 = Reads Enabled - * [ 1: 1] Write Enable - * 0 = Writes Disabled - * 1 = Writes Enabled - * [ 3: 2] Reserved - * [ 4: 4] VGA Enable - * 0 = VGA matches Disabled - * 1 = matches all address < 64K and where A[9:0] is in the - * range 3B0-3BB or 3C0-3DF independen of the base & limit registers - * [ 5: 5] ISA Enable - * 0 = ISA matches Disabled - * 1 = Blocks address < 64K and in the last 768 bytes of eack 1K block - * from matching agains this base/limit pair - * [11: 6] Reserved - * [24:12] PCI I/O Base i - * This field defines the start of PCI I/O region n - * [31:25] Reserved - */ -// ADDRMAP_REG(0xC0), 0xFE000FCC, 0x00000003, - ADDRMAP_REG(0xC8), 0xFE000FCC, 0x00000000, - ADDRMAP_REG(0xD0), 0xFE000FCC, 0x00000000, - ADDRMAP_REG(0xD8), 0xFE000FCC, 0x00000000, - - /* Config Base and Limit i Registers - * F1:0xE0 i = 0 - * F1:0xE4 i = 1 - * F1:0xE8 i = 2 - * F1:0xEC i = 3 - * [ 0: 0] Read Enable - * 0 = Reads Disabled - * 1 = Reads Enabled - * [ 1: 1] Write Enable - * 0 = Writes Disabled - * 1 = Writes Enabled - * [ 2: 2] Device Number Compare Enable - * 0 = The ranges are based on bus number - * 1 = The ranges are ranges of devices on bus 0 - * [ 3: 3] Reserved - * [ 6: 4] Destination Node - * 000 = Node 0 - * 001 = Node 1 - * 010 = Node 2 - * 011 = Node 3 - * 100 = Node 4 - * 101 = Node 5 - * 110 = Node 6 - * 111 = Node 7 - * [ 7: 7] Reserved - * [ 9: 8] Destination Link - * 00 = Link 0 - * 01 = Link 1 - * 10 = Link 2 - * 11 - Reserved - * [15:10] Reserved - * [23:16] Bus Number Base i - * This field defines the lowest bus number in configuration region i - * [31:24] Bus Number Limit i - * This field defines the highest bus number in configuration regin i - */ -// ADDRMAP_REG(0xE0), 0x0000FC88, 0x06000003, // AMD 8111 on link0 of CPU 0 - ADDRMAP_REG(0xE4), 0x0000FC88, 0x00000000, - ADDRMAP_REG(0xE8), 0x0000FC88, 0x00000000, - ADDRMAP_REG(0xEC), 0x0000FC88, 0x00000000, - }; - - int max; - max = ARRAY_SIZE(register_values); - setup_resource_map(register_values, max); -} diff --git a/src/mainboard/gigabyte/ma785gmt/romstage.c b/src/mainboard/gigabyte/ma785gmt/romstage.c deleted file mode 100644 index 384eccdb11..0000000000 --- a/src/mainboard/gigabyte/ma785gmt/romstage.c +++ /dev/null @@ -1,226 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2010 Wang Qing Pei - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -//#define SYSTEM_TYPE 0 /* SERVER */ -#define SYSTEM_TYPE 1 /* DESKTOP */ -//#define SYSTEM_TYPE 2 /* MOBILE */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include "cpu/amd/quadcore/quadcore.c" - -#define SERIAL_DEV PNP_DEV(0x2e, IT8718F_SP1) -#define GPIO_DEV PNP_DEV(0x2e, IT8718F_GPIO) - -int spd_read_byte(unsigned int device, unsigned int address); - - -int spd_read_byte(u32 device, u32 address) -{ - return do_smbus_read_byte(SMBUS_IO_BASE, device, address); -} - -void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) -{ - struct sys_info *sysinfo = get_sysinfo(); - static const u8 spd_addr[] = {RC00, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, }; - u32 bsp_apicid = 0, val; - msr_t msr; - - timestamp_init(timestamp_get()); - timestamp_add_now(TS_START_ROMSTAGE); - - if (!cpu_init_detectedx && boot_cpu()) { - /* Nothing special needs to be done to find bus 0 */ - /* Allow the HT devices to be found */ - /* mov bsp to bus 0xff when > 8 nodes */ - set_bsp_node_CHtExtNodeCfgEn(); - enumerate_ht_chain(); - sb7xx_51xx_pci_port80(); - } - - post_code(0x30); - - if (bist == 0) { - bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo); /* mmconf is inited in init_cpus */ - /* All cores run this but the BSP(node0,core0) is the only core that returns. */ - } - - post_code(0x32); - - enable_rs780_dev8(); - sb7xx_51xx_lpc_init(); - - ite_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); - it8718f_disable_reboot(GPIO_DEV); - console_init(); - - /* Halt if there was a built in self test failure */ - report_bist_failure(bist); - - // Load MPB - val = cpuid_eax(1); - printk(BIOS_DEBUG, "BSP Family_Model: %08x\n", val); - printk(BIOS_DEBUG, "*sysinfo range: [%p,%p]\n",sysinfo,sysinfo+1); - printk(BIOS_DEBUG, "bsp_apicid = %02x\n", bsp_apicid); - printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx); - - /* Setup sysinfo defaults */ - set_sysinfo_in_ram(0); - - update_microcode(val); - - post_code(0x33); - - cpuSetAMDMSR(0); - post_code(0x34); - - amd_ht_init(sysinfo); - post_code(0x35); - - /* Setup nodes PCI space and start core 0 AP init. */ - finalize_node_setup(sysinfo); - - /* Setup any mainboard PCI settings etc. */ - setup_mb_resource_map(); - post_code(0x36); - - /* wait for all the APs core0 started by finalize_node_setup. */ - /* FIXME: A bunch of cores are going to start output to serial at once. - It would be nice to fixup prink spinlocks for ROM XIP mode. - I think it could be done by putting the spinlock flag in the cache - of the BSP located right after sysinfo. - */ - wait_all_core0_started(); - -#if CONFIG(LOGICAL_CPUS) - /* Core0 on each node is configured. Now setup any additional cores. */ - printk(BIOS_DEBUG, "start_other_cores()\n"); - start_other_cores(bsp_apicid); - post_code(0x37); - wait_all_other_cores_started(bsp_apicid); -#endif - - post_code(0x38); - - /* run _early_setup before soft-reset. */ - rs780_early_setup(); - sb7xx_51xx_early_setup(); - -#if CONFIG(SET_FIDVID) - msr = rdmsr(MSR_COFVID_STS); - printk(BIOS_DEBUG, "\nBegin FIDVID MSR 0xc0010071 0x%08x 0x%08x\n", msr.hi, msr.lo); - - /* FIXME: The sb fid change may survive the warm reset and only - need to be done once.*/ - enable_fid_change_on_sb(sysinfo->sbbusn, sysinfo->sbdn); - - post_code(0x39); - - if (!warm_reset_detect(0)) { // BSP is node 0 - init_fidvid_bsp(bsp_apicid, sysinfo->nodes); - } else { - init_fidvid_stage2(bsp_apicid, 0); // BSP is node 0 - } - - post_code(0x3A); - - /* show final fid and vid */ - msr = rdmsr(MSR_COFVID_STS); - printk(BIOS_DEBUG, "End FIDVIDMSR 0xc0010071 0x%08x 0x%08x\n", msr.hi, msr.lo); -#endif - - rs780_htinit(); - - /* Reset for HT, FIDVID, PLL and errata changes to take affect. */ - if (!warm_reset_detect(0)) { - printk(BIOS_INFO, "...WARM RESET...\n\n\n"); - soft_reset(); - die("After soft_reset - shouldn't see this message!!!\n"); - } - - post_code(0x3B); - - /* It's the time to set ctrl in sysinfo now; */ - printk(BIOS_DEBUG, "fill_mem_ctrl()\n"); - fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr); - - post_code(0x40); - - raminit_amdmct(sysinfo); - - cbmem_initialize_empty(); - post_code(0x41); - - amdmct_cbmem_store_info(sysinfo); - - sb7xx_51xx_before_pci_init(); - - post_code(0x42); -} - -/** - * BOOL AMD_CB_ManualBUIDSwapList(u8 Node, u8 Link, u8 **List) - * Description: - * This routine is called every time a non-coherent chain is processed. - * BUID assignment may be controlled explicitly on a non-coherent chain. Provide a - * swap list. The first part of the list controls the BUID assignment and the - * second part of the list provides the device to device linking. Device orientation - * can be detected automatically, or explicitly. See documentation for more details. - * - * Automatic non-coherent init assigns BUIDs starting at 1 and incrementing sequentially - * based on each device's unit count. - * - * Parameters: - * @param[in] node = The node on which this chain is located - * @param[in] link = The link on the host for this chain - * @param[out] List = supply a pointer to a list - */ -BOOL AMD_CB_ManualBUIDSwapList (u8 node, u8 link, const u8 **List) -{ - static const u8 swaplist[] = { 0xFF, CONFIG_HT_CHAIN_UNITID_BASE, CONFIG_HT_CHAIN_END_UNITID_BASE, 0xFF }; - /* If the BUID was adjusted in early_ht we need to do the manual override */ - if ((CONFIG_HT_CHAIN_UNITID_BASE != 0) && (CONFIG_HT_CHAIN_END_UNITID_BASE != 0)) { - printk(BIOS_DEBUG, "AMD_CB_ManualBUIDSwapList()\n"); - if ((node == 0) && (link == 0)) { /* BSP SB link */ - *List = swaplist; - return 1; - } - } - - return 0; -} diff --git a/src/mainboard/gigabyte/ma78gm/Kconfig b/src/mainboard/gigabyte/ma78gm/Kconfig deleted file mode 100644 index fcc21ea3ba..0000000000 --- a/src/mainboard/gigabyte/ma78gm/Kconfig +++ /dev/null @@ -1,54 +0,0 @@ -if BOARD_GIGABYTE_MA78GM - -config BOARD_SPECIFIC_OPTIONS - def_bool y - select CPU_AMD_SOCKET_AM2R2 - select DIMM_DDR2 - select DIMM_REGISTERED - select NORTHBRIDGE_AMD_AMDFAM10 - select SOUTHBRIDGE_AMD_RS780 - select SOUTHBRIDGE_AMD_SB700 - select SUPERIO_ITE_IT8718F - select HAVE_OPTION_TABLE - select HAVE_PIRQ_TABLE - select HAVE_MP_TABLE - select SB_HT_CHAIN_UNITID_OFFSET_ONLY - select LIFT_BSP_APIC_ID - select HAVE_ACPI_TABLES - select BOARD_ROMSIZE_KB_1024 - select ENABLE_APIC_EXT_ID - select GFXUMA - -config MAINBOARD_DIR - string - default gigabyte/ma78gm - -config APIC_ID_OFFSET - hex - default 0x0 - -config MAINBOARD_PART_NUMBER - string - default "GA-MA78GM-US2H" - -config MAX_CPUS - int - default 8 - -config MAX_PHYSICAL_CPUS - int - default 2 - -config HT_CHAIN_END_UNITID_BASE - hex - default 0x1 - -config HT_CHAIN_UNITID_BASE - hex - default 0x0 - -config IRQ_SLOT_COUNT - int - default 11 - -endif # BOARD_GIGABYTE_MA78GM diff --git a/src/mainboard/gigabyte/ma78gm/Kconfig.name b/src/mainboard/gigabyte/ma78gm/Kconfig.name deleted file mode 100644 index 5b21fdef4a..0000000000 --- a/src/mainboard/gigabyte/ma78gm/Kconfig.name +++ /dev/null @@ -1,2 +0,0 @@ -config BOARD_GIGABYTE_MA78GM - bool "GA-MA78GM-US2H" diff --git a/src/mainboard/gigabyte/ma78gm/Makefile.inc b/src/mainboard/gigabyte/ma78gm/Makefile.inc deleted file mode 100644 index 91d4b39c32..0000000000 --- a/src/mainboard/gigabyte/ma78gm/Makefile.inc +++ /dev/null @@ -1,16 +0,0 @@ -# -# This file is part of the coreboot project. -# -# This program is free software; you can redistribute it and/or modify -# it under the terms of the GNU General Public License as published by -# the Free Software Foundation; version 2 of the License. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# - -romstage-y += resourcemap.c - -ramstage-y += get_bus_conf.c diff --git a/src/mainboard/gigabyte/ma78gm/acpi/cpstate.asl b/src/mainboard/gigabyte/ma78gm/acpi/cpstate.asl deleted file mode 100644 index acaa5bae32..0000000000 --- a/src/mainboard/gigabyte/ma78gm/acpi/cpstate.asl +++ /dev/null @@ -1,80 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2010 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -/* This file defines the processor and performance state capability - * for each core in the system. It is included into the DSDT for each - * core. It assumes that each core of the system has the same performance - * characteristics. -*/ -/* -#include -DefinitionBlock ("DSDT.AML", "DSDT", 0x01, OEM_ID, ACPI_TABLE_CREATOR, 0x00010001) - { - Scope (\_PR) { - Device (CPU0) { - Name (_HID, "ACPI0007") - Name (_UID, 0) - #include "cpstate.asl" - } - Device (CPU1) { - Name (_HID, "ACPI0007") - Name (_UID, 1) - #include "cpstate.asl" - } - Device (CPU2) { - Name (_HID, "ACPI0007") - Name (_UID, 2) - #include "cpstate.asl" - } - Device (CPU3) { - Name (_HID, "ACPI0007") - Name (_UID, 3) - #include "cpstate.asl" - } - } -*/ - /* P-state support: The maximum number of P-states supported by the */ - /* CPUs we'll use is 6. */ - /* Get from AMI BIOS. */ - Name(_PSS, Package(){ - Package () - { - 0x00000AF0, - 0x0000BF81, - 0x00000002, - 0x00000002, - 0x00000000, - 0x00000000 - }, - - Package () - { - 0x00000578, - 0x000076F2, - 0x00000002, - 0x00000002, - 0x00000001, - 0x00000001 - } - }) - - Name(_PCT, Package(){ - ResourceTemplate(){Register(FFixedHW, 0, 0, 0)}, - ResourceTemplate(){Register(FFixedHW, 0, 0, 0)} - }) - - Method(_PPC, 0){ - Return(0) - } diff --git a/src/mainboard/gigabyte/ma78gm/acpi/ide.asl b/src/mainboard/gigabyte/ma78gm/acpi/ide.asl deleted file mode 100644 index 5c155cf301..0000000000 --- a/src/mainboard/gigabyte/ma78gm/acpi/ide.asl +++ /dev/null @@ -1,240 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2010 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -/* -Scope (_SB) { - Device(PCI0) { - Device(IDEC) { - Name(_ADR, 0x00140001) - #include "ide.asl" - } - } -} -*/ - -/* Some timing tables */ -Name(UDTT, Package(){ /* Udma timing table */ - 120, 90, 60, 45, 30, 20, 15, 0 /* UDMA modes 0 -> 6 */ -}) - -Name(MDTT, Package(){ /* MWDma timing table */ - 480, 150, 120, 0 /* Legacy DMA modes 0 -> 2 */ -}) - -Name(POTT, Package(){ /* Pio timing table */ - 600, 390, 270, 180, 120, 0 /* PIO modes 0 -> 4 */ -}) - -/* Some timing register value tables */ -Name(MDRT, Package(){ /* MWDma timing register table */ - 0x77, 0x21, 0x20, 0xFF /* Legacy DMA modes 0 -> 2 */ -}) - -Name(PORT, Package(){ - 0x99, 0x47, 0x34, 0x22, 0x20, 0x99 /* PIO modes 0 -> 4 */ -}) - -OperationRegion(ICRG, PCI_Config, 0x40, 0x20) /* ide control registers */ - Field(ICRG, AnyAcc, NoLock, Preserve) -{ - PPTS, 8, /* Primary PIO Slave Timing */ - PPTM, 8, /* Primary PIO Master Timing */ - OFFSET(0x04), PMTS, 8, /* Primary MWDMA Slave Timing */ - PMTM, 8, /* Primary MWDMA Master Timing */ - OFFSET(0x08), PPCR, 8, /* Primary PIO Control */ - OFFSET(0x0A), PPMM, 4, /* Primary PIO master Mode */ - PPSM, 4, /* Primary PIO slave Mode */ - OFFSET(0x14), PDCR, 2, /* Primary UDMA Control */ - OFFSET(0x16), PDMM, 4, /* Primary UltraDMA Mode */ - PDSM, 4, /* Primary UltraDMA Mode */ -} - -Method(GTTM, 1) /* get total time*/ -{ - Store(And(Arg0, 0x0F), Local0) /* Recovery Width */ - Increment(Local0) - Store(ShiftRight(Arg0, 4), Local1) /* Command Width */ - Increment(Local1) - Return(Multiply(30, Add(Local0, Local1))) -} - -Device(PRID) -{ - Name (_ADR, Zero) - Method(_GTM, 0) - { - NAME(OTBF, Buffer(20) { /* out buffer */ - 0xFF, 0xFF, 0xFF, 0xFF, - 0xFF, 0xFF, 0xFF, 0xFF, - 0xFF, 0xFF, 0xFF, 0xFF, - 0xFF, 0xFF, 0xFF, 0xFF, 0x00, 0x00, 0x00, 0x00 - }) - - CreateDwordField(OTBF, 0, PSD0) /* PIO spd0 */ - CreateDwordField(OTBF, 4, DSD0) /* DMA spd0 */ - CreateDwordField(OTBF, 8, PSD1) /* PIO spd1 */ - CreateDwordField(OTBF, 12, DSD1) /* DMA spd1 */ - CreateDwordField(OTBF, 16, BFFG) /* buffer flags */ - - /* Just return if the channel is disabled */ - If(And(PPCR, 0x01)) { /* primary PIO control */ - Return(OTBF) - } - - /* Always tell them independent timing available and IOChannelReady used on both drives */ - Or(BFFG, 0x1A, BFFG) - - Store(GTTM(PPTM), PSD0) /* save total time of primary PIO master timming to PIO spd0 */ - Store(GTTM(PPTS), PSD1) /* save total time of primary PIO slave Timing to PIO spd1 */ - - If(And(PDCR, 0x01)) { /* It's under UDMA mode */ - Or(BFFG, 0x01, BFFG) - Store(DerefOf(Index(UDTT, PDMM)), DSD0) - } - Else { - Store(GTTM(PMTM), DSD0) /* Primary MWDMA Master Timing, DmaSpd0 */ - } - - If(And(PDCR, 0x02)) { /* It's under UDMA mode */ - Or(BFFG, 0x04, BFFG) - Store(DerefOf(Index(UDTT, PDSM)), DSD1) - } - Else { - Store(GTTM(PMTS), DSD1) /* Primary MWDMA Slave Timing, DmaSpd0 */ - } - - Return(OTBF) /* out buffer */ - } /* End Method(_GTM) */ - - Method(_STM, 3, NotSerialized) - { - NAME(INBF, Buffer(20) { /* in buffer */ - 0xFF, 0xFF, 0xFF, 0xFF, - 0xFF, 0xFF, 0xFF, 0xFF, - 0xFF, 0xFF, 0xFF, 0xFF, - 0xFF, 0xFF, 0xFF, 0xFF, 0x00, 0x00, 0x00, 0x00 - }) - - CreateDwordField(INBF, 0, PSD0) /* PIO spd0 */ - CreateDwordField(INBF, 4, DSD0) /* PIO spd0 */ - CreateDwordField(INBF, 8, PSD1) /* PIO spd1 */ - CreateDwordField(INBF, 12, DSD1) /* DMA spd1 */ - CreateDwordField(INBF, 16, BFFG) /*buffer flag */ - - Store(Match(POTT, MLE, PSD0, MTR, 0, 0), Local0) - Divide(Local0, 5, PPMM,) /* Primary PIO master Mode */ - Store(Match(POTT, MLE, PSD1, MTR, 0, 0), Local1) - Divide(Local1, 5, PPSM,) /* Primary PIO slave Mode */ - - Store(DerefOf(Index(PORT, Local0)), PPTM) /* Primary PIO Master Timing */ - Store(DerefOf(Index(PORT, Local1)), PPTS) /* Primary PIO Slave Timing */ - - If(And(BFFG, 0x01)) { /* Drive 0 is under UDMA mode */ - Store(Match(UDTT, MLE, DSD0, MTR, 0, 0), Local0) - Divide(Local0, 7, PDMM,) - Or(PDCR, 0x01, PDCR) - } - Else { - If(LNotEqual(DSD0, 0xFFFFFFFF)) { - Store(Match(MDTT, MLE, DSD0, MTR, 0, 0), Local0) - Store(DerefOf(Index(MDRT, Local0)), PMTM) - } - } - - If(And(BFFG, 0x04)) { /* Drive 1 is under UDMA mode */ - Store(Match(UDTT, MLE, DSD1, MTR, 0, 0), Local0) - Divide(Local0, 7, PDSM,) - Or(PDCR, 0x02, PDCR) - } - Else { - If(LNotEqual(DSD1, 0xFFFFFFFF)) { - Store(Match(MDTT, MLE, DSD1, MTR, 0, 0), Local0) - Store(DerefOf(Index(MDRT, Local0)), PMTS) - } - } - /* Return(INBF) */ - } /*End Method(_STM) */ - Device(MST) - { - Name(_ADR, 0) - Method(_GTF) { - Name(CMBF, Buffer(21) { - 0x03, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xEF, - 0x03, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xEF, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xF5 - }) - CreateByteField(CMBF, 1, POMD) - CreateByteField(CMBF, 8, DMMD) - CreateByteField(CMBF, 5, CMDA) - CreateByteField(CMBF, 12, CMDB) - CreateByteField(CMBF, 19, CMDC) - - Store(0xA0, CMDA) - Store(0xA0, CMDB) - Store(0xA0, CMDC) - - Or(PPMM, 0x08, POMD) - - If(And(PDCR, 0x01)) { - Or(PDMM, 0x40, DMMD) - } - Else { - Store(Match - (MDTT, MLE, GTTM(PMTM), - MTR, 0, 0), Local0) - If(LLess(Local0, 3)) { - Or(0x20, Local0, DMMD) - } - } - Return(CMBF) - } - } /* End Device(MST) */ - - Device(SLAV) - { - Name(_ADR, 1) - Method(_GTF) { - Name(CMBF, Buffer(21) { - 0x03, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xEF, - 0x03, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xEF, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xF5 - }) - CreateByteField(CMBF, 1, POMD) - CreateByteField(CMBF, 8, DMMD) - CreateByteField(CMBF, 5, CMDA) - CreateByteField(CMBF, 12, CMDB) - CreateByteField(CMBF, 19, CMDC) - - Store(0xB0, CMDA) - Store(0xB0, CMDB) - Store(0xB0, CMDC) - - Or(PPSM, 0x08, POMD) - - If(And(PDCR, 0x02)) { - Or(PDSM, 0x40, DMMD) - } - Else { - Store(Match - (MDTT, MLE, GTTM(PMTS), - MTR, 0, 0), Local0) - If(LLess(Local0, 3)) { - Or(0x20, Local0, DMMD) - } - } - Return(CMBF) - } - } /* End Device(SLAV) */ -} diff --git a/src/mainboard/gigabyte/ma78gm/acpi/routing.asl b/src/mainboard/gigabyte/ma78gm/acpi/routing.asl deleted file mode 100644 index abb8ddc6bf..0000000000 --- a/src/mainboard/gigabyte/ma78gm/acpi/routing.asl +++ /dev/null @@ -1,308 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2010 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -/* -#include -DefinitionBlock ("DSDT.AML", "DSDT", 0x01, OEM_ID, ACPI_TABLE_CREATOR, 0x00010001 - ) - { - #include "routing.asl" - } -*/ - -/* Routing is in System Bus scope */ -Scope(\_SB) { - Name(PR0, Package(){ - /* NB devices */ - /* Bus 0, Dev 0 - RS780 Host Controller */ - /* Bus 0, Dev 1 - PCI Bridge for Internal Graphics */ - /* Bus 0, Dev 2 - PCIe Bridge for x8 PCIe Slot (GFX0) */ - Package(){0x0002FFFF, 0, INTC, 0 }, - Package(){0x0002FFFF, 1, INTD, 0 }, - Package(){0x0002FFFF, 2, INTA, 0 }, - Package(){0x0002FFFF, 3, INTB, 0 }, - /* Bus 0, Dev 3 - PCIe graphics port 1 bridge */ - /* Bus 0, Dev 4 - PCIe Bridge for Express Card Slot */ - Package(){0x0004FFFF, 0, INTA, 0 }, - Package(){0x0004FFFF, 1, INTB, 0 }, - Package(){0x0004FFFF, 2, INTC, 0 }, - Package(){0x0004FFFF, 3, INTD, 0 }, - /* Bus 0, Dev 5 - General purpose PCIe bridge 5 */ - /* Package(){0x0005FFFF, 0, INTB, 0 }, */ - /* Package(){0x0005FFFF, 1, INTC, 0 }, */ - /* Package(){0x0005FFFF, 2, INTD, 0 }, */ - /* Package(){0x0005FFFF, 3, INTA, 0 }, */ - /* Bus 0, Dev 6 - PCIe Bridge for Ethernet Chip */ - Package(){0x0006FFFF, 0, INTC, 0 }, - Package(){0x0006FFFF, 1, INTD, 0 }, - Package(){0x0006FFFF, 2, INTA, 0 }, - Package(){0x0006FFFF, 3, INTB, 0 }, - /* Bus 0, Dev 7 - PCIe Bridge for x1 PCIe Slot */ - Package(){0x0007FFFF, 0, INTD, 0 }, - Package(){0x0007FFFF, 1, INTA, 0 }, - Package(){0x0007FFFF, 2, INTB, 0 }, - Package(){0x0007FFFF, 3, INTC, 0 }, - /* Bus 0, Funct 8 - Southbridge port (normally hidden) */ - - /* SB devices */ - /* Bus 0, Dev 17 - SATA controller #2 */ - /* Bus 0, Dev 18 - SATA controller #1 */ - Package(){0x0011FFFF, 0, INTA, 0 }, - - /* Bus 0, Dev 19 - USB: OHCI, dev 18,19 func 0-2, dev 20 func 5; - * EHCI, dev 18, 19 func 2 */ - Package(){0x0012FFFF, 0, INTA, 0 }, - Package(){0x0012FFFF, 1, INTB, 0 }, - Package(){0x0012FFFF, 2, INTC, 0 }, - - Package(){0x0013FFFF, 0, INTC, 0 }, - Package(){0x0013FFFF, 1, INTD, 0 }, - Package(){0x0013FFFF, 2, INTA, 0 }, - - /* Package(){0x0014FFFF, 1, INTA, 0 }, */ - - /* Bus 0, Dev 20 - F0:SMBus/ACPI,F1:IDE;F2:HDAudio;F3:LPC;F4:PCIBridge;F5:USB */ - Package(){0x0014FFFF, 0, INTA, 0 }, - Package(){0x0014FFFF, 1, INTB, 0 }, - Package(){0x0014FFFF, 2, INTC, 0 }, - Package(){0x0014FFFF, 3, INTD, 0 }, - }) - - Name(APR0, Package(){ - /* NB devices in APIC mode */ - /* Bus 0, Dev 0 - RS780 Host Controller */ - - /* Bus 0, Dev 1 - PCI Bridge for Internal Graphics */ - /* Package(){0x0001FFFF, 0, 0, 18 }, */ - /* Package(){0x0001FFFF, 1, 0, 19 }, */ - - /* Bus 0, Dev 2 - PCIe Bridge for x8 PCIe Slot (GFX0) */ - Package(){0x0002FFFF, 0, 0, 18 }, - /* Package(){0x0002FFFF, 1, 0, 19 }, */ - /* Package(){0x0002FFFF, 2, 0, 16 }, */ - /* Package(){0x0002FFFF, 3, 0, 17 }, */ - - /* Bus 0, Dev 3 - PCIe graphics port 1 bridge */ - Package(){0x0003FFFF, 0, 0, 19 }, - - /* Bus 0, Dev 4 - PCIe Bridge for Express Card Slot */ - Package(){0x0004FFFF, 0, 0, 16 }, - /* Package(){0x0004FFFF, 1, 0, 17 }, */ - /* Package(){0x0004FFFF, 2, 0, 18 }, */ - /* Package(){0x0004FFFF, 3, 0, 19 }, */ - - /* Bus 0, Dev 5 - General purpose PCIe bridge 5 */ - /* Package(){0x0005FFFF, 0, 0, 17 }, */ - /* Package(){0x0005FFFF, 1, 0, 18 }, */ - /* Package(){0x0005FFFF, 2, 0, 19 }, */ - /* Package(){0x0005FFFF, 3, 0, 16 }, */ - - /* Bus 0, Dev 6 - General purpose PCIe bridge 6 */ - /* Package(){0x0006FFFF, 0, 0, 18 }, */ - /* Package(){0x0006FFFF, 1, 0, 19 }, */ - /* Package(){0x0006FFFF, 2, 0, 16 }, */ - /* Package(){0x0006FFFF, 3, 0, 17 }, */ - - /* Bus 0, Dev 7 - PCIe Bridge for network card */ - /* Package(){0x0007FFFF, 0, 0, 19 }, */ - /* Package(){0x0007FFFF, 1, 0, 16 }, */ - /* Package(){0x0007FFFF, 2, 0, 17 }, */ - /* Package(){0x0007FFFF, 3, 0, 18 }, */ - - /* Bus 0, Dev 9 - PCIe Bridge for network card */ - Package(){0x0009FFFF, 0, 0, 17 }, - /* Package(){0x0009FFFF, 1, 0, 16 }, */ - /* Package(){0x0009FFFF, 2, 0, 17 }, */ - /* Package(){0x0009FFFF, 3, 0, 18 }, */ - /* Bus 0, Dev A - PCIe Bridge for network card */ - Package(){0x000AFFFF, 0, 0, 18 }, - /* Package(){0x000AFFFF, 1, 0, 16 }, */ - /* Package(){0x000AFFFF, 2, 0, 17 }, */ - /* Package(){0x000AFFFF, 3, 0, 18 }, */ - /* Bus 0, Funct 8 - Southbridge port (normally hidden) */ - - /* SB devices in APIC mode */ - /* Bus 0, Dev 17 - SATA controller #2 */ - /* Bus 0, Dev 18 - SATA controller #1 */ - Package(){0x0011FFFF, 0, 0, 22 }, - - /* Bus 0, Dev 19 - USB: OHCI, dev 18,19 func 0-2, dev 20 func 5; - * EHCI, dev 18, 19 func 2 */ - Package(){0x0012FFFF, 0, 0, 16 }, - Package(){0x0012FFFF, 1, 0, 17 }, - Package(){0x0012FFFF, 2, 0, 18 }, - - Package(){0x0013FFFF, 0, 0, 18 }, - Package(){0x0013FFFF, 1, 0, 19 }, - Package(){0x0013FFFF, 2, 0, 16 }, - - /* Package(){0x00140000, 0, 0, 16 }, */ - - /* Package(){0x00130004, 2, 0, 18 }, */ - /* Package(){0x00130005, 3, 0, 19 }, */ - - /* Bus 0, Dev 20 - F0:SMBus/ACPI, F1:IDE; F2:HDAudio; F3:LPC; F4:PCIBridge; F5:USB */ - Package(){0x0014FFFF, 0, 0, 16 }, - Package(){0x0014FFFF, 1, 0, 17 }, - Package(){0x0014FFFF, 2, 0, 18 }, - Package(){0x0014FFFF, 3, 0, 19 }, - /* Package(){0x00140004, 2, 0, 18 }, */ - /* Package(){0x00140004, 3, 0, 19 }, */ - /* Package(){0x00140005, 1, 0, 17 }, */ - /* Package(){0x00140006, 1, 0, 17 }, */ - }) - - Name(PR1, Package(){ - /* Internal graphics - RS780 VGA, Bus1, Dev5 */ - Package(){0x0005FFFF, 0, INTA, 0 }, - Package(){0x0005FFFF, 1, INTB, 0 }, - Package(){0x0005FFFF, 2, INTC, 0 }, - Package(){0x0005FFFF, 3, INTD, 0 }, - }) - - Name(APR1, Package(){ - /* Internal graphics - RS780 VGA, Bus1, Dev5 */ - Package(){0x0005FFFF, 0, 0, 18 }, - Package(){0x0005FFFF, 1, 0, 19 }, - /* Package(){0x0005FFFF, 2, 0, 20 }, */ - /* Package(){0x0005FFFF, 3, 0, 17 }, */ - }) - - Name(PS2, Package(){ - /* The external GFX - Hooked to PCIe slot 2 */ - Package(){0x0000FFFF, 0, INTC, 0 }, - Package(){0x0000FFFF, 1, INTD, 0 }, - Package(){0x0000FFFF, 2, INTA, 0 }, - Package(){0x0000FFFF, 3, INTB, 0 }, - }) - - Name(APS2, Package(){ - /* The external GFX - Hooked to PCIe slot 2 */ - Package(){0x0000FFFF, 0, 0, 18 }, - Package(){0x0000FFFF, 1, 0, 19 }, - Package(){0x0000FFFF, 2, 0, 16 }, - Package(){0x0000FFFF, 3, 0, 17 }, - }) - - Name(PS4, Package(){ - /* PCIe slot - Hooked to PCIe slot 4 */ - Package(){0x0000FFFF, 0, INTA, 0 }, - Package(){0x0000FFFF, 1, INTB, 0 }, - Package(){0x0000FFFF, 2, INTC, 0 }, - Package(){0x0000FFFF, 3, INTD, 0 }, - }) - - Name(APS4, Package(){ - /* PCIe slot - Hooked to PCIe slot 4 */ - Package(){0x0000FFFF, 0, 0, 16 }, - Package(){0x0000FFFF, 1, 0, 17 }, - Package(){0x0000FFFF, 2, 0, 18 }, - Package(){0x0000FFFF, 3, 0, 19 }, - }) - - Name(PS5, Package(){ - /* PCIe slot - Hooked to PCIe slot 5 */ - Package(){0x0000FFFF, 0, INTB, 0 }, - Package(){0x0000FFFF, 1, INTC, 0 }, - Package(){0x0000FFFF, 2, INTD, 0 }, - Package(){0x0000FFFF, 3, INTA, 0 }, - }) - - Name(APS5, Package(){ - /* PCIe slot - Hooked to PCIe slot 5 */ - Package(){0x0000FFFF, 0, 0, 17 }, - Package(){0x0000FFFF, 1, 0, 18 }, - Package(){0x0000FFFF, 2, 0, 19 }, - Package(){0x0000FFFF, 3, 0, 16 }, - }) - - Name(PS6, Package(){ - /* PCIe slot - Hooked to PCIe slot 6 */ - Package(){0x0000FFFF, 0, INTC, 0 }, - Package(){0x0000FFFF, 1, INTD, 0 }, - Package(){0x0000FFFF, 2, INTA, 0 }, - Package(){0x0000FFFF, 3, INTB, 0 }, - }) - - Name(APS6, Package(){ - /* PCIe slot - Hooked to PCIe slot 6 */ - Package(){0x0000FFFF, 0, 0, 18 }, - Package(){0x0000FFFF, 1, 0, 19 }, - Package(){0x0000FFFF, 2, 0, 16 }, - Package(){0x0000FFFF, 3, 0, 17 }, - }) - - Name(PS7, Package(){ - /* The onboard Ethernet chip - Hooked to PCIe slot 7 */ - Package(){0x0000FFFF, 0, INTD, 0 }, - Package(){0x0000FFFF, 1, INTA, 0 }, - Package(){0x0000FFFF, 2, INTB, 0 }, - Package(){0x0000FFFF, 3, INTC, 0 }, - }) - - Name(APS7, Package(){ - /* The onboard Ethernet chip - Hooked to PCIe slot 7 */ - Package(){0x0000FFFF, 0, 0, 19 }, - Package(){0x0000FFFF, 1, 0, 16 }, - Package(){0x0000FFFF, 2, 0, 17 }, - Package(){0x0000FFFF, 3, 0, 18 }, - }) - Name(PS9, Package(){ - /* PCIe slot - Hooked to PCIe slot 9 */ - Package(){0x0000FFFF, 0, INTD, 0 }, - Package(){0x0000FFFF, 1, INTA, 0 }, - Package(){0x0000FFFF, 2, INTB, 0 }, - Package(){0x0000FFFF, 3, INTC, 0 }, - }) - - Name(APS9, Package(){ - /* PCIe slot - Hooked to PCIe slot 9 */ - Package(){0x0000FFFF, 0, 0, 17 }, - Package(){0x0000FFFF, 1, 0, 18 }, - Package(){0x0000FFFF, 2, 0, 19 }, - Package(){0x0000FFFF, 3, 0, 16 }, - }) - Name(PSa, Package(){ - /* PCIe slot - Hooked to PCIe slot 10 */ - Package(){0x0000FFFF, 0, INTD, 0 }, - Package(){0x0000FFFF, 1, INTA, 0 }, - Package(){0x0000FFFF, 2, INTB, 0 }, - Package(){0x0000FFFF, 3, INTC, 0 }, - }) - - Name(APSa, Package(){ - /* PCIe slot - Hooked to PCIe slot 10 */ - Package(){0x0000FFFF, 0, 0, 18 }, - Package(){0x0000FFFF, 1, 0, 19 }, - Package(){0x0000FFFF, 2, 0, 16 }, - Package(){0x0000FFFF, 3, 0, 17 }, - }) - - Name(PCIB, Package(){ - /* PCI slots: slot 0, slot 1, slot 2 behind Dev14, Fun4. */ - Package(){0x0005FFFF, 0, 0, 0x14 }, - Package(){0x0005FFFF, 1, 0, 0x15 }, - Package(){0x0005FFFF, 2, 0, 0x16 }, - Package(){0x0005FFFF, 3, 0, 0x17 }, - Package(){0x0006FFFF, 0, 0, 0x15 }, - Package(){0x0006FFFF, 1, 0, 0x16 }, - Package(){0x0006FFFF, 2, 0, 0x17 }, - Package(){0x0006FFFF, 3, 0, 0x14 }, - Package(){0x0007FFFF, 0, 0, 0x16 }, - Package(){0x0007FFFF, 1, 0, 0x17 }, - Package(){0x0007FFFF, 2, 0, 0x14 }, - Package(){0x0007FFFF, 3, 0, 0x15 }, - }) -} diff --git a/src/mainboard/gigabyte/ma78gm/acpi/sata.asl b/src/mainboard/gigabyte/ma78gm/acpi/sata.asl deleted file mode 100644 index cb9b221ba3..0000000000 --- a/src/mainboard/gigabyte/ma78gm/acpi/sata.asl +++ /dev/null @@ -1,145 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2010 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -/* simple name description */ - -/* -Scope (_SB) { - Device(PCI0) { - Device(SATA) { - Name(_ADR, 0x00110000) - #include "sata.asl" - } - } -} -*/ - -Name(STTM, Buffer(20) { - 0x78, 0x00, 0x00, 0x00, 0x0f, 0x00, 0x00, 0x00, - 0x78, 0x00, 0x00, 0x00, 0x0f, 0x00, 0x00, 0x00, - 0x1f, 0x00, 0x00, 0x00 -}) - -/* Start by clearing the PhyRdyChg bits */ -Method(_INI) { - \_GPE._L1F() -} - -Device(PMRY) -{ - Name(_ADR, 0) - Method(_GTM, 0x0, NotSerialized) { - Return(STTM) - } - Method(_STM, 0x3, NotSerialized) {} - - Device(PMST) { - Name(_ADR, 0) - Method(_STA,0) { - if (LGreater(P0IS,0)) { - return (0x0F) /* sata is visible */ - } - else { - return (0x00) /* sata is missing */ - } - } - }/* end of PMST */ - - Device(PSLA) - { - Name(_ADR, 1) - Method(_STA,0) { - if (LGreater(P1IS,0)) { - return (0x0F) /* sata is visible */ - } - else { - return (0x00) /* sata is missing */ - } - } - } /* end of PSLA */ -} /* end of PMRY */ - - -Device(SEDY) -{ - Name(_ADR, 1) /* IDE Scondary Channel */ - Method(_GTM, 0x0, NotSerialized) { - Return(STTM) - } - Method(_STM, 0x3, NotSerialized) {} - - Device(SMST) - { - Name(_ADR, 0) - Method(_STA,0) { - if (LGreater(P2IS,0)) { - return (0x0F) /* sata is visible */ - } - else { - return (0x00) /* sata is missing */ - } - } - } /* end of SMST */ - - Device(SSLA) - { - Name(_ADR, 1) - Method(_STA,0) { - if (LGreater(P3IS,0)) { - return (0x0F) /* sata is visible */ - } - else { - return (0x00) /* sata is missing */ - } - } - } /* end of SSLA */ -} /* end of SEDY */ - -/* SATA Hot Plug Support */ -Scope(\_GPE) { - Method(_L1F,0x0,NotSerialized) { - if (\_SB.P0PR) { - if (LGreater(\_SB.P0IS,0)) { - sleep(32) - } - Notify(\_SB.PCI0.STCR.PMRY.PMST, 0x01) /* NOTIFY_DEVICE_CHECK */ - store(one, \_SB.P0PR) - } - - if (\_SB.P1PR) { - if (LGreater(\_SB.P1IS,0)) { - sleep(32) - } - Notify(\_SB.PCI0.STCR.PMRY.PSLA, 0x01) /* NOTIFY_DEVICE_CHECK */ - store(one, \_SB.P1PR) - } - - if (\_SB.P2PR) { - if (LGreater(\_SB.P2IS,0)) { - sleep(32) - } - Notify(\_SB.PCI0.STCR.SEDY.SMST, 0x01) /* NOTIFY_DEVICE_CHECK */ - store(one, \_SB.P2PR) - } - - if (\_SB.P3PR) { - if (LGreater(\_SB.P3IS,0)) { - sleep(32) - } - Notify(\_SB.PCI0.STCR.SEDY.SSLA, 0x01) /* NOTIFY_DEVICE_CHECK */ - store(one, \_SB.P3PR) - } - } -} diff --git a/src/mainboard/gigabyte/ma78gm/acpi/usb.asl b/src/mainboard/gigabyte/ma78gm/acpi/usb.asl deleted file mode 100644 index a3ccb97ff9..0000000000 --- a/src/mainboard/gigabyte/ma78gm/acpi/usb.asl +++ /dev/null @@ -1,158 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2010 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -/* simple name description */ -/* -#include -DefinitionBlock ("DSDT.AML", "DSDT", 0x01, OEM_ID, ACPI_TABLE_CREATOR, 0x00010001 - ) - { - #include "usb.asl" - } -*/ -Method(UCOC, 0) { - Sleep(20) - Store(0x13,CMTI) - Store(0,GPSL) -} - -/* USB Port 0 overcurrent uses Gpm 0 */ -If(LLessEqual(UOM0,9)) { - Scope (\_GPE) { - Method (_L13) { - UCOC() - if(LEqual(GPB0,PLC0)) { - Not(PLC0,PLC0) - Store(PLC0, \_SB.PT0D) - } - } - } -} - -/* USB Port 1 overcurrent uses Gpm 1 */ -If (LLessEqual(UOM1,9)) { - Scope (\_GPE) { - Method (_L14) { - UCOC() - if (LEqual(GPB1,PLC1)) { - Not(PLC1,PLC1) - Store(PLC1, \_SB.PT1D) - } - } - } -} - -/* USB Port 2 overcurrent uses Gpm 2 */ -If (LLessEqual(UOM2,9)) { - Scope (\_GPE) { - Method (_L15) { - UCOC() - if (LEqual(GPB2,PLC2)) { - Not(PLC2,PLC2) - Store(PLC2, \_SB.PT2D) - } - } - } -} - -/* USB Port 3 overcurrent uses Gpm 3 */ -If (LLessEqual(UOM3,9)) { - Scope (\_GPE) { - Method (_L16) { - UCOC() - if (LEqual(GPB3,PLC3)) { - Not(PLC3,PLC3) - Store(PLC3, \_SB.PT3D) - } - } - } -} - -/* USB Port 4 overcurrent uses Gpm 4 */ -If (LLessEqual(UOM4,9)) { - Scope (\_GPE) { - Method (_L19) { - UCOC() - if (LEqual(GPB4,PLC4)) { - Not(PLC4,PLC4) - Store(PLC4, \_SB.PT4D) - } - } - } -} - -/* USB Port 5 overcurrent uses Gpm 5 */ -If (LLessEqual(UOM5,9)) { - Scope (\_GPE) { - Method (_L1A) { - UCOC() - if (LEqual(GPB5,PLC5)) { - Not(PLC5,PLC5) - Store(PLC5, \_SB.PT5D) - } - } - } -} - -/* USB Port 6 overcurrent uses Gpm 6 */ -If (LLessEqual(UOM6,9)) { - Scope (\_GPE) { - /* Method (_L1C) { */ - Method (_L06) { - UCOC() - if (LEqual(GPB6,PLC6)) { - Not(PLC6,PLC6) - Store(PLC6, \_SB.PT6D) - } - } - } -} - -/* USB Port 7 overcurrent uses Gpm 7 */ -If (LLessEqual(UOM7,9)) { - Scope (\_GPE) { - /* Method (_L1D) { */ - Method (_L07) { - UCOC() - if (LEqual(GPB7,PLC7)) { - Not(PLC7,PLC7) - Store(PLC7, \_SB.PT7D) - } - } - } -} - -/* USB Port 8 overcurrent uses Gpm 8 */ -If (LLessEqual(UOM8,9)) { - Scope (\_GPE) { - Method (_L17) { - if (LEqual(G8IS,PLC8)) { - Not(PLC8,PLC8) - Store(PLC8, \_SB.PT8D) - } - } - } -} - -/* USB Port 9 overcurrent uses Gpm 9 */ -If (LLessEqual(UOM9,9)) { - Scope (\_GPE) { - Method (_L0E) { - if (LEqual(G9IS,0)) { - Store(1,\_SB.PT9D) - } - } - } -} diff --git a/src/mainboard/gigabyte/ma78gm/acpi_tables.c b/src/mainboard/gigabyte/ma78gm/acpi_tables.c deleted file mode 100644 index 967343da67..0000000000 --- a/src/mainboard/gigabyte/ma78gm/acpi_tables.c +++ /dev/null @@ -1,44 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2010 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include -#include - -unsigned long acpi_fill_madt(unsigned long current) -{ - /* create all subtables for processors */ - current = acpi_create_madt_lapics(current); - - /* Write SB700 IOAPIC, only one */ - current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, 2, - IO_APIC_ADDR, 0); - - current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) - current, 0, 0, 2, 0); - current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) - current, 0, 9, 9, 0xF); - /* 0: mean bus 0--->ISA */ - /* 0: PIC 0 */ - /* 2: APIC 2 */ - /* 5 mean: 0101 --> Edge-triggered, Active high */ - - /* create all subtables for processors */ - /* current = acpi_create_madt_lapic_nmis(current, 5, 1); */ - /* 1: LINT1 connect to NMI */ - - return current; -} diff --git a/src/mainboard/gigabyte/ma78gm/board_info.txt b/src/mainboard/gigabyte/ma78gm/board_info.txt deleted file mode 100644 index 53e393244d..0000000000 --- a/src/mainboard/gigabyte/ma78gm/board_info.txt +++ /dev/null @@ -1,3 +0,0 @@ -Category: desktop -Board URL: http://www.gigabyte.com/products/product-page.aspx?pid=2995#ov -Release year: 2008 diff --git a/src/mainboard/gigabyte/ma78gm/cmos.layout b/src/mainboard/gigabyte/ma78gm/cmos.layout deleted file mode 100644 index 6c3d3f6c9e..0000000000 --- a/src/mainboard/gigabyte/ma78gm/cmos.layout +++ /dev/null @@ -1,52 +0,0 @@ -entries - -0 384 r 0 reserved_memory -384 1 e 4 boot_option -388 4 h 0 reboot_counter -#392 3 r 0 unused -395 1 e 1 hw_scrubber -396 1 e 1 interleave_chip_selects -397 2 e 8 max_mem_clock -399 1 e 2 multi_core -400 1 e 1 power_on_after_fail -412 4 e 6 debug_level -440 4 e 9 slow_cpu -444 1 e 1 nmi -445 1 e 1 gart -456 1 e 1 ECC_memory -728 256 h 0 user_data -984 16 h 0 check_sum -# Reserve the extended AMD configuration registers -1000 24 r 0 amd_reserved - - - -enumerations - -#ID value text -1 0 Disable -1 1 Enable -2 0 Enable -2 1 Disable -4 0 Fallback -4 1 Normal -6 5 Notice -6 6 Info -6 7 Debug -6 8 Spew -8 0 400Mhz -8 1 333Mhz -8 2 266Mhz -8 3 200Mhz -9 0 off -9 1 87.5% -9 2 75.0% -9 3 62.5% -9 4 50.0% -9 5 37.5% -9 6 25.0% -9 7 12.5% - -checksums - -checksum 392 983 984 diff --git a/src/mainboard/gigabyte/ma78gm/devicetree.cb b/src/mainboard/gigabyte/ma78gm/devicetree.cb deleted file mode 100644 index 3e69cb3527..0000000000 --- a/src/mainboard/gigabyte/ma78gm/devicetree.cb +++ /dev/null @@ -1,115 +0,0 @@ -# sample config for gigabyte/ma78gm -chip northbridge/amd/amdfam10/root_complex - device cpu_cluster 0 on - chip cpu/amd/socket_AM2r2 #L1 and DDR2 - device lapic 0 on end - end - end - device domain 0 on - subsystemid 0x1022 0x3060 inherit - chip northbridge/amd/amdfam10 - device pci 18.0 on # northbridge - chip southbridge/amd/rs780 - device pci 0.0 on end # HT 0x9600 - device pci 1.0 on end # Internal Graphics P2P bridge 0x9602 - device pci 2.0 on end # PCIE P2P bridge (external graphics) 0x9603 - device pci 3.0 off end # PCIE P2P bridge 0x960b - device pci 4.0 on end # PCIE P2P bridge 0x9604 - device pci 5.0 off end # PCIE P2P bridge 0x9605 - device pci 6.0 off end # PCIE P2P bridge 0x9606 - device pci 7.0 off end # PCIE P2P bridge 0x9607 - device pci 8.0 off end # NB/SB Link P2P bridge - device pci 9.0 on end # - device pci a.0 on end # - register "gppsb_configuration" = "1" # Configuration B - register "gpp_configuration" = "3" # Configuration D default - register "port_enable" = "0x6fc" - register "gfx_dev2_dev3" = "1" - register "gfx_dual_slot" = "1" - register "gfx_lane_reversal" = "0" - register "gfx_tmds" = "0" - register "gfx_compliance" = "0" - register "gfx_reconfiguration" = "1" - register "gfx_link_width" = "0" - end - chip southbridge/amd/sb700 # it is under NB/SB Link, but on the same pri bus - device pci 11.0 on end # SATA - device pci 12.0 on end # USB - device pci 12.1 on end # USB - device pci 12.2 on end # USB - device pci 13.0 on end # USB - device pci 13.1 on end # USB - device pci 13.2 on end # USB - device pci 14.0 on # SM - chip drivers/generic/generic #dimm 0-0-0 - device i2c 50 on end - end - chip drivers/generic/generic #dimm 0-0-1 - device i2c 51 on end - end - chip drivers/generic/generic #dimm 0-1-0 - device i2c 52 on end - end - chip drivers/generic/generic #dimm 0-1-1 - device i2c 53 on end - end - end # SM - device pci 14.1 on end # IDE 0x439c - device pci 14.2 on end # HDA 0x4383 - device pci 14.3 on # LPC 0x439d - chip superio/ite/it8718f - device pnp 2e.0 off # Floppy - io 0x60 = 0x3f0 - irq 0x70 = 6 - drq 0x74 = 2 - end - device pnp 2e.1 on # Com1 - io 0x60 = 0x3f8 - irq 0x70 = 4 - end - device pnp 2e.2 off # Com2 - io 0x60 = 0x2f8 - irq 0x70 = 3 - end - device pnp 2e.3 off # Parallel Port - io 0x60 = 0x378 - irq 0x70 = 7 - end - device pnp 2e.4 off end # EC - device pnp 2e.5 on # Keyboard - io 0x60 = 0x60 - io 0x62 = 0x64 - irq 0x70 = 1 - end - device pnp 2e.6 on # Mouse - irq 0x70 = 12 - end - device pnp 2e.7 off # GPIO, must be closed for unresolved reason. - end - device pnp 2e.8 off # MIDI - io 0x60 = 0x300 - irq 0x70 = 9 - end - device pnp 2e.9 off # GAME - io 0x60 = 0x220 - end - device pnp 2e.a off end # CIR - end #superio/ite/it8718f - end #LPC - device pci 14.4 on end # PCI 0x4384 - device pci 14.5 on end # USB 2 - register "boot_switch_sata_ide" = "0" # 0: boot from SATA. 1: IDE - end #southbridge/amd/sb700 - end # device pci 18.0 - - device pci 18.0 on end - device pci 18.0 on end - device pci 18.1 on end - device pci 18.2 on end - device pci 18.3 on end - device pci 18.4 on end -# device pci 00.5 on end - end - end #domain - #for node 32 to node 63 -end diff --git a/src/mainboard/gigabyte/ma78gm/dsdt.asl b/src/mainboard/gigabyte/ma78gm/dsdt.asl deleted file mode 100644 index eec3093b8e..0000000000 --- a/src/mainboard/gigabyte/ma78gm/dsdt.asl +++ /dev/null @@ -1,1718 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2010 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -/* DefinitionBlock Statement */ -#include -DefinitionBlock ( - "DSDT.AML", /* Output filename */ - "DSDT", /* Signature */ - 0x02, /* DSDT Revision, needs to be 2 for 64bit */ - OEM_ID, - ACPI_TABLE_CREATOR, - 0x00010001 /* OEM Revision */ - ) -{ /* Start of ASL file */ - /* #include */ /* Include global debug methods if needed */ - - /* Data to be patched by the BIOS during POST */ - /* FIXME the patching is not done yet! */ - /* Memory related values */ - Name(LOMH, 0x0) /* Start of unused memory in C0000-E0000 range */ - Name(PBAD, 0x0) /* Address of BIOS area (If TOM2 != 0, Addr >> 16) */ - Name(PBLN, 0x0) /* Length of BIOS area */ - - Name(PCBA, 0xE0000000) /* Base address of PCIe config space */ - Name(HPBA, 0xFED00000) /* Base address of HPET table */ - - /* USB overcurrent mapping pins. */ - Name(UOM0, 0) - Name(UOM1, 2) - Name(UOM2, 0) - Name(UOM3, 7) - Name(UOM4, 2) - Name(UOM5, 2) - Name(UOM6, 6) - Name(UOM7, 2) - Name(UOM8, 6) - Name(UOM9, 6) - - /* Some global data */ - Name(OSVR, 3) /* Assume nothing. WinXp = 1, Vista = 2, Linux = 3, WinCE = 4 */ - Name(OSV, Ones) /* Assume nothing */ - Name(PMOD, One) /* Assume APIC */ - - /* - * Processor Object - * - */ - Scope (\_PR) { /* define processor scope */ - Device (CPU0) { - Name (_HID, "ACPI0007") - Name (_UID, 0) - #include "acpi/cpstate.asl" - } - Device (CPU1) { - Name (_HID, "ACPI0007") - Name (_UID, 1) - #include "acpi/cpstate.asl" - } - Device (CPU2) { - Name (_HID, "ACPI0007") - Name (_UID, 2) - #include "acpi/cpstate.asl" - } - Device (CPU3) { - Name (_HID, "ACPI0007") - Name (_UID, 3) - #include "acpi/cpstate.asl" - } - } /* End _PR scope */ - - /* PIC IRQ mapping registers, C00h-C01h */ - OperationRegion(PRQM, SystemIO, 0x00000C00, 0x00000002) - Field(PRQM, ByteAcc, NoLock, Preserve) { - PRQI, 0x00000008, - PRQD, 0x00000008, /* Offset: 1h */ - } - IndexField(PRQI, PRQD, ByteAcc, NoLock, Preserve) { - PINA, 0x00000008, /* Index 0 */ - PINB, 0x00000008, /* Index 1 */ - PINC, 0x00000008, /* Index 2 */ - PIND, 0x00000008, /* Index 3 */ - AINT, 0x00000008, /* Index 4 */ - SINT, 0x00000008, /* Index 5 */ - , 0x00000008, /* Index 6 */ - AAUD, 0x00000008, /* Index 7 */ - AMOD, 0x00000008, /* Index 8 */ - PINE, 0x00000008, /* Index 9 */ - PINF, 0x00000008, /* Index A */ - PING, 0x00000008, /* Index B */ - PINH, 0x00000008, /* Index C */ - } - - /* PCI Error control register */ - OperationRegion(PERC, SystemIO, 0x00000C14, 0x00000001) - Field(PERC, ByteAcc, NoLock, Preserve) { - SENS, 0x00000001, - PENS, 0x00000001, - SENE, 0x00000001, - PENE, 0x00000001, - } - - /* Client Management index/data registers */ - OperationRegion(CMT, SystemIO, 0x00000C50, 0x00000002) - Field(CMT, ByteAcc, NoLock, Preserve) { - CMTI, 8, - /* Client Management Data register */ - G64E, 1, - G64O, 1, - G32O, 2, - , 2, - GPSL, 2, - } - - /* GPM Port register */ - OperationRegion(GPT, SystemIO, 0x00000C52, 0x00000001) - Field(GPT, ByteAcc, NoLock, Preserve) { - GPB0,1, - GPB1,1, - GPB2,1, - GPB3,1, - GPB4,1, - GPB5,1, - GPB6,1, - GPB7,1, - } - - /* Flash ROM program enable register */ - OperationRegion(FRE, SystemIO, 0x00000C6F, 0x00000001) - Field(FRE, ByteAcc, NoLock, Preserve) { - , 0x00000006, - FLRE, 0x00000001, - } - - /* PM2 index/data registers */ - OperationRegion(PM2R, SystemIO, 0x00000CD0, 0x00000002) - Field(PM2R, ByteAcc, NoLock, Preserve) { - PM2I, 0x00000008, - PM2D, 0x00000008, - } - - /* Power Management I/O registers */ - OperationRegion(PIOR, SystemIO, 0x00000CD6, 0x00000002) - Field(PIOR, ByteAcc, NoLock, Preserve) { - PIOI, 0x00000008, - PIOD, 0x00000008, - } - IndexField (PIOI, PIOD, ByteAcc, NoLock, Preserve) { - Offset(0x00), /* MiscControl */ - , 1, - T1EE, 1, - T2EE, 1, - Offset(0x01), /* MiscStatus */ - , 1, - T1E, 1, - T2E, 1, - Offset(0x04), /* SmiWakeUpEventEnable3 */ - , 7, - SSEN, 1, - Offset(0x07), /* SmiWakeUpEventStatus3 */ - , 7, - CSSM, 1, - Offset(0x10), /* AcpiEnable */ - , 6, - PWDE, 1, - Offset(0x1C), /* ProgramIoEnable */ - , 3, - MKME, 1, - IO3E, 1, - IO2E, 1, - IO1E, 1, - IO0E, 1, - Offset(0x1D), /* IOMonitorStatus */ - , 3, - MKMS, 1, - IO3S, 1, - IO2S, 1, - IO1S, 1, - IO0S,1, - Offset(0x20), /* AcpiPmEvtBlk */ - APEB, 16, - Offset(0x36), /* GEvtLevelConfig */ - , 6, - ELC6, 1, - ELC7, 1, - Offset(0x37), /* GPMLevelConfig0 */ - , 3, - PLC0, 1, - PLC1, 1, - PLC2, 1, - PLC3, 1, - PLC8, 1, - Offset(0x38), /* GPMLevelConfig1 */ - , 1, - PLC4, 1, - PLC5, 1, - , 1, - PLC6, 1, - PLC7, 1, - Offset(0x3B), /* PMEStatus1 */ - GP0S, 1, - GM4S, 1, - GM5S, 1, - APS, 1, - GM6S, 1, - GM7S, 1, - GP2S, 1, - STSS, 1, - Offset(0x55), /* SoftPciRst */ - SPRE, 1, - , 1, - , 1, - PNAT, 1, - PWMK, 1, - PWNS, 1, - - /* Offset(0x61), */ /* Options_1 */ - /* ,7, */ - /* R617,1, */ - - Offset(0x65), /* UsbPMControl */ - , 4, - URRE, 1, - Offset(0x68), /* MiscEnable68 */ - , 3, - TMTE, 1, - , 1, - Offset(0x92), /* GEVENTIN */ - , 7, - E7IS, 1, - Offset(0x96), /* GPM98IN */ - G8IS, 1, - G9IS, 1, - Offset(0x9A), /* EnhanceControl */ - ,7, - HPDE, 1, - Offset(0xA8), /* PIO7654Enable */ - IO4E, 1, - IO5E, 1, - IO6E, 1, - IO7E, 1, - Offset(0xA9), /* PIO7654Status */ - IO4S, 1, - IO5S, 1, - IO6S, 1, - IO7S, 1, - } - - /* PM1 Event Block - * First word is PM1_Status, Second word is PM1_Enable - */ - OperationRegion(P1EB, SystemIO, APEB, 0x04) - Field(P1EB, ByteAcc, NoLock, Preserve) { - TMST, 1, - , 3, - BMST, 1, - GBST, 1, - Offset(0x01), - PBST, 1, - , 1, - RTST, 1, - , 3, - PWST, 1, - SPWS, 1, - Offset(0x02), - TMEN, 1, - , 4, - GBEN, 1, - Offset(0x03), - PBEN, 1, - , 1, - RTEN, 1, - , 3, - PWDA, 1, - } - - Scope(\_SB) { - /* PCIe Configuration Space for 16 busses */ - OperationRegion(PCFG, SystemMemory, PCBA, 0x01000000) /* Each bus consumes 1MB */ - Field(PCFG, ByteAcc, NoLock, Preserve) { - /* Byte offsets are computed using the following technique: - * ((bus number + 1) * ((device number * 8) * 4096)) + register offset - * The 8 comes from 8 functions per device, and 4096 bytes per function config space - */ - Offset(0x00088024), /* Byte offset to SATA register 24h - Bus 0, Device 17, Function 0 */ - STB5, 32, - Offset(0x00098042), /* Byte offset to OHCI0 register 42h - Bus 0, Device 19, Function 0 */ - PT0D, 1, - PT1D, 1, - PT2D, 1, - PT3D, 1, - PT4D, 1, - PT5D, 1, - PT6D, 1, - PT7D, 1, - PT8D, 1, - PT9D, 1, - Offset(0x000A0004), /* Byte offset to SMBUS register 4h - Bus 0, Device 20, Function 0 */ - SBIE, 1, - SBME, 1, - Offset(0x000A0008), /* Byte offset to SMBUS register 8h - Bus 0, Device 20, Function 0 */ - SBRI, 8, - Offset(0x000A0014), /* Byte offset to SMBUS register 14h - Bus 0, Device 20, Function 0 */ - SBB1, 32, - Offset(0x000A0078), /* Byte offset to SMBUS register 78h - Bus 0, Device 20, Function 0 */ - ,14, - P92E, 1, /* Port92 decode enable */ - } - - OperationRegion(SB5, SystemMemory, STB5, 0x1000) - Field(SB5, AnyAcc, NoLock, Preserve){ - /* Port 0 */ - Offset(0x120), /* Port 0 Task file status */ - P0ER, 1, - , 2, - P0DQ, 1, - , 3, - P0BY, 1, - Offset(0x128), /* Port 0 Serial ATA status */ - P0DD, 4, - , 4, - P0IS, 4, - Offset(0x12C), /* Port 0 Serial ATA control */ - P0DI, 4, - Offset(0x130), /* Port 0 Serial ATA error */ - , 16, - P0PR, 1, - - /* Port 1 */ - offset(0x1A0), /* Port 1 Task file status */ - P1ER, 1, - , 2, - P1DQ, 1, - , 3, - P1BY, 1, - Offset(0x1A8), /* Port 1 Serial ATA status */ - P1DD, 4, - , 4, - P1IS, 4, - Offset(0x1AC), /* Port 1 Serial ATA control */ - P1DI, 4, - Offset(0x1B0), /* Port 1 Serial ATA error */ - , 16, - P1PR, 1, - - /* Port 2 */ - Offset(0x220), /* Port 2 Task file status */ - P2ER, 1, - , 2, - P2DQ, 1, - , 3, - P2BY, 1, - Offset(0x228), /* Port 2 Serial ATA status */ - P2DD, 4, - , 4, - P2IS, 4, - Offset(0x22C), /* Port 2 Serial ATA control */ - P2DI, 4, - Offset(0x230), /* Port 2 Serial ATA error */ - , 16, - P2PR, 1, - - /* Port 3 */ - Offset(0x2A0), /* Port 3 Task file status */ - P3ER, 1, - , 2, - P3DQ, 1, - , 3, - P3BY, 1, - Offset(0x2A8), /* Port 3 Serial ATA status */ - P3DD, 4, - , 4, - P3IS, 4, - Offset(0x2AC), /* Port 3 Serial ATA control */ - P3DI, 4, - Offset(0x2B0), /* Port 3 Serial ATA error */ - , 16, - P3PR, 1, - } - } - - - #include "acpi/routing.asl" - - Scope(\_SB) { - - Method(OSFL, 0){ - - if(LNotEqual(OSVR, Ones)) {Return(OSVR)} /* OS version was already detected */ - - if(CondRefOf(\_OSI)) - { - Store(1, OSVR) /* Assume some form of XP */ - if (\_OSI("Windows 2006")) /* Vista */ - { - Store(2, OSVR) - } - } else { - If(WCMP(\_OS,"Linux")) { - Store(3, OSVR) /* Linux */ - } Else { - Store(4, OSVR) /* Gotta be WinCE */ - } - } - Return(OSVR) - } - - Method(_PIC, 0x01, NotSerialized) - { - If (Arg0) - { - \_SB.CIRQ() - } - Store(Arg0, PMOD) - } - Method(CIRQ, 0x00, NotSerialized){ - Store(0, PINA) - Store(0, PINB) - Store(0, PINC) - Store(0, PIND) - Store(0, PINE) - Store(0, PINF) - Store(0, PING) - Store(0, PINH) - } - - Name(IRQB, ResourceTemplate(){ - IRQ(Level,ActiveLow,Shared){15} - }) - - Name(IRQP, ResourceTemplate(){ - IRQ(Level,ActiveLow,Exclusive){3, 4, 5, 7, 10, 11, 12, 15} - }) - - Name(PITF, ResourceTemplate(){ - IRQ(Level,ActiveLow,Exclusive){9} - }) - - Device(INTA) { - Name(_HID, EISAID("PNP0C0F")) - Name(_UID, 1) - - Method(_STA, 0) { - if (PINA) { - Return(0x0B) /* sata is invisible */ - } else { - Return(0x09) /* sata is disabled */ - } - } /* End Method(_SB.INTA._STA) */ - - Method(_DIS ,0) { - /* DBGO("\\_SB\\LNKA\\_DIS\n") */ - Store(0, PINA) - } /* End Method(_SB.INTA._DIS) */ - - Method(_PRS ,0) { - /* DBGO("\\_SB\\LNKA\\_PRS\n") */ - Return(IRQP) - } /* Method(_SB.INTA._PRS) */ - - Method(_CRS ,0) { - /* DBGO("\\_SB\\LNKA\\_CRS\n") */ - CreateWordField(IRQB, 0x1, IRQN) - ShiftLeft(1, PINA, IRQN) - Return(IRQB) - } /* Method(_SB.INTA._CRS) */ - - Method(_SRS, 1) { - /* DBGO("\\_SB\\LNKA\\_CRS\n") */ - CreateWordField(ARG0, 1, IRQM) - - /* Use lowest available IRQ */ - FindSetRightBit(IRQM, Local0) - if (Local0) { - Decrement(Local0) - } - Store(Local0, PINA) - } /* End Method(_SB.INTA._SRS) */ - } /* End Device(INTA) */ - - Device(INTB) { - Name(_HID, EISAID("PNP0C0F")) - Name(_UID, 2) - - Method(_STA, 0) { - if (PINB) { - Return(0x0B) /* sata is invisible */ - } else { - Return(0x09) /* sata is disabled */ - } - } /* End Method(_SB.INTB._STA) */ - - Method(_DIS ,0) { - /* DBGO("\\_SB\\LNKB\\_DIS\n") */ - Store(0, PINB) - } /* End Method(_SB.INTB._DIS) */ - - Method(_PRS ,0) { - /* DBGO("\\_SB\\LNKB\\_PRS\n") */ - Return(IRQP) - } /* Method(_SB.INTB._PRS) */ - - Method(_CRS ,0) { - /* DBGO("\\_SB\\LNKB\\_CRS\n") */ - CreateWordField(IRQB, 0x1, IRQN) - ShiftLeft(1, PINB, IRQN) - Return(IRQB) - } /* Method(_SB.INTB._CRS) */ - - Method(_SRS, 1) { - /* DBGO("\\_SB\\LNKB\\_CRS\n") */ - CreateWordField(ARG0, 1, IRQM) - - /* Use lowest available IRQ */ - FindSetRightBit(IRQM, Local0) - if (Local0) { - Decrement(Local0) - } - Store(Local0, PINB) - } /* End Method(_SB.INTB._SRS) */ - } /* End Device(INTB) */ - - Device(INTC) { - Name(_HID, EISAID("PNP0C0F")) - Name(_UID, 3) - - Method(_STA, 0) { - if (PINC) { - Return(0x0B) /* sata is invisible */ - } else { - Return(0x09) /* sata is disabled */ - } - } /* End Method(_SB.INTC._STA) */ - - Method(_DIS ,0) { - /* DBGO("\\_SB\\LNKC\\_DIS\n") */ - Store(0, PINC) - } /* End Method(_SB.INTC._DIS) */ - - Method(_PRS ,0) { - /* DBGO("\\_SB\\LNKC\\_PRS\n") */ - Return(IRQP) - } /* Method(_SB.INTC._PRS) */ - - Method(_CRS ,0) { - /* DBGO("\\_SB\\LNKC\\_CRS\n") */ - CreateWordField(IRQB, 0x1, IRQN) - ShiftLeft(1, PINC, IRQN) - Return(IRQB) - } /* Method(_SB.INTC._CRS) */ - - Method(_SRS, 1) { - /* DBGO("\\_SB\\LNKC\\_CRS\n") */ - CreateWordField(ARG0, 1, IRQM) - - /* Use lowest available IRQ */ - FindSetRightBit(IRQM, Local0) - if (Local0) { - Decrement(Local0) - } - Store(Local0, PINC) - } /* End Method(_SB.INTC._SRS) */ - } /* End Device(INTC) */ - - Device(INTD) { - Name(_HID, EISAID("PNP0C0F")) - Name(_UID, 4) - - Method(_STA, 0) { - if (PIND) { - Return(0x0B) /* sata is invisible */ - } else { - Return(0x09) /* sata is disabled */ - } - } /* End Method(_SB.INTD._STA) */ - - Method(_DIS ,0) { - /* DBGO("\\_SB\\LNKD\\_DIS\n") */ - Store(0, PIND) - } /* End Method(_SB.INTD._DIS) */ - - Method(_PRS ,0) { - /* DBGO("\\_SB\\LNKD\\_PRS\n") */ - Return(IRQP) - } /* Method(_SB.INTD._PRS) */ - - Method(_CRS ,0) { - /* DBGO("\\_SB\\LNKD\\_CRS\n") */ - CreateWordField(IRQB, 0x1, IRQN) - ShiftLeft(1, PIND, IRQN) - Return(IRQB) - } /* Method(_SB.INTD._CRS) */ - - Method(_SRS, 1) { - /* DBGO("\\_SB\\LNKD\\_CRS\n") */ - CreateWordField(ARG0, 1, IRQM) - - /* Use lowest available IRQ */ - FindSetRightBit(IRQM, Local0) - if (Local0) { - Decrement(Local0) - } - Store(Local0, PIND) - } /* End Method(_SB.INTD._SRS) */ - } /* End Device(INTD) */ - - Device(INTE) { - Name(_HID, EISAID("PNP0C0F")) - Name(_UID, 5) - - Method(_STA, 0) { - if (PINE) { - Return(0x0B) /* sata is invisible */ - } else { - Return(0x09) /* sata is disabled */ - } - } /* End Method(_SB.INTE._STA) */ - - Method(_DIS ,0) { - /* DBGO("\\_SB\\LNKE\\_DIS\n") */ - Store(0, PINE) - } /* End Method(_SB.INTE._DIS) */ - - Method(_PRS ,0) { - /* DBGO("\\_SB\\LNKE\\_PRS\n") */ - Return(IRQP) - } /* Method(_SB.INTE._PRS) */ - - Method(_CRS ,0) { - /* DBGO("\\_SB\\LNKE\\_CRS\n") */ - CreateWordField(IRQB, 0x1, IRQN) - ShiftLeft(1, PINE, IRQN) - Return(IRQB) - } /* Method(_SB.INTE._CRS) */ - - Method(_SRS, 1) { - /* DBGO("\\_SB\\LNKE\\_CRS\n") */ - CreateWordField(ARG0, 1, IRQM) - - /* Use lowest available IRQ */ - FindSetRightBit(IRQM, Local0) - if (Local0) { - Decrement(Local0) - } - Store(Local0, PINE) - } /* End Method(_SB.INTE._SRS) */ - } /* End Device(INTE) */ - - Device(INTF) { - Name(_HID, EISAID("PNP0C0F")) - Name(_UID, 6) - - Method(_STA, 0) { - if (PINF) { - Return(0x0B) /* sata is invisible */ - } else { - Return(0x09) /* sata is disabled */ - } - } /* End Method(_SB.INTF._STA) */ - - Method(_DIS ,0) { - /* DBGO("\\_SB\\LNKF\\_DIS\n") */ - Store(0, PINF) - } /* End Method(_SB.INTF._DIS) */ - - Method(_PRS ,0) { - /* DBGO("\\_SB\\LNKF\\_PRS\n") */ - Return(PITF) - } /* Method(_SB.INTF._PRS) */ - - Method(_CRS ,0) { - /* DBGO("\\_SB\\LNKF\\_CRS\n") */ - CreateWordField(IRQB, 0x1, IRQN) - ShiftLeft(1, PINF, IRQN) - Return(IRQB) - } /* Method(_SB.INTF._CRS) */ - - Method(_SRS, 1) { - /* DBGO("\\_SB\\LNKF\\_CRS\n") */ - CreateWordField(ARG0, 1, IRQM) - - /* Use lowest available IRQ */ - FindSetRightBit(IRQM, Local0) - if (Local0) { - Decrement(Local0) - } - Store(Local0, PINF) - } /* End Method(_SB.INTF._SRS) */ - } /* End Device(INTF) */ - - Device(INTG) { - Name(_HID, EISAID("PNP0C0F")) - Name(_UID, 7) - - Method(_STA, 0) { - if (PING) { - Return(0x0B) /* sata is invisible */ - } else { - Return(0x09) /* sata is disabled */ - } - } /* End Method(_SB.INTG._STA) */ - - Method(_DIS ,0) { - /* DBGO("\\_SB\\LNKG\\_DIS\n") */ - Store(0, PING) - } /* End Method(_SB.INTG._DIS) */ - - Method(_PRS ,0) { - /* DBGO("\\_SB\\LNKG\\_PRS\n") */ - Return(IRQP) - } /* Method(_SB.INTG._CRS) */ - - Method(_CRS ,0) { - /* DBGO("\\_SB\\LNKG\\_CRS\n") */ - CreateWordField(IRQB, 0x1, IRQN) - ShiftLeft(1, PING, IRQN) - Return(IRQB) - } /* Method(_SB.INTG._CRS) */ - - Method(_SRS, 1) { - /* DBGO("\\_SB\\LNKG\\_CRS\n") */ - CreateWordField(ARG0, 1, IRQM) - - /* Use lowest available IRQ */ - FindSetRightBit(IRQM, Local0) - if (Local0) { - Decrement(Local0) - } - Store(Local0, PING) - } /* End Method(_SB.INTG._SRS) */ - } /* End Device(INTG) */ - - Device(INTH) { - Name(_HID, EISAID("PNP0C0F")) - Name(_UID, 8) - - Method(_STA, 0) { - if (PINH) { - Return(0x0B) /* sata is invisible */ - } else { - Return(0x09) /* sata is disabled */ - } - } /* End Method(_SB.INTH._STA) */ - - Method(_DIS ,0) { - /* DBGO("\\_SB\\LNKH\\_DIS\n") */ - Store(0, PINH) - } /* End Method(_SB.INTH._DIS) */ - - Method(_PRS ,0) { - /* DBGO("\\_SB\\LNKH\\_PRS\n") */ - Return(IRQP) - } /* Method(_SB.INTH._CRS) */ - - Method(_CRS ,0) { - /* DBGO("\\_SB\\LNKH\\_CRS\n") */ - CreateWordField(IRQB, 0x1, IRQN) - ShiftLeft(1, PINH, IRQN) - Return(IRQB) - } /* Method(_SB.INTH._CRS) */ - - Method(_SRS, 1) { - /* DBGO("\\_SB\\LNKH\\_CRS\n") */ - CreateWordField(ARG0, 1, IRQM) - - /* Use lowest available IRQ */ - FindSetRightBit(IRQM, Local0) - if (Local0) { - Decrement(Local0) - } - Store(Local0, PINH) - } /* End Method(_SB.INTH._SRS) */ - } /* End Device(INTH) */ - - } /* End Scope(_SB) */ - - #include - - /* Wake status package */ - Name(WKST,Package(){Zero, Zero}) - - /* - * \_PTS - Prepare to Sleep method - * - * Entry: - * Arg0=The value of the sleeping state S1=1, S2=2, etc - * - * Exit: - * -none- - * - * The _PTS control method is executed at the beginning of the sleep process - * for S1-S5. The sleeping value is passed to the _PTS control method. This - * control method may be executed a relatively long time before entering the - * sleep state and the OS may abort the operation without notification to - * the ACPI driver. This method cannot modify the configuration or power - * state of any device in the system. - */ - Method(\_PTS, 1) { - /* DBGO("\\_PTS\n") */ - /* DBGO("From S0 to S") */ - /* DBGO(Arg0) */ - /* DBGO("\n") */ - - /* Don't allow PCIRST# to reset USB */ - if (LEqual(Arg0,3)){ - Store(0,URRE) - } - - /* Clear sleep SMI status flag and enable sleep SMI trap. */ - /*Store(One, CSSM) - Store(One, SSEN)*/ - - /* On older chips, clear PciExpWakeDisEn */ - /*if (LLessEqual(\_SB.SBRI, 0x13)) { - * Store(0,\_SB.PWDE) - *} - */ - - /* Clear wake status structure. */ - Store(0, Index(WKST,0)) - Store(0, Index(WKST,1)) - \_SB.PCI0.SIOS (Arg0) - } /* End Method(\_PTS) */ - - /* - * The following method results in a "not a valid reserved NameSeg" - * warning so I have commented it out for the duration. It isn't - * used, so it could be removed. - * - * - * \_GTS OEM Going To Sleep method - * - * Entry: - * Arg0=The value of the sleeping state S1=1, S2=2 - * - * Exit: - * -none- - * - * Method(\_GTS, 1) { - * DBGO("\\_GTS\n") - * DBGO("From S0 to S") - * DBGO(Arg0) - * DBGO("\n") - * } - */ - - /* - * \_BFS OEM Back From Sleep method - * - * Entry: - * Arg0=The value of the sleeping state S1=1, S2=2 - * - * Exit: - * -none- - */ - Method(\_BFS, 1) { - /* DBGO("\\_BFS\n") */ - /* DBGO("From S") */ - /* DBGO(Arg0) */ - /* DBGO(" to S0\n") */ - } - - /* - * \_WAK System Wake method - * - * Entry: - * Arg0=The value of the sleeping state S1=1, S2=2 - * - * Exit: - * Return package of 2 DWords - * Dword 1 - Status - * 0x00000000 wake succeeded - * 0x00000001 Wake was signaled but failed due to lack of power - * 0x00000002 Wake was signaled but failed due to thermal condition - * Dword 2 - Power Supply state - * if non-zero the effective S-state the power supply entered - */ - Method(\_WAK, 1) { - /* DBGO("\\_WAK\n") */ - /* DBGO("From S") */ - /* DBGO(Arg0) */ - /* DBGO(" to S0\n") */ - - /* Re-enable HPET */ - Store(1,HPDE) - - /* Restore PCIRST# so it resets USB */ - if (LEqual(Arg0,3)){ - Store(1,URRE) - } - - /* Arbitrarily clear PciExpWakeStatus */ - Store(PWST, Local1) - Store(Local1, PWST) - - /* if (DeRefOf(Index(WKST,0))) { - * Store(0, Index(WKST,1)) - * } else { - * Store(Arg0, Index(WKST,1)) - * } - */ - \_SB.PCI0.SIOW () - Return(WKST) - } /* End Method(\_WAK) */ - - Scope(\_GPE) { /* Start Scope GPE */ - /* General event 0 */ - /* Method(_L00) { - * DBGO("\\_GPE\\_L00\n") - * } - */ - - /* General event 1 */ - /* Method(_L01) { - * DBGO("\\_GPE\\_L00\n") - * } - */ - - /* General event 2 */ - /* Method(_L02) { - * DBGO("\\_GPE\\_L00\n") - * } - */ - - /* General event 3 */ - Method(_L03) { - /* DBGO("\\_GPE\\_L00\n") */ - Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ - } - - /* General event 4 */ - /* Method(_L04) { - * DBGO("\\_GPE\\_L00\n") - * } - */ - - /* General event 5 */ - /* Method(_L05) { - * DBGO("\\_GPE\\_L00\n") - * } - */ - - /* General event 6 - Used for GPM6, moved to USB.asl */ - /* Method(_L06) { - * DBGO("\\_GPE\\_L00\n") - * } - */ - - /* General event 7 - Used for GPM7, moved to USB.asl */ - /* Method(_L07) { - * DBGO("\\_GPE\\_L07\n") - * } - */ - - /* Legacy PM event */ - Method(_L08) { - /* DBGO("\\_GPE\\_L08\n") */ - } - - /* Temp warning (TWarn) event */ - Method(_L09) { - /* DBGO("\\_GPE\\_L09\n") */ - Notify (\_TZ.TZ00, 0x80) - } - - /* Reserved */ - /* Method(_L0A) { - * DBGO("\\_GPE\\_L0A\n") - * } - */ - - /* USB controller PME# */ - Method(_L0B) { - /* DBGO("\\_GPE\\_L0B\n") */ - Notify(\_SB.PCI0.UOH1, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(\_SB.PCI0.UOH2, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(\_SB.PCI0.UOH3, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(\_SB.PCI0.UOH4, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(\_SB.PCI0.UOH5, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(\_SB.PCI0.UEH1, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ - } - - /* AC97 controller PME# */ - /* Method(_L0C) { - * DBGO("\\_GPE\\_L0C\n") - * } - */ - - /* OtherTherm PME# */ - /* Method(_L0D) { - * DBGO("\\_GPE\\_L0D\n") - * } - */ - - /* GPM9 SCI event - Moved to USB.asl */ - /* Method(_L0E) { - * DBGO("\\_GPE\\_L0E\n") - * } - */ - - /* PCIe HotPlug event */ - /* Method(_L0F) { - * DBGO("\\_GPE\\_L0F\n") - * } - */ - - /* ExtEvent0 SCI event */ - Method(_L10) { - /* DBGO("\\_GPE\\_L10\n") */ - } - - - /* ExtEvent1 SCI event */ - Method(_L11) { - /* DBGO("\\_GPE\\_L11\n") */ - } - - /* PCIe PME# event */ - /* Method(_L12) { - * DBGO("\\_GPE\\_L12\n") - * } - */ - - /* GPM0 SCI event - Moved to USB.asl */ - /* Method(_L13) { - * DBGO("\\_GPE\\_L13\n") - * } - */ - - /* GPM1 SCI event - Moved to USB.asl */ - /* Method(_L14) { - * DBGO("\\_GPE\\_L14\n") - * } - */ - - /* GPM2 SCI event - Moved to USB.asl */ - /* Method(_L15) { - * DBGO("\\_GPE\\_L15\n") - * } - */ - - /* GPM3 SCI event - Moved to USB.asl */ - /* Method(_L16) { - * DBGO("\\_GPE\\_L16\n") - * } - */ - - /* GPM8 SCI event - Moved to USB.asl */ - /* Method(_L17) { - * DBGO("\\_GPE\\_L17\n") - * } - */ - - /* GPIO0 or GEvent8 event */ - Method(_L18) { - /* DBGO("\\_GPE\\_L18\n") */ - Notify(\_SB.PCI0.PBR2, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(\_SB.PCI0.PBR4, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(\_SB.PCI0.PBR5, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(\_SB.PCI0.PBR6, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(\_SB.PCI0.PBR7, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ - } - - /* GPM4 SCI event - Moved to USB.asl */ - /* Method(_L19) { - * DBGO("\\_GPE\\_L19\n") - * } - */ - - /* GPM5 SCI event - Moved to USB.asl */ - /* Method(_L1A) { - * DBGO("\\_GPE\\_L1A\n") - * } - */ - - /* Azalia SCI event */ - Method(_L1B) { - /* DBGO("\\_GPE\\_L1B\n") */ - Notify(\_SB.PCI0.AZHD, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ - } - - /* GPM6 SCI event - Reassigned to _L06 */ - /* Method(_L1C) { - * DBGO("\\_GPE\\_L1C\n") - * } - */ - - /* GPM7 SCI event - Reassigned to _L07 */ - /* Method(_L1D) { - * DBGO("\\_GPE\\_L1D\n") - * } - */ - - /* GPIO2 or GPIO66 SCI event */ - /* Method(_L1E) { - * DBGO("\\_GPE\\_L1E\n") - * } - */ - - /* SATA SCI event - Moved to sata.asl */ - /* Method(_L1F) { - * DBGO("\\_GPE\\_L1F\n") - * } - */ - - } /* End Scope GPE */ - - #include "acpi/usb.asl" - - /* System Bus */ - Scope(\_SB) { /* Start \_SB scope */ - #include /* global utility methods expected within the \_SB scope */ - - /* _SB.PCI0 */ - /* Note: Only need HID on Primary Bus */ - Device(PCI0) { - External (TOM1) - External (TOM2) /* ( >> 20) to make it fit into 32 bit for XP */ - Name(_HID, EISAID("PNP0A03")) - Name(_ADR, 0x00180000) /* Dev# = BSP Dev#, Func# = 0 */ - Method(_BBN, 0) { /* Bus number = 0 */ - Return(0) - } - Method(_STA, 0) { - /* DBGO("\\_SB\\PCI0\\_STA\n") */ - Return(0x0B) /* Status is visible */ - } - - Method(_PRT,0) { - If(PMOD){ Return(APR0) } /* APIC mode */ - Return (PR0) /* PIC Mode */ - } /* end _PRT */ - - /* Describe the Northbridge devices */ - Device(AMRT) { - Name(_ADR, 0x00000000) - } /* end AMRT */ - - /* The internal GFX bridge */ - Device(AGPB) { - Name(_ADR, 0x00010000) - Name(_PRW, Package() {0x18, 4}) - Method(_PRT,0) { - Return (APR1) - } - } /* end AGPB */ - - /* The external GFX bridge */ - Device(PBR2) { - Name(_ADR, 0x00020000) - Name(_PRW, Package() {0x18, 4}) - Method(_PRT,0) { - If(PMOD){ Return(APS2) } /* APIC mode */ - Return (PS2) /* PIC Mode */ - } /* end _PRT */ - } /* end PBR2 */ - - /* Dev3 is also an external GFX bridge, not used in Herring */ - - Device(PBR4) { - Name(_ADR, 0x00040000) - Name(_PRW, Package() {0x18, 4}) - Method(_PRT,0) { - If(PMOD){ Return(APS4) } /* APIC mode */ - Return (PS4) /* PIC Mode */ - } /* end _PRT */ - } /* end PBR4 */ - - Device(PBR5) { - Name(_ADR, 0x00050000) - Name(_PRW, Package() {0x18, 4}) - Method(_PRT,0) { - If(PMOD){ Return(APS5) } /* APIC mode */ - Return (PS5) /* PIC Mode */ - } /* end _PRT */ - } /* end PBR5 */ - - Device(PBR6) { - Name(_ADR, 0x00060000) - Name(_PRW, Package() {0x18, 4}) - Method(_PRT,0) { - If(PMOD){ Return(APS6) } /* APIC mode */ - Return (PS6) /* PIC Mode */ - } /* end _PRT */ - } /* end PBR6 */ - - /* The onboard EtherNet chip */ - Device(PBR7) { - Name(_ADR, 0x00070000) - Name(_PRW, Package() {0x18, 4}) - Method(_PRT,0) { - If(PMOD){ Return(APS7) } /* APIC mode */ - Return (PS7) /* PIC Mode */ - } /* end _PRT */ - } /* end PBR7 */ - - /* GPP */ - Device(PBR9) { - Name(_ADR, 0x00090000) - Name(_PRW, Package() {0x18, 4}) - Method(_PRT,0) { - If(PMOD){ Return(APS9) } /* APIC mode */ - Return (PS9) /* PIC Mode */ - } /* end _PRT */ - } /* end PBR9 */ - - Device(PBRa) { - Name(_ADR, 0x000A0000) - Name(_PRW, Package() {0x18, 4}) - Method(_PRT,0) { - If(PMOD){ Return(APSa) } /* APIC mode */ - Return (PSa) /* PIC Mode */ - } /* end _PRT */ - } /* end PBRa */ - - - /* PCI slot 1, 2, 3 */ - Device(PIBR) { - Name(_ADR, 0x00140004) - Name(_PRW, Package() {0x18, 4}) - - Method(_PRT, 0) { - Return (PCIB) - } - } - - /* Describe the Southbridge devices */ - Device(STCR) { - Name(_ADR, 0x00110000) - #include "acpi/sata.asl" - } /* end STCR */ - - Device(UOH1) { - Name(_ADR, 0x00130000) - Name(_PRW, Package() {0x0B, 3}) - } /* end UOH1 */ - - Device(UOH2) { - Name(_ADR, 0x00130001) - Name(_PRW, Package() {0x0B, 3}) - } /* end UOH2 */ - - Device(UOH3) { - Name(_ADR, 0x00130002) - Name(_PRW, Package() {0x0B, 3}) - } /* end UOH3 */ - - Device(UOH4) { - Name(_ADR, 0x00130003) - Name(_PRW, Package() {0x0B, 3}) - } /* end UOH4 */ - - Device(UOH5) { - Name(_ADR, 0x00130004) - Name(_PRW, Package() {0x0B, 3}) - } /* end UOH5 */ - - Device(UEH1) { - Name(_ADR, 0x00130005) - Name(_PRW, Package() {0x0B, 3}) - } /* end UEH1 */ - - Device(SBUS) { - Name(_ADR, 0x00140000) - } /* end SBUS */ - - /* Primary (and only) IDE channel */ - Device(IDEC) { - Name(_ADR, 0x00140001) - #include "acpi/ide.asl" - } /* end IDEC */ - - Device(AZHD) { - Name(_ADR, 0x00140002) - OperationRegion(AZPD, PCI_Config, 0x00, 0x100) - Field(AZPD, AnyAcc, NoLock, Preserve) { - offset (0x42), - NSDI, 1, - NSDO, 1, - NSEN, 1, - offset (0x44), - IPCR, 4, - offset (0x54), - PWST, 2, - , 6, - PMEB, 1, - , 6, - PMST, 1, - offset (0x62), - MMCR, 1, - offset (0x64), - MMLA, 32, - offset (0x68), - MMHA, 32, - offset (0x6C), - MMDT, 16, - } - - Method(_INI) { - If(LEqual(OSVR,3)){ /* If we are running Linux */ - Store(zero, NSEN) - Store(one, NSDO) - Store(one, NSDI) - } - } - } /* end AZHD */ - - Device(LIBR) { - Name(_ADR, 0x00140003) - /* Method(_INI) { - * DBGO("\\_SB\\PCI0\\LpcIsaBr\\_INI\n") - } */ /* End Method(_SB.SBRDG._INI) */ - - /* Real Time Clock Device */ - Device(RTC0) { - Name(_HID, EISAID("PNP0B00")) /* AT Real Time Clock (not PIIX4 compatible) */ - Name(_CRS, ResourceTemplate() { - IRQNoFlags(){8} - IO(Decode16,0x0070, 0x0070, 0, 2) - /* IO(Decode16,0x0070, 0x0070, 0, 4) */ - }) - } /* End Device(_SB.PCI0.LpcIsaBr.RTC0) */ - - Device(TMR) { /* Timer */ - Name(_HID,EISAID("PNP0100")) /* System Timer */ - Name(_CRS, ResourceTemplate() { - IRQNoFlags(){0} - IO(Decode16, 0x0040, 0x0040, 0, 4) - /* IO(Decode16, 0x0048, 0x0048, 0, 4) */ - }) - } /* End Device(_SB.PCI0.LpcIsaBr.TMR) */ - - Device(SPKR) { /* Speaker */ - Name(_HID,EISAID("PNP0800")) /* AT style speaker */ - Name(_CRS, ResourceTemplate() { - IO(Decode16, 0x0061, 0x0061, 0, 1) - }) - } /* End Device(_SB.PCI0.LpcIsaBr.SPKR) */ - - Device(PIC) { - Name(_HID,EISAID("PNP0000")) /* AT Interrupt Controller */ - Name(_CRS, ResourceTemplate() { - IRQNoFlags(){2} - IO(Decode16,0x0020, 0x0020, 0, 2) - IO(Decode16,0x00A0, 0x00A0, 0, 2) - /* IO(Decode16, 0x00D0, 0x00D0, 0x10, 0x02) */ - /* IO(Decode16, 0x04D0, 0x04D0, 0x10, 0x02) */ - }) - } /* End Device(_SB.PCI0.LpcIsaBr.PIC) */ - - Device(MAD) { /* 8257 DMA */ - Name(_HID,EISAID("PNP0200")) /* Hardware Device ID */ - Name(_CRS, ResourceTemplate() { - DMA(Compatibility,BusMaster,Transfer8){4} - IO(Decode16, 0x0000, 0x0000, 0x10, 0x10) - IO(Decode16, 0x0081, 0x0081, 0x01, 0x03) - IO(Decode16, 0x0087, 0x0087, 0x01, 0x01) - IO(Decode16, 0x0089, 0x0089, 0x01, 0x03) - IO(Decode16, 0x008F, 0x008F, 0x01, 0x01) - IO(Decode16, 0x00C0, 0x00C0, 0x10, 0x20) - }) /* End Name(_SB.PCI0.LpcIsaBr.MAD._CRS) */ - } /* End Device(_SB.PCI0.LpcIsaBr.MAD) */ - - Device(COPR) { - Name(_HID,EISAID("PNP0C04")) /* Math Coprocessor */ - Name(_CRS, ResourceTemplate() { - IO(Decode16, 0x00F0, 0x00F0, 0, 0x10) - IRQNoFlags(){13} - }) - } /* End Device(_SB.PCI0.LpcIsaBr.COPR) */ - - Device(HPTM) { - Name(_HID,EISAID("PNP0103")) - Name(CRS,ResourceTemplate() { - Memory32Fixed(ReadOnly,0xFED00000, 0x00000400, HPT) /* 1kb reserved space */ - }) - Method(_STA, 0) { - Return(0x0F) /* sata is visible */ - } - Method(_CRS, 0) { - CreateDwordField(CRS, ^HPT._BAS, HPBX) - Store(HPBA, HPBX) - Return(CRS) - } - } /* End Device(_SB.PCI0.LpcIsaBr.COPR) */ - } /* end LIBR */ - - Device(HPBR) { - Name(_ADR, 0x00140004) - } /* end HostPciBr */ - - Device(ACAD) { - Name(_ADR, 0x00140005) - } /* end Ac97audio */ - - Device(ACMD) { - Name(_ADR, 0x00140006) - } /* end Ac97modem */ - - /* ITE8718 Support */ - OperationRegion (IOID, SystemIO, 0x2E, 0x02) /* sometimes it is 0x4E */ - Field (IOID, ByteAcc, NoLock, Preserve) - { - SIOI, 8, SIOD, 8 /* 0x2E and 0x2F */ - } - - IndexField (SIOI, SIOD, ByteAcc, NoLock, Preserve) - { - Offset (0x07), - LDN, 8, /* Logical Device Number */ - Offset (0x20), - CID1, 8, /* Chip ID Byte 1, 0x87 */ - CID2, 8, /* Chip ID Byte 2, 0x12 */ - Offset (0x30), - ACTR, 8, /* Function activate */ - Offset (0xF0), - APC0, 8, /* APC/PME Event Enable Register */ - APC1, 8, /* APC/PME Status Register */ - APC2, 8, /* APC/PME Control Register 1 */ - APC3, 8, /* Environment Controller Special Configuration Register */ - APC4, 8 /* APC/PME Control Register 2 */ - } - - /* Enter the 8718 MB PnP Mode */ - Method (EPNP) - { - Store(0x87, SIOI) - Store(0x01, SIOI) - Store(0x55, SIOI) - Store(0x55, SIOI) /* 8718 magic number */ - } - /* Exit the 8718 MB PnP Mode */ - Method (XPNP) - { - Store (0x02, SIOI) - Store (0x02, SIOD) - } - /* - * Keyboard PME is routed to SB700 Gevent3. We can wake - * up the system by pressing the key. - */ - Method (SIOS, 1) - { - /* We only enable KBD PME for S5. */ - If (LLess (Arg0, 0x05)) - { - EPNP() - /* DBGO("8718F\n") */ - - Store (0x4, LDN) - Store (One, ACTR) /* Enable EC */ - /* - Store (0x4, LDN) - Store (0x04, APC4) - */ /* falling edge. which mode? Not sure. */ - - Store (0x4, LDN) - Store (0x08, APC1) /* clear PME status, Use 0x18 for mouse & KBD */ - Store (0x4, LDN) - Store (0x08, APC0) /* enable PME, Use 0x18 for mouse & KBD */ - - XPNP() - } - } - Method (SIOW, 0) - { - EPNP() - Store (0x4, LDN) - Store (Zero, APC0) /* disable keyboard PME */ - Store (0x4, LDN) - Store (0xFF, APC1) /* clear keyboard PME status */ - XPNP() - } - - Name(CRES, ResourceTemplate() { - IO(Decode16, 0x0CF8, 0x0CF8, 1, 8) - - WORDIO(ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, - 0x0000, /* address granularity */ - 0x0000, /* range minimum */ - 0x0CF7, /* range maximum */ - 0x0000, /* translation */ - 0x0CF8 /* length */ - ) - - WORDIO(ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, - 0x0000, /* address granularity */ - 0x0D00, /* range minimum */ - 0xFFFF, /* range maximum */ - 0x0000, /* translation */ - 0xF300 /* length */ - ) - - Memory32Fixed(READWRITE, 0, 0xA0000, BSMM) - Memory32Fixed(READONLY, 0x000A0000, 0x00020000, VGAM) /* VGA memory space */ - Memory32Fixed(READONLY, 0x000C0000, 0x00020000, EMM1) /* Assume C0000-E0000 empty */ - Memory32Fixed(READONLY, 0x000E0000, 0x00020000, RDBS) /* BIOS ROM area */ - - /* DRAM Memory from 1MB to TopMem */ - Memory32Fixed(READWRITE, 0x00100000, 0, DMLO) /* 1MB to TopMem */ - - /* BIOS space just below 4GB */ - DWORDMemory( - ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite, - 0x00, /* Granularity */ - 0x00000000, /* Min */ - 0x00000000, /* Max */ - 0x00000000, /* Translation */ - 0x00000001, /* Max-Min, RLEN */ - ,, - PCBM - ) - - /* DRAM memory from 4GB to TopMem2 */ - QWORDMemory(ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite, - 0x00000000, /* Granularity */ - 0x00000000, /* Min */ - 0x00000000, /* Max */ - 0x00000000, /* Translation */ - 0x00000001, /* Max-Min, RLEN */ - ,, - DMHI - ) - - /* BIOS space just below 16EB */ - QWORDMemory(ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite, - 0x00000000, /* Granularity */ - 0x00000000, /* Min */ - 0x00000000, /* Max */ - 0x00000000, /* Translation */ - 0x00000001, /* Max-Min, RLEN */ - ,, - PEBM - ) - - }) /* End Name(_SB.PCI0.CRES) */ - - Method(_CRS, 0) { - /* DBGO("\\_SB\\PCI0\\_CRS\n") */ - - CreateDWordField(CRES, ^EMM1._BAS, EM1B) - CreateDWordField(CRES, ^EMM1._LEN, EM1L) - CreateDWordField(CRES, ^DMLO._BAS, DMLB) - CreateDWordField(CRES, ^DMLO._LEN, DMLL) - CreateDWordField(CRES, ^PCBM._MIN, PBMB) - CreateDWordField(CRES, ^PCBM._LEN, PBML) - - CreateQWordField(CRES, ^DMHI._MIN, DMHB) - CreateQWordField(CRES, ^DMHI._LEN, DMHL) - CreateQWordField(CRES, ^PEBM._MIN, EBMB) - CreateQWordField(CRES, ^PEBM._LEN, EBML) - - If(LGreater(LOMH, 0xC0000)){ - Store(0xC0000, EM1B) /* Hole above C0000 and below E0000 */ - Subtract(LOMH, 0xC0000, EM1L) /* subtract start, assumes allocation from C0000 going up */ - } - - /* Set size of memory from 1MB to TopMem */ - Subtract(TOM1, 0x100000, DMLL) - - /* - * If(LNotEqual(TOM2, 0x00000000)){ - * Store(0x100000000,DMHB) DRAM from 4GB to TopMem2 - * ShiftLeft(TOM2, 20, Local0) - * Subtract(Local0, 0x100000000, DMHL) - * } - */ - - /* If there is no memory above 4GB, put the BIOS just below 4GB */ - If(LEqual(TOM2, 0x00000000)){ - Store(PBAD,PBMB) /* Reserve the "BIOS" space */ - Store(PBLN,PBML) - } - Else { /* Otherwise, put the BIOS just below 16EB */ - ShiftLeft(PBAD,16,EBMB) /* Reserve the "BIOS" space */ - Store(PBLN,EBML) - } - - Return(CRES) /* note to change the Name buffer */ - } /* end of Method(_SB.PCI0._CRS) */ - - /* - * - * FIRST METHOD CALLED UPON BOOT - * - * 1. If debugging, print current OS and ACPI interpreter. - * 2. Get PCI Interrupt routing from ACPI VSM, this - * value is based on user choice in BIOS setup. - */ - Method(_INI, 0) { - /* DBGO("\\_SB\\_INI\n") */ - /* DBGO(" DSDT.ASL code from ") */ - /* DBGO(__DATE__) */ - /* DBGO(" ") */ - /* DBGO(__TIME__) */ - /* DBGO("\n Sleep states supported: ") */ - /* DBGO("\n") */ - /* DBGO(" \\_OS=") */ - /* DBGO(\_OS) */ - /* DBGO("\n \\_REV=") */ - /* DBGO(\_REV) */ - /* DBGO("\n") */ - - /* Determine the OS we're running on */ - OSFL() - - /* On older chips, clear PciExpWakeDisEn */ - /*if (LLessEqual(\SBRI, 0x13)) { - * Store(0,\PWDE) - * } - */ - } /* End Method(_SB._INI) */ - } /* End Device(PCI0) */ - - Device(PWRB) { /* Start Power button device */ - Name(_HID, EISAID("PNP0C0C")) - Name(_UID, 0xAA) - Name(_PRW, Package () {3, 0x04}) /* wake from S1-S4 */ - Name(_STA, 0x0B) /* sata is invisible */ - } - } /* End \_SB scope */ - - Scope(\_SI) { - Method(_SST, 1) { - /* DBGO("\\_SI\\_SST\n") */ - /* DBGO(" New Indicator state: ") */ - /* DBGO(Arg0) */ - /* DBGO("\n") */ - } - } /* End Scope SI */ - - #include - - /* THERMAL */ - Scope(\_TZ) { - Name (KELV, 2732) - Name (THOT, 800) - Name (TCRT, 850) - - ThermalZone(TZ00) { - Method(_AC0,0) { /* Active Cooling 0 (0=highest fan speed) */ - /* DBGO("\\_TZ\\TZ00\\_AC0\n") */ - Return(Add(0, 2730)) - } - Method(_AL0,0) { /* Returns package of cooling device to turn on */ - /* DBGO("\\_TZ\\TZ00\\_AL0\n") */ - Return(Package() {\_TZ.TZ00.FAN0}) - } - Device (FAN0) { - Name(_HID, EISAID("PNP0C0B")) - Name(_PR0, Package() {PFN0}) - } - - PowerResource(PFN0,0,0) { - Method(_STA) { - Store(0xF,Local0) - Return(Local0) - } - Method(_ON) { - /* DBGO("\\_TZ\\TZ00\\FAN0 _ON\n") */ - } - Method(_OFF) { - /* DBGO("\\_TZ\\TZ00\\FAN0 _OFF\n") */ - } - } - - Method(_HOT,0) { /* return hot temp in tenths degree Kelvin */ - /* DBGO("\\_TZ\\TZ00\\_HOT\n") */ - Return (Add (THOT, KELV)) - } - Method(_CRT,0) { /* return critical temp in tenths degree Kelvin */ - /* DBGO("\\_TZ\\TZ00\\_CRT\n") */ - Return (Add (TCRT, KELV)) - } - Method(_TMP,0) { /* return current temp of this zone */ - Store (SMBR (0x07, 0x4C,, 0x00), Local0) - If (LGreater (Local0, 0x10)) { - Store (Local0, Local1) - } - Else { - Add (Local0, THOT, Local0) - Return (Add (400, KELV)) - } - - Store (SMBR (0x07, 0x4C, 0x01), Local0) - /* only the two MSBs in the external temperature low byte are used, resolution 0.25. We ignore it */ - /* Store (SMBR (0x07, 0x4C, 0x10), Local2) */ - If (LGreater (Local0, 0x10)) { - If (LGreater (Local0, Local1)) { - Store (Local0, Local1) - } - - Multiply (Local1, 10, Local1) - Return (Add (Local1, KELV)) - } - Else { - Add (Local0, THOT, Local0) - Return (Add (400 , KELV)) - } - } /* end of _TMP */ - } /* end of TZ00 */ - } -} -/* End of ASL file */ diff --git a/src/mainboard/gigabyte/ma78gm/get_bus_conf.c b/src/mainboard/gigabyte/ma78gm/get_bus_conf.c deleted file mode 100644 index ee2a6caeb9..0000000000 --- a/src/mainboard/gigabyte/ma78gm/get_bus_conf.c +++ /dev/null @@ -1,44 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2010 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include -#include - -#include - -/* Global variables for MB layouts and these will be shared by irqtable mptable -* and acpi_tables busnum is default. -*/ -u32 apicid_sb700; - -void get_bus_conf(void) -{ - u32 apicid_base; - - get_default_pci1234(1); - - sysconf.sbdn = (sysconf.hcdn[0] & 0xff); - - pirq_router_bus = (sysconf.pci1234[0] >> 16) & 0xff; - - /* I/O APICs: APIC ID Version State Address */ - if (CONFIG(LOGICAL_CPUS)) - apicid_base = get_apicid_base(1); - else - apicid_base = CONFIG_MAX_PHYSICAL_CPUS; - apicid_sb700 = apicid_base + 0; -} diff --git a/src/mainboard/gigabyte/ma78gm/irq_tables.c b/src/mainboard/gigabyte/ma78gm/irq_tables.c deleted file mode 100644 index 0f7192514e..0000000000 --- a/src/mainboard/gigabyte/ma78gm/irq_tables.c +++ /dev/null @@ -1,102 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2010 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include -#include -#include - -#include - -static void write_pirq_info(struct irq_info *pirq_info, u8 bus, u8 devfn, - u8 link0, u16 bitmap0, u8 link1, u16 bitmap1, - u8 link2, u16 bitmap2, u8 link3, u16 bitmap3, - u8 slot, u8 rfu) -{ - pirq_info->bus = bus; - pirq_info->devfn = devfn; - pirq_info->irq[0].link = link0; - pirq_info->irq[0].bitmap = bitmap0; - pirq_info->irq[1].link = link1; - pirq_info->irq[1].bitmap = bitmap1; - pirq_info->irq[2].link = link2; - pirq_info->irq[2].bitmap = bitmap2; - pirq_info->irq[3].link = link3; - pirq_info->irq[3].bitmap = bitmap3; - pirq_info->slot = slot; - pirq_info->rfu = rfu; -} - - -unsigned long write_pirq_routing_table(unsigned long addr) -{ - struct irq_routing_table *pirq; - struct irq_info *pirq_info; - u32 slot_num; - u8 *v; - - u8 sum = 0; - int i; - - /* Align the table to be 16 byte aligned. */ - addr += 15; - addr &= ~15; - - /* This table must be between 0xf0000 & 0x100000 */ - printk(BIOS_INFO, "Writing IRQ routing tables to 0x%lx...", addr); - - pirq = (void *)(addr); - v = (u8 *) (addr); - - pirq->signature = PIRQ_SIGNATURE; - pirq->version = PIRQ_VERSION; - - pirq->rtr_bus = pirq_router_bus; - pirq->rtr_devfn = PCI_DEVFN(0x14, 4); - - pirq->exclusive_irqs = 0; - - pirq->rtr_vendor = 0x1002; - pirq->rtr_device = 0x4384; - - pirq->miniport_data = 0; - - memset(pirq->rfu, 0, sizeof(pirq->rfu)); - - pirq_info = (void *)(&pirq->checksum + 1); - slot_num = 0; - - /* pci bridge */ - write_pirq_info(pirq_info, pirq_router_bus, PCI_DEVFN(0x14, 4), - 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, - 0); - pirq_info++; - slot_num++; - - pirq->size = 32 + 16 * slot_num; - - for (i = 0; i < pirq->size; i++) - sum += v[i]; - - sum = pirq->checksum - sum; - if (sum != pirq->checksum) { - pirq->checksum = sum; - } - - printk(BIOS_INFO, "write_pirq_routing_table done.\n"); - - return (unsigned long)pirq_info; -} diff --git a/src/mainboard/gigabyte/ma78gm/mainboard.c b/src/mainboard/gigabyte/ma78gm/mainboard.c deleted file mode 100644 index fb6045a6d8..0000000000 --- a/src/mainboard/gigabyte/ma78gm/mainboard.c +++ /dev/null @@ -1,76 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2010 Wang Qing Pei - * Copyright (C) 2010 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include -#include -#include -#include -#include -#include - -/* - * ma78gm-us2h uses GPIO 6 as PCIe slot reset, GPIO4 as GFX slot reset. We need to - * pull it up before training the slot. - ***/ -void set_pcie_dereset(void) -{ - u16 word; - struct device *sm_dev; - /* GPIO 6 reset PCIe slot, GPIO 4 reset GFX PCIe */ - sm_dev = pcidev_on_root(0x14, 0); - - word = pci_read_config16(sm_dev, 0xA8); - word |= (1 << 0) | (1 << 2); /* Set Gpio6,4 as output */ - word &= ~((1 << 8) | (1 << 10)); - pci_write_config16(sm_dev, 0xA8, word); -} - -void set_pcie_reset(void) -{ - u16 word; - struct device *sm_dev; - /* GPIO 6 reset PCIe slot, GPIO 4 reset GFX PCIe */ - sm_dev = pcidev_on_root(0x14, 0); - - word = pci_read_config16(sm_dev, 0xA8); - word &= ~((1 << 0) | (1 << 2)); /* Set Gpio6,4 as output */ - word &= ~((1 << 8) | (1 << 10)); - pci_write_config16(sm_dev, 0xA8, word); -} - - -int is_dev3_present(void) -{ - return 0; -} - -/************************************************* -* enable the dedicated function in board. -* This function called early than rs780_enable. -*************************************************/ -static void mainboard_enable(struct device *dev) -{ - printk(BIOS_INFO, "Mainboard MA78GM-US2H Enable. dev=0x%p\n", dev); - - set_pcie_dereset(); - /* get_ide_dma66(); */ -} - -struct chip_operations mainboard_ops = { - .enable_dev = mainboard_enable, -}; diff --git a/src/mainboard/gigabyte/ma78gm/mptable.c b/src/mainboard/gigabyte/ma78gm/mptable.c deleted file mode 100644 index 876e7ee578..0000000000 --- a/src/mainboard/gigabyte/ma78gm/mptable.c +++ /dev/null @@ -1,103 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2010 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include -#include -#include - - -extern u32 apicid_sb700; - - -static void *smp_write_config_table(void *v) -{ - struct mp_config_table *mc; - int bus_isa; - - mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); - - mptable_init(mc, LOCAL_APIC_ADDR); - - smp_write_processors(mc); - - mptable_write_buses(mc, NULL, &bus_isa); - - /* I/O APICs: APIC ID Version State Address */ - { - struct device *dev; - u32 dword; - u8 byte; - - dev = - dev_find_slot(pirq_router_bus, - PCI_DEVFN(0x14, 0)); - if (dev) { - dword = pci_read_config32(dev, 0x74) & 0xfffffff0; - smp_write_ioapic(mc, apicid_sb700, - 0x11,(void *) dword); - - /* Initialize interrupt mapping */ - /* aza */ - byte = pci_read_config8(dev, 0x63); - byte &= 0xf8; - byte |= 0; /* 0: INTA, ...., 7: INTH */ - pci_write_config8(dev, 0x63, byte); - - /* SATA */ - dword = pci_read_config32(dev, 0xac); - dword &= ~(7 << 26); - dword |= 6 << 26; /* 0: INTA, ...., 7: INTH */ - /* dword |= 1 << 22; PIC and APIC co exists */ - pci_write_config32(dev, 0xac, dword); - - /* - * 00:12.0: PROG SATA : INT F - * 00:13.0: INTA USB_0 - * 00:13.1: INTB USB_1 - * 00:13.2: INTC USB_2 - * 00:13.3: INTD USB_3 - * 00:13.4: INTC USB_4 - * 00:13.5: INTD USB2 - * 00:14.1: INTA IDE - * 00:14.2: Prog HDA : INT E - * 00:14.5: INTB ACI - * 00:14.6: INTB MCI - */ - } - } - - /* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ -#define IO_LOCAL_INT(type, intr, apicid, pin) \ - smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin)); - - mptable_add_isa_interrupts(mc, bus_isa, apicid_sb700, 0); - - /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ - IO_LOCAL_INT(mp_ExtINT, 0x0, MP_APIC_ALL, 0x0); - IO_LOCAL_INT(mp_NMI, 0x0, MP_APIC_ALL, 0x1); - /* There is no extension information... */ - - /* Compute the checksums */ - return mptable_finalize(mc); -} - -unsigned long write_smp_table(unsigned long addr) -{ - void *v; - v = smp_write_floating_table(addr, 0); - return (unsigned long)smp_write_config_table(v); -} diff --git a/src/mainboard/gigabyte/ma78gm/resourcemap.c b/src/mainboard/gigabyte/ma78gm/resourcemap.c deleted file mode 100644 index 80d2d9d05c..0000000000 --- a/src/mainboard/gigabyte/ma78gm/resourcemap.c +++ /dev/null @@ -1,279 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2010 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - - - -#include -#include - -void setup_mb_resource_map(void) -{ - static const unsigned int register_values[] = { - /* Careful set limit registers before base registers which contain the enables */ - /* DRAM Limit i Registers - * F1:0x44 i = 0 - * F1:0x4C i = 1 - * F1:0x54 i = 2 - * F1:0x5C i = 3 - * F1:0x64 i = 4 - * F1:0x6C i = 5 - * F1:0x74 i = 6 - * F1:0x7C i = 7 - * [ 2: 0] Destination Node ID - * 000 = Node 0 - * 001 = Node 1 - * 010 = Node 2 - * 011 = Node 3 - * 100 = Node 4 - * 101 = Node 5 - * 110 = Node 6 - * 111 = Node 7 - * [ 7: 3] Reserved - * [10: 8] Interleave select - * specifies the values of A[14:12] to use with interleave enable. - * [15:11] Reserved - * [31:16] DRAM Limit Address i Bits 39-24 - * This field defines the upper address bits of a 40 bit address - * that define the end of the DRAM region. - */ -// ADDRMAP_REG(0x44), 0x0000f8f8, 0x00000000, // Don't touch it, we need it for CONFIG_CAR_FAM10 - ADDRMAP_REG(0x4C), 0x0000f8f8, 0x00000001, - ADDRMAP_REG(0x54), 0x0000f8f8, 0x00000002, - ADDRMAP_REG(0x5C), 0x0000f8f8, 0x00000003, - ADDRMAP_REG(0x64), 0x0000f8f8, 0x00000004, - ADDRMAP_REG(0x6C), 0x0000f8f8, 0x00000005, - ADDRMAP_REG(0x74), 0x0000f8f8, 0x00000006, - ADDRMAP_REG(0x7C), 0x0000f8f8, 0x00000007, - /* DRAM Base i Registers - * F1:0x40 i = 0 - * F1:0x48 i = 1 - * F1:0x50 i = 2 - * F1:0x58 i = 3 - * F1:0x60 i = 4 - * F1:0x68 i = 5 - * F1:0x70 i = 6 - * F1:0x78 i = 7 - * [ 0: 0] Read Enable - * 0 = Reads Disabled - * 1 = Reads Enabled - * [ 1: 1] Write Enable - * 0 = Writes Disabled - * 1 = Writes Enabled - * [ 7: 2] Reserved - * [10: 8] Interleave Enable - * 000 = No interleave - * 001 = Interleave on A[12] (2 nodes) - * 010 = reserved - * 011 = Interleave on A[12] and A[14] (4 nodes) - * 100 = reserved - * 101 = reserved - * 110 = reserved - * 111 = Interleve on A[12] and A[13] and A[14] (8 nodes) - * [15:11] Reserved - * [13:16] DRAM Base Address i Bits 39-24 - * This field defines the upper address bits of a 40-bit address - * that define the start of the DRAM region. - */ -// ADDRMAP_REG(0x40), 0x0000f8fc, 0x00000000,// don't touch it, we need it for CONFIG_CAR_FAM10 - ADDRMAP_REG(0x48), 0x0000f8fc, 0x00000000, - ADDRMAP_REG(0x50), 0x0000f8fc, 0x00000000, - ADDRMAP_REG(0x58), 0x0000f8fc, 0x00000000, - ADDRMAP_REG(0x60), 0x0000f8fc, 0x00000000, - ADDRMAP_REG(0x68), 0x0000f8fc, 0x00000000, - ADDRMAP_REG(0x70), 0x0000f8fc, 0x00000000, - ADDRMAP_REG(0x78), 0x0000f8fc, 0x00000000, - - /* Memory-Mapped I/O Limit i Registers - * F1:0x84 i = 0 - * F1:0x8C i = 1 - * F1:0x94 i = 2 - * F1:0x9C i = 3 - * F1:0xA4 i = 4 - * F1:0xAC i = 5 - * F1:0xB4 i = 6 - * F1:0xBC i = 7 - * [ 2: 0] Destination Node ID - * 000 = Node 0 - * 001 = Node 1 - * 010 = Node 2 - * 011 = Node 3 - * 100 = Node 4 - * 101 = Node 5 - * 110 = Node 6 - * 111 = Node 7 - * [ 3: 3] Reserved - * [ 5: 4] Destination Link ID - * 00 = Link 0 - * 01 = Link 1 - * 10 = Link 2 - * 11 = Reserved - * [ 6: 6] Reserved - * [ 7: 7] Non-Posted - * 0 = CPU writes may be posted - * 1 = CPU writes must be non-posted - * [31: 8] Memory-Mapped I/O Limit Address i (39-16) - * This field defines the upp address bits of a 40-bit address that - * defines the end of a memory-mapped I/O region n - */ - ADDRMAP_REG(0x84), 0x00000048, 0x00000000, - ADDRMAP_REG(0x8C), 0x00000048, 0x00000000, - ADDRMAP_REG(0x94), 0x00000048, 0x00000000, - ADDRMAP_REG(0x9C), 0x00000048, 0x00000000, - ADDRMAP_REG(0xA4), 0x00000048, 0x00000000, - ADDRMAP_REG(0xAC), 0x00000048, 0x00000000, - ADDRMAP_REG(0xB4), 0x00000048, 0x00000000, -// ADDRMAP_REG(0xBC), 0x00000048, 0x00ffff00, - - /* Memory-Mapped I/O Base i Registers - * F1:0x80 i = 0 - * F1:0x88 i = 1 - * F1:0x90 i = 2 - * F1:0x98 i = 3 - * F1:0xA0 i = 4 - * F1:0xA8 i = 5 - * F1:0xB0 i = 6 - * F1:0xB8 i = 7 - * [ 0: 0] Read Enable - * 0 = Reads disabled - * 1 = Reads Enabled - * [ 1: 1] Write Enable - * 0 = Writes disabled - * 1 = Writes Enabled - * [ 2: 2] Cpu Disable - * 0 = Cpu can use this I/O range - * 1 = Cpu requests do not use this I/O range - * [ 3: 3] Lock - * 0 = base/limit registers i are read/write - * 1 = base/limit registers i are read-only - * [ 7: 4] Reserved - * [31: 8] Memory-Mapped I/O Base Address i (39-16) - * This field defines the upper address bits of a 40bit address - * that defines the start of memory-mapped I/O region i - */ - ADDRMAP_REG(0x80), 0x000000f0, 0x00000000, - ADDRMAP_REG(0x88), 0x000000f0, 0x00000000, - ADDRMAP_REG(0x90), 0x000000f0, 0x00000000, - ADDRMAP_REG(0x98), 0x000000f0, 0x00000000, - ADDRMAP_REG(0xA0), 0x000000f0, 0x00000000, - ADDRMAP_REG(0xA8), 0x000000f0, 0x00000000, - ADDRMAP_REG(0xB0), 0x000000f0, 0x00000000, -// ADDRMAP_REG(0xB8), 0x000000f0, 0x00fc0003, - - /* PCI I/O Limit i Registers - * F1:0xC4 i = 0 - * F1:0xCC i = 1 - * F1:0xD4 i = 2 - * F1:0xDC i = 3 - * [ 2: 0] Destination Node ID - * 000 = Node 0 - * 001 = Node 1 - * 010 = Node 2 - * 011 = Node 3 - * 100 = Node 4 - * 101 = Node 5 - * 110 = Node 6 - * 111 = Node 7 - * [ 3: 3] Reserved - * [ 5: 4] Destination Link ID - * 00 = Link 0 - * 01 = Link 1 - * 10 = Link 2 - * 11 = reserved - * [11: 6] Reserved - * [24:12] PCI I/O Limit Address i - * This field defines the end of PCI I/O region n - * [31:25] Reserved - */ -// ADDRMAP_REG(0xC4), 0xFE000FC8, 0x01fff000, - ADDRMAP_REG(0xCC), 0xFE000FC8, 0x00000000, - ADDRMAP_REG(0xD4), 0xFE000FC8, 0x00000000, - ADDRMAP_REG(0xDC), 0xFE000FC8, 0x00000000, - - /* PCI I/O Base i Registers - * F1:0xC0 i = 0 - * F1:0xC8 i = 1 - * F1:0xD0 i = 2 - * F1:0xD8 i = 3 - * [ 0: 0] Read Enable - * 0 = Reads Disabled - * 1 = Reads Enabled - * [ 1: 1] Write Enable - * 0 = Writes Disabled - * 1 = Writes Enabled - * [ 3: 2] Reserved - * [ 4: 4] VGA Enable - * 0 = VGA matches Disabled - * 1 = matches all address < 64K and where A[9:0] is in the - * range 3B0-3BB or 3C0-3DF independen of the base & limit registers - * [ 5: 5] ISA Enable - * 0 = ISA matches Disabled - * 1 = Blocks address < 64K and in the last 768 bytes of eack 1K block - * from matching agains this base/limit pair - * [11: 6] Reserved - * [24:12] PCI I/O Base i - * This field defines the start of PCI I/O region n - * [31:25] Reserved - */ -// ADDRMAP_REG(0xC0), 0xFE000FCC, 0x00000003, - ADDRMAP_REG(0xC8), 0xFE000FCC, 0x00000000, - ADDRMAP_REG(0xD0), 0xFE000FCC, 0x00000000, - ADDRMAP_REG(0xD8), 0xFE000FCC, 0x00000000, - - /* Config Base and Limit i Registers - * F1:0xE0 i = 0 - * F1:0xE4 i = 1 - * F1:0xE8 i = 2 - * F1:0xEC i = 3 - * [ 0: 0] Read Enable - * 0 = Reads Disabled - * 1 = Reads Enabled - * [ 1: 1] Write Enable - * 0 = Writes Disabled - * 1 = Writes Enabled - * [ 2: 2] Device Number Compare Enable - * 0 = The ranges are based on bus number - * 1 = The ranges are ranges of devices on bus 0 - * [ 3: 3] Reserved - * [ 6: 4] Destination Node - * 000 = Node 0 - * 001 = Node 1 - * 010 = Node 2 - * 011 = Node 3 - * 100 = Node 4 - * 101 = Node 5 - * 110 = Node 6 - * 111 = Node 7 - * [ 7: 7] Reserved - * [ 9: 8] Destination Link - * 00 = Link 0 - * 01 = Link 1 - * 10 = Link 2 - * 11 - Reserved - * [15:10] Reserved - * [23:16] Bus Number Base i - * This field defines the lowest bus number in configuration region i - * [31:24] Bus Number Limit i - * This field defines the highest bus number in configuration regin i - */ -// ADDRMAP_REG(0xE0), 0x0000FC88, 0x06000003, // AMD 8111 on link0 of CPU 0 - ADDRMAP_REG(0xE4), 0x0000FC88, 0x00000000, - ADDRMAP_REG(0xE8), 0x0000FC88, 0x00000000, - ADDRMAP_REG(0xEC), 0x0000FC88, 0x00000000, - }; - - int max; - max = ARRAY_SIZE(register_values); - setup_resource_map(register_values, max); -} diff --git a/src/mainboard/gigabyte/ma78gm/romstage.c b/src/mainboard/gigabyte/ma78gm/romstage.c deleted file mode 100644 index 48af367817..0000000000 --- a/src/mainboard/gigabyte/ma78gm/romstage.c +++ /dev/null @@ -1,227 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2010 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -//#define SYSTEM_TYPE 0 /* SERVER */ -#define SYSTEM_TYPE 1 /* DESKTOP */ -//#define SYSTEM_TYPE 2 /* MOBILE */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include "cpu/amd/quadcore/quadcore.c" - -#define SERIAL_DEV PNP_DEV(0x2e, IT8718F_SP1) -#define GPIO_DEV PNP_DEV(0x2e, IT8718F_GPIO) - -int spd_read_byte(unsigned int device, unsigned int address); - - -int spd_read_byte(u32 device, u32 address) -{ - return do_smbus_read_byte(SMBUS_IO_BASE, device, address); -} - -void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) -{ - struct sys_info *sysinfo = get_sysinfo(); - static const u8 spd_addr[] = {RC00, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, }; - u32 bsp_apicid = 0, val; - msr_t msr; - - timestamp_init(timestamp_get()); - timestamp_add_now(TS_START_ROMSTAGE); - - if (!cpu_init_detectedx && boot_cpu()) { - /* Nothing special needs to be done to find bus 0 */ - /* Allow the HT devices to be found */ - /* mov bsp to bus 0xff when > 8 nodes */ - set_bsp_node_CHtExtNodeCfgEn(); - enumerate_ht_chain(); - sb7xx_51xx_pci_port80(); - } - - post_code(0x30); - - if (bist == 0) { - bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo); /* mmconf is inited in init_cpus */ - /* All cores run this but the BSP(node0,core0) is the only core that returns. */ - } - - post_code(0x32); - - enable_rs780_dev8(); - sb7xx_51xx_lpc_init(); - - ite_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); - it8718f_disable_reboot(GPIO_DEV); - - console_init(); - - /* Halt if there was a built in self test failure */ - report_bist_failure(bist); - - // Load MPB - val = cpuid_eax(1); - printk(BIOS_DEBUG, "BSP Family_Model: %08x\n", val); - printk(BIOS_DEBUG, "*sysinfo range: [%p,%p]\n",sysinfo,sysinfo+1); - printk(BIOS_DEBUG, "bsp_apicid = %02x\n", bsp_apicid); - printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx); - - /* Setup sysinfo defaults */ - set_sysinfo_in_ram(0); - - update_microcode(val); - - post_code(0x33); - - cpuSetAMDMSR(0); - post_code(0x34); - - amd_ht_init(sysinfo); - post_code(0x35); - - /* Setup nodes PCI space and start core 0 AP init. */ - finalize_node_setup(sysinfo); - - /* Setup any mainboard PCI settings etc. */ - setup_mb_resource_map(); - post_code(0x36); - - /* wait for all the APs core0 started by finalize_node_setup. */ - /* FIXME: A bunch of cores are going to start output to serial at once. - It would be nice to fixup prink spinlocks for ROM XIP mode. - I think it could be done by putting the spinlock flag in the cache - of the BSP located right after sysinfo. - */ - wait_all_core0_started(); - -#if CONFIG(LOGICAL_CPUS) - /* Core0 on each node is configured. Now setup any additional cores. */ - printk(BIOS_DEBUG, "start_other_cores()\n"); - start_other_cores(bsp_apicid); - post_code(0x37); - wait_all_other_cores_started(bsp_apicid); -#endif - - post_code(0x38); - - /* run _early_setup before soft-reset. */ - rs780_early_setup(); - sb7xx_51xx_early_setup(); - -#if CONFIG(SET_FIDVID) - msr = rdmsr(MSR_COFVID_STS); - printk(BIOS_DEBUG, "\nBegin FIDVID MSR 0xc0010071 0x%08x 0x%08x\n", msr.hi, msr.lo); - - /* FIXME: The sb fid change may survive the warm reset and only - need to be done once.*/ - enable_fid_change_on_sb(sysinfo->sbbusn, sysinfo->sbdn); - - post_code(0x39); - - if (!warm_reset_detect(0)) { // BSP is node 0 - init_fidvid_bsp(bsp_apicid, sysinfo->nodes); - } else { - init_fidvid_stage2(bsp_apicid, 0); // BSP is node 0 - } - - post_code(0x3A); - - /* show final fid and vid */ - msr = rdmsr(MSR_COFVID_STS); - printk(BIOS_DEBUG, "End FIDVIDMSR 0xc0010071 0x%08x 0x%08x\n", msr.hi, msr.lo); -#endif - - rs780_htinit(); - - /* Reset for HT, FIDVID, PLL and errata changes to take affect. */ - if (!warm_reset_detect(0)) { - printk(BIOS_INFO, "...WARM RESET...\n\n\n"); - soft_reset(); - die("After soft_reset - shouldn't see this message!!!\n"); - } - - post_code(0x3B); - - /* It's the time to set ctrl in sysinfo now; */ - printk(BIOS_DEBUG, "fill_mem_ctrl()\n"); - fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr); - - post_code(0x40); - - raminit_amdmct(sysinfo); - - cbmem_initialize_empty(); - post_code(0x41); - - amdmct_cbmem_store_info(sysinfo); - - sb7xx_51xx_before_pci_init(); - - post_code(0x42); -} - -/** - * BOOL AMD_CB_ManualBUIDSwapList(u8 Node, u8 Link, u8 **List) - * Description: - * This routine is called every time a non-coherent chain is processed. - * BUID assignment may be controlled explicitly on a non-coherent chain. Provide a - * swap list. The first part of the list controls the BUID assignment and the - * second part of the list provides the device to device linking. Device orientation - * can be detected automatically, or explicitly. See documentation for more details. - * - * Automatic non-coherent init assigns BUIDs starting at 1 and incrementing sequentially - * based on each device's unit count. - * - * Parameters: - * @param[in] node = The node on which this chain is located - * @param[in] link = The link on the host for this chain - * @param[out] List = supply a pointer to a list - */ -BOOL AMD_CB_ManualBUIDSwapList (u8 node, u8 link, const u8 **List) -{ - static const u8 swaplist[] = { 0xFF, CONFIG_HT_CHAIN_UNITID_BASE, CONFIG_HT_CHAIN_END_UNITID_BASE, 0xFF }; - /* If the BUID was adjusted in early_ht we need to do the manual override */ - if ((CONFIG_HT_CHAIN_UNITID_BASE != 0) && (CONFIG_HT_CHAIN_END_UNITID_BASE != 0)) { - printk(BIOS_DEBUG, "AMD_CB_ManualBUIDSwapList()\n"); - if ((node == 0) && (link == 0)) { /* BSP SB link */ - *List = swaplist; - return 1; - } - } - - return 0; -} diff --git a/src/mainboard/hp/dl165_g6_fam10/Kconfig b/src/mainboard/hp/dl165_g6_fam10/Kconfig deleted file mode 100644 index 65d7edfd90..0000000000 --- a/src/mainboard/hp/dl165_g6_fam10/Kconfig +++ /dev/null @@ -1,65 +0,0 @@ -if BOARD_HP_DL165_G6_FAM10 - -config BOARD_SPECIFIC_OPTIONS - def_bool y - select CPU_AMD_SOCKET_F_1207 - select NORTHBRIDGE_AMD_AMDFAM10 - select SOUTHBRIDGE_BROADCOM_BCM21000 - select SOUTHBRIDGE_BROADCOM_BCM5785 - select HT_CHAIN_DISTRIBUTE - select SUPERIO_SERVERENGINES_PILOT - select SUPERIO_NSC_PC87417 - select DIMM_DDR2 - select DIMM_REGISTERED - select HAVE_OPTION_TABLE - select HAVE_PIRQ_TABLE - select HAVE_MP_TABLE - select LIFT_BSP_APIC_ID - select BOARD_ROMSIZE_KB_1024 - select ENABLE_APIC_EXT_ID - -config MAINBOARD_DIR - string - default hp/dl165_g6_fam10 - -config DCACHE_RAM_BASE - hex - default 0xc4000 - -config DCACHE_RAM_SIZE - hex - default 0x0c000 - -config APIC_ID_OFFSET - hex - default 0x0 - -config MAINBOARD_PART_NUMBER - string - default "ProLiant DL165 G6 (Fam10)" - -config MAX_CPUS - int - default 12 - -config MAX_PHYSICAL_CPUS - int - default 2 - -config HT_CHAIN_END_UNITID_BASE - hex - default 0x1 - -config HT_CHAIN_UNITID_BASE - hex - default 0x6 - -config IRQ_SLOT_COUNT - int - default 15 - -config BOOTBLOCK_MAINBOARD_INIT - string - default "mainboard/hp/dl165_g6_fam10/bootblock.c" - -endif # BOARD_HP_DL165_G6_FAM10 diff --git a/src/mainboard/hp/dl165_g6_fam10/Kconfig.name b/src/mainboard/hp/dl165_g6_fam10/Kconfig.name deleted file mode 100644 index ceb6e86b14..0000000000 --- a/src/mainboard/hp/dl165_g6_fam10/Kconfig.name +++ /dev/null @@ -1,2 +0,0 @@ -config BOARD_HP_DL165_G6_FAM10 - bool "ProLiant DL165 G6 Fam10" diff --git a/src/mainboard/hp/dl165_g6_fam10/Makefile.inc b/src/mainboard/hp/dl165_g6_fam10/Makefile.inc deleted file mode 100644 index 0fd5b079f5..0000000000 --- a/src/mainboard/hp/dl165_g6_fam10/Makefile.inc +++ /dev/null @@ -1,14 +0,0 @@ -# -# This file is part of the coreboot project. -# -# This program is free software; you can redistribute it and/or modify -# it under the terms of the GNU General Public License as published by -# the Free Software Foundation; version 2 of the License. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# - -ramstage-y += get_bus_conf.c diff --git a/src/mainboard/hp/dl165_g6_fam10/board_info.txt b/src/mainboard/hp/dl165_g6_fam10/board_info.txt deleted file mode 100644 index 30851bc699..0000000000 --- a/src/mainboard/hp/dl165_g6_fam10/board_info.txt +++ /dev/null @@ -1,3 +0,0 @@ -Category: server -Board URL: http://h20000.www2.hp.com/bizsupport/TechSupport/Document.jsp?lang=en&cc=us&objectID=c01765799 -Release year: 2009 diff --git a/src/mainboard/hp/dl165_g6_fam10/bootblock.c b/src/mainboard/hp/dl165_g6_fam10/bootblock.c deleted file mode 100644 index b70b0a3e24..0000000000 --- a/src/mainboard/hp/dl165_g6_fam10/bootblock.c +++ /dev/null @@ -1,69 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include - -#define SCH4307_CONFIG_PORT 0x162e -static inline void shc4307_enter_ext_func_mode(pnp_devfn_t dev) -{ - unsigned int port = dev >> 8; - outb(0x55, port); -} - -static inline void shc4307_exit_ext_func_mode(pnp_devfn_t dev) -{ - unsigned int port = dev >> 8; - outb(0xaa, port); -} - -#define CMOS_DEV PNP_DEV(SCH4307_CONFIG_PORT, 0x6) -#define KBD_DEV PNP_DEV(SCH4307_CONFIG_PORT, 0x7) -#define DBG_DEV PNP_DEV(SCH4307_CONFIG_PORT, 0x3) -#define REGS_DEV PNP_DEV(SCH4307_CONFIG_PORT, 0xa) - -/* FIXME: This appears to be a super-io initialisation, - * placed in the mainboard directory. - */ -void shc4307_init(void) -{ - shc4307_enter_ext_func_mode(CMOS_DEV); - pnp_set_logical_device(CMOS_DEV); /* CMOS/RTC */ - pnp_set_iobase(CMOS_DEV, PNP_IDX_IO0, 0x70); - pnp_set_iobase(CMOS_DEV, PNP_IDX_IO1, 0x72); - pnp_set_irq(CMOS_DEV, PNP_IDX_IRQ0, 8); - /* pnp_set_enable(CMOS_DEV, 3); */ - pnp_write_config(CMOS_DEV, 0x30, 3); - - pnp_set_logical_device(KBD_DEV); /* Keyboard */ - pnp_set_irq(KBD_DEV, PNP_IDX_IRQ0, 1); - pnp_set_enable(KBD_DEV, 1); - - pnp_set_logical_device(DBG_DEV); /* Debug */ - pnp_set_iobase(DBG_DEV, PNP_IDX_IO0, 0x80); - pnp_set_enable(DBG_DEV, 1); - - pnp_set_logical_device(REGS_DEV); - pnp_set_iobase(REGS_DEV, PNP_IDX_IO0, 0x600); - pnp_set_enable(REGS_DEV, 1); - - shc4307_exit_ext_func_mode(CMOS_DEV); -} - -static void bootblock_mainboard_init(void) -{ - bootblock_northbridge_init(); - bootblock_southbridge_init(); - shc4307_init(); -} diff --git a/src/mainboard/hp/dl165_g6_fam10/cmos.layout b/src/mainboard/hp/dl165_g6_fam10/cmos.layout deleted file mode 100644 index 40d93aa5d6..0000000000 --- a/src/mainboard/hp/dl165_g6_fam10/cmos.layout +++ /dev/null @@ -1,101 +0,0 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2015 Timothy Pearson , Raptor Engineering -## Copyright (C) 2007 AMD -## Written by Yinghai Lu for AMD. -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; either version 2 of the License, or -## (at your option) any later version. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## - -entries - -0 384 r 0 reserved_memory -384 1 e 4 boot_option -388 4 h 0 reboot_counter -393 3 r 0 unused -#394 7 unused -401 1 e 1 interleave_chip_selects -402 1 e 1 interleave_nodes -403 1 e 1 interleave_memory_channels -404 2 e 8 max_mem_clock -406 1 e 2 multi_core -412 4 e 6 debug_level -416 5 e 10 ecc_scrub_rate -440 4 e 9 slow_cpu -444 1 e 1 nmi -445 1 e 1 gart -456 1 e 1 ECC_memory -457 1 e 1 ECC_redirection -728 256 h 0 user_data -984 16 h 0 check_sum -# Reserve the extended AMD configuration registers -1000 24 r 0 amd_reserved - - - -enumerations - -#ID value text -1 0 Disable -1 1 Enable -2 0 Enable -2 1 Disable -4 0 Fallback -4 1 Normal -6 0 Emergency -6 1 Alert -6 2 Critical -6 3 Error -6 4 Warning -6 5 Notice -6 6 Information -6 7 Debug -6 8 Spew -8 0 DDR2-800 -8 1 DDR2-667 -8 2 DDR2-533 -8 3 DDR2-400 -9 0 off -9 1 87.5% -9 2 75.0% -9 3 62.5% -9 4 50.0% -9 5 37.5% -9 6 25.0% -9 7 12.5% -10 0 Disabled -10 1 40ns -10 2 80ns -10 3 160ns -10 4 320ns -10 5 640ns -10 6 1.28us -10 7 2.56us -10 8 5.12us -10 9 10.2us -10 10 20.5us -10 11 41us -10 12 81.9us -10 13 163.8us -10 14 327.7us -10 15 655.4us -10 16 1.31ms -10 17 2.62ms -10 18 5.24ms -10 19 10.49ms -10 20 20.97sms -10 21 42ms -10 22 84ms - -checksums - -checksum 392 983 984 diff --git a/src/mainboard/hp/dl165_g6_fam10/devicetree.cb b/src/mainboard/hp/dl165_g6_fam10/devicetree.cb deleted file mode 100644 index 4e08efd401..0000000000 --- a/src/mainboard/hp/dl165_g6_fam10/devicetree.cb +++ /dev/null @@ -1,88 +0,0 @@ -chip northbridge/amd/amdfam10/root_complex - device cpu_cluster 0 on - chip cpu/amd/socket_F_1207 - device lapic 0 on end - end - end - device domain 0 on - chip northbridge/amd/amdfam10 # northbridge - device pci 18.0 on end - device pci 18.0 on end - device pci 18.0 on # devices on link 2 - chip southbridge/broadcom/bcm21000 # HT2100 - device pci 0.0 on - end # bridge to slot PCI-E 4x ?? - device pci 1.0 on - end - device pci 2.0 on - end # unused - device pci 3.0 on # bridge to slot PCI-E 16x ?? - end - device pci 4.0 on - end # unused - device pci 5.0 on - device pci 4.0 on end # BCM5715 NIC - device pci 4.1 on end # BCM5715 NIC - end - end - chip southbridge/broadcom/bcm5785 # HT1000 - device pci 0.0 on # HT PXB 0x0036 - device pci d.0 on end # PCI/PCI-X bridge 0x0104 - device pci e.0 on end # SATA 0x024a - end - device pci 1.0 on end # Legacy pci main 0x0205 - device pci 1.1 on end # IDE 0x0214 - device pci 1.2 on # LPC 0x0234 - chip superio/nsc/pc87417 - device pnp 4e.0 off # Floppy - io 0x60 = 0x3f0 - irq 0x70 = 6 - drq 0x74 = 2 - end - device pnp 4e.1 off # Parallel Port - io 0x60 = 0x378 - irq 0x70 = 7 - end - device pnp 4e.2 off # Com 2 - io 0x60 = 0x2f8 - irq 0x70 = 3 - end - device pnp 4e.3 off # Com 1 - io 0x60 = 0x3f8 - irq 0x70 = 4 - end - device pnp 4e.4 off end # SWC - device pnp 4e.5 off end # Mouse - device pnp 4e.6 off # Keyboard - io 0x60 = 0x60 - io 0x62 = 0x64 - irq 0x70 = 1 - end - device pnp 4e.7 off end # GPIO - device pnp 4e.f off end # XBUS - device pnp 4e.10 on #RTC - io 0x60 = 0x70 - io 0x62 = 0x72 - end - end # end superio - end # end pci 1.2 - device pci 1.3 off end # WDTimer 0x0238 - device pci 1.4 on end # XIOAPIC0 0x0235 - device pci 1.5 on end # XIOAPIC1 - device pci 1.6 on end # XIOAPIC2 - device pci 2.0 on end # USB 0x0223 - device pci 2.1 on end # USB - device pci 2.2 on end # USB - device pci 3.0 on end # VGA - end - end - device pci 18.0 on end - device pci 18.0 on end - device pci 18.1 on end - device pci 18.2 on end - device pci 18.3 on end - device pci 18.4 on end - end # amdfam10 - - end #domain -end diff --git a/src/mainboard/hp/dl165_g6_fam10/get_bus_conf.c b/src/mainboard/hp/dl165_g6_fam10/get_bus_conf.c deleted file mode 100644 index 0d8ee8c28b..0000000000 --- a/src/mainboard/hp/dl165_g6_fam10/get_bus_conf.c +++ /dev/null @@ -1,85 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007 AMD - * Written by Yinghai Lu for AMD. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include -#include -#include -#include - -#include - -#include -#include "mb_sysconf.h" - -// Global variables for MB layouts and these will be shared by irqtable mptable and acpi_tables -struct mb_sysconf_t mb_sysconf; - -void get_bus_conf(void) -{ - - unsigned int apicid_base; - - struct device *dev; - int i; - struct mb_sysconf_t *m; - - - sysconf.mb = &mb_sysconf; - - m = sysconf.mb; - memset(m, 0, sizeof(struct mb_sysconf_t)); - - get_default_pci1234(32); - - sysconf.sbdn = (sysconf.hcdn[0] >> 8) & 0xff; - m->sbdn2 = sysconf.hcdn[0] & 0xff; // bcm5780 - - m->bus_bcm5785_0 = (sysconf.pci1234[0] >> 12) & 0xff; - m->bus_bcm5780[0] = m->bus_bcm5785_0; - - /* bcm5785 */ - printk(BIOS_DEBUG, "search for def %d.0 on bus %d\n",sysconf.sbdn,m->bus_bcm5785_0); - dev = dev_find_slot(m->bus_bcm5785_0, PCI_DEVFN(sysconf.sbdn,0)); - if (dev) { - printk(BIOS_DEBUG, "found dev %s...\n",dev_path(dev)); - m->bus_bcm5785_1 = pci_read_config8(dev, PCI_SECONDARY_BUS); - printk(BIOS_DEBUG, "secondary is %d...\n",m->bus_bcm5785_1); - dev = dev_find_slot(m->bus_bcm5785_1, PCI_DEVFN(0xd,0)); - printk(BIOS_DEBUG, "now found %s...\n",dev_path(dev)); - if (dev) - m->bus_bcm5785_1_1 = pci_read_config8(dev, PCI_SECONDARY_BUS); - } - else { - printk(BIOS_DEBUG, "ERROR - could not find PCI %02x:%02x.0, using defaults\n", m->bus_bcm5785_0, sysconf.sbdn); - } - - /* bcm5780 */ - for (i = 1; i < 6; i++) { - dev = dev_find_slot(m->bus_bcm5780[0], PCI_DEVFN(m->sbdn2 + i - 1,0)); - if (dev) - m->bus_bcm5780[i] = pci_read_config8(dev, PCI_SECONDARY_BUS); - else - printk(BIOS_DEBUG, "ERROR - could not find PCI %02x:%02x.0, using defaults\n", m->bus_bcm5780[0], m->sbdn2+i-1); - } - -/*I/O APICs: APIC ID Version State Address*/ - apicid_base = 0x10; - for (i = 0; i < 3; i++) - m->apicid_bcm5785[i] = apicid_base+i; -} diff --git a/src/mainboard/hp/dl165_g6_fam10/irq_tables.c b/src/mainboard/hp/dl165_g6_fam10/irq_tables.c deleted file mode 100644 index ef52ef8b50..0000000000 --- a/src/mainboard/hp/dl165_g6_fam10/irq_tables.c +++ /dev/null @@ -1,55 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifdef GETPIR -#include "pirq_routing.h" -#else -#include -#endif - -static const struct irq_routing_table intel_irq_routing_table = { - PIRQ_SIGNATURE, /* u32 signature */ - PIRQ_VERSION, /* u16 version */ - 32 + 16 * 11, /* Max. number of devices on the bus */ - 0x00, /* Interrupt router bus */ - (0x02 << 3) | 0x0, /* Interrupt router dev */ - 0, /* IRQs devoted exclusively to PCI usage */ - 0x1166, /* Vendor */ - 0x36, /* Device */ - 0, /* Miniport */ - { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */ - 0xe9, /* Checksum (has to be set to some value that - * would give 0 after the sum of all bytes - * for this structure (including checksum). - */ - { - /* bus, dev | fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */ - {0x01, (0x0e << 3) | 0x0, {{0x07, 0x0020}, {0x07, 0x0020}, {0x07, 0x0020}, {0x07, 0x0020}}, 0x0, 0x0}, /* 1166:024a */ - {0x00, (0x03 << 3) | 0x0, {{0x01, 0x0400}, {0x01, 0x0400}, {0x01, 0x0400}, {0x01, 0x0400}}, 0x0, 0x0}, /* 1166:0223 */ - {0x00, (0x06 << 3) | 0x0, {{0x24, 0xdac0}, {0x24, 0xdac0}, {0x24, 0xdac0}, {0x24, 0xdac0}}, 0x0, 0x0}, /* 1166:0140 */ - {0x00, (0x07 << 3) | 0x0, {{0x23, 0xdac0}, {0x23, 0xdac0}, {0x23, 0xdac0}, {0x23, 0xdac0}}, 0x0, 0x0}, /* 1166:0142 */ - {0x00, (0x08 << 3) | 0x0, {{0x22, 0xdac0}, {0x22, 0xdac0}, {0x22, 0xdac0}, {0x22, 0xdac0}}, 0x0, 0x0}, /* 1166:0144 */ - {0x00, (0x09 << 3) | 0x0, {{0x21, 0xdac0}, {0x21, 0xdac0}, {0x21, 0xdac0}, {0x21, 0xdac0}}, 0x0, 0x0}, /* 1166:0142 */ - {0x00, (0x0a << 3) | 0x0, {{0x20, 0xdac0}, {0x20, 0xdac0}, {0x20, 0xdac0}, {0x20, 0xdac0}}, 0x0, 0x0}, /* 1166:0144 */ - {0x02, (0x02 << 3) | 0x0, {{0x28, 0xdac0}, {0x27, 0xdac0}, {0x00, 0x0000}, {0x00, 0x0000}}, 0x0, 0x0}, /* 14e4:1648 */ - {0x06, (0x00 << 3) | 0x0, {{0x21, 0xdac0}, {0x21, 0xdac0}, {0x21, 0xdac0}, {0x21, 0xdac0}}, 0x2, 0x0}, - {0x03, (0x00 << 3) | 0x0, {{0x24, 0xdac0}, {0x24, 0xdac0}, {0x24, 0xdac0}, {0x24, 0xdac0}}, 0x2, 0x0}, - {0x07, (0x00 << 3) | 0x0, {{0x2a, 0xdac0}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x0000}}, 0x0, 0x0}, /* 102b:0522 */ - } -}; - - -unsigned long write_pirq_routing_table(unsigned long addr) -{ - return copy_pirq_routing_table(addr, &intel_irq_routing_table); -} diff --git a/src/mainboard/hp/dl165_g6_fam10/mb_sysconf.h b/src/mainboard/hp/dl165_g6_fam10/mb_sysconf.h deleted file mode 100644 index b2a11e33f2..0000000000 --- a/src/mainboard/hp/dl165_g6_fam10/mb_sysconf.h +++ /dev/null @@ -1,37 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2006 AMD - * Written by Yinghai Lu for AMD. - * - * Copyright (C) 2007 University of Mannheim - * Written by Philipp Degler for Uni of Mannheim - * - * Copyright (C) 2009 University of Heidelberg - * Written by Mondrian Nuessle for Uni of Heidelberg - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef MB_SYSCONF_H -#define MB_SYSCONF_H - -struct mb_sysconf_t { - unsigned char bus_bcm5780[7]; - unsigned char bus_bcm5785_0; - unsigned char bus_bcm5785_1; - unsigned char bus_bcm5785_1_1; - unsigned int apicid_bcm5785[3]; - - unsigned int sbdn2; -}; - -#endif diff --git a/src/mainboard/hp/dl165_g6_fam10/mptable.c b/src/mainboard/hp/dl165_g6_fam10/mptable.c deleted file mode 100644 index 6bf83cf928..0000000000 --- a/src/mainboard/hp/dl165_g6_fam10/mptable.c +++ /dev/null @@ -1,164 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2001 Eric W.Biederman < ebiderman@lnxi.com> - * - * Copyright (C) 2006 AMD - * Written by Yinghai Lu for AMD. - * - * Copyright (C) 2007 University of Mannheim - * Written by Philipp Degler for Uni of Mannheim - * - * Copyright (C) 2009 University of Heidelberg - * Written by Mondrian Nuessle for Uni of Heidelberg - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include -#include -#include -#include -#if CONFIG(LOGICAL_CPUS) -#include -#endif -#include -#include "mb_sysconf.h" - -static void *smp_write_config_table(void *v) -{ - struct mp_config_table *mc; - int isa_bus; - - struct mb_sysconf_t *m; - - mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); - - mptable_init(mc, LOCAL_APIC_ADDR); - - smp_write_processors(mc); - - m = sysconf.mb; - - mptable_write_buses(mc, NULL, &isa_bus); - - /*I/O APICs: APIC ID Version State Address*/ - { - struct device *dev = NULL; - int i; - struct resource *res; - for (i = 0; i < 3; i++) { - dev = dev_find_device(0x1166, 0x0235, dev); - if (dev) { - res = find_resource(dev, PCI_BASE_ADDRESS_0); - if (res) { - printk(BIOS_DEBUG, "APIC %d base address: %x\n",m->apicid_bcm5785[i], (int)res->base); - smp_write_ioapic(mc, m->apicid_bcm5785[i], 0x11, - res2mmio(res, 0, 0)); - } - } - } - - } - - /* IRQ routing as factory BIOS */ - outb(0x00, 0xc00); outb(0x09, 0xc01); - outb(0x01, 0xc00); outb(0x0a, 0xc01); - outb(0x02, 0xc00); outb(0x0e, 0xc01); - outb(0x03, 0xc00); outb(0x07, 0xc01); - outb(0x07, 0xc00); outb(0x05, 0xc01); - - // 8259 registers... - outb(0xa0, 0x4d0); - outb(0x0e, 0x4d1); - - { - struct device *dev; - dev = dev_find_device(0x1166, 0x0205, 0); - if (dev) { - uint32_t dword; - dword = pci_read_config32(dev, 0x64); - dword |= (1 << 30); // GEVENT14-21 used as PCI IRQ0-7 - pci_write_config32(dev, 0x64, dword); - } - // set GEVENT pins to NO OP - /* outb(0x33, 0xcd6); outb(0x00, 0xcd7); - outb(0x34, 0xcd6); outb(0x00, 0xcd7); - outb(0x35, 0xcd6); outb(0x00, 0xcd7); */ - } - - // hide XIOAPIC PCI configuration space - { - struct device *dev; - dev = dev_find_device(0x1166, 0x205, 0); - if (dev) { - uint32_t dword; - dword = pci_read_config32(dev, 0x64); - dword |= (1 << 26); - pci_write_config32(dev, 0x64, dword); - } - } - - mptable_add_isa_interrupts(mc, isa_bus, m->apicid_bcm5785[0], 0); - - /* I/O Ints: Type Polarity/Trigger Bus ID IRQ APIC ID PIN# */ - smp_write_pci_intsrc(mc, mp_INT, m->bus_bcm5785_1, 0xe, 0, m->apicid_bcm5785[0], 0x5); - smp_write_pci_intsrc(mc, mp_INT, m->bus_bcm5785_0, 0x3, 0, m->apicid_bcm5785[0], 0xa); - smp_write_pci_intsrc(mc, mp_INT, m->bus_bcm5785_0, 0x6, 0, m->apicid_bcm5785[2], 0x4); - smp_write_pci_intsrc(mc, mp_INT, m->bus_bcm5785_0, 0x7, 0, m->apicid_bcm5785[2], 0x3); - smp_write_pci_intsrc(mc, mp_INT, m->bus_bcm5785_0, 0x8, 0, m->apicid_bcm5785[2], 0x2); - smp_write_pci_intsrc(mc, mp_INT, m->bus_bcm5785_0, 0x9, 0, m->apicid_bcm5785[2], 0x1); - smp_write_pci_intsrc(mc, mp_INT, m->bus_bcm5785_0, 0xa, 0, m->apicid_bcm5785[2], 0x0); - smp_write_pci_intsrc(mc, mp_INT, m->bus_bcm5785_1_1, 0x2, 0, m->apicid_bcm5785[2], 0x8); - smp_write_pci_intsrc(mc, mp_INT, m->bus_bcm5785_1_1, 0x2, 1, m->apicid_bcm5785[2], 0x7); - smp_write_pci_intsrc(mc, mp_INT, m->bus_bcm5780[5], 0x0, 0, m->apicid_bcm5785[2], 0xa); - - /* enable int */ - /* why here? must get the BAR and PCI command bit 1 set before enable it ....*/ - { - struct device *dev; - dev = dev_find_device(0x1166, 0x0205, 0); - if (dev) { - uint32_t dword; - dword = pci_read_config32(dev, 0x6c); - dword |= (1 << 4); // enable interrupts - printk(BIOS_DEBUG, "6ch: %x\n",dword); - pci_write_config32(dev, 0x6c, dword); - } - } - - /* Local Ints: Type Polarity/Trigger Bus ID IRQ APIC ID PIN# */ - mptable_lintsrc(mc, isa_bus); - - //extended table entries - smp_write_address_space(mc,0 , ADDRESS_TYPE_IO, 0x0, 0x0, 0x0, 0x0001); - smp_write_address_space(mc,0 , ADDRESS_TYPE_MEM, 0x0, 0x7f80, 0x0, 0x5e80); - smp_write_address_space(mc,0 , ADDRESS_TYPE_PREFETCH, 0x0, 0xde00, 0x0, 0x0100); - smp_write_address_space(mc,0 , ADDRESS_TYPE_MEM, 0x0, 0xdf00, 0x0, 0x1fe0); - smp_write_address_space(mc,0 , ADDRESS_TYPE_MEM, 0x1000, 0xfee0, 0xf000, 0x011f); - smp_write_address_space(mc,0 , ADDRESS_TYPE_MEM, 0x0, 0x000a, 0x0, 0x0006); - smp_write_bus_hierarchy(mc, 8, 0x01, 0); - smp_write_compatibility_address_space(mc, 0, ADDRESS_RANGE_ADD, 0); - smp_write_compatibility_address_space(mc, 0, ADDRESS_RANGE_ADD, 1); - - - /* Compute the checksums */ - return mptable_finalize(mc); -} - -unsigned long write_smp_table(unsigned long addr) -{ - void *v; - v = smp_write_floating_table(addr, 0); - return (unsigned long)smp_write_config_table(v); -} diff --git a/src/mainboard/hp/dl165_g6_fam10/romstage.c b/src/mainboard/hp/dl165_g6_fam10/romstage.c deleted file mode 100644 index 1b91e97ec7..0000000000 --- a/src/mainboard/hp/dl165_g6_fam10/romstage.c +++ /dev/null @@ -1,240 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2006 Tyan - * Copyright (C) 2006 AMD - * Written by Yinghai Lu for Tyan and AMD. - * - * Copyright (C) 2007 University of Mannheim - * Written by Philipp Degler for University of Mannheim - * Copyright (C) 2009 University of Heidelberg - * Written by Mondrian Nuessle for University of Heidelberg - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include -#include -#include -#include "option_table.h" -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include "southbridge/broadcom/bcm5785/early_smbus.c" -#include "southbridge/broadcom/bcm5785/early_setup.c" - -#include "cpu/amd/quadcore/quadcore.c" - -#define SERIAL_DEV PNP_DEV(0x2e, PILOT_SP1) -#define RTC_DEV PNP_DEV(0x4e, PC87417_RTC) - -int spd_read_byte(unsigned int device, unsigned int address); - -void activate_spd_rom(const struct mem_controller *ctrl) -{ - u8 val; - outb(0x3d, 0x0cd6); - outb(0x87, 0x0cd7); - - outb(0x44, 0xcd6); - val = inb(0xcd7); - outb((val & ~3) | ctrl->spd_switch_addr, 0xcd7); -} - -inline int spd_read_byte(unsigned int device, unsigned int address) -{ - return smbus_read_byte(device, address); -} - -static const u8 spd_addr[] = { - // switch addr, 1A addr, 2A addr, 3A addr, 4A addr, 1B addr, 2B addr, 3B addr 4B addr - //first node - RC00, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, -#if CONFIG_MAX_PHYSICAL_CPUS > 1 - //second node - RC01, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, -#endif -}; - -void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) -{ - struct sys_info *sysinfo = get_sysinfo(); - u32 bsp_apicid = 0, val; - msr_t msr; - - timestamp_init(timestamp_get()); - timestamp_add_now(TS_START_ROMSTAGE); - - if (!cpu_init_detectedx && boot_cpu()) { - /* Nothing special needs to be done to find bus 0 */ - /* Allow the HT devices to be found */ - /* mov bsp to bus 0xff when > 8 nodes */ - set_bsp_node_CHtExtNodeCfgEn(); - enumerate_ht_chain(); - bcm5785_enable_lpc(); - pc87417_enable_dev(RTC_DEV); /* Enable RTC */ - } - - post_code(0x30); - - if (bist == 0) - bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo); - - pilot_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); - - console_init(); - - /* Halt if there was a built in self test failure */ - report_bist_failure(bist); - - pilot_early_init(SERIAL_DEV); //config port is being taken from SERIAL_DEV - - val = cpuid_eax(1); - printk(BIOS_DEBUG, "BSP Family_Model: %08x\n", val); - printk(BIOS_DEBUG, "*sysinfo range: [%p,%p]\n",sysinfo,sysinfo+1); - printk(BIOS_DEBUG, "bsp_apicid = %02x\n", bsp_apicid); - printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx); - - /* Setup sysinfo defaults */ - set_sysinfo_in_ram(0); - - update_microcode(val); - - post_code(0x33); - - cpuSetAMDMSR(0); - post_code(0x34); - - amd_ht_init(sysinfo); - post_code(0x35); - - /* Setup nodes PCI space and start core 0 AP init. */ - finalize_node_setup(sysinfo); - - post_code(0x36); - - /* wait for all the APs core0 started by finalize_node_setup. */ - /* FIXME: A bunch of cores are going to start output to serial at once. - * It would be nice to fixup prink spinlocks for ROM XIP mode. - * I think it could be done by putting the spinlock flag in the cache - * of the BSP located right after sysinfo. - */ - - wait_all_core0_started(); - -#if CONFIG(LOGICAL_CPUS) - /* Core0 on each node is configured. Now setup any additional cores. */ - printk(BIOS_DEBUG, "start_other_cores()\n"); - start_other_cores(bsp_apicid); - post_code(0x37); - wait_all_other_cores_started(bsp_apicid); -#endif - -#if CONFIG(SET_FIDVID) - msr = rdmsr(MSR_COFVID_STS); - printk(BIOS_DEBUG, "\nBegin FIDVID MSR 0xc0010071 0x%08x 0x%08x\n", msr.hi, msr.lo); - - /* FIXME: The sb fid change may survive the warm reset and only - * need to be done once.*/ - - enable_fid_change_on_sb(sysinfo->sbbusn, sysinfo->sbdn); - - post_code(0x39); - - if (!warm_reset_detect(0)) { // BSP is node 0 - init_fidvid_bsp(bsp_apicid, sysinfo->nodes); - } else { - init_fidvid_stage2(bsp_apicid, 0); // BSP is node 0 - } - - post_code(0x3A); - - /* show final fid and vid */ - msr = rdmsr(MSR_COFVID_STS); - printk(BIOS_DEBUG, "End FIDVIDMSR 0xc0010071 0x%08x 0x%08x\n", msr.hi, msr.lo); -#endif - - init_timer(); - - /* Reset for HT, FIDVID, PLL and errata changes to take affect. */ - if (!warm_reset_detect(0)) { - printk(BIOS_INFO, "...WARM RESET...\n\n\n"); - soft_reset(); - die("After soft_reset - shouldn't see this message!!!\n"); - } - - /* It's the time to set ctrl in sysinfo now; */ - fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr); - enable_smbus(); - - //do we need ACPI timer, tsc...., only debug need it for better output - /* all ap stopped? */ -// init_timer(); // Need to use TMICT to synchronize FID/VID - - timestamp_add_now(TS_BEFORE_INITRAM); - printk(BIOS_DEBUG, "raminit_amdmct()\n"); - raminit_amdmct(sysinfo); - timestamp_add_now(TS_AFTER_INITRAM); - - cbmem_initialize_empty(); - post_code(0x41); - - amdmct_cbmem_store_info(sysinfo); - - bcm5785_early_setup(); -} - -/** - * BOOL AMD_CB_ManualBUIDSwapList(u8 Node, u8 Link, u8 **List) - * Description: - * This routine is called every time a non-coherent chain is processed. - * BUID assignment may be controlled explicitly on a non-coherent chain. Provide a - * swap list. The first part of the list controls the BUID assignment and the - * second part of the list provides the device to device linking. Device orientation - * can be detected automatically, or explicitly. See documentation for more details. - * - * Automatic non-coherent init assigns BUIDs starting at 1 and incrementing sequentially - * based on each device's unit count. - * - * Parameters: - * @param[in] node = The node on which this chain is located - * @param[in] link = The link on the host for this chain - * @param[out] List = supply a pointer to a list - */ -BOOL AMD_CB_ManualBUIDSwapList (u8 node, u8 link, const u8 **List) -{ - static const u8 swaplist[] = { 0xFF, CONFIG_HT_CHAIN_UNITID_BASE, CONFIG_HT_CHAIN_END_UNITID_BASE, 0xFF }; - /* If the BUID was adjusted in early_ht we need to do the manual override */ - if ((CONFIG_HT_CHAIN_UNITID_BASE != 0) && (CONFIG_HT_CHAIN_END_UNITID_BASE != 0)) { - printk(BIOS_DEBUG, "AMD_CB_ManualBUIDSwapList()\n"); - if ((node == 0) && (link == 0)) { /* BSP SB link */ - *List = swaplist; - return 1; - } - } - - return 0; -} diff --git a/src/mainboard/iei/Kconfig b/src/mainboard/iei/Kconfig deleted file mode 100644 index a1b47d5d9c..0000000000 --- a/src/mainboard/iei/Kconfig +++ /dev/null @@ -1,30 +0,0 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2009 Uwe Hermann -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; version 2 of the License. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## -if VENDOR_IEI - -choice - prompt "Mainboard model" - -source "src/mainboard/iei/*/Kconfig.name" - -endchoice - -source "src/mainboard/iei/*/Kconfig" - -config MAINBOARD_VENDOR - string - default "IEI" - -endif # VENDOR_IEI diff --git a/src/mainboard/iei/Kconfig.name b/src/mainboard/iei/Kconfig.name deleted file mode 100644 index 1dec78d8a1..0000000000 --- a/src/mainboard/iei/Kconfig.name +++ /dev/null @@ -1,2 +0,0 @@ -config VENDOR_IEI - bool "IEI" diff --git a/src/mainboard/iei/kino-780am2-fam10/Kconfig b/src/mainboard/iei/kino-780am2-fam10/Kconfig deleted file mode 100644 index 3f096d7738..0000000000 --- a/src/mainboard/iei/kino-780am2-fam10/Kconfig +++ /dev/null @@ -1,58 +0,0 @@ -if BOARD_IEI_KINO_FAM10 - -config BOARD_SPECIFIC_OPTIONS - def_bool y - select CPU_AMD_SOCKET_AM2R2 - select DIMM_DDR2 - select DIMM_REGISTERED - select NORTHBRIDGE_AMD_AMDFAM10 - select SOUTHBRIDGE_AMD_RS780 - select SOUTHBRIDGE_AMD_SB700 - select SUPERIO_FINTEK_F71859 - select HAVE_OPTION_TABLE - select HAVE_PIRQ_TABLE - select HAVE_MP_TABLE - select SB_HT_CHAIN_UNITID_OFFSET_ONLY - select LIFT_BSP_APIC_ID - select HAVE_ACPI_TABLES - select BOARD_ROMSIZE_KB_1024 - select ENABLE_APIC_EXT_ID - select GFXUMA - -config MAINBOARD_DIR - string - default iei/kino-780am2-fam10 - -config APIC_ID_OFFSET - hex - default 0x0 - -config MAINBOARD_PART_NUMBER - string - default "Kino-780AM2(Fam10)" - -config MAX_CPUS - int - default 8 - -config MAX_PHYSICAL_CPUS - int - default 2 - -config HT_CHAIN_END_UNITID_BASE - hex - default 0x1 - -config HT_CHAIN_UNITID_BASE - hex - default 0x0 - -config IRQ_SLOT_COUNT - int - default 11 - -config VGA_BIOS_ID - string - default "1002,9615" - -endif #BOARD_IEI_KINO_FAM10 diff --git a/src/mainboard/iei/kino-780am2-fam10/Kconfig.name b/src/mainboard/iei/kino-780am2-fam10/Kconfig.name deleted file mode 100644 index 20dfeda5b0..0000000000 --- a/src/mainboard/iei/kino-780am2-fam10/Kconfig.name +++ /dev/null @@ -1,2 +0,0 @@ -config BOARD_IEI_KINO_FAM10 - bool "Kino-780AM2(Fam10)" diff --git a/src/mainboard/iei/kino-780am2-fam10/Makefile.inc b/src/mainboard/iei/kino-780am2-fam10/Makefile.inc deleted file mode 100644 index 91d4b39c32..0000000000 --- a/src/mainboard/iei/kino-780am2-fam10/Makefile.inc +++ /dev/null @@ -1,16 +0,0 @@ -# -# This file is part of the coreboot project. -# -# This program is free software; you can redistribute it and/or modify -# it under the terms of the GNU General Public License as published by -# the Free Software Foundation; version 2 of the License. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# - -romstage-y += resourcemap.c - -ramstage-y += get_bus_conf.c diff --git a/src/mainboard/iei/kino-780am2-fam10/acpi/cpstate.asl b/src/mainboard/iei/kino-780am2-fam10/acpi/cpstate.asl deleted file mode 100644 index acaa5bae32..0000000000 --- a/src/mainboard/iei/kino-780am2-fam10/acpi/cpstate.asl +++ /dev/null @@ -1,80 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2010 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -/* This file defines the processor and performance state capability - * for each core in the system. It is included into the DSDT for each - * core. It assumes that each core of the system has the same performance - * characteristics. -*/ -/* -#include -DefinitionBlock ("DSDT.AML", "DSDT", 0x01, OEM_ID, ACPI_TABLE_CREATOR, 0x00010001) - { - Scope (\_PR) { - Device (CPU0) { - Name (_HID, "ACPI0007") - Name (_UID, 0) - #include "cpstate.asl" - } - Device (CPU1) { - Name (_HID, "ACPI0007") - Name (_UID, 1) - #include "cpstate.asl" - } - Device (CPU2) { - Name (_HID, "ACPI0007") - Name (_UID, 2) - #include "cpstate.asl" - } - Device (CPU3) { - Name (_HID, "ACPI0007") - Name (_UID, 3) - #include "cpstate.asl" - } - } -*/ - /* P-state support: The maximum number of P-states supported by the */ - /* CPUs we'll use is 6. */ - /* Get from AMI BIOS. */ - Name(_PSS, Package(){ - Package () - { - 0x00000AF0, - 0x0000BF81, - 0x00000002, - 0x00000002, - 0x00000000, - 0x00000000 - }, - - Package () - { - 0x00000578, - 0x000076F2, - 0x00000002, - 0x00000002, - 0x00000001, - 0x00000001 - } - }) - - Name(_PCT, Package(){ - ResourceTemplate(){Register(FFixedHW, 0, 0, 0)}, - ResourceTemplate(){Register(FFixedHW, 0, 0, 0)} - }) - - Method(_PPC, 0){ - Return(0) - } diff --git a/src/mainboard/iei/kino-780am2-fam10/acpi/ide.asl b/src/mainboard/iei/kino-780am2-fam10/acpi/ide.asl deleted file mode 100644 index 5c155cf301..0000000000 --- a/src/mainboard/iei/kino-780am2-fam10/acpi/ide.asl +++ /dev/null @@ -1,240 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2010 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -/* -Scope (_SB) { - Device(PCI0) { - Device(IDEC) { - Name(_ADR, 0x00140001) - #include "ide.asl" - } - } -} -*/ - -/* Some timing tables */ -Name(UDTT, Package(){ /* Udma timing table */ - 120, 90, 60, 45, 30, 20, 15, 0 /* UDMA modes 0 -> 6 */ -}) - -Name(MDTT, Package(){ /* MWDma timing table */ - 480, 150, 120, 0 /* Legacy DMA modes 0 -> 2 */ -}) - -Name(POTT, Package(){ /* Pio timing table */ - 600, 390, 270, 180, 120, 0 /* PIO modes 0 -> 4 */ -}) - -/* Some timing register value tables */ -Name(MDRT, Package(){ /* MWDma timing register table */ - 0x77, 0x21, 0x20, 0xFF /* Legacy DMA modes 0 -> 2 */ -}) - -Name(PORT, Package(){ - 0x99, 0x47, 0x34, 0x22, 0x20, 0x99 /* PIO modes 0 -> 4 */ -}) - -OperationRegion(ICRG, PCI_Config, 0x40, 0x20) /* ide control registers */ - Field(ICRG, AnyAcc, NoLock, Preserve) -{ - PPTS, 8, /* Primary PIO Slave Timing */ - PPTM, 8, /* Primary PIO Master Timing */ - OFFSET(0x04), PMTS, 8, /* Primary MWDMA Slave Timing */ - PMTM, 8, /* Primary MWDMA Master Timing */ - OFFSET(0x08), PPCR, 8, /* Primary PIO Control */ - OFFSET(0x0A), PPMM, 4, /* Primary PIO master Mode */ - PPSM, 4, /* Primary PIO slave Mode */ - OFFSET(0x14), PDCR, 2, /* Primary UDMA Control */ - OFFSET(0x16), PDMM, 4, /* Primary UltraDMA Mode */ - PDSM, 4, /* Primary UltraDMA Mode */ -} - -Method(GTTM, 1) /* get total time*/ -{ - Store(And(Arg0, 0x0F), Local0) /* Recovery Width */ - Increment(Local0) - Store(ShiftRight(Arg0, 4), Local1) /* Command Width */ - Increment(Local1) - Return(Multiply(30, Add(Local0, Local1))) -} - -Device(PRID) -{ - Name (_ADR, Zero) - Method(_GTM, 0) - { - NAME(OTBF, Buffer(20) { /* out buffer */ - 0xFF, 0xFF, 0xFF, 0xFF, - 0xFF, 0xFF, 0xFF, 0xFF, - 0xFF, 0xFF, 0xFF, 0xFF, - 0xFF, 0xFF, 0xFF, 0xFF, 0x00, 0x00, 0x00, 0x00 - }) - - CreateDwordField(OTBF, 0, PSD0) /* PIO spd0 */ - CreateDwordField(OTBF, 4, DSD0) /* DMA spd0 */ - CreateDwordField(OTBF, 8, PSD1) /* PIO spd1 */ - CreateDwordField(OTBF, 12, DSD1) /* DMA spd1 */ - CreateDwordField(OTBF, 16, BFFG) /* buffer flags */ - - /* Just return if the channel is disabled */ - If(And(PPCR, 0x01)) { /* primary PIO control */ - Return(OTBF) - } - - /* Always tell them independent timing available and IOChannelReady used on both drives */ - Or(BFFG, 0x1A, BFFG) - - Store(GTTM(PPTM), PSD0) /* save total time of primary PIO master timming to PIO spd0 */ - Store(GTTM(PPTS), PSD1) /* save total time of primary PIO slave Timing to PIO spd1 */ - - If(And(PDCR, 0x01)) { /* It's under UDMA mode */ - Or(BFFG, 0x01, BFFG) - Store(DerefOf(Index(UDTT, PDMM)), DSD0) - } - Else { - Store(GTTM(PMTM), DSD0) /* Primary MWDMA Master Timing, DmaSpd0 */ - } - - If(And(PDCR, 0x02)) { /* It's under UDMA mode */ - Or(BFFG, 0x04, BFFG) - Store(DerefOf(Index(UDTT, PDSM)), DSD1) - } - Else { - Store(GTTM(PMTS), DSD1) /* Primary MWDMA Slave Timing, DmaSpd0 */ - } - - Return(OTBF) /* out buffer */ - } /* End Method(_GTM) */ - - Method(_STM, 3, NotSerialized) - { - NAME(INBF, Buffer(20) { /* in buffer */ - 0xFF, 0xFF, 0xFF, 0xFF, - 0xFF, 0xFF, 0xFF, 0xFF, - 0xFF, 0xFF, 0xFF, 0xFF, - 0xFF, 0xFF, 0xFF, 0xFF, 0x00, 0x00, 0x00, 0x00 - }) - - CreateDwordField(INBF, 0, PSD0) /* PIO spd0 */ - CreateDwordField(INBF, 4, DSD0) /* PIO spd0 */ - CreateDwordField(INBF, 8, PSD1) /* PIO spd1 */ - CreateDwordField(INBF, 12, DSD1) /* DMA spd1 */ - CreateDwordField(INBF, 16, BFFG) /*buffer flag */ - - Store(Match(POTT, MLE, PSD0, MTR, 0, 0), Local0) - Divide(Local0, 5, PPMM,) /* Primary PIO master Mode */ - Store(Match(POTT, MLE, PSD1, MTR, 0, 0), Local1) - Divide(Local1, 5, PPSM,) /* Primary PIO slave Mode */ - - Store(DerefOf(Index(PORT, Local0)), PPTM) /* Primary PIO Master Timing */ - Store(DerefOf(Index(PORT, Local1)), PPTS) /* Primary PIO Slave Timing */ - - If(And(BFFG, 0x01)) { /* Drive 0 is under UDMA mode */ - Store(Match(UDTT, MLE, DSD0, MTR, 0, 0), Local0) - Divide(Local0, 7, PDMM,) - Or(PDCR, 0x01, PDCR) - } - Else { - If(LNotEqual(DSD0, 0xFFFFFFFF)) { - Store(Match(MDTT, MLE, DSD0, MTR, 0, 0), Local0) - Store(DerefOf(Index(MDRT, Local0)), PMTM) - } - } - - If(And(BFFG, 0x04)) { /* Drive 1 is under UDMA mode */ - Store(Match(UDTT, MLE, DSD1, MTR, 0, 0), Local0) - Divide(Local0, 7, PDSM,) - Or(PDCR, 0x02, PDCR) - } - Else { - If(LNotEqual(DSD1, 0xFFFFFFFF)) { - Store(Match(MDTT, MLE, DSD1, MTR, 0, 0), Local0) - Store(DerefOf(Index(MDRT, Local0)), PMTS) - } - } - /* Return(INBF) */ - } /*End Method(_STM) */ - Device(MST) - { - Name(_ADR, 0) - Method(_GTF) { - Name(CMBF, Buffer(21) { - 0x03, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xEF, - 0x03, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xEF, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xF5 - }) - CreateByteField(CMBF, 1, POMD) - CreateByteField(CMBF, 8, DMMD) - CreateByteField(CMBF, 5, CMDA) - CreateByteField(CMBF, 12, CMDB) - CreateByteField(CMBF, 19, CMDC) - - Store(0xA0, CMDA) - Store(0xA0, CMDB) - Store(0xA0, CMDC) - - Or(PPMM, 0x08, POMD) - - If(And(PDCR, 0x01)) { - Or(PDMM, 0x40, DMMD) - } - Else { - Store(Match - (MDTT, MLE, GTTM(PMTM), - MTR, 0, 0), Local0) - If(LLess(Local0, 3)) { - Or(0x20, Local0, DMMD) - } - } - Return(CMBF) - } - } /* End Device(MST) */ - - Device(SLAV) - { - Name(_ADR, 1) - Method(_GTF) { - Name(CMBF, Buffer(21) { - 0x03, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xEF, - 0x03, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xEF, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xF5 - }) - CreateByteField(CMBF, 1, POMD) - CreateByteField(CMBF, 8, DMMD) - CreateByteField(CMBF, 5, CMDA) - CreateByteField(CMBF, 12, CMDB) - CreateByteField(CMBF, 19, CMDC) - - Store(0xB0, CMDA) - Store(0xB0, CMDB) - Store(0xB0, CMDC) - - Or(PPSM, 0x08, POMD) - - If(And(PDCR, 0x02)) { - Or(PDSM, 0x40, DMMD) - } - Else { - Store(Match - (MDTT, MLE, GTTM(PMTS), - MTR, 0, 0), Local0) - If(LLess(Local0, 3)) { - Or(0x20, Local0, DMMD) - } - } - Return(CMBF) - } - } /* End Device(SLAV) */ -} diff --git a/src/mainboard/iei/kino-780am2-fam10/acpi/routing.asl b/src/mainboard/iei/kino-780am2-fam10/acpi/routing.asl deleted file mode 100644 index 4c3075c368..0000000000 --- a/src/mainboard/iei/kino-780am2-fam10/acpi/routing.asl +++ /dev/null @@ -1,334 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2010 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -/* -#include -DefinitionBlock ("DSDT.AML", "DSDT", 0x01, OEM_ID, ACPI_TABLE_CREATOR, 0x00010001 - ) - { - #include "routing.asl" - } -*/ - -/* Routing is in System Bus scope */ -Scope(\_SB) { - Name(PR0, Package(){ - /* NB devices */ - /* Bus 0, Dev 0 - RS780 Host Controller */ - /* Bus 0, Dev 1 - PCI Bridge for Internal Graphics */ - Package(){0x0001FFFF, 0, INTC, 0 }, - Package(){0x0001FFFF, 1, INTD, 0 }, - /* Bus 0, Dev 2 - PCIe Bridge for x8 PCIe Slot (GFX0) */ - Package(){0x0002FFFF, 0, INTC, 0 }, - Package(){0x0002FFFF, 1, INTD, 0 }, - Package(){0x0002FFFF, 2, INTA, 0 }, - Package(){0x0002FFFF, 3, INTB, 0 }, - /* Bus 0, Dev 3 - PCIe graphics port 1 bridge */ - /* Bus 0, Dev 4 - PCIe Bridge for Express Card Slot */ - Package(){0x0004FFFF, 0, INTA, 0 }, - Package(){0x0004FFFF, 1, INTB, 0 }, - Package(){0x0004FFFF, 2, INTC, 0 }, - Package(){0x0004FFFF, 3, INTD, 0 }, - /* Bus 0, Dev 5 - General purpose PCIe bridge 5 */ - /* Package(){0x0005FFFF, 0, INTB, 0 }, */ - /* Package(){0x0005FFFF, 1, INTC, 0 }, */ - /* Package(){0x0005FFFF, 2, INTD, 0 }, */ - /* Package(){0x0005FFFF, 3, INTA, 0 }, */ - /* Bus 0, Dev 6 - PCIe Bridge for Ethernet Chip */ - Package(){0x0006FFFF, 0, INTC, 0 }, - Package(){0x0006FFFF, 1, INTD, 0 }, - Package(){0x0006FFFF, 2, INTA, 0 }, - Package(){0x0006FFFF, 3, INTB, 0 }, - /* Bus 0, Dev 7 - PCIe Bridge for x1 PCIe Slot */ - Package(){0x0007FFFF, 0, INTD, 0 }, - Package(){0x0007FFFF, 1, INTA, 0 }, - Package(){0x0007FFFF, 2, INTB, 0 }, - Package(){0x0007FFFF, 3, INTC, 0 }, - - Package(){0x0009FFFF, 0, INTB, 0 }, - Package(){0x0009FFFF, 1, INTC, 0 }, - Package(){0x0009FFFF, 2, INTD, 0 }, - Package(){0x0009FFFF, 3, INTA, 0 }, - - Package(){0x000AFFFF, 0, INTC, 0 }, - Package(){0x000AFFFF, 1, INTD, 0 }, - Package(){0x000AFFFF, 2, INTA, 0 }, - Package(){0x000AFFFF, 3, INTB, 0 }, - - Package(){0x000BFFFF, 0, INTD, 0 }, - Package(){0x000BFFFF, 1, INTA, 0 }, - Package(){0x000BFFFF, 2, INTB, 0 }, - Package(){0x000BFFFF, 3, INTC, 0 }, - - Package(){0x000CFFFF, 0, INTA, 0 }, - Package(){0x000CFFFF, 1, INTB, 0 }, - Package(){0x000CFFFF, 2, INTC, 0 }, - Package(){0x000CFFFF, 3, INTD, 0 }, - - /* Bus 0, Funct 8 - Southbridge port (normally hidden) */ - - /* SB devices */ - /* Bus 0, Dev 17 - SATA controller #2 */ - /* Bus 0, Dev 18 - SATA controller #1 */ - Package(){0x0011FFFF, 0, INTG, 0 }, - - /* Bus 0, Dev 19 - USB: OHCI, dev 18,19 func 0-2, dev 20 func 5; - * EHCI, dev 18, 19 func 2 */ - Package(){0x0012FFFF, 0, INTA, 0 }, - Package(){0x0012FFFF, 1, INTB, 0 }, - Package(){0x0012FFFF, 2, INTC, 0 }, - Package(){0x0012FFFF, 3, INTD, 0 }, - - Package(){0x0013FFFF, 0, INTC, 0 }, - Package(){0x0013FFFF, 1, INTD, 0 }, - Package(){0x0013FFFF, 2, INTA, 0 }, - Package(){0x0013FFFF, 3, INTB, 0 }, - - /* Package(){0x0014FFFF, 1, INTA, 0 }, */ - - /* Bus 0, Dev 20 - F0:SMBus/ACPI,F1:IDE;F2:HDAudio;F3:LPC;F4:PCIBridge;F5:USB */ - Package(){0x0014FFFF, 0, INTA, 0 }, - Package(){0x0014FFFF, 1, INTB, 0 }, - Package(){0x0014FFFF, 2, INTC, 0 }, - Package(){0x0014FFFF, 3, INTD, 0 }, - -/* Package(){0x0015FFFF, 0, INTA, 0 }, - Package(){0x0015FFFF, 1, INTB, 0 }, - Package(){0x0015FFFF, 2, INTC, 0 }, - Package(){0x0015FFFF, 3, INTD, 0 }, -*/ - }) - - Name(APR0, Package(){ - /* NB devices in APIC mode */ - /* Bus 0, Dev 0 - RS780 Host Controller */ - - /* Bus 0, Dev 1 - PCI Bridge for Internal Graphics */ - /* Package(){0x0001FFFF, 0, 0, 18 }, */ - /* Package(){0x0001FFFF, 1, 0, 19 }, */ - - /* Bus 0, Dev 2 - PCIe Bridge for x8 PCIe Slot (GFX0) */ - Package(){0x0002FFFF, 0, 0, 18 }, - /* Package(){0x0002FFFF, 1, 0, 19 }, */ - /* Package(){0x0002FFFF, 2, 0, 16 }, */ - /* Package(){0x0002FFFF, 3, 0, 17 }, */ - - /* Bus 0, Dev 3 - PCIe graphics port 1 bridge */ - Package(){0x0003FFFF, 0, 0, 19 }, - - /* Bus 0, Dev 4 - PCIe Bridge for Express Card Slot */ - Package(){0x0004FFFF, 0, 0, 16 }, - /* Package(){0x0004FFFF, 1, 0, 17 }, */ - /* Package(){0x0004FFFF, 2, 0, 18 }, */ - /* Package(){0x0004FFFF, 3, 0, 19 }, */ - - /* Bus 0, Dev 5 - General purpose PCIe bridge 5 */ - /* Package(){0x0005FFFF, 0, 0, 17 }, */ - /* Package(){0x0005FFFF, 1, 0, 18 }, */ - /* Package(){0x0005FFFF, 2, 0, 19 }, */ - /* Package(){0x0005FFFF, 3, 0, 16 }, */ - - /* Bus 0, Dev 6 - General purpose PCIe bridge 6 */ - /* Package(){0x0006FFFF, 0, 0, 18 }, */ - /* Package(){0x0006FFFF, 1, 0, 19 }, */ - /* Package(){0x0006FFFF, 2, 0, 16 }, */ - /* Package(){0x0006FFFF, 3, 0, 17 }, */ - - /* Bus 0, Dev 7 - PCIe Bridge for network card */ - /* Package(){0x0007FFFF, 0, 0, 19 }, */ - /* Package(){0x0007FFFF, 1, 0, 16 }, */ - /* Package(){0x0007FFFF, 2, 0, 17 }, */ - /* Package(){0x0007FFFF, 3, 0, 18 }, */ - - /* Bus 0, Dev 9 - PCIe Bridge for network card */ - Package(){0x0009FFFF, 0, 0, 17 }, - /* Package(){0x0009FFFF, 1, 0, 16 }, */ - /* Package(){0x0009FFFF, 2, 0, 17 }, */ - /* Package(){0x0009FFFF, 3, 0, 18 }, */ - - /* Bus 0, Dev A - PCIe Bridge for network card */ - Package(){0x000AFFFF, 0, 0, 18 }, - /* Package(){0x000AFFFF, 1, 0, 16 }, */ - /* Package(){0x000AFFFF, 2, 0, 17 }, */ - /* Package(){0x000AFFFF, 3, 0, 18 }, */ - - /* Bus 0, Funct 8 - Southbridge port (normally hidden) */ - - /* SB devices in APIC mode */ - /* Bus 0, Dev 17 - SATA controller #2 */ - /* Bus 0, Dev 18 - SATA controller #1 */ - Package(){0x0011FFFF, 0, 0, 22 }, - - /* Bus 0, Dev 19 - USB: OHCI, dev 18,19 func 0-2, dev 20 func 5; - * EHCI, dev 18, 19 func 2 */ - Package(){0x0012FFFF, 0, 0, 16 }, - Package(){0x0012FFFF, 1, 0, 17 }, - Package(){0x0012FFFF, 2, 0, 18 }, - Package(){0x0012FFFF, 3, 0, 19 }, - - Package(){0x0013FFFF, 0, 0, 18 }, - Package(){0x0013FFFF, 1, 0, 19 }, - Package(){0x0013FFFF, 2, 0, 16 }, - Package(){0x0013FFFF, 3, 0, 17 }, - - /* Bus 0, Dev 20 - F0:SMBus/ACPI, F1:IDE; F2:HDAudio; F3:LPC; F4:PCIBridge; F5:USB */ - Package(){0x0014FFFF, 0, 0, 16 }, - Package(){0x0014FFFF, 1, 0, 17 }, - Package(){0x0014FFFF, 2, 0, 18 }, - Package(){0x0014FFFF, 3, 0, 19 }, - }) - - Name(PR1, Package(){ - /* Internal graphics - RS780 VGA, Bus1, Dev5 */ - Package(){0x0005FFFF, 0, INTC, 0 }, - Package(){0x0005FFFF, 1, INTD, 0 }, - Package(){0x0005FFFF, 2, INTA, 0 }, - Package(){0x0005FFFF, 3, INTB, 0 }, - }) - - Name(APR1, Package(){ - /* Internal graphics - RS780 VGA, Bus1, Dev5 */ - Package(){0x0005FFFF, 0, 0, 18 }, - Package(){0x0005FFFF, 1, 0, 19 }, - Package(){0x0005FFFF, 2, 0, 16 }, - Package(){0x0005FFFF, 3, 0, 17 }, - }) - - Name(PS2, Package(){ - /* The external GFX - Hooked to PCIe slot 2 */ - Package(){0x0000FFFF, 0, INTC, 0 }, - Package(){0x0000FFFF, 1, INTD, 0 }, - Package(){0x0000FFFF, 2, INTA, 0 }, - Package(){0x0000FFFF, 3, INTB, 0 }, - }) - - Name(APS2, Package(){ - /* The external GFX - Hooked to PCIe slot 2 */ - Package(){0x0000FFFF, 0, 0, 18 }, - Package(){0x0000FFFF, 1, 0, 19 }, - Package(){0x0000FFFF, 2, 0, 16 }, - Package(){0x0000FFFF, 3, 0, 17 }, - }) - - Name(PS4, Package(){ - /* PCIe slot - Hooked to PCIe slot 4 */ - Package(){0x0000FFFF, 0, INTD, 0 }, - Package(){0x0000FFFF, 1, INTA, 0 }, - Package(){0x0000FFFF, 2, INTB, 0 }, - Package(){0x0000FFFF, 3, INTC, 0 }, - }) - - Name(APS4, Package(){ - /* PCIe slot - Hooked to PCIe slot 4 */ - Package(){0x0000FFFF, 0, 0, 16 }, - Package(){0x0000FFFF, 1, 0, 17 }, - Package(){0x0000FFFF, 2, 0, 18 }, - Package(){0x0000FFFF, 3, 0, 19 }, - }) - - Name(PS5, Package(){ - /* PCIe slot - Hooked to PCIe slot 5 */ - Package(){0x0000FFFF, 0, INTB, 0 }, - Package(){0x0000FFFF, 1, INTC, 0 }, - Package(){0x0000FFFF, 2, INTD, 0 }, - Package(){0x0000FFFF, 3, INTA, 0 }, - }) - - Name(APS5, Package(){ - /* PCIe slot - Hooked to PCIe slot 5 */ - Package(){0x0000FFFF, 0, 0, 17 }, - Package(){0x0000FFFF, 1, 0, 18 }, - Package(){0x0000FFFF, 2, 0, 19 }, - Package(){0x0000FFFF, 3, 0, 16 }, - }) - - Name(PS6, Package(){ - /* PCIe slot - Hooked to PCIe slot 6 */ - Package(){0x0000FFFF, 0, INTC, 0 }, - Package(){0x0000FFFF, 1, INTD, 0 }, - Package(){0x0000FFFF, 2, INTA, 0 }, - Package(){0x0000FFFF, 3, INTB, 0 }, - }) - - Name(APS6, Package(){ - /* PCIe slot - Hooked to PCIe slot 6 */ - Package(){0x0000FFFF, 0, 0, 18 }, - Package(){0x0000FFFF, 1, 0, 19 }, - Package(){0x0000FFFF, 2, 0, 16 }, - Package(){0x0000FFFF, 3, 0, 17 }, - }) - - Name(PS7, Package(){ - /* The onboard Ethernet chip - Hooked to PCIe slot 7 */ - Package(){0x0000FFFF, 0, INTD, 0 }, - Package(){0x0000FFFF, 1, INTA, 0 }, - Package(){0x0000FFFF, 2, INTB, 0 }, - Package(){0x0000FFFF, 3, INTC, 0 }, - }) - - Name(APS7, Package(){ - /* The onboard Ethernet chip - Hooked to PCIe slot 7 */ - Package(){0x0000FFFF, 0, 0, 19 }, - Package(){0x0000FFFF, 1, 0, 16 }, - Package(){0x0000FFFF, 2, 0, 17 }, - Package(){0x0000FFFF, 3, 0, 18 }, - }) - Name(PS9, Package(){ - /* PCIe slot - Hooked to PCIe slot 9 */ - Package(){0x0000FFFF, 0, INTD, 0 }, - Package(){0x0000FFFF, 1, INTA, 0 }, - Package(){0x0000FFFF, 2, INTB, 0 }, - Package(){0x0000FFFF, 3, INTC, 0 }, - }) - - Name(APS9, Package(){ - /* PCIe slot - Hooked to PCIe slot 9 */ - Package(){0x0000FFFF, 0, 0, 19 }, - Package(){0x0000FFFF, 1, 0, 16 }, - Package(){0x0000FFFF, 2, 0, 17 }, - Package(){0x0000FFFF, 3, 0, 18 }, - }) - Name(PSa, Package(){ - /* PCIe slot - Hooked to PCIe slot 10 */ - Package(){0x0000FFFF, 0, INTD, 0 }, - Package(){0x0000FFFF, 1, INTA, 0 }, - Package(){0x0000FFFF, 2, INTB, 0 }, - Package(){0x0000FFFF, 3, INTC, 0 }, - }) - - Name(APSa, Package(){ - /* PCIe slot - Hooked to PCIe slot 10 */ - Package(){0x0000FFFF, 0, 0, 18 }, - Package(){0x0000FFFF, 1, 0, 16 }, - Package(){0x0000FFFF, 2, 0, 17 }, - Package(){0x0000FFFF, 3, 0, 18 }, - }) - - Name(PCIB, Package(){ - /* PCI slots: slot 0, slot 1, slot 2 behind Dev14, Fun4. */ - Package(){0x0005FFFF, 0, 0, 0x14 }, - Package(){0x0005FFFF, 1, 0, 0x15 }, - Package(){0x0005FFFF, 2, 0, 0x16 }, - Package(){0x0005FFFF, 3, 0, 0x17 }, - Package(){0x0006FFFF, 0, 0, 0x15 }, - Package(){0x0006FFFF, 1, 0, 0x16 }, - Package(){0x0006FFFF, 2, 0, 0x17 }, - Package(){0x0006FFFF, 3, 0, 0x14 }, - Package(){0x0007FFFF, 0, 0, 0x16 }, - Package(){0x0007FFFF, 1, 0, 0x17 }, - Package(){0x0007FFFF, 2, 0, 0x14 }, - Package(){0x0007FFFF, 3, 0, 0x15 }, - }) -} diff --git a/src/mainboard/iei/kino-780am2-fam10/acpi/sata.asl b/src/mainboard/iei/kino-780am2-fam10/acpi/sata.asl deleted file mode 100644 index cb9b221ba3..0000000000 --- a/src/mainboard/iei/kino-780am2-fam10/acpi/sata.asl +++ /dev/null @@ -1,145 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2010 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -/* simple name description */ - -/* -Scope (_SB) { - Device(PCI0) { - Device(SATA) { - Name(_ADR, 0x00110000) - #include "sata.asl" - } - } -} -*/ - -Name(STTM, Buffer(20) { - 0x78, 0x00, 0x00, 0x00, 0x0f, 0x00, 0x00, 0x00, - 0x78, 0x00, 0x00, 0x00, 0x0f, 0x00, 0x00, 0x00, - 0x1f, 0x00, 0x00, 0x00 -}) - -/* Start by clearing the PhyRdyChg bits */ -Method(_INI) { - \_GPE._L1F() -} - -Device(PMRY) -{ - Name(_ADR, 0) - Method(_GTM, 0x0, NotSerialized) { - Return(STTM) - } - Method(_STM, 0x3, NotSerialized) {} - - Device(PMST) { - Name(_ADR, 0) - Method(_STA,0) { - if (LGreater(P0IS,0)) { - return (0x0F) /* sata is visible */ - } - else { - return (0x00) /* sata is missing */ - } - } - }/* end of PMST */ - - Device(PSLA) - { - Name(_ADR, 1) - Method(_STA,0) { - if (LGreater(P1IS,0)) { - return (0x0F) /* sata is visible */ - } - else { - return (0x00) /* sata is missing */ - } - } - } /* end of PSLA */ -} /* end of PMRY */ - - -Device(SEDY) -{ - Name(_ADR, 1) /* IDE Scondary Channel */ - Method(_GTM, 0x0, NotSerialized) { - Return(STTM) - } - Method(_STM, 0x3, NotSerialized) {} - - Device(SMST) - { - Name(_ADR, 0) - Method(_STA,0) { - if (LGreater(P2IS,0)) { - return (0x0F) /* sata is visible */ - } - else { - return (0x00) /* sata is missing */ - } - } - } /* end of SMST */ - - Device(SSLA) - { - Name(_ADR, 1) - Method(_STA,0) { - if (LGreater(P3IS,0)) { - return (0x0F) /* sata is visible */ - } - else { - return (0x00) /* sata is missing */ - } - } - } /* end of SSLA */ -} /* end of SEDY */ - -/* SATA Hot Plug Support */ -Scope(\_GPE) { - Method(_L1F,0x0,NotSerialized) { - if (\_SB.P0PR) { - if (LGreater(\_SB.P0IS,0)) { - sleep(32) - } - Notify(\_SB.PCI0.STCR.PMRY.PMST, 0x01) /* NOTIFY_DEVICE_CHECK */ - store(one, \_SB.P0PR) - } - - if (\_SB.P1PR) { - if (LGreater(\_SB.P1IS,0)) { - sleep(32) - } - Notify(\_SB.PCI0.STCR.PMRY.PSLA, 0x01) /* NOTIFY_DEVICE_CHECK */ - store(one, \_SB.P1PR) - } - - if (\_SB.P2PR) { - if (LGreater(\_SB.P2IS,0)) { - sleep(32) - } - Notify(\_SB.PCI0.STCR.SEDY.SMST, 0x01) /* NOTIFY_DEVICE_CHECK */ - store(one, \_SB.P2PR) - } - - if (\_SB.P3PR) { - if (LGreater(\_SB.P3IS,0)) { - sleep(32) - } - Notify(\_SB.PCI0.STCR.SEDY.SSLA, 0x01) /* NOTIFY_DEVICE_CHECK */ - store(one, \_SB.P3PR) - } - } -} diff --git a/src/mainboard/iei/kino-780am2-fam10/acpi/usb.asl b/src/mainboard/iei/kino-780am2-fam10/acpi/usb.asl deleted file mode 100644 index a3ccb97ff9..0000000000 --- a/src/mainboard/iei/kino-780am2-fam10/acpi/usb.asl +++ /dev/null @@ -1,158 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2010 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -/* simple name description */ -/* -#include -DefinitionBlock ("DSDT.AML", "DSDT", 0x01, OEM_ID, ACPI_TABLE_CREATOR, 0x00010001 - ) - { - #include "usb.asl" - } -*/ -Method(UCOC, 0) { - Sleep(20) - Store(0x13,CMTI) - Store(0,GPSL) -} - -/* USB Port 0 overcurrent uses Gpm 0 */ -If(LLessEqual(UOM0,9)) { - Scope (\_GPE) { - Method (_L13) { - UCOC() - if(LEqual(GPB0,PLC0)) { - Not(PLC0,PLC0) - Store(PLC0, \_SB.PT0D) - } - } - } -} - -/* USB Port 1 overcurrent uses Gpm 1 */ -If (LLessEqual(UOM1,9)) { - Scope (\_GPE) { - Method (_L14) { - UCOC() - if (LEqual(GPB1,PLC1)) { - Not(PLC1,PLC1) - Store(PLC1, \_SB.PT1D) - } - } - } -} - -/* USB Port 2 overcurrent uses Gpm 2 */ -If (LLessEqual(UOM2,9)) { - Scope (\_GPE) { - Method (_L15) { - UCOC() - if (LEqual(GPB2,PLC2)) { - Not(PLC2,PLC2) - Store(PLC2, \_SB.PT2D) - } - } - } -} - -/* USB Port 3 overcurrent uses Gpm 3 */ -If (LLessEqual(UOM3,9)) { - Scope (\_GPE) { - Method (_L16) { - UCOC() - if (LEqual(GPB3,PLC3)) { - Not(PLC3,PLC3) - Store(PLC3, \_SB.PT3D) - } - } - } -} - -/* USB Port 4 overcurrent uses Gpm 4 */ -If (LLessEqual(UOM4,9)) { - Scope (\_GPE) { - Method (_L19) { - UCOC() - if (LEqual(GPB4,PLC4)) { - Not(PLC4,PLC4) - Store(PLC4, \_SB.PT4D) - } - } - } -} - -/* USB Port 5 overcurrent uses Gpm 5 */ -If (LLessEqual(UOM5,9)) { - Scope (\_GPE) { - Method (_L1A) { - UCOC() - if (LEqual(GPB5,PLC5)) { - Not(PLC5,PLC5) - Store(PLC5, \_SB.PT5D) - } - } - } -} - -/* USB Port 6 overcurrent uses Gpm 6 */ -If (LLessEqual(UOM6,9)) { - Scope (\_GPE) { - /* Method (_L1C) { */ - Method (_L06) { - UCOC() - if (LEqual(GPB6,PLC6)) { - Not(PLC6,PLC6) - Store(PLC6, \_SB.PT6D) - } - } - } -} - -/* USB Port 7 overcurrent uses Gpm 7 */ -If (LLessEqual(UOM7,9)) { - Scope (\_GPE) { - /* Method (_L1D) { */ - Method (_L07) { - UCOC() - if (LEqual(GPB7,PLC7)) { - Not(PLC7,PLC7) - Store(PLC7, \_SB.PT7D) - } - } - } -} - -/* USB Port 8 overcurrent uses Gpm 8 */ -If (LLessEqual(UOM8,9)) { - Scope (\_GPE) { - Method (_L17) { - if (LEqual(G8IS,PLC8)) { - Not(PLC8,PLC8) - Store(PLC8, \_SB.PT8D) - } - } - } -} - -/* USB Port 9 overcurrent uses Gpm 9 */ -If (LLessEqual(UOM9,9)) { - Scope (\_GPE) { - Method (_L0E) { - if (LEqual(G9IS,0)) { - Store(1,\_SB.PT9D) - } - } - } -} diff --git a/src/mainboard/iei/kino-780am2-fam10/acpi_tables.c b/src/mainboard/iei/kino-780am2-fam10/acpi_tables.c deleted file mode 100644 index 6cdf89ac26..0000000000 --- a/src/mainboard/iei/kino-780am2-fam10/acpi_tables.c +++ /dev/null @@ -1,44 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2010-2011 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include -#include - -unsigned long acpi_fill_madt(unsigned long current) -{ - /* create all subtables for processors */ - current = acpi_create_madt_lapics(current); - - /* Write SB700 IOAPIC, only one */ - current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, - CONFIG_MAX_CPUS, IO_APIC_ADDR, 0); - - current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) - current, 0, 0, 2, 0); - current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) - current, 0, 9, 9, 0xF); - /* 0: mean bus 0--->ISA */ - /* 0: PIC 0 */ - /* 2: APIC 2 */ - /* 5 mean: 0101 --> Edge-triggered, Active high */ - - /* create all subtables for processors */ - /* current = acpi_create_madt_lapic_nmis(current, 5, 1); */ - /* 1: LINT1 connect to NMI */ - - return current; -} diff --git a/src/mainboard/iei/kino-780am2-fam10/board_info.txt b/src/mainboard/iei/kino-780am2-fam10/board_info.txt deleted file mode 100644 index 82656426d2..0000000000 --- a/src/mainboard/iei/kino-780am2-fam10/board_info.txt +++ /dev/null @@ -1,4 +0,0 @@ -Board name: Kino-780AM2 -Category: half -Board URL: http://web.archive.org/web/20111208234719/http://ieiworld.com/product_groups/industrial/content.aspx?gid=00001000010000000001&cid=09050652111816087425&id=09069696333360342284 -ROM protocol: SPI diff --git a/src/mainboard/iei/kino-780am2-fam10/cmos.layout b/src/mainboard/iei/kino-780am2-fam10/cmos.layout deleted file mode 100644 index 6c3d3f6c9e..0000000000 --- a/src/mainboard/iei/kino-780am2-fam10/cmos.layout +++ /dev/null @@ -1,52 +0,0 @@ -entries - -0 384 r 0 reserved_memory -384 1 e 4 boot_option -388 4 h 0 reboot_counter -#392 3 r 0 unused -395 1 e 1 hw_scrubber -396 1 e 1 interleave_chip_selects -397 2 e 8 max_mem_clock -399 1 e 2 multi_core -400 1 e 1 power_on_after_fail -412 4 e 6 debug_level -440 4 e 9 slow_cpu -444 1 e 1 nmi -445 1 e 1 gart -456 1 e 1 ECC_memory -728 256 h 0 user_data -984 16 h 0 check_sum -# Reserve the extended AMD configuration registers -1000 24 r 0 amd_reserved - - - -enumerations - -#ID value text -1 0 Disable -1 1 Enable -2 0 Enable -2 1 Disable -4 0 Fallback -4 1 Normal -6 5 Notice -6 6 Info -6 7 Debug -6 8 Spew -8 0 400Mhz -8 1 333Mhz -8 2 266Mhz -8 3 200Mhz -9 0 off -9 1 87.5% -9 2 75.0% -9 3 62.5% -9 4 50.0% -9 5 37.5% -9 6 25.0% -9 7 12.5% - -checksums - -checksum 392 983 984 diff --git a/src/mainboard/iei/kino-780am2-fam10/devicetree.cb b/src/mainboard/iei/kino-780am2-fam10/devicetree.cb deleted file mode 100644 index 6517c97f0f..0000000000 --- a/src/mainboard/iei/kino-780am2-fam10/devicetree.cb +++ /dev/null @@ -1,70 +0,0 @@ -# Config for iei/kino-780am2-fam10 -chip northbridge/amd/amdfam10/root_complex - device cpu_cluster 0 on - chip cpu/amd/socket_AM2r2 #L1 and DDR2 - device lapic 0 on end - end - end - device domain 0 on - chip northbridge/amd/amdfam10 - device pci 18.0 on # northbridge - chip southbridge/amd/rs780 - device pci 0.0 on end # HT 0x9600 - device pci 1.0 on end # Internal Graphics P2P bridge 0x9602 - device pci 2.0 on end # PCIE P2P bridge (external graphics) 0x9603 - device pci 3.0 on end # PCIE P2P bridge 0x960b - device pci 4.0 on end # PCIE P2P bridge 0x9604 - device pci 5.0 on end # PCIE P2P bridge 0x9605 - device pci 6.0 off end # PCIE P2P bridge 0x9606 - device pci 7.0 off end # PCIE P2P bridge 0x9607 - device pci 8.0 off end # NB/SB Link P2P bridge - device pci 9.0 on end # - device pci a.0 on end # - register "gppsb_configuration" = "1" # Configuration B - register "gpp_configuration" = "3" # Configuration D default - register "port_enable" = "0x6fc" - register "gfx_dev2_dev3" = "1" - register "gfx_dual_slot" = "1" - register "gfx_lane_reversal" = "0" - register "gfx_tmds" = "0" - register "gfx_compliance" = "0" - register "gfx_reconfiguration" = "1" - register "gfx_link_width" = "0" - end - chip southbridge/amd/sb700 # it is under NB/SB Link, but on the same pri bus - device pci 11.0 on end # SATA - device pci 12.0 on end # USB - device pci 12.1 on end # USB - device pci 12.2 on end # USB - device pci 13.0 on end # USB - device pci 13.1 on end # USB - device pci 13.2 on end # USB - device pci 14.0 on # SM - chip drivers/generic/generic #dimm 0-0-0 - device i2c 50 on end - end - chip drivers/generic/generic #dimm 0-0-1 - device i2c 51 on end - end - end # SM - device pci 14.1 on end # IDE 0x439c - device pci 14.2 on end # HDA 0x4383 - device pci 14.3 on # LPC 0x439d - chip superio/fintek/f71859 - device pnp 2e.3 on # Com1 - io 0x60 = 0x3f8 - irq 0x70 = 4 - end - end #SIO - end #LPC - device pci 14.4 on end # PCI 0x4384 - device pci 14.5 on end # USB 2 - register "boot_switch_sata_ide" = "0" # 0: boot from SATA. 1: IDE - end #southbridge/amd/sb700 - end # device pci 18.0 - device pci 18.1 on end - device pci 18.2 on end - device pci 18.3 on end - end - end #domain -end #root_complex diff --git a/src/mainboard/iei/kino-780am2-fam10/dsdt.asl b/src/mainboard/iei/kino-780am2-fam10/dsdt.asl deleted file mode 100644 index ffbe3ac974..0000000000 --- a/src/mainboard/iei/kino-780am2-fam10/dsdt.asl +++ /dev/null @@ -1,1736 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2010 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -/* DefinitionBlock Statement */ -#include -DefinitionBlock ( - "DSDT.AML", /* Output filename */ - "DSDT", /* Signature */ - 0x02, /* DSDT Revision, needs to be 2 for 64bit */ - OEM_ID, - ACPI_TABLE_CREATOR, - 0x00010001 /* OEM Revision */ - ) -{ /* Start of ASL file */ - /* #include */ /* Include global debug methods if needed */ - - /* Data to be patched by the BIOS during POST */ - /* FIXME the patching is not done yet! */ - /* Memory related values */ - Name(LOMH, 0x0) /* Start of unused memory in C0000-E0000 range */ - Name(PBAD, 0x0) /* Address of BIOS area (If TOM2 != 0, Addr >> 16) */ - Name(PBLN, 0x0) /* Length of BIOS area */ - - Name(PCBA, CONFIG_MMCONF_BASE_ADDRESS) /* Base address of PCIe config space */ - Name(HPBA, 0xFED00000) /* Base address of HPET table */ - - /* USB overcurrent mapping pins. */ - Name(UOM0, 0) - Name(UOM1, 2) - Name(UOM2, 0) - Name(UOM3, 7) - Name(UOM4, 2) - Name(UOM5, 2) - Name(UOM6, 6) - Name(UOM7, 2) - Name(UOM8, 6) - Name(UOM9, 6) - - /* Some global data */ - Name(OSVR, 3) /* Assume nothing. WinXp = 1, Vista = 2, Linux = 3, WinCE = 4 */ - Name(OSV, Ones) /* Assume nothing */ - Name(PMOD, One) /* Assume APIC */ - - /* - * Processor Object - * - */ - Scope (\_PR) { /* define processor scope */ - Device (CPU0) { - Name (_HID, "ACPI0007") - Name (_UID, 0) - #include "acpi/cpstate.asl" - } - Device (CPU1) { - Name (_HID, "ACPI0007") - Name (_UID, 1) - #include "acpi/cpstate.asl" - } - Device (CPU2) { - Name (_HID, "ACPI0007") - Name (_UID, 2) - #include "acpi/cpstate.asl" - } - Device (CPU3) { - Name (_HID, "ACPI0007") - Name (_UID, 3) - #include "acpi/cpstate.asl" - } - } /* End _PR scope */ - - /* PIC IRQ mapping registers, C00h-C01h */ - OperationRegion(PRQM, SystemIO, 0x00000C00, 0x00000002) - Field(PRQM, ByteAcc, NoLock, Preserve) { - PRQI, 0x00000008, - PRQD, 0x00000008, /* Offset: 1h */ - } - IndexField(PRQI, PRQD, ByteAcc, NoLock, Preserve) { - PINA, 0x00000008, /* Index 0 */ - PINB, 0x00000008, /* Index 1 */ - PINC, 0x00000008, /* Index 2 */ - PIND, 0x00000008, /* Index 3 */ - AINT, 0x00000008, /* Index 4 */ - SINT, 0x00000008, /* Index 5 */ - , 0x00000008, /* Index 6 */ - AAUD, 0x00000008, /* Index 7 */ - AMOD, 0x00000008, /* Index 8 */ - PINE, 0x00000008, /* Index 9 */ - PINF, 0x00000008, /* Index A */ - PING, 0x00000008, /* Index B */ - PINH, 0x00000008, /* Index C */ - } - - /* PCI Error control register */ - OperationRegion(PERC, SystemIO, 0x00000C14, 0x00000001) - Field(PERC, ByteAcc, NoLock, Preserve) { - SENS, 0x00000001, - PENS, 0x00000001, - SENE, 0x00000001, - PENE, 0x00000001, - } - - /* Client Management index/data registers */ - OperationRegion(CMT, SystemIO, 0x00000C50, 0x00000002) - Field(CMT, ByteAcc, NoLock, Preserve) { - CMTI, 8, - /* Client Management Data register */ - G64E, 1, - G64O, 1, - G32O, 2, - , 2, - GPSL, 2, - } - - /* GPM Port register */ - OperationRegion(GPT, SystemIO, 0x00000C52, 0x00000001) - Field(GPT, ByteAcc, NoLock, Preserve) { - GPB0,1, - GPB1,1, - GPB2,1, - GPB3,1, - GPB4,1, - GPB5,1, - GPB6,1, - GPB7,1, - } - - /* Flash ROM program enable register */ - OperationRegion(FRE, SystemIO, 0x00000C6F, 0x00000001) - Field(FRE, ByteAcc, NoLock, Preserve) { - , 0x00000006, - FLRE, 0x00000001, - } - - /* PM2 index/data registers */ - OperationRegion(PM2R, SystemIO, 0x00000CD0, 0x00000002) - Field(PM2R, ByteAcc, NoLock, Preserve) { - PM2I, 0x00000008, - PM2D, 0x00000008, - } - - /* Power Management I/O registers */ - OperationRegion(PIOR, SystemIO, 0x00000CD6, 0x00000002) - Field(PIOR, ByteAcc, NoLock, Preserve) { - PIOI, 0x00000008, - PIOD, 0x00000008, - } - IndexField (PIOI, PIOD, ByteAcc, NoLock, Preserve) { - Offset(0x00), /* MiscControl */ - , 1, - T1EE, 1, - T2EE, 1, - Offset(0x01), /* MiscStatus */ - , 1, - T1E, 1, - T2E, 1, - Offset(0x04), /* SmiWakeUpEventEnable3 */ - , 7, - SSEN, 1, - Offset(0x07), /* SmiWakeUpEventStatus3 */ - , 7, - CSSM, 1, - Offset(0x10), /* AcpiEnable */ - , 6, - PWDE, 1, - Offset(0x1C), /* ProgramIoEnable */ - , 3, - MKME, 1, - IO3E, 1, - IO2E, 1, - IO1E, 1, - IO0E, 1, - Offset(0x1D), /* IOMonitorStatus */ - , 3, - MKMS, 1, - IO3S, 1, - IO2S, 1, - IO1S, 1, - IO0S,1, - Offset(0x20), /* AcpiPmEvtBlk */ - APEB, 16, - Offset(0x36), /* GEvtLevelConfig */ - , 6, - ELC6, 1, - ELC7, 1, - Offset(0x37), /* GPMLevelConfig0 */ - , 3, - PLC0, 1, - PLC1, 1, - PLC2, 1, - PLC3, 1, - PLC8, 1, - Offset(0x38), /* GPMLevelConfig1 */ - , 1, - PLC4, 1, - PLC5, 1, - , 1, - PLC6, 1, - PLC7, 1, - Offset(0x3B), /* PMEStatus1 */ - GP0S, 1, - GM4S, 1, - GM5S, 1, - APS, 1, - GM6S, 1, - GM7S, 1, - GP2S, 1, - STSS, 1, - Offset(0x55), /* SoftPciRst */ - SPRE, 1, - , 1, - , 1, - PNAT, 1, - PWMK, 1, - PWNS, 1, - - /* Offset(0x61), */ /* Options_1 */ - /* ,7, */ - /* R617,1, */ - - Offset(0x65), /* UsbPMControl */ - , 4, - URRE, 1, - Offset(0x68), /* MiscEnable68 */ - , 3, - TMTE, 1, - , 1, - Offset(0x92), /* GEVENTIN */ - , 7, - E7IS, 1, - Offset(0x96), /* GPM98IN */ - G8IS, 1, - G9IS, 1, - Offset(0x9A), /* EnhanceControl */ - ,7, - HPDE, 1, - Offset(0xA8), /* PIO7654Enable */ - IO4E, 1, - IO5E, 1, - IO6E, 1, - IO7E, 1, - Offset(0xA9), /* PIO7654Status */ - IO4S, 1, - IO5S, 1, - IO6S, 1, - IO7S, 1, - } - - /* PM1 Event Block - * First word is PM1_Status, Second word is PM1_Enable - */ - OperationRegion(P1EB, SystemIO, APEB, 0x04) - Field(P1EB, ByteAcc, NoLock, Preserve) { - TMST, 1, - , 3, - BMST, 1, - GBST, 1, - Offset(0x01), - PBST, 1, - , 1, - RTST, 1, - , 3, - PWST, 1, - SPWS, 1, - Offset(0x02), - TMEN, 1, - , 4, - GBEN, 1, - Offset(0x03), - PBEN, 1, - , 1, - RTEN, 1, - , 3, - PWDA, 1, - } - - Scope(\_SB) { - /* PCIe Configuration Space for 16 busses */ - OperationRegion(PCFG, SystemMemory, PCBA, 0x01000000) /* Each bus consumes 1MB */ - Field(PCFG, ByteAcc, NoLock, Preserve) { - /* Byte offsets are computed using the following technique: - * ((bus number + 1) * ((device number * 8) * 4096)) + register offset - * The 8 comes from 8 functions per device, and 4096 bytes per function config space - */ - Offset(0x00088024), /* Byte offset to SATA register 24h - Bus 0, Device 17, Function 0 */ - STB5, 32, - Offset(0x00098042), /* Byte offset to OHCI0 register 42h - Bus 0, Device 19, Function 0 */ - PT0D, 1, - PT1D, 1, - PT2D, 1, - PT3D, 1, - PT4D, 1, - PT5D, 1, - PT6D, 1, - PT7D, 1, - PT8D, 1, - PT9D, 1, - Offset(0x000A0004), /* Byte offset to SMBUS register 4h - Bus 0, Device 20, Function 0 */ - SBIE, 1, - SBME, 1, - Offset(0x000A0008), /* Byte offset to SMBUS register 8h - Bus 0, Device 20, Function 0 */ - SBRI, 8, - Offset(0x000A0014), /* Byte offset to SMBUS register 14h - Bus 0, Device 20, Function 0 */ - SBB1, 32, - Offset(0x000A0078), /* Byte offset to SMBUS register 78h - Bus 0, Device 20, Function 0 */ - ,14, - P92E, 1, /* Port92 decode enable */ - } - - OperationRegion(SB5, SystemMemory, STB5, 0x1000) - Field(SB5, AnyAcc, NoLock, Preserve){ - /* Port 0 */ - Offset(0x120), /* Port 0 Task file status */ - P0ER, 1, - , 2, - P0DQ, 1, - , 3, - P0BY, 1, - Offset(0x128), /* Port 0 Serial ATA status */ - P0DD, 4, - , 4, - P0IS, 4, - Offset(0x12C), /* Port 0 Serial ATA control */ - P0DI, 4, - Offset(0x130), /* Port 0 Serial ATA error */ - , 16, - P0PR, 1, - - /* Port 1 */ - offset(0x1A0), /* Port 1 Task file status */ - P1ER, 1, - , 2, - P1DQ, 1, - , 3, - P1BY, 1, - Offset(0x1A8), /* Port 1 Serial ATA status */ - P1DD, 4, - , 4, - P1IS, 4, - Offset(0x1AC), /* Port 1 Serial ATA control */ - P1DI, 4, - Offset(0x1B0), /* Port 1 Serial ATA error */ - , 16, - P1PR, 1, - - /* Port 2 */ - Offset(0x220), /* Port 2 Task file status */ - P2ER, 1, - , 2, - P2DQ, 1, - , 3, - P2BY, 1, - Offset(0x228), /* Port 2 Serial ATA status */ - P2DD, 4, - , 4, - P2IS, 4, - Offset(0x22C), /* Port 2 Serial ATA control */ - P2DI, 4, - Offset(0x230), /* Port 2 Serial ATA error */ - , 16, - P2PR, 1, - - /* Port 3 */ - Offset(0x2A0), /* Port 3 Task file status */ - P3ER, 1, - , 2, - P3DQ, 1, - , 3, - P3BY, 1, - Offset(0x2A8), /* Port 3 Serial ATA status */ - P3DD, 4, - , 4, - P3IS, 4, - Offset(0x2AC), /* Port 3 Serial ATA control */ - P3DI, 4, - Offset(0x2B0), /* Port 3 Serial ATA error */ - , 16, - P3PR, 1, - } - } - - - #include "acpi/routing.asl" - - Scope(\_SB) { - - Method(OSFL, 0){ - - if(LNotEqual(OSVR, Ones)) {Return(OSVR)} /* OS version was already detected */ - - if(CondRefOf(\_OSI)) - { - Store(1, OSVR) /* Assume some form of XP */ - if (\_OSI("Windows 2006")) /* Vista */ - { - Store(2, OSVR) - } - } else { - If(WCMP(\_OS,"Linux")) { - Store(3, OSVR) /* Linux */ - } Else { - Store(4, OSVR) /* Gotta be WinCE */ - } - } - Return(OSVR) - } - - Method(_PIC, 0x01, NotSerialized) - { - If (Arg0) - { - \_SB.CIRQ() - } - Store(Arg0, PMOD) - } - Method(CIRQ, 0x00, NotSerialized){ - Store(0, PINA) - Store(0, PINB) - Store(0, PINC) - Store(0, PIND) - Store(0, PINE) - Store(0, PINF) - Store(0, PING) - Store(0, PINH) - } - - Name(IRQB, ResourceTemplate(){ - IRQ(Level,ActiveLow,Shared){15} - }) - - Name(IRQP, ResourceTemplate(){ - IRQ(Level,ActiveLow,Exclusive){3, 4, 5, 7, 10, 11, 12, 15} - }) - - Name(PITF, ResourceTemplate(){ - IRQ(Level,ActiveLow,Exclusive){9} - }) - - Device(INTA) { - Name(_HID, EISAID("PNP0C0F")) - Name(_UID, 1) - - Method(_STA, 0) { - if (PINA) { - Return(0x0B) /* sata is invisible */ - } else { - Return(0x09) /* sata is disabled */ - } - } /* End Method(_SB.INTA._STA) */ - - Method(_DIS ,0) { - /* DBGO("\\_SB\\LNKA\\_DIS\n") */ - Store(0, PINA) - } /* End Method(_SB.INTA._DIS) */ - - Method(_PRS ,0) { - /* DBGO("\\_SB\\LNKA\\_PRS\n") */ - Return(IRQP) - } /* Method(_SB.INTA._PRS) */ - - Method(_CRS ,0) { - /* DBGO("\\_SB\\LNKA\\_CRS\n") */ - CreateWordField(IRQB, 0x1, IRQN) - ShiftLeft(1, PINA, IRQN) - Return(IRQB) - } /* Method(_SB.INTA._CRS) */ - - Method(_SRS, 1) { - /* DBGO("\\_SB\\LNKA\\_CRS\n") */ - CreateWordField(ARG0, 1, IRQM) - - /* Use lowest available IRQ */ - FindSetRightBit(IRQM, Local0) - if (Local0) { - Decrement(Local0) - } - Store(Local0, PINA) - } /* End Method(_SB.INTA._SRS) */ - } /* End Device(INTA) */ - - Device(INTB) { - Name(_HID, EISAID("PNP0C0F")) - Name(_UID, 2) - - Method(_STA, 0) { - if (PINB) { - Return(0x0B) /* sata is invisible */ - } else { - Return(0x09) /* sata is disabled */ - } - } /* End Method(_SB.INTB._STA) */ - - Method(_DIS ,0) { - /* DBGO("\\_SB\\LNKB\\_DIS\n") */ - Store(0, PINB) - } /* End Method(_SB.INTB._DIS) */ - - Method(_PRS ,0) { - /* DBGO("\\_SB\\LNKB\\_PRS\n") */ - Return(IRQP) - } /* Method(_SB.INTB._PRS) */ - - Method(_CRS ,0) { - /* DBGO("\\_SB\\LNKB\\_CRS\n") */ - CreateWordField(IRQB, 0x1, IRQN) - ShiftLeft(1, PINB, IRQN) - Return(IRQB) - } /* Method(_SB.INTB._CRS) */ - - Method(_SRS, 1) { - /* DBGO("\\_SB\\LNKB\\_CRS\n") */ - CreateWordField(ARG0, 1, IRQM) - - /* Use lowest available IRQ */ - FindSetRightBit(IRQM, Local0) - if (Local0) { - Decrement(Local0) - } - Store(Local0, PINB) - } /* End Method(_SB.INTB._SRS) */ - } /* End Device(INTB) */ - - Device(INTC) { - Name(_HID, EISAID("PNP0C0F")) - Name(_UID, 3) - - Method(_STA, 0) { - if (PINC) { - Return(0x0B) /* sata is invisible */ - } else { - Return(0x09) /* sata is disabled */ - } - } /* End Method(_SB.INTC._STA) */ - - Method(_DIS ,0) { - /* DBGO("\\_SB\\LNKC\\_DIS\n") */ - Store(0, PINC) - } /* End Method(_SB.INTC._DIS) */ - - Method(_PRS ,0) { - /* DBGO("\\_SB\\LNKC\\_PRS\n") */ - Return(IRQP) - } /* Method(_SB.INTC._PRS) */ - - Method(_CRS ,0) { - /* DBGO("\\_SB\\LNKC\\_CRS\n") */ - CreateWordField(IRQB, 0x1, IRQN) - ShiftLeft(1, PINC, IRQN) - Return(IRQB) - } /* Method(_SB.INTC._CRS) */ - - Method(_SRS, 1) { - /* DBGO("\\_SB\\LNKC\\_CRS\n") */ - CreateWordField(ARG0, 1, IRQM) - - /* Use lowest available IRQ */ - FindSetRightBit(IRQM, Local0) - if (Local0) { - Decrement(Local0) - } - Store(Local0, PINC) - } /* End Method(_SB.INTC._SRS) */ - } /* End Device(INTC) */ - - Device(INTD) { - Name(_HID, EISAID("PNP0C0F")) - Name(_UID, 4) - - Method(_STA, 0) { - if (PIND) { - Return(0x0B) /* sata is invisible */ - } else { - Return(0x09) /* sata is disabled */ - } - } /* End Method(_SB.INTD._STA) */ - - Method(_DIS ,0) { - /* DBGO("\\_SB\\LNKD\\_DIS\n") */ - Store(0, PIND) - } /* End Method(_SB.INTD._DIS) */ - - Method(_PRS ,0) { - /* DBGO("\\_SB\\LNKD\\_PRS\n") */ - Return(IRQP) - } /* Method(_SB.INTD._PRS) */ - - Method(_CRS ,0) { - /* DBGO("\\_SB\\LNKD\\_CRS\n") */ - CreateWordField(IRQB, 0x1, IRQN) - ShiftLeft(1, PIND, IRQN) - Return(IRQB) - } /* Method(_SB.INTD._CRS) */ - - Method(_SRS, 1) { - /* DBGO("\\_SB\\LNKD\\_CRS\n") */ - CreateWordField(ARG0, 1, IRQM) - - /* Use lowest available IRQ */ - FindSetRightBit(IRQM, Local0) - if (Local0) { - Decrement(Local0) - } - Store(Local0, PIND) - } /* End Method(_SB.INTD._SRS) */ - } /* End Device(INTD) */ - - Device(INTE) { - Name(_HID, EISAID("PNP0C0F")) - Name(_UID, 5) - - Method(_STA, 0) { - if (PINE) { - Return(0x0B) /* sata is invisible */ - } else { - Return(0x09) /* sata is disabled */ - } - } /* End Method(_SB.INTE._STA) */ - - Method(_DIS ,0) { - /* DBGO("\\_SB\\LNKE\\_DIS\n") */ - Store(0, PINE) - } /* End Method(_SB.INTE._DIS) */ - - Method(_PRS ,0) { - /* DBGO("\\_SB\\LNKE\\_PRS\n") */ - Return(IRQP) - } /* Method(_SB.INTE._PRS) */ - - Method(_CRS ,0) { - /* DBGO("\\_SB\\LNKE\\_CRS\n") */ - CreateWordField(IRQB, 0x1, IRQN) - ShiftLeft(1, PINE, IRQN) - Return(IRQB) - } /* Method(_SB.INTE._CRS) */ - - Method(_SRS, 1) { - /* DBGO("\\_SB\\LNKE\\_CRS\n") */ - CreateWordField(ARG0, 1, IRQM) - - /* Use lowest available IRQ */ - FindSetRightBit(IRQM, Local0) - if (Local0) { - Decrement(Local0) - } - Store(Local0, PINE) - } /* End Method(_SB.INTE._SRS) */ - } /* End Device(INTE) */ - - Device(INTF) { - Name(_HID, EISAID("PNP0C0F")) - Name(_UID, 6) - - Method(_STA, 0) { - if (PINF) { - Return(0x0B) /* sata is invisible */ - } else { - Return(0x09) /* sata is disabled */ - } - } /* End Method(_SB.INTF._STA) */ - - Method(_DIS ,0) { - /* DBGO("\\_SB\\LNKF\\_DIS\n") */ - Store(0, PINF) - } /* End Method(_SB.INTF._DIS) */ - - Method(_PRS ,0) { - /* DBGO("\\_SB\\LNKF\\_PRS\n") */ - Return(PITF) - } /* Method(_SB.INTF._PRS) */ - - Method(_CRS ,0) { - /* DBGO("\\_SB\\LNKF\\_CRS\n") */ - CreateWordField(IRQB, 0x1, IRQN) - ShiftLeft(1, PINF, IRQN) - Return(IRQB) - } /* Method(_SB.INTF._CRS) */ - - Method(_SRS, 1) { - /* DBGO("\\_SB\\LNKF\\_CRS\n") */ - CreateWordField(ARG0, 1, IRQM) - - /* Use lowest available IRQ */ - FindSetRightBit(IRQM, Local0) - if (Local0) { - Decrement(Local0) - } - Store(Local0, PINF) - } /* End Method(_SB.INTF._SRS) */ - } /* End Device(INTF) */ - - Device(INTG) { - Name(_HID, EISAID("PNP0C0F")) - Name(_UID, 7) - - Method(_STA, 0) { - if (PING) { - Return(0x0B) /* sata is invisible */ - } else { - Return(0x09) /* sata is disabled */ - } - } /* End Method(_SB.INTG._STA) */ - - Method(_DIS ,0) { - /* DBGO("\\_SB\\LNKG\\_DIS\n") */ - Store(0, PING) - } /* End Method(_SB.INTG._DIS) */ - - Method(_PRS ,0) { - /* DBGO("\\_SB\\LNKG\\_PRS\n") */ - Return(IRQP) - } /* Method(_SB.INTG._CRS) */ - - Method(_CRS ,0) { - /* DBGO("\\_SB\\LNKG\\_CRS\n") */ - CreateWordField(IRQB, 0x1, IRQN) - ShiftLeft(1, PING, IRQN) - Return(IRQB) - } /* Method(_SB.INTG._CRS) */ - - Method(_SRS, 1) { - /* DBGO("\\_SB\\LNKG\\_CRS\n") */ - CreateWordField(ARG0, 1, IRQM) - - /* Use lowest available IRQ */ - FindSetRightBit(IRQM, Local0) - if (Local0) { - Decrement(Local0) - } - Store(Local0, PING) - } /* End Method(_SB.INTG._SRS) */ - } /* End Device(INTG) */ - - Device(INTH) { - Name(_HID, EISAID("PNP0C0F")) - Name(_UID, 8) - - Method(_STA, 0) { - if (PINH) { - Return(0x0B) /* sata is invisible */ - } else { - Return(0x09) /* sata is disabled */ - } - } /* End Method(_SB.INTH._STA) */ - - Method(_DIS ,0) { - /* DBGO("\\_SB\\LNKH\\_DIS\n") */ - Store(0, PINH) - } /* End Method(_SB.INTH._DIS) */ - - Method(_PRS ,0) { - /* DBGO("\\_SB\\LNKH\\_PRS\n") */ - Return(IRQP) - } /* Method(_SB.INTH._CRS) */ - - Method(_CRS ,0) { - /* DBGO("\\_SB\\LNKH\\_CRS\n") */ - CreateWordField(IRQB, 0x1, IRQN) - ShiftLeft(1, PINH, IRQN) - Return(IRQB) - } /* Method(_SB.INTH._CRS) */ - - Method(_SRS, 1) { - /* DBGO("\\_SB\\LNKH\\_CRS\n") */ - CreateWordField(ARG0, 1, IRQM) - - /* Use lowest available IRQ */ - FindSetRightBit(IRQM, Local0) - if (Local0) { - Decrement(Local0) - } - Store(Local0, PINH) - } /* End Method(_SB.INTH._SRS) */ - } /* End Device(INTH) */ - - } /* End Scope(_SB) */ - - #include - - /* Wake status package */ - Name(WKST,Package(){Zero, Zero}) - - /* - * \_PTS - Prepare to Sleep method - * - * Entry: - * Arg0=The value of the sleeping state S1=1, S2=2, etc - * - * Exit: - * -none- - * - * The _PTS control method is executed at the beginning of the sleep process - * for S1-S5. The sleeping value is passed to the _PTS control method. This - * control method may be executed a relatively long time before entering the - * sleep state and the OS may abort the operation without notification to - * the ACPI driver. This method cannot modify the configuration or power - * state of any device in the system. - */ - Method(\_PTS, 1) { - /* DBGO("\\_PTS\n") */ - /* DBGO("From S0 to S") */ - /* DBGO(Arg0) */ - /* DBGO("\n") */ - - /* Don't allow PCIRST# to reset USB */ - if (LEqual(Arg0,3)){ - Store(0,URRE) - } - - /* Clear sleep SMI status flag and enable sleep SMI trap. */ - /*Store(One, CSSM) - Store(One, SSEN)*/ - - /* On older chips, clear PciExpWakeDisEn */ - /*if (LLessEqual(\_SB.SBRI, 0x13)) { - * Store(0,\_SB.PWDE) - *} - */ - - /* Clear wake status structure. */ - Store(0, Index(WKST,0)) - Store(0, Index(WKST,1)) - \_SB.PCI0.SIOS (Arg0) - } /* End Method(\_PTS) */ - - /* - * The following method results in a "not a valid reserved NameSeg" - * warning so I have commented it out for the duration. It isn't - * used, so it could be removed. - * - * - * \_GTS OEM Going To Sleep method - * - * Entry: - * Arg0=The value of the sleeping state S1=1, S2=2 - * - * Exit: - * -none- - * - * Method(\_GTS, 1) { - * DBGO("\\_GTS\n") - * DBGO("From S0 to S") - * DBGO(Arg0) - * DBGO("\n") - * } - */ - - /* - * \_BFS OEM Back From Sleep method - * - * Entry: - * Arg0=The value of the sleeping state S1=1, S2=2 - * - * Exit: - * -none- - */ - Method(\_BFS, 1) { - /* DBGO("\\_BFS\n") */ - /* DBGO("From S") */ - /* DBGO(Arg0) */ - /* DBGO(" to S0\n") */ - } - - /* - * \_WAK System Wake method - * - * Entry: - * Arg0=The value of the sleeping state S1=1, S2=2 - * - * Exit: - * Return package of 2 DWords - * Dword 1 - Status - * 0x00000000 wake succeeded - * 0x00000001 Wake was signaled but failed due to lack of power - * 0x00000002 Wake was signaled but failed due to thermal condition - * Dword 2 - Power Supply state - * if non-zero the effective S-state the power supply entered - */ - Method(\_WAK, 1) { - /* DBGO("\\_WAK\n") */ - /* DBGO("From S") */ - /* DBGO(Arg0) */ - /* DBGO(" to S0\n") */ - - /* Re-enable HPET */ - Store(1,HPDE) - - /* Restore PCIRST# so it resets USB */ - if (LEqual(Arg0,3)){ - Store(1,URRE) - } - - /* Arbitrarily clear PciExpWakeStatus */ - Store(PWST, Local1) - Store(Local1, PWST) - - /* if (DeRefOf(Index(WKST,0))) { - * Store(0, Index(WKST,1)) - * } else { - * Store(Arg0, Index(WKST,1)) - * } - */ - \_SB.PCI0.SIOW () - Return(WKST) - } /* End Method(\_WAK) */ - - Scope(\_GPE) { /* Start Scope GPE */ - /* General event 0 */ - /* Method(_L00) { - * DBGO("\\_GPE\\_L00\n") - * } - */ - - /* General event 1 */ - /* Method(_L01) { - * DBGO("\\_GPE\\_L00\n") - * } - */ - - /* General event 2 */ - /* Method(_L02) { - * DBGO("\\_GPE\\_L00\n") - * } - */ - - /* General event 3 */ - Method(_L03) { - /* DBGO("\\_GPE\\_L00\n") */ - Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ - } - - /* General event 4 */ - /* Method(_L04) { - * DBGO("\\_GPE\\_L00\n") - * } - */ - - /* General event 5 */ - /* Method(_L05) { - * DBGO("\\_GPE\\_L00\n") - * } - */ - - /* General event 6 - Used for GPM6, moved to USB.asl */ - /* Method(_L06) { - * DBGO("\\_GPE\\_L00\n") - * } - */ - - /* General event 7 - Used for GPM7, moved to USB.asl */ - /* Method(_L07) { - * DBGO("\\_GPE\\_L07\n") - * } - */ - - /* Legacy PM event */ - Method(_L08) { - /* DBGO("\\_GPE\\_L08\n") */ - } - - /* Temp warning (TWarn) event */ - Method(_L09) { - /* DBGO("\\_GPE\\_L09\n") */ - Notify (\_TZ.TZ00, 0x80) - } - - /* Reserved */ - /* Method(_L0A) { - * DBGO("\\_GPE\\_L0A\n") - * } - */ - - /* USB controller PME# */ - Method(_L0B) { - /* DBGO("\\_GPE\\_L0B\n") */ - Notify(\_SB.PCI0.UOH1, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(\_SB.PCI0.UOH2, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(\_SB.PCI0.UOH3, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(\_SB.PCI0.UOH4, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(\_SB.PCI0.UOH5, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(\_SB.PCI0.UEH1, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ - } - - /* AC97 controller PME# */ - /* Method(_L0C) { - * DBGO("\\_GPE\\_L0C\n") - * } - */ - - /* OtherTherm PME# */ - /* Method(_L0D) { - * DBGO("\\_GPE\\_L0D\n") - * } - */ - - /* GPM9 SCI event - Moved to USB.asl */ - /* Method(_L0E) { - * DBGO("\\_GPE\\_L0E\n") - * } - */ - - /* PCIe HotPlug event */ - /* Method(_L0F) { - * DBGO("\\_GPE\\_L0F\n") - * } - */ - - /* ExtEvent0 SCI event */ - Method(_L10) { - /* DBGO("\\_GPE\\_L10\n") */ - } - - - /* ExtEvent1 SCI event */ - Method(_L11) { - /* DBGO("\\_GPE\\_L11\n") */ - } - - /* PCIe PME# event */ - /* Method(_L12) { - * DBGO("\\_GPE\\_L12\n") - * } - */ - - /* GPM0 SCI event - Moved to USB.asl */ - /* Method(_L13) { - * DBGO("\\_GPE\\_L13\n") - * } - */ - - /* GPM1 SCI event - Moved to USB.asl */ - /* Method(_L14) { - * DBGO("\\_GPE\\_L14\n") - * } - */ - - /* GPM2 SCI event - Moved to USB.asl */ - /* Method(_L15) { - * DBGO("\\_GPE\\_L15\n") - * } - */ - - /* GPM3 SCI event - Moved to USB.asl */ - /* Method(_L16) { - * DBGO("\\_GPE\\_L16\n") - * } - */ - - /* GPM8 SCI event - Moved to USB.asl */ - /* Method(_L17) { - * DBGO("\\_GPE\\_L17\n") - * } - */ - - /* GPIO0 or GEvent8 event */ - Method(_L18) { - /* DBGO("\\_GPE\\_L18\n") */ - Notify(\_SB.PCI0.PBR2, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(\_SB.PCI0.PBR4, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(\_SB.PCI0.PBR5, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(\_SB.PCI0.PBR6, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(\_SB.PCI0.PBR7, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ - } - - /* GPM4 SCI event - Moved to USB.asl */ - /* Method(_L19) { - * DBGO("\\_GPE\\_L19\n") - * } - */ - - /* GPM5 SCI event - Moved to USB.asl */ - /* Method(_L1A) { - * DBGO("\\_GPE\\_L1A\n") - * } - */ - - /* Azalia SCI event */ - Method(_L1B) { - /* DBGO("\\_GPE\\_L1B\n") */ - Notify(\_SB.PCI0.AZHD, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ - } - - /* GPM6 SCI event - Reassigned to _L06 */ - /* Method(_L1C) { - * DBGO("\\_GPE\\_L1C\n") - * } - */ - - /* GPM7 SCI event - Reassigned to _L07 */ - /* Method(_L1D) { - * DBGO("\\_GPE\\_L1D\n") - * } - */ - - /* GPIO2 or GPIO66 SCI event */ - /* Method(_L1E) { - * DBGO("\\_GPE\\_L1E\n") - * } - */ - - /* SATA SCI event - Moved to sata.asl */ - /* Method(_L1F) { - * DBGO("\\_GPE\\_L1F\n") - * } - */ - - } /* End Scope GPE */ - - #include "acpi/usb.asl" - - /* System Bus */ - Scope(\_SB) { /* Start \_SB scope */ - #include /* global utility methods expected within the \_SB scope */ - - /* _SB.PCI0 */ - /* Note: Only need HID on Primary Bus */ - Device(PCI0) { - External (TOM1) - External (TOM2) - Name(_HID, EISAID("PNP0A03")) - Name(_ADR, 0x00180000) /* Dev# = BSP Dev#, Func# = 0 */ - Method(_BBN, 0) { /* Bus number = 0 */ - Return(0) - } - Method(_STA, 0) { - /* DBGO("\\_SB\\PCI0\\_STA\n") */ - Return(0x0B) /* Status is visible */ - } - - Method(_PRT,0) { - If(PMOD){ Return(APR0) } /* APIC mode */ - Return (PR0) /* PIC Mode */ - } /* end _PRT */ - - /* Describe the Northbridge devices */ - Device(AMRT) { - Name(_ADR, 0x00000000) - } /* end AMRT */ - - /* The internal GFX bridge */ - Device(AGPB) { - Name(_ADR, 0x00010000) - Name(_PRW, Package() {0x18, 4}) - Method(_PRT,0) { - Return (APR1) - } - } /* end AGPB */ - - /* The external GFX bridge */ - Device(PBR2) { - Name(_ADR, 0x00020000) - Name(_PRW, Package() {0x18, 4}) - Method(_PRT,0) { - If(PMOD){ Return(APS2) } /* APIC mode */ - Return (PS2) /* PIC Mode */ - } /* end _PRT */ - } /* end PBR2 */ - - /* Dev3 is also an external GFX bridge, not used in Herring */ - - Device(PBR4) { - Name(_ADR, 0x00040000) - Name(_PRW, Package() {0x18, 4}) - Method(_PRT,0) { - If(PMOD){ Return(APS4) } /* APIC mode */ - Return (PS4) /* PIC Mode */ - } /* end _PRT */ - } /* end PBR4 */ - - Device(PBR5) { - Name(_ADR, 0x00050000) - Name(_PRW, Package() {0x18, 4}) - Method(_PRT,0) { - If(PMOD){ Return(APS5) } /* APIC mode */ - Return (PS5) /* PIC Mode */ - } /* end _PRT */ - } /* end PBR5 */ - - Device(PBR6) { - Name(_ADR, 0x00060000) - Name(_PRW, Package() {0x18, 4}) - Method(_PRT,0) { - If(PMOD){ Return(APS6) } /* APIC mode */ - Return (PS6) /* PIC Mode */ - } /* end _PRT */ - } /* end PBR6 */ - - /* The onboard EtherNet chip */ - Device(PBR7) { - Name(_ADR, 0x00070000) - Name(_PRW, Package() {0x18, 4}) - Method(_PRT,0) { - If(PMOD){ Return(APS7) } /* APIC mode */ - Return (PS7) /* PIC Mode */ - } /* end _PRT */ - } /* end PBR7 */ - - /* GPP */ - Device(PBR9) { - Name(_ADR, 0x00090000) - Name(_PRW, Package() {0x18, 4}) - Method(_PRT,0) { - If(PMOD){ Return(APS9) } /* APIC mode */ - Return (PS9) /* PIC Mode */ - } /* end _PRT */ - } /* end PBR9 */ - - Device(PBRa) { - Name(_ADR, 0x000A0000) - Name(_PRW, Package() {0x18, 4}) - Method(_PRT,0) { - If(PMOD){ Return(APSa) } /* APIC mode */ - Return (PSa) /* PIC Mode */ - } /* end _PRT */ - } /* end PBRa */ - - - /* PCI slot 1, 2, 3 */ - Device(PIBR) { - Name(_ADR, 0x00140004) - Name(_PRW, Package() {0x18, 4}) - - Method(_PRT, 0) { - Return (PCIB) - } - } - - /* Describe the Southbridge devices */ - Device(STCR) { - Name(_ADR, 0x00110000) - #include "acpi/sata.asl" - } /* end STCR */ - - Device(UOH1) { - Name(_ADR, 0x00130000) - Name(_PRW, Package() {0x0B, 3}) - } /* end UOH1 */ - - Device(UOH2) { - Name(_ADR, 0x00130001) - Name(_PRW, Package() {0x0B, 3}) - } /* end UOH2 */ - - Device(UOH3) { - Name(_ADR, 0x00130002) - Name(_PRW, Package() {0x0B, 3}) - } /* end UOH3 */ - - Device(UOH4) { - Name(_ADR, 0x00130003) - Name(_PRW, Package() {0x0B, 3}) - } /* end UOH4 */ - - Device(UOH5) { - Name(_ADR, 0x00130004) - Name(_PRW, Package() {0x0B, 3}) - } /* end UOH5 */ - - Device(UEH1) { - Name(_ADR, 0x00130005) - Name(_PRW, Package() {0x0B, 3}) - } /* end UEH1 */ - - Device(SBUS) { - Name(_ADR, 0x00140000) - } /* end SBUS */ - - /* Primary (and only) IDE channel */ - Device(IDEC) { - Name(_ADR, 0x00140001) - #include "acpi/ide.asl" - } /* end IDEC */ - - Device(AZHD) { - Name(_ADR, 0x00140002) - OperationRegion(AZPD, PCI_Config, 0x00, 0x100) - Field(AZPD, AnyAcc, NoLock, Preserve) { - offset (0x42), - NSDI, 1, - NSDO, 1, - NSEN, 1, - offset (0x44), - IPCR, 4, - offset (0x54), - PWST, 2, - , 6, - PMEB, 1, - , 6, - PMST, 1, - offset (0x62), - MMCR, 1, - offset (0x64), - MMLA, 32, - offset (0x68), - MMHA, 32, - offset (0x6C), - MMDT, 16, - } - - Method(_INI) { - If(LEqual(OSVR,3)){ /* If we are running Linux */ - Store(zero, NSEN) - Store(one, NSDO) - Store(one, NSDI) - } - } - } /* end AZHD */ - - Device(LIBR) { - Name(_ADR, 0x00140003) - /* Method(_INI) { - * DBGO("\\_SB\\PCI0\\LpcIsaBr\\_INI\n") - } */ /* End Method(_SB.SBRDG._INI) */ - - /* Real Time Clock Device */ - Device(RTC0) { - Name(_HID, EISAID("PNP0B00")) /* AT Real Time Clock (not PIIX4 compatible) */ - Name(_CRS, ResourceTemplate() { - IRQNoFlags(){8} - IO(Decode16,0x0070, 0x0070, 0, 2) - /* IO(Decode16,0x0070, 0x0070, 0, 4) */ - }) - } /* End Device(_SB.PCI0.LpcIsaBr.RTC0) */ - - Device(TMR) { /* Timer */ - Name(_HID,EISAID("PNP0100")) /* System Timer */ - Name(_CRS, ResourceTemplate() { - IRQNoFlags(){0} - IO(Decode16, 0x0040, 0x0040, 0, 4) - /* IO(Decode16, 0x0048, 0x0048, 0, 4) */ - }) - } /* End Device(_SB.PCI0.LpcIsaBr.TMR) */ - - Device(SPKR) { /* Speaker */ - Name(_HID,EISAID("PNP0800")) /* AT style speaker */ - Name(_CRS, ResourceTemplate() { - IO(Decode16, 0x0061, 0x0061, 0, 1) - }) - } /* End Device(_SB.PCI0.LpcIsaBr.SPKR) */ - - Device(PIC) { - Name(_HID,EISAID("PNP0000")) /* AT Interrupt Controller */ - Name(_CRS, ResourceTemplate() { - IRQNoFlags(){2} - IO(Decode16,0x0020, 0x0020, 0, 2) - IO(Decode16,0x00A0, 0x00A0, 0, 2) - /* IO(Decode16, 0x00D0, 0x00D0, 0x10, 0x02) */ - /* IO(Decode16, 0x04D0, 0x04D0, 0x10, 0x02) */ - }) - } /* End Device(_SB.PCI0.LpcIsaBr.PIC) */ - - Device(MAD) { /* 8257 DMA */ - Name(_HID,EISAID("PNP0200")) /* Hardware Device ID */ - Name(_CRS, ResourceTemplate() { - DMA(Compatibility,BusMaster,Transfer8){4} - IO(Decode16, 0x0000, 0x0000, 0x10, 0x10) - IO(Decode16, 0x0081, 0x0081, 0x01, 0x03) - IO(Decode16, 0x0087, 0x0087, 0x01, 0x01) - IO(Decode16, 0x0089, 0x0089, 0x01, 0x03) - IO(Decode16, 0x008F, 0x008F, 0x01, 0x01) - IO(Decode16, 0x00C0, 0x00C0, 0x10, 0x20) - }) /* End Name(_SB.PCI0.LpcIsaBr.MAD._CRS) */ - } /* End Device(_SB.PCI0.LpcIsaBr.MAD) */ - - Device(COPR) { - Name(_HID,EISAID("PNP0C04")) /* Math Coprocessor */ - Name(_CRS, ResourceTemplate() { - IO(Decode16, 0x00F0, 0x00F0, 0, 0x10) - IRQNoFlags(){13} - }) - } /* End Device(_SB.PCI0.LpcIsaBr.COPR) */ -#if 0 /* defined by HPET table? */ - Device(HPTM) { - Name(_HID,EISAID("PNP0103")) - Name(CRS,ResourceTemplate() { - Memory32Fixed(ReadOnly,0xFED00000, 0x00000400, HPT) /* 1kb reserved space */ - }) - Method(_STA, 0) { - Return(0x0F) /* sata is visible */ - } - Method(_CRS, 0) { - CreateDwordField(CRS, ^HPT._BAS, HPBX) - Store(HPBA, HPBX) - Return(CRS) - } - } /* End Device(_SB.PCI0.LpcIsaBr.COPR) */ -#endif - } /* end LIBR */ - - Device(HPBR) { - Name(_ADR, 0x00140004) - } /* end HostPciBr */ - - Device(ACAD) { - Name(_ADR, 0x00140005) - } /* end Ac97audio */ - - Device(ACMD) { - Name(_ADR, 0x00140006) - } /* end Ac97modem */ - - /* f71859 Support */ - OperationRegion (IOID, SystemIO, 0x2E, 0x02) /* sometimes it is 0x4E */ - Field (IOID, ByteAcc, NoLock, Preserve) - { - SIOI, 8, SIOD, 8 /* 0x2E and 0x2F */ - } - - IndexField (SIOI, SIOD, ByteAcc, NoLock, Preserve) - { - Offset (0x07), - LDN, 8, /* Logical Device Number */ - Offset (0x20), - CID1, 8, /* Chip ID Byte 1, 0x87 */ - CID2, 8, /* Chip ID Byte 2, 0x12 */ - Offset (0x30), - ACTR, 8, /* Function activate */ - Offset (0xF0), - APC0, 8, /* APC/PME Event Enable Register */ - APC1, 8, /* APC/PME Status Register */ - APC2, 8, /* APC/PME Control Register 1 */ - APC3, 8, /* Environment Controller Special Configuration Register */ - APC4, 8 /* APC/PME Control Register 2 */ - } - - /* Enter the 8718 MB PnP Mode */ - Method (EPNP) - { - Store(0x87, SIOI) - Store(0x01, SIOI) - Store(0x55, SIOI) - Store(0x55, SIOI) /* 8718 magic number */ - } - /* Exit the 8718 MB PnP Mode */ - Method (XPNP) - { - Store (0x02, SIOI) - Store (0x02, SIOD) - } - /* - * Keyboard PME is routed to SB700 Gevent3. We can wake - * up the system by pressing the key. - */ - Method (SIOS, 1) - { - /* We only enable KBD PME for S5. */ - If (LLess (Arg0, 0x05)) - { - EPNP() - /* DBGO("8718F\n") */ - - Store (0x4, LDN) - Store (One, ACTR) /* Enable EC */ - /* - Store (0x4, LDN) - Store (0x04, APC4) - */ /* falling edge. which mode? Not sure. */ - - Store (0x4, LDN) - Store (0x08, APC1) /* clear PME status, Use 0x18 for mouse & KBD */ - Store (0x4, LDN) - Store (0x08, APC0) /* enable PME, Use 0x18 for mouse & KBD */ - - XPNP() - } - } - Method (SIOW, 0) - { - EPNP() - Store (0x4, LDN) - Store (Zero, APC0) /* disable keyboard PME */ - Store (0x4, LDN) - Store (0xFF, APC1) /* clear keyboard PME status */ - XPNP() - } - - Name(CRES, ResourceTemplate() { - IO(Decode16, 0x0CF8, 0x0CF8, 1, 8) - - WORDIO(ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, - 0x0000, /* address granularity */ - 0x0000, /* range minimum */ - 0x0CF7, /* range maximum */ - 0x0000, /* translation */ - 0x0CF8 /* length */ - ) - - WORDIO(ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, - 0x0000, /* address granularity */ - 0x0D00, /* range minimum */ - 0xFFFF, /* range maximum */ - 0x0000, /* translation */ - 0xF300 /* length */ - ) - - Memory32Fixed(READONLY, 0x000A0000, 0x00020000, VGAM) /* VGA memory space */ -#if 0 - Memory32Fixed(READWRITE, 0, 0xA0000, BSMM) - Memory32Fixed(READONLY, 0x000C0000, 0x00020000, EMM1) /* Assume C0000-E0000 empty */ - Memory32Fixed(READONLY, 0x000E0000, 0x00020000, RDBS) /* BIOS ROM area */ - - /* DRAM Memory from 1MB to TopMem */ - Memory32Fixed(READWRITE, 0x00100000, 0, DMLO) /* 1MB to TopMem */ - - /* BIOS space just below 4GB */ - DWORDMemory( - ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite, - 0x00, /* Granularity */ - 0x00000000, /* Min */ - 0x00000000, /* Max */ - 0x00000000, /* Translation */ - 0x00000001, /* Max-Min, RLEN */ - ,, - PCBM - ) - - /* DRAM memory from 4GB to TopMem2 */ - QWORDMemory(ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite, - 0x00000000, /* Granularity */ - 0x00000000, /* Min */ - 0x00000000, /* Max */ - 0x00000000, /* Translation */ - 0x00000001, /* Max-Min, RLEN */ - ,, - DMHI - ) - - /* BIOS space just below 16EB */ - QWORDMemory(ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite, - 0x00000000, /* Granularity */ - 0x00000000, /* Min */ - 0x00000000, /* Max */ - 0x00000000, /* Translation */ - 0x00000001, /* Max-Min, RLEN */ - ,, - PEBM - ) -#endif - /* memory space for PCI BARs below 4GB */ - Memory32Fixed(ReadOnly, 0x00000000, 0x00000000, MMIO) - }) /* End Name(_SB.PCI0.CRES) */ - - Method(_CRS, 0) { - /* DBGO("\\_SB\\PCI0\\_CRS\n") */ -#if 0 - CreateDWordField(CRES, ^EMM1._BAS, EM1B) - CreateDWordField(CRES, ^EMM1._LEN, EM1L) - CreateDWordField(CRES, ^DMLO._BAS, DMLB) - CreateDWordField(CRES, ^DMLO._LEN, DMLL) - CreateDWordField(CRES, ^PCBM._MIN, PBMB) - CreateDWordField(CRES, ^PCBM._LEN, PBML) - - CreateQWordField(CRES, ^DMHI._MIN, DMHB) - CreateQWordField(CRES, ^DMHI._LEN, DMHL) - CreateQWordField(CRES, ^PEBM._MIN, EBMB) - CreateQWordField(CRES, ^PEBM._LEN, EBML) - - If(LGreater(LOMH, 0xC0000)){ - Store(0xC0000, EM1B) /* Hole above C0000 and below E0000 */ - Subtract(LOMH, 0xC0000, EM1L) /* subtract start, assumes allocation from C0000 going up */ - } - - /* Set size of memory from 1MB to TopMem */ - Subtract(TOM1, 0x100000, DMLL) - - /* - * If(LNotEqual(TOM2, 0x00000000)){ - * Store(0x100000000,DMHB) DRAM from 4GB to TopMem2 - * Subtract(TOM2, 0x100000000, DMHL) - * } - */ - - /* If there is no memory above 4GB, put the BIOS just below 4GB */ - If(LEqual(TOM2, 0x00000000)){ - Store(PBAD,PBMB) /* Reserve the "BIOS" space */ - Store(PBLN,PBML) - } - Else { /* Otherwise, put the BIOS just below 16EB */ - ShiftLeft(PBAD,16,EBMB) /* Reserve the "BIOS" space */ - Store(PBLN,EBML) - } -#endif - CreateDWordField(CRES, ^MMIO._BAS, MM1B) - CreateDWordField(CRES, ^MMIO._LEN, MM1L) - /* - * Declare memory between TOM1 and 4GB as available - * for PCI MMIO. - * Use ShiftLeft to avoid 64bit constant (for XP). - * This will work even if the OS does 32bit arithmetic, as - * 32bit (0x00000000 - TOM1) will wrap and give the same - * result as 64bit (0x100000000 - TOM1). - */ - Store(TOM1, MM1B) - ShiftLeft(0x10000000, 4, Local0) - Subtract(Local0, TOM1, Local0) - Store(Local0, MM1L) - - Return(CRES) /* note to change the Name buffer */ - } /* end of Method(_SB.PCI0._CRS) */ - - /* - * - * FIRST METHOD CALLED UPON BOOT - * - * 1. If debugging, print current OS and ACPI interpreter. - * 2. Get PCI Interrupt routing from ACPI VSM, this - * value is based on user choice in BIOS setup. - */ - Method(_INI, 0) { - /* DBGO("\\_SB\\_INI\n") */ - /* DBGO(" DSDT.ASL code from ") */ - /* DBGO(__DATE__) */ - /* DBGO(" ") */ - /* DBGO(__TIME__) */ - /* DBGO("\n Sleep states supported: ") */ - /* DBGO("\n") */ - /* DBGO(" \\_OS=") */ - /* DBGO(\_OS) */ - /* DBGO("\n \\_REV=") */ - /* DBGO(\_REV) */ - /* DBGO("\n") */ - - /* Determine the OS we're running on */ - OSFL() - - /* On older chips, clear PciExpWakeDisEn */ - /*if (LLessEqual(\SBRI, 0x13)) { - * Store(0,\PWDE) - * } - */ - } /* End Method(_SB._INI) */ - } /* End Device(PCI0) */ - - Device(PWRB) { /* Start Power button device */ - Name(_HID, EISAID("PNP0C0C")) - Name(_UID, 0xAA) - Name(_PRW, Package () {3, 0x04}) /* wake from S1-S4 */ - Name(_STA, 0x0B) /* sata is invisible */ - } - } /* End \_SB scope */ - - Scope(\_SI) { - Method(_SST, 1) { - /* DBGO("\\_SI\\_SST\n") */ - /* DBGO(" New Indicator state: ") */ - /* DBGO(Arg0) */ - /* DBGO("\n") */ - } - } /* End Scope SI */ - - #include - - /* THERMAL */ - Scope(\_TZ) { - Name (KELV, 2732) - Name (THOT, 800) - Name (TCRT, 850) - - ThermalZone(TZ00) { - Method(_AC0,0) { /* Active Cooling 0 (0=highest fan speed) */ - /* DBGO("\\_TZ\\TZ00\\_AC0\n") */ - Return(Add(0, 2730)) - } - Method(_AL0,0) { /* Returns package of cooling device to turn on */ - /* DBGO("\\_TZ\\TZ00\\_AL0\n") */ - Return(Package() {\_TZ.TZ00.FAN0}) - } - Device (FAN0) { - Name(_HID, EISAID("PNP0C0B")) - Name(_PR0, Package() {PFN0}) - } - - PowerResource(PFN0,0,0) { - Method(_STA) { - Store(0xF,Local0) - Return(Local0) - } - Method(_ON) { - /* DBGO("\\_TZ\\TZ00\\FAN0 _ON\n") */ - } - Method(_OFF) { - /* DBGO("\\_TZ\\TZ00\\FAN0 _OFF\n") */ - } - } - - Method(_HOT,0) { /* return hot temp in tenths degree Kelvin */ - /* DBGO("\\_TZ\\TZ00\\_HOT\n") */ - Return (Add (THOT, KELV)) - } - Method(_CRT,0) { /* return critical temp in tenths degree Kelvin */ - /* DBGO("\\_TZ\\TZ00\\_CRT\n") */ - Return (Add (TCRT, KELV)) - } - Method(_TMP,0) { /* return current temp of this zone */ - Store (SMBR (0x07, 0x4C,, 0x00), Local0) - If (LGreater (Local0, 0x10)) { - Store (Local0, Local1) - } - Else { - Add (Local0, THOT, Local0) - Return (Add (400, KELV)) - } - - Store (SMBR (0x07, 0x4C, 0x01), Local0) - /* only the two MSBs in the external temperature low byte are used, resolution 0.25. We ignore it */ - /* Store (SMBR (0x07, 0x4C, 0x10), Local2) */ - If (LGreater (Local0, 0x10)) { - If (LGreater (Local0, Local1)) { - Store (Local0, Local1) - } - - Multiply (Local1, 10, Local1) - Return (Add (Local1, KELV)) - } - Else { - Add (Local0, THOT, Local0) - Return (Add (400 , KELV)) - } - } /* end of _TMP */ - } /* end of TZ00 */ - } -} -/* End of ASL file */ diff --git a/src/mainboard/iei/kino-780am2-fam10/get_bus_conf.c b/src/mainboard/iei/kino-780am2-fam10/get_bus_conf.c deleted file mode 100644 index 237ef2a2bd..0000000000 --- a/src/mainboard/iei/kino-780am2-fam10/get_bus_conf.c +++ /dev/null @@ -1,44 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2010 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include -#include -#include - -/* Global variables for MB layouts and these will be shared by irqtable mptable -* and acpi_tables busnum is default. -*/ -u32 apicid_sb700; - - -void get_bus_conf(void) -{ - u32 apicid_base; - - get_default_pci1234(1); - - sysconf.sbdn = (sysconf.hcdn[0] & 0xff); - - pirq_router_bus = (sysconf.pci1234[0] >> 16) & 0xff; - - /* I/O APICs: APIC ID Version State Address */ - if (CONFIG(LOGICAL_CPUS)) - apicid_base = get_apicid_base(1); - else - apicid_base = CONFIG_MAX_PHYSICAL_CPUS; - apicid_sb700 = apicid_base + 0; -} diff --git a/src/mainboard/iei/kino-780am2-fam10/irq_tables.c b/src/mainboard/iei/kino-780am2-fam10/irq_tables.c deleted file mode 100644 index 0f7192514e..0000000000 --- a/src/mainboard/iei/kino-780am2-fam10/irq_tables.c +++ /dev/null @@ -1,102 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2010 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include -#include -#include - -#include - -static void write_pirq_info(struct irq_info *pirq_info, u8 bus, u8 devfn, - u8 link0, u16 bitmap0, u8 link1, u16 bitmap1, - u8 link2, u16 bitmap2, u8 link3, u16 bitmap3, - u8 slot, u8 rfu) -{ - pirq_info->bus = bus; - pirq_info->devfn = devfn; - pirq_info->irq[0].link = link0; - pirq_info->irq[0].bitmap = bitmap0; - pirq_info->irq[1].link = link1; - pirq_info->irq[1].bitmap = bitmap1; - pirq_info->irq[2].link = link2; - pirq_info->irq[2].bitmap = bitmap2; - pirq_info->irq[3].link = link3; - pirq_info->irq[3].bitmap = bitmap3; - pirq_info->slot = slot; - pirq_info->rfu = rfu; -} - - -unsigned long write_pirq_routing_table(unsigned long addr) -{ - struct irq_routing_table *pirq; - struct irq_info *pirq_info; - u32 slot_num; - u8 *v; - - u8 sum = 0; - int i; - - /* Align the table to be 16 byte aligned. */ - addr += 15; - addr &= ~15; - - /* This table must be between 0xf0000 & 0x100000 */ - printk(BIOS_INFO, "Writing IRQ routing tables to 0x%lx...", addr); - - pirq = (void *)(addr); - v = (u8 *) (addr); - - pirq->signature = PIRQ_SIGNATURE; - pirq->version = PIRQ_VERSION; - - pirq->rtr_bus = pirq_router_bus; - pirq->rtr_devfn = PCI_DEVFN(0x14, 4); - - pirq->exclusive_irqs = 0; - - pirq->rtr_vendor = 0x1002; - pirq->rtr_device = 0x4384; - - pirq->miniport_data = 0; - - memset(pirq->rfu, 0, sizeof(pirq->rfu)); - - pirq_info = (void *)(&pirq->checksum + 1); - slot_num = 0; - - /* pci bridge */ - write_pirq_info(pirq_info, pirq_router_bus, PCI_DEVFN(0x14, 4), - 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, - 0); - pirq_info++; - slot_num++; - - pirq->size = 32 + 16 * slot_num; - - for (i = 0; i < pirq->size; i++) - sum += v[i]; - - sum = pirq->checksum - sum; - if (sum != pirq->checksum) { - pirq->checksum = sum; - } - - printk(BIOS_INFO, "write_pirq_routing_table done.\n"); - - return (unsigned long)pirq_info; -} diff --git a/src/mainboard/iei/kino-780am2-fam10/mainboard.c b/src/mainboard/iei/kino-780am2-fam10/mainboard.c deleted file mode 100644 index c602c82d60..0000000000 --- a/src/mainboard/iei/kino-780am2-fam10/mainboard.c +++ /dev/null @@ -1,48 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2010 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include -#include -#include -#include -#include - -/* TODO - Need to find GPIO for PCIE slot. - * Kino uses GPIO ? as PCIe slot reset, GPIO? as GFX slot reset. We need to - * pull it up before training the slot. - ***/ - -int is_dev3_present(void) -{ - return 0; -} - -/************************************************* -* enable the dedicated function in kino board. -* This function called early than rs780_enable. -*************************************************/ -static void mainboard_enable(struct device *dev) -{ - printk(BIOS_INFO, "Mainboard Kino Enable. dev=0x%p\n", dev); - - set_pcie_dereset(); - /* get_ide_dma66(); */ -} - -struct chip_operations mainboard_ops = { - .enable_dev = mainboard_enable, -}; diff --git a/src/mainboard/iei/kino-780am2-fam10/mptable.c b/src/mainboard/iei/kino-780am2-fam10/mptable.c deleted file mode 100644 index b04a315bb1..0000000000 --- a/src/mainboard/iei/kino-780am2-fam10/mptable.c +++ /dev/null @@ -1,101 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2010 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include -#include -#include - -extern u32 apicid_sb700; - -static void *smp_write_config_table(void *v) -{ - struct mp_config_table *mc; - int bus_isa; - - mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); - - mptable_init(mc, LOCAL_APIC_ADDR); - - smp_write_processors(mc); - - mptable_write_buses(mc, NULL, &bus_isa); - - /* I/O APICs: APIC ID Version State Address */ - { - struct device *dev; - u32 dword; - u8 byte; - - dev = - dev_find_slot(pirq_router_bus, - PCI_DEVFN(0x14, 0)); - if (dev) { - dword = pci_read_config32(dev, 0x74) & 0xfffffff0; - smp_write_ioapic(mc, apicid_sb700, - 0x11,(void *) dword); - - /* Initialize interrupt mapping */ - /* aza */ - byte = pci_read_config8(dev, 0x63); - byte &= 0xf8; - byte |= 0; /* 0: INTA, ...., 7: INTH */ - pci_write_config8(dev, 0x63, byte); - - /* SATA */ - dword = pci_read_config32(dev, 0xac); - dword &= ~(7 << 26); - dword |= 6 << 26; /* 0: INTA, ...., 7: INTH */ - /* dword |= 1 << 22; PIC and APIC co exists */ - pci_write_config32(dev, 0xac, dword); - - /* - * 00:12.0: PROG SATA : INT F - * 00:13.0: INTA USB_0 - * 00:13.1: INTB USB_1 - * 00:13.2: INTC USB_2 - * 00:13.3: INTD USB_3 - * 00:13.4: INTC USB_4 - * 00:13.5: INTD USB2 - * 00:14.1: INTA IDE - * 00:14.2: Prog HDA : INT E - * 00:14.5: INTB ACI - * 00:14.6: INTB MCI - */ - } - } - - /* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ -#define IO_LOCAL_INT(type, intr, apicid, pin) \ - smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin)); - - mptable_add_isa_interrupts(mc, bus_isa, apicid_sb700, 0); - - /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ - IO_LOCAL_INT(mp_ExtINT, 0x0, MP_APIC_ALL, 0x0); - IO_LOCAL_INT(mp_NMI, 0x0, MP_APIC_ALL, 0x1); - /* There is no extension information... */ - - /* Compute the checksums */ - return mptable_finalize(mc); -} - -unsigned long write_smp_table(unsigned long addr) -{ - void *v; - v = smp_write_floating_table(addr, 0); - return (unsigned long)smp_write_config_table(v); -} diff --git a/src/mainboard/iei/kino-780am2-fam10/resourcemap.c b/src/mainboard/iei/kino-780am2-fam10/resourcemap.c deleted file mode 100644 index 80d2d9d05c..0000000000 --- a/src/mainboard/iei/kino-780am2-fam10/resourcemap.c +++ /dev/null @@ -1,279 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2010 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - - - -#include -#include - -void setup_mb_resource_map(void) -{ - static const unsigned int register_values[] = { - /* Careful set limit registers before base registers which contain the enables */ - /* DRAM Limit i Registers - * F1:0x44 i = 0 - * F1:0x4C i = 1 - * F1:0x54 i = 2 - * F1:0x5C i = 3 - * F1:0x64 i = 4 - * F1:0x6C i = 5 - * F1:0x74 i = 6 - * F1:0x7C i = 7 - * [ 2: 0] Destination Node ID - * 000 = Node 0 - * 001 = Node 1 - * 010 = Node 2 - * 011 = Node 3 - * 100 = Node 4 - * 101 = Node 5 - * 110 = Node 6 - * 111 = Node 7 - * [ 7: 3] Reserved - * [10: 8] Interleave select - * specifies the values of A[14:12] to use with interleave enable. - * [15:11] Reserved - * [31:16] DRAM Limit Address i Bits 39-24 - * This field defines the upper address bits of a 40 bit address - * that define the end of the DRAM region. - */ -// ADDRMAP_REG(0x44), 0x0000f8f8, 0x00000000, // Don't touch it, we need it for CONFIG_CAR_FAM10 - ADDRMAP_REG(0x4C), 0x0000f8f8, 0x00000001, - ADDRMAP_REG(0x54), 0x0000f8f8, 0x00000002, - ADDRMAP_REG(0x5C), 0x0000f8f8, 0x00000003, - ADDRMAP_REG(0x64), 0x0000f8f8, 0x00000004, - ADDRMAP_REG(0x6C), 0x0000f8f8, 0x00000005, - ADDRMAP_REG(0x74), 0x0000f8f8, 0x00000006, - ADDRMAP_REG(0x7C), 0x0000f8f8, 0x00000007, - /* DRAM Base i Registers - * F1:0x40 i = 0 - * F1:0x48 i = 1 - * F1:0x50 i = 2 - * F1:0x58 i = 3 - * F1:0x60 i = 4 - * F1:0x68 i = 5 - * F1:0x70 i = 6 - * F1:0x78 i = 7 - * [ 0: 0] Read Enable - * 0 = Reads Disabled - * 1 = Reads Enabled - * [ 1: 1] Write Enable - * 0 = Writes Disabled - * 1 = Writes Enabled - * [ 7: 2] Reserved - * [10: 8] Interleave Enable - * 000 = No interleave - * 001 = Interleave on A[12] (2 nodes) - * 010 = reserved - * 011 = Interleave on A[12] and A[14] (4 nodes) - * 100 = reserved - * 101 = reserved - * 110 = reserved - * 111 = Interleve on A[12] and A[13] and A[14] (8 nodes) - * [15:11] Reserved - * [13:16] DRAM Base Address i Bits 39-24 - * This field defines the upper address bits of a 40-bit address - * that define the start of the DRAM region. - */ -// ADDRMAP_REG(0x40), 0x0000f8fc, 0x00000000,// don't touch it, we need it for CONFIG_CAR_FAM10 - ADDRMAP_REG(0x48), 0x0000f8fc, 0x00000000, - ADDRMAP_REG(0x50), 0x0000f8fc, 0x00000000, - ADDRMAP_REG(0x58), 0x0000f8fc, 0x00000000, - ADDRMAP_REG(0x60), 0x0000f8fc, 0x00000000, - ADDRMAP_REG(0x68), 0x0000f8fc, 0x00000000, - ADDRMAP_REG(0x70), 0x0000f8fc, 0x00000000, - ADDRMAP_REG(0x78), 0x0000f8fc, 0x00000000, - - /* Memory-Mapped I/O Limit i Registers - * F1:0x84 i = 0 - * F1:0x8C i = 1 - * F1:0x94 i = 2 - * F1:0x9C i = 3 - * F1:0xA4 i = 4 - * F1:0xAC i = 5 - * F1:0xB4 i = 6 - * F1:0xBC i = 7 - * [ 2: 0] Destination Node ID - * 000 = Node 0 - * 001 = Node 1 - * 010 = Node 2 - * 011 = Node 3 - * 100 = Node 4 - * 101 = Node 5 - * 110 = Node 6 - * 111 = Node 7 - * [ 3: 3] Reserved - * [ 5: 4] Destination Link ID - * 00 = Link 0 - * 01 = Link 1 - * 10 = Link 2 - * 11 = Reserved - * [ 6: 6] Reserved - * [ 7: 7] Non-Posted - * 0 = CPU writes may be posted - * 1 = CPU writes must be non-posted - * [31: 8] Memory-Mapped I/O Limit Address i (39-16) - * This field defines the upp address bits of a 40-bit address that - * defines the end of a memory-mapped I/O region n - */ - ADDRMAP_REG(0x84), 0x00000048, 0x00000000, - ADDRMAP_REG(0x8C), 0x00000048, 0x00000000, - ADDRMAP_REG(0x94), 0x00000048, 0x00000000, - ADDRMAP_REG(0x9C), 0x00000048, 0x00000000, - ADDRMAP_REG(0xA4), 0x00000048, 0x00000000, - ADDRMAP_REG(0xAC), 0x00000048, 0x00000000, - ADDRMAP_REG(0xB4), 0x00000048, 0x00000000, -// ADDRMAP_REG(0xBC), 0x00000048, 0x00ffff00, - - /* Memory-Mapped I/O Base i Registers - * F1:0x80 i = 0 - * F1:0x88 i = 1 - * F1:0x90 i = 2 - * F1:0x98 i = 3 - * F1:0xA0 i = 4 - * F1:0xA8 i = 5 - * F1:0xB0 i = 6 - * F1:0xB8 i = 7 - * [ 0: 0] Read Enable - * 0 = Reads disabled - * 1 = Reads Enabled - * [ 1: 1] Write Enable - * 0 = Writes disabled - * 1 = Writes Enabled - * [ 2: 2] Cpu Disable - * 0 = Cpu can use this I/O range - * 1 = Cpu requests do not use this I/O range - * [ 3: 3] Lock - * 0 = base/limit registers i are read/write - * 1 = base/limit registers i are read-only - * [ 7: 4] Reserved - * [31: 8] Memory-Mapped I/O Base Address i (39-16) - * This field defines the upper address bits of a 40bit address - * that defines the start of memory-mapped I/O region i - */ - ADDRMAP_REG(0x80), 0x000000f0, 0x00000000, - ADDRMAP_REG(0x88), 0x000000f0, 0x00000000, - ADDRMAP_REG(0x90), 0x000000f0, 0x00000000, - ADDRMAP_REG(0x98), 0x000000f0, 0x00000000, - ADDRMAP_REG(0xA0), 0x000000f0, 0x00000000, - ADDRMAP_REG(0xA8), 0x000000f0, 0x00000000, - ADDRMAP_REG(0xB0), 0x000000f0, 0x00000000, -// ADDRMAP_REG(0xB8), 0x000000f0, 0x00fc0003, - - /* PCI I/O Limit i Registers - * F1:0xC4 i = 0 - * F1:0xCC i = 1 - * F1:0xD4 i = 2 - * F1:0xDC i = 3 - * [ 2: 0] Destination Node ID - * 000 = Node 0 - * 001 = Node 1 - * 010 = Node 2 - * 011 = Node 3 - * 100 = Node 4 - * 101 = Node 5 - * 110 = Node 6 - * 111 = Node 7 - * [ 3: 3] Reserved - * [ 5: 4] Destination Link ID - * 00 = Link 0 - * 01 = Link 1 - * 10 = Link 2 - * 11 = reserved - * [11: 6] Reserved - * [24:12] PCI I/O Limit Address i - * This field defines the end of PCI I/O region n - * [31:25] Reserved - */ -// ADDRMAP_REG(0xC4), 0xFE000FC8, 0x01fff000, - ADDRMAP_REG(0xCC), 0xFE000FC8, 0x00000000, - ADDRMAP_REG(0xD4), 0xFE000FC8, 0x00000000, - ADDRMAP_REG(0xDC), 0xFE000FC8, 0x00000000, - - /* PCI I/O Base i Registers - * F1:0xC0 i = 0 - * F1:0xC8 i = 1 - * F1:0xD0 i = 2 - * F1:0xD8 i = 3 - * [ 0: 0] Read Enable - * 0 = Reads Disabled - * 1 = Reads Enabled - * [ 1: 1] Write Enable - * 0 = Writes Disabled - * 1 = Writes Enabled - * [ 3: 2] Reserved - * [ 4: 4] VGA Enable - * 0 = VGA matches Disabled - * 1 = matches all address < 64K and where A[9:0] is in the - * range 3B0-3BB or 3C0-3DF independen of the base & limit registers - * [ 5: 5] ISA Enable - * 0 = ISA matches Disabled - * 1 = Blocks address < 64K and in the last 768 bytes of eack 1K block - * from matching agains this base/limit pair - * [11: 6] Reserved - * [24:12] PCI I/O Base i - * This field defines the start of PCI I/O region n - * [31:25] Reserved - */ -// ADDRMAP_REG(0xC0), 0xFE000FCC, 0x00000003, - ADDRMAP_REG(0xC8), 0xFE000FCC, 0x00000000, - ADDRMAP_REG(0xD0), 0xFE000FCC, 0x00000000, - ADDRMAP_REG(0xD8), 0xFE000FCC, 0x00000000, - - /* Config Base and Limit i Registers - * F1:0xE0 i = 0 - * F1:0xE4 i = 1 - * F1:0xE8 i = 2 - * F1:0xEC i = 3 - * [ 0: 0] Read Enable - * 0 = Reads Disabled - * 1 = Reads Enabled - * [ 1: 1] Write Enable - * 0 = Writes Disabled - * 1 = Writes Enabled - * [ 2: 2] Device Number Compare Enable - * 0 = The ranges are based on bus number - * 1 = The ranges are ranges of devices on bus 0 - * [ 3: 3] Reserved - * [ 6: 4] Destination Node - * 000 = Node 0 - * 001 = Node 1 - * 010 = Node 2 - * 011 = Node 3 - * 100 = Node 4 - * 101 = Node 5 - * 110 = Node 6 - * 111 = Node 7 - * [ 7: 7] Reserved - * [ 9: 8] Destination Link - * 00 = Link 0 - * 01 = Link 1 - * 10 = Link 2 - * 11 - Reserved - * [15:10] Reserved - * [23:16] Bus Number Base i - * This field defines the lowest bus number in configuration region i - * [31:24] Bus Number Limit i - * This field defines the highest bus number in configuration regin i - */ -// ADDRMAP_REG(0xE0), 0x0000FC88, 0x06000003, // AMD 8111 on link0 of CPU 0 - ADDRMAP_REG(0xE4), 0x0000FC88, 0x00000000, - ADDRMAP_REG(0xE8), 0x0000FC88, 0x00000000, - ADDRMAP_REG(0xEC), 0x0000FC88, 0x00000000, - }; - - int max; - max = ARRAY_SIZE(register_values); - setup_resource_map(register_values, max); -} diff --git a/src/mainboard/iei/kino-780am2-fam10/romstage.c b/src/mainboard/iei/kino-780am2-fam10/romstage.c deleted file mode 100644 index d8afd67e94..0000000000 --- a/src/mainboard/iei/kino-780am2-fam10/romstage.c +++ /dev/null @@ -1,222 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2010 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -//#define SYSTEM_TYPE 0 /* SERVER */ -#define SYSTEM_TYPE 1 /* DESKTOP */ -//#define SYSTEM_TYPE 2 /* MOBILE */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include "cpu/amd/quadcore/quadcore.c" - -#define SERIAL_DEV PNP_DEV(0x2e, F71859_SP1) - -int spd_read_byte(unsigned int device, unsigned int address); - - -int spd_read_byte(u32 device, u32 address) -{ - return do_smbus_read_byte(SMBUS_IO_BASE, device, address); -} - -void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) -{ - struct sys_info *sysinfo = get_sysinfo(); - static const u8 spd_addr[] = {RC00, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, }; - u32 bsp_apicid = 0, val; - msr_t msr; - - timestamp_init(timestamp_get()); - timestamp_add_now(TS_START_ROMSTAGE); - - if (!cpu_init_detectedx && boot_cpu()) { - /* Nothing special needs to be done to find bus 0 */ - /* Allow the HT devices to be found */ - /* mov bsp to bus 0xff when > 8 nodes */ - set_bsp_node_CHtExtNodeCfgEn(); - enumerate_ht_chain(); - sb7xx_51xx_pci_port80(); - } - - post_code(0x30); - - if (bist == 0) { - bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo); /* mmconf is inited in init_cpus */ - /* All cores run this but the BSP(node0,core0) is the only core that returns. */ - } - - post_code(0x32); - - enable_rs780_dev8(); - sb7xx_51xx_lpc_init(); - - fintek_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); - - console_init(); - - /* Halt if there was a built in self test failure */ - report_bist_failure(bist); - - // Load MPB - val = cpuid_eax(1); - printk(BIOS_DEBUG, "BSP Family_Model: %08x\n", val); - printk(BIOS_DEBUG, "*sysinfo range: [%p,%p]\n",sysinfo,sysinfo+1); - printk(BIOS_DEBUG, "bsp_apicid = %02x\n", bsp_apicid); - printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx); - - /* Setup sysinfo defaults */ - set_sysinfo_in_ram(0); - - update_microcode(val); - - post_code(0x33); - - cpuSetAMDMSR(0); - post_code(0x34); - - amd_ht_init(sysinfo); - post_code(0x35); - - /* Setup nodes PCI space and start core 0 AP init. */ - finalize_node_setup(sysinfo); - - /* Setup any mainboard PCI settings etc. */ - setup_mb_resource_map(); - post_code(0x36); - - /* wait for all the APs core0 started by finalize_node_setup. */ - /* FIXME: A bunch of cores are going to start output to serial at once. - It would be nice to fixup prink spinlocks for ROM XIP mode. - I think it could be done by putting the spinlock flag in the cache - of the BSP located right after sysinfo. - */ - wait_all_core0_started(); - - #if CONFIG(LOGICAL_CPUS) - /* Core0 on each node is configured. Now setup any additional cores. */ - printk(BIOS_DEBUG, "start_other_cores()\n"); - start_other_cores(bsp_apicid); - post_code(0x37); - wait_all_other_cores_started(bsp_apicid); - #endif - - post_code(0x38); - - /* run _early_setup before soft-reset. */ - rs780_early_setup(); - sb7xx_51xx_early_setup(); - - #if CONFIG(SET_FIDVID) - msr = rdmsr(MSR_COFVID_STS); - printk(BIOS_DEBUG, "\nBegin FIDVID MSR 0xc0010071 0x%08x 0x%08x\n", msr.hi, msr.lo); - - /* FIXME: The sb fid change may survive the warm reset and only - need to be done once.*/ - enable_fid_change_on_sb(sysinfo->sbbusn, sysinfo->sbdn); - - post_code(0x39); - - if (!warm_reset_detect(0)) { // BSP is node 0 - init_fidvid_bsp(bsp_apicid, sysinfo->nodes); - } else { - init_fidvid_stage2(bsp_apicid, 0); // BSP is node 0 - } - - post_code(0x3A); - - /* show final fid and vid */ - msr = rdmsr(MSR_COFVID_STS); - printk(BIOS_DEBUG, "End FIDVIDMSR 0xc0010071 0x%08x 0x%08x\n", msr.hi, msr.lo); - #endif - - rs780_htinit(); - - /* Reset for HT, FIDVID, PLL and errata changes to take affect. */ - if (!warm_reset_detect(0)) { - printk(BIOS_INFO, "...WARM RESET...\n\n\n"); - soft_reset(); - die("After soft_reset - shouldn't see this message!!!\n"); - } - - post_code(0x3B); - - /* It's the time to set ctrl in sysinfo now; */ - printk(BIOS_DEBUG, "fill_mem_ctrl()\n"); - fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr); - - post_code(0x40); - - raminit_amdmct(sysinfo); - - cbmem_initialize_empty(); - post_code(0x41); - - amdmct_cbmem_store_info(sysinfo); - - sb7xx_51xx_before_pci_init(); - - post_code(0x42); -} - -/** - * BOOL AMD_CB_ManualBUIDSwapList(u8 Node, u8 Link, u8 **List) - * Description: - * This routine is called every time a non-coherent chain is processed. - * BUID assignment may be controlled explicitly on a non-coherent chain. Provide a - * swap list. The first part of the list controls the BUID assignment and the - * second part of the list provides the device to device linking. Device orientation - * can be detected automatically, or explicitly. See documentation for more details. - * - * Automatic non-coherent init assigns BUIDs starting at 1 and incrementing sequentially - * based on each device's unit count. - * - * Parameters: - * @param[in] node = The node on which this chain is located - * @param[in] link = The link on the host for this chain - * @param[out] List = supply a pointer to a list - */ -BOOL AMD_CB_ManualBUIDSwapList (u8 node, u8 link, const u8 **List) -{ - static const u8 swaplist[] = {0, 1, 0xFF, 0, 0xFF}; - /* If the BUID was adjusted in early_ht we need to do the manual override */ - if ((node == 0) && (link == 0)) { /* BSP SB link */ - *List = swaplist; - return 1; - } - - return 0; -} diff --git a/src/mainboard/jetway/pa78vm5/Kconfig b/src/mainboard/jetway/pa78vm5/Kconfig deleted file mode 100644 index 5513969590..0000000000 --- a/src/mainboard/jetway/pa78vm5/Kconfig +++ /dev/null @@ -1,54 +0,0 @@ -if BOARD_JETWAY_PA78VM5 - -config BOARD_SPECIFIC_OPTIONS - def_bool y - select CPU_AMD_SOCKET_AM2R2 - select DIMM_DDR2 - select DIMM_REGISTERED - select NORTHBRIDGE_AMD_AMDFAM10 - select SOUTHBRIDGE_AMD_RS780 - select SOUTHBRIDGE_AMD_SB700 - select SUPERIO_FINTEK_F71863FG - select HAVE_OPTION_TABLE - select HAVE_PIRQ_TABLE - select HAVE_MP_TABLE - select SB_HT_CHAIN_UNITID_OFFSET_ONLY - select LIFT_BSP_APIC_ID - select HAVE_ACPI_TABLES - select BOARD_ROMSIZE_KB_1024 - select ENABLE_APIC_EXT_ID - select GFXUMA - -config MAINBOARD_DIR - string - default jetway/pa78vm5 - -config APIC_ID_OFFSET - hex - default 0x0 - -config MAINBOARD_PART_NUMBER - string - default "PA78VM5 (Fam10)" - -config MAX_CPUS - int - default 8 - -config MAX_PHYSICAL_CPUS - int - default 2 - -config HT_CHAIN_END_UNITID_BASE - hex - default 0x1 - -config HT_CHAIN_UNITID_BASE - hex - default 0x0 - -config IRQ_SLOT_COUNT - int - default 11 - -endif # BOARD_JETWAY_PA78VM5 diff --git a/src/mainboard/jetway/pa78vm5/Kconfig.name b/src/mainboard/jetway/pa78vm5/Kconfig.name deleted file mode 100644 index 9de8d2b480..0000000000 --- a/src/mainboard/jetway/pa78vm5/Kconfig.name +++ /dev/null @@ -1,2 +0,0 @@ -config BOARD_JETWAY_PA78VM5 - bool "PA78VM5 (Fam10)" diff --git a/src/mainboard/jetway/pa78vm5/Makefile.inc b/src/mainboard/jetway/pa78vm5/Makefile.inc deleted file mode 100644 index 91d4b39c32..0000000000 --- a/src/mainboard/jetway/pa78vm5/Makefile.inc +++ /dev/null @@ -1,16 +0,0 @@ -# -# This file is part of the coreboot project. -# -# This program is free software; you can redistribute it and/or modify -# it under the terms of the GNU General Public License as published by -# the Free Software Foundation; version 2 of the License. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# - -romstage-y += resourcemap.c - -ramstage-y += get_bus_conf.c diff --git a/src/mainboard/jetway/pa78vm5/acpi/cpstate.asl b/src/mainboard/jetway/pa78vm5/acpi/cpstate.asl deleted file mode 100644 index acaa5bae32..0000000000 --- a/src/mainboard/jetway/pa78vm5/acpi/cpstate.asl +++ /dev/null @@ -1,80 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2010 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -/* This file defines the processor and performance state capability - * for each core in the system. It is included into the DSDT for each - * core. It assumes that each core of the system has the same performance - * characteristics. -*/ -/* -#include -DefinitionBlock ("DSDT.AML", "DSDT", 0x01, OEM_ID, ACPI_TABLE_CREATOR, 0x00010001) - { - Scope (\_PR) { - Device (CPU0) { - Name (_HID, "ACPI0007") - Name (_UID, 0) - #include "cpstate.asl" - } - Device (CPU1) { - Name (_HID, "ACPI0007") - Name (_UID, 1) - #include "cpstate.asl" - } - Device (CPU2) { - Name (_HID, "ACPI0007") - Name (_UID, 2) - #include "cpstate.asl" - } - Device (CPU3) { - Name (_HID, "ACPI0007") - Name (_UID, 3) - #include "cpstate.asl" - } - } -*/ - /* P-state support: The maximum number of P-states supported by the */ - /* CPUs we'll use is 6. */ - /* Get from AMI BIOS. */ - Name(_PSS, Package(){ - Package () - { - 0x00000AF0, - 0x0000BF81, - 0x00000002, - 0x00000002, - 0x00000000, - 0x00000000 - }, - - Package () - { - 0x00000578, - 0x000076F2, - 0x00000002, - 0x00000002, - 0x00000001, - 0x00000001 - } - }) - - Name(_PCT, Package(){ - ResourceTemplate(){Register(FFixedHW, 0, 0, 0)}, - ResourceTemplate(){Register(FFixedHW, 0, 0, 0)} - }) - - Method(_PPC, 0){ - Return(0) - } diff --git a/src/mainboard/jetway/pa78vm5/acpi/ide.asl b/src/mainboard/jetway/pa78vm5/acpi/ide.asl deleted file mode 100644 index 5c155cf301..0000000000 --- a/src/mainboard/jetway/pa78vm5/acpi/ide.asl +++ /dev/null @@ -1,240 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2010 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -/* -Scope (_SB) { - Device(PCI0) { - Device(IDEC) { - Name(_ADR, 0x00140001) - #include "ide.asl" - } - } -} -*/ - -/* Some timing tables */ -Name(UDTT, Package(){ /* Udma timing table */ - 120, 90, 60, 45, 30, 20, 15, 0 /* UDMA modes 0 -> 6 */ -}) - -Name(MDTT, Package(){ /* MWDma timing table */ - 480, 150, 120, 0 /* Legacy DMA modes 0 -> 2 */ -}) - -Name(POTT, Package(){ /* Pio timing table */ - 600, 390, 270, 180, 120, 0 /* PIO modes 0 -> 4 */ -}) - -/* Some timing register value tables */ -Name(MDRT, Package(){ /* MWDma timing register table */ - 0x77, 0x21, 0x20, 0xFF /* Legacy DMA modes 0 -> 2 */ -}) - -Name(PORT, Package(){ - 0x99, 0x47, 0x34, 0x22, 0x20, 0x99 /* PIO modes 0 -> 4 */ -}) - -OperationRegion(ICRG, PCI_Config, 0x40, 0x20) /* ide control registers */ - Field(ICRG, AnyAcc, NoLock, Preserve) -{ - PPTS, 8, /* Primary PIO Slave Timing */ - PPTM, 8, /* Primary PIO Master Timing */ - OFFSET(0x04), PMTS, 8, /* Primary MWDMA Slave Timing */ - PMTM, 8, /* Primary MWDMA Master Timing */ - OFFSET(0x08), PPCR, 8, /* Primary PIO Control */ - OFFSET(0x0A), PPMM, 4, /* Primary PIO master Mode */ - PPSM, 4, /* Primary PIO slave Mode */ - OFFSET(0x14), PDCR, 2, /* Primary UDMA Control */ - OFFSET(0x16), PDMM, 4, /* Primary UltraDMA Mode */ - PDSM, 4, /* Primary UltraDMA Mode */ -} - -Method(GTTM, 1) /* get total time*/ -{ - Store(And(Arg0, 0x0F), Local0) /* Recovery Width */ - Increment(Local0) - Store(ShiftRight(Arg0, 4), Local1) /* Command Width */ - Increment(Local1) - Return(Multiply(30, Add(Local0, Local1))) -} - -Device(PRID) -{ - Name (_ADR, Zero) - Method(_GTM, 0) - { - NAME(OTBF, Buffer(20) { /* out buffer */ - 0xFF, 0xFF, 0xFF, 0xFF, - 0xFF, 0xFF, 0xFF, 0xFF, - 0xFF, 0xFF, 0xFF, 0xFF, - 0xFF, 0xFF, 0xFF, 0xFF, 0x00, 0x00, 0x00, 0x00 - }) - - CreateDwordField(OTBF, 0, PSD0) /* PIO spd0 */ - CreateDwordField(OTBF, 4, DSD0) /* DMA spd0 */ - CreateDwordField(OTBF, 8, PSD1) /* PIO spd1 */ - CreateDwordField(OTBF, 12, DSD1) /* DMA spd1 */ - CreateDwordField(OTBF, 16, BFFG) /* buffer flags */ - - /* Just return if the channel is disabled */ - If(And(PPCR, 0x01)) { /* primary PIO control */ - Return(OTBF) - } - - /* Always tell them independent timing available and IOChannelReady used on both drives */ - Or(BFFG, 0x1A, BFFG) - - Store(GTTM(PPTM), PSD0) /* save total time of primary PIO master timming to PIO spd0 */ - Store(GTTM(PPTS), PSD1) /* save total time of primary PIO slave Timing to PIO spd1 */ - - If(And(PDCR, 0x01)) { /* It's under UDMA mode */ - Or(BFFG, 0x01, BFFG) - Store(DerefOf(Index(UDTT, PDMM)), DSD0) - } - Else { - Store(GTTM(PMTM), DSD0) /* Primary MWDMA Master Timing, DmaSpd0 */ - } - - If(And(PDCR, 0x02)) { /* It's under UDMA mode */ - Or(BFFG, 0x04, BFFG) - Store(DerefOf(Index(UDTT, PDSM)), DSD1) - } - Else { - Store(GTTM(PMTS), DSD1) /* Primary MWDMA Slave Timing, DmaSpd0 */ - } - - Return(OTBF) /* out buffer */ - } /* End Method(_GTM) */ - - Method(_STM, 3, NotSerialized) - { - NAME(INBF, Buffer(20) { /* in buffer */ - 0xFF, 0xFF, 0xFF, 0xFF, - 0xFF, 0xFF, 0xFF, 0xFF, - 0xFF, 0xFF, 0xFF, 0xFF, - 0xFF, 0xFF, 0xFF, 0xFF, 0x00, 0x00, 0x00, 0x00 - }) - - CreateDwordField(INBF, 0, PSD0) /* PIO spd0 */ - CreateDwordField(INBF, 4, DSD0) /* PIO spd0 */ - CreateDwordField(INBF, 8, PSD1) /* PIO spd1 */ - CreateDwordField(INBF, 12, DSD1) /* DMA spd1 */ - CreateDwordField(INBF, 16, BFFG) /*buffer flag */ - - Store(Match(POTT, MLE, PSD0, MTR, 0, 0), Local0) - Divide(Local0, 5, PPMM,) /* Primary PIO master Mode */ - Store(Match(POTT, MLE, PSD1, MTR, 0, 0), Local1) - Divide(Local1, 5, PPSM,) /* Primary PIO slave Mode */ - - Store(DerefOf(Index(PORT, Local0)), PPTM) /* Primary PIO Master Timing */ - Store(DerefOf(Index(PORT, Local1)), PPTS) /* Primary PIO Slave Timing */ - - If(And(BFFG, 0x01)) { /* Drive 0 is under UDMA mode */ - Store(Match(UDTT, MLE, DSD0, MTR, 0, 0), Local0) - Divide(Local0, 7, PDMM,) - Or(PDCR, 0x01, PDCR) - } - Else { - If(LNotEqual(DSD0, 0xFFFFFFFF)) { - Store(Match(MDTT, MLE, DSD0, MTR, 0, 0), Local0) - Store(DerefOf(Index(MDRT, Local0)), PMTM) - } - } - - If(And(BFFG, 0x04)) { /* Drive 1 is under UDMA mode */ - Store(Match(UDTT, MLE, DSD1, MTR, 0, 0), Local0) - Divide(Local0, 7, PDSM,) - Or(PDCR, 0x02, PDCR) - } - Else { - If(LNotEqual(DSD1, 0xFFFFFFFF)) { - Store(Match(MDTT, MLE, DSD1, MTR, 0, 0), Local0) - Store(DerefOf(Index(MDRT, Local0)), PMTS) - } - } - /* Return(INBF) */ - } /*End Method(_STM) */ - Device(MST) - { - Name(_ADR, 0) - Method(_GTF) { - Name(CMBF, Buffer(21) { - 0x03, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xEF, - 0x03, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xEF, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xF5 - }) - CreateByteField(CMBF, 1, POMD) - CreateByteField(CMBF, 8, DMMD) - CreateByteField(CMBF, 5, CMDA) - CreateByteField(CMBF, 12, CMDB) - CreateByteField(CMBF, 19, CMDC) - - Store(0xA0, CMDA) - Store(0xA0, CMDB) - Store(0xA0, CMDC) - - Or(PPMM, 0x08, POMD) - - If(And(PDCR, 0x01)) { - Or(PDMM, 0x40, DMMD) - } - Else { - Store(Match - (MDTT, MLE, GTTM(PMTM), - MTR, 0, 0), Local0) - If(LLess(Local0, 3)) { - Or(0x20, Local0, DMMD) - } - } - Return(CMBF) - } - } /* End Device(MST) */ - - Device(SLAV) - { - Name(_ADR, 1) - Method(_GTF) { - Name(CMBF, Buffer(21) { - 0x03, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xEF, - 0x03, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xEF, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xF5 - }) - CreateByteField(CMBF, 1, POMD) - CreateByteField(CMBF, 8, DMMD) - CreateByteField(CMBF, 5, CMDA) - CreateByteField(CMBF, 12, CMDB) - CreateByteField(CMBF, 19, CMDC) - - Store(0xB0, CMDA) - Store(0xB0, CMDB) - Store(0xB0, CMDC) - - Or(PPSM, 0x08, POMD) - - If(And(PDCR, 0x02)) { - Or(PDSM, 0x40, DMMD) - } - Else { - Store(Match - (MDTT, MLE, GTTM(PMTS), - MTR, 0, 0), Local0) - If(LLess(Local0, 3)) { - Or(0x20, Local0, DMMD) - } - } - Return(CMBF) - } - } /* End Device(SLAV) */ -} diff --git a/src/mainboard/jetway/pa78vm5/acpi/routing.asl b/src/mainboard/jetway/pa78vm5/acpi/routing.asl deleted file mode 100644 index abb8ddc6bf..0000000000 --- a/src/mainboard/jetway/pa78vm5/acpi/routing.asl +++ /dev/null @@ -1,308 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2010 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -/* -#include -DefinitionBlock ("DSDT.AML", "DSDT", 0x01, OEM_ID, ACPI_TABLE_CREATOR, 0x00010001 - ) - { - #include "routing.asl" - } -*/ - -/* Routing is in System Bus scope */ -Scope(\_SB) { - Name(PR0, Package(){ - /* NB devices */ - /* Bus 0, Dev 0 - RS780 Host Controller */ - /* Bus 0, Dev 1 - PCI Bridge for Internal Graphics */ - /* Bus 0, Dev 2 - PCIe Bridge for x8 PCIe Slot (GFX0) */ - Package(){0x0002FFFF, 0, INTC, 0 }, - Package(){0x0002FFFF, 1, INTD, 0 }, - Package(){0x0002FFFF, 2, INTA, 0 }, - Package(){0x0002FFFF, 3, INTB, 0 }, - /* Bus 0, Dev 3 - PCIe graphics port 1 bridge */ - /* Bus 0, Dev 4 - PCIe Bridge for Express Card Slot */ - Package(){0x0004FFFF, 0, INTA, 0 }, - Package(){0x0004FFFF, 1, INTB, 0 }, - Package(){0x0004FFFF, 2, INTC, 0 }, - Package(){0x0004FFFF, 3, INTD, 0 }, - /* Bus 0, Dev 5 - General purpose PCIe bridge 5 */ - /* Package(){0x0005FFFF, 0, INTB, 0 }, */ - /* Package(){0x0005FFFF, 1, INTC, 0 }, */ - /* Package(){0x0005FFFF, 2, INTD, 0 }, */ - /* Package(){0x0005FFFF, 3, INTA, 0 }, */ - /* Bus 0, Dev 6 - PCIe Bridge for Ethernet Chip */ - Package(){0x0006FFFF, 0, INTC, 0 }, - Package(){0x0006FFFF, 1, INTD, 0 }, - Package(){0x0006FFFF, 2, INTA, 0 }, - Package(){0x0006FFFF, 3, INTB, 0 }, - /* Bus 0, Dev 7 - PCIe Bridge for x1 PCIe Slot */ - Package(){0x0007FFFF, 0, INTD, 0 }, - Package(){0x0007FFFF, 1, INTA, 0 }, - Package(){0x0007FFFF, 2, INTB, 0 }, - Package(){0x0007FFFF, 3, INTC, 0 }, - /* Bus 0, Funct 8 - Southbridge port (normally hidden) */ - - /* SB devices */ - /* Bus 0, Dev 17 - SATA controller #2 */ - /* Bus 0, Dev 18 - SATA controller #1 */ - Package(){0x0011FFFF, 0, INTA, 0 }, - - /* Bus 0, Dev 19 - USB: OHCI, dev 18,19 func 0-2, dev 20 func 5; - * EHCI, dev 18, 19 func 2 */ - Package(){0x0012FFFF, 0, INTA, 0 }, - Package(){0x0012FFFF, 1, INTB, 0 }, - Package(){0x0012FFFF, 2, INTC, 0 }, - - Package(){0x0013FFFF, 0, INTC, 0 }, - Package(){0x0013FFFF, 1, INTD, 0 }, - Package(){0x0013FFFF, 2, INTA, 0 }, - - /* Package(){0x0014FFFF, 1, INTA, 0 }, */ - - /* Bus 0, Dev 20 - F0:SMBus/ACPI,F1:IDE;F2:HDAudio;F3:LPC;F4:PCIBridge;F5:USB */ - Package(){0x0014FFFF, 0, INTA, 0 }, - Package(){0x0014FFFF, 1, INTB, 0 }, - Package(){0x0014FFFF, 2, INTC, 0 }, - Package(){0x0014FFFF, 3, INTD, 0 }, - }) - - Name(APR0, Package(){ - /* NB devices in APIC mode */ - /* Bus 0, Dev 0 - RS780 Host Controller */ - - /* Bus 0, Dev 1 - PCI Bridge for Internal Graphics */ - /* Package(){0x0001FFFF, 0, 0, 18 }, */ - /* Package(){0x0001FFFF, 1, 0, 19 }, */ - - /* Bus 0, Dev 2 - PCIe Bridge for x8 PCIe Slot (GFX0) */ - Package(){0x0002FFFF, 0, 0, 18 }, - /* Package(){0x0002FFFF, 1, 0, 19 }, */ - /* Package(){0x0002FFFF, 2, 0, 16 }, */ - /* Package(){0x0002FFFF, 3, 0, 17 }, */ - - /* Bus 0, Dev 3 - PCIe graphics port 1 bridge */ - Package(){0x0003FFFF, 0, 0, 19 }, - - /* Bus 0, Dev 4 - PCIe Bridge for Express Card Slot */ - Package(){0x0004FFFF, 0, 0, 16 }, - /* Package(){0x0004FFFF, 1, 0, 17 }, */ - /* Package(){0x0004FFFF, 2, 0, 18 }, */ - /* Package(){0x0004FFFF, 3, 0, 19 }, */ - - /* Bus 0, Dev 5 - General purpose PCIe bridge 5 */ - /* Package(){0x0005FFFF, 0, 0, 17 }, */ - /* Package(){0x0005FFFF, 1, 0, 18 }, */ - /* Package(){0x0005FFFF, 2, 0, 19 }, */ - /* Package(){0x0005FFFF, 3, 0, 16 }, */ - - /* Bus 0, Dev 6 - General purpose PCIe bridge 6 */ - /* Package(){0x0006FFFF, 0, 0, 18 }, */ - /* Package(){0x0006FFFF, 1, 0, 19 }, */ - /* Package(){0x0006FFFF, 2, 0, 16 }, */ - /* Package(){0x0006FFFF, 3, 0, 17 }, */ - - /* Bus 0, Dev 7 - PCIe Bridge for network card */ - /* Package(){0x0007FFFF, 0, 0, 19 }, */ - /* Package(){0x0007FFFF, 1, 0, 16 }, */ - /* Package(){0x0007FFFF, 2, 0, 17 }, */ - /* Package(){0x0007FFFF, 3, 0, 18 }, */ - - /* Bus 0, Dev 9 - PCIe Bridge for network card */ - Package(){0x0009FFFF, 0, 0, 17 }, - /* Package(){0x0009FFFF, 1, 0, 16 }, */ - /* Package(){0x0009FFFF, 2, 0, 17 }, */ - /* Package(){0x0009FFFF, 3, 0, 18 }, */ - /* Bus 0, Dev A - PCIe Bridge for network card */ - Package(){0x000AFFFF, 0, 0, 18 }, - /* Package(){0x000AFFFF, 1, 0, 16 }, */ - /* Package(){0x000AFFFF, 2, 0, 17 }, */ - /* Package(){0x000AFFFF, 3, 0, 18 }, */ - /* Bus 0, Funct 8 - Southbridge port (normally hidden) */ - - /* SB devices in APIC mode */ - /* Bus 0, Dev 17 - SATA controller #2 */ - /* Bus 0, Dev 18 - SATA controller #1 */ - Package(){0x0011FFFF, 0, 0, 22 }, - - /* Bus 0, Dev 19 - USB: OHCI, dev 18,19 func 0-2, dev 20 func 5; - * EHCI, dev 18, 19 func 2 */ - Package(){0x0012FFFF, 0, 0, 16 }, - Package(){0x0012FFFF, 1, 0, 17 }, - Package(){0x0012FFFF, 2, 0, 18 }, - - Package(){0x0013FFFF, 0, 0, 18 }, - Package(){0x0013FFFF, 1, 0, 19 }, - Package(){0x0013FFFF, 2, 0, 16 }, - - /* Package(){0x00140000, 0, 0, 16 }, */ - - /* Package(){0x00130004, 2, 0, 18 }, */ - /* Package(){0x00130005, 3, 0, 19 }, */ - - /* Bus 0, Dev 20 - F0:SMBus/ACPI, F1:IDE; F2:HDAudio; F3:LPC; F4:PCIBridge; F5:USB */ - Package(){0x0014FFFF, 0, 0, 16 }, - Package(){0x0014FFFF, 1, 0, 17 }, - Package(){0x0014FFFF, 2, 0, 18 }, - Package(){0x0014FFFF, 3, 0, 19 }, - /* Package(){0x00140004, 2, 0, 18 }, */ - /* Package(){0x00140004, 3, 0, 19 }, */ - /* Package(){0x00140005, 1, 0, 17 }, */ - /* Package(){0x00140006, 1, 0, 17 }, */ - }) - - Name(PR1, Package(){ - /* Internal graphics - RS780 VGA, Bus1, Dev5 */ - Package(){0x0005FFFF, 0, INTA, 0 }, - Package(){0x0005FFFF, 1, INTB, 0 }, - Package(){0x0005FFFF, 2, INTC, 0 }, - Package(){0x0005FFFF, 3, INTD, 0 }, - }) - - Name(APR1, Package(){ - /* Internal graphics - RS780 VGA, Bus1, Dev5 */ - Package(){0x0005FFFF, 0, 0, 18 }, - Package(){0x0005FFFF, 1, 0, 19 }, - /* Package(){0x0005FFFF, 2, 0, 20 }, */ - /* Package(){0x0005FFFF, 3, 0, 17 }, */ - }) - - Name(PS2, Package(){ - /* The external GFX - Hooked to PCIe slot 2 */ - Package(){0x0000FFFF, 0, INTC, 0 }, - Package(){0x0000FFFF, 1, INTD, 0 }, - Package(){0x0000FFFF, 2, INTA, 0 }, - Package(){0x0000FFFF, 3, INTB, 0 }, - }) - - Name(APS2, Package(){ - /* The external GFX - Hooked to PCIe slot 2 */ - Package(){0x0000FFFF, 0, 0, 18 }, - Package(){0x0000FFFF, 1, 0, 19 }, - Package(){0x0000FFFF, 2, 0, 16 }, - Package(){0x0000FFFF, 3, 0, 17 }, - }) - - Name(PS4, Package(){ - /* PCIe slot - Hooked to PCIe slot 4 */ - Package(){0x0000FFFF, 0, INTA, 0 }, - Package(){0x0000FFFF, 1, INTB, 0 }, - Package(){0x0000FFFF, 2, INTC, 0 }, - Package(){0x0000FFFF, 3, INTD, 0 }, - }) - - Name(APS4, Package(){ - /* PCIe slot - Hooked to PCIe slot 4 */ - Package(){0x0000FFFF, 0, 0, 16 }, - Package(){0x0000FFFF, 1, 0, 17 }, - Package(){0x0000FFFF, 2, 0, 18 }, - Package(){0x0000FFFF, 3, 0, 19 }, - }) - - Name(PS5, Package(){ - /* PCIe slot - Hooked to PCIe slot 5 */ - Package(){0x0000FFFF, 0, INTB, 0 }, - Package(){0x0000FFFF, 1, INTC, 0 }, - Package(){0x0000FFFF, 2, INTD, 0 }, - Package(){0x0000FFFF, 3, INTA, 0 }, - }) - - Name(APS5, Package(){ - /* PCIe slot - Hooked to PCIe slot 5 */ - Package(){0x0000FFFF, 0, 0, 17 }, - Package(){0x0000FFFF, 1, 0, 18 }, - Package(){0x0000FFFF, 2, 0, 19 }, - Package(){0x0000FFFF, 3, 0, 16 }, - }) - - Name(PS6, Package(){ - /* PCIe slot - Hooked to PCIe slot 6 */ - Package(){0x0000FFFF, 0, INTC, 0 }, - Package(){0x0000FFFF, 1, INTD, 0 }, - Package(){0x0000FFFF, 2, INTA, 0 }, - Package(){0x0000FFFF, 3, INTB, 0 }, - }) - - Name(APS6, Package(){ - /* PCIe slot - Hooked to PCIe slot 6 */ - Package(){0x0000FFFF, 0, 0, 18 }, - Package(){0x0000FFFF, 1, 0, 19 }, - Package(){0x0000FFFF, 2, 0, 16 }, - Package(){0x0000FFFF, 3, 0, 17 }, - }) - - Name(PS7, Package(){ - /* The onboard Ethernet chip - Hooked to PCIe slot 7 */ - Package(){0x0000FFFF, 0, INTD, 0 }, - Package(){0x0000FFFF, 1, INTA, 0 }, - Package(){0x0000FFFF, 2, INTB, 0 }, - Package(){0x0000FFFF, 3, INTC, 0 }, - }) - - Name(APS7, Package(){ - /* The onboard Ethernet chip - Hooked to PCIe slot 7 */ - Package(){0x0000FFFF, 0, 0, 19 }, - Package(){0x0000FFFF, 1, 0, 16 }, - Package(){0x0000FFFF, 2, 0, 17 }, - Package(){0x0000FFFF, 3, 0, 18 }, - }) - Name(PS9, Package(){ - /* PCIe slot - Hooked to PCIe slot 9 */ - Package(){0x0000FFFF, 0, INTD, 0 }, - Package(){0x0000FFFF, 1, INTA, 0 }, - Package(){0x0000FFFF, 2, INTB, 0 }, - Package(){0x0000FFFF, 3, INTC, 0 }, - }) - - Name(APS9, Package(){ - /* PCIe slot - Hooked to PCIe slot 9 */ - Package(){0x0000FFFF, 0, 0, 17 }, - Package(){0x0000FFFF, 1, 0, 18 }, - Package(){0x0000FFFF, 2, 0, 19 }, - Package(){0x0000FFFF, 3, 0, 16 }, - }) - Name(PSa, Package(){ - /* PCIe slot - Hooked to PCIe slot 10 */ - Package(){0x0000FFFF, 0, INTD, 0 }, - Package(){0x0000FFFF, 1, INTA, 0 }, - Package(){0x0000FFFF, 2, INTB, 0 }, - Package(){0x0000FFFF, 3, INTC, 0 }, - }) - - Name(APSa, Package(){ - /* PCIe slot - Hooked to PCIe slot 10 */ - Package(){0x0000FFFF, 0, 0, 18 }, - Package(){0x0000FFFF, 1, 0, 19 }, - Package(){0x0000FFFF, 2, 0, 16 }, - Package(){0x0000FFFF, 3, 0, 17 }, - }) - - Name(PCIB, Package(){ - /* PCI slots: slot 0, slot 1, slot 2 behind Dev14, Fun4. */ - Package(){0x0005FFFF, 0, 0, 0x14 }, - Package(){0x0005FFFF, 1, 0, 0x15 }, - Package(){0x0005FFFF, 2, 0, 0x16 }, - Package(){0x0005FFFF, 3, 0, 0x17 }, - Package(){0x0006FFFF, 0, 0, 0x15 }, - Package(){0x0006FFFF, 1, 0, 0x16 }, - Package(){0x0006FFFF, 2, 0, 0x17 }, - Package(){0x0006FFFF, 3, 0, 0x14 }, - Package(){0x0007FFFF, 0, 0, 0x16 }, - Package(){0x0007FFFF, 1, 0, 0x17 }, - Package(){0x0007FFFF, 2, 0, 0x14 }, - Package(){0x0007FFFF, 3, 0, 0x15 }, - }) -} diff --git a/src/mainboard/jetway/pa78vm5/acpi/sata.asl b/src/mainboard/jetway/pa78vm5/acpi/sata.asl deleted file mode 100644 index 06b9b85a36..0000000000 --- a/src/mainboard/jetway/pa78vm5/acpi/sata.asl +++ /dev/null @@ -1,145 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2010 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -/* simple name description */ - -/* -Scope (_SB) { - Device(PCI0) { - Device(SATA) { - Name(_ADR, 0x00120000) - #include "sata.asl" - } - } -} -*/ - -Name(STTM, Buffer(20) { - 0x78, 0x00, 0x00, 0x00, 0x0f, 0x00, 0x00, 0x00, - 0x78, 0x00, 0x00, 0x00, 0x0f, 0x00, 0x00, 0x00, - 0x1f, 0x00, 0x00, 0x00 -}) - -/* Start by clearing the PhyRdyChg bits */ -Method(_INI) { - \_GPE._L1F() -} - -Device(PMRY) -{ - Name(_ADR, 0) - Method(_GTM, 0x0, NotSerialized) { - Return(STTM) - } - Method(_STM, 0x3, NotSerialized) {} - - Device(PMST) { - Name(_ADR, 0) - Method(_STA,0) { - if (LGreater(P0IS,0)) { - return (0x0F) /* sata is visible */ - } - else { - return (0x00) /* sata is missing */ - } - } - }/* end of PMST */ - - Device(PSLA) - { - Name(_ADR, 1) - Method(_STA,0) { - if (LGreater(P1IS,0)) { - return (0x0F) /* sata is visible */ - } - else { - return (0x00) /* sata is missing */ - } - } - } /* end of PSLA */ -} /* end of PMRY */ - - -Device(SEDY) -{ - Name(_ADR, 1) /* IDE Scondary Channel */ - Method(_GTM, 0x0, NotSerialized) { - Return(STTM) - } - Method(_STM, 0x3, NotSerialized) {} - - Device(SMST) - { - Name(_ADR, 0) - Method(_STA,0) { - if (LGreater(P2IS,0)) { - return (0x0F) /* sata is visible */ - } - else { - return (0x00) /* sata is missing */ - } - } - } /* end of SMST */ - - Device(SSLA) - { - Name(_ADR, 1) - Method(_STA,0) { - if (LGreater(P3IS,0)) { - return (0x0F) /* sata is visible */ - } - else { - return (0x00) /* sata is missing */ - } - } - } /* end of SSLA */ -} /* end of SEDY */ - -/* SATA Hot Plug Support */ -Scope(\_GPE) { - Method(_L1F,0x0,NotSerialized) { - if (\_SB.P0PR) { - if (LGreater(\_SB.P0IS,0)) { - sleep(32) - } - Notify(\_SB.PCI0.STCR.PMRY.PMST, 0x01) /* NOTIFY_DEVICE_CHECK */ - store(one, \_SB.P0PR) - } - - if (\_SB.P1PR) { - if (LGreater(\_SB.P1IS,0)) { - sleep(32) - } - Notify(\_SB.PCI0.STCR.PMRY.PSLA, 0x01) /* NOTIFY_DEVICE_CHECK */ - store(one, \_SB.P1PR) - } - - if (\_SB.P2PR) { - if (LGreater(\_SB.P2IS,0)) { - sleep(32) - } - Notify(\_SB.PCI0.STCR.SEDY.SMST, 0x01) /* NOTIFY_DEVICE_CHECK */ - store(one, \_SB.P2PR) - } - - if (\_SB.P3PR) { - if (LGreater(\_SB.P3IS,0)) { - sleep(32) - } - Notify(\_SB.PCI0.STCR.SEDY.SSLA, 0x01) /* NOTIFY_DEVICE_CHECK */ - store(one, \_SB.P3PR) - } - } -} diff --git a/src/mainboard/jetway/pa78vm5/acpi/usb.asl b/src/mainboard/jetway/pa78vm5/acpi/usb.asl deleted file mode 100644 index a3ccb97ff9..0000000000 --- a/src/mainboard/jetway/pa78vm5/acpi/usb.asl +++ /dev/null @@ -1,158 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2010 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -/* simple name description */ -/* -#include -DefinitionBlock ("DSDT.AML", "DSDT", 0x01, OEM_ID, ACPI_TABLE_CREATOR, 0x00010001 - ) - { - #include "usb.asl" - } -*/ -Method(UCOC, 0) { - Sleep(20) - Store(0x13,CMTI) - Store(0,GPSL) -} - -/* USB Port 0 overcurrent uses Gpm 0 */ -If(LLessEqual(UOM0,9)) { - Scope (\_GPE) { - Method (_L13) { - UCOC() - if(LEqual(GPB0,PLC0)) { - Not(PLC0,PLC0) - Store(PLC0, \_SB.PT0D) - } - } - } -} - -/* USB Port 1 overcurrent uses Gpm 1 */ -If (LLessEqual(UOM1,9)) { - Scope (\_GPE) { - Method (_L14) { - UCOC() - if (LEqual(GPB1,PLC1)) { - Not(PLC1,PLC1) - Store(PLC1, \_SB.PT1D) - } - } - } -} - -/* USB Port 2 overcurrent uses Gpm 2 */ -If (LLessEqual(UOM2,9)) { - Scope (\_GPE) { - Method (_L15) { - UCOC() - if (LEqual(GPB2,PLC2)) { - Not(PLC2,PLC2) - Store(PLC2, \_SB.PT2D) - } - } - } -} - -/* USB Port 3 overcurrent uses Gpm 3 */ -If (LLessEqual(UOM3,9)) { - Scope (\_GPE) { - Method (_L16) { - UCOC() - if (LEqual(GPB3,PLC3)) { - Not(PLC3,PLC3) - Store(PLC3, \_SB.PT3D) - } - } - } -} - -/* USB Port 4 overcurrent uses Gpm 4 */ -If (LLessEqual(UOM4,9)) { - Scope (\_GPE) { - Method (_L19) { - UCOC() - if (LEqual(GPB4,PLC4)) { - Not(PLC4,PLC4) - Store(PLC4, \_SB.PT4D) - } - } - } -} - -/* USB Port 5 overcurrent uses Gpm 5 */ -If (LLessEqual(UOM5,9)) { - Scope (\_GPE) { - Method (_L1A) { - UCOC() - if (LEqual(GPB5,PLC5)) { - Not(PLC5,PLC5) - Store(PLC5, \_SB.PT5D) - } - } - } -} - -/* USB Port 6 overcurrent uses Gpm 6 */ -If (LLessEqual(UOM6,9)) { - Scope (\_GPE) { - /* Method (_L1C) { */ - Method (_L06) { - UCOC() - if (LEqual(GPB6,PLC6)) { - Not(PLC6,PLC6) - Store(PLC6, \_SB.PT6D) - } - } - } -} - -/* USB Port 7 overcurrent uses Gpm 7 */ -If (LLessEqual(UOM7,9)) { - Scope (\_GPE) { - /* Method (_L1D) { */ - Method (_L07) { - UCOC() - if (LEqual(GPB7,PLC7)) { - Not(PLC7,PLC7) - Store(PLC7, \_SB.PT7D) - } - } - } -} - -/* USB Port 8 overcurrent uses Gpm 8 */ -If (LLessEqual(UOM8,9)) { - Scope (\_GPE) { - Method (_L17) { - if (LEqual(G8IS,PLC8)) { - Not(PLC8,PLC8) - Store(PLC8, \_SB.PT8D) - } - } - } -} - -/* USB Port 9 overcurrent uses Gpm 9 */ -If (LLessEqual(UOM9,9)) { - Scope (\_GPE) { - Method (_L0E) { - if (LEqual(G9IS,0)) { - Store(1,\_SB.PT9D) - } - } - } -} diff --git a/src/mainboard/jetway/pa78vm5/acpi_tables.c b/src/mainboard/jetway/pa78vm5/acpi_tables.c deleted file mode 100644 index 92e711866f..0000000000 --- a/src/mainboard/jetway/pa78vm5/acpi_tables.c +++ /dev/null @@ -1,45 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2010 Wang Qing Pei - * Copyright (C) 2010 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include -#include - -unsigned long acpi_fill_madt(unsigned long current) -{ - /* create all subtables for processors */ - current = acpi_create_madt_lapics(current); - - /* Write SB700 IOAPIC, only one */ - current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, 2, - IO_APIC_ADDR, 0); - - current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) - current, 0, 0, 2, 0); - current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) - current, 0, 9, 9, 0xF); - /* 0: mean bus 0--->ISA */ - /* 0: PIC 0 */ - /* 2: APIC 2 */ - /* 5 mean: 0101 --> Edge-triggered, Active high */ - - /* create all subtables for processors */ - /* current = acpi_create_madt_lapic_nmis(current, 5, 1); */ - /* 1: LINT1 connect to NMI */ - - return current; -} diff --git a/src/mainboard/jetway/pa78vm5/board_info.txt b/src/mainboard/jetway/pa78vm5/board_info.txt deleted file mode 100644 index f1368cf532..0000000000 --- a/src/mainboard/jetway/pa78vm5/board_info.txt +++ /dev/null @@ -1,3 +0,0 @@ -Category: desktop -Board URL: http://www.jetway.com.tw/jw/motherboard_view.asp?productid=567&proname=PA78VM5 -Release year: 2009 diff --git a/src/mainboard/jetway/pa78vm5/cmos.layout b/src/mainboard/jetway/pa78vm5/cmos.layout deleted file mode 100644 index 6c3d3f6c9e..0000000000 --- a/src/mainboard/jetway/pa78vm5/cmos.layout +++ /dev/null @@ -1,52 +0,0 @@ -entries - -0 384 r 0 reserved_memory -384 1 e 4 boot_option -388 4 h 0 reboot_counter -#392 3 r 0 unused -395 1 e 1 hw_scrubber -396 1 e 1 interleave_chip_selects -397 2 e 8 max_mem_clock -399 1 e 2 multi_core -400 1 e 1 power_on_after_fail -412 4 e 6 debug_level -440 4 e 9 slow_cpu -444 1 e 1 nmi -445 1 e 1 gart -456 1 e 1 ECC_memory -728 256 h 0 user_data -984 16 h 0 check_sum -# Reserve the extended AMD configuration registers -1000 24 r 0 amd_reserved - - - -enumerations - -#ID value text -1 0 Disable -1 1 Enable -2 0 Enable -2 1 Disable -4 0 Fallback -4 1 Normal -6 5 Notice -6 6 Info -6 7 Debug -6 8 Spew -8 0 400Mhz -8 1 333Mhz -8 2 266Mhz -8 3 200Mhz -9 0 off -9 1 87.5% -9 2 75.0% -9 3 62.5% -9 4 50.0% -9 5 37.5% -9 6 25.0% -9 7 12.5% - -checksums - -checksum 392 983 984 diff --git a/src/mainboard/jetway/pa78vm5/devicetree.cb b/src/mainboard/jetway/pa78vm5/devicetree.cb deleted file mode 100644 index 79915ac26b..0000000000 --- a/src/mainboard/jetway/pa78vm5/devicetree.cb +++ /dev/null @@ -1,110 +0,0 @@ -# sample config for jetway/PA78VM5 -chip northbridge/amd/amdfam10/root_complex - device cpu_cluster 0 on - chip cpu/amd/socket_AM2r2 #L1 and DDR2 - device lapic 0 on end - end - end - device domain 0 on - subsystemid 0x1022 0x3060 inherit - chip northbridge/amd/amdfam10 - device pci 18.0 on # northbridge - chip southbridge/amd/rs780 - device pci 0.0 on end # HT 0x9600 - device pci 1.0 on end # Internal Graphics P2P bridge 0x9602 - device pci 2.0 on end # PCIE P2P bridge (external graphics) 0x9603 - device pci 3.0 on end # PCIE P2P bridge 0x960b - device pci 4.0 on end # PCIE P2P bridge 0x9604 - device pci 5.0 off end # PCIE P2P bridge 0x9605 - device pci 6.0 off end # PCIE P2P bridge 0x9606 - device pci 7.0 off end # PCIE P2P bridge 0x9607 - device pci 8.0 off end # NB/SB Link P2P bridge - device pci 9.0 on end # - device pci a.0 on end # - register "gppsb_configuration" = "1" # Configuration B - register "gpp_configuration" = "3" # Configuration D default - register "port_enable" = "0x6fc" - register "gfx_dev2_dev3" = "1" - register "gfx_dual_slot" = "1" - register "gfx_lane_reversal" = "0" - register "gfx_tmds" = "0" - register "gfx_compliance" = "0" - register "gfx_reconfiguration" = "1" - register "gfx_link_width" = "0" - end - chip southbridge/amd/sb700 # it is under NB/SB Link, but on the same pri bus - device pci 11.0 on end # SATA - device pci 12.0 on end # USB - device pci 12.1 on end # USB - device pci 12.2 on end # USB - device pci 13.0 on end # USB - device pci 13.1 on end # USB - device pci 13.2 on end # USB - device pci 14.0 on # SM - chip drivers/generic/generic #dimm 0-0-0 - device i2c 50 on end - end - chip drivers/generic/generic #dimm 0-0-1 - device i2c 51 on end - end - end # SM - device pci 14.1 on end # IDE 0x439c - device pci 14.2 on end # HDA 0x4383 - device pci 14.3 on # LPC 0x439d - chip superio/fintek/f71863fg - device pnp 2e.0 off # Floppy - io 0x60 = 0x3f0 - irq 0x70 = 6 - drq 0x74 = 2 - end - device pnp 2e.1 on # Com1 - io 0x60 = 0x3f8 - irq 0x70 = 4 - end - device pnp 2e.2 off # Com2 - io 0x60 = 0x2f8 - irq 0x70 = 3 - end - device pnp 2e.3 off # Parallel Port - io 0x60 = 0x378 - irq 0x70 = 7 - end - device pnp 2e.4 off end # EC - device pnp 2e.5 on # Keyboard - io 0x60 = 0x60 - io 0x62 = 0x64 - irq 0x70 = 1 - end - device pnp 2e.6 on # Mouse - irq 0x70 = 12 - end - device pnp 2e.7 off # GPIO, must be closed for unresolved reason. - end - device pnp 2e.8 off # MIDI - io 0x60 = 0x300 - irq 0x70 = 9 - end - device pnp 2e.9 off # GAME - io 0x60 = 0x220 - end - device pnp 2e.a off end # CIR - end #superio/ite/it8718f - end #LPC - device pci 14.4 on end # PCI 0x4384 - device pci 14.5 on end # USB 2 - register "boot_switch_sata_ide" = "0" # 0: boot from SATA. 1: IDE - end #southbridge/amd/sb700 - end # device pci 18.0 - - device pci 18.0 on end - device pci 18.0 on end - device pci 18.1 on end - device pci 18.2 on end - device pci 18.3 on end - device pci 18.4 on end -# device pci 00.5 on end - end - end #domain - #for node 32 to node 63 - -end diff --git a/src/mainboard/jetway/pa78vm5/dsdt.asl b/src/mainboard/jetway/pa78vm5/dsdt.asl deleted file mode 100644 index 89120c7b02..0000000000 --- a/src/mainboard/jetway/pa78vm5/dsdt.asl +++ /dev/null @@ -1,1718 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2010 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -/* DefinitionBlock Statement */ -#include -DefinitionBlock ( - "DSDT.AML", /* Output filename */ - "DSDT", /* Signature */ - 0x02, /* DSDT Revision, needs to be 2 for 64bit */ - OEM_ID, - ACPI_TABLE_CREATOR, - 0x00010001 /* OEM Revision */ - ) -{ /* Start of ASL file */ - /* #include */ /* Include global debug methods if needed */ - - /* Data to be patched by the BIOS during POST */ - /* FIXME the patching is not done yet! */ - /* Memory related values */ - Name(LOMH, 0x0) /* Start of unused memory in C0000-E0000 range */ - Name(PBAD, 0x0) /* Address of BIOS area (If TOM2 != 0, Addr >> 16) */ - Name(PBLN, 0x0) /* Length of BIOS area */ - - Name(PCBA, 0xE0000000) /* Base address of PCIe config space */ - Name(HPBA, 0xFED00000) /* Base address of HPET table */ - - /* USB overcurrent mapping pins. */ - Name(UOM0, 0) - Name(UOM1, 2) - Name(UOM2, 0) - Name(UOM3, 7) - Name(UOM4, 2) - Name(UOM5, 2) - Name(UOM6, 6) - Name(UOM7, 2) - Name(UOM8, 6) - Name(UOM9, 6) - - /* Some global data */ - Name(OSVR, 3) /* Assume nothing. WinXp = 1, Vista = 2, Linux = 3, WinCE = 4 */ - Name(OSV, Ones) /* Assume nothing */ - Name(PMOD, One) /* Assume APIC */ - - /* - * Processor Object - * - */ - Scope (\_PR) { /* define processor scope */ - Device (CPU0) { - Name (_HID, "ACPI0007") - Name (_UID, 0) - #include "acpi/cpstate.asl" - } - Device (CPU1) { - Name (_HID, "ACPI0007") - Name (_UID, 1) - #include "acpi/cpstate.asl" - } - Device (CPU2) { - Name (_HID, "ACPI0007") - Name (_UID, 2) - #include "acpi/cpstate.asl" - } - Device (CPU3) { - Name (_HID, "ACPI0007") - Name (_UID, 3) - #include "acpi/cpstate.asl" - } - } /* End _PR scope */ - - /* PIC IRQ mapping registers, C00h-C01h */ - OperationRegion(PRQM, SystemIO, 0x00000C00, 0x00000002) - Field(PRQM, ByteAcc, NoLock, Preserve) { - PRQI, 0x00000008, - PRQD, 0x00000008, /* Offset: 1h */ - } - IndexField(PRQI, PRQD, ByteAcc, NoLock, Preserve) { - PINA, 0x00000008, /* Index 0 */ - PINB, 0x00000008, /* Index 1 */ - PINC, 0x00000008, /* Index 2 */ - PIND, 0x00000008, /* Index 3 */ - AINT, 0x00000008, /* Index 4 */ - SINT, 0x00000008, /* Index 5 */ - , 0x00000008, /* Index 6 */ - AAUD, 0x00000008, /* Index 7 */ - AMOD, 0x00000008, /* Index 8 */ - PINE, 0x00000008, /* Index 9 */ - PINF, 0x00000008, /* Index A */ - PING, 0x00000008, /* Index B */ - PINH, 0x00000008, /* Index C */ - } - - /* PCI Error control register */ - OperationRegion(PERC, SystemIO, 0x00000C14, 0x00000001) - Field(PERC, ByteAcc, NoLock, Preserve) { - SENS, 0x00000001, - PENS, 0x00000001, - SENE, 0x00000001, - PENE, 0x00000001, - } - - /* Client Management index/data registers */ - OperationRegion(CMT, SystemIO, 0x00000C50, 0x00000002) - Field(CMT, ByteAcc, NoLock, Preserve) { - CMTI, 8, - /* Client Management Data register */ - G64E, 1, - G64O, 1, - G32O, 2, - , 2, - GPSL, 2, - } - - /* GPM Port register */ - OperationRegion(GPT, SystemIO, 0x00000C52, 0x00000001) - Field(GPT, ByteAcc, NoLock, Preserve) { - GPB0,1, - GPB1,1, - GPB2,1, - GPB3,1, - GPB4,1, - GPB5,1, - GPB6,1, - GPB7,1, - } - - /* Flash ROM program enable register */ - OperationRegion(FRE, SystemIO, 0x00000C6F, 0x00000001) - Field(FRE, ByteAcc, NoLock, Preserve) { - , 0x00000006, - FLRE, 0x00000001, - } - - /* PM2 index/data registers */ - OperationRegion(PM2R, SystemIO, 0x00000CD0, 0x00000002) - Field(PM2R, ByteAcc, NoLock, Preserve) { - PM2I, 0x00000008, - PM2D, 0x00000008, - } - - /* Power Management I/O registers */ - OperationRegion(PIOR, SystemIO, 0x00000CD6, 0x00000002) - Field(PIOR, ByteAcc, NoLock, Preserve) { - PIOI, 0x00000008, - PIOD, 0x00000008, - } - IndexField (PIOI, PIOD, ByteAcc, NoLock, Preserve) { - Offset(0x00), /* MiscControl */ - , 1, - T1EE, 1, - T2EE, 1, - Offset(0x01), /* MiscStatus */ - , 1, - T1E, 1, - T2E, 1, - Offset(0x04), /* SmiWakeUpEventEnable3 */ - , 7, - SSEN, 1, - Offset(0x07), /* SmiWakeUpEventStatus3 */ - , 7, - CSSM, 1, - Offset(0x10), /* AcpiEnable */ - , 6, - PWDE, 1, - Offset(0x1C), /* ProgramIoEnable */ - , 3, - MKME, 1, - IO3E, 1, - IO2E, 1, - IO1E, 1, - IO0E, 1, - Offset(0x1D), /* IOMonitorStatus */ - , 3, - MKMS, 1, - IO3S, 1, - IO2S, 1, - IO1S, 1, - IO0S,1, - Offset(0x20), /* AcpiPmEvtBlk */ - APEB, 16, - Offset(0x36), /* GEvtLevelConfig */ - , 6, - ELC6, 1, - ELC7, 1, - Offset(0x37), /* GPMLevelConfig0 */ - , 3, - PLC0, 1, - PLC1, 1, - PLC2, 1, - PLC3, 1, - PLC8, 1, - Offset(0x38), /* GPMLevelConfig1 */ - , 1, - PLC4, 1, - PLC5, 1, - , 1, - PLC6, 1, - PLC7, 1, - Offset(0x3B), /* PMEStatus1 */ - GP0S, 1, - GM4S, 1, - GM5S, 1, - APS, 1, - GM6S, 1, - GM7S, 1, - GP2S, 1, - STSS, 1, - Offset(0x55), /* SoftPciRst */ - SPRE, 1, - , 1, - , 1, - PNAT, 1, - PWMK, 1, - PWNS, 1, - - /* Offset(0x61), */ /* Options_1 */ - /* ,7, */ - /* R617,1, */ - - Offset(0x65), /* UsbPMControl */ - , 4, - URRE, 1, - Offset(0x68), /* MiscEnable68 */ - , 3, - TMTE, 1, - , 1, - Offset(0x92), /* GEVENTIN */ - , 7, - E7IS, 1, - Offset(0x96), /* GPM98IN */ - G8IS, 1, - G9IS, 1, - Offset(0x9A), /* EnhanceControl */ - ,7, - HPDE, 1, - Offset(0xA8), /* PIO7654Enable */ - IO4E, 1, - IO5E, 1, - IO6E, 1, - IO7E, 1, - Offset(0xA9), /* PIO7654Status */ - IO4S, 1, - IO5S, 1, - IO6S, 1, - IO7S, 1, - } - - /* PM1 Event Block - * First word is PM1_Status, Second word is PM1_Enable - */ - OperationRegion(P1EB, SystemIO, APEB, 0x04) - Field(P1EB, ByteAcc, NoLock, Preserve) { - TMST, 1, - , 3, - BMST, 1, - GBST, 1, - Offset(0x01), - PBST, 1, - , 1, - RTST, 1, - , 3, - PWST, 1, - SPWS, 1, - Offset(0x02), - TMEN, 1, - , 4, - GBEN, 1, - Offset(0x03), - PBEN, 1, - , 1, - RTEN, 1, - , 3, - PWDA, 1, - } - - Scope(\_SB) { - /* PCIe Configuration Space for 16 busses */ - OperationRegion(PCFG, SystemMemory, PCBA, 0x01000000) /* Each bus consumes 1MB */ - Field(PCFG, ByteAcc, NoLock, Preserve) { - /* Byte offsets are computed using the following technique: - * ((bus number + 1) * ((device number * 8) * 4096)) + register offset - * The 8 comes from 8 functions per device, and 4096 bytes per function config space - */ - Offset(0x00090024), /* Byte offset to SATA register 24h - Bus 0, Device 18, Function 0 */ - STB5, 32, - Offset(0x00098042), /* Byte offset to OHCI0 register 42h - Bus 0, Device 19, Function 0 */ - PT0D, 1, - PT1D, 1, - PT2D, 1, - PT3D, 1, - PT4D, 1, - PT5D, 1, - PT6D, 1, - PT7D, 1, - PT8D, 1, - PT9D, 1, - Offset(0x000A0004), /* Byte offset to SMBUS register 4h - Bus 0, Device 20, Function 0 */ - SBIE, 1, - SBME, 1, - Offset(0x000A0008), /* Byte offset to SMBUS register 8h - Bus 0, Device 20, Function 0 */ - SBRI, 8, - Offset(0x000A0014), /* Byte offset to SMBUS register 14h - Bus 0, Device 20, Function 0 */ - SBB1, 32, - Offset(0x000A0078), /* Byte offset to SMBUS register 78h - Bus 0, Device 20, Function 0 */ - ,14, - P92E, 1, /* Port92 decode enable */ - } - - OperationRegion(SB5, SystemMemory, STB5, 0x1000) - Field(SB5, AnyAcc, NoLock, Preserve){ - /* Port 0 */ - Offset(0x120), /* Port 0 Task file status */ - P0ER, 1, - , 2, - P0DQ, 1, - , 3, - P0BY, 1, - Offset(0x128), /* Port 0 Serial ATA status */ - P0DD, 4, - , 4, - P0IS, 4, - Offset(0x12C), /* Port 0 Serial ATA control */ - P0DI, 4, - Offset(0x130), /* Port 0 Serial ATA error */ - , 16, - P0PR, 1, - - /* Port 1 */ - offset(0x1A0), /* Port 1 Task file status */ - P1ER, 1, - , 2, - P1DQ, 1, - , 3, - P1BY, 1, - Offset(0x1A8), /* Port 1 Serial ATA status */ - P1DD, 4, - , 4, - P1IS, 4, - Offset(0x1AC), /* Port 1 Serial ATA control */ - P1DI, 4, - Offset(0x1B0), /* Port 1 Serial ATA error */ - , 16, - P1PR, 1, - - /* Port 2 */ - Offset(0x220), /* Port 2 Task file status */ - P2ER, 1, - , 2, - P2DQ, 1, - , 3, - P2BY, 1, - Offset(0x228), /* Port 2 Serial ATA status */ - P2DD, 4, - , 4, - P2IS, 4, - Offset(0x22C), /* Port 2 Serial ATA control */ - P2DI, 4, - Offset(0x230), /* Port 2 Serial ATA error */ - , 16, - P2PR, 1, - - /* Port 3 */ - Offset(0x2A0), /* Port 3 Task file status */ - P3ER, 1, - , 2, - P3DQ, 1, - , 3, - P3BY, 1, - Offset(0x2A8), /* Port 3 Serial ATA status */ - P3DD, 4, - , 4, - P3IS, 4, - Offset(0x2AC), /* Port 3 Serial ATA control */ - P3DI, 4, - Offset(0x2B0), /* Port 3 Serial ATA error */ - , 16, - P3PR, 1, - } - } - - - #include "acpi/routing.asl" - - Scope(\_SB) { - - Method(OSFL, 0){ - - if(LNotEqual(OSVR, Ones)) {Return(OSVR)} /* OS version was already detected */ - - if(CondRefOf(\_OSI)) - { - Store(1, OSVR) /* Assume some form of XP */ - if (\_OSI("Windows 2006")) /* Vista */ - { - Store(2, OSVR) - } - } else { - If(WCMP(\_OS,"Linux")) { - Store(3, OSVR) /* Linux */ - } Else { - Store(4, OSVR) /* Gotta be WinCE */ - } - } - Return(OSVR) - } - - Method(_PIC, 0x01, NotSerialized) - { - If (Arg0) - { - \_SB.CIRQ() - } - Store(Arg0, PMOD) - } - Method(CIRQ, 0x00, NotSerialized){ - Store(0, PINA) - Store(0, PINB) - Store(0, PINC) - Store(0, PIND) - Store(0, PINE) - Store(0, PINF) - Store(0, PING) - Store(0, PINH) - } - - Name(IRQB, ResourceTemplate(){ - IRQ(Level,ActiveLow,Shared){15} - }) - - Name(IRQP, ResourceTemplate(){ - IRQ(Level,ActiveLow,Exclusive){3, 4, 5, 7, 10, 11, 12, 15} - }) - - Name(PITF, ResourceTemplate(){ - IRQ(Level,ActiveLow,Exclusive){9} - }) - - Device(INTA) { - Name(_HID, EISAID("PNP0C0F")) - Name(_UID, 1) - - Method(_STA, 0) { - if (PINA) { - Return(0x0B) /* sata is invisible */ - } else { - Return(0x09) /* sata is disabled */ - } - } /* End Method(_SB.INTA._STA) */ - - Method(_DIS ,0) { - /* DBGO("\\_SB\\LNKA\\_DIS\n") */ - Store(0, PINA) - } /* End Method(_SB.INTA._DIS) */ - - Method(_PRS ,0) { - /* DBGO("\\_SB\\LNKA\\_PRS\n") */ - Return(IRQP) - } /* Method(_SB.INTA._PRS) */ - - Method(_CRS ,0) { - /* DBGO("\\_SB\\LNKA\\_CRS\n") */ - CreateWordField(IRQB, 0x1, IRQN) - ShiftLeft(1, PINA, IRQN) - Return(IRQB) - } /* Method(_SB.INTA._CRS) */ - - Method(_SRS, 1) { - /* DBGO("\\_SB\\LNKA\\_CRS\n") */ - CreateWordField(ARG0, 1, IRQM) - - /* Use lowest available IRQ */ - FindSetRightBit(IRQM, Local0) - if (Local0) { - Decrement(Local0) - } - Store(Local0, PINA) - } /* End Method(_SB.INTA._SRS) */ - } /* End Device(INTA) */ - - Device(INTB) { - Name(_HID, EISAID("PNP0C0F")) - Name(_UID, 2) - - Method(_STA, 0) { - if (PINB) { - Return(0x0B) /* sata is invisible */ - } else { - Return(0x09) /* sata is disabled */ - } - } /* End Method(_SB.INTB._STA) */ - - Method(_DIS ,0) { - /* DBGO("\\_SB\\LNKB\\_DIS\n") */ - Store(0, PINB) - } /* End Method(_SB.INTB._DIS) */ - - Method(_PRS ,0) { - /* DBGO("\\_SB\\LNKB\\_PRS\n") */ - Return(IRQP) - } /* Method(_SB.INTB._PRS) */ - - Method(_CRS ,0) { - /* DBGO("\\_SB\\LNKB\\_CRS\n") */ - CreateWordField(IRQB, 0x1, IRQN) - ShiftLeft(1, PINB, IRQN) - Return(IRQB) - } /* Method(_SB.INTB._CRS) */ - - Method(_SRS, 1) { - /* DBGO("\\_SB\\LNKB\\_CRS\n") */ - CreateWordField(ARG0, 1, IRQM) - - /* Use lowest available IRQ */ - FindSetRightBit(IRQM, Local0) - if (Local0) { - Decrement(Local0) - } - Store(Local0, PINB) - } /* End Method(_SB.INTB._SRS) */ - } /* End Device(INTB) */ - - Device(INTC) { - Name(_HID, EISAID("PNP0C0F")) - Name(_UID, 3) - - Method(_STA, 0) { - if (PINC) { - Return(0x0B) /* sata is invisible */ - } else { - Return(0x09) /* sata is disabled */ - } - } /* End Method(_SB.INTC._STA) */ - - Method(_DIS ,0) { - /* DBGO("\\_SB\\LNKC\\_DIS\n") */ - Store(0, PINC) - } /* End Method(_SB.INTC._DIS) */ - - Method(_PRS ,0) { - /* DBGO("\\_SB\\LNKC\\_PRS\n") */ - Return(IRQP) - } /* Method(_SB.INTC._PRS) */ - - Method(_CRS ,0) { - /* DBGO("\\_SB\\LNKC\\_CRS\n") */ - CreateWordField(IRQB, 0x1, IRQN) - ShiftLeft(1, PINC, IRQN) - Return(IRQB) - } /* Method(_SB.INTC._CRS) */ - - Method(_SRS, 1) { - /* DBGO("\\_SB\\LNKC\\_CRS\n") */ - CreateWordField(ARG0, 1, IRQM) - - /* Use lowest available IRQ */ - FindSetRightBit(IRQM, Local0) - if (Local0) { - Decrement(Local0) - } - Store(Local0, PINC) - } /* End Method(_SB.INTC._SRS) */ - } /* End Device(INTC) */ - - Device(INTD) { - Name(_HID, EISAID("PNP0C0F")) - Name(_UID, 4) - - Method(_STA, 0) { - if (PIND) { - Return(0x0B) /* sata is invisible */ - } else { - Return(0x09) /* sata is disabled */ - } - } /* End Method(_SB.INTD._STA) */ - - Method(_DIS ,0) { - /* DBGO("\\_SB\\LNKD\\_DIS\n") */ - Store(0, PIND) - } /* End Method(_SB.INTD._DIS) */ - - Method(_PRS ,0) { - /* DBGO("\\_SB\\LNKD\\_PRS\n") */ - Return(IRQP) - } /* Method(_SB.INTD._PRS) */ - - Method(_CRS ,0) { - /* DBGO("\\_SB\\LNKD\\_CRS\n") */ - CreateWordField(IRQB, 0x1, IRQN) - ShiftLeft(1, PIND, IRQN) - Return(IRQB) - } /* Method(_SB.INTD._CRS) */ - - Method(_SRS, 1) { - /* DBGO("\\_SB\\LNKD\\_CRS\n") */ - CreateWordField(ARG0, 1, IRQM) - - /* Use lowest available IRQ */ - FindSetRightBit(IRQM, Local0) - if (Local0) { - Decrement(Local0) - } - Store(Local0, PIND) - } /* End Method(_SB.INTD._SRS) */ - } /* End Device(INTD) */ - - Device(INTE) { - Name(_HID, EISAID("PNP0C0F")) - Name(_UID, 5) - - Method(_STA, 0) { - if (PINE) { - Return(0x0B) /* sata is invisible */ - } else { - Return(0x09) /* sata is disabled */ - } - } /* End Method(_SB.INTE._STA) */ - - Method(_DIS ,0) { - /* DBGO("\\_SB\\LNKE\\_DIS\n") */ - Store(0, PINE) - } /* End Method(_SB.INTE._DIS) */ - - Method(_PRS ,0) { - /* DBGO("\\_SB\\LNKE\\_PRS\n") */ - Return(IRQP) - } /* Method(_SB.INTE._PRS) */ - - Method(_CRS ,0) { - /* DBGO("\\_SB\\LNKE\\_CRS\n") */ - CreateWordField(IRQB, 0x1, IRQN) - ShiftLeft(1, PINE, IRQN) - Return(IRQB) - } /* Method(_SB.INTE._CRS) */ - - Method(_SRS, 1) { - /* DBGO("\\_SB\\LNKE\\_CRS\n") */ - CreateWordField(ARG0, 1, IRQM) - - /* Use lowest available IRQ */ - FindSetRightBit(IRQM, Local0) - if (Local0) { - Decrement(Local0) - } - Store(Local0, PINE) - } /* End Method(_SB.INTE._SRS) */ - } /* End Device(INTE) */ - - Device(INTF) { - Name(_HID, EISAID("PNP0C0F")) - Name(_UID, 6) - - Method(_STA, 0) { - if (PINF) { - Return(0x0B) /* sata is invisible */ - } else { - Return(0x09) /* sata is disabled */ - } - } /* End Method(_SB.INTF._STA) */ - - Method(_DIS ,0) { - /* DBGO("\\_SB\\LNKF\\_DIS\n") */ - Store(0, PINF) - } /* End Method(_SB.INTF._DIS) */ - - Method(_PRS ,0) { - /* DBGO("\\_SB\\LNKF\\_PRS\n") */ - Return(PITF) - } /* Method(_SB.INTF._PRS) */ - - Method(_CRS ,0) { - /* DBGO("\\_SB\\LNKF\\_CRS\n") */ - CreateWordField(IRQB, 0x1, IRQN) - ShiftLeft(1, PINF, IRQN) - Return(IRQB) - } /* Method(_SB.INTF._CRS) */ - - Method(_SRS, 1) { - /* DBGO("\\_SB\\LNKF\\_CRS\n") */ - CreateWordField(ARG0, 1, IRQM) - - /* Use lowest available IRQ */ - FindSetRightBit(IRQM, Local0) - if (Local0) { - Decrement(Local0) - } - Store(Local0, PINF) - } /* End Method(_SB.INTF._SRS) */ - } /* End Device(INTF) */ - - Device(INTG) { - Name(_HID, EISAID("PNP0C0F")) - Name(_UID, 7) - - Method(_STA, 0) { - if (PING) { - Return(0x0B) /* sata is invisible */ - } else { - Return(0x09) /* sata is disabled */ - } - } /* End Method(_SB.INTG._STA) */ - - Method(_DIS ,0) { - /* DBGO("\\_SB\\LNKG\\_DIS\n") */ - Store(0, PING) - } /* End Method(_SB.INTG._DIS) */ - - Method(_PRS ,0) { - /* DBGO("\\_SB\\LNKG\\_PRS\n") */ - Return(IRQP) - } /* Method(_SB.INTG._CRS) */ - - Method(_CRS ,0) { - /* DBGO("\\_SB\\LNKG\\_CRS\n") */ - CreateWordField(IRQB, 0x1, IRQN) - ShiftLeft(1, PING, IRQN) - Return(IRQB) - } /* Method(_SB.INTG._CRS) */ - - Method(_SRS, 1) { - /* DBGO("\\_SB\\LNKG\\_CRS\n") */ - CreateWordField(ARG0, 1, IRQM) - - /* Use lowest available IRQ */ - FindSetRightBit(IRQM, Local0) - if (Local0) { - Decrement(Local0) - } - Store(Local0, PING) - } /* End Method(_SB.INTG._SRS) */ - } /* End Device(INTG) */ - - Device(INTH) { - Name(_HID, EISAID("PNP0C0F")) - Name(_UID, 8) - - Method(_STA, 0) { - if (PINH) { - Return(0x0B) /* sata is invisible */ - } else { - Return(0x09) /* sata is disabled */ - } - } /* End Method(_SB.INTH._STA) */ - - Method(_DIS ,0) { - /* DBGO("\\_SB\\LNKH\\_DIS\n") */ - Store(0, PINH) - } /* End Method(_SB.INTH._DIS) */ - - Method(_PRS ,0) { - /* DBGO("\\_SB\\LNKH\\_PRS\n") */ - Return(IRQP) - } /* Method(_SB.INTH._CRS) */ - - Method(_CRS ,0) { - /* DBGO("\\_SB\\LNKH\\_CRS\n") */ - CreateWordField(IRQB, 0x1, IRQN) - ShiftLeft(1, PINH, IRQN) - Return(IRQB) - } /* Method(_SB.INTH._CRS) */ - - Method(_SRS, 1) { - /* DBGO("\\_SB\\LNKH\\_CRS\n") */ - CreateWordField(ARG0, 1, IRQM) - - /* Use lowest available IRQ */ - FindSetRightBit(IRQM, Local0) - if (Local0) { - Decrement(Local0) - } - Store(Local0, PINH) - } /* End Method(_SB.INTH._SRS) */ - } /* End Device(INTH) */ - - } /* End Scope(_SB) */ - - #include - - /* Wake status package */ - Name(WKST,Package(){Zero, Zero}) - - /* - * \_PTS - Prepare to Sleep method - * - * Entry: - * Arg0=The value of the sleeping state S1=1, S2=2, etc - * - * Exit: - * -none- - * - * The _PTS control method is executed at the beginning of the sleep process - * for S1-S5. The sleeping value is passed to the _PTS control method. This - * control method may be executed a relatively long time before entering the - * sleep state and the OS may abort the operation without notification to - * the ACPI driver. This method cannot modify the configuration or power - * state of any device in the system. - */ - Method(\_PTS, 1) { - /* DBGO("\\_PTS\n") */ - /* DBGO("From S0 to S") */ - /* DBGO(Arg0) */ - /* DBGO("\n") */ - - /* Don't allow PCIRST# to reset USB */ - if (LEqual(Arg0,3)){ - Store(0,URRE) - } - - /* Clear sleep SMI status flag and enable sleep SMI trap. */ - /*Store(One, CSSM) - Store(One, SSEN)*/ - - /* On older chips, clear PciExpWakeDisEn */ - /*if (LLessEqual(\_SB.SBRI, 0x13)) { - * Store(0,\_SB.PWDE) - *} - */ - - /* Clear wake status structure. */ - Store(0, Index(WKST,0)) - Store(0, Index(WKST,1)) - \_SB.PCI0.SIOS (Arg0) - } /* End Method(\_PTS) */ - - /* - * The following method results in a "not a valid reserved NameSeg" - * warning so I have commented it out for the duration. It isn't - * used, so it could be removed. - * - * - * \_GTS OEM Going To Sleep method - * - * Entry: - * Arg0=The value of the sleeping state S1=1, S2=2 - * - * Exit: - * -none- - * - * Method(\_GTS, 1) { - * DBGO("\\_GTS\n") - * DBGO("From S0 to S") - * DBGO(Arg0) - * DBGO("\n") - * } - */ - - /* - * \_BFS OEM Back From Sleep method - * - * Entry: - * Arg0=The value of the sleeping state S1=1, S2=2 - * - * Exit: - * -none- - */ - Method(\_BFS, 1) { - /* DBGO("\\_BFS\n") */ - /* DBGO("From S") */ - /* DBGO(Arg0) */ - /* DBGO(" to S0\n") */ - } - - /* - * \_WAK System Wake method - * - * Entry: - * Arg0=The value of the sleeping state S1=1, S2=2 - * - * Exit: - * Return package of 2 DWords - * Dword 1 - Status - * 0x00000000 wake succeeded - * 0x00000001 Wake was signaled but failed due to lack of power - * 0x00000002 Wake was signaled but failed due to thermal condition - * Dword 2 - Power Supply state - * if non-zero the effective S-state the power supply entered - */ - Method(\_WAK, 1) { - /* DBGO("\\_WAK\n") */ - /* DBGO("From S") */ - /* DBGO(Arg0) */ - /* DBGO(" to S0\n") */ - - /* Re-enable HPET */ - Store(1,HPDE) - - /* Restore PCIRST# so it resets USB */ - if (LEqual(Arg0,3)){ - Store(1,URRE) - } - - /* Arbitrarily clear PciExpWakeStatus */ - Store(PWST, Local1) - Store(Local1, PWST) - - /* if (DeRefOf(Index(WKST,0))) { - * Store(0, Index(WKST,1)) - * } else { - * Store(Arg0, Index(WKST,1)) - * } - */ - \_SB.PCI0.SIOW () - Return(WKST) - } /* End Method(\_WAK) */ - - Scope(\_GPE) { /* Start Scope GPE */ - /* General event 0 */ - /* Method(_L00) { - * DBGO("\\_GPE\\_L00\n") - * } - */ - - /* General event 1 */ - /* Method(_L01) { - * DBGO("\\_GPE\\_L00\n") - * } - */ - - /* General event 2 */ - /* Method(_L02) { - * DBGO("\\_GPE\\_L00\n") - * } - */ - - /* General event 3 */ - Method(_L03) { - /* DBGO("\\_GPE\\_L00\n") */ - Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ - } - - /* General event 4 */ - /* Method(_L04) { - * DBGO("\\_GPE\\_L00\n") - * } - */ - - /* General event 5 */ - /* Method(_L05) { - * DBGO("\\_GPE\\_L00\n") - * } - */ - - /* General event 6 - Used for GPM6, moved to USB.asl */ - /* Method(_L06) { - * DBGO("\\_GPE\\_L00\n") - * } - */ - - /* General event 7 - Used for GPM7, moved to USB.asl */ - /* Method(_L07) { - * DBGO("\\_GPE\\_L07\n") - * } - */ - - /* Legacy PM event */ - Method(_L08) { - /* DBGO("\\_GPE\\_L08\n") */ - } - - /* Temp warning (TWarn) event */ - Method(_L09) { - /* DBGO("\\_GPE\\_L09\n") */ - Notify (\_TZ.TZ00, 0x80) - } - - /* Reserved */ - /* Method(_L0A) { - * DBGO("\\_GPE\\_L0A\n") - * } - */ - - /* USB controller PME# */ - Method(_L0B) { - /* DBGO("\\_GPE\\_L0B\n") */ - Notify(\_SB.PCI0.UOH1, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(\_SB.PCI0.UOH2, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(\_SB.PCI0.UOH3, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(\_SB.PCI0.UOH4, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(\_SB.PCI0.UOH5, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(\_SB.PCI0.UEH1, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ - } - - /* AC97 controller PME# */ - /* Method(_L0C) { - * DBGO("\\_GPE\\_L0C\n") - * } - */ - - /* OtherTherm PME# */ - /* Method(_L0D) { - * DBGO("\\_GPE\\_L0D\n") - * } - */ - - /* GPM9 SCI event - Moved to USB.asl */ - /* Method(_L0E) { - * DBGO("\\_GPE\\_L0E\n") - * } - */ - - /* PCIe HotPlug event */ - /* Method(_L0F) { - * DBGO("\\_GPE\\_L0F\n") - * } - */ - - /* ExtEvent0 SCI event */ - Method(_L10) { - /* DBGO("\\_GPE\\_L10\n") */ - } - - - /* ExtEvent1 SCI event */ - Method(_L11) { - /* DBGO("\\_GPE\\_L11\n") */ - } - - /* PCIe PME# event */ - /* Method(_L12) { - * DBGO("\\_GPE\\_L12\n") - * } - */ - - /* GPM0 SCI event - Moved to USB.asl */ - /* Method(_L13) { - * DBGO("\\_GPE\\_L13\n") - * } - */ - - /* GPM1 SCI event - Moved to USB.asl */ - /* Method(_L14) { - * DBGO("\\_GPE\\_L14\n") - * } - */ - - /* GPM2 SCI event - Moved to USB.asl */ - /* Method(_L15) { - * DBGO("\\_GPE\\_L15\n") - * } - */ - - /* GPM3 SCI event - Moved to USB.asl */ - /* Method(_L16) { - * DBGO("\\_GPE\\_L16\n") - * } - */ - - /* GPM8 SCI event - Moved to USB.asl */ - /* Method(_L17) { - * DBGO("\\_GPE\\_L17\n") - * } - */ - - /* GPIO0 or GEvent8 event */ - Method(_L18) { - /* DBGO("\\_GPE\\_L18\n") */ - Notify(\_SB.PCI0.PBR2, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(\_SB.PCI0.PBR4, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(\_SB.PCI0.PBR5, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(\_SB.PCI0.PBR6, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(\_SB.PCI0.PBR7, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ - } - - /* GPM4 SCI event - Moved to USB.asl */ - /* Method(_L19) { - * DBGO("\\_GPE\\_L19\n") - * } - */ - - /* GPM5 SCI event - Moved to USB.asl */ - /* Method(_L1A) { - * DBGO("\\_GPE\\_L1A\n") - * } - */ - - /* Azalia SCI event */ - Method(_L1B) { - /* DBGO("\\_GPE\\_L1B\n") */ - Notify(\_SB.PCI0.AZHD, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ - } - - /* GPM6 SCI event - Reassigned to _L06 */ - /* Method(_L1C) { - * DBGO("\\_GPE\\_L1C\n") - * } - */ - - /* GPM7 SCI event - Reassigned to _L07 */ - /* Method(_L1D) { - * DBGO("\\_GPE\\_L1D\n") - * } - */ - - /* GPIO2 or GPIO66 SCI event */ - /* Method(_L1E) { - * DBGO("\\_GPE\\_L1E\n") - * } - */ - - /* SATA SCI event - Moved to sata.asl */ - /* Method(_L1F) { - * DBGO("\\_GPE\\_L1F\n") - * } - */ - - } /* End Scope GPE */ - - #include "acpi/usb.asl" - - /* System Bus */ - Scope(\_SB) { /* Start \_SB scope */ - #include /* global utility methods expected within the \_SB scope */ - - /* _SB.PCI0 */ - /* Note: Only need HID on Primary Bus */ - Device(PCI0) { - External (TOM1) - External (TOM2) /* ( >> 20) to make it fit into 32 bit for XP */ - Name(_HID, EISAID("PNP0A03")) - Name(_ADR, 0x00180000) /* Dev# = BSP Dev#, Func# = 0 */ - Method(_BBN, 0) { /* Bus number = 0 */ - Return(0) - } - Method(_STA, 0) { - /* DBGO("\\_SB\\PCI0\\_STA\n") */ - Return(0x0B) /* Status is visible */ - } - - Method(_PRT,0) { - If(PMOD){ Return(APR0) } /* APIC mode */ - Return (PR0) /* PIC Mode */ - } /* end _PRT */ - - /* Describe the Northbridge devices */ - Device(AMRT) { - Name(_ADR, 0x00000000) - } /* end AMRT */ - - /* The internal GFX bridge */ - Device(AGPB) { - Name(_ADR, 0x00010000) - Name(_PRW, Package() {0x18, 4}) - Method(_PRT,0) { - Return (APR1) - } - } /* end AGPB */ - - /* The external GFX bridge */ - Device(PBR2) { - Name(_ADR, 0x00020000) - Name(_PRW, Package() {0x18, 4}) - Method(_PRT,0) { - If(PMOD){ Return(APS2) } /* APIC mode */ - Return (PS2) /* PIC Mode */ - } /* end _PRT */ - } /* end PBR2 */ - - /* Dev3 is also an external GFX bridge, not used in Herring */ - - Device(PBR4) { - Name(_ADR, 0x00040000) - Name(_PRW, Package() {0x18, 4}) - Method(_PRT,0) { - If(PMOD){ Return(APS4) } /* APIC mode */ - Return (PS4) /* PIC Mode */ - } /* end _PRT */ - } /* end PBR4 */ - - Device(PBR5) { - Name(_ADR, 0x00050000) - Name(_PRW, Package() {0x18, 4}) - Method(_PRT,0) { - If(PMOD){ Return(APS5) } /* APIC mode */ - Return (PS5) /* PIC Mode */ - } /* end _PRT */ - } /* end PBR5 */ - - Device(PBR6) { - Name(_ADR, 0x00060000) - Name(_PRW, Package() {0x18, 4}) - Method(_PRT,0) { - If(PMOD){ Return(APS6) } /* APIC mode */ - Return (PS6) /* PIC Mode */ - } /* end _PRT */ - } /* end PBR6 */ - - /* The onboard EtherNet chip */ - Device(PBR7) { - Name(_ADR, 0x00070000) - Name(_PRW, Package() {0x18, 4}) - Method(_PRT,0) { - If(PMOD){ Return(APS7) } /* APIC mode */ - Return (PS7) /* PIC Mode */ - } /* end _PRT */ - } /* end PBR7 */ - - /* GPP */ - Device(PBR9) { - Name(_ADR, 0x00090000) - Name(_PRW, Package() {0x18, 4}) - Method(_PRT,0) { - If(PMOD){ Return(APS9) } /* APIC mode */ - Return (PS9) /* PIC Mode */ - } /* end _PRT */ - } /* end PBR9 */ - - Device(PBRa) { - Name(_ADR, 0x000A0000) - Name(_PRW, Package() {0x18, 4}) - Method(_PRT,0) { - If(PMOD){ Return(APSa) } /* APIC mode */ - Return (PSa) /* PIC Mode */ - } /* end _PRT */ - } /* end PBRa */ - - - /* PCI slot 1, 2, 3 */ - Device(PIBR) { - Name(_ADR, 0x00140004) - Name(_PRW, Package() {0x18, 4}) - - Method(_PRT, 0) { - Return (PCIB) - } - } - - /* Describe the Southbridge devices */ - Device(STCR) { - Name(_ADR, 0x00110000) - #include "acpi/sata.asl" - } /* end STCR */ - - Device(UOH1) { - Name(_ADR, 0x00130000) - Name(_PRW, Package() {0x0B, 3}) - } /* end UOH1 */ - - Device(UOH2) { - Name(_ADR, 0x00130001) - Name(_PRW, Package() {0x0B, 3}) - } /* end UOH2 */ - - Device(UOH3) { - Name(_ADR, 0x00130002) - Name(_PRW, Package() {0x0B, 3}) - } /* end UOH3 */ - - Device(UOH4) { - Name(_ADR, 0x00130003) - Name(_PRW, Package() {0x0B, 3}) - } /* end UOH4 */ - - Device(UOH5) { - Name(_ADR, 0x00130004) - Name(_PRW, Package() {0x0B, 3}) - } /* end UOH5 */ - - Device(UEH1) { - Name(_ADR, 0x00130005) - Name(_PRW, Package() {0x0B, 3}) - } /* end UEH1 */ - - Device(SBUS) { - Name(_ADR, 0x00140000) - } /* end SBUS */ - - /* Primary (and only) IDE channel */ - Device(IDEC) { - Name(_ADR, 0x00140001) - #include "acpi/ide.asl" - } /* end IDEC */ - - Device(AZHD) { - Name(_ADR, 0x00140002) - OperationRegion(AZPD, PCI_Config, 0x00, 0x100) - Field(AZPD, AnyAcc, NoLock, Preserve) { - offset (0x42), - NSDI, 1, - NSDO, 1, - NSEN, 1, - offset (0x44), - IPCR, 4, - offset (0x54), - PWST, 2, - , 6, - PMEB, 1, - , 6, - PMST, 1, - offset (0x62), - MMCR, 1, - offset (0x64), - MMLA, 32, - offset (0x68), - MMHA, 32, - offset (0x6C), - MMDT, 16, - } - - Method(_INI) { - If(LEqual(OSVR,3)){ /* If we are running Linux */ - Store(zero, NSEN) - Store(one, NSDO) - Store(one, NSDI) - } - } - } /* end AZHD */ - - Device(LIBR) { - Name(_ADR, 0x00140003) - /* Method(_INI) { - * DBGO("\\_SB\\PCI0\\LpcIsaBr\\_INI\n") - } */ /* End Method(_SB.SBRDG._INI) */ - - /* Real Time Clock Device */ - Device(RTC0) { - Name(_HID, EISAID("PNP0B00")) /* AT Real Time Clock (not PIIX4 compatible) */ - Name(_CRS, ResourceTemplate() { - IRQNoFlags(){8} - IO(Decode16,0x0070, 0x0070, 0, 2) - /* IO(Decode16,0x0070, 0x0070, 0, 4) */ - }) - } /* End Device(_SB.PCI0.LpcIsaBr.RTC0) */ - - Device(TMR) { /* Timer */ - Name(_HID,EISAID("PNP0100")) /* System Timer */ - Name(_CRS, ResourceTemplate() { - IRQNoFlags(){0} - IO(Decode16, 0x0040, 0x0040, 0, 4) - /* IO(Decode16, 0x0048, 0x0048, 0, 4) */ - }) - } /* End Device(_SB.PCI0.LpcIsaBr.TMR) */ - - Device(SPKR) { /* Speaker */ - Name(_HID,EISAID("PNP0800")) /* AT style speaker */ - Name(_CRS, ResourceTemplate() { - IO(Decode16, 0x0061, 0x0061, 0, 1) - }) - } /* End Device(_SB.PCI0.LpcIsaBr.SPKR) */ - - Device(PIC) { - Name(_HID,EISAID("PNP0000")) /* AT Interrupt Controller */ - Name(_CRS, ResourceTemplate() { - IRQNoFlags(){2} - IO(Decode16,0x0020, 0x0020, 0, 2) - IO(Decode16,0x00A0, 0x00A0, 0, 2) - /* IO(Decode16, 0x00D0, 0x00D0, 0x10, 0x02) */ - /* IO(Decode16, 0x04D0, 0x04D0, 0x10, 0x02) */ - }) - } /* End Device(_SB.PCI0.LpcIsaBr.PIC) */ - - Device(MAD) { /* 8257 DMA */ - Name(_HID,EISAID("PNP0200")) /* Hardware Device ID */ - Name(_CRS, ResourceTemplate() { - DMA(Compatibility,BusMaster,Transfer8){4} - IO(Decode16, 0x0000, 0x0000, 0x10, 0x10) - IO(Decode16, 0x0081, 0x0081, 0x01, 0x03) - IO(Decode16, 0x0087, 0x0087, 0x01, 0x01) - IO(Decode16, 0x0089, 0x0089, 0x01, 0x03) - IO(Decode16, 0x008F, 0x008F, 0x01, 0x01) - IO(Decode16, 0x00C0, 0x00C0, 0x10, 0x20) - }) /* End Name(_SB.PCI0.LpcIsaBr.MAD._CRS) */ - } /* End Device(_SB.PCI0.LpcIsaBr.MAD) */ - - Device(COPR) { - Name(_HID,EISAID("PNP0C04")) /* Math Coprocessor */ - Name(_CRS, ResourceTemplate() { - IO(Decode16, 0x00F0, 0x00F0, 0, 0x10) - IRQNoFlags(){13} - }) - } /* End Device(_SB.PCI0.LpcIsaBr.COPR) */ - - Device(HPTM) { - Name(_HID,EISAID("PNP0103")) - Name(CRS,ResourceTemplate() { - Memory32Fixed(ReadOnly,0xFED00000, 0x00000400, HPT) /* 1kb reserved space */ - }) - Method(_STA, 0) { - Return(0x0F) /* sata is visible */ - } - Method(_CRS, 0) { - CreateDwordField(CRS, ^HPT._BAS, HPBX) - Store(HPBA, HPBX) - Return(CRS) - } - } /* End Device(_SB.PCI0.LpcIsaBr.COPR) */ - } /* end LIBR */ - - Device(HPBR) { - Name(_ADR, 0x00140004) - } /* end HostPciBr */ - - Device(ACAD) { - Name(_ADR, 0x00140005) - } /* end Ac97audio */ - - Device(ACMD) { - Name(_ADR, 0x00140006) - } /* end Ac97modem */ - - /* ITE8718 Support */ - OperationRegion (IOID, SystemIO, 0x2E, 0x02) /* sometimes it is 0x4E */ - Field (IOID, ByteAcc, NoLock, Preserve) - { - SIOI, 8, SIOD, 8 /* 0x2E and 0x2F */ - } - - IndexField (SIOI, SIOD, ByteAcc, NoLock, Preserve) - { - Offset (0x07), - LDN, 8, /* Logical Device Number */ - Offset (0x20), - CID1, 8, /* Chip ID Byte 1, 0x87 */ - CID2, 8, /* Chip ID Byte 2, 0x12 */ - Offset (0x30), - ACTR, 8, /* Function activate */ - Offset (0xF0), - APC0, 8, /* APC/PME Event Enable Register */ - APC1, 8, /* APC/PME Status Register */ - APC2, 8, /* APC/PME Control Register 1 */ - APC3, 8, /* Environment Controller Special Configuration Register */ - APC4, 8 /* APC/PME Control Register 2 */ - } - - /* Enter the 8718 MB PnP Mode */ - Method (EPNP) - { - Store(0x87, SIOI) - Store(0x01, SIOI) - Store(0x55, SIOI) - Store(0x55, SIOI) /* 8718 magic number */ - } - /* Exit the 8718 MB PnP Mode */ - Method (XPNP) - { - Store (0x02, SIOI) - Store (0x02, SIOD) - } - /* - * Keyboard PME is routed to SB700 Gevent3. We can wake - * up the system by pressing the key. - */ - Method (SIOS, 1) - { - /* We only enable KBD PME for S5. */ - If (LLess (Arg0, 0x05)) - { - EPNP() - /* DBGO("8718F\n") */ - - Store (0x4, LDN) - Store (One, ACTR) /* Enable EC */ - /* - Store (0x4, LDN) - Store (0x04, APC4) - */ /* falling edge. which mode? Not sure. */ - - Store (0x4, LDN) - Store (0x08, APC1) /* clear PME status, Use 0x18 for mouse & KBD */ - Store (0x4, LDN) - Store (0x08, APC0) /* enable PME, Use 0x18 for mouse & KBD */ - - XPNP() - } - } - Method (SIOW, 0) - { - EPNP() - Store (0x4, LDN) - Store (Zero, APC0) /* disable keyboard PME */ - Store (0x4, LDN) - Store (0xFF, APC1) /* clear keyboard PME status */ - XPNP() - } - - Name(CRES, ResourceTemplate() { - IO(Decode16, 0x0CF8, 0x0CF8, 1, 8) - - WORDIO(ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, - 0x0000, /* address granularity */ - 0x0000, /* range minimum */ - 0x0CF7, /* range maximum */ - 0x0000, /* translation */ - 0x0CF8 /* length */ - ) - - WORDIO(ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, - 0x0000, /* address granularity */ - 0x0D00, /* range minimum */ - 0xFFFF, /* range maximum */ - 0x0000, /* translation */ - 0xF300 /* length */ - ) - - Memory32Fixed(READWRITE, 0, 0xA0000, BSMM) - Memory32Fixed(READONLY, 0x000A0000, 0x00020000, VGAM) /* VGA memory space */ - Memory32Fixed(READONLY, 0x000C0000, 0x00020000, EMM1) /* Assume C0000-E0000 empty */ - Memory32Fixed(READONLY, 0x000E0000, 0x00020000, RDBS) /* BIOS ROM area */ - - /* DRAM Memory from 1MB to TopMem */ - Memory32Fixed(READWRITE, 0x00100000, 0, DMLO) /* 1MB to TopMem */ - - /* BIOS space just below 4GB */ - DWORDMemory( - ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite, - 0x00, /* Granularity */ - 0x00000000, /* Min */ - 0x00000000, /* Max */ - 0x00000000, /* Translation */ - 0x00000001, /* Max-Min, RLEN */ - ,, - PCBM - ) - - /* DRAM memory from 4GB to TopMem2 */ - QWORDMemory(ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite, - 0x00000000, /* Granularity */ - 0x00000000, /* Min */ - 0x00000000, /* Max */ - 0x00000000, /* Translation */ - 0x00000001, /* Max-Min, RLEN */ - ,, - DMHI - ) - - /* BIOS space just below 16EB */ - QWORDMemory(ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite, - 0x00000000, /* Granularity */ - 0x00000000, /* Min */ - 0x00000000, /* Max */ - 0x00000000, /* Translation */ - 0x00000001, /* Max-Min, RLEN */ - ,, - PEBM - ) - - }) /* End Name(_SB.PCI0.CRES) */ - - Method(_CRS, 0) { - /* DBGO("\\_SB\\PCI0\\_CRS\n") */ - - CreateDWordField(CRES, ^EMM1._BAS, EM1B) - CreateDWordField(CRES, ^EMM1._LEN, EM1L) - CreateDWordField(CRES, ^DMLO._BAS, DMLB) - CreateDWordField(CRES, ^DMLO._LEN, DMLL) - CreateDWordField(CRES, ^PCBM._MIN, PBMB) - CreateDWordField(CRES, ^PCBM._LEN, PBML) - - CreateQWordField(CRES, ^DMHI._MIN, DMHB) - CreateQWordField(CRES, ^DMHI._LEN, DMHL) - CreateQWordField(CRES, ^PEBM._MIN, EBMB) - CreateQWordField(CRES, ^PEBM._LEN, EBML) - - If(LGreater(LOMH, 0xC0000)){ - Store(0xC0000, EM1B) /* Hole above C0000 and below E0000 */ - Subtract(LOMH, 0xC0000, EM1L) /* subtract start, assumes allocation from C0000 going up */ - } - - /* Set size of memory from 1MB to TopMem */ - Subtract(TOM1, 0x100000, DMLL) - - /* - * If(LNotEqual(TOM2, 0x00000000)){ - * Store(0x100000000,DMHB) DRAM from 4GB to TopMem2 - * ShiftLeft(TOM2, 20, Local0) - * Subtract(Local0, 0x100000000, DMHL) - * } - */ - - /* If there is no memory above 4GB, put the BIOS just below 4GB */ - If(LEqual(TOM2, 0x00000000)){ - Store(PBAD,PBMB) /* Reserve the "BIOS" space */ - Store(PBLN,PBML) - } - Else { /* Otherwise, put the BIOS just below 16EB */ - ShiftLeft(PBAD,16,EBMB) /* Reserve the "BIOS" space */ - Store(PBLN,EBML) - } - - Return(CRES) /* note to change the Name buffer */ - } /* end of Method(_SB.PCI0._CRS) */ - - /* - * - * FIRST METHOD CALLED UPON BOOT - * - * 1. If debugging, print current OS and ACPI interpreter. - * 2. Get PCI Interrupt routing from ACPI VSM, this - * value is based on user choice in BIOS setup. - */ - Method(_INI, 0) { - /* DBGO("\\_SB\\_INI\n") */ - /* DBGO(" DSDT.ASL code from ") */ - /* DBGO(__DATE__) */ - /* DBGO(" ") */ - /* DBGO(__TIME__) */ - /* DBGO("\n Sleep states supported: ") */ - /* DBGO("\n") */ - /* DBGO(" \\_OS=") */ - /* DBGO(\_OS) */ - /* DBGO("\n \\_REV=") */ - /* DBGO(\_REV) */ - /* DBGO("\n") */ - - /* Determine the OS we're running on */ - OSFL() - - /* On older chips, clear PciExpWakeDisEn */ - /*if (LLessEqual(\SBRI, 0x13)) { - * Store(0,\PWDE) - * } - */ - } /* End Method(_SB._INI) */ - } /* End Device(PCI0) */ - - Device(PWRB) { /* Start Power button device */ - Name(_HID, EISAID("PNP0C0C")) - Name(_UID, 0xAA) - Name(_PRW, Package () {3, 0x04}) /* wake from S1-S4 */ - Name(_STA, 0x0B) /* sata is invisible */ - } - } /* End \_SB scope */ - - Scope(\_SI) { - Method(_SST, 1) { - /* DBGO("\\_SI\\_SST\n") */ - /* DBGO(" New Indicator state: ") */ - /* DBGO(Arg0) */ - /* DBGO("\n") */ - } - } /* End Scope SI */ - - #include - - /* THERMAL */ - Scope(\_TZ) { - Name (KELV, 2732) - Name (THOT, 800) - Name (TCRT, 850) - - ThermalZone(TZ00) { - Method(_AC0,0) { /* Active Cooling 0 (0=highest fan speed) */ - /* DBGO("\\_TZ\\TZ00\\_AC0\n") */ - Return(Add(0, 2730)) - } - Method(_AL0,0) { /* Returns package of cooling device to turn on */ - /* DBGO("\\_TZ\\TZ00\\_AL0\n") */ - Return(Package() {\_TZ.TZ00.FAN0}) - } - Device (FAN0) { - Name(_HID, EISAID("PNP0C0B")) - Name(_PR0, Package() {PFN0}) - } - - PowerResource(PFN0,0,0) { - Method(_STA) { - Store(0xF,Local0) - Return(Local0) - } - Method(_ON) { - /* DBGO("\\_TZ\\TZ00\\FAN0 _ON\n") */ - } - Method(_OFF) { - /* DBGO("\\_TZ\\TZ00\\FAN0 _OFF\n") */ - } - } - - Method(_HOT,0) { /* return hot temp in tenths degree Kelvin */ - /* DBGO("\\_TZ\\TZ00\\_HOT\n") */ - Return (Add (THOT, KELV)) - } - Method(_CRT,0) { /* return critical temp in tenths degree Kelvin */ - /* DBGO("\\_TZ\\TZ00\\_CRT\n") */ - Return (Add (TCRT, KELV)) - } - Method(_TMP,0) { /* return current temp of this zone */ - Store (SMBR (0x07, 0x4C,, 0x00), Local0) - If (LGreater (Local0, 0x10)) { - Store (Local0, Local1) - } - Else { - Add (Local0, THOT, Local0) - Return (Add (400, KELV)) - } - - Store (SMBR (0x07, 0x4C, 0x01), Local0) - /* only the two MSBs in the external temperature low byte are used, resolution 0.25. We ignore it */ - /* Store (SMBR (0x07, 0x4C, 0x10), Local2) */ - If (LGreater (Local0, 0x10)) { - If (LGreater (Local0, Local1)) { - Store (Local0, Local1) - } - - Multiply (Local1, 10, Local1) - Return (Add (Local1, KELV)) - } - Else { - Add (Local0, THOT, Local0) - Return (Add (400 , KELV)) - } - } /* end of _TMP */ - } /* end of TZ00 */ - } -} -/* End of ASL file */ diff --git a/src/mainboard/jetway/pa78vm5/get_bus_conf.c b/src/mainboard/jetway/pa78vm5/get_bus_conf.c deleted file mode 100644 index ee2a6caeb9..0000000000 --- a/src/mainboard/jetway/pa78vm5/get_bus_conf.c +++ /dev/null @@ -1,44 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2010 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include -#include - -#include - -/* Global variables for MB layouts and these will be shared by irqtable mptable -* and acpi_tables busnum is default. -*/ -u32 apicid_sb700; - -void get_bus_conf(void) -{ - u32 apicid_base; - - get_default_pci1234(1); - - sysconf.sbdn = (sysconf.hcdn[0] & 0xff); - - pirq_router_bus = (sysconf.pci1234[0] >> 16) & 0xff; - - /* I/O APICs: APIC ID Version State Address */ - if (CONFIG(LOGICAL_CPUS)) - apicid_base = get_apicid_base(1); - else - apicid_base = CONFIG_MAX_PHYSICAL_CPUS; - apicid_sb700 = apicid_base + 0; -} diff --git a/src/mainboard/jetway/pa78vm5/irq_tables.c b/src/mainboard/jetway/pa78vm5/irq_tables.c deleted file mode 100644 index 0f7192514e..0000000000 --- a/src/mainboard/jetway/pa78vm5/irq_tables.c +++ /dev/null @@ -1,102 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2010 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include -#include -#include - -#include - -static void write_pirq_info(struct irq_info *pirq_info, u8 bus, u8 devfn, - u8 link0, u16 bitmap0, u8 link1, u16 bitmap1, - u8 link2, u16 bitmap2, u8 link3, u16 bitmap3, - u8 slot, u8 rfu) -{ - pirq_info->bus = bus; - pirq_info->devfn = devfn; - pirq_info->irq[0].link = link0; - pirq_info->irq[0].bitmap = bitmap0; - pirq_info->irq[1].link = link1; - pirq_info->irq[1].bitmap = bitmap1; - pirq_info->irq[2].link = link2; - pirq_info->irq[2].bitmap = bitmap2; - pirq_info->irq[3].link = link3; - pirq_info->irq[3].bitmap = bitmap3; - pirq_info->slot = slot; - pirq_info->rfu = rfu; -} - - -unsigned long write_pirq_routing_table(unsigned long addr) -{ - struct irq_routing_table *pirq; - struct irq_info *pirq_info; - u32 slot_num; - u8 *v; - - u8 sum = 0; - int i; - - /* Align the table to be 16 byte aligned. */ - addr += 15; - addr &= ~15; - - /* This table must be between 0xf0000 & 0x100000 */ - printk(BIOS_INFO, "Writing IRQ routing tables to 0x%lx...", addr); - - pirq = (void *)(addr); - v = (u8 *) (addr); - - pirq->signature = PIRQ_SIGNATURE; - pirq->version = PIRQ_VERSION; - - pirq->rtr_bus = pirq_router_bus; - pirq->rtr_devfn = PCI_DEVFN(0x14, 4); - - pirq->exclusive_irqs = 0; - - pirq->rtr_vendor = 0x1002; - pirq->rtr_device = 0x4384; - - pirq->miniport_data = 0; - - memset(pirq->rfu, 0, sizeof(pirq->rfu)); - - pirq_info = (void *)(&pirq->checksum + 1); - slot_num = 0; - - /* pci bridge */ - write_pirq_info(pirq_info, pirq_router_bus, PCI_DEVFN(0x14, 4), - 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, - 0); - pirq_info++; - slot_num++; - - pirq->size = 32 + 16 * slot_num; - - for (i = 0; i < pirq->size; i++) - sum += v[i]; - - sum = pirq->checksum - sum; - if (sum != pirq->checksum) { - pirq->checksum = sum; - } - - printk(BIOS_INFO, "write_pirq_routing_table done.\n"); - - return (unsigned long)pirq_info; -} diff --git a/src/mainboard/jetway/pa78vm5/mainboard.c b/src/mainboard/jetway/pa78vm5/mainboard.c deleted file mode 100644 index 7bf82971c5..0000000000 --- a/src/mainboard/jetway/pa78vm5/mainboard.c +++ /dev/null @@ -1,104 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2010 Wang Qing Pei - * Copyright (C) 2010 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include -#include -#include -#include -#include -#include - -/* - * the board uses GPIO 6 as PCIe slot reset, GPIO4 as GFX slot reset. We need to - * pull it up before training the slot. - ***/ -void set_pcie_dereset(void) -{ - u16 word; - struct device *sm_dev; - /* GPIO 6 reset PCIe slot, GPIO 4 reset GFX PCIe */ - sm_dev = pcidev_on_root(0x14, 0); - - word = pci_read_config16(sm_dev, 0xA8); - word |= (1 << 0) | (1 << 2); /* Set Gpio6,4 as output */ - word &= ~((1 << 8) | (1 << 10)); - pci_write_config16(sm_dev, 0xA8, word); -} - -void set_pcie_reset(void) -{ - u16 word; - struct device *sm_dev; - /* GPIO 6 reset PCIe slot, GPIO 4 reset GFX PCIe */ - sm_dev = pcidev_on_root(0x14, 0); - - word = pci_read_config16(sm_dev, 0xA8); - word &= ~((1 << 0) | (1 << 2)); /* Set Gpio6,4 as output */ - word &= ~((1 << 8) | (1 << 10)); - pci_write_config16(sm_dev, 0xA8, word); -} - -#if 0 /* not tested yet. */ -/******************************************************** -* board uses SB700 GPIO9 to detect IDE_DMA66. -* IDE_DMA66 is routed to GPIO 9. So we read Gpio 9 to -* get the cable type, 40 pin or 80 pin? -********************************************************/ -static void get_ide_dma66(void) -{ - u8 byte; - /*u32 sm_dev, ide_dev; */ - struct device *sm_dev, ide_dev; - - sm_dev = pcidev_on_root(0x14, 0); - - byte = pci_read_config8(sm_dev, 0xA9); - byte |= (1 << 5); /* Set Gpio9 as input */ - pci_write_config8(sm_dev, 0xA9, byte); - - ide_dev = pcidev_on_root(0x14, 1); - byte = pci_read_config8(ide_dev, 0x56); - byte &= ~(7 << 0); - if ((1 << 5) & pci_read_config8(sm_dev, 0xAA)) - byte |= 2 << 0; /* mode 2 */ - else - byte |= 5 << 0; /* mode 5 */ - pci_write_config8(ide_dev, 0x56, byte); -} -#endif /* get_ide_dma66() */ - -int is_dev3_present(void) -{ - return 0; -} - -/************************************************* -* enable the dedicated function in this board. -* This function called early than rs780_enable. -*************************************************/ -static void mainboard_enable(struct device *dev) -{ - printk(BIOS_INFO, "Mainboard PA78VM5 Enable. dev=0x%p\n", dev); - - set_pcie_dereset(); - /* get_ide_dma66(); */ -} - -struct chip_operations mainboard_ops = { - .enable_dev = mainboard_enable, -}; diff --git a/src/mainboard/jetway/pa78vm5/mptable.c b/src/mainboard/jetway/pa78vm5/mptable.c deleted file mode 100644 index 6e9d1cce06..0000000000 --- a/src/mainboard/jetway/pa78vm5/mptable.c +++ /dev/null @@ -1,102 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2010 Wang Qing Pei - * Copyright (C) 2010 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include -#include -#include - -extern u32 apicid_sb700; - -static void *smp_write_config_table(void *v) -{ - struct mp_config_table *mc; - int bus_isa; - - mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); - - mptable_init(mc, LOCAL_APIC_ADDR); - - smp_write_processors(mc); - - mptable_write_buses(mc, NULL, &bus_isa); - - /* I/O APICs: APIC ID Version State Address */ - { - struct device *dev; - u32 dword; - u8 byte; - - dev = - dev_find_slot(pirq_router_bus, - PCI_DEVFN(0x14, 0)); - if (dev) { - dword = pci_read_config32(dev, 0x74) & 0xfffffff0; - smp_write_ioapic(mc, apicid_sb700, - 0x11,(void *) dword); - - /* Initialize interrupt mapping */ - /* aza */ - byte = pci_read_config8(dev, 0x63); - byte &= 0xf8; - byte |= 0; /* 0: INTA, ...., 7: INTH */ - pci_write_config8(dev, 0x63, byte); - - /* SATA */ - dword = pci_read_config32(dev, 0xac); - dword &= ~(7 << 26); - dword |= 6 << 26; /* 0: INTA, ...., 7: INTH */ - /* dword |= 1 << 22; PIC and APIC co exists */ - pci_write_config32(dev, 0xac, dword); - - /* - * 00:12.0: PROG SATA : INT F - * 00:13.0: INTA USB_0 - * 00:13.1: INTB USB_1 - * 00:13.2: INTC USB_2 - * 00:13.3: INTD USB_3 - * 00:13.4: INTC USB_4 - * 00:13.5: INTD USB2 - * 00:14.1: INTA IDE - * 00:14.2: Prog HDA : INT E - * 00:14.5: INTB ACI - * 00:14.6: INTB MCI - */ - } - } - - /* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ -#define IO_LOCAL_INT(type, intr, apicid, pin) \ - smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin)); - - mptable_add_isa_interrupts(mc, bus_isa, apicid_sb700, 0); - - /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ - IO_LOCAL_INT(mp_ExtINT, 0x0, MP_APIC_ALL, 0x0); - IO_LOCAL_INT(mp_NMI, 0x0, MP_APIC_ALL, 0x1); - /* There is no extension information... */ - - /* Compute the checksums */ - return mptable_finalize(mc); -} - -unsigned long write_smp_table(unsigned long addr) -{ - void *v; - v = smp_write_floating_table(addr, 0); - return (unsigned long)smp_write_config_table(v); -} diff --git a/src/mainboard/jetway/pa78vm5/resourcemap.c b/src/mainboard/jetway/pa78vm5/resourcemap.c deleted file mode 100644 index d10263923f..0000000000 --- a/src/mainboard/jetway/pa78vm5/resourcemap.c +++ /dev/null @@ -1,280 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2010 Wang Qing Pei - * Copyright (C) 2010 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - - - -#include -#include - -void setup_mb_resource_map(void) -{ - static const unsigned int register_values[] = { - /* Careful set limit registers before base registers which contain the enables */ - /* DRAM Limit i Registers - * F1:0x44 i = 0 - * F1:0x4C i = 1 - * F1:0x54 i = 2 - * F1:0x5C i = 3 - * F1:0x64 i = 4 - * F1:0x6C i = 5 - * F1:0x74 i = 6 - * F1:0x7C i = 7 - * [ 2: 0] Destination Node ID - * 000 = Node 0 - * 001 = Node 1 - * 010 = Node 2 - * 011 = Node 3 - * 100 = Node 4 - * 101 = Node 5 - * 110 = Node 6 - * 111 = Node 7 - * [ 7: 3] Reserved - * [10: 8] Interleave select - * specifies the values of A[14:12] to use with interleave enable. - * [15:11] Reserved - * [31:16] DRAM Limit Address i Bits 39-24 - * This field defines the upper address bits of a 40 bit address - * that define the end of the DRAM region. - */ -// ADDRMAP_REG(0x44), 0x0000f8f8, 0x00000000, // Don't touch it, we need it for CONFIG_CAR_FAM10 - ADDRMAP_REG(0x4C), 0x0000f8f8, 0x00000001, - ADDRMAP_REG(0x54), 0x0000f8f8, 0x00000002, - ADDRMAP_REG(0x5C), 0x0000f8f8, 0x00000003, - ADDRMAP_REG(0x64), 0x0000f8f8, 0x00000004, - ADDRMAP_REG(0x6C), 0x0000f8f8, 0x00000005, - ADDRMAP_REG(0x74), 0x0000f8f8, 0x00000006, - ADDRMAP_REG(0x7C), 0x0000f8f8, 0x00000007, - /* DRAM Base i Registers - * F1:0x40 i = 0 - * F1:0x48 i = 1 - * F1:0x50 i = 2 - * F1:0x58 i = 3 - * F1:0x60 i = 4 - * F1:0x68 i = 5 - * F1:0x70 i = 6 - * F1:0x78 i = 7 - * [ 0: 0] Read Enable - * 0 = Reads Disabled - * 1 = Reads Enabled - * [ 1: 1] Write Enable - * 0 = Writes Disabled - * 1 = Writes Enabled - * [ 7: 2] Reserved - * [10: 8] Interleave Enable - * 000 = No interleave - * 001 = Interleave on A[12] (2 nodes) - * 010 = reserved - * 011 = Interleave on A[12] and A[14] (4 nodes) - * 100 = reserved - * 101 = reserved - * 110 = reserved - * 111 = Interleve on A[12] and A[13] and A[14] (8 nodes) - * [15:11] Reserved - * [13:16] DRAM Base Address i Bits 39-24 - * This field defines the upper address bits of a 40-bit address - * that define the start of the DRAM region. - */ -// ADDRMAP_REG(0x40), 0x0000f8fc, 0x00000000,// don't touch it, we need it for CONFIG_CAR_FAM10 - ADDRMAP_REG(0x48), 0x0000f8fc, 0x00000000, - ADDRMAP_REG(0x50), 0x0000f8fc, 0x00000000, - ADDRMAP_REG(0x58), 0x0000f8fc, 0x00000000, - ADDRMAP_REG(0x60), 0x0000f8fc, 0x00000000, - ADDRMAP_REG(0x68), 0x0000f8fc, 0x00000000, - ADDRMAP_REG(0x70), 0x0000f8fc, 0x00000000, - ADDRMAP_REG(0x78), 0x0000f8fc, 0x00000000, - - /* Memory-Mapped I/O Limit i Registers - * F1:0x84 i = 0 - * F1:0x8C i = 1 - * F1:0x94 i = 2 - * F1:0x9C i = 3 - * F1:0xA4 i = 4 - * F1:0xAC i = 5 - * F1:0xB4 i = 6 - * F1:0xBC i = 7 - * [ 2: 0] Destination Node ID - * 000 = Node 0 - * 001 = Node 1 - * 010 = Node 2 - * 011 = Node 3 - * 100 = Node 4 - * 101 = Node 5 - * 110 = Node 6 - * 111 = Node 7 - * [ 3: 3] Reserved - * [ 5: 4] Destination Link ID - * 00 = Link 0 - * 01 = Link 1 - * 10 = Link 2 - * 11 = Reserved - * [ 6: 6] Reserved - * [ 7: 7] Non-Posted - * 0 = CPU writes may be posted - * 1 = CPU writes must be non-posted - * [31: 8] Memory-Mapped I/O Limit Address i (39-16) - * This field defines the upp address bits of a 40-bit address that - * defines the end of a memory-mapped I/O region n - */ - ADDRMAP_REG(0x84), 0x00000048, 0x00000000, - ADDRMAP_REG(0x8C), 0x00000048, 0x00000000, - ADDRMAP_REG(0x94), 0x00000048, 0x00000000, - ADDRMAP_REG(0x9C), 0x00000048, 0x00000000, - ADDRMAP_REG(0xA4), 0x00000048, 0x00000000, - ADDRMAP_REG(0xAC), 0x00000048, 0x00000000, - ADDRMAP_REG(0xB4), 0x00000048, 0x00000000, -// ADDRMAP_REG(0xBC), 0x00000048, 0x00ffff00, - - /* Memory-Mapped I/O Base i Registers - * F1:0x80 i = 0 - * F1:0x88 i = 1 - * F1:0x90 i = 2 - * F1:0x98 i = 3 - * F1:0xA0 i = 4 - * F1:0xA8 i = 5 - * F1:0xB0 i = 6 - * F1:0xB8 i = 7 - * [ 0: 0] Read Enable - * 0 = Reads disabled - * 1 = Reads Enabled - * [ 1: 1] Write Enable - * 0 = Writes disabled - * 1 = Writes Enabled - * [ 2: 2] Cpu Disable - * 0 = Cpu can use this I/O range - * 1 = Cpu requests do not use this I/O range - * [ 3: 3] Lock - * 0 = base/limit registers i are read/write - * 1 = base/limit registers i are read-only - * [ 7: 4] Reserved - * [31: 8] Memory-Mapped I/O Base Address i (39-16) - * This field defines the upper address bits of a 40bit address - * that defines the start of memory-mapped I/O region i - */ - ADDRMAP_REG(0x80), 0x000000f0, 0x00000000, - ADDRMAP_REG(0x88), 0x000000f0, 0x00000000, - ADDRMAP_REG(0x90), 0x000000f0, 0x00000000, - ADDRMAP_REG(0x98), 0x000000f0, 0x00000000, - ADDRMAP_REG(0xA0), 0x000000f0, 0x00000000, - ADDRMAP_REG(0xA8), 0x000000f0, 0x00000000, - ADDRMAP_REG(0xB0), 0x000000f0, 0x00000000, -// ADDRMAP_REG(0xB8), 0x000000f0, 0x00fc0003, - - /* PCI I/O Limit i Registers - * F1:0xC4 i = 0 - * F1:0xCC i = 1 - * F1:0xD4 i = 2 - * F1:0xDC i = 3 - * [ 2: 0] Destination Node ID - * 000 = Node 0 - * 001 = Node 1 - * 010 = Node 2 - * 011 = Node 3 - * 100 = Node 4 - * 101 = Node 5 - * 110 = Node 6 - * 111 = Node 7 - * [ 3: 3] Reserved - * [ 5: 4] Destination Link ID - * 00 = Link 0 - * 01 = Link 1 - * 10 = Link 2 - * 11 = reserved - * [11: 6] Reserved - * [24:12] PCI I/O Limit Address i - * This field defines the end of PCI I/O region n - * [31:25] Reserved - */ -// ADDRMAP_REG(0xC4), 0xFE000FC8, 0x01fff000, - ADDRMAP_REG(0xCC), 0xFE000FC8, 0x00000000, - ADDRMAP_REG(0xD4), 0xFE000FC8, 0x00000000, - ADDRMAP_REG(0xDC), 0xFE000FC8, 0x00000000, - - /* PCI I/O Base i Registers - * F1:0xC0 i = 0 - * F1:0xC8 i = 1 - * F1:0xD0 i = 2 - * F1:0xD8 i = 3 - * [ 0: 0] Read Enable - * 0 = Reads Disabled - * 1 = Reads Enabled - * [ 1: 1] Write Enable - * 0 = Writes Disabled - * 1 = Writes Enabled - * [ 3: 2] Reserved - * [ 4: 4] VGA Enable - * 0 = VGA matches Disabled - * 1 = matches all address < 64K and where A[9:0] is in the - * range 3B0-3BB or 3C0-3DF independen of the base & limit registers - * [ 5: 5] ISA Enable - * 0 = ISA matches Disabled - * 1 = Blocks address < 64K and in the last 768 bytes of eack 1K block - * from matching agains this base/limit pair - * [11: 6] Reserved - * [24:12] PCI I/O Base i - * This field defines the start of PCI I/O region n - * [31:25] Reserved - */ -// ADDRMAP_REG(0xC0), 0xFE000FCC, 0x00000003, - ADDRMAP_REG(0xC8), 0xFE000FCC, 0x00000000, - ADDRMAP_REG(0xD0), 0xFE000FCC, 0x00000000, - ADDRMAP_REG(0xD8), 0xFE000FCC, 0x00000000, - - /* Config Base and Limit i Registers - * F1:0xE0 i = 0 - * F1:0xE4 i = 1 - * F1:0xE8 i = 2 - * F1:0xEC i = 3 - * [ 0: 0] Read Enable - * 0 = Reads Disabled - * 1 = Reads Enabled - * [ 1: 1] Write Enable - * 0 = Writes Disabled - * 1 = Writes Enabled - * [ 2: 2] Device Number Compare Enable - * 0 = The ranges are based on bus number - * 1 = The ranges are ranges of devices on bus 0 - * [ 3: 3] Reserved - * [ 6: 4] Destination Node - * 000 = Node 0 - * 001 = Node 1 - * 010 = Node 2 - * 011 = Node 3 - * 100 = Node 4 - * 101 = Node 5 - * 110 = Node 6 - * 111 = Node 7 - * [ 7: 7] Reserved - * [ 9: 8] Destination Link - * 00 = Link 0 - * 01 = Link 1 - * 10 = Link 2 - * 11 - Reserved - * [15:10] Reserved - * [23:16] Bus Number Base i - * This field defines the lowest bus number in configuration region i - * [31:24] Bus Number Limit i - * This field defines the highest bus number in configuration regin i - */ -// ADDRMAP_REG(0xE0), 0x0000FC88, 0x06000003, // AMD 8111 on link0 of CPU 0 - ADDRMAP_REG(0xE4), 0x0000FC88, 0x00000000, - ADDRMAP_REG(0xE8), 0x0000FC88, 0x00000000, - ADDRMAP_REG(0xEC), 0x0000FC88, 0x00000000, - }; - - int max; - max = ARRAY_SIZE(register_values); - setup_resource_map(register_values, max); -} diff --git a/src/mainboard/jetway/pa78vm5/romstage.c b/src/mainboard/jetway/pa78vm5/romstage.c deleted file mode 100644 index 33d40b8876..0000000000 --- a/src/mainboard/jetway/pa78vm5/romstage.c +++ /dev/null @@ -1,230 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2010 Wang Qing Pei - * Copyright (C) 2010 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -//#define SYSTEM_TYPE 0 /* SERVER */ -#define SYSTEM_TYPE 1 /* DESKTOP */ -//#define SYSTEM_TYPE 2 /* MOBILE */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include "cpu/amd/quadcore/quadcore.c" - -#if CONFIG_TTYS0_BASE == 0x2f8 -#define SERIAL_DEV PNP_DEV(0x2e, F71863FG_SP2) -#else -#define SERIAL_DEV PNP_DEV(0x2e, F71863FG_SP1) -#endif - -int spd_read_byte(unsigned int device, unsigned int address); - - -int spd_read_byte(u32 device, u32 address) -{ - return do_smbus_read_byte(SMBUS_IO_BASE, device, address); -} - -void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) -{ - struct sys_info *sysinfo = get_sysinfo(); - static const u8 spd_addr[] = {RC00, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, }; - u32 bsp_apicid = 0, val; - msr_t msr; - - timestamp_init(timestamp_get()); - timestamp_add_now(TS_START_ROMSTAGE); - - if (!cpu_init_detectedx && boot_cpu()) { - /* Nothing special needs to be done to find bus 0 */ - /* Allow the HT devices to be found */ - /* mov bsp to bus 0xff when > 8 nodes */ - set_bsp_node_CHtExtNodeCfgEn(); - enumerate_ht_chain(); - sb7xx_51xx_pci_port80(); - } - - post_code(0x30); - - if (bist == 0) { - bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo); /* mmconf is inited in init_cpus */ - /* All cores run this but the BSP(node0,core0) is the only core that returns. */ - } - - post_code(0x32); - - enable_rs780_dev8(); - sb7xx_51xx_lpc_init(); - - fintek_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); - - console_init(); - - /* Halt if there was a built in self test failure */ - report_bist_failure(bist); - - // Load MPB - val = cpuid_eax(1); - printk(BIOS_DEBUG, "BSP Family_Model: %08x\n", val); - printk(BIOS_DEBUG, "*sysinfo range: [%p,%p]\n",sysinfo,sysinfo+1); - printk(BIOS_DEBUG, "bsp_apicid = %02x\n", bsp_apicid); - printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx); - - /* Setup sysinfo defaults */ - set_sysinfo_in_ram(0); - - update_microcode(val); - - post_code(0x33); - - cpuSetAMDMSR(0); - post_code(0x34); - - amd_ht_init(sysinfo); - post_code(0x35); - - /* Setup nodes PCI space and start core 0 AP init. */ - finalize_node_setup(sysinfo); - - /* Setup any mainboard PCI settings etc. */ - setup_mb_resource_map(); - post_code(0x36); - - /* wait for all the APs core0 started by finalize_node_setup. */ - /* FIXME: A bunch of cores are going to start output to serial at once. - It would be nice to fixup prink spinlocks for ROM XIP mode. - I think it could be done by putting the spinlock flag in the cache - of the BSP located right after sysinfo. - */ - wait_all_core0_started(); - - #if CONFIG(LOGICAL_CPUS) - /* Core0 on each node is configured. Now setup any additional cores. */ - printk(BIOS_DEBUG, "start_other_cores()\n"); - start_other_cores(bsp_apicid); - post_code(0x37); - wait_all_other_cores_started(bsp_apicid); - #endif - - post_code(0x38); - - /* run _early_setup before soft-reset. */ - rs780_early_setup(); - sb7xx_51xx_early_setup(); - -#if CONFIG(SET_FIDVID) - msr = rdmsr(MSR_COFVID_STS); - printk(BIOS_DEBUG, "\nBegin FIDVID MSR 0xc0010071 0x%08x 0x%08x\n", msr.hi, msr.lo); - - /* FIXME: The sb fid change may survive the warm reset and only - need to be done once.*/ - enable_fid_change_on_sb(sysinfo->sbbusn, sysinfo->sbdn); - - post_code(0x39); - - if (!warm_reset_detect(0)) { // BSP is node 0 - init_fidvid_bsp(bsp_apicid, sysinfo->nodes); - } else { - init_fidvid_stage2(bsp_apicid, 0); // BSP is node 0 - } - - post_code(0x3A); - - /* show final fid and vid */ - msr = rdmsr(MSR_COFVID_STS); - printk(BIOS_DEBUG, "End FIDVIDMSR 0xc0010071 0x%08x 0x%08x\n", msr.hi, msr.lo); -#endif - - rs780_htinit(); - - /* Reset for HT, FIDVID, PLL and errata changes to take affect. */ - if (!warm_reset_detect(0)) { - printk(BIOS_INFO, "...WARM RESET...\n\n\n"); - soft_reset(); - die("After soft_reset - shouldn't see this message!!!\n"); - } - - post_code(0x3B); - - /* It's the time to set ctrl in sysinfo now; */ - printk(BIOS_DEBUG, "fill_mem_ctrl()\n"); - fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr); - - post_code(0x40); - - raminit_amdmct(sysinfo); - - cbmem_initialize_empty(); - post_code(0x41); - - amdmct_cbmem_store_info(sysinfo); - - sb7xx_51xx_before_pci_init(); - - post_code(0x42); -} - -/** - * BOOL AMD_CB_ManualBUIDSwapList(u8 Node, u8 Link, u8 **List) - * Description: - * This routine is called every time a non-coherent chain is processed. - * BUID assignment may be controlled explicitly on a non-coherent chain. Provide a - * swap list. The first part of the list controls the BUID assignment and the - * second part of the list provides the device to device linking. Device orientation - * can be detected automatically, or explicitly. See documentation for more details. - * - * Automatic non-coherent init assigns BUIDs starting at 1 and incrementing sequentially - * based on each device's unit count. - * - * Parameters: - * @param[in] node = The node on which this chain is located - * @param[in] link = The link on the host for this chain - * @param[out] List = supply a pointer to a list - */ -BOOL AMD_CB_ManualBUIDSwapList (u8 node, u8 link, const u8 **List) -{ - static const u8 swaplist[] = { 0xFF, CONFIG_HT_CHAIN_UNITID_BASE, CONFIG_HT_CHAIN_END_UNITID_BASE, 0xFF }; - /* If the BUID was adjusted in early_ht we need to do the manual override */ - if ((CONFIG_HT_CHAIN_UNITID_BASE != 0) && (CONFIG_HT_CHAIN_END_UNITID_BASE != 0)) { - printk(BIOS_DEBUG, "AMD_CB_ManualBUIDSwapList()\n"); - if ((node == 0) && (link == 0)) { /* BSP SB link */ - *List = swaplist; - return 1; - } - } - - return 0; -} diff --git a/src/mainboard/msi/ms9652_fam10/Kconfig b/src/mainboard/msi/ms9652_fam10/Kconfig deleted file mode 100644 index 22f655a116..0000000000 --- a/src/mainboard/msi/ms9652_fam10/Kconfig +++ /dev/null @@ -1,83 +0,0 @@ -if BOARD_MSI_MS9652_FAM10 - -config BOARD_SPECIFIC_OPTIONS - def_bool y - select CPU_AMD_SOCKET_F_1207 - select DIMM_DDR2 - select DIMM_REGISTERED - select NORTHBRIDGE_AMD_AMDFAM10 - select SOUTHBRIDGE_NVIDIA_MCP55 - select MCP55_USE_NIC - select MCP55_USE_AZA - select SUPERIO_WINBOND_W83627EHG - select HAVE_PIRQ_TABLE - select HAVE_MP_TABLE - select HAVE_ACPI_TABLES - select HAVE_OPTION_TABLE - select BOARD_ROMSIZE_KB_512 - select ENABLE_APIC_EXT_ID - select SB_HT_CHAIN_UNITID_OFFSET_ONLY - select LIFT_BSP_APIC_ID - select IOAPIC - select SMP - select POWER_STATE_DEFAULT_ON_AFTER_FAILURE - -config MAINBOARD_DIR - string - default msi/ms9652_fam10 - -config DCACHE_RAM_BASE - hex - default 0xc4000 - -config DCACHE_RAM_SIZE - hex - default 0x0c000 - -# Define to 0 because the IRQ slot count is -# determined dynamically for this board. -config IRQ_SLOT_COUNT - int - default 0 - -config MAX_CPUS - int - default 8 - -config MAX_PHYSICAL_CPUS - int - default 2 - -config USE_OPTION_TABLE - bool - default n - -config MAINBOARD_PART_NUMBER - string - default "MS-9652" - -config DEFAULT_CONSOLE_LOGLEVEL - int - default 9 - -config USBDEBUG - bool - default n - -config HT_CHAIN_UNITID_BASE - hex - default 0x20 - -config HT_CHAIN_END_UNITID_BASE - hex - default 0x00 - -config APIC_ID_OFFSET - hex - default 0x00 - -config MCP55_PCI_E_X_0 - int - default 1 - -endif # BOARD_MSI_MS9652_FAM10 diff --git a/src/mainboard/msi/ms9652_fam10/Kconfig.name b/src/mainboard/msi/ms9652_fam10/Kconfig.name deleted file mode 100644 index 3c6659c857..0000000000 --- a/src/mainboard/msi/ms9652_fam10/Kconfig.name +++ /dev/null @@ -1,2 +0,0 @@ -config BOARD_MSI_MS9652_FAM10 - bool "MS-9652 Fam10 (Speedster K9ND)" diff --git a/src/mainboard/msi/ms9652_fam10/Makefile.inc b/src/mainboard/msi/ms9652_fam10/Makefile.inc deleted file mode 100644 index 91d4b39c32..0000000000 --- a/src/mainboard/msi/ms9652_fam10/Makefile.inc +++ /dev/null @@ -1,16 +0,0 @@ -# -# This file is part of the coreboot project. -# -# This program is free software; you can redistribute it and/or modify -# it under the terms of the GNU General Public License as published by -# the Free Software Foundation; version 2 of the License. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# - -romstage-y += resourcemap.c - -ramstage-y += get_bus_conf.c diff --git a/src/mainboard/msi/ms9652_fam10/acpi/util.asl b/src/mainboard/msi/ms9652_fam10/acpi/util.asl deleted file mode 100644 index d272233d2d..0000000000 --- a/src/mainboard/msi/ms9652_fam10/acpi/util.asl +++ /dev/null @@ -1,329 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright 2005 AMD - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -//AMD k8 util for BUSB and res range - -Scope (\_SB) -{ - - Name (OSTB, Ones) - Method (OSVR, 0, NotSerialized) - { - If (LEqual (^OSTB, Ones)) - { - Store (0x00, ^OSTB) - } - - Return (^OSTB) - } - - Method (SEQL, 2, Serialized) - { - Store (SizeOf (Arg0), Local0) - Store (SizeOf (Arg1), Local1) - If (LNot (LEqual (Local0, Local1))) { Return (Zero) } - - Name (BUF0, Buffer (Local0) {}) - Store (Arg0, BUF0) - Name (BUF1, Buffer (Local0) {}) - Store (Arg1, BUF1) - Store (Zero, Local2) - While (LLess (Local2, Local0)) - { - Store (DerefOf (Index (BUF0, Local2)), Local3) - Store (DerefOf (Index (BUF1, Local2)), Local4) - If (LNot (LEqual (Local3, Local4))) { Return (Zero) } - - Increment (Local2) - } - - Return (One) - } - - - Method (DADD, 2, NotSerialized) - { - Store(Arg1, Local0) - Store(Arg0, Local1) - Add(ShiftLeft(Local1,16), Local0, Local0) - Return (Local0) - } - - - Method (GHCE, 1, NotSerialized) // check if the HC enabled - { - Store (DerefOf (Index (\_SB.PCI0.HCLK, Arg0)), Local1) - if (LEqual (And(Local1, 0x01), 0x01)) { Return (0x0F) } - Else { Return (0x00) } - } - - Method (GHCN, 1, NotSerialized) // get the node num for the HC - { - Store (0x00, Local0) - Store (DerefOf (Index (\_SB.PCI0.HCLK, Arg0)), Local1) - Store (ShiftRight(And (Local1, 0xf0), 0x04), Local0) - Return (Local0) - } - - Method (GHCL, 1, NotSerialized) // get the link num on node for the HC - { - Store (0x00, Local0) - Store (DerefOf (Index (\_SB.PCI0.HCLK, Arg0)), Local1) - Store (ShiftRight(And (Local1, 0xf00), 0x08), Local0) - Return (Local0) - } - - Method (GHCD, 2, NotSerialized) // get the unit id base for the HT device in HC - { - Store (0x00, Local0) - Store (DerefOf (Index (\_SB.PCI0.HCDN, Arg0)), Local1) - Store (Arg1, Local2) // Arg1 could be 3, 2, 1, 0 - Multiply (Local2, 0x08, Local2) // change to 24, 16, 8, 0 - Store (And (ShiftRight(Local1, Local2), 0xff), Local0) - Return (Local0) - } - - /* GetBus(Node, Link) */ - Method (GBUS, 2, NotSerialized) - { - Store (0x00, Local0) - While (LLess (Local0, 0x04)) - { - Store (DerefOf (Index (\_SB.PCI0.BUSN, Local0)), Local1) - If (LEqual (And (Local1, 0x03), 0x03)) - { - If (LEqual (Arg0, ShiftRight (And (Local1, 0x70), 0x04))) - { - If (LOr (LEqual (Arg1, 0xFF), LEqual (Arg1, ShiftRight (And (Local1, 0x0300), 0x08)))) - { - Return (ShiftRight (And (Local1, 0x00FF0000), 0x10)) - } - } - } - - Increment (Local0) - } - - Return (0x00) - } - - /* GetBusResources(Node, Link) */ - Method (GWBN, 2, Serialized) - { - Name (BUF0, ResourceTemplate () - { - WordBusNumber (ResourceProducer, MinFixed, MaxFixed, PosDecode, - 0x0000, // Address Space Granularity - 0x0000, // Address Range Minimum - 0x0000, // Address Range Maximum - 0x0000, // Address Translation Offset - 0x0001,,,) - }) - CreateWordField (BUF0, 0x08, BMIN) - CreateWordField (BUF0, 0x0A, BMAX) - CreateWordField (BUF0, 0x0E, BLEN) - Store (0x00, Local0) - While (LLess (Local0, 0x04)) - { - Store (DerefOf (Index (\_SB.PCI0.BUSN, Local0)), Local1) - If (LEqual (And (Local1, 0x03), 0x03)) - { - If (LEqual (Arg0, ShiftRight (And (Local1, 0x70), 0x04))) - { - If (LOr (LEqual (Arg1, 0xFF), LEqual (Arg1, ShiftRight (And (Local1, 0x0300), 0x08)))) - { - Store (ShiftRight (And (Local1, 0x00FF0000), 0x10), BMIN) - Store (ShiftRight (Local1, 0x18), BMAX) - Subtract (BMAX, BMIN, BLEN) - Increment (BLEN) - Return (RTAG (BUF0)) - } - } - } - - Increment (Local0) - } - - Return (RTAG (BUF0)) - } - - /* GetMemoryResources(Node, Link) */ - Method (GMEM, 2, Serialized) - { - Name (BUF0, ResourceTemplate () - { - DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, NonCacheable, ReadWrite, - 0x00000000, // Address Space Granularity - 0x00000000, // Address Range Minimum - 0x00000000, // Address Range Maximum - 0x00000000, // Address Translation Offset - 0x00000001,,, - , AddressRangeMemory, TypeStatic) - }) - CreateDWordField (BUF0, 0x0A, MMIN) - CreateDWordField (BUF0, 0x0E, MMAX) - CreateDWordField (BUF0, 0x16, MLEN) - Store (0x00, Local0) - Store (0x00, Local4) - Store (0x00, Local3) - While (LLess (Local0, 0x10)) - { - /* Get value of the first register */ - Store (DerefOf (Index (\_SB.PCI0.MMIO, Local0)), Local1) - Increment (Local0) - Store (DerefOf (Index (\_SB.PCI0.MMIO, Local0)), Local2) - If (LEqual (And (Local1, 0x03), 0x03)) /* Pair enabled? */ - { - If (LEqual (Arg0, And (Local2, 0x07))) /* Node matches? */ - { - /* If Link Matches (or we got passed 0xFF) */ - If (LOr (LEqual (Arg1, 0xFF), LEqual (Arg1, ShiftRight (And (Local2, 0x30), 0x04)))) - { - /* Extract the Base and Limit values */ - Store (ShiftLeft (And (Local1, 0xFFFFFF00), 0x08), MMIN) - Store (ShiftLeft (And (Local2, 0xFFFFFF00), 0x08), MMAX) - Or (MMAX, 0xFFFF, MMAX) - Subtract (MMAX, MMIN, MLEN) - Increment (MLEN) - - If (Local4) /* I've already done this once */ - { - Concatenate (RTAG (BUF0), Local3, Local5) - Store (Local5, Local3) - } - Else - { - Store (RTAG (BUF0), Local3) - } - - Increment (Local4) - } - } - } - - Increment (Local0) - } - - If (LNot (Local4)) /* No resources for this node and link. */ - { - Store (RTAG (BUF0), Local3) - } - - Return (Local3) - } - - /* GetIOResources(Node, Link) */ - Method (GIOR, 2, Serialized) - { - Name (BUF0, ResourceTemplate () - { - DWordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, - 0x00000000, // Address Space Granularity - 0x00000000, // Address Range Minimum - 0x00000000, // Address Range Maximum - 0x00000000, // Address Translation Offset - 0x00000001,,, - , TypeStatic) - }) - CreateDWordField (BUF0, 0x0A, PMIN) - CreateDWordField (BUF0, 0x0E, PMAX) - CreateDWordField (BUF0, 0x16, PLEN) - Store (0x00, Local0) - Store (0x00, Local4) - Store (0x00, Local3) - While (LLess (Local0, 0x08)) - { - Store (DerefOf (Index (\_SB.PCI0.PCIO, Local0)), Local1) - Increment (Local0) - Store (DerefOf (Index (\_SB.PCI0.PCIO, Local0)), Local2) - If (LEqual (And (Local1, 0x03), 0x03)) /* Pair enabled? */ - { - If (LEqual (Arg0, And (Local2, 0x07))) /* Node matches? */ - { - /* If Link Matches (or we got passed 0xFF) */ - If (LOr (LEqual (Arg1, 0xFF), LEqual (Arg1, ShiftRight (And (Local2, 0x30), 0x04)))) - { - /* Extract the Base and Limit values */ - Store (And (Local1, 0x01FFF000), PMIN) - Store (And (Local2, 0x01FFF000), PMAX) - Or (PMAX, 0x0FFF, PMAX) - Subtract (PMAX, PMIN, PLEN) - Increment (PLEN) - - If (Local4) /* I've already done this once */ - { - Concatenate (RTAG (BUF0), Local3, Local5) - Store (Local5, Local3) - } - Else - { - If (LGreater (PMAX, PMIN)) - { - If (LOr (LAnd (LEqual (Arg1, 0xFF), LEqual (Arg0, 0x00)), LEqual (Arg1, \_SB.PCI0.SBLK))) - { - Store (0x0D00, PMIN) - Subtract (PMAX, PMIN, PLEN) - Increment (PLEN) - } - - Store (RTAG (BUF0), Local3) - Increment (Local4) - } - - If (And (Local1, 0x10)) - { - Store (0x03B0, PMIN) - Store (0x03DF, PMAX) - Store (0x30, PLEN) - - If (Local4) - { - Concatenate (RTAG (BUF0), Local3, Local5) - Store (Local5, Local3) - } - Else - { - Store (RTAG (BUF0), Local3) - } - } - } - - Increment (Local4) - } - } - } - - Increment (Local0) - } - - If (LNot (Local4)) /* No resources for this node and link. */ - { - Store (RTAG (BUF0), Local3) - } - - Return (Local3) - } - - Method (RTAG, 1, NotSerialized) - { - Store (Arg0, Local0) - Store (SizeOf (Local0), Local1) - Subtract (Local1, 0x02, Local1) - Multiply (Local1, 0x08, Local1) - CreateField (Local0, 0x00, Local1, RETB) - Store (RETB, Local2) - Return (Local2) - } -} diff --git a/src/mainboard/msi/ms9652_fam10/acpi_tables.c b/src/mainboard/msi/ms9652_fam10/acpi_tables.c deleted file mode 100644 index 9f230df518..0000000000 --- a/src/mainboard/msi/ms9652_fam10/acpi_tables.c +++ /dev/null @@ -1,80 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Written by Stefan Reinauer . - * ACPI FADT, FACS, and DSDT table support added by - * - * Copyright (C) 2004 Stefan Reinauer - * Copyright (C) 2005 Nick Barker - * Copyright (C) 2007, 2008 Rudolf Marek - * Copyright (C) 2009 Harald Gutmann - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include -#include -#include -#include -#include "mb_sysconf.h" - -unsigned long acpi_fill_madt(unsigned long current) -{ - unsigned int gsi_base = 0x18; - struct mb_sysconf_t *m; - //extern unsigned char bus_mcp55[8]; - //extern unsigned apicid_mcp55; - - unsigned int sbdn; - struct resource *res; - struct device *dev; - - sbdn = sysconf.sbdn; - m = sysconf.mb; - - /* Create all subtables for processors. */ - current = acpi_create_madt_lapics(current); - - /* Write SB IOAPIC. */ - dev = dev_find_slot(m->bus_mcp55[0], PCI_DEVFN(sbdn+ 0x1,0)); - if (dev) { - res = find_resource(dev, PCI_BASE_ADDRESS_1); - if (res) { - current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, - m->apicid_mcp55, res->base, 0); - } - } - - /* Write NB IOAPIC. */ - dev = dev_find_slot(m->bus_mcp55[0], PCI_DEVFN(sbdn+ 0x12,1)); - if (dev) { - res = find_resource(dev, PCI_BASE_ADDRESS_1); - if (res) { - current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, - m->apicid_mcp55++, res->base, gsi_base); - } - } - - /* IRQ9 ACPI active low. */ - current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) - current, 0, 9, 9, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW); - - /* IRQ0 -> APIC IRQ2. */ - current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) - current, 0, 0, 2, 0x0); - - /* Create all subtables for processors. */ - current = acpi_create_madt_lapic_nmis(current, - MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, 1); - - return current; -} diff --git a/src/mainboard/msi/ms9652_fam10/board_info.txt b/src/mainboard/msi/ms9652_fam10/board_info.txt deleted file mode 100644 index eb2dda33a8..0000000000 --- a/src/mainboard/msi/ms9652_fam10/board_info.txt +++ /dev/null @@ -1,2 +0,0 @@ -Category: desktop -Release year: 2007 diff --git a/src/mainboard/msi/ms9652_fam10/cmos.layout b/src/mainboard/msi/ms9652_fam10/cmos.layout deleted file mode 100644 index 331e0162bb..0000000000 --- a/src/mainboard/msi/ms9652_fam10/cmos.layout +++ /dev/null @@ -1,102 +0,0 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2015 Timothy Pearson , Raptor Engineering -## Copyright (C) 2007 AMD -## Written by Yinghai Lu for AMD. -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; either version 2 of the License, or -## (at your option) any later version. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## - -entries - -0 384 r 0 reserved_memory -384 1 e 4 boot_option -388 4 h 0 reboot_counter -393 3 r 0 unused -#394 7 unused -401 1 e 1 interleave_chip_selects -402 1 e 1 interleave_nodes -403 1 e 1 interleave_memory_channels -404 2 e 8 max_mem_clock -406 1 e 2 multi_core -412 4 e 6 debug_level -416 5 e 10 ecc_scrub_rate -440 4 e 9 slow_cpu -444 1 e 1 nmi -445 1 e 1 gart -446 1 e 1 power_on_after_fail -456 1 e 1 ECC_memory -457 1 e 1 ECC_redirection -728 256 h 0 user_data -984 16 h 0 check_sum -# Reserve the extended AMD configuration registers -1000 24 r 0 amd_reserved - - - -enumerations - -#ID value text -1 0 Disable -1 1 Enable -2 0 Enable -2 1 Disable -4 0 Fallback -4 1 Normal -6 0 Emergency -6 1 Alert -6 2 Critical -6 3 Error -6 4 Warning -6 5 Notice -6 6 Information -6 7 Debug -6 8 Spew -8 0 DDR2-800 -8 1 DDR2-667 -8 2 DDR2-533 -8 3 DDR2-400 -9 0 off -9 1 87.5% -9 2 75.0% -9 3 62.5% -9 4 50.0% -9 5 37.5% -9 6 25.0% -9 7 12.5% -10 0 Disabled -10 1 40ns -10 2 80ns -10 3 160ns -10 4 320ns -10 5 640ns -10 6 1.28us -10 7 2.56us -10 8 5.12us -10 9 10.2us -10 10 20.5us -10 11 41us -10 12 81.9us -10 13 163.8us -10 14 327.7us -10 15 655.4us -10 16 1.31ms -10 17 2.62ms -10 18 5.24ms -10 19 10.49ms -10 20 20.97sms -10 21 42ms -10 22 84ms - -checksums - -checksum 392 983 984 diff --git a/src/mainboard/msi/ms9652_fam10/devicetree.cb b/src/mainboard/msi/ms9652_fam10/devicetree.cb deleted file mode 100644 index c6dae6d451..0000000000 --- a/src/mainboard/msi/ms9652_fam10/devicetree.cb +++ /dev/null @@ -1,165 +0,0 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2007 AMD -## Written by Yinghai Lu for AMD. -## Copyright (C) 2010 Raptor Engineering -## Written by Timothy Pearson for Raptor Engineering. -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; either version 2 of the License, or -## (at your option) any later version. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## - -chip northbridge/amd/amdfam10/root_complex # Root complex - device cpu_cluster 0 on # (L)APIC cluster - chip cpu/amd/socket_F_1207 # CPU socket - device lapic 0 on end # Local APIC of the CPU - end - end - device domain 0 on # PCI domain - subsystemid 0x1462 0x9652 inherit - chip northbridge/amd/amdfam10 # Northbridge / RAM controller - device pci 18.0 on # Link 0 - chip southbridge/nvidia/mcp55 # Southbridge - device pci 0.0 on end # HT - device pci 1.0 on # LPC - chip superio/winbond/w83627ehg # Super I/O - device pnp 2e.0 on # Floppy - io 0x60 = 0x3f0 - irq 0x70 = 6 - drq 0x74 = 2 - end - device pnp 2e.1 off # Parallel port - io 0x60 = 0x378 - irq 0x70 = 7 - end - device pnp 2e.2 on # Com1 - io 0x60 = 0x3f8 - irq 0x70 = 4 - end - device pnp 2e.3 on # Com2 - io 0x60 = 0x2f8 - irq 0x70 = 3 - end - device pnp 2e.5 on # PS/2 keyboard & mouse - io 0x60 = 0x60 - io 0x62 = 0x64 - irq 0x70 = 1 - irq 0x72 = 12 - end - device pnp 2e.106 off # Serial flash interface (SFI) - io 0x60 = 0x100 - end - device pnp 2e.007 off # GPIO 1 - end - device pnp 2e.107 on # Game port - io 0x60 = 0x220 - end - device pnp 2e.207 on # MIDI - io 0x62 = 0x330 - irq 0x70 = 0xa - end - device pnp 2e.307 off # GPIO 6 - end - device pnp 2e.8 off # WDTO#, PLED - end - device pnp 2e.009 off # GPIO 2 - end - device pnp 2e.109 off # GPIO 3 - end - device pnp 2e.209 off # GPIO 4 - end - device pnp 2e.309 off # GPIO 5 - end - device pnp 2e.a off end # ACPI - device pnp 2e.b on # Hardware monitor - io 0x60 = 0x290 - irq 0x70 = 5 - end - end - end - device pci 1.1 on # SM 0 - chip drivers/generic/generic # DIMM 0-0-0 - device i2c 50 on end - end - chip drivers/generic/generic # DIMM 0-0-1 - device i2c 51 on end - end - chip drivers/generic/generic # DIMM 0-1-0 - device i2c 52 on end - end - chip drivers/generic/generic # DIMM 0-1-1 - device i2c 53 on end - end - chip drivers/generic/generic # DIMM 1-0-0 - device i2c 54 on end - end - chip drivers/generic/generic # DIMM 1-0-1 - device i2c 55 on end - end - chip drivers/generic/generic # DIMM 1-1-0 - device i2c 56 on end - end - chip drivers/generic/generic # DIMM 1-1-1 - device i2c 57 on end - end - end - device pci 1.1 on # SM 1 - # PCI device SMBus address will - # depend on addon PCI device, do - # we need to scan_smbus_bus? - # chip drivers/generic/generic # PCIXA slot 1 - # device i2c 50 on end - # end - # chip drivers/generic/generic # PCIXB slot 1 - # device i2c 51 on end - # end - # chip drivers/generic/generic # PCIXB slot 2 - # device i2c 52 on end - # end - # chip drivers/generic/generic # PCI slot 1 - # device i2c 53 on end - # end - # chip drivers/generic/generic # Master MCP55 PCI-E - # device i2c 54 on end - # end - # chip drivers/generic/generic # Slave MCP55 PCI-E - # device i2c 55 on end - # end - # chip drivers/generic/generic # MAC EEPROM - # device i2c 51 on end - # end - end - device pci 2.0 on end # USB 1.1 - device pci 2.1 on end # USB 2 - device pci 4.0 on end # IDE - device pci 5.0 on end # SATA 0 - device pci 5.1 on end # SATA 1 - device pci 5.2 on end # SATA 2 - device pci 6.1 on end # AZA - device pci 8.0 on end # NIC - device pci 9.0 on end # NIC - register "ide0_enable" = "1" - register "sata0_enable" = "1" - register "sata1_enable" = "1" - # 1: SMBus under 2e.8, 2: SM0 3: SM1 - register "mac_eeprom_smbus" = "3" - register "mac_eeprom_addr" = "0x51" - end - end - device pci 18.0 on end # HT 1.0 - device pci 18.0 on end # HT 2.0 - device pci 18.1 on end - device pci 18.2 on end - device pci 18.3 on end - device pci 18.4 on end - end - end -end diff --git a/src/mainboard/msi/ms9652_fam10/dsdt.asl b/src/mainboard/msi/ms9652_fam10/dsdt.asl deleted file mode 100644 index 2115f4cc44..0000000000 --- a/src/mainboard/msi/ms9652_fam10/dsdt.asl +++ /dev/null @@ -1,298 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2004 Nick Barker - * Copyright (C) 2007, 2008 Rudolf Marek - * Copyright (C) 2009 Harald Gutmann - * - * ISA portions taken from QEMU acpi-dsdt.dsl. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -DefinitionBlock ("DSDT.aml", "DSDT", 1, OEM_ID, ACPI_TABLE_CREATOR, 1) -{ - #include "acpi/util.asl" - - /* For now only define 2 power states: - * - S0 which is fully on - * - S5 which is soft off - */ - Name (\_S0, Package () { 0x00, 0x00, 0x00, 0x00 }) - Name (\_S5, Package () { 0x07, 0x00, 0x00, 0x00 }) - - /* Root of the bus hierarchy */ - Scope (\_SB) - { - /* Top PCI device */ - Device (PCI0) - { - Name (_HID, EisaId ("PNP0A03")) - Name (_UID, 0x00) - Name (_BBN, 0x00) - - External (BUSN) - External (MMIO) - External (PCIO) - External (SBLK) - External (TOM1) - External (HCLK) - External (SBDN) - External (HCDN) - - Method (_CRS, 0, NotSerialized) - { - Name (BUF0, ResourceTemplate () - { - IO (Decode16, - 0x0CF8, // Address Range Minimum - 0x0CF8, // Address Range Maximum - 0x01, // Address Alignment - 0x08, // Address Length - ) - WordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, - 0x0000, // Address Space Granularity - 0x0000, // Address Range Minimum - 0x0CF7, // Address Range Maximum - 0x0000, // Address Translation Offset - 0x0CF8, // Address Length - ,, , TypeStatic) - }) - /* Methods bellow use SSDT to get actual MMIO regs - The IO ports are from 0xd00, optionally an VGA, - otherwise the info from MMIO is used. - */ - Concatenate (\_SB.GMEM (0x00, \_SB.PCI0.SBLK), BUF0, Local1) - Concatenate (\_SB.GIOR (0x00, \_SB.PCI0.SBLK), Local1, Local2) - Concatenate (\_SB.GWBN (0x00, \_SB.PCI0.SBLK), Local2, Local3) - Return (Local3) - } - - /* PCI Routing Table */ - Name (_PRT, Package () { - Package (0x04) { 0x0001FFFF, 0x01, 0x00, 0x0A }, /* 0x1 - 00:01.1 - IRQ 10 - SMBus */ - Package (0x04) { 0x0002FFFF, 0x00, 0x00, 0x16 }, /* 0x2 - 00:02.0 - IRQ 22 - USB */ - Package (0x04) { 0x0002FFFF, 0x01, 0x00, 0x17 }, /* 0x2 - 00:01.1 - IRQ 23 - USB */ - Package (0x04) { 0x0004FFFF, 0x00, 0x00, 0x15 }, /* 0x4 - 00:04.0 - IRQ 21 - IDE */ - Package (0x04) { 0x0005FFFF, 0x00, 0x00, 0x14 }, /* 0x5 - 00:05.0 - IRQ 20 - SATA */ - Package (0x04) { 0x0005FFFF, 0x01, 0x00, 0x15 }, /* 0x5 - 00:05.1 - IRQ 21 - SATA */ - Package (0x04) { 0x0005FFFF, 0x02, 0x00, 0x16 }, /* 0x5 - 00:05.2 - IRQ 22 - SATA */ - Package (0x04) { 0x0006FFFF, 0x01, 0x00, 0x17 }, /* 0x6 - 00:06.1 - IRQ 23 - HD Audio */ - Package (0x04) { 0x0008FFFF, 0x00, 0x00, 0x14 }, /* 0x8 - 00:08.0 - IRQ 20 - GBit Ethernet */ - }) - - Device (PEBF) /* PCI-E Bridge F */ - { - Name (_ADR, 0x000F0000) - Name (_UID, 0x00) - Name (_BBN, 0x07) - Name (_PRT, Package () { - Package (0x04) { 0x0000FFFF, 0x00, 0x00, 0x11 }, - Package (0x04) { 0x0000FFFF, 0x01, 0x00, 0x12 }, - Package (0x04) { 0x0000FFFF, 0x02, 0x00, 0x13 }, - Package (0x04) { 0x0000FFFF, 0x03, 0x00, 0x10 }, - }) - } - - Device (PEBE) /* PCI-E Bridge E */ - { - Name (_ADR, 0x000E0000) - Name (_UID, 0x00) - Name (_BBN, 0x06) - Name (_PRT, Package () { - Package (0x04) { 0x0000FFFF, 0x00, 0x00, 0x12 }, - Package (0x04) { 0x0000FFFF, 0x01, 0x00, 0x13 }, - Package (0x04) { 0x0000FFFF, 0x02, 0x00, 0x10 }, - Package (0x04) { 0x0000FFFF, 0x03, 0x00, 0x11 }, - }) - } - - Device (PEBD) /* PCI-E Bridge D */ - { - Name (_ADR, 0x000D0000) - Name (_UID, 0x00) - Name (_BBN, 0x05) - Name (_PRT, Package () { - Package (0x04) { 0x0000FFFF, 0x00, 0x00, 0x13 }, - Package (0x04) { 0x0000FFFF, 0x01, 0x00, 0x10 }, - Package (0x04) { 0x0000FFFF, 0x02, 0x00, 0x11 }, - Package (0x04) { 0x0000FFFF, 0x03, 0x00, 0x12 }, - }) - } - - Device (PEBC) /* PCI-E Bridge C */ - { - Name (_ADR, 0x000C0000) - Name (_UID, 0x00) - Name (_BBN, 0x04) - Name (_PRT, Package () { - Package (0x04) { 0x0000FFFF, 0x00, 0x00, 0x10 }, - Package (0x04) { 0x0000FFFF, 0x01, 0x00, 0x11 }, - Package (0x04) { 0x0000FFFF, 0x02, 0x00, 0x12 }, - Package (0x04) { 0x0000FFFF, 0x03, 0x00, 0x13 }, - }) - } - - Device (PEBB) /* PCI-E Bridge B */ - { - Name (_ADR, 0x000B0000) - Name (_UID, 0x00) - Name (_BBN, 0x03) - Name (_PRT, Package () { - Package (0x04) { 0x0000FFFF, 0x00, 0x00, 0x11 }, - Package (0x04) { 0x0000FFFF, 0x01, 0x00, 0x12 }, - Package (0x04) { 0x0000FFFF, 0x02, 0x00, 0x13 }, - Package (0x04) { 0x0000FFFF, 0x03, 0x00, 0x10 }, - }) - } - - Device (PEBA) /* PCI-E Bridge A */ - { - Name (_ADR, 0x000A0000) - Name (_UID, 0x00) - Name (_BBN, 0x02) - Name (_PRT, Package () { - Package (0x04) { 0x0000FFFF, 0x00, 0x00, 0x12 }, - Package (0x04) { 0x0000FFFF, 0x01, 0x00, 0x13 }, - Package (0x04) { 0x0000FFFF, 0x02, 0x00, 0x10 }, - Package (0x04) { 0x0000FFFF, 0x03, 0x00, 0x11 }, - }) - } - - Device (PCID) /* PCI Device */ - { - Name (_ADR, 0x00060000) - Name (_UID, 0x00) - Name (_BBN, 0x01) - Name (_PRT, Package () { - Package (0x04) { 0x0006FFFF, 0x00, 0x00, 0x12 }, - Package (0x04) { 0x0006FFFF, 0x01, 0x00, 0x13 }, - Package (0x04) { 0x0006FFFF, 0x02, 0x00, 0x10 }, - Package (0x04) { 0x0006FFFF, 0x03, 0x00, 0x11 }, - Package (0x04) { 0x0007FFFF, 0x00, 0x00, 0x13 }, /* PCI slot 1 */ - Package (0x04) { 0x0007FFFF, 0x01, 0x00, 0x10 }, - Package (0x04) { 0x0007FFFF, 0x02, 0x00, 0x11 }, - Package (0x04) { 0x0007FFFF, 0x03, 0x00, 0x12 }, - Package (0x04) { 0x0008FFFF, 0x00, 0x00, 0x10 }, /* PCI slot 2 */ - Package (0x04) { 0x0008FFFF, 0x01, 0x00, 0x11 }, - Package (0x04) { 0x0008FFFF, 0x02, 0x00, 0x12 }, - Package (0x04) { 0x0008FFFF, 0x03, 0x00, 0x13 }, - Package (0x04) { 0x0009FFFF, 0x00, 0x00, 0x11 }, - Package (0x04) { 0x0009FFFF, 0x01, 0x00, 0x12 }, - Package (0x04) { 0x0009FFFF, 0x02, 0x00, 0x13 }, - Package (0x04) { 0x0009FFFF, 0x03, 0x00, 0x10 }, - Package (0x04) { 0x000AFFFF, 0x00, 0x00, 0x12 }, /* FireWire */ - Package (0x04) { 0x000AFFFF, 0x01, 0x00, 0x13 }, - Package (0x04) { 0x000AFFFF, 0x02, 0x00, 0x10 }, - Package (0x04) { 0x000AFFFF, 0x03, 0x00, 0x11 }, - }) - } - } - - Device (ISA) { - Name (_ADR, 0x000010000) - - /* PS/2 keyboard (seems to be important for WinXP install) */ - Device (KBD) - { - Name (_HID, EisaId ("PNP0303")) - Method (_STA, 0, NotSerialized) - { - Return (0x0f) - } - Method (_CRS, 0, NotSerialized) - { - Name (TMP0, ResourceTemplate () { - IO (Decode16, 0x0060, 0x0060, 0x01, 0x01) - IO (Decode16, 0x0064, 0x0064, 0x01, 0x01) - IRQNoFlags () {1} - }) - Return (TMP0) - } - } - - /* PS/2 mouse */ - Device (MOU) - { - Name (_HID, EisaId ("PNP0F13")) - Method (_STA, 0, NotSerialized) - { - Return (0x0f) - } - Method (_CRS, 0, NotSerialized) - { - Name (TMP1, ResourceTemplate () { - IO (Decode16, 0x0060, 0x0060, 0x01, 0x01) - IO (Decode16, 0x0064, 0x0064, 0x01, 0x01) - IRQNoFlags () {12} - }) - Return (TMP1) - } - } - - /* PS/2 floppy controller */ - Device (FDC0) - { - Name (_HID, EisaId ("PNP0700")) - Method (_STA, 0, NotSerialized) - { - Return (0x0f) - } - Method (_CRS, 0, NotSerialized) - { - Name (BUF0, ResourceTemplate () { - IO (Decode16, 0x03F0, 0x03F0, 0x01, 0x06) - IO (Decode16, 0x03F7, 0x03F7, 0x01, 0x01) - IRQNoFlags () {6} - DMA (Compatibility, NotBusMaster, Transfer8) {2} - }) - Return (BUF0) - } - } - /* Parallel Port */ - Device (LPT1) - { - Name (_HID, EisaId ("PNP0400")) - Method (_STA, 0, NotSerialized) - { - Return (0x0f) - } - Method (_CRS, 0, NotSerialized) - { - Name (BUF1, ResourceTemplate () { - IO (Decode16, 0x0378, 0x0378, 0x01, 0x08) - IRQNoFlags () {7} - }) - Return (BUF1) - } - } - /* Parallel Port ECP */ - Device (ECP1) - { - Name (_HID, EisaId ("PNP0401")) - Method (_STA, 0, NotSerialized) - { - Return (0x0f) - } - Method (_CRS, 0, NotSerialized) - { - Name (BUF1, ResourceTemplate () { - IO (Decode16, 0x0378, 0x0378, 0x01, 0x04) - IO (Decode16, 0x0778, 0x0778, 0x01, 0x04) - IRQNoFlags() {7} - DMA (Compatibility, NotBusMaster, Transfer8) {0,1,3} - }) - Return (BUF1) - } - } - } - } -} diff --git a/src/mainboard/msi/ms9652_fam10/get_bus_conf.c b/src/mainboard/msi/ms9652_fam10/get_bus_conf.c deleted file mode 100644 index d13a8130ed..0000000000 --- a/src/mainboard/msi/ms9652_fam10/get_bus_conf.c +++ /dev/null @@ -1,80 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007 AMD - * Written by Yinghai Lu for AMD. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include -#include -#include -#include - -#include - -#include -#include "mb_sysconf.h" - -// Global variables for MB layouts and these will be shared by irqtable mptable and acpi_tables -struct mb_sysconf_t mb_sysconf; - -void get_bus_conf(void) -{ - unsigned int apicid_base; - struct mb_sysconf_t *m; - - struct device *dev; - int i; - - - sysconf.mb = &mb_sysconf; - - m = sysconf.mb; - memset(m, 0, sizeof(struct mb_sysconf_t)); - - get_default_pci1234(32); - - sysconf.sbdn = (sysconf.hcdn[0] & 0xff); // first byte of first chain - m->bus_mcp55[0] = (sysconf.pci1234[0] >> 12) & 0xff; - - /* MCP55 */ - dev = dev_find_slot(m->bus_mcp55[0], PCI_DEVFN(sysconf.sbdn + 0x06,0)); - if (dev) { - m->bus_mcp55[1] = pci_read_config8(dev, PCI_SECONDARY_BUS); - } - else { - printk(BIOS_DEBUG, "ERROR - could not find PCI 1:%02x.0, using defaults\n", sysconf.sbdn + 0x06); - } - - for (i = 2; i < 8; i++) { - dev = dev_find_slot(m->bus_mcp55[0], PCI_DEVFN(sysconf.sbdn + 0x0a + i - 2, 0)); - if (dev) { - m->bus_mcp55[i] = pci_read_config8(dev, PCI_SECONDARY_BUS); - } - else { - printk(BIOS_DEBUG, "ERROR - could not find PCI %02x:%02x.0, using defaults\n", m->bus_mcp55[0], sysconf.sbdn + 0x0a + i - 2); - } - } - -/*I/O APICs: APIC ID Version State Address*/ - if (CONFIG(LOGICAL_CPUS)) { - apicid_base = get_apicid_base(1); - printk(BIOS_SPEW, "CONFIG_LOGICAL_CPUS == 1: apicid_base: %08x\n", apicid_base); - } else { - apicid_base = CONFIG_MAX_PHYSICAL_CPUS; - printk(BIOS_SPEW, "CONFIG_LOGICAL_CPUS == 0: apicid_base: %08x\n", apicid_base); - } - m->apicid_mcp55 = apicid_base+0; -} diff --git a/src/mainboard/msi/ms9652_fam10/hda_verb.c b/src/mainboard/msi/ms9652_fam10/hda_verb.c deleted file mode 100644 index 5d088790a5..0000000000 --- a/src/mainboard/msi/ms9652_fam10/hda_verb.c +++ /dev/null @@ -1,20 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include - -const u32 cim_verb_data[0] = {}; - -const u32 pc_beep_verbs[0] = {}; - -AZALIA_ARRAY_SIZES; diff --git a/src/mainboard/msi/ms9652_fam10/irq_tables.c b/src/mainboard/msi/ms9652_fam10/irq_tables.c deleted file mode 100644 index 69327dcafa..0000000000 --- a/src/mainboard/msi/ms9652_fam10/irq_tables.c +++ /dev/null @@ -1,137 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007 AMD - * Written by Yinghai Lu for AMD. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include -#include -#include - -#include -#include "mb_sysconf.h" - -static void write_pirq_info(struct irq_info *pirq_info, uint8_t bus, - uint8_t devfn, uint8_t link0, uint16_t bitmap0, - uint8_t link1, uint16_t bitmap1, uint8_t link2, - uint16_t bitmap2, uint8_t link3, uint16_t bitmap3, - uint8_t slot, uint8_t rfu) -{ - pirq_info->bus = bus; - pirq_info->devfn = devfn; - pirq_info->irq[0].link = link0; - pirq_info->irq[0].bitmap = bitmap0; - pirq_info->irq[1].link = link1; - pirq_info->irq[1].bitmap = bitmap1; - pirq_info->irq[2].link = link2; - pirq_info->irq[2].bitmap = bitmap2; - pirq_info->irq[3].link = link3; - pirq_info->irq[3].bitmap = bitmap3; - pirq_info->slot = slot; - pirq_info->rfu = rfu; -} - -unsigned long write_pirq_routing_table(unsigned long addr) -{ - - struct irq_routing_table *pirq; - struct irq_info *pirq_info; - unsigned int slot_num; - uint8_t *v; - struct mb_sysconf_t *m; - unsigned int sbdn; - - uint8_t sum = 0; - int i; - - sbdn = sysconf.sbdn; - m = sysconf.mb; - - /* Align the table to be 16 byte aligned. */ - addr += 15; - addr &= ~15; - - /* This table must be between 0xf0000 & 0x100000 */ - printk(BIOS_INFO, "Writing IRQ routing tables to 0x%lx...", addr); - - pirq = (void *)(addr); - v = (uint8_t *) (addr); - - pirq->signature = PIRQ_SIGNATURE; - pirq->version = PIRQ_VERSION; - - pirq->rtr_bus = m->bus_mcp55[0]; - pirq->rtr_devfn = PCI_DEVFN(sbdn + 6, 0); - - pirq->exclusive_irqs = 0; - - pirq->rtr_vendor = 0x10de; - pirq->rtr_device = 0x0370; - - pirq->miniport_data = 0; - - memset(pirq->rfu, 0, sizeof(pirq->rfu)); - - pirq_info = (void *)(&pirq->checksum + 1); - slot_num = 0; -//pci bridge - write_pirq_info(pirq_info, m->bus_mcp55[0], PCI_DEVFN(sbdn + 6, 0), 0x1, - 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, 0); - pirq_info++; - slot_num++; - - for (i = 1; i < sysconf.hc_possible_num; i++) { - if (!(sysconf.pci1234[i] & 0x1)) - continue; - unsigned int busn = (sysconf.pci1234[i] >> 12) & 0xff; - unsigned int devn = sysconf.hcdn[i] & 0xff; - - write_pirq_info(pirq_info, busn, PCI_DEVFN(devn, 0), 0x1, 0xdef8, - 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, 0); - pirq_info++; - slot_num++; - } - -#if CONFIG_CBB - write_pirq_info(pirq_info, CONFIG_CBB, PCI_DEVFN(0, 0), 0x1, 0xdef8, 0x2, - 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, 0); - pirq_info++; - slot_num++; - if (sysconf.nodes > 32) { - write_pirq_info(pirq_info, CONFIG_CBB - 1, PCI_DEVFN(0, 0), 0x1, - 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, - 0, 0); - pirq_info++; - slot_num++; - } -#endif - - pirq->size = 32 + 16 * slot_num; - - for (i = 0; i < pirq->size; i++) - sum += v[i]; - - sum = pirq->checksum - sum; - - if (sum != pirq->checksum) { - pirq->checksum = sum; - } - - printk(BIOS_INFO, "done.\n"); - - return (unsigned long)pirq_info; - -} diff --git a/src/mainboard/msi/ms9652_fam10/mb_sysconf.h b/src/mainboard/msi/ms9652_fam10/mb_sysconf.h deleted file mode 100644 index 1a287c6a8a..0000000000 --- a/src/mainboard/msi/ms9652_fam10/mb_sysconf.h +++ /dev/null @@ -1,26 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007 AMD - * Written by Yinghai Lu for AMD. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef MB_SYSCONF_H -#define MB_SYSCONF_H - -struct mb_sysconf_t { - unsigned char bus_mcp55[8]; //1 - unsigned int apicid_mcp55; -}; - -#endif diff --git a/src/mainboard/msi/ms9652_fam10/mptable.c b/src/mainboard/msi/ms9652_fam10/mptable.c deleted file mode 100644 index 6ae3de18f0..0000000000 --- a/src/mainboard/msi/ms9652_fam10/mptable.c +++ /dev/null @@ -1,113 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007 AMD - * Written by Yinghai Lu for AMD. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include -#include -#include -#include "mb_sysconf.h" - -static void *smp_write_config_table(void *v) -{ - struct mp_config_table *mc; - struct mb_sysconf_t *m; - unsigned int sbdn; - - int i, j, bus_isa; - - mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); - - mptable_init(mc, LOCAL_APIC_ADDR); - - smp_write_processors(mc); - - sbdn = sysconf.sbdn; - m = sysconf.mb; - - mptable_write_buses(mc, NULL, &bus_isa); - -/*I/O APICs: APIC ID Version State Address*/ - { - struct device *dev; - struct resource *res; - uint32_t dword; - - dev = dev_find_slot(m->bus_mcp55[0], PCI_DEVFN(sbdn+ 0x1,0)); - if (dev) { - res = find_resource(dev, PCI_BASE_ADDRESS_1); - if (res) { - smp_write_ioapic(mc, m->apicid_mcp55, 0x11, - res2mmio(res, 0, 0)); - } - - dword = 0x43c6c643; - pci_write_config32(dev, 0x7c, dword); - - dword = 0x81001a00; - pci_write_config32(dev, 0x80, dword); - - dword = 0xd00012d2; - pci_write_config32(dev, 0x84, dword); - - } - - - } - - mptable_add_isa_interrupts(mc, bus_isa, m->apicid_mcp55, 0); - - smp_write_pci_intsrc(mc, mp_INT, m->bus_mcp55[0], sbdn + 1, 1, m->apicid_mcp55, 0xa); - - smp_write_pci_intsrc(mc, mp_INT, m->bus_mcp55[0], sbdn + 2, 0, m->apicid_mcp55, 0x16); // 22) - - smp_write_pci_intsrc(mc, mp_INT, m->bus_mcp55[0], sbdn + 2, 1, m->apicid_mcp55, 0x17); // 23) - - smp_write_pci_intsrc(mc, mp_INT, m->bus_mcp55[0], sbdn + 6, 1, m->apicid_mcp55, 0x17); // 23) - - smp_write_pci_intsrc(mc, mp_INT, m->bus_mcp55[0], sbdn + 5, 0, m->apicid_mcp55, 0x14); // 20) - smp_write_pci_intsrc(mc, mp_INT, m->bus_mcp55[0], sbdn + 5, 1, m->apicid_mcp55, 0x17); // 23) - smp_write_pci_intsrc(mc, mp_INT, m->bus_mcp55[0], sbdn + 5, 2, m->apicid_mcp55, 0x15); // 21) - - smp_write_pci_intsrc(mc, mp_INT, m->bus_mcp55[0], sbdn + 8, 0, m->apicid_mcp55, 0x16); // 22) - smp_write_pci_intsrc(mc, mp_INT, m->bus_mcp55[0], sbdn + 9, 0, m->apicid_mcp55, 0x15); // 21) - - for (j = 7; j >= 2; j--) { - if (!m->bus_mcp55[j]) - continue; - for (i = 0; i < 4; i++) - smp_write_pci_intsrc(mc, mp_INT, m->bus_mcp55[j], 0x00, i, m->apicid_mcp55, 0x10 + (2+j+i+4-sbdn%4)%4); - } - - for (j = 0; j < 1; j++) - for (i = 0; i < 4; i++) - smp_write_pci_intsrc(mc, mp_INT, m->bus_mcp55[1], 0x04+j, i, m->apicid_mcp55, 0x10 + (2+i+j)%4); - -/*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN#*/ - mptable_lintsrc(mc, bus_isa); - /* There is no extension information... */ - - /* Compute the checksums */ - return mptable_finalize(mc); -} - -unsigned long write_smp_table(unsigned long addr) -{ - void *v; - v = smp_write_floating_table(addr, 0); - return (unsigned long)smp_write_config_table(v); -} diff --git a/src/mainboard/msi/ms9652_fam10/resourcemap.c b/src/mainboard/msi/ms9652_fam10/resourcemap.c deleted file mode 100644 index 5d8aca7f8e..0000000000 --- a/src/mainboard/msi/ms9652_fam10/resourcemap.c +++ /dev/null @@ -1,285 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007 AMD - * Written by Yinghai Lu for AMD. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include - -void setup_mb_resource_map(void) -{ - static const unsigned int register_values[] = { - /* Careful set limit registers before base registers which contain the enables */ - /* DRAM Limit i Registers - * F1:0x44 i = 0 - * F1:0x4C i = 1 - * F1:0x54 i = 2 - * F1:0x5C i = 3 - * F1:0x64 i = 4 - * F1:0x6C i = 5 - * F1:0x74 i = 6 - * F1:0x7C i = 7 - * [ 2: 0] Destination Node ID - * 000 = Node 0 - * 001 = Node 1 - * 010 = Node 2 - * 011 = Node 3 - * 100 = Node 4 - * 101 = Node 5 - * 110 = Node 6 - * 111 = Node 7 - * [ 7: 3] Reserved - * [10: 8] Interleave select - * specifies the values of A[14:12] to use with interleave enable. - * [15:11] Reserved - * [31:16] DRAM Limit Address i Bits 39-24 - * This field defines the upper address bits of a 40 bit address - * that define the end of the DRAM region. - */ - // ADDRMAP_REG(0x44), 0x0000f8f8, 0x00000000, // Don't touch it, we need it for CAR with FAM10 - ADDRMAP_REG(0x4C), 0x0000f8f8, 0x00000001, - ADDRMAP_REG(0x54), 0x0000f8f8, 0x00000002, - ADDRMAP_REG(0x5C), 0x0000f8f8, 0x00000003, - ADDRMAP_REG(0x64), 0x0000f8f8, 0x00000004, - ADDRMAP_REG(0x6C), 0x0000f8f8, 0x00000005, - ADDRMAP_REG(0x74), 0x0000f8f8, 0x00000006, - ADDRMAP_REG(0x7C), 0x0000f8f8, 0x00000007, - - /* DRAM Base i Registers - * F1:0x40 i = 0 - * F1:0x48 i = 1 - * F1:0x50 i = 2 - * F1:0x58 i = 3 - * F1:0x60 i = 4 - * F1:0x68 i = 5 - * F1:0x70 i = 6 - * F1:0x78 i = 7 - * [ 0: 0] Read Enable - * 0 = Reads Disabled - * 1 = Reads Enabled - * [ 1: 1] Write Enable - * 0 = Writes Disabled - * 1 = Writes Enabled - * [ 7: 2] Reserved - * [10: 8] Interleave Enable - * 000 = No interleave - * 001 = Interleave on A[12] (2 nodes) - * 010 = reserved - * 011 = Interleave on A[12] and A[14] (4 nodes) - * 100 = reserved - * 101 = reserved - * 110 = reserved - * 111 = Interleve on A[12] and A[13] and A[14] (8 nodes) - * [15:11] Reserved - * [13:16] DRAM Base Address i Bits 39-24 - * This field defines the upper address bits of a 40-bit address - * that define the start of the DRAM region. - */ - // ADDRMAP_REG(0x40), 0x0000f8fc, 0x00000000, // don't touch it, we need it for CAR with FAM10 - ADDRMAP_REG(0x48), 0x0000f8fc, 0x00000000, - ADDRMAP_REG(0x50), 0x0000f8fc, 0x00000000, - ADDRMAP_REG(0x58), 0x0000f8fc, 0x00000000, - ADDRMAP_REG(0x60), 0x0000f8fc, 0x00000000, - ADDRMAP_REG(0x68), 0x0000f8fc, 0x00000000, - ADDRMAP_REG(0x70), 0x0000f8fc, 0x00000000, - ADDRMAP_REG(0x78), 0x0000f8fc, 0x00000000, - - /* Memory-Mapped I/O Limit i Registers - * F1:0x84 i = 0 - * F1:0x8C i = 1 - * F1:0x94 i = 2 - * F1:0x9C i = 3 - * F1:0xA4 i = 4 - * F1:0xAC i = 5 - * F1:0xB4 i = 6 - * F1:0xBC i = 7 - * [ 2: 0] Destination Node ID - * 000 = Node 0 - * 001 = Node 1 - * 010 = Node 2 - * 011 = Node 3 - * 100 = Node 4 - * 101 = Node 5 - * 110 = Node 6 - * 111 = Node 7 - * [ 3: 3] Reserved - * [ 5: 4] Destination Link ID - * 00 = Link 0 - * 01 = Link 1 - * 10 = Link 2 - * 11 = Reserved - * [ 6: 6] Reserved - * [ 7: 7] Non-Posted - * 0 = CPU writes may be posted - * 1 = CPU writes must be non-posted - * [31: 8] Memory-Mapped I/O Limit Address i (39-16) - * This field defines the upp address bits of a 40-bit address that - * defines the end of a memory-mapped I/O region n - */ - ADDRMAP_REG(0x84), 0x00000048, 0x00000000, - ADDRMAP_REG(0x8C), 0x00000048, 0x00000000, - ADDRMAP_REG(0x94), 0x00000048, 0x00000000, - ADDRMAP_REG(0x9C), 0x00000048, 0x00000000, - ADDRMAP_REG(0xA4), 0x00000048, 0x00000000, - ADDRMAP_REG(0xAC), 0x00000048, 0x00000000, - ADDRMAP_REG(0xB4), 0x00000048, 0x00000000, -// ADDRMAP_REG(0xBC), 0x00000048, 0x00ffff00, - - /* Memory-Mapped I/O Base i Registers - * F1:0x80 i = 0 - * F1:0x88 i = 1 - * F1:0x90 i = 2 - * F1:0x98 i = 3 - * F1:0xA0 i = 4 - * F1:0xA8 i = 5 - * F1:0xB0 i = 6 - * F1:0xB8 i = 7 - * [ 0: 0] Read Enable - * 0 = Reads disabled - * 1 = Reads Enabled - * [ 1: 1] Write Enable - * 0 = Writes disabled - * 1 = Writes Enabled - * [ 2: 2] Cpu Disable - * 0 = Cpu can use this I/O range - * 1 = Cpu requests do not use this I/O range - * [ 3: 3] Lock - * 0 = base/limit registers i are read/write - * 1 = base/limit registers i are read-only - * [ 7: 4] Reserved - * [31: 8] Memory-Mapped I/O Base Address i (39-16) - * This field defines the upper address bits of a 40bit address - * that defines the start of memory-mapped I/O region i - */ - ADDRMAP_REG(0x80), 0x000000f0, 0x00000000, - ADDRMAP_REG(0x88), 0x000000f0, 0x00000000, - ADDRMAP_REG(0x90), 0x000000f0, 0x00000000, - ADDRMAP_REG(0x98), 0x000000f0, 0x00000000, - ADDRMAP_REG(0xA0), 0x000000f0, 0x00000000, - ADDRMAP_REG(0xA8), 0x000000f0, 0x00000000, - ADDRMAP_REG(0xB0), 0x000000f0, 0x00000000, -// ADDRMAP_REG(0xB8), 0x000000f0, 0x00fc0003, - - /* PCI I/O Limit i Registers - * F1:0xC4 i = 0 - * F1:0xCC i = 1 - * F1:0xD4 i = 2 - * F1:0xDC i = 3 - * [ 2: 0] Destination Node ID - * 000 = Node 0 - * 001 = Node 1 - * 010 = Node 2 - * 011 = Node 3 - * 100 = Node 4 - * 101 = Node 5 - * 110 = Node 6 - * 111 = Node 7 - * [ 3: 3] Reserved - * [ 5: 4] Destination Link ID - * 00 = Link 0 - * 01 = Link 1 - * 10 = Link 2 - * 11 = reserved - * [11: 6] Reserved - * [24:12] PCI I/O Limit Address i - * This field defines the end of PCI I/O region n - * [31:25] Reserved - */ -// ADDRMAP_REG(0xC4), 0xFE000FC8, 0x00004000, - ADDRMAP_REG(0xC4), 0xFE000FC8, 0x01fff000, - ADDRMAP_REG(0xCC), 0xFE000FC8, 0x00000000, - ADDRMAP_REG(0xD4), 0xFE000FC8, 0x00000000, - ADDRMAP_REG(0xDC), 0xFE000FC8, 0x00000000, - - /* PCI I/O Base i Registers - * F1:0xC0 i = 0 - * F1:0xC8 i = 1 - * F1:0xD0 i = 2 - * F1:0xD8 i = 3 - * [ 0: 0] Read Enable - * 0 = Reads Disabled - * 1 = Reads Enabled - * [ 1: 1] Write Enable - * 0 = Writes Disabled - * 1 = Writes Enabled - * [ 3: 2] Reserved - * [ 4: 4] VGA Enable - * 0 = VGA matches Disabled - * 1 = matches all address < 64K and where A[9:0] is in the - * range 3B0-3BB or 3C0-3DF independen of the base & limit registers - * [ 5: 5] ISA Enable - * 0 = ISA matches Disabled - * 1 = Blocks address < 64K and in the last 768 bytes of eack 1K block - * from matching agains this base/limit pair - * [11: 6] Reserved - * [24:12] PCI I/O Base i - * This field defines the start of PCI I/O region n - * [31:25] Reserved - */ - /* Verified against board configuration registers after normal proprietary BIOS boot */ - //ADDRMAP_REG(0xC0), 0xFE000FCC, 0x00001033, - ADDRMAP_REG(0xC0), 0xFE000FCC, 0x00000033, - ADDRMAP_REG(0xC8), 0xFE000FCC, 0x00000000, - ADDRMAP_REG(0xD0), 0xFE000FCC, 0x00000000, - ADDRMAP_REG(0xD8), 0xFE000FCC, 0x00000000, - - /* Config Base and Limit i Registers - * F1:0xE0 i = 0 - * F1:0xE4 i = 1 - * F1:0xE8 i = 2 - * F1:0xEC i = 3 - * [ 0: 0] Read Enable - * 0 = Reads Disabled - * 1 = Reads Enabled - * [ 1: 1] Write Enable - * 0 = Writes Disabled - * 1 = Writes Enabled - * [ 2: 2] Device Number Compare Enable - * 0 = The ranges are based on bus number - * 1 = The ranges are ranges of devices on bus 0 - * [ 3: 3] Reserved - * [ 6: 4] Destination Node - * 000 = Node 0 - * 001 = Node 1 - * 010 = Node 2 - * 011 = Node 3 - * 100 = Node 4 - * 101 = Node 5 - * 110 = Node 6 - * 111 = Node 7 - * [ 7: 7] Reserved - * [ 9: 8] Destination Link - * 00 = Link 0 - * 01 = Link 1 - * 10 = Link 2 - * 11 - Reserved - * [15:10] Reserved - * [23:16] Bus Number Base i - * This field defines the lowest bus number in configuration region i - * [31:24] Bus Number Limit i - * This field defines the highest bus number in configuration region i - */ - /* Verified against board configuration registers after normal proprietary BIOS boot */ - ADDRMAP_REG(0xE0), 0x0000FC88, 0xff000003, /* link 0 of CPU 0 --> Nvidia MCP55 Pro */ - ADDRMAP_REG(0xE4), 0x0000FC88, 0x00000000, - ADDRMAP_REG(0xE8), 0x0000FC88, 0x00000000, - ADDRMAP_REG(0xEC), 0x0000FC88, 0x00000000, - - }; - - int max; - max = ARRAY_SIZE(register_values); - setup_resource_map(register_values, max); -} diff --git a/src/mainboard/msi/ms9652_fam10/romstage.c b/src/mainboard/msi/ms9652_fam10/romstage.c deleted file mode 100644 index 4658d75427..0000000000 --- a/src/mainboard/msi/ms9652_fam10/romstage.c +++ /dev/null @@ -1,271 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007 AMD - * Written by Yinghai Lu for AMD. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include "cpu/amd/quadcore/quadcore.c" - -#define SERIAL_DEV PNP_DEV(0x2e, W83627EHG_SP1) - -int spd_read_byte(unsigned int device, unsigned int address); - - -inline int spd_read_byte(unsigned int device, unsigned int address) -{ - return smbus_read_byte(device, address); -} - -unsigned int get_sbdn(unsigned int bus) -{ - pci_devfn_t dev; - - /* Find the device. */ - dev = pci_locate_device_on_bus(PCI_ID(PCI_VENDOR_ID_NVIDIA, - PCI_DEVICE_ID_NVIDIA_MCP55_HT), bus); - - return (dev >> 15) & 0x1f; -} - -#define MCP55_MB_SETUP \ - RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+37, 0x00, 0x44,/* GPIO38 PCI_REQ3 */ \ - RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+38, 0x00, 0x44,/* GPIO39 PCI_GNT3 */ \ - RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+39, 0x00, 0x44,/* GPIO40 PCI_GNT2 */ \ - RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+40, 0x00, 0x44,/* GPIO41 PCI_REQ2 */ \ - RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+59, 0x00, 0x60,/* GPIP60 FANCTL0 */ \ - RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+60, 0x00, 0x60,/* GPIO61 FANCTL1 */ - -#include -#include "southbridge/nvidia/mcp55/early_setup_car.c" - -static void sio_setup(void) -{ - u32 dword; - u8 byte; - - byte = pci_read_config32(PCI_DEV(0, MCP55_DEVN_BASE+1, 0), 0x7b); - byte |= 0x20; - pci_write_config8(PCI_DEV(0, MCP55_DEVN_BASE+1, 0), 0x7b, byte); - - dword = pci_read_config32(PCI_DEV(0, MCP55_DEVN_BASE+1, 0), 0xa0); - dword |= (1 << 0); - pci_write_config32(PCI_DEV(0, MCP55_DEVN_BASE+1, 0), 0xa0, dword); -} - -static const u8 spd_addr[] = { - //first node - RC00, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, -#if CONFIG_MAX_PHYSICAL_CPUS > 1 - //second node - RC00, DIMM4, DIMM6, 0, 0, DIMM5, DIMM7, 0, 0, -#endif -}; - -void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) -{ - struct sys_info *sysinfo = get_sysinfo(); - u32 bsp_apicid = 0, val, wants_reset; - u8 reg; - msr_t msr; - - timestamp_init(timestamp_get()); - timestamp_add_now(TS_START_ROMSTAGE); - - if (!cpu_init_detectedx && boot_cpu()) { - /* Nothing special needs to be done to find bus 0 */ - /* Allow the HT devices to be found */ - set_bsp_node_CHtExtNodeCfgEn(); - enumerate_ht_chain(); - sio_setup(); - } - - post_code(0x30); - - if (bist == 0) - bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo); - - post_code(0x32); - - pnp_enter_conf_state(SERIAL_DEV); - /* We have 24MHz input. */ - reg = pnp_read_config(SERIAL_DEV, 0x24); - pnp_write_config(SERIAL_DEV, 0x24, (reg & 0xbf)); - pnp_exit_conf_state(SERIAL_DEV); - - winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); - console_init(); - - /* Halt if there was a built in self test failure */ - report_bist_failure(bist); - - val = cpuid_eax(1); - printk(BIOS_DEBUG, "BSP Family_Model: %08x\n", val); - printk(BIOS_DEBUG, "*sysinfo range: [%p,%p]\n",sysinfo,sysinfo+1); - printk(BIOS_DEBUG, "bsp_apicid = %02x\n", bsp_apicid); - printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx); - - /* Setup sysinfo defaults */ - set_sysinfo_in_ram(0); - - update_microcode(val); - - post_code(0x33); - - cpuSetAMDMSR(0); - post_code(0x34); - - amd_ht_init(sysinfo); - post_code(0x35); - - /* Setup nodes PCI space and start core 0 AP init. */ - finalize_node_setup(sysinfo); - printk(BIOS_DEBUG, "finalize_node_setup done\n"); - - /* Setup any mainboard PCI settings etc. */ - printk(BIOS_DEBUG, "setup_mb_resource_map begin\n"); - setup_mb_resource_map(); - printk(BIOS_DEBUG, "setup_mb_resource_map end\n"); - post_code(0x36); - - /* wait for all the APs core0 started by finalize_node_setup. */ - /* FIXME: A bunch of cores are going to start output to serial at once. - * It would be nice to fixup prink spinlocks for ROM XIP mode. - * I think it could be done by putting the spinlock flag in the cache - * of the BSP located right after sysinfo. - */ - wait_all_core0_started(); - -#if CONFIG(LOGICAL_CPUS) - /* Core0 on each node is configured. Now setup any additional cores. */ - printk(BIOS_DEBUG, "start_other_cores()\n"); - start_other_cores(bsp_apicid); - post_code(0x37); - printk(BIOS_DEBUG, "wait_all_other_cores_started()\n"); - wait_all_other_cores_started(bsp_apicid); -#endif - - post_code(0x38); - -#if CONFIG(SET_FIDVID) - msr = rdmsr(MSR_COFVID_STS); - printk(BIOS_DEBUG, "\nBegin FIDVID MSR 0xc0010071 0x%08x 0x%08x\n", msr.hi, msr.lo); - - /* FIXME: The sb fid change may survive the warm reset and only - * need to be done once.*/ - enable_fid_change_on_sb(sysinfo->sbbusn, sysinfo->sbdn); - - post_code(0x39); - - if (!warm_reset_detect(0)) { // BSP is node 0 - init_fidvid_bsp(bsp_apicid, sysinfo->nodes); - } else { - init_fidvid_stage2(bsp_apicid, 0); // BSP is node 0 - } - - post_code(0x3A); - - /* show final fid and vid */ - msr = rdmsr(MSR_COFVID_STS); - printk(BIOS_DEBUG, "End FIDVIDMSR 0xc0010071 0x%08x 0x%08x\n", msr.hi, msr.lo); -#endif - init_timer(); /* Need to use TMICT to synchronize FID/VID. */ - - wants_reset = mcp55_early_setup_x(); - - /* Reset for HT, FIDVID, PLL and errata changes to take affect. */ - if (!warm_reset_detect(0)) { - printk(BIOS_INFO, "...WARM RESET...\n\n\n"); - soft_reset(); - die("After soft_reset - shouldn't see this message!!!\n"); - } - - if (wants_reset) - printk(BIOS_DEBUG, "mcp55_early_setup_x wanted additional reset!\n"); - - post_code(0x3B); - - /* It's the time to set ctrl in sysinfo now; */ - printk(BIOS_DEBUG, "fill_mem_ctrl()\n"); - fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr); - post_code(0x3D); - - printk(BIOS_DEBUG, "enable_smbus()\n"); - enable_smbus(); - - post_code(0x40); - - raminit_amdmct(sysinfo); - - cbmem_initialize_empty(); - post_code(0x41); - - amdmct_cbmem_store_info(sysinfo); -} - -/** - * BOOL AMD_CB_ManualBUIDSwapList(u8 Node, u8 Link, u8 **List) - * Description: - * This routine is called every time a non-coherent chain is processed. - * BUID assignment may be controlled explicitly on a non-coherent chain. Provide a - * swap list. The first part of the list controls the BUID assignment and the - * second part of the list provides the device to device linking. Device orientation - * can be detected automatically, or explicitly. See documentation for more details. - * - * Automatic non-coherent init assigns BUIDs starting at 1 and incrementing sequentially - * based on each device's unit count. - * - * Parameters: - * @param[in] node = The node on which this chain is located - * @param[in] link = The link on the host for this chain - * @param[out] List = supply a pointer to a list - */ -BOOL AMD_CB_ManualBUIDSwapList (u8 node, u8 link, const u8 **List) -{ - static const u8 swaplist[] = { 0xFF, CONFIG_HT_CHAIN_UNITID_BASE, CONFIG_HT_CHAIN_END_UNITID_BASE, 0xFF }; - /* If the BUID was adjusted in early_ht we need to do the manual override */ - if ((CONFIG_HT_CHAIN_UNITID_BASE != 0) && (CONFIG_HT_CHAIN_END_UNITID_BASE != 0)) { - printk(BIOS_DEBUG, "AMD_CB_ManualBUIDSwapList()\n"); - if ((node == 0) && (link == 0)) { /* BSP SB link */ - *List = swaplist; - return 1; - } - } - - return 0; -} diff --git a/src/mainboard/supermicro/h8dmr_fam10/Kconfig b/src/mainboard/supermicro/h8dmr_fam10/Kconfig deleted file mode 100644 index 928a84fc96..0000000000 --- a/src/mainboard/supermicro/h8dmr_fam10/Kconfig +++ /dev/null @@ -1,62 +0,0 @@ -if BOARD_SUPERMICRO_H8DMR_FAM10 - -config BOARD_SPECIFIC_OPTIONS - def_bool y - select CPU_AMD_SOCKET_F_1207 - select DIMM_DDR2 - select DIMM_REGISTERED - select NORTHBRIDGE_AMD_AMDFAM10 - select SOUTHBRIDGE_NVIDIA_MCP55 - select HT_CHAIN_DISTRIBUTE - select MCP55_USE_NIC - select MCP55_USE_AZA - select SUPERIO_WINBOND_W83627HF - select PARALLEL_CPU_INIT - select HAVE_OPTION_TABLE - select HAVE_PIRQ_TABLE - select HAVE_MP_TABLE - select LIFT_BSP_APIC_ID - select BOARD_ROMSIZE_KB_1024 - select ENABLE_APIC_EXT_ID - -config MAINBOARD_DIR - string - default supermicro/h8dmr_fam10 - -config DCACHE_RAM_BASE - hex - default 0xc4000 - -config DCACHE_RAM_SIZE - hex - default 0x0c000 - -config APIC_ID_OFFSET - hex - default 0x0 - -config MAINBOARD_PART_NUMBER - string - default "H8DMR-i2 (Fam10)" - -config MAX_CPUS - int - default 8 - -config MAX_PHYSICAL_CPUS - int - default 2 - -config HT_CHAIN_END_UNITID_BASE - hex - default 0x20 - -config HT_CHAIN_UNITID_BASE - hex - default 0x1 - -config IRQ_SLOT_COUNT - int - default 11 - -endif # BOARD_SUPERMICRO_H8DMR_FAM10 diff --git a/src/mainboard/supermicro/h8dmr_fam10/Kconfig.name b/src/mainboard/supermicro/h8dmr_fam10/Kconfig.name deleted file mode 100644 index 379d9bb026..0000000000 --- a/src/mainboard/supermicro/h8dmr_fam10/Kconfig.name +++ /dev/null @@ -1,2 +0,0 @@ -config BOARD_SUPERMICRO_H8DMR_FAM10 - bool "H8DMR-i2 (Fam10)" diff --git a/src/mainboard/supermicro/h8dmr_fam10/Makefile.inc b/src/mainboard/supermicro/h8dmr_fam10/Makefile.inc deleted file mode 100644 index 91d4b39c32..0000000000 --- a/src/mainboard/supermicro/h8dmr_fam10/Makefile.inc +++ /dev/null @@ -1,16 +0,0 @@ -# -# This file is part of the coreboot project. -# -# This program is free software; you can redistribute it and/or modify -# it under the terms of the GNU General Public License as published by -# the Free Software Foundation; version 2 of the License. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# - -romstage-y += resourcemap.c - -ramstage-y += get_bus_conf.c diff --git a/src/mainboard/supermicro/h8dmr_fam10/README b/src/mainboard/supermicro/h8dmr_fam10/README deleted file mode 100644 index ffcbcc021f..0000000000 --- a/src/mainboard/supermicro/h8dmr_fam10/README +++ /dev/null @@ -1,22 +0,0 @@ - - -There are a number of outstanding issues: - -* I'm seeing toolchain issues. I can't get this tree to compile correctly with -gcc 4.3 (32 bit) - there is an optimization issue where certain parts of the -CBFS code execute very slowly. With gcc 3.4 (32 bit) that slowness -disappears. This is probably not a problem related to this port specifically. - -* setting CONFIG_DEFAULT_CONSOLE_LOGLEVEL lower than 8 simply hangs the boot -shortly after the warm reset triggered by the MCP55 code. I think this too -might be a toolchain problem (but I see it on gcc 3.4 as well as 4.3). - -* during startup, the CPU cores talk through each other on serial for a -while. Again, not an issue specific to this port. - -* to avoid very slow LZMA decompression I use this port with LZMA compression -disabled in CBFS. I'm not sure what's causing this particular slowness. - -See also this thread: https://www.coreboot.org/pipermail/coreboot/2009-September/052107.html - -Ward, 2009-09-22 diff --git a/src/mainboard/supermicro/h8dmr_fam10/board_info.txt b/src/mainboard/supermicro/h8dmr_fam10/board_info.txt deleted file mode 100644 index 3d902b640a..0000000000 --- a/src/mainboard/supermicro/h8dmr_fam10/board_info.txt +++ /dev/null @@ -1 +0,0 @@ -Category: server diff --git a/src/mainboard/supermicro/h8dmr_fam10/cmos.layout b/src/mainboard/supermicro/h8dmr_fam10/cmos.layout deleted file mode 100644 index 331e0162bb..0000000000 --- a/src/mainboard/supermicro/h8dmr_fam10/cmos.layout +++ /dev/null @@ -1,102 +0,0 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2015 Timothy Pearson , Raptor Engineering -## Copyright (C) 2007 AMD -## Written by Yinghai Lu for AMD. -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; either version 2 of the License, or -## (at your option) any later version. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## - -entries - -0 384 r 0 reserved_memory -384 1 e 4 boot_option -388 4 h 0 reboot_counter -393 3 r 0 unused -#394 7 unused -401 1 e 1 interleave_chip_selects -402 1 e 1 interleave_nodes -403 1 e 1 interleave_memory_channels -404 2 e 8 max_mem_clock -406 1 e 2 multi_core -412 4 e 6 debug_level -416 5 e 10 ecc_scrub_rate -440 4 e 9 slow_cpu -444 1 e 1 nmi -445 1 e 1 gart -446 1 e 1 power_on_after_fail -456 1 e 1 ECC_memory -457 1 e 1 ECC_redirection -728 256 h 0 user_data -984 16 h 0 check_sum -# Reserve the extended AMD configuration registers -1000 24 r 0 amd_reserved - - - -enumerations - -#ID value text -1 0 Disable -1 1 Enable -2 0 Enable -2 1 Disable -4 0 Fallback -4 1 Normal -6 0 Emergency -6 1 Alert -6 2 Critical -6 3 Error -6 4 Warning -6 5 Notice -6 6 Information -6 7 Debug -6 8 Spew -8 0 DDR2-800 -8 1 DDR2-667 -8 2 DDR2-533 -8 3 DDR2-400 -9 0 off -9 1 87.5% -9 2 75.0% -9 3 62.5% -9 4 50.0% -9 5 37.5% -9 6 25.0% -9 7 12.5% -10 0 Disabled -10 1 40ns -10 2 80ns -10 3 160ns -10 4 320ns -10 5 640ns -10 6 1.28us -10 7 2.56us -10 8 5.12us -10 9 10.2us -10 10 20.5us -10 11 41us -10 12 81.9us -10 13 163.8us -10 14 327.7us -10 15 655.4us -10 16 1.31ms -10 17 2.62ms -10 18 5.24ms -10 19 10.49ms -10 20 20.97sms -10 21 42ms -10 22 84ms - -checksums - -checksum 392 983 984 diff --git a/src/mainboard/supermicro/h8dmr_fam10/devicetree.cb b/src/mainboard/supermicro/h8dmr_fam10/devicetree.cb deleted file mode 100644 index ee88c31a97..0000000000 --- a/src/mainboard/supermicro/h8dmr_fam10/devicetree.cb +++ /dev/null @@ -1,152 +0,0 @@ -chip northbridge/amd/amdfam10/root_complex # Root complex - device cpu_cluster 0 on # (L)APIC cluster - chip cpu/amd/socket_F_1207 # CPU socket - device lapic 0 on end # Local APIC of the CPU - end - end - device domain 0 on # PCI domain - subsystemid 0x15d9 0x1511 inherit - chip northbridge/amd/amdfam10 # Northbridge / RAM controller - device pci 18.0 on end - device pci 18.0 on end - device pci 18.0 on # SB on link 2.0 - chip southbridge/nvidia/mcp55 # Southbridge - device pci 0.0 on end # HT - device pci 1.0 on # LPC - chip superio/winbond/w83627hf # Super I/O - device pnp 2e.0 off # Floppy - io 0x60 = 0x3f0 - irq 0x70 = 6 - drq 0x74 = 2 - end - device pnp 2e.1 off # Parallel port - io 0x60 = 0x378 - irq 0x70 = 7 - end - device pnp 2e.2 on # Com1 - io 0x60 = 0x3f8 - irq 0x70 = 4 - end - device pnp 2e.3 on # Com2 - io 0x60 = 0x2f8 - irq 0x70 = 3 - end - device pnp 2e.5 on # PS/2 keyboard - io 0x60 = 0x60 - io 0x62 = 0x64 - irq 0x70 = 1 - irq 0x72 = 12 - end - device pnp 2e.6 off # SFI - io 0x62 = 0x100 - end - device pnp 2e.7 off # GPIO, game port, MIDI - io 0x60 = 0x220 - io 0x62 = 0x300 - irq 0x70 = 9 - end - device pnp 2e.8 off end # WDTO PLED - device pnp 2e.9 off end # GPIO SUSLED - device pnp 2e.a off end # ACPI - device pnp 2e.b on # Hardware monitor - io 0x60 = 0x290 - irq 0x70 = 5 - end - end - end - device pci 1.1 on # SM 0 - chip drivers/generic/generic # DIMM 0-0-0 - device i2c 50 on end - end - chip drivers/generic/generic # DIMM 0-0-1 - device i2c 51 on end - end - chip drivers/generic/generic # DIMM 0-1-0 - device i2c 52 on end - end - chip drivers/generic/generic # DIMM 0-1-1 - device i2c 53 on end - end - chip drivers/generic/generic # DIMM 1-0-0 - device i2c 54 on end - end - chip drivers/generic/generic # DIMM 1-0-1 - device i2c 55 on end - end - chip drivers/generic/generic # DIMM 1-1-0 - device i2c 56 on end - end - chip drivers/generic/generic # DIMM 1-1-1 - device i2c 57 on end - end - end - device pci 1.1 on # SM 1 - # PCI device SMBus address will - # depend on addon PCI device, do - # we need to scan_smbus_bus? - # chip drivers/generic/generic # PCIXA slot 1 - # device i2c 50 on end - # end - # chip drivers/generic/generic # PCIXB slot 1 - # device i2c 51 on end - # end - # chip drivers/generic/generic # PCIXB slot 2 - # device i2c 52 on end - # end - # chip drivers/generic/generic # PCI slot 1 - # device i2c 53 on end - # end - # chip drivers/generic/generic # Master MCP55 PCI-E - # device i2c 54 on end - # end - # chip drivers/generic/generic # Slave MCP55 PCI-E - # device i2c 55 on end - # end - chip drivers/generic/generic # MAC EEPROM - device i2c 51 on end - end - end - device pci 2.0 on end # USB 1.1 - device pci 2.1 on end # USB 2 - device pci 4.0 on end # IDE - device pci 5.0 on end # SATA 0 - device pci 5.1 on end # SATA 1 - device pci 5.2 on end # SATA 2 - device pci 6.0 on # PCI - device pci 6.0 on end - end - device pci 6.1 on end # AZA - device pci 8.0 on end # NIC - device pci 9.0 on end # NIC - device pci a.0 on # PCI E 5 - device pci 0.0 on end # NEC PCI-X - device pci 0.1 on # NEC PCI-X - device pci 4.0 on end # SCSI - device pci 4.1 on end # SCSI - end - end - device pci b.0 on end # PCI E 4 - device pci c.0 on end # PCI E 3 - device pci d.0 on end # PCI E 2 - device pci e.0 on end # PCI E 1 - device pci f.0 on end # PCI E 0 - register "ide0_enable" = "1" - register "sata0_enable" = "1" - register "sata1_enable" = "1" - # 1: SMBus under 2e.8, 2: SM0 3: SM1 - register "mac_eeprom_smbus" = "3" - register "mac_eeprom_addr" = "0x51" - end - end - device pci 18.1 on end - device pci 18.2 on end - device pci 18.3 on end - device pci 18.4 on end - device pci 19.0 on end - device pci 19.1 on end - device pci 19.2 on end - device pci 19.3 on end - device pci 19.4 on end - end - end -end diff --git a/src/mainboard/supermicro/h8dmr_fam10/get_bus_conf.c b/src/mainboard/supermicro/h8dmr_fam10/get_bus_conf.c deleted file mode 100644 index 0bb16d36b2..0000000000 --- a/src/mainboard/supermicro/h8dmr_fam10/get_bus_conf.c +++ /dev/null @@ -1,78 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007 AMD - * Written by Yinghai Lu for AMD. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include -#include -#include -#include - -#include - -#include -#include "mb_sysconf.h" - -// Global variables for MB layouts and these will be shared by irqtable mptable and acpi_tables -struct mb_sysconf_t mb_sysconf; - -void get_bus_conf(void) -{ - - unsigned int apicid_base; - struct mb_sysconf_t *m; - - struct device *dev; - int i; - - sysconf.mb = &mb_sysconf; - - m = sysconf.mb; - memset(m, 0, sizeof(struct mb_sysconf_t)); - - get_default_pci1234(32); - - sysconf.sbdn = (sysconf.hcdn[0] & 0xff); // first byte of first chain - m->bus_mcp55[0] = (sysconf.pci1234[0] >> 12) & 0xff; - - /* MCP55 */ - dev = dev_find_slot(m->bus_mcp55[0], PCI_DEVFN(sysconf.sbdn + 0x06,0)); - if (dev) { - m->bus_mcp55[1] = pci_read_config8(dev, PCI_SECONDARY_BUS); - } - else { - printk(BIOS_DEBUG, "ERROR - could not find PCI 1:%02x.0, using defaults\n", sysconf.sbdn + 0x06); - } - - for(i = 2; i < 8; i++) { - dev = dev_find_slot(m->bus_mcp55[0], PCI_DEVFN(sysconf.sbdn + 0x0a + i - 2, 0)); - if (dev) { - m->bus_mcp55[i] = pci_read_config8(dev, PCI_SECONDARY_BUS); - } - else { - printk(BIOS_DEBUG, "ERROR - could not find PCI %02x:%02x.0, using defaults\n", m->bus_mcp55[0], sysconf.sbdn + 0x0a + i - 2); - } - } - -/*I/O APICs: APIC ID Version State Address*/ - if (CONFIG(LOGICAL_CPUS)) - apicid_base = get_apicid_base(1); - else - apicid_base = CONFIG_MAX_PHYSICAL_CPUS; - m->apicid_mcp55 = apicid_base+0; - -} diff --git a/src/mainboard/supermicro/h8dmr_fam10/hda_verb.c b/src/mainboard/supermicro/h8dmr_fam10/hda_verb.c deleted file mode 100644 index 5d088790a5..0000000000 --- a/src/mainboard/supermicro/h8dmr_fam10/hda_verb.c +++ /dev/null @@ -1,20 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include - -const u32 cim_verb_data[0] = {}; - -const u32 pc_beep_verbs[0] = {}; - -AZALIA_ARRAY_SIZES; diff --git a/src/mainboard/supermicro/h8dmr_fam10/irq_tables.c b/src/mainboard/supermicro/h8dmr_fam10/irq_tables.c deleted file mode 100644 index 69327dcafa..0000000000 --- a/src/mainboard/supermicro/h8dmr_fam10/irq_tables.c +++ /dev/null @@ -1,137 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007 AMD - * Written by Yinghai Lu for AMD. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include -#include -#include - -#include -#include "mb_sysconf.h" - -static void write_pirq_info(struct irq_info *pirq_info, uint8_t bus, - uint8_t devfn, uint8_t link0, uint16_t bitmap0, - uint8_t link1, uint16_t bitmap1, uint8_t link2, - uint16_t bitmap2, uint8_t link3, uint16_t bitmap3, - uint8_t slot, uint8_t rfu) -{ - pirq_info->bus = bus; - pirq_info->devfn = devfn; - pirq_info->irq[0].link = link0; - pirq_info->irq[0].bitmap = bitmap0; - pirq_info->irq[1].link = link1; - pirq_info->irq[1].bitmap = bitmap1; - pirq_info->irq[2].link = link2; - pirq_info->irq[2].bitmap = bitmap2; - pirq_info->irq[3].link = link3; - pirq_info->irq[3].bitmap = bitmap3; - pirq_info->slot = slot; - pirq_info->rfu = rfu; -} - -unsigned long write_pirq_routing_table(unsigned long addr) -{ - - struct irq_routing_table *pirq; - struct irq_info *pirq_info; - unsigned int slot_num; - uint8_t *v; - struct mb_sysconf_t *m; - unsigned int sbdn; - - uint8_t sum = 0; - int i; - - sbdn = sysconf.sbdn; - m = sysconf.mb; - - /* Align the table to be 16 byte aligned. */ - addr += 15; - addr &= ~15; - - /* This table must be between 0xf0000 & 0x100000 */ - printk(BIOS_INFO, "Writing IRQ routing tables to 0x%lx...", addr); - - pirq = (void *)(addr); - v = (uint8_t *) (addr); - - pirq->signature = PIRQ_SIGNATURE; - pirq->version = PIRQ_VERSION; - - pirq->rtr_bus = m->bus_mcp55[0]; - pirq->rtr_devfn = PCI_DEVFN(sbdn + 6, 0); - - pirq->exclusive_irqs = 0; - - pirq->rtr_vendor = 0x10de; - pirq->rtr_device = 0x0370; - - pirq->miniport_data = 0; - - memset(pirq->rfu, 0, sizeof(pirq->rfu)); - - pirq_info = (void *)(&pirq->checksum + 1); - slot_num = 0; -//pci bridge - write_pirq_info(pirq_info, m->bus_mcp55[0], PCI_DEVFN(sbdn + 6, 0), 0x1, - 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, 0); - pirq_info++; - slot_num++; - - for (i = 1; i < sysconf.hc_possible_num; i++) { - if (!(sysconf.pci1234[i] & 0x1)) - continue; - unsigned int busn = (sysconf.pci1234[i] >> 12) & 0xff; - unsigned int devn = sysconf.hcdn[i] & 0xff; - - write_pirq_info(pirq_info, busn, PCI_DEVFN(devn, 0), 0x1, 0xdef8, - 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, 0); - pirq_info++; - slot_num++; - } - -#if CONFIG_CBB - write_pirq_info(pirq_info, CONFIG_CBB, PCI_DEVFN(0, 0), 0x1, 0xdef8, 0x2, - 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, 0); - pirq_info++; - slot_num++; - if (sysconf.nodes > 32) { - write_pirq_info(pirq_info, CONFIG_CBB - 1, PCI_DEVFN(0, 0), 0x1, - 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, - 0, 0); - pirq_info++; - slot_num++; - } -#endif - - pirq->size = 32 + 16 * slot_num; - - for (i = 0; i < pirq->size; i++) - sum += v[i]; - - sum = pirq->checksum - sum; - - if (sum != pirq->checksum) { - pirq->checksum = sum; - } - - printk(BIOS_INFO, "done.\n"); - - return (unsigned long)pirq_info; - -} diff --git a/src/mainboard/supermicro/h8dmr_fam10/mb_sysconf.h b/src/mainboard/supermicro/h8dmr_fam10/mb_sysconf.h deleted file mode 100644 index 1a287c6a8a..0000000000 --- a/src/mainboard/supermicro/h8dmr_fam10/mb_sysconf.h +++ /dev/null @@ -1,26 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007 AMD - * Written by Yinghai Lu for AMD. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef MB_SYSCONF_H -#define MB_SYSCONF_H - -struct mb_sysconf_t { - unsigned char bus_mcp55[8]; //1 - unsigned int apicid_mcp55; -}; - -#endif diff --git a/src/mainboard/supermicro/h8dmr_fam10/mptable.c b/src/mainboard/supermicro/h8dmr_fam10/mptable.c deleted file mode 100644 index cdb2980867..0000000000 --- a/src/mainboard/supermicro/h8dmr_fam10/mptable.c +++ /dev/null @@ -1,114 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007 AMD - * Written by Yinghai Lu for AMD. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include -#include -#include -#include "mb_sysconf.h" - -static void *smp_write_config_table(void *v) -{ - struct mp_config_table *mc; - struct mb_sysconf_t *m; - unsigned int sbdn; - int i, j, bus_isa; - - mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); - - mptable_init(mc, LOCAL_APIC_ADDR); - - smp_write_processors(mc); - - sbdn = sysconf.sbdn; - m = sysconf.mb; - - mptable_write_buses(mc, NULL, &bus_isa); - -/*I/O APICs: APIC ID Version State Address*/ - { - struct device *dev; - struct resource *res; - uint32_t dword; - - dev = dev_find_slot(m->bus_mcp55[0], PCI_DEVFN(sbdn+ 0x1,0)); - if (dev) { - res = find_resource(dev, PCI_BASE_ADDRESS_1); - if (res) { - smp_write_ioapic(mc, m->apicid_mcp55, 0x11, - res2mmio(res, 0, 0)); - } - - dword = 0x43c6c643; - pci_write_config32(dev, 0x7c, dword); - - dword = 0x81001a00; - pci_write_config32(dev, 0x80, dword); - - dword = 0xd00012d2; - pci_write_config32(dev, 0x84, dword); - - } - - - } - - mptable_add_isa_interrupts(mc, bus_isa, m->apicid_mcp55, 0); - - /*I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ - smp_write_pci_intsrc(mc, mp_INT, m->bus_mcp55[0], sbdn + 1, 1, m->apicid_mcp55, 0xa); - - smp_write_pci_intsrc(mc, mp_INT, m->bus_mcp55[0], sbdn + 2, 0, m->apicid_mcp55, 0x16); // 22) - - smp_write_pci_intsrc(mc, mp_INT, m->bus_mcp55[0], sbdn + 2, 1, m->apicid_mcp55, 0x17); // 23) - - smp_write_pci_intsrc(mc, mp_INT, m->bus_mcp55[0], sbdn + 6, 1, m->apicid_mcp55, 0x17); // 23) - - smp_write_pci_intsrc(mc, mp_INT, m->bus_mcp55[0], sbdn + 5, 0, m->apicid_mcp55, 0x14); // 20) - smp_write_pci_intsrc(mc, mp_INT, m->bus_mcp55[0], sbdn + 5, 1, m->apicid_mcp55, 0x17); // 23) - smp_write_pci_intsrc(mc, mp_INT, m->bus_mcp55[0], sbdn + 5, 2, m->apicid_mcp55, 0x15); // 21) - - smp_write_pci_intsrc(mc, mp_INT, m->bus_mcp55[0], sbdn + 8, 0, m->apicid_mcp55, 0x16); // 22) - smp_write_pci_intsrc(mc, mp_INT, m->bus_mcp55[0], sbdn + 9, 0, m->apicid_mcp55, 0x15); // 21) - - for(j = 7; j >= 2; j--) { - if(!m->bus_mcp55[j]) continue; - for(i = 0; i < 4; i++) { - smp_write_pci_intsrc(mc, mp_INT, m->bus_mcp55[j], 0x00, i, m->apicid_mcp55, 0x10 + (2+j+i+4-sbdn%4)%4); - } - } - - for(j = 0; j < 1; j++) - for(i = 0; i < 4; i++) { - smp_write_pci_intsrc(mc, mp_INT, m->bus_mcp55[1], 0x04+j, i, m->apicid_mcp55, 0x10 + (2+i+j)%4); - } - -/*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN#*/ - mptable_lintsrc(mc, bus_isa); - /* There is no extension information... */ - - /* Compute the checksums */ - return mptable_finalize(mc); -} - -unsigned long write_smp_table(unsigned long addr) -{ - void *v; - v = smp_write_floating_table(addr, 0); - return (unsigned long)smp_write_config_table(v); -} diff --git a/src/mainboard/supermicro/h8dmr_fam10/resourcemap.c b/src/mainboard/supermicro/h8dmr_fam10/resourcemap.c deleted file mode 100644 index 2398ba25d7..0000000000 --- a/src/mainboard/supermicro/h8dmr_fam10/resourcemap.c +++ /dev/null @@ -1,284 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007 AMD - * Written by Yinghai Lu for AMD. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include - -void setup_mb_resource_map(void) -{ - static const unsigned int register_values[] = { - /* Careful set limit registers before base registers which contain the enables */ - /* DRAM Limit i Registers - * F1:0x44 i = 0 - * F1:0x4C i = 1 - * F1:0x54 i = 2 - * F1:0x5C i = 3 - * F1:0x64 i = 4 - * F1:0x6C i = 5 - * F1:0x74 i = 6 - * F1:0x7C i = 7 - * [ 2: 0] Destination Node ID - * 000 = Node 0 - * 001 = Node 1 - * 010 = Node 2 - * 011 = Node 3 - * 100 = Node 4 - * 101 = Node 5 - * 110 = Node 6 - * 111 = Node 7 - * [ 7: 3] Reserved - * [10: 8] Interleave select - * specifies the values of A[14:12] to use with interleave enable. - * [15:11] Reserved - * [31:16] DRAM Limit Address i Bits 39-24 - * This field defines the upper address bits of a 40 bit address - * that define the end of the DRAM region. - */ - // ADDRMAP_REG(0x44), 0x0000f8f8, 0x00000000, // Don't touch it, we need it for CAR with FAM10 - ADDRMAP_REG(0x4C), 0x0000f8f8, 0x00000001, - ADDRMAP_REG(0x54), 0x0000f8f8, 0x00000002, - ADDRMAP_REG(0x5C), 0x0000f8f8, 0x00000003, - ADDRMAP_REG(0x64), 0x0000f8f8, 0x00000004, - ADDRMAP_REG(0x6C), 0x0000f8f8, 0x00000005, - ADDRMAP_REG(0x74), 0x0000f8f8, 0x00000006, - ADDRMAP_REG(0x7C), 0x0000f8f8, 0x00000007, - - /* DRAM Base i Registers - * F1:0x40 i = 0 - * F1:0x48 i = 1 - * F1:0x50 i = 2 - * F1:0x58 i = 3 - * F1:0x60 i = 4 - * F1:0x68 i = 5 - * F1:0x70 i = 6 - * F1:0x78 i = 7 - * [ 0: 0] Read Enable - * 0 = Reads Disabled - * 1 = Reads Enabled - * [ 1: 1] Write Enable - * 0 = Writes Disabled - * 1 = Writes Enabled - * [ 7: 2] Reserved - * [10: 8] Interleave Enable - * 000 = No interleave - * 001 = Interleave on A[12] (2 nodes) - * 010 = reserved - * 011 = Interleave on A[12] and A[14] (4 nodes) - * 100 = reserved - * 101 = reserved - * 110 = reserved - * 111 = Interleve on A[12] and A[13] and A[14] (8 nodes) - * [15:11] Reserved - * [13:16] DRAM Base Address i Bits 39-24 - * This field defines the upper address bits of a 40-bit address - * that define the start of the DRAM region. - */ - // ADDRMAP_REG(0x40), 0x0000f8fc, 0x00000000, // don't touch it, we need it for CAR with FAM10 - ADDRMAP_REG(0x48), 0x0000f8fc, 0x00000000, - ADDRMAP_REG(0x50), 0x0000f8fc, 0x00000000, - ADDRMAP_REG(0x58), 0x0000f8fc, 0x00000000, - ADDRMAP_REG(0x60), 0x0000f8fc, 0x00000000, - ADDRMAP_REG(0x68), 0x0000f8fc, 0x00000000, - ADDRMAP_REG(0x70), 0x0000f8fc, 0x00000000, - ADDRMAP_REG(0x78), 0x0000f8fc, 0x00000000, - - /* Memory-Mapped I/O Limit i Registers - * F1:0x84 i = 0 - * F1:0x8C i = 1 - * F1:0x94 i = 2 - * F1:0x9C i = 3 - * F1:0xA4 i = 4 - * F1:0xAC i = 5 - * F1:0xB4 i = 6 - * F1:0xBC i = 7 - * [ 2: 0] Destination Node ID - * 000 = Node 0 - * 001 = Node 1 - * 010 = Node 2 - * 011 = Node 3 - * 100 = Node 4 - * 101 = Node 5 - * 110 = Node 6 - * 111 = Node 7 - * [ 3: 3] Reserved - * [ 5: 4] Destination Link ID - * 00 = Link 0 - * 01 = Link 1 - * 10 = Link 2 - * 11 = Reserved - * [ 6: 6] Reserved - * [ 7: 7] Non-Posted - * 0 = CPU writes may be posted - * 1 = CPU writes must be non-posted - * [31: 8] Memory-Mapped I/O Limit Address i (39-16) - * This field defines the upp address bits of a 40-bit address that - * defines the end of a memory-mapped I/O region n - */ - ADDRMAP_REG(0x84), 0x00000048, 0x00000000, - ADDRMAP_REG(0x8C), 0x00000048, 0x00000000, - ADDRMAP_REG(0x94), 0x00000048, 0x00000000, - ADDRMAP_REG(0x9C), 0x00000048, 0x00000000, - ADDRMAP_REG(0xA4), 0x00000048, 0x00000000, - ADDRMAP_REG(0xAC), 0x00000048, 0x00000000, - ADDRMAP_REG(0xB4), 0x00000048, 0x00000000, -// ADDRMAP_REG(0xBC), 0x00000048, 0x00ffff00, - - /* Memory-Mapped I/O Base i Registers - * F1:0x80 i = 0 - * F1:0x88 i = 1 - * F1:0x90 i = 2 - * F1:0x98 i = 3 - * F1:0xA0 i = 4 - * F1:0xA8 i = 5 - * F1:0xB0 i = 6 - * F1:0xB8 i = 7 - * [ 0: 0] Read Enable - * 0 = Reads disabled - * 1 = Reads Enabled - * [ 1: 1] Write Enable - * 0 = Writes disabled - * 1 = Writes Enabled - * [ 2: 2] Cpu Disable - * 0 = Cpu can use this I/O range - * 1 = Cpu requests do not use this I/O range - * [ 3: 3] Lock - * 0 = base/limit registers i are read/write - * 1 = base/limit registers i are read-only - * [ 7: 4] Reserved - * [31: 8] Memory-Mapped I/O Base Address i (39-16) - * This field defines the upper address bits of a 40bit address - * that defines the start of memory-mapped I/O region i - */ - ADDRMAP_REG(0x80), 0x000000f0, 0x00000000, - ADDRMAP_REG(0x88), 0x000000f0, 0x00000000, - ADDRMAP_REG(0x90), 0x000000f0, 0x00000000, - ADDRMAP_REG(0x98), 0x000000f0, 0x00000000, - ADDRMAP_REG(0xA0), 0x000000f0, 0x00000000, - ADDRMAP_REG(0xA8), 0x000000f0, 0x00000000, - ADDRMAP_REG(0xB0), 0x000000f0, 0x00000000, -// ADDRMAP_REG(0xB8), 0x000000f0, 0x00fc0003, - - /* PCI I/O Limit i Registers - * F1:0xC4 i = 0 - * F1:0xCC i = 1 - * F1:0xD4 i = 2 - * F1:0xDC i = 3 - * [ 2: 0] Destination Node ID - * 000 = Node 0 - * 001 = Node 1 - * 010 = Node 2 - * 011 = Node 3 - * 100 = Node 4 - * 101 = Node 5 - * 110 = Node 6 - * 111 = Node 7 - * [ 3: 3] Reserved - * [ 5: 4] Destination Link ID - * 00 = Link 0 - * 01 = Link 1 - * 10 = Link 2 - * 11 = reserved - * [11: 6] Reserved - * [24:12] PCI I/O Limit Address i - * This field defines the end of PCI I/O region n - * [31:25] Reserved - */ -// WARD CHANGED - ADDRMAP_REG(0xC4), 0xFE000FC8, 0x01fff020, - ADDRMAP_REG(0xCC), 0xFE000FC8, 0x00000000, // need to talk to ANALOG of second CK804 to release PCI E reset - ADDRMAP_REG(0xD4), 0xFE000FC8, 0x00000000, - ADDRMAP_REG(0xDC), 0xFE000FC8, 0x00000000, - - /* PCI I/O Base i Registers - * F1:0xC0 i = 0 - * F1:0xC8 i = 1 - * F1:0xD0 i = 2 - * F1:0xD8 i = 3 - * [ 0: 0] Read Enable - * 0 = Reads Disabled - * 1 = Reads Enabled - * [ 1: 1] Write Enable - * 0 = Writes Disabled - * 1 = Writes Enabled - * [ 3: 2] Reserved - * [ 4: 4] VGA Enable - * 0 = VGA matches Disabled - * 1 = matches all address < 64K and where A[9:0] is in the - * range 3B0-3BB or 3C0-3DF independen of the base & limit registers - * [ 5: 5] ISA Enable - * 0 = ISA matches Disabled - * 1 = Blocks address < 64K and in the last 768 bytes of eack 1K block - * from matching agains this base/limit pair - * [11: 6] Reserved - * [24:12] PCI I/O Base i - * This field defines the start of PCI I/O region n - * [31:25] Reserved - */ - // WARD CHANGED - ADDRMAP_REG(0xC0), 0xFE000FCC, 0x00000033, - ADDRMAP_REG(0xC8), 0xFE000FCC, 0x00000000, - ADDRMAP_REG(0xD0), 0xFE000FCC, 0x00000000, - ADDRMAP_REG(0xD8), 0xFE000FCC, 0x00000000, - - /* Config Base and Limit i Registers - * F1:0xE0 i = 0 - * F1:0xE4 i = 1 - * F1:0xE8 i = 2 - * F1:0xEC i = 3 - * [ 0: 0] Read Enable - * 0 = Reads Disabled - * 1 = Reads Enabled - * [ 1: 1] Write Enable - * 0 = Writes Disabled - * 1 = Writes Enabled - * [ 2: 2] Device Number Compare Enable - * 0 = The ranges are based on bus number - * 1 = The ranges are ranges of devices on bus 0 - * [ 3: 3] Reserved - * [ 6: 4] Destination Node - * 000 = Node 0 - * 001 = Node 1 - * 010 = Node 2 - * 011 = Node 3 - * 100 = Node 4 - * 101 = Node 5 - * 110 = Node 6 - * 111 = Node 7 - * [ 7: 7] Reserved - * [ 9: 8] Destination Link - * 00 = Link 0 - * 01 = Link 1 - * 10 = Link 2 - * 11 - Reserved - * [15:10] Reserved - * [23:16] Bus Number Base i - * This field defines the lowest bus number in configuration region i - * [31:24] Bus Number Limit i - * This field defines the highest bus number in configuration region i - */ - // WARD CHANGED - ADDRMAP_REG(0xE0), 0x0000FC88, 0x3f000203, /* link 2 of CPU 0 --> Nvidia MCP55 Pro */ - ADDRMAP_REG(0xE4), 0x0000FC88, 0x00000000, - ADDRMAP_REG(0xE8), 0x0000FC88, 0x00000000, - ADDRMAP_REG(0xEC), 0x0000FC88, 0x00000000, - - }; - - int max; - max = ARRAY_SIZE(register_values); - setup_resource_map(register_values, max); -} diff --git a/src/mainboard/supermicro/h8dmr_fam10/romstage.c b/src/mainboard/supermicro/h8dmr_fam10/romstage.c deleted file mode 100644 index 6f6ac712c7..0000000000 --- a/src/mainboard/supermicro/h8dmr_fam10/romstage.c +++ /dev/null @@ -1,269 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007 AMD - * Written by Yinghai Lu for AMD. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include // for enable the FAN - -#include "cpu/amd/quadcore/quadcore.c" -#include -#include "southbridge/nvidia/mcp55/early_setup_car.c" - -#define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1) -#define SUPERIO_DEV PNP_DEV(0x2e, 0) - -int spd_read_byte(unsigned int device, unsigned int address); - - -inline int spd_read_byte(unsigned int device, unsigned int address) -{ - return smbus_read_byte(device, address); -} - -unsigned int get_sbdn(unsigned int bus) -{ - pci_devfn_t dev; - - /* Find the device. */ - dev = pci_locate_device_on_bus(PCI_ID(PCI_VENDOR_ID_NVIDIA, - PCI_DEVICE_ID_NVIDIA_MCP55_HT), bus); - - return (dev >> 15) & 0x1f; -} - -static void sio_setup(void) -{ - uint32_t dword; - uint8_t byte; - - enable_smbus(); - // smbusx_write_byte(1, (0x58 >> 1), 0, 0x80); /* select bank0 */ - /* set FAN ctrl to DC mode */ - smbusx_write_byte(1, (0x58 >> 1), 0xb1, 0xff); - - byte = pci_read_config8(PCI_DEV(0, MCP55_DEVN_BASE + 1, 0), 0x7b); - byte |= 0x20; - pci_write_config8(PCI_DEV(0, MCP55_DEVN_BASE + 1, 0), 0x7b, byte); - - dword = pci_read_config32(PCI_DEV(0, MCP55_DEVN_BASE + 1, 0), 0xa0); - dword |= (1 << 0); - pci_write_config32(PCI_DEV(0, MCP55_DEVN_BASE + 1, 0), 0xa0, dword); - - dword = pci_read_config32(PCI_DEV(0, MCP55_DEVN_BASE + 1, 0), 0xa4); - dword |= (1 << 16); - pci_write_config32(PCI_DEV(0, MCP55_DEVN_BASE + 1, 0), 0xa4, dword); -} - -static const u8 spd_addr[] = { - //first node - RC00, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, -#if CONFIG_MAX_PHYSICAL_CPUS > 1 - //second node - RC00, DIMM4, DIMM6, 0, 0, DIMM5, DIMM7, 0, 0, -#endif -}; - -void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) -{ - struct sys_info *sysinfo = get_sysinfo(); - u32 bsp_apicid = 0, val, wants_reset; - msr_t msr; - - timestamp_init(timestamp_get()); - timestamp_add_now(TS_START_ROMSTAGE); - - if (!cpu_init_detectedx && boot_cpu()) { - /* Nothing special needs to be done to find bus 0 */ - /* Allow the HT devices to be found */ - set_bsp_node_CHtExtNodeCfgEn(); - enumerate_ht_chain(); - sio_setup(); - } - - post_code(0x30); - - if (bist == 0) - bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo); - - post_code(0x32); - - winbond_set_clksel_48(SUPERIO_DEV); - winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); - - console_init(); - - /* Halt if there was a built in self test failure */ - report_bist_failure(bist); - - val = cpuid_eax(1); - printk(BIOS_DEBUG, "BSP Family_Model: %08x\n", val); - printk(BIOS_DEBUG, "*sysinfo range: [%p,%p]\n", sysinfo, sysinfo + 1); - printk(BIOS_DEBUG, "bsp_apicid = %02x\n", bsp_apicid); - printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx); - - /* Setup sysinfo defaults */ - set_sysinfo_in_ram(0); - - update_microcode(val); - - post_code(0x33); - - cpuSetAMDMSR(0); - post_code(0x34); - - amd_ht_init(sysinfo); - post_code(0x35); - - /* Setup nodes PCI space and start core 0 AP init. */ - finalize_node_setup(sysinfo); - - /* Setup any mainboard PCI settings etc. */ - setup_mb_resource_map(); - post_code(0x36); - - /* wait for all the APs core0 started by finalize_node_setup. */ - - /* FIXME: A bunch of cores are going to start output to serial at once. - * It would be nice to fixup prink spinlocks for ROM XIP mode. - * I think it could be done by putting the spinlock flag in the cache - * of the BSP located right after sysinfo. - */ - - wait_all_core0_started(); -#if CONFIG(LOGICAL_CPUS) - /* Core0 on each node is configured. Now setup any additional cores. */ - printk(BIOS_DEBUG, "start_other_cores()\n"); - start_other_cores(bsp_apicid); - post_code(0x37); - wait_all_other_cores_started(bsp_apicid); -#endif - - post_code(0x38); - -#if CONFIG(SET_FIDVID) - msr = rdmsr(MSR_COFVID_STS); - printk(BIOS_DEBUG, "\nBegin FIDVID MSR 0xc0010071 0x%08x 0x%08x\n", - msr.hi, msr.lo); - - /* FIXME: The sb fid change may survive the warm reset and only - * need to be done once.*/ - - enable_fid_change_on_sb(sysinfo->sbbusn, sysinfo->sbdn); - post_code(0x39); - - if (!warm_reset_detect(0)) { // BSP is node 0 - init_fidvid_bsp(bsp_apicid, sysinfo->nodes); - } else { - init_fidvid_stage2(bsp_apicid, 0); // BSP is node 0 - } - - post_code(0x3A); - - /* show final fid and vid */ - msr = rdmsr(MSR_COFVID_STS); - printk(BIOS_DEBUG, "End FIDVIDMSR 0xc0010071 0x%08x 0x%08x\n", - msr.hi, msr.lo); -#endif - - init_timer(); // Need to use TMICT to synchronize FID/VID - - wants_reset = mcp55_early_setup_x(); - - /* Reset for HT, FIDVID, PLL and errata changes to take affect. */ - if (!warm_reset_detect(0)) { - printk(BIOS_INFO, "...WARM RESET...\n\n\n"); - soft_reset(); - die("After soft_reset - shouldn't see this message!!!\n"); - } - - if (wants_reset) - printk(BIOS_DEBUG, "mcp55_early_setup_x wants additional reset!\n"); - - post_code(0x3B); - - /* It's the time to set ctrl in sysinfo now; */ - printk(BIOS_DEBUG, "fill_mem_ctrl()\n"); - fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr); - - post_code(0x3D); - - // printk(BIOS_DEBUG, "enable_smbus()\n"); - // enable_smbus(); /* enable in sio_setup */ - - post_code(0x40); - - raminit_amdmct(sysinfo); - - cbmem_initialize_empty(); - post_code(0x41); - - amdmct_cbmem_store_info(sysinfo); - -} - -/** - * BOOL AMD_CB_ManualBUIDSwapList(u8 Node, u8 Link, u8 **List) - * Description: - * This routine is called every time a non-coherent chain is processed. - * BUID assignment may be controlled explicitly on a non-coherent chain. Provide a - * swap list. The first part of the list controls the BUID assignment and the - * second part of the list provides the device to device linking. Device orientation - * can be detected automatically, or explicitly. See documentation for more details. - * - * Automatic non-coherent init assigns BUIDs starting at 1 and incrementing sequentially - * based on each device's unit count. - * - * Parameters: - * @param[in] node = The node on which this chain is located - * @param[in] link = The link on the host for this chain - * @param[out] List = supply a pointer to a list - */ -BOOL AMD_CB_ManualBUIDSwapList (u8 node, u8 link, const u8 **List) -{ - static const u8 swaplist[] = { 0xFF, CONFIG_HT_CHAIN_UNITID_BASE, CONFIG_HT_CHAIN_END_UNITID_BASE, 0xFF }; - /* If the BUID was adjusted in early_ht we need to do the manual override */ - if ((CONFIG_HT_CHAIN_UNITID_BASE != 0) && (CONFIG_HT_CHAIN_END_UNITID_BASE != 0)) { - printk(BIOS_DEBUG, "AMD_CB_ManualBUIDSwapList()\n"); - if ((node == 0) && (link == 0)) { /* BSP SB link */ - *List = swaplist; - return 1; - } - } - - return 0; -} diff --git a/src/mainboard/supermicro/h8qme_fam10/Kconfig b/src/mainboard/supermicro/h8qme_fam10/Kconfig deleted file mode 100644 index 55d1153c7b..0000000000 --- a/src/mainboard/supermicro/h8qme_fam10/Kconfig +++ /dev/null @@ -1,60 +0,0 @@ -if BOARD_SUPERMICRO_H8QME_FAM10 - -config BOARD_SPECIFIC_OPTIONS - def_bool y - select CPU_AMD_SOCKET_F_1207 - select DIMM_DDR2 - select DIMM_REGISTERED - select NORTHBRIDGE_AMD_AMDFAM10 - select SOUTHBRIDGE_AMD_AMD8132 - select SOUTHBRIDGE_NVIDIA_MCP55 - select HT_CHAIN_DISTRIBUTE - select SUPERIO_WINBOND_W83627HF - select HAVE_OPTION_TABLE - select HAVE_PIRQ_TABLE - select HAVE_MP_TABLE - select LIFT_BSP_APIC_ID - select BOARD_ROMSIZE_KB_1024 - select ENABLE_APIC_EXT_ID - -config MAINBOARD_DIR - string - default supermicro/h8qme_fam10 - -config DCACHE_RAM_BASE - hex - default 0xc4000 - -config DCACHE_RAM_SIZE - hex - default 0x0c000 - -config APIC_ID_OFFSET - hex - default 0x0 - -config MAINBOARD_PART_NUMBER - string - default "H8QME-2+ (Fam10)" - -config MAX_CPUS - int - default 16 - -config MAX_PHYSICAL_CPUS - int - default 4 - -config HT_CHAIN_END_UNITID_BASE - hex - default 0x20 - -config HT_CHAIN_UNITID_BASE - hex - default 0x1 - -config IRQ_SLOT_COUNT - int - default 11 - -endif # BOARD_SUPERMICRO_H8QME_FAM10 diff --git a/src/mainboard/supermicro/h8qme_fam10/Kconfig.name b/src/mainboard/supermicro/h8qme_fam10/Kconfig.name deleted file mode 100644 index d7f1933d60..0000000000 --- a/src/mainboard/supermicro/h8qme_fam10/Kconfig.name +++ /dev/null @@ -1,2 +0,0 @@ -config BOARD_SUPERMICRO_H8QME_FAM10 - bool "H8QME-2+ (Fam10)" diff --git a/src/mainboard/supermicro/h8qme_fam10/Makefile.inc b/src/mainboard/supermicro/h8qme_fam10/Makefile.inc deleted file mode 100644 index 91d4b39c32..0000000000 --- a/src/mainboard/supermicro/h8qme_fam10/Makefile.inc +++ /dev/null @@ -1,16 +0,0 @@ -# -# This file is part of the coreboot project. -# -# This program is free software; you can redistribute it and/or modify -# it under the terms of the GNU General Public License as published by -# the Free Software Foundation; version 2 of the License. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# - -romstage-y += resourcemap.c - -ramstage-y += get_bus_conf.c diff --git a/src/mainboard/supermicro/h8qme_fam10/board_info.txt b/src/mainboard/supermicro/h8qme_fam10/board_info.txt deleted file mode 100644 index cb3000fd04..0000000000 --- a/src/mainboard/supermicro/h8qme_fam10/board_info.txt +++ /dev/null @@ -1,2 +0,0 @@ -Category: server -Board URL: http://www.supermicro.com/Aplus/motherboard/Opteron8000/MCP55/H8QME-2.cfm diff --git a/src/mainboard/supermicro/h8qme_fam10/cmos.layout b/src/mainboard/supermicro/h8qme_fam10/cmos.layout deleted file mode 100644 index 331e0162bb..0000000000 --- a/src/mainboard/supermicro/h8qme_fam10/cmos.layout +++ /dev/null @@ -1,102 +0,0 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2015 Timothy Pearson , Raptor Engineering -## Copyright (C) 2007 AMD -## Written by Yinghai Lu for AMD. -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; either version 2 of the License, or -## (at your option) any later version. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## - -entries - -0 384 r 0 reserved_memory -384 1 e 4 boot_option -388 4 h 0 reboot_counter -393 3 r 0 unused -#394 7 unused -401 1 e 1 interleave_chip_selects -402 1 e 1 interleave_nodes -403 1 e 1 interleave_memory_channels -404 2 e 8 max_mem_clock -406 1 e 2 multi_core -412 4 e 6 debug_level -416 5 e 10 ecc_scrub_rate -440 4 e 9 slow_cpu -444 1 e 1 nmi -445 1 e 1 gart -446 1 e 1 power_on_after_fail -456 1 e 1 ECC_memory -457 1 e 1 ECC_redirection -728 256 h 0 user_data -984 16 h 0 check_sum -# Reserve the extended AMD configuration registers -1000 24 r 0 amd_reserved - - - -enumerations - -#ID value text -1 0 Disable -1 1 Enable -2 0 Enable -2 1 Disable -4 0 Fallback -4 1 Normal -6 0 Emergency -6 1 Alert -6 2 Critical -6 3 Error -6 4 Warning -6 5 Notice -6 6 Information -6 7 Debug -6 8 Spew -8 0 DDR2-800 -8 1 DDR2-667 -8 2 DDR2-533 -8 3 DDR2-400 -9 0 off -9 1 87.5% -9 2 75.0% -9 3 62.5% -9 4 50.0% -9 5 37.5% -9 6 25.0% -9 7 12.5% -10 0 Disabled -10 1 40ns -10 2 80ns -10 3 160ns -10 4 320ns -10 5 640ns -10 6 1.28us -10 7 2.56us -10 8 5.12us -10 9 10.2us -10 10 20.5us -10 11 41us -10 12 81.9us -10 13 163.8us -10 14 327.7us -10 15 655.4us -10 16 1.31ms -10 17 2.62ms -10 18 5.24ms -10 19 10.49ms -10 20 20.97sms -10 21 42ms -10 22 84ms - -checksums - -checksum 392 983 984 diff --git a/src/mainboard/supermicro/h8qme_fam10/devicetree.cb b/src/mainboard/supermicro/h8qme_fam10/devicetree.cb deleted file mode 100644 index 317d643d9a..0000000000 --- a/src/mainboard/supermicro/h8qme_fam10/devicetree.cb +++ /dev/null @@ -1,115 +0,0 @@ -chip northbridge/amd/amdfam10/root_complex # Root complex - device cpu_cluster 0 on # (L)APIC cluster - chip cpu/amd/socket_F_1207 # CPU socket - device lapic 0 on end # Local APIC of the CPU - end - end - device domain 0 on # PCI domain - subsystemid 0x15d9 0x1511 inherit - chip northbridge/amd/amdfam10 # Northbridge / RAM controller - device pci 18.0 on end - device pci 18.0 on end - device pci 18.0 on # SB on link 2 - chip southbridge/nvidia/mcp55 # Southbridge - device pci 0.0 on end # HT - device pci 1.0 on # LPC - chip superio/winbond/w83627hf # Super I/O - device pnp 2e.0 off # Floppy - io 0x60 = 0x3f0 - irq 0x70 = 6 - drq 0x74 = 2 - end - device pnp 2e.1 off # Parallel port - io 0x60 = 0x378 - irq 0x70 = 7 - end - device pnp 2e.2 on # Com1 - io 0x60 = 0x3f8 - irq 0x70 = 4 - end - device pnp 2e.3 off # Com2 - io 0x60 = 0x2f8 - irq 0x70 = 3 - end - device pnp 2e.5 on # PS/2 keyboard - io 0x60 = 0x60 - io 0x62 = 0x64 - irq 0x70 = 1 - irq 0x72 = 12 - end - device pnp 2e.6 off # SFI - io 0x62 = 0x100 - end - device pnp 2e.7 off # GPIO, game port, MIDI - io 0x60 = 0x220 - io 0x62 = 0x300 - irq 0x70 = 9 - end - device pnp 2e.8 off end # WDTO PLED - device pnp 2e.9 off end # GPIO SUSLED - device pnp 2e.a off end # ACPI - device pnp 2e.b on # Hardware monitor - io 0x60 = 0x290 - irq 0x70 = 5 - end - end - end - device pci 1.1 on end - device pci 1.1 on # SM 1 - # PCI device SMBus address will - # depend on addon PCI device, do - # we need to scan_smbus_bus? - chip drivers/generic/generic # MAC EEPROM - device i2c 51 on end - end - end - device pci 2.0 on end # USB 1.1 - device pci 2.1 on end # USB 2 - device pci 4.0 on end # IDE - device pci 5.0 on end # SATA 0 - device pci 5.1 on end # SATA 1 - device pci 5.2 on end # SATA 2 - device pci 6.1 off end # AZA - device pci 7.0 on - device pci 1.0 on end - end - device pci 8.0 off end - device pci 9.0 off end - device pci a.0 on end # PCI E 5 - device pci b.0 on end # PCI E 4 - device pci c.0 on end # PCI E 3 - device pci d.0 on end # PCI E 2 - device pci e.0 on end # PCI E 1 - device pci f.0 on end # PCI E 0 - register "ide0_enable" = "1" - register "sata0_enable" = "1" - register "sata1_enable" = "1" - # 1: SMBus under 2e.8, 2: SM0 3: SM1 - register "mac_eeprom_smbus" = "3" - register "mac_eeprom_addr" = "0x51" - end - end - device pci 18.1 on end - device pci 18.2 on end - device pci 18.3 on end - device pci 18.4 on end - device pci 19.0 on end - device pci 19.0 on end - device pci 19.0 on - chip southbridge/amd/amd8132 - device pci 0.0 on end - device pci 0.1 on end - device pci 1.0 on - device pci 3.0 on end - device pci 3.1 on end - end - device pci 1.1 on end - end - end - device pci 19.1 on end - device pci 19.2 on end - device pci 19.3 on end - device pci 19.4 on end - end - end -end diff --git a/src/mainboard/supermicro/h8qme_fam10/get_bus_conf.c b/src/mainboard/supermicro/h8qme_fam10/get_bus_conf.c deleted file mode 100644 index 56ea43c7fe..0000000000 --- a/src/mainboard/supermicro/h8qme_fam10/get_bus_conf.c +++ /dev/null @@ -1,96 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007 AMD - * Written by Yinghai Lu for AMD. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include -#include -#include -#include - -#include - -#include -#include "mb_sysconf.h" - -// Global variables for MB layouts and these will be shared by irqtable mptable and acpi_tables -struct mb_sysconf_t mb_sysconf; - -unsigned int sbdn3; - -void get_bus_conf(void) -{ - - unsigned int apicid_base; - struct mb_sysconf_t *m; - - struct device *dev; - int i; - - sysconf.mb = &mb_sysconf; - - m = sysconf.mb; - memset(m, 0, sizeof(struct mb_sysconf_t)); - - get_default_pci1234(32); - - sysconf.sbdn = (sysconf.hcdn[0] & 0xff); // first byte of first chain - m->bus_mcp55[0] = (sysconf.pci1234[0] >> 12) & 0xff; - - m->bus_8132_0 = (sysconf.pci1234[1] >> 12) & 0xff; - sbdn3 = (sysconf.hcdn[1] & 0xff); // first byte of second chain - - /* MCP55 */ - dev = dev_find_slot(m->bus_mcp55[0], PCI_DEVFN(sysconf.sbdn + 0x06,0)); - - if (dev) { - m->bus_mcp55[1] = pci_read_config8(dev, PCI_SECONDARY_BUS); - } - else { - printk(BIOS_DEBUG, "ERROR - could not find PCI 1:%02x.0, using defaults\n", sysconf.sbdn + 0x06); - } - - for(i = 2; i < 8; i++) { - dev = dev_find_slot(m->bus_mcp55[0], PCI_DEVFN(sysconf.sbdn + 0x0a + i - 2, 0)); - if (dev) { - m->bus_mcp55[i] = pci_read_config8(dev, PCI_SECONDARY_BUS); - } - else { - printk(BIOS_DEBUG, "ERROR - could not find PCI %02x:%02x.0, using defaults\n", m->bus_mcp55[0], sysconf.sbdn + 0x0a + i - 2); - } - } - - /* 8132_1 */ - - dev = dev_find_slot(m->bus_8132_0, PCI_DEVFN(sbdn3, 0)); - m->bus_8132_1 = pci_read_config8(dev, PCI_SECONDARY_BUS); - m->bus_8132_2 = pci_read_config8(dev, PCI_SUBORDINATE_BUS); - m->bus_8132_2++; - - /* 8132_2 */ - dev = dev_find_slot(m->bus_8132_0, PCI_DEVFN(sbdn3 + 1, 0)); - m->bus_8132_2 = pci_read_config8(dev, PCI_SECONDARY_BUS); - -/*I/O APICs: APIC ID Version State Address*/ - if (CONFIG(LOGICAL_CPUS)) - apicid_base = get_apicid_base(3); - else - apicid_base = CONFIG_MAX_PHYSICAL_CPUS; - m->apicid_mcp55 = apicid_base+0; - m->apicid_8132_1 = apicid_base+1; - m->apicid_8132_2 = apicid_base+2; -} diff --git a/src/mainboard/supermicro/h8qme_fam10/irq_tables.c b/src/mainboard/supermicro/h8qme_fam10/irq_tables.c deleted file mode 100644 index b77e86209b..0000000000 --- a/src/mainboard/supermicro/h8qme_fam10/irq_tables.c +++ /dev/null @@ -1,137 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007 AMD - * Written by Yinghai Lu for AMD. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include -#include -#include - -#include -#include "mb_sysconf.h" - -static void write_pirq_info(struct irq_info *pirq_info, uint8_t bus, - uint8_t devfn, uint8_t link0, uint16_t bitmap0, - uint8_t link1, uint16_t bitmap1, uint8_t link2, - uint16_t bitmap2, uint8_t link3, uint16_t bitmap3, - uint8_t slot, uint8_t rfu) -{ - pirq_info->bus = bus; - pirq_info->devfn = devfn; - pirq_info->irq[0].link = link0; - pirq_info->irq[0].bitmap = bitmap0; - pirq_info->irq[1].link = link1; - pirq_info->irq[1].bitmap = bitmap1; - pirq_info->irq[2].link = link2; - pirq_info->irq[2].bitmap = bitmap2; - pirq_info->irq[3].link = link3; - pirq_info->irq[3].bitmap = bitmap3; - pirq_info->slot = slot; - pirq_info->rfu = rfu; -} - -unsigned long write_pirq_routing_table(unsigned long addr) -{ - - struct irq_routing_table *pirq; - struct irq_info *pirq_info; - unsigned int slot_num; - uint8_t *v; - struct mb_sysconf_t *m; - unsigned int sbdn; - - uint8_t sum = 0; - int i; - - sbdn = sysconf.sbdn; - m = sysconf.mb; - - /* Align the table to be 16 byte aligned. */ - addr += 15; - addr &= ~15; - - /* This table must be between 0xf0000 & 0x100000 */ - printk(BIOS_INFO, "Writing IRQ routing tables to 0x%lx...", addr); - - pirq = (void *)(addr); - v = (uint8_t *) (addr); - - pirq->signature = PIRQ_SIGNATURE; - pirq->version = PIRQ_VERSION; - - pirq->rtr_bus = m->bus_mcp55[0]; - pirq->rtr_devfn = PCI_DEVFN(sbdn + 6, 0); - - pirq->exclusive_irqs = 0; - - pirq->rtr_vendor = 0x10de; - pirq->rtr_device = 0x0364; - - pirq->miniport_data = 0; - - memset(pirq->rfu, 0, sizeof(pirq->rfu)); - - pirq_info = (void *)(&pirq->checksum + 1); - slot_num = 0; -//pci bridge - write_pirq_info(pirq_info, m->bus_mcp55[0], PCI_DEVFN(sbdn + 6, 0), 0x1, - 0x4ca0, 0x2, 0x4ca0, 0x3, 0x4ca0, 0x4, 0x4ca0, 0, 0); - pirq_info++; - slot_num++; - - for (i = 1; i < sysconf.hc_possible_num; i++) { - if (!(sysconf.pci1234[i] & 0x1)) - continue; - unsigned int busn = (sysconf.pci1234[i] >> 12) & 0xff; - unsigned int devn = sysconf.hcdn[i] & 0xff; - - write_pirq_info(pirq_info, busn, PCI_DEVFN(devn, 0), 0x1, 0x4ca0, - 0x2, 0x4ca0, 0x3, 0x4ca0, 0x4, 0x4ca0, 0, 0); - pirq_info++; - slot_num++; - } - -#if CONFIG_CBB - write_pirq_info(pirq_info, CONFIG_CBB, PCI_DEVFN(0, 0), 0x1, 0x4ca0, 0x2, - 0x4ca0, 0x3, 0x4ca0, 0x4, 0x4ca0, 0, 0); - pirq_info++; - slot_num++; - if (sysconf.nodes > 32) { - write_pirq_info(pirq_info, CONFIG_CBB - 1, PCI_DEVFN(0, 0), 0x1, - 0x4ca0, 0x2, 0x4ca0, 0x3, 0x4ca0, 0x4, 0x4ca0, - 0, 0); - pirq_info++; - slot_num++; - } -#endif - - pirq->size = 32 + 16 * slot_num; - - for (i = 0; i < pirq->size; i++) - sum += v[i]; - - sum = pirq->checksum - sum; - - if (sum != pirq->checksum) { - pirq->checksum = sum; - } - - printk(BIOS_INFO, "done.\n"); - - return (unsigned long)pirq_info; - -} diff --git a/src/mainboard/supermicro/h8qme_fam10/mb_sysconf.h b/src/mainboard/supermicro/h8qme_fam10/mb_sysconf.h deleted file mode 100644 index f93f9e8380..0000000000 --- a/src/mainboard/supermicro/h8qme_fam10/mb_sysconf.h +++ /dev/null @@ -1,32 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007 AMD - * Written by Yinghai Lu for AMD. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef MB_SYSCONF_H -#define MB_SYSCONF_H - -struct mb_sysconf_t { - unsigned char bus_mcp55[8]; //1 - unsigned int apicid_mcp55; - - unsigned char bus_8132_0; //7 - unsigned char bus_8132_1; //8 - unsigned char bus_8132_2; //9 - unsigned int apicid_8132_1; - unsigned int apicid_8132_2; -}; - -#endif diff --git a/src/mainboard/supermicro/h8qme_fam10/mptable.c b/src/mainboard/supermicro/h8qme_fam10/mptable.c deleted file mode 100644 index 7e6237f1f6..0000000000 --- a/src/mainboard/supermicro/h8qme_fam10/mptable.c +++ /dev/null @@ -1,112 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007 AMD - * Written by Yinghai Lu for AMD. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include -#include -#include -#include "mb_sysconf.h" - -extern unsigned int sbdn3; - -static void *smp_write_config_table(void *v) -{ - struct mp_config_table *mc; - struct mb_sysconf_t *m; - unsigned int sbdn; - int i, j, bus_isa; - - mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); - - mptable_init(mc, LOCAL_APIC_ADDR); - - smp_write_processors(mc); - - sbdn = sysconf.sbdn; - m = sysconf.mb; - - mptable_write_buses(mc, NULL, &bus_isa); - -/*I/O APICs: APIC ID Version State Address*/ - { - struct device *dev; - struct resource *res; - uint32_t dword; - - dev = dev_find_slot(m->bus_mcp55[0], PCI_DEVFN(sbdn+ 0x1,0)); - if (dev) { - res = find_resource(dev, PCI_BASE_ADDRESS_1); - if (res) { - smp_write_ioapic(mc, m->apicid_mcp55, 0x11, - res2mmio(res, 0, 0)); - } - - dword = 0x00000ab5; - pci_write_config32(dev, 0x7c, dword); - - dword = 0x5ab0a500; - pci_write_config32(dev, 0x80, dword); - - dword = 0xa000000b; - pci_write_config32(dev, 0x84, dword); - - } - - - } - - mptable_add_isa_interrupts(mc, bus_isa, m->apicid_mcp55, 0); - - /*I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ - smp_write_pci_intsrc(mc, mp_INT, m->bus_mcp55[0], sbdn + 1, 1, m->apicid_mcp55, 0x5); /* 5 SMBus, OK */ - smp_write_pci_intsrc(mc, mp_INT, m->bus_mcp55[0], sbdn + 2, 0, m->apicid_mcp55, 0xb); /* 11 USB, OK */ - smp_write_pci_intsrc(mc, mp_INT, m->bus_mcp55[0], sbdn + 2, 1, m->apicid_mcp55, 0xa); /* 10 USB, OK */ - smp_write_pci_intsrc(mc, mp_INT, m->bus_mcp55[0], sbdn + 5, 0, m->apicid_mcp55, 0x5); /* 5 IDE, OK*/ - smp_write_pci_intsrc(mc, mp_INT, m->bus_mcp55[0], sbdn + 5, 1, m->apicid_mcp55, 0xa); /* 10 IDE, OK*/ - smp_write_pci_intsrc(mc, mp_INT, m->bus_mcp55[0], sbdn + 5, 2, m->apicid_mcp55, 0xa); /* 10 IDE, OK*/ - smp_write_pci_intsrc(mc, mp_INT, m->bus_mcp55[0], sbdn + 6, 1, m->apicid_mcp55, 0xa); /* 10 VGA, OK*/ - - smp_write_pci_intsrc(mc, mp_INT, m->bus_8132_2, 3, 0, m->apicid_mcp55, 0x5); /* 5 eth0, OK*/ - smp_write_pci_intsrc(mc, mp_INT, m->bus_8132_2, 3, 1, m->apicid_mcp55, 0xb); /* 11 eth1, OK*/ - - for(j = 7;j >= 2; j--) { - if(!m->bus_mcp55[j]) continue; - for(i = 0; i < 4; i++) { - smp_write_pci_intsrc(mc, mp_INT, m->bus_mcp55[j], 0x00, i, m->apicid_mcp55, 0x10 + (2+j+i+4-sbdn%4)%4); - } - } - - for(j = 0; j < 1; j++) - for(i = 0; i < 4; i++) { - smp_write_pci_intsrc(mc, mp_INT, m->bus_mcp55[1], 0x04+j, i, m->apicid_mcp55, 0x10 + (2+i+j)%4); - } - -/*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN#*/ - mptable_lintsrc(mc, bus_isa); - /* There is no extension information... */ - - /* Compute the checksums */ - return mptable_finalize(mc); -} - -unsigned long write_smp_table(unsigned long addr) -{ - void *v; - v = smp_write_floating_table(addr, 0); - return (unsigned long)smp_write_config_table(v); -} diff --git a/src/mainboard/supermicro/h8qme_fam10/resourcemap.c b/src/mainboard/supermicro/h8qme_fam10/resourcemap.c deleted file mode 100644 index 2398ba25d7..0000000000 --- a/src/mainboard/supermicro/h8qme_fam10/resourcemap.c +++ /dev/null @@ -1,284 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007 AMD - * Written by Yinghai Lu for AMD. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include - -void setup_mb_resource_map(void) -{ - static const unsigned int register_values[] = { - /* Careful set limit registers before base registers which contain the enables */ - /* DRAM Limit i Registers - * F1:0x44 i = 0 - * F1:0x4C i = 1 - * F1:0x54 i = 2 - * F1:0x5C i = 3 - * F1:0x64 i = 4 - * F1:0x6C i = 5 - * F1:0x74 i = 6 - * F1:0x7C i = 7 - * [ 2: 0] Destination Node ID - * 000 = Node 0 - * 001 = Node 1 - * 010 = Node 2 - * 011 = Node 3 - * 100 = Node 4 - * 101 = Node 5 - * 110 = Node 6 - * 111 = Node 7 - * [ 7: 3] Reserved - * [10: 8] Interleave select - * specifies the values of A[14:12] to use with interleave enable. - * [15:11] Reserved - * [31:16] DRAM Limit Address i Bits 39-24 - * This field defines the upper address bits of a 40 bit address - * that define the end of the DRAM region. - */ - // ADDRMAP_REG(0x44), 0x0000f8f8, 0x00000000, // Don't touch it, we need it for CAR with FAM10 - ADDRMAP_REG(0x4C), 0x0000f8f8, 0x00000001, - ADDRMAP_REG(0x54), 0x0000f8f8, 0x00000002, - ADDRMAP_REG(0x5C), 0x0000f8f8, 0x00000003, - ADDRMAP_REG(0x64), 0x0000f8f8, 0x00000004, - ADDRMAP_REG(0x6C), 0x0000f8f8, 0x00000005, - ADDRMAP_REG(0x74), 0x0000f8f8, 0x00000006, - ADDRMAP_REG(0x7C), 0x0000f8f8, 0x00000007, - - /* DRAM Base i Registers - * F1:0x40 i = 0 - * F1:0x48 i = 1 - * F1:0x50 i = 2 - * F1:0x58 i = 3 - * F1:0x60 i = 4 - * F1:0x68 i = 5 - * F1:0x70 i = 6 - * F1:0x78 i = 7 - * [ 0: 0] Read Enable - * 0 = Reads Disabled - * 1 = Reads Enabled - * [ 1: 1] Write Enable - * 0 = Writes Disabled - * 1 = Writes Enabled - * [ 7: 2] Reserved - * [10: 8] Interleave Enable - * 000 = No interleave - * 001 = Interleave on A[12] (2 nodes) - * 010 = reserved - * 011 = Interleave on A[12] and A[14] (4 nodes) - * 100 = reserved - * 101 = reserved - * 110 = reserved - * 111 = Interleve on A[12] and A[13] and A[14] (8 nodes) - * [15:11] Reserved - * [13:16] DRAM Base Address i Bits 39-24 - * This field defines the upper address bits of a 40-bit address - * that define the start of the DRAM region. - */ - // ADDRMAP_REG(0x40), 0x0000f8fc, 0x00000000, // don't touch it, we need it for CAR with FAM10 - ADDRMAP_REG(0x48), 0x0000f8fc, 0x00000000, - ADDRMAP_REG(0x50), 0x0000f8fc, 0x00000000, - ADDRMAP_REG(0x58), 0x0000f8fc, 0x00000000, - ADDRMAP_REG(0x60), 0x0000f8fc, 0x00000000, - ADDRMAP_REG(0x68), 0x0000f8fc, 0x00000000, - ADDRMAP_REG(0x70), 0x0000f8fc, 0x00000000, - ADDRMAP_REG(0x78), 0x0000f8fc, 0x00000000, - - /* Memory-Mapped I/O Limit i Registers - * F1:0x84 i = 0 - * F1:0x8C i = 1 - * F1:0x94 i = 2 - * F1:0x9C i = 3 - * F1:0xA4 i = 4 - * F1:0xAC i = 5 - * F1:0xB4 i = 6 - * F1:0xBC i = 7 - * [ 2: 0] Destination Node ID - * 000 = Node 0 - * 001 = Node 1 - * 010 = Node 2 - * 011 = Node 3 - * 100 = Node 4 - * 101 = Node 5 - * 110 = Node 6 - * 111 = Node 7 - * [ 3: 3] Reserved - * [ 5: 4] Destination Link ID - * 00 = Link 0 - * 01 = Link 1 - * 10 = Link 2 - * 11 = Reserved - * [ 6: 6] Reserved - * [ 7: 7] Non-Posted - * 0 = CPU writes may be posted - * 1 = CPU writes must be non-posted - * [31: 8] Memory-Mapped I/O Limit Address i (39-16) - * This field defines the upp address bits of a 40-bit address that - * defines the end of a memory-mapped I/O region n - */ - ADDRMAP_REG(0x84), 0x00000048, 0x00000000, - ADDRMAP_REG(0x8C), 0x00000048, 0x00000000, - ADDRMAP_REG(0x94), 0x00000048, 0x00000000, - ADDRMAP_REG(0x9C), 0x00000048, 0x00000000, - ADDRMAP_REG(0xA4), 0x00000048, 0x00000000, - ADDRMAP_REG(0xAC), 0x00000048, 0x00000000, - ADDRMAP_REG(0xB4), 0x00000048, 0x00000000, -// ADDRMAP_REG(0xBC), 0x00000048, 0x00ffff00, - - /* Memory-Mapped I/O Base i Registers - * F1:0x80 i = 0 - * F1:0x88 i = 1 - * F1:0x90 i = 2 - * F1:0x98 i = 3 - * F1:0xA0 i = 4 - * F1:0xA8 i = 5 - * F1:0xB0 i = 6 - * F1:0xB8 i = 7 - * [ 0: 0] Read Enable - * 0 = Reads disabled - * 1 = Reads Enabled - * [ 1: 1] Write Enable - * 0 = Writes disabled - * 1 = Writes Enabled - * [ 2: 2] Cpu Disable - * 0 = Cpu can use this I/O range - * 1 = Cpu requests do not use this I/O range - * [ 3: 3] Lock - * 0 = base/limit registers i are read/write - * 1 = base/limit registers i are read-only - * [ 7: 4] Reserved - * [31: 8] Memory-Mapped I/O Base Address i (39-16) - * This field defines the upper address bits of a 40bit address - * that defines the start of memory-mapped I/O region i - */ - ADDRMAP_REG(0x80), 0x000000f0, 0x00000000, - ADDRMAP_REG(0x88), 0x000000f0, 0x00000000, - ADDRMAP_REG(0x90), 0x000000f0, 0x00000000, - ADDRMAP_REG(0x98), 0x000000f0, 0x00000000, - ADDRMAP_REG(0xA0), 0x000000f0, 0x00000000, - ADDRMAP_REG(0xA8), 0x000000f0, 0x00000000, - ADDRMAP_REG(0xB0), 0x000000f0, 0x00000000, -// ADDRMAP_REG(0xB8), 0x000000f0, 0x00fc0003, - - /* PCI I/O Limit i Registers - * F1:0xC4 i = 0 - * F1:0xCC i = 1 - * F1:0xD4 i = 2 - * F1:0xDC i = 3 - * [ 2: 0] Destination Node ID - * 000 = Node 0 - * 001 = Node 1 - * 010 = Node 2 - * 011 = Node 3 - * 100 = Node 4 - * 101 = Node 5 - * 110 = Node 6 - * 111 = Node 7 - * [ 3: 3] Reserved - * [ 5: 4] Destination Link ID - * 00 = Link 0 - * 01 = Link 1 - * 10 = Link 2 - * 11 = reserved - * [11: 6] Reserved - * [24:12] PCI I/O Limit Address i - * This field defines the end of PCI I/O region n - * [31:25] Reserved - */ -// WARD CHANGED - ADDRMAP_REG(0xC4), 0xFE000FC8, 0x01fff020, - ADDRMAP_REG(0xCC), 0xFE000FC8, 0x00000000, // need to talk to ANALOG of second CK804 to release PCI E reset - ADDRMAP_REG(0xD4), 0xFE000FC8, 0x00000000, - ADDRMAP_REG(0xDC), 0xFE000FC8, 0x00000000, - - /* PCI I/O Base i Registers - * F1:0xC0 i = 0 - * F1:0xC8 i = 1 - * F1:0xD0 i = 2 - * F1:0xD8 i = 3 - * [ 0: 0] Read Enable - * 0 = Reads Disabled - * 1 = Reads Enabled - * [ 1: 1] Write Enable - * 0 = Writes Disabled - * 1 = Writes Enabled - * [ 3: 2] Reserved - * [ 4: 4] VGA Enable - * 0 = VGA matches Disabled - * 1 = matches all address < 64K and where A[9:0] is in the - * range 3B0-3BB or 3C0-3DF independen of the base & limit registers - * [ 5: 5] ISA Enable - * 0 = ISA matches Disabled - * 1 = Blocks address < 64K and in the last 768 bytes of eack 1K block - * from matching agains this base/limit pair - * [11: 6] Reserved - * [24:12] PCI I/O Base i - * This field defines the start of PCI I/O region n - * [31:25] Reserved - */ - // WARD CHANGED - ADDRMAP_REG(0xC0), 0xFE000FCC, 0x00000033, - ADDRMAP_REG(0xC8), 0xFE000FCC, 0x00000000, - ADDRMAP_REG(0xD0), 0xFE000FCC, 0x00000000, - ADDRMAP_REG(0xD8), 0xFE000FCC, 0x00000000, - - /* Config Base and Limit i Registers - * F1:0xE0 i = 0 - * F1:0xE4 i = 1 - * F1:0xE8 i = 2 - * F1:0xEC i = 3 - * [ 0: 0] Read Enable - * 0 = Reads Disabled - * 1 = Reads Enabled - * [ 1: 1] Write Enable - * 0 = Writes Disabled - * 1 = Writes Enabled - * [ 2: 2] Device Number Compare Enable - * 0 = The ranges are based on bus number - * 1 = The ranges are ranges of devices on bus 0 - * [ 3: 3] Reserved - * [ 6: 4] Destination Node - * 000 = Node 0 - * 001 = Node 1 - * 010 = Node 2 - * 011 = Node 3 - * 100 = Node 4 - * 101 = Node 5 - * 110 = Node 6 - * 111 = Node 7 - * [ 7: 7] Reserved - * [ 9: 8] Destination Link - * 00 = Link 0 - * 01 = Link 1 - * 10 = Link 2 - * 11 - Reserved - * [15:10] Reserved - * [23:16] Bus Number Base i - * This field defines the lowest bus number in configuration region i - * [31:24] Bus Number Limit i - * This field defines the highest bus number in configuration region i - */ - // WARD CHANGED - ADDRMAP_REG(0xE0), 0x0000FC88, 0x3f000203, /* link 2 of CPU 0 --> Nvidia MCP55 Pro */ - ADDRMAP_REG(0xE4), 0x0000FC88, 0x00000000, - ADDRMAP_REG(0xE8), 0x0000FC88, 0x00000000, - ADDRMAP_REG(0xEC), 0x0000FC88, 0x00000000, - - }; - - int max; - max = ARRAY_SIZE(register_values); - setup_resource_map(register_values, max); -} diff --git a/src/mainboard/supermicro/h8qme_fam10/romstage.c b/src/mainboard/supermicro/h8qme_fam10/romstage.c deleted file mode 100644 index 7c489ca8dd..0000000000 --- a/src/mainboard/supermicro/h8qme_fam10/romstage.c +++ /dev/null @@ -1,321 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007 AMD - * Written by Yinghai Lu for AMD. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include // for enable the FAN - -#include "cpu/amd/quadcore/quadcore.c" -#include -#include "southbridge/nvidia/mcp55/early_setup_car.c" - -#define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1) -#define SUPERIO_DEV PNP_DEV(0x2e, 0) - -#define SMBUS_SWITCH1 0x70 -#define SMBUS_SWITCH2 0x72 - -int spd_read_byte(unsigned int device, unsigned int address); - -void activate_spd_rom(const struct mem_controller *ctrl) -{ - smbus_send_byte(SMBUS_SWITCH1, 5 & 0x0f); - smbus_send_byte(SMBUS_SWITCH2, (5 >> 4) & 0x0f); -} - -inline int spd_read_byte(unsigned int device, unsigned int address) -{ - return smbus_read_byte(device, address); -} - -unsigned int get_sbdn(unsigned int bus) -{ - pci_devfn_t dev; - - /* Find the device. */ - dev = pci_locate_device_on_bus(PCI_ID(PCI_VENDOR_ID_NVIDIA, - PCI_DEVICE_ID_NVIDIA_MCP55_HT), bus); - - return (dev >> 15) & 0x1f; -} - -static void sio_setup(void) -{ - uint32_t dword; - uint8_t byte; - enable_smbus(); -// smbusx_write_byte(1, (0x58 >> 1), 0, 0x80); /* select bank0 */ - smbusx_write_byte(1, (0x58 >> 1), 0xb1, 0xff); /* set FAN ctrl to DC mode */ - - byte = pci_read_config8(PCI_DEV(0, MCP55_DEVN_BASE+1, 0), 0x7b); - byte |= 0x20; - pci_write_config8(PCI_DEV(0, MCP55_DEVN_BASE+1, 0), 0x7b, byte); - - dword = pci_read_config32(PCI_DEV(0, MCP55_DEVN_BASE+1, 0), 0xa0); - dword |= (1 << 0); - pci_write_config32(PCI_DEV(0, MCP55_DEVN_BASE+1, 0), 0xa0, dword); - - dword = pci_read_config32(PCI_DEV(0, MCP55_DEVN_BASE+1, 0), 0xa4); - dword |= (1 << 16); - pci_write_config32(PCI_DEV(0, MCP55_DEVN_BASE+1, 0), 0xa4, dword); -} - -static const u8 spd_addr[] = { - /* first node */ - RC00, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, -#if CONFIG_MAX_PHYSICAL_CPUS > 1 - /* second node */ - RC00, DIMM4, DIMM6, 0, 0, DIMM5, DIMM7, 0, 0, -#endif -#if CONFIG_MAX_PHYSICAL_CPUS > 2 - /* third node */ - RC02, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, - /* fourth node */ - RC03, DIMM4, DIMM6, 0, 0, DIMM5, DIMM7, 0, 0, -#endif -}; - -#define GPIO1_DEV PNP_DEV(0x2e, W83627HF_GAME_MIDI_GPIO1) -#define GPIO2_DEV PNP_DEV(0x2e, W83627HF_GPIO2) -#define GPIO3_DEV PNP_DEV(0x2e, W83627HF_GPIO3) - -static void write_GPIO(void) -{ - pnp_enter_conf_state(GPIO1_DEV); - pnp_set_logical_device(GPIO1_DEV); - pnp_write_config(GPIO1_DEV, 0x30, 0x01); - pnp_write_config(GPIO1_DEV, 0x60, 0x00); - pnp_write_config(GPIO1_DEV, 0x61, 0x00); - pnp_write_config(GPIO1_DEV, 0x62, 0x00); - pnp_write_config(GPIO1_DEV, 0x63, 0x00); - pnp_write_config(GPIO1_DEV, 0x70, 0x00); - pnp_write_config(GPIO1_DEV, 0xf0, 0xff); - pnp_write_config(GPIO1_DEV, 0xf1, 0xff); - pnp_write_config(GPIO1_DEV, 0xf2, 0x00); - pnp_exit_conf_state(GPIO1_DEV); - - pnp_enter_conf_state(GPIO2_DEV); - pnp_set_logical_device(GPIO2_DEV); - pnp_write_config(GPIO2_DEV, 0x30, 0x01); - pnp_write_config(GPIO2_DEV, 0xf0, 0xef); - pnp_write_config(GPIO2_DEV, 0xf1, 0xff); - pnp_write_config(GPIO2_DEV, 0xf2, 0x00); - pnp_write_config(GPIO2_DEV, 0xf3, 0x00); - pnp_write_config(GPIO2_DEV, 0xf5, 0x48); - pnp_write_config(GPIO2_DEV, 0xf6, 0x00); - pnp_write_config(GPIO2_DEV, 0xf7, 0xc0); - pnp_exit_conf_state(GPIO2_DEV); - - pnp_enter_conf_state(GPIO3_DEV); - pnp_set_logical_device(GPIO3_DEV); - pnp_write_config(GPIO3_DEV, 0x30, 0x00); - pnp_write_config(GPIO3_DEV, 0xf0, 0xff); - pnp_write_config(GPIO3_DEV, 0xf1, 0xff); - pnp_write_config(GPIO3_DEV, 0xf2, 0xff); - pnp_write_config(GPIO3_DEV, 0xf3, 0x40); - pnp_exit_conf_state(GPIO3_DEV); -} - -void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) -{ - struct sys_info *sysinfo = get_sysinfo(); - u32 bsp_apicid = 0, val, wants_reset; - msr_t msr; - - timestamp_init(timestamp_get()); - timestamp_add_now(TS_START_ROMSTAGE); - - if (!cpu_init_detectedx && boot_cpu()) { - /* Nothing special needs to be done to find bus 0 */ - /* Allow the HT devices to be found */ - set_bsp_node_CHtExtNodeCfgEn(); - enumerate_ht_chain(); - sio_setup(); - } - - post_code(0x30); - - if (bist == 0) - bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo); - - post_code(0x32); - - winbond_set_clksel_48(SUPERIO_DEV); - winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); - - console_init(); - write_GPIO(); - printk(BIOS_DEBUG, "\n"); - - /* Halt if there was a built in self test failure */ - report_bist_failure(bist); - - val = cpuid_eax(1); - printk(BIOS_DEBUG, "BSP Family_Model: %08x\n", val); - printk(BIOS_DEBUG, "*sysinfo range: [%p,%p]\n",sysinfo,sysinfo+1); - printk(BIOS_DEBUG, "bsp_apicid = %02x\n", bsp_apicid); - printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx); - - /* Setup sysinfo defaults */ - set_sysinfo_in_ram(0); - - update_microcode(val); - - post_code(0x33); - - cpuSetAMDMSR(0); - post_code(0x34); - - amd_ht_init(sysinfo); - post_code(0x35); - - /* Setup nodes PCI space and start core 0 AP init. */ - finalize_node_setup(sysinfo); - - /* Setup any mainboard PCI settings etc. */ - setup_mb_resource_map(); - post_code(0x36); - - /* wait for all the APs core0 started by finalize_node_setup. */ - /* FIXME: A bunch of cores are going to start output to serial at once. - * It would be nice to fixup prink spinlocks for ROM XIP mode. - * I think it could be done by putting the spinlock flag in the cache - * of the BSP located right after sysinfo. - */ - - wait_all_core0_started(); -#if CONFIG(LOGICAL_CPUS) - /* Core0 on each node is configured. Now setup any additional cores. */ - printk(BIOS_DEBUG, "start_other_cores()\n"); - start_other_cores(bsp_apicid); - post_code(0x37); - wait_all_other_cores_started(bsp_apicid); -#endif - - post_code(0x38); - -#if CONFIG(SET_FIDVID) - msr = rdmsr(MSR_COFVID_STS); - printk(BIOS_DEBUG, "\nBegin FIDVID MSR 0xc0010071 0x%08x 0x%08x\n", msr.hi, msr.lo); - - /* FIXME: The sb fid change may survive the warm reset and only - * need to be done once.*/ - - enable_fid_change_on_sb(sysinfo->sbbusn, sysinfo->sbdn); - post_code(0x39); - - if (!warm_reset_detect(0)) { // BSP is node 0 - init_fidvid_bsp(bsp_apicid, sysinfo->nodes); - } else { - init_fidvid_stage2(bsp_apicid, 0); // BSP is node 0 - } - - post_code(0x3A); - - /* show final fid and vid */ - msr = rdmsr(MSR_COFVID_STS); - printk(BIOS_DEBUG, "End FIDVIDMSR 0xc0010071 0x%08x 0x%08x\n", msr.hi, msr.lo); -#endif - - init_timer(); // Need to use TMICT to synchronize FID/VID - - wants_reset = mcp55_early_setup_x(); - - /* Reset for HT, FIDVID, PLL and errata changes to take affect. */ - if (!warm_reset_detect(0)) { - printk(BIOS_INFO, "...WARM RESET...\n\n\n"); - soft_reset(); - die("After soft_reset - shouldn't see this message!!!\n"); - } - - if (wants_reset) - printk(BIOS_DEBUG, "mcp55_early_setup_x wanted additional reset!\n"); - - post_code(0x3B); - - /* It's the time to set ctrl in sysinfo now; */ - printk(BIOS_DEBUG, "fill_mem_ctrl()\n"); - fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr); - - post_code(0x3D); - -// printk(BIOS_DEBUG, "enable_smbus()\n"); -// enable_smbus(); /* enable in sio_setup */ - - post_code(0x40); - - raminit_amdmct(sysinfo); - - cbmem_initialize_empty(); - post_code(0x41); - - amdmct_cbmem_store_info(sysinfo); - -} - -/** - * BOOL AMD_CB_ManualBUIDSwapList(u8 Node, u8 Link, u8 **List) - * Description: - * This routine is called every time a non-coherent chain is processed. - * BUID assignment may be controlled explicitly on a non-coherent chain. Provide a - * swap list. The first part of the list controls the BUID assignment and the - * second part of the list provides the device to device linking. Device orientation - * can be detected automatically, or explicitly. See documentation for more details. - * - * Automatic non-coherent init assigns BUIDs starting at 1 and incrementing sequentially - * based on each device's unit count. - * - * Parameters: - * @param[in] node = The node on which this chain is located - * @param[in] link = The link on the host for this chain - * @param[out] List = supply a pointer to a list - */ -BOOL AMD_CB_ManualBUIDSwapList (u8 node, u8 link, const u8 **List) -{ - static const u8 swaplist[] = { 0xFF, CONFIG_HT_CHAIN_UNITID_BASE, CONFIG_HT_CHAIN_END_UNITID_BASE, 0xFF }; - /* If the BUID was adjusted in early_ht we need to do the manual override */ - if ((CONFIG_HT_CHAIN_UNITID_BASE != 0) && (CONFIG_HT_CHAIN_END_UNITID_BASE != 0)) { - printk(BIOS_DEBUG, "AMD_CB_ManualBUIDSwapList()\n"); - if ((node == 0) && (link == 0)) { /* BSP SB link */ - *List = swaplist; - return 1; - } - } - - return 0; -} diff --git a/src/mainboard/supermicro/h8scm_fam10/Kconfig b/src/mainboard/supermicro/h8scm_fam10/Kconfig deleted file mode 100644 index 2e6db0e1ed..0000000000 --- a/src/mainboard/supermicro/h8scm_fam10/Kconfig +++ /dev/null @@ -1,55 +0,0 @@ -if BOARD_SUPERMICRO_H8SCM_FAM10 - -config BOARD_SPECIFIC_OPTIONS - def_bool y - select CPU_AMD_SOCKET_C32_NON_AGESA - select DIMM_DDR3 - select DIMM_REGISTERED - select NORTHBRIDGE_AMD_AMDFAM10 - select SOUTHBRIDGE_AMD_SR5650 - select SOUTHBRIDGE_AMD_SB700 - select SOUTHBRIDGE_AMD_SUBTYPE_SP5100 - select SUPERIO_WINBOND_W83627HF - select SUPERIO_NUVOTON_WPCM450 - select HAVE_OPTION_TABLE - select HAVE_PIRQ_TABLE - select HAVE_MP_TABLE - select HAVE_ACPI_TABLES - select SB_HT_CHAIN_UNITID_OFFSET_ONLY - select LIFT_BSP_APIC_ID - select BOARD_ROMSIZE_KB_2048 - select ENABLE_APIC_EXT_ID - -config MAINBOARD_DIR - string - default supermicro/h8scm_fam10 - -config APIC_ID_OFFSET - hex - default 0x0 - -config MAINBOARD_PART_NUMBER - string - default "H8SCM (Fam10)" - -config MAX_CPUS - int - default 16 - -config MAX_PHYSICAL_CPUS - int - default 1 - -config HT_CHAIN_END_UNITID_BASE - hex - default 0x1 - -config HT_CHAIN_UNITID_BASE - hex - default 0x0 - -config IRQ_SLOT_COUNT - int - default 11 - -endif # BOARD_AMD_H8SCM_FAM10 diff --git a/src/mainboard/supermicro/h8scm_fam10/Kconfig.name b/src/mainboard/supermicro/h8scm_fam10/Kconfig.name deleted file mode 100644 index 03ff6bc5fc..0000000000 --- a/src/mainboard/supermicro/h8scm_fam10/Kconfig.name +++ /dev/null @@ -1,2 +0,0 @@ -config BOARD_SUPERMICRO_H8SCM_FAM10 - bool "H8SCM (Fam10)" diff --git a/src/mainboard/supermicro/h8scm_fam10/Makefile.inc b/src/mainboard/supermicro/h8scm_fam10/Makefile.inc deleted file mode 100644 index 91d4b39c32..0000000000 --- a/src/mainboard/supermicro/h8scm_fam10/Makefile.inc +++ /dev/null @@ -1,16 +0,0 @@ -# -# This file is part of the coreboot project. -# -# This program is free software; you can redistribute it and/or modify -# it under the terms of the GNU General Public License as published by -# the Free Software Foundation; version 2 of the License. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# - -romstage-y += resourcemap.c - -ramstage-y += get_bus_conf.c diff --git a/src/mainboard/supermicro/h8scm_fam10/acpi/cpstate.asl b/src/mainboard/supermicro/h8scm_fam10/acpi/cpstate.asl deleted file mode 100644 index acaa5bae32..0000000000 --- a/src/mainboard/supermicro/h8scm_fam10/acpi/cpstate.asl +++ /dev/null @@ -1,80 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2010 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -/* This file defines the processor and performance state capability - * for each core in the system. It is included into the DSDT for each - * core. It assumes that each core of the system has the same performance - * characteristics. -*/ -/* -#include -DefinitionBlock ("DSDT.AML", "DSDT", 0x01, OEM_ID, ACPI_TABLE_CREATOR, 0x00010001) - { - Scope (\_PR) { - Device (CPU0) { - Name (_HID, "ACPI0007") - Name (_UID, 0) - #include "cpstate.asl" - } - Device (CPU1) { - Name (_HID, "ACPI0007") - Name (_UID, 1) - #include "cpstate.asl" - } - Device (CPU2) { - Name (_HID, "ACPI0007") - Name (_UID, 2) - #include "cpstate.asl" - } - Device (CPU3) { - Name (_HID, "ACPI0007") - Name (_UID, 3) - #include "cpstate.asl" - } - } -*/ - /* P-state support: The maximum number of P-states supported by the */ - /* CPUs we'll use is 6. */ - /* Get from AMI BIOS. */ - Name(_PSS, Package(){ - Package () - { - 0x00000AF0, - 0x0000BF81, - 0x00000002, - 0x00000002, - 0x00000000, - 0x00000000 - }, - - Package () - { - 0x00000578, - 0x000076F2, - 0x00000002, - 0x00000002, - 0x00000001, - 0x00000001 - } - }) - - Name(_PCT, Package(){ - ResourceTemplate(){Register(FFixedHW, 0, 0, 0)}, - ResourceTemplate(){Register(FFixedHW, 0, 0, 0)} - }) - - Method(_PPC, 0){ - Return(0) - } diff --git a/src/mainboard/supermicro/h8scm_fam10/acpi/ide.asl b/src/mainboard/supermicro/h8scm_fam10/acpi/ide.asl deleted file mode 100644 index 5c155cf301..0000000000 --- a/src/mainboard/supermicro/h8scm_fam10/acpi/ide.asl +++ /dev/null @@ -1,240 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2010 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -/* -Scope (_SB) { - Device(PCI0) { - Device(IDEC) { - Name(_ADR, 0x00140001) - #include "ide.asl" - } - } -} -*/ - -/* Some timing tables */ -Name(UDTT, Package(){ /* Udma timing table */ - 120, 90, 60, 45, 30, 20, 15, 0 /* UDMA modes 0 -> 6 */ -}) - -Name(MDTT, Package(){ /* MWDma timing table */ - 480, 150, 120, 0 /* Legacy DMA modes 0 -> 2 */ -}) - -Name(POTT, Package(){ /* Pio timing table */ - 600, 390, 270, 180, 120, 0 /* PIO modes 0 -> 4 */ -}) - -/* Some timing register value tables */ -Name(MDRT, Package(){ /* MWDma timing register table */ - 0x77, 0x21, 0x20, 0xFF /* Legacy DMA modes 0 -> 2 */ -}) - -Name(PORT, Package(){ - 0x99, 0x47, 0x34, 0x22, 0x20, 0x99 /* PIO modes 0 -> 4 */ -}) - -OperationRegion(ICRG, PCI_Config, 0x40, 0x20) /* ide control registers */ - Field(ICRG, AnyAcc, NoLock, Preserve) -{ - PPTS, 8, /* Primary PIO Slave Timing */ - PPTM, 8, /* Primary PIO Master Timing */ - OFFSET(0x04), PMTS, 8, /* Primary MWDMA Slave Timing */ - PMTM, 8, /* Primary MWDMA Master Timing */ - OFFSET(0x08), PPCR, 8, /* Primary PIO Control */ - OFFSET(0x0A), PPMM, 4, /* Primary PIO master Mode */ - PPSM, 4, /* Primary PIO slave Mode */ - OFFSET(0x14), PDCR, 2, /* Primary UDMA Control */ - OFFSET(0x16), PDMM, 4, /* Primary UltraDMA Mode */ - PDSM, 4, /* Primary UltraDMA Mode */ -} - -Method(GTTM, 1) /* get total time*/ -{ - Store(And(Arg0, 0x0F), Local0) /* Recovery Width */ - Increment(Local0) - Store(ShiftRight(Arg0, 4), Local1) /* Command Width */ - Increment(Local1) - Return(Multiply(30, Add(Local0, Local1))) -} - -Device(PRID) -{ - Name (_ADR, Zero) - Method(_GTM, 0) - { - NAME(OTBF, Buffer(20) { /* out buffer */ - 0xFF, 0xFF, 0xFF, 0xFF, - 0xFF, 0xFF, 0xFF, 0xFF, - 0xFF, 0xFF, 0xFF, 0xFF, - 0xFF, 0xFF, 0xFF, 0xFF, 0x00, 0x00, 0x00, 0x00 - }) - - CreateDwordField(OTBF, 0, PSD0) /* PIO spd0 */ - CreateDwordField(OTBF, 4, DSD0) /* DMA spd0 */ - CreateDwordField(OTBF, 8, PSD1) /* PIO spd1 */ - CreateDwordField(OTBF, 12, DSD1) /* DMA spd1 */ - CreateDwordField(OTBF, 16, BFFG) /* buffer flags */ - - /* Just return if the channel is disabled */ - If(And(PPCR, 0x01)) { /* primary PIO control */ - Return(OTBF) - } - - /* Always tell them independent timing available and IOChannelReady used on both drives */ - Or(BFFG, 0x1A, BFFG) - - Store(GTTM(PPTM), PSD0) /* save total time of primary PIO master timming to PIO spd0 */ - Store(GTTM(PPTS), PSD1) /* save total time of primary PIO slave Timing to PIO spd1 */ - - If(And(PDCR, 0x01)) { /* It's under UDMA mode */ - Or(BFFG, 0x01, BFFG) - Store(DerefOf(Index(UDTT, PDMM)), DSD0) - } - Else { - Store(GTTM(PMTM), DSD0) /* Primary MWDMA Master Timing, DmaSpd0 */ - } - - If(And(PDCR, 0x02)) { /* It's under UDMA mode */ - Or(BFFG, 0x04, BFFG) - Store(DerefOf(Index(UDTT, PDSM)), DSD1) - } - Else { - Store(GTTM(PMTS), DSD1) /* Primary MWDMA Slave Timing, DmaSpd0 */ - } - - Return(OTBF) /* out buffer */ - } /* End Method(_GTM) */ - - Method(_STM, 3, NotSerialized) - { - NAME(INBF, Buffer(20) { /* in buffer */ - 0xFF, 0xFF, 0xFF, 0xFF, - 0xFF, 0xFF, 0xFF, 0xFF, - 0xFF, 0xFF, 0xFF, 0xFF, - 0xFF, 0xFF, 0xFF, 0xFF, 0x00, 0x00, 0x00, 0x00 - }) - - CreateDwordField(INBF, 0, PSD0) /* PIO spd0 */ - CreateDwordField(INBF, 4, DSD0) /* PIO spd0 */ - CreateDwordField(INBF, 8, PSD1) /* PIO spd1 */ - CreateDwordField(INBF, 12, DSD1) /* DMA spd1 */ - CreateDwordField(INBF, 16, BFFG) /*buffer flag */ - - Store(Match(POTT, MLE, PSD0, MTR, 0, 0), Local0) - Divide(Local0, 5, PPMM,) /* Primary PIO master Mode */ - Store(Match(POTT, MLE, PSD1, MTR, 0, 0), Local1) - Divide(Local1, 5, PPSM,) /* Primary PIO slave Mode */ - - Store(DerefOf(Index(PORT, Local0)), PPTM) /* Primary PIO Master Timing */ - Store(DerefOf(Index(PORT, Local1)), PPTS) /* Primary PIO Slave Timing */ - - If(And(BFFG, 0x01)) { /* Drive 0 is under UDMA mode */ - Store(Match(UDTT, MLE, DSD0, MTR, 0, 0), Local0) - Divide(Local0, 7, PDMM,) - Or(PDCR, 0x01, PDCR) - } - Else { - If(LNotEqual(DSD0, 0xFFFFFFFF)) { - Store(Match(MDTT, MLE, DSD0, MTR, 0, 0), Local0) - Store(DerefOf(Index(MDRT, Local0)), PMTM) - } - } - - If(And(BFFG, 0x04)) { /* Drive 1 is under UDMA mode */ - Store(Match(UDTT, MLE, DSD1, MTR, 0, 0), Local0) - Divide(Local0, 7, PDSM,) - Or(PDCR, 0x02, PDCR) - } - Else { - If(LNotEqual(DSD1, 0xFFFFFFFF)) { - Store(Match(MDTT, MLE, DSD1, MTR, 0, 0), Local0) - Store(DerefOf(Index(MDRT, Local0)), PMTS) - } - } - /* Return(INBF) */ - } /*End Method(_STM) */ - Device(MST) - { - Name(_ADR, 0) - Method(_GTF) { - Name(CMBF, Buffer(21) { - 0x03, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xEF, - 0x03, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xEF, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xF5 - }) - CreateByteField(CMBF, 1, POMD) - CreateByteField(CMBF, 8, DMMD) - CreateByteField(CMBF, 5, CMDA) - CreateByteField(CMBF, 12, CMDB) - CreateByteField(CMBF, 19, CMDC) - - Store(0xA0, CMDA) - Store(0xA0, CMDB) - Store(0xA0, CMDC) - - Or(PPMM, 0x08, POMD) - - If(And(PDCR, 0x01)) { - Or(PDMM, 0x40, DMMD) - } - Else { - Store(Match - (MDTT, MLE, GTTM(PMTM), - MTR, 0, 0), Local0) - If(LLess(Local0, 3)) { - Or(0x20, Local0, DMMD) - } - } - Return(CMBF) - } - } /* End Device(MST) */ - - Device(SLAV) - { - Name(_ADR, 1) - Method(_GTF) { - Name(CMBF, Buffer(21) { - 0x03, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xEF, - 0x03, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xEF, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xF5 - }) - CreateByteField(CMBF, 1, POMD) - CreateByteField(CMBF, 8, DMMD) - CreateByteField(CMBF, 5, CMDA) - CreateByteField(CMBF, 12, CMDB) - CreateByteField(CMBF, 19, CMDC) - - Store(0xB0, CMDA) - Store(0xB0, CMDB) - Store(0xB0, CMDC) - - Or(PPSM, 0x08, POMD) - - If(And(PDCR, 0x02)) { - Or(PDSM, 0x40, DMMD) - } - Else { - Store(Match - (MDTT, MLE, GTTM(PMTS), - MTR, 0, 0), Local0) - If(LLess(Local0, 3)) { - Or(0x20, Local0, DMMD) - } - } - Return(CMBF) - } - } /* End Device(SLAV) */ -} diff --git a/src/mainboard/supermicro/h8scm_fam10/acpi/routing.asl b/src/mainboard/supermicro/h8scm_fam10/acpi/routing.asl deleted file mode 100644 index a8c47fdb7c..0000000000 --- a/src/mainboard/supermicro/h8scm_fam10/acpi/routing.asl +++ /dev/null @@ -1,380 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2010 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -/* -#include -DefinitionBlock ("DSDT.AML", "DSDT", 0x01, OEM_ID, ACPI_TABLE_CREATOR, 0x00010001 - ) - { - #include "routing.asl" - } -*/ - -/* Routing is in System Bus scope */ -Scope(\_SB) { - Name(PR0, Package(){ - /* NB devices */ - /* Bus 0, Dev 0 - RS780 Host Controller */ - Package (0x04) { 0xFFFF, Zero, INTA, Zero }, - - /* Bus 0, Dev 1 - PCI Bridge for Internal Graphics */ - /* Bus 0, Dev 2 - PCIe Bridge for x8 PCIe Slot (GFX0) */ - Package(){0x0002FFFF, 0, INTC, 0 }, - Package(){0x0002FFFF, 1, INTD, 0 }, - Package(){0x0002FFFF, 2, INTA, 0 }, - Package(){0x0002FFFF, 3, INTB, 0 }, - /* Bus 0, Dev 3 - PCIe graphics port 1 bridge */ - Package(){0x0003FFFF, 0, INTD, 0 }, - Package(){0x0003FFFF, 1, INTA, 0 }, - Package(){0x0003FFFF, 2, INTB, 0 }, - Package(){0x0003FFFF, 3, INTC, 0 }, - /* Bus 0, Dev 4 - PCIe Bridge for Express Card Slot */ - Package(){0x0004FFFF, 0, INTA, 0 }, - Package(){0x0004FFFF, 1, INTB, 0 }, - Package(){0x0004FFFF, 2, INTC, 0 }, - Package(){0x0004FFFF, 3, INTD, 0 }, - /* Bus 0, Dev 5 - General purpose PCIe bridge 5 */ - Package(){0x0005FFFF, 0, INTB, 0 }, - Package(){0x0005FFFF, 1, INTC, 0 }, - Package(){0x0005FFFF, 2, INTD, 0 }, - Package(){0x0005FFFF, 3, INTA, 0 }, - /* Bus 0, Dev 6 - PCIe Bridge for Ethernet Chip */ - Package(){0x0006FFFF, 0, INTC, 0 }, - Package(){0x0006FFFF, 1, INTD, 0 }, - Package(){0x0006FFFF, 2, INTA, 0 }, - Package(){0x0006FFFF, 3, INTB, 0 }, - /* Bus 0, Dev 7 - PCIe Bridge for x1 PCIe Slot */ - Package(){0x0007FFFF, 0, INTD, 0 }, - Package(){0x0007FFFF, 1, INTA, 0 }, - Package(){0x0007FFFF, 2, INTB, 0 }, - Package(){0x0007FFFF, 3, INTC, 0 }, - /* Bus 0, Funct 8 - Southbridge port (normally hidden) */ - - /* Bus 0, Dev 9 - PCIe Bridge for network card */ - Package(){0x0009FFFF, 0, INTB, 0 }, - Package(){0x0009FFFF, 1, INTC, 0 }, - Package(){0x0009FFFF, 2, INTD, 0 }, - Package(){0x0009FFFF, 3, INTA, 0 }, - - /* Bus 0, Dev a - PCIe Bridge for network card */ - Package(){0x000AFFFF, 0, INTC, 0 }, - Package(){0x000AFFFF, 1, INTD, 0 }, - Package(){0x000AFFFF, 2, INTA, 0 }, - Package(){0x000AFFFF, 3, INTB, 0 }, - - /* Bus 0, Dev b - */ - Package(){0x000BFFFF, 0, INTD, 0 }, - Package(){0x000BFFFF, 1, INTA, 0 }, - Package(){0x000BFFFF, 2, INTB, 0 }, - Package(){0x000BFFFF, 3, INTC, 0 }, - - /* Bus 0, Dev c - */ - Package(){0x000CFFFF, 0, INTA, 0 }, - Package(){0x000CFFFF, 1, INTB, 0 }, - Package(){0x000CFFFF, 2, INTC, 0 }, - Package(){0x000CFFFF, 3, INTD, 0 }, - - /* Bus 0, Dev 17 - SATA controller */ - Package(){0x0011FFFF, 0, INTG, 0 }, - - /* Bus 0, Dev 19 - USB: OHCI, funct 0-4; EHCI, funct 5 */ - Package(){0x0012FFFF, 0, INTA, 0 }, - Package(){0x0012FFFF, 1, INTB, 0 }, - Package(){0x0012FFFF, 2, INTC, 0 }, - Package(){0x0012FFFF, 3, INTD, 0 }, - - Package(){0x0013FFFF, 0, INTC, 0 }, - Package(){0x0013FFFF, 1, INTD, 0 }, - Package(){0x0013FFFF, 2, INTA, 0 }, - Package(){0x0013FFFF, 3, INTB, 0 }, - - /* Bus 0, Dev 20 - F0:SMBus/ACPI,F1:IDE;F2:HDAudio;F3:LPC;F4:PCIBridge;F5:AC97 Audio;F6:AC97 Modem */ - Package(){0x0014FFFF, 0, INTA, 0 }, - Package(){0x0014FFFF, 1, INTB, 0 }, - Package(){0x0014FFFF, 2, INTC, 0 }, - Package(){0x0014FFFF, 3, INTD, 0 }, - }) - - Name(APR0, Package(){ - /* NB devices in APIC mode */ - /* Bus 0, Dev 0 - RS780 Host Controller */ - Package (0x04) { 0xFFFF, Zero, Zero, 16 }, - - /* Bus 0, Dev 1 - PCI Bridge for Internal Graphics */ - - /* Bus 0, Dev 2 - PCIe Bridge for x8 PCIe Slot (GFX0) */ - Package(){0x0002FFFF, 0, 0, 18 }, - Package(){0x0002FFFF, 1, 0, 19 }, - Package(){0x0002FFFF, 2, 0, 16 }, - Package(){0x0002FFFF, 3, 0, 17 }, - - /* Bus 0, Dev 3 - PCIe graphics port 1 bridge */ - Package(){0x0003FFFF, 0, 0, 19 }, - Package(){0x0003FFFF, 1, 0, 16 }, - Package(){0x0003FFFF, 2, 0, 17 }, - Package(){0x0003FFFF, 3, 0, 18 }, - - /* Bus 0, Dev 4 - PCIe Bridge for Express Card Slot */ - Package(){0x0004FFFF, 0, 0, 16 }, - Package(){0x0004FFFF, 1, 0, 17 }, - Package(){0x0004FFFF, 2, 0, 18 }, - Package(){0x0004FFFF, 3, 0, 19 }, - - /* Bus 0, Dev 5 - General purpose PCIe bridge 5 */ - Package(){0x0005FFFF, 0, 0, 17 }, - Package(){0x0005FFFF, 1, 0, 18 }, - Package(){0x0005FFFF, 2, 0, 19 }, - Package(){0x0005FFFF, 3, 0, 16 }, - - /* Bus 0, Dev 6 - General purpose PCIe bridge 6 */ - Package(){0x0006FFFF, 0, 0, 18 }, - Package(){0x0006FFFF, 1, 0, 19 }, - Package(){0x0006FFFF, 2, 0, 16 }, - Package(){0x0006FFFF, 3, 0, 17 }, - - /* Bus 0, Dev 7 - PCIe Bridge for network card */ - Package(){0x0007FFFF, 0, 0, 19 }, - Package(){0x0007FFFF, 1, 0, 16 }, - Package(){0x0007FFFF, 2, 0, 17 }, - Package(){0x0007FFFF, 3, 0, 18 }, - - /* Bus 0, Funct 8 - Southbridge port (normally hidden) */ - - /* Bus 0, Dev 9 - PCIe Bridge for network card */ - Package(){0x0009FFFF, 0, 0, 17 }, - Package(){0x0009FFFF, 1, 0, 18 }, - Package(){0x0009FFFF, 2, 0, 19 }, - Package(){0x0009FFFF, 3, 0, 16 }, - - /* Bus 0, Dev A - PCIe Bridge for network card */ - Package(){0x000AFFFF, 0, 0, 18 }, - Package(){0x000AFFFF, 1, 0, 19 }, - Package(){0x000AFFFF, 2, 0, 16 }, - Package(){0x000AFFFF, 3, 0, 17 }, - - /* Bus 0, Dev b - */ - Package(){0x000BFFFF, 0, 0, 19 }, - Package(){0x000BFFFF, 1, 0, 16 }, - Package(){0x000BFFFF, 2, 0, 17 }, - Package(){0x000BFFFF, 3, 0, 18 }, - - /* Bus 0, Dev c - */ - Package(){0x000CFFFF, 0, 0, 16 }, - Package(){0x000CFFFF, 1, 0, 17 }, - Package(){0x000CFFFF, 2, 0, 18 }, - Package(){0x000CFFFF, 3, 0, 19 }, - - /* Bus 0, Dev 17 - SATA controller */ - Package(){0x0011FFFF, 0, 0, 22 }, - - /* Bus 0, Dev 19 - USB: OHCI, funct 0-4; EHCI, funct 5 */ - Package(){0x0012FFFF, 0, 0, 16 }, - Package(){0x0012FFFF, 1, 0, 17 }, - Package(){0x0012FFFF, 2, 0, 18 }, - Package(){0x0012FFFF, 3, 0, 19 }, - - Package(){0x0013FFFF, 0, 0, 18 }, - Package(){0x0013FFFF, 1, 0, 19 }, - Package(){0x0013FFFF, 2, 0, 16 }, - Package(){0x0013FFFF, 3, 0, 17 }, - /* Package(){0x00130004, 2, 0, 18 }, */ - /* Package(){0x00130005, 3, 0, 19 }, */ - - /* Bus 0, Dev 20 - F0:SMBus/ACPI,F1:IDE;F2:HDAudio;F3:LPC;F4:PCIBridge;F5:AC97 Audio;F6:AC97 Modem */ - Package(){0x0014FFFF, 0, 0, 16 }, - Package(){0x0014FFFF, 1, 0, 17 }, - Package(){0x0014FFFF, 2, 0, 18 }, - Package(){0x0014FFFF, 3, 0, 19 }, - /* Package(){0x00140004, 2, 0, 18 }, */ - /* Package(){0x00140004, 3, 0, 19 }, */ - /* Package(){0x00140005, 1, 0, 17 }, */ - /* Package(){0x00140006, 1, 0, 17 }, */ - }) - - Name(PR1, Package(){ - /* Internal graphics - RS780 VGA, Bus1, Dev5 */ - Package(){0x0005FFFF, 0, INTA, 0 }, - Package(){0x0005FFFF, 1, INTB, 0 }, - Package(){0x0005FFFF, 2, INTC, 0 }, - Package(){0x0005FFFF, 3, INTD, 0 }, - }) - - Name(APR1, Package(){ - /* Internal graphics - RS780 VGA, Bus1, Dev5 */ - Package(){0x0005FFFF, 0, 0, 18 }, - Package(){0x0005FFFF, 1, 0, 19 }, - /* Package(){0x0005FFFF, 2, 0, 20 }, */ - /* Package(){0x0005FFFF, 3, 0, 17 }, */ - }) - - Name(PS2, Package(){ - /* The external GFX - Hooked to PCIe slot 2 */ - Package(){0x0000FFFF, 0, INTC, 0 }, - Package(){0x0000FFFF, 1, INTD, 0 }, - Package(){0x0000FFFF, 2, INTA, 0 }, - Package(){0x0000FFFF, 3, INTB, 0 }, - }) - - Name(APS2, Package(){ - /* The external GFX - Hooked to PCIe slot 2 */ - Package(){0x0000FFFF, 0, 0, 18 }, - Package(){0x0000FFFF, 1, 0, 19 }, - Package(){0x0000FFFF, 2, 0, 16 }, - Package(){0x0000FFFF, 3, 0, 17 }, - }) - - Name(PS4, Package(){ - /* PCIe slot - Hooked to PCIe slot 4 */ - Package(){0x0000FFFF, 0, INTA, 0 }, - Package(){0x0000FFFF, 1, INTB, 0 }, - Package(){0x0000FFFF, 2, INTC, 0 }, - Package(){0x0000FFFF, 3, INTD, 0 }, - }) - - Name(APS4, Package(){ - /* PCIe slot - Hooked to PCIe slot 4 */ - Package(){0x0000FFFF, 0, 0, 16 }, - Package(){0x0000FFFF, 1, 0, 17 }, - Package(){0x0000FFFF, 2, 0, 18 }, - Package(){0x0000FFFF, 3, 0, 19 }, - }) - - Name(PS5, Package(){ - /* PCIe slot - Hooked to PCIe slot 5 */ - Package(){0x0000FFFF, 0, INTB, 0 }, - Package(){0x0000FFFF, 1, INTC, 0 }, - Package(){0x0000FFFF, 2, INTD, 0 }, - Package(){0x0000FFFF, 3, INTA, 0 }, - }) - - Name(APS5, Package(){ - /* PCIe slot - Hooked to PCIe slot 5 */ - Package(){0x0000FFFF, 0, 0, 45 }, - Package(){0x0000FFFF, 1, 0, 46 }, - Package(){0x0000FFFF, 2, 0, 47 }, - Package(){0x0000FFFF, 3, 0, 44 }, - }) - - Name(PS6, Package(){ - /* PCIe slot - Hooked to PCIe slot 6 */ - Package(){0x0000FFFF, 0, INTC, 0 }, - Package(){0x0000FFFF, 1, INTD, 0 }, - Package(){0x0000FFFF, 2, INTA, 0 }, - Package(){0x0000FFFF, 3, INTB, 0 }, - }) - - Name(APS6, Package(){ - /* PCIe slot - Hooked to PCIe slot 6 */ - Package(){0x0000FFFF, 0, 0, 46 }, - Package(){0x0000FFFF, 1, 0, 47 }, - Package(){0x0000FFFF, 2, 0, 44 }, - Package(){0x0000FFFF, 3, 0, 45 }, - }) - - Name(PS7, Package(){ - /* The onboard Ethernet chip - Hooked to PCIe slot 7 */ - Package(){0x0000FFFF, 0, INTD, 0 }, - Package(){0x0000FFFF, 1, INTA, 0 }, - Package(){0x0000FFFF, 2, INTB, 0 }, - Package(){0x0000FFFF, 3, INTC, 0 }, - }) - - Name(APS7, Package(){ - /* The onboard Ethernet chip - Hooked to PCIe slot 7 */ - Package(){0x0000FFFF, 0, 0, 47 }, - Package(){0x0000FFFF, 1, 0, 44 }, - Package(){0x0000FFFF, 2, 0, 45 }, - Package(){0x0000FFFF, 3, 0, 46 }, - }) - - Name(PS9, Package(){ - /* PCIe slot - Hooked to PCIe slot 9 */ - Package(){0x0000FFFF, 0, INTB, 0 }, - Package(){0x0000FFFF, 1, INTC, 0 }, - Package(){0x0000FFFF, 2, INTD, 0 }, - Package(){0x0000FFFF, 3, INTA, 0 }, - }) - - Name(APS9, Package(){ - /* PCIe slot - Hooked to PCIe slot 9 */ - Package(){0x0000FFFF, 0, 0, 17 }, - Package(){0x0000FFFF, 1, 0, 18 }, - Package(){0x0000FFFF, 2, 0, 19 }, - Package(){0x0000FFFF, 3, 0, 16 }, - }) - Name(PSa, Package(){ - /* PCIe slot - Hooked to PCIe slot 10 */ - Package(){0x0000FFFF, 0, INTC, 0 }, - Package(){0x0000FFFF, 1, INTD, 0 }, - Package(){0x0000FFFF, 2, INTA, 0 }, - Package(){0x0000FFFF, 3, INTB, 0 }, - }) - - Name(APSa, Package(){ - /* PCIe slot - Hooked to PCIe slot 10 */ - Package(){0x0000FFFF, 0, 0, 18 }, - Package(){0x0000FFFF, 1, 0, 19 }, - Package(){0x0000FFFF, 2, 0, 16 }, - Package(){0x0000FFFF, 3, 0, 17 }, - }) - - Name(PSb, Package(){ - /* PCIe slot - Hooked to PCIe slot 11 */ - Package(){0x0000FFFF, 0, INTD, 0 }, - Package(){0x0000FFFF, 1, INTA, 0 }, - Package(){0x0000FFFF, 2, INTB, 0 }, - Package(){0x0000FFFF, 3, INTC, 0 }, - }) - - Name(APSb, Package(){ - /* PCIe slot - Hooked to PCIe slot 11 */ - Package(){0x0000FFFF, 0, 0, 32 }, - Package(){0x0000FFFF, 1, 0, 33 }, - Package(){0x0000FFFF, 2, 0, 34 }, - Package(){0x0000FFFF, 3, 0, 34 }, - }) - - Name(PSc, Package(){ - /* PCIe slot - Hooked to PCIe slot 12 */ - Package(){0x0000FFFF, 0, INTD, 0 }, - Package(){0x0000FFFF, 1, INTA, 0 }, - Package(){0x0000FFFF, 2, INTB, 0 }, - Package(){0x0000FFFF, 3, INTC, 0 }, - }) - - Name(APSc, Package(){ - /* PCIe slot - Hooked to PCIe slot 12 */ - Package(){0x0000FFFF, 0, 0, 36 }, - Package(){0x0000FFFF, 1, 0, 37 }, - Package(){0x0000FFFF, 2, 0, 38 }, - Package(){0x0000FFFF, 3, 0, 39 }, - }) - - Name(PCIB, Package(){ - /* PCI slots: slot 0, slot 1, slot 2 behind Dev14, Fun4. */ - Package(){0x0005FFFF, 0, 0, 0x14 }, - Package(){0x0005FFFF, 1, 0, 0x15 }, - Package(){0x0005FFFF, 2, 0, 0x16 }, - Package(){0x0005FFFF, 3, 0, 0x17 }, - Package(){0x0006FFFF, 0, 0, 0x15 }, - Package(){0x0006FFFF, 1, 0, 0x16 }, - Package(){0x0006FFFF, 2, 0, 0x17 }, - Package(){0x0006FFFF, 3, 0, 0x14 }, - Package(){0x0007FFFF, 0, 0, 0x16 }, - Package(){0x0007FFFF, 1, 0, 0x17 }, - Package(){0x0007FFFF, 2, 0, 0x14 }, - Package(){0x0007FFFF, 3, 0, 0x15 }, - }) -} diff --git a/src/mainboard/supermicro/h8scm_fam10/acpi/sata.asl b/src/mainboard/supermicro/h8scm_fam10/acpi/sata.asl deleted file mode 100644 index cb9b221ba3..0000000000 --- a/src/mainboard/supermicro/h8scm_fam10/acpi/sata.asl +++ /dev/null @@ -1,145 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2010 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -/* simple name description */ - -/* -Scope (_SB) { - Device(PCI0) { - Device(SATA) { - Name(_ADR, 0x00110000) - #include "sata.asl" - } - } -} -*/ - -Name(STTM, Buffer(20) { - 0x78, 0x00, 0x00, 0x00, 0x0f, 0x00, 0x00, 0x00, - 0x78, 0x00, 0x00, 0x00, 0x0f, 0x00, 0x00, 0x00, - 0x1f, 0x00, 0x00, 0x00 -}) - -/* Start by clearing the PhyRdyChg bits */ -Method(_INI) { - \_GPE._L1F() -} - -Device(PMRY) -{ - Name(_ADR, 0) - Method(_GTM, 0x0, NotSerialized) { - Return(STTM) - } - Method(_STM, 0x3, NotSerialized) {} - - Device(PMST) { - Name(_ADR, 0) - Method(_STA,0) { - if (LGreater(P0IS,0)) { - return (0x0F) /* sata is visible */ - } - else { - return (0x00) /* sata is missing */ - } - } - }/* end of PMST */ - - Device(PSLA) - { - Name(_ADR, 1) - Method(_STA,0) { - if (LGreater(P1IS,0)) { - return (0x0F) /* sata is visible */ - } - else { - return (0x00) /* sata is missing */ - } - } - } /* end of PSLA */ -} /* end of PMRY */ - - -Device(SEDY) -{ - Name(_ADR, 1) /* IDE Scondary Channel */ - Method(_GTM, 0x0, NotSerialized) { - Return(STTM) - } - Method(_STM, 0x3, NotSerialized) {} - - Device(SMST) - { - Name(_ADR, 0) - Method(_STA,0) { - if (LGreater(P2IS,0)) { - return (0x0F) /* sata is visible */ - } - else { - return (0x00) /* sata is missing */ - } - } - } /* end of SMST */ - - Device(SSLA) - { - Name(_ADR, 1) - Method(_STA,0) { - if (LGreater(P3IS,0)) { - return (0x0F) /* sata is visible */ - } - else { - return (0x00) /* sata is missing */ - } - } - } /* end of SSLA */ -} /* end of SEDY */ - -/* SATA Hot Plug Support */ -Scope(\_GPE) { - Method(_L1F,0x0,NotSerialized) { - if (\_SB.P0PR) { - if (LGreater(\_SB.P0IS,0)) { - sleep(32) - } - Notify(\_SB.PCI0.STCR.PMRY.PMST, 0x01) /* NOTIFY_DEVICE_CHECK */ - store(one, \_SB.P0PR) - } - - if (\_SB.P1PR) { - if (LGreater(\_SB.P1IS,0)) { - sleep(32) - } - Notify(\_SB.PCI0.STCR.PMRY.PSLA, 0x01) /* NOTIFY_DEVICE_CHECK */ - store(one, \_SB.P1PR) - } - - if (\_SB.P2PR) { - if (LGreater(\_SB.P2IS,0)) { - sleep(32) - } - Notify(\_SB.PCI0.STCR.SEDY.SMST, 0x01) /* NOTIFY_DEVICE_CHECK */ - store(one, \_SB.P2PR) - } - - if (\_SB.P3PR) { - if (LGreater(\_SB.P3IS,0)) { - sleep(32) - } - Notify(\_SB.PCI0.STCR.SEDY.SSLA, 0x01) /* NOTIFY_DEVICE_CHECK */ - store(one, \_SB.P3PR) - } - } -} diff --git a/src/mainboard/supermicro/h8scm_fam10/acpi/usb.asl b/src/mainboard/supermicro/h8scm_fam10/acpi/usb.asl deleted file mode 100644 index a3ccb97ff9..0000000000 --- a/src/mainboard/supermicro/h8scm_fam10/acpi/usb.asl +++ /dev/null @@ -1,158 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2010 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -/* simple name description */ -/* -#include -DefinitionBlock ("DSDT.AML", "DSDT", 0x01, OEM_ID, ACPI_TABLE_CREATOR, 0x00010001 - ) - { - #include "usb.asl" - } -*/ -Method(UCOC, 0) { - Sleep(20) - Store(0x13,CMTI) - Store(0,GPSL) -} - -/* USB Port 0 overcurrent uses Gpm 0 */ -If(LLessEqual(UOM0,9)) { - Scope (\_GPE) { - Method (_L13) { - UCOC() - if(LEqual(GPB0,PLC0)) { - Not(PLC0,PLC0) - Store(PLC0, \_SB.PT0D) - } - } - } -} - -/* USB Port 1 overcurrent uses Gpm 1 */ -If (LLessEqual(UOM1,9)) { - Scope (\_GPE) { - Method (_L14) { - UCOC() - if (LEqual(GPB1,PLC1)) { - Not(PLC1,PLC1) - Store(PLC1, \_SB.PT1D) - } - } - } -} - -/* USB Port 2 overcurrent uses Gpm 2 */ -If (LLessEqual(UOM2,9)) { - Scope (\_GPE) { - Method (_L15) { - UCOC() - if (LEqual(GPB2,PLC2)) { - Not(PLC2,PLC2) - Store(PLC2, \_SB.PT2D) - } - } - } -} - -/* USB Port 3 overcurrent uses Gpm 3 */ -If (LLessEqual(UOM3,9)) { - Scope (\_GPE) { - Method (_L16) { - UCOC() - if (LEqual(GPB3,PLC3)) { - Not(PLC3,PLC3) - Store(PLC3, \_SB.PT3D) - } - } - } -} - -/* USB Port 4 overcurrent uses Gpm 4 */ -If (LLessEqual(UOM4,9)) { - Scope (\_GPE) { - Method (_L19) { - UCOC() - if (LEqual(GPB4,PLC4)) { - Not(PLC4,PLC4) - Store(PLC4, \_SB.PT4D) - } - } - } -} - -/* USB Port 5 overcurrent uses Gpm 5 */ -If (LLessEqual(UOM5,9)) { - Scope (\_GPE) { - Method (_L1A) { - UCOC() - if (LEqual(GPB5,PLC5)) { - Not(PLC5,PLC5) - Store(PLC5, \_SB.PT5D) - } - } - } -} - -/* USB Port 6 overcurrent uses Gpm 6 */ -If (LLessEqual(UOM6,9)) { - Scope (\_GPE) { - /* Method (_L1C) { */ - Method (_L06) { - UCOC() - if (LEqual(GPB6,PLC6)) { - Not(PLC6,PLC6) - Store(PLC6, \_SB.PT6D) - } - } - } -} - -/* USB Port 7 overcurrent uses Gpm 7 */ -If (LLessEqual(UOM7,9)) { - Scope (\_GPE) { - /* Method (_L1D) { */ - Method (_L07) { - UCOC() - if (LEqual(GPB7,PLC7)) { - Not(PLC7,PLC7) - Store(PLC7, \_SB.PT7D) - } - } - } -} - -/* USB Port 8 overcurrent uses Gpm 8 */ -If (LLessEqual(UOM8,9)) { - Scope (\_GPE) { - Method (_L17) { - if (LEqual(G8IS,PLC8)) { - Not(PLC8,PLC8) - Store(PLC8, \_SB.PT8D) - } - } - } -} - -/* USB Port 9 overcurrent uses Gpm 9 */ -If (LLessEqual(UOM9,9)) { - Scope (\_GPE) { - Method (_L0E) { - if (LEqual(G9IS,0)) { - Store(1,\_SB.PT9D) - } - } - } -} diff --git a/src/mainboard/supermicro/h8scm_fam10/acpi_tables.c b/src/mainboard/supermicro/h8scm_fam10/acpi_tables.c deleted file mode 100644 index e9f181b836..0000000000 --- a/src/mainboard/supermicro/h8scm_fam10/acpi_tables.c +++ /dev/null @@ -1,97 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2010 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include -#include -#include - -#include "mb_sysconf.h" - -unsigned long acpi_fill_madt(unsigned long current) -{ - struct device *dev; - u32 dword; - u32 gsi_base = 0; - /* create all subtables for processors */ - current = acpi_create_madt_lapics(current); - - /* Write SB700 IOAPIC, only one */ - current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, 2, - IO_APIC_ADDR, gsi_base); - /* IOAPIC on rs5690 */ - gsi_base += 24; /* SB700 has 24 IOAPIC entries. */ - dev = pcidev_on_root(0, 0); - if (dev) { - pci_write_config32(dev, 0xF8, 0x1); - dword = pci_read_config32(dev, 0xFC) & 0xfffffff0; - current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, 2+1, - dword, gsi_base); - } - - - current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) - current, 0, 0, 2, 0); - current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) - current, 0, 9, 9, 0xF); - /* 0: mean bus 0--->ISA */ - /* 0: PIC 0 */ - /* 2: APIC 2 */ - /* 5 mean: 0101 --> Edge-triggered, Active high */ - - /* create all subtables for processors */ - /* current = acpi_create_madt_lapic_nmis(current, 5, 1); */ - /* 1: LINT1 connect to NMI */ - - return current; -} - -unsigned long acpi_fill_ivrs_ioapic(acpi_ivrs_t *ivrs, unsigned long current) -{ - uint8_t *p; - - uint32_t apicid_sp5100; - uint32_t apicid_sr5650; - - apicid_sp5100 = 0x20; - apicid_sr5650 = apicid_sp5100 + 1; - - /* Describe NB IOAPIC */ - p = (uint8_t *)current; - p[0] = 0x48; /* Entry type */ - p[1] = 0; /* Device */ - p[2] = 0; /* Bus */ - p[3] = 0x0; /* Data */ - p[4] = apicid_sr5650; /* IOAPIC ID */ - p[5] = 0x1; /* Device 0 Function 1 */ - p[6] = 0x0; /* Northbridge bus */ - p[7] = 0x1; /* Variety */ - current += 8; - - /* Describe SB IOAPIC */ - p = (uint8_t *)current; - p[0] = 0x48; /* Entry type */ - p[1] = 0; /* Device */ - p[2] = 0; /* Bus */ - p[3] = 0xd7; /* Data */ - p[4] = apicid_sp5100; /* IOAPIC ID */ - p[5] = 0x14 << 3; /* Device 0x14 Function 0 */ - p[6] = 0x0; /* Southbridge bus */ - p[7] = 0x1; /* Variety */ - current += 8; - - return current; -} diff --git a/src/mainboard/supermicro/h8scm_fam10/board_info.txt b/src/mainboard/supermicro/h8scm_fam10/board_info.txt deleted file mode 100644 index 3d902b640a..0000000000 --- a/src/mainboard/supermicro/h8scm_fam10/board_info.txt +++ /dev/null @@ -1 +0,0 @@ -Category: server diff --git a/src/mainboard/supermicro/h8scm_fam10/cmos.layout b/src/mainboard/supermicro/h8scm_fam10/cmos.layout deleted file mode 100644 index 6c3d3f6c9e..0000000000 --- a/src/mainboard/supermicro/h8scm_fam10/cmos.layout +++ /dev/null @@ -1,52 +0,0 @@ -entries - -0 384 r 0 reserved_memory -384 1 e 4 boot_option -388 4 h 0 reboot_counter -#392 3 r 0 unused -395 1 e 1 hw_scrubber -396 1 e 1 interleave_chip_selects -397 2 e 8 max_mem_clock -399 1 e 2 multi_core -400 1 e 1 power_on_after_fail -412 4 e 6 debug_level -440 4 e 9 slow_cpu -444 1 e 1 nmi -445 1 e 1 gart -456 1 e 1 ECC_memory -728 256 h 0 user_data -984 16 h 0 check_sum -# Reserve the extended AMD configuration registers -1000 24 r 0 amd_reserved - - - -enumerations - -#ID value text -1 0 Disable -1 1 Enable -2 0 Enable -2 1 Disable -4 0 Fallback -4 1 Normal -6 5 Notice -6 6 Info -6 7 Debug -6 8 Spew -8 0 400Mhz -8 1 333Mhz -8 2 266Mhz -8 3 200Mhz -9 0 off -9 1 87.5% -9 2 75.0% -9 3 62.5% -9 4 50.0% -9 5 37.5% -9 6 25.0% -9 7 12.5% - -checksums - -checksum 392 983 984 diff --git a/src/mainboard/supermicro/h8scm_fam10/devicetree.cb b/src/mainboard/supermicro/h8scm_fam10/devicetree.cb deleted file mode 100644 index 2799a26751..0000000000 --- a/src/mainboard/supermicro/h8scm_fam10/devicetree.cb +++ /dev/null @@ -1,123 +0,0 @@ -# GPP1 (dev2,3) --> slot 7 -# GPP2 (dev12) --> slot 6 -# GPP3A (dev9,A) --> Lan1, Lan2 - -# sample config for supermicro/h8scm_fam10 -chip northbridge/amd/amdfam10/root_complex - device cpu_cluster 0 on - chip cpu/amd/socket_C32 #L1 and DDR3 - device lapic 0 on end - end - end - device domain 0 on - subsystemid 0x15d9 0x1511 inherit - chip northbridge/amd/amdfam10 - ##device pci 18.0 on end - ##device pci 18.0 on end - device pci 18.0 on # northbridge - chip southbridge/amd/sr5650 - device pci 0.0 on end # HT 0x9600 - device pci 0.1 on end # CLKCONFIG - device pci 2.0 on end # PCIE P2P bridge (external graphics) 0x9603 - device pci 3.0 off end # PCIE P2P bridge 0x960b - device pci 4.0 off end # PCIE P2P bridge 0x9604 - device pci 5.0 off end # PCIE P2P bridge 0x9605 - device pci 6.0 on end # PCIE P2P bridge 0x9606 - device pci 7.0 on end # PCIE P2P bridge 0x9607 - device pci 8.0 on end # NB/SB Link P2P bridge - device pci 9.0 on end # - device pci a.0 on end # - device pci b.0 on end # - device pci c.0 on end # - device pci d.0 on end # - register "gpp1_configuration" = "0" # Configuration 16:0 default - register "gpp2_configuration" = "1" # Configuration 8:8 - #register "gpp3a_configuration" = "2" # Configuration 4:1:1:0:0:0 - register "gpp3a_configuration" = "11" # Configuration 1:1:1:1:1:1 - register "port_enable" = "0x1ffc" - end - chip southbridge/amd/sb700 # (model:sp5100) it is under NB/SB Link, but on the same pri bus - device pci 11.0 on end # SATA - device pci 12.0 on end # USB - device pci 12.1 on end # USB - device pci 12.2 on end # USB - device pci 13.0 on end # USB - device pci 13.1 on end # USB - device pci 13.2 on end # USB - device pci 14.0 on end # SM - device pci 14.1 on end # IDE 0x439c - device pci 14.2 off end # HDA 0x4383, h8scm doesnt have codec. - device pci 14.3 on # LPC 0x439d - chip superio/winbond/w83627hf - device pnp 2e.0 off # Floppy - io 0x60 = 0x3f0 - irq 0x70 = 6 - drq 0x74 = 2 - end - device pnp 2e.1 off # Parallel Port - io 0x60 = 0x378 - irq 0x70 = 7 - end - device pnp 2e.2 off # Com1 - io 0x60 = 0x3f8 - irq 0x70 = 4 - end - device pnp 2e.3 off # Com2 - io 0x60 = 0x2f8 - irq 0x70 = 3 - end - device pnp 2e.5 on # Keyboard - io 0x60 = 0x60 - io 0x62 = 0x64 - irq 0x70 = 1 - irq 0x72 = 12 - end - device pnp 2e.6 off # SFI - io 0x62 = 0x100 - end - device pnp 2e.7 off # GPIO_GAME_MIDI - io 0x60 = 0x220 - io 0x62 = 0x300 - irq 0x70 = 9 - end - device pnp 2e.8 off end # WDTO_PLED - device pnp 2e.9 off end # GPIO_SUSLED - device pnp 2e.a off end # ACPI - device pnp 2e.b on # HW Monitor - io 0x60 = 0x290 - irq 0x70 = 5 - end - end #superio/winbond/w83627hf - end #LPC - device pci 14.4 on end # PCI 0x4384 - device pci 14.5 on end # USB 2 - register "boot_switch_sata_ide" = "0" # 0: boot from SATA. 1: IDE - end #southbridge/amd/sb700 - end # device pci 18.0 - device pci 18.1 on end - device pci 18.2 on end - device pci 18.3 on end - device pci 18.4 on end - device pci 19.0 on end - device pci 19.1 on end - device pci 19.2 on end - device pci 19.3 on end - device pci 19.4 on end - end - end #domain - #for node 32 to node 63 -# device domain 0 on -# chip northbridge/amd/amdfam10 -# device pci 00.0 on end# northbridge -# device pci 00.0 on end -# device pci 00.0 on end -# device pci 00.0 on end -# device pci 00.1 on end -# device pci 00.2 on end -# device pci 00.3 on end -# device pci 00.4 on end -# device pci 00.5 on end -# end -# end #domain - -end diff --git a/src/mainboard/supermicro/h8scm_fam10/dsdt.asl b/src/mainboard/supermicro/h8scm_fam10/dsdt.asl deleted file mode 100644 index 4dfa9995b9..0000000000 --- a/src/mainboard/supermicro/h8scm_fam10/dsdt.asl +++ /dev/null @@ -1,1766 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2009 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -/* DefinitionBlock Statement */ -#include -DefinitionBlock ( - "DSDT.AML", /* Output filename */ - "DSDT", /* Signature */ - 0x02, /* DSDT Revision, needs to be 2 for 64bit */ - OEM_ID, - ACPI_TABLE_CREATOR, - 0x00010001 /* OEM Revision */ - ) -{ /* Start of ASL file */ - /* #include */ /* Include global debug methods if needed */ - - /* Data to be patched by the BIOS during POST */ - /* FIXME the patching is not done yet! */ - /* Memory related values */ - Name(LOMH, 0x0) /* Start of unused memory in C0000-E0000 range */ - Name(PBAD, 0x0) /* Address of BIOS area (If TOM2 != 0, Addr >> 16) */ - Name(PBLN, 0x0) /* Length of BIOS area */ - - Name(PCBA, 0xE0000000) /* Base address of PCIe config space */ - Name(HPBA, 0xFED00000) /* Base address of HPET table */ - - /* USB overcurrent mapping pins. */ - Name(UOM0, 0) - Name(UOM1, 2) - Name(UOM2, 0) - Name(UOM3, 7) - Name(UOM4, 2) - Name(UOM5, 2) - Name(UOM6, 6) - Name(UOM7, 2) - Name(UOM8, 6) - Name(UOM9, 6) - - /* Some global data */ - Name(OSVR, 3) /* Assume nothing. WinXp = 1, Vista = 2, Linux = 3, WinCE = 4 */ - Name(OSV, Ones) /* Assume nothing */ - Name(PMOD, One) /* Assume APIC */ - - /* - * Processor Object - * - */ - Scope (\_PR) { /* define processor scope */ - Device (CPU0) { - Name (_HID, "ACPI0007") - Name (_UID, 0) - #include "acpi/cpstate.asl" - } - Device (CPU1) { - Name (_HID, "ACPI0007") - Name (_UID, 1) - #include "acpi/cpstate.asl" - } - Device (CPU2) { - Name (_HID, "ACPI0007") - Name (_UID, 2) - #include "acpi/cpstate.asl" - } - Device (CPU3) { - Name (_HID, "ACPI0007") - Name (_UID, 3) - #include "acpi/cpstate.asl" - } - Device (CPU4) { - Name (_HID, "ACPI0007") - Name (_UID, 4) - #include "acpi/cpstate.asl" - } - Device (CPU5) { - Name (_HID, "ACPI0007") - Name (_UID, 5) - #include "acpi/cpstate.asl" - } - } /* End _PR scope */ - - /* PIC IRQ mapping registers, C00h-C01h */ - OperationRegion(PRQM, SystemIO, 0x00000C00, 0x00000002) - Field(PRQM, ByteAcc, NoLock, Preserve) { - PRQI, 0x00000008, - PRQD, 0x00000008, /* Offset: 1h */ - } - IndexField(PRQI, PRQD, ByteAcc, NoLock, Preserve) { - PINA, 0x00000008, /* Index 0 */ - PINB, 0x00000008, /* Index 1 */ - PINC, 0x00000008, /* Index 2 */ - PIND, 0x00000008, /* Index 3 */ - AINT, 0x00000008, /* Index 4 */ - SINT, 0x00000008, /* Index 5 */ - , 0x00000008, /* Index 6 */ - AAUD, 0x00000008, /* Index 7 */ - AMOD, 0x00000008, /* Index 8 */ - PINE, 0x00000008, /* Index 9 */ - PINF, 0x00000008, /* Index A */ - PING, 0x00000008, /* Index B */ - PINH, 0x00000008, /* Index C */ - } - - /* PCI Error control register */ - OperationRegion(PERC, SystemIO, 0x00000C14, 0x00000001) - Field(PERC, ByteAcc, NoLock, Preserve) { - SENS, 0x00000001, - PENS, 0x00000001, - SENE, 0x00000001, - PENE, 0x00000001, - } - - /* Client Management index/data registers */ - OperationRegion(CMT, SystemIO, 0x00000C50, 0x00000002) - Field(CMT, ByteAcc, NoLock, Preserve) { - CMTI, 8, - /* Client Management Data register */ - G64E, 1, - G64O, 1, - G32O, 2, - , 2, - GPSL, 2, - } - - /* GPM Port register */ - OperationRegion(GPT, SystemIO, 0x00000C52, 0x00000001) - Field(GPT, ByteAcc, NoLock, Preserve) { - GPB0,1, - GPB1,1, - GPB2,1, - GPB3,1, - GPB4,1, - GPB5,1, - GPB6,1, - GPB7,1, - } - - /* Flash ROM program enable register */ - OperationRegion(FRE, SystemIO, 0x00000C6F, 0x00000001) - Field(FRE, ByteAcc, NoLock, Preserve) { - , 0x00000006, - FLRE, 0x00000001, - } - - /* PM2 index/data registers */ - OperationRegion(PM2R, SystemIO, 0x00000CD0, 0x00000002) - Field(PM2R, ByteAcc, NoLock, Preserve) { - PM2I, 0x00000008, - PM2D, 0x00000008, - } - - /* Power Management I/O registers */ - OperationRegion(PIOR, SystemIO, 0x00000CD6, 0x00000002) - Field(PIOR, ByteAcc, NoLock, Preserve) { - PIOI, 0x00000008, - PIOD, 0x00000008, - } - IndexField (PIOI, PIOD, ByteAcc, NoLock, Preserve) { - Offset(0x00), /* MiscControl */ - , 1, - T1EE, 1, - T2EE, 1, - Offset(0x01), /* MiscStatus */ - , 1, - T1E, 1, - T2E, 1, - Offset(0x04), /* SmiWakeUpEventEnable3 */ - , 7, - SSEN, 1, - Offset(0x07), /* SmiWakeUpEventStatus3 */ - , 7, - CSSM, 1, - Offset(0x10), /* AcpiEnable */ - , 6, - PWDE, 1, - Offset(0x1C), /* ProgramIoEnable */ - , 3, - MKME, 1, - IO3E, 1, - IO2E, 1, - IO1E, 1, - IO0E, 1, - Offset(0x1D), /* IOMonitorStatus */ - , 3, - MKMS, 1, - IO3S, 1, - IO2S, 1, - IO1S, 1, - IO0S,1, - Offset(0x20), /* AcpiPmEvtBlk */ - APEB, 16, - Offset(0x36), /* GEvtLevelConfig */ - , 6, - ELC6, 1, - ELC7, 1, - Offset(0x37), /* GPMLevelConfig0 */ - , 3, - PLC0, 1, - PLC1, 1, - PLC2, 1, - PLC3, 1, - PLC8, 1, - Offset(0x38), /* GPMLevelConfig1 */ - , 1, - PLC4, 1, - PLC5, 1, - , 1, - PLC6, 1, - PLC7, 1, - Offset(0x3B), /* PMEStatus1 */ - GP0S, 1, - GM4S, 1, - GM5S, 1, - APS, 1, - GM6S, 1, - GM7S, 1, - GP2S, 1, - STSS, 1, - Offset(0x55), /* SoftPciRst */ - SPRE, 1, - , 1, - , 1, - PNAT, 1, - PWMK, 1, - PWNS, 1, - - /* Offset(0x61), */ /* Options_1 */ - /* ,7, */ - /* R617,1, */ - - Offset(0x65), /* UsbPMControl */ - , 4, - URRE, 1, - Offset(0x68), /* MiscEnable68 */ - , 3, - TMTE, 1, - , 1, - Offset(0x92), /* GEVENTIN */ - , 7, - E7IS, 1, - Offset(0x96), /* GPM98IN */ - G8IS, 1, - G9IS, 1, - Offset(0x9A), /* EnhanceControl */ - ,7, - HPDE, 1, - Offset(0xA8), /* PIO7654Enable */ - IO4E, 1, - IO5E, 1, - IO6E, 1, - IO7E, 1, - Offset(0xA9), /* PIO7654Status */ - IO4S, 1, - IO5S, 1, - IO6S, 1, - IO7S, 1, - } - - /* PM1 Event Block - * First word is PM1_Status, Second word is PM1_Enable - */ - OperationRegion(P1EB, SystemIO, APEB, 0x04) - Field(P1EB, ByteAcc, NoLock, Preserve) { - TMST, 1, - , 3, - BMST, 1, - GBST, 1, - Offset(0x01), - PBST, 1, - , 1, - RTST, 1, - , 3, - PWST, 1, - SPWS, 1, - Offset(0x02), - TMEN, 1, - , 4, - GBEN, 1, - Offset(0x03), - PBEN, 1, - , 1, - RTEN, 1, - , 3, - PWDA, 1, - } - - Scope(\_SB) { - /* PCIe Configuration Space for 16 busses */ - OperationRegion(PCFG, SystemMemory, PCBA, 0x01000000) /* Each bus consumes 1MB */ - Field(PCFG, ByteAcc, NoLock, Preserve) { - /* Byte offsets are computed using the following technique: - * ((bus number + 1) * ((device number * 8) * 4096)) + register offset - * The 8 comes from 8 functions per device, and 4096 bytes per function config space - */ - Offset(0x00088024), /* Byte offset to SATA register 24h - Bus 0, Device 17, Function 0 */ - STB5, 32, - Offset(0x00098042), /* Byte offset to OHCI0 register 42h - Bus 0, Device 19, Function 0 */ - PT0D, 1, - PT1D, 1, - PT2D, 1, - PT3D, 1, - PT4D, 1, - PT5D, 1, - PT6D, 1, - PT7D, 1, - PT8D, 1, - PT9D, 1, - Offset(0x000A0004), /* Byte offset to SMBUS register 4h - Bus 0, Device 20, Function 0 */ - SBIE, 1, - SBME, 1, - Offset(0x000A0008), /* Byte offset to SMBUS register 8h - Bus 0, Device 20, Function 0 */ - SBRI, 8, - Offset(0x000A0014), /* Byte offset to SMBUS register 14h - Bus 0, Device 20, Function 0 */ - SBB1, 32, - Offset(0x000A0078), /* Byte offset to SMBUS register 78h - Bus 0, Device 20, Function 0 */ - ,14, - P92E, 1, /* Port92 decode enable */ - } - - OperationRegion(SB5, SystemMemory, STB5, 0x1000) - Field(SB5, AnyAcc, NoLock, Preserve){ - /* Port 0 */ - Offset(0x120), /* Port 0 Task file status */ - P0ER, 1, - , 2, - P0DQ, 1, - , 3, - P0BY, 1, - Offset(0x128), /* Port 0 Serial ATA status */ - P0DD, 4, - , 4, - P0IS, 4, - Offset(0x12C), /* Port 0 Serial ATA control */ - P0DI, 4, - Offset(0x130), /* Port 0 Serial ATA error */ - , 16, - P0PR, 1, - - /* Port 1 */ - offset(0x1A0), /* Port 1 Task file status */ - P1ER, 1, - , 2, - P1DQ, 1, - , 3, - P1BY, 1, - Offset(0x1A8), /* Port 1 Serial ATA status */ - P1DD, 4, - , 4, - P1IS, 4, - Offset(0x1AC), /* Port 1 Serial ATA control */ - P1DI, 4, - Offset(0x1B0), /* Port 1 Serial ATA error */ - , 16, - P1PR, 1, - - /* Port 2 */ - Offset(0x220), /* Port 2 Task file status */ - P2ER, 1, - , 2, - P2DQ, 1, - , 3, - P2BY, 1, - Offset(0x228), /* Port 2 Serial ATA status */ - P2DD, 4, - , 4, - P2IS, 4, - Offset(0x22C), /* Port 2 Serial ATA control */ - P2DI, 4, - Offset(0x230), /* Port 2 Serial ATA error */ - , 16, - P2PR, 1, - - /* Port 3 */ - Offset(0x2A0), /* Port 3 Task file status */ - P3ER, 1, - , 2, - P3DQ, 1, - , 3, - P3BY, 1, - Offset(0x2A8), /* Port 3 Serial ATA status */ - P3DD, 4, - , 4, - P3IS, 4, - Offset(0x2AC), /* Port 3 Serial ATA control */ - P3DI, 4, - Offset(0x2B0), /* Port 3 Serial ATA error */ - , 16, - P3PR, 1, - } - } - - - #include "acpi/routing.asl" - - Scope(\_SB) { - - Method(OSFL, 0){ - - if(LNotEqual(OSVR, Ones)) {Return(OSVR)} /* OS version was already detected */ - - if(CondRefOf(\_OSI)) - { - Store(1, OSVR) /* Assume some form of XP */ - if (\_OSI("Windows 2006")) /* Vista */ - { - Store(2, OSVR) - } - } else { - If(WCMP(\_OS,"Linux")) { - Store(3, OSVR) /* Linux */ - } Else { - Store(4, OSVR) /* Gotta be WinCE */ - } - } - Return(OSVR) - } - - Method(_PIC, 0x01, NotSerialized) - { - If (Arg0) - { - \_SB.CIRQ() - } - Store(Arg0, PMOD) - } - Method(CIRQ, 0x00, NotSerialized){ - Store(0, PINA) - Store(0, PINB) - Store(0, PINC) - Store(0, PIND) - Store(0, PINE) - Store(0, PINF) - Store(0, PING) - Store(0, PINH) - } - - Name(IRQB, ResourceTemplate(){ - IRQ(Level,ActiveLow,Shared){15} - }) - - Name(IRQP, ResourceTemplate(){ - IRQ(Level,ActiveLow,Exclusive){3, 4, 5, 7, 10, 11, 12, 15} - }) - - Name(PITF, ResourceTemplate(){ - IRQ(Level,ActiveLow,Exclusive){9} - }) - - Device(INTA) { - Name(_HID, EISAID("PNP0C0F")) - Name(_UID, 1) - - Method(_STA, 0) { - if (PINA) { - Return(0x0B) /* sata is invisible */ - } else { - Return(0x09) /* sata is disabled */ - } - } /* End Method(_SB.INTA._STA) */ - - Method(_DIS ,0) { - /* DBGO("\\_SB\\LNKA\\_DIS\n") */ - Store(0, PINA) - } /* End Method(_SB.INTA._DIS) */ - - Method(_PRS ,0) { - /* DBGO("\\_SB\\LNKA\\_PRS\n") */ - Return(IRQP) - } /* Method(_SB.INTA._PRS) */ - - Method(_CRS ,0) { - /* DBGO("\\_SB\\LNKA\\_CRS\n") */ - CreateWordField(IRQB, 0x1, IRQN) - ShiftLeft(1, PINA, IRQN) - Return(IRQB) - } /* Method(_SB.INTA._CRS) */ - - Method(_SRS, 1) { - /* DBGO("\\_SB\\LNKA\\_CRS\n") */ - CreateWordField(ARG0, 1, IRQM) - - /* Use lowest available IRQ */ - FindSetRightBit(IRQM, Local0) - if (Local0) { - Decrement(Local0) - } - Store(Local0, PINA) - } /* End Method(_SB.INTA._SRS) */ - } /* End Device(INTA) */ - - Device(INTB) { - Name(_HID, EISAID("PNP0C0F")) - Name(_UID, 2) - - Method(_STA, 0) { - if (PINB) { - Return(0x0B) /* sata is invisible */ - } else { - Return(0x09) /* sata is disabled */ - } - } /* End Method(_SB.INTB._STA) */ - - Method(_DIS ,0) { - /* DBGO("\\_SB\\LNKB\\_DIS\n") */ - Store(0, PINB) - } /* End Method(_SB.INTB._DIS) */ - - Method(_PRS ,0) { - /* DBGO("\\_SB\\LNKB\\_PRS\n") */ - Return(IRQP) - } /* Method(_SB.INTB._PRS) */ - - Method(_CRS ,0) { - /* DBGO("\\_SB\\LNKB\\_CRS\n") */ - CreateWordField(IRQB, 0x1, IRQN) - ShiftLeft(1, PINB, IRQN) - Return(IRQB) - } /* Method(_SB.INTB._CRS) */ - - Method(_SRS, 1) { - /* DBGO("\\_SB\\LNKB\\_CRS\n") */ - CreateWordField(ARG0, 1, IRQM) - - /* Use lowest available IRQ */ - FindSetRightBit(IRQM, Local0) - if (Local0) { - Decrement(Local0) - } - Store(Local0, PINB) - } /* End Method(_SB.INTB._SRS) */ - } /* End Device(INTB) */ - - Device(INTC) { - Name(_HID, EISAID("PNP0C0F")) - Name(_UID, 3) - - Method(_STA, 0) { - if (PINC) { - Return(0x0B) /* sata is invisible */ - } else { - Return(0x09) /* sata is disabled */ - } - } /* End Method(_SB.INTC._STA) */ - - Method(_DIS ,0) { - /* DBGO("\\_SB\\LNKC\\_DIS\n") */ - Store(0, PINC) - } /* End Method(_SB.INTC._DIS) */ - - Method(_PRS ,0) { - /* DBGO("\\_SB\\LNKC\\_PRS\n") */ - Return(IRQP) - } /* Method(_SB.INTC._PRS) */ - - Method(_CRS ,0) { - /* DBGO("\\_SB\\LNKC\\_CRS\n") */ - CreateWordField(IRQB, 0x1, IRQN) - ShiftLeft(1, PINC, IRQN) - Return(IRQB) - } /* Method(_SB.INTC._CRS) */ - - Method(_SRS, 1) { - /* DBGO("\\_SB\\LNKC\\_CRS\n") */ - CreateWordField(ARG0, 1, IRQM) - - /* Use lowest available IRQ */ - FindSetRightBit(IRQM, Local0) - if (Local0) { - Decrement(Local0) - } - Store(Local0, PINC) - } /* End Method(_SB.INTC._SRS) */ - } /* End Device(INTC) */ - - Device(INTD) { - Name(_HID, EISAID("PNP0C0F")) - Name(_UID, 4) - - Method(_STA, 0) { - if (PIND) { - Return(0x0B) /* sata is invisible */ - } else { - Return(0x09) /* sata is disabled */ - } - } /* End Method(_SB.INTD._STA) */ - - Method(_DIS ,0) { - /* DBGO("\\_SB\\LNKD\\_DIS\n") */ - Store(0, PIND) - } /* End Method(_SB.INTD._DIS) */ - - Method(_PRS ,0) { - /* DBGO("\\_SB\\LNKD\\_PRS\n") */ - Return(IRQP) - } /* Method(_SB.INTD._PRS) */ - - Method(_CRS ,0) { - /* DBGO("\\_SB\\LNKD\\_CRS\n") */ - CreateWordField(IRQB, 0x1, IRQN) - ShiftLeft(1, PIND, IRQN) - Return(IRQB) - } /* Method(_SB.INTD._CRS) */ - - Method(_SRS, 1) { - /* DBGO("\\_SB\\LNKD\\_CRS\n") */ - CreateWordField(ARG0, 1, IRQM) - - /* Use lowest available IRQ */ - FindSetRightBit(IRQM, Local0) - if (Local0) { - Decrement(Local0) - } - Store(Local0, PIND) - } /* End Method(_SB.INTD._SRS) */ - } /* End Device(INTD) */ - - Device(INTE) { - Name(_HID, EISAID("PNP0C0F")) - Name(_UID, 5) - - Method(_STA, 0) { - if (PINE) { - Return(0x0B) /* sata is invisible */ - } else { - Return(0x09) /* sata is disabled */ - } - } /* End Method(_SB.INTE._STA) */ - - Method(_DIS ,0) { - /* DBGO("\\_SB\\LNKE\\_DIS\n") */ - Store(0, PINE) - } /* End Method(_SB.INTE._DIS) */ - - Method(_PRS ,0) { - /* DBGO("\\_SB\\LNKE\\_PRS\n") */ - Return(IRQP) - } /* Method(_SB.INTE._PRS) */ - - Method(_CRS ,0) { - /* DBGO("\\_SB\\LNKE\\_CRS\n") */ - CreateWordField(IRQB, 0x1, IRQN) - ShiftLeft(1, PINE, IRQN) - Return(IRQB) - } /* Method(_SB.INTE._CRS) */ - - Method(_SRS, 1) { - /* DBGO("\\_SB\\LNKE\\_CRS\n") */ - CreateWordField(ARG0, 1, IRQM) - - /* Use lowest available IRQ */ - FindSetRightBit(IRQM, Local0) - if (Local0) { - Decrement(Local0) - } - Store(Local0, PINE) - } /* End Method(_SB.INTE._SRS) */ - } /* End Device(INTE) */ - - Device(INTF) { - Name(_HID, EISAID("PNP0C0F")) - Name(_UID, 6) - - Method(_STA, 0) { - if (PINF) { - Return(0x0B) /* sata is invisible */ - } else { - Return(0x09) /* sata is disabled */ - } - } /* End Method(_SB.INTF._STA) */ - - Method(_DIS ,0) { - /* DBGO("\\_SB\\LNKF\\_DIS\n") */ - Store(0, PINF) - } /* End Method(_SB.INTF._DIS) */ - - Method(_PRS ,0) { - /* DBGO("\\_SB\\LNKF\\_PRS\n") */ - Return(PITF) - } /* Method(_SB.INTF._PRS) */ - - Method(_CRS ,0) { - /* DBGO("\\_SB\\LNKF\\_CRS\n") */ - CreateWordField(IRQB, 0x1, IRQN) - ShiftLeft(1, PINF, IRQN) - Return(IRQB) - } /* Method(_SB.INTF._CRS) */ - - Method(_SRS, 1) { - /* DBGO("\\_SB\\LNKF\\_CRS\n") */ - CreateWordField(ARG0, 1, IRQM) - - /* Use lowest available IRQ */ - FindSetRightBit(IRQM, Local0) - if (Local0) { - Decrement(Local0) - } - Store(Local0, PINF) - } /* End Method(_SB.INTF._SRS) */ - } /* End Device(INTF) */ - - Device(INTG) { - Name(_HID, EISAID("PNP0C0F")) - Name(_UID, 7) - - Method(_STA, 0) { - if (PING) { - Return(0x0B) /* sata is invisible */ - } else { - Return(0x09) /* sata is disabled */ - } - } /* End Method(_SB.INTG._STA) */ - - Method(_DIS ,0) { - /* DBGO("\\_SB\\LNKG\\_DIS\n") */ - Store(0, PING) - } /* End Method(_SB.INTG._DIS) */ - - Method(_PRS ,0) { - /* DBGO("\\_SB\\LNKG\\_PRS\n") */ - Return(IRQP) - } /* Method(_SB.INTG._CRS) */ - - Method(_CRS ,0) { - /* DBGO("\\_SB\\LNKG\\_CRS\n") */ - CreateWordField(IRQB, 0x1, IRQN) - ShiftLeft(1, PING, IRQN) - Return(IRQB) - } /* Method(_SB.INTG._CRS) */ - - Method(_SRS, 1) { - /* DBGO("\\_SB\\LNKG\\_CRS\n") */ - CreateWordField(ARG0, 1, IRQM) - - /* Use lowest available IRQ */ - FindSetRightBit(IRQM, Local0) - if (Local0) { - Decrement(Local0) - } - Store(Local0, PING) - } /* End Method(_SB.INTG._SRS) */ - } /* End Device(INTG) */ - - Device(INTH) { - Name(_HID, EISAID("PNP0C0F")) - Name(_UID, 8) - - Method(_STA, 0) { - if (PINH) { - Return(0x0B) /* sata is invisible */ - } else { - Return(0x09) /* sata is disabled */ - } - } /* End Method(_SB.INTH._STA) */ - - Method(_DIS ,0) { - /* DBGO("\\_SB\\LNKH\\_DIS\n") */ - Store(0, PINH) - } /* End Method(_SB.INTH._DIS) */ - - Method(_PRS ,0) { - /* DBGO("\\_SB\\LNKH\\_PRS\n") */ - Return(IRQP) - } /* Method(_SB.INTH._CRS) */ - - Method(_CRS ,0) { - /* DBGO("\\_SB\\LNKH\\_CRS\n") */ - CreateWordField(IRQB, 0x1, IRQN) - ShiftLeft(1, PINH, IRQN) - Return(IRQB) - } /* Method(_SB.INTH._CRS) */ - - Method(_SRS, 1) { - /* DBGO("\\_SB\\LNKH\\_CRS\n") */ - CreateWordField(ARG0, 1, IRQM) - - /* Use lowest available IRQ */ - FindSetRightBit(IRQM, Local0) - if (Local0) { - Decrement(Local0) - } - Store(Local0, PINH) - } /* End Method(_SB.INTH._SRS) */ - } /* End Device(INTH) */ - - } /* End Scope(_SB) */ - - #include - - /* Wake status package */ - Name(WKST,Package(){Zero, Zero}) - - /* - * \_PTS - Prepare to Sleep method - * - * Entry: - * Arg0=The value of the sleeping state S1=1, S2=2, etc - * - * Exit: - * -none- - * - * The _PTS control method is executed at the beginning of the sleep process - * for S1-S5. The sleeping value is passed to the _PTS control method. This - * control method may be executed a relatively long time before entering the - * sleep state and the OS may abort the operation without notification to - * the ACPI driver. This method cannot modify the configuration or power - * state of any device in the system. - */ - Method(\_PTS, 1) { - /* DBGO("\\_PTS\n") */ - /* DBGO("From S0 to S") */ - /* DBGO(Arg0) */ - /* DBGO("\n") */ - - /* Don't allow PCIRST# to reset USB */ - if (LEqual(Arg0,3)){ - Store(0,URRE) - } - - /* Clear sleep SMI status flag and enable sleep SMI trap. */ - /*Store(One, CSSM) - Store(One, SSEN)*/ - - /* On older chips, clear PciExpWakeDisEn */ - /*if (LLessEqual(\_SB.SBRI, 0x13)) { - * Store(0,\_SB.PWDE) - *} - */ - - /* Clear wake status structure. */ - Store(0, Index(WKST,0)) - Store(0, Index(WKST,1)) - \_SB.PCI0.SIOS (Arg0) - } /* End Method(\_PTS) */ - - /* - * The following method results in a "not a valid reserved NameSeg" - * warning so I have commented it out for the duration. It isn't - * used, so it could be removed. - * - * - * \_GTS OEM Going To Sleep method - * - * Entry: - * Arg0=The value of the sleeping state S1=1, S2=2 - * - * Exit: - * -none- - * - * Method(\_GTS, 1) { - * DBGO("\\_GTS\n") - * DBGO("From S0 to S") - * DBGO(Arg0) - * DBGO("\n") - * } - */ - - /* - * \_BFS OEM Back From Sleep method - * - * Entry: - * Arg0=The value of the sleeping state S1=1, S2=2 - * - * Exit: - * -none- - */ - Method(\_BFS, 1) { - /* DBGO("\\_BFS\n") */ - /* DBGO("From S") */ - /* DBGO(Arg0) */ - /* DBGO(" to S0\n") */ - } - - /* - * \_WAK System Wake method - * - * Entry: - * Arg0=The value of the sleeping state S1=1, S2=2 - * - * Exit: - * Return package of 2 DWords - * Dword 1 - Status - * 0x00000000 wake succeeded - * 0x00000001 Wake was signaled but failed due to lack of power - * 0x00000002 Wake was signaled but failed due to thermal condition - * Dword 2 - Power Supply state - * if non-zero the effective S-state the power supply entered - */ - Method(\_WAK, 1) { - /* DBGO("\\_WAK\n") */ - /* DBGO("From S") */ - /* DBGO(Arg0) */ - /* DBGO(" to S0\n") */ - - /* Re-enable HPET */ - Store(1,HPDE) - - /* Restore PCIRST# so it resets USB */ - if (LEqual(Arg0,3)){ - Store(1,URRE) - } - - /* Arbitrarily clear PciExpWakeStatus */ - Store(PWST, Local1) - Store(Local1, PWST) - - /* if (DeRefOf(Index(WKST,0))) { - * Store(0, Index(WKST,1)) - * } else { - * Store(Arg0, Index(WKST,1)) - * } - */ - \_SB.PCI0.SIOW () - Return(WKST) - } /* End Method(\_WAK) */ - - Scope(\_GPE) { /* Start Scope GPE */ - /* General event 0 */ - /* Method(_L00) { - * DBGO("\\_GPE\\_L00\n") - * } - */ - - /* General event 1 */ - /* Method(_L01) { - * DBGO("\\_GPE\\_L00\n") - * } - */ - - /* General event 2 */ - /* Method(_L02) { - * DBGO("\\_GPE\\_L00\n") - * } - */ - - /* General event 3 */ - Method(_L03) { - /* DBGO("\\_GPE\\_L00\n") */ - Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ - } - - /* General event 4 */ - /* Method(_L04) { - * DBGO("\\_GPE\\_L00\n") - * } - */ - - /* General event 5 */ - /* Method(_L05) { - * DBGO("\\_GPE\\_L00\n") - * } - */ - - /* General event 6 - Used for GPM6, moved to USB.asl */ - /* Method(_L06) { - * DBGO("\\_GPE\\_L00\n") - * } - */ - - /* General event 7 - Used for GPM7, moved to USB.asl */ - /* Method(_L07) { - * DBGO("\\_GPE\\_L07\n") - * } - */ - - /* Legacy PM event */ - Method(_L08) { - /* DBGO("\\_GPE\\_L08\n") */ - } - - /* Temp warning (TWarn) event */ - Method(_L09) { - /* DBGO("\\_GPE\\_L09\n") */ - Notify (\_TZ.TZ00, 0x80) - } - - /* Reserved */ - /* Method(_L0A) { - * DBGO("\\_GPE\\_L0A\n") - * } - */ - - /* USB controller PME# */ - Method(_L0B) { - /* DBGO("\\_GPE\\_L0B\n") */ - Notify(\_SB.PCI0.UOH1, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(\_SB.PCI0.UOH2, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(\_SB.PCI0.UOH3, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(\_SB.PCI0.UOH4, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(\_SB.PCI0.UOH5, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(\_SB.PCI0.UEH1, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ - } - - /* AC97 controller PME# */ - /* Method(_L0C) { - * DBGO("\\_GPE\\_L0C\n") - * } - */ - - /* OtherTherm PME# */ - /* Method(_L0D) { - * DBGO("\\_GPE\\_L0D\n") - * } - */ - - /* GPM9 SCI event - Moved to USB.asl */ - /* Method(_L0E) { - * DBGO("\\_GPE\\_L0E\n") - * } - */ - - /* PCIe HotPlug event */ - /* Method(_L0F) { - * DBGO("\\_GPE\\_L0F\n") - * } - */ - - /* ExtEvent0 SCI event */ - Method(_L10) { - /* DBGO("\\_GPE\\_L10\n") */ - } - - - /* ExtEvent1 SCI event */ - Method(_L11) { - /* DBGO("\\_GPE\\_L11\n") */ - } - - /* PCIe PME# event */ - /* Method(_L12) { - * DBGO("\\_GPE\\_L12\n") - * } - */ - - /* GPM0 SCI event - Moved to USB.asl */ - /* Method(_L13) { - * DBGO("\\_GPE\\_L13\n") - * } - */ - - /* GPM1 SCI event - Moved to USB.asl */ - /* Method(_L14) { - * DBGO("\\_GPE\\_L14\n") - * } - */ - - /* GPM2 SCI event - Moved to USB.asl */ - /* Method(_L15) { - * DBGO("\\_GPE\\_L15\n") - * } - */ - - /* GPM3 SCI event - Moved to USB.asl */ - /* Method(_L16) { - * DBGO("\\_GPE\\_L16\n") - * } - */ - - /* GPM8 SCI event - Moved to USB.asl */ - /* Method(_L17) { - * DBGO("\\_GPE\\_L17\n") - * } - */ - - /* GPIO0 or GEvent8 event */ - Method(_L18) { - /* DBGO("\\_GPE\\_L18\n") */ - Notify(\_SB.PCI0.PBR2, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(\_SB.PCI0.PBR4, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(\_SB.PCI0.PBR5, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(\_SB.PCI0.PBR6, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(\_SB.PCI0.PBR7, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ - } - - /* GPM4 SCI event - Moved to USB.asl */ - /* Method(_L19) { - * DBGO("\\_GPE\\_L19\n") - * } - */ - - /* GPM5 SCI event - Moved to USB.asl */ - /* Method(_L1A) { - * DBGO("\\_GPE\\_L1A\n") - * } - */ - - /* Azalia SCI event */ - Method(_L1B) { - /* DBGO("\\_GPE\\_L1B\n") */ - Notify(\_SB.PCI0.AZHD, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ - } - - /* GPM6 SCI event - Reassigned to _L06 */ - /* Method(_L1C) { - * DBGO("\\_GPE\\_L1C\n") - * } - */ - - /* GPM7 SCI event - Reassigned to _L07 */ - /* Method(_L1D) { - * DBGO("\\_GPE\\_L1D\n") - * } - */ - - /* GPIO2 or GPIO66 SCI event */ - /* Method(_L1E) { - * DBGO("\\_GPE\\_L1E\n") - * } - */ - - /* SATA SCI event - Moved to sata.asl */ - /* Method(_L1F) { - * DBGO("\\_GPE\\_L1F\n") - * } - */ - - } /* End Scope GPE */ - - #include "acpi/usb.asl" - - /* System Bus */ - Scope(\_SB) { /* Start \_SB scope */ - #include /* global utility methods expected within the \_SB scope */ - - /* _SB.PCI0 */ - /* Note: Only need HID on Primary Bus */ - Device(PCI0) { - External (TOM1) - External (TOM2) /* ( >> 20) to make it fit into 32 bit for XP */ - Name(_HID, EISAID("PNP0A03")) - Name(_ADR, 0x00180000) /* Dev# = BSP Dev#, Func# = 0 */ - Method(_BBN, 0) { /* Bus number = 0 */ - Return(0) - } - Method(_STA, 0) { - /* DBGO("\\_SB\\PCI0\\_STA\n") */ - Return(0x0B) /* Status is visible */ - } - - Method(_PRT,0) { - If(PMOD){ Return(APR0) } /* APIC mode */ - Return (PR0) /* PIC Mode */ - } /* end _PRT */ - - /* Describe the Northbridge devices */ - Device(AMRT) { - Name(_ADR, 0x00000000) - } /* end AMRT */ - - /* The internal GFX bridge */ - Device(AGPB) { - Name(_ADR, 0x00010000) - Name(_PRW, Package() {0x18, 4}) - Method(_PRT,0) { - Return (APR1) - } - } /* end AGPB */ - - /* The external GFX bridge */ - Device(PBR2) { - Name(_ADR, 0x00020000) - Name(_PRW, Package() {0x18, 4}) - Method(_PRT,0) { - If(PMOD){ Return(APS2) } /* APIC mode */ - Return (PS2) /* PIC Mode */ - } /* end _PRT */ - } /* end PBR2 */ - - /* Dev3 is also an external GFX bridge, not used in Herring */ - - Device(PBR4) { - Name(_ADR, 0x00040000) - Name(_PRW, Package() {0x18, 4}) - Method(_PRT,0) { - If(PMOD){ Return(APS4) } /* APIC mode */ - Return (PS4) /* PIC Mode */ - } /* end _PRT */ - } /* end PBR4 */ - - Device(PBR5) { - Name(_ADR, 0x00050000) - Name(_PRW, Package() {0x18, 4}) - Method(_PRT,0) { - If(PMOD){ Return(APS5) } /* APIC mode */ - Return (PS5) /* PIC Mode */ - } /* end _PRT */ - } /* end PBR5 */ - - Device(PBR6) { - Name(_ADR, 0x00060000) - Name(_PRW, Package() {0x18, 4}) - Method(_PRT,0) { - If(PMOD){ Return(APS6) } /* APIC mode */ - Return (PS6) /* PIC Mode */ - } /* end _PRT */ - } /* end PBR6 */ - - /* The onboard EtherNet chip */ - Device(PBR7) { - Name(_ADR, 0x00070000) - Name(_PRW, Package() {0x18, 4}) - Method(_PRT,0) { - If(PMOD){ Return(APS7) } /* APIC mode */ - Return (PS7) /* PIC Mode */ - } /* end _PRT */ - } /* end PBR7 */ - - /* GPP */ - Device(PBR9) { - Name(_ADR, 0x00090000) - Name(_PRW, Package() {0x18, 4}) - Method(_PRT,0) { - If(PMOD){ Return(APS9) } /* APIC mode */ - Return (PS9) /* PIC Mode */ - } /* end _PRT */ - } /* end PBR9 */ - - Device(PBRa) { - Name(_ADR, 0x000A0000) - Name(_PRW, Package() {0x18, 4}) - Method(_PRT,0) { - If(PMOD){ Return(APSa) } /* APIC mode */ - Return (PSa) /* PIC Mode */ - } /* end _PRT */ - } /* end PBRa */ - - Device(PBRb) { - Name(_ADR, 0x000b0000) - Name(_PRW, Package() {0x18, 4}) - Method(_PRT,0) { - If(PMOD){ Return(APSb) } /* APIC mode */ - Return (PSb) /* PIC Mode */ - } /* end _PRT */ - } /* end PBRb */ - - Device(PBRc) { - Name(_ADR, 0x000c0000) - Name(_PRW, Package() {0x18, 4}) - Method(_PRT,0) { - If(PMOD){ Return(APSc) } /* APIC mode */ - Return (PSc) /* PIC Mode */ - } /* end _PRT */ - } /* end PBRc */ - - - /* PCI slot 1, 2, 3 */ - Device(PIBR) { - Name(_ADR, 0x00140004) - Name(_PRW, Package() {0x18, 4}) - - Method(_PRT, 0) { - Return (PCIB) - } - } - - /* Describe the Southbridge devices */ - Device(STCR) { - Name(_ADR, 0x00110000) - #include "acpi/sata.asl" - } /* end STCR */ - - Device(UOH1) { - Name(_ADR, 0x00130000) - Name(_PRW, Package() {0x0B, 3}) - } /* end UOH1 */ - - Device(UOH2) { - Name(_ADR, 0x00130001) - Name(_PRW, Package() {0x0B, 3}) - } /* end UOH2 */ - - Device(UOH3) { - Name(_ADR, 0x00130002) - Name(_PRW, Package() {0x0B, 3}) - } /* end UOH3 */ - - Device(UOH4) { - Name(_ADR, 0x00130003) - Name(_PRW, Package() {0x0B, 3}) - } /* end UOH4 */ - - Device(UOH5) { - Name(_ADR, 0x00130004) - Name(_PRW, Package() {0x0B, 3}) - } /* end UOH5 */ - - Device(UEH1) { - Name(_ADR, 0x00130005) - Name(_PRW, Package() {0x0B, 3}) - } /* end UEH1 */ - - Device(SBUS) { - Name(_ADR, 0x00140000) - } /* end SBUS */ - - /* Primary (and only) IDE channel */ - Device(IDEC) { - Name(_ADR, 0x00140001) - #include "acpi/ide.asl" - } /* end IDEC */ - - Device(AZHD) { - Name(_ADR, 0x00140002) - OperationRegion(AZPD, PCI_Config, 0x00, 0x100) - Field(AZPD, AnyAcc, NoLock, Preserve) { - offset (0x42), - NSDI, 1, - NSDO, 1, - NSEN, 1, - offset (0x44), - IPCR, 4, - offset (0x54), - PWST, 2, - , 6, - PMEB, 1, - , 6, - PMST, 1, - offset (0x62), - MMCR, 1, - offset (0x64), - MMLA, 32, - offset (0x68), - MMHA, 32, - offset (0x6C), - MMDT, 16, - } - - Method(_INI) { - If(LEqual(OSVR,3)){ /* If we are running Linux */ - Store(zero, NSEN) - Store(one, NSDO) - Store(one, NSDI) - } - } - } /* end AZHD */ - - Device(LIBR) { - Name(_ADR, 0x00140003) - /* Method(_INI) { - * DBGO("\\_SB\\PCI0\\LpcIsaBr\\_INI\n") - } */ /* End Method(_SB.SBRDG._INI) */ - - /* Real Time Clock Device */ - Device(RTC0) { - Name(_HID, EISAID("PNP0B00")) /* AT Real Time Clock (not PIIX4 compatible) */ - Name(_CRS, ResourceTemplate() { - IRQNoFlags(){8} - IO(Decode16,0x0070, 0x0070, 0, 2) - /* IO(Decode16,0x0070, 0x0070, 0, 4) */ - }) - } /* End Device(_SB.PCI0.LpcIsaBr.RTC0) */ - - Device(TMR) { /* Timer */ - Name(_HID,EISAID("PNP0100")) /* System Timer */ - Name(_CRS, ResourceTemplate() { - IRQNoFlags(){0} - IO(Decode16, 0x0040, 0x0040, 0, 4) - /* IO(Decode16, 0x0048, 0x0048, 0, 4) */ - }) - } /* End Device(_SB.PCI0.LpcIsaBr.TMR) */ - - Device(SPKR) { /* Speaker */ - Name(_HID,EISAID("PNP0800")) /* AT style speaker */ - Name(_CRS, ResourceTemplate() { - IO(Decode16, 0x0061, 0x0061, 0, 1) - }) - } /* End Device(_SB.PCI0.LpcIsaBr.SPKR) */ - - Device(PIC) { - Name(_HID,EISAID("PNP0000")) /* AT Interrupt Controller */ - Name(_CRS, ResourceTemplate() { - IRQNoFlags(){2} - IO(Decode16,0x0020, 0x0020, 0, 2) - IO(Decode16,0x00A0, 0x00A0, 0, 2) - /* IO(Decode16, 0x00D0, 0x00D0, 0x10, 0x02) */ - /* IO(Decode16, 0x04D0, 0x04D0, 0x10, 0x02) */ - }) - } /* End Device(_SB.PCI0.LpcIsaBr.PIC) */ - - Device(MAD) { /* 8257 DMA */ - Name(_HID,EISAID("PNP0200")) /* Hardware Device ID */ - Name(_CRS, ResourceTemplate() { - DMA(Compatibility,BusMaster,Transfer8){4} - IO(Decode16, 0x0000, 0x0000, 0x10, 0x10) - IO(Decode16, 0x0081, 0x0081, 0x01, 0x03) - IO(Decode16, 0x0087, 0x0087, 0x01, 0x01) - IO(Decode16, 0x0089, 0x0089, 0x01, 0x03) - IO(Decode16, 0x008F, 0x008F, 0x01, 0x01) - IO(Decode16, 0x00C0, 0x00C0, 0x10, 0x20) - }) /* End Name(_SB.PCI0.LpcIsaBr.MAD._CRS) */ - } /* End Device(_SB.PCI0.LpcIsaBr.MAD) */ - - Device(COPR) { - Name(_HID,EISAID("PNP0C04")) /* Math Coprocessor */ - Name(_CRS, ResourceTemplate() { - IO(Decode16, 0x00F0, 0x00F0, 0, 0x10) - IRQNoFlags(){13} - }) - } /* End Device(_SB.PCI0.LpcIsaBr.COPR) */ - - Device(HPTM) { - Name(_HID,EISAID("PNP0103")) - Name(CRS,ResourceTemplate() { - Memory32Fixed(ReadOnly,0xFED00000, 0x00000400, HPT) /* 1kb reserved space */ - }) - Method(_STA, 0) { - Return(0x0F) /* sata is visible */ - } - Method(_CRS, 0) { - CreateDwordField(CRS, ^HPT._BAS, HPBX) - Store(HPBA, HPBX) - Return(CRS) - } - } /* End Device(_SB.PCI0.LpcIsaBr.COPR) */ - } /* end LIBR */ - - Device(HPBR) { - Name(_ADR, 0x00140004) - } /* end HostPciBr */ - - Device(ACAD) { - Name(_ADR, 0x00140005) - } /* end Ac97audio */ - - Device(ACMD) { - Name(_ADR, 0x00140006) - } /* end Ac97modem */ - - /* ITE8718 Support */ - OperationRegion (IOID, SystemIO, 0x2E, 0x02) /* sometimes it is 0x4E */ - Field (IOID, ByteAcc, NoLock, Preserve) - { - SIOI, 8, SIOD, 8 /* 0x2E and 0x2F */ - } - - IndexField (SIOI, SIOD, ByteAcc, NoLock, Preserve) - { - Offset (0x07), - LDN, 8, /* Logical Device Number */ - Offset (0x20), - CID1, 8, /* Chip ID Byte 1, 0x87 */ - CID2, 8, /* Chip ID Byte 2, 0x12 */ - Offset (0x30), - ACTR, 8, /* Function activate */ - Offset (0xF0), - APC0, 8, /* APC/PME Event Enable Register */ - APC1, 8, /* APC/PME Status Register */ - APC2, 8, /* APC/PME Control Register 1 */ - APC3, 8, /* Environment Controller Special Configuration Register */ - APC4, 8 /* APC/PME Control Register 2 */ - } - - /* Enter the 8718 MB PnP Mode */ - Method (EPNP) - { - Store(0x87, SIOI) - Store(0x01, SIOI) - Store(0x55, SIOI) - Store(0x55, SIOI) /* 8718 magic number */ - } - /* Exit the 8718 MB PnP Mode */ - Method (XPNP) - { - Store (0x02, SIOI) - Store (0x02, SIOD) - } - /* - * Keyboard PME is routed to SB700 Gevent3. We can wake - * up the system by pressing the key. - */ - Method (SIOS, 1) - { - /* We only enable KBD PME for S5. */ - If (LLess (Arg0, 0x05)) - { - EPNP() - /* DBGO("8718F\n") */ - - Store (0x4, LDN) - Store (One, ACTR) /* Enable EC */ - /* - Store (0x4, LDN) - Store (0x04, APC4) - */ /* falling edge. which mode? Not sure. */ - - Store (0x4, LDN) - Store (0x08, APC1) /* clear PME status, Use 0x18 for mouse & KBD */ - Store (0x4, LDN) - Store (0x08, APC0) /* enable PME, Use 0x18 for mouse & KBD */ - - XPNP() - } - } - Method (SIOW, 0) - { - EPNP() - Store (0x4, LDN) - Store (Zero, APC0) /* disable keyboard PME */ - Store (0x4, LDN) - Store (0xFF, APC1) /* clear keyboard PME status */ - XPNP() - } - - Name(CRES, ResourceTemplate() { - IO(Decode16, 0x0CF8, 0x0CF8, 1, 8) - - WORDIO(ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, - 0x0000, /* address granularity */ - 0x0000, /* range minimum */ - 0x0CF7, /* range maximum */ - 0x0000, /* translation */ - 0x0CF8 /* length */ - ) - - WORDIO(ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, - 0x0000, /* address granularity */ - 0x0D00, /* range minimum */ - 0xFFFF, /* range maximum */ - 0x0000, /* translation */ - 0xF300 /* length */ - ) - -#if 0 - Memory32Fixed(READWRITE, 0, 0xA0000, BSMM) - Memory32Fixed(READONLY, 0x000A0000, 0x00020000, VGAM) /* VGA memory space */ - Memory32Fixed(READONLY, 0x000C0000, 0x00020000, EMM1) /* Assume C0000-E0000 empty */ - Memory32Fixed(READONLY, 0x000E0000, 0x00020000, RDBS) /* BIOS ROM area */ - - /* DRAM Memory from 1MB to TopMem */ - Memory32Fixed(READWRITE, 0x00100000, 0, DMLO) /* 1MB to TopMem */ - - /* BIOS space just below 4GB */ - DWORDMemory( - ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite, - 0x00, /* Granularity */ - 0x00000000, /* Min */ - 0x00000000, /* Max */ - 0x00000000, /* Translation */ - 0x00000001, /* Max-Min, RLEN */ - ,, - PCBM - ) - - /* DRAM memory from 4GB to TopMem2 */ - QWORDMemory(ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite, - 0x00000000, /* Granularity */ - 0x00000000, /* Min */ - 0x00000000, /* Max */ - 0x00000000, /* Translation */ - 0x00000001, /* Max-Min, RLEN */ - ,, - DMHI - ) - - /* BIOS space just below 16EB */ - QWORDMemory(ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite, - 0x00000000, /* Granularity */ - 0x00000000, /* Min */ - 0x00000000, /* Max */ - 0x00000000, /* Translation */ - 0x00000001, /* Max-Min, RLEN */ - ,, - PEBM - ) -#endif - - /* memory space for PCI BARs below 4GB */ - Memory32Fixed(ReadOnly, 0x00000000, 0x00000000, MMIO) - }) /* End Name(_SB.PCI0.CRES) */ - - Method(_CRS, 0) { - /* DBGO("\\_SB\\PCI0\\_CRS\n") */ - -#if 0 - CreateDWordField(CRES, ^EMM1._BAS, EM1B) - CreateDWordField(CRES, ^EMM1._LEN, EM1L) - CreateDWordField(CRES, ^DMLO._BAS, DMLB) - CreateDWordField(CRES, ^DMLO._LEN, DMLL) - CreateDWordField(CRES, ^PCBM._MIN, PBMB) - CreateDWordField(CRES, ^PCBM._LEN, PBML) - - CreateQWordField(CRES, ^DMHI._MIN, DMHB) - CreateQWordField(CRES, ^DMHI._LEN, DMHL) - CreateQWordField(CRES, ^PEBM._MIN, EBMB) - CreateQWordField(CRES, ^PEBM._LEN, EBML) - - If(LGreater(LOMH, 0xC0000)){ - Store(0xC0000, EM1B) /* Hole above C0000 and below E0000 */ - Subtract(LOMH, 0xC0000, EM1L) /* subtract start, assumes allocation from C0000 going up */ - } - - /* Set size of memory from 1MB to TopMem */ - Subtract(TOM1, 0x100000, DMLL) - - /* - * If(LNotEqual(TOM2, 0x00000000)){ - * Store(0x100000000,DMHB) DRAM from 4GB to TopMem2 - * Subtract(TOM2, 0x100000000, DMHL) - * } - */ - - /* If there is no memory above 4GB, put the BIOS just below 4GB */ - If(LEqual(TOM2, 0x00000000)){ - Store(PBAD,PBMB) /* Reserve the "BIOS" space */ - Store(PBLN,PBML) - } - Else { /* Otherwise, put the BIOS just below 16EB */ - ShiftLeft(PBAD,16,EBMB) /* Reserve the "BIOS" space */ - Store(PBLN,EBML) - } -#endif - - CreateDWordField(CRES, ^MMIO._BAS, MM1B) - CreateDWordField(CRES, ^MMIO._LEN, MM1L) - /* - * Declare memory between TOM1 and 4GB as available - * for PCI MMIO. - * Use ShiftLeft to avoid 64bit constant (for XP). - * This will work even if the OS does 32bit arithmetic, as - * 32bit (0x00000000 - TOM1) will wrap and give the same - * result as 64bit (0x100000000 - TOM1). - */ - Store(TOM1, MM1B) - ShiftLeft(0x10000000, 4, Local0) - Subtract(Local0, TOM1, Local0) - Store(Local0, MM1L) - - Return(CRES) /* note to change the Name buffer */ - } /* end of Method(_SB.PCI0._CRS) */ - - /* - * - * FIRST METHOD CALLED UPON BOOT - * - * 1. If debugging, print current OS and ACPI interpreter. - * 2. Get PCI Interrupt routing from ACPI VSM, this - * value is based on user choice in BIOS setup. - */ - Method(_INI, 0) { - /* DBGO("\\_SB\\_INI\n") */ - /* DBGO(" DSDT.ASL code from ") */ - /* DBGO(__DATE__) */ - /* DBGO(" ") */ - /* DBGO(__TIME__) */ - /* DBGO("\n Sleep states supported: ") */ - /* DBGO("\n") */ - /* DBGO(" \\_OS=") */ - /* DBGO(\_OS) */ - /* DBGO("\n \\_REV=") */ - /* DBGO(\_REV) */ - /* DBGO("\n") */ - - /* Determine the OS we're running on */ - OSFL() - - /* On older chips, clear PciExpWakeDisEn */ - /*if (LLessEqual(\SBRI, 0x13)) { - * Store(0,\PWDE) - * } - */ - } /* End Method(_SB._INI) */ - } /* End Device(PCI0) */ - - Device(PWRB) { /* Start Power button device */ - Name(_HID, EISAID("PNP0C0C")) - Name(_UID, 0xAA) - Name(_PRW, Package () {3, 0x04}) /* wake from S1-S4 */ - Name(_STA, 0x0B) /* sata is invisible */ - } - } /* End \_SB scope */ - - Scope(\_SI) { - Method(_SST, 1) { - /* DBGO("\\_SI\\_SST\n") */ - /* DBGO(" New Indicator state: ") */ - /* DBGO(Arg0) */ - /* DBGO("\n") */ - } - } /* End Scope SI */ - - #include - - /* THERMAL */ - Scope(\_TZ) { - Name (KELV, 2732) - Name (THOT, 800) - Name (TCRT, 850) - - ThermalZone(TZ00) { - Method(_AC0,0) { /* Active Cooling 0 (0=highest fan speed) */ - /* DBGO("\\_TZ\\TZ00\\_AC0\n") */ - Return(Add(0, 2730)) - } - Method(_AL0,0) { /* Returns package of cooling device to turn on */ - /* DBGO("\\_TZ\\TZ00\\_AL0\n") */ - Return(Package() {\_TZ.TZ00.FAN0}) - } - Device (FAN0) { - Name(_HID, EISAID("PNP0C0B")) - Name(_PR0, Package() {PFN0}) - } - - PowerResource(PFN0,0,0) { - Method(_STA) { - Store(0xF,Local0) - Return(Local0) - } - Method(_ON) { - /* DBGO("\\_TZ\\TZ00\\FAN0 _ON\n") */ - } - Method(_OFF) { - /* DBGO("\\_TZ\\TZ00\\FAN0 _OFF\n") */ - } - } - - Method(_HOT,0) { /* return hot temp in tenths degree Kelvin */ - /* DBGO("\\_TZ\\TZ00\\_HOT\n") */ - Return (Add (THOT, KELV)) - } - Method(_CRT,0) { /* return critical temp in tenths degree Kelvin */ - /* DBGO("\\_TZ\\TZ00\\_CRT\n") */ - Return (Add (TCRT, KELV)) - } - Method(_TMP,0) { /* return current temp of this zone */ - Store (SMBR (0x07, 0x4C,, 0x00), Local0) - If (LGreater (Local0, 0x10)) { - Store (Local0, Local1) - } - Else { - Add (Local0, THOT, Local0) - Return (Add (400, KELV)) - } - - Store (SMBR (0x07, 0x4C, 0x01), Local0) - /* only the two MSBs in the external temperature low byte are used, resolution 0.25. We ignore it */ - /* Store (SMBR (0x07, 0x4C, 0x10), Local2) */ - If (LGreater (Local0, 0x10)) { - If (LGreater (Local0, Local1)) { - Store (Local0, Local1) - } - - Multiply (Local1, 10, Local1) - Return (Add (Local1, KELV)) - } - Else { - Add (Local0, THOT, Local0) - Return (Add (400 , KELV)) - } - } /* end of _TMP */ - } /* end of TZ00 */ - } -} -/* End of ASL file */ diff --git a/src/mainboard/supermicro/h8scm_fam10/get_bus_conf.c b/src/mainboard/supermicro/h8scm_fam10/get_bus_conf.c deleted file mode 100644 index 8bc96c22a8..0000000000 --- a/src/mainboard/supermicro/h8scm_fam10/get_bus_conf.c +++ /dev/null @@ -1,55 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2010 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include -#include -#include - -#include - -/* Global variables for MB layouts and these will be shared by irqtable mptable -* and acpi_tables busnum is default. -*/ -u8 bus_sr5650[14]; - -void get_bus_conf(void) -{ - struct device *dev; - int i; - - get_default_pci1234(1); - - sysconf.sbdn = (sysconf.hcdn[0] & 0xff); - - for (i = 0; i < ARRAY_SIZE(bus_sr5650); i++) { - bus_sr5650[i] = 0; - } - - - bus_sr5650[0] = (sysconf.pci1234[0] >> 16) & 0xff; - pirq_router_bus = bus_sr5650[0]; - - /* sr5650 */ - for (i = 1; i < ARRAY_SIZE(bus_sr5650); i++) { - dev = dev_find_slot(bus_sr5650[0], PCI_DEVFN(sysconf.sbdn + i, 0)); - if (dev) { - bus_sr5650[i] = pci_read_config8(dev, PCI_SECONDARY_BUS); - if(255 != bus_sr5650[i]) { - } - } - } -} diff --git a/src/mainboard/supermicro/h8scm_fam10/irq_tables.c b/src/mainboard/supermicro/h8scm_fam10/irq_tables.c deleted file mode 100644 index 81fae72956..0000000000 --- a/src/mainboard/supermicro/h8scm_fam10/irq_tables.c +++ /dev/null @@ -1,102 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2010 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include -#include -#include - -#include - -static void write_pirq_info(struct irq_info *pirq_info, u8 bus, u8 devfn, - u8 link0, u16 bitmap0, u8 link1, u16 bitmap1, - u8 link2, u16 bitmap2, u8 link3, u16 bitmap3, - u8 slot, u8 rfu) -{ - pirq_info->bus = bus; - pirq_info->devfn = devfn; - pirq_info->irq[0].link = link0; - pirq_info->irq[0].bitmap = bitmap0; - pirq_info->irq[1].link = link1; - pirq_info->irq[1].bitmap = bitmap1; - pirq_info->irq[2].link = link2; - pirq_info->irq[2].bitmap = bitmap2; - pirq_info->irq[3].link = link3; - pirq_info->irq[3].bitmap = bitmap3; - pirq_info->slot = slot; - pirq_info->rfu = rfu; -} - - -unsigned long write_pirq_routing_table(unsigned long addr) -{ - struct irq_routing_table *pirq; - struct irq_info *pirq_info; - u32 slot_num; - u8 *v; - - u8 sum = 0; - int i; - - /* Align the table to be 16 byte aligned. */ - addr += 15; - addr &= ~15; - - /* This table must be between 0xf0000 & 0x100000 */ - printk(BIOS_INFO, "Writing IRQ routing tables to 0x%lx...", addr); - - pirq = (void *)(addr); - v = (u8 *) (addr); - - pirq->signature = PIRQ_SIGNATURE; - pirq->version = PIRQ_VERSION; - - pirq->rtr_bus = pirq_router_bus; - pirq->rtr_devfn = PCI_DEVFN(0x14, 4); - - pirq->exclusive_irqs = 0; - - pirq->rtr_vendor = 0x1002; - pirq->rtr_device = 0x4384; - - pirq->miniport_data = 0; - - memset(pirq->rfu, 0, sizeof(pirq->rfu)); - - pirq_info = (void *)(&pirq->checksum + 1); - slot_num = 0; - - /* pci bridge */ - write_pirq_info(pirq_info, pirq_router_bus, - PCI_DEVFN(0x14, 4), 0x1, 0xdef8, 0x2, - 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, 0); - pirq_info++; - slot_num++; - - pirq->size = 32 + 16 * slot_num; - - for (i = 0; i < pirq->size; i++) - sum += v[i]; - - sum = pirq->checksum - sum; - if (sum != pirq->checksum) { - pirq->checksum = sum; - } - - printk(BIOS_INFO, "write_pirq_routing_table done.\n"); - - return (unsigned long)pirq_info; -} diff --git a/src/mainboard/supermicro/h8scm_fam10/mainboard.c b/src/mainboard/supermicro/h8scm_fam10/mainboard.c deleted file mode 100644 index b16f7a24d1..0000000000 --- a/src/mainboard/supermicro/h8scm_fam10/mainboard.c +++ /dev/null @@ -1,80 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2010 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include -#include -#include -#include -#include -#include - -/* - * TODO: Add the routine info of each PCIE_RESET_L. - * TODO: Add the reset of each PCIE_RESET_L. - * PCIE_RESET_GPIO1 -> Slot 0 - * PCIE_RESET_GPIO2 -> On-board NIC Bcm5709 - * PCIE_RESET_GPIO3 -> TMS - * PCIE_RESET_GPIO4 -> Slot 1 - * PCIE_RESET_GPIO5 -> Slot 2 - ***/ -void set_pcie_reset(void) -{ - struct device *pcie_core_dev; - - pcie_core_dev = pcidev_on_root(0, 0); - set_htiu_enable_bits(pcie_core_dev, 0xA8, 0xFFFFFFFF, 0x28282828); - set_htiu_enable_bits(pcie_core_dev, 0xA9, 0x000000FF, 0x00000028); -} - -void set_pcie_dereset(void) -{ - struct device *pcie_core_dev; - - pcie_core_dev = pcidev_on_root(0, 0); - set_htiu_enable_bits(pcie_core_dev, 0xA8, 0xFFFFFFFF, 0x6F6F6F6F); - set_htiu_enable_bits(pcie_core_dev, 0xA9, 0x000000FF, 0x0000006F); -} - -/************************************************* -* enable the dedicated function in h8scm board. -* This function called early than sr5650_enable. -*************************************************/ -static void mainboard_enable(struct device *dev) -{ - printk(BIOS_INFO, "Mainboard H8SCM Enable. dev=0x%p\n", dev); - - msr_t msr, msr2; - - /* TOP_MEM: the top of DRAM below 4G */ - msr = rdmsr(TOP_MEM); - printk - (BIOS_INFO, "%s, TOP MEM: msr.lo = 0x%08x, msr.hi = 0x%08x\n", - __func__, msr.lo, msr.hi); - - /* TOP_MEM2: the top of DRAM above 4G */ - msr2 = rdmsr(TOP_MEM2); - printk - (BIOS_INFO, "%s, TOP MEM2: msr2.lo = 0x%08x, msr2.hi = 0x%08x\n", - __func__, msr2.lo, msr2.hi); - - set_pcie_dereset(); - /* get_ide_dma66(); */ -} - -struct chip_operations mainboard_ops = { - .enable_dev = mainboard_enable, -}; diff --git a/src/mainboard/supermicro/h8scm_fam10/mb_sysconf.h b/src/mainboard/supermicro/h8scm_fam10/mb_sysconf.h deleted file mode 100644 index 59861163c9..0000000000 --- a/src/mainboard/supermicro/h8scm_fam10/mb_sysconf.h +++ /dev/null @@ -1,39 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2010 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef MB_SYSCONF_H - -#define MB_SYSCONF_H - -struct mb_sysconf_t { - u8 bus_isa; - u8 bus_8132_0; - u8 bus_8132_1; - u8 bus_8132_2; - u8 bus_8111_0; - u8 bus_8111_1; - u8 bus_8132a[31][3]; - u8 bus_8151[31][2]; - - u32 apicid_8111; - u32 apicid_8132_1; - u32 apicid_8132_2; - u32 apicid_8132a[31][2]; - u32 sbdn3; - u32 sbdn3a[31]; - u32 sbdn5[31]; -}; - -#endif diff --git a/src/mainboard/supermicro/h8scm_fam10/mptable.c b/src/mainboard/supermicro/h8scm_fam10/mptable.c deleted file mode 100644 index 112d20ae41..0000000000 --- a/src/mainboard/supermicro/h8scm_fam10/mptable.c +++ /dev/null @@ -1,128 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2010 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include -#include -#include - -extern u8 bus_sr5650[14]; - -static void *smp_write_config_table(void *v) -{ - struct mp_config_table *mc; - int bus_isa; - u32 apicid_sp5100; - u32 apicid_sr5650; - - mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); - - mptable_init(mc, LOCAL_APIC_ADDR); - - smp_write_processors(mc); - - apicid_sp5100 = 0x20; - apicid_sr5650 = apicid_sp5100 + 1; - - mptable_write_buses(mc, NULL, &bus_isa); - /* I/O APICs: APIC ID Version State Address */ - { - struct device *dev; - u32 *dword; - u8 byte; - - dev = pcidev_on_root(0x14, 0); - if (dev) { - dword = (u32 *)(pci_read_config32(dev, 0x74) & 0xfffffff0); - smp_write_ioapic(mc, apicid_sp5100, 0x11, dword); - - /* Initialize interrupt mapping */ - /* aza */ - byte = pci_read_config8(dev, 0x63); - byte &= 0xf8; - byte |= 0; /* 0: INTA, ...., 7: INTH */ - pci_write_config8(dev, 0x63, byte); - - /* SATA */ - dword = (u32 *)((pci_read_config32(dev, 0xac) & - ~(7 << 26)) | (6 << 26)); - - /* dword |= 1 << 22; PIC and APIC co exists */ - pci_write_config32(dev, 0xac, (u32)dword); - - /* - * 00:12.0: PROG SATA : INT F - * 00:13.0: INTA USB_0 - * 00:13.1: INTB USB_1 - * 00:13.2: INTC USB_2 - * 00:13.3: INTD USB_3 - * 00:13.4: INTC USB_4 - * 00:13.5: INTD USB2 - * 00:14.1: INTA IDE - * 00:14.2: Prog HDA : INT E - * 00:14.5: INTB ACI - * 00:14.6: INTB MCI - */ - } - dev = pcidev_on_root(0, 0); - if (dev) { - pci_write_config32(dev, 0xF8, 0x1); - dword = (u32 *)(pci_read_config32(dev, 0xFC) & 0xfffffff0); - smp_write_ioapic(mc, apicid_sr5650, 0x11, dword); - } - } - - /* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ -#define IO_LOCAL_INT(type, intr, apicid, pin) \ - smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin)); - - mptable_add_isa_interrupts(mc, bus_isa, apicid_sp5100, 0); - - /* on board NIC & Slot PCIE. */ - /* configuration B doesnt need dev 5,6,7 */ - /* - * PCI_INT(bus_sr5650[0x5], 0x0, 0x0, 0x11); - * PCI_INT(bus_sr5650[0x6], 0x0, 0x0, 0x12); - * PCI_INT(bus_sr5650[0x7], 0x0, 0x0, 0x13); - */ - smp_write_pci_intsrc(mc, mp_INT, 0, 2, 0, apicid_sr5650, 28); /* dev 2 */ - smp_write_pci_intsrc(mc, mp_INT, 0, 4, 0, apicid_sr5650, 28); /* dev 4 */ - smp_write_pci_intsrc(mc, mp_INT, 0, 12, 0, apicid_sr5650, 30); /* dev 11 */ - smp_write_pci_intsrc(mc, mp_INT, 0, 12, 0, apicid_sr5650, 30); /* dev 12 */ - - smp_write_pci_intsrc(mc, mp_INT, bus_sr5650[2], 0, 0, apicid_sr5650, 0); /* card behind dev2 */ - smp_write_pci_intsrc(mc, mp_INT, bus_sr5650[4], 0, 0, apicid_sr5650, 20); - smp_write_pci_intsrc(mc, mp_INT, bus_sr5650[4], 0, 1, apicid_sr5650, 21); /* NIC */ - smp_write_pci_intsrc(mc, mp_INT, bus_sr5650[11], 0, 0, apicid_sr5650, 8); - smp_write_pci_intsrc(mc, mp_INT, bus_sr5650[11], 0, 1, apicid_sr5650, 9); /* card behind dev11 */ - smp_write_pci_intsrc(mc, mp_INT, bus_sr5650[12], 0, 0, apicid_sr5650, 12); - smp_write_pci_intsrc(mc, mp_INT, bus_sr5650[12], 0, 1, apicid_sr5650, 13); /* card behind dev12 */ - - /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ - IO_LOCAL_INT(mp_ExtINT, 0x0, MP_APIC_ALL, 0x0); - IO_LOCAL_INT(mp_NMI, 0x0, MP_APIC_ALL, 0x1); - /* There is no extension information... */ - - /* Compute the checksums */ - return mptable_finalize(mc); -} - -unsigned long write_smp_table(unsigned long addr) -{ - void *v; - v = smp_write_floating_table(addr, 0); - return (unsigned long)smp_write_config_table(v); -} diff --git a/src/mainboard/supermicro/h8scm_fam10/resourcemap.c b/src/mainboard/supermicro/h8scm_fam10/resourcemap.c deleted file mode 100644 index 80d2d9d05c..0000000000 --- a/src/mainboard/supermicro/h8scm_fam10/resourcemap.c +++ /dev/null @@ -1,279 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2010 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - - - -#include -#include - -void setup_mb_resource_map(void) -{ - static const unsigned int register_values[] = { - /* Careful set limit registers before base registers which contain the enables */ - /* DRAM Limit i Registers - * F1:0x44 i = 0 - * F1:0x4C i = 1 - * F1:0x54 i = 2 - * F1:0x5C i = 3 - * F1:0x64 i = 4 - * F1:0x6C i = 5 - * F1:0x74 i = 6 - * F1:0x7C i = 7 - * [ 2: 0] Destination Node ID - * 000 = Node 0 - * 001 = Node 1 - * 010 = Node 2 - * 011 = Node 3 - * 100 = Node 4 - * 101 = Node 5 - * 110 = Node 6 - * 111 = Node 7 - * [ 7: 3] Reserved - * [10: 8] Interleave select - * specifies the values of A[14:12] to use with interleave enable. - * [15:11] Reserved - * [31:16] DRAM Limit Address i Bits 39-24 - * This field defines the upper address bits of a 40 bit address - * that define the end of the DRAM region. - */ -// ADDRMAP_REG(0x44), 0x0000f8f8, 0x00000000, // Don't touch it, we need it for CONFIG_CAR_FAM10 - ADDRMAP_REG(0x4C), 0x0000f8f8, 0x00000001, - ADDRMAP_REG(0x54), 0x0000f8f8, 0x00000002, - ADDRMAP_REG(0x5C), 0x0000f8f8, 0x00000003, - ADDRMAP_REG(0x64), 0x0000f8f8, 0x00000004, - ADDRMAP_REG(0x6C), 0x0000f8f8, 0x00000005, - ADDRMAP_REG(0x74), 0x0000f8f8, 0x00000006, - ADDRMAP_REG(0x7C), 0x0000f8f8, 0x00000007, - /* DRAM Base i Registers - * F1:0x40 i = 0 - * F1:0x48 i = 1 - * F1:0x50 i = 2 - * F1:0x58 i = 3 - * F1:0x60 i = 4 - * F1:0x68 i = 5 - * F1:0x70 i = 6 - * F1:0x78 i = 7 - * [ 0: 0] Read Enable - * 0 = Reads Disabled - * 1 = Reads Enabled - * [ 1: 1] Write Enable - * 0 = Writes Disabled - * 1 = Writes Enabled - * [ 7: 2] Reserved - * [10: 8] Interleave Enable - * 000 = No interleave - * 001 = Interleave on A[12] (2 nodes) - * 010 = reserved - * 011 = Interleave on A[12] and A[14] (4 nodes) - * 100 = reserved - * 101 = reserved - * 110 = reserved - * 111 = Interleve on A[12] and A[13] and A[14] (8 nodes) - * [15:11] Reserved - * [13:16] DRAM Base Address i Bits 39-24 - * This field defines the upper address bits of a 40-bit address - * that define the start of the DRAM region. - */ -// ADDRMAP_REG(0x40), 0x0000f8fc, 0x00000000,// don't touch it, we need it for CONFIG_CAR_FAM10 - ADDRMAP_REG(0x48), 0x0000f8fc, 0x00000000, - ADDRMAP_REG(0x50), 0x0000f8fc, 0x00000000, - ADDRMAP_REG(0x58), 0x0000f8fc, 0x00000000, - ADDRMAP_REG(0x60), 0x0000f8fc, 0x00000000, - ADDRMAP_REG(0x68), 0x0000f8fc, 0x00000000, - ADDRMAP_REG(0x70), 0x0000f8fc, 0x00000000, - ADDRMAP_REG(0x78), 0x0000f8fc, 0x00000000, - - /* Memory-Mapped I/O Limit i Registers - * F1:0x84 i = 0 - * F1:0x8C i = 1 - * F1:0x94 i = 2 - * F1:0x9C i = 3 - * F1:0xA4 i = 4 - * F1:0xAC i = 5 - * F1:0xB4 i = 6 - * F1:0xBC i = 7 - * [ 2: 0] Destination Node ID - * 000 = Node 0 - * 001 = Node 1 - * 010 = Node 2 - * 011 = Node 3 - * 100 = Node 4 - * 101 = Node 5 - * 110 = Node 6 - * 111 = Node 7 - * [ 3: 3] Reserved - * [ 5: 4] Destination Link ID - * 00 = Link 0 - * 01 = Link 1 - * 10 = Link 2 - * 11 = Reserved - * [ 6: 6] Reserved - * [ 7: 7] Non-Posted - * 0 = CPU writes may be posted - * 1 = CPU writes must be non-posted - * [31: 8] Memory-Mapped I/O Limit Address i (39-16) - * This field defines the upp address bits of a 40-bit address that - * defines the end of a memory-mapped I/O region n - */ - ADDRMAP_REG(0x84), 0x00000048, 0x00000000, - ADDRMAP_REG(0x8C), 0x00000048, 0x00000000, - ADDRMAP_REG(0x94), 0x00000048, 0x00000000, - ADDRMAP_REG(0x9C), 0x00000048, 0x00000000, - ADDRMAP_REG(0xA4), 0x00000048, 0x00000000, - ADDRMAP_REG(0xAC), 0x00000048, 0x00000000, - ADDRMAP_REG(0xB4), 0x00000048, 0x00000000, -// ADDRMAP_REG(0xBC), 0x00000048, 0x00ffff00, - - /* Memory-Mapped I/O Base i Registers - * F1:0x80 i = 0 - * F1:0x88 i = 1 - * F1:0x90 i = 2 - * F1:0x98 i = 3 - * F1:0xA0 i = 4 - * F1:0xA8 i = 5 - * F1:0xB0 i = 6 - * F1:0xB8 i = 7 - * [ 0: 0] Read Enable - * 0 = Reads disabled - * 1 = Reads Enabled - * [ 1: 1] Write Enable - * 0 = Writes disabled - * 1 = Writes Enabled - * [ 2: 2] Cpu Disable - * 0 = Cpu can use this I/O range - * 1 = Cpu requests do not use this I/O range - * [ 3: 3] Lock - * 0 = base/limit registers i are read/write - * 1 = base/limit registers i are read-only - * [ 7: 4] Reserved - * [31: 8] Memory-Mapped I/O Base Address i (39-16) - * This field defines the upper address bits of a 40bit address - * that defines the start of memory-mapped I/O region i - */ - ADDRMAP_REG(0x80), 0x000000f0, 0x00000000, - ADDRMAP_REG(0x88), 0x000000f0, 0x00000000, - ADDRMAP_REG(0x90), 0x000000f0, 0x00000000, - ADDRMAP_REG(0x98), 0x000000f0, 0x00000000, - ADDRMAP_REG(0xA0), 0x000000f0, 0x00000000, - ADDRMAP_REG(0xA8), 0x000000f0, 0x00000000, - ADDRMAP_REG(0xB0), 0x000000f0, 0x00000000, -// ADDRMAP_REG(0xB8), 0x000000f0, 0x00fc0003, - - /* PCI I/O Limit i Registers - * F1:0xC4 i = 0 - * F1:0xCC i = 1 - * F1:0xD4 i = 2 - * F1:0xDC i = 3 - * [ 2: 0] Destination Node ID - * 000 = Node 0 - * 001 = Node 1 - * 010 = Node 2 - * 011 = Node 3 - * 100 = Node 4 - * 101 = Node 5 - * 110 = Node 6 - * 111 = Node 7 - * [ 3: 3] Reserved - * [ 5: 4] Destination Link ID - * 00 = Link 0 - * 01 = Link 1 - * 10 = Link 2 - * 11 = reserved - * [11: 6] Reserved - * [24:12] PCI I/O Limit Address i - * This field defines the end of PCI I/O region n - * [31:25] Reserved - */ -// ADDRMAP_REG(0xC4), 0xFE000FC8, 0x01fff000, - ADDRMAP_REG(0xCC), 0xFE000FC8, 0x00000000, - ADDRMAP_REG(0xD4), 0xFE000FC8, 0x00000000, - ADDRMAP_REG(0xDC), 0xFE000FC8, 0x00000000, - - /* PCI I/O Base i Registers - * F1:0xC0 i = 0 - * F1:0xC8 i = 1 - * F1:0xD0 i = 2 - * F1:0xD8 i = 3 - * [ 0: 0] Read Enable - * 0 = Reads Disabled - * 1 = Reads Enabled - * [ 1: 1] Write Enable - * 0 = Writes Disabled - * 1 = Writes Enabled - * [ 3: 2] Reserved - * [ 4: 4] VGA Enable - * 0 = VGA matches Disabled - * 1 = matches all address < 64K and where A[9:0] is in the - * range 3B0-3BB or 3C0-3DF independen of the base & limit registers - * [ 5: 5] ISA Enable - * 0 = ISA matches Disabled - * 1 = Blocks address < 64K and in the last 768 bytes of eack 1K block - * from matching agains this base/limit pair - * [11: 6] Reserved - * [24:12] PCI I/O Base i - * This field defines the start of PCI I/O region n - * [31:25] Reserved - */ -// ADDRMAP_REG(0xC0), 0xFE000FCC, 0x00000003, - ADDRMAP_REG(0xC8), 0xFE000FCC, 0x00000000, - ADDRMAP_REG(0xD0), 0xFE000FCC, 0x00000000, - ADDRMAP_REG(0xD8), 0xFE000FCC, 0x00000000, - - /* Config Base and Limit i Registers - * F1:0xE0 i = 0 - * F1:0xE4 i = 1 - * F1:0xE8 i = 2 - * F1:0xEC i = 3 - * [ 0: 0] Read Enable - * 0 = Reads Disabled - * 1 = Reads Enabled - * [ 1: 1] Write Enable - * 0 = Writes Disabled - * 1 = Writes Enabled - * [ 2: 2] Device Number Compare Enable - * 0 = The ranges are based on bus number - * 1 = The ranges are ranges of devices on bus 0 - * [ 3: 3] Reserved - * [ 6: 4] Destination Node - * 000 = Node 0 - * 001 = Node 1 - * 010 = Node 2 - * 011 = Node 3 - * 100 = Node 4 - * 101 = Node 5 - * 110 = Node 6 - * 111 = Node 7 - * [ 7: 7] Reserved - * [ 9: 8] Destination Link - * 00 = Link 0 - * 01 = Link 1 - * 10 = Link 2 - * 11 - Reserved - * [15:10] Reserved - * [23:16] Bus Number Base i - * This field defines the lowest bus number in configuration region i - * [31:24] Bus Number Limit i - * This field defines the highest bus number in configuration regin i - */ -// ADDRMAP_REG(0xE0), 0x0000FC88, 0x06000003, // AMD 8111 on link0 of CPU 0 - ADDRMAP_REG(0xE4), 0x0000FC88, 0x00000000, - ADDRMAP_REG(0xE8), 0x0000FC88, 0x00000000, - ADDRMAP_REG(0xEC), 0x0000FC88, 0x00000000, - }; - - int max; - max = ARRAY_SIZE(register_values); - setup_resource_map(register_values, max); -} diff --git a/src/mainboard/supermicro/h8scm_fam10/romstage.c b/src/mainboard/supermicro/h8scm_fam10/romstage.c deleted file mode 100644 index 302e86f4e8..0000000000 --- a/src/mainboard/supermicro/h8scm_fam10/romstage.c +++ /dev/null @@ -1,238 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2010 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -//#define SYSTEM_TYPE 0 /* SERVER */ //FIXME SERVER enable ECC, cause linux hang -#define SYSTEM_TYPE 1 /* DESKTOP */ -//#define SYSTEM_TYPE 2 /* MOBILE */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include "cpu/amd/quadcore/quadcore.c" - -int spd_read_byte(unsigned int device, unsigned int address); - - -int spd_read_byte(u32 device, u32 address) -{ - return do_smbus_read_byte(SMBUS_IO_BASE, device, address); -} - -void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) -{ - struct sys_info *sysinfo = get_sysinfo(); - static const u8 spd_addr[] = { - RC00, 0x52, 0x53, 0, 0, 0x50, 0x51, 0, 0, - //RC00, DIMM2, DIMM3, 0, 0, DIMM0, DIMM1, 0, 0, - }; - u32 bsp_apicid = 0; - u32 val; - msr_t msr; - - timestamp_init(timestamp_get()); - timestamp_add_now(TS_START_ROMSTAGE); - - if (!cpu_init_detectedx && boot_cpu()) { - /* Nothing special needs to be done to find bus 0 */ - /* Allow the HT devices to be found */ - /* mov bsp to bus 0xff when > 8 nodes */ - set_bsp_node_CHtExtNodeCfgEn(); - enumerate_ht_chain(); - - /* SR56x0 pcie bridges block pci_locate_device() before pcie training. - * disable all pcie bridges on SR56x0 to work around it - */ - sr5650_disable_pcie_bridge(); - sb7xx_51xx_lpc_port80(); - } - - post_code(0x30); - - if (bist == 0) { - bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo); /* mmconf is inited in init_cpus */ - /* All cores run this but the BSP(node0,core0) is the only core that returns. */ - } - - post_code(0x32); - - enable_sr5650_dev8(); - sb7xx_51xx_lpc_init(); - - sb7xx_51xx_enable_wideio(0, 0x1600); - - wpcm450_enable_dev(WPCM450_SP1, 0x164E, CONFIG_TTYS0_BASE); - - sb7xx_51xx_disable_wideio(0); - - console_init(); - - /* Halt if there was a built in self test failure */ - report_bist_failure(bist); - - // Load MPB - val = cpuid_eax(1); - printk(BIOS_DEBUG, "BSP Family_Model: %08x\n", val); - printk(BIOS_DEBUG, "*sysinfo range: [%p,%p]\n",sysinfo,sysinfo+1); - printk(BIOS_DEBUG, "bsp_apicid = %02x\n", bsp_apicid); - printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx); - - /* Setup sysinfo defaults */ - set_sysinfo_in_ram(0); - - update_microcode(val); - - post_code(0x33); - - cpuSetAMDMSR(0); - post_code(0x34); - - /* TODO: The Kernel must support 12 processor, otherwise the interrupt - * can not work correctly. */ - amd_ht_init(sysinfo); - post_code(0x35); - - /* Setup nodes PCI space and start core 0 AP init. */ - finalize_node_setup(sysinfo); - - /* Setup any mainboard PCI settings etc. */ - setup_mb_resource_map(); - post_code(0x36); - - /* wait for all the APs core0 started by finalize_node_setup. */ - /* FIXME: A bunch of cores are going to start output to serial at once. - It would be nice to fixup prink spinlocks for ROM XIP mode. - I think it could be done by putting the spinlock flag in the cache - of the BSP located right after sysinfo. - */ - wait_all_core0_started(); - -#if CONFIG(LOGICAL_CPUS) - /* Core0 on each node is configured. Now setup any additional cores. */ - printk(BIOS_DEBUG, "start_other_cores()\n"); - start_other_cores(bsp_apicid); - post_code(0x37); - wait_all_other_cores_started(bsp_apicid); -#endif - - post_code(0x38); - - /* run _early_setup before soft-reset. */ - sr5650_early_setup(); - sb7xx_51xx_early_setup(); - -#if CONFIG(SET_FIDVID) - msr = rdmsr(MSR_COFVID_STS); - printk(BIOS_DEBUG, "\nBegin FIDVID MSR 0xc0010071 0x%08x 0x%08x\n", msr.hi, msr.lo); - - /* FIXME: The sb fid change may survive the warm reset and only - need to be done once.*/ - enable_fid_change_on_sb(sysinfo->sbbusn, sysinfo->sbdn); - - post_code(0x39); - - if (!warm_reset_detect(0)) { // BSP is node 0 - init_fidvid_bsp(bsp_apicid, sysinfo->nodes); - } else { - init_fidvid_stage2(bsp_apicid, 0); // BSP is node 0 - } - - post_code(0x3A); - - /* show final fid and vid */ - msr = rdmsr(MSR_COFVID_STS); - printk(BIOS_DEBUG, "End FIDVIDMSR 0xc0010071 0x%08x 0x%08x\n", msr.hi, msr.lo); -#endif - - sr5650_htinit(); - - /* Reset for HT, FIDVID, PLL and errata changes to take affect. */ - if (!warm_reset_detect(0)) { - printk(BIOS_INFO, "...WARM RESET...\n\n\n"); - soft_reset(); - die("After soft_reset - shouldn't see this message!!!\n"); - } - - post_code(0x3B); - - /* It's the time to set ctrl in sysinfo now; */ - printk(BIOS_DEBUG, "fill_mem_ctrl()\n"); - fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr); - - post_code(0x40); - - raminit_amdmct(sysinfo); - - cbmem_initialize_empty(); - post_code(0x41); - - amdmct_cbmem_store_info(sysinfo); - - sr5650_before_pci_init(); - sb7xx_51xx_before_pci_init(); - - post_code(0x42); -} - -/** - * BOOL AMD_CB_ManualBUIDSwapList(u8 Node, u8 Link, u8 **List) - * Description: - * This routine is called every time a non-coherent chain is processed. - * BUID assignment may be controlled explicitly on a non-coherent chain. Provide a - * swap list. The first part of the list controls the BUID assignment and the - * second part of the list provides the device to device linking. Device orientation - * can be detected automatically, or explicitly. See documentation for more details. - * - * Automatic non-coherent init assigns BUIDs starting at 1 and incrementing sequentially - * based on each device's unit count. - * - * Parameters: - * @param[in] node = The node on which this chain is located - * @param[in] link = The link on the host for this chain - * @param[out] List = supply a pointer to a list - */ -BOOL AMD_CB_ManualBUIDSwapList (u8 node, u8 link, const u8 **List) -{ - static const u8 swaplist[] = { 0xFF, CONFIG_HT_CHAIN_UNITID_BASE, CONFIG_HT_CHAIN_END_UNITID_BASE, 0xFF }; - /* If the BUID was adjusted in early_ht we need to do the manual override */ - if ((CONFIG_HT_CHAIN_UNITID_BASE != 0) && (CONFIG_HT_CHAIN_END_UNITID_BASE != 0)) { - printk(BIOS_DEBUG, "AMD_CB_ManualBUIDSwapList()\n"); - if ((node == 0) && (link == 0)) { /* BSP SB link */ - *List = swaplist; - return 1; - } - } - - return 0; -} diff --git a/src/mainboard/tyan/Kconfig b/src/mainboard/tyan/Kconfig deleted file mode 100644 index 203a56a35f..0000000000 --- a/src/mainboard/tyan/Kconfig +++ /dev/null @@ -1,30 +0,0 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2009 Uwe Hermann -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; version 2 of the License. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## -if VENDOR_TYAN - -choice - prompt "Mainboard model" - -source "src/mainboard/tyan/*/Kconfig.name" - -endchoice - -source "src/mainboard/tyan/*/Kconfig" - -config MAINBOARD_VENDOR - string - default "Tyan" - -endif # VENDOR_TYAN diff --git a/src/mainboard/tyan/Kconfig.name b/src/mainboard/tyan/Kconfig.name deleted file mode 100644 index ee21057adc..0000000000 --- a/src/mainboard/tyan/Kconfig.name +++ /dev/null @@ -1,2 +0,0 @@ -config VENDOR_TYAN - bool "Tyan" diff --git a/src/mainboard/tyan/s2912_fam10/Kconfig b/src/mainboard/tyan/s2912_fam10/Kconfig deleted file mode 100644 index eeb2db6a75..0000000000 --- a/src/mainboard/tyan/s2912_fam10/Kconfig +++ /dev/null @@ -1,65 +0,0 @@ -if BOARD_TYAN_S2912_FAM10 - -config BOARD_SPECIFIC_OPTIONS - def_bool y - select CPU_AMD_SOCKET_F_1207 - select DIMM_DDR2 - select DIMM_REGISTERED - select NORTHBRIDGE_AMD_AMDFAM10 - select SOUTHBRIDGE_NVIDIA_MCP55 - select HT_CHAIN_DISTRIBUTE - select MCP55_USE_NIC - select SUPERIO_WINBOND_W83627HF - select PARALLEL_CPU_INIT - select HAVE_OPTION_TABLE - select HAVE_PIRQ_TABLE - select HAVE_MP_TABLE - select LIFT_BSP_APIC_ID - select BOARD_ROMSIZE_KB_1024 - select ENABLE_APIC_EXT_ID - -config MAINBOARD_DIR - string - default tyan/s2912_fam10 - -config DCACHE_RAM_BASE - hex - default 0xc4000 - -config DCACHE_RAM_SIZE - hex - default 0x0c000 - -config APIC_ID_OFFSET - hex - default 0x0 - -config MAINBOARD_PART_NUMBER - string - default "S2912 (Fam10)" - -config MAX_CPUS - int - default 12 - -config MAX_PHYSICAL_CPUS - int - default 2 - -config HT_CHAIN_UNITID_BASE - hex - default 0x1 - -config HT_CHAIN_END_UNITID_BASE - hex - default 0x20 - -config IRQ_SLOT_COUNT - int - default 11 - -config MCP55_PCI_E_X_0 - int - default 1 - -endif # BOARD_TYAN_S2912_FAM10 diff --git a/src/mainboard/tyan/s2912_fam10/Kconfig.name b/src/mainboard/tyan/s2912_fam10/Kconfig.name deleted file mode 100644 index 711373266c..0000000000 --- a/src/mainboard/tyan/s2912_fam10/Kconfig.name +++ /dev/null @@ -1,2 +0,0 @@ -config BOARD_TYAN_S2912_FAM10 - bool "S2912 Fam10 (Thunder n3600R)" diff --git a/src/mainboard/tyan/s2912_fam10/Makefile.inc b/src/mainboard/tyan/s2912_fam10/Makefile.inc deleted file mode 100644 index 91d4b39c32..0000000000 --- a/src/mainboard/tyan/s2912_fam10/Makefile.inc +++ /dev/null @@ -1,16 +0,0 @@ -# -# This file is part of the coreboot project. -# -# This program is free software; you can redistribute it and/or modify -# it under the terms of the GNU General Public License as published by -# the Free Software Foundation; version 2 of the License. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# - -romstage-y += resourcemap.c - -ramstage-y += get_bus_conf.c diff --git a/src/mainboard/tyan/s2912_fam10/board_info.txt b/src/mainboard/tyan/s2912_fam10/board_info.txt deleted file mode 100644 index 3a5cfe5eba..0000000000 --- a/src/mainboard/tyan/s2912_fam10/board_info.txt +++ /dev/null @@ -1,2 +0,0 @@ -Category: server -Release year: 2007 diff --git a/src/mainboard/tyan/s2912_fam10/cmos.layout b/src/mainboard/tyan/s2912_fam10/cmos.layout deleted file mode 100644 index 42b34aeec0..0000000000 --- a/src/mainboard/tyan/s2912_fam10/cmos.layout +++ /dev/null @@ -1,101 +0,0 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2015 Timothy Pearson , Raptor Engineering -## Copyright (C) 2007 AMD -## Written by Yinghai Lu for AMD. -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; either version 2 of the License, or -## (at your option) any later version. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## - -entries - -0 384 r 0 reserved_memory -384 1 e 4 boot_option -388 4 h 0 reboot_counter -#393 8 unused -401 1 e 1 interleave_chip_selects -402 1 e 1 interleave_nodes -403 1 e 1 interleave_memory_channels -404 2 e 8 max_mem_clock -406 1 e 2 multi_core -412 4 e 6 debug_level -416 5 e 10 ecc_scrub_rate -440 4 e 9 slow_cpu -444 1 e 1 nmi -445 1 e 1 gart -446 1 e 1 power_on_after_fail -456 1 e 1 ECC_memory -457 1 e 1 ECC_redirection -728 256 h 0 user_data -984 16 h 0 check_sum -# Reserve the extended AMD configuration registers -1000 24 r 0 amd_reserved - - - -enumerations - -#ID value text -1 0 Disable -1 1 Enable -2 0 Enable -2 1 Disable -4 0 Fallback -4 1 Normal -6 0 Emergency -6 1 Alert -6 2 Critical -6 3 Error -6 4 Warning -6 5 Notice -6 6 Information -6 7 Debug -6 8 Spew -8 0 DDR2-800 -8 1 DDR2-667 -8 2 DDR2-533 -8 3 DDR2-400 -9 0 off -9 1 87.5% -9 2 75.0% -9 3 62.5% -9 4 50.0% -9 5 37.5% -9 6 25.0% -9 7 12.5% -10 0 Disabled -10 1 40ns -10 2 80ns -10 3 160ns -10 4 320ns -10 5 640ns -10 6 1.28us -10 7 2.56us -10 8 5.12us -10 9 10.2us -10 10 20.5us -10 11 41us -10 12 81.9us -10 13 163.8us -10 14 327.7us -10 15 655.4us -10 16 1.31ms -10 17 2.62ms -10 18 5.24ms -10 19 10.49ms -10 20 20.97sms -10 21 42ms -10 22 84ms - -checksums - -checksum 392 983 984 diff --git a/src/mainboard/tyan/s2912_fam10/devicetree.cb b/src/mainboard/tyan/s2912_fam10/devicetree.cb deleted file mode 100644 index e49e16b94e..0000000000 --- a/src/mainboard/tyan/s2912_fam10/devicetree.cb +++ /dev/null @@ -1,141 +0,0 @@ -chip northbridge/amd/amdfam10/root_complex # Root complex - device cpu_cluster 0 on # (L)APIC cluster - chip cpu/amd/socket_F_1207 # CPU socket - device lapic 0 on end # Local APIC of the CPU - end - end - device domain 0 on # PCI domain - subsystemid 0x10f1 0x2912 inherit - chip northbridge/amd/amdfam10 # Northbridge / RAM controller - device pci 18.0 on end - device pci 18.0 on end - device pci 18.0 on # SB on link 2 - chip southbridge/nvidia/mcp55 # Southbridge - device pci 0.0 on end # HT - device pci 1.0 on # LPC - chip superio/winbond/w83627hf # Super I/O - device pnp 2e.0 off # Floppy - io 0x60 = 0x3f0 - irq 0x70 = 6 - drq 0x74 = 2 - end - device pnp 2e.1 off # Parallel port - io 0x60 = 0x378 - irq 0x70 = 7 - end - device pnp 2e.2 on # Com1 - io 0x60 = 0x3f8 - irq 0x70 = 4 - end - device pnp 2e.3 on # Com2 - io 0x60 = 0x2f8 - irq 0x70 = 3 - end - device pnp 2e.5 on # PS/2 keyboard - io 0x60 = 0x60 - io 0x62 = 0x64 - irq 0x70 = 1 - irq 0x72 = 12 - end - device pnp 2e.6 off # SFI - io 0x62 = 0x100 - end - device pnp 2e.7 off # GPIO, game port, MIDI - io 0x60 = 0x220 - io 0x62 = 0x300 - irq 0x70 = 9 - end - device pnp 2e.8 off end # WDTO PLED - device pnp 2e.9 off end # GPIO SUSLED - device pnp 2e.a off end # ACPI - device pnp 2e.b on # Hardware monitor - io 0x60 = 0x290 - irq 0x70 = 5 - end - end - end - device pci 1.1 on # SM 0 - chip drivers/generic/generic # DIMM 0-0-0 - device i2c 50 on end - end - chip drivers/generic/generic # DIMM 0-0-1 - device i2c 51 on end - end - chip drivers/generic/generic # DIMM 0-1-0 - device i2c 52 on end - end - chip drivers/generic/generic # DIMM 0-1-1 - device i2c 53 on end - end - chip drivers/generic/generic # DIMM 1-0-0 - device i2c 54 on end - end - chip drivers/generic/generic # DIMM 1-0-1 - device i2c 55 on end - end - chip drivers/generic/generic # DIMM 1-1-0 - device i2c 56 on end - end - chip drivers/generic/generic # DIMM 1-1-1 - device i2c 57 on end - end - end - device pci 1.1 on # SM 1 - # PCI device SMBus address will - # depend on addon PCI device, do - # we need to scan_smbus_bus? - # chip drivers/generic/generic # PCIXA slot 1 - # device i2c 50 on end - # end - # chip drivers/generic/generic # PCIXB slot 1 - # device i2c 51 on end - # end - # chip drivers/generic/generic # PCIXB slot 2 - # device i2c 52 on end - # end - # chip drivers/generic/generic # PCI slot 1 - # device i2c 53 on end - # end - # chip drivers/generic/generic # Master MCP55 PCI-E - # device i2c 54 on end - # end - # chip drivers/generic/generic # Slave MCP55 PCI-E - # device i2c 55 on end - # end - chip drivers/generic/generic # MAC EEPROM - device i2c 51 on end - end - end - device pci 2.0 on end # USB 1.1 - device pci 2.1 on end # USB 2 - device pci 4.0 on end # IDE - device pci 5.0 on end # SATA 0 - device pci 5.1 on end # SATA 1 - device pci 5.2 on end # SATA 2 - device pci 6.0 on # PCI - device pci 4.0 on end - end - device pci 6.1 off end # AZA - device pci 8.0 on end # NIC - device pci 9.0 on end # NIC - device pci a.0 on end # PCI E 5 - device pci b.0 off end # PCI E 4 - device pci c.0 off end # PCI E 3 - device pci d.0 on end # PCI E 2 - device pci e.0 off end # PCI E 1 - device pci f.0 on end # PCI E 0 - register "ide0_enable" = "1" - register "sata0_enable" = "1" - register "sata1_enable" = "1" - # 1: SMBus under 2e.8, 2: SM0 3: SM1 - register "mac_eeprom_smbus" = "3" - register "mac_eeprom_addr" = "0x51" - end - end - device pci 18.1 on end - device pci 18.2 on end - device pci 18.3 on end - device pci 18.4 on end - end - end -end diff --git a/src/mainboard/tyan/s2912_fam10/get_bus_conf.c b/src/mainboard/tyan/s2912_fam10/get_bus_conf.c deleted file mode 100644 index 7155813394..0000000000 --- a/src/mainboard/tyan/s2912_fam10/get_bus_conf.c +++ /dev/null @@ -1,76 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007 AMD - * Written by Yinghai Lu for AMD. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include -#include -#include -#include - -#include - -#include -#include "mb_sysconf.h" - -// Global variables for MB layouts and these will be shared by irqtable mptable and acpi_tables -struct mb_sysconf_t mb_sysconf; - -void get_bus_conf(void) -{ - unsigned int apicid_base; - struct mb_sysconf_t *m; - - struct device *dev; - int i; - - sysconf.mb = &mb_sysconf; - - m = sysconf.mb; - memset(m, 0, sizeof(struct mb_sysconf_t)); - - get_default_pci1234(32); - - sysconf.sbdn = (sysconf.hcdn[0] & 0xff); // first byte of first chain - m->bus_mcp55[0] = (sysconf.pci1234[0] >> 12) & 0xff; - - /* MCP55 */ - dev = dev_find_slot(m->bus_mcp55[0], PCI_DEVFN(sysconf.sbdn + 0x06,0)); - if (dev) { - m->bus_mcp55[1] = pci_read_config8(dev, PCI_SECONDARY_BUS); - } - else { - printk(BIOS_DEBUG, "ERROR - could not find PCI 1:%02x.0, using defaults\n", sysconf.sbdn + 0x06); - } - - for(i = 2; i < 8; i++) { - dev = dev_find_slot(m->bus_mcp55[0], PCI_DEVFN(sysconf.sbdn + 0x0a + i - 2, 0)); - if (dev) { - m->bus_mcp55[i] = pci_read_config8(dev, PCI_SECONDARY_BUS); - } - else { - printk(BIOS_DEBUG, "ERROR - could not find PCI %02x:%02x.0, using defaults\n", m->bus_mcp55[0], sysconf.sbdn + 0x0a + i - 2); - } - } - -/*I/O APICs: APIC ID Version State Address*/ - if (CONFIG(LOGICAL_CPUS)) - apicid_base = get_apicid_base(1); - else - apicid_base = CONFIG_MAX_PHYSICAL_CPUS; - m->apicid_mcp55 = apicid_base+0; -} diff --git a/src/mainboard/tyan/s2912_fam10/irq_tables.c b/src/mainboard/tyan/s2912_fam10/irq_tables.c deleted file mode 100644 index 69327dcafa..0000000000 --- a/src/mainboard/tyan/s2912_fam10/irq_tables.c +++ /dev/null @@ -1,137 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007 AMD - * Written by Yinghai Lu for AMD. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include -#include -#include - -#include -#include "mb_sysconf.h" - -static void write_pirq_info(struct irq_info *pirq_info, uint8_t bus, - uint8_t devfn, uint8_t link0, uint16_t bitmap0, - uint8_t link1, uint16_t bitmap1, uint8_t link2, - uint16_t bitmap2, uint8_t link3, uint16_t bitmap3, - uint8_t slot, uint8_t rfu) -{ - pirq_info->bus = bus; - pirq_info->devfn = devfn; - pirq_info->irq[0].link = link0; - pirq_info->irq[0].bitmap = bitmap0; - pirq_info->irq[1].link = link1; - pirq_info->irq[1].bitmap = bitmap1; - pirq_info->irq[2].link = link2; - pirq_info->irq[2].bitmap = bitmap2; - pirq_info->irq[3].link = link3; - pirq_info->irq[3].bitmap = bitmap3; - pirq_info->slot = slot; - pirq_info->rfu = rfu; -} - -unsigned long write_pirq_routing_table(unsigned long addr) -{ - - struct irq_routing_table *pirq; - struct irq_info *pirq_info; - unsigned int slot_num; - uint8_t *v; - struct mb_sysconf_t *m; - unsigned int sbdn; - - uint8_t sum = 0; - int i; - - sbdn = sysconf.sbdn; - m = sysconf.mb; - - /* Align the table to be 16 byte aligned. */ - addr += 15; - addr &= ~15; - - /* This table must be between 0xf0000 & 0x100000 */ - printk(BIOS_INFO, "Writing IRQ routing tables to 0x%lx...", addr); - - pirq = (void *)(addr); - v = (uint8_t *) (addr); - - pirq->signature = PIRQ_SIGNATURE; - pirq->version = PIRQ_VERSION; - - pirq->rtr_bus = m->bus_mcp55[0]; - pirq->rtr_devfn = PCI_DEVFN(sbdn + 6, 0); - - pirq->exclusive_irqs = 0; - - pirq->rtr_vendor = 0x10de; - pirq->rtr_device = 0x0370; - - pirq->miniport_data = 0; - - memset(pirq->rfu, 0, sizeof(pirq->rfu)); - - pirq_info = (void *)(&pirq->checksum + 1); - slot_num = 0; -//pci bridge - write_pirq_info(pirq_info, m->bus_mcp55[0], PCI_DEVFN(sbdn + 6, 0), 0x1, - 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, 0); - pirq_info++; - slot_num++; - - for (i = 1; i < sysconf.hc_possible_num; i++) { - if (!(sysconf.pci1234[i] & 0x1)) - continue; - unsigned int busn = (sysconf.pci1234[i] >> 12) & 0xff; - unsigned int devn = sysconf.hcdn[i] & 0xff; - - write_pirq_info(pirq_info, busn, PCI_DEVFN(devn, 0), 0x1, 0xdef8, - 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, 0); - pirq_info++; - slot_num++; - } - -#if CONFIG_CBB - write_pirq_info(pirq_info, CONFIG_CBB, PCI_DEVFN(0, 0), 0x1, 0xdef8, 0x2, - 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, 0); - pirq_info++; - slot_num++; - if (sysconf.nodes > 32) { - write_pirq_info(pirq_info, CONFIG_CBB - 1, PCI_DEVFN(0, 0), 0x1, - 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, - 0, 0); - pirq_info++; - slot_num++; - } -#endif - - pirq->size = 32 + 16 * slot_num; - - for (i = 0; i < pirq->size; i++) - sum += v[i]; - - sum = pirq->checksum - sum; - - if (sum != pirq->checksum) { - pirq->checksum = sum; - } - - printk(BIOS_INFO, "done.\n"); - - return (unsigned long)pirq_info; - -} diff --git a/src/mainboard/tyan/s2912_fam10/mb_sysconf.h b/src/mainboard/tyan/s2912_fam10/mb_sysconf.h deleted file mode 100644 index 1a287c6a8a..0000000000 --- a/src/mainboard/tyan/s2912_fam10/mb_sysconf.h +++ /dev/null @@ -1,26 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007 AMD - * Written by Yinghai Lu for AMD. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef MB_SYSCONF_H -#define MB_SYSCONF_H - -struct mb_sysconf_t { - unsigned char bus_mcp55[8]; //1 - unsigned int apicid_mcp55; -}; - -#endif diff --git a/src/mainboard/tyan/s2912_fam10/mptable.c b/src/mainboard/tyan/s2912_fam10/mptable.c deleted file mode 100644 index 5563aef2cf..0000000000 --- a/src/mainboard/tyan/s2912_fam10/mptable.c +++ /dev/null @@ -1,112 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007 AMD - * Written by Yinghai Lu for AMD. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include -#include -#include -#include "mb_sysconf.h" - -static void *smp_write_config_table(void *v) -{ - struct mp_config_table *mc; - struct mb_sysconf_t *m; - unsigned int sbdn; - int i, j, bus_isa; - - mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); - - mptable_init(mc, LOCAL_APIC_ADDR); - - smp_write_processors(mc); - - sbdn = sysconf.sbdn; - m = sysconf.mb; - - mptable_write_buses(mc, NULL, &bus_isa); - -/*I/O APICs: APIC ID Version State Address*/ - { - struct device *dev; - struct resource *res; - uint32_t dword; - - dev = dev_find_slot(m->bus_mcp55[0], PCI_DEVFN(sbdn+ 0x1,0)); - if (dev) { - res = find_resource(dev, PCI_BASE_ADDRESS_1); - if (res) { - smp_write_ioapic(mc, m->apicid_mcp55, 0x11, - res2mmio(res, 0, 0)); - } - - dword = 0x43c6c643; - pci_write_config32(dev, 0x7c, dword); - - dword = 0x81001a00; - pci_write_config32(dev, 0x80, dword); - - dword = 0xd00002d2; - pci_write_config32(dev, 0x84, dword); - - } - - - } - - mptable_add_isa_interrupts(mc, bus_isa, m->apicid_mcp55, 0); - - /*I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ - smp_write_pci_intsrc(mc, mp_INT, m->bus_mcp55[0], sbdn + 1, 1, m->apicid_mcp55, 0xa); - - smp_write_pci_intsrc(mc, mp_INT, m->bus_mcp55[0], sbdn + 2, 0, m->apicid_mcp55, 0x16); // 22) - - smp_write_pci_intsrc(mc, mp_INT, m->bus_mcp55[0], sbdn + 2, 1, m->apicid_mcp55, 0x17); // 23) - - smp_write_pci_intsrc(mc, mp_INT, m->bus_mcp55[0], sbdn + 5, 0, m->apicid_mcp55, 0x14); // 20) - smp_write_pci_intsrc(mc, mp_INT, m->bus_mcp55[0], sbdn + 5, 1, m->apicid_mcp55, 0x17); // 23) - smp_write_pci_intsrc(mc, mp_INT, m->bus_mcp55[0], sbdn + 5, 2, m->apicid_mcp55, 0x15); // 21) - - smp_write_pci_intsrc(mc, mp_INT, m->bus_mcp55[0], sbdn + 8, 0, m->apicid_mcp55, 0x16); // 22) - smp_write_pci_intsrc(mc, mp_INT, m->bus_mcp55[0], sbdn + 9, 0, m->apicid_mcp55, 0x15); // 21) - - for(j = 7; j >= 2; j--) { - if(!m->bus_mcp55[j]) continue; - for(i = 0; i < 4; i++) { - smp_write_pci_intsrc(mc, mp_INT, m->bus_mcp55[j], 0x00, i, m->apicid_mcp55, 0x10 + (2+j+i+4-sbdn%4)%4); - } - } - - for(j = 0; j < 1; j++) - for(i = 0; i < 4; i++) { - smp_write_pci_intsrc(mc, mp_INT, m->bus_mcp55[1], 0x04+j, i, m->apicid_mcp55, 0x10 + (2+i+j)%4); - } - -/*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN#*/ - mptable_lintsrc(mc, bus_isa); - /* There is no extension information... */ - - /* Compute the checksums */ - return mptable_finalize(mc); -} - -unsigned long write_smp_table(unsigned long addr) -{ - void *v; - v = smp_write_floating_table(addr, 0); - return (unsigned long)smp_write_config_table(v); -} diff --git a/src/mainboard/tyan/s2912_fam10/resourcemap.c b/src/mainboard/tyan/s2912_fam10/resourcemap.c deleted file mode 100644 index 50e245a610..0000000000 --- a/src/mainboard/tyan/s2912_fam10/resourcemap.c +++ /dev/null @@ -1,281 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007 AMD - * Written by Yinghai Lu for AMD. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include - -void setup_mb_resource_map(void) -{ - static const unsigned int register_values[] = { - /* Careful set limit registers before base registers which contain the enables */ - /* DRAM Limit i Registers - * F1:0x44 i = 0 - * F1:0x4C i = 1 - * F1:0x54 i = 2 - * F1:0x5C i = 3 - * F1:0x64 i = 4 - * F1:0x6C i = 5 - * F1:0x74 i = 6 - * F1:0x7C i = 7 - * [ 2: 0] Destination Node ID - * 000 = Node 0 - * 001 = Node 1 - * 010 = Node 2 - * 011 = Node 3 - * 100 = Node 4 - * 101 = Node 5 - * 110 = Node 6 - * 111 = Node 7 - * [ 7: 3] Reserved - * [10: 8] Interleave select - * specifies the values of A[14:12] to use with interleave enable. - * [15:11] Reserved - * [31:16] DRAM Limit Address i Bits 39-24 - * This field defines the upper address bits of a 40 bit address - * that define the end of the DRAM region. - */ - // ADDRMAP_REG(0x44), 0x0000f8f8, 0x00000000, - ADDRMAP_REG(0x4C), 0x0000f8f8, 0x00000001, - ADDRMAP_REG(0x54), 0x0000f8f8, 0x00000002, - ADDRMAP_REG(0x5C), 0x0000f8f8, 0x00000003, - ADDRMAP_REG(0x64), 0x0000f8f8, 0x00000004, - ADDRMAP_REG(0x6C), 0x0000f8f8, 0x00000005, - ADDRMAP_REG(0x74), 0x0000f8f8, 0x00000006, - ADDRMAP_REG(0x7C), 0x0000f8f8, 0x00000007, - - /* DRAM Base i Registers - * F1:0x40 i = 0 - * F1:0x48 i = 1 - * F1:0x50 i = 2 - * F1:0x58 i = 3 - * F1:0x60 i = 4 - * F1:0x68 i = 5 - * F1:0x70 i = 6 - * F1:0x78 i = 7 - * [ 0: 0] Read Enable - * 0 = Reads Disabled - * 1 = Reads Enabled - * [ 1: 1] Write Enable - * 0 = Writes Disabled - * 1 = Writes Enabled - * [ 7: 2] Reserved - * [10: 8] Interleave Enable - * 000 = No interleave - * 001 = Interleave on A[12] (2 nodes) - * 010 = reserved - * 011 = Interleave on A[12] and A[14] (4 nodes) - * 100 = reserved - * 101 = reserved - * 110 = reserved - * 111 = Interleve on A[12] and A[13] and A[14] (8 nodes) - * [15:11] Reserved - * [13:16] DRAM Base Address i Bits 39-24 - * This field defines the upper address bits of a 40-bit address - * that define the start of the DRAM region. - */ - // ADDRMAP_REG(0x40), 0x0000f8fc, 0x00000000, - ADDRMAP_REG(0x48), 0x0000f8fc, 0x00000000, - ADDRMAP_REG(0x50), 0x0000f8fc, 0x00000000, - ADDRMAP_REG(0x58), 0x0000f8fc, 0x00000000, - ADDRMAP_REG(0x60), 0x0000f8fc, 0x00000000, - ADDRMAP_REG(0x68), 0x0000f8fc, 0x00000000, - ADDRMAP_REG(0x70), 0x0000f8fc, 0x00000000, - ADDRMAP_REG(0x78), 0x0000f8fc, 0x00000000, - - /* Memory-Mapped I/O Limit i Registers - * F1:0x84 i = 0 - * F1:0x8C i = 1 - * F1:0x94 i = 2 - * F1:0x9C i = 3 - * F1:0xA4 i = 4 - * F1:0xAC i = 5 - * F1:0xB4 i = 6 - * F1:0xBC i = 7 - * [ 2: 0] Destination Node ID - * 000 = Node 0 - * 001 = Node 1 - * 010 = Node 2 - * 011 = Node 3 - * 100 = Node 4 - * 101 = Node 5 - * 110 = Node 6 - * 111 = Node 7 - * [ 3: 3] Reserved - * [ 5: 4] Destination Link ID - * 00 = Link 0 - * 01 = Link 1 - * 10 = Link 2 - * 11 = Reserved - * [ 6: 6] Reserved - * [ 7: 7] Non-Posted - * 0 = CPU writes may be posted - * 1 = CPU writes must be non-posted - * [31: 8] Memory-Mapped I/O Limit Address i (39-16) - * This field defines the upp address bits of a 40-bit address that - * defines the end of a memory-mapped I/O region n - */ - ADDRMAP_REG(0x84), 0x00000048, 0x00000000, - ADDRMAP_REG(0x8C), 0x00000048, 0x00000000, - ADDRMAP_REG(0x94), 0x00000048, 0x00000000, - ADDRMAP_REG(0x9C), 0x00000048, 0x00000000, - ADDRMAP_REG(0xA4), 0x00000048, 0x00000000, - ADDRMAP_REG(0xAC), 0x00000048, 0x00000000, - ADDRMAP_REG(0xB4), 0x00000048, 0x00000000, -// ADDRMAP_REG(0xBC), 0x00000048, 0x00ffff00, - - /* Memory-Mapped I/O Base i Registers - * F1:0x80 i = 0 - * F1:0x88 i = 1 - * F1:0x90 i = 2 - * F1:0x98 i = 3 - * F1:0xA0 i = 4 - * F1:0xA8 i = 5 - * F1:0xB0 i = 6 - * F1:0xB8 i = 7 - * [ 0: 0] Read Enable - * 0 = Reads disabled - * 1 = Reads Enabled - * [ 1: 1] Write Enable - * 0 = Writes disabled - * 1 = Writes Enabled - * [ 2: 2] Cpu Disable - * 0 = Cpu can use this I/O range - * 1 = Cpu requests do not use this I/O range - * [ 3: 3] Lock - * 0 = base/limit registers i are read/write - * 1 = base/limit registers i are read-only - * [ 7: 4] Reserved - * [31: 8] Memory-Mapped I/O Base Address i (39-16) - * This field defines the upper address bits of a 40bit address - * that defines the start of memory-mapped I/O region i - */ - ADDRMAP_REG(0x80), 0x000000f0, 0x00000000, - ADDRMAP_REG(0x88), 0x000000f0, 0x00000000, - ADDRMAP_REG(0x90), 0x000000f0, 0x00000000, - ADDRMAP_REG(0x98), 0x000000f0, 0x00000000, - ADDRMAP_REG(0xA0), 0x000000f0, 0x00000000, - ADDRMAP_REG(0xA8), 0x000000f0, 0x00000000, - ADDRMAP_REG(0xB0), 0x000000f0, 0x00000000, -// ADDRMAP_REG(0xB8), 0x000000f0, 0x00fc0003, - - /* PCI I/O Limit i Registers - * F1:0xC4 i = 0 - * F1:0xCC i = 1 - * F1:0xD4 i = 2 - * F1:0xDC i = 3 - * [ 2: 0] Destination Node ID - * 000 = Node 0 - * 001 = Node 1 - * 010 = Node 2 - * 011 = Node 3 - * 100 = Node 4 - * 101 = Node 5 - * 110 = Node 6 - * 111 = Node 7 - * [ 3: 3] Reserved - * [ 5: 4] Destination Link ID - * 00 = Link 0 - * 01 = Link 1 - * 10 = Link 2 - * 11 = reserved - * [11: 6] Reserved - * [24:12] PCI I/O Limit Address i - * This field defines the end of PCI I/O region n - * [31:25] Reserved - */ -// ADDRMAP_REG(0xC4), 0xFE000FC8, 0x00007000, -// ADDRMAP_REG(0xCC), 0xFE000FC8, 0x01fff020, // need to talk to ANALOG of second CK804 to release PCI E reset - ADDRMAP_REG(0xD4), 0xFE000FC8, 0x00000000, - ADDRMAP_REG(0xDC), 0xFE000FC8, 0x00000000, - - /* PCI I/O Base i Registers - * F1:0xC0 i = 0 - * F1:0xC8 i = 1 - * F1:0xD0 i = 2 - * F1:0xD8 i = 3 - * [ 0: 0] Read Enable - * 0 = Reads Disabled - * 1 = Reads Enabled - * [ 1: 1] Write Enable - * 0 = Writes Disabled - * 1 = Writes Enabled - * [ 3: 2] Reserved - * [ 4: 4] VGA Enable - * 0 = VGA matches Disabled - * 1 = matches all address < 64K and where A[9:0] is in the - * range 3B0-3BB or 3C0-3DF independen of the base & limit registers - * [ 5: 5] ISA Enable - * 0 = ISA matches Disabled - * 1 = Blocks address < 64K and in the last 768 bytes of eack 1K block - * from matching agains this base/limit pair - * [11: 6] Reserved - * [24:12] PCI I/O Base i - * This field defines the start of PCI I/O region n - * [31:25] Reserved - */ -// ADDRMAP_REG(0xC0), 0xFE000FCC, 0x00000033, -// ADDRMAP_REG(0xC8), 0xFE000FCC, 0x00008033, - ADDRMAP_REG(0xD0), 0xFE000FCC, 0x00000000, - ADDRMAP_REG(0xD8), 0xFE000FCC, 0x00000000, - - /* Config Base and Limit i Registers - * F1:0xE0 i = 0 - * F1:0xE4 i = 1 - * F1:0xE8 i = 2 - * F1:0xEC i = 3 - * [ 0: 0] Read Enable - * 0 = Reads Disabled - * 1 = Reads Enabled - * [ 1: 1] Write Enable - * 0 = Writes Disabled - * 1 = Writes Enabled - * [ 2: 2] Device Number Compare Enable - * 0 = The ranges are based on bus number - * 1 = The ranges are ranges of devices on bus 0 - * [ 3: 3] Reserved - * [ 6: 4] Destination Node - * 000 = Node 0 - * 001 = Node 1 - * 010 = Node 2 - * 011 = Node 3 - * 100 = Node 4 - * 101 = Node 5 - * 110 = Node 6 - * 111 = Node 7 - * [ 7: 7] Reserved - * [ 9: 8] Destination Link - * 00 = Link 0 - * 01 = Link 1 - * 10 = Link 2 - * 11 - Reserved - * [15:10] Reserved - * [23:16] Bus Number Base i - * This field defines the lowest bus number in configuration region i - * [31:24] Bus Number Limit i - * This field defines the highest bus number in configuration region i - */ -// ADDRMAP_REG(0xE0), 0x0000FC88, 0x3f000003, /* link 0 of CPU 0 --> Nvidia MCP55 Pro */ -// ADDRMAP_REG(0xE4), 0x0000FC88, 0x7f400203, /* link 2 of CPU 0 --> nvidia io55 */ - ADDRMAP_REG(0xE8), 0x0000FC88, 0x00000000, - ADDRMAP_REG(0xEC), 0x0000FC88, 0x00000000, - - }; - - int max; - max = ARRAY_SIZE(register_values); - setup_resource_map(register_values, max); -} diff --git a/src/mainboard/tyan/s2912_fam10/romstage.c b/src/mainboard/tyan/s2912_fam10/romstage.c deleted file mode 100644 index c546a3309f..0000000000 --- a/src/mainboard/tyan/s2912_fam10/romstage.c +++ /dev/null @@ -1,267 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007 AMD - * Written by Yinghai Lu for AMD. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include "cpu/amd/quadcore/quadcore.c" - -#define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1) - -int spd_read_byte(unsigned int device, unsigned int address); - - -inline int spd_read_byte(unsigned int device, unsigned int address) -{ - return smbus_read_byte(device, address); -} - -#define MCP55_MB_SETUP \ - RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+37, 0x00, 0x44,/* GPIO38 PCI_REQ3 */ \ - RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+38, 0x00, 0x44,/* GPIO39 PCI_GNT3 */ \ - RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+39, 0x00, 0x44,/* GPIO40 PCI_GNT2 */ \ - RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+40, 0x00, 0x44,/* GPIO41 PCI_REQ2 */ \ - RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+59, 0x00, 0x60,/* GPIP60 FANCTL0 */ \ - RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+60, 0x00, 0x60,/* GPIO61 FANCTL1 */ - -#include -#include "southbridge/nvidia/mcp55/early_setup_car.c" - -unsigned int get_sbdn(unsigned int bus) -{ - pci_devfn_t dev; - - /* Find the device. */ - dev = pci_locate_device_on_bus(PCI_ID(PCI_VENDOR_ID_NVIDIA, - PCI_DEVICE_ID_NVIDIA_MCP55_HT), bus); - - return (dev >> 15) & 0x1f; -} - -static void sio_setup(void) -{ - uint32_t dword; - uint8_t byte; - - byte = pci_read_config8(PCI_DEV(0, MCP55_DEVN_BASE+1, 0), 0x7b); - byte |= 0x20; - pci_write_config8(PCI_DEV(0, MCP55_DEVN_BASE+1, 0), 0x7b, byte); - - dword = pci_read_config32(PCI_DEV(0, MCP55_DEVN_BASE+1, 0), 0xa0); - /*serial 0 */ - dword |= (1 << 0); - pci_write_config32(PCI_DEV(0, MCP55_DEVN_BASE+1, 0), 0xa0, dword); - - dword = pci_read_config32(PCI_DEV(0, MCP55_DEVN_BASE+1, 0), 0xa4); - dword |= (1 << 16); - pci_write_config32(PCI_DEV(0, MCP55_DEVN_BASE+1, 0), 0xa4, dword); -} - -static const u8 spd_addr[] = { - //first node - RC00, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, -#if CONFIG_MAX_PHYSICAL_CPUS > 1 - //second node - RC00, DIMM4, DIMM6, 0, 0, DIMM5, DIMM7, 0, 0, -#endif -}; - -void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) -{ - struct sys_info *sysinfo = get_sysinfo(); - - u32 bsp_apicid = 0, val, wants_reset; - msr_t msr; - - timestamp_init(timestamp_get()); - timestamp_add_now(TS_START_ROMSTAGE); - - if (!cpu_init_detectedx && boot_cpu()) { - /* Nothing special needs to be done to find bus 0 */ - /* Allow the HT devices to be found */ - set_bsp_node_CHtExtNodeCfgEn(); - enumerate_ht_chain(); - sio_setup(); - } - - post_code(0x30); - - if (bist == 0) - bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo); - - post_code(0x32); - - winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); - console_init(); - - /* Halt if there was a built in self test failure */ - report_bist_failure(bist); - - val = cpuid_eax(1); - printk(BIOS_DEBUG, "BSP Family_Model: %08x\n", val); - printk(BIOS_DEBUG, "*sysinfo range: [%p,%p]\n",sysinfo,sysinfo+1); - printk(BIOS_DEBUG, "bsp_apicid = %02x\n", bsp_apicid); - printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx); - - /* Setup sysinfo defaults */ - set_sysinfo_in_ram(0); - - update_microcode(val); - - post_code(0x33); - - cpuSetAMDMSR(0); - post_code(0x34); - - amd_ht_init(sysinfo); - post_code(0x35); - - /* Setup nodes PCI space and start core 0 AP init. */ - finalize_node_setup(sysinfo); - - /* Setup any mainboard PCI settings etc. */ - setup_mb_resource_map(); - post_code(0x36); - - /* wait for all the APs core0 started by finalize_node_setup. */ - /* FIXME: A bunch of cores are going to start output to serial at once. - * It would be nice to fixup prink spinlocks for ROM XIP mode. - * I think it could be done by putting the spinlock flag in the cache - * of the BSP located right after sysinfo. - */ - wait_all_core0_started(); - -#if CONFIG(LOGICAL_CPUS) - /* Core0 on each node is configured. Now setup any additional cores. */ - printk(BIOS_DEBUG, "start_other_cores()\n"); - start_other_cores(bsp_apicid); - post_code(0x37); - wait_all_other_cores_started(bsp_apicid); -#endif - - post_code(0x38); - -#if CONFIG(SET_FIDVID) - msr = rdmsr(MSR_COFVID_STS); - printk(BIOS_DEBUG, "\nBegin FIDVID MSR 0xc0010071 0x%08x 0x%08x\n", msr.hi, msr.lo); - - /* FIXME: The sb fid change may survive the warm reset and only - * need to be done once.*/ - enable_fid_change_on_sb(sysinfo->sbbusn, sysinfo->sbdn); - - post_code(0x39); - - if (!warm_reset_detect(0)) { // BSP is node 0 - init_fidvid_bsp(bsp_apicid, sysinfo->nodes); - } else { - init_fidvid_stage2(bsp_apicid, 0); // BSP is node 0 - } - - post_code(0x3A); - - /* show final fid and vid */ - msr = rdmsr(MSR_COFVID_STS); - printk(BIOS_DEBUG, "End FIDVIDMSR 0xc0010071 0x%08x 0x%08x\n", msr.hi, msr.lo); -#endif - - init_timer(); // Need to use TMICT to synchronize FID/VID - - wants_reset = mcp55_early_setup_x(); - - /* Reset for HT, FIDVID, PLL and errata changes to take affect. */ - if (!warm_reset_detect(0)) { - printk(BIOS_INFO, "...WARM RESET...\n\n\n"); - soft_reset(); - die("After soft_reset - shouldn't see this message!!!\n"); - } - - if (wants_reset) - printk(BIOS_DEBUG, "mcp55_early_setup_x wanted additional reset!\n"); - - post_code(0x3B); - - /* It's the time to set ctrl in sysinfo now; */ - printk(BIOS_DEBUG, "fill_mem_ctrl()\n"); - fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr); - post_code(0x3D); - - printk(BIOS_DEBUG, "enable_smbus()\n"); - enable_smbus(); - - post_code(0x40); - - raminit_amdmct(sysinfo); - - cbmem_initialize_empty(); - post_code(0x41); - - amdmct_cbmem_store_info(sysinfo); - -} - -/** - * BOOL AMD_CB_ManualBUIDSwapList(u8 Node, u8 Link, u8 **List) - * Description: - * This routine is called every time a non-coherent chain is processed. - * BUID assignment may be controlled explicitly on a non-coherent chain. Provide a - * swap list. The first part of the list controls the BUID assignment and the - * second part of the list provides the device to device linking. Device orientation - * can be detected automatically, or explicitly. See documentation for more details. - * - * Automatic non-coherent init assigns BUIDs starting at 1 and incrementing sequentially - * based on each device's unit count. - * - * Parameters: - * @param[in] node = The node on which this chain is located - * @param[in] link = The link on the host for this chain - * @param[out] List = supply a pointer to a list - */ -BOOL AMD_CB_ManualBUIDSwapList (u8 node, u8 link, const u8 **List) -{ - static const u8 swaplist[] = { 0xFF, CONFIG_HT_CHAIN_UNITID_BASE, CONFIG_HT_CHAIN_END_UNITID_BASE, 0xFF }; - /* If the BUID was adjusted in early_ht we need to do the manual override */ - if ((CONFIG_HT_CHAIN_UNITID_BASE != 0) && (CONFIG_HT_CHAIN_END_UNITID_BASE != 0)) { - printk(BIOS_DEBUG, "AMD_CB_ManualBUIDSwapList()\n"); - if ((node == 0) && (link == 0)) { /* BSP SB link */ - *List = swaplist; - return 1; - } - } - - return 0; -} From b274ccf59670c9110c75edbe563e6d5287d4604d Mon Sep 17 00:00:00 2001 From: Arthur Heymans Date: Tue, 19 Nov 2019 15:59:51 +0100 Subject: [PATCH 0290/1242] sb/amd/amd8111: Remove support MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Relocatable ramstage, postcar stage and C_ENVIRONMENT_BOOTBLOCK are now mandatory features, which this platform lacks. Change-Id: I5d7f3bfca47b86e4fd761f9462bc7297b487fdee Signed-off-by: Arthur Heymans Reviewed-on: https://review.coreboot.org/c/coreboot/+/36964 Reviewed-by: Kyösti Mälkki Reviewed-by: Angel Pons Reviewed-by: HAOUAS Elyes Tested-by: build bot (Jenkins) --- src/southbridge/amd/amd8111/Kconfig | 24 -- src/southbridge/amd/amd8111/Makefile.inc | 15 - src/southbridge/amd/amd8111/ac97.c | 56 --- src/southbridge/amd/amd8111/acpi.c | 254 ------------- .../amd/amd8111/acpi/sleepstates.asl | 39 -- src/southbridge/amd/amd8111/amd8111.c | 86 ----- src/southbridge/amd/amd8111/amd8111.h | 22 -- src/southbridge/amd/amd8111/amd8111_smbus.h | 344 ------------------ src/southbridge/amd/amd8111/bootblock.c | 57 --- src/southbridge/amd/amd8111/chip.h | 24 -- src/southbridge/amd/amd8111/early_ctrl.c | 100 ----- src/southbridge/amd/amd8111/early_smbus.c | 77 ---- src/southbridge/amd/amd8111/ide.c | 80 ---- src/southbridge/amd/amd8111/lpc.c | 176 --------- src/southbridge/amd/amd8111/nic.c | 103 ------ src/southbridge/amd/amd8111/pci.c | 79 ---- src/southbridge/amd/amd8111/reset.c | 59 --- src/southbridge/amd/amd8111/smbus.c | 52 --- src/southbridge/amd/amd8111/usb.c | 46 --- src/southbridge/amd/amd8111/usb2.c | 43 --- 20 files changed, 1736 deletions(-) delete mode 100644 src/southbridge/amd/amd8111/Kconfig delete mode 100644 src/southbridge/amd/amd8111/Makefile.inc delete mode 100644 src/southbridge/amd/amd8111/ac97.c delete mode 100644 src/southbridge/amd/amd8111/acpi.c delete mode 100644 src/southbridge/amd/amd8111/acpi/sleepstates.asl delete mode 100644 src/southbridge/amd/amd8111/amd8111.c delete mode 100644 src/southbridge/amd/amd8111/amd8111.h delete mode 100644 src/southbridge/amd/amd8111/amd8111_smbus.h delete mode 100644 src/southbridge/amd/amd8111/bootblock.c delete mode 100644 src/southbridge/amd/amd8111/chip.h delete mode 100644 src/southbridge/amd/amd8111/early_ctrl.c delete mode 100644 src/southbridge/amd/amd8111/early_smbus.c delete mode 100644 src/southbridge/amd/amd8111/ide.c delete mode 100644 src/southbridge/amd/amd8111/lpc.c delete mode 100644 src/southbridge/amd/amd8111/nic.c delete mode 100644 src/southbridge/amd/amd8111/pci.c delete mode 100644 src/southbridge/amd/amd8111/reset.c delete mode 100644 src/southbridge/amd/amd8111/smbus.c delete mode 100644 src/southbridge/amd/amd8111/usb.c delete mode 100644 src/southbridge/amd/amd8111/usb2.c diff --git a/src/southbridge/amd/amd8111/Kconfig b/src/southbridge/amd/amd8111/Kconfig deleted file mode 100644 index a3abf89d9e..0000000000 --- a/src/southbridge/amd/amd8111/Kconfig +++ /dev/null @@ -1,24 +0,0 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2008-2009 coresystems GmbH -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; version 2 of the License. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## - -config SOUTHBRIDGE_AMD_AMD8111 - bool - select IOAPIC - select HAVE_POWER_STATE_AFTER_FAILURE - -config BOOTBLOCK_SOUTHBRIDGE_INIT - string - default "southbridge/amd/amd8111/bootblock.c" - depends on SOUTHBRIDGE_AMD_AMD8111 diff --git a/src/southbridge/amd/amd8111/Makefile.inc b/src/southbridge/amd/amd8111/Makefile.inc deleted file mode 100644 index 4c9ebaed88..0000000000 --- a/src/southbridge/amd/amd8111/Makefile.inc +++ /dev/null @@ -1,15 +0,0 @@ -ifeq ($(CONFIG_SOUTHBRIDGE_AMD_AMD8111),y) - -ramstage-y += amd8111.c -ramstage-y += usb.c -ramstage-y += lpc.c -ramstage-y += ide.c -ramstage-y += acpi.c -ramstage-y += usb2.c -ramstage-y += ac97.c -ramstage-y += nic.c -ramstage-y += pci.c -ramstage-y += smbus.c -ramstage-y += reset.c - -endif diff --git a/src/southbridge/amd/amd8111/ac97.c b/src/southbridge/amd/amd8111/ac97.c deleted file mode 100644 index d05f0be6d9..0000000000 --- a/src/southbridge/amd/amd8111/ac97.c +++ /dev/null @@ -1,56 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * (C) 2003 Linux Networx - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include -#include "amd8111.h" - -static struct pci_operations lops_pci = { - .set_subsystem = pci_dev_set_subsystem, -}; - -static struct device_operations ac97audio_ops = { - .read_resources = pci_dev_read_resources, - .set_resources = pci_dev_set_resources, - .enable_resources = pci_dev_enable_resources, - .enable = amd8111_enable, - .init = 0, - .scan_bus = 0, - .ops_pci = &lops_pci, -}; - -static const struct pci_driver ac97audio_driver __pci_driver = { - .ops = &ac97audio_ops, - .vendor = PCI_VENDOR_ID_AMD, - .device = 0x746D, -}; - - -static struct device_operations ac97modem_ops = { - .read_resources = pci_dev_read_resources, - .set_resources = pci_dev_set_resources, - .enable_resources = pci_dev_enable_resources, - .enable = amd8111_enable, - .init = 0, - .scan_bus = 0, - .ops_pci = &lops_pci, -}; - -static const struct pci_driver ac97modem_driver __pci_driver = { - .ops = &ac97modem_ops, - .vendor = PCI_VENDOR_ID_AMD, - .device = 0x746E, -}; diff --git a/src/southbridge/amd/amd8111/acpi.c b/src/southbridge/amd/amd8111/acpi.c deleted file mode 100644 index a735ff9bf9..0000000000 --- a/src/southbridge/amd/amd8111/acpi.c +++ /dev/null @@ -1,254 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include "amd8111.h" -#include "amd8111_smbus.h" - -#define PREVIOUS_POWER_STATE 0x43 -#define MAINBOARD_POWER_OFF 0 -#define MAINBOARD_POWER_ON 1 -#define SLOW_CPU_OFF 0 -#define SLOW_CPU__ON 1 - -static int lsmbus_recv_byte(struct device *dev) -{ - unsigned int device; - struct resource *res; - - device = dev->path.i2c.device; - res = find_resource(get_pbus_smbus(dev)->dev, 0x58); - - return do_smbus_recv_byte(res->base, device); -} - -static int lsmbus_send_byte(struct device *dev, uint8_t val) -{ - unsigned int device; - struct resource *res; - - device = dev->path.i2c.device; - res = find_resource(get_pbus_smbus(dev)->dev, 0x58); - - return do_smbus_send_byte(res->base, device, val); -} - - -static int lsmbus_read_byte(struct device *dev, uint8_t address) -{ - unsigned int device; - struct resource *res; - - device = dev->path.i2c.device; - res = find_resource(get_pbus_smbus(dev)->dev, 0x58); - - return do_smbus_read_byte(res->base, device, address); -} - -static int lsmbus_write_byte(struct device *dev, uint8_t address, uint8_t val) -{ - unsigned int device; - struct resource *res; - - device = dev->path.i2c.device; - res = find_resource(get_pbus_smbus(dev)->dev, 0x58); - - return do_smbus_write_byte(res->base, device, address, val); -} - -static int lsmbus_block_read(struct device *dev, uint8_t cmd, u8 bytes, - u8 *buffer) -{ - unsigned int device; - struct resource *res; - - device = dev->path.i2c.device; - res = find_resource(get_pbus_smbus(dev)->dev, 0x58); - - return do_smbus_block_read(res->base, device, cmd, bytes, buffer); -} - -static int lsmbus_block_write(struct device *dev, uint8_t cmd, u8 bytes, - const u8 *buffer) -{ - unsigned int device; - struct resource *res; - - device = dev->path.i2c.device; - res = find_resource(get_pbus_smbus(dev)->dev, 0x58); - - return do_smbus_block_write(res->base, device, cmd, bytes, buffer); -} - - -#if CONFIG(HAVE_ACPI_TABLES) -unsigned int pm_base; -#endif - -static void acpi_init(struct device *dev) -{ - uint8_t byte; - uint16_t pm10_bar; - int on; - -#if 0 - uint16_t word; - printk(BIOS_DEBUG, "ACPI: disabling NMI watchdog.. "); - byte = pci_read_config8(dev, 0x49); - pci_write_config8(dev, 0x49, byte | (1<<2)); - - - byte = pci_read_config8(dev, 0x41); - pci_write_config8(dev, 0x41, byte | (1<<6)|(1<<2)); - - /* added from sourceforge */ - byte = pci_read_config8(dev, 0x48); - pci_write_config8(dev, 0x48, byte | (1<<3)); - - printk(BIOS_DEBUG, "done.\n"); - - - printk(BIOS_DEBUG, "ACPI: Routing IRQ 12 to PS2 port.. "); - word = pci_read_config16(dev, 0x46); - pci_write_config16(dev, 0x46, word | (1<<9)); - printk(BIOS_DEBUG, "done.\n"); -#endif - - /* To enable the register 0xcf9 in the IO space - * bit [D5] is set in the amd8111 configuration register. - * The config. reg. is devBx41. Register 0xcf9 allows - * hard reset capability to the system. For the ACPI - * reset.reg values in fadt.c to work this register - * must be enabled. - */ - byte = pci_read_config8(dev, 0x41); - pci_write_config8(dev, 0x41, byte | (1<<6)|(1<<5)); - - /* power on after power fail */ - on = CONFIG_MAINBOARD_POWER_FAILURE_STATE; - get_option(&on, "power_on_after_fail"); - byte = pci_read_config8(dev, PREVIOUS_POWER_STATE); - byte &= ~0x40; - if (!on) { - byte |= 0x40; - } - pci_write_config8(dev, PREVIOUS_POWER_STATE, byte); - printk(BIOS_INFO, "set power %s after power fail\n", on?"on":"off"); - - /* switch serial irq logic from quiet mode to continuous - * mode for Winbond W83627HF Rev. 17 - */ - byte = pci_read_config8(dev, 0x4a); - pci_write_config8(dev, 0x4a, byte | (1<<6)); - - /* Throttle the CPU speed down for testing */ - on = SLOW_CPU_OFF; - get_option(&on, "slow_cpu"); - if (on) { - pm10_bar = (pci_read_config16(dev, 0x58) & 0xff00); - outl(((on << 1) + 0x10), (pm10_bar + 0x10)); - inl(pm10_bar + 0x10); - on = 8-on; - printk(BIOS_DEBUG, "Throttling CPU %2d.%1.1d percent.\n", - (on * 12) + (on >> 1), (on & 1) * 5); - } - -#if CONFIG(HAVE_ACPI_TABLES) - pm_base = pci_read_config16(dev, 0x58) & 0xff00; - printk(BIOS_DEBUG, "pm_base: 0x%04x\n", pm_base); -#endif - -} - -static void acpi_read_resources(struct device *dev) -{ - struct resource *resource; - - /* Handle the generic bars */ - pci_dev_read_resources(dev); - - /* Add the ACPI/SMBUS bar */ - resource = new_resource(dev, 0x58); - resource->base = 0; - resource->size = 256; - resource->align = log2(256); - resource->gran = log2(256); - resource->limit = 65536; - resource->flags = IORESOURCE_IO; - resource->index = 0x58; -} - -static void acpi_enable_resources(struct device *dev) -{ - uint8_t byte; - /* Enable the generic pci resources */ - pci_dev_enable_resources(dev); - - /* Enable the ACPI/SMBUS Bar */ - byte = pci_read_config8(dev, 0x41); - byte |= (1 << 7); - pci_write_config8(dev, 0x41, byte); - - /* Set the class code */ - pci_write_config32(dev, 0x60, 0x06800000); - -} - -static void lpci_set_subsystem(struct device *dev, unsigned int vendor, - unsigned int device) -{ - pci_write_config32(dev, 0x7c, - ((device & 0xffff) << 16) | (vendor & 0xffff)); -} - -static struct smbus_bus_operations lops_smbus_bus = { - .recv_byte = lsmbus_recv_byte, - .send_byte = lsmbus_send_byte, - .read_byte = lsmbus_read_byte, - .write_byte = lsmbus_write_byte, - .block_read = lsmbus_block_read, - .block_write= lsmbus_block_write, -}; - -static struct pci_operations lops_pci = { - .set_subsystem = lpci_set_subsystem, -}; - -static struct device_operations acpi_ops = { - .read_resources = acpi_read_resources, - .set_resources = pci_dev_set_resources, - .enable_resources = acpi_enable_resources, - .init = acpi_init, - .scan_bus = scan_smbus, - /* We don't need amd8111_enable, chip ops takes care of it. - * It could be useful if these devices were not - * enabled by default. - */ -// .enable = amd8111_enable, - .ops_pci = &lops_pci, - .ops_smbus_bus = &lops_smbus_bus, -}; - -static const struct pci_driver acpi_driver __pci_driver = { - .ops = &acpi_ops, - .vendor = PCI_VENDOR_ID_AMD, - .device = PCI_DEVICE_ID_AMD_8111_ACPI, -}; diff --git a/src/southbridge/amd/amd8111/acpi/sleepstates.asl b/src/southbridge/amd/amd8111/acpi/sleepstates.asl deleted file mode 100644 index 19fde4ded2..0000000000 --- a/src/southbridge/amd/amd8111/acpi/sleepstates.asl +++ /dev/null @@ -1,39 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007-2009 coresystems GmbH - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -/* S1 support: bit 0, S2 Support: bit 1, etc. S0 & S5 assumed */ -#if CONFIG(HAVE_ACPI_RESUME) -Name (SSFG, 0x05) -#else -Name (SSFG, 0x01) -#endif - -/* Supported sleep states: */ -Name(\_S0, Package () {0x00, 0x00, 0x00, 0x00} ) /* (S0) - working state */ - -If (And(SSFG, 0x01)) { - Name(\_S1, Package () {0x01, 0x01, 0x01, 0x01} ) /* (S1) - sleeping w/CPU context */ -} -If (And(SSFG, 0x02)) { - Name(\_S2, Package () {0x02, 0x02, 0x02, 0x02} ) /* (S2) - "light" Suspend to RAM */ -} -If (And(SSFG, 0x04)) { - Name(\_S3, Package () {0x05, 0x05, 0x05, 0x05} ) /* (S3) - Suspend to RAM */ -} -If (And(SSFG, 0x08)) { - Name(\_S4, Package () {0x06, 0x06, 0x06, 0x06} ) /* (S4) - Suspend to Disk */ -} - -Name(\_S5, Package () {0x07, 0x07, 0x07, 0x07} ) /* (S5) - Soft Off */ diff --git a/src/southbridge/amd/amd8111/amd8111.c b/src/southbridge/amd/amd8111/amd8111.c deleted file mode 100644 index 0180f45653..0000000000 --- a/src/southbridge/amd/amd8111/amd8111.c +++ /dev/null @@ -1,86 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include -#include -#include "amd8111.h" - -void amd8111_enable(struct device *dev) -{ - struct device *lpc_dev; - struct device *bus_dev; - unsigned int index; - unsigned int reg_old, reg; - - /* See if we are on the bus behind the amd8111 pci bridge */ - bus_dev = dev->bus->dev; - if ((bus_dev->vendor == PCI_VENDOR_ID_AMD) && - (bus_dev->device == PCI_DEVICE_ID_AMD_8111_PCI)) - { - unsigned int devfn; - devfn = bus_dev->path.pci.devfn + (1 << 3); - lpc_dev = pcidev_path_behind(bus_dev->bus, devfn); - index = ((dev->path.pci.devfn & ~7) >> 3) + 8; - if (dev->path.pci.devfn == 2) { /* EHCI */ - index = 16; - } - } else { - unsigned int devfn; - devfn = (dev->path.pci.devfn) & ~7; - lpc_dev = pcidev_path_behind(dev->bus, devfn); - index = dev->path.pci.devfn & 7; - } - if ((!lpc_dev) || (index >= 17)) { - return; - } - if ((lpc_dev->vendor != PCI_VENDOR_ID_AMD) || - (lpc_dev->device != PCI_DEVICE_ID_AMD_8111_ISA)) - { - uint32_t id; - id = pci_read_config32(lpc_dev, PCI_VENDOR_ID); - if (id != (PCI_VENDOR_ID_AMD | (PCI_DEVICE_ID_AMD_8111_ISA << 16))) { - return; - } - } - - if (index < 16) { - reg = reg_old = pci_read_config16(lpc_dev, 0x48); - reg &= ~(1 << index); - if (dev->enabled) { - reg |= (1 << index); - } - if (reg != reg_old) { - pci_write_config16(lpc_dev, 0x48, reg); - } - } - else if (index == 16) { - reg = reg_old = pci_read_config8(lpc_dev, 0x47); - reg &= ~(1 << 7); - if (!dev->enabled) { - reg |= (1 << 7); - } - if (reg != reg_old) { - pci_write_config8(lpc_dev, 0x47, reg); - } - } -} - -struct chip_operations southbridge_amd_amd8111_ops = { - CHIP_NAME("AMD-8111 Southbridge") - /* This only called when this device is listed in the - * static device tree. - */ - .enable_dev = amd8111_enable, -}; diff --git a/src/southbridge/amd/amd8111/amd8111.h b/src/southbridge/amd/amd8111/amd8111.h deleted file mode 100644 index fc57936908..0000000000 --- a/src/southbridge/amd/amd8111/amd8111.h +++ /dev/null @@ -1,22 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef AMD8111_H -#define AMD8111_H - -#include - -void amd8111_enable(struct device *dev); -void enable_fid_change_on_sb(unsigned int sbbusn, unsigned int sbdn); - -#endif /* AMD8111_H */ diff --git a/src/southbridge/amd/amd8111/amd8111_smbus.h b/src/southbridge/amd/amd8111/amd8111_smbus.h deleted file mode 100644 index 894fcd0a61..0000000000 --- a/src/southbridge/amd/amd8111/amd8111_smbus.h +++ /dev/null @@ -1,344 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include - -#define SMBGSTATUS 0xe0 -#define SMBGCTL 0xe2 -#define SMBHSTADDR 0xe4 -#define SMBHSTDAT 0xe6 -#define SMBHSTCMD 0xe8 -#define SMBHSTFIFO 0xe9 - -#define SMBUS_TIMEOUT (100*1000*10) -#define SMBUS_STATUS_MASK 0xfbff - -static inline void smbus_delay(void) -{ - outb(0x80, 0x80); -} - -static int smbus_wait_until_ready(unsigned int smbus_io_base) -{ - unsigned long loops; - loops = SMBUS_TIMEOUT; - do { - unsigned short val; - smbus_delay(); - val = inw(smbus_io_base + SMBGSTATUS); - if ((val & 0x800) == 0) { - break; - } - if (loops == (SMBUS_TIMEOUT / 2)) { - outw(inw(smbus_io_base + SMBGSTATUS), - smbus_io_base + SMBGSTATUS); - } - } while (--loops); - return loops?0:SMBUS_WAIT_UNTIL_READY_TIMEOUT; -} - -static int smbus_wait_until_done(unsigned int smbus_io_base) -{ - unsigned long loops; - loops = SMBUS_TIMEOUT; - do { - unsigned short val; - smbus_delay(); - - val = inw(smbus_io_base + SMBGSTATUS); - if (((val & 0x8) == 0) | ((val & 0x0037) != 0)) { - break; - } - } while (--loops); - return loops?0:SMBUS_WAIT_UNTIL_DONE_TIMEOUT; -} - -static int do_smbus_recv_byte(unsigned int smbus_io_base, unsigned int device) -{ - unsigned int global_status_register; - unsigned int byte; - - if (smbus_wait_until_ready(smbus_io_base) < 0) { - return SMBUS_WAIT_UNTIL_READY_TIMEOUT; - } - - /* setup transaction */ - /* disable interrupts */ - outw(inw(smbus_io_base + SMBGCTL) & ~((1<<10)|(1<<9)|(1<<8)|(1<<4)), smbus_io_base + SMBGCTL); - /* set the device I'm talking to */ - outw(((device & 0x7f) << 1) | 1, smbus_io_base + SMBHSTADDR); - /* set the command/address... */ - outb(0, smbus_io_base + SMBHSTCMD); - /* set up for a send byte */ - outw((inw(smbus_io_base + SMBGCTL) & ~7) | (0x1), smbus_io_base + SMBGCTL); - - /* clear any lingering errors, so the transaction will run */ - /* Do I need to write the bits to a 1 to clear an error? */ - outw(inw(smbus_io_base + SMBGSTATUS), smbus_io_base + SMBGSTATUS); - - /* set the data word...*/ - outw(0, smbus_io_base + SMBHSTDAT); - - /* start the command */ - outw((inw(smbus_io_base + SMBGCTL) | (1 << 3)), smbus_io_base + SMBGCTL); - - - /* poll for transaction completion */ - if (smbus_wait_until_done(smbus_io_base) < 0) { - return SMBUS_WAIT_UNTIL_DONE_TIMEOUT; - } - - global_status_register = inw(smbus_io_base + SMBGSTATUS); - - /* read results of transaction */ - byte = inw(smbus_io_base + SMBHSTDAT) & 0xff; - - if ((global_status_register & SMBUS_STATUS_MASK) != (1 << 4)) { - return SMBUS_ERROR; - } - return byte; -} - -static int do_smbus_send_byte(unsigned int smbus_io_base, unsigned int device, - unsigned int value) -{ - unsigned int global_status_register; - - if (smbus_wait_until_ready(smbus_io_base) < 0) { - return SMBUS_WAIT_UNTIL_READY_TIMEOUT; - } - - /* setup transaction */ - /* disable interrupts */ - outw(inw(smbus_io_base + SMBGCTL) & ~((1<<10)|(1<<9)|(1<<8)|(1<<4)), smbus_io_base + SMBGCTL); - /* set the device I'm talking to */ - outw(((device & 0x7f) << 1) | 0, smbus_io_base + SMBHSTADDR); - /* set the command/address... */ - outb(0, smbus_io_base + SMBHSTCMD); - /* set up for a send byte */ - outw((inw(smbus_io_base + SMBGCTL) & ~7) | (0x1), smbus_io_base + SMBGCTL); - - /* clear any lingering errors, so the transaction will run */ - /* Do I need to write the bits to a 1 to clear an error? */ - outw(inw(smbus_io_base + SMBGSTATUS), smbus_io_base + SMBGSTATUS); - - /* set the data word...*/ - outw(value, smbus_io_base + SMBHSTDAT); - - /* start the command */ - outw((inw(smbus_io_base + SMBGCTL) | (1 << 3)), smbus_io_base + SMBGCTL); - - - /* poll for transaction completion */ - if (smbus_wait_until_done(smbus_io_base) < 0) { - return SMBUS_WAIT_UNTIL_DONE_TIMEOUT; - } - global_status_register = inw(smbus_io_base + SMBGSTATUS); - - if ((global_status_register & SMBUS_STATUS_MASK) != (1 << 4)) { - return SMBUS_ERROR; - } - return 0; -} - - -static int do_smbus_read_byte(unsigned int smbus_io_base, unsigned int device, - unsigned int address) -{ - unsigned int global_status_register; - unsigned int byte; - - if (smbus_wait_until_ready(smbus_io_base) < 0) { - return SMBUS_WAIT_UNTIL_READY_TIMEOUT; - } - - /* setup transaction */ - /* disable interrupts */ - outw(inw(smbus_io_base + SMBGCTL) & ~((1<<10)|(1<<9)|(1<<8)|(1<<4)), smbus_io_base + SMBGCTL); - /* set the device I'm talking to */ - outw(((device & 0x7f) << 1) | 1, smbus_io_base + SMBHSTADDR); - /* set the command/address... */ - outb(address & 0xFF, smbus_io_base + SMBHSTCMD); - /* set up for a byte data read */ - outw((inw(smbus_io_base + SMBGCTL) & ~7) | (0x2), smbus_io_base + SMBGCTL); - - /* clear any lingering errors, so the transaction will run */ - /* Do I need to write the bits to a 1 to clear an error? */ - outw(inw(smbus_io_base + SMBGSTATUS), smbus_io_base + SMBGSTATUS); - - /* clear the data word...*/ - outw(0, smbus_io_base + SMBHSTDAT); - - /* start the command */ - outw((inw(smbus_io_base + SMBGCTL) | (1 << 3)), smbus_io_base + SMBGCTL); - - - /* poll for transaction completion */ - if (smbus_wait_until_done(smbus_io_base) < 0) { - return SMBUS_WAIT_UNTIL_DONE_TIMEOUT; - } - - global_status_register = inw(smbus_io_base + SMBGSTATUS); - - /* read results of transaction */ - byte = inw(smbus_io_base + SMBHSTDAT) & 0xff; - - if ((global_status_register & SMBUS_STATUS_MASK) != (1 << 4)) { - return SMBUS_ERROR; - } - return byte; -} - -static int do_smbus_write_byte(unsigned int smbus_io_base, unsigned int device, - unsigned int address, unsigned char val) -{ - unsigned int global_status_register; - - if (smbus_wait_until_ready(smbus_io_base) < 0) { - return SMBUS_WAIT_UNTIL_READY_TIMEOUT; - } - - /* setup transaction */ - /* disable interrupts */ - outw(inw(smbus_io_base + SMBGCTL) & ~((1<<10)|(1<<9)|(1<<8)|(1<<4)), smbus_io_base + SMBGCTL); - /* set the device I'm talking to */ - outw(((device & 0x7f) << 1) | 0, smbus_io_base + SMBHSTADDR); - outb(address & 0xFF, smbus_io_base + SMBHSTCMD); - /* set up for a byte data write */ /* FIXME */ - outw((inw(smbus_io_base + SMBGCTL) & ~7) | (0x2), smbus_io_base + SMBGCTL); - /* clear any lingering errors, so the transaction will run */ - /* Do I need to write the bits to a 1 to clear an error? */ - outw(inw(smbus_io_base + SMBGSTATUS), smbus_io_base + SMBGSTATUS); - - /* write the data word...*/ - outw(val, smbus_io_base + SMBHSTDAT); - - /* start the command */ - outw((inw(smbus_io_base + SMBGCTL) | (1 << 3)), smbus_io_base + SMBGCTL); - - /* poll for transaction completion */ - if (smbus_wait_until_done(smbus_io_base) < 0) { - return SMBUS_WAIT_UNTIL_DONE_TIMEOUT; - } - global_status_register = inw(smbus_io_base + SMBGSTATUS); - - if ((global_status_register & SMBUS_STATUS_MASK) != (1 << 4)) { - return SMBUS_ERROR; - } - return 0; -} - -static int do_smbus_block_read(unsigned int smbus_io_base, unsigned int device, - unsigned int cmd, u8 bytes, u8 *buf) -{ - unsigned int global_status_register; - unsigned int i; - u8 msglen; - - if (smbus_wait_until_ready(smbus_io_base) < 0) { - return SMBUS_WAIT_UNTIL_READY_TIMEOUT; - } - - /* setup transaction */ - /* disable interrupts */ - outw(inw(smbus_io_base + SMBGCTL) & ~((1<<10)|(1<<9)|(1<<8)|(1<<4)), smbus_io_base + SMBGCTL); - /* set the device I'm talking to */ - outw(((device & 0x7f) << 1) | 1, smbus_io_base + SMBHSTADDR); - /* set the command/address... */ - outb(cmd & 0xFF, smbus_io_base + SMBHSTCMD); - /* set up for a block data read */ - outw((inw(smbus_io_base + SMBGCTL) & ~7) | (0x5), smbus_io_base + SMBGCTL); - - /* clear any lingering errors, so the transaction will run */ - /* Do I need to write the bits to a 1 to clear an error? */ - outw(inw(smbus_io_base + SMBGSTATUS), smbus_io_base + SMBGSTATUS); - - /* clear the length word...*/ - outw(0, smbus_io_base + SMBHSTDAT); - - /* start the command */ - outw((inw(smbus_io_base + SMBGCTL) | (1 << 3)), smbus_io_base + SMBGCTL); - - /* poll for transaction completion */ - if (smbus_wait_until_done(smbus_io_base) < 0) { - return SMBUS_WAIT_UNTIL_DONE_TIMEOUT; - } - - global_status_register = inw(smbus_io_base + SMBGSTATUS); - - /* read results of transaction */ - msglen = inw(smbus_io_base + SMBHSTDAT) & 0x3f; - - if ((global_status_register & SMBUS_STATUS_MASK) != (1 << 4)) { - return SMBUS_ERROR; - } - - /* read data block */ - for (i = 0; i < msglen && i < bytes; i++) { - buf[i] = inw(smbus_io_base + SMBHSTFIFO) & 0xff; - } - /* empty fifo */ - while (bytes++ for Linux Networx) - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include -#include - -#define PCI_ID(VENDOR_ID, DEVICE_ID) \ - ((((DEVICE_ID) & 0xFFFF) << 16) | ((VENDOR_ID) & 0xFFFF)) - -static pci_devfn_t pci_io_locate_device(unsigned int pci_id, pci_devfn_t dev) -{ - for (; dev <= PCI_DEV(255, 31, 7); dev += PCI_DEV(0, 0, 1)) { - unsigned int id; - id = pci_io_read_config32(dev, 0); - if (id == pci_id) - return dev; - } - return PCI_DEV_INVALID; -} - -/* Enable 5MB ROM access at 0xFFB00000 - 0xFFFFFFFF. */ -static void amd8111_enable_rom(void) -{ - u8 byte; - pci_devfn_t dev; - - dev = pci_io_locate_device(PCI_ID(PCI_VENDOR_ID_AMD, - PCI_DEVICE_ID_AMD_8111_ISA), 0); - - /* Note: The 0xFFFF0000 - 0xFFFFFFFF range is always enabled. */ - - /* Set the 5MB enable bits. */ - byte = pci_io_read_config8(dev, 0x43); - byte |= (1 << 7); /* Enable 0xFFC00000-0xFFFFFFFF (4MB). */ - byte |= (1 << 6); /* Enable 0xFFB00000-0xFFBFFFFF (1MB). */ - pci_io_write_config8(dev, 0x43, byte); -} - -static void bootblock_southbridge_init(void) -{ - amd8111_enable_rom(); -} diff --git a/src/southbridge/amd/amd8111/chip.h b/src/southbridge/amd/amd8111/chip.h deleted file mode 100644 index 54501f5039..0000000000 --- a/src/southbridge/amd/amd8111/chip.h +++ /dev/null @@ -1,24 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef AMD8111_CHIP_H -#define AMD8111_CHIP_H - -struct southbridge_amd_amd8111_config -{ - unsigned int ide0_enable : 1; - unsigned int ide1_enable : 1; - unsigned int phy_lowreset : 1; -}; - -#endif /* AMD8111_CHIP_H */ diff --git a/src/southbridge/amd/amd8111/early_ctrl.c b/src/southbridge/amd/amd8111/early_ctrl.c deleted file mode 100644 index e9676ebc08..0000000000 --- a/src/southbridge/amd/amd8111/early_ctrl.c +++ /dev/null @@ -1,100 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright 2015 yhlu - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include -#include -#include "amd8111.h" - -unsigned int get_sbdn(unsigned int bus) -{ - pci_devfn_t dev; - - /* Find the device. - * There can only be one 8111 on a hypertransport chain/bus. - */ - dev = pci_locate_device_on_bus( - PCI_ID(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8111_PCI), - bus); - - return (dev>>15) & 0x1f; - -} - -static void enable_cf9_x(unsigned int sbbusn, unsigned int sbdn) -{ - pci_devfn_t dev; - uint8_t byte; - - dev = PCI_DEV(sbbusn, sbdn+1, 3); //ACPI - /* enable cf9 */ - byte = pci_read_config8(dev, 0x41); - byte |= (1<<6) | (1<<5); - pci_write_config8(dev, 0x41, byte); -} - -static void enable_cf9(void) -{ - unsigned int sblk = get_sblk(); - unsigned int sbbusn = get_sbbusn(sblk); - unsigned int sbdn = get_sbdn(sbbusn); - - enable_cf9_x(sbbusn, sbdn); -} - -void do_board_reset(void) -{ - set_bios_reset(); - /* reset */ - enable_cf9(); - outb(0x0e, 0x0cf9); // make sure cf9 is enabled -} - -void enable_fid_change_on_sb(unsigned int sbbusn, unsigned int sbdn) -{ - pci_devfn_t dev; - - dev = PCI_DEV(sbbusn, sbdn+1, 3); // ACPI - - pci_write_config8(dev, 0x74, 4); - - /* set VFSMAF (VID/FID System Management Action Field) to 2 */ - pci_write_config32(dev, 0x70, 2<<12); - -} - -static void soft_reset_x(unsigned int sbbusn, unsigned int sbdn) -{ - pci_devfn_t dev; - - dev = PCI_DEV(sbbusn, sbdn+1, 0); //ISA - - /* Reset */ - set_bios_reset(); - pci_write_config8(dev, 0x47, 1); - -} - -void do_soft_reset(void) -{ - - unsigned int sblk = get_sblk(); - unsigned int sbbusn = get_sbbusn(sblk); - unsigned int sbdn = get_sbdn(sbbusn); - - return soft_reset_x(sbbusn, sbdn); - -} diff --git a/src/southbridge/amd/amd8111/early_smbus.c b/src/southbridge/amd/amd8111/early_smbus.c deleted file mode 100644 index c82190223d..0000000000 --- a/src/southbridge/amd/amd8111/early_smbus.c +++ /dev/null @@ -1,77 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include - -#include "amd8111_smbus.h" - -#define SMBUS_IO_BASE 0x0f00 - -static void enable_smbus(void) -{ - pci_devfn_t dev; - uint8_t enable; - - dev = pci_locate_device(PCI_ID(0x1022, 0x746b), 0); - if (dev == PCI_DEV_INVALID) { - die("SMBUS controller not found\n"); - } - - pci_write_config32(dev, 0x58, SMBUS_IO_BASE | 1); - enable = pci_read_config8(dev, 0x41); - pci_write_config8(dev, 0x41, enable | (1 << 7)); - - /* check that we can see the smbus controller I/O. */ - if (inw(SMBUS_IO_BASE)==0xFF){ - die("SMBUS controller I/O not found\n"); - } - - /* clear any lingering errors, so the transaction will run */ - outw(inw(SMBUS_IO_BASE + SMBGSTATUS), SMBUS_IO_BASE + SMBGSTATUS); - printk(BIOS_SPEW, "SMBus controller enabled\n"); -} - -static inline int smbus_recv_byte(unsigned int device) -{ - return do_smbus_recv_byte(SMBUS_IO_BASE, device); -} - -static inline int smbus_send_byte(unsigned int device, unsigned char val) -{ - return do_smbus_send_byte(SMBUS_IO_BASE, device, val); -} - -static inline int smbus_read_byte(unsigned int device, unsigned int address) -{ - return do_smbus_read_byte(SMBUS_IO_BASE, device, address); -} - -static inline int smbus_write_byte(unsigned int device, unsigned int address, - unsigned char val) -{ - return do_smbus_write_byte(SMBUS_IO_BASE, device, address, val); -} - -static inline int smbus_block_read(unsigned int device, unsigned int cmd, u8 bytes, - u8 *buf) -{ - return do_smbus_block_read(SMBUS_IO_BASE, device, cmd, bytes, buf); -} - -static inline int smbus_block_write(unsigned int device, unsigned int cmd, u8 bytes, - const u8 *buf) -{ - return do_smbus_block_write(SMBUS_IO_BASE, device, cmd, bytes, buf); -} diff --git a/src/southbridge/amd/amd8111/ide.c b/src/southbridge/amd/amd8111/ide.c deleted file mode 100644 index 49f9d154f8..0000000000 --- a/src/southbridge/amd/amd8111/ide.c +++ /dev/null @@ -1,80 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include -#include -#include -#include "amd8111.h" -#include "chip.h" - -static void ide_init(struct device *dev) -{ - struct southbridge_amd_amd8111_config *conf; - /* Enable ide devices so the linux ide driver will work */ - uint16_t word; - uint8_t byte; - conf = dev->chip_info; - - word = pci_read_config16(dev, 0x40); - /* Ensure prefetch is disabled */ - word &= ~((1 << 15) | (1 << 13)); - if (conf->ide1_enable) { - /* Enable secondary ide interface */ - word |= (1<<0); - printk(BIOS_DEBUG, "IDE1 "); - } - if (conf->ide0_enable) { - /* Enable primary ide interface */ - word |= (1<<1); - printk(BIOS_DEBUG, "IDE0 "); - } - - word |= (1<<12); - word |= (1<<14); - - pci_write_config16(dev, 0x40, word); - - - byte = 0x20; // Latency: 64-->32 - pci_write_config8(dev, 0xd, byte); - - word = 0x0f; - pci_write_config16(dev, 0x42, word); -} - -static void lpci_set_subsystem(struct device *dev, unsigned int vendor, - unsigned int device) -{ - pci_write_config32(dev, 0x70, - ((device & 0xffff) << 16) | (vendor & 0xffff)); -} -static struct pci_operations lops_pci = { - .set_subsystem = lpci_set_subsystem, -}; -static struct device_operations ide_ops = { - .read_resources = pci_dev_read_resources, - .set_resources = pci_dev_set_resources, - .enable_resources = pci_dev_enable_resources, - .init = ide_init, - .scan_bus = 0, - .enable = amd8111_enable, - .ops_pci = &lops_pci -}; - -static const struct pci_driver ide_driver __pci_driver = { - .ops = &ide_ops, - .vendor = PCI_VENDOR_ID_AMD, - .device = PCI_DEVICE_ID_AMD_8111_IDE, -}; diff --git a/src/southbridge/amd/amd8111/lpc.c b/src/southbridge/amd/amd8111/lpc.c deleted file mode 100644 index b4a92a0f03..0000000000 --- a/src/southbridge/amd/amd8111/lpc.c +++ /dev/null @@ -1,176 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * (C) 2003 Linux Networx, SuSE Linux AG - * 2006.1 yhlu add dest apicid for IRQ0 - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#if CONFIG(HAVE_ACPI_TABLES) -#include -#include -#include -#endif -#include - -#include "amd8111.h" - -#define NMI_OFF 0 - -static void enable_hpet(struct device *dev) -{ - unsigned long hpet_address; - - pci_write_config32(dev, 0xa0, CONFIG_HPET_ADDRESS|1); - hpet_address = pci_read_config32(dev,0xa0)& 0xfffffffe; - printk(BIOS_DEBUG, "enabling HPET @0x%lx\n", hpet_address); - -} - -static void lpc_init(struct device *dev) -{ - uint8_t byte; - int nmi_option; - - /* IO APIC initialization */ - byte = pci_read_config8(dev, 0x4B); - byte |= 1; - pci_write_config8(dev, 0x4B, byte); - /* Don't rename IO APIC */ - setup_ioapic(VIO_APIC_VADDR, 0); - - /* posted memory write enable */ - byte = pci_read_config8(dev, 0x46); - pci_write_config8(dev, 0x46, byte | (1<<0)); - - /* Enable 5Mib Rom window */ - byte = pci_read_config8(dev, 0x43); - byte |= 0xc0; - pci_write_config8(dev, 0x43, byte); - - /* Enable Port 92 fast reset */ - byte = pci_read_config8(dev, 0x41); - byte |= (1 << 5); - pci_write_config8(dev, 0x41, byte); - - /* Enable Error reporting */ - /* Set up sync flood detected */ - byte = pci_read_config8(dev, 0x47); - byte |= (1 << 1); - pci_write_config8(dev, 0x47, byte); - - /* Set up NMI on errors */ - byte = pci_read_config8(dev, 0x40); - byte |= (1 << 1); /* clear PW2LPC error */ - byte |= (1 << 6); /* clear LPCERR */ - pci_write_config8(dev, 0x40, byte); - nmi_option = NMI_OFF; - get_option(&nmi_option, "nmi"); - if (nmi_option) { - byte |= (1 << 7); /* set NMI */ - pci_write_config8(dev, 0x40, byte); - } - - /* Initialize the real time clock */ - cmos_init(0); - - /* Initialize isa dma */ - isa_dma_init(); - - /* Initialize the High Precision Event Timers */ - enable_hpet(dev); -} - -static void amd8111_lpc_read_resources(struct device *dev) -{ - struct resource *res; - - /* Get the normal PCI resources of this device. */ - pci_dev_read_resources(dev); - - /* Add an extra subtractive resource for both memory and I/O. */ - res = new_resource(dev, IOINDEX_SUBTRACTIVE(0, 0)); - res->base = 0; - res->size = 0x1000; - res->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE | - IORESOURCE_ASSIGNED | IORESOURCE_FIXED; - - res = new_resource(dev, IOINDEX_SUBTRACTIVE(1, 0)); - res->base = 0xff800000; - res->size = 0x00800000; /* 8 MB for flash */ - res->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE | - IORESOURCE_ASSIGNED | IORESOURCE_FIXED; - - res = new_resource(dev, 3); /* IOAPIC */ - res->base = IO_APIC_ADDR; - res->size = 0x00001000; - res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; -} - -static void lpci_set_subsystem(struct device *dev, unsigned int vendor, - unsigned int device) -{ - pci_write_config32(dev, 0x70, - ((device & 0xffff) << 16) | (vendor & 0xffff)); -} - -#if CONFIG(HAVE_ACPI_TABLES) - -extern u16 pm_base; - -unsigned long acpi_fill_mcfg(unsigned long current) -{ - /* Just a dummy */ - return current; -} - -static void southbridge_acpi_fill_ssdt_generator(struct device *device) { -#if CONFIG(SET_FIDVID) - amd_generate_powernow(pm_base + 0x10, 6, 1); - acpigen_write_mainboard_resources("\\_SB.PCI0.MBRS", "_CRS"); -#endif -} - -#endif - - -static struct pci_operations lops_pci = { - .set_subsystem = lpci_set_subsystem, -}; - -static struct device_operations lpc_ops = { - .read_resources = amd8111_lpc_read_resources, - .set_resources = pci_dev_set_resources, - .enable_resources = pci_dev_enable_resources, - .init = lpc_init, -#if CONFIG(HAVE_ACPI_TABLES) - .write_acpi_tables = acpi_write_hpet, - .acpi_fill_ssdt_generator = southbridge_acpi_fill_ssdt_generator, -#endif - .scan_bus = scan_static_bus, - .enable = amd8111_enable, - .ops_pci = &lops_pci, -}; - -static const struct pci_driver lpc_driver __pci_driver = { - .ops = &lpc_ops, - .vendor = PCI_VENDOR_ID_AMD, - .device = PCI_DEVICE_ID_AMD_8111_ISA, -}; diff --git a/src/southbridge/amd/amd8111/nic.c b/src/southbridge/amd/amd8111/nic.c deleted file mode 100644 index a4abd0360a..0000000000 --- a/src/southbridge/amd/amd8111/nic.c +++ /dev/null @@ -1,103 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * (C) 2004 Linux Networx - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include -#include -#include -#include -#include -#include "amd8111.h" -#include "chip.h" - -#define CMD3 0x54 - -typedef enum { - VAL3 = (1 << 31), /* VAL bit for byte 3 */ - VAL2 = (1 << 23), /* VAL bit for byte 2 */ - VAL1 = (1 << 15), /* VAL bit for byte 1 */ - VAL0 = (1 << 7), /* VAL bit for byte 0 */ -}VAL_BITS; - -typedef enum { - /* VAL3 */ - ASF_INIT_DONE_ALIAS = (1 << 29), - /* VAL2 */ - JUMBO = (1 << 21), - VSIZE = (1 << 20), - VLONLY = (1 << 19), - VL_TAG_DEL = (1 << 18), - /* VAL1 */ - EN_PMGR = (1 << 14), - INTLEVEL = (1 << 13), - FORCE_FULL_DUPLEX = (1 << 12), - FORCE_LINK_STATUS = (1 << 11), - APEP = (1 << 10), - MPPLBA = (1 << 9), - /* VAL0 */ - RESET_PHY_PULSE = (1 << 2), - RESET_PHY = (1 << 1), - PHY_RST_POL = (1 << 0), -}CMD3_BITS; - -static void nic_init(struct device *dev) -{ - struct southbridge_amd_amd8111_config *conf; - struct resource *resource; - u8 *mmio; - - conf = dev->chip_info; - resource = find_resource(dev, PCI_BASE_ADDRESS_0); - mmio = res2mmio(resource, 0, 0); - - /* Hard Reset PHY */ - printk(BIOS_DEBUG, "Resetting PHY... "); - if (conf->phy_lowreset) { - write32((mmio + CMD3), VAL0 | PHY_RST_POL | RESET_PHY); - } else { - write32((mmio + CMD3), VAL0 | RESET_PHY); - } - mdelay(15); - write32((mmio + CMD3), RESET_PHY); - printk(BIOS_DEBUG, "Done\n"); -} - -static void lpci_set_subsystem(struct device *dev, unsigned int vendor, - unsigned int device) -{ - pci_write_config32(dev, 0xc8, - ((device & 0xffff) << 16) | (vendor & 0xffff)); -} - -static struct pci_operations lops_pci = { - .set_subsystem = lpci_set_subsystem, -}; - -static struct device_operations nic_ops = { - .read_resources = pci_dev_read_resources, - .set_resources = pci_dev_set_resources, - .enable_resources = pci_dev_enable_resources, - .init = nic_init, - .scan_bus = 0, - .enable = amd8111_enable, - .ops_pci = &lops_pci, -}; - -static const struct pci_driver nic_driver __pci_driver = { - .ops = &nic_ops, - .vendor = PCI_VENDOR_ID_AMD, - .device = PCI_DEVICE_ID_AMD_8111_NIC, -}; diff --git a/src/southbridge/amd/amd8111/pci.c b/src/southbridge/amd/amd8111/pci.c deleted file mode 100644 index ae47716627..0000000000 --- a/src/southbridge/amd/amd8111/pci.c +++ /dev/null @@ -1,79 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include -#include -#include "amd8111.h" - -static void pci_init(struct device *dev) -{ - - /* Enable pci error detecting */ - uint32_t dword; - - /* System error enable */ - dword = pci_read_config32(dev, 0x04); - dword |= (1<<8); /* System error enable */ - dword |= (7<<28); /* Clear possible errors */ - pci_write_config32(dev, 0x04, dword); - - /* System,Parity,timer,and abort error enable */ - dword = pci_read_config32(dev, 0x3c); - dword |= (1<<16); /* Parity */ - dword |= (1<<17); /* System */ - dword |= (1<<21); /* Master abort */ -// dword &= ~(1<<21); /* Master abort */ -// dword |= (1<<27); /* Discard timer */ - dword &= ~(1<<27); /* Discard timer */ - dword |= (1<<26); /* DTSTAT error clear */ - pci_write_config32(dev, 0x3c, dword); - - /* CRC flood enable */ - dword = pci_read_config32(dev, 0xc4); - dword |= (1<<1); /* CRC Flood enable */ - dword |= (1<<8); /* Clear any CRC errors */ - dword |= (1<<4); /* Clear any LKFAIL errors */ - pci_write_config32(dev, 0xc4, dword); - - /* Clear possible errors */ - dword = pci_read_config32(dev, 0x1c); - dword |= (1<<27); /* STA */ - dword |= (1<<28); /* RTA */ - dword |= (1<<29); /* RMA */ - dword |= (1<<30); /* RSE */ - dword |= (1<<31); /* DPE */ - dword |= (1<<24); /* MDPE */ - pci_write_config32(dev, 0x1c, dword); -} - -static struct pci_operations lops_pci = { - .set_subsystem = 0, -}; - -static struct device_operations pci_ops = { - .read_resources = pci_bus_read_resources, - .set_resources = pci_dev_set_resources, - .enable_resources = pci_bus_enable_resources, - .init = pci_init, - .scan_bus = pci_scan_bridge, - /* PCI Subordinate bus reset is not implemented */ - .ops_pci = &lops_pci, -}; - -static const struct pci_driver pci_driver __pci_driver = { - .ops = &pci_ops, - .vendor = PCI_VENDOR_ID_AMD, - .device = PCI_DEVICE_ID_AMD_8111_PCI, -}; diff --git a/src/southbridge/amd/amd8111/reset.c b/src/southbridge/amd/amd8111/reset.c deleted file mode 100644 index b175be2727..0000000000 --- a/src/southbridge/amd/amd8111/reset.c +++ /dev/null @@ -1,59 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - - -#define __SIMPLE_DEVICE__ - -#include -#include -#include -#include - - -#define PCI_DEV_INVALID (0xffffffffU) -static pci_devfn_t pci_io_locate_device_on_bus(unsigned int pci_id, unsigned int bus) -{ - pci_devfn_t dev, last; - dev = PCI_DEV(bus, 0, 0); - last = PCI_DEV(bus, 31, 7); - for (; dev <= last; dev += PCI_DEV(0,0,1)) { - unsigned int id; - id = pci_io_read_config32(dev, 0); - if (id == pci_id) { - return dev; - } - } - return PCI_DEV_INVALID; -} - -#include "../../../northbridge/amd/amdk8/reset_test.c" - -void do_board_reset(void) -{ - pci_devfn_t dev; - unsigned int bus; - unsigned int node = 0; - unsigned int link = get_sblk(); - - /* Find the device. - * There can only be one 8111 on a hypertransport chain/bus. - */ - bus = node_link_to_bus(node, link); - dev = pci_io_locate_device_on_bus( - PCI_ID(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8111_ISA), - bus); - - /* Reset */ - set_bios_reset(); - pci_io_write_config8(dev, 0x47, 1); -} diff --git a/src/southbridge/amd/amd8111/smbus.c b/src/southbridge/amd/amd8111/smbus.c deleted file mode 100644 index aa580fecbb..0000000000 --- a/src/southbridge/amd/amd8111/smbus.c +++ /dev/null @@ -1,52 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * (C) 2004 Linux Networx - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include -#include -#include -#include "amd8111.h" - - -static void lpci_set_subsystem(struct device *dev, unsigned int vendor, - unsigned int device) -{ - pci_write_config32(dev, 0x44, - ((device & 0xffff) << 16) | (vendor & 0xffff)); -} - -static struct smbus_bus_operations lops_smbus_bus = { - /* I haven't seen the 2.0 SMBUS controller used yet. */ -}; -static struct pci_operations lops_pci = { - .set_subsystem = lpci_set_subsystem, -}; -static struct device_operations smbus_ops = { - .read_resources = pci_dev_read_resources, - .set_resources = pci_dev_set_resources, - .enable_resources = pci_dev_enable_resources, - .init = 0, - .scan_bus = scan_smbus, - .enable = amd8111_enable, - .ops_pci = &lops_pci, - .ops_smbus_bus = &lops_smbus_bus, -}; - -static const struct pci_driver smbus_driver __pci_driver = { - .ops = &smbus_ops, - .vendor = PCI_VENDOR_ID_AMD, - .device = PCI_DEVICE_ID_AMD_8111_SMB, -}; diff --git a/src/southbridge/amd/amd8111/usb.c b/src/southbridge/amd/amd8111/usb.c deleted file mode 100644 index 741cad9d37..0000000000 --- a/src/southbridge/amd/amd8111/usb.c +++ /dev/null @@ -1,46 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * (C) 2004 Linux Networx - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include -#include -#include "amd8111.h" - - -static void lpci_set_subsystem(struct device *dev, unsigned int vendor, - unsigned int device) -{ - pci_write_config32(dev, 0x70, - ((device & 0xffff) << 16) | (vendor & 0xffff)); -} - -static struct pci_operations lops_pci = { - .set_subsystem = lpci_set_subsystem, -}; - -static struct device_operations usb_ops = { - .read_resources = pci_dev_read_resources, - .set_resources = pci_dev_set_resources, - .enable_resources = pci_dev_enable_resources, - .init = 0, - .ops_pci = &lops_pci, -}; - -static const struct pci_driver usb_driver __pci_driver = { - .ops = &usb_ops, - .vendor = PCI_VENDOR_ID_AMD, - .device = PCI_DEVICE_ID_AMD_8111_USB, -}; diff --git a/src/southbridge/amd/amd8111/usb2.c b/src/southbridge/amd/amd8111/usb2.c deleted file mode 100644 index b41c0bee66..0000000000 --- a/src/southbridge/amd/amd8111/usb2.c +++ /dev/null @@ -1,43 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright 2003 Tyan - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - - -#include -#include -#include -#include -#include "amd8111.h" - -static void amd8111_usb2_enable(struct device *dev) -{ - // Due to buggy USB2 we force it to disable. - dev->enabled = 0; - amd8111_enable(dev); - printk(BIOS_DEBUG, "USB2 disabled.\n"); -} - -static struct device_operations usb2_ops = { - .read_resources = pci_dev_read_resources, - .set_resources = pci_dev_set_resources, - .enable_resources = pci_dev_enable_resources, - .scan_bus = 0, - .enable = amd8111_usb2_enable, -}; - -static const struct pci_driver usb2_driver __pci_driver = { - .ops = &usb2_ops, - .vendor = PCI_VENDOR_ID_AMD, - .device = PCI_DEVICE_ID_AMD_8111_USB2, -}; From 979d4ce02f489996aeca0ae7ec4437712012619c Mon Sep 17 00:00:00 2001 From: Arthur Heymans Date: Tue, 19 Nov 2019 17:22:04 +0100 Subject: [PATCH 0291/1242] sb/amd/amd8132: Drop support MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Relocatable ramstage, postcar stage and C_ENVIRONMENT_BOOTBLOCK are now mandatory features, which this platform lacks. Change-Id: I83d7025280b75088c37049f34564610612996e1b Signed-off-by: Arthur Heymans Reviewed-on: https://review.coreboot.org/c/coreboot/+/36965 Reviewed-by: Kyösti Mälkki Reviewed-by: Angel Pons Reviewed-by: HAOUAS Elyes Tested-by: build bot (Jenkins) --- src/southbridge/amd/amd8132/Kconfig | 2 - src/southbridge/amd/amd8132/Makefile.inc | 5 - src/southbridge/amd/amd8132/bridge.c | 424 ----------------------- 3 files changed, 431 deletions(-) delete mode 100644 src/southbridge/amd/amd8132/Kconfig delete mode 100644 src/southbridge/amd/amd8132/Makefile.inc delete mode 100644 src/southbridge/amd/amd8132/bridge.c diff --git a/src/southbridge/amd/amd8132/Kconfig b/src/southbridge/amd/amd8132/Kconfig deleted file mode 100644 index 09e7ac58d5..0000000000 --- a/src/southbridge/amd/amd8132/Kconfig +++ /dev/null @@ -1,2 +0,0 @@ -config SOUTHBRIDGE_AMD_AMD8132 - bool diff --git a/src/southbridge/amd/amd8132/Makefile.inc b/src/southbridge/amd/amd8132/Makefile.inc deleted file mode 100644 index 75dce39f54..0000000000 --- a/src/southbridge/amd/amd8132/Makefile.inc +++ /dev/null @@ -1,5 +0,0 @@ -ifeq ($(CONFIG_SOUTHBRIDGE_AMD_AMD8132),y) - -ramstage-y += bridge.c - -endif diff --git a/src/southbridge/amd/amd8132/bridge.c b/src/southbridge/amd/amd8132/bridge.c deleted file mode 100644 index 1088dda79c..0000000000 --- a/src/southbridge/amd/amd8132/bridge.c +++ /dev/null @@ -1,424 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2005,2010 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include -#include -#include -#include -#include - -#define NMI_OFF 0 - -#define NPUML 0xD9 /* Non prefetchable upper memory limit */ -#define NPUMB 0xD8 /* Non prefetchable upper memory base */ - -static void amd8132_walk_children(struct bus *bus, - void (*visit)(struct device *dev, void *ptr), void *ptr) -{ - struct device *child; - for (child = bus->children; child; child = child->sibling) { - if (child->path.type != DEVICE_PATH_PCI) { - continue; - } - if (child->hdr_type == PCI_HEADER_TYPE_BRIDGE) { - amd8132_walk_children(child->link_list, visit, ptr); - } - visit(child, ptr); - } -} - -struct amd8132_bus_info { - unsigned int sstatus; - unsigned int rev; - int master_devices; - int max_func; -}; - -static void amd8132_count_dev(struct device *dev, void *ptr) -{ - struct amd8132_bus_info *info = ptr; - /* Don't count pci bridges */ - if (dev->hdr_type != PCI_HEADER_TYPE_BRIDGE) { - info->master_devices++; - } - if (PCI_FUNC(dev->path.pci.devfn) > info->max_func) { - info->max_func = PCI_FUNC(dev->path.pci.devfn); - } -} - - -static void amd8132_pcix_tune_dev(struct device *dev, void *ptr) -{ - struct amd8132_bus_info *info = ptr; - unsigned int cap; - unsigned int status, cmd, orig_cmd; - unsigned int max_read, max_tran; - int sibs; - - if (dev->hdr_type != PCI_HEADER_TYPE_NORMAL) { - return; - } - cap = pci_find_capability(dev, PCI_CAP_ID_PCIX); - if (!cap) { - return; - } - /* How many siblings does this device have? */ - sibs = info->master_devices - 1; - - printk(BIOS_DEBUG, "%s AMD8132 PCI-X tuning\n", dev_path(dev)); - status = pci_read_config32(dev, cap + PCI_X_STATUS); - orig_cmd = cmd = pci_read_config16(dev,cap + PCI_X_CMD); - - max_read = (status & PCI_X_STATUS_MAX_READ) >> 21; - max_tran = (status & PCI_X_STATUS_MAX_SPLIT) >> 23; - - if (info->rev == 0x01) { // only a1 need it - /* Errata #53 Limit the number of split transactions to avoid starvation */ - if (sibs >= 2) { - /* At most 2 outstanding split transactions when we have - * 3 or more bus master devices on the bus. - */ - if (max_tran > 1) { - max_tran = 1; - } - } - else if (sibs == 1) { - /* At most 4 outstanding split transactions when we have - * 2 bus master devices on the bus. - */ - if (max_tran > 3) { - max_tran = 3; - } - } - else { - /* At most 8 outstanding split transactions when we have - * only one bus master device on the bus. - */ - if (max_tran > 4) { - max_tran = 4; - } - } - } - - if (max_read != ((cmd & PCI_X_CMD_MAX_READ) >> 2)) { - cmd &= ~PCI_X_CMD_MAX_READ; - cmd |= max_read << 2; - } - if (max_tran != ((cmd & PCI_X_CMD_MAX_SPLIT) >> 4)) { - cmd &= ~PCI_X_CMD_MAX_SPLIT; - cmd |= max_tran << 4; - } - - /* Don't attempt to handle PCI-X errors */ - cmd &= ~PCI_X_CMD_DPERR_E; - if (orig_cmd != cmd) { - pci_write_config16(dev, cap + PCI_X_CMD, cmd); - } - - -} -static void amd8132_scan_bus(struct bus *bus, - unsigned int min_devfn, unsigned int max_devfn) -{ - struct amd8132_bus_info info; - unsigned int pos; - - /* Find the children on the bus */ - pci_scan_bus(bus, min_devfn, max_devfn); - - /* Find the revision of the 8132 */ - info.rev = pci_read_config8(bus->dev, PCI_CLASS_REVISION); - - /* Find the pcix capability and get the secondary bus status */ - pos = pci_find_capability(bus->dev, PCI_CAP_ID_PCIX); - info.sstatus = pci_read_config16(bus->dev, pos + PCI_X_SEC_STATUS); - - /* Print the PCI-X bus speed */ - printk(BIOS_DEBUG, "PCI: %02x: %s sstatus=%04x rev=%02x\n", bus->secondary, pcix_speed(info.sstatus), info.sstatus, info.rev); - - - /* Examine the bus and find out how loaded it is */ - info.max_func = 0; - info.master_devices = 0; - amd8132_walk_children(bus, amd8132_count_dev, &info); - -#if 0 - /* Disable the bus if there are no devices on it - */ - if (!bus->children) - { - unsigned int pcix_misc; - /* Disable all of my children */ - disable_children(bus); - - /* Remember the device is disabled */ - bus->dev->enabled = 0; - - /* Disable the PCI-X clocks */ - pcix_misc = pci_read_config32(bus->dev, 0x40); - pcix_misc &= ~(0x1f << 16); - pci_write_config32(bus->dev, 0x40, pcix_misc); - - return; - } -#endif - - /* If we are in conventional PCI mode nothing more is necessary. - */ - if (PCI_X_SSTATUS_MFREQ(info.sstatus) == PCI_X_SSTATUS_CONVENTIONAL_PCI) { - return; - } - - /* Tune the devices on the bus */ - amd8132_walk_children(bus, amd8132_pcix_tune_dev, &info); -} - -static void amd8132_scan_bridge(struct device *dev) -{ - do_pci_scan_bridge(dev, amd8132_scan_bus); -} - - -static void amd8132_pcix_init(struct device *dev) -{ - uint32_t dword; - uint8_t byte; - unsigned int chip_rev; - - /* Find the revision of the 8132 */ - chip_rev = pci_read_config8(dev, PCI_CLASS_REVISION); - - /* Enable memory write and invalidate ??? */ - dword = pci_read_config32(dev, 0x04); - dword |= 0x10; - dword &= ~(1<<6); // PERSP Parity Error Response - pci_write_config32(dev, 0x04, dword); - - if (chip_rev == 0x01) { - /* Errata #37 */ - byte = pci_read_config8(dev, 0x0c); - if (byte == 0x08) - pci_write_config8(dev, 0x0c, 0x10); - -#if 0 - /* Errata #59*/ - dword = pci_read_config32(dev, 0x40); - dword &= ~(1<<31); - pci_write_config32(dev, 0x40, dword); -#endif - - } - - /* Set up error reporting, enable all */ - /* system error enable */ - dword = pci_read_config32(dev, 0x04); - dword |= (1<<8); - pci_write_config32(dev, 0x04, dword); - - /* system and error parity enable */ - dword = pci_read_config32(dev, 0x3c); - dword |= (3<<16); - pci_write_config32(dev, 0x3c, dword); - - dword = pci_read_config32(dev, 0x40); -// dword &= ~(1<<31); /* WriteChainEnable */ - dword |= (1<<31); - dword |= (1<<7);// must set to 1 - dword |= (3<<21); //PCIErrorSerrDisable - pci_write_config32(dev, 0x40, dword); - - /* EXTARB = 1, COMPAT = 0 */ - dword = pci_read_config32(dev, 0x48); - dword |= (1<<3); - dword &= ~(1<<0); - dword |= (1<<15); //CLEARPCILOG_L - dword |= (1<<19); //PERR FATAL Enable - dword |= (1<<22); // SERR FATAL Enable - dword |= (1<<23); // LPMARBENABLE - dword |= (0x61<<24); //LPMARBCOUNT - pci_write_config32(dev, 0x48, dword); - - dword = pci_read_config32(dev, 0x4c); - dword |= (1<<6); //Initial prefetch for memory read line request - dword |= (1<<9); //continuous prefetch Enable for memory read line request - pci_write_config32(dev, 0x4c, dword); - - - /* Disable Single-Bit-Error Correction [30] = 0 */ - dword = pci_read_config32(dev, 0x70); - dword &= ~(1<<30); - pci_write_config32(dev, 0x70, dword); - - //link - dword = pci_read_config32(dev, 0xd4); - dword |= (0x5c<<16); - pci_write_config32(dev, 0xd4, dword); - - /* TxSlack0 [16:17] = 0, RxHwLookahdEn0 [18] = 1, TxSlack1 [24:25] = 0, RxHwLookahdEn1 [26] = 1 */ - dword = pci_read_config32(dev, 0xdc); - dword |= (1<<1) | (1<<4); // stream disable 1 to 0, DBLINSRATE - dword |= (1<<18)|(1<<26); - dword &= ~((3<<16)|(3<<24)); - pci_write_config32(dev, 0xdc, dword); - - /* Set up CRC flood enable */ - dword = pci_read_config32(dev, 0xc0); - if (dword) { /* do device A only */ -#if 0 - dword = pci_read_config32(dev, 0xc4); - dword |= (1<<1); - pci_write_config32(dev, 0xc4, dword); - dword = pci_read_config32(dev, 0xc8); - dword |= (1<<1); - pci_write_config32(dev, 0xc8, dword); -#endif - - if (chip_rev == 0x11) { - /* [18] Clock Gate Enable = 1 */ - dword = pci_read_config32(dev, 0xf0); - dword |= 0x00040008; - pci_write_config32(dev, 0xf0, dword); - } - - } - return; -} - -#define BRIDGE_40_BIT_SUPPORT 0 -#if BRIDGE_40_BIT_SUPPORT -static void bridge_read_resources(struct device *dev) -{ - struct resource *res; - pci_bus_read_resources(dev); - res = find_resource(dev, PCI_MEMORY_BASE); - if (res) { - res->limit = 0xffffffffffULL; - } -} - -static void bridge_set_resources(struct device *dev) -{ - struct resource *res; - res = find_resource(dev, PCI_MEMORY_BASE); - if (res) { - resource_t base, end; - /* set the memory range */ - dev->command |= PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER; - res->flags |= IORESOURCE_STORED; - base = res->base; - end = resource_end(res); - pci_write_config16(dev, PCI_MEMORY_BASE, base >> 16); - pci_write_config8(dev, NPUML, (base >> 32) & 0xff); - pci_write_config16(dev, PCI_MEMORY_LIMIT, end >> 16); - pci_write_config8(dev, NPUMB, (end >> 32) & 0xff); - - report_resource_stored(dev, res, ""); - } - pci_dev_set_resources(dev); -} -#endif /* BRIDGE_40_BIT_SUPPORT */ - -static struct device_operations pcix_ops = { -#if BRIDGE_40_BIT_SUPPORT - .read_resources = bridge_read_resources, - .set_resources = bridge_set_resources, -#else - .read_resources = pci_bus_read_resources, - .set_resources = pci_dev_set_resources, -#endif - .enable_resources = pci_bus_enable_resources, - .init = amd8132_pcix_init, - .scan_bus = amd8132_scan_bridge, - .reset_bus = pci_bus_reset, -}; - -static const struct pci_driver pcix_driver __pci_driver = { - .ops = &pcix_ops, - .vendor = PCI_VENDOR_ID_AMD, - .device = 0x7458, -}; - -static void ioapic_enable(struct device *dev) -{ - uint32_t value; - - value = pci_read_config32(dev, 0x44); - if (dev->enabled) { - value |= ((1 << 1) | (1 << 0)); - } else { - value &= ~((1 << 1) | (1 << 0)); - } - pci_write_config32(dev, 0x44, value); -} -static void amd8132_ioapic_init(struct device *dev) -{ - uint32_t dword; - unsigned int chip_rev; - - /* Find the revision of the 8132 */ - chip_rev = pci_read_config8(dev, PCI_CLASS_REVISION); - - if (chip_rev == 0x01) { -#if 0 - /* Errata #43 */ - dword = pci_read_config32(dev, 0xc8); - dword |= (0x3<<23); - pci_write_config32(dev, 0xc8, dword); -#endif - - } - - - if ((chip_rev == 0x11) || (chip_rev == 0x12)) { - //for b1 b2 - /* Errata #73 */ - dword = pci_read_config32(dev, 0x80); - dword |= (0x1f<<5); - pci_write_config32(dev, 0x80, dword); - dword = pci_read_config32(dev, 0x88); - dword |= (0x1f<<5); - pci_write_config32(dev, 0x88, dword); - - /* Errata #74 */ - dword = pci_read_config32(dev, 0x7c); - dword &= ~(0x3<<30); - dword |= (0x01<<30); - pci_write_config32(dev, 0x7c, dword); - } - -} - -static struct pci_operations pci_ops_pci_dev = { - .set_subsystem = pci_dev_set_subsystem, -}; -static struct device_operations ioapic_ops = { - .read_resources = pci_dev_read_resources, - .set_resources = pci_dev_set_resources, - .enable_resources = pci_dev_enable_resources, - .init = amd8132_ioapic_init, - .scan_bus = 0, - .enable = ioapic_enable, - .ops_pci = &pci_ops_pci_dev, -}; - -static const struct pci_driver ioapic_driver __pci_driver = { - .ops = &ioapic_ops, - .vendor = PCI_VENDOR_ID_AMD, - .device = 0x7459, - -}; From ecebee0561cf3e06bfba55509a5b7bebdb54d998 Mon Sep 17 00:00:00 2001 From: Arthur Heymans Date: Tue, 19 Nov 2019 17:22:29 +0100 Subject: [PATCH 0292/1242] sb/amd/rs780: Drop support MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Relocatable ramstage, postcar stage and C_ENVIRONMENT_BOOTBLOCK are now mandatory features, which platforms using this code lack. Change-Id: I00d260f22badb712a963b907f7beb8fbb5b71eac Signed-off-by: Arthur Heymans Reviewed-on: https://review.coreboot.org/c/coreboot/+/36966 Reviewed-by: Kyösti Mälkki Reviewed-by: Angel Pons Reviewed-by: HAOUAS Elyes Tested-by: build bot (Jenkins) --- src/southbridge/amd/rs780/Kconfig | 17 - src/southbridge/amd/rs780/Makefile.inc | 11 - src/southbridge/amd/rs780/chip.h | 36 - src/southbridge/amd/rs780/cmn.c | 399 ------ src/southbridge/amd/rs780/early_setup.c | 631 --------- src/southbridge/amd/rs780/gfx.c | 1572 ----------------------- src/southbridge/amd/rs780/ht.c | 86 -- src/southbridge/amd/rs780/pcie.c | 406 ------ src/southbridge/amd/rs780/rev.h | 23 - src/southbridge/amd/rs780/rs780.c | 363 ------ src/southbridge/amd/rs780/rs780.h | 227 ---- 11 files changed, 3771 deletions(-) delete mode 100644 src/southbridge/amd/rs780/Kconfig delete mode 100644 src/southbridge/amd/rs780/Makefile.inc delete mode 100644 src/southbridge/amd/rs780/chip.h delete mode 100644 src/southbridge/amd/rs780/cmn.c delete mode 100644 src/southbridge/amd/rs780/early_setup.c delete mode 100644 src/southbridge/amd/rs780/gfx.c delete mode 100644 src/southbridge/amd/rs780/ht.c delete mode 100644 src/southbridge/amd/rs780/pcie.c delete mode 100644 src/southbridge/amd/rs780/rev.h delete mode 100644 src/southbridge/amd/rs780/rs780.c delete mode 100644 src/southbridge/amd/rs780/rs780.h diff --git a/src/southbridge/amd/rs780/Kconfig b/src/southbridge/amd/rs780/Kconfig deleted file mode 100644 index 9c71694f17..0000000000 --- a/src/southbridge/amd/rs780/Kconfig +++ /dev/null @@ -1,17 +0,0 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2010 Advanced Micro Devices, Inc. -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; version 2 of the License. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## - -config SOUTHBRIDGE_AMD_RS780 - bool diff --git a/src/southbridge/amd/rs780/Makefile.inc b/src/southbridge/amd/rs780/Makefile.inc deleted file mode 100644 index 36086e90c2..0000000000 --- a/src/southbridge/amd/rs780/Makefile.inc +++ /dev/null @@ -1,11 +0,0 @@ -ifeq ($(CONFIG_SOUTHBRIDGE_AMD_RS780),y) - -romstage-y += early_setup.c - -ramstage-y += rs780.c -ramstage-y += cmn.c -ramstage-y += pcie.c -ramstage-y += ht.c -ramstage-y += gfx.c - -endif diff --git a/src/southbridge/amd/rs780/chip.h b/src/southbridge/amd/rs780/chip.h deleted file mode 100644 index ca86a67b27..0000000000 --- a/src/southbridge/amd/rs780/chip.h +++ /dev/null @@ -1,36 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2010 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef RS780_CHIP_H -#define RS780_CHIP_H - -/* Member variables are defined in devicetree.cb. */ -struct southbridge_amd_rs780_config -{ - u8 gppsb_configuration; /* The configuration of General Purpose Port, A/B/C/D/E. */ - u8 gpp_configuration; /* The configuration of General Purpose Port, C/D. */ - u16 port_enable; /* Which port is enabled? GFX(2,3), GPP(4,5,6,7) */ - u8 gfx_dev2_dev3; /* for GFX Core initialization REFCLK_SEL */ - u8 gfx_dual_slot; /* Is it dual graphics slots */ - u8 gfx_lane_reversal; /* Single/Dual slot lan reversal */ - u8 gfx_tmds; /* whether support TMDS? */ - u8 gfx_compliance; /* whether support compliance? */ - u8 gfx_reconfiguration; /* Dynamic Link Width Control */ - u8 gfx_link_width; /* Desired width of lane 2 */ - u8 gfx_pcie_config; /* GFX PCIE Modes */ - u8 gfx_ddi_config; /* GFX DDI Modes */ -}; - -#endif /* RS780_CHIP_H */ diff --git a/src/southbridge/amd/rs780/cmn.c b/src/southbridge/amd/rs780/cmn.c deleted file mode 100644 index 1520748796..0000000000 --- a/src/southbridge/amd/rs780/cmn.c +++ /dev/null @@ -1,399 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2010 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include "rs780.h" - -static u32 nb_read_index(struct device *dev, u32 index_reg, u32 index) -{ - pci_write_config32(dev, index_reg, index); - return pci_read_config32(dev, index_reg + 0x4); -} - -static void nb_write_index(struct device *dev, u32 index_reg, u32 index, u32 data) -{ - pci_write_config32(dev, index_reg, index); - pci_write_config32(dev, index_reg + 0x4, data); -} - -/* extension registers */ -u32 pci_ext_read_config32(struct device *nb_dev, struct device *dev, u32 reg) -{ - /* get BAR3 base address for nbcfg0x1c */ - u32 addr = pci_read_config32(nb_dev, 0x1c) & ~0xF; - printk(BIOS_DEBUG, "addr=%x,bus=%x,devfn=%x\n", addr, dev->bus->secondary, - dev->path.pci.devfn); - addr |= dev->bus->secondary << 20 | /* bus num */ - dev->path.pci.devfn << 12 | reg; - return *((u32 *) addr); -} - -void pci_ext_write_config32(struct device *nb_dev, struct device *dev, u32 reg_pos, u32 mask, u32 val) -{ - u32 reg_old, reg; - - /* get BAR3 base address for nbcfg0x1c */ - u32 addr = pci_read_config32(nb_dev, 0x1c) & ~0xF; - /*printk(BIOS_DEBUG, "write: addr=%x,bus=%x,devfn=%x\n", addr, dev->bus->secondary, - dev->path.pci.devfn);*/ - addr |= dev->bus->secondary << 20 | /* bus num */ - dev->path.pci.devfn << 12 | reg_pos; - - reg = reg_old = *((u32 *) addr); - reg &= ~mask; - reg |= val; - if (reg != reg_old) { - *((u32 *) addr) = reg; - } -} - -u32 nbmisc_read_index(struct device *nb_dev, u32 index) -{ - return nb_read_index((nb_dev), NBMISC_INDEX, (index)); -} - -void nbmisc_write_index(struct device *nb_dev, u32 index, u32 data) -{ - nb_write_index((nb_dev), NBMISC_INDEX, ((index) | 0x80), (data)); -} - -u32 nbpcie_p_read_index(struct device *dev, u32 index) -{ - return nb_read_index((dev), NBPCIE_INDEX, (index)); -} - -void nbpcie_p_write_index(struct device *dev, u32 index, u32 data) -{ - nb_write_index((dev), NBPCIE_INDEX, (index), (data)); -} - -u32 nbpcie_ind_read_index(struct device *nb_dev, u32 index) -{ - return nb_read_index((nb_dev), NBPCIE_INDEX, (index)); -} - -void nbpcie_ind_write_index(struct device *nb_dev, u32 index, u32 data) -{ - nb_write_index((nb_dev), NBPCIE_INDEX, (index), (data)); -} - -u32 htiu_read_index(struct device *nb_dev, u32 index) -{ - return nb_read_index((nb_dev), NBHTIU_INDEX, (index)); -} - -void htiu_write_index(struct device *nb_dev, u32 index, u32 data) -{ - nb_write_index((nb_dev), NBHTIU_INDEX, ((index) | 0x100), (data)); -} - -u32 nbmc_read_index(struct device *nb_dev, u32 index) -{ - return nb_read_index((nb_dev), NBMC_INDEX, (index)); -} - -void nbmc_write_index(struct device *nb_dev, u32 index, u32 data) -{ - nb_write_index((nb_dev), NBMC_INDEX, ((index) | 1 << 9), (data)); -} - -void set_nbcfg_enable_bits(struct device *nb_dev, u32 reg_pos, u32 mask, u32 val) -{ - u32 reg_old, reg; - reg = reg_old = pci_read_config32(nb_dev, reg_pos); - reg &= ~mask; - reg |= val; - if (reg != reg_old) { - pci_write_config32(nb_dev, reg_pos, reg); - } -} - -void set_nbcfg_enable_bits_8(struct device *nb_dev, u32 reg_pos, u8 mask, u8 val) -{ - u8 reg_old, reg; - reg = reg_old = pci_read_config8(nb_dev, reg_pos); - reg &= ~mask; - reg |= val; - if (reg != reg_old) { - pci_write_config8(nb_dev, reg_pos, reg); - } -} - -void set_nbmc_enable_bits(struct device *nb_dev, u32 reg_pos, u32 mask, u32 val) -{ - u32 reg_old, reg; - reg = reg_old = nbmc_read_index(nb_dev, reg_pos); - reg &= ~mask; - reg |= val; - if (reg != reg_old) { - nbmc_write_index(nb_dev, reg_pos, reg); - } -} - -void set_htiu_enable_bits(struct device *nb_dev, u32 reg_pos, u32 mask, u32 val) -{ - u32 reg_old, reg; - reg = reg_old = htiu_read_index(nb_dev, reg_pos); - reg &= ~mask; - reg |= val; - if (reg != reg_old) { - htiu_write_index(nb_dev, reg_pos, reg); - } -} - -void set_nbmisc_enable_bits(struct device *nb_dev, u32 reg_pos, u32 mask, u32 val) -{ - u32 reg_old, reg; - reg = reg_old = nbmisc_read_index(nb_dev, reg_pos); - reg &= ~mask; - reg |= val; - if (reg != reg_old) { - nbmisc_write_index(nb_dev, reg_pos, reg); - } -} - -void set_pcie_enable_bits(struct device *dev, u32 reg_pos, u32 mask, u32 val) -{ - u32 reg_old, reg; - reg = reg_old = nb_read_index(dev, NBPCIE_INDEX, reg_pos); - reg &= ~mask; - reg |= val; - if (reg != reg_old) { - nb_write_index(dev, NBPCIE_INDEX, reg_pos, reg); - } -} - -/* - * To access bar3 we need to program PCI MMIO 7 in K8. - * in_out: - * 1: enable/enter k8 temp mmio base - * 0: disable/restore - */ -void ProgK8TempMmioBase(u8 in_out, u32 pcie_base_add, u32 mmio_base_add) -{ - /* K8 Function1 is address map */ - struct device *k8_f1 = pcidev_on_root(0x18, 1); - struct device *k8_f0 = pcidev_on_root(0x18, 0); - - if (in_out) { - u32 dword, sblk; - - /* Get SBLink value (HyperTransport I/O Hub Link ID). */ - dword = pci_read_config32(k8_f0, 0x64); - sblk = (dword >> 8) & 0x3; - - /* Fill MMIO limit/base pair. */ - pci_write_config32(k8_f1, 0xbc, - (((pcie_base_add + 0x10000000 - - 1) >> 8) & 0xffffff00) | 0x80 | (sblk << 4)); - pci_write_config32(k8_f1, 0xb8, (pcie_base_add >> 8) | 0x3); - pci_write_config32(k8_f1, 0xb4, - (((mmio_base_add + 0x10000000 - - 1) >> 8) & 0xffffff00) | (sblk << 4)); - pci_write_config32(k8_f1, 0xb0, (mmio_base_add >> 8) | 0x3); - } else { - pci_write_config32(k8_f1, 0xb8, 0); - pci_write_config32(k8_f1, 0xbc, 0); - pci_write_config32(k8_f1, 0xb0, 0); - pci_write_config32(k8_f1, 0xb4, 0); - } -} - -void PcieReleasePortTraining(struct device *nb_dev, struct device *dev, u32 port) -{ - switch (port) { - case 2: /* GFX, bit4-5 */ - case 3: - set_nbmisc_enable_bits(nb_dev, PCIE_LINK_CFG, - 1 << (port + 2), 0 << (port + 2)); - break; - case 4: /* GPPSB, bit20-24 */ - case 5: - case 6: - case 7: - set_nbmisc_enable_bits(nb_dev, PCIE_LINK_CFG, - 1 << (port + 17), 0 << (port + 17)); - break; - case 9: /* GPP, bit 4,5 of miscind 0x2D */ - case 10: - set_nbmisc_enable_bits(nb_dev, 0x2D, - 1 << (port - 5), 0 << (port - 5)); - break; - } -} - -/* - * Output: - * 0: no device is present. - * 1: device is present and is trained. - */ -u8 PcieTrainPort(struct device *nb_dev, struct device *dev, u32 port) -{ - u16 count = 5000; - u32 lc_state, reg, current_link_width, lane_mask; - int8_t current, res = 0; - u32 gfx_gpp_sb_sel; - switch (port) { - case 2 ... 3: - gfx_gpp_sb_sel = PCIE_CORE_INDEX_GFX; - break; - case 4 ... 7: - gfx_gpp_sb_sel = PCIE_CORE_INDEX_GPPSB; - break; - case 9 ... 10: - gfx_gpp_sb_sel = PCIE_CORE_INDEX_GPP; - break; - default: - return 0; - } - - while (count--) { - mdelay(40); - udelay(200); - lc_state = nbpcie_p_read_index(dev, 0xa5); /* lc_state */ - printk(BIOS_DEBUG, "PcieLinkTraining port=%x:lc current state=%x\n", - port, lc_state); - current = lc_state & 0x3f; /* get LC_CURRENT_STATE, bit0-5 */ - - switch (current) { - case 0x00: /* 0x00-0x04 means no device is present */ - case 0x01: - case 0x02: - case 0x03: - case 0x04: - res = 0; - count = 0; - break; - case 0x06: - /* read back current link width [6:4]. */ - current_link_width = (nbpcie_p_read_index(dev, 0xA2) >> 4) & 0x7; - /* 4 means 7:4 and 15:12 - * 3 means 7:2 and 15:10 - * 2 means 7:1 and 15:9 - * ignoring the reversal case - */ - lane_mask = (0xFF << (current_link_width - 2) * 2) & 0xFF; - reg = nbpcie_ind_read_index(nb_dev, 0x65 | gfx_gpp_sb_sel); - reg |= lane_mask << 8 | lane_mask; - reg = 0xE0E0; /* TODO: See the comments in rs780_pcie.c, at about line 145. */ - nbpcie_ind_write_index(nb_dev, 0x65 | gfx_gpp_sb_sel, reg); - printk(BIOS_DEBUG, "link_width=%x, lane_mask=%x", - current_link_width, lane_mask); - set_pcie_reset(); - mdelay(1); - set_pcie_dereset(); - break; - case 0x07: /* device is in compliance state (training sequence is done). Move to train the next device */ - res = 0; - count = 0; - break; - case 0x10: - reg = pci_ext_read_config32(nb_dev, dev, PCIE_VC0_RESOURCE_STATUS); - printk(BIOS_DEBUG, "PcieTrainPort reg=0x%x\n", reg); - /* check bit1 */ - if (reg & VC_NEGOTIATION_PENDING) { /* bit1=1 means the link needs to be re-trained. */ - /* set bit8=1, bit0-2=bit4-6 */ - u32 tmp; - reg = nbpcie_p_read_index(dev, PCIE_LC_LINK_WIDTH); - tmp = (reg >> 4) & 0x07; /* get bit4-6 */ - reg &= 0xfff8; /* clear bit0-2 */ - reg += tmp; /* merge */ - reg |= 1 << 8; - nbpcie_p_write_index(dev, PCIE_LC_LINK_WIDTH, reg); - count++; /* CIM said "keep in loop"? */ - } else { - res = 1; - count = 0; - } - break; - default: /* reset pcie */ - res = 0; - count = 0; /* break loop */ - break; - } - } - return res; -} - -/* - * Compliant with CIM_33's ATINB_SetToms. - * Set Top Of Memory below and above 4G. - */ -void rs780_set_tom(struct device *nb_dev) -{ - /* set TOM */ -#if CONFIG(GFXUMA) - pci_write_config32(nb_dev, 0x90, uma_memory_base); - //nbmc_write_index(nb_dev, 0x1e, uma_memory_base); -#else - /* 1GB system memory supposed */ - pci_write_config32(nb_dev, 0x90, 0x38000000); - //nbmc_write_index(nb_dev, 0x1e, 0x38000000); -#endif -} - -// extract single bit -u32 extractbit(u32 data, int bit_number) -{ - return (data >> bit_number) & 1; -} - -// extract bit field -u32 extractbits(u32 source, int lsb, int msb) -{ - int field_width = msb - lsb + 1; - u32 mask = 0xFFFFFFFF >> (32 - field_width); - return (source >> lsb) & mask; -} - -// return AMD cpuid family -int cpuidFamily(void) -{ - u32 baseFamily, extendedFamily, fms; - - fms = cpuid_eax (1); - baseFamily = extractbits (fms, 8, 11); - extendedFamily = extractbits (fms, 20, 27); - return baseFamily + extendedFamily; -} - - -// return non-zero for AMD family 0Fh processor found -int is_family0Fh(void) -{ - return cpuidFamily() == 0x0F; -} - - -// return non-zero for AMD family 10h processor found -int is_family10h(void) -{ - return cpuidFamily() == 0x10; -} - -__weak void set_pcie_reset(void) -{ -} - -__weak void set_pcie_dereset(void) -{ -} diff --git a/src/southbridge/amd/rs780/early_setup.c b/src/southbridge/amd/rs780/early_setup.c deleted file mode 100644 index 6be6423266..0000000000 --- a/src/southbridge/amd/rs780/early_setup.c +++ /dev/null @@ -1,631 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2010 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include -#include -#include -#include - -#include "rev.h" -#include "rs780.h" - -#define NBHTIU_INDEX 0x94 /* Note: It is different with RS690, whose HTIU index is 0xA8 */ -#define NBMISC_INDEX 0x60 -#define NBMC_INDEX 0xE8 - -static u32 nb_read_index(pci_devfn_t dev, u32 index_reg, u32 index) -{ - pci_write_config32(dev, index_reg, index); - return pci_read_config32(dev, index_reg + 0x4); -} - -static void nb_write_index(pci_devfn_t dev, u32 index_reg, u32 index, u32 data) -{ - pci_write_config32(dev, index_reg, index /* | 0x80 */); - pci_write_config32(dev, index_reg + 0x4, data); -} - -static u32 nbmisc_read_index(pci_devfn_t nb_dev, u32 index) -{ - return nb_read_index((nb_dev), NBMISC_INDEX, (index)); -} - -static void nbmisc_write_index(pci_devfn_t nb_dev, u32 index, u32 data) -{ - nb_write_index((nb_dev), NBMISC_INDEX, ((index) | 0x80), (data)); -} - -static u32 htiu_read_index(pci_devfn_t nb_dev, u32 index) -{ - return nb_read_index((nb_dev), NBHTIU_INDEX, (index)); -} - -static void htiu_write_index(pci_devfn_t nb_dev, u32 index, u32 data) -{ - nb_write_index((nb_dev), NBHTIU_INDEX, ((index) | 0x100), (data)); -} - -static u32 nbmc_read_index(pci_devfn_t nb_dev, u32 index) -{ - return nb_read_index((nb_dev), NBMC_INDEX, (index)); -} - -static void nbmc_write_index(pci_devfn_t nb_dev, u32 index, u32 data) -{ - nb_write_index((nb_dev), NBMC_INDEX, ((index) | 1 << 9), (data)); -} - -static void set_htiu_enable_bits(pci_devfn_t nb_dev, u32 reg_pos, u32 mask, - u32 val) -{ - u32 reg_old, reg; - reg = reg_old = htiu_read_index(nb_dev, reg_pos); - reg &= ~mask; - reg |= val; - if (reg != reg_old) { - htiu_write_index(nb_dev, reg_pos, reg); - } -} - -static void set_nbmisc_enable_bits(pci_devfn_t nb_dev, u32 reg_pos, u32 mask, - u32 val) -{ - u32 reg_old, reg; - reg = reg_old = nbmisc_read_index(nb_dev, reg_pos); - reg &= ~mask; - reg |= val; - if (reg != reg_old) { - nbmisc_write_index(nb_dev, reg_pos, reg); - } -} - -static void set_nbcfg_enable_bits(pci_devfn_t nb_dev, u32 reg_pos, u32 mask, - u32 val) -{ - u32 reg_old, reg; - reg = reg_old = pci_read_config32(nb_dev, reg_pos); - reg &= ~mask; - reg |= val; - if (reg != reg_old) { - pci_write_config32(nb_dev, reg_pos, reg); - } -} -/* family 10 only, for reg > 0xFF */ -#if CONFIG(NORTHBRIDGE_AMD_AMDFAM10) -static void set_fam10_ext_cfg_enable_bits(pci_devfn_t fam10_dev, u32 reg_pos, - u32 mask, u32 val) -{ - u32 reg_old, reg; - reg = reg_old = Get_NB32(fam10_dev, reg_pos); - reg &= ~mask; - reg |= val; - if (reg != reg_old) { - Set_NB32(fam10_dev, reg_pos, reg); - } -} -#else -#define set_fam10_ext_cfg_enable_bits(a, b, c, d) do {} while (0) -#endif - - -static void set_nbcfg_enable_bits_8(pci_devfn_t nb_dev, u32 reg_pos, u8 mask, - u8 val) -{ - u8 reg_old, reg; - reg = reg_old = pci_read_config8(nb_dev, reg_pos); - reg &= ~mask; - reg |= val; - if (reg != reg_old) { - pci_write_config8(nb_dev, reg_pos, reg); - } -} - -static void set_nbmc_enable_bits(pci_devfn_t nb_dev, u32 reg_pos, u32 mask, - u32 val) -{ - u32 reg_old, reg; - reg = reg_old = nbmc_read_index(nb_dev, reg_pos); - reg &= ~mask; - reg |= val; - if (reg != reg_old) { - nbmc_write_index(nb_dev, reg_pos, reg); - } -} - -static u8 is_famly10(void) -{ - return (cpuid_eax(1) & 0xff00000) != 0; -} - -#if CONFIG(NORTHBRIDGE_AMD_AMDFAM10) -static u8 l3_cache(void) -{ - return (cpuid_edx(0x80000006) & (0x3FFF << 18)) != 0; -} - -static u8 cpu_core_number(void) -{ - return (cpuid_ecx(0x80000008) & 0xFF) + 1; -} -#endif - -/***************************************** - * Init HT link speed/width for rs780 -- k8 link - * 1: Check CPU Family, Family10? - * 2: Get CPU's HT speed and width - * 3: Decide HT mode 1 or 3 by HT Speed. >1GHz: HT3, else HT1 - *****************************************/ -static const u8 rs780_ibias[] = { - /* 1, 3 are reserved. */ - [0x0] = 0x4C, /* 200MHz HyperTransport 1 only */ - [0x2] = 0x4C, /* 400MHz HyperTransport 1 only */ - [0x4] = 0xB6, /* 600MHz HyperTransport 1 only */ - [0x5] = 0x4C, /* 800MHz HyperTransport 1 only */ - [0x6] = 0x9D, /* 1GHz HyperTransport 1 only */ - /* HT3 for Family 10 */ - [0x7] = 0xB6, /* 1.2GHz HyperTransport 3 only */ - [0x8] = 0x2B, /* 1.4GHz HyperTransport 3 only */ - [0x9] = 0x4C, /* 1.6GHz HyperTransport 3 only */ - [0xa] = 0x6C, /* 1.8GHz HyperTransport 3 only */ - [0xb] = 0x9D, /* 2.0GHz HyperTransport 3 only */ - [0xc] = 0xAD, /* 2.2GHz HyperTransport 3 only */ - [0xd] = 0xB6, /* 2.4GHz HyperTransport 3 only */ - [0xe] = 0xC6, /* 2.6GHz HyperTransport 3 only */ -}; - -void rs780_htinit(void) -{ - /* - * About HT, it has been done in enumerate_ht_chain(). - */ - pci_devfn_t cpu_f0, rs780_f0, clk_f1; - u32 reg; - u8 cpu_ht_freq, ibias; - - cpu_f0 = PCI_DEV(0, 0x18, 0); - /************************ - * get cpu's ht freq, in cpu's function 0, offset 0x88 - * bit11-8, specifics the maximum operation frequency of the link's transmitter clock. - * The link frequency field (Frq) is cleared by cold reset. SW can write a nonzero - * value to this reg, and that value takes effect on the next warm reset or - * LDTSTOP_L disconnect sequence. - * please see the table rs780_ibias about the value and its corresponding frequency. - ************************/ - reg = pci_read_config32(cpu_f0, 0x88); - cpu_ht_freq = (reg & 0xf00) >> 8; - printk(BIOS_INFO, "rs780_htinit cpu_ht_freq=%x.\n", cpu_ht_freq); - rs780_f0 = PCI_DEV(0, 0, 0); - //set_nbcfg_enable_bits(rs780_f0, 0xC8, 0x7<<24 | 0x7<<28, 1<<24 | 1<<28); - - clk_f1 = PCI_DEV(0, 0, 1); /* We need to make sure the F1 is accessible. */ - - ibias = rs780_ibias[cpu_ht_freq]; - - /* If HT freq>1GHz, we assume the CPU is fam10, else it is K8. - * Is it appropriate? - * Frequency is 1GHz, i.e. cpu_ht_freq is 6, in most cases. - * So we check 6 only, it would be faster. */ - if ((cpu_ht_freq == 0x6) || (cpu_ht_freq == 0x5) || (cpu_ht_freq == 0x4) || - (cpu_ht_freq == 0x2) || (cpu_ht_freq == 0x0)) { - printk(BIOS_INFO, "rs780_htinit: HT1 mode\n"); - - /* HT1 mode, RPR 8.4.2 */ - /* set IBIAS code */ - set_nbcfg_enable_bits(clk_f1, 0xD8, 0x3FF, ibias); - /* Optimizes chipset HT transmitter drive strength */ - set_htiu_enable_bits(rs780_f0, 0x2A, 0x3, 0x1); - } else if ((cpu_ht_freq > 0x6) && (cpu_ht_freq < 0xf)) { - printk(BIOS_INFO, "rs780_htinit: HT3 mode\n"); - - #if CONFIG(NORTHBRIDGE_AMD_AMDFAM10) - /* HT3 mode, RPR 8.4.3 */ - set_nbcfg_enable_bits(rs780_f0, 0x9c, 0x3 << 16, 0); - - /* set IBIAS code */ - set_nbcfg_enable_bits(clk_f1, 0xD8, 0x3FF, ibias); - /* Optimizes chipset HT transmitter drive strength */ - set_htiu_enable_bits(rs780_f0, 0x2A, 0x3, 0x1); - /* Enables error-retry mode */ - set_nbcfg_enable_bits(rs780_f0, 0x44, 0x1, 0x1); - /* Enables scrambling and Disables command throttling */ - set_nbcfg_enable_bits(rs780_f0, 0xac, (1 << 3) | (1 << 14), (1 << 3) | (1 << 14)); - /* Enables transmitter de-emphasis */ - set_nbcfg_enable_bits(rs780_f0, 0xa4, 1 << 31, 1 << 31); - /* Enables transmitter de-emphasis level */ - /* Sets training 0 time */ - set_nbcfg_enable_bits(rs780_f0, 0xa0, 0x3F, 0x14); - - /* Enables strict TM4 detection */ - set_htiu_enable_bits(rs780_f0, 0x15, 0x1 << 22, 0x1 << 22); - /* Enables proper DLL reset sequence */ - set_htiu_enable_bits(rs780_f0, 0x16, 0x1 << 10, 0x1 << 10); - - /* HyperTransport 3 Processor register settings to be done in northbridge */ - /* Enables error-retry mode */ - set_fam10_ext_cfg_enable_bits(cpu_f0, 0x130, 1 << 0, 1 << 0); - /* Enables scrambling */ - set_fam10_ext_cfg_enable_bits(cpu_f0, 0x170, 1 << 3, 1 << 3); - /* Enables transmitter de-emphasis - * This depends on the PCB design and the trace */ - /* TODO: */ - /* Disables command throttling */ - set_fam10_ext_cfg_enable_bits(cpu_f0, 0x168, 1 << 10, 1 << 10); - /* Sets Training 0 Time. See T0Time table for encodings */ - set_fam10_ext_cfg_enable_bits(cpu_f0, 0x16C, 0x3F, 0x20); - /* TODO: */ - #endif /* CONFIG_NORTHBRIDGE_AMD_AMDFAM10 */ - } -} - -#if !CONFIG(NORTHBRIDGE_AMD_AMDFAM10) -/******************************************************* -* Optimize k8 with UMA. -* See BKDG_NPT_0F guide for details. -* The processor node is addressed by its Node ID on the HT link and can be -* accessed with a device number in the PCI configuration space on Bus0. -* The Node ID 0 is mapped to Device 24 (0x18), the Node ID 1 is mapped -* to Device 25, and so on. -* The processor implements configuration registers in PCI configuration -* space using the following four headers -* Function0: HT technology configuration -* Function1: Address map configuration -* Function2: DRAM and HT technology Trace mode configuration -* Function3: Miscellaneous configuration -*******************************************************/ -static void k8_optimization(void) -{ - pci_devfn_t k8_f0, k8_f2, k8_f3; - msr_t msr; - - printk(BIOS_INFO, "k8_optimization()\n"); - k8_f0 = PCI_DEV(0, 0x18, 0); - k8_f2 = PCI_DEV(0, 0x18, 2); - k8_f3 = PCI_DEV(0, 0x18, 3); - - /* 8.6.6 K8 Buffer Allocation Settings */ - pci_write_config32(k8_f0, 0x90, 0x01700169); /* CIM NPT_Optimization */ - set_nbcfg_enable_bits(k8_f0, 0x68, 1 << 28, 0 << 28); - set_nbcfg_enable_bits(k8_f0, 0x68, 3 << 26, 3 << 26); - set_nbcfg_enable_bits(k8_f0, 0x68, 1 << 11, 1 << 11); - /* set_nbcfg_enable_bits(k8_f0, 0x84, 1 << 11 | 1 << 13 | 1 << 15, 1 << 11 | 1 << 13 | 1 << 15); */ /* TODO */ - - pci_write_config32(k8_f3, 0x70, 0x51220111); - pci_write_config32(k8_f3, 0x74, 0x50404021); - pci_write_config32(k8_f3, 0x78, 0x08002A00); - if (pci_read_config32(k8_f3, 0xE8) & 0x3<<12) - pci_write_config32(k8_f3, 0x7C, 0x0000211A); /* dual core */ - else - pci_write_config32(k8_f3, 0x7C, 0x0000212B); /* single core */ - set_nbcfg_enable_bits_8(k8_f3, 0xDC, 0xFF, 0x25); - - set_nbcfg_enable_bits(k8_f2, 0xA0, 1 << 5, 1 << 5); - set_nbcfg_enable_bits(k8_f2, 0x94, 0xF << 24, 7 << 24); - set_nbcfg_enable_bits(k8_f2, 0x90, 1 << 10, 0 << 10); - set_nbcfg_enable_bits(k8_f2, 0xA0, 3 << 2, 3 << 2); - set_nbcfg_enable_bits(k8_f2, 0xA0, 1 << 5, 1 << 5); - - msr = rdmsr(NB_CFG_MSR); - msr.lo &= ~(1 << 9); - msr.hi &= ~(1 << 4); - wrmsr(NB_CFG_MSR, msr); -} -#else -#define k8_optimization() do {} while (0) -#endif /* !CONFIG_NORTHBRIDGE_AMD_AMDFAM10 */ - -#if CONFIG(NORTHBRIDGE_AMD_AMDFAM10) -static void fam10_optimization(void) -{ - pci_devfn_t cpu_f0, cpu_f2, cpu_f3; - u32 val; - - printk(BIOS_INFO, "fam10_optimization()\n"); - - cpu_f0 = PCI_DEV(0, 0x18, 0); - cpu_f2 = PCI_DEV(0, 0x18, 2); - cpu_f3 = PCI_DEV(0, 0x18, 3); - - /* 8.6.4.1 */ - /* Table 8-13 */ - pci_write_config32(cpu_f0, 0x90, 0x808502D0); - /* Table 8-14 */ - pci_write_config32(cpu_f0, 0x94, 0x00000000); - - /* Table 8-15 */ - val = pci_read_config32(cpu_f0, 0x68); - val |= 1 << 24; - pci_write_config32(cpu_f0, 0x68, val); - - /* Table 8-16 */ - val = pci_read_config32(cpu_f0, 0x84); - val &= ~(1 << 12); - pci_write_config32(cpu_f0, 0x84, val); - - /* Table 8-17 */ - val = pci_read_config32(cpu_f2, 0x90); - val &= ~(1 << 10); - pci_write_config32(cpu_f2, 0x90, val); - - /* Table 8-18 */ - pci_write_config32(cpu_f3, 0x6C, 0x60018051); - /* Table 8-19 */ - pci_write_config32(cpu_f3, 0x70, 0x60321151); - /* Table 8-20 */ - pci_write_config32(cpu_f3, 0x74, 0x00980101); - /* Table 8-21 */ - pci_write_config32(cpu_f3, 0x78, 0x00200C14); - /* Table 8-22 */ - pci_write_config32(cpu_f3, 0x7C, 0x00070811); /* TODO: Check if L3 Cache is enabled. */ - - /* Table 8-23 */ - Set_NB32(cpu_f3, 0x140, 0x00D33656); - /* Table 8-24 */ - Set_NB32(cpu_f3, 0x144, 0x00000036); - /* Table 8-25 */ - Set_NB32(cpu_f3, 0x148, 0x8000832A); - /* Table 8-26 */ - Set_NB32(cpu_f3, 0x158, 0); - /* L3 Disabled: L3 Enabled: */ - /* cores: 2 3 4 2 3 4 */ - /* bit8:4 28 26 24 24 20 16 */ - if (!l3_cache()) { - Set_NB32(cpu_f3, 0x1A0, 4 << 12 | (24 + 2*(4-cpu_core_number())) << 4 | 2); - } else { - Set_NB32(cpu_f3, 0x1A0, 4 << 12 | (16 + 4*(4-cpu_core_number())) << 4 | 4); - } -} -#else -#define fam10_optimization() do {} while (0) -#endif /* CONFIG_NORTHBRIDGE_AMD_AMDFAM10 */ - -/***************************************** -* rs780_por_pcicfg_init() -*****************************************/ -static void rs780_por_pcicfg_init(pci_devfn_t nb_dev) -{ - /* enable PCI Memory Access */ - set_nbcfg_enable_bits_8(nb_dev, 0x04, (u8)(~0xFD), 0x02); - /* Set RCRB Enable */ - set_nbcfg_enable_bits_8(nb_dev, 0x84, (u8)(~0xFF), 0x1); - /* allow decode of 640k-1MB */ - set_nbcfg_enable_bits_8(nb_dev, 0x84, (u8)(~0xEF), 0x10); - /* Enable PM2_CNTL(BAR2) IO mapped cfg write access to be broadcast to both NB and SB */ - set_nbcfg_enable_bits_8(nb_dev, 0x84, (u8)(~0xFF), 0x4); - /* Power Management Register Enable */ - set_nbcfg_enable_bits_8(nb_dev, 0x84, (u8)(~0xFF), 0x80); - - /* Reg4Ch[1]=1 (APIC_ENABLE) force CPU request with address 0xFECx_xxxx to south-bridge - * Reg4Ch[6]=1 (BMMsgEn) enable BM_Set message generation - * BMMsgEn */ - set_nbcfg_enable_bits_8(nb_dev, 0x4C, (u8)(~0x00), 0x42 | 1); - - /* Reg4Ch[16]=1 (WakeC2En) enable Wake_from_C2 message generation. - * Reg4Ch[18]=1 (P4IntEnable) Enable north-bridge to accept MSI with address 0xFEEx_xxxx from south-bridge */ - set_nbcfg_enable_bits_8(nb_dev, 0x4E, (u8)(~0xFF), 0x05); - /* Reg94h[4:0] = 0x0 P drive strength offset 0 - * Reg94h[6:5] = 0x2 P drive strength additive adjust */ - set_nbcfg_enable_bits_8(nb_dev, 0x94, (u8)(~0x80), 0x40); - - /* Reg94h[20:16] = 0x0 N drive strength offset 0 - * Reg94h[22:21] = 0x2 N drive strength additive adjust */ - set_nbcfg_enable_bits_8(nb_dev, 0x96, (u8)(~0x80), 0x40); - - /* Reg80h[4:0] = 0x0 Termination offset - * Reg80h[6:5] = 0x2 Termination additive adjust */ - set_nbcfg_enable_bits_8(nb_dev, 0x80, (u8)(~0x80), 0x40); - - /* Reg80h[14] = 0x1 Enable receiver termination control */ - set_nbcfg_enable_bits_8(nb_dev, 0x81, (u8)(~0xFF), 0x40); - - /* Reg94h[15] = 0x1 Enables HT transmitter advanced features to be turned on - * Reg94h[14] = 0x1 Enable drive strength control */ - set_nbcfg_enable_bits_8(nb_dev, 0x95, (u8)(~0x3F), 0xC4); - - /* Reg94h[31:29] = 0x7 Enables HT transmitter de-emphasis */ - set_nbcfg_enable_bits_8(nb_dev, 0x97, (u8)(~0x1F), 0xE0); - - /* Reg8Ch[9] enables Gfx Debug BAR programming - * Reg8Ch[10] enables Gfx Debug BAR operation - * Enable programming of the debug bar now, but enable - * operation only after it has been programmed */ - set_nbcfg_enable_bits_8(nb_dev, 0x8D, (u8)(~0xFF), 0x02); -} - -static void rs780_por_mc_index_init(pci_devfn_t nb_dev) -{ - set_nbmc_enable_bits(nb_dev, 0x7A, ~0xFFFFFF80, 0x0000005F); - set_nbmc_enable_bits(nb_dev, 0xD8, ~0x00000000, 0x00600060); - set_nbmc_enable_bits(nb_dev, 0xD9, ~0x00000000, 0x00600060); - set_nbmc_enable_bits(nb_dev, 0xE0, ~0x00000000, 0x00000000); - set_nbmc_enable_bits(nb_dev, 0xE1, ~0x00000000, 0x00000000); - set_nbmc_enable_bits(nb_dev, 0xE8, ~0x00000000, 0x003E003E); - set_nbmc_enable_bits(nb_dev, 0xE9, ~0x00000000, 0x003E003E); -} - -static void rs780_por_misc_index_init(pci_devfn_t nb_dev) -{ - /* NB_MISC_IND_WR_EN + IOC_PCIE_CNTL - * Block non-snoop DMA request if PMArbDis is set. - * Set BMSetDis */ - set_nbmisc_enable_bits(nb_dev, 0x0B, ~0xFFFF0000, 0x00000180); - set_nbmisc_enable_bits(nb_dev, 0x01, ~0xFFFFFFFF, 0x00000040); - - /* NBCFG (NBMISCIND 0x0): NB_CNTL - - * HIDE_NB_AGP_CAP ([0], default=1)HIDE - * HIDE_P2P_AGP_CAP ([1], default=1)HIDE - * HIDE_NB_GART_BAR ([2], default=1)HIDE - * AGPMODE30 ([4], default=0)DISABLE - * AGP30ENCHANCED ([5], default=0)DISABLE - * HIDE_AGP_CAP ([8], default=1)ENABLE */ - set_nbmisc_enable_bits(nb_dev, 0x00, ~0xFFFF0000, 0x00000506); /* set bit 10 for MSI */ - - /* NBMISCIND:0x6A[16]= 1 SB link can get a full swing - * set_nbmisc_enable_bits(nb_dev, 0x6A, 0ffffffffh, 000010000); - * NBMISCIND:0x6A[17]=1 Set CMGOOD_OVERRIDE. */ - set_nbmisc_enable_bits(nb_dev, 0x6A, ~0xffffffff, 0x00020000); - - /* NBMISIND:0x40 Bit[8]=1 and Bit[10]=1 following bits are required to set in order to allow LVDS or PWM features to work. */ - set_nbmisc_enable_bits(nb_dev, 0x40, ~0xffffffff, 0x00000500); - - /* NBMISIND:0xC Bit[13]=1 Enable GSM mode for C1e or C3 with pop-up. */ - set_nbmisc_enable_bits(nb_dev, 0x0C, ~0xffffffff, 0x00002000); - - /* Set NBMISIND:0x1F[3] to map NB F2 interrupt pin to INTB# */ - set_nbmisc_enable_bits(nb_dev, 0x1F, ~0xffffffff, 0x00000008); - - /* - * Enable access to DEV8 - * Enable setPower message for all ports - */ - set_nbmisc_enable_bits(nb_dev, 0x00, 1 << 6, 1 << 6); - set_nbmisc_enable_bits(nb_dev, 0x0b, 1 << 20, 1 << 20); - set_nbmisc_enable_bits(nb_dev, 0x51, 1 << 20, 1 << 20); - set_nbmisc_enable_bits(nb_dev, 0x53, 1 << 20, 1 << 20); - set_nbmisc_enable_bits(nb_dev, 0x55, 1 << 20, 1 << 20); - set_nbmisc_enable_bits(nb_dev, 0x57, 1 << 20, 1 << 20); - set_nbmisc_enable_bits(nb_dev, 0x59, 1 << 20, 1 << 20); - set_nbmisc_enable_bits(nb_dev, 0x5B, 1 << 20, 1 << 20); - set_nbmisc_enable_bits(nb_dev, 0x5D, 1 << 20, 1 << 20); - set_nbmisc_enable_bits(nb_dev, 0x5F, 1 << 20, 1 << 20); - - set_nbmisc_enable_bits(nb_dev, 0x00, 1 << 7, 1 << 7); - set_nbmisc_enable_bits(nb_dev, 0x07, 0x000000f0, 0x30); - - set_nbmisc_enable_bits(nb_dev, 0x01, 0xFFFFFFFF, 0x48); - /* Disable bus-master trigger event from SB and Enable set_slot_power message to SB */ - set_nbmisc_enable_bits(nb_dev, 0x0B, 0xffffffff, 0x500180); -} - -/***************************************** -* Some setting is from rpr. Some is from CIMx. -*****************************************/ -static void rs780_por_htiu_index_init(pci_devfn_t nb_dev) -{ -#if 0 /* get from rpr. */ - set_htiu_enable_bits(nb_dev, 0x1C, 0x1<<17, 0x1<<17); - set_htiu_enable_bits(nb_dev, 0x06, 0x1<<0, 0x0<<0); - set_htiu_enable_bits(nb_dev, 0x06, 0x1<<1, 0x1<<1); - set_htiu_enable_bits(nb_dev, 0x06, 0x1<<9, 0x1<<9); - set_htiu_enable_bits(nb_dev, 0x06, 0x1<<13, 0x1<<13); - set_htiu_enable_bits(nb_dev, 0x06, 0x1<<17, 0x1<<17); - set_htiu_enable_bits(nb_dev, 0x06, 0x3<<15, 0x3<<15); - set_htiu_enable_bits(nb_dev, 0x06, 0x1<<25, 0x1<<25); - set_htiu_enable_bits(nb_dev, 0x06, 0x1<<30, 0x1<<30); - - set_htiu_enable_bits(nb_dev, 0x07, 0x1<<0, 0x1<<0); - set_htiu_enable_bits(nb_dev, 0x07, 0x1<<1, 0x0<<1); - set_htiu_enable_bits(nb_dev, 0x07, 0x1<<2, 0x0<<2); - set_htiu_enable_bits(nb_dev, 0x07, 0x1<<15, 0x1<<15); - - set_htiu_enable_bits(nb_dev, 0x0C, 0x3<<0, 0x1<<0); - set_htiu_enable_bits(nb_dev, 0x0C, 0x3<<2, 0x2<<2); - set_htiu_enable_bits(nb_dev, 0x0C, 0x3<<4, 0x0<<4); - - /* A12 only */ - set_htiu_enable_bits(nb_dev, 0x2D, 0x1<<4, 0x1<<4); - set_htiu_enable_bits(nb_dev, 0x2D, 0x1<<6, 0x1<<6); - set_htiu_enable_bits(nb_dev, 0x05, 0x1<<2, 0x1<<2); - - set_htiu_enable_bits(nb_dev, 0x1E, 0xFFFFFFFF, 0xFFFFFFFF); -#else /* get from CIM. It is more reliable than above. */ - set_htiu_enable_bits(nb_dev, 0x05, (1<<10|1<<9), 1<<10 | 1<<9); - set_htiu_enable_bits(nb_dev, 0x06, ~0xFFFFFFFE, 0x04203A202); - - set_htiu_enable_bits(nb_dev, 0x07, ~0xFFFFFFF9, 0x8001/* | 7 << 8 */); /* fam 10 */ - - set_htiu_enable_bits(nb_dev, 0x15, ~0xFFFFFFFF, 1<<31| 1<<30 | 1<<27); - set_htiu_enable_bits(nb_dev, 0x1C, ~0xFFFFFFFF, 0xFFFE0000); - - set_htiu_enable_bits(nb_dev, 0x4B, (1<<11), 1<<11); - - set_htiu_enable_bits(nb_dev, 0x0C, ~0xFFFFFFC0, 1<<0|1<<3); - - set_htiu_enable_bits(nb_dev, 0x17, (1<<27|1<<1), 0x1<<1); - set_htiu_enable_bits(nb_dev, 0x17, 0x1 << 30, 0x1<<30); - - set_htiu_enable_bits(nb_dev, 0x19, (0xFFFFF+(1<<31)), 0x186A0+(1<<31)); - - set_htiu_enable_bits(nb_dev, 0x16, (0x3F<<10), 0x7<<10); - - set_htiu_enable_bits(nb_dev, 0x23, 0xFFFFFFF, 1<<28); - - set_htiu_enable_bits(nb_dev, 0x1E, 0xFFFFFFFF, 0xFFFFFFFF); -#endif -} - -/***************************************** -* Configure RS780 registers to power-on default RPR. -* POR: Power On Reset -* RPR: Register Programming Requirements -*****************************************/ -static void rs780_por_init(pci_devfn_t nb_dev) -{ - printk(BIOS_INFO, "rs780_por_init\n"); - /* ATINB_PCICFG_POR_TABLE, initialize the values for rs780 PCI Config registers */ - rs780_por_pcicfg_init(nb_dev); - - /* ATINB_MCIND_POR_TABLE */ - rs780_por_mc_index_init(nb_dev); - - /* ATINB_MISCIND_POR_TABLE */ - rs780_por_misc_index_init(nb_dev); - - /* ATINB_HTIUNBIND_POR_TABLE */ - rs780_por_htiu_index_init(nb_dev); - - /* ATINB_CLKCFG_PORT_TABLE */ - /* rs780 A11 SB Link full swing? */ - - /* SET NB_MISC_REG01 BIT8 to Enable HDMI, reference CIMX_5_9_3 NBPOR_InitPOR(), - * then the accesses to internal graphics IO space 0x60/0x64, are forwarded to - * nbconfig:0x60/0x64 - */ - - set_nbmisc_enable_bits(nb_dev, 0x01, ~(1 << 8), (1 << 8)); -} - -/* enable CFG access to Dev8, which is the SB P2P Bridge */ -void enable_rs780_dev8(void) -{ - set_nbmisc_enable_bits(PCI_DEV(0, 0, 0), 0x00, 1 << 6, 1 << 6); -} - -void rs780_early_setup(void) -{ - pci_devfn_t nb_dev = PCI_DEV(0, 0, 0); - printk(BIOS_INFO, "rs780_early_setup()\n"); - - /* The printk(BIOS_INFO, s) below cause the system unstable. */ - switch (get_nb_rev(nb_dev)) { - case REV_RS780_A11: - /* printk(BIOS_INFO, "NB Revision is A11.\n"); */ - break; - case REV_RS780_A12: - /* printk(BIOS_INFO, "NB Revision is A12.\n"); */ - break; - case REV_RS780_A13: - /* printk(BIOS_INFO, "NB Revision is A13.\n"); */ - break; - } - - if (is_famly10()) - fam10_optimization(); - else - k8_optimization(); - - rs780_por_init(nb_dev); -} diff --git a/src/southbridge/amd/rs780/gfx.c b/src/southbridge/amd/rs780/gfx.c deleted file mode 100644 index ca7414a9eb..0000000000 --- a/src/southbridge/amd/rs780/gfx.c +++ /dev/null @@ -1,1572 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2010 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -/* - * for rs780 internal graphics device - * device id of internal graphics: - * RS780: 0x9610 - * RS780C: 0x9611 - * RS780M: 0x9612 - * RS780MC:0x9613 - * RS780E: 0x9615 - * RS785G: 0x9710 - just works, not much tested - * RS785C: 0x9711 - * RS785M: 0x9712 - * RS785MC:0x9713 - * RS785D: 0x9714 - */ -#include -#include -#include -#include -#include -#include -#include -#include -#include "rs780.h" - -/* Trust the original resource allocation. Don't do it again. */ -#undef DONT_TRUST_RESOURCE_ALLOCATION -//#define DONT_TRUST_RESOURCE_ALLOCATION - -#define CLK_CNTL_INDEX 0x8 -#define CLK_CNTL_DATA 0xC - -/* The Integrated Info Table. */ -ATOM_INTEGRATED_SYSTEM_INFO_V2 vgainfo; - -#ifdef UNUSED_CODE -static u32 clkind_read(struct device *dev, u32 index) -{ - u32 gfx_bar2 = pci_read_config32(dev, 0x18) & ~0xF; - - *(u32*)(gfx_bar2+CLK_CNTL_INDEX) = index & 0x7F; - return *(u32*)(gfx_bar2+CLK_CNTL_DATA); -} -#endif - -static void clkind_write(struct device *dev, u32 index, u32 data) -{ - u32 gfx_bar2 = pci_read_config32(dev, 0x18) & ~0xF; - /* printk(BIOS_DEBUG, "gfx bar 2 %02x\n", gfx_bar2); */ - - *(u32*)(gfx_bar2+CLK_CNTL_INDEX) = index | 1<<7; - *(u32*)(gfx_bar2+CLK_CNTL_DATA) = data; -} - -/* -* pci_dev_read_resources thinks it is a IO type. -* We have to force it to mem type. -*/ -static void rs780_gfx_read_resources(struct device *dev) -{ - printk(BIOS_DEBUG, "rs780_gfx_read_resources.\n"); - - /* The initial value of 0x24 is 0xFFFFFFFF, which is confusing. - Even if we write 0xFFFFFFFF into it, it will be 0xFFF00000, - which tells us it is a memory address base. - */ - pci_write_config32(dev, 0x24, 0x00000000); - - /* Get the normal pci resources of this device */ - pci_dev_read_resources(dev); - compact_resources(dev); -} - -typedef struct _MMIORANGE -{ - u32 Base; - u32 Limit; - u8 Attribute; -} MMIORANGE; - -MMIORANGE MMIO[8], CreativeMMIO[8]; - -#define CIM_STATUS u32 -#define CIM_SUCCESS 0x00000000 -#define CIM_ERROR 0x80000000 -#define CIM_UNSUPPORTED 0x80000001 -#define CIM_DISABLEPORT 0x80000002 - -#define MMIO_ATTRIB_NP_ONLY 1 -#define MMIO_ATTRIB_BOTTOM_TO_TOP (1 << 1) -#define MMIO_ATTRIB_SKIP_ZERO (1 << 2) - -#ifdef DONT_TRUST_RESOURCE_ALLOCATION -static MMIORANGE* AllocMMIO(MMIORANGE* pMMIO) -{ - int i; - for (i = 0; i < 8; i++) { - if (pMMIO[i].Limit == 0) - return &pMMIO[i]; - } - return 0; -} - -static void FreeMMIO(MMIORANGE* pMMIO) -{ - pMMIO->Base = 0; - pMMIO->Limit = 0; -} - -static u32 SetMMIO(u32 Base, u32 Limit, u8 Attribute, MMIORANGE *pMMIO) -{ - int i; - MMIORANGE * TempRange; - for (i = 0; i < 8; i++) { - if (pMMIO[i].Attribute != Attribute && Base >= pMMIO[i].Base && Limit <= pMMIO[i].Limit) { - TempRange = AllocMMIO(pMMIO); - if (TempRange == 0) return 0x80000000; - TempRange->Base = Limit; - TempRange->Limit = pMMIO[i].Limit; - TempRange->Attribute = pMMIO[i].Attribute; - pMMIO[i].Limit = Base; - } - } - TempRange = AllocMMIO(pMMIO); - if (TempRange == 0) return 0x80000000; - TempRange->Base = Base; - TempRange->Limit = Limit; - TempRange->Attribute = Attribute; - return 0; -} - -static u8 FinalizeMMIO(MMIORANGE *pMMIO) -{ - int i, j, n = 0; - for (i = 0; i < 8; i++) { - if (pMMIO[i].Base == pMMIO[i].Limit) { - FreeMMIO(&pMMIO[i]); - continue; - } - for (j = 0; j < i; j++) { - if (i!=j && pMMIO[i].Attribute == pMMIO[j].Attribute) { - if (pMMIO[i].Base == pMMIO[j].Limit) { - pMMIO[j].Limit = pMMIO[i].Limit; - FreeMMIO(&pMMIO[i]); - } - if (pMMIO[i].Limit == pMMIO[j].Base) { - pMMIO[j].Base = pMMIO[i].Base; - FreeMMIO(&pMMIO[i]); - } - } - } - } - for (i = 0; i < 8; i++) { - if (pMMIO[i].Limit != 0) n++; - } - return n; -} - -static CIM_STATUS GetCreativeMMIO(MMIORANGE *pMMIO) -{ - CIM_STATUS Status = CIM_UNSUPPORTED; - u8 Bus, Dev, Reg, BusStart, BusEnd; - u32 Value; - struct device *dev0x14 = pcidev_on_root(0x14, 4); - struct device *tempdev; - Value = pci_read_config32(dev0x14, 0x18); - BusStart = (Value >> 8) & 0xFF; - BusEnd = (Value >> 16) & 0xFF; - for (Bus = BusStart; Bus <= BusEnd; Bus++) { - for (Dev = 0; Dev <= 0x1f; Dev++) { - tempdev = dev_find_slot(Bus, Dev << 3); - Value = pci_read_config32(tempdev, 0); - printk(BIOS_DEBUG, "Dev ID %x\n", Value); - if ((Value & 0xffff) == 0x1102) {//Creative - //Found Creative SB - u32 MMIOStart = 0xffffffff; - u32 MMIOLimit = 0; - for (Reg = 0x10; Reg < 0x20; Reg+=4) { - u32 BaseA, LimitA; - BaseA = pci_read_config32(tempdev, Reg); - Value = BaseA; - if (!(Value & 0x01)) { - Value = Value & 0xffffff00; - if (Value != 0) { - if (MMIOStart > Value) - MMIOStart = Value; - LimitA = 0xffffffff; - //WritePCI(PciAddress,AccWidthUint32,&LimitA); - pci_write_config32(tempdev, Reg, LimitA); - //ReadPCI(PciAddress,AccWidthUint32,&LimitA); - LimitA = pci_read_config32(tempdev, Reg); - LimitA = Value + (~LimitA + 1); - //WritePCI(PciAddress,AccWidthUint32,&BaseA); - pci_write_config32(tempdev, Reg, BaseA); - if (LimitA > MMIOLimit) - MMIOLimit = LimitA; - } - } - } - printk(BIOS_DEBUG, " MMIOStart %x MMIOLimit %x\n", MMIOStart, MMIOLimit); - if (MMIOStart < MMIOLimit) - { - Status = SetMMIO(MMIOStart>>8, MMIOLimit>>8, 0x80, pMMIO); - if (Status == CIM_ERROR) return Status; - } - } - } - } - if (Status == CIM_SUCCESS) { - //Lets optimize MMIO - if (FinalizeMMIO(pMMIO) > 4) { - Status = CIM_ERROR; - } - } - - return Status; -} - -static void ProgramMMIO(MMIORANGE *pMMIO, u8 LinkID, u8 Attribute) -{ - int i, j, n = 7; - struct device *k8_f1; - - k8_f1 = pcidev_on_root(0x18, 1); - - for (i = 0; i < 8; i++) { - int k = 0, MmioReg; - u32 Base = 0; - u32 Limit = 0; - for (j = 0; j < 8; j++) { - if (Base < pMMIO[j].Base) { - Base = pMMIO[j].Base; - k = j; - } - } - if (pMMIO[k].Limit != 0) { - if (Attribute & MMIO_ATTRIB_NP_ONLY && pMMIO[k].Attribute == 0) { - Base = 0; - } - else - { - Base = pMMIO[k].Base | 0x3; - Limit= ((pMMIO[k].Limit - 1) & 0xffffff00) | pMMIO[k].Attribute | (LinkID << 4); - } - FreeMMIO(&pMMIO[k]); - } - if (Attribute & MMIO_ATTRIB_SKIP_ZERO && Base == 0 && Limit == 0) continue; - MmioReg = (Attribute & MMIO_ATTRIB_BOTTOM_TO_TOP)?n:(7-n); - n--; - //RWPCI(PCI_ADDRESS(0,CPU_DEV,CPU_F1,0x80+MmioReg*8),AccWidthUint32 |S3_SAVE,0x0,0x0); - pci_write_config32(k8_f1, 0x80+MmioReg*8, 0); - - //WritePCI(PCI_ADDRESS(0,CPU_DEV,CPU_F1,0x84+MmioReg*8),AccWidthUint32 |S3_SAVE,&Limit); - pci_write_config32(k8_f1, 0x84+MmioReg*8, Limit); - - //WritePCI(PCI_ADDRESS(0,CPU_DEV,CPU_F1,0x80+MmioReg*8),AccWidthUint32 |S3_SAVE,&Base); - pci_write_config32(k8_f1, 0x80+MmioReg*8, Base); - } -} -#endif - -#define GFX_CONFIG_DDI1 0x04 -#define GFX_CONFIG_DDI2 0x08 -#define GFX_CONFIG_DDI (GFX_CONFIG_DDI1 | GFX_CONFIG_DDI2) - -/** - * Force poweron pads for lanes used for DDI - * reference CIMx PCIEL_PowerOnDDILanes() - * - * Inactive B_PRX_PDNB_FDIS B_PTX_PDNB_FDIS - * Lanes - * Lanes 0-1 Bit 8 Bit 0 - * Lanes 2-3 Bit 9 Bit 1 - * Lanes 4-5 Bit 10 Bit 2 - * Lanes 6-7 Bit 11 Bit 3 - * Lanes 8-9 Bit 12 Bit 4 - * Lanes 10-11 Bit 13 Bit 5 - * Lanes 12-13 Bit 14 Bit 6 - * Lanes 14-15 Bit 15 Bit 7 - */ -static void poweron_ddi_lanes(struct device *nb_dev) -{ - u8 i; - u32 gfx_cfg = 0; - u32 ddi_pads = 0; - - ddi_pads = ~(nbpcie_ind_read_index(nb_dev, 0x65)); /* save original setting */ - gfx_cfg = nbmisc_read_index(nb_dev, 0x74); - for (i = 0; i < 3; i++) { - if (gfx_cfg & GFX_CONFIG_DDI) { - ddi_pads |= (3 << (i * 2)); - } - gfx_cfg >>= 8; - } - ddi_pads |= ddi_pads << 8; /* both TX and RX */ - nbpcie_ind_write_index(nb_dev, 0x65, ~ddi_pads); -} - -static void internal_gfx_pci_dev_init(struct device *dev) -{ - unsigned char *bpointer; - volatile u32 *GpuF0MMReg; - volatile u32 *pointer; - int i; - u16 command; - u32 value; - u16 deviceid, vendorid; - struct device *nb_dev = pcidev_on_root(0x0, 0); - struct device *k8_f2 = pcidev_on_root(0x18, 2); - struct device *k8_f0 = pcidev_on_root(0x18, 0); - static const u8 ht_freq_lookup [] = {2, 0, 4, 0, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 26, 0, 0, 28, 30, 32}; - static const u8 ht_width_lookup [] = {8, 16, 0, 0, 2, 4, 0, 0}; - static const u16 memclk_lookup_fam0F [] = {100, 0, 133, 0, 0, 166, 0, 200}; - static const u16 memclk_lookup_fam10 [] = {200, 266, 333, 400, 533, 667, 800, 800}; - - /* We definitely will use this in future. Just leave it here. */ - /*struct southbridge_amd_rs780_config *cfg = - (struct southbridge_amd_rs780_config *)dev->chip_info;*/ - - deviceid = pci_read_config16(dev, PCI_DEVICE_ID); - vendorid = pci_read_config16(dev, PCI_VENDOR_ID); - printk(BIOS_DEBUG, "internal_gfx_pci_dev_init device=%x, vendor=%x.\n", - deviceid, vendorid); - - command = pci_read_config16(dev, 0x04); - command |= 0x7; - pci_write_config16(dev, 0x04, command); - - /* Clear vgainfo. */ - bpointer = (unsigned char *) &vgainfo; - for (i = 0; i < sizeof(ATOM_INTEGRATED_SYSTEM_INFO_V2); i++) { - *bpointer = 0; - bpointer++; - } - - GpuF0MMReg = (u32 *)pci_read_config32(dev, 0x18); - - /* GFX_InitFBAccess. */ - value = nbmc_read_index(nb_dev, 0x10); - *(GpuF0MMReg + 0x2000/4) = 0x11; - *(GpuF0MMReg + 0x2180/4) = ((value&0xff00)>>8)|((value&0xff000000)>>8); - *(GpuF0MMReg + 0x2c04/4) = ((value&0xff00)<<8); - *(GpuF0MMReg + 0x5428/4) = ((value&0xffff0000)+0x10000)-((value&0xffff)<<16); - *(GpuF0MMReg + 0xF774/4) = 0xffffffff; - *(GpuF0MMReg + 0xF770/4) = 0x00000001; - *(GpuF0MMReg + 0x2000/4) = 0x00000011; - *(GpuF0MMReg + 0x200c/4) = 0x00000020; - *(GpuF0MMReg + 0x2010/4) = 0x10204810; - *(GpuF0MMReg + 0x2010/4) = 0x00204810; - *(GpuF0MMReg + 0x2014/4) = 0x10408810; - *(GpuF0MMReg + 0x2014/4) = 0x00408810; - *(GpuF0MMReg + 0x2414/4) = 0x00000080; - *(GpuF0MMReg + 0x2418/4) = 0x84422415; - *(GpuF0MMReg + 0x2418/4) = 0x04422415; - *(GpuF0MMReg + 0x5490/4) = 0x00000001; - *(GpuF0MMReg + 0x7de4/4) |= (1<<3) | (1<<4); - /* Force allow LDT_STOP Cool'n'Quiet workaround. */ - *(GpuF0MMReg + 0x655c/4) |= 1<<4; - - // disable write combining, needed for stability - // reference bios does this only for RS780 rev A11 - // need to figure out why we need it for all revs - *(GpuF0MMReg + 0x2000/4) = 0x00000010; - *(GpuF0MMReg + 0x2408/4) = 1 << 9; - *(GpuF0MMReg + 0x2000/4) = 0x00000011; - - /* GFX_InitFBAccess finished. */ - -#if CONFIG(GFXUMA) /* for UMA mode. */ - /* GFX_StartMC. */ - set_nbmc_enable_bits(nb_dev, 0x02, 0x00000000, 0x80000000); - set_nbmc_enable_bits(nb_dev, 0x01, 0x00000000, 0x00000001); - set_nbmc_enable_bits(nb_dev, 0x01, 0x00000000, 0x00000004); - set_nbmc_enable_bits(nb_dev, 0x01, 0x00040000, 0x00000000); - set_nbmc_enable_bits(nb_dev, 0xB1, 0xFFFF0000, 0x00000040); - set_nbmc_enable_bits(nb_dev, 0xC3, 0x00000000, 0x00000001); - set_nbmc_enable_bits(nb_dev, 0x07, 0xFFFFFFFF, 0x00000018); - set_nbmc_enable_bits(nb_dev, 0x06, 0xFFFFFFFF, 0x00000102); - set_nbmc_enable_bits(nb_dev, 0x09, 0xFFFFFFFF, 0x40000008); - set_nbmc_enable_bits(nb_dev, 0x06, 0x00000000, 0x80000000); - /* GFX_StartMC finished. */ -#else - /* for SP mode. */ - set_nbmc_enable_bits(nb_dev, 0xaa, 0xf0, 0x30); - set_nbmc_enable_bits(nb_dev, 0xce, 0xf0, 0x30); - set_nbmc_enable_bits(nb_dev, 0xca, 0xff000000, 0x47000000); - set_nbmc_enable_bits(nb_dev, 0xcb, 0x3f000000, 0x01000000); - set_nbmc_enable_bits(nb_dev, 0x01, 0, 1<<0); - set_nbmc_enable_bits(nb_dev, 0x04, 0, 1<<31); - set_nbmc_enable_bits(nb_dev, 0xb4, 0x3f, 0x3f); - set_nbmc_enable_bits(nb_dev, 0xb4, 0, 1<<6); - set_nbmc_enable_bits(nb_dev, 0xc3, 1<<11, 0); - set_nbmc_enable_bits(nb_dev, 0xa0, 1<<29, 0); - nbmc_write_index(nb_dev, 0xa4, 0x3484576f); - nbmc_write_index(nb_dev, 0xa5, 0x222222df); - nbmc_write_index(nb_dev, 0xa6, 0x00000000); - nbmc_write_index(nb_dev, 0xa7, 0x00000000); - set_nbmc_enable_bits(nb_dev, 0xc3, 1<<8, 0); - udelay(10); - set_nbmc_enable_bits(nb_dev, 0xc3, 1<<9, 0); - udelay(10); - set_nbmc_enable_bits(nb_dev, 0x01, 0, 1<<2); - udelay(200); - set_nbmc_enable_bits(nb_dev, 0x01, 0, 1<<3); - set_nbmc_enable_bits(nb_dev, 0xa0, 0, 1<<31); - udelay(500); - set_nbmc_enable_bits(nb_dev, 0x02, 0, 1<<31); - set_nbmc_enable_bits(nb_dev, 0xa0, 0, 1<<30); - set_nbmc_enable_bits(nb_dev, 0xa0, 1<<31, 0); - set_nbmc_enable_bits(nb_dev, 0xa0, 0, 1<<29); - nbmc_write_index(nb_dev, 0xa4, 0x23484576); - nbmc_write_index(nb_dev, 0xa5, 0x00000000); - nbmc_write_index(nb_dev, 0xa6, 0x00000000); - nbmc_write_index(nb_dev, 0xa7, 0x00000000); - /* GFX_StartMC finished. */ - - /* GFX_SPPowerManagment, don't care for new. */ - /* Post MC Init table programming. */ - set_nbmc_enable_bits(nb_dev, 0xac, ~(0xfffffff0), 0x0b); - - /* Do we need Write and Read Calibration? */ - /* GFX_Init finished. */ -#endif - - /* GFX_InitIntegratedInfo. */ - /* fill the Integrated Info Table. */ - vgainfo.sHeader.usStructureSize = sizeof(ATOM_INTEGRATED_SYSTEM_INFO_V2); - vgainfo.sHeader.ucTableFormatRevision = 1; - vgainfo.sHeader.ucTableContentRevision = 2; - -#if !CONFIG(GFXUMA) /* SP mode. */ - // Side port support is incomplete, do not use it - // These parameters must match the motherboard - vgainfo.ulBootUpSidePortClock = 667*100; - vgainfo.ucMemoryType = 3; // 3 = ddr3 sp mem, 2 = ddr2 sp mem - vgainfo.ulMinSidePortClock = 333*100; -#endif - - vgainfo.ulBootUpEngineClock = 500 * 100; // setup option on reference BIOS, 500 is default - - // find the DDR memory frequency - if (is_family10h()) { - value = pci_read_config32(k8_f2, 0x94); // read channel 0 DRAM Configuration High Register - if (extractbit(value, 14)) // if channel 0 disabled, channel 1 must have memory - value = pci_read_config32(k8_f2, 0x194);// read channel 1 DRAM Configuration High Register - vgainfo.ulBootUpUMAClock = memclk_lookup_fam10 [extractbits (value, 0, 2)] * 100; - } - if (is_family0Fh()) { - value = pci_read_config32(k8_f2, 0x94); - vgainfo.ulBootUpUMAClock = memclk_lookup_fam0F [extractbits (value, 20, 22)] * 100; - } - - /* UMA Channel Number: 1 or 2. */ - vgainfo.ucUMAChannelNumber = 1; - if (is_family0Fh()) { - value = pci_read_config32(k8_f2, 0x90); - if (extractbit(value, 11)) // 128-bit mode - vgainfo.ucUMAChannelNumber = 2; - } - if (is_family10h()) { - u32 dch0 = pci_read_config32(k8_f2, 0x94); - u32 dch1 = pci_read_config32(k8_f2, 0x194); - if (extractbit(dch0, 14) == 0 && extractbit(dch1, 14) == 0) { // both channels enabled - value = pci_read_config32(k8_f2, 0x110); - if (extractbit(value, 4)) // ganged mode - vgainfo.ucUMAChannelNumber = 2; - } - } - - // processor type - if (is_family0Fh()) - vgainfo.ulCPUCapInfo = 3; - if (is_family10h()) - vgainfo.ulCPUCapInfo = 2; - - /* HT speed */ - value = pci_read_config8(nb_dev, 0xd1); - value = ht_freq_lookup [value] * 100; // HT link frequency in MHz - vgainfo.ulHTLinkFreq = value * 100; // HT frequency in units of 100 MHz - vgainfo.ulHighVoltageHTLinkFreq = vgainfo.ulHTLinkFreq; - vgainfo.ulLowVoltageHTLinkFreq = vgainfo.ulHTLinkFreq; - - if (value <= 1800) - vgainfo.ulLowVoltageHTLinkFreq = vgainfo.ulHTLinkFreq; - else { - int sblink, cpuLnkFreqCap, nbLnkFreqCap; - value = pci_read_config32(k8_f0, 0x64); - sblink = extractbits(value, 8, 10); - cpuLnkFreqCap = pci_read_config16(k8_f0, 0x8a + sblink * 0x20); - nbLnkFreqCap = pci_read_config16(nb_dev, 0xd2); - if (cpuLnkFreqCap & nbLnkFreqCap & (1 << 10)) // if both 1800 MHz capable - vgainfo.ulLowVoltageHTLinkFreq = 1800*100; - } - - /* HT width. */ - value = pci_read_config8(nb_dev, 0xcb); - vgainfo.usMinDownStreamHTLinkWidth = - vgainfo.usMaxDownStreamHTLinkWidth = - vgainfo.usMinUpStreamHTLinkWidth = - vgainfo.usMaxUpStreamHTLinkWidth = - vgainfo.usMinHTLinkWidth = - vgainfo.usMaxHTLinkWidth = ht_width_lookup [extractbits(value, 0, 2)]; - - if (is_family0Fh()) { - vgainfo.usUMASyncStartDelay = 322; - vgainfo.usUMADataReturnTime = 286; - } - - if (is_family10h()) { - static u16 t0mult_lookup [] = {10, 50, 200, 2000}; - int t0time, t0scale; - value = pci_read_config32(k8_f0, 0x16c); - t0time = extractbits(value, 0, 3); - t0scale = extractbits(value, 4, 5); - vgainfo.usLinkStatusZeroTime = t0mult_lookup [t0scale] * t0time; - vgainfo.usUMASyncStartDelay = 100; - if (vgainfo.ulHTLinkFreq < 1000 * 100) { // less than 1000 MHz - vgainfo.usUMADataReturnTime = 300; - vgainfo.usLinkStatusZeroTime = 6 * 100; // 6us for GH in HT1 mode - } - else { - int lssel; - value = pci_read_config32(nb_dev, 0xac); - lssel = extractbits (value, 7, 8); - vgainfo.usUMADataReturnTime = 1300; - if (lssel == 0) vgainfo.usUMADataReturnTime = 150; - } - } - - /* Poweron DDI Lanes */ - poweron_ddi_lanes(nb_dev); - - printk(BIOS_DEBUG,"vgainfo:\n" - " ulBootUpEngineClock:%lu\n" - " ulBootUpUMAClock:%lu\n" - " ulBootUpSidePortClock:%lu\n" - " ulMinSidePortClock:%lu\n" - " ulSystemConfig:%lu\n" - " ulBootUpReqDisplayVector:%lu\n" - " ulOtherDisplayMisc:%lu\n" - " ulDDISlot1Config:%lu\n" - " ulDDISlot2Config:%lu\n" - - " ucMemoryType:%u\n" - " ucUMAChannelNumber:%u\n" - " ucDockingPinBit:%u\n" - " ucDockingPinPolarity:%u\n" - - " ulDockingPinCFGInfo:%lu\n" - " ulCPUCapInfo: %lu\n" - - " usNumberOfCyclesInPeriod:%hu\n" - " usMaxNBVoltage:%hu\n" - " usMinNBVoltage:%hu\n" - " usBootUpNBVoltage:%hu\n" - - " ulHTLinkFreq:%lu\n" - - " usMinHTLinkWidth:%hu\n" - " usMaxHTLinkWidth:%hu\n" - " usUMASyncStartDelay:%hu\n" - " usUMADataReturnTime:%hu\n" - " usLinkStatusZeroTime:%hu\n" - - " ulHighVoltageHTLinkFreq:%lu\n" - " ulLowVoltageHTLinkFreq:%lu\n" - - " usMaxUpStreamHTLinkWidth:%hu\n" - " usMaxDownStreamHTLinkWidth:%hu\n" - " usMinUpStreamHTLinkWidth:%hu\n" - " usMinDownStreamHTLinkWidth:%hu\n", - - (unsigned long)vgainfo.ulBootUpEngineClock, - (unsigned long)vgainfo.ulBootUpUMAClock, - (unsigned long)vgainfo.ulBootUpSidePortClock, - (unsigned long)vgainfo.ulMinSidePortClock, - (unsigned long)vgainfo.ulSystemConfig, - (unsigned long)vgainfo.ulBootUpReqDisplayVector, - (unsigned long)vgainfo.ulOtherDisplayMisc, - (unsigned long)vgainfo.ulDDISlot1Config, - (unsigned long)vgainfo.ulDDISlot2Config, - - vgainfo.ucMemoryType, - vgainfo.ucUMAChannelNumber, - vgainfo.ucDockingPinBit, - vgainfo.ucDockingPinPolarity, - - (unsigned long)vgainfo.ulDockingPinCFGInfo, - (unsigned long)vgainfo.ulCPUCapInfo, - - vgainfo.usNumberOfCyclesInPeriod, - vgainfo.usMaxNBVoltage, - vgainfo.usMinNBVoltage, - vgainfo.usBootUpNBVoltage, - - (unsigned long)vgainfo.ulHTLinkFreq, - - vgainfo.usMinHTLinkWidth, - vgainfo.usMaxHTLinkWidth, - vgainfo.usUMASyncStartDelay, - vgainfo.usUMADataReturnTime, - vgainfo.usLinkStatusZeroTime, - - (unsigned long)vgainfo.ulHighVoltageHTLinkFreq, - (unsigned long)vgainfo.ulLowVoltageHTLinkFreq, - - vgainfo.usMaxUpStreamHTLinkWidth, - vgainfo.usMaxDownStreamHTLinkWidth, - vgainfo.usMinUpStreamHTLinkWidth, - vgainfo.usMinDownStreamHTLinkWidth); - - - /* Transfer the Table to VBIOS. */ - pointer = (u32 *)&vgainfo; - for (i = 0; i < sizeof(ATOM_INTEGRATED_SYSTEM_INFO_V2); i+=4) { -#if CONFIG(GFXUMA) - *GpuF0MMReg = 0x80000000 + uma_memory_size - 512 + i; -#else - *GpuF0MMReg = 0x80000000 + 0x8000000 - 512 + i; -#endif - *(GpuF0MMReg+1) = *pointer++; - } - - /* GFX_InitLate. */ - { - u32 temp; - temp = pci_read_config8(dev, 0x4); - //temp &= ~1; /* CIM clears this bit. Strangely, I can'd. */ - temp |= 1<<1|1<<2; - pci_write_config8(dev, 0x4, temp); - - // if the GFX debug bar is writable, then it has - // been programmed and can be safely enabled now - temp = pci_read_config32(nb_dev, 0x8c); - - // if bits 1 (intgfx_enable) and 9 (gfx_debug_bar_enable) - // then enable gfx debug bar (set gxf_debug_decode_enable) - if (temp & 0x202) - temp |= (1 << 10); - pci_write_config32(nb_dev, 0x8c, temp); - - } - -#ifdef DONT_TRUST_RESOURCE_ALLOCATION - /* NB_SetupMGMMIO. */ - - /* clear MMIO and CreativeMMIO. */ - bpointer = (unsigned char *)MMIO; - for (i = 0; i < sizeof(MMIO); i++) { - *bpointer = 0; - bpointer++; - } - bpointer = (unsigned char *)CreativeMMIO; - for (i = 0; i < sizeof(CreativeMMIO); i++) { - *bpointer = 0; - bpointer++; - } - - /* Set MMIO ranges in K8. */ - /* Set MMIO TOM - 4G. */ - SetMMIO(0x400<<12, 0x1000000, 0x80, &MMIO[0]); - /* Set MMIO for VGA Legacy FB. */ - SetMMIO(0xa00, 0xc00, 0x80, &MMIO[0]); - - /* Set MMIO for non prefetchable P2P. */ - temp = pci_read_config32(dev0x14, 0x20); - Base32 = (temp & 0x0fff0) << 8; - Limit32 = ((temp & 0x0fff00000) + 0x100000) >> 8; - if (Base32 < Limit32) { - Status = GetCreativeMMIO(&CreativeMMIO[0]); - if (Status != CIM_ERROR) - SetMMIO(Base32, Limit32, 0x0, &MMIO[0]); - } - /* Set MMIO for prefetchable P2P. */ - if (Status != CIM_ERROR) { - temp = pci_read_config32(dev0x14, 0x24); - - Base32 = (temp & 0x0fff0) <<8; - Limit32 = ((temp & 0x0fff00000) + 0x100000) >> 8; - if (Base32 < Limit32) - SetMMIO(Base32, Limit32, 0x0, &MMIO[0]); - } - - FinalizeMMIO(&MMIO[0]); - - ProgramMMIO(&CreativeMMIO[0], 0, MMIO_ATTRIB_NP_ONLY); - ProgramMMIO(&MMIO[0], 0, MMIO_ATTRIB_NP_ONLY | MMIO_ATTRIB_BOTTOM_TO_TOP | MMIO_ATTRIB_SKIP_ZERO); -#endif - - pci_dev_init(dev); - - /* clk ind */ - clkind_write(dev, 0x08, 0x01); - clkind_write(dev, 0x0C, 0x22); - clkind_write(dev, 0x0F, 0x0); - clkind_write(dev, 0x11, 0x0); - clkind_write(dev, 0x12, 0x0); - clkind_write(dev, 0x14, 0x0); - clkind_write(dev, 0x15, 0x0); - clkind_write(dev, 0x16, 0x0); - clkind_write(dev, 0x17, 0x0); - clkind_write(dev, 0x18, 0x0); - clkind_write(dev, 0x19, 0x0); - clkind_write(dev, 0x1A, 0x0); - clkind_write(dev, 0x1B, 0x0); - clkind_write(dev, 0x1C, 0x0); - clkind_write(dev, 0x1D, 0x0); - clkind_write(dev, 0x1E, 0x0); - clkind_write(dev, 0x26, 0x0); - clkind_write(dev, 0x27, 0x0); - clkind_write(dev, 0x28, 0x0); - clkind_write(dev, 0x5C, 0x0); -} - -/** - * Set registers in RS780 and CPU to disable the internal GFX. - * Please refer to `rs780_internal_gfx_enable()`. - */ -static void rs780_internal_gfx_disable(struct device *dev) -{ - u32 l_dword; - struct device *nb_dev = pcidev_on_root(0x0, 0); - - /* Disable internal GFX and enable external GFX. */ - l_dword = pci_read_config32(nb_dev, 0x8c); - l_dword |= 1<<0; - l_dword &= ~(1<<1); - pci_write_config32(nb_dev, 0x8c, l_dword); - - dev->enabled = 0; -} - -/* -* Set registers in RS780 and CPU to enable the internal GFX. -* Please refer to CIM source code and BKDG. -*/ - -static void rs780_internal_gfx_enable(struct device *dev) -{ - u32 l_dword; - int i; - struct device *nb_dev = pcidev_on_root(0x0, 0); - msr_t sysmem; - -#if !CONFIG(GFXUMA) - u32 FB_Start, FB_End; -#endif - - printk(BIOS_DEBUG, "rs780_internal_gfx_enable dev = 0x%p, nb_dev = 0x%p.\n", dev, nb_dev); - - /* The system top memory in 780. */ - sysmem = rdmsr(TOP_MEM); - printk(BIOS_DEBUG, "Sysmem TOM = %x_%x\n", sysmem.hi, sysmem.lo); - pci_write_config32(nb_dev, 0x90, sysmem.lo); - - sysmem = rdmsr(TOP_MEM2); - printk(BIOS_DEBUG, "Sysmem TOM2 = %x_%x\n", sysmem.hi, sysmem.lo); - htiu_write_index(nb_dev, 0x31, sysmem.hi); - htiu_write_index(nb_dev, 0x30, sysmem.lo | 1); - - /* Disable external GFX and enable internal GFX. */ - l_dword = pci_read_config32(nb_dev, 0x8c); - l_dword &= ~(1<<0); - l_dword |= 1<<1; - pci_write_config32(nb_dev, 0x8c, l_dword); - - /* NB_SetDefaultIndexes */ - pci_write_config32(nb_dev, 0x94, 0x7f); - pci_write_config32(nb_dev, 0x60, 0x7f); - pci_write_config32(nb_dev, 0xe0, 0); - - /* NB_InitEarlyNB finished. */ - - /* LPC DMA Deadlock workaround? */ - /* GFX_InitCommon*/ - struct device *k8_f0 = pcidev_on_root(0x18, 0); - l_dword = pci_read_config32(k8_f0, 0x68); - l_dword &= ~(3 << 21); - l_dword |= (1 << 21); - pci_write_config32(k8_f0, 0x68, l_dword); - - /* GFX_InitCommon. */ - nbmc_write_index(nb_dev, 0x23, 0x00c00010); - set_nbmc_enable_bits(nb_dev, 0x16, 1<<15, 1<<15); - set_nbmc_enable_bits(nb_dev, 0x25, 0xffffffff, 0x111f111f); - set_htiu_enable_bits(nb_dev, 0x37, 1<<24, 1<<24); - -#if CONFIG(GFXUMA) - /* GFX_InitUMA. */ - /* Copy CPU DDR Controller to NB MC. */ - struct device *k8_f1 = pcidev_on_root(0x18, 1); - struct device *k8_f2 = pcidev_on_root(0x18, 2); - struct device *k8_f4 = pcidev_on_root(0x18, 4); - for (i = 0; i < 12; i++) { - l_dword = pci_read_config32(k8_f2, 0x40 + i * 4); - nbmc_write_index(nb_dev, 0x30 + i, l_dword); - } - - l_dword = pci_read_config32(k8_f2, 0x80); - nbmc_write_index(nb_dev, 0x3c, l_dword); - l_dword = pci_read_config32(k8_f2, 0x94); - set_nbmc_enable_bits(nb_dev, 0x3c, 0, !!(l_dword & (1<<22))<<16); - set_nbmc_enable_bits(nb_dev, 0x3c, 0, !!(l_dword & (1<< 8))<<17); - l_dword = pci_read_config32(k8_f2, 0x90); - set_nbmc_enable_bits(nb_dev, 0x3c, 0, !!(l_dword & (1<<10))<<18); - if (is_family10h()) { - for (i = 0; i < 12; i++) { - l_dword = pci_read_config32(k8_f2, 0x140 + i * 4); - nbmc_write_index(nb_dev, 0x3d + i, l_dword); - } - - l_dword = pci_read_config32(k8_f2, 0x180); - nbmc_write_index(nb_dev, 0x49, l_dword); - l_dword = pci_read_config32(k8_f2, 0x194); - set_nbmc_enable_bits(nb_dev, 0x49, 0, !!(l_dword & (1<<22))<<16); - set_nbmc_enable_bits(nb_dev, 0x49, 0, !!(l_dword & (1<< 8))<<17); - l_dword = pci_read_config32(k8_f2, 0x190); - set_nbmc_enable_bits(nb_dev, 0x49, 0, !!(l_dword & (1<<10))<<18); - - l_dword = pci_read_config32(k8_f2, 0x110); - nbmc_write_index(nb_dev, 0x4a, l_dword); - l_dword = pci_read_config32(k8_f2, 0x114); - nbmc_write_index(nb_dev, 0x4b, l_dword); - l_dword = pci_read_config32(k8_f4, 0x44); - set_nbmc_enable_bits(nb_dev, 0x4a, 0, !!(l_dword & (1<<22))<<24); - l_dword = pci_read_config32(k8_f1, 0x40); - nbmc_write_index(nb_dev, 0x4c, l_dword); - l_dword = pci_read_config32(k8_f1, 0xf0); - nbmc_write_index(nb_dev, 0x4d, l_dword); - } - - - /* Set UMA in the 780 side. */ - /* UMA start address, size. */ - /* The UMA starts at 0xC0000000 of internal RS780 address space - [31:16] addr of last byte | [31:16] addr of first byte - */ - nbmc_write_index(nb_dev, 0x10, ((uma_memory_size - 1 + 0xC0000000) & (~0xffff)) | 0xc000); - nbmc_write_index(nb_dev, 0x11, uma_memory_base); - nbmc_write_index(nb_dev, 0x12, 0); - nbmc_write_index(nb_dev, 0xf0, uma_memory_size >> 20); - /* GFX_InitUMA finished. */ -#else - /* GFX_InitSP. */ - /* SP memory:Hynix HY5TQ1G631ZNFP. 128MB = 64M * 16. 667MHz. DDR3. */ - - /* Enable Async mode. */ - set_nbmc_enable_bits(nb_dev, 0x06, 7<<8, 1<<8); - set_nbmc_enable_bits(nb_dev, 0x08, 1<<10, 0); - /* The last item in AsynchMclkTaskFileIndex. Why? */ - /* MC_MPLL_CONTROL2. */ - nbmc_write_index(nb_dev, 0x07, 0x40100028); - /* MC_MPLL_DIV_CONTROL. */ - nbmc_write_index(nb_dev, 0x0b, 0x00000028); - /* MC_MPLL_FREQ_CONTROL. */ - set_nbmc_enable_bits(nb_dev, 0x09, 3<<12|15<<16|15<<8, 1<<12|4<<16|0<<8); - /* MC_MPLL_CONTROL3. For PM. */ - set_nbmc_enable_bits(nb_dev, 0x08, 0xff<<13, 1<<13|1<<18); - /* MPLL_CAL_TRIGGER. */ - set_nbmc_enable_bits(nb_dev, 0x06, 0, 1<<0); - udelay(200); /* time is long enough? */ - set_nbmc_enable_bits(nb_dev, 0x06, 0, 1<<1); - set_nbmc_enable_bits(nb_dev, 0x06, 1<<0, 0); - /* MCLK_SRC_USE_MPLL. */ - set_nbmc_enable_bits(nb_dev, 0x02, 0, 1<<20); - - /* Pre Init MC. */ - nbmc_write_index(nb_dev, 0x01, 0x88108280); - set_nbmc_enable_bits(nb_dev, 0x02, ~(1<<20), 0x00030200); - nbmc_write_index(nb_dev, 0x04, 0x08881018); - nbmc_write_index(nb_dev, 0x05, 0x000000bb); - nbmc_write_index(nb_dev, 0x0c, 0x0f00001f); - nbmc_write_index(nb_dev, 0xa1, 0x01f10000); - /* MCA_INIT_DLL_PM. */ - set_nbmc_enable_bits(nb_dev, 0xc9, 1<<24, 1<<24); - nbmc_write_index(nb_dev, 0xa2, 0x74f20000); - nbmc_write_index(nb_dev, 0xa3, 0x8af30000); - nbmc_write_index(nb_dev, 0xaf, 0x47d0a41c); - nbmc_write_index(nb_dev, 0xb0, 0x88800130); - nbmc_write_index(nb_dev, 0xb1, 0x00000040); - nbmc_write_index(nb_dev, 0xb4, 0x41247000); - nbmc_write_index(nb_dev, 0xb5, 0x00066664); - nbmc_write_index(nb_dev, 0xb6, 0x00000022); - nbmc_write_index(nb_dev, 0xb7, 0x00000044); - nbmc_write_index(nb_dev, 0xb8, 0xbbbbbbbb); - nbmc_write_index(nb_dev, 0xb9, 0xbbbbbbbb); - nbmc_write_index(nb_dev, 0xba, 0x55555555); - nbmc_write_index(nb_dev, 0xc1, 0x00000000); - nbmc_write_index(nb_dev, 0xc2, 0x00000000); - nbmc_write_index(nb_dev, 0xc3, 0x80006b00); - nbmc_write_index(nb_dev, 0xc4, 0x00066664); - nbmc_write_index(nb_dev, 0xc5, 0x00000000); - nbmc_write_index(nb_dev, 0xd2, 0x00000022); - nbmc_write_index(nb_dev, 0xd3, 0x00000044); - nbmc_write_index(nb_dev, 0xd6, 0x00050005); - nbmc_write_index(nb_dev, 0xd7, 0x00000000); - nbmc_write_index(nb_dev, 0xd8, 0x00700070); - nbmc_write_index(nb_dev, 0xd9, 0x00700070); - nbmc_write_index(nb_dev, 0xe0, 0x00200020); - nbmc_write_index(nb_dev, 0xe1, 0x00200020); - nbmc_write_index(nb_dev, 0xe8, 0x00200020); - nbmc_write_index(nb_dev, 0xe9, 0x00200020); - nbmc_write_index(nb_dev, 0xe0, 0x00180018); - nbmc_write_index(nb_dev, 0xe1, 0x00180018); - nbmc_write_index(nb_dev, 0xe8, 0x00180018); - nbmc_write_index(nb_dev, 0xe9, 0x00180018); - - /* Misc options. */ - /* Memory Termination. */ - set_nbmc_enable_bits(nb_dev, 0xa1, 0x0ff, 0x044); - set_nbmc_enable_bits(nb_dev, 0xb4, 0xf00, 0xb00); -#if 0 - /* Controller Termination. */ - set_nbmc_enable_bits(nb_dev, 0xb1, 0x77770000, 0x77770000); -#endif - - /* OEM Init MC. 667MHz. */ - nbmc_write_index(nb_dev, 0xa8, 0x7a5aaa78); - nbmc_write_index(nb_dev, 0xa9, 0x514a2319); - nbmc_write_index(nb_dev, 0xaa, 0x54400520); - nbmc_write_index(nb_dev, 0xab, 0x441460ff); - nbmc_write_index(nb_dev, 0xa0, 0x20f00a48); - set_nbmc_enable_bits(nb_dev, 0xa2, ~(0xffffffc7), 0x10); - nbmc_write_index(nb_dev, 0xb2, 0x00000303); - set_nbmc_enable_bits(nb_dev, 0xb1, ~(0xffffff70), 0x45); - /* Do it later. */ - /* set_nbmc_enable_bits(nb_dev, 0xac, ~(0xfffffff0), 0x0b); */ - - /* Init PM timing. */ - for (i = 0; i < 4; i++) { - l_dword = nbmc_read_index(nb_dev, 0xa0+i); - nbmc_write_index(nb_dev, 0xc8+i, l_dword); - } - for (i = 0; i < 4; i++) { - l_dword = nbmc_read_index(nb_dev, 0xa8+i); - nbmc_write_index(nb_dev, 0xcc+i, l_dword); - } - l_dword = nbmc_read_index(nb_dev, 0xb1); - set_nbmc_enable_bits(nb_dev, 0xc8, 0xff<<24, ((l_dword&0x0f)<<24)|((l_dword&0xf00)<<20)); - - /* Init MC FB. */ - /* FB_Start = ; FB_End = ; iSpSize = 0x0080, 128MB. */ - nbmc_write_index(nb_dev, 0x11, 0x40000000); - FB_Start = 0xc00 + 0x080; - FB_End = 0xc00 + 0x080; - nbmc_write_index(nb_dev, 0x10, (((FB_End&0xfff)<<20)-0x10000)|(((FB_Start&0xfff)-0x080)<<4)); - set_nbmc_enable_bits(nb_dev, 0x0d, ~0x000ffff0, (FB_Start&0xfff)<<20); - nbmc_write_index(nb_dev, 0x0f, 0); - nbmc_write_index(nb_dev, 0x0e, (FB_Start&0xfff)|(0xaaaa<<12)); -#endif - - /* GFX_InitSP finished. */ -} - -static struct pci_operations lops_pci = { - .set_subsystem = pci_dev_set_subsystem, -}; - -static struct device_operations pcie_ops = { - .read_resources = rs780_gfx_read_resources, - .set_resources = pci_dev_set_resources, - .enable_resources = pci_dev_enable_resources, - .init = internal_gfx_pci_dev_init, /* The option ROM initializes the device. rs780_gfx_init, */ - .scan_bus = 0, - .enable = rs780_internal_gfx_enable, - .disable = rs780_internal_gfx_disable, - .ops_pci = &lops_pci, -}; - -/* - * We should list all of them here. - * */ -static const unsigned short pcie_780_ids[] = { - PCI_DEVICE_ID_ATI_RS780_INT_GFX, - PCI_DEVICE_ID_ATI_RS780C_INT_GFX, - PCI_DEVICE_ID_ATI_RS780M_INT_GFX, - PCI_DEVICE_ID_ATI_RS780MC_INT_GFX, - PCI_DEVICE_ID_ATI_RS780E_INT_GFX, - PCI_DEVICE_ID_ATI_RS785G_INT_GFX, - PCI_DEVICE_ID_ATI_RS785C_INT_GFX, - PCI_DEVICE_ID_ATI_RS785M_INT_GFX, - PCI_DEVICE_ID_ATI_RS785MC_INT_GFX, - PCI_DEVICE_ID_ATI_RS785D_INT_GFX, - 0 -}; - -static const struct pci_driver pcie_driver_780 __pci_driver = { - .ops = &pcie_ops, - .vendor = PCI_VENDOR_ID_ATI, - .devices = pcie_780_ids, -}; - -/* step 12 ~ step 14 from rpr */ -static void single_port_configuration(struct device *nb_dev, struct device *dev) -{ - u8 result, width; - u32 reg32; - struct southbridge_amd_rs780_config *cfg = - (struct southbridge_amd_rs780_config *)nb_dev->chip_info; - - printk(BIOS_DEBUG, "rs780_gfx_init single_port_configuration.\n"); - - /* step 12 training, releases hold training for GFX port 0 (device 2) */ - PcieReleasePortTraining(nb_dev, dev, 2); - result = PcieTrainPort(nb_dev, dev, 2); - printk(BIOS_DEBUG, "rs780_gfx_init single_port_configuration step12.\n"); - - /* step 13 Power Down Control */ - /* step 13.1 Enables powering down transmitter and receiver pads along with PLL macros. */ - set_pcie_enable_bits(nb_dev, 0x40, 1 << 0, 1 << 0); - - /* step 13.a Link Training was NOT successful */ - if (!result) { - set_nbmisc_enable_bits(nb_dev, 0x8, 0, 0x3 << 4); /* prevent from training. */ - set_nbmisc_enable_bits(nb_dev, 0xc, 0, 0x3 << 2); /* hide the GFX bridge. */ - if (cfg->gfx_tmds) - nbpcie_ind_write_index(nb_dev, 0x65, 0xccf0f0); - else { - nbpcie_ind_write_index(nb_dev, 0x65, 0xffffffff); - set_nbmisc_enable_bits(nb_dev, 0x7, 1 << 3, 1 << 3); - } - } else { /* step 13.b Link Training was successful */ - AtiPcieCfg.PortDetect |= 1 << 2; /* Port 2 */ - set_pcie_enable_bits(dev, 0xA2, 0xFF, 0x1); - reg32 = nbpcie_p_read_index(dev, 0x29); - width = reg32 & 0xFF; - printk(BIOS_DEBUG, "GFX Inactive Lanes = 0x%x.\n", width); - switch (width) { - case 1: - case 2: - nbpcie_ind_write_index(nb_dev, 0x65, - cfg->gfx_lane_reversal ? 0x7f7f : 0xccfefe); - break; - case 4: - nbpcie_ind_write_index(nb_dev, 0x65, - cfg->gfx_lane_reversal ? 0x3f3f : 0xccfcfc); - break; - case 8: - nbpcie_ind_write_index(nb_dev, 0x65, - cfg->gfx_lane_reversal ? 0x0f0f : 0xccf0f0); - break; - } - } - printk(BIOS_DEBUG, "rs780_gfx_init single_port_configuration step13.\n"); - - /* step 14 Reset Enumeration Timer, disables the shortening of the enumeration timer */ - set_pcie_enable_bits(dev, 0x70, 1 << 19, 1 << 19); - printk(BIOS_DEBUG, "rs780_gfx_init single_port_configuration step14.\n"); -} - -static void dual_port_configuration(struct device *nb_dev, struct device *dev) -{ - u8 result, width; - u32 reg32, dev_ind = dev->path.pci.devfn >> 3; - struct southbridge_amd_rs780_config *cfg = - (struct southbridge_amd_rs780_config *)nb_dev->chip_info; - - /* 5.4.1.2 Dual Port Configuration */ - set_nbmisc_enable_bits(nb_dev, 0x36, 1 << 31, 1 << 31); - set_nbmisc_enable_bits(nb_dev, 0x08, 0xF << 8, 0x5 << 8); - set_nbmisc_enable_bits(nb_dev, 0x36, 1 << 31, 0 << 31); - - /* 5.7. Training for Device 2 */ - /* 5.7.1. Releases hold training for GFX port 0 (device 2) */ - PcieReleasePortTraining(nb_dev, dev, dev_ind); - /* 5.7.2- 5.7.9. PCIE Link Training Sequence */ - result = PcieTrainPort(nb_dev, dev, dev_ind); - - /* Power Down Control for Device 2 */ - /* Link Training was NOT successful */ - if (!result) { - /* Powers down all lanes for port A */ - /* nbpcie_ind_write_index(nb_dev, 0x65, 0x0f0f); */ - /* Note: I have to disable the slot where there isn't a device, - * otherwise the system will hang. I don't know why. */ - set_nbmisc_enable_bits(nb_dev, 0x0c, 1 << dev_ind, 1 << dev_ind); - - } else { /* step 16.b Link Training was successful */ - AtiPcieCfg.PortDetect |= 1 << dev_ind; - reg32 = nbpcie_p_read_index(dev, 0xa2); - width = (reg32 >> 4) & 0x7; - printk(BIOS_DEBUG, "GFX LC_LINK_WIDTH = 0x%x.\n", width); - switch (width) { - case 1: - case 2: - nbpcie_ind_write_index(nb_dev, 0x65, - cfg->gfx_lane_reversal ? 0x0707 : 0x0e0e); - break; - case 4: - nbpcie_ind_write_index(nb_dev, 0x65, - cfg->gfx_lane_reversal ? 0x0303 : 0x0c0c); - break; - } - } -} - -/* For single port GFX configuration Only -* width: -* 000 = x16 -* 001 = x1 -* 010 = x2 -* 011 = x4 -* 100 = x8 -* 101 = x12 (not supported) -* 110 = x16 -*/ -static void dynamic_link_width_control(struct device *nb_dev, struct device *dev, u8 width) -{ - u32 reg32; - struct device *sb_dev; - struct southbridge_amd_rs780_config *cfg = - (struct southbridge_amd_rs780_config *)nb_dev->chip_info; - - /* step 5.9.1.1 */ - reg32 = nbpcie_p_read_index(dev, 0xa2); - - /* step 5.9.1.2 */ - set_pcie_enable_bits(nb_dev, 0x40, 1 << 0, 1 << 0); - /* step 5.9.1.3 */ - set_pcie_enable_bits(dev, 0xa2, 3 << 0, width << 0); - /* step 5.9.1.4 */ - set_pcie_enable_bits(dev, 0xa2, 1 << 8, 1 << 8); - /* step 5.9.2.4 */ - if (0 == cfg->gfx_reconfiguration) - set_pcie_enable_bits(dev, 0xa2, 1 << 11, 1 << 11); - - /* step 5.9.1.5 */ - do { - reg32 = nbpcie_p_read_index(dev, 0xa2); - } - while (reg32 & 0x100); - - /* step 5.9.1.6 */ - sb_dev = pcidev_on_root(8, 0); - do { - reg32 = pci_ext_read_config32(nb_dev, sb_dev, - PCIE_VC0_RESOURCE_STATUS); - } while (reg32 & VC_NEGOTIATION_PENDING); - - /* step 5.9.1.7 */ - reg32 = nbpcie_p_read_index(dev, 0xa2); - if (((reg32 & 0x70) >> 4) != 0x6) { - /* the unused lanes should be powered off. */ - } - - /* step 5.9.1.8 */ - set_pcie_enable_bits(nb_dev, 0x40, 1 << 0, 0 << 0); -} - -/* -* GFX Core initialization, dev2, dev3 -*/ -void rs780_gfx_init(struct device *nb_dev, struct device *dev, u32 port) -{ - u32 reg32; - struct southbridge_amd_rs780_config *cfg = - (struct southbridge_amd_rs780_config *)nb_dev->chip_info; - - printk(BIOS_DEBUG, "rs780_gfx_init, nb_dev=0x%p, dev=0x%p, port=0x%x.\n", - nb_dev, dev, port); - - /* GFX Core Initialization */ - //if (port == 2) return; - - /* step 2, TMDS, (only need if CMOS option is enabled) */ - if (cfg->gfx_tmds) { - /** - * PCIe Initialization for DDI. - * The VBIOS/Driver is responsible for DDI programming sequence, - * The SBIOS is responsible for programming the lane and clock muxing specific to each case. - * Refer to RPR Chapter 7: "PCIe Initialization for DDI". - * Note: This programming must be done before hold training is released. - */ - switch (cfg->gfx_pcie_config) { - case 1: /* 1x16 GFX -default case, no programming required */ - break; - case 2: /* 1x8 GFX on Lanes 0-7 */ - case 5: /* 1x4 GPP on Lanes 0-3 */ - set_nbmisc_enable_bits(nb_dev, 0x27, 0x1 << 6, 0x1 << 6); /* Disables PCIe mode on PHY Lanes 8-11 */ - set_nbmisc_enable_bits(nb_dev, 0x27, 0x1 << 7, 0x1 << 7); /* Disables PCIe mode on PHY Lanes 12-15 */ - break; - case 3: /* 1x8 on Lanes 8-15 */ - case 7: /* 1x4 GPP on Lanes 8-11 */ - /* TXCLK */ - set_nbmisc_enable_bits(nb_dev, 0x07, 1 << 16, 1 << 16); - set_nbmisc_enable_bits(nb_dev, 0x07, 0xF << 12, 0xF << 12); - set_nbmisc_enable_bits(nb_dev, 0x07, 0x3 << 24, 0x2 << 24); - set_nbmisc_enable_bits(nb_dev, 0x28, 0x3 << 0, 0x0 << 0); - /* RXCLK */ - set_nbmisc_enable_bits(nb_dev, 0x27, 0x3 << 8, 0x2 << 8); - set_nbmisc_enable_bits(nb_dev, 0x27, 0x3 << 10, 0x2 << 10); - set_nbmisc_enable_bits(nb_dev, 0x27, 0x3 << 12, 0x2 << 12); - set_nbmisc_enable_bits(nb_dev, 0x27, 0x3 << 14, 0x2 << 14); - /* TX Lane Muxing */ - set_nbmisc_enable_bits(nb_dev, 0x27, 0x1 << 2, 0x1 << 2); - set_nbmisc_enable_bits(nb_dev, 0x27, 0x1 << 3, 0x1 << 3); - set_nbmisc_enable_bits(nb_dev, 0x27, 0x1 << 4, 0x1 << 4); - set_nbmisc_enable_bits(nb_dev, 0x27, 0x1 << 5, 0x1 << 5); - break; - case 4: /* 2x8 */ - case 10: /* 1x4 GPP on Lanes 0-3 and 1x4 GPP on Lanes 8-11 */ - case 14: /* 1x8 GFX on Lanes 0-7 and 1x4 GPP on Lanes 8-11 */ - case 17: /* 1x4 GPP on Lanes 0-3 and 1x8 GFX on Lanes 8-15 */ - /* Set dual slot configuration */ - set_nbmisc_enable_bits(nb_dev, 0x08, 0xF << 8, 0x5 << 8); - break; - case 9: /* PCIe 2x4 GPPs on Lanes 0-7 */ - case 6: /* PCIe 1x4 GPP on Lanes 4-7 */ - /* Set dual slot configuration */ - set_nbmisc_enable_bits(nb_dev, 0x08, 0xF << 8, 0x5 << 8); - /* TXCLK */ - set_nbmisc_enable_bits(nb_dev, 0x07, 1 << 16, 0 << 16); - set_nbmisc_enable_bits(nb_dev, 0x07, 0xF << 12, 0x0 << 12); - set_nbmisc_enable_bits(nb_dev, 0x07, 0x3 << 20, 0x0 << 20); - set_nbmisc_enable_bits(nb_dev, 0x28, 0x1 << 0, 0x0 << 0); - /* RXCLK */ - set_nbmisc_enable_bits(nb_dev, 0x27, 0x3 << 8, 0x0 << 8); - set_nbmisc_enable_bits(nb_dev, 0x27, 0x3 << 10, 0x1 << 10); - set_nbmisc_enable_bits(nb_dev, 0x27, 0x3 << 12, 0x3 << 12); - set_nbmisc_enable_bits(nb_dev, 0x27, 0x3 << 14, 0x0 << 14); - /* TX Lane Muxing */ - set_nbmisc_enable_bits(nb_dev, 0x27, 0x1 << 1, 0x1 << 1); - set_nbmisc_enable_bits(nb_dev, 0x27, 0x1 << 6, 0x1 << 6); - set_nbmisc_enable_bits(nb_dev, 0x27, 0x1 << 7, 0x1 << 7); - break; - case 13: /* 2x4 GPPs on Lanes 8-15 */ - case 8: /* 1x4 GPP on Lanes 12-15 */ - /* Set dual slot configuration */ - set_nbmisc_enable_bits(nb_dev, 0x08, 0xF << 8, 0x5 << 8); - /* TXCLK */ - set_nbmisc_enable_bits(nb_dev, 0x07, 1 << 16, 1 << 16); - set_nbmisc_enable_bits(nb_dev, 0x07, 0xF << 12, 0xF << 12); - set_nbmisc_enable_bits(nb_dev, 0x07, 0x3 << 24, 0x2 << 24); - set_nbmisc_enable_bits(nb_dev, 0x28, 0x3 << 0, 0x3 << 0); - /* RXCLK */ - set_nbmisc_enable_bits(nb_dev, 0x27, 0x3 << 8, 0x2 << 8); - set_nbmisc_enable_bits(nb_dev, 0x27, 0x3 << 10, 0x3 << 10); - set_nbmisc_enable_bits(nb_dev, 0x27, 0x3 << 12, 0x1 << 12); - set_nbmisc_enable_bits(nb_dev, 0x27, 0x3 << 14, 0x2 << 14); - /* TX Lane Muxing */ - set_nbmisc_enable_bits(nb_dev, 0x27, 0x1 << 2, 0x1 << 2); - set_nbmisc_enable_bits(nb_dev, 0x28, 0x1 << 14, 0x1 << 14); - set_nbmisc_enable_bits(nb_dev, 0x27, 0x1 << 4, 0x1 << 4); - set_nbmisc_enable_bits(nb_dev, 0x27, 0x1 << 5, 0x1 << 5); - break; - case 15: /* 1x8 GFX on Lanes 0-7 and 1x4 GPP on Lanes 12-15 */ - case 11: /* 1x4 GPP on Lanes 0-3 and 1x4 GPP on Lanes 12-15 */ - /* Set dual slot configuration */ - set_nbmisc_enable_bits(nb_dev, 0x08, 0xF << 8, 0x5 << 8); - /* TXCLK */ - set_nbmisc_enable_bits(nb_dev, 0x07, 1 << 16, 0 << 16); - set_nbmisc_enable_bits(nb_dev, 0x07, 0xF << 12, 0x0 << 12); - set_nbmisc_enable_bits(nb_dev, 0x07, 0x3 << 20, 0x0 << 20); - set_nbmisc_enable_bits(nb_dev, 0x28, 0x3 << 0, 0x1 << 0); - /* RXCLK */ - set_nbmisc_enable_bits(nb_dev, 0x27, 0x3 << 8, 0x0 << 8); - set_nbmisc_enable_bits(nb_dev, 0x27, 0x3 << 10, 0x0 << 10); - set_nbmisc_enable_bits(nb_dev, 0x27, 0x3 << 12, 0x1 << 12); - set_nbmisc_enable_bits(nb_dev, 0x27, 0x3 << 14, 0x3 << 14); - /* TX Lane Muxing */ - set_nbmisc_enable_bits(nb_dev, 0x28, 0x1 << 14, 0x1 << 14); - set_nbmisc_enable_bits(nb_dev, 0x27, 0x1 << 6, 0x1 << 6); - break; - case 16: /* 1x8 GFX on Lanes 8-15 and 1x4 GPP on Lanes 4-7 */ - case 12: /* 1x4 GPP on Lanes 4-7 and 1x8 GFX on Lanes 8-15 */ - /* Set dual slot configuration */ - set_nbmisc_enable_bits(nb_dev, 0x08, 0xF << 8, 0x5 << 8); - /* TXCLK */ - set_nbmisc_enable_bits(nb_dev, 0x07, 1 << 16, 1 << 16); - set_nbmisc_enable_bits(nb_dev, 0x07, 0xF << 12, 0xF << 12); - set_nbmisc_enable_bits(nb_dev, 0x07, 0x3 << 24, 0x2 << 24); - set_nbmisc_enable_bits(nb_dev, 0x07, 0x3 << 22, 0x2 << 22); - set_nbmisc_enable_bits(nb_dev, 0x28, 0x3 << 0, 0x2 << 0); - /* RXCLK */ - set_nbmisc_enable_bits(nb_dev, 0x27, 0x3 << 8, 0x2 << 8); - set_nbmisc_enable_bits(nb_dev, 0x27, 0x3 << 10, 0x2 << 10); - set_nbmisc_enable_bits(nb_dev, 0x27, 0x3 << 12, 0x3 << 12); - set_nbmisc_enable_bits(nb_dev, 0x27, 0x3 << 14, 0x1 << 14); - /* TX Lane Muxing */ - set_nbmisc_enable_bits(nb_dev, 0x27, 0x1 << 2, 0x1 << 2); - set_nbmisc_enable_bits(nb_dev, 0x27, 0x1 << 3, 0x1 << 3); - set_nbmisc_enable_bits(nb_dev, 0x27, 0x1 << 1, 0x1 << 1); - set_nbmisc_enable_bits(nb_dev, 0x27, 0x1 << 4, 0x1 << 4); - break; - default: - printk(BIOS_INFO, "Incorrect configuration of external GFX slot.\n"); - break; - } - - /* DDI Configuration */ - switch (cfg->gfx_ddi_config) { - case 1: /* DDI_SL lanes0-3 */ - nbmisc_write_index(nb_dev, 0x74, GFX_CONFIG_DDI); - break; - case 2: /* DDI_SL lanes4-7 */ - nbmisc_write_index(nb_dev, 0x74, (GFX_CONFIG_DDI << 8)); - break; - case 5: /* DDI_SL lanes0-4, lanes4-7 */ - nbmisc_write_index(nb_dev, 0x74, (GFX_CONFIG_DDI << 8) | GFX_CONFIG_DDI); - break; - case 6: /* DDI_DL lanes0-7 */ - nbmisc_write_index(nb_dev, 0x74, (GFX_CONFIG_DDI << 8) | GFX_CONFIG_DDI); - break; - default: - printk(BIOS_INFO, "Incorrect configuration of external GFX slot.\n"); - break; - } - } - -#if 1 /* external clock mode */ - /* table 5-22, 5.9.1. REFCLK */ - /* 5.9.1.1. Disables the GFX REFCLK transmitter so that the GFX - * REFCLK PAD can be driven by an external source. */ - /* 5.9.1.2. Enables GFX REFCLK receiver to receive the REFCLK from an external source. */ - set_nbmisc_enable_bits(nb_dev, 0x38, 1 << 29 | 1 << 28 | 1 << 26, 1 << 28); - - /* 5.9.1.3 Selects the GFX REFCLK to be the source for PLL A. */ - /* 5.9.1.4 Selects the GFX REFCLK to be the source for PLL B. */ - /* 5.9.1.5 Selects the GFX REFCLK to be the source for PLL C. */ - reg32 = nbmisc_read_index(nb_dev, 0x28); - printk(BIOS_DEBUG, "misc 28 = %x\n", reg32); - - /* 5.9.1.6.Selects the single ended GFX REFCLK to be the source for core logic. */ - set_nbmisc_enable_bits(nb_dev, 0x6C, 1 << 31, 1 << 31); -#else /* internal clock mode */ - /* table 5-23, 5.9.1. REFCLK */ - /* 5.9.1.1. Enables the GFX REFCLK transmitter so that the GFX - * REFCLK PAD can be driven by the SB REFCLK. */ - /* 5.9.1.2. Disables GFX REFCLK receiver from receiving the - * REFCLK from an external source.*/ - set_nbmisc_enable_bits(nb_dev, 0x38, 1 << 29 | 1 << 28, 1 << 29 | 0 << 28); - - /* 5.9.1.3 Selects the GFX REFCLK to be the source for PLL A. */ - /* 5.9.1.4 Selects the GFX REFCLK to be the source for PLL B. */ - /* 5.9.1.5 Selects the GFX REFCLK to be the source for PLL C. */ - set_nbmisc_enable_bits(nb_dev, 0x28, 3 << 6 | 3 << 8 | 3 << 10, - 0); - reg32 = nbmisc_read_index(nb_dev, 0x28); - printk(BIOS_DEBUG, "misc 28 = %x\n", reg32); - - /* 5.9.1.6.Selects the single ended GFX REFCLK to be the source for core logic. */ - set_nbmisc_enable_bits(nb_dev, 0x6C, 1 << 31, 0 << 31); -#endif - - /* step 5.9.3, GFX overclocking, (only need if CMOS option is enabled) */ - /* 5.9.3.1. Increases PLL BW for 6G operation.*/ - /* set_nbmisc_enable_bits(nb_dev, 0x36, 0x3FF << 4, 0xB5 << 4); */ - /* skip */ - - /* step 5.9.4, reset the GFX link */ - /* step 5.9.4.1 asserts both calibration reset and global reset */ - set_nbmisc_enable_bits(nb_dev, 0x8, 0x3 << 14, 0x3 << 14); - - /* step 5.9.4.2 de-asserts calibration reset */ - set_nbmisc_enable_bits(nb_dev, 0x8, 1 << 14, 0 << 14); - - /* step 5.9.4.3 wait for at least 200us */ - udelay(300); - - /* step 5.9.4.4 de-asserts global reset */ - set_nbmisc_enable_bits(nb_dev, 0x8, 1 << 15, 0 << 15); - - /* 5.9.5 Reset PCIE_GFX Slot */ - /* It is done in mainboard.c */ - set_pcie_reset(); - mdelay(1); - set_pcie_dereset(); - - /* step 5.9.8 program PCIE memory mapped configuration space */ - /* done by enable_pci_bar3() before */ - - /* step 7 compliance state, (only need if CMOS option is enabled) */ - /* the compliance state is just for test. refer to 4.2.5.2 of PCIe specification */ - if (cfg->gfx_compliance) { - /* force compliance */ - set_nbmisc_enable_bits(nb_dev, 0x32, 1 << 6, 1 << 6); - /* release hold training for device 2. GFX initialization is done. */ - set_nbmisc_enable_bits(nb_dev, 0x8, 1 << 4, 0 << 4); - dynamic_link_width_control(nb_dev, dev, cfg->gfx_link_width); - printk(BIOS_DEBUG, "rs780_gfx_init step7.\n"); - return; - } - - /* 5.9.12 Core Initialization. */ - /* 5.9.12.1 sets RCB timeout to be 25ms */ - /* 5.9.12.2. RCB Cpl timeout on link down. */ - set_pcie_enable_bits(dev, 0x70, 7 << 16 | 1 << 19, 4 << 16 | 1 << 19); - printk(BIOS_DEBUG, "rs780_gfx_init step5.9.12.1.\n"); - - /* step 5.9.12.3 disables slave ordering logic */ - set_pcie_enable_bits(nb_dev, 0x20, 1 << 8, 1 << 8); - printk(BIOS_DEBUG, "rs780_gfx_init step5.9.12.3.\n"); - - /* step 5.9.12.4 sets DMA payload size to 64 bytes */ - set_pcie_enable_bits(nb_dev, 0x10, 7 << 10, 4 << 10); - /* 5.9.12.5. Blocks DMA traffic during C3 state. */ - set_pcie_enable_bits(dev, 0x10, 1 << 0, 0 << 0); - - /* 5.9.12.6. Disables RC ordering logic */ - set_pcie_enable_bits(nb_dev, 0x20, 1 << 9, 1 << 9); - - /* Enables TLP flushing. */ - /* Note: It is got from RS690. The system will hang without this action. */ - set_pcie_enable_bits(dev, 0x20, 1 << 19, 0 << 19); - - /* 5.9.12.7. Ignores DLLPs during L1 so that txclk can be turned off */ - set_pcie_enable_bits(nb_dev, 0x2, 1 << 0, 1 << 0); - - /* 5.9.12.8 Prevents LC to go from L0 to Rcv_L0s if L1 is armed. */ - set_pcie_enable_bits(dev, 0xA1, 1 << 11, 1 << 11); - - /* 5.9.12.9 CMGOOD_OVERRIDE for end point initiated lane degradation. */ - set_nbmisc_enable_bits(nb_dev, 0x6a, 1 << 17, 1 << 17); - printk(BIOS_DEBUG, "rs780_gfx_init step5.9.12.9.\n"); - - /* 5.9.12.10 Sets the timer in Config state from 20us to */ - /* 5.9.12.11 De-asserts RX_EN in L0s. */ - /* 5.9.12.12 Enables de-assertion of PG2RX_CR_EN to lock clock - * recovery parameter when lane is in electrical idle in L0s.*/ - set_pcie_enable_bits(dev, 0xB1, 1 << 23 | 1 << 19 | 1 << 28, 1 << 23 | 1 << 19 | 1 << 28); - - /* 5.9.12.13. Turns off offset calibration. */ - /* 5.9.12.14. Enables Rx Clock gating in CDR */ - set_nbmisc_enable_bits(nb_dev, 0x34, 1 << 10/* | 1 << 22 */, 1 << 10/* | 1 << 22 */); - - /* 5.9.12.15. Sets number of TX Clocks to drain TX Pipe to 3. */ - set_pcie_enable_bits(dev, 0xA0, 0xF << 4, 3 << 4); - - /* 5.9.12.16. Lets PI use Electrical Idle from PHY when - * turning off PLL in L1 at Gen2 speed instead Inferred Electrical Idle. */ - set_pcie_enable_bits(nb_dev, 0x40, 3 << 14, 2 << 14); - - /* 5.9.12.17. Prevents the Electrical Idle from causing a transition from Rcv_L0 to Rcv_L0s. */ - set_pcie_enable_bits(dev, 0xB1, 1 << 20, 1 << 20); - - /* 5.9.12.18. Prevents the LTSSM from going to Rcv_L0s if it has already - * acknowledged a request to go to L1. */ - set_pcie_enable_bits(dev, 0xA1, 1 << 11, 1 << 11); - - /* 5.9.12.19. LDSK only taking deskew on deskewing error detect */ - set_pcie_enable_bits(nb_dev, 0x40, 1 << 28, 0 << 28); - - /* 5.9.12.20. Bypasses lane de-skew logic if in x1 */ - set_pcie_enable_bits(nb_dev, 0xC2, 1 << 14, 1 << 14); - - /* 5.9.12.21. Sets Electrical Idle Threshold. */ - set_nbmisc_enable_bits(nb_dev, 0x35, 3 << 21, 2 << 21); - - /* 5.9.12.22. Advertises -6 dB de-emphasis value in TS1 Data Rate Identifier - * Only if CMOS Option in section. skip */ - - /* 5.9.12.23. Disables GEN2 capability of the device. */ - set_pcie_enable_bits(dev, 0xA4, 1 << 0, 0 << 0); - - /* 5.9.12.24.Disables advertising Upconfigure Support. */ - set_pcie_enable_bits(dev, 0xA2, 1 << 13, 1 << 13); - - /* 5.9.12.25. No comment in RPR. */ - set_nbmisc_enable_bits(nb_dev, 0x39, 1 << 10, 0 << 10); - - /* 5.9.12.26. This capacity is required since links wider than x1 and/or multiple link - * speed are supported */ - set_pcie_enable_bits(nb_dev, 0xC1, 1 << 0, 1 << 0); - - /* 5.9.12.27. Enables NVG86 ECO. A13 above only. */ - if (get_nb_rev(nb_dev) == REV_RS780_A12) /* A12 */ - set_pcie_enable_bits(dev, 0x02, 1 << 11, 1 << 11); - - /* 5.9.12.28 Hides and disables the completion timeout method. */ - set_pcie_enable_bits(nb_dev, 0xC1, 1 << 2, 0 << 2); - - /* 5.9.12.29. Use the bif_core de-emphasis strength by default. */ - /* set_nbmisc_enable_bits(nb_dev, 0x36, 1 << 28, 1 << 28); */ - - /* 5.9.12.30. Set TX arbitration algorithm to round robin */ - set_pcie_enable_bits(nb_dev, 0x1C, - 1 << 0 | 0x1F << 1 | 0x1F << 6, - 1 << 0 | 0x04 << 1 | 0x04 << 6); - - /* Single-port/Dual-port configuration. */ - switch (cfg->gfx_dual_slot) { - case 0: - /* step 1, lane reversal (only need if build config option is enabled) */ - if (cfg->gfx_lane_reversal) { - set_nbmisc_enable_bits(nb_dev, 0x36, 1 << 31, 1 << 31); - set_nbmisc_enable_bits(nb_dev, 0x33, 1 << 2, 1 << 2); - set_nbmisc_enable_bits(nb_dev, 0x36, 1 << 31, 0 << 31); - } - printk(BIOS_DEBUG, "rs780_gfx_init step1.\n"); - - printk(BIOS_DEBUG, "device = %x\n", dev->path.pci.devfn >> 3); - if ((dev->path.pci.devfn >> 3) == 2) { - single_port_configuration(nb_dev, dev); - } else { - set_nbmisc_enable_bits(nb_dev, 0xc, 0, 0x2 << 2); /* hide the GFX bridge. */ - printk(BIOS_INFO, "Single port. Do nothing.\n"); // If dev3 - } - - break; - case 1: - /* step 1, lane reversal (only need if build config option is enabled) */ - if (cfg->gfx_lane_reversal) { - set_nbmisc_enable_bits(nb_dev, 0x36, 1 << 31, 1 << 31); - set_nbmisc_enable_bits(nb_dev, 0x33, 1 << 2, 1 << 2); - set_nbmisc_enable_bits(nb_dev, 0x33, 1 << 3, 1 << 3); - set_nbmisc_enable_bits(nb_dev, 0x36, 1 << 31, 0 << 31); - } - printk(BIOS_DEBUG, "rs780_gfx_init step1.\n"); - /* step 1.1, dual-slot gfx configuration (only need if CMOS option is enabled) */ - /* AMD calls the configuration CrossFire */ - set_nbmisc_enable_bits(nb_dev, 0x0, 0xf << 8, 5 << 8); - printk(BIOS_DEBUG, "rs780_gfx_init step2.\n"); - - printk(BIOS_DEBUG, "device = %x\n", dev->path.pci.devfn >> 3); - dual_port_configuration(nb_dev, dev); - break; - - case 2: - if (is_dev3_present()) { - /* step 1, lane reversal (only need if CMOS option is enabled) */ - if (cfg->gfx_lane_reversal) { - set_nbmisc_enable_bits(nb_dev, 0x36, 1 << 31, 1 << 31); - set_nbmisc_enable_bits(nb_dev, 0x33, 1 << 2, 1 << 2); - set_nbmisc_enable_bits(nb_dev, 0x33, 1 << 3, 1 << 3); - set_nbmisc_enable_bits(nb_dev, 0x36, 1 << 31, 0 << 31); - } - printk(BIOS_DEBUG, "rs780_gfx_init step1.\n"); - /* step 1.1, dual-slot gfx configuration (only need if CMOS option is enabled) */ - /* AMD calls the configuration CrossFire */ - set_nbmisc_enable_bits(nb_dev, 0x0, 0xf << 8, 5 << 8); - printk(BIOS_DEBUG, "rs780_gfx_init step2.\n"); - - - printk(BIOS_DEBUG, "device = %x\n", dev->path.pci.devfn >> 3); - dual_port_configuration(nb_dev, dev); - - } else { - if (cfg->gfx_lane_reversal) { - set_nbmisc_enable_bits(nb_dev, 0x36, 1 << 31, 1 << 31); - set_nbmisc_enable_bits(nb_dev, 0x33, 1 << 2, 1 << 2); - set_nbmisc_enable_bits(nb_dev, 0x36, 1 << 31, 0 << 31); - } - printk(BIOS_DEBUG, "rs780_gfx_init step1.\n"); - - if ((dev->path.pci.devfn >> 3) == 2) - single_port_configuration(nb_dev, dev); - else { - set_nbmisc_enable_bits(nb_dev, 0xc, 0, 0x2 << 2); /* hide the GFX bridge. */ - printk(BIOS_DEBUG, "If dev3.., single port. Do nothing.\n"); - } - } - break; - - default: - printk(BIOS_INFO, "Incorrect configuration of external GFX slot.\n"); - break; - } -} diff --git a/src/southbridge/amd/rs780/ht.c b/src/southbridge/amd/rs780/ht.c deleted file mode 100644 index 8943fc1300..0000000000 --- a/src/southbridge/amd/rs780/ht.c +++ /dev/null @@ -1,86 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2010 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include -#include -#include -#include "rs780.h" - -/* for UMA internal graphics */ -void avoid_lpc_dma_deadlock(struct device *nb_dev, struct device *sb_dev) -{ - struct device *cpu_f0; - u32 reg32; - - cpu_f0 = pcidev_on_root(0x18, 0); - set_nbcfg_enable_bits(cpu_f0, 0x68, 3 << 21, 1 << 21); - - reg32 = nbpcie_p_read_index(sb_dev, 0x10); - reg32 |= 0x100; /* bit9=1 */ - nbpcie_p_write_index(sb_dev, 0x10, reg32); - - reg32 = nbpcie_p_read_index(nb_dev, 0x10); - reg32 |= 0x100; /* bit9=1 */ - nbpcie_p_write_index(nb_dev, 0x10, reg32); - - /* Enable NP protocol over PCIE for memory-mapped writes targeting LPC - * Set this bit to avoid a deadlock condition. */ - reg32 = htiu_read_index(nb_dev, 0x6); - reg32 |= 0x1000000; /* bit26 */ - htiu_write_index(nb_dev, 0x6, reg32); -} - -static void pcie_init(struct device *dev) -{ - /* Enable pci error detecting */ - u32 dword; - - printk(BIOS_INFO, "pcie_init in rs780_ht.c\n"); - - /* System error enable */ - dword = pci_read_config32(dev, 0x04); - dword |= (1 << 8); /* System error enable */ - dword |= (1 << 30); /* Clear possible errors */ - pci_write_config32(dev, 0x04, dword); - - /* - * 1 is APIC enable - * 18 is enable nb to accept A4 interrupt request from SB. - */ - dword = pci_read_config32(dev, 0x4C); - dword |= 1 << 1 | 1 << 18; /* Clear possible errors */ - pci_write_config32(dev, 0x4C, dword); -} - -static struct pci_operations lops_pci = { - .set_subsystem = pci_dev_set_subsystem, -}; - -static struct device_operations ht_ops = { - .read_resources = pci_dev_read_resources, - .set_resources = pci_dev_set_resources, - .enable_resources = pci_dev_enable_resources, - .init = pcie_init, - .scan_bus = 0, - .ops_pci = &lops_pci, -}; - -static const struct pci_driver ht_driver __pci_driver = { - .ops = &ht_ops, - .vendor = PCI_VENDOR_ID_AMD, - .device = PCI_DEVICE_ID_AMD_RS780_HT, -}; diff --git a/src/southbridge/amd/rs780/pcie.c b/src/southbridge/amd/rs780/pcie.c deleted file mode 100644 index 437a62aa87..0000000000 --- a/src/southbridge/amd/rs780/pcie.c +++ /dev/null @@ -1,406 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2010 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include -#include -#include -#include "rs780.h" - -/*------------------------------------------------ -* Global variable -------------------------------------------------*/ -PCIE_CFG AtiPcieCfg = { - PCIE_ENABLE_STATIC_DEV_REMAP, /* Config */ - 0, /* ResetReleaseDelay */ - 0, /* Gfx0Width */ - 0, /* Gfx1Width */ - 0, /* GfxPayload */ - 0, /* GppPayload */ - 0, /* PortDetect, filled by GppSbInit */ - 0, /* PortHp */ - 0, /* DbgConfig */ - 0, /* DbgConfig2 */ - 0, /* GfxLx */ - 0, /* GppLx */ - 0, /* NBSBLx */ - 0, /* PortSlotInit */ - 0, /* Gfx0Pwr */ - 0, /* Gfx1Pwr */ - 0 /* GppPwr */ -}; - -static void PciePowerOffGppPorts(struct device *nb_dev, struct device *dev, u32 port); -static void ValidatePortEn(struct device *nb_dev); - -static void ValidatePortEn(struct device *nb_dev) -{ -} - -/***************************************************************** -* Compliant with CIM_33's PCIEPowerOffGppPorts -* Power off unused GPP lines -*****************************************************************/ -static void PciePowerOffGppPorts(struct device *nb_dev, struct device *dev, u32 port) -{ - u32 reg; - u16 state_save; - struct southbridge_amd_rs780_config *cfg = - (struct southbridge_amd_rs780_config *)nb_dev->chip_info; - u8 state = cfg->port_enable; - - if (!(AtiPcieCfg.Config & PCIE_DISABLE_HIDE_UNUSED_PORTS)) - state &= AtiPcieCfg.PortDetect; - state = ~state; - state &= (1 << 4) + (1 << 5) + (1 << 6) + (1 << 7); - state_save = state << 17; - state &= ~(AtiPcieCfg.PortHp); - reg = nbmisc_read_index(nb_dev, 0x0c); - reg |= state; - nbmisc_write_index(nb_dev, 0x0c, reg); - - reg = nbmisc_read_index(nb_dev, 0x08); - reg |= state_save; - nbmisc_write_index(nb_dev, 0x08, reg); - - if ((AtiPcieCfg.Config & PCIE_OFF_UNUSED_GPP_LANES) - && !(AtiPcieCfg. - Config & (PCIE_DISABLE_HIDE_UNUSED_PORTS + - PCIE_GFX_COMPLIANCE))) { - } - - /* step 3 Power Down Control for Southbridge */ - if (port != 8) - return; - - reg = nbpcie_p_read_index(dev, 0xa2); - - switch ((reg >> 4) & 0x7) { /* get bit 4-6, LC_LINK_WIDTH_RD */ - case 1: - set_pcie_enable_bits(nb_dev, 0x65 | PCIE_CORE_INDEX_GPPSB, - 0x0f0f, 0x0e0e); - break; - case 2: - set_pcie_enable_bits(nb_dev, 0x65 | PCIE_CORE_INDEX_GPPSB, - 0x0f0f, 0x0c0c); - break; - default: - break; - } -} - -/********************************************************************** -**********************************************************************/ -static void switching_gppsb_configurations(struct device *nb_dev, struct device *sb_dev) -{ - u32 reg; - struct southbridge_amd_rs780_config *cfg = - (struct southbridge_amd_rs780_config *)nb_dev->chip_info; - - /* 5.5.7.1-3 enables GPP reconfiguration */ - reg = nbmisc_read_index(nb_dev, PCIE_NBCFG_REG7); - reg |= - (RECONFIG_GPPSB_EN + RECONFIG_GPPSB_LINK_CONFIG + - RECONFIG_GPPSB_ATOMIC_RESET); - nbmisc_write_index(nb_dev, PCIE_NBCFG_REG7, reg); - - /* 5.5.7.4a. De-asserts STRAP_BIF_all_valid for PCIE-GPPSB core */ - reg = nbmisc_read_index(nb_dev, 0x66); - reg |= 1 << 31; - nbmisc_write_index(nb_dev, 0x66, reg); - /* 5.5.7.4b. sets desired GPPSB configurations, bit4-7 */ - reg = nbmisc_read_index(nb_dev, 0x67); - reg &= 0xFFFFff0f; /* clean */ - reg |= cfg->gppsb_configuration << 4; - nbmisc_write_index(nb_dev, 0x67, reg); - -#if 1 - /* NOTE: - * In CIMx 4.5.0 and RPR, 4c is done before 5 & 6. But in this way, - * a x4 device in port B (dev 4) of Configuration B can only be detected - * as x1, instead of x4. When the port B is being trained, the - * LC_CURRENT_STATE is 6 and the LC_LINK_WIDTH_RD is 1. We have - * to set the PCIEIND:0x65 as 0xE0E0 and reset the slot. Then the card - * seems to work in x1 mode. - * In the 2nd way below, we do the 5 & 6 before 4c. it conforms the - * CIMx 4.3.0. It conflicts with RPR. But based on the test result I've - * made so far, I haven't found any mistake. - */ - /* 5.5.7.4c. Asserts STRAP_BIF_all_valid for PCIE-GPPSB core */ - reg = nbmisc_read_index(nb_dev, 0x66); - reg &= ~(1 << 31); - nbmisc_write_index(nb_dev, 0x66, reg); - - /* 5.5.7.5-6. read bit14 and write back its inverted value */ - reg = nbmisc_read_index(nb_dev, PCIE_NBCFG_REG7); - reg ^= RECONFIG_GPPSB_GPPSB; - nbmisc_write_index(nb_dev, PCIE_NBCFG_REG7, reg); -#else - /* 5.5.7.5-6. read bit14 and write back its inverted value */ - reg = nbmisc_read_index(nb_dev, PCIE_NBCFG_REG7); - reg ^= RECONFIG_GPPSB_GPPSB; - nbmisc_write_index(nb_dev, PCIE_NBCFG_REG7, reg); - - /* 5.5.7.4c. Asserts STRAP_BIF_all_valid for PCIE-GPPSB core */ - reg = nbmisc_read_index(nb_dev, 0x66); - reg &= ~(1 << 31); - nbmisc_write_index(nb_dev, 0x66, reg); -#endif - /* 5.5.7.7. delay 1ms */ - mdelay(1); - - /* 5.5.7.8. waits until SB has trained to L0, poll for bit0-5 = 0x10 */ - do { - reg = nbpcie_p_read_index(sb_dev, PCIE_LC_STATE0); - reg &= 0x3f; /* remain LSB [5:0] bits */ - } while (LC_STATE_RECONFIG_GPPSB != reg); - - /* 5.5.7.9.ensures that virtual channel negotiation is completed. poll for bit1 = 0 */ - do { - reg = - pci_ext_read_config32(nb_dev, sb_dev, - PCIE_VC0_RESOURCE_STATUS); - } while (reg & VC_NEGOTIATION_PENDING); -} - -static void switching_gpp_configurations(struct device *nb_dev, struct device *sb_dev) -{ - u32 reg; - struct southbridge_amd_rs780_config *cfg = - (struct southbridge_amd_rs780_config *)nb_dev->chip_info; - - /* 5.6.2.1. De-asserts STRAP_BIF_all_valid for PCIE-GPP core */ - reg = nbmisc_read_index(nb_dev, 0x22); - reg |= 1 << 14; - nbmisc_write_index(nb_dev, 0x22, reg); - /* 5.6.2.2. sets desired GPP configurations, bit7-10 */ - reg = nbmisc_read_index(nb_dev, 0x2D); - reg &= ~(0xF << 7); /* clean */ - reg |= cfg->gpp_configuration << 7; - nbmisc_write_index(nb_dev, 0x2D, reg); - /* 5.6.2.3. Asserts STRAP_BIF_all_valid for PCIE-GPP core */ - reg = nbmisc_read_index(nb_dev, 0x22); - reg &= ~(1 << 14); - nbmisc_write_index(nb_dev, 0x22, reg); -} - -/***************************************************************** -* The rs780 uses NBCONFIG:0x1c (BAR3) to map the PCIE Extended Configuration -* Space to a 256MB range within the first 4GB of addressable memory. -*****************************************************************/ -void enable_pcie_bar3(struct device *nb_dev) -{ - printk(BIOS_DEBUG, "enable_pcie_bar3()\n"); - set_nbcfg_enable_bits(nb_dev, 0x7C, 1 << 30, 1 << 30); /* Enables writes to the BAR3 register. */ - set_nbcfg_enable_bits(nb_dev, 0x84, 7 << 16, 0 << 16); - - pci_write_config32(nb_dev, 0x1C, EXT_CONF_BASE_ADDRESS); /* PCIEMiscInit */ - pci_write_config32(nb_dev, 0x20, 0x00000000); - set_htiu_enable_bits(nb_dev, 0x32, 1 << 28, 1 << 28); /* PCIEMiscInit */ - ProgK8TempMmioBase(1, EXT_CONF_BASE_ADDRESS, TEMP_MMIO_BASE_ADDRESS); -} - -/***************************************************************** -* We should disable bar3 when we want to exit rs780_enable, because bar3 will be -* remapped in set_resource later. -*****************************************************************/ -void disable_pcie_bar3(struct device *nb_dev) -{ - printk(BIOS_DEBUG, "disable_pcie_bar3()\n"); - pci_write_config32(nb_dev, 0x1C, 0); /* clear BAR3 address */ - set_nbcfg_enable_bits(nb_dev, 0x7C, 1 << 30, 0 << 30); /* Disable writes to the BAR3. */ - set_htiu_enable_bits(nb_dev, 0x32, 1 << 28, 0); /* disable bar3 decode */ - ProgK8TempMmioBase(0, EXT_CONF_BASE_ADDRESS, TEMP_MMIO_BASE_ADDRESS); -} - -/***************************************** -* Compliant with CIM_33's PCIEGPPInit -* nb_dev: -* root bridge struct -* dev: -* p2p bridge struct -* port: -* p2p bridge number, 4-10 -*****************************************/ -void rs780_gpp_sb_init(struct device *nb_dev, struct device *dev, u32 port) -{ - u32 gfx_gpp_sb_sel; - struct southbridge_amd_rs780_config *cfg = - (struct southbridge_amd_rs780_config *)nb_dev->chip_info; - printk(BIOS_DEBUG, "gpp_sb_init nb_dev=0x%x, dev=0x%x, port=0x%x\n", nb_dev->path.pci.devfn, dev->path.pci.devfn, port); - - gfx_gpp_sb_sel = port >= 4 && port <= 8 ? - PCIE_CORE_INDEX_GPPSB : /* 4,5,6,7,8 */ - PCIE_CORE_INDEX_GPP; /* 9,10 */ - /* init GPP core */ - /* 5.10.8.3. Disable slave ordering logic */ - set_pcie_enable_bits(nb_dev, 0x20 | gfx_gpp_sb_sel, 1 << 8, - 1 << 8); - /* 5.10.8.7. PCIE initialization 5.10.2: rpr 2.12*/ - set_pcie_enable_bits(nb_dev, 0x02 | gfx_gpp_sb_sel, 1 << 0, 1 << 0); /* no description in datasheet. */ - - /* init GPPSB port. rpr 5.10.8 */ - /* 5.10.8.1-5.10.8.2. Sets RCB timeout to be 100ms/4=25ms by setting bits[18:16] to 3 h4 - * and shortens the enumeration timer by setting bit[19] to 1 - */ - set_pcie_enable_bits(dev, 0x70, 0xF << 16, 0x4 << 16 | 1 << 19); - /* 5.10.8.4. Sets DMA payload size to 64 bytes. */ - set_pcie_enable_bits(nb_dev, 0x10 | gfx_gpp_sb_sel, 7 << 10, 4 << 10); - /* 5.10.8.6. Disable RC ordering logic */ - set_pcie_enable_bits(nb_dev, 0x20 | gfx_gpp_sb_sel, 1 << 9, 1 << 9); - /* 5.10.8.7. Ignores DLLs druing L1 */ - set_pcie_enable_bits(nb_dev, 0x02 | gfx_gpp_sb_sel, 1 << 0, 1 << 0); - /* 5.10.8.8. Prevents LCto go from L0 to Rcv_L0s if L1 is armed. */ - set_pcie_enable_bits(dev, 0xA1, 1 << 11, 1 << 11); - /* 5.10.8.9. Sets timer in Config state from 20us to 1us. - * 5.10.8.10. De-asserts RX_EN in L0s - * 5.10.8.11. Enables de-assertion of PG2RX_CR_EN to lock clock recovery parameter when .. */ - set_pcie_enable_bits(dev, 0xB1, 1 << 23 | 1 << 19 | 1 << 28, 1 <<23 | 1 << 19 | 1 << 28); - /* 5.10.8.12. Turns off offset calibration */ - /* 5.10.8.13. Enables Rx Clock gating in CDR */ - if (gfx_gpp_sb_sel == PCIE_CORE_INDEX_GPPSB) - set_nbmisc_enable_bits(nb_dev, 0x67, 1 << 14 | 1 << 26, 1 << 14 | 1 << 26); /* 4,5,6,7 */ - else - set_nbmisc_enable_bits(nb_dev, 0x24, 1 << 29 | 1 << 28, 1 << 29 | 1 << 28); /* 9,10 */ - /* 5.10.8.14. Sets number of TX Clocks to drain TX Pipe to 3 */ - set_pcie_enable_bits(dev, 0xA0, 0xF << 4, 0x3 << 4); - /* 5.10.8.15. empty */ - /* 5.10.8.16. P_ELEC_IDLE_MODE */ - set_pcie_enable_bits(nb_dev, 0x40 | gfx_gpp_sb_sel, 0x3 << 14, 0x2 << 14); - /* 5.10.8.17. LC_BLOCK_EL_IDLE_IN_L0 */ - set_pcie_enable_bits(dev, 0xB1, 1 << 20, 1 << 20); - /* 5.10.8.18. LC_DONT_GO_TO_L0S_IFL1_ARMED */ - set_pcie_enable_bits(dev, 0xA1, 1 << 11, 1 << 11); - /* 5.10.8.19. RXP_REALIGN_ON_EACH_TSX_OR_SKP */ - set_pcie_enable_bits(nb_dev, 0x40 | gfx_gpp_sb_sel, 1 << 28, 0 << 28); - /* 5.10.8.20. Bypass lane de-skew logic if in x1 */ - set_pcie_enable_bits(nb_dev, 0xC2 | gfx_gpp_sb_sel, 1 << 14, 1 << 14); - /* 5.10.8.21. sets electrical idle threshold. */ - if (gfx_gpp_sb_sel == PCIE_CORE_INDEX_GPPSB) - set_nbmisc_enable_bits(nb_dev, 0x6A, 3 << 22, 2 << 22); - else - set_nbmisc_enable_bits(nb_dev, 0x24, 3 << 16, 2 << 16); - - /* 5.10.8.22. Disable GEN2 */ - /* TODO: should be 2 separated cases. */ - set_nbmisc_enable_bits(nb_dev, 0x39, 1 << 31, 0 << 31); - set_nbmisc_enable_bits(nb_dev, 0x22, 1 << 5, 0 << 5); - set_nbmisc_enable_bits(nb_dev, 0x34, 1 << 31, 0 << 31); - set_nbmisc_enable_bits(nb_dev, 0x37, 7 << 5, 0 << 5); - /* 5.10.8.23. Disables GEN2 capability of the device. RPR says enable? No! */ - set_pcie_enable_bits(dev, 0xA4, 1 << 0, 0 << 0); - /* 5.10.8.24. Disable advertising upconfigure support. */ - set_pcie_enable_bits(dev, 0xA2, 1 << 13, 1 << 13); - /* 5.10.8.25-26. STRAP_BIF_DSN_EN */ - if (gfx_gpp_sb_sel == PCIE_CORE_INDEX_GPPSB) - set_nbmisc_enable_bits(nb_dev, 0x68, 1 << 19, 0 << 19); - else - set_nbmisc_enable_bits(nb_dev, 0x22, 1 << 3, 0 << 3); - /* 5.10.8.27-28. */ - set_pcie_enable_bits(nb_dev, 0xC1 | gfx_gpp_sb_sel, 1 << 0 | 1 << 2, 1 << 0 | 0 << 2); - /* 5.10.8.29. Uses the bif_core de-emphasis strength by default. */ - if (gfx_gpp_sb_sel == PCIE_CORE_INDEX_GPPSB) { - set_nbmisc_enable_bits(nb_dev, 0x67, 1 << 10, 1 << 10); - set_nbmisc_enable_bits(nb_dev, 0x36, 1 << 29, 1 << 29); - } - else { - set_nbmisc_enable_bits(nb_dev, 0x39, 1 << 30, 1 << 30); - } - /* 5.10.8.30. Set TX arbitration algorithm to round robin. */ - set_pcie_enable_bits(nb_dev, 0x1C | gfx_gpp_sb_sel, - 1 << 0 | 0x1F << 1 | 0x1F << 6, - 1 << 0 | 0x04 << 1 | 0x04 << 6); - - /* check compliance rpr step 2.1*/ - if (AtiPcieCfg.Config & PCIE_GPP_COMPLIANCE) { - u32 tmp; - tmp = nbmisc_read_index(nb_dev, 0x67); - tmp |= 1 << 3; - nbmisc_write_index(nb_dev, 0x67, tmp); - } - - /* step 5: dynamic slave CPL buffer allocation. Disable it, otherwise linux hangs. Why? */ - /* set_pcie_enable_bits(nb_dev, 0x20 | gfx_gpp_sb_sel, 1 << 11, 1 << 11); */ - - /* step 5a: Training for GPP devices */ - /* init GPP */ - switch (port) { - case 4: /* GPP */ - case 5: - case 6: - case 7: - case 9: - case 10: - /* 5.10.8.5. Blocks DMA traffic during C3 state */ - set_pcie_enable_bits(dev, 0x10, 1 << 0, 0 << 0); - /* Enables TLP flushing */ - set_pcie_enable_bits(dev, 0x20, 1 << 19, 0 << 19); - - /* check port enable */ - if (cfg->port_enable & (1 << port)) { - PcieReleasePortTraining(nb_dev, dev, port); - if (!(AtiPcieCfg.Config & PCIE_GPP_COMPLIANCE)) { - u8 res = PcieTrainPort(nb_dev, dev, port); - printk(BIOS_DEBUG, "PcieTrainPort port=0x%x result=%d\n", port, res); - if (res) { - AtiPcieCfg.PortDetect |= 1 << port; - } - } - } - break; - case 8: /* SB */ - break; - } - PciePowerOffGppPorts(nb_dev, dev, port); -} - -/***************************************** -* Compliant with CIM_33's PCIEConfigureGPPCore -*****************************************/ -void config_gpp_core(struct device *nb_dev, struct device *sb_dev) -{ - u32 reg; - struct southbridge_amd_rs780_config *cfg = - (struct southbridge_amd_rs780_config *)nb_dev->chip_info; - - reg = nbmisc_read_index(nb_dev, 0x20); - if (AtiPcieCfg.Config & PCIE_ENABLE_STATIC_DEV_REMAP) - reg &= 0xfffffffd; /* set bit1 = 0 */ - else - reg |= 0x2; /* set bit1 = 1 */ - nbmisc_write_index(nb_dev, 0x20, reg); - - reg = nbmisc_read_index(nb_dev, 0x67); /* get STRAP_BIF_LINK_CONFIG_GPPSB at bit 4-7 */ - if (cfg->gppsb_configuration != ((reg >> 4) & 0xf)) - switching_gppsb_configurations(nb_dev, sb_dev); - reg = nbmisc_read_index(nb_dev, 0x2D); /* get STRAP_BIF_LINK_CONFIG_GPP at bit 7-10 */ - if (cfg->gpp_configuration != ((reg >> 7) & 0xf)) - switching_gpp_configurations(nb_dev, sb_dev); - ValidatePortEn(nb_dev); -} - -/** - * Hide unused Gpp port - */ -void pcie_hide_unused_ports(struct device *nb_dev) -{ - u16 hide = 0x6FC; /* skip port 0, 1, 8 */ - - hide &= ~(AtiPcieCfg.PortDetect | AtiPcieCfg.PortHp); - printk(BIOS_INFO, "rs780 unused GPP ports bitmap=0x%03x, force disabled\n", hide); - set_nbmisc_enable_bits(nb_dev, 0x0C, 0xFC, (hide & 0xFC)); /* bridge 2-7 */ - set_nbmisc_enable_bits(nb_dev, 0x0C, 0x30000, ((hide >> 9) & 0x3) << 16); /* bridge 9-a */ -} diff --git a/src/southbridge/amd/rs780/rev.h b/src/southbridge/amd/rs780/rev.h deleted file mode 100644 index 0db7b9622d..0000000000 --- a/src/southbridge/amd/rs780/rev.h +++ /dev/null @@ -1,23 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2010 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef __RS780_REV_H__ -#define __RS780_REV_H__ - -#define REV_RS780_A11 0 -#define REV_RS780_A12 1 -#define REV_RS780_A13 2 - -#endif /* __RS780_REV_H__ */ diff --git a/src/southbridge/amd/rs780/rs780.c b/src/southbridge/amd/rs780/rs780.c deleted file mode 100644 index fa9433b56b..0000000000 --- a/src/southbridge/amd/rs780/rs780.c +++ /dev/null @@ -1,363 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2010 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include -#include -#include -#include -#include -#include "rs780.h" - -/***************************************** -* rs780_config_misc_clk() -*****************************************/ -void static rs780_config_misc_clk(struct device *nb_dev) -{ - u32 reg; - u16 word; - u8 byte; - pci_devfn_t d0f1 = PCI_DEV(0, 0, 1); - - reg = pci_read_config32(nb_dev, 0x4c); - reg |= 1 << 0; - pci_write_config32(nb_dev, 0x4c, reg); - - word = pci_io_read_config16(d0f1, 0xf8); - word &= 0xf00; - pci_io_write_config16(d0f1, 0xf8, word); - - word = pci_io_read_config16(d0f1, 0xe8); - word &= ~((1 << 12) | (1 << 13) | (1 << 14)); - word |= 1 << 13; - pci_io_write_config16(d0f1, 0xe8, word); - - reg = pci_io_read_config32(d0f1, 0x94); - reg &= ~((1 << 16) | (1 << 24) | (1 << 28)); - pci_io_write_config32(d0f1, 0x94, reg); - - reg = pci_io_read_config32(d0f1, 0x8c); - reg &= ~((1 << 13) | (1 << 14) | (1 << 24) | (1 << 25)); - reg |= 1 << 13; - pci_io_write_config32(d0f1, 0x8c, reg); - - reg = pci_io_read_config32(d0f1, 0xcc); - reg |= 1 << 24; - pci_io_write_config32(d0f1, 0xcc, reg); - - reg = nbmc_read_index(nb_dev, 0x7a); - reg &= ~0x3f; - reg |= 1 << 2; - reg &= ~(1 << 6); - set_htiu_enable_bits(nb_dev, 0x05, 1 << 11, 1 << 11); - nbmc_write_index(nb_dev, 0x7a, reg); - /* Powering Down efuse and strap block clocks after boot-up. GFX Mode. */ - reg = pci_io_read_config32(d0f1, 0xcc); - reg &= ~(1 << 23); - reg |= 1 << 24; - pci_io_write_config32(d0f1, 0xcc, reg); - - /* Programming NB CLK table. */ - byte = pci_io_read_config8(d0f1, 0xe0); - byte |= 0x01; - pci_io_write_config8(d0f1, 0xe0, byte); - -#if 0 - /* Powerdown reference clock to graphics core PLL in northbridge only mode */ - reg = pci_io_read_config32(d0f1, 0x8c); - reg |= 1 << 21; - pci_io_write_config32(d0f1, 0x8c, reg); - - /* Powering Down efuse and strap block clocks after boot-up. NB Only Mode. */ - reg = pci_io_read_config32(d0f1, 0xcc); - reg |= (1 << 23) | (1 << 24); - pci_io_write_config32(d0f1, 0xcc, reg); - - /* Powerdown clock to memory controller in northbridge only mode */ - byte = pci_io_read_config8(d0f1, 0xe4); - byte |= 1 << 0; - pci_io_write_config8(d0f1, 0xe4, reg); - - /* CLKCFG:0xE8 Bit[17] = 0x1 Powerdown clock to IOC GFX block in no external graphics mode */ - /* TODO: */ -#endif - - reg = pci_read_config32(nb_dev, 0x4c); - reg &= ~(1 << 0); - pci_write_config32(nb_dev, 0x4c, reg); - - set_htiu_enable_bits(nb_dev, 0x05, 7 << 8, 7 << 8); -} - -static u32 get_vid_did(struct device *dev) -{ - return pci_read_config32(dev, 0); -} - -static void rs780_nb_pci_table(struct device *nb_dev) -{ /* NBPOR_InitPOR function. */ - u8 temp8; - u16 temp16; - u32 temp32; - - /* Program NB PCI table. */ - temp16 = pci_read_config16(nb_dev, 0x04); - printk(BIOS_DEBUG, "NB_PCI_REG04 = %x.\n", temp16); - temp32 = pci_read_config32(nb_dev, 0x84); - printk(BIOS_DEBUG, "NB_PCI_REG84 = %x.\n", temp32); - - pci_write_config8(nb_dev, 0x4c, 0x42); - - temp8 = pci_read_config8(nb_dev, 0x4e); - temp8 |= 0x05; - pci_write_config8(nb_dev, 0x4e, temp8); - - temp32 = pci_read_config32(nb_dev, 0x4c); - printk(BIOS_DEBUG, "NB_PCI_REG4C = %x.\n", temp32); - - /* set temporary NB TOM to 0x40000000. */ - rs780_set_tom(nb_dev); - - /* Program NB HTIU table. */ -#if 0 - set_htiu_enable_bits(nb_dev, 0x05, 1<<10 | 1<<9, 1<<10|1<<9); - set_htiu_enable_bits(nb_dev, 0x06, 1, 0x4203a202); - set_htiu_enable_bits(nb_dev, 0x07, 1<<1 | 1<<2, 0x8001); - set_htiu_enable_bits(nb_dev, 0x15, 0, 1<<31 | 1<<30 | 1<<27); - set_htiu_enable_bits(nb_dev, 0x1c, 0, 0xfffe0000); - set_htiu_enable_bits(nb_dev, 0x4b, 1<<11, 1<<11); - set_htiu_enable_bits(nb_dev, 0x0c, 0x3f, 1 | 1<<3); - set_htiu_enable_bits(nb_dev, 0x17, 1<<1 | 1<<27, 1<<1); - set_htiu_enable_bits(nb_dev, 0x17, 0, 1<<30); - set_htiu_enable_bits(nb_dev, 0x19, 0xfffff+(1<<31), 0x186a0+(1<<31)); - set_htiu_enable_bits(nb_dev, 0x16, 0x3f<<10, 0x7<<10); - set_htiu_enable_bits(nb_dev, 0x23, 0, 1<<28); - - /* Program NB MISC table. */ - set_nbmisc_enable_bits(nb_dev, 0x0b, 0xffff, 0x00000180); - set_nbmisc_enable_bits(nb_dev, 0x00, 0xffff, 0x00000106); - set_nbmisc_enable_bits(nb_dev, 0x51, 0xffffffff, 0x00100100); - set_nbmisc_enable_bits(nb_dev, 0x53, 0xffffffff, 0x00100100); - set_nbmisc_enable_bits(nb_dev, 0x55, 0xffffffff, 0x00100100); - set_nbmisc_enable_bits(nb_dev, 0x57, 0xffffffff, 0x00100100); - set_nbmisc_enable_bits(nb_dev, 0x59, 0xffffffff, 0x00100100); - set_nbmisc_enable_bits(nb_dev, 0x5b, 0xffffffff, 0x00100100); - set_nbmisc_enable_bits(nb_dev, 0x5d, 0xffffffff, 0x00100100); - set_nbmisc_enable_bits(nb_dev, 0x5f, 0xffffffff, 0x00100100); - set_nbmisc_enable_bits(nb_dev, 0x20, 1<<1, 0); - set_nbmisc_enable_bits(nb_dev, 0x37, 1<<11|1<<12|1<<13|1<<26, 0); - set_nbmisc_enable_bits(nb_dev, 0x68, 1<<5|1<<6, 1<<5); - set_nbmisc_enable_bits(nb_dev, 0x6b, 1<<22, 1<<10); - set_nbmisc_enable_bits(nb_dev, 0x67, 1<<26, 1<<14|1<<10); - set_nbmisc_enable_bits(nb_dev, 0x24, 1<<28|1<<26|1<<25|1<<16, 1<<29|1<<25); - set_nbmisc_enable_bits(nb_dev, 0x38, 1<<24|1<<25, 1<<24); - set_nbmisc_enable_bits(nb_dev, 0x36, 1<<29, 1<<29|1<<28); - set_nbmisc_enable_bits(nb_dev, 0x0c, 0, 1<<13); - set_nbmisc_enable_bits(nb_dev, 0x34, 1<<22, 1<<10); - set_nbmisc_enable_bits(nb_dev, 0x39, 1<<10, 1<<30); - set_nbmisc_enable_bits(nb_dev, 0x22, 1<<3, 0); - set_nbmisc_enable_bits(nb_dev, 0x68, 1<<19, 0); - set_nbmisc_enable_bits(nb_dev, 0x24, 1<<16|1<<17, 1<<17); - set_nbmisc_enable_bits(nb_dev, 0x6a, 1<<22|1<<23, 1<<17|1<<23); - set_nbmisc_enable_bits(nb_dev, 0x35, 1<<21|1<<22, 1<<22); - set_nbmisc_enable_bits(nb_dev, 0x01, 0xffffffff, 0x48); - - /* the last two step. */ - set_nbmisc_enable_bits(nb_dev, 0x01, 1<<8, 1<<8); - set_htiu_enable_bits(nb_dev, 0x2d, 1<<6|1<<4, 1<<6|1<<4); -#endif -} - -static void rs780_nb_gfx_dev_table(struct device *nb_dev, struct device *dev) -{ - /* NB_InitGFXStraps */ - u32 MMIOBase, apc04, apc18, apc24, romstrap2; - volatile u32 *strap; - - /* Choose a base address that is unused and routed to the RS780. */ - MMIOBase = 0xFFB00000; - - /* 1E: NB_BIF_SPARE */ - set_nbmisc_enable_bits(nb_dev, 0x1e, 0xffffffff, 1<<1 | 1<<4 | 1<<6 | 1<<7); - /* Set a temporary Bus number. */ - apc18 = pci_read_config32(dev, 0x18); - pci_write_config32(dev, 0x18, 0x010100); - /* Set MMIO window for AGP target(graphics controller). */ - apc24 = pci_read_config32(dev, 0x24); - pci_write_config32(dev, 0x24, (MMIOBase>>16)+((MMIOBase+0x20000)&0xffff0000)); - /* Enable memory access. */ - apc04 = pci_read_config32(dev, 0x04); - pci_write_config8(dev, 0x04, 0x02); - - /* Program Straps. */ - romstrap2 = 1 << 26; // enables audio function -#if CONFIG(GFXUMA) - // bits 7-9: aperture size - // 0-7: 128mb, 256mb, 64mb, 32mb, 512mb, 1g, 2g, 4g - if (uma_memory_size == 0x02000000) romstrap2 |= 3 << 7; - if (uma_memory_size == 0x04000000) romstrap2 |= 2 << 7; - if (uma_memory_size == 0x08000000) romstrap2 |= 0 << 7; - if (uma_memory_size == 0x10000000) romstrap2 |= 1 << 7; - if (uma_memory_size == 0x20000000) romstrap2 |= 4 << 7; - if (uma_memory_size == 0x40000000) romstrap2 |= 5 << 7; - if (uma_memory_size == 0x80000000) romstrap2 |= 6 << 7; -#endif - strap = (volatile u32 *)(MMIOBase + 0x15020); - *strap = romstrap2; - strap = (volatile u32 *)(MMIOBase + 0x15000); - *strap = 0x2c006300; - strap = (volatile u32 *)(MMIOBase + 0x15010); - *strap = 0x03015330; - strap = (volatile u32 *)(MMIOBase + 0x15020); - *strap = romstrap2 | 0x00000040; - strap = (volatile u32 *)(MMIOBase + 0x15030); - *strap = 0x00001002; - strap = (volatile u32 *)(MMIOBase + 0x15040); - *strap = 0x00000000; - strap = (volatile u32 *)(MMIOBase + 0x15050); - *strap = 0x00000000; - strap = (volatile u32 *)(MMIOBase + 0x15220); - *strap = 0x03c03800; - strap = (volatile u32 *)(MMIOBase + 0x15060); - *strap = 0x00000000; - - /* BIF switches into normal functional mode. */ - set_nbmisc_enable_bits(nb_dev, 0x1e, 1<<4 | 1<<5, 1<<5); - - /* NB Revision is A12 or newer */ - if (get_nb_rev(nb_dev) >= REV_RS780_A12) - set_nbmisc_enable_bits(nb_dev, 0x1e, 1<<9, 1<<9); - - /* Restore APC04, APC18, APC24. */ - pci_write_config32(dev, 0x04, apc04); - pci_write_config32(dev, 0x18, apc18); - pci_write_config32(dev, 0x24, apc24); - - printk(BIOS_INFO, "GC is accessible from now on.\n"); -} - -/*********************************************** -* 0:00.0 NBCFG : -* 0:00.1 CLK : bit 0 of nb_cfg 0x4c : 0 - disable, default -* 0:01.0 P2P Internal: -* 0:02.0 P2P : bit 2 of nbmiscind 0x0c : 0 - enable, default + 32 * 2 -* 0:03.0 P2P : bit 3 of nbmiscind 0x0c : 0 - enable, default + 32 * 2 -* 0:04.0 P2P : bit 4 of nbmiscind 0x0c : 0 - enable, default + 32 * 2 -* 0:05.0 P2P : bit 5 of nbmiscind 0x0c : 0 - enable, default + 32 * 2 -* 0:06.0 P2P : bit 6 of nbmiscind 0x0c : 0 - enable, default + 32 * 2 -* 0:07.0 P2P : bit 7 of nbmiscind 0x0c : 0 - enable, default + 32 * 2 -* 0:08.0 NB2SB : bit 6 of nbmiscind 0x00 : 0 - disable, default + 32 * 1 -* case 0 will be called twice, one is by CPU in hypertransport.c line458, -* the other is by rs780. -***********************************************/ -void rs780_enable(struct device *dev) -{ - struct device *nb_dev = NULL, *sb_dev = NULL; - int dev_ind; - - printk(BIOS_INFO, "rs780_enable: dev=%p, VID_DID=0x%x\n", dev, get_vid_did(dev)); - - nb_dev = pcidev_on_root(0, 0); - if (!nb_dev) { - die("rs780_enable: CAN NOT FIND RS780 DEVICE, HALT!\n"); - /* NOT REACHED */ - } - - /* sb_dev (dev 8) is a bridge that links to southbridge. */ - sb_dev = pcidev_on_root(8, 0); - if (!sb_dev) { - die("rs780_enable: CAN NOT FIND SB bridge, HALT!\n"); - /* NOT REACHED */ - } - - dev_ind = dev->path.pci.devfn >> 3; - switch (dev_ind) { - case 0: /* bus0, dev0, fun0; */ - printk(BIOS_INFO, "Bus-0, Dev-0, Fun-0.\n"); - enable_pcie_bar3(nb_dev); /* PCIEMiscInit */ - config_gpp_core(nb_dev, sb_dev); - rs780_gpp_sb_init(nb_dev, sb_dev, 8); - /* 5.10.8.4. set SB payload size: 64byte */ - set_pcie_enable_bits(nb_dev, 0x10 | PCIE_CORE_INDEX_GPPSB, 3 << 11, 2 << 11); - - /* Bus0Dev0Fun1Clock control init, we have to do it here, for dev0 Fun1 doesn't have a vendor or device ID */ - rs780_config_misc_clk(nb_dev); - - rs780_nb_pci_table(nb_dev); - break; - - case 1: /* bus0, dev1, APC. */ - printk(BIOS_INFO, "Bus-0, Dev-1, Fun-0.\n"); - rs780_nb_gfx_dev_table(nb_dev, dev); - break; - case 2: /* bus0, dev2,3, two GFX */ - case 3: - printk(BIOS_INFO, "Bus-0, Dev-2,3, Fun-0. enable=%d\n", dev->enabled); - set_nbmisc_enable_bits(nb_dev, 0x0c, 1 << dev_ind, - (dev->enabled ? 0 : 1) << dev_ind); - if (dev->enabled) - rs780_gfx_init(nb_dev, dev, dev_ind); - break; - case 4: /* bus0, dev4-7, four GPPSB */ - case 5: - case 6: - case 7: - printk(BIOS_INFO, "Bus-0, Dev-4,5,6,7, Fun-0. enable=%d\n", - dev->enabled); - set_nbmisc_enable_bits(nb_dev, 0x0c, 1 << dev_ind, - (dev->enabled ? 0 : 1) << dev_ind); - if (dev->enabled) - rs780_gpp_sb_init(nb_dev, dev, dev_ind); - break; - case 8: /* bus0, dev8, SB */ - printk(BIOS_INFO, "Bus-0, Dev-8, Fun-0. enable=%d\n", dev->enabled); - set_nbmisc_enable_bits(nb_dev, 0x00, 1 << 6, - (dev->enabled ? 1 : 0) << 6); - if (dev->enabled) - rs780_gpp_sb_init(nb_dev, dev, dev_ind); - break; - case 9: /* bus 0, dev 9,10, GPP */ - case 10: - printk(BIOS_INFO, "Bus-0, Dev-9, 10, Fun-0. enable=%d\n", - dev->enabled); - set_nbmisc_enable_bits(nb_dev, 0x0c, 1 << (7 + dev_ind), - (dev->enabled ? 0 : 1) << (7 + dev_ind)); - if (dev->enabled) - rs780_gpp_sb_init(nb_dev, dev, dev_ind); - - if (dev_ind == 10) { - disable_pcie_bar3(nb_dev); - pcie_hide_unused_ports(nb_dev); - } - break; - default: - printk(BIOS_DEBUG, "unknown dev: %s\n", dev_path(dev)); - } -} - -unsigned long acpi_fill_mcfg(unsigned long current) -{ - /* FIXME - * Leave table blank until proper contents - * are determined. - */ - return current; -} - -struct chip_operations southbridge_amd_rs780_ops = { - CHIP_NAME("ATI RS780") - .enable_dev = rs780_enable, -}; diff --git a/src/southbridge/amd/rs780/rs780.h b/src/southbridge/amd/rs780/rs780.h deleted file mode 100644 index 3a9dbeee25..0000000000 --- a/src/southbridge/amd/rs780/rs780.h +++ /dev/null @@ -1,227 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2010 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef __RS780_H__ -#define __RS780_H__ - -#include -#include "chip.h" -#include "rev.h" - -#define NBMISC_INDEX 0x60 -#define NBHTIU_INDEX 0x94 -#define NBMC_INDEX 0xE8 -#define NBPCIE_INDEX 0xE0 -#define EXT_CONF_BASE_ADDRESS 0xE0000000 -#define TEMP_MMIO_BASE_ADDRESS 0xC0000000 - -#define get_nb_rev(dev) pci_read_config8((dev), 0x89) - -typedef struct __PCIE_CFG__ { - u16 Config; - u8 ResetReleaseDelay; - u8 Gfx0Width; - u8 Gfx1Width; - u8 GfxPayload; - u8 GppPayload; - u16 PortDetect; - u8 PortHp; /* hot plug */ - u16 DbgConfig; - u32 DbgConfig2; - u8 GfxLx; - u8 GppLx; - u8 NBSBLx; - u8 PortSlotInit; - u8 Gfx0Pwr; - u8 Gfx1Pwr; - u8 GppPwr; -} PCIE_CFG; - -/* The Integrated Info Table */ -#define USHORT u16 -#define UCHAR u8 -#define ULONG u32 - -typedef struct _ATOM_COMMON_TABLE_HEADER -{ - USHORT usStructureSize; - UCHAR ucTableFormatRevision; - UCHAR ucTableContentRevision; -}ATOM_COMMON_TABLE_HEADER; - -typedef struct _ATOM_INTEGRATED_SYSTEM_INFO_V2 -{ - ATOM_COMMON_TABLE_HEADER sHeader; - ULONG ulBootUpEngineClock; //in 10kHz unit - ULONG ulReserved1[2]; //must be 0x0 for the reserved - ULONG ulBootUpUMAClock; //in 10kHz unit - ULONG ulBootUpSidePortClock; //in 10kHz unit - ULONG ulMinSidePortClock; //in 10kHz unit - ULONG ulReserved2[6]; //must be 0x0 for the reserved - ULONG ulSystemConfig; -//[0]=1: PowerExpress mode -// =0 Non-PowerExpress mode; -//[1]=1: system boots up at AMD overdriven state or user customized mode. In this case, driver will disable other power state in VBIOS table. -// =0: system boots up at driver control state. Power state depends on VBIOS PP table. -//[2]=1: PWM method is used on NB voltage control. -// =0: GPIO method is used. -//[3]=1: Only one power state(Performance) will be supported. -// =0: Number of power states supported is from VBIOS PP table. -//[4]=1: CLMC is supported and enabled on current system. -// =0: CLMC is not supported or enabled on current system. SBIOS need to support HT link/freq change through ATIF interface. -//[5]=1: Enable CDLW for all driver control power states. Max HT width is from SBIOS, while Min HT width is determined by display requirement. -// =0: CDLW is disabled. If CLMC is enabled case, Min HT width will be set equal to Max HT width. If CLMC disabled case, Max HT width will be applied. -//[6]=1: High Voltage requested for all power states. In this case, voltage will be forced at 1.1v and VBIOS PP table voltage drop/throttling request will be ignored. -// =0: Voltage settings is determined by VBIOS PP table. -//[7]=1: Enable CLMC Hybrid Mode. CDLD and CILR will be disabled in this case and we're using legacy C1E. This is workaround for CPU(Griffin) performance issue. -// =0: Enable regular CLMC mode, CDLD and CILR will be enabled. -//[8]=1: CDLF is supported and enabled by fuse //CHP 914 -// =0: CDLF is not supported and not enabled by fuses - ULONG ulBootUpReqDisplayVector; - ULONG ulOtherDisplayMisc; - ULONG ulDDISlot1Config; - ULONG ulDDISlot2Config; - UCHAR ucMemoryType; //[3:0]=1:DDR1;=2:DDR2;=3:DDR3.[7:4] is reserved - UCHAR ucUMAChannelNumber; - UCHAR ucDockingPinBit; - UCHAR ucDockingPinPolarity; - ULONG ulDockingPinCFGInfo; - ULONG ulCPUCapInfo; - USHORT usNumberOfCyclesInPeriod; //usNumberOfCyclesInPeriod[15] = 0 - invert waveform - // 1 - non inverted waveform - USHORT usMaxNBVoltage; - USHORT usMinNBVoltage; - USHORT usBootUpNBVoltage; - ULONG ulHTLinkFreq; //in 10Khz - USHORT usMinHTLinkWidth; // if no CLMC, usMinHTLinkWidth should be equal to usMaxHTLinkWidth?? - USHORT usMaxHTLinkWidth; - USHORT usUMASyncStartDelay; // will be same as usK8SyncStartDelay on RS690 - USHORT usUMADataReturnTime; // will be same as usK8DataReturnTime on RS690 - USHORT usLinkStatusZeroTime; - USHORT usReserved; - ULONG ulHighVoltageHTLinkFreq; // in 10Khz - ULONG ulLowVoltageHTLinkFreq; // in 10Khz - USHORT usMaxUpStreamHTLinkWidth; - USHORT usMaxDownStreamHTLinkWidth; - USHORT usMinUpStreamHTLinkWidth; - USHORT usMinDownStreamHTLinkWidth; - ULONG ulReserved3[97]; //must be 0x0 -} ATOM_INTEGRATED_SYSTEM_INFO_V2; - -/* PCIE config flags */ -#define PCIE_DUALSLOT_CONFIG (1 << 0) -#define PCIE_OVERCLOCK_ENABLE (1 << 1) -#define PCIE_GPP_CLK_GATING (1 << 2) -#define PCIE_ENABLE_STATIC_DEV_REMAP (1 << 3) -#define PCIE_OFF_UNUSED_GFX_LANES (1 << 4) -#define PCIE_OFF_UNUSED_GPP_LANES (1 << 5) -#define PCIE_DISABLE_HIDE_UNUSED_PORTS (1 << 7) -#define PCIE_GFX_CLK_GATING (1 << 11) -#define PCIE_GFX_COMPLIANCE (1 << 14) -#define PCIE_GPP_COMPLIANCE (1 << 15) - -/* -------------------- ---------------------- -* NBMISCIND - ------------------- -----------------------*/ -#define PCIE_LINK_CFG 0x8 -#define PCIE_NBCFG_REG7 0x37 -#define STRAPS_OUTPUT_MUX_7 0x67 -#define STRAPS_OUTPUT_MUX_A 0x6a - -/* -------------------- ---------------------- -* PCIEIND - ------------------- -----------------------*/ -#define PCIE_CI_CNTL 0x20 -#define PCIE_LC_LINK_WIDTH 0xa2 -#define PCIE_LC_STATE0 0xa5 -#define PCIE_VC0_RESOURCE_STATUS 0x12a /* 16bit read only */ - -#define PCIE_CORE_INDEX_GFX (0x00 << 16) /* see 5.2.2 */ -#define PCIE_CORE_INDEX_GPPSB (0x01 << 16) -#define PCIE_CORE_INDEX_GPP (0x02 << 16) -#define PCIE_CORE_INDEX_BRDCST (0x03 << 16) - -/* contents of PCIE_NBCFG_REG7 */ -#define RECONFIG_GPPSB_EN (1 << 12) -#define RECONFIG_GPPSB_GPPSB (1 << 14) -#define RECONFIG_GPPSB_LINK_CONFIG (1 << 15) -#define RECONFIG_GPPSB_ATOMIC_RESET (1 << 17) - -/* contents of PCIE_VC0_RESOURCE_STATUS */ -#define VC_NEGOTIATION_PENDING (1 << 1) - -#define LC_STATE_RECONFIG_GPPSB 0x10 - -/* ------------------------------------------------ -* Global variable -* ------------------------------------------------- */ -extern PCIE_CFG AtiPcieCfg; - -#if ENV_RAMSTAGE -/* ----------------- export functions ----------------- */ -u32 nbmisc_read_index(struct device * nb_dev, u32 index); -void nbmisc_write_index(struct device * nb_dev, u32 index, u32 data); -u32 nbpcie_p_read_index(struct device * dev, u32 index); -void nbpcie_p_write_index(struct device * dev, u32 index, u32 data); -u32 nbpcie_ind_read_index(struct device * nb_dev, u32 index); -void nbpcie_ind_write_index(struct device * nb_dev, u32 index, u32 data); -u32 htiu_read_index(struct device * nb_dev, u32 index); -void htiu_write_index(struct device * nb_dev, u32 index, u32 data); -u32 nbmc_read_index(struct device * nb_dev, u32 index); -void nbmc_write_index(struct device * nb_dev, u32 index, u32 data); - -u32 pci_ext_read_config32(struct device *nb_dev, struct device *dev, u32 reg); -void pci_ext_write_config32(struct device *nb_dev, struct device *dev, u32 reg, u32 mask, u32 val); - -void set_nbcfg_enable_bits(struct device * nb_dev, u32 reg_pos, u32 mask, u32 val); -void set_nbcfg_enable_bits_8(struct device * nb_dev, u32 reg_pos, u8 mask, u8 val); -void set_nbmc_enable_bits(struct device * nb_dev, u32 reg_pos, u32 mask, u32 val); -void set_htiu_enable_bits(struct device * nb_dev, u32 reg_pos, u32 mask, u32 val); - -void set_nbmisc_enable_bits(struct device * nb_dev, u32 reg_pos, u32 mask, u32 val); - -void set_pcie_enable_bits(struct device *dev, u32 reg_pos, u32 mask, u32 val); -void rs780_set_tom(struct device *nb_dev); - -void ProgK8TempMmioBase(u8 in_out, u32 pcie_base_add, u32 mmio_base_add); -void enable_pcie_bar3(struct device *nb_dev); -void disable_pcie_bar3(struct device *nb_dev); - -void rs780_enable(struct device *dev); -void rs780_gpp_sb_init(struct device *nb_dev, struct device *dev, u32 port); -void rs780_gfx_init(struct device *nb_dev, struct device *dev, u32 port); -void avoid_lpc_dma_deadlock(struct device *nb_dev, struct device *sb_dev); -void config_gpp_core(struct device *nb_dev, struct device *sb_dev); -void PcieReleasePortTraining(struct device *nb_dev, struct device *dev, u32 port); -u8 PcieTrainPort(struct device *nb_dev, struct device *dev, u32 port); - -void pcie_hide_unused_ports(struct device *nb_dev); - -#endif - -u32 extractbit(u32 data, int bit_number); -u32 extractbits(u32 source, int lsb, int msb); -int cpuidFamily(void); -int is_family0Fh(void); -int is_family10h(void); - -void enable_rs780_dev8(void); -void rs780_early_setup(void); -void rs780_htinit(void); -int is_dev3_present(void); -void set_pcie_reset(void); -void set_pcie_dereset(void); - -#endif /* __RS780_H__ */ From 24284270c73ba4e35af10ea9054f084c989dff52 Mon Sep 17 00:00:00 2001 From: Arthur Heymans Date: Tue, 19 Nov 2019 17:23:12 +0100 Subject: [PATCH 0293/1242] sb/amd/sb700: Drop support MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Relocatable ramstage, postcar stage and C_ENVIRONMENT_BOOTBLOCK are now mandatory features, which platforms using this code lack. Change-Id: Iffa4f54b2d1b43b6710447e69061c6ed433bff1d Signed-off-by: Arthur Heymans Reviewed-on: https://review.coreboot.org/c/coreboot/+/36967 Reviewed-by: Kyösti Mälkki Reviewed-by: Angel Pons Reviewed-by: HAOUAS Elyes Tested-by: build bot (Jenkins) --- src/cpu/amd/family_10h-family_15h/init_cpus.c | 6 +- src/southbridge/amd/sb700/Kconfig | 68 -- src/southbridge/amd/sb700/Makefile.inc | 27 - src/southbridge/amd/sb700/acpi/ide.asl | 230 ----- src/southbridge/amd/sb700/acpi/sata.asl | 129 --- src/southbridge/amd/sb700/bootblock.c | 129 --- src/southbridge/amd/sb700/chip.h | 24 - src/southbridge/amd/sb700/early_setup.c | 854 ------------------ src/southbridge/amd/sb700/enable_usbdebug.c | 47 - src/southbridge/amd/sb700/fadt.c | 162 ---- src/southbridge/amd/sb700/hda.c | 226 ----- src/southbridge/amd/sb700/ide.c | 87 -- src/southbridge/amd/sb700/lpc.c | 292 ------ src/southbridge/amd/sb700/pci.c | 123 --- src/southbridge/amd/sb700/pmio.c | 50 - src/southbridge/amd/sb700/pmio.h | 30 - src/southbridge/amd/sb700/ramtop.c | 51 -- src/southbridge/amd/sb700/reset.c | 66 -- src/southbridge/amd/sb700/sata.c | 555 ------------ src/southbridge/amd/sb700/sb700.c | 227 ----- src/southbridge/amd/sb700/sb700.h | 83 -- src/southbridge/amd/sb700/sm.c | 542 ----------- src/southbridge/amd/sb700/smbus.c | 231 ----- src/southbridge/amd/sb700/smbus.h | 70 -- src/southbridge/amd/sb700/spi.c | 129 --- src/southbridge/amd/sb700/spi.h | 17 - src/southbridge/amd/sb700/usb.c | 257 ------ 27 files changed, 1 insertion(+), 4711 deletions(-) delete mode 100644 src/southbridge/amd/sb700/Kconfig delete mode 100644 src/southbridge/amd/sb700/Makefile.inc delete mode 100644 src/southbridge/amd/sb700/acpi/ide.asl delete mode 100644 src/southbridge/amd/sb700/acpi/sata.asl delete mode 100644 src/southbridge/amd/sb700/bootblock.c delete mode 100644 src/southbridge/amd/sb700/chip.h delete mode 100644 src/southbridge/amd/sb700/early_setup.c delete mode 100644 src/southbridge/amd/sb700/enable_usbdebug.c delete mode 100644 src/southbridge/amd/sb700/fadt.c delete mode 100644 src/southbridge/amd/sb700/hda.c delete mode 100644 src/southbridge/amd/sb700/ide.c delete mode 100644 src/southbridge/amd/sb700/lpc.c delete mode 100644 src/southbridge/amd/sb700/pci.c delete mode 100644 src/southbridge/amd/sb700/pmio.c delete mode 100644 src/southbridge/amd/sb700/pmio.h delete mode 100644 src/southbridge/amd/sb700/ramtop.c delete mode 100644 src/southbridge/amd/sb700/reset.c delete mode 100644 src/southbridge/amd/sb700/sata.c delete mode 100644 src/southbridge/amd/sb700/sb700.c delete mode 100644 src/southbridge/amd/sb700/sb700.h delete mode 100644 src/southbridge/amd/sb700/sm.c delete mode 100644 src/southbridge/amd/sb700/smbus.c delete mode 100644 src/southbridge/amd/sb700/smbus.h delete mode 100644 src/southbridge/amd/sb700/spi.c delete mode 100644 src/southbridge/amd/sb700/spi.h delete mode 100644 src/southbridge/amd/sb700/usb.c diff --git a/src/cpu/amd/family_10h-family_15h/init_cpus.c b/src/cpu/amd/family_10h-family_15h/init_cpus.c index 452f7ce3fd..89188fddd7 100644 --- a/src/cpu/amd/family_10h-family_15h/init_cpus.c +++ b/src/cpu/amd/family_10h-family_15h/init_cpus.c @@ -30,10 +30,6 @@ #include -#if CONFIG(SOUTHBRIDGE_AMD_SB700) -#include -#endif - #if CONFIG(SOUTHBRIDGE_AMD_SB800) #include #endif @@ -1045,7 +1041,7 @@ void cpuSetAMDMSR(uint8_t node_id) } } -#if CONFIG(SOUTHBRIDGE_AMD_SB700) || CONFIG(SOUTHBRIDGE_AMD_SB800) +#if CONFIG(SOUTHBRIDGE_AMD_SB800) if (revision & (AMD_DR_GT_D0 | AMD_FAM15_ALL)) { /* Set up message triggered C1E */ msr = rdmsr(MSR_INTPEND); diff --git a/src/southbridge/amd/sb700/Kconfig b/src/southbridge/amd/sb700/Kconfig deleted file mode 100644 index 58dc75a5de..0000000000 --- a/src/southbridge/amd/sb700/Kconfig +++ /dev/null @@ -1,68 +0,0 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2010 Advanced Micro Devices, Inc. -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; version 2 of the License. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## - -config SOUTHBRIDGE_AMD_SB700 - bool - -if SOUTHBRIDGE_AMD_SB700 - -config SOUTHBRIDGE_SPECIFIC_OPTIONS # dummy - def_bool y - select IOAPIC - select HAVE_USBDEBUG_OPTIONS - select SMBUS_HAS_AUX_CHANNELS - select HAVE_POWER_STATE_AFTER_FAILURE - select HAVE_POWER_STATE_PREVIOUS_AFTER_FAILURE - -config SOUTHBRIDGE_AMD_SB700_33MHZ_SPI - bool "Enable high speed SPI clock" - default n - help - When set, the SPI clock will run at 33MHz instead - of the compatibility mode 16.5MHz. Note that not - all ROMs are capable of 33MHz operation, so you - will need to verify this option is appropriate for - the ROM you are using. - -# Set for southbridge SP5100 which also uses SB700 driver -config SOUTHBRIDGE_AMD_SUBTYPE_SP5100 - bool - default n - -config BOOTBLOCK_SOUTHBRIDGE_INIT - string - default "southbridge/amd/sb700/bootblock.c" - -config SOUTHBRIDGE_AMD_SB700_SKIP_ISA_DMA_INIT - bool - default n - -config SOUTHBRIDGE_AMD_SB700_DISABLE_ISA_DMA - bool - default n - -config SOUTHBRIDGE_AMD_SB700_SATA_PORT_COUNT_BITFIELD - hex - default 0xf - -config EHCI_BAR - hex - default 0xfef00000 - -config HPET_MIN_TICKS - hex - default 0x14 - -endif # SOUTHBRIDGE_AMD_SB700 diff --git a/src/southbridge/amd/sb700/Makefile.inc b/src/southbridge/amd/sb700/Makefile.inc deleted file mode 100644 index 0a20a8c8b3..0000000000 --- a/src/southbridge/amd/sb700/Makefile.inc +++ /dev/null @@ -1,27 +0,0 @@ -ifeq ($(CONFIG_SOUTHBRIDGE_AMD_SB700),y) - -ramstage-y += sb700.c -ramstage-y += usb.c -ramstage-y += lpc.c -ramstage-y += smbus.c -ramstage-y += sm.c -ramstage-y += ide.c -ramstage-y += sata.c -ramstage-y += hda.c -ramstage-y += pci.c -ramstage-$(CONFIG_HAVE_ACPI_TABLES) += fadt.c -romstage-y += reset.c -ramstage-y += reset.c -ramstage-y += spi.c - -bootblock-y += enable_usbdebug.c -romstage-y += enable_usbdebug.c -ramstage-y += enable_usbdebug.c - -romstage-y += early_setup.c -romstage-y += smbus.c - -romstage-y += ramtop.c -ramstage-y += ramtop.c - -endif diff --git a/src/southbridge/amd/sb700/acpi/ide.asl b/src/southbridge/amd/sb700/acpi/ide.asl deleted file mode 100644 index f793a9f8f9..0000000000 --- a/src/southbridge/amd/sb700/acpi/ide.asl +++ /dev/null @@ -1,230 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2015 Timothy Pearson , Raptor Engineering - * Copyright (C) 2010 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -/* Some timing tables */ -Name(UDTT, Package(){ /* Udma timing table */ - 120, 90, 60, 45, 30, 20, 15, 0 /* UDMA modes 0 -> 6 */ -}) - -Name(MDTT, Package(){ /* MWDma timing table */ - 480, 150, 120, 0 /* Legacy DMA modes 0 -> 2 */ -}) - -Name(POTT, Package(){ /* Pio timing table */ - 600, 390, 270, 180, 120, 0 /* PIO modes 0 -> 4 */ -}) - -/* Some timing register value tables */ -Name(MDRT, Package(){ /* MWDma timing register table */ - 0x77, 0x21, 0x20, 0xFF /* Legacy DMA modes 0 -> 2 */ -}) - -Name(PORT, Package(){ - 0x99, 0x47, 0x34, 0x22, 0x20, 0x99 /* PIO modes 0 -> 4 */ -}) - -OperationRegion(ICRG, PCI_Config, 0x40, 0x20) /* ide control registers */ - Field(ICRG, AnyAcc, NoLock, Preserve) -{ - PPTS, 8, /* Primary PIO Slave Timing */ - PPTM, 8, /* Primary PIO Master Timing */ - OFFSET(0x04), PMTS, 8, /* Primary MWDMA Slave Timing */ - PMTM, 8, /* Primary MWDMA Master Timing */ - OFFSET(0x08), PPCR, 8, /* Primary PIO Control */ - OFFSET(0x0A), PPMM, 4, /* Primary PIO master Mode */ - PPSM, 4, /* Primary PIO slave Mode */ - OFFSET(0x14), PDCR, 2, /* Primary UDMA Control */ - OFFSET(0x16), PDMM, 4, /* Primary UltraDMA Mode */ - PDSM, 4, /* Primary UltraDMA Mode */ -} - -Method(GTTM, 1) /* get total time*/ -{ - Store(And(Arg0, 0x0F), Local0) /* Recovery Width */ - Increment(Local0) - Store(ShiftRight(Arg0, 4), Local1) /* Command Width */ - Increment(Local1) - Return(Multiply(30, Add(Local0, Local1))) -} - -Device(PRID) -{ - Name (_ADR, Zero) - Method(_GTM, 0, Serialized) - { - NAME(OTBF, Buffer(20) { /* out buffer */ - 0xFF, 0xFF, 0xFF, 0xFF, - 0xFF, 0xFF, 0xFF, 0xFF, - 0xFF, 0xFF, 0xFF, 0xFF, - 0xFF, 0xFF, 0xFF, 0xFF, 0x00, 0x00, 0x00, 0x00 - }) - - CreateDwordField(OTBF, 0, PSD0) /* PIO spd0 */ - CreateDwordField(OTBF, 4, DSD0) /* DMA spd0 */ - CreateDwordField(OTBF, 8, PSD1) /* PIO spd1 */ - CreateDwordField(OTBF, 12, DSD1) /* DMA spd1 */ - CreateDwordField(OTBF, 16, BFFG) /* buffer flags */ - - /* Just return if the channel is disabled */ - If(And(PPCR, 0x01)) { /* primary PIO control */ - Return(OTBF) - } - - /* Always tell them independent timing available and IOChannelReady used on both drives */ - Or(BFFG, 0x1A, BFFG) - - Store(GTTM(PPTM), PSD0) /* save total time of primary PIO master timming to PIO spd0 */ - Store(GTTM(PPTS), PSD1) /* save total time of primary PIO slave Timing to PIO spd1 */ - - If(And(PDCR, 0x01)) { /* It's under UDMA mode */ - Or(BFFG, 0x01, BFFG) - Store(DerefOf(Index(UDTT, PDMM)), DSD0) - } - Else { - Store(GTTM(PMTM), DSD0) /* Primary MWDMA Master Timing, DmaSpd0 */ - } - - If(And(PDCR, 0x02)) { /* It's under UDMA mode */ - Or(BFFG, 0x04, BFFG) - Store(DerefOf(Index(UDTT, PDSM)), DSD1) - } - Else { - Store(GTTM(PMTS), DSD1) /* Primary MWDMA Slave Timing, DmaSpd0 */ - } - - Return(OTBF) /* out buffer */ - } /* End Method(_GTM) */ - - Method(_STM, 3, Serialized) - { - NAME(INBF, Buffer(20) { /* in buffer */ - 0xFF, 0xFF, 0xFF, 0xFF, - 0xFF, 0xFF, 0xFF, 0xFF, - 0xFF, 0xFF, 0xFF, 0xFF, - 0xFF, 0xFF, 0xFF, 0xFF, 0x00, 0x00, 0x00, 0x00 - }) - - CreateDwordField(INBF, 0, PSD0) /* PIO spd0 */ - CreateDwordField(INBF, 4, DSD0) /* PIO spd0 */ - CreateDwordField(INBF, 8, PSD1) /* PIO spd1 */ - CreateDwordField(INBF, 12, DSD1) /* DMA spd1 */ - CreateDwordField(INBF, 16, BFFG) /*buffer flag */ - - Store(Match(POTT, MLE, PSD0, MTR, 0, 0), Local0) - Divide(Local0, 5, PPMM,) /* Primary PIO master Mode */ - Store(Match(POTT, MLE, PSD1, MTR, 0, 0), Local1) - Divide(Local1, 5, PPSM,) /* Primary PIO slave Mode */ - - Store(DerefOf(Index(PORT, Local0)), PPTM) /* Primary PIO Master Timing */ - Store(DerefOf(Index(PORT, Local1)), PPTS) /* Primary PIO Slave Timing */ - - If(And(BFFG, 0x01)) { /* Drive 0 is under UDMA mode */ - Store(Match(UDTT, MLE, DSD0, MTR, 0, 0), Local0) - Divide(Local0, 7, PDMM,) - Or(PDCR, 0x01, PDCR) - } - Else { - If(LNotEqual(DSD0, 0xFFFFFFFF)) { - Store(Match(MDTT, MLE, DSD0, MTR, 0, 0), Local0) - Store(DerefOf(Index(MDRT, Local0)), PMTM) - } - } - - If(And(BFFG, 0x04)) { /* Drive 1 is under UDMA mode */ - Store(Match(UDTT, MLE, DSD1, MTR, 0, 0), Local0) - Divide(Local0, 7, PDSM,) - Or(PDCR, 0x02, PDCR) - } - Else { - If(LNotEqual(DSD1, 0xFFFFFFFF)) { - Store(Match(MDTT, MLE, DSD1, MTR, 0, 0), Local0) - Store(DerefOf(Index(MDRT, Local0)), PMTS) - } - } - /* Return(INBF) */ - } /*End Method(_STM) */ - Device(MST) - { - Name(_ADR, 0) - Method(_GTF, 0, Serialized) { - Name(CMBF, Buffer(21) { - 0x03, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xEF, - 0x03, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xEF, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xF5 - }) - CreateByteField(CMBF, 1, POMD) - CreateByteField(CMBF, 8, DMMD) - CreateByteField(CMBF, 5, CMDA) - CreateByteField(CMBF, 12, CMDB) - CreateByteField(CMBF, 19, CMDC) - - Store(0xA0, CMDA) - Store(0xA0, CMDB) - Store(0xA0, CMDC) - - Or(PPMM, 0x08, POMD) - - If(And(PDCR, 0x01)) { - Or(PDMM, 0x40, DMMD) - } - Else { - Store(Match - (MDTT, MLE, GTTM(PMTM), - MTR, 0, 0), Local0) - If(LLess(Local0, 3)) { - Or(0x20, Local0, DMMD) - } - } - Return(CMBF) - } - } /* End Device(MST) */ - - Device(SLAV) - { - Name(_ADR, 1) - Method(_GTF, 0, Serialized) { - Name(CMBF, Buffer(21) { - 0x03, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xEF, - 0x03, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xEF, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xF5 - }) - CreateByteField(CMBF, 1, POMD) - CreateByteField(CMBF, 8, DMMD) - CreateByteField(CMBF, 5, CMDA) - CreateByteField(CMBF, 12, CMDB) - CreateByteField(CMBF, 19, CMDC) - - Store(0xB0, CMDA) - Store(0xB0, CMDB) - Store(0xB0, CMDC) - - Or(PPSM, 0x08, POMD) - - If(And(PDCR, 0x02)) { - Or(PDSM, 0x40, DMMD) - } - Else { - Store(Match - (MDTT, MLE, GTTM(PMTS), - MTR, 0, 0), Local0) - If(LLess(Local0, 3)) { - Or(0x20, Local0, DMMD) - } - } - Return(CMBF) - } - } /* End Device(SLAV) */ -} diff --git a/src/southbridge/amd/sb700/acpi/sata.asl b/src/southbridge/amd/sb700/acpi/sata.asl deleted file mode 100644 index d827b69ea9..0000000000 --- a/src/southbridge/amd/sb700/acpi/sata.asl +++ /dev/null @@ -1,129 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2010 Advanced Micro Devices, Inc. - * Copyright (C) 2015 Timothy Pearson , Raptor Engineering - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -Name(STTM, Buffer(20) { - 0x78, 0x00, 0x00, 0x00, 0x0f, 0x00, 0x00, 0x00, - 0x78, 0x00, 0x00, 0x00, 0x0f, 0x00, 0x00, 0x00, - 0x1f, 0x00, 0x00, 0x00 -}) - -/* Start by clearing the PhyRdyChg bits */ -Method(_INI) { - \_GPE._L1F() -} - -Device(PMRY) -{ - Name(_ADR, 0) - Method(_GTM, 0x0, NotSerialized) { - Return(STTM) - } - Method(_STM, 0x3, NotSerialized) {} - - Device(PMST) { - Name(_ADR, 0) - Method(_STA,0) { - if (LGreater(P0IS,0)) { - return (0x0F) /* sata is visible */ - } else { - return (0x00) /* sata is missing */ - } - } - }/* end of PMST */ - - Device(PSLA) - { - Name(_ADR, 1) - Method(_STA,0) { - if (LGreater(P1IS,0)) { - return (0x0F) /* sata is visible */ - } else { - return (0x00) /* sata is missing */ - } - } - } /* end of PSLA */ -} /* end of PMRY */ - - -Device(SEDY) -{ - Name(_ADR, 1) /* IDE Scondary Channel */ - Method(_GTM, 0x0, NotSerialized) { - Return(STTM) - } - Method(_STM, 0x3, NotSerialized) {} - - Device(SMST) - { - Name(_ADR, 0) - Method(_STA,0) { - if (LGreater(P2IS,0)) { - return (0x0F) /* sata is visible */ - } else { - return (0x00) /* sata is missing */ - } - } - } /* end of SMST */ - - Device(SSLA) - { - Name(_ADR, 1) - Method(_STA,0) { - if (LGreater(P3IS,0)) { - return (0x0F) /* sata is visible */ - } else { - return (0x00) /* sata is missing */ - } - } - } /* end of SSLA */ -} /* end of SEDY */ - -/* SATA Hot Plug Support */ -Scope(\_GPE) { - Method(_L1F,0x0,NotSerialized) { - if (\_SB.P0PR) { - if (LGreater(\_SB.P0IS,0)) { - sleep(32) - } - Notify(\_SB.PCI0.SAT0.PMRY.PMST, 0x01) /* NOTIFY_DEVICE_CHECK */ - store(one, \_SB.P0PR) - } - - if (\_SB.P1PR) { - if (LGreater(\_SB.P1IS,0)) { - sleep(32) - } - Notify(\_SB.PCI0.SAT0.PMRY.PSLA, 0x01) /* NOTIFY_DEVICE_CHECK */ - store(one, \_SB.P1PR) - } - - if (\_SB.P2PR) { - if (LGreater(\_SB.P2IS,0)) { - sleep(32) - } - Notify(\_SB.PCI0.SAT0.SEDY.SMST, 0x01) /* NOTIFY_DEVICE_CHECK */ - store(one, \_SB.P2PR) - } - - if (\_SB.P3PR) { - if (LGreater(\_SB.P3IS,0)) { - sleep(32) - } - Notify(\_SB.PCI0.SAT0.SEDY.SSLA, 0x01) /* NOTIFY_DEVICE_CHECK */ - store(one, \_SB.P3PR) - } - } -} diff --git a/src/southbridge/amd/sb700/bootblock.c b/src/southbridge/amd/sb700/bootblock.c deleted file mode 100644 index 222b33df72..0000000000 --- a/src/southbridge/amd/sb700/bootblock.c +++ /dev/null @@ -1,129 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2015 Timothy Pearson , Raptor Engineering - * Copyright (C) 2010 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include - -#define IO_MEM_PORT_DECODE_ENABLE_5 0x48 -#define IO_MEM_PORT_DECODE_ENABLE_6 0x4a -#define SPI_BASE_ADDRESS 0xa0 - -#define SPI_CONTROL_1 0xc -#define TEMPORARY_SPI_BASE_ADDRESS 0xfec10000 - -/* - * Enable 4MB (LPC) ROM access at 0xFFC00000 - 0xFFFFFFFF. - * - * Hardware should enable LPC ROM by pin straps. This function does not - * handle the theoretically possible PCI ROM, FWH, or SPI ROM configurations. - * - * The SB700 power-on default is to map 512K ROM space. - * - * Details: AMD SB700/710/750 BIOS Developer's Guide (BDG), Rev. 1.00, - * PN 43366_sb7xx_bdg_pub_1.00, June 2009, section 3.1, page 14. - */ -static void sb700_enable_rom(void) -{ - u8 reg8; - u32 dword; - pci_devfn_t dev; - - dev = PCI_DEV(0, 0x14, 3); - - reg8 = pci_io_read_config8(dev, IO_MEM_PORT_DECODE_ENABLE_5); - if (CONFIG(SPI_FLASH)) - /* Disable decode of variable LPC ROM address ranges 1 and 2. */ - reg8 &= ~((1 << 3) | (1 << 4)); - else - /* Decode variable LPC ROM address ranges 1 and 2. */ - reg8 |= (1 << 3) | (1 << 4); - pci_io_write_config8(dev, IO_MEM_PORT_DECODE_ENABLE_5, reg8); - - /* LPC ROM address range 1: */ - /* Enable LPC ROM range mirroring start at 0x000e(0000). */ - pci_io_write_config16(dev, 0x68, 0x000e); - /* Enable LPC ROM range mirroring end at 0x000f(ffff). */ - pci_io_write_config16(dev, 0x6a, 0x000f); - - /* LPC ROM address range 2: */ - /* - * Enable LPC ROM range start at: - * 0xfff8(0000): 512KB - * 0xfff0(0000): 1MB - * 0xffe0(0000): 2MB - * 0xffc0(0000): 4MB - * 0xff80(0000): 8MB - */ - pci_io_write_config16(dev, 0x6c, 0x10000 - (CONFIG_COREBOOT_ROMSIZE_KB >> 6)); - /* Enable LPC ROM range end at 0xffff(ffff). */ - pci_io_write_config16(dev, 0x6e, 0xffff); - - /* SB700 LPC Bridge 0x48. - * Turn on all LPC IO Port decode enables - */ - pci_io_write_config32(dev, 0x44, 0xffffffff); - - /* SB700 LPC Bridge 0x48. - * BIT0: Port Enable for SuperIO 0x2E-0x2F - * BIT1: Port Enable for SuperIO 0x4E-0x4F - * BIT6: Port Enable for RTC IO 0x70-0x73 - */ - reg8 = pci_io_read_config8(dev, IO_MEM_PORT_DECODE_ENABLE_5); - reg8 |= (1 << 0) | (1 << 1) | (1 << 6); - pci_io_write_config8(dev, IO_MEM_PORT_DECODE_ENABLE_5, reg8); - - /* SB700 LPC Bridge 0x4a. - * BIT5: Port Enable for Port 0x80 - */ - reg8 = pci_io_read_config8(dev, IO_MEM_PORT_DECODE_ENABLE_6); - reg8 |= (1 << 5); - pci_io_write_config8(dev, IO_MEM_PORT_DECODE_ENABLE_6, reg8); -} - -static void sb700_configure_rom(void) -{ - pci_devfn_t dev; - uint32_t dword; - - dev = PCI_DEV(0, 0x14, 3); - - if (CONFIG(SOUTHBRIDGE_AMD_SB700_33MHZ_SPI)) { - uint32_t prev_spi_cfg; - volatile uint32_t *spi_mmio; - - /* Temporarily set up SPI access to change SPI speed */ - prev_spi_cfg = dword = pci_io_read_config32(dev, SPI_BASE_ADDRESS); - dword &= ~(0x7ffffff << 5); /* SPI_BaseAddr */ - dword |= TEMPORARY_SPI_BASE_ADDRESS & (0x7ffffff << 5); - dword |= (0x1 << 1); /* SpiRomEnable = 1 */ - pci_io_write_config32(dev, SPI_BASE_ADDRESS, dword); - - spi_mmio = (void *)(TEMPORARY_SPI_BASE_ADDRESS + SPI_CONTROL_1); - dword = *spi_mmio; - dword &= ~(0x3 << 12); /* NormSpeed = 0x1 */ - dword |= (0x1 << 12); - *spi_mmio = dword; - - /* Restore previous SPI access */ - pci_io_write_config32(dev, SPI_BASE_ADDRESS, prev_spi_cfg); - } -} - -static void bootblock_southbridge_init(void) -{ - sb700_enable_rom(); - sb700_configure_rom(); -} diff --git a/src/southbridge/amd/sb700/chip.h b/src/southbridge/amd/sb700/chip.h deleted file mode 100644 index fe3289d913..0000000000 --- a/src/southbridge/amd/sb700/chip.h +++ /dev/null @@ -1,24 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2010 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef SB700_CHIP_H -#define SB700_CHIP_H - -struct southbridge_amd_sb700_config -{ - u32 boot_switch_sata_ide : 1; -}; - -#endif /* SB700_CHIP_H */ diff --git a/src/southbridge/amd/sb700/early_setup.c b/src/southbridge/amd/sb700/early_setup.c deleted file mode 100644 index 1c248835ef..0000000000 --- a/src/southbridge/amd/sb700/early_setup.c +++ /dev/null @@ -1,854 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2010 Advanced Micro Devices, Inc. - * Copyright (C) 2015 - 2016 Raptor Engineering, LLC - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef _SB700_EARLY_SETUP_C_ -#define _SB700_EARLY_SETUP_C_ - -#include -#include -#include -#include -#include -#include -#include - -#include "sb700.h" -#include "smbus.h" - -u32 get_sbdn(u32 bus); - -static void pmio_write(u8 reg, u8 value) -{ - outb(reg, PM_INDEX); - outb(value, PM_INDEX + 1); -} - -static u8 pmio_read(u8 reg) -{ - outb(reg, PM_INDEX); - return inb(PM_INDEX + 1); -} - -static void sb700_acpi_init(void) -{ - u16 word; - pmio_write(0x20, ACPI_PM_EVT_BLK & 0xFF); - pmio_write(0x21, ACPI_PM_EVT_BLK >> 8); - pmio_write(0x22, ACPI_PM1_CNT_BLK & 0xFF); - pmio_write(0x23, ACPI_PM1_CNT_BLK >> 8); - pmio_write(0x24, ACPI_PM_TMR_BLK & 0xFF); - pmio_write(0x25, ACPI_PM_TMR_BLK >> 8); - pmio_write(0x28, ACPI_GPE0_BLK & 0xFF); - pmio_write(0x29, ACPI_GPE0_BLK >> 8); - - /* CpuControl is in \_PR.CP00, 6 bytes */ - pmio_write(0x26, ACPI_CPU_CONTROL & 0xFF); - pmio_write(0x27, ACPI_CPU_CONTROL >> 8); - - pmio_write(0x2A, 0); /* AcpiSmiCmdLo */ - pmio_write(0x2B, 0); /* AcpiSmiCmdHi */ - - pmio_write(0x2C, ACPI_PMA_CNT_BLK & 0xFF); - pmio_write(0x2D, ACPI_PMA_CNT_BLK >> 8); - - pmio_write(0x0E, 1<<3 | 0<<2); /* AcpiDecodeEnable, When set, SB uses - * the contents of the PM registers at - * index 20-2B to decode ACPI I/O address. - * AcpiSmiEn & SmiCmdEn*/ - pmio_write(0x10, 1<<1 | 1<<3| 1<<5); /* RTC_En_En, TMR_En_En, GBL_EN_EN */ - word = inl(ACPI_PM1_CNT_BLK); - word |= 1; - outl(word, ACPI_PM1_CNT_BLK); /* set SCI_EN */ -} - -/* RPR 2.28: Get SB ASIC Revision. */ -static u8 set_sb700_revision(void) -{ - pci_devfn_t dev; - u8 rev_id, enable_14Mhz, byte; - u8 rev = 0; - - /* if (rev != 0) return rev; */ - - dev = pci_locate_device(PCI_ID(0x1002, 0x4385), 0); - - if (dev == PCI_DEV_INVALID) { - die("SMBUS controller not found\n"); - /* NOT REACHED */ - } - rev_id = pci_read_config8(dev, 0x08); - - if (rev_id == 0x39) { - enable_14Mhz = (pmio_read(0x53) >> 6) & 1; - if (enable_14Mhz == 0x0) - rev = 0x11; /* A11 */ - else if (enable_14Mhz == 0x1) { - /* This happens, if does, only once. So later if we need to get - * the revision ID, we don't have to make such a big function. - * We just get reg 0x8 in smbus dev. 0x39 is A11, 0x3A is A12. */ - rev = 0x12; - byte = pci_read_config8(dev, 0x40); - byte |= 1 << 0; - pci_write_config8(dev, 0x40, byte); - - pci_write_config8(dev, 0x08, 0x3A); /* Change 0x39 to 0x3A. */ - - byte &= ~(1 << 0); - pci_write_config8(dev, 0x40, byte); - } - } else if (rev_id == 0x3A) { /* A12 will be 0x3A after BIOS is initialized */ - rev = 0x12; - } else if (rev_id == 0x3C) { - rev = 0x14; - } else if (rev_id == 0x3D) { - rev = 0x15; - } else - die("It is not SB700 or SB710\n"); - - return rev; -} - -/*************************************** -* Legacy devices are mapped to LPC space. -* Serial port 0 -* KBC Port -* ACPI Micro-controller port -* This function does not change port 0x80 decoding. -* Console output through any port besides 0x3f8 is unsupported. -* If you use FWH ROMs, you have to setup IDSEL. -***************************************/ -void sb7xx_51xx_lpc_init(void) -{ - u8 reg8; - u32 reg32; - pci_devfn_t dev; - - dev = pci_locate_device(PCI_ID(0x1002, 0x4385), 0); /* SMBUS controller */ - /* NOTE: Set BootTimerDisable, otherwise it would keep rebooting!! - * This bit has no meaning if debug strap is not enabled. So if the - * board keeps rebooting and the code fails to reach here, we could - * disable the debug strap first. */ - reg32 = pci_read_config32(dev, 0x4C); - reg32 |= 1 << 31; - pci_write_config32(dev, 0x4C, reg32); - - /* Enable lpc controller */ - reg32 = pci_read_config32(dev, 0x64); - reg32 |= 1 << 20; - pci_write_config32(dev, 0x64, reg32); - -#if CONFIG(SOUTHBRIDGE_AMD_SUBTYPE_SP5100) - post_code(0x66); - dev = pci_locate_device(PCI_ID(0x1002, 0x439d), 0); /* LPC Controller */ - reg8 = pci_read_config8(dev, 0xBB); - reg8 |= 1 << 2 | 1 << 3 | 1 << 6 | 1 << 7; - reg8 &= ~(1 << 1); - pci_write_config8(dev, 0xBB, reg8); -#endif - - dev = pci_locate_device(PCI_ID(0x1002, 0x439d), 0); /* LPC Controller */ - /* Decode port 0x3f8-0x3ff (Serial 0) */ - // XXX Serial port decode on LPC is hardcoded to 0x3f8 - reg8 = pci_read_config8(dev, 0x44); - reg8 |= 1 << 6; -#if CONFIG(SOUTHBRIDGE_AMD_SUBTYPE_SP5100) -#if CONFIG_TTYS0_BASE == 0x2f8 - reg8 |= 1 << 7; -#endif -#endif - pci_write_config8(dev, 0x44, reg8); - - /* Decode port 0x60 & 0x64 (PS/2 keyboard) and port 0x62 & 0x66 (ACPI)*/ - reg8 = pci_read_config8(dev, 0x47); - reg8 |= (1 << 5) | (1 << 6); - pci_write_config8(dev, 0x47, reg8); - - /* Enable PrefetchEnSPIFromHost to speed up SPI flash read (does not affect LPC) */ - reg8 = pci_read_config8(dev, 0xbb); - reg8 |= 1 << 0; - pci_write_config8(dev, 0xbb, reg8); - - /* Super I/O, RTC */ - reg8 = pci_read_config8(dev, 0x48); - /* Decode ports 0x2e-0x2f, 0x4e-0x4f (SuperI/O configuration) */ - reg8 |= (1 << 1) | (1 << 0); - /* Decode port 0x70-0x73 (RTC) */ - reg8 |= (1 << 6); - pci_write_config8(dev, 0x48, reg8); -} - -void sb7xx_51xx_enable_wideio(u8 wio_index, u16 base) -{ - /* TODO: Now assume wio_index=0 */ - pci_devfn_t dev; - u8 reg8; - - dev = pci_locate_device(PCI_ID(0x1002, 0x439d), 0); /* LPC Controller */ - pci_write_config32(dev, 0x64, base); - reg8 = pci_read_config8(dev, 0x48); - reg8 |= 1 << 2; - pci_write_config8(dev, 0x48, reg8); -} - -void sb7xx_51xx_disable_wideio(u8 wio_index) -{ - /* TODO: Now assume wio_index=0 */ - pci_devfn_t dev; - u8 reg8; - - dev = pci_locate_device(PCI_ID(0x1002, 0x439d), 0); /* LPC Controller */ - pci_write_config32(dev, 0x64, 0); - reg8 = pci_read_config8(dev, 0x48); - reg8 &= ~(1 << 2); - pci_write_config8(dev, 0x48, reg8); -} - -/* what is its usage? */ -u32 get_sbdn(u32 bus) -{ - pci_devfn_t dev; - - /* Find the device. */ - dev = pci_locate_device_on_bus(PCI_ID(0x1002, 0x4385), bus); - return (dev >> 15) & 0x1f; -} - -static u8 dual_core(void) -{ - return (pci_read_config32(PCI_DEV(0, 0x18, 3), 0xE8) & (0x3<<12)) != 0; -} - -/* - * RPR 2.4 C-state and VID/FID change for the K8 platform. - */ -void enable_fid_change_on_sb(u32 sbbusn, u32 sbdn) -{ - u8 byte; - byte = pmio_read(0x9a); - byte &= ~0x34; - if (dual_core()) - byte |= 0x34; - else - byte |= 0x04; - pmio_write(0x9a, byte); - - byte = pmio_read(0x8f); - byte &= ~0x30; - byte |= 0x20; - pmio_write(0x8f, byte); - - pmio_write(0x8b, 0x01); /* TODO: if the HT Link is 200 MHz, it is 0x0A. It doesn't often happen. */ - pmio_write(0x8a, 0x90); - - pmio_write(0x88, 0x10); - - byte = pmio_read(0x7c); - byte |= 0x03; - pmio_write(0x7c, byte); - - /* Must be 0 for K8 platform. */ - byte = pmio_read(0x68); - byte &= ~0x01; - pmio_write(0x68, byte); - /* Must be 0 for K8 platform. */ - byte = pmio_read(0x8d); - byte &= ~(1<<6); - pmio_write(0x8d, byte); - - byte = pmio_read(0x42); - byte &= ~0x04; - pmio_write(0x42, byte); - - pmio_write(0x89, 0x10); - - /* Toggle the LDT_STOP# during FID/VID Change, this bit is documented - only in SB600! - While here, enable C states too - */ - pmio_write(0x67, 0x6); -} - -void sb7xx_51xx_pci_port80(void) -{ - u8 byte; - pci_devfn_t dev; - - /* P2P Bridge */ - dev = pci_locate_device(PCI_ID(0x1002, 0x4384), 0); - - /* Chip Control: Enable subtractive decoding */ - byte = pci_read_config8(dev, 0x40); - byte |= 1 << 5; - pci_write_config8(dev, 0x40, byte); - - /* Misc Control: Enable subtractive decoding if 0x40 bit 5 is set */ - byte = pci_read_config8(dev, 0x4B); - byte |= 1 << 7; - pci_write_config8(dev, 0x4B, byte); - - /* The same IO Base and IO Limit here is meaningful because we set the - * bridge to be subtractive. During early setup stage, we have to make - * sure that data can go through port 0x80. - */ - /* IO Base: 0xf000 */ - byte = pci_read_config8(dev, 0x1C); - byte |= 0xF << 4; - pci_write_config8(dev, 0x1C, byte); - - /* IO Limit: 0xf000 */ - byte = pci_read_config8(dev, 0x1D); - byte |= 0xF << 4; - pci_write_config8(dev, 0x1D, byte); - - /* PCI Command: Enable IO response */ - byte = pci_read_config8(dev, 0x04); - byte |= 1 << 0; - pci_write_config8(dev, 0x04, byte); - - /* LPC controller */ - dev = pci_locate_device(PCI_ID(0x1002, 0x439D), 0); - - byte = pci_read_config8(dev, 0x4A); - byte &= ~(1 << 5); /* disable lpc port 80 */ - pci_write_config8(dev, 0x4A, byte); -} - -void sb7xx_51xx_lpc_port80(void) -{ - u8 byte; - pci_devfn_t dev; - u32 reg32; - - /* Enable LPC controller */ - dev = pci_locate_device(PCI_ID(0x1002, 0x4385), 0); - reg32 = pci_read_config32(dev, 0x64); - reg32 |= 0x00100000; /* lpcEnable */ - pci_write_config32(dev, 0x64, reg32); - - /* Enable port 80 LPC decode in pci function 3 configuration space. */ - dev = pci_locate_device(PCI_ID(0x1002, 0x439d), 0); - byte = pci_read_config8(dev, 0x4a); - byte |= 1 << 5; /* enable port 80 */ - pci_write_config8(dev, 0x4a, byte); -} - -/* sbDevicesPorInitTable */ -static void sb700_devices_por_init(void) -{ - pci_devfn_t dev; - u8 byte; - uint32_t dword; - uint8_t nvram; - uint8_t sata_ahci_mode; - - sata_ahci_mode = 0; - if (get_option(&nvram, "sata_ahci_mode") == CB_SUCCESS) - sata_ahci_mode = !!nvram; - - printk(BIOS_INFO, "sb700_devices_por_init()\n"); - /* SMBus Device, BDF:0-20-0 */ - printk(BIOS_INFO, "sb700_devices_por_init(): SMBus Device, BDF:0-20-0\n"); - dev = pci_locate_device(PCI_ID(0x1002, 0x4385), 0); - - if (dev == PCI_DEV_INVALID) { - die("SMBUS controller not found\n"); - /* NOT REACHED */ - } - printk(BIOS_INFO, "SMBus controller enabled, sb revision is A%x\n", - set_sb700_revision()); - - /* sbPorAtStartOfTblCfg */ - /* Set A-Link bridge access address. This address is set at device 14h, function 0, register 0xf0. - * This is an I/O address. The I/O address must be on 16-byte boundary. */ - pci_write_config32(dev, 0xf0, AB_INDX); - - /* To enable AB/BIF DMA access, a specific register inside the BIF register space needs to be configured first. */ - /* 4.3:Enables the SB700 to send transactions upstream over A-Link Express interface. */ - axcfg_reg(0x04, 1 << 2, 1 << 2); - axindxc_reg(0x21, 0xff, 0); - - /* 2.5:Enabling Non-Posted Memory Write for the K8 Platform */ - axindxc_reg(0x10, 1 << 9, 1 << 9); - /* END of sbPorAtStartOfTblCfg */ - - /* sbDevicesPorInitTables */ - /* set smbus iobase */ - pci_write_config32(dev, 0x90, SMBUS_IO_BASE | 1); - - /* enable smbus controller interface */ - byte = pci_read_config8(dev, 0xd2); - byte |= (1 << 0); - pci_write_config8(dev, 0xd2, byte); - - /* set auxiliary smbus iobase and enable controller */ - pci_write_config32(dev, 0x58, SMBUS_AUX_IO_BASE | 1); - - if (inb(SMBUS_IO_BASE) == 0xff) - printk(BIOS_INFO, "%s: Primary SMBUS controller I/O not found\n", __func__); - - if (inb(SMBUS_AUX_IO_BASE) == 0xff) { - printk(BIOS_INFO, "%s: Secondary SMBUS controller I/O not found\n", __func__); - } - else { - if (CONFIG(SOUTHBRIDGE_AMD_SUBTYPE_SP5100)) { - /* Disable legacy sensor support / reset ASF Slave state machine per RPR 2.27 step 3 */ - outb(0x40, SMBUS_AUX_IO_BASE + SMBSLVMISC); - } - } - - /* KB2RstEnable */ - pci_write_config8(dev, 0x40, 0x44); - - /* Enable ISA Address 0-960K decoding */ - pci_write_config8(dev, 0x48, 0x0f); - - /* Enable ISA Address 0xC0000-0xDFFFF decode */ - pci_write_config8(dev, 0x49, 0xff); - - /* Enable decode cycles to IO C50, C51, C52 GPM controls. */ - byte = pci_read_config8(dev, 0x41); - byte &= 0x80; - byte |= 0x33; - pci_write_config8(dev, 0x41, byte); - - /* Legacy DMA Prefetch Enhancement, CIM masked it. */ - /* pci_write_config8(dev, 0x43, 0x1); */ - - /* Enable DMA verify bugfix */ - byte = pci_read_config8(dev, 0x67); - byte |= 0x1 << 1; - pci_write_config8(dev, 0x67, byte); - - /* Disabling Legacy USB Fast SMI# */ - byte = pci_read_config8(dev, 0x62); - byte |= 0x24; - pci_write_config8(dev, 0x62, byte); - - /* Configure HPET Counter CLK period */ - byte = pci_read_config8(dev, 0x43); - byte &= 0xF7; /* Unhide HPET regs */ - pci_write_config8(dev, 0x43, byte); - pci_write_config32(dev, 0x34, 0x0429b17e); /* Counter CLK period */ - byte |= 0x08; /* Hide HPET regs */ - pci_write_config8(dev, 0x43, byte); - - /* Features Enable */ - pci_write_config32(dev, 0x64, 0x829E79BF); /* bit10: Enables the HPET interrupt. */ - - /* SerialIrq Control */ - pci_write_config8(dev, 0x69, 0x90); - - /* Test Mode, PCIB_SReset_En Mask is set. */ - pci_write_config8(dev, 0x6c, 0x20); - - /* IO Address Enable, CIM set 0x78 only and masked 0x79. */ - /*pci_write_config8(dev, 0x79, 0x4F); */ - pci_write_config8(dev, 0x78, 0xFF); - - if (CONFIG(SOUTHBRIDGE_AMD_SB700_DISABLE_ISA_DMA)) { - printk(BIOS_DEBUG, "%s: Disabling ISA DMA support\n", __func__); - /* Disable LPC ISA DMA Capability */ - byte = pci_read_config8(dev, 0x78); - byte &= ~(1 << 0); - pci_write_config8(dev, 0x78, byte); - } - - /* Set smbus iospace enable, I don't know why write 0x04 into reg5 that is reserved */ - pci_write_config16(dev, 0x4, 0x0407); - - /* clear any lingering errors, so the transaction will run */ - outb(inb(SMBUS_IO_BASE + SMBHSTSTAT), SMBUS_IO_BASE + SMBHSTSTAT); - - /* IDE Device, BDF:0-20-1 */ - printk(BIOS_INFO, "sb700_devices_por_init(): IDE Device, BDF:0-20-1\n"); - dev = pci_locate_device(PCI_ID(0x1002, 0x439C), 0); - /* Disable prefetch */ - byte = pci_read_config8(dev, 0x63); - byte |= 0x1; - pci_write_config8(dev, 0x63, byte); - - /* LPC Device, BDF:0-20-3 */ - printk(BIOS_INFO, "sb700_devices_por_init(): LPC Device, BDF:0-20-3\n"); - dev = pci_locate_device(PCI_ID(0x1002, 0x439D), 0); - if (!CONFIG(SOUTHBRIDGE_AMD_SB700_DISABLE_ISA_DMA)) { - /* DMA enable */ - pci_write_config8(dev, 0x40, 0x04); - } - - /* IO Port Decode Enable */ - pci_write_config8(dev, 0x44, 0xFF); - pci_write_config8(dev, 0x45, 0xFF); - pci_write_config8(dev, 0x46, 0xC3); - pci_write_config8(dev, 0x47, 0xFF); - - // TODO: This has already been done(?) - /* IO/Mem Port Decode Enable, I don't know why CIM disable some ports. - * Disable LPC TimeOut counter, enable SuperIO Configuration Port (2e/2f), - * Alternate Super I/O Configuration Port (4e/4f), Wide Generic IO Port (64/65). */ - byte = pci_read_config8(dev, 0x48); - byte |= (1 << 1) | (1 << 0); /* enable Super IO config port 2e-2h, 4e-4f */ - byte |= 1 << 6; /* enable for RTC I/O range */ - pci_write_config8(dev, 0x48, byte); - pci_write_config8(dev, 0x49, 0xFF); - /* Enable 0x480-0x4bf, 0x4700-0x470B */ - byte = pci_read_config8(dev, 0x4A); - byte |= ((1 << 1) + (1 << 6)); /*0x42, save the configuration for port 0x80. */ - pci_write_config8(dev, 0x4A, byte); - - /* Enable Tpm12_en and Tpm_legacy. I don't know what is its usage and copied from CIM. */ - pci_write_config8(dev, 0x7C, 0x05); - - /* P2P Bridge, BDF:0-20-4, the configuration of the registers in this dev are copied from CIM, - */ - printk(BIOS_INFO, "sb700_devices_por_init(): P2P Bridge, BDF:0-20-4\n"); - dev = pci_locate_device(PCI_ID(0x1002, 0x4384), 0); - - /* Arbiter enable. */ - pci_write_config8(dev, 0x43, 0xff); - - /* Set PCDMA request into height priority list. */ - /* pci_write_config8(dev, 0x49, 0x1); */ - - pci_write_config8(dev, 0x40, 0x26); - - pci_write_config8(dev, 0x0d, 0x40); - pci_write_config8(dev, 0x1b, 0x40); - /* Enable PCIB_DUAL_EN_UP will fix potential problem with PCI cards. */ - pci_write_config8(dev, 0x50, 0x01); - - if (!sata_ahci_mode){ -#if CONFIG(SOUTHBRIDGE_AMD_SUBTYPE_SP5100) - /* SP5100 default SATA mode is RAID5 MODE */ - dev = pci_locate_device(PCI_ID(0x1002, 0x4392), 0); - - if (dev != PCI_DEV_INVALID) { - /* Set SATA Operation Mode, Set to IDE mode */ - byte = pci_read_config8(dev, 0x40); - byte |= (1 << 0); - pci_write_config8(dev, 0x40, byte); - - dword = 0x01018f00; - pci_write_config32(dev, 0x8, dword); - - /* set SATA Device ID writable */ - dword = pci_read_config32(dev, 0x40); - dword &= ~(1 << 24); - pci_write_config32(dev, 0x40, dword); - - /* set Device ID consistent with IDE emulation mode configuration */ - pci_write_config32(dev, 0x0, 0x43901002); - } -#endif - } - - /* rpr v2.13 4.17 Reset CPU on Sync Flood */ - abcfg_reg(0x10050, 1 << 2, 1 << 2); - - /* SATA Device, BDF:0-17-0, Non-Raid-5 SATA controller */ - printk(BIOS_INFO, "sb700_devices_por_init(): SATA Device, BDF:0-17-0\n"); - dev = pci_locate_device(PCI_ID(0x1002, 0x4390), 0); - - if (sata_ahci_mode) { - /* Switch to AHCI mode (AMD inbox) */ - dword = pci_read_config32(dev, 0x40); - dword |= (0x1 << 24); /* Lock Flash Device ID = 1 */ - pci_write_config32(dev, 0x40, dword); - - /* Deactivate Sub-Class Code write protection */ - byte = pci_read_config8(dev, 0x40); - byte |= (1 << 0); - pci_write_config8(dev, 0x40, byte); - - dword = pci_read_config32(dev, 0x08); - dword &= ~(0xff << 16); /* Sub-Class Code = 0x6 */ - dword |= (0x6 << 16); - dword &= ~(0xff << 8); /* Operating Mode Selection = 0x1 */ - dword |= (0x1 << 8); - pci_write_config32(dev, 0x08, dword); - } - - /* PHY Global Control */ - pci_write_config16(dev, 0x86, 0x2C00); -} - -/* sbPmioPorInitTable, Pre-initializing PMIO register space -* The power management (PM) block is resident in the PCI/LPC/ISA bridge. -* The PM regs are accessed via IO mapped regs 0xcd6 and 0xcd7. -* The index address is first programmed into IO reg 0xcd6. -* Read or write values are accessed through IO reg 0xcd7. -*/ -static void sb700_pmio_por_init(void) -{ - u8 byte; - uint8_t enable_c_states; - - enable_c_states = 0; -#if CONFIG(HAVE_ACPI_TABLES) - if (get_option(&byte, "cpu_c_states") == CB_SUCCESS) - enable_c_states = !!byte; -#endif - - printk(BIOS_INFO, "sb700_pmio_por_init()\n"); - /* K8KbRstEn, KB_RST# control for K8 system. */ - byte = pmio_read(0x66); - byte |= 0x20; - pmio_write(0x66, byte); - - if (CONFIG(SOUTHBRIDGE_AMD_SUBTYPE_SP5100)) { - /* RPR 2.11 Sx State Settings */ - byte = pmio_read(0x65); - byte &= ~(1 << 7); /* SpecialFunc = 0 */ - pmio_write(0x65, byte); - - byte = pmio_read(0x68); - byte |= 1 << 2; /* MaskApicEn = 1 */ - pmio_write(0x68, byte); - } else { - /* RPR2.31 PM_TURN_OFF_MSG during ASF Shutdown. */ - if (get_sb700_revision(pci_locate_device(PCI_ID(0x1002, 0x4385), 0)) <= 0x12) { - byte = pmio_read(0x65); - byte &= ~(1 << 7); - pmio_write(0x65, byte); - - byte = pmio_read(0x75); - byte &= 0xc0; - byte |= 0x05; - pmio_write(0x75, byte); - - byte = pmio_read(0x52); - byte &= 0xc0; - byte |= 0x08; - pmio_write(0x52, byte); - } else { - byte = pmio_read(0xD7); - byte |= 1 << 0; - pmio_write(0xD7, byte); - - byte = pmio_read(0x65); - byte |= 1 << 7; - pmio_write(0x65, byte); - - byte = pmio_read(0x75); - byte &= 0xc0; - byte |= 0x01; - pmio_write(0x75, byte); - - byte = pmio_read(0x52); - byte &= 0xc0; - byte |= 0x02; - pmio_write(0x52, byte); - } - } - - /* Watch Dog Timer Control - * Set watchdog time base to 0xfec000f0 to avoid SCSI card boot failure. - * But I don't find WDT is enabled in SMBUS 0x41 bit3 in CIM. - */ - pmio_write(0x6c, 0xf0); - pmio_write(0x6d, 0x00); - pmio_write(0x6e, 0xc0); - pmio_write(0x6f, 0xfe); - - /* rpr2.15: Enabling Spread Spectrum */ - byte = pmio_read(0x42); - byte |= 1 << 7; - pmio_write(0x42, byte); - /* TODO: Check if it is necessary. IDE reset */ - byte = pmio_read(0xB2); - byte |= 1 << 0; - pmio_write(0xB2, byte); - - /* Set up IOAPIC and BM_STS monitoring */ - byte = pmio_read(0x61); - if (enable_c_states) - byte |= 0x4; - else - byte &= ~0x04; - pmio_write(0x61, byte); - - /* NOTE: Enabling automatic C1e state switch caused failures when initializing processors */ - - /* Enable precision HPET clock and automatic C state switch */ - byte = pmio_read(0xbb); - byte |= 0xc0; - pmio_write(0xbb, byte); - -#if CONFIG(SOUTHBRIDGE_AMD_SUBTYPE_SP5100) - /* RPR 2.26 Alter CPU reset timing */ - byte = pmio_read(0xb2); - byte |= 0x1 << 2; /* Enable CPU reset timing option */ - pmio_write(0xb2, byte); - - /* Work around system clock drift issues */ - byte = pmio_read(0xd4); - byte |= 0x1 << 6; /* Enable alternate 14MHz clock source */ - byte |= 0x1 << 7; /* Disable 25MHz oscillator buffer */ - pmio_write(0xd4, byte); -#endif -} - -/* -* Add any south bridge setting. -*/ -static void sb700_pci_cfg(void) -{ - pci_devfn_t dev; - u8 byte; - uint8_t acpi_s1_supported = 1; - - /* SMBus Device, BDF:0-20-0 */ - dev = pci_locate_device(PCI_ID(0x1002, 0x4385), 0); - - /* Enable watchdog timer decode */ - byte = pci_read_config8(dev, 0x41); - byte |= (1 << 3); - pci_write_config8(dev, 0x41, byte); - - /* Set to 1 to reset USB on the software (such as IO-64 or IO-CF9 cycles) - * generated PCIRST#. */ - byte = pmio_read(0x65); - byte |= (1 << 4); - pmio_write(0x65, byte); - - /* IDE Device, BDF:0-20-1 */ - dev = pci_locate_device(PCI_ID(0x1002, 0x439C), 0); - /* Enable IDE Explicit prefetch, 0x63[0] clear */ - byte = pci_read_config8(dev, 0x63); - byte &= 0xfe; - pci_write_config8(dev, 0x63, byte); - - /* LPC Device, BDF:0-20-3 */ - /* The code below is ported from old chipset. It is not - * mentioned in RPR. But I keep them. The registers and the - * comments are compatible. */ - dev = pci_locate_device(PCI_ID(0x1002, 0x439D), 0); - if (!CONFIG(SOUTHBRIDGE_AMD_SB700_DISABLE_ISA_DMA)) { - /* Enabling LPC DMA function. */ - byte = pci_read_config8(dev, 0x40); - byte |= (1 << 2); - pci_write_config8(dev, 0x40, byte); - } - /* Disabling LPC TimeOut. 0x48[7] clear. */ - byte = pci_read_config8(dev, 0x48); - byte &= 0x7f; - pci_write_config8(dev, 0x48, byte); - /* Disabling LPC MSI Capability, 0x78[1] clear. */ - byte = pci_read_config8(dev, 0x78); - byte &= 0xfd; - pci_write_config8(dev, 0x78, byte); - - /* SATA Device, BDF:0-17-0, Non-Raid-5 SATA controller */ - dev = pci_locate_device(PCI_ID(0x1002, 0x4390), 0); - if (dev == PCI_DEV_INVALID) - dev = pci_locate_device(PCI_ID(0x1002, 0x4391), 0); - if (dev == PCI_DEV_INVALID) - dev = pci_locate_device(PCI_ID(0x1002, 0x4394), 0); - - /* rpr7.12 SATA MSI and D3 Power State Capability. */ - byte = pci_read_config8(dev, 0x40); - byte |= 1 << 0; - pci_write_config8(dev, 0x40, byte); - if (acpi_s1_supported) - pci_write_config8(dev, 0x34, 0x70); /* Hide D3 power state and MSI capabilities */ - else - pci_write_config8(dev, 0x61, 0x70); /* Hide MSI capability */ - byte &= ~(1 << 0); - pci_write_config8(dev, 0x40, byte); -} - -/* -*/ -static void sb700_por_init(void) -{ - /* sbDevicesPorInitTable + sbK8PorInitTable */ - sb700_devices_por_init(); - - /* sbPmioPorInitTable + sbK8PmioPorInitTable */ - sb700_pmio_por_init(); -} - -uint16_t sb7xx_51xx_decode_last_reset(void) { - uint16_t reset_status = 0; - reset_status |= pmio_read(0x44); - reset_status |= (pmio_read(0x45) << 8); - printk(BIOS_INFO, "sb700 reset flags: %04x\n", reset_status); - if (reset_status & (0x1 << 10)) - printk(BIOS_WARNING, "WARNING: Last reset was caused by fatal error / sync flood!\n"); - - return reset_status; -} - -/* -* It should be called during early POST after memory detection and BIOS shadowing but before PCI bus enumeration. -*/ -void sb7xx_51xx_before_pci_init(void) -{ - sb700_pci_cfg(); -} - -/* -* This function should be called after enable_sb700_smbus(). -*/ -void sb7xx_51xx_early_setup(void) -{ - printk(BIOS_INFO, "sb700_early_setup()\n"); - sb700_por_init(); - sb700_acpi_init(); -} - -int s3_save_nvram_early(u32 dword, int size, int nvram_pos) -{ - int i; - printk(BIOS_DEBUG, "Writing %x of size %d to nvram pos: %d\n", dword, size, nvram_pos); - - for (i = 0; i < size; i++) { - outb(nvram_pos, BIOSRAM_INDEX); - outb((dword >> (8 * i)) & 0xff, BIOSRAM_DATA); - nvram_pos++; - } - - return nvram_pos; -} - -int s3_load_nvram_early(int size, u32 *old_dword, int nvram_pos) -{ - u32 data = *old_dword; - int i; - for (i = 0; i < size; i++) { - outb(nvram_pos, BIOSRAM_INDEX); - data &= ~(0xff << (i * 8)); - data |= inb(BIOSRAM_DATA) << (i *8); - nvram_pos++; - } - *old_dword = data; - printk(BIOS_DEBUG, "Loading %x of size %d to nvram pos:%d\n", *old_dword, size, - nvram_pos-size); - return nvram_pos; -} - -void set_lpc_sticky_ctl(bool enable) -{ - uint8_t byte; - - byte = pmio_read(0xbb); - if (enable) - byte |= 0x20; - else - byte &= ~0x20; - pmio_write(0xbb, byte); -} - -#endif diff --git a/src/southbridge/amd/sb700/enable_usbdebug.c b/src/southbridge/amd/sb700/enable_usbdebug.c deleted file mode 100644 index 4f859c6da6..0000000000 --- a/src/southbridge/amd/sb700/enable_usbdebug.c +++ /dev/null @@ -1,47 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2010 Advanced Micro Devices, Inc. - * Copyright (C) 2010 Uwe Hermann - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -// Use simple device model for this file even in ramstage -#define __SIMPLE_DEVICE__ - -#include -#include -#include -#include -#include "sb700.h" - -#define DEBUGPORT_MISC_CONTROL 0x80 - -pci_devfn_t pci_ehci_dbg_dev(unsigned int hcd_idx) -{ - if (hcd_idx == 2) - return PCI_DEV(0, 0x13, 2); - else - return PCI_DEV(0, 0x12, 2); -} - -void pci_ehci_dbg_set_port(pci_devfn_t dev, unsigned int port) -{ - u8 *base_regs = pci_ehci_base_regs(dev); - u32 reg32; - - /* Write the port number to DEBUGPORT_MISC_CONTROL[31:28]. */ - reg32 = read32(base_regs + DEBUGPORT_MISC_CONTROL); - reg32 &= ~(0xf << 28); - reg32 |= (port << 28); - reg32 |= (1 << 27); /* Enable Debug Port port number remapping. */ - write32(base_regs + DEBUGPORT_MISC_CONTROL, reg32); -} diff --git a/src/southbridge/amd/sb700/fadt.c b/src/southbridge/amd/sb700/fadt.c deleted file mode 100644 index c81e644aa7..0000000000 --- a/src/southbridge/amd/sb700/fadt.c +++ /dev/null @@ -1,162 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2010 Advanced Micro Devices, Inc. - * Copyright (C) 2015 Raptor Engineering - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -/* - * ACPI - create the Fixed ACPI Description Tables (FADT) - */ - -#include -#include -#include -#include -#include -#include - -#include "sb700.h" - -void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt) -{ - acpi_header_t *header = &(fadt->header); - - printk(BIOS_DEBUG, "pm_base: 0x%04x\n", SB700_ACPI_IO_BASE); - - /* Prepare the header */ - memset((void *)fadt, 0, sizeof(acpi_fadt_t)); - memcpy(header->signature, "FACP", 4); - header->length = sizeof(acpi_fadt_t); - header->revision = get_acpi_table_revision(FADT); - memcpy(header->oem_id, OEM_ID, 6); - memcpy(header->oem_table_id, ACPI_TABLE_CREATOR, 8); - memcpy(header->asl_compiler_id, ASLC, 4); - header->asl_compiler_revision = asl_revision; - - fadt->firmware_ctrl = (u32) facs; - fadt->dsdt = (u32) dsdt; - /* 3=Workstation,4=Enterprise Server, 7=Performance Server */ - fadt->preferred_pm_profile = 0x03; - fadt->sci_int = 9; - /* disable system management mode by setting to 0: */ - fadt->smi_cmd = 0; - fadt->acpi_enable = 0xf0; - fadt->acpi_disable = 0xf1; - fadt->s4bios_req = 0x0; - fadt->pstate_cnt = 0xe2; - fadt->pm1a_evt_blk = ACPI_PM_EVT_BLK; - fadt->pm1b_evt_blk = 0x0000; - fadt->pm1a_cnt_blk = ACPI_PM1_CNT_BLK; - fadt->pm1b_cnt_blk = 0x0000; - fadt->pm2_cnt_blk = ACPI_PMA_CNT_BLK; - fadt->pm_tmr_blk = ACPI_PM_TMR_BLK; - fadt->gpe0_blk = ACPI_GPE0_BLK; - fadt->gpe1_blk = 0x0000; /* we don't have gpe1 block, do we? */ - - fadt->pm1_evt_len = 4; - fadt->pm1_cnt_len = 2; - fadt->pm2_cnt_len = 1; - fadt->pm_tmr_len = 4; - fadt->gpe0_blk_len = 8; - fadt->gpe1_blk_len = 0; - fadt->gpe1_base = 0; - - fadt->cst_cnt = 0xe3; - fadt->p_lvl2_lat = 101; - fadt->p_lvl3_lat = 1001; - fadt->flush_size = 0; - fadt->flush_stride = 0; - fadt->duty_offset = 1; - fadt->duty_width = 3; - fadt->day_alrm = 0; /* 0x7d these have to be */ - fadt->mon_alrm = 0; /* 0x7e added to cmos.layout */ - fadt->century = 0; /* 0x7f to make rtc alarm work */ - fadt->iapc_boot_arch = 0x3; /* See table 5-11 */ - fadt->flags = 0x0001c1a5;/* 0x25; */ - - fadt->res2 = 0; - - fadt->reset_reg.space_id = 1; - fadt->reset_reg.bit_width = 8; - fadt->reset_reg.bit_offset = 0; - fadt->reset_reg.access_size = 0; - fadt->reset_reg.addrl = 0xcf9; - fadt->reset_reg.addrh = 0x0; - - fadt->reset_value = 6; - fadt->x_firmware_ctl_l = (u32) facs; - fadt->x_firmware_ctl_h = 0; - fadt->x_dsdt_l = (u32) dsdt; - fadt->x_dsdt_h = 0; - - fadt->x_pm1a_evt_blk.space_id = 1; - fadt->x_pm1a_evt_blk.bit_width = 32; - fadt->x_pm1a_evt_blk.bit_offset = 0; - fadt->x_pm1a_evt_blk.access_size = 0; - fadt->x_pm1a_evt_blk.addrl = ACPI_PM_EVT_BLK; - fadt->x_pm1a_evt_blk.addrh = 0x0; - - fadt->x_pm1b_evt_blk.space_id = 1; - fadt->x_pm1b_evt_blk.bit_width = 4; - fadt->x_pm1b_evt_blk.bit_offset = 0; - fadt->x_pm1b_evt_blk.access_size = 0; - fadt->x_pm1b_evt_blk.addrl = 0x0; - fadt->x_pm1b_evt_blk.addrh = 0x0; - - fadt->x_pm1a_cnt_blk.space_id = 1; - fadt->x_pm1a_cnt_blk.bit_width = 16; - fadt->x_pm1a_cnt_blk.bit_offset = 0; - fadt->x_pm1a_cnt_blk.access_size = 0; - fadt->x_pm1a_cnt_blk.addrl = ACPI_PM1_CNT_BLK; - fadt->x_pm1a_cnt_blk.addrh = 0x0; - - fadt->x_pm1b_cnt_blk.space_id = 1; - fadt->x_pm1b_cnt_blk.bit_width = 2; - fadt->x_pm1b_cnt_blk.bit_offset = 0; - fadt->x_pm1b_cnt_blk.access_size = 0; - fadt->x_pm1b_cnt_blk.addrl = 0x0; - fadt->x_pm1b_cnt_blk.addrh = 0x0; - - fadt->x_pm2_cnt_blk.space_id = 1; - fadt->x_pm2_cnt_blk.bit_width = 8; - fadt->x_pm2_cnt_blk.bit_offset = 0; - fadt->x_pm2_cnt_blk.access_size = 0; - fadt->x_pm2_cnt_blk.addrl = ACPI_PMA_CNT_BLK; - fadt->x_pm2_cnt_blk.addrh = 0x0; - - fadt->x_pm_tmr_blk.space_id = 1; - fadt->x_pm_tmr_blk.bit_width = 32; - fadt->x_pm_tmr_blk.bit_offset = 0; - fadt->x_pm_tmr_blk.access_size = 0; - fadt->x_pm_tmr_blk.addrl = ACPI_PM_TMR_BLK; - fadt->x_pm_tmr_blk.addrh = 0x0; - - fadt->x_gpe0_blk.space_id = 1; - fadt->x_gpe0_blk.bit_width = 64; - fadt->x_gpe0_blk.bit_offset = 0; - fadt->x_gpe0_blk.access_size = 0; - fadt->x_gpe0_blk.addrl = ACPI_GPE0_BLK; - fadt->x_gpe0_blk.addrh = 0x0; - - fadt->x_gpe1_blk.space_id = 1; - fadt->x_gpe1_blk.bit_width = 0; - fadt->x_gpe1_blk.bit_offset = 0; - fadt->x_gpe1_blk.access_size = 0; - fadt->x_gpe1_blk.addrl = 0; - fadt->x_gpe1_blk.addrh = 0x0; - - if (CONFIG(CPU_AMD_MODEL_10XXX)) - amd_powernow_update_fadt(fadt); - - header->checksum = acpi_checksum((void *)fadt, sizeof(acpi_fadt_t)); -} diff --git a/src/southbridge/amd/sb700/hda.c b/src/southbridge/amd/sb700/hda.c deleted file mode 100644 index bf988b72c0..0000000000 --- a/src/southbridge/amd/sb700/hda.c +++ /dev/null @@ -1,226 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2010 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include -#include -#include -#include -#include -#include "sb700.h" - -#define HDA_ICII_REG 0x68 -#define HDA_ICII_BUSY (1 << 0) -#define HDA_ICII_VALID (1 << 1) - -static int set_bits(void *port, u32 mask, u32 val) -{ - u32 dword; - int count; - - /* Write (val & ~mask) to port */ - val &= mask; - dword = read32(port); - dword &= ~mask; - dword |= val; - write32(port, dword); - - /* Wait for readback of register to - * match what was just written to it - */ - count = 50; - do { - /* Wait 1ms based on BKDG wait time */ - mdelay(1); - dword = read32(port); - dword &= mask; - } while ((dword != val) && --count); - - /* Timeout occurred */ - if (!count) - return -1; - return 0; -} - -static u32 codec_detect(void *base) -{ - u32 dword; - - /* Set Bit0 to 0 to enter reset state (BAR + 0x8)[0] */ - if (set_bits(base + 0x08, 1, 0) == -1) - goto no_codec; - - /* Set Bit 0 to 1 to exit reset state (BAR + 0x8)[0] */ - if (set_bits(base + 0x08, 1, 1) == -1) - goto no_codec; - - /* Delay for 1 ms since the BKDG does */ - mdelay(1); - - /* Read in Codec location (BAR + 0xe)[3..0]*/ - dword = read32(base + 0xe); - dword &= 0x0F; - if (!dword) - goto no_codec; - - return dword; - -no_codec: - /* Codec Not found */ - /* Put HDA back in reset (BAR + 0x8) [0] */ - set_bits(base + 0x08, 1, 0); - printk(BIOS_DEBUG, "No codec!\n"); - return 0; -} - -/** - * Wait 50usec for the codec to indicate it is ready - * no response would imply that the codec is non-operative - */ -static int wait_for_ready(void *base) -{ - /* Use a 50 usec timeout - the Linux kernel uses the - * same duration */ - - int timeout = 50; - - while (timeout--) { - u32 dword = read32(base + HDA_ICII_REG); - if (!(dword & HDA_ICII_BUSY)) - return 0; - udelay(1); - } - - return -1; -} - -/** - * Wait 50usec for the codec to indicate that it accepted - * the previous command. No response would imply that the code - * is non-operative - */ -static int wait_for_valid(void *base) -{ - /* Use a 50 usec timeout - the Linux kernel uses the - * same duration */ - - int timeout = 50; - while (timeout--) { - u32 dword = read32(base + HDA_ICII_REG); - if ((dword & (HDA_ICII_VALID | HDA_ICII_BUSY)) == - HDA_ICII_VALID) - return 0; - udelay(1); - } - - return -1; -} - -static void codec_init(void *base, int addr) -{ - u32 dword; - - /* 1 */ - if (wait_for_ready(base) == -1) - return; - - dword = (addr << 28) | 0x000f0000; - write32(base + 0x60, dword); - - if (wait_for_valid(base) == -1) - return; - - dword = read32(base + 0x64); - - /* 2 */ - printk(BIOS_DEBUG, "%x(th) codec viddid: %08x\n", addr, dword); -} - -static void codecs_init(void *base, u32 codec_mask) -{ - int i; - for (i = 2; i >= 0; i--) { - if (codec_mask & (1 << i)) - codec_init(base, i); - } -} - -static void hda_init(struct device *dev) -{ - u8 byte; - u32 dword; - void *base; - struct resource *res; - u32 codec_mask; - struct device *sm_dev; - - /* Enable azalia - PM_io 0x59[3], no ac97 in sb700. */ - byte = pm_ioread(0x59); - byte |= 1 << 3; - pm_iowrite(0x59, byte); - - /* Find the SMBus */ - sm_dev = dev_find_device(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_SB700_SM, 0); - - /* Set routing pin - SMBus ExtFunc (0xf8/0xfc) */ - pci_write_config32(sm_dev, 0xf8, 0x00); - pci_write_config8(sm_dev, 0xfc, 0xAA); - /* Set INTA - SMBus 0x63 [2..0] */ - byte = pci_read_config8(sm_dev, 0x63); - byte &= ~0x7; - byte |= 0x0; /* INTA:0x0 - INTH:0x7 */ - pci_write_config8(sm_dev, 0x63, byte); - - /* Program the 2C to 0x437b1002 */ - dword = 0x437b1002; - pci_write_config32(dev, 0x2c, dword); - - /* Read in BAR */ - /* Is this right? HDA allows for a 64-bit BAR - * but this is only setup for a 32-bit one - */ - res = find_resource(dev, 0x10); - if (!res) - return; - - base = res2mmio(res, 0, 0); - printk(BIOS_DEBUG, "base = 0x%p\n", base); - codec_mask = codec_detect(base); - - if (codec_mask) { - printk(BIOS_DEBUG, "codec_mask = %02x\n", codec_mask); - codecs_init(base, codec_mask); - } -} - -static struct pci_operations lops_pci = { - .set_subsystem = pci_dev_set_subsystem, -}; - -static struct device_operations hda_audio_ops = { - .read_resources = pci_dev_read_resources, - .set_resources = pci_dev_set_resources, - .enable_resources = pci_dev_enable_resources, - .init = hda_init, - .scan_bus = 0, - .ops_pci = &lops_pci, -}; - -static const struct pci_driver hdaaudio_driver __pci_driver = { - .ops = &hda_audio_ops, - .vendor = PCI_VENDOR_ID_ATI, - .device = PCI_DEVICE_ID_ATI_SB700_HDA, -}; diff --git a/src/southbridge/amd/sb700/ide.c b/src/southbridge/amd/sb700/ide.c deleted file mode 100644 index 070ee67d9c..0000000000 --- a/src/southbridge/amd/sb700/ide.c +++ /dev/null @@ -1,87 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2015 Timothy Pearson , Raptor Engineering - * Copyright (C) 2010 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include -#include -#include -#include - -#include "sb700.h" -#include "chip.h" - -static void ide_init(struct device *dev) -{ - struct southbridge_amd_sb700_config *conf; - /* Enable ide devices so the linux ide driver will work */ - u32 dword; - u8 byte; - uint8_t nvram; - uint8_t sata_ahci_mode; - - sata_ahci_mode = 0; - if (get_option(&nvram, "sata_ahci_mode") == CB_SUCCESS) - sata_ahci_mode = !!nvram; - - conf = dev->chip_info; - - /* RPR9.1 disable MSI */ - /* TODO: For A14, it should set as 1. I doubt it. */ - dword = pci_read_config32(dev, 0x70); - dword &= ~(1 << 16); - pci_write_config32(dev, 0x70, dword); - - if (!sata_ahci_mode) { - /* Enable UDMA on all devices, it will become UDMA0 (default PIO is PIO0) */ - byte = pci_read_config8(dev, 0x54); - byte |= 0xf; - pci_write_config8(dev, 0x54, byte); - - /* Enable I/O Access&& Bus Master */ - dword = pci_read_config16(dev, 0x4); - dword |= 1 << 2; - pci_write_config16(dev, 0x4, dword); - - /* set ide as primary, if you want to boot from IDE, you'd better set it - * in $vendor/$mainboard/devicetree.cb */ - if (conf->boot_switch_sata_ide == 1) { - struct device *sm_dev = pcidev_on_root(0x14, 0); - byte = pci_read_config8(sm_dev, 0xad); - byte |= 1 << 4; - pci_write_config8(sm_dev, 0xad, byte); - } - } -} - -static struct pci_operations lops_pci = { - .set_subsystem = pci_dev_set_subsystem, -}; - -static struct device_operations ide_ops = { - .read_resources = pci_dev_read_resources, - .set_resources = pci_dev_set_resources, - .enable_resources = pci_dev_enable_resources, - .init = ide_init, - .scan_bus = 0, - .ops_pci = &lops_pci, -}; - -static const struct pci_driver ide_driver __pci_driver = { - .ops = &ide_ops, - .vendor = PCI_VENDOR_ID_ATI, - .device = PCI_DEVICE_ID_ATI_SB700_IDE, -}; diff --git a/src/southbridge/amd/sb700/lpc.c b/src/southbridge/amd/sb700/lpc.c deleted file mode 100644 index 5d6d1cd85a..0000000000 --- a/src/southbridge/amd/sb700/lpc.c +++ /dev/null @@ -1,292 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2010 Advanced Micro Devices, Inc. - * Copyright (C) 2015 Timothy Pearson , Raptor Engineering - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include "sb700.h" - -static void lpc_init(struct device *dev) -{ - u8 byte; - u32 dword; - struct device *sm_dev; - - printk(BIOS_SPEW, "%s\n", __func__); - - /* Enable the LPC Controller */ - sm_dev = pcidev_on_root(0x14, 0); - dword = pci_read_config32(sm_dev, 0x64); - dword |= 1 << 20; - pci_write_config32(sm_dev, 0x64, dword); - - /* Initialize isa dma */ -#if CONFIG(SOUTHBRIDGE_AMD_SB700_SKIP_ISA_DMA_INIT) - printk(BIOS_DEBUG, "Skipping isa_dma_init() to avoid getting stuck.\n"); -#else - isa_dma_init(); -#endif - - if (!CONFIG(SOUTHBRIDGE_AMD_SB700_DISABLE_ISA_DMA)) { - /* Enable DMA transaction on the LPC bus */ - byte = pci_read_config8(dev, 0x40); - byte |= (1 << 2); - pci_write_config8(dev, 0x40, byte); - } - - /* Disable the timeout mechanism on LPC */ - byte = pci_read_config8(dev, 0x48); - byte &= ~(1 << 7); - pci_write_config8(dev, 0x48, byte); - - /* Disable LPC MSI Capability */ - byte = pci_read_config8(dev, 0x78); - byte &= ~(1 << 1); -#if CONFIG(SOUTHBRIDGE_AMD_SUBTYPE_SP5100) - /* Disable FlowContrl, Always service the request from Host - * whenever there is a request from Host pending - */ - byte &= ~(1 << 0); -#endif - pci_write_config8(dev, 0x78, byte); - - cmos_check_update_date(); - - setup_i8259(); /* Initialize i8259 pic */ - setup_i8254(); /* Initialize i8254 timers */ -} - -static void sb700_lpc_read_resources(struct device *dev) -{ - struct resource *res; - - /* Get the normal pci resources of this device */ - pci_dev_read_resources(dev); /* We got one for APIC, or one more for TRAP */ - - pci_get_resource(dev, 0xA0); /* SPI ROM base address */ - - /* Add an extra subtractive resource for both memory and I/O. */ - res = new_resource(dev, IOINDEX_SUBTRACTIVE(0, 0)); - res->base = 0; - res->size = 0x1000; - res->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE | - IORESOURCE_ASSIGNED | IORESOURCE_FIXED; - - res = new_resource(dev, IOINDEX_SUBTRACTIVE(1, 0)); - res->base = 0xff800000; - res->size = 0x00800000; /* 8 MB for flash */ - res->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE | - IORESOURCE_ASSIGNED | IORESOURCE_FIXED; - - res = new_resource(dev, 3); /* IOAPIC */ - res->base = IO_APIC_ADDR; - res->size = 0x00001000; - res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; - - compact_resources(dev); -} - -static void sb700_lpc_set_resources(struct device *dev) -{ - struct resource *res; - - pci_dev_set_resources(dev); - - /* Special case. SPI Base Address. The SpiRomEnable should be set. */ - res = find_resource(dev, 0xA0); - pci_write_config32(dev, 0xA0, res->base | 1 << 1); -} - -/** - * @brief Enable resources for children devices - * - * @param dev the device whose children's resources are to be enabled - * - */ -static void sb700_lpc_enable_childrens_resources(struct device *dev) -{ - struct bus *link; - u32 reg, reg_x; - int var_num = 0; - u16 reg_var[3] = {0x0, 0x0, 0x0}; - u8 wiosize = pci_read_config8(dev, 0x74); - - reg = pci_read_config32(dev, 0x44); - reg_x = pci_read_config32(dev, 0x48); - - for (link = dev->link_list; link; link = link->next) { - struct device *child; - for (child = link->children; child; - child = child->sibling) { - if (!(child->enabled - && (child->path.type == DEVICE_PATH_PNP))) - continue; - - struct resource *res; - for (res = child->resource_list; res; res = res->next) { - u32 base, end; /* don't need long long */ - if (!(res->flags & IORESOURCE_IO)) - continue; - base = res->base; - end = resource_end(res); - printk(BIOS_DEBUG, "sb700 lpc decode:%s," - " base=0x%08x, end=0x%08x\n", - dev_path(child), base, end); - switch (base) { - case 0x60: /* KB */ - case 0x64: /* MS */ - reg |= (1 << 29); - break; - case 0x3f8: /* COM1 */ - reg |= (1 << 6); - break; - case 0x2f8: /* COM2 */ - reg |= (1 << 7); - break; - case 0x378: /* Parallel 1 */ - reg |= (1 << 0); - reg |= (1 << 1); /* + 0x778 for ECP */ - break; - case 0x3f0: /* FD0 */ - reg |= (1 << 26); - break; - case 0x220: /* Audio 0 */ - reg |= (1 << 8); - break; - case 0x300: /* Midi 0 */ - reg |= (1 << 18); - break; - case 0x400: - reg_x |= (1 << 16); - break; - case 0x480: - reg_x |= (1 << 17); - break; - case 0x500: - reg_x |= (1 << 18); - break; - case 0x580: - reg_x |= (1 << 19); - break; - case 0x4700: - reg_x |= (1 << 22); - break; - case 0xfd60: - reg_x |= (1 << 23); - break; - default: - /* only 3 var ; compact them ? */ - if (var_num >= 3) - continue; - switch (var_num) { - case 0: - reg_x |= (1 << 2); - if ((end - base) < 16) - wiosize |= (1 << 0); - break; - case 1: - reg_x |= (1 << 24); - if ((end - base) < 16) - wiosize |= (1 << 2); - break; - case 2: - reg_x |= (1 << 25); - reg_x |= (1 << 24); - if ((end - base) < 16) - wiosize |= (1 << 3); - break; - } - reg_var[var_num++] = base & 0xffff; - } - } - } - } - pci_write_config32(dev, 0x44, reg); - pci_write_config32(dev, 0x48, reg_x); - /* Set WideIO for as many IOs found (fall through is on purpose) */ - switch (var_num) { - case 3: - pci_write_config16(dev, 0x90, reg_var[2]); - /* fall through */ - case 2: - pci_write_config16(dev, 0x66, reg_var[1]); - /* fall through */ - case 1: - pci_write_config16(dev, 0x64, reg_var[0]); - break; - } - pci_write_config8(dev, 0x74, wiosize); -} - -static void sb700_lpc_enable_resources(struct device *dev) -{ - pci_dev_enable_resources(dev); - sb700_lpc_enable_childrens_resources(dev); -} - -#if CONFIG(HAVE_ACPI_TABLES) - -static void southbridge_acpi_fill_ssdt_generator(struct device *device) { - amd_generate_powernow(ACPI_CPU_CONTROL, 6, 1); -} - -static const char *lpc_acpi_name(const struct device *dev) -{ - if (dev->path.type != DEVICE_PATH_PCI) - return NULL; - - switch (dev->path.pci.devfn) { - case PCI_DEVFN(0x14, 3): - return "LPC"; - } - - return NULL; -} -#endif - - -static struct pci_operations lops_pci = { - .set_subsystem = pci_dev_set_subsystem, -}; - -static struct device_operations lpc_ops = { - .read_resources = sb700_lpc_read_resources, - .set_resources = sb700_lpc_set_resources, - .enable_resources = sb700_lpc_enable_resources, -#if CONFIG(HAVE_ACPI_TABLES) - .acpi_name = lpc_acpi_name, - .write_acpi_tables = acpi_write_hpet, - .acpi_fill_ssdt_generator = southbridge_acpi_fill_ssdt_generator, -#endif - .init = lpc_init, - .scan_bus = scan_static_bus, - .ops_pci = &lops_pci, -}; -static const struct pci_driver lpc_driver __pci_driver = { - .ops = &lpc_ops, - .vendor = PCI_VENDOR_ID_ATI, - .device = PCI_DEVICE_ID_ATI_SB700_LPC, -}; diff --git a/src/southbridge/amd/sb700/pci.c b/src/southbridge/amd/sb700/pci.c deleted file mode 100644 index b3c71569c7..0000000000 --- a/src/southbridge/amd/sb700/pci.c +++ /dev/null @@ -1,123 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2010 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include -#include -#include "sb700.h" - -static void pci_init(struct device *dev) -{ - u32 dword; - u16 word; - u8 byte; - - /* RPR 5.1 Enables the PCI-bridge subtractive decode */ - /* This setting is strongly recommended since it supports some legacy PCI add-on cards,such as BIOS debug cards */ - byte = pci_read_config8(dev, 0x4B); - byte |= 1 << 7; - pci_write_config8(dev, 0x4B, byte); - byte = pci_read_config8(dev, 0x40); - byte |= 1 << 5; - pci_write_config8(dev, 0x40, byte); - - /* RPR5.2 PCI-bridge upstream dual address window */ - /* this setting is applicable if the system memory is more than 4GB,and the PCI device can support dual address access */ - byte = pci_read_config8(dev, 0x50); - byte |= 1 << 0; - pci_write_config8(dev, 0x50, byte); - - /* RPR 5.3 PCI bus 64-byte DMA read access */ - /* Enhance the PCI bus DMA performance */ - byte = pci_read_config8(dev, 0x4B); - byte |= 1 << 4; - pci_write_config8(dev, 0x4B, byte); - - /* RPR 5.4 Enables the PCIB writes to be cacheline aligned. */ - /* The size of the writes will be set in the Cacheline Register */ - byte = pci_read_config8(dev, 0x40); - byte |= 1 << 1; - pci_write_config8(dev, 0x40, byte); - - /* RPR 5.5 Enables the PCIB to retain ownership of the bus on the Primary side and on the Secondary side when GNT# is deasserted */ - pci_write_config8(dev, 0x0D, 0x40); - pci_write_config8(dev, 0x1B, 0x40); - - /* RPR 5.6 Enable the command matching checking function on "Memory Read" & "Memory Read Line" commands */ - byte = pci_read_config8(dev, 0x4B); - byte |= 1 << 6; - pci_write_config8(dev, 0x4B, byte); - - /* RPR 5.7 When enabled, the PCI arbiter checks for the Bus Idle before asserting GNT# */ - byte = pci_read_config8(dev, 0x4B); - byte |= 1 << 0; - pci_write_config8(dev, 0x4B, byte); - - /* RPR 5.8 Adjusts the GNT# de-assertion time */ - word = pci_read_config16(dev, 0x64); - word |= 1 << 12; - pci_write_config16(dev, 0x64, word); - - /* RPR 5.9 Fast Back to Back transactions support */ - byte = pci_read_config8(dev, 0x48); - byte |= 1 << 2; - /* pci_write_config8(dev, 0x48, byte); */ - - /* RPR 5.10 Enable Lock Operation */ - /* byte = pci_read_config8(dev, 0x48); */ - byte |= 1 << 3; - pci_write_config8(dev, 0x48, byte); - - /* RPR 5.11 Enable additional optional PCI clock */ - word = pci_read_config16(dev, 0x64); - word |= 1 << 8; - pci_write_config16(dev, 0x64, word); - - /* RPR 5.12 Enable One-Prefetch-Channel Mode */ - dword = pci_read_config32(dev, 0x64); - dword |= 1 << 20; - pci_write_config32(dev, 0x64, dword); - - /* RPR 5.13 Disable PCIB MSI Capability */ - byte = pci_read_config8(dev, 0x40); - byte &= ~(1 << 3); - pci_write_config8(dev, 0x40, byte); - - /* rpr5.14 Adjusting CLKRUN# */ - dword = pci_read_config32(dev, 0x64); - dword |= (1 << 15); - pci_write_config32(dev, 0x64, dword); -} - -static struct pci_operations lops_pci = { - .set_subsystem = 0, -}; - -static struct device_operations pci_ops = { - .read_resources = pci_bus_read_resources, - .set_resources = pci_dev_set_resources, - .enable_resources = pci_bus_enable_resources, - .init = pci_init, - .scan_bus = pci_scan_bridge, - .reset_bus = pci_bus_reset, - .ops_pci = &lops_pci, -}; - -static const struct pci_driver pci_driver __pci_driver = { - .ops = &pci_ops, - .vendor = PCI_VENDOR_ID_ATI, - .device = PCI_DEVICE_ID_ATI_SB700_PCI, -}; diff --git a/src/southbridge/amd/sb700/pmio.c b/src/southbridge/amd/sb700/pmio.c deleted file mode 100644 index 12cc2c223e..0000000000 --- a/src/southbridge/amd/sb700/pmio.c +++ /dev/null @@ -1,50 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - - -#include /*inb, outb*/ -#include "pmio.h" - -static void pmio_write_index(u16 port_base, u8 reg, u8 value) -{ - outb(reg, port_base); - outb(value, port_base + 1); -} - -static u8 pmio_read_index(u16 port_base, u8 reg) -{ - outb(reg, port_base); - return inb(port_base + 1); -} - -void pm_iowrite(u8 reg, u8 value) -{ - pmio_write_index(PM_INDEX, reg, value); -} - -u8 pm_ioread(u8 reg) -{ - return pmio_read_index(PM_INDEX, reg); -} - -void pm2_iowrite(u8 reg, u8 value) -{ - pmio_write_index(PM2_INDEX, reg, value); -} - -u8 pm2_ioread(u8 reg) -{ - return pmio_read_index(PM2_INDEX, reg); -} diff --git a/src/southbridge/amd/sb700/pmio.h b/src/southbridge/amd/sb700/pmio.h deleted file mode 100644 index ed38eed569..0000000000 --- a/src/southbridge/amd/sb700/pmio.h +++ /dev/null @@ -1,30 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - - -#ifndef _PMIO_H_ -#define _PMIO_H_ - -#define PM_INDEX 0xCD6 -#define PM_DATA 0xCD7 -#define PM2_INDEX 0xCD0 -#define PM2_DATA 0xCD1 - -void pm_iowrite(u8 reg, u8 value); -u8 pm_ioread(u8 reg); -void pm2_iowrite(u8 reg, u8 value); -u8 pm2_ioread(u8 reg); - -#endif diff --git a/src/southbridge/amd/sb700/ramtop.c b/src/southbridge/amd/sb700/ramtop.c deleted file mode 100644 index 4d261210fe..0000000000 --- a/src/southbridge/amd/sb700/ramtop.c +++ /dev/null @@ -1,51 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2010 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include -#include -#include "sb700.h" - -int acpi_get_sleep_type(void) -{ - u16 tmp; - tmp = inw(ACPI_PM1_CNT_BLK); - return ((tmp & (7 << 10)) >> 10); -} - -void backup_top_of_low_cacheable(uintptr_t ramtop) -{ - u32 dword = (u32) ramtop; - int nvram_pos = 0xfc, i; - for (i = 0; i < 4; i++) { - outb(nvram_pos, BIOSRAM_INDEX); - outb((dword >> (8 * i)) & 0xff, BIOSRAM_DATA); - nvram_pos++; - } -} - -uintptr_t restore_top_of_low_cacheable(void) -{ - uint32_t xdata = 0; - int xnvram_pos = 0xfc, xi; - for (xi = 0; xi < 4; xi++) { - outb(xnvram_pos, BIOSRAM_INDEX); - xdata &= ~(0xff << (xi * 8)); - xdata |= inb(BIOSRAM_DATA) << (xi *8); - xnvram_pos++; - } - return xdata; -} diff --git a/src/southbridge/amd/sb700/reset.c b/src/southbridge/amd/sb700/reset.c deleted file mode 100644 index 9a04459799..0000000000 --- a/src/southbridge/amd/sb700/reset.c +++ /dev/null @@ -1,66 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2010 - 2011 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -// Use simple device model for this file even in ramstage -#define __SIMPLE_DEVICE__ - -#include -#include -#include -#include - -#define HT_INIT_CONTROL 0x6C -#define HTIC_BIOSR_Detect (1<<5) - -#if CONFIG_MAX_PHYSICAL_CPUS > 32 -#define NODE_PCI(x, fn) ((x < 32)?(PCI_DEV(CONFIG_CBB,(CONFIG_CDB+x),fn)):(PCI_DEV((CONFIG_CBB-1),(CONFIG_CDB+x-32),fn))) -#else -#define NODE_PCI(x, fn) PCI_DEV(CONFIG_CBB,(CONFIG_CDB+x),fn) -#endif - -static void set_bios_reset(void) -{ - u32 nodes; - u32 htic; - pci_devfn_t dev; - int i; - - nodes = ((pci_read_config32(PCI_DEV(CONFIG_CBB, CONFIG_CDB, 0), 0x60) >> 4) & 7) + 1; - for (i = 0; i < nodes; i++) { - dev = NODE_PCI(i, 0); - htic = pci_read_config32(dev, HT_INIT_CONTROL); - htic &= ~HTIC_BIOSR_Detect; - pci_write_config32(dev, HT_INIT_CONTROL, htic); - } -} - -void do_board_reset(void) -{ - set_bios_reset(); - - /* Try rebooting through port 0xcf9 */ - /* Actually it is not a real hard_reset - * --- it only reset coherent link table, but not reset link freq and width - */ - outb((0 << 3) | (0 << 2) | (1 << 1), 0xcf9); - outb((0 << 3) | (1 << 2) | (1 << 1), 0xcf9); -} - -void do_soft_reset(void) -{ - set_bios_reset(); - /* link reset */ - outb(0x06, 0x0cf9); -} diff --git a/src/southbridge/amd/sb700/sata.c b/src/southbridge/amd/sb700/sata.c deleted file mode 100644 index 292a7f2c9e..0000000000 --- a/src/southbridge/amd/sb700/sata.c +++ /dev/null @@ -1,555 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2010 Advanced Micro Devices, Inc. - * Copyright (C) 2015 Timothy Pearson , Raptor Engineering - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include "sb700.h" - -static int sata_drive_detect(int portnum, uint16_t iobar) -{ - u8 byte, byte2; - u8 byte_prev, byte2_prev; - int i = 0; - byte_prev = byte2_prev = 0; - outb(0xa0 + 0x10 * (portnum % 2), iobar + 0x6); - while (byte = inb(iobar + 0x6), byte2 = inb(iobar + 0x7), - (byte != (0xa0 + 0x10 * (portnum % 2))) || - ((byte2 & 0x88) != 0)) { - if ((byte != byte_prev) || (byte2 != byte2_prev)) - printk(BIOS_SPEW, "0x6=%x, 0x7=%x\n", byte, byte2); - if (byte != (0xa0 + 0x10 * (portnum % 2))) { - /* This will happen at the first iteration of this loop - * if the first SATA port is unpopulated and the - * second SATA port is populated. - */ - printk(BIOS_DEBUG, "drive no longer selected after %i ms, " - "retrying init\n", i * 10); - return 1; - } else { - if (i == 0) - printk(BIOS_SPEW, "drive detection not yet completed, " - "waiting...\n"); - } - mdelay(10); - i++; - byte_prev = byte; - byte2_prev = byte2; - - /* Detect stuck SATA controller and attempt reset */ - if (i > 1024) { - printk(BIOS_DEBUG, "drive detection not done after %i ms, " - "resetting HBA and retrying init\n", i * 10); - return 2; - } - } - printk(BIOS_SPEW, "drive detection done after %i ms\n", i * 10); - return 0; -} - -/* This function can be overloaded in mainboard.c */ -void __weak sb7xx_51xx_setup_sata_phys(struct device *dev) -{ - /* RPR7.6.1 Program the PHY Global Control to 0x2C00 */ - pci_write_config16(dev, 0x86, 0x2c00); - - /* RPR7.6.2 SATA GENI PHY ports setting */ - pci_write_config32(dev, 0x88, 0x01B48017); - pci_write_config32(dev, 0x8c, 0x01B48019); - pci_write_config32(dev, 0x90, 0x01B48016); - pci_write_config32(dev, 0x94, 0x01B48016); - pci_write_config32(dev, 0x98, 0x01B48016); - pci_write_config32(dev, 0x9c, 0x01B48016); - - /* RPR7.6.3 SATA GEN II PHY port setting for port [0~5]. */ - pci_write_config16(dev, 0xa0, 0xA09A); - pci_write_config16(dev, 0xa2, 0xA09F); - pci_write_config16(dev, 0xa4, 0xA07A); - pci_write_config16(dev, 0xa6, 0xA07A); - pci_write_config16(dev, 0xa8, 0xA07A); - pci_write_config16(dev, 0xaa, 0xA07A); -} - -/* This function can be overloaded in mainboard.c */ -void __weak sb7xx_51xx_setup_sata_port_indication(void *sata_bar5) -{ - uint32_t dword; - - /* RPR7.9 Program Port Indication Registers */ - dword = read32(sata_bar5 + 0xf8); - dword &= ~(0x3f << 12); /* Ports 0 and 1 are eSATA */ - dword |= (0x3 << 12); - dword &= ~0x3f; - write32(sata_bar5 + 0xf8, dword); - - dword = read32(sata_bar5 + 0xfc); - dword |= 0x1 << 20; /* At least one eSATA port is present */ - write32(sata_bar5 + 0xfc, dword); -} - -static void sata_init(struct device *dev) -{ - u8 byte; - u16 word; - u32 dword; - u8 rev_id; - void *sata_bar5; - uint16_t sata_bar0, sata_bar1, sata_bar2, sata_bar3, sata_bar4; - uint16_t ide_bar0, ide_bar1, ide_bar2, ide_bar3; - uint16_t current_bar; - int i, j, ret; - uint8_t nvram; - uint8_t sata_ahci_mode; - uint8_t sata_alpm_enable; - uint8_t port_count; - uint8_t max_port_count; - uint8_t ide_io_enabled; - uint8_t ide_legacy_io_enabled; - - sata_ahci_mode = 0; - if (get_option(&nvram, "sata_ahci_mode") == CB_SUCCESS) - sata_ahci_mode = !!nvram; - - sata_alpm_enable = 0; - if (get_option(&nvram, "sata_alpm") == CB_SUCCESS) - sata_alpm_enable = !!nvram; - - struct device *sm_dev; - /* SATA SMBus Disable */ - sm_dev = pcidev_on_root(0x14, 0); - - /* WARNING - * Enabling the SATA link latency enhancement (SMBUS 0xAD bit 5) - * causes random persistent drive detection failures until it is cleared, - * with the probabability of detection failure rising exponentially with - * the number of drives attached to the controller! - * This happens on Rev15 H/W. - * Do NOT follow the RPR advice; leave this bit set at all times... - */ - byte = pci_read_config8(sm_dev, 0xad); - /* Disable SATA SMBUS */ - byte |= (1 << 1); - /* Enable SATA and power saving */ - byte |= (1 << 0); - /* Disable link latency enhancement */ - byte |= (1 << 5); - pci_write_config8(sm_dev, 0xad, byte); - - /* Take the PHY logic out of reset */ - word = pci_read_config16(dev, 0x84); - word |= 0x1 << 2; - word &= ~0x1f8; - pci_write_config16(dev, 0x84, word); - - /* get rev_id */ - rev_id = pci_read_config8(sm_dev, 0x08) - 0x28; - - printk(BIOS_SPEW, "rev_id=%x\n", rev_id); - - /* Enable combined mode */ - byte = pci_read_config8(sm_dev, 0xad); - byte |= (1 << 3); - pci_write_config8(sm_dev, 0xad, byte); - - struct device *ide_dev; - /* IDE Device */ - ide_dev = pcidev_on_root(0x14, 1); - - /* Disable legacy IDE mode (enable PATA_BAR0/2) */ - byte = pci_read_config8(ide_dev, 0x09); - ide_legacy_io_enabled = !(byte & 0x1); - byte |= 0x1; - pci_write_config8(ide_dev, 0x09, byte); - - /* Enable IDE I/O access (enable PATA_BAR0/2) */ - byte = pci_read_config8(ide_dev, 0x04); - ide_io_enabled = byte & 0x1; - byte |= 0x1; - pci_write_config8(ide_dev, 0x04, byte); - - /* RPR 7.2 SATA Initialization */ - /* Set the interrupt Mapping to INTG# */ - byte = pci_read_config8(sm_dev, 0xaf); - byte = 0x6 << 2; - pci_write_config8(sm_dev, 0xaf, byte); - - /* get base address */ - sata_bar5 = (void *)(pci_read_config32(dev, 0x24) & ~0x3FF); - sata_bar0 = pci_read_config16(dev, 0x10) & ~0x7; - sata_bar1 = pci_read_config16(dev, 0x14) & ~0x3; - sata_bar2 = pci_read_config16(dev, 0x18) & ~0x7; - sata_bar3 = pci_read_config16(dev, 0x1c) & ~0x3; - sata_bar4 = pci_read_config16(dev, 0x20) & ~0xf; - - printk(BIOS_SPEW, "sata_bar0=%x\n", sata_bar0); /* 3030 */ - printk(BIOS_SPEW, "sata_bar1=%x\n", sata_bar1); /* 3070 */ - printk(BIOS_SPEW, "sata_bar2=%x\n", sata_bar2); /* 3040 */ - printk(BIOS_SPEW, "sata_bar3=%x\n", sata_bar3); /* 3080 */ - printk(BIOS_SPEW, "sata_bar4=%x\n", sata_bar4); /* 3000 */ - printk(BIOS_SPEW, "sata_bar5=%p\n", sata_bar5); /* e0309000 */ - - ide_bar0 = pci_read_config16(ide_dev, 0x10) & ~0x7; - ide_bar1 = pci_read_config16(ide_dev, 0x14) & ~0x3; - ide_bar2 = pci_read_config16(ide_dev, 0x18) & ~0x7; - ide_bar3 = pci_read_config16(ide_dev, 0x1c) & ~0x3; - printk(BIOS_SPEW, "ide_bar0=%x\n", ide_bar0); - printk(BIOS_SPEW, "ide_bar1=%x\n", ide_bar1); - printk(BIOS_SPEW, "ide_bar2=%x\n", ide_bar2); - printk(BIOS_SPEW, "ide_bar3=%x\n", ide_bar3); - - /* Program the Subsystem ID/VID to 0x43801002 */ - dword = 0x43801002; - pci_write_config32(dev, 0x2c, dword); - - /* SERR-Enable */ - word = pci_read_config16(dev, 0x04); - word |= (1 << 8); - pci_write_config16(dev, 0x04, word); - - /* Dynamic power saving */ - byte = pci_read_config8(dev, 0x40); - byte |= (1 << 2); - pci_write_config8(dev, 0x40, byte); - - /* Unlock subclass and certain BAR R/O registers */ - byte = pci_read_config8(dev, 0x40); - byte |= (1 << 0); - pci_write_config8(dev, 0x40, byte); - - /* Disable AHCI enhancement (AMD SP5100 RPR page 54) */ - dword = pci_read_config32(dev, 0x40); - dword |= (1 << 23); - pci_write_config32(dev, 0x40, dword); - - if (sata_ahci_mode) { - /* Force number of ports to 6 - * NOTE: This is not documented in the register - * reference guide, but CIMX needs to do this - * to activate all 6 ports when IDE is disabled. - */ - dword = read32(sata_bar5 + 0x00); - dword &= ~0x7; - dword |= 0x5; - write32(sata_bar5 + 0x00, dword); - } else { - /* Set SATA Operation Mode, Set to IDE mode */ - byte = pci_read_config8(dev, 0x40); - byte |= (1 << 4); - pci_write_config8(dev, 0x40, byte); - - dword = 0x01018f00; - pci_write_config32(dev, 0x8, dword); - } - - /* Get maximum number of ports */ - max_port_count = read32(sata_bar5 + 0x00) & 0x1f; - max_port_count++; - printk(BIOS_SPEW, "Maximum SATA port count supported by silicon: %d\n", max_port_count); - - /* Set number of ports */ - dword = CONFIG_SOUTHBRIDGE_AMD_SB700_SATA_PORT_COUNT_BITFIELD; - for (i = max_port_count; i < 32; i++) - dword &= ~(0x1 << i); - write32(sata_bar5 + 0x0c, dword); - - /* Disable ALPM if ALPM support not requested */ - if (!sata_alpm_enable) { - dword = read32(sata_bar5 + 0xfc); - dword &= ~(0x1 << 11); /* Disable ALPM */ - write32(sata_bar5 + 0xfc, dword); - } - - /* Enable SATA ports */ - byte = pci_read_config8(dev, 0x42); - if (max_port_count <= 6) { - byte |= 0x3f; - for (i = 0; i < max_port_count; i++) - byte &= ~(0x1 << i); - } else { - byte &= ~0x3f; - } - pci_write_config8(dev, 0x42, byte); - - if (sata_ahci_mode) { - /* FIXME - * SeaBIOS does not know how to spin - * up the drives and therefore hangs - * in AHCI init if this is enabled... - */ - /* Enable staggered spin-up */ - dword = read32(sata_bar5 + 0x00); -#if 0 - dword |= 0x1 << 27; -#else - dword &= ~(0x1 << 27); -#endif - write32(sata_bar5 + 0x00, dword); - - /* Reset the HBA to avoid stuck drives in SeaBIOS */ - dword = read32(sata_bar5 + 0x04); - dword |= 0x1; - write32(sata_bar5 + 0x04, dword); - } - - sb7xx_51xx_setup_sata_phys(dev); - sb7xx_51xx_setup_sata_port_indication(sata_bar5); - - /* Write protect Sub-Class Code */ - byte = pci_read_config8(dev, 0x40); - byte &= ~(1 << 0); - pci_write_config8(dev, 0x40, byte); - - /* Enable the SATA watchdog counter */ - byte = pci_read_config8(dev, 0x44); - byte |= (1 << 0); - pci_write_config8(dev, 0x44, byte); - - /* Set bit 29 and 24 for A12 */ - dword = pci_read_config32(dev, 0x40); - if (rev_id < 0x14) /* before A12 */ - dword |= (1 << 29); - else - dword &= ~(1 << 29); /* A14 and above */ - pci_write_config32(dev, 0x40, dword); - - /* set bit 21 for A12 */ - dword = pci_read_config32(dev, 0x48); - if (rev_id < 0x14) /* before A12 */ - dword |= 1 << 24 | 1 << 21; - else { - dword &= ~(1 << 24 | 1 << 21); /* A14 and above */ - dword &= ~0xFF80; /* 15:7 */ - dword |= 1 << 15 | 0x7F << 7 | 1 << 6; - } - pci_write_config32(dev, 0x48, dword); - - /* Program the watchdog counter to 0x10 */ - byte = 0x10; - pci_write_config8(dev, 0x46, byte); - - /* Enable the I/O, MM, BusMaster access for SATA */ - byte = pci_read_config8(dev, 0x4); - byte |= 7 << 0; - pci_write_config8(dev, 0x4, byte); - -#if CONFIG(SOUTHBRIDGE_AMD_SUBTYPE_SP5100) - /* Master Latency Timer */ - pci_write_config32(dev, 0xC, 0x00004000); -#endif - - /* Determine port count */ - port_count = 0; - for (i = 0; i < 32; i++) { - if (CONFIG_SOUTHBRIDGE_AMD_SB700_SATA_PORT_COUNT_BITFIELD & (0x1 << i)) - port_count = i; - } - port_count++; - if (port_count > max_port_count) - port_count = max_port_count; - - /* Send COMRESET to all ports */ - for (i = 0; i < port_count; i++) { - /* Read in Port-N Serial ATA Control Register */ - byte = read8(sata_bar5 + 0x12C + 0x80 * i); - - /* Set Reset Bit */ - byte |= 0x1; - write8((sata_bar5 + 0x12C + 0x80 * i), byte); - - /* Wait 1ms */ - mdelay(1); - - /* Clear Reset Bit */ - byte &= ~0x01; - write8((sata_bar5 + 0x12C + 0x80 * i), byte); - - /* Wait 1ms */ - mdelay(1); - } - - /* RPR7.7 SATA drive detection. */ - /* Use BAR5+0x128,BAR0 for Primary Slave */ - /* Use BAR5+0x1A8,BAR0 for Primary Slave */ - /* Use BAR5+0x228,BAR2 for Secondary Master */ - /* Use BAR5+0x2A8,BAR2 for Secondary Slave */ - /* Use BAR5+0x328,PATA_BAR0/2 for Primary/Secondary Master emulation */ - /* Use BAR5+0x3A8,PATA_BAR0/2 for Primary/Secondary Slave emulation */ - for (i = 0; i < port_count; i++) { - byte = read8(sata_bar5 + 0x128 + 0x80 * i); - printk(BIOS_SPEW, "SATA port %i status = %x\n", i, byte); - byte &= 0xF; - if (byte == 0x1) { - /* If the drive status is 0x1 then we see it but we aren't talking to it. */ - /* Try to do something about it. */ - printk(BIOS_SPEW, "SATA device detected but not talking. Trying lower speed.\n"); - - /* Read in Port-N Serial ATA Control Register */ - byte = read8(sata_bar5 + 0x12C + 0x80 * i); - - /* Set Reset Bit and 1.5g bit */ - byte |= 0x11; - write8((sata_bar5 + 0x12C + 0x80 * i), byte); - - /* Wait 1ms */ - mdelay(1); - - /* Clear Reset Bit */ - byte &= ~0x01; - write8((sata_bar5 + 0x12C + 0x80 * i), byte); - - /* Wait 1ms */ - mdelay(1); - - /* Reread status */ - byte = read8(sata_bar5 + 0x128 + 0x80 * i); - printk(BIOS_SPEW, "SATA port %i status = %x\n", i, byte); - byte &= 0xF; - } - - if (byte == 0x3) { - for (j = 0; j < 10; j++) { - if (i < 4) - current_bar = ((i / 2) == 0) ? sata_bar0 : sata_bar2; - else - current_bar = (pci_read_config8(sm_dev, 0xad) & (0x1 << 4)) - ? ide_bar2 : ide_bar0; - ret = sata_drive_detect(i, current_bar); - if (ret == 0) { - break; - } else if (ret == 2) { - /* Read in Port-N Serial ATA Control Register */ - byte = read8(sata_bar5 + 0x12C + 0x80 * i); - - /* Set Reset Bit */ - byte |= 0x1; - write8((sata_bar5 + 0x12C + 0x80 * i), byte); - - /* Wait 1000ms */ - mdelay(1000); - - /* Clear Reset Bit */ - byte &= ~0x01; - write8((sata_bar5 + 0x12C + 0x80 * i), byte); - - /* Wait 1ms */ - mdelay(1); - } - } - if (sata_ahci_mode) - printk(BIOS_DEBUG, "AHCI device %d is %sready after %i tries\n", - i, - (j == 10) ? "not " : "", - (j == 10) ? j : j + 1); - else - printk(BIOS_DEBUG, "%s %s device is %sready after %i tries\n", - (i / 2) ? "Secondary" : "Primary", - (i % 2) ? "Slave" : "Master", - (j == 10) ? "not " : "", - (j == 10) ? j : j + 1); - } else { - if (sata_ahci_mode) - printk(BIOS_DEBUG, "No AHCI SATA drive on Slot%i\n", i); - else - printk(BIOS_DEBUG, "No %s %s SATA drive on Slot%i\n", - (i / 2) ? "Secondary" : "Primary", - (i % 2) ? "Slave" : "Master", i); - } - } - - /* Restore IDE I/O access */ - if (!ide_io_enabled) { - byte = pci_read_config8(ide_dev, 0x04); - byte &= ~0x1; - pci_write_config8(ide_dev, 0x04, byte); - } - - /* Re-enable legacy IDE mode */ - if (ide_legacy_io_enabled) { - byte = pci_read_config8(ide_dev, 0x09); - byte &= ~0x1; - pci_write_config8(ide_dev, 0x09, byte); - } - - /* Below is CIM InitSataLateFar */ - if (sata_ahci_mode) { - /* Disable combined mode */ - byte = pci_read_config8(sm_dev, 0xad); - byte &= ~(1 << 3); - pci_write_config8(sm_dev, 0xad, byte); - } else { - /* Enable interrupts from the HBA */ - byte = read8(sata_bar5 + 0x4); - byte |= 1 << 1; - write8((sata_bar5 + 0x4), byte); - } - - /* Clear error status */ - write32((sata_bar5 + 0x130), 0xFFFFFFFF); - write32((sata_bar5 + 0x1b0), 0xFFFFFFFF); - write32((sata_bar5 + 0x230), 0xFFFFFFFF); - write32((sata_bar5 + 0x2b0), 0xFFFFFFFF); - write32((sata_bar5 + 0x330), 0xFFFFFFFF); - write32((sata_bar5 + 0x3b0), 0xFFFFFFFF); - - /* Clear SATA status,Firstly we get the AcpiGpe0BlkAddr */ - /* ????? why CIM does not set the AcpiGpe0BlkAddr, but use it??? */ - - /* word = 0x0000; */ - /* word = pm_ioread(0x28); */ - /* byte = pm_ioread(0x29); */ - /* word |= byte<<8; */ - /* printk(BIOS_DEBUG, "AcpiGpe0Blk addr = %x\n", word); */ - /* write32(word, 0x80000000); */ -} - -static struct pci_operations lops_pci = { - .set_subsystem = pci_dev_set_subsystem, -}; - -static struct device_operations sata_ops = { - .read_resources = pci_dev_read_resources, - .set_resources = pci_dev_set_resources, - .enable_resources = pci_dev_enable_resources, - .init = sata_init, - .scan_bus = 0, - .ops_pci = &lops_pci, -}; - -static const struct pci_driver sata0_driver __pci_driver = { - .ops = &sata_ops, - .vendor = PCI_VENDOR_ID_ATI, - .device = PCI_DEVICE_ID_ATI_SB700_SATA, -}; - -static const struct pci_driver sata1_driver __pci_driver = { - .ops = &sata_ops, - .vendor = PCI_VENDOR_ID_ATI, - .device = PCI_DEVICE_ID_ATI_SB700_SATA_AHCI, -}; - -static const struct pci_driver sata2_driver __pci_driver = { - .ops = &sata_ops, - .vendor = PCI_VENDOR_ID_ATI, - .device = PCI_DEVICE_ID_ATI_SB700_SATA_AHCI_AMD, -}; diff --git a/src/southbridge/amd/sb700/sb700.c b/src/southbridge/amd/sb700/sb700.c deleted file mode 100644 index 1eaf347dcc..0000000000 --- a/src/southbridge/amd/sb700/sb700.c +++ /dev/null @@ -1,227 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2010 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include - -#include - -#include -#include -#include -#include -#include "sb700.h" -#include "chip.h" - -static struct device *find_sm_dev(struct device *dev, u32 devfn) -{ - struct device *sm_dev; - - sm_dev = pcidev_path_behind(dev->bus, devfn); - if (!sm_dev) - return sm_dev; - - if ((sm_dev->vendor != PCI_VENDOR_ID_ATI) || - ((sm_dev->device != PCI_DEVICE_ID_ATI_SB700_SM))) { - u32 id; - id = pci_read_config32(sm_dev, PCI_VENDOR_ID); - if ((id != - (PCI_VENDOR_ID_ATI | (PCI_DEVICE_ID_ATI_SB700_SM << 16)))) - { - sm_dev = 0; - } - } - - return sm_dev; -} - -void set_sm_enable_bits(struct device *sm_dev, u32 reg_pos, u32 mask, u32 val) -{ - u32 reg_old, reg; - reg = reg_old = pci_read_config32(sm_dev, reg_pos); - reg &= ~mask; - reg |= val; - if (reg != reg_old) { - pci_write_config32(sm_dev, reg_pos, reg); - } -} - -static void pmio_write_index(u16 port_base, u8 reg, u8 value) -{ - outb(reg, port_base); - outb(value, port_base + 1); -} - -static u8 pmio_read_index(u16 port_base, u8 reg) -{ - outb(reg, port_base); - return inb(port_base + 1); -} - -void pm_iowrite(u8 reg, u8 value) -{ - pmio_write_index(PM_INDEX, reg, value); -} - -u8 pm_ioread(u8 reg) -{ - return pmio_read_index(PM_INDEX, reg); -} - -void pm2_iowrite(u8 reg, u8 value) -{ - pmio_write_index(PM2_INDEX, reg, value); -} - -u8 pm2_ioread(u8 reg) -{ - return pmio_read_index(PM2_INDEX, reg); -} - -static void set_pmio_enable_bits(struct device *sm_dev, u32 reg_pos, - u32 mask, u32 val) -{ - u8 reg_old, reg; - reg = reg_old = pm_ioread(reg_pos); - reg &= ~mask; - reg |= val; - if (reg != reg_old) { - pm_iowrite(reg_pos, reg); - } -} - -void sb7xx_51xx_enable(struct device *dev) -{ - struct device *sm_dev = NULL; - struct device *bus_dev = NULL; - int index; - u32 deviceid; - u32 vendorid; - - /* struct southbridge_ati_sb700_config *conf; */ - /* conf = dev->chip_info; */ - int i; - - u32 devfn; - - printk(BIOS_DEBUG, "sb7xx_51xx_enable()\n"); - - /* - * 0:11.0 SATA bit 8 of sm_dev 0xac : 1 - enable, default + 32 * 3 - * 0:12.0 OHCI0-USB1 bit 0 of sm_dev 0x68 - * 0:12.1 OHCI1-USB1 bit 1 of sm_dev 0x68 - * 0:12.2 EHCI-USB1 bit 2 of sm_dev 0x68 - * 0:13.0 OHCI0-USB2 bit 4 of sm_dev 0x68 - * 0:13.1 OHCI1-USB2 bit 5 of sm_dev 0x68 - * 0:13.2 EHCI-USB2 bit 6 of sm_dev 0x68 - * 0:14.5 OHCI0-USB3 bit 7 of sm_dev 0x68 - * 0:14.0 SMBUS 0 - * 0:14.1 IDE 1 - * 0:14.2 HDA bit 3 of pm_io 0x59 : 1 - enable, default + 32 * 4 - * 0:14.3 LPC bit 20 of sm_dev 0x64 : 0 - disable, default + 32 * 1 - * 0:14.4 PCI 4 - */ - if (dev->device == 0x0000) { - vendorid = pci_read_config32(dev, PCI_VENDOR_ID); - deviceid = (vendorid >> 16) & 0xffff; - vendorid &= 0xffff; - } else { - vendorid = dev->vendor; - deviceid = dev->device; - } - - bus_dev = dev->bus->dev; - if ((bus_dev->vendor == PCI_VENDOR_ID_ATI) && - (bus_dev->device == PCI_DEVICE_ID_ATI_SB700_PCI)) { - devfn = (bus_dev->path.pci.devfn) & ~7; - sm_dev = find_sm_dev(bus_dev, devfn); - if (!sm_dev) - return; - - /* something under 00:01.0 */ - switch (dev->path.pci.devfn) { - case 5 << 3: - ; - } - return; - } - - i = (dev->path.pci.devfn) & ~7; - i += (3 << 3); - for (devfn = (0x14 << 3); devfn <= i; devfn += (1 << 3)) { - sm_dev = find_sm_dev(dev, devfn); - if (sm_dev) - break; - } - if (!sm_dev) - return; - - switch (dev->path.pci.devfn - (devfn - (0x14 << 3))) { - case PCI_DEVFN(0x11, 0): - index = 8; - set_sm_enable_bits(sm_dev, 0xac, 1 << index, - (dev->enabled ? 1 : 0) << index); - break; - case PCI_DEVFN(0x12, 0): - case PCI_DEVFN(0x12, 1): - case PCI_DEVFN(0x12, 2): - index = dev->path.pci.devfn & 3; - set_sm_enable_bits(sm_dev, 0x68, 1 << index, - (dev->enabled ? 1 : 0) << index); - break; - case PCI_DEVFN(0x13, 0): - case PCI_DEVFN(0x13, 1): - case PCI_DEVFN(0x13, 2): - index = (dev->path.pci.devfn & 3) + 4; - set_sm_enable_bits(sm_dev, 0x68, 1 << index, - (dev->enabled ? 1 : 0) << index); - break; - case PCI_DEVFN(0x14, 5): - index = 7; - set_sm_enable_bits(sm_dev, 0x68, 1 << index, - (dev->enabled ? 1 : 0) << index); - break; - case PCI_DEVFN(0x14, 0): - break; - case PCI_DEVFN(0x14, 1): - break; - case PCI_DEVFN(0x14, 2): - index = 3; - set_pmio_enable_bits(sm_dev, 0x59, 1 << index, - (dev->enabled ? 1 : 0) << index); - break; - case PCI_DEVFN(0x14, 3): - index = 20; - set_sm_enable_bits(sm_dev, 0x64, 1 << index, - (dev->enabled ? 1 : 0) << index); - break; - case PCI_DEVFN(0x14, 4): - break; - default: - printk(BIOS_DEBUG, "unknown dev: %s deviceid=%4x\n", dev_path(dev), - deviceid); - } -} - -#if CONFIG(SOUTHBRIDGE_AMD_SUBTYPE_SP5100) -struct chip_operations southbridge_amd_sb700_ops = { - CHIP_NAME("ATI SP5100") - .enable_dev = sb7xx_51xx_enable, -}; -#else -struct chip_operations southbridge_amd_sb700_ops = { - CHIP_NAME("ATI SB700") - .enable_dev = sb7xx_51xx_enable, -}; -#endif diff --git a/src/southbridge/amd/sb700/sb700.h b/src/southbridge/amd/sb700/sb700.h deleted file mode 100644 index 4b863a0778..0000000000 --- a/src/southbridge/amd/sb700/sb700.h +++ /dev/null @@ -1,83 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2010 Advanced Micro Devices, Inc. - * Copyright (C) 2015 Timothy Pearson , Raptor Engineering - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef SB700_H -#define SB700_H - -#include -#include - -/* Power management index/data registers */ -#define BIOSRAM_INDEX 0xcd4 -#define BIOSRAM_DATA 0xcd5 -#define PM_INDEX 0xcd6 -#define PM_DATA 0xcd7 -#define PM2_INDEX 0xcd0 -#define PM2_DATA 0xcd1 - -#define SB700_ACPI_IO_BASE 0x800 - -#define ACPI_PM_EVT_BLK (SB700_ACPI_IO_BASE + 0x00) /* 4 bytes */ -#define ACPI_PM1_CNT_BLK (SB700_ACPI_IO_BASE + 0x04) /* 2 bytes */ -#define ACPI_PMA_CNT_BLK (SB700_ACPI_IO_BASE + 0x16) /* 1 byte */ -#define ACPI_PM_TMR_BLK (SB700_ACPI_IO_BASE + 0x20) /* 4 bytes */ -#define ACPI_GPE0_BLK (SB700_ACPI_IO_BASE + 0x18) /* 8 bytes */ -#define ACPI_CPU_CONTROL (SB700_ACPI_IO_BASE + 0x08) /* 6 bytes */ -#define ACPI_CPU_P_LVL2 (ACPI_CPU_CONTROL + 0x4) /* 1 byte */ - -void pm_iowrite(u8 reg, u8 value); -u8 pm_ioread(u8 reg); -void pm2_iowrite(u8 reg, u8 value); -u8 pm2_ioread(u8 reg); - -void set_sm_enable_bits(struct device *sm_dev, u32 reg_pos, u32 mask, u32 val); - -#define REV_SB700_A11 0x11 -#define REV_SB700_A12 0x12 -#define REV_SB700_A14 0x14 -#define REV_SB700_A15 0x15 - -/* This shouldn't be called before set_sb700_revision() is called. - * Once set_sb700_revision() is called, we use get_sb700_revision(), - * the simpler one, to get the sb700 revision ID. - * The id is 0x39 if A11, 0x3A if A12, 0x3C if A14, 0x3D if A15. - * The differentiate is 0x28, isn't it? */ -#define get_sb700_revision(sm_dev) (pci_read_config8((sm_dev), 0x08) - 0x28) - - -void sb7xx_51xx_lpc_port80(void); -void sb7xx_51xx_pci_port80(void); -void sb7xx_51xx_lpc_init(void); -void sb7xx_51xx_enable_wideio(u8 wio_index, u16 base); -void sb7xx_51xx_disable_wideio(u8 wio_index); -void sb7xx_51xx_early_setup(void); -void sb7xx_51xx_before_pci_init(void); -uint16_t sb7xx_51xx_decode_last_reset(void); - - -/* allow override in mainboard.c */ -void sb7xx_51xx_setup_sata_phys(struct device *dev); -void sb7xx_51xx_setup_sata_port_indication(void *sata_bar5); -void sb7xx_51xx_enable(struct device *dev); - -void set_lpc_sticky_ctl(bool enable); - -int s3_save_nvram_early(u32 dword, int size, int nvram_pos); -int s3_load_nvram_early(int size, u32 *old_dword, int nvram_pos); - -void enable_fid_change_on_sb(u32 sbbusn, u32 sbdn); - -#endif /* SB700_H */ diff --git a/src/southbridge/amd/sb700/sm.c b/src/southbridge/amd/sb700/sm.c deleted file mode 100644 index 535e5e4135..0000000000 --- a/src/southbridge/amd/sb700/sm.c +++ /dev/null @@ -1,542 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2010 Advanced Micro Devices, Inc. - * Copyright (C) 2015 Timothy Pearson , Raptor Engineering - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include "sb700.h" -#include "smbus.h" - -#define NMI_OFF 0 - -#define SB_MMIO_CFG_REG 0x9c -#define SB_MMIO_BASE_ADDRESS 0xfeb00000 - -#define PRIMARY_SMBUS_RESOURCE_NUMBER 0x90 -#define AUXILIARY_SMBUS_RESOURCE_NUMBER 0x58 - -uint8_t amd_sb700_aux_smbus = 0; - -enum power_mode { - POWER_MODE_OFF = 0, - POWER_MODE_ON = 1, - POWER_MODE_LAST = 2, -}; - -static const char *power_mode_names[] = { - [POWER_MODE_OFF] = "off", - [POWER_MODE_ON] = "on", - [POWER_MODE_LAST] = "last", -}; - -/* -* SB700 enables all USB controllers by default in SMBUS Control. -* SB700 enables SATA by default in SMBUS Control. -*/ -static void sm_init(struct device *dev) -{ - u8 byte; - u8 byte_old; - u8 rev; - u32 dword; - void *ioapic_base; - uint32_t power_state; - uint32_t enable_legacy_usb; - u32 nmi_option; - - printk(BIOS_INFO, "sm_init().\n"); - - rev = get_sb700_revision(dev); - /* This works in a similar fashion to a memory resource, but without an enable bit */ - ioapic_base = (void *)(pci_read_config32(dev, 0x74) & (0xffffffe0)); - setup_ioapic(ioapic_base, 0); /* Don't rename IOAPIC ID. */ - - enable_legacy_usb = 1; - get_option(&enable_legacy_usb, "enable_legacy_usb"); - - /* 2.10 Interrupt Routing/Filtering */ - byte = pci_read_config8(dev, 0x62); - if (enable_legacy_usb) - byte |= 0x3; - else - byte &= ~0x3; - pci_write_config8(dev, 0x62, byte); - - byte = pci_read_config8(dev, 0x67); - if (enable_legacy_usb) - byte |= 0x1 << 7; - else - byte &= ~(0x1 << 7); - pci_write_config8(dev, 0x67, byte); - - /* Delay back to back interrupts to the CPU. */ - dword = pci_read_config16(dev, 0x64); - dword |= 1 << 13; - pci_write_config16(dev, 0x64, dword); - - /* rrg:K8 INTR Enable (BIOS should set this bit after PIC initialization) */ - /* rpr 2.1 Enabling Legacy Interrupt */ - dword = pci_read_config8(dev, 0x62); - dword |= 1 << 2; - pci_write_config8(dev, 0x62, dword); - - dword = pci_read_config32(dev, 0x78); - dword |= 1 << 9; - pci_write_config32(dev, 0x78, dword); /* enable 0xCD6 0xCD7 */ - - /* bit 10: MultiMediaTimerIrqEn */ - dword = pci_read_config8(dev, 0x64); - dword |= 1 << 10; - pci_write_config8(dev, 0x64, dword); - /* enable serial irq */ - byte = pci_read_config8(dev, 0x69); - byte |= 1 << 7; /* enable serial irq function */ - byte &= ~(0xF << 2); - byte |= 4 << 2; /* set NumSerIrqBits=4 */ - pci_write_config8(dev, 0x69, byte); - - /* Sx State Settings - * Note: These 2 registers need to be set correctly for the S-state - * to work properly. Otherwise the system may hang during resume - * from the S-state. - */ - /*Use 8us clock for delays in the S-state resume timing sequence.*/ - byte = pm_ioread(0x65); - byte &= ~(1 << 7); - pm_iowrite(0x65, byte); - /* Delay the APIC interrupt to the CPU until the system has fully resumed from the S-state. */ - byte = pm_ioread(0x68); - byte |= 1 << 2; - pm_iowrite(0x68, byte); - - /* IRQ0From8254 */ - byte = pci_read_config8(dev, 0x41); - byte &= ~(1 << 7); - pci_write_config8(dev, 0x41, byte); - - byte = pm_ioread(0x61); - if (CONFIG(CPU_AMD_MODEL_10XXX)) - byte &= ~(1 << 1); /* Clear for non-K8 CPUs */ - else - byte |= 1 << 1; /* Set to enable NB/SB handshake during IOAPIC interrupt for AMD K8/K7 */ - pm_iowrite(0x61, byte); - - /* disable SMI */ - byte = pm_ioread(0x53); - byte |= 1 << 3; - pm_iowrite(0x53, byte); - - /* power after power fail */ - power_state = CONFIG_MAINBOARD_POWER_FAILURE_STATE; - get_option(&power_state, "power_on_after_fail"); - if (power_state > 2) { - printk(BIOS_WARNING, "Invalid power_on_after_fail setting, using default\n"); - power_state = CONFIG_MAINBOARD_POWER_FAILURE_STATE; - } - byte = pm_ioread(0x74); - byte &= ~0x03; - if (power_state == POWER_MODE_OFF) - byte |= 0x0; - else if (power_state == POWER_MODE_ON) - byte |= 0x1; - else if (power_state == POWER_MODE_LAST) - byte |= 0x2; - byte |= 1 << 2; - pm_iowrite(0x74, byte); - printk(BIOS_INFO, "set power \"%s\" after power fail\n", power_mode_names[power_state]); - - byte = pm_ioread(0x68); - byte &= ~(1 << 1); - /* 2.7 */ - byte |= 1 << 2; - pm_iowrite(0x68, byte); - - /* 2.7 */ - byte = pm_ioread(0x65); - byte &= ~(1 << 7); - pm_iowrite(0x65, byte); - - /* 2.16 */ - byte = pm_ioread(0x55); - byte |= 1 << 5; - pm_iowrite(0x55, byte); - - byte = pm_ioread(0xD7); - byte |= 1 << 6 | 1 << 1; - pm_iowrite(0xD7, byte); - - /* 2.15 */ - byte = pm_ioread(0x42); - byte &= ~(1 << 2); - pm_iowrite(0x42, byte); - - /* Set up NMI on errors */ - byte = inb(0x70); /* RTC70 */ - byte_old = byte; - nmi_option = NMI_OFF; - get_option(&nmi_option, "nmi"); - if (nmi_option) { - byte &= ~(1 << 7); /* set NMI */ - printk(BIOS_INFO, "++++++++++set NMI+++++\n"); - } else { - byte |= (1 << 7); /* Can not mask NMI from PCI-E and NMI_NOW */ - printk(BIOS_INFO, "++++++++++no set NMI+++++\n"); - } - byte &= ~(1 << 7); - if (byte != byte_old) { - outb(byte, 0x70); - } - - /*rpr v2.13 2.22 SMBUS PCI Config */ - byte = pci_read_config8(dev, 0xE1); - if ((REV_SB700_A11 == rev) || REV_SB700_A12 == rev) { - byte |= 1 << 0; - } - /*Set bit2 to 1, enable Io port 60h read/write SMi trapping and - *Io port 64h write Smi trapping. conflict with ps2 keyboard - */ - //byte |= 1 << 2 | 1 << 3 | 1 << 4; - byte |= 1 << 3 | 1 << 4; - pci_write_config8(dev, 0xE1, byte); - - /* 2.5 Enabling Non-Posted Memory Write */ - axindxc_reg(0x10, 1 << 9, 1 << 9); - - /* 2.11 IO Trap Settings */ - abcfg_reg(0x10090, 1 << 16, 1 << 16); - - /* ab index */ - pci_write_config32(dev, 0xF0, AB_INDX); - /* Initialize the real time clock */ - cmos_init(0); - - /* 4.3 Enabling Upstream DMA Access */ - axcfg_reg(0x04, 1 << 2, 1 << 2); - /* 4.4 Enabling IDE/PCIB Prefetch for Performance Enhancement */ - abcfg_reg(0x10060, 9 << 17, 9 << 17); - abcfg_reg(0x10064, 9 << 17, 9 << 17); - - /* 4.5 Enabling OHCI Prefetch for Performance Enhancement, A12 */ - abcfg_reg(0x80, 1 << 0, 1<< 0); - - /* 4.6 B-Link Client's Credit Variable Settings for the Downstream Arbitration Equation */ - /* 4.7 Enabling Additional Address Bits Checking in Downstream */ - /* 4.16 IO write and SMI ordering enhancement*/ - abcfg_reg(0x9c, 3 << 0, 3 << 0); - if (REV_SB700_A12 == rev) { - abcfg_reg(0x9c, 1 << 8, 1 << 8); - } else if (rev >= REV_SB700_A14) { - abcfg_reg(0x9c, 1 << 8, 0 << 8); - } - if (REV_SB700_A15 == rev) { - abcfg_reg(0x90, 1 << 21, 1 << 21); - abcfg_reg(0x9c, 1 << 5 | 1 << 9 | 1 << 15, 1 << 5 | 1 << 9 | 1 << 15); - } - - /* 4.8 Set B-Link Prefetch Mode */ - abcfg_reg(0x80, 3 << 17, 3 << 17); - - /* 4.9 Enabling Detection of Upstream Interrupts */ - abcfg_reg(0x94, 1 << 20 | 0x7FFFF, 1 << 20 | 0x00FEE); - - /* 4.10: Enabling Downstream Posted Transactions to Pass Non-Posted - * Transactions for the K8 Platform (for All Revisions) */ - abcfg_reg(0x10090, 1 << 8, 1 << 8); - - /* Set ACPI Software clock Throttling Period to 244 us*/ - byte = pm_ioread(0x68); - byte &= ~(3 << 6); - byte |= (2 << 6); /* 244us */ - pm_iowrite(0x68, byte); - - if (REV_SB700_A15 == rev) { - u16 word; - - /* rpr v2.13 4.18 Enabling Posted Pass Non-Posted Downstream */ - axindxc_reg(0x02, 1 << 9, 1 << 9); - abcfg_reg(0x9C, 0x00007CC0, 0x00007CC0); - abcfg_reg(0x1009C, 0x00000030, 0x00000030); - abcfg_reg(0x10090, 0x00001E00, 0x00001E00); - - /* rpr v2.13 4.19 Enabling Posted Pass Non-Posted Upstream */ - abcfg_reg(0x58, 0x0000F800, 0x0000E800); - - /* rpr v2.13 4.20 64 bit Non-Posted Memory Write Support */ - axindxc_reg(0x02, 1 << 10, 1 << 10); - - /* rpr v2.13 2.38 Unconditional Shutdown */ - byte = pci_read_config8(dev, 0x43); - byte &= ~(1 << 3); - pci_write_config8(dev, 0x43, byte); - - word = pci_read_config16(dev, 0x38); - word |= 1 << 12; - pci_write_config16(dev, 0x38, word); - - byte |= 1 << 3; - pci_write_config8(dev, 0x43, byte); - - /* Enable southbridge MMIO decode */ - dword = pci_read_config32(dev, SB_MMIO_CFG_REG); - dword &= ~(0xffffff << 8); - dword |= SB_MMIO_BASE_ADDRESS; - dword |= 0x1; - pci_write_config32(dev, SB_MMIO_CFG_REG, dword); - } - byte = pci_read_config8(dev, 0xAE); - if (CONFIG(ENABLE_APIC_EXT_ID)) - byte |= 1 << 4; - byte |= 1 << 5; /* ACPI_DISABLE_TIMER_IRQ_ENHANCEMENT_FOR_8254_TIMER */ - byte |= 1 << 6; /* Enable arbiter between APIC and PIC interrupts */ - pci_write_config8(dev, 0xAE, byte); - - /* 4.11:Programming Cycle Delay for AB and BIF Clock Gating */ - /* 4.12: Enabling AB and BIF Clock Gating */ - abcfg_reg(0x10054, 0xFFFF0000, 0x1040000); - abcfg_reg(0x54, 0xFF << 16, 4 << 16); - abcfg_reg(0x54, 1 << 24, 0 << 24); - abcfg_reg(0x98, 0x0000FF00, 0x00004700); - - /* 4.13:Enabling AB Int_Arbiter Enhancement (for All Revisions) */ - abcfg_reg(0x10054, 0x0000FFFF, 0x07FF); - - /* 4.14:Enabling Requester ID for upstream traffic. */ - abcfg_reg(0x98, 1 << 16, 1 << 16); - - /* 9.2: Enabling IDE Data Bus DD7 Pull Down Resistor */ - byte = pm2_ioread(0xE5); - byte |= 1 << 2; - pm2_iowrite(0xE5, byte); - - /* Enable IDE controller. */ - byte = pm_ioread(0x59); - byte &= ~(1 << 1); - pm_iowrite(0x59, byte); - - /* Enable SCI as irq9. */ - outb(0x4, 0xC00); - outb(0x9, 0xC01); - - printk(BIOS_INFO, "sm_init() end\n"); - - /* Enable NbSb virtual channel */ - axcfg_reg(0x114, 0x3f << 1, 0 << 1); - axcfg_reg(0x120, 0x7f << 1, 0x7f << 1); - axcfg_reg(0x120, 7 << 24, 1 << 24); - axcfg_reg(0x120, 1 << 31, 1 << 31); - abcfg_reg(0x50, 1 << 3, 1 << 3); -} - -static int lsmbus_recv_byte(struct device *dev) -{ - u32 device; - struct resource *res; - struct bus *pbus; - - device = dev->path.i2c.device; - pbus = get_pbus_smbus(dev); - - if (!amd_sb700_aux_smbus) - res = find_resource(pbus->dev, PRIMARY_SMBUS_RESOURCE_NUMBER); - else - res = find_resource(pbus->dev, AUXILIARY_SMBUS_RESOURCE_NUMBER); - - return do_smbus_recv_byte(res->base, device); -} - -static int lsmbus_send_byte(struct device *dev, u8 val) -{ - u32 device; - struct resource *res; - struct bus *pbus; - - device = dev->path.i2c.device; - pbus = get_pbus_smbus(dev); - - if (!amd_sb700_aux_smbus) - res = find_resource(pbus->dev, PRIMARY_SMBUS_RESOURCE_NUMBER); - else - res = find_resource(pbus->dev, AUXILIARY_SMBUS_RESOURCE_NUMBER); - - return do_smbus_send_byte(res->base, device, val); -} - -static int lsmbus_read_byte(struct device *dev, u8 address) -{ - u32 device; - struct resource *res; - struct bus *pbus; - - device = dev->path.i2c.device; - pbus = get_pbus_smbus(dev); - - if (!amd_sb700_aux_smbus) - res = find_resource(pbus->dev, PRIMARY_SMBUS_RESOURCE_NUMBER); - else - res = find_resource(pbus->dev, AUXILIARY_SMBUS_RESOURCE_NUMBER); - - return do_smbus_read_byte(res->base, device, address); -} - -static int lsmbus_write_byte(struct device *dev, u8 address, u8 val) -{ - u32 device; - struct resource *res; - struct bus *pbus; - - device = dev->path.i2c.device; - pbus = get_pbus_smbus(dev); - - if (!amd_sb700_aux_smbus) - res = find_resource(pbus->dev, PRIMARY_SMBUS_RESOURCE_NUMBER); - else - res = find_resource(pbus->dev, AUXILIARY_SMBUS_RESOURCE_NUMBER); - - return do_smbus_write_byte(res->base, device, address, val); -} - -static struct smbus_bus_operations lops_smbus_bus = { - .recv_byte = lsmbus_recv_byte, - .send_byte = lsmbus_send_byte, - .read_byte = lsmbus_read_byte, - .write_byte = lsmbus_write_byte, -}; - -static void sb700_sm_read_resources(struct device *dev) -{ - struct resource *res; - - /* Get the normal pci resources of this device */ - pci_dev_read_resources(dev); - - /* apic */ - res = new_resource(dev, 0x74); - res->base = IO_APIC_ADDR; - res->size = 256 * 0x10; - res->limit = 0xFFFFFFFFUL; /* res->base + res->size -1; */ - res->align = 8; - res->gran = 8; - res->flags = IORESOURCE_MEM | IORESOURCE_FIXED | IORESOURCE_RESERVE | IORESOURCE_ASSIGNED; - - /* SB MMIO / WDT */ - res = new_resource(dev, SB_MMIO_CFG_REG); - res->base = SB_MMIO_BASE_ADDRESS; - res->size = 0x1000; - res->limit = 0xFFFFFFFFUL; /* res->base + res->size -1; */ - res->align = 8; - res->gran = 8; - res->flags = IORESOURCE_MEM | IORESOURCE_FIXED | IORESOURCE_RESERVE | IORESOURCE_ASSIGNED; - - /* HPET */ - res = new_resource(dev, 0xB4); /* TODO: test hpet */ - res->base = 0xfed00000; /* reset hpet to widely accepted address */ - res->size = 0x400; - res->limit = 0xFFFFFFFFUL; /* res->base + res->size -1; */ - res->align = 8; - res->gran = 8; - res->flags = IORESOURCE_MEM | IORESOURCE_FIXED | IORESOURCE_RESERVE | IORESOURCE_ASSIGNED; - - /* dev->command |= PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER; */ - - /* primary smbus */ - res = new_resource(dev, PRIMARY_SMBUS_RESOURCE_NUMBER); - res->base = SMBUS_IO_BASE; - res->size = 0x10; - res->limit = 0xFFFFUL; /* res->base + res->size -1; */ - res->align = 8; - res->gran = 8; - res->flags = IORESOURCE_IO | IORESOURCE_FIXED | IORESOURCE_RESERVE | IORESOURCE_ASSIGNED; - - /* auxiliary smbus */ - res = new_resource(dev, AUXILIARY_SMBUS_RESOURCE_NUMBER); - res->base = SMBUS_AUX_IO_BASE; - res->size = 0x10; - res->limit = 0xFFFFUL; /* res->base + res->size -1; */ - res->align = 8; - res->gran = 8; - res->flags = IORESOURCE_IO | IORESOURCE_FIXED | IORESOURCE_RESERVE | IORESOURCE_ASSIGNED; - - compact_resources(dev); -} - -static void sb700_sm_set_resources(struct device *dev) -{ - struct resource *res; - u8 byte; - - pci_dev_set_resources(dev); - res = find_resource(dev, 0x74); - pci_write_config32(dev, 0x74, res->base | 1 << 3); - - /* TODO: test hpet */ -#if 0 //rrg-2.0.3 shows BAR1 not used - /* Make SMBUS BAR1(HPET base at offset 14h) visible */ - byte = pci_read_config8(dev, 0x43); - byte &= ~(1 << 3); - pci_write_config8(dev, 0x43, byte); -#endif - - res = find_resource(dev, 0xB4); - /* Program HPET BAR Address */ - pci_write_config32(dev, 0xB4, res->base); - - /* Enable decoding of HPET MMIO, enable HPET MSI */ - byte = pci_read_config8(dev, 0x43); - //byte |= (1 << 3); // Make SMBus Bar1 invisible - //byte |= ((1 << 4) | (1 << 5) | (1 << 6) | (1 << 7)); - byte |= (1 << 4); - pci_write_config8(dev, 0x43, byte); - - /* Enable HPET irq */ - byte = pci_read_config8(dev, 0x65); - byte |= (1 << 2); - pci_write_config8(dev, 0x65, byte); - /* TODO: End of test hpet */ - - res = find_resource(dev, PRIMARY_SMBUS_RESOURCE_NUMBER); - pci_write_config32(dev, PRIMARY_SMBUS_RESOURCE_NUMBER, res->base | 1); - - res = find_resource(dev, AUXILIARY_SMBUS_RESOURCE_NUMBER); - pci_write_config32(dev, AUXILIARY_SMBUS_RESOURCE_NUMBER, res->base | 1); -} - -static struct pci_operations lops_pci = { - .set_subsystem = pci_dev_set_subsystem, -}; - -static struct device_operations smbus_ops = { - .read_resources = sb700_sm_read_resources, - .set_resources = sb700_sm_set_resources, - .enable_resources = pci_dev_enable_resources, - .init = sm_init, - .scan_bus = scan_smbus, - .ops_pci = &lops_pci, - .ops_smbus_bus = &lops_smbus_bus, -}; - -static const struct pci_driver smbus_driver __pci_driver = { - .ops = &smbus_ops, - .vendor = PCI_VENDOR_ID_ATI, - .device = PCI_DEVICE_ID_ATI_SB700_SM, -}; diff --git a/src/southbridge/amd/sb700/smbus.c b/src/southbridge/amd/sb700/smbus.c deleted file mode 100644 index 9b0e8f9904..0000000000 --- a/src/southbridge/amd/sb700/smbus.c +++ /dev/null @@ -1,231 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2010 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef _SB700_SMBUS_C_ -#define _SB700_SMBUS_C_ - -#include -#include "smbus.h" - -extern uint8_t amd_sb700_aux_smbus; - -void smbus_switch_to_channel(uint8_t channel_number); -uint8_t smbus_get_current_channel(void); - -void alink_ab_indx(u32 reg_space, u32 reg_addr, u32 mask, u32 val) -{ - u32 tmp; - - outl((reg_space & 0x3) << 30 | reg_addr, AB_INDX); - tmp = inl(AB_DATA); - /* rpr 4.2 - * For certain revisions of the chip, the ABCFG registers, - * with an address of 0x100NN (where 'N' is any hexadecimal - * number), require an extra programming step.*/ - reg_addr & 0x10000 ? outl(0, AB_INDX) : NULL; - - tmp &= ~mask; - tmp |= val; - - /* printk(BIOS_DEBUG, "about write %x, index=%x", tmp, (reg_space&0x3)<<30 | reg_addr); */ - outl((reg_space & 0x3) << 30 | reg_addr, AB_INDX); /* probably we don't have to do it again. */ - outl(tmp, AB_DATA); - reg_addr & 0x10000 ? outl(0, AB_INDX) : NULL; -} - -/* space = 0: AX_INDXC, AX_DATAC - * space = 1: AX_INDXP, AX_DATAP - */ -void alink_ax_indx(u32 space, u32 axindc, u32 mask, u32 val) -{ - u32 tmp; - - /* read axindc to tmp */ - outl(space << 30 | space << 3 | 0x30, AB_INDX); - outl(axindc, AB_DATA); - outl(space << 30 | space << 3 | 0x34, AB_INDX); - tmp = inl(AB_DATA); - - tmp &= ~mask; - tmp |= val; - - /* write tmp */ - outl(space << 30 | space << 3 | 0x30, AB_INDX); - outl(axindc, AB_DATA); - outl(space << 30 | space << 3 | 0x34, AB_INDX); - outl(tmp, AB_DATA); -} - -static int smbus_wait_until_ready(u32 smbus_io_base) -{ - u32 loops; - loops = SMBUS_TIMEOUT; - do { - u8 val; - val = inb(smbus_io_base + SMBHSTSTAT); - val &= 0x1f; - if (val == 0) { /* ready now */ - return 0; - } - outb(val, smbus_io_base + SMBHSTSTAT); - } while (--loops); - return -2; /* time out */ -} - -static int smbus_wait_until_done(u32 smbus_io_base) -{ - u32 loops; - loops = SMBUS_TIMEOUT; - do { - u8 val; - - val = inb(smbus_io_base + SMBHSTSTAT); - val &= 0x1f; /* mask off reserved bits */ - if (val & 0x1c) { - return -5; /* error */ - } - if (val == 0x02) { - outb(val, smbus_io_base + SMBHSTSTAT); /* clear status */ - return 0; - } - } while (--loops); - return -3; /* timeout */ -} - -int do_smbus_recv_byte(u32 smbus_io_base, u32 device) -{ - u8 byte; - - if (smbus_wait_until_ready(smbus_io_base) < 0) { - return -2; /* not ready */ - } - - /* set the device I'm talking to */ - outb(((device & 0x7f) << 1) | 1, smbus_io_base + SMBHSTADDR); - - byte = inb(smbus_io_base + SMBHSTCTRL); - byte &= 0xe3; /* Clear [4:2] */ - byte |= (1 << 2) | (1 << 6); /* Byte data read/write command, start the command */ - outb(byte, smbus_io_base + SMBHSTCTRL); - - /* poll for transaction completion */ - if (smbus_wait_until_done(smbus_io_base) < 0) { - return -3; /* timeout or error */ - } - - /* read results of transaction */ - byte = inb(smbus_io_base + SMBHSTCMD); - - return byte; -} - -int do_smbus_send_byte(u32 smbus_io_base, u32 device, u8 val) -{ - u8 byte; - - if (smbus_wait_until_ready(smbus_io_base) < 0) { - return -2; /* not ready */ - } - - /* set the command... */ - outb(val, smbus_io_base + SMBHSTCMD); - - /* set the device I'm talking to */ - outb(((device & 0x7f) << 1) | 0, smbus_io_base + SMBHSTADDR); - - byte = inb(smbus_io_base + SMBHSTCTRL); - byte &= 0xe3; /* Clear [4:2] */ - byte |= (1 << 2) | (1 << 6); /* Byte data read/write command, start the command */ - outb(byte, smbus_io_base + SMBHSTCTRL); - - /* poll for transaction completion */ - if (smbus_wait_until_done(smbus_io_base) < 0) { - return -3; /* timeout or error */ - } - - return 0; -} - -int do_smbus_read_byte(u32 smbus_io_base, u32 device, u32 address) -{ - u8 byte; - - if (smbus_wait_until_ready(smbus_io_base) < 0) { - return -2; /* not ready */ - } - - /* set the command/address... */ - outb(address & 0xff, smbus_io_base + SMBHSTCMD); - - /* set the device I'm talking to */ - outb(((device & 0x7f) << 1) | 1, smbus_io_base + SMBHSTADDR); - - byte = inb(smbus_io_base + SMBHSTCTRL); - byte &= 0xe3; /* Clear [4:2] */ - byte |= (1 << 3) | (1 << 6); /* Byte data read/write command, start the command */ - outb(byte, smbus_io_base + SMBHSTCTRL); - - /* poll for transaction completion */ - if (smbus_wait_until_done(smbus_io_base) < 0) { - return -3; /* timeout or error */ - } - - /* read results of transaction */ - byte = inb(smbus_io_base + SMBHSTDAT0); - - return byte; -} - -int do_smbus_write_byte(u32 smbus_io_base, u32 device, u32 address, u8 val) -{ - u8 byte; - - if (smbus_wait_until_ready(smbus_io_base) < 0) { - return -2; /* not ready */ - } - - /* set the command/address... */ - outb(address & 0xff, smbus_io_base + SMBHSTCMD); - - /* set the device I'm talking to */ - outb(((device & 0x7f) << 1) | 0, smbus_io_base + SMBHSTADDR); - - /* output value */ - outb(val, smbus_io_base + SMBHSTDAT0); - - byte = inb(smbus_io_base + SMBHSTCTRL); - byte &= 0xe3; /* Clear [4:2] */ - byte |= (1 << 3) | (1 << 6); /* Byte data read/write command, start the command */ - outb(byte, smbus_io_base + SMBHSTCTRL); - - /* poll for transaction completion */ - if (smbus_wait_until_done(smbus_io_base) < 0) { - return -3; /* timeout or error */ - } - - return 0; -} - -void smbus_switch_to_channel(uint8_t channel_number) -{ - amd_sb700_aux_smbus = !!channel_number; -} - -uint8_t smbus_get_current_channel(void) -{ - return amd_sb700_aux_smbus; -} - -#endif diff --git a/src/southbridge/amd/sb700/smbus.h b/src/southbridge/amd/sb700/smbus.h deleted file mode 100644 index 179fbf0282..0000000000 --- a/src/southbridge/amd/sb700/smbus.h +++ /dev/null @@ -1,70 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2010 Advanced Micro Devices, Inc. - * Copyright (C) 2015 Timothy Pearson , Raptor Engineering - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef SB700_SMBUS_H -#define SB700_SMBUS_H - -#include -#include "stddef.h" - -#define SMBUS_IO_BASE 0xb00 -#define SMBUS_AUX_IO_BASE 0xb20 - -#define SMBHSTSTAT 0x0 -#define SMBSLVSTAT 0x1 -#define SMBHSTCTRL 0x2 -#define SMBHSTCMD 0x3 -#define SMBHSTADDR 0x4 -#define SMBHSTDAT0 0x5 -#define SMBHSTDAT1 0x6 -#define SMBHSTBLKDAT 0x7 - -#define SMBSLVCTRL 0x8 -#define SMBSLVCMD_SHADOW 0x9 -#define SMBSLVEVT 0xa -#define SMBSLVDAT 0xc -#define SMBSLVMISC 0xd - -#define AX_INDXC 0 -#define AX_INDXP 1 -#define AXCFG 2 -#define ABCFG 3 - -#define AB_INDX 0xCD8 -#define AB_DATA (AB_INDX+4) - -/* Between 1-10 seconds, We should never timeout normally - * Longer than this is just painful when a timeout condition occurs. - */ -#define SMBUS_TIMEOUT (100*1000*10) - -#define abcfg_reg(reg, mask, val) \ - alink_ab_indx((ABCFG), (reg), (mask), (val)) -#define axcfg_reg(reg, mask, val) \ - alink_ab_indx((AXCFG), (reg), (mask), (val)) -#define axindxc_reg(reg, mask, val) \ - alink_ax_indx(0, (reg), (mask), (val)) -#define axindxp_reg(reg, mask, val) \ - alink_ax_indx(1, (reg), (mask), (val)) - -void alink_ab_indx(u32 reg_space, u32 reg_addr, u32 mask, u32 val); -void alink_ax_indx(u32 space, u32 axindc, u32 mask, u32 val); -int do_smbus_recv_byte(u32 smbus_io_base, u32 device); -int do_smbus_send_byte(u32 smbus_io_base, u32 device, u8 val); -int do_smbus_read_byte(u32 smbus_io_base, u32 device, u32 address); -int do_smbus_write_byte(u32 smbus_io_base, u32 device, u32 address, u8 val); - -#endif diff --git a/src/southbridge/amd/sb700/spi.c b/src/southbridge/amd/sb700/spi.c deleted file mode 100644 index f772f755ba..0000000000 --- a/src/southbridge/amd/sb700/spi.c +++ /dev/null @@ -1,129 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2015 Timothy Pearson , Raptor Engineering - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include -#include -#include -#include -#include -#include - -#define AMD_SB_SPI_TX_LEN 8 - -static uint32_t get_spi_bar(void) -{ - struct device *dev; - - dev = pcidev_on_root(0x14, 3); - return pci_read_config32(dev, 0xa0) & ~0x1f; -} - -static void reset_internal_fifo_pointer(void) -{ - uint32_t spibar = get_spi_bar(); - - do { - write8((void *)(spibar + 2), - read8((void *)(spibar + 2)) | 0x10); - } while (read8((void *)(spibar + 0xd)) & 0x7); -} - -static void execute_command(void) -{ - uint32_t spibar = get_spi_bar(); - - write8((void *)(spibar + 2), read8((void *)(spibar + 2)) | 1); - - while ((read8((void *)(spibar + 2)) & 1) && - (read8((void *)(spibar+3)) & 0x80)); -} - -static int spi_ctrlr_xfer(const struct spi_slave *slave, const void *dout, - size_t bytesout, void *din, size_t bytesin) -{ - /* First byte is cmd which cannot be sent through the FIFO. */ - u8 cmd = *(u8 *)dout++; - u8 readoffby1; - u8 readwrite; - size_t count; - - uint32_t spibar = get_spi_bar(); - - bytesout--; - - /* - * Check if this is a write command attempting to transfer more bytes - * than the controller can handle. Iterations for writes are not - * supported here because each SPI write command needs to be preceded - * and followed by other SPI commands, and this sequence is controlled - * by the SPI chip driver. - */ - if (bytesout > AMD_SB_SPI_TX_LEN) { - printk(BIOS_DEBUG, "FCH SPI: Too much to write. Does your SPI chip driver use" - " spi_crop_chunk()?\n"); - return -1; - } - - readoffby1 = bytesout ? 0 : 1; - - readwrite = (bytesin + readoffby1) << 4 | bytesout; - write8((void *)(spibar + 1), readwrite); - write8((void *)(spibar + 0), cmd); - - reset_internal_fifo_pointer(); - for (count = 0; count < bytesout; count++, dout++) { - write8((void *)(spibar + 0x0C), *(u8 *)dout); - } - - reset_internal_fifo_pointer(); - execute_command(); - - reset_internal_fifo_pointer(); - /* Skip the bytes we sent. */ - for (count = 0; count < bytesout; count++) { - cmd = read8((void *)(spibar + 0x0C)); - } - /* read response bytes */ - for (count = 0; count < bytesin; count++, din++) { - *(u8 *)din = read8((void *)(spibar + 0x0C)); - } - - return 0; -} - -static int xfer_vectors(const struct spi_slave *slave, - struct spi_op vectors[], size_t count) -{ - return spi_flash_vector_helper(slave, vectors, count, spi_ctrlr_xfer); -} - -static const struct spi_ctrlr spi_ctrlr = { - .xfer_vector = xfer_vectors, - .max_xfer_size = AMD_SB_SPI_TX_LEN, - .flags = SPI_CNTRLR_DEDUCT_CMD_LEN, -}; - -const struct spi_ctrlr_buses spi_ctrlr_bus_map[] = { - { - .ctrlr = &spi_ctrlr, - .bus_start = 0, - .bus_end = 0, - }, -}; - -const size_t spi_ctrlr_bus_map_count = ARRAY_SIZE(spi_ctrlr_bus_map); diff --git a/src/southbridge/amd/sb700/spi.h b/src/southbridge/amd/sb700/spi.h deleted file mode 100644 index 605f3eedf2..0000000000 --- a/src/southbridge/amd/sb700/spi.h +++ /dev/null @@ -1,17 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2015 Timothy Pearson , Raptor Engineering - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -int spi_claim_bus(const struct spi_slave *slave); -void spi_release_bus(const struct spi_slave *slave); diff --git a/src/southbridge/amd/sb700/usb.c b/src/southbridge/amd/sb700/usb.c deleted file mode 100644 index 4109e88cc3..0000000000 --- a/src/southbridge/amd/sb700/usb.c +++ /dev/null @@ -1,257 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2010 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include "sb700.h" - -static struct pci_operations lops_pci = { - .set_subsystem = pci_dev_set_subsystem, -}; - -static void usb_init(struct device *dev) -{ - u8 byte; - u16 word; - u32 dword; - - /* 6.1 Enable OHCI0-4 and EHCI Controllers */ - struct device *sm_dev; - sm_dev = pcidev_on_root(0x14, 0); - byte = pci_read_config8(sm_dev, 0x68); - byte |= 0xFF; - pci_write_config8(sm_dev, 0x68, byte); - - /* RPR 6.2 Enables the USB PME Event,Enable USB resume support */ - byte = pm_ioread(0x61); - byte |= 1 << 6; - pm_iowrite(0x61, byte); - byte = pm_ioread(0x65); - byte |= 1 << 2; - pm_iowrite(0x65, byte); - - /* RPR 6.3 Support USB device wakeup from the S4/S5 state */ - byte = pm_ioread(0x65); - byte &= ~(1 << 0); - pm_iowrite(0x65, byte); - - /* RPR 6.5 Enable the USB controller to get reset by any software that generate a PCIRst# condition */ - byte = pm_ioread(0x65); - byte |= (1 << 4); - pm_iowrite(0x65, byte); - - /* USB_ADVANCED_SLEEP_CONTROL */ - byte = pm_ioread(0x95); - byte &= ~(7 << 0); - byte |= 6 << 0; /* Advanced sleep up to 6 uframes */ - pm_iowrite(0x95, byte); - - /* RPR 6.10 Disable OHCI MSI Capability. */ - word = pci_read_config16(dev, 0x40); - word |= (0x3 << 8); - pci_write_config16(dev, 0x40, word); - - /* USB-1_OHCI0_Corner Case S3 Wake Up */ - dword = pci_read_config32(dev, 0x50); - dword |= (1 << 16); - pci_write_config32(dev, 0x50, dword); -} - -static void usb_init2(struct device *dev) -{ - uint32_t dword; - void *usb2_bar0; - struct device *sm_dev; - uint8_t rev; - uint8_t ehci_async_data_cache; - uint8_t nvram; - - ehci_async_data_cache = 1; - if (get_option(&nvram, "ehci_async_data_cache") == CB_SUCCESS) - ehci_async_data_cache = !!nvram; - - sm_dev = pcidev_on_root(0x14, 0); - rev = get_sb700_revision(sm_dev); - - /* dword = pci_read_config32(dev, 0xf8); */ - /* dword |= 40; */ - /* pci_write_config32(dev, 0xf8, dword); */ - - usb2_bar0 = (void *)(pci_read_config32(dev, 0x10) & ~0xFF); - printk(BIOS_INFO, "usb2_bar0=0x%p\n", usb2_bar0); - - /* RPR6.4 Enables the USB PHY auto calibration resister to match 45ohm resistance */ - dword = 0x00020F00; - write32(usb2_bar0 + 0xC0, dword); - - /* RPR6.9 Sets In/OUT FIFO threshold for best performance */ - dword = 0x00400040; - write32(usb2_bar0 + 0xA4, dword); - - /* RPR6.11 Disabling EHCI Advance Asynchronous Enhancement */ - dword = pci_read_config32(dev, 0x50); - dword |= (1 << 28); - pci_write_config32(dev, 0x50, dword); - - /* RPR 6.12 EHCI Advance PHY Power Savings */ - /* RPR says it is just for A12. CIMM sets it when it is above A11. */ - /* But it makes the linux crash, so we skip it */ - dword = pci_read_config32(dev, 0x50); - dword |= 1 << 31; - pci_write_config32(dev, 0x50, dword); - - /* RPR6.13 Enabling Fix for EHCI Controller Driver Yellow Sign Issue */ - /* RPR says it is just for A12. CIMx sets it when it is above A11. */ - dword = pci_read_config32(dev, 0x50); - dword |= (1 << 20); - pci_write_config32(dev, 0x50, dword); - - /* RPR6.15 EHCI Async Park Mode */ - dword = pci_read_config32(dev, 0x50); - dword |= (1 << 23); - pci_write_config32(dev, 0x50, dword); - - /* Each step below causes the linux crashes. Leave them here - * for future debugging. */ - u8 byte; - u16 word; - - /* RPR6.16 Disable EHCI MSI support */ - byte = pci_read_config8(dev, 0x50); - byte |= (1 << 6); - pci_write_config8(dev, 0x50, byte); - - /* RPR6.17 Disable the EHCI Dynamic Power Saving feature */ - word = read32(usb2_bar0 + 0xBC); - word &= ~(1 << 12); - write16(usb2_bar0 + 0xBC, word); - - /* RPR6.19 USB Controller DMA Read Delay Tolerant. */ - if (rev >= REV_SB700_A14) { - byte = pci_read_config8(dev, 0x50); - byte |= (1 << 7); - pci_write_config8(dev, 0x50, byte); - } - - /* SB700_A15, USB-2_EHCI_PID_ERROR_CHECKING */ - if (rev == REV_SB700_A15) { - word = pci_read_config16(dev, 0x50); - word |= (1 << 9); - pci_write_config16(dev, 0x50, word); - } - - /* RPR6.20 Async Park Mode. */ - /* RPR recommends not to set these bits. */ - #if 0 - dword = pci_read_config32(dev, 0x50); - dword |= 1 << 23; - if (rev >= REV_SB700_A14) { - dword &= ~(1 << 2); - } - pci_write_config32(dev, 0x50, dword); - #endif - - /* RPR6.22 Advance Async Enhancement */ - /* RPR6.23 USB Periodic Cache Setting */ - dword = pci_read_config32(dev, 0x50); - if (rev == REV_SB700_A12) { - dword |= 1 << 28; /* 6.22 */ - dword |= 1 << 27; /* 6.23 */ - } else if (rev >= REV_SB700_A14) { - dword |= 1 << 3; - dword &= ~(1 << 28); /* 6.22 */ - dword |= 1 << 8; - dword &= ~(1 << 27); /* 6.23 */ - } -#if CONFIG(SOUTHBRIDGE_AMD_SUBTYPE_SP5100) - /* SP5100 Erratum 36 */ - dword &= ~(1 << 26); - if (!ehci_async_data_cache) - dword |= 1 << 26; -#endif - pci_write_config32(dev, 0x50, dword); - printk(BIOS_DEBUG, "rpr 6.23, final dword=%x\n", dword); -} - -static struct device_operations usb_ops = { - .read_resources = pci_ehci_read_resources, - .set_resources = pci_dev_set_resources, - .enable_resources = pci_dev_enable_resources, - .init = usb_init, - .scan_bus = 0, - .ops_pci = &lops_pci, -}; - -static const struct pci_driver usb_0_driver __pci_driver = { - .ops = &usb_ops, - .vendor = PCI_VENDOR_ID_ATI, - .device = PCI_DEVICE_ID_ATI_SB700_USB_18_0, -}; - -static const struct pci_driver usb_1_driver __pci_driver = { - .ops = &usb_ops, - .vendor = PCI_VENDOR_ID_ATI, - .device = PCI_DEVICE_ID_ATI_SB700_USB_18_1, -}; - -/* the pci id of usb ctrl 0 and 1 are the same. */ -/* - * static const struct pci_driver usb_3_driver __pci_driver = { - * .ops = &usb_ops, - * .vendor = PCI_VENDOR_ID_ATI, - * .device = PCI_DEVICE_ID_ATI_SB700_USB_19_0, - * }; - * static const struct pci_driver usb_4_driver __pci_driver = { - * .ops = &usb_ops, - * .vendor = PCI_VENDOR_ID_ATI, - * .device = PCI_DEVICE_ID_ATI_SB700_USB_19_1, - * }; - */ - -static const struct pci_driver usb_4_driver __pci_driver = { - .ops = &usb_ops, - .vendor = PCI_VENDOR_ID_ATI, - .device = PCI_DEVICE_ID_ATI_SB700_USB_20_5, -}; - -static struct device_operations usb_ops2 = { - .read_resources = pci_ehci_read_resources, - .set_resources = pci_dev_set_resources, - .enable_resources = pci_dev_enable_resources, - .init = usb_init2, - .scan_bus = 0, - .ops_pci = &lops_pci, -}; - -static const struct pci_driver usb_5_driver __pci_driver = { - .ops = &usb_ops2, - .vendor = PCI_VENDOR_ID_ATI, - .device = PCI_DEVICE_ID_ATI_SB700_USB_18_2, -}; -/* - * static const struct pci_driver usb_5_driver __pci_driver = { - * .ops = &usb_ops2, - * .vendor = PCI_VENDOR_ID_ATI, - * .device = PCI_DEVICE_ID_ATI_SB700_USB_19_2, - * }; - */ From 334699d20574a165fa5e8045cfc6823be90b59b6 Mon Sep 17 00:00:00 2001 From: Arthur Heymans Date: Wed, 20 Nov 2019 05:06:18 +0100 Subject: [PATCH 0294/1242] mb/*/*: Use proper header for pm_iowrite() MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit These boards don't include any from sb/amd/sb800. Change-Id: I2dbe39df6e4c5a86a0714b396bb89b03bbafd164 Signed-off-by: Arthur Heymans Reviewed-on: https://review.coreboot.org/c/coreboot/+/36987 Reviewed-by: Kyösti Mälkki Reviewed-by: Angel Pons Reviewed-by: HAOUAS Elyes Tested-by: build bot (Jenkins) --- src/mainboard/amd/inagua/mainboard.c | 2 +- src/mainboard/amd/south_station/mainboard.c | 2 +- src/mainboard/amd/union_station/mainboard.c | 2 +- src/mainboard/gizmosphere/gizmo/mainboard.c | 2 +- src/mainboard/lippert/frontrunner-af/mainboard.c | 2 +- src/mainboard/lippert/toucan-af/mainboard.c | 2 +- 6 files changed, 6 insertions(+), 6 deletions(-) diff --git a/src/mainboard/amd/inagua/mainboard.c b/src/mainboard/amd/inagua/mainboard.c index c4fc3b8dd9..cf40e262aa 100644 --- a/src/mainboard/amd/inagua/mainboard.c +++ b/src/mainboard/amd/inagua/mainboard.c @@ -15,7 +15,7 @@ #include #include -#include +#include #include /* Platform Specific Definitions */ static void init_gpios(void) diff --git a/src/mainboard/amd/south_station/mainboard.c b/src/mainboard/amd/south_station/mainboard.c index 8932f7a7b7..c6f219662f 100644 --- a/src/mainboard/amd/south_station/mainboard.c +++ b/src/mainboard/amd/south_station/mainboard.c @@ -16,7 +16,7 @@ #include #include #include -#include +#include #include /* Platform Specific Definitions */ /** diff --git a/src/mainboard/amd/union_station/mainboard.c b/src/mainboard/amd/union_station/mainboard.c index 402bc3634a..e2c0ac7370 100644 --- a/src/mainboard/amd/union_station/mainboard.c +++ b/src/mainboard/amd/union_station/mainboard.c @@ -15,7 +15,7 @@ #include #include -#include +#include #include /* Platform Specific Definitions */ /********************************************** diff --git a/src/mainboard/gizmosphere/gizmo/mainboard.c b/src/mainboard/gizmosphere/gizmo/mainboard.c index 5d4fbd71e1..36fa5f9074 100644 --- a/src/mainboard/gizmosphere/gizmo/mainboard.c +++ b/src/mainboard/gizmosphere/gizmo/mainboard.c @@ -20,7 +20,7 @@ #include #include #include -#include +#include #include /********************************************** diff --git a/src/mainboard/lippert/frontrunner-af/mainboard.c b/src/mainboard/lippert/frontrunner-af/mainboard.c index 653027630c..44d0104e00 100644 --- a/src/mainboard/lippert/frontrunner-af/mainboard.c +++ b/src/mainboard/lippert/frontrunner-af/mainboard.c @@ -21,7 +21,7 @@ #include #include #include -#include +#include #include #include /* SMBUS0_BASE_ADDRESS */ #include diff --git a/src/mainboard/lippert/toucan-af/mainboard.c b/src/mainboard/lippert/toucan-af/mainboard.c index b7126ea18b..746b1953f8 100644 --- a/src/mainboard/lippert/toucan-af/mainboard.c +++ b/src/mainboard/lippert/toucan-af/mainboard.c @@ -20,7 +20,7 @@ #include #include #include -#include +#include #include #include /* SMBUS0_BASE_ADDRESS */ #include From 57803ba3f5b10d1214d1089baa401e4b12ef94bf Mon Sep 17 00:00:00 2001 From: Arthur Heymans Date: Tue, 19 Nov 2019 17:23:34 +0100 Subject: [PATCH 0295/1242] sb/amd/sb800: Drop support MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Relocatable ramstage, postcar stage and C_ENVIRONMENT_BOOTBLOCK are now mandatory features, which platforms using this code lack. Change-Id: I1c25837f1ba05ecd58309b63a471001f4aee2fff Signed-off-by: Arthur Heymans Reviewed-on: https://review.coreboot.org/c/coreboot/+/36968 Reviewed-by: Kyösti Mälkki Reviewed-by: Angel Pons Reviewed-by: HAOUAS Elyes Tested-by: build bot (Jenkins) --- src/cpu/amd/family_10h-family_15h/init_cpus.c | 35 - src/southbridge/amd/sb800/Kconfig | 31 - src/southbridge/amd/sb800/Makefile.inc | 22 - src/southbridge/amd/sb800/bootblock.c | 62 -- src/southbridge/amd/sb800/chip.h | 28 - src/southbridge/amd/sb800/early_setup.c | 662 ------------------ src/southbridge/amd/sb800/enable_usbdebug.c | 53 -- src/southbridge/amd/sb800/fadt.c | 162 ----- src/southbridge/amd/sb800/hda.c | 209 ------ src/southbridge/amd/sb800/ide.c | 75 -- src/southbridge/amd/sb800/lpc.c | 261 ------- src/southbridge/amd/sb800/pci.c | 71 -- src/southbridge/amd/sb800/pcie.c | 71 -- src/southbridge/amd/sb800/ramtop.c | 51 -- src/southbridge/amd/sb800/reset.c | 31 - src/southbridge/amd/sb800/sata.c | 268 ------- src/southbridge/amd/sb800/sb800.c | 376 ---------- src/southbridge/amd/sb800/sb800.h | 60 -- src/southbridge/amd/sb800/sm.c | 346 --------- src/southbridge/amd/sb800/smbus.c | 245 ------- src/southbridge/amd/sb800/smbus.h | 70 -- src/southbridge/amd/sb800/usb.c | 205 ------ 22 files changed, 3394 deletions(-) delete mode 100644 src/southbridge/amd/sb800/Kconfig delete mode 100644 src/southbridge/amd/sb800/Makefile.inc delete mode 100644 src/southbridge/amd/sb800/bootblock.c delete mode 100644 src/southbridge/amd/sb800/chip.h delete mode 100644 src/southbridge/amd/sb800/early_setup.c delete mode 100644 src/southbridge/amd/sb800/enable_usbdebug.c delete mode 100644 src/southbridge/amd/sb800/fadt.c delete mode 100644 src/southbridge/amd/sb800/hda.c delete mode 100644 src/southbridge/amd/sb800/ide.c delete mode 100644 src/southbridge/amd/sb800/lpc.c delete mode 100644 src/southbridge/amd/sb800/pci.c delete mode 100644 src/southbridge/amd/sb800/pcie.c delete mode 100644 src/southbridge/amd/sb800/ramtop.c delete mode 100644 src/southbridge/amd/sb800/reset.c delete mode 100644 src/southbridge/amd/sb800/sata.c delete mode 100644 src/southbridge/amd/sb800/sb800.c delete mode 100644 src/southbridge/amd/sb800/sb800.h delete mode 100644 src/southbridge/amd/sb800/sm.c delete mode 100644 src/southbridge/amd/sb800/smbus.c delete mode 100644 src/southbridge/amd/sb800/smbus.h delete mode 100644 src/southbridge/amd/sb800/usb.c diff --git a/src/cpu/amd/family_10h-family_15h/init_cpus.c b/src/cpu/amd/family_10h-family_15h/init_cpus.c index 89188fddd7..c7ef86a5a1 100644 --- a/src/cpu/amd/family_10h-family_15h/init_cpus.c +++ b/src/cpu/amd/family_10h-family_15h/init_cpus.c @@ -30,10 +30,6 @@ #include -#if CONFIG(SOUTHBRIDGE_AMD_SB800) -#include -#endif - #include "cpu/amd/car/disable_cache_as_ram.c" #if CONFIG(PCI_IO_CFG_EXT) @@ -1041,37 +1037,6 @@ void cpuSetAMDMSR(uint8_t node_id) } } -#if CONFIG(SOUTHBRIDGE_AMD_SB800) - if (revision & (AMD_DR_GT_D0 | AMD_FAM15_ALL)) { - /* Set up message triggered C1E */ - msr = rdmsr(MSR_INTPEND); - msr.lo &= ~0xffff; /* IOMsgAddr = ACPI_PM_EVT_BLK */ - msr.lo |= ACPI_PM_EVT_BLK & 0xffff; - msr.lo |= (0x1 << 29); /* BmStsClrOnHltEn = 1 */ - if (revision & AMD_DR_GT_D0) { - msr.lo &= ~(0x1 << 28); /* C1eOnCmpHalt = 0 */ - msr.lo &= ~(0x1 << 27); /* SmiOnCmpHalt = 0 */ - } - wrmsr(MSR_INTPEND, msr); - - msr = rdmsr(HWCR_MSR); - msr.lo |= (0x1 << 12); /* HltXSpCycEn = 1 */ - wrmsr(HWCR_MSR, msr); - } - - if (revision & (AMD_DR_Ex | AMD_FAM15_ALL)) { - if (CONFIG(HAVE_ACPI_TABLES)) - if ((get_option(&nvram, "cpu_c_states") == CB_SUCCESS) && - (nvram)) { - /* Set up the C-state base address */ - msr_t c_state_addr_msr; - c_state_addr_msr = rdmsr(MSR_CSTATE_ADDRESS); - c_state_addr_msr.lo = ACPI_CPU_P_LVL2; - wrmsr(MSR_CSTATE_ADDRESS, c_state_addr_msr); - } - } -#endif - if (revision & AMD_FAM15_ALL) { enable_cpb = 1; if (get_option(&nvram, "cpu_core_boost") == CB_SUCCESS) diff --git a/src/southbridge/amd/sb800/Kconfig b/src/southbridge/amd/sb800/Kconfig deleted file mode 100644 index 245a9f2272..0000000000 --- a/src/southbridge/amd/sb800/Kconfig +++ /dev/null @@ -1,31 +0,0 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2010 Advanced Micro Devices, Inc. -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; version 2 of the License. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## - -config SOUTHBRIDGE_AMD_SB800 - bool - select IOAPIC - select HAVE_USBDEBUG_OPTIONS - -if SOUTHBRIDGE_AMD_SB800 - -config BOOTBLOCK_SOUTHBRIDGE_INIT - string - default "southbridge/amd/sb800/bootblock.c" - -config EHCI_BAR - hex - default 0xfef00000 - -endif # SOUTHBRIDGE_AMD_SB800 diff --git a/src/southbridge/amd/sb800/Makefile.inc b/src/southbridge/amd/sb800/Makefile.inc deleted file mode 100644 index 276ca29acd..0000000000 --- a/src/southbridge/amd/sb800/Makefile.inc +++ /dev/null @@ -1,22 +0,0 @@ -ifeq ($(CONFIG_SOUTHBRIDGE_AMD_SB800),y) - -ramstage-y += sb800.c -ramstage-y += usb.c -ramstage-y += lpc.c -ramstage-y += sm.c -ramstage-y += ide.c -ramstage-y += sata.c -ramstage-y += hda.c -ramstage-y += pci.c -ramstage-y += pcie.c -ramstage-$(CONFIG_HAVE_ACPI_TABLES) += fadt.c -ramstage-y += reset.c - -bootblock-y += enable_usbdebug.c -romstage-y += enable_usbdebug.c -ramstage-y += enable_usbdebug.c - -romstage-y += ramtop.c -ramstage-y += ramtop.c - -endif diff --git a/src/southbridge/amd/sb800/bootblock.c b/src/southbridge/amd/sb800/bootblock.c deleted file mode 100644 index 0b3486406e..0000000000 --- a/src/southbridge/amd/sb800/bootblock.c +++ /dev/null @@ -1,62 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2010 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include - -/* - * Enable 4MB (LPC) ROM access at 0xFFC00000 - 0xFFFFFFFF. - * - * Hardware should enable LPC ROM by pin straps. This function does not - * handle the theoretically possible PCI ROM, FWH, or SPI ROM configurations. - * - * The SB800 power-on default is to map 512K ROM space. - * - */ -static void sb800_enable_rom(void) -{ - u8 reg8; - pci_devfn_t dev; - - dev = PCI_DEV(0, 0x14, 3); - - /* Decode variable LPC ROM address ranges 1 and 2. */ - reg8 = pci_io_read_config8(dev, 0x48); - reg8 |= (1 << 3) | (1 << 4); - pci_io_write_config8(dev, 0x48, reg8); - - /* LPC ROM address range 1: */ - /* Enable LPC ROM range mirroring start at 0x000e(0000). */ - pci_io_write_config16(dev, 0x68, 0x000e); - /* Enable LPC ROM range mirroring end at 0x000f(ffff). */ - pci_io_write_config16(dev, 0x6a, 0x000f); - - /* LPC ROM address range 2: */ - /* - * Enable LPC ROM range start at: - * 0xfff8(0000): 512KB - * 0xfff0(0000): 1MB - * 0xffe0(0000): 2MB - * 0xffc0(0000): 4MB - */ - pci_io_write_config16(dev, 0x6c, 0x10000 - (CONFIG_COREBOOT_ROMSIZE_KB >> 6)); - /* Enable LPC ROM range end at 0xffff(ffff). */ - pci_io_write_config16(dev, 0x6e, 0xffff); -} - -static void bootblock_southbridge_init(void) -{ - sb800_enable_rom(); -} diff --git a/src/southbridge/amd/sb800/chip.h b/src/southbridge/amd/sb800/chip.h deleted file mode 100644 index f77397744f..0000000000 --- a/src/southbridge/amd/sb800/chip.h +++ /dev/null @@ -1,28 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2010 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef SB800_CHIP_H -#define SB800_CHIP_H - -struct southbridge_amd_sb800_config -{ - u32 ide0_enable : 1; - u32 sata0_enable : 1; - u32 boot_switch_sata_ide : 1; - u32 hda_viddid; - u8 gpp_configuration; -}; - -#endif /* SB800_CHIP_H */ diff --git a/src/southbridge/amd/sb800/early_setup.c b/src/southbridge/amd/sb800/early_setup.c deleted file mode 100644 index b549c5e17c..0000000000 --- a/src/southbridge/amd/sb800/early_setup.c +++ /dev/null @@ -1,662 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2010 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef _SB800_EARLY_SETUP_C_ -#define _SB800_EARLY_SETUP_C_ - -#include -#include -#include -#include -#include -#include - -#include "sb800.h" -#include "smbus.c" - -#define SMBUS_IO_BASE 0x6000 /* Is it a temporary SMBus I/O base address? */ - /*SIZE 0x40 */ - -static void pmio_write(u8 reg, u8 value) -{ - outb(reg, PM_INDEX); - outb(value, PM_INDEX + 1); -} - -static u8 pmio_read(u8 reg) -{ - outb(reg, PM_INDEX); - return inb(PM_INDEX + 1); -} - -static void sb800_acpi_init(void) -{ - pmio_write(0x60, ACPI_PM_EVT_BLK & 0xFF); - pmio_write(0x61, ACPI_PM_EVT_BLK >> 8); - pmio_write(0x62, ACPI_PM1_CNT_BLK & 0xFF); - pmio_write(0x63, ACPI_PM1_CNT_BLK >> 8); - pmio_write(0x64, ACPI_PM_TMR_BLK & 0xFF); - pmio_write(0x65, ACPI_PM_TMR_BLK >> 8); - pmio_write(0x68, ACPI_GPE0_BLK & 0xFF); - pmio_write(0x69, ACPI_GPE0_BLK >> 8); - - /* CpuControl is in \_PR.CP00, 6 bytes */ - pmio_write(0x66, ACPI_CPU_CONTROL & 0xFF); - pmio_write(0x67, ACPI_CPU_CONTROL >> 8); - - pmio_write(0x6A, 0xB0); /* AcpiSmiCmdLo */ - pmio_write(0x6B, 0); /* AcpiSmiCmdHi */ - - pmio_write(0x6E, 0xB8); /* AcpiPmaCntBlkLo */ - pmio_write(0x6F, 0); /* AcpiPmaCntBlkHi */ - - pmio_write(0x6C, ACPI_PMA_CNT_BLK & 0xFF); - pmio_write(0x6D, ACPI_PMA_CNT_BLK >> 8); - - pmio_write(0x74, 1<<0 | 1<<1 | 1<<4 | 1<<2); /* AcpiDecodeEnable, When set, SB uses - * the contents of the PM registers at - * index 60-6B to decode ACPI I/O address. - * AcpiSmiEn & SmiCmdEn*/ - /* RTC_En_En, TMR_En_En, GBL_EN_EN */ - outl(0x1, ACPI_PM1_CNT_BLK); /* set SCI_EN */ -} - -/* RPR 2.28 Get SB ASIC Revision.*/ -static u8 get_sb800_revision(void) -{ - pci_devfn_t dev; - u8 rev_id; - u8 rev = 0; - - /* if (rev != 0) return rev; */ - - dev = PCI_DEV(0, 0x14, 0); - - if (dev == PCI_DEV_INVALID) { - die("SMBUS controller not found\n"); - /* NOT REACHED */ - } - rev_id = pci_read_config8(dev, 0x08); - - if (rev_id == 0x40) { - rev = REV_SB800_A11; - } else if (rev_id == 0x41) { - rev = REV_SB800_A12; - } else { - die("It is not SB800 or SB810\r\n"); - } - - return rev; -} - -void sb800_clk_output_48Mhz(void) -{ - /* AcpiMMioDecodeEn */ - u8 reg8; - reg8 = pmio_read(0x24); - reg8 |= 1; - reg8 &= ~(1 << 1); - pmio_write(0x24, reg8); - - *(volatile u32 *)(AMD_SB_ACPI_MMIO_ADDR+0xE00+0x40) &= ~((1 << 0) | (1 << 2)); /* 48Mhz */ - *(volatile u32 *)(AMD_SB_ACPI_MMIO_ADDR+0xE00+0x40) |= 1 << 1; /* 48Mhz */ -} -/*************************************** -* Legacy devices are mapped to LPC space. -* Serial port 0 -* KBC Port -* ACPI Micro-controller port -* LPC ROM size -* This function does not change port 0x80 decoding. -* Console output through any port besides 0x3f8 is unsupported. -* If you use FWH ROMs, you have to setup IDSEL. -***************************************/ -static void sb800_lpc_init(void) -{ - u8 reg8; - pci_devfn_t dev; - - dev = PCI_DEV(0, 0x14, 0); /* SMBUS controller */ - /* NOTE: Set BootTimerDisable, otherwise it would keep rebooting!! - * This bit has no meaning if debug strap is not enabled. So if the - * board keeps rebooting and the code fails to reach here, we could - * disable the debug strap first. */ - reg8 = pmio_read(0x44+3); - reg8 |= 1 << 7; - pmio_write(0x44+3, reg8); - - /* Enable lpc controller */ - reg8 = pmio_read(0xEC); - reg8 |= 1 << 0; - pmio_write(0xEC, reg8); - - dev = PCI_DEV(0, 0x14, 3); /* LPC Controller */ - /* Decode port 0x3f8-0x3ff (Serial 0) */ - //#warning Serial port decode on LPC is hardcoded to 0x3f8 - reg8 = pci_read_config8(dev, 0x44); - reg8 |= 1 << 6; - pci_write_config8(dev, 0x44, reg8); - - /* Decode port 0x60 & 0x64 (PS/2 keyboard) and port 0x62 & 0x66 (ACPI)*/ - reg8 = pci_read_config8(dev, 0x47); - reg8 |= (1 << 5) | (1 << 6); - pci_write_config8(dev, 0x47, reg8); - - /* SuperIO, LPC ROM */ - reg8 = pci_read_config8(dev, 0x48); - /* Decode ports 0x2e-0x2f, 0x4e-0x4f (SuperI/O configuration) */ - reg8 |= (1 << 1) | (1 << 0); - /* Decode variable LPC ROM address ranges 1&2 (see register 0x68-0x6b, 0x6c-0x6f) */ - reg8 |= (1 << 3) | (1 << 4); - /* Decode port 0x70-0x73 (RTC) */ - reg8 |= 1 << 6; - pci_write_config8(dev, 0x48, reg8); -} - -/* what is its usage? */ -u32 get_sbdn(u32 bus) -{ - pci_devfn_t dev; - - /* Find the device. */ - dev = PCI_DEV(bus, 0x14, 0); - return (dev >> 15) & 0x1f; -} - -static u8 dual_core(void) -{ - return (pci_read_config32(PCI_DEV(0, 0x18, 3), 0xE8) & (0x3<<12)) != 0; -} - -/* - * RPR 2.6 C-state and VID/FID change for the K8 platform. - */ -static void enable_fid_change_on_sb(u32 sbbusn, u32 sbdn) -{ - u8 byte; - byte = pmio_read(0x80); - if (dual_core()) - byte |= 1 << 2 | 1 << 1; - byte |= 1 << 3; - byte |= 1 << 4; - byte &= ~(1 << 7); - pmio_write(0x80, byte); - - byte = pmio_read(0x7E); - byte |= 1 << 6; - byte &= ~(1 << 2); - pmio_write(0x7E, byte); - - pmio_write(0x94, 0x01); - - byte = pmio_read(0x89); - byte |= 1 << 4; - pmio_write(0x89, byte); - - byte = pmio_read(0x9b); - byte &= ~(7 << 4); - byte |= 1 << 4; - pmio_write(0x9b, byte); - - pmio_write(0x99, 0x10); - - pmio_write(0x9A, 0x00); - pmio_write(0x96, 0x10); - pmio_write(0x97, 0x00); - - byte = pmio_read(0x81); - byte &= ~(1 << 1); - pmio_write(0x81, byte); -} - -void do_board_reset(void) -{ - set_bios_reset(); - - /* full reset */ - outb(0x0a, 0x0cf9); - outb(0x0e, 0x0cf9); -} - -void do_soft_reset(void) -{ - set_bios_reset(); - /* link reset */ - outb(0x06, 0x0cf9); -} - -void sb800_pci_port80(void) -{ - u8 byte; - pci_devfn_t dev; - - /* P2P Bridge */ - dev = PCI_DEV(0, 0x14, 4); - - /* Chip Control: Enable subtractive decoding */ - byte = pci_read_config8(dev, 0x40); - byte |= 1 << 5; - pci_write_config8(dev, 0x40, byte); - - /* Misc Control: Enable subtractive decoding if 0x40 bit 5 is set */ - byte = pci_read_config8(dev, 0x4B); - byte |= 1 << 7; - pci_write_config8(dev, 0x4B, byte); - - /* The same IO Base and IO Limit here is meaningful because we set the - * bridge to be subtractive. During early setup stage, we have to make - * sure that data can go through port 0x80. - */ - /* IO Base: 0xf000 */ - byte = pci_read_config8(dev, 0x1C); - byte |= 0xF << 4; - pci_write_config8(dev, 0x1C, byte); - - /* IO Limit: 0xf000 */ - byte = pci_read_config8(dev, 0x1D); - byte |= 0xF << 4; - pci_write_config8(dev, 0x1D, byte); - - /* PCI Command: Enable IO response */ - byte = pci_read_config8(dev, 0x04); - byte |= 1 << 0; - pci_write_config8(dev, 0x04, byte); - - /* LPC controller */ - dev = PCI_DEV(0, 0x14, 3); - - byte = pci_read_config8(dev, 0x4A); - byte &= ~(1 << 5); /* disable lpc port 80 */ - pci_write_config8(dev, 0x4A, byte); -} - -#define BIT0 (1 << 0) -#define BIT1 (1 << 1) -#define BIT2 (1 << 2) -#define BIT3 (1 << 3) -#define BIT4 (1 << 4) -#define BIT5 (1 << 5) -#define BIT6 (1 << 6) -#define BIT7 (1 << 7) - -struct pm_entry { - u8 port; - u8 mask; - u8 bit; -}; -struct pm_entry const pm_table[] = -{ - {0x5D, 0x00, BIT0}, - {0xD2, 0xCF, BIT4 + BIT5}, - {0x12, 0x00, BIT0}, - {0x28, 0xFF, BIT0}, - {0x44 + 3, 0x7F, BIT7}, - {0x48, 0xFF, BIT0}, - {0x00, 0xFF, 0x0E}, - {0x00 + 2, 0xFF, 0x40}, - {0x00 + 3, 0xFF, 0x08}, - {0x34, 0xEF, BIT0 + BIT1}, - {0xEC, 0xFD, BIT1}, - {0x5B, 0xF9, BIT1 + BIT2}, - {0x08, 0xFE, BIT2 + BIT4}, - {0x08 + 1, 0xFF, BIT0}, - {0x54, 0x00, BIT4 + BIT7}, - {0x04 + 3, 0xFD, BIT1}, - {0x74, 0xF6, BIT0 + BIT3}, - {0xF0, ~BIT2, 0x00}, - {0xF8, 0x00, 0x6C}, - {0xF8 + 1, 0x00, 0x27}, - {0xF8 + 2, 0x00, 0x00}, - {0xC4, 0xFE, 0x14}, - {0xC0 + 2, 0xBF, 0x40}, - {0xBE, 0xDD, BIT5}, - // HPET workaround - {0x54 + 3, 0xFC, BIT0 + BIT1}, - {0x54 + 2, 0x7F, BIT7}, - {0x54 + 2, 0x7F, 0x00}, - {0xC4, ~(BIT2 + BIT4), BIT2 + BIT4}, - {0xC0, 0, 0xF9}, - {0xC0 + 1, 0x04, 0x03}, - {0xC2, 0x20, 0x58}, - {0xC2 + 1, 0, 0x40}, - {0xC2, ~(BIT4), BIT4}, - {0x74, 0x00, BIT0 + BIT1 + BIT2 + BIT4}, - {0xDE + 1, ~(BIT0 + BIT1), BIT0 + BIT1}, - {0xDE, ~BIT4, BIT4}, - {0xBA, ~BIT3, BIT3}, - {0xBA + 1, ~BIT6, BIT6}, - {0xBC, ~BIT1, BIT1}, - {0xED, ~(BIT0 + BIT1), 0}, - {0xDC, 0x7C, BIT0}, -// {0xFF, 0xFF, 0xFF}, -}; - -void sb800_lpc_port80(void) -{ - u8 byte; - pci_devfn_t dev; - - /* Enable LPC controller */ - byte = pmio_read(0xEC); - byte |= 1 << 0; - pmio_write(0xEC, byte); - - /* Enable port 80 LPC decode in pci function 3 configuration space. */ - dev = PCI_DEV(0, 0x14, 3); - byte = pci_read_config8(dev, 0x4a); - byte |= 1 << 5; /* enable port 80 */ - pci_write_config8(dev, 0x4a, byte); -} - -/* sbDevicesPorInitTable */ -static void sb800_devices_por_init(void) -{ - pci_devfn_t dev; - u8 byte; - - printk(BIOS_INFO, "sb800_devices_por_init()\n"); - /* SMBus Device, BDF:0-20-0 */ - printk(BIOS_INFO, "sb800_devices_por_init(): SMBus Device, BDF:0-20-0\n"); - dev = PCI_DEV(0, 0x14, 0); - - if (dev == PCI_DEV_INVALID) { - die("SMBUS controller not found\n"); - /* NOT REACHED */ - } - printk(BIOS_INFO, "SMBus controller enabled, sb revision is A%x\n", - get_sb800_revision()); - - /* sbPorAtStartOfTblCfg */ - /* rpr 4.1.Set A-Link bridge access address. - * This is an I/O address. The I/O address must be on 16-byte boundary. */ - //pci_write_config32(dev, 0xf0, AB_INDX); - pmio_write(0xE0, AB_INDX & 0xFF); - pmio_write(0xE1, (AB_INDX >> 8) & 0xFF); - pmio_write(0xE2, (AB_INDX >> 16) & 0xFF); - pmio_write(0xE3, (AB_INDX >> 24) & 0xFF); - - /* To enable AB/BIF DMA access, a specific register inside the BIF register space needs to be configured first. */ - /* 4.2:Enables the SB800 to send transactions upstream over A-Link Express interface. */ - axcfg_reg(0x04, 1 << 2, 1 << 2); - //axindxc_reg(0x21, 0xff, 0); - - /* 4.15:Enabling Non-Posted Memory Write for the K8 Platform */ - axindxc_reg(0x10, 1 << 9, 1 << 9); - /* END of sbPorAtStartOfTblCfg */ - - /* sbDevicesPorInitTables */ - /* set smbus iobase */ - //pci_write_config32(dev, 0x90, SMBUS_IO_BASE | 1); - /* The base address of SMBUS is set in a different way with sb700. */ - byte = (SMBUS_IO_BASE & 0xFF) | 1; - pmio_write(0x2c, byte & 0xFF); - pmio_write(0x2d, SMBUS_IO_BASE >> 8); - - /* AcpiMMioDecodeEn */ - byte = pmio_read(0x24); - byte |= 1; - byte &= ~(1 << 1); - pmio_write(0x24, byte); - /* enable smbus controller interface */ - //byte = pci_read_config8(dev, 0xd2); - //byte |= (1 << 0); - //pci_write_config8(dev, 0xd2, byte); - - /* KB2RstEnable */ - //pci_write_config8(dev, 0x40, 0x44); - - /* Enable ISA Address 0-960K decoding */ - //pci_write_config8(dev, 0x48, 0x0f); - - /* Enable ISA Address 0xC0000-0xDFFFF decode */ - //pci_write_config8(dev, 0x49, 0xff); - - /* Enable decode cycles to IO C50, C51, C52 GPM controls. */ - //byte = pci_read_config8(dev, 0x41); - //byte &= 0x80; - //byte |= 0x33; - //pci_write_config8(dev, 0x41, byte); - - /* Legacy DMA Prefetch Enhancement, CIM masked it. */ - /* pci_write_config8(dev, 0x43, 0x1); */ - - /* clear any lingering errors, so the transaction will run */ - outb(inb(SMBUS_IO_BASE + SMBHSTSTAT), SMBUS_IO_BASE + SMBHSTSTAT); - - /* IDE Device, BDF:0-20-1 */ - printk(BIOS_INFO, "sb800_devices_por_init(): IDE Device, BDF:0-20-1\n"); - dev = PCI_DEV(0, 0x14, 1); - /* Disable prefetch */ - byte = pci_read_config8(dev, 0x63); - byte |= 0x1; - pci_write_config8(dev, 0x63, byte); - - /* LPC Device, BDF:0-20-3 */ - printk(BIOS_INFO, "sb800_devices_por_init(): LPC Device, BDF:0-20-3\n"); - dev = PCI_DEV(0, 0x14, 3); - /* DMA enable */ - pci_write_config8(dev, 0x40, 0x04); - - /* LPC Sync Timeout */ - pci_write_config8(dev, 0x49, 0xFF); - - /* Set LPC ROM size, it has been done in sb800_lpc_init(). - * enable LPC ROM range, 0xfff8: 512KB, 0xfff0: 1MB; - * enable LPC ROM range, 0xfff8: 512KB, 0xfff0: 1MB - * pci_write_config16(dev, 0x68, 0x000e) - * pci_write_config16(dev, 0x6c, 0xfff0);*/ - - /* Enable Tpm12_en and Tpm_legacy. I don't know what is its usage and copied from CIM. */ - pci_write_config8(dev, 0x7C, 0x05); - - /* P2P Bridge, BDF:0-20-4, the configuration of the registers in this dev are copied from CIM, - */ - printk(BIOS_INFO, "sb800_devices_por_init(): P2P Bridge, BDF:0-20-4\n"); - dev = PCI_DEV(0, 0x14, 4); - - /* Arbiter enable. */ - pci_write_config8(dev, 0x43, 0xff); - - /* Set PCDMA request into height priority list. */ - /* pci_write_config8(dev, 0x49, 0x1); */ - - pci_write_config8(dev, 0x40, 0x26); - - pci_write_config8(dev, 0x0d, 0x40); - pci_write_config8(dev, 0x1b, 0x40); - /* Enable PCIB_DUAL_EN_UP will fix potential problem with PCI cards. */ - pci_write_config8(dev, 0x50, 0x01); - - /* SATA Device, BDF:0-17-0, Non-Raid-5 SATA controller */ - printk(BIOS_INFO, "sb800_devices_por_init(): SATA Device, BDF:0-18-0\n"); - dev = PCI_DEV(0, 0x11, 0); - - /*PHY Global Control*/ - pci_write_config16(dev, 0x86, 0x2C00); -} - -/* sbPmioPorInitTable, Pre-initializing PMIO register space -* The power management (PM) block is resident in the PCI/LPC/ISA bridge. -* The PM regs are accessed via IO mapped regs 0xcd6 and 0xcd7. -* The index address is first programmed into IO reg 0xcd6. -* Read or write values are accessed through IO reg 0xcd7. -*/ -#if 0 -static void sb800_pmio_por_init(void) -{ - u8 byte, i; - - printk(BIOS_INFO, "sb800_pmio_por_init()\n"); - - byte = pmio_read(0xD2); - byte |= 3 << 4; - pmio_write(0xD2, byte); - - byte = pmio_read(0x5D); - byte &= 3; - byte |= 1; - pmio_write(0x5D, byte); - - /* Watch Dog Timer Control - * Set watchdog time base to 0xfec000f0 to avoid SCSI card boot failure. - * But I don't find WDT is enabled in SMBUS 0x41 bit3 in CIM. - */ - pmio_write(0x6c, 0xf0); - pmio_write(0x6d, 0x00); - pmio_write(0x6e, 0xc0); - pmio_write(0x6f, 0xfe); - - /* rpr2.15: Enabling Spread Spectrum */ - byte = pmio_read(0x42); - byte |= 1 << 7; - pmio_write(0x42, byte); - /* TODO: Check if it is necessary. IDE reset */ - byte = pmio_read(0xB2); - byte |= 1 << 0; - pmio_write(0xB2, byte); - - for (i = 0; i < sizeof(pm_table)/sizeof(struct pm_entry); i++) { - byte = pmio_read(pm_table[i].port); - byte &= pm_table[i].mask; - byte |= pm_table[i].bit; - pmio_write(pm_table[i].port, byte); - } - pmio_write(0x00, 0x0E); - pmio_write(0x01, 0x00); - pmio_write(0x02, 0x4F); - pmio_write(0x03, 0x4A); -} -#endif - -/* -* Add any south bridge setting. -*/ -static void sb800_pci_cfg(void) -{ - pci_devfn_t dev; - u8 byte; - - /* SMBus Device, BDF:0-20-0 */ - dev = PCI_DEV(0, 0x14, 0); - /* Enable watchdog decode timer */ - byte = pci_read_config8(dev, 0x41); - byte |= (1 << 3); - pci_write_config8(dev, 0x41, byte); - - /* rpr 7.4. Set to 1 to reset USB on the software (such as IO-64 or IO-CF9 cycles) - * generated PCIRST#. */ - byte = pmio_read(0xF0); - byte |= (1 << 2); - pmio_write(0xF0, byte); - - /* IDE Device, BDF:0-20-1 */ - dev = PCI_DEV(0, 0x14, 1); - /* Enable IDE Explicit prefetch, 0x63[0] clear */ - byte = pci_read_config8(dev, 0x63); - byte &= 0xfe; - pci_write_config8(dev, 0x63, byte); - - /* LPC Device, BDF:0-20-3 */ - /* The code below is ported from old chipset. It is not - * Mentioned in RPR. But I keep them. The registers and the - * comments are compatible. */ - dev = PCI_DEV(0, 0x14, 3); - /* Enabling LPC DMA function. */ - byte = pci_read_config8(dev, 0x40); - byte |= (1 << 2); - pci_write_config8(dev, 0x40, byte); - /* Disabling LPC TimeOut. 0x48[7] clear. */ - byte = pci_read_config8(dev, 0x48); - byte &= 0x7f; - pci_write_config8(dev, 0x48, byte); - /* Disabling LPC MSI Capability, 0x78[1] clear. */ - byte = pci_read_config8(dev, 0x78); - byte &= 0xfd; - pci_write_config8(dev, 0x78, byte); - - /* SATA Device, BDF:0-17-0, Non-Raid-5 SATA controller */ - dev = PCI_DEV(0, 0x11, 0); - /* rpr7.12 SATA MSI and D3 Power State Capability. */ - byte = pci_read_config8(dev, 0x40); - byte |= 1 << 0; - pci_write_config8(dev, 0x40, byte); - if (get_sb800_revision() <= 0x12) - pci_write_config8(dev, 0x34, 0x70); /* set 0x61 to 0x70 if S1 is not supported. */ - else - pci_write_config8(dev, 0x34, 0x50); /* set 0x61 to 0x50 if S1 is not supported. */ - byte &= ~(1 << 0); - pci_write_config8(dev, 0x40, byte); -} - -/* -*/ -static void sb800_por_init(void) -{ - /* sbDevicesPorInitTable + sbK8PorInitTable */ - sb800_devices_por_init(); - - /* sbPmioPorInitTable + sbK8PmioPorInitTable */ - //sb800_pmio_por_init(); -} - -/* -* It should be called during early POST after memory detection and BIOS shadowing but before PCI bus enumeration. -*/ -static void sb800_before_pci_init(void) -{ - sb800_pci_cfg(); -} - -/* -* This function should be called after enable_sb800_smbus(). -*/ -static void sb800_early_setup(void) -{ - printk(BIOS_INFO, "sb800_early_setup()\n"); - sb800_por_init(); - sb800_acpi_init(); -} - -int s3_save_nvram_early(u32 dword, int size, int nvram_pos) -{ - int i; - printk(BIOS_DEBUG, "Writing %x of size %d to nvram pos: %d\n", dword, size, nvram_pos); - - for (i = 0; i < size; i++) { - outb(nvram_pos, BIOSRAM_INDEX); - outb((dword >> (8 * i)) & 0xff, BIOSRAM_DATA); - nvram_pos++; - } - - return nvram_pos; -} - -int s3_load_nvram_early(int size, u32 *old_dword, int nvram_pos) -{ - u32 data = *old_dword; - int i; - for (i = 0; i < size; i++) { - outb(nvram_pos, BIOSRAM_INDEX); - data &= ~(0xff << (i * 8)); - data |= inb(BIOSRAM_DATA) << (i *8); - nvram_pos++; - } - *old_dword = data; - printk(BIOS_DEBUG, "Loading %x of size %d to nvram pos:%d\n", *old_dword, size, - nvram_pos-size); - return nvram_pos; -} - -#endif diff --git a/src/southbridge/amd/sb800/enable_usbdebug.c b/src/southbridge/amd/sb800/enable_usbdebug.c deleted file mode 100644 index 2c193cbe4c..0000000000 --- a/src/southbridge/amd/sb800/enable_usbdebug.c +++ /dev/null @@ -1,53 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2010 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -// Use simple device model for this file even in ramstage -#define __SIMPLE_DEVICE__ - -#include -#include -#include -#include -#include -#include "sb800.h" - -#define DEBUGPORT_MISC_CONTROL 0x80 - -pci_devfn_t pci_ehci_dbg_dev(unsigned int hcd_idx) -{ - /* Enable all of the USB controllers */ - outb(0xEF, PM_INDEX); - outb(0x7F, PM_DATA); - - if (hcd_idx == 3) - return PCI_DEV(0, 0x16, 2); - else if (hcd_idx == 2) - return PCI_DEV(0, 0x13, 2); - else - return PCI_DEV(0, 0x12, 2); -} - -void pci_ehci_dbg_set_port(pci_devfn_t dev, unsigned int port) -{ - u8 *base_regs = pci_ehci_base_regs(dev); - u32 reg32; - - /* Write the port number to DEBUGPORT_MISC_CONTROL[31:28]. */ - reg32 = read32(base_regs + DEBUGPORT_MISC_CONTROL); - reg32 &= ~(0xf << 28); - reg32 |= (port << 28); - reg32 |= (1 << 27); /* Enable Debug Port port number remapping. */ - write32(base_regs + DEBUGPORT_MISC_CONTROL, reg32); -} diff --git a/src/southbridge/amd/sb800/fadt.c b/src/southbridge/amd/sb800/fadt.c deleted file mode 100644 index acda6dbd52..0000000000 --- a/src/southbridge/amd/sb800/fadt.c +++ /dev/null @@ -1,162 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2010 Advanced Micro Devices, Inc. - * Copyright (C) 2015 Raptor Engineering - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -/* - * ACPI - create the Fixed ACPI Description Tables (FADT) - */ - -#include -#include -#include -#include -#include -#include - -#include "sb800.h" - -void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt) -{ - acpi_header_t *header = &(fadt->header); - - printk(BIOS_DEBUG, "pm_base: 0x%04x\n", SB800_ACPI_IO_BASE); - - /* Prepare the header */ - memset((void *)fadt, 0, sizeof(acpi_fadt_t)); - memcpy(header->signature, "FACP", 4); - header->length = sizeof(acpi_fadt_t); - header->revision = get_acpi_table_revision(FADT); - memcpy(header->oem_id, OEM_ID, 6); - memcpy(header->oem_table_id, ACPI_TABLE_CREATOR, 8); - memcpy(header->asl_compiler_id, ASLC, 4); - header->asl_compiler_revision = asl_revision; - - fadt->firmware_ctrl = (u32) facs; - fadt->dsdt = (u32) dsdt; - /* 3=Workstation,4=Enterprise Server, 7=Performance Server */ - fadt->preferred_pm_profile = 0x03; - fadt->sci_int = 9; - /* disable system management mode by setting to 0: */ - fadt->smi_cmd = 0; - fadt->acpi_enable = 0xf0; - fadt->acpi_disable = 0xf1; - fadt->s4bios_req = 0x0; - fadt->pstate_cnt = 0xe2; - fadt->pm1a_evt_blk = ACPI_PM_EVT_BLK; - fadt->pm1b_evt_blk = 0x0000; - fadt->pm1a_cnt_blk = ACPI_PM1_CNT_BLK; - fadt->pm1b_cnt_blk = 0x0000; - fadt->pm2_cnt_blk = ACPI_PMA_CNT_BLK; - fadt->pm_tmr_blk = ACPI_PM_TMR_BLK; - fadt->gpe0_blk = ACPI_GPE0_BLK; - fadt->gpe1_blk = 0x0000; /* we don't have gpe1 block, do we? */ - - fadt->pm1_evt_len = 4; - fadt->pm1_cnt_len = 2; - fadt->pm2_cnt_len = 1; - fadt->pm_tmr_len = 4; - fadt->gpe0_blk_len = 8; - fadt->gpe1_blk_len = 0; - fadt->gpe1_base = 0; - - fadt->cst_cnt = 0xe3; - fadt->p_lvl2_lat = 101; - fadt->p_lvl3_lat = 1001; - fadt->flush_size = 0; - fadt->flush_stride = 0; - fadt->duty_offset = 1; - fadt->duty_width = 3; - fadt->day_alrm = 0; /* 0x7d these have to be */ - fadt->mon_alrm = 0; /* 0x7e added to cmos.layout */ - fadt->century = 0; /* 0x7f to make rtc alarm work */ - fadt->iapc_boot_arch = 0x3; /* See table 5-11 */ - fadt->flags = 0x0001c1a5;/* 0x25; */ - - fadt->res2 = 0; - - fadt->reset_reg.space_id = 1; - fadt->reset_reg.bit_width = 8; - fadt->reset_reg.bit_offset = 0; - fadt->reset_reg.access_size = 0; - fadt->reset_reg.addrl = 0xcf9; - fadt->reset_reg.addrh = 0x0; - - fadt->reset_value = 6; - fadt->x_firmware_ctl_l = (u32) facs; - fadt->x_firmware_ctl_h = 0; - fadt->x_dsdt_l = (u32) dsdt; - fadt->x_dsdt_h = 0; - - fadt->x_pm1a_evt_blk.space_id = 1; - fadt->x_pm1a_evt_blk.bit_width = 32; - fadt->x_pm1a_evt_blk.bit_offset = 0; - fadt->x_pm1a_evt_blk.access_size = 0; - fadt->x_pm1a_evt_blk.addrl = ACPI_PM_EVT_BLK; - fadt->x_pm1a_evt_blk.addrh = 0x0; - - fadt->x_pm1b_evt_blk.space_id = 1; - fadt->x_pm1b_evt_blk.bit_width = 4; - fadt->x_pm1b_evt_blk.bit_offset = 0; - fadt->x_pm1b_evt_blk.access_size = 0; - fadt->x_pm1b_evt_blk.addrl = 0x0; - fadt->x_pm1b_evt_blk.addrh = 0x0; - - fadt->x_pm1a_cnt_blk.space_id = 1; - fadt->x_pm1a_cnt_blk.bit_width = 16; - fadt->x_pm1a_cnt_blk.bit_offset = 0; - fadt->x_pm1a_cnt_blk.access_size = 0; - fadt->x_pm1a_cnt_blk.addrl = ACPI_PM1_CNT_BLK; - fadt->x_pm1a_cnt_blk.addrh = 0x0; - - fadt->x_pm1b_cnt_blk.space_id = 1; - fadt->x_pm1b_cnt_blk.bit_width = 2; - fadt->x_pm1b_cnt_blk.bit_offset = 0; - fadt->x_pm1b_cnt_blk.access_size = 0; - fadt->x_pm1b_cnt_blk.addrl = 0x0; - fadt->x_pm1b_cnt_blk.addrh = 0x0; - - fadt->x_pm2_cnt_blk.space_id = 1; - fadt->x_pm2_cnt_blk.bit_width = 0; - fadt->x_pm2_cnt_blk.bit_offset = 0; - fadt->x_pm2_cnt_blk.access_size = 0; - fadt->x_pm2_cnt_blk.addrl = ACPI_PMA_CNT_BLK; - fadt->x_pm2_cnt_blk.addrh = 0x0; - - fadt->x_pm_tmr_blk.space_id = 1; - fadt->x_pm_tmr_blk.bit_width = 32; - fadt->x_pm_tmr_blk.bit_offset = 0; - fadt->x_pm_tmr_blk.access_size = 0; - fadt->x_pm_tmr_blk.addrl = ACPI_PM_TMR_BLK; - fadt->x_pm_tmr_blk.addrh = 0x0; - - fadt->x_gpe0_blk.space_id = 1; - fadt->x_gpe0_blk.bit_width = 32; - fadt->x_gpe0_blk.bit_offset = 0; - fadt->x_gpe0_blk.access_size = 0; - fadt->x_gpe0_blk.addrl = ACPI_GPE0_BLK; - fadt->x_gpe0_blk.addrh = 0x0; - - fadt->x_gpe1_blk.space_id = 1; - fadt->x_gpe1_blk.bit_width = 0; - fadt->x_gpe1_blk.bit_offset = 0; - fadt->x_gpe1_blk.access_size = 0; - fadt->x_gpe1_blk.addrl = 0; - fadt->x_gpe1_blk.addrh = 0x0; - - if (CONFIG(CPU_AMD_MODEL_10XXX)) - amd_powernow_update_fadt(fadt); - - header->checksum = acpi_checksum((void *)fadt, sizeof(acpi_fadt_t)); -} diff --git a/src/southbridge/amd/sb800/hda.c b/src/southbridge/amd/sb800/hda.c deleted file mode 100644 index 8cac15369d..0000000000 --- a/src/southbridge/amd/sb800/hda.c +++ /dev/null @@ -1,209 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2010 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include -#include -#include -#include -#include -#include "sb800.h" - -#define HDA_ICII_REG 0x68 -#define HDA_ICII_BUSY (1 << 0) -#define HDA_ICII_VALID (1 << 1) - -static int set_bits(void *port, u32 mask, u32 val) -{ - u32 dword; - int count; - - /* Write (val & ~mask) to port */ - val &= mask; - dword = read32(port); - dword &= ~mask; - dword |= val; - write32(port, dword); - - /* Wait for readback of register to - * match what was just written to it - */ - count = 50; - do { - /* Wait 1ms based on BKDG wait time */ - mdelay(1); - dword = read32(port); - dword &= mask; - } while ((dword != val) && --count); - - /* Timeout occurred */ - if (!count) - return -1; - return 0; -} - -static u32 codec_detect(void *base) -{ - u32 dword; - - /* Before Codec detection, we need to set the GPIO167-170 as - * AZ_SDINx. */ - /* Set Bit0 to 0 to enter reset state (BAR + 0x8)[0] */ - if (set_bits(base + 0x08, 1, 0) == -1) - goto no_codec; - - /* Set Bit 0 to 1 to exit reset state (BAR + 0x8)[0] */ - if (set_bits(base + 0x08, 1, 1) == -1) - goto no_codec; - - /* Delay for 1 ms since the BKDG does */ - mdelay(1); - - /* Read in Codec location (BAR + 0xe)[3..0]*/ - dword = read32(base + 0xe); - dword &= 0x0F; - if (!dword) - goto no_codec; - - return dword; - -no_codec: - /* Codec Not found */ - /* Put HDA back in reset (BAR + 0x8) [0] */ - set_bits(base + 0x08, 1, 0); - printk(BIOS_DEBUG, "No codec!\n"); - return 0; -} - -/** - * Wait 50usec for the codec to indicate it is ready - * no response would imply that the codec is non-operative - */ -static int wait_for_ready(void *base) -{ - /* Use a 50 usec timeout - the Linux kernel uses the - * same duration */ - - int timeout = 50; - - while (timeout--) { - u32 dword = read32(base + HDA_ICII_REG); - if (!(dword & HDA_ICII_BUSY)) - return 0; - udelay(1); - } - - return -1; -} - -/** - * Wait 50usec for the codec to indicate that it accepted - * the previous command. No response would imply that the code - * is non-operative - */ -static int wait_for_valid(void *base) -{ - /* Use a 50 usec timeout - the Linux kernel uses the - * same duration */ - - int timeout = 50; - while (timeout--) { - u32 dword = read32(base + HDA_ICII_REG); - if ((dword & (HDA_ICII_VALID | HDA_ICII_BUSY)) == - HDA_ICII_VALID) - return 0; - udelay(1); - } - - return -1; -} - -static void codec_init(void *base, int addr) -{ - u32 dword; - - /* 1 */ - if (wait_for_ready(base) == -1) - return; - - dword = (addr << 28) | 0x000f0000; - write32(base + 0x60, dword); - - if (wait_for_valid(base) == -1) - return; - - dword = read32(base + 0x64); - - /* 2 */ - printk(BIOS_DEBUG, "%x(th) codec viddid: %08x\n", addr, dword); -} - -static void codecs_init(void *base, u32 codec_mask) -{ - int i; - for (i = 3; i >= 0; i--) { - if (codec_mask & (1 << i)) - codec_init(base, i); - } -} - -static void hda_init(struct device *dev) -{ - u32 dword; - void *base; - struct resource *res; - u32 codec_mask; - - /* Program the 2C to 0x437b1002 */ - dword = 0x43831002; - pci_write_config32(dev, 0x2c, dword); - - /* Read in BAR */ - /* Is this right? HDA allows for a 64-bit BAR - * but this is only setup for a 32-bit one - */ - res = find_resource(dev, 0x10); - if (!res) - return; - - base = res2mmio(res, 0, 0); - printk(BIOS_DEBUG, "base = 0x%p\n", base); - codec_mask = codec_detect(base); - - if (codec_mask) { - printk(BIOS_DEBUG, "codec_mask = %02x\n", codec_mask); - codecs_init(base, codec_mask); - } -} - -static struct pci_operations lops_pci = { - .set_subsystem = pci_dev_set_subsystem, -}; - -static struct device_operations hda_audio_ops = { - .read_resources = pci_dev_read_resources, - .set_resources = pci_dev_set_resources, - .enable_resources = pci_dev_enable_resources, - .init = hda_init, - .scan_bus = 0, - .ops_pci = &lops_pci, -}; - -static const struct pci_driver hdaaudio_driver __pci_driver = { - .ops = &hda_audio_ops, - .vendor = PCI_VENDOR_ID_ATI, - .device = PCI_DEVICE_ID_ATI_SB800_HDA, -}; diff --git a/src/southbridge/amd/sb800/ide.c b/src/southbridge/amd/sb800/ide.c deleted file mode 100644 index 77e2f5ef1d..0000000000 --- a/src/southbridge/amd/sb800/ide.c +++ /dev/null @@ -1,75 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2010 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include -#include -#include "sb800.h" -#include "chip.h" - -static void ide_init(struct device *dev) -{ - struct southbridge_amd_sb800_config *conf; - /* Enable ide devices so the linux ide driver will work */ - u32 dword; - u8 byte; - - conf = dev->chip_info; - - /* RPR9.1 disable MSI */ - /* TODO: For A14, it should set as 1. I doubt it. */ - dword = pci_read_config32(dev, 0x70); - dword &= ~(1 << 16); - pci_write_config32(dev, 0x70, dword); - - /* Ultra DMA mode */ - /* enable UDMA */ - byte = pci_read_config8(dev, 0x54); - byte |= 1 << 0; - pci_write_config8(dev, 0x54, byte); - - /* Enable I/O Access&& Bus Master */ - dword = pci_read_config16(dev, 0x4); - dword |= 1 << 2; - pci_write_config16(dev, 0x4, dword); - - /* set ide as primary, if you want to boot from IDE, you'd better set it - * in mainboard/Config.lb */ - if (conf->boot_switch_sata_ide == 1) { - byte = pci_read_config8(dev, 0xAD); - byte |= 1 << 4; - pci_write_config8(dev, 0xAD, byte); - } -} - -static struct pci_operations lops_pci = { - .set_subsystem = pci_dev_set_subsystem, -}; - -static struct device_operations ide_ops = { - .read_resources = pci_dev_read_resources, - .set_resources = pci_dev_set_resources, - .enable_resources = pci_dev_enable_resources, - .init = ide_init, - .scan_bus = 0, - .ops_pci = &lops_pci, -}; - -static const struct pci_driver ide_driver __pci_driver = { - .ops = &ide_ops, - .vendor = PCI_VENDOR_ID_ATI, - .device = PCI_DEVICE_ID_ATI_SB800_IDE, -}; diff --git a/src/southbridge/amd/sb800/lpc.c b/src/southbridge/amd/sb800/lpc.c deleted file mode 100644 index 0ca50cce74..0000000000 --- a/src/southbridge/amd/sb800/lpc.c +++ /dev/null @@ -1,261 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2010 Advanced Micro Devices, Inc. - * Copyright (C) 2015 Timothy Pearson , Raptor Engineering - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include "sb800.h" - -static void lpc_init(struct device *dev) -{ - u8 byte; - u32 dword; - struct device *sm_dev; - - /* Enable the LPC Controller */ - sm_dev = pcidev_on_root(0x14, 0); - dword = pci_read_config32(sm_dev, 0x64); - dword |= 1 << 20; - pci_write_config32(sm_dev, 0x64, dword); - - /* Initialize isa dma */ - isa_dma_init(); - - /* Enable DMA transaction on the LPC bus */ - byte = pci_read_config8(dev, 0x40); - byte |= (1 << 2); - pci_write_config8(dev, 0x40, byte); - - /* Disable the timeout mechanism on LPC */ - byte = pci_read_config8(dev, 0x48); - byte &= ~(1 << 7); - pci_write_config8(dev, 0x48, byte); - - /* Disable LPC MSI Capability */ - byte = pci_read_config8(dev, 0x78); - byte &= ~(1 << 1); - byte &= ~(1 << 0); /* Keep the old way. i.e., when bus master/DMA cycle is going - on on LPC, it holds PCI grant, so no LPC slave cycle can - interrupt and visit LPC. */ - pci_write_config8(dev, 0x78, byte); - - /* bit0: Enable prefetch a cacheline (64 bytes) when Host reads code from SPI ROM */ - /* bit3: Fix SPI_CS# timing issue when running at 66M. TODO:A12. */ - byte = pci_read_config8(dev, 0xBB); - byte |= 1 << 0 | 1 << 3; - pci_write_config8(dev, 0xBB, byte); - - cmos_check_update_date(); - - setup_i8259(); /* Initialize i8259 pic */ - setup_i8254(); /* Initialize i8254 timers */ -} - -static void sb800_lpc_read_resources(struct device *dev) -{ - struct resource *res; - - /* Get the normal pci resources of this device */ - pci_dev_read_resources(dev); /* We got one for APIC, or one more for TRAP */ - - pci_get_resource(dev, 0xA0); /* SPI ROM base address */ - - /* Add an extra subtractive resource for both memory and I/O. */ - res = new_resource(dev, IOINDEX_SUBTRACTIVE(0, 0)); - res->base = 0; - res->size = 0x1000; - res->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE | - IORESOURCE_ASSIGNED | IORESOURCE_FIXED; - - res = new_resource(dev, IOINDEX_SUBTRACTIVE(1, 0)); - res->base = 0xff800000; - res->size = 0x00800000; /* 8 MB for flash */ - res->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE | - IORESOURCE_ASSIGNED | IORESOURCE_FIXED; - - //res = new_resource(dev, 3); - //res->base = IO_APIC_ADDR; - //res->size = 0x00001000; - //res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; - - compact_resources(dev); -} - -static void sb800_lpc_set_resources(struct device *dev) -{ - struct resource *res; - - pci_dev_set_resources(dev); - - /* Special case. SPI Base Address. The SpiRomEnable should be set. */ - res = find_resource(dev, 0xA0); - pci_write_config32(dev, 0xA0, res->base | 1 << 1); - -} - -/** - * @brief Enable resources for children devices - * - * @param dev the device whose children's resources are to be enabled - * - */ -static void sb800_lpc_enable_childrens_resources(struct device *dev) -{ - struct bus *link; - u32 reg, reg_x; - int var_num = 0; - u16 reg_var[3] = {0x0, 0x0, 0x0}; - u8 wiosize = pci_read_config8(dev, 0x74); - - reg = pci_read_config32(dev, 0x44); - reg_x = pci_read_config32(dev, 0x48); - - for (link = dev->link_list; link; link = link->next) { - struct device *child; - for (child = link->children; child; - child = child->sibling) { - if (child->enabled - && (child->path.type == DEVICE_PATH_PNP)) { - struct resource *res; - for (res = child->resource_list; res; res = res->next) { - u32 base, end; /* don't need long long */ - if (!(res->flags & IORESOURCE_IO)) - continue; - base = res->base; - end = resource_end(res); - printk(BIOS_DEBUG, "sb800 lpc decode:%s, base=0x%08x, end=0x%08x\n", - dev_path(child), base, end); - switch (base) { - case 0x60: /* KB */ - case 0x64: /* MS */ - reg |= (1 << 29); - break; - case 0x3f8: /* COM1 */ - reg |= (1 << 6); - break; - case 0x2f8: /* COM2 */ - reg |= (1 << 7); - break; - case 0x378: /* Parallel 1 */ - reg |= (1 << 0); - reg |= (1 << 1); /* + 0x778 for ECP */ - break; - case 0x3f0: /* FD0 */ - reg |= (1 << 26); - break; - case 0x220: /* Audio 0 */ - reg |= (1 << 8); - break; - case 0x300: /* Midi 0 */ - reg |= (1 << 18); - break; - case 0x400: - reg_x |= (1 << 16); - break; - case 0x480: - reg_x |= (1 << 17); - break; - case 0x500: - reg_x |= (1 << 18); - break; - case 0x580: - reg_x |= (1 << 19); - break; - case 0x4700: - reg_x |= (1 << 22); - break; - case 0xfd60: - reg_x |= (1 << 23); - break; - default: - if (var_num >= 3) - continue; /* only 3 var ; compact them ? */ - switch (var_num) { - case 0: - reg_x |= (1 << 2); - if ((end - base) < 16) - wiosize |= (1 << 0); - break; - case 1: - reg_x |= (1 << 24); - if ((end - base) < 16) - wiosize |= (1 << 2); - break; - case 2: - reg_x |= (1 << 25); - reg_x |= (1 << 24); - if ((end - base) < 16) - wiosize |= (1 << 3); - break; - } - reg_var[var_num++] = - base & 0xffff; - } - } - } - } - } - pci_write_config32(dev, 0x44, reg); - pci_write_config32(dev, 0x48, reg_x); - /* Set WideIO for as many IOs found (fall through is on purpose) */ - switch (var_num) { - case 3: - pci_write_config16(dev, 0x90, reg_var[2]); - /* fall through */ - case 2: - pci_write_config16(dev, 0x66, reg_var[1]); - /* fall through */ - case 1: - pci_write_config16(dev, 0x64, reg_var[0]); - break; - } - pci_write_config8(dev, 0x74, wiosize); -} - -static void sb800_lpc_enable_resources(struct device *dev) -{ - pci_dev_enable_resources(dev); - sb800_lpc_enable_childrens_resources(dev); -} - -static struct pci_operations lops_pci = { - .set_subsystem = pci_dev_set_subsystem, -}; - -static struct device_operations lpc_ops = { - .read_resources = sb800_lpc_read_resources, - .set_resources = sb800_lpc_set_resources, - .enable_resources = sb800_lpc_enable_resources, -#if CONFIG(HAVE_ACPI_TABLES) - .write_acpi_tables = acpi_write_hpet, -#endif - .init = lpc_init, - .scan_bus = scan_static_bus, - .ops_pci = &lops_pci, -}; -static const struct pci_driver lpc_driver __pci_driver = { - .ops = &lpc_ops, - .vendor = PCI_VENDOR_ID_ATI, - .device = PCI_DEVICE_ID_ATI_SB800_LPC, -}; diff --git a/src/southbridge/amd/sb800/pci.c b/src/southbridge/amd/sb800/pci.c deleted file mode 100644 index 025d0a3643..0000000000 --- a/src/southbridge/amd/sb800/pci.c +++ /dev/null @@ -1,71 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2010 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include -#include -#include "sb800.h" - -static void pci_init(struct device *dev) -{ - u32 dword; - u8 byte; - - /* RPR 6.1 Enables the PCI-bridge subtractive decode */ - /* This setting is strongly recommended since it supports some legacy PCI add-on cards,such as BIOS debug cards */ - byte = pci_read_config8(dev, 0x4B); - byte |= 1 << 7; - pci_write_config8(dev, 0x4B, byte); - byte = pci_read_config8(dev, 0x40); - byte |= 1 << 5; - pci_write_config8(dev, 0x40, byte); - - /* RPR6.2 PCI-bridge upstream dual address window */ - /* this setting is applicable if the system memory is more than 4GB,and the PCI device can support dual address access */ - byte = pci_read_config8(dev, 0x50); - byte |= 1 << 0; - pci_write_config8(dev, 0x50, byte); - - /* RPR 6.3 Enable One-Prefetch-Channel Mode */ - dword = pci_read_config32(dev, 0x64); - dword |= 1 << 20; - pci_write_config32(dev, 0x64, dword); - - /* rpr6.4 Adjusting CLKRUN# */ - dword = pci_read_config32(dev, 0x64); - dword |= (1 << 15); - pci_write_config32(dev, 0x64, dword); -} - -static struct pci_operations lops_pci = { - .set_subsystem = 0, -}; - -static struct device_operations pci_ops = { - .read_resources = pci_bus_read_resources, - .set_resources = pci_dev_set_resources, - .enable_resources = pci_bus_enable_resources, - .init = pci_init, - .scan_bus = pci_scan_bridge, - .reset_bus = pci_bus_reset, - .ops_pci = &lops_pci, -}; - -static const struct pci_driver pci_driver __pci_driver = { - .ops = &pci_ops, - .vendor = PCI_VENDOR_ID_ATI, - .device = PCI_DEVICE_ID_ATI_SB800_PCI, -}; diff --git a/src/southbridge/amd/sb800/pcie.c b/src/southbridge/amd/sb800/pcie.c deleted file mode 100644 index d0c5260910..0000000000 --- a/src/southbridge/amd/sb800/pcie.c +++ /dev/null @@ -1,71 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2010 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include -#include -#include -#include "sb800.h" - -static void pcie_init(struct device *dev) -{ - /* Enable pci error detecting */ - u32 dword; - - printk(BIOS_INFO, "pcie_init in rs780_ht.c\n"); - - /* System error enable */ - dword = pci_read_config32(dev, 0x04); - dword |= (1 << 8); /* System error enable */ - dword |= (1 << 30); /* Clear possible errors */ - pci_write_config32(dev, 0x04, dword); -} - -static struct pci_operations lops_pci = { - .set_subsystem = 0, -}; - -static struct device_operations pci_ops = { - .read_resources = pci_bus_read_resources, - .set_resources = pci_dev_set_resources, - .enable_resources = pci_bus_enable_resources, - .init = pcie_init, - .scan_bus = pci_scan_bridge, - .reset_bus = pci_bus_reset, - .ops_pci = &lops_pci, -}; - -static const struct pci_driver pciea_driver __pci_driver = { - .ops = &pci_ops, - .vendor = PCI_VENDOR_ID_ATI, - .device = PCI_DEVICE_ID_ATI_SB800_PCIEA, -}; - -static const struct pci_driver pcieb_driver __pci_driver = { - .ops = &pci_ops, - .vendor = PCI_VENDOR_ID_ATI, - .device = PCI_DEVICE_ID_ATI_SB800_PCIEB, -}; -static const struct pci_driver pciec_driver __pci_driver = { - .ops = &pci_ops, - .vendor = PCI_VENDOR_ID_ATI, - .device = PCI_DEVICE_ID_ATI_SB800_PCIEC, -}; -static const struct pci_driver pcied_driver __pci_driver = { - .ops = &pci_ops, - .vendor = PCI_VENDOR_ID_ATI, - .device = PCI_DEVICE_ID_ATI_SB800_PCIED, -}; diff --git a/src/southbridge/amd/sb800/ramtop.c b/src/southbridge/amd/sb800/ramtop.c deleted file mode 100644 index 889c699379..0000000000 --- a/src/southbridge/amd/sb800/ramtop.c +++ /dev/null @@ -1,51 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2010 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include -#include -#include "sb800.h" - -int acpi_get_sleep_type(void) -{ - u16 tmp; - tmp = inw(ACPI_PM1_CNT_BLK); - return ((tmp & (7 << 10)) >> 10); -} - -void backup_top_of_low_cacheable(uintptr_t ramtop) -{ - u32 dword = ramtop; - int nvram_pos = 0xfc, i; - for (i = 0; i < 4; i++) { - outb(nvram_pos, BIOSRAM_INDEX); - outb((dword >> (8 * i)) & 0xff, BIOSRAM_DATA); - nvram_pos++; - } -} - -uintptr_t restore_top_of_low_cacheable(void) -{ - uint32_t xdata = 0; - int xnvram_pos = 0xfc, xi; - for (xi = 0; xi < 4; xi++) { - outb(xnvram_pos, BIOSRAM_INDEX); - xdata &= ~(0xff << (xi * 8)); - xdata |= inb(BIOSRAM_DATA) << (xi *8); - xnvram_pos++; - } - return xdata; -} diff --git a/src/southbridge/amd/sb800/reset.c b/src/southbridge/amd/sb800/reset.c deleted file mode 100644 index bd578b6c0d..0000000000 --- a/src/southbridge/amd/sb800/reset.c +++ /dev/null @@ -1,31 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2010 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -// Use simple device model for this file even in ramstage -#define __SIMPLE_DEVICE__ - -#include -#include - -#include - -void do_board_reset(void) -{ - set_bios_reset(); - /* Try rebooting through port 0xcf9 */ - /* Actually it is not a real hard_reset --- it only reset coherent link table, but not reset link freq and width */ - outb((0 << 3) | (0 << 2) | (1 << 1), 0xcf9); - outb((0 << 3) | (1 << 2) | (1 << 1), 0xcf9); -} diff --git a/src/southbridge/amd/sb800/sata.c b/src/southbridge/amd/sb800/sata.c deleted file mode 100644 index 8611272d78..0000000000 --- a/src/southbridge/amd/sb800/sata.c +++ /dev/null @@ -1,268 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2010 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include "sb800.h" -#include "chip.h" - -static int sata_drive_detect(int portnum, u16 iobar) -{ - u8 byte, byte2; - int i = 0; - outb(0xA0 + 0x10 * (portnum % 2), iobar + 0x6); - while (byte = inb(iobar + 0x6), byte2 = inb(iobar + 0x7), - (byte != (0xA0 + 0x10 * (portnum % 2))) || - ((byte2 & 0x88) != 0)) { - printk(BIOS_SPEW, "0x6=%x, 0x7=%x\n", byte, byte2); - if (byte != (0xA0 + 0x10 * (portnum % 2))) { - /* This will happen at the first iteration of this loop - * if the first SATA port is unpopulated and the - * second SATA port is populated. - */ - printk(BIOS_DEBUG, "drive no longer selected after %i ms, " - "retrying init\n", i * 10); - return 1; - } else - printk(BIOS_SPEW, "drive detection not yet completed, " - "waiting...\n"); - mdelay(10); - i++; - } - printk(BIOS_SPEW, "drive detection done after %i ms\n", i * 10); - return 0; -} - -static void sb800_setup_sata_phys(struct device *dev) -{ - int i; - static const u32 sata_phy[][3] = { - {0x0056A607, 0x00061400, 0x00061302}, /* port 0 */ - {0x0056A607, 0x00061400, 0x00061302}, /* port 1 */ - {0x0056A607, 0x00061402, 0x00064300}, /* port 2 */ - {0x0056A607, 0x00061402, 0x00064300}, /* port 3 */ - {0x0056A700, 0x00061502, 0x00064302}, /* port 4 */ - {0x0056A700, 0x00061502, 0x00064302} /* port 5 */ - }; - /* RPR8.4 */ - /* Port 0 - 5 */ - for (i = 0; i < 6; i++) { - pci_write_config16(dev, 0x84, 0x3006 | i << 9); - pci_write_config32(dev, 0x94, sata_phy[i][0]); /* Gen 3 */ - pci_write_config16(dev, 0x84, 0x2006 | i << 9); - pci_write_config32(dev, 0x94, sata_phy[i][1]); /* Gen 2 */ - pci_write_config16(dev, 0x84, 0x1006 | i << 9); - pci_write_config32(dev, 0x94, sata_phy[i][2]); /* Gen 1 */ - } - -} -static void sata_init(struct device *dev) -{ - u8 byte; - u16 word; - u32 dword; - u8 rev_id; - void *sata_bar5; - u16 sata_bar0, sata_bar1, sata_bar2, sata_bar3, sata_bar4; - int i, j; - - struct southbridge_ati_sb800_config *conf; - conf = dev->chip_info; - - struct device *sm_dev; - /* SATA SMBus Disable */ - sm_dev = pcidev_on_root(0x14, 0); - - /* get rev_id */ - rev_id = pci_read_config8(sm_dev, 0x08) - 0x2F; - - /* get base address */ - sata_bar5 = (void *)(pci_read_config32(dev, 0x24) & ~0x3FF); - sata_bar0 = pci_read_config16(dev, 0x10) & ~0x7; - sata_bar1 = pci_read_config16(dev, 0x14) & ~0x3; - sata_bar2 = pci_read_config16(dev, 0x18) & ~0x7; - sata_bar3 = pci_read_config16(dev, 0x1C) & ~0x3; - sata_bar4 = pci_read_config16(dev, 0x20) & ~0xf; - - printk(BIOS_SPEW, "sata_bar0=%x\n", sata_bar0); /* 3030 */ - printk(BIOS_SPEW, "sata_bar1=%x\n", sata_bar1); /* 3070 */ - printk(BIOS_SPEW, "sata_bar2=%x\n", sata_bar2); /* 3040 */ - printk(BIOS_SPEW, "sata_bar3=%x\n", sata_bar3); /* 3080 */ - printk(BIOS_SPEW, "sata_bar4=%x\n", sata_bar4); /* 3000 */ - printk(BIOS_SPEW, "sata_bar5=%p\n", sata_bar5); /* e0309000 */ - - /* SERR-Enable */ - word = pci_read_config16(dev, 0x04); - word |= (1 << 8); - pci_write_config16(dev, 0x04, word); - - /* Set SATA Operation Mode, Set to IDE mode */ - byte = pci_read_config8(dev, 0x40); - byte |= (1 << 0); - //byte |= (1 << 4); - pci_write_config8(dev, 0x40, byte); - - dword = 0x01018f00; - pci_write_config32(dev, 0x8, dword); - - /* Program the 2C to 0x43801002 */ - dword = 0x43801002; - pci_write_config32(dev, 0x2c, dword); - - pci_write_config8(dev, 0x34, 0x70); /* 8.11 SATA MSI and D3 Power State Capability */ - - dword = read32(sata_bar5 + 0xFC); - dword &= ~(1 << 11); /* rpr 8.8. Disabling Aggressive Link Power Management */ - dword &= ~(1 << 12); /* rpr 8.9.1 Disabling Port Multiplier support. */ - dword &= ~(1 << 10); /* rpr 8.9.2 disabling FIS-based Switching support */ - dword &= ~(1 << 19); /* rpr 8.10. Disabling CCC (Command Completion Coalescing) Support */ - write32((sata_bar5 + 0xFC), dword); - - dword = read32(sata_bar5 + 0xF8); - dword &= ~(0x3F << 22); /* rpr 8.9.2 disabling FIS-based Switching support */ - write32(sata_bar5 + 0xF8, dword); - - byte = pci_read_config8(dev, 0x40); - byte &= ~(1 << 0); - pci_write_config8(dev, 0x40, byte); - - /* rpr 8.3 */ - printk(BIOS_SPEW, "rev_id=%x\n", rev_id); - dword = pci_read_config32(dev, 0x84); - if (rev_id == 0x11) /* A11 */ - dword |= 1 << 22; - pci_write_config32(dev, 0x84, dword); - - /* rpr8.12 Program the watchdog counter to 0x20 */ - byte = pci_read_config8(dev, 0x44); - byte |= 1 << 0; - pci_write_config8(dev, 0x44, byte); - - pci_write_config8(dev, 0x46, 0x20); - - sb800_setup_sata_phys(dev); - /* Enable the I/O, MM, BusMaster access for SATA */ - byte = pci_read_config8(dev, 0x4); - byte |= 7 << 0; - pci_write_config8(dev, 0x4, byte); - - /* RPR7.7 SATA drive detection. */ - /* Use BAR5+0x128,BAR0 for Primary Slave */ - /* Use BAR5+0x1A8,BAR0 for Primary Slave */ - /* Use BAR5+0x228,BAR2 for Secondary Master */ - /* Use BAR5+0x2A8,BAR2 for Secondary Slave */ - /* Use BAR5+0x328,PATA_BAR0/2 for Primary/Secondary master emulation */ - /* Use BAR5+0x3A8,PATA_BAR0/2 for Primary/Secondary Slave emulation */ - - /* TODO: port 4,5, which are PATA emulations. What are PATA_BARs? */ - - for (i = 0; i < 4; i++) { - byte = read8(sata_bar5 + 0x128 + 0x80 * i); - printk(BIOS_SPEW, "SATA port %i status = %x\n", i, byte); - byte &= 0xF; - if (byte == 0x1) { - /* If the drive status is 0x1 then we see it but we aren't talking to it. */ - /* Try to do something about it. */ - printk(BIOS_SPEW, "SATA device detected but not talking. Trying lower speed.\n"); - - /* Read in Port-N Serial ATA Control Register */ - byte = read8(sata_bar5 + 0x12C + 0x80 * i); - - /* Set Reset Bit and 1.5g bit */ - byte |= 0x11; - write8((sata_bar5 + 0x12C + 0x80 * i), byte); - - /* Wait 1ms */ - mdelay(1); - - /* Clear Reset Bit */ - byte &= ~0x01; - write8((sata_bar5 + 0x12C + 0x80 * i), byte); - - /* Wait 1ms */ - mdelay(1); - - /* Reread status */ - byte = read8(sata_bar5 + 0x128 + 0x80 * i); - printk(BIOS_SPEW, "SATA port %i status = %x\n", i, byte); - byte &= 0xF; - } - - if (byte == 0x3) { - for (j = 0; j < 10; j++) { - if (!sata_drive_detect(i, ((i / 2) == 0) ? sata_bar0 : sata_bar2)) - break; - } - printk(BIOS_DEBUG, "%s %s device is %sready after %i tries\n", - (i / 2) ? "Secondary" : "Primary", - (i % 2) ? "Slave" : "Master", - (j == 10) ? "not " : "", - (j == 10) ? j : j + 1); - } else { - printk(BIOS_DEBUG, "No %s %s SATA drive on Slot%i\n", - (i / 2) ? "Secondary" : "Primary", - (i % 2) ? "Slave" : "Master", i); - } - } - - /* Below is CIM InitSataLateFar */ - /* Enable interrupts from the HBA */ - byte = read8(sata_bar5 + 0x4); - byte |= 1 << 1; - write8((sata_bar5 + 0x4), byte); - - /* Clear error status */ - write32((sata_bar5 + 0x130), 0xFFFFFFFF); - write32((sata_bar5 + 0x1b0), 0xFFFFFFFF); - write32((sata_bar5 + 0x230), 0xFFFFFFFF); - write32((sata_bar5 + 0x2b0), 0xFFFFFFFF); - write32((sata_bar5 + 0x330), 0xFFFFFFFF); - write32((sata_bar5 + 0x3b0), 0xFFFFFFFF); - - /* Clear SATA status,Firstly we get the AcpiGpe0BlkAddr */ - /* ????? why CIM does not set the AcpiGpe0BlkAddr, but use it??? */ - - /* word = 0x0000; */ - /* word = pm_ioread(0x28); */ - /* byte = pm_ioread(0x29); */ - /* word |= byte<<8; */ - /* printk(BIOS_DEBUG, "AcpiGpe0Blk addr = %x\n", word); */ - /* write32(word, 0x80000000); */ -} - -static struct pci_operations lops_pci = { - /* .set_subsystem = pci_dev_set_subsystem, */ -}; - -static struct device_operations sata_ops = { - .read_resources = pci_dev_read_resources, - .set_resources = pci_dev_set_resources, - .enable_resources = pci_dev_enable_resources, - .init = sata_init, - .scan_bus = 0, - .ops_pci = &lops_pci, -}; - -static const struct pci_driver sata0_driver __pci_driver = { - .ops = &sata_ops, - .vendor = PCI_VENDOR_ID_ATI, - .device = PCI_DEVICE_ID_ATI_SB800_SATA, -}; diff --git a/src/southbridge/amd/sb800/sb800.c b/src/southbridge/amd/sb800/sb800.c deleted file mode 100644 index c7efaec732..0000000000 --- a/src/southbridge/amd/sb800/sb800.c +++ /dev/null @@ -1,376 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2010 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include - -#include - -#include -#include -#include -#include -#include "sb800.h" -#include "smbus.h" -#include "chip.h" - -static struct device *find_sm_dev(struct device *dev, u32 devfn) -{ - struct device *sm_dev; - - sm_dev = pcidev_path_behind(dev->bus, devfn); - if (!sm_dev) - return sm_dev; - - if ((sm_dev->vendor != PCI_VENDOR_ID_ATI) || - ((sm_dev->device != PCI_DEVICE_ID_ATI_SB800_SM))) { - u32 id; - id = pci_read_config32(sm_dev, PCI_VENDOR_ID); - if ((id != - (PCI_VENDOR_ID_ATI | (PCI_DEVICE_ID_ATI_SB800_SM << 16)))) - { - sm_dev = 0; - } - } - - return sm_dev; -} - -void set_sm_enable_bits(struct device *sm_dev, u32 reg_pos, u32 mask, u32 val) -{ - u32 reg_old, reg; - reg = reg_old = pci_read_config32(sm_dev, reg_pos); - reg &= ~mask; - reg |= val; - if (reg != reg_old) { - pci_write_config32(sm_dev, reg_pos, reg); - } -} - -static void pmio_write_index(u16 port_base, u8 reg, u8 value) -{ - outb(reg, port_base); - outb(value, port_base + 1); -} - -static u8 pmio_read_index(u16 port_base, u8 reg) -{ - outb(reg, port_base); - return inb(port_base + 1); -} - -void pm_iowrite(u8 reg, u8 value) -{ - pmio_write_index(PM_INDEX, reg, value); -} - -u8 pm_ioread(u8 reg) -{ - return pmio_read_index(PM_INDEX, reg); -} - -void pm2_iowrite(u8 reg, u8 value) -{ - pmio_write_index(PM2_INDEX, reg, value); -} - -u8 pm2_ioread(u8 reg) -{ - return pmio_read_index(PM2_INDEX, reg); -} - -static void set_pmio_enable_bits(u32 reg_pos, u32 mask, u32 val) -{ - u8 reg_old, reg; - reg = reg_old = pm_ioread(reg_pos); - reg &= ~mask; - reg |= val; - if (reg != reg_old) { - pm_iowrite(reg_pos, reg); - } -} - -u16 tx_convert_table[] = { - [0x0] = 0xFFFF, - [0x1] = 0xFFFE, - [0x2] = 0xFFFC, - [0x3] = 0xFFF8, - [0x4] = 0xFFF0, - [0x5] = 0xFFE0, - [0x6] = 0xFFC0, - [0x7] = 0xFF80, - [0x8] = 0xFF00, - [0x9] = 0xFE00, - [0xA] = 0xFC00, - [0xB] = 0xF800, - [0xC] = 0xF000, - [0xD] = 0xE000, - [0xE] = 0xC000, - [0xF] = 0x8000 -}; - -u16 rx_convert_table[] = { - [0x0] = 0x0001, - [0x1] = 0x0003, - [0x2] = 0x0007, - [0x3] = 0x000F, - [0x4] = 0x001F, - [0x5] = 0x003F, - [0x6] = 0x007F, - [0x7] = 0x00FF, - [0x8] = 0x01FF, - [0x9] = 0x03FF, - [0xA] = 0x07FF, - [0xB] = 0x0FFF, - [0xC] = 0x1FFF, - [0xD] = 0x3FFF, - [0xE] = 0x7FFF, - [0xF] = 0xFFFF -}; - -/* PCIe General Purpose Ports */ -/* v:1814, d:3090. cp421A */ -static void set_sb800_gpp(struct device *dev) -{ - struct southbridge_amd_sb800_config *conf; - u32 imp_rb, lc_status; - u8 port; - - conf = dev->chip_info; - port = dev->path.pci.devfn & 3; - - /* 5.1 GPP Lane Configuration */ - /* To support one of 4 legal configurations: - * 0000: PortA lanes[3:0] - * 0001: N/A - * 0010: PortA lanes[1:0], PortB lanes[3:2] - * 0011: PortA lanes[1:0], PortB lane2, PortC lane3 - * 0100: PortA lane0, PortB lane1, PortC lane2, PortD lane3. - * Other combinations are not supported. - */ - /* CIMx: Set abcfg:0x90[20] = 1 to enable GPP bridge multi-function */ - abcfg_reg(0x90, 1 << 20, 1 << 20); - - printk(BIOS_DEBUG, "set_sb800_gpp() 1\n"); - //abcfg_reg(0xC0, 0xF << 0, 0x4 << 0); /* bimini:4; tarpon:3 */ - abcfg_reg(0xC0, 0xF << 0, (conf->gpp_configuration & 0xF) << 0); /* bimini:4; tarpon:3 */ - - printk(BIOS_DEBUG, "set_sb800_gpp() 2,\n"); - /* 5.2 Enabling GPP Port A/B/C/D */ - //abcfg_reg(0xC0, 0xF << 4, 0x1 << 4); - abcfg_reg(0xC0, 0xF << 4, dev->enabled ? 0x1 << (4 + port) : 0); - - printk(BIOS_DEBUG, "set_sb800_gpp() 3\n"); - /* 5.3 Releasing GPP Reset */ - abcfg_reg(0xC0, 0x1 << 8, 0x0 << 8); - - /* release training */ - abcfg_reg(0xC0, 0xF << 12, 0x0 << 12); - /* 5.4 Power Saving Feature for GPP Lanes. Skip */ - /* 5.5 PCIe Ports De-emphasis Settings. Skip */ - abcfg_reg(0x340, 1 << 21, 0 << 21); - abcfg_reg(0x344, 1 << 21, 0 << 21); - abcfg_reg(0x348, 1 << 21, 0 << 21); - abcfg_reg(0x34C, 1 << 21, 0 << 21); - /* 5.6 PCIe PHY Calibration Impedance Value Setting */ - /* AXINDC_Reg 0x60: TX_IMP_RB */ - outl(0x30, 0xCD8); - outl(0x60, 0xCDC); - outl(0x34, 0xCD8); - imp_rb = inl(0xCDC); - - printk(BIOS_DEBUG, "imp_rb 1=%x\n", imp_rb); - /* tx */ - abcfg_reg(0xA4, 0x1FFF, (rx_convert_table[(imp_rb>>8)&0xF]) & 0x1FFF); - abcfg_reg(0xA4, 0x1FFF<<19, ((tx_convert_table[(imp_rb>>4)&0xF] >> 3) & 0x1FFF) << 19); - - /* 5.4. */ - abcfg_reg(0xA0, 3 << 12, 3 << 12); - - axindxp_reg(0xa0, 0xf<<4, 3<<4); - rcindxp_reg(0xA0, 0, 0xF << 4, 1 << 0); - rcindxp_reg(0xA0, 1, 0xF << 4, 1 << 0); - rcindxp_reg(0xA0, 2, 0xF << 4, 1 << 0); - rcindxp_reg(0xA0, 3, 0xF << 4, 1 << 0); - - /* 5.8 Disabling Serial Number Capability */ - abcfg_reg(0x330, 1 << 26, 0 << 26); - - abcfg_reg(0x50, 0xFFFFFFFF, 0x04000004); - abcfg_reg(0x54, 0xFFFFFFFF, 0x00040000); - abcfg_reg(0x80, 0xFFFFFFFF, 0x03060001); - abcfg_reg(0x90, 0xFFFFFFFF, 0x00300000); - abcfg_reg(0x98, 0xFFFFFFFF, 0x03034700); - - pci_write_config32(dev, 0x80, 0x00000006); - /* Set PCIEIND_P:PCIE_RX_CNTL[RX_RCB_CPL_TIMEOUT_MODE] (0x70:[19]) = 1 */ - rcindxp_reg(0x70, 0, 1 << 19, 1 << 19); - //outl(3<<29|0<<24|0x70, 0xCD8); - /* Set PCIEIND_P:PCIE_TX_CNTL[TX_FLUSH_TLP_DIS] (0x20:[19]) = 0 */ - rcindxp_reg(0x20, 0, 1 << 19, 0 << 19); - printk(BIOS_DEBUG, "imp_rb 5=%x\n", imp_rb); - outl(3<<29|0<<24|0xA5, 0xCD8); - lc_status = inl(0xCDC); - printk(BIOS_DEBUG, "lc_status=%x\n", lc_status); -} - -void sb800_enable(struct device *dev) -{ - struct device *sm_dev = NULL; - struct device *bus_dev = NULL; - int index; - u32 deviceid; - u32 vendorid; - - /* struct southbridge_ati_sb800_config *conf; */ - /* conf = dev->chip_info; */ - int i; - - u32 devfn, dword; - - printk(BIOS_DEBUG, "sb800_enable()\n"); - - /* - * 0:11.0 SATA bit 8 of pmio 0xDA : 1 - enable - * 0:12.0 OHCI-USB1 bit 0 of pmio 0xEF - * 0:12.2 EHCI-USB1 bit 1 of pmio 0xEF - * 0:13.0 OHCI-USB2 bit 2 of pmio 0xEF - * 0:13.2 EHCI-USB2 bit 3 of pmio 0xEF - * 0:16.1 OHCI-USB3 bit 4 of pmio 0xEF - * 0:16.2 EHCI-USB3 bit 5 of pmio 0xEF - * 0:14.5 OHCI-USB4 bit 6 of pmio 0xEF - * 0:14.0 SMBUS 0 - * 0:14.1 IDE 1 - * 0:14.2 HDA bit 0 of pm_io 0xEB : 1 - enable - * 0:14.3 LPC bit 0 of pm_io 0xEC : 1 - enable - * 0:14.4 PCI bit 0 of pm_io 0xEA : 0 - enable - * 0:14.6 GEC bit 0 of pm_io 0xF6 : 0 - enable - */ - if (dev->device == 0x0000) { - vendorid = pci_read_config32(dev, PCI_VENDOR_ID); - deviceid = (vendorid >> 16) & 0xffff; - vendorid &= 0xffff; - } else { - vendorid = dev->vendor; - deviceid = dev->device; - } - bus_dev = dev->bus->dev; - if ((bus_dev->vendor == PCI_VENDOR_ID_ATI) && - (bus_dev->device == PCI_DEVICE_ID_ATI_SB800_PCI)) { - devfn = (bus_dev->path.pci.devfn) & ~7; - sm_dev = find_sm_dev(bus_dev, devfn); - if (!sm_dev) - return; - - /* something under 00:01.0 */ - switch (dev->path.pci.devfn) { - case 5 << 3: - ; - } - - return; - } - printk(BIOS_DEBUG, "sb800_enable() 1\n"); - - i = (dev->path.pci.devfn) & ~7; - i += (3 << 3); - for (devfn = (0x14 << 3); devfn <= i; devfn += (1 << 3)) { - sm_dev = find_sm_dev(dev, devfn); - if (sm_dev) - break; - } - if (!sm_dev) - return; - printk(BIOS_DEBUG, "sb800_enable() 2\n"); - - switch (dev->path.pci.devfn - (devfn - (0x14 << 3))) { - case PCI_DEVFN(0x11, 0): - index = 0; - set_pmio_enable_bits(0xDA, 1 << index, - (dev->enabled ? 1 : 0) << index); - /* Set the device ID of SATA as 0x4390 to reduce the confusing. */ - dword = pci_read_config32(dev, 0x40); - dword |= 1 << 0; - pci_write_config32(dev, 0x40, dword); - pci_write_config16(dev, 0x2, 0x4390); - dword &= ~1; - pci_write_config32(dev, 0x40, dword);//for (;;); - break; - case PCI_DEVFN(0x12, 0): - case PCI_DEVFN(0x12, 2): - index = (dev->path.pci.devfn & 0x3) / 2; - set_pmio_enable_bits(0xEF, 1 << index, - (dev->enabled ? 1 : 0) << index); - break; - case PCI_DEVFN(0x13, 0): - case PCI_DEVFN(0x13, 2): - index = (dev->path.pci.devfn & 0x3) / 2 + 2; - set_pmio_enable_bits(0xEF, 1 << index, - (dev->enabled ? 1 : 0) << index); - break; - case PCI_DEVFN(0x14, 0): - break; - case PCI_DEVFN(0x14, 1): - index = 3; - set_pmio_enable_bits(0xDA, 1 << index, - (dev->enabled ? 0 : 1) << index); - break; - case PCI_DEVFN(0x14, 2): - index = 0; - set_pmio_enable_bits(0xEB, 1 << index, - (dev->enabled ? 1 : 0) << index); - break; - case PCI_DEVFN(0x14, 3): - index = 0; - set_pmio_enable_bits(0xEC, 1 << index, - (dev->enabled ? 1 : 0) << index); - break; - case PCI_DEVFN(0x14, 4): - index = 0; - set_pmio_enable_bits(0xEA, 1 << index, - (dev->enabled ? 0 : 1) << index); - break; - case PCI_DEVFN(0x14, 5): - index = 6; - set_pmio_enable_bits(0xEF, 1 << index, - (dev->enabled ? 1 : 0) << index); - break; - case PCI_DEVFN(0x14, 6): - index = 0; - set_pmio_enable_bits(0xF6, 1 << index, - (dev->enabled ? 0 : 1) << index); - break; - case PCI_DEVFN(0x15, 0): - set_sb800_gpp(dev); - break; - case PCI_DEVFN(0x15, 1): - case PCI_DEVFN(0x15, 2): - case PCI_DEVFN(0x15, 3): - break; - case PCI_DEVFN(0x16, 0): - case PCI_DEVFN(0x16, 2): - index = (dev->path.pci.devfn & 0x3) / 2 + 4; - set_pmio_enable_bits(0xEF, 1 << index, - (dev->enabled ? 1 : 0) << index); - break; - default: - printk(BIOS_DEBUG, "unknown dev: %s deviceid=%4x\n", dev_path(dev), - deviceid); - } -} - -struct chip_operations southbridge_amd_sb800_ops = { - CHIP_NAME("ATI SB800") - .enable_dev = sb800_enable, -}; diff --git a/src/southbridge/amd/sb800/sb800.h b/src/southbridge/amd/sb800/sb800.h deleted file mode 100644 index 07c78ec429..0000000000 --- a/src/southbridge/amd/sb800/sb800.h +++ /dev/null @@ -1,60 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2010 Advanced Micro Devices, Inc. - * Copyright (C) 2015 Timothy Pearson , Raptor Engineering - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef SB800_H -#define SB800_H - -#include -#include - -/* Power management index/data registers */ -#define BIOSRAM_INDEX 0xcd4 -#define BIOSRAM_DATA 0xcd5 -#define PM_INDEX 0xcd6 -#define PM_DATA 0xcd7 -#define PM2_INDEX 0xcd0 -#define PM2_DATA 0xcd1 - -#define SB800_ACPI_IO_BASE 0x800 - -#define ACPI_PM_EVT_BLK (SB800_ACPI_IO_BASE + 0x00) /* 4 bytes */ -#define ACPI_PM1_CNT_BLK (SB800_ACPI_IO_BASE + 0x04) /* 2 bytes */ -#define ACPI_PMA_CNT_BLK (SB800_ACPI_IO_BASE + 0x17) /* 1 byte */ -#define ACPI_PM_TMR_BLK (SB800_ACPI_IO_BASE + 0x20) /* 4 bytes */ -#define ACPI_GPE0_BLK (SB800_ACPI_IO_BASE + 0x18) /* 8 bytes */ -#define ACPI_CPU_CONTROL (SB800_ACPI_IO_BASE + 0x08) /* 6 bytes */ -#define ACPI_CPU_P_LVL2 (ACPI_CPU_CONTROL + 0x4) /* 1 byte */ - -void pm_iowrite(u8 reg, u8 value); -u8 pm_ioread(u8 reg); -void pm2_iowrite(u8 reg, u8 value); -u8 pm2_ioread(u8 reg); - -void set_sm_enable_bits(struct device *sm_dev, u32 reg_pos, u32 mask, u32 val); - -#define REV_SB800_A11 0x11 -#define REV_SB800_A12 0x12 - -void sb800_lpc_port80(void); -void sb800_pci_port80(void); -void sb800_clk_output_48Mhz(void); - -int s3_save_nvram_early(u32 dword, int size, int nvram_pos); -int s3_load_nvram_early(int size, u32 *old_dword, int nvram_pos); - -void sb800_enable(struct device *dev); - -#endif /* SB800_H */ diff --git a/src/southbridge/amd/sb800/sm.c b/src/southbridge/amd/sb800/sm.c deleted file mode 100644 index e1cf05ce09..0000000000 --- a/src/southbridge/amd/sb800/sm.c +++ /dev/null @@ -1,346 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2010 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include "sb800.h" -#include "smbus.c" - -#define NMI_OFF 0 - -#define MAINBOARD_POWER_OFF 0 -#define MAINBOARD_POWER_ON 1 - -#define BIT0 (1 << 0) -#define BIT1 (1 << 1) -#define BIT2 (1 << 2) -#define BIT3 (1 << 3) -#define BIT4 (1 << 4) -#define BIT5 (1 << 5) -#define BIT6 (1 << 6) -#define BIT7 (1 << 7) - -#define BIT8 (1 << 8) -#define BIT9 (1 << 9) -#define BIT10 (1 << 10) -#define BIT11 (1 << 11) -#define BIT12 (1 << 12) -#define BIT13 (1 << 13) -#define BIT14 (1 << 14) -#define BIT15 (1 << 15) - -#define BIT16 (1 << 16) -#define BIT17 (1 << 17) -#define BIT18 (1 << 18) -#define BIT19 (1 << 19) -#define BIT20 (1 << 20) -#define BIT21 (1 << 21) -#define BIT22 (1 << 22) -#define BIT23 (1 << 23) -#define BIT24 (1 << 24) -#define BIT25 (1 << 25) -#define BIT26 (1 << 26) -#define BIT27 (1 << 27) -#define BIT28 (1 << 28) -#define BIT29 (1 << 29) -#define BIT30 (1 << 30) -#define BIT31 (1 << 31) - -/* -* SB800 enables all USB controllers by default in SMBUS Control. -* SB800 enables SATA by default in SMBUS Control. -*/ - -static void sm_init(struct device *dev) -{ - u8 byte; - - printk(BIOS_INFO, "sm_init().\n"); - - /* Don't rename APIC ID */ - /* TODO: We should call setup_ioapic() here. But kernel hangs if CPU is K8. - * We need to check out why and change back. */ - clear_ioapic(VIO_APIC_VADDR); - //setup_ioapic(IO_APIC_ADDR, 0); - - /* enable serial irq */ - byte = pm_ioread(0x54); - byte |= 1 << 7; /* enable serial irq function */ - byte &= ~(0xF << 2); - byte |= 4 << 2; /* set NumSerIrqBits=4 */ - pm_iowrite(0x54, byte); - - pm_iowrite(0x00, 0x0E); - pm_iowrite(0x0B, 0x02); - /* 2.11 IO Trap Settings */ - abcfg_reg(0x10090, 1 << 16, 1 << 16); - - /* 4.1 ab index */ - //pci_write_config32(dev, 0xF0, AB_INDX); - pm_iowrite(0xE0, AB_INDX & 0xFF); - pm_iowrite(0xE1, (AB_INDX >> 8) & 0xFF); - pm_iowrite(0xE2, (AB_INDX >> 16) & 0xFF); - pm_iowrite(0xE3, (AB_INDX >> 24) & 0xFF); - /* Initialize the real time clock */ - cmos_init(0); - - byte = pm_ioread(0x8); - byte |= 1 << 2 | 1 << 4; - pm_iowrite(0x08, byte); - byte = pm_ioread(0x9); - byte |= 1 << 0; - pm_iowrite(0x09, byte); - - abcfg_reg(0x10060, (BIT31), BIT31); - abcfg_reg(0x1009C, (BIT4 + BIT5), BIT4 + BIT5); - abcfg_reg(0x9C, (BIT2 + BIT3 + BIT4 + BIT5 + BIT6 + BIT7), BIT2 + BIT3 + BIT4 + BIT5 + BIT6 + BIT7); - abcfg_reg(0x90, (BIT21 + BIT22 + BIT23), BIT21 + BIT22 + BIT23); - abcfg_reg(0xF0, (BIT6 + BIT5), BIT6 + BIT5); - abcfg_reg(0x10090, (BIT9 + BIT10 + BIT11 + BIT12), BIT9 + BIT10 + BIT11 + BIT12); - abcfg_reg(0x58, (BIT10), BIT10); - abcfg_reg(0xF0, (BIT3 + BIT4), BIT3 + BIT4); - abcfg_reg(0x54, (BIT1), BIT1); - // - axindxc_reg(0x02, BIT9, BIT9); - axindxc_reg(0x10, BIT9, BIT9); - - /* 4.2 Enabling Upstream DMA Access */ - axcfg_reg(0x04, 1 << 2, 1 << 2); - /* 4.3 Enabling PCIB Prefetch Settings */ - abcfg_reg(0x10060, 1 << 20, 1 << 20); - abcfg_reg(0x10064, 1 << 20, 1 << 20); - - /* 4.4 Enabling OHCI Prefetch for Performance Enhancement, A12 */ - abcfg_reg(0x80, 1 << 0, 1<< 0); - - /* 4.5 B-Link Client's Credit Variable Settings for the Downstream Arbitration Equation */ - /* 4.6 Enabling Additional Address Bits Checking in Downstream */ - abcfg_reg(0x9c, 1 << 0, 1 << 0); - //abcfg_reg(0x9c, 3 << 0, 3 << 0); //A11 - - /* 4.7 Set B-Link Prefetch Mode */ - abcfg_reg(0x80, 3 << 17, 3 << 17); - - // RPR Enabled SMI ordering enhancement. ABCFG 0x90[21] - // RPR USB Delay A-Link Express L1 State. ABCFG 0x90[17] - abcfg_reg(0x90, 1 << 17 | 1 << 21, 1 << 17 | 1 << 21); - /* 4.8 Enabling Detection of Upstream Interrupts */ - abcfg_reg(0x94, 1 << 20 | 0x7FFFF, 1 << 20 | 0x00FEE); - - /* 4.9: Enabling Downstream Posted Transactions to Pass Non-Posted - * Transactions for the K8 Platform (for All Revisions) */ - abcfg_reg(0x10090, 1 << 8, 1 << 8); - - /* 4.10:Programming Cycle Delay for AB and BIF Clock Gating */ - /* 4.11:Enabling AB Int_Arbiter Enhancement (for All Revisions) */ - abcfg_reg(0x10054, 0xFFFF0000, 0x01040000); - abcfg_reg(0x54, 0xFF << 16, 4 << 16); - abcfg_reg(0x54, 1 << 24, 0 << 24); - abcfg_reg(0x54, 1 << 26, 1 << 26); - abcfg_reg(0x98, 0xFFFFFF00, 0x00004700); - - /* 4.12: Enabling AB and BIF Clock Gating */ - abcfg_reg(0x10054, 0x0000FFFF, 0x07FF); - - /* 4.13:Enabling Requester ID for upstream traffic. */ - abcfg_reg(0x98, 3 << 16, 3 << 16); - - abcfg_reg(0x50, 1 << 2, 0 << 2); - - /* 5.2 Enabling GPP Port A/B/C/D */ - //abcfg_reg(0xC0, 0xF << 4, 0xF << 4); - - /* Enable SCI as irq9. */ - outb(0x10, 0xC00); - outb(0x9, 0xC01); - /* Enabled IRQ input */ - outb(0x9, 0xC00); - outb(0xF7, 0xC01); - - abcfg_reg(0x90, 0xFFFFFFFF, 0x00F80040); - abcfg_reg(0xA0, 0xFFFFFFFF, 0x00000000); - abcfg_reg(0xA4, 0xFFFFFFFF, 0x00000000); - abcfg_reg(0xC0, 0xFFFFFFFF, 0x0000F014); - abcfg_reg(0x98, 0xFFFFFFFF, 0X01034700); -} - -static int lsmbus_recv_byte(struct device *dev) -{ - u32 device; - struct resource *res; - struct bus *pbus; - - device = dev->path.i2c.device; - pbus = get_pbus_smbus(dev); - - res = find_resource(pbus->dev, 0x90); - - return do_smbus_recv_byte(res->base, device); -} - -static int lsmbus_send_byte(struct device *dev, u8 val) -{ - u32 device; - struct resource *res; - struct bus *pbus; - - device = dev->path.i2c.device; - pbus = get_pbus_smbus(dev); - - res = find_resource(pbus->dev, 0x90); - - return do_smbus_send_byte(res->base, device, val); -} - -static int lsmbus_read_byte(struct device *dev, u8 address) -{ - u32 device; - struct resource *res; - struct bus *pbus; - - device = dev->path.i2c.device; - pbus = get_pbus_smbus(dev); - - res = find_resource(pbus->dev, 0x90); - - return do_smbus_read_byte(res->base, device, address); -} - -static int lsmbus_write_byte(struct device *dev, u8 address, u8 val) -{ - u32 device; - struct resource *res; - struct bus *pbus; - - device = dev->path.i2c.device; - pbus = get_pbus_smbus(dev); - - res = find_resource(pbus->dev, 0x90); - - return do_smbus_write_byte(res->base, device, address, val); -} -static struct smbus_bus_operations lops_smbus_bus = { - .recv_byte = lsmbus_recv_byte, - .send_byte = lsmbus_send_byte, - .read_byte = lsmbus_read_byte, - .write_byte = lsmbus_write_byte, -}; - -static void sb800_sm_read_resources(struct device *dev) -{ - struct resource *res; - u8 byte; - - /* rpr2.14: Hides SM bus controller Bar1 where stores HPET MMIO base address */ - byte = pm_ioread(0x55); - byte |= 1 << 7; - pm_iowrite(0x55, byte); - - /* Get the normal pci resources of this device */ - /* pci_dev_read_resources(dev); */ - - byte = pm_ioread(0x55); - byte &= ~(1 << 7); - pm_iowrite(0x55, byte); - - /* apic */ - res = new_resource(dev, 0x74); - res->base = IO_APIC_ADDR; - res->size = 256 * 0x10; - res->limit = 0xFEFFFFFUL; /* res->base + res->size -1; */ - res->align = 8; - res->gran = 8; - res->flags = IORESOURCE_MEM | IORESOURCE_FIXED; - - #if 0 /* Linux ACPI crashes when it is 1. For late debugging. */ - res = new_resource(dev, 0x14); /* TODO: hpet */ - res->base = 0xfed00000; /* reset hpet to widely accepted address */ - res->size = 0x400; - res->limit = 0xFFFFFFFFUL; /* res->base + res->size -1; */ - res->align = 8; - res->gran = 8; - res->flags = IORESOURCE_MEM | IORESOURCE_FIXED; - #endif - /* dev->command |= PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER; */ - - /* smbus */ - //res = new_resource(dev, 0x90); - //res->base = 0xB00; - //res->size = 0x10; - //res->limit = 0xFFFFUL; /* res->base + res->size -1; */ - //res->align = 8; - //res->gran = 8; - //res->flags = IORESOURCE_IO | IORESOURCE_FIXED; - - - compact_resources(dev); -} - -static void sb800_sm_set_resources(struct device *dev) -{ - struct resource *res; - u8 byte; - - pci_dev_set_resources(dev); - - - /* rpr2.14: Make HPET MMIO decoding controlled by the memory enable bit in command register of LPC ISA bridge */ - byte = pm_ioread(0x52); - byte |= 1 << 6; - pm_iowrite(0x52, byte); - - res = find_resource(dev, 0x74); - - printk(BIOS_INFO, "sb800_sm_set_resources, res->base=0x%llx\n", res->base); - - //pci_write_config32(dev, 0x74, res->base | 1 << 3); - pm_iowrite(0x34, res->base | 0x7); - pm_iowrite(0x35, (res->base >> 8) & 0xFF); - pm_iowrite(0x36, (res->base >> 16) & 0xFF); - pm_iowrite(0x37, (res->base >> 24) & 0xFF); -#if 0 /* TODO:hpet */ - res = find_resource(dev, 0x14); - pci_write_config32(dev, 0x14, res->base); -#endif - //res = find_resource(dev, 0x90); - //pci_write_config32(dev, 0x90, res->base | 1); -} - -static struct pci_operations lops_pci = { - .set_subsystem = pci_dev_set_subsystem, -}; -static struct device_operations smbus_ops = { - .read_resources = sb800_sm_read_resources, - .set_resources = sb800_sm_set_resources, - .enable_resources = pci_dev_enable_resources, - .init = sm_init, - .scan_bus = scan_smbus, - .ops_pci = &lops_pci, - .ops_smbus_bus = &lops_smbus_bus, -}; -static const struct pci_driver smbus_driver __pci_driver = { - .ops = &smbus_ops, - .vendor = PCI_VENDOR_ID_ATI, - .device = PCI_DEVICE_ID_ATI_SB800_SM, -}; diff --git a/src/southbridge/amd/sb800/smbus.c b/src/southbridge/amd/sb800/smbus.c deleted file mode 100644 index fef6ab80c1..0000000000 --- a/src/southbridge/amd/sb800/smbus.c +++ /dev/null @@ -1,245 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2010 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef _SB800_SMBUS_C_ -#define _SB800_SMBUS_C_ - -#include -#include "smbus.h" - -static int smbus_wait_until_ready(u32 smbus_io_base) -{ - u32 loops; - loops = SMBUS_TIMEOUT; - do { - u8 val; - val = inb(smbus_io_base + SMBHSTSTAT); - val &= 0x1f; - if (val == 0) { /* ready now */ - return 0; - } - outb(val, smbus_io_base + SMBHSTSTAT); - } while (--loops); - return -2; /* time out */ -} - -static int smbus_wait_until_done(u32 smbus_io_base) -{ - u32 loops; - loops = SMBUS_TIMEOUT; - do { - u8 val; - - val = inb(smbus_io_base + SMBHSTSTAT); - val &= 0x1f; /* mask off reserved bits */ - if (val & 0x1c) { - return -5; /* error */ - } - if (val == 0x02) { - outb(val, smbus_io_base + SMBHSTSTAT); /* clear status */ - return 0; - } - } while (--loops); - return -3; /* timeout */ -} - -int do_smbus_recv_byte(u32 smbus_io_base, u32 device) -{ - u8 byte; - - if (smbus_wait_until_ready(smbus_io_base) < 0) { - return -2; /* not ready */ - } - - /* set the device I'm talking to */ - outb(((device & 0x7f) << 1) | 1, smbus_io_base + SMBHSTADDR); - - byte = inb(smbus_io_base + SMBHSTCTRL); - byte &= 0xe3; /* Clear [4:2] */ - byte |= (1 << 2) | (1 << 6); /* Byte data read/write command, start the command */ - outb(byte, smbus_io_base + SMBHSTCTRL); - - /* poll for transaction completion */ - if (smbus_wait_until_done(smbus_io_base) < 0) { - return -3; /* timeout or error */ - } - - /* read results of transaction */ - byte = inb(smbus_io_base + SMBHSTCMD); - - return byte; -} - -int do_smbus_send_byte(u32 smbus_io_base, u32 device, u8 val) -{ - u8 byte; - - if (smbus_wait_until_ready(smbus_io_base) < 0) { - return -2; /* not ready */ - } - - /* set the command... */ - outb(val, smbus_io_base + SMBHSTCMD); - - /* set the device I'm talking to */ - outb(((device & 0x7f) << 1) | 0, smbus_io_base + SMBHSTADDR); - - byte = inb(smbus_io_base + SMBHSTCTRL); - byte &= 0xe3; /* Clear [4:2] */ - byte |= (1 << 2) | (1 << 6); /* Byte data read/write command, start the command */ - outb(byte, smbus_io_base + SMBHSTCTRL); - - /* poll for transaction completion */ - if (smbus_wait_until_done(smbus_io_base) < 0) { - return -3; /* timeout or error */ - } - - return 0; -} - -int do_smbus_read_byte(u32 smbus_io_base, u32 device, - u32 address) -{ - u8 byte; - - if (smbus_wait_until_ready(smbus_io_base) < 0) { - return -2; /* not ready */ - } - - /* set the command/address... */ - outb(address & 0xff, smbus_io_base + SMBHSTCMD); - - /* set the device I'm talking to */ - outb(((device & 0x7f) << 1) | 1, smbus_io_base + SMBHSTADDR); - - byte = inb(smbus_io_base + SMBHSTCTRL); - byte &= 0xe3; /* Clear [4:2] */ - byte |= (1 << 3) | (1 << 6); /* Byte data read/write command, start the command */ - outb(byte, smbus_io_base + SMBHSTCTRL); - - /* poll for transaction completion */ - if (smbus_wait_until_done(smbus_io_base) < 0) { - return -3; /* timeout or error */ - } - - /* read results of transaction */ - byte = inb(smbus_io_base + SMBHSTDAT0); - - return byte; -} - -int do_smbus_write_byte(u32 smbus_io_base, u32 device, - u32 address, u8 val) -{ - u8 byte; - - if (smbus_wait_until_ready(smbus_io_base) < 0) { - return -2; /* not ready */ - } - - /* set the command/address... */ - outb(address & 0xff, smbus_io_base + SMBHSTCMD); - - /* set the device I'm talking to */ - outb(((device & 0x7f) << 1) | 0, smbus_io_base + SMBHSTADDR); - - /* output value */ - outb(val, smbus_io_base + SMBHSTDAT0); - - byte = inb(smbus_io_base + SMBHSTCTRL); - byte &= 0xe3; /* Clear [4:2] */ - byte |= (1 << 3) | (1 << 6); /* Byte data read/write command, start the command */ - outb(byte, smbus_io_base + SMBHSTCTRL); - - /* poll for transaction completion */ - if (smbus_wait_until_done(smbus_io_base) < 0) { - return -3; /* timeout or error */ - } - - return 0; -} - -void alink_ab_indx(u32 reg_space, u32 reg_addr, - u32 mask, u32 val) -{ - u32 tmp; - - outl((reg_space & 0x7) << 29 | reg_addr, AB_INDX); - tmp = inl(AB_DATA); - /* rpr 4.2 - * For certain revisions of the chip, the ABCFG registers, - * with an address of 0x100NN (where 'N' is any hexadecimal - * number), require an extra programming step.*/ - outl(0, AB_INDX); - - tmp &= ~mask; - tmp |= val; - - /* printk(BIOS_DEBUG, "about write %x, index=%x", tmp, (reg_space&0x3)<<29 | reg_addr); */ - outl((reg_space & 0x7) << 29 | reg_addr, AB_INDX); /* probably we don't have to do it again. */ - outl(tmp, AB_DATA); - outl(0, AB_INDX); -} - -void alink_rc_indx(u32 reg_space, u32 reg_addr, u32 port, - u32 mask, u32 val) -{ - u32 tmp; - - outl((reg_space & 0x7) << 29 | (port & 3) << 24 | reg_addr, AB_INDX); - tmp = inl(AB_DATA); - /* rpr 4.2 - * For certain revisions of the chip, the ABCFG registers, - * with an address of 0x100NN (where 'N' is any hexadecimal - * number), require an extra programming step.*/ - outl(0, AB_INDX); - - tmp &= ~mask; - tmp |= val; - - //printk(BIOS_DEBUG, "about write %x, index=%x", tmp, (reg_space&0x3)<<29 | (port&3) << 24 | reg_addr); - outl((reg_space & 0x7) << 29 | (port & 3) << 24 | reg_addr, AB_INDX); /* probably we don't have to do it again. */ - outl(tmp, AB_DATA); - outl(0, AB_INDX); -} - -/* space = 0: AX_INDXC, AX_DATAC - * space = 1: AX_INDXP, AX_DATAP - */ -void alink_ax_indx(u32 space /*c or p? */, u32 axindc, - u32 mask, u32 val) -{ - u32 tmp; - - /* read axindc to tmp */ - outl(space << 29 | space << 3 | 0x30, AB_INDX); - outl(axindc, AB_DATA); - outl(0, AB_INDX); - outl(space << 29 | space << 3 | 0x34, AB_INDX); - tmp = inl(AB_DATA); - outl(0, AB_INDX); - - tmp &= ~mask; - tmp |= val; - - /* write tmp */ - outl(space << 29 | space << 3 | 0x30, AB_INDX); - outl(axindc, AB_DATA); - outl(0, AB_INDX); - outl(space << 29 | space << 3 | 0x34, AB_INDX); - outl(tmp, AB_DATA); - outl(0, AB_INDX); -} -#endif diff --git a/src/southbridge/amd/sb800/smbus.h b/src/southbridge/amd/sb800/smbus.h deleted file mode 100644 index 0a7ca0e1ea..0000000000 --- a/src/southbridge/amd/sb800/smbus.h +++ /dev/null @@ -1,70 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2010 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef SB800_SMBUS_H -#define SB800_SMBUS_H - -#define SMBHSTSTAT 0x0 -#define SMBSLVSTAT 0x1 -#define SMBHSTCTRL 0x2 -#define SMBHSTCMD 0x3 -#define SMBHSTADDR 0x4 -#define SMBHSTDAT0 0x5 -#define SMBHSTDAT1 0x6 -#define SMBHSTBLKDAT 0x7 - -#define SMBSLVCTRL 0x8 -#define SMBSLVCMD_SHADOW 0x9 -#define SMBSLVEVT 0xa -#define SMBSLVDAT 0xc - -#define AX_INDXC 0 -#define AX_INDXP 2 -#define AXCFG 4 -#define ABCFG 6 -#define RC_INDXC 1 -#define RC_INDXP 3 - -#define AB_INDX 0xCD8 -#define AB_DATA (AB_INDX+4) - -/* Between 1-10 seconds, We should never timeout normally - * Longer than this is just painful when a timeout condition occurs. - */ -#define SMBUS_TIMEOUT (100*1000*10) - -#define abcfg_reg(reg, mask, val) \ - alink_ab_indx((ABCFG), (reg), (mask), (val)) -#define axcfg_reg(reg, mask, val) \ - alink_ab_indx((AXCFG), (reg), (mask), (val)) -#define axindxc_reg(reg, mask, val) \ - alink_ax_indx((AX_INDXC), (reg), (mask), (val)) -#define axindxp_reg(reg, mask, val) \ - alink_ax_indx((AX_INDXP), (reg), (mask), (val)) -#define rcindxc_reg(reg, port, mask, val) \ - alink_rc_indx((RC_INDXC), (reg), (port), (mask), (val)) -#define rcindxp_reg(reg, port, mask, val) \ - alink_rc_indx((RC_INDXP), (reg), (port), (mask), (val)) - -int do_smbus_read_byte(u32 smbus_io_base, u32 device, u32 address); -int do_smbus_write_byte(u32 smbus_io_base, u32 device, u32 address, u8 val); -int do_smbus_recv_byte(u32 smbus_io_base, u32 device); -int do_smbus_send_byte(u32 smbus_io_base, u32 device, u8 val); -void alink_rc_indx(u32 reg_space, u32 reg_addr, u32 port, u32 mask, u32 val); -void alink_ab_indx(u32 reg_space, u32 reg_addr, u32 mask, u32 val); -void alink_ax_indx(u32 space /*c or p? */ , u32 axindc, u32 mask, u32 val); - - -#endif diff --git a/src/southbridge/amd/sb800/usb.c b/src/southbridge/amd/sb800/usb.c deleted file mode 100644 index 063750dc46..0000000000 --- a/src/southbridge/amd/sb800/usb.c +++ /dev/null @@ -1,205 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2010 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include -#include -#include -#include -#include -#include "sb800.h" - -static struct pci_operations lops_pci = { - .set_subsystem = pci_dev_set_subsystem, -}; - -static void usb_init(struct device *dev) -{ - u8 byte; - u16 word; - - /* 7.1 Enable OHCI0-4 and EHCI Controllers */ - /* pmio 0xEF; */ - - /* RPR 7.2 USB S4/S5 Wake-up or PHY Power-down Support */ - byte = pm_ioread(0xF0); - byte |= 1 << 0; /* A12, USB Wake from S5 not supported on the platform */ - pm_iowrite(0xF0, byte); - - /* RPR 7.4 Enable the USB controller to get reset by any software that generate a PCIRst# condition */ - byte = pm_ioread(0xF0); - byte |= (1 << 2); - pm_iowrite(0xF0, byte); - - /* RPR 7.9 Disable OHCI MSI Capability. */ - word = pci_read_config16(dev, 0x40); - word |= (0x1 << 8); - pci_write_config16(dev, 0x40, word); -} - -static void usb_init2(struct device *dev) -{ - u32 dword; - void *usb2_bar0; - struct device *sm_dev; - - sm_dev = pcidev_on_root(0x14, 0); - //rev = get_sb800_revision(sm_dev); - - /* dword = pci_read_config32(dev, 0xf8); */ - /* dword |= 40; */ - /* pci_write_config32(dev, 0xf8, dword); */ - - usb2_bar0 = (void *)(pci_read_config32(dev, 0x10) & ~0xFF); - printk(BIOS_INFO, "usb2_bar0=0x%p\n", usb2_bar0); - - /* RPR7.3 Enables the USB PHY auto calibration resister to match 45ohm resistance */ - dword = 0x00020F00; - write32(usb2_bar0 + 0xC0, dword); - - /* RPR7.8 Sets In/OUT FIFO threshold for best performance */ - dword = 0x00400040; - write32(usb2_bar0 + 0xA4, dword); - - /* RPR7.10 Disable EHCI MSI support */ - dword = pci_read_config32(dev, 0x50); - dword |= (1 << 6); - pci_write_config32(dev, 0x50, dword); - - /* RPR7.12 EHCI Async Park Mode */ - dword = pci_read_config32(dev, 0x50); - dword &= ~(0xF << 8); - dword &= ~(0xF << 12); - dword |= 1 << 8; - dword |= 2 << 12; - pci_write_config32(dev, 0x50, dword); - - /* RPR 6.12 EHCI Advance PHY Power Savings */ - /* RPR says it is just for A12. CIMM sets it when it is above A11. */ - /* But it makes the linux crash, so we skip it */ - #if 0 - dword = pci_read_config32(dev, 0x50); - dword |= 1 << 31; - pci_write_config32(dev, 0x50, dword); - #endif - - /* Each step below causes the linux crashes. Leave them here - * for future debugging. */ -#if 0 - u8 byte; - u16 word; - - - /* RPR6.17 Disable the EHCI Dynamic Power Saving feature */ - word = read32(usb2_bar0 + 0xBC); - word &= ~(1 << 12); - write16(usb2_bar0 + 0xBC, word); - - /* RPR6.19 USB Controller DMA Read Delay Tolerant. */ - if (rev >= REV_SB800_A14) { - byte = pci_read_config8(dev, 0x50); - byte |= (1 << 7); - pci_write_config8(dev, 0x50, byte); - } - - /* RPR6.20 Async Park Mode. */ - /* RPR recommends not to set these bits. */ - #if 0 - dword = pci_read_config32(dev, 0x50); - dword |= 1 << 23; - if (rev >= REV_SB800_A14) { - dword &= ~(1 << 2); - } - pci_write_config32(dev, 0x50, dword); - #endif - - /* RPR6.22 Advance Async Enhancement */ - /* RPR6.23 USB Periodic Cache Setting */ - dword = pci_read_config32(dev, 0x50); - if (rev == REV_SB800_A12) { - dword |= 1 << 28; /* 6.22 */ - dword |= 1 << 27; /* 6.23 */ - } else if (rev >= REV_SB800_A14) { - dword |= 1 << 3; - dword &= ~(1 << 28); /* 6.22 */ - dword |= 1 << 8; - dword &= ~(1 << 27); /* 6.23 */ - } - printk(BIOS_DEBUG, "rpr 6.23, final dword=%x\n", dword); -#endif -} - -static struct device_operations usb_ops = { - .read_resources = pci_ehci_read_resources, - .set_resources = pci_dev_set_resources, - .enable_resources = pci_dev_enable_resources, - .init = usb_init, - .scan_bus = 0, - .ops_pci = &lops_pci, -}; - -static const struct pci_driver usb_0_driver __pci_driver = { - .ops = &usb_ops, - .vendor = PCI_VENDOR_ID_ATI, - .device = PCI_DEVICE_ID_ATI_SB800_USB_18_0, -}; -static const struct pci_driver usb_1_driver __pci_driver = { - .ops = &usb_ops, - .vendor = PCI_VENDOR_ID_ATI, - .device = PCI_DEVICE_ID_ATI_SB800_USB_18_2, -}; - -/* the pci id of usb ctrl 0 and 1 are the same. */ -/* - * static const struct pci_driver usb_3_driver __pci_driver = { - * .ops = &usb_ops, - * .vendor = PCI_VENDOR_ID_ATI, - * .device = PCI_DEVICE_ID_ATI_SB800_USB_19_0, - * }; - * static const struct pci_driver usb_4_driver __pci_driver = { - * .ops = &usb_ops, - * .vendor = PCI_VENDOR_ID_ATI, - * .device = PCI_DEVICE_ID_ATI_SB800_USB_19_1, - * }; - */ - -static const struct pci_driver usb_4_driver __pci_driver = { - .ops = &usb_ops, - .vendor = PCI_VENDOR_ID_ATI, - .device = PCI_DEVICE_ID_ATI_SB800_USB_20_5, -}; - -static struct device_operations usb_ops2 = { - .read_resources = pci_ehci_read_resources, - .set_resources = pci_dev_set_resources, - .enable_resources = pci_dev_enable_resources, - .init = usb_init2, - .scan_bus = 0, - .ops_pci = &lops_pci, -}; - -static const struct pci_driver usb_5_driver __pci_driver = { - .ops = &usb_ops2, - .vendor = PCI_VENDOR_ID_ATI, - .device = PCI_DEVICE_ID_ATI_SB800_USB_18_2, -}; -/* - * static const struct pci_driver usb_5_driver __pci_driver = { - * .ops = &usb_ops2, - * .vendor = PCI_VENDOR_ID_ATI, - * .device = PCI_DEVICE_ID_ATI_SB800_USB_19_2, - * }; - */ From fc20682f074a00b93501ad820824fcbd0f2d0ad1 Mon Sep 17 00:00:00 2001 From: Arthur Heymans Date: Tue, 19 Nov 2019 17:23:57 +0100 Subject: [PATCH 0296/1242] sb/amd/sr5650: Drop support MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Relocatable ramstage, postcar stage and C_ENVIRONMENT_BOOTBLOCK are now mandatory features, which platforms using this code lack. Change-Id: I63551b9ad861fecb689036c9f26c3b0950a8b8e9 Signed-off-by: Arthur Heymans Reviewed-on: https://review.coreboot.org/c/coreboot/+/36969 Reviewed-by: Kyösti Mälkki Reviewed-by: Angel Pons Reviewed-by: HAOUAS Elyes Tested-by: build bot (Jenkins) --- src/southbridge/amd/sr5650/Kconfig | 26 - src/southbridge/amd/sr5650/Makefile.inc | 9 - src/southbridge/amd/sr5650/acpi/sr5650.asl | 384 --------- src/southbridge/amd/sr5650/chip.h | 34 - src/southbridge/amd/sr5650/cmn.h | 219 ----- src/southbridge/amd/sr5650/early_setup.c | 586 ------------- src/southbridge/amd/sr5650/ht.c | 290 ------- src/southbridge/amd/sr5650/pcie.c | 940 --------------------- src/southbridge/amd/sr5650/rev.h | 23 - src/southbridge/amd/sr5650/sr5650.c | 931 -------------------- src/southbridge/amd/sr5650/sr5650.h | 139 --- 11 files changed, 3581 deletions(-) delete mode 100644 src/southbridge/amd/sr5650/Kconfig delete mode 100644 src/southbridge/amd/sr5650/Makefile.inc delete mode 100644 src/southbridge/amd/sr5650/acpi/sr5650.asl delete mode 100644 src/southbridge/amd/sr5650/chip.h delete mode 100644 src/southbridge/amd/sr5650/cmn.h delete mode 100644 src/southbridge/amd/sr5650/early_setup.c delete mode 100644 src/southbridge/amd/sr5650/ht.c delete mode 100644 src/southbridge/amd/sr5650/pcie.c delete mode 100644 src/southbridge/amd/sr5650/rev.h delete mode 100644 src/southbridge/amd/sr5650/sr5650.c delete mode 100644 src/southbridge/amd/sr5650/sr5650.h diff --git a/src/southbridge/amd/sr5650/Kconfig b/src/southbridge/amd/sr5650/Kconfig deleted file mode 100644 index 85f6b13013..0000000000 --- a/src/southbridge/amd/sr5650/Kconfig +++ /dev/null @@ -1,26 +0,0 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2010 Advanced Micro Devices, Inc. -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; version 2 of the License. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## - -config SOUTHBRIDGE_AMD_SR5650 - bool - -if SOUTHBRIDGE_AMD_SR5650 -config EXT_CONF_SUPPORT - bool "Enable PCI-E MMCONFIG support" - default y - help - Select to enable PCI-E MMCONFIG support on the SR5650. - -endif diff --git a/src/southbridge/amd/sr5650/Makefile.inc b/src/southbridge/amd/sr5650/Makefile.inc deleted file mode 100644 index f695a112a6..0000000000 --- a/src/southbridge/amd/sr5650/Makefile.inc +++ /dev/null @@ -1,9 +0,0 @@ -ifeq ($(CONFIG_SOUTHBRIDGE_AMD_SR5650),y) - -ramstage-y += sr5650.c -ramstage-y += pcie.c -ramstage-y += ht.c - -romstage-y += early_setup.c - -endif diff --git a/src/southbridge/amd/sr5650/acpi/sr5650.asl b/src/southbridge/amd/sr5650/acpi/sr5650.asl deleted file mode 100644 index 93a74e3507..0000000000 --- a/src/southbridge/amd/sr5650/acpi/sr5650.asl +++ /dev/null @@ -1,384 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2015 Timothy Pearson , Raptor Engineering - * Copyright (C) 2009 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -Scope(\) { - Name(PCBA, CONFIG_MMCONF_BASE_ADDRESS) /* Base address of PCIe config space */ - Name(HPBA, 0xFED00000) /* Base address of HPET table */ - - /* PIC IRQ mapping registers, C00h-C01h */ - OperationRegion(PRQM, SystemIO, 0x00000C00, 0x00000002) - Field(PRQM, ByteAcc, NoLock, Preserve) { - PRQI, 0x00000008, - PRQD, 0x00000008, /* Offset: 1h */ - } - IndexField(PRQI, PRQD, ByteAcc, NoLock, Preserve) { - PINA, 0x00000008, /* Index 0 */ - PINB, 0x00000008, /* Index 1 */ - PINC, 0x00000008, /* Index 2 */ - PIND, 0x00000008, /* Index 3 */ - AINT, 0x00000008, /* Index 4 */ - SINT, 0x00000008, /* Index 5 */ - , 0x00000008, /* Index 6 */ - AAUD, 0x00000008, /* Index 7 */ - AMOD, 0x00000008, /* Index 8 */ - PINE, 0x00000008, /* Index 9 */ - PINF, 0x00000008, /* Index A */ - PING, 0x00000008, /* Index B */ - PINH, 0x00000008, /* Index C */ - } - - /* PCI Error control register */ - OperationRegion(PERC, SystemIO, 0x00000C14, 0x00000001) - Field(PERC, ByteAcc, NoLock, Preserve) { - SENS, 0x00000001, - PENS, 0x00000001, - SENE, 0x00000001, - PENE, 0x00000001, - } - - Scope(\_SB) { - /* PCIe Configuration Space for 16 busses */ - OperationRegion(PCFG, SystemMemory, PCBA, 0x01000000) /* Each bus consumes 1MB */ - Field(PCFG, ByteAcc, NoLock, Preserve) { - /* Byte offsets are computed using the following technique: - * ((bus number + 1) * ((device number * 8) * 4096)) + register offset - * The 8 comes from 8 functions per device, and 4096 bytes per function config space - */ - Offset(0x00088024), /* Byte offset to SATA register 24h - Bus 0, Device 17, Function 0 */ - STB5, 32, - Offset(0x00098042), /* Byte offset to OHCI0 register 42h - Bus 0, Device 19, Function 0 */ - PT0D, 1, - PT1D, 1, - PT2D, 1, - PT3D, 1, - PT4D, 1, - PT5D, 1, - PT6D, 1, - PT7D, 1, - PT8D, 1, - PT9D, 1, - Offset(0x000A0004), /* Byte offset to SMBUS register 4h - Bus 0, Device 20, Function 0 */ - SBIE, 1, - SBME, 1, - Offset(0x000A0008), /* Byte offset to SMBUS register 8h - Bus 0, Device 20, Function 0 */ - SBRI, 8, - Offset(0x000A0014), /* Byte offset to SMBUS register 14h - Bus 0, Device 20, Function 0 */ - SBB1, 32, - Offset(0x000A0078), /* Byte offset to SMBUS register 78h - Bus 0, Device 20, Function 0 */ - ,14, - P92E, 1, /* Port92 decode enable */ - } - - OperationRegion(SB5, SystemMemory, STB5, 0x1000) - Field(SB5, AnyAcc, NoLock, Preserve){ - /* Port 0 */ - Offset(0x120), /* Port 0 Task file status */ - P0ER, 1, - , 2, - P0DQ, 1, - , 3, - P0BY, 1, - Offset(0x128), /* Port 0 Serial ATA status */ - P0DD, 4, - , 4, - P0IS, 4, - Offset(0x12C), /* Port 0 Serial ATA control */ - P0DI, 4, - Offset(0x130), /* Port 0 Serial ATA error */ - , 16, - P0PR, 1, - - /* Port 1 */ - offset(0x1A0), /* Port 1 Task file status */ - P1ER, 1, - , 2, - P1DQ, 1, - , 3, - P1BY, 1, - Offset(0x1A8), /* Port 1 Serial ATA status */ - P1DD, 4, - , 4, - P1IS, 4, - Offset(0x1AC), /* Port 1 Serial ATA control */ - P1DI, 4, - Offset(0x1B0), /* Port 1 Serial ATA error */ - , 16, - P1PR, 1, - - /* Port 2 */ - Offset(0x220), /* Port 2 Task file status */ - P2ER, 1, - , 2, - P2DQ, 1, - , 3, - P2BY, 1, - Offset(0x228), /* Port 2 Serial ATA status */ - P2DD, 4, - , 4, - P2IS, 4, - Offset(0x22C), /* Port 2 Serial ATA control */ - P2DI, 4, - Offset(0x230), /* Port 2 Serial ATA error */ - , 16, - P2PR, 1, - - /* Port 3 */ - Offset(0x2A0), /* Port 3 Task file status */ - P3ER, 1, - , 2, - P3DQ, 1, - , 3, - P3BY, 1, - Offset(0x2A8), /* Port 3 Serial ATA status */ - P3DD, 4, - , 4, - P3IS, 4, - Offset(0x2AC), /* Port 3 Serial ATA control */ - P3DI, 4, - Offset(0x2B0), /* Port 3 Serial ATA error */ - , 16, - P3PR, 1, - } - - Method(CIRQ, 0x00, NotSerialized){ - Store(0, PINA) - Store(0, PINB) - Store(0, PINC) - Store(0, PIND) - Store(0, PINE) - Store(0, PINF) - Store(0, PING) - Store(0, PINH) - } - - /* set "A", 8259 interrupts */ - Name (PRSA, ResourceTemplate () { - IRQ(Level, ActiveLow, Exclusive) {4, 7, 10, 11, 12, 14, 15} - }) - - Method (CRSA, 1, Serialized) { - Name (LRTL, ResourceTemplate() { - IRQ(Level, ActiveLow, Shared) {15} - }) - CreateWordField(LRTL, 1, LIRQ) - ShiftLeft(1, Arg0, LIRQ) - Return (LRTL) - } - - Method (SRSA, 1, Serialized) { - CreateWordField(Arg0, 1, LIRQ) - FindSetRightBit(LIRQ, Local0) - if (Local0) { - Decrement(Local0) - } - Return (Local0) - } - - Device(LNKA) { - Name(_HID, EISAID("PNP0C0F")) - Name(_UID, 1) - Method(_STA, 0) { - if (PINA) { - Return(0x0B) /* LNKA is invisible */ - } else { - Return(0x09) /* LNKA is disabled */ - } - } - Method(_DIS, 0) { - Store(0, PINA) - } - Method(_PRS, 0) { - Return (PRSA) - } - Method (_CRS, 0, Serialized) { - Return (CRSA(PINA)) - } - Method (_SRS, 1, Serialized) { - Store (SRSA(Arg0), PINA) - } - } - - Device(LNKB) { - Name(_HID, EISAID("PNP0C0F")) - Name(_UID, 2) - Method(_STA, 0) { - if (PINB) { - Return(0x0B) /* LNKB is invisible */ - } else { - Return(0x09) /* LNKB is disabled */ - } - } - Method(_DIS, 0) { - Store(0, PINB) - } - Method(_PRS, 0) { - Return (PRSA) - } - Method (_CRS, 0, Serialized) { - Return (CRSA(PINB)) - } - Method (_SRS, 1, Serialized) { - Store (SRSA(Arg0), PINB) - } - } - - Device(LNKC) { - Name(_HID, EISAID("PNP0C0F")) - Name(_UID, 3) - Method(_STA, 0) { - if (PINC) { - Return(0x0B) /* LNKC is invisible */ - } else { - Return(0x09) /* LNKC is disabled */ - } - } - Method(_DIS, 0) { - Store(0, PINC) - } - Method(_PRS, 0) { - Return (PRSA) - } - Method (_CRS, 0, Serialized) { - Return (CRSA(PINC)) - } - Method (_SRS, 1, Serialized) { - Store (SRSA(Arg0), PINC) - } - } - - Device(LNKD) { - Name(_HID, EISAID("PNP0C0F")) - Name(_UID, 4) - Method(_STA, 0) { - if (PIND) { - Return(0x0B) /* LNKD is invisible */ - } else { - Return(0x09) /* LNKD is disabled */ - } - } - Method(_DIS, 0) { - Store(0, PIND) - } - Method(_PRS, 0) { - Return (PRSA) - } - Method (_CRS, 0, Serialized) { - Return (CRSA(PIND)) - } - Method (_SRS, 1, Serialized) { - Store (SRSA(Arg0), PIND) - } - } - - Device(LNKE) { - Name(_HID, EISAID("PNP0C0F")) - Name(_UID, 5) - Method(_STA, 0) { - if (PINE) { - Return(0x0B) /* LNKE is invisible */ - } else { - Return(0x09) /* LNKE is disabled */ - } - } - Method(_DIS, 0) { - Store(0, PINE) - } - Method(_PRS, 0) { - Return (PRSA) - } - Method (_CRS, 0, Serialized) { - Return (CRSA(PINE)) - } - Method (_SRS, 1, Serialized) { - Store (SRSA(Arg0), PINE) - } - } - - Device(LNKF) { - Name(_HID, EISAID("PNP0C0F")) - Name(_UID, 6) - Method(_STA, 0) { - if (PINF) { - Return(0x0B) /* LNKF is invisible */ - } else { - Return(0x09) /* LNKF is disabled */ - } - } - Method(_DIS, 0) { - Store(0, PINF) - } - Method(_PRS, 0) { - Return (PRSA) - } - Method (_CRS, 0, Serialized) { - Return (CRSA(PINF)) - } - Method (_SRS, 1, Serialized) { - Store (SRSA(Arg0), PINF) - } - } - - Device(LNKG) { - Name(_HID, EISAID("PNP0C0F")) - Name(_UID, 7) - Method(_STA, 0) { - if (PING) { - Return(0x0B) /* LNKG is invisible */ - } else { - Return(0x09) /* LNKG is disabled */ - } - } - Method(_DIS, 0) { - Store(0, PING) - } - Method(_PRS, 0) { - Return (PRSA) - } - Method (_CRS, 0, Serialized) { - Return (CRSA(PING)) - } - Method (_SRS, 1, Serialized) { - Store (SRSA(Arg0), PING) - } - } - - Device(LNKH) { - Name(_HID, EISAID("PNP0C0F")) - Name(_UID, 8) - Method(_STA, 0) { - if (PINH) { - Return(0x0B) /* LNKH is invisible */ - } else { - Return(0x09) /* LNKH is disabled */ - } - } - Method(_DIS, 0) { - Store(0, PINH) - } - Method(_PRS, 0) { - Return (PRSA) - } - Method (_CRS, 0, Serialized) { - Return (CRSA(PINH)) - } - Method (_SRS, 1, Serialized) { - Store (SRSA(Arg0), PINH) - } - } - - } /* End Scope(_SB) */ - -} /* End Scope(/) */ diff --git a/src/southbridge/amd/sr5650/chip.h b/src/southbridge/amd/sr5650/chip.h deleted file mode 100644 index 082300edcf..0000000000 --- a/src/southbridge/amd/sr5650/chip.h +++ /dev/null @@ -1,34 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2010 Advanced Micro Devices, Inc. - * Copyright (C) 2015 Timothy Pearson , Raptor Engineering - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef SR5650_CHIP_H -#define SR5650_CHIP_H - -#include - -/* Member variables are defined in Config.lb. */ -struct southbridge_amd_sr5650_config -{ - u8 gpp1_configuration; /* The configuration of General Purpose Port. */ - u8 gpp2_configuration; /* The configuration of General Purpose Port. */ - u8 gpp3a_configuration; /* The configuration of General Purpose Port. */ - u16 port_enable; /* Which port is enabled? GPP(2,3,4,5,6,7,9,10,11,12,13) */ - uint32_t pcie_settling_time; /* How long to wait after link training for PCI-e devices to - * initialize before probing PCI-e busses (in microseconds). - */ -}; - -#endif /* SR5650_CHIP_H */ diff --git a/src/southbridge/amd/sr5650/cmn.h b/src/southbridge/amd/sr5650/cmn.h deleted file mode 100644 index 9588105c5a..0000000000 --- a/src/southbridge/amd/sr5650/cmn.h +++ /dev/null @@ -1,219 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2010 Advanced Micro Devices, Inc. - * Copyright (C) 2015 Timothy Pearson , Raptor Engineering - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef __SR5650_CMN_H__ -#define __SR5650_CMN_H__ - -#include - -#define NBMISC_INDEX 0x60 -#define NBHTIU_INDEX 0x94 /* Note: It is different with RS690, whose HTIU index is 0xA8 */ -#define NBMC_INDEX 0xE8 -#define NBPCIE_INDEX 0xE0 -#define L2CFG_INDEX 0xF0 -#define L1CFG_INDEX 0xF8 -#define EXT_CONF_BASE_ADDRESS CONFIG_MMCONF_BASE_ADDRESS -#define TEMP_MMIO_BASE_ADDRESS 0xC0000000 - -#define axindxc_reg(reg, mask, val) \ - alink_ax_indx(0, (reg), (mask), (val)) - -#define AB_INDX 0xCD8 -#define AB_DATA (AB_INDX+4) - -#if ENV_PCI_SIMPLE_DEVICE -static inline u32 nb_read_index(pci_devfn_t dev, u32 index_reg, u32 index) -#else -static inline u32 nb_read_index(struct device *dev, u32 index_reg, u32 index) -#endif -{ - pci_write_config32(dev, index_reg, index); - return pci_read_config32(dev, index_reg + 0x4); -} - -#if ENV_PCI_SIMPLE_DEVICE -static inline void nb_write_index(pci_devfn_t dev, u32 index_reg, u32 index, - u32 data) -#else -static inline void nb_write_index(struct device *dev, u32 index_reg, u32 index, - u32 data) -#endif -{ - pci_write_config32(dev, index_reg, index); - pci_write_config32(dev, index_reg + 0x4, data); -} - -#if ENV_PCI_SIMPLE_DEVICE -static inline u32 nbmisc_read_index(pci_devfn_t nb_dev, u32 index) -#else -static inline u32 nbmisc_read_index(struct device *nb_dev, u32 index) -#endif -{ - return nb_read_index((nb_dev), NBMISC_INDEX, (index)); -} - -#if ENV_PCI_SIMPLE_DEVICE -static inline void nbmisc_write_index(pci_devfn_t nb_dev, u32 index, u32 data) -#else -static inline void nbmisc_write_index(struct device *nb_dev, u32 index, - u32 data) -#endif -{ - nb_write_index((nb_dev), NBMISC_INDEX, ((index) | 0x80), (data)); -} - -#if ENV_PCI_SIMPLE_DEVICE -static inline void set_nbmisc_enable_bits(pci_devfn_t nb_dev, u32 reg_pos, - u32 mask, u32 val) -#else -static inline void set_nbmisc_enable_bits(struct device *nb_dev, u32 reg_pos, - u32 mask, u32 val) -#endif -{ - u32 reg_old, reg; - reg = reg_old = nbmisc_read_index(nb_dev, reg_pos); - reg &= ~mask; - reg |= val; - if (reg != reg_old) { - nbmisc_write_index(nb_dev, reg_pos, reg); - } -} - -#if ENV_PCI_SIMPLE_DEVICE -static inline u32 htiu_read_index(pci_devfn_t nb_dev, u32 index) -#else -static inline u32 htiu_read_index(struct device *nb_dev, u32 index) -#endif -{ - return nb_read_index((nb_dev), NBHTIU_INDEX, (index)); -} - -#if ENV_PCI_SIMPLE_DEVICE -static inline void htiu_write_index(pci_devfn_t nb_dev, u32 index, u32 data) -#else -static inline void htiu_write_index(struct device *nb_dev, u32 index, u32 data) -#endif -{ - nb_write_index((nb_dev), NBHTIU_INDEX, ((index) | 0x100), (data)); -} - -#if ENV_PCI_SIMPLE_DEVICE -static inline u32 nbmc_read_index(pci_devfn_t nb_dev, u32 index) -#else -static inline u32 nbmc_read_index(struct device *nb_dev, u32 index) -#endif -{ - return nb_read_index((nb_dev), NBMC_INDEX, (index)); -} - -#if ENV_PCI_SIMPLE_DEVICE -static inline void nbmc_write_index(pci_devfn_t nb_dev, u32 index, u32 data) -#else -static inline void nbmc_write_index(struct device *nb_dev, u32 index, u32 data) -#endif -{ - nb_write_index((nb_dev), NBMC_INDEX, ((index) | 1 << 9), (data)); -} - -#if ENV_PCI_SIMPLE_DEVICE -static inline void set_htiu_enable_bits(pci_devfn_t nb_dev, u32 reg_pos, - u32 mask, u32 val) -#else -static inline void set_htiu_enable_bits(struct device *nb_dev, u32 reg_pos, - u32 mask, u32 val) -#endif -{ - u32 reg_old, reg; - reg = reg_old = htiu_read_index(nb_dev, reg_pos); - reg &= ~mask; - reg |= val; - if (reg != reg_old) { - htiu_write_index(nb_dev, reg_pos, reg); - } -} - -#if ENV_PCI_SIMPLE_DEVICE -static inline void set_nbcfg_enable_bits(pci_devfn_t nb_dev, u32 reg_pos, - u32 mask, u32 val) -#else -static inline void set_nbcfg_enable_bits(struct device *nb_dev, u32 reg_pos, - u32 mask, u32 val) -#endif -{ - u32 reg_old, reg; - reg = reg_old = pci_read_config32(nb_dev, reg_pos); - reg &= ~mask; - reg |= val; - if (reg != reg_old) { - pci_write_config32(nb_dev, reg_pos, reg); - } -} - -#if ENV_PCI_SIMPLE_DEVICE -static inline void set_nbcfg_enable_bits_8(pci_devfn_t nb_dev, u32 reg_pos, - u8 mask, u8 val) -#else -static inline void set_nbcfg_enable_bits_8(struct device *nb_dev, u32 reg_pos, - u8 mask, u8 val) -#endif -{ - u8 reg_old, reg; - reg = reg_old = pci_read_config8(nb_dev, reg_pos); - reg &= ~mask; - reg |= val; - if (reg != reg_old) { - pci_write_config8(nb_dev, reg_pos, reg); - } -} - -#if ENV_PCI_SIMPLE_DEVICE -static inline void set_nbmc_enable_bits(pci_devfn_t nb_dev, u32 reg_pos, - u32 mask, u32 val) -#else -static inline void set_nbmc_enable_bits(struct device *nb_dev, u32 reg_pos, - u32 mask, u32 val) -#endif -{ - u32 reg_old, reg; - reg = reg_old = nbmc_read_index(nb_dev, reg_pos); - reg &= ~mask; - reg |= val; - if (reg != reg_old) { - nbmc_write_index(nb_dev, reg_pos, reg); - } -} - -#if ENV_PCI_SIMPLE_DEVICE -static inline void set_pcie_enable_bits(pci_devfn_t dev, u32 reg_pos, u32 mask, - u32 val) -#else -static inline void set_pcie_enable_bits(struct device *dev, u32 reg_pos, - u32 mask, u32 val) -#endif -{ - u32 reg_old, reg; - reg = reg_old = nb_read_index(dev, NBPCIE_INDEX, reg_pos); - reg &= ~mask; - reg |= val; - if (reg != reg_old) { - nb_write_index(dev, NBPCIE_INDEX, reg_pos, reg); - } -} - -void set_pcie_reset(void); -void set_pcie_dereset(void); - -#endif /* __SR5650_CMN_H__ */ diff --git a/src/southbridge/amd/sr5650/early_setup.c b/src/southbridge/amd/sr5650/early_setup.c deleted file mode 100644 index b119df287a..0000000000 --- a/src/southbridge/amd/sr5650/early_setup.c +++ /dev/null @@ -1,586 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2015 Timothy Pearson , Raptor Engineering - * Copyright (C) 2010 Advanced Micro Devices, Inc. - * Copyright (C) 2015 Timothy Pearson , Raptor Engineering - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include "sr5650.h" -#include "cmn.h" - -/* space = 0: AX_INDXC, AX_DATAC - * space = 1: AX_INDXP, AX_DATAP - */ -static void alink_ax_indx(u32 space, u32 axindc, u32 mask, u32 val) -{ - u32 tmp; - - /* read axindc to tmp */ - outl(space << 30 | space << 3 | 0x30, AB_INDX); - outl(axindc, AB_DATA); - outl(space << 30 | space << 3 | 0x34, AB_INDX); - tmp = inl(AB_DATA); - - tmp &= ~mask; - tmp |= val; - - /* write tmp */ - outl(space << 30 | space << 3 | 0x30, AB_INDX); - outl(axindc, AB_DATA); - outl(space << 30 | space << 3 | 0x34, AB_INDX); - outl(tmp, AB_DATA); -} - - -static void set_fam10_ext_cfg_enable_bits(pci_devfn_t fam10_dev, - u32 reg_pos, u32 mask, u32 val) -{ - u32 reg_old, reg; - - /* family 10 only, for reg > 0xFF */ - if (!CONFIG(NORTHBRIDGE_AMD_AMDFAM10)) - return; - - reg = reg_old = pci_read_config32(fam10_dev, reg_pos); - reg &= ~mask; - reg |= val; - if (reg != reg_old) { - pci_write_config32(fam10_dev, reg_pos, reg); - } -} - -/* -* Compliant with CIM_33's ATINB_PrepareInit -*/ -static void get_cpu_rev(void) -{ - u32 eax; - - eax = cpuid_eax(1); - printk(BIOS_INFO, "get_cpu_rev EAX=0x%x.\n", eax); - if (eax <= 0xfff) - printk(BIOS_INFO, "CPU Rev is K8_Cx.\n"); - else if (eax <= 0x10fff) - printk(BIOS_INFO, "CPU Rev is K8_Dx.\n"); - else if (eax <= 0x20fff) - printk(BIOS_INFO, "CPU Rev is K8_Ex.\n"); - else if (eax <= 0x40fff) - printk(BIOS_INFO, "CPU Rev is K8_Fx.\n"); - else if (eax == 0x60fb1 || eax == 0x60f81) /*These two IDS are exception, they are G1. */ - printk(BIOS_INFO, "CPU Rev is K8_G1.\n"); - else if (eax <= 0X60FF0) - printk(BIOS_INFO, "CPU Rev is K8_G0.\n"); - else if (eax <= 0x100000) - printk(BIOS_INFO, "CPU Rev is K8_G1.\n"); - else if (eax <= 0x100fa0) - printk(BIOS_INFO, "CPU Rev is Fam 10.\n"); - else if (eax <= 0x600f20) - printk(BIOS_INFO, "CPU Rev is Fam 15.\n"); - else - printk(BIOS_INFO, "CPU Rev is not recognized.\n"); -} - -/* -CIM NB_GetRevisionInfo() -*/ -static u8 get_nb_rev(pci_devfn_t nb_dev) -{ - u8 reg; - reg = pci_read_config8(nb_dev, 0x8); /* copy from CIM, can't find in doc */ - switch (reg & 3) - { - case 0x00: - reg = REV_SR5650_A11; - break; - case 0x02: - default: - reg = REV_SR5650_A12; - break; - } - return reg; -} - -/***************************************** -* Compliant with SR5650_CIMX_4_5_0 NBHT_InitHT(). -* Init HT link speed/width for sr5650 -- k8 link -1: Check CPU Family, Family10? -2: Get CPU's HT speed and width -3: Decide HT mode 1 or 3 by HT Speed. >1GHz: HT3, else HT1 -4: -*****************************************/ -static const u8 sr5650_ibias[] = { - /* 1, 3 are reserved. */ - [0x0] = 0x44, /* 200MHz HyperTransport 1 only */ - [0x2] = 0x44, /* 400MHz HyperTransport 1 only */ - [0x4] = 0xB6, /* 600MHz HyperTransport 1 only */ - [0x5] = 0x44, /* 800MHz HyperTransport 1 only */ - [0x6] = 0x96, /* 1GHz HyperTransport 1 only */ - /* HT3 for Family 10 */ - [0x7] = 0xB6, /* 1.2GHz HyperTransport 3 only */ - [0x8] = 0x23, /* 1.4GHz HyperTransport 3 only */ - [0x9] = 0x44, /* 1.6GHz HyperTransport 3 only */ - [0xa] = 0x64, /* 1.8GHz HyperTransport 3 only */ - [0xb] = 0x96, /* 2.0GHz HyperTransport 3 only */ - [0xc] = 0xA6, /* 2.2GHz HyperTransport 3 only */ - [0xd] = 0xB6, /* 2.4GHz HyperTransport 3 only */ - [0xe] = 0xC6, /* 2.6GHz HyperTransport 3 only */ -}; - -void sr5650_htinit(void) -{ - /* - * About HT, it has been done in enumerate_ht_chain(). - */ - pci_devfn_t cpu_f0, sr5650_f0, clk_f1; - u32 reg; - u8 cpu_ht_freq, cpu_htfreq_max, ibias; - u8 sbnode; - u8 sblink; - u16 linkfreq_reg; - u16 linkfreqext_reg; - - /************************ - * get cpu's ht freq, in cpu's function 0, offset 0x88 - * bit11-8, specifics the maximum operation frequency of the link's transmitter clock. - * The link frequency field (Frq) is cleared by cold reset. SW can write a nonzero - * value to this reg, and that value takes effect on the next warm reset or - * LDTSTOP_L disconnect sequence. - * please see the table sr5650_ibias about the value and its corresponding frequency. - ************************/ - /* Link0, Link1 are for connection between P0 and P1. - * TODO: Check the topology of the MP and NB. Or we just read the nbconfig? */ - /* NOTE: In most cases, we only have one CPU. In that case, we should read 0x88. */ - - /* Find out the node ID and the Link ID that - * connects to the Southbridge (system IO hub). - */ - sbnode = (pci_read_config32(PCI_DEV(0, 0x18, 0), 0x60) >> 8) & 7; - sblink = (pci_read_config32(PCI_DEV(0, 0x18, 0), 0x64) >> 8) & 3; /* bit[10] sublink, bit[9,8] link. */ - cpu_f0 = PCI_DEV(0, (0x18 + sbnode), 0); - - /* - * link freq reg of Link0, 1, 2, 3 is 0x88, 0xA8, 0xC8, 0xE8 respectively - * link freq ext reg of Link0, 1, 2, 3 is 0x9C, 0xBC, 0xDC, 0xFC respectively - */ - linkfreq_reg = 0x88 + (sblink << 5); - linkfreqext_reg = 0x9C + (sblink << 5); - reg = pci_read_config32(cpu_f0, linkfreq_reg); - - cpu_ht_freq = (reg & 0xf00) >> 8; - - /* Freq[4] is only valid for revision D and later processors */ - if (cpuid_eax(1) >= 0x100F80) { - cpu_htfreq_max = 0x14; - cpu_ht_freq |= ((pci_read_config32(cpu_f0, linkfreqext_reg) & 0x01) << 4); - } else { - cpu_htfreq_max = 0x0F; - } - - printk(BIOS_INFO, "sr5650_htinit: Node %x Link %x, HT freq=%x.\n", - sbnode, sblink, cpu_ht_freq); - sr5650_f0 = PCI_DEV(0, 0, 0); - - clk_f1 = PCI_DEV(0, 0, 1); /* We need to make sure the F1 is accessible. */ - - ibias = sr5650_ibias[cpu_ht_freq]; - - /* If HT freq>1GHz, we assume the CPU is fam10, else it is K8. - * Is it appropriate? - * Frequency is 1GHz, i.e. cpu_ht_freq is 6, in most cases. - * So we check 6 only, it would be faster. */ - if ((cpu_ht_freq == 0x6) || (cpu_ht_freq == 0x5) || (cpu_ht_freq == 0x4) || - (cpu_ht_freq == 0x2) || (cpu_ht_freq == 0x0)) { - printk(BIOS_INFO, "sr5650_htinit: HT1 mode\n"); - - /* HT1 mode, RPR 5.4.2 */ - /* set IBIAS code */ - set_nbcfg_enable_bits(clk_f1, 0xD8, 0x3FF, ibias); - /* Optimizes chipset HT transmitter drive strength */ - set_htiu_enable_bits(sr5650_f0, 0x2A, 0x3, 0x3); - } else if ((cpu_ht_freq > 0x6) && (cpu_ht_freq < cpu_htfreq_max)) { - printk(BIOS_INFO, "sr5650_htinit: HT3 mode\n"); - - /* Enable Protocol checker */ - set_htiu_enable_bits(sr5650_f0, 0x1E, 0xFFFFFFFF, 0x7FFFFFFC); - -#if CONFIG(NORTHBRIDGE_AMD_AMDFAM10) - /* HT3 mode, RPR 5.4.3 */ - set_nbcfg_enable_bits(sr5650_f0, 0x9c, 0x3 << 16, 0); - - /* set IBIAS code */ - set_nbcfg_enable_bits(clk_f1, 0xD8, 0x3FF, ibias); - /* Optimizes chipset HT transmitter drive strength */ - set_htiu_enable_bits(sr5650_f0, 0x2A, 0x3, 0x1); - /* Enables error-retry mode */ - set_nbcfg_enable_bits(sr5650_f0, 0x44, 0x1, 0x1); - /* Enables scrambling and Disables command throttling */ - set_nbcfg_enable_bits(sr5650_f0, 0xac, (1 << 3) | (1 << 14), (1 << 3) | (1 << 14)); - /* Enables transmitter de-emphasis */ - set_nbcfg_enable_bits(sr5650_f0, 0xa4, 1 << 31, 1 << 31); - /* Enables transmitter de-emphasis level */ - /* Sets training 0 time */ - set_nbcfg_enable_bits(sr5650_f0, 0xa0, 0x3F, 0x14); - - /* Enables strict TM4 detection */ - set_htiu_enable_bits(sr5650_f0, 0x15, 0x1 << 22, 0x1 << 22); - - /* Optimizes chipset HT transmitter drive strength */ - set_htiu_enable_bits(sr5650_f0, 0x2A, 0x3 << 0, 0x1 << 0); - - /* HyperTransport 3 Processor register settings to be done in northbridge */ - - /* Enables error-retry mode */ - set_fam10_ext_cfg_enable_bits(cpu_f0, 0x130 + (sblink << 2), 1 << 0, 1 << 0); - - /* Enables scrambling */ - set_fam10_ext_cfg_enable_bits(cpu_f0, 0x170 + (sblink << 2), 1 << 3, 1 << 3); - - /* Enables transmitter de-emphasis - * This depends on the PCB design and the trace - */ - /* Disables command throttling */ - set_fam10_ext_cfg_enable_bits(cpu_f0, 0x168, 1 << 10, 1 << 10); - - /* Sets Training 0 Time. See T0Time table for encodings */ - /* AGESA have set it to recommended value already - * The recommended values are 14h(2us) if F0x[18C:170][LS2En]=0 - * and 26h(12us) if F0x[18C:170][LS2En]=1 - */ - //set_fam10_ext_cfg_enable_bits(cpu_f0, 0x16C, 0x3F, 0x26); - - /* HT Buffer Allocation for Ganged Links!!! */ -#endif /* CONFIG_NORTHBRIDGE_AMD_AMDFAM10 */ - } - -} - -/* Must be run immediately after HT setup is complete and first warm reset has occurred (if applicable) - * Attempting to switch the NB into isochronous mode before the CPUs have engaged isochronous mode - * will cause a system hard lockup... - */ -void sr5650_htinit_dect_and_enable_isochronous_link(void) -{ - pci_devfn_t sr5650_f0; - unsigned char iommu; - - sr5650_f0 = PCI_DEV(0, 0, 0); - - iommu = 1; - get_option(&iommu, "iommu"); - - if (iommu) { - /* Enable isochronous mode */ - set_nbcfg_enable_bits(sr5650_f0, 0xc8, 1 << 12, 1 << 12); - - /* Apply pending changes */ - if (!((pci_read_config32(sr5650_f0, 0xc8) >> 12) & 0x1)) { - printk(BIOS_INFO, "...WARM RESET...\n\n\n"); - soft_reset(); - die("After soft_reset - shouldn't see this message!!!\n"); - } - } -} - -void fam10_optimization(void) -{ - pci_devfn_t cpu_f0, cpu_f2, cpu_f3; - pci_devfn_t cpu1_f0, cpu1_f2, cpu1_f3; - msr_t msr; - u32 val; - - if (!CONFIG(NORTHBRIDGE_AMD_AMDFAM10)) - return; - - printk(BIOS_INFO, "fam10_optimization()\n"); - msr = rdmsr(NB_CFG_MSR); - msr.hi |= 1 << 14; /* bit 46: EnableCf8ExtCfg */ - wrmsr(NB_CFG_MSR, msr); - - cpu_f0 = PCI_DEV(0, 0x18, 0); - cpu_f2 = PCI_DEV(0, 0x18, 2); - cpu_f3 = PCI_DEV(0, 0x18, 3); - cpu1_f0 = PCI_DEV(0, 0x19, 0); - cpu1_f2 = PCI_DEV(0, 0x19, 2); - cpu1_f3 = PCI_DEV(0, 0x19, 3); - - val = pci_read_config32(cpu1_f3, 0x8C); - val |= 1 << 14; - pci_write_config32(cpu1_f3, 0x8C, val); - - /* TODO: HT Buffer Allocation for (un)Ganged Links */ - /* rpr Table 5-11, 5-12 */ -} - -/***************************************** -* Compliant with CIM_33's ATINB_PCICFG_POR_TABLE -*****************************************/ -static void sr5650_por_pcicfg_init(pci_devfn_t nb_dev) -{ - /* enable PCI Memory Access */ - set_nbcfg_enable_bits_8(nb_dev, 0x04, (u8)(~0xFD), 0x02); - - set_nbcfg_enable_bits(nb_dev, 0x14, ~0, 0x0); - set_nbcfg_enable_bits(nb_dev, 0x18, ~0, 0x0); - set_nbcfg_enable_bits(nb_dev, 0x20, ~0, 0x0); - set_nbcfg_enable_bits(nb_dev, 0x84, ~0, 0x03000010); - - /* Reg4Ch[1]=1 (APIC_ENABLE) force CPU request with address 0xFECx_xxxx to south-bridge - * Reg4Ch[6]=1 (BMMsgEn) enable BM_Set message generation - * BMMsgEn */ - set_nbcfg_enable_bits(nb_dev, 0x4C, (u8)(~0x00), 0x52042); - - set_nbcfg_enable_bits(nb_dev, 0x7C, (u8)(~0), 0x0); - - /* Reg8Ch[10:9] = 0x3 Enables Gfx Debug BAR, - * force this BAR as mem type in sr5650_gfx.c */ - //set_nbcfg_enable_bits_8(nb_dev, 0x8D, (u8)(~0xFF), 0x03); -} - -/***************************************** -* Compliant with CIM_33's ATINB_MISCIND_POR_TABLE -* Compliant with CIM_33's MISC_INIT_TBL -*****************************************/ -static void sr5650_por_misc_index_init(pci_devfn_t nb_dev) -{ - unsigned char iommu; - - iommu = 1; - get_option(&iommu, "iommu"); - - if (iommu) { - /* enable IOMMU */ - printk(BIOS_DEBUG, "Enabling IOMMU\n"); - set_nbmisc_enable_bits(nb_dev, 0x75, 0x1, 0x1); - } else { - /* disable IOMMU */ - printk(BIOS_DEBUG, "Disabling IOMMU\n"); - set_nbmisc_enable_bits(nb_dev, 0x75, 0x1, 0x0); - } - - /* NBMISCIND:0x75[29]= 1 Device ID for hotplug and PME message */ - set_nbmisc_enable_bits(nb_dev, 0x75, 1 << 29, 1 << 29); - set_nbmisc_enable_bits(nb_dev, 0x75, 1 << 9, 1 << 9); /* no doc reference, comply with BTS */ - set_nbmisc_enable_bits(nb_dev, 0x46, 1 << 7, 1 << 7); /* bit7 BTS fail*/ - /*P2P*/ - set_nbmisc_enable_bits(nb_dev, 0x48, 1 << 8, 0); - - set_nbmisc_enable_bits(nb_dev, 0x2A, 1 << 15 | 1 << 17, 1 << 17); - set_nbmisc_enable_bits(nb_dev, 0x2B, 1 << 15 | 1 << 27, 1 << 15 | 1 << 27); - set_nbmisc_enable_bits(nb_dev, 0x2C, 1 << 0 | 1 << 1 | 1 << 5 | 1 << 4 | 1 << 10, 1 << 0 | 1 << 1 | 1 << 5); - set_nbmisc_enable_bits(nb_dev, 0x32, 0x3F << 20, 0x2A << 20); - set_nbmisc_enable_bits(nb_dev, 0x34, 1 << 7 | 1 << 15 | 1 << 23, 0); - set_nbmisc_enable_bits(nb_dev, 0x35, 0x3F << 26, 0x2A << 26); - set_nbmisc_enable_bits(nb_dev, 0x37, 0xfff << 20, 0xddd << 20); - set_nbmisc_enable_bits(nb_dev, 0x37, 7 << 11, 0); - /* PCIE CDR setting */ - set_nbmisc_enable_bits(nb_dev, 0x38, 0xFFFFFFFF, 0xC0C0C0); - set_nbmisc_enable_bits(nb_dev, 0x22, 0xFFFFFFFF, (1 << 27) | (0x8 << 12) | (0x8 << 16) | (0x8 << 20)); - set_nbmisc_enable_bits(nb_dev, 0x22, 1 << 1 | 1 << 2 | 1 << 6 | 1 << 7, 1 << 1 | 1 << 2 | 1 << 6 | 1 << 7); - - set_nbmisc_enable_bits(nb_dev, 0x07, 0xF << 4 | 1 << 24, 0xF << 4 | 1 << 24); - set_nbmisc_enable_bits(nb_dev, 0x67, 1 << 10 | 1 << 11 | 1 << 26, 1 << 11); - set_nbmisc_enable_bits(nb_dev, 0x67, 3 << 21, 3 << 21); - set_nbmisc_enable_bits(nb_dev, 0x68, 1 << 8 | 1 << 9 | 1 << 19, 1 << 9 | 1 << 19); - set_nbmisc_enable_bits(nb_dev, 0x6B, 3 << 3 | 1 << 15 | 0x1F << 27, 3 << 3 | 1 << 15 | 0x1F << 27); - set_nbmisc_enable_bits(nb_dev, 0x6C, 0xFFFFFFFF, 0x41183000); - - /* NB_MISC_IND_WR_EN + IOC_PCIE_CNTL - * Block non-snoop DMA request if PMArbDis is set. - * Set BMSetDis */ - set_nbmisc_enable_bits(nb_dev, 0x0B, 0xFFFFFFFF, 0x00400180); - set_nbmisc_enable_bits(nb_dev, 0x01, 0xFFFFFFFF, 0x00000310); - - /* NBCFG (NBMISCIND 0x0): NB_CNTL - - * HIDE_NB_AGP_CAP ([0], default=1)HIDE - * HIDE_P2P_AGP_CAP ([1], default=1)HIDE - * HIDE_NB_GART_BAR ([2], default=1)HIDE - * HIDE_MMCFG_BAR ([3], default=1)SHOW - * AGPMODE30 ([4], default=0)DISABLE - * AGP30ENCHANCED ([5], default=0)DISABLE - * HIDE_CLKCFG_HEADER ([8], default=0)SHOW */ - set_nbmisc_enable_bits(nb_dev, 0x00, 0x0000FFFF, 0 << 0 | 1 << 1 | 1 << 2 | 0 << 3 | 0 << 6 | 0 << 8); - - /* IOC_LAT_PERF_CNTR_CNTL */ - set_nbmisc_enable_bits(nb_dev, 0x30, 0xFF, 0x00); - //set_nbmisc_enable_bits(nb_dev, 0x31, 0xFF, 0x00); - - /* IOC_LAT_PERF_CNTR_OUT */ - /* IOC_JTAG_CNTL */ - set_nbmisc_enable_bits(nb_dev, 0x47, 0xFFFFFFFF, 0x0000000B); - - set_nbmisc_enable_bits(nb_dev, 0x12, 0xFFFFFFFF, 0x00FB5555); - set_nbmisc_enable_bits(nb_dev, 0x0C, 0xFFFFFFFF, 0x001F37FC); - set_nbmisc_enable_bits(nb_dev, 0x15, 0xFFFFFFFF, 0x0); - - /* NB_PROG_DEVICE_REMAP */ - set_nbmisc_enable_bits(nb_dev, 0x20, 0xFFFFFFFF, 0x0); - set_nbmisc_enable_bits(nb_dev, 0x21, 0xFFFFFFFF, 0x0); - - /* Compliant with CIM_33's MISC_INIT_TBL, except Hide NB_BAR3_PCIE - * Enable access to DEV8 - * Enable setPower message for all ports - */ - set_nbmisc_enable_bits(nb_dev, 0x51, 1 << 20 | 1 << 8, 1 << 20 | 1 << 8); - set_nbmisc_enable_bits(nb_dev, 0x53, 1 << 20 | 1 << 8, 1 << 20 | 1 << 8); - set_nbmisc_enable_bits(nb_dev, 0x55, 1 << 20 | 1 << 8, 1 << 20 | 1 << 8); - set_nbmisc_enable_bits(nb_dev, 0x57, 1 << 20 | 1 << 8, 1 << 20 | 1 << 8); - set_nbmisc_enable_bits(nb_dev, 0x59, 1 << 20 | 1 << 8, 1 << 20 | 1 << 8); - set_nbmisc_enable_bits(nb_dev, 0x5B, 1 << 20 | 1 << 8, 1 << 20 | 1 << 8); - set_nbmisc_enable_bits(nb_dev, 0x5D, 1 << 20 | 1 << 8, 1 << 20 | 1 << 8); - set_nbmisc_enable_bits(nb_dev, 0x5F, 1 << 20 | 1 << 8, 1 << 20 | 1 << 8); - set_nbmisc_enable_bits(nb_dev, 0x61, 1 << 20 | 1 << 8, 1 << 20 | 1 << 8); - set_nbmisc_enable_bits(nb_dev, 0x63, 1 << 20 | 1 << 8, 1 << 20 | 1 << 8); - - /* Disable bus-master trigger event from SB and Enable set_slot_power message to SB */ - set_nbmisc_enable_bits(nb_dev, 0x0B, 0xffffffff, 0x400180); -} - -/***************************************** -* Some setting is from rpr. Some is from CIMx. -*****************************************/ -static void sr5650_por_htiu_index_init(pci_devfn_t nb_dev) -{ - pci_devfn_t cpu_f0; - - cpu_f0 = PCI_DEV(0, 0x18, 0); - - set_htiu_enable_bits(nb_dev, 0x1C, 0x1<<17, 0x1<<17); - set_htiu_enable_bits(nb_dev, 0x05, 0x1<<8, 0x1<<8); - set_htiu_enable_bits(nb_dev, 0x06, 0x1<<0, 0x0<<0); - set_htiu_enable_bits(nb_dev, 0x06, 0x1<<1, 0x1<<1); - set_htiu_enable_bits(nb_dev, 0x06, 0x1<<9, 0x1<<9); - set_htiu_enable_bits(nb_dev, 0x06, 0x1<<13, 0x1<<13); - set_htiu_enable_bits(nb_dev, 0x06, 0x1<<17, 0x1<<17); - set_htiu_enable_bits(nb_dev, 0x06, 0x3<<15, 0x3<<15); - set_htiu_enable_bits(nb_dev, 0x06, 0x1<<25, 0x1<<25); - set_htiu_enable_bits(nb_dev, 0x06, 0x1<<30, 0x1<<30); - - set_htiu_enable_bits(nb_dev, 0x07, 0x1 << 0 | 0x1 << 1 | 0x1 << 2, 0x1 << 0); - - set_htiu_enable_bits(nb_dev, 0x16, 0x1<<11, 0x1<<11); - - set_htiu_enable_bits(nb_dev, 0x1D, 0x1<<2, 0x1<<2); - set_htiu_enable_bits(nb_dev, 0x1D, 0x1<<4, 0x1<<4); - - axindxc_reg(0x10, 1 << 9, 1 << 9); - set_pcie_enable_bits(nb_dev, 0x10 | 5 << 16, 1 << 9, 1 << 9); - set_htiu_enable_bits(nb_dev, 0x06, 0x1<<26, 0x1<<26); - set_htiu_enable_bits(nb_dev, 0x16, 0x1<<10, 0x1<<10); - - /* Enable BIAS circuit for all lanes. */ - //set_htiu_enable_bits(nb_dev, 0x2B, 0xF<<28, 0xF<<28); - set_htiu_enable_bits(nb_dev, 0x2B, 0xF << 28, 0); - set_htiu_enable_bits(nb_dev, 0x05, 0xFFFFFF, 0xFF558); - set_htiu_enable_bits(nb_dev, 0x06, 0xFFFFFFFE, 0x04203A202); - set_htiu_enable_bits(nb_dev, 0x0C, 0xFFFF, 0x101); - - /* A21 only */ - //if (REV_SR5650_A21 == get_nb_rev(nb_dev)) { - if (get_nb_rev(nb_dev) > REV_SR5650_A11) { - set_htiu_enable_bits(nb_dev, 0x05, 0x3<<3| 1<<6 | 1<<10 | 0xFF<<12, 0x3<<3 | 1<<6 | 1<<10 | 0xFF<<12); - set_htiu_enable_bits(nb_dev, 0x1D, 1 << 2 | 1 << 4, 0); - } -} - -/***************************************** -* Compliant with CIM_33's ATINB_POR_INIT_JMPDI -* Configure SR5650 registers to power-on default RPR. -* POR: Power On Reset -* RPR: Register Programming Requirements -*****************************************/ -static void sr5650_por_init(pci_devfn_t nb_dev) -{ - printk(BIOS_INFO, "sr5650_por_init\n"); - /* ATINB_PCICFG_POR_TABLE, initialize the values for sr5650 PCI Config registers */ - sr5650_por_pcicfg_init(nb_dev); - - /* ATINB_MISCIND_POR_TABLE */ - sr5650_por_misc_index_init(nb_dev); - - /* ATINB_HTIUNBIND_POR_TABLE */ - sr5650_por_htiu_index_init(nb_dev); - - /* ATINB_CLKCFG_PORT_TABLE */ - /* sr5650 A11 SB Link full swing? */ -} - -/* enable CFG access to Dev8, which is the SB P2P Bridge */ -void enable_sr5650_dev8(void) -{ - set_nbmisc_enable_bits(PCI_DEV(0, 0, 0), 0x00, 1 << 6, 1 << 6); -} - -/* -* Compliant with CIM_33's AtiNBInitEarlyPost (AtiInitNBBeforePCIInit). -*/ -void sr5650_before_pci_init(void) -{ -} - -/* -* The calling sequence is same as CIM. -*/ -void sr5650_early_setup(void) -{ - pci_devfn_t nb_dev = PCI_DEV(0, 0, 0); - printk(BIOS_INFO, "sr5650_early_setup()\n"); - - /*ATINB_PrepareInit */ - get_cpu_rev(); - - uint8_t revno = get_nb_rev(nb_dev); - switch (revno) { /* PCIEMiscInit */ - case REV_SR5650_A11: - printk(BIOS_INFO, "NB Revision is A11.\n"); - break; - case REV_SR5650_A12: - printk(BIOS_INFO, "NB Revision is A12.\n"); - break; - case REV_SR5650_A21: - printk(BIOS_INFO, "NB Revision is A21.\n"); - break; - default: - printk(BIOS_INFO, "NB Revision is %02x (Unrecognized).\n", revno); - break; - } - - fam10_optimization(); - sr5650_por_init(nb_dev); -} - -/** - * @brief disable GPP1 Port0,1, GPP2, GPP3a Port0,1,2,3,4,5, GPP3b - * - */ -void sr5650_disable_pcie_bridge(void) -{ - u32 mask; - u32 reg; - pci_devfn_t nb_dev = PCI_DEV(0, 0, 0); - - mask = (1 << 2) | (1 << 3); /*GPP1*/ - mask |= (1 << 4) | (1 << 5) | (1 << 6) | (1 << 7) | (1 << 16) | (1 << 17); /*GPP3a*/ - mask |= (1 << 18) | (1 << 19); /*GPP2*/ - mask |= (1 << 20); /*GPP3b*/ - reg = mask; - set_nbmisc_enable_bits(nb_dev, 0x0c, mask, reg); -} diff --git a/src/southbridge/amd/sr5650/ht.c b/src/southbridge/amd/sr5650/ht.c deleted file mode 100644 index c08809f4aa..0000000000 --- a/src/southbridge/amd/sr5650/ht.c +++ /dev/null @@ -1,290 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2010 Advanced Micro Devices, Inc. - * Copyright (C) 2015 Timothy Pearson , Raptor Engineering - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include -#include -#include -#include -#include "sr5650.h" -#include "cmn.h" - -/* Table 6-6 Recommended Interrupt Routing Configuration */ -typedef struct _apic_device_info { - u8 group; - u8 swizzle; - u8 pin; -} apic_device_info; - -#define ABCD 0 -#define BCDA 1 -#define CDAB 2 -#define DABC 3 - -static const apic_device_info default_apic_device_info_t [] = { - /* Group Swizzling Port Int Pin */ - [0] = {0, 0, 31}, /* HT */ - [1] = {0, 0, 31}, /* IOMMU */ - [2] = {0, ABCD, 28}, /* Dev2 Grp0 [Int - 0..3] */ - [3] = {1, ABCD, 28}, /* Dev3 Grp1 [Int - 4..7] */ - [4] = {5, ABCD, 28}, /* Dev4 Grp5 [Int - 20..23] */ - [5] = {5, CDAB, 28}, /* Dev5 Grp5 [Int - 20..23] */ - [6] = {6, BCDA, 29}, /* Dev6 Grp6 [Int - 24..27] */ - [7] = {6, CDAB, 29}, /* Dev7 Grp6 [Int - 24..27] */ - [8] = {0, 0, 0 }, /* Reserved */ - [9] = {6, ABCD, 29}, /* Dev9 Grp6 [Int - 24..27] */ - [10] = {5, BCDA, 30}, /* Dev10 Grp5 [Int - 20..23] */ - [11] = {2, ABCD, 30}, /* Dev11 Grp2 [Int - 8..11] */ - [12] = {3, ABCD, 30}, /* Dev12 Grp3 [Int - 12..15] */ - [13] = {4, ABCD, 30} /* Dev13 Grp4 [Int - 16..19] */ -}; - -/* These define names are common, so undefine them to avoid potential issues in other code */ -#undef ABCD -#undef BCDA -#undef CDAB -#undef DABC - -/* Init APIC of sr5690 */ -static void sr5690_apic_init(struct device *dev) -{ - u32 dword; - const apic_device_info *entry = default_apic_device_info_t; - - /* rpr6.2.(2). Write to the IOAPIC Features Enable register */ - pci_write_config32(dev, 0xF8, 0x0); - pci_write_config32(dev, 0xFC, 0x1F); - /* rpr6.2.(3). Write to the remaining interrupt routing registers */ - - /* IOAPICCMISCIND:0x3, group & swizzle of Dev 2,3,4,5 */ - dword = (entry[2].group | entry[2].swizzle << 4) << 0 | - (entry[3].group | entry[3].swizzle << 4) << 8 | - (entry[4].group | entry[4].swizzle << 4) << 16 | - (entry[5].group | entry[5].swizzle << 4) << 24; - pci_write_config32(dev, 0xF8, 0x3); - pci_write_config32(dev, 0xFC, dword); - - /* IOAPICCMISCIND:0x4, group & swizzle of Dev 6,7,9,10 */ - dword = (entry[6].group | entry[6].swizzle << 4) << 0 | - (entry[7].group | entry[7].swizzle << 4) << 8 | - (entry[9].group | entry[9].swizzle << 4) << 16 | - (entry[10].group | entry[10].swizzle << 4) << 24; - pci_write_config32(dev, 0xF8, 0x4); - pci_write_config32(dev, 0xFC, dword); - - /* IOAPICCMISCIND:0x5, group & swizzle of Dev 11,12,13 */ - dword = (entry[11].group | entry[11].swizzle << 4) << 0 | - (entry[12].group | entry[12].swizzle << 4) << 8 | - (entry[13].group | entry[13].swizzle << 4) << 16; - pci_write_config32(dev, 0xF8, 0x5); - pci_write_config32(dev, 0xFC, dword); - - /* IOAPICCMISCIND:0x6, pin map of dev 2,3,4,5 */ - dword = entry[2].pin | - entry[3].pin << 8 | - entry[4].pin << 16| - entry[5].pin << 24; - pci_write_config32(dev, 0xF8, 0x6); - pci_write_config32(dev, 0xFC, dword); - - /* IOAPICCMISCIND:0x7, pin map of dev 6,7,8,9 */ - dword = entry[6].pin | - entry[7].pin << 8 | - entry[8].pin << 16| - entry[9].pin << 24; - pci_write_config32(dev, 0xF8, 0x7); - pci_write_config32(dev, 0xFC, dword); - - /* IOAPICCMISCIND:0x8, pin map of dev 10,11,12,13 */ - dword = entry[10].pin | - entry[11].pin << 8 | - entry[12].pin << 16| - entry[13].pin << 24; - pci_write_config32(dev, 0xF8, 0x8); - pci_write_config32(dev, 0xFC, dword); - - /* IOAPICCMISCIND:0x9, pin map of ht, iommu */ - dword = entry[0].pin | entry[1].pin << 8; - pci_write_config32(dev, 0xF8, 0x9); - pci_write_config32(dev, 0xFC, dword); - - pci_write_config32(dev, 0xF8, 0x1); - dword = pci_read_config32(dev, 0xFC) & 0xfffffff0; - /* TODO: On SR56x0/SP5100 board, the IOAPIC on SR56x0 is the - * 2nd one. We need to check if it also is on your board. */ - setup_ioapic((void *)dword, 1); -} - -static void pcie_init(struct device *dev) -{ - /* Enable pci error detecting */ - u32 dword; - - printk(BIOS_INFO, "pcie_init in sr5650_ht.c\n"); - - /* System error enable */ - dword = pci_read_config32(dev, 0x04); - dword |= (1 << 8); /* System error enable */ - dword |= (1 << 30); /* Clear possible errors */ - pci_write_config32(dev, 0x04, dword); - - /* - * 1 is APIC enable - * 18 is enable nb to accept A4 interrupt request from SB. - */ - dword = pci_read_config32(dev, 0x4C); - dword |= 1 << 1 | 1 << 18; /* Clear possible errors */ - pci_write_config32(dev, 0x4C, dword); - - sr5690_apic_init(dev); -} - -static void sr5690_read_resource(struct device *dev) -{ - if (CONFIG(EXT_CONF_SUPPORT)) { - printk(BIOS_DEBUG,"%s: %s\n", __func__, dev_path(dev)); - set_nbmisc_enable_bits(dev, 0x0, 1 << 3, 1 << 3); /* Hide BAR3 */ - } - - pci_dev_read_resources(dev); - - /* rpr6.2.(1). Write the Base Address Register (BAR) */ - pci_write_config32(dev, 0xf8, 0x1); /* Set IOAPIC's index to 1 and make sure no one changes it */ - pci_get_resource(dev, 0xfc); /* APIC located in sr5690 */ - - compact_resources(dev); -} - -/* If IOAPIC's index changes, we should replace the pci_dev_set_resource(). */ -static void sr5690_set_resources(struct device *dev) -{ - pci_write_config32(dev, 0xf8, 0x1); /* Set IOAPIC's index to 1 and make sure no one changes it */ - - if (CONFIG(EXT_CONF_SUPPORT)) { - uint32_t reg; - struct device *amd_ht_cfg_dev; - struct device *amd_addr_map_dev; - resource_t res_base; - resource_t res_end; - uint32_t base; - uint32_t limit; - struct resource *res; - - printk(BIOS_DEBUG,"%s %s\n", dev_path(dev), __func__); - - /* Find requisite AMD CPU devices */ - amd_ht_cfg_dev = pcidev_on_root(0x18, 0); - amd_addr_map_dev = pcidev_on_root(0x18, 1); - - if (!amd_ht_cfg_dev || !amd_addr_map_dev) { - printk(BIOS_WARNING, "%s: %s Unable to locate CPU control devices\n", __func__, dev_path(dev)); - } else { - res = sr5650_retrieve_cpu_mmio_resource(); - if (res) { - /* Set up MMCONFIG bus range */ - set_nbmisc_enable_bits(dev, 0x0, 1 << 3, 0 << 3); /* Make BAR3 visible */ - set_nbcfg_enable_bits(dev, 0x7c, 1 << 30, 1 << 30); /* Enables writes to the BAR3 register */ - set_nbcfg_enable_bits(dev, 0x84, 7 << 16, 0 << 16); /* Program bus range = 255 busses */ - pci_write_config32(dev, 0x1c, res->base); - - /* Enable MMCONFIG decoding. */ - set_htiu_enable_bits(dev, 0x32, 1 << 28, 1 << 28); /* PCIEMiscInit */ - set_nbcfg_enable_bits(dev, 0x7c, 1 << 30, 0 << 30); /* Disable writes to the BAR3 register */ - set_nbmisc_enable_bits(dev, 0x0, 1 << 3, 1 << 3); /* Hide BAR3 */ - - /* Set up nonposted resource in MMIO space */ - res_base = res->base; /* Get the base address */ - res_end = resource_end(res); /* Get the limit (rounded up) */ - printk(BIOS_DEBUG, "%s: %s[0x1c] base = %0llx limit = %0llx\n", __func__, dev_path(dev), res_base, res_end); - - /* Locate an unused MMIO resource */ - for (reg = 0xb8; reg >= 0x80; reg -= 8) { - base = pci_read_config32(amd_addr_map_dev, reg); - limit = pci_read_config32(amd_addr_map_dev, reg + 4); - if (!(base & 0x3)) - break; /* Unused resource found */ - } - - /* If an unused MMIO resource was available, set up the mapping */ - if (!(base & 0x3)) { - uint32_t sblk; - - /* Remember this resource has been stored. */ - res->flags |= IORESOURCE_STORED; - report_resource_stored(dev, res, " "); - - /* Get SBLink value (HyperTransport I/O Hub Link ID). */ - sblk = (pci_read_config32(amd_ht_cfg_dev, 0x64) >> 8) & 0x3; - - /* Calculate the MMIO mapping base */ - base &= 0x000000f0; - base |= ((res_base >> 8) & 0xffffff00); - base |= 3; - - /* Calculate the MMIO mapping limit */ - limit &= 0x00000048; - limit |= ((res_end >> 8) & 0xffffff00); - limit |= (sblk << 4); - limit |= (1 << 7); - - /* Configure and enable MMIO mapping */ - printk(BIOS_INFO, "%s: %s <- index %x base %04x limit %04x\n", __func__, dev_path(amd_addr_map_dev), reg, base, limit); - pci_write_config32(amd_addr_map_dev, reg + 4, limit); - pci_write_config32(amd_addr_map_dev, reg, base); - } - else { - printk(BIOS_WARNING, "%s: %s No free MMIO resources available\n", __func__, dev_path(dev)); - } - } else { - printk(BIOS_WARNING, "%s: %s Unable to locate CPU MMCONF resource\n", __func__, dev_path(dev)); - } - } - } - - pci_dev_set_resources(dev); -} - -static struct pci_operations lops_pci = { - .set_subsystem = pci_dev_set_subsystem, -}; - -static struct device_operations ht_ops = { - .read_resources = sr5690_read_resource, - .set_resources = sr5690_set_resources, - .enable_resources = pci_dev_enable_resources, - .init = pcie_init, - .scan_bus = 0, - .ops_pci = &lops_pci, -}; - -static const struct pci_driver ht_driver_sr5690 __pci_driver = { - .ops = &ht_ops, - .vendor = PCI_VENDOR_ID_ATI, - .device = PCI_DEVICE_ID_AMD_SR5690_HT, -}; - -static const struct pci_driver ht_driver_sr5670 __pci_driver = { - .ops = &ht_ops, - .vendor = PCI_VENDOR_ID_ATI, - .device = PCI_DEVICE_ID_AMD_SR5670_HT, -}; - -static const struct pci_driver ht_driver_sr5650 __pci_driver = { - .ops = &ht_ops, - .vendor = PCI_VENDOR_ID_ATI, - .device = PCI_DEVICE_ID_AMD_SR5650_HT, -}; diff --git a/src/southbridge/amd/sr5650/pcie.c b/src/southbridge/amd/sr5650/pcie.c deleted file mode 100644 index 5c3aee7995..0000000000 --- a/src/southbridge/amd/sr5650/pcie.c +++ /dev/null @@ -1,940 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2010 Advanced Micro Devices, Inc. - * Copyright (C) 2015 Timothy Pearson , Raptor Engineering - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include -#include -#include -#include "sr5650.h" -#include "cmn.h" - -/*------------------------------------------------ -* Global variable -------------------------------------------------*/ -PCIE_CFG AtiPcieCfg = { - PCIE_ENABLE_STATIC_DEV_REMAP, /* Config */ - 0, /* ResetReleaseDelay */ - 0, /* Gfx0Width */ - 0, /* Gfx1Width */ - 0, /* GfxPayload */ - 0, /* GppPayload */ - 0, /* PortDetect, filled by GppSbInit */ - 0, /* PortHp */ - 0, /* DbgConfig */ - 0, /* DbgConfig2 */ - 0, /* GfxLx */ - 0, /* GppLx */ - 0, /* NBSBLx */ - 0, /* PortSlotInit */ - 0, /* Gfx0Pwr */ - 0, /* Gfx1Pwr */ - 0 /* GppPwr */ -}; - -static void ValidatePortEn(struct device *nb_dev); - -static void ValidatePortEn(struct device *nb_dev) -{ -} - -/***************************************************************** -* Compliant with CIM_33's PCIEPowerOffGppPorts -* Power off unused GPP lines -*****************************************************************/ -static void PciePowerOffGppPorts(struct device *nb_dev, struct device *dev, u32 port) -{ - printk(BIOS_DEBUG, "PciePowerOffGppPorts() port %d\n", port); - u32 reg; - u32 state_save; - uint8_t i; - struct southbridge_amd_sr5650_config *cfg = - (struct southbridge_amd_sr5650_config *)nb_dev->chip_info; - u32 state = cfg->port_enable; - - if (!(AtiPcieCfg.Config & PCIE_DISABLE_HIDE_UNUSED_PORTS)) - state &= AtiPcieCfg.PortDetect; - state = ~state; - state &= (1 << 4) + (1 << 5) + (1 << 6) + (1 << 7); - state_save = state << 17; - /* Disable ports any that failed training */ - for (i = 9; i <= 13; i++) { - if (!(AtiPcieCfg.PortDetect & 1 << i)) { - if ((port >= 9) && (port <= 13)) { - state |= (1 << (port + 7)); - } - if (port == 9) - state_save |= 1 << 25; - if (port == 10) - state_save |= 1 << 26; - if (port == 11) - state_save |= 1 << 6; - if (port == 12) - state_save |= 1 << 7; - - if (port == 13) { - reg = nbmisc_read_index(nb_dev, 0x2a); - reg |= 1 << 4; - nbmisc_write_index(nb_dev, 0x2a, reg); - } - } - } - state &= !(AtiPcieCfg.PortHp); - reg = nbmisc_read_index(nb_dev, 0x0c); - reg |= state; - nbmisc_write_index(nb_dev, 0x0c, reg); - - reg = nbmisc_read_index(nb_dev, 0x08); - reg |= state_save; - nbmisc_write_index(nb_dev, 0x08, reg); - - if ((AtiPcieCfg.Config & PCIE_OFF_UNUSED_GPP_LANES) - && !(AtiPcieCfg. - Config & (PCIE_DISABLE_HIDE_UNUSED_PORTS + - PCIE_GFX_COMPLIANCE))) { - } - /* step 3 Power Down Control for Southbridge */ - reg = nbpcie_p_read_index(dev, 0xa2); - - switch ((reg >> 4) & 0x7) { /* get bit 4-6, LC_LINK_WIDTH_RD */ - case 1: - nbpcie_ind_write_index(nb_dev, 0x65, 0x0e0e); - break; - case 2: - nbpcie_ind_write_index(nb_dev, 0x65, 0x0c0c); - break; - default: - break; - } -} - -/********************************************************************** -**********************************************************************/ -static void switching_gpp1_configurations(struct device *nb_dev, struct device *sb_dev) -{ - u32 reg; - struct southbridge_amd_sr5650_config *cfg = - (struct southbridge_amd_sr5650_config *)nb_dev->chip_info; - - /* 4.3.3.1.1.1.step1. Asserts PCIE-GPP1 global reset */ - reg = nbmisc_read_index(nb_dev, 0x8); - reg |= 1 << 15; - nbmisc_write_index(nb_dev, 0x8, reg); - - /* 4.3.3.1.1.1.step2. De-asserts STRAP_BIF_all_valid for PCIE-GPP1 core */ - reg = nbmisc_read_index(nb_dev, 0x26); - reg |= 1 << 28; - nbmisc_write_index(nb_dev, 0x26, reg); - - /* 4.3.3.1.1.1.step3. Programs PCIE-GPP1 to be desired port configuration 8:8 or 16:0. */ - reg = nbmisc_read_index(nb_dev, 0x8); - reg &= ~(1 << 8); /* clean */ - reg |= cfg->gpp1_configuration << 8; - nbmisc_write_index(nb_dev, 0x8, reg); - - /* 4.3.3.1.1.1.step4. Wait for 2ms */ - mdelay(1); - - /* 4.3.3.1.1.1.step5. Asserts STRAP_BIF_all_valid for PCIE-GPP1 core */ - reg = nbmisc_read_index(nb_dev, 0x26); - reg &= ~(1 << 28); - nbmisc_write_index(nb_dev, 0x26, reg); - - /* 4.3.3.1.1.1.step6. De-asserts PCIE-GPP1 global reset */ - reg = nbmisc_read_index(nb_dev, 0x8); - reg &= ~(1 << 15); - nbmisc_write_index(nb_dev, 0x8, reg); - - /* Follow the procedure for PCIE-GPP1 common initialization and - * link training sequence. */ -} - -/********************************************************************** -**********************************************************************/ -static void switching_gpp2_configurations(struct device *nb_dev, struct device *sb_dev) -{ - u32 reg; - struct southbridge_amd_sr5650_config *cfg = - (struct southbridge_amd_sr5650_config *)nb_dev->chip_info; - - /* 4.3.3.1.1.2.step1. Asserts PCIE-GPP2 global reset */ - reg = nbmisc_read_index(nb_dev, 0x8); - reg |= 1 << 13; - nbmisc_write_index(nb_dev, 0x8, reg); - - /* 4.3.3.1.1.2.step2. De-asserts STRAP_BIF_all_valid for PCIE-GPP2 core */ - reg = nbmisc_read_index(nb_dev, 0x26); - reg |= 1 << 29; - nbmisc_write_index(nb_dev, 0x26, reg); - - /* 4.3.3.1.1.2.step3. Programs PCIE-GPP2 to be desired port configuration 8:8 or 16:0. */ - reg = nbmisc_read_index(nb_dev, 0x8); - reg &= ~(1 << 9); /* clean */ - reg |= (cfg->gpp2_configuration & 1) << 9; - nbmisc_write_index(nb_dev, 0x8, reg); - - /* 4.3.3.1.1.2.step4. Wait for 2ms */ - mdelay(2); - - /* 4.3.3.1.1.2.step5. Asserts STRAP_BIF_all_valid for PCIE-GPP2 core */ - reg = nbmisc_read_index(nb_dev, 0x26); - reg &= ~(1 << 29); - nbmisc_write_index(nb_dev, 0x26, reg); - - /* 4.3.3.1.1.2.step6. De-asserts PCIE-GPP2 global reset */ - reg = nbmisc_read_index(nb_dev, 0x8); - reg &= ~(1 << 13); - nbmisc_write_index(nb_dev, 0x8, reg); - - /* Follow the procedure for PCIE-GPP2 common initialization and - * link training sequence. */ -} -static void switching_gpp3a_configurations(struct device *nb_dev, struct device *sb_dev) -{ - u32 reg; - struct southbridge_amd_sr5650_config *cfg = - (struct southbridge_amd_sr5650_config *)nb_dev->chip_info; - - /* 4.3.3.2.3.2.step1. Asserts PCIE-GPP3a global reset. */ - reg = nbmisc_read_index(nb_dev, 0x8); - reg |= 1 << 31; - nbmisc_write_index(nb_dev, 0x8, reg); - /* 4.3.3.2.3.2.step2. De-asserts STRAP_BIF_all_valid for PCIE-GPP3a core */ - reg = nbmisc_read_index(nb_dev, 0x26); - reg |= 1 << 30; - nbmisc_write_index(nb_dev, 0x26, reg); - /* 4.3.3.2.3.2.step3. Programs the desired PCIE-GPP3a configuration. */ - reg = nbmisc_read_index(nb_dev, 0x67); - reg &= ~0x1F; /* clean */ - reg |= cfg->gpp3a_configuration; - nbmisc_write_index(nb_dev, 0x67, reg); - /* 4.3.3.2.3.2.step4. Programs PCIE-GPP3a Line Director. */ - reg = nbmisc_read_index(nb_dev, 0x26); - reg &= 0xF0000000; /* TODO:Lane reversed. */ - switch (cfg->gpp3a_configuration) { - case 0xB: /* 1:1:1:1:1:1 */ - reg |= 0x2AA3554; - break; - case 0x1: /* 4:2:0:0:0:0 */ - reg |= 0x055B000; - break; - case 0x2: /* 4:1:1:0:0:0 */ - reg |= 0x215B400; - break; - case 0xC: /* 2:2:2:0:0:0 */ - reg |= 0xFF0BAA0; - break; - case 0xA: /* 2:2:1:1:0:0 */ - reg |= 0x215B400; - break; - case 0x4: /* 2:1:1:1:1:0 */ - reg |= 0xFF0BAA0; - break; - default: /* shouldn't be here. */ - printk(BIOS_DEBUG, "Warning:gpp3a_configuration is not correct. Check your devicetree.cb\n"); - break; - } - nbmisc_write_index(nb_dev, 0x26, reg); - /* 4.3.3.2.3.2.step5. De-asserts STRAP_BIF_all_valid for PCIE-GPP3a core */ - reg = nbmisc_read_index(nb_dev, 0x26); - reg &= ~(1 << 30); - nbmisc_write_index(nb_dev, 0x26, reg); - /* 4.3.3.2.3.2.step6. De-asserts PCIE-GPP3a global reset. */ - reg = nbmisc_read_index(nb_dev, 0x8); - reg &= ~(1 << 31); - nbmisc_write_index(nb_dev, 0x8, reg); -} - -/***************************************************************** -* The sr5650 uses NBCONFIG:0x1c (BAR3) to map the PCIE Extended Configuration -* Space to a 256MB range within the first 4GB of addressable memory. -*****************************************************************/ -void enable_pcie_bar3(struct device *nb_dev) -{ - printk(BIOS_DEBUG, "%s\n", __func__); - set_nbcfg_enable_bits(nb_dev, 0x7C, 1 << 30, 1 << 30); /* Enables writes to the BAR3 register. */ - set_nbcfg_enable_bits(nb_dev, 0x84, 7 << 16, 0 << 16); - - pci_write_config32(nb_dev, 0x1C, EXT_CONF_BASE_ADDRESS); /* PCIEMiscInit */ - pci_write_config32(nb_dev, 0x20, 0x00000000); - set_htiu_enable_bits(nb_dev, 0x32, 1 << 28, 1 << 28); /* PCIEMiscInit */ - ProgK8TempMmioBase(1, EXT_CONF_BASE_ADDRESS, TEMP_MMIO_BASE_ADDRESS); -} - -/***************************************************************** -* We should disable bar3 when we want to exit sr5650_enable, because bar3 will be -* remapped in set_resource later. -*****************************************************************/ -void disable_pcie_bar3(struct device *nb_dev) -{ - printk(BIOS_DEBUG, "%s\n", __func__); - pci_write_config32(nb_dev, 0x1C, 0); /* clear BAR3 address */ - set_nbcfg_enable_bits(nb_dev, 0x7C, 1 << 30, 0 << 30); /* Disable writes to the BAR3. */ - ProgK8TempMmioBase(0, EXT_CONF_BASE_ADDRESS, TEMP_MMIO_BASE_ADDRESS); -} - -/* - * GEN2 Software Compliance - */ -void init_gen2(struct device *nb_dev, struct device *dev, u8 port) -{ - u32 reg, val; - - /* for A11 (0x89 == 0) */ - reg = 0x34; - if (port <= 3) { - val = 1<<5; - } else { - val = 1<<31; - if (port >= 9) - reg = 0x39; - } - - /* TODO: check for rev > a11 */ - switch (port) { - case 2: - reg = 0x34; - val = 1<<5; - break; - case 3: - reg = 0x22; - val = 1<<6; - break; - case 4: - reg = 0x34; - val = 1<<31; - break; - case 5: - case 6: - reg = 0x39; - val = 1<<31; - break; - case 7: - case 8: - case 9: - reg = 0x37; - val = 1<chip_info; - - dev_index = dev->path.pci.devfn >> 3; - - if (dev_index < 4) - return; - - dev_index -= 4; - - switch (cfg->gpp3a_configuration) { - case 0x1: /* 4:2:0:0:0:0 */ - if (dev_index >= ARRAY_SIZE(pGpp420000)) - return; - value = pGpp420000[dev_index]; - break; - case 0x2: /* 4:1:1:0:0:0 */ - if (dev_index >= ARRAY_SIZE(pGpp411000)) - return; - value = pGpp411000[dev_index]; - break; - case 0xC: /* 2:2:2:0:0:0 */ - if (dev_index >= ARRAY_SIZE(pGpp222000)) - return; - value = pGpp222000[dev_index]; - break; - case 0xA: /* 2:2:1:1:0:0 */ - if (dev_index >= ARRAY_SIZE(pGpp221100)) - return; - value = pGpp221100[dev_index]; - break; - case 0x4: /* 2:1:1:1:1:0 */ - if (dev_index >= ARRAY_SIZE(pGpp211110)) - return; - value = pGpp211110[dev_index]; - break; - case 0xB: /* 1:1:1:1:1:1 */ - if (dev_index >= ARRAY_SIZE(pGpp111111)) - return; - value = pGpp111111[dev_index]; - break; - default: /* shouldn't be here. */ - printk(BIOS_WARNING, "buggy gpp3a_configuration\n"); - return; - } - - if (value != 0) { - set_pcie_enable_bits(dev, 0x10, 0x3f << 8, value << 8); - set_pcie_enable_bits(dev, 0x20, 1 << 11, 1 << 11); - } -} - -/* - * Enabling Dynamic Slave CPL Buffer Allocation Feature for PCIE-GPP1/PCIE-GPP2 Ports - * PcieLibCplBufferAllocation - */ -static void gpp12_cpl_buf_alloc(struct device *nb_dev, struct device *dev) -{ - u8 gpp_cfg; - u8 value; - u8 dev_index; - - dev_index = dev->path.pci.devfn >> 3; - struct southbridge_amd_sr5650_config *cfg = - (struct southbridge_amd_sr5650_config *)nb_dev->chip_info; - - if (dev_index < 4) { - gpp_cfg = cfg->gpp1_configuration; - } else if (dev_index > 0xa) { - gpp_cfg = cfg->gpp2_configuration; - } else { - return; - } - - if (gpp_cfg == 0) { - /* Configuration 16:0, leave the default value */ - } else if (gpp_cfg == 1) { - /* Configuration 8:8 */ - value = 0x60; - set_pcie_enable_bits(dev, 0x10, 0x3f << 8, value << 8); - set_pcie_enable_bits(dev, 0x20, 1 << 11, 1 << 11); - } else { - printk(BIOS_DEBUG, "buggy gpp configuration\n"); - } -} - -#if 1 /* BTS report error without this function. But some board - * fail to boot. Leave it here for future debug. */ - -/* - * Enable LCLK clock gating - */ -static void EnableLclkGating(struct device *dev) -{ - u8 port; - u32 reg = 0; - u32 mask = 0; - u32 value = 0; - struct device *nb_dev = pcidev_on_root(0x0, 0); - struct device *clk_f1 = pcidev_on_root(0x0, 1); - - reg = 0xE8; - port = dev->path.pci.devfn >> 3; - switch (port) { - //PCIE_CORE_INDEX_GPP1 - case 2: - case 3: - reg = 0x94; - mask = 1 << 16; - break; - - //PCIE_CORE_INDEX_GPP2 - case 11: - case 12: - value = 1 << 28; - break; - - //PCIE_CORE_INDEX_GPP3a - case 4 ... 7: - case 9: - case 10: - value = 1 << 31; - break; - - //PCIE_CORE_INDEX_GPP3b; - case 13: - value = 1 << 25; - break; - - //PCIE_CORE_INDEX_SB; - case 8: - reg = 0x94; - mask = 1 << 24; - break; - default: - break; - } - /* enable access func1 */ - set_nbcfg_enable_bits(nb_dev, 0x4C, 1 << 0, 1 << 0); - set_nbcfg_enable_bits(clk_f1, reg, mask, value); -} -#endif - -/***************************************** -* Compliant with CIM_33's PCIEGPPInit -* nb_dev: -* root bridge struct -* dev: -* p2p bridge struct -* port: -* p2p bridge number, 4-10 -*****************************************/ -void sr5650_gpp_sb_init(struct device *nb_dev, struct device *dev, u32 port) -{ - uint8_t training_ok = 1; - - u32 gpp_sb_sel = 0; - struct southbridge_amd_sr5650_config *cfg = - (struct southbridge_amd_sr5650_config *)nb_dev->chip_info; - - printk(BIOS_DEBUG, "%s: nb_dev=0x%p, dev=0x%p, port=0x%x\n", __func__, nb_dev, dev, port); - switch (port) { - case 2: - case 3: - gpp_sb_sel = PCIE_CORE_INDEX_GPP1; - break; - case 4 ... 7: - case 9: - case 10: - gpp_sb_sel = PCIE_CORE_INDEX_GPP3a; - break; - case 8: - gpp_sb_sel = PCIE_CORE_INDEX_SB; - break; - case 11: - case 12: - gpp_sb_sel = PCIE_CORE_INDEX_GPP2; - break; - case 13: - gpp_sb_sel = PCIE_CORE_INDEX_GPP3b; - break; - } - - /* Init common Core registers */ - set_pcie_enable_bits(dev, 0xB1, 1 << 28 | 1 << 23 | 1 << 20 | 1 << 19, - 1 << 28 | 1 << 23 | 1 << 20 | 1 << 19); - if (gpp_sb_sel == PCIE_CORE_INDEX_GPP3a) { - set_pcie_enable_bits(dev, 0xB1, 1 << 22, 1 << 22); - /* 4.3.3.2.3 Step 10: Dynamic Slave CPL Buffer Allocation */ - gpp3a_cpl_buf_alloc(nb_dev, dev); - } - if (gpp_sb_sel == PCIE_CORE_INDEX_GPP1 || gpp_sb_sel == PCIE_CORE_INDEX_GPP2) { - gpp12_cpl_buf_alloc(nb_dev, dev); - } - set_pcie_enable_bits(dev, 0xA1, (1 << 26) | (1 << 24) | (1 << 11), 1 << 11); - set_pcie_enable_bits(dev, 0xA0, 0x0000FFF0, 0x6830); - // PCIE should not ignore malformed packet error or ATS request - set_pcie_enable_bits(dev, 0x70, 1 << 12, 0); - //Step 14.1: Advertising Hot Plug Capabilities - set_pcie_enable_bits(dev, 0x10, 1 << 4, 1 << 4); //Enable power fault - - set_pcie_enable_bits(nb_dev, 0xC1 | gpp_sb_sel, 1 << 0, 1 << 0); - - /* init GPP core */ - /* 4.4.2.step13.1. Sets RCB completion timeout to be 200ms */ - pci_ext_write_config32(nb_dev, dev, 0x80, 0xF << 0, 0x6 << 0); - /* 4.4.2.step13.2. RCB completion timeout on link down to shorten enumeration time. */ - set_pcie_enable_bits(dev, 0x70, 1 << 19, 1 << 19); - /* 4.4.2.step13.3. Enable slave ordering rules */ - set_pcie_enable_bits(nb_dev, 0x20 | gpp_sb_sel, 1 << 8, 0 << 8); - /* 4.4.2.step13.4. Sets DMA payload size to 64 bytes. */ - set_pcie_enable_bits(nb_dev, 0x10 | gpp_sb_sel, 7 << 10, 4 << 10); - /* 4.4.2.step13.5. Set REGS_DLP_IGNORE_IN_L1_EN to ignore DLLPs - during L1 so that Tx Clk can be turned off. */ - set_pcie_enable_bits(nb_dev, 0x02 | gpp_sb_sel, 1 << 0 | 1 << 8, 1 << 0 | 1 << 8); // add bit 8 from CIMx - /* 4.4.2.step13.6. Set REGS_LC_ALLOW_TX_L1_CONTROL to allow TX to - prevent LC from going to L1 when there are outstanding completions.*/ - set_pcie_enable_bits(dev, 0x02, 1 << 15, 1 << 15); - - /* Enables the PLL power down when all lanes are inactive. - * It should be on in GPP. - */ - if (gpp_sb_sel == PCIE_CORE_INDEX_GPP3a || gpp_sb_sel == PCIE_CORE_INDEX_GPP3b || gpp_sb_sel == PCIE_CORE_INDEX_SB) { - set_pcie_enable_bits(nb_dev, 0x02 | gpp_sb_sel, 1 << 3, 1 << 3); - } - - /* 4.4.2.step13.7. Set REGS_LC_DONT_GO_TO_L0S_IF_L1_ARMED to prevent - lc to go to from L0 to Rcv_L0s if L1 is armed. */ - set_pcie_enable_bits(dev, 0xA1, 1 << 11, 1 << 11); - /* 4.4.2.step13.8. CMGOOD_OVERRIDE for all five PCIe cores. */ - set_nbmisc_enable_bits(nb_dev, 0x22, 1 << 27, 1 << 27); - /* 4.4.2.step13.9. Prevents Electrical Idle from causing a - transition from Rcv_L0 to Rcv_L0s. */ - set_pcie_enable_bits(dev, 0xB1, 1 << 20, 1 << 20); - /* 4.4.2.step13.10. Prevents the LTSSM from going to Rcv_L0s if - it has already acknowledged a request to go - to L1 but it has not transitioned there yet. */ - /* seems the same as step13.7 */ - set_pcie_enable_bits(dev, 0xA1, 1 << 11, 1 << 11); - /* 4.4.2.step13.11. Transmits FTS before Recovery. */ - set_pcie_enable_bits(dev, 0xA3, 1 << 9, 1 << 9); - /* 4.4.2.step13.12. Sets TX arbitration algorithm to round robin - for PCIE-GPP1, PCIE-GPP2, PCIE-GPP3a and PCIE-GPP3b cores only. */ - //if (gpp_sb_sel != PCIE_CORE_INDEX_SB) /* RPR NOT set SB_CORE, BTS set SB_CORE, we comply with BTS */ - set_pcie_enable_bits(nb_dev, 0x1C | gpp_sb_sel, 0x7FF, 0x109); - /* 4.4.2.step13.13. Sets number of TX Clocks to drain TX Pipe to 0x3.*/ - set_pcie_enable_bits(dev, 0xA0, 0xF << 4, 0x3 << 4); - /* 4.4.2.step13.14. Lets PI use Electrical Idle from PHY when - turning off PLL in L1 at Gen 2 speed instead of Inferred Electrical - Idle. - NOTE: LC still uses Inferred Electrical Idle. */ - set_pcie_enable_bits(nb_dev, 0x40 | gpp_sb_sel, 3 << 14, 2 << 14); - /* 4.4.2.step13.15. Turn on rx_fronten_en for all active lanes upon - exit from Electrical Idle, rather than being tied to PLL_PDNB. */ - set_pcie_enable_bits(nb_dev, 0xC2 | gpp_sb_sel, 1 << 25, 1 << 25); - - /* 4.4.2.step13.16. Advertises TX L0s and L1 exit latency. - TX L0s exit latency to be 100b: 512ns to less than 1us; - L1 exit latency to be 011b: 4us to less than 8us. - For Hot-Plug Slots: Advertise TX L0s and L1 exit latency. - TX L0s exit latency to be 110b: 2us to 4us. - L1 exit latency to be 111b: more than 64us.*/ - //set_pcie_enable_bits(dev, 0xC1, 0xF << 0, 0xC << 0); /* 0xF for hotplug. */ - set_pcie_enable_bits(dev, 0xC1, 0xF << 0, 0xF << 0); /* 0xF for hotplug. */ - /* 4.4.2.step13.17. Always ACK an ASPM L1 entry DLLP to - workaround credit control issue on PM_NAK - message of SB700 and SB800. */ - /* 4.4.4.step13.18. To allow advertising Gen 2 capabilities to Southbridge. */ - if (port == 8) { - set_pcie_enable_bits(dev, 0xA0, 1 << 23, 1 << 23); - set_pcie_enable_bits(nb_dev, 0xC1 | gpp_sb_sel, 1 << 1, 1 << 1); - } - /* 4.4.2.step13.19. CMOS Option (Gen 2 AUTO-Part 1 - Enabled by Default) */ - /* 4.4.2.step13.20. CMOS Option (RC Advertised Gen 2-Part1 - Disabled by Default)*/ - set_nbcfg_enable_bits(dev, 0x88, 0xF << 0, 0x2 << 0); - /* Disables GEN2 capability of the device. - * RPR typo- it says enable but the bit setting says disable. - * Disable it here and we enable it later. */ - set_pcie_enable_bits(dev, 0xA4, 1 << 0, 1 << 0); - - /* 4.4.2.step13.21. Legacy Hot Plug -CMOS Option */ - /* NOTE: This feature can be enabled only for Hot-Plug slots implemented on SR5690 platform. */ - - /* 4.4.2.step13.22. Native PCIe Mode -CMOS Option */ - /* Enable native PME. */ - set_pcie_enable_bits(dev, 0x10, 1 << 3, 1 < 3); - /* This bit when set indicates that the PCIe Link associated with this port - is connected to a slot. */ - pci_ext_write_config32(nb_dev, dev, 0x5a, 1 << 8, 1 << 8); - /* This bit when set indicates that this slot is capable of supporting - Hot-Plug operations. */ - set_nbcfg_enable_bits(dev, 0x6C, 1 << 6, 1 << 6); - /* Enables flushing of TLPs when Data Link is down. */ - set_pcie_enable_bits(dev, 0x20, 1 << 19, 0 << 19); - - /* 4.4.2.step14. Server Class Hot Plug Feature. NOTE: This feature is not supported on SR5670 and SR5650 */ - /* 4.4.2 step14.1: Advertising Hot Plug Capabilities */ - /* 4.4.2.step14.2: Firmware Upload */ - /* 4.4.2.Step14.3: SBIOS Acknowledgment to Firmware of Successful Firmware Upload */ - /* step14.4 */ - /* step14.5 */ - /* skip */ - - /* CIMx LPC Deadlock workaround - Enable Memory Write Map*/ - if (gpp_sb_sel == PCIE_CORE_INDEX_SB) { - set_pcie_enable_bits(nb_dev, 0x10 | gpp_sb_sel, 1 << 9, 1 << 9); - set_htiu_enable_bits(nb_dev, 0x06, 1 << 26, 1 << 26); - } - - /* This CPL setup requires more than this one register and should be done in gpp_core. - * The additional setup is for the different revisions. */ - - /* CIMx CommonPortInit settings that are not set above. */ - pci_ext_write_config32(nb_dev, dev, 0x88, 0xF0, 1 << 0); /* LINK_CRTL2 */ - - if (port == 8) - set_pcie_enable_bits(dev, 0xA0, 0, 1 << 23); - -#if 0 //SR56x0 pcie Gen2 code is not tested yet, we should enable it again when test finished. - /* set automatic Gen2 support, needs mainboard config option as Gen2 can cause issues on some platforms. */ - init_gen2(nb_dev, dev, port); - set_pcie_enable_bits(dev, 0xA4, 1 << 29, 1 << 29); - set_pcie_enable_bits(dev, 0xC0, 1 << 15, 0); - set_pcie_enable_bits(dev, 0xA2, 1 << 13, 0); -#endif - - /* Hotplug Support - bit5 + bit6 capable and surprise */ - pci_ext_write_config32(nb_dev, dev, 0x6c, 0x60, 0x60); - - /* Set interrupt pin info 0x3d */ - pci_ext_write_config32(nb_dev, dev, 0x3c, 1 << 8, 1 << 8); - - /* 5.12.9.3 Hotplug step 1 - NB_PCIE_ROOT_CTRL - enable pm irq - The RPR is wrong - this is not a PCIEND_P register */ - pci_ext_write_config32(nb_dev, dev, 0x74, 1 << 3, 1 << 3); - - /* 5.12.9.3 step 2 - PCIEP_PORT_CNTL - enable hotplug messages */ - if (port != 8) - set_pcie_enable_bits(dev, 0x10, 1 << 2, 1 << 2); - - /* Not sure about this PME setup */ - /* Native PME */ - set_pcie_enable_bits(dev, 0x10, 1 << 3, 1 << 3); /* Not set in CIMx */ - - /* PME Enable */ - pci_ext_write_config32(nb_dev, dev, 0x54, 1 << 8, 1 << 8); /* Not in CIMx */ - - /* 4.4.3 Training for GPP devices */ - /* init GPP */ - switch (port) { - case 2: - case 3: - case 4: /* GPP_SB */ - case 5: - case 6: - case 7: - case 9: /*GPP*/ - case 10: - case 11: - case 12: - case 13: - /* 4.4.2.step13.5. Blocks DMA traffic during C3 state */ - set_pcie_enable_bits(dev, 0x10, 1 << 0, 0 << 0); - /* Enables TLP flushing */ - set_pcie_enable_bits(dev, 0x20, 1 << 19, 0 << 19); - - /* check port enable */ - if (cfg->port_enable & (1 << port)) { - uint32_t hw_port = port; - switch (cfg->gpp3a_configuration) { - case 0x1: /* 4:2:0:0:0:0 */ - if (hw_port == 9) - hw_port = 4 + 1; - break; - case 0x2: /* 4:1:1:0:0:0 */ - if (hw_port == 9) - hw_port = 4 + 1; - else if (hw_port == 10) - hw_port = 4 + 2; - break; - case 0xc: /* 2:2:2:0:0:0 */ - if (hw_port == 6) - hw_port = 4 + 1; - else if (hw_port == 9) - hw_port = 4 + 2; - break; - case 0xa: /* 2:2:1:1:0:0 */ - if (hw_port == 6) - hw_port = 4 + 1; - else if (hw_port == 9) - hw_port = 4 + 2; - else if (hw_port == 10) - hw_port = 4 + 3; - break; - case 0x4: /* 2:1:1:1:1:0 */ - if (hw_port == 6) - hw_port = 4 + 1; - else if (hw_port == 7) - hw_port = 4 + 2; - else if (hw_port == 9) - hw_port = 4 + 3; - else if (hw_port == 10) - hw_port = 4 + 4; - break; - case 0xb: /* 1:1:1:1:1:1 */ - break; - default: /* shouldn't be here. */ - printk(BIOS_WARNING, "invalid gpp3a_configuration\n"); - return; - } - PcieReleasePortTraining(nb_dev, dev, hw_port); - if (!(AtiPcieCfg.Config & PCIE_GPP_COMPLIANCE)) { - u8 res = PcieTrainPort(nb_dev, dev, hw_port); - printk(BIOS_DEBUG, "%s: port=0x%x hw_port=0x%x result=%d\n", - __func__, port, hw_port, res); - if (res) { - AtiPcieCfg.PortDetect |= 1 << port; - } else { - /* Even though nothing is attached to this port - * the port needs to be "enabled" to obtain - * a bus number from the PCI resource allocator - */ - training_ok = 0; - dev->enabled = 1; - } - } - } - break; - case 8: /* SB */ - break; - default: - break; - } - - /* Re-enable RC ordering logic after training (from CIMx)*/ - set_pcie_enable_bits(nb_dev, 0x20 | gpp_sb_sel, 1 << 9, 0); - - /* Advertising Hot Plug Capabilities */ - pci_ext_write_config32(nb_dev, dev, 0x6c, 0x04001B, 0x00001B); - - /* PCIE Late Init (CIMx late init - Maybe move somewhere else? Later in the coreboot PCI device enum?) */ - /* Set Slot Number */ - pci_ext_write_config32(nb_dev, dev, 0x6c, 0x1FFF << 19, port << 19); - - /* Set Slot present 0x5A*/ - pci_ext_write_config32(nb_dev, dev, 0x58, 1 << 24, 1 << 24); - - //PCIE-GPP1 TXCLK Clock Gating In L1 Late Core setting - Maybe move somewhere else? */ - set_pcie_enable_bits(nb_dev, 0x11 | gpp_sb_sel, 0xF << 0, 0x0C << 0); - /* Enable powering down PLLs in L1 or L23 Ready states. - * Turns off PHY`s RX FRONTEND during L1 when PLL power down is enabled */ - set_pcie_enable_bits(nb_dev, 0x40 | gpp_sb_sel, 0x1219, 0x1009); - /* 4.4..7.1 TXCLK Gating in L1, Enables powering down TXCLK clock pads on the receive side. */ - set_pcie_enable_bits(nb_dev, 0x40 | gpp_sb_sel, 1 << 6, 1 << 6); - - /* Step 20: Disables immediate RCB timeout on link down */ - if (!((pci_read_config32(dev, 0x6C) >> 6) & 0x01)) { - set_pcie_enable_bits(dev, 0x70, 1 << 19, 0 << 19); - } - - /* Step 27: LCLK Gating */ - EnableLclkGating(dev); - - /* Set Common Clock */ - /* If dev present, set PcieCapPtr+0x10, BIT6); - * set dev 0x68,bit 6 - * retrain link, set dev, 0x68 bit 5; - * wait dev 0x6B bit3 clear - */ - - if ((port == 8) || (!training_ok)) { - PciePowerOffGppPorts(nb_dev, dev, port); /* This is run for all ports that are not hotplug and don't detect devices */ - } -} - -/** - * Step 21: Register Locking - * Lock HWInit Register of each pcie core - */ -static void lock_hwinitreg(struct device *nb_dev) -{ - /* Step 21: Register Locking, Lock HWInit Register */ - set_pcie_enable_bits(nb_dev, 0x10 | PCIE_CORE_INDEX_GPP1, 1 << 0, 1 << 0); - set_pcie_enable_bits(nb_dev, 0x10 | PCIE_CORE_INDEX_SB, 1 << 0, 1 << 0); - set_pcie_enable_bits(nb_dev, 0x10 | PCIE_CORE_INDEX_GPP2, 1 << 0, 1 << 0); - set_pcie_enable_bits(nb_dev, 0x10 | PCIE_CORE_INDEX_GPP3a, 1 << 0, 1 << 0); - set_pcie_enable_bits(nb_dev, 0x10 | PCIE_CORE_INDEX_GPP3b, 1 << 0, 1 << 0); -} - -/** - * Lock HWInit Register - */ -void sr56x0_lock_hwinitreg(void) -{ - struct device *nb_dev = pcidev_on_root(0, 0); - - /* Lock HWInit Register */ - lock_hwinitreg(nb_dev); - - /* Lock HWInit Register NBMISCIND:0x0 NBCNTL[7] HWINIT_WR_LOCK */ - set_nbmisc_enable_bits(nb_dev, 0x00, 1 << 7, 1 << 7); - - /* Hide clock configuration PCI device HIDE_CLKCFG_HEADER */ - set_nbmisc_enable_bits(nb_dev, 0x00, 0x00000100, 1 << 8); -} - -/***************************************** -* Compliant with CIM_33's PCIEConfigureGPPCore -*****************************************/ -void config_gpp_core(struct device *nb_dev, struct device *sb_dev) -{ - u32 reg; - - reg = nbmisc_read_index(nb_dev, 0x20); - if (AtiPcieCfg.Config & PCIE_ENABLE_STATIC_DEV_REMAP) - reg &= 0xfffffffd; /* set bit1 = 0 */ - else - reg |= 0x2; /* set bit1 = 1 */ - nbmisc_write_index(nb_dev, 0x20, reg); - - /* Must perform PCIE-GPP1, GPP2, GPP3a global reset anyway */ - reg = nbmisc_read_index(nb_dev, 0x8); - reg |= (1 << 31) | (1 << 15) | (1 << 13); //asserts - nbmisc_write_index(nb_dev, 0x8, reg); - reg &= ~((1 << 31) | (1 << 15) | (1 << 13)); //De-asserts - nbmisc_write_index(nb_dev, 0x8, reg); - - switching_gpp3a_configurations(nb_dev, sb_dev); - switching_gpp1_configurations(nb_dev, sb_dev); - switching_gpp2_configurations(nb_dev, sb_dev); - ValidatePortEn(nb_dev); -} - -/***************************************** -* Compliant with CIM_33's PCIEMiscClkProg -*****************************************/ -void pcie_config_misc_clk(struct device *nb_dev) -{ - u32 reg; - - reg = pci_read_config32(nb_dev, 0x4c); - reg |= 1 << 0; - pci_write_config32(nb_dev, 0x4c, reg); - -#if 0 - /* TODO: Check the mics clock later. */ - pci_devfn_t d0f1 = PCI_DEV(0, 0, 1); - - if (AtiPcieCfg.Config & PCIE_GFX_CLK_GATING) { - /* TXCLK Clock Gating */ - set_nbmisc_enable_bits(nb_dev, 0x07, 3 << 0, 3 << 0); - set_nbmisc_enable_bits(nb_dev, 0x07, 1 << 22, 1 << 22); - set_pcie_enable_bits(nb_dev, 0x11 | PCIE_CORE_INDEX_GFX, (3 << 6) | (~0xf), 3 << 6); - - /* LCLK Clock Gating */ - reg = pci_io_read_config32(d0f1, 0x94); - reg &= ~(1 << 16); - pci_io_write_config32(d0f1, 0x94, reg); - } - - if (AtiPcieCfg.Config & PCIE_GPP_CLK_GATING) { - /* TXCLK Clock Gating */ - set_nbmisc_enable_bits(nb_dev, 0x07, 3 << 4, 3 << 4); - set_nbmisc_enable_bits(nb_dev, 0x07, 1 << 22, 1 << 22); - set_pcie_enable_bits(nb_dev, 0x11 | PCIE_CORE_INDEX_SB, (3 << 6) | (~0xf), 3 << 6); - - /* LCLK Clock Gating */ - reg = pci_io_read_config32(d0f1, 0x94); - reg &= ~(1 << 24); - pci_io_write_config32(d0f1, 0x94, reg); - } -#endif - - reg = pci_read_config32(nb_dev, 0x4c); - reg &= ~(1 << 0); - pci_write_config32(nb_dev, 0x4c, reg); -} diff --git a/src/southbridge/amd/sr5650/rev.h b/src/southbridge/amd/sr5650/rev.h deleted file mode 100644 index 31e99148f7..0000000000 --- a/src/southbridge/amd/sr5650/rev.h +++ /dev/null @@ -1,23 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2010 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef __SR5650_REV_H__ -#define __SR5650_REV_H__ - -#define REV_SR5650_A11 0 -#define REV_SR5650_A12 1 -#define REV_SR5650_A21 2 - -#endif /* __SR5650_REV_H__ */ diff --git a/src/southbridge/amd/sr5650/sr5650.c b/src/southbridge/amd/sr5650/sr5650.c deleted file mode 100644 index 8131e77e5f..0000000000 --- a/src/southbridge/amd/sr5650/sr5650.c +++ /dev/null @@ -1,931 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2010 Advanced Micro Devices, Inc. - * Copyright (C) 2015 Timothy Pearson , Raptor Engineering - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include "sr5650.h" -#include "cmn.h" - -/* - * extern function declaration - */ -struct resource *sr5650_retrieve_cpu_mmio_resource() -{ - struct device *domain; - struct resource *res; - - for (domain = all_devices; domain; domain = domain->next) { - if (domain->bus->dev->path.type != DEVICE_PATH_DOMAIN) - continue; - res = probe_resource(domain->bus->dev, MMIO_CONF_BASE); - if (res) - return res; - } - - return NULL; -} - -/* extension registers */ -u32 pci_ext_read_config32(struct device *nb_dev, struct device *dev, u32 reg) -{ - /*get BAR3 base address for nbcfg0x1c */ - u32 addr = pci_read_config32(nb_dev, 0x1c) & ~0xF; - printk(BIOS_DEBUG, "addr=%x,bus=%x,devfn=%x\n", addr, dev->bus->secondary, - dev->path.pci.devfn); - addr |= dev->bus->secondary << 20 | /* bus num */ - dev->path.pci.devfn << 12 | reg; - return *((u32 *) addr); -} - -void pci_ext_write_config32(struct device *nb_dev, struct device *dev, u32 reg_pos, u32 mask, u32 val) -{ - u32 reg_old, reg; - - /*get BAR3 base address for nbcfg0x1c */ - u32 addr = pci_read_config32(nb_dev, 0x1c) & ~0xF; - /*printk(BIOS_DEBUG, "write: addr=%x,bus=%x,devfn=%x\n", addr, dev->bus->secondary, - dev->path.pci.devfn);*/ - addr |= dev->bus->secondary << 20 | /* bus num */ - dev->path.pci.devfn << 12 | reg_pos; - - reg = reg_old = *((u32 *) addr); - reg &= ~mask; - reg |= val; - if (reg != reg_old) { - *((u32 *) addr) = reg; - } -} - -u32 nbpcie_p_read_index(struct device *dev, u32 index) -{ - return nb_read_index((dev), NBPCIE_INDEX, (index)); -} - -void nbpcie_p_write_index(struct device *dev, u32 index, u32 data) -{ - nb_write_index((dev), NBPCIE_INDEX, (index), (data)); -} - -u32 nbpcie_ind_read_index(struct device *nb_dev, u32 index) -{ - return nb_read_index((nb_dev), NBPCIE_INDEX, (index)); -} - -void nbpcie_ind_write_index(struct device *nb_dev, u32 index, u32 data) -{ - nb_write_index((nb_dev), NBPCIE_INDEX, (index), (data)); -} - -uint32_t l2cfg_ind_read_index(struct device *nb_dev, uint32_t index) -{ - return nb_read_index((nb_dev), L2CFG_INDEX, (index)); -} - -void l2cfg_ind_write_index(struct device *nb_dev, uint32_t index, uint32_t data) -{ - nb_write_index((nb_dev), L2CFG_INDEX | (0x1 << 8), (index), (data)); -} - -uint32_t l1cfg_ind_read_index(struct device *nb_dev, uint32_t index) -{ - return nb_read_index((nb_dev), L1CFG_INDEX, (index)); -} - -void l1cfg_ind_write_index(struct device *nb_dev, uint32_t index, uint32_t data) -{ - nb_write_index((nb_dev), L1CFG_INDEX | (0x1 << 31), (index), (data)); -} - -/*********************************************************** -* To access bar3 we need to program PCI MMIO 7 in K8. -* in_out: -* 1: enable/enter k8 temp mmio base -* 0: disable/restore -***********************************************************/ -void ProgK8TempMmioBase(u8 in_out, u32 pcie_base_add, u32 mmio_base_add) -{ - /* K8 Function1 is address map */ - struct device *k8_f1 = pcidev_on_root(0x18, 1); - struct device *k8_f0 = pcidev_on_root(0x18, 0); - - if (in_out) { - u32 dword, sblk; - - /* Get SBLink value (HyperTransport I/O Hub Link ID). */ - dword = pci_read_config32(k8_f0, 0x64); - sblk = (dword >> 8) & 0x3; - - /* Fill MMIO limit/base pair. */ - pci_write_config32(k8_f1, 0xbc, - (((pcie_base_add + 0x10000000 - - 1) >> 8) & 0xffffff00) | 0x80 | (sblk << 4)); - pci_write_config32(k8_f1, 0xb8, (pcie_base_add >> 8) | 0x3); - pci_write_config32(k8_f1, 0xb4, - (((mmio_base_add + 0x10000000 - - 1) >> 8) & 0xffffff00) | (sblk << 4)); - pci_write_config32(k8_f1, 0xb0, (mmio_base_add >> 8) | 0x3); - } else { - pci_write_config32(k8_f1, 0xb8, 0); - pci_write_config32(k8_f1, 0xbc, 0); - pci_write_config32(k8_f1, 0xb0, 0); - pci_write_config32(k8_f1, 0xb4, 0); - } -} - -void PcieReleasePortTraining(struct device *nb_dev, struct device *dev, u32 port) -{ - switch (port) { - case 2: /* GPP1, bit4-5 */ - case 3: - set_nbmisc_enable_bits(nb_dev, PCIE_LINK_CFG, - 1 << (port + 2), 0 << (port + 2)); - break; - case 4: /* GPP3a, bit20-24 */ - case 5: - case 6: - case 7: - set_nbmisc_enable_bits(nb_dev, PCIE_LINK_CFG, - 1 << (port + 17), 0 << (port + 17)); - break; - case 9: /* GPP3a, bit25,26 */ - case 10: - set_nbmisc_enable_bits(nb_dev, PCIE_LINK_CFG, - 1 << (port + 16), 0 << (port + 16)); - break; - case 11: /* GPP2, bit6-7 */ - case 12: - set_nbmisc_enable_bits(nb_dev, PCIE_LINK_CFG, - 1 << (port - 5), 0 << (port - 5)); - break; - case 13: /* GPP3b, bit4 of NBMISCIND:0x2A */ - set_nbmisc_enable_bits(nb_dev, 0x2A, - 1 << 4, 0 << 4); - break; - } -} - -/******************************************************************************************************** -* Output: -* 0: no device is present. -* 1: device is present and is trained. -********************************************************************************************************/ -u8 PcieTrainPort(struct device *nb_dev, struct device *dev, u32 port) -{ - u16 count = 5000; - u32 lc_state, reg, current_link_width, lane_mask; - u8 current, res = 0; - u32 gpp_sb_sel = 0; - - switch (port) { - case 2: - case 3: - gpp_sb_sel = PCIE_CORE_INDEX_GPP1; - break; - case 4 ... 7: - case 9: - case 10: - gpp_sb_sel = PCIE_CORE_INDEX_GPP3a; - break; - case 11: - case 12: - gpp_sb_sel = PCIE_CORE_INDEX_GPP2; - break; - case 13: - gpp_sb_sel = PCIE_CORE_INDEX_GPP3b; - break; - } - - while (count--) { - udelay(40200); - lc_state = nbpcie_p_read_index(dev, 0xa5); /* lc_state */ - printk(BIOS_DEBUG, "PcieLinkTraining port=%x:lc current state=%x\n", - port, lc_state); - current = lc_state & 0x3f; /* get LC_CURRENT_STATE, bit0-5 */ - - switch (current) { - /* 0x00-0x04 means no device is present */ - case 0x06: - /* read back current link width [6:4]. */ - current_link_width = (nbpcie_p_read_index(dev, 0xA2) >> 4) & 0x7; - /* 4 means 7:4 and 15:12 - * 3 means 7:2 and 15:10 - * 2 means 7:1 and 15:9 - * ignoring the reversal case - */ - lane_mask = (0xFF << (current_link_width - 2) * 2) & 0xFF; - reg = nbpcie_ind_read_index(nb_dev, 0x65 | gpp_sb_sel); - reg |= lane_mask << 8 | lane_mask; - /* NOTE: See the comments in rs780_pcie.c - * switching_gppsb_configurations - * In CIMx 4.5.0 and RPR, 4c is done before 5 & 6. - * But in this way, a x4 device in port B (dev 4) of - * Configuration B can only be detected as x1, instead - * of x4. When the port B is being trained, the - * LC_CURRENT_STATE is 6 and the LC_LINK_WIDTH_RD is 1. - * We have to set the PCIEIND:0x65 as 0xE0E0 and reset - * the slot. Then the card seems to work in x1 mode. - */ - reg = 0xE0E0; /*I think that the lane_mask calc above is wrong, and this can't be hardcoded because the configuration changes.*/ - nbpcie_ind_write_index(nb_dev, 0x65 | gpp_sb_sel, reg); - printk(BIOS_DEBUG, "link_width=%x, lane_mask=%x", - current_link_width, lane_mask); - set_pcie_reset(); - mdelay(1); - set_pcie_dereset(); - break; - case 0x07: /* device is in compliance state (training sequence is done). Move to train the next device */ - res = 1; - count = 0; - break; - case 0x10: - reg = - pci_ext_read_config32(nb_dev, dev, - PCIE_VC0_RESOURCE_STATUS); - printk(BIOS_DEBUG, "PcieTrainPort reg=0x%x\n", reg); - /* check bit1 */ - if (reg & VC_NEGOTIATION_PENDING) { /* bit1=1 means the link needs to be re-trained. */ - /* set bit8=1, bit0-2=bit4-6 */ - u32 tmp; - reg = nbpcie_p_read_index(dev, PCIE_LC_LINK_WIDTH); - tmp = (reg >> 4) & 0x7; /* get bit4-6 */ - reg &= 0xfff8; /* clear bit0-2 */ - reg += tmp; /* merge */ - reg |= 1 << 8; - nbpcie_p_write_index(dev, PCIE_LC_LINK_WIDTH, reg); - count++; /* CIM said "keep in loop"? */ - } else { - res = 1; - count = 0; - } - break; - default: - /* CIMx Unknown Workaround - There is a device that won't train. Try to reset it. */ - /* if there are no device resets and nothing works, CIMx does a cf9 system reset (yikes!) */ - set_pcie_reset(); - mdelay(1); - set_pcie_dereset(); - res = 0; - count = 0; /* break loop */ - break; - } - } - return res; -} - -/* - * Set Top Of Memory below and above 4G. - */ -void sr5650_set_tom(struct device *nb_dev) -{ - msr_t sysmem; - - /* The system top memory in SR56X0. */ - sysmem = rdmsr(TOP_MEM); - printk(BIOS_DEBUG, "Sysmem TOM = %x_%x\n", sysmem.hi, sysmem.lo); - pci_write_config32(nb_dev, 0x90, sysmem.lo); - - sysmem = rdmsr(TOP_MEM2); - printk(BIOS_DEBUG, "Sysmem TOM2 = %x_%x\n", sysmem.hi, sysmem.lo); - htiu_write_index(nb_dev, 0x31, sysmem.hi); - htiu_write_index(nb_dev, 0x30, sysmem.lo | 1); -} - -u32 get_vid_did(struct device *dev) -{ - return pci_read_config32(dev, 0); -} - -void detect_and_enable_iommu(struct device *iommu_dev) { - uint32_t dword; - uint8_t l1_target; - unsigned char iommu; - void *mmio_base; - - iommu = 1; - get_option(&iommu, "iommu"); - - if (iommu) { - printk(BIOS_DEBUG, "Initializing IOMMU\n"); - - struct device *nb_dev = pcidev_on_root(0, 0); - - if (!nb_dev) { - printk(BIOS_WARNING, "Unable to find SR5690 device! IOMMU NOT initialized\n"); - return; - } - - mmio_base = (void *)(pci_read_config32(iommu_dev, 0x44) & - 0xffffc000); - - // if (get_nb_rev(nb_dev) == REV_SR5650_A11) { - // dword = pci_read_config32(iommu_dev, 0x6c); - // dword &= ~(0x1 << 8); - // pci_write_config32(iommu_dev, 0x6c, dword); - // } - - dword = pci_read_config32(iommu_dev, 0x50); - dword &= ~(0x1 << 22); - pci_write_config32(iommu_dev, 0x50, dword); - - dword = pci_read_config32(iommu_dev, 0x44); - dword |= 0x1; - pci_write_config32(iommu_dev, 0x44, dword); - - write32((void *)(mmio_base + 0x8), 0x0); - write32((void *)(mmio_base + 0xc), 0x08000000); - write32((void *)(mmio_base + 0x10), 0x0); - write32((void *)(mmio_base + 0x2008), 0x0); - write32((void *)(mmio_base + 0x2010), 0x0); - - /* IOMMU L1 initialization */ - for (l1_target = 0; l1_target < 6; l1_target++) { - dword = l1cfg_ind_read_index(nb_dev, (l1_target << 16) + 0xc); - dword |= (0x7 << 28); - l1cfg_ind_write_index(nb_dev, (l1_target << 16) + 0xc, dword); - - dword = l1cfg_ind_read_index(nb_dev, (l1_target << 16) + 0x7); - dword |= (0x1 << 5); - l1cfg_ind_write_index(nb_dev, (l1_target << 16) + 0x7, dword); - } - - /* IOMMU L2 initialization */ - dword = l2cfg_ind_read_index(nb_dev, 0xc); - dword |= (0x7 << 29); - l2cfg_ind_write_index(nb_dev, 0xc, dword); - - dword = l2cfg_ind_read_index(nb_dev, 0x10); - dword &= ~(0x3 << 8); - dword |= (0x2 << 8); - l2cfg_ind_write_index(nb_dev, 0x10, dword); - - dword = l2cfg_ind_read_index(nb_dev, 0x14); - dword &= ~(0x3 << 8); - dword |= (0x2 << 8); - l2cfg_ind_write_index(nb_dev, 0x14, dword); - - dword = l2cfg_ind_read_index(nb_dev, 0x18); - dword &= ~(0x3 << 8); - dword |= (0x2 << 8); - l2cfg_ind_write_index(nb_dev, 0x18, dword); - - dword = l2cfg_ind_read_index(nb_dev, 0x1c); - dword &= ~(0x3 << 8); - dword |= (0x2 << 8); - l2cfg_ind_write_index(nb_dev, 0x1c, dword); - - dword = l2cfg_ind_read_index(nb_dev, 0x50); - dword &= ~(0x3 << 8); - dword |= (0x2 << 8); - l2cfg_ind_write_index(nb_dev, 0x50, dword); - - dword = l2cfg_ind_read_index(nb_dev, 0x10); - dword |= (0x1 << 4); - l2cfg_ind_write_index(nb_dev, 0x10, dword); - - dword = l2cfg_ind_read_index(nb_dev, 0x14); - dword |= (0x1 << 4); - l2cfg_ind_write_index(nb_dev, 0x14, dword); - - dword = l2cfg_ind_read_index(nb_dev, 0x18); - dword |= (0x1 << 4); - l2cfg_ind_write_index(nb_dev, 0x18, dword); - - dword = l2cfg_ind_read_index(nb_dev, 0x1c); - dword |= (0x1 << 4); - l2cfg_ind_write_index(nb_dev, 0x1c, dword); - - dword = l2cfg_ind_read_index(nb_dev, 0x50); - dword |= (0x1 << 4); - l2cfg_ind_write_index(nb_dev, 0x50, dword); - - dword = l2cfg_ind_read_index(nb_dev, 0x6); - dword |= (0x1 << 7); - l2cfg_ind_write_index(nb_dev, 0x6, dword); - - dword = l2cfg_ind_read_index(nb_dev, 0x44); - dword |= (0x1 << 0); - l2cfg_ind_write_index(nb_dev, 0x44, dword); - -// if (get_nb_rev(nb_dev) == REV_SR5650_A21) { - dword = l2cfg_ind_read_index(nb_dev, 0x7); - dword |= (0x1 << 1); - l2cfg_ind_write_index(nb_dev, 0x7, dword); - - dword = l2cfg_ind_read_index(nb_dev, 0x44); - dword |= (0x1 << 1); - l2cfg_ind_write_index(nb_dev, 0x44, dword); - - dword = l2cfg_ind_read_index(nb_dev, 0x7); - dword |= (0x1 << 2); - l2cfg_ind_write_index(nb_dev, 0x7, dword); - - dword = l2cfg_ind_read_index(nb_dev, 0x7); - dword |= (0x1 << 3); - l2cfg_ind_write_index(nb_dev, 0x7, dword); - - dword = l2cfg_ind_read_index(nb_dev, 0x44); - dword |= (0x1 << 3); - l2cfg_ind_write_index(nb_dev, 0x44, dword); - - dword = l2cfg_ind_read_index(nb_dev, 0x7); - dword |= (0x1 << 4); - l2cfg_ind_write_index(nb_dev, 0x7, dword); - - dword = l2cfg_ind_read_index(nb_dev, 0x6); - dword |= (0x1 << 5); - l2cfg_ind_write_index(nb_dev, 0x6, dword); - - dword = l2cfg_ind_read_index(nb_dev, 0x6); - dword |= (0x1 << 6); - l2cfg_ind_write_index(nb_dev, 0x6, dword); - - dword = l2cfg_ind_read_index(nb_dev, 0x7); - dword |= (0x1 << 5); - l2cfg_ind_write_index(nb_dev, 0x7, dword); - - dword = l2cfg_ind_read_index(nb_dev, 0x44); - dword |= (0x1 << 4); - l2cfg_ind_write_index(nb_dev, 0x44, dword); - - dword = l2cfg_ind_read_index(nb_dev, 0x7); - dword |= (0x1 << 6); - l2cfg_ind_write_index(nb_dev, 0x7, dword); - - dword = l2cfg_ind_read_index(nb_dev, 0x7); - dword |= (0x1 << 7); - l2cfg_ind_write_index(nb_dev, 0x7, dword); - - dword = l2cfg_ind_read_index(nb_dev, 0x6); - dword |= (0x1 << 8); - l2cfg_ind_write_index(nb_dev, 0x6, dword); -// } - - l2cfg_ind_write_index(nb_dev, 0x52, 0xf0000002); - - dword = l2cfg_ind_read_index(nb_dev, 0x80); - dword |= (0x1 << 0); - l2cfg_ind_write_index(nb_dev, 0x80, dword); - - dword = l2cfg_ind_read_index(nb_dev, 0x30); - dword |= (0x1 << 0); - l2cfg_ind_write_index(nb_dev, 0x30, dword); - } -} - -void sr5650_iommu_read_resources(struct device *dev) -{ - unsigned char iommu; - struct resource *res; - - iommu = 1; - get_option(&iommu, "iommu"); - - /* Get the normal pci resources of this device */ - pci_dev_read_resources(dev); - - if (iommu) { - /* Request MMIO range allocation */ - res = new_resource(dev, 0x44); /* IOMMU */ - res->base = 0x0; - res->size = 0x4000; - res->limit = 0xFFFFFFFFUL; /* res->base + res->size -1; */ - res->align = 14; /* 16k alignment */ - res->gran = 14; - res->flags = IORESOURCE_MEM | IORESOURCE_RESERVE; - } - - compact_resources(dev); -} - -void sr5650_iommu_set_resources(struct device *dev) -{ - unsigned char iommu; - struct resource *res; - - iommu = 1; - get_option(&iommu, "iommu"); - - /* Get the normal pci resources of this device */ - pci_dev_read_resources(dev); - - if (iommu) { - /* Get the allocated range */ - res = find_resource(dev, 0x44); - - if (res->base == 0) { - printk(BIOS_WARNING, "Unable to allocate MMIO range to IOMMU\n"); - } - - /* Assign the range to hardware */ - pci_write_config32(dev, 0x44, res->base & 0xffffc000); - pci_write_config32(dev, 0x48, 0x0); - } - - /* Run standard resource set routine */ - pci_dev_set_resources(dev); -} - -void sr5650_iommu_enable_resources(struct device *dev) -{ - detect_and_enable_iommu(dev); -} - -void sr5650_nb_pci_table(struct device *nb_dev) -{ /* NBPOR_InitPOR function. */ - u8 temp8; - u16 temp16; - u32 temp32; - - /* Program NB PCI table. */ - temp16 = pci_read_config16(nb_dev, 0x04); - printk(BIOS_DEBUG, "NB_PCI_REG04 = %x.\n", temp16); - temp32 = pci_read_config32(nb_dev, 0x84); - printk(BIOS_DEBUG, "NB_PCI_REG84 = %x.\n", temp32); - //Reg4Ch[1]=1 (APIC_ENABLE) force CPU request with address 0xFECx_xxxx to south-bridge - //Reg4Ch[6]=1 (BMMsgEn) enable BM_Set message generation - pci_write_config8(nb_dev, 0x4c, 0x42); - temp8 = pci_read_config8(nb_dev, 0x4e); - temp8 |= 0x05; /* BAR1_ENABLE */ - pci_write_config8(nb_dev, 0x4e, temp8); - - temp32 = pci_read_config32(nb_dev, 0x4c); - printk(BIOS_DEBUG, "NB_PCI_REG4C = %x.\n", temp32); - - /* disable GFX debug. */ - temp8 = pci_read_config8(nb_dev, 0x8d); - temp8 &= ~(1<<1); - pci_write_config8(nb_dev, 0x8d, temp8); - - /* The system top memory in SR56X0. */ - sr5650_set_tom(nb_dev); - - /* Program NB HTIU table. */ - //set_htiu_enable_bits(nb_dev, 0x05, 1<<10 | 1<<9, 1<<10|1<<9); - set_htiu_enable_bits(nb_dev, 0x06, 1, 0x4203a202); - //set_htiu_enable_bits(nb_dev, 0x07, 1<<1 | 1<<2, 0x8001); - set_htiu_enable_bits(nb_dev, 0x15, 0, 1<<31 | 1<<30 | 1<<27); - set_htiu_enable_bits(nb_dev, 0x1c, 0, 0xfffe0000); - set_htiu_enable_bits(nb_dev, 0x0c, 0x3f, 1 | 1<<3); - set_htiu_enable_bits(nb_dev, 0x19, 0xfffff+(1<<31), 0x186a0+(1<<31)); - set_htiu_enable_bits(nb_dev, 0x16, 0x3f<<10, 0x7<<10); - set_htiu_enable_bits(nb_dev, 0x23, 0, 1<<28); -} - -/*********************************************** -* 0:00.0 NBCFG : -* 0:00.1 CLK : bit 0 of nb_cfg 0x4c : 0 - disable, default -* 0:01.0 P2P Internal: -* 0:02.0 P2P : bit 2 of nbmiscind 0x0c : 0 - enable, default + 32 * 2 -* 0:03.0 P2P : bit 3 of nbmiscind 0x0c : 0 - enable, default + 32 * 2 -* 0:04.0 P2P : bit 4 of nbmiscind 0x0c : 0 - enable, default + 32 * 2 -* 0:05.0 P2P : bit 5 of nbmiscind 0x0c : 0 - enable, default + 32 * 2 -* 0:06.0 P2P : bit 6 of nbmiscind 0x0c : 0 - enable, default + 32 * 2 -* 0:07.0 P2P : bit 7 of nbmiscind 0x0c : 0 - enable, default + 32 * 2 -* 0:08.0 NB2SB : bit 6 of nbmiscind 0x00 : 0 - disable, default + 32 * 1 -* case 0 will be called twice, one is by CPU in hypertransport.c line458, -* the other is by sr5650. -***********************************************/ -void sr5650_enable(struct device *dev) -{ - struct device *nb_dev = NULL, *sb_dev = NULL; - int dev_ind; - struct southbridge_amd_sr5650_config *cfg; - - printk(BIOS_INFO, "sr5650_enable: dev=%p, VID_DID=0x%x\n", dev, get_vid_did(dev)); - nb_dev = pcidev_on_root(0, 0); - if (!nb_dev) { - die("sr5650_enable: CAN NOT FIND SR5650 DEVICE, HALT!\n"); - /* NOT REACHED */ - } - cfg = (struct southbridge_amd_sr5650_config *)nb_dev->chip_info; - - /* sb_dev (dev 8) is a bridge that links to southbridge. */ - sb_dev = pcidev_on_root(8, 0); - if (!sb_dev) { - die("sr5650_enable: CAN NOT FIND SB bridge, HALT!\n"); - /* NOT REACHED */ - } - - dev_ind = dev->path.pci.devfn >> 3; - switch (dev_ind) { - case 0: /* bus0, dev0, fun0; */ - switch (dev->path.pci.devfn & 0x7) { - case 0: - printk(BIOS_INFO, "Bus-0, Dev-0, Fun-0.\n"); - enable_pcie_bar3(nb_dev); /* PCIEMiscInit */ - - config_gpp_core(nb_dev, sb_dev); - sr5650_gpp_sb_init(nb_dev, sb_dev, 8); - - sr5650_nb_pci_table(nb_dev); - break; - case 1: - printk(BIOS_INFO, "Bus-0, Dev-0, Fun-1.\n"); - break; - case 2: - printk(BIOS_INFO, "Bus-0, Dev-0, Fun-2.\n"); - break; - } - break; - - case 2: /* bus0, dev2,3 GPP1 */ - case 3: - printk(BIOS_INFO, "Bus-0, Dev-2,3, Fun-0. enable=%d\n", dev->enabled); - set_nbmisc_enable_bits(nb_dev, 0x0c, 1 << dev_ind, - (dev->enabled ? 0 : 1) << dev_ind); - if (dev->enabled) - sr5650_gpp_sb_init(nb_dev, dev, dev_ind); /* Note, dev 2,3 are generic PCIe ports. */ - break; - case 4: /* bus0, dev4-7, four GPP3a */ - case 5: - case 6: - case 7: - enable_pcie_bar3(nb_dev); /* PCIEMiscInit */ - printk(BIOS_INFO, "Bus-0, Dev-4,5,6,7, Fun-0. enable=%d\n", - dev->enabled); - set_nbmisc_enable_bits(nb_dev, 0x0c, 1 << dev_ind, - (dev->enabled ? 0 : 1) << dev_ind); - if (dev->enabled) - sr5650_gpp_sb_init(nb_dev, dev, dev_ind); - break; - case 8: /* bus0, dev8, SB */ - printk(BIOS_INFO, "Bus-0, Dev-8, Fun-0. enable=%d\n", dev->enabled); - set_nbmisc_enable_bits(nb_dev, 0x00, 1 << 6, - (dev->enabled ? 1 : 0) << 6); - if (dev->enabled) - sr5650_gpp_sb_init(nb_dev, dev, dev_ind); - disable_pcie_bar3(nb_dev); - break; - case 9: /* bus 0, dev 9,10, GPP3a */ - case 10: - printk(BIOS_INFO, "Bus-0, Dev-9, 10, Fun-0. enable=%d\n", - dev->enabled); - enable_pcie_bar3(nb_dev); /* PCIEMiscInit */ - set_nbmisc_enable_bits(nb_dev, 0x0c, 1 << (7 + dev_ind), - (dev->enabled ? 0 : 1) << (7 + dev_ind)); - if (dev->enabled) - sr5650_gpp_sb_init(nb_dev, dev, dev_ind); - /* Don't call disable_pcie_bar3(nb_dev) here, otherwise the screen will crash. */ - break; - case 11: - case 12: /* bus 0, dev 11,12, GPP2 */ - printk(BIOS_INFO, "Bus-0, Dev-11,12, Fun-0. enable=%d\n", dev->enabled); - set_nbmisc_enable_bits(nb_dev, 0x0c, 1 << (7 + dev_ind), - (dev->enabled ? 0 : 1) << (7 + dev_ind)); - if (dev->enabled) - sr5650_gpp_sb_init(nb_dev, dev, dev_ind); - break; - case 13: /* bus 0, dev 12, GPP3b */ - set_nbmisc_enable_bits(nb_dev, 0x0c, 1 << (7 + dev_ind), - (dev->enabled ? 0 : 1) << (7 + dev_ind)); - if (dev->enabled) - sr5650_gpp_sb_init(nb_dev, dev, dev_ind); - break; - default: - printk(BIOS_DEBUG, "unknown dev: %s\n", dev_path(dev)); - } - - /* Lock HWInit Register after the last device was done */ - if (dev_ind == 13) { - sr56x0_lock_hwinitreg(); - udelay(cfg->pcie_settling_time); - } -} - -static void add_ivrs_device_entries(struct device *parent, struct device *dev, - int depth, int linknum, int8_t *root_level, - unsigned long *current, uint16_t *length) -{ - uint8_t *p = (uint8_t *) *current; - - struct device *sibling; - struct bus *link; - - if ((dev->path.type == DEVICE_PATH_PCI) && - (dev->bus->secondary == 0x0) && (dev->path.pci.devfn == 0x0)) - *root_level = depth; - - if ((dev->path.type == DEVICE_PATH_PCI) && (*root_level != -1) && - (depth >= *root_level) && (dev->enabled)) { - - *p = 0; - if (depth == *root_level) { - if (dev->path.pci.devfn < (0x1 << 3)) { - /* SR5690 control device */ - } else if ((dev->path.pci.devfn >= (0x1 << 3)) && - (dev->path.pci.devfn < (0xe << 3))) { - /* SR5690 PCIe bridge device */ - } else if (dev->path.pci.devfn == (0x14 << 3)) { - /* SMBUS controller */ - p[0] = IVHD_DEV_4_BYTE_SELECT; /* Entry type */ - p[1] = dev->path.pci.devfn; /* Device */ - p[2] = dev->bus->secondary; /* Bus */ - p[3] = IVHD_DTE_LINT_1_PASS | /* Data */ - IVHD_DTE_SYS_MGT_NO_TRANS | - IVHD_DTE_NMI_PASS | - IVHD_DTE_EXT_INT_PASS | - IVHD_DTE_INIT_PASS; - } else { - /* Other southbridge device */ - p[0] = IVHD_DEV_4_BYTE_SELECT; /* Entry type */ - p[1] = dev->path.pci.devfn; /* Device */ - p[2] = dev->bus->secondary; /* Bus */ - p[3] = 0x0; /* Data */ - } - } else if ((dev->hdr_type & 0x7f) == PCI_HEADER_TYPE_NORMAL) { - /* Device behind bridge */ - if (pci_find_capability(dev, PCI_CAP_ID_PCIE)) { - /* Device is PCIe */ - p[0] = IVHD_DEV_4_BYTE_SELECT; /* Entry type */ - p[1] = dev->path.pci.devfn; /* Device */ - p[2] = dev->bus->secondary; /* Bus */ - p[3] = 0x0; /* Data */ - } else { - /* Device is legacy PCI or PCI-X */ - p[0] = IVHD_DEV_8_BYTE_ALIAS_SELECT; /* Entry */ - p[1] = dev->path.pci.devfn; /* Device */ - p[2] = dev->bus->secondary; /* Bus */ - p[3] = 0x0; /* Data */ - p[4] = 0x0; /* Reserved */ - p[5] = parent->path.pci.devfn; /* Device */ - p[6] = parent->bus->secondary; /* Bus */ - p[7] = 0x0; /* Reserved */ - } - } - - if (*p == IVHD_DEV_4_BYTE_SELECT) { - *length += 4; - *current += 4; - } else if (*p == IVHD_DEV_8_BYTE_ALIAS_SELECT) { - *length += 8; - *current += 8; - } - } - - for (link = dev->link_list; link; link = link->next) - for (sibling = link->children; sibling; - sibling = sibling->sibling) - add_ivrs_device_entries(dev, sibling, depth + 1, - depth, root_level, current, length); -} - -unsigned long acpi_fill_mcfg(unsigned long current) -{ - struct resource *res; - resource_t mmconf_base = EXT_CONF_BASE_ADDRESS; - - if (CONFIG(EXT_CONF_SUPPORT)) { - res = sr5650_retrieve_cpu_mmio_resource(); - if (res) - mmconf_base = res->base; - - current += acpi_create_mcfg_mmconfig((acpi_mcfg_mmconfig_t *)current, mmconf_base, 0x0, 0x0, 0x1f); - } - - return current; -} - -static unsigned long acpi_fill_ivrs(acpi_ivrs_t *ivrs, unsigned long current) -{ - uint8_t *p; - - struct device *nb_dev = pcidev_on_root(0, 0); - if (!nb_dev) { - printk(BIOS_WARNING, "acpi_fill_ivrs: Unable to locate SR5650 " - "device! IVRS table not generated...\n"); - return (unsigned long)ivrs; - } - - struct device *iommu_dev = pcidev_on_root(0, 2); - if (!iommu_dev) { - printk(BIOS_WARNING, "acpi_fill_ivrs: Unable to locate SR5650 " - "IOMMU device! IVRS table not generated...\n"); - return (unsigned long)ivrs; - } - - ivrs->iv_info = IVINFO_VA_SIZE_64_BITS | IVINFO_PA_SIZE_52_BITS; - - ivrs->ivhd.type = IVHD_BLOCK_TYPE_LEGACY__FIXED; - ivrs->ivhd.flags = IVHD_FLAG_ISOC | - IVHD_FLAG_RES_PASS_PW | - IVHD_FLAG_PASS_PW | - IVHD_FLAG_IOTLB_SUP; - - ivrs->ivhd.length = sizeof(struct acpi_ivrs_ivhd); - - /* BDF :00.2 */ - ivrs->ivhd.device_id = 0x2 | (nb_dev->bus->secondary << 8); - - /* Capability block 0x40 (type 0xf, "Secure device") */ - ivrs->ivhd.capability_offset = 0x40; - ivrs->ivhd.iommu_base_low = pci_read_config32(iommu_dev, 0x44) & - 0xffffc000; - ivrs->ivhd.iommu_base_high = pci_read_config32(iommu_dev, 0x48); - ivrs->ivhd.pci_segment_group = 0x0; - ivrs->ivhd.iommu_info = 0x0; - ivrs->ivhd.iommu_info |= (0x14 << IOMMU_INFO_UNIT_ID_SHIFT); - ivrs->ivhd.iommu_feature_info = 0x0; - - /* Describe HPET */ - p = (uint8_t *)current; - p[0] = IVHD_DEV_8_BYTE_EXT_SPECIAL_DEV; /* Entry type */ - p[1] = 0; /* Device */ - p[2] = 0; /* Bus */ - p[3] = IVHD_DTE_LINT_1_PASS | /* DTE */ - IVHD_DTE_LINT_0_PASS | - IVHD_DTE_SYS_MGT_INTX_NO_TRANS | - IVHD_DTE_NMI_PASS | - IVHD_DTE_EXT_INT_PASS | - IVHD_DTE_INIT_PASS; - p[4] = 0x0; /* HPET number */ - p[5] = 0x14 << 3; /* HPET device */ - p[6] = nb_dev->bus->secondary; /* HPET bus */ - p[7] = IVHD_SPECIAL_DEV_HPET; /* Variety */ - ivrs->ivhd.length += 8; - current += 8; - - /* Describe PCI devices */ - int8_t root_level = -1; - add_ivrs_device_entries(NULL, all_devices, 0, -1, &root_level, ¤t, - &ivrs->ivhd.length); - - /* Describe IOAPICs */ - unsigned long prev_current = current; - current = acpi_fill_ivrs_ioapic(ivrs, current); - ivrs->ivhd.length += (current - prev_current); - - return current; -} - -unsigned long southbridge_write_acpi_tables(struct device *device, - unsigned long current, - struct acpi_rsdp *rsdp) -{ - unsigned char iommu; - - iommu = 1; - get_option(&iommu, "iommu"); - - if (iommu) { - acpi_ivrs_t *ivrs; - - /* IVRS */ - current = ALIGN(current, 8); - printk(BIOS_DEBUG, "ACPI: * IVRS at %lx\n", current); - ivrs = (acpi_ivrs_t *) current; - acpi_create_ivrs(ivrs, acpi_fill_ivrs); - current += ivrs->header.length; - acpi_add_table(rsdp, ivrs); - } - - return current; -} - -static struct pci_operations iommu_ops_pci = { - .set_subsystem = pci_dev_set_subsystem, -}; - -static struct device_operations iommu_ops = { - .read_resources = sr5650_iommu_read_resources, - .set_resources = sr5650_iommu_set_resources, - .enable_resources = sr5650_iommu_enable_resources, - .write_acpi_tables = southbridge_write_acpi_tables, - .init = 0, - .scan_bus = 0, - .ops_pci = &iommu_ops_pci, -}; - -static const struct pci_driver ht_driver_sr5690 __pci_driver = { - .ops = &iommu_ops, - .vendor = PCI_VENDOR_ID_ATI, - .device = PCI_DEVICE_ID_AMD_SR5650_IOMMU, -}; - -struct chip_operations southbridge_amd_sr5650_ops = { - CHIP_NAME("ATI SR5650") - .enable_dev = sr5650_enable, -}; diff --git a/src/southbridge/amd/sr5650/sr5650.h b/src/southbridge/amd/sr5650/sr5650.h deleted file mode 100644 index 06a427987d..0000000000 --- a/src/southbridge/amd/sr5650/sr5650.h +++ /dev/null @@ -1,139 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2010 Advanced Micro Devices, Inc. - * Copyright (C) 2015 Timothy Pearson , Raptor Engineering - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef __SR5650_H__ -#define __SR5650_H__ - -#include -#include -#include "chip.h" -#include "rev.h" - -typedef struct __PCIE_CFG__ { - u16 Config; - u8 ResetReleaseDelay; - u8 Gfx0Width; - u8 Gfx1Width; - u8 GfxPayload; - u8 GppPayload; - u16 PortDetect; - u8 PortHp; /* hot plug */ - u16 DbgConfig; - u32 DbgConfig2; - u8 GfxLx; - u8 GppLx; - u8 NBSBLx; - u8 PortSlotInit; - u8 Gfx0Pwr; - u8 Gfx1Pwr; - u8 GppPwr; -} PCIE_CFG; - -/* PCIE config flags */ -#define PCIE_DUALSLOT_CONFIG (1 << 0) -#define PCIE_OVERCLOCK_ENABLE (1 << 1) -#define PCIE_GPP_CLK_GATING (1 << 2) -#define PCIE_ENABLE_STATIC_DEV_REMAP (1 << 3) -#define PCIE_OFF_UNUSED_GFX_LANES (1 << 4) -#define PCIE_OFF_UNUSED_GPP_LANES (1 << 5) -#define PCIE_DISABLE_HIDE_UNUSED_PORTS (1 << 7) -#define PCIE_GFX_CLK_GATING (1 << 11) -#define PCIE_GFX_COMPLIANCE (1 << 14) -#define PCIE_GPP_COMPLIANCE (1 << 15) - -/* -------------------- ---------------------- -* NBMISCIND - ------------------- -----------------------*/ -#define PCIE_LINK_CFG 0x8 -#define PCIE_NBCFG_REG7 0x37 -#define STRAPS_OUTPUT_MUX_7 0x67 -#define STRAPS_OUTPUT_MUX_A 0x6a - -/* -------------------- ---------------------- -* PCIEIND - ------------------- -----------------------*/ -#define PCIE_CI_CNTL 0x20 -#define PCIE_LC_LINK_WIDTH 0xa2 -#define PCIE_LC_STATE0 0xa5 -#define PCIE_VC0_RESOURCE_STATUS 0x12a /* 16bit read only */ - -#define PCIE_CORE_INDEX_SB (0x05 << 16) /* see rpr 4.3.2.2, bdg 2.1 */ -#define PCIE_CORE_INDEX_GPP1 (0x04 << 16) -#define PCIE_CORE_INDEX_GPP2 (0x06 << 16) -#define PCIE_CORE_INDEX_GPP1_GPP2 (0x00 << 16) -#define PCIE_CORE_INDEX_GPP3a (0x07 << 16) -#define PCIE_CORE_INDEX_GPP3b (0x03 << 16) - -/* contents of PCIE_VC0_RESOURCE_STATUS */ -#define VC_NEGOTIATION_PENDING (1 << 1) - -#define LC_STATE_RECONFIG_GPPSB 0x10 - -/* ------------------------------------------------ -* Global variable -* ------------------------------------------------- */ -extern PCIE_CFG AtiPcieCfg; - -/* ----------------- export functions ----------------- */ -u32 nbpcie_p_read_index(struct device *dev, u32 index); -void nbpcie_p_write_index(struct device *dev, u32 index, u32 data); -u32 nbpcie_ind_read_index(struct device *nb_dev, u32 index); -void nbpcie_ind_write_index(struct device *nb_dev, u32 index, u32 data); -uint32_t l2cfg_ind_read_index(struct device *nb_dev, uint32_t index); -void l2cfg_ind_write_index(struct device *nb_dev, uint32_t index, - uint32_t data); -uint32_t l1cfg_ind_read_index(struct device *nb_dev, uint32_t index); -void l1cfg_ind_write_index(struct device *nb_dev, uint32_t index, - uint32_t data); -u32 pci_ext_read_config32(struct device *nb_dev, struct device *dev, u32 reg); -void pci_ext_write_config32(struct device *nb_dev, struct device *dev, u32 reg, - u32 mask, u32 val); -void sr5650_set_tom(struct device *nb_dev); - -unsigned long southbridge_write_acpi_tables(struct device *device, - unsigned long current, - struct acpi_rsdp *rsdp); - -void ProgK8TempMmioBase(u8 in_out, u32 pcie_base_add, u32 mmio_base_add); -void enable_pcie_bar3(struct device *nb_dev); -void disable_pcie_bar3(struct device *nb_dev); - -void enable_sr5650_dev8(void); -void sr5650_htinit(void); -void sr5650_htinit_dect_and_enable_isochronous_link(void); -void sr5650_early_setup(void); -void sr5650_before_pci_init(void); -void sr5650_enable(struct device *dev); -void sr5650_gpp_sb_init(struct device *nb_dev, struct device *dev, u32 port); -void sr5650_gfx_init(struct device *nb_dev, struct device *dev, u32 port); -void avoid_lpc_dma_deadlock(struct device *nb_dev, struct device *sb_dev); -void config_gpp_core(struct device *nb_dev, struct device *sb_dev); -void PcieReleasePortTraining(struct device *nb_dev, struct device *dev, - u32 port); -u8 PcieTrainPort(struct device *nb_dev, struct device *dev, u32 port); -void pcie_config_misc_clk(struct device *nb_dev); -void fam10_optimization(void); -void sr5650_disable_pcie_bridge(void); -u32 get_vid_did(struct device *dev); -void detect_and_enable_iommu(struct device *iommu_dev); -void sr5650_iommu_read_resources(struct device *dev); -void sr5650_iommu_set_resources(struct device *dev); -void sr5650_iommu_enable_resources(struct device *dev); -void sr5650_nb_pci_table(struct device *nb_dev); -void init_gen2(struct device *nb_dev, struct device *dev, u8 port); -void sr56x0_lock_hwinitreg(void); -struct resource * sr5650_retrieve_cpu_mmio_resource(void); -#endif /* __SR5650_H__ */ From 4c9bbb9b34bd4b8ec65f090748d79b81c6aad6ae Mon Sep 17 00:00:00 2001 From: Arthur Heymans Date: Tue, 19 Nov 2019 17:26:49 +0100 Subject: [PATCH 0297/1242] sb/broadcom/bcm5785: Drop support MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Relocatable ramstage, postcar stage and C_ENVIRONMENT_BOOTBLOCK are now mandatory features, which platforms using this code lack. Change-Id: I2305e0d9de0d4b1768e171f4c65d07306e7c3801 Signed-off-by: Arthur Heymans Reviewed-on: https://review.coreboot.org/c/coreboot/+/36970 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki Reviewed-by: Angel Pons --- src/southbridge/broadcom/bcm5785/Kconfig | 7 - src/southbridge/broadcom/bcm5785/Makefile.inc | 11 - src/southbridge/broadcom/bcm5785/bcm5785.c | 99 -------- src/southbridge/broadcom/bcm5785/bcm5785.h | 31 --- src/southbridge/broadcom/bcm5785/bootblock.c | 54 ----- src/southbridge/broadcom/bcm5785/chip.h | 28 --- .../broadcom/bcm5785/early_setup.c | 223 ------------------ .../broadcom/bcm5785/early_smbus.c | 61 ----- src/southbridge/broadcom/bcm5785/ide.c | 55 ----- src/southbridge/broadcom/bcm5785/lpc.c | 136 ----------- src/southbridge/broadcom/bcm5785/reset.c | 31 --- src/southbridge/broadcom/bcm5785/sata.c | 89 ------- .../broadcom/bcm5785/sb_pci_main.c | 155 ------------ src/southbridge/broadcom/bcm5785/smbus.h | 193 --------------- src/southbridge/broadcom/bcm5785/usb.c | 53 ----- 15 files changed, 1226 deletions(-) delete mode 100644 src/southbridge/broadcom/bcm5785/Kconfig delete mode 100644 src/southbridge/broadcom/bcm5785/Makefile.inc delete mode 100644 src/southbridge/broadcom/bcm5785/bcm5785.c delete mode 100644 src/southbridge/broadcom/bcm5785/bcm5785.h delete mode 100644 src/southbridge/broadcom/bcm5785/bootblock.c delete mode 100644 src/southbridge/broadcom/bcm5785/chip.h delete mode 100644 src/southbridge/broadcom/bcm5785/early_setup.c delete mode 100644 src/southbridge/broadcom/bcm5785/early_smbus.c delete mode 100644 src/southbridge/broadcom/bcm5785/ide.c delete mode 100644 src/southbridge/broadcom/bcm5785/lpc.c delete mode 100644 src/southbridge/broadcom/bcm5785/reset.c delete mode 100644 src/southbridge/broadcom/bcm5785/sata.c delete mode 100644 src/southbridge/broadcom/bcm5785/sb_pci_main.c delete mode 100644 src/southbridge/broadcom/bcm5785/smbus.h delete mode 100644 src/southbridge/broadcom/bcm5785/usb.c diff --git a/src/southbridge/broadcom/bcm5785/Kconfig b/src/southbridge/broadcom/bcm5785/Kconfig deleted file mode 100644 index 1ec4f8f692..0000000000 --- a/src/southbridge/broadcom/bcm5785/Kconfig +++ /dev/null @@ -1,7 +0,0 @@ -config SOUTHBRIDGE_BROADCOM_BCM5785 - bool - -config BOOTBLOCK_SOUTHBRIDGE_INIT - string - default "southbridge/broadcom/bcm5785/bootblock.c" - depends on SOUTHBRIDGE_BROADCOM_BCM5785 diff --git a/src/southbridge/broadcom/bcm5785/Makefile.inc b/src/southbridge/broadcom/bcm5785/Makefile.inc deleted file mode 100644 index 70fba1f218..0000000000 --- a/src/southbridge/broadcom/bcm5785/Makefile.inc +++ /dev/null @@ -1,11 +0,0 @@ -ifeq ($(CONFIG_SOUTHBRIDGE_BROADCOM_BCM5785),y) - -ramstage-y += bcm5785.c -ramstage-y += usb.c -ramstage-y += lpc.c -ramstage-y += sb_pci_main.c -ramstage-y += ide.c -ramstage-y += sata.c -ramstage-y += reset.c - -endif diff --git a/src/southbridge/broadcom/bcm5785/bcm5785.c b/src/southbridge/broadcom/bcm5785/bcm5785.c deleted file mode 100644 index ea77359257..0000000000 --- a/src/southbridge/broadcom/bcm5785/bcm5785.c +++ /dev/null @@ -1,99 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2005 AMD - * Written by Yinghai Lu for AMD. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include -#include -#include "bcm5785.h" - -void bcm5785_enable(struct device *dev) -{ - struct device *sb_pci_main_dev; - struct device *bus_dev; - // unsigned index; - - /* See if we are on the behind the pcix bridge */ - bus_dev = dev->bus->dev; - if ((bus_dev->vendor == PCI_VENDOR_ID_SERVERWORKS) && - (bus_dev->device == 0x0036)) // device under PCI-X Bridge - { - unsigned int devfn; - devfn = bus_dev->path.pci.devfn + (1 << 3); - sb_pci_main_dev = pcidev_path_behind(bus_dev->bus, devfn); - // index = ((dev->path.pci.devfn & ~7) >> 3) + 8; - } else if ((bus_dev->vendor == PCI_VENDOR_ID_SERVERWORKS) && - (bus_dev->device == 0x0104)) // device under PCI Bridge (under PCI-X) - { - unsigned int devfn; - devfn = bus_dev->bus->dev->path.pci.devfn + (1 << 3); - sb_pci_main_dev = pcidev_path_behind(bus_dev->bus->dev->bus, - devfn); - // index = ((dev->path.pci.devfn & ~7) >> 3) + 8; - } - else { // same bus - unsigned int devfn; - devfn = (dev->path.pci.devfn) & ~7; - if (dev->vendor == PCI_VENDOR_ID_SERVERWORKS) { - if (dev->device == 0x0036) //PCI-X Bridge - { devfn += (1<<3); } - else if (dev->device == 0x0223) // USB - { devfn -= (1<<3); } - } - sb_pci_main_dev = pcidev_path_behind(dev->bus, devfn); - // index = dev->path.pci.devfn & 7; - } - if (!sb_pci_main_dev) { - return; - } - - // get index now -#if 0 - unsigned int reg_old, reg; - if (index < 16) { - reg = reg_old = pci_read_config16(sb_pci_main_dev, 0x48); - reg &= ~(1 << index); - if (dev->enabled) { - reg |= (1 << index); - } - if (reg != reg_old) { - pci_write_config16(sb_pci_main_dev, 0x48, reg); - } - } - else if (index == 16) { - reg = reg_old = pci_read_config8(sb_pci_main_dev, 0x47); - reg &= ~(1 << 7); - if (!dev->enabled) { - reg |= (1 << 7); - } - if (reg != reg_old) { - pci_write_config8(sb_pci_main_dev, 0x47, reg); - } - } -#endif -} - -void bcm5785_set_subsystem(struct device *dev, unsigned int vendor, - unsigned int device) -{ - pci_write_config32(dev, 0x40, - ((device & 0xffff) << 16) | (vendor & 0xffff)); -} - -struct chip_operations southbridge_broadcom_bcm5785_ops = { - CHIP_NAME("Serverworks BCM5785 Southbridge") - .enable_dev = bcm5785_enable, -}; diff --git a/src/southbridge/broadcom/bcm5785/bcm5785.h b/src/southbridge/broadcom/bcm5785/bcm5785.h deleted file mode 100644 index db723dd8b3..0000000000 --- a/src/southbridge/broadcom/bcm5785/bcm5785.h +++ /dev/null @@ -1,31 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2005 AMD - * Written by Yinghai Lu for AMD. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef BCM5785_H -#define BCM5785_H - -#include -#include "chip.h" - -void bcm5785_enable(struct device *dev); -void enable_fid_change_on_sb(unsigned int sbbusn, unsigned int sbdn); - -void bcm5785_set_subsystem(struct device *dev, unsigned int vendor, - unsigned int device); - -void ldtstop_sb(void); - -#endif /* BCM5785_H */ diff --git a/src/southbridge/broadcom/bcm5785/bootblock.c b/src/southbridge/broadcom/bcm5785/bootblock.c deleted file mode 100644 index c14f47aa53..0000000000 --- a/src/southbridge/broadcom/bcm5785/bootblock.c +++ /dev/null @@ -1,54 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2005 AMD - * Written by Yinghai Lu for AMD. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include -#include - -#define PCI_ID(VENDOR_ID, DEVICE_ID) \ - ((((DEVICE_ID) & 0xFFFF) << 16) | ((VENDOR_ID) & 0xFFFF)) - -static pci_devfn_t pci_locate_device(unsigned int pci_id, pci_devfn_t dev) -{ - for (; dev <= PCI_DEV(255, 31, 7); dev += PCI_DEV(0, 0, 1)) { - unsigned int id; - id = pci_read_config32(dev, 0); - if (id == pci_id) - return dev; - } - return PCI_DEV_INVALID; -} - -/* Enable 4MB ROM access at 0xFFC00000 - 0xFFFFFFFF. */ -static void bcm5785_enable_rom(void) -{ - u8 byte; - pci_devfn_t dev; - - dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_SERVERWORKS, - PCI_DEVICE_ID_SERVERWORKS_BCM5785_SB_PCI_MAIN), 0); - - /* Set the 4MB enable bits. */ - byte = pci_read_config8(dev, 0x41); - byte |= 0x0e; - pci_write_config8(dev, 0x41, byte); -} - -static void bootblock_southbridge_init(void) -{ - bcm5785_enable_rom(); -} diff --git a/src/southbridge/broadcom/bcm5785/chip.h b/src/southbridge/broadcom/bcm5785/chip.h deleted file mode 100644 index 2c6573439c..0000000000 --- a/src/southbridge/broadcom/bcm5785/chip.h +++ /dev/null @@ -1,28 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2005 AMD - * Written by Yinghai Lu for AMD. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef BCM5785_CHIP_H -#define BCM5785_CHIP_H - -struct southbridge_broadcom_bcm5785_config -{ - unsigned int ide0_enable : 1; - unsigned int ide1_enable : 1; - unsigned int sata0_enable : 1; - unsigned int sata1_enable : 1; -}; - -#endif /* BCM5785_CHIP_H */ diff --git a/src/southbridge/broadcom/bcm5785/early_setup.c b/src/southbridge/broadcom/bcm5785/early_setup.c deleted file mode 100644 index b4d623b98c..0000000000 --- a/src/southbridge/broadcom/bcm5785/early_setup.c +++ /dev/null @@ -1,223 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2005 AMD - * Written by Yinghai Lu for AMD. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include -#include -#include "bcm5785.h" - -static void bcm5785_enable_lpc(void) -{ - uint8_t byte; - pci_devfn_t dev; - - dev = pci_locate_device(PCI_ID(0x1166, 0x0234), 0); - - /* LPC Control 0 */ - byte = pci_read_config8(dev, 0x44); - /* Serial 0 */ - byte |= 1 << 6; - pci_write_config8(dev, 0x44, byte); - - /* LPC Control 4 */ - byte = pci_read_config8(dev, 0x48); - /* superio port 0x2e/4e enable */ - byte |= (1 << 1) | (1 << 0); - pci_write_config8(dev, 0x48, byte); -} - -static void bcm5785_enable_wdt_port_cf9(void) -{ - pci_devfn_t dev; - uint32_t dword; - uint32_t dword_old; - - dev = pci_locate_device(PCI_ID(0x1166, 0x0205), 0); - - dword_old = pci_read_config32(dev, 0x4c); - dword = dword_old | (1 << 4); //enable Timer Func - if (dword != dword_old) - pci_write_config32(dev, 0x4c, dword); - - dword_old = pci_read_config32(dev, 0x6c); - dword = dword_old | (1 << 9); //unhide Timer Func in pci space - if (dword != dword_old) - pci_write_config32(dev, 0x6c, dword); - - dev = pci_locate_device(PCI_ID(0x1166, 0x0238), 0); - - /* enable cf9 */ - pci_write_config8(dev, 0x40, 1 << 2); -} - -unsigned int get_sbdn(unsigned int bus) -{ - pci_devfn_t dev; - - /* Find the device. - * There can only be one bcm5785 on a hypertransport chain/bus. - */ - dev = pci_locate_device_on_bus( - PCI_ID(0x1166, 0x0036), - bus); - - return (dev >> 15) & 0x1f; - -} - -#define SB_VFSMAF 0 - -void enable_fid_change_on_sb(unsigned int sbbusn, unsigned int sbdn) -{ - //ACPI Decode Enable - outb(0x0e, 0xcd6); - outb(1 << 3, 0xcd7); - - // set port to 0x2060 - outb(0x67, 0xcd6); - outb(0x60, 0xcd7); - outb(0x68, 0xcd6); - outb(0x20, 0xcd7); - - outb(0x69, 0xcd6); - outb(7, 0xcd7); - - outb(0x64, 0xcd6); - outb(9, 0xcd7); -} - -void ldtstop_sb(void) -{ - outb(1, 0x2060); -} - - -void do_board_reset(void) -{ - bcm5785_enable_wdt_port_cf9(); - - set_bios_reset(); - - /* full reset */ - outb(0x0a, 0x0cf9); - outb(0x0e, 0x0cf9); -} - -void do_soft_reset(void) -{ - bcm5785_enable_wdt_port_cf9(); - - set_bios_reset(); -#if 1 - /* link reset */ -// outb(0x02, 0x0cf9); - outb(0x06, 0x0cf9); -#endif -} - -static void bcm5785_enable_msg(void) -{ - pci_devfn_t dev; - uint32_t dword; - uint32_t dword_old; - uint8_t byte; - - dev = pci_locate_device(PCI_ID(0x1166, 0x0205), 0); - - byte = pci_read_config8(dev, 0x42); - byte = 1 << 1; //enable a20 - pci_write_config8(dev, 0x42, byte); - - dword_old = pci_read_config32(dev, 0x6c); - // bit 5: enable A20 Message - // bit 4: enable interrupt messages - // bit 3: enable reset init message - // bit 2: enable keyboard init message - // bit 1: enable upsteam messages - // bit 0: enable shutdowm message to init generation - - /* bit 1 and bit 4 must be set, otherwise - * interrupt msg will not be delivered to the processor - */ - dword = dword_old | (1 << 5) | (1 << 3) | (1 << 2) | (1 << 1) | (1 << 0); - if (dword != dword_old) - pci_write_config32(dev, 0x6c, dword); -} - -static void bcm5785_early_setup(void) -{ - uint8_t byte; - uint32_t dword; - pci_devfn_t dev; - -//F0 - // enable device on bcm5785 at first - dev = pci_locate_device(PCI_ID(0x1166, 0x0205), 0); - dword = pci_read_config32(dev, 0x64); - dword |= (1 << 15) | (1 << 11) | (1 << 3); // IOAPIC enable - dword |= 1 << 8; // USB enable - dword |= /* (1 << 27)|*/ 1 << 14; // IDE enable - pci_write_config32(dev, 0x64, dword); - - byte = pci_read_config8(dev, 0x84); - byte |= 1 << 0; // SATA enable - pci_write_config8(dev, 0x84, byte); - -// WDT and cf9 for later in ramstage to call hard_reset - bcm5785_enable_wdt_port_cf9(); - - bcm5785_enable_msg(); - - -// IDE related - //F0 - byte = pci_read_config8(dev, 0x4e); - byte |= 1 << 4; //enable IDE ext regs - pci_write_config8(dev, 0x4e, byte); - - //F1 - dev = pci_locate_device(PCI_ID(0x1166, 0x0214), 0); - byte = pci_read_config8(dev, 0x48); - byte &= ~1; // disable pri channel - pci_write_config8(dev, 0x48, byte); - pci_write_config8(dev, 0xb0, 0x01); - pci_write_config8(dev, 0xb2, 0x02); - byte = pci_read_config8(dev, 0x06); - byte |= 1 << 4; // so b0, b2 can not be changed from now - pci_write_config8(dev, 0x06, byte); - byte = pci_read_config8(dev, 0x49); - byte |= 1; // enable second channel - pci_write_config8(dev, 0x49, byte); - - //F2 - dev = pci_locate_device(PCI_ID(0x1166, 0x0234), 0); - - byte = pci_read_config8(dev, 0x40); - byte |= (1 << 3) | (1 << 2); // LPC Retry, LPC to PCI DMA enable - pci_write_config8(dev, 0x40, byte); - - pci_write_config32(dev, 0x60, 0x0000ffff); // LPC Memory hole start and end - -// USB related - pci_write_config8(dev, 0x90, 0x40); - pci_write_config8(dev, 0x92, 0x06); - pci_write_config8(dev, 0x9c, 0x7c); //PHY timinig register - pci_write_config8(dev, 0xa4, 0x02); //mask reg - low/full speed func - pci_write_config8(dev, 0xa5, 0x02); //mask reg - low/full speed func - pci_write_config8(dev, 0xa6, 0x00); //mask reg - high speed func - pci_write_config8(dev, 0xb4, 0x40); -} diff --git a/src/southbridge/broadcom/bcm5785/early_smbus.c b/src/southbridge/broadcom/bcm5785/early_smbus.c deleted file mode 100644 index 05e401dae1..0000000000 --- a/src/southbridge/broadcom/bcm5785/early_smbus.c +++ /dev/null @@ -1,61 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2005 AMD - * Written by Yinghai Lu for AMD. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include - -#include "smbus.h" - -#define SMBUS_IO_BASE 0x1000 - -static void enable_smbus(void) -{ - pci_devfn_t dev; - dev = pci_locate_device(PCI_ID(0x1166, 0x0205), 0); // 0x0201? - - if (dev == PCI_DEV_INVALID) { - die("SMBUS controller not found\n"); - } - - printk(BIOS_DEBUG, "SMBus controller enabled\n"); - /* set smbus iobase */ - pci_write_config32(dev, 0x90, SMBUS_IO_BASE | 1); - /* Set smbus iospace enable */ - pci_write_config8(dev, 0xd2, 0x03); - /* clear any lingering errors, so the transaction will run */ - outb(inb(SMBUS_IO_BASE + SMBHSTSTAT), SMBUS_IO_BASE + SMBHSTSTAT); -} - -static inline int smbus_recv_byte(unsigned int device) -{ - return do_smbus_recv_byte(SMBUS_IO_BASE, device); -} - -static inline int smbus_send_byte(unsigned int device, unsigned char val) -{ - return do_smbus_send_byte(SMBUS_IO_BASE, device, val); -} - -static inline int smbus_read_byte(unsigned int device, unsigned int address) -{ - return do_smbus_read_byte(SMBUS_IO_BASE, device, address); -} - -static inline int smbus_write_byte(unsigned int device, unsigned int address, unsigned char val) -{ - return do_smbus_write_byte(SMBUS_IO_BASE, device, address, val); -} diff --git a/src/southbridge/broadcom/bcm5785/ide.c b/src/southbridge/broadcom/bcm5785/ide.c deleted file mode 100644 index c143c22a53..0000000000 --- a/src/southbridge/broadcom/bcm5785/ide.c +++ /dev/null @@ -1,55 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2005 AMD - * Written by Yinghai Lu for AMD. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include -#include "bcm5785.h" - -static void bcm5785_ide_read_resources(struct device *dev) -{ - /* Get the normal pci resources of this device */ - pci_dev_read_resources(dev); - - /* BAR */ - pci_get_resource(dev, 0x64); - - compact_resources(dev); -} - -static void ide_init(struct device *dev) -{ -} - -static struct pci_operations lops_pci = { - .set_subsystem = bcm5785_set_subsystem, -}; - -static struct device_operations ide_ops = { - .read_resources = bcm5785_ide_read_resources, - .set_resources = pci_dev_set_resources, - .enable_resources = pci_dev_enable_resources, - .init = ide_init, - .scan_bus = 0, -// .enable = bcm5785_enable, - .ops_pci = &lops_pci, -}; - -static const struct pci_driver ide_driver __pci_driver = { - .ops = &ide_ops, - .vendor = PCI_VENDOR_ID_SERVERWORKS, - .device = PCI_DEVICE_ID_SERVERWORKS_BCM5785_IDE, -}; diff --git a/src/southbridge/broadcom/bcm5785/lpc.c b/src/southbridge/broadcom/bcm5785/lpc.c deleted file mode 100644 index 5ac15e0fd0..0000000000 --- a/src/southbridge/broadcom/bcm5785/lpc.c +++ /dev/null @@ -1,136 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2005 AMD - * Written by Yinghai Lu for AMD. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include "bcm5785.h" - -static void lpc_init(struct device *dev) -{ - /* Initialize the real time clock */ - cmos_init(0); - - /* Initialize isa dma */ - isa_dma_init(); -} - -static void bcm5785_lpc_read_resources(struct device *dev) -{ - struct resource *res; - - /* Get the normal pci resources of this device */ - pci_dev_read_resources(dev); - - /* Add an extra subtractive resource for both memory and I/O. */ - res = new_resource(dev, IOINDEX_SUBTRACTIVE(0, 0)); - res->base = 0; - res->size = 0x1000; - res->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE | - IORESOURCE_ASSIGNED | IORESOURCE_FIXED; - - res = new_resource(dev, IOINDEX_SUBTRACTIVE(1, 0)); - res->base = 0xff800000; - res->size = 0x00800000; /* 8 MB for flash */ - res->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE | - IORESOURCE_ASSIGNED | IORESOURCE_FIXED; - - res = new_resource(dev, 3); /* IOAPIC */ - res->base = IO_APIC_ADDR; - res->size = 0x00001000; - res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; -} - -/** - * Enable resources for children devices. - * - * @param dev The device whos children's resources are to be enabled. - */ -static void bcm5785_lpc_enable_childrens_resources(struct device *dev) -{ - struct bus *link; - uint32_t reg; - - reg = pci_read_config8(dev, 0x44); - - for (link = dev->link_list; link; link = link->next) { - struct device *child; - for (child = link->children; child; child = child->sibling) { - if (child->enabled && (child->path.type == DEVICE_PATH_PNP)) { - struct resource *res; - for (res = child->resource_list; res; res = res->next) { - unsigned long base, end; // don't need long long - if (!(res->flags & IORESOURCE_IO)) continue; - base = res->base; - end = resource_end(res); - printk(BIOS_DEBUG, "bcm5785lpc decode:%s, base=0x%08lx, end=0x%08lx\n",dev_path(child),base, end); - switch (base) { - case 0x60: //KBC - case 0x64: - reg |= (1<<29); break; - case 0x3f8: // COM1 - reg |= (1<<6); break; - case 0x2f8: // COM2 - reg |= (1<<7); break; - case 0x378: // Parallel 1 - reg |= (1<<0); break; - case 0x3f0: // FD0 - reg |= (1<<26); break; - case 0x220: // Audio 0 - reg |= (1<<14); break; - case 0x300: // MIDI 0 - reg |= (1<<18); break; - } - } - } - } - } - pci_write_config32(dev, 0x44, reg); - - -} - -static void bcm5785_lpc_enable_resources(struct device *dev) -{ - pci_dev_enable_resources(dev); - bcm5785_lpc_enable_childrens_resources(dev); -} - -static struct pci_operations lops_pci = { - .set_subsystem = bcm5785_set_subsystem, -}; - -static struct device_operations lpc_ops = { - .read_resources = bcm5785_lpc_read_resources, - .set_resources = pci_dev_set_resources, - .enable_resources = bcm5785_lpc_enable_resources, - .init = lpc_init, - .scan_bus = scan_static_bus, -// .enable = bcm5785_enable, - .ops_pci = &lops_pci, -}; - -static const struct pci_driver lpc_driver __pci_driver = { - .ops = &lpc_ops, - .vendor = PCI_VENDOR_ID_SERVERWORKS, - .device = PCI_DEVICE_ID_SERVERWORKS_BCM5785_LPC, -}; diff --git a/src/southbridge/broadcom/bcm5785/reset.c b/src/southbridge/broadcom/bcm5785/reset.c deleted file mode 100644 index ad3ea8f5ba..0000000000 --- a/src/southbridge/broadcom/bcm5785/reset.c +++ /dev/null @@ -1,31 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2005 AMD - * Written by Yinghai Lu for AMD. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#define __SIMPLE_DEVICE__ - -#include -#include - -#include "../../../northbridge/amd/amdk8/reset_test.c" - -void do_board_reset(void) -{ - set_bios_reset(); - /* Try rebooting through port 0xcf9 */ - /* Actually it is not a real hard_reset --- it only reset coherent link table, but not reset link freq and width */ - outb((0 <<3)|(0<<2)|(1<<1), 0xcf9); - outb((0 <<3)|(1<<2)|(1<<1), 0xcf9); -} diff --git a/src/southbridge/broadcom/bcm5785/sata.c b/src/southbridge/broadcom/bcm5785/sata.c deleted file mode 100644 index cdd4295531..0000000000 --- a/src/southbridge/broadcom/bcm5785/sata.c +++ /dev/null @@ -1,89 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2005 AMD - * Written by Yinghai Lu for AMD. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include -#include -#include -#include -#include -#include "bcm5785.h" - -static void sata_init(struct device *dev) -{ - uint8_t byte; - - u8 *mmio; - struct resource *res; - u8 *mmio_base; - int i; - - if (!(dev->path.pci.devfn & 7)) { // only set it in Func0 - byte = pci_read_config8(dev, 0x78); - byte |= (1<<7); - pci_write_config8(dev, 0x78, byte); - - res = find_resource(dev, 0x24); - mmio_base = res2mmio(res, 0, 3); - - write32(mmio_base + 0x10f0, 0x40000001); - write32(mmio_base + 0x8c, 0x00ff2007); - mdelay(10); - write32(mmio_base + 0x8c, 0x78592009); - mdelay(10); - write32(mmio_base + 0x8c, 0x00082004); - mdelay(10); - write32(mmio_base + 0x8c, 0x00002004); - mdelay(10); - - //init PHY - - printk(BIOS_DEBUG, "init PHY...\n"); - for (i=0; i<4; i++) { - mmio = (u8 *)(uintptr_t)(res->base + 0x100 * i); - byte = read8(mmio + 0x40); - printk(BIOS_DEBUG, "port %d PHY status = %02x\n", i, byte); - if (byte & 0x4) {// bit 2 is set - byte = read8(mmio+0x48); - write8(mmio + 0x48, byte | 1); - write8(mmio + 0x48, byte & (~1)); - byte = read8(mmio + 0x40); - printk(BIOS_DEBUG, "after reset port %d PHY status = %02x\n", i, byte); - } - } - } -} - -static struct pci_operations lops_pci = { - .set_subsystem = bcm5785_set_subsystem, -}; - -static struct device_operations sata_ops = { - .read_resources = pci_dev_read_resources, - .set_resources = pci_dev_set_resources, - .enable_resources = pci_dev_enable_resources, -// .enable = bcm5785_enable, - .init = sata_init, - .scan_bus = 0, - .ops_pci = &lops_pci, -}; - -static const struct pci_driver sata0_driver __pci_driver = { - .ops = &sata_ops, - .vendor = PCI_VENDOR_ID_SERVERWORKS, - .device = PCI_DEVICE_ID_SERVERWORKS_BCM5785_SATA, -}; diff --git a/src/southbridge/broadcom/bcm5785/sb_pci_main.c b/src/southbridge/broadcom/bcm5785/sb_pci_main.c deleted file mode 100644 index 837ce42b4b..0000000000 --- a/src/southbridge/broadcom/bcm5785/sb_pci_main.c +++ /dev/null @@ -1,155 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2005 AMD - * Written by Yinghai Lu for AMD. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include "bcm5785.h" -#include "smbus.h" - -#define NMI_OFF 0 - -static void sb_init(struct device *dev) -{ - uint8_t byte; - uint8_t byte_old; - int nmi_option; - - /* Set up NMI on errors */ - byte = inb(0x70); // RTC70 - byte_old = byte; - nmi_option = NMI_OFF; - get_option(&nmi_option, "nmi"); - if (nmi_option) { - byte &= ~(1 << 7); /* set NMI */ - } else { - byte |= (1 << 7); // Can not mask NMI from PCI-E and NMI_NOW - } - if (byte != byte_old) { - outb(byte, 0x70); - } - - -} - -static void bcm5785_sb_read_resources(struct device *dev) -{ - struct resource *res; - - /* Get the normal pci resources of this device */ - pci_dev_read_resources(dev); - /* Get Resource for SMBUS */ - pci_get_resource(dev, 0x90); - - compact_resources(dev); - - /* Add an extra subtractive resource for both memory and I/O */ - res = new_resource(dev, IOINDEX_SUBTRACTIVE(0, 0)); - res->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED; - - res = new_resource(dev, IOINDEX_SUBTRACTIVE(1, 0)); - res->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED; - -} - -static int lsmbus_recv_byte(struct device *dev) -{ - unsigned int device; - struct resource *res; - struct bus *pbus; - - device = dev->path.i2c.device; - pbus = get_pbus_smbus(dev); - - res = find_resource(pbus->dev, 0x90); - - return do_smbus_recv_byte(res->base, device); -} - -static int lsmbus_send_byte(struct device *dev, uint8_t val) -{ - unsigned int device; - struct resource *res; - struct bus *pbus; - - device = dev->path.i2c.device; - pbus = get_pbus_smbus(dev); - - res = find_resource(pbus->dev, 0x90); - - return do_smbus_send_byte(res->base, device, val); -} - -static int lsmbus_read_byte(struct device *dev, uint8_t address) -{ - unsigned int device; - struct resource *res; - struct bus *pbus; - - device = dev->path.i2c.device; - pbus = get_pbus_smbus(dev); - - res = find_resource(pbus->dev, 0x90); - - return do_smbus_read_byte(res->base, device, address); -} - -static int lsmbus_write_byte(struct device *dev, uint8_t address, uint8_t val) -{ - unsigned int device; - struct resource *res; - struct bus *pbus; - - device = dev->path.i2c.device; - pbus = get_pbus_smbus(dev); - - res = find_resource(pbus->dev, 0x90); - - return do_smbus_write_byte(res->base, device, address, val); -} - -static struct smbus_bus_operations lops_smbus_bus = { - .recv_byte = lsmbus_recv_byte, - .send_byte = lsmbus_send_byte, - .read_byte = lsmbus_read_byte, - .write_byte = lsmbus_write_byte, -}; - -static struct pci_operations lops_pci = { - .set_subsystem = pci_dev_set_subsystem, -}; - -static struct device_operations sb_ops = { - .read_resources = bcm5785_sb_read_resources, - .set_resources = pci_dev_set_resources, - .enable_resources = pci_dev_enable_resources, - .init = sb_init, - .scan_bus = scan_smbus, -// .enable = bcm5785_enable, - .ops_pci = &lops_pci, - .ops_smbus_bus = &lops_smbus_bus, -}; - -static const struct pci_driver sb_driver __pci_driver = { - .ops = &sb_ops, - .vendor = PCI_VENDOR_ID_SERVERWORKS, - .device = PCI_DEVICE_ID_SERVERWORKS_BCM5785_SB_PCI_MAIN, -}; diff --git a/src/southbridge/broadcom/bcm5785/smbus.h b/src/southbridge/broadcom/bcm5785/smbus.h deleted file mode 100644 index 40ed774b72..0000000000 --- a/src/southbridge/broadcom/bcm5785/smbus.h +++ /dev/null @@ -1,193 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2005 AMD - * Written by Yinghai Lu for AMD. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include - -#define SMBHSTSTAT 0x0 -#define SMBSLVSTAT 0x1 -#define SMBHSTCTRL 0x2 -#define SMBHSTCMD 0x3 -#define SMBHSTADDR 0x4 -#define SMBHSTDAT0 0x5 -#define SMBHSTDAT1 0x6 -#define SMBHSTBLKDAT 0x7 - -#define SMBSLVCTRL 0x8 -#define SMBSLVCMD_SHADOW 0x9 -#define SMBSLVEVT 0xa -#define SMBSLVDAT 0xc - - -/* Between 1-10 seconds, We should never timeout normally - * Longer than this is just painful when a timeout condition occurs. - */ -#define SMBUS_TIMEOUT (100*1000*10) - -static inline void smbus_delay(void) -{ - outb(0x80, 0x80); -} - -static int smbus_wait_until_ready(unsigned int smbus_io_base) -{ - unsigned long loops; - loops = SMBUS_TIMEOUT; - do { - unsigned char val; - val = inb(smbus_io_base + SMBHSTSTAT); - val &= 0x1f; - if (val == 0) { // ready now - return 0; - } - outb(val, smbus_io_base + SMBHSTSTAT); - } while (--loops); - return -2; // time out -} - -static int smbus_wait_until_done(unsigned int smbus_io_base) -{ - unsigned long loops; - loops = SMBUS_TIMEOUT; - do { - unsigned char val; - - val = inb(smbus_io_base + SMBHSTSTAT); - val &= 0x1f; // mask off reserved bits - if (val & 0x1c) { - return -5; // error - } - if (val == 0x02) { - outb(val, smbus_io_base + SMBHSTSTAT); // clear status - return 0; // - } - } while (--loops); - return -3; // timeout -} - -static int do_smbus_recv_byte(unsigned int smbus_io_base, unsigned int device) -{ - uint8_t byte; - - if (smbus_wait_until_ready(smbus_io_base) < 0) { - return -2; // not ready - } - - /* set the device I'm talking to */ - outb(((device & 0x7f) << 1)|1 , smbus_io_base + SMBHSTADDR); - - byte = inb(smbus_io_base + SMBHSTCTRL); - byte &= 0xe3; // Clear [4:2] - byte |= (1<<2) | (1<<6); // Byte data read/write command, start the command - outb(byte, smbus_io_base + SMBHSTCTRL); - - /* poll for transaction completion */ - if (smbus_wait_until_done(smbus_io_base) < 0) { - return -3; // timeout or error - } - - /* read results of transaction */ - byte = inb(smbus_io_base + SMBHSTCMD); - - return byte; -} - -static int do_smbus_send_byte(unsigned int smbus_io_base, unsigned int device, unsigned char val) -{ - uint8_t byte; - - if (smbus_wait_until_ready(smbus_io_base) < 0) { - return -2; // not ready - } - - /* set the command... */ - outb(val, smbus_io_base + SMBHSTCMD); - - /* set the device I'm talking to */ - outb(((device & 0x7f) << 1)|0 , smbus_io_base + SMBHSTADDR); - - byte = inb(smbus_io_base + SMBHSTCTRL); - byte &= 0xe3; // Clear [4:2] - byte |= (1<<2) | (1<<6); // Byte data read/write command, start the command - outb(byte, smbus_io_base + SMBHSTCTRL); - - /* poll for transaction completion */ - if (smbus_wait_until_done(smbus_io_base) < 0) { - return -3; // timeout or error - } - - return 0; -} - -static int do_smbus_read_byte(unsigned int smbus_io_base, unsigned int device, unsigned int address) -{ - uint8_t byte; - - if (smbus_wait_until_ready(smbus_io_base) < 0) { - return -2; // not ready - } - - /* set the command/address... */ - outb(address & 0xff, smbus_io_base + SMBHSTCMD); - - /* set the device I'm talking to */ - outb(((device & 0x7f) << 1)|1 , smbus_io_base + SMBHSTADDR); - - byte = inb(smbus_io_base + SMBHSTCTRL); - byte &= 0xe3; // Clear [4:2] - byte |= (1<<3) | (1<<6); // Byte data read/write command, start the command - outb(byte, smbus_io_base + SMBHSTCTRL); - - /* poll for transaction completion */ - if (smbus_wait_until_done(smbus_io_base) < 0) { - return -3; // timeout or error - } - - /* read results of transaction */ - byte = inb(smbus_io_base + SMBHSTDAT0); - - return byte; -} - -static int do_smbus_write_byte(unsigned int smbus_io_base, unsigned int device, unsigned int address, unsigned char val) -{ - uint8_t byte; - - if (smbus_wait_until_ready(smbus_io_base) < 0) { - return -2; // not ready - } - - /* set the command/address... */ - outb(address & 0xff, smbus_io_base + SMBHSTCMD); - - /* set the device I'm talking to */ - outb(((device & 0x7f) << 1)|0 , smbus_io_base + SMBHSTADDR); - - /* output value */ - outb(val, smbus_io_base + SMBHSTDAT0); - - byte = inb(smbus_io_base + SMBHSTCTRL); - byte &= 0xe3; // Clear [4:2] - byte |= (1<<3) | (1<<6); // Byte data read/write command, start the command - outb(byte, smbus_io_base + SMBHSTCTRL); - - /* poll for transaction completion */ - if (smbus_wait_until_done(smbus_io_base) < 0) { - return -3; // timeout or error - } - - return 0; -} diff --git a/src/southbridge/broadcom/bcm5785/usb.c b/src/southbridge/broadcom/bcm5785/usb.c deleted file mode 100644 index ef374ad482..0000000000 --- a/src/southbridge/broadcom/bcm5785/usb.c +++ /dev/null @@ -1,53 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2005 AMD - * Written by Yinghai Lu for AMD. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include -#include -#include "bcm5785.h" - -static void usb_init(struct device *dev) -{ - uint32_t dword; - - dword = pci_read_config32(dev, 0x04); - dword |= (1<<2)|(1<<1)|(1<<0); - pci_write_config32(dev, 0x04, dword); - - pci_write_config8(dev, 0x41, 0x00); // Serversworks said - -} - -static struct pci_operations lops_pci = { - .set_subsystem = bcm5785_set_subsystem, -}; - -static struct device_operations usb_ops = { - .read_resources = pci_dev_read_resources, - .set_resources = pci_dev_set_resources, - .enable_resources = pci_dev_enable_resources, - .init = usb_init, -// .enable = bcm5785_enable, - .scan_bus = 0, - .ops_pci = &lops_pci, -}; - -static const struct pci_driver usb_driver __pci_driver = { - .ops = &usb_ops, - .vendor = PCI_VENDOR_ID_SERVERWORKS, - .device = PCI_DEVICE_ID_SERVERWORKS_BCM5785_USB, -}; From 87bc7554478bc7a723baef0aedf5ad42e7747499 Mon Sep 17 00:00:00 2001 From: Arthur Heymans Date: Tue, 19 Nov 2019 17:27:30 +0100 Subject: [PATCH 0298/1242] sb/broadcom/bcm21000: Drop support MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Relocatable ramstage, postcar stage and C_ENVIRONMENT_BOOTBLOCK are now mandatory features, which platforms using this code lack. Change-Id: I5e9250a7c7adb7dffd64422637ba760155d966d2 Signed-off-by: Arthur Heymans Reviewed-on: https://review.coreboot.org/c/coreboot/+/36971 Reviewed-by: Kyösti Mälkki Reviewed-by: Angel Pons Reviewed-by: HAOUAS Elyes Tested-by: build bot (Jenkins) --- src/southbridge/broadcom/bcm21000/Kconfig | 2 - .../broadcom/bcm21000/Makefile.inc | 5 -- src/southbridge/broadcom/bcm21000/pcie.c | 75 ------------------- 3 files changed, 82 deletions(-) delete mode 100644 src/southbridge/broadcom/bcm21000/Kconfig delete mode 100644 src/southbridge/broadcom/bcm21000/Makefile.inc delete mode 100644 src/southbridge/broadcom/bcm21000/pcie.c diff --git a/src/southbridge/broadcom/bcm21000/Kconfig b/src/southbridge/broadcom/bcm21000/Kconfig deleted file mode 100644 index 1131684d52..0000000000 --- a/src/southbridge/broadcom/bcm21000/Kconfig +++ /dev/null @@ -1,2 +0,0 @@ -config SOUTHBRIDGE_BROADCOM_BCM21000 - bool diff --git a/src/southbridge/broadcom/bcm21000/Makefile.inc b/src/southbridge/broadcom/bcm21000/Makefile.inc deleted file mode 100644 index d298c8e008..0000000000 --- a/src/southbridge/broadcom/bcm21000/Makefile.inc +++ /dev/null @@ -1,5 +0,0 @@ -ifeq ($(CONFIG_SOUTHBRIDGE_BROADCOM_BCM21000),y) - -ramstage-y += pcie.c - -endif diff --git a/src/southbridge/broadcom/bcm21000/pcie.c b/src/southbridge/broadcom/bcm21000/pcie.c deleted file mode 100644 index ab52029729..0000000000 --- a/src/southbridge/broadcom/bcm21000/pcie.c +++ /dev/null @@ -1,75 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2009 University of Heidelberg - * Written by Mondrian Nuessle for - * University of Heidelberg. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include -#include -#include - -static void pcie_init(struct device *dev) -{ - /* Enable pci error detecting */ - uint32_t dword; - uint32_t msicap; - - printk(BIOS_DEBUG, "PCIE enable.... dev= %s\n",dev_path(dev)); - - /* System error enable */ - dword = pci_read_config32(dev, 0x04); - dword |= (1<<8); /* System error enable */ - dword |= (1<<30); /* Clear possible errors */ - pci_write_config32(dev, 0x04, dword); - - /* enable MSI on PCIE: */ - msicap = pci_read_config32(dev, 0xa0); - msicap |= (1<<16); /* enable MSI*/ - pci_write_config32(dev, 0xa0, msicap); -} - -static struct pci_operations lops_pci = { - .set_subsystem = 0, -}; - -static struct device_operations pcie_ops = { - .read_resources = pci_bus_read_resources, - .set_resources = pci_dev_set_resources, - .enable_resources = pci_bus_enable_resources, - .init = pcie_init, - .scan_bus = pci_scan_bridge, - .reset_bus = pci_bus_reset, - .ops_pci = &lops_pci, -}; - -static const struct pci_driver pcie_driver1 __pci_driver = { - .ops = &pcie_ops, - .vendor = PCI_VENDOR_ID_SERVERWORKS, - .device = PCI_DEVICE_ID_SERVERWORKS_BCM21000_EXB0, -}; - -static const struct pci_driver pcie_driver2 __pci_driver = { - .ops = &pcie_ops, - .vendor = PCI_VENDOR_ID_SERVERWORKS, - .device = PCI_DEVICE_ID_SERVERWORKS_BCM21000_EXB1, -}; - -static const struct pci_driver pcie_driver3 __pci_driver = { - .ops = &pcie_ops, - .vendor = PCI_VENDOR_ID_SERVERWORKS, - .device = PCI_DEVICE_ID_SERVERWORKS_BCM21000_EXB2, -}; From 185691eedb37ae26f7829d762cd476395be57f5d Mon Sep 17 00:00:00 2001 From: Arthur Heymans Date: Tue, 19 Nov 2019 17:28:05 +0100 Subject: [PATCH 0299/1242] sb/nvidia/ck804: Drop support MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Relocatable ramstage, postcar stage and C_ENVIRONMENT_BOOTBLOCK are now mandatory features, which platforms using this code lack. Change-Id: I56cb6d0a04056b10af1e53afb697883329235c87 Signed-off-by: Arthur Heymans Reviewed-on: https://review.coreboot.org/c/coreboot/+/36972 Reviewed-by: Kyösti Mälkki Reviewed-by: Angel Pons Reviewed-by: HAOUAS Elyes Tested-by: build bot (Jenkins) --- src/southbridge/nvidia/ck804/Kconfig | 41 -- src/southbridge/nvidia/ck804/Makefile.inc | 28 - src/southbridge/nvidia/ck804/ac97.c | 50 -- src/southbridge/nvidia/ck804/acpi/ck804.asl | 631 ------------------ src/southbridge/nvidia/ck804/bootblock.c | 38 -- src/southbridge/nvidia/ck804/chip.h | 32 - src/southbridge/nvidia/ck804/ck804.c | 196 ------ src/southbridge/nvidia/ck804/ck804.h | 31 - .../nvidia/ck804/early_setup_car.c | 387 ----------- src/southbridge/nvidia/ck804/early_setup_ss.h | 216 ------ src/southbridge/nvidia/ck804/early_smbus.c | 77 --- src/southbridge/nvidia/ck804/early_smbus.h | 18 - .../nvidia/ck804/enable_usbdebug.c | 43 -- src/southbridge/nvidia/ck804/fadt.c | 157 ----- src/southbridge/nvidia/ck804/ht.c | 74 -- src/southbridge/nvidia/ck804/ide.c | 73 -- src/southbridge/nvidia/ck804/lpc.c | 348 ---------- src/southbridge/nvidia/ck804/nic.c | 126 ---- src/southbridge/nvidia/ck804/pci.c | 80 --- src/southbridge/nvidia/ck804/pcie.c | 46 -- src/southbridge/nvidia/ck804/reset.c | 30 - src/southbridge/nvidia/ck804/romstrap.S | 55 -- src/southbridge/nvidia/ck804/romstrap.ld | 22 - src/southbridge/nvidia/ck804/sata.c | 146 ---- src/southbridge/nvidia/ck804/smbus.c | 101 --- src/southbridge/nvidia/ck804/smbus.h | 185 ----- src/southbridge/nvidia/ck804/usb.c | 57 -- src/southbridge/nvidia/ck804/usb2.c | 45 -- 28 files changed, 3333 deletions(-) delete mode 100644 src/southbridge/nvidia/ck804/Kconfig delete mode 100644 src/southbridge/nvidia/ck804/Makefile.inc delete mode 100644 src/southbridge/nvidia/ck804/ac97.c delete mode 100644 src/southbridge/nvidia/ck804/acpi/ck804.asl delete mode 100644 src/southbridge/nvidia/ck804/bootblock.c delete mode 100644 src/southbridge/nvidia/ck804/chip.h delete mode 100644 src/southbridge/nvidia/ck804/ck804.c delete mode 100644 src/southbridge/nvidia/ck804/ck804.h delete mode 100644 src/southbridge/nvidia/ck804/early_setup_car.c delete mode 100644 src/southbridge/nvidia/ck804/early_setup_ss.h delete mode 100644 src/southbridge/nvidia/ck804/early_smbus.c delete mode 100644 src/southbridge/nvidia/ck804/early_smbus.h delete mode 100644 src/southbridge/nvidia/ck804/enable_usbdebug.c delete mode 100644 src/southbridge/nvidia/ck804/fadt.c delete mode 100644 src/southbridge/nvidia/ck804/ht.c delete mode 100644 src/southbridge/nvidia/ck804/ide.c delete mode 100644 src/southbridge/nvidia/ck804/lpc.c delete mode 100644 src/southbridge/nvidia/ck804/nic.c delete mode 100644 src/southbridge/nvidia/ck804/pci.c delete mode 100644 src/southbridge/nvidia/ck804/pcie.c delete mode 100644 src/southbridge/nvidia/ck804/reset.c delete mode 100644 src/southbridge/nvidia/ck804/romstrap.S delete mode 100644 src/southbridge/nvidia/ck804/romstrap.ld delete mode 100644 src/southbridge/nvidia/ck804/sata.c delete mode 100644 src/southbridge/nvidia/ck804/smbus.c delete mode 100644 src/southbridge/nvidia/ck804/smbus.h delete mode 100644 src/southbridge/nvidia/ck804/usb.c delete mode 100644 src/southbridge/nvidia/ck804/usb2.c diff --git a/src/southbridge/nvidia/ck804/Kconfig b/src/southbridge/nvidia/ck804/Kconfig deleted file mode 100644 index f931d4892b..0000000000 --- a/src/southbridge/nvidia/ck804/Kconfig +++ /dev/null @@ -1,41 +0,0 @@ -config SOUTHBRIDGE_NVIDIA_CK804 - bool - select HAVE_USBDEBUG - select IOAPIC - select HAVE_POWER_STATE_AFTER_FAILURE - -if SOUTHBRIDGE_NVIDIA_CK804 - -config BOOTBLOCK_SOUTHBRIDGE_INIT - string - default "southbridge/nvidia/ck804/bootblock.c" - -config EHCI_BAR - hex - default 0xfef00000 - -config CK804_USE_NIC - bool - default n - -config CK804_USE_ACI - bool - default n - -config CK804_PCI_E_X - int - default 4 - -config CK804B_PCI_E_X - int - default 4 - -config CK804_PCIE_PME_WAKE - bool "Enable system wake on PCIe PME# signal" - default n - -config HPET_MIN_TICKS - hex - default 0xfa - -endif diff --git a/src/southbridge/nvidia/ck804/Makefile.inc b/src/southbridge/nvidia/ck804/Makefile.inc deleted file mode 100644 index e74c70b180..0000000000 --- a/src/southbridge/nvidia/ck804/Makefile.inc +++ /dev/null @@ -1,28 +0,0 @@ -ifeq ($(CONFIG_SOUTHBRIDGE_NVIDIA_CK804),y) - -ramstage-y += ck804.c -ramstage-y += usb.c -ramstage-y += lpc.c -ramstage-y += smbus.c -ramstage-y += ide.c -ramstage-y += sata.c -ramstage-y += usb2.c -ramstage-y += ac97.c -ramstage-y += nic.c -ramstage-y += pci.c -ramstage-y += pcie.c -ramstage-y += ht.c - -ramstage-y += reset.c - -ramstage-$(CONFIG_HAVE_ACPI_TABLES) += fadt.c - -bootblock-y += enable_usbdebug.c -romstage-y += enable_usbdebug.c -ramstage-y += enable_usbdebug.c -romstage-y += early_smbus.c - -bootblock-y += romstrap.ld -bootblock-y += romstrap.S - -endif diff --git a/src/southbridge/nvidia/ck804/ac97.c b/src/southbridge/nvidia/ck804/ac97.c deleted file mode 100644 index 28c5e74b2e..0000000000 --- a/src/southbridge/nvidia/ck804/ac97.c +++ /dev/null @@ -1,50 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2004 Tyan Computer - * Written by Yinghai Lu for Tyan Computer. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include -#include "chip.h" - -static struct device_operations ac97audio_ops = { - .read_resources = pci_dev_read_resources, - .set_resources = pci_dev_set_resources, - .enable_resources = pci_dev_enable_resources, - .init = 0, - .scan_bus = 0, - .ops_pci = &ck804_pci_ops, -}; - -static const struct pci_driver ac97audio_driver __pci_driver = { - .ops = &ac97audio_ops, - .vendor = PCI_VENDOR_ID_NVIDIA, - .device = PCI_DEVICE_ID_NVIDIA_CK804_ACI, -}; - -static struct device_operations ac97modem_ops = { - .read_resources = pci_dev_read_resources, - .set_resources = pci_dev_set_resources, - .enable_resources = pci_dev_enable_resources, - .init = 0, - .scan_bus = 0, - .ops_pci = &ck804_pci_ops, -}; - -static const struct pci_driver ac97modem_driver __pci_driver = { - .ops = &ac97modem_ops, - .vendor = PCI_VENDOR_ID_NVIDIA, - .device = PCI_DEVICE_ID_NVIDIA_CK804_MCI, -}; diff --git a/src/southbridge/nvidia/ck804/acpi/ck804.asl b/src/southbridge/nvidia/ck804/acpi/ck804.asl deleted file mode 100644 index 4a83b8481e..0000000000 --- a/src/southbridge/nvidia/ck804/acpi/ck804.asl +++ /dev/null @@ -1,631 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -Device (LPCB) { - Name (_ADR, 0x00010000) - OperationRegion (LPC0, PCI_Config, 0x00, 0x100) - Field (LPC0, AnyAcc, NoLock, Preserve) { - Offset (0x7c), - INTA, 4, INTB, 4, - INTC, 4, INTD, 4, - INTE, 4, INTF, 4, - INTG, 4, INTH, 4, - - INTI, 4, INTJ, 4, - INTK, 4, INTL, 4, - INTM, 4, INTN, 4, - INTO, 4, INTP, 4, - - INTQ, 4, INTR, 4, - INTS, 4, INTT, 4, - INTU, 4, INTV, 4, - INTW, 4, INTX, 4, - } -} - -/* set "A", 8259 interrupts */ -Name (PRSA, ResourceTemplate () { - IRQ(Level, ActiveLow, Shared) {5, 7, 10, 11} -}) -Method (CRSA, 1, Serialized) { - Name (LRTL, ResourceTemplate() { - IRQ(Level, ActiveLow, Shared) {} - }) - CreateWordField(LRTL, 1, LIRQ) - ShiftLeft(1, Arg0, LIRQ) - Return (LRTL) -} -Method (SRSA, 1, Serialized) { - CreateWordField(Arg0, 1, LIRQ) - FindSetRightBit(LIRQ, Local0) - Decrement(Local0) - Return (Local0) -} - -/* set "B", external (PCI) APIC interrupts */ -Name (PRSB, ResourceTemplate () { - Interrupt (ResourceConsumer, Level, ActiveLow, Shared, ,,) { - 16, 17, 18, 19, - } -}) -Method (CRSB, 1, Serialized) { - Name (LRTL, ResourceTemplate() { - Interrupt (ResourceConsumer, Level, ActiveLow, Shared, ,,) { 0 } - }) - CreateDWordField (LRTL, 5, LIRQ) - If (LEqual (Arg0, 8)) { - Store (16, LIRQ) - } ElseIf (LEqual (Arg0, 1)) { - Store (17, LIRQ) - } ElseIf (LEqual (Arg0, 2)) { - Store (18, LIRQ) - } ElseIf (LEqual (Arg0, 13)) { - Store (19, LIRQ) - } Else { - Store (0, LIRQ) - } - Return (LRTL) -} -Method (SRSB, 1, Serialized) { - CreateDWordField(Arg0, 5, LIRQ) - If (LEqual (LIRQ, 16)) { - Return (8) - } ElseIf (LEqual (LIRQ, 17)) { - Return (1) - } ElseIf (LEqual (LIRQ, 18)) { - Return (2) - } ElseIf (LEqual (LIRQ, 19)) { - Return (13) - } Else { - Return (0) - } -} - -/* set "C", southbridge APIC interrupts */ -Name (PRSC, ResourceTemplate () { - Interrupt (ResourceConsumer, Level, ActiveLow, Shared, ,,) { - 20, 21, 22, 23, - } -}) -Method (CRSC, 1, Serialized) { - Name (LRTL, ResourceTemplate() { - Interrupt (ResourceConsumer, Level, ActiveLow, Shared, ,,) { 0 } - }) - CreateDWordField (LRTL, 5, LIRQ) - If (LEqual (Arg0, 8)) { - Store (20, LIRQ) - } ElseIf (LEqual (Arg0, 13)) { - Store (21, LIRQ) - } ElseIf (LEqual (Arg0, 2)) { - Store (22, LIRQ) - } ElseIf (LEqual (Arg0, 1)) { - Store (23, LIRQ) - } Else { - Store (0, LIRQ) - } - Return (LRTL) -} -Method (SRSC, 1, Serialized) { - CreateDWordField(Arg0, 5, LIRQ) - If (LEqual (LIRQ, 20)) { - Return (8) - } ElseIf (LEqual (LIRQ, 21)) { - Return (13) - } ElseIf (LEqual (LIRQ, 22)) { - Return (2) - } ElseIf (LEqual (LIRQ, 23)) { - Return (1) - } Else { - Return (0) - } -} - -Device (LNKA) { - Name (_HID, EISAID ("PNP0C0F")) - Name (_UID, 1) - Method (_STA, 0, Serialized) { - If (\_SB.PCI0.LPCB.INTA) { - Return (0xb) - } Else { - Return (0x9) - } - } - Method (_DIS, 0, Serialized) { - Store (0, \_SB.PCI0.LPCB.INTA) - } - Method (_PRS, 0, Serialized) { - If (PICM) { - Return (PRSB) - } Else { - Return (PRSA) - } - } - Method (_CRS, 0, Serialized) { - If (PICM) { - Return (CRSB(\_SB.PCI0.LPCB.INTA)) - } Else { - Return (CRSA(\_SB.PCI0.LPCB.INTA)) - } - } - Method (_SRS, 1, Serialized) { - If (PICM) { - Store (SRSB(Arg0), \_SB.PCI0.LPCB.INTA) - } Else { - Store (SRSA(Arg0), \_SB.PCI0.LPCB.INTA) - } - } -} -Device (LNKB) { - Name (_HID, EISAID ("PNP0C0F")) - Name (_UID, 2) - Method (_STA, 0, Serialized) { - If (\_SB.PCI0.LPCB.INTB) { - Return (0xb) - } Else { - Return (0x9) - } - } - Method (_DIS, 0, Serialized) { - Store (0, \_SB.PCI0.LPCB.INTB) - } - Method (_PRS, 0, Serialized) { - If (PICM) { - Return (PRSB) - } Else { - Return (PRSA) - } - } - Method (_CRS, 0, Serialized) { - If (PICM) { - Return (CRSB(\_SB.PCI0.LPCB.INTB)) - } Else { - Return (CRSA(\_SB.PCI0.LPCB.INTB)) - } - } - Method (_SRS, 1, Serialized) { - If (PICM) { - Store (SRSB(Arg0), \_SB.PCI0.LPCB.INTB) - } Else { - Store (SRSA(Arg0), \_SB.PCI0.LPCB.INTB) - } - } -} -Device (LNKC) { - Name (_HID, EISAID ("PNP0C0F")) - Name (_UID, 3) - Method (_STA, 0, Serialized) { - If (\_SB.PCI0.LPCB.INTC) { - Return (0xb) - } Else { - Return (0x9) - } - } - Method (_DIS, 0, Serialized) { - Store (0, \_SB.PCI0.LPCB.INTC) - } - Method (_PRS, 0, Serialized) { - If (PICM) { - Return (PRSB) - } Else { - Return (PRSA) - } - } - Method (_CRS, 0, Serialized) { - If (PICM) { - Return (CRSB(\_SB.PCI0.LPCB.INTC)) - } Else { - Return (CRSA(\_SB.PCI0.LPCB.INTC)) - } - } - Method (_SRS, 1, Serialized) { - If (PICM) { - Store (SRSB(Arg0), \_SB.PCI0.LPCB.INTC) - } Else { - Store (SRSA(Arg0), \_SB.PCI0.LPCB.INTC) - } - } -} -Device (LNKD) { - Name (_HID, EISAID ("PNP0C0F")) - Name (_UID, 4) - Method (_STA, 0, Serialized) { - If (\_SB.PCI0.LPCB.INTD) { - Return (0xb) - } Else { - Return (0x9) - } - } - Method (_DIS, 0, Serialized) { - Store (0, \_SB.PCI0.LPCB.INTD) - } - Method (_PRS, 0, Serialized) { - If (PICM) { - Return (PRSB) - } Else { - Return (PRSA) - } - } - Method (_CRS, 0, Serialized) { - If (PICM) { - Return (CRSB(\_SB.PCI0.LPCB.INTD)) - } Else { - Return (CRSA(\_SB.PCI0.LPCB.INTD)) - } - } - Method (_SRS, 1, Serialized) { - If (PICM) { - Store (SRSB(Arg0), \_SB.PCI0.LPCB.INTD) - } Else { - Store (SRSA(Arg0), \_SB.PCI0.LPCB.INTD) - } - } -} -Device (LNKE) { - Name (_HID, EISAID ("PNP0C0F")) - Name (_UID, 5) - Method (_STA, 0, Serialized) { - If (\_SB.PCI0.LPCB.INTE) { - Return (0xb) - } Else { - Return (0x9) - } - } - Method (_DIS, 0, Serialized) { - Store (0, \_SB.PCI0.LPCB.INTE) - } - Method (_PRS, 0, Serialized) { - If (PICM) { - Return (PRSB) - } Else { - Return (PRSA) - } - } - Method (_CRS, 0, Serialized) { - If (PICM) { - Return (CRSB(\_SB.PCI0.LPCB.INTE)) - } Else { - Return (CRSA(\_SB.PCI0.LPCB.INTE)) - } - } - Method (_SRS, 1, Serialized) { - If (PICM) { - Store (SRSB(Arg0), \_SB.PCI0.LPCB.INTE) - } Else { - Store (SRSA(Arg0), \_SB.PCI0.LPCB.INTE) - } - } -} -Device (LLAS) { - Name (_HID, EISAID ("PNP0C0F")) - Name (_UID, 6) - Method (_STA, 0, Serialized) { - If (\_SB.PCI0.LPCB.INTK) { - Return (0xb) - } Else { - Return (0x9) - } - } - Method (_DIS, 0, Serialized) { - Store (0, \_SB.PCI0.LPCB.INTK) - } - Method (_PRS, 0, Serialized) { - If (PICM) { - Return (PRSC) - } Else { - Return (PRSA) - } - } - Method (_CRS, 0, Serialized) { - If (PICM) { - Return (CRSC(\_SB.PCI0.LPCB.INTK)) - } Else { - Return (CRSA(\_SB.PCI0.LPCB.INTK)) - } - } - Method (_SRS, 1, Serialized) { - If (PICM) { - Store (SRSC(Arg0), \_SB.PCI0.LPCB.INTK) - } Else { - Store (SRSA(Arg0), \_SB.PCI0.LPCB.INTK) - } - } -} -Device (LUOH) { - Name (_HID, EISAID ("PNP0C0F")) - Name (_UID, 7) - Method (_STA, 0, Serialized) { - If (\_SB.PCI0.LPCB.INTQ) { - Return (0xb) - } Else { - Return (0x9) - } - } - Method (_DIS, 0, Serialized) { - Store (0, \_SB.PCI0.LPCB.INTQ) - } - Method (_PRS, 0, Serialized) { - If (PICM) { - Return (PRSC) - } Else { - Return (PRSA) - } - } - Method (_CRS, 0, Serialized) { - If (PICM) { - Return (CRSC(\_SB.PCI0.LPCB.INTQ)) - } Else { - Return (CRSA(\_SB.PCI0.LPCB.INTQ)) - } - } - Method (_SRS, 1, Serialized) { - If (PICM) { - Store (SRSC(Arg0), \_SB.PCI0.LPCB.INTQ) - } Else { - Store (SRSA(Arg0), \_SB.PCI0.LPCB.INTQ) - } - } -} -Device (LUEH) { - Name (_HID, EISAID ("PNP0C0F")) - Name (_UID, 8) - Method (_STA, 0, Serialized) { - If (\_SB.PCI0.LPCB.INTL) { - Return (0xb) - } Else { - Return (0x9) - } - } - Method (_DIS, 0, Serialized) { - Store (0, \_SB.PCI0.LPCB.INTL) - } - Method (_PRS, 0, Serialized) { - If (PICM) { - Return (PRSC) - } Else { - Return (PRSA) - } - } - Method (_CRS, 0, Serialized) { - If (PICM) { - Return (CRSC(\_SB.PCI0.LPCB.INTL)) - } Else { - Return (CRSA(\_SB.PCI0.LPCB.INTL)) - } - } - Method (_SRS, 1, Serialized) { - If (PICM) { - Store (SRSC(Arg0), \_SB.PCI0.LPCB.INTL) - } Else { - Store (SRSA(Arg0), \_SB.PCI0.LPCB.INTL) - } - } -} -Device (LAUD) { - Name (_HID, EISAID ("PNP0C0F")) - Name (_UID, 9) - Method (_STA, 0, Serialized) { - If (\_SB.PCI0.LPCB.INTU) { - Return (0xb) - } Else { - Return (0x9) - } - } - Method (_DIS, 0, Serialized) { - Store (0, \_SB.PCI0.LPCB.INTU) - } - Method (_PRS, 0, Serialized) { - If (PICM) { - Return (PRSC) - } Else { - Return (PRSA) - } - } - Method (_CRS, 0, Serialized) { - If (PICM) { - Return (CRSC(\_SB.PCI0.LPCB.INTU)) - } Else { - Return (CRSA(\_SB.PCI0.LPCB.INTU)) - } - } - Method (_SRS, 1, Serialized) { - If (PICM) { - Store (SRSC(Arg0), \_SB.PCI0.LPCB.INTU) - } Else { - Store (SRSA(Arg0), \_SB.PCI0.LPCB.INTU) - } - } -} -Device (LMOD) { - Name (_HID, EISAID ("PNP0C0F")) - Name (_UID, 10) - Method (_STA, 0, Serialized) { - If (\_SB.PCI0.LPCB.INTV) { - Return (0xb) - } Else { - Return (0x9) - } - } - Method (_DIS, 0, Serialized) { - Store (0, \_SB.PCI0.LPCB.INTV) - } - Method (_PRS, 0, Serialized) { - If (PICM) { - Return (PRSC) - } Else { - Return (PRSA) - } - } - Method (_CRS, 0, Serialized) { - If (PICM) { - Return (CRSC(\_SB.PCI0.LPCB.INTV)) - } Else { - Return (CRSA(\_SB.PCI0.LPCB.INTV)) - } - } - Method (_SRS, 1, Serialized) { - If (PICM) { - Store (SRSC(Arg0), \_SB.PCI0.LPCB.INTV) - } Else { - Store (SRSA(Arg0), \_SB.PCI0.LPCB.INTV) - } - } -} -Device (LPA0) { - Name (_HID, EISAID ("PNP0C0F")) - Name (_UID, 11) - Method (_STA, 0, Serialized) { - If (\_SB.PCI0.LPCB.INTW) { - Return (0xb) - } Else { - Return (0x9) - } - } - Method (_DIS, 0, Serialized) { - Store (0, \_SB.PCI0.LPCB.INTW) - Store (0, \_SB.PCI0.LPCB.INTX) - } - Method (_PRS, 0, Serialized) { - If (PICM) { - Return (PRSC) - } Else { - Return (PRSA) - } - } - Method (_CRS, 0, Serialized) { - If (PICM) { - Return (CRSC(\_SB.PCI0.LPCB.INTW)) - } Else { - Return (CRSA(\_SB.PCI0.LPCB.INTW)) - } - } - Method (_SRS, 1, Serialized) { - If (PICM) { - Store (SRSC(Arg0), Local0) - } Else { - Store (SRSA(Arg0), Local0) - } - Store(Local0, \_SB.PCI0.LPCB.INTW) - Store(Local0, \_SB.PCI0.LPCB.INTX) - } -} -Device (LSA0) { - Name (_HID, EISAID ("PNP0C0F")) - Name (_UID, 12) - Method (_STA, 0, Serialized) { - If (\_SB.PCI0.LPCB.INTP) { - Return (0xb) - } Else { - Return (0x9) - } - } - Method (_DIS, 0, Serialized) { - Store (0, \_SB.PCI0.LPCB.INTP) - Store (0, \_SB.PCI0.LPCB.INTG) - } - Method (_PRS, 0, Serialized) { - If (PICM) { - Return (PRSC) - } Else { - Return (PRSA) - } - } - Method (_CRS, 0, Serialized) { - If (PICM) { - Return (CRSC(\_SB.PCI0.LPCB.INTP)) - } Else { - Return (CRSA(\_SB.PCI0.LPCB.INTP)) - } - } - Method (_SRS, 1, Serialized) { - If (PICM) { - Store (SRSC(Arg0), Local0) - } Else { - Store (SRSA(Arg0), Local0) - } - Store(Local0, \_SB.PCI0.LPCB.INTP) - Store(Local0, \_SB.PCI0.LPCB.INTG) - } -} -Device (LSA1) { - Name (_HID, EISAID ("PNP0C0F")) - Name (_UID, 13) - Method (_STA, 0, Serialized) { - If (\_SB.PCI0.LPCB.INTO) { - Return (0xb) - } Else { - Return (0x9) - } - } - Method (_DIS, 0, Serialized) { - Store (0, \_SB.PCI0.LPCB.INTO) - Store (0, \_SB.PCI0.LPCB.INTF) - } - Method (_PRS, 0, Serialized) { - If (PICM) { - Return (PRSC) - } Else { - Return (PRSA) - } - } - Method (_CRS, 0, Serialized) { - If (PICM) { - Return (CRSC(\_SB.PCI0.LPCB.INTO)) - } Else { - Return (CRSA(\_SB.PCI0.LPCB.INTO)) - } - } - Method (_SRS, 1, Serialized) { - If (PICM) { - Store (SRSC(Arg0), Local0) - } Else { - Store (SRSA(Arg0), Local0) - } - Store(Local0, \_SB.PCI0.LPCB.INTO) - Store(Local0, \_SB.PCI0.LPCB.INTF) - } -} -Device (LEMA) { - Name (_HID, EISAID ("PNP0C0F")) - Name (_UID, 14) - Method (_STA, 0, Serialized) { - If (\_SB.PCI0.LPCB.INTS) { - Return (0xb) - } Else { - Return (0x9) - } - } - Method (_DIS, 0, Serialized) { - Store (0, \_SB.PCI0.LPCB.INTS) - } - Method (_PRS, 0, Serialized) { - If (PICM) { - Return (PRSC) - } Else { - Return (PRSA) - } - } - Method (_CRS, 0, Serialized) { - If (PICM) { - Return (CRSC(\_SB.PCI0.LPCB.INTS)) - } Else { - Return (CRSA(\_SB.PCI0.LPCB.INTS)) - } - } - Method (_SRS, 1, Serialized) { - If (PICM) { - Store (SRSC(Arg0), \_SB.PCI0.LPCB.INTS) - } Else { - Store (SRSA(Arg0), \_SB.PCI0.LPCB.INTS) - } - } -} diff --git a/src/southbridge/nvidia/ck804/bootblock.c b/src/southbridge/nvidia/ck804/bootblock.c deleted file mode 100644 index 3b36a69733..0000000000 --- a/src/southbridge/nvidia/ck804/bootblock.c +++ /dev/null @@ -1,38 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2004 Tyan Computer - * Written by Yinghai Lu for Tyan Computer. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include "ck804.h" - -static void ck804_enable_rom(void) -{ - unsigned char byte; - pci_devfn_t addr; - - /* Enable 4MB ROM access at 0xFFC00000 - 0xFFFFFFFF. */ - /* Locate the ck804 LPC. */ - addr = PCI_DEV(0, (CK804_DEVN_BASE + 1), 0); - - /* Set the 4MB enable bit. */ - byte = pci_read_config8(addr, 0x88); - byte |= 0x80; - pci_write_config8(addr, 0x88, byte); -} - -static void bootblock_southbridge_init(void) -{ - ck804_enable_rom(); -} diff --git a/src/southbridge/nvidia/ck804/chip.h b/src/southbridge/nvidia/ck804/chip.h deleted file mode 100644 index b1676ce4ab..0000000000 --- a/src/southbridge/nvidia/ck804/chip.h +++ /dev/null @@ -1,32 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2004 Tyan Computer - * Written by Yinghai Lu for Tyan Computer. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef SOUTHBRIDGE_NVIDIA_CK804_CHIP_H -#define SOUTHBRIDGE_NVIDIA_CK804_CHIP_H - -struct southbridge_nvidia_ck804_config { - unsigned int usb1_hc_reset : 1; - unsigned int ide0_enable : 1; - unsigned int ide1_enable : 1; - unsigned int sata0_enable : 1; - unsigned int sata1_enable : 1; - unsigned int mac_eeprom_smbus; - unsigned int mac_eeprom_addr; -}; - -extern struct pci_operations ck804_pci_ops; - -#endif diff --git a/src/southbridge/nvidia/ck804/ck804.c b/src/southbridge/nvidia/ck804/ck804.c deleted file mode 100644 index 2293392d46..0000000000 --- a/src/southbridge/nvidia/ck804/ck804.c +++ /dev/null @@ -1,196 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2004 Tyan Computer - * Written by Yinghai Lu for Tyan Computer. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include -#include -#include "chip.h" - -static u32 final_reg; - -static struct device *find_lpc_dev(struct device *dev, unsigned int devfn) -{ - struct device *lpc_dev; - - lpc_dev = pcidev_path_behind(dev->bus, devfn); - if (!lpc_dev) - return lpc_dev; - - if ((lpc_dev->vendor != PCI_VENDOR_ID_NVIDIA) - || ((lpc_dev->device != PCI_DEVICE_ID_NVIDIA_CK804_LPC) - && (lpc_dev->device != PCI_DEVICE_ID_NVIDIA_CK804_PRO) - && (lpc_dev->device != PCI_DEVICE_ID_NVIDIA_CK804_SLAVE))) - { - u32 id; - id = pci_read_config32(lpc_dev, PCI_VENDOR_ID); - if ((id != (PCI_VENDOR_ID_NVIDIA | - (PCI_DEVICE_ID_NVIDIA_CK804_LPC << 16))) - && (id != (PCI_VENDOR_ID_NVIDIA | - (PCI_DEVICE_ID_NVIDIA_CK804_PRO << 16))) - && (id != (PCI_VENDOR_ID_NVIDIA | - (PCI_DEVICE_ID_NVIDIA_CK804_SLAVE << 16)))) - { - lpc_dev = 0; - } - } - - return lpc_dev; -} - -static void ck804_enable(struct device *dev) -{ - struct device *lpc_dev; - unsigned int index = 0, index2 = 0, deviceid, vendorid, devfn; - u32 reg_old, reg; - u8 byte; - - if (dev->device == 0x0000) { - vendorid = pci_read_config32(dev, PCI_VENDOR_ID); - deviceid = (vendorid >> 16) & 0xffff; - /* vendorid &= 0xffff; */ - } else { - /* vendorid = dev->vendor; */ - deviceid = dev->device; - } - - devfn = (dev->path.pci.devfn) & ~7; - switch (deviceid) { - case PCI_DEVICE_ID_NVIDIA_CK804_SM: - index = 16; - break; - case PCI_DEVICE_ID_NVIDIA_CK804_USB: - devfn -= (1 << 3); - index = 8; - break; - case PCI_DEVICE_ID_NVIDIA_CK804_USB2: - devfn -= (1 << 3); - index = 20; - break; - case PCI_DEVICE_ID_NVIDIA_CK804_NIC: - devfn -= (9 << 3); - index = 10; - break; - case PCI_DEVICE_ID_NVIDIA_CK804_NIC_BRIDGE: - devfn -= (9 << 3); - index = 10; - break; - case PCI_DEVICE_ID_NVIDIA_CK804_ACI: - devfn -= (3 << 3); - index = 12; - break; - case PCI_DEVICE_ID_NVIDIA_CK804_MCI: - devfn -= (3 << 3); - index = 13; - break; - case PCI_DEVICE_ID_NVIDIA_CK804_IDE: - devfn -= (5 << 3); - index = 14; - break; - case PCI_DEVICE_ID_NVIDIA_CK804_SATA0: - devfn -= (6 << 3); - index = 22; - break; - case PCI_DEVICE_ID_NVIDIA_CK804_SATA1: - devfn -= (7 << 3); - index = 18; - break; - case PCI_DEVICE_ID_NVIDIA_CK804_PCI: - devfn -= (8 << 3); - index = 15; - break; - case PCI_DEVICE_ID_NVIDIA_CK804_PCI_E: - devfn -= (0xa << 3); - index2 = 19; - break; - default: - index = 0; - } - - if (index2 != 0) { - int i; - for (i = 0; i < 4; i++) { - lpc_dev = find_lpc_dev(dev, devfn - (i << 3)); - if (!lpc_dev) - continue; - index2 -= i; - break; - } - - if (lpc_dev) { - reg_old = reg = pci_read_config32(lpc_dev, 0xe4); - if (!dev->enabled) - reg |= (1 << index2); - if (reg != reg_old) - pci_write_config32(lpc_dev, 0xe4, reg); - } - - index2 = 0; - return; - } - - lpc_dev = find_lpc_dev(dev, devfn); - if (!lpc_dev) - return; - - if (index == 0) { - final_reg = pci_read_config32(lpc_dev, 0xe8); - final_reg &= ~((1 << 16) | (1 << 8) | (1 << 20) | (1 << 10) - | (1 << 12) | (1 << 13) | (1 << 14) | (1 << 22) - | (1 << 18) | (1 << 15)); - pci_write_config32(lpc_dev, 0xe8, final_reg); - - reg_old = reg = pci_read_config32(lpc_dev, 0xe4); - reg |= (1 << 20); - if (reg != reg_old) - pci_write_config32(lpc_dev, 0xe4, reg); - - byte = pci_read_config8(lpc_dev, 0x74); - byte |= ((1 << 1)); - pci_write_config8(dev, 0x74, byte); - - byte = pci_read_config8(lpc_dev, 0xdd); - byte |= ((1 << 0) | (1 << 3)); - pci_write_config8(dev, 0xdd, byte); - - return; - } - - if (!dev->enabled) - final_reg |= (1 << index); - - if (index == 10) { - reg_old = pci_read_config32(lpc_dev, 0xe8); - if (final_reg != reg_old) - pci_write_config32(lpc_dev, 0xe8, final_reg); - } -} - -static void ck804_set_subsystem(struct device *dev, unsigned int vendor, - unsigned int device) -{ - pci_write_config32(dev, 0x40, - ((device & 0xffff) << 16) | (vendor & 0xffff)); -} - -struct pci_operations ck804_pci_ops = { - .set_subsystem = ck804_set_subsystem, -}; - -struct chip_operations southbridge_nvidia_ck804_ops = { - CHIP_NAME("NVIDIA CK804 Southbridge") - .enable_dev = ck804_enable, -}; diff --git a/src/southbridge/nvidia/ck804/ck804.h b/src/southbridge/nvidia/ck804/ck804.h deleted file mode 100644 index c4c4c4f91a..0000000000 --- a/src/southbridge/nvidia/ck804/ck804.h +++ /dev/null @@ -1,31 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2004 Tyan Computer - * Written by Yinghai Lu for Tyan Computer. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef SOUTHBRIDGE_NVIDIA_CK804_CK804_H -#define SOUTHBRIDGE_NVIDIA_CK804_CK804_H - -#if CONFIG_HT_CHAIN_END_UNITID_BASE < CONFIG_HT_CHAIN_UNITID_BASE -#define CK804_DEVN_BASE CONFIG_HT_CHAIN_END_UNITID_BASE -#else -#define CK804_DEVN_BASE CONFIG_HT_CHAIN_UNITID_BASE -#endif - -#define CK804B_BUSN 0x80 -#define CK804B_DEVN_BASE (!CONFIG(SB_HT_CHAIN_UNITID_OFFSET_ONLY) ? CK804_DEVN_BASE : 1) - -void enable_fid_change_on_sb(unsigned int sbbusn, unsigned int sbdn); - -#endif diff --git a/src/southbridge/nvidia/ck804/early_setup_car.c b/src/southbridge/nvidia/ck804/early_setup_car.c deleted file mode 100644 index bbd8210d21..0000000000 --- a/src/southbridge/nvidia/ck804/early_setup_car.c +++ /dev/null @@ -1,387 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2015 Timothy Pearson , Raptor Engineering - * - * Copyright (C) 2004 Tyan Computer - * Written by Yinghai Lu for Tyan Computer. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include -#include - -#include "ck804.h" - -/* Someone messed up and snuck in some K8-specific code */ -static int set_ht_link_buffer_counts_chain(uint8_t ht_c_num, unsigned int vendorid, unsigned int val) { return 0; /* stub */}; - -static int set_ht_link_ck804(u8 ht_c_num) -{ - unsigned int vendorid = 0x10de; - unsigned int val = 0x01610169; - return set_ht_link_buffer_counts_chain(ht_c_num, vendorid, val); -} - -static void setup_ss_table(unsigned int index, unsigned int where, unsigned int control, - const unsigned int *register_values, int max) -{ - int i; - unsigned int val; - - val = inl(control); - val &= 0xfffffffe; - outl(val, control); - - outl(0, index); - - for (i = 0; i < max; i++) { - unsigned long reg; - reg = register_values[i]; - outl(reg, where); - } - val = inl(control); - val |= 1; - outl(val, control); -} - -#define ANACTRL_IO_BASE 0x3000 -#define ANACTRL_REG_POS 0x68 - -#define SYSCTRL_IO_BASE 0x2000 -#define SYSCTRL_REG_POS 0x64 - -/* - * Values for CONFIG_CK804_PCI_E_X and CONFIG_CK804B_PCI_E_X. - * Apparently some sort of lane configuration. - * - * 16 1 1 2 :0 - * 8 8 2 2 :1 - * 8 8 4 :2 - * 8 4 4 4 :3 - * 16 4 :4 - */ - -/* There will be implicit offsets applied, the writes below do not - * really happen at the PCI_ADDR() this expands to. - */ -#define CK804_DEV(d, f, r) PCI_ADDR(0, d, f, r) - -static void ck804_early_set_port(unsigned int ck804_num, unsigned int *busn, - unsigned int *io_base) -{ - static const unsigned int ctrl_devport_conf[] = { - CK804_DEV(0x1, 0, ANACTRL_REG_POS), ~(0x0000ff00), ANACTRL_IO_BASE, - CK804_DEV(0x1, 0, SYSCTRL_REG_POS), ~(0x0000ff00), SYSCTRL_IO_BASE, - }; - - int j; - for (j = 0; j < ck804_num; j++) { - u32 dev; - if (busn[j] == 0) /* SB chain */ - dev = PCI_DEV(busn[j], CK804_DEVN_BASE, 0); - else - dev = PCI_DEV(busn[j], CK804B_DEVN_BASE, 0); - setup_resource_map_offset(ctrl_devport_conf, - ARRAY_SIZE(ctrl_devport_conf), dev, io_base[j]); - } -} - -static void ck804_early_clear_port(unsigned int ck804_num, unsigned int *busn, - unsigned int *io_base) -{ - static const unsigned int ctrl_devport_conf_clear[] = { - CK804_DEV(0x1, 0, ANACTRL_REG_POS), ~(0x0000ff01), 0, - CK804_DEV(0x1, 0, SYSCTRL_REG_POS), ~(0x0000ff01), 0, - }; - - int j; - for (j = 0; j < ck804_num; j++) { - u32 dev; - if (busn[j] == 0) /* SB chain */ - dev = PCI_DEV(busn[j], CK804_DEVN_BASE, 0); - else - dev = PCI_DEV(busn[j], CK804B_DEVN_BASE, 0); - setup_resource_map_offset(ctrl_devport_conf_clear, - ARRAY_SIZE(ctrl_devport_conf_clear), dev, io_base[j]); - } -} - -static void ck804_early_setup(unsigned int ck804_num, unsigned int *busn, - unsigned int *io_base) -{ - static const unsigned int ctrl_conf_master[] = { - RES_PCI_IO, CK804_DEV(1, 2, 0x8c), 0xffff0000, 0x00009880, - RES_PCI_IO, CK804_DEV(1, 2, 0x90), 0xffff000f, 0x000074a0, - RES_PCI_IO, CK804_DEV(1, 2, 0xa0), 0xfffff0ff, 0x00000a00, - RES_PCI_IO, CK804_DEV(1, 2, 0xac), 0xffffff00, 0x00000000, - - RES_PCI_IO, CK804_DEV(0, 0, 0x48), 0xfffffffd, 0x00000002, - RES_PCI_IO, CK804_DEV(0, 0, 0x74), 0xfffff00f, 0x000009d0, - RES_PCI_IO, CK804_DEV(0, 0, 0x8c), 0xffff0000, 0x0000007f, - RES_PCI_IO, CK804_DEV(0, 0, 0xcc), 0xfffffff8, 0x00000003, - RES_PCI_IO, CK804_DEV(0, 0, 0xd0), 0xff000000, 0x00000000, - RES_PCI_IO, CK804_DEV(0, 0, 0xd4), 0xff000000, 0x00000000, - RES_PCI_IO, CK804_DEV(0, 0, 0xd8), 0xff000000, 0x00000000, - RES_PCI_IO, CK804_DEV(0, 0, 0xdc), 0x7f000000, 0x00000000, - - RES_PCI_IO, CK804_DEV(1, 0, 0xf0), 0xfffffffd, 0x00000002, - RES_PCI_IO, CK804_DEV(1, 0, 0xf8), 0xffffffcf, 0x00000010, - - RES_PCI_IO, CK804_DEV(9, 0, 0x40), 0xfff8ffff, 0x00030000, - RES_PCI_IO, CK804_DEV(9, 0, 0x4c), 0xfe00ffff, 0x00440000, - RES_PCI_IO, CK804_DEV(9, 0, 0x74), 0xffffffc0, 0x00000000, - -#ifdef CK804_MB_SETUP - CK804_MB_SETUP -#endif - -#if CONFIG(NORTHBRIDGE_AMD_AMDFAM10) - /* - * Avoid crash (complete with severe memory corruption!) during initial CAR boot - * in ck804_early_setup_x() on Fam10h systems by not touching 0x78. - * Interestingly once the system is fully booted into Linux this can be set, but - * not before! Apparently something isn't initialized but the amount of effort - * required to fix this is non-negligible and of unknown real-world benefit - */ -#else - RES_PCI_IO, CK804_DEV(1, 0, 0x78), 0xc0ffffff, 0x19000000, -#endif - RES_PCI_IO, CK804_DEV(1, 0, 0xe0), 0xfffffeff, 0x00000100, - - RES_PORT_IO_32, ANACTRL_IO_BASE + 0x20, 0xe00fffff, 0x11000000, - RES_PORT_IO_32, ANACTRL_IO_BASE + 0x24, 0xc3f0ffff, 0x24040000, - RES_PORT_IO_32, ANACTRL_IO_BASE + 0x80, 0x8c3f04df, 0x51407120, - RES_PORT_IO_32, ANACTRL_IO_BASE + 0x84, 0xffffff8f, 0x00000010, - RES_PORT_IO_32, ANACTRL_IO_BASE + 0x94, 0xff00ffff, 0x00c00000, - RES_PORT_IO_32, ANACTRL_IO_BASE + 0xcc, 0xf7ffffff, 0x00000000, - - RES_PORT_IO_32, ANACTRL_IO_BASE + 0x74, ~(0xffff), 0x0f008, - RES_PORT_IO_32, ANACTRL_IO_BASE + 0x78, ~((0xff) | (0xff << 16)), (0x41 << 16) | (0x32), - RES_PORT_IO_32, ANACTRL_IO_BASE + 0x7c, ~(0xff << 16), (0xa0 << 16), - - RES_PORT_IO_32, ANACTRL_IO_BASE + 0x24, 0xfcffff0f, 0x020000b0, - - /* Activate master port on primary SATA controller. */ - RES_PCI_IO, CK804_DEV(7, 0, 0x50), ~(0x1f000013), 0x15000013, - RES_PCI_IO, CK804_DEV(7, 0, 0x64), ~(0x00000001), 0x00000001, - RES_PCI_IO, CK804_DEV(7, 0, 0x68), ~(0x02000000), 0x02000000, - RES_PCI_IO, CK804_DEV(7, 0, 0x70), ~(0x000f0000), 0x00040000, - RES_PCI_IO, CK804_DEV(7, 0, 0xa0), ~(0x000001ff), 0x00000150, - RES_PCI_IO, CK804_DEV(7, 0, 0xac), ~(0xffff8f00), 0x02aa8b00, - RES_PCI_IO, CK804_DEV(7, 0, 0x7c), ~(0x00000010), 0x00000000, - RES_PCI_IO, CK804_DEV(7, 0, 0xc8), ~(0x0fff0fff), 0x000a000a, - RES_PCI_IO, CK804_DEV(7, 0, 0xd0), ~(0xf0000000), 0x00000000, - RES_PCI_IO, CK804_DEV(7, 0, 0xe0), ~(0xf0000000), 0x00000000, - - RES_PCI_IO, CK804_DEV(8, 0, 0x50), ~(0x1f000013), 0x15000013, - RES_PCI_IO, CK804_DEV(8, 0, 0x64), ~(0x00000001), 0x00000001, - RES_PCI_IO, CK804_DEV(8, 0, 0x68), ~(0x02000000), 0x02000000, - RES_PCI_IO, CK804_DEV(8, 0, 0x70), ~(0x000f0000), 0x00040000, - RES_PCI_IO, CK804_DEV(8, 0, 0xa0), ~(0x000001ff), 0x00000150, - RES_PCI_IO, CK804_DEV(8, 0, 0xac), ~(0xffff8f00), 0x02aa8b00, - RES_PCI_IO, CK804_DEV(8, 0, 0x7c), ~(0x00000010), 0x00000000, - RES_PCI_IO, CK804_DEV(8, 0, 0xc8), ~(0x0fff0fff), 0x000a000a, - RES_PCI_IO, CK804_DEV(8, 0, 0xd0), ~(0xf0000000), 0x00000000, - RES_PCI_IO, CK804_DEV(8, 0, 0xe0), ~(0xf0000000), 0x00000000, - - RES_PORT_IO_32, ANACTRL_IO_BASE + 0x04, ~((0x3ff << 0) | (0x3ff << 10)), (0x21 << 0) | (0x22 << 10), - - RES_PORT_IO_32, ANACTRL_IO_BASE + 0x08, ~(0xfffff), (0x1c << 10) | 0x1b, - - RES_PORT_IO_32, ANACTRL_IO_BASE + 0x80, ~(1 << 3), 0x00000000, - - RES_PORT_IO_32, ANACTRL_IO_BASE + 0xcc, ~((7 << 4) | (1 << 8)), (CONFIG_CK804_PCI_E_X << 4) | (1 << 8), - - /* SYSCTRL */ - RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0 + 8, ~(0xff), ((0 << 4) | (0 << 2) | (0 << 0)), - RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0 + 9, ~(0xff), ((0 << 4) | (1 << 2) | (1 << 0)), -#if CONFIG(CK804_USE_NIC) - RES_PCI_IO, CK804_DEV(0xa, 0, 0xf8), 0xffffffbf, 0x00000040, - RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0 + 19, ~(0xff), ((0 << 4) | (1 << 2) | (0 << 0)), - RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0 + 3, ~(0xff), ((0 << 4) | (1 << 2) | (0 << 0)), - RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0 + 3, ~(0xff), ((0 << 4) | (1 << 2) | (1 << 0)), - RES_PCI_IO, CK804_DEV(1, 0, 0xe4), ~(1 << 23), (1 << 23), -#endif - -#if CONFIG(CK804_USE_ACI) - RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0 + 0x0d, ~(0xff), ((0 << 4) | (2 << 2) | (0 << 0)), - RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0 + 0x1a, ~(0xff), ((0 << 4) | (2 << 2) | (0 << 0)), -#endif - -#if CONFIG(CK804_PCIE_PME_WAKE) - RES_PCI_IO, CK804_DEV(1, 0, 0xe4), 0xffffffff, 0x00400000, -#else - RES_PCI_IO, CK804_DEV(1, 0, 0xe4), 0xffbfffff, 0x00000000, -#endif - }; - - static const unsigned int ctrl_conf_multiple[] = { - RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0 + 0, ~(3 << 2), (0 << 2), - }; - - static const unsigned int ctrl_conf_slave[] = { - RES_PCI_IO, CK804_DEV(1, 2, 0x8c), 0xffff0000, 0x00009880, - RES_PCI_IO, CK804_DEV(1, 2, 0x90), 0xffff000f, 0x000074a0, - RES_PCI_IO, CK804_DEV(1, 2, 0xa0), 0xfffff0ff, 0x00000a00, - - RES_PCI_IO, CK804_DEV(0, 0, 0x48), 0xfffffffd, 0x00000002, - RES_PCI_IO, CK804_DEV(0, 0, 0x74), 0xfffff00f, 0x000009d0, - RES_PCI_IO, CK804_DEV(0, 0, 0x8c), 0xffff0000, 0x0000007f, - RES_PCI_IO, CK804_DEV(0, 0, 0xcc), 0xfffffff8, 0x00000003, - RES_PCI_IO, CK804_DEV(0, 0, 0xd0), 0xff000000, 0x00000000, - RES_PCI_IO, CK804_DEV(0, 0, 0xd4), 0xff000000, 0x00000000, - RES_PCI_IO, CK804_DEV(0, 0, 0xd8), 0xff000000, 0x00000000, - RES_PCI_IO, CK804_DEV(0, 0, 0xdc), 0x7f000000, 0x00000000, - - RES_PCI_IO, CK804_DEV(1, 0, 0xf0), 0xfffffffd, 0x00000002, - RES_PCI_IO, CK804_DEV(1, 0, 0xf8), 0xffffffcf, 0x00000010, - - RES_PCI_IO, CK804_DEV(9, 0, 0x40), 0xfff8ffff, 0x00030000, - RES_PCI_IO, CK804_DEV(9, 0, 0x4c), 0xfe00ffff, 0x00440000, - RES_PCI_IO, CK804_DEV(9, 0, 0x74), 0xffffffc0, 0x00000000, - - /* - * Avoid touching 0x78 for CONFIG_NORTHBRIDGE_AMD_AMDFAM10 for - * non-primary chains too??? - */ - RES_PCI_IO, CK804_DEV(1, 0, 0x78), 0xc0ffffff, 0x20000000, - RES_PCI_IO, CK804_DEV(1, 0, 0xe0), 0xfffffeff, 0x00000000, - RES_PCI_IO, CK804_DEV(1, 0, 0xe8), 0xffffff00, 0x000000ff, - - RES_PORT_IO_32, ANACTRL_IO_BASE + 0x20, 0xe00fffff, 0x11000000, - RES_PORT_IO_32, ANACTRL_IO_BASE + 0x24, 0xc3f0ffff, 0x24040000, - RES_PORT_IO_32, ANACTRL_IO_BASE + 0x80, 0x8c3f04df, 0x51407120, - RES_PORT_IO_32, ANACTRL_IO_BASE + 0x84, 0xffffff8f, 0x00000010, - RES_PORT_IO_32, ANACTRL_IO_BASE + 0x94, 0xff00ffff, 0x00c00000, - RES_PORT_IO_32, ANACTRL_IO_BASE + 0xcc, 0xf7ffffff, 0x00000000, - - RES_PORT_IO_32, ANACTRL_IO_BASE + 0x24, 0xfcffff0f, 0x020000b0, - - RES_PCI_IO, CK804_DEV(8, 0, 0x50), ~(0x1f000013), 0x15000013, - RES_PCI_IO, CK804_DEV(8, 0, 0x64), ~(0x00000001), 0x00000001, - RES_PCI_IO, CK804_DEV(8, 0, 0x68), ~(0x02000000), 0x02000000, - RES_PCI_IO, CK804_DEV(8, 0, 0x70), ~(0x000f0000), 0x00040000, - RES_PCI_IO, CK804_DEV(8, 0, 0xa0), ~(0x000001ff), 0x00000150, - RES_PCI_IO, CK804_DEV(8, 0, 0xac), ~(0xffff8f00), 0x02aa8b00, - RES_PCI_IO, CK804_DEV(8, 0, 0x7c), ~(0x00000010), 0x00000000, - RES_PCI_IO, CK804_DEV(8, 0, 0xc8), ~(0x0fff0fff), 0x000a000a, - RES_PCI_IO, CK804_DEV(8, 0, 0xd0), ~(0xf0000000), 0x00000000, - RES_PCI_IO, CK804_DEV(8, 0, 0xe0), ~(0xf0000000), 0x00000000, - - RES_PORT_IO_32, ANACTRL_IO_BASE + 0x04, ~((0x3ff << 0) | (0x3ff << 10)), (0x21 << 0) | (0x22 << 10), - - RES_PORT_IO_32, ANACTRL_IO_BASE + 0x08, ~(0xfffff), (0x1c << 10) | 0x1b, - - /* This line doesn't exist in the non-CAR version. */ - RES_PORT_IO_32, ANACTRL_IO_BASE + 0x80, ~(1 << 3), 0x00000000, - - RES_PORT_IO_32, ANACTRL_IO_BASE + 0xcc, ~((7 << 4) | (1 << 8)), (CONFIG_CK804B_PCI_E_X << 4) | (1 << 8), - -#if CONFIG(CK804_USE_NIC) - RES_PCI_IO, CK804_DEV(0xa, 0, 0xf8), 0xffffffbf, 0x00000040, - RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0 + 19, ~(0xff), ((0 << 4) | (1 << 2) | (0 << 0)), - RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0 + 3, ~(0xff), ((0 << 4) | (1 << 2) | (0 << 0)), - RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0 + 3, ~(0xff), ((0 << 4) | (1 << 2) | (1 << 0)), - RES_PCI_IO, CK804_DEV(1, 0, 0xe4), ~(1 << 23), (1 << 23), -#endif - }; - - int j; - for (j = 0; j < ck804_num; j++) { - if (busn[j] == 0) { - setup_resource_map_x_offset(ctrl_conf_master, - ARRAY_SIZE(ctrl_conf_master), - PCI_DEV(0, CK804_DEVN_BASE, 0), io_base[0]); - if (ck804_num > 1) - setup_resource_map_x_offset(ctrl_conf_multiple, - ARRAY_SIZE(ctrl_conf_multiple), - PCI_DEV(0, CK804_DEVN_BASE, 0), 0); - - continue; - } - - setup_resource_map_x_offset(ctrl_conf_slave, - ARRAY_SIZE(ctrl_conf_slave), - PCI_DEV(busn[j], CK804B_DEVN_BASE, 0), io_base[j]); - } - - for (j = 0; j < ck804_num; j++) { - /* PCI-E (XSPLL) SS table 0x40, x044, 0x48 */ - /* SATA (SPPLL) SS table 0xb0, 0xb4, 0xb8 */ - /* CPU (PPLL) SS table 0xc0, 0xc4, 0xc8 */ - setup_ss_table(io_base[j] + ANACTRL_IO_BASE + 0x40, - io_base[j] + ANACTRL_IO_BASE + 0x44, - io_base[j] + ANACTRL_IO_BASE + 0x48, - pcie_ss_tbl, 64); - setup_ss_table(io_base[j] + ANACTRL_IO_BASE + 0xb0, - io_base[j] + ANACTRL_IO_BASE + 0xb4, - io_base[j] + ANACTRL_IO_BASE + 0xb8, - sata_ss_tbl, 64); - setup_ss_table(io_base[j] + ANACTRL_IO_BASE + 0xc0, - io_base[j] + ANACTRL_IO_BASE + 0xc4, - io_base[j] + ANACTRL_IO_BASE + 0xc8, - cpu_ss_tbl, 64); - } -} - -static int ck804_early_setup_x(void) -{ - unsigned int busn[4], io_base[4]; - int i, ck804_num = 0; - - for (i = 0; i < 4; i++) { - u32 id; - pci_devfn_t dev; - if (i == 0) /* SB chain */ - dev = PCI_DEV(i * 0x40, CK804_DEVN_BASE, 0); - else - dev = PCI_DEV(i * 0x40, CK804B_DEVN_BASE, 0); - id = pci_read_config32(dev, PCI_VENDOR_ID); - if (id == 0x005e10de) { - busn[ck804_num] = i * 0x40; - io_base[ck804_num] = i * 0x4000; - ck804_num++; - } - } - - ck804_early_set_port(ck804_num, busn, io_base); - ck804_early_setup(ck804_num, busn, io_base); - ck804_early_clear_port(ck804_num, busn, io_base); - - return set_ht_link_ck804(4); -} - -void do_board_reset(void) -{ - set_bios_reset(); - - /* full reset */ - outb(0x0a, 0x0cf9); - outb(0x0e, 0x0cf9); -} - -void do_soft_reset(void) -{ - set_bios_reset(); - - /* link reset */ - outb(0x02, 0x0cf9); - outb(0x06, 0x0cf9); -} - -void enable_fid_change_on_sb(unsigned int sbbusn, unsigned int sbdn) -{ - /* The default value for CK804 is good. */ - /* Set VFSMAF (VID/FID System Management Action Field) to 2. */ -} diff --git a/src/southbridge/nvidia/ck804/early_setup_ss.h b/src/southbridge/nvidia/ck804/early_setup_ss.h deleted file mode 100644 index 69220d9549..0000000000 --- a/src/southbridge/nvidia/ck804/early_setup_ss.h +++ /dev/null @@ -1,216 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2004 Tyan Computer - * Written by Yinghai Lu for Tyan Computer. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -static const unsigned int pcie_ss_tbl[] = { - 0x0C504103f, - 0x0C504103f, - 0x0C504103f, - 0x0C5042040, - 0x0C5042040, - 0x0C5042040, - 0x0C5043041, - 0x0C5043041, - 0x0C5043041, - 0x0C5043041, - 0x0C5044042, - 0x0C5044042, - 0x0C5044042, - 0x0C5045043, - 0x0C5045043, - 0x0C5045043, - 0x0C5045043, - 0x0C5045043, - 0x0C5046044, - 0x0C5046044, - 0x0C5046044, - 0x0C5046044, - 0x0C5047045, - 0x0C5047045, - 0x0C5047045, - 0x0C5047045, - 0x0C5047045, - 0x0C5048046, - 0x0C5048046, - 0x0C5048046, - 0x0C5048046, - 0x0C5049047, - 0x0C5049047, - 0x0C5049047, - 0x0C504a048, - 0x0C504a048, - 0x0C504b049, - 0x0C504b049, - 0x0C504a048, - 0x0C504a048, - 0x0C5049047, - 0x0C5049047, - 0x0C5048046, - 0x0C5048046, - 0x0C5048046, - 0x0C5047045, - 0x0C5047045, - 0x0C5047045, - 0x0C5047045, - 0x0C5047045, - 0x0C5046044, - 0x0C5046044, - 0x0C5046044, - 0x0C5046044, - 0x0C5045043, - 0x0C5045043, - 0x0C5045043, - 0x0C5044042, - 0x0C5044042, - 0x0C5044042, - 0x0C5043041, - 0x0C5043041, - 0x0C5042040, - 0x0C5042040, -}; - -static const unsigned int sata_ss_tbl[] = { - 0x0c9044042, - 0x0c9044042, - 0x0c9044042, - 0x0c9045043, - 0x0c9045043, - 0x0c9045043, - 0x0c9045043, - 0x0c9045043, - 0x0c9046044, - 0x0c9046044, - 0x0c9046044, - 0x0c9046044, - 0x0c9047045, - 0x0c9047045, - 0x0c9047045, - 0x0c9047045, - 0x0c9047045, - 0x0c9048046, - 0x0c9048046, - 0x0c9048046, - 0x0c9048046, - 0x0c9049047, - 0x0c9049047, - 0x0c9049047, - 0x0c9049047, - 0x0c904a048, - 0x0c904a048, - 0x0c904a048, - 0x0c904a048, - 0x0c904b049, - 0x0c904b049, - 0x0c904b049, - 0x0c904b049, - 0x0c904b049, - 0x0c904b049, - 0x0c904a048, - 0x0c904a048, - 0x0c904a048, - 0x0c904a048, - 0x0c9049047, - 0x0c9049047, - 0x0c9049047, - 0x0c9049047, - 0x0c9048046, - 0x0c9048046, - 0x0c9048046, - 0x0c9048046, - 0x0c9047045, - 0x0c9047045, - 0x0c9047045, - 0x0c9047045, - 0x0c9047045, - 0x0c9046044, - 0x0c9046044, - 0x0c9046044, - 0x0c9046044, - 0x0c9045043, - 0x0c9045043, - 0x0c9045043, - 0x0c9045043, - 0x0c9045043, - 0x0c9044042, - 0x0c9044042, - 0x0c9044042, -}; - -static const unsigned int cpu_ss_tbl[] = { - 0x0C5038036, - 0x0C5038036, - 0x0C5038036, - 0x0C5037035, - 0x0C5037035, - 0x0C5037035, - 0x0C5037035, - 0x0C5036034, - 0x0C5036034, - 0x0C5036034, - 0x0C5036034, - 0x0C5036034, - 0x0C5035033, - 0x0C5035033, - 0x0C5035033, - 0x0C5035033, - 0x0C5035033, - 0x0C5035033, - 0x0C5034032, - 0x0C5034032, - 0x0C5034032, - 0x0C5034032, - 0x0C5034032, - 0x0C5034032, - 0x0C5035033, - 0x0C5035033, - 0x0C5035033, - 0x0C5035033, - 0x0C5035033, - 0x0C5036034, - 0x0C5036034, - 0x0C5036034, - 0x0C5036034, - 0x0C5036034, - 0x0C5037035, - 0x0C5037035, - 0x0C5037035, - 0x0C5037035, - 0x0C5038036, - 0x0C5038036, - 0x0C5038036, - 0x0C5038036, - 0x0C5039037, - 0x0C5039037, - 0x0C5039037, - 0x0C5039037, - 0x0C503a038, - 0x0C503a038, - 0x0C503a038, - 0x0C503a038, - 0x0C503b039, - 0x0C503b039, - 0x0C503b039, - 0x0C503b039, - 0x0C503b039, - 0x0C503a038, - 0x0C503a038, - 0x0C503a038, - 0x0C503a038, - 0x0C503a038, - 0x0C5039037, - 0x0C5039037, - 0x0C5039037, - 0x0C5039037, -}; diff --git a/src/southbridge/nvidia/ck804/early_smbus.c b/src/southbridge/nvidia/ck804/early_smbus.c deleted file mode 100644 index 8997ef0da6..0000000000 --- a/src/southbridge/nvidia/ck804/early_smbus.c +++ /dev/null @@ -1,77 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2004 Tyan Computer - * Written by Yinghai Lu for Tyan Computer. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include -#include -#include -#include -#include - -#include "smbus.h" -#include "early_smbus.h" - -#define SMBUS_BAR_BASE 0x20 -#define SMBUS_IO_BASE 0x1000 -#define SMBUS_IO_SIZE 0x0040 - -#define SMBUS_BAR(x) (SMBUS_BAR_BASE + 4 * (x)) -#define SMBUS_BASE(x) (SMBUS_IO_BASE + SMBUS_IO_SIZE * (x)) - -void enable_smbus(void) -{ - pci_devfn_t dev; - - dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_NVIDIA, - PCI_DEVICE_ID_NVIDIA_CK804_SMB), 0); - if (dev == PCI_DEV_INVALID) - die("SMBus controller not found\n"); - - /* Set SMBus I/O base. */ - pci_write_config32(dev, SMBUS_BAR(0), SMBUS_BASE(0) | 1); - pci_write_config32(dev, SMBUS_BAR(1), SMBUS_BASE(1) | 1); - - /* Set SMBus I/O space enable. */ - pci_write_config16(dev, 0x4, 0x01); - - /* Clear any lingering errors, so the transaction will run. */ - outb(inb(SMBUS_BASE(0) + SMBHSTSTAT), SMBUS_BASE(0) + SMBHSTSTAT); - outb(inb(SMBUS_BASE(1) + SMBHSTSTAT), SMBUS_BASE(1) + SMBHSTSTAT); - - printk(BIOS_DEBUG, "SMBus controller enabled\n"); -} - -int ck804_smbus_read_byte(unsigned int bus, unsigned int device, unsigned int address) -{ - return do_smbus_read_byte(SMBUS_BASE(bus), device, address); -} - -int ck804_smbus_write_byte(unsigned int bus, unsigned int device, unsigned int address, - unsigned char val) -{ - return do_smbus_write_byte(SMBUS_BASE(bus), device, address, val); -} - -int smbus_read_byte(unsigned int device, unsigned int address) -{ - return ck804_smbus_read_byte(0, device, address); -} - -int smbus_write_byte(unsigned int device, unsigned int address, unsigned char val) -{ - return ck804_smbus_write_byte(0, device, address, val); -} diff --git a/src/southbridge/nvidia/ck804/early_smbus.h b/src/southbridge/nvidia/ck804/early_smbus.h deleted file mode 100644 index 30c4b02fa5..0000000000 --- a/src/southbridge/nvidia/ck804/early_smbus.h +++ /dev/null @@ -1,18 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -int ck804_smbus_read_byte(unsigned int, unsigned int, unsigned int); -int ck804_smbus_write_byte(unsigned int, unsigned int, unsigned int, unsigned char); -void enable_smbus(void); -int smbus_read_byte(unsigned int, unsigned int); -int smbus_write_byte(unsigned int, unsigned int, unsigned char); diff --git a/src/southbridge/nvidia/ck804/enable_usbdebug.c b/src/southbridge/nvidia/ck804/enable_usbdebug.c deleted file mode 100644 index e8315092d6..0000000000 --- a/src/southbridge/nvidia/ck804/enable_usbdebug.c +++ /dev/null @@ -1,43 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2004 Tyan Computer - * Written by Yinghai Lu for Tyan Computer. - * Copyright (C) 2006,2007 AMD - * Written by Yinghai Lu for AMD. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -// Use simple device model for this file even in ramstage -#define __SIMPLE_DEVICE__ - -#include -#include -#include -#include -#include "ck804.h" - -pci_devfn_t pci_ehci_dbg_dev(unsigned int hcd_idx) -{ - return PCI_DEV(0, CK804_DEVN_BASE + 2, 1); /* USB EHCI */ -} - -void pci_ehci_dbg_set_port(pci_devfn_t dev, unsigned int port) -{ - u32 dword; - - /* Write the port number to 0x74[15:12]. */ - dword = pci_read_config32(dev, 0x74); - dword &= ~(0xf << 12); - dword |= (port << 12); - pci_write_config32(dev, 0x74, dword); -} diff --git a/src/southbridge/nvidia/ck804/fadt.c b/src/southbridge/nvidia/ck804/fadt.c deleted file mode 100644 index 55f98bffce..0000000000 --- a/src/southbridge/nvidia/ck804/fadt.c +++ /dev/null @@ -1,157 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * (C) Copyright 2005 Stefan Reinauer - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -/* - * ACPI - create the Fixed ACPI Description Tables (FADT) - */ - -#include -#include -#include -#include - -extern unsigned int pm_base; /* pm_base should be set in sb acpi */ - -void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt) -{ - acpi_header_t *header = &(fadt->header); - - printk(BIOS_DEBUG, "pm_base: 0x%04x\n", pm_base); - - /* Prepare the header */ - memset((void *)fadt, 0, sizeof(acpi_fadt_t)); - memcpy(header->signature, "FACP", 4); - header->length = sizeof(acpi_fadt_t); - header->revision = get_acpi_table_revision(FADT); - memcpy(header->oem_id, OEM_ID, 6); - memcpy(header->oem_table_id, ACPI_TABLE_CREATOR, 8); - memcpy(header->asl_compiler_id, ASLC, 4); - header->asl_compiler_revision = asl_revision; - - fadt->firmware_ctrl = (u32)facs; - fadt->dsdt = (u32)dsdt; - // 3=Workstation,4=Enterprise Server, 7=Performance Server - fadt->preferred_pm_profile = 0; - fadt->sci_int = 9; - // disable system management mode by setting to 0: - fadt->smi_cmd = 0; - fadt->acpi_enable = 0; - fadt->acpi_disable = 0; - fadt->s4bios_req = 0x0; - fadt->pstate_cnt = 0x0; - - fadt->pm1a_evt_blk = pm_base; - fadt->pm1b_evt_blk = 0x0000; - fadt->pm1a_cnt_blk = pm_base + 0x04; - fadt->pm1b_cnt_blk = 0x0000; - fadt->pm2_cnt_blk = pm_base + 0x1c; - fadt->pm_tmr_blk = pm_base + 0x08; - fadt->gpe0_blk = pm_base + 0x20; - fadt->gpe1_blk = 0x0000; - - fadt->pm1_evt_len = 4; - fadt->pm1_cnt_len = 2; - fadt->pm2_cnt_len = 1; - fadt->pm_tmr_len = 4; - fadt->gpe0_blk_len = 8; - fadt->gpe1_blk_len = 0; - fadt->gpe1_base = 0; - fadt->cst_cnt = 0; - fadt->p_lvl2_lat = 0xffff; - fadt->p_lvl3_lat = 0xffff; - fadt->flush_size = 0; - fadt->flush_stride = 0; - fadt->duty_offset = 1; - fadt->duty_width = 3; - fadt->day_alrm = 0x7d; - fadt->mon_alrm = 0x7e; - fadt->century = 0x32; - fadt->iapc_boot_arch = ACPI_FADT_LEGACY_FREE; - fadt->flags = 0xa5; - -#ifdef LONG_FADT - fadt->res2 = 0; - - fadt->reset_reg.space_id = 1; - fadt->reset_reg.bit_width = 8; - fadt->reset_reg.bit_offset = 0; - fadt->reset_reg.access_size = 0; - fadt->reset_reg.addrl = 0xcf9; - fadt->reset_reg.addrh = 0x0; - - fadt->reset_value = 6; - fadt->x_firmware_ctl_l = facs; - fadt->x_firmware_ctl_h = 0; - fadt->x_dsdt_l = dsdt; - fadt->x_dsdt_h = 0; - - fadt->x_pm1a_evt_blk.space_id = 1; - fadt->x_pm1a_evt_blk.bit_width = 32; - fadt->x_pm1a_evt_blk.bit_offset = 0; - fadt->x_pm1a_evt_blk.access_size = 0; - fadt->x_pm1a_evt_blk.addrl = pm_base; - fadt->x_pm1a_evt_blk.addrh = 0x0; - - fadt->x_pm1b_evt_blk.space_id = 1; - fadt->x_pm1b_evt_blk.bit_width = 4; - fadt->x_pm1b_evt_blk.bit_offset = 0; - fadt->x_pm1b_evt_blk.access_size = 0; - fadt->x_pm1b_evt_blk.addrl = 0x0; - fadt->x_pm1b_evt_blk.addrh = 0x0; - - fadt->x_pm1a_cnt_blk.space_id = 1; - fadt->x_pm1a_cnt_blk.bit_width = 16; - fadt->x_pm1a_cnt_blk.bit_offset = 0; - fadt->x_pm1a_cnt_blk.access_size = 0; - fadt->x_pm1a_cnt_blk.addrl = pm_base + 4; - fadt->x_pm1a_cnt_blk.addrh = 0x0; - - fadt->x_pm1b_cnt_blk.space_id = 1; - fadt->x_pm1b_cnt_blk.bit_width = 2; - fadt->x_pm1b_cnt_blk.bit_offset = 0; - fadt->x_pm1b_cnt_blk.access_size = 0; - fadt->x_pm1b_cnt_blk.addrl = 0x0; - fadt->x_pm1b_cnt_blk.addrh = 0x0; - - fadt->x_pm2_cnt_blk.space_id = 1; - fadt->x_pm2_cnt_blk.bit_width = 0; - fadt->x_pm2_cnt_blk.bit_offset = 0; - fadt->x_pm2_cnt_blk.access_size = 0; - fadt->x_pm2_cnt_blk.addrl = 0x0; - fadt->x_pm2_cnt_blk.addrh = 0x0; - - fadt->x_pm_tmr_blk.space_id = 1; - fadt->x_pm_tmr_blk.bit_width = 32; - fadt->x_pm_tmr_blk.bit_offset = 0; - fadt->x_pm_tmr_blk.access_size = 0; - fadt->x_pm_tmr_blk.addrl = pm_base + 0x08; - fadt->x_pm_tmr_blk.addrh = 0x0; - - fadt->x_gpe0_blk.space_id = 1; - fadt->x_gpe0_blk.bit_width = 32; - fadt->x_gpe0_blk.bit_offset = 0; - fadt->x_gpe0_blk.access_size = 0; - fadt->x_gpe0_blk.addrl = pm_base + 0x20; - fadt->x_gpe0_blk.addrh = 0x0; - - fadt->x_gpe1_blk.space_id = 1; - fadt->x_gpe1_blk.bit_width = 64; - fadt->x_gpe1_blk.bit_offset = 16; - fadt->x_gpe1_blk.access_size = 0; - fadt->x_gpe1_blk.addrl = pm_base + 0xb0; - fadt->x_gpe1_blk.addrh = 0x0; -#endif - header->checksum = acpi_checksum((void *)fadt, header->length); -} diff --git a/src/southbridge/nvidia/ck804/ht.c b/src/southbridge/nvidia/ck804/ht.c deleted file mode 100644 index 2925b05068..0000000000 --- a/src/southbridge/nvidia/ck804/ht.c +++ /dev/null @@ -1,74 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2004 Tyan Computer - * Written by Yinghai Lu for Tyan Computer. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include -#include -#include -#include -#include "chip.h" - -#if CONFIG(HAVE_ACPI_TABLES) - -unsigned long acpi_fill_mcfg(unsigned long current) -{ - struct device *dev; - unsigned long mcfg_base; - - dev = pcidev_on_root(0x0, 0); - if (!dev) - return current; - - mcfg_base = pci_read_config16(dev, 0x90); - if ((mcfg_base & 0x1000) == 0) - return current; - - mcfg_base = (mcfg_base & 0xf) << 28; - - printk(BIOS_INFO, "mcfg_base %lx.\n", mcfg_base); - - current += acpi_create_mcfg_mmconfig((acpi_mcfg_mmconfig_t *) - current, mcfg_base, 0x0, 0x0, 0xff); - return current; -} - -#endif - -static void ht_init(struct device *dev) -{ - u32 htmsi; - - /* Enable HT MSI Mapping in capability register */ - htmsi = pci_read_config32(dev, 0xe0); - htmsi |= (1 << 16); - pci_write_config32(dev, 0xe0, htmsi); -} - -static struct device_operations ht_ops = { - .read_resources = pci_dev_read_resources, - .set_resources = pci_dev_set_resources, - .enable_resources = pci_dev_enable_resources, - .init = ht_init, - .scan_bus = 0, - .ops_pci = &ck804_pci_ops, -}; - -static const struct pci_driver ht_driver __pci_driver = { - .ops = &ht_ops, - .vendor = PCI_VENDOR_ID_NVIDIA, - .device = PCI_DEVICE_ID_NVIDIA_CK804_HT, -}; diff --git a/src/southbridge/nvidia/ck804/ide.c b/src/southbridge/nvidia/ck804/ide.c deleted file mode 100644 index a4b5475ca0..0000000000 --- a/src/southbridge/nvidia/ck804/ide.c +++ /dev/null @@ -1,73 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2004 Tyan Computer - * Written by Yinghai Lu for Tyan Computer. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include -#include -#include -#include "chip.h" - -static void ide_init(struct device *dev) -{ - struct southbridge_nvidia_ck804_config *conf; - u32 dword; - u16 word; - u8 byte; - - conf = dev->chip_info; - - word = pci_read_config16(dev, 0x50); - /* Ensure prefetch is disabled. */ - word &= ~((1 << 15) | (1 << 13)); - if (conf->ide1_enable) { - /* Enable secondary IDE interface. */ - word |= (1 << 0); - printk(BIOS_DEBUG, "IDE1\t"); - } - if (conf->ide0_enable) { - /* Enable primary IDE interface. */ - word |= (1 << 1); - printk(BIOS_DEBUG, "IDE0\n"); - } - - word |= (1 << 12); - word |= (1 << 14); - - pci_write_config16(dev, 0x50, word); - - byte = 0x20; /* Latency: 64 --> 32 */ - pci_write_config8(dev, 0xd, byte); - - dword = pci_read_config32(dev, 0xf8); - dword |= 12; - pci_write_config32(dev, 0xf8, dword); -} - -static struct device_operations ide_ops = { - .read_resources = pci_dev_read_resources, - .set_resources = pci_dev_set_resources, - .enable_resources = pci_dev_enable_resources, - .init = ide_init, - .scan_bus = 0, - .ops_pci = &ck804_pci_ops, -}; - -static const struct pci_driver ide_driver __pci_driver = { - .ops = &ide_ops, - .vendor = PCI_VENDOR_ID_NVIDIA, - .device = PCI_DEVICE_ID_NVIDIA_CK804_IDE, -}; diff --git a/src/southbridge/nvidia/ck804/lpc.c b/src/southbridge/nvidia/ck804/lpc.c deleted file mode 100644 index b8aec2667d..0000000000 --- a/src/southbridge/nvidia/ck804/lpc.c +++ /dev/null @@ -1,348 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2015 Timothy Pearson , Raptor Engineering - * Copyright (C) 2003 Linux Networx - * Copyright (C) 2003 SuSE Linux AG - * Copyright (C) 2004 Tyan Computer - * Written by Yinghai Lu for Tyan Computer. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include "chip.h" - -#define NMI_OFF 0 - -// Power restoration control register is at 0x7a -#define PREVIOUS_POWER_STATE 0x7A - - // Auxiliary power control register possibly located at 0xe3 -#define PREVIOUS_POWER_STATE_AUX 0xe3 - -#define MAINBOARD_POWER_OFF 0 -#define MAINBOARD_POWER_ON 1 -#define SLOW_CPU_OFF 0 -#define SLOW_CPU__ON 1 - -static void lpc_common_init(struct device *dev) -{ - u32 dword; - struct resource *res; - - /* I/O APIC initialization. */ - res = find_resource(dev, PCI_BASE_ADDRESS_1); /* IOAPIC */ - ASSERT(res != NULL); - setup_ioapic(res2mmio(res, 0, 0), 0); /* Don't rename IOAPIC ID. */ - -#if 1 - dword = pci_read_config32(dev, 0xe4); - dword |= (1 << 23); - pci_write_config32(dev, 0xe4, dword); -#endif -} - -static void lpc_slave_init(struct device *dev) -{ - lpc_common_init(dev); -} - -static void rom_dummy_write(struct device *dev) -{ - u8 old, new; - u8 *p; - - old = pci_read_config8(dev, 0x88); - new = old | 0xc0; - if (new != old) - pci_write_config8(dev, 0x88, new); - /* Enable write. */ - old = pci_read_config8(dev, 0x6d); - new = old | 0x01; - if (new != old) - pci_write_config8(dev, 0x6d, new); - - /* Dummy write. */ - p = (u8 *) 0xffffffe0; - old = 0; - *p = old; - old = *p; - - /* Disable write. */ - old = pci_read_config8(dev, 0x6d); - new = old & 0xfe; - if (new != old) - pci_write_config8(dev, 0x6d, new); -} - -unsigned int pm_base = 0; - -static void lpc_init(struct device *dev) -{ - u8 byte, byte_old; - int on, nmi_option; - - lpc_common_init(dev); - - pm_base = pci_read_config32(dev, 0x60) & 0xff00; - printk(BIOS_INFO, "%s: pm_base = %x\n", __func__, pm_base); - - /* Power after power fail */ - on = CONFIG_MAINBOARD_POWER_FAILURE_STATE; - get_option(&on, "power_on_after_fail"); - byte = pci_read_config8(dev, PREVIOUS_POWER_STATE); - byte &= ~0x45; - if (!on) - byte |= 0x45; - pci_write_config8(dev, PREVIOUS_POWER_STATE, byte); - printk(BIOS_INFO, "set power %s after power fail\n", on ? "on" : "off"); - - /* Throttle the CPU speed down for testing. */ - on = SLOW_CPU_OFF; - get_option(&on, "slow_cpu"); - if (on) { - u16 pm10_bar; - pm10_bar = (pci_read_config16(dev, 0x60) & 0xff00); - outl(((on << 1) + 0x10), (pm10_bar + 0x10)); - inl(pm10_bar + 0x10); - on = 8 - on; - printk(BIOS_DEBUG, "Throttling CPU %2d.%1.1d percent.\n", - (on * 12) + (on >> 1), (on & 1) * 5); - } - - /* Set up NMI on errors. */ - byte = inb(0x70); /* RTC70 */ - byte_old = byte; - nmi_option = NMI_OFF; - get_option(&nmi_option, "nmi"); - if (nmi_option) - byte &= ~(1 << 7); /* Set NMI. */ - else - byte |= (1 << 7); /* Can't mask NMI from PCI-E and NMI_NOW. */ - if (byte != byte_old) - outb(byte, 0x70); - - /* Initialize the real time clock (RTC). */ - cmos_init(0); - - /* Initialize ISA DMA. */ - isa_dma_init(); - - rom_dummy_write(dev); -} - -static void ck804_lpc_read_resources(struct device *dev) -{ - struct resource *res; - unsigned long index; - - /* Get the normal PCI resources of this device. */ - /* We got one for APIC, or one more for TRAP. */ - pci_dev_read_resources(dev); - - /* HPET */ - pci_get_resource(dev, 0x44); - - /* Get resource for ACPI, SYSTEM_CONTROL, ANALOG_CONTROL. */ - for (index = 0x60; index <= 0x68; index += 4) /* We got another 3. */ - pci_get_resource(dev, index); - compact_resources(dev); - - /* Add an extra subtractive resource for both memory and I/O. */ - res = new_resource(dev, IOINDEX_SUBTRACTIVE(0, 0)); - res->base = 0; - res->size = 0x1000; - res->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE | - IORESOURCE_ASSIGNED | IORESOURCE_FIXED; - - res = new_resource(dev, IOINDEX_SUBTRACTIVE(1, 0)); - res->base = 0xff800000; - res->size = 0x00800000; /* 8 MB for flash */ - res->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE | - IORESOURCE_ASSIGNED | IORESOURCE_FIXED; - - if (dev->device != PCI_DEVICE_ID_NVIDIA_CK804_SLAVE) { - res = find_resource(dev, PCI_BASE_ADDRESS_1); /* IOAPIC */ - if (res) { - res->base = IO_APIC_ADDR; - res->flags |= IORESOURCE_ASSIGNED | IORESOURCE_FIXED; - } - - res = find_resource(dev, 0x44); /* HPET */ - if (res) { - res->base = CONFIG_HPET_ADDRESS; - res->flags |= IORESOURCE_ASSIGNED | IORESOURCE_FIXED; - } - } -} - -static void ck804_lpc_set_resources(struct device *dev) -{ - u8 byte; - struct resource *res; - - pci_dev_set_resources(dev); - - /* APIC */ - res = find_resource(dev, PCI_BASE_ADDRESS_1); - if (res) { - byte = pci_read_config8(dev, 0x74); - byte |= (1 << 1); /* enable access to PCI_BASE_ADDRESS_1 */ - pci_write_config8(dev, 0x74, byte); - pci_write_config32(dev, PCI_BASE_ADDRESS_1, res->base); - res->flags |= IORESOURCE_STORED; - report_resource_stored(dev, res, ""); - byte |= (1 << 0); /* enable decode of IOAPIC space */ - byte &= ~(1 << 1); /* hide PCI_BASE_ADDRESS_1 */ - pci_write_config8(dev, 0x74, byte); - } - - /* HPET */ - res = find_resource(dev, 0x44); - if (res) { - pci_write_config32(dev, 0x44, res->base|1); - res->flags |= IORESOURCE_STORED; - report_resource_stored(dev, res, ""); - } -} - -/** - * Enable resources for children devices. - * - * This function is called by the global enable_resources() indirectly via the - * device_operation::enable_resources() method of devices. - */ -static void ck804_lpc_enable_childrens_resources(struct device *dev) -{ - struct bus *link; - u32 reg, reg_var[4]; - int i, var_num = 0; - - reg = pci_read_config32(dev, 0xa0); - - for (link = dev->link_list; link; link = link->next) { - struct device *child; - for (child = link->children; child; child = child->sibling) { - if (child->enabled && (child->path.type == DEVICE_PATH_PNP)) { - struct resource *res; - for (res = child->resource_list; res; res = res->next) { - unsigned long base, end; /* Don't need long long. */ - if (!(res->flags & IORESOURCE_IO)) - continue; - base = res->base; - end = resource_end(res); - printk(BIOS_DEBUG, "ck804 lpc decode:%s, base=0x%08lx, end=0x%08lx\n", dev_path(child), base, end); - switch (base) { - case 0x3f8: // COM1 - reg |= (1 << 0); - break; - case 0x2f8: // COM2 - reg |= (1 << 1); - break; - case 0x378: // Parallel 1 - reg |= (1 << 24); - break; - case 0x3f0: // FD0 - reg |= (1 << 20); - break; - case 0x220: // Audio 0 - reg |= (1 << 8); - break; - case 0x300: // Midi 0 - reg |= (1 << 12); - break; - } - if (base == 0x290 || base >= 0x400) { - /* Only 4 var; compact them? */ - if (var_num >= 4) - continue; - reg |= (1 << (28 + var_num)); - reg_var[var_num++] = (base & 0xffff) | ((end & 0xffff) << 16); - } - } - } - } - } - pci_write_config32(dev, 0xa0, reg); - for (i = 0; i < var_num; i++) - pci_write_config32(dev, 0xa8 + i * 4, reg_var[i]); -} - -static void ck804_lpc_enable_resources(struct device *dev) -{ - pci_dev_enable_resources(dev); - ck804_lpc_enable_childrens_resources(dev); -} - -#if CONFIG(HAVE_ACPI_TABLES) - -static void southbridge_acpi_fill_ssdt_generator(struct device *device) -{ - amd_generate_powernow(0, 0, 0); -} - -#endif - -static struct device_operations lpc_ops = { - .read_resources = ck804_lpc_read_resources, - .set_resources = ck804_lpc_set_resources, - .enable_resources = ck804_lpc_enable_resources, -#if CONFIG(HAVE_ACPI_TABLES) - .acpi_fill_ssdt_generator = southbridge_acpi_fill_ssdt_generator, - .write_acpi_tables = acpi_write_hpet, -#endif - .init = lpc_init, - .scan_bus = scan_static_bus, - .ops_pci = &ck804_pci_ops, -}; - -static const struct pci_driver lpc_driver __pci_driver = { - .ops = &lpc_ops, - .vendor = PCI_VENDOR_ID_NVIDIA, - .device = PCI_DEVICE_ID_NVIDIA_CK804_LPC, -}; - -static const struct pci_driver lpc_driver_pro __pci_driver = { - .ops = &lpc_ops, - .vendor = PCI_VENDOR_ID_NVIDIA, - .device = PCI_DEVICE_ID_NVIDIA_CK804_PRO, -}; - -static struct device_operations lpc_slave_ops = { - .read_resources = ck804_lpc_read_resources, - .set_resources = pci_dev_set_resources, - .enable_resources = pci_dev_enable_resources, -#if CONFIG(HAVE_ACPI_TABLES) - .write_acpi_tables = acpi_write_hpet, -#endif - .init = lpc_slave_init, - .ops_pci = &ck804_pci_ops, -}; - -static const struct pci_driver lpc_driver_slave __pci_driver = { - .ops = &lpc_slave_ops, - .vendor = PCI_VENDOR_ID_NVIDIA, - .device = PCI_DEVICE_ID_NVIDIA_CK804_SLAVE, -}; diff --git a/src/southbridge/nvidia/ck804/nic.c b/src/southbridge/nvidia/ck804/nic.c deleted file mode 100644 index 5dbb6b4aa9..0000000000 --- a/src/southbridge/nvidia/ck804/nic.c +++ /dev/null @@ -1,126 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2004 Tyan Computer - * Written by Yinghai Lu for Tyan Computer. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include -#include -#include -#include -#include "chip.h" - -static void nic_init(struct device *dev) -{ - u32 dword, old, mac_h = 0, mac_l = 0; - int eeprom_valid = 0; - struct southbridge_nvidia_ck804_config *conf; - static u32 nic_index = 0; - u8 *base; - struct resource *res; - - res = find_resource(dev, 0x10); - base = res2mmio(res, 0, 0); - -#define NvRegPhyInterface 0xC0 -#define PHY_RGMII 0x10000000 - - write32(base + NvRegPhyInterface, PHY_RGMII); - - old = dword = pci_read_config32(dev, 0x30); - dword &= ~(0xf); - dword |= 0xf; - if (old != dword) - pci_write_config32(dev, 0x30, dword); - - conf = dev->chip_info; - - if (conf->mac_eeprom_smbus != 0) { - /* Read MAC address from EEPROM at first. */ - struct device *dev_eeprom; - dev_eeprom = dev_find_slot_on_smbus(conf->mac_eeprom_smbus, - conf->mac_eeprom_addr); - - if (dev_eeprom) { - /* If that is valid we will use that. */ - unsigned char dat[6]; - int i, status; - for (i = 0; i < 6; i++) { - status = smbus_read_byte(dev_eeprom, i); - if (status < 0) - break; - dat[i] = status & 0xff; - } - if (status >= 0) { - mac_l = 0; - for (i = 3; i >= 0; i--) { - mac_l <<= 8; - mac_l += dat[i]; - } - if (mac_l != 0xffffffff) { - mac_l += nic_index; - mac_h = 0; - for (i = 5; i >= 4; i--) { - mac_h <<= 8; - mac_h += dat[i]; - } - eeprom_valid = 1; - } - } - } - } - - /* If that is invalid we will read that from romstrap. */ - if (!eeprom_valid) { - u32 *mac_pos; - mac_pos = (u32 *)0xffffffd0; /* See romstrap.inc and romstrap.ld. */ - mac_l = read32(mac_pos) + nic_index; - mac_h = read32(mac_pos + 1); - } -#if 1 - /* Set that into NIC MMIO. */ -#define NvRegMacAddrA 0xA8 -#define NvRegMacAddrB 0xAC - write32(base + NvRegMacAddrA, mac_l); - write32(base + NvRegMacAddrB, mac_h); -#else - /* Set that into NIC. */ - pci_write_config32(dev, 0xa8, mac_l); - pci_write_config32(dev, 0xac, mac_h); -#endif - - nic_index++; -} - -static struct device_operations nic_ops = { - .read_resources = pci_dev_read_resources, - .set_resources = pci_dev_set_resources, - .enable_resources = pci_dev_enable_resources, - .init = nic_init, - .scan_bus = 0, - .ops_pci = &ck804_pci_ops, -}; - -static const struct pci_driver nic_driver __pci_driver = { - .ops = &nic_ops, - .vendor = PCI_VENDOR_ID_NVIDIA, - .device = PCI_DEVICE_ID_NVIDIA_CK804_NIC, -}; - -static const struct pci_driver nic_bridge_driver __pci_driver = { - .ops = &nic_ops, - .vendor = PCI_VENDOR_ID_NVIDIA, - .device = PCI_DEVICE_ID_NVIDIA_CK804_NIC_BRIDGE, -}; diff --git a/src/southbridge/nvidia/ck804/pci.c b/src/southbridge/nvidia/ck804/pci.c deleted file mode 100644 index d4b074d14b..0000000000 --- a/src/southbridge/nvidia/ck804/pci.c +++ /dev/null @@ -1,80 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2004 Tyan Computer - * Written by Yinghai Lu for Tyan Computer. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include -#include -#include -#include -#include "chip.h" - -static void pci_init(struct device *dev) -{ - u32 dword; - struct device *pci_domain_dev; - struct resource *mem, *pref; - - dword = pci_read_config32(dev, 0x04); - dword |= (1 << 8); /* System error enable */ - dword |= (1 << 30); /* Clear possible errors */ - pci_write_config32(dev, 0x04, dword); - - dword = pci_read_config32(dev, 0x4c); - dword |= 0x00440000; /* TABORT_SER_ENABLE Park Last Enable. */ - pci_write_config32(dev, 0x4c, dword); - - pci_domain_dev = dev->bus->dev; - while (pci_domain_dev) { - if (pci_domain_dev->path.type == DEVICE_PATH_DOMAIN) - break; - pci_domain_dev = pci_domain_dev->bus->dev; - } - - if (!pci_domain_dev) - return; /* Impossible */ - - pref = probe_resource(pci_domain_dev, IOINDEX_SUBTRACTIVE(2,0)); - mem = probe_resource(pci_domain_dev, IOINDEX_SUBTRACTIVE(1,0)); - - if (!mem) - return; /* Impossible */ - - if (!pref || pref->base > mem->base) { - dword = mem->base & (0xffff0000UL); - printk(BIOS_DEBUG, "PCI DOMAIN mem base = 0x%010Lx\n", mem->base); - } else { - dword = pref->base & (0xffff0000UL); - printk(BIOS_DEBUG, "PCI DOMAIN pref base = 0x%010Lx\n", pref->base); - } - - printk(BIOS_DEBUG, "[0x50] <-- 0x%08x\n", dword); - pci_write_config32(dev, 0x50, dword); /* TOM */ -} - -static struct device_operations pci_ops = { - .read_resources = pci_bus_read_resources, - .set_resources = pci_dev_set_resources, - .enable_resources = pci_bus_enable_resources, - .init = pci_init, - .scan_bus = pci_scan_bridge, -}; - -static const struct pci_driver pci_driver __pci_driver = { - .ops = &pci_ops, - .vendor = PCI_VENDOR_ID_NVIDIA, - .device = PCI_DEVICE_ID_NVIDIA_CK804_PCI, -}; diff --git a/src/southbridge/nvidia/ck804/pcie.c b/src/southbridge/nvidia/ck804/pcie.c deleted file mode 100644 index 7bd8324d8c..0000000000 --- a/src/southbridge/nvidia/ck804/pcie.c +++ /dev/null @@ -1,46 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2004 Tyan Computer - * Written by Yinghai Lu for Tyan Computer. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include -#include -#include "chip.h" - -static void pcie_init(struct device *dev) -{ - u32 dword; - - /* Enable PCI error detecting. */ - dword = pci_read_config32(dev, 0x04); - dword |= (1 << 8); /* System error enable */ - dword |= (1 << 30); /* Clear possible errors */ - pci_write_config32(dev, 0x04, dword); -} - -static struct device_operations pcie_ops = { - .read_resources = pci_bus_read_resources, - .set_resources = pci_dev_set_resources, - .enable_resources = pci_bus_enable_resources, - .init = pcie_init, - .scan_bus = pci_scan_bridge, -}; - -static const struct pci_driver pcie_driver __pci_driver = { - .ops = &pcie_ops, - .vendor = PCI_VENDOR_ID_NVIDIA, - .device = PCI_DEVICE_ID_NVIDIA_CK804_PCI_E, -}; diff --git a/src/southbridge/nvidia/ck804/reset.c b/src/southbridge/nvidia/ck804/reset.c deleted file mode 100644 index f828c53e71..0000000000 --- a/src/southbridge/nvidia/ck804/reset.c +++ /dev/null @@ -1,30 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2004 Tyan Computer - * Written by Yinghai Lu for Tyan Computer. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#define __SIMPLE_DEVICE__ - -#include -#include - -#include "../../../northbridge/amd/amdk8/reset_test.c" - -void do_board_reset(void) -{ - set_bios_reset(); - /* Try rebooting through port 0xcf9. */ - outb((0 << 3) | (0 << 2) | (1 << 1), 0xcf9); - outb((0 << 3) | (1 << 2) | (1 << 1), 0xcf9); -} diff --git a/src/southbridge/nvidia/ck804/romstrap.S b/src/southbridge/nvidia/ck804/romstrap.S deleted file mode 100644 index 5a20107376..0000000000 --- a/src/southbridge/nvidia/ck804/romstrap.S +++ /dev/null @@ -1,55 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2004 Tyan Computer - * Written by Yinghai Lu for Tyan Computer. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - - .section ".romstrap", "a", @progbits - - - .align 16 - .globl __romstrap_start -__romstrap_start: -rstables: - .long 0x2b16d065 - .long 0x0 - .long 0x0 - .long linkedlist - -linkedlist: - .long 0x0003001C // 10h - .long 0x08000000 // 14h - .long 0x00000000 // 18h - .long 0xFFFFFFFF // 1Ch - - .long 0xFFFFFFFF // 20h - .long 0xFFFFFFFF // 24h - .long 0xFFFFFFFF // 28h - .long 0xFFFFFFFF // 2Ch - - .long 0x81543266 // 30h, MAC address low 4 byte ---> keep it in 0xffffffd0 - .long 0x000000E0 // 34h, MAC address high 4 byte - - .long 0x002309CE // 38h, UUID low 4 byte - .long 0x00E08100 // 3Ch, UUID high 4 byte - -rspointers: - .long rstables // It will be 0xffffffe0 - .long rstables - .long rstables - .long rstables - - .globl __romstrap_end - -__romstrap_end: -.previous diff --git a/src/southbridge/nvidia/ck804/romstrap.ld b/src/southbridge/nvidia/ck804/romstrap.ld deleted file mode 100644 index 6b14be9d8a..0000000000 --- a/src/southbridge/nvidia/ck804/romstrap.ld +++ /dev/null @@ -1,22 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2004 Tyan Computer - * Written by Yinghai Lu for Tyan Computer. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -SECTIONS { - . = (0xffffffff - 0x10) - (__romstrap_end - __romstrap_start) + 1; - .romstrap (.): { - KEEP(*(.romstrap)) - } -} diff --git a/src/southbridge/nvidia/ck804/sata.c b/src/southbridge/nvidia/ck804/sata.c deleted file mode 100644 index 9abd6d26ba..0000000000 --- a/src/southbridge/nvidia/ck804/sata.c +++ /dev/null @@ -1,146 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2004 Tyan Computer - * Written by Yinghai Lu for Tyan Computer. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include -#include -#include -#include -#include "chip.h" - -#ifndef CK804_SATA_RESET_FOR_ATAPI -#define CK804_SATA_RESET_FOR_ATAPI 0 -#endif - -#if CK804_SATA_RESET_FOR_ATAPI -static void sata_com_reset(struct device *dev, unsigned int reset) -// reset = 1 : reset -// reset = 0 : clear -{ - u32 *base; - u32 dword; - int loop; - - base = (u32 *) pci_read_config32(dev, 0x24); - - printk(BIOS_DEBUG, "base = %08lx\n", base); - - if (reset) { - *(base + 4) = 0xffffffff; - *(base + 0x44) = 0xffffffff; - } - - dword = *(base + 8); - dword &= ~(0xf); - dword |= reset; - - *(base + 8) = dword; - *(base + 0x48) = dword; - - if (reset) - return; - - dword = *(base + 0); - printk(BIOS_DEBUG, "*(base+0)=%08x\n", dword); - if (dword == 0x113) { - loop = 200000; // 2 - do { - dword = *(base + 4); - if ((dword & 0x10000) != 0) - break; - udelay(10); - } while (--loop > 0); - printk(BIOS_DEBUG, "loop=%d, *(base+4)=%08x\n", loop, dword); - } - - dword = *(base + 0x40); - printk(BIOS_DEBUG, "*(base+0x40)=%08x\n", dword); - if (dword == 0x113) { - loop = 200000; //2 - do { - dword = *(base + 0x44); - if ((dword & 0x10000) != 0) - break; - udelay(10); - } while (--loop > 0); - printk(BIOS_DEBUG, "loop=%d, *(base+0x44)=%08x\n", loop, dword); - } -} -#endif - -static void sata_init(struct device *dev) -{ - u32 dword; - struct southbridge_nvidia_ck804_config *conf; - - conf = dev->chip_info; - - dword = pci_read_config32(dev, 0x50); - /* Ensure prefetch is disabled. */ - dword &= ~((1 << 15) | (1 << 13)); - if (conf->sata1_enable) { - /* Enable secondary SATA interface. */ - dword |= (1 << 0); - printk(BIOS_DEBUG, "SATA S\t"); - } - if (conf->sata0_enable) { - /* Enable primary SATA interface. */ - dword |= (1 << 1); - printk(BIOS_DEBUG, "SATA P\n"); - } - -#if 1 - /* DO NOT relay OK and PAGE_FRNDLY_DTXFR_CNT. */ - dword &= ~(0x1f << 24); - dword |= (0x15 << 24); -#endif - pci_write_config32(dev, 0x50, dword); - - dword = pci_read_config32(dev, 0xf8); - dword |= 2; - pci_write_config32(dev, 0xf8, dword); - -#if CK804_SATA_RESET_FOR_ATAPI - dword = pci_read_config32(dev, 0xac); - dword &= ~((1 << 13) | (1 << 14)); - dword |= (1 << 13) | (0 << 14); - pci_write_config32(dev, 0xac, dword); - - sata_com_reset(dev, 1); /* For discover some s-atapi device. */ -#endif -} - -static struct device_operations sata_ops = { - .read_resources = pci_dev_read_resources, - .set_resources = pci_dev_set_resources, - .enable_resources = pci_dev_enable_resources, - .init = sata_init, - .scan_bus = 0, - .ops_pci = &ck804_pci_ops, -}; - -static const struct pci_driver sata0_driver __pci_driver = { - .ops = &sata_ops, - .vendor = PCI_VENDOR_ID_NVIDIA, - .device = PCI_DEVICE_ID_NVIDIA_CK804_SATA0, -}; - -static const struct pci_driver sata1_driver __pci_driver = { - .ops = &sata_ops, - .vendor = PCI_VENDOR_ID_NVIDIA, - .device = PCI_DEVICE_ID_NVIDIA_CK804_SATA1, -}; diff --git a/src/southbridge/nvidia/ck804/smbus.c b/src/southbridge/nvidia/ck804/smbus.c deleted file mode 100644 index 9737d0070f..0000000000 --- a/src/southbridge/nvidia/ck804/smbus.c +++ /dev/null @@ -1,101 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2004 Tyan Computer - * Written by Yinghai Lu for Tyan Computer. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include -#include -#include "chip.h" -#include "smbus.h" - -static int lsmbus_recv_byte(struct device *dev) -{ - unsigned int device; - struct resource *res; - struct bus *pbus; - - device = dev->path.i2c.device; - pbus = get_pbus_smbus(dev); - - res = find_resource(pbus->dev, 0x20 + (pbus->link_num * 4)); - - return do_smbus_recv_byte(res->base, device); -} - -static int lsmbus_send_byte(struct device *dev, u8 val) -{ - unsigned int device; - struct resource *res; - struct bus *pbus; - - device = dev->path.i2c.device; - pbus = get_pbus_smbus(dev); - - res = find_resource(pbus->dev, 0x20 + (pbus->link_num * 4)); - - return do_smbus_send_byte(res->base, device, val); -} - -static int lsmbus_read_byte(struct device *dev, u8 address) -{ - unsigned int device; - struct resource *res; - struct bus *pbus; - - device = dev->path.i2c.device; - pbus = get_pbus_smbus(dev); - - res = find_resource(pbus->dev, 0x20 + (pbus->link_num * 4)); - - return do_smbus_read_byte(res->base, device, address); -} - -static int lsmbus_write_byte(struct device *dev, u8 address, u8 val) -{ - unsigned int device; - struct resource *res; - struct bus *pbus; - - device = dev->path.i2c.device; - pbus = get_pbus_smbus(dev); - - res = find_resource(pbus->dev, 0x20 + (pbus->link_num * 4)); - - return do_smbus_write_byte(res->base, device, address, val); -} - -static struct smbus_bus_operations lops_smbus_bus = { - .recv_byte = lsmbus_recv_byte, - .send_byte = lsmbus_send_byte, - .read_byte = lsmbus_read_byte, - .write_byte = lsmbus_write_byte, -}; - -static struct device_operations smbus_ops = { - .read_resources = pci_dev_read_resources, - .set_resources = pci_dev_set_resources, - .enable_resources = pci_dev_enable_resources, - .init = 0, - .scan_bus = scan_smbus, - .ops_pci = &ck804_pci_ops, - .ops_smbus_bus = &lops_smbus_bus, -}; - -static const struct pci_driver smbus_driver __pci_driver = { - .ops = &smbus_ops, - .vendor = PCI_VENDOR_ID_NVIDIA, - .device = PCI_DEVICE_ID_NVIDIA_CK804_SM, -}; diff --git a/src/southbridge/nvidia/ck804/smbus.h b/src/southbridge/nvidia/ck804/smbus.h deleted file mode 100644 index 9aad5e14f0..0000000000 --- a/src/southbridge/nvidia/ck804/smbus.h +++ /dev/null @@ -1,185 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2004 Tyan Computer - * Written by Yinghai Lu for Tyan Computer. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include - -#define SMBHSTSTAT 0x1 -#define SMBHSTPRTCL 0x0 -#define SMBHSTCMD 0x3 -#define SMBXMITADD 0x2 -#define SMBHSTDAT0 0x4 -#define SMBHSTDAT1 0x5 - -/* - * Between 1-10 seconds, We should never timeout normally. - * Longer than this is just painful when a timeout condition occurs. - */ -#define SMBUS_TIMEOUT (100 * 1000 * 10) - -static inline void smbus_delay(void) -{ - outb(0x80, 0x80); -} - -static int smbus_wait_until_done(unsigned int smbus_io_base) -{ - unsigned long loops; - loops = SMBUS_TIMEOUT; - do { - unsigned char val; - smbus_delay(); - val = inb(smbus_io_base + SMBHSTSTAT); - if ((val & 0xff) != 0) - return 0; - } while (--loops); - return -3; -} - - -/* Platform has severe issues placing non-inlined functions in headers. */ -#if ENV_RAMSTAGE -static int do_smbus_recv_byte(unsigned int smbus_io_base, unsigned int device) -{ - unsigned char global_status_register, byte; - - /* Set the device I'm talking to. */ - outb(((device & 0x7f) << 1) | 1, smbus_io_base + SMBXMITADD); - smbus_delay(); - - /* Set the command/address. */ - outb(0, smbus_io_base + SMBHSTCMD); - smbus_delay(); - - /* Byte data recv. */ - outb(0x05, smbus_io_base + SMBHSTPRTCL); - smbus_delay(); - - /* Poll for transaction completion. */ - if (smbus_wait_until_done(smbus_io_base) < 0) - return -3; - - /* Lose check. */ - global_status_register = inb(smbus_io_base + SMBHSTSTAT) & 0x80; - - /* Read results of transaction. */ - byte = inb(smbus_io_base + SMBHSTDAT0); - - /* Lose check, otherwise it should be 0. */ - if (global_status_register != 0x80) - return -1; - - return byte; -} - -static int do_smbus_send_byte(unsigned int smbus_io_base, unsigned int device, - unsigned char val) -{ - unsigned int global_status_register; - - outb(val, smbus_io_base + SMBHSTDAT0); - smbus_delay(); - - /* Set the device I'm talking to. */ - outb(((device & 0x7f) << 1) | 0, smbus_io_base + SMBXMITADD); - smbus_delay(); - - outb(0, smbus_io_base + SMBHSTCMD); - smbus_delay(); - - /* Set up for a byte data write. */ - outb(0x04, smbus_io_base + SMBHSTPRTCL); - smbus_delay(); - - /* Poll for transaction completion. */ - if (smbus_wait_until_done(smbus_io_base) < 0) - return -3; - - /* Lose check. */ - global_status_register = inb(smbus_io_base + SMBHSTSTAT) & 0x80; - - if (global_status_register != 0x80) - return -1; - - return 0; -} -#endif /* ENV_RAMSTAGE */ - -static int do_smbus_read_byte(unsigned int smbus_io_base, unsigned int device, - unsigned int address) -{ - unsigned char global_status_register, byte; - - /* Set the device I'm talking to. */ - outb(((device & 0x7f) << 1) | 1, smbus_io_base + SMBXMITADD); - smbus_delay(); - - /* Set the command/address. */ - outb(address & 0xff, smbus_io_base + SMBHSTCMD); - smbus_delay(); - - /* Byte data read. */ - outb(0x07, smbus_io_base + SMBHSTPRTCL); - smbus_delay(); - - /* Poll for transaction completion. */ - if (smbus_wait_until_done(smbus_io_base) < 0) - return -3; - - /* Lose check. */ - global_status_register = inb(smbus_io_base + SMBHSTSTAT) & 0x80; - - /* Read results of transaction. */ - byte = inb(smbus_io_base + SMBHSTDAT0); - - /* Lose check, otherwise it should be 0. */ - if (global_status_register != 0x80) - return -1; - - return byte; -} - -static int do_smbus_write_byte(unsigned int smbus_io_base, unsigned int device, - unsigned int address, unsigned char val) -{ - unsigned int global_status_register; - - outb(val, smbus_io_base + SMBHSTDAT0); - smbus_delay(); - - /* Set the device I'm talking to. */ - outb(((device & 0x7f) << 1) | 0, smbus_io_base + SMBXMITADD); - smbus_delay(); - - outb(address & 0xff, smbus_io_base + SMBHSTCMD); - smbus_delay(); - - /* Set up for a byte data write. */ - outb(0x06, smbus_io_base + SMBHSTPRTCL); - smbus_delay(); - - /* Poll for transaction completion. */ - if (smbus_wait_until_done(smbus_io_base) < 0) - return -3; - - /* Lose check. */ - global_status_register = inb(smbus_io_base + SMBHSTSTAT) & 0x80; - - if (global_status_register != 0x80) - return -1; - - return 0; -} diff --git a/src/southbridge/nvidia/ck804/usb.c b/src/southbridge/nvidia/ck804/usb.c deleted file mode 100644 index f7c315af91..0000000000 --- a/src/southbridge/nvidia/ck804/usb.c +++ /dev/null @@ -1,57 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2004 Tyan Computer - * Written by Yinghai Lu for Tyan Computer. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include -#include -#include "chip.h" - -static void usb1_init(struct device *dev) -{ - struct southbridge_nvidia_ck804_config const *conf = dev->chip_info; - - if (!conf->usb1_hc_reset) - return; - - /* - * Somehow the warm reset does not really reset the USB - * controller. Later, during boot, when the Bus Master bit is - * set, the USB controller trashes the memory, causing weird - * misbehavior. Was detected on Sun Ultra40, where mptable - * was damaged. - */ - u32 bar0 = pci_read_config32(dev, 0x10); - u32 *regs = (u32 *) (bar0 & ~0xfff); - - /* OHCI USB HCCommandStatus Register, HostControllerReset bit */ - regs[2] |= 1; -} - -static struct device_operations usb_ops = { - .read_resources = pci_dev_read_resources, - .set_resources = pci_dev_set_resources, - .enable_resources = pci_dev_enable_resources, - .init = usb1_init, - .scan_bus = 0, - .ops_pci = &ck804_pci_ops, -}; - -static const struct pci_driver usb_driver __pci_driver = { - .ops = &usb_ops, - .vendor = PCI_VENDOR_ID_NVIDIA, - .device = PCI_DEVICE_ID_NVIDIA_CK804_USB, -}; diff --git a/src/southbridge/nvidia/ck804/usb2.c b/src/southbridge/nvidia/ck804/usb2.c deleted file mode 100644 index 47643aefbf..0000000000 --- a/src/southbridge/nvidia/ck804/usb2.c +++ /dev/null @@ -1,45 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2004 Tyan Computer - * Written by Yinghai Lu for Tyan Computer. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include -#include -#include "chip.h" - -static void usb2_init(struct device *dev) -{ - u32 dword; - - dword = pci_read_config32(dev, 0xf8); - dword |= 40; - pci_write_config32(dev, 0xf8, dword); -} - -static struct device_operations usb2_ops = { - .read_resources = pci_dev_read_resources, - .set_resources = pci_dev_set_resources, - .enable_resources = pci_dev_enable_resources, - .init = usb2_init, - .scan_bus = 0, - .ops_pci = &ck804_pci_ops, -}; - -static const struct pci_driver usb2_driver __pci_driver = { - .ops = &usb2_ops, - .vendor = PCI_VENDOR_ID_NVIDIA, - .device = PCI_DEVICE_ID_NVIDIA_CK804_USB2, -}; From 1ca978ee6529251ed80b47da679be7adc75fa46a Mon Sep 17 00:00:00 2001 From: Arthur Heymans Date: Tue, 19 Nov 2019 17:28:43 +0100 Subject: [PATCH 0300/1242] sb/nvidia/mcp55: Drop support MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Relocatable ramstage, postcar stage and C_ENVIRONMENT_BOOTBLOCK are now mandatory features, which platforms using this code lack. Change-Id: I7cd33316140f2cdc83949aa5db7e6f1565982543 Signed-off-by: Arthur Heymans Reviewed-on: https://review.coreboot.org/c/coreboot/+/36973 Reviewed-by: Kyösti Mälkki Reviewed-by: Angel Pons Reviewed-by: HAOUAS Elyes Tested-by: build bot (Jenkins) --- src/southbridge/nvidia/mcp55/Kconfig | 45 -- src/southbridge/nvidia/mcp55/Makefile.inc | 33 -- src/southbridge/nvidia/mcp55/azalia.c | 275 ------------ src/southbridge/nvidia/mcp55/bootblock.c | 49 --- src/southbridge/nvidia/mcp55/chip.h | 31 -- src/southbridge/nvidia/mcp55/early_ctrl.c | 45 -- .../nvidia/mcp55/early_setup_car.c | 402 ------------------ src/southbridge/nvidia/mcp55/early_setup_ss.h | 217 ---------- src/southbridge/nvidia/mcp55/early_smbus.c | 96 ----- .../nvidia/mcp55/enable_usbdebug.c | 43 -- src/southbridge/nvidia/mcp55/fadt.c | 169 -------- src/southbridge/nvidia/mcp55/ht.c | 47 -- src/southbridge/nvidia/mcp55/ide.c | 78 ---- src/southbridge/nvidia/mcp55/lpc.c | 284 ------------- src/southbridge/nvidia/mcp55/mcp55.c | 234 ---------- src/southbridge/nvidia/mcp55/mcp55.h | 49 --- src/southbridge/nvidia/mcp55/nic.c | 201 --------- src/southbridge/nvidia/mcp55/pci.c | 97 ----- src/southbridge/nvidia/mcp55/pcie.c | 61 --- src/southbridge/nvidia/mcp55/reset.c | 34 -- src/southbridge/nvidia/mcp55/romstrap.S | 55 --- src/southbridge/nvidia/mcp55/romstrap.ld | 23 - src/southbridge/nvidia/mcp55/sata.c | 89 ---- src/southbridge/nvidia/mcp55/smbus.c | 132 ------ src/southbridge/nvidia/mcp55/smbus.h | 173 -------- src/southbridge/nvidia/mcp55/usb.c | 39 -- src/southbridge/nvidia/mcp55/usb2.c | 49 --- 27 files changed, 3050 deletions(-) delete mode 100644 src/southbridge/nvidia/mcp55/Kconfig delete mode 100644 src/southbridge/nvidia/mcp55/Makefile.inc delete mode 100644 src/southbridge/nvidia/mcp55/azalia.c delete mode 100644 src/southbridge/nvidia/mcp55/bootblock.c delete mode 100644 src/southbridge/nvidia/mcp55/chip.h delete mode 100644 src/southbridge/nvidia/mcp55/early_ctrl.c delete mode 100644 src/southbridge/nvidia/mcp55/early_setup_car.c delete mode 100644 src/southbridge/nvidia/mcp55/early_setup_ss.h delete mode 100644 src/southbridge/nvidia/mcp55/early_smbus.c delete mode 100644 src/southbridge/nvidia/mcp55/enable_usbdebug.c delete mode 100644 src/southbridge/nvidia/mcp55/fadt.c delete mode 100644 src/southbridge/nvidia/mcp55/ht.c delete mode 100644 src/southbridge/nvidia/mcp55/ide.c delete mode 100644 src/southbridge/nvidia/mcp55/lpc.c delete mode 100644 src/southbridge/nvidia/mcp55/mcp55.c delete mode 100644 src/southbridge/nvidia/mcp55/mcp55.h delete mode 100644 src/southbridge/nvidia/mcp55/nic.c delete mode 100644 src/southbridge/nvidia/mcp55/pci.c delete mode 100644 src/southbridge/nvidia/mcp55/pcie.c delete mode 100644 src/southbridge/nvidia/mcp55/reset.c delete mode 100644 src/southbridge/nvidia/mcp55/romstrap.S delete mode 100644 src/southbridge/nvidia/mcp55/romstrap.ld delete mode 100644 src/southbridge/nvidia/mcp55/sata.c delete mode 100644 src/southbridge/nvidia/mcp55/smbus.c delete mode 100644 src/southbridge/nvidia/mcp55/smbus.h delete mode 100644 src/southbridge/nvidia/mcp55/usb.c delete mode 100644 src/southbridge/nvidia/mcp55/usb2.c diff --git a/src/southbridge/nvidia/mcp55/Kconfig b/src/southbridge/nvidia/mcp55/Kconfig deleted file mode 100644 index c70161e7ff..0000000000 --- a/src/southbridge/nvidia/mcp55/Kconfig +++ /dev/null @@ -1,45 +0,0 @@ -config SOUTHBRIDGE_NVIDIA_MCP55 - bool - select HAVE_USBDEBUG - select IOAPIC - select HAVE_POWER_STATE_AFTER_FAILURE - -if SOUTHBRIDGE_NVIDIA_MCP55 - -config BOOTBLOCK_SOUTHBRIDGE_INIT - string - default "southbridge/nvidia/mcp55/bootblock.c" - -config EHCI_BAR - hex - default 0xfef00000 - -config MCP55_USE_NIC - bool - default n - -config MCP55_USE_AZA - bool - default n - -config MCP55_NUM - int - default 1 - -config MCP55_PCI_E_X_0 - int - default 4 - -config MCP55_PCI_E_X_1 - int - default 4 - -config MCP55_PCI_E_X_2 - int - default 4 - -config MCP55_PCI_E_X_3 - int - default 4 - -endif diff --git a/src/southbridge/nvidia/mcp55/Makefile.inc b/src/southbridge/nvidia/mcp55/Makefile.inc deleted file mode 100644 index d9c4134453..0000000000 --- a/src/southbridge/nvidia/mcp55/Makefile.inc +++ /dev/null @@ -1,33 +0,0 @@ -ifeq ($(CONFIG_SOUTHBRIDGE_NVIDIA_MCP55),y) - -ramstage-y += mcp55.c -ramstage-y += azalia.c -ramstage-y += ht.c -ramstage-y += ide.c -ramstage-y += lpc.c -ramstage-y += nic.c -ramstage-y += pci.c -ramstage-y += pcie.c -ramstage-y += sata.c -ramstage-y += smbus.c -ramstage-y += usb2.c -ramstage-y += usb.c - -ramstage-$(CONFIG_HAVE_ACPI_TABLES) += fadt.c - -ramstage-y += reset.c - -bootblock-y += enable_usbdebug.c -romstage-y += enable_usbdebug.c -ramstage-y += enable_usbdebug.c -romstage-y += early_smbus.c -romstage-y += early_ctrl.c - -ifeq ($(CONFIG_MCP55_USE_AZA),y) -ramstage-srcs += src/mainboard/$(MAINBOARDDIR)/hda_verb.c -endif - -bootblock-y += romstrap.ld -bootblock-y += romstrap.S - -endif diff --git a/src/southbridge/nvidia/mcp55/azalia.c b/src/southbridge/nvidia/mcp55/azalia.c deleted file mode 100644 index f393297d2c..0000000000 --- a/src/southbridge/nvidia/mcp55/azalia.c +++ /dev/null @@ -1,275 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2008 Advanced Micro Devices, Inc. - * Copyright (C) 2008-2010 coresystems GmbH - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include "mcp55.h" - -#if CONFIG(MCP55_USE_AZA) -#define HDA_ICII_REG 0x68 -#define HDA_ICII_BUSY (1 << 0) -#define HDA_ICII_VALID (1 << 1) - -static int set_bits(void *port, u32 mask, u32 val) -{ - u32 reg32; - int count; - - /* Write (val & mask) to port. */ - val &= mask; - reg32 = read32(port); - reg32 &= ~mask; - reg32 |= val; - write32(port, reg32); - - /* Wait for readback of register to match what was written to it. */ - count = 50; - do { - /* Wait 1ms based on BKDG wait time. */ - mdelay(1); - reg32 = read32(port); - reg32 &= mask; - } while ((reg32 != val) && --count); - - /* Timeout occurred. */ - if (!count) - return -1; - return 0; -} - -static int codec_detect(u8 *base) -{ - u32 reg32; - - /* Set bit 0 to 0 to enter reset state (BAR + 0x8)[0]. */ - if (set_bits(base + 0x08, 1, 0) == -1) - goto no_codec; - - /* Set bit 0 to 1 to exit reset state (BAR + 0x8)[0]. */ - if (set_bits(base + 0x08, 1, 1) == -1) - goto no_codec; - - /* Read in codec location (BAR + 0xe)[2..0]. */ - reg32 = read32(base + 0xe); - reg32 &= 0x0f; - if (!reg32) - goto no_codec; - - return reg32; - -no_codec: - /* Codec not found. */ - /* Put HDA back in reset (BAR + 0x8)[0]. */ - set_bits(base + 0x08, 1, 0); - printk(BIOS_DEBUG, "Azalia: No codec!\n"); - return 0; -} - - -static u32 find_verb(struct device *dev, u32 viddid, const u32 **verb) -{ - int idx = 0; - - while (idx < (cim_verb_data_size / sizeof(u32))) { - u32 verb_size = 4 * cim_verb_data[idx + 2]; /* in u32 */ - if (cim_verb_data[idx] != viddid) { - idx += verb_size + 3; /* Skip verb + header. */ - continue; - } - *verb = &cim_verb_data[idx + 3]; - return verb_size; - } - - /* Not all codecs need to load another verb. */ - return 0; -} - -/** - * Wait 50usec for the codec to indicate it is ready. - * No response would imply that the codec is non-operative. - */ -static int wait_for_ready(u8 *base) -{ - /* Use a 50 usec timeout - the Linux kernel uses the same duration. */ - int timeout = 50; - - while (timeout--) { - u32 reg32 = read32(base + HDA_ICII_REG); - if (!(reg32 & HDA_ICII_BUSY)) - return 0; - udelay(1); - } - - return -1; -} - -/** - * Wait 50usec for the codec to indicate that it accepted the previous command. - * No response would imply that the code is non-operative. - */ -static int wait_for_valid(u8 *base) -{ - u32 reg32; - - /* Send the verb to the codec. */ - reg32 = read32(base + 0x68); - reg32 |= (1 << 0) | (1 << 1); - write32(base + 0x68, reg32); - - /* Use a 50 usec timeout - the Linux kernel uses the same duration. */ - int timeout = 50; - while (timeout--) { - reg32 = read32(base + HDA_ICII_REG); - if ((reg32 & (HDA_ICII_VALID | HDA_ICII_BUSY)) == - HDA_ICII_VALID) - return 0; - udelay(1); - } - - return -1; -} - -static void codec_init(struct device *dev, u8 *base, int addr) -{ - u32 reg32, verb_size; - const u32 *verb; - int i; - - printk(BIOS_DEBUG, "Azalia: Initializing codec #%d\n", addr); - - /* 1 */ - if (wait_for_ready(base) == -1) - return; - - reg32 = (addr << 28) | 0x000f0000; - write32(base + 0x60, reg32); - - if (wait_for_valid(base) == -1) - return; - - reg32 = read32(base + 0x64); - - /* 2 */ - printk(BIOS_DEBUG, "Azalia: codec viddid: %08x\n", reg32); - verb_size = find_verb(dev, reg32, &verb); - - if (!verb_size) { - printk(BIOS_DEBUG, "Azalia: No verb!\n"); - return; - } - printk(BIOS_DEBUG, "Azalia: verb_size: %d\n", verb_size); - - /* 3 */ - for (i = 0; i < verb_size; i++) { - if (wait_for_ready(base) == -1) - return; - - write32(base + 0x60, verb[i]); - - if (wait_for_valid(base) == -1) - return; - } - printk(BIOS_DEBUG, "Azalia: verb loaded.\n"); -} - -static void codecs_init(struct device *dev, u8 *base, u32 codec_mask) -{ - int i; - for (i = 2; i >= 0; i--) { - if (codec_mask & (1 << i)) - codec_init(dev, base, i); - } -} -#endif - -static void azalia_init(struct device *dev) -{ -#if CONFIG(MCP55_USE_AZA) - u8 *base; - u32 codec_mask, reg32; - struct resource *res; - u8 reg8; - - /* Set bus master. */ - reg32 = pci_read_config32(dev, PCI_COMMAND); - pci_write_config32(dev, PCI_COMMAND, reg32 | PCI_COMMAND_MASTER); - - pci_write_config8(dev, 0x3c, 0x0a); // TODO: Unused? - - reg8 = pci_read_config8(dev, 0x40); - reg8 |= (1 << 3); /* Clear Clock Detect bit. */ - pci_write_config8(dev, 0x40, reg8); - reg8 &= ~(1 << 3); /* Keep CLKDETCLR from clearing the bit over and over. */ - pci_write_config8(dev, 0x40, reg8); - reg8 |= (1 << 2); /* Enable clock detection. */ - pci_write_config8(dev, 0x40, reg8); - mdelay(1); - reg8 = pci_read_config8(dev, 0x40); - printk(BIOS_DEBUG, "Azalia: codec type: %s\n", - (reg8 & (1 << 1)) ? "Azalia" : "AC97"); - - reg8 = pci_read_config8(dev, 0x40); /* Audio control */ - reg8 |= 1; /* Select Azalia mode. TODO: Control via devicetree.cb. */ - pci_write_config8(dev, 0x40, reg8); - - reg8 = pci_read_config8(dev, 0x4d); /* Docking status. */ - reg8 &= ~(1 << 7); /* Docking not supported. */ - pci_write_config8(dev, 0x4d, reg8); - - res = find_resource(dev, 0x10); - if (!res) - return; - - /* - * NOTE: This will break as soon as the Azalia gets a BAR above - * 4G. Is there anything we can do about it? - */ - base = res2mmio(res, 0, 0); - printk(BIOS_DEBUG, "Azalia: base = %p\n", base); - codec_mask = codec_detect(base); - - if (codec_mask) { - printk(BIOS_DEBUG, "Azalia: codec_mask = %02x\n", codec_mask); - codecs_init(dev, base, codec_mask); - } -#endif -} - -static struct pci_operations azalia_pci_ops = { - .set_subsystem = pci_dev_set_subsystem, -}; - -static struct device_operations azalia_ops = { - .read_resources = pci_dev_read_resources, - .set_resources = pci_dev_set_resources, - .enable_resources = pci_dev_enable_resources, - .init = azalia_init, - .scan_bus = 0, -// .enable = mcp55_enable, - .ops_pci = &azalia_pci_ops, -}; - -static const struct pci_driver azalia __pci_driver = { - .ops = &azalia_ops, - .vendor = PCI_VENDOR_ID_NVIDIA, - .device = PCI_DEVICE_ID_NVIDIA_MCP55_AZA, -}; diff --git a/src/southbridge/nvidia/mcp55/bootblock.c b/src/southbridge/nvidia/mcp55/bootblock.c deleted file mode 100644 index a3593d3001..0000000000 --- a/src/southbridge/nvidia/mcp55/bootblock.c +++ /dev/null @@ -1,49 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2004 Tyan Computer - * Written by Yinghai Lu for Tyan Computer. - * Copyright (C) 2006,2007 AMD - * Written by Yinghai Lu for AMD. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include "mcp55.h" - -static void mcp55_enable_rom(void) -{ - u8 byte; - u16 word; - pci_devfn_t addr; - - /* Enable 4MB ROM access at 0xFFC00000 - 0xFFFFFFFF. */ - - addr = PCI_DEV(0, (MCP55_DEVN_BASE + 1), 0); - - /* Set the 15MB enable bits. */ - byte = pci_read_config8(addr, 0x88); - byte |= 0xff; /* 256K */ - pci_write_config8(addr, 0x88, byte); - byte = pci_read_config8(addr, 0x8c); - byte |= 0xff; /* 1M */ - pci_write_config8(addr, 0x8c, byte); - word = pci_read_config16(addr, 0x90); - word |= 0x7fff; /* 15M */ - pci_write_config16(addr, 0x90, word); -} - -static void bootblock_southbridge_init(void) -{ - mcp55_enable_rom(); -} diff --git a/src/southbridge/nvidia/mcp55/chip.h b/src/southbridge/nvidia/mcp55/chip.h deleted file mode 100644 index 4bc8428a1a..0000000000 --- a/src/southbridge/nvidia/mcp55/chip.h +++ /dev/null @@ -1,31 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007 AMD - * Written by Yinghai Lu for AMD. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef SOUTHBRIDGE_NVIDIA_MCP55_CHIP_H -#define SOUTHBRIDGE_NVIDIA_MCP55_CHIP_H - -struct southbridge_nvidia_mcp55_config -{ - unsigned int ide0_enable : 1; - unsigned int ide1_enable : 1; - unsigned int sata0_enable : 1; - unsigned int sata1_enable : 1; - unsigned int mac_eeprom_smbus; - unsigned int mac_eeprom_addr; -}; - -#endif diff --git a/src/southbridge/nvidia/mcp55/early_ctrl.c b/src/southbridge/nvidia/mcp55/early_ctrl.c deleted file mode 100644 index 042dfa0b0f..0000000000 --- a/src/southbridge/nvidia/mcp55/early_ctrl.c +++ /dev/null @@ -1,45 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007 AMD - * Written by Yinghai Lu for AMD. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include -#include -#include "mcp55.h" - -void do_soft_reset(void) -{ - set_bios_reset(); - /* link reset */ - outb(0x02, 0x0cf9); - outb(0x06, 0x0cf9); -} - -void do_board_reset(void) -{ - set_bios_reset(); - - /* full reset */ - outb(0x0a, 0x0cf9); - outb(0x0e, 0x0cf9); -} - -void enable_fid_change_on_sb(unsigned int sbbusn, unsigned int sbdn) -{ - /* The default value for MCP55 is good. */ - /* Set VFSMAF (VID/FID System Management Action Field) to 2. */ -} diff --git a/src/southbridge/nvidia/mcp55/early_setup_car.c b/src/southbridge/nvidia/mcp55/early_setup_car.c deleted file mode 100644 index 85198ad7c3..0000000000 --- a/src/southbridge/nvidia/mcp55/early_setup_car.c +++ /dev/null @@ -1,402 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2006 AMD - * Written by Yinghai Lu for AMD. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include -#include - -#ifdef UNUSED_CODE -int set_ht_link_buffer_counts_chain(u8 ht_c_num, unsigned int vendorid, unsigned int val); - -static int set_ht_link_mcp55(u8 ht_c_num) -{ - unsigned int vendorid = 0x10de; - unsigned int val = 0x01610109; - /* NVIDIA MCP55 hardcode, hardware can not set it automatically. */ - return set_ht_link_buffer_counts_chain(ht_c_num, vendorid, val); -} - -static void setup_ss_table(unsigned int index, unsigned int where, unsigned int control, - const unsigned int *register_values, int max) -{ - int i; - unsigned int val; - - val = inl(control); - val &= 0xfffffffe; - outl(val, control); - - outl(0, index); /* Index */ - for (i = 0; i < max; i++) { - unsigned long reg; - reg = register_values[i]; - outl(reg, where); - } - - val = inl(control); - val |= 1; - outl(val, control); -} -#endif - -/* SIZE 0x100 */ -#define ANACTRL_IO_BASE 0x2800 -#define ANACTRL_REG_POS 0x68 - -/* SIZE 0x100 */ -#define SYSCTRL_IO_BASE 0x2400 -#define SYSCTRL_REG_POS 0x64 - -/* SIZE 0x100 */ -#define ACPICTRL_IO_BASE 0x2000 -#define ACPICTRL_REG_POS 0x60 - -/* - * 16 1 1 1 1 8 :0 - * 16 0 4 0 0 8 :1 - * 16 0 4 2 2 4 :2 - * 4 4 4 4 4 8 :3 - * 8 8 4 0 0 8 :4 - * 8 0 4 4 4 8 :5 -*/ - -#define MCP55_CHIP_REV 3 - -/* There will be implicit offsets applied, the writes below do not - * really happen at the PCI_ADDR() this expands to. - */ -#define MCP55_DEV(d, f, r) PCI_ADDR(0, d, f, r) - -static void mcp55_early_set_port(unsigned int mcp55_num, unsigned int *busn, - unsigned int *devn, unsigned int *io_base) -{ - - static const unsigned int ctrl_devport_conf[] = { - MCP55_DEV(1, 1, ANACTRL_REG_POS), ~(0x0000ff00), ANACTRL_IO_BASE, - MCP55_DEV(1, 1, SYSCTRL_REG_POS), ~(0x0000ff00), SYSCTRL_IO_BASE, - MCP55_DEV(1, 1, ACPICTRL_REG_POS), ~(0x0000ff00), ACPICTRL_IO_BASE, - }; - - int j; - for (j = 0; j < mcp55_num; j++) { - setup_resource_map_offset(ctrl_devport_conf, - ARRAY_SIZE(ctrl_devport_conf), - PCI_DEV(busn[j], devn[j], 0), io_base[j]); - } -} - -static void mcp55_early_clear_port(unsigned int mcp55_num, unsigned int *busn, - unsigned int *devn, unsigned int *io_base) -{ - static const unsigned int ctrl_devport_conf_clear[] = { - MCP55_DEV(1, 1, ANACTRL_REG_POS), ~(0x0000ff00), 0, - MCP55_DEV(1, 1, SYSCTRL_REG_POS), ~(0x0000ff00), 0, - MCP55_DEV(1, 1, ACPICTRL_REG_POS), ~(0x0000ff00), 0, - }; - - int j; - for (j = 0; j < mcp55_num; j++) { - setup_resource_map_offset(ctrl_devport_conf_clear, - ARRAY_SIZE(ctrl_devport_conf_clear), - PCI_DEV(busn[j], devn[j], 0), io_base[j]); - } -} - -static void mcp55_early_pcie_setup(unsigned int busnx, unsigned int devnx, - unsigned int anactrl_io_base, unsigned int pci_e_x) -{ - u32 tgio_ctrl, pll_ctrl, dword; - int i; - pci_devfn_t dev; - - dev = PCI_DEV(busnx, devnx + 1, 1); - - dword = pci_read_config32(dev, 0xe4); - dword |= 0x3f0; /* Disable it at first. */ - pci_write_config32(dev, 0xe4, dword); - - for (i = 0; i < 3; i++) { - tgio_ctrl = inl(anactrl_io_base + 0xcc); - tgio_ctrl &= ~(3 << 9); - tgio_ctrl |= (i << 9); - outl(tgio_ctrl, anactrl_io_base + 0xcc); - pll_ctrl = inl(anactrl_io_base + 0x30); - pll_ctrl |= (1 << 31); - outl(pll_ctrl, anactrl_io_base + 0x30); - do { - pll_ctrl = inl(anactrl_io_base + 0x30); - } while (!(pll_ctrl & 1)); - } - tgio_ctrl = inl(anactrl_io_base + 0xcc); - tgio_ctrl &= ~((7 << 4) | (1 << 8)); - tgio_ctrl |= (pci_e_x << 4) | (1 << 8); - outl(tgio_ctrl, anactrl_io_base + 0xcc); - - udelay(100); /* Wait 100us. */ - - dword = pci_read_config32(dev, 0xe4); - dword &= ~(0x3f0); /* Enable. */ - pci_write_config32(dev, 0xe4, dword); - - mdelay(100); /* Need to wait 100ms. */ -} - -static void mcp55_early_setup(unsigned int mcp55_num, unsigned int *busn, - unsigned int *devn, unsigned int *io_base, - unsigned int *pci_e_x) -{ - static const unsigned int ctrl_conf_1[] = { - RES_PORT_IO_32, ACPICTRL_IO_BASE + 0x10, 0x0007ffff, 0xff78000, - RES_PORT_IO_32, ACPICTRL_IO_BASE + 0xa4, 0xffedffff, 0x0012000, - RES_PORT_IO_32, ACPICTRL_IO_BASE + 0xac, 0xfffffdff, 0x0000200, - RES_PORT_IO_32, ACPICTRL_IO_BASE + 0xb4, 0xfffffffd, 0x0000002, - - RES_PORT_IO_32, ANACTRL_IO_BASE + 0x24, 0xc0f0f08f, 0x26020230, - RES_PORT_IO_32, ANACTRL_IO_BASE + 0x34, 0x00000000, 0x22222222, - RES_PORT_IO_32, ANACTRL_IO_BASE + 0x08, 0x7FFFFFFF, 0x00000000, - RES_PORT_IO_32, ANACTRL_IO_BASE + 0x2C, 0x7FFFFFFF, 0x80000000, - RES_PORT_IO_32, ANACTRL_IO_BASE + 0xCC, 0xFFFFF9FF, 0x00000000, - RES_PORT_IO_32, ANACTRL_IO_BASE + 0x30, 0x8FFFFFFF, 0x40000000, - RES_PORT_IO_32, ANACTRL_IO_BASE + 0xCC, 0xFFFFF9FF, 0x00000200, - RES_PORT_IO_32, ANACTRL_IO_BASE + 0x30, 0x8FFFFFFF, 0x40000000, - RES_PORT_IO_32, ANACTRL_IO_BASE + 0xCC, 0xFFFFF9FF, 0x00000400, - RES_PORT_IO_32, ANACTRL_IO_BASE + 0x30, 0x8FFFFFFF, 0x40000000, - RES_PORT_IO_32, ANACTRL_IO_BASE + 0x74, 0xFFFF0FF5, 0x0000F000, - RES_PORT_IO_32, ANACTRL_IO_BASE + 0x78, 0xFF00FF00, 0x00100010, - RES_PORT_IO_32, ANACTRL_IO_BASE + 0x7C, 0xFF0FF0FF, 0x00500500, - RES_PORT_IO_32, ANACTRL_IO_BASE + 0x80, 0xFFFFFFE7, 0x00000000, - RES_PORT_IO_32, ANACTRL_IO_BASE + 0x60, 0xFFCFFFFF, 0x00300000, - RES_PORT_IO_32, ANACTRL_IO_BASE + 0x90, 0xFFFF00FF, 0x0000FF00, - RES_PORT_IO_32, ANACTRL_IO_BASE + 0x9C, 0xFF00FFFF, 0x00070000, - - RES_PCI_IO, MCP55_DEV(0, 0, 0x40), 0x00000000, 0xCB8410DE, - RES_PCI_IO, MCP55_DEV(0, 0, 0x48), 0xFFFFDCED, 0x00002002, - RES_PCI_IO, MCP55_DEV(0, 0, 0x78), 0xFFFFFF8E, 0x00000011, - RES_PCI_IO, MCP55_DEV(0, 0, 0x80), 0xFFFF0000, 0x00009923, - RES_PCI_IO, MCP55_DEV(0, 0, 0x88), 0xFFFFFFFE, 0x00000000, - RES_PCI_IO, MCP55_DEV(0, 0, 0x8C), 0xFFFF0000, 0x0000007F, - RES_PCI_IO, MCP55_DEV(0, 0, 0xDC), 0xFFFEFFFF, 0x00010000, - - RES_PCI_IO, MCP55_DEV(1, 0, 0x40), 0x00000000, 0xCB8410DE, - RES_PCI_IO, MCP55_DEV(1, 0, 0x74), 0xFFFFFF7B, 0x00000084, - RES_PCI_IO, MCP55_DEV(1, 0, 0xF8), 0xFFFFFFCF, 0x00000010, - - RES_PCI_IO, MCP55_DEV(1, 1, 0xC4), 0xFFFFFFFE, 0x00000001, - RES_PCI_IO, MCP55_DEV(1, 1, 0xF0), 0x7FFFFFFD, 0x00000002, - RES_PCI_IO, MCP55_DEV(1, 1, 0xF8), 0xFFFFFFCF, 0x00000010, - - RES_PCI_IO, MCP55_DEV(8, 0, 0x40), 0x00000000, 0xCB8410DE, - RES_PCI_IO, MCP55_DEV(8, 0, 0x68), 0xFFFFFF00, 0x000000FF, - RES_PCI_IO, MCP55_DEV(8, 0, 0xF8), 0xFFFFFFBF, 0x00000040, /* Enable bridge mode. */ - - RES_PCI_IO, MCP55_DEV(9, 0, 0x40), 0x00000000, 0xCB8410DE, - RES_PCI_IO, MCP55_DEV(9, 0, 0x68), 0xFFFFFF00, 0x000000FF, - RES_PCI_IO, MCP55_DEV(9, 0, 0xF8), 0xFFFFFFBF, 0x00000040, /* Enable bridge mode. */ - }; - - static const unsigned int ctrl_conf_1_1[] = { - RES_PCI_IO, MCP55_DEV(5, 0, 0x40), 0x00000000, 0xCB8410DE, - RES_PCI_IO, MCP55_DEV(5, 0, 0x50), 0xFFFFFFFC, 0x00000003, - RES_PCI_IO, MCP55_DEV(5, 0, 0x64), 0xFFFFFFFE, 0x00000001, - RES_PCI_IO, MCP55_DEV(5, 0, 0x70), 0xFFF0FFFF, 0x00040000, - RES_PCI_IO, MCP55_DEV(5, 0, 0xAC), 0xFFFFF0FF, 0x00000100, - RES_PCI_IO, MCP55_DEV(5, 0, 0x7C), 0xFFFFFFEF, 0x00000000, - RES_PCI_IO, MCP55_DEV(5, 0, 0xC8), 0xFF00FF00, 0x000A000A, - RES_PCI_IO, MCP55_DEV(5, 0, 0xD0), 0xF0FFFFFF, 0x03000000, - RES_PCI_IO, MCP55_DEV(5, 0, 0xE0), 0xF0FFFFFF, 0x03000000, - }; - - static const unsigned int ctrl_conf_mcp55_only[] = { - RES_PCI_IO, MCP55_DEV(1, 1, 0x40), 0x00000000, 0xCB8410DE, - RES_PCI_IO, MCP55_DEV(1, 1, 0xE0), 0xFFFFFEFF, 0x00000000, - RES_PCI_IO, MCP55_DEV(1, 1, 0xE4), 0xFFFFFFFB, 0x00000000, - RES_PCI_IO, MCP55_DEV(1, 1, 0xE8), 0xFFA9C8FF, 0x00003000, - - RES_PCI_IO, MCP55_DEV(4, 0, 0x40), 0x00000000, 0xCB8410DE, - RES_PCI_IO, MCP55_DEV(4, 0, 0xF8), 0xFFFFFFCF, 0x00000010, - - RES_PCI_IO, MCP55_DEV(2, 0, 0x40), 0x00000000, 0xCB8410DE, - - RES_PCI_IO, MCP55_DEV(2, 1, 0x40), 0x00000000, 0xCB8410DE, - RES_PCI_IO, MCP55_DEV(2, 1, 0x64), 0xF87FFFFF, 0x05000000, - RES_PCI_IO, MCP55_DEV(2, 1, 0x78), 0xFFC07FFF, 0x00360000, - RES_PCI_IO, MCP55_DEV(2, 1, 0x68), 0xFE00D03F, 0x013F2C00, - RES_PCI_IO, MCP55_DEV(2, 1, 0x70), 0xFFF7FFFF, 0x00080000, - RES_PCI_IO, MCP55_DEV(2, 1, 0x7C), 0xFFFFF00F, 0x00000570, - RES_PCI_IO, MCP55_DEV(2, 1, 0xF8), 0xFFFFFFCF, 0x00000010, - - RES_PCI_IO, MCP55_DEV(6, 0, 0x04), 0xFFFFFEFB, 0x00000104, - RES_PCI_IO, MCP55_DEV(6, 0, 0x3C), 0xF5FFFFFF, 0x0A000000, - RES_PCI_IO, MCP55_DEV(6, 0, 0x40), 0x00C8FFFF, 0x07330000, - RES_PCI_IO, MCP55_DEV(6, 0, 0x48), 0xFFFFFFF8, 0x00000005, - RES_PCI_IO, MCP55_DEV(6, 0, 0x4C), 0xFE02FFFF, 0x004C0000, - RES_PCI_IO, MCP55_DEV(6, 0, 0x74), 0xFFFFFFC0, 0x00000000, - RES_PCI_IO, MCP55_DEV(6, 0, 0xC0), 0x00000000, 0xCB8410DE, - RES_PCI_IO, MCP55_DEV(6, 0, 0xC4), 0xFFFFFFF8, 0x00000007, -#if CONFIG(NORTHBRIDGE_AMD_AMDFAM10) - /* - * Avoid crash (complete with severe memory corruption!) during initial CAR boot - * in mcp55_early_setup_x() on Fam10h systems by not touching 0x78. - * Interestingly once the system is fully booted into Linux this can be set, but - * not before! Apparently something isn't initialized but the amount of effort - * required to fix this is non-negligible and of unknown real-world benefit - */ -#else - RES_PCI_IO, MCP55_DEV(1, 0, 0x78), 0xC0FFFFFF, 0x19000000, -#endif - -#if CONFIG(MCP55_USE_AZA) - RES_PCI_IO, MCP55_DEV(6, 1, 0x40), 0x00000000, 0xCB8410DE, - -#endif - -#ifdef MCP55_MB_SETUP - /* Play a while with GPIO in MCP55. */ - MCP55_MB_SETUP -#endif - -#if CONFIG(MCP55_USE_AZA) - RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+ 21, ~(3 << 2), (2 << 2), - RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+ 22, ~(3 << 2), (2 << 2), - RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+ 46, ~(3 << 2), (2 << 2), -#endif - }; - - static const unsigned int ctrl_conf_master_only[] = { - RES_PORT_IO_32, ACPICTRL_IO_BASE + 0x80, 0xEFFFFFF, 0x01000000, - - /* Master MCP55???? YHLU */ - RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+ 0, ~(3 << 2), (0 << 2), - }; - - static const unsigned int ctrl_conf_2[] = { - /* I didn't put PCI-E related stuff here. */ - - RES_PCI_IO, MCP55_DEV(0, 0, 0x74), 0xFFFFF00F, 0x000009D0, - RES_PCI_IO, MCP55_DEV(1, 0, 0x74), 0xFFFF7FFF, 0x00008000, - - RES_PORT_IO_32, SYSCTRL_IO_BASE + 0x48, 0xFFFEFFFF, 0x00010000, - - RES_PORT_IO_32, ANACTRL_IO_BASE + 0x60, 0xFFFFFF00, 0x00000012, - -#if CONFIG(MCP55_USE_NIC) - RES_PCI_IO, MCP55_DEV(1, 1, 0xe4), ~((1 << 22) | (1 << 20)), (1 << 22) | (1 << 20), - - RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+ 4, ~(0xff), ((0 << 4) | (1 << 2) | (0 << 0)), - RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+ 4, ~(0xff), ((0 << 4) | (1 << 2) | (1 << 0)), -#endif - }; - - int j, i; - - for (j = 0; j < mcp55_num; j++) { - mcp55_early_pcie_setup(busn[j], devn[j], - io_base[j] + ANACTRL_IO_BASE, pci_e_x[j]); - - setup_resource_map_x_offset(ctrl_conf_1, - ARRAY_SIZE(ctrl_conf_1), - PCI_DEV(busn[j], devn[j], 0), io_base[j]); - - for (i = 0; i < 3; i++) { /* Three SATA */ - setup_resource_map_x_offset(ctrl_conf_1_1, - ARRAY_SIZE(ctrl_conf_1_1), - PCI_DEV(busn[j], devn[j], i), io_base[j]); - } - - if (busn[j] == 0) { - setup_resource_map_x_offset(ctrl_conf_mcp55_only, - ARRAY_SIZE(ctrl_conf_mcp55_only), - PCI_DEV(busn[j], devn[j], 0), io_base[j]); - } - - if ((busn[j] == 0) && (mcp55_num>1)) { - setup_resource_map_x_offset(ctrl_conf_master_only, - ARRAY_SIZE(ctrl_conf_master_only), - PCI_DEV(busn[j], devn[j], 0), io_base[j]); - } - - setup_resource_map_x_offset(ctrl_conf_2, - ARRAY_SIZE(ctrl_conf_2), - PCI_DEV(busn[j], devn[j], 0), io_base[j]); - } - -} - -#ifndef HT_CHAIN_NUM_MAX - -#define HT_CHAIN_NUM_MAX 4 -#define HT_CHAIN_BUSN_D 0x40 -#define HT_CHAIN_IOBASE_D 0x4000 - -#endif - -static int mcp55_early_setup_x(void) -{ - /* Find out how many MCP55 we have. */ - unsigned int busn[HT_CHAIN_NUM_MAX] = {0}; - unsigned int devn[HT_CHAIN_NUM_MAX] = {0}; - unsigned int io_base[HT_CHAIN_NUM_MAX] = {0}; - - /* - * FIXME: May have problem if there is different MCP55 HTX card with - * different PCI_E lane allocation. Need to use same trick about - * pci1234 to verify node/link connection. - */ - unsigned int pci_e_x[HT_CHAIN_NUM_MAX] = { - CONFIG_MCP55_PCI_E_X_0, CONFIG_MCP55_PCI_E_X_1, - CONFIG_MCP55_PCI_E_X_2, CONFIG_MCP55_PCI_E_X_3, - }; - int mcp55_num = 0, ht_c_index; - unsigned int busnx, devnx; - - /* FIXME: Multi PCI segment handling. */ - - /* Any system that only have IO55 without MCP55? */ - for (ht_c_index = 0; ht_c_index < HT_CHAIN_NUM_MAX; ht_c_index++) { - busnx = ht_c_index * HT_CHAIN_BUSN_D; - for (devnx = 0; devnx < 0x20; devnx++) { - u32 id; - pci_devfn_t dev; - dev = PCI_DEV(busnx, devnx, 0); - id = pci_read_config32(dev, PCI_VENDOR_ID); - if (id == 0x036910de) { - busn[mcp55_num] = busnx; - devn[mcp55_num] = devnx; - - /* We may have HT chain other than MCP55. */ - io_base[mcp55_num] - = ht_c_index * HT_CHAIN_IOBASE_D; - - mcp55_num++; - if (mcp55_num == CONFIG_MCP55_NUM) - goto out; - break; /* Only one MCP55 on one chain. */ - } - } - } - -out: - printk(BIOS_DEBUG, "mcp55_num: %02x\n", mcp55_num); - - mcp55_early_set_port(mcp55_num, busn, devn, io_base); - mcp55_early_setup(mcp55_num, busn, devn, io_base, pci_e_x); - - mcp55_early_clear_port(mcp55_num, busn, devn, io_base); - - return 0; -} diff --git a/src/southbridge/nvidia/mcp55/early_setup_ss.h b/src/southbridge/nvidia/mcp55/early_setup_ss.h deleted file mode 100644 index a5ddb3be24..0000000000 --- a/src/southbridge/nvidia/mcp55/early_setup_ss.h +++ /dev/null @@ -1,217 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2004 Tyan Computer - * Written by Yinghai Lu for Tyan Computer. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -static const unsigned int pcie_ss_tbl[] = { - 0x0C504103f, - 0x0C504103f, - 0x0C504103f, - 0x0C5042040, - 0x0C5042040, - 0x0C5042040, - 0x0C5043041, - 0x0C5043041, - 0x0C5043041, - 0x0C5043041, - 0x0C5044042, - 0x0C5044042, - 0x0C5044042, - 0x0C5045043, - 0x0C5045043, - 0x0C5045043, - 0x0C5045043, - 0x0C5045043, - 0x0C5046044, - 0x0C5046044, - 0x0C5046044, - 0x0C5046044, - 0x0C5047045, - 0x0C5047045, - 0x0C5047045, - 0x0C5047045, - 0x0C5047045, - 0x0C5048046, - 0x0C5048046, - 0x0C5048046, - 0x0C5048046, - 0x0C5049047, - 0x0C5049047, - 0x0C5049047, - 0x0C504a048, - 0x0C504a048, - 0x0C504b049, - 0x0C504b049, - 0x0C504a048, - 0x0C504a048, - 0x0C5049047, - 0x0C5049047, - 0x0C5048046, - 0x0C5048046, - 0x0C5048046, - 0x0C5047045, - 0x0C5047045, - 0x0C5047045, - 0x0C5047045, - 0x0C5047045, - 0x0C5046044, - 0x0C5046044, - 0x0C5046044, - 0x0C5046044, - 0x0C5045043, - 0x0C5045043, - 0x0C5045043, - 0x0C5044042, - 0x0C5044042, - 0x0C5044042, - 0x0C5043041, - 0x0C5043041, - 0x0C5042040, - 0x0C5042040, -}; - -static const unsigned int sata_ss_tbl[] = { - 0x0c9044042, - 0x0c9044042, - 0x0c9044042, - 0x0c9045043, - 0x0c9045043, - 0x0c9045043, - 0x0c9045043, - 0x0c9045043, - 0x0c9046044, - 0x0c9046044, - 0x0c9046044, - 0x0c9046044, - 0x0c9047045, - 0x0c9047045, - 0x0c9047045, - 0x0c9047045, - 0x0c9047045, - 0x0c9048046, - 0x0c9048046, - 0x0c9048046, - 0x0c9048046, - 0x0c9049047, - 0x0c9049047, - 0x0c9049047, - 0x0c9049047, - 0x0c904a048, - 0x0c904a048, - 0x0c904a048, - 0x0c904a048, - 0x0c904b049, - 0x0c904b049, - 0x0c904b049, - 0x0c904b049, - 0x0c904b049, - 0x0c904b049, - 0x0c904a048, - 0x0c904a048, - 0x0c904a048, - 0x0c904a048, - 0x0c9049047, - 0x0c9049047, - 0x0c9049047, - 0x0c9049047, - 0x0c9048046, - 0x0c9048046, - 0x0c9048046, - 0x0c9048046, - 0x0c9047045, - 0x0c9047045, - 0x0c9047045, - 0x0c9047045, - 0x0c9047045, - 0x0c9046044, - 0x0c9046044, - 0x0c9046044, - 0x0c9046044, - 0x0c9045043, - 0x0c9045043, - 0x0c9045043, - 0x0c9045043, - 0x0c9045043, - 0x0c9044042, - 0x0c9044042, - 0x0c9044042, -}; - -static const unsigned int cpu_ss_tbl[] = { - 0x0C5038036, - 0x0C5038036, - 0x0C5038036, - 0x0C5037035, - 0x0C5037035, - 0x0C5037035, - 0x0C5037035, - 0x0C5036034, - 0x0C5036034, - 0x0C5036034, - 0x0C5036034, - 0x0C5036034, - 0x0C5035033, - 0x0C5035033, - 0x0C5035033, - 0x0C5035033, - 0x0C5035033, - 0x0C5035033, - 0x0C5034032, - 0x0C5034032, - 0x0C5034032, - 0x0C5034032, - 0x0C5034032, - 0x0C5034032, - 0x0C5035033, - 0x0C5035033, - 0x0C5035033, - 0x0C5035033, - 0x0C5035033, - 0x0C5036034, - 0x0C5036034, - 0x0C5036034, - 0x0C5036034, - 0x0C5036034, - 0x0C5037035, - 0x0C5037035, - 0x0C5037035, - 0x0C5037035, - 0x0C5038036, - 0x0C5038036, - 0x0C5038036, - 0x0C5038036, - 0x0C5039037, - 0x0C5039037, - 0x0C5039037, - 0x0C5039037, - 0x0C503a038, - 0x0C503a038, - 0x0C503a038, - 0x0C503a038, - 0x0C503b039, - 0x0C503b039, - 0x0C503b039, - 0x0C503b039, - 0x0C503b039, - 0x0C503a038, - 0x0C503a038, - 0x0C503a038, - 0x0C503a038, - 0x0C503a038, - 0x0C5039037, - 0x0C5039037, - 0x0C5039037, - 0x0C5039037, -}; diff --git a/src/southbridge/nvidia/mcp55/early_smbus.c b/src/southbridge/nvidia/mcp55/early_smbus.c deleted file mode 100644 index 1b49456a18..0000000000 --- a/src/southbridge/nvidia/mcp55/early_smbus.c +++ /dev/null @@ -1,96 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2004 Tyan Computer - * Written by Yinghai Lu for Tyan Computer. - * Copyright (C) 2006,2007 AMD - * Written by Yinghai Lu for AMD. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include -#include -#include "smbus.h" -#include "mcp55.h" - -#define SMBUS0_IO_BASE 0x1000 -#define SMBUS1_IO_BASE (0x1000 + (1 << 8)) -/* Size: 0x40 */ - -void enable_smbus(void) -{ - pci_devfn_t dev; - dev = pci_locate_device(PCI_ID(0x10de, 0x0368), 0); - - if (dev == PCI_DEV_INVALID) - die("SMBus controller not found\n"); - - /* Set SMBus I/O base. */ - pci_write_config32(dev, 0x20, SMBUS0_IO_BASE | 1); - pci_write_config32(dev, 0x24, SMBUS1_IO_BASE | 1); - - /* Set SMBus I/O space enable. */ - pci_write_config16(dev, 0x4, 0x01); - - /* Clear any lingering errors, so the transaction will run. */ - outb(inb(SMBUS0_IO_BASE + SMBHSTSTAT), SMBUS0_IO_BASE + SMBHSTSTAT); - outb(inb(SMBUS1_IO_BASE + SMBHSTSTAT), SMBUS1_IO_BASE + SMBHSTSTAT); -} - -int smbus_recv_byte(unsigned int device) -{ - return do_smbus_recv_byte(SMBUS0_IO_BASE, device); -} - -int smbus_send_byte(unsigned int device, unsigned char val) -{ - return do_smbus_send_byte(SMBUS0_IO_BASE, device, val); -} - -int smbus_read_byte(unsigned int device, unsigned int address) -{ - return do_smbus_read_byte(SMBUS0_IO_BASE, device, address); -} - -int smbus_write_byte(unsigned int device, unsigned int address, - unsigned char val) -{ - return do_smbus_write_byte(SMBUS0_IO_BASE, device, address, val); -} - -int smbusx_recv_byte(unsigned int smb_index, unsigned int device) -{ - return do_smbus_recv_byte(SMBUS0_IO_BASE + (smb_index << 8), device); -} - -int smbusx_send_byte(unsigned int smb_index, unsigned int device, - unsigned char val) -{ - return do_smbus_send_byte(SMBUS0_IO_BASE + (smb_index << 8), - device, val); -} - -int smbusx_read_byte(unsigned int smb_index, unsigned int device, - unsigned int address) -{ - return do_smbus_read_byte(SMBUS0_IO_BASE + (smb_index << 8), - device, address); -} - -int smbusx_write_byte(unsigned int smb_index, unsigned int device, - unsigned int address, unsigned char val) -{ - return do_smbus_write_byte(SMBUS0_IO_BASE + (smb_index << 8), - device, address, val); -} diff --git a/src/southbridge/nvidia/mcp55/enable_usbdebug.c b/src/southbridge/nvidia/mcp55/enable_usbdebug.c deleted file mode 100644 index badf8f47e2..0000000000 --- a/src/southbridge/nvidia/mcp55/enable_usbdebug.c +++ /dev/null @@ -1,43 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2004 Tyan Computer - * Written by Yinghai Lu for Tyan Computer. - * Copyright (C) 2006,2007 AMD - * Written by Yinghai Lu for AMD. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -// Use simple device model for this file even in ramstage -#define __SIMPLE_DEVICE__ - -#include -#include -#include -#include -#include "mcp55.h" - -pci_devfn_t pci_ehci_dbg_dev(unsigned int hcd_idx) -{ - return PCI_DEV(0, MCP55_DEVN_BASE + 2, 1); /* USB EHCI */ -} - -void pci_ehci_dbg_set_port(pci_devfn_t dev, unsigned int port) -{ - u32 dword; - - /* Write the port number to 0x74[15:12]. */ - dword = pci_read_config32(dev, 0x74); - dword &= ~(0xf << 12); - dword |= (port << 12); - pci_write_config32(dev, 0x74, dword); -} diff --git a/src/southbridge/nvidia/mcp55/fadt.c b/src/southbridge/nvidia/mcp55/fadt.c deleted file mode 100644 index 16f0df85de..0000000000 --- a/src/southbridge/nvidia/mcp55/fadt.c +++ /dev/null @@ -1,169 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2004 Nick Barker - * Copyright (C) 2007 Rudolf Marek - * Copyright (C) 2009 Harald Gutmann - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include -#include -#include -#include - -extern unsigned int pm_base; - -/* Create the Fixed ACPI Description Tables (FADT) for this board. */ -void acpi_create_fadt(acpi_fadt_t *fadt, acpi_facs_t *facs, void *dsdt) -{ - acpi_header_t *header = &(fadt->header); - struct device *dev; - int is_mcp55 = 0; - dev = dev_find_device(PCI_VENDOR_ID_NVIDIA, - PCI_DEVICE_ID_NVIDIA_MCP55_LPC, 0); - if (dev) - is_mcp55 = 1; - - memset((void *) fadt, 0, sizeof(acpi_fadt_t)); - memcpy(header->signature, "FACP", 4); - header->length = sizeof(acpi_fadt_t); - header->revision = ACPI_FADT_REV_ACPI_1_0; - memcpy(header->oem_id, OEM_ID, 6); - memcpy(header->oem_table_id, ACPI_TABLE_CREATOR, 8); - memcpy(header->asl_compiler_id, ASLC, 4); - header->asl_compiler_revision = asl_revision; - - printk(BIOS_INFO, "ACPI: pm_base: %u...\n", pm_base); - - fadt->firmware_ctrl = (u32)facs; - fadt->dsdt = (u32)dsdt; - fadt->preferred_pm_profile = 1; //check - fadt->sci_int = 9; - /* disable system management mode by setting to 0 */ - fadt->smi_cmd = 0x0; //pm_base+0x42e; (value from proprietary acpi fadt) - fadt->acpi_enable = 0xa1; - fadt->acpi_disable = 0xa0; - fadt->s4bios_req = 0x0; - fadt->pstate_cnt = 0x0; - - fadt->pm1a_evt_blk = pm_base; - fadt->pm1b_evt_blk = 0x0; - fadt->pm1a_cnt_blk = pm_base + 0x4; - fadt->pm1b_cnt_blk = 0x0; - fadt->pm2_cnt_blk = pm_base + 0x1c; - fadt->pm_tmr_blk = pm_base + 0x8; - fadt->gpe0_blk = pm_base + 0x20; - - fadt->pm1_evt_len = 4; - fadt->pm1_cnt_len = 2; - fadt->pm2_cnt_len = 1; - fadt->pm_tmr_len = 4; - fadt->gpe0_blk_len = 8; - if (is_mcp55) { - fadt->gpe1_blk = pm_base + 0x4a0; - fadt->gpe1_base = 0x20; - fadt->gpe1_blk_len = 0x10; - } - else { - fadt->gpe1_blk = 0x0; - fadt->gpe1_base = 0x0; - fadt->gpe1_blk_len = 0x0; - } - - fadt->cst_cnt = 0; - fadt->p_lvl2_lat = 0x65; - fadt->p_lvl3_lat = 0x3e9; - fadt->flush_size = 0; - fadt->flush_stride = 0; - fadt->duty_offset = 1; - fadt->duty_width = 3; - fadt->day_alrm = 0x7d; - fadt->mon_alrm = 0x7e; - fadt->century = 0x32; - - fadt->iapc_boot_arch = ACPI_FADT_LEGACY_FREE; - - fadt->flags = 0x4a5; - fadt->reset_reg.space_id = 0; - fadt->reset_reg.bit_width = 0; - fadt->reset_reg.bit_offset = 0; - fadt->reset_reg.access_size = 0; - fadt->reset_reg.addrl = 0x0; - fadt->reset_reg.addrh = 0x0; - - fadt->reset_value = 0; - fadt->x_firmware_ctl_l = (u32)facs; - fadt->x_firmware_ctl_h = 0; - fadt->x_dsdt_l = (u32)dsdt; - fadt->x_dsdt_h = 0; - - fadt->x_pm1a_evt_blk.space_id = 1; - fadt->x_pm1a_evt_blk.bit_width = fadt->pm1_evt_len * 8; - fadt->x_pm1a_evt_blk.bit_offset = 0; - fadt->x_pm1a_evt_blk.access_size = 0; - fadt->x_pm1a_evt_blk.addrl = fadt->pm1a_evt_blk; - fadt->x_pm1a_evt_blk.addrh = 0x0; - - fadt->x_pm1b_evt_blk.space_id = 1; - fadt->x_pm1b_evt_blk.bit_width = fadt->pm1_evt_len * 8; - fadt->x_pm1b_evt_blk.bit_offset = 0; - fadt->x_pm1b_evt_blk.access_size = 0; - fadt->x_pm1b_evt_blk.addrl = fadt->pm1b_evt_blk; - fadt->x_pm1b_evt_blk.addrh = 0x0; - - fadt->x_pm1a_cnt_blk.space_id = 1; - fadt->x_pm1a_cnt_blk.bit_width = fadt->pm1_cnt_len * 8; - fadt->x_pm1a_cnt_blk.bit_offset = 0; - fadt->x_pm1a_cnt_blk.access_size = 0; - fadt->x_pm1a_cnt_blk.addrl = fadt->pm1a_cnt_blk; - fadt->x_pm1a_cnt_blk.addrh = 0x0; - - fadt->x_pm1b_cnt_blk.space_id = 1; - fadt->x_pm1b_cnt_blk.bit_width = fadt->pm1_cnt_len * 8; - fadt->x_pm1b_cnt_blk.bit_offset = 0; - fadt->x_pm1b_cnt_blk.access_size = 0; - fadt->x_pm1b_cnt_blk.addrl = fadt->pm1b_cnt_blk; - fadt->x_pm1b_cnt_blk.addrh = 0x0; - - fadt->x_pm2_cnt_blk.space_id = 1; - fadt->x_pm2_cnt_blk.bit_width = fadt->pm2_cnt_len * 8; - fadt->x_pm2_cnt_blk.bit_offset = 0; - fadt->x_pm2_cnt_blk.access_size = 0; - fadt->x_pm2_cnt_blk.addrl = fadt->pm2_cnt_blk; - fadt->x_pm2_cnt_blk.addrh = 0x0; - - fadt->x_pm_tmr_blk.space_id = 1; - fadt->x_pm_tmr_blk.bit_width = fadt->pm_tmr_len * 8; - fadt->x_pm_tmr_blk.bit_offset = 0; - fadt->x_pm_tmr_blk.access_size = 0; - fadt->x_pm_tmr_blk.addrl = fadt->pm_tmr_blk; - fadt->x_pm_tmr_blk.addrh = 0x0; - - fadt->x_gpe0_blk.space_id = 1; - fadt->x_gpe0_blk.bit_width = fadt->gpe0_blk_len * 8; - fadt->x_gpe0_blk.bit_offset = 0; - fadt->x_gpe0_blk.access_size = 0; - fadt->x_gpe0_blk.addrl = fadt->gpe0_blk; - fadt->x_gpe0_blk.addrh = 0x0; - - fadt->x_gpe1_blk.space_id = 1; - fadt->x_gpe1_blk.bit_width = fadt->gpe1_blk_len * 8; - fadt->x_gpe1_blk.bit_offset = 0; - fadt->x_gpe1_blk.access_size = 0; - fadt->x_gpe1_blk.addrl = fadt->gpe1_blk; - fadt->x_gpe1_blk.addrh = 0x0; - - header->checksum = acpi_checksum((void *) fadt, header->length); -} diff --git a/src/southbridge/nvidia/mcp55/ht.c b/src/southbridge/nvidia/mcp55/ht.c deleted file mode 100644 index 070f8b7125..0000000000 --- a/src/southbridge/nvidia/mcp55/ht.c +++ /dev/null @@ -1,47 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2004 Tyan Computer - * Written by Yinghai Lu for Tyan Computer. - * Copyright (C) 2006,2007 AMD - * Written by Yinghai Lu for AMD. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include -#include -#include "mcp55.h" - -#if CONFIG(HAVE_ACPI_TABLES) -unsigned long acpi_fill_mcfg(unsigned long current) -{ - /* Not implemented */ - return current; -} -#endif - -static struct device_operations ht_ops = { - .read_resources = pci_dev_read_resources, - .set_resources = pci_dev_set_resources, - .enable_resources = pci_dev_enable_resources, - .init = 0, - .scan_bus = 0, - .ops_pci = &mcp55_pci_ops, -}; - -static const struct pci_driver ht_driver __pci_driver = { - .ops = &ht_ops, - .vendor = PCI_VENDOR_ID_NVIDIA, - .device = PCI_DEVICE_ID_NVIDIA_MCP55_HT, -}; diff --git a/src/southbridge/nvidia/mcp55/ide.c b/src/southbridge/nvidia/mcp55/ide.c deleted file mode 100644 index 36e20b4aa0..0000000000 --- a/src/southbridge/nvidia/mcp55/ide.c +++ /dev/null @@ -1,78 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2004 Tyan Computer - * Written by Yinghai Lu for Tyan Computer. - * Copyright (C) 2006,2007 AMD - * Written by Yinghai Lu for AMD. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include -#include -#include - -#include "chip.h" -#include "mcp55.h" - -static void ide_init(struct device *dev) -{ - struct southbridge_nvidia_mcp55_config *conf; - u32 dword; - u16 word; - u8 byte; - conf = dev->chip_info; - - word = pci_read_config16(dev, 0x50); - /* Ensure prefetch is disabled. */ - word &= ~((1 << 15) | (1 << 13)); - if (conf->ide1_enable) { - /* Enable secondary IDE interface. */ - word |= (1 << 0); - printk(BIOS_DEBUG, "IDE1\t"); - } - if (conf->ide0_enable) { - /* Enable primary IDE interface. */ - word |= (1 << 1); - printk(BIOS_DEBUG, "IDE0\n"); - } - - word |= (1 << 12); - word |= (1 << 14); - - pci_write_config16(dev, 0x50, word); - - byte = 0x20; /* Latency: 64-->32 */ - pci_write_config8(dev, 0xd, byte); - - dword = pci_read_config32(dev, 0xf8); - dword |= 12; - pci_write_config32(dev, 0xf8, dword); -} - -static struct device_operations ide_ops = { - .read_resources = pci_dev_read_resources, - .set_resources = pci_dev_set_resources, - .enable_resources = pci_dev_enable_resources, - .init = ide_init, - .scan_bus = 0, -// .enable = mcp55_enable, - .ops_pci = &mcp55_pci_ops, -}; - -static const struct pci_driver ide_driver __pci_driver = { - .ops = &ide_ops, - .vendor = PCI_VENDOR_ID_NVIDIA, - .device = PCI_DEVICE_ID_NVIDIA_MCP55_IDE, -}; diff --git a/src/southbridge/nvidia/mcp55/lpc.c b/src/southbridge/nvidia/mcp55/lpc.c deleted file mode 100644 index de2de5c090..0000000000 --- a/src/southbridge/nvidia/mcp55/lpc.c +++ /dev/null @@ -1,284 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2003 Linux Networx - * Copyright (C) 2003 SuSE Linux AG - * Copyright (C) 2004 Tyan Computer - * Written by Yinghai Lu for Tyan Computer. - * Copyright (C) 2006,2007 AMD - * Written by Yinghai Lu for AMD. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include "mcp55.h" - -#define NMI_OFF 0 - -// 0x7a or e3 -#define PREVIOUS_POWER_STATE 0x7A - -#define MAINBOARD_POWER_OFF 0 -#define MAINBOARD_POWER_ON 1 -#define SLOW_CPU_OFF 0 -#define SLOW_CPU__ON 1 - -static void lpc_common_init(struct device *dev, int master) -{ - u8 byte; - void *ioapic_base; - - /* IOAPIC initialization. */ - byte = pci_read_config8(dev, 0x74); - byte |= (1 << 0); /* Enable IOAPIC. */ - pci_write_config8(dev, 0x74, byte); - ioapic_base = (void *)pci_read_config32(dev, PCI_BASE_ADDRESS_1); /* 0x14 */ - - if (master) - setup_ioapic(ioapic_base, 0); - else - clear_ioapic(ioapic_base); -} - -static void lpc_slave_init(struct device *dev) -{ - lpc_common_init(dev, 0); -} - -static void enable_hpet(struct device *dev) -{ - unsigned long hpet_address; - - pci_write_config32(dev, 0x44, CONFIG_HPET_ADDRESS|1); - hpet_address=pci_read_config32(dev, 0x44) & 0xfffffffe; - printk(BIOS_DEBUG, "enabling HPET @0x%lx\n", hpet_address); -} - -static void lpc_init(struct device *dev) -{ - u8 byte, byte_old; - int on, nmi_option; - - lpc_common_init(dev, 1); - - /* power after power fail */ - -#if 1 - on = CONFIG_MAINBOARD_POWER_FAILURE_STATE; - get_option(&on, "power_on_after_fail"); - byte = pci_read_config8(dev, PREVIOUS_POWER_STATE); - byte &= ~0x40; - if (!on) - byte |= 0x40; - pci_write_config8(dev, PREVIOUS_POWER_STATE, byte); - printk(BIOS_INFO, "set power %s after power fail\n", on ? "on" : "off"); -#endif - /* Throttle the CPU speed down for testing. */ - on = SLOW_CPU_OFF; - get_option(&on, "slow_cpu"); - if (on) { - u16 pm10_bar; - pm10_bar = (pci_read_config16(dev, 0x60) & 0xff00); - outl(((on << 1) + 0x10), (pm10_bar + 0x10)); - inl(pm10_bar + 0x10); - on = 8 - on; - printk(BIOS_DEBUG, "Throttling CPU %2d.%1.1d percent.\n", - (on * 12) + (on >> 1), (on & 1) * 5); - } - - /* Enable error reporting. */ - /* Set up sync flood detected. */ - byte = pci_read_config8(dev, 0x47); - byte |= (1 << 1); - pci_write_config8(dev, 0x47, byte); - - /* Set up NMI on errors. */ - byte = inb(0x70); /* RTC70 */ - byte_old = byte; - nmi_option = NMI_OFF; - get_option(&nmi_option, "nmi"); - if (nmi_option) - byte &= ~(1 << 7); /* Set NMI. */ - else - byte |= (1 << 7); /* Can't mask NMI from PCI-E and NMI_NOW. */ - if (byte != byte_old) - outb(byte, 0x70); - - /* Initialize the real time clock. */ - cmos_init(0); - - /* Initialize ISA DMA. */ - isa_dma_init(); - - /* Initialize the High Precision Event Timers (HPET). */ - enable_hpet(dev); -} - -static void mcp55_lpc_read_resources(struct device *dev) -{ - struct resource *res; - - /* Get the normal PCI resources of this device. */ - /* We got one for APIC, or one more for TRAP. */ - pci_dev_read_resources(dev); - - /* Add an extra subtractive resource for both memory and I/O. */ - res = new_resource(dev, IOINDEX_SUBTRACTIVE(0, 0)); - res->base = 0; - res->size = 0x1000; - res->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE | - IORESOURCE_ASSIGNED | IORESOURCE_FIXED; - - res = new_resource(dev, IOINDEX_SUBTRACTIVE(1, 0)); - res->base = 0xff800000; - res->size = 0x00800000; /* 8 MB for flash */ - res->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE | - IORESOURCE_ASSIGNED | IORESOURCE_FIXED; - - res = new_resource(dev, 3); /* IOAPIC */ - res->base = IO_APIC_ADDR; - res->size = 0x00001000; - res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; -} - -/** - * Enable resources for children devices. - * - * @param dev The device whose children's resources are to be enabled. - */ -static void mcp55_lpc_enable_childrens_resources(struct device *dev) -{ - u32 reg, reg_var[4]; - int i, var_num = 0; - struct bus *link; - - reg = pci_read_config32(dev, 0xa0); - - for (link = dev->link_list; link; link = link->next) { - struct device *child; - for (child = link->children; child; child = child->sibling) { - if (child->enabled && (child->path.type == DEVICE_PATH_PNP)) { - struct resource *res; - for (res = child->resource_list; res; res = res->next) { - unsigned long base, end; /* Don't need long long. */ - if (!(res->flags & IORESOURCE_IO)) - continue; - base = res->base; - end = resource_end(res); - printk(BIOS_DEBUG, "mcp55 lpc decode:%s, base=0x%08lx, end=0x%08lx\n",dev_path(child),base, end); - switch (base) { - case 0x3f8: /* COM1 */ - reg |= (1 << 0); - break; - case 0x2f8: /* COM2 */ - reg |= (1 << 1); - break; - case 0x378: /* Parallel 1 */ - reg |= (1 << 24); - break; - case 0x3f0: /* FD0 */ - reg |= (1 << 20); - break; - case 0x220: /* Audio 0 */ - reg |= (1 << 8); - break; - case 0x300: /* Midi 0 */ - reg |= (1 << 12); - break; - } - if ((base == 0x290) - || (base >= 0x400)) { - /* Only 4 var; compact them? */ - if (var_num >= 4) - continue; - reg |= (1 << (28 + var_num)); - reg_var[var_num++] = (base & 0xffff) | ((end & 0xffff) << 16); - } - } - } - } - } - pci_write_config32(dev, 0xa0, reg); - for (i = 0; i < var_num; i++) - pci_write_config32(dev, 0xa8 + i * 4, reg_var[i]); -} - -static void mcp55_lpc_enable_resources(struct device *dev) -{ - pci_dev_enable_resources(dev); - mcp55_lpc_enable_childrens_resources(dev); -} - -#if CONFIG(HAVE_ACPI_TABLES) -static void southbridge_acpi_fill_ssdt_generator(struct device *device) -{ - amd_generate_powernow(0, 0, 0); -} -#endif - -static struct device_operations lpc_ops = { - .read_resources = mcp55_lpc_read_resources, - .set_resources = pci_dev_set_resources, - .enable_resources = mcp55_lpc_enable_resources, -#if CONFIG(HAVE_ACPI_TABLES) - .acpi_fill_ssdt_generator = southbridge_acpi_fill_ssdt_generator, - .write_acpi_tables = acpi_write_hpet, -#endif - .init = lpc_init, - .scan_bus = scan_static_bus, - .ops_pci = &mcp55_pci_ops, -}; -static const unsigned short lpc_ids[] = { - PCI_DEVICE_ID_NVIDIA_MCP55_LPC, - PCI_DEVICE_ID_NVIDIA_MCP55_PRO, - PCI_DEVICE_ID_NVIDIA_MCP55_LPC_2, - PCI_DEVICE_ID_NVIDIA_MCP55_LPC_3, - PCI_DEVICE_ID_NVIDIA_MCP55_LPC_4, - PCI_DEVICE_ID_NVIDIA_MCP55_LPC_5, - PCI_DEVICE_ID_NVIDIA_MCP55_LPC_6, - 0 -}; -static const struct pci_driver lpc_driver __pci_driver = { - .ops = &lpc_ops, - .vendor = PCI_VENDOR_ID_NVIDIA, - .devices = lpc_ids, -}; - -static struct device_operations lpc_slave_ops = { - .read_resources = mcp55_lpc_read_resources, - .set_resources = pci_dev_set_resources, - .enable_resources = pci_dev_enable_resources, -#if CONFIG(HAVE_ACPI_TABLES) - .write_acpi_tables = acpi_write_hpet, -#endif - .init = lpc_slave_init, - .ops_pci = &mcp55_pci_ops, -}; - -static const struct pci_driver lpc_driver_slave __pci_driver = { - .ops = &lpc_slave_ops, - .vendor = PCI_VENDOR_ID_NVIDIA, - .device = PCI_DEVICE_ID_NVIDIA_MCP55_SLAVE, -}; diff --git a/src/southbridge/nvidia/mcp55/mcp55.c b/src/southbridge/nvidia/mcp55/mcp55.c deleted file mode 100644 index db646cd659..0000000000 --- a/src/southbridge/nvidia/mcp55/mcp55.c +++ /dev/null @@ -1,234 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2004 Tyan Computer - * Written by Yinghai Lu for Tyan Computer. - * Copyright (C) 2006,2007 AMD - * Written by Yinghai Lu for AMD. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include -#include -#include "mcp55.h" - -static u32 final_reg; - -static struct device *find_lpc_dev(struct device *dev, unsigned int devfn) -{ - struct device *lpc_dev; - - lpc_dev = pcidev_path_behind(dev->bus, devfn); - - if (!lpc_dev) - return lpc_dev; - - if ((lpc_dev->vendor != PCI_VENDOR_ID_NVIDIA) || ( - (lpc_dev->device < PCI_DEVICE_ID_NVIDIA_MCP55_LPC) || - (lpc_dev->device > PCI_DEVICE_ID_NVIDIA_MCP55_PRO))) - { - u32 id; - id = pci_read_config32(lpc_dev, PCI_VENDOR_ID); - if ((id < (PCI_VENDOR_ID_NVIDIA - | (PCI_DEVICE_ID_NVIDIA_MCP55_LPC << 16))) || - (id > (PCI_VENDOR_ID_NVIDIA - | (PCI_DEVICE_ID_NVIDIA_MCP55_PRO << 16)))) - { - lpc_dev = 0; - } - } - - return lpc_dev; -} - -void mcp55_enable(struct device *dev) -{ - struct device *lpc_dev = NULL, *sm_dev = NULL; - unsigned int index = 0, index2 = 0; - u32 reg_old, reg; - u8 byte; - unsigned int deviceid, vendorid, devfn; - int i; - - if (dev->device == 0x0000) { - vendorid = pci_read_config32(dev, PCI_VENDOR_ID); - deviceid = (vendorid >> 16) & 0xffff; - } else { - deviceid = dev->device; - } - - devfn = (dev->path.pci.devfn) & ~7; - switch (deviceid) { - case PCI_DEVICE_ID_NVIDIA_MCP55_HT: - return; - case PCI_DEVICE_ID_NVIDIA_MCP55_SM2: //? - index = 16; - break; - case PCI_DEVICE_ID_NVIDIA_MCP55_USB: - devfn -= (1 << 3); - index = 8; - break; - case PCI_DEVICE_ID_NVIDIA_MCP55_USB2: - devfn -= (1 << 3); - index = 20; - break; - case PCI_DEVICE_ID_NVIDIA_MCP55_NIC: // two - case PCI_DEVICE_ID_NVIDIA_MCP55_NIC_BRIDGE: // two - devfn -= (7 << 3); - index = 10; - for (i = 0; i < 2; i++) { - lpc_dev = find_lpc_dev(dev, devfn - (i << 3)); - if (!lpc_dev) - continue; - index -= i; - devfn -= (i << 3); - break; - } - break; - case PCI_DEVICE_ID_NVIDIA_MCP55_AZA: - devfn -= (5 << 3); - index = 11; - break; - case PCI_DEVICE_ID_NVIDIA_MCP55_IDE: - devfn -= (3 << 3); - index = 14; - break; - case PCI_DEVICE_ID_NVIDIA_MCP55_SATA0: // three - case PCI_DEVICE_ID_NVIDIA_MCP55_SATA1: // three - devfn -= (4 << 3); - index = 22; - i = (dev->path.pci.devfn) & 7; - if (i > 0) - index -= (i + 3); - break; - case PCI_DEVICE_ID_NVIDIA_MCP55_PCI: - devfn -= (5 << 3); - index = 15; - break; - case PCI_DEVICE_ID_NVIDIA_MCP55_PCIE_A: - devfn -= (0x9 << 3); // to LPC - index2 = 9; - break; - case PCI_DEVICE_ID_NVIDIA_MCP55_PCIE_B_C: // two - devfn -= (0xa << 3); // to LPC - index2 = 8; - for (i = 0; i < 2; i++) { - lpc_dev = find_lpc_dev(dev, devfn - (i << 3)); - if (!lpc_dev) - continue; - index2 -= i; - devfn -= (i << 3); - break; - } - break; - case PCI_DEVICE_ID_NVIDIA_MCP55_PCIE_D: - devfn -= (0xc << 3); // to LPC - index2 = 6; - break; - case PCI_DEVICE_ID_NVIDIA_MCP55_PCIE_E: - devfn -= (0xd << 3); // to LPC - index2 = 5; - break; - case PCI_DEVICE_ID_NVIDIA_MCP55_PCIE_F: - devfn -= (0xe << 3); // to LPC - index2 = 4; - break; - default: - index = 0; - } - - if (!lpc_dev) - lpc_dev = find_lpc_dev(dev, devfn); - - if (!lpc_dev) - return; - - if (index2 != 0) { - sm_dev = pcidev_path_behind(dev->bus, devfn + 1); - if (!sm_dev) - return; - if (sm_dev) { - reg_old = reg = pci_read_config32(sm_dev, 0xe4); - if (!dev->enabled) - reg |= (1<bus, devfn + 1); - if (!sm_dev) - return; - - final_reg = pci_read_config32(sm_dev, 0xe8); - final_reg &= ~((1 << 16) | (1 << 8) | (1 << 20) | (1 << 14) - | (1 << 22) | (1 << 18) | (1 << 17) | (1 << 15) - | (1 << 11) | (1 << 10) | (1 << 9)); - pci_write_config32(sm_dev, 0xe8, final_reg); /* Enable all at first. */ - - } - - if (!dev->enabled) { - final_reg |= (1 << index); /* Disable it. */ - /* - * The reason for using final_reg is that if func 1 is disabled, - * then func 2 will become func 1. - * Because of this, we need loop through disabling them all at - * the same time. - */ - } - - /* NIC1 is the final, we need update final reg to 0xe8. */ - if (index == 9) { - sm_dev = pcidev_path_behind(dev->bus, devfn + 1); - if (!sm_dev) - return; - reg_old = pci_read_config32(sm_dev, 0xe8); - if (final_reg != reg_old) - pci_write_config32(sm_dev, 0xe8, final_reg); - } -} - -static void mcp55_set_subsystem(struct device *dev, unsigned int vendor, - unsigned int device) -{ - pci_write_config32(dev, 0x40, - ((device & 0xffff) << 16) | (vendor & 0xffff)); -} - -struct pci_operations mcp55_pci_ops = { - .set_subsystem = mcp55_set_subsystem, -}; - -struct chip_operations southbridge_nvidia_mcp55_ops = { - CHIP_NAME("NVIDIA MCP55 Southbridge") - .enable_dev = mcp55_enable, -}; diff --git a/src/southbridge/nvidia/mcp55/mcp55.h b/src/southbridge/nvidia/mcp55/mcp55.h deleted file mode 100644 index c3e93d3714..0000000000 --- a/src/southbridge/nvidia/mcp55/mcp55.h +++ /dev/null @@ -1,49 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007 AMD - * Written by Yinghai Lu for AMD. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef SOUTHBRIDGE_NVIDIA_MCP55_MCP55_H -#define SOUTHBRIDGE_NVIDIA_MCP55_MCP55_H - -#if CONFIG_HT_CHAIN_END_UNITID_BASE != 0x20 -#define MCP55_DEVN_BASE CONFIG_HT_CHAIN_END_UNITID_BASE -#else -#define MCP55_DEVN_BASE CONFIG_HT_CHAIN_UNITID_BASE -#endif - -#ifndef __ROMCC__ -#include -void mcp55_enable(struct device *dev); -extern struct pci_operations mcp55_pci_ops; -#endif - -void enable_fid_change_on_sb(unsigned int sbbusn, unsigned int sbdn); -void enable_smbus(void); - -/* Concflict declarations with . */ -#if !ENV_RAMSTAGE -int smbus_recv_byte(unsigned int device); -int smbus_send_byte(unsigned int device, unsigned char val); -int smbus_read_byte(unsigned int device, unsigned int address); -int smbus_write_byte(unsigned int device, unsigned int address, unsigned char val); -int smbusx_recv_byte(unsigned int smb_index, unsigned int device); -int smbusx_send_byte(unsigned int smb_index, unsigned int device, unsigned char val); -int smbusx_read_byte(unsigned int smb_index, unsigned int device, unsigned int address); -int smbusx_write_byte(unsigned int smb_index, unsigned int device, unsigned int address, - unsigned char val); -#endif /* !ENV_RAMSTAGE */ - -#endif diff --git a/src/southbridge/nvidia/mcp55/nic.c b/src/southbridge/nvidia/mcp55/nic.c deleted file mode 100644 index 9e350dda26..0000000000 --- a/src/southbridge/nvidia/mcp55/nic.c +++ /dev/null @@ -1,201 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2004 Tyan Computer - * Written by Yinghai Lu for Tyan Computer. - * Copyright (C) 2006,2007 AMD - * Written by Yinghai Lu for AMD. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include -#include -#include -#include -#include -#include - -#include "chip.h" -#include "mcp55.h" - -static int phy_read(u8 *base, unsigned int phy_addr, unsigned int phy_reg) -{ - u32 dword; - unsigned int loop = 0x100; - - write32(base + 0x190, 0x8000); /* Clear MDIO lock bit. */ - mdelay(1); - dword = read32(base + 0x190); - if (dword & (1 << 15)) - return -1; - - write32(base + 0x180, 1); - write32(base + 0x190, (phy_addr << 5) | (phy_reg)); - do { - dword = read32(base + 0x190); - if (--loop == 0) - return -4; - } while ((dword & (1 << 15))); - - dword = read32(base + 0x180); - if (dword & 1) - return -3; - - dword = read32(base + 0x194); - - return dword; -} - -static void phy_detect(u8 *base) -{ - u32 dword; - int i, val; - unsigned int id; - - dword = read32(base + 0x188); - dword &= ~(1 << 20); - write32(base + 0x188, dword); - - phy_read(base, 0, 1); - - for (i = 1; i <= 32; i++) { - int phyaddr = i & 0x1f; - val = phy_read(base, phyaddr, 1); - if (val < 0) - continue; - if ((val & 0xffff) == 0xffff) - continue; - if ((val & 0xffff) == 0) - continue; - if (!(val & 1)) - break; /* Ethernet PHY */ - - val = phy_read(base, phyaddr, 3); - if (val < 0 || val == 0xffff) - continue; - id = val & 0xfc00; - val = phy_read(base, phyaddr, 2); - if (val < 0 || val == 0xffff) - continue; - id |= ((val & 0xffff) << 16); - printk(BIOS_DEBUG, "MCP55 MAC PHY ID 0x%08x PHY ADDR %d\n", - id, i); -// if ((id == 0xe0180000) || (id == 0x0032cc00)) - break; - } - - if (i > 32) - printk(BIOS_DEBUG, "MCP55 MAC PHY not found\n"); -} - -static void nic_init(struct device *dev) -{ - u8 *base; - u32 mac_h = 0, mac_l = 0; - int eeprom_valid = 0; - struct southbridge_nvidia_mcp55_config *conf; - static u32 nic_index = 0; - struct resource *res; - - res = find_resource(dev, 0x10); - - if (!res) - return; - - base = res2mmio(res, 0, 0); - - phy_detect(base); - -#define NvRegPhyInterface 0xC0 -#define PHY_RGMII 0x10000000 - - write32(base + NvRegPhyInterface, PHY_RGMII); - - conf = dev->chip_info; - - if (conf->mac_eeprom_smbus != 0) { -// read MAC address from EEPROM at first - struct device *dev_eeprom; - dev_eeprom = dev_find_slot_on_smbus(conf->mac_eeprom_smbus, conf->mac_eeprom_addr); - - if (dev_eeprom) { - // if that is valid we will use that - unsigned char dat[6]; - int status; - int i; - for (i=0;i<6;i++) { - status = smbus_read_byte(dev_eeprom, i); - if (status < 0) break; - dat[i] = status & 0xff; - } - if (status >= 0) { - mac_l = 0; - for (i=3;i>=0;i--) { - mac_l <<= 8; - mac_l += dat[i]; - } - if (mac_l != 0xffffffff) { - mac_l += nic_index; - mac_h = 0; - for (i=5;i>=4;i--) { - mac_h <<= 8; - mac_h += dat[i]; - } - eeprom_valid = 1; - } - } - } - } -// if that is invalid we will read that from romstrap - if (!eeprom_valid) { - u32 *mac_pos; - mac_pos = (u32 *)0xffffffd0; // refer to romstrap.inc and romstrap.ld - mac_l = read32(mac_pos) + nic_index; // overflow? - mac_h = read32(mac_pos + 1); - - } -#if 1 -// set that into NIC MMIO -#define NvRegMacAddrA 0xA8 -#define NvRegMacAddrB 0xAC - write32(base + NvRegMacAddrA, mac_l); - write32(base + NvRegMacAddrB, mac_h); -#else -// set that into NIC - pci_write_config32(dev, 0xa8, mac_l); - pci_write_config32(dev, 0xac, mac_h); -#endif - - nic_index++; -} - -static struct device_operations nic_ops = { - .read_resources = pci_dev_read_resources, - .set_resources = pci_dev_set_resources, - .enable_resources = pci_dev_enable_resources, - .init = nic_init, - .scan_bus = 0, -// .enable = mcp55_enable, - .ops_pci = &mcp55_pci_ops, -}; -static const struct pci_driver nic_driver __pci_driver = { - .ops = &nic_ops, - .vendor = PCI_VENDOR_ID_NVIDIA, - .device = PCI_DEVICE_ID_NVIDIA_MCP55_NIC, -}; -static const struct pci_driver nic_bridge_driver __pci_driver = { - .ops = &nic_ops, - .vendor = PCI_VENDOR_ID_NVIDIA, - .device = PCI_DEVICE_ID_NVIDIA_MCP55_NIC_BRIDGE, -}; diff --git a/src/southbridge/nvidia/mcp55/pci.c b/src/southbridge/nvidia/mcp55/pci.c deleted file mode 100644 index bd92c7eaed..0000000000 --- a/src/southbridge/nvidia/mcp55/pci.c +++ /dev/null @@ -1,97 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2004 Tyan Computer - * Written by Yinghai Lu for Tyan Computer. - * Copyright (C) 2006,2007 AMD - * Written by Yinghai Lu for AMD. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include -#include -#include -#include -#include "mcp55.h" - -static void pci_init(struct device *dev) -{ - u32 dword; - u16 word; - struct device *pci_domain_dev; - struct resource *mem, *pref; - - /* System error enable */ - dword = pci_read_config32(dev, 0x04); - dword |= (1<<8); /* System error enable */ - dword |= (1<<30); /* Clear possible errors */ - pci_write_config32(dev, 0x04, dword); - -#if 1 - //only need (a01,xx] - word = pci_read_config16(dev, 0x48); - word |= (1<<0); /* MRL2MRM */ - word |= (1<<2); /* MR2MRM */ - pci_write_config16(dev, 0x48, word); -#endif - -#if 1 - dword = pci_read_config32(dev, 0x4c); - dword |= 0x00440000; /*TABORT_SER_ENABLE Park Last Enable.*/ - pci_write_config32(dev, 0x4c, dword); -#endif - - pci_domain_dev = dev->bus->dev; - while (pci_domain_dev) { - if (pci_domain_dev->path.type == DEVICE_PATH_DOMAIN) - break; - pci_domain_dev = pci_domain_dev->bus->dev; - } - - if (!pci_domain_dev) - return; /* Impossible */ - - pref = probe_resource(pci_domain_dev, IOINDEX_SUBTRACTIVE(2,0)); - mem = probe_resource(pci_domain_dev, IOINDEX_SUBTRACTIVE(1,0)); - - if (!mem) - return; /* Impossible */ - - if (!pref || pref->base > mem->base) { - dword = mem->base & (0xffff0000UL); - printk(BIOS_DEBUG, "PCI DOMAIN mem base = 0x%010Lx\n", mem->base); - } else { - dword = pref->base & (0xffff0000UL); - printk(BIOS_DEBUG, "PCI DOMAIN pref base = 0x%010Lx\n", pref->base); - } - - printk(BIOS_DEBUG, "[0x50] <-- 0x%08x\n", dword); - pci_write_config32(dev, 0x50, dword); /* TOM */ -} - -static struct device_operations pci_ops = { - .read_resources = pci_bus_read_resources, - .set_resources = pci_dev_set_resources, - .enable_resources = pci_bus_enable_resources, - .init = pci_init, - .scan_bus = pci_scan_bridge, -// .enable = mcp55_enable, - .reset_bus = pci_bus_reset, -}; - -static const struct pci_driver pci_driver __pci_driver = { - .ops = &pci_ops, - .vendor = PCI_VENDOR_ID_NVIDIA, - .device = PCI_DEVICE_ID_NVIDIA_MCP55_PCI, -}; diff --git a/src/southbridge/nvidia/mcp55/pcie.c b/src/southbridge/nvidia/mcp55/pcie.c deleted file mode 100644 index 0a352443b4..0000000000 --- a/src/southbridge/nvidia/mcp55/pcie.c +++ /dev/null @@ -1,61 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2004 Tyan Computer - * Written by Yinghai Lu for Tyan Computer. - * Copyright (C) 2006,2007 AMD - * Written by Yinghai Lu for AMD. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include -#include -#include "mcp55.h" - -static void pcie_init(struct device *dev) -{ - /* Enable pci error detecting */ - u32 dword; - - /* System error enable */ - dword = pci_read_config32(dev, 0x04); - dword |= (1<<8); /* System error enable */ - dword |= (1<<30); /* Clear possible errors */ - pci_write_config32(dev, 0x04, dword); - -} - -static struct device_operations pcie_ops = { - .read_resources = pci_bus_read_resources, - .set_resources = pci_dev_set_resources, - .enable_resources = pci_bus_enable_resources, - .init = pcie_init, - .scan_bus = pci_scan_bridge, -// .enable = mcp55_enable, -}; - -static const unsigned short pcie_ids[] = { - PCI_DEVICE_ID_NVIDIA_MCP55_PCIE_B_C, - PCI_DEVICE_ID_NVIDIA_MCP55_PCIE_E, - PCI_DEVICE_ID_NVIDIA_MCP55_PCIE_A, - PCI_DEVICE_ID_NVIDIA_MCP55_PCIE_F, - PCI_DEVICE_ID_NVIDIA_MCP55_PCIE_D, - 0 -}; - -static const struct pci_driver pciebc_driver __pci_driver = { - .ops = &pcie_ops, - .vendor = PCI_VENDOR_ID_NVIDIA, - .devices= pcie_ids, -}; diff --git a/src/southbridge/nvidia/mcp55/reset.c b/src/southbridge/nvidia/mcp55/reset.c deleted file mode 100644 index d6f7f6f337..0000000000 --- a/src/southbridge/nvidia/mcp55/reset.c +++ /dev/null @@ -1,34 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2004 Tyan Computer - * Written by Yinghai Lu for Tyan Computer. - * Copyright (C) 2006,2007 AMD - * Written by Yinghai Lu for AMD. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#define __SIMPLE_DEVICE__ - -#include -#include - -#include "../../../northbridge/amd/amdk8/reset_test.c" - -void do_board_reset(void) -{ - set_bios_reset(); - /* Try rebooting through port 0xcf9 */ - /* Actually it is not a real hard_reset --- it only reset coherent link table, but not reset link freq and width */ - outb((0 <<3)|(0<<2)|(1<<1), 0xcf9); - outb((0 <<3)|(1<<2)|(1<<1), 0xcf9); -} diff --git a/src/southbridge/nvidia/mcp55/romstrap.S b/src/southbridge/nvidia/mcp55/romstrap.S deleted file mode 100644 index ff170a9927..0000000000 --- a/src/southbridge/nvidia/mcp55/romstrap.S +++ /dev/null @@ -1,55 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2004 Tyan Computer - * Written by Yinghai Lu for Tyan Computer. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - - .section ".romstrap", "a", @progbits - - - .globl __romstrap_start -__romstrap_start: -rstables: - .long 0x2b16d065 - .long 0x0 - .long 0x0 - .long linkedlist - -linkedlist: - .long 0x0003001C // 10h - .long 0x08000000 // 14h - .long 0x00000000 // 18h - .long 0xFFFFFFFF // 1Ch - - .long 0xFFFFFFFF // 20h - .long 0xFFFFFFFF // 24h - .long 0xFFFFFFFF // 28h - .long 0xFFFFFFFF // 2Ch - - .long 0x81543266 // 30h, MAC address low 4 byte ---> keep it in 0xffffffd0 - .long 0x000000E0 // 34h, MAC address high 4 byte - - .long 0x002309CE // 38h, UUID low 4 byte - .long 0x00E08100 // 3Ch, UUID high 4 byte - -rspointers: - .long rstables // It will be 0xffffffe0 - .long rstables - .long rstables - .long rstables - - .globl __romstrap_end - -__romstrap_end: -.previous diff --git a/src/southbridge/nvidia/mcp55/romstrap.ld b/src/southbridge/nvidia/mcp55/romstrap.ld deleted file mode 100644 index 621cebd9e2..0000000000 --- a/src/southbridge/nvidia/mcp55/romstrap.ld +++ /dev/null @@ -1,23 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007 AMD - * Written by Yinghai Lu for AMD. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -SECTIONS { - . = (0xffffffff - 0x10) - (__romstrap_end - __romstrap_start) + 1; - .romstrap (.): { - KEEP(*(.romstrap)) - } -} diff --git a/src/southbridge/nvidia/mcp55/sata.c b/src/southbridge/nvidia/mcp55/sata.c deleted file mode 100644 index 9f70890ff7..0000000000 --- a/src/southbridge/nvidia/mcp55/sata.c +++ /dev/null @@ -1,89 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2004 Tyan Computer - * Written by Yinghai Lu for Tyan Computer. - * Copyright (C) 2006,2007 AMD - * Written by Yinghai Lu for AMD. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include -#include -#include - -#include "chip.h" -#include "mcp55.h" - -static void sata_init(struct device *dev) -{ - u32 dword; - - struct southbridge_nvidia_mcp55_config *conf; - conf = dev->chip_info; - - dword = pci_read_config32(dev, 0x50); - /* Ensure prefetch is disabled */ - dword &= ~((1 << 15) | (1 << 13)); - if (conf) { - if (conf->sata1_enable) { - /* Enable secondary SATA interface */ - dword |= (1<<0); - printk(BIOS_DEBUG, "SATA S\t"); - } - if (conf->sata0_enable) { - /* Enable primary SATA interface */ - dword |= (1<<1); - printk(BIOS_DEBUG, "SATA P\n"); - } - } else { - dword |= (1<<1) | (1<<0); - printk(BIOS_DEBUG, "SATA P and S\n"); - } - - -#if 1 - dword &= ~(0x1f<<24); - dword |= (0x15<<24); -#endif - pci_write_config32(dev, 0x50, dword); - - dword = pci_read_config32(dev, 0xf8); - dword |= 2; - pci_write_config32(dev, 0xf8, dword); - - -} - -static struct device_operations sata_ops = { - .read_resources = pci_dev_read_resources, - .set_resources = pci_dev_set_resources, - .enable_resources = pci_dev_enable_resources, -// .enable = mcp55_enable, - .init = sata_init, - .scan_bus = 0, - .ops_pci = &mcp55_pci_ops, -}; - -static const struct pci_driver sata0_driver __pci_driver = { - .ops = &sata_ops, - .vendor = PCI_VENDOR_ID_NVIDIA, - .device = PCI_DEVICE_ID_NVIDIA_MCP55_SATA0, -}; - -static const struct pci_driver sata1_driver __pci_driver = { - .ops = &sata_ops, - .vendor = PCI_VENDOR_ID_NVIDIA, - .device = PCI_DEVICE_ID_NVIDIA_MCP55_SATA1, -}; diff --git a/src/southbridge/nvidia/mcp55/smbus.c b/src/southbridge/nvidia/mcp55/smbus.c deleted file mode 100644 index 0f8dbe3fc5..0000000000 --- a/src/southbridge/nvidia/mcp55/smbus.c +++ /dev/null @@ -1,132 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2004 Tyan Computer - * Written by Yinghai Lu for Tyan Computer. - * Copyright (C) 2006,2007 AMD - * Written by Yinghai Lu for AMD. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include -#include -#include "mcp55.h" -#include "smbus.h" - -static int lsmbus_recv_byte(struct device *dev) -{ - unsigned int device; - struct resource *res; - struct bus *pbus; - - device = dev->path.i2c.device; - pbus = get_pbus_smbus(dev); - - res = find_resource(pbus->dev, 0x20 + (pbus->link_num * 4)); - - return do_smbus_recv_byte(res->base, device); -} - -static int lsmbus_send_byte(struct device *dev, u8 val) -{ - unsigned int device; - struct resource *res; - struct bus *pbus; - - device = dev->path.i2c.device; - pbus = get_pbus_smbus(dev); - - res = find_resource(pbus->dev, 0x20 + (pbus->link_num * 4)); - - return do_smbus_send_byte(res->base, device, val); -} - -static int lsmbus_read_byte(struct device *dev, u8 address) -{ - unsigned int device; - struct resource *res; - struct bus *pbus; - - device = dev->path.i2c.device; - pbus = get_pbus_smbus(dev); - - res = find_resource(pbus->dev, 0x20 + (pbus->link_num * 4)); - - return do_smbus_read_byte(res->base, device, address); -} - -static int lsmbus_write_byte(struct device *dev, u8 address, u8 val) -{ - unsigned int device; - struct resource *res; - struct bus *pbus; - - device = dev->path.i2c.device; - pbus = get_pbus_smbus(dev); - - res = find_resource(pbus->dev, 0x20 + (pbus->link_num * 4)); - - return do_smbus_write_byte(res->base, device, address, val); -} -static struct smbus_bus_operations lops_smbus_bus = { - .recv_byte = lsmbus_recv_byte, - .send_byte = lsmbus_send_byte, - .read_byte = lsmbus_read_byte, - .write_byte = lsmbus_write_byte, -}; - -#if CONFIG(HAVE_ACPI_TABLES) -unsigned int pm_base; -#endif - -static void mcp55_sm_read_resources(struct device *dev) -{ - unsigned long index; - - /* Get the normal pci resources of this device */ - pci_dev_read_resources(dev); - - for (index = 0x60; index <= 0x68; index+=4) { // We got another 3. - pci_get_resource(dev, index); - } - compact_resources(dev); -} - -static void mcp55_sm_init(struct device *dev) -{ -#if CONFIG(HAVE_ACPI_TABLES) - struct resource *res; - - res = find_resource(dev, 0x60); - - if (res) - pm_base = res->base; -#endif -} - -static struct device_operations smbus_ops = { - .read_resources = mcp55_sm_read_resources, - .set_resources = pci_dev_set_resources, - .enable_resources = pci_dev_enable_resources, - .init = mcp55_sm_init, - .scan_bus = scan_smbus, -// .enable = mcp55_enable, - .ops_pci = &mcp55_pci_ops, - .ops_smbus_bus = &lops_smbus_bus, -}; -static const struct pci_driver smbus_driver __pci_driver = { - .ops = &smbus_ops, - .vendor = PCI_VENDOR_ID_NVIDIA, - .device = PCI_DEVICE_ID_NVIDIA_MCP55_SM2, -}; diff --git a/src/southbridge/nvidia/mcp55/smbus.h b/src/southbridge/nvidia/mcp55/smbus.h deleted file mode 100644 index 91e48ba5fe..0000000000 --- a/src/southbridge/nvidia/mcp55/smbus.h +++ /dev/null @@ -1,173 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2004 Tyan Computer - * Written by Yinghai Lu for Tyan Computer. - * Copyright (C) 2006,2007 AMD - * Written by Yinghai Lu for AMD. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include - -#define SMBHSTSTAT 0x1 -#define SMBHSTPRTCL 0x0 -#define SMBHSTCMD 0x3 -#define SMBXMITADD 0x2 -#define SMBHSTDAT0 0x4 -#define SMBHSTDAT1 0x5 - -/* Between 1-10 seconds, We should never timeout normally - * Longer than this is just painful when a timeout condition occurs. - */ -#define SMBUS_TIMEOUT (100*1000*10) - -static inline void smbus_delay(void) -{ - outb(0x80, 0x80); -} - -static int smbus_wait_until_done(unsigned int smbus_io_base) -{ - unsigned long loops; - loops = SMBUS_TIMEOUT; - do { - unsigned char val; - smbus_delay(); - - val = inb(smbus_io_base + SMBHSTSTAT); - if ((val & 0xff) != 0) { - return 0; - } - } while (--loops); - return -3; -} -static int do_smbus_recv_byte(unsigned int smbus_io_base, unsigned int device) -{ - unsigned char global_status_register; - unsigned char byte; - - /* set the device I'm talking to */ - outb(((device & 0x7f) << 1)|1 , smbus_io_base + SMBXMITADD); - smbus_delay(); - - /* byte data recv */ - outb(0x05, smbus_io_base + SMBHSTPRTCL); - smbus_delay(); - - /* poll for transaction completion */ - if (smbus_wait_until_done(smbus_io_base) < 0) { - return -3; - } - - global_status_register = inb(smbus_io_base + SMBHSTSTAT) & 0x80; /* lose check */ - - /* read results of transaction */ - byte = inb(smbus_io_base + SMBHSTCMD); - - if (global_status_register != 0x80) { // lose check, otherwise it should be 0 - return -1; - } - return byte; -} -static int do_smbus_send_byte(unsigned int smbus_io_base, unsigned int device, unsigned char val) -{ - unsigned int global_status_register; - - outb(val, smbus_io_base + SMBHSTDAT0); - smbus_delay(); - - /* set the command... */ - outb(val, smbus_io_base + SMBHSTCMD); - smbus_delay(); - - /* set the device I'm talking to */ - outb(((device & 0x7f) << 1) | 0, smbus_io_base + SMBXMITADD); - smbus_delay(); - - /* set up for a byte data write */ - outb(0x04, smbus_io_base + SMBHSTPRTCL); - smbus_delay(); - - /* poll for transaction completion */ - if (smbus_wait_until_done(smbus_io_base) < 0) { - return -3; - } - global_status_register = inb(smbus_io_base + SMBHSTSTAT) & 0x80; /* lose check */ - - if (global_status_register != 0x80) { - return -1; - } - return 0; -} -static int do_smbus_read_byte(unsigned int smbus_io_base, unsigned int device, unsigned int address) -{ - unsigned char global_status_register; - unsigned char byte; - - /* set the device I'm talking to */ - outb(((device & 0x7f) << 1)|1 , smbus_io_base + SMBXMITADD); - smbus_delay(); - /* set the command/address... */ - outb(address & 0xff, smbus_io_base + SMBHSTCMD); - smbus_delay(); - /* byte data read */ - outb(0x07, smbus_io_base + SMBHSTPRTCL); - smbus_delay(); - - /* poll for transaction completion */ - if (smbus_wait_until_done(smbus_io_base) < 0) { - return -3; - } - - global_status_register = inb(smbus_io_base + SMBHSTSTAT) & 0x80; /* lose check */ - - /* read results of transaction */ - byte = inb(smbus_io_base + SMBHSTDAT0); - - if (global_status_register != 0x80) { // lose check, otherwise it should be 0 - return -1; - } - return byte; -} - - -static int do_smbus_write_byte(unsigned int smbus_io_base, unsigned int device, unsigned int address, unsigned char val) -{ - unsigned int global_status_register; - - outb(val, smbus_io_base + SMBHSTDAT0); - smbus_delay(); - - /* set the device I'm talking to */ - outb(((device & 0x7f) << 1) | 0, smbus_io_base + SMBXMITADD); - smbus_delay(); - - outb(address & 0xff, smbus_io_base + SMBHSTCMD); - smbus_delay(); - - /* set up for a byte data write */ - outb(0x06, smbus_io_base + SMBHSTPRTCL); - smbus_delay(); - - /* poll for transaction completion */ - if (smbus_wait_until_done(smbus_io_base) < 0) { - return -3; - } - global_status_register = inb(smbus_io_base + SMBHSTSTAT) & 0x80; /* lose check */ - - if (global_status_register != 0x80) { - return -1; - } - return 0; -} diff --git a/src/southbridge/nvidia/mcp55/usb.c b/src/southbridge/nvidia/mcp55/usb.c deleted file mode 100644 index 46e27750aa..0000000000 --- a/src/southbridge/nvidia/mcp55/usb.c +++ /dev/null @@ -1,39 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2004 Tyan Computer - * Written by Yinghai Lu for Tyan Computer. - * Copyright (C) 2006,2007 AMD - * Written by Yinghai Lu for AMD. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include -#include "mcp55.h" - -static struct device_operations usb_ops = { - .read_resources = pci_dev_read_resources, - .set_resources = pci_dev_set_resources, - .enable_resources = pci_dev_enable_resources, - .init = 0, -// .enable = mcp55_enable, - .scan_bus = 0, - .ops_pci = &mcp55_pci_ops, -}; - -static const struct pci_driver usb_driver __pci_driver = { - .ops = &usb_ops, - .vendor = PCI_VENDOR_ID_NVIDIA, - .device = PCI_DEVICE_ID_NVIDIA_MCP55_USB, -}; diff --git a/src/southbridge/nvidia/mcp55/usb2.c b/src/southbridge/nvidia/mcp55/usb2.c deleted file mode 100644 index 590dedf04a..0000000000 --- a/src/southbridge/nvidia/mcp55/usb2.c +++ /dev/null @@ -1,49 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2004 Tyan Computer - * Written by Yinghai Lu for Tyan Computer. - * Copyright (C) 2006,2007 AMD - * Written by Yinghai Lu for AMD. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include -#include -#include "mcp55.h" -#include - -static void usb2_init(struct device *dev) -{ - u32 dword; - dword = pci_read_config32(dev, 0xf8); - dword |= 40; - pci_write_config32(dev, 0xf8, dword); -} - -static struct device_operations usb2_ops = { - .read_resources = pci_ehci_read_resources, - .set_resources = pci_dev_set_resources, - .enable_resources = pci_dev_enable_resources, - .init = usb2_init, -// .enable = mcp55_enable, - .scan_bus = 0, - .ops_pci = &mcp55_pci_ops, -}; - -static const struct pci_driver usb2_driver __pci_driver = { - .ops = &usb2_ops, - .vendor = PCI_VENDOR_ID_NVIDIA, - .device = PCI_DEVICE_ID_NVIDIA_MCP55_USB2, -}; From ffcac3eb502bbe0acbb30d6fe804f00e07461a7a Mon Sep 17 00:00:00 2001 From: Arthur Heymans Date: Tue, 19 Nov 2019 15:46:49 +0100 Subject: [PATCH 0301/1242] nb/amd/fam10: Drop support MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Relocatable ramstage, postcar stage and C_ENVIRONMENT_BOOTBLOCK are now mandatory features, which this platform lacks. Change-Id: If36ef0749dbb661f731fb04829bd7e2202ebb422 Signed-off-by: Arthur Heymans Reviewed-on: https://review.coreboot.org/c/coreboot/+/36962 Tested-by: build bot (Jenkins) Reviewed-by: HAOUAS Elyes Reviewed-by: Kyösti Mälkki Reviewed-by: Angel Pons --- src/cpu/amd/family_10h-family_15h/fidvid.c | 4 +- src/cpu/amd/family_10h-family_15h/init_cpus.c | 2 +- src/device/device_const.c | 7 - src/include/device/hypertransport_def.h | 3 +- .../amd/agesa/family14/acpi/northbridge.asl | 2 +- .../family14/acpi}/thermal_mixin.asl | 0 src/northbridge/amd/amdfam10/Kconfig | 145 - src/northbridge/amd/amdfam10/Makefile.inc | 34 - src/northbridge/amd/amdfam10/acpi.c | 351 - src/northbridge/amd/amdfam10/amdfam10.h | 1025 -- .../amd/amdfam10/amdfam10_util.asl | 321 - src/northbridge/amd/amdfam10/amdfam10_util.c | 112 - src/northbridge/amd/amdfam10/bootblock.c | 22 - src/northbridge/amd/amdfam10/chip.h | 25 - src/northbridge/amd/amdfam10/debug.c | 324 - src/northbridge/amd/amdfam10/debug.h | 45 - src/northbridge/amd/amdfam10/early_ht.c | 176 - src/northbridge/amd/amdfam10/early_ht.h | 21 - src/northbridge/amd/amdfam10/get_pci1234.c | 132 - src/northbridge/amd/amdfam10/ht_config.c | 229 - src/northbridge/amd/amdfam10/ht_config.h | 54 - src/northbridge/amd/amdfam10/inline_helper.c | 31 - src/northbridge/amd/amdfam10/link_control.c | 153 - src/northbridge/amd/amdfam10/misc_control.c | 261 - src/northbridge/amd/amdfam10/nb_control.c | 85 - src/northbridge/amd/amdfam10/northbridge.c | 1928 ---- src/northbridge/amd/amdfam10/northbridge.h | 21 - src/northbridge/amd/amdfam10/nums.h | 36 - src/northbridge/amd/amdfam10/pci.c | 72 - src/northbridge/amd/amdfam10/pci.h | 26 - src/northbridge/amd/amdfam10/raminit.h | 47 - src/northbridge/amd/amdfam10/raminit_amdmct.c | 620 -- .../amd/amdfam10/raminit_sysinfo_in_ram.c | 81 - src/northbridge/amd/amdfam10/reset_test.c | 136 - src/northbridge/amd/amdfam10/resourcemap.c | 282 - .../amd/amdfam10/setup_resource_map.c | 184 - src/northbridge/amd/amdfam10/util.c | 261 - src/northbridge/amd/amdht/AsPsDefs.h | 273 - src/northbridge/amd/amdht/AsPsNb.c | 121 - src/northbridge/amd/amdht/AsPsNb.h | 22 - src/northbridge/amd/amdht/Makefile.inc | 5 - src/northbridge/amd/amdht/comlib.c | 238 - src/northbridge/amd/amdht/comlib.h | 42 - src/northbridge/amd/amdht/h3ffeat.h | 180 - src/northbridge/amd/amdht/h3finit.c | 1879 ---- src/northbridge/amd/amdht/h3finit.h | 620 -- src/northbridge/amd/amdht/h3gtopo.h | 355 - src/northbridge/amd/amdht/h3ncmn.c | 2549 ----- src/northbridge/amd/amdht/h3ncmn.h | 115 - src/northbridge/amd/amdht/ht_wrapper.c | 384 - src/northbridge/amd/amdht/ht_wrapper.h | 28 - src/northbridge/amd/amdht/porting.h | 79 - src/northbridge/amd/amdk8/amdk8.h | 31 - src/northbridge/amd/amdk8/reset_test.c | 94 - src/northbridge/amd/amdmct/amddefs.h | 158 - src/northbridge/amd/amdmct/mct/Makefile.inc | 16 - src/northbridge/amd/amdmct/mct/mct.h | 539 -- src/northbridge/amd/amdmct/mct/mct_d.c | 3980 -------- src/northbridge/amd/amdmct/mct/mct_d.h | 804 -- src/northbridge/amd/amdmct/mct/mct_d_gcc.c | 351 - src/northbridge/amd/amdmct/mct/mct_d_gcc.h | 48 - src/northbridge/amd/amdmct/mct/mctardk3.c | 179 - src/northbridge/amd/amdmct/mct/mctardk4.c | 149 - src/northbridge/amd/amdmct/mct/mctchi_d.c | 125 - src/northbridge/amd/amdmct/mct/mctcsi_d.c | 140 - src/northbridge/amd/amdmct/mct/mctdqs_d.c | 1207 --- src/northbridge/amd/amdmct/mct/mctecc_d.c | 314 - src/northbridge/amd/amdmct/mct/mctgr.c | 84 - src/northbridge/amd/amdmct/mct/mcthdi.c | 30 - src/northbridge/amd/amdmct/mct/mctmtr_d.c | 254 - src/northbridge/amd/amdmct/mct/mctndi_d.c | 234 - src/northbridge/amd/amdmct/mct/mctpro_d.c | 396 - src/northbridge/amd/amdmct/mct/mctsrc.c | 1090 --- src/northbridge/amd/amdmct/mct/mctsrc1p.c | 91 - src/northbridge/amd/amdmct/mct/mctsrc2p.c | 130 - src/northbridge/amd/amdmct/mct/mcttmrl.c | 409 - .../amd/amdmct/mct_ddr3/Makefile.inc | 31 - src/northbridge/amd/amdmct/mct_ddr3/mct_d.c | 8220 ----------------- src/northbridge/amd/amdmct/mct_ddr3/mct_d.h | 1165 --- .../amd/amdmct/mct_ddr3/mct_d_gcc.c | 296 - .../amd/amdmct/mct_ddr3/mct_d_gcc.h | 50 - .../amd/amdmct/mct_ddr3/mctardk5.c | 100 - .../amd/amdmct/mct_ddr3/mctardk6.c | 114 - .../amd/amdmct/mct_ddr3/mctchi_d.c | 123 - .../amd/amdmct/mct_ddr3/mctcsi_d.c | 144 - .../amd/amdmct/mct_ddr3/mctdqs_d.c | 2493 ----- .../amd/amdmct/mct_ddr3/mctecc_d.c | 389 - src/northbridge/amd/amdmct/mct_ddr3/mcthdi.c | 33 - src/northbridge/amd/amdmct/mct_ddr3/mcthwl.c | 305 - .../amd/amdmct/mct_ddr3/mctmtr_d.c | 256 - .../amd/amdmct/mct_ddr3/mctndi_d.c | 233 - src/northbridge/amd/amdmct/mct_ddr3/mctprob.c | 45 - src/northbridge/amd/amdmct/mct_ddr3/mctproc.c | 113 - src/northbridge/amd/amdmct/mct_ddr3/mctprod.c | 66 - src/northbridge/amd/amdmct/mct_ddr3/mctrci.c | 474 - src/northbridge/amd/amdmct/mct_ddr3/mctsdi.c | 1210 --- src/northbridge/amd/amdmct/mct_ddr3/mctsrc.c | 2438 ----- .../amd/amdmct/mct_ddr3/mctsrc1p.c | 104 - .../amd/amdmct/mct_ddr3/mctsrc2p.c | 126 - src/northbridge/amd/amdmct/mct_ddr3/mcttmrl.c | 398 - src/northbridge/amd/amdmct/mct_ddr3/mctwl.c | 509 - src/northbridge/amd/amdmct/mct_ddr3/mhwlc_d.c | 1519 --- src/northbridge/amd/amdmct/mct_ddr3/modtrd.c | 95 - .../amd/amdmct/mct_ddr3/modtrdim.c | 262 - src/northbridge/amd/amdmct/mct_ddr3/mport_d.c | 42 - .../amd/amdmct/mct_ddr3/mutilc_d.c | 374 - src/northbridge/amd/amdmct/mct_ddr3/mwlc_d.h | 192 - src/northbridge/amd/amdmct/mct_ddr3/s3utils.c | 1237 --- src/northbridge/amd/amdmct/mct_ddr3/s3utils.h | 31 - .../amd/amdmct/wrappers/Makefile.inc | 5 - src/northbridge/amd/amdmct/wrappers/mcti.h | 153 - src/northbridge/amd/amdmct/wrappers/mcti_d.c | 543 -- 112 files changed, 5 insertions(+), 48884 deletions(-) rename src/northbridge/amd/{amdfam10 => agesa/family14/acpi}/thermal_mixin.asl (100%) delete mode 100644 src/northbridge/amd/amdfam10/Kconfig delete mode 100644 src/northbridge/amd/amdfam10/Makefile.inc delete mode 100644 src/northbridge/amd/amdfam10/acpi.c delete mode 100644 src/northbridge/amd/amdfam10/amdfam10.h delete mode 100644 src/northbridge/amd/amdfam10/amdfam10_util.asl delete mode 100644 src/northbridge/amd/amdfam10/amdfam10_util.c delete mode 100644 src/northbridge/amd/amdfam10/bootblock.c delete mode 100644 src/northbridge/amd/amdfam10/chip.h delete mode 100644 src/northbridge/amd/amdfam10/debug.c delete mode 100644 src/northbridge/amd/amdfam10/debug.h delete mode 100644 src/northbridge/amd/amdfam10/early_ht.c delete mode 100644 src/northbridge/amd/amdfam10/early_ht.h delete mode 100644 src/northbridge/amd/amdfam10/get_pci1234.c delete mode 100644 src/northbridge/amd/amdfam10/ht_config.c delete mode 100644 src/northbridge/amd/amdfam10/ht_config.h delete mode 100644 src/northbridge/amd/amdfam10/inline_helper.c delete mode 100644 src/northbridge/amd/amdfam10/link_control.c delete mode 100644 src/northbridge/amd/amdfam10/misc_control.c delete mode 100644 src/northbridge/amd/amdfam10/nb_control.c delete mode 100644 src/northbridge/amd/amdfam10/northbridge.c delete mode 100644 src/northbridge/amd/amdfam10/northbridge.h delete mode 100644 src/northbridge/amd/amdfam10/nums.h delete mode 100644 src/northbridge/amd/amdfam10/pci.c delete mode 100644 src/northbridge/amd/amdfam10/pci.h delete mode 100644 src/northbridge/amd/amdfam10/raminit.h delete mode 100644 src/northbridge/amd/amdfam10/raminit_amdmct.c delete mode 100644 src/northbridge/amd/amdfam10/raminit_sysinfo_in_ram.c delete mode 100644 src/northbridge/amd/amdfam10/reset_test.c delete mode 100644 src/northbridge/amd/amdfam10/resourcemap.c delete mode 100644 src/northbridge/amd/amdfam10/setup_resource_map.c delete mode 100644 src/northbridge/amd/amdfam10/util.c delete mode 100644 src/northbridge/amd/amdht/AsPsDefs.h delete mode 100644 src/northbridge/amd/amdht/AsPsNb.c delete mode 100644 src/northbridge/amd/amdht/AsPsNb.h delete mode 100644 src/northbridge/amd/amdht/Makefile.inc delete mode 100644 src/northbridge/amd/amdht/comlib.c delete mode 100644 src/northbridge/amd/amdht/comlib.h delete mode 100644 src/northbridge/amd/amdht/h3ffeat.h delete mode 100644 src/northbridge/amd/amdht/h3finit.c delete mode 100644 src/northbridge/amd/amdht/h3finit.h delete mode 100644 src/northbridge/amd/amdht/h3gtopo.h delete mode 100644 src/northbridge/amd/amdht/h3ncmn.c delete mode 100644 src/northbridge/amd/amdht/h3ncmn.h delete mode 100644 src/northbridge/amd/amdht/ht_wrapper.c delete mode 100644 src/northbridge/amd/amdht/ht_wrapper.h delete mode 100644 src/northbridge/amd/amdht/porting.h delete mode 100644 src/northbridge/amd/amdk8/amdk8.h delete mode 100644 src/northbridge/amd/amdk8/reset_test.c delete mode 100644 src/northbridge/amd/amdmct/amddefs.h delete mode 100644 src/northbridge/amd/amdmct/mct/Makefile.inc delete mode 100644 src/northbridge/amd/amdmct/mct/mct.h delete mode 100644 src/northbridge/amd/amdmct/mct/mct_d.c delete mode 100644 src/northbridge/amd/amdmct/mct/mct_d.h delete mode 100644 src/northbridge/amd/amdmct/mct/mct_d_gcc.c delete mode 100644 src/northbridge/amd/amdmct/mct/mct_d_gcc.h delete mode 100644 src/northbridge/amd/amdmct/mct/mctardk3.c delete mode 100644 src/northbridge/amd/amdmct/mct/mctardk4.c delete mode 100644 src/northbridge/amd/amdmct/mct/mctchi_d.c delete mode 100644 src/northbridge/amd/amdmct/mct/mctcsi_d.c delete mode 100644 src/northbridge/amd/amdmct/mct/mctdqs_d.c delete mode 100644 src/northbridge/amd/amdmct/mct/mctecc_d.c delete mode 100644 src/northbridge/amd/amdmct/mct/mctgr.c delete mode 100644 src/northbridge/amd/amdmct/mct/mcthdi.c delete mode 100644 src/northbridge/amd/amdmct/mct/mctmtr_d.c delete mode 100644 src/northbridge/amd/amdmct/mct/mctndi_d.c delete mode 100644 src/northbridge/amd/amdmct/mct/mctpro_d.c delete mode 100644 src/northbridge/amd/amdmct/mct/mctsrc.c delete mode 100644 src/northbridge/amd/amdmct/mct/mctsrc1p.c delete mode 100644 src/northbridge/amd/amdmct/mct/mctsrc2p.c delete mode 100644 src/northbridge/amd/amdmct/mct/mcttmrl.c delete mode 100644 src/northbridge/amd/amdmct/mct_ddr3/Makefile.inc delete mode 100644 src/northbridge/amd/amdmct/mct_ddr3/mct_d.c delete mode 100644 src/northbridge/amd/amdmct/mct_ddr3/mct_d.h delete mode 100644 src/northbridge/amd/amdmct/mct_ddr3/mct_d_gcc.c delete mode 100644 src/northbridge/amd/amdmct/mct_ddr3/mct_d_gcc.h delete mode 100644 src/northbridge/amd/amdmct/mct_ddr3/mctardk5.c delete mode 100644 src/northbridge/amd/amdmct/mct_ddr3/mctardk6.c delete mode 100644 src/northbridge/amd/amdmct/mct_ddr3/mctchi_d.c delete mode 100644 src/northbridge/amd/amdmct/mct_ddr3/mctcsi_d.c delete mode 100644 src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c delete mode 100644 src/northbridge/amd/amdmct/mct_ddr3/mctecc_d.c delete mode 100644 src/northbridge/amd/amdmct/mct_ddr3/mcthdi.c delete mode 100644 src/northbridge/amd/amdmct/mct_ddr3/mcthwl.c delete mode 100644 src/northbridge/amd/amdmct/mct_ddr3/mctmtr_d.c delete mode 100644 src/northbridge/amd/amdmct/mct_ddr3/mctndi_d.c delete mode 100644 src/northbridge/amd/amdmct/mct_ddr3/mctprob.c delete mode 100644 src/northbridge/amd/amdmct/mct_ddr3/mctproc.c delete mode 100644 src/northbridge/amd/amdmct/mct_ddr3/mctprod.c delete mode 100644 src/northbridge/amd/amdmct/mct_ddr3/mctrci.c delete mode 100644 src/northbridge/amd/amdmct/mct_ddr3/mctsdi.c delete mode 100644 src/northbridge/amd/amdmct/mct_ddr3/mctsrc.c delete mode 100644 src/northbridge/amd/amdmct/mct_ddr3/mctsrc1p.c delete mode 100644 src/northbridge/amd/amdmct/mct_ddr3/mctsrc2p.c delete mode 100644 src/northbridge/amd/amdmct/mct_ddr3/mcttmrl.c delete mode 100644 src/northbridge/amd/amdmct/mct_ddr3/mctwl.c delete mode 100644 src/northbridge/amd/amdmct/mct_ddr3/mhwlc_d.c delete mode 100644 src/northbridge/amd/amdmct/mct_ddr3/modtrd.c delete mode 100644 src/northbridge/amd/amdmct/mct_ddr3/modtrdim.c delete mode 100644 src/northbridge/amd/amdmct/mct_ddr3/mport_d.c delete mode 100644 src/northbridge/amd/amdmct/mct_ddr3/mutilc_d.c delete mode 100644 src/northbridge/amd/amdmct/mct_ddr3/mwlc_d.h delete mode 100644 src/northbridge/amd/amdmct/mct_ddr3/s3utils.c delete mode 100644 src/northbridge/amd/amdmct/mct_ddr3/s3utils.h delete mode 100644 src/northbridge/amd/amdmct/wrappers/Makefile.inc delete mode 100644 src/northbridge/amd/amdmct/wrappers/mcti.h delete mode 100644 src/northbridge/amd/amdmct/wrappers/mcti_d.c diff --git a/src/cpu/amd/family_10h-family_15h/fidvid.c b/src/cpu/amd/family_10h-family_15h/fidvid.c index 57207a431a..d4dec2b1c0 100644 --- a/src/cpu/amd/family_10h-family_15h/fidvid.c +++ b/src/cpu/amd/family_10h-family_15h/fidvid.c @@ -505,7 +505,7 @@ static void config_power_ctrl_misc_reg(pci_devfn_t dev, uint64_t cpuRev, } /* TODO: look into C1E state and F3xA0[IdleExitEn]*/ - #if CONFIG(SVI_HIGH_FREQ) + #if 0 if (cpuRev & AMD_FAM10_C3) { dword |= SVI_HIGH_FREQ_ON; } @@ -585,7 +585,7 @@ static void config_acpi_pwr_state_ctrl_regs(pci_devfn_t dev, uint64_t cpuRev, if (cpuRev & AMD_DR_Bx ) { smaf001 = 0xA6; } else { - #if CONFIG(SVI_HIGH_FREQ) + #if 0 if (cpuRev & (AMD_RB_C3 | AMD_DA_C3)) { smaf001 = 0xF6; } diff --git a/src/cpu/amd/family_10h-family_15h/init_cpus.c b/src/cpu/amd/family_10h-family_15h/init_cpus.c index c7ef86a5a1..ae04f2aace 100644 --- a/src/cpu/amd/family_10h-family_15h/init_cpus.c +++ b/src/cpu/amd/family_10h-family_15h/init_cpus.c @@ -576,7 +576,7 @@ static void start_node(u8 node) /* Enable routing table */ printk(BIOS_DEBUG, "Start node %02x", node); -#if CONFIG(NORTHBRIDGE_AMD_AMDFAM10) +#if 0 /* For FAM10 support, we need to set Dram base/limit for the new node */ pci_write_config32(NODE_MP(node), 0x44, 0); pci_write_config32(NODE_MP(node), 0x40, 3); diff --git a/src/device/device_const.c b/src/device/device_const.c index 27197f251c..5a3e89bfb9 100644 --- a/src/device/device_const.c +++ b/src/device/device_const.c @@ -218,13 +218,6 @@ DEVTREE_CONST struct bus *pci_root_bus(void) DEVTREE_CONST struct device *pcidev_path_on_root(pci_devfn_t devfn) { - /* Work around pcidev_path_behind() below failing - * due tue complicated devicetree with topology - * being manipulated on-the-fly. - */ - if (CONFIG(NORTHBRIDGE_AMD_AMDFAM10)) - return dev_find_slot(0, devfn); - return pcidev_path_behind(pci_root_bus(), devfn); } diff --git a/src/include/device/hypertransport_def.h b/src/include/device/hypertransport_def.h index ef9de2c3aa..a0b1a36a21 100644 --- a/src/include/device/hypertransport_def.h +++ b/src/include/device/hypertransport_def.h @@ -23,8 +23,7 @@ static inline bool offset_unit_id(bool is_sb_ht_chain) { bool need_offset = (CONFIG_HT_CHAIN_UNITID_BASE != 1) || (CONFIG_HT_CHAIN_END_UNITID_BASE != 0x20); - return need_offset && (!CONFIG(SB_HT_CHAIN_UNITID_OFFSET_ONLY) - || is_sb_ht_chain); + return need_offset && is_sb_ht_chain; } #endif /* DEVICE_HYPERTRANSPORT_DEF_H */ diff --git a/src/northbridge/amd/agesa/family14/acpi/northbridge.asl b/src/northbridge/amd/agesa/family14/acpi/northbridge.asl index e95c95a019..06199a1b07 100644 --- a/src/northbridge/amd/agesa/family14/acpi/northbridge.asl +++ b/src/northbridge/amd/agesa/family14/acpi/northbridge.asl @@ -128,5 +128,5 @@ Device(NBF3) { Name(_ADR, 0x00180003) /* k10temp thermal zone */ - #include + #include "thermal_mixin.asl" } /* end NBF3 */ diff --git a/src/northbridge/amd/amdfam10/thermal_mixin.asl b/src/northbridge/amd/agesa/family14/acpi/thermal_mixin.asl similarity index 100% rename from src/northbridge/amd/amdfam10/thermal_mixin.asl rename to src/northbridge/amd/agesa/family14/acpi/thermal_mixin.asl diff --git a/src/northbridge/amd/amdfam10/Kconfig b/src/northbridge/amd/amdfam10/Kconfig deleted file mode 100644 index 64358875f1..0000000000 --- a/src/northbridge/amd/amdfam10/Kconfig +++ /dev/null @@ -1,145 +0,0 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2015 Timothy Pearson , Raptor Engineering -## Copyright (C) 2007-2009 coresystems GmbH -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; version 2 of the License. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## - -config NORTHBRIDGE_AMD_AMDFAM10 - bool - select HAVE_DEBUG_RAM_SETUP - select HAVE_DEBUG_SMBUS - select HAVE_DEBUG_CAR - select HYPERTRANSPORT_PLUGIN_SUPPORT - select PCIEXP_ASPM - select PCIEXP_COMMON_CLOCK - select PCIEXP_CLK_PM - select PCIEXP_L1_SUB_STATE - select NO_RELOCATABLE_RAMSTAGE - -if NORTHBRIDGE_AMD_AMDFAM10 -config AGP_APERTURE_SIZE - hex - default 0x4000000 - -config HW_MEM_HOLE_SIZEK - hex - default 0x100000 - -config MMCONF_BASE_ADDRESS - hex - default 0xc0000000 - -config MMCONF_BUS_NUMBER - int - default 256 - -# TODO: Reservation for heap seems excessive -config HEAP_SIZE - hex - default 0xc0000 - -config BOOTBLOCK_NORTHBRIDGE_INIT - string - default "northbridge/amd/amdfam10/bootblock.c" - -config SB_HT_CHAIN_UNITID_OFFSET_ONLY - bool - default n - -config HT_CHAIN_DISTRIBUTE - def_bool n - -config DIMM_DDR2 - bool - default n - -config DIMM_DDR3 - bool - default n - -config DIMM_REGISTERED - bool - default n - -config DIMM_VOLTAGE_SET_SUPPORT - bool - default n - -config S3_DATA_SIZE - int - default 32768 - depends on (HAVE_ACPI_RESUME) - -config S3_DATA_POS - hex - default 0x0 - depends on (HAVE_ACPI_RESUME) - -config SVI_HIGH_FREQ - bool - default n - help - Select this for boards with a Voltage Regulator able to operate - at 3.4 MHz in SVI mode. Ignored unless the AMD CPU is rev C3. - -menu "HyperTransport setup" - #could be implemented for K8 (NORTHBRIDGE_AMD_AMDK8) - depends on (NORTHBRIDGE_AMD_AMDFAM10) - -choice - prompt "HyperTransport downlink width" - default LIMIT_HT_DOWN_WIDTH_16 - help - This option sets the maximum permissible HyperTransport - downlink width. - - Use of this option will only limit the autodetected HT width. - It will not (and cannot) increase the width beyond the autodetected - limits. - - This is primarily used to work around poorly designed or laid out HT - traces on certain motherboards. - -config LIMIT_HT_DOWN_WIDTH_8 - bool "8 bits" -config LIMIT_HT_DOWN_WIDTH_16 - bool "16 bits" -endchoice - -choice - prompt "HyperTransport uplink width" - default LIMIT_HT_UP_WIDTH_16 - help - This option sets the maximum permissible HyperTransport - uplink width. - - Use of this option will only limit the autodetected HT width. - It will not (and cannot) increase the width beyond the autodetected - limits. - - This is primarily used to work around poorly designed or laid out HT - traces on certain motherboards. - -config LIMIT_HT_UP_WIDTH_8 - bool "8 bits" -config LIMIT_HT_UP_WIDTH_16 - bool "16 bits" -endchoice - -endmenu - -config MAX_REBOOT_CNT - int - default 6 - -endif # NORTHBRIDGE_AMD_AMDFAM10 diff --git a/src/northbridge/amd/amdfam10/Makefile.inc b/src/northbridge/amd/amdfam10/Makefile.inc deleted file mode 100644 index 787f4444ce..0000000000 --- a/src/northbridge/amd/amdfam10/Makefile.inc +++ /dev/null @@ -1,34 +0,0 @@ -ifeq ($(CONFIG_NORTHBRIDGE_AMD_AMDFAM10),y) - -subdirs-y += ../amdht -subdirs-y += ../amdmct/wrappers -subdirs-$(CONFIG_DIMM_DDR3) += ../amdmct/mct_ddr3 -subdirs-$(CONFIG_DIMM_DDR2) += ../amdmct/mct - -# Generic ROMSTAGE stuff -romstage-y += reset_test.c debug.c setup_resource_map.c raminit_sysinfo_in_ram.c -romstage-y += raminit_amdmct.c pci.c early_ht.c amdfam10_util.c - -# RAMSTAGE -ramstage-y += northbridge.c misc_control.c link_control.c nb_control.c -ramstage-y += amdfam10_util.c ht_config.c get_pci1234.c -ramstage-$(CONFIG_HAVE_ACPI_TABLES) += acpi.c - -# Enable this if you want to check the values of the PCI routing registers. -# Call show_all_routes() anywhere amdfam10.h is included. -#ramstage-y += util.c - -# Reserve 2x CONFIG_S3_DATA_SIZE to allow for random file placement -# (not respecting erase sector boundaries) within CBFS -$(obj)/coreboot_s3nv.rom: $(obj)/config.h - echo " S3 NVRAM $(CONFIG_S3_DATA_POS) (S3 storage area)" - # force C locale, so cygwin awk doesn't try to interpret the 0xff below as UTF-8 (or worse) - printf %d $(CONFIG_S3_DATA_SIZE) | LC_ALL=C awk '{for (i=0; i<$$1*2; i++) {printf "%c", 255}}' > $@.tmp - mv $@.tmp $@ - -cbfs-files-$(CONFIG_HAVE_ACPI_RESUME) += s3nv -s3nv-file := $(obj)/coreboot_s3nv.rom -s3nv-align := $(CONFIG_S3_DATA_SIZE) -s3nv-type := raw - -endif diff --git a/src/northbridge/amd/amdfam10/acpi.c b/src/northbridge/amd/amdfam10/acpi.c deleted file mode 100644 index dc139adb87..0000000000 --- a/src/northbridge/amd/amdfam10/acpi.c +++ /dev/null @@ -1,351 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2015 Timothy Pearson , Raptor Engineering - * Copyright (C) 2007 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include "amdfam10.h" - -//it seems some functions can be moved arch/x86/boot/acpi.c - -unsigned long acpi_create_madt_lapic_nmis(unsigned long current, u16 flags, u8 lint) -{ - struct device *cpu; - int cpu_index = 0; - - for (cpu = all_devices; cpu; cpu = cpu->next) { - if ((cpu->path.type != DEVICE_PATH_APIC) || - (cpu->bus->dev->path.type != DEVICE_PATH_CPU_CLUSTER)) { - continue; - } - if (!cpu->enabled) { - continue; - } - current += acpi_create_madt_lapic_nmi((acpi_madt_lapic_nmi_t *)current, cpu_index, flags, lint); - cpu_index++; - } - return current; -} - -unsigned long acpi_create_srat_lapics(unsigned long current) -{ - struct device *cpu; - int cpu_index = 0; - - for (cpu = all_devices; cpu; cpu = cpu->next) { - if ((cpu->path.type != DEVICE_PATH_APIC) || - (cpu->bus->dev->path.type != DEVICE_PATH_CPU_CLUSTER)) { - continue; - } - if (!cpu->enabled) { - continue; - } - printk(BIOS_DEBUG, "SRAT: lapic cpu_index=%02x, node_id=%02x, apic_id=%02x\n", cpu_index, cpu->path.apic.node_id, cpu->path.apic.apic_id); - current += acpi_create_srat_lapic((acpi_srat_lapic_t *)current, cpu->path.apic.node_id, cpu->path.apic.apic_id); - cpu_index++; - } - return current; -} - -static unsigned long resk(uint64_t value) -{ - unsigned long resultk; - if (value < (1ULL << 42)) { - resultk = value >> 10; - } else { - resultk = 0xffffffff; - } - return resultk; -} - -struct acpi_srat_mem_state { - unsigned long current; -}; - -static void set_srat_mem(void *gp, struct device *dev, struct resource *res) -{ - struct acpi_srat_mem_state *state = gp; - unsigned long basek, sizek; - basek = resk(res->base); - sizek = resk(res->size); - - printk(BIOS_DEBUG, "set_srat_mem: dev %s, res->index=%04lx startk=%08lx, sizek=%08lx\n", - dev_path(dev), res->index, basek, sizek); - /* - * 0-640K must be on node 0 - * next range is from 1M--- - * So will cut off before 1M in the mem range - */ - if ((basek+sizek)<1024) return; - - if (basek < 1024) { - sizek -= 1024 - basek; - basek = 1024; - } - - // need to figure out NV - if (res->index > 0xf) /* Exclude MMIO resources, e.g. as set in northbridge.c amdfam10_domain_read_resources() */ - state->current += acpi_create_srat_mem((acpi_srat_mem_t *)state->current, (res->index & 0xf), basek, sizek, 1); -} - -static unsigned long acpi_fill_srat(unsigned long current) -{ - struct acpi_srat_mem_state srat_mem_state; - - /* create all subtables for processors */ - current = acpi_create_srat_lapics(current); - - /* create all subteble for memory range */ - - /* 0-640K must be on node 0 */ - current += acpi_create_srat_mem((acpi_srat_mem_t *)current, 0, 0, 640, 1);//enable - - srat_mem_state.current = current; - search_global_resources( - IORESOURCE_MEM | IORESOURCE_CACHEABLE, IORESOURCE_MEM | IORESOURCE_CACHEABLE, - set_srat_mem, &srat_mem_state); - - current = srat_mem_state.current; - return current; -} - -static unsigned long acpi_fill_slit(unsigned long current) -{ - /* Implement SLIT algorithm in BKDG Rev. 3.62 Section 2.3.6.1 - * Fill the first 8 bytes with the node number, - * then fill the next num*num byte with the distance, - * Distance entries vary with topology; the local node - * is always 10. - * - * Fully connected: - * Set all non-local nodes to 16 - * - * Partially connected; with probe filter: - * Set all non-local nodes to 10+(num_hops*6) - * - * Partially connected; without probe filter: - * Set all non-local nodes to 13 - * - * FIXME - * The partially connected cases are not implemented; - * once a means is found to detect partially connected - * topologies, implement the remaining cases. - */ - - u8 *p = (u8 *)current; - int nodes = sysconf.nodes; - int i,j; - - memset(p, 0, 8+nodes*nodes); - *p = (u8) nodes; - p += 8; - - for (i = 0; i < nodes; i++) { - for (j = 0; j < nodes; j++) { - if (i == j) - p[i*nodes+j] = 10; - else - p[i*nodes+j] = 16; - } - } - - current += 8+nodes*nodes; - return current; -} - -void update_ssdtx(void *ssdtx, int i) -{ - u8 *PCI; - u8 *HCIN; - u8 *UID; - - PCI = ssdtx + 0x32; - HCIN = ssdtx + 0x39; - UID = ssdtx + 0x40; - - if (i < 7) { - *PCI = (u8) ('4' + i - 1); - } else { - *PCI = (u8) ('A' + i - 1 - 6); - } - *HCIN = (u8) i; - *UID = (u8) (i + 3); - - /* FIXME: need to update the GSI id in the ssdtx too */ - -} - -void northbridge_acpi_write_vars(struct device *device) -{ - /* - * If more than one physical CPU is installed, northbridge_acpi_write_vars() - * is called more than once and the resultant SSDT table is corrupted - * (duplicated entries). - * This prevents Linux from booting, with log messages like these: - * ACPI Error: [BUSN] Namespace lookup failure, AE_ALREADY_EXISTS (/dswload-353) - * ACPI Exception: AE_ALREADY_EXISTS, During name lookup/catalog (/psobject-222) - * followed by a slew of ACPI method failures and a hang when the invalid PCI - * resource entries are used. - * This routine prevents the SSDT table from being corrupted. - */ - static uint8_t ssdt_generated = 0; - if (ssdt_generated) - return; - ssdt_generated = 1; - - msr_t msr; - char pscope[] = "\\_SB.PCI0"; - int i; - - acpigen_write_scope(pscope); - - acpigen_write_name("BUSN"); - acpigen_write_package(HC_NUMS); - for (i = 0; i < HC_NUMS; i++) { - acpigen_write_dword(sysconf.ht_c_conf_bus[i]); - } - // minus the opcode - acpigen_pop_len(); - - acpigen_write_name("MMIO"); - - acpigen_write_package(HC_NUMS * 4); - - for (i = 0; i<(HC_NUMS*2); i++) { // FIXME: change to more chain - acpigen_write_dword(sysconf.conf_mmio_addrx[i]); //base - acpigen_write_dword(sysconf.conf_mmio_addr[i]); //mask - } - // minus the opcode - acpigen_pop_len(); - - acpigen_write_name("PCIO"); - - acpigen_write_package(HC_NUMS * 2); - - for (i = 0; i < HC_NUMS; i++) { // FIXME: change to more chain - acpigen_write_dword(sysconf.conf_io_addrx[i]); - acpigen_write_dword(sysconf.conf_io_addr[i]); - } - - // minus the opcode - acpigen_pop_len(); - - acpigen_write_name_byte("SBLK", sysconf.sblk); - - msr = rdmsr(TOP_MEM); - acpigen_write_name_dword("TOM1", msr.lo); - - msr = rdmsr(TOP_MEM2); - /* - * Since XP only implements parts of ACPI 2.0, we can't use a qword - * here. - * See http://www.acpi.info/presentations/S01USMOBS169_OS%2520new.ppt - * slide 22ff. - * Shift value right by 20 bit to make it fit into 32bit, - * giving us 1MB granularity and a limit of almost 4Exabyte of memory. - */ - acpigen_write_name_dword("TOM2", (msr.hi << 12) | msr.lo >> 20); - - - acpigen_write_name_dword("SBDN", sysconf.sbdn); - - acpigen_write_name("HCLK"); - - acpigen_write_package(HC_POSSIBLE_NUM); - - for (i = 0; i < sysconf.hc_possible_num; i++) { - acpigen_write_dword(sysconf.pci1234[i]); - } - for (i = sysconf.hc_possible_num; i < HC_POSSIBLE_NUM; i++) { // in case we set array size to other than 8 - acpigen_write_dword(0x00000000); - } - // minus the opcode - acpigen_pop_len(); - - acpigen_write_name("HCDN"); - - acpigen_write_package(HC_POSSIBLE_NUM); - - for (i = 0; i < sysconf.hc_possible_num; i++) { - acpigen_write_dword(sysconf.hcdn[i]); - } - for (i = sysconf.hc_possible_num; i < HC_POSSIBLE_NUM; i++) { // in case we set array size to other than 8 - acpigen_write_dword(0x20202020); - } - // minus the opcode - acpigen_pop_len(); - - acpigen_write_name_byte("CBB", CONFIG_CBB); - - u8 CBST, CBB2, CBS2; - - if (CONFIG_CBB == 0xff) { - CBST = (u8) (0x0f); - } else { - if ((sysconf.pci1234[0] >> 12) & 0xff) { //sb chain on other than bus 0 - CBST = (u8) (0x0f); - } else { - CBST = (u8) (0x00); - } - } - - acpigen_write_name_byte("CBST", CBST); - - if ((CONFIG_CBB == 0xff) && (sysconf.nodes > 32)) { - CBS2 = 0x0f; - CBB2 = (u8)(CONFIG_CBB-1); - } else { - CBS2 = 0x00; - CBB2 = 0x00; - } - - acpigen_write_name_byte("CBB2", CBB2); - acpigen_write_name_byte("CBS2", CBS2); - - //minus opcode - acpigen_pop_len(); -} - -unsigned long northbridge_write_acpi_tables(struct device *device, - unsigned long current, - struct acpi_rsdp *rsdp) -{ - acpi_srat_t *srat; - acpi_slit_t *slit; - - /* SRAT */ - current = ALIGN(current, 8); - printk(BIOS_DEBUG, "ACPI: * SRAT at %lx\n", current); - srat = (acpi_srat_t *) current; - acpi_create_srat(srat, acpi_fill_srat); - current += srat->header.length; - acpi_add_table(rsdp, srat); - - /* SLIT */ - current = ALIGN(current, 8); - printk(BIOS_DEBUG, "ACPI: * SLIT at %lx\n", current); - slit = (acpi_slit_t *) current; - acpi_create_slit(slit, acpi_fill_slit); - current += slit->header.length; - acpi_add_table(rsdp, slit); - - return current; -} diff --git a/src/northbridge/amd/amdfam10/amdfam10.h b/src/northbridge/amd/amdfam10/amdfam10.h deleted file mode 100644 index ad8d01365d..0000000000 --- a/src/northbridge/amd/amdfam10/amdfam10.h +++ /dev/null @@ -1,1025 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2015 Timothy Pearson , Raptor Engineering - * Copyright (C) 2007 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef AMDFAM10_H -#define AMDFAM10_H - -#include -#include -#include "early_ht.h" - -#include "inline_helper.c" -struct DCTStatStruc; -struct MCTStatStruc; - - -/* Definitions for setup_resourcemap() variants. */ - -#define PCI_ADDR(SEGBUS, DEV, FN, WHERE) ( \ - (((SEGBUS) & 0xFFF) << 20) | \ - (((DEV) & 0x1F) << 15) | \ - (((FN) & 0x07) << 12) | \ - ((WHERE) & 0xFFF)) - -#define ADDRMAP_REG(r) PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, r) - -#define RES_PCI_IO 0x10 -#define RES_PORT_IO_8 0x22 -#define RES_PORT_IO_32 0x20 -#define RES_MEM_IO 0x40 - -#define NODE_ID 0x60 -#define HT_INIT_CONTROL 0x6c -#define HTIC_ColdR_Detect (1<<4) -#define HTIC_BIOSR_Detect (1<<5) -#define HTIC_INIT_Detect (1<<6) - -/* Definitions of various FAM10 registers */ -/* Function 0 */ -#define HT_TRANSACTION_CONTROL 0x68 -#define HTTC_DIS_RD_B_P (1 << 0) -#define HTTC_DIS_RD_DW_P (1 << 1) -#define HTTC_DIS_WR_B_P (1 << 2) -#define HTTC_DIS_WR_DW_P (1 << 3) -#define HTTC_DIS_MTS (1 << 4) -#define HTTC_CPU1_EN (1 << 5) -#define HTTC_CPU_REQ_PASS_PW (1 << 6) -#define HTTC_CPU_RD_RSP_PASS_PW (1 << 7) -#define HTTC_DIS_P_MEM_C (1 << 8) -#define HTTC_DIS_RMT_MEM_C (1 << 9) -#define HTTC_DIS_FILL_P (1 << 10) -#define HTTC_RSP_PASS_PW (1 << 11) -#define HTTC_BUF_REL_PRI_SHIFT 13 -#define HTTC_BUF_REL_PRI_MASK 3 -#define HTTC_BUF_REL_PRI_64 0 -#define HTTC_BUF_REL_PRI_16 1 -#define HTTC_BUF_REL_PRI_8 2 -#define HTTC_BUF_REL_PRI_2 3 -#define HTTC_LIMIT_CLDT_CFG (1 << 15) -#define HTTC_LINT_EN (1 << 16) -#define HTTC_APIC_EXT_BRD_CST (1 << 17) -#define HTTC_APIC_EXT_ID (1 << 18) -#define HTTC_APIC_EXT_SPUR (1 << 19) -#define HTTC_SEQ_ID_SRC_NODE_EN (1 << 20) -#define HTTC_DS_NP_REQ_LIMIT_SHIFT 21 -#define HTTC_DS_NP_REQ_LIMIT_MASK 3 -#define HTTC_DS_NP_REQ_LIMIT_NONE 0 -#define HTTC_DS_NP_REQ_LIMIT_1 1 -#define HTTC_DS_NP_REQ_LIMIT_4 2 -#define HTTC_DS_NP_REQ_LIMIT_8 3 - - -/* Function 1 */ -#define PCI_IO_BASE0 0xc0 -#define PCI_IO_BASE1 0xc8 -#define PCI_IO_BASE2 0xd0 -#define PCI_IO_BASE3 0xd8 -#define PCI_IO_BASE_VGA_EN (1 << 4) -#define PCI_IO_BASE_NO_ISA (1 << 5) - -/* Function 2 */ -// 0x1xx is for DCT1 -#define DRAM_CSBASE 0x40 -#define DRAM_CSMASK 0x60 -#define DRAM_BANK_ADDR_MAP 0x80 - -#define DRAM_CTRL 0x78 -#define DC_RdPtrInit_SHIFT 0 -#define DC_RdPrtInit_MASK 0xf -#define DC_Twrrd3_2_SHIFT 8 /*DDR3 */ -#define DC_Twrrd3_2_MASK 3 -#define DC_Twrwr3_2_SHIFT 10 /*DDR3 */ -#define DC_Twrwr3_2_MASK 3 -#define DC_Trdrd3_2_SHIFT 12 /*DDR3 */ -#define DC_Trdrd3_2_MASK 3 -#define DC_AltVidC3MemClkTriEn (1<<16) -#define DC_DqsRcvEnTrain (1<<18) -#define DC_MaxRdLatency_SHIFT 22 -#define DC_MaxRdLatency_MASK 0x3ff - -#define DRAM_INIT 0x7c -#define DI_MrsAddress_SHIFT 0 -#define DI_MrsAddress_MASK 0xffff -#define DI_MrsBank_SHIFT 16 -#define DI_MrsBank_MASK 7 -#define DI_MrsChipSel_SHIFT 20 -#define DI_MrsChipSel_MASK 7 -#define DI_SendRchgAll (1<<24) -#define DI_SendAutoRefresh (1<<25) -#define DI_SendMrsCmd (1<<26) -#define DI_DeassertMemRstX (1<<27) -#define DI_AssertCke (1<<28) -#define DI_SendZQCmd (1<<29) /*DDR3 */ -#define DI_EnMrsCmd (1<<30) -#define DI_EnDramInit (1<<31) - -#define DRAM_MRS 0x84 -#define DM_BurstCtrl_SHIFT 0 -#define DM_BurstCtrl_MASK 3 -#define DM_DrvImpCtrl_SHIFT 2 /* DDR3 */ -#define DM_DrvImpCtrl_MASK 3 -#define DM_Twr_SHIFT 4 /* DDR3 */ -#define DM_Twr_MASK 7 -#define DM_Twr_BASE 4 -#define DM_Twr_MIN 5 -#define DM_Twr_MAX 12 -#define DM_DramTerm_SHIFT 7 /*DDR3 */ -#define DM_DramTerm_MASK 7 -#define DM_DramTermDyn_SHIFT 10 /* DDR3 */ -#define DM_DramTermDyn_MASK 3 -#define DM_Ooff (1<<13) -#define DM_ASR (1<<18) -#define DM_SRT (1<<19) -#define DM_Tcwl_SHIFT 20 -#define DM_Tcwl_MASK 7 -#define DM_PchgPDModeSel (1<<23) /* DDR3 */ -#define DM_MPrLoc_SHIFT 24 /* DDR3 */ -#define DM_MPrLoc_MASK 3 -#define DM_MprEn (1<<26) /* DDR3 */ - -#define DRAM_TIMING_LOW 0x88 -#define DTL_TCL_SHIFT 0 -#define DTL_TCL_MASK 0xf -#define DTL_TCL_BASE 1 /* DDR3 =4 */ -#define DTL_TCL_MIN 3 /* DDR3 =4 */ -#define DTL_TCL_MAX 6 /* DDR3 =12 */ -#define DTL_TRCD_SHIFT 4 -#define DTL_TRCD_MASK 3 /* DDR3 =7 */ -#define DTL_TRCD_BASE 3 /* DDR3 =5 */ -#define DTL_TRCD_MIN 3 /* DDR3 =5 */ -#define DTL_TRCD_MAX 6 /* DDR3 =12 */ -#define DTL_TRP_SHIFT 8 /* DDR3 =7 */ -#define DTL_TRP_MASK 3 /* DDR3 =7 */ -#define DTL_TRP_BASE 3 /* DDR3 =5 */ -#define DTL_TRP_MIN 3 /* DDR3 =5 */ -#define DTL_TRP_MAX 6 /* DDR3 =12 */ -#define DTL_TRTP_SHIFT 11 /*DDR3 =10 */ -#define DTL_TRTP_MASK 1 /*DDR3 =3 */ -#define DTL_TRTP_BASE 2 /* DDR3 =4 */ -#define DTL_TRTP_MIN 2 /* 4 for 64 bytes*/ /* DDR3 =4 for 32bytes or 64bytes */ -#define DTL_TRTP_MAX 3 /* 5 for 64 bytes */ /* DDR3 =7 for 32Bytes or 64bytes */ -#define DTL_TRAS_SHIFT 12 -#define DTL_TRAS_MASK 0xf -#define DTL_TRAS_BASE 3 /* DDR3 =15 */ -#define DTL_TRAS_MIN 5 /* DDR3 =15 */ -#define DTL_TRAS_MAX 18 /*DDR3 =30 */ -#define DTL_TRC_SHIFT 16 -#define DTL_TRC_MASK 0xf /* DDR3 =0x1f */ -#define DTL_TRC_BASE 11 -#define DTL_TRC_MIN 11 -#define DTL_TRC_MAX 26 /* DDR3 =43 */ -#define DTL_TWR_SHIFT 20 /* only for DDR2, DDR3's is on DC */ -#define DTL_TWR_MASK 3 -#define DTL_TWR_BASE 3 -#define DTL_TWR_MIN 3 -#define DTL_TWR_MAX 6 -#define DTL_TRRD_SHIFT 22 -#define DTL_TRRD_MASK 3 -#define DTL_TRRD_BASE 2 /* DDR3 =4 */ -#define DTL_TRRD_MIN 2 /* DDR3 =4 */ -#define DTL_TRRD_MAX 5 /* DDR3 =7 */ -#define DTL_MemClkDis_SHIFT 24 /* Channel A */ -#define DTL_MemClkDis3 (1 << 26) -#define DTL_MemClkDis2 (1 << 27) -#define DTL_MemClkDis1 (1 << 28) -#define DTL_MemClkDis0 (1 << 29) -/* DTL_MemClkDis for m2 and s1g1 is different */ - -#define DRAM_TIMING_HIGH 0x8c -#define DTH_TRWTWB_SHIFT 0 -#define DTH_TRWTWB_MASK 3 -#define DTH_TRWTWB_BASE 3 /* DDR3 =4 */ -#define DTH_TRWTWB_MIN 3 /* DDR3 =5 */ -#define DTH_TRWTWB_MAX 10 /* DDR3 =11 */ -#define DTH_TRWTTO_SHIFT 4 -#define DTH_TRWTTO_MASK 7 -#define DTH_TRWTTO_BASE 2 /* DDR3 =3 */ -#define DTH_TRWTTO_MIN 2 /* DDR3 =3 */ -#define DTH_TRWTTO_MAX 9 /* DDR3 =10 */ -#define DTH_TWTR_SHIFT 8 -#define DTH_TWTR_MASK 3 -#define DTH_TWTR_BASE 0 /* DDR3 =4 */ -#define DTH_TWTR_MIN 1 /* DDR3 =4 */ -#define DTH_TWTR_MAX 3 /* DDR3 =7 */ -#define DTH_TWRRD_SHIFT 10 -#define DTH_TWRRD_MASK 3 /* For DDR3 3_2 is at 0x78 DC */ -#define DTH_TWRRD_BASE 0 /* DDR3 =0 */ -#define DTH_TWRRD_MIN 0 /* DDR3 =2 */ -#define DTH_TWRRD_MAX 3 /* DDR3 =12 */ -#define DTH_TWRWR_SHIFT 12 -#define DTH_TWRWR_MASK 3 /* For DDR3 3_2 is at 0x78 DC */ -#define DTH_TWRWR_BASE 1 -#define DTH_TWRWR_MIN 1 /* DDR3 =3 */ -#define DTH_TWRWR_MAX 3 /* DDR3 =12 */ -#define DTH_TRDRD_SHIFT 14 -#define DTH_TRDRD_MASK 3 /* For DDR3 3_2 is at 0x78 DC */ -#define DTH_TRDRD_BASE 2 -#define DTH_TRDRD_MIN 2 -#define DTH_TRDRD_MAX 5 /* DDR3 =10 */ -#define DTH_TREF_SHIFT 16 -#define DTH_TREF_MASK 3 -#define DTH_TREF_7_8_US 2 -#define DTH_TREF_3_9_US 3 -#define DTH_DisAutoRefresh (1<<18) -#define DTH_TRFC0_SHIFT 20 /* for Logical DIMM0 */ -#define DTH_TRFC_MASK 7 -#define DTH_TRFC_75_256M 0 -#define DTH_TRFC_105_512M 1 -#define DTH_TRFC_127_5_1G 2 -#define DTH_TRFC_195_2G 3 -#define DTH_TRFC_327_5_4G 4 -#define DTH_TRFC1_SHIFT 23 /*for Logical DIMM1 */ -#define DTH_TRFC2_SHIFT 26 /*for Logical DIMM2 */ -#define DTH_TRFC3_SHIFT 29 /*for Logical DIMM3 */ - -#define DRAM_CONFIG_LOW 0x90 -#define DCL_InitDram (1<<0) -#define DCL_ExitSelfRef (1<<1) -#define DCL_PllLockTime_SHIFT 2 -#define DCL_PllLockTime_MASK 3 -#define DCL_PllLockTime_15US 0 -#define DCL_PllLockTime_6US 1 -#define DCL_DramTerm_SHIFT 4 -#define DCL_DramTerm_MASK 3 -#define DCL_DramTerm_No 0 -#define DCL_DramTerm_75_OH 1 -#define DCL_DramTerm_150_OH 2 -#define DCL_DramTerm_50_OH 3 -#define DCL_DisDqsBar (1<<6) /* only for DDR2 */ -#define DCL_DramDrvWeak (1<<7) /* only for DDR2 */ -#define DCL_ParEn (1<<8) -#define DCL_SelfRefRateEn (1<<9) /* only for DDR2 */ -#define DCL_BurstLength32 (1<<10) /* only for DDR3 */ -#define DCL_Width128 (1<<11) -#define DCL_X4Dimm_SHIFT 12 -#define DCL_X4Dimm_MASK 0xf -#define DCL_UnBuffDimm (1<<16) -#define DCL_EnPhyDqsRcvEnTr (1<<18) -#define DCL_DimmEccEn (1<<19) -#define DCL_DynPageCloseEn (1<<20) -#define DCL_IdleCycInit_SHIFT 21 -#define DCL_IdleCycInit_MASK 3 -#define DCL_IdleCycInit_16CLK 0 -#define DCL_IdleCycInit_32CLK 1 -#define DCL_IdleCycInit_64CLK 2 -#define DCL_IdleCycInit_96CLK 3 -#define DCL_ForceAutoPchg (1<<23) - -#define DRAM_CONFIG_HIGH 0x94 -#define DCH_MemClkFreq_SHIFT 0 -#define DCH_MemClkFreq_MASK 7 -#define DCH_MemClkFreq_200MHz 0 /* DDR2 */ -#define DCH_MemClkFreq_266MHz 1 /* DDR2 */ -#define DCH_MemClkFreq_333MHz 2 /* DDR2 */ -#define DCH_MemClkFreq_400MHz 3 /* DDR2 and DDR 3*/ -#define DCH_MemClkFreq_533MHz 4 /* DDR 3 */ -#define DCH_MemClkFreq_667MHz 5 /* DDR 3 */ -#define DCH_MemClkFreq_800MHz 6 /* DDR 3 */ -#define DCH_MemClkFreqVal (1<<3) -#define DCH_Ddr3Mode (1<<8) -#define DCH_LegacyBiosMode (1<<9) -#define DCH_ZqcsInterval_SHIFT 10 -#define DCH_ZqcsInterval_MASK 3 -#define DCH_ZqcsInterval_DIS 0 -#define DCH_ZqcsInterval_64MS 1 -#define DCH_ZqcsInterval_128MS 2 -#define DCH_ZqcsInterval_256MS 3 -#define DCH_RDqsEn (1<<12) /* only for DDR2 */ -#define DCH_DisSimulRdWr (1<<13) -#define DCH_DisDramInterface (1<<14) -#define DCH_PowerDownEn (1<<15) -#define DCH_PowerDownMode_SHIFT 16 -#define DCH_PowerDownMode_MASK 1 -#define DCH_PowerDownMode_Channel_CKE 0 -#define DCH_PowerDownMode_ChipSelect_CKE 1 -#define DCH_FourRankSODimm (1<<17) -#define DCH_FourRankRDimm (1<<18) -#define DCH_SlowAccessMode (1<<20) -#define DCH_BankSwizzleMode (1<<22) -#define DCH_DcqBypassMax_SHIFT 24 -#define DCH_DcqBypassMax_MASK 0xf -#define DCH_DcqBypassMax_BASE 0 -#define DCH_DcqBypassMax_MIN 0 -#define DCH_DcqBypassMax_MAX 15 -#define DCH_FourActWindow_SHIFT 28 -#define DCH_FourActWindow_MASK 0xf -#define DCH_FourActWindow_BASE 7 /* DDR3 15 */ -#define DCH_FourActWindow_MIN 8 /* DDR3 16 */ -#define DCH_FourActWindow_MAX 20 /* DDR3 30 */ - - -// for 0x98 index and 0x9c data for DCT0 -// for 0x198 index and 0x19c data for DCT1 -// even at ganged mode, 0x198/0x19c will be used for channel B - -#define DRAM_CTRL_ADDI_DATA_OFFSET 0x98 -#define DCAO_DctOffset_SHIFT 0 -#define DCAO_DctOffset_MASK 0x3fffffff -#define DCAO_DctAccessWrite (1<<30) -#define DCAO_DctAccessDone (1<<31) - -#define DRAM_CTRL_ADDI_DATA_PORT 0x9c - -#define DRAM_OUTPUT_DRV_COMP_CTRL 0x00 -#define DODCC_CkeDrvStren_SHIFT 0 -#define DODCC_CkeDrvStren_MASK 3 -#define DODCC_CkeDrvStren_1_0X 0 -#define DODCC_CkeDrvStren_1_25X 1 -#define DODCC_CkeDrvStren_1_5X 2 -#define DODCC_CkeDrvStren_2_0X 3 -#define DODCC_CsOdtDrvStren_SHIFT 4 -#define DODCC_CsOdtDrvStren_MASK 3 -#define DODCC_CsOdtDrvStren_1_0X 0 -#define DODCC_CsOdtDrvStren_1_25X 1 -#define DODCC_CsOdtDrvStren_1_5X 2 -#define DODCC_CsOdtDrvStren_2_0X 3 -#define DODCC_AddrCmdDrvStren_SHIFT 8 -#define DODCC_AddrCmdDrvStren_MASK 3 -#define DODCC_AddrCmdDrvStren_1_0X 0 -#define DODCC_AddrCmdDrvStren_1_25X 1 -#define DODCC_AddrCmdDrvStren_1_5X 2 -#define DODCC_AddrCmdDrvStren_2_0X 3 -#define DODCC_ClkDrvStren_SHIFT 12 -#define DODCC_ClkDrvStren_MASK 3 -#define DODCC_ClkDrvStren_0_75X 0 -#define DODCC_ClkDrvStren_1_0X 1 -#define DODCC_ClkDrvStren_1_25X 2 -#define DODCC_ClkDrvStren_1_5X 3 -#define DODCC_DataDrvStren_SHIFT 16 -#define DODCC_DataDrvStren_MASK 3 -#define DODCC_DataDrvStren_0_75X 0 -#define DODCC_DataDrvStren_1_0X 1 -#define DODCC_DataDrvStren_1_25X 2 -#define DODCC_DataDrvStren_1_5X 3 -#define DODCC_DqsDrvStren_SHIFT 20 -#define DODCC_DqsDrvStren_MASK 3 -#define DODCC_DqsDrvStren_0_75X 0 -#define DODCC_DqsDrvStren_1_0X 1 -#define DODCC_DqsDrvStren_1_25X 2 -#define DODCC_DqsDrvStren_1_5X 3 -#define DODCC_ProcOdt_SHIFT 28 -#define DODCC_ProcOdt_MASK 3 -#define DODCC_ProcOdt_300_OHMS 0 -#define DODCC_ProcOdt_150_OHMS 1 -#define DODCC_ProcOdt_75_OHMS 2 - -/* - for DDR2 400, 533, 667, F2x[1,0]9C_x[02:01], [03], [06:05], [07] control timing of all DIMMs - for DDR2 800, DDR3 800, 1067, 1333, 1600, F2x[1,0]9C_x[02:01], [03], [06:05], [07] control timing of DIMM0 - F2x[1,0]9C_x[102:101], [103], [106:105], [107] control timing of DIMM1 - So Socket F with Four Logical DIMM will only support DDR2 800 ? -*/ -/* there are index +100 ===> for DIMM1 -that are corresponding to 0x01, 0x02, 0x03, 0x05, 0x06, 0x07 -*/ -//02/15/2006 18:37 -#define DRAM_WRITE_DATA_TIMING_CTRL_LOW 0x01 -#define DWDTC_WrDatFineDlyByte0_SHIFT 0 -#define DWDTC_WrDatFineDlyByte_MASK 0x1f -#define DWDTC_WrDatFineDlyByte_BASE 0 -#define DWDTC_WrDatFineDlyByte_MIN 0 -#define DWDTC_WrDatFineDlyByte_MAX 31 // 1/64 MEMCLK -#define DWDTC_WrDatGrossDlyByte0_SHIFT 5 -#define DWDTC_WrDatGrossDlyByte_MASK 0x3 -#define DWDTC_WrDatGrossDlyByte_NO_DELAY 0 -#define DWDTC_WrDatGrossDlyByte_0_5_ 1 -#define DWDTC_WrDatGrossDlyByte_1 2 -#define DWDTC_WrDatFineDlyByte1_SHIFT 8 -#define DWDTC_WrDatGrossDlyByte1_SHIFT 13 -#define DWDTC_WrDatFineDlyByte2_SHIFT 16 -#define DWDTC_WrDatGrossDlyByte2_SHIFT 21 -#define DWDTC_WrDatFineDlyByte3_SHIFT 24 -#define DWDTC_WrDatGrossDlyByte3_SHIFT 29 - -#define DRAM_WRITE_DATA_TIMING_CTRL_HIGH 0x02 -#define DWDTC_WrDatFineDlyByte4_SHIFT 0 -#define DWDTC_WrDatGrossDlyByte4_SHIFT 5 -#define DWDTC_WrDatFineDlyByte5_SHIFT 8 -#define DWDTC_WrDatGrossDlyByte5_SHIFT 13 -#define DWDTC_WrDatFineDlyByte6_SHIFT 16 -#define DWDTC_WrDatGrossDlyByte6_SHIFT 21 -#define DWDTC_WrDatFineDlyByte7_SHIFT 24 -#define DWDTC_WrDatGrossDlyByte7_SHIFT 29 - -#define DRAM_WRITE_ECC_TIMING_CTRL 0x03 -#define DWETC_WrChkFinDly_SHIFT 0 -#define DWETC_WrChkGrossDly_SHIFT 5 - -#define DRAM_ADDR_CMD_TIMING_CTRL 0x04 -#define DACTC_CkeFineDelay_SHIFT 0 -#define DACTC_CkeFineDelay_MASK 0x1f -#define DACTC_CkeFineDelay_BASE 0 -#define DACTC_CkeFineDelay_MIN 0 -#define DACTC_CkeFineDelay_MAX 31 -#define DACTC_CkeSetup (1<<5) -#define DACTC_CsOdtFineDelay_SHIFT 8 -#define DACTC_CsOdtFineDelay_MASK 0x1f -#define DACTC_CsOdtFineDelay_BASE 0 -#define DACTC_CsOdtFineDelay_MIN 0 -#define DACTC_CsOdtFineDelay_MAX 31 -#define DACTC_CsOdtSetup (1<<13) -#define DACTC_AddrCmdFineDelay_SHIFT 16 -#define DACTC_AddrCmdFineDelay_MASK 0x1f -#define DACTC_AddrCmdFineDelay_BASE 0 -#define DACTC_AddrCmdFineDelay_MIN 0 -#define DACTC_AddrCmdFineDelay_MAX 31 -#define DACTC_AddrCmdSetup (1<<21) - -#define DRAM_READ_DQS_TIMING_CTRL_LOW 0x05 -#define DRDTC_RdDqsTimeByte0_SHIFT 0 -#define DRDTC_RdDqsTimeByte_MASK 0x3f -#define DRDTC_RdDqsTimeByte_BASE 0 -#define DRDTC_RdDqsTimeByte_MIN 0 -#define DRDTC_RdDqsTimeByte_MAX 63 // 1/128 MEMCLK -#define DRDTC_RdDqsTimeByte1_SHIFT 8 -#define DRDTC_RdDqsTimeByte2_SHIFT 16 -#define DRDTC_RdDqsTimeByte3_SHIFT 24 - -#define DRAM_READ_DQS_TIMING_CTRL_HIGH 0x06 -#define DRDTC_RdDqsTimeByte4_SHIFT 0 -#define DRDTC_RdDqsTimeByte5_SHIFT 8 -#define DRDTC_RdDqsTimeByte6_SHIFT 16 -#define DRDTC_RdDqsTimeByte7_SHIFT 24 - -#define DRAM_READ_DQS_ECC_TIMING_CTRL 0x07 -#define DRDETC_RdDqsTimeCheck_SHIFT 0 - -#define DRAM_PHY_CTRL 0x08 -#define DPC_WrtLvTrEn (1<<0) -#define DPC_WrtLvTrMode (1<<1) -#define DPC_TrNibbleSel (1<<2) -#define DPC_TrDimmSel_SHIFT 4 -#define DPC_TrDimmSel_MASK 3 /* 0-->dimm0, 1-->dimm1, 2--->dimm2, 3--->dimm3 */ -#define DPC_WrLvOdt_SHIFT 8 -#define DPC_WrLvOdt_MASK 0xf /* bit 0-->odt 0, ...*/ -#define DPC_WrLvODtEn (1<<12) -#define DPC_DqsRcvTrEn (1<<13) -#define DPC_DisAutoComp (1<<30) -#define DPC_AsyncCompUpdate (1<<31) - -#define DRAM_DQS_RECV_ENABLE_TIME_CTRL_0_0 0x10 //DIMM0 Channel A -#define DDRETC_DqsRcvEnFineDelayByte0_SHIFT 0 -#define DDRETC_DqsRcvEnFineDelayByte0_MASK 0x1f -#define DDRETC_DqsRcvEnGrossDelayByte0_SHIFT 5 -#define DDRETC_DqsRcvEnGrossDelayByte0_MASK 0x3 -#define DDRETC_DqsRcvEnFineDelayByte1_SHIFT 8 -#define DDRETC_DqsRcvEnGrossDelayByte1_SHIFT 13 -#define DDRETC_DqsRcvEnFineDelayByte2_SHIFT 16 -#define DDRETC_DqsRcvEnGrossDelayByte2_SHIFT 21 -#define DDRETC_DqsRcvEnFineDelayByte3_SHIFT 24 -#define DDRETC_DqsRcvEnGrossDelayByte3_SHIFT 29 - -#define DRAM_DQS_RECV_ENABLE_TIME_CTRL_0_1 0x11 //DIMM0 Channel A -#define DDRETC_DqsRcvEnFineDelayByte4_SHIFT 0 -#define DDRETC_DqsRcvEnGrossDelayByte4_SHIFT 5 -#define DDRETC_DqsRcvEnFineDelayByte5_SHIFT 8 -#define DDRETC_DqsRcvEnGrossDelayByte5_SHIFT 13 -#define DDRETC_DqsRcvEnFineDelayByte6_SHIFT 16 -#define DDRETC_DqsRcvEnGrossDelayByte6_SHIFT 21 -#define DDRETC_DqsRcvEnFineDelayByte7_SHIFT 24 -#define DDRETC_DqsRcvEnGrossDelayByte7_SHIFT 29 - -#define DRAM_DQS_RECV_ENABLE_TIMING_CTRL_ECC_0_0 0x12 -#define DDRETCE_WrChkFineDlyByte0_SHIFT 0 -#define DDRETCE_WrChkGrossDlyByte0_SHIFT 5 - -#define DRAM_DQS_RECV_ENABLE_TIME_CTRL_0_2 0x20 //DIMM0 channel B -#define DDRETC_DqsRcvEnFineDelayByte8_SHIFT 0 -#define DDRETC_DqsRcvEnGrossDelayByte8_SHIFT 5 -#define DDRETC_DqsRcvEnFineDelayByte9_SHIFT 8 -#define DDRETC_DqsRcvEnGrossDelayByte9_SHIFT 13 -#define DDRETC_DqsRcvEnFineDelayByte10_SHIFT 16 -#define DDRETC_DqsRcvEnGrossDelayByte10_SHIFT 21 -#define DDRETC_DqsRcvEnFineDelayByte11_SHIFT 24 -#define DDRETC_DqsRcvEnGrossDelayByte11_SHIFT 29 - -#define DRAM_DQS_RECV_ENABLE_TIME_CTRL_0_3 0x21 // DIMM0 Channel B -#define DDRETC_DqsRcvEnFineDelayByte12_SHIFT 0 -#define DDRETC_DqsRcvEnGrossDelayByte12_SHIFT 5 -#define DDRETC_DqsRcvEnFineDelayByte13_SHIFT 8 -#define DDRETC_DqsRcvEnGrossDelayByte13_SHIFT 13 -#define DDRETC_DqsRcvEnFineDelayByte14_SHIFT 16 -#define DDRETC_DqsRcvEnGrossDelayByte14_SHIFT 21 -#define DDRETC_DqsRcvEnFineDelayByte15_SHIFT 24 -#define DDRETC_DqsRcvEnGrossDelayByte15_SHIFT 29 - -#define DRAM_DQS_RECV_ENABLE_TIMING_CTRL_ECC_0_1 0x22 -#define DDRETCE_WrChkFineDlyByte1_SHIFT 0 -#define DDRETCE_WrChkGrossDlyByte1_SHIFT 5 - -#define DRAM_DQS_RECV_ENABLE_TIME_CTRL_1_0 0x13 //DIMM1 -#define DRAM_DQS_RECV_ENABLE_TIME_CTRL_1_1 0x14 -#define DRAM_DQS_RECV_ENABLE_TIMING_CTRL_ECC_1_0 0x15 -#define DRAM_DQS_RECV_ENABLE_TIME_CTRL_1_2 0x23 -#define DRAM_DQS_RECV_ENABLE_TIME_CTRL_1_3 0x24 -#define DRAM_DQS_RECV_ENABLE_TIMING_CTRL_ECC_1_1 0x25 - -#define DRAM_DQS_RECV_ENABLE_TIME_CTRL_2_0 0x16 // DIMM2 -#define DRAM_DQS_RECV_ENABLE_TIME_CTRL_2_1 0x17 -#define DRAM_DQS_RECV_ENABLE_TIMING_CTRL_ECC_2_0 0x18 -#define DRAM_DQS_RECV_ENABLE_TIME_CTRL_2_2 0x26 -#define DRAM_DQS_RECV_ENABLE_TIME_CTRL_2_3 0x27 -#define DRAM_DQS_RECV_ENABLE_TIMING_CTRL_ECC_2_1 0x28 - -#define DRAM_DQS_RECV_ENABLE_TIME_CTRL_3_0 0x19 // DIMM3 -#define DRAM_DQS_RECV_ENABLE_TIME_CTRL_3_1 0x1a -#define DRAM_DQS_RECV_ENABLE_TIMING_CTRL_ECC_3_0 0x1b -#define DRAM_DQS_RECV_ENABLE_TIME_CTRL_3_2 0x29 -#define DRAM_DQS_RECV_ENABLE_TIME_CTRL_3_3 0x2a -#define DRAM_DQS_RECV_ENABLE_TIMING_CTRL_ECC_3_1 0x2b - -/* 04.06.2006 19:12 */ - -#define DRAM_PHASE_RECOVERY_CTRL_0 0x50 -#define DPRC_PhRecFineDlyByte0_SHIFT 0 -#define DDWTC_PhRecFineDlyByte0_MASK 0x1f -#define DDWTC_PhRecGrossDlyByte0_SHIFT 5 -#define DDWTC_PhRecGrossDlyByte0_MASK 0x3 -#define DDWTC_PhRecFineDlyByte1_SHIFT 8 -#define DDWTC_PhRecGrossDlyByte1_SHIFT 13 -#define DDWTC_PhRecFineDlyByte2_SHIFT 16 -#define DDWTC_PhRecGrossDlyByte2_SHIFT 21 -#define DDWTC_PhRecFineDlyByte3_SHIFT 24 -#define DDWTC_PhRecGrossDlyByte3_SHIFT 29 - -#define DRAM_PHASE_RECOVERY_CTRL_1 0x51 -#define DPRC_PhRecFineDlyByte4_SHIFT 0 -#define DDWTC_PhRecGrossDlyByte4_SHIFT 5 -#define DDWTC_PhRecFineDlyByte5_SHIFT 8 -#define DDWTC_PhRecGrossDlyByte5_SHIFT 13 -#define DDWTC_PhRecFineDlyByte6_SHIFT 16 -#define DDWTC_PhRecGrossDlyByte6_SHIFT 21 -#define DDWTC_PhRecFineDlyByte7_SHIFT 24 -#define DDWTC_PhRecGrossDlyByte7_SHIFT 29 - -#define DRAM_ECC_PHASE_RECOVERY_CTRL 0x52 -#define DEPRC_PhRecEccDlyByte0_SHIFT 0 -#define DEPRC_PhRecEccGrossDlyByte0_SHIFT 5 - -#define DRAM_WRITE_LEVEL_ERROR 0x53 /* read only */ -#define DWLE_WrLvErr_SHIFT 0 -#define DWLE_WrLvErr_MASK 0xff - -#define DRAM_CTRL_MISC 0xa0 -#define DCM_MemCleared (1<<0) /* RD == F2x110 [MemCleared] */ -#define DCM_DramEnabled (1<<9) /* RD == F2x110 [DramEnabled] */ - -#define NB_TIME_STAMP_COUNT_LOW 0xb0 -#define TscLow_SHIFT 0 -#define TscLow_MASK 0xffffffff - -#define NB_TIME_STAMP_COUNT_HIGH 0xb4 -#define TscHigh_SHIFT 0 -#define TscHigh_Mask 0xff - -#define DCT_DEBUG_CTRL 0xf0 /* 0xf0 for DCT0, 0x1f0 is for DCT1*/ -#define DDC_DllAdjust_SHIFT 0 -#define DDC_DllAdjust_MASK 0xff -#define DDC_DllSlower (1<<8) -#define DDC_DllFaster (1<<9) -#define DDC_WrtDqsAdjust_SHIFT 16 -#define DDC_WrtDqsAdjust_MASK 0x7 -#define DDC_WrtDqsAdjustEn (1<<19) - -#define DRAM_CTRL_SEL_LOW 0x110 -#define DCSL_DctSelHiRngEn (1<<0) -#define DCSL_DctSelHi (1<<1) -#define DCSL_DctSelIntLvEn (1<<2) -#define DCSL_MemClrInit (1<<3) /* WR only */ -#define DCSL_DctGangEn (1<<4) -#define DCSL_DctDataIntLv (1<<5) -#define DCSL_DctSelIntLvAddr_SHIFT -#define DCSL_DctSelIntLvAddr_MASK 3 -#define DCSL_DramEnable (1<<8) /* RD only */ -#define DCSL_MemClrBusy (1<<9) /* RD only */ -#define DCSL_MemCleared (1<<10) /* RD only */ -#define DCSL_DctSelBaseAddr_47_27_SHIFT 11 -#define DCSL_DctSelBaseAddr_47_27_MASK 0x1fffff - -#define DRAM_CTRL_SEL_HIGH 0x114 -#define DCSH_DctSelBaseOffset_47_26_SHIFT 10 -#define DCSH_DctSelBaseOffset_47_26_MASK 0x3fffff - -#define MEM_CTRL_CONF_LOW 0x118 -#define MCCL_MctPriCpuRd (1<<0) -#define MCCL_MctPriCpuWr (1<<1) -#define MCCL_MctPriIsocRd_SHIFT 4 -#define MCCL_MctPriIsoc_MASK 0x3 -#define MCCL_MctPriIsocWr_SHIFT 6 -#define MCCL_MctPriIsocWe_MASK 0x3 -#define MCCL_MctPriDefault_SHIFT 8 -#define MCCL_MctPriDefault_MASK 0x3 -#define MCCL_MctPriWr_SHIFT 10 -#define MCCL_MctPriWr_MASK 0x3 -#define MCCL_MctPriIsoc_SHIFT 12 -#define MCCL_MctPriIsoc_MASK 0x3 -#define MCCL_MctPriTrace_SHIFT 14 -#define MCCL_MctPriTrace_MASK 0x3 -#define MCCL_MctPriScrub_SHIFT 16 -#define MCCL_MctPriScrub_MASK 0x3 -#define MCCL_McqMedPriByPassMax_SHIFT 20 -#define MCCL_McqMedPriByPassMax_MASK 0x7 -#define MCCL_McqHiPriByPassMax_SHIFT 24 -#define MCCL_McqHiPriByPassMax_MASK 0x7 -#define MCCL_MctVarPriCntLmt_SHIFT 28 -#define MCCL_MctVarPriCntLmt_MASK 0x7 - -#define MEM_CTRL_CONF_HIGH 0x11c -#define MCCH_DctWrLimit_SHIFT 0 -#define MCCH_DctWrLimit_MASK 0x3 -#define MCCH_MctWrLimit_SHIFT 2 -#define MCCH_MctWrLimit_MASK 0x1f -#define MCCH_MctPrefReqLimit_SHIFT 7 -#define MCCH_MctPrefReqLimit_MASK 0x1f -#define MCCH_PrefCpuDis (1<<12) -#define MCCH_PrefIoDis (1<<13) -#define MCCH_PrefIoFixStrideEn (1<<14) -#define MCCH_PrefFixStrideEn (1<<15) -#define MCCH_PrefFixDist_SHIFT 16 -#define MCCH_PrefFixDist_MASK 0x3 -#define MCCH_PrefConfSat_SHIFT 18 -#define MCCH_PrefConfSat_MASK 0x3 -#define MCCH_PrefOneConf_SHIFT 20 -#define MCCH_PrefOneConf_MASK 0x3 -#define MCCH_PrefTwoConf_SHIFT 22 -#define MCCH_PrefTwoConf_MASK 0x7 -#define MCCH_PrefThreeConf_SHIFT 25 -#define MCCH_prefThreeConf_MASK 0x7 -#define MCCH_PrefDramTrainMode (1<<28) -#define MCCH_FlushWrOnStpGnt (1<<29) -#define MCCH_FlushWr (1<<30) -#define MCCH_MctScrubEn (1<<31) - - -/* Function 3 */ -#define MCA_NB_CONTROL 0x40 -#define MNCT_CorrEccEn (1<<0) -#define MNCT_UnCorrEccEn (1<<1) -#define MNCT_CrcErr0En (1<<2) /* Link 0 */ -#define MNCT_CrcErr1En (1<<3) -#define MNCT_CrcErr2En (1<<4) -#define MBCT_SyncPkt0En (1<<5) /* Link 0 */ -#define MBCT_SyncPkt1En (1<<6) -#define MBCT_SyncPkt2En (1<<7) -#define MBCT_MstrAbrtEn (1<<8) -#define MBCT_TgtAbrtEn (1<<9) -#define MBCT_GartTblEkEn (1<<10) -#define MBCT_AtomicRMWEn (1<<11) -#define MBCT_WdogTmrRptEn (1<<12) -#define MBCT_DevErrEn (1<<13) -#define MBCT_L3ArrayCorEn (1<<14) -#define MBCT_L3ArrayUncEn (1<<15) -#define MBCT_HtProtEn (1<<16) -#define MBCT_HtDataEn (1<<17) -#define MBCT_DramParEn (1<<18) -#define MBCT_RtryHt0En (1<<19) /* Link 0 */ -#define MBCT_RtryHt1En (1<<20) -#define MBCT_RtryHt2En (1<<21) -#define MBCT_RtryHt3En (1<<22) -#define MBCT_CrcErr3En (1<<23) /* Link 3*/ -#define MBCT_SyncPkt3En (1<<24) /* Link 4 */ -#define MBCT_McaUsPwDatErrEn (1<<25) -#define MBCT_NbArrayParEn (1<<26) -#define MBCT_TblWlkDatErrEn (1<<27) -#define MBCT_FbDimmCorErrEn (1<<28) -#define MBCT_FbDimmUnCorErrEn (1<<29) - - - -#define MCA_NB_CONFIG 0x44 -#define MNC_CpuRdDatErrEn (1<<1) -#define MNC_SyncOnUcEccEn (1<<2) -#define MNC_SynvPktGenDis (1<<3) -#define MNC_SyncPktPropDis (1<<4) -#define MNC_IoMstAbortDis (1<<5) -#define MNC_CpuErrDis (1<<6) -#define MNC_IoErrDis (1<<7) -#define MNC_WdogTmrDis (1<<8) -#define MNC_WdogTmrCntSel_2_0_SHIFT 9 /* 3 is ar f3x180 */ -#define MNC_WdogTmrCntSel_2_0_MASK 0x3 -#define MNC_WdogTmrBaseSel_SHIFT 12 -#define MNC_WdogTmrBaseSel_MASK 0x3 -#define MNC_LdtLinkSel_SHIFT 14 -#define MNC_LdtLinkSel_MASK 0x3 -#define MNC_GenCrcErrByte0 (1<<16) -#define MNC_GenCrcErrByte1 (1<<17) -#define MNC_SubLinkSel_SHIFT 18 -#define MNC_SubLinkSel_MASK 0x3 -#define MNC_SyncOnWdogEn (1<<20) -#define MNC_SyncOnAnyErrEn (1<<21) -#define MNC_DramEccEn (1<<22) -#define MNC_ChipKillEccEn (1<<23) -#define MNC_IoRdDatErrEn (1<<24) -#define MNC_DisPciCfgCpuErrRsp (1<<25) -#define MNC_CorrMcaExcEn (1<<26) -#define MNC_NbMcaToMstCpuEn (1<<27) -#define MNC_DisTgtAbtCpuErrRsp (1<<28) -#define MNC_DisMstAbtCpuErrRsp (1<<29) -#define MNC_SyncOnDramAdrParErrEn (1<<30) -#define MNC_NbMcaLogEn (1<<31) - -#define MCA_NB_STATUS_LOW 0x48 -#define MNSL_ErrorCode_SHIFT 0 -#define MNSL_ErrorCode_MASK 0xffff -#define MNSL_ErrorCodeExt_SHIFT 16 -#define MNSL_ErrorCodeExt_MASK 0x1f -#define MNSL_Syndrome_15_8_SHIFT 24 -#define MNSL_Syndrome_15_8_MASK 0xff - -#define MCA_NB_STATUS_HIGH 0x4c -#define MNSH_ErrCPU_SHIFT 0 -#define MNSH_ErrCPU_MASK 0xf -#define MNSH_LDTLink_SHIFT 4 -#define MNSH_LDTLink_MASK 0xf -#define MNSH_ErrScrub (1<<8) -#define MNSH_SubLink (1<<9) -#define MNSH_McaStatusSubCache_SHIFT 10 -#define MNSH_McaStatusSubCache_MASK 0x3 -#define MNSH_Deffered (1<<12) -#define MNSH_UnCorrECC (1<<13) -#define MNSH_CorrECC (1<<14) -#define MNSH_Syndrome_7_0_SHIFT 15 -#define MNSH_Syndrome_7_0_MASK 0xff -#define MNSH_PCC (1<<25) -#define MNSH_ErrAddrVal (1<<26) -#define MNSH_ErrMiscVal (1<<27) -#define MNSH_ErrEn (1<<28) -#define MNSH_ErrUnCorr (1<<29) -#define MNSH_ErrOver (1<<30) -#define MNSH_ErrValid (1<<31) - -#define MCA_NB_ADDR_LOW 0x50 -#define MNAL_ErrAddr_31_1_SHIFT 1 -#define MNAL_ErrAddr_31_1_MASK 0x7fffffff - -#define MCA_NB_ADDR_HIGH 0x54 -#define MNAL_ErrAddr_47_32_SHIFT 0 -#define MNAL_ErrAddr_47_32_MASK 0xffff - -#define DRAM_SCRUB_RATE_CTRL 0x58 -#define SCRUB_NONE 0 -#define SCRUB_40ns 1 -#define SCRUB_80ns 2 -#define SCRUB_160ns 3 -#define SCRUB_320ns 4 -#define SCRUB_640ns 5 -#define SCRUB_1_28us 6 -#define SCRUB_2_56us 7 -#define SCRUB_5_12us 8 -#define SCRUB_10_2us 9 -#define SCRUB_20_5us 0xa -#define SCRUB_41_0us 0xb -#define SCRUB_81_9us 0xc -#define SCRUB_163_8us 0xd -#define SCRUB_327_7us 0xe -#define SCRUB_655_4us 0xf -#define SCRUB_1_31ms 0x10 -#define SCRUB_2_62ms 0x11 -#define SCRUB_5_24ms 0x12 -#define SCRUB_10_49ms 0x13 -#define SCRUB_20_97ms 0x14 -#define SCRUB_42ms 0x15 -#define SCRUB_84ms 0x16 -#define DSRC_DramScrub_SHFIT 0 -#define DSRC_DramScrub_MASK 0x1f -#define DSRC_L2Scrub_SHIFT 8 -#define DSRC_L2Scrub_MASK 0x1f -#define DSRC_DcacheScrub_SHIFT 16 -#define DSRC_DcacheScrub_MASK 0x1f -#define DSRC_L3Scrub_SHIFT 24 -#define DSRC_L3Scrub_MASK 0x1f - -#define DRAM_SCRUB_ADDR_LOW 0x5C -#define DSAL_ScrubReDirEn (1<<0) -#define DSAL_ScrubAddrLo_SHIFT 6 -#define DSAL_ScrubAddrLo_MASK 0x3ffffff - -#define DRAM_SCRUB_ADDR_HIGH 0x60 -#define DSAH_ScrubAddrHi_SHIFT 0 -#define DSAH_ScrubAddrHi_MASK 0xffff - -#define HW_THERMAL_CTRL 0x64 - -#define SW_THERMAL_CTRL 0x68 - -#define DATA_BUF_CNT 0x6c - -#define SRI_XBAR_CMD_BUF_CNT 0x70 - -#define XBAR_SRI_CMD_BUF_CNT 0x74 - -#define MCT_XBAR_CMD_BUF_CNT 0x78 - -#define ACPI_PWR_STATE_CTRL 0x80 /* till 0x84 */ - -#define NB_CONFIG_LOW 0x88 -#define NB_CONFIG_HIGH 0x8c - -#define GART_APERTURE_CTRL 0x90 - -#define GART_APERTURE_BASE 0x94 - -#define GART_TBL_BASE 0x98 - -#define GART_CACHE_CTRL 0x9c - -#define PWR_CTRL_MISC 0xa0 - -#define RPT_TEMP_CTRL 0xa4 - -#define ON_LINE_SPARE_CTRL 0xb0 - -#define SBI_P_STATE_LIMIT 0xc4 - -#define CLK_PWR_TIMING_CTRL0 0xd4 -#define CLK_PWR_TIMING_CTRL1 0xd8 -#define CLK_PWR_TIMING_CTRL2 0xdc - -#define THERMTRIP_STATUS 0xE4 - - -#define NORTHBRIDGE_CAP 0xE8 -#define NBCAP_TwoChanDRAMcap (1 << 0) -#define NBCAP_DualNodeMPcap (1 << 1) -#define NBCAP_EightNodeMPcap (1 << 2) -#define NBCAP_ECCcap (1 << 3) -#define NBCAP_ChipkillECCcap (1 << 4) -#define NBCAP_DdrMaxRate_SHIFT 5 -#define NBCAP_DdrMaxRate_MASK 7 -#define NBCAP_DdrMaxRate_400 7 -#define NBCAP_DdrMaxRate_533 6 -#define NBCAP_DdrMaxRate_667 5 -#define NBCAP_DdrMaxRate_800 4 -#define NBCAP_DdrMaxRate_1067 3 -#define NBCAP_DdrMaxRate_1333 2 -#define NBCAP_DdrMaxRate_1600 1 -#define NBCAP_DdrMaxRate_3_2G 6 -#define NBCAP_DdrMaxRate_4_0G 5 -#define NBCAP_DdrMaxRate_4_8G 4 -#define NBCAP_DdrMaxRate_6_4G 3 -#define NBCAP_DdrMaxRate_8_0G 2 -#define NBCAP_DdrMaxRate_9_6G 1 -#define NBCAP_Mem_ctrl_cap (1 << 8) -#define MBCAP_SVMCap (1<<9) -#define NBCAP_HtcCap (1<<10) -#define NBCAP_CmpCap_SHIFT 12 -#define NBCAP_CmpCap_MASK 3 -#define NBCAP_MpCap_SHIFT 16 -#define NBCAP_MpCap_MASK 7 -#define NBCAP_MpCap_1N 7 -#define NBCAP_MpCap_2N 6 -#define NBCAP_MpCap_4N 5 -#define NBCAP_MpCap_8N 4 -#define NBCAP_MpCap_32N 0 -#define NBCAP_UnGangEn_SHIFT 20 -#define NBCAP_UnGangEn_MASK 0xf -#define NBCAP_L3Cap (1<<25) -#define NBCAP_HtAcCap (1<<26) - -/* 04/04/2006 18:00 */ - -#define EXT_NB_MCA_CTRL 0x180 - -#define NB_EXT_CONF 0x188 -#define DOWNCORE_CTRL 0x190 -#define DWNCC_DisCore_SHIFT 0 -#define DWNCC_DisCore_MASK 0xf - -/* Function 5 for FBDIMM */ -#define FBD_DRAM_TIMING_LOW - -#define LinkConnected (1 << 0) -#define InitComplete (1 << 1) -#define NonCoherent (1 << 2) -#define ConnectionPending (1 << 4) - -// Use the LAPIC timer count register to hold each core's init status -// Format: byte 0 - state -// byte 1 - fid_max -// byte 2 - nb_cof_vid_update -// byte 3 - apic id - -#define LAPIC_MSG_REG 0x380 -#define F10_APSTATE_STARTED 0x13 // start of AP execution -#define F10_APSTATE_ASLEEP 0x14 // AP sleeping -#define F10_APSTATE_STOPPED 0x15 // allow AP to stop -#define F10_APSTATE_RESET 0x01 // waiting for warm reset - -#define MAX_CORES_SUPPORTED 128 - -#include "nums.h" - -#if NODE_NUMS == 64 - #define NODE_PCI(x, fn) ((x < 32)?(PCI_DEV(CONFIG_CBB,(CONFIG_CDB+x),fn)):(PCI_DEV((CONFIG_CBB-1),(CONFIG_CDB+x-32),fn))) -#else - #define NODE_PCI(x, fn) PCI_DEV(CONFIG_CBB,(CONFIG_CDB+x),fn) -#endif - -/* Include wrapper for MCT (works for DDR2 or DDR3) */ -#include - -struct link_pair_t { - pci_devfn_t udev; - u32 upos; - u32 uoffs; - pci_devfn_t dev; - u32 pos; - u32 offs; - u8 host; - u8 nodeid; - u8 linkn; - u8 rsv; -} __packed; - -struct nodes_info_t { - u32 nodes_in_group; // could be 2, 3, 4, 5, 6, 7, 8 - u32 groups_in_plane; // could be 1, 2, 3, 4, 5 - u32 planes; // could be 1, 2 - u32 up_planes; // down planes will be [up_planes, planes) -} __packed; - -struct ht_link_config { - uint32_t ht_speed_limit; // Speed in MHz; 0 for autodetect (default) -}; - -/* be careful with the alignment of sysinfo, bacause sysinfo may be shared by coreboot_car and ramstage stage. and ramstage may be running at 64bit later.*/ - -struct sys_info { - int32_t needs_reset; - - u8 ln[NODE_NUMS*NODE_NUMS];// [0, 3] link n, [4, 7] will be hop num - u16 ln_tn[NODE_NUMS*8]; // for 0x0zzz: bit [0,7] target node num, bit[8,11] respone link from target num; 0x80ff mean not inited, 0x4yyy mean non coherent and yyy is link pair index - struct nodes_info_t nodes_info; - u32 nodes; - - u8 host_link_freq[NODE_NUMS*8]; // record freq for every link from cpu, 0x0f means don't need to touch it - u16 host_link_freq_cap[NODE_NUMS*8]; //cap - - struct ht_link_config ht_link_cfg; - - u32 segbit; - u32 sbdn; - u32 sblk; - u32 sbbusn; - - u32 ht_c_num; - u32 ht_c_conf_bus[HC_NUMS]; // 4-->32 - - struct link_pair_t link_pair[HC_NUMS*4];// enough? only in_conherent, 32 chain and every chain have 4 HT device - u32 link_pair_num; - - struct mem_controller ctrl[NODE_NUMS]; - - struct MCTStatStruc MCTstat; - struct DCTStatStruc DCTstatA[NODE_NUMS]; -} __packed; - -struct device *get_node_pci(u32 nodeid, u32 fn); - -void showallroutes(int level, pci_devfn_t dev); - -void setup_resource_map_offset(const u32 *register_values, u32 max, u32 - offset_pci_dev, u32 offset_io_base); - -void setup_resource_map_x_offset(const u32 *register_values, u32 max, u32 - offset_pci_dev, u32 offset_io_base); - -void setup_resource_map_x(const u32 *register_values, u32 max); -void setup_resource_map(const u32 *register_values, u32 max); -void setup_mb_resource_map(void); - -/* reset_test.c */ -u32 cpu_init_detected(u8 nodeid); -u32 bios_reset_detected(void); -u32 cold_reset_detected(void); -u32 other_reset_detected(void); -u32 warm_reset_detect(u8 nodeid); -void distinguish_cpu_resets(u8 nodeid); -u32 get_sblk(void); -u8 get_sbbusn(u8 sblk); -void set_bios_reset(void); - -#include "northbridge/amd/amdht/porting.h" -BOOL AMD_CB_ManualBUIDSwapList(u8 Node, u8 Link, const u8 **List); - -struct acpi_rsdp; - -unsigned long northbridge_write_acpi_tables(struct device *device, - unsigned long start, - struct acpi_rsdp *rsdp); -void northbridge_acpi_write_vars(struct device *device); - -#endif /* AMDFAM10_H */ diff --git a/src/northbridge/amd/amdfam10/amdfam10_util.asl b/src/northbridge/amd/amdfam10/amdfam10_util.asl deleted file mode 100644 index 6e2118d1ae..0000000000 --- a/src/northbridge/amd/amdfam10/amdfam10_util.asl +++ /dev/null @@ -1,321 +0,0 @@ -// -// This file is part of the coreboot project. -// -// Copyright (C) 2015 Timothy Pearson , Raptor Engineering -// Copyright (C) 2007 Advanced Micro Devices, Inc. -// -// This program is free software; you can redistribute it and/or modify -// it under the terms of the GNU General Public License as published by -// the Free Software Foundation; version 2 of the License. -// -// This program is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. -// - -//AMD FAM10 util for BUSB and res range - -Scope (\_SB) -{ - - Name (OSTB, Ones) - Method (OSVR, 0, NotSerialized) - { - If (LEqual (^OSTB, Ones)) - { - Store (0x00, ^OSTB) - } - - Return (^OSTB) - } - - Method (SEQL, 2, Serialized) - { - Store (SizeOf (Arg0), Local0) - Store (SizeOf (Arg1), Local1) - If (LNot (LEqual (Local0, Local1))) { Return (Zero) } - - Name (BUF0, Buffer (Local0) {}) - Store (Arg0, BUF0) - Name (BUF1, Buffer (Local0) {}) - Store (Arg1, BUF1) - Store (Zero, Local2) - While (LLess (Local2, Local0)) - { - Store (DerefOf (Index (BUF0, Local2)), Local3) - Store (DerefOf (Index (BUF1, Local2)), Local4) - If (LNot (LEqual (Local3, Local4))) { Return (Zero) } - - Increment (Local2) - } - - Return (One) - } - - - Method (DADD, 2, NotSerialized) - { - Store(Arg1, Local0) - Store(Arg0, Local1) - Add(ShiftLeft(Local1,16), Local0, Local0) - Return (Local0) - } - - - Method (GHCE, 1, NotSerialized) // check if the HC enabled - { - Store (DerefOf (Index (\_SB.PCI0.HCLK, Arg0)), Local1) - if (LEqual (And(Local1, 0x01), 0x01)) { Return (0x0F) } - Else { Return (0x00) } - } - - Method (GHCN, 1, NotSerialized) // get the node num for the HC - { - Store (0x00, Local0) - Store (DerefOf (Index (\_SB.PCI0.HCLK, Arg0)), Local1) - Store (ShiftRight(And (Local1, 0xfc), 0x02), Local0) - Return (Local0) - } - - Method (GHCL, 1, NotSerialized) // get the link num on node for the HC - { - Store (0x00, Local0) - Store (DerefOf (Index (\_SB.PCI0.HCLK, Arg0)), Local1) - Store (ShiftRight(And (Local1, 0x700), 0x08), Local0) - Return (Local0) - } - - Method (GHCD, 2, NotSerialized) // get the unit id base for the HT device in HC - { - Store (0x00, Local0) - Store (DerefOf (Index (\_SB.PCI0.HCDN, Arg0)), Local1) - Store (Arg1, Local2) // Arg1 could be 3, 2, 1, 0 - Multiply (Local2, 0x08, Local2) // change to 24, 16, 8, 0 - Store (And (ShiftRight(Local1, Local2), 0xff), Local0) - Return (Local0) - } - - Method (GBUS, 2, NotSerialized) - { - Store (0x00, Local0) - While (LLess (Local0, 0x20)) // 32 ht links - { - Store (DerefOf (Index (\_SB.PCI0.BUSN, Local0)), Local1) - If (LEqual (And (Local1, 0x03), 0x03)) - { - If (LEqual (Arg0, ShiftRight (And (Local1, 0xfc), 0x02))) - { - If (LOr (LEqual (Arg1, 0xFF), LEqual (Arg1, ShiftRight (And (Local1, 0x0700), 0x08)))) - { - Return (ShiftRight (And (Local1, 0x000FF000), 0x0c)) - } - } - } - - Increment (Local0) - } - - Return (0x00) - } - - Method (GWBN, 2, Serialized) - { - Name (BUF0, ResourceTemplate () - { - WordBusNumber (ResourceProducer, MinFixed, MaxFixed, PosDecode, - 0x0000, // Address Space Granularity - 0x0000, // Address Range Minimum - 0x0000, // Address Range Maximum - 0x0000, // Address Translation Offset - 0x0001,,,) - }) - CreateWordField (BUF0, 0x08, BMIN) - CreateWordField (BUF0, 0x0A, BMAX) - CreateWordField (BUF0, 0x0E, BLEN) - Store (0x00, Local0) - While (LLess (Local0, 0x20)) - { - Store (DerefOf (Index (\_SB.PCI0.BUSN, Local0)), Local1) - If (LEqual (And (Local1, 0x03), 0x03)) - { - If (LEqual (Arg0, ShiftRight (And (Local1, 0xfc), 0x02))) - { - If (LOr (LEqual (Arg1, 0xFF), LEqual (Arg1, ShiftRight (And (Local1, 0x0700), 0x08)))) - { - Store (ShiftRight (And (Local1, 0x000FF000), 0x0c), BMIN) - Store (ShiftRight (Local1, 0x14), BMAX) - Subtract (BMAX, BMIN, BLEN) - Increment (BLEN) - Return (RTAG (BUF0)) - } - } - } - - Increment (Local0) - } - - Return (RTAG (BUF0)) - } - - Method (GMEM, 2, Serialized) - { - Name (BUF0, ResourceTemplate () - { - DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, NonCacheable, ReadWrite, - 0x00000000, // Address Space Granularity - 0x00000000, // Address Range Minimum - 0x00000000, // Address Range Maximum - 0x00000000, // Address Translation Offset - 0x00000001,,, - , AddressRangeMemory, TypeStatic) - }) - CreateDWordField (BUF0, 0x0A, MMIN) - CreateDWordField (BUF0, 0x0E, MMAX) - CreateDWordField (BUF0, 0x16, MLEN) - Store (0x00, Local0) - Store (0x00, Local4) - Store (0x00, Local3) - While (LLess (Local0, 0x80)) // 0x20 links * 2(mem, prefmem) *2 (base, limit) - { - Store (DerefOf (Index (\_SB.PCI0.MMIO, Local0)), Local1) - Increment (Local0) - Store (DerefOf (Index (\_SB.PCI0.MMIO, Local0)), Local2) - If (LEqual (And (Local1, 0x03), 0x03)) - { - If (LEqual (Arg0, And (Local2, 0x3f))) - { - If (LOr (LEqual (Arg1, 0xFF), LEqual (Arg1, ShiftRight (And (Local1, 0x70), 0x04)))) - { - Store (ShiftLeft (And (Local1, 0xFFFFFF00), 0x08), MMIN) - Store (ShiftLeft (And (Local2, 0xFFFFFF00), 0x08), MMAX) - Or (MMAX, 0xFFFF, MMAX) - Subtract (MMAX, MMIN, MLEN) - Increment (MLEN) - - If (Local4) - { - Concatenate (RTAG (BUF0), Local3, Local5) - Store (Local5, Local3) - } - Else - { - Store (RTAG (BUF0), Local3) - } - - Increment (Local4) - } - } - } - - Increment (Local0) - } - - If (LNot (Local4)) - { - Store (BUF0, Local3) - } - - Return (Local3) - } - - Method (GIOR, 2, Serialized) - { - Name (BUF0, ResourceTemplate () - { - DWordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, - 0x00000000, // Address Space Granularity - 0x00000000, // Address Range Minimum - 0x00000000, // Address Range Maximum - 0x00000000, // Address Translation Offset - 0x00000001,,, - , TypeStatic) - }) - CreateDWordField (BUF0, 0x0A, PMIN) - CreateDWordField (BUF0, 0x0E, PMAX) - CreateDWordField (BUF0, 0x16, PLEN) - Store (0x00, Local0) - Store (0x00, Local4) - Store (0x00, Local3) - While (LLess (Local0, 0x40)) // 0x20 ht links * 2 (base, limit) - { - Store (DerefOf (Index (\_SB.PCI0.PCIO, Local0)), Local1) - Increment (Local0) - Store (DerefOf (Index (\_SB.PCI0.PCIO, Local0)), Local2) - If (LEqual (And (Local1, 0x03), 0x03)) - { - If (LEqual (Arg0, And (Local2, 0x3f))) - { - If (LOr (LEqual (Arg1, 0xFF), LEqual (Arg1, ShiftRight (And (Local1, 0x70), 0x04)))) - { - Store (And (Local1, 0x01FFF000), PMIN) - Store (And (Local2, 0x01FFF000), PMAX) - Or (PMAX, 0x0FFF, PMAX) - Subtract (PMAX, PMIN, PLEN) - Increment (PLEN) - - If (Local4) - { - Concatenate (RTAG (BUF0), Local3, Local5) - Store (Local5, Local3) - } - Else - { - If (LGreater (PMAX, PMIN)) - { - If (LOr (LAnd (LEqual (Arg1, 0xFF), LEqual (Arg0, 0x00)), LEqual (Arg1, \_SB.PCI0.SBLK))) - { - Store (0x0D00, PMIN) - Subtract (PMAX, PMIN, PLEN) - Increment (PLEN) - } - - Store (RTAG (BUF0), Local3) - Increment (Local4) - } - - If (And (Local1, 0x10)) - { - Store (0x03B0, PMIN) - Store (0x03DF, PMAX) - Store (0x30, PLEN) - - If (Local4) - { - Concatenate (RTAG (BUF0), Local3, Local5) - Store (Local5, Local3) - } - Else - { - Store (RTAG (BUF0), Local3) - } - } - } - - Increment (Local4) - } - } - } - - Increment (Local0) - } - - If (LNot (Local4)) - { - Store (RTAG (BUF0), Local3) - } - - Return (Local3) - } - - Method (RTAG, 1, NotSerialized) - { - Store (Arg0, Local0) - Store (SizeOf (Local0), Local1) - Subtract (Local1, 0x02, Local1) - Multiply (Local1, 0x08, Local1) - CreateField (Local0, 0x00, Local1, RETB) - Store (RETB, Local2) - Return (Local2) - } -} diff --git a/src/northbridge/amd/amdfam10/amdfam10_util.c b/src/northbridge/amd/amdfam10/amdfam10_util.c deleted file mode 100644 index 23e92323a8..0000000000 --- a/src/northbridge/amd/amdfam10/amdfam10_util.c +++ /dev/null @@ -1,112 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2015 Timothy Pearson , Raptor Engineering - * Copyright (C) 2007 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include -#include -#include "raminit.h" -#include - -#if !ENV_PCI_SIMPLE_DEVICE -u32 Get_NB32(u32 dev, u32 reg) -{ - return pci_read_config32(pcidev_path_on_root(PCI_DEV2DEVFN(dev)), reg); -} -#endif - -uint64_t mctGetLogicalCPUID(u32 Node) -{ - /* Converts the CPUID to a logical ID MASK that is used to check - CPU version support versions */ - u32 dev; - u32 val, valx; - u32 family, model, stepping; - uint64_t ret; - - if (Node == 0xFF) { /* current node */ - val = cpuid_eax(0x80000001); - } else { - dev = PA_NBMISC(Node); - val = Get_NB32(dev, 0xfc); - } - - family = ((val >> 8) & 0x0f) + ((val >> 20) & 0xff); - model = ((val >> 4) & 0x0f) | ((val >> (16-4)) & 0xf0); - stepping = val & 0x0f; - - valx = (family << 12) | (model << 4) | (stepping); - - switch (valx) { - case 0x10000: - ret = AMD_DR_A0A; - break; - case 0x10001: - ret = AMD_DR_A1B; - break; - case 0x10002: - ret = AMD_DR_A2; - break; - case 0x10020: - ret = AMD_DR_B0; - break; - case 0x10021: - ret = AMD_DR_B1; - break; - case 0x10022: - ret = AMD_DR_B2; - break; - case 0x10023: - ret = AMD_DR_B3; - break; - case 0x10042: - ret = AMD_RB_C2; - break; - case 0x10043: - ret = AMD_RB_C3; - break; - case 0x10062: - ret = AMD_DA_C2; - break; - case 0x10063: - ret = AMD_DA_C3; - break; - case 0x10080: - ret = AMD_HY_D0; - break; - case 0x10081: - case 0x10091: - ret = AMD_HY_D1; - break; - case 0x100a0: - ret = AMD_PH_E0; - break; - case 0x15012: - case 0x1501f: - ret = AMD_OR_B2; - break; - case 0x15020: - case 0x15101: - ret = AMD_OR_C0; - break; - default: - /* FIXME: mabe we should die() here. */ - printk(BIOS_ERR, "FIXME! CPU Version unknown or not supported! %08x\n", valx); - ret = 0; - } - - return ret; -} diff --git a/src/northbridge/amd/amdfam10/bootblock.c b/src/northbridge/amd/amdfam10/bootblock.c deleted file mode 100644 index f2d5f89ec7..0000000000 --- a/src/northbridge/amd/amdfam10/bootblock.c +++ /dev/null @@ -1,22 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include "northbridge/amd/amdfam10/early_ht.c" - -static void bootblock_northbridge_init(void) { - /* Nothing special needs to be done to find bus 0 */ - /* Allow the HT devices to be found */ - /* mov bsp to bus 0xff when > 8 nodes */ - set_bsp_node_CHtExtNodeCfgEn(); - enumerate_ht_chain(); -} diff --git a/src/northbridge/amd/amdfam10/chip.h b/src/northbridge/amd/amdfam10/chip.h deleted file mode 100644 index daf429d91a..0000000000 --- a/src/northbridge/amd/amdfam10/chip.h +++ /dev/null @@ -1,25 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2015 Timothy Pearson , Raptor Engineering - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef _AMD_FAM10_CHIP_H_ -#define _AMD_FAM10_CHIP_H_ - -#include - -struct northbridge_amd_amdfam10_config { - uint64_t maximum_memory_capacity; -}; - -#endif /* _AMD_FAM10_CHIP_H_ */ diff --git a/src/northbridge/amd/amdfam10/debug.c b/src/northbridge/amd/amdfam10/debug.c deleted file mode 100644 index 5090352e9a..0000000000 --- a/src/northbridge/amd/amdfam10/debug.c +++ /dev/null @@ -1,324 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include "debug.h" -#include -#include -#include -#include -#include - -void print_debug_addr(const char *str, void *val) -{ -#if CONFIG(DEBUG_CAR) - printk(BIOS_DEBUG, "------Address debug: %s%p------\n", str, val); -#endif -} - -void print_debug_pci_dev(u32 dev) -{ - printk(BIOS_DEBUG, "PCI: %02x:%02x.%02x", (dev>>20) & 0xff, (dev>>15) & 0x1f, (dev>>12) & 0x7); -} - -void print_pci_devices(void) -{ - pci_devfn_t dev; - for (dev = PCI_DEV(0, 0, 0); - dev <= PCI_DEV(0xff, 0x1f, 0x7); - dev += PCI_DEV(0,0,1)) { - u32 id; - id = pci_read_config32(dev, PCI_VENDOR_ID); - if (((id & 0xffff) == 0x0000) || ((id & 0xffff) == 0xffff) || - (((id >> 16) & 0xffff) == 0xffff) || - (((id >> 16) & 0xffff) == 0x0000)) { - continue; - } - print_debug_pci_dev(dev); - printk(BIOS_DEBUG, " %04x:%04x\n", (id & 0xffff), (id>>16)); - if (((dev>>12) & 0x07) == 0) { - u8 hdr_type; - hdr_type = pci_read_config8(dev, PCI_HEADER_TYPE); - if ((hdr_type & 0x80) != 0x80) { - dev += PCI_DEV(0,0,7); - } - } - } -} - -void print_pci_devices_on_bus(u32 busn) -{ - pci_devfn_t dev; - for (dev = PCI_DEV(busn, 0, 0); - dev <= PCI_DEV(busn, 0x1f, 0x7); - dev += PCI_DEV(0,0,1)) { - u32 id; - id = pci_read_config32(dev, PCI_VENDOR_ID); - if (((id & 0xffff) == 0x0000) || ((id & 0xffff) == 0xffff) || - (((id >> 16) & 0xffff) == 0xffff) || - (((id >> 16) & 0xffff) == 0x0000)) { - continue; - } - print_debug_pci_dev(dev); - printk(BIOS_DEBUG, " %04x:%04x\n", (id & 0xffff), (id>>16)); - if (((dev>>12) & 0x07) == 0) { - u8 hdr_type; - hdr_type = pci_read_config8(dev, PCI_HEADER_TYPE); - if ((hdr_type & 0x80) != 0x80) { - dev += PCI_DEV(0,0,7); - } - } - } -} - -void dump_pci_device_range(u32 dev, u32 start_reg, u32 size) -{ - int i; - print_debug_pci_dev(dev); - int j; - int end = start_reg + size; - - for (i = start_reg; i < end; i+=4) { - u32 val; - if ((i & 0x0f) == 0) { - printk(BIOS_DEBUG, "\n%04x:",i); - } - val = pci_read_config32(dev, i); - for (j = 0; j < 4; j++) { - printk(BIOS_DEBUG, " %02x", val & 0xff); - val >>= 8; - } - } - printk(BIOS_DEBUG, "\n"); -} - -void dump_pci_device(u32 dev) -{ - dump_pci_device_range(dev, 0, 4096); -} - -void dump_pci_device_index_wait_range(u32 dev, u32 index_reg, u32 start, - u32 size) -{ - int i; - int end = start + size; - print_debug_pci_dev(dev); - printk(BIOS_DEBUG, " -- index_reg=%08x", index_reg); - - for (i = start; i < end; i++) { - u32 val; - int j; - printk(BIOS_DEBUG, "\n%02x:",i); - val = pci_read_config32_index_wait(dev, index_reg, i); - for (j = 0; j < 4; j++) { - printk(BIOS_DEBUG, " %02x", val & 0xff); - val >>= 8; - } - - } - printk(BIOS_DEBUG, "\n"); -} - -void dump_pci_device_index_wait(u32 dev, u32 index_reg) -{ - dump_pci_device_index_wait_range(dev, index_reg, 0, 0x54); - dump_pci_device_index_wait_range(dev, index_reg, 0x100, 0x08); //DIMM1 when memclk > 400Hz -} - -void dump_pci_device_index(u32 dev, u32 index_reg, u32 type, u32 length) -{ - int i; - print_debug_pci_dev(dev); - - printk(BIOS_DEBUG, " index reg: %04x type: %02x", index_reg, type); - - type<<=28; - - for (i = 0; i < length; i++) { - u32 val; - if ((i & 0x0f) == 0) { - printk(BIOS_DEBUG, "\n%02x:",i); - } - val = pci_read_config32_index(dev, index_reg, i|type); - printk(BIOS_DEBUG, " %08x", val); - } - printk(BIOS_DEBUG, "\n"); -} - -void dump_pci_devices(void) -{ - pci_devfn_t dev; - for (dev = PCI_DEV(0, 0, 0); - dev <= PCI_DEV(0xff, 0x1f, 0x7); - dev += PCI_DEV(0,0,1)) { - u32 id; - id = pci_read_config32(dev, PCI_VENDOR_ID); - if (((id & 0xffff) == 0x0000) || ((id & 0xffff) == 0xffff) || - (((id >> 16) & 0xffff) == 0xffff) || - (((id >> 16) & 0xffff) == 0x0000)) { - continue; - } - dump_pci_device(dev); - - if (((dev>>12) & 0x07) == 0) { - u8 hdr_type; - hdr_type = pci_read_config8(dev, PCI_HEADER_TYPE); - if ((hdr_type & 0x80) != 0x80) { - dev += PCI_DEV(0,0,7); - } - } - } -} - -void dump_pci_devices_on_bus(u32 busn) -{ - pci_devfn_t dev; - for (dev = PCI_DEV(busn, 0, 0); - dev <= PCI_DEV(busn, 0x1f, 0x7); - dev += PCI_DEV(0,0,1)) { - u32 id; - id = pci_read_config32(dev, PCI_VENDOR_ID); - if (((id & 0xffff) == 0x0000) || ((id & 0xffff) == 0xffff) || - (((id >> 16) & 0xffff) == 0xffff) || - (((id >> 16) & 0xffff) == 0x0000)) { - continue; - } - dump_pci_device(dev); - - if (((dev>>12) & 0x07) == 0) { - u8 hdr_type; - hdr_type = pci_read_config8(dev, PCI_HEADER_TYPE); - if ((hdr_type & 0x80) != 0x80) { - dev += PCI_DEV(0,0,7); - } - } - } -} - -#if CONFIG(DEBUG_SMBUS) -void dump_spd_registers(const struct mem_controller *ctrl) -{ - int i; - printk(BIOS_DEBUG, "\n"); - for (i = 0; i < DIMM_SOCKETS; i++) { - u32 device; - device = ctrl->spd_addr[i]; - if (device) { - int j; - printk(BIOS_DEBUG, "dimm: %02x.0: %02x", i, device); - for (j = 0; j < 128; j++) { - int status; - u8 byte; - if ((j & 0xf) == 0) { - printk(BIOS_DEBUG, "\n%02x: ", j); - } - status = smbus_read_byte(device, j); - if (status < 0) { - break; - } - byte = status & 0xff; - printk(BIOS_DEBUG, "%02x ", byte); - } - printk(BIOS_DEBUG, "\n"); - } - device = ctrl->spd_addr[i+DIMM_SOCKETS]; - if (device) { - int j; - printk(BIOS_DEBUG, "dimm: %02x.1: %02x", i, device); - for (j = 0; j < 128; j++) { - int status; - u8 byte; - if ((j & 0xf) == 0) { - printk(BIOS_DEBUG, "\n%02x: ", j); - } - status = smbus_read_byte(device, j); - if (status < 0) { - break; - } - byte = status & 0xff; - printk(BIOS_DEBUG, "%02x ", byte); - } - printk(BIOS_DEBUG, "\n"); - } - } -} - -void dump_smbus_registers(void) -{ - u32 device; - printk(BIOS_DEBUG, "\n"); - for (device = 1; device < 0x80; device++) { - int j; - if (smbus_read_byte(device, 0) < 0) continue; - printk(BIOS_DEBUG, "smbus: %02x", device); - for (j = 0; j < 256; j++) { - int status; - u8 byte; - status = smbus_read_byte(device, j); - if (status < 0) { - break; - } - if ((j & 0xf) == 0) { - printk(BIOS_DEBUG, "\n%02x: ",j); - } - byte = status & 0xff; - printk(BIOS_DEBUG, "%02x ", byte); - } - printk(BIOS_DEBUG, "\n"); - } -} -#endif - -void dump_io_resources(u32 port) -{ - - int i; - udelay(2000); - printk(BIOS_DEBUG, "%04x:\n", port); - for (i = 0; i < 256; i++) { - u8 val; - if ((i & 0x0f) == 0) { - printk(BIOS_DEBUG, "%02x:", i); - } - val = inb(port); - printk(BIOS_DEBUG, " %02x",val); - if ((i & 0x0f) == 0x0f) { - printk(BIOS_DEBUG, "\n"); - } - port++; - } -} - -#if CONFIG(DIMM_DDR2) -void print_tx(const char *strval, u32 val) -{ -#if CONFIG(DEBUG_RAM_SETUP) - printk(BIOS_DEBUG, "%s%08x\n", strval, val); -#endif -} - -void print_t(const char *strval) -{ -#if CONFIG(DEBUG_RAM_SETUP) - printk(BIOS_DEBUG, "%s", strval); -#endif -} -#endif /* CONFIG_DIMM_DDR2 */ - -void print_tf(const char *func, const char *strval) -{ -#if CONFIG(DEBUG_RAM_SETUP) - printk(BIOS_DEBUG, "%s: %s", func, strval); -#endif -} diff --git a/src/northbridge/amd/amdfam10/debug.h b/src/northbridge/amd/amdfam10/debug.h deleted file mode 100644 index 01d87d96af..0000000000 --- a/src/northbridge/amd/amdfam10/debug.h +++ /dev/null @@ -1,45 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2016 Damien Zammit - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef AMDFAM10_DEBUG_H -#define AMDFAM10_DEBUG_H - -#include -#include "pci.h" - -void print_debug_addr(const char *str, void *val); -void print_debug_pci_dev(u32 dev); -void print_pci_devices(void); -void print_pci_devices_on_bus(u32 busn); -void dump_pci_device_range(u32 dev, u32 start_reg, u32 size); -void dump_pci_device(u32 dev); -void dump_pci_device_index_wait_range(u32 dev, u32 index_reg, u32 start, - u32 size); -void dump_pci_device_index_wait(u32 dev, u32 index_reg); -void dump_pci_device_index(u32 dev, u32 index_reg, u32 type, u32 length); -void dump_pci_devices(void); -void dump_pci_devices_on_bus(u32 busn); - -#if CONFIG(DEBUG_SMBUS) -void dump_spd_registers(const struct mem_controller *ctrl); -void dump_smbus_registers(void); -#endif - -void dump_io_resources(u32 port); - -void print_tx(const char *strval, u32 val); -void print_t(const char *strval); -void print_tf(const char *func, const char *strval); -#endif diff --git a/src/northbridge/amd/amdfam10/early_ht.c b/src/northbridge/amd/amdfam10/early_ht.c deleted file mode 100644 index dc0f6840e2..0000000000 --- a/src/northbridge/amd/amdfam10/early_ht.c +++ /dev/null @@ -1,176 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include "early_ht.h" -#include -#include -#include - -// For SB HT chain only -// mmconf is not ready yet -void set_bsp_node_CHtExtNodeCfgEn(void) -{ -#if CONFIG(EXT_RT_TBL_SUPPORT) - u32 dword; - dword = pci_io_read_config32(PCI_DEV(0, 0x18, 0), 0x68); - dword |= (1<<27) | (1<<25); - /* CHtExtNodeCfgEn: coherent link extended node configuration enable, - Nodes[31:0] will be 0xff:[31:0], Nodes[63:32] will be 0xfe:[31:0] - ---- 32 nodes now only - It can be used even nodes less than 8 nodes. - We can have 8 more device on bus 0 in that case - */ - - /* CHtExtAddrEn */ - pci_io_write_config32(PCI_DEV(0, 0x18, 0), 0x68, dword); - // CPU on bus 0xff and 0xfe now. For now on we can use CONFIG_CBB and CONFIG_CDB. -#endif -} - -void enumerate_ht_chain(void) -{ -#if CONFIG_HT_CHAIN_UNITID_BASE != 0 -/* CONFIG_HT_CHAIN_UNITID_BASE could be 0 (only one ht device in the ht chain), - if so, don't need to go through the chain */ - - /* Assumption the HT chain that is bus 0 has the HT I/O Hub on it. - * On most boards this just happens. If a CPU has multiple - * non Coherent links the appropriate bus registers for the - * links needs to be programed to point at bus 0. - */ - unsigned int next_unitid, last_unitid = 0; -#if CONFIG_HT_CHAIN_END_UNITID_BASE != 0x20 - // let't record the device of last ht device, So we can set the - // Unitid to CONFIG_HT_CHAIN_END_UNITID_BASE - unsigned int real_last_unitid = 0; - u8 real_last_pos = 0; - int ht_dev_num = 0; // except host_bridge - u8 end_used = 0; -#endif - - next_unitid = CONFIG_HT_CHAIN_UNITID_BASE; - do { - u32 id; - u8 hdr_type, pos; - last_unitid = next_unitid; - - id = pci_io_read_config32(PCI_DEV(0,0,0), PCI_VENDOR_ID); - /* If the chain is enumerated quit */ - if (((id & 0xffff) == 0x0000) || ((id & 0xffff) == 0xffff) || - (((id >> 16) & 0xffff) == 0xffff) || - (((id >> 16) & 0xffff) == 0x0000)) - { - break; - } - - hdr_type = pci_io_read_config8(PCI_DEV(0,0,0), PCI_HEADER_TYPE); - pos = 0; - hdr_type &= 0x7f; - - if ((hdr_type == PCI_HEADER_TYPE_NORMAL) || - (hdr_type == PCI_HEADER_TYPE_BRIDGE)) - { - pos = pci_io_read_config8(PCI_DEV(0,0,0), PCI_CAPABILITY_LIST); - } - while (pos != 0) { - u8 cap; - cap = pci_io_read_config8(PCI_DEV(0,0,0), pos + PCI_CAP_LIST_ID); - if (cap == PCI_CAP_ID_HT) { - u16 flags; - /* Read and write and reread flags so the link - * direction bit is valid. - */ - flags = pci_io_read_config16(PCI_DEV(0,0,0), pos + PCI_CAP_FLAGS); - pci_io_write_config16(PCI_DEV(0,0,0), pos + PCI_CAP_FLAGS, flags); - flags = pci_io_read_config16(PCI_DEV(0,0,0), pos + PCI_CAP_FLAGS); - if ((flags >> 13) == 0) { - unsigned int count; - unsigned int ctrl, ctrl_off; - pci_devfn_t devx; - -#if CONFIG_HT_CHAIN_END_UNITID_BASE != 0x20 - if (next_unitid >= 0x18) { - if (!end_used) { - next_unitid = CONFIG_HT_CHAIN_END_UNITID_BASE; - end_used = 1; - } else { - goto out; - } - } - real_last_unitid = next_unitid; - real_last_pos = pos; - ht_dev_num++; -#endif - #if !CONFIG_HT_CHAIN_END_UNITID_BASE - if (!next_unitid) - goto out; - #endif - flags &= ~0x1f; - flags |= next_unitid & 0x1f; - count = (flags >> 5) & 0x1f; - devx = PCI_DEV(0, next_unitid, 0); - next_unitid += count; - - pci_io_write_config16(PCI_DEV(0, 0, 0), pos + PCI_CAP_FLAGS, flags); - - /* Test for end of chain */ - ctrl_off = ((flags >> 10) & 1)? - PCI_HT_CAP_SLAVE_CTRL0 : PCI_HT_CAP_SLAVE_CTRL1; - - do { - ctrl = pci_io_read_config16(devx, pos + ctrl_off); - /* Is this the end of the hypertransport chain? */ - if (ctrl & (1 << 6)) { - goto out; - } - - if (ctrl & ((1 << 4) | (1 << 8))) { - /* - * Either the link has failed, or we have - * a CRC error. - * Sometimes this can happen due to link - * retrain, so lets knock it down and see - * if its transient - */ - ctrl |= ((1 << 4) | (1 <<8)); // Link fail + Crc - pci_io_write_config16(devx, pos + ctrl_off, ctrl); - ctrl = pci_io_read_config16(devx, pos + ctrl_off); - if (ctrl & ((1 << 4) | (1 << 8))) { - // can not clear the error - break; - } - } - } while ((ctrl & (1 << 5)) == 0); - - break; - } - } - pos = pci_io_read_config8(PCI_DEV(0, 0, 0), pos + PCI_CAP_LIST_NEXT); - } - } while (last_unitid != next_unitid); - -out: ; -#if CONFIG_HT_CHAIN_END_UNITID_BASE != 0x20 - if ((ht_dev_num > 1) && (real_last_unitid != CONFIG_HT_CHAIN_END_UNITID_BASE) && !end_used) { - u16 flags; - flags = pci_io_read_config16(PCI_DEV(0,real_last_unitid,0), real_last_pos + PCI_CAP_FLAGS); - flags &= ~0x1f; - flags |= CONFIG_HT_CHAIN_END_UNITID_BASE & 0x1f; - pci_io_write_config16(PCI_DEV(0, real_last_unitid, 0), real_last_pos + PCI_CAP_FLAGS, flags); - } -#endif - -#endif -} diff --git a/src/northbridge/amd/amdfam10/early_ht.h b/src/northbridge/amd/amdfam10/early_ht.h deleted file mode 100644 index 67476fd849..0000000000 --- a/src/northbridge/amd/amdfam10/early_ht.h +++ /dev/null @@ -1,21 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2016 Damien Zammit - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ -#ifndef EARLY_HT_H -#define EARLY_HT_H - -void set_bsp_node_CHtExtNodeCfgEn(void); -void enumerate_ht_chain(void); - -#endif diff --git a/src/northbridge/amd/amdfam10/get_pci1234.c b/src/northbridge/amd/amdfam10/get_pci1234.c deleted file mode 100644 index 94ec831d65..0000000000 --- a/src/northbridge/amd/amdfam10/get_pci1234.c +++ /dev/null @@ -1,132 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include - -#include - - -/* Need pci1234 array - * pci1234[0] will record sblink and bus range - * pci1234[i] will record ht chain i. - * It will keep the sequence when some ht io card is not installed. - * - * 1n: 8 - * 2n: 7x2 - * 3n: 6x3 - * 4n: 5x4 - * 5n: 4x5 - * 6n: 3x6 - * 7n: 2x7 - * 8n: 1x8 - * - * 8n(4x2): 8x4 - * 16n(4x4): 16*2 - * 20n(4x5): 20x1 - * 32n(4x4+4x4): 16x1 - * - * Total: xxx: I just want to use 32 instead, If you have more, you may need to - * reset HC_POSSIBLE_NUM and update ssdt.dsl (hcdn, hclk) - * - * Put all the possible ht node/link to the list tp pci1234[] in get_bus_conf.c - * on MB dir. How about co-processor on socket 1 on 2 way system. - * or socket 2, and socket3 on 4 way system? treat that as one hc too! - * - */ - -#include "northbridge.h" - -void get_pci1234(void) -{ - - int i,j; - u32 dword; - - dword = sysconf.sblk<<8; - dword |= 1; - sysconf.pci1234[0] = dword; // sblink - sysconf.hcid[0] = 0; - - /* about hardcode numbering for HT_IO support - set the node_id and link_id that could have ht chain in the one array, - then check if is enabled.... then update final value - */ - - //here we need to set hcdn - //1. hypertransport.c need to record hcdn_reg together with 0xe0, 0xe4, 0xe8, 0xec when are set - //2. so at the same time we need update hsdn with hcdn_reg here - - for (j = 0; j < sysconf.ht_c_num; j++) { - u32 dwordx; - dwordx = sysconf.ht_c_conf_bus[j]; - dwordx &=0xfffffffd; //keep bus num, node_id, link_num, enable bits - if ((dwordx & 0x7fd) == dword) { //SBLINK - sysconf.pci1234[0] = dwordx; - sysconf.hcdn[0] = sysconf.hcdn_reg[j]; - continue; - } - if ((dwordx & 1)) { - // We need to find out the number of HC - // for exact match - for (i = 1; i < sysconf.hc_possible_num; i++) { - if ((dwordx & 0x7fc) == (sysconf.pci1234[i] & 0x7fc)) { // same node and same linkn - sysconf.pci1234[i] = dwordx; - sysconf.hcdn[i] = sysconf.hcdn_reg[j]; - break; - } - } - // for 0xffc match or same node - for (i = 1; i < sysconf.hc_possible_num; i++) { - if ((dwordx & 0x7fc) == (dwordx & sysconf.pci1234[i] & 0x7fc)) { - sysconf.pci1234[i] = dwordx; - sysconf.hcdn[i] = sysconf.hcdn_reg[j]; - break; - } - } - } - } - - for (i = 1; i < sysconf.hc_possible_num; i++) { - if (!(sysconf.pci1234[i] & 1)) { - sysconf.pci1234[i] = 0; - sysconf.hcdn[i] = 0x20202020; - } - sysconf.hcid[i] = 0; - } -} - -void get_default_pci1234(int mb_hc_possible) -{ - int i; - - for (i = 0; i < mb_hc_possible; i++) { - sysconf.pci1234[i] = 0x0000ffc; - sysconf.hcdn[i] = 0x20202020; - } - sysconf.hc_possible_num = mb_hc_possible; - get_pci1234(); -} - -static void amd_bs_sysconf(void *arg) -{ - /* Prepare sysconf structures, which are used to generate IRQ, - * MP and ACPI table entries. - */ - get_bus_conf(); -} - -BOOT_STATE_INIT_ENTRY(BS_WRITE_TABLES, BS_ON_ENTRY, amd_bs_sysconf, NULL); diff --git a/src/northbridge/amd/amdfam10/ht_config.c b/src/northbridge/amd/amdfam10/ht_config.c deleted file mode 100644 index 8499dbb623..0000000000 --- a/src/northbridge/amd/amdfam10/ht_config.c +++ /dev/null @@ -1,229 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include -#include - -#include -#include "northbridge.h" -#include "amdfam10.h" -#include "ht_config.h" - -struct dram_base_mask_t get_dram_base_mask(u32 nodeid) -{ - struct dram_base_mask_t d; - struct device *dev = __f1_dev[0]; - - u32 temp; - temp = pci_read_config32(dev, 0x44 + (nodeid << 3)); //[39:24] at [31:16] - d.mask = ((temp & 0xfff80000)>>(8+3)); // mask out DramMask [26:24] too - temp = pci_read_config32(dev, 0x144 + (nodeid <<3)) & 0xff; //[47:40] at [7:0] - d.mask |= temp<<21; - - temp = pci_read_config32(dev, 0x40 + (nodeid << 3)); //[39:24] at [31:16] - d.mask |= (temp & 1); // enable bit - - d.base = ((temp & 0xfff80000)>>(8+3)); // mask out DramBase [26:24) too - temp = pci_read_config32(dev, 0x140 + (nodeid <<3)) & 0xff; //[47:40] at [7:0] - d.base |= temp<<21; - return d; -} - -void set_config_map_reg(struct bus *link) -{ - u32 tempreg; - u32 i; - u32 ht_c_index = get_ht_c_index(link); - u32 linkn = link->link_num & 0x0f; - u32 busn_min = (link->secondary >> sysconf.segbit) & 0xff; - u32 busn_max = (link->subordinate >> sysconf.segbit) & 0xff; - u32 nodeid = amdfam10_nodeid(link->dev); - - tempreg = ((nodeid & 0x30) << (12-4)) | ((nodeid & 0xf) << 4) | 3; - tempreg |= (busn_max << 24)|(busn_min << 16)|(linkn << 8); - - for (i = 0; i < sysconf.nodes; i++) { - struct device *dev = __f1_dev[i]; - pci_write_config32(dev, 0xe0 + ht_c_index * 4, tempreg); - } -} - -void clear_config_map_reg(struct bus *link) -{ - u32 i; - u32 ht_c_index = get_ht_c_index(link); - - for (i = 0; i < sysconf.nodes; i++) { - struct device *dev = __f1_dev[i]; - pci_write_config32(dev, 0xe0 + ht_c_index * 4, 0); - } -} - - -static u32 ht_c_key(struct bus *link) -{ - u32 nodeid = amdfam10_nodeid(link->dev); - u32 linkn = link->link_num & 0x0f; - u32 val = (linkn << 8) | ((nodeid & 0x3f) << 2) | 3; - return val; -} - -static u32 get_ht_c_index_by_key(u32 key, sys_info_conf_t *sysinfo) -{ - u32 ht_c_index = 0; - - for (ht_c_index = 0; ht_c_index < 32; ht_c_index++) { - if ((sysinfo->ht_c_conf_bus[ht_c_index] & 0xfff) == key) { - return ht_c_index; - } - } - - for (ht_c_index = 0; ht_c_index < 32; ht_c_index++) { - if (sysinfo->ht_c_conf_bus[ht_c_index] == 0) { - return ht_c_index; - } - } - - return -1; -} - -u32 get_ht_c_index(struct bus *link) -{ - u32 val = ht_c_key(link); - return get_ht_c_index_by_key(val, &sysconf); -} - -void store_ht_c_conf_bus(struct bus *link) -{ - u32 val = ht_c_key(link); - u32 ht_c_index = get_ht_c_index_by_key(val, &sysconf); - - u32 segn = (link->subordinate >> 8) & 0x0f; - u32 busn_min = link->secondary & 0xff; - u32 busn_max = link->subordinate & 0xff; - - val |= (segn << 28) | (busn_max << 20) | (busn_min << 12); - - sysconf.ht_c_conf_bus[ht_c_index] = val; - sysconf.hcdn_reg[ht_c_index] = link->hcdn_reg; - sysconf.ht_c_num++; -} - -u32 get_io_addr_index(u32 nodeid, u32 linkn) -{ - u32 index; - - for (index = 0; index < 256; index++) { - - if (index + 4 >= ARRAY_SIZE(sysconf.conf_io_addrx)) - die("Error! Out of bounds read in %s:%s\n", __FILE__, __func__); - - if (sysconf.conf_io_addrx[index+4] == 0) { - sysconf.conf_io_addr[index+4] = (nodeid & 0x3f); - sysconf.conf_io_addrx[index+4] = 1 | ((linkn & 0x7)<<4); - return index; - } - } - - return 0; -} - -u32 get_mmio_addr_index(u32 nodeid, u32 linkn) -{ - u32 index; - - for (index = 0; index < 64; index++) { - - if (index + 8 >= ARRAY_SIZE(sysconf.conf_mmio_addrx)) - die("Error! Out of bounds read in %s:%s\n", __FILE__, __func__); - - if (sysconf.conf_mmio_addrx[index+8] == 0) { - sysconf.conf_mmio_addr[index+8] = (nodeid & 0x3f); - sysconf.conf_mmio_addrx[index+8] = 1 | ((linkn & 0x7)<<4); - return index; - } - } - - return 0; -} - - -void store_conf_io_addr(u32 nodeid, u32 linkn, u32 reg, u32 index, - u32 io_min, u32 io_max) -{ - u32 val; - - /* io range allocation */ - index = (reg-0xc0)>>3; - - val = (nodeid & 0x3f); // 6 bits used - sysconf.conf_io_addr[index] = val | ((io_max<<8) & 0xfffff000); //limit : with nodeid - val = 3 | ((linkn & 0x7)<<4); // 8 bits used - sysconf.conf_io_addrx[index] = val | ((io_min<<8) & 0xfffff000); // base : with enable bit - - if (sysconf.io_addr_num < (index+1)) - sysconf.io_addr_num = index+1; -} - - -void store_conf_mmio_addr(u32 nodeid, u32 linkn, u32 reg, u32 index, - u32 mmio_min, u32 mmio_max) -{ - u32 val; - - /* io range allocation */ - index = (reg-0x80)>>3; - - val = (nodeid & 0x3f); // 6 bits used - sysconf.conf_mmio_addr[index] = val | (mmio_max & 0xffffff00); //limit : with nodeid and linkn - val = 3 | ((linkn & 0x7)<<4); // 8 bits used - sysconf.conf_mmio_addrx[index] = val | (mmio_min & 0xffffff00); // base : with enable bit - - if (sysconf.mmio_addr_num<(index+1)) - sysconf.mmio_addr_num = index+1; -} - - -void set_io_addr_reg(struct device *dev, u32 nodeid, u32 linkn, u32 reg, - u32 io_min, u32 io_max) -{ - u32 i; - u32 tempreg; - - /* io range allocation */ - tempreg = (nodeid&0xf) | ((nodeid & 0x30)<<(8-4)) | (linkn<<4) | ((io_max&0xf0)<<(12-4)); //limit - for (i = 0; i < sysconf.nodes; i++) - pci_write_config32(__f1_dev[i], reg+4, tempreg); - - tempreg = 3 /*| (3<<4)*/ | ((io_min&0xf0)<<(12-4)); //base :ISA and VGA ? - for (i = 0; i < sysconf.nodes; i++) - pci_write_config32(__f1_dev[i], reg, tempreg); -} - -void set_mmio_addr_reg(u32 nodeid, u32 linkn, u32 reg, u32 index, u32 mmio_min, u32 mmio_max, u32 nodes) -{ - u32 i; - u32 tempreg; - - /* io range allocation */ - tempreg = (nodeid&0xf) | (linkn<<4) | (mmio_max&0xffffff00); //limit - for (i = 0; i < nodes; i++) - pci_write_config32(__f1_dev[i], reg+4, tempreg); - tempreg = 3 | (nodeid & 0x30) | (mmio_min&0xffffff00); - for (i = 0; i < sysconf.nodes; i++) - pci_write_config32(__f1_dev[i], reg, tempreg); -} diff --git a/src/northbridge/amd/amdfam10/ht_config.h b/src/northbridge/amd/amdfam10/ht_config.h deleted file mode 100644 index 748a9818c1..0000000000 --- a/src/northbridge/amd/amdfam10/ht_config.h +++ /dev/null @@ -1,54 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef __AMDFAM10_HT_CONFIG_H__ -#define __AMDFAM10_HT_CONFIG_H__ - -typedef struct amdfam10_sysconf_t sys_info_conf_t; - -/* FIXME */ -u32 amdfam10_nodeid(struct device *dev); -extern struct device *__f1_dev[]; - -struct dram_base_mask_t { - u32 base; //[47:27] at [28:8] - u32 mask; //[47:27] at [28:8] and enable at bit 0 -}; - -struct dram_base_mask_t get_dram_base_mask(u32 nodeid); - -u32 get_ht_c_index(struct bus *link); -void store_ht_c_conf_bus(struct bus *link); - -void set_config_map_reg(struct bus *link); -void clear_config_map_reg(struct bus *link); - - -void store_conf_io_addr(u32 nodeid, u32 linkn, u32 reg, u32 index, - u32 io_min, u32 io_max); - -void store_conf_mmio_addr(u32 nodeid, u32 linkn, u32 reg, u32 index, - u32 mmio_min, u32 mmio_max); - - -u32 get_io_addr_index(u32 nodeid, u32 linkn); -u32 get_mmio_addr_index(u32 nodeid, u32 linkn); - -void set_io_addr_reg(struct device *dev, u32 nodeid, u32 linkn, u32 reg, - u32 io_min, u32 io_max); - -void set_mmio_addr_reg(u32 nodeid, u32 linkn, u32 reg, u32 index, u32 mmio_min, u32 mmio_max, u32 nodes); - -#endif diff --git a/src/northbridge/amd/amdfam10/inline_helper.c b/src/northbridge/amd/amdfam10/inline_helper.c deleted file mode 100644 index 7f260318f7..0000000000 --- a/src/northbridge/amd/amdfam10/inline_helper.c +++ /dev/null @@ -1,31 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2016 Damien Zammit - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include - -static inline uint8_t is_fam15h(void) -{ - uint8_t fam15h = 0; - uint32_t family; - - family = cpuid_eax(0x80000001); - family = ((family & 0xf00000) >> 16) | ((family & 0xf00) >> 8); - - if (family >= 0x6f) - /* Family 15h or later */ - fam15h = 1; - - return fam15h; -} diff --git a/src/northbridge/amd/amdfam10/link_control.c b/src/northbridge/amd/amdfam10/link_control.c deleted file mode 100644 index 384772374b..0000000000 --- a/src/northbridge/amd/amdfam10/link_control.c +++ /dev/null @@ -1,153 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2015 Timothy Pearson , Raptor Engineering - * Copyright (C) 2016 Damien Zammit - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -/* Configure various power control registers, including processor - * boost support. - */ - -#include -#include -#include -#include -#include -#include -#include -#include - -#include "amdfam10.h" - -static void nb_control_init(struct device *dev) -{ - uint8_t enable_c_states; - uint8_t enable_cc6; - uint32_t dword; - - printk(BIOS_DEBUG, "NB: Function 4 Link Control.. "); - - /* Configure L3 Power Control */ - dword = pci_read_config32(dev, 0x1c4); - dword |= (0x1 << 8); /* L3PwrSavEn = 1 */ - pci_write_config32(dev, 0x1c4, dword); - - if (is_fam15h()) { - /* Configure L3 Control 2 */ - dword = pci_read_config32(dev, 0x1cc); - dword &= ~(0x7 << 6); /* ImplRdProjDelayThresh = 0x2 */ - dword |= (0x2 << 6); - pci_write_config32(dev, 0x1cc, dword); - - /* Configure TDP Accumulator Divisor Control */ - dword = pci_read_config32(dev, 0x104); - dword &= ~(0xfff << 2); /* TdpAccDivRate = 0xc8 */ - dword |= (0xc8 << 2); - dword &= ~0x3; /* TdpAccDivVal = 0x1 */ - dword |= 0x1; - pci_write_config32(dev, 0x104, dword); - - /* Configure Sample and Residency Timers */ - dword = pci_read_config32(dev, 0x110); - dword &= ~0xfff; /* CSampleTimer = 0x1 */ - dword |= 0x1; - pci_write_config32(dev, 0x110, dword); - - /* Configure APM TDP Control */ - dword = pci_read_config32(dev, 0x16c); - dword |= (0x1 << 4); /* ApmTdpLimitIntEn = 1 */ - pci_write_config32(dev, 0x16c, dword); - - /* Enable APM */ - dword = pci_read_config32(dev, 0x15c); - dword |= (0x1 << 7); /* ApmMasterEn = 1 */ - pci_write_config32(dev, 0x15c, dword); - - enable_c_states = 0; - enable_cc6 = 0; -#if CONFIG(HAVE_ACPI_TABLES) - uint8_t nvram; - - if (get_option(&nvram, "cpu_c_states") == CB_SUCCESS) - enable_c_states = !!nvram; - - if (get_option(&nvram, "cpu_cc6_state") == CB_SUCCESS) - enable_cc6 = !!nvram; -#endif - - if (enable_c_states) { - /* Configure C-state Control 1 */ - dword = pci_read_config32(dev, 0x118); - dword |= (0x1 << 24); /* PwrGateEnCstAct1 = 1 */ - dword &= ~(0x7 << 21); /* ClkDivisorCstAct1 = 0x0 */ - dword &= ~(0x3 << 18); /* CacheFlushTmrSelCstAct1 = 0x1 */ - dword |= (0x1 << 18); - dword |= (0x1 << 17); /* CacheFlushEnCstAct1 = 1 */ - dword |= (0x1 << 16); /* CpuPrbEnCstAct1 = 1 */ - dword &= ~(0x1 << 8); /* PwrGateEnCstAct0 = 0 */ - dword &= ~(0x7 << 5); /* ClkDivisorCstAct0 = 0x0 */ - dword &= ~(0x3 << 2); /* CacheFlushTmrSelCstAct0 = 0x2 */ - dword |= (0x2 << 2); - dword |= (0x1 << 1); /* CacheFlushEnCstAct0 = 1 */ - dword |= 0x1; /* CpuPrbEnCstAct0 = 1 */ - pci_write_config32(dev, 0x118, dword); - - /* Configure C-state Control 2 */ - dword = pci_read_config32(dev, 0x11c); - dword &= ~(0x1 << 8); /* PwrGateEnCstAct2 = 0 */ - dword &= ~(0x7 << 5); /* ClkDivisorCstAct2 = 0x0 */ - dword &= ~(0x3 << 2); /* CacheFlushTmrSelCstAct0 = 0x0 */ - dword &= ~(0x1 << 1); /* CacheFlushEnCstAct0 = 0 */ - dword &= ~(0x1); /* CpuPrbEnCstAct0 = 0 */ - pci_write_config32(dev, 0x11c, dword); - - /* Configure C-state Policy Control 1 */ - dword = pci_read_config32(dev, 0x128); - dword &= ~(0x7f << 5); /* CacheFlushTmr = 0x28 */ - dword |= (0x28 << 5); - dword &= ~0x1; /* CoreCstateMode = !enable_cc6 */ - dword |= ((enable_cc6)?0:1); - pci_write_config32(dev, 0x128, dword); - } - } - - printk(BIOS_DEBUG, "done.\n"); -} - - -static struct device_operations mcf4_ops = { - .read_resources = pci_dev_read_resources, - .set_resources = pci_dev_set_resources, - .enable_resources = pci_dev_enable_resources, - .init = nb_control_init, - .scan_bus = 0, - .ops_pci = 0, -}; - -static const struct pci_driver mcf4_driver_fam10 __pci_driver = { - .ops = &mcf4_ops, - .vendor = PCI_VENDOR_ID_AMD, - .device = 0x1204, -}; - -static const struct pci_driver mcf4_driver_fam15_model10 __pci_driver = { - .ops = &mcf4_ops, - .vendor = PCI_VENDOR_ID_AMD, - .device = 0x1404, -}; - -static const struct pci_driver mcf4_driver_fam15 __pci_driver = { - .ops = &mcf4_ops, - .vendor = PCI_VENDOR_ID_AMD, - .device = 0x1604, -}; diff --git a/src/northbridge/amd/amdfam10/misc_control.c b/src/northbridge/amd/amdfam10/misc_control.c deleted file mode 100644 index b0a1ab679a..0000000000 --- a/src/northbridge/amd/amdfam10/misc_control.c +++ /dev/null @@ -1,261 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2003 by Eric Biederman - * Copyright (C) Stefan Reinauer - * Copyright (C) 2007 Advanced Micro Devices, Inc. - * Copyright (C) 2015 Timothy Pearson , Raptor Engineering - * Copyright (C) 2016 Damien Zammit - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -/* Turn off machine check triggers when reading - * pci space where there are no devices. - * This is necessary when scanning the bus for - * devices which is done by the kernel - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include "amdfam10.h" - -/** - * @brief Read resources for AGP aperture - * - * @param dev - * - * There is only one AGP aperture resource needed. The resource is added to - * the northbridge of BSP. - * - * The same trick can be used to augment legacy VGA resources which can - * be detect by generic pci reousrce allocator for VGA devices. - * BAD: it is more tricky than I think, the resource allocation code is - * implemented in a way to NOT DOING legacy VGA resource allocation on - * purpose :-(. - */ -static void mcf3_read_resources(struct device *dev) -{ - struct resource *resource; - unsigned char gart; - /* Read the generic PCI resources */ - pci_dev_read_resources(dev); - - /* If we are not the first processor don't allocate the gart apeture */ - if (dev->path.pci.devfn != PCI_DEVFN(CONFIG_CDB, 3)) { - return; - } - - gart = 1; - get_option(&gart, "gart"); - - if (gart) { - /* Add a Gart apeture resource */ - resource = new_resource(dev, 0x94); - resource->size = CONFIG_AGP_APERTURE_SIZE; - resource->align = log2(resource->size); - resource->gran = log2(resource->size); - resource->limit = 0xffffffff; /* 4G */ - resource->flags = IORESOURCE_MEM; - } -} - -static void set_agp_aperture(struct device *dev, uint32_t pci_id) -{ - uint32_t dword; - struct resource *resource; - - resource = probe_resource(dev, 0x94); - if (resource) { - struct device *pdev; - u32 gart_base, gart_acr; - - /* Remember this resource has been stored */ - resource->flags |= IORESOURCE_STORED; - - /* Find the size of the GART aperture */ - gart_acr = (0<<6)|(0<<5)|(0<<4)|((resource->gran - 25) << 1)|(0<<0); - - /* Get the base address */ - gart_base = ((resource->base) >> 25) & 0x00007fff; - - /* Update the other northbriges */ - pdev = 0; - while ((pdev = dev_find_device(PCI_VENDOR_ID_AMD, pci_id, pdev))) { - /* Store the GART size but don't enable it */ - pci_write_config32(pdev, 0x90, gart_acr); - - /* Store the GART base address */ - pci_write_config32(pdev, 0x94, gart_base); - - /* Don't set the GART Table base address */ - pci_write_config32(pdev, 0x98, 0); - - /* Report the resource has been stored... */ - report_resource_stored(pdev, resource, " "); - - /* Errata 540 workaround */ - dword = pci_read_config32(pdev, 0x90); - dword |= 0x1 << 6; /* DisGartTblWlkPrb = 0x1 */ - pci_write_config32(pdev, 0x90, dword); - } - } -} - -static void mcf3_set_resources_fam10h(struct device *dev) -{ - /* Set the gart aperture */ - set_agp_aperture(dev, 0x1203); - - /* Set the generic PCI resources */ - pci_dev_set_resources(dev); -} - -static void mcf3_set_resources_fam15h_model10(struct device *dev) -{ - /* Set the gart aperture */ - set_agp_aperture(dev, 0x1403); - - /* Set the generic PCI resources */ - pci_dev_set_resources(dev); -} - -static void mcf3_set_resources_fam15h(struct device *dev) -{ - /* Set the gart aperture */ - set_agp_aperture(dev, 0x1603); - - /* Set the generic PCI resources */ - pci_dev_set_resources(dev); -} - -static void misc_control_init(struct device *dev) -{ - uint32_t dword; - uint8_t nvram; - uint8_t boost_limit; - uint8_t current_boost; - - printk(BIOS_DEBUG, "NB: Function 3 Misc Control.. "); - -#if CONFIG(DIMM_DDR3) && !CONFIG(NORTHBRIDGE_AMD_AGESA) - uint8_t node; - uint8_t slot; - uint8_t dimm_present; - - /* Restore DRAM MCA registers */ - struct amdmct_memory_info *mem_info; - mem_info = cbmem_find(CBMEM_ID_AMDMCT_MEMINFO); - if (mem_info) { - node = PCI_SLOT(dev->path.pci.devfn) - 0x18; - - /* Check node for installed DIMMs */ - dimm_present = 0; - - /* Check all slots for installed DIMMs */ - for (slot = 0; slot < MAX_DIMMS_SUPPORTED; slot++) { - if (mem_info->dct_stat[node].DIMMPresent & (1 << slot)) { - dimm_present = 1; - break; - } - } - - if (dimm_present) { - uint32_t mc4_status_high = pci_read_config32(dev, 0x4c); - uint32_t mc4_status_low = pci_read_config32(dev, 0x48); - if ((mc4_status_high & (0x1 << 31)) && (mc4_status_high != 0xffffffff)) { - printk(BIOS_WARNING, "\nWARNING: MC4 Machine Check Exception detected on node %d!\n" - "Signature: %08x%08x\n", node, mc4_status_high, mc4_status_low); - } - - /* Clear MC4 error status */ - pci_write_config32(dev, 0x48, 0x0); - pci_write_config32(dev, 0x4c, 0x0); - } - } -#endif - - /* Disable Machine checks from Invalid Locations. - * This is needed for PC backwards compatibility. - */ - dword = pci_read_config32(dev, 0x44); - dword |= (1<<6) | (1<<25); - pci_write_config32(dev, 0x44, dword); - - boost_limit = 0xf; - if (get_option(&nvram, "maximum_p_state_limit") == CB_SUCCESS) - boost_limit = nvram & 0xf; - - /* Set P-state maximum value */ - dword = pci_read_config32(dev, 0xdc); - current_boost = (dword >> 8) & 0x7; - if (boost_limit > current_boost) - boost_limit = current_boost; - dword &= ~(0x7 << 8); - dword |= (boost_limit & 0x7) << 8; - pci_write_config32(dev, 0xdc, dword); - - printk(BIOS_DEBUG, "done.\n"); -} - - -static struct device_operations mcf3_ops_fam10h = { - .read_resources = mcf3_read_resources, - .set_resources = mcf3_set_resources_fam10h, - .enable_resources = pci_dev_enable_resources, - .init = misc_control_init, - .scan_bus = 0, - .ops_pci = 0, -}; - -static struct device_operations mcf3_ops_fam15h_model10 = { - .read_resources = mcf3_read_resources, - .set_resources = mcf3_set_resources_fam15h_model10, - .enable_resources = pci_dev_enable_resources, - .init = misc_control_init, - .scan_bus = 0, - .ops_pci = 0, -}; - -static struct device_operations mcf3_ops_fam15h = { - .read_resources = mcf3_read_resources, - .set_resources = mcf3_set_resources_fam15h, - .enable_resources = pci_dev_enable_resources, - .init = misc_control_init, - .scan_bus = 0, - .ops_pci = 0, -}; - -static const struct pci_driver mcf3_driver __pci_driver = { - .ops = &mcf3_ops_fam10h, - .vendor = PCI_VENDOR_ID_AMD, - .device = 0x1203, -}; - -static const struct pci_driver mcf3_driver_fam15_model10 __pci_driver = { - .ops = &mcf3_ops_fam15h_model10, - .vendor = PCI_VENDOR_ID_AMD, - .device = 0x1403, -}; - -static const struct pci_driver mcf3_driver_fam15 __pci_driver = { - .ops = &mcf3_ops_fam15h, - .vendor = PCI_VENDOR_ID_AMD, - .device = 0x1603, -}; diff --git a/src/northbridge/amd/amdfam10/nb_control.c b/src/northbridge/amd/amdfam10/nb_control.c deleted file mode 100644 index a9bdb18415..0000000000 --- a/src/northbridge/amd/amdfam10/nb_control.c +++ /dev/null @@ -1,85 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2015 Timothy Pearson , Raptor Engineering - * Copyright (C) 2016 Damien Zammit - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -/* Configure various power control registers, including processor boost - * and TDP monitoring support. - */ - -#include -#include -#include -#include -#include -#include - -#include "amdfam10.h" - -static void nb_control_init(struct device *dev) -{ - uint32_t dword; - uint32_t f5x80; - uint8_t cu_enabled; - uint8_t compute_unit_count = 0; - - printk(BIOS_DEBUG, "NB: Function 5 Northbridge Control.. "); - - /* Determine the number of active compute units on this node */ - f5x80 = pci_read_config32(dev, 0x80); - cu_enabled = f5x80 & 0xf; - if (cu_enabled == 0x1) - compute_unit_count = 1; - if (cu_enabled == 0x3) - compute_unit_count = 2; - if (cu_enabled == 0x7) - compute_unit_count = 3; - if (cu_enabled == 0xf) - compute_unit_count = 4; - - /* Configure Processor TDP Running Average */ - dword = pci_read_config32(dev, 0xe0); - dword &= ~0xf; /* RunAvgRange = 0x9 */ - dword |= 0x9; - pci_write_config32(dev, 0xe0, dword); - - /* Configure northbridge P-states */ - dword = pci_read_config32(dev, 0x170); - dword &= ~(0x7 << 9); /* NbPstateThreshold = compute_unit_count */ - dword |= (compute_unit_count & 0x7) << 9; - pci_write_config32(dev, 0x170, dword); - - printk(BIOS_DEBUG, "done.\n"); -} - -static struct device_operations mcf5_ops = { - .read_resources = pci_dev_read_resources, - .set_resources = pci_dev_set_resources, - .enable_resources = pci_dev_enable_resources, - .init = nb_control_init, - .scan_bus = 0, - .ops_pci = 0, -}; - -static const struct pci_driver mcf5_driver_fam15_model10 __pci_driver = { - .ops = &mcf5_ops, - .vendor = PCI_VENDOR_ID_AMD, - .device = 0x1405, -}; - -static const struct pci_driver mcf5_driver_fam15 __pci_driver = { - .ops = &mcf5_ops, - .vendor = PCI_VENDOR_ID_AMD, - .device = 0x1605, -}; diff --git a/src/northbridge/amd/amdfam10/northbridge.c b/src/northbridge/amd/amdfam10/northbridge.c deleted file mode 100644 index df1d947cdb..0000000000 --- a/src/northbridge/amd/amdfam10/northbridge.c +++ /dev/null @@ -1,1928 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2016 Damien Zammit - * Copyright (C) 2015 - 2017 Timothy Pearson , Raptor Engineering - * Copyright (C) 2007 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#if CONFIG(LOGICAL_CPUS) -#include -#include -#endif - -#include "northbridge.h" -#include "amdfam10.h" -#include "ht_config.h" -#include "chip.h" - -#if CONFIG_HW_MEM_HOLE_SIZEK != 0 -#include -#endif - -#if CONFIG(DIMM_DDR3) -#include "../amdmct/mct_ddr3/s3utils.h" -#endif - -struct amdfam10_sysconf_t sysconf; -u8 pirq_router_bus; - -#define FX_DEVS NODE_NUMS -static struct device *__f0_dev[FX_DEVS]; -struct device *__f1_dev[FX_DEVS]; -static struct device *__f2_dev[FX_DEVS]; -static struct device *__f4_dev[FX_DEVS]; -static unsigned int fx_devs = 0; - -struct device *get_node_pci(u32 nodeid, u32 fn) -{ -#if NODE_NUMS + CONFIG_CDB >= 32 - if ((CONFIG_CDB + nodeid) < 32) { - return dev_find_slot(CONFIG_CBB, PCI_DEVFN(CONFIG_CDB + nodeid, fn)); - } else { - return dev_find_slot(CONFIG_CBB-1, PCI_DEVFN(CONFIG_CDB + nodeid - 32, fn)); - } - -#else - return dev_find_slot(CONFIG_CBB, PCI_DEVFN(CONFIG_CDB + nodeid, fn)); -#endif -} - -static void get_fx_devs(void) -{ - int i; - for (i = 0; i < FX_DEVS; i++) { - __f0_dev[i] = get_node_pci(i, 0); - __f1_dev[i] = get_node_pci(i, 1); - __f2_dev[i] = get_node_pci(i, 2); - __f4_dev[i] = get_node_pci(i, 4); - if (__f0_dev[i] != NULL && __f1_dev[i] != NULL) - fx_devs = i+1; - } - if (__f1_dev[0] == NULL || __f0_dev[0] == NULL || fx_devs == 0) { - die("Cannot find 0:0x18.[0|1]\n"); - } -} - -static u32 f1_read_config32(unsigned int reg) -{ - if (fx_devs == 0) - get_fx_devs(); - return pci_read_config32(__f1_dev[0], reg); -} - -static void f1_write_config32(unsigned int reg, u32 value) -{ - int i; - if (fx_devs == 0) - get_fx_devs(); - for (i = 0; i < fx_devs; i++) { - struct device *dev; - dev = __f1_dev[i]; - if (dev && dev->enabled) { - pci_write_config32(dev, reg, value); - } - } -} - -u32 amdfam10_nodeid(struct device *dev) -{ -#if NODE_NUMS == 64 - unsigned int busn; - busn = dev->bus->secondary; - if (busn != CONFIG_CBB) { - return (dev->path.pci.devfn >> 3) - CONFIG_CDB + 32; - } else { - return (dev->path.pci.devfn >> 3) - CONFIG_CDB; - } - -#else - return (dev->path.pci.devfn >> 3) - CONFIG_CDB; -#endif -} - -static void set_vga_enable_reg(u32 nodeid, u32 linkn) -{ - u32 val; - - val = 1 | (nodeid<<4) | (linkn<<12); - /* it will routing (1)mmio 0xa0000:0xbffff (2) io 0x3b0:0x3bb, - 0x3c0:0x3df */ - f1_write_config32(0xf4, val); - -} - -typedef enum { - HT_ROUTE_CLOSE, - HT_ROUTE_SCAN, - HT_ROUTE_FINAL, -} scan_state; - -static void ht_route_link(struct bus *link, scan_state mode) -{ - struct bus *parent = link->dev->bus; - u32 busses; - - if (mode == HT_ROUTE_SCAN) { - if (parent->subordinate == 0) - link->secondary = 0; - else - link->secondary = parent->subordinate + 1; - - link->subordinate = link->secondary; - } - - /* Configure the bus numbers for this bridge: the configuration - * transactions will not be propagated by the bridge if it is - * not correctly configured - */ - busses = pci_read_config32(link->dev, link->cap + 0x14); - busses &= ~(0xff << 8); - busses |= parent->secondary & 0xff; - if (mode == HT_ROUTE_CLOSE) - busses |= 0xff << 8; - else if (mode == HT_ROUTE_SCAN) - busses |= ((u32) link->secondary & 0xff) << 8; - else if (mode == HT_ROUTE_FINAL) - busses |= ((u32) link->secondary & 0xff) << 8; - pci_write_config32(link->dev, link->cap + 0x14, busses); - - if (mode == HT_ROUTE_FINAL) { - if (CONFIG(HT_CHAIN_DISTRIBUTE)) - parent->subordinate = ALIGN_UP(link->subordinate, 8) - 1; - else - parent->subordinate = link->subordinate; - } -} - -static void amd_g34_fixup(struct bus *link, struct device *dev) -{ - uint32_t nodeid = amdfam10_nodeid(dev); - uint8_t rev_gte_d = 0; - uint8_t dual_node = 0; - uint32_t f3xe8; - - if (cpuid_eax(0x80000001) >= 0x8) - /* Revision D or later */ - rev_gte_d = 1; - - if (rev_gte_d || is_fam15h()) { - f3xe8 = pci_read_config32(get_node_pci(0, 3), 0xe8); - - /* Check for dual node capability */ - if (f3xe8 & 0x20000000) - dual_node = 1; - - if (dual_node) { - /* Each G34 processor contains a defective HT link. - * See the BKDG Rev 3.62 section 2.7.1.5 for details. - */ - f3xe8 = pci_read_config32(get_node_pci(nodeid, 3), 0xe8); - uint8_t internal_node_number = ((f3xe8 & 0xc0000000) >> 30); - if (internal_node_number == 0) { - /* Node 0 */ - if (link->link_num == 6) /* Link 2 Sublink 1 */ - printk(BIOS_DEBUG, "amdfam10_scan_chain(): node %d (internal node ID %d): skipping defective HT link\n", nodeid, internal_node_number); - } else { - /* Node 1 */ - if (link->link_num == 5) /* Link 1 Sublink 1 */ - printk(BIOS_DEBUG, "amdfam10_scan_chain(): node %d (internal node ID %d): skipping defective HT link\n", nodeid, internal_node_number); - } - } - } -} - -static void amdfam10_scan_chain(struct bus *link) -{ - unsigned int next_unitid; - - /* See if there is an available configuration space mapping - * register in function 1. - */ - if (get_ht_c_index(link) >= 4) - return; - - /* Set up the primary, secondary and subordinate bus numbers. - * We have no idea how many busses are behind this bridge yet, - * so we set the subordinate bus number to 0xff for the moment. - */ - - ht_route_link(link, HT_ROUTE_SCAN); - - /* set the config map space */ - set_config_map_reg(link); - - /* Now we can scan all of the subordinate busses i.e. the - * chain on the hypertranport link - */ - - next_unitid = hypertransport_scan_chain(link); - - /* Now that nothing is overlapping it is safe to scan the children. */ - pci_scan_bus(link, 0x00, ((next_unitid - 1) << 3) | 7); - - ht_route_link(link, HT_ROUTE_FINAL); - - /* We know the number of busses behind this bridge. Set the - * subordinate bus number to it's real value - */ - if (0) { - /* Clear the extend reg. */ - clear_config_map_reg(link); - } - - set_config_map_reg(link); - - store_ht_c_conf_bus(link); -} - -/* Do sb ht chain at first, in case s2885 put sb chain - * (8131/8111) on link2, but put 8151 on link0. - */ -static void relocate_sb_ht_chain(void) -{ - struct device *dev; - struct bus *link, *prev = NULL; - u8 sblink; - - dev = dev_find_slot(CONFIG_CBB, PCI_DEVFN(CONFIG_CDB, 0)); - sblink = (pci_read_config32(dev, 0x64)>>8) & 7; - link = dev->link_list; - - while (link) { - if (link->link_num == sblink) { - if (!prev) - return; - prev->next = link->next; - link->next = dev->link_list; - dev->link_list = link; - return; - } - prev = link; - link = link->next; - } -} - -static void trim_ht_chain(struct device *dev) -{ - struct bus *link; - - /* Check for connected link. */ - for (link = dev->link_list; link; link = link->next) { - link->cap = 0x80 + (link->link_num * 0x20); - link->ht_link_up = ht_is_non_coherent_link(link); - } -} - -static void amdfam10_scan_chains(struct device *dev) -{ - struct bus *link; - -#if CONFIG(CPU_AMD_SOCKET_G34_NON_AGESA) - if (is_fam15h()) { - uint8_t current_link_number = 0; - - for (link = dev->link_list; link; link = link->next) { - /* The following links have changed position in Fam15h G34 processors: - * Fam10 Fam15 - * Node 0 - * L3 --> L1 - * L0 --> L3 - * L1 --> L2 - * L2 --> L0 - * Node 1 - * L0 --> L0 - * L1 --> L3 - * L2 --> L1 - * L3 --> L2 - */ - if (link->link_num == 0) - link->link_num = 3; - else if (link->link_num == 1) - link->link_num = 2; - else if (link->link_num == 2) - link->link_num = 0; - else if (link->link_num == 3) - link->link_num = 1; - else if (link->link_num == 5) - link->link_num = 7; - else if (link->link_num == 6) - link->link_num = 5; - else if (link->link_num == 7) - link->link_num = 6; - - current_link_number++; - if (current_link_number > 3) - current_link_number = 0; - } - } -#endif - - /* Do sb ht chain at first, in case s2885 put sb chain (8131/8111) on link2, but put 8151 on link0 */ - trim_ht_chain(dev); - - for (link = dev->link_list; link; link = link->next) { - if (link->ht_link_up) { - if (CONFIG(CPU_AMD_MODEL_10XXX)) - amd_g34_fixup(link, dev); - amdfam10_scan_chain(link); - } - } -} - - -static int reg_useable(unsigned int reg, struct device *goal_dev, unsigned int goal_nodeid, - unsigned int goal_link) -{ - struct resource *res; - unsigned int nodeid, link = 0; - int result; - res = 0; - for (nodeid = 0; !res && (nodeid < fx_devs); nodeid++) { - struct device *dev; - dev = __f0_dev[nodeid]; - if (!dev) - continue; - for (link = 0; !res && (link < 8); link++) { - res = probe_resource(dev, IOINDEX(0x1000 + reg, link)); - } - } - result = 2; - if (res) { - result = 0; - if ( (goal_link == (link - 1)) && - (goal_nodeid == (nodeid - 1)) && - (res->flags <= 1)) { - result = 1; - } - } - return result; -} - -static struct resource *amdfam10_find_iopair(struct device *dev, unsigned int nodeid, unsigned int link) -{ - struct resource *resource; - u32 free_reg, reg; - resource = 0; - free_reg = 0; - for (reg = 0xc0; reg <= 0xd8; reg += 0x8) { - int result; - result = reg_useable(reg, dev, nodeid, link); - if (result == 1) { - /* I have been allocated this one */ - break; - } else if (result > 1) { - /* I have a free register pair */ - free_reg = reg; - } - } - if (reg > 0xd8) { - reg = free_reg; // if no free, the free_reg still be 0 - } - - //Ext conf space - if (!reg) { - //because of Extend conf space, we will never run out of reg, but we need one index to differ them. so same node and same link can have multi range - u32 index = get_io_addr_index(nodeid, link); - reg = 0x110+ (index<<24) + (4<<20); // index could be 0, 255 - } - - resource = new_resource(dev, IOINDEX(0x1000 + reg, link)); - - return resource; -} - -static struct resource *amdfam10_find_mempair(struct device *dev, u32 nodeid, u32 link) -{ - struct resource *resource; - u32 free_reg, reg; - resource = 0; - free_reg = 0; - for (reg = 0x80; reg <= 0xb8; reg += 0x8) { - int result; - result = reg_useable(reg, dev, nodeid, link); - if (result == 1) { - /* I have been allocated this one */ - break; - } else if (result > 1) { - /* I have a free register pair */ - free_reg = reg; - } - } - if (reg > 0xb8) { - reg = free_reg; - } - - //Ext conf space - if (!reg) { - //because of Extend conf space, we will never run out of reg, - // but we need one index to differ them. so same node and - // same link can have multi range - u32 index = get_mmio_addr_index(nodeid, link); - reg = 0x110+ (index<<24) + (6<<20); // index could be 0, 63 - - } - resource = new_resource(dev, IOINDEX(0x1000 + reg, link)); - return resource; -} - - -static void amdfam10_link_read_bases(struct device *dev, u32 nodeid, u32 link) -{ - struct resource *resource; - - /* Initialize the io space constraints on the current bus */ - resource = amdfam10_find_iopair(dev, nodeid, link); - if (resource) { - u32 align; - align = log2(HT_IO_HOST_ALIGN); - resource->base = 0; - resource->size = 0; - resource->align = align; - resource->gran = align; - resource->limit = 0xffffUL; - resource->flags = IORESOURCE_IO | IORESOURCE_BRIDGE; - } - - /* Initialize the prefetchable memory constraints on the current bus */ - resource = amdfam10_find_mempair(dev, nodeid, link); - if (resource) { - resource->base = 0; - resource->size = 0; - resource->align = log2(HT_MEM_HOST_ALIGN); - resource->gran = log2(HT_MEM_HOST_ALIGN); - resource->limit = 0xffffffffffULL; - resource->flags = IORESOURCE_MEM | IORESOURCE_PREFETCH; - resource->flags |= IORESOURCE_BRIDGE; - } - - /* Initialize the memory constraints on the current bus */ - resource = amdfam10_find_mempair(dev, nodeid, link); - if (resource) { - resource->base = 0; - resource->size = 0; - resource->align = log2(HT_MEM_HOST_ALIGN); - resource->gran = log2(HT_MEM_HOST_ALIGN); - resource->limit = 0xffffffffffULL; - resource->flags = IORESOURCE_MEM | IORESOURCE_BRIDGE; - } -} - -static void amdfam10_read_resources(struct device *dev) -{ - u32 nodeid; - struct bus *link; - nodeid = amdfam10_nodeid(dev); - for (link = dev->link_list; link; link = link->next) { - if (link->children) { - amdfam10_link_read_bases(dev, nodeid, link->link_num); - } - } -} - -static void amdfam10_set_resource(struct device *dev, struct resource *resource, - u32 nodeid) -{ - resource_t rbase, rend; - unsigned int reg, link_num; - char buf[50]; - - /* Make certain the resource has actually been set */ - if (!(resource->flags & IORESOURCE_ASSIGNED)) { - return; - } - - /* If I have already stored this resource don't worry about it */ - if (resource->flags & IORESOURCE_STORED) { - return; - } - - /* Only handle PCI memory and IO resources */ - if (!(resource->flags & (IORESOURCE_MEM | IORESOURCE_IO))) - return; - - /* Ensure I am actually looking at a resource of function 1 */ - if ((resource->index & 0xffff) < 0x1000) { - return; - } - /* Get the base address */ - rbase = resource->base; - - /* Get the limit (rounded up) */ - rend = resource_end(resource); - - /* Get the register and link */ - reg = resource->index & 0xfff; // 4k - link_num = IOINDEX_LINK(resource->index); - - if (resource->flags & IORESOURCE_IO) { - - set_io_addr_reg(dev, nodeid, link_num, reg, rbase>>8, rend>>8); - store_conf_io_addr(nodeid, link_num, reg, (resource->index >> 24), rbase>>8, rend>>8); - } else if (resource->flags & IORESOURCE_MEM) { - set_mmio_addr_reg(nodeid, link_num, reg, (resource->index >>24), rbase>>8, rend>>8, sysconf.nodes); // [39:8] - store_conf_mmio_addr(nodeid, link_num, reg, (resource->index >>24), rbase>>8, rend>>8); - } - resource->flags |= IORESOURCE_STORED; - snprintf(buf, sizeof(buf), " ", - nodeid, link_num); - report_resource_stored(dev, resource, buf); -} - -/** - * I tried to reuse the resource allocation code in amdfam10_set_resource() - * but it is too difficult to deal with the resource allocation magic. - */ - -static void amdfam10_create_vga_resource(struct device *dev, unsigned int nodeid) -{ - struct bus *link; - struct resource *res; - - /* find out which link the VGA card is connected, - * we only deal with the 'first' vga card */ - for (link = dev->link_list; link; link = link->next) { - if (link->bridge_ctrl & PCI_BRIDGE_CTL_VGA) { -#if CONFIG(MULTIPLE_VGA_ADAPTERS) - extern struct device *vga_pri; // the primary vga device, defined in device.c - printk(BIOS_DEBUG, "VGA: vga_pri bus num = %d bus range [%d,%d]\n", vga_pri->bus->secondary, - link->secondary,link->subordinate); - /* We need to make sure the vga_pri is under the link */ - if ((vga_pri->bus->secondary >= link->secondary) && - (vga_pri->bus->secondary <= link->subordinate)) -#endif - break; - } - } - - /* no VGA card installed */ - if (link == NULL) - return; - - printk(BIOS_DEBUG, "VGA: %s (aka node %d) link %d has VGA device\n", dev_path(dev), nodeid, link->link_num); - set_vga_enable_reg(nodeid, link->link_num); - - /* Redirect VGA memory access to MMIO - * This signals the Family 10h resource parser - * to add a new MMIO mapping to the Range 11 - * MMIO control registers (starting at F1x1B8), - * and also reserves the resource in the E820 map. - */ - res = new_resource(dev, IOINDEX(0x1000 + 0x1b8, link->link_num)); - res->base = 0xa0000; - res->size = 0x20000; - res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; - amdfam10_set_resource(dev, res, nodeid); -} - -static void amdfam10_set_resources(struct device *dev) -{ - unsigned int nodeid; - struct bus *bus; - struct resource *res; - - /* Find the nodeid */ - nodeid = amdfam10_nodeid(dev); - - amdfam10_create_vga_resource(dev, nodeid); - - /* Set each resource we have found */ - for (res = dev->resource_list; res; res = res->next) { - amdfam10_set_resource(dev, res, nodeid); - } - - for (bus = dev->link_list; bus; bus = bus->next) { - if (bus->children) { - assign_resources(bus); - } - } -} - -static void mcf0_control_init(struct device *dev) -{ -} - -#if CONFIG(HAVE_ACPI_TABLES) -static const char *amdfam10_northbridge_acpi_name(const struct device *dev) -{ - return ""; -} -#endif - -static struct device_operations northbridge_operations = { - .read_resources = amdfam10_read_resources, - .set_resources = amdfam10_set_resources, - .enable_resources = pci_dev_enable_resources, - .init = mcf0_control_init, - .scan_bus = amdfam10_scan_chains, -#if CONFIG(HAVE_ACPI_TABLES) - .write_acpi_tables = northbridge_write_acpi_tables, - .acpi_fill_ssdt_generator = northbridge_acpi_write_vars, - .acpi_name = amdfam10_northbridge_acpi_name, -#endif - .enable = 0, - .ops_pci = 0, -}; - -static const struct pci_driver mcf0_driver __pci_driver = { - .ops = &northbridge_operations, - .vendor = PCI_VENDOR_ID_AMD, - .device = 0x1200, -}; - -static void amdfam10_nb_init(void *chip_info) -{ - relocate_sb_ht_chain(); -} - -static const struct pci_driver mcf0_driver_fam15_model10 __pci_driver = { - .ops = &northbridge_operations, - .vendor = PCI_VENDOR_ID_AMD, - .device = 0x1400, -}; - -static const struct pci_driver mcf0_driver_fam15 __pci_driver = { - .ops = &northbridge_operations, - .vendor = PCI_VENDOR_ID_AMD, - .device = 0x1600, -}; - -struct chip_operations northbridge_amd_amdfam10_ops = { - CHIP_NAME("AMD Family 10h/15h Northbridge") - .enable_dev = 0, - .init = amdfam10_nb_init, -}; - -static void amdfam10_domain_read_resources(struct device *dev) -{ - unsigned int reg; - uint8_t nvram; - uint8_t enable_cc6; - - /* Find the already assigned resource pairs */ - get_fx_devs(); - for (reg = 0x80; reg <= 0xd8; reg+= 0x08) { - u32 base, limit; - base = f1_read_config32(reg); - limit = f1_read_config32(reg + 0x04); - /* Is this register allocated? */ - if ((base & 3) != 0) { - unsigned int nodeid, reg_link; - struct device *reg_dev; - if (reg < 0xc0) { // mmio - nodeid = (limit & 0xf) + (base&0x30); - } else { // io - nodeid = (limit & 0xf) + ((base>>4)&0x30); - } - reg_link = (limit >> 4) & 7; - reg_dev = __f0_dev[nodeid]; - if (reg_dev) { - /* Reserve the resource */ - struct resource *res; - res = new_resource(reg_dev, IOINDEX(0x1000 + reg, reg_link)); - if (res) { - res->flags = 1; - } - } - } - } - /* FIXME: do we need to check extend conf space? - I don't believe that much preset value */ - - pci_domain_read_resources(dev); - - /* We have MMCONF_SUPPORT, create the resource window. */ - mmconf_resource(dev, MMIO_CONF_BASE); - - /* Reserve lower DRAM region to force PCI MMIO region to correct location above 0xefffffff */ - ram_resource(dev, 7, 0, rdmsr(TOP_MEM).lo >> 10); - - if (is_fam15h()) { - enable_cc6 = 0; - if (get_option(&nvram, "cpu_cc6_state") == CB_SUCCESS) - enable_cc6 = !!nvram; - - if (enable_cc6) { - uint8_t node; - uint8_t interleaved; - int8_t range; - uint8_t max_node; - uint64_t max_range_limit; - uint32_t dword; - uint32_t dword2; - uint64_t qword; - uint8_t num_nodes; - - /* Find highest DRAM range (DramLimitAddr) */ - num_nodes = 0; - max_node = 0; - interleaved = 0; - max_range_limit = 0; - struct device *node_dev; - for (node = 0; node < FX_DEVS; node++) { - node_dev = get_node_pci(node, 0); - /* Test for node presence */ - if ((!node_dev) || (pci_read_config32(node_dev, PCI_VENDOR_ID) == 0xffffffff)) - continue; - - num_nodes++; - for (range = 0; range < 8; range++) { - dword = pci_read_config32(get_node_pci(node, 1), 0x40 + (range * 0x8)); - if (!(dword & 0x3)) - continue; - - if ((dword >> 8) & 0x7) - interleaved = 1; - - dword = pci_read_config32(get_node_pci(node, 1), 0x44 + (range * 0x8)); - dword2 = pci_read_config32(get_node_pci(node, 1), 0x144 + (range * 0x8)); - qword = 0xffffff; - qword |= ((((uint64_t)dword) >> 16) & 0xffff) << 24; - qword |= (((uint64_t)dword2) & 0xff) << 40; - - if (qword > max_range_limit) { - max_range_limit = qword; - max_node = dword & 0x7; - } - } - } - - /* Calculate CC6 storage area size */ - if (interleaved) - qword = (uint64_t)0x1000000 * num_nodes; - else - qword = 0x1000000; - - /* FIXME - * The BKDG appears to be incorrect as to the location of the CC6 save region - * lower boundary on non-interleaved systems, causing lockups on attempted write - * to the CC6 save region. - * - * For now, work around by allocating the maximum possible CC6 save region size. - * - * Determine if this is a BKDG error or a setup problem and remove this warning! - */ - qword = (0x1 << 27); - max_range_limit = (((uint64_t)(pci_read_config32(get_node_pci(max_node, 1), 0x124) & 0x1fffff)) << 27) - 1; - - printk(BIOS_INFO, "Reserving CC6 save segment base: %08llx size: %08llx\n", (max_range_limit + 1), qword); - - /* Reserve the CC6 save segment */ - reserved_ram_resource(dev, 8, (max_range_limit + 1) >> 10, qword >> 10); - } - } -} - -static u32 my_find_pci_tolm(struct bus *bus, u32 tolm) -{ - struct resource *min; - min = 0; - search_bus_resources(bus, IORESOURCE_MEM, IORESOURCE_MEM, tolm_test, &min); - if (min && tolm > min->base) { - tolm = min->base; - } - return tolm; -} - -#if CONFIG_HW_MEM_HOLE_SIZEK != 0 - -struct hw_mem_hole_info { - unsigned int hole_startk; - int node_id; -}; - -static struct hw_mem_hole_info get_hw_mem_hole_info(void) -{ - struct hw_mem_hole_info mem_hole; - int i; - - mem_hole.hole_startk = CONFIG_HW_MEM_HOLE_SIZEK; - mem_hole.node_id = -1; - - for (i = 0; i < sysconf.nodes; i++) { - struct dram_base_mask_t d; - u32 hole; - d = get_dram_base_mask(i); - if (!(d.mask & 1)) continue; // no memory on this node - - hole = pci_read_config32(__f1_dev[i], 0xf0); - if (hole & 1) { // we find the hole - mem_hole.hole_startk = (hole & (0xff<<24)) >> 10; - mem_hole.node_id = i; // record the node No with hole - break; // only one hole - } - } - - /* We need to double check if there is special set on base reg and limit reg - * are not continuous instead of hole, it will find out its hole_startk. - */ - if (mem_hole.node_id==-1) { - resource_t limitk_pri = 0; - for (i = 0; i < sysconf.nodes; i++) { - struct dram_base_mask_t d; - resource_t base_k, limit_k; - d = get_dram_base_mask(i); - if (!(d.base & 1)) continue; - - base_k = ((resource_t)(d.base & 0x1fffff00)) <<9; - if (base_k > 4 *1024 * 1024) break; // don't need to go to check - if (limitk_pri != base_k) { // we find the hole - mem_hole.hole_startk = (unsigned int)limitk_pri; // must beblow 4G - mem_hole.node_id = i; - break; //only one hole - } - - limit_k = ((resource_t)((d.mask + 0x00000100) & 0x1fffff00)) << 9; - limitk_pri = limit_k; - } - } - return mem_hole; -} - -#endif - -#include - -static void setup_uma_memory(void) -{ -#if CONFIG(GFXUMA) - uint32_t topmem = (uint32_t) bsp_topmem(); - uma_memory_size = get_uma_memory_size(topmem); - uma_memory_base = topmem - uma_memory_size; /* TOP_MEM1 */ - printk(BIOS_INFO, "%s: uma size 0x%08llx, memory start 0x%08llx\n", - __func__, uma_memory_size, uma_memory_base); -#endif -} - -static void amdfam10_domain_set_resources(struct device *dev) -{ - unsigned long mmio_basek; - u32 pci_tolm; - int i, idx; - struct bus *link; -#if CONFIG_HW_MEM_HOLE_SIZEK != 0 - struct hw_mem_hole_info mem_hole; -#endif - - pci_tolm = 0xffffffffUL; - for (link = dev->link_list; link; link = link->next) { - pci_tolm = my_find_pci_tolm(link, pci_tolm); - } - - // FIXME handle interleaved nodes. If you fix this here, please fix - // amdk8, too. - mmio_basek = pci_tolm >> 10; - /* Round mmio_basek to something the processor can support */ - mmio_basek &= ~((1 << 6) -1); - - // FIXME improve mtrr.c so we don't use up all of the mtrrs with a 64M - // MMIO hole. If you fix this here, please fix amdk8, too. - /* Round the mmio hole to 64M */ - mmio_basek &= ~((64*1024) - 1); - -#if CONFIG_HW_MEM_HOLE_SIZEK != 0 -/* if the hw mem hole is already set in raminit stage, here we will compare - * mmio_basek and hole_basek. if mmio_basek is bigger that hole_basek and will - * use hole_basek as mmio_basek and we don't need to reset hole. - * otherwise We reset the hole to the mmio_basek - */ - - mem_hole = get_hw_mem_hole_info(); - - // Use hole_basek as mmio_basek, and we don't need to reset hole anymore - if ((mem_hole.node_id != -1) && (mmio_basek > mem_hole.hole_startk)) { - mmio_basek = mem_hole.hole_startk; - } - -#endif - - idx = 0x10; - for (i = 0; i < sysconf.nodes; i++) { - struct dram_base_mask_t d; - resource_t basek, limitk, sizek; // 4 1T - d = get_dram_base_mask(i); - - if (!(d.mask & 1)) continue; - basek = ((resource_t)(d.base & 0x1fffff00)) << 9; // could overflow, we may lost 6 bit here - limitk = ((resource_t)((d.mask + 0x00000100) & 0x1fffff00)) << 9; - sizek = limitk - basek; - - /* see if we need a hole from 0xa0000 to 0xbffff */ - if ((basek < ((8*64)+(8*16))) && (sizek > ((8*64)+(16*16)))) { - ram_resource(dev, (idx | i), basek, ((8*64)+(8*16)) - basek); - idx += 0x10; - basek = (8*64)+(16*16); - sizek = limitk - ((8*64)+(16*16)); - - } - - /* split the region to accommodate pci memory space */ - if ((basek < 4*1024*1024) && (limitk > mmio_basek)) { - if (basek <= mmio_basek) { - unsigned int pre_sizek; - pre_sizek = mmio_basek - basek; - if (pre_sizek > 0) { - ram_resource(dev, (idx | i), basek, pre_sizek); - idx += 0x10; - sizek -= pre_sizek; - } - basek = mmio_basek; - } - if ((basek + sizek) <= 4*1024*1024) { - sizek = 0; - } else { - basek = 4*1024*1024; - sizek -= (4*1024*1024 - mmio_basek); - } - } - - ram_resource(dev, (idx | i), basek, sizek); - idx += 0x10; - printk(BIOS_DEBUG, "%d: mmio_basek=%08lx, basek=%08llx, limitk=%08llx\n", - i, mmio_basek, basek, limitk); - } - -#if CONFIG(GFXUMA) - uma_resource(dev, 7, uma_memory_base >> 10, uma_memory_size >> 10); -#endif - - for (link = dev->link_list; link; link = link->next) { - if (link->children) { - assign_resources(link); - } - } -} - -static void amdfam10_domain_scan_bus(struct device *dev) -{ - u32 reg; - int i; - struct bus *link; - /* Unmap all of the HT chains */ - for (reg = 0xe0; reg <= 0xec; reg += 4) { - f1_write_config32(reg, 0); - } - - for (link = dev->link_list; link; link = link->next) { - link->secondary = dev->bus->subordinate; - pci_scan_bus(link, PCI_DEVFN(CONFIG_CDB, 0), 0xff); - dev->bus->subordinate = link->subordinate; - } - - /* Tune the hypertransport transaction for best performance. - * Including enabling relaxed ordering if it is safe. - */ - get_fx_devs(); - for (i = 0; i < fx_devs; i++) { - struct device *f0_dev; - f0_dev = __f0_dev[i]; - if (f0_dev && f0_dev->enabled) { - u32 httc; - httc = pci_read_config32(f0_dev, HT_TRANSACTION_CONTROL); - httc &= ~HTTC_RSP_PASS_PW; - if (!dev->link_list->disable_relaxed_ordering) { - httc |= HTTC_RSP_PASS_PW; - } - printk(BIOS_SPEW, "%s passpw: %s\n", - dev_path(dev), - (!dev->link_list->disable_relaxed_ordering)? - "enabled":"disabled"); - pci_write_config32(f0_dev, HT_TRANSACTION_CONTROL, httc); - } - } -} - -#if CONFIG(GENERATE_SMBIOS_TABLES) -static int amdfam10_get_smbios_data16(int *count, int handle, - unsigned long *current) -{ - struct amdmct_memory_info *mem_info; - mem_info = cbmem_find(CBMEM_ID_AMDMCT_MEMINFO); - if (mem_info == NULL) - return 0; /* can't find amdmct information in cbmem */ - - struct device *dev = get_node_pci(0, 0); - struct northbridge_amd_amdfam10_config *config = dev->chip_info; - - int node; - int slot; - - struct smbios_type16 *t = (struct smbios_type16 *)*current; - int len = sizeof(struct smbios_type16); - - memset(t, 0, sizeof(struct smbios_type16)); - t->type = SMBIOS_PHYS_MEMORY_ARRAY; - t->handle = handle; - t->length = len - 2; - t->location = MEMORY_ARRAY_LOCATION_SYSTEM_BOARD; - t->use = MEMORY_ARRAY_USE_SYSTEM; - t->memory_error_correction = MEMORY_ARRAY_ECC_NONE; - if ((mem_info->ecc_enabled) - && (mem_info->mct_stat.GStatus & (1 << GSB_ECCDIMMs)) - && !(mem_info->mct_stat.GStatus & (1 << GSB_DramECCDis))) - /* Single-bit ECC enabled */ - t->memory_error_correction = MEMORY_ARRAY_ECC_SINGLE_BIT; - t->maximum_capacity = config->maximum_memory_capacity / 1024; /* Convert to kilobytes */ - t->memory_error_information_handle = 0xFFFE; /* no error information handle available */ - - t->number_of_memory_devices = 0; - /* Check all nodes for installed DIMMs */ - for (node = 0; node < MAX_NODES_SUPPORTED; node++) - /* Check all slots for installed DIMMs */ - for (slot = 0; slot < MAX_DIMMS_SUPPORTED; slot++) - if (mem_info->dct_stat[node].DIMMPresent & (1 << slot)) - /* Found an installed DIMM; increment count */ - t->number_of_memory_devices++; - - *current += len; - *count += 1; - return len; -} - -static uint16_t amdmct_mct_speed_enum_to_mhz(uint8_t speed) -{ - if (is_fam15h()) { - if (CONFIG(DIMM_DDR3)) { - switch (speed) { - case 0x4: - return 333; - case 0x6: - return 400; - case 0xa: - return 533; - case 0xe: - return 667; - case 0x12: - return 800; - case 0x16: - return 933; - default: - return 0; - } - } else { - return 0; - } - } else { - if (CONFIG(DIMM_DDR2)) { - switch (speed) { - case 1: - return 200; - case 2: - return 266; - case 3: - return 333; - case 4: - return 400; - case 5: - return 533; - default: - return 0; - } - } else if (CONFIG(DIMM_DDR3)) { - switch (speed) { - case 3: - return 333; - case 4: - return 400; - case 5: - return 533; - case 6: - return 667; - case 7: - return 800; - default: - return 0; - } - } else { - return 0; - } - } -} - -static int amdfam10_get_smbios_data17(int *count, int handle, int parent_handle, - unsigned long *current) -{ - struct amdmct_memory_info *mem_info; - mem_info = cbmem_find(CBMEM_ID_AMDMCT_MEMINFO); - if (mem_info == NULL) - return 0; /* can't find amdmct information in cbmem */ - - int single_len; - int len = 0; - int node; - int slot; - - /* Check all nodes for installed DIMMs */ - for (node = 0; node < MAX_NODES_SUPPORTED; node++) { - /* Get configured RAM bus speed */ - uint16_t speed; - speed = amdmct_mct_speed_enum_to_mhz(mem_info->dct_stat[node].Speed); - - /* Get maximum RAM bus speed */ - uint16_t max_speed; - max_speed = amdmct_mct_speed_enum_to_mhz(mem_info->dct_stat[node].DIMMAutoSpeed); - - /* Check all slots for installed DIMMs */ - for (slot = 0; slot < MAX_DIMMS_SUPPORTED; slot++) { - if (mem_info->dct_stat[node].DIMMPresent & (1 << slot)) { - /* Found an installed DIMM; populate tables */ - struct smbios_type17 *t = (struct smbios_type17 *)*current; - char string_buffer[256]; - - /* Initialize structure */ - memset(t, 0, sizeof(struct smbios_type17)); - - /* Calculate the total module size in bytes: - * Primary data width * 2^(#rows) * 2^(#cols) * #banks * #ranks - */ - uint8_t width, rows, cols, banks, ranks; - uint64_t chip_size; - uint32_t chip_width; - rows = mem_info->dct_stat[node].DimmRows[slot]; - cols = mem_info->dct_stat[node].DimmCols[slot]; - ranks = mem_info->dct_stat[node].DimmRanks[slot]; - banks = mem_info->dct_stat[node].DimmBanks[slot]; -#if CONFIG(DIMM_DDR3) - chip_size = mem_info->dct_stat[node].DimmChipSize[slot]; - chip_width = mem_info->dct_stat[node].DimmChipWidth[slot]; -#else - chip_size = 0; - chip_width = 0; -#endif - uint64_t dimm_size_bytes; - if (CONFIG(DIMM_DDR3)) { - width = mem_info->dct_stat[node].DimmWidth[slot]; - dimm_size_bytes = ((width / chip_width) * chip_size * ranks) / 8; - } else { - width = 8; - dimm_size_bytes = width * (1ULL << rows) * (1ULL << cols) * banks * ranks; - } - - memset(t, 0, sizeof(struct smbios_type17)); - t->type = SMBIOS_MEMORY_DEVICE; - t->handle = handle; - t->phys_memory_array_handle = parent_handle; - t->length = sizeof(struct smbios_type17) - 2; - if (dimm_size_bytes > 0x800000000) { - t->size = 0x7FFF; - t->extended_size = dimm_size_bytes >> 16; - } else { - t->size = dimm_size_bytes / (1024*1024); - t->size &= (~0x8000); /* size specified in megabytes */ - } - t->total_width = t->data_width = 64; - if (mem_info->dct_stat[node].DimmECCPresent & (1 << slot)) - t->total_width += 8; - t->attributes = 0; - t->attributes |= ranks & 0xf; /* rank number is stored in the lowest 4 bits of the attributes field */ - t->form_factor = MEMORY_FORMFACTOR_DIMM; - if (mem_info->dct_stat[node].Dual_Node_Package) { - snprintf(string_buffer, sizeof(string_buffer), "NODE %d DIMM_%s%d", node >> 1, - (mem_info->dct_stat[node].Internal_Node_ID)?((slot & 0x1)?"D":"C"):((slot & 0x1)?"B":"A"), (slot >> 1) + 1); - } else { - snprintf(string_buffer, sizeof(string_buffer), "NODE %d DIMM_%s%d", node, (slot & 0x1)?"B":"A", (slot >> 1) + 1); - } - t->device_locator = smbios_add_string(t->eos, string_buffer); - if (CONFIG(DIMM_DDR2)) - t->memory_type = MEMORY_TYPE_DDR2; - else if (CONFIG(DIMM_DDR3)) - t->memory_type = MEMORY_TYPE_DDR3; - t->type_detail = MEMORY_TYPE_DETAIL_SYNCHRONOUS; - if (mem_info->dct_stat[node].DimmRegistered[slot]) - t->type_detail |= MEMORY_TYPE_DETAIL_REGISTERED; - else - t->type_detail |= MEMORY_TYPE_DETAIL_UNBUFFERED; - t->speed = max_speed; - t->clock_speed = speed; - smbios_fill_dimm_manufacturer_from_id(mem_info->dct_stat[node].DimmManufacturerID[slot], t); - t->part_number = smbios_add_string(t->eos, mem_info->dct_stat[node].DimmPartNumber[slot]); - if (mem_info->dct_stat[node].DimmSerialNumber[slot] == 0) { - t->serial_number = smbios_add_string(t->eos, "None"); - } else { - snprintf(string_buffer, sizeof(string_buffer), "%08X", mem_info->dct_stat[node].DimmSerialNumber[slot]); - t->serial_number = smbios_add_string(t->eos, string_buffer); - } - if (CONFIG(DIMM_DDR2)) { - /* JEDEC specifies 1.8V only, so assume that the memory is configured for 1.8V */ - t->minimum_voltage = 1800; - t->maximum_voltage = 1800; - t->configured_voltage = 1800; - } else if (CONFIG(DIMM_DDR3)) { -#if CONFIG(DIMM_DDR3) - /* Find the maximum and minimum supported voltages */ - uint8_t supported_voltages = mem_info->dct_stat[node].DimmSupportedVoltages[slot]; - uint8_t configured_voltage = mem_info->dct_stat[node].DimmConfiguredVoltage[slot]; - - if (supported_voltages & 0x8) - t->minimum_voltage = 1150; - else if (supported_voltages & 0x4) - t->minimum_voltage = 1250; - else if (supported_voltages & 0x2) - t->minimum_voltage = 1350; - else if (supported_voltages & 0x1) - t->minimum_voltage = 1500; - - if (supported_voltages & 0x1) - t->maximum_voltage = 1500; - else if (supported_voltages & 0x2) - t->maximum_voltage = 1350; - else if (supported_voltages & 0x4) - t->maximum_voltage = 1250; - else if (supported_voltages & 0x8) - t->maximum_voltage = 1150; - - if (configured_voltage & 0x8) - t->configured_voltage = 1150; - else if (configured_voltage & 0x4) - t->configured_voltage = 1250; - else if (configured_voltage & 0x2) - t->configured_voltage = 1350; - else if (configured_voltage & 0x1) - t->configured_voltage = 1500; -#endif - } - t->memory_error_information_handle = 0xFFFE; /* no error information handle available */ - single_len = t->length + smbios_string_table_len(t->eos); - len += single_len; - *current += single_len; - handle++; - *count += 1; - } - } - } - - return len; -} - -static int amdfam10_get_smbios_data(struct device *dev, int *handle, unsigned long *current) -{ - int len; - int count = 0; - len = amdfam10_get_smbios_data16(&count, *handle, current); - len += amdfam10_get_smbios_data17(&count, *handle + 1, *handle, current); - *handle += count; - return len; -} -#endif - -#if CONFIG(HAVE_ACPI_TABLES) -static const char *amdfam10_domain_acpi_name(const struct device *dev) -{ - if (dev->path.type == DEVICE_PATH_DOMAIN) - return "PCI0"; - - return NULL; -} -#endif - -static struct device_operations pci_domain_ops = { - .read_resources = amdfam10_domain_read_resources, - .set_resources = amdfam10_domain_set_resources, - .enable_resources = NULL, - .init = NULL, - .scan_bus = amdfam10_domain_scan_bus, -#if CONFIG(HAVE_ACPI_TABLES) - .acpi_name = amdfam10_domain_acpi_name, -#endif -#if CONFIG(GENERATE_SMBIOS_TABLES) - .get_smbios_data = amdfam10_get_smbios_data, -#endif -}; - -static void sysconf_init(struct device *dev) // first node -{ - sysconf.sblk = (pci_read_config32(dev, 0x64)>>8) & 7; // don't forget sublink1 - sysconf.segbit = 0; - sysconf.ht_c_num = 0; - - unsigned int ht_c_index; - - for (ht_c_index = 0; ht_c_index < 32; ht_c_index++) { - sysconf.ht_c_conf_bus[ht_c_index] = 0; - } - - sysconf.nodes = ((pci_read_config32(dev, 0x60)>>4) & 7) + 1; -#if CONFIG_MAX_PHYSICAL_CPUS > 8 - sysconf.nodes += (((pci_read_config32(dev, 0x160)>>4) & 7)<<3); -#endif - - sysconf.enabled_apic_ext_id = 0; - sysconf.lift_bsp_apicid = 0; - - /* Find the bootstrap processors apicid */ - sysconf.bsp_apicid = lapicid(); - sysconf.apicid_offset = sysconf.bsp_apicid; - -#if CONFIG(ENABLE_APIC_EXT_ID) - if (pci_read_config32(dev, 0x68) & (HTTC_APIC_EXT_ID|HTTC_APIC_EXT_BRD_CST)) - { - sysconf.enabled_apic_ext_id = 1; - } - #if (CONFIG_APIC_ID_OFFSET > 0) - if (sysconf.enabled_apic_ext_id) { - if (sysconf.bsp_apicid == 0) { - /* bsp apic id is not changed */ - sysconf.apicid_offset = CONFIG_APIC_ID_OFFSET; - } else { - sysconf.lift_bsp_apicid = 1; - } - } - #endif -#endif -} - -static void remap_bsp_lapic(struct bus *cpu_bus) -{ - struct device_path cpu_path; - struct device *cpu; - u32 bsp_lapic_id = lapicid(); - - if (bsp_lapic_id) { - cpu_path.type = DEVICE_PATH_APIC; - cpu_path.apic.apic_id = 0; - cpu = find_dev_path(cpu_bus, &cpu_path); - if (cpu) - cpu->path.apic.apic_id = bsp_lapic_id; - } -} - -static void cpu_bus_scan(struct device *dev) -{ - struct bus *cpu_bus; - struct device *dev_mc; -#if CONFIG_CBB - struct device *pci_domain; -#endif - int nvram = 0; - int i,j; - int nodes; - unsigned int nb_cfg_54; - unsigned int siblings; - int cores_found; - int disable_siblings; - uint8_t disable_cu_siblings = 0; - unsigned int ApicIdCoreIdSize; - - nb_cfg_54 = 0; - ApicIdCoreIdSize = (cpuid_ecx(0x80000008)>>12 & 0xf); - if (ApicIdCoreIdSize) { - siblings = (1<bus) { - printk(BIOS_DEBUG, "%s found", dev_path(dev_mc)); - pci_domain = dev_mc->bus->dev; - if (pci_domain && (pci_domain->path.type == DEVICE_PATH_DOMAIN)) { - printk(BIOS_DEBUG, "\n%s move to ",dev_path(dev_mc)); - dev_mc->bus->secondary = CONFIG_CBB; // move to 0xff - printk(BIOS_DEBUG, "%s",dev_path(dev_mc)); - - } else { - printk(BIOS_DEBUG, " but it is not under pci_domain directly "); - } - printk(BIOS_DEBUG, "\n"); - } - dev_mc = dev_find_slot(CONFIG_CBB, PCI_DEVFN(CONFIG_CDB, 0)); - if (!dev_mc) { - dev_mc = pcidev_on_root(0x18, 0); - if (dev_mc && dev_mc->bus) { - printk(BIOS_DEBUG, "%s found\n", dev_path(dev_mc)); - pci_domain = dev_mc->bus->dev; - if (pci_domain && (pci_domain->path.type == DEVICE_PATH_DOMAIN)) { - if ((pci_domain->link_list) && (pci_domain->link_list->children == dev_mc)) { - printk(BIOS_DEBUG, "%s move to ",dev_path(dev_mc)); - dev_mc->bus->secondary = CONFIG_CBB; // move to 0xff - printk(BIOS_DEBUG, "%s\n",dev_path(dev_mc)); - while (dev_mc) { - printk(BIOS_DEBUG, "%s move to ",dev_path(dev_mc)); - dev_mc->path.pci.devfn -= PCI_DEVFN(0x18,0); - printk(BIOS_DEBUG, "%s\n",dev_path(dev_mc)); - dev_mc = dev_mc->sibling; - } - } - } - } - } - -#endif - - dev_mc = dev_find_slot(CONFIG_CBB, PCI_DEVFN(CONFIG_CDB, 0)); - if (!dev_mc) { - printk(BIOS_ERR, "%02x:%02x.0 not found", CONFIG_CBB, CONFIG_CDB); - die(""); - } - - sysconf_init(dev_mc); - - nodes = sysconf.nodes; - -#if CONFIG_CBB && (NODE_NUMS > 32) - if (nodes > 32) { // need to put node 32 to node 63 to bus 0xfe - if (pci_domain->link_list && !pci_domain->link_list->next) { - struct bus *new_link = new_link(pci_domain); - pci_domain->link_list->next = new_link; - new_link->link_num = 1; - new_link->dev = pci_domain; - new_link->children = 0; - printk(BIOS_DEBUG, "%s links now 2\n", dev_path(pci_domain)); - } - pci_domain->link_list->next->secondary = CONFIG_CBB - 1; - } -#endif - /* Find which cpus are present */ - cpu_bus = dev->link_list; - - /* Always use the devicetree node with lapic_id 0 for BSP. */ - remap_bsp_lapic(cpu_bus); - - if (get_option(&nvram, "compute_unit_siblings") == CB_SUCCESS) - disable_cu_siblings = !!nvram; - - if (disable_cu_siblings) - printk(BIOS_DEBUG, "Disabling siblings on each compute unit as requested\n"); - - for (i = 0; i < nodes; i++) { - struct device *cdb_dev; - unsigned int busn, devn; - struct bus *pbus; - - uint8_t fam15h = 0; - uint8_t rev_gte_d = 0; - uint8_t dual_node = 0; - uint32_t f3xe8; - uint32_t model; - - busn = CONFIG_CBB; - devn = CONFIG_CDB+i; - pbus = dev_mc->bus; -#if CONFIG_CBB && (NODE_NUMS > 32) - if (i >= 32) { - busn--; - devn-=32; - pbus = pci_domain->link_list->next; - } -#endif - - /* Find the cpu's pci device */ - cdb_dev = dev_find_slot(busn, PCI_DEVFN(devn, 0)); - if (!cdb_dev) { - /* If I am probing things in a weird order - * ensure all of the cpu's pci devices are found. - */ - int fn; - for (fn = 0; fn <= 5; fn++) { //FBDIMM? - cdb_dev = pci_probe_dev(NULL, pbus, - PCI_DEVFN(devn, fn)); - } - } - - - /* Ok, We need to set the links for that device. - * otherwise the device under it will not be scanned - */ - cdb_dev = dev_find_slot(busn, PCI_DEVFN(devn, 0)); - if (cdb_dev) - add_more_links(cdb_dev, 4); - - cdb_dev = dev_find_slot(busn, PCI_DEVFN(devn, 4)); - if (cdb_dev) - add_more_links(cdb_dev, 4); - - f3xe8 = pci_read_config32(get_node_pci(0, 3), 0xe8); - - model = cpuid_eax(0x80000001); - model = ((model & 0xf0000) >> 12) | ((model & 0xf0) >> 4); - - if (is_fam15h()) { - /* Family 15h or later */ - fam15h = 1; - nb_cfg_54 = 1; - } - - if ((model >= 0x8) || fam15h) - /* Revision D or later */ - rev_gte_d = 1; - - if (rev_gte_d) - /* Check for dual node capability */ - if (f3xe8 & 0x20000000) - dual_node = 1; - - cores_found = 0; // one core - if (fam15h) - cdb_dev = dev_find_slot(busn, PCI_DEVFN(devn, 5)); - else - cdb_dev = dev_find_slot(busn, PCI_DEVFN(devn, 3)); - int enable_node = cdb_dev && cdb_dev->enabled; - if (enable_node) { - if (fam15h) { - cores_found = pci_read_config32(cdb_dev, 0x84) & 0xff; - } else { - j = pci_read_config32(cdb_dev, 0xe8); - cores_found = (j >> 12) & 3; // dev is func 3 - if (siblings > 3) - cores_found |= (j >> 13) & 4; - } - printk(BIOS_DEBUG, " %s siblings=%d\n", dev_path(cdb_dev), cores_found); - } - - if (siblings > cores_found) - siblings = cores_found; - - u32 jj; - if (disable_siblings) { - jj = 0; - } else - { - jj = cores_found; - } - - for (j = 0; j <=jj; j++) { - u32 apic_id; - - if (dual_node) { - apic_id = 0; - if (fam15h) { - apic_id |= ((i >> 1) & 0x3) << 5; /* Node ID */ - apic_id |= ((i & 0x1) * (siblings + 1)) + j; /* Core ID */ - } else { - if (nb_cfg_54) { - apic_id |= ((i >> 1) & 0x3) << 4; /* Node ID */ - apic_id |= ((i & 0x1) * (siblings + 1)) + j; /* Core ID */ - } else { - apic_id |= i & 0x3; /* Node ID */ - apic_id |= (((i & 0x1) * (siblings + 1)) + j) << 4; /* Core ID */ - } - } - } else { - if (fam15h) { - apic_id = 0; - apic_id |= (i & 0x7) << 4; /* Node ID */ - apic_id |= j & 0xf; /* Core ID */ - } else { - apic_id = i * (nb_cfg_54?(siblings+1):1) + j * (nb_cfg_54?1:64); // ? - } - } - -#if CONFIG(ENABLE_APIC_EXT_ID) && (CONFIG_APIC_ID_OFFSET > 0) - if (sysconf.enabled_apic_ext_id) { - if (apic_id != 0 || sysconf.lift_bsp_apicid) { - apic_id += sysconf.apicid_offset; - } - } -#endif - if (disable_cu_siblings && (j & 0x1)) - continue; - - struct device *cpu = add_cpu_device(cpu_bus, apic_id, enable_node); - if (cpu) - amd_cpu_topology(cpu, i, j); - } - } -} - -static void detect_and_enable_probe_filter(struct device *dev) -{ - uint32_t dword; - - uint8_t nvram; - uint8_t enable_probe_filter; - - /* Check to see if the probe filter is allowed */ - enable_probe_filter = 1; - if (get_option(&nvram, "probe_filter") == CB_SUCCESS) - enable_probe_filter = !!nvram; - - if (!enable_probe_filter) - return; - - uint8_t fam15h = 0; - uint8_t rev_gte_d = 0; - uint32_t model; - - model = cpuid_eax(0x80000001); - model = ((model & 0xf0000) >> 12) | ((model & 0xf0) >> 4); - - if (is_fam15h()) { - /* Family 15h or later */ - fam15h = 1; - } - - if ((model >= 0x8) || fam15h) - /* Revision D or later */ - rev_gte_d = 1; - - if (rev_gte_d && (sysconf.nodes > 1)) { - /* Enable the probe filter */ - uint8_t i; - uint8_t pfmode = 0x0; - - uint32_t f3x58[MAX_NODES_SUPPORTED]; - uint32_t f3x5c[MAX_NODES_SUPPORTED]; - - printk(BIOS_DEBUG, "Enabling probe filter\n"); - - /* Disable L3 and DRAM scrubbers and configure system for probe filter support */ - for (i = 0; i < sysconf.nodes; i++) { - struct device *f2x_dev = pcidev_on_root(0x18 + i, 2); - struct device *f3x_dev = pcidev_on_root(0x18 + i, 3); - - f3x58[i] = pci_read_config32(f3x_dev, 0x58); - f3x5c[i] = pci_read_config32(f3x_dev, 0x5c); - pci_write_config32(f3x_dev, 0x58, f3x58[i] & ~((0x1f << 24) | 0x1f)); - pci_write_config32(f3x_dev, 0x5c, f3x5c[i] & ~0x1); - - dword = pci_read_config32(f2x_dev, 0x1b0); - dword &= ~(0x7 << 8); /* CohPrefPrbLmt = 0x0 */ - pci_write_config32(f2x_dev, 0x1b0, dword); - - msr_t msr = rdmsr_amd(BU_CFG2_MSR); - msr.hi |= 1 << (42 - 32); - wrmsr_amd(BU_CFG2_MSR, msr); - - if (is_fam15h()) { - uint8_t subcache_size = 0x0; - uint8_t pref_so_repl = 0x0; - uint32_t f3x1c4 = pci_read_config32(f3x_dev, 0x1c4); - if ((f3x1c4 & 0xffff) == 0xcccc) { - subcache_size = 0x1; - pref_so_repl = 0x2; - pfmode = 0x3; - } else { - pfmode = 0x2; - } - - dword = pci_read_config32(f3x_dev, 0x1d4); - dword |= 0x1 << 29; /* PFLoIndexHashEn = 0x1 */ - dword &= ~(0x3 << 20); /* PFPreferredSORepl = pref_so_repl */ - dword |= (pref_so_repl & 0x3) << 20; - dword |= 0x1 << 17; /* PFWayHashEn = 0x1 */ - dword |= 0xf << 12; /* PFSubCacheEn = 0xf */ - dword &= ~(0x3 << 10); /* PFSubCacheSize3 = subcache_size */ - dword |= (subcache_size & 0x3) << 10; - dword &= ~(0x3 << 8); /* PFSubCacheSize2 = subcache_size */ - dword |= (subcache_size & 0x3) << 8; - dword &= ~(0x3 << 6); /* PFSubCacheSize1 = subcache_size */ - dword |= (subcache_size & 0x3) << 6; - dword &= ~(0x3 << 4); /* PFSubCacheSize0 = subcache_size */ - dword |= (subcache_size & 0x3) << 4; - dword &= ~(0x3 << 2); /* PFWayNum = 0x2 */ - dword |= 0x2 << 2; - pci_write_config32(f3x_dev, 0x1d4, dword); - } else { - pfmode = 0x2; - - dword = pci_read_config32(f3x_dev, 0x1d4); - dword |= 0x1 << 29; /* PFLoIndexHashEn = 0x1 */ - dword &= ~(0x3 << 20); /* PFPreferredSORepl = 0x2 */ - dword |= 0x2 << 20; - dword |= 0xf << 12; /* PFSubCacheEn = 0xf */ - dword &= ~(0x3 << 10); /* PFSubCacheSize3 = 0x0 */ - dword &= ~(0x3 << 8); /* PFSubCacheSize2 = 0x0 */ - dword &= ~(0x3 << 6); /* PFSubCacheSize1 = 0x0 */ - dword &= ~(0x3 << 4); /* PFSubCacheSize0 = 0x0 */ - dword &= ~(0x3 << 2); /* PFWayNum = 0x2 */ - dword |= 0x2 << 2; - pci_write_config32(f3x_dev, 0x1d4, dword); - } - } - - udelay(40); - - disable_cache(); - wbinvd(); - - /* Enable probe filter */ - for (i = 0; i < sysconf.nodes; i++) { - struct device *f3x_dev = pcidev_on_root(0x18 + i, 3); - - dword = pci_read_config32(f3x_dev, 0x1c4); - dword |= (0x1 << 31); /* L3TagInit = 1 */ - pci_write_config32(f3x_dev, 0x1c4, dword); - do { - } while (pci_read_config32(f3x_dev, 0x1c4) & (0x1 << 31)); - - dword = pci_read_config32(f3x_dev, 0x1d4); - dword &= ~0x3; /* PFMode = pfmode */ - dword |= pfmode & 0x3; - pci_write_config32(f3x_dev, 0x1d4, dword); - do { - } while (!(pci_read_config32(f3x_dev, 0x1d4) & (0x1 << 19))); - } - - if (is_fam15h()) { - printk(BIOS_DEBUG, "Enabling ATM mode\n"); - - /* Enable ATM mode */ - for (i = 0; i < sysconf.nodes; i++) { - struct device *f0x_dev = - pcidev_on_root(0x18 + i, 0); - struct device *f3x_dev = - pcidev_on_root(0x18 + i, 3); - - dword = pci_read_config32(f0x_dev, 0x68); - dword |= (0x1 << 12); /* ATMModeEn = 1 */ - pci_write_config32(f0x_dev, 0x68, dword); - - dword = pci_read_config32(f3x_dev, 0x1b8); - dword |= (0x1 << 27); /* L3ATMModeEn = 1 */ - pci_write_config32(f3x_dev, 0x1b8, dword); - } - } - - enable_cache(); - - /* Reenable L3 and DRAM scrubbers */ - for (i = 0; i < sysconf.nodes; i++) { - struct device *f3x_dev = pcidev_on_root(0x18 + i, 3); - - pci_write_config32(f3x_dev, 0x58, f3x58[i]); - pci_write_config32(f3x_dev, 0x5c, f3x5c[i]); - } - - } -} - -static void detect_and_enable_cache_partitioning(struct device *dev) -{ - uint8_t i; - uint32_t dword; - - uint8_t nvram; - uint8_t enable_l3_cache_partitioning; - - /* Check to see if cache partitioning is allowed */ - enable_l3_cache_partitioning = 0; - if (get_option(&nvram, "l3_cache_partitioning") == CB_SUCCESS) - enable_l3_cache_partitioning = !!nvram; - - if (!enable_l3_cache_partitioning) - return; - - if (is_fam15h()) { - printk(BIOS_DEBUG, "Enabling L3 cache partitioning\n"); - - uint32_t f5x80; - uint8_t cu_enabled; - uint8_t compute_unit_count = 0; - - for (i = 0; i < sysconf.nodes; i++) { - struct device *f3x_dev = pcidev_on_root(0x18 + i, 3); - struct device *f4x_dev = pcidev_on_root(0x18 + i, 4); - struct device *f5x_dev = pcidev_on_root(0x18 + i, 5); - - /* Determine the number of active compute units on this node */ - f5x80 = pci_read_config32(f5x_dev, 0x80); - cu_enabled = f5x80 & 0xf; - if (cu_enabled == 0x1) - compute_unit_count = 1; - if (cu_enabled == 0x3) - compute_unit_count = 2; - if (cu_enabled == 0x7) - compute_unit_count = 3; - if (cu_enabled == 0xf) - compute_unit_count = 4; - - /* Disable BAN mode */ - dword = pci_read_config32(f3x_dev, 0x1b8); - dword &= ~(0x7 << 19); /* L3BanMode = 0x0 */ - pci_write_config32(f3x_dev, 0x1b8, dword); - - /* Set up cache mapping */ - dword = pci_read_config32(f4x_dev, 0x1d4); - if (compute_unit_count == 1) { - dword |= 0xf; /* ComputeUnit0SubCacheEn = 0xf */ - } - if (compute_unit_count == 2) { - dword &= ~(0xf << 4); /* ComputeUnit1SubCacheEn = 0xc */ - dword |= (0xc << 4); - dword &= ~0xf; /* ComputeUnit0SubCacheEn = 0x3 */ - dword |= 0x3; - } - if (compute_unit_count == 3) { - dword &= ~(0xf << 8); /* ComputeUnit2SubCacheEn = 0x8 */ - dword |= (0x8 << 8); - dword &= ~(0xf << 4); /* ComputeUnit1SubCacheEn = 0x4 */ - dword |= (0x4 << 4); - dword &= ~0xf; /* ComputeUnit0SubCacheEn = 0x3 */ - dword |= 0x3; - } - if (compute_unit_count == 4) { - dword &= ~(0xf << 12); /* ComputeUnit3SubCacheEn = 0x8 */ - dword |= (0x8 << 12); - dword &= ~(0xf << 8); /* ComputeUnit2SubCacheEn = 0x4 */ - dword |= (0x4 << 8); - dword &= ~(0xf << 4); /* ComputeUnit1SubCacheEn = 0x2 */ - dword |= (0x2 << 4); - dword &= ~0xf; /* ComputeUnit0SubCacheEn = 0x1 */ - dword |= 0x1; - } - pci_write_config32(f4x_dev, 0x1d4, dword); - - /* Enable cache partitioning */ - pci_write_config32(f4x_dev, 0x1d4, dword); - if (compute_unit_count == 1) { - dword &= ~(0xf << 26); /* MaskUpdateForComputeUnit = 0x1 */ - dword |= (0x1 << 26); - } else if (compute_unit_count == 2) { - dword &= ~(0xf << 26); /* MaskUpdateForComputeUnit = 0x3 */ - dword |= (0x3 << 26); - } else if (compute_unit_count == 3) { - dword &= ~(0xf << 26); /* MaskUpdateForComputeUnit = 0x7 */ - dword |= (0x7 << 26); - } else if (compute_unit_count == 4) { - dword |= (0xf << 26); /* MaskUpdateForComputeUnit = 0xf */ - } - pci_write_config32(f4x_dev, 0x1d4, dword); - } - } -} - -static void cpu_bus_init(struct device *dev) -{ - detect_and_enable_probe_filter(dev); - detect_and_enable_cache_partitioning(dev); - initialize_cpus(dev->link_list); -} - -static struct device_operations cpu_bus_ops = { - .read_resources = DEVICE_NOOP, - .set_resources = DEVICE_NOOP, - .enable_resources = DEVICE_NOOP, - .init = cpu_bus_init, - .scan_bus = cpu_bus_scan, -}; - -static void root_complex_enable_dev(struct device *dev) -{ - static int done = 0; - - /* Do not delay UMA setup, as a device on the PCI bus may evaluate - the global uma_memory variables already in its enable function. */ - if (!done) { - setup_bsp_ramtop(); - setup_uma_memory(); - done = 1; - } - - /* Set the operations if it is a special bus type */ - if (dev->path.type == DEVICE_PATH_DOMAIN) { - dev->ops = &pci_domain_ops; - } else if (dev->path.type == DEVICE_PATH_CPU_CLUSTER) { - dev->ops = &cpu_bus_ops; - } -} - -static void root_complex_finalize(void *chip_info) { -#if CONFIG(HAVE_ACPI_RESUME) && CONFIG(DIMM_DDR3) - save_mct_information_to_nvram(); -#endif -} - -struct chip_operations northbridge_amd_amdfam10_root_complex_ops = { - CHIP_NAME("AMD Family 10h/15h Root Complex") - .enable_dev = root_complex_enable_dev, - .final = root_complex_finalize, -}; diff --git a/src/northbridge/amd/amdfam10/northbridge.h b/src/northbridge/amd/amdfam10/northbridge.h deleted file mode 100644 index fdfd4c8c2c..0000000000 --- a/src/northbridge/amd/amdfam10/northbridge.h +++ /dev/null @@ -1,21 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef NORTHBRIDGE_AMD_AMDFAM10_H -#define NORTHBRIDGE_AMD_AMDFAM10_H - -u32 amdfam10_scan_root_bus(struct device *root, u32 max); - -#endif /* NORTHBRIDGE_AMD_AMDFAM10_H */ diff --git a/src/northbridge/amd/amdfam10/nums.h b/src/northbridge/amd/amdfam10/nums.h deleted file mode 100644 index 771ef12b95..0000000000 --- a/src/northbridge/amd/amdfam10/nums.h +++ /dev/null @@ -1,36 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef AMDFAM10_NUMS_H - -#define AMDFAM10_NUMS_H - -#if CONFIG_MAX_PHYSICAL_CPUS > 8 - #if CONFIG_MAX_PHYSICAL_CPUS > 32 - #define NODE_NUMS 64 - #else - #define NODE_NUMS 32 - #endif -#else - #define NODE_NUMS 8 -#endif - -// max HC installed at the same time. ...could be bigger than (48+24) if we have 3x4x4 -#define HC_NUMS 32 - -//it could be more bigger -#define HC_POSSIBLE_NUM 32 - -#endif diff --git a/src/northbridge/amd/amdfam10/pci.c b/src/northbridge/amd/amdfam10/pci.c deleted file mode 100644 index 410923a01e..0000000000 --- a/src/northbridge/amd/amdfam10/pci.c +++ /dev/null @@ -1,72 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include "pci.h" - -/* bit [10,8] are dev func, bit[1,0] are dev index */ - -u32 pci_read_config32_index(pci_devfn_t dev, u32 index_reg, u32 index) -{ - u32 dword; - - pci_write_config32(dev, index_reg, index); - dword = pci_read_config32(dev, index_reg+0x4); - return dword; -} - -#ifdef UNUSED_CODE -void pci_write_config32_index(pci_devfn_t dev, u32 index_reg, u32 index, - u32 data) -{ - - pci_write_config32(dev, index_reg, index); - - pci_write_config32(dev, index_reg + 0x4, data); - -} -#endif - -u32 pci_read_config32_index_wait(pci_devfn_t dev, u32 index_reg, - u32 index) -{ - - u32 dword; - - index &= ~(1<<30); - pci_write_config32(dev, index_reg, index); - do { - dword = pci_read_config32(dev, index_reg); - } while (!(dword & (1<<31))); - dword = pci_read_config32(dev, index_reg+0x4); - return dword; -} - -#ifdef UNUSED_CODE -void pci_write_config32_index_wait(pci_devfn_t dev, u32 index_reg, - u32 index, u32 data) -{ - - u32 dword; - - pci_write_config32(dev, index_reg + 0x4, data); - index |= (1<<30); - pci_write_config32(dev, index_reg, index); - do { - dword = pci_read_config32(dev, index_reg); - } while (!(dword & (1<<31))); - -} -#endif diff --git a/src/northbridge/amd/amdfam10/pci.h b/src/northbridge/amd/amdfam10/pci.h deleted file mode 100644 index 21623c1168..0000000000 --- a/src/northbridge/amd/amdfam10/pci.h +++ /dev/null @@ -1,26 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2016 Damien Zammit - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef AMDFAM10_PCI_H -#define AMDFAM10_PCI_H - -#include -#include -#include - -u32 pci_read_config32_index(pci_devfn_t dev, u32 index_reg, u32 index); -u32 pci_read_config32_index_wait(pci_devfn_t dev, u32 index_reg, u32 index); - -#endif diff --git a/src/northbridge/amd/amdfam10/raminit.h b/src/northbridge/amd/amdfam10/raminit.h deleted file mode 100644 index c9c57ff2c2..0000000000 --- a/src/northbridge/amd/amdfam10/raminit.h +++ /dev/null @@ -1,47 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2016 Damien Zammit - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef AMDFAM10_RAMINIT_H -#define AMDFAM10_RAMINIT_H - -#include -#include -#include - -struct sys_info; -struct DCTStatStruc; -struct MCTStatStruc; - -void activate_spd_rom(const struct mem_controller *ctrl); - -int mctRead_SPD(u32 smaddr, u32 reg); -void mctSMBhub_Init(u32 node); -void mctGet_DIMMAddr(struct DCTStatStruc *pDCTstat, u32 node); -void set_sysinfo_in_ram(u32 val); -struct sys_info *get_sysinfo(void); -void raminit_amdmct(struct sys_info *sysinfo); -void amdmct_cbmem_store_info(struct sys_info *sysinfo); -void fill_mem_ctrl(u32 controllers, struct mem_controller *ctrl_a, const u8 *spd_addr); -uint16_t mct_MaxLoadFreq(uint8_t count, uint8_t highest_rank_count, uint8_t registered, uint8_t voltage, uint16_t freq); -u8 mctGetProcessorPackageType(void); -void Set_NB32_DCT(uint32_t dev, uint8_t dct, uint32_t reg, uint32_t val); -uint32_t Get_NB32_DCT(uint32_t dev, uint8_t dct, uint32_t reg); -uint32_t Get_NB32_index_wait_DCT(uint32_t dev, uint8_t dct, uint32_t index_reg, uint32_t index); -void Set_NB32_index_wait_DCT(uint32_t dev, uint8_t dct, uint32_t index_reg, uint32_t index, uint32_t data); -void fam15h_switch_dct(uint32_t dev, uint8_t dct); -uint32_t Get_NB32_DCT_NBPstate(uint32_t dev, uint8_t dct, uint8_t nb_pstate, uint32_t reg); -void Set_NB32_DCT_NBPstate(uint32_t dev, uint8_t dct, uint8_t nb_pstate, uint32_t reg, uint32_t val); - -#endif diff --git a/src/northbridge/amd/amdfam10/raminit_amdmct.c b/src/northbridge/amd/amdfam10/raminit_amdmct.c deleted file mode 100644 index a25a1510c8..0000000000 --- a/src/northbridge/amd/amdfam10/raminit_amdmct.c +++ /dev/null @@ -1,620 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2016 Damien Zammit - * Copyright (C) 2015 Timothy Pearson , Raptor Engineering - * Copyright (C) 2007 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -/* Global allocation of sysinfo_car */ -#include -static struct sys_info sysinfo_car CAR_GLOBAL; - -struct sys_info *get_sysinfo(void) -{ - return car_get_var_ptr(&sysinfo_car); -} - -struct mem_controller; -extern int spd_read_byte(unsigned int device, unsigned int address); - -void __weak activate_spd_rom(const struct mem_controller *ctrl) -{ -} - -void fam15h_switch_dct(uint32_t dev, uint8_t dct) -{ - uint32_t dword; - - dword = Get_NB32(dev, 0x10c); - dword &= ~0x1; - dword |= (dct & 0x1); - Set_NB32(dev, 0x10c, dword); -} - -static inline void fam15h_switch_nb_pstate_config_reg(uint32_t dev, uint8_t nb_pstate) -{ - uint32_t dword; - - dword = Get_NB32(dev, 0x10c); - dword &= ~(0x3 << 4); - dword |= (nb_pstate & 0x3) << 4; - Set_NB32(dev, 0x10c, dword); -} - -uint32_t Get_NB32_DCT(uint32_t dev, uint8_t dct, uint32_t reg) -{ - if (is_fam15h()) { - /* Obtain address of function 0x1 */ - uint32_t dev_map = (dev & (~(0x7 << 12))) | (0x1 << 12); - fam15h_switch_dct(dev_map, dct); - return Get_NB32(dev, reg); - } else { - return Get_NB32(dev, (0x100 * dct) + reg); - } -} - -void Set_NB32_DCT(uint32_t dev, uint8_t dct, uint32_t reg, uint32_t val) -{ - if (is_fam15h()) { - /* Obtain address of function 0x1 */ - uint32_t dev_map = (dev & (~(0x7 << 12))) | (0x1 << 12); - fam15h_switch_dct(dev_map, dct); - Set_NB32(dev, reg, val); - } else { - Set_NB32(dev, (0x100 * dct) + reg, val); - } -} - -uint32_t Get_NB32_DCT_NBPstate(uint32_t dev, uint8_t dct, uint8_t nb_pstate, uint32_t reg) -{ - if (is_fam15h()) { - /* Obtain address of function 0x1 */ - uint32_t dev_map = (dev & (~(0x7 << 12))) | (0x1 << 12); - fam15h_switch_dct(dev_map, dct); - fam15h_switch_nb_pstate_config_reg(dev_map, nb_pstate); - return Get_NB32(dev, reg); - } else { - return Get_NB32(dev, (0x100 * dct) + reg); - } -} - -void Set_NB32_DCT_NBPstate(uint32_t dev, uint8_t dct, uint8_t nb_pstate, uint32_t reg, uint32_t val) -{ - if (is_fam15h()) { - /* Obtain address of function 0x1 */ - uint32_t dev_map = (dev & (~(0x7 << 12))) | (0x1 << 12); - fam15h_switch_dct(dev_map, dct); - fam15h_switch_nb_pstate_config_reg(dev_map, nb_pstate); - Set_NB32(dev, reg, val); - } else { - Set_NB32(dev, (0x100 * dct) + reg, val); - } -} - -uint32_t Get_NB32_index_wait_DCT(uint32_t dev, uint8_t dct, uint32_t index_reg, uint32_t index) -{ - if (is_fam15h()) { - /* Obtain address of function 0x1 */ - uint32_t dev_map = (dev & (~(0x7 << 12))) | (0x1 << 12); - fam15h_switch_dct(dev_map, dct); - return Get_NB32_index_wait(dev, index_reg, index); - } else { - return Get_NB32_index_wait(dev, (0x100 * dct) + index_reg, index); - } -} - -void Set_NB32_index_wait_DCT(uint32_t dev, uint8_t dct, uint32_t index_reg, uint32_t index, uint32_t data) -{ - if (is_fam15h()) { - /* Obtain address of function 0x1 */ - uint32_t dev_map = (dev & (~(0x7 << 12))) | (0x1 << 12); - fam15h_switch_dct(dev_map, dct); - Set_NB32_index_wait(dev, index_reg, index, data); - } else { - Set_NB32_index_wait(dev, (0x100 * dct) + index_reg, index, data); - } -} - -static uint16_t voltage_index_to_mv(uint8_t index) -{ - if (index & 0x8) - return 1150; - if (index & 0x4) - return 1250; - else if (index & 0x2) - return 1350; - else - return 1500; -} - -uint16_t mct_MaxLoadFreq(uint8_t count, uint8_t highest_rank_count, uint8_t registered, uint8_t voltage, uint16_t freq) -{ - /* FIXME - * Mainboards need to be able to specify the maximum number of DIMMs installable per channel - * For now assume a maximum of 2 DIMMs per channel can be installed - */ - uint8_t MaxDimmsInstallable = 2; - - /* Return limited maximum RAM frequency */ - if (CONFIG(DIMM_DDR2)) { - if (CONFIG(DIMM_REGISTERED) && registered) { - /* K10 BKDG Rev. 3.62 Table 53 */ - if (count > 2) { - /* Limit to DDR2-533 */ - if (freq > 266) { - freq = 266; - print_tf(__func__, ": More than 2 registered DIMMs on channel; limiting to DDR2-533\n"); - } - } - } else { - /* K10 BKDG Rev. 3.62 Table 52 */ - if (count > 1) { - /* Limit to DDR2-800 */ - if (freq > 400) { - freq = 400; - print_tf(__func__, ": More than 1 unbuffered DIMM on channel; limiting to DDR2-800\n"); - } - } - } - } else if (CONFIG(DIMM_DDR3)) { - if (voltage == 0) { - printk(BIOS_DEBUG, "%s: WARNING: Mainboard DDR3 voltage unknown, assuming 1.5V!\n", __func__); - voltage = 0x1; - } - - if (is_fam15h()) { - if (CONFIG_CPU_SOCKET_TYPE == 0x15) { - /* Socket G34 */ - if (CONFIG(DIMM_REGISTERED) && registered) { - /* Fam15h BKDG Rev. 3.14 Table 27 */ - if (voltage & 0x4) { - /* 1.25V */ - if (count > 1) { - if (highest_rank_count > 1) { - /* Limit to DDR3-1066 */ - if (freq > 533) { - freq = 533; - printk(BIOS_DEBUG, "%s: More than 1 registered DIMM on %dmV channel; limiting to DDR3-1066\n", __func__, voltage_index_to_mv(voltage)); - } - } else { - /* Limit to DDR3-1333 */ - if (freq > 666) { - freq = 666; - printk(BIOS_DEBUG, "%s: More than 1 registered DIMM on %dmV channel; limiting to DDR3-1333\n", __func__, voltage_index_to_mv(voltage)); - } - } - } else { - /* Limit to DDR3-1333 */ - if (freq > 666) { - freq = 666; - printk(BIOS_DEBUG, "%s: 1 registered DIMM on %dmV channel; limiting to DDR3-1333\n", __func__, voltage_index_to_mv(voltage)); - } - } - } else if (voltage & 0x2) { - /* 1.35V */ - if (count > 1) { - /* Limit to DDR3-1333 */ - if (freq > 666) { - freq = 666; - printk(BIOS_DEBUG, "%s: More than 1 registered DIMM on %dmV channel; limiting to DDR3-1333\n", __func__, voltage_index_to_mv(voltage)); - } - } else { - /* Limit to DDR3-1600 */ - if (freq > 800) { - freq = 800; - printk(BIOS_DEBUG, "%s: 1 registered DIMM on %dmV channel; limiting to DDR3-1600\n", __func__, voltage_index_to_mv(voltage)); - } - } - } else if (voltage & 0x1) { - /* 1.50V */ - if (count > 1) { - /* Limit to DDR3-1600 */ - if (freq > 800) { - freq = 800; - printk(BIOS_DEBUG, "%s: More than 1 registered DIMM on %dmV channel; limiting to DDR3-1600\n", __func__, voltage_index_to_mv(voltage)); - } - } else { - /* Limit to DDR3-1866 */ - if (freq > 933) { - freq = 933; - printk(BIOS_DEBUG, "%s: 1 registered DIMM on %dmV channel; limiting to DDR3-1866\n", __func__, voltage_index_to_mv(voltage)); - } - } - } - } else { - /* Fam15h BKDG Rev. 3.14 Table 26 */ - if (voltage & 0x4) { - /* 1.25V */ - if (count > 1) { - if (highest_rank_count > 1) { - /* Limit to DDR3-1066 */ - if (freq > 533) { - freq = 533; - printk(BIOS_DEBUG, "%s: More than 1 unbuffered DIMM on %dmV channel; limiting to DDR3-1066\n", __func__, voltage_index_to_mv(voltage)); - } - } else { - /* Limit to DDR3-1333 */ - if (freq > 666) { - freq = 666; - printk(BIOS_DEBUG, "%s: More than 1 unbuffered DIMM on %dmV channel; limiting to DDR3-1333\n", __func__, voltage_index_to_mv(voltage)); - } - } - } else { - /* Limit to DDR3-1333 */ - if (freq > 666) { - freq = 666; - printk(BIOS_DEBUG, "%s: 1 unbuffered DIMM on %dmV channel; limiting to DDR3-1333\n", __func__, voltage_index_to_mv(voltage)); - } - } - } else if (voltage & 0x2) { - /* 1.35V */ - if (MaxDimmsInstallable > 1) { - /* Limit to DDR3-1333 */ - if (freq > 666) { - freq = 666; - printk(BIOS_DEBUG, "%s: More than 1 unbuffered DIMM on %dmV channel; limiting to DDR3-1333\n", __func__, voltage_index_to_mv(voltage)); - } - } else { - /* Limit to DDR3-1600 */ - if (freq > 800) { - freq = 800; - printk(BIOS_DEBUG, "%s: 1 unbuffered DIMM on %dmV channel; limiting to DDR3-1600\n", __func__, voltage_index_to_mv(voltage)); - } - } - } else if (voltage & 0x1) { - if (MaxDimmsInstallable == 1) { - if (count > 1) { - /* Limit to DDR3-1600 */ - if (freq > 800) { - freq = 800; - printk(BIOS_DEBUG, "%s: More than 1 unbuffered DIMM on %dmV channel; limiting to DDR3-1600\n", __func__, voltage_index_to_mv(voltage)); - } - } else { - /* Limit to DDR3-1866 */ - if (freq > 933) { - freq = 933; - printk(BIOS_DEBUG, "%s: 1 unbuffered DIMM on %dmV channel; limiting to DDR3-1866\n", __func__, voltage_index_to_mv(voltage)); - } - } - } else { - if (count > 1) { - if (highest_rank_count > 1) { - /* Limit to DDR3-1333 */ - if (freq > 666) { - freq = 666; - printk(BIOS_DEBUG, "%s: More than 1 unbuffered DIMM on %dmV channel; limiting to DDR3-1333\n", __func__, voltage_index_to_mv(voltage)); - } - } else { - /* Limit to DDR3-1600 */ - if (freq > 800) { - freq = 800; - printk(BIOS_DEBUG, "%s: More than 1 unbuffered DIMM on %dmV channel; limiting to DDR3-1600\n", __func__, voltage_index_to_mv(voltage)); - } - } - } else { - /* Limit to DDR3-1600 */ - if (freq > 800) { - freq = 800; - printk(BIOS_DEBUG, "%s: 1 unbuffered DIMM on %dmV channel; limiting to DDR3-1600\n", __func__, voltage_index_to_mv(voltage)); - } - } - } - } - } - } else if (CONFIG_CPU_SOCKET_TYPE == 0x14) { - /* Socket C32 */ - if (CONFIG(DIMM_REGISTERED) && registered) { - /* Fam15h BKDG Rev. 3.14 Table 30 */ - if (voltage & 0x4) { - /* 1.25V */ - if (count > 1) { - if (highest_rank_count > 2) { - /* Limit to DDR3-800 */ - if (freq > 400) { - freq = 400; - printk(BIOS_DEBUG, "%s: More than 1 registered DIMM on %dmV channel; limiting to DDR3-800\n", __func__, voltage_index_to_mv(voltage)); - } - } else { - /* Limit to DDR3-1333 */ - if (freq > 666) { - freq = 666; - printk(BIOS_DEBUG, "%s: More than 1 registered DIMM on %dmV channel; limiting to DDR3-1333\n", __func__, voltage_index_to_mv(voltage)); - } - } - } else { - /* Limit to DDR3-1333 */ - if (freq > 666) { - freq = 666; - printk(BIOS_DEBUG, "%s: 1 registered DIMM on %dmV channel; limiting to DDR3-1333\n", __func__, voltage_index_to_mv(voltage)); - } - } - } else if (voltage & 0x2) { - /* 1.35V */ - if (count > 1) { - if (highest_rank_count > 2) { - /* Limit to DDR3-800 */ - if (freq > 400) { - freq = 400; - printk(BIOS_DEBUG, "%s: More than 1 registered DIMM on %dmV channel; limiting to DDR3-800\n", __func__, voltage_index_to_mv(voltage)); - } - } else if (highest_rank_count > 1) { - /* Limit to DDR3-1066 */ - if (freq > 533) { - freq = 533; - printk(BIOS_DEBUG, "%s: More than 1 registered DIMM on %dmV channel; limiting to DDR3-1066\n", __func__, voltage_index_to_mv(voltage)); - } - } else { - /* Limit to DDR3-1333 */ - if (freq > 666) { - freq = 666; - printk(BIOS_DEBUG, "%s: More than 1 registered DIMM on %dmV channel; limiting to DDR3-1333\n", __func__, voltage_index_to_mv(voltage)); - } - } - } else { - /* Limit to DDR3-1600 */ - if (freq > 800) { - freq = 800; - printk(BIOS_DEBUG, "%s: 1 registered DIMM on %dmV channel; limiting to DDR3-1600\n", __func__, voltage_index_to_mv(voltage)); - } - } - } else if (voltage & 0x1) { - /* 1.50V */ - if (count > 1) { - if (highest_rank_count > 2) { - /* Limit to DDR3-800 */ - if (freq > 400) { - freq = 400; - printk(BIOS_DEBUG, "%s: More than 1 registered DIMM on %dmV channel; limiting to DDR3-800\n", __func__, voltage_index_to_mv(voltage)); - } - } else if (highest_rank_count > 1) { - /* Limit to DDR3-1066 */ - if (freq > 533) { - freq = 533; - printk(BIOS_DEBUG, "%s: More than 1 registered DIMM on %dmV channel; limiting to DDR3-1066\n", __func__, voltage_index_to_mv(voltage)); - } - } else { - /* Limit to DDR3-1333 */ - if (freq > 666) { - freq = 666; - printk(BIOS_DEBUG, "%s: More than 1 registered DIMM on %dmV channel; limiting to DDR3-1333\n", __func__, voltage_index_to_mv(voltage)); - } - } - } else { - if (highest_rank_count > 2) { - /* Limit to DDR3-1333 */ - if (freq > 666) { - freq = 666; - printk(BIOS_DEBUG, "%s: More than 1 registered DIMM on %dmV channel; limiting to DDR3-1333\n", __func__, voltage_index_to_mv(voltage)); - } - } else { - /* Limit to DDR3-1600 */ - if (freq > 800) { - freq = 800; - printk(BIOS_DEBUG, "%s: More than 1 registered DIMM on %dmV channel; limiting to DDR3-1600\n", __func__, voltage_index_to_mv(voltage)); - } - } - } - } - } else { - /* Fam15h BKDG Rev. 3.14 Table 29 */ - if (voltage & 0x4) { - /* 1.25V */ - if (count > 1) { - /* Limit to DDR3-1066 */ - if (freq > 533) { - freq = 533; - printk(BIOS_DEBUG, "%s: More than 1 unbuffered DIMM on %dmV channel; limiting to DDR3-1066\n", __func__, voltage_index_to_mv(voltage)); - } - } else { - /* Limit to DDR3-1333 */ - if (freq > 666) { - freq = 666; - printk(BIOS_DEBUG, "%s: 1 unbuffered DIMM on %dmV channel; limiting to DDR3-1333\n", __func__, voltage_index_to_mv(voltage)); - } - } - } else if (voltage & 0x2) { - if (count > 1) { - if (highest_rank_count > 1) { - /* Limit to DDR3-1066 */ - if (freq > 533) { - freq = 533; - printk(BIOS_DEBUG, "%s: More than 1 unbuffered DIMM on %dmV channel; limiting to DDR3-1066\n", __func__, voltage_index_to_mv(voltage)); - } - } else { - /* Limit to DDR3-1333 */ - if (freq > 666) { - freq = 666; - printk(BIOS_DEBUG, "%s: More than 1 unbuffered DIMM on %dmV channel; limiting to DDR3-1333\n", __func__, voltage_index_to_mv(voltage)); - } - } - } else { - /* Limit to DDR3-1333 */ - if (freq > 666) { - freq = 666; - printk(BIOS_DEBUG, "%s: 1 unbuffered DIMM on %dmV channel; limiting to DDR3-1333\n", __func__, voltage_index_to_mv(voltage)); - } - } - } else if (voltage & 0x1) { - if (MaxDimmsInstallable == 1) { - /* Limit to DDR3-1600 */ - if (freq > 800) { - freq = 800; - printk(BIOS_DEBUG, "%s: 1 unbuffered DIMM on %dmV channel; limiting to DDR3-1600\n", __func__, voltage_index_to_mv(voltage)); - } - } else { - if (count > 1) { - if (highest_rank_count > 1) { - /* Limit to DDR3-1066 */ - if (freq > 533) { - freq = 533; - printk(BIOS_DEBUG, "%s: More than 1 unbuffered DIMM on %dmV channel; limiting to DDR3-1066\n", __func__, voltage_index_to_mv(voltage)); - } - } else { - /* Limit to DDR3-1333 */ - if (freq > 666) { - freq = 666; - printk(BIOS_DEBUG, "%s: More than 1 unbuffered DIMM on %dmV channel; limiting to DDR3-1333\n", __func__, voltage_index_to_mv(voltage)); - } - } - } else { - /* Limit to DDR3-1600 */ - if (freq > 800) { - freq = 800; - printk(BIOS_DEBUG, "%s: 1 unbuffered DIMM on %dmV channel; limiting to DDR3-1600\n", __func__, voltage_index_to_mv(voltage)); - } - } - } - } - } - } else { - /* TODO - * Other socket support unimplemented - */ - } - } else { - if (CONFIG(DIMM_REGISTERED) && registered) { - /* K10 BKDG Rev. 3.62 Table 34 */ - if (count > 2) { - /* Limit to DDR3-800 */ - if (freq > 400) { - freq = 400; - printk(BIOS_DEBUG, "%s: More than 2 registered DIMMs on %dmV channel; limiting to DDR3-800\n", __func__, voltage_index_to_mv(voltage)); - } - } else if (count == 2) { - /* Limit to DDR3-1066 */ - if (freq > 533) { - freq = 533; - printk(BIOS_DEBUG, "%s: 2 registered DIMMs on %dmV channel; limiting to DDR3-1066\n", __func__, voltage_index_to_mv(voltage)); - } - } else { - /* Limit to DDR3-1333 */ - if (freq > 666) { - freq = 666; - printk(BIOS_DEBUG, "%s: 1 registered DIMM on %dmV channel; limiting to DDR3-1333\n", __func__, voltage_index_to_mv(voltage)); - } - } - } else { - /* K10 BKDG Rev. 3.62 Table 33 */ - /* Limit to DDR3-1333 */ - if (freq > 666) { - freq = 666; - printk(BIOS_DEBUG, "%s: unbuffered DIMMs on %dmV channel; limiting to DDR3-1333\n", __func__, voltage_index_to_mv(voltage)); - } - } - } - } - - return freq; -} - -int mctRead_SPD(u32 smaddr, u32 reg) -{ - return spd_read_byte(smaddr, reg); -} - - -void mctSMBhub_Init(u32 node) -{ - struct sys_info *sysinfo = &sysinfo_car; - struct mem_controller *ctrl = &(sysinfo->ctrl[node]); - activate_spd_rom(ctrl); -} - - -void mctGet_DIMMAddr(struct DCTStatStruc *pDCTstat, u32 node) -{ - int j; - struct sys_info *sysinfo = &sysinfo_car; - struct mem_controller *ctrl = &(sysinfo->ctrl[node]); - - for (j = 0; j < DIMM_SOCKETS; j++) { - pDCTstat->DIMMAddr[j*2] = ctrl->spd_addr[j] & 0xff; - pDCTstat->DIMMAddr[j*2+1] = ctrl->spd_addr[DIMM_SOCKETS + j] & 0xff; - } - -} - -#if CONFIG(SET_FIDVID) -u8 mctGetProcessorPackageType(void) { - /* FIXME: I guess this belongs wherever mctGetLogicalCPUID ends up ? */ - u32 BrandId = cpuid_ebx(0x80000001); - return (u8)((BrandId >> 28) & 0x0F); -} -#endif - -void raminit_amdmct(struct sys_info *sysinfo) -{ - struct MCTStatStruc *pMCTstat = &(sysinfo->MCTstat); - struct DCTStatStruc *pDCTstatA = sysinfo->DCTstatA; - - printk(BIOS_DEBUG, "raminit_amdmct begin:\n"); - timestamp_add_now(TS_BEFORE_INITRAM); - - mctAutoInitMCT_D(pMCTstat, pDCTstatA); - - timestamp_add_now(TS_AFTER_INITRAM); - printk(BIOS_DEBUG, "raminit_amdmct end:\n"); -} - -void amdmct_cbmem_store_info(struct sys_info *sysinfo) -{ - if (!sysinfo) - return; - - /* Save memory info structures for use in ramstage */ - size_t i; - struct DCTStatStruc *pDCTstatA = NULL; - - if (!acpi_is_wakeup_s3()) { - /* Allocate memory */ - struct amdmct_memory_info *mem_info; - mem_info = cbmem_add(CBMEM_ID_AMDMCT_MEMINFO, sizeof(struct amdmct_memory_info)); - if (!mem_info) - return; - - printk(BIOS_DEBUG, "%s: Storing AMDMCT configuration in CBMEM\n", __func__); - - /* Initialize memory */ - memset(mem_info, 0, sizeof(struct amdmct_memory_info)); - - /* Copy data */ - memcpy(&mem_info->mct_stat, &sysinfo->MCTstat, sizeof(struct MCTStatStruc)); - for (i = 0; i < MAX_NODES_SUPPORTED; i++) { - pDCTstatA = sysinfo->DCTstatA + i; - memcpy(&mem_info->dct_stat[i], pDCTstatA, sizeof(struct DCTStatStruc)); - } - mem_info->ecc_enabled = mctGet_NVbits(NV_ECC_CAP); - mem_info->ecc_scrub_rate = mctGet_NVbits(NV_DramBKScrub); - - /* Zero out invalid/unused pointers */ -#if CONFIG(DIMM_DDR3) - for (i = 0; i < MAX_NODES_SUPPORTED; i++) { - mem_info->dct_stat[i].C_MCTPtr = NULL; - mem_info->dct_stat[i].C_DCTPtr[0] = NULL; - mem_info->dct_stat[i].C_DCTPtr[1] = NULL; - } -#endif - } -} diff --git a/src/northbridge/amd/amdfam10/raminit_sysinfo_in_ram.c b/src/northbridge/amd/amdfam10/raminit_sysinfo_in_ram.c deleted file mode 100644 index 218df75887..0000000000 --- a/src/northbridge/amd/amdfam10/raminit_sysinfo_in_ram.c +++ /dev/null @@ -1,81 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include -#include - -static void set_htic_bit(u8 i, u32 val, u8 bit) -{ - u32 dword; - dword = pci_read_config32(NODE_PCI(i, 0), HT_INIT_CONTROL); - dword &= ~(1<node_id = i; - ctrl->f0 = NODE_PCI(i, 0); - ctrl->f1 = NODE_PCI(i, 1); - ctrl->f2 = NODE_PCI(i, 2); - ctrl->f3 = NODE_PCI(i, 3); - ctrl->f4 = NODE_PCI(i, 4); - ctrl->f5 = NODE_PCI(i, 5); - - if (spd_addr == (void *)0) continue; - - ctrl->spd_switch_addr = spd_addr[index++]; - - for (j = 0; j < 8; j++) { - ctrl->spd_addr[j] = spd_addr[index++]; - - } - } -} - -void set_sysinfo_in_ram(u32 val) -{ - set_htic_bit(0, val, 9); -} diff --git a/src/northbridge/amd/amdfam10/reset_test.c b/src/northbridge/amd/amdfam10/reset_test.c deleted file mode 100644 index 76d1144e7d..0000000000 --- a/src/northbridge/amd/amdfam10/reset_test.c +++ /dev/null @@ -1,136 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include -#include -#include - -/* mmconf is not ready */ -/* io_ext is not ready */ -u32 cpu_init_detected(u8 nodeid) -{ - u32 htic; - pci_devfn_t dev; - - dev = NODE_PCI(nodeid, 0); - htic = pci_io_read_config32(dev, HT_INIT_CONTROL); - - return !!(htic & HTIC_INIT_Detect); -} - -u32 bios_reset_detected(void) -{ - u32 htic; - htic = pci_io_read_config32(PCI_DEV(CONFIG_CBB, CONFIG_CDB, 0), HT_INIT_CONTROL); - - return (htic & HTIC_ColdR_Detect) && !(htic & HTIC_BIOSR_Detect); -} - -u32 cold_reset_detected(void) -{ - u32 htic; - htic = pci_io_read_config32(PCI_DEV(CONFIG_CBB, CONFIG_CDB, 0), HT_INIT_CONTROL); - - return !(htic & HTIC_ColdR_Detect); -} - -u32 other_reset_detected(void) // other warm reset not started by BIOS -{ - u32 htic; - htic = pci_io_read_config32(PCI_DEV(CONFIG_CBB, CONFIG_CDB, 0), HT_INIT_CONTROL); - - return (htic & HTIC_ColdR_Detect) && (htic & HTIC_BIOSR_Detect); -} - -void distinguish_cpu_resets(u8 nodeid) -{ - u32 htic; - pci_devfn_t device; - device = NODE_PCI(nodeid, 0); - htic = pci_io_read_config32(device, HT_INIT_CONTROL); - htic |= HTIC_ColdR_Detect | HTIC_BIOSR_Detect | HTIC_INIT_Detect; - pci_io_write_config32(device, HT_INIT_CONTROL, htic); -} - -u32 warm_reset_detect(u8 nodeid) -{ - u32 htic; - pci_devfn_t device; - device = NODE_PCI(nodeid, 0); - htic = pci_io_read_config32(device, HT_INIT_CONTROL); - return (htic & HTIC_ColdR_Detect) && !(htic & HTIC_BIOSR_Detect); -} - -void set_bios_reset(void) -{ - - u32 nodes; - u32 htic; - pci_devfn_t dev; - int i; - - nodes = ((pci_read_config32(PCI_DEV(CONFIG_CBB, CONFIG_CDB, 0), 0x60) >> 4) & 7) + 1; - - for (i = 0; i < nodes; i++) { - dev = NODE_PCI(i,0); - htic = pci_read_config32(dev, HT_INIT_CONTROL); - htic &= ~HTIC_BIOSR_Detect; - pci_write_config32(dev, HT_INIT_CONTROL, htic); - } -} - - -/* Look up a which bus a given node/link combination is on. - * return 0 when we can't find the answer. - */ -static u8 node_link_to_bus(u8 node, u8 link) // node are 6 bit, and link three bit -{ - u32 reg; - u32 val; - - // put node and link in correct bit - val = ((node & 0x0f)<<4) | ((node & 0x30)<< (12-4)) | ((link & 0x07)<<8); - - for (reg = 0xE0; reg < 0xF0; reg += 0x04) { - u32 config_map; - config_map = pci_io_read_config32(PCI_DEV(CONFIG_CBB, CONFIG_CDB, 1), reg); - if ((config_map & 3) != 3) { - continue; - } - if ((config_map & (((63 & 0x0f)<<4) | ((63 & 0x30)<< (12-4)) | ((7 & 0x07)<<8)) - ) == val) - { - return (config_map >> 16) & 0xff; - } - } - - return 0; -} - -u32 get_sblk(void) -{ - u32 reg; - /* read PCI_DEV(CONFIG_CBB,CONFIG_CDB,0) 0x64 bit [8:9] to find out SbLink m */ - reg = pci_io_read_config32(PCI_DEV(CONFIG_CBB, CONFIG_CDB, 0), 0x64); - return ((reg>>8) & 3); -} - - -u8 get_sbbusn(u8 sblk) -{ - return node_link_to_bus(0, sblk); -} diff --git a/src/northbridge/amd/amdfam10/resourcemap.c b/src/northbridge/amd/amdfam10/resourcemap.c deleted file mode 100644 index fa4ab3cfd7..0000000000 --- a/src/northbridge/amd/amdfam10/resourcemap.c +++ /dev/null @@ -1,282 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -static void setup_default_resource_map(void) -{ - static const u32 register_values[] = { - /* Careful set limit registers before base registers which contain - the enables */ - /* DRAM Limit i Registers - * F1:0x44 i = 0 - * F1:0x4C i = 1 - * F1:0x54 i = 2 - * F1:0x5C i = 3 - * F1:0x64 i = 4 - * F1:0x6C i = 5 - * F1:0x74 i = 6 - * F1:0x7C i = 7 - * [ 2: 0] Destination Node ID - * 000 = Node 0 - * 001 = Node 1 - * 010 = Node 2 - * 011 = Node 3 - * 100 = Node 4 - * 101 = Node 5 - * 110 = Node 6 - * 111 = Node 7 - * [ 7: 3] Reserved - * [10: 8] Interleave select - * specifies the values of A[14:12] to use with - * interleave enable. - * [15:11] Reserved - * [31:16] DRAM Limit Address i Bits 39-24 - * This field defines the upper address bits of a 40 bit - * address that define the end of the DRAM region. - */ - ADDRMAP_REG(0x44), 0x0000f8f8, 0x00000000, - ADDRMAP_REG(0x4C), 0x0000f8f8, 0x00000001, - ADDRMAP_REG(0x54), 0x0000f8f8, 0x00000002, - ADDRMAP_REG(0x5C), 0x0000f8f8, 0x00000003, - ADDRMAP_REG(0x64), 0x0000f8f8, 0x00000004, - ADDRMAP_REG(0x6C), 0x0000f8f8, 0x00000005, - ADDRMAP_REG(0x74), 0x0000f8f8, 0x00000006, - ADDRMAP_REG(0x7C), 0x0000f8f8, 0x00000007, - /* DRAM Base i Registers - * F1:0x40 i = 0 - * F1:0x48 i = 1 - * F1:0x50 i = 2 - * F1:0x58 i = 3 - * F1:0x60 i = 4 - * F1:0x68 i = 5 - * F1:0x70 i = 6 - * F1:0x78 i = 7 - * [ 0: 0] Read Enable - * 0 = Reads Disabled - * 1 = Reads Enabled - * [ 1: 1] Write Enable - * 0 = Writes Disabled - * 1 = Writes Enabled - * [ 7: 2] Reserved - * [10: 8] Interleave Enable - * 000 = No interleave - * 001 = Interleave on A[12] (2 nodes) - * 010 = reserved - * 011 = Interleave on A[12] and A[14] (4 nodes) - * 100 = reserved - * 101 = reserved - * 110 = reserved - * 111 = Interleve on A[12] and A[13] and A[14] (8 nodes) - * [15:11] Reserved - * [13:16] DRAM Base Address i Bits 39-24 - * This field defines the upper address bits of a 40-bit - * address that define the start of the DRAM region. - */ - ADDRMAP_REG(0x40), 0x0000f8fc, 0x00000000, - ADDRMAP_REG(0x48), 0x0000f8fc, 0x00000000, - ADDRMAP_REG(0x50), 0x0000f8fc, 0x00000000, - ADDRMAP_REG(0x58), 0x0000f8fc, 0x00000000, - ADDRMAP_REG(0x60), 0x0000f8fc, 0x00000000, - ADDRMAP_REG(0x68), 0x0000f8fc, 0x00000000, - ADDRMAP_REG(0x70), 0x0000f8fc, 0x00000000, - ADDRMAP_REG(0x78), 0x0000f8fc, 0x00000000, - - /* Memory-Mapped I/O Limit i Registers - * F1:0x84 i = 0 - * F1:0x8C i = 1 - * F1:0x94 i = 2 - * F1:0x9C i = 3 - * F1:0xA4 i = 4 - * F1:0xAC i = 5 - * F1:0xB4 i = 6 - * F1:0xBC i = 7 - * [ 2: 0] Destination Node ID - * 000 = Node 0 - * 001 = Node 1 - * 010 = Node 2 - * 011 = Node 3 - * 100 = Node 4 - * 101 = Node 5 - * 110 = Node 6 - * 111 = Node 7 - * [ 3: 3] Reserved - * [ 5: 4] Destination Link ID - * 00 = Link 0 - * 01 = Link 1 - * 10 = Link 2 - * 11 = Reserved - * [ 6: 6] Reserved - * [ 7: 7] Non-Posted - * 0 = CPU writes may be posted - * 1 = CPU writes must be non-posted - * [31: 8] Memory-Mapped I/O Limit Address i (39-16) - * This field defines the upp address bits of a 40-bit - * address that defines the end of a memory-mapped - * I/O region n - */ - ADDRMAP_REG(0x84), 0x00000048, 0x00000000, - ADDRMAP_REG(0x8C), 0x00000048, 0x00000000, - ADDRMAP_REG(0x94), 0x00000048, 0x00000000, - ADDRMAP_REG(0x9C), 0x00000048, 0x00000000, - ADDRMAP_REG(0xA4), 0x00000048, 0x00000000, - ADDRMAP_REG(0xAC), 0x00000048, 0x00000000, - ADDRMAP_REG(0xB4), 0x00000048, 0x00000000, - ADDRMAP_REG(0xBC), 0x00000048, 0x00ffff00, - - /* Memory-Mapped I/O Base i Registers - * F1:0x80 i = 0 - * F1:0x88 i = 1 - * F1:0x90 i = 2 - * F1:0x98 i = 3 - * F1:0xA0 i = 4 - * F1:0xA8 i = 5 - * F1:0xB0 i = 6 - * F1:0xB8 i = 7 - * [ 0: 0] Read Enable - * 0 = Reads disabled - * 1 = Reads Enabled - * [ 1: 1] Write Enable - * 0 = Writes disabled - * 1 = Writes Enabled - * [ 2: 2] Cpu Disable - * 0 = Cpu can use this I/O range - * 1 = Cpu requests do not use this I/O range - * [ 3: 3] Lock - * 0 = base/limit registers i are read/write - * 1 = base/limit registers i are read-only - * [ 7: 4] Reserved - * [31: 8] Memory-Mapped I/O Base Address i (39-16) - * This field defines the upper address bits of a 40bit - * address that defines the start of memory-mapped - * I/O region i - */ - ADDRMAP_REG(0x80), 0x000000f0, 0x00000000, - ADDRMAP_REG(0x88), 0x000000f0, 0x00000000, - ADDRMAP_REG(0x90), 0x000000f0, 0x00000000, - ADDRMAP_REG(0x98), 0x000000f0, 0x00000000, - ADDRMAP_REG(0xA0), 0x000000f0, 0x00000000, - ADDRMAP_REG(0xA8), 0x000000f0, 0x00000000, - ADDRMAP_REG(0xB0), 0x000000f0, 0x00000000, - ADDRMAP_REG(0xB8), 0x000000f0, 0x00fc0003, - - /* PCI I/O Limit i Registers - * F1:0xC4 i = 0 - * F1:0xCC i = 1 - * F1:0xD4 i = 2 - * F1:0xDC i = 3 - * [ 2: 0] Destination Node ID - * 000 = Node 0 - * 001 = Node 1 - * 010 = Node 2 - * 011 = Node 3 - * 100 = Node 4 - * 101 = Node 5 - * 110 = Node 6 - * 111 = Node 7 - * [ 3: 3] Reserved - * [ 5: 4] Destination Link ID - * 00 = Link 0 - * 01 = Link 1 - * 10 = Link 2 - * 11 = reserved - * [11: 6] Reserved - * [24:12] PCI I/O Limit Address i - * This field defines the end of PCI I/O region n - * [31:25] Reserved - */ - ADDRMAP_REG(0xC4), 0xFE000FC8, 0x01fff000, - ADDRMAP_REG(0xCC), 0xFE000FC8, 0x00000000, - ADDRMAP_REG(0xD4), 0xFE000FC8, 0x00000000, - ADDRMAP_REG(0xDC), 0xFE000FC8, 0x00000000, - - /* PCI I/O Base i Registers - * F1:0xC0 i = 0 - * F1:0xC8 i = 1 - * F1:0xD0 i = 2 - * F1:0xD8 i = 3 - * [ 0: 0] Read Enable - * 0 = Reads Disabled - * 1 = Reads Enabled - * [ 1: 1] Write Enable - * 0 = Writes Disabled - * 1 = Writes Enabled - * [ 3: 2] Reserved - * [ 4: 4] VGA Enable - * 0 = VGA matches Disabled - * 1 = matches all address < 64K and where A[9:0] is in - * the range 3B0-3BB or 3C0-3DF independent of the - * base & limit registers - * [ 5: 5] ISA Enable - * 0 = ISA matches Disabled - * 1 = Blocks address < 64K and in the last 768 bytes of - * eack 1K block from matching agains this base/limit - * pair - * [11: 6] Reserved - * [24:12] PCI I/O Base i - * This field defines the start of PCI I/O region n - * [31:25] Reserved - */ - ADDRMAP_REG(0xC0), 0xFE000FCC, 0x00000003, - ADDRMAP_REG(0xC8), 0xFE000FCC, 0x00000000, - ADDRMAP_REG(0xD0), 0xFE000FCC, 0x00000000, - ADDRMAP_REG(0xD8), 0xFE000FCC, 0x00000000, - - /* Config Base and Limit i Registers - * F1:0xE0 i = 0 - * F1:0xE4 i = 1 - * F1:0xE8 i = 2 - * F1:0xEC i = 3 - * [ 0: 0] Read Enable - * 0 = Reads Disabled - * 1 = Reads Enabled - * [ 1: 1] Write Enable - * 0 = Writes Disabled - * 1 = Writes Enabled - * [ 2: 2] Device Number Compare Enable - * 0 = The ranges are based on bus number - * 1 = The ranges are ranges of devices on bus 0 - * [ 3: 3] Reserved - * [ 6: 4] Destination Node - * 000 = Node 0 - * 001 = Node 1 - * 010 = Node 2 - * 011 = Node 3 - * 100 = Node 4 - * 101 = Node 5 - * 110 = Node 6 - * 111 = Node 7 - * [ 7: 7] Reserved - * [ 9: 8] Destination Link - * 00 = Link 0 - * 01 = Link 1 - * 10 = Link 2 - * 11 - Reserved - * [15:10] Reserved - * [23:16] Bus Number Base i - * This field defines the lowest bus number in - * configuration region i - * [31:24] Bus Number Limit i - * This field defines the highest bus number in - * configuration regin i - */ - ADDRMAP_REG(0xE0), 0x0000FC88, 0xff000003, - ADDRMAP_REG(0xE4), 0x0000FC88, 0x00000000, - ADDRMAP_REG(0xE8), 0x0000FC88, 0x00000000, - ADDRMAP_REG(0xEC), 0x0000FC88, 0x00000000, - }; - - u32 max; - max = ARRAY_SIZE(register_values); - setup_resource_map(register_values, max); -} diff --git a/src/northbridge/amd/amdfam10/setup_resource_map.c b/src/northbridge/amd/amdfam10/setup_resource_map.c deleted file mode 100644 index 735d72bbf7..0000000000 --- a/src/northbridge/amd/amdfam10/setup_resource_map.c +++ /dev/null @@ -1,184 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2015 Timothy Pearson , Raptor Engineering - * Copyright (C) 2007 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include -#include -#include -#include - -#define RES_DEBUG 0 - -void setup_resource_map(const u32 *register_values, u32 max) -{ - u32 i; - - for (i = 0; i < max; i += 3) { - pci_devfn_t dev; - u32 where; - u32 reg; - - dev = register_values[i] & ~0xfff; - where = register_values[i] & 0xfff; - reg = pci_read_config32(dev, where); - reg &= register_values[i+1]; - reg |= register_values[i+2]; - pci_write_config32(dev, where, reg); - } -} - - -void setup_resource_map_offset(const u32 *register_values, u32 max, u32 offset_pci_dev, u32 offset_io_base) -{ - u32 i; - - for (i = 0; i < max; i += 3) { - pci_devfn_t dev; - u32 where; - unsigned long reg; - dev = (register_values[i] & ~0xfff) + offset_pci_dev; - where = register_values[i] & 0xfff; - reg = pci_read_config32(dev, where); - reg &= register_values[i+1]; - reg |= register_values[i+2] + offset_io_base; - pci_write_config32(dev, where, reg); - } -} - -void setup_resource_map_x_offset(const u32 *register_values, u32 max, u32 offset_pci_dev, u32 offset_io_base) -{ - u32 i; - - if (RES_DEBUG) - printk(BIOS_DEBUG, "setting up resource map ex offset....\n"); - - for (i = 0; i < max; i += 4) { - if (RES_DEBUG) - printk(BIOS_DEBUG, "%04x: %02x %08x <- & %08x | %08x\n", - i/4, register_values[i], - register_values[i+1] + ((register_values[i]==RES_PCI_IO) ? offset_pci_dev : 0), - register_values[i+2], - register_values[i+3] + (((register_values[i] & RES_PORT_IO_32) == RES_PORT_IO_32) ? offset_io_base : 0) - ); - switch (register_values[i]) { - case RES_PCI_IO: //PCI - { - pci_devfn_t dev; - u32 where; - u32 reg; - dev = (register_values[i+1] & ~0xfff) + offset_pci_dev; - where = register_values[i+1] & 0xfff; - reg = pci_read_config32(dev, where); - if (RES_DEBUG) - printk(BIOS_SPEW, "WAS: %08x\n", reg); - reg &= register_values[i+2]; - reg |= register_values[i+3]; - pci_write_config32(dev, where, reg); - if (RES_DEBUG) - printk(BIOS_SPEW, "NOW: %08x\n", reg); - } - break; - case RES_PORT_IO_8: // io 8 - { - u32 where; - u32 reg; - where = register_values[i+1] + offset_io_base; - reg = inb(where); - if (RES_DEBUG) - printk(BIOS_SPEW, "WAS: %08x\n", reg); - reg &= register_values[i+2]; - reg |= register_values[i+3]; - outb(reg, where); - if (RES_DEBUG) - printk(BIOS_SPEW, "NOW: %08x\n", reg); - } - break; - case RES_PORT_IO_32: //io32 - { - u32 where; - u32 reg; - where = register_values[i+1] + offset_io_base; - reg = inl(where); - if (RES_DEBUG) - printk(BIOS_SPEW, "WAS: %08x\n", reg); - reg &= register_values[i+2]; - reg |= register_values[i+3]; - outl(reg, where); - if (RES_DEBUG) - printk(BIOS_SPEW, "NOW: %08x\n", reg); - } - break; - } - } - - if (RES_DEBUG) - printk(BIOS_DEBUG, "done.\n"); -} - -void setup_resource_map_x(const u32 *register_values, u32 max) -{ - u32 i; - - if (RES_DEBUG) - printk(BIOS_DEBUG, "setting up resource map ex offset....\n"); - - for (i = 0; i < max; i += 4) { - if (RES_DEBUG) - printk(BIOS_DEBUG, "%04x: %02x %08x <- & %08x | %08x\n", - i/4, register_values[i],register_values[i+1], register_values[i+2], register_values[i+3]); - switch (register_values[i]) { - case RES_PCI_IO: //PCI - { - pci_devfn_t dev; - u32 where; - u32 reg; - dev = register_values[i+1] & ~0xfff; - where = register_values[i+1] & 0xfff; - reg = pci_read_config32(dev, where); - reg &= register_values[i+2]; - reg |= register_values[i+3]; - pci_write_config32(dev, where, reg); - } - break; - case RES_PORT_IO_8: // io 8 - { - u32 where; - u32 reg; - where = register_values[i+1]; - reg = inb(where); - reg &= register_values[i+2]; - reg |= register_values[i+3]; - outb(reg, where); - } - break; - case RES_PORT_IO_32: //io32 - { - u32 where; - u32 reg; - where = register_values[i+1]; - reg = inl(where); - reg &= register_values[i+2]; - reg |= register_values[i+3]; - outl(reg, where); - } - break; - } - } - - if (RES_DEBUG) - printk(BIOS_DEBUG, "done.\n"); -} diff --git a/src/northbridge/amd/amdfam10/util.c b/src/northbridge/amd/amdfam10/util.c deleted file mode 100644 index ed5556ff70..0000000000 --- a/src/northbridge/amd/amdfam10/util.c +++ /dev/null @@ -1,261 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2008 Vincent Legoll - * Copyright (C) 2008 Ronald G. Minnich - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -/* - * fam10 northbridge utilities (dump routing registers). - * Designed to be called at any time. - * It can be called before RAM is set up by including this file. - * It can be called after RAM is set up by including amdfam10.h and enabling the - * compilation of this file in src/northbridge/amd/amdfam10/Makefile.inc. - */ -#include -#include -#include - -#include "amdfam10.h" - -/* Function 1 */ -/* the DRAM, MMIO,and PCIIO routing are 64-bit registers, hence the ending at - * 0x78, 0xb8, and 0xd8 - */ -#define DRAM_ROUTE_START 0x40 -#define DRAM_ROUTE_END 0x78 -#define MMIO_ROUTE_START 0x80 -#define MMIO_ROUTE_END 0xb8 -#define PCIIO_ROUTE_START 0xc0 -#define PCIIO_ROUTE_END 0xd8 -#define CONF_ROUTE_START 0xe0 -#define CONF_ROUTE_END 0xec - -#define BITS(r, shift, mask) (((r>>shift)&mask)) - -/** - * Return "R" if the register has read-enable bit set. - */ -static const char *re(u32 i) -{ - return ((i & 1) ? "R" : ""); -} - -/** - * Return "W" if the register has write-enable bit set. - */ -static const char *we(u32 i) -{ - return ((i & 1) ? "W" : ""); -} - -/** - * Return a string containing the interleave settings. - */ -static const char *ileave(u32 base) -{ - switch ((base >> 8) & 7) { - case 0: - return "No interleave"; - case 1: - return "2 nodes"; - case 3: - return "4 nodes"; - case 7: - return "8 nodes"; - default: - return "Reserved"; - } -} - -/** - * Return the node number. - * For one case (config registers) these are not the right bit fields. - */ -static int r_node(u32 reg) -{ - return BITS(reg, 0, 0x7); -} - -/** - * Return the link number. - * For one case (config registers) these are not the right bit fields. - */ -static int r_link(u32 reg) -{ - return BITS(reg, 4, 0x3); -} - -/** - * Print the DRAM routing info for one base/limit pair. - * - * Show base, limit, dest node, dest link on that node, read and write - * enable, and interleave information. - * - * @param level Printing level - * @param which Register number - * @param base Base register - * @param lim Limit register - */ -static void showdram(int level, u8 which, u32 base, u32 lim) -{ - printk(level, "DRAM(%02x)%010llx-%010llx, ->(%d), %s, %s, %s, %d\n", - which, (((u64) base & 0xffff0000) << 8), - (((u64) lim & 0xffff0000) << 8) + 0xffffff, - r_node(lim), re(base), we(base), ileave(base), (lim >> 8) & 3); -} - -/** - * Print the config routing info for a config register. - * - * Show base, limit, dest node, dest link on that node, read and write - * enable, and device number compare enable - * - * @param level Printing level - * @param which Register number - * @param reg Config register - */ -static void showconfig(int level, u8 which, u32 reg) -{ - /* Don't use r_node() and r_link() here. */ - printk(level, "Config(%02x)%02x-%02x ->(%d,%d),%s %s (%s numbers)\n", - which, BITS(reg, 16, 0xff), BITS(reg, 24, 0xff), - BITS(reg, 4, 0x7), BITS(reg, 8, 0x3), - re(reg), we(reg), - BITS(reg, 2, 0x1)?"dev":"bus"); -} - -/** - * Print the PCIIO routing info for one base/limit pair. - * - * Show base, limit, dest node, dest link on that node, read and write - * enable, and VGA and ISA Enable. - * - * @param level Printing level - * @param which Register number - * @param base Base register - * @param lim Limit register - */ -static void showpciio(int level, u8 which, u32 base, u32 lim) -{ - printk(level, "PCIIO(%02x)%07x-%07x, ->(%d,%d), %s, %s,VGA %d ISA %d\n", - which, BITS(base, 12, 0x3fff) << 12, - (BITS(lim, 12, 0x3fff) << 12) + 0xfff, r_node(lim), r_link(lim), - re(base), we(base), BITS(base, 4, 0x1), BITS(base, 5, 0x1)); -} - -/** - * Print the MMIO routing info for one base/limit pair. - * - * Show base, limit, dest node, dest link on that node, read and write - * enable, and CPU Disable, Lock, and Non-posted. - * - * @param level Printing level - * @param which Register number - * @param base Base register - * @param lim Limit register - */ -static void showmmio(int level, u8 which, u32 base, u32 lim) -{ - printk(level, "MMIO(%02x)%010llx-%010llx, ->(%d,%d), %s, %s, " - "CPU disable %d, Lock %d, Non posted %d\n", - which, ((u64) BITS(base, 0, 0xffffff00)) << 8, - (((u64) BITS(lim, 0, 0xffffff00)) << 8) + 0xffff, r_node(lim), - r_link(lim), re(base), we(base), BITS(base, 4, 0x1), - BITS(base, 7, 0x1), BITS(lim, 7, 0x1)); -} - -/** - * Show all DRAM routing registers. This function is callable at any time. - * - * @param level The debug level. - * @param dev A 32-bit number in the standard bus/dev/fn format which is used - * raw config space. - */ -static void showalldram(int level, struct device *dev) -{ - u8 reg; - for (reg = DRAM_ROUTE_START; reg <= DRAM_ROUTE_END; reg += 8) { - u32 base = pci_read_config32(dev, reg); - u32 lim = pci_read_config32(dev, reg + 4); - if (base || lim!=(reg-DRAM_ROUTE_START)/8) - showdram(level, reg, base, lim); - } -} - -/** - * Show all MMIO routing registers. This function is callable at any time. - * - * @param level The debug level. - * @param dev A 32-bit number in the standard bus/dev/fn format which is used - * raw config space. - */ -static void showallmmio(int level, struct device *dev) -{ - u8 reg; - for (reg = MMIO_ROUTE_START; reg <= MMIO_ROUTE_END; reg += 8) { - u32 base = pci_read_config32(dev, reg); - u32 lim = pci_read_config32(dev, reg + 4); - if (base || lim) - showmmio(level, reg, base, lim); - } -} - -/** - * Show all PCIIO routing registers. This function is callable at any time. - * - * @param level The debug level. - * @param dev A 32-bit number in the standard bus/dev/fn format which is used - * raw config space. - */ -static void showallpciio(int level, struct device *dev) -{ - u8 reg; - for (reg = PCIIO_ROUTE_START; reg <= PCIIO_ROUTE_END; reg += 8) { - u32 base = pci_read_config32(dev, reg); - u32 lim = pci_read_config32(dev, reg + 4); - if (base || lim) - showpciio(level, reg, base, lim); - } -} - -/** - * Show all config routing registers. This function is callable at any time. - * - * @param level The debug level. - * @param dev A 32-bit number in the standard bus/dev/fn format which is used - * raw config space. - */ -static void showallconfig(int level, struct device *dev) -{ - u8 reg; - for (reg = CONF_ROUTE_START; reg <= CONF_ROUTE_END; reg += 4) { - u32 val = pci_read_config32(dev, reg); - if (val) - showconfig(level, reg, val); - } -} - -/** - * Show all routing registers. This function is callable at any time. - * - * @param level The debug level. - * @param dev A 32-bit number in the standard bus/dev/fn format which is used - * raw config space. - */ -void showallroutes(int level, struct device *dev) -{ - showalldram(level, dev); - showallmmio(level, dev); - showallpciio(level, dev); - showallconfig(level, dev); -} diff --git a/src/northbridge/amd/amdht/AsPsDefs.h b/src/northbridge/amd/amdht/AsPsDefs.h deleted file mode 100644 index 30f4d759b6..0000000000 --- a/src/northbridge/amd/amdht/AsPsDefs.h +++ /dev/null @@ -1,273 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007-2008 Advanced Micro Devices, Inc. - * Copyright (C) 2015 Timothy Pearson , Raptor Engineering - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - - -#ifndef ASPSDEFS_H -#define ASPSDEFS_H - -/* P-state register offset */ -#define PS_REG0 0 /* offset for P0 */ -#define PS_REG1 1 /* offset for P1 */ -#define PS_REG2 2 /* offset for P2 */ -#define PS_REG3 3 /* offset for P3 */ -#define PS_REG4 4 /* offset for P4 */ - -#define PS_IDD_VALUE_SHFT 0 /* IddValue: current value - field offset for msr.hi */ -#define PS_IDD_VALUE_MASK 0xFF /* IddValue: current value - field mask for msr.hi */ -#define PS_PSDIS_MASK 0x7fffffff /* disable P-state register */ -#define PS_EN_MASK 0x80000000 /* P-state register enable mask */ -#define PS_NB_DID_MASK 0x400000 /* P-state Reg[NbDid] Mask */ -#define PS_NB_VID_M_OFF 0x01ffffff /* P-state Reg[NbVid] Mask OFF */ -#define PS_CPU_VID_M_ON 0x0fe00 /* P-state Reg[CpuVid] Mask On */ -#define PS_NB_VID_M_ON 0x0fe000000 /* P-state Reg[NbVid] Mask On */ -#define PS_CPU_VID_SHFT 9 /* P-state bit shift for CpuVid */ -#define PS_NB_VID_SHFT 25 /* P-state bit shift for NbVid */ -#define PS_BOTH_VID_OFF 0x01ff01ff /* Mask NbVid & CpuVid */ -#define PS_CPU_NB_VID_SHFT 16 /* P-state bit shift from CpuVid to NbVid */ -#define PS_DIS 0x7fffffff /* disable P-state reg */ -#define PS_EN 0x80000000 /* enable P-state reg */ -#define PS_CPU_FID_MASK 0x03f /* MSRC001_00[68:64][CpuFid] - Core Frequency Id */ -#define PS_CURDIV_SHFT 8 /* P-state Current Divisor shift position */ -#define PS_CPUDID_SHIFT 6 /* P-state CPU DID shift position */ - -/* for unfused parts */ -#define PS_NB_VID_110V 0x48000000 -#define PS_NB_VID_1175V 0x3c000000 -/* NB VID 1.100V =0x12[PVI]=0x24[SVI] = 0100100b 7-bit code */ - -#define PS_NB_DID0 0 /* NB DID 0 */ -#define PS_NB_DID1 0x400000 /* NB DID 1 */ -#define PS_CPU_VID_110V 0x4800 /* CPU VID 1.100V */ -#define PS_CPU_VID_1175V 0x3c00 /* CPU VID 1.175V */ -#define PS_CPU_DID 0x40 /* CPU DID 1 = divisor of 2 */ -#define PS_CPU_DID0 0 /* CPU DID 0 = divisor of 1 */ -#define PS_CPU_FID_16G 0x00 /* CPU FID of 00 = 1.6GHz */ -#define PS_CPU_FID_16G1 0x10 /* CPU FId of 16 COF = 16+16/2 = 16 */ -#define PS_CPU_FID_18G 20 /* CPU FId of 20 COF = 20+16/2 = 18 */ -#define PS_CPU_FID_19G 22 /* CPU FId of 20 COF = 22+16/2 = 19 */ -#define PS_CPU_FID_20G 24 /* CPU FId of 20 COF = 24+16/2 = 20 */ -#define PS_CPU_FID_22G 28 /* CPU FId of 2C COF = 28+16/2 = 22 */ -#define PS_CPU_FID_30G 44 /* CPU FId of 2C COF = 44+16/2 = 30 */ - - - -#define PCI_DEV_BASE 24 /* System PCI device ID base */ -#define LOCAL_APIC_ID_SHIFT 24 /* Local APIC ID shift bit # */ -#define APIC_CID_SIZE_SHIFT 12 /* ApicCoreIdSize shift bit # */ -#define FN_0 0 /* Function 0 */ -#define FN_1 1 /* Function 1 */ -#define FN_2 2 /* Function 2 */ -#define FN_3 3 /* Function 3 */ -#define FN_4 4 /* Function 4 */ -#define FN_5 5 /* Function 5 */ -#define FN_80000000 0x80000000 /* Function 8000_0000 */ -#define FN_80000001 0x80000001 /* Function 8000_0001 */ -#define FN_80000008 0x80000008 /* Function 8000_0008 */ - -#define LNK_INIT_REG 0x6C /* F0x6C link initialization control register */ -#define WARM_RESET_BIT 0x10 /* bit 4 =1 : warm reset */ - -#define HTC_REG 0x64 /* hardware thermal control reg */ -#define HTC_PS_LMT_MASK 0x8fffffff /* HtcPstateLimit mask off */ -#define PS_LIMIT_POS 28 /* PstateLimit position for HTC & STC */ - -#define STC_REG 0x68 /* software thermal control reg */ -#define STC_PS_LMT_MASK 0x8fffffff /* StcPstateLimit mask off */ - -#define CPTC0 0x0d4 /* Clock Power/Timing Control0 Register*/ -#define CPTC0_MASK 0x000cffff /* Reset mask for this register */ -#define CPTC0_NBFID_MASK 0xffffffe0 /* NbFid mask off for this register */ -#define CPTC0_NBFID_MON 0x1f /* NbFid mask on for this register */ -#define NB_FID_EN 0x20 /* NbFidEn bit ON */ -#define NB_CLKDID_ALL 0x80000000 /* NbClkDidApplyAll bit ON */ -#define NB_CLKDID 0x40000000 /* NbClkDid value set by BIOS */ -#define NB_CLKDID_SHIFT 28 /* NbClkDid bit shift */ -#define PW_STP_UP50 0x08000000 /* PowerStepUp 50nS(1000b) */ -#define PW_STP_DN50 0x00800000 /* PowerStepDown 50nS (1000b)*/ -#define PW_STP_UP100 0x03000000 /* PowerStepUp 100nS(0011b) */ -#define PW_STP_DN100 0x00300000 /* PowerStepDown 100nS (0011b)*/ -#define PW_STP_UP200 0x02000000 /* PowerStepUp 200nS(0010b) */ -#define PW_STP_DN200 0x00200000 /* PowerStepDown 200nS (0010b)*/ -#define PW_STP_UP400 0x00000000 /* PowerStepUp 400nS(0000b) */ -#define PW_STP_DN400 0x00000000 /* PowerStepDown 400nS (0000b)*/ -#define CLK_RAMP_HYST_SEL_VAL 0x00000f00 /* value mask for clock ramp - hysteresis select. BIOS - should program - F3xC4[ClkRampHystSel] to - 1111b */ - - -#define LNK_PLL_LOCK 0x00010000 /* LnkPllLock value set (01b) by BIOS */ - - - -#define PSTATE_CTL 0xC0010070 /* P-state Control Register */ -#define NB_VID_POS 25 /* NbVid bit shift for position */ -#define NB_VID_MASK_OFF 0x01ffffff /* NbVid bits mask off */ -#define NB_VID_MASK_ON 0xfe000000 /* NbVid bits mask on */ -#define CPU_VID_POS 0x9 /* CpuVid bit shift for position */ -#define CPU_VID_MASK_OFF 0xffff01ff /* CpuVid bits mask off */ -#define CPU_VID_MASK_ON 0x0000fe00 /* CpuVid bits mask on */ -#define CPU_FID_DID_M_ON 0x000001ff /* CpuFid & CpuDid mask on */ -#define CPU_FID_DID_M_OFF 0xfffffe00 /* CpuFid & CpuDid mask off */ -#define NB_DID_VID_M_ON 0xfe400000 /* NbDid & NbVid mask on */ -#define NB_DID_M_ON 0x00400000 /* NbDid mask on */ -#define NB_DID_M_OFF 0xffbfffff /* NbDid mask off */ -#define NB_DID_POS 22 /* NbDid bit shift for position */ -#define PS_M_OFF 0xfff8ffff /* Cur Pstate mask off */ -#define PS_1 0x00010000 /* P-state 1 */ -#define PS_2 0x00020000 /* P-state 2 */ -#define PS_CPU_DID_1 0x40 /* Cpu Did 1 */ - -#define NB_VID1_MASK 0x00003f80 /* F3x1F4[NbVid1]*/ -#define NB_VID1_SHIFT 7 /* F3x1F4[NbVid1] */ - - - -#define PSTATE_STS 0xC0010071 /* P-state Status Register */ -#define STARTUP_PS_MASK 0x7 /* StartupPstate Mask */ - -/* define for NB VID & CPU VID transition functions */ -#define IS_NB 1 -#define IS_CPU 0 - -/* F3xD8 Clock Power/Timing Control 1 Register */ -#define CPTC1 0xd8 /* Clock Power/Timing Control1 Register*/ -#define VSRAMP_SLAM_MASK 0xffffff88 /* MaskOff [VSRampTime]&[VSSlamTime] */ -#define VSRAMP_SLAM_VALUE 0x16 /* [VSRampTime]=001b&[VSSlamTime]=110b */ -#define VSRAMP_MASK 0xffffff8f /* MaskOff [VSRampTime] */ -#define VSRAMP_VALUE 0x10 /* [VSRampTime]=001b */ -#define VS_RAMP_T 4 /* VSRampTime bit position */ -#define VSSLAM_MASK 0xfffffff8 /* MaskOff [VSSlamTime] */ -#define PWR_PLN_SHIFT 28 /* PwrPlanes bit shift */ -#define PWR_PLN_ON 0x10000000 /* PwrPlanes bit ON */ -#define PWR_PLN_OFF 0x0efffffff /* PwrPlanes bit OFF */ - - - -/* Northbridge Capability Register */ -#define NB_CAP 0xe8 /* Northbridge Cap Reg */ -#define CMP_CAP_SHFT 12 /* CMP CAP - number of enabled cores */ - -/* F3xDC Clock Power/Timing Control 2 Register */ -#define CPTC2 0xdc /* Clock Power/Timing Control2 Register*/ -#define PS_MAX_VAL_POS 8 /* PstateMaxValue bit shift */ -#define PS_MAX_VAL_MASK 0xfffff8ff /* PstateMaxValue Mask off */ -#define NB_SYN_PTR_ADJ_POS 12 /* NbsynPtrAdj bit shift */ -#define NB_SYN_PTR_ADJ_MASK (0x7 << NB_SYN_PTR_ADJ_POS) /* NbsynPtrAdj bit mask */ - -#define PRCT_INFO 0x1fc /* Product Info Register */ -#define DUAL_PLANE_ONLY_MASK 0x80000000 /* F3x1FC[DualPlaneOnly] */ -#define UNI_NB_FID_BIT 2 /* UniNbFid bit position */ -#define UNI_NB_VID_BIT 7 /* UniNbVid bit position */ -#define SPLT_NB_FID_OFFSET 14 /* SpltNbFidOffset value bit position */ -#define SPLT_NB_VID_OFFSET 17 /* SpltNbVidOffset value bit position */ -#define NB_CV_UPDATE 0x01 /* F3x1FC[NbCofVidUpdated] bit mask */ -#define NB_VID_UPDATE_ALL 0x02 /* F3x1FC[NbVidUpdatedAll] bit mask */ -#define C_FID_DID_M_OFF 0xfffffe00 /* mask off Core FID & DID */ - -#define CPB_MASK 0x00000020 /* core performance - boost. CPUID Fn8000 0007 edx */ -#define NC_MASK 0x000000FF /* number of cores - 1. CPUID - Fn8000 0008 ecx */ -#define PW_CTL_MISC 0x0a0 /* Power Control Miscellaneous Register */ -#define COF_VID_PROG_BIT 0x80000000 /* CofVidProg bit. 0= unfused part */ -#define DUAL_VDD_BIT 0x40000000 /* DualVdd bit. */ -#define NB_COFVID_UPDATE_BIT 0x01 /* NbCOFVIDUpdated bit */ -#define PVI_MODE 0x100 /* PviMode bit mask */ -#define VID_SLAM_OFF 0x0dfffffff /* set VidSlamMode OFF */ -#define VID_SLAM_ON 0x020000000 /* set VidSlamMode ON */ -#define NB_PSTATE_FORCE_ON 0x010000000 /* set Northbridge P-state - force on next LDTSTOP - assertion on, in F3xA0 */ -#define BP_INS_TRI_EN_ON 0x00004000 /* breakpoint pins tristate - enable in F3xA0 */ -#define PLLLOCK_OFF 0x0ffffc7ff /* PllLockTime Mask OFF */ -#define PLLLOCK_DFT 0x00001800 /* PllLockTime default value = 011b */ -#define PLLLOCK_DFT_L 0x00002800 /* PllLockTime long value = 101b */ - -#define SVI_HIGH_FREQ_ON 0x00000200 /* F3xA0[SviHighFreqSel] for - 3.4 MHz SVI in rev. C3 */ - -/* P-state Specification register base in PCI space */ -#define PS_SPEC_REG 0x1e0 /* PS Spec register base address */ -#define PCI_REG_LEN 4 /* PCI register length */ -#define NB_DID_MASK 0x10000 /* NbDid bit mask */ -#define NB_DID_2 2 /* NbDid = 2 */ -#define NB_DID_1 1 /* NbDid = 1 */ -#define SPEC_PWRDIV_M_ON 0x06000000 /* PwrDiv mask on */ -#define SPEC_PWRVAL_M_ON 0x01e00000 /* PwrValue mask on */ -#define SPEC_PWRDIV_SHFT 25 /* PwrDiv shift */ -#define SPEC_PWRVAL_SHFT 17 /* PwrValue shift */ - -/* F4x1F4 Northbridge P-state spec register */ -#define NB_PS_SPEC_REG 0x1f4 /* Nb PS spec reg */ - -/* F3x1F0 Product Information Register */ -#define NB_PSTATE_MASK 0x00070000 /* NbPstate for CPU rev C3 */ - -/* F3x1FC Product Information Register */ -#define NB_COF_VID_UPDATE_MASK 1 /* for CPU rev <= C */ -#define SINGLE_PLANE_NB_FID_MASK 0x007c/* for CPU rev <= C */ -#define SINGLE_PLANE_NB_FID_SHIFT 2/* for CPU rev <= C */ -#define SINGLE_PLANE_NB_VID_MASK 0x3f80/* for CPU rev <= C */ -#define SINGLE_PLANE_NB_VID_SHIFT 7/* for CPU rev <= C */ - -#define DUAL_PLANE_NB_FID_OFF_MASK 0x001c000/* for CPU rev <= C */ -#define DUAL_PLANE_NB_FID_SHIFT 14/* for CPU rev <= C */ -#define DUAL_PLANE_NB_VID_OFF_MASK 0x3e0000/* for CPU rev <= C */ -#define DUAL_PLANE_NB_VID_SHIFT 17/* for CPU rev <= C */ - -#define NM_PS_REG (is_fam15h()?8:5) /* number of P-state MSR registers */ - -/* sFidVidInit.outFlags defines */ -#define PWR_CK_OK 0 /* System board check OK */ -#define PWR_CK_NO_PS 1 /* All P-state registers are over - the limit */ - -/* bit mask */ -#define BIT_MASK_1 0x1 -#define BIT_MASK_2 0x3 -#define BIT_MASK_3 0x7 -#define BIT_MASK_4 0x0f -#define BIT_MASK_5 0x1f -#define BIT_MASK_6 0x3f -#define BIT_MASK_7 0x7f -#define BIT_MASK_8 0x0ff - -/* VID Code */ -#define VID_1_100V 0x12 /* 1.100V */ -#define VID_1_175V 0x1E /* 1.175V */ - -/* Nb Fid Code */ -#define NB_FID_800M 0x00 /* 800MHz */ - -/* Nb DID Code */ -#define NB_DID_0 0 -#define NB_DID_1 1 - -/* GH Logical ID */ -#define GH_REV_A2 0x4 /* GH Rev A2 logical ID, Upper half */ - -#define TSC_FREQ_SEL_SHIFT 24 -#define TSC_FREQ_SEL_MASK (1 << TSC_FREQ_SEL_SHIFT) - -#define WAIT_PSTATE_TIMEOUT 80000000 /* 0.1 s , unit : 1.25 ns */ - -#endif diff --git a/src/northbridge/amd/amdht/AsPsNb.c b/src/northbridge/amd/amdht/AsPsNb.c deleted file mode 100644 index 70dbacfbab..0000000000 --- a/src/northbridge/amd/amdht/AsPsNb.c +++ /dev/null @@ -1,121 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include "comlib.h" -#include "AsPsDefs.h" -#include "AsPsNb.h" - -u8 getNumOfNodeNb(void); -u8 translateNodeIdToDeviceIdNb(u8 nodeId); - -/** - * Return the minimum possible NbCOF (in 100MHz) for the system. - * - * This function can be run on any core and is used by the HT & Memory init - * code in Phase 1. - * - * @return minNbCOF (in multiple of half of CLKIN, 100MHz). - */ -u8 getMinNbCOF(void) -{ - u8 numOfNode, i, j, deviceId, nbDid, nbFid, nextNbFid; - u32 dtemp; - - nbDid = 0; - nbFid = 0; - - /* get number of node in the system */ - numOfNode = getNumOfNodeNb(); - - /* go through each node for the minimum NbCOF (in multiple of CLKIN/2) */ - for (i = 0; i < numOfNode; i++) - { - /* stub function for APIC ID virtualization for large MP system later */ - deviceId = translateNodeIdToDeviceIdNb(i); - - /* read all P-state spec registers for NbDid = 1 */ - for (j = 0; j < 5; j++) - { - AmdPCIRead(MAKE_SBDFO(0,0,deviceId,FN_4,PS_SPEC_REG+(j*PCI_REG_LEN)), &dtemp); /*F4x1E0 + j*4 */ - /* get NbDid */ - if (dtemp & NB_DID_MASK) - nbDid = 1; - } - /* if F3x1FC[NbCofVidUpdate]=0, NbFid = default value */ - AmdPCIRead(MAKE_SBDFO(0,0,deviceId,FN_3,PRCT_INFO), &dtemp); /*F3x1FC*/ - if (!(dtemp & NB_CV_UPDATE)) /* F3x1FC[NbCofVidUpdated]=0, use default VID */ - { - AmdPCIRead(MAKE_SBDFO(0,0,deviceId,FN_3,CPTC0), &dtemp); /*F3xD4*/ - nextNbFid = (u8) (dtemp & BIT_MASK_5); - if (nbDid) - nextNbFid = (u8) (nextNbFid >> 1); - } - else - { - /* check PVI/SPI */ - AmdPCIRead(MAKE_SBDFO(0,0,deviceId,FN_3,PW_CTL_MISC), &dtemp); /*F3xA0*/ - if (dtemp & PVI_MODE) /* PVI */ - { - AmdPCIRead(MAKE_SBDFO(0,0,deviceId,FN_3,PRCT_INFO), &dtemp); /*F3x1FC*/ - nextNbFid = (u8) (dtemp >> UNI_NB_FID_BIT); - nextNbFid &= BIT_MASK_5; - /* if (nbDid) - nextNbFid = nextNbFid >> 1; */ - } - else /* SVI */ - { - AmdPCIRead(MAKE_SBDFO(0,0,deviceId,FN_3,PRCT_INFO), &dtemp); /*F3x1FC*/ - nextNbFid = (u8) ((dtemp >> UNI_NB_FID_BIT) & BIT_MASK_5); - nextNbFid = (u8) (nextNbFid + ((dtemp >> SPLT_NB_FID_OFFSET) & BIT_MASK_3)); - /* if (nbDid) - nextNbFid = nextNbFid >> 1; */ - } - } - if (i == 0) - nbFid = nextNbFid; - else if (nbFid > nextNbFid) - nbFid = nextNbFid; - } - - /* add the base and convert to 100MHz divide by 2 if DID = 1 */ - if (nbDid) - nbFid = (u8) (nbFid + 4); - else - nbFid = (u8) ((nbFid + 4) << 1); - return nbFid; -} - -u8 getNumOfNodeNb(void) -{ - u32 dtemp; - - AmdPCIRead(MAKE_SBDFO(0,0,24,0,0x60), &dtemp); - dtemp = (dtemp >> 4) & BIT_MASK_3; - dtemp++; - return (u8)dtemp; -} - -/** - * Return the PCI device ID for PCI access using node ID. - * - * This function may need to change node ID to device ID in big MP systems. - * - * @param nodeId Node ID of the node. - * @return PCI device ID of the node. - */ -u8 translateNodeIdToDeviceIdNb(u8 nodeId) -{ - return (u8) (nodeId+PCI_DEV_BASE); -} diff --git a/src/northbridge/amd/amdht/AsPsNb.h b/src/northbridge/amd/amdht/AsPsNb.h deleted file mode 100644 index 35008920fe..0000000000 --- a/src/northbridge/amd/amdht/AsPsNb.h +++ /dev/null @@ -1,22 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - - -#ifndef ASPSNB_H -#define ASPSNB_H - -u8 getMinNbCOF(void); - -#endif diff --git a/src/northbridge/amd/amdht/Makefile.inc b/src/northbridge/amd/amdht/Makefile.inc deleted file mode 100644 index 0b33352e7c..0000000000 --- a/src/northbridge/amd/amdht/Makefile.inc +++ /dev/null @@ -1,5 +0,0 @@ -ifeq ($(CONFIG_NORTHBRIDGE_AMD_AMDFAM10),y) - -romstage-y += h3finit.c ht_wrapper.c comlib.c AsPsNb.c h3ncmn.c - -endif diff --git a/src/northbridge/amd/amdht/comlib.c b/src/northbridge/amd/amdht/comlib.c deleted file mode 100644 index 883f634c74..0000000000 --- a/src/northbridge/amd/amdht/comlib.c +++ /dev/null @@ -1,238 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include "comlib.h" - -#include -#include -#include -#include - - -/* - *--------------------------------------------------------------------------- - * EXPORTED FUNCTIONS - * - *--------------------------------------------------------------------------- - */ - -void CALLCONV AmdPCIReadBits(SBDFO loc, u8 highbit, u8 lowbit, u32 *pValue) -{ - ASSERT(highbit < 32 && lowbit < 32 && highbit >= lowbit && (loc & 3) == 0); - - AmdPCIRead(loc, pValue); - *pValue = *pValue >> lowbit; /* Shift */ - - /* A 1<<32 == 1<<0 due to x86 SHL instruction, so skip if that is the case */ - if ((highbit-lowbit) != 31) - *pValue &= (((u32)1 << (highbit-lowbit+1))-1); -} - - -void CALLCONV AmdPCIWriteBits(SBDFO loc, u8 highbit, u8 lowbit, u32 *pValue) -{ - u32 temp, mask; - - ASSERT(highbit < 32 && lowbit < 32 && highbit >= lowbit && (loc & 3) == 0); - - /* A 1<<32 == 1<<0 due to x86 SHL instruction, so skip if that is the case */ - if ((highbit-lowbit) != 31) - mask = (((u32)1 << (highbit-lowbit+1))-1); - else - mask = (u32)0xFFFFFFFF; - - AmdPCIRead(loc, &temp); - temp &= ~(mask << lowbit); - temp |= (*pValue & mask) << lowbit; - AmdPCIWrite(loc, &temp); -} - - -/* - * Given a SBDFO this routine will find the next PCI capabilities list entry. - * If the end of the list of reached, or if a problem is detected, then - * ILLEGAL_SBDFO is returned. - * - * To start a new search from the beginning of head of the list, specify a - * SBDFO with a offset of zero. - */ -void CALLCONV AmdPCIFindNextCap(SBDFO *pCurrent) -{ - SBDFO base; - u32 offset; - u32 temp; - - if (*pCurrent == ILLEGAL_SBDFO) - return; - - offset = SBDFO_OFF(*pCurrent); - base = *pCurrent - offset; - *pCurrent = ILLEGAL_SBDFO; - - /* Verify that the SBDFO points to a valid PCI device SANITY CHECK */ - AmdPCIRead(base, &temp); - if (temp == 0xFFFFFFFF) - return; /* There is no device at this address */ - - /* Verify that the device supports a capability list */ - AmdPCIReadBits(base + 0x04, 20, 20, &temp); - if (temp == 0) - return; /* This PCI device does not support capability lists */ - - if (offset != 0) - { - /* If we are continuing on an existing list */ - AmdPCIReadBits(base + offset, 15, 8, &temp); - } - else - { - /* We are starting on a new list */ - AmdPCIReadBits(base + 0x34, 7, 0, &temp); - } - - if (temp == 0) - return; /* We have reached the end of the capabilties list */ - - /* Error detection and recovery- The statement below protects against - PCI devices with broken PCI capabilities lists. Detect a pointer - that is not u32 aligned, points into the first 64 reserved DWORDs - or points back to itself. - */ - if (((temp & 3) != 0) || (temp == offset) || (temp < 0x40)) - return; - - *pCurrent = base + temp; - return; -} - - -void CALLCONV Amdmemcpy(void *pDst, const void *pSrc, u32 length) -{ - ASSERT(length <= 32768); - ASSERT(pDst != NULL); - ASSERT(pSrc != NULL); - - while (length--) { - // *(((u8*)pDst)++) = *(((u8*)pSrc)++); - *((u8*)pDst) = *((u8*)pSrc); - pDst++; - pSrc++; - } -} - - -void CALLCONV Amdmemset(void *pBuf, u8 val, u32 length) -{ - ASSERT(length <= 32768); - ASSERT(pBuf != NULL); - - while (length--) { - //*(((u8*)pBuf)++) = val; - *(((u8*)pBuf)) = val; - pBuf++; - } -} - - -u8 CALLCONV AmdBitScanReverse(u32 value) -{ - u8 i; - - for (i = 31; i != 0xFF; i--) - { - if (value & ((u32)1 << i)) - break; - } - - return i; -} - - -u32 CALLCONV AmdRotateRight(u32 value, u8 size, u32 count) -{ - u32 msb, mask; - ASSERT(size > 0 && size <= 32); - - msb = (u32)1 << (size-1); - mask = ((msb-1) << 1) + 1; - - value = value & mask; - - while (count--) - { - if (value & 1) - value = (value >> 1) | msb; - else - value = value >> 1; - } - - return value; -} - - -u32 CALLCONV AmdRotateLeft(u32 value, u8 size, u32 count) -{ - u32 msb, mask; - ASSERT(size > 0 && size <= 32); - - msb = (u32)1 << (size-1); - mask = ((msb-1) << 1) + 1; - - value = value & mask; - - while (count--) - { - if (value & msb) - value = ((value << 1) & mask) | (u32)1; - else - value = ((value << 1) & mask); - } - - return value; -} - - -void CALLCONV AmdPCIRead(SBDFO loc, u32 *Value) -{ - /* Use coreboot PCI functions */ - *Value = pci_read_config32((loc & 0xFFFFF000), SBDFO_OFF(loc)); -} - - -void CALLCONV AmdPCIWrite(SBDFO loc, u32 *Value) -{ - /* Use coreboot PCI functions */ - pci_write_config32((loc & 0xFFFFF000), SBDFO_OFF(loc), *Value); -} - - -void CALLCONV AmdMSRRead(uint32 Address, uint64 *Value) -{ - msr_t msr; - - msr = rdmsr(Address); - Value->lo = msr.lo; - Value->hi = msr.hi; -} - - -void CALLCONV AmdMSRWrite(uint32 Address, uint64 *Value) -{ - msr_t msr; - - msr.lo = Value->lo; - msr.hi = Value->hi; - wrmsr(Address, msr); -} diff --git a/src/northbridge/amd/amdht/comlib.h b/src/northbridge/amd/amdht/comlib.h deleted file mode 100644 index 98326b280f..0000000000 --- a/src/northbridge/amd/amdht/comlib.h +++ /dev/null @@ -1,42 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef COMLIB_H -#define COMLIB_H - -#include -#include -#include -#include "porting.h" - -#ifdef AMD_DEBUG_ERROR_STOP - /* Macro to aid debugging, causes program to halt and display the line number of the halt */ - #define STOP_HERE ASSERT(0) -#else - #define STOP_HERE -#endif - -void CALLCONV AmdPCIReadBits(SBDFO loc, uint8 highbit, uint8 lowbit, uint32 *value); -void CALLCONV AmdPCIWriteBits(SBDFO loc, uint8 highbit, uint8 lowbit, uint32 *value); -void CALLCONV AmdPCIFindNextCap(SBDFO *current); - -void CALLCONV Amdmemcpy(void *dst, const void *src, uint32 length); -void CALLCONV Amdmemset(void *buf, uint8 val, uint32 length); - -uint8 CALLCONV AmdBitScanReverse(uint32 value); -uint32 CALLCONV AmdRotateRight(uint32 value, uint8 size, uint32 count); -uint32 CALLCONV AmdRotateLeft(uint32 value, uint8 size, uint32 count); - -#endif diff --git a/src/northbridge/amd/amdht/h3ffeat.h b/src/northbridge/amd/amdht/h3ffeat.h deleted file mode 100644 index 2cf4bd1a1c..0000000000 --- a/src/northbridge/amd/amdht/h3ffeat.h +++ /dev/null @@ -1,180 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007-2008 Advanced Micro Devices, Inc. - * Copyright (C) 2015 Timothy Pearson , Raptor Engineering - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - - -#ifndef H3FFEAT_H -#define H3FFEAT_H - -#include "h3finit.h" - -/*---------------------------------------------------------------------------- - * Mixed (DEFINITIONS AND MACROS / TYPEDEFS, STRUCTURES, ENUMS) - * - *---------------------------------------------------------------------------- - */ - -/*----------------------------------------------------------------------------- - * DEFINITIONS AND MACROS - * - *----------------------------------------------------------------------------- - */ - -#define MAX_NODES 8 -#define MAX_LINKS 8 -#define MAX_PLATFORM_LINKS 64 /* 8x8 fully connected (28) + 4 chains with two HT devices */ - -/* These following are internal definitions */ -#define ROUTETOSELF 0x0F -#define INVALID_LINK 0xCC /* Used in port list data structure to mark unused data entries. - Can also be used for no link found in a port list search */ - -/* definitions for working with the port list structure */ -#define PORTLIST_TYPE_CPU 0 -#define PORTLIST_TYPE_IO 1 - -/* - * Hypertransport Capability definitions and macros - * - */ - -/* HT Host Capability */ -/* bool isHTHostCapability(u32 reg) */ -#define IS_HT_HOST_CAPABILITY(reg) \ - ((reg & (u32)0xE00000FF) == (u32)0x20000008) - -#define HT_HOST_CAP_SIZE 0x20 - -/* Host CapabilityRegisters */ -#define HTHOST_LINK_CAPABILITY_REG 0x00 -#define HTHOST_LINK_CONTROL_REG 0x04 -#define HTHOST_FREQ_REV_REG 0x08 -#define HTHOST_FREQ_REV_REG_2 0x1c - #define HT_HOST_REV_REV3 0x60 -#define HTHOST_FEATURE_CAP_REG 0x0C -#define HTHOST_BUFFER_COUNT_REG 0x10 -#define HTHOST_ISOC_REG 0x14 -#define HTHOST_LINK_TYPE_REG 0x18 - #define HTHOST_TYPE_COHERENT 3 - #define HTHOST_TYPE_NONCOHERENT 7 - #define HTHOST_TYPE_MASK 0x1F - -/* HT Slave Capability (HT1 compat) */ -#define IS_HT_SLAVE_CAPABILITY(reg) \ - ((reg & (u32)0xE00000FF) == (u32)0x00000008) -#define HTSLAVE_LINK01_OFFSET 4 -#define HTSLAVE_LINK_CONTROL_0_REG 4 -#define HTSLAVE_FREQ_REV_0_REG 0xC -#define HTSLAVE_FEATURE_CAP_REG 0x10 - -/* HT3 gen Capability */ -#define IS_HT_GEN3_CAPABILITY(reg) \ - ((reg & (u32)0xF80000FF) == (u32)0xD0000008) -#define HTGEN3_LINK01_OFFSET 0x10 -#define HTGEN3_LINK_TRAINING_0_REG 0x10 - -/* HT3 Retry Capability */ -#define IS_HT_RETRY_CAPABILITY(reg) \ - ((reg & (u32)0xF80000FF) == (u32)0xC0000008) - -#define HTRETRY_CONTROL_REG 4 - -/* Unit ID Clumping Capability */ -#define IS_HT_UNITID_CAPABILITY(reg) \ - ((reg & (u32)0xF80000FF) == (u32)0x90000008) - -#define HTUNIT_SUPPORT_REG 4 -#define HTUNIT_ENABLE_REG 8 - -/*---------------------------------------------------------------------------- - * TYPEDEFS, STRUCTURES, ENUMS - * - *---------------------------------------------------------------------------- - */ - -typedef struct cNorthBridge cNorthBridge; - -/* A pair consists of a source node, a link to the destination node, the - * destination node, and its link back to source node. The even indices are - * the source nodes and links, and the odd indices are for the destination - * nodes and links. - */ -typedef struct -{ - /* This section is where the link is in the system and how to find it */ - u8 Type; /* 0 = CPU, 1 = Device, all others reserved */ - u8 Link; /* 0-1 for devices, 0-7 for CPUs */ - u8 NodeID; /* The node, or a pointer to the devices parent node */ - u8 HostLink, HostDepth; /* Link of parent node + depth in chain. Only used by devices */ - SBDFO Pointer; /* A pointer to the device's slave HT capability, so we don't have to keep searching */ - - /* This section is for the final settings, which are written to hardware */ - BOOL SelRegang; /* Only used for CPU->CPU links */ - u8 SelWidthIn; - u8 SelWidthOut; - u8 SelFrequency; - uint8_t enable_isochronous_mode; - - /* This section is for keeping track of capabilities and possible configurations */ - BOOL RegangCap; - uint32_t PrvFrequencyCap; - uint32_t PrvFeatureCap; - u8 PrvWidthInCap; - u8 PrvWidthOutCap; - uint32_t CompositeFrequencyCap; - -} sPortDescriptor; - - -/* - * Our global state data structure - */ -typedef struct { - AMD_HTBLOCK *HtBlock; - - u8 NodesDiscovered; /* One less than the number of nodes found in the system */ - u8 TotalLinks; - u8 sysMpCap; /* The maximum number of nodes that all processors are capable of */ - - /* Two ports for each link - * Note: The Port pair 2*N and 2*N+1 are connected together to form a link - * (e.g. 0,1 and 8,9 are ports on either end of an HT link) The lower number - * port (2*N) is the source port. The device that owns the source port is - * always the device closer to the BSP. (i.e. nearer the CPU in a - * non-coherent chain, or the CPU with the lower NodeID). - */ - sPortDescriptor PortList[MAX_PLATFORM_LINKS*2]; - - /* The number of coherent links coming off of each node (i.e. the 'Degree' of the node) */ - u8 sysDegree[MAX_NODES]; - /* The systems adjency (sysMatrix[i][j] is true if Node_i has a link to Node_j) */ - BOOL sysMatrix[MAX_NODES][MAX_NODES]; - - /* Same as above, but for the currently selected database entry */ - u8 dbDegree[MAX_NODES]; - BOOL dbMatrix[MAX_NODES][MAX_NODES]; - - u8 Perm[MAX_NODES]; /* The node mapping from the database to the system */ - u8 ReversePerm[MAX_NODES]; /* The node mapping from the system to the database */ - - /* Data for non-coherent initialization */ - u8 AutoBusCurrent; - u8 UsedCfgMapEntires; - - /* 'This' pointer for northbridge */ - cNorthBridge *nb; -} sMainData; - -#endif /* H3FFEAT_H */ diff --git a/src/northbridge/amd/amdht/h3finit.c b/src/northbridge/amd/amdht/h3finit.c deleted file mode 100644 index cda0a28cef..0000000000 --- a/src/northbridge/amd/amdht/h3finit.c +++ /dev/null @@ -1,1879 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2015 Timothy Pearson , Raptor Engineering - * Copyright (C) 2007 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -/* - *---------------------------------------------------------------------------- - * MODULES USED - * - *---------------------------------------------------------------------------- - */ - -#include "h3finit.h" -#include "h3ffeat.h" -#include "h3ncmn.h" -#include "h3gtopo.h" -#include "AsPsNb.h" - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -/*---------------------------------------------------------------------------- - * DEFINITIONS AND MACROS - * - *---------------------------------------------------------------------------- - */ - -#define NVRAM_LIMIT_HT_SPEED_200 0x12 -#define NVRAM_LIMIT_HT_SPEED_300 0x11 -#define NVRAM_LIMIT_HT_SPEED_400 0x10 -#define NVRAM_LIMIT_HT_SPEED_500 0xf -#define NVRAM_LIMIT_HT_SPEED_600 0xe -#define NVRAM_LIMIT_HT_SPEED_800 0xd -#define NVRAM_LIMIT_HT_SPEED_1000 0xc -#define NVRAM_LIMIT_HT_SPEED_1200 0xb -#define NVRAM_LIMIT_HT_SPEED_1400 0xa -#define NVRAM_LIMIT_HT_SPEED_1600 0x9 -#define NVRAM_LIMIT_HT_SPEED_1800 0x8 -#define NVRAM_LIMIT_HT_SPEED_2000 0x7 -#define NVRAM_LIMIT_HT_SPEED_2200 0x6 -#define NVRAM_LIMIT_HT_SPEED_2400 0x5 -#define NVRAM_LIMIT_HT_SPEED_2600 0x4 -#define NVRAM_LIMIT_HT_SPEED_2800 0x3 -#define NVRAM_LIMIT_HT_SPEED_3000 0x2 -#define NVRAM_LIMIT_HT_SPEED_3200 0x1 -#define NVRAM_LIMIT_HT_SPEED_AUTO 0x0 - -static const uint32_t ht_speed_limit[20] = - {0xFFFFF, 0xFFFFF, 0x7FFFF, 0x3FFFF, - 0x0FFFF, 0x07FFF, 0x03FFF, 0x01FFF, - 0x00FFF, 0x007FF, 0x003FF, 0x001FF, - 0x000FF, 0x0007F, 0x0003F, 0x0001F, - 0x0000F, 0x00007, 0x00003, 0x00001}; - -static const struct ht_speed_limit_map_t { - uint16_t mhz; - uint8_t nvram; -} ht_speed_limit_map[] = { - {0, NVRAM_LIMIT_HT_SPEED_AUTO}, - {200, NVRAM_LIMIT_HT_SPEED_200}, - {300, NVRAM_LIMIT_HT_SPEED_300}, - {400, NVRAM_LIMIT_HT_SPEED_400}, - {500, NVRAM_LIMIT_HT_SPEED_500}, - {600, NVRAM_LIMIT_HT_SPEED_600}, - {800, NVRAM_LIMIT_HT_SPEED_800}, - {1000, NVRAM_LIMIT_HT_SPEED_1000}, - {1200, NVRAM_LIMIT_HT_SPEED_1200}, - {1400, NVRAM_LIMIT_HT_SPEED_1400}, - {1600, NVRAM_LIMIT_HT_SPEED_1600}, - {1800, NVRAM_LIMIT_HT_SPEED_1800}, - {2000, NVRAM_LIMIT_HT_SPEED_2000}, - {2200, NVRAM_LIMIT_HT_SPEED_2200}, - {2400, NVRAM_LIMIT_HT_SPEED_2400}, - {2600, NVRAM_LIMIT_HT_SPEED_2600}, - {2800, NVRAM_LIMIT_HT_SPEED_2800}, - {3000, NVRAM_LIMIT_HT_SPEED_3000}, - {3200, NVRAM_LIMIT_HT_SPEED_3200}, -}; - -static const uint32_t ht_speed_mhz_to_hw(uint16_t mhz) -{ - size_t i; - for (i = 0; i < ARRAY_SIZE(ht_speed_limit_map); i++) - if (ht_speed_limit_map[i].mhz == mhz) - return ht_speed_limit[ht_speed_limit_map[i].nvram]; - - printk(BIOS_WARNING, - "WARNING: Invalid HT link limit frequency %d specified, ignoring...\n", - mhz); - return ht_speed_limit[NVRAM_LIMIT_HT_SPEED_AUTO]; -} - -/*---------------------------------------------------------------------------- - * TYPEDEFS AND STRUCTURES - * - *---------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------- - * PROTOTYPES OF LOCAL FUNCTIONS - * - *---------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------- - * EXPORTED FUNCTIONS - * - *---------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------- - * LOCAL FUNCTIONS - * - *---------------------------------------------------------------------------- - */ -#ifndef HT_BUILD_NC_ONLY -/* - ************************************************************************** - * Routing table decompressor - ************************************************************************** - */ - -/* - ************************************************************************** - * Graph Support routines - * These routines provide support for dealing with the graph representation - * of the topologies, along with the routing table information for that topology. - * The routing information is compressed and these routines currently decompress - * 'on the fly'. A graph is represented as a set of routes. All the edges in the - * graph are routes; a direct route from node i to node j exists in the graph IFF - * there is an edge directly connecting node i to node j. All other routes designate - * the edge which the route to that node initially takes, by designating a node - * to which a direct connection exists. That is, the route to non-adjacent node j - * from node i specifies node k where node i directly connects to node k. - * - * - * pseudo definition of compressed graph: - * typedef struct - * { - * BIT broadcast[8]; - * uint4 responseRoute; - * uint4 requestRoute; - * } sRoute; - * typedef struct - * { - * u8 size; - * sRoute graph[size][size]; - * } sGraph; - * - ************************************************************************** - */ - -/*---------------------------------------------------------------------------------------- - * u8 - * graphHowManyNodes(u8 *graph) - * - * Description: - * Returns the number of nodes in the compressed graph - * - * Parameters: - * @param[in] graph = a compressed graph - * @param[out] results = the number of nodes in the graph - * --------------------------------------------------------------------------------------- - */ -static u8 graphHowManyNodes(u8 *graph) -{ - return graph[0]; -} - -/*---------------------------------------------------------------------------------------- - * BOOL - * graphIsAdjacent(u8 *graph, u8 nodeA, u8 nodeB) - * - * Description: - * Returns true if NodeA is directly connected to NodeB, false otherwise - * (if NodeA == NodeB also returns false) - * Relies on rule that directly connected nodes always route requests directly. - * - * Parameters: - * @param[in] graph = the graph to examine - * @param[in] nodeA = the node number of the first node - * @param[in] nodeB = the node number of the second node - * @param[out] results = true if nodeA connects to nodeB false if not - * --------------------------------------------------------------------------------------- - */ -static BOOL graphIsAdjacent(u8 *graph, u8 nodeA, u8 nodeB) -{ - u8 size = graph[0]; - ASSERT(size <= MAX_NODES); - ASSERT((nodeA < size) && (nodeB < size)); - return (graph[1+(nodeA*size+nodeB)*2+1] & 0x0F) == nodeB; -} - -/*---------------------------------------------------------------------------------------- - * u8 - * graphGetRsp(u8 *graph, u8 nodeA, u8 nodeB) - * - * Description: - * Returns the graph node used by nodeA to route responses targeted at nodeB. - * This will be a node directly connected to nodeA (possibly nodeB itself), - * or "Route to Self" if nodeA and nodeB are the same node. - * Note that all node numbers are abstract node numbers of the topology graph, - * it is the responsibility of the caller to apply any permutation needed. - * - * Parameters: - * @param[in] u8 graph = the graph to examine - * @param[in] u8 nodeA = the node number of the first node - * @param[in] u8 nodeB = the node number of the second node - * @param[out] u8 results = The response route node - * --------------------------------------------------------------------------------------- - */ -static u8 graphGetRsp(u8 *graph, u8 nodeA, u8 nodeB) -{ - u8 size = graph[0]; - ASSERT(size <= MAX_NODES); - ASSERT((nodeA < size) && (nodeB < size)); - return (graph[1+(nodeA*size+nodeB)*2+1] & 0xF0)>>4; -} - -/*---------------------------------------------------------------------------------------- - * u8 - * graphGetReq(u8 *graph, u8 nodeA, u8 nodeB) - * - * Description: - * Returns the graph node used by nodeA to route requests targeted at nodeB. - * This will be a node directly connected to nodeA (possibly nodeB itself), - * or "Route to Self" if nodeA and nodeB are the same node. - * Note that all node numbers are abstract node numbers of the topology graph, - * it is the responsibility of the caller to apply any permutation needed. - * - * Parameters: - * @param[in] graph = the graph to examine - * @param[in] nodeA = the node number of the first node - * @param[in] nodeB = the node number of the second node - * @param[out] results = The request route node - * --------------------------------------------------------------------------------------- - */ -static u8 graphGetReq(u8 *graph, u8 nodeA, u8 nodeB) -{ - u8 size = graph[0]; - ASSERT(size <= MAX_NODES); - ASSERT((nodeA < size) && (nodeB < size)); - return (graph[1+(nodeA*size+nodeB)*2+1] & 0x0F); -} - -/*---------------------------------------------------------------------------------------- - * u8 - * graphGetBc(u8 *graph, u8 nodeA, u8 nodeB) - * - * Description: - * Returns a bit vector of nodes that nodeA should forward a broadcast from - * nodeB towards - * - * Parameters: - * @param[in] graph = the graph to examine - * @param[in] nodeA = the node number of the first node - * @param[in] nodeB = the node number of the second node - * OU results = the broadcast routes for nodeA from nodeB - * --------------------------------------------------------------------------------------- - */ -static u8 graphGetBc(u8 *graph, u8 nodeA, u8 nodeB) -{ - u8 size = graph[0]; - ASSERT(size <= MAX_NODES); - ASSERT((nodeA < size) && (nodeB < size)); - return graph[1+(nodeA*size+nodeB)*2]; -} - - -/*************************************************************************** - *** GENERIC HYPERTRANSPORT DISCOVERY CODE *** - ***************************************************************************/ - -/*---------------------------------------------------------------------------------------- - * void - * routeFromBSP(u8 targetNode, u8 actualTarget, sMainData *pDat) - * - * Description: - * Ensure a request / response route from target node to bsp. Since target node is - * always a predecessor of actual target node, each node gets a route to actual target - * on the link that goes to target. The routing produced by this routine is adequate - * for config access during discovery, but NOT for coherency. - * - * Parameters: - * @param[in] u8 targetNode = the path to actual target goes through target - * @param[in] u8 actualTarget = the ultimate target being routed to - * @param[in] sMainData* pDat = our global state, port config info - * --------------------------------------------------------------------------------------- - */ -static void routeFromBSP(u8 targetNode, u8 actualTarget, sMainData *pDat) -{ - u8 predecessorNode, predecessorLink, currentPair; - - if (targetNode == 0) - return; /* BSP has no predecessor, stop */ - - /* Search for the link that connects targetNode to its predecessor */ - currentPair = 0; - while (pDat->PortList[currentPair*2+1].NodeID != targetNode) - { - currentPair++; - ASSERT(currentPair < pDat->TotalLinks); - } - - predecessorNode = pDat->PortList[currentPair*2].NodeID; - predecessorLink = pDat->PortList[currentPair*2].Link; - - /* Recursively call self to ensure the route from the BSP to the Predecessor */ - /* Node is established */ - routeFromBSP(predecessorNode, actualTarget, pDat); - - pDat->nb->writeRoutingTable(predecessorNode, actualTarget, predecessorLink, pDat->nb); -} - -/*---------------------------------------------------------------------------*/ - -/** - * u8 - * convertNodeToLink(u8 srcNode, u8 targetNode, sMainData *pDat) - * - * Description: - * Return the link on source node which connects to target node - * - * Parameters: - * @param[in] srcNode = the source node - * @param[in] targetNode = the target node to find the link to - * @param[in] pDat = our global state - * @return the link on source which connects to target - * - */ -static u8 convertNodeToLink(u8 srcNode, u8 targetNode, sMainData *pDat) -{ - u8 targetlink = INVALID_LINK; - u8 k; - - for (k = 0; k < pDat->TotalLinks*2; k += 2) - { - if ((pDat->PortList[k+0].NodeID == srcNode) && (pDat->PortList[k+1].NodeID == targetNode)) - { - targetlink = pDat->PortList[k+0].Link; - break; - } - else if ((pDat->PortList[k+1].NodeID == srcNode) && (pDat->PortList[k+0].NodeID == targetNode)) - { - targetlink = pDat->PortList[k+1].Link; - break; - } - } - ASSERT(targetlink != INVALID_LINK); - - return targetlink; -} - - -/*---------------------------------------------------------------------------------------- - * void - * htDiscoveryFloodFill(sMainData *pDat) - * - * Description: - * Discover all coherent devices in the system, initializing some basics like node IDs - * and total nodes found in the process. As we go we also build a representation of the - * discovered system which we will use later to program the routing tables. During this - * step, the routing is via default link back to BSP and to each new node on the link it - * was discovered on (no coherency is active yet). - * - * Parameters: - * @param[in] sMainData* pDat = our global state - * --------------------------------------------------------------------------------------- - */ -static void htDiscoveryFloodFill(sMainData *pDat) -{ - uint8_t currentNode = 0; - uint8_t currentLink; - uint8_t currentLinkID; - - /* NOTE - * Each node inside a dual node (socket G34) processor must share - * an adjacent node ID. Alter the link scan order such that the - * other internal node is always scanned first... - */ - uint8_t currentLinkScanOrder_Default[8] = {0, 1, 2, 3, 4, 5, 6, 7}; - uint8_t currentLinkScanOrder_G34_Fam10[8] = {1, 0, 2, 3, 4, 5, 6, 7}; - uint8_t currentLinkScanOrder_G34_Fam15[8] = {2, 0, 1, 3, 4, 5, 6, 7}; - - uint8_t fam15h = 0; - uint8_t rev_gte_d = 0; - uint8_t dual_node = 0; - uint32_t f3xe8; - uint32_t family; - uint32_t model; - - f3xe8 = pci_read_config32(NODE_PCI(0, 3), 0xe8); - - family = model = cpuid_eax(0x80000001); - model = ((model & 0xf0000) >> 12) | ((model & 0xf0) >> 4); - family = ((family & 0xf00000) >> 16) | ((family & 0xf00) >> 8); - - if (family >= 0x6f) { - /* Family 15h or later */ - fam15h = 1; - } - - if ((model >= 0x8) || fam15h) - /* Revision D or later */ - rev_gte_d = 1; - - if (rev_gte_d) - /* Check for dual node capability */ - if (f3xe8 & 0x20000000) - dual_node = 1; - - /* Entries are always added in pairs, the even indices are the 'source' - * side closest to the BSP, the odd indices are the 'destination' side - */ - while (currentNode <= pDat->NodesDiscovered) - { - u32 temp; - - if (currentNode != 0) - { - /* Set path from BSP to currentNode */ - routeFromBSP(currentNode, currentNode, pDat); - - /* Set path from BSP to currentNode for currentNode+1 if - * currentNode+1 != MAX_NODES - */ - if (currentNode+1 != MAX_NODES) - routeFromBSP(currentNode, currentNode+1, pDat); - - /* Configure currentNode to route traffic to the BSP through its - * default link - */ - pDat->nb->writeRoutingTable(currentNode, 0, pDat->nb->readDefLnk(currentNode, pDat->nb), pDat->nb); - } - - /* Set currentNode's NodeID field to currentNode */ - pDat->nb->writeNodeID(currentNode, currentNode, pDat->nb); - - /* Enable routing tables on currentNode */ - pDat->nb->enableRoutingTables(currentNode, pDat->nb); - - for (currentLinkID = 0; currentLinkID < pDat->nb->maxLinks; currentLinkID++) - { - BOOL linkfound; - u8 token; - - if (currentLinkID < 8) { - if (dual_node) { - if (fam15h) - currentLink = currentLinkScanOrder_G34_Fam15[currentLinkID]; - else - currentLink = currentLinkScanOrder_G34_Fam10[currentLinkID]; - } else { - currentLink = currentLinkScanOrder_Default[currentLinkID]; - } - } else { - currentLink = currentLinkID; - } - - if (pDat->HtBlock->AMD_CB_IgnoreLink && pDat->HtBlock->AMD_CB_IgnoreLink(currentNode, currentLink)) - continue; - - if (pDat->nb->readTrueLinkFailStatus(currentNode, currentLink, pDat, pDat->nb)) - continue; - - /* Make sure that the link is connected, coherent, and ready */ - if (!pDat->nb->verifyLinkIsCoherent(currentNode, currentLink, pDat->nb)) - continue; - - - /* Test to see if the currentLink has already been explored */ - linkfound = FALSE; - for (temp = 0; temp < pDat->TotalLinks; temp++) - { - if ((pDat->PortList[temp*2+1].NodeID == currentNode) && - (pDat->PortList[temp*2+1].Link == currentLink)) - { - linkfound = TRUE; - break; - } - } - if (linkfound) - { - /* We had already expored this link */ - continue; - } - - if (pDat->nb->handleSpecialLinkCase(currentNode, currentLink, pDat, pDat->nb)) - { - continue; - } - - /* Modify currentNode's routing table to use currentLink to send - * traffic to currentNode+1 - */ - pDat->nb->writeRoutingTable(currentNode, currentNode+1, currentLink, pDat->nb); - - /* Check the northbridge of the node we just found, to make sure it is compatible - * before doing anything else to it. - */ - if (!pDat->nb->isCompatible(currentNode+1, pDat->nb)) - { - u8 nodeToKill; - - /* Notify BIOS of event (while variables are still the same) */ - if (pDat->HtBlock->AMD_CB_EventNotify) - { - sHtEventCohFamilyFeud evt; - evt.eSize = sizeof(sHtEventCohFamilyFeud); - evt.node = currentNode; - evt.link = currentLink; - evt.totalNodes = pDat->NodesDiscovered; - - pDat->HtBlock->AMD_CB_EventNotify(HT_EVENT_CLASS_ERROR, - HT_EVENT_COH_FAMILY_FEUD, - (u8 *)&evt); - } - - /* If node is not compatible, force boot to 1P - * If they are not compatible stop cHT init and: - * 1. Disable all cHT links on the BSP - * 2. Configure the BSP routing tables as a UP. - * 3. Notify main BIOS. - */ - pDat->NodesDiscovered = 0; - currentNode = 0; - pDat->TotalLinks = 0; - /* Abandon our coherent link data structure. At this point there may - * be coherent links on the BSP that are not yet in the portList, and - * we have to turn them off anyway. So depend on the hardware to tell us. - */ - for (currentLink = 0; currentLink < pDat->nb->maxLinks; currentLink++) - { - /* Stop all links which are connected, coherent, and ready */ - if (pDat->nb->verifyLinkIsCoherent(currentNode, currentLink, pDat->nb)) - pDat->nb->stopLink(currentNode, currentLink, pDat->nb); - } - - for (nodeToKill = 0; nodeToKill < pDat->nb->maxNodes; nodeToKill++) - { - pDat->nb->writeFullRoutingTable(0, nodeToKill, ROUTETOSELF, ROUTETOSELF, 0, pDat->nb); - } - - /* End Coherent Discovery */ - STOP_HERE; - break; - } - - /* Read token from Current+1 */ - token = pDat->nb->readToken(currentNode+1, pDat->nb); - ASSERT(token <= pDat->NodesDiscovered); - if (token == 0) - { - pDat->NodesDiscovered++; - ASSERT(pDat->NodesDiscovered < pDat->nb->maxNodes); - /* Check the capability of northbridges against the currently known configuration */ - if (!pDat->nb->isCapable(currentNode+1, pDat, pDat->nb)) - { - u8 nodeToKill; - - /* Notify BIOS of event */ - if (pDat->HtBlock->AMD_CB_EventNotify) - { - sHtEventCohMpCapMismatch evt; - evt.eSize = sizeof(sHtEventCohMpCapMismatch); - evt.node = currentNode; - evt.link = currentLink; - evt.sysMpCap = pDat->sysMpCap; - evt.totalNodes = pDat->NodesDiscovered; - - pDat->HtBlock->AMD_CB_EventNotify(HT_EVENT_CLASS_ERROR, - HT_EVENT_COH_MPCAP_MISMATCH, - (u8 *)&evt); - } - - pDat->NodesDiscovered = 0; - currentNode = 0; - pDat->TotalLinks = 0; - - for (nodeToKill = 0; nodeToKill < pDat->nb->maxNodes; nodeToKill++) - { - pDat->nb->writeFullRoutingTable(0, nodeToKill, ROUTETOSELF, ROUTETOSELF, 0, pDat->nb); - } - - /* End Coherent Discovery */ - STOP_HERE; - break; - } - - token = pDat->NodesDiscovered; - pDat->nb->writeToken(currentNode+1, token, pDat->nb); - /* Inform that we have discovered a node, so that logical id to - * socket mapping info can be recorded. - */ - if (pDat->HtBlock->AMD_CB_EventNotify) - { - sHtEventCohNodeDiscovered evt; - evt.eSize = sizeof(sHtEventCohNodeDiscovered); - evt.node = currentNode; - evt.link = currentLink; - evt.newNode = token; - - pDat->HtBlock->AMD_CB_EventNotify(HT_EVENT_CLASS_INFO, - HT_EVENT_COH_NODE_DISCOVERED, - (u8 *)&evt); - } - } - - if (pDat->TotalLinks == MAX_PLATFORM_LINKS) - { - /* - * Exceeded our capacity to describe all coherent links found in the system. - * Error strategy: - * Auto recovery is not possible because data space is already all used. - * If the callback is not implemented or returns we will continue to initialize - * the fabric we are capable of representing, adding no more nodes or links. - * This should yield a bootable topology, but likely not the one intended. - * We cannot continue discovery, there may not be any way to route a new - * node back to the BSP if we can't add links to our representation of the system. - */ - if (pDat->HtBlock->AMD_CB_EventNotify) - { - sHtEventCohLinkExceed evt; - evt.eSize = sizeof(sHtEventCohLinkExceed); - evt.node = currentNode; - evt.link = currentLink; - evt.targetNode = token; - evt.totalNodes = pDat->NodesDiscovered; - evt.maxLinks = pDat->nb->maxLinks; - - pDat->HtBlock->AMD_CB_EventNotify(HT_EVENT_CLASS_ERROR, - HT_EVENT_COH_LINK_EXCEED, - (u8 *)&evt); - } - /* Force link and node loops to halt */ - STOP_HERE; - currentNode = pDat->NodesDiscovered; - break; - } - - pDat->PortList[pDat->TotalLinks*2].Type = PORTLIST_TYPE_CPU; - pDat->PortList[pDat->TotalLinks*2].Link = currentLink; - pDat->PortList[pDat->TotalLinks*2].NodeID = currentNode; - - pDat->PortList[pDat->TotalLinks*2+1].Type = PORTLIST_TYPE_CPU; - pDat->PortList[pDat->TotalLinks*2+1].Link = pDat->nb->readDefLnk(currentNode+1, pDat->nb); - pDat->PortList[pDat->TotalLinks*2+1].NodeID = token; - - pDat->TotalLinks++; - - if (!pDat->sysMatrix[currentNode][token]) - { - pDat->sysDegree[currentNode]++; - pDat->sysDegree[token]++; - pDat->sysMatrix[currentNode][token] = TRUE; - pDat->sysMatrix[token][currentNode] = TRUE; - } - } - currentNode++; - } -} - - -/*************************************************************************** - *** ISOMORPHISM BASED ROUTING TABLE GENERATION CODE *** - ***************************************************************************/ - -/*---------------------------------------------------------------------------------------- - * BOOL - * isoMorph(u8 i, sMainData *pDat) - * - * Description: - * Is graphA isomorphic to graphB? - * if this function returns true, then Perm will contain the permutation - * required to transform graphB into graphA. - * We also use the degree of each node, that is the number of connections it has, to - * speed up rejection of non-isomorphic graphs (if there is a node in graphA with n - * connections, there must be at least one unmatched in graphB with n connections). - * - * Parameters: - * @param[in] u8 i = the discovered node which we are trying to match - * with a permutation the topology - * @param[in]/@param[out] sMainData* pDat = our global state, degree and adjacency matrix, - * output a permutation if successful - * @param[out] BOOL results = the graphs are (or are not) isomorphic - * --------------------------------------------------------------------------------------- - */ -static BOOL isoMorph(u8 i, sMainData *pDat) -{ - u8 j, k; - u8 nodecnt; - - /* We have only been called if nodecnt == pSelected->size ! */ - nodecnt = pDat->NodesDiscovered+1; - - if (i != nodecnt) - { - /* Keep building the permutation */ - for (j = 0; j < nodecnt; j++) - { - /* Make sure the degree matches */ - if (pDat->sysDegree[i] != pDat->dbDegree[j]) - continue; - - /* Make sure that j hasn't been used yet (ought to use a "used" */ - /* array instead, might be faster) */ - for (k = 0; k < i; k++) - { - if (pDat->Perm[k] == j) - break; - } - if (k != i) - continue; - pDat->Perm[i] = j; - if (isoMorph(i+1, pDat)) - return TRUE; - } - return FALSE; - } else { - /* Test to see if the permutation is isomorphic */ - for (j = 0; j < nodecnt; j++) - { - for (k = 0; k < nodecnt; k++) - { - if (pDat->sysMatrix[j][k] != - pDat->dbMatrix[pDat->Perm[j]][pDat->Perm[k]]) - return FALSE; - } - } - return TRUE; - } -} - - -/*---------------------------------------------------------------------------------------- - * void - * lookupComputeAndLoadRoutingTables(sMainData *pDat) - * - * Description: - * Using the description of the fabric topology we discovered, try to find a match - * among the supported topologies. A supported topology description matches - * the discovered fabric if the nodes can be matched in such a way that all the nodes connected - * in one set are exactly the nodes connected in the other (formally, that the graphs are - * isomorphic). Which links are used is not really important to matching. If the graphs - * match, then there is a permutation of one that translates the node positions and linkages - * to the other. - * - * In order to make the isomorphism test efficient, we test for matched number of nodes - * (a 4 node fabric is not isomorphic to a 2 node topology), and provide degrees of nodes - * to the isomorphism test. - * - * The generic routing table solution for any topology is predetermined and represented - * as part of the topology. The permutation we computed tells us how to interpret the - * routing onto the fabric we discovered. We do this working backward from the last - * node discovered to the BSP, writing the routing tables as we go. - * - * Parameters: - * @param[in] sMainData* pDat = our global state, the discovered fabric, - * @param[out] degree matrix, permutation - * --------------------------------------------------------------------------------------- - */ -static void lookupComputeAndLoadRoutingTables(sMainData *pDat) -{ - u8 **pTopologyList; - u8 *pSelected; - - int i, j, k, size; - - size = pDat->NodesDiscovered + 1; - /* Use the provided topology list or the internal, default one. */ - pTopologyList = pDat->HtBlock->topolist; - if (pTopologyList == NULL) - { - getAmdTopolist(&pTopologyList); - } - - pSelected = *pTopologyList; - while (pSelected != NULL) - { - if (graphHowManyNodes(pSelected) == size) - { - /* Build Degree vector and Adjency Matrix for this entry */ - for (i = 0; i < size; i++) - { - pDat->dbDegree[i] = 0; - for (j = 0; j < size; j++) - { - if (graphIsAdjacent(pSelected, i, j)) - { - pDat->dbMatrix[i][j] = 1; - pDat->dbDegree[i]++; - } - else - { - pDat->dbMatrix[i][j] = 0; - } - } - } - if (isoMorph(0, pDat)) - break; /* A matching topology was found */ - } - - pTopologyList++; - pSelected = *pTopologyList; - } - - if (pSelected != NULL) - { - /* Compute the reverse Permutation */ - for (i = 0; i < size; i++) - { - pDat->ReversePerm[pDat->Perm[i]] = i; - } - - /* Start with the last discovered node, and move towards the BSP */ - for (i = size-1; i >= 0; i--) - { - for (j = 0; j < size; j++) - { - u8 ReqTargetLink, RspTargetLink; - u8 ReqTargetNode, RspTargetNode; - - u8 AbstractBcTargetNodes = graphGetBc(pSelected, pDat->Perm[i], pDat->Perm[j]); - u32 BcTargetLinks = 0; - - for (k = 0; k < MAX_NODES; k++) - { - if (AbstractBcTargetNodes & ((u32)1<ReversePerm[k], pDat); - } - } - - if (i == j) - { - ReqTargetLink = ROUTETOSELF; - RspTargetLink = ROUTETOSELF; - } - else - { - ReqTargetNode = graphGetReq(pSelected, pDat->Perm[i], pDat->Perm[j]); - ReqTargetLink = convertNodeToLink(i, pDat->ReversePerm[ReqTargetNode], pDat); - - RspTargetNode = graphGetRsp(pSelected, pDat->Perm[i], pDat->Perm[j]); - RspTargetLink = convertNodeToLink(i, pDat->ReversePerm[RspTargetNode], pDat); - } - - pDat->nb->writeFullRoutingTable(i, j, ReqTargetLink, RspTargetLink, BcTargetLinks, pDat->nb); - } - /* Clean up discovery 'footprint' that otherwise remains in the routing table. It didn't hurt - * anything, but might cause confusion during debug and validation. Do this by setting the - * route back to all self routes. Since it's the node that would be one more than actually installed, - * this only applies if less than maxNodes were found. - */ - if (size < pDat->nb->maxNodes) - { - pDat->nb->writeFullRoutingTable(i, size, ROUTETOSELF, ROUTETOSELF, 0, pDat->nb); - } - } - - } - else - { - /* - * No Matching Topology was found - * Error Strategy: - * Auto recovery doesn't seem likely, Force boot as 1P. - * For reporting, logging, provide number of nodes - * If not implemented or returns, boot as BSP uniprocessor. - */ - if (pDat->HtBlock->AMD_CB_EventNotify) - { - sHtEventCohNoTopology evt; - evt.eSize = sizeof(sHtEventCohNoTopology); - evt.totalNodes = pDat->NodesDiscovered; - - pDat->HtBlock->AMD_CB_EventNotify(HT_EVENT_CLASS_ERROR, - HT_EVENT_COH_NO_TOPOLOGY, - (u8 *)&evt); - } - STOP_HERE; - /* Force 1P */ - pDat->NodesDiscovered = 0; - pDat->TotalLinks = 0; - pDat->nb->enableRoutingTables(0, pDat->nb); - } -} -#endif /* HT_BUILD_NC_ONLY */ - - -/*---------------------------------------------------------------------------------------- - * void - * finializeCoherentInit(sMainData *pDat) - * - * Description: - * Find the total number of cores and update the number of nodes and cores in all cpus. - * Limit CPU config access to installed cpus. - * - * Parameters: - * @param[in] sMainData* pDat = our global state, number of nodes discovered. - * --------------------------------------------------------------------------------------- - */ -static void finializeCoherentInit(sMainData *pDat) -{ - u8 curNode; - - u8 totalCores = 0; - for (curNode = 0; curNode < pDat->NodesDiscovered+1; curNode++) - { - totalCores += pDat->nb->getNumCoresOnNode(curNode, pDat->nb); - } - - for (curNode = 0; curNode < pDat->NodesDiscovered+1; curNode++) - { - pDat->nb->setTotalNodesAndCores(curNode, pDat->NodesDiscovered+1, totalCores, pDat->nb); - } - - for (curNode = 0; curNode < pDat->NodesDiscovered+1; curNode++) - { - pDat->nb->limitNodes(curNode, pDat->nb); - } - -} - -/*---------------------------------------------------------------------------------------- - * void - * coherentInit(sMainData *pDat) - * - * Description: - * Perform discovery and initialization of the coherent fabric. - * - * Parameters: - * @param[in] sMainData* pDat = our global state - * --------------------------------------------------------------------------------------- - */ -static void coherentInit(sMainData *pDat) -{ -#ifdef HT_BUILD_NC_ONLY - /* Replace discovery process with: - * No other nodes, no coherent links - * Enable routing tables on currentNode, for power on self route - */ - pDat->NodesDiscovered = 0; - pDat->TotalLinks = 0; - pDat->nb->enableRoutingTables(0, pDat->nb); -#else - u8 i, j; - - pDat->NodesDiscovered = 0; - pDat->TotalLinks = 0; - for (i = 0; i < MAX_NODES; i++) - { - pDat->sysDegree[i] = 0; - for (j = 0; j < MAX_NODES; j++) - { - pDat->sysMatrix[i][j] = 0; - } - } - - htDiscoveryFloodFill(pDat); - lookupComputeAndLoadRoutingTables(pDat); -#endif - finializeCoherentInit(pDat); -} - -/*************************************************************************** - *** Non-coherent init code *** - *** Algorithms *** - ***************************************************************************/ -/*---------------------------------------------------------------------------------------- - * void - * processLink(u8 node, u8 link, sMainData *pDat) - * - * Description: - * Process a non-coherent link, enabling a range of bus numbers, and setting the device - * ID for all devices found - * - * Parameters: - * @param[in] u8 node = Node on which to process nc init - * @param[in] u8 link = The non-coherent link on that node - * @param[in] sMainData* pDat = our global state - * --------------------------------------------------------------------------------------- - */ -static void processLink(u8 node, u8 link, sMainData *pDat) -{ - u8 secBus, subBus; - u32 currentBUID; - u32 temp; - u32 unitIDcnt; - SBDFO currentPtr; - u8 depth; - const u8 *pSwapPtr; - - SBDFO lastSBDFO = ILLEGAL_SBDFO; - u8 lastLink = 0; - - ASSERT(node < pDat->nb->maxNodes && link < pDat->nb->maxLinks); - - if ((pDat->HtBlock->AMD_CB_OverrideBusNumbers == NULL) - || !pDat->HtBlock->AMD_CB_OverrideBusNumbers(node, link, &secBus, &subBus)) - { - /* Assign Bus numbers */ - if (pDat->AutoBusCurrent >= pDat->HtBlock->AutoBusMax) - { - /* If we run out of Bus Numbers notify, if call back unimplemented or if it - * returns, skip this chain - */ - if (pDat->HtBlock->AMD_CB_EventNotify) - { - sHTEventNcohBusMaxExceed evt; - evt.eSize = sizeof(sHTEventNcohBusMaxExceed); - evt.node = node; - evt.link = link; - evt.bus = pDat->AutoBusCurrent; - - pDat->HtBlock->AMD_CB_EventNotify(HT_EVENT_CLASS_ERROR,HT_EVENT_NCOH_BUS_MAX_EXCEED,(u8 *)&evt); - } - STOP_HERE; - return; - } - - if (pDat->UsedCfgMapEntires >= 4) - { - /* If we have used all the PCI Config maps we can't add another chain. - * Notify and if call back is unimplemented or returns, skip this chain. - */ - if (pDat->HtBlock->AMD_CB_EventNotify) - { - sHtEventNcohCfgMapExceed evt; - evt.eSize = sizeof(sHtEventNcohCfgMapExceed); - evt.node = node; - evt.link = link; - - pDat->HtBlock->AMD_CB_EventNotify(HT_EVENT_CLASS_ERROR, - HT_EVENT_NCOH_CFG_MAP_EXCEED, - (u8 *)&evt); - } - STOP_HERE; - return; - } - - secBus = pDat->AutoBusCurrent; - subBus = secBus + pDat->HtBlock->AutoBusIncrement-1; - pDat->AutoBusCurrent += pDat->HtBlock->AutoBusIncrement; - } - - pDat->nb->setCFGAddrMap(pDat->UsedCfgMapEntires, secBus, subBus, node, link, pDat, pDat->nb); - pDat->UsedCfgMapEntires++; - - if ((pDat->HtBlock->AMD_CB_ManualBUIDSwapList != NULL) - && pDat->HtBlock->AMD_CB_ManualBUIDSwapList(node, link, &pSwapPtr)) - { - /* Manual non-coherent BUID assignment */ - currentBUID = 1; - - /* Assign BUID's per manual override */ - while (*pSwapPtr != 0xFF) - { - currentPtr = MAKE_SBDFO(0, secBus, *pSwapPtr, 0, 0); - pSwapPtr++; - - do - { - AmdPCIFindNextCap(¤tPtr); - ASSERT(currentPtr != ILLEGAL_SBDFO); - AmdPCIRead(currentPtr, &temp); - } while (!IS_HT_SLAVE_CAPABILITY(temp)); - - currentBUID = *pSwapPtr; - pSwapPtr++; - AmdPCIWriteBits(currentPtr, 20, 16, ¤tBUID); - } - - /* Build chain of devices */ - depth = 0; - pSwapPtr++; - while (*pSwapPtr != 0xFF) - { - pDat->PortList[pDat->TotalLinks*2].NodeID = node; - if (depth == 0) - { - pDat->PortList[pDat->TotalLinks*2].Type = PORTLIST_TYPE_CPU; - pDat->PortList[pDat->TotalLinks*2].Link = link; - } - else - { - pDat->PortList[pDat->TotalLinks*2].Type = PORTLIST_TYPE_IO; - pDat->PortList[pDat->TotalLinks*2].Link = 1-lastLink; - pDat->PortList[pDat->TotalLinks*2].HostLink = link; - pDat->PortList[pDat->TotalLinks*2].HostDepth = depth-1; - pDat->PortList[pDat->TotalLinks*2].Pointer = lastSBDFO; - } - - pDat->PortList[pDat->TotalLinks*2+1].Type = PORTLIST_TYPE_IO; - pDat->PortList[pDat->TotalLinks*2+1].NodeID = node; - pDat->PortList[pDat->TotalLinks*2+1].HostLink = link; - pDat->PortList[pDat->TotalLinks*2+1].HostDepth = depth; - - currentPtr = MAKE_SBDFO(0, secBus, (*pSwapPtr & 0x3F), 0, 0); - do - { - AmdPCIFindNextCap(¤tPtr); - ASSERT(currentPtr != ILLEGAL_SBDFO); - AmdPCIRead(currentPtr, &temp); - } while (!IS_HT_SLAVE_CAPABILITY(temp)); - pDat->PortList[pDat->TotalLinks*2+1].Pointer = currentPtr; - lastSBDFO = currentPtr; - - /* Bit 6 indicates whether orientation override is desired. - * Bit 7 indicates the upstream link if overriding. - */ - /* assert catches at least the one known incorrect setting */ - ASSERT ((*pSwapPtr & 0x40) || (!(*pSwapPtr & 0x80))); - if (*pSwapPtr & 0x40) - { - /* Override the device's orientation */ - lastLink = *pSwapPtr >> 7; - } - else - { - /* Detect the device's orientation */ - AmdPCIReadBits(currentPtr, 26, 26, &temp); - lastLink = (u8)temp; - } - pDat->PortList[pDat->TotalLinks*2+1].Link = lastLink; - - depth++; - pDat->TotalLinks++; - pSwapPtr++; - } - } - else - { - /* Automatic non-coherent device detection */ - depth = 0; - currentBUID = 1; - while (1) - { - currentPtr = MAKE_SBDFO(0, secBus, 0, 0, 0); - - AmdPCIRead(currentPtr, &temp); - if (temp == 0xFFFFFFFF) - /* No device found at currentPtr */ - break; - - if (pDat->TotalLinks == MAX_PLATFORM_LINKS) - { - /* - * Exceeded our capacity to describe all non-coherent links found in the system. - * Error strategy: - * Auto recovery is not possible because data space is already all used. - */ - if (pDat->HtBlock->AMD_CB_EventNotify) - { - sHtEventNcohLinkExceed evt; - evt.eSize = sizeof(sHtEventNcohLinkExceed); - evt.node = node; - evt.link = link; - evt.depth = depth; - evt.maxLinks = pDat->nb->maxLinks; - - pDat->HtBlock->AMD_CB_EventNotify(HT_EVENT_CLASS_ERROR, - HT_EVENT_NCOH_LINK_EXCEED, - (u8 *)&evt); - } - /* Force link loop to halt */ - STOP_HERE; - break; - } - - pDat->PortList[pDat->TotalLinks*2].NodeID = node; - if (depth == 0) - { - pDat->PortList[pDat->TotalLinks*2].Type = PORTLIST_TYPE_CPU; - pDat->PortList[pDat->TotalLinks*2].Link = link; - } - else - { - pDat->PortList[pDat->TotalLinks*2].Type = PORTLIST_TYPE_IO; - pDat->PortList[pDat->TotalLinks*2].Link = 1-lastLink; - pDat->PortList[pDat->TotalLinks*2].HostLink = link; - pDat->PortList[pDat->TotalLinks*2].HostDepth = depth-1; - pDat->PortList[pDat->TotalLinks*2].Pointer = lastSBDFO; - } - - pDat->PortList[pDat->TotalLinks*2+1].Type = PORTLIST_TYPE_IO; - pDat->PortList[pDat->TotalLinks*2+1].NodeID = node; - pDat->PortList[pDat->TotalLinks*2+1].HostLink = link; - pDat->PortList[pDat->TotalLinks*2+1].HostDepth = depth; - - do - { - AmdPCIFindNextCap(¤tPtr); - ASSERT(currentPtr != ILLEGAL_SBDFO); - AmdPCIRead(currentPtr, &temp); - } while (!IS_HT_SLAVE_CAPABILITY(temp)); - - AmdPCIReadBits(currentPtr, 25, 21, &unitIDcnt); - if ((unitIDcnt + currentBUID > 31) || ((secBus == 0) && (unitIDcnt + currentBUID > 24))) - { - /* An error handler for the case where we run out of BUID's on a chain */ - if (pDat->HtBlock->AMD_CB_EventNotify) - { - sHtEventNcohBuidExceed evt; - evt.eSize = sizeof(sHtEventNcohBuidExceed); - evt.node = node; - evt.link = link; - evt.depth = depth; - evt.currentBUID = (uint8)currentBUID; - evt.unitCount = (uint8)unitIDcnt; - - pDat->HtBlock->AMD_CB_EventNotify(HT_EVENT_CLASS_ERROR,HT_EVENT_NCOH_BUID_EXCEED,(u8 *)&evt); - } - STOP_HERE; - break; - } - AmdPCIWriteBits(currentPtr, 20, 16, ¤tBUID); - - - currentPtr += MAKE_SBDFO(0, 0, currentBUID, 0, 0); - AmdPCIReadBits(currentPtr, 20, 16, &temp); - if (temp != currentBUID) - { - /* An error handler for this critical error */ - if (pDat->HtBlock->AMD_CB_EventNotify) - { - sHtEventNcohDeviceFailed evt; - evt.eSize = sizeof(sHtEventNcohDeviceFailed); - evt.node = node; - evt.link = link; - evt.depth = depth; - evt.attemptedBUID = (uint8)currentBUID; - - pDat->HtBlock->AMD_CB_EventNotify(HT_EVENT_CLASS_ERROR,HT_EVENT_NCOH_DEVICE_FAILED,(u8 *)&evt); - } - STOP_HERE; - break; - } - - AmdPCIReadBits(currentPtr, 26, 26, &temp); - pDat->PortList[pDat->TotalLinks*2+1].Link = (u8)temp; - pDat->PortList[pDat->TotalLinks*2+1].Pointer = currentPtr; - - lastLink = (u8)temp; - lastSBDFO = currentPtr; - - depth++; - pDat->TotalLinks++; - currentBUID += unitIDcnt; - } - if (pDat->HtBlock->AMD_CB_EventNotify) - { - /* Provide information on automatic device results */ - sHtEventNcohAutoDepth evt; - evt.eSize = sizeof(sHtEventNcohAutoDepth); - evt.node = node; - evt.link = link; - evt.depth = (depth - 1); - - pDat->HtBlock->AMD_CB_EventNotify(HT_EVENT_CLASS_INFO,HT_EVENT_NCOH_AUTO_DEPTH,(u8 *)&evt); - } - } -} - - -/*---------------------------------------------------------------------------------------- - * void - * ncInit(sMainData *pDat) - * - * Description: - * Initialize the non-coherent fabric. Begin with the compat link on the BSP, then - * find and initialize all other non-coherent chains. - * - * Parameters: - * @param[in] sMainData* pDat = our global state - * --------------------------------------------------------------------------------------- - */ -static void ncInit(sMainData *pDat) -{ - u8 node, link; - u8 compatLink; - - compatLink = pDat->nb->readSbLink(pDat->nb); - processLink(0, compatLink, pDat); - - for (node = 0; node <= pDat->NodesDiscovered; node++) - { - for (link = 0; link < pDat->nb->maxLinks; link++) - { - if (pDat->HtBlock->AMD_CB_IgnoreLink && pDat->HtBlock->AMD_CB_IgnoreLink(node, link)) - continue; /* Skip the link */ - - if (node == 0 && link == compatLink) - continue; - - if (pDat->nb->readTrueLinkFailStatus(node, link, pDat, pDat->nb)) - continue; - - if (pDat->nb->verifyLinkIsNonCoherent(node, link, pDat->nb)) - processLink(node, link, pDat); - } - } -} - -/*************************************************************************** - *** Link Optimization *** - ***************************************************************************/ - -/*---------------------------------------------------------------------------------------- - * void - * regangLinks(sMainData *pDat) - * - * Description: - * Test the sublinks of a link to see if they qualify to be reganged. If they do, - * update the port list data to indicate that this should be done. Note that no - * actual hardware state is changed in this routine. - * - * Parameters: - * @param[in,out] sMainData* pDat = our global state - * --------------------------------------------------------------------------------------- - */ -static void regangLinks(sMainData *pDat) -{ -#ifndef HT_BUILD_NC_ONLY - u8 i, j; - for (i = 0; i < pDat->TotalLinks*2; i += 2) - { - ASSERT(pDat->PortList[i].Type < 2 && pDat->PortList[i].Link < pDat->nb->maxLinks); /* Data validation */ - ASSERT(pDat->PortList[i+1].Type < 2 && pDat->PortList[i+1].Link < pDat->nb->maxLinks); /* data validation */ - ASSERT(!(pDat->PortList[i].Type == PORTLIST_TYPE_IO && pDat->PortList[i+1].Type == PORTLIST_TYPE_CPU)); /* ensure src is closer to the bsp than dst */ - - /* Regang is false unless we pass all conditions below */ - pDat->PortList[i].SelRegang = FALSE; - pDat->PortList[i+1].SelRegang = FALSE; - - if ((pDat->PortList[i].Type != PORTLIST_TYPE_CPU) || (pDat->PortList[i+1].Type != PORTLIST_TYPE_CPU)) - continue; /* Only process CPU to CPU links */ - - for (j = i+2; j < pDat->TotalLinks*2; j += 2) - { - if ((pDat->PortList[j].Type != PORTLIST_TYPE_CPU) || (pDat->PortList[j+1].Type != PORTLIST_TYPE_CPU)) - continue; /* Only process CPU to CPU links */ - - if (pDat->PortList[i].NodeID != pDat->PortList[j].NodeID) - continue; /* Links must be from the same source */ - - if (pDat->PortList[i+1].NodeID != pDat->PortList[j+1].NodeID) - continue; /* Link must be to the same target */ - - if ((pDat->PortList[i].Link & 3) != (pDat->PortList[j].Link & 3)) - continue; /* Ensure same source base port */ - - if ((pDat->PortList[i+1].Link & 3) != (pDat->PortList[j+1].Link & 3)) - continue; /* Ensure same destination base port */ - - if ((pDat->PortList[i].Link & 4) != (pDat->PortList[i+1].Link & 4)) - continue; /* Ensure sublink0 routes to sublink0 */ - - ASSERT((pDat->PortList[j].Link & 4) == (pDat->PortList[j+1].Link & 4)); /* (therefore sublink1 routes to sublink1) */ - - if (pDat->HtBlock->AMD_CB_SkipRegang && - pDat->HtBlock->AMD_CB_SkipRegang(pDat->PortList[i].NodeID, - pDat->PortList[i].Link & 0x03, - pDat->PortList[i+1].NodeID, - pDat->PortList[i+1].Link & 0x03)) - { - continue; /* Skip regang */ - } - - - pDat->PortList[i].Link &= 0x03; /* Force to point to sublink0 */ - pDat->PortList[i+1].Link &= 0x03; - pDat->PortList[i].SelRegang = TRUE; /* Enable link reganging */ - pDat->PortList[i+1].SelRegang = TRUE; - pDat->PortList[i].PrvWidthOutCap = HT_WIDTH_16_BITS; - pDat->PortList[i+1].PrvWidthOutCap = HT_WIDTH_16_BITS; - pDat->PortList[i].PrvWidthInCap = HT_WIDTH_16_BITS; - pDat->PortList[i+1].PrvWidthInCap = HT_WIDTH_16_BITS; - - /* Delete PortList[j, j+1], slow but easy to debug implementation */ - pDat->TotalLinks--; - Amdmemcpy(&(pDat->PortList[j]), &(pDat->PortList[j+2]), sizeof(sPortDescriptor)*(pDat->TotalLinks*2-j)); - Amdmemset(&(pDat->PortList[pDat->TotalLinks*2]), INVALID_LINK, sizeof(sPortDescriptor)*2); - - /* //High performance, but would make debuging harder due to 'shuffling' of the records */ - /* //Amdmemcpy(PortList[TotalPorts-2], PortList[j], SIZEOF(sPortDescriptor)*2); */ - /* //TotalPorts -=2; */ - - break; /* Exit loop, advance to PortList[i+2] */ - } - } -#endif /* HT_BUILD_NC_ONLY */ -} - -static void detectIoLinkIsochronousCapable(sMainData *pDat) -{ - uint8_t i; - unsigned char iommu; - uint8_t isochronous_capable = 0; - - iommu = 1; - get_option(&iommu, "iommu"); - - for (i = 0; i < pDat->TotalLinks*2; i += 2) { - if ((pDat->PortList[i].Type == PORTLIST_TYPE_CPU) && (pDat->PortList[i+1].Type == PORTLIST_TYPE_IO)) { - if ((pDat->PortList[i].PrvFeatureCap & 0x1) && (pDat->PortList[i+1].PrvFeatureCap & 0x1)) { - pDat->PortList[i].enable_isochronous_mode = 1; - pDat->PortList[i+1].enable_isochronous_mode = 1; - isochronous_capable = 1; - } else { - pDat->PortList[i].enable_isochronous_mode = 0; - pDat->PortList[i+1].enable_isochronous_mode = 0; - } - } - } - - if (isochronous_capable && iommu) { - printk(BIOS_DEBUG, "Forcing HT links to isochronous mode due to enabled IOMMU\n"); - /* Isochronous mode must be set on all links if the IOMMU is enabled */ - for (i = 0; i < pDat->TotalLinks*2; i += 2) { - pDat->PortList[i].enable_isochronous_mode = 1; - pDat->PortList[i+1].enable_isochronous_mode = 1; - } - } -} - -/*---------------------------------------------------------------------------------------- - * void - * selectOptimalWidthAndFrequency(sMainData *pDat) - * - * Description: - * For all links: - * Examine both sides of a link and determine the optimal frequency and width, - * taking into account externally provided limits and enforcing any other limit - * or matching rules as applicable except sublink balancing. Update the port - * list date with the optimal settings. - * Note no hardware state changes in this routine. - * - * Parameters: - * @param[in,out] sMainData* pDat = our global state, port list data - * --------------------------------------------------------------------------------------- - */ -static void selectOptimalWidthAndFrequency(sMainData *pDat) -{ - u8 i, j; - uint32_t temp; - uint32_t cbPCBFreqLimit; - uint32_t cbPCBFreqLimit_NVRAM; - u8 cbPCBABDownstreamWidth; - u8 cbPCBBAUpstreamWidth; - - cbPCBFreqLimit_NVRAM = 0xfffff; - if (get_option(&temp, "hypertransport_speed_limit") == CB_SUCCESS) - cbPCBFreqLimit_NVRAM = ht_speed_limit[temp & 0xf]; - - if (!is_fam15h()) { - /* FIXME - * By default limit frequency to 2.6 GHz as there are residual - * problems with HT v3.1 implementation on at least some Socket G34 - * mainboards / Fam10h CPUs. - * Debug the issues and reenable this... - */ - if (cbPCBFreqLimit_NVRAM > 0xffff) - cbPCBFreqLimit_NVRAM = 0xffff; - } - - for (i = 0; i < pDat->TotalLinks*2; i += 2) - { - cbPCBFreqLimit = 0xfffff; // Maximum allowed by autoconfiguration - if (pDat->HtBlock->ht_link_configuration) - cbPCBFreqLimit = ht_speed_mhz_to_hw(pDat->HtBlock->ht_link_configuration->ht_speed_limit); - cbPCBFreqLimit = min(cbPCBFreqLimit, cbPCBFreqLimit_NVRAM); - -#if CONFIG(LIMIT_HT_DOWN_WIDTH_8) - cbPCBABDownstreamWidth = 8; -#else - cbPCBABDownstreamWidth = 16; -#endif - -#if CONFIG(LIMIT_HT_UP_WIDTH_8) - cbPCBBAUpstreamWidth = 8; -#else - cbPCBBAUpstreamWidth = 16; -#endif - - if ((pDat->PortList[i].Type == PORTLIST_TYPE_CPU) && (pDat->PortList[i+1].Type == PORTLIST_TYPE_CPU)) - { - if (pDat->HtBlock->AMD_CB_Cpu2CpuPCBLimits) - { - pDat->HtBlock->AMD_CB_Cpu2CpuPCBLimits( - pDat->PortList[i].NodeID, - pDat->PortList[i].Link, - pDat->PortList[i+1].NodeID, - pDat->PortList[i+1].Link, - &cbPCBABDownstreamWidth, - &cbPCBBAUpstreamWidth, &cbPCBFreqLimit - ); - } - } - else - { - if (pDat->HtBlock->AMD_CB_IOPCBLimits) - { - pDat->HtBlock->AMD_CB_IOPCBLimits( - pDat->PortList[i+1].NodeID, - pDat->PortList[i+1].HostLink, - pDat->PortList[i+1].HostDepth, - &cbPCBABDownstreamWidth, - &cbPCBBAUpstreamWidth, &cbPCBFreqLimit - ); - } - } - - temp = pDat->PortList[i].PrvFrequencyCap; - temp &= pDat->PortList[i+1].PrvFrequencyCap; - temp &= cbPCBFreqLimit; - pDat->PortList[i].CompositeFrequencyCap = temp; - pDat->PortList[i+1].CompositeFrequencyCap = temp; - - ASSERT (temp != 0); - for (j = 19;; j--) - { - if ((j == 16) || (j == 15)) - continue; - if (temp & ((uint32_t)1 << j)) - break; - } - - pDat->PortList[i].SelFrequency = j; - pDat->PortList[i+1].SelFrequency = j; - - temp = pDat->PortList[i].PrvWidthOutCap; - if (pDat->PortList[i+1].PrvWidthInCap < temp) - temp = pDat->PortList[i+1].PrvWidthInCap; - if (cbPCBABDownstreamWidth < temp) - temp = cbPCBABDownstreamWidth; - pDat->PortList[i].SelWidthOut = (u8)temp; - pDat->PortList[i+1].SelWidthIn = (u8)temp; - - temp = pDat->PortList[i].PrvWidthInCap; - if (pDat->PortList[i+1].PrvWidthOutCap < temp) - temp = pDat->PortList[i+1].PrvWidthOutCap; - if (cbPCBBAUpstreamWidth < temp) - temp = cbPCBBAUpstreamWidth; - pDat->PortList[i].SelWidthIn = (u8)temp; - pDat->PortList[i+1].SelWidthOut = (u8)temp; - } -} - -/*---------------------------------------------------------------------------------------- - * void - * hammerSublinkFixup(sMainData *pDat) - * - * Description: - * Iterate through all links, checking the frequency of each sublink pair. Make the - * adjustment to the port list data so that the frequencies are at a valid ratio, - * reducing frequency as needed to achieve this. (All links support the minimum 200 MHz - * frequency.) Repeat the above until no adjustments are needed. - * Note no hardware state changes in this routine. - * - * Parameters: - * @param[in,out] sMainData* pDat = our global state, link state and port list - * --------------------------------------------------------------------------------------- - */ -static void hammerSublinkFixup(sMainData *pDat) -{ -#ifndef HT_BUILD_NC_ONLY - u8 i, j, k; - BOOL changes, downgrade; - - u8 hiIndex; - u8 hiFreq, loFreq; - - u32 temp; - - do - { - changes = FALSE; - for (i = 0; i < pDat->TotalLinks*2; i++) - { - if (pDat->PortList[i].Type != PORTLIST_TYPE_CPU) /* Must be a CPU link */ - continue; - if (pDat->PortList[i].Link < 4) /* Only look for sublink1's */ - continue; - - for (j = 0; j < pDat->TotalLinks*2; j++) - { - /* Step 1. Find the matching sublink0 */ - if (pDat->PortList[j].Type != PORTLIST_TYPE_CPU) - continue; - if (pDat->PortList[j].NodeID != pDat->PortList[i].NodeID) - continue; - if (pDat->PortList[j].Link != (pDat->PortList[i].Link & 0x03)) - continue; - - /* Step 2. Check for an illegal frequency ratio */ - if (pDat->PortList[i].SelFrequency >= pDat->PortList[j].SelFrequency) - { - hiIndex = i; - hiFreq = pDat->PortList[i].SelFrequency; - loFreq = pDat->PortList[j].SelFrequency; - } - else - { - hiIndex = j; - hiFreq = pDat->PortList[j].SelFrequency; - loFreq = pDat->PortList[i].SelFrequency; - } - - if (hiFreq == loFreq) - break; /* The frequencies are 1:1, no need to do anything */ - - downgrade = FALSE; - - if (hiFreq == 13) - { - if ((loFreq != 7) && /* {13, 7} 2400MHz / 1200MHz 2:1 */ - (loFreq != 4) && /* {13, 4} 2400MHz / 600MHz 4:1 */ - (loFreq != 2)) /* {13, 2} 2400MHz / 400MHz 6:1 */ - downgrade = TRUE; - } - else if (hiFreq == 11) - { - if ((loFreq != 6)) /* {11, 6} 2000MHz / 1000MHz 2:1 */ - downgrade = TRUE; - } - else if (hiFreq == 9) - { - if ((loFreq != 5) && /* { 9, 5} 1600MHz / 800MHz 2:1 */ - (loFreq != 2) && /* { 9, 2} 1600MHz / 400MHz 4:1 */ - (loFreq != 0)) /* { 9, 0} 1600MHz / 200MHz 8:1 */ - downgrade = TRUE; - } - else if (hiFreq == 7) - { - if ((loFreq != 4) && /* { 7, 4} 1200MHz / 600MHz 2:1 */ - (loFreq != 0)) /* { 7, 0} 1200MHz / 200MHz 6:1 */ - downgrade = TRUE; - } - else if (hiFreq == 5) - { - if ((loFreq != 2) && /* { 5, 2} 800MHz / 400MHz 2:1 */ - (loFreq != 0)) /* { 5, 0} 800MHz / 200MHz 4:1 */ - downgrade = TRUE; - } - else if (hiFreq == 2) - { - if ((loFreq != 0)) /* { 2, 0} 400MHz / 200MHz 2:1 */ - downgrade = TRUE; - } - else - { - downgrade = TRUE; /* no legal ratios for hiFreq */ - } - - /* Step 3. Downgrade the higher of the two frequencies, and set nochanges to FALSE */ - if (downgrade) - { - /* Although the problem was with the port specified by hiIndex, we need to */ - /* downgrade both ends of the link. */ - hiIndex = hiIndex & 0xFE; /* Select the 'upstream' (i.e. even) port */ - - temp = pDat->PortList[hiIndex].CompositeFrequencyCap; - - /* Remove hiFreq from the list of valid frequencies */ - temp = temp & ~((uint32)1 << hiFreq); - ASSERT (temp != 0); - pDat->PortList[hiIndex].CompositeFrequencyCap = temp; - pDat->PortList[hiIndex+1].CompositeFrequencyCap = temp; - - for (k = 19;; k--) - { - if ((j == 16) || (j == 15)) - continue; - if (temp & ((uint32_t)1 << k)) - break; - } - - pDat->PortList[hiIndex].SelFrequency = k; - pDat->PortList[hiIndex+1].SelFrequency = k; - - changes = TRUE; - } - } - } - } while (changes); /* Repeat until a valid configuration is reached */ -#endif /* HT_BUILD_NC_ONLY */ -} - -/*---------------------------------------------------------------------------------------- - * void - * linkOptimization(sMainData *pDat) - * - * Description: - * Based on link capabilities, apply optimization rules to come up with the real best - * settings, including several external limit decision from call backs. This includes - * handling of sublinks. Finally, after the port list data is updated, set the hardware - * state for all links. - * - * Parameters: - * @param[in] sMainData* pDat = our global state - * --------------------------------------------------------------------------------------- - */ -static void linkOptimization(sMainData *pDat) -{ - pDat->nb->gatherLinkData(pDat, pDat->nb); - regangLinks(pDat); - if (is_fam15h()) - detectIoLinkIsochronousCapable(pDat); - selectOptimalWidthAndFrequency(pDat); - hammerSublinkFixup(pDat); - pDat->nb->setLinkData(pDat, pDat->nb); -} - - -/*---------------------------------------------------------------------------------------- - * void - * trafficDistribution(sMainData *pDat) - * - * Description: - * In the case of a two node system with both sublinks used, enable the traffic - * distribution feature. - * - * Parameters: - * @param[in] sMainData* pDat = our global state, port list data - * --------------------------------------------------------------------------------------- - */ -static void trafficDistribution(sMainData *pDat) -{ -#ifndef HT_BUILD_NC_ONLY - u32 links01, links10; - u8 linkCount; - u8 i; - - /* Traffic Distribution is only used when there are exactly two nodes in the system */ - if (pDat->NodesDiscovered+1 != 2) - return; - - links01 = 0; - links10 = 0; - linkCount = 0; - for (i = 0; i < pDat->TotalLinks*2; i += 2) - { - if ((pDat->PortList[i].Type == PORTLIST_TYPE_CPU) && (pDat->PortList[i+1].Type == PORTLIST_TYPE_CPU)) - { - links01 |= (u32)1 << pDat->PortList[i].Link; - links10 |= (u32)1 << pDat->PortList[i+1].Link; - linkCount++; - } - } - ASSERT(linkCount != 0); - if (linkCount == 1) - return; /* Don't setup Traffic Distribution if only one link is being used */ - - pDat->nb->writeTrafficDistribution(links01, links10, pDat->nb); -#endif /* HT_BUILD_NC_ONLY */ -} - -/*---------------------------------------------------------------------------------------- - * void - * tuning(sMainData *pDat) - * - * Description: - * Handle system and performance tunings, such as traffic distribution, fifo and - * buffer tuning, and special config tunings. - * - * Parameters: - * @param[in] sMainData* pDat = our global state, port list data - * --------------------------------------------------------------------------------------- - */ -static void tuning(sMainData *pDat) -{ - u8 i; - - /* See if traffic distribution can be done and do it if so - * or allow system specific customization - */ - if ((pDat->HtBlock->AMD_CB_CustomizeTrafficDistribution == NULL) - || !pDat->HtBlock->AMD_CB_CustomizeTrafficDistribution()) - { - trafficDistribution(pDat); - } - - /* For each node, invoke northbridge specific buffer tunings or - * system specific customizations. - */ - for (i = 0; i < pDat->NodesDiscovered + 1; i++) - { - if ((pDat->HtBlock->AMD_CB_CustomizeBuffers == NULL) - || !pDat->HtBlock->AMD_CB_CustomizeBuffers(i)) - { - pDat->nb->bufferOptimizations(i, pDat, pDat->nb); - } - } -} - -/*---------------------------------------------------------------------------------------- - * BOOL - * isSanityCheckOk() - * - * Description: - * Perform any general sanity checks which should prevent HT from running if they fail. - * Currently only the "Must run on BSP only" check. - * - * Parameters: - * @param[out] result BOOL = true if check is ok, false if it failed - * --------------------------------------------------------------------------------------- - */ -static BOOL isSanityCheckOk(void) -{ - uint64 qValue; - - AmdMSRRead(LAPIC_BASE_MSR, &qValue); - - return ((qValue.lo & LAPIC_BASE_MSR_BOOTSTRAP_PROCESSOR) != 0); -} - -/*************************************************************************** - *** HT Initialize *** - ***************************************************************************/ - -/*---------------------------------------------------------------------------------------- - * void - * htInitialize(AMD_HTBLOCK *pBlock) - * - * Description: - * This is the top level external interface for Hypertransport Initialization. - * Create our initial internal state, initialize the coherent fabric, - * initialize the non-coherent chains, and perform any required fabric tuning or - * optimization. - * - * Parameters: - * @param[in] AMD_HTBLOCK* pBlock = Our Initial State including possible - * topologies and routings, non coherent bus - * assignment info, and actual - * wrapper or OEM call back routines. - * --------------------------------------------------------------------------------------- - */ -void amdHtInitialize(AMD_HTBLOCK *pBlock) -{ - sMainData pDat; - cNorthBridge nb; - - if (isSanityCheckOk()) - { - newNorthBridge(0, &nb); - - pDat.HtBlock = pBlock; - pDat.nb = &nb; - pDat.sysMpCap = nb.maxNodes; - nb.isCapable(0, &pDat, pDat.nb); - coherentInit(&pDat); - - pDat.AutoBusCurrent = pBlock->AutoBusStart; - pDat.UsedCfgMapEntires = 0; - ncInit(&pDat); - linkOptimization(&pDat); - tuning(&pDat); - } -} diff --git a/src/northbridge/amd/amdht/h3finit.h b/src/northbridge/amd/amdht/h3finit.h deleted file mode 100644 index 743ae97065..0000000000 --- a/src/northbridge/amd/amdht/h3finit.h +++ /dev/null @@ -1,620 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2015 Timothy Pearson , Raptor Engineering - * Copyright (C) 2007 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef H3FINIT_H -#define H3FINIT_H - -#include "comlib.h" - -/*---------------------------------------------------------------------------- - * Mixed (DEFINITIONS AND MACROS / TYPEDEFS, STRUCTURES, ENUMS) - * - *---------------------------------------------------------------------------- - */ - -/*----------------------------------------------------------------------------- - * DEFINITIONS AND MACROS - * - *----------------------------------------------------------------------------- - */ - -/* Width equates for call backs */ -#define HT_WIDTH_8_BITS 8 -#define HT_WIDTH_16_BITS 16 -#define HT_WIDTH_4_BITS 4 -#define HT_WIDTH_2_BITS 2 - -/* Frequency equates for call backs which take an actual frequency setting */ -#define HT_FREQUENCY_200M 0 -#define HT_FREQUENCY_400M 2 -#define HT_FREQUENCY_600M 4 -#define HT_FREQUENCY_800M 5 -#define HT_FREQUENCY_1000M 6 -#define HT_FREQUENCY_1200M 7 -#define HT_FREQUENCY_1400M 8 -#define HT_FREQUENCY_1600M 9 -#define HT_FREQUENCY_1800M 10 -#define HT_FREQUENCY_2000M 11 -#define HT_FREQUENCY_2200M 12 -#define HT_FREQUENCY_2400M 13 -#define HT_FREQUENCY_2600M 14 -#define HT_FREQUENCY_2800M 17 -#define HT_FREQUENCY_3000M 18 -#define HT_FREQUENCY_3200M 19 - -/* Frequency Limit equates for call backs which take a frequency supported mask. */ -#define HT_FREQUENCY_LIMIT_200M 1 -#define HT_FREQUENCY_LIMIT_400M 7 -#define HT_FREQUENCY_LIMIT_600M 0x1F -#define HT_FREQUENCY_LIMIT_800M 0x3F -#define HT_FREQUENCY_LIMIT_1000M 0x7F -#define HT_FREQUENCY_LIMIT_HT1_ONLY 0x7F -#define HT_FREQUENCY_LIMIT_1200M 0xFF -#define HT_FREQUENCY_LIMIT_1400M 0x1FF -#define HT_FREQUENCY_LIMIT_1600M 0x3FF -#define HT_FREQUENCY_LIMIT_1800M 0x7FF -#define HT_FREQUENCY_LIMIT_2000M 0xFFF -#define HT_FREQUENCY_LIMIT_2200M 0x1FFF -#define HT_FREQUENCY_LIMIT_2400M 0x3FFF -#define HT_FREQUENCY_LIMIT_2600M 0x7FFF -#define HT_FREQUENCY_LIMIT_2800M 0x3FFFF -#define HT_FREQUENCY_LIMIT_3000M 0x7FFFF -#define HT_FREQUENCY_LIMIT_3200M 0xFFFFF - -/* - * Event Notify definitions - */ - -/* Event Class definitions */ -#define HT_EVENT_CLASS_CRITICAL 1 -#define HT_EVENT_CLASS_ERROR 2 -#define HT_EVENT_CLASS_HW_FAULT 3 -#define HT_EVENT_CLASS_WARNING 4 -#define HT_EVENT_CLASS_INFO 5 - -/* Event definitions. */ - -/* Coherent subfunction events */ -#define HT_EVENT_COH_EVENTS 0x1000 -#define HT_EVENT_COH_NO_TOPOLOGY 0x1001 -#define HT_EVENT_COH_LINK_EXCEED 0x1002 -#define HT_EVENT_COH_FAMILY_FEUD 0x1003 -#define HT_EVENT_COH_NODE_DISCOVERED 0x1004 -#define HT_EVENT_COH_MPCAP_MISMATCH 0x1005 - -/* Non-coherent subfunction events */ -#define HT_EVENT_NCOH_EVENTS 0x2000 -#define HT_EVENT_NCOH_BUID_EXCEED 0x2001 -#define HT_EVENT_NCOH_LINK_EXCEED 0x2002 -#define HT_EVENT_NCOH_BUS_MAX_EXCEED 0x2003 -#define HT_EVENT_NCOH_CFG_MAP_EXCEED 0x2004 -#define HT_EVENT_NCOH_DEVICE_FAILED 0x2005 -#define HT_EVENT_NCOH_AUTO_DEPTH 0x2006 - -/* Optimization subfunction events */ -#define HT_EVENT_OPT_EVENTS 0x3000 -#define HT_EVENT_OPT_REQUIRED_CAP_RETRY 0x3001 -#define HT_EVENT_OPT_REQUIRED_CAP_GEN3 0x3002 - -/* HW Fault events */ -#define HT_EVENT_HW_EVENTS 0x4000 -#define HT_EVENT_HW_SYNCHFLOOD 0x4001 -#define HT_EVENT_HW_HTCRC 0x4002 - -/* The bbHT component (hb*) uses 0x5000 for events. - * For consistency, we avoid that range here. - */ - -/*---------------------------------------------------------------------------- - * TYPEDEFS, STRUCTURES, ENUMS - * - *---------------------------------------------------------------------------- - */ - -typedef struct { - u8 **topolist; - u8 AutoBusStart; - /* Note: This should always be the form AutoBusCurrent+N*AutoBusIncrement, also bus 253-255 are reserved */ - u8 AutoBusMax; - u8 AutoBusIncrement; - - /**---------------------------------------------------------------------------------------- - * - * BOOL - * AMD_CB_IgnoreLink(u8 Node, u8 Link) - * - * Description: - * This routine is called every time a coherent link is found and then every - * time a non-coherent link from a CPU is found. - * Any coherent or non-coherent link from a CPU can be ignored and not used - * for discovery or initialization. Useful for connection based systems. - * (Note: not called for IO device to IO Device links.) - * - * Parameters: - * @param[in] u8 node = The node on which this link is located - * @param[in] u8 link = The link about to be initialized - * @param[out] BOOL result = true to ignore this link and skip it - * false to initialize the link normally - * - * --------------------------------------------------------------------------------------- - */ - BOOL (*AMD_CB_IgnoreLink)(u8 Node, u8 Link); - - /**---------------------------------------------------------------------------------------- - * - * BOOL - * AMD_CB_OverrideBusNumbers(u8 Node, u8 Link, u8 *SecBus, u8 *SubBus) - * - * Description: - * This routine is called every time a non-coherent chain is processed. - * If a system can not use the auto Bus numbering feature for non-coherent chain bus - * assignments, this routine can provide explicit control. For each chain, provide - * the bus number range to use. - * - * Parameters: - * @param[in] u8 node = The node on which this chain is located - * @param[in] u8 link = The link on the host for this chain - * @param[out] u8 secBus = Secondary Bus number for this non-coherent chain - * @param[out] u8 *subBus = Subordinate Bus number - * @param[out] BOOL result = true this routine is supplying the bus numbers - * false use auto Bus numbering - * - * --------------------------------------------------------------------------------------- - */ - BOOL (*AMD_CB_OverrideBusNumbers)(u8 Node, u8 Link, u8 *SecBus, u8 *SubBus); - - /**---------------------------------------------------------------------------------------- - * - * BOOL - * AMD_CB_ManualBUIDSwapList(u8 Node, u8 Link, u8 **List) - * - * Description: - * This routine is called every time a non-coherent chain is processed. - * BUID assignment may be controlled explicitly on a non-coherent chain. Provide a - * swap list. The first part of the list controls the BUID assignment and the - * second part of the list provides the device to device linking. Device orientation - * can be detected automatically, or explicitly. See documentation for more details. - * - * Automatic non-coherent init assigns BUIDs starting at 1 and incrementing sequentially - * based on each device's unit count. - * - * Parameters: - * @param[in] u8 node = The node on which this chain is located - * @param[in] u8 link = The link on the host for this chain - * @param[out] u8 **list = supply a pointer to a list - * @param[out] BOOL result = true to use a manual list - * false to initialize the link automatically - * - * --------------------------------------------------------------------------------------- - */ - BOOL (*AMD_CB_ManualBUIDSwapList)(u8 Node, u8 Link, const u8 **List); - - /**---------------------------------------------------------------------------------------- - * - * void - * AMD_CB_DeviceCapOverride(u8 HostNode, u8 HostLink, u8 Depth, u8 Segment, - * u8 Bus, u8 Dev, u32 DevVenID, u8 Link, - * u8 *LinkWidthIn, u8 *LinkWidthOut, u16 *FreqCap) - * - * Description: - * This routine is called once for every link on every IO device. - * Update the width and frequency capability if needed for this device. - * This is used along with device capabilities, the limit call backs, and northbridge - * limits to compute the default settings. The components of the device's PCI config - * address are provided, so its settings can be consulted if need be. The input width - * and frequency are the reported device capabilities. - * - * Parameters: - * @param[in] u8 hostNode = The node on which this chain is located - * @param[in] u8 hostLink = The link on the host for this chain - * @param[in] u8 Depth = The depth in the I/O chain from the Host - * @param[in] u8 Segment = The Device's PCI Bus Segment number - * @param[in] u8 Bus = The Device's PCI Bus number - * @param[in] u8 Dev = The Device's PCI device Number - * @param[in] u32 DevVenID = The Device's PCI Vendor + Device ID (offset 0x00) - * @param[in] u8 Link = The Device's link number (0 or 1) - * @param[in,out] u8 *LinkWidthIn = modify to change the Link Witdh In - * @param[in,out] u8 *LinkWidthOut = modify to change the Link Witdh Out - * @param[in,out] u32 *FreqCap = modify to change the link's frequency capability - * @param[in,out] u32 *FeatureCap = modify to change the link's feature capability - * - * --------------------------------------------------------------------------------------- - */ - void (*AMD_CB_DeviceCapOverride)( - u8 HostNode, - u8 HostLink, - u8 Depth, - u8 Segment, - u8 Bus, - u8 Dev, - u32 DevVenID, - u8 Link, - u8 *LinkWidthIn, - u8 *LinkWidthOut, - u32 *FreqCap, - u32 *FeatureCap - ); - - /**---------------------------------------------------------------------------------------- - * - * void - * AMD_CB_Cpu2CpuPCBLimits(u8 NodeA, u8 LinkA, u8 NodeB, u8 LinkB, - * u8 *ABLinkWidthLimit, u8 *BALinkWidthLimit, u16 *PCBFreqCap) - * - * Description: - * For each coherent connection this routine is called once. - * Update the frequency and width if needed for this link (usually based on board - * restriction). This is used with CPU device capabilities and northbridge limits - * to compute the default settings. The input width and frequency are valid, but do - * not necessarily reflect the minimum setting that will be chosen. - * - * Parameters: - * @param[in] u8 nodeA = One node on which this link is located - * @param[in] u8 linkA = The link on this node - * @param[in] u8 nodeB = The other node on which this link is located - * @param[in] u8 linkB = The link on that node - * @param[in,out] u8 *ABLinkWidthLimit = modify to change the Link Witdh In - * @param[in,out] u8 *BALinkWidthLimit = modify to change the Link Witdh Out - * @param[in,out] u32 *PCBFreqCap = modify to change the link's frequency capability - * - * --------------------------------------------------------------------------------------- - */ - void (*AMD_CB_Cpu2CpuPCBLimits)( - u8 NodeA, - u8 LinkA, - u8 NodeB, - u8 LinkB, - u8 *ABLinkWidthLimit, - u8 *BALinkWidthLimit, - u32 *PCBFreqCap - ); - - /**---------------------------------------------------------------------------------------- - * - * void - * AMD_CB_IOPCBLimits(u8 HostNode, u8 HostLink, u8 Depth, u8 *DownstreamLinkWidthLimit, - * u8 *UpstreamLinkWidthLimit, u16 *PCBFreqCap) - * - * Description: - * For each non-coherent connection this routine is called once. - * Update the frequency and width if needed for this link (usually based on board - * restriction). This is used with device capabilities, device overrides, and northbridge limits - * to compute the default settings. The input width and frequency are valid, but do - * not necessarily reflect the minimum setting that will be chosen. - * - * Parameters: - * @param[in] u8 hostNode = The node on which this link is located - * @param[in] u8 hostLink = The link about to be initialized - * @param[in] u8 Depth = The depth in the I/O chain from the Host - * @param[in,out] u8 *DownstreamLinkWidthLimit = modify to change the Link Witdh In - * @param[in,out] u8 *UpstreamLinkWidthLimit = modify to change the Link Witdh Out - * @param[in,out] u32 *PCBFreqCap = modify to change the link's frequency capability - * - * --------------------------------------------------------------------------------------- - */ - void (*AMD_CB_IOPCBLimits)( - u8 HostNode, - u8 HostLink, - u8 Depth, - u8 *DownstreamLinkWidthLimit, - u8 *UpstreamLinkWidthLimit, - u32 *PCBFreqCap - ); - - /**---------------------------------------------------------------------------------------- - * - * BOOL - * AMD_CB_SkipRegang(u8 NodeA, u8 LinkA, u8 NodeB, u8 LinkB) - * - * Description: - * This routine is called whenever two sublinks are both connected to the same CPUs. - * Normally, unganged subsinks between the same two CPUs are reganged. - * Return true from this routine to leave the links unganged. - * - * Parameters: - * @param[in] u8 nodeA = One node on which this link is located - * @param[in] u8 linkA = The link on this node - * @param[in] u8 nodeB = The other node on which this link is located - * @param[in] u8 linkB = The link on that node - * @param[out] BOOL result = true to leave link unganged - * false to regang link automatically - * - * --------------------------------------------------------------------------------------- - */ - BOOL (*AMD_CB_SkipRegang)( - u8 NodeA, - u8 LinkA, - u8 NodeB, - u8 LinkB - ); - - /**---------------------------------------------------------------------------------------- - * - * BOOL - * AMD_CB_CustomizeTrafficDistribution() - * - * Description: - * Near the end of HT initialization, this routine is called once. - * If this routine will handle traffic distribution in a proprietary way, - * after detecting which links to distribute traffic on and configuring the system, - * return true. Return false to let the HT code detect and do traffic distribution - * This routine can also be used to simply turn this feature off, or to pre-process - * the system before normal traffic distribution. - * - * Parameters: - * @param[out] BOOL result = true skip traffic distribution - * false do normal traffic distribution - * - * --------------------------------------------------------------------------------------- - */ - BOOL (*AMD_CB_CustomizeTrafficDistribution)(void); - - - /**---------------------------------------------------------------------------------------- - * - * BOOL - * AMD_CB_CustomizeBuffers(u8 Node) - * - * Description: - * Near the end of HT initialization, this routine is called once per CPU node. - * Implement proprietary buffer tuning and return true, or return false for normal tuning. - * This routine can also be used to simply turn this feature off, or to pre-process - * the system before normal tuning. - * - * Parameters: - * @param[in] u8 node = buffer allocation may apply to this node - * @param[out] BOOL result = true skip buffer allocation on this node - * false tune buffers normally - * - * --------------------------------------------------------------------------------------- - */ - BOOL (*AMD_CB_CustomizeBuffers)(u8 node); - - /**---------------------------------------------------------------------------------------- - * - * void - * AMD_CB_OverrideDevicePort(u8 HostNode, u8 HostLink, u8 Depth, u8 *LinkWidthIn, - * u8 *LinkWidthOut, u16 *LinkFrequency) - * - * Description: - * Called once for each active link on each IO device. - * Provides an opportunity to directly control the frequency and width, - * intended for test and debug. The input frequency and width will be used - * if not overridden. - * - * Parameters: - * @param[in] u8 hostNode = The node on which this link is located - * @param[in] u8 hostLink = The link about to be initialized - * @param[in] u8 Depth = The depth in the I/O chain from the Host - * @param[in] u8 Link = the link on the device (0 or 1) - * @param[in,out] u8 *LinkWidthIn = modify to change the Link Witdh In - * @param[in,out] u8 *LinkWidthOut = modify to change the Link Witdh Out - * @param[in,out] u16 *LinkFrequency = modify to change the link's frequency capability - * - * --------------------------------------------------------------------------------------- - */ - void (*AMD_CB_OverrideDevicePort)( - u8 HostNode, - u8 HostLink, - u8 Depth, - u8 Link, - u8 *LinkWidthIn, - u8 *LinkWidthOut, - u8 *LinkFrequency - ); - - /**---------------------------------------------------------------------------------------- - * - * void - * AMD_CB_OverrideCpuPort(u8 Node, u8 Link, u8 *LinkWidthIn, u8 *LinkWidthOut, - * u16 *LinkFrequency) - * - * Description: - * Called once for each active link on each CPU. - * Provides an opportunity to directly control the frequency and width, - * intended for test and debug. The input frequency and width will be used - * if not overridden. - * - * Parameters: - * @param[in] u8 node = One node on which this link is located - * @param[in] u8 link = The link on this node - * @param[in,out] u8 *LinkWidthIn = modify to change the Link Witdh In - * @param[in,out] u8 *LinkWidthOut = modify to change the Link Witdh Out - * @param[in,out] u16 *LinkFrequency = modify to change the link's frequency capability - * - *--------------------------------------------------------------------------------------- - */ - void (*AMD_CB_OverrideCpuPort)( - u8 Node, - u8 Link, - u8 *LinkWidthIn, - u8 *LinkWidthOut, - u8 *LinkFrequency - ); - - /**---------------------------------------------------------------------------------------- - * - * void - * AMD_CB_EventNotify(u8 evtClass, u16 event, const u8 *pEventData0) - * - * Description: - * Errors, events, faults, warnings, and useful information are provided by - * calling this routine as often as necessary, once for each notification. - * See elsewhere in this file for class, event, and event data definitions. - * See the documentation for more details. - * - * Parameters: - * @param[in] u8 evtClass = What level event is this - * @param[in] u16 event = A unique ID of this event - * @param[in] u8 *pEventData0 = useful data associated with the event. - * - * --------------------------------------------------------------------------------------- - */ - void (*AMD_CB_EventNotify) ( - u8 evtClass, - u16 event, - const u8 *pEventData0 - ); - - const struct ht_link_config *ht_link_configuration; - -} AMD_HTBLOCK; - -/* - * Event Notification Structures - * These structures are passed to AMD_CB_EventNotify as *pEventData0. - */ - -/* For event HT_EVENT_HW_SYNCHFLOOD */ -typedef struct -{ - u8 eSize; - u8 node; - u8 link; -} sHtEventHWSynchFlood; - -/* For event HT_EVENT_HW_HTCRC */ -typedef struct -{ - u8 eSize; - u8 node; - u8 link; - u8 laneMask; -} sHtEventHWHtCrc; - -/* For event HT_EVENT_NCOH_BUS_MAX_EXCEED */ -typedef struct -{ - u8 eSize; - u8 node; - u8 link; - u8 bus; -} sHTEventNcohBusMaxExceed; - -/* For event HT_EVENT_NCOH_LINK_EXCEED */ -typedef struct -{ - u8 eSize; - u8 node; - u8 link; - u8 depth; - u8 maxLinks; -} sHtEventNcohLinkExceed; - -/* For event HT_EVENT_NCOH_CFG_MAP_EXCEED */ -typedef struct -{ - u8 eSize; - u8 node; - u8 link; -} sHtEventNcohCfgMapExceed; - -/* For event HT_EVENT_NCOH_BUID_EXCEED */ -typedef struct -{ - u8 eSize; - u8 node; - u8 link; - u8 depth; - u8 currentBUID; - u8 unitCount; -} sHtEventNcohBuidExceed; - -/* For event HT_EVENT_NCOH_DEVICE_FAILED */ -typedef struct -{ - u8 eSize; - u8 node; - u8 link; - u8 depth; - u8 attemptedBUID; -} sHtEventNcohDeviceFailed; - -/* For event HT_EVENT_NCOH_AUTO_DEPTH */ -typedef struct -{ - u8 eSize; - u8 node; - u8 link; - u8 depth; -} sHtEventNcohAutoDepth; - -/* For event HT_EVENT_OPT_REQUIRED_CAP_RETRY, - * HT_EVENT_OPT_REQUIRED_CAP_GEN3 - */ -typedef struct -{ - u8 eSize; - u8 node; - u8 link; - u8 depth; -} sHtEventOptRequiredCap; - -/* For event HT_EVENT_COH_NO_TOPOLOGY */ -typedef struct -{ - u8 eSize; - u8 totalNodes; -} sHtEventCohNoTopology; - -/* For event HT_EVENT_COH_LINK_EXCEED */ -typedef struct -{ - u8 eSize; - u8 node; - u8 link; - u8 targetNode; - u8 totalNodes; - u8 maxLinks; -} sHtEventCohLinkExceed; - -/* For event HT_EVENT_COH_FAMILY_FEUD */ -typedef struct -{ - u8 eSize; - u8 node; - u8 link; - u8 totalNodes; -} sHtEventCohFamilyFeud; - -/* For event HT_EVENT_COH_NODE_DISCOVERED */ -typedef struct -{ - u8 eSize; - u8 node; - u8 link; - u8 newNode; -} sHtEventCohNodeDiscovered; - -/* For event HT_EVENT_COH_MPCAP_MISMATCH */ -typedef struct -{ - u8 eSize; - u8 node; - u8 link; - u8 sysMpCap; - u8 totalNodes; -} sHtEventCohMpCapMismatch; - -/*---------------------------------------------------------------------------- - * FUNCTIONS PROTOTYPE - * - *---------------------------------------------------------------------------- - */ -void amdHtInitialize(AMD_HTBLOCK *pBlock); - - -#endif /* H3FINIT_H */ diff --git a/src/northbridge/amd/amdht/h3gtopo.h b/src/northbridge/amd/amdht/h3gtopo.h deleted file mode 100644 index e211d4c006..0000000000 --- a/src/northbridge/amd/amdht/h3gtopo.h +++ /dev/null @@ -1,355 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007 Advanced Micro Devices, Inc. - * - * This program is free software * you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation * version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY * without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef HTTOPO_H -#define HTTOPO_H - -#include - -/*---------------------------------------------------------------------------- - * Mixed (DEFINITIONS AND MACROS / TYPEDEFS, STRUCTURES, ENUMS) - * - *---------------------------------------------------------------------------- - */ - -/*----------------------------------------------------------------------------- - * DEFINITIONS AND MACROS - * - *----------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------- - * TYPEDEFS, STRUCTURES, ENUMS - * - *---------------------------------------------------------------------------- - */ - -/* - * 0 - */ -static u8 const amdHtTopologySingleNode[] = { - 0x01, - 0x00, 0xFF // Node 0 -}; - -/* - * 0---1 - */ -static u8 const amdHtTopologyDualNode[] = { - 0x02, - 0x02, 0xFF, 0x00, 0x11, // Node 0 - 0x00, 0x00, 0x01, 0xFF // Node 1 -}; - -/* - * 2 - * | - * | - * 0---1 - */ -static u8 const amdHtTopologyThreeLine[] = { - 0x03, - 0x06, 0xFF, 0x04, 0x11, 0x02, 0x22, // Node 0 - 0x00, 0x00, 0x01, 0xFF, 0x00, 0x00, // Node 1 - 0x00, 0x00, 0x00, 0x00, 0x01, 0xFF // Node 2 -}; - -/* - * 2 - * |\ - * | \ - * 0---1 - */ -static u8 const amdHtTopologyTriangle[] = { - 0x03, - 0x06, 0xFF, 0x00, 0x11, 0x00, 0x22, // Node 0 - 0x00, 0x00, 0x05, 0xFF, 0x00, 0x22, // Node 1 - 0x00, 0x00, 0x00, 0x11, 0x03, 0xFF // Node 2 -}; - -/* - * 2 3 - * |\ | - * | \| - * 0---1 - */ -static u8 const amdHtTopologyFourDegenerate[] = { - 0x04, - 0x06, 0xFF, 0x00, 0x11, 0x00, 0x22, 0x00, 0x11, // Node 0 - 0x08, 0x00, 0x0D, 0xFF, 0x08, 0x22, 0x05, 0x33, // Node 1 - 0x00, 0x00, 0x00, 0x11, 0x03, 0xFF, 0x00, 0x11, // Node 2 - 0x00, 0x11, 0x00, 0x11, 0x00, 0x11, 0x02, 0xFF // Node 3 -}; - -/* - * 2---3 - * |\ /| - * |/ \| - * 0---1 - */ -static u8 const amdHtTopologyFourFully[] = { - 0x04, - 0x0E, 0xFF, 0x00, 0x11, 0x00, 0x22, 0x00, 0x33, // Node 0 - 0x00, 0x00, 0x0D, 0xFF, 0x00, 0x22, 0x00, 0x33, // Node 1 - 0x00, 0x00, 0x00, 0x11, 0x0B, 0xFF, 0x00, 0x33, // Node 2 - 0x00, 0x00, 0x00, 0x11, 0x00, 0x22, 0x07, 0xFF // Node 3 -}; - - -/* - * 2---3 - * |\ | - * | \| - * 0---1 - */ -static u8 const amdHtTopologyFourKite[] = { - 0x04, - 0x06, 0xFF, 0x00, 0x11, 0x00, 0x22, 0x00, 0x11, // Node 0 - 0x08, 0x00, 0x0D, 0xFF, 0x00, 0x22, 0x00, 0x33, // Node 1 - 0x00, 0x00, 0x00, 0x11, 0x0B, 0xFF, 0x01, 0x33, // Node 2 - 0x00, 0x22, 0x00, 0x11, 0x00, 0x22, 0x06, 0xFF // Node 3 -}; - - -/* - * 2 3 - * | | - * | | - * 0---1 - */ -static u8 const amdHtTopologyFourLine[] = { - 0x04, - 0x06, 0xFF, 0x04, 0x11, 0x02, 0x22, 0x04, 0x11, // Node 0 - 0x08, 0x00, 0x09, 0xFF, 0x08, 0x00, 0x01, 0x33, // Node 1 - 0x00, 0x00, 0x00, 0x00, 0x01, 0xFF, 0x00, 0x00, // Node 2 - 0x00, 0x11, 0x00, 0x11, 0x00, 0x11, 0x02, 0xFF // Node 3 -}; - - -/* - * 2---3 - * | | - * | | - * 0---1 - */ -static u8 const amdHtTopologyFourSquare[] = { - 0x04, - 0x06, 0xFF, 0x00, 0x11, 0x02, 0x22, 0x00, 0x22, // Node 0 - 0x00, 0x00, 0x09, 0xFF, 0x00, 0x33, 0x01, 0x33, // Node 1 - 0x08, 0x00, 0x00, 0x00, 0x09, 0xFF, 0x00, 0x33, // Node 2 - 0x00, 0x11, 0x04, 0x11, 0x00, 0x22, 0x06, 0xFF, // Node 3 -}; - - -/* - * 2---3 - * |\ - * | \ - * 0 1 - */ -static u8 const amdHtTopologyFourStar[] = { - 0x04, - 0x04, 0xFF, 0x00, 0x22, 0x00, 0x22, 0x00, 0x22, // Node 0 - 0x00, 0x22, 0x04, 0xFF, 0x00, 0x22, 0x00, 0x22, // Node 1 - 0x0A, 0x00, 0x09, 0x11, 0x0B, 0xFF, 0x03, 0x33, // Node 2 - 0x00, 0x22, 0x00, 0x22, 0x00, 0x22, 0x04, 0xFF, // Node 3 -}; - - -static u8 const amdHtTopologyFiveFully[] = { - 0x05, - 0x1E, 0xFF, 0x00, 0x11, 0x00, 0x22, 0x00, 0x33, 0x00, 0x44, // Node 0 - 0x00, 0x00, 0x1D, 0xFF, 0x00, 0x22, 0x00, 0x33, 0x00, 0x44, // Node 1 - 0x00, 0x00, 0x00, 0x11, 0x1B, 0xFF, 0x00, 0x33, 0x00, 0x44, // Node 2 - 0x00, 0x00, 0x00, 0x11, 0x00, 0x22, 0x17, 0xFF, 0x00, 0x44, // Node 3 - 0x00, 0x00, 0x00, 0x11, 0x00, 0x22, 0x00, 0x33, 0x0F, 0xFF // Node 4 -}; - - -/* - * - * 4 - * |\ - * | \ - * 2 3 - * | | - * 0---1 - */ -static u8 const amdHtTopologyFiveTwistedLadder[] = { - 0x05, - 0x06, 0xFF, 0x04, 0x11, 0x02, 0x22, 0x00, 0x11, 0x00, 0x22, // Node0 - 0x08, 0x00, 0x09, 0xFF, 0x08, 0x00, 0x01, 0x33, 0x00, 0x30, // Node1 - 0x10, 0x00, 0x10, 0x00, 0x11, 0xFF, 0x00, 0x40, 0x01, 0x44, // Node2 - 0x00, 0x11, 0x00, 0x11, 0x00, 0x14, 0x12, 0xFF, 0x02, 0x44, // Node3 - 0x00, 0x22, 0x00, 0x23, 0x00, 0x22, 0x04, 0x33, 0x0C, 0xFF // Node4 -}; - - -static u8 const amdHtTopologySixFully[] = { - 0x06, - 0x3E, 0xFF, 0x00, 0x11, 0x00, 0x22, 0x00, 0x33, 0x00, 0x44, 0x00, 0x55, // Node 0 - 0x00, 0x00, 0x3D, 0xFF, 0x00, 0x22, 0x00, 0x33, 0x00, 0x44, 0x00, 0x55, // Node 1 - 0x00, 0x00, 0x00, 0x11, 0x3B, 0xFF, 0x00, 0x33, 0x00, 0x44, 0x00, 0x55, // Node 2 - 0x00, 0x00, 0x00, 0x11, 0x00, 0x22, 0x37, 0xFF, 0x00, 0x44, 0x00, 0x55, // Node 3 - 0x00, 0x00, 0x00, 0x11, 0x00, 0x22, 0x00, 0x33, 0x2F, 0xFF, 0x00, 0x55, // Node 4 - 0x00, 0x00, 0x00, 0x11, 0x00, 0x22, 0x00, 0x33, 0x00, 0x44, 0x1F, 0xFF // Node 5 -}; - -/* - * - * 4 5 - * |\ /| - * |/ \| - * 2 3 - * | | - * 0---1 - */ -static u8 const amdHtTopologySixTwistedLadder[] = { - 0x06, - 0x06, 0xFF, 0x04, 0x11, 0x02, 0x22, 0x00, 0x11, 0x02, 0x22, 0x00, 0x12, // Node0 - 0x08, 0x00, 0x09, 0xFF, 0x00, 0x00, 0x01, 0x33, 0x00, 0x03, 0x01, 0x33, // Node1 - 0x30, 0x00, 0x00, 0x00, 0x31, 0xFF, 0x00, 0x54, 0x21, 0x44, 0x00, 0x55, // Node2 - 0x00, 0x11, 0x30, 0x11, 0x00, 0x45, 0x32, 0xFF, 0x00, 0x44, 0x12, 0x55, // Node3 - 0x00, 0x22, 0x00, 0x32, 0x08, 0x22, 0x00, 0x33, 0x0C, 0xFF, 0x00, 0x32, // Node4 - 0x00, 0x23, 0x00, 0x33, 0x00, 0x22, 0x04, 0x33, 0x00, 0x23, 0x0C, 0xFF // Node5 -}; - - -static u8 const amdHtTopologySevenFully[] = { - 0x07, - 0x7E, 0xFF, 0x00, 0x11, 0x00, 0x22, 0x00, 0x33, 0x00, 0x44, 0x00, 0x55, 0x00, 0x66, // Node 0 - 0x00, 0x00, 0x7D, 0xFF, 0x00, 0x22, 0x00, 0x33, 0x00, 0x44, 0x00, 0x55, 0x00, 0x66, // Node 1 - 0x00, 0x00, 0x00, 0x11, 0x7B, 0xFF, 0x00, 0x33, 0x00, 0x44, 0x00, 0x55, 0x00, 0x66, // Node 2 - 0x00, 0x00, 0x00, 0x11, 0x00, 0x22, 0x77, 0xFF, 0x00, 0x44, 0x00, 0x55, 0x00, 0x66, // Node 3 - 0x00, 0x00, 0x00, 0x11, 0x00, 0x22, 0x00, 0x33, 0x6F, 0xFF, 0x00, 0x55, 0x00, 0x66, // Node 4 - 0x00, 0x00, 0x00, 0x11, 0x00, 0x22, 0x00, 0x33, 0x00, 0x44, 0x5F, 0xFF, 0x00, 0x66, // Node 5 - 0x00, 0x00, 0x00, 0x11, 0x00, 0x22, 0x00, 0x33, 0x00, 0x44, 0x00, 0x55, 0x3F, 0xFF, // Node 6 -}; - - -/* 6 - * | - * 4 5 - * |\ /| - * |/ \| - * 2 3 - * | | - * 0---1 - */ -static u8 const amdHtTopologySevenTwistedLadder[] = { - 0x07, - 0x06, 0xFF, 0x00, 0x11, 0x02, 0x22, 0x00, 0x12, 0x00, 0x22, 0x00, 0x22, 0x00, 0x22, // Node0 - 0x00, 0x00, 0x09, 0xFF, 0x00, 0x03, 0x01, 0x33, 0x00, 0x33, 0x00, 0x33, 0x00, 0x33, // Node1 - 0x30, 0x00, 0x00, 0x50, 0x31, 0xFF, 0x00, 0x54, 0x21, 0x44, 0x01, 0x55, 0x21, 0x44, // Node2 - 0x00, 0x41, 0x30, 0x11, 0x00, 0x45, 0x32, 0xFF, 0x02, 0x44, 0x12, 0x55, 0x02, 0x44, // Node3 - 0x48, 0x22, 0x40, 0x33, 0x48, 0x22, 0x40, 0x33, 0x4C, 0xFF, 0x40, 0x32, 0x0C, 0x66, // Node4 - 0x00, 0x22, 0x04, 0x33, 0x00, 0x22, 0x04, 0x33, 0x00, 0x23, 0x0C, 0xFF, 0x00, 0x23, // Node5 - 0x00, 0x44, 0x00, 0x44, 0x00, 0x44, 0x00, 0x44, 0x00, 0x44, 0x00, 0x44, 0x10, 0xFF // Node6 -}; - - -/* - * 5--4 - * /####\ - * 6######3 - * |######| - * 7######2 - * \####/ - * 0--1 - */ -static u8 const amdHtTopologyEightFully [] = { - 0x08, - 0xFE, 0xFF, 0x00, 0x11, 0x00, 0x22, 0x00, 0x33, 0x00, 0x44, 0x00, 0x55, 0x00, 0x66, 0x00, 0x77, // Node 0 - 0x00, 0x00, 0xFD, 0xFF, 0x00, 0x22, 0x00, 0x33, 0x00, 0x44, 0x00, 0x55, 0x00, 0x66, 0x00, 0x77, // Node 1 - 0x00, 0x00, 0x00, 0x11, 0xFB, 0xFF, 0x00, 0x33, 0x00, 0x44, 0x00, 0x55, 0x00, 0x66, 0x00, 0x77, // Node 2 - 0x00, 0x00, 0x00, 0x11, 0x00, 0x22, 0xF7, 0xFF, 0x00, 0x44, 0x00, 0x55, 0x00, 0x66, 0x00, 0x77, // Node 3 - 0x00, 0x00, 0x00, 0x11, 0x00, 0x22, 0x00, 0x33, 0xEF, 0xFF, 0x00, 0x55, 0x00, 0x66, 0x00, 0x77, // Node 4 - 0x00, 0x00, 0x00, 0x11, 0x00, 0x22, 0x00, 0x33, 0x00, 0x44, 0xDF, 0xFF, 0x00, 0x66, 0x00, 0x77, // Node 5 - 0x00, 0x00, 0x00, 0x11, 0x00, 0x22, 0x00, 0x33, 0x00, 0x44, 0x00, 0x55, 0xBF, 0xFF, 0x00, 0x77, // Node 6 - 0x00, 0x00, 0x00, 0x11, 0x00, 0x22, 0x00, 0x33, 0x00, 0x44, 0x00, 0x55, 0x00, 0x66, 0x7F, 0xFF // Node 7 -}; - - -/* 6---7 - * | | - * 4---5 - * | | - * 2---3 - * | | - * 0---1 - */ -static u8 const amdHtTopologyEightStraightLadder[] = { - 0x08, - 0x06, 0xFF, 0x00, 0x11, 0x02, 0x22, 0x00, 0x22, 0x02, 0x22, 0x00, 0x22, 0x02, 0x22, 0x00, 0x22, // Node0 - 0x00, 0x00, 0x09, 0xFF, 0x00, 0x33, 0x01, 0x33, 0x00, 0x33, 0x01, 0x33, 0x00, 0x33, 0x01, 0x33, // Node1 - 0x18, 0x00, 0x00, 0x00, 0x19, 0xFF, 0x00, 0x33, 0x09, 0x44, 0x00, 0x44, 0x09, 0x44, 0x00, 0x44, // Node2 - 0x00, 0x11, 0x24, 0x11, 0x00, 0x22, 0x26, 0xFF, 0x00, 0x55, 0x06, 0x55, 0x00, 0x55, 0x06, 0x55, // Node3 - 0x60, 0x22, 0x00, 0x22, 0x60, 0x22, 0x00, 0x22, 0x64, 0xFF, 0x00, 0x55, 0x24, 0x66, 0x00, 0x66, // Node4 - 0x00, 0x33, 0x90, 0x33, 0x00, 0x33, 0x90, 0x33, 0x00, 0x44, 0x98, 0xFF, 0x00, 0x77, 0x18, 0x77, // Node5 - 0x80, 0x44, 0x00, 0x44, 0x80, 0x44, 0x00, 0x44, 0x80, 0x44, 0x00, 0x44, 0x90, 0xFF, 0x00, 0x77, // Node6 - 0x00, 0x55, 0x40, 0x55, 0x00, 0x55, 0x40, 0x55, 0x00, 0x55, 0x40, 0x55, 0x00, 0x66, 0x60, 0xFF // Node7 -}; - - -/* 6---7 - * | | - * 4 5 - * |\ /| - * |/ \| - * 2 3 - * | | - * 0---1 - */ -static u8 const amdHtTopologyEightTwistedLadder[] = { - 0x08, - 0x06, 0xFF, 0x00, 0x11, 0x02, 0x22, 0x00, 0x12, 0x00, 0x22, 0x00, 0x22, 0x00, 0x22, 0x00, 0x22, // Node0 - 0x00, 0x00, 0x09, 0xFF, 0x00, 0x03, 0x01, 0x33, 0x00, 0x33, 0x00, 0x33, 0x00, 0x33, 0x00, 0x33, // Node1 - 0x30, 0x00, 0x00, 0x50, 0x31, 0xFF, 0x00, 0x54, 0x21, 0x44, 0x01, 0x55, 0x21, 0x44, 0x01, 0x55, // Node2 - 0x00, 0x41, 0x30, 0x11, 0x00, 0x45, 0x32, 0xFF, 0x02, 0x44, 0x12, 0x55, 0x02, 0x44, 0x12, 0x55, // Node3 - 0x48, 0x22, 0x40, 0x33, 0x48, 0x22, 0x40, 0x33, 0x4C, 0xFF, 0x00, 0x32, 0x0C, 0x66, 0x00, 0x36, // Node4 - 0x80, 0x22, 0x84, 0x33, 0x80, 0x22, 0x84, 0x33, 0x00, 0x23, 0x8C, 0xFF, 0x00, 0x27, 0x0C, 0x77, // Node5 - 0x00, 0x44, 0x00, 0x44, 0x00, 0x44, 0x00, 0x44, 0x80, 0x44, 0x00, 0x74, 0x90, 0xFF, 0x00, 0x77, // Node6 - 0x00, 0x55, 0x00, 0x55, 0x00, 0x55, 0x00, 0x55, 0x00, 0x65, 0x40, 0x55, 0x00, 0x66, 0x60, 0xFF // Node7 -}; - -static const u8 *const amd_topo_list[] = { - amdHtTopologySingleNode, - amdHtTopologyDualNode, - amdHtTopologyThreeLine, - amdHtTopologyTriangle, - amdHtTopologyFourLine, - amdHtTopologyFourStar, - amdHtTopologyFourDegenerate, - amdHtTopologyFourSquare, - amdHtTopologyFourKite, - amdHtTopologyFourFully, - amdHtTopologyFiveFully, - amdHtTopologySixFully, - amdHtTopologySevenFully, - amdHtTopologyEightFully, - amdHtTopologyEightTwistedLadder, - amdHtTopologyEightStraightLadder, - NULL // NULL to mark end of list -}; - -/*---------------------------------------------------------------------------- - * FUNCTIONS PROTOTYPE - * - *---------------------------------------------------------------------------- - */ -void getAmdTopolist(u8 ***p); - - -#endif /* HTTOPO_H */ diff --git a/src/northbridge/amd/amdht/h3ncmn.c b/src/northbridge/amd/amdht/h3ncmn.c deleted file mode 100644 index 830e9888c9..0000000000 --- a/src/northbridge/amd/amdht/h3ncmn.c +++ /dev/null @@ -1,2549 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007 Advanced Micro Devices, Inc. - * Copyright (C) 2015 Timothy Pearson , Raptor Engineering - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - - -/*---------------------------------------------------------------------------- - * MODULES USED - * - *---------------------------------------------------------------------------- - */ - -#include "h3ncmn.h" -#include "h3finit.h" -#include "h3ffeat.h" -#include "AsPsNb.h" - -#include -#include -#include -#include -#include -#include - -/*---------------------------------------------------------------------------- - * DEFINITIONS AND MACROS - * - *---------------------------------------------------------------------------- - */ - -/* CPU Northbridge Functions */ -#define CPU_HTNB_FUNC_00 0 -#define CPU_HTNB_FUNC_04 4 -#define CPU_ADDR_FUNC_01 1 -#define CPU_NB_FUNC_03 3 -#define CPU_NB_FUNC_05 5 - -/* Function 0 registers */ -#define REG_ROUTE0_0X40 0x40 -#define REG_ROUTE1_0X44 0x44 -#define REG_NODE_ID_0X60 0x60 -#define REG_UNIT_ID_0X64 0x64 -#define REG_LINK_TRANS_CONTROL_0X68 0x68 -#define REG_LINK_INIT_CONTROL_0X6C 0x6c -#define REG_HT_CAP_BASE_0X80 0x80 -#define REG_NORTHBRIDGE_CFG_3X8C 0x8c -#define REG_HT_LINK_RETRY0_0X130 0x130 -#define REG_HT_TRAFFIC_DIST_0X164 0x164 -#define REG_HT_LINK_EXT_CONTROL0_0X170 0x170 - -#define HT_CONTROL_CLEAR_CRC (~(3 << 8)) - -/* Function 1 registers */ -#define REG_ADDR_CONFIG_MAP0_1XE0 0xE0 -#define CPU_ADDR_NUM_CONFIG_MAPS 4 - -/* Function 3 registers */ -#define REG_NB_SRI_XBAR_BUF_3X70 0x70 -#define REG_NB_MCT_XBAR_BUF_3X78 0x78 -#define REG_NB_FIFOPTR_3XDC 0xDC -#define REG_NB_CAPABILITY_3XE8 0xE8 -#define REG_NB_CPUID_3XFC 0xFC -#define REG_NB_LINK_XCS_TOKEN0_3X148 0x148 -#define REG_NB_DOWNCORE_3X190 0x190 -#define REG_NB_CAPABILITY_5X84 0x84 - -/* Function 4 registers */ - - -/*---------------------------------------------------------------------------- - * TYPEDEFS AND STRUCTURES - * - *---------------------------------------------------------------------------- - */ -/*---------------------------------------------------------------------------- - * PROTOTYPES OF LOCAL FUNCTIONS - * - *---------------------------------------------------------------------------- - */ - -/*************************************************************************** - *** FAMILY/NORTHBRIDGE SPECIFIC FUNCTIONS *** - ***************************************************************************/ - -inline uint8_t is_gt_rev_d(void) -{ - uint8_t fam15h = 0; - uint8_t rev_gte_d = 0; - uint32_t family; - uint32_t model; - - family = model = cpuid_eax(0x80000001); - model = ((model & 0xf0000) >> 12) | ((model & 0xf0) >> 4); - family = ((family & 0xf00000) >> 16) | ((family & 0xf00) >> 8); - - if (family >= 0x6f) - /* Family 15h or later */ - fam15h = 1; - - if ((model >= 0x8) || fam15h) - /* Revision D or later */ - rev_gte_d = 1; - - return rev_gte_d; -} - -/***************************************************************************//** - * - * SBDFO - * makeLinkBase(u8 currentNode, u8 currentLink) - * - * Description: - * Private to northbridge implementation. Return the HT Host capability base - * PCI config address for a link. - * - * Parameters: - * @param[in] node = the node this link is on - * @param[in] link = the link - * - *****************************************************************************/ -static SBDFO makeLinkBase(u8 node, u8 link) -{ - SBDFO linkBase; - - /* With rev F can not be called with a 4th link or with the sublinks */ - if (link < 4) - linkBase = MAKE_SBDFO(makePCISegmentFromNode(node), - makePCIBusFromNode(node), - makePCIDeviceFromNode(node), - CPU_HTNB_FUNC_00, - REG_HT_CAP_BASE_0X80 + link*HT_HOST_CAP_SIZE); - else - linkBase = MAKE_SBDFO(makePCISegmentFromNode(node), - makePCIBusFromNode(node), - makePCIDeviceFromNode(node), - CPU_HTNB_FUNC_04, - REG_HT_CAP_BASE_0X80 + (link-4)*HT_HOST_CAP_SIZE); - return linkBase; -} - -/***************************************************************************//** - * - * void - * setHtControlRegisterBits(SBDFO reg, u8 hiBit, u8 loBit, u32 *pValue) - * - * Description: - * Private to northbridge implementation. Provide a common routine for accessing the - * HT Link Control registers (84, a4, c4, e4), to enforce not clearing the - * HT CRC error bits. Replaces direct use of AmdPCIWriteBits(). - * NOTE: This routine is called for IO Devices as well as CPUs! - * - * Parameters: - * @param[in] reg = the PCI config address the control register - * @param[in] hiBit = the high bit number - * @param[in] loBit = the low bit number - * @param[in] pValue = the value to write to that bit range. Bit 0 => loBit. - * - *****************************************************************************/ -static void setHtControlRegisterBits(SBDFO reg, u8 hiBit, u8 loBit, u32 *pValue) -{ - u32 temp, mask; - - ASSERT((hiBit < 32) && (loBit < 32) && (hiBit >= loBit) && ((reg & 0x3) == 0)); - ASSERT((hiBit < 8) || (loBit > 9)); - - /* A 1<<32 == 1<<0 due to x86 SHL instruction, so skip if that is the case */ - if ((hiBit-loBit) != 31) - mask = (((u32)1 << (hiBit-loBit+1))-1); - else - mask = (u32)0xFFFFFFFF; - - AmdPCIRead(reg, &temp); - temp &= ~(mask << loBit); - temp |= (*pValue & mask) << loBit; - temp &= (u32)HT_CONTROL_CLEAR_CRC; - AmdPCIWrite(reg, &temp); -} - -/***************************************************************************//** - * - * static void - * writeRoutingTable(u8 node, u8 target, u8 Link, cNorthBridge *nb) - * - * Description: - * This routine will modify the routing tables on the - * SourceNode to cause it to route both request and response traffic to the - * targetNode through the specified Link. - * - * NOTE: This routine is to be used for early discovery and initialization. The - * final routing tables must be loaded some other way because this - * routine does not address the issue of probes, or independent request - * response paths. - * - * Parameters: - * @param[in] node = the node that will have it's routing tables modified. - * @param[in] target = For routing to node target - * @param[in] link = Link from node to target - * @param[in] *nb = this northbridge - * - *****************************************************************************/ - -static void writeRoutingTable(u8 node, u8 target, u8 link, cNorthBridge *nb) -{ -#ifndef HT_BUILD_NC_ONLY - u32 temp = (nb->selfRouteResponseMask | nb->selfRouteRequestMask) << (link + 1); - ASSERT((node < nb->maxNodes) && (target < nb->maxNodes) && (link < nb->maxLinks)); - AmdPCIWrite(MAKE_SBDFO(makePCISegmentFromNode(node), - makePCIBusFromNode(node), - makePCIDeviceFromNode(node), - CPU_HTNB_FUNC_00, - REG_ROUTE0_0X40 + target*4), - &temp); -#else - STOP_HERE; -#endif -} - -/***************************************************************************//** - * - * static void - * writeNodeID(u8 node, u8 nodeID, cNorthBridge *nb) - * - * Description: - * Modifies the NodeID register on the target node - * - * Parameters: - * @param[in] node = the node that will have its NodeID altered. - * @param[in] nodeID = the new value for NodeID - * @param[in] *nb = this northbridge - * - *****************************************************************************/ - -static void writeNodeID(u8 node, u8 nodeID, cNorthBridge *nb) -{ - u32 temp; - ASSERT((node < nb->maxNodes) && (nodeID < nb->maxNodes)); - if (is_fam15h()) { - temp = 1; - AmdPCIWriteBits(MAKE_SBDFO(makePCISegmentFromNode(node), - makePCIBusFromNode(node), - makePCIDeviceFromNode(node), - CPU_NB_FUNC_03, - REG_NORTHBRIDGE_CFG_3X8C), - 22, 22, &temp); - } - temp = nodeID; - AmdPCIWriteBits(MAKE_SBDFO(makePCISegmentFromNode(node), - makePCIBusFromNode(node), - makePCIDeviceFromNode(node), - CPU_HTNB_FUNC_00, - REG_NODE_ID_0X60), - 2, 0, &temp); -} - -/***************************************************************************//** - * - * static void - * readDefLnk(u8 node, cNorthBridge *nb) - * - * Description: - * Read the DefLnk (the source link of the current packet) - * from node - * - * Parameters: - * @param[in] node = the node that will have its NodeID altered. - * @param[in] *nb = this northbridge - * @return The HyperTransport link where the request to - * read the default link came from. Since this - * code is running on the BSP, this should be the link - * pointing back towards the BSP. - * - *****************************************************************************/ - -static u8 readDefLnk(u8 node, cNorthBridge *nb) -{ - u32 deflink = 0; - SBDFO licr; - u32 temp; - - licr = MAKE_SBDFO(makePCISegmentFromNode(node), - makePCIBusFromNode(node), - makePCIDeviceFromNode(node), - CPU_HTNB_FUNC_00, - REG_LINK_INIT_CONTROL_0X6C); - - ASSERT((node < nb->maxNodes)); - AmdPCIReadBits(licr, 3, 2, &deflink); - AmdPCIReadBits(licr, 8, 8, &temp); /* on rev F, this bit is reserved == 0 */ - deflink |= temp << 2; - return (u8)deflink; -} - -/***************************************************************************//** - * - * static void - * enableRoutingTables(u8 node, cNorthBridge *nb) - * - * Description: - * Turns routing tables on for a given node - * - * Parameters: - * @param[in] node = the node that will have it's routing tables enabled - * @param[in] *nb = this northbridge - * - *****************************************************************************/ - -static void enableRoutingTables(u8 node, cNorthBridge *nb) -{ - u32 temp = 0; - ASSERT((node < nb->maxNodes)); - AmdPCIWriteBits(MAKE_SBDFO(makePCISegmentFromNode(node), - makePCIBusFromNode(node), - makePCIDeviceFromNode(node), - CPU_HTNB_FUNC_00, - REG_LINK_INIT_CONTROL_0X6C), - 0, 0, &temp); -} - - -/***************************************************************************//** - * - * static BOOL - * verifyLinkIsCoherent(u8 node, u8 Link, cNorthBridge *nbk) - * - * Description: - * Verify that the link is coherent, connected, and ready - * - * Parameters: - * @param[in] node = the node that will be examined - * @param[in] link = the link on that Node to examine - * @param[in] *nb = this northbridge - * @return true - The link has the following status - * linkCon = 1, Link is connected - * InitComplete = 1, Link initialization is complete - * NC = 0, Link is coherent - * UniP-cLDT = 0, Link is not Uniprocessor cLDT - * LinkConPend = 0 Link connection is not pending - * false- The link has some other status - * - *****************************************************************************/ - -static BOOL verifyLinkIsCoherent(u8 node, u8 link, cNorthBridge *nb) -{ -#ifndef HT_BUILD_NC_ONLY - - u32 linkType; - SBDFO linkBase; - - ASSERT((node < nb->maxNodes) && (link < nb->maxLinks)); - - linkBase = makeLinkBase(node, link); - - /* FN0_98/A4/C4 = LDT Type Register */ - AmdPCIRead(linkBase + HTHOST_LINK_TYPE_REG, &linkType); - - /* Verify LinkCon = 1, InitComplete = 1, NC = 0, UniP-cLDT = 0, LinkConPend = 0 */ - return (linkType & HTHOST_TYPE_MASK) == HTHOST_TYPE_COHERENT; -#else - return 0; -#endif /* HT_BUILD_NC_ONLY */ -} - -/***************************************************************************//** - * - * static bool - * readTrueLinkFailStatus(u8 node, u8 link, sMainData *pDat, cNorthBridge *nb) - * - * Description: - * Return the LinkFailed status AFTER an attempt is made to clear the bit. - * Also, call event notify if a Hardware Fault caused a synch flood on a previous boot. - * - * The table below summarizes correct responses of this routine. - * Family before after unconnected Notify? return - * 0F 0 0 0 No 0 - * 0F 1 0 0 Yes 0 - * 0F 1 1 X No 1 - * 10 0 0 0 No 0 - * 10 1 0 0 Yes 0 - * 10 1 0 3 No 1 - * - * Parameters: - * @param[in] node = the node that will be examined - * @param[in] link = the link on that node to examine - * @param[in] *pDat = access to call back routine - * @param[in] *nb = this northbridge - * @return true - the link is not connected or has hard error - * false- if the link is connected - * - *****************************************************************************/ - -static BOOL readTrueLinkFailStatus(u8 node, u8 link, sMainData *pDat, cNorthBridge *nb) -{ - u32 before, after, unconnected, crc; - SBDFO linkBase; - - ASSERT((node < nb->maxNodes) && (link < nb->maxLinks)); - - linkBase = makeLinkBase(node, link); - - /* Save the CRC status before doing anything else. - * Read, Clear, the Re-read the error bits in the Link Control Register - * FN0_84/A4/C4[4] = LinkFail bit - * and the connection status, TransOff and EndOfChain - */ - AmdPCIReadBits(linkBase + HTHOST_LINK_CONTROL_REG, 9, 8, &crc); - AmdPCIReadBits(linkBase + HTHOST_LINK_CONTROL_REG, 4, 4, &before); - setHtControlRegisterBits(linkBase + HTHOST_LINK_CONTROL_REG, 4, 4, &before); - AmdPCIReadBits(linkBase + HTHOST_LINK_CONTROL_REG, 4, 4, &after); - AmdPCIReadBits(linkBase + HTHOST_LINK_CONTROL_REG, 7, 6, &unconnected); - - if (before != after) - { - if (!unconnected) - { - if (crc != 0) - { - /* A synch flood occurred due to HT CRC */ - if (pDat->HtBlock->AMD_CB_EventNotify) - { - /* Pass the node and link on which the generic synch flood event occurred. */ - sHtEventHWHtCrc evt; - evt.eSize = sizeof(sHtEventHWHtCrc); - evt.node = node; - evt.link = link; - evt.laneMask = (uint8)crc; - - pDat->HtBlock->AMD_CB_EventNotify(HT_EVENT_CLASS_HW_FAULT, - HT_EVENT_HW_HTCRC, - (u8 *)&evt); - } - } - else - { - /* Some synch flood occurred */ - if (pDat->HtBlock->AMD_CB_EventNotify) - { - /* Pass the node and link on which the generic synch flood event occurred. */ - sHtEventHWSynchFlood evt; - evt.eSize = sizeof(sHtEventHWSynchFlood); - evt.node = node; - evt.link = link; - - pDat->HtBlock->AMD_CB_EventNotify(HT_EVENT_CLASS_HW_FAULT, - HT_EVENT_HW_SYNCHFLOOD, - (u8 *)&evt); - } - } - } - } - return ((after != 0) || unconnected); -} - - -/***************************************************************************//** - * - * static u8 - * readToken(u8 node, cNorthBridge *nb) - * - * Description: - * Read the token stored in the scratchpad register - * NOTE: The location used to store the token is arbitrary. The only - * requirement is that the location warm resets to zero, and that - * using it will have no ill-effects during HyperTransport initialization. - * - * Parameters: - * @param[in] node = the node that will be examined - * @param[in] *nb = this northbridge - * @return the Token read from the node - * - *****************************************************************************/ -static u8 readToken(u8 node, cNorthBridge *nb) -{ - u32 temp; - - ASSERT((node < nb->maxNodes)); - /* Use CpuCnt as a scratch register */ - /* Limiting use to 4 bits makes code GH to rev F compatible. */ - AmdPCIReadBits(MAKE_SBDFO(makePCISegmentFromNode(node), - makePCIBusFromNode(node), - makePCIDeviceFromNode(node), - CPU_HTNB_FUNC_00, - REG_NODE_ID_0X60), - 19, 16, &temp); - - return (u8)temp; -} - - -/***************************************************************************//** - * - * static void - * writeToken(u8 node, u8 Value, cNorthBridge *nb) - * - * Description: - * Write the token stored in the scratchpad register - * NOTE: The location used to store the token is arbitrary. The only - * requirement is that the location warm resets to zero, and that - * using it will have no ill-effects during HyperTransport initialization. - * Limiting use to 4 bits makes code GH to rev F compatible. - * - * Parameters: - * @param[in] node = the node that will be examined - * @param value - * @param[in] *nb = this northbridge - * - *****************************************************************************/ -static void writeToken(u8 node, u8 value, cNorthBridge *nb) -{ - u32 temp = value; - ASSERT((node < nb->maxNodes)); - /* Use CpuCnt as a scratch register */ - /* Limiting use to 4 bits makes code GH to rev F compatible. */ - AmdPCIWriteBits(MAKE_SBDFO(makePCISegmentFromNode(node), - makePCIBusFromNode(node), - makePCIDeviceFromNode(node), - CPU_HTNB_FUNC_00, - REG_NODE_ID_0X60), - 19, 16, &temp); -} - -/***************************************************************************//** - * - * static u8 - * fam0FGetNumCoresOnNode(u8 node, cNorthBridge *nb) - * - * Description: - * Return the number of cores (1 based count) on node. - * - * Parameters: - * @param[in] node = the node that will be examined - * @param[in] *nb = this northbridge - * @return = the number of cores - * - * --------------------------------------------------------------------------------------- - */ -static u8 fam0FGetNumCoresOnNode(u8 node, cNorthBridge *nb) -{ - u32 temp; - - ASSERT((node < nb->maxNodes)); - /* Read CmpCap */ - AmdPCIReadBits(MAKE_SBDFO(makePCISegmentFromNode(node), - makePCIBusFromNode(node), - makePCIDeviceFromNode(node), - CPU_NB_FUNC_03, - REG_NB_CAPABILITY_3XE8), - 13, 12, &temp); - - /* and add one */ - return (u8)(temp+1); -} - -/***************************************************************************//** - * - * static u8 - * fam10GetNumCoresOnNode(u8 node, cNorthBridge *nb) - * - * Description: - * Return the number of cores (1 based count) on node. - * - * Parameters: - * @param[in] node = the node that will be examined - * @param[in] *nb = this northbridge - * @return = the number of cores - * - * - */ -static u8 fam10GetNumCoresOnNode(u8 node, cNorthBridge *nb) -{ - u32 temp, leveling, cores; - u8 i; - - ASSERT((node < nb->maxNodes)); - /* Read CmpCap [2][1:0] */ - AmdPCIReadBits(MAKE_SBDFO(makePCISegmentFromNode(node), - makePCIBusFromNode(node), - makePCIDeviceFromNode(node), - CPU_NB_FUNC_03, - REG_NB_CAPABILITY_3XE8), - 15, 12, &temp); - - /* bits[15,13,12] specify the cores */ - temp = ((temp & 8) >> 1) + (temp & 3); - cores = temp + 1; - - /* Support Downcoring */ - AmdPCIReadBits (MAKE_SBDFO(makePCISegmentFromNode(node), - makePCIBusFromNode(node), - makePCIDeviceFromNode(node), - CPU_NB_FUNC_03, - REG_NB_DOWNCORE_3X190), - 3, 0, &leveling); - for (i = 0; i < cores; i++) - { - if (leveling & ((u32) 1 << i)) - { - temp--; - } - } - return (u8)(temp+1); -} - -/***************************************************************************//** - * - * static u8 - * fam15GetNumCoresOnNode(u8 node, cNorthBridge *nb) - * - * Description: - * Return the number of cores (1 based count) on node. - * - * Parameters: - * @param[in] node = the node that will be examined - * @param[in] *nb = this northbridge - * @return = the number of cores - * - * - */ -static u8 fam15GetNumCoresOnNode(u8 node, cNorthBridge *nb) -{ - u32 temp, leveling, cores; - u8 i; - - ASSERT((node < nb->maxNodes)); - /* Read CmpCap [7:0] */ - AmdPCIReadBits(MAKE_SBDFO(makePCISegmentFromNode(node), - makePCIBusFromNode(node), - makePCIDeviceFromNode(node), - CPU_NB_FUNC_05, - REG_NB_CAPABILITY_5X84), - 7, 0, &temp); - - /* bits[7:0] specify the cores */ - temp = temp & 0xff; - cores = temp + 1; - - /* Support Downcoring */ - AmdPCIReadBits (MAKE_SBDFO(makePCISegmentFromNode(node), - makePCIBusFromNode(node), - makePCIDeviceFromNode(node), - CPU_NB_FUNC_03, - REG_NB_DOWNCORE_3X190), - 31, 0, &leveling); - for (i = 0; i < cores; i++) - { - if (leveling & ((u32) 1 << i)) - { - temp--; - } - } - return (u8)(temp+1); -} - -/***************************************************************************//** - * - * static void - * setTotalNodesAndCores(u8 node, u8 totalNodes, u8 totalCores, cNorthBridge *nb) - * - * Description: - * Write the total number of cores and nodes to the node - * - * Parameters: - * @param[in] node = the node that will be examined - * @param[in] totalNodes = the total number of nodes - * @param[in] totalCores = the total number of cores - * @param[in] *nb = this northbridge - * - * --------------------------------------------------------------------------------------- - */ -static void setTotalNodesAndCores(u8 node, u8 totalNodes, u8 totalCores, cNorthBridge *nb) -{ - SBDFO nodeIDReg; - u32 temp; - - ASSERT((node < nb->maxNodes) && (totalNodes <= nb->maxNodes)); - nodeIDReg = MAKE_SBDFO(makePCISegmentFromNode(node), - makePCIBusFromNode(node), - makePCIDeviceFromNode(node), - CPU_HTNB_FUNC_00, - REG_NODE_ID_0X60); - - temp = totalCores-1; - /* Rely on max number of nodes:cores for rev F and GH to make - * this code work, even though we write reserved bit 20 on rev F it will be - * zero in that case. - */ - AmdPCIWriteBits(nodeIDReg, 20, 16, &temp); - temp = totalNodes-1; - AmdPCIWriteBits(nodeIDReg, 6, 4, &temp); -} - -/***************************************************************************//** - * - * static void - * limitNodes(u8 node, cNorthBridge *nb) - * - * Description: - * Limit coherent config accesses to cpus as indicated by nodecnt. - * - * Parameters: - * @param[in] node = the node that will be examined - * @param[in] *nb = this northbridge - * - * --------------------------------------------------------------------------------------- - */ -static void limitNodes(u8 node, cNorthBridge *nb) -{ - u32 temp = 1; - ASSERT((node < nb->maxNodes)); - AmdPCIWriteBits(MAKE_SBDFO(makePCISegmentFromNode(node), - makePCIBusFromNode(node), - makePCIDeviceFromNode(node), - CPU_HTNB_FUNC_00, - REG_LINK_TRANS_CONTROL_0X68), - 15, 15, &temp); -} - -/***************************************************************************//** - * - * static void - * writeFullRoutingTable(u8 node, u8 target, u8 reqLink, u8 rspLink, u32 BClinks, cNorthBridge *nb) - * - * Description: - * Write the routing table entry for node to target, using the request link, response - * link, and broadcast links provided. - * - * Parameters: - * @param[in] node = the node that will be examined - * @param[in] target = the target node for these routes - * @param[in] reqLink = the link for requests to target - * @param[in] rspLink = the link for responses to target - * @param[in] bClinks = the broadcast links - * @param[in] *nb = this northbridge - * - * --------------------------------------------------------------------------------------- - */ -static void writeFullRoutingTable(u8 node, u8 target, u8 reqLink, u8 rspLink, u32 bClinks, cNorthBridge *nb) -{ -#ifndef HT_BUILD_NC_ONLY - u32 value = 0; - - ASSERT((node < nb->maxNodes) && (target < nb->maxNodes)); - if (reqLink == ROUTETOSELF) - value |= nb->selfRouteRequestMask; - else - value |= nb->selfRouteRequestMask << (reqLink+1); - - if (rspLink == ROUTETOSELF) - value |= nb->selfRouteResponseMask; - else - value |= nb->selfRouteResponseMask << (rspLink+1); - - /* Allow us to accept a Broadcast ourselves, then set broadcasts for routes */ - value |= (u32)1 << nb->broadcastSelfBit; - value |= (u32)bClinks << (nb->broadcastSelfBit + 1); - - AmdPCIWrite(MAKE_SBDFO(makePCISegmentFromNode(node), - makePCIBusFromNode(node), - makePCIDeviceFromNode(node), - CPU_HTNB_FUNC_00, - REG_ROUTE0_0X40 + target*4), &value); -#else - STOP_HERE; -#endif /* HT_BUILD_NC_ONLY */ -} - -/***************************************************************************//** - * - * static u32 - * makeKey(u8 currentNode) - * - * Description: - * Private routine to northbridge code. - * Determine whether a node is compatible with the discovered configuration so - * far. Currently, that means the family, extended family of the new node are the - * same as the BSP's. - * - * Parameters: - * @param[in] node = the node - * @return = the key value - * - * --------------------------------------------------------------------------------------- - */ -static u32 makeKey(u8 node) -{ - u32 extFam, baseFam; - AmdPCIReadBits(MAKE_SBDFO(makePCISegmentFromNode(node), - makePCIBusFromNode(node), - makePCIDeviceFromNode(node), - CPU_NB_FUNC_03, - REG_NB_CPUID_3XFC), - 27, 20, &extFam); - AmdPCIReadBits(MAKE_SBDFO(makePCISegmentFromNode(node), - makePCIBusFromNode(node), - makePCIDeviceFromNode(node), - CPU_NB_FUNC_03, - REG_NB_CPUID_3XFC), - 11, 8, &baseFam); - return ((u32)(baseFam << 8) | extFam); -} - - -/***************************************************************************//** - * - * static BOOL - * isCompatible(u8 currentNode, cNorthBridge *nb) - * - * Description: - * Determine whether a node is compatible with the discovered configuration so - * far. Currently, that means the family, extended family of the new node are the - * same as the BSP's. - * - * Parameters: - * @param[in] node = the node - * @param[in] *nb = this northbridge - * @return = true: the new is compatible, false: it is not - * - * --------------------------------------------------------------------------------------- - */ -static BOOL isCompatible(u8 node, cNorthBridge *nb) -{ - return (makeKey(node) == nb->compatibleKey); -} - -/***************************************************************************//** - * - * static BOOL - * fam0fIsCapable(u8 node, sMainData *pDat, cNorthBridge *nb) - * - * Description: - * Get node capability and update the minimum supported system capability. - * Return whether the current configuration exceeds the capability. - * - * Parameters: - * @param[in] node = the node - * @param[in,out] *pDat = sysMpCap (updated) and NodesDiscovered - * @param[in] *nb = this northbridge - * @return true: system is capable of current config. - * false: system is not capable of current config. - * - * --------------------------------------------------------------------------------------- - */ -static BOOL fam0fIsCapable(u8 node, sMainData *pDat, cNorthBridge *nb) -{ -#ifndef HT_BUILD_NC_ONLY - u32 temp; - u8 maxNodes; - - ASSERT(node < nb->maxNodes); - - AmdPCIReadBits(MAKE_SBDFO(makePCISegmentFromNode(node), - makePCIBusFromNode(node), - makePCIDeviceFromNode(node), - CPU_NB_FUNC_03, - REG_NB_CAPABILITY_3XE8), - 2, 1, &temp); - if (temp > 1) - { - maxNodes = 8; - } else { - if (temp == 1) - { - maxNodes = 2; - } else { - maxNodes = 1; - } - } - if (pDat->sysMpCap > maxNodes) - { - pDat->sysMpCap = maxNodes; - } - /* Note since sysMpCap is one based and NodesDiscovered is zero based, equal is false */ - return (pDat->sysMpCap > pDat->NodesDiscovered); -#else - return 1; -#endif -} - -/***************************************************************************//** - * - * static BOOL - * fam10IsCapable(u8 node, sMainData *pDat, cNorthBridge *nb) - * - * Description: - * Get node capability and update the minimum supported system capability. - * Return whether the current configuration exceeds the capability. - * - * Parameters: - * @param[in] node = the node - * @param[in,out] *pDat = sysMpCap (updated) and NodesDiscovered - * @param[in] *nb = this northbridge - * @return true: system is capable of current config. - * false: system is not capable of current config. - * - * --------------------------------------------------------------------------------------- - */ -static BOOL fam10IsCapable(u8 node, sMainData *pDat, cNorthBridge *nb) -{ -#ifndef HT_BUILD_NC_ONLY - u32 temp; - u8 maxNodes; - - ASSERT(node < nb->maxNodes); - - AmdPCIReadBits(MAKE_SBDFO(makePCISegmentFromNode(node), - makePCIBusFromNode(node), - makePCIDeviceFromNode(node), - CPU_NB_FUNC_03, - REG_NB_CAPABILITY_3XE8), - 18, 16, &temp); - - if (temp != 0) - { - maxNodes = (1 << (~temp & 0x3)); /* That is, 1, 2, 4, or 8 */ - } - else - { - maxNodes = 8; - } - - if (pDat->sysMpCap > maxNodes) - { - pDat->sysMpCap = maxNodes; - } - /* Note since sysMpCap is one based and NodesDiscovered is zero based, equal is false */ - return (pDat->sysMpCap > pDat->NodesDiscovered); -#else - return 1; -#endif -} - -/***************************************************************************//** - * - * static BOOL - * fam15IsCapable(u8 node, sMainData *pDat, cNorthBridge *nb) - * - * Description: - * Get node capability and update the minimum supported system capability. - * Return whether the current configuration exceeds the capability. - * - * Parameters: - * @param[in] node = the node - * @param[in,out] *pDat = sysMpCap (updated) and NodesDiscovered - * @param[in] *nb = this northbridge - * @return true: system is capable of current config. - * false: system is not capable of current config. - * - * --------------------------------------------------------------------------------------- - */ -static BOOL fam15IsCapable(u8 node, sMainData *pDat, cNorthBridge *nb) -{ -#ifndef HT_BUILD_NC_ONLY - u32 temp; - u8 maxNodes; - - ASSERT(node < nb->maxNodes); - - AmdPCIReadBits(MAKE_SBDFO(makePCISegmentFromNode(node), - makePCIBusFromNode(node), - makePCIDeviceFromNode(node), - CPU_NB_FUNC_03, - REG_NB_CAPABILITY_3XE8), - 18, 16, &temp); - - if (temp != 0) - { - maxNodes = (1 << (~temp & 0x3)); /* That is, 1, 2, 4, or 8 */ - } - else - { - /* Check if CPU package is dual node */ - AmdPCIReadBits(MAKE_SBDFO(makePCISegmentFromNode(node), - makePCIBusFromNode(node), - makePCIDeviceFromNode(node), - CPU_NB_FUNC_03, - REG_NB_CAPABILITY_3XE8), - 29, 29, &temp); - if (temp) - maxNodes = 4; - else - maxNodes = 8; - } - - if (pDat->sysMpCap > maxNodes) - { - pDat->sysMpCap = maxNodes; - } - /* Note since sysMpCap is one based and NodesDiscovered is zero based, equal is false */ - return (pDat->sysMpCap > pDat->NodesDiscovered); -#else - return 1; -#endif -} - -/***************************************************************************//** - * - * static void - * fam0fStopLink(u8 currentNode, u8 currentLink, cNorthBridge *nb) - * - * Description: - * Disable a cHT link on node by setting F0x[E4, C4, A4, 84][TransOff, EndOfChain]=1 - * - * Parameters: - * @param[in] node = the node this link is on - * @param[in] link = the link to stop - * @param[in] *nb = this northbridge - * - * --------------------------------------------------------------------------------------- - */ -static void fam0fStopLink(u8 node, u8 link, cNorthBridge *nb) -{ -#ifndef HT_BUILD_NC_ONLY - u32 temp; - SBDFO linkBase; - - ASSERT((node < nb->maxNodes) && (link < nb->maxLinks)); - - linkBase = makeLinkBase(node, link); - - /* Set TransOff, EndOfChain */ - temp = 3; - setHtControlRegisterBits(linkBase + HTHOST_LINK_CONTROL_REG, 7, 6, &temp); -#endif -} - -/***************************************************************************//** - * - * static void - * commonVoid() - * - * Description: - * Nothing. - * - * Parameters: - * None. - * - * --------------------------------------------------------------------------------------- - */ -static void commonVoid(void) -{ -} - -/***************************************************************************//** - * - * static BOOL - * commonReturnFalse() - * - * Description: - * Return False. - * - * Parameters: - * @return = false - * - */ -static BOOL commonReturnFalse(void) -{ - return 0; -} - -/*************************************************************************** - *** Non-coherent init code *** - *** Northbridge access routines *** - ***************************************************************************/ - -/***************************************************************************//** - * - * static u8 - * readSbLink(cNorthBridge *nb) - * - * Description: - * Return the link to the Southbridge - * - * Parameters: - * @param[in] *nb = this northbridge - * @return the link to the southbridge - * - * --------------------------------------------------------------------------------------- - */ -static u8 readSbLink(cNorthBridge *nb) -{ - u32 temp; - AmdPCIReadBits(MAKE_SBDFO(makePCISegmentFromNode(0), - makePCIBusFromNode(0), - makePCIDeviceFromNode(0), - CPU_HTNB_FUNC_00, - REG_UNIT_ID_0X64), - 10, 8, &temp); - return (u8)temp; -} - -/***************************************************************************//** - * - * static BOOL - * verifyLinkIsNonCoherent(u8 node, u8 link, cNorthBridge *nb) - * - * Description: - * Verify that the link is non-coherent, connected, and ready - * - * Parameters: - * @param[in] node = the node that will be examined - * @param[in] link = the Link on that node to examine - * @param[in] *nb = this northbridge - * @return = true - The link has the following status - * LinkCon = 1, Link is connected - * InitComplete = 1,Link initialization is complete - * NC = 1, Link is coherent - * UniP-cLDT = 0, Link is not Uniprocessor cLDT - * LinkConPend = 0 Link connection is not pending - * false- The link has some other status - * - * --------------------------------------------------------------------------------------- - */ -static BOOL verifyLinkIsNonCoherent(u8 node, u8 link, cNorthBridge *nb) -{ - u32 linkType; - SBDFO linkBase; - - ASSERT((node < nb->maxNodes) && (link < nb->maxLinks)); - - linkBase = makeLinkBase(node, link); - - /* FN0_98/A4/C4 = LDT Type Register */ - AmdPCIRead(linkBase + HTHOST_LINK_TYPE_REG, &linkType); - - /* Verify linkCon = 1, InitComplete = 1, NC = 0, UniP-cLDT = 0, LinkConPend = 0 */ - return (linkType & HTHOST_TYPE_MASK) == HTHOST_TYPE_NONCOHERENT; -} - -/***************************************************************************//** - * - * static void - * ht3SetCFGAddrMap(u8 cfgMapIndex, u8 secBus, u8 subBus, u8 targetNode, u8 targetLink, sMainData *pDat, cNorthBridge *nb) - * - * Description: - * Configure and enable config access to a non-coherent chain for the given bus range. - * - * Parameters: - * @param[in] cfgMapIndex = the map entry to set - * @param[in] secBus = The secondary bus number to use - * @param[in] subBus = The subordinate bus number to use - * @param[in] targetNode = The node that shall be the recipient of the traffic - * @param[in] targetLink = The link that shall be the recipient of the traffic - * @param[in] pDat = our global state - * @param[in] *nb = this northbridge - * - * --------------------------------------------------------------------------------------- - */ -static void ht3SetCFGAddrMap(u8 cfgMapIndex, u8 secBus, u8 subBus, u8 targetNode, u8 targetLink, sMainData *pDat, cNorthBridge *nb) -{ - u8 curNode; - SBDFO linkBase; - u32 temp; - - linkBase = makeLinkBase(targetNode, targetLink); - - ASSERT(secBus <= subBus); - temp = secBus; - AmdPCIWriteBits(linkBase + HTHOST_ISOC_REG, 15, 8, &temp); - - /* For target link, note that rev F uses bits 9:8 and only with GH is bit 10 - * set to indicate a sublink. For node, we are currently not supporting Extended - * routing tables. - */ - temp = ((u32)subBus << 24) + ((u32)secBus << 16) + ((u32)targetLink << 8) - + ((u32)targetNode << 4) + (u32)3; - for (curNode = 0; curNode < pDat->NodesDiscovered+1; curNode++) - AmdPCIWrite(MAKE_SBDFO(makePCISegmentFromNode(curNode), - makePCIBusFromNode(curNode), - makePCIDeviceFromNode(curNode), - CPU_ADDR_FUNC_01, - REG_ADDR_CONFIG_MAP0_1XE0 + 4*cfgMapIndex), - &temp); -} - -/***************************************************************************//** - * - * static void - * ht1SetCFGAddrMap(u8 cfgMapIndex, u8 secBus, u8 subBus, u8 targetNode, u8 targetLink, sMainData *pDat, cNorthBridge *nb) - * - * Description: - * Configure and enable config access to a non-coherent chain for the given bus range. - * - * Parameters: - * @param[in] cfgMapIndex = the map entry to set - * @param[in] secBus = The secondary bus number to use - * @param[in] subBus = The subordinate bus number to use - * @param[in] targetNode = The node that shall be the recipient of the traffic - * @param[in] targetLink = The link that shall be the recipient of the traffic - * @param[in] pDat = our global state - * @param[in] *nb = this northbridge - * - ******************************************************************************/ -static void ht1SetCFGAddrMap(u8 cfgMapIndex, u8 secBus, u8 subBus, u8 targetNode, u8 targetLink, sMainData *pDat, cNorthBridge *nb) -{ - u8 curNode; - SBDFO linkBase; - u32 temp; - - linkBase = makeLinkBase(targetNode, targetLink); - - ASSERT(secBus <= subBus); - temp = secBus; - AmdPCIWriteBits(linkBase + HTHOST_ISOC_REG, 15, 8, &temp); - - temp = subBus; - AmdPCIWriteBits(linkBase + HTHOST_ISOC_REG, 23, 16, &temp); - - /* For target link, note that rev F uses bits 9:8 and only with GH is bit 10 - * set to indicate a sublink. For node, we are currently not supporting Extended - * routing tables. - */ - temp = ((u32)subBus << 24) + ((u32)secBus << 16) + ((u32)targetLink << 8) - + ((u32)targetNode << 4) + (u32)3; - for (curNode = 0; curNode < pDat->NodesDiscovered+1; curNode++) - AmdPCIWrite(MAKE_SBDFO(makePCISegmentFromNode(curNode), - makePCIBusFromNode(curNode), - makePCIDeviceFromNode(curNode), - CPU_ADDR_FUNC_01, - REG_ADDR_CONFIG_MAP0_1XE0 + 4*cfgMapIndex), - &temp); -} - -/*************************************************************************** - *** Link Optimization *** - ***************************************************************************/ - -/** - * static u8 - * convertBitsToWidth(u8 value, cNorthBridge *nb) - * - * Description: - * Given the bits set in the register field, return the width it represents - * - * Parameters: - * @param[in] value = The bits for the register - * @param[in] *nb = this northbridge - * @return The width - * - ******************************************************************************/ -static u8 convertBitsToWidth(u8 value, cNorthBridge *nb) -{ - switch (value) { - case 1: return 16; - case 0: return 8; - case 5: return 4; - case 4: return 2; - default: STOP_HERE; /* This is an error internal condition */ - } - return 0; // shut up GCC. -} - -/***************************************************************************//** - * - * static u8 - * convertWidthToBits(u8 value, cNorthBridge *nb) - * - * Description: - * Translate a desired width setting to the bits to set in the register field - * - * Parameters: - * @param[in] value = The width - * @param[in] *nb = this northbridge - * @return The bits for the register - * - ******************************************************************************/ -static u8 convertWidthToBits(u8 value, cNorthBridge *nb) -{ - switch (value) { - case 16: return 1; - case 8: return 0; - case 4: return 5; - case 2: return 4; - default: STOP_HERE; /* This is an internal error condition */ - } - return 0; // shut up GCC -} - -/***************************************************************************//** - * - * static u16 - * ht1NorthBridgeFreqMask(u8 NodeID, cNorthBridge *nb) - * - * Description: - * Return a mask that eliminates HT frequencies that cannot be used due to a slow - * northbridge frequency. - * - * Parameters: - * @param[in] node = Result could (later) be for a specific node - * @param[in] *nb = this northbridge - * @return Frequency mask - * - ******************************************************************************/ -static uint32_t ht1NorthBridgeFreqMask(u8 node, cNorthBridge *nb) -{ - /* only up to HT1 speeds */ - return (HT_FREQUENCY_LIMIT_HT1_ONLY); -} - -/***************************************************************************//** - * - * static u16 - * fam10NorthBridgeFreqMask(u8 NodeID, cNorthBridge *nb) - * - * Description: - * Return a mask that eliminates HT frequencies that cannot be used due to a slow - * northbridge frequency. - * - * Parameters: - * @param[in] node = Result could (later) be for a specific node - * @param[in] *nb = this northbridge - * @return = Frequency mask - * - ******************************************************************************/ -static uint32_t fam10NorthBridgeFreqMask(u8 node, cNorthBridge *nb) -{ - u8 nbCOF; - uint32_t supported; - - nbCOF = getMinNbCOF(); - /* - * nbCOF is minimum northbridge speed in hundreds of MHz. - * HT can not go faster than the minimum speed of the northbridge. - */ - if ((nbCOF >= 6) && (nbCOF < 10)) - { - /* Generation 1 HT link frequency */ - /* Convert frequency to bit and all less significant bits, - * by setting next power of 2 and subtracting 1. - */ - supported = ((uint32_t)1 << ((nbCOF >> 1) + 2)) - 1; - } - else if ((nbCOF >= 10) && (nbCOF <= 32)) - { - /* Generation 3 HT link frequency - * Assume error retry is enabled on all Gen 3 links - */ - if (is_gt_rev_d()) { - nbCOF *= 2; - if (nbCOF > 32) - nbCOF = 32; - } - - /* Convert frequency to bit and all less significant bits, - * by setting next power of 2 and subtracting 1. - */ - supported = ((uint32_t)1 << ((nbCOF >> 1) + 2)) - 1; - } - else if (nbCOF > 32) - { - supported = HT_FREQUENCY_LIMIT_3200M; - } - /* unlikely cases, but include as a defensive measure, also avoid trick above */ - else if (nbCOF == 4) - { - supported = HT_FREQUENCY_LIMIT_400M; - } - else if (nbCOF == 2) - { - supported = HT_FREQUENCY_LIMIT_200M; - } - else - { - STOP_HERE; - supported = HT_FREQUENCY_LIMIT_200M; - } - - return (fixEarlySampleFreqCapability(supported)); -} - -/***************************************************************************//** - * - * static u16 - * fam15NorthBridgeFreqMask(u8 NodeID, cNorthBridge *nb) - * - * Description: - * Return a mask that eliminates HT frequencies that cannot be used due to a slow - * northbridge frequency. - * - * Parameters: - * @param[in] node = Result could (later) be for a specific node - * @param[in] *nb = this northbridge - * @return = Frequency mask - * - ******************************************************************************/ -static uint32_t fam15NorthBridgeFreqMask(u8 node, cNorthBridge *nb) -{ - u8 nbCOF; - uint32_t supported; - - nbCOF = getMinNbCOF(); - /* - * nbCOF is minimum northbridge speed in hundreds of MHz. - * HT can not go faster than the minimum speed of the northbridge. - */ - if ((nbCOF >= 6) && (nbCOF < 10)) - { - /* Generation 1 HT link frequency */ - /* Convert frequency to bit and all less significant bits, - * by setting next power of 2 and subtracting 1. - */ - supported = ((uint32_t)1 << ((nbCOF >> 1) + 2)) - 1; - } - else if ((nbCOF >= 10) && (nbCOF <= 32)) - { - /* Generation 3 HT link frequency - * Assume error retry is enabled on all Gen 3 links - */ - nbCOF *= 2; - if (nbCOF > 32) - nbCOF = 32; - - /* Convert frequency to bit and all less significant bits, - * by setting next power of 2 and subtracting 1. - */ - supported = ((uint32_t)1 << ((nbCOF >> 1) + 2)) - 1; - } - else if (nbCOF > 32) - { - supported = HT_FREQUENCY_LIMIT_3200M; - } - /* unlikely cases, but include as a defensive measure, also avoid trick above */ - else if (nbCOF == 4) - { - supported = HT_FREQUENCY_LIMIT_400M; - } - else if (nbCOF == 2) - { - supported = HT_FREQUENCY_LIMIT_200M; - } - else - { - STOP_HERE; - supported = HT_FREQUENCY_LIMIT_200M; - } - - return (fixEarlySampleFreqCapability(supported)); -} - -/***************************************************************************//** - * - * static void - * gatherLinkData(sMainData *pDat, cNorthBridge *nb) - * - * Description: - * For all discovered links, populate the port list with the frequency and width - * capabilities. - * - * Parameters: - * @param[in,out] pDat = our global state, port list - * @param[in] *nb = this northbridge - * - ******************************************************************************/ -static void gatherLinkData(sMainData *pDat, cNorthBridge *nb) -{ - u8 i; - SBDFO linkBase; - u32 temp; - - for (i = 0; i < pDat->TotalLinks*2; i++) - { - if (pDat->PortList[i].Type == PORTLIST_TYPE_CPU) - { - linkBase = makeLinkBase(pDat->PortList[i].NodeID, pDat->PortList[i].Link); - - pDat->PortList[i].Pointer = linkBase; - - AmdPCIReadBits(linkBase + HTHOST_LINK_CONTROL_REG, 22, 20, &temp); - pDat->PortList[i].PrvWidthOutCap = convertBitsToWidth((u8)temp, pDat->nb); - - AmdPCIReadBits(linkBase + HTHOST_LINK_CONTROL_REG, 18, 16, &temp); - pDat->PortList[i].PrvWidthInCap = convertBitsToWidth((u8)temp, pDat->nb); - - AmdPCIReadBits(linkBase + HTHOST_FREQ_REV_REG, 31, 16, &temp); - pDat->PortList[i].PrvFrequencyCap = temp & 0x7FFF /* Mask off bit 15, reserved value */ - & nb->northBridgeFreqMask(pDat->PortList[i].NodeID, pDat->nb); - if (is_gt_rev_d()) { - AmdPCIReadBits(linkBase + HTHOST_FREQ_REV_REG_2, 15, 1, &temp); - temp &= 0x7; /* Mask off reserved values */ - pDat->PortList[i].PrvFrequencyCap |= (temp << 17); - } - - AmdPCIReadBits(linkBase + HTHOST_FEATURE_CAP_REG, 9, 0, &temp); - pDat->PortList[i].PrvFeatureCap = (u16)temp; - } - else - { - linkBase = pDat->PortList[i].Pointer; - if (pDat->PortList[i].Link == 1) - linkBase += HTSLAVE_LINK01_OFFSET; - - AmdPCIReadBits(linkBase + HTSLAVE_LINK_CONTROL_0_REG, 22, 20, &temp); - pDat->PortList[i].PrvWidthOutCap = convertBitsToWidth((u8)temp, pDat->nb); - - AmdPCIReadBits(linkBase + HTSLAVE_LINK_CONTROL_0_REG, 18, 16, &temp); - pDat->PortList[i].PrvWidthInCap = convertBitsToWidth((u8)temp, pDat->nb); - - AmdPCIReadBits(linkBase + HTSLAVE_FREQ_REV_0_REG, 31, 16, &temp); - pDat->PortList[i].PrvFrequencyCap = (u16)temp; - - AmdPCIReadBits(linkBase + HTSLAVE_FEATURE_CAP_REG, 7, 0, &temp); - pDat->PortList[i].PrvFeatureCap = (u16)temp; - - if (pDat->HtBlock->AMD_CB_DeviceCapOverride) - { - linkBase &= 0xFFFFF000; - AmdPCIRead(linkBase, &temp); - - pDat->HtBlock->AMD_CB_DeviceCapOverride( - pDat->PortList[i].NodeID, - pDat->PortList[i].HostLink, - pDat->PortList[i].HostDepth, - (u8)SBDFO_SEG(pDat->PortList[i].Pointer), - (u8)SBDFO_BUS(pDat->PortList[i].Pointer), - (u8)SBDFO_DEV(pDat->PortList[i].Pointer), - temp, - pDat->PortList[i].Link, - &(pDat->PortList[i].PrvWidthInCap), - &(pDat->PortList[i].PrvWidthOutCap), - &(pDat->PortList[i].PrvFrequencyCap), - &(pDat->PortList[i].PrvFeatureCap)); - } - } - } -} - -/***************************************************************************//** - * - * static void - * setLinkData(sMainData *pDat, cNorthBridge *nb) - * - * Description: - * Change the hardware state for all links according to the now optimized data in the - * port list data structure. - * - * Parameters: - * @param[in] pDat = our global state, port list - * @param[in] *nb = this northbridge - * - ******************************************************************************/ -static void setLinkData(sMainData *pDat, cNorthBridge *nb) -{ - u8 i; - SBDFO linkBase; - u32 temp, temp2, frequency_index, widthin, widthout, bits; - - for (i = 0; i < pDat->TotalLinks*2; i++) - { - - ASSERT(pDat->PortList[i&0xFE].SelWidthOut == pDat->PortList[(i&0xFE)+1].SelWidthIn); - ASSERT(pDat->PortList[i&0xFE].SelWidthIn == pDat->PortList[(i&0xFE)+1].SelWidthOut); - ASSERT(pDat->PortList[i&0xFE].SelFrequency == pDat->PortList[(i&0xFE)+1].SelFrequency); - - if (pDat->PortList[i].SelRegang) - { - ASSERT(pDat->PortList[i].Type == PORTLIST_TYPE_CPU); - ASSERT(pDat->PortList[i].Link < 4); - temp = 1; - AmdPCIWriteBits(MAKE_SBDFO(makePCISegmentFromNode(pDat->PortList[i].NodeID), - makePCIBusFromNode(pDat->PortList[i].NodeID), - makePCIDeviceFromNode(pDat->PortList[i].NodeID), - CPU_HTNB_FUNC_00, - REG_HT_LINK_EXT_CONTROL0_0X170 + 4*pDat->PortList[i].Link), - 0, 0, &temp); - } - - if (pDat->PortList[i].Type == PORTLIST_TYPE_CPU) - { - if (pDat->HtBlock->AMD_CB_OverrideCpuPort) - pDat->HtBlock->AMD_CB_OverrideCpuPort(pDat->PortList[i].NodeID, - pDat->PortList[i].Link, - &(pDat->PortList[i].SelWidthIn), - &(pDat->PortList[i].SelWidthOut), - &(pDat->PortList[i].SelFrequency)); - } - else - { - if (pDat->HtBlock->AMD_CB_OverrideDevicePort) - pDat->HtBlock->AMD_CB_OverrideDevicePort(pDat->PortList[i].NodeID, - pDat->PortList[i].HostLink, - pDat->PortList[i].HostDepth, - pDat->PortList[i].Link, - &(pDat->PortList[i].SelWidthIn), - &(pDat->PortList[i].SelWidthOut), - &(pDat->PortList[i].SelFrequency)); - } - - linkBase = pDat->PortList[i].Pointer; - if ((pDat->PortList[i].Type == PORTLIST_TYPE_IO) && (pDat->PortList[i].Link == 1)) - linkBase += HTSLAVE_LINK01_OFFSET; - - /* Some IO devices don't work properly when setting widths, so write them in a single operation, - * rather than individually. - */ - widthout = convertWidthToBits(pDat->PortList[i].SelWidthOut, pDat->nb); - ASSERT(widthout == 1 || widthout == 0 || widthout == 5 || widthout == 4); - widthin = convertWidthToBits(pDat->PortList[i].SelWidthIn, pDat->nb); - ASSERT(widthin == 1 || widthin == 0 || widthin == 5 || widthin == 4); - - temp = (widthin & 7) | ((widthout & 7) << 4); - setHtControlRegisterBits(linkBase + HTHOST_LINK_CONTROL_REG, 31, 24, &temp); - - temp = pDat->PortList[i].SelFrequency; - if (pDat->PortList[i].Type == PORTLIST_TYPE_CPU) - { - ASSERT((temp >= HT_FREQUENCY_600M && temp <= HT_FREQUENCY_3200M) - || (temp == HT_FREQUENCY_200M) || (temp == HT_FREQUENCY_400M)); - frequency_index = temp; - if (temp > 0xf) { - temp2 = (temp >> 4) & 0x1; - temp &= 0xf; - } else { - temp2 = 0x0; - } - /* NOTE - * The Family 15h BKDG Rev. 3.14 is wrong - * Freq[4] must be set before Freq[3:0], otherwise the register writes will be ignored! - */ - if (is_gt_rev_d()) - AmdPCIWriteBits(linkBase + HTHOST_FREQ_REV_REG_2, 0, 0, &temp2); - AmdPCIWriteBits(linkBase + HTHOST_FREQ_REV_REG, 11, 8, &temp); - - /* Enable isochronous flow control mode if supported by chipset */ - if (is_fam15h()) { - if (pDat->PortList[i].enable_isochronous_mode) - temp = 1; - else - temp = 0; - setHtControlRegisterBits(linkBase + HTHOST_LINK_CONTROL_REG, 12, 12, &temp); - } - - if (frequency_index > HT_FREQUENCY_1000M) /* Gen1 = 200MHz -> 1000MHz, Gen3 = 1200MHz -> 3200MHz */ - { - /* Enable for Gen3 frequencies */ - temp = 1; - } - else - { - /* Disable for Gen1 frequencies */ - temp = 0; - } - /* HT3 retry mode enable / disable */ - AmdPCIWriteBits(MAKE_SBDFO(makePCISegmentFromNode(pDat->PortList[i].NodeID), - makePCIBusFromNode(pDat->PortList[i].NodeID), - makePCIDeviceFromNode(pDat->PortList[i].NodeID), - CPU_HTNB_FUNC_00, - REG_HT_LINK_RETRY0_0X130 + 4*pDat->PortList[i].Link), - 0, 0, &temp); - - /* and Scrambling enable / disable */ - AmdPCIWriteBits(MAKE_SBDFO(makePCISegmentFromNode(pDat->PortList[i].NodeID), - makePCIBusFromNode(pDat->PortList[i].NodeID), - makePCIDeviceFromNode(pDat->PortList[i].NodeID), - CPU_HTNB_FUNC_00, - REG_HT_LINK_EXT_CONTROL0_0X170 + 4*pDat->PortList[i].Link), - 3, 3, &temp); - } - else - { - SBDFO currentPtr; - BOOL isFound; - - ASSERT(temp <= HT_FREQUENCY_3200M); - /* Write the frequency setting */ - AmdPCIWriteBits(linkBase + HTSLAVE_FREQ_REV_0_REG, 11, 8, &temp); - - /* Handle additional HT3 frequency requirements, if needed, - * or clear them if switching down to ht1 on a warm reset. - * Gen1 = 200MHz -> 1000MHz, Gen3 = 1200MHz -> 2600MHz - * - * Even though we assert if debugging, we need to check that the capability was found - * always, since this is an unknown hardware device, also we are taking - * unqualified frequency from the call backs - * (could be trying to do ht3 on an ht1 IO device). - */ - - if (temp > HT_FREQUENCY_1000M) - { - /* Enabling features if gen 3 */ - bits = 1; - } - else - { - /* Disabling features if gen 1 */ - bits = 0; - } - - /* Enable isochronous flow control mode if supported by chipset */ - if (is_fam15h()) { - if (pDat->PortList[i].enable_isochronous_mode) - temp = 1; - else - temp = 0; - } - - /* Retry Enable */ - isFound = FALSE; - currentPtr = linkBase & (u32)0xFFFFF000; /* Set PCI Offset to 0 */ - do - { - AmdPCIFindNextCap(¤tPtr); - if (currentPtr != ILLEGAL_SBDFO) - { - AmdPCIRead(currentPtr, &temp); - /* HyperTransport Retry Capability? */ - if (IS_HT_RETRY_CAPABILITY(temp)) - { - ASSERT(pDat->PortList[i].Link < 2); - AmdPCIWriteBits(currentPtr + HTRETRY_CONTROL_REG, - pDat->PortList[i].Link*16, - pDat->PortList[i].Link*16, - &bits); - isFound = TRUE; - } - /* Some other capability, keep looking */ - } - else - { - /* If we are turning it off, that may mean the device was only ht1 capable, - * so don't complain that we can't do it. - */ - if (bits != 0) - { - if (pDat->HtBlock->AMD_CB_EventNotify) - { - sHtEventOptRequiredCap evt; - evt.eSize = sizeof(sHtEventOptRequiredCap); - evt.node = pDat->PortList[i].NodeID; - evt.link = pDat->PortList[i].HostLink; - evt.depth = pDat->PortList[i].HostDepth; - - pDat->HtBlock->AMD_CB_EventNotify(HT_EVENT_CLASS_WARNING, - HT_EVENT_OPT_REQUIRED_CAP_RETRY, - (u8 *)&evt); - } - STOP_HERE; - } - isFound = TRUE; - } - } while (!isFound); - - /* Scrambling enable */ - isFound = FALSE; - currentPtr = linkBase & (u32)0xFFFFF000; /* Set PCI Offset to 0 */ - do - { - AmdPCIFindNextCap(¤tPtr); - if (currentPtr != ILLEGAL_SBDFO) - { - AmdPCIRead(currentPtr, &temp); - /* HyperTransport Gen3 Capability? */ - if (IS_HT_GEN3_CAPABILITY(temp)) - { - ASSERT(pDat->PortList[i].Link < 2); - AmdPCIWriteBits((currentPtr + - HTGEN3_LINK_TRAINING_0_REG + - pDat->PortList[i].Link*HTGEN3_LINK01_OFFSET), - 3, 3, &bits); - isFound = TRUE; - } - /* Some other capability, keep looking */ - } - else - { - /* If we are turning it off, that may mean the device was only ht1 capable, - * so don't complain that we can't do it. - */ - if (bits != 0) - { - if (pDat->HtBlock->AMD_CB_EventNotify) - { - sHtEventOptRequiredCap evt; - evt.eSize = sizeof(sHtEventOptRequiredCap); - evt.node = pDat->PortList[i].NodeID; - evt.link = pDat->PortList[i].HostLink; - evt.depth = pDat->PortList[i].HostDepth; - - pDat->HtBlock->AMD_CB_EventNotify(HT_EVENT_CLASS_WARNING, - HT_EVENT_OPT_REQUIRED_CAP_GEN3, - (u8 *)&evt); - } - STOP_HERE; - } - isFound = TRUE; - } - } while (!isFound); - } - } -} - -/***************************************************************************//** - * - * void - * fam0fWriteHTLinkCmdBufferAlloc(u8 node, u8 link, u8 req, u8 preq, u8 rsp, u8 prb) - * - * Description: - * Set the command buffer allocations in the buffer count register for the node and link. - * The command buffer settings in the low 16 bits are the same on both - * family 10h and family 0fh northbridges. - * - * Parameters: - * @param[in] node = The node to set allocations on - * @param[in] link = the link to set allocations on - * @param[in] req = non-posted Request Command Buffers - * @param[in] preq = Posted Request Command Buffers - * @param[in] rsp = Response Command Buffers - * @param[in] prb = Probe Command Buffers - * - ******************************************************************************/ -#ifndef HT_BUILD_NC_ONLY - -static void fam0fWriteHTLinkCmdBufferAlloc(u8 node, u8 link, u8 req, u8 preq, u8 rsp, u8 prb) -{ - u32 temp; - SBDFO currentPtr; - - currentPtr = makeLinkBase(node, link); - currentPtr += HTHOST_BUFFER_COUNT_REG; - - /* non-posted Request Command Buffers */ - temp = req; - AmdPCIWriteBits(currentPtr, 3, 0, &temp); - /* Posted Request Command Buffers */ - temp = preq; - AmdPCIWriteBits(currentPtr, 7, 4, &temp); - /* Response Command Buffers */ - temp = rsp; - AmdPCIWriteBits(currentPtr, 11, 8, &temp); - /* Probe Command Buffers */ - temp = prb; - AmdPCIWriteBits(currentPtr, 15, 12, &temp); - /* LockBc */ - temp = 1; - AmdPCIWriteBits(currentPtr, 31, 31, &temp); -} -#endif /* HT_BUILD_NC_ONLY */ - -/***************************************************************************//** - * - * void - * fam0fWriteHTLinkDatBufferAlloc(u8 node, u8 link, u8 reqD, u8 preqD, u8 rspD) - * - * Description: - * Set the data buffer allocations in the buffer count register for the node and link. - * The command buffer settings in the high 16 bits are not the same on both - * family 10h and family 0fh northbridges. - * - * Parameters: - * @param[in] node = The node to set allocations on - * @param[in] link = the link to set allocations on - * @param[in] reqD = non-posted Request Data Buffers - * @param[in] preqD = Posted Request Data Buffers - * @param[in] rspD = Response Data Buffers - * - ******************************************************************************/ -#ifndef HT_BUILD_NC_ONLY - -static void fam0fWriteHTLinkDatBufferAlloc(u8 node, u8 link, u8 reqD, u8 preqD, u8 rspD) -{ - u32 temp; - SBDFO currentPtr; - - currentPtr = makeLinkBase(node, link); - currentPtr += HTHOST_BUFFER_COUNT_REG; - - /* Request Data Buffers */ - temp = reqD; - AmdPCIWriteBits(currentPtr, 18, 16, &temp); - /* Posted Request Data Buffers */ - temp = preqD; - AmdPCIWriteBits(currentPtr, 22, 20, &temp); - /* Response Data Buffers */ - temp = rspD; - AmdPCIWriteBits(currentPtr, 26, 24, &temp); -} -#endif /* HT_BUILD_NC_ONLY */ - -/***************************************************************************//** - * - * static void - * ht3WriteTrafficDistribution(u32 links01, u32 links10, cNorthBridge *nb) - * - * Description: - * Set the traffic distribution register for the links provided. - * - * Parameters: - * @param[in] links01 = coherent links from node 0 to 1 - * @param[in] links10 = coherent links from node 1 to 0 - * @param[in] nb = this northbridge - * - ******************************************************************************/ -static void ht3WriteTrafficDistribution(u32 links01, u32 links10, cNorthBridge *nb) -{ -#ifndef HT_BUILD_NC_ONLY - u32 temp; - - /* Node 0 */ - /* DstLnk */ - AmdPCIWriteBits(MAKE_SBDFO(makePCISegmentFromNode(0), - makePCIBusFromNode(0), - makePCIDeviceFromNode(0), - CPU_HTNB_FUNC_00, - REG_HT_TRAFFIC_DIST_0X164), - 23, 16, &links01); - /* DstNode = 1, cHTPrbDistEn = 1, cHTRspDistEn = 1, cHTReqDistEn = 1 */ - temp = 0x0107; - AmdPCIWriteBits(MAKE_SBDFO(makePCISegmentFromNode(0), - makePCIBusFromNode(0), - makePCIDeviceFromNode(0), - CPU_HTNB_FUNC_00, - REG_HT_TRAFFIC_DIST_0X164), - 15, 0, &temp); - - /* Node 1 */ - /* DstLnk */ - AmdPCIWriteBits(MAKE_SBDFO(makePCISegmentFromNode(1), - makePCIBusFromNode(1), - makePCIDeviceFromNode(1), - CPU_HTNB_FUNC_00, - REG_HT_TRAFFIC_DIST_0X164), - 23, 16, &links10); - /* DstNode = 0, cHTPrbDistEn = 1, cHTRspDistEn = 1, cHTReqDistEn = 1 */ - temp = 0x0007; - AmdPCIWriteBits(MAKE_SBDFO(makePCISegmentFromNode(1), - makePCIBusFromNode(1), - makePCIDeviceFromNode(1), - CPU_HTNB_FUNC_00, - REG_HT_TRAFFIC_DIST_0X164), - 15, 0, &temp); -#endif /* HT_BUILD_NC_ONLY */ -} - -/***************************************************************************//** - * - * static void - * ht1WriteTrafficDistribution(u32 links01, u32 links10, cNorthBridge *nb) - * - * Description: - * Traffic distribution is more complex in this case as the routing table must be - * adjusted to use one link for requests and the other for responses. Also, - * perform the buffer tunings on the links required for this config. - * - * Parameters: - * @param[in] links01 = coherent links from node 0 to 1 - * @param[in] links10 = coherent links from node 1 to 0 - * @param[in] nb = this northbridge - * - ******************************************************************************/ -static void ht1WriteTrafficDistribution(u32 links01, u32 links10, cNorthBridge *nb) -{ -#ifndef HT_BUILD_NC_ONLY - u32 route01, route10; - u8 req0, req1, rsp0, rsp1, nclink; - - /* - * Get the current request route for 0->1 and 1->0. This will indicate which of the links - * in links01 are connected to which links in links10. Since we have to route to distribute - * traffic, we need to know that. The link used by htinit will become the request, probe link. - * the other link will be used for responses. - */ - - /* Get the routes, and hang on to them, we will write them back updated. */ - AmdPCIRead(MAKE_SBDFO(makePCISegmentFromNode(0), - makePCIBusFromNode(0), - makePCIDeviceFromNode(0), - CPU_HTNB_FUNC_00, - REG_ROUTE1_0X44), - &route01); - AmdPCIRead(MAKE_SBDFO(makePCISegmentFromNode(1), - makePCIBusFromNode(1), - makePCIDeviceFromNode(1), - CPU_HTNB_FUNC_00, - REG_ROUTE0_0X40), - &route10); - - /* Convert the request routes to a link number. Note "0xE" is ht1 nb specific. - * Find the response link numbers. - */ - ASSERT((route01 & 0xE) && (route10 & 0xE)); /* no route! error! */ - req0 = (u8)AmdBitScanReverse((route01 & 0xE)) - 1; - req1 = (u8)AmdBitScanReverse((route10 & 0xE)) - 1; - /* Now, find the other link for the responses */ - rsp0 = (u8)AmdBitScanReverse((links01 & ~((u32)1 << req0))); - rsp1 = (u8)AmdBitScanReverse((links10 & ~((u32)1 << req1))); - - /* ht1 nb restriction, must have exactly two links */ - ASSERT(((((links01 & ~((u32)1 << req0)) & ~((u32)1 << rsp0))) == 0) - && ((((links10 & ~((u32)1 << req1)) & ~((u32)1 << rsp1))) == 0)); - - route01 = (route01 & ~0x0E00) | ((u32)0x0100<<(rsp0 + 1)); - route10 = (route10 & ~0x0E00) | ((u32)0x0100<<(rsp1 + 1)); - - AmdPCIWrite(MAKE_SBDFO(makePCISegmentFromNode(0), - makePCIBusFromNode(0), - makePCIDeviceFromNode(0), - CPU_HTNB_FUNC_00, - REG_ROUTE1_0X44), - &route01); - - AmdPCIWrite(MAKE_SBDFO(makePCISegmentFromNode(1), - makePCIBusFromNode(1), - makePCIDeviceFromNode(1), - CPU_HTNB_FUNC_00, - REG_ROUTE0_0X40), - &route10); - - /* While we otherwise do buffer tunings elsewhere, for the dual cHT DP case with - * ht1 northbridges like family 0Fh, do the tunings here where we have all the - * link and route info at hand and don't need to recalculate it. - */ - - /* Node 0, Request / Probe Link (note family F only has links < 4) */ - fam0fWriteHTLinkCmdBufferAlloc(0, req0, 6, 3, 1, 6); - fam0fWriteHTLinkDatBufferAlloc(0, req0, 4, 3, 1); - /* Node 0, Response Link (note family F only has links < 4) */ - fam0fWriteHTLinkCmdBufferAlloc(0, rsp0, 1, 0, 15, 0); - fam0fWriteHTLinkDatBufferAlloc(0, rsp0, 1, 1, 6); - /* Node 1, Request / Probe Link (note family F only has links < 4) */ - fam0fWriteHTLinkCmdBufferAlloc(1, req1, 6, 3, 1, 6); - fam0fWriteHTLinkDatBufferAlloc(1, req1, 4, 3, 1); - /* Node 1, Response Link (note family F only has links < 4) */ - fam0fWriteHTLinkCmdBufferAlloc(1, rsp1, 1, 0, 15, 0); - fam0fWriteHTLinkDatBufferAlloc(1, rsp1, 1, 1, 6); - - /* Node 0, is the third link non-coherent? */ - nclink = (u8)AmdBitScanReverse(((u8)0x07 & ~((u32)1 << req0) & ~((u32)1 << rsp0))); - if (nb->verifyLinkIsNonCoherent(0, nclink, nb)) - { - fam0fWriteHTLinkCmdBufferAlloc(0, nclink, 6, 5, 2, 0); - } - - /* Node 1, is the third link non-coherent? */ - nclink = (u8)AmdBitScanReverse(((u8)0x07 & ~((u32)1 << req1) & ~((u32)1 << rsp1))); - if (nb->verifyLinkIsNonCoherent(1, nclink, nb)) - { - fam0fWriteHTLinkCmdBufferAlloc(1, nclink, 6, 5, 2, 0); - } -#endif /* HT_BUILD_NC_ONLY */ -} - -/***************************************************************************//** - * - * static void - * fam0fBufferOptimizations(u8 node, sMainData *pDat, cNorthBridge *nb) - * - * Description: - * Buffer tunings are inherently northbridge specific. Check for specific configs - * which require adjustments and apply any standard workarounds to this node. - * - * Parameters: - * @param[in] node = the node to - * @param[in] *pDat = coherent links from node 0 to 1 - * @param[in] nb = this northbridge - * - ******************************************************************************/ -static void fam0fBufferOptimizations(u8 node, sMainData *pDat, cNorthBridge *nb) -{ -#ifndef HT_BUILD_NC_ONLY - u8 i; - u32 temp; - SBDFO currentPtr; - - ASSERT(node < nb->maxNodes); - - /* Fix the FIFO pointer register before changing speeds */ - currentPtr = MAKE_SBDFO(makePCISegmentFromNode(node), - makePCIBusFromNode(node), - makePCIDeviceFromNode(node), - CPU_NB_FUNC_03, - REG_NB_FIFOPTR_3XDC); - for (i = 0; i < nb->maxLinks; i++) - { - temp = 0; - if (nb->verifyLinkIsCoherent(node, i, nb)) - { - temp = 0x26; - ASSERT(i < 3); - AmdPCIWriteBits(currentPtr, 8*i + 5, 8*i, &temp); - } - else - { - if (nb->verifyLinkIsNonCoherent(node, i, nb)) - { - temp = 0x25; - ASSERT(i < 3); - AmdPCIWriteBits(currentPtr, 8*i + 5, 8*i, &temp); - } - } - } - /* - * 8P Buffer tuning. - * Either apply the BKDG tunings or, if applicable, apply the more restrictive errata 153 - * workaround. - * If 8 nodes, Check this node for 'inner' or 'outer'. - * Tune each link based on coherent or non-coherent - */ - if (pDat->NodesDiscovered >= 6) - { - u8 j; - BOOL isOuter; - BOOL isErrata153; - - /* This is for family 0Fh, so assuming dual core max then 7 or 8 nodes are required - * to be in the situation of 14 or more cores. We checked nodes above, cross check - * that the number of cores is 14 or more. We want both 14 cores with at least 7 or 8 nodes - * not one condition alone, to apply the errata 153 workaround. Otherwise, 7 or 8 rev F - * nodes use the BKDG tuning. - */ - - isErrata153 = 0; - - AmdPCIReadBits (MAKE_SBDFO(makePCISegmentFromNode(0), - makePCIBusFromNode(0), - makePCIDeviceFromNode(0), - CPU_HTNB_FUNC_00, - REG_NODE_ID_0X60), - 19, 16, &temp); - - if (temp >= 14) - { - /* Check whether we need to do errata 153 tuning or BKDG tuning. - * Errata 153 applies to JH-1, JH-2 and older. It is fixed in JH-3 - * (and, one assumes, from there on). - */ - for (i = 0; i < (pDat->NodesDiscovered +1); i++) - { - AmdPCIReadBits(MAKE_SBDFO(makePCISegmentFromNode(i), - makePCIBusFromNode(i), - makePCIDeviceFromNode(i), - CPU_NB_FUNC_03, - REG_NB_CPUID_3XFC), - 7, 0, &temp); - if (((u8)temp & ~0x40) < 0x13) - { - isErrata153 = 1; - break; - } - } - } - - for (i = 0; i < CPU_ADDR_NUM_CONFIG_MAPS; i++) - { - isOuter = FALSE; - /* Check for outer node by scanning the config maps on node 0 for one - * which is assigned to this node. - */ - currentPtr = MAKE_SBDFO(makePCISegmentFromNode(0), - makePCIBusFromNode(0), - makePCIDeviceFromNode(0), - CPU_ADDR_FUNC_01, - REG_ADDR_CONFIG_MAP0_1XE0 + (4 * i)); - AmdPCIReadBits (currentPtr, 1, 0, &temp); - /* Make sure this config map is valid, if it is it will be enabled for read/write */ - if (temp == 3) - { - /* It's valid, get the node (that node is an outer node) */ - AmdPCIReadBits (currentPtr, 6, 4, &temp); - /* Is the node we're working on now? */ - if (node == (u8)temp) - { - /* This is an outer node. Tune it appropriately. */ - for (j = 0; j < nb->maxLinks; j++) - { - if (isErrata153) - { - if (nb->verifyLinkIsCoherent(node, j, nb)) - { - fam0fWriteHTLinkCmdBufferAlloc(node, j, 1, 1, 6, 4); - } - else - { - if (nb->verifyLinkIsNonCoherent(node, j, nb)) - { - fam0fWriteHTLinkCmdBufferAlloc(node, j, 5, 4, 1, 0); - } - } - } - else - { - if (nb->verifyLinkIsCoherent(node, j, nb)) - { - fam0fWriteHTLinkCmdBufferAlloc(node, j, 1, 1, 8, 5); - } - } - } - /* - * SRI to XBAR Buffer Counts are correct for outer node at power on defaults. - */ - isOuter = TRUE; - break; - } - } - /* We fill config maps in ascending order, so if we didn't use this one, we're done. */ - else break; - } - if (!isOuter) - { - if (isErrata153) - { - /* Tuning for inner node coherent links */ - for (j = 0; j < nb->maxLinks; j++) - { - if (nb->verifyLinkIsCoherent(node, j, nb)) - { - fam0fWriteHTLinkCmdBufferAlloc(node, j, 2, 1, 5, 4); - } - - } - /* SRI to XBAR Buffer Count for inner nodes, zero DReq and DPReq */ - temp = 0; - AmdPCIWriteBits (MAKE_SBDFO(makePCISegmentFromNode(node), - makePCIBusFromNode(node), - makePCIDeviceFromNode(node), - CPU_NB_FUNC_03, - REG_NB_SRI_XBAR_BUF_3X70), - 31, 28, &temp); - } - } - - /* - * Tune MCT to XBAR Buffer Count the same an all nodes, 2 Probes, 5 Response - */ - if (isErrata153) - { - temp = 0x25; - AmdPCIWriteBits (MAKE_SBDFO(makePCISegmentFromNode(node), - makePCIBusFromNode(node), - makePCIDeviceFromNode(node), - CPU_NB_FUNC_03, - REG_NB_MCT_XBAR_BUF_3X78), - 14, 8, &temp); - } - } -#endif /* HT_BUILD_NC_ONLY */ -} - -/***************************************************************************//** - * - * static void - * fam10BufferOptimizations(u8 node, sMainData *pDat, cNorthBridge *nb) - * - * Description: - * Buffer tunings are inherently northbridge specific. Check for specific configs - * which require adjustments and apply any standard workarounds to this node. - * - * Parameters: - * @param[in] node = the node to tune - * @param[in] *pDat = global state - * @param[in] nb = this northbridge - * - ******************************************************************************/ -static void fam10BufferOptimizations(u8 node, sMainData *pDat, cNorthBridge *nb) -{ - u32 temp; - SBDFO currentPtr; - u8 i; - - ASSERT(node < nb->maxNodes); - - /* - * Link to XCS Token Count Tuning - * - * For each active link that we reganged (so this unfortunately can't go into the PCI reg - * table), we have to switch the Link to XCS Token Counts to the ganged state. - * We do this here for the non-uma case, which is to write the values that would have - * been power on defaults if the link was ganged at cold reset. - */ - for (i = 0; i < pDat->TotalLinks*2; i++) - { - if ((pDat->PortList[i].NodeID == node) && (pDat->PortList[i].Type == PORTLIST_TYPE_CPU)) - { - /* If the link is greater than 4, this is a sublink 1, so it is not reganged. */ - if (pDat->PortList[i].Link < 4) - { - currentPtr = MAKE_SBDFO(makePCISegmentFromNode(node), - makePCIBusFromNode(node), - makePCIDeviceFromNode(node), - CPU_NB_FUNC_03, - REG_NB_LINK_XCS_TOKEN0_3X148 + 4*pDat->PortList[i].Link); - if (pDat->PortList[i].SelRegang) - { - /* Handle all the regang Token count adjustments */ - - /* Sublink 0: [Probe0tok] = 2 [Rsp0tok] = 2 [PReq0tok] = 2 [Req0tok] = 2 */ - temp = 0xAA; - AmdPCIWriteBits(currentPtr, 7, 0, &temp); - /* Sublink 1: [Probe1tok] = 0 [Rsp1tok] = 0 [PReq1tok] = 0 [Req1tok] = 0 */ - temp = 0; - AmdPCIWriteBits(currentPtr, 23, 16, &temp); - /* [FreeTok] = 3 */ - temp = 3; - AmdPCIWriteBits(currentPtr, 15, 14, &temp); - } - else - { - /* Read the regang bit in hardware */ - AmdPCIReadBits(MAKE_SBDFO(makePCISegmentFromNode(pDat->PortList[i].NodeID), - makePCIBusFromNode(pDat->PortList[i].NodeID), - makePCIDeviceFromNode(pDat->PortList[i].NodeID), - CPU_HTNB_FUNC_00, - REG_HT_LINK_EXT_CONTROL0_0X170 + 4*pDat->PortList[i].Link), - 0, 0, &temp); - if (temp == 1) - { - /* handle a minor adjustment for stapped ganged links. If SelRegang is false we - * didn't do the regang, so if the bit is on then it's hardware strapped. - */ - - /* [FreeTok] = 3 */ - temp = 3; - AmdPCIWriteBits(currentPtr, 15, 14, &temp); - } - } - } - } - } -} - -/***************************************************************************//** - * - * static void - * fam15BufferOptimizations(u8 node, sMainData *pDat, cNorthBridge *nb) - * - * Description: - * Buffer tunings are inherently northbridge specific. Check for specific configs - * which require adjustments and apply any standard workarounds to this node. - * - * Parameters: - * @param[in] node = the node to tune - * @param[in] *pDat = global state - * @param[in] nb = this northbridge - * - ******************************************************************************/ -static void fam15BufferOptimizations(u8 node, sMainData *pDat, cNorthBridge *nb) -{ - /* Buffer count setup on Family 15h is currently handled in cpuSetAMDPCI */ -} - -/* - * North Bridge 'constructor'. - * - */ - -/***************************************************************************//** - * - * void - * newNorthBridge(u8 node, cNorthBridge *nb) - * - * Description: - * Construct a new northbridge. This routine encapsulates knowledge of how to tell - * significant differences between families of supported northbridges and what routines - * can be used in common and which are unique. A fully populated northbridge interface - * is provided by nb. - * - * Parameters: - * @param node - * @param[out] nb = the caller's northbridge structure to initialize. - * - ******************************************************************************/ -void newNorthBridge(u8 node, cNorthBridge *nb) -{ - u32 match; - u32 extFam, baseFam, model; - - cNorthBridge fam15 = - { -#ifdef HT_BUILD_NC_ONLY - 8, - 1, - 12, -#else - 8, - 8, - 64, -#endif /* HT_BUILD_NC_ONLY*/ - writeRoutingTable, - writeNodeID, - readDefLnk, - enableRoutingTables, - verifyLinkIsCoherent, - readTrueLinkFailStatus, - readToken, - writeToken, - fam15GetNumCoresOnNode, - setTotalNodesAndCores, - limitNodes, - writeFullRoutingTable, - isCompatible, - fam15IsCapable, - (void (*)(u8, u8, cNorthBridge*))commonVoid, - (BOOL (*)(u8, u8, sMainData*, cNorthBridge*))commonReturnFalse, - readSbLink, - verifyLinkIsNonCoherent, - ht3SetCFGAddrMap, - convertBitsToWidth, - convertWidthToBits, - fam15NorthBridgeFreqMask, - gatherLinkData, - setLinkData, - ht3WriteTrafficDistribution, - fam15BufferOptimizations, - 0x00000001, - 0x00000200, - 18, - 0x00000f06 - }; - - cNorthBridge fam10 = - { -#ifdef HT_BUILD_NC_ONLY - 8, - 1, - 12, -#else - 8, - 8, - 64, -#endif /* HT_BUILD_NC_ONLY*/ - writeRoutingTable, - writeNodeID, - readDefLnk, - enableRoutingTables, - verifyLinkIsCoherent, - readTrueLinkFailStatus, - readToken, - writeToken, - fam10GetNumCoresOnNode, - setTotalNodesAndCores, - limitNodes, - writeFullRoutingTable, - isCompatible, - fam10IsCapable, - (void (*)(u8, u8, cNorthBridge*))commonVoid, - (BOOL (*)(u8, u8, sMainData*, cNorthBridge*))commonReturnFalse, - readSbLink, - verifyLinkIsNonCoherent, - ht3SetCFGAddrMap, - convertBitsToWidth, - convertWidthToBits, - fam10NorthBridgeFreqMask, - gatherLinkData, - setLinkData, - ht3WriteTrafficDistribution, - fam10BufferOptimizations, - 0x00000001, - 0x00000200, - 18, - 0x00000f01 - }; - - cNorthBridge fam0f = - { -#ifdef HT_BUILD_NC_ONLY - 3, - 1, - 12, -#else - 3, - 8, - 32, -#endif /* HT_BUILD_NC_ONLY*/ - writeRoutingTable, - writeNodeID, - readDefLnk, - enableRoutingTables, - verifyLinkIsCoherent, - readTrueLinkFailStatus, - readToken, - writeToken, - fam0FGetNumCoresOnNode, - setTotalNodesAndCores, - limitNodes, - writeFullRoutingTable, - isCompatible, - fam0fIsCapable, - fam0fStopLink, - (BOOL (*)(u8, u8, sMainData*, cNorthBridge*))commonReturnFalse, - readSbLink, - verifyLinkIsNonCoherent, - ht1SetCFGAddrMap, - convertBitsToWidth, - convertWidthToBits, - ht1NorthBridgeFreqMask, - gatherLinkData, - setLinkData, - ht1WriteTrafficDistribution, - fam0fBufferOptimizations, - 0x00000001, - 0x00000100, - 16, - 0x00000f00 - }; - - /* Start with enough of the key to identify the northbridge interface */ - AmdPCIReadBits(MAKE_SBDFO(makePCISegmentFromNode(node), - makePCIBusFromNode(node), - makePCIDeviceFromNode(node), - CPU_NB_FUNC_03, - REG_NB_CPUID_3XFC), - 27, 20, &extFam); - AmdPCIReadBits(MAKE_SBDFO(makePCISegmentFromNode(node), - makePCIBusFromNode(node), - makePCIDeviceFromNode(node), - CPU_NB_FUNC_03, - REG_NB_CPUID_3XFC), - 11, 8, &baseFam); - AmdPCIReadBits(MAKE_SBDFO(makePCISegmentFromNode(node), - makePCIBusFromNode(node), - makePCIDeviceFromNode(node), - CPU_NB_FUNC_03, - REG_NB_CPUID_3XFC), - 7, 4, &model); - match = (u32)((baseFam << 8) | extFam); - - /* Test each in turn looking for a match. - * Initialize the struct if found. - */ - if (match == fam15.compatibleKey) - { - Amdmemcpy((void *)nb, (const void *)&fam15, (u32) sizeof(cNorthBridge)); - } - else if (match == fam10.compatibleKey) - { - Amdmemcpy((void *)nb, (const void *)&fam10, (u32) sizeof(cNorthBridge)); - } - else - { - if (match == fam0f.compatibleKey) - { - Amdmemcpy((void *)nb, (const void *)&fam0f, (u32) sizeof(cNorthBridge)); - } - else - { - STOP_HERE; - } - } - - /* Update the initial limited key to the real one, which may include other matching info */ - nb->compatibleKey = makeKey(node); -} diff --git a/src/northbridge/amd/amdht/h3ncmn.h b/src/northbridge/amd/amdht/h3ncmn.h deleted file mode 100644 index db057c0f1c..0000000000 --- a/src/northbridge/amd/amdht/h3ncmn.h +++ /dev/null @@ -1,115 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007 Advanced Micro Devices, Inc. - * Copyright (C) 2015 Timothy Pearson , Raptor Engineering - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef H3NCMN_H -#define H3NCMN_H - -#include -#include -#include - -#include "comlib.h" -#include "h3finit.h" -#include "h3ffeat.h" - -/* Use a macro to convert a node number to a PCI device. If some future port of - * this code needs to, this can easily be replaced by a function call: - * u8 makePCIDeviceFromNode(u8 node); - */ -#define makePCIDeviceFromNode(node) \ - ((u8)(24 + node)) - -/* Use a macro to convert a node number to a PCI bus. If some future port of - * this code needs to, this can easily be replaced by a function call: - * u8 makePCIBusFromNode(u8 node); - */ -#define makePCIBusFromNode(node) \ - ((u8)(0)) - -/* Use a macro to convert a node number to a PCI Segment. If some future port of - * this code needs to, this can easily be replaced by a function call: - * u8 makePCISegmentFromNode(u8 node); - */ -#define makePCISegmentFromNode(node) \ - ((u8)(0)) - -/* Macros to fix support issues that come up with early sample processors, which - * sometimes do things like report capabilities that are actually unsupported. - * Use the build flag, HT_BUILD_EARLY_SAMPLE_CPU_SUPPORT, to enable this support. - * - * It's not envisioned this would be replaced by an external function, but the prototype is - * u16 fixEarlySampleFreqCapability(u16 fc); - */ -#ifndef HT_BUILD_EARLY_SAMPLE_CPU_SUPPORT -#define fixEarlySampleFreqCapability(fc) \ - ((u16)fc) -#else -#define fixEarlySampleFreqCapability(fc) \ - ((u16)fc & HT_FREQUENCY_LIMIT_HT1_ONLY) -#endif - -struct cNorthBridge -{ - /* Public data, clients of northbridge can access */ - u8 maxLinks; - u8 maxNodes; - u8 maxPlatformLinks; - - /* Public Interfaces for northbridge clients, coherent init*/ - void (*writeRoutingTable)(u8 node, u8 target, u8 link, cNorthBridge *nb); - void (*writeNodeID)(u8 node, u8 nodeID, cNorthBridge *nb); - u8 (*readDefLnk)(u8 node, cNorthBridge *nb); - void (*enableRoutingTables)(u8 node, cNorthBridge *nb); - BOOL (*verifyLinkIsCoherent)(u8 node, u8 link, cNorthBridge *nb); - BOOL (*readTrueLinkFailStatus)(u8 node, u8 link, sMainData *pDat, cNorthBridge *nb); - u8 (*readToken)(u8 node, cNorthBridge *nb); - void (*writeToken)(u8 node, u8 value, cNorthBridge *nb); - u8 (*getNumCoresOnNode)(u8 node, cNorthBridge *nb); - void (*setTotalNodesAndCores)(u8 node, u8 totalNodes, u8 totalCores, cNorthBridge *nb); - void (*limitNodes)(u8 node, cNorthBridge *nb); - void (*writeFullRoutingTable)(u8 node, u8 target, u8 reqLink, u8 rspLink, u32 bClinks, cNorthBridge *nb); - BOOL (*isCompatible)(u8 node, cNorthBridge *nb); - BOOL (*isCapable)(u8 node, sMainData *pDat, cNorthBridge *nb); - void (*stopLink)(u8 node, u8 link, cNorthBridge *nb); - BOOL (*handleSpecialLinkCase)(u8 node, u8 link, sMainData *pDat, cNorthBridge *nb); - - /* Public Interfaces for northbridge clients, noncoherent init */ - u8 (*readSbLink)(cNorthBridge *nb); - BOOL (*verifyLinkIsNonCoherent)(u8 node, u8 link, cNorthBridge *nb); - void (*setCFGAddrMap)(u8 cfgMapIndex, u8 secBus, u8 subBus, u8 targetNode, u8 targetLink, sMainData *pDat, cNorthBridge *nb); - - /* Public Interfaces for northbridge clients, Optimization */ - u8 (*convertBitsToWidth)(u8 value, cNorthBridge *nb); - u8 (*convertWidthToBits)(u8 value, cNorthBridge *nb); - uint32_t (*northBridgeFreqMask)(u8 node, cNorthBridge *nb); - void (*gatherLinkData)(sMainData *pDat, cNorthBridge *nb); - void (*setLinkData)(sMainData *pDat, cNorthBridge *nb); - - /* Public Interfaces for northbridge clients, System and performance Tuning. */ - void (*writeTrafficDistribution)(u32 links01, u32 links10, cNorthBridge *nb); - void (*bufferOptimizations)(u8 node, sMainData *pDat, cNorthBridge *nb); - - /* Private Data for northbridge implementation use only */ - u32 selfRouteRequestMask; - u32 selfRouteResponseMask; - u8 broadcastSelfBit; - u32 compatibleKey; -} ; - -void newNorthBridge(u8 node, cNorthBridge *nb); -uint8_t is_gt_rev_d(void); - -#endif /* H3NCMN_H */ diff --git a/src/northbridge/amd/amdht/ht_wrapper.c b/src/northbridge/amd/amdht/ht_wrapper.c deleted file mode 100644 index 89ff46eae3..0000000000 --- a/src/northbridge/amd/amdht/ht_wrapper.c +++ /dev/null @@ -1,384 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2015 Timothy Pearson , Raptor Engineering - * Copyright (C) 2007-2008 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include -#include -#include "ht_wrapper.h" - -/*---------------------------------------------------------------------------- - * TYPEDEFS, DEFINITIONS AND MACROS - * - *---------------------------------------------------------------------------- - */ - -/* Single CPU system? */ -#if (CONFIG_MAX_PHYSICAL_CPUS == 1) - /* FIXME - * This #define is used by other #included .c files - * When set, multiprocessor support is completely disabled - */ - #define HT_BUILD_NC_ONLY 1 -#endif - -/* Debugging Options */ -//#define AMD_DEBUG_ERROR_STOP 1 - -/*---------------------------------------------------------------------------- - * MODULES USED - * - *---------------------------------------------------------------------------- - */ - -#include "comlib.h" -#include "h3gtopo.h" -#include "h3finit.h" - -/*---------------------------------------------------------------------------- - * LOCAL FUNCTIONS - * - *---------------------------------------------------------------------------- - */ - -static const char * event_class_string_decodes[] = { - [HT_EVENT_CLASS_CRITICAL] = "CRITICAL", - [HT_EVENT_CLASS_ERROR] = "ERROR", - [HT_EVENT_CLASS_HW_FAULT] = "HARDWARE FAULT", - [HT_EVENT_CLASS_WARNING] = "WARNING", - [HT_EVENT_CLASS_INFO] = "INFO" -}; - -typedef struct { - uint32_t code; - const char *string; -} event_string_decode_t; - -static const event_string_decode_t event_string_decodes[] = { - { HT_EVENT_COH_EVENTS, "HT_EVENT_COH_EVENTS" }, - { HT_EVENT_COH_NO_TOPOLOGY, "HT_EVENT_COH_NO_TOPOLOGY" }, - { HT_EVENT_COH_LINK_EXCEED, "HT_EVENT_COH_LINK_EXCEED" }, - { HT_EVENT_COH_FAMILY_FEUD, "HT_EVENT_COH_FAMILY_FEUD" }, - { HT_EVENT_COH_NODE_DISCOVERED, "HT_EVENT_COH_NODE_DISCOVERED" }, - { HT_EVENT_COH_MPCAP_MISMATCH, "HT_EVENT_COH_MPCAP_MISMATCH" }, - { HT_EVENT_NCOH_EVENTS, "HT_EVENT_NCOH_EVENTS" }, - { HT_EVENT_NCOH_BUID_EXCEED, "HT_EVENT_NCOH_BUID_EXCEED" }, - { HT_EVENT_NCOH_LINK_EXCEED, "HT_EVENT_NCOH_LINK_EXCEED" }, - { HT_EVENT_NCOH_BUS_MAX_EXCEED, "HT_EVENT_NCOH_BUS_MAX_EXCEED" }, - { HT_EVENT_NCOH_CFG_MAP_EXCEED, "HT_EVENT_NCOH_CFG_MAP_EXCEED" }, - { HT_EVENT_NCOH_DEVICE_FAILED, "HT_EVENT_NCOH_DEVICE_FAILED" }, - { HT_EVENT_NCOH_AUTO_DEPTH, "HT_EVENT_NCOH_AUTO_DEPTH" }, - { HT_EVENT_OPT_EVENTS, "HT_EVENT_OPT_EVENTS" }, - { HT_EVENT_OPT_REQUIRED_CAP_RETRY, "HT_EVENT_OPT_REQUIRED_CAP_RETRY" }, - { HT_EVENT_OPT_REQUIRED_CAP_GEN3, "HT_EVENT_OPT_REQUIRED_CAP_GEN3" }, - { HT_EVENT_HW_EVENTS, "HT_EVENT_HW_EVENTS" }, - { HT_EVENT_HW_SYNCHFLOOD, "HT_EVENT_HW_SYNCHFLOOD" }, - { HT_EVENT_HW_HTCRC, "HT_EVENT_HW_HTCRC" } -}; - -static const char *event_string_decode(uint32_t event) -{ - uint32_t i; - for (i = 0; i < ARRAY_SIZE(event_string_decodes); i++) - if (event_string_decodes[i].code == event) - break; - if (i == ARRAY_SIZE(event_string_decodes)) - return "ERROR: Unmatched event code! " - "Did you forget to update event_string_decodes[]?"; - return event_string_decodes[i].string; -} - -/** - * void AMD_CB_EventNotify (u8 evtClass, u16 event, const u8 *pEventData0) - */ -static void AMD_CB_EventNotify (u8 evtClass, u16 event, const u8 *pEventData0) -{ - uint8_t i; - uint8_t log_level; - uint8_t dump_event_detail; - - printk(BIOS_DEBUG, "%s: ", __func__); - - /* Decode event */ - dump_event_detail = 1; - switch (evtClass) { - case HT_EVENT_CLASS_CRITICAL: - case HT_EVENT_CLASS_ERROR: - case HT_EVENT_CLASS_HW_FAULT: - case HT_EVENT_CLASS_WARNING: - case HT_EVENT_CLASS_INFO: - log_level = BIOS_DEBUG; - printk(log_level, "%s", event_class_string_decodes[evtClass]); - break; - default: - log_level = BIOS_DEBUG; - printk(log_level, "UNKNOWN"); - break; - } - printk(log_level, ": "); - - switch (event) { - case HT_EVENT_COH_EVENTS: - case HT_EVENT_COH_NO_TOPOLOGY: - case HT_EVENT_COH_LINK_EXCEED: - case HT_EVENT_COH_FAMILY_FEUD: - printk(log_level, "%s", event_string_decode(event)); - break; - case HT_EVENT_COH_NODE_DISCOVERED: - { - printk(log_level, "HT_EVENT_COH_NODE_DISCOVERED"); - sHtEventCohNodeDiscovered *evt = (sHtEventCohNodeDiscovered*)pEventData0; - printk(log_level, ": node %d link %d new node: %d", - evt->node, evt->link, evt->newNode); - dump_event_detail = 0; - break; - } - case HT_EVENT_COH_MPCAP_MISMATCH: - case HT_EVENT_NCOH_EVENTS: - case HT_EVENT_NCOH_BUID_EXCEED: - case HT_EVENT_NCOH_LINK_EXCEED: - case HT_EVENT_NCOH_BUS_MAX_EXCEED: - case HT_EVENT_NCOH_CFG_MAP_EXCEED: - printk(log_level, "%s", event_string_decode(event)); - break; - case HT_EVENT_NCOH_DEVICE_FAILED: - { - printk(log_level, "%s", event_string_decode(event)); - sHtEventNcohDeviceFailed *evt = (sHtEventNcohDeviceFailed*)pEventData0; - printk(log_level, ": node %d link %d depth: %d attemptedBUID: %d", - evt->node, evt->link, evt->depth, evt->attemptedBUID); - dump_event_detail = 0; - break; - } - case HT_EVENT_NCOH_AUTO_DEPTH: - { - printk(log_level, "%s", event_string_decode(event)); - sHtEventNcohAutoDepth *evt = (sHtEventNcohAutoDepth*)pEventData0; - printk(log_level, ": node %d link %d depth: %d", - evt->node, evt->link, evt->depth); - dump_event_detail = 0; - break; - } - case HT_EVENT_OPT_EVENTS: - case HT_EVENT_OPT_REQUIRED_CAP_RETRY: - case HT_EVENT_OPT_REQUIRED_CAP_GEN3: - case HT_EVENT_HW_EVENTS: - case HT_EVENT_HW_SYNCHFLOOD: - case HT_EVENT_HW_HTCRC: - printk(log_level, "%s", event_string_decode(event)); - break; - default: - printk(log_level, "HT_EVENT_UNKNOWN"); - break; - } - printk(log_level, "\n"); - - if (dump_event_detail) { - printk(BIOS_DEBUG, " event class: %02x\n event: %04x\n data: ", evtClass, event); - - for (i = 0; i < *pEventData0; i++) { - printk(BIOS_DEBUG, " %02x ", *(pEventData0 + i)); - } - printk(BIOS_DEBUG, "\n"); - } -} - -/** - * void getAmdTopolist(u8 ***p) - * - * point to the stock topo list array - * - */ -void getAmdTopolist(u8 ***p) -{ - *p = (u8 **)amd_topo_list; -} - -/** - * BOOL AMD_CB_IgnoreLink(u8 Node, u8 Link) - * Description: - * This routine is used to ignore connected yet faulty HT links, - * such as those present in a G34 processor package. - * - * Parameters: - * @param[in] node = The node on which this chain is located - * @param[in] link = The link on the host for this chain - */ -static BOOL AMD_CB_IgnoreLink (u8 node, u8 link) -{ - return 0; -} - -/** - * void amd_ht_init(struct sys_info *sysinfo) - * - * AMD HT init coreboot wrapper - * - */ -void amd_ht_init(struct sys_info *sysinfo) -{ - - if (!sysinfo) { - printk(BIOS_DEBUG, "Skipping %s\n", __func__); - return; - } - - AMD_HTBLOCK ht_wrapper = { - NULL, // u8 **topolist; - 0, // u8 AutoBusStart; - 32, // u8 AutoBusMax; - 6, // u8 AutoBusIncrement; - AMD_CB_IgnoreLink, // BOOL (*AMD_CB_IgnoreLink)(); - NULL, // BOOL (*AMD_CB_OverrideBusNumbers)(); - AMD_CB_ManualBUIDSwapList, // BOOL (*AMD_CB_ManualBUIDSwapList)(); - NULL, // void (*AMD_CB_DeviceCapOverride)(); - NULL, // void (*AMD_CB_Cpu2CpuPCBLimits)(); - NULL, // void (*AMD_CB_IOPCBLimits)(); - NULL, // BOOL (*AMD_CB_SkipRegang)(); - NULL, // BOOL (*AMD_CB_CustomizeTrafficDistribution)(); - NULL, // BOOL (*AMD_CB_CustomizeBuffers)(); - NULL, // void (*AMD_CB_OverrideDevicePort)(); - NULL, // void (*AMD_CB_OverrideCpuPort)(); - AMD_CB_EventNotify, // void (*AMD_CB_EventNotify) (); - &sysinfo->ht_link_cfg // struct ht_link_config* - }; - - printk(BIOS_DEBUG, "Enter %s\n", __func__); - amdHtInitialize(&ht_wrapper); - printk(BIOS_DEBUG, "Exit %s\n", __func__); -} - -/** - * void amd_ht_fixup(struct sys_info *sysinfo) - * - * AMD HT fixup - * - */ -void amd_ht_fixup(struct sys_info *sysinfo) { - printk(BIOS_DEBUG, "%s\n", __func__); - if (CONFIG(CPU_AMD_MODEL_10XXX)) { - uint8_t rev_gte_d = 0; - uint8_t fam15h = 0; - uint8_t dual_node = 0; - uint32_t f3xe8; - uint32_t family; - uint32_t model; - - family = model = cpuid_eax(0x80000001); - model = ((model & 0xf0000) >> 12) | ((model & 0xf0) >> 4); - family = ((family & 0xf00000) >> 16) | ((family & 0xf00) >> 8); - - if (family >= 0x6f) - /* Family 15h or later */ - fam15h = 1; - - if ((model >= 0x8) || fam15h) - /* Family 10h Revision D or later */ - rev_gte_d = 1; - - if (rev_gte_d) { - f3xe8 = pci_read_config32(NODE_PCI(0, 3), 0xe8); - - /* Check for dual node capability */ - if (f3xe8 & 0x20000000) - dual_node = 1; - - if (dual_node) { - /* Each G34 processor contains a defective HT link. - * See the Family 10h BKDG Rev 3.62 section 2.7.1.5 for details - * For Family 15h see the BKDG Rev. 3.14 section 2.12.1.5 for details. - */ - uint8_t node; - uint8_t node_count = get_nodes(); - uint32_t dword; - for (node = 0; node < node_count; node++) { - f3xe8 = pci_read_config32(NODE_PCI(node, 3), 0xe8); - uint8_t internal_node_number = ((f3xe8 & 0xc0000000) >> 30); - printk(BIOS_DEBUG, - "%s: node %d (internal node " - "ID %d): disabling defective " - "HT link", __func__, node, - internal_node_number); - if (internal_node_number == 0) { - uint8_t package_link_3_connected = pci_read_config32(NODE_PCI(node, 0), (fam15h)?0x98:0xd8) & 0x1; - printk(BIOS_DEBUG, " (L3 connected: %d)\n", package_link_3_connected); - if (package_link_3_connected) { - /* Set WidthIn and WidthOut to 0 */ - dword = pci_read_config32(NODE_PCI(node, 0), (fam15h)?0x84:0xc4); - dword &= ~0x77000000; - pci_write_config32(NODE_PCI(node, 0), (fam15h)?0x84:0xc4, dword); - /* Set Ganged to 1 */ - dword = pci_read_config32(NODE_PCI(node, 0), (fam15h)?0x170:0x178); - dword |= 0x00000001; - pci_write_config32(NODE_PCI(node, 0), (fam15h)?0x170:0x178, dword); - } else { - /* Set ConnDly to 1 */ - dword = pci_read_config32(NODE_PCI(node, 0), 0x16c); - dword |= 0x00000100; - pci_write_config32(NODE_PCI(node, 0), 0x16c, dword); - /* Set TransOff and EndOfChain to 1 */ - dword = pci_read_config32(NODE_PCI(node, 4), (fam15h)?0x84:0xc4); - dword |= 0x000000c0; - pci_write_config32(NODE_PCI(node, 4), (fam15h)?0x84:0xc4, dword); - } - } else if (internal_node_number == 1) { - uint8_t package_link_3_connected = pci_read_config32(NODE_PCI(node, 0), (fam15h)?0xf8:0xb8) & 0x1; - printk(BIOS_DEBUG, " (L3 connected: %d)\n", package_link_3_connected); - if (package_link_3_connected) { - /* Set WidthIn and WidthOut to 0 */ - dword = pci_read_config32(NODE_PCI(node, 0), (fam15h)?0xe4:0xa4); - dword &= ~0x77000000; - pci_write_config32(NODE_PCI(node, 0), (fam15h)?0xe4:0xa4, dword); - /* Set Ganged to 1 */ - /* WARNING - * The Family 15h BKDG states that 0x18c should be set, - * however this is in error. 0x17c is the correct control - * register (sublink 0) for these processors... - */ - dword = pci_read_config32(NODE_PCI(node, 0), (fam15h)?0x17c:0x174); - dword |= 0x00000001; - pci_write_config32(NODE_PCI(node, 0), (fam15h)?0x17c:0x174, dword); - } else { - /* Set ConnDly to 1 */ - dword = pci_read_config32(NODE_PCI(node, 0), 0x16c); - dword |= 0x00000100; - pci_write_config32(NODE_PCI(node, 0), 0x16c, dword); - /* Set TransOff and EndOfChain to 1 */ - dword = pci_read_config32(NODE_PCI(node, 4), (fam15h)?0xe4:0xa4); - dword |= 0x000000c0; - pci_write_config32(NODE_PCI(node, 4), (fam15h)?0xe4:0xa4, dword); - } - } - } - } - } - } -} - -u32 get_nodes(void) -{ - pci_devfn_t dev; - u32 nodes; - - dev = PCI_DEV(CONFIG_CBB, CONFIG_CDB, 0); - nodes = ((pci_read_config32(dev, 0x60)>>4) & 7); -#if CONFIG_MAX_PHYSICAL_CPUS > 8 - nodes += (((pci_read_config32(dev, 0x160)>>4) & 7)<<3); -#endif - nodes++; - - return nodes; -} diff --git a/src/northbridge/amd/amdht/ht_wrapper.h b/src/northbridge/amd/amdht/ht_wrapper.h deleted file mode 100644 index 629e08f4fe..0000000000 --- a/src/northbridge/amd/amdht/ht_wrapper.h +++ /dev/null @@ -1,28 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2015 Timothy Pearson , Raptor Engineering - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef AMD_HT_WRAPPER_H -#define AMD_HT_WRAPPER_H - -#include -#include -#include -#include "h3finit.h" - -void amd_ht_fixup(struct sys_info *sysinfo); -u32 get_nodes(void); -void amd_ht_init(struct sys_info *sysinfo); - -#endif diff --git a/src/northbridge/amd/amdht/porting.h b/src/northbridge/amd/amdht/porting.h deleted file mode 100644 index 9058d4d0e1..0000000000 --- a/src/northbridge/amd/amdht/porting.h +++ /dev/null @@ -1,79 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef PORTING_H -#define PORTING_H - - -/* For AMD64 or 32-bit GCC */ -typedef int int32; -typedef unsigned int uint32; -typedef short int16; -typedef unsigned short uint16; -typedef char int8; -typedef unsigned char uint8; - -/* Create the Boolean type */ -#define TRUE 1 -#define FALSE 0 -typedef unsigned char BOOL; - -/* Force tight packing of structures */ -#pragma pack(1) - -#define CALLCONV - - -typedef struct _uint64 -{ - uint32 lo; - uint32 hi; -}uint64; - - -/* - * SBDFO - Segment Bus Device Function Offset - * 31:28 Segment (4-bits) - * 27:20 Bus (8-bits) - * 19:15 Device (5-bits) - * 14:12 Function(3-bits) - * 11:00 Offset (12-bits) - */ -typedef uint32 SBDFO; - -#define MAKE_SBDFO(seg,bus,dev,fun,off) ((((uint32)(seg))<<28) | (((uint32)(bus))<<20) | \ - (((uint32)(dev))<<15) | (((uint32)(fun))<<12) | ((uint32)(off))) -#define SBDFO_SEG(x) (((uint32)(x)>>28) & 0x0F) -#define SBDFO_BUS(x) (((uint32)(x)>>20) & 0xFF) -#define SBDFO_DEV(x) (((uint32)(x)>>15) & 0x1F) -#define SBDFO_FUN(x) (((uint32)(x)>>12) & 0x07) -#define SBDFO_OFF(x) (((uint32)(x)) & 0xFFF) -#define ILLEGAL_SBDFO 0xFFFFFFFF - -void CALLCONV AmdMSRRead(uint32 Address, uint64 *Value); -void CALLCONV AmdMSRWrite(uint32 Address, uint64 *Value); -void CALLCONV AmdIORead(uint8 IOSize, uint16 Address, uint32 *Value); -void CALLCONV AmdIOWrite(uint8 IOSize, uint16 Address, uint32 *Value); -void CALLCONV AmdMemRead(uint8 MemSize, uint64 *Address, uint32 *Value); -void CALLCONV AmdMemWrite(uint8 MemSize, uint64 *Address, uint32 *Value); -void CALLCONV AmdPCIRead(SBDFO loc, uint32 *Value); -void CALLCONV AmdPCIWrite(SBDFO loc, uint32 *Value); -void CALLCONV AmdCPUIDRead(uint32 Address, uint32 Regs[4]); - -#define BYTESIZE 1 -#define WORDSIZE 2 -#define DWORDSIZE 4 - -#endif /* PORTING_H */ diff --git a/src/northbridge/amd/amdk8/amdk8.h b/src/northbridge/amd/amdk8/amdk8.h deleted file mode 100644 index 2b821b7c9e..0000000000 --- a/src/northbridge/amd/amdk8/amdk8.h +++ /dev/null @@ -1,31 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef AMDK8_H -#define AMDK8_H - -#define HT_INIT_CONTROL 0x6C -#define HTIC_ColdR_Detect (1<<4) -#define HTIC_BIOSR_Detect (1<<5) -#define HTIC_INIT_Detect (1<<6) - -#define NODE_HT(x) PCI_DEV(0,24+x,0) -#define NODE_MP(x) PCI_DEV(0,24+x,1) -#define NODE_MC(x) PCI_DEV(0,24+x,3) - -void set_bios_reset(void); -void distinguish_cpu_resets(unsigned int nodeid); -unsigned int get_sblk(void); -unsigned int get_sbbusn(unsigned int sblk); - -#endif /* AMDK8_H */ diff --git a/src/northbridge/amd/amdk8/reset_test.c b/src/northbridge/amd/amdk8/reset_test.c deleted file mode 100644 index 214aed448a..0000000000 --- a/src/northbridge/amd/amdk8/reset_test.c +++ /dev/null @@ -1,94 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include -#include "amdk8.h" - -static inline int cpu_init_detected(unsigned int nodeid) -{ - u32 htic; - pci_devfn_t dev; - - dev = PCI_DEV(0, 0x18 + nodeid, 0); - htic = pci_io_read_config32(dev, HT_INIT_CONTROL); - - return !!(htic & HTIC_INIT_Detect); -} - -static inline int bios_reset_detected(void) -{ - u32 htic; - htic = pci_io_read_config32(PCI_DEV(0, 0x18, 0), HT_INIT_CONTROL); - - return (htic & HTIC_ColdR_Detect) && !(htic & HTIC_BIOSR_Detect); -} - -static inline int cold_reset_detected(void) -{ - u32 htic; - htic = pci_io_read_config32(PCI_DEV(0, 0x18, 0), HT_INIT_CONTROL); - - return !(htic & HTIC_ColdR_Detect); -} - -void distinguish_cpu_resets(unsigned int nodeid) -{ - u32 htic; - pci_devfn_t device; - device = PCI_DEV(0, 0x18 + nodeid, 0); - htic = pci_io_read_config32(device, HT_INIT_CONTROL); - htic |= HTIC_ColdR_Detect | HTIC_BIOSR_Detect | HTIC_INIT_Detect; - pci_io_write_config32(device, HT_INIT_CONTROL, htic); -} - -void set_bios_reset(void) -{ - u32 htic; - htic = pci_io_read_config32(PCI_DEV(0, 0x18, 0), HT_INIT_CONTROL); - htic &= ~HTIC_BIOSR_Detect; - pci_io_write_config32(PCI_DEV(0, 0x18, 0), HT_INIT_CONTROL, htic); -} - -static unsigned int node_link_to_bus(unsigned int node, unsigned int link) -{ - u8 reg; - - for (reg = 0xE0; reg < 0xF0; reg += 0x04) { - u32 config_map; - config_map = pci_io_read_config32(PCI_DEV(0, 0x18, 1), reg); - if ((config_map & 3) != 3) { - continue; - } - if ((((config_map >> 4) & 7) == node) && - (((config_map >> 8) & 3) == link)) - { - return (config_map >> 16) & 0xff; - } - } - return 0; -} - -unsigned int get_sblk(void) -{ - u32 reg; - /* read PCI_DEV(0,0x18,0) 0x64 bit [8:9] to find out SbLink m */ - reg = pci_io_read_config32(PCI_DEV(0, 0x18, 0), 0x64); - return ((reg>>8) & 3); -} - -unsigned int get_sbbusn(unsigned int sblk) -{ - return node_link_to_bus(0, sblk); -} diff --git a/src/northbridge/amd/amdmct/amddefs.h b/src/northbridge/amd/amdmct/amddefs.h deleted file mode 100644 index 1a442082ff..0000000000 --- a/src/northbridge/amd/amdmct/amddefs.h +++ /dev/null @@ -1,158 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007-2008 Advanced Micro Devices, Inc. - * Copyright (C) 2015 Timothy Pearson , Raptor Engineering - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ -#ifndef AMDDEFS_H -#define AMDDEFS_H - -/* FIXME: this file should be moved to include/cpu/amd/amddefs.h */ - -/* Public Revisions - USE THESE VERSIONS TO MAKE COMPARE WITH CPULOGICALID RETURN VALUE*/ -#define AMD_SAFEMODE 0x8000000000000000 /* Unknown future revision - SAFE MODE */ -#define AMD_NPT_F0 0x0000000000000001 /* F0 stepping */ -#define AMD_NPT_F1 0x0000000000000002 /* F1 stepping */ -#define AMD_NPT_F2C 0x0000000000000004 -#define AMD_NPT_F2D 0x0000000000000008 -#define AMD_NPT_F2E 0x0000000000000010 /* F2 stepping E */ -#define AMD_NPT_F2G 0x0000000000000020 /* F2 stepping G */ -#define AMD_NPT_F2J 0x0000000000000040 -#define AMD_NPT_F2K 0x0000000000000080 -#define AMD_NPT_F3L 0x0000000000000100 /* F3 Stepping */ -#define AMD_NPT_G0A 0x0000000000000200 /* G0 stepping */ -#define AMD_NPT_G1B 0x0000000000000400 /* G1 stepping */ -#define AMD_DR_A0A 0x0000000000010000 /* Barcelona A0 */ -#define AMD_DR_A1B 0x0000000000020000 /* Barcelona A1 */ -#define AMD_DR_A2 0x0000000000040000 /* Barcelona A2 */ -#define AMD_DR_B0 0x0000000000080000 /* Barcelona B0 */ -#define AMD_DR_B1 0x0000000000100000 /* Barcelona B1 */ -#define AMD_DR_B2 0x0000000000200000 /* Barcelona B2 */ -#define AMD_DR_BA 0x0000000000400000 /* Barcelona BA */ -#define AMD_DR_B3 0x0000000000800000 /* Barcelona B3 */ -#define AMD_RB_C2 0x0000000001000000 /* Shanghai C2 */ -#define AMD_DA_C2 0x0000000002000000 /* XXXX C2 */ -#define AMD_HY_D0 0x0000000004000000 /* Istanbul D0 */ -#define AMD_RB_C3 0x0000000008000000 /* ??? C3 */ -#define AMD_DA_C3 0x0000000010000000 /* XXXX C3 */ -#define AMD_HY_D1 0x0000000020000000 /* Istanbul D1 */ -#define AMD_PH_E0 0x0000000040000000 /* Phenom II X4 X6 */ -#define AMD_OR_B2 0x0000000080000000 /* Interlagos */ -#define AMD_OR_C0 0x0000000100000000 /* Abu Dhabi */ - -/* - * Groups - Create as many as you wish, from the above public values - */ -#define AMD_NPT_F2 (AMD_NPT_F2C | AMD_NPT_F2D | AMD_NPT_F2E | AMD_NPT_F2G | AMD_NPT_F2J | AMD_NPT_F2K) -#define AMD_NPT_F3 (AMD_NPT_F3L) -#define AMD_NPT_Fx (AMD_NPT_F0 | AMD_NPT_F1 | AMD_NPT_F2 | AMD_NPT_F3) -#define AMD_NPT_Gx (AMD_NPT_G0A | AMD_NPT_G1B) -#define AMD_NPT_ALL (AMD_NPT_Fx | AMD_NPT_Gx) -#define AMD_FINEDELAY (AMD_NPT_F0 | AMD_NPT_F1 | AMD_NPT_F2) -#define AMD_GT_F0 (AMD_NPT_ALL AND NOT AMD_NPT_F0) -#define AMD_DR_Ax (AMD_DR_A0A + AMD_DR_A1B + AMD_DR_A2) -#define AMD_DR_Bx (AMD_DR_B0 | AMD_DR_B1 | AMD_DR_B2 | AMD_DR_B3 | AMD_DR_BA) -#define AMD_DR_Cx (AMD_RB_C2 | AMD_RB_C3 | AMD_DA_Cx) -#define AMD_DR_Dx (AMD_HY_D0 | AMD_HY_D1) -#define AMD_DR_Ex (AMD_PH_E0) -#define AMD_DR_LT_B2 (AMD_DR_B0 | AMD_DR_B1 | AMD_DR_BA) -#define AMD_DR_LT_B3 (AMD_DR_B0 | AMD_DR_B1 | AMD_DR_B2 | AMD_DR_BA) -#define AMD_DR_GT_B0 (AMD_DR_ALL & ~(AMD_DR_B0)) -#define AMD_DR_GT_Bx (AMD_DR_ALL & ~(AMD_DR_Ax | AMD_DR_Bx)) -#define AMD_DR_GT_D0 ((AMD_DR_Dx & ~(AMD_HY_D0)) | AMD_DR_Ex) -#define AMD_DR_ALL (AMD_DR_Ax | AMD_DR_Bx | AMD_DR_Cx | AMD_DR_Dx | AMD_DR_Ex) -#define AMD_FAM10_ALL (AMD_DR_ALL | AMD_RB_C2 | AMD_HY_D0 | AMD_DA_C3 | AMD_DA_C2 | AMD_RB_C3 | AMD_HY_D1 | AMD_PH_E0) -#define AMD_FAM10_LT_D (AMD_FAM10_ALL & ~(AMD_HY_D0)) -#define AMD_FAM10_GT_B0 (AMD_FAM10_ALL & ~(AMD_DR_B0)) -#define AMD_FAM10_REV_D (AMD_HY_D0 | AMD_HY_D1) -#define AMD_DA_Cx (AMD_DA_C2 | AMD_DA_C3) -#define AMD_FAM10_C3 (AMD_RB_C3 | AMD_DA_C3) -#define AMD_DRBH_Cx (AMD_DR_Cx | AMD_HY_D0) -#define AMD_DRBA23_RBC2 (AMD_DR_BA | AMD_DR_B2 | AMD_DR_B3 | AMD_RB_C2) -#define AMD_DR_DAC2_OR_C3 (AMD_DA_C2 | AMD_DA_C3 | AMD_RB_C3) -#define AMD_FAM15_ALL (AMD_OR_B2 | AMD_OR_C0) - -/* - * Public Platforms - USE THESE VERSIONS TO MAKE COMPARE WITH CPUPLATFORMTYPE RETURN VALUE - */ -#define AMD_PTYPE_DSK 0x001 /* Desktop/DTR/UP */ -#define AMD_PTYPE_MOB 0x002 /* Mobile/Cool-n-quiet */ -#define AMD_PTYPE_SVR 0x004 /* Workstation/Server/Multicore DT */ -#define AMD_PTYPE_UC 0x008 /* Single Core */ -#define AMD_PTYPE_DC 0x010 /* Dual Core */ -#define AMD_PTYPE_MC 0x020 /* Multi Core (>2) */ -#define AMD_PTYPE_UMA 0x040 /* UMA required */ - -/* - * Groups - Create as many as you wish, from the above public values - */ -#define AMD_PTYPE_ALL 0xFFFFFFFF /* A mask for all */ - - -/* - * CPU PCI HT PHY REGISTER, LINK TYPES - PRIVATE - */ -#define HTPHY_LINKTYPE_HT3 0x00000001 -#define HTPHY_LINKTYPE_HT1 0x00000002 -#define HTPHY_LINKTYPE_COHERENT 0x00000004 -#define HTPHY_LINKTYPE_NONCOHERENT 0x00000008 -#define HTPHY_LINKTYPE_CONNECTED (HTPHY_LINKTYPE_COHERENT | HTPHY_LINKTYPE_NONCOHERENT) -#define HTPHY_LINKTYPE_GANGED 0x00000010 -#define HTPHY_LINKTYPE_UNGANGED 0x00000020 -#define HTPHY_LINKTYPE_ALL 0x7FFFFFFF - - -/* - * CPU HT PHY REGISTERS, FIELDS, AND MASKS - */ -#define HTPHY_OFFSET_MASK 0xE000FFFF -#define HTPHY_WRITE_CMD 0x40000000 -#define HTPHY_IS_COMPLETE_MASK 0x80000000 -#define HTPHY_DIRECT_MAP 0x20000000 -#define HTPHY_DIRECT_OFFSET_MASK 0xE000FFFF - -/* - * Processor package types - */ -#define AMD_PKGTYPE_FrX_1207 0 -#define AMD_PKGTYPE_AM3_2r2 1 -#define AMD_PKGTYPE_S1gX 2 -#define AMD_PKGTYPE_G34 3 -#define AMD_PKGTYPE_ASB2 4 -#define AMD_PKGTYPE_C32 5 -#define AMD_PKGTYPE_FM2 6 - -//DDR2 REG and unbuffered : Socket F 1027 and AM3 -/* every channel have 4 DDR2 DIMM for socket F - * 2 for socket M2/M3 - * 1 for socket s1g1 - */ -#define DIMM_SOCKETS 4 -struct mem_controller { - u32 node_id; - pci_devfn_t f0, f1, f2, f3, f4, f5; - /* channel0 is DCT0 --- channelA - * channel1 is DCT1 --- channelB - * can be ganged, a single dual-channel DCT ---> 128 bit - * or unganged a two single-channel DCTs ---> 64bit - * When the DCTs are ganged, the writes to DCT1 set of registers - * (F2x1XX) are ignored and reads return all 0's - * The exception is the DCT phy registers, F2x[1,0]98, F2x[1,0]9C, - * and all the associated indexed registers, are still - * independently accessiable - */ - /* FIXME: I will only support ganged mode for easy support */ - u8 spd_switch_addr; - u8 spd_addr[DIMM_SOCKETS*2]; -}; - -#endif diff --git a/src/northbridge/amd/amdmct/mct/Makefile.inc b/src/northbridge/amd/amdmct/mct/Makefile.inc deleted file mode 100644 index f986201c6d..0000000000 --- a/src/northbridge/amd/amdmct/mct/Makefile.inc +++ /dev/null @@ -1,16 +0,0 @@ -ifeq ($(CONFIG_NORTHBRIDGE_AMD_AMDFAM10),y) - -# DDR2 -romstage-y += mct_d.c mct_d_gcc.c mctcsi_d.c mctmtr_d.c mctecc_d.c -romstage-y += mctpro_d.c mctdqs_d.c mctsrc.c mctsrc1p.c mcttmrl.c -romstage-y += mcthdi.c mctndi_d.c mctchi_d.c - -ifeq ($(CONFIG_CPU_SOCKET_TYPE), 0x10) -romstage-y += mctardk3.c -endif - -ifeq ($(CONFIG_CPU_SOCKET_TYPE), 0x11) -romstage-y += mctardk4.c -endif - -endif diff --git a/src/northbridge/amd/amdmct/mct/mct.h b/src/northbridge/amd/amdmct/mct/mct.h deleted file mode 100644 index 598ab37e76..0000000000 --- a/src/northbridge/amd/amdmct/mct/mct.h +++ /dev/null @@ -1,539 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007 Advanced Micro Devices, Inc. - * Copyright (C) 2015 Timothy Pearson , Raptor Engineering - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef MCT_H -#define MCT_H - -#include - -/*=========================================================================== - CPU - K8/FAM10 -===========================================================================*/ -#define PT_L1 0 /* CPU Package Type*/ -#define PT_M2 1 -#define PT_S1 2 - -#define J_MIN 0 /* j loop constraint. 1 = CL 2.0 T*/ -#define J_MAX 4 /* j loop constraint. 4 = CL 6.0 T*/ -#define K_MIN 1 /* k loop constraint. 1 = 200 MHz*/ -#define K_MAX 4 /* k loop constraint. 9 = 400 MHz*/ -#define CL_DEF 2 /* Default value for failsafe operation. 2 = CL 4.0 T*/ -#define T_DEF 1 /* Default value for failsafe operation. 1 = 5ns (cycle time)*/ - -#define BSCRate 1 /* reg bit field = rate of dram scrubber for ecc*/ - /* memory initialization (ecc and check-bits).*/ - /* 1 = 40 ns/64 bytes.*/ -#define FirstPass 1 /* First pass through RcvEn training*/ -#define SecondPass 2 /* Second pass through Rcven training*/ - -#define RCVREN_MARGIN 6 /* number of DLL taps to delay beyond first passing position*/ -#define MAXASYNCLATCTL_3 60 /* Max Async Latency Control value (This value will be divided by 20)*/ -#define DQS_FAIL 1 -#define DQS_PASS 0 -#define DQS_WRITEDIR 0 -#define DQS_READDIR 1 -#define MIN_DQS_WNDW 3 -#define secPassOffset 6 - -#define PA_HOST (((24 << 3)+0) << 8) /* Node 0 Host Bus function PCI Address bits [15:0] */ -#define PA_MAP (((24 << 3)+1) << 8) /* Node 0 MAP function PCI Address bits [15:0] */ -#define PA_DCT (((24 << 3)+2) << 8) /* Node 0 DCT function PCI Address bits [15:0] */ -#define PA_DCTADDL (((00 << 3)+2) << 8) /* Node x DCT function, Additional Registers PCI Address bits [15:0] */ -#define PA_NBMISC (((24 << 3)+3) << 8) /* Node 0 Misc PCI Address bits [15:0] */ -#define PA_NBDEVOP (((00 << 3)+3) << 8) /* Node 0 Misc PCI Address bits [15:0] */ - -#define DCC_EN 1 /* X:2:0x94[19]*/ -#define ILD_Lmt 3 /* X:2:0x94[18:16]*/ - -#define EncodedTSPD 0x00191709 /* encodes which SPD byte to get T from*/ - /* versus CL X, CL X-.5, and CL X-1*/ - -#define Bias_TrpT 3 /* bias to convert bus clocks to bit field value*/ -#define Bias_TrrdT 2 -#define Bias_TrcdT 3 -#define Bias_TrasT 3 -#define Bias_TrcT 11 -#define Bias_TrtpT 4 -#define Bias_TwrT 3 -#define Bias_TwtrT 0 - -#define Min_TrpT 3 /* min programmable value in busclocks*/ -#define Max_TrpT 6 /* max programmable value in busclocks*/ -#define Min_TrrdT 2 -#define Max_TrrdT 5 -#define Min_TrcdT 3 -#define Max_TrcdT 6 -#define Min_TrasT 5 -#define Max_TrasT 18 -#define Min_TrcT 11 -#define Max_TrcT 26 -#define Min_TrtpT 4 -#define Max_TrtpT 5 -#define Min_TwrT 3 -#define Max_TwrT 6 -#define Min_TwtrT 1 -#define Max_TwtrT 3 - -/* common register bit names */ -#define DramHoleValid 0 /* func 1, offset F0h, bit 0 */ -#define CSEnable 0 /* func 2, offset 40h-5C, bit 0 */ -#define Spare 1 /* func 2, offset 40h-5C, bit 1 */ -#define TestFail 2 /* func 2, offset 40h-5C, bit 2 */ -#define DqsRcvEnTrain 18 /* func 2, offset 78h, bit 18 */ -#define EnDramInit 31 /* func 2, offset 7Ch, bit 31 */ -#define DisAutoRefresh 18 /* func 2, offset 8Ch, bit 18 */ -#define InitDram 0 /* func 2, offset 90h, bit 0 */ -#define BurstLength32 10 /* func 2, offset 90h, bit 10 */ -#define Width128 11 /* func 2, offset 90h, bit 11 */ -#define X4Dimm 12 /* func 2, offset 90h, bit 12 */ -#define UnBuffDimm 16 /* func 2, offset 90h, bit 16 */ -#define DimmEcEn 19 /* func 2, offset 90h, bit 19 */ -#define MemClkFreqVal 3 /* func 2, offset 94h, bit 3 */ -#define RDqsEn 12 /* func 2, offset 94h, bit 12 */ -#define DisDramInterface 14 /* func 2, offset 94h, bit 14 */ -#define DctAccessWrite 30 /* func 2, offset 98h, bit 30 */ -#define DctAccessDone 31 /* func 2, offset 98h, bit 31 */ -#define PwrSavingsEn 10 /* func 2, offset A0h, bit 10 */ -#define Mod64BitMux 4 /* func 2, offset A0h, bit 4 */ -#define DisableJitter 1 /* func 2, offset A0h, bit 1 */ -#define DramEnabled 9 /* func 2, offset A0h, bit 9 */ -#define SyncOnUcEccEn 2 /* func 3, offset 44h, bit 2 */ - -/*============================================================================= - Jedec DDR II -=============================================================================*/ -#define SPD_TYPE 2 /* SPD byte read location*/ - #define JED_DDRSDRAM 0x07 /* Jedec defined bit field*/ - #define JED_DDR2SDRAM 0x08 /* Jedec defined bit field*/ - -#define SPD_DIMMTYPE 20 -#define SPD_ATTRIB 21 - #define JED_DIFCKMSK 0x20 /* Differential Clock Input*/ - #define JED_REGADCMSK 0x11 /* Registered Address/Control*/ - #define JED_PROBEMSK 0x40 /* Analysis Probe installed*/ -#define SPD_DEVATTRIB 22 -#define SPD_EDCTYPE 11 - #define JED_ECC 0x02 - #define JED_ADRCPAR 0x04 -#define SPD_ROWSZ 3 -#define SPD_COLSZ 4 -#define SPD_LBANKS 17 /* number of [logical] banks on each device*/ -#define SPD_DMBANKS 5 /* number of physical banks on dimm*/ - #define SPDPLBit 4 /* Dram package bit*/ -#define SPD_BANKSZ 31 /* capacity of physical bank*/ -#define SPD_DEVWIDTH 13 -#define SPD_CASLAT 18 -#define SPD_TRP 27 -#define SPD_TRRD 28 -#define SPD_TRCD 29 -#define SPD_TRAS 30 -#define SPD_TWR 36 -#define SPD_TWTR 37 -#define SPD_TRTP 38 -#define SPD_TRCRFC 40 -#define SPD_TRC 41 -#define SPD_TRFC 42 - -#define SPD_MANDATEYR 93 /* Module Manufacturing Year (BCD) */ - -#define SPD_MANDATEWK 94 /* Module Manufacturing Week (BCD) */ - -/*-------------------------------------- - Jedec DDR II related equates ---------------------------------------*/ -#define MYEAR06 6 /* Manufacturing Year BCD encoding of 2006 - 06d*/ -#define MWEEK24 0x24 /* Manufacturing Week BCD encoding of June - 24d*/ - -/*============================================================================= - Macros -=============================================================================*/ - -#define _2GB_RJ8 (2<<(30-8)) -#define _4GB_RJ8 (4<<(30-8)) -#define _4GB_RJ4 (4<<(30-4)) - -#define BigPagex8_RJ8 (1<<(17+3-8)) /* 128KB * 8 >> 8 */ - -/*============================================================================= - Global MCT Status Structure -=============================================================================*/ -struct MCTStatStruc { - u32 GStatus; /* Global Status bitfield*/ - u32 HoleBase; /* If not zero, BASE[39:8] (system address) - of sub 4GB dram hole for HW remapping.*/ - u32 Sub4GCacheTop; /* If not zero, the 32-bit top of cacheable memory.*/ - u32 SysLimit; /* LIMIT[39:8] (system address)*/ -}; -/*============================================================================= - Global MCT Configuration Status Word (GStatus) -=============================================================================*/ -/*These should begin at bit 0 of GStatus[31:0]*/ -#define GSB_MTRRshort 0 /* Ran out of MTRRs while mapping memory*/ -#define GSB_ECCDIMMs 1 /* All banks of all Nodes are ECC capable*/ -#define GSB_DramECCDis 2 /* Dram ECC requested but not enabled.*/ -#define GSB_SoftHole 3 /* A Node Base gap was created*/ -#define GSB_HWHole 4 /* A HW dram remap was created*/ -#define GSB_NodeIntlv 5 /* Node Memory interleaving was enabled*/ -#define GSB_SpIntRemapHole 16 /* Special condition for Node Interleave and HW remapping*/ - - -/*=============================================================================== - Local DCT Status structure (a structure for each DCT) -===============================================================================*/ - -struct DCTStatStruc { /* A per Node structure*/ - u8 Node_ID; /* Node ID of current controller*/ - u8 ErrCode; /* Current error condition of Node - 0= no error - 1= Variance Error, DCT is running but not in an optimal configuration. - 2= Stop Error, DCT is NOT running - 3= Fatal Error, DCT/MCT initialization has been halted.*/ - u32 ErrStatus; /* Error Status bit Field */ - u32 Status; /* Status bit Field*/ - u8 DIMMAddr[8]; /* SPD address of DIMM controlled by MA0_CS_L[0,1]*/ - /* SPD address of..MB0_CS_L[0,1]*/ - /* SPD address of..MA1_CS_L[0,1]*/ - /* SPD address of..MB1_CS_L[0,1]*/ - /* SPD address of..MA2_CS_L[0,1]*/ - /* SPD address of..MB2_CS_L[0,1]*/ - /* SPD address of..MA3_CS_L[0,1]*/ - /* SPD address of..MB3_CS_L[0,1]*/ - u16 DIMMPresent; /* For each bit n 0..7, 1 = DIMM n is present. - DIMM# Select Signal - 0 MA0_CS_L[0,1] - 1 MB0_CS_L[0,1] - 2 MA1_CS_L[0,1] - 3 MB1_CS_L[0,1] - 4 MA2_CS_L[0,1] - 5 MB2_CS_L[0,1] - 6 MA3_CS_L[0,1] - 7 MB3_CS_L[0,1]*/ - u16 DIMMValid; /* For each bit n 0..7, 1 = DIMM n is valid and is/will be configured*/ - u16 DIMMSPDCSE; /* For each bit n 0..7, 1 = DIMM n SPD checksum error*/ - u16 DimmECCPresent; /* For each bit n 0..7, 1 = DIMM n is ECC capable.*/ - u16 DimmPARPresent; /* For each bit n 0..7, 1 = DIMM n is ADR/CMD Parity capable.*/ - u16 Dimmx4Present; /* For each bit n 0..7, 1 = DIMM n contains x4 data devices.*/ - u16 Dimmx8Present; /* For each bit n 0..7, 1 = DIMM n contains x8 data devices.*/ - u16 Dimmx16Present; /* For each bit n 0..7, 1 = DIMM n contains x16 data devices.*/ - u16 DIMM1Kpage; /* For each bit n 0..7, 1 = DIMM n contains 1K page devices.*/ - u8 MAload[2]; /* Number of devices loading MAA bus*/ - /* Number of devices loading MAB bus*/ - u8 MAdimms[2]; /* Number of DIMMs loading CH A*/ - /* Number of DIMMs loading CH B*/ - u8 DATAload[2]; /* Number of ranks loading CH A DATA*/ - /* Number of ranks loading CH B DATA*/ - u8 DIMMAutoSpeed; /* Max valid Mfg. Speed of DIMMs - 1 = 200MHz - 2 = 266MHz - 3 = 333MHz - 4 = 400MHz */ - u8 DIMMCASL; /* Min valid Mfg. CL bitfield - 0 = 2.0 - 1 = 3.0 - 2 = 4.0 - 3 = 5.0 - 4 = 6.0 */ - u16 DIMMTrcd; /* Minimax Trcd*40 (ns) of DIMMs*/ - u16 DIMMTrp; /* Minimax Trp*40 (ns) of DIMMs*/ - u16 DIMMTrtp; /* Minimax Trtp*40 (ns) of DIMMs*/ - u16 DIMMTras; /* Minimax Tras*40 (ns) of DIMMs*/ - u16 DIMMTrc; /* Minimax Trc*40 (ns) of DIMMs*/ - u16 DIMMTwr; /* Minimax Twr*40 (ns) of DIMMs*/ - u16 DIMMTrrd; /* Minimax Trrd*40 (ns) of DIMMs*/ - u16 DIMMTwtr; /* Minimax Twtr*40 (ns) of DIMMs*/ - u8 Speed; /* Bus Speed (to set Controller) - 1 = 200MHz - 2 = 266MHz - 3 = 333MHz - 4 = 400MHz */ - u8 CASL; /* CAS latency DCT setting - 0 = 2.0 - 1 = 3.0 - 2 = 4.0 - 3 = 5.0 - 4 = 6.0 */ - u8 Trcd; /* DCT Trcd (busclocks) */ - u8 Trp; /* DCT Trp (busclocks) */ - u8 Trtp; /* DCT Trtp (busclocks) */ - u8 Tras; /* DCT Tras (busclocks) */ - u8 Trc; /* DCT Trc (busclocks) */ - u8 Twr; /* DCT Twr (busclocks) */ - u8 Trrd; /* DCT Trrd (busclocks) */ - u8 Twtr; /* DCT Twtr (busclocks) */ - u8 Trfc[4]; /* DCT Logical DIMM0 Trfc - 0 = 75ns (for 256Mb devs) - 1 = 105ns (for 512Mb devs) - 2 = 127.5ns (for 1Gb devs) - 3 = 195ns (for 2Gb devs) - 4 = 327.5ns (for 4Gb devs) */ - /* DCT Logical DIMM1 Trfc (see Trfc0 for format) */ - /* DCT Logical DIMM2 Trfc (see Trfc0 for format) */ - /* DCT Logical DIMM3 Trfc (see Trfc0 for format) */ - u16 CSPresent; /* For each bit n 0..7, 1 = Chip-select n is present */ - u16 CSTestFail; /* For each bit n 0..7, 1 = Chip-select n is present but disabled */ - u32 DCTSysBase; /* BASE[39:8] (system address) of this Node's DCTs. */ - u32 DCTHoleBase; /* If not zero, BASE[39:8] (system address) of dram hole for HW remapping. Dram hole exists on this Node's DCTs. */ - u32 DCTSysLimit; /* LIMIT[39:8] (system address) of this Node's DCTs */ - u16 PresetmaxFreq; /* Maximum OEM defined DDR frequency - 200 = 200MHz (DDR400) - 266 = 266MHz (DDR533) - 333 = 333MHz (DDR667) - 400 = 400MHz (DDR800) */ - u8 _2Tmode; /* 1T or 2T CMD mode (slow access mode) - 1 = 1T - 2 = 2T */ - u8 TrwtTO; /* DCT TrwtTO (busclocks)*/ - u8 Twrrd; /* DCT Twrrd (busclocks)*/ - u8 Twrwr; /* DCT Twrwr (busclocks)*/ - u8 Trdrd; /* DCT Trdrd (busclocks)*/ - u32 CH_ODC_CTL[2]; /* Output Driver Strength (see BKDG FN2:Offset 9Ch, index 00h*/ - u32 CH_ADDR_TMG[2]; /* Address Bus Timing (see BKDG FN2:Offset 9Ch, index 04h*/ - /* Output Driver Strength (see BKDG FN2:Offset 9Ch, index 20h*/ - /* Address Bus Timing (see BKDG FN2:Offset 9Ch, index 24h*/ - u16 CH_EccDQSLike[2]; /* CHA DQS ECC byte like...*/ - u8 CH_EccDQSScale[2]; /* CHA DQS ECC byte scale*/ -// u8 reserved_b_1; /* Reserved*/ - /* CHB DQS ECC byte like...*/ - /* CHB DQS ECC byte scale*/ -// u8 reserved_b_2; /*Reserved*/ - u8 MaxAsyncLat; /* Max Asynchronous Latency (ns)*/ - u8 CH_B_DQS[2][2][9]; /* CHA Byte 0 - 7 and Check Write DQS Delay*/ - /* Reserved*/ - /* CHA Byte 0 - 7 and Check Read DQS Delay*/ - /* Reserved*/ - /* CHB Byte 0 - 7 and Check Write DQS Delay*/ - /* Reserved*/ - /* CHB Byte 0 - 7 and Check Read DQS Delay*/ - /* Reserved*/ - u8 CH_D_RCVRDLY[2][4]; /* CHA DIMM 0 - 3 Receiver Enable Delay*/ - /* CHB DIMM 0 - 3 Receiver Enable Delay*/ - u32 PtrPatternBufA; /* Ptr on stack to aligned DQS testing pattern*/ - u32 PtrPatternBufB; /*Ptr on stack to aligned DQS testing pattern*/ - u8 Channel; /* Current Channel (0= CH A, 1 = CH B)*/ - u8 ByteLane; /* Current Byte Lane (0..7)*/ - u8 Direction; /* Current DQS-DQ training write direction (0 = read, 1 = write)*/ - u8 Pattern; /* Current pattern*/ - u8 DQSDelay; /* Current DQS delay value*/ - u32 TrainErrors; /* Current Training Errors*/ -// u8 reserved_b_3; /* RSVD */ - u32 AMC_TSC_DeltaLo; /* Time Stamp Counter measurement of AMC, Low dword*/ - u32 AMC_TSC_DeltaHi; /* Time Stamp Counter measurement of AMC, High dword*/ - u8 CH_B_Dly[2][2][2][8]; /* CH A byte lane 0 - 7 minimum filtered window passing DQS delay value*/ - /* CH A byte lane 0 - 7 maximum filtered window passing DQS delay value*/ - /* CH B byte lane 0 - 7 minimum filtered window passing DQS delay value*/ - /* CH B byte lane 0 - 7 maximum filtered window passing DQS delay value*/ - /* CH A byte lane 0 - 7 minimum filtered window passing DQS delay value*/ - /* CH A byte lane 0 - 7 maximum filtered window passing DQS delay value*/ - /* CH B byte lane 0 - 7 minimum filtered window passing DQS delay value*/ - /* CH B byte lane 0 - 7 maximum filtered window passing DQS delay value*/ - u32 LogicalCPUID; /* The logical CPUID of the node*/ - u16 HostBiosSrvc1; /* Word sized general purpose field for use by host BIOS. Scratch space.*/ - u32 HostBiosSrvc2; /* Dword sized general purpose field for use by host BIOS. Scratch space.*/ - u16 DimmQRPresent; /* QuadRank DIMM present?*/ - u16 DimmTrainFail; /* Bitmap showing which dimms failed training*/ - u16 CSTrainFail; /* Bitmap showing which chipselects failed training*/ - u16 DimmYr06; /* Bitmap indicating which Dimms have a manufactur's year code <= 2006*/ - u16 DimmWk2406; /* Bitmap indicating which Dimms have a manufactur's week code <= 24 of 2006 (June)*/ - u16 DimmDRPresent; /* Bitmap indicating that Dual Rank Dimms are present*/ - u16 DimmPlPresent; /* Bitmap indicating that Planar (1) or Stacked (0) Dimms are present.*/ - u16 ChannelTrainFail; /* Bitmap showing the channel information about failed Chip Selects*/ - /* 0 in any bit field indicates Channel 0*/ - /* 1 in any bit field indicates Channel 1*/ -}; - -/*=============================================================================== - Local Error Status Codes (DCTStatStruc.ErrCode) -===============================================================================*/ -#define SC_RunningOK 0 -#define SC_VarianceErr 1 /* Running non-optimally*/ -#define SC_StopError 2 /* Not Running*/ -#define SC_FatalErr 3 /* Fatal Error, MCTB has exited immediately*/ - -/*=============================================================================== - Local Error Status (DCTStatStruc.ErrStatus[31:0]) - ===============================================================================*/ -#define SB_NoDimms 0 -#define SB_DIMMChkSum 1 -#define SB_DimmMismatchM 2 /* dimm module type(buffer) mismatch*/ -#define SB_DimmMismatchT 3 /* dimm CL/T mismatch*/ -#define SB_DimmMismatchO 4 /* dimm organization mismatch (128-bit)*/ -#define SB_NoTrcTrfc 5 /* SPD missing Trc or Trfc info*/ -#define SB_NoCycTime 6 /* SPD missing byte 23 or 25*/ -#define SB_BkIntDis 7 /* Bank interleave requested but not enabled*/ -#define SB_DramECCDis 8 /* Dram ECC requested but not enabled*/ -#define SB_SpareDis 9 /* Online spare requested but not enabled*/ -#define SB_MinimumMode 10 /* Running in Minimum Mode*/ -#define SB_NORCVREN 11 /* No DQS Receiver Enable pass window found*/ -#define SB_CHA2BRCVREN 12 /* DQS Rcvr En pass window CHA to CH B too large*/ -#define SB_SmallRCVR 13 /* DQS Rcvr En pass window too small (far right of dynamic range)*/ -#define SB_NODQSPOS 14 /* No DQS-DQ passing positions*/ -#define SB_SMALLDQS 15 /* DQS-DQ passing window too small*/ - -/*=============================================================================== - Local Configuration Status (DCTStatStruc.Status[31:0]) -===============================================================================*/ -#define SB_Registered 0 /* All DIMMs are Registered*/ -#define SB_ECCDIMMs 1 /* All banks ECC capable*/ -#define SB_PARDIMMs 2 /* All banks Addr/CMD Parity capable*/ -#define SB_DiagClks 3 /* Jedec ALL slots clock enable diag mode*/ -#define SB_128bitmode 4 /* DCT in 128-bit mode operation*/ -#define SB_64MuxedMode 5 /* DCT in 64-bit mux'ed mode.*/ -#define SB_2TMode 6 /* 2T CMD timing mode is enabled.*/ -#define SB_SWNodeHole 7 /* Remapping of Node Base on this Node to create a gap.*/ -#define SB_HWHole 8 /* Memory Hole created on this Node using HW remapping.*/ - - - -/*=============================================================================== - NVRAM/run-time-configurable Items -===============================================================================*/ -/* Platform Configuration */ -#define NV_PACK_TYPE 0 /* CPU Package Type (2-bits) - 0 = NPT L1 - 1 = NPT M2 - 2 = NPT S1*/ -#define NV_MAX_NODES 1 /* Number of Nodes/Sockets (4-bits)*/ -#define NV_MAX_DIMMS 2 /* Number of DIMM slots for the specified Node ID (4-bits)*/ -#define NV_MAX_MEMCLK 3 /* Maximum platform demonstrated Memclock (10-bits) - 200 = 200MHz (DDR400) - 266 = 266MHz (DDR533) - 333 = 333MHz (DDR667) - 400 = 400MHz (DDR800)*/ -#define NV_ECC_CAP 4 /* Bus ECC capable (1-bits) - 0 = Platform not capable - 1 = Platform is capable*/ -#define NV_4RANKType 5 /* Quad Rank DIMM slot type (2-bits) - 0 = Normal - 1 = R4 (4-Rank Registered DIMMs in AMD server configuration) - 2 = S4 (Unbuffered SO-DIMMs)*/ -#define NV_BYPMAX 6 /* Value to set DcqBypassMax field (See Function 2, Offset 94h, [27:24] of BKDG for field definition). - 4 = 4 times bypass (normal for non-UMA systems) - 7 = 7 times bypass (normal for UMA systems)*/ -#define NV_RDWRQBYP 7 /* Value to set RdWrQByp field (See Function 2, Offset A0h, [3:2] of BKDG for field definition). - 2 = 8 times (normal for non-UMA systems) - 3 = 16 times (normal for UMA systems)*/ - - -/* Dram Timing */ -#define NV_MCTUSRTMGMODE 10 /* User Memclock Mode (2-bits) - 0 = Auto, no user limit - 1 = Auto, user limit provided in NV_MemCkVal - 2 = Manual, user value provided in NV_MemCkVal*/ -#define NV_MemCkVal 11 /* Memory Clock Value (2-bits) - 0 = 200MHz - 1 = 266MHz - 2 = 333MHz - 3 = 400MHz*/ - -/* Dram Configuration */ -#define NV_BankIntlv 20 /* Dram Bank (chip-select) Interleaving (1-bits) - 0 = disable - 1 = enable*/ -#define NV_AllMemClks 21 /* Turn on All DIMM clocks (1-bits) - 0 = normal - 1 = enable all memclocks*/ -#define NV_SPDCHK_RESTRT 22 /* SPD Check control bitmap (1-bits) - 0 = Exit current node init if any DIMM has SPD checksum error - 1 = Ignore faulty SPD checksums (Note: DIMM cannot be enabled)*/ -#define NV_DQSTrainCTL 23 /* DQS Signal Timing Training Control - 0 = skip DQS training - 1 = perform DQS training*/ -#define NV_NodeIntlv 24 /* Node Memory Interleaving (1-bits) - 0 = disable - 1 = enable*/ -#define NV_BurstLen32 25 /* burstLength32 for 64-bit mode (1-bits) - 0 = disable (normal) - 1 = enable (4 beat burst when width is 64-bits)*/ - -/* Dram Power */ -#define NV_CKE_PDEN 30 /* CKE based power down mode (1-bits) - 0 = disable - 1 = enable*/ -#define NV_CKE_CTL 31 /* CKE based power down control (1-bits) - 0 = per Channel control - 1 = per Chip select control*/ -#define NV_CLKHZAltVidC3 32 /* Memclock tri-stating during C3 and Alt VID (1-bits) - 0 = disable - 1 = enable*/ - -/* Memory Map/Mgt.*/ -#define NV_BottomIO 40 /* Bottom of 32-bit IO space (8-bits) - NV_BottomIO[7:0]=Addr[31:24]*/ -#define NV_BottomUMA 41 /* Bottom of shared graphics dram (8-bits) - NV_BottomUMA[7:0]=Addr[31:24]*/ -#define NV_MemHole 42 /* Memory Hole Remapping (1-bits) - 0 = disable - 1 = enable */ - -/* ECC */ -#define NV_ECC 50 /* Dram ECC enable*/ -#define NV_NBECC 52 /* ECC MCE enable*/ -#define NV_ChipKill 53 /* Chip-Kill ECC Mode enable*/ -#define NV_ECCRedir 54 /* Dram ECC Redirection enable*/ -#define NV_DramBKScrub 55 /* Dram ECC Background Scrubber CTL*/ -#define NV_L2BKScrub 56 /* L2 ECC Background Scrubber CTL*/ -#define NV_DCBKScrub 57 /* DCache ECC Background Scrubber CTL*/ -#define NV_CS_SpareCTL 58 /* Chip Select Spare Control bit 0: - 0 = disable Spare - 1 = enable Spare */ - /*Chip Select Spare Control bit 1-4: - Reserved, must be zero*/ -#define NV_Parity 60 /* Parity Enable*/ -#define NV_SyncOnUnEccEn 61 /* SyncOnUnEccEn control - 0 = disable - 1 = enable*/ - - -/* global function */ -u32 NodePresent(u32 Node); -u32 Get_NB32n(struct DCTStatStruc *pDCTstat, u32 addrx); -u32 Get_NB32(u32 addr); /* NOTE: extend addr to 32 bit for bus > 0 */ -uint64_t mctGetLogicalCPUID(u32 Node); - -void K8FInterleaveBanks(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstat); - -void mctInitWithWritetoCS(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstat); - -void mctGet_PS_Cfg(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstat); -void Get_ChannelPS_Cfg0(unsigned int MAAdimms, unsigned int Speed, unsigned int MAAload, unsigned int DATAAload, - unsigned int *AddrTmgCTL, unsigned int *ODC_CTL); -void Get_ChannelPS_Cfg1(unsigned int MAAdimms, unsigned int Speed, unsigned int MAAload, - unsigned int *AddrTmgCTL, unsigned int *ODC_CTL, unsigned int *val); -void Get_ChannelPS_Cfg2(unsigned int MAAdimms, unsigned int Speed, unsigned int MAAload, - unsigned int *AddrTmgCTL, unsigned int *ODC_CTL, unsigned int *val); - -u8 MCTDefRet(void); - -u32 Get_RcvrSysAddr(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstat, u8 channel, u8 receiver, u8 *valid); -u32 Get_MCTSysAddr(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstat, u8 channel, u8 chipsel, u8 *valid); -void K8FTrainReceiverEn(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstatA, u8 pass); -void K8FTrainDQSPos(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstatA); -u32 SetUpperFSbase(u32 addr_hi); - - -void K8FECCInit(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstatA); - -void amd_MCTInit(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstatA); - -void K8FCPUMemTyping(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstatA); -void K8FCPUMemTyping_clear(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstatA); - -void K8FWaitMemClrDelay(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstat); -unsigned int K8FCalcFinalDQSRcvValue(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstat, unsigned int LeftRcvEn, unsigned int RightRcvEn, unsigned int *valid); - -void K8FGetDeltaTSCPart1(struct DCTStatStruc *pDCTstat); -void K8FGetDeltaTSCPart2(struct DCTStatStruc *pDCTstat); -#endif diff --git a/src/northbridge/amd/amdmct/mct/mct_d.c b/src/northbridge/amd/amdmct/mct/mct_d.c deleted file mode 100644 index 60a2c66de3..0000000000 --- a/src/northbridge/amd/amdmct/mct/mct_d.c +++ /dev/null @@ -1,3980 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2015-2017 Timothy Pearson , Raptor Engineering - * Copyright (C) 2007-2008 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -/* Description: Main memory controller system configuration for DDR 2 */ - - -/* KNOWN ISSUES - ERRATA - * - * Trtp is not calculated correctly when the controller is in 64-bit mode, it - * is 1 busclock off. No fix planned. The controller is not ordinarily in - * 64-bit mode. - * - * 32 Byte burst not supported. No fix planned. The controller is not - * ordinarily in 64-bit mode. - * - * Trc precision does not use extra Jedec defined fractional component. - * Instead Trc (course) is rounded up to nearest 1 ns. - * - * Mini and Micro DIMM not supported. Only RDIMM, UDIMM, SO-DIMM defined types - * supported. - */ - -#include -#include -#include -#include - -#include "mct_d.h" - -static u8 ReconfigureDIMMspare_D(struct MCTStatStruc *pMCTstat, - struct DCTStatStruc *pDCTstatA); -static void DQSTiming_D(struct MCTStatStruc *pMCTstat, - struct DCTStatStruc *pDCTstatA); -static void LoadDQSSigTmgRegs_D(struct MCTStatStruc *pMCTstat, - struct DCTStatStruc *pDCTstatA); -static void HTMemMapInit_D(struct MCTStatStruc *pMCTstat, - struct DCTStatStruc *pDCTstatA); -static void DCTMemClr_Sync_D(struct MCTStatStruc *pMCTstat, - struct DCTStatStruc *pDCTstat); -static void SyncDCTsReady_D(struct MCTStatStruc *pMCTstat, - struct DCTStatStruc *pDCTstatA); -static void StartupDCT_D(struct MCTStatStruc *pMCTstat, - struct DCTStatStruc *pDCTstat, u8 dct); -static void ClearDCT_D(struct MCTStatStruc *pMCTstat, - struct DCTStatStruc *pDCTstat, u8 dct); -static u8 AutoCycTiming_D(struct MCTStatStruc *pMCTstat, - struct DCTStatStruc *pDCTstat, u8 dct); -static void GetPresetmaxF_D(struct MCTStatStruc *pMCTstat, - struct DCTStatStruc *pDCTstat); -static void SPDGetTCL_D(struct MCTStatStruc *pMCTstat, - struct DCTStatStruc *pDCTstat, u8 dct); -static u8 AutoConfig_D(struct MCTStatStruc *pMCTstat, - struct DCTStatStruc *pDCTstat, u8 dct); -static u8 PlatformSpec_D(struct MCTStatStruc *pMCTstat, - struct DCTStatStruc *pDCTstat, u8 dct); -static u8 mct_PlatformSpec(struct MCTStatStruc *pMCTstat, - struct DCTStatStruc *pDCTstat, u8 dct); -static void SPDSetBanks_D(struct MCTStatStruc *pMCTstat, - struct DCTStatStruc *pDCTstat, u8 dct); -static void StitchMemory_D(struct MCTStatStruc *pMCTstat, - struct DCTStatStruc *pDCTstat, u8 dct); -static u8 Get_DefTrc_k_D(u8 k); -static u16 Get_40Tk_D(u8 k); -static u16 Get_Fk_D(u8 k); -static u8 Dimm_Supports_D(struct DCTStatStruc *pDCTstat, u8 i, u8 j, u8 k); -static u8 Sys_Capability_D(struct MCTStatStruc *pMCTstat, - struct DCTStatStruc *pDCTstat, int j, int k); -static u8 Get_DIMMAddress_D(struct DCTStatStruc *pDCTstat, u8 i); -static void mct_initDCT(struct MCTStatStruc *pMCTstat, - struct DCTStatStruc *pDCTstat); -static void mct_DramInit(struct MCTStatStruc *pMCTstat, - struct DCTStatStruc *pDCTstat, u8 dct); -static void mct_SyncDCTsReady(struct DCTStatStruc *pDCTstat); -static void Get_Trdrd(struct MCTStatStruc *pMCTstat, - struct DCTStatStruc *pDCTstat, u8 dct); -static void mct_AfterGetCLT(struct MCTStatStruc *pMCTstat, - struct DCTStatStruc *pDCTstat, u8 dct); -static u8 mct_SPDCalcWidth(struct MCTStatStruc *pMCTstat,\ - struct DCTStatStruc *pDCTstat, u8 dct); -static void mct_AfterStitchMemory(struct MCTStatStruc *pMCTstat, - struct DCTStatStruc *pDCTstat, u8 dct); -static u8 mct_DIMMPresence(struct MCTStatStruc *pMCTstat, - struct DCTStatStruc *pDCTstat, u8 dct); -static void Set_OtherTiming(struct MCTStatStruc *pMCTstat, - struct DCTStatStruc *pDCTstat, u8 dct); -static void Get_Twrwr(struct MCTStatStruc *pMCTstat, - struct DCTStatStruc *pDCTstat, u8 dct); -static void Get_Twrrd(struct MCTStatStruc *pMCTstat, - struct DCTStatStruc *pDCTstat, u8 dct); -static void Get_TrwtTO(struct MCTStatStruc *pMCTstat, - struct DCTStatStruc *pDCTstat, u8 dct); -static void Get_TrwtWB(struct MCTStatStruc *pMCTstat, - struct DCTStatStruc *pDCTstat); -static u8 Check_DqsRcvEn_Diff(struct DCTStatStruc *pDCTstat, u8 dct, - u32 dev, u32 index_reg, u32 index); -static u8 Get_DqsRcvEnGross_Diff(struct DCTStatStruc *pDCTstat, - u32 dev, u32 index_reg); -static u8 Get_WrDatGross_Diff(struct DCTStatStruc *pDCTstat, u8 dct, - u32 dev, u32 index_reg); -static u16 Get_DqsRcvEnGross_MaxMin(struct DCTStatStruc *pDCTstat, - u32 dev, u32 index_reg, u32 index); -static void mct_FinalMCT_D(struct MCTStatStruc *pMCTstat, - struct DCTStatStruc *pDCTstat); -static u16 Get_WrDatGross_MaxMin(struct DCTStatStruc *pDCTstat, u8 dct, - u32 dev, u32 index_reg, u32 index); -static void mct_InitialMCT_D(struct MCTStatStruc *pMCTstat, - struct DCTStatStruc *pDCTstat); -static void mct_init(struct MCTStatStruc *pMCTstat, - struct DCTStatStruc *pDCTstat); -static void clear_legacy_Mode(struct MCTStatStruc *pMCTstat, - struct DCTStatStruc *pDCTstat); -static void mct_HTMemMapExt(struct MCTStatStruc *pMCTstat, - struct DCTStatStruc *pDCTstatA); -static void SetCSTriState(struct MCTStatStruc *pMCTstat, - struct DCTStatStruc *pDCTstat, u8 dct); -static void SetODTTriState(struct MCTStatStruc *pMCTstat, - struct DCTStatStruc *pDCTstat, u8 dct); -static void InitPhyCompensation(struct MCTStatStruc *pMCTstat, - struct DCTStatStruc *pDCTstat, u8 dct); -static u32 mct_NodePresent_D(void); -static void WaitRoutine_D(u32 time); -static void mct_OtherTiming(struct MCTStatStruc *pMCTstat, - struct DCTStatStruc *pDCTstatA); -static void mct_ResetDataStruct_D(struct MCTStatStruc *pMCTstat, - struct DCTStatStruc *pDCTstatA); -static void mct_EarlyArbEn_D(struct MCTStatStruc *pMCTstat, - struct DCTStatStruc *pDCTstat); -static void mct_BeforeDramInit_Prod_D(struct MCTStatStruc *pMCTstat, - struct DCTStatStruc *pDCTstat); -void mct_ClrClToNB_D(struct MCTStatStruc *pMCTstat, - struct DCTStatStruc *pDCTstat); -static u8 CheckNBCOFEarlyArbEn(struct MCTStatStruc *pMCTstat, - struct DCTStatStruc *pDCTstat); -void mct_ClrWbEnhWsbDis_D(struct MCTStatStruc *pMCTstat, - struct DCTStatStruc *pDCTstat); -static void mct_BeforeDQSTrain_D(struct MCTStatStruc *pMCTstat, - struct DCTStatStruc *pDCTstatA); -static void AfterDramInit_D(struct DCTStatStruc *pDCTstat, u8 dct); -static void mct_ResetDLL_D(struct MCTStatStruc *pMCTstat, - struct DCTStatStruc *pDCTstat, u8 dct); -static u32 mct_DisDllShutdownSR(struct MCTStatStruc *pMCTstat, - struct DCTStatStruc *pDCTstat, u32 DramConfigLo, u8 dct); -static void mct_EnDllShutdownSR(struct MCTStatStruc *pMCTstat, - struct DCTStatStruc *pDCTstat, u8 dct); - -/*See mctAutoInitMCT header for index relationships to CL and T*/ -static const u16 Table_F_k[] = {00,200,266,333,400,533 }; -static const u8 Table_T_k[] = {0x00,0x50,0x3D,0x30,0x25, 0x18 }; -static const u8 Table_CL2_j[] = {0x04,0x08,0x10,0x20,0x40, 0x80 }; -static const u8 Tab_defTrc_k[] = {0x0,0x41,0x3C,0x3C,0x3A, 0x3A }; -static const u16 Tab_40T_k[] = {00,200,150,120,100,75 }; -static const u8 Tab_BankAddr[] = {0x0,0x08,0x09,0x10,0x0C,0x0D,0x11,0x0E,0x15,0x16,0x0F,0x17}; -static const u8 Tab_tCL_j[] = {0,2,3,4,5}; -static const u8 Tab_1KTfawT_k[] = {00,8,10,13,14,20}; -static const u8 Tab_2KTfawT_k[] = {00,10,14,17,18,24}; -static const u8 Tab_L1CLKDis[] = {8,8,6,4,2,0,8,8}; -static const u8 Tab_M2CLKDis[] = {2,0,8,8,2,0,2,0}; -static const u8 Tab_S1CLKDis[] = {8,0,8,8,8,0,8,0}; -static const u8 Table_Comp_Rise_Slew_20x[] = {7, 3, 2, 2, 0xFF}; -static const u8 Table_Comp_Rise_Slew_15x[] = {7, 7, 3, 2, 0xFF}; -static const u8 Table_Comp_Fall_Slew_20x[] = {7, 5, 3, 2, 0xFF}; -static const u8 Table_Comp_Fall_Slew_15x[] = {7, 7, 5, 3, 0xFF}; - -const u8 Table_DQSRcvEn_Offset[] = {0x00,0x01,0x10,0x11,0x2}; - -void mctAutoInitMCT_D(struct MCTStatStruc *pMCTstat, - struct DCTStatStruc *pDCTstatA) -{ - /* - * Memory may be mapped contiguously all the way up to 4GB (depending - * on setup options). It is the responsibility of PCI subsystem to - * create an uncacheable IO region below 4GB and to adjust TOP_MEM - * downward prior to any IO mapping or accesses. It is the same - * responsibility of the CPU sub-system prior to accessing LAPIC. - * - * Slot Number is an external convention, and is determined by OEM with - * accompanying silk screening. OEM may choose to use Slot number - * convention which is consistent with DIMM number conventions. - * All AMD engineering - * platforms do. - * - * Run-Time Requirements: - * 1. Complete Hypertransport Bus Configuration - * 2. SMBus Controller Initialized - * 3. Checksummed or Valid NVRAM bits - * 4. MCG_CTL=-1, MC4_CTL_EN = 0 for all CPUs - * 5. MCi_STS from shutdown/warm reset recorded (if desired) prior to - * entry - * 6. All var MTRRs reset to zero - * 7. State of NB_CFG.DisDatMsk set properly on all CPUs - * 8. All CPUs at 2GHz Speed (unless DQS training is not installed). - * 9. All cHT links at max Speed/Width (unless DQS training is not - * installed). - * - * - * Global relationship between index values and item values: - * j CL(j) k F(k) - * -------------------------- - * 0 2.0 - - - * 1 3.0 1 200 MHz - * 2 4.0 2 266 MHz - * 3 5.0 3 333 MHz - * 4 6.0 4 400 MHz - * 5 7.0 5 533 MHz - */ - u8 Node, NodesWmem; - u32 node_sys_base; - -restartinit: - mctInitMemGPIOs_A_D(); /* Set any required GPIOs*/ - NodesWmem = 0; - node_sys_base = 0; - for (Node = 0; Node < MAX_NODES_SUPPORTED; Node++) { - struct DCTStatStruc *pDCTstat; - pDCTstat = pDCTstatA + Node; - pDCTstat->Node_ID = Node; - pDCTstat->dev_host = PA_HOST(Node); - pDCTstat->dev_map = PA_MAP(Node); - pDCTstat->dev_dct = PA_DCT(Node); - pDCTstat->dev_nbmisc = PA_NBMISC(Node); - pDCTstat->NodeSysBase = node_sys_base; - - if (mctGet_NVbits(NV_PACK_TYPE) == PT_GR) { - uint32_t dword; - pDCTstat->Dual_Node_Package = 1; - - /* Get the internal node number */ - dword = Get_NB32(pDCTstat->dev_nbmisc, 0xe8); - dword = (dword >> 30) & 0x3; - pDCTstat->Internal_Node_ID = dword; - } else { - pDCTstat->Dual_Node_Package = 0; - } - - print_tx("mctAutoInitMCT_D: mct_init Node ", Node); - mct_init(pMCTstat, pDCTstat); - mctNodeIDDebugPort_D(); - pDCTstat->NodePresent = NodePresent_D(Node); - if (pDCTstat->NodePresent) { /* See if Node is there*/ - print_t("mctAutoInitMCT_D: clear_legacy_Mode\n"); - clear_legacy_Mode(pMCTstat, pDCTstat); - pDCTstat->LogicalCPUID = mctGetLogicalCPUID_D(Node); - - print_t("mctAutoInitMCT_D: mct_InitialMCT_D\n"); - mct_InitialMCT_D(pMCTstat, pDCTstat); - - print_t("mctAutoInitMCT_D: mctSMBhub_Init\n"); - mctSMBhub_Init(Node); /* Switch SMBUS crossbar to proper node*/ - - print_t("mctAutoInitMCT_D: mct_initDCT\n"); - mct_initDCT(pMCTstat, pDCTstat); - if (pDCTstat->ErrCode == SC_FatalErr) { - goto fatalexit; /* any fatal errors?*/ - } else if (pDCTstat->ErrCode < SC_StopError) { - NodesWmem++; - } - } /* if Node present */ - node_sys_base = pDCTstat->NodeSysBase; - node_sys_base += (pDCTstat->NodeSysLimit + 2) & ~0x0F; - } - if (NodesWmem == 0) { - printk(BIOS_DEBUG, "No Nodes?!\n"); - goto fatalexit; - } - - print_t("mctAutoInitMCT_D: SyncDCTsReady_D\n"); - SyncDCTsReady_D(pMCTstat, pDCTstatA); /* Make sure DCTs are ready for accesses.*/ - - print_t("mctAutoInitMCT_D: HTMemMapInit_D\n"); - HTMemMapInit_D(pMCTstat, pDCTstatA); /* Map local memory into system address space.*/ - mctHookAfterHTMap(); - - print_t("mctAutoInitMCT_D: CPUMemTyping_D\n"); - CPUMemTyping_D(pMCTstat, pDCTstatA); /* Map dram into WB/UC CPU cacheability */ - mctHookAfterCPU(); /* Setup external northbridge(s) */ - - print_t("mctAutoInitMCT_D: DQSTiming_D\n"); - DQSTiming_D(pMCTstat, pDCTstatA); /* Get Receiver Enable and DQS signal timing*/ - - print_t("mctAutoInitMCT_D: UMAMemTyping_D\n"); - UMAMemTyping_D(pMCTstat, pDCTstatA); /* Fix up for UMA sizing */ - - print_t("mctAutoInitMCT_D: :OtherTiming\n"); - mct_OtherTiming(pMCTstat, pDCTstatA); - - if (ReconfigureDIMMspare_D(pMCTstat, pDCTstatA)) { /* RESET# if 1st pass of DIMM spare enabled*/ - goto restartinit; - } - - InterleaveNodes_D(pMCTstat, pDCTstatA); - InterleaveChannels_D(pMCTstat, pDCTstatA); - - print_t("mctAutoInitMCT_D: ECCInit_D\n"); - if (ECCInit_D(pMCTstat, pDCTstatA)) { /* Setup ECC control and ECC check-bits*/ - print_t("mctAutoInitMCT_D: MCTMemClr_D\n"); - MCTMemClr_D(pMCTstat,pDCTstatA); - } - - mct_FinalMCT_D(pMCTstat, (pDCTstatA + 0)); // Node 0 - print_tx("mctAutoInitMCT_D Done: Global Status: ", pMCTstat->GStatus); - return; - -fatalexit: - die("mct_d: fatalexit"); -} - - -static u8 ReconfigureDIMMspare_D(struct MCTStatStruc *pMCTstat, - struct DCTStatStruc *pDCTstatA) -{ - u8 ret; - - if (mctGet_NVbits(NV_CS_SpareCTL)) { - if (MCT_DIMM_SPARE_NO_WARM) { - /* Do no warm-reset DIMM spare */ - if (pMCTstat->GStatus & (1 << GSB_EnDIMMSpareNW)) { - LoadDQSSigTmgRegs_D(pMCTstat, pDCTstatA); - ret = 0; - } else { - mct_ResetDataStruct_D(pMCTstat, pDCTstatA); - pMCTstat->GStatus |= 1 << GSB_EnDIMMSpareNW; - ret = 1; - } - } else { - /* Do warm-reset DIMM spare */ - if (mctGet_NVbits(NV_DQSTrainCTL)) - mctWarmReset_D(); - ret = 0; - } - - - } else { - ret = 0; - } - - return ret; -} - - -static void DQSTiming_D(struct MCTStatStruc *pMCTstat, - struct DCTStatStruc *pDCTstatA) -{ - u8 nv_DQSTrainCTL; - - if (pMCTstat->GStatus & (1 << GSB_EnDIMMSpareNW)) { - return; - } - nv_DQSTrainCTL = mctGet_NVbits(NV_DQSTrainCTL); - /* FIXME: BOZO- DQS training every time*/ - nv_DQSTrainCTL = 1; - - print_t("DQSTiming_D: mct_BeforeDQSTrain_D:\n"); - mct_BeforeDQSTrain_D(pMCTstat, pDCTstatA); - phyAssistedMemFnceTraining(pMCTstat, pDCTstatA); - - if (nv_DQSTrainCTL) { - mctHookBeforeAnyTraining(pMCTstat, pDCTstatA); - - print_t("DQSTiming_D: TrainReceiverEn_D FirstPass:\n"); - TrainReceiverEn_D(pMCTstat, pDCTstatA, FirstPass); - - print_t("DQSTiming_D: mct_TrainDQSPos_D\n"); - mct_TrainDQSPos_D(pMCTstat, pDCTstatA); - - // Second Pass never used for Barcelona! - //print_t("DQSTiming_D: TrainReceiverEn_D SecondPass:\n"); - //TrainReceiverEn_D(pMCTstat, pDCTstatA, SecondPass); - - print_t("DQSTiming_D: mctSetEccDQSRcvrEn_D\n"); - mctSetEccDQSRcvrEn_D(pMCTstat, pDCTstatA); - - print_t("DQSTiming_D: TrainMaxReadLatency_D\n"); -//FIXME - currently uses calculated value TrainMaxReadLatency_D(pMCTstat, pDCTstatA); - mctHookAfterAnyTraining(); - mctSaveDQSSigTmg_D(); - - print_t("DQSTiming_D: mct_EndDQSTraining_D\n"); - mct_EndDQSTraining_D(pMCTstat, pDCTstatA); - - print_t("DQSTiming_D: MCTMemClr_D\n"); - MCTMemClr_D(pMCTstat, pDCTstatA); - } else { - mctGetDQSSigTmg_D(); /* get values into data structure */ - LoadDQSSigTmgRegs_D(pMCTstat, pDCTstatA); /* load values into registers.*/ - //mctDoWarmResetMemClr_D(); - MCTMemClr_D(pMCTstat, pDCTstatA); - } -} - - -static void LoadDQSSigTmgRegs_D(struct MCTStatStruc *pMCTstat, - struct DCTStatStruc *pDCTstatA) -{ - u8 Node, Receiver, Channel, Dir, DIMM; - u32 dev; - u32 index_reg; - u32 reg; - u32 index; - u32 val; - - - for (Node = 0; Node < MAX_NODES_SUPPORTED; Node++) { - struct DCTStatStruc *pDCTstat; - pDCTstat = pDCTstatA + Node; - - if (pDCTstat->DCTSysLimit) { - dev = pDCTstat->dev_dct; - for (Channel = 0;Channel < 2; Channel++) { - /* there are four receiver pairs, - loosely associated with chipselects.*/ - index_reg = 0x98 + Channel * 0x100; - for (Receiver = 0; Receiver < 8; Receiver += 2) { - /* Set Receiver Enable Values */ - mct_SetRcvrEnDly_D(pDCTstat, - 0, /* RcvrEnDly */ - 1, /* FinalValue, From stack */ - Channel, - Receiver, - dev, index_reg, - (Receiver >> 1) * 3 + 0x10, /* Addl_Index */ - 2); /* Pass Second Pass ? */ - - } - } - for (Channel = 0; Channel < 2; Channel++) { - SetEccDQSRcvrEn_D(pDCTstat, Channel); - } - - for (Channel = 0; Channel < 2; Channel++) { - u8 *p; - index_reg = 0x98 + Channel * 0x100; - - /* NOTE: - * when 400, 533, 667, it will support dimm0/1/2/3, - * and set conf for dimm0, hw will copy to dimm1/2/3 - * set for dimm1, hw will copy to dimm3 - * Rev A/B only support DIMM0/1 when 800MHz and above - * + 0x100 to next dimm - * Rev C support DIMM0/1/2/3 when 800MHz and above - * + 0x100 to next dimm - */ - for (DIMM = 0; DIMM < 2; DIMM++) { - if (DIMM == 0) { - index = 0; /* CHA Write Data Timing Low */ - } else { - if (pDCTstat->Speed >= 4) { - index = 0x100 * DIMM; - } else { - break; - } - } - for (Dir = 0; Dir < 2; Dir++) {//RD/WR - p = pDCTstat->persistentData.CH_D_DIR_B_DQS[Channel][DIMM][Dir]; - val = stream_to_int(p); /* CHA Read Data Timing High */ - Set_NB32_index_wait(dev, index_reg, index+1, val); - val = stream_to_int(p+4); /* CHA Write Data Timing High */ - Set_NB32_index_wait(dev, index_reg, index+2, val); - val = *(p+8); /* CHA Write ECC Timing */ - Set_NB32_index_wait(dev, index_reg, index+3, val); - index += 4; - } - } - } - - for (Channel = 0; Channel < 2; Channel++) { - reg = 0x78 + Channel * 0x100; - val = Get_NB32(dev, reg); - val &= ~(0x3ff<<22); - val |= ((u32) pDCTstat->CH_MaxRdLat[Channel] << 22); - val &= ~(1 << DqsRcvEnTrain); - Set_NB32(dev, reg, val); /* program MaxRdLatency to correspond with current delay*/ - } - } - } -} - -#ifdef UNUSED_CODE -static void ResetNBECCstat_D(struct MCTStatStruc *pMCTstat, - struct DCTStatStruc *pDCTstatA); -static void ResetNBECCstat_D(struct MCTStatStruc *pMCTstat, - struct DCTStatStruc *pDCTstatA) -{ - /* Clear MC4_STS for all Nodes in the system. This is required in some - * circumstances to clear left over garbage from cold reset, shutdown, - * or normal ECC memory conditioning. - */ - - //FIXME: this function depends on pDCTstat Array (with Node id) - Is this really a problem? - - u32 dev; - u8 Node; - - for (Node = 0; Node < MAX_NODES_SUPPORTED; Node++) { - struct DCTStatStruc *pDCTstat; - pDCTstat = pDCTstatA + Node; - - if (pDCTstat->NodePresent) { - dev = pDCTstat->dev_nbmisc; - /*MCA NB Status Low (alias to MC4_STS[31:0] */ - Set_NB32(dev, 0x48, 0); - /* MCA NB Status High (alias to MC4_STS[63:32] */ - Set_NB32(dev, 0x4C, 0); - } - } -} -#endif - -static void HTMemMapInit_D(struct MCTStatStruc *pMCTstat, - struct DCTStatStruc *pDCTstatA) -{ - u8 Node; - u32 NextBase, BottomIO; - u8 _MemHoleRemap, DramHoleBase; - u32 HoleSize, DramSelBaseAddr; - - u32 val; - u32 base; - u32 limit; - u32 dev, devx; - struct DCTStatStruc *pDCTstat; - - _MemHoleRemap = mctGet_NVbits(NV_MemHole); - - if (pMCTstat->HoleBase == 0) { - DramHoleBase = mctGet_NVbits(NV_BottomIO); - } else { - DramHoleBase = pMCTstat->HoleBase >> (24-8); - } - - BottomIO = DramHoleBase << (24-8); - - NextBase = 0; - pDCTstat = pDCTstatA + 0; - dev = pDCTstat->dev_map; - - - for (Node = 0; Node < MAX_NODES_SUPPORTED; Node++) { - pDCTstat = pDCTstatA + Node; - devx = pDCTstat->dev_map; - DramSelBaseAddr = 0; - if (!pDCTstat->GangedMode) { - DramSelBaseAddr = pDCTstat->NodeSysLimit - pDCTstat->DCTSysLimit; - /*In unganged mode, we must add DCT0 and DCT1 to DCTSysLimit */ - val = pDCTstat->NodeSysLimit; - if ((val & 0xFF) == 0xFE) { - DramSelBaseAddr++; - val++; - } - pDCTstat->DCTSysLimit = val; - } - - base = pDCTstat->DCTSysBase; - limit = pDCTstat->DCTSysLimit; - if (limit > base) { - base += NextBase; - limit += NextBase; - DramSelBaseAddr += NextBase; - printk(BIOS_DEBUG, " Node: %02x base: %02x limit: %02x BottomIO: %02x\n", Node, base, limit, BottomIO); - - if (_MemHoleRemap) { - if ((base < BottomIO) && (limit >= BottomIO)) { - /* HW Dram Remap */ - pDCTstat->Status |= 1 << SB_HWHole; - pMCTstat->GStatus |= 1 << GSB_HWHole; - pDCTstat->DCTSysBase = base; - pDCTstat->DCTSysLimit = limit; - pDCTstat->DCTHoleBase = BottomIO; - pMCTstat->HoleBase = BottomIO; - HoleSize = _4GB_RJ8 - BottomIO; /* HoleSize[39:8] */ - if ((DramSelBaseAddr > 0) && (DramSelBaseAddr < BottomIO)) - base = DramSelBaseAddr; - val = ((base + HoleSize) >> (24-8)) & 0xFF; - val <<= 8; /* shl 16, rol 24 */ - val |= DramHoleBase << 24; - val |= 1 << DramHoleValid; - Set_NB32(devx, 0xF0, val); /* Dram Hole Address Reg */ - pDCTstat->DCTSysLimit += HoleSize; - base = pDCTstat->DCTSysBase; - limit = pDCTstat->DCTSysLimit; - } else if (base == BottomIO) { - /* SW Node Hoist */ - pMCTstat->GStatus |= 1 << GSB_SpIntRemapHole; - pDCTstat->Status |= 1 << SB_SWNodeHole; - pMCTstat->GStatus |= 1 << GSB_SoftHole; - pMCTstat->HoleBase = base; - limit -= base; - base = _4GB_RJ8; - limit += base; - pDCTstat->DCTSysBase = base; - pDCTstat->DCTSysLimit = limit; - } else { - /* No Remapping. Normal Contiguous mapping */ - pDCTstat->DCTSysBase = base; - pDCTstat->DCTSysLimit = limit; - } - } else { - /*No Remapping. Normal Contiguous mapping*/ - pDCTstat->DCTSysBase = base; - pDCTstat->DCTSysLimit = limit; - } - base |= 3; /* set WE,RE fields*/ - pMCTstat->SysLimit = limit; - } - Set_NB32(dev, 0x40 + (Node << 3), base); /* [Node] + Dram Base 0 */ - - /* if Node limit > 1GB then set it to 1GB boundary for each node */ - if ((mctSetNodeBoundary_D()) && (limit > 0x00400000)) { - limit++; - limit &= 0xFFC00000; - limit--; - } - val = limit & 0xFFFF0000; - val |= Node; - Set_NB32(dev, 0x44 + (Node << 3), val); /* set DstNode */ - - limit = pDCTstat->DCTSysLimit; - if (limit) { - NextBase = (limit & 0xFFFF0000) + 0x10000; - if ((mctSetNodeBoundary_D()) && (NextBase > 0x00400000)) { - NextBase++; - NextBase &= 0xFFC00000; - NextBase--; - } - } - } - - /* Copy dram map from Node 0 to Node 1-7 */ - for (Node = 1; Node < MAX_NODES_SUPPORTED; Node++) { - u32 reg; - pDCTstat = pDCTstatA + Node; - devx = pDCTstat->dev_map; - - if (pDCTstat->NodePresent) { - printk(BIOS_DEBUG, " Copy dram map from Node 0 to Node %02x\n", Node); - reg = 0x40; /*Dram Base 0*/ - do { - val = Get_NB32(dev, reg); - Set_NB32(devx, reg, val); - reg += 4; - } while (reg < 0x80); - } else { - break; /* stop at first absent Node */ - } - } - - /*Copy dram map to F1x120/124*/ - mct_HTMemMapExt(pMCTstat, pDCTstatA); -} - - -void MCTMemClr_D(struct MCTStatStruc *pMCTstat, - struct DCTStatStruc *pDCTstatA) -{ - - /* Initiates a memory clear operation for all node. The mem clr - * is done in parallel. After the memclr is complete, all processors - * status are checked to ensure that memclr has completed. - */ - u8 Node; - struct DCTStatStruc *pDCTstat; - - if (!mctGet_NVbits(NV_DQSTrainCTL)) { - // FIXME: callback to wrapper: mctDoWarmResetMemClr_D - } else { // NV_DQSTrainCTL == 1 - for (Node = 0; Node < MAX_NODES_SUPPORTED; Node++) { - pDCTstat = pDCTstatA + Node; - - if (pDCTstat->NodePresent) { - DCTMemClr_Init_D(pMCTstat, pDCTstat); - } - } - for (Node = 0; Node < MAX_NODES_SUPPORTED; Node++) { - pDCTstat = pDCTstatA + Node; - - if (pDCTstat->NodePresent) { - DCTMemClr_Sync_D(pMCTstat, pDCTstat); - } - } - } -} - - -void DCTMemClr_Init_D(struct MCTStatStruc *pMCTstat, - struct DCTStatStruc *pDCTstat) -{ - u32 val; - u32 dev; - u32 reg; - - /* Initiates a memory clear operation on one node */ - if (pDCTstat->DCTSysLimit) { - dev = pDCTstat->dev_dct; - reg = 0x110; - - do { - val = Get_NB32(dev, reg); - } while (val & (1 << MemClrBusy)); - - val |= (1 << MemClrInit); - Set_NB32(dev, reg, val); - - } -} - - -void MCTMemClrSync_D(struct MCTStatStruc *pMCTstat, - struct DCTStatStruc *pDCTstatA) -{ - /* Ensures that memory clear has completed on all node.*/ - u8 Node; - struct DCTStatStruc *pDCTstat; - - if (!mctGet_NVbits(NV_DQSTrainCTL)) { - // callback to wrapper: mctDoWarmResetMemClr_D - } else { // NV_DQSTrainCTL == 1 - for (Node = 0; Node < MAX_NODES_SUPPORTED; Node++) { - pDCTstat = pDCTstatA + Node; - - if (pDCTstat->NodePresent) { - DCTMemClr_Sync_D(pMCTstat, pDCTstat); - } - } - } -} - - -static void DCTMemClr_Sync_D(struct MCTStatStruc *pMCTstat, - struct DCTStatStruc *pDCTstat) -{ - u32 val; - u32 dev = pDCTstat->dev_dct; - u32 reg; - - /* Ensure that a memory clear operation has completed on one node */ - if (pDCTstat->DCTSysLimit) { - reg = 0x110; - - do { - val = Get_NB32(dev, reg); - } while (val & (1 << MemClrBusy)); - - do { - val = Get_NB32(dev, reg); - } while (!(val & (1 << Dr_MemClrStatus))); - } - - /* Implement BKDG Rev 3.62 recommendations */ - val = 0x0FE40F80; - if (!(mctGetLogicalCPUID(0) & AMD_FAM10_LT_D) && mctGet_NVbits(NV_Unganged)) - val |= (0x18 << 2); - else - val |= (0x10 << 2); - val |= MCCH_FlushWrOnStpGnt; // Set for S3 - Set_NB32(dev, 0x11C, val); -} - - -u8 NodePresent_D(u8 Node) -{ - /* - * Determine if a single Hammer Node exists within the network. - */ - - u32 dev; - u32 val; - u32 dword; - u8 ret = 0; - - dev = PA_HOST(Node); /*test device/vendor id at host bridge */ - val = Get_NB32(dev, 0); - dword = mct_NodePresent_D(); /* FIXME: BOZO -11001022h rev for F */ - if (val == dword) { /* AMD Hammer Family CPU HT Configuration */ - if (oemNodePresent_D(Node, &ret)) - goto finish; - /* Node ID register */ - val = Get_NB32(dev, 0x60); - val &= 0x07; - dword = Node; - if (val == dword) /* current nodeID = requested nodeID ? */ - ret = 1; -finish: - ; - } - - return ret; -} - - -static void DCTInit_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstat, u8 dct) -{ - /* - * Initialize DRAM on single Athlon 64/Opteron Node. - */ - - u8 stopDCTflag; - u32 val; - - ClearDCT_D(pMCTstat, pDCTstat, dct); - stopDCTflag = 1; /*preload flag with 'disable' */ - if (mct_DIMMPresence(pMCTstat, pDCTstat, dct) < SC_StopError) { - print_t("\t\tDCTInit_D: mct_DIMMPresence Done\n"); - if (mct_SPDCalcWidth(pMCTstat, pDCTstat, dct) < SC_StopError) { - print_t("\t\tDCTInit_D: mct_SPDCalcWidth Done\n"); - if (AutoCycTiming_D(pMCTstat, pDCTstat, dct) < SC_StopError) { - print_t("\t\tDCTInit_D: AutoCycTiming_D Done\n"); - if (AutoConfig_D(pMCTstat, pDCTstat, dct) < SC_StopError) { - print_t("\t\tDCTInit_D: AutoConfig_D Done\n"); - if (PlatformSpec_D(pMCTstat, pDCTstat, dct) < SC_StopError) { - print_t("\t\tDCTInit_D: PlatformSpec_D Done\n"); - stopDCTflag = 0; - if (!(pMCTstat->GStatus & (1 << GSB_EnDIMMSpareNW))) { - print_t("\t\tDCTInit_D: StartupDCT_D\n"); - StartupDCT_D(pMCTstat, pDCTstat, dct); /*yeaahhh! */ - } - } - } - } - } - } - if (stopDCTflag) { - u32 reg_off = dct * 0x100; - val = 1<dev_dct, reg_off+0x94, val); - /*To maximize power savings when DisDramInterface = 1b, - all of the MemClkDis bits should also be set.*/ - val = 0xFF000000; - Set_NB32(pDCTstat->dev_dct, reg_off+0x88, val); - } else { - mct_EnDllShutdownSR(pMCTstat, pDCTstat, dct); - } -} - - -static void SyncDCTsReady_D(struct MCTStatStruc *pMCTstat, - struct DCTStatStruc *pDCTstatA) -{ - /* Wait (and block further access to dram) for all DCTs to be ready, - * by polling all InitDram bits and waiting for possible memory clear - * operations to be complete. Read MemClkFreqVal bit to see if - * the DIMMs are present in this node. - */ - - u8 Node; - - for (Node = 0; Node < MAX_NODES_SUPPORTED; Node++) { - struct DCTStatStruc *pDCTstat; - pDCTstat = pDCTstatA + Node; - mct_SyncDCTsReady(pDCTstat); - } -} - - -static void StartupDCT_D(struct MCTStatStruc *pMCTstat, - struct DCTStatStruc *pDCTstat, u8 dct) -{ - /* Read MemClkFreqVal bit to see if the DIMMs are present in this node. - * If the DIMMs are present then set the DRAM Enable bit for this node. - * - * Setting dram init starts up the DCT state machine, initializes the - * dram devices with MRS commands, and kicks off any - * HW memory clear process that the chip is capable of. The sooner - * that dram init is set for all nodes, the faster the memory system - * initialization can complete. Thus, the init loop is unrolled into - * two loops so as to start the processes for non BSP nodes sooner. - * This procedure will not wait for the process to finish. - * Synchronization is handled elsewhere. - */ - - u32 val; - u32 dev; - u8 byte; - u32 reg; - u32 reg_off = dct * 0x100; - - dev = pDCTstat->dev_dct; - val = Get_NB32(dev, 0x94 + reg_off); - if (val & (1 << MemClkFreqVal)) { - print_t("\t\t\tStartupDCT_D: MemClkFreqVal\n"); - byte = mctGet_NVbits(NV_DQSTrainCTL); - if (byte == 1) { - /* Enable DQSRcvEn training mode */ - print_t("\t\t\tStartupDCT_D: DqsRcvEnTrain set\n"); - reg = 0x78 + reg_off; - val = Get_NB32(dev, reg); - /* Setting this bit forces a 1T window with hard left - * pass/fail edge and a probabilistic right pass/fail - * edge. LEFT edge is referenced for final - * receiver enable position.*/ - val |= 1 << DqsRcvEnTrain; - Set_NB32(dev, reg, val); - } - mctHookBeforeDramInit(); /* generalized Hook */ - print_t("\t\t\tStartupDCT_D: DramInit\n"); - mct_DramInit(pMCTstat, pDCTstat, dct); - AfterDramInit_D(pDCTstat, dct); - mctHookAfterDramInit(); /* generalized Hook*/ - } -} - - -static void ClearDCT_D(struct MCTStatStruc *pMCTstat, - struct DCTStatStruc *pDCTstat, u8 dct) -{ - u32 reg_end; - u32 dev = pDCTstat->dev_dct; - u32 reg = 0x40 + 0x100 * dct; - u32 val = 0; - - if (pMCTstat->GStatus & (1 << GSB_EnDIMMSpareNW)) { - reg_end = 0x78 + 0x100 * dct; - } else { - reg_end = 0xA4 + 0x100 * dct; - } - - while (reg < reg_end) { - Set_NB32(dev, reg, val); - reg += 4; - } - - val = 0; - dev = pDCTstat->dev_map; - reg = 0xF0; - Set_NB32(dev, reg, val); -} - - -static u8 AutoCycTiming_D(struct MCTStatStruc *pMCTstat, - struct DCTStatStruc *pDCTstat, u8 dct) -{ - /* Initialize DCT Timing registers as per DIMM SPD. - * For primary timing (T, CL) use best case T value. - * For secondary timing params., use most aggressive settings - * of slowest DIMM. - * - * There are three components to determining "maximum frequency": - * SPD component, Bus load component, and "Preset" max frequency - * component. - * - * The SPD component is a function of the min cycle time specified - * by each DIMM, and the interaction of cycle times from all DIMMs - * in conjunction with CAS latency. The SPD component only applies - * when user timing mode is 'Auto'. - * - * The Bus load component is a limiting factor determined by electrical - * characteristics on the bus as a result of varying number of device - * loads. The Bus load component is specific to each platform but may - * also be a function of other factors. The bus load component only - * applies when user timing mode is 'Auto'. - * - * The Preset component is subdivided into three items and is the - * minimum of the set: Silicon revision, user limit setting when user - * timing mode is 'Auto' and memclock mode is 'Limit', OEM build - * specification of the maximum frequency. The Preset component is only - * applies when user timing mode is 'Auto'. - */ - - u8 i; - u8 Twr, Trtp; - u8 Trp, Trrd, Trcd, Tras, Trc, Trfc[4], Rows; - u32 DramTimingLo, DramTimingHi; - u16 Tk40; - u8 Twtr; - u8 LDIMM; - u8 DDR2_1066; - u8 byte; - u32 dword; - u32 dev; - u32 reg; - u32 reg_off; - u32 val; - u16 smbaddr; - - /* Get primary timing (CAS Latency and Cycle Time) */ - if (pDCTstat->Speed == 0) { - mctGet_MaxLoadFreq(pDCTstat); - - /* and Factor in presets (setup options, Si cap, etc.) */ - GetPresetmaxF_D(pMCTstat, pDCTstat); - - /* Go get best T and CL as specified by DIMM mfgs. and OEM */ - SPDGetTCL_D(pMCTstat, pDCTstat, dct); - /* skip callback mctForce800to1067_D */ - pDCTstat->Speed = pDCTstat->DIMMAutoSpeed; - pDCTstat->CASL = pDCTstat->DIMMCASL; - - /* if "manual" memclock mode */ - if (mctGet_NVbits(NV_MCTUSRTMGMODE) == 2) - pDCTstat->Speed = mctGet_NVbits(NV_MemCkVal) + 1; - - } - mct_AfterGetCLT(pMCTstat, pDCTstat, dct); - - /* Gather all DIMM mini-max values for cycle timing data */ - Rows = 0; - Trp = 0; - Trrd = 0; - Trcd = 0; - Trtp = 0; - Tras = 0; - Trc = 0; - Twr = 0; - Twtr = 0; - for (i = 0; i < 4; i++) - Trfc[i] = 0; - - for (i = 0; i< MAX_DIMMS_SUPPORTED; i++) { - LDIMM = i >> 1; - if (pDCTstat->DIMMValid & (1 << i)) { - smbaddr = Get_DIMMAddress_D(pDCTstat, dct + i); - byte = mctRead_SPD(smbaddr, SPD_ROWSZ); - if (Rows < byte) - Rows = byte; /* keep track of largest row sz */ - - byte = mctRead_SPD(smbaddr, SPD_TRP); - if (Trp < byte) - Trp = byte; - - byte = mctRead_SPD(smbaddr, SPD_TRRD); - if (Trrd < byte) - Trrd = byte; - - byte = mctRead_SPD(smbaddr, SPD_TRCD); - if (Trcd < byte) - Trcd = byte; - - byte = mctRead_SPD(smbaddr, SPD_TRTP); - if (Trtp < byte) - Trtp = byte; - - byte = mctRead_SPD(smbaddr, SPD_TWR); - if (Twr < byte) - Twr = byte; - - byte = mctRead_SPD(smbaddr, SPD_TWTR); - if (Twtr < byte) - Twtr = byte; - - val = mctRead_SPD(smbaddr, SPD_TRC); - if ((val == 0) || (val == 0xFF)) { - pDCTstat->ErrStatus |= 1<ErrCode = SC_VarianceErr; - val = Get_DefTrc_k_D(pDCTstat->Speed); - } else { - byte = mctRead_SPD(smbaddr, SPD_TRCRFC); - if (byte & 0xF0) { - val++; /* round up in case fractional extension is non-zero.*/ - } - } - if (Trc < val) - Trc = val; - - /* dev density = rank size/#devs per rank */ - byte = mctRead_SPD(smbaddr, SPD_BANKSZ); - - val = ((byte >> 5) | (byte << 3)) & 0xFF; - val <<= 2; - - byte = mctRead_SPD(smbaddr, SPD_DEVWIDTH) & 0xFE; /* dev density = 2^(rows+columns+banks) */ - if (byte == 4) { - val >>= 4; - } else if (byte == 8) { - val >>= 3; - } else if (byte == 16) { - val >>= 2; - } - - byte = bsr(val); - - if (Trfc[LDIMM] < byte) - Trfc[LDIMM] = byte; - - byte = mctRead_SPD(smbaddr, SPD_TRAS); - if (Tras < byte) - Tras = byte; - } /* Dimm Present */ - } - - /* Convert DRAM CycleTiming values and store into DCT structure */ - DDR2_1066 = 0; - byte = pDCTstat->Speed; - if (byte == 5) - DDR2_1066 = 1; - Tk40 = Get_40Tk_D(byte); - - /* Notes: - 1. All secondary time values given in SPDs are in binary with units of ns. - 2. Some time values are scaled by four, in order to have least count of 0.25 ns - (more accuracy). JEDEC SPD spec. shows which ones are x1 and x4. - 3. Internally to this SW, cycle time, Tk, is scaled by 10 to affect a - least count of 0.1 ns (more accuracy). - 4. SPD values not scaled are multiplied by 10 and then divided by 10T to find - equivalent minimum number of bus clocks (a remainder causes round-up of clocks). - 5. SPD values that are prescaled by 4 are multiplied by 10 and then divided by 40T to find - equivalent minimum number of bus clocks (a remainder causes round-up of clocks).*/ - - /* Tras */ - dword = Tras * 40; - pDCTstat->DIMMTras = (u16)dword; - val = dword / Tk40; - if (dword % Tk40) { /* round up number of busclocks */ - val++; - } - if (DDR2_1066) { - if (val < Min_TrasT_1066) - val = Min_TrasT_1066; - else if (val > Max_TrasT_1066) - val = Max_TrasT_1066; - } else { - if (val < Min_TrasT) - val = Min_TrasT; - else if (val > Max_TrasT) - val = Max_TrasT; - } - pDCTstat->Tras = val; - - /* Trp */ - dword = Trp * 10; - pDCTstat->DIMMTrp = dword; - val = dword / Tk40; - if (dword % Tk40) { /* round up number of busclocks */ - val++; - } - if (DDR2_1066) { - if (val < Min_TrasT_1066) - val = Min_TrpT_1066; - else if (val > Max_TrpT_1066) - val = Max_TrpT_1066; - } else { - if (val < Min_TrpT) - val = Min_TrpT; - else if (val > Max_TrpT) - val = Max_TrpT; - } - pDCTstat->Trp = val; - - /*Trrd*/ - dword = Trrd * 10; - pDCTstat->DIMMTrrd = dword; - val = dword / Tk40; - if (dword % Tk40) { /* round up number of busclocks */ - val++; - } - if (DDR2_1066) { - if (val < Min_TrrdT_1066) - val = Min_TrrdT_1066; - else if (val > Max_TrrdT_1066) - val = Max_TrrdT_1066; - } else { - if (val < Min_TrrdT) - val = Min_TrrdT; - else if (val > Max_TrrdT) - val = Max_TrrdT; - } - pDCTstat->Trrd = val; - - /* Trcd */ - dword = Trcd * 10; - pDCTstat->DIMMTrcd = dword; - val = dword / Tk40; - if (dword % Tk40) { /* round up number of busclocks */ - val++; - } - if (DDR2_1066) { - if (val < Min_TrcdT_1066) - val = Min_TrcdT_1066; - else if (val > Max_TrcdT_1066) - val = Max_TrcdT_1066; - } else { - if (val < Min_TrcdT) - val = Min_TrcdT; - else if (val > Max_TrcdT) - val = Max_TrcdT; - } - pDCTstat->Trcd = val; - - /* Trc */ - dword = Trc * 40; - pDCTstat->DIMMTrc = dword; - val = dword / Tk40; - if (dword % Tk40) { /* round up number of busclocks */ - val++; - } - if (DDR2_1066) { - if (val < Min_TrcT_1066) - val = Min_TrcT_1066; - else if (val > Max_TrcT_1066) - val = Max_TrcT_1066; - } else { - if (val < Min_TrcT) - val = Min_TrcT; - else if (val > Max_TrcT) - val = Max_TrcT; - } - pDCTstat->Trc = val; - - /* Trtp */ - dword = Trtp * 10; - pDCTstat->DIMMTrtp = dword; - val = pDCTstat->Speed; - if (val <= 2) { /* 7.75ns / Speed in ns to get clock # */ - val = 2; /* for DDR400/DDR533 */ - } else { /* Note a speed of 3 will be a Trtp of 3 */ - val = 3; /* for DDR667/DDR800/DDR1066 */ - } - pDCTstat->Trtp = val; - - /* Twr */ - dword = Twr * 10; - pDCTstat->DIMMTwr = dword; - val = dword / Tk40; - if (dword % Tk40) { /* round up number of busclocks */ - val++; - } - if (DDR2_1066) { - if (val < Min_TwrT_1066) - val = Min_TwrT_1066; - else if (val > Max_TwrT_1066) - val = Max_TwrT_1066; - } else { - if (val < Min_TwrT) - val = Min_TwrT; - else if (val > Max_TwrT) - val = Max_TwrT; - } - pDCTstat->Twr = val; - - /* Twtr */ - dword = Twtr * 10; - pDCTstat->DIMMTwtr = dword; - val = dword / Tk40; - if (dword % Tk40) { /* round up number of busclocks */ - val++; - } - if (DDR2_1066) { - if (val < Min_TwrT_1066) - val = Min_TwtrT_1066; - else if (val > Max_TwtrT_1066) - val = Max_TwtrT_1066; - } else { - if (val < Min_TwtrT) - val = Min_TwtrT; - else if (val > Max_TwtrT) - val = Max_TwtrT; - } - pDCTstat->Twtr = val; - - - /* Trfc0-Trfc3 */ - for (i = 0; i < 4; i++) - pDCTstat->Trfc[i] = Trfc[i]; - - mctAdjustAutoCycTmg_D(); - - /* Program DRAM Timing values */ - DramTimingLo = 0; /* Dram Timing Low init */ - val = pDCTstat->CASL; - val = Tab_tCL_j[val]; - DramTimingLo |= val; - - val = pDCTstat->Trcd; - if (DDR2_1066) - val -= Bias_TrcdT_1066; - else - val -= Bias_TrcdT; - - DramTimingLo |= val << 4; - - val = pDCTstat->Trp; - if (DDR2_1066) - val -= Bias_TrpT_1066; - else { - val -= Bias_TrpT; - val <<= 1; - } - DramTimingLo |= val << 7; - - val = pDCTstat->Trtp; - val -= Bias_TrtpT; - DramTimingLo |= val << 11; - - val = pDCTstat->Tras; - if (DDR2_1066) - val -= Bias_TrasT_1066; - else - val -= Bias_TrasT; - DramTimingLo |= val << 12; - - val = pDCTstat->Trc; - val -= Bias_TrcT; - DramTimingLo |= val << 16; - - if (!DDR2_1066) { - val = pDCTstat->Twr; - val -= Bias_TwrT; - DramTimingLo |= val << 20; - } - - val = pDCTstat->Trrd; - if (DDR2_1066) - val -= Bias_TrrdT_1066; - else - val -= Bias_TrrdT; - DramTimingLo |= val << 22; - - - DramTimingHi = 0; /* Dram Timing Low init */ - val = pDCTstat->Twtr; - if (DDR2_1066) - val -= Bias_TwtrT_1066; - else - val -= Bias_TwtrT; - DramTimingHi |= val << 8; - - val = 2; - DramTimingHi |= val << 16; - - val = 0; - for (i = 4; i > 0; i--) { - val <<= 3; - val |= Trfc[i-1]; - } - DramTimingHi |= val << 20; - - - dev = pDCTstat->dev_dct; - reg_off = 0x100 * dct; - print_tx("AutoCycTiming: DramTimingLo ", DramTimingLo); - print_tx("AutoCycTiming: DramTimingHi ", DramTimingHi); - - Set_NB32(dev, 0x88 + reg_off, DramTimingLo); /*DCT Timing Low*/ - DramTimingHi |=0x0000FC77; - Set_NB32(dev, 0x8c + reg_off, DramTimingHi); /*DCT Timing Hi*/ - - if (DDR2_1066) { - /* Twr */ - dword = pDCTstat->Twr; - dword -= Bias_TwrT_1066; - dword <<= 4; - reg = 0x84 + reg_off; - val = Get_NB32(dev, reg); - val &= 0x8F; - val |= dword; - Set_NB32(dev, reg, val); - } - - print_tx("AutoCycTiming: Status ", pDCTstat->Status); - print_tx("AutoCycTiming: ErrStatus ", pDCTstat->ErrStatus); - print_tx("AutoCycTiming: ErrCode ", pDCTstat->ErrCode); - print_t("AutoCycTiming: Done\n"); - - mctHookAfterAutoCycTmg(); - - return pDCTstat->ErrCode; -} - - -static void GetPresetmaxF_D(struct MCTStatStruc *pMCTstat, - struct DCTStatStruc *pDCTstat) -{ - /* Get max frequency from OEM platform definition, from any user - * override (limiting) of max frequency, and from any Si Revision - * Specific information. Return the least of these three in - * DCTStatStruc.PresetmaxFreq. - */ - - u16 proposedFreq; - u16 word; - - /* Get CPU Si Revision defined limit (NPT) */ - proposedFreq = 533; /* Rev F0 programmable max memclock is */ - - /*Get User defined limit if "limit" mode */ - if (mctGet_NVbits(NV_MCTUSRTMGMODE) == 1) { - word = Get_Fk_D(mctGet_NVbits(NV_MemCkVal) + 1); - if (word < proposedFreq) - proposedFreq = word; - - /* Get Platform defined limit */ - word = mctGet_NVbits(NV_MAX_MEMCLK); - if (word < proposedFreq) - proposedFreq = word; - - word = pDCTstat->PresetmaxFreq; - if (word > proposedFreq) - word = proposedFreq; - - pDCTstat->PresetmaxFreq = word; - } -} - - - -static void SPDGetTCL_D(struct MCTStatStruc *pMCTstat, - struct DCTStatStruc *pDCTstat, u8 dct) -{ - /* Find the best T and CL primary timing parameter pair, per Mfg., - * for the given set of DIMMs, and store into DCTStatStruc - * (.DIMMAutoSpeed and .DIMMCASL). See "Global relationship between - * index values and item values" for definition of CAS latency - * index (j) and Frequency index (k). - */ - int i, j, k; - u8 T1min, CL1min; - - /* i={0..7} (std. physical DIMM number) - * j is an integer which enumerates increasing CAS latency. - * k is an integer which enumerates decreasing cycle time. - * CL no. {0,1,2} corresponds to CL X, CL X-.5, or CL X-1 (per individual DIMM) - * Max timing values are per parameter, of all DIMMs, spec'd in ns like the SPD. - */ - - CL1min = 0xFF; - T1min = 0xFF; - for (k = K_MAX; k >= K_MIN; k--) { - for (j = J_MIN; j <= J_MAX; j++) { - if (Sys_Capability_D(pMCTstat, pDCTstat, j, k)) { - /* 1. check to see if DIMMi is populated. - 2. check if DIMMi supports CLj and Tjk */ - for (i = 0; i < MAX_DIMMS_SUPPORTED; i++) { - if (pDCTstat->DIMMValid & (1 << i)) { - if (Dimm_Supports_D(pDCTstat, i, j, k)) - break; - } - } /* while ++i */ - if (i == MAX_DIMMS_SUPPORTED) { - T1min = k; - CL1min = j; - goto got_TCL; - } - } - } /* while ++j */ - } /* while --k */ - -got_TCL: - if (T1min != 0xFF) { - pDCTstat->DIMMCASL = CL1min; /*mfg. optimized */ - pDCTstat->DIMMAutoSpeed = T1min; - print_tx("SPDGetTCL_D: DIMMCASL ", pDCTstat->DIMMCASL); - print_tx("SPDGetTCL_D: DIMMAutoSpeed ", pDCTstat->DIMMAutoSpeed); - - } else { - pDCTstat->DIMMCASL = CL_DEF; /* failsafe values (running in min. mode) */ - pDCTstat->DIMMAutoSpeed = T_DEF; - pDCTstat->ErrStatus |= 1 << SB_DimmMismatchT; - pDCTstat->ErrStatus |= 1 << SB_MinimumMode; - pDCTstat->ErrCode = SC_VarianceErr; - } - print_tx("SPDGetTCL_D: Status ", pDCTstat->Status); - print_tx("SPDGetTCL_D: ErrStatus ", pDCTstat->ErrStatus); - print_tx("SPDGetTCL_D: ErrCode ", pDCTstat->ErrCode); - print_t("SPDGetTCL_D: Done\n"); -} - - -static u8 PlatformSpec_D(struct MCTStatStruc *pMCTstat, - struct DCTStatStruc *pDCTstat, u8 dct) -{ - u32 dev; - u32 reg; - u32 val; - - mctGet_PS_Cfg_D(pMCTstat, pDCTstat, dct); - - if (pDCTstat->GangedMode) { - mctGet_PS_Cfg_D(pMCTstat, pDCTstat, 1); - } - - if (pDCTstat->_2Tmode == 2) { - dev = pDCTstat->dev_dct; - reg = 0x94 + 0x100 * dct; /* Dram Configuration Hi */ - val = Get_NB32(dev, reg); - val |= 1 << 20; /* 2T CMD mode */ - Set_NB32(dev, reg, val); - } - - mct_PlatformSpec(pMCTstat, pDCTstat, dct); - InitPhyCompensation(pMCTstat, pDCTstat, dct); - mctHookAfterPSCfg(); - return pDCTstat->ErrCode; -} - - -static u8 AutoConfig_D(struct MCTStatStruc *pMCTstat, - struct DCTStatStruc *pDCTstat, u8 dct) -{ - u32 DramControl, DramTimingLo, Status; - u32 DramConfigLo, DramConfigHi, DramConfigMisc, DramConfigMisc2; - u32 val; - u32 reg_off; - u32 dev; - u16 word; - u32 dword; - u8 byte; - - print_tx("AutoConfig_D: DCT: ", dct); - - DramConfigLo = 0; - DramConfigHi = 0; - DramConfigMisc = 0; - DramConfigMisc2 = 0; - - /* set bank addressing and Masks, plus CS pops */ - SPDSetBanks_D(pMCTstat, pDCTstat, dct); - if (pDCTstat->ErrCode == SC_StopError) - goto AutoConfig_exit; - - /* map chip-selects into local address space */ - StitchMemory_D(pMCTstat, pDCTstat, dct); - InterleaveBanks_D(pMCTstat, pDCTstat, dct); - - /* temp image of status (for convenience). RO usage! */ - Status = pDCTstat->Status; - - dev = pDCTstat->dev_dct; - reg_off = 0x100 * dct; - - - /* Build Dram Control Register Value */ - DramConfigMisc2 = Get_NB32 (dev, 0xA8 + reg_off); /* Dram Control*/ - DramControl = Get_NB32 (dev, 0x78 + reg_off); /* Dram Control*/ - - if (mctGet_NVbits(NV_CLKHZAltVidC3)) - DramControl |= 1<<16; - - // FIXME: Add support(skip) for Ax and Cx versions - DramControl |= 5; /* RdPtrInit */ - - - /* Build Dram Config Lo Register Value */ - DramConfigLo |= 1 << 4; /* 75 Ohms ODT */ - if (mctGet_NVbits(NV_MAX_DIMMS) == 8) { - if (pDCTstat->Speed == 3) { - if (pDCTstat->MAdimms[dct] == 4) - DramConfigLo |= 1 << 5; /* 50 Ohms ODT */ - } else if (pDCTstat->Speed == 4) { - if (pDCTstat->MAdimms[dct] != 1) - DramConfigLo |= 1 << 5; /* 50 Ohms ODT */ - } - } else { - // FIXME: Skip for Ax versions - if (pDCTstat->MAdimms[dct] == 4) { - if (pDCTstat->DimmQRPresent != 0) { - if ((pDCTstat->Speed == 3) || (pDCTstat->Speed == 4)) { - DramConfigLo |= 1 << 5; /* 50 Ohms ODT */ - } - } else if (pDCTstat->MAdimms[dct] == 4) { - if (pDCTstat->Speed == 4) { - if (pDCTstat->DimmQRPresent != 0) { - DramConfigLo |= 1 << 5; /* 50 Ohms ODT */ - } - } - } - } else if (pDCTstat->MAdimms[dct] == 2) { - DramConfigLo |= 1 << 5; /* 50 Ohms ODT */ - } - - } - - // FIXME: Skip for Ax versions - /* callback not required - if (!mctParityControl_D()) */ - if (Status & (1 << SB_PARDIMMs)) { - DramConfigLo |= 1 << ParEn; - DramConfigMisc2 |= 1 << ActiveCmdAtRst; - } else { - DramConfigLo &= ~(1 << ParEn); - DramConfigMisc2 &= ~(1 << ActiveCmdAtRst); - } - - if (mctGet_NVbits(NV_BurstLen32)) { - if (!pDCTstat->GangedMode) - DramConfigLo |= 1 << BurstLength32; - } - - if (Status & (1 << SB_128bitmode)) - DramConfigLo |= 1 << Width128; /* 128-bit mode (normal) */ - - word = dct; - dword = X4Dimm; - while (word < 8) { - if (pDCTstat->Dimmx4Present & (1 << word)) - DramConfigLo |= 1 << dword; /* X4Dimm[3:0] */ - word++; - word++; - dword++; - } - - if (!(Status & (1 << SB_Registered))) - DramConfigLo |= 1 << UnBuffDimm; /* Unbuffered DIMMs */ - - if (mctGet_NVbits(NV_ECC_CAP)) - if (Status & (1 << SB_ECCDIMMs)) - if (mctGet_NVbits(NV_ECC)) - DramConfigLo |= 1 << DimmEcEn; - - DramConfigLo = mct_DisDllShutdownSR(pMCTstat, pDCTstat, DramConfigLo, dct); - - /* Build Dram Config Hi Register Value */ - dword = pDCTstat->Speed; - DramConfigHi |= dword - 1; /* get MemClk encoding */ - DramConfigHi |= 1 << MemClkFreqVal; - - if (Status & (1 << SB_Registered)) - if ((pDCTstat->Dimmx4Present != 0) && (pDCTstat->Dimmx8Present != 0)) - /* set only if x8 Registered DIMMs in System*/ - DramConfigHi |= 1 << RDqsEn; - - if (mctGet_NVbits(NV_CKE_PDEN)) { - DramConfigHi |= 1 << 15; /* PowerDownEn */ - if (mctGet_NVbits(NV_CKE_CTL)) - /*Chip Select control of CKE*/ - DramConfigHi |= 1 << 16; - } - - /* Control Bank Swizzle */ - if (0) /* call back not needed mctBankSwizzleControl_D()) */ - DramConfigHi &= ~(1 << BankSwizzleMode); - else - DramConfigHi |= 1 << BankSwizzleMode; /* recommended setting (default) */ - - /* Check for Quadrank DIMM presence */ - if (pDCTstat->DimmQRPresent != 0) { - byte = mctGet_NVbits(NV_4RANKType); - if (byte == 2) - DramConfigHi |= 1 << 17; /* S4 (4-Rank SO-DIMMs) */ - else if (byte == 1) - DramConfigHi |= 1 << 18; /* R4 (4-Rank Registered DIMMs) */ - } - - if (0) /* call back not needed mctOverrideDcqBypMax_D) */ - val = mctGet_NVbits(NV_BYPMAX); - else - val = 0x0f; // recommended setting (default) - DramConfigHi |= val << 24; - - val = pDCTstat->DIMM2Kpage; - if (pDCTstat->GangedMode != 0) { - if (dct != 0) { - val &= 0x55; - } else { - val &= 0xAA; - } - } - if (val) - val = Tab_2KTfawT_k[pDCTstat->Speed]; - else - val = Tab_1KTfawT_k[pDCTstat->Speed]; - - if (pDCTstat->Speed == 5) - val >>= 1; - - val -= Bias_TfawT; - val <<= 28; - DramConfigHi |= val; /* Tfaw for 1K or 2K paged drams */ - - // FIXME: Skip for Ax versions - DramConfigHi |= 1 << DcqArbBypassEn; - - - /* Build MemClkDis Value from Dram Timing Lo and - Dram Config Misc Registers - 1. We will assume that MemClkDis field has been preset prior to this - point. - 2. We will only set MemClkDis bits if a DIMM is NOT present AND if: - NV_AllMemClks <>0 AND SB_DiagClks == 0 */ - - - /* Dram Timing Low (owns Clock Enable bits) */ - DramTimingLo = Get_NB32(dev, 0x88 + reg_off); - if (mctGet_NVbits(NV_AllMemClks) == 0) { - /* Special Jedec SPD diagnostic bit - "enable all clocks" */ - if (!(pDCTstat->Status & (1 << SB_DiagClks))) { - const u8 *p; - byte = mctGet_NVbits(NV_PACK_TYPE); - if (byte == PT_L1) - p = Tab_L1CLKDis; - else if (byte == PT_M2) - p = Tab_M2CLKDis; - else - p = Tab_S1CLKDis; - - dword = 0; - while (dword < MAX_DIMMS_SUPPORTED) { - val = p[dword]; - print_tx("DramTimingLo: val=", val); - if (!(pDCTstat->DIMMValid & (1 << val))) - /*disable memclk*/ - DramTimingLo |= 1 << (dword+24); - dword++; - } - } - } - - print_tx("AutoConfig_D: DramControl: ", DramControl); - print_tx("AutoConfig_D: DramTimingLo: ", DramTimingLo); - print_tx("AutoConfig_D: DramConfigMisc: ", DramConfigMisc); - print_tx("AutoConfig_D: DramConfigMisc2: ", DramConfigMisc2); - print_tx("AutoConfig_D: DramConfigLo: ", DramConfigLo); - print_tx("AutoConfig_D: DramConfigHi: ", DramConfigHi); - - /* Write Values to the registers */ - Set_NB32(dev, 0x78 + reg_off, DramControl); - Set_NB32(dev, 0x88 + reg_off, DramTimingLo); - Set_NB32(dev, 0xA0 + reg_off, DramConfigMisc); - Set_NB32(dev, 0xA8 + reg_off, DramConfigMisc2); - Set_NB32(dev, 0x90 + reg_off, DramConfigLo); - mct_SetDramConfigHi_D(pDCTstat, dct, DramConfigHi); - mct_ForceAutoPrecharge_D(pDCTstat, dct); - mct_EarlyArbEn_D(pMCTstat, pDCTstat); - mctHookAfterAutoCfg(); - - print_tx("AutoConfig: Status ", pDCTstat->Status); - print_tx("AutoConfig: ErrStatus ", pDCTstat->ErrStatus); - print_tx("AutoConfig: ErrCode ", pDCTstat->ErrCode); - print_t("AutoConfig: Done\n"); -AutoConfig_exit: - return pDCTstat->ErrCode; -} - - -static void SPDSetBanks_D(struct MCTStatStruc *pMCTstat, - struct DCTStatStruc *pDCTstat, u8 dct) -{ - /* Set bank addressing, program Mask values and build a chip-select - * population map. This routine programs PCI 0:24N:2x80 config register - * and PCI 0:24N:2x60,64,68,6C config registers (CS Mask 0-3). - */ - - u8 ChipSel, Rows, Cols, Ranks, Banks; - u32 BankAddrReg, csMask; - - u32 val; - u32 reg; - u32 dev; - u32 reg_off; - u8 byte; - u16 word; - u32 dword; - u16 smbaddr; - - dev = pDCTstat->dev_dct; - reg_off = 0x100 * dct; - - BankAddrReg = 0; - for (ChipSel = 0; ChipSel < MAX_CS_SUPPORTED; ChipSel+=2) { - byte = ChipSel; - if ((pDCTstat->Status & (1 << SB_64MuxedMode)) && ChipSel >=4) - byte -= 3; - - if (pDCTstat->DIMMValid & (1 << byte)) { - smbaddr = Get_DIMMAddress_D(pDCTstat, (ChipSel + dct)); - - byte = mctRead_SPD(smbaddr, SPD_ROWSZ); - Rows = byte & 0x1f; - - byte = mctRead_SPD(smbaddr, SPD_COLSZ); - Cols = byte & 0x1f; - - Banks = mctRead_SPD(smbaddr, SPD_LBANKS); - - byte = mctRead_SPD(smbaddr, SPD_DEVWIDTH); - - byte = mctRead_SPD(smbaddr, SPD_DMBANKS); - Ranks = (byte & 7) + 1; - - /* Configure Bank encoding - * Use a 6-bit key into a lookup table. - * Key (index) = CCCBRR, where CCC is the number of - * Columns minus 9,RR is the number of Rows minus 13, - * and B is the number of banks minus 2. - * See "6-bit Bank Addressing Table" at the end of - * this file.*/ - byte = Cols - 9; /* 9 Cols is smallest dev size */ - byte <<= 3; /* make room for row and bank bits*/ - if (Banks == 8) - byte |= 4; - - /* 13 Rows is smallest dev size */ - byte |= Rows - 13; /* CCCBRR internal encode */ - - for (dword = 0; dword < 12; dword++) { - if (byte == Tab_BankAddr[dword]) - break; - } - - if (dword < 12) { - - /* bit no. of CS field in address mapping reg.*/ - dword <<= (ChipSel << 1); - BankAddrReg |= dword; - - /* Mask value=(2pow(rows+cols+banks+3)-1)>>8, - or 2pow(rows+cols+banks-5)-1*/ - csMask = 0; - - byte = Rows + Cols; /* cl = rows+cols*/ - if (Banks == 8) - byte -= 2; /* 3 banks - 5 */ - else - byte -= 3; /* 2 banks - 5 */ - /* mask size (64-bit rank only) */ - - if (pDCTstat->Status & (1 << SB_128bitmode)) - byte++; /* double mask size if in 128-bit mode*/ - - csMask |= 1 << byte; - csMask--; - - /*set ChipSelect population indicator even bits*/ - pDCTstat->CSPresent |= (1 << ChipSel); - if (Ranks >= 2) - /*set ChipSelect population indicator odd bits*/ - pDCTstat->CSPresent |= 1 << (ChipSel + 1); - - reg = 0x60+(ChipSel << 1) + reg_off; /*Dram CS Mask Register */ - val = csMask; - val &= 0x1FF83FE0; /* Mask out reserved bits.*/ - Set_NB32(dev, reg, val); - } - } else { - if (pDCTstat->DIMMSPDCSE & (1 << ChipSel)) - pDCTstat->CSTestFail |= (1 << ChipSel); - } /* if DIMMValid*/ - } /* while ChipSel*/ - - SetCSTriState(pMCTstat, pDCTstat, dct); - /* SetCKETriState */ - SetODTTriState(pMCTstat, pDCTstat, dct); - - if (pDCTstat->Status & (1 << SB_128bitmode)) { - SetCSTriState(pMCTstat, pDCTstat, 1); /* force dct1) */ - SetODTTriState(pMCTstat, pDCTstat, 1); /* force dct1) */ - } - word = pDCTstat->CSPresent; - mctGetCS_ExcludeMap(); /* mask out specified chip-selects */ - word ^= pDCTstat->CSPresent; - pDCTstat->CSTestFail |= word; /* enable ODT to disabled DIMMs */ - if (!pDCTstat->CSPresent) - pDCTstat->ErrCode = SC_StopError; - - reg = 0x80 + reg_off; /* Bank Addressing Register */ - Set_NB32(dev, reg, BankAddrReg); - - print_tx("SPDSetBanks: Status ", pDCTstat->Status); - print_tx("SPDSetBanks: ErrStatus ", pDCTstat->ErrStatus); - print_tx("SPDSetBanks: ErrCode ", pDCTstat->ErrCode); - print_t("SPDSetBanks: Done\n"); -} - - -static void SPDCalcWidth_D(struct MCTStatStruc *pMCTstat, - struct DCTStatStruc *pDCTstat) -{ - /* Per SPDs, check the symmetry of DIMM pairs (DIMM on Channel A - * matching with DIMM on Channel B), the overall DIMM population, - * and determine the width mode: 64-bit, 64-bit muxed, 128-bit. - */ - - u8 i; - u8 smbaddr, smbaddr1; - u8 byte, byte1; - - /* Check Symmetry of Channel A and Channel B DIMMs - (must be matched for 128-bit mode).*/ - for (i = 0; i < MAX_DIMMS_SUPPORTED; i += 2) { - if ((pDCTstat->DIMMValid & (1 << i)) && (pDCTstat->DIMMValid & (1<<(i+1)))) { - smbaddr = Get_DIMMAddress_D(pDCTstat, i); - smbaddr1 = Get_DIMMAddress_D(pDCTstat, i+1); - - byte = mctRead_SPD(smbaddr, SPD_ROWSZ) & 0x1f; - byte1 = mctRead_SPD(smbaddr1, SPD_ROWSZ) & 0x1f; - if (byte != byte1) { - pDCTstat->ErrStatus |= (1 << SB_DimmMismatchO); - break; - } - - byte = mctRead_SPD(smbaddr, SPD_COLSZ) & 0x1f; - byte1 = mctRead_SPD(smbaddr1, SPD_COLSZ) & 0x1f; - if (byte != byte1) { - pDCTstat->ErrStatus |= (1 << SB_DimmMismatchO); - break; - } - - byte = mctRead_SPD(smbaddr, SPD_BANKSZ); - byte1 = mctRead_SPD(smbaddr1, SPD_BANKSZ); - if (byte != byte1) { - pDCTstat->ErrStatus |= (1 << SB_DimmMismatchO); - break; - } - - byte = mctRead_SPD(smbaddr, SPD_DEVWIDTH) & 0x7f; - byte1 = mctRead_SPD(smbaddr1, SPD_DEVWIDTH) & 0x7f; - if (byte != byte1) { - pDCTstat->ErrStatus |= (1 << SB_DimmMismatchO); - break; - } - - byte = mctRead_SPD(smbaddr, SPD_DMBANKS) & 7; /* #ranks-1 */ - byte1 = mctRead_SPD(smbaddr1, SPD_DMBANKS) & 7; /* #ranks-1 */ - if (byte != byte1) { - pDCTstat->ErrStatus |= (1 << SB_DimmMismatchO); - break; - } - - } - } - -} - - -static void StitchMemory_D(struct MCTStatStruc *pMCTstat, - struct DCTStatStruc *pDCTstat, u8 dct) -{ - /* Requires that Mask values for each bank be programmed first and that - * the chip-select population indicator is correctly set. - */ - - u8 b = 0; - u32 nxtcsBase, curcsBase; - u8 p, q; - u32 BiggestBank; - u8 _DSpareEn; - - u16 word; - u32 dev; - u32 reg; - u32 reg_off; - u32 val; - - - dev = pDCTstat->dev_dct; - reg_off = 0x100 * dct; - - _DSpareEn = 0; - - /* CS Sparing 1 = enabled, 0 = disabled */ - if (mctGet_NVbits(NV_CS_SpareCTL) & 1) { - if (MCT_DIMM_SPARE_NO_WARM) { - /* Do no warm-reset DIMM spare */ - if (pMCTstat->GStatus & 1 << GSB_EnDIMMSpareNW) { - word = pDCTstat->CSPresent; - val = bsf(word); - word &= ~(1<ErrStatus |= 1 << SB_SpareDis; - } - } else { - if (!mctGet_NVbits(NV_DQSTrainCTL)) { /*DQS Training 1 = enabled, 0 = disabled */ - word = pDCTstat->CSPresent; - val = bsf(word); - word &= ~(1 << val); - if (word) - /* Make sure at least two chip-selects are available */ - _DSpareEn = 1; - else - pDCTstat->ErrStatus |= 1 << SB_SpareDis; - } - } - } - - nxtcsBase = 0; /* Next available cs base ADDR[39:8] */ - for (p = 0; p < MAX_DIMMS_SUPPORTED; p++) { - BiggestBank = 0; - for (q = 0; q < MAX_CS_SUPPORTED; q++) { /* from DIMMS to CS */ - if (pDCTstat->CSPresent & (1 << q)) { /* bank present? */ - reg = 0x40 + (q << 2) + reg_off; /* Base[q] reg.*/ - val = Get_NB32(dev, reg); - if (!(val & 3)) { /* (CSEnable|Spare == 1)bank is enabled already? */ - reg = 0x60 + ((q << 1) & 0xc) + reg_off; /*Mask[q] reg.*/ - val = Get_NB32(dev, reg); - val >>= 19; - val++; - val <<= 19; - if (val > BiggestBank) { - /*Bingo! possibly Map this chip-select next! */ - BiggestBank = val; - b = q; - } - } - } /*if bank present */ - } /* while q */ - if (BiggestBank !=0) { - curcsBase = nxtcsBase; /* curcsBase = nxtcsBase*/ - /* DRAM CS Base b Address Register offset */ - reg = 0x40 + (b << 2) + reg_off; - if (_DSpareEn) { - BiggestBank = 0; - val = 1 << Spare; /* Spare Enable*/ - } else { - val = curcsBase; - val |= 1 << CSEnable; /* Bank Enable */ - } - Set_NB32(dev, reg, val); - if (_DSpareEn) - _DSpareEn = 0; - else - /* let nxtcsBase+=Size[b] */ - nxtcsBase += BiggestBank; - } - - /* bank present but disabled?*/ - if (pDCTstat->CSTestFail & (1 << p)) { - /* DRAM CS Base b Address Register offset */ - reg = (p << 2) + 0x40 + reg_off; - val = 1 << TestFail; - Set_NB32(dev, reg, val); - } - } - - if (nxtcsBase) { - pDCTstat->DCTSysLimit = nxtcsBase - 1; - mct_AfterStitchMemory(pMCTstat, pDCTstat, dct); - } - - print_tx("StitchMemory: Status ", pDCTstat->Status); - print_tx("StitchMemory: ErrStatus ", pDCTstat->ErrStatus); - print_tx("StitchMemory: ErrCode ", pDCTstat->ErrCode); - print_t("StitchMemory: Done\n"); -} - - -static u8 Get_Tk_D(u8 k) -{ - return Table_T_k[k]; -} - - -static u8 Get_CLj_D(u8 j) -{ - return Table_CL2_j[j]; -} - -static u8 Get_DefTrc_k_D(u8 k) -{ - return Tab_defTrc_k[k]; -} - - -static u16 Get_40Tk_D(u8 k) -{ - return Tab_40T_k[k]; /* FIXME: k or k<<1 ?*/ -} - - -static u16 Get_Fk_D(u8 k) -{ - return Table_F_k[k]; /* FIXME: k or k<<1 ? */ -} - - -static u8 Dimm_Supports_D(struct DCTStatStruc *pDCTstat, - u8 i, u8 j, u8 k) -{ - u8 Tk, CLj, CL_i; - u8 ret = 0; - - u32 DIMMi; - u8 byte; - u16 word, wordx; - - DIMMi = Get_DIMMAddress_D(pDCTstat, i); - - CLj = Get_CLj_D(j); - - /* check if DIMMi supports CLj */ - CL_i = mctRead_SPD(DIMMi, SPD_CASLAT); - byte = CL_i & CLj; - if (byte) { - /*find out if its CL X, CLX-1, or CLX-2 */ - word = bsr(byte); /* bit position of CLj */ - wordx = bsr(CL_i); /* bit position of CLX of CLi */ - wordx -= word; /* CL number (CL no. = 0,1, 2, or 3) */ - wordx <<= 3; /* 8 bits per SPD byte index */ - /*get T from SPD byte 9, 23, 25*/ - word = (EncodedTSPD >> wordx) & 0xFF; - Tk = Get_Tk_D(k); - byte = mctRead_SPD(DIMMi, word); /* DIMMi speed */ - if (Tk < byte) { - ret = 1; - } else if (byte == 0) { - pDCTstat->ErrStatus |= 1 << SB_NoCycTime; - ret = 1; - } else { - ret = 0; /* DIMM is capable! */ - } - } else { - ret = 1; - } - return ret; -} - - -static u8 DIMMPresence_D(struct MCTStatStruc *pMCTstat, - struct DCTStatStruc *pDCTstat) -{ - /* Check DIMMs present, verify checksum, flag SDRAM type, - * build population indicator bitmaps, and preload bus loading - * of DIMMs into DCTStatStruc. - * MAAload = number of devices on the "A" bus. - * MABload = number of devices on the "B" bus. - * MAAdimms = number of DIMMs on the "A" bus slots. - * MABdimms = number of DIMMs on the "B" bus slots. - * DATAAload = number of ranks on the "A" bus slots. - * DATABload = number of ranks on the "B" bus slots. - */ - - u16 i, j, k; - u8 smbaddr, Index; - u16 Checksum; - u8 SPDCtrl; - u16 RegDIMMPresent, MaxDimms; - u8 devwidth; - u16 DimmSlots; - u8 byte = 0, bytex; - u16 word; - - /* preload data structure with addrs */ - mctGet_DIMMAddr(pDCTstat, pDCTstat->Node_ID); - - DimmSlots = MaxDimms = mctGet_NVbits(NV_MAX_DIMMS); - - SPDCtrl = mctGet_NVbits(NV_SPDCHK_RESTRT); - - RegDIMMPresent = 0; - pDCTstat->DimmQRPresent = 0; - - for (i = 0; i< MAX_DIMMS_SUPPORTED; i++) { - if (i >= MaxDimms) - break; - - if ((pDCTstat->DimmQRPresent & (1 << i)) || (i < DimmSlots)) { - print_tx("\t DIMMPresence: i=", i); - smbaddr = Get_DIMMAddress_D(pDCTstat, i); - print_tx("\t DIMMPresence: smbaddr=", smbaddr); - if (smbaddr) { - Checksum = 0; - for (Index = 0; Index < 64; Index++) { - int status; - status = mctRead_SPD(smbaddr, Index); - if (status < 0) - break; - byte = status & 0xFF; - if (Index < 63) - Checksum += byte; - } - - if (Index == 64) { - pDCTstat->DIMMPresent |= 1 << i; - if ((Checksum & 0xFF) == byte) { - byte = mctRead_SPD(smbaddr, SPD_TYPE); - if (byte == JED_DDR2SDRAM) { - /*Dimm is 'Present'*/ - pDCTstat->DIMMValid |= 1 << i; - } - } else { - pDCTstat->DIMMSPDCSE = 1 << i; - if (SPDCtrl == 0) { - pDCTstat->ErrStatus |= 1 << SB_DIMMChkSum; - pDCTstat->ErrCode = SC_StopError; - } else { - /*if NV_SPDCHK_RESTRT is set to 1, ignore faulty SPD checksum*/ - pDCTstat->ErrStatus |= 1 << SB_DIMMChkSum; - byte = mctRead_SPD(smbaddr, SPD_TYPE); - if (byte == JED_DDR2SDRAM) - pDCTstat->DIMMValid |= 1 << i; - } - } - /* Get module information for SMBIOS */ - if (pDCTstat->DIMMValid & (1 << i)) { - pDCTstat->DimmManufacturerID[i] = 0; - for (k = 0; k < 8; k++) - pDCTstat->DimmManufacturerID[i] |= ((uint64_t)mctRead_SPD(smbaddr, SPD_MANID_START + k)) << (k * 8); - for (k = 0; k < SPD_PARTN_LENGTH; k++) - pDCTstat->DimmPartNumber[i][k] = mctRead_SPD(smbaddr, SPD_PARTN_START + k); - pDCTstat->DimmPartNumber[i][SPD_PARTN_LENGTH] = 0; - pDCTstat->DimmRevisionNumber[i] = 0; - for (k = 0; k < 2; k++) - pDCTstat->DimmRevisionNumber[i] |= ((uint16_t)mctRead_SPD(smbaddr, SPD_REVNO_START + k)) << (k * 8); - pDCTstat->DimmSerialNumber[i] = 0; - for (k = 0; k < 4; k++) - pDCTstat->DimmSerialNumber[i] |= ((uint32_t)mctRead_SPD(smbaddr, SPD_SERIAL_START + k)) << (k * 8); - pDCTstat->DimmRows[i] = mctRead_SPD(smbaddr, SPD_ROWSZ) & 0xf; - pDCTstat->DimmCols[i] = mctRead_SPD(smbaddr, SPD_COLSZ) & 0xf; - pDCTstat->DimmRanks[i] = (mctRead_SPD(smbaddr, SPD_DMBANKS) & 0x7) + 1; - pDCTstat->DimmBanks[i] = mctRead_SPD(smbaddr, SPD_LBANKS); - pDCTstat->DimmWidth[i] = mctRead_SPD(smbaddr, SPD_DEVWIDTH); - } - /* Check module type */ - byte = mctRead_SPD(smbaddr, SPD_DIMMTYPE); - if (byte & JED_REGADCMSK) { - RegDIMMPresent |= 1 << i; - pDCTstat->DimmRegistered[i] = 1; - } else { - pDCTstat->DimmRegistered[i] = 0; - } - /* Check ECC capable */ - byte = mctRead_SPD(smbaddr, SPD_EDCTYPE); - if (byte & JED_ECC) { - /* DIMM is ECC capable */ - pDCTstat->DimmECCPresent |= 1 << i; - } - if (byte & JED_ADRCPAR) { - /* DIMM is ECC capable */ - pDCTstat->DimmPARPresent |= 1 << i; - } - /* Check if x4 device */ - devwidth = mctRead_SPD(smbaddr, SPD_DEVWIDTH) & 0xFE; - if (devwidth == 4) { - /* DIMM is made with x4 or x16 drams */ - pDCTstat->Dimmx4Present |= 1 << i; - } else if (devwidth == 8) { - pDCTstat->Dimmx8Present |= 1 << i; - } else if (devwidth == 16) { - pDCTstat->Dimmx16Present |= 1 << i; - } - /* check page size */ - byte = mctRead_SPD(smbaddr, SPD_COLSZ); - byte &= 0x0F; - word = 1 << byte; - word >>= 3; - word *= devwidth; /* (((2^COLBITS) / 8) * ORG) / 2048 */ - word >>= 11; - if (word) - pDCTstat->DIMM2Kpage |= 1 << i; - - /*Check if SPD diag bit 'analysis probe installed' is set */ - byte = mctRead_SPD(smbaddr, SPD_ATTRIB); - if (byte & JED_PROBEMSK) - pDCTstat->Status |= 1 << SB_DiagClks; - - byte = mctRead_SPD(smbaddr, SPD_DMBANKS); - if (!(byte & (1 << SPDPLBit))) - pDCTstat->DimmPlPresent |= 1 << i; - byte &= 7; - byte++; /* ranks */ - if (byte > 2) { - /* if any DIMMs are QR, we have to make two passes through DIMMs*/ - if (pDCTstat->DimmQRPresent == 0) { - MaxDimms <<= 1; - } - if (i < DimmSlots) { - pDCTstat->DimmQRPresent |= (1 << i) | (1 << (i+4)); - } - byte = 2; /* upper two ranks of QR DIMM will be counted on another DIMM number iteration*/ - } else if (byte == 2) { - pDCTstat->DimmDRPresent |= 1 << i; - } - bytex = devwidth; - if (devwidth == 16) - bytex = 4; - else if (devwidth == 4) - bytex = 16; - - if (byte == 2) - bytex <<= 1; /*double Addr bus load value for dual rank DIMMs*/ - - j = i & (1<<0); - pDCTstat->DATAload[j] += byte; /*number of ranks on DATA bus*/ - pDCTstat->MAload[j] += bytex; /*number of devices on CMD/ADDR bus*/ - pDCTstat->MAdimms[j]++; /*number of DIMMs on A bus */ - /*check for DRAM package Year <= 06*/ - byte = mctRead_SPD(smbaddr, SPD_MANDATEYR); - if (byte < MYEAR06) { - /*Year < 06 and hence Week < 24 of 06 */ - pDCTstat->DimmYr06 |= 1 << i; - pDCTstat->DimmWk2406 |= 1 << i; - } else if (byte == MYEAR06) { - /*Year = 06, check if Week <= 24 */ - pDCTstat->DimmYr06 |= 1 << i; - byte = mctRead_SPD(smbaddr, SPD_MANDATEWK); - if (byte <= MWEEK24) - pDCTstat->DimmWk2406 |= 1 << i; - } - } - } - } - } - print_tx("\t DIMMPresence: DIMMValid=", pDCTstat->DIMMValid); - print_tx("\t DIMMPresence: DIMMPresent=", pDCTstat->DIMMPresent); - print_tx("\t DIMMPresence: RegDIMMPresent=", RegDIMMPresent); - print_tx("\t DIMMPresence: DimmECCPresent=", pDCTstat->DimmECCPresent); - print_tx("\t DIMMPresence: DimmPARPresent=", pDCTstat->DimmPARPresent); - print_tx("\t DIMMPresence: Dimmx4Present=", pDCTstat->Dimmx4Present); - print_tx("\t DIMMPresence: Dimmx8Present=", pDCTstat->Dimmx8Present); - print_tx("\t DIMMPresence: Dimmx16Present=", pDCTstat->Dimmx16Present); - print_tx("\t DIMMPresence: DimmPlPresent=", pDCTstat->DimmPlPresent); - print_tx("\t DIMMPresence: DimmDRPresent=", pDCTstat->DimmDRPresent); - print_tx("\t DIMMPresence: DimmQRPresent=", pDCTstat->DimmQRPresent); - print_tx("\t DIMMPresence: DATAload[0]=", pDCTstat->DATAload[0]); - print_tx("\t DIMMPresence: MAload[0]=", pDCTstat->MAload[0]); - print_tx("\t DIMMPresence: MAdimms[0]=", pDCTstat->MAdimms[0]); - print_tx("\t DIMMPresence: DATAload[1]=", pDCTstat->DATAload[1]); - print_tx("\t DIMMPresence: MAload[1]=", pDCTstat->MAload[1]); - print_tx("\t DIMMPresence: MAdimms[1]=", pDCTstat->MAdimms[1]); - - if (pDCTstat->DIMMValid != 0) { /* If any DIMMs are present...*/ - if (RegDIMMPresent != 0) { - if ((RegDIMMPresent ^ pDCTstat->DIMMValid) !=0) { - /* module type DIMM mismatch (reg'ed, unbuffered) */ - pDCTstat->ErrStatus |= 1 << SB_DimmMismatchM; - pDCTstat->ErrCode = SC_StopError; - } else{ - /* all DIMMs are registered */ - pDCTstat->Status |= 1 << SB_Registered; - } - } - if (pDCTstat->DimmECCPresent != 0) { - if ((pDCTstat->DimmECCPresent ^ pDCTstat->DIMMValid) == 0) { - /* all DIMMs are ECC capable */ - pDCTstat->Status |= 1 << SB_ECCDIMMs; - } - } - if (pDCTstat->DimmPARPresent != 0) { - if ((pDCTstat->DimmPARPresent ^ pDCTstat->DIMMValid) == 0) { - /*all DIMMs are Parity capable */ - pDCTstat->Status |= 1 << SB_PARDIMMs; - } - } - } else { - /* no DIMMs present or no DIMMs that qualified. */ - pDCTstat->ErrStatus |= 1 << SB_NoDimms; - pDCTstat->ErrCode = SC_StopError; - } - - print_tx("\t DIMMPresence: Status ", pDCTstat->Status); - print_tx("\t DIMMPresence: ErrStatus ", pDCTstat->ErrStatus); - print_tx("\t DIMMPresence: ErrCode ", pDCTstat->ErrCode); - print_t("\t DIMMPresence: Done\n"); - - mctHookAfterDIMMpre(); - - return pDCTstat->ErrCode; -} - - -static u8 Sys_Capability_D(struct MCTStatStruc *pMCTstat, - struct DCTStatStruc *pDCTstat, int j, int k) -{ - /* Determine if system is capable of operating at given input - * parameters for CL, and T. There are three components to - * determining "maximum frequency" in AUTO mode: SPD component, - * Bus load component, and "Preset" max frequency component. - * This procedure is used to help find the SPD component and relies - * on pre-determination of the bus load component and the Preset - * components. The generalized algorithm for finding maximum - * frequency is structured this way so as to optimize for CAS - * latency (which might get better as a result of reduced frequency). - * See "Global relationship between index values and item values" - * for definition of CAS latency index (j) and Frequency index (k). - */ - u8 freqOK, ClOK; - u8 ret = 0; - - if (Get_Fk_D(k) > pDCTstat->PresetmaxFreq) - freqOK = 0; - else - freqOK = 1; - - /* compare proposed CAS latency with AMD Si capabilities */ - if ((j < J_MIN) || (j > J_MAX)) - ClOK = 0; - else - ClOK = 1; - - if (freqOK && ClOK) - ret = 1; - - return ret; -} - - -static u8 Get_DIMMAddress_D(struct DCTStatStruc *pDCTstat, u8 i) -{ - u8 *p; - - p = pDCTstat->DIMMAddr; - return p[i]; -} - - -static void mct_initDCT(struct MCTStatStruc *pMCTstat, - struct DCTStatStruc *pDCTstat) -{ - u32 val; - u8 err_code; - - /* Config. DCT0 for Ganged or unganged mode */ - print_t("\tmct_initDCT: DCTInit_D 0\n"); - DCTInit_D(pMCTstat, pDCTstat, 0); - if (pDCTstat->ErrCode == SC_FatalErr) { - // Do nothing goto exitDCTInit; /* any fatal errors? */ - } else { - /* Configure DCT1 if unganged and enabled*/ - if (!pDCTstat->GangedMode) { - if (pDCTstat->DIMMValidDCT[1] > 0) { - print_t("\tmct_initDCT: DCTInit_D 1\n"); - err_code = pDCTstat->ErrCode; /* save DCT0 errors */ - pDCTstat->ErrCode = 0; - DCTInit_D(pMCTstat, pDCTstat, 1); - if (pDCTstat->ErrCode == 2) /* DCT1 is not Running */ - pDCTstat->ErrCode = err_code; /* Using DCT0 Error code to update pDCTstat.ErrCode */ - } else { - val = 1 << DisDramInterface; - Set_NB32(pDCTstat->dev_dct, 0x100 + 0x94, val); - } - } - } -// exitDCTInit: -} - - -static void mct_DramInit(struct MCTStatStruc *pMCTstat, - struct DCTStatStruc *pDCTstat, u8 dct) -{ - u32 val; - - mct_BeforeDramInit_Prod_D(pMCTstat, pDCTstat); - // FIXME: for rev A: mct_BeforeDramInit_D(pDCTstat, dct); - - /* Disable auto refresh before Dram init when in ganged mode (Erratum 278) */ - if (pDCTstat->LogicalCPUID & (AMD_DR_B0 | AMD_DR_B1 | AMD_DR_BA)) { - if (pDCTstat->GangedMode) { - val = Get_NB32(pDCTstat->dev_dct, 0x8C + (0x100 * dct)); - val |= 1 << DisAutoRefresh; - Set_NB32(pDCTstat->dev_dct, 0x8C + (0x100 * dct), val); - } - } - - mct_DramInit_Hw_D(pMCTstat, pDCTstat, dct); - - /* Re-enable auto refresh after Dram init when in ganged mode - * to ensure both DCTs are in sync (Erratum 278) - */ - - if (pDCTstat->LogicalCPUID & (AMD_DR_B0 | AMD_DR_B1 | AMD_DR_BA)) { - if (pDCTstat->GangedMode) { - do { - val = Get_NB32(pDCTstat->dev_dct, 0x90 + (0x100 * dct)); - } while (!(val & (1 << InitDram))); - - WaitRoutine_D(50); - - val = Get_NB32(pDCTstat->dev_dct, 0x8C + (0x100 * dct)); - val &= ~(1 << DisAutoRefresh); - Set_NB32(pDCTstat->dev_dct, 0x8C + (0x100 * dct), val); - val |= 1 << DisAutoRefresh; - Set_NB32(pDCTstat->dev_dct, 0x8C + (0x100 * dct), val); - val &= ~(1 << DisAutoRefresh); - Set_NB32(pDCTstat->dev_dct, 0x8C + (0x100 * dct), val); - } - } -} - - -static u8 mct_setMode(struct MCTStatStruc *pMCTstat, - struct DCTStatStruc *pDCTstat) -{ - u8 byte; - u8 bytex; - u32 val; - u32 reg; - - byte = bytex = pDCTstat->DIMMValid; - bytex &= 0x55; /* CHA DIMM pop */ - pDCTstat->DIMMValidDCT[0] = bytex; - - byte &= 0xAA; /* CHB DIMM popa */ - byte >>= 1; - pDCTstat->DIMMValidDCT[1] = byte; - - if (byte != bytex) { - pDCTstat->ErrStatus &= ~(1 << SB_DimmMismatchO); - } else { - if (mctGet_NVbits(NV_Unganged)) - pDCTstat->ErrStatus |= (1 << SB_DimmMismatchO); - - if (!(pDCTstat->ErrStatus & (1 << SB_DimmMismatchO))) { - pDCTstat->GangedMode = 1; - /* valid 128-bit mode population. */ - pDCTstat->Status |= 1 << SB_128bitmode; - reg = 0x110; - val = Get_NB32(pDCTstat->dev_dct, reg); - val |= 1 << DctGangEn; - Set_NB32(pDCTstat->dev_dct, reg, val); - print_tx("setMode: DRAM Controller Select Low Register = ", val); - } - } - return pDCTstat->ErrCode; -} - - -u32 Get_NB32(u32 dev, u32 reg) -{ - return pci_read_config32(dev, reg); -} - - -void Set_NB32(u32 dev, u32 reg, u32 val) -{ - pci_write_config32(dev, reg, val); -} - - -u32 Get_NB32_index(u32 dev, u32 index_reg, u32 index) -{ - u32 dword; - - Set_NB32(dev, index_reg, index); - dword = Get_NB32(dev, index_reg+0x4); - - return dword; -} - -void Set_NB32_index(u32 dev, u32 index_reg, u32 index, u32 data) -{ - Set_NB32(dev, index_reg, index); - Set_NB32(dev, index_reg + 0x4, data); -} - - -u32 Get_NB32_index_wait(u32 dev, u32 index_reg, u32 index) -{ - - u32 dword; - - - index &= ~(1 << DctAccessWrite); - Set_NB32(dev, index_reg, index); - do { - dword = Get_NB32(dev, index_reg); - } while (!(dword & (1 << DctAccessDone))); - dword = Get_NB32(dev, index_reg + 0x4); - - return dword; -} - - -void Set_NB32_index_wait(u32 dev, u32 index_reg, u32 index, u32 data) -{ - u32 dword; - - - Set_NB32(dev, index_reg + 0x4, data); - index |= (1 << DctAccessWrite); - Set_NB32(dev, index_reg, index); - do { - dword = Get_NB32(dev, index_reg); - } while (!(dword & (1 << DctAccessDone))); - -} - - -static u8 mct_PlatformSpec(struct MCTStatStruc *pMCTstat, - struct DCTStatStruc *pDCTstat, u8 dct) -{ - /* Get platform specific config/timing values from the interface layer - * and program them into DCT. - */ - - u32 dev = pDCTstat->dev_dct; - u32 index_reg; - u8 i, i_start, i_end; - - if (pDCTstat->GangedMode) { - SyncSetting(pDCTstat); - i_start = 0; - i_end = 2; - } else { - i_start = dct; - i_end = dct + 1; - } - for (i = i_start; i < i_end; i++) { - index_reg = 0x98 + (i * 0x100); - Set_NB32_index_wait(dev, index_reg, 0x00, pDCTstat->CH_ODC_CTL[i]); /* Channel A Output Driver Compensation Control */ - Set_NB32_index_wait(dev, index_reg, 0x04, pDCTstat->CH_ADDR_TMG[i]); /* Channel A Output Driver Compensation Control */ - } - - return pDCTstat->ErrCode; - -} - - -static void mct_SyncDCTsReady(struct DCTStatStruc *pDCTstat) -{ - u32 dev; - u32 val; - - if (pDCTstat->NodePresent) { - print_tx("mct_SyncDCTsReady: Node ", pDCTstat->Node_ID); - dev = pDCTstat->dev_dct; - - if ((pDCTstat->DIMMValidDCT[0]) || (pDCTstat->DIMMValidDCT[1])) { /* This Node has dram */ - do { - val = Get_NB32(dev, 0x110); - } while (!(val & (1 << DramEnabled))); - print_t("mct_SyncDCTsReady: DramEnabled\n"); - } - } /* Node is present */ -} - - -static void mct_AfterGetCLT(struct MCTStatStruc *pMCTstat, - struct DCTStatStruc *pDCTstat, u8 dct) -{ - if (!pDCTstat->GangedMode) { - if (dct == 0) { - pDCTstat->DIMMValid = pDCTstat->DIMMValidDCT[dct]; - if (pDCTstat->DIMMValidDCT[dct] == 0) - pDCTstat->ErrCode = SC_StopError; - } else { - pDCTstat->CSPresent = 0; - pDCTstat->CSTestFail = 0; - pDCTstat->DIMMValid = pDCTstat->DIMMValidDCT[dct]; - if (pDCTstat->DIMMValidDCT[dct] == 0) - pDCTstat->ErrCode = SC_StopError; - } - } -} - -static u8 mct_SPDCalcWidth(struct MCTStatStruc *pMCTstat, - struct DCTStatStruc *pDCTstat, u8 dct) -{ - u8 ret; - - if (dct == 0) { - SPDCalcWidth_D(pMCTstat, pDCTstat); - ret = mct_setMode(pMCTstat, pDCTstat); - } else { - ret = pDCTstat->ErrCode; - } - - print_tx("SPDCalcWidth: Status ", pDCTstat->Status); - print_tx("SPDCalcWidth: ErrStatus ", pDCTstat->ErrStatus); - print_tx("SPDCalcWidth: ErrCode ", pDCTstat->ErrCode); - print_t("SPDCalcWidth: Done\n"); - - return ret; -} - - -static void mct_AfterStitchMemory(struct MCTStatStruc *pMCTstat, - struct DCTStatStruc *pDCTstat, u8 dct) -{ - u32 val; - u32 dword; - u32 dev; - u32 reg; - u8 _MemHoleRemap; - u32 DramHoleBase; - - _MemHoleRemap = mctGet_NVbits(NV_MemHole); - DramHoleBase = mctGet_NVbits(NV_BottomIO); - DramHoleBase <<= 8; - /* Increase hole size so;[31:24]to[31:16] - * it has granularity of 128MB shl eax,8 - * Set 'effective' bottom IOmov DramHoleBase,eax - */ - pMCTstat->HoleBase = (DramHoleBase & 0xFFFFF800) << 8; - - /* In unganged mode, we must add DCT0 and DCT1 to DCTSysLimit */ - if (!pDCTstat->GangedMode) { - dev = pDCTstat->dev_dct; - pDCTstat->NodeSysLimit += pDCTstat->DCTSysLimit; - /* if DCT0 and DCT1 both exist, set DctSelBaseAddr[47:27] to the top of DCT0 */ - if (dct == 0) { - if (pDCTstat->DIMMValidDCT[1] > 0) { - dword = pDCTstat->DCTSysLimit + 1; - dword += pDCTstat->NodeSysBase; - dword >>= 8; /* scale [39:8] to [47:27],and to F2x110[31:11] */ - if ((dword >= DramHoleBase) && _MemHoleRemap) { - pMCTstat->HoleBase = (DramHoleBase & 0xFFFFF800) << 8; - val = pMCTstat->HoleBase; - val >>= 16; - val = (((~val) & 0xFF) + 1); - val <<= 8; - dword += val; - } - reg = 0x110; - val = Get_NB32(dev, reg); - val &= 0x7F; - val |= dword; - val |= 3; /* Set F2x110[DctSelHiRngEn], F2x110[DctSelHi] */ - Set_NB32(dev, reg, val); - print_tx("AfterStitch DCT0 and DCT1: DRAM Controller Select Low Register = ", val); - print_tx("AfterStitch DCT0 and DCT1: DRAM Controller Select High Register = ", dword); - - reg = 0x114; - val = dword; - Set_NB32(dev, reg, val); - } - } else { - /* Program the DctSelBaseAddr value to 0 - if DCT 0 is disabled */ - if (pDCTstat->DIMMValidDCT[0] == 0) { - dword = pDCTstat->NodeSysBase; - dword >>= 8; - if ((dword >= DramHoleBase) && _MemHoleRemap) { - pMCTstat->HoleBase = (DramHoleBase & 0xFFFFF800) << 8; - val = pMCTstat->HoleBase; - val >>= 8; - val &= ~(0xFFFF); - val |= (((~val) & 0xFFFF) + 1); - dword += val; - } - reg = 0x114; - val = dword; - Set_NB32(dev, reg, val); - - reg = 0x110; - val |= 3; /* Set F2x110[DctSelHiRngEn], F2x110[DctSelHi] */ - Set_NB32(dev, reg, val); - print_tx("AfterStitch DCT1 only: DRAM Controller Select Low Register = ", val); - print_tx("AfterStitch DCT1 only: DRAM Controller Select High Register = ", dword); - } - } - } else { - pDCTstat->NodeSysLimit += pDCTstat->DCTSysLimit; - } - print_tx("AfterStitch pDCTstat->NodeSysBase = ", pDCTstat->NodeSysBase); - print_tx("mct_AfterStitchMemory: pDCTstat->NodeSysLimit ", pDCTstat->NodeSysLimit); -} - - -static u8 mct_DIMMPresence(struct MCTStatStruc *pMCTstat, - struct DCTStatStruc *pDCTstat, u8 dct) -{ - u8 ret; - - if (dct == 0) - ret = DIMMPresence_D(pMCTstat, pDCTstat); - else - ret = pDCTstat->ErrCode; - - return ret; -} - - -/* mct_BeforeGetDIMMAddress inline in C */ - - -static void mct_OtherTiming(struct MCTStatStruc *pMCTstat, - struct DCTStatStruc *pDCTstatA) -{ - u8 Node; - - for (Node = 0; Node < MAX_NODES_SUPPORTED; Node++) { - struct DCTStatStruc *pDCTstat; - pDCTstat = pDCTstatA + Node; - if (pDCTstat->NodePresent) { - if (pDCTstat->DIMMValidDCT[0]) { - pDCTstat->DIMMValid = pDCTstat->DIMMValidDCT[0]; - Set_OtherTiming(pMCTstat, pDCTstat, 0); - } - if (pDCTstat->DIMMValidDCT[1] && !pDCTstat->GangedMode) { - pDCTstat->DIMMValid = pDCTstat->DIMMValidDCT[1]; - Set_OtherTiming(pMCTstat, pDCTstat, 1); - } - } /* Node is present*/ - } /* while Node */ -} - - -static void Set_OtherTiming(struct MCTStatStruc *pMCTstat, - struct DCTStatStruc *pDCTstat, u8 dct) -{ - u32 reg; - u32 reg_off = 0x100 * dct; - u32 val; - u32 dword; - u32 dev = pDCTstat->dev_dct; - - Get_Trdrd(pMCTstat, pDCTstat, dct); - Get_Twrwr(pMCTstat, pDCTstat, dct); - Get_Twrrd(pMCTstat, pDCTstat, dct); - Get_TrwtTO(pMCTstat, pDCTstat, dct); - Get_TrwtWB(pMCTstat, pDCTstat); - - reg = 0x8C + reg_off; /* Dram Timing Hi */ - val = Get_NB32(dev, reg); - val &= 0xffff0300; - dword = pDCTstat->TrwtTO; //0x07 - val |= dword << 4; - dword = pDCTstat->Twrrd; //0x03 - val |= dword << 10; - dword = pDCTstat->Twrwr; //0x03 - val |= dword << 12; - dword = pDCTstat->Trdrd; //0x03 - val |= dword << 14; - dword = pDCTstat->TrwtWB; //0x07 - val |= dword; - val = OtherTiming_A_D(pDCTstat, val); - Set_NB32(dev, reg, val); - -} - - -static void Get_Trdrd(struct MCTStatStruc *pMCTstat, - struct DCTStatStruc *pDCTstat, u8 dct) -{ - u8 Trdrd; - u8 byte; - u32 dword; - u32 val; - u32 index_reg = 0x98 + 0x100 * dct; - u32 dev = pDCTstat->dev_dct; - - if ((pDCTstat->Dimmx4Present != 0) && (pDCTstat->Dimmx8Present != 0)) { - /* mixed (x4 or x8) DIMM types - the largest DqsRcvEnGrossDelay of any DIMM minus the DqsRcvEnGrossDelay - of any other DIMM is equal to the Critical Gross Delay Difference (CGDD) for Trdrd.*/ - byte = Get_DqsRcvEnGross_Diff(pDCTstat, dev, index_reg); - if (byte == 0) - Trdrd = 1; - else - Trdrd = 2; - - } else { - /* - Trdrd with non-mixed DIMM types - RdDqsTime are the same for all DIMMs and DqsRcvEn difference between - any two DIMMs is less than half of a MEMCLK, BIOS should program Trdrd to 0000b, - else BIOS should program Trdrd to 0001b. - - RdDqsTime are the same for all DIMMs - DDR400~DDR667 only use one set register - DDR800 have two set register for DIMM0 and DIMM1 */ - Trdrd = 1; - if (pDCTstat->Speed > 3) { - /* DIMM0+DIMM1 exist */ //NOTE it should be 5 - val = bsf(pDCTstat->DIMMValid); - dword = bsr(pDCTstat->DIMMValid); - if (dword != val && dword != 0) { - /* DCT Read DQS Timing Control - DIMM0 - Low */ - dword = Get_NB32_index_wait(dev, index_reg, 0x05); - /* DCT Read DQS Timing Control - DIMM1 - Low */ - val = Get_NB32_index_wait(dev, index_reg, 0x105); - if (val != dword) - goto Trdrd_1; - - /* DCT Read DQS Timing Control - DIMM0 - High */ - dword = Get_NB32_index_wait(dev, index_reg, 0x06); - /* DCT Read DQS Timing Control - DIMM1 - High */ - val = Get_NB32_index_wait(dev, index_reg, 0x106); - if (val != dword) - goto Trdrd_1; - } - } - - /* DqsRcvEn difference between any two DIMMs is - less than half of a MEMCLK */ - /* DqsRcvEn byte 1,0*/ - if (Check_DqsRcvEn_Diff(pDCTstat, dct, dev, index_reg, 0x10)) - goto Trdrd_1; - /* DqsRcvEn byte 3,2*/ - if (Check_DqsRcvEn_Diff(pDCTstat, dct, dev, index_reg, 0x11)) - goto Trdrd_1; - /* DqsRcvEn byte 5,4*/ - if (Check_DqsRcvEn_Diff(pDCTstat, dct, dev, index_reg, 0x20)) - goto Trdrd_1; - /* DqsRcvEn byte 7,6*/ - if (Check_DqsRcvEn_Diff(pDCTstat, dct, dev, index_reg, 0x21)) - goto Trdrd_1; - /* DqsRcvEn ECC*/ - if (Check_DqsRcvEn_Diff(pDCTstat, dct, dev, index_reg, 0x12)) - goto Trdrd_1; - Trdrd = 0; - Trdrd_1: - ; - } - pDCTstat->Trdrd = Trdrd; - -} - - -static void Get_Twrwr(struct MCTStatStruc *pMCTstat, - struct DCTStatStruc *pDCTstat, u8 dct) -{ - u8 Twrwr = 0; - u32 index_reg = 0x98 + 0x100 * dct; - u32 dev = pDCTstat->dev_dct; - u32 val; - u32 dword; - - /* WrDatGrossDlyByte only use one set register when DDR400~DDR667 - DDR800 have two set register for DIMM0 and DIMM1 */ - if (pDCTstat->Speed > 3) { - val = bsf(pDCTstat->DIMMValid); - dword = bsr(pDCTstat->DIMMValid); - if (dword != val && dword != 0) { - /*the largest WrDatGrossDlyByte of any DIMM minus the - WrDatGrossDlyByte of any other DIMM is equal to CGDD */ - val = Get_WrDatGross_Diff(pDCTstat, dct, dev, index_reg); - } - if (val == 0) - Twrwr = 2; - else - Twrwr = 3; - } - pDCTstat->Twrwr = Twrwr; -} - - -static void Get_Twrrd(struct MCTStatStruc *pMCTstat, - struct DCTStatStruc *pDCTstat, u8 dct) -{ - u8 byte, bytex, val; - u32 index_reg = 0x98 + 0x100 * dct; - u32 dev = pDCTstat->dev_dct; - - /* On any given byte lane, the largest WrDatGrossDlyByte delay of - any DIMM minus the DqsRcvEnGrossDelay delay of any other DIMM is - equal to the Critical Gross Delay Difference (CGDD) for Twrrd.*/ - - /* WrDatGrossDlyByte only use one set register when DDR400~DDR667 - DDR800 have two set register for DIMM0 and DIMM1 */ - if (pDCTstat->Speed > 3) { - val = Get_WrDatGross_Diff(pDCTstat, dct, dev, index_reg); - } else { - val = Get_WrDatGross_MaxMin(pDCTstat, dct, dev, index_reg, 1); /* WrDatGrossDlyByte byte 0,1,2,3 for DIMM0 */ - pDCTstat->WrDatGrossH = (u8) val; /* low byte = max value */ - } - - Get_DqsRcvEnGross_Diff(pDCTstat, dev, index_reg); - - bytex = pDCTstat->DqsRcvEnGrossL; - byte = pDCTstat->WrDatGrossH; - if (byte > bytex) { - byte -= bytex; - if (byte == 1) - bytex = 1; - else - bytex = 2; - } else { - bytex = 0; - } - pDCTstat->Twrrd = bytex; -} - - -static void Get_TrwtTO(struct MCTStatStruc *pMCTstat, - struct DCTStatStruc *pDCTstat, u8 dct) -{ - u8 byte, bytex; - u32 index_reg = 0x98 + 0x100 * dct; - u32 dev = pDCTstat->dev_dct; - - /* On any given byte lane, the largest WrDatGrossDlyByte delay of - any DIMM minus the DqsRcvEnGrossDelay delay of any other DIMM is - equal to the Critical Gross Delay Difference (CGDD) for TrwtTO. */ - Get_DqsRcvEnGross_Diff(pDCTstat, dev, index_reg); - Get_WrDatGross_Diff(pDCTstat, dct, dev, index_reg); - bytex = pDCTstat->DqsRcvEnGrossL; - byte = pDCTstat->WrDatGrossH; - if (bytex > byte) { - bytex -= byte; - if ((bytex == 1) || (bytex == 2)) - bytex = 3; - else - bytex = 4; - } else { - byte -= bytex; - if ((byte == 0) || (byte == 1)) - bytex = 2; - else - bytex = 1; - } - - pDCTstat->TrwtTO = bytex; -} - - -static void Get_TrwtWB(struct MCTStatStruc *pMCTstat, - struct DCTStatStruc *pDCTstat) -{ - /* TrwtWB ensures read-to-write data-bus turnaround. - This value should be one more than the programmed TrwtTO.*/ - pDCTstat->TrwtWB = pDCTstat->TrwtTO + 1; -} - - -static u8 Check_DqsRcvEn_Diff(struct DCTStatStruc *pDCTstat, - u8 dct, u32 dev, u32 index_reg, - u32 index) -{ - u8 Smallest_0, Largest_0, Smallest_1, Largest_1; - u8 i; - u32 val; - u8 byte; - u8 ecc_reg = 0; - - Smallest_0 = 0xFF; - Smallest_1 = 0xFF; - Largest_0 = 0; - Largest_1 = 0; - - if (index == 0x12) - ecc_reg = 1; - - for (i = 0; i < 8; i+=2) { - if (pDCTstat->DIMMValid & (1 << i)) { - val = Get_NB32_index_wait(dev, index_reg, index); - byte = val & 0xFF; - if (byte < Smallest_0) - Smallest_0 = byte; - if (byte > Largest_0) - Largest_0 = byte; - if (!(ecc_reg)) { - byte = (val >> 16) & 0xFF; - if (byte < Smallest_1) - Smallest_1 = byte; - if (byte > Largest_1) - Largest_1 = byte; - } - } - index += 3; - } /* while ++i */ - - /* check if total DqsRcvEn delay difference between any - two DIMMs is less than half of a MEMCLK */ - if ((Largest_0 - Smallest_0) > 31) - return 1; - if (!(ecc_reg)) - if ((Largest_1 - Smallest_1) > 31) - return 1; - return 0; -} - - -static u8 Get_DqsRcvEnGross_Diff(struct DCTStatStruc *pDCTstat, - u32 dev, u32 index_reg) -{ - u8 Smallest, Largest; - u32 val; - u8 byte, bytex; - - /* The largest DqsRcvEnGrossDelay of any DIMM minus the - DqsRcvEnGrossDelay of any other DIMM is equal to the Critical - Gross Delay Difference (CGDD) */ - /* DqsRcvEn byte 1,0 */ - val = Get_DqsRcvEnGross_MaxMin(pDCTstat, dev, index_reg, 0x10); - Largest = val & 0xFF; - Smallest = (val >> 8) & 0xFF; - - /* DqsRcvEn byte 3,2 */ - val = Get_DqsRcvEnGross_MaxMin(pDCTstat, dev, index_reg, 0x11); - byte = val & 0xFF; - bytex = (val >> 8) & 0xFF; - if (bytex < Smallest) - Smallest = bytex; - if (byte > Largest) - Largest = byte; - - /* DqsRcvEn byte 5,4 */ - val = Get_DqsRcvEnGross_MaxMin(pDCTstat, dev, index_reg, 0x20); - byte = val & 0xFF; - bytex = (val >> 8) & 0xFF; - if (bytex < Smallest) - Smallest = bytex; - if (byte > Largest) - Largest = byte; - - /* DqsRcvEn byte 7,6 */ - val = Get_DqsRcvEnGross_MaxMin(pDCTstat, dev, index_reg, 0x21); - byte = val & 0xFF; - bytex = (val >> 8) & 0xFF; - if (bytex < Smallest) - Smallest = bytex; - if (byte > Largest) - Largest = byte; - - if (pDCTstat->DimmECCPresent> 0) { - /*DqsRcvEn Ecc */ - val = Get_DqsRcvEnGross_MaxMin(pDCTstat, dev, index_reg, 0x12); - byte = val & 0xFF; - bytex = (val >> 8) & 0xFF; - if (bytex < Smallest) - Smallest = bytex; - if (byte > Largest) - Largest = byte; - } - - pDCTstat->DqsRcvEnGrossL = Largest; - return Largest - Smallest; -} - - -static u8 Get_WrDatGross_Diff(struct DCTStatStruc *pDCTstat, - u8 dct, u32 dev, u32 index_reg) -{ - u8 Smallest, Largest; - u32 val; - u8 byte, bytex; - - /* The largest WrDatGrossDlyByte of any DIMM minus the - WrDatGrossDlyByte of any other DIMM is equal to CGDD */ - val = Get_WrDatGross_MaxMin(pDCTstat, dct, dev, index_reg, 0x01); /* WrDatGrossDlyByte byte 0,1,2,3 for DIMM0 */ - Largest = val & 0xFF; - Smallest = (val >> 8) & 0xFF; - val = Get_WrDatGross_MaxMin(pDCTstat, dct, dev, index_reg, 0x101); /* WrDatGrossDlyByte byte 0,1,2,3 for DIMM1 */ - byte = val & 0xFF; - bytex = (val >> 8) & 0xFF; - if (bytex < Smallest) - Smallest = bytex; - if (byte > Largest) - Largest = byte; - - // FIXME: Add Cx support. - - pDCTstat->WrDatGrossH = Largest; - return Largest - Smallest; -} - -static u16 Get_DqsRcvEnGross_MaxMin(struct DCTStatStruc *pDCTstat, - u32 dev, u32 index_reg, - u32 index) -{ - u8 Smallest, Largest; - u8 i; - u8 byte; - u32 val; - u16 word; - u8 ecc_reg = 0; - - Smallest = 7; - Largest = 0; - - if (index == 0x12) - ecc_reg = 1; - - for (i = 0; i < 8; i+=2) { - if (pDCTstat->DIMMValid & (1 << i)) { - val = Get_NB32_index_wait(dev, index_reg, index); - val &= 0x00E000E0; - byte = (val >> 5) & 0xFF; - if (byte < Smallest) - Smallest = byte; - if (byte > Largest) - Largest = byte; - if (!(ecc_reg)) { - byte = (val >> (16 + 5)) & 0xFF; - if (byte < Smallest) - Smallest = byte; - if (byte > Largest) - Largest = byte; - } - } - index += 3; - } /* while ++i */ - - word = Smallest; - word <<= 8; - word |= Largest; - - return word; -} - -static u16 Get_WrDatGross_MaxMin(struct DCTStatStruc *pDCTstat, - u8 dct, u32 dev, u32 index_reg, - u32 index) -{ - u8 Smallest, Largest; - u8 i, j; - u32 val; - u8 byte; - u16 word; - - Smallest = 3; - Largest = 0; - for (i = 0; i < 2; i++) { - val = Get_NB32_index_wait(dev, index_reg, index); - val &= 0x60606060; - val >>= 5; - for (j = 0; j < 4; j++) { - byte = val & 0xFF; - if (byte < Smallest) - Smallest = byte; - if (byte > Largest) - Largest = byte; - val >>= 8; - } /* while ++j */ - index++; - } /*while ++i*/ - - if (pDCTstat->DimmECCPresent > 0) { - index++; - val = Get_NB32_index_wait(dev, index_reg, index); - val &= 0x00000060; - val >>= 5; - byte = val & 0xFF; - if (byte < Smallest) - Smallest = byte; - if (byte > Largest) - Largest = byte; - } - - word = Smallest; - word <<= 8; - word |= Largest; - - return word; -} - - - -static void mct_FinalMCT_D(struct MCTStatStruc *pMCTstat, - struct DCTStatStruc *pDCTstat) -{ - print_t("\tmct_FinalMCT_D: Clr Cl, Wb\n"); - - - /* ClrClToNB_D postponed until we're done executing from ROM */ - mct_ClrWbEnhWsbDis_D(pMCTstat, pDCTstat); -} - - -static void mct_InitialMCT_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstat) -{ - print_t("\tmct_InitialMCT_D: Set Cl, Wb\n"); - mct_SetClToNB_D(pMCTstat, pDCTstat); - mct_SetWbEnhWsbDis_D(pMCTstat, pDCTstat); -} - - -static u32 mct_NodePresent_D(void) -{ - u32 val; - val = 0x12001022; - return val; -} - - -static void mct_init(struct MCTStatStruc *pMCTstat, - struct DCTStatStruc *pDCTstat) -{ - u32 lo, hi; - u32 addr; - - pDCTstat->GangedMode = 0; - pDCTstat->DRPresent = 1; - - /* enable extend PCI configuration access */ - addr = NB_CFG_MSR; - _RDMSR(addr, &lo, &hi); - if (hi & (1 << (46-32))) { - pDCTstat->Status |= 1 << SB_ExtConfig; - } else { - hi |= 1 << (46-32); - _WRMSR(addr, lo, hi); - } -} - - -static void clear_legacy_Mode(struct MCTStatStruc *pMCTstat, - struct DCTStatStruc *pDCTstat) -{ - u32 reg; - u32 val; - u32 dev = pDCTstat->dev_dct; - - /* Clear Legacy BIOS Mode bit */ - reg = 0x94; - val = Get_NB32(dev, reg); - val &= ~(1<dev_map; - - /* Copy dram map from F1x40/44,F1x48/4c, - to F1x120/124(Node0),F1x120/124(Node1),...*/ - for (Node = 0; Node < MAX_NODES_SUPPORTED; Node++) { - pDCTstat = pDCTstatA + Node; - devx = pDCTstat->dev_map; - - /* get base/limit from Node0 */ - reg = 0x40 + (Node << 3); /* Node0/Dram Base 0 */ - val = Get_NB32(dev, reg); - Drambase = val >> (16 + 3); - - reg = 0x44 + (Node << 3); /* Node0/Dram Base 0 */ - val = Get_NB32(dev, reg); - Dramlimit = val >> (16 + 3); - - /* set base/limit to F1x120/124 per Node */ - if (pDCTstat->NodePresent) { - reg = 0x120; /* F1x120,DramBase[47:27] */ - val = Get_NB32(devx, reg); - val &= 0xFFE00000; - val |= Drambase; - Set_NB32(devx, reg, val); - - reg = 0x124; - val = Get_NB32(devx, reg); - val &= 0xFFE00000; - val |= Dramlimit; - Set_NB32(devx, reg, val); - - if (pMCTstat->GStatus & (1 << GSB_HWHole)) { - reg = 0xF0; - val = Get_NB32(devx, reg); - val |= (1 << DramMemHoistValid); - val &= ~(0xFF << 24); - dword = (pMCTstat->HoleBase >> (24 - 8)) & 0xFF; - dword <<= 24; - val |= dword; - Set_NB32(devx, reg, val); - } - - } - } -} - -static void SetCSTriState(struct MCTStatStruc *pMCTstat, - struct DCTStatStruc *pDCTstat, u8 dct) -{ - u32 val; - u32 dev = pDCTstat->dev_dct; - u32 index_reg = 0x98 + 0x100 * dct; - u8 cs; - u32 index; - u16 word; - - /* Tri-state unused chipselects when motherboard - termination is available */ - - // FIXME: skip for Ax - - word = pDCTstat->CSPresent; - if (pDCTstat->Status & (1 << SB_Registered)) { - for (cs = 0; cs < 8; cs++) { - if (word & (1 << cs)) { - if (!(cs & 1)) - word |= 1 << (cs + 1); - } - } - } - word = (~word) & 0xFF; - index = 0x0c; - val = Get_NB32_index_wait(dev, index_reg, index); - val |= word; - Set_NB32_index_wait(dev, index_reg, index, val); -} - - -#ifdef UNUSED_CODE -static void SetCKETriState(struct MCTStatStruc *pMCTstat, - struct DCTStatStruc *pDCTstat, u8 dct) -{ - u32 val; - u32 dev; - u32 index_reg = 0x98 + 0x100 * dct; - u8 cs; - u32 index; - u16 word; - - /* Tri-state unused CKEs when motherboard termination is available */ - - // FIXME: skip for Ax - - dev = pDCTstat->dev_dct; - word = 0x101; - for (cs = 0; cs < 8; cs++) { - if (pDCTstat->CSPresent & (1 << cs)) { - if (!(cs & 1)) - word &= 0xFF00; - else - word &= 0x00FF; - } - } - - index = 0x0c; - val = Get_NB32_index_wait(dev, index_reg, index); - if ((word & 0x00FF) == 1) - val |= 1 << 12; - else - val &= ~(1 << 12); - - if ((word >> 8) == 1) - val |= 1 << 13; - else - val &= ~(1 << 13); - - Set_NB32_index_wait(dev, index_reg, index, val); -} -#endif - -static void SetODTTriState(struct MCTStatStruc *pMCTstat, - struct DCTStatStruc *pDCTstat, u8 dct) -{ - u32 val; - u32 dev; - u32 index_reg = 0x98 + 0x100 * dct; - u8 cs; - u32 index; - u8 odt; - u8 max_dimms; - - // FIXME: skip for Ax - - dev = pDCTstat->dev_dct; - - /* Tri-state unused ODTs when motherboard termination is available */ - max_dimms = (u8) mctGet_NVbits(NV_MAX_DIMMS); - odt = 0x0F; /* tristate all the pins then clear the used ones. */ - - for (cs = 0; cs < 8; cs += 2) { - if (pDCTstat->CSPresent & (1 << cs)) { - odt &= ~(1 << (cs / 2)); - - /* if quad-rank capable platform clear additional pins */ - if (max_dimms != MAX_CS_SUPPORTED) { - if (pDCTstat->CSPresent & (1 << (cs + 1))) - odt &= ~(4 << (cs / 2)); - } - } - } - - index = 0x0C; - val = Get_NB32_index_wait(dev, index_reg, index); - val |= (odt << 8); - Set_NB32_index_wait(dev, index_reg, index, val); - -} - - -static void InitPhyCompensation(struct MCTStatStruc *pMCTstat, - struct DCTStatStruc *pDCTstat, u8 dct) -{ - u8 i; - u32 index_reg = 0x98 + 0x100 * dct; - u32 dev = pDCTstat->dev_dct; - u32 val; - u32 valx = 0; - u32 dword; - const u8 *p; - - val = Get_NB32_index_wait(dev, index_reg, 0x00); - dword = 0; - for (i = 0; i < 6; i++) { - switch (i) { - case 0: - case 4: - p = Table_Comp_Rise_Slew_15x; - valx = p[(val >> 16) & 3]; - break; - case 1: - case 5: - p = Table_Comp_Fall_Slew_15x; - valx = p[(val >> 16) & 3]; - break; - case 2: - p = Table_Comp_Rise_Slew_20x; - valx = p[(val >> 8) & 3]; - break; - case 3: - p = Table_Comp_Fall_Slew_20x; - valx = p[(val >> 8) & 3]; - break; - - } - dword |= valx << (5 * i); - } - - /* Override/Exception */ - if (!pDCTstat->GangedMode) { - i = 0; /* use i for the dct setting required */ - if (pDCTstat->MAdimms[0] < 4) - i = 1; - if (((pDCTstat->Speed == 2) || (pDCTstat->Speed == 3)) && (pDCTstat->MAdimms[i] == 4)) { - dword &= 0xF18FFF18; - index_reg = 0x98; /* force dct = 0 */ - } - } - - Set_NB32_index_wait(dev, index_reg, 0x0a, dword); -} - - -static void WaitRoutine_D(u32 time) -{ - while (time) { - _EXECFENCE; - time--; - } -} - - -static void mct_EarlyArbEn_D(struct MCTStatStruc *pMCTstat, - struct DCTStatStruc *pDCTstat) -{ - u32 reg; - u32 val; - u32 dev = pDCTstat->dev_dct; - - /* GhEnhancement #18429 modified by askar: For low NB CLK : - * Memclk ratio, the DCT may need to arbitrate early to avoid - * unnecessary bubbles. - * bit 19 of F2x[1,0]78 Dram Control Register, set this bit only when - * NB CLK : Memclk ratio is between 3:1 (inclusive) to 4:5 (inclusive) - */ - - reg = 0x78; - val = Get_NB32(dev, reg); - - //FIXME: check for Cx - if (CheckNBCOFEarlyArbEn(pMCTstat, pDCTstat)) - val |= (1 << EarlyArbEn); - - Set_NB32(dev, reg, val); - -} - - -static u8 CheckNBCOFEarlyArbEn(struct MCTStatStruc *pMCTstat, - struct DCTStatStruc *pDCTstat) -{ - u32 reg; - u32 val; - u32 tmp; - u32 rem; - u32 dev = pDCTstat->dev_dct; - u32 hi, lo; - u8 NbDid = 0; - - /* Check if NB COF >= 4*Memclk, if it is not, return a fatal error - */ - - /* 3*(Fn2xD4[NBFid]+4)/(2^NbDid)/(3+Fn2x94[MemClkFreq]) */ - _RDMSR(MSR_COFVID_STS, &lo, &hi); - if (lo & (1 << 22)) - NbDid |= 1; - - - reg = 0x94; - val = Get_NB32(dev, reg); - if (!(val & (1 << MemClkFreqVal))) - val = Get_NB32(dev, reg * 0x100); /* get the DCT1 value */ - - val &= 0x07; - val += 3; - if (NbDid) - val <<= 1; - tmp = val; - - dev = pDCTstat->dev_nbmisc; - reg = 0xD4; - val = Get_NB32(dev, reg); - val &= 0x1F; - val += 3; - val *= 3; - val = val / tmp; - rem = val % tmp; - tmp >>= 1; - - // Yes this could be nicer but this was how the asm was.... - if (val < 3) { /* NClk:MemClk < 3:1 */ - return 0; - } else if (val > 4) { /* NClk:MemClk >= 5:1 */ - return 0; - } else if ((val == 4) && (rem > tmp)) { /* NClk:MemClk > 4.5:1 */ - return 0; - } else { - return 1; /* 3:1 <= NClk:MemClk <= 4.5:1*/ - } -} - - -static void mct_ResetDataStruct_D(struct MCTStatStruc *pMCTstat, - struct DCTStatStruc *pDCTstatA) -{ - u8 Node; - struct DCTStatStruc *pDCTstat; - - /* Initialize Data structures by clearing all entries to 0 */ - memset(pMCTstat, 0x00, sizeof(*pMCTstat)); - - for (Node = 0; Node < 8; Node++) { - pDCTstat = pDCTstatA + Node; - - /* Clear all entries except persistentData */ - memset(pDCTstat, 0x00, sizeof(*pDCTstat) - sizeof(pDCTstat->persistentData)); - } -} - - -static void mct_BeforeDramInit_Prod_D(struct MCTStatStruc *pMCTstat, - struct DCTStatStruc *pDCTstat) -{ - u8 i; - u32 reg_off; - u32 dev = pDCTstat->dev_dct; - - // FIXME: skip for Ax - if ((pDCTstat->Speed == 3) || (pDCTstat->Speed == 2)) { // MemClkFreq = 667MHz or 533MHz - for (i = 0; i < 2; i++) { - reg_off = 0x100 * i; - Set_NB32(dev, 0x98 + reg_off, 0x0D000030); - Set_NB32(dev, 0x9C + reg_off, 0x00000806); - Set_NB32(dev, 0x98 + reg_off, 0x4D040F30); - } - } -} - - -void mct_AdjustDelayRange_D(struct MCTStatStruc *pMCTstat, - struct DCTStatStruc *pDCTstat, u8 *dqs_pos) -{ - // FIXME: Skip for Ax - if ((pDCTstat->Speed == 3) || (pDCTstat->Speed == 2)) { // MemClkFreq = 667MHz or 533MHz - *dqs_pos = 32; - } -} - -static u32 mct_DisDllShutdownSR(struct MCTStatStruc *pMCTstat, - struct DCTStatStruc *pDCTstat, u32 DramConfigLo, u8 dct) -{ - u32 reg_off = 0x100 * dct; - u32 dev = pDCTstat->dev_dct; - - /* Write 0000_07D0h to register F2x[1, 0]98_x4D0FE006 */ - if (pDCTstat->LogicalCPUID & (AMD_DA_C2 | AMD_RB_C3)) { - Set_NB32(dev, 0x9C + reg_off, 0x7D0); - Set_NB32(dev, 0x98 + reg_off, 0x4D0FE006); - Set_NB32(dev, 0x9C + reg_off, 0x190); - Set_NB32(dev, 0x98 + reg_off, 0x4D0FE007); - } - - return DramConfigLo | /* DisDllShutdownSR */ 1 << 27; -} - -static void mct_EnDllShutdownSR(struct MCTStatStruc *pMCTstat, - struct DCTStatStruc *pDCTstat, u8 dct) -{ - u32 reg_off = 0x100 * dct; - u32 dev = pDCTstat->dev_dct, val; - - /* Write 0000_07D0h to register F2x[1, 0]98_x4D0FE006 */ - if (pDCTstat->LogicalCPUID & (AMD_DA_C2 | AMD_RB_C3)) { - Set_NB32(dev, 0x9C + reg_off, 0x1C); - Set_NB32(dev, 0x98 + reg_off, 0x4D0FE006); - Set_NB32(dev, 0x9C + reg_off, 0x13D); - Set_NB32(dev, 0x98 + reg_off, 0x4D0FE007); - - val = Get_NB32(dev, 0x90 + reg_off); - val &= ~(1 << 27/* DisDllShutdownSR */); - Set_NB32(dev, 0x90 + reg_off, val); - } -} - -void mct_SetClToNB_D(struct MCTStatStruc *pMCTstat, - struct DCTStatStruc *pDCTstat) -{ - u32 lo, hi; - u32 msr; - - // FIXME: Maybe check the CPUID? - not for now. - // pDCTstat->LogicalCPUID; - - msr = BU_CFG2_MSR; - _RDMSR(msr, &lo, &hi); - lo |= 1 << ClLinesToNbDis; - _WRMSR(msr, lo, hi); -} - - -void mct_ClrClToNB_D(struct MCTStatStruc *pMCTstat, - struct DCTStatStruc *pDCTstat) -{ - - u32 lo, hi; - u32 msr; - - // FIXME: Maybe check the CPUID? - not for now. - // pDCTstat->LogicalCPUID; - - msr = BU_CFG2_MSR; - _RDMSR(msr, &lo, &hi); - if (!pDCTstat->ClToNB_flag) - lo &= ~(1 << ClLinesToNbDis); - _WRMSR(msr, lo, hi); - -} - - -void mct_SetWbEnhWsbDis_D(struct MCTStatStruc *pMCTstat, - struct DCTStatStruc *pDCTstat) -{ - u32 lo, hi; - u32 msr; - - // FIXME: Maybe check the CPUID? - not for now. - // pDCTstat->LogicalCPUID; - - msr = BU_CFG_MSR; - _RDMSR(msr, &lo, &hi); - hi |= (1 << WbEnhWsbDis_D); - _WRMSR(msr, lo, hi); -} - - -void mct_ClrWbEnhWsbDis_D(struct MCTStatStruc *pMCTstat, - struct DCTStatStruc *pDCTstat) -{ - u32 lo, hi; - u32 msr; - - // FIXME: Maybe check the CPUID? - not for now. - // pDCTstat->LogicalCPUID; - - msr = BU_CFG_MSR; - _RDMSR(msr, &lo, &hi); - hi &= ~(1 << WbEnhWsbDis_D); - _WRMSR(msr, lo, hi); -} - - -void mct_SetDramConfigHi_D(struct DCTStatStruc *pDCTstat, u32 dct, - u32 DramConfigHi) -{ - /* Bug#15114: Comp. update interrupted by Freq. change can cause - * subsequent update to be invalid during any MemClk frequency change: - * Solution: From the bug report: - * 1. A software-initiated frequency change should be wrapped into the - * following sequence : - * a) Disable Compensation (F2[1, 0]9C_x08[30]) - * b) Reset the Begin Compensation bit (D3CMP->COMP_CONFIG[0]) in - * all the compensation engines - * c) Do frequency change - * d) Enable Compensation (F2[1, 0]9C_x08[30]) - * 2. A software-initiated Disable Compensation should always be - * followed by step b) of the above steps. - * Silicon Status: Fixed In Rev B0 - * - * Errata#177: DRAM Phy Automatic Compensation Updates May Be Invalid - * Solution: BIOS should disable the phy automatic compensation prior - * to initiating a memory clock frequency change as follows: - * 1. Disable PhyAutoComp by writing 1'b1 to F2x[1, 0]9C_x08[30] - * 2. Reset the Begin Compensation bits by writing 32'h0 to - * F2x[1, 0]9C_x4D004F00 - * 3. Perform frequency change - * 4. Enable PhyAutoComp by writing 1'b0 to F2x[1, 0]9C_08[30] - * In addition, any time software disables the automatic phy - * compensation it should reset the begin compensation bit per step 2. - * Silicon Status: Fixed in DR-B0 - */ - - u32 dev = pDCTstat->dev_dct; - u32 index_reg = 0x98 + 0x100 * dct; - u32 index; - - u32 val; - - index = 0x08; - val = Get_NB32_index_wait(dev, index_reg, index); - Set_NB32_index_wait(dev, index_reg, index, val | (1 << DisAutoComp)); - - //FIXME: check for Bx Cx CPU - // if Ax mct_SetDramConfigHi_Samp_D - - /* errata#177 */ - index = 0x4D014F00; /* F2x[1, 0]9C_x[D0FFFFF:D000000] DRAM Phy Debug Registers */ - index |= 1 << DctAccessWrite; - val = 0; - Set_NB32_index_wait(dev, index_reg, index, val); - - Set_NB32(dev, 0x94 + 0x100 * dct, DramConfigHi); - - index = 0x08; - val = Get_NB32_index_wait(dev, index_reg, index); - Set_NB32_index_wait(dev, index_reg, index, val & (~(1 << DisAutoComp))); -} - -static void mct_BeforeDQSTrain_D(struct MCTStatStruc *pMCTstat, - struct DCTStatStruc *pDCTstatA) -{ - u8 Node; - struct DCTStatStruc *pDCTstat; - - /* Errata 178 - * - * Bug#15115: Uncertainty In The Sync Chain Leads To Setup Violations - * In TX FIFO - * Solution: BIOS should program DRAM Control Register[RdPtrInit] = - * 5h, (F2x[1, 0]78[3:0] = 5h). - * Silicon Status: Fixed In Rev B0 - * - * Bug#15880: Determine validity of reset settings for DDR PHY timing. - * Solution: At least, set WrDqs fine delay to be 0 for DDR2 training. - */ - - for (Node = 0; Node < 8; Node++) { - pDCTstat = pDCTstatA + Node; - - if (pDCTstat->NodePresent) { - mct_BeforeDQSTrain_Samp_D(pMCTstat, pDCTstat); - mct_ResetDLL_D(pMCTstat, pDCTstat, 0); - mct_ResetDLL_D(pMCTstat, pDCTstat, 1); - } - } -} - -static void mct_ResetDLL_D(struct MCTStatStruc *pMCTstat, - struct DCTStatStruc *pDCTstat, u8 dct) -{ - u8 Receiver; - u32 dev = pDCTstat->dev_dct; - u32 reg_off = 0x100 * dct; - u32 addr; - u32 lo, hi; - u8 wrap32dis = 0; - u8 valid = 0; - - /* Skip reset DLL for B3 */ - if (pDCTstat->LogicalCPUID & AMD_DR_B3) { - return; - } - - addr = HWCR_MSR; - _RDMSR(addr, &lo, &hi); - if (lo & (1<<17)) { /* save the old value */ - wrap32dis = 1; - } - lo |= (1<<17); /* HWCR.wrap32dis */ - lo &= ~(1<<15); /* SSEDIS */ - /* Setting wrap32dis allows 64-bit memory references in 32bit mode */ - _WRMSR(addr, lo, hi); - - - pDCTstat->Channel = dct; - Receiver = mct_InitReceiver_D(pDCTstat, dct); - /* there are four receiver pairs, loosely associated with chipselects.*/ - for (; Receiver < 8; Receiver += 2) { - if (mct_RcvrRankEnabled_D(pMCTstat, pDCTstat, dct, Receiver)) { - addr = mct_GetRcvrSysAddr_D(pMCTstat, pDCTstat, dct, Receiver, &valid); - if (valid) { - mct_Read1LTestPattern_D(pMCTstat, pDCTstat, addr); /* cache fills */ - - /* Write 0000_8000h to register F2x[1,0]9C_xD080F0C */ - Set_NB32_index_wait(dev, 0x98 + reg_off, 0x4D080F0C, 0x00008000); - mct_Wait(80); /* wait >= 300ns */ - - /* Write 0000_0000h to register F2x[1,0]9C_xD080F0C */ - Set_NB32_index_wait(dev, 0x98 + reg_off, 0x4D080F0C, 0x00000000); - mct_Wait(800); /* wait >= 2us */ - break; - } - } - } - if (!wrap32dis) { - addr = HWCR_MSR; - _RDMSR(addr, &lo, &hi); - lo &= ~(1<<17); /* restore HWCR.wrap32dis */ - _WRMSR(addr, lo, hi); - } -} - - -void mct_EnableDatIntlv_D(struct MCTStatStruc *pMCTstat, - struct DCTStatStruc *pDCTstat) -{ - u32 dev = pDCTstat->dev_dct; - u32 val; - - /* Enable F2x110[DctDatIntlv] */ - // Call back not required mctHookBeforeDatIntlv_D() - // FIXME Skip for Ax - if (!pDCTstat->GangedMode) { - val = Get_NB32(dev, 0x110); - val |= 1 << 5; // DctDatIntlv - Set_NB32(dev, 0x110, val); - - // FIXME Skip for Cx - dev = pDCTstat->dev_nbmisc; - val = Get_NB32(dev, 0x8C); // NB Configuration Hi - val |= 1 << (36-32); // DisDatMask - Set_NB32(dev, 0x8C, val); - } -} - -#ifdef UNUSED_CODE -static void mct_SetupSync_D(struct MCTStatStruc *pMCTstat, - struct DCTStatStruc *pDCTstat) -{ - /* set F2x78[ChSetupSync] when F2x[1, 0]9C_x04[AddrCmdSetup, CsOdtSetup, - * CkeSetup] setups for one DCT are all 0s and at least one of the setups, - * F2x[1, 0]9C_x04[AddrCmdSetup, CsOdtSetup, CkeSetup], of the other - * controller is 1 - */ - u32 cha, chb; - u32 dev = pDCTstat->dev_dct; - u32 val; - - cha = pDCTstat->CH_ADDR_TMG[0] & 0x0202020; - chb = pDCTstat->CH_ADDR_TMG[1] & 0x0202020; - - if ((cha != chb) && ((cha == 0) || (chb == 0))) { - val = Get_NB32(dev, 0x78); - val |= ChSetupSync; - Set_NB32(dev, 0x78, val); - } -} -#endif - -static void AfterDramInit_D(struct DCTStatStruc *pDCTstat, u8 dct) { - - u32 val; - u32 reg_off = 0x100 * dct; - u32 dev = pDCTstat->dev_dct; - - if (pDCTstat->LogicalCPUID & (AMD_DR_B2 | AMD_DR_B3)) { - mct_Wait(10000); /* Wait 50 us*/ - val = Get_NB32(dev, 0x110); - if (val & (1 << DramEnabled)) { - /* If 50 us expires while DramEnable =0 then do the following */ - val = Get_NB32(dev, 0x90 + reg_off); - val &= ~(1 << Width128); /* Program Width128 = 0 */ - Set_NB32(dev, 0x90 + reg_off, val); - - val = Get_NB32_index_wait(dev, 0x98 + reg_off, 0x05); /* Perform dummy CSR read to F2x09C_x05 */ - - if (pDCTstat->GangedMode) { - val = Get_NB32(dev, 0x90 + reg_off); - val |= 1 << Width128; /* Program Width128 = 0 */ - Set_NB32(dev, 0x90 + reg_off, val); - } - } - } -} - - -/* ========================================================== - * 6-bit Bank Addressing Table - * RR = rows-13 binary - * B = Banks-2 binary - * CCC = Columns-9 binary - * ========================================================== - * DCT CCCBRR Rows Banks Columns 64-bit CS Size - * Encoding - * 0000 000000 13 2 9 128MB - * 0001 001000 13 2 10 256MB - * 0010 001001 14 2 10 512MB - * 0011 010000 13 2 11 512MB - * 0100 001100 13 3 10 512MB - * 0101 001101 14 3 10 1GB - * 0110 010001 14 2 11 1GB - * 0111 001110 15 3 10 2GB - * 1000 010101 14 3 11 2GB - * 1001 010110 15 3 11 4GB - * 1010 001111 16 3 10 4GB - * 1011 010111 16 3 11 8GB - */ diff --git a/src/northbridge/amd/amdmct/mct/mct_d.h b/src/northbridge/amd/amdmct/mct/mct_d.h deleted file mode 100644 index b985137987..0000000000 --- a/src/northbridge/amd/amdmct/mct/mct_d.h +++ /dev/null @@ -1,804 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2015-2017 Timothy Pearson , Raptor Engineering - * Copyright (C) 2007-2008 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -/* - * Description: Include file for all generic DDR 2 MCT files. - */ -#ifndef MCT_D_H -#define MCT_D_H - -#define DQS_TRAIN_DEBUG 0 - -#include -#include -#include - -#include "mct_d_gcc.h" - -extern const u8 Table_DQSRcvEn_Offset[]; -extern const u32 TestPattern0_D[]; -extern const u32 TestPattern1_D[]; -extern const u32 TestPattern2_D[]; - -/*=========================================================================== - CPU - K8/FAM10 -===========================================================================*/ -#define PT_L1 0 /* CPU Package Type */ -#define PT_M2 1 -#define PT_S1 2 -#define PT_GR 3 - -#define J_MIN 0 /* j loop constraint. 1 = CL 2.0 T*/ -#define J_MAX 5 /* j loop constraint. 5 = CL 7.0 T*/ -#define K_MIN 1 /* k loop constraint. 1 = 200 MHz*/ -#define K_MAX 5 /* k loop constraint. 5 = 533 MHz*/ -#define CL_DEF 2 /* Default value for failsafe operation. 2 = CL 4.0 T*/ -#define T_DEF 1 /* Default value for failsafe operation. 1 = 5ns (cycle time)*/ - -#define BSCRate 1 /* reg bit field = rate of dram scrubber for ecc*/ - /* memory initialization (ecc and check-bits).*/ - /* 1 = 40 ns/64 bytes.*/ -#define FirstPass 1 /* First pass through RcvEn training*/ -#define SecondPass 2 /* Second pass through Rcven training*/ - -#define RCVREN_MARGIN 6 /* number of DLL taps to delay beyond first passing position*/ -#define MAXASYNCLATCTL_2 2 /* Max Async Latency Control value*/ -#define MAXASYNCLATCTL_3 3 /* Max Async Latency Control value*/ - -#define DQS_FAIL 1 -#define DQS_PASS 0 -#define DQS_WRITEDIR 1 -#define DQS_READDIR 0 -#define MIN_DQS_WNDW 3 -#define secPassOffset 6 -#define Pass1MemClkDly 0x20 /* Add 1/2 Memlock delay */ -#define MAX_RD_LAT 0x3FF -#define MIN_FENCE 14 -#define MAX_FENCE 20 -#define MIN_DQS_WR_FENCE 14 -#define MAX_DQS_WR_FENCE 20 -#define FenceTrnFinDlySeed 19 -#define EarlyArbEn 19 - -#define PA_HOST(Node) ((((0x18+Node) << 3)+0) << 12) /* Node 0 Host Bus function PCI Address bits [15:0]*/ -#define PA_MAP(Node) ((((0x18+Node) << 3)+1) << 12) /* Node 0 MAP function PCI Address bits [15:0]*/ -#define PA_DCT(Node) ((((0x18+Node) << 3)+2) << 12) /* Node 0 DCT function PCI Address bits [15:0]*/ -//#define PA_EXT_DCT (((00 << 3)+4) << 8) /*Node 0 DCT extended configuration registers*/ -//#define PA_DCTADDL (((00 << 3)+2) << 8) /*Node x DCT function, Additional Registers PCI Address bits [15:0]*/ -//#define PA_EXT_DCTADDL (((00 << 3)+5) << 8) /*Node x DCT function, Additional Registers PCI Address bits [15:0]*/ - -#define PA_NBMISC(Node) ((((0x18+Node) << 3)+3) << 12) /*Node 0 Misc PCI Address bits [15:0]*/ -//#define PA_NBDEVOP (((00 << 3)+3) << 8) /*Node 0 Misc PCI Address bits [15:0]*/ - -#define DCC_EN 1 /* X:2:0x94[19]*/ -#define ILD_Lmt 3 /* X:2:0x94[18:16]*/ - -#define EncodedTSPD 0x00191709 /* encodes which SPD byte to get T from*/ - /* versus CL X, CL X-.5, and CL X-1*/ - -#define Bias_TrpT 3 /* bias to convert bus clocks to bit field value*/ -#define Bias_TrrdT 2 -#define Bias_TrcdT 3 -#define Bias_TrasT 3 -#define Bias_TrcT 11 -#define Bias_TrtpT 2 -#define Bias_TwrT 3 -#define Bias_TwtrT 0 -#define Bias_TfawT 7 - -#define Min_TrpT 3 /* min programmable value in busclocks*/ -#define Max_TrpT 6 /* max programmable value in busclocks*/ -#define Min_TrrdT 2 -#define Max_TrrdT 5 -#define Min_TrcdT 3 -#define Max_TrcdT 6 -#define Min_TrasT 5 -#define Max_TrasT 18 -#define Min_TrcT 11 -#define Max_TrcT 26 -#define Min_TrtpT 2 -#define Max_TrtpT 3 -#define Min_TwrT 3 -#define Max_TwrT 6 -#define Min_TwtrT 1 -#define Max_TwtrT 3 - -/*DDR2-1066 support*/ -#define Bias_TrcdT_1066 5 -#define Bias_TrasT_1066 15 -#define Bias_TrrdT_1066 4 -#define Bias_TwrT_1066 4 -#define Bias_TrpT_1066 5 -#define Bias_TwtrT_1066 4 -#define Bias_TfawT_1066 15 - -#define Min_TrcdT_1066 5 -#define Max_TrcdT_1066 12 -#define Min_TrasT_1066 15 -#define Max_TrasT_1066 30 -#define Min_TrcT_1066 11 -#define Max_TrcT_1066 42 -#define Min_TrrdT_1066 4 -#define Max_TrrdT_1066 7 -#define Min_TwrT_1066 5 -#define Max_TwrT_1066 8 -#define Min_TrpT_1066 5 -#define Max_TrpT_1066 12 -#define Min_TwtrT_1066 4 -#define Max_TwtrT_1066 7 - -/*common register bit names*/ -#define DramHoleValid 0 /* func 1, offset F0h, bit 0*/ -#define DramMemHoistValid 1 /* func 1, offset F0h, bit 1*/ -#define CSEnable 0 /* func 2, offset 40h-5C, bit 0*/ -#define Spare 1 /* func 2, offset 40h-5C, bit 1*/ -#define TestFail 2 /* func 2, offset 40h-5C, bit 2*/ -#define DqsRcvEnTrain 18 /* func 2, offset 78h, bit 18*/ -#define EnDramInit 31 /* func 2, offset 7Ch, bit 31*/ -#define DisAutoRefresh 18 /* func 2, offset 8Ch, bit 18*/ -#define InitDram 0 /* func 2, offset 90h, bit 0*/ -#define BurstLength32 10 /* func 2, offset 90h, bit 10*/ -#define Width128 11 /* func 2, offset 90h, bit 11*/ -#define X4Dimm 12 /* func 2, offset 90h, bit 12*/ -#define UnBuffDimm 16 /* func 2, offset 90h, bit 16*/ -#define DimmEcEn 19 /* func 2, offset 90h, bit 19*/ -#define MemClkFreqVal 3 /* func 2, offset 94h, bit 3*/ -#define RDqsEn 12 /* func 2, offset 94h, bit 12*/ -#define DisDramInterface 14 /* func 2, offset 94h, bit 14*/ -#define DctAccessWrite 30 /* func 2, offset 98h, bit 30*/ -#define DctAccessDone 31 /* func 2, offset 98h, bit 31*/ -#define MemClrStatus 0 /* func 2, offset A0h, bit 0*/ -#define PwrSavingsEn 10 /* func 2, offset A0h, bit 10*/ -#define Mod64BitMux 4 /* func 2, offset A0h, bit 4*/ -#define DisableJitter 1 /* func 2, offset A0h, bit 1*/ -#define MemClrDis 1 /* func 3, offset F8h, FNC 4, bit 1*/ -#define SyncOnUcEccEn 2 /* func 3, offset 44h, bit 2*/ -#define Dr_MemClrStatus 10 /* func 3, offset 110h, bit 10*/ -#define MemClrBusy 9 /* func 3, offset 110h, bit 9*/ -#define DctGangEn 4 /* func 3, offset 110h, bit 4*/ -#define MemClrInit 3 /* func 3, offset 110h, bit 3*/ -#define AssertCke 28 /* func 2, offset 7Ch, bit 28*/ -#define DeassertMemRstX 27 /* func 2, offset 7Ch, bit 27*/ -#define SendMrsCmd 26 /* func 2, offset 7Ch, bit 26*/ -#define SendAutoRefresh 25 /* func 2, offset 7Ch, bit 25*/ -#define SendPchgAll 24 /* func 2, offset 7Ch, bit 24*/ -#define DisDqsBar 6 /* func 2, offset 90h, bit 6*/ -#define DramEnabled 8 /* func 2, offset 110h, bit 8*/ -#define LegacyBiosMode 9 /* func 2, offset 94h, bit 9*/ -#define PrefDramTrainMode 28 /* func 2, offset 11Ch, bit 28*/ -#define FlushWr 30 /* func 2, offset 11Ch, bit 30*/ -#define DisAutoComp 30 /* func 2, offset 9Ch, Index 8, bit 30*/ -#define DqsRcvTrEn 13 /* func 2, offset 9Ch, Index 8, bit 13*/ -#define ForceAutoPchg 23 /* func 2, offset 90h, bit 23*/ -#define ClLinesToNbDis 15 /* Bu_CFG2, bit 15*/ -#define WbEnhWsbDis_D (48-32) -#define PhyFenceTrEn 3 /* func 2, offset 9Ch, Index 8, bit 3 */ -#define ParEn 8 /* func 2, offset 90h, bit 8 */ -#define DcqArbBypassEn 19 /* func 2, offset 94h, bit 19 */ -#define ActiveCmdAtRst 1 /* func 2, offset A8H, bit 1 */ -#define FlushWrOnStpGnt 29 /* func 2, offset 11Ch, bit 29 */ -#define BankSwizzleMode 22 /* func 2, offset 94h, bit 22 */ -#define ChSetupSync 15 /* func 2, offset 78h, bit 15 */ - - - -/*============================================================================= - SW Initialization -============================================================================*/ -#define DLL_Enable 1 -#define OCD_Default 2 -#define OCD_Exit 3 - - - -/*============================================================================= - Jedec DDR II -=============================================================================*/ -#define SPD_TYPE 2 /*SPD byte read location*/ - #define JED_DDRSDRAM 0x07 /*Jedec defined bit field*/ - #define JED_DDR2SDRAM 0x08 /*Jedec defined bit field*/ - -#define SPD_DIMMTYPE 20 -#define SPD_ATTRIB 21 - #define JED_DIFCKMSK 0x20 /*Differential Clock Input*/ - #define JED_REGADCMSK 0x11 /*Registered Address/Control*/ - #define JED_PROBEMSK 0x40 /*Analysis Probe installed*/ -#define SPD_DEVATTRIB 22 -#define SPD_EDCTYPE 11 - #define JED_ECC 0x02 - #define JED_ADRCPAR 0x04 -#define SPD_ROWSZ 3 -#define SPD_COLSZ 4 -#define SPD_LBANKS 17 /*number of [logical] banks on each device*/ -#define SPD_DMBANKS 5 /*number of physical banks on dimm*/ - #define SPDPLBit 4 /* Dram package bit*/ -#define SPD_BANKSZ 31 /*capacity of physical bank*/ -#define SPD_DEVWIDTH 13 -#define SPD_CASLAT 18 -#define SPD_TRP 27 -#define SPD_TRRD 28 -#define SPD_TRCD 29 -#define SPD_TRAS 30 -#define SPD_TWR 36 -#define SPD_TWTR 37 -#define SPD_TRTP 38 -#define SPD_TRCRFC 40 -#define SPD_TRC 41 -#define SPD_TRFC 42 - -#define SPD_MANID_START 64 -#define SPD_PARTN_START 73 -#define SPD_PARTN_LENGTH 18 -#define SPD_REVNO_START 91 - -#define SPD_MANDATEYR 93 /*Module Manufacturing Year (BCD)*/ - -#define SPD_MANDATEWK 94 /*Module Manufacturing Week (BCD)*/ - -#define SPD_SERIAL_START 95 - -/*----------------------------- - Jedec DDR II related equates ------------------------------*/ -#define MYEAR06 6 /* Manufacturing Year BCD encoding of 2006 - 06d*/ -#define MWEEK24 0x24 /* Manufacturing Week BCD encoding of June - 24d*/ - -/*============================================================================= - Macros -=============================================================================*/ - -#define _2GB_RJ8 (2<<(30-8)) -#define _4GB_RJ8 (4<<(30-8)) -#define _4GB_RJ4 (4<<(30-4)) - -#define BigPagex8_RJ8 (1<<(17+3-8)) /*128KB * 8 >> 8 */ - -/*============================================================================= - Global MCT Status Structure -=============================================================================*/ -struct MCTStatStruc { - u32 GStatus; /* Global Status bitfield*/ - u32 HoleBase; /* If not zero, BASE[39:8] (system address) - of sub 4GB dram hole for HW remapping.*/ - u32 Sub4GCacheTop; /* If not zero, the 32-bit top of cacheable memory.*/ - u32 SysLimit; /* LIMIT[39:8] (system address)*/ -} __packed; - -/*============================================================================= - Global MCT Configuration Status Word (GStatus) -=============================================================================*/ -/*These should begin at bit 0 of GStatus[31:0]*/ -#define GSB_MTRRshort 0 /* Ran out of MTRRs while mapping memory*/ -#define GSB_ECCDIMMs 1 /* All banks of all Nodes are ECC capable*/ -#define GSB_DramECCDis 2 /* Dram ECC requested but not enabled.*/ -#define GSB_SoftHole 3 /* A Node Base gap was created*/ -#define GSB_HWHole 4 /* A HW dram remap was created*/ -#define GSB_NodeIntlv 5 /* Node Memory interleaving was enabled*/ -#define GSB_SpIntRemapHole 16 /* Special condition for Node Interleave and HW remapping*/ -#define GSB_EnDIMMSpareNW 17 /* Indicates that DIMM Spare can be used without a warm reset */ - /* NOTE: This is a local bit used by memory code */ - - -/*=============================================================================== - Local DCT Status structure (a structure for each DCT) -===============================================================================*/ - -struct DCTPersistentStatStruc { - u8 CH_D_DIR_B_DQS[2][4][2][9]; /* [A/B] [DIMM1-4] [R/W] [DQS] */ - /* CHA DIMM0 Byte 0 - 7 and Check Write DQS Delay*/ - /* CHA DIMM0 Byte 0 - 7 and Check Read DQS Delay*/ - /* CHA DIMM1 Byte 0 - 7 and Check Write DQS Delay*/ - /* CHA DIMM1 Byte 0 - 7 and Check Read DQS Delay*/ - /* CHB DIMM0 Byte 0 - 7 and Check Write DQS Delay*/ - /* CHB DIMM0 Byte 0 - 7 and Check Read DQS Delay*/ - /* CHB DIMM1 Byte 0 - 7 and Check Write DQS Delay*/ - /* CHB DIMM1 Byte 0 - 7 and Check Read DQS Delay*/ - u8 CH_D_B_RCVRDLY[2][4][8]; /* [A/B] [DIMM0-3] [DQS] */ - /* CHA DIMM 0 Receiver Enable Delay*/ - /* CHA DIMM 1 Receiver Enable Delay*/ - /* CHA DIMM 2 Receiver Enable Delay*/ - /* CHA DIMM 3 Receiver Enable Delay*/ - - /* CHB DIMM 0 Receiver Enable Delay*/ - /* CHB DIMM 1 Receiver Enable Delay*/ - /* CHB DIMM 2 Receiver Enable Delay*/ - /* CHB DIMM 3 Receiver Enable Delay*/ - u8 CH_D_BC_RCVRDLY[2][4]; - /* CHA DIMM 0 - 4 Check Byte Receiver Enable Delay*/ - /* CHB DIMM 0 - 4 Check Byte Receiver Enable Delay*/ - u16 HostBiosSrvc1; /* Word sized general purpose field for use by host BIOS. Scratch space.*/ - u32 HostBiosSrvc2; /* Dword sized general purpose field for use by host BIOS. Scratch space.*/ -} __packed; - - -struct DCTStatStruc { /* A per Node structure*/ -/* DCTStatStruct_F - start */ - u8 Node_ID; /* Node ID of current controller*/ - uint8_t Internal_Node_ID; /* Internal Node ID of the current controller */ - uint8_t Dual_Node_Package; /* 1 = Dual node package (G34) */ - uint8_t stopDCT; /* Set if the DCT will be stopped */ - u8 ErrCode; /* Current error condition of Node - 0= no error - 1= Variance Error, DCT is running but not in an optimal configuration. - 2= Stop Error, DCT is NOT running - 3= Fatal Error, DCT/MCT initialization has been halted.*/ - u32 ErrStatus; /* Error Status bit Field */ - u32 Status; /* Status bit Field*/ - u8 DIMMAddr[8]; /* SPD address of DIMM controlled by MA0_CS_L[0,1]*/ - /* SPD address of..MB0_CS_L[0,1]*/ - /* SPD address of..MA1_CS_L[0,1]*/ - /* SPD address of..MB1_CS_L[0,1]*/ - /* SPD address of..MA2_CS_L[0,1]*/ - /* SPD address of..MB2_CS_L[0,1]*/ - /* SPD address of..MA3_CS_L[0,1]*/ - /* SPD address of..MB3_CS_L[0,1]*/ - u16 DIMMPresent; /*For each bit n 0..7, 1 = DIMM n is present. - DIMM# Select Signal - 0 MA0_CS_L[0,1] - 1 MB0_CS_L[0,1] - 2 MA1_CS_L[0,1] - 3 MB1_CS_L[0,1] - 4 MA2_CS_L[0,1] - 5 MB2_CS_L[0,1] - 6 MA3_CS_L[0,1] - 7 MB3_CS_L[0,1]*/ - u16 DIMMValid; /* For each bit n 0..7, 1 = DIMM n is valid and is/will be configured*/ - u16 DIMMMismatch; /* For each bit n 0..7, 1 = DIMM n is mismatched, channel B is always considered the mismatch */ - u16 DIMMSPDCSE; /* For each bit n 0..7, 1 = DIMM n SPD checksum error*/ - u16 DimmECCPresent; /* For each bit n 0..7, 1 = DIMM n is ECC capable.*/ - u16 DimmPARPresent; /* For each bit n 0..7, 1 = DIMM n is ADR/CMD Parity capable.*/ - u16 Dimmx4Present; /* For each bit n 0..7, 1 = DIMM n contains x4 data devices.*/ - u16 Dimmx8Present; /* For each bit n 0..7, 1 = DIMM n contains x8 data devices.*/ - u16 Dimmx16Present; /* For each bit n 0..7, 1 = DIMM n contains x16 data devices.*/ - u16 DIMM2Kpage; /* For each bit n 0..7, 1 = DIMM n contains 1K page devices.*/ - u8 MAload[2]; /* Number of devices loading MAA bus*/ - /* Number of devices loading MAB bus*/ - u8 MAdimms[2]; /*Number of DIMMs loading CH A*/ - /* Number of DIMMs loading CH B*/ - u8 DATAload[2]; /*Number of ranks loading CH A DATA*/ - /* Number of ranks loading CH B DATA*/ - u8 DIMMAutoSpeed; /*Max valid Mfg. Speed of DIMMs - 1 = 200MHz - 2 = 266MHz - 3 = 333MHz - 4 = 400MHz - 5 = 533MHz*/ - u8 DIMMCASL; /* Min valid Mfg. CL bitfield - 0 = 2.0 - 1 = 3.0 - 2 = 4.0 - 3 = 5.0 - 4 = 6.0 */ - u16 DIMMTrcd; /* Minimax Trcd*40 (ns) of DIMMs*/ - u16 DIMMTrp; /* Minimax Trp*40 (ns) of DIMMs*/ - u16 DIMMTrtp; /* Minimax Trtp*40 (ns) of DIMMs*/ - u16 DIMMTras; /* Minimax Tras*40 (ns) of DIMMs*/ - u16 DIMMTrc; /* Minimax Trc*40 (ns) of DIMMs*/ - u16 DIMMTwr; /* Minimax Twr*40 (ns) of DIMMs*/ - u16 DIMMTrrd; /* Minimax Trrd*40 (ns) of DIMMs*/ - u16 DIMMTwtr; /* Minimax Twtr*40 (ns) of DIMMs*/ - u8 Speed; /* Bus Speed (to set Controller) - 1 = 200MHz - 2 = 266MHz - 3 = 333MHz - 4 = 400MHz */ - u8 CASL; /* CAS latency DCT setting - 0 = 2.0 - 1 = 3.0 - 2 = 4.0 - 3 = 5.0 - 4 = 6.0 */ - u8 Trcd; /* DCT Trcd (busclocks) */ - u8 Trp; /* DCT Trp (busclocks) */ - u8 Trtp; /* DCT Trtp (busclocks) */ - u8 Tras; /* DCT Tras (busclocks) */ - u8 Trc; /* DCT Trc (busclocks) */ - u8 Twr; /* DCT Twr (busclocks) */ - u8 Trrd; /* DCT Trrd (busclocks) */ - u8 Twtr; /* DCT Twtr (busclocks) */ - u8 Trfc[4]; /* DCT Logical DIMM0 Trfc - 0 = 75ns (for 256Mb devs) - 1 = 105ns (for 512Mb devs) - 2 = 127.5ns (for 1Gb devs) - 3 = 195ns (for 2Gb devs) - 4 = 327.5ns (for 4Gb devs) */ - /* DCT Logical DIMM1 Trfc (see Trfc0 for format) */ - /* DCT Logical DIMM2 Trfc (see Trfc0 for format) */ - /* DCT Logical DIMM3 Trfc (see Trfc0 for format) */ - u16 CSPresent; /* For each bit n 0..7, 1 = Chip-select n is present */ - u16 CSTestFail; /* For each bit n 0..7, 1 = Chip-select n is present but disabled */ - u32 DCTSysBase; /* BASE[39:8] (system address) of this Node's DCTs. */ - u32 DCTHoleBase; /* If not zero, BASE[39:8] (system address) of dram hole for HW remapping. Dram hole exists on this Node's DCTs. */ - u32 DCTSysLimit; /* LIMIT[39:8] (system address) of this Node's DCTs */ - u16 PresetmaxFreq; /* Maximum OEM defined DDR frequency - 200 = 200MHz (DDR400) - 266 = 266MHz (DDR533) - 333 = 333MHz (DDR667) - 400 = 400MHz (DDR800) */ - u8 _2Tmode; /* 1T or 2T CMD mode (slow access mode) - 1 = 1T - 2 = 2T */ - u8 TrwtTO; /* DCT TrwtTO (busclocks)*/ - u8 Twrrd; /* DCT Twrrd (busclocks)*/ - u8 Twrwr; /* DCT Twrwr (busclocks)*/ - u8 Trdrd; /* DCT Trdrd (busclocks)*/ - u32 CH_ODC_CTL[2]; /* Output Driver Strength (see BKDG FN2:Offset 9Ch, index 00h*/ - u32 CH_ADDR_TMG[2]; /* Address Bus Timing (see BKDG FN2:Offset 9Ch, index 04h*/ - /* Output Driver Strength (see BKDG FN2:Offset 9Ch, index 20h*/ - /* Address Bus Timing (see BKDG FN2:Offset 9Ch, index 24h*/ - u16 CH_EccDQSLike[2]; /* CHA DQS ECC byte like...*/ - u8 CH_EccDQSScale[2]; /* CHA DQS ECC byte scale*/ - /* CHA DQS ECC byte like...*/ - /* CHA DQS ECC byte scale*/ - u8 MaxAsyncLat; /* Max Asynchronous Latency (ns)*/ - // NOTE: Not used in Barcelona - u8 CH_D_RCVRDLY[2][4]; - /* CHA DIMM 0 - 4 Receiver Enable Delay*/ - /* CHB DIMM 0 - 4 Receiver Enable Delay */ - // NOTE: Not used in Barcelona - u8 CH_D_B_DQS[2][2][8]; - /* CHA Byte 0-7 Write DQS Delay */ - /* CHA Byte 0-7 Read DQS Delay */ - /* CHB Byte 0-7 Write DQS Delay */ - /* CHB Byte 0-7 Read DQS Delay */ - u32 PtrPatternBufA; /* Ptr on stack to aligned DQS testing pattern*/ - u32 PtrPatternBufB; /* Ptr on stack to aligned DQS testing pattern*/ - u8 Channel; /* Current Channel (0= CH A, 1 = CH B)*/ - u8 ByteLane; /* Current Byte Lane (0..7)*/ - u8 Direction; /* Current DQS-DQ training write direction (0 = read, 1 = write)*/ - u8 Pattern; /* Current pattern*/ - u8 DQSDelay; /* Current DQS delay value*/ - u32 TrainErrors; /* Current Training Errors*/ - - u32 AMC_TSC_DeltaLo; /* Time Stamp Counter measurement of AMC, Low dword*/ - u32 AMC_TSC_DeltaHi; /* Time Stamp Counter measurement of AMC, High dword*/ - // NOTE: Not used in Barcelona - u8 CH_D_DIR_MaxMin_B_Dly[2][4][2][2][8]; - /* CH A byte lane 0 - 7 minimum filtered window passing DQS delay value*/ - /* CH A byte lane 0 - 7 maximum filtered window passing DQS delay value*/ - /* CH B byte lane 0 - 7 minimum filtered window passing DQS delay value*/ - /* CH B byte lane 0 - 7 maximum filtered window passing DQS delay value*/ - /* CH A byte lane 0 - 7 minimum filtered window passing DQS delay value*/ - /* CH A byte lane 0 - 7 maximum filtered window passing DQS delay value*/ - /* CH B byte lane 0 - 7 minimum filtered window passing DQS delay value*/ - /* CH B byte lane 0 - 7 maximum filtered window passing DQS delay value*/ - uint64_t LogicalCPUID; /* The logical CPUID of the node*/ - u16 DimmQRPresent; /* QuadRank DIMM present?*/ - u16 DimmTrainFail; /* Bitmap showing which dimms failed training*/ - u16 CSTrainFail; /* Bitmap showing which chipselects failed training*/ - u16 DimmYr06; /* Bitmap indicating which Dimms have a manufactur's year code <= 2006*/ - u16 DimmWk2406; /* Bitmap indicating which Dimms have a manufactur's week code <= 24 of 2006 (June)*/ - u16 DimmDRPresent; /* Bitmap indicating that Dual Rank Dimms are present*/ - u16 DimmPlPresent; /* Bitmap indicating that Planar (1) or Stacked (0) Dimms are present.*/ - u16 ChannelTrainFai; /* Bitmap showing the channel information about failed Chip Selects - 0 in any bit field indicates Channel 0 - 1 in any bit field indicates Channel 1 */ - u16 CSUsrTestFail; /* Chip selects excluded by user */ -/* DCTStatStruct_F - end */ - - u16 CH_MaxRdLat[2]; /* Max Read Latency (ns) for DCT 0*/ - /* Max Read Latency (ns) for DCT 1*/ - u8 DIMMValidDCT[2]; /* DIMM# in DCT0*/ - /* DIMM# in DCT1*/ - u8 MaxDCTs; /* Max number of DCTs in system*/ - // NOTE: removed u8 DCT. Use ->dev_ for pci R/W; /*DCT pointer*/ - u8 GangedMode; /* Ganged mode enabled, 0 = disabled, 1 = enabled*/ - u8 DRPresent; /* Family 10 present flag, 0 = not Fam10, 1 = Fam10*/ - u32 NodeSysLimit; /* BASE[39:8],for DCT0+DCT1 system address*/ - u8 WrDatGrossH; - u8 DqsRcvEnGrossL; - // NOTE: Not used - u8 NodeSpeed /* Bus Speed (to set Controller) - /* 1 = 200MHz */ - /* 2 = 266MHz */ - /* 3 = 333MHz */ - // NOTE: Not used - u8 NodeCASL /* CAS latency DCT setting - /* 0 = 2.0 */ - /* 1 = 3.0 */ - /* 2 = 4.0 */ - /* 3 = 5.0 */ - /* 4 = 6.0 */ - u8 TrwtWB; - u8 CurrRcvrCHADelay; /* for keep current RcvrEnDly of chA*/ - u16 T1000; /* get the T1000 figure (cycle time (ns)*1K)*/ - u8 DqsRcvEn_Pass; /* for TrainRcvrEn byte lane pass flag*/ - u8 DqsRcvEn_Saved; /* for TrainRcvrEn byte lane saved flag*/ - u8 SeedPass1Remainder; /* for Phy assisted DQS receiver enable training*/ - - /* for second pass - Second pass should never run for Fam10*/ - // NOTE: Not used for Barcelona - u8 CH_D_B_RCVRDLY_1[2][4][8]; /* CHA DIMM 0 Receiver Enable Delay*/ - /* CHA DIMM 1 Receiver Enable Delay*/ - /* CHA DIMM 2 Receiver Enable Delay*/ - /* CHA DIMM 3 Receiver Enable Delay*/ - - /* CHB DIMM 0 Receiver Enable Delay*/ - /* CHB DIMM 1 Receiver Enable Delay*/ - /* CHB DIMM 2 Receiver Enable Delay*/ - /* CHB DIMM 3 Receiver Enable Delay*/ - - u8 ClToNB_flag; /* is used to restore ClLinesToNbDis bit after memory */ - u32 NodeSysBase; /* for channel interleave usage */ - -/* New for LB Support */ - u8 NodePresent; - u32 dev_host; - u32 dev_map; - u32 dev_dct; - u32 dev_nbmisc; - - uint8_t DimmRows[MAX_DIMMS_SUPPORTED]; - uint8_t DimmCols[MAX_DIMMS_SUPPORTED]; - uint8_t DimmRanks[MAX_DIMMS_SUPPORTED]; - uint8_t DimmBanks[MAX_DIMMS_SUPPORTED]; - uint8_t DimmWidth[MAX_DIMMS_SUPPORTED]; - uint8_t DimmRegistered[MAX_DIMMS_SUPPORTED]; - - uint64_t DimmManufacturerID[MAX_DIMMS_SUPPORTED]; - char DimmPartNumber[MAX_DIMMS_SUPPORTED][SPD_PARTN_LENGTH+1]; - uint16_t DimmRevisionNumber[MAX_DIMMS_SUPPORTED]; - uint32_t DimmSerialNumber[MAX_DIMMS_SUPPORTED]; - - /* NOTE: This must remain the last entry in this structure */ - struct DCTPersistentStatStruc persistentData; -} __packed; - -/*=============================================================================== - Local Error Status Codes (DCTStatStruc.ErrCode) -===============================================================================*/ -#define SC_RunningOK 0 -#define SC_VarianceErr 1 /* Running non-optimally*/ -#define SC_StopError 2 /* Not Running*/ -#define SC_FatalErr 3 /* Fatal Error, MCTB has exited immediately*/ - -/*=============================================================================== - Local Error Status (DCTStatStruc.ErrStatus[31:0]) -===============================================================================*/ -#define SB_NoDimms 0 -#define SB_DIMMChkSum 1 -#define SB_DimmMismatchM 2 /* dimm module type(buffer) mismatch*/ -#define SB_DimmMismatchT 3 /* dimm CL/T mismatch*/ -#define SB_DimmMismatchO 4 /* dimm organization mismatch (128-bit)*/ -#define SB_NoTrcTrfc 5 /* SPD missing Trc or Trfc info*/ -#define SB_NoCycTime 6 /* SPD missing byte 23 or 25*/ -#define SB_BkIntDis 7 /* Bank interleave requested but not enabled*/ -#define SB_DramECCDis 8 /* Dram ECC requested but not enabled*/ -#define SB_SpareDis 9 /* Online spare requested but not enabled*/ -#define SB_MinimumMode 10 /* Running in Minimum Mode*/ -#define SB_NORCVREN 11 /* No DQS Receiver Enable pass window found*/ -#define SB_CHA2BRCVREN 12 /* DQS Rcvr En pass window CHA to CH B too large*/ -#define SB_SmallRCVR 13 /* DQS Rcvr En pass window too small (far right of dynamic range)*/ -#define SB_NODQSPOS 14 /* No DQS-DQ passing positions*/ -#define SB_SMALLDQS 15 /* DQS-DQ passing window too small*/ -#define SB_DCBKScrubDis 16 /* DCache scrub requested but not enabled */ - -/*=============================================================================== - Local Configuration Status (DCTStatStruc.Status[31:0]) -===============================================================================*/ -#define SB_Registered 0 /* All DIMMs are Registered*/ -#define SB_ECCDIMMs 1 /* All banks ECC capable*/ -#define SB_PARDIMMs 2 /* All banks Addr/CMD Parity capable*/ -#define SB_DiagClks 3 /* Jedec ALL slots clock enable diag mode*/ -#define SB_128bitmode 4 /* DCT in 128-bit mode operation*/ -#define SB_64MuxedMode 5 /* DCT in 64-bit mux'ed mode.*/ -#define SB_2TMode 6 /* 2T CMD timing mode is enabled.*/ -#define SB_SWNodeHole 7 /* Remapping of Node Base on this Node to create a gap.*/ -#define SB_HWHole 8 /* Memory Hole created on this Node using HW remapping.*/ -#define SB_Over400MHz 9 /* DCT freq >= 400MHz flag*/ -#define SB_DQSPos_Pass2 10 /* Using for TrainDQSPos DIMM0/1, when freq >= 400MHz*/ -#define SB_DQSRcvLimit 11 /* Using for DQSRcvEnTrain to know we have reached to upper bound.*/ -#define SB_ExtConfig 12 /* Indicator the default setting for extend PCI configuration support*/ - - - - -/*=============================================================================== - NVRAM/run-time-configurable Items -===============================================================================*/ -/*Platform Configuration*/ -#define NV_PACK_TYPE 0 /* CPU Package Type (2-bits) - 0 = NPT L1 - 1 = NPT M2 - 2 = NPT S1*/ -#define NV_MAX_NODES 1 /* Number of Nodes/Sockets (4-bits)*/ -#define NV_MAX_DIMMS 2 /* Number of DIMM slots for the specified Node ID (4-bits)*/ -#define NV_MAX_MEMCLK 3 /* Maximum platform demonstrated Memclock (10-bits) - 200 = 200MHz (DDR400) - 266 = 266MHz (DDR533) - 333 = 333MHz (DDR667) - 400 = 400MHz (DDR800)*/ -#define NV_MIN_MEMCLK 4 /* Minimum platform demonstrated Memclock (10-bits) */ -#define NV_ECC_CAP 5 /* Bus ECC capable (1-bits) - 0 = Platform not capable - 1 = Platform is capable*/ -#define NV_4RANKType 6 /* Quad Rank DIMM slot type (2-bits) - 0 = Normal - 1 = R4 (4-Rank Registered DIMMs in AMD server configuration) - 2 = S4 (Unbuffered SO-DIMMs)*/ -#define NV_BYPMAX 7 /* Value to set DcqBypassMax field (See Function 2, Offset 94h, [27:24] of BKDG for field definition). - 4 = 4 times bypass (normal for non-UMA systems) - 7 = 7 times bypass (normal for UMA systems)*/ -#define NV_RDWRQBYP 8 /* Value to set RdWrQByp field (See Function 2, Offset A0h, [3:2] of BKDG for field definition). - 2 = 8 times (normal for non-UMA systems) - 3 = 16 times (normal for UMA systems)*/ - - -/*Dram Timing*/ -#define NV_MCTUSRTMGMODE 10 /* User Memclock Mode (2-bits) - 0 = Auto, no user limit - 1 = Auto, user limit provided in NV_MemCkVal - 2 = Manual, user value provided in NV_MemCkVal*/ -#define NV_MemCkVal 11 /* Memory Clock Value (2-bits) - 0 = 200MHz - 1 = 266MHz - 2 = 333MHz - 3 = 400MHz*/ - -/*Dram Configuration*/ -#define NV_BankIntlv 20 /* Dram Bank (chip-select) Interleaving (1-bits) - 0 = disable - 1 = enable*/ -#define NV_AllMemClks 21 /* Turn on All DIMM clocks (1-bits) - 0 = normal - 1 = enable all memclocks*/ -#define NV_SPDCHK_RESTRT 22 /* SPD Check control bitmap (1-bits) - 0 = Exit current node init if any DIMM has SPD checksum error - 1 = Ignore faulty SPD checksums (Note: DIMM cannot be enabled)*/ -#define NV_DQSTrainCTL 23 /* DQS Signal Timing Training Control - 0 = skip DQS training - 1 = perform DQS training*/ -#define NV_NodeIntlv 24 /* Node Memory Interleaving (1-bits) - 0 = disable - 1 = enable*/ -#define NV_BurstLen32 25 /* BurstLength32 for 64-bit mode (1-bits) - 0 = disable (normal) - 1 = enable (4 beat burst when width is 64-bits)*/ - -/*Dram Power*/ -#define NV_CKE_PDEN 30 /* CKE based power down mode (1-bits) - 0 = disable - 1 = enable*/ -#define NV_CKE_CTL 31 /* CKE based power down control (1-bits) - 0 = per Channel control - 1 = per Chip select control*/ -#define NV_CLKHZAltVidC3 32 /* Memclock tri-stating during C3 and Alt VID (1-bits) - 0 = disable - 1 = enable*/ - -/*Memory Map/Mgt.*/ -#define NV_BottomIO 40 /* Bottom of 32-bit IO space (8-bits) - NV_BottomIO[7:0]=Addr[31:24]*/ -#define NV_BottomUMA 41 /* Bottom of shared graphics dram (8-bits) - NV_BottomUMA[7:0]=Addr[31:24]*/ -#define NV_MemHole 42 /* Memory Hole Remapping (1-bits) - 0 = disable - 1 = enable */ - -/*ECC*/ -#define NV_ECC 50 /* Dram ECC enable*/ -#define NV_NBECC 52 /* ECC MCE enable*/ -#define NV_ChipKill 53 /* Chip-Kill ECC Mode enable*/ -#define NV_ECCRedir 54 /* Dram ECC Redirection enable*/ -#define NV_DramBKScrub 55 /* Dram ECC Background Scrubber CTL*/ -#define NV_L2BKScrub 56 /* L2 ECC Background Scrubber CTL*/ -#define NV_L3BKScrub 57 /* L3 ECC Background Scrubber CTL*/ -#define NV_DCBKScrub 58 /* DCache ECC Background Scrubber CTL*/ -#define NV_CS_SpareCTL 59 /* Chip Select Spare Control bit 0: - 0 = disable Spare - 1 = enable Spare */ - /* Chip Select Spare Control bit 1-4: - Reserved, must be zero*/ -#define NV_SyncOnUnEccEn 61 /* SyncOnUnEccEn control - 0 = disable - 1 = enable*/ -#define NV_Unganged 62 - -#define NV_ChannelIntlv 63 /* Channel Interleaving (3-bits) - xx0b = disable - yy1b = enable with DctSelIntLvAddr set to yyb */ - -#define NV_MAX_DIMMS_PER_CH 64 /* Maximum number of DIMMs per channel */ - -#include - -/*=============================================================================== - CBMEM storage -===============================================================================*/ -struct amdmct_memory_info { - struct MCTStatStruc mct_stat; - struct DCTStatStruc dct_stat[MAX_NODES_SUPPORTED]; - uint16_t ecc_enabled; - uint16_t ecc_scrub_rate; -} __packed; - -u32 Get_NB32(u32 dev, u32 reg); -void Set_NB32(u32 dev, u32 reg, u32 val); -u32 Get_NB32_index(u32 dev, u32 index_reg, u32 index); -void Set_NB32_index(u32 dev, u32 index_reg, u32 index, u32 data); -u32 Get_NB32_index_wait(u32 dev, u32 index_reg, u32 index); -void Set_NB32_index_wait(u32 dev, u32 index_reg, u32 index, u32 data); -u32 OtherTiming_A_D(struct DCTStatStruc *pDCTstat, u32 val); -void mct_ForceAutoPrecharge_D(struct DCTStatStruc *pDCTstat, u32 dct); -u32 Modify_D3CMP(struct DCTStatStruc *pDCTstat, u32 dct, u32 value); -u8 mct_checkNumberOfDqsRcvEn_1Pass(u8 pass); -u32 SetupDqsPattern_1PassA(u8 Pass); -u32 SetupDqsPattern_1PassB(u8 Pass); -u8 mct_Get_Start_RcvrEnDly_1Pass(u8 Pass); -u8 mct_Average_RcvrEnDly_Pass(struct DCTStatStruc *pDCTstat, u8 RcvrEnDly, u8 RcvrEnDlyLimit, u8 Channel, u8 Receiver, u8 Pass); -void CPUMemTyping_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstatA); -void UMAMemTyping_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstatA); -uint64_t mctGetLogicalCPUID(u32 Node); -u8 ECCInit_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstatA); -void TrainReceiverEn_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstatA, u8 Pass); -void mct_TrainDQSPos_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstatA); -void mctSetEccDQSRcvrEn_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstatA); -void TrainMaxReadLatency_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstatA); -void mct_EndDQSTraining_D(struct MCTStatStruc *pMCTstat,struct DCTStatStruc *pDCTstatA); -void mct_SetRcvrEnDly_D(struct DCTStatStruc *pDCTstat, u8 RcvrEnDly, u8 FinalValue, u8 Channel, u8 Receiver, u32 dev, u32 index_reg, u8 Addl_Index, u8 Pass); -void SetEccDQSRcvrEn_D(struct DCTStatStruc *pDCTstat, u8 Channel); -void mctGet_PS_Cfg_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstat, u32 dct); -void InterleaveBanks_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstat, u8 dct); -void mct_SetDramConfigHi_D(struct DCTStatStruc *pDCTstat, u32 dct, u32 DramConfigHi); -void mct_DramInit_Hw_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstat, u8 dct); -void SyncSetting(struct DCTStatStruc *pDCTstat); -void mct_SetClToNB_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstat); -void mct_SetWbEnhWsbDis_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstat); -void mct_TrainRcvrEn_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstat, u8 Pass); -void mct_EnableDimmEccEn_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstat, u8 _DisableDramECC); -u32 procOdtWorkaround(struct DCTStatStruc *pDCTstat, u32 dct, u32 val); -void mct_BeforeDramInit_D(struct DCTStatStruc *pDCTstat, u32 dct); -void InterleaveNodes_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstatA); -void InterleaveChannels_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstatA); -void mct_BeforeDQSTrain_Samp_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstat); -void StoreDQSDatStrucVal_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstat, u8 ChipSel); -void phyAssistedMemFnceTraining(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstatA); -u8 mct_SaveRcvEnDly_D_1Pass(struct DCTStatStruc *pDCTstat, u8 pass); -u32 CheckNBCOFAutoPrechg(struct DCTStatStruc *pDCTstat, u32 dct); -u8 mct_AdjustDQSPosDelay_D(struct DCTStatStruc *pDCTstat, u8 dly); -void mct_AdjustScrub_D(struct DCTStatStruc *pDCTstat, u16 *scrub_request); -u8 mct_InitReceiver_D(struct DCTStatStruc *pDCTstat, u8 dct); -void mct_Wait(u32 cycles); -u8 mct_RcvrRankEnabled_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstat, u8 Channel, u8 ChipSel); -u32 mct_GetRcvrSysAddr_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstat, u8 channel, u8 receiver, u8 *valid); -void mct_Read1LTestPattern_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstat, u32 addr); -void EarlySampleSupport_D(void); - -void mctAutoInitMCT_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstatA); -void mct_AdjustDelayRange_D(struct MCTStatStruc *pMCTstat, - struct DCTStatStruc *pDCTstat, u8 *dqs_pos); -void mct_EnableDatIntlv_D(struct MCTStatStruc *pMCTstat, - struct DCTStatStruc *pDCTstat); -void MCTMemClrSync_D(struct MCTStatStruc *pMCTstat, - struct DCTStatStruc *pDCTstatA); -void beforeInterleaveChannels_D(struct DCTStatStruc *pDCTstatA, u8 *enabled); -u8 mct_checkFenceHoleAdjust_D(struct MCTStatStruc *pMCTstat, - struct DCTStatStruc *pDCTstat, u8 DQSDelay, - u8 ChipSel, u8 *result); -void proc_IOCLFLUSH_D(u32 addr_hi); -void mct_Write1LTestPattern_D(struct MCTStatStruc *pMCTstat, - struct DCTStatStruc *pDCTstat, - u32 TestAddr, u8 pattern); -u8 NodePresent_D(u8 Node); -void DCTMemClr_Init_D(struct MCTStatStruc *pMCTstat, - struct DCTStatStruc *pDCTstat); -void MCTMemClr_D(struct MCTStatStruc *pMCTstat, - struct DCTStatStruc *pDCTstatA); -void print_debug_dqs(const char *str, u32 val, u8 level); -void print_debug_dqs_pair(const char *str, u32 val, const char *str2, u32 val2, u8 level); -u8 mct_DisableDimmEccEn_D(struct MCTStatStruc *pMCTstat, - struct DCTStatStruc *pDCTstat); -void ResetDCTWrPtr_D(u32 dev, u32 index_reg, u32 index); -void SetTargetWTIO_D(u32 TestAddr); -void ResetTargetWTIO_D(void); -u32 mct_GetMCTSysAddr_D(struct MCTStatStruc *pMCTstat, - struct DCTStatStruc *pDCTstat, u8 Channel, - u8 receiver, u8 *valid); -#endif diff --git a/src/northbridge/amd/amdmct/mct/mct_d_gcc.c b/src/northbridge/amd/amdmct/mct/mct_d_gcc.c deleted file mode 100644 index d826fed96d..0000000000 --- a/src/northbridge/amd/amdmct/mct/mct_d_gcc.c +++ /dev/null @@ -1,351 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include "mct_d_gcc.h" - -inline void _WRMSR(u32 addr, u32 lo, u32 hi) -{ - __asm__ volatile ( - "wrmsr" - : - :"c"(addr),"a"(lo), "d" (hi) - ); -} - - -inline void _RDMSR(u32 addr, u32 *lo, u32 *hi) -{ - __asm__ volatile ( - "rdmsr" - :"=a"(*lo), "=d" (*hi) - :"c"(addr) - ); -} - - -inline void _RDTSC(u32 *lo, u32 *hi) -{ - __asm__ volatile ( - "rdtsc" - : "=a" (*lo), "=d"(*hi) - ); -} - - -inline void _cpu_id(u32 addr, u32 *val) -{ - __asm__ volatile( - "cpuid" - : "=a" (val[0]), - "=b" (val[1]), - "=c" (val[2]), - "=d" (val[3]) - : "0" (addr)); - -} - - -u32 bsr(u32 x) -{ - u8 i; - u32 ret = 0; - - for (i = 31; i > 0; i--) { - if (x & (1< - -void proc_CLFLUSH(u32 addr_hi) -{ - SetUpperFSbase(addr_hi); - - __asm__ volatile ( - /* clflush fs:[eax] */ - "outb %%al, $0xed\n\t" /* _EXECFENCE */ - "clflush %%fs:(%0)\n\t" - "mfence\n\t" - ::"a" (addr_hi<<8) - ); -} - - -void WriteLNTestPattern(u32 addr_lo, u8 *buf_a, u32 line_num) -{ - __asm__ volatile ( - /*prevent speculative execution of following instructions*/ - /* FIXME: needed ? */ - "outb %%al, $0xed\n\t" /* _EXECFENCE */ - "1:\n\t" - "movdqa (%3), %%xmm0\n\t" - "movntdq %%xmm0, %%fs:(%0)\n\t" /* xmm0 is 128 bit */ - "addl %1, %0\n\t" - "addl %1, %3\n\t" - "loop 1b\n\t" - "mfence\n\t" - - :: "a" (addr_lo), "d" (16), "c" (line_num * 4), "b"(buf_a) - ); - -} - - -u32 read32_fs(u32 addr_lo) -{ - u32 value; - __asm__ volatile ( - "outb %%al, $0xed\n\t" /* _EXECFENCE */ - "movl %%fs:(%1), %0\n\t" - :"=b"(value): "a" (addr_lo) - ); - return value; -} - -#ifdef UNUSED_CODE -static u8 read8_fs(u32 addr_lo) -{ - u8 byte; - __asm__ volatile ( - "outb %%al, $0xed\n\t" /* _EXECFENCE */ - "movb %%fs:(%1), %b0\n\t" - "mfence\n\t" - :"=b"(byte): "a" (addr_lo) - ); - return byte; -} -#endif - -void FlushDQSTestPattern_L9(u32 addr_lo) -{ - __asm__ volatile ( - "outb %%al, $0xed\n\t" /* _EXECFENCE */ - "clflush %%fs:-128(%%ecx)\n\t" - "clflush %%fs:-64(%%ecx)\n\t" - "clflush %%fs:(%%ecx)\n\t" - "clflush %%fs:64(%%ecx)\n\t" - - "clflush %%fs:-128(%%eax)\n\t" - "clflush %%fs:-64(%%eax)\n\t" - "clflush %%fs:(%%eax)\n\t" - "clflush %%fs:64(%%eax)\n\t" - - "clflush %%fs:-128(%%ebx)\n\t" - - :: "b" (addr_lo+128+8*64), "c"(addr_lo+128), - "a"(addr_lo+128+4*64) - ); - -} - - -__attribute__((noinline)) void FlushDQSTestPattern_L18(u32 addr_lo) -{ - __asm__ volatile ( - "outb %%al, $0xed\n\t" /* _EXECFENCE */ - "clflush %%fs:-128(%%eax)\n\t" - "clflush %%fs:-64(%%eax)\n\t" - "clflush %%fs:(%%eax)\n\t" - "clflush %%fs:64(%%eax)\n\t" - - "clflush %%fs:-128(%%edi)\n\t" - "clflush %%fs:-64(%%edi)\n\t" - "clflush %%fs:(%%edi)\n\t" - "clflush %%fs:64(%%edi)\n\t" - - "clflush %%fs:-128(%%ebx)\n\t" - "clflush %%fs:-64(%%ebx)\n\t" - "clflush %%fs:(%%ebx)\n\t" - "clflush %%fs:64(%%ebx)\n\t" - - "clflush %%fs:-128(%%ecx)\n\t" - "clflush %%fs:-64(%%ecx)\n\t" - "clflush %%fs:(%%ecx)\n\t" - "clflush %%fs:64(%%ecx)\n\t" - - "clflush %%fs:-128(%%edx)\n\t" - "clflush %%fs:-64(%%edx)\n\t" - - :: "b" (addr_lo+128+8*64), "c" (addr_lo+128+12*64), - "d" (addr_lo +128+16*64), "a"(addr_lo+128), - "D"(addr_lo+128+4*64) - ); -} - -void ReadL18TestPattern(u32 addr_lo) -{ - // set fs and use fs prefix to access the mem - __asm__ volatile ( - "outb %%al, $0xed\n\t" /* _EXECFENCE */ - "movl %%fs:-128(%%esi), %%eax\n\t" //TestAddr cache line - "movl %%fs:-64(%%esi), %%eax\n\t" //+1 - "movl %%fs:(%%esi), %%eax\n\t" //+2 - "movl %%fs:64(%%esi), %%eax\n\t" //+3 - - "movl %%fs:-128(%%edi), %%eax\n\t" //+4 - "movl %%fs:-64(%%edi), %%eax\n\t" //+5 - "movl %%fs:(%%edi), %%eax\n\t" //+6 - "movl %%fs:64(%%edi), %%eax\n\t" //+7 - - "movl %%fs:-128(%%ebx), %%eax\n\t" //+8 - "movl %%fs:-64(%%ebx), %%eax\n\t" //+9 - "movl %%fs:(%%ebx), %%eax\n\t" //+10 - "movl %%fs:64(%%ebx), %%eax\n\t" //+11 - - "movl %%fs:-128(%%ecx), %%eax\n\t" //+12 - "movl %%fs:-64(%%ecx), %%eax\n\t" //+13 - "movl %%fs:(%%ecx), %%eax\n\t" //+14 - "movl %%fs:64(%%ecx), %%eax\n\t" //+15 - - "movl %%fs:-128(%%edx), %%eax\n\t" //+16 - "movl %%fs:-64(%%edx), %%eax\n\t" //+17 - "mfence\n\t" - - :: "a"(0), "b" (addr_lo+128+8*64), "c" (addr_lo+128+12*64), - "d" (addr_lo +128+16*64), "S"(addr_lo+128), - "D"(addr_lo+128+4*64) - ); - -} - -void ReadL9TestPattern(u32 addr_lo) -{ - - // set fs and use fs prefix to access the mem - __asm__ volatile ( - "outb %%al, $0xed\n\t" /* _EXECFENCE */ - - "movl %%fs:-128(%%ecx), %%eax\n\t" //TestAddr cache line - "movl %%fs:-64(%%ecx), %%eax\n\t" //+1 - "movl %%fs:(%%ecx), %%eax\n\t" //+2 - "movl %%fs:64(%%ecx), %%eax\n\t" //+3 - - "movl %%fs:-128(%%edx), %%eax\n\t" //+4 - "movl %%fs:-64(%%edx), %%eax\n\t" //+5 - "movl %%fs:(%%edx), %%eax\n\t" //+6 - "movl %%fs:64(%%edx), %%eax\n\t" //+7 - - "movl %%fs:-128(%%ebx), %%eax\n\t" //+8 - "mfence\n\t" - - :: "a"(0), "b" (addr_lo+128+8*64), "c"(addr_lo+128), - "d"(addr_lo+128+4*64) - ); - -} - -void ReadMaxRdLat1CLTestPattern_D(u32 addr) -{ - SetUpperFSbase(addr); - - __asm__ volatile ( - "outb %%al, $0xed\n\t" /* _EXECFENCE */ - "movl %%fs:-128(%%esi), %%eax\n\t" //TestAddr cache line - "movl %%fs:-64(%%esi), %%eax\n\t" //+1 - "movl %%fs:(%%esi), %%eax\n\t" //+2 - "mfence\n\t" - :: "a"(0), "S"((addr<<8)+128) - ); - -} - -void WriteMaxRdLat1CLTestPattern_D(u32 buf, u32 addr) -{ - SetUpperFSbase(addr); - - __asm__ volatile ( - "outb %%al, $0xed\n\t" /* _EXECFENCE */ - "1:\n\t" - "movdqa (%3), %%xmm0\n\t" - "movntdq %%xmm0, %%fs:(%0)\n\t" /* xmm0 is 128 bit */ - "addl %1, %0\n\t" - "addl %1, %3\n\t" - "loop 1b\n\t" - "mfence\n\t" - - :: "a" (addr<<8), "d" (16), "c" (3 * 4), "b"(buf) - ); -} - -void FlushMaxRdLatTestPattern_D(u32 addr) -{ - /* Flush a pattern of 72 bit times (per DQ) from cache. - * This procedure is used to ensure cache miss on the next read training. - */ - - SetUpperFSbase(addr); - - __asm__ volatile ( - "outb %%al, $0xed\n\t" /* _EXECFENCE */ - "clflush %%fs:-128(%%esi)\n\t" //TestAddr cache line - "clflush %%fs:-64(%%esi)\n\t" //+1 - "clflush %%fs:(%%esi)\n\t" //+2 - "mfence\n\t" - - :: "S"((addr<<8)+128) - ); -} - -u32 stream_to_int(u8 const *p) -{ - int i; - u32 val; - u32 valx; - - val = 0; - - for (i = 3; i >= 0; i--) { - val <<= 8; - valx = *(p+i); - val |= valx; - } - - return val; -} - -u8 oemNodePresent_D(u8 Node, u8 *ret) -{ - *ret = 0; - return 0; -} diff --git a/src/northbridge/amd/amdmct/mct/mct_d_gcc.h b/src/northbridge/amd/amdmct/mct/mct_d_gcc.h deleted file mode 100644 index 993aa21d74..0000000000 --- a/src/northbridge/amd/amdmct/mct/mct_d_gcc.h +++ /dev/null @@ -1,48 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef MCT_D_GCC_H -#define MCT_D_GCC_H - -#include - -void _WRMSR(u32 addr, u32 lo, u32 hi); -void _RDMSR(u32 addr, u32 *lo, u32 *hi); -void _RDTSC(u32 *lo, u32 *hi); -void _cpu_id(u32 addr, u32 *val); -u32 bsr(u32 x); -u32 bsf(u32 x); - -#define _MFENCE asm volatile ("mfence") -#define _SFENCE asm volatile ("sfence") - -/* prevent speculative execution of following instructions */ -#define _EXECFENCE asm volatile ("outb %al, $0xed") - -u32 SetUpperFSbase(u32 addr_hi); -void proc_CLFLUSH(u32 addr_hi); -void WriteLNTestPattern(u32 addr_lo, u8 *buf_a, u32 line_num); -u32 read32_fs(u32 addr_lo); -void FlushDQSTestPattern_L9(u32 addr_lo); -__attribute__((noinline)) void FlushDQSTestPattern_L18(u32 addr_lo); -void ReadL18TestPattern(u32 addr_lo); -void ReadL9TestPattern(u32 addr_lo); -void ReadMaxRdLat1CLTestPattern_D(u32 addr); -void WriteMaxRdLat1CLTestPattern_D(u32 buf, u32 addr); -void FlushMaxRdLatTestPattern_D(u32 addr); -u32 stream_to_int(u8 const *p); -u8 oemNodePresent_D(u8 Node, u8 *ret); - -#endif diff --git a/src/northbridge/amd/amdmct/mct/mctardk3.c b/src/northbridge/amd/amdmct/mct/mctardk3.c deleted file mode 100644 index c36ba8ea7a..0000000000 --- a/src/northbridge/amd/amdmct/mct/mctardk3.c +++ /dev/null @@ -1,179 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include "mct_d.h" - -static void Get_ChannelPS_Cfg0_D(u8 MAAdimms, u8 Speed, u8 MAAload, - u8 DATAAload, u32 *AddrTmgCTL, u32 *ODC_CTL); - - -void mctGet_PS_Cfg_D(struct MCTStatStruc *pMCTstat, - struct DCTStatStruc *pDCTstat, u32 dct) -{ - u16 val, valx; - - print_tx("dct: ", dct); - print_tx("Speed: ", pDCTstat->Speed); - - Get_ChannelPS_Cfg0_D(pDCTstat->MAdimms[dct], pDCTstat->Speed, - pDCTstat->MAload[dct], pDCTstat->DATAload[dct], - &(pDCTstat->CH_ADDR_TMG[dct]), &(pDCTstat->CH_ODC_CTL[dct])); - - - if (pDCTstat->MAdimms[dct] == 1) - pDCTstat->CH_ODC_CTL[dct] |= 0x20000000; /* 75ohms */ - else - pDCTstat->CH_ODC_CTL[dct] |= 0x10000000; /* 150ohms */ - - pDCTstat->_2Tmode = 1; - - /* use byte lane 4 delay for ECC lane */ - pDCTstat->CH_EccDQSLike[0] = 0x0504; - pDCTstat->CH_EccDQSScale[0] = 0; /* 100% byte lane 4 */ - pDCTstat->CH_EccDQSLike[1] = 0x0504; - pDCTstat->CH_EccDQSScale[1] = 0; /* 100% byte lane 4 */ - - - /* - Overrides and/or exceptions - */ - - /* 1) QRx4 needs to adjust CS/ODT setup time */ - // FIXME: Add Ax support? - if (mctGet_NVbits(NV_MAX_DIMMS) == 4) { - if (pDCTstat->DimmQRPresent != 0) { - pDCTstat->CH_ADDR_TMG[dct] &= 0xFF00FFFF; - pDCTstat->CH_ADDR_TMG[dct] |= 0x00000000; - if (pDCTstat->MAdimms[dct] == 4) { - pDCTstat->CH_ADDR_TMG[dct] &= 0xFF00FFFF; - pDCTstat->CH_ADDR_TMG[dct] |= 0x002F0000; - if (pDCTstat->Speed == 3 || pDCTstat->Speed == 4) { - pDCTstat->CH_ADDR_TMG[dct] &= 0xFF00FFFF; - pDCTstat->CH_ADDR_TMG[dct] |= 0x00002F00; - if (pDCTstat->MAdimms[dct] == 4) - pDCTstat->CH_ODC_CTL[dct] = 0x00331222; - } - } - } - } - - - /* 2) DRx4 (R/C-J) @ DDR667 needs to adjust CS/ODT setup time */ - if (pDCTstat->Speed == 3 || pDCTstat->Speed == 4) { - val = pDCTstat->Dimmx4Present; - if (dct == 0) { - val &= 0x55; - } else { - val &= 0xAA; - val >>= 1; - } - val &= pDCTstat->DIMMValid; - if (val) { - //FIXME: skip for Ax - valx = pDCTstat->DimmDRPresent; - if (dct == 0) { - valx &= 0x55; - } else { - valx &= 0xAA; - valx >>= 1; - } - val &= valx; - if (val != 0) { - if (mctGet_NVbits(NV_MAX_DIMMS) == 8 || - pDCTstat->Speed == 3) { - pDCTstat->CH_ADDR_TMG[dct] &= 0xFFFF00FF; - pDCTstat->CH_ADDR_TMG[dct] |= 0x00002F00; - } - } - } - } - - - pDCTstat->CH_ODC_CTL[dct] = procOdtWorkaround(pDCTstat, dct, pDCTstat->CH_ODC_CTL[dct]); - - print_tx("CH_ODC_CTL: ", pDCTstat->CH_ODC_CTL[dct]); - print_tx("CH_ADDR_TMG: ", pDCTstat->CH_ADDR_TMG[dct]); - - -} - - -/*=============================================================================== - * Vendor is responsible for correct settings. - * M2/Unbuffered 4 Slot - AMD Design Guideline. - *=============================================================================== - * #1, BYTE, Speed (DCTStatstruc.Speed) (Secondary Key) - * #2, BYTE, number of Address bus loads on the Channel. (Tershery Key) - * These must be listed in ascending order. - * FFh (0xFE) has special meaning of 'any', and must be listed first for each speed grade. - * #3, DWORD, Address Timing Control Register Value - * #4, DWORD, Output Driver Compensation Control Register Value - * #5, BYTE, Number of DIMMs (Primary Key) - */ -static const u8 Table_ATC_ODC_8D_D[] = { - 0xFE, 0xFF, 0x00, 0x00, 0x00, 0x00, 0x22, 0x12, 0x11, 0x00, 1, - 0xFE, 0xFF, 0x00, 0x00, 0x37, 0x00, 0x22, 0x12, 0x11, 0x00, 2, - 1, 0xFF, 0x00, 0x00, 0x2F, 0x00, 0x22, 0x12, 0x11, 0x00, 3, - 2, 0xFF, 0x00, 0x00, 0x2F, 0x00, 0x22, 0x12, 0x11, 0x00, 3, - 3, 0xFF, 0x2F, 0x00, 0x2F, 0x00, 0x22, 0x12, 0x11, 0x00, 3, - 4, 0xFF, 0x2F, 0x00, 0x2F, 0x00, 0x22, 0x12, 0x33, 0x00, 3, - 1, 0xFF, 0x00, 0x00, 0x2F, 0x00, 0x22, 0x12, 0x11, 0x00, 4, - 2, 0xFF, 0x00, 0x00, 0x2F, 0x00, 0x22, 0x12, 0x11, 0x00, 4, - 3, 0xFF, 0x2F, 0x00, 0x2F, 0x00, 0x22, 0x12, 0x33, 0x00, 4, - 4, 0xFF, 0x2F, 0x00, 0x2F, 0x00, 0x22, 0x12, 0x33, 0x00, 4, - 0xFF -}; - -static const u8 Table_ATC_ODC_4D_D[] = { - 0xFE, 0xFF, 0x00, 0x00, 0x00, 0x00, 0x22, 0x12, 0x11, 0x00, 1, - 0xFE, 0xFF, 0x00, 0x00, 0x37, 0x00, 0x22, 0x12, 0x11, 0x00, 2, - 0xFE, 0xFF, 0x00, 0x00, 0x00, 0x00, 0x22, 0x12, 0x11, 0x00, 3, - 0xFE, 0xFF, 0x00, 0x00, 0x00, 0x00, 0x22, 0x12, 0x11, 0x00, 4, - 0xFF -}; - - -static void Get_ChannelPS_Cfg0_D(u8 MAAdimms, u8 Speed, u8 MAAload, - u8 DATAAload, u32 *AddrTmgCTL, u32 *ODC_CTL) -{ - const u8 *p; - - *AddrTmgCTL = 0; - *ODC_CTL = 0; - - if (mctGet_NVbits(NV_MAX_DIMMS) == 8) { - /* 8 DIMM Table */ - p = Table_ATC_ODC_8D_D; - //FIXME Add Ax support - } else { - /* 4 DIMM Table*/ - p = Table_ATC_ODC_4D_D; - //FIXME Add Ax support - } - - while (*p != 0xFF) { - if ((MAAdimms == *(p+10)) || (*(p+10) == 0xFE)) { - if ((*p == Speed) || (*p == 0xFE)) { - if (MAAload <= *(p+1)) { - *AddrTmgCTL = stream_to_int((u8*)(p+2)); - *ODC_CTL = stream_to_int((u8*)(p+6)); - break; - } - } - } - p+=11; - } -} diff --git a/src/northbridge/amd/amdmct/mct/mctardk4.c b/src/northbridge/amd/amdmct/mct/mctardk4.c deleted file mode 100644 index c700593740..0000000000 --- a/src/northbridge/amd/amdmct/mct/mctardk4.c +++ /dev/null @@ -1,149 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include "mct_d.h" - -static void Get_ChannelPS_Cfg0_D(u8 MAAdimms, u8 Speed, u8 MAAload, - u8 DATAAload, u32 *AddrTmgCTL, u32 *ODC_CTL, - u8 *CMDmode); - - -void mctGet_PS_Cfg_D(struct MCTStatStruc *pMCTstat, - struct DCTStatStruc *pDCTstat, u32 dct) -{ - print_tx("dct: ", dct); - print_tx("Speed: ", pDCTstat->Speed); - - Get_ChannelPS_Cfg0_D(pDCTstat->MAdimms[dct], pDCTstat->Speed, - pDCTstat->MAload[dct], pDCTstat->DATAload[dct], - &(pDCTstat->CH_ADDR_TMG[dct]), &(pDCTstat->CH_ODC_CTL[dct]), - &pDCTstat->_2Tmode); - - if (pDCTstat->MAdimms[dct] == 1) - pDCTstat->CH_ODC_CTL[dct] |= 0x20000000; /* 75ohms */ - else - pDCTstat->CH_ODC_CTL[dct] |= 0x10000000; /* 150ohms */ - - - /* - * Overrides and/or workarounds - */ - pDCTstat->CH_ODC_CTL[dct] = procOdtWorkaround(pDCTstat, dct, pDCTstat->CH_ODC_CTL[dct]); - - print_tx("4 CH_ODC_CTL: ", pDCTstat->CH_ODC_CTL[dct]); - print_tx("4 CH_ADDR_TMG: ", pDCTstat->CH_ADDR_TMG[dct]); -} - -/*============================================================================= - * Vendor is responsible for correct settings. - * M2/Unbuffered 4 Slot - AMD Design Guideline. - *============================================================================= - * #1, BYTE, Speed (DCTStatstruc.Speed) - * #2, BYTE, number of Address bus loads on the Channel. - * These must be listed in ascending order. - * FFh (-1) has special meaning of 'any', and must be listed first for - * each speed grade. - * #3, DWORD, Address Timing Control Register Value - * #4, DWORD, Output Driver Compensation Control Register Value - */ - -static const u8 Table_ATC_ODC_D_Bx[] = { - 1, 0xFF, 0x00, 0x2F, 0x2F, 0x0, 0x22, 0x13, 0x11, 0x0, - 2, 12, 0x00, 0x2F, 0x2F, 0x0, 0x22, 0x13, 0x11, 0x0, - 2, 16, 0x00, 0x2F, 0x00, 0x0, 0x22, 0x13, 0x11, 0x0, - 2, 20, 0x00, 0x2F, 0x38, 0x0, 0x22, 0x13, 0x11, 0x0, - 2, 24, 0x00, 0x2F, 0x37, 0x0, 0x22, 0x13, 0x11, 0x0, - 2, 32, 0x00, 0x2F, 0x34, 0x0, 0x22, 0x13, 0x11, 0x0, - 3, 12, 0x20, 0x22, 0x20, 0x0, 0x22, 0x13, 0x11, 0x0, - 3, 16, 0x20, 0x22, 0x30, 0x0, 0x22, 0x13, 0x11, 0x0, - 3, 20, 0x20, 0x22, 0x2C, 0x0, 0x22, 0x13, 0x11, 0x0, - 3, 24, 0x20, 0x22, 0x2A, 0x0, 0x22, 0x13, 0x11, 0x0, - 3, 32, 0x20, 0x22, 0x2B, 0x0, 0x22, 0x13, 0x11, 0x0, - 4, 0xFF, 0x20, 0x25, 0x20, 0x0, 0x22, 0x33, 0x11, 0x0, - 5, 0xFF, 0x20, 0x20, 0x2F, 0x0, 0x22, 0x32, 0x11, 0x0, - 0xFF -}; - - -static void Get_ChannelPS_Cfg0_D(u8 MAAdimms, u8 Speed, u8 MAAload, - u8 DATAAload, u32 *AddrTmgCTL, u32 *ODC_CTL, - u8 *CMDmode) -{ - u8 const *p; - - *AddrTmgCTL = 0; - *ODC_CTL = 0; - *CMDmode = 1; - - // FIXME: add Ax support - if (MAAdimms == 0) { - *ODC_CTL = 0x00111222; - if (Speed == 3) - *AddrTmgCTL = 0x00202220; - else if (Speed == 2) - *AddrTmgCTL = 0x002F2F00; - else if (Speed == 1) - *AddrTmgCTL = 0x002F2F00; - else if (Speed == 4) - *AddrTmgCTL = 0x00202520; - else if (Speed == 5) - *AddrTmgCTL = 0x002F2020; - else - *AddrTmgCTL = 0x002F2F2F; - } else if (MAAdimms == 1) { - if (Speed == 4) { - *CMDmode = 2; - *AddrTmgCTL = 0x00202520; - *ODC_CTL = 0x00113222; - } else if (Speed == 5) { - *CMDmode = 2; - *AddrTmgCTL = 0x002F2020; - *ODC_CTL = 0x00113222; - } else { - *CMDmode = 1; - *ODC_CTL = 0x00111222; - if (Speed == 3) { - *AddrTmgCTL = 0x00202220; - } else if (Speed == 2) { - if (MAAload == 4) - *AddrTmgCTL = 0x002B2F00; - else if (MAAload == 16) - *AddrTmgCTL = 0x002B2F00; - else if (MAAload == 8) - *AddrTmgCTL = 0x002F2F00; - else - *AddrTmgCTL = 0x002F2F00; - } else if (Speed == 1) { - *AddrTmgCTL = 0x002F2F00; - } else { - *AddrTmgCTL = 0x002F2F2F; - } - } - } else { - *CMDmode = 2; - p = Table_ATC_ODC_D_Bx; - do { - if (Speed == *p) { - if (MAAload <= *(p+1)) { - *AddrTmgCTL = stream_to_int(p+2); - *ODC_CTL = stream_to_int(p+6); - break; - } - } - p+=10; - } while (*p == 0xff); - } -} diff --git a/src/northbridge/amd/amdmct/mct/mctchi_d.c b/src/northbridge/amd/amdmct/mct/mctchi_d.c deleted file mode 100644 index d2acc15118..0000000000 --- a/src/northbridge/amd/amdmct/mct/mctchi_d.c +++ /dev/null @@ -1,125 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007-2008 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include "mct_d.h" - -void InterleaveChannels_D(struct MCTStatStruc *pMCTstat, - struct DCTStatStruc *pDCTstatA) -{ - - u8 Node; - u32 DramBase, DctSelBase; - u8 DctSelIntLvAddr, DctSelHi; - u8 HoleValid = 0; - u32 HoleSize, HoleBase = 0; - u32 val, tmp; - u32 dct0_size, dct1_size; - u8 enabled; - struct DCTStatStruc *pDCTstat; - - /* HoleValid - indicates whether the current Node contains hole. - * HoleSize - indicates whether there is IO hole in the whole system - * memory. - */ - - /* call back to wrapper not needed ManualChannelInterleave_D(); */ - /* call back - DctSelIntLvAddr = mctGet_NVbits(NV_ChannelIntlv);*/ /* override interleave */ - // FIXME: Check for Cx - DctSelIntLvAddr = mctGet_NVbits(NV_ChannelIntlv); /* typ = 5: Hash*: exclusive OR of address bits[20:16, 6]. */ - beforeInterleaveChannels_D(pDCTstatA, &enabled); - - if (DctSelIntLvAddr & 1) { - DctSelIntLvAddr >>= 1; - HoleSize = 0; - if ((pMCTstat->GStatus & (1 << GSB_SoftHole)) || - (pMCTstat->GStatus & (1 << GSB_HWHole))) { - if (pMCTstat->HoleBase) { - HoleBase = pMCTstat->HoleBase >> 8; - HoleSize = HoleBase & 0xFFFF0000; - HoleSize |= ((~HoleBase) + 1) & 0xFFFF; - } - } - Node = 0; - while (Node < MAX_NODES_SUPPORTED) { - pDCTstat = pDCTstatA + Node; - val = Get_NB32(pDCTstat->dev_map, 0xF0); - if (val & (1 << DramHoleValid)) - HoleValid = 1; - if (!pDCTstat->GangedMode && pDCTstat->DIMMValidDCT[0] && pDCTstat->DIMMValidDCT[1]) { - DramBase = pDCTstat->NodeSysBase >> 8; - dct1_size = ((pDCTstat->NodeSysLimit) + 2) >> 8; - dct0_size = Get_NB32(pDCTstat->dev_dct, 0x114); - if (dct0_size >= 0x10000) { - dct0_size -= HoleSize; - } - - dct0_size -= DramBase; - dct1_size -= dct0_size; - DctSelHi = 0x05; /* DctSelHiRngEn = 1, DctSelHi = 0 */ - if (dct1_size == dct0_size) { - dct1_size = 0; - DctSelHi = 0x04; /* DctSelHiRngEn = 0 */ - } else if (dct1_size > dct0_size) { - dct1_size = dct0_size; - DctSelHi = 0x07; /* DctSelHiRngEn = 1, DctSelHi = 1 */ - } - dct0_size = dct1_size; - dct0_size += DramBase; - dct0_size += dct1_size; - if (dct0_size >= HoleBase) /* if DctSelBaseAddr > HoleBase */ - dct0_size += HoleSize; - DctSelBase = dct0_size; - - if (dct1_size == 0) - dct0_size = 0; - dct0_size -= dct1_size; /* DctSelBaseOffset = DctSelBaseAddr - Interleaved region */ - Set_NB32(pDCTstat->dev_dct, 0x114, dct0_size); - - if (dct1_size == 0) - dct1_size = DctSelBase; - val = Get_NB32(pDCTstat->dev_dct, 0x110); - val &= 0x7F8; - val |= dct1_size; - val |= DctSelHi; - val |= (DctSelIntLvAddr << 6) & 0xFF; - Set_NB32(pDCTstat->dev_dct, 0x110, val); - print_tx("InterleaveChannels: F2x110 DRAM Controller Select Low Register = ", val); - - if (HoleValid) { - tmp = DramBase; - val = DctSelBase; - if (val < HoleBase) { /* DctSelBaseAddr < DramHoleBase */ - val -= DramBase; - val >>= 1; - tmp += val; - } - tmp += HoleSize; - val = Get_NB32(pDCTstat->dev_map, 0xF0); /* DramHoleOffset */ - val &= 0xFFFF007F; - val |= (tmp & ~0xFFFF007F); - Set_NB32(pDCTstat->dev_map, 0xF0, val); - print_tx("InterleaveChannels: F1xF0 DRAM Hole Address Register = ", val); - - } - } - print_tx("InterleaveChannels_D: Node ", Node); - print_tx("InterleaveChannels_D: Status ", pDCTstat->Status); - print_tx("InterleaveChannels_D: ErrStatus ", pDCTstat->ErrStatus); - print_tx("InterleaveChannels_D: ErrCode ", pDCTstat->ErrCode); - Node++; - } - } - print_t("InterleaveChannels_D: Done\n"); -} diff --git a/src/northbridge/amd/amdmct/mct/mctcsi_d.c b/src/northbridge/amd/amdmct/mct/mctcsi_d.c deleted file mode 100644 index 6a19788ab3..0000000000 --- a/src/northbridge/amd/amdmct/mct/mctcsi_d.c +++ /dev/null @@ -1,140 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include "mct_d.h" - -/* Low swap bit vs bank size encoding (physical, not logical address bit) - * ;To calculate the number by hand, add the number of Bank address bits - * ;(2 or 3) to the number of column address bits, plus 3 (the logical - * ;page size), and subtract 8. - */ -static const u8 Tab_int_D[] = { 6,7,7,8,8,8,8,8,9,9,8,9 }; - -void InterleaveBanks_D(struct MCTStatStruc *pMCTstat, - struct DCTStatStruc *pDCTstat, u8 dct) -{ - u8 ChipSel, EnChipSels; - u32 AddrLoMask, AddrHiMask; - u32 AddrLoMaskN, AddrHiMaskN, MemSize = 0; - u8 DoIntlv, _CsIntCap; - u32 BitDelta, BankEncd = 0; - - u32 dev; - u32 reg; - u32 reg_off; - u32 val; - u32 val_lo, val_hi; - - DoIntlv = mctGet_NVbits(NV_BankIntlv); - _CsIntCap = 0; - EnChipSels = 0; - - dev = pDCTstat->dev_dct; - reg_off = 0x100 * dct; - - ChipSel = 0; /* Find out if current configuration is capable */ - while (DoIntlv && (ChipSel < MAX_CS_SUPPORTED)) { - reg = 0x40+(ChipSel << 2) + reg_off; /* Dram CS Base 0 */ - val = Get_NB32(dev, reg); - if (val & (1 << CSEnable)) { - EnChipSels++; - reg = 0x60+((ChipSel >> 1) << 2)+reg_off; /*Dram CS Mask 0 */ - val = Get_NB32(dev, reg); - val >>= 19; - val &= 0x3ff; - val++; - if (EnChipSels == 1) - MemSize = val; - else - /*If mask sizes not same then skip */ - if (val != MemSize) - break; - reg = 0x80 + reg_off; /*Dram Bank Addressing */ - val = Get_NB32(dev, reg); - val >>= (ChipSel >> 1) << 2; - val &= 0x0f; - if (EnChipSels == 1) - BankEncd = val; - else - /*If number of Rows/Columns not equal, skip */ - if (val != BankEncd) - break; - } - ChipSel++; - } - if (ChipSel == MAX_CS_SUPPORTED) { - if ((EnChipSels == 2) || (EnChipSels == 4) || (EnChipSels == 8)) - _CsIntCap = 1; - } - - if (DoIntlv) { - if (!_CsIntCap) { - pDCTstat->ErrStatus |= 1 << SB_BkIntDis; - DoIntlv = 0; - } - } - - if (DoIntlv) { - val = Tab_int_D[BankEncd]; - if (pDCTstat->Status & (1 << SB_128bitmode)) - val++; - - AddrLoMask = (EnChipSels - 1) << val; - AddrLoMaskN = ~AddrLoMask; - - val = bsf(MemSize) + 19; - AddrHiMask = (EnChipSels -1) << val; - AddrHiMaskN = ~AddrHiMask; - - BitDelta = bsf(AddrHiMask) - bsf(AddrLoMask); - - for (ChipSel = 0; ChipSel < MAX_CS_SUPPORTED; ChipSel++) { - reg = 0x40+(ChipSel << 2) + reg_off; /*Dram CS Base 0 */ - val = Get_NB32(dev, reg); - if (val & 3) { - val_lo = val & AddrLoMask; - val_hi = val & AddrHiMask; - val &= AddrLoMaskN; - val &= AddrHiMaskN; - val_lo <<= BitDelta; - val_hi >>= BitDelta; - val |= val_lo; - val |= val_hi; - Set_NB32(dev, reg, val); - - if (ChipSel & 1) - continue; - - reg = 0x60 + ((ChipSel >> 1) << 2) + reg_off; /*Dram CS Mask 0 */ - val = Get_NB32(dev, reg); - val_lo = val & AddrLoMask; - val_hi = val & AddrHiMask; - val &= AddrLoMaskN; - val &= AddrHiMaskN; - val_lo <<= BitDelta; - val_hi >>= BitDelta; - val |= val_lo; - val |= val_hi; - Set_NB32(dev, reg, val); - } - } - print_t("InterleaveBanks_D: Banks Interleaved "); - } /* DoIntlv */ - - print_tx("InterleaveBanks_D: Status ", pDCTstat->Status); - print_tx("InterleaveBanks_D: ErrStatus ", pDCTstat->ErrStatus); - print_tx("InterleaveBanks_D: ErrCode ", pDCTstat->ErrCode); - print_t("InterleaveBanks_D: Done\n"); -} diff --git a/src/northbridge/amd/amdmct/mct/mctdqs_d.c b/src/northbridge/amd/amdmct/mct/mctdqs_d.c deleted file mode 100644 index 2e52a39619..0000000000 --- a/src/northbridge/amd/amdmct/mct/mctdqs_d.c +++ /dev/null @@ -1,1207 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007-2008 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include -#include - -#include "mct_d.h" - -static void CalcEccDQSPos_D(struct MCTStatStruc *pMCTstat, - struct DCTStatStruc *pDCTstat, u16 like, - u8 scale, u8 ChipSel); -static void GetDQSDatStrucVal_D(struct MCTStatStruc *pMCTstat, - struct DCTStatStruc *pDCTstat, u8 ChipSel); -static u8 MiddleDQS_D(u8 min, u8 max); -static void TrainReadDQS_D(struct MCTStatStruc *pMCTstat, - struct DCTStatStruc *pDCTstat, - u8 cs_start); -static void TrainWriteDQS_D(struct MCTStatStruc *pMCTstat, - struct DCTStatStruc *pDCTstat, - u8 cs_start); -static void WriteDQSTestPattern_D(struct MCTStatStruc *pMCTstat, - struct DCTStatStruc *pDCTstat, - u32 TestAddr_lo); -static void WriteL18TestPattern_D(struct DCTStatStruc *pDCTstat, - u32 TestAddr_lo); -static void WriteL9TestPattern_D(struct DCTStatStruc *pDCTstat, - u32 TestAddr_lo); -static u8 CompareDQSTestPattern_D(struct MCTStatStruc *pMCTstat, - struct DCTStatStruc *pDCTstat, - u32 addr_lo); -static void FlushDQSTestPattern_D(struct DCTStatStruc *pDCTstat, - u32 addr_lo); -static void ReadDQSTestPattern_D(struct MCTStatStruc *pMCTstat, - struct DCTStatStruc *pDCTstat, - u32 TestAddr_lo); -static void mct_SetDQSDelayCSR_D(struct MCTStatStruc *pMCTstat, - struct DCTStatStruc *pDCTstat, - u8 ChipSel); -static void mct_SetDQSDelayAllCSR_D(struct MCTStatStruc *pMCTstat, - struct DCTStatStruc *pDCTstat, - u8 cs_start); -static void SetupDqsPattern_D(struct MCTStatStruc *pMCTstat, - struct DCTStatStruc *pDCTstat, - u32 *buffer); - -void print_debug_dqs(const char *str, u32 val, u8 level) -{ -#if DQS_TRAIN_DEBUG > 0 - if (DQS_TRAIN_DEBUG >= level) { - printk(BIOS_DEBUG, "%s%x\n", str, val); - } -#endif -} - -void print_debug_dqs_pair(const char *str, u32 val, const char *str2, u32 val2, u8 level) -{ -#if DQS_TRAIN_DEBUG > 0 - if (DQS_TRAIN_DEBUG >= level) { - printk(BIOS_DEBUG, "%s%08x%s%08x\n", str, val, str2, val2); - } -#endif -} - -/*Warning: These must be located so they do not cross a logical 16-bit segment boundary!*/ -static const u32 TestPatternJD1a_D[] = { - 0x00000000,0x00000000,0xFFFFFFFF,0xFFFFFFFF, /* QW0-1, ALL-EVEN */ - 0x00000000,0x00000000,0x00000000,0x00000000, /* QW2-3, ALL-EVEN */ - 0x00000000,0x00000000,0xFFFFFFFF,0xFFFFFFFF, /* QW4-5, ALL-EVEN */ - 0x00000000,0x00000000,0x00000000,0x00000000, /* QW6-7, ALL-EVEN */ - 0xFeFeFeFe,0xFeFeFeFe,0x01010101,0x01010101, /* QW0-1, DQ0-ODD */ - 0xFeFeFeFe,0xFeFeFeFe,0x01010101,0x01010101, /* QW2-3, DQ0-ODD */ - 0x01010101,0x01010101,0xFeFeFeFe,0xFeFeFeFe, /* QW4-5, DQ0-ODD */ - 0xFeFeFeFe,0xFeFeFeFe,0x01010101,0x01010101, /* QW6-7, DQ0-ODD */ - 0x02020202,0x02020202,0x02020202,0x02020202, /* QW0-1, DQ1-ODD */ - 0xFdFdFdFd,0xFdFdFdFd,0xFdFdFdFd,0xFdFdFdFd, /* QW2-3, DQ1-ODD */ - 0xFdFdFdFd,0xFdFdFdFd,0x02020202,0x02020202, /* QW4-5, DQ1-ODD */ - 0x02020202,0x02020202,0x02020202,0x02020202, /* QW6-7, DQ1-ODD */ - 0x04040404,0x04040404,0xfBfBfBfB,0xfBfBfBfB, /* QW0-1, DQ2-ODD */ - 0x04040404,0x04040404,0x04040404,0x04040404, /* QW2-3, DQ2-ODD */ - 0xfBfBfBfB,0xfBfBfBfB,0xfBfBfBfB,0xfBfBfBfB, /* QW4-5, DQ2-ODD */ - 0xfBfBfBfB,0xfBfBfBfB,0xfBfBfBfB,0xfBfBfBfB, /* QW6-7, DQ2-ODD */ - 0x08080808,0x08080808,0xF7F7F7F7,0xF7F7F7F7, /* QW0-1, DQ3-ODD */ - 0x08080808,0x08080808,0x08080808,0x08080808, /* QW2-3, DQ3-ODD */ - 0xF7F7F7F7,0xF7F7F7F7,0x08080808,0x08080808, /* QW4-5, DQ3-ODD */ - 0xF7F7F7F7,0xF7F7F7F7,0xF7F7F7F7,0xF7F7F7F7, /* QW6-7, DQ3-ODD */ - 0x10101010,0x10101010,0x10101010,0x10101010, /* QW0-1, DQ4-ODD */ - 0xeFeFeFeF,0xeFeFeFeF,0x10101010,0x10101010, /* QW2-3, DQ4-ODD */ - 0xeFeFeFeF,0xeFeFeFeF,0xeFeFeFeF,0xeFeFeFeF, /* QW4-5, DQ4-ODD */ - 0xeFeFeFeF,0xeFeFeFeF,0x10101010,0x10101010, /* QW6-7, DQ4-ODD */ - 0xdFdFdFdF,0xdFdFdFdF,0xdFdFdFdF,0xdFdFdFdF, /* QW0-1, DQ5-ODD */ - 0xdFdFdFdF,0xdFdFdFdF,0x20202020,0x20202020, /* QW2-3, DQ5-ODD */ - 0xdFdFdFdF,0xdFdFdFdF,0xdFdFdFdF,0xdFdFdFdF, /* QW4-5, DQ5-ODD */ - 0xdFdFdFdF,0xdFdFdFdF,0xdFdFdFdF,0xdFdFdFdF, /* QW6-7, DQ5-ODD */ - 0xBfBfBfBf,0xBfBfBfBf,0xBfBfBfBf,0xBfBfBfBf, /* QW0-1, DQ6-ODD */ - 0x40404040,0x40404040,0xBfBfBfBf,0xBfBfBfBf, /* QW2-3, DQ6-ODD */ - 0x40404040,0x40404040,0xBfBfBfBf,0xBfBfBfBf, /* QW4-5, DQ6-ODD */ - 0x40404040,0x40404040,0xBfBfBfBf,0xBfBfBfBf, /* QW6-7, DQ6-ODD */ - 0x80808080,0x80808080,0x7F7F7F7F,0x7F7F7F7F, /* QW0-1, DQ7-ODD */ - 0x80808080,0x80808080,0x7F7F7F7F,0x7F7F7F7F, /* QW2-3, DQ7-ODD */ - 0x80808080,0x80808080,0x7F7F7F7F,0x7F7F7F7F, /* QW4-5, DQ7-ODD */ - 0x80808080,0x80808080,0x80808080,0x80808080 /* QW6-7, DQ7-ODD */ -}; -static const u32 TestPatternJD1b_D[] = { - 0x00000000,0x00000000,0x00000000,0x00000000, /* QW0,CHA-B, ALL-EVEN */ - 0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF, /* QW1,CHA-B, ALL-EVEN */ - 0x00000000,0x00000000,0x00000000,0x00000000, /* QW2,CHA-B, ALL-EVEN */ - 0x00000000,0x00000000,0x00000000,0x00000000, /* QW3,CHA-B, ALL-EVEN */ - 0x00000000,0x00000000,0x00000000,0x00000000, /* QW4,CHA-B, ALL-EVEN */ - 0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF, /* QW5,CHA-B, ALL-EVEN */ - 0x00000000,0x00000000,0x00000000,0x00000000, /* QW6,CHA-B, ALL-EVEN */ - 0x00000000,0x00000000,0x00000000,0x00000000, /* QW7,CHA-B, ALL-EVEN */ - 0xFeFeFeFe,0xFeFeFeFe,0xFeFeFeFe,0xFeFeFeFe, /* QW0,CHA-B, DQ0-ODD */ - 0x01010101,0x01010101,0x01010101,0x01010101, /* QW1,CHA-B, DQ0-ODD */ - 0xFeFeFeFe,0xFeFeFeFe,0xFeFeFeFe,0xFeFeFeFe, /* QW2,CHA-B, DQ0-ODD */ - 0x01010101,0x01010101,0x01010101,0x01010101, /* QW3,CHA-B, DQ0-ODD */ - 0x01010101,0x01010101,0x01010101,0x01010101, /* QW4,CHA-B, DQ0-ODD */ - 0xFeFeFeFe,0xFeFeFeFe,0xFeFeFeFe,0xFeFeFeFe, /* QW5,CHA-B, DQ0-ODD */ - 0xFeFeFeFe,0xFeFeFeFe,0xFeFeFeFe,0xFeFeFeFe, /* QW6,CHA-B, DQ0-ODD */ - 0x01010101,0x01010101,0x01010101,0x01010101, /* QW7,CHA-B, DQ0-ODD */ - 0x02020202,0x02020202,0x02020202,0x02020202, /* QW0,CHA-B, DQ1-ODD */ - 0x02020202,0x02020202,0x02020202,0x02020202, /* QW1,CHA-B, DQ1-ODD */ - 0xFdFdFdFd,0xFdFdFdFd,0xFdFdFdFd,0xFdFdFdFd, /* QW2,CHA-B, DQ1-ODD */ - 0xFdFdFdFd,0xFdFdFdFd,0xFdFdFdFd,0xFdFdFdFd, /* QW3,CHA-B, DQ1-ODD */ - 0xFdFdFdFd,0xFdFdFdFd,0xFdFdFdFd,0xFdFdFdFd, /* QW4,CHA-B, DQ1-ODD */ - 0x02020202,0x02020202,0x02020202,0x02020202, /* QW5,CHA-B, DQ1-ODD */ - 0x02020202,0x02020202,0x02020202,0x02020202, /* QW6,CHA-B, DQ1-ODD */ - 0x02020202,0x02020202,0x02020202,0x02020202, /* QW7,CHA-B, DQ1-ODD */ - 0x04040404,0x04040404,0x04040404,0x04040404, /* QW0,CHA-B, DQ2-ODD */ - 0xfBfBfBfB,0xfBfBfBfB,0xfBfBfBfB,0xfBfBfBfB, /* QW1,CHA-B, DQ2-ODD */ - 0x04040404,0x04040404,0x04040404,0x04040404, /* QW2,CHA-B, DQ2-ODD */ - 0x04040404,0x04040404,0x04040404,0x04040404, /* QW3,CHA-B, DQ2-ODD */ - 0xfBfBfBfB,0xfBfBfBfB,0xfBfBfBfB,0xfBfBfBfB, /* QW4,CHA-B, DQ2-ODD */ - 0xfBfBfBfB,0xfBfBfBfB,0xfBfBfBfB,0xfBfBfBfB, /* QW5,CHA-B, DQ2-ODD */ - 0xfBfBfBfB,0xfBfBfBfB,0xfBfBfBfB,0xfBfBfBfB, /* QW6,CHA-B, DQ2-ODD */ - 0xfBfBfBfB,0xfBfBfBfB,0xfBfBfBfB,0xfBfBfBfB, /* QW7,CHA-B, DQ2-ODD */ - 0x08080808,0x08080808,0x08080808,0x08080808, /* QW0,CHA-B, DQ3-ODD */ - 0xF7F7F7F7,0xF7F7F7F7,0xF7F7F7F7,0xF7F7F7F7, /* QW1,CHA-B, DQ3-ODD */ - 0x08080808,0x08080808,0x08080808,0x08080808, /* QW2,CHA-B, DQ3-ODD */ - 0x08080808,0x08080808,0x08080808,0x08080808, /* QW3,CHA-B, DQ3-ODD */ - 0xF7F7F7F7,0xF7F7F7F7,0xF7F7F7F7,0xF7F7F7F7, /* QW4,CHA-B, DQ3-ODD */ - 0x08080808,0x08080808,0x08080808,0x08080808, /* QW5,CHA-B, DQ3-ODD */ - 0xF7F7F7F7,0xF7F7F7F7,0xF7F7F7F7,0xF7F7F7F7, /* QW6,CHA-B, DQ3-ODD */ - 0xF7F7F7F7,0xF7F7F7F7,0xF7F7F7F7,0xF7F7F7F7, /* QW7,CHA-B, DQ3-ODD */ - 0x10101010,0x10101010,0x10101010,0x10101010, /* QW0,CHA-B, DQ4-ODD */ - 0x10101010,0x10101010,0x10101010,0x10101010, /* QW1,CHA-B, DQ4-ODD */ - 0xeFeFeFeF,0xeFeFeFeF,0xeFeFeFeF,0xeFeFeFeF, /* QW2,CHA-B, DQ4-ODD */ - 0x10101010,0x10101010,0x10101010,0x10101010, /* QW3,CHA-B, DQ4-ODD */ - 0xeFeFeFeF,0xeFeFeFeF,0xeFeFeFeF,0xeFeFeFeF, /* QW4,CHA-B, DQ4-ODD */ - 0xeFeFeFeF,0xeFeFeFeF,0xeFeFeFeF,0xeFeFeFeF, /* QW5,CHA-B, DQ4-ODD */ - 0xeFeFeFeF,0xeFeFeFeF,0xeFeFeFeF,0xeFeFeFeF, /* QW6,CHA-B, DQ4-ODD */ - 0x10101010,0x10101010,0x10101010,0x10101010, /* QW7,CHA-B, DQ4-ODD */ - 0xdFdFdFdF,0xdFdFdFdF,0xdFdFdFdF,0xdFdFdFdF, /* QW0,CHA-B, DQ5-ODD */ - 0xdFdFdFdF,0xdFdFdFdF,0xdFdFdFdF,0xdFdFdFdF, /* QW1,CHA-B, DQ5-ODD */ - 0xdFdFdFdF,0xdFdFdFdF,0xdFdFdFdF,0xdFdFdFdF, /* QW2,CHA-B, DQ5-ODD */ - 0x20202020,0x20202020,0x20202020,0x20202020, /* QW3,CHA-B, DQ5-ODD */ - 0xdFdFdFdF,0xdFdFdFdF,0xdFdFdFdF,0xdFdFdFdF, /* QW4,CHA-B, DQ5-ODD */ - 0xdFdFdFdF,0xdFdFdFdF,0xdFdFdFdF,0xdFdFdFdF, /* QW5,CHA-B, DQ5-ODD */ - 0xdFdFdFdF,0xdFdFdFdF,0xdFdFdFdF,0xdFdFdFdF, /* QW6,CHA-B, DQ5-ODD */ - 0xdFdFdFdF,0xdFdFdFdF,0xdFdFdFdF,0xdFdFdFdF, /* QW7,CHA-B, DQ5-ODD */ - 0xBfBfBfBf,0xBfBfBfBf,0xBfBfBfBf,0xBfBfBfBf, /* QW0,CHA-B, DQ6-ODD */ - 0xBfBfBfBf,0xBfBfBfBf,0xBfBfBfBf,0xBfBfBfBf, /* QW1,CHA-B, DQ6-ODD */ - 0x40404040,0x40404040,0x40404040,0x40404040, /* QW2,CHA-B, DQ6-ODD */ - 0xBfBfBfBf,0xBfBfBfBf,0xBfBfBfBf,0xBfBfBfBf, /* QW3,CHA-B, DQ6-ODD */ - 0x40404040,0x40404040,0x40404040,0x40404040, /* QW4,CHA-B, DQ6-ODD */ - 0xBfBfBfBf,0xBfBfBfBf,0xBfBfBfBf,0xBfBfBfBf, /* QW5,CHA-B, DQ6-ODD */ - 0x40404040,0x40404040,0x40404040,0x40404040, /* QW6,CHA-B, DQ6-ODD */ - 0xBfBfBfBf,0xBfBfBfBf,0xBfBfBfBf,0xBfBfBfBf, /* QW7,CHA-B, DQ6-ODD */ - 0x80808080,0x80808080,0x80808080,0x80808080, /* QW0,CHA-B, DQ7-ODD */ - 0x7F7F7F7F,0x7F7F7F7F,0x7F7F7F7F,0x7F7F7F7F, /* QW1,CHA-B, DQ7-ODD */ - 0x80808080,0x80808080,0x80808080,0x80808080, /* QW2,CHA-B, DQ7-ODD */ - 0x7F7F7F7F,0x7F7F7F7F,0x7F7F7F7F,0x7F7F7F7F, /* QW3,CHA-B, DQ7-ODD */ - 0x80808080,0x80808080,0x80808080,0x80808080, /* QW4,CHA-B, DQ7-ODD */ - 0x7F7F7F7F,0x7F7F7F7F,0x7F7F7F7F,0x7F7F7F7F, /* QW5,CHA-B, DQ7-ODD */ - 0x80808080,0x80808080,0x80808080,0x80808080, /* QW6,CHA-B, DQ7-ODD */ - 0x80808080,0x80808080,0x80808080,0x80808080 /* QW7,CHA-B, DQ7-ODD */ -}; - -void TrainReceiverEn_D(struct MCTStatStruc *pMCTstat, - struct DCTStatStruc *pDCTstatA, u8 Pass) -{ - u8 Node; - struct DCTStatStruc *pDCTstat; - - for (Node = 0; Node < MAX_NODES_SUPPORTED; Node++) { - pDCTstat = pDCTstatA + Node; - -/*FIXME: needed? if (!pDCTstat->NodePresent) - break; -*/ - if (pDCTstat->DCTSysLimit) { - mct_TrainRcvrEn_D(pMCTstat, pDCTstat, Pass); - } - } -} - - -static void SetEccDQSRdWrPos_D(struct MCTStatStruc *pMCTstat, - struct DCTStatStruc *pDCTstat, u8 ChipSel) -{ - u8 channel; - u8 direction; - - for (channel = 0; channel < 2; channel++) { - for (direction = 0; direction < 2; direction++) { - pDCTstat->Channel = channel; /* Channel A or B */ - pDCTstat->Direction = direction; /* Read or write */ - CalcEccDQSPos_D(pMCTstat, pDCTstat, pDCTstat->CH_EccDQSLike[channel], pDCTstat->CH_EccDQSScale[channel], ChipSel); - print_debug_dqs_pair("\t\tSetEccDQSRdWrPos: channel ", channel, direction == DQS_READDIR? " R dqs_delay":" W dqs_delay", pDCTstat->DQSDelay, 2); - pDCTstat->ByteLane = 8; - StoreDQSDatStrucVal_D(pMCTstat, pDCTstat, ChipSel); - mct_SetDQSDelayCSR_D(pMCTstat, pDCTstat, ChipSel); - } - } -} - - - -static void CalcEccDQSPos_D(struct MCTStatStruc *pMCTstat, - struct DCTStatStruc *pDCTstat, - u16 like, u8 scale, u8 ChipSel) -{ - u8 DQSDelay0, DQSDelay1; - u16 DQSDelay; - - pDCTstat->ByteLane = like & 0xff; - GetDQSDatStrucVal_D(pMCTstat, pDCTstat, ChipSel); - DQSDelay0 = pDCTstat->DQSDelay; - - pDCTstat->ByteLane = (like >> 8) & 0xff; - GetDQSDatStrucVal_D(pMCTstat, pDCTstat, ChipSel); - DQSDelay1 = pDCTstat->DQSDelay; - - if (DQSDelay0 > DQSDelay1) { - DQSDelay = DQSDelay0 - DQSDelay1; - } else { - DQSDelay = DQSDelay1 - DQSDelay0; - } - - DQSDelay = DQSDelay * (~scale); - - DQSDelay += 0x80; // round it - - DQSDelay >>= 8; // /256 - - if (DQSDelay0 > DQSDelay1) { - DQSDelay = DQSDelay1 - DQSDelay; - } else { - DQSDelay += DQSDelay1; - } - - pDCTstat->DQSDelay = (u8)DQSDelay; -} - - -static void TrainDQSRdWrPos_D(struct MCTStatStruc *pMCTstat, - struct DCTStatStruc *pDCTstat, - u8 cs_start) -{ - u32 Errors; - u8 Channel, DQSWrDelay; - u8 _DisableDramECC = 0; - u32 PatternBuffer[292]; - u8 _Wrap32Dis = 0, _SSE2 = 0; - u8 dqsWrDelay_end; - - u32 addr; - CRx_TYPE cr4; - u32 lo, hi; - - print_debug_dqs("\nTrainDQSRdWrPos: Node_ID ", pDCTstat->Node_ID, 0); - cr4 = read_cr4(); - if (cr4 & (1<<9)) { - _SSE2 = 1; - } - cr4 |= (1<<9); /* OSFXSR enable SSE2 */ - write_cr4(cr4); - - addr = HWCR_MSR; - _RDMSR(addr, &lo, &hi); - if (lo & (1<<17)) { - _Wrap32Dis = 1; - } - lo |= (1<<17); /* HWCR.wrap32dis */ - _WRMSR(addr, lo, hi); /* allow 64-bit memory references in real mode */ - - /* Disable ECC correction of reads on the dram bus. */ - _DisableDramECC = mct_DisableDimmEccEn_D(pMCTstat, pDCTstat); - - SetupDqsPattern_D(pMCTstat, pDCTstat, PatternBuffer); - - /* mct_BeforeTrainDQSRdWrPos_D */ - dqsWrDelay_end = 0x20; - - Errors = 0; - for (Channel = 0; Channel < 2; Channel++) { - print_debug_dqs("\tTrainDQSRdWrPos: 1 Channel ",Channel, 1); - pDCTstat->Channel = Channel; - - if (pDCTstat->DIMMValidDCT[Channel] == 0) /* mct_BeforeTrainDQSRdWrPos_D */ - continue; - - for (DQSWrDelay = 0; DQSWrDelay < dqsWrDelay_end; DQSWrDelay++) { - pDCTstat->DQSDelay = DQSWrDelay; - pDCTstat->Direction = DQS_WRITEDIR; - mct_SetDQSDelayAllCSR_D(pMCTstat, pDCTstat, cs_start); - - print_debug_dqs("\t\tTrainDQSRdWrPos: 21 DQSWrDelay ", DQSWrDelay, 2); - TrainReadDQS_D(pMCTstat, pDCTstat, cs_start); - - print_debug_dqs("\t\tTrainDQSRdWrPos: 22 TrainErrors ",pDCTstat->TrainErrors, 2); - if (pDCTstat->TrainErrors == 0) { - break; - } - Errors |= pDCTstat->TrainErrors; - } - if (DQSWrDelay < dqsWrDelay_end) { - Errors = 0; - - print_debug_dqs("\tTrainDQSRdWrPos: 231 DQSWrDelay ", DQSWrDelay, 1); - TrainWriteDQS_D(pMCTstat, pDCTstat, cs_start); - } - print_debug_dqs("\tTrainDQSRdWrPos: 232 Errors ", Errors, 1); - pDCTstat->ErrStatus |= Errors; - } - -#if DQS_TRAIN_DEBUG > 0 - { - u8 val; - u8 i; - u8 Channel, Receiver, Dir; - u8 *p; - - for (Dir = 0; Dir < 2; Dir++) { - if (Dir == 0) { - printk(BIOS_DEBUG, "TrainDQSRdWrPos: CH_D_DIR_B_DQS WR:\n"); - } else { - printk(BIOS_DEBUG, "TrainDQSRdWrPos: CH_D_DIR_B_DQS RD:\n"); - } - for (Channel = 0; Channel < 2; Channel++) { - printk(BIOS_DEBUG, "Channel: %02x\n", Channel); - for (Receiver = cs_start; Receiver < (cs_start + 2); Receiver += 2) { - printk(BIOS_DEBUG, "\t\tReceiver: %02x: ", Receiver); - p = pDCTstat->persistentData.CH_D_DIR_B_DQS[Channel][Receiver >> 1][Dir]; - for (i = 0; i < 8; i++) { - val = p[i]; - printk(BIOS_DEBUG, "%02x ", val); - } - printk(BIOS_DEBUG, "\n"); - } - } - } - - } -#endif - - if (_DisableDramECC) { - mct_EnableDimmEccEn_D(pMCTstat, pDCTstat, _DisableDramECC); - } - if (!_Wrap32Dis) { - addr = HWCR_MSR; - _RDMSR(addr, &lo, &hi); - lo &= ~(1<<17); /* restore HWCR.wrap32dis */ - _WRMSR(addr, lo, hi); - } - if (!_SSE2) { - cr4 = read_cr4(); - cr4 &= ~(1<<9); /* restore cr4.OSFXSR */ - write_cr4(cr4); - } - - print_tx("TrainDQSRdWrPos: Status ", pDCTstat->Status); - print_tx("TrainDQSRdWrPos: TrainErrors ", pDCTstat->TrainErrors); - print_tx("TrainDQSRdWrPos: ErrStatus ", pDCTstat->ErrStatus); - print_tx("TrainDQSRdWrPos: ErrCode ", pDCTstat->ErrCode); - print_t("TrainDQSRdWrPos: Done\n"); -} - - -static void SetupDqsPattern_D(struct MCTStatStruc *pMCTstat, - struct DCTStatStruc *pDCTstat, u32 *buffer) -{ - /* 1. Set the Pattern type (0 or 1) in DCTStatstruc.Pattern - * 2. Copy the pattern from ROM to Cache, aligning on 16 byte boundary - * 3. Set the ptr to Cacheable copy in DCTStatstruc.PtrPatternBufA - */ - - u32 *buf; - u16 i; - - buf = (u32 *)(((u32)buffer + 0x10) & (0xfffffff0)); - if (pDCTstat->Status & (1 << SB_128bitmode)) { - pDCTstat->Pattern = 1; /* 18 cache lines, alternating qwords */ - for (i = 0; i < 16*18; i++) - buf[i] = TestPatternJD1b_D[i]; - } else { - pDCTstat->Pattern = 0; /* 9 cache lines, sequential qwords */ - for (i = 0; i < 16*9; i++) - buf[i] = TestPatternJD1a_D[i]; - } - pDCTstat->PtrPatternBufA = (u32)buf; -} - - -static void TrainDQSPos_D(struct MCTStatStruc *pMCTstat, - struct DCTStatStruc *pDCTstat, - u8 cs_start) -{ - u32 Errors; - u8 ChipSel, DQSDelay; - u8 RnkDlySeqPassMin,RnkDlySeqPassMax, RnkDlyFilterMin, RnkDlyFilterMax; - u8 LastTest; - u32 TestAddr; - u8 ByteLane; - u8 MutualCSPassW[64]; - u8 BanksPresent; - u8 dqsDelay_end; - u8 tmp, valid; - - - /* MutualCSPassW: each byte represents a bitmap of pass/fail per - * ByteLane. The indext within MutualCSPassW is the delay value - * given the results. - */ - - - print_debug_dqs("\t\t\tTrainDQSPos begin ", 0, 3); - - Errors = 0; - BanksPresent = 0; - - if (pDCTstat->Direction == DQS_READDIR) { - dqsDelay_end = 64; - mct_AdjustDelayRange_D(pMCTstat, pDCTstat, &dqsDelay_end); - } else { - dqsDelay_end = 32; - } - - /* Bitmapped status per delay setting, 0xff = All positions - * passing (1= PASS). Set the entire array. - */ - for (DQSDelay = 0; DQSDelay < 64; DQSDelay++) { - MutualCSPassW[DQSDelay] = 0xFF; - } - - for (ChipSel = cs_start; ChipSel < (cs_start + 2); ChipSel++) { /* logical register chipselects 0..7 */ - print_debug_dqs("\t\t\t\tTrainDQSPos: 11 ChipSel ", ChipSel, 4); - - if (!mct_RcvrRankEnabled_D(pMCTstat, pDCTstat, pDCTstat->Channel, ChipSel)) { - print_debug_dqs("\t\t\t\tmct_RcvrRankEnabled_D CS not enabled ", ChipSel, 4); - continue; - } - - BanksPresent = 1; /* flag for at least one bank is present */ - TestAddr = mct_GetMCTSysAddr_D(pMCTstat, pDCTstat, pDCTstat->Channel, ChipSel, &valid); - if (!valid) { - print_debug_dqs("\t\t\t\tAddress not supported on current CS ", TestAddr, 4); - continue; - } - - print_debug_dqs("\t\t\t\tTrainDQSPos: 12 TestAddr ", TestAddr, 4); - SetUpperFSbase(TestAddr); /* fs:eax = far ptr to target */ - - if (pDCTstat->Direction == DQS_READDIR) { - print_debug_dqs("\t\t\t\tTrainDQSPos: 13 for read ", 0, 4); - WriteDQSTestPattern_D(pMCTstat, pDCTstat, TestAddr << 8); - } - - for (DQSDelay = 0; DQSDelay < dqsDelay_end; DQSDelay++) { - print_debug_dqs("\t\t\t\t\tTrainDQSPos: 141 DQSDelay ", DQSDelay, 5); - if (MutualCSPassW[DQSDelay] == 0) - continue; //skip current delay value if other chipselects have failed all 8 bytelanes - pDCTstat->DQSDelay = DQSDelay; - mct_SetDQSDelayAllCSR_D(pMCTstat, pDCTstat, cs_start); - print_debug_dqs("\t\t\t\t\tTrainDQSPos: 142 MutualCSPassW ", MutualCSPassW[DQSDelay], 5); - - if (pDCTstat->Direction == DQS_WRITEDIR) { - print_debug_dqs("\t\t\t\t\tTrainDQSPos: 143 for write", 0, 5); - WriteDQSTestPattern_D(pMCTstat, pDCTstat, TestAddr << 8); - } - - print_debug_dqs("\t\t\t\t\tTrainDQSPos: 144 Pattern ", pDCTstat->Pattern, 5); - ReadDQSTestPattern_D(pMCTstat, pDCTstat, TestAddr << 8); - /* print_debug_dqs("\t\t\t\t\tTrainDQSPos: 145 MutualCSPassW ", MutualCSPassW[DQSDelay], 5); */ - tmp = CompareDQSTestPattern_D(pMCTstat, pDCTstat, TestAddr << 8); /* 0 = fail, 1 = pass */ - - if (mct_checkFenceHoleAdjust_D(pMCTstat, pDCTstat, DQSDelay, ChipSel, &tmp)) { - goto skipLocMiddle; - } - - MutualCSPassW[DQSDelay] &= tmp; - print_debug_dqs("\t\t\t\t\tTrainDQSPos: 146\tMutualCSPassW ", MutualCSPassW[DQSDelay], 5); - - SetTargetWTIO_D(TestAddr); - FlushDQSTestPattern_D(pDCTstat, TestAddr << 8); - ResetTargetWTIO_D(); - } - - } - - if (BanksPresent) { - for (ByteLane = 0; ByteLane < 8; ByteLane++) { - print_debug_dqs("\t\t\t\tTrainDQSPos: 31 ByteLane ",ByteLane, 4); - pDCTstat->ByteLane = ByteLane; - LastTest = DQS_FAIL; /* Analyze the results */ - RnkDlySeqPassMin = 0; - RnkDlySeqPassMax = 0; - RnkDlyFilterMax = 0; - RnkDlyFilterMin = 0; - for (DQSDelay = 0; DQSDelay < dqsDelay_end; DQSDelay++) { - if (MutualCSPassW[DQSDelay] & (1 << ByteLane)) { - print_debug_dqs("\t\t\t\t\tTrainDQSPos: 321 DQSDelay ", DQSDelay, 5); - print_debug_dqs("\t\t\t\t\tTrainDQSPos: 322 MutualCSPassW ", MutualCSPassW[DQSDelay], 5); - - RnkDlySeqPassMax = DQSDelay; - if (LastTest == DQS_FAIL) { - RnkDlySeqPassMin = DQSDelay; //start sequential run - } - if ((RnkDlySeqPassMax - RnkDlySeqPassMin)>(RnkDlyFilterMax-RnkDlyFilterMin)) { - RnkDlyFilterMin = RnkDlySeqPassMin; - RnkDlyFilterMax = RnkDlySeqPassMax; - } - LastTest = DQS_PASS; - } else { - LastTest = DQS_FAIL; - } - } - print_debug_dqs("\t\t\t\tTrainDQSPos: 33 RnkDlySeqPassMax ", RnkDlySeqPassMax, 4); - if (RnkDlySeqPassMax == 0) { - Errors |= 1 << SB_NODQSPOS; /* no passing window */ - } else { - print_debug_dqs_pair("\t\t\t\tTrainDQSPos: 34 RnkDlyFilter: ", RnkDlyFilterMin, " ", RnkDlyFilterMax, 4); - if (((RnkDlyFilterMax - RnkDlyFilterMin) < MIN_DQS_WNDW)) { - Errors |= 1 << SB_SMALLDQS; - } else { - u8 middle_dqs; - /* mctEngDQSwindow_Save_D Not required for arrays */ - middle_dqs = MiddleDQS_D(RnkDlyFilterMin, RnkDlyFilterMax); - pDCTstat->DQSDelay = middle_dqs; - mct_SetDQSDelayCSR_D(pMCTstat, pDCTstat, cs_start); /* load the register with the value */ - StoreDQSDatStrucVal_D(pMCTstat, pDCTstat, cs_start); /* store the value into the data structure */ - print_debug_dqs("\t\t\t\tTrainDQSPos: 42 middle_dqs : ",middle_dqs, 4); - } - } - } - } -skipLocMiddle: - pDCTstat->TrainErrors = Errors; - - print_debug_dqs("\t\t\tTrainDQSPos: Errors ", Errors, 3); - -} - - -void StoreDQSDatStrucVal_D(struct MCTStatStruc *pMCTstat, - struct DCTStatStruc *pDCTstat, u8 ChipSel) -{ - /* Store the DQSDelay value, found during a training sweep, into the DCT - * status structure for this node - */ - - - /* When 400, 533, 667, it will support dimm0/1/2/3, - * and set conf for dimm0, hw will copy to dimm1/2/3 - * set for dimm1, hw will copy to dimm3 - * Rev A/B only support DIMM0/1 when 800MHz and above + 0x100 to next dimm - * Rev C support DIMM0/1/2/3 when 800MHz and above + 0x100 to next dimm - */ - - /* FindDQSDatDimmVal_D is not required since we use an array */ - u8 dn = 0; - - if (pDCTstat->Status & (1 << SB_Over400MHz)) - dn = ChipSel>>1; /* if odd or even logical DIMM */ - - pDCTstat->persistentData.CH_D_DIR_B_DQS[pDCTstat->Channel][dn][pDCTstat->Direction][pDCTstat->ByteLane] = - pDCTstat->DQSDelay; -} - - -static void GetDQSDatStrucVal_D(struct MCTStatStruc *pMCTstat, - struct DCTStatStruc *pDCTstat, u8 ChipSel) -{ - u8 dn = 0; - - - /* When 400, 533, 667, it will support dimm0/1/2/3, - * and set conf for dimm0, hw will copy to dimm1/2/3 - * set for dimm1, hw will copy to dimm3 - * Rev A/B only support DIMM0/1 when 800MHz and above + 0x100 to next dimm - * Rev C support DIMM0/1/2/3 when 800MHz and above + 0x100 to next dimm - */ - - /* FindDQSDatDimmVal_D is not required since we use an array */ - if (pDCTstat->Status & (1<> 1; /*if odd or even logical DIMM */ - - pDCTstat->DQSDelay = - pDCTstat->persistentData.CH_D_DIR_B_DQS[pDCTstat->Channel][dn][pDCTstat->Direction][pDCTstat->ByteLane]; -} - - -/* FindDQSDatDimmVal_D is not required since we use an array */ - - -static u8 MiddleDQS_D(u8 min, u8 max) -{ - u8 size; - size = max-min; - if (size % 2) - size++; // round up if the size isn't even. - return (min + (size >> 1)); -} - - -static void TrainReadDQS_D(struct MCTStatStruc *pMCTstat, - struct DCTStatStruc *pDCTstat, - u8 cs_start) -{ - print_debug_dqs("\t\tTrainReadPos ", 0, 2); - pDCTstat->Direction = DQS_READDIR; - TrainDQSPos_D(pMCTstat, pDCTstat, cs_start); -} - - -static void TrainWriteDQS_D(struct MCTStatStruc *pMCTstat, - struct DCTStatStruc *pDCTstat, - u8 cs_start) -{ - pDCTstat->Direction = DQS_WRITEDIR; - print_debug_dqs("\t\tTrainWritePos", 0, 2); - TrainDQSPos_D(pMCTstat, pDCTstat, cs_start); -} - - -void proc_IOCLFLUSH_D(u32 addr_hi) -{ - SetTargetWTIO_D(addr_hi); - proc_CLFLUSH(addr_hi); - ResetTargetWTIO_D(); -} - - -static u8 ChipSelPresent_D(struct MCTStatStruc *pMCTstat, - struct DCTStatStruc *pDCTstat, - u8 Channel, u8 ChipSel) -{ - u32 val; - u32 reg; - u32 dev = pDCTstat->dev_dct; - u32 reg_off; - u8 ret = 0; - - if (!pDCTstat->GangedMode) { - reg_off = 0x100 * Channel; - } else { - reg_off = 0; - } - - if (ChipSel < MAX_CS_SUPPORTED) { - reg = 0x40 + (ChipSel << 2) + reg_off; - val = Get_NB32(dev, reg); - if (val & (1 << 0)) - ret = 1; - } - - return ret; -} - - -/* proc_CLFLUSH_D located in mct_gcc.h */ - - -static void WriteDQSTestPattern_D(struct MCTStatStruc *pMCTstat, - struct DCTStatStruc *pDCTstat, - u32 TestAddr_lo) -{ - /* Write a pattern of 72 bit times (per DQ), to test dram functionality. - * The pattern is a stress pattern which exercises both ISI and - * crosstalk. The number of cache lines to fill is dependent on DCT - * width mode and burstlength. - * Mode BL Lines Pattern no. - * ----+---+------------------- - * 64 4 9 0 - * 64 8 9 0 - * 64M 4 9 0 - * 64M 8 9 0 - * 128 4 18 1 - * 128 8 N/A - - */ - - if (pDCTstat->Pattern == 0) - WriteL9TestPattern_D(pDCTstat, TestAddr_lo); - else - WriteL18TestPattern_D(pDCTstat, TestAddr_lo); -} - - -static void WriteL18TestPattern_D(struct DCTStatStruc *pDCTstat, - u32 TestAddr_lo) -{ - u8 *buf; - - buf = (u8 *)pDCTstat->PtrPatternBufA; - WriteLNTestPattern(TestAddr_lo, buf, 18); - -} - - -static void WriteL9TestPattern_D(struct DCTStatStruc *pDCTstat, - u32 TestAddr_lo) -{ - u8 *buf; - - buf = (u8 *)pDCTstat->PtrPatternBufA; - WriteLNTestPattern(TestAddr_lo, buf, 9); -} - - - -static u8 CompareDQSTestPattern_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstat, u32 addr_lo) -{ - /* Compare a pattern of 72 bit times (per DQ), to test dram functionality. - * The pattern is a stress pattern which exercises both ISI and - * crosstalk. The number of cache lines to fill is dependent on DCT - * width mode and burstlength. - * Mode BL Lines Pattern no. - * ----+---+------------------- - * 64 4 9 0 - * 64 8 9 0 - * 64M 4 9 0 - * 64M 8 9 0 - * 128 4 18 1 - * 128 8 N/A - - */ - - u32 *test_buf; - u8 bitmap; - u8 bytelane; - u8 i; - u32 value; - u8 j; - u32 value_test; - u8 pattern, channel; - - pattern = pDCTstat->Pattern; - channel = pDCTstat->Channel; - test_buf = (u32 *)pDCTstat->PtrPatternBufA; - - if (pattern && channel) { - addr_lo += 8; //second channel - test_buf += 2; - } - - bytelane = 0; /* bytelane counter */ - bitmap = 0xFF; /* bytelane test bitmap, 1 = pass */ - for (i = 0; i < (9 * 64 / 4); i++) { /* sizeof testpattern. /4 due to next loop */ - value = read32_fs(addr_lo); - value_test = *test_buf; - - print_debug_dqs_pair("\t\t\t\t\t\ttest_buf = ", (u32)test_buf, " value = ", value_test, 7); - print_debug_dqs_pair("\t\t\t\t\t\ttaddr_lo = ", addr_lo, " value = ", value, 7); - - for (j = 0; j < (4 * 8); j += 8) { /* go through a 32bit data, on 1 byte step. */ - if (((value >> j) & 0xff) != ((value_test >> j) & 0xff)) { - bitmap &= ~(1 << bytelane); - } - - bytelane++; - bytelane &= 0x7; - } - - print_debug_dqs("\t\t\t\t\t\tbitmap = ", bitmap, 7); - - if (!bitmap) - break; - - if (bytelane == 0) { - if (pattern == 1) { //dual channel - addr_lo += 8; //skip over other channel's data - test_buf += 2; - } - } - addr_lo += 4; - test_buf += 1; - } - - return bitmap; -} - - -static void FlushDQSTestPattern_D(struct DCTStatStruc *pDCTstat, - u32 addr_lo) -{ - /* Flush functions in mct_gcc.h */ - if (pDCTstat->Pattern == 0) { - FlushDQSTestPattern_L9(addr_lo); - } else { - FlushDQSTestPattern_L18(addr_lo); - } -} - -void SetTargetWTIO_D(u32 TestAddr) -{ - u32 lo, hi; - hi = TestAddr >> 24; - lo = TestAddr << 8; - _WRMSR(MTRR_IORR0_BASE, lo, hi); /* IORR0 Base */ - hi = 0xFF; - lo = 0xFC000800; /* 64MB Mask */ - _WRMSR(MTRR_IORR0_MASK, lo, hi); /* IORR0 Mask */ -} - - -void ResetTargetWTIO_D(void) -{ - u32 lo, hi; - - hi = 0; - lo = 0; - _WRMSR(MTRR_IORR0_MASK, lo, hi); // IORR0 Mask -} - - -static void ReadDQSTestPattern_D(struct MCTStatStruc *pMCTstat, - struct DCTStatStruc *pDCTstat, - u32 TestAddr_lo) -{ - /* Read a pattern of 72 bit times (per DQ), to test dram functionality. - * The pattern is a stress pattern which exercises both ISI and - * crosstalk. The number of cache lines to fill is dependent on DCT - * width mode and burstlength. - * Mode BL Lines Pattern no. - * ----+---+------------------- - * 64 4 9 0 - * 64 8 9 0 - * 64M 4 9 0 - * 64M 8 9 0 - * 128 4 18 1 - * 128 8 N/A - - */ - if (pDCTstat->Pattern == 0) - ReadL9TestPattern(TestAddr_lo); - else - ReadL18TestPattern(TestAddr_lo); - _MFENCE; -} - - -u32 SetUpperFSbase(u32 addr_hi) -{ - /* Set the upper 32-bits of the Base address, 4GB aligned) for the - * FS selector. - */ - - u32 lo, hi; - u32 addr; - lo = 0; - hi = addr_hi>>24; - addr = FS_Base; - _WRMSR(addr, lo, hi); - return addr_hi << 8; -} - - -void ResetDCTWrPtr_D(u32 dev, u32 index_reg, u32 index) -{ - u32 val; - - val = Get_NB32_index_wait(dev, index_reg, index); - Set_NB32_index_wait(dev, index_reg, index, val); -} - - -/* mctEngDQSwindow_Save_D not required with arrays */ - - -void mct_TrainDQSPos_D(struct MCTStatStruc *pMCTstat, - struct DCTStatStruc *pDCTstatA) -{ - u8 Node; - u8 ChipSel; - struct DCTStatStruc *pDCTstat; - - for (Node = 0; Node < MAX_NODES_SUPPORTED; Node++) { - pDCTstat = pDCTstatA + Node; - if (pDCTstat->DCTSysLimit) { - /* when DCT speed >= 400MHz, we only support 2 DIMMs - * and we have two sets registers for DIMM0 and DIMM1 so - * here we must traning DQSRd/WrPos for DIMM0 and DIMM1 - */ - if (pDCTstat->Speed >= 4) { - pDCTstat->Status |= (1 << SB_Over400MHz); - } - for (ChipSel = 0; ChipSel < MAX_CS_SUPPORTED; ChipSel += 2) { - TrainDQSRdWrPos_D(pMCTstat, pDCTstat, ChipSel); - SetEccDQSRdWrPos_D(pMCTstat, pDCTstat, ChipSel); - } - } - } -} - - -/* mct_BeforeTrainDQSRdWrPos_D - * Function is inline. - */ - -u8 mct_DisableDimmEccEn_D(struct MCTStatStruc *pMCTstat, - struct DCTStatStruc *pDCTstat) -{ - u8 _DisableDramECC = 0; - u32 val; - u32 reg; - u32 dev; - - /*Disable ECC correction of reads on the dram bus. */ - - dev = pDCTstat->dev_dct; - reg = 0x90; - val = Get_NB32(dev, reg); - if (val & (1<GangedMode) { - reg = 0x190; - val = Get_NB32(dev, reg); - if (val & (1<dev_dct; - - if ((_DisableDramECC & 0x01) == 0x01) { - reg = 0x90; - val = Get_NB32(dev, reg); - val |= (1<Channel; - u8 shift; - u32 dqs_delay = (u32)pDCTstat->DQSDelay; - u32 dev = pDCTstat->dev_dct; - u32 index; - - ByteLane = pDCTstat->ByteLane; - - /* Channel is offset */ - if (ByteLane < 4) { - index = 1; - } else if (ByteLane <8) { - index = 2; - } else { - index = 3; - } - - if (pDCTstat->Direction == DQS_READDIR) { - index += 4; - } - - /* get the proper register index */ - shift = ByteLane % 4; - shift <<= 3; /* get bit position of bytelane, 8 bit */ - - if (pDCTstat->Status & (1 << SB_Over400MHz)) { - index += (ChipSel >> 1) * 0x100; /* if logical DIMM1/DIMM3 */ - } - - val = Get_NB32_index_wait(dev, index_reg, index); - val &= ~(0x7f << shift); - val |= (dqs_delay << shift); - Set_NB32_index_wait(dev, index_reg, index, val); -} - - -static void mct_SetDQSDelayAllCSR_D(struct MCTStatStruc *pMCTstat, - struct DCTStatStruc *pDCTstat, - u8 cs_start) -{ - u8 ByteLane; - u8 ChipSel = cs_start; - - - for (ChipSel = cs_start; ChipSel < (cs_start + 2); ChipSel++) { - if (mct_RcvrRankEnabled_D(pMCTstat, pDCTstat, pDCTstat->Channel, ChipSel)) { - for (ByteLane = 0; ByteLane < 8; ByteLane++) { - pDCTstat->ByteLane = ByteLane; - mct_SetDQSDelayCSR_D(pMCTstat, pDCTstat, ChipSel); - } - } - } -} - - -u8 mct_RcvrRankEnabled_D(struct MCTStatStruc *pMCTstat, - struct DCTStatStruc *pDCTstat, - u8 Channel, u8 ChipSel) -{ - u8 ret; - - ret = ChipSelPresent_D(pMCTstat, pDCTstat, Channel, ChipSel); - return ret; -} - - -u32 mct_GetRcvrSysAddr_D(struct MCTStatStruc *pMCTstat, - struct DCTStatStruc *pDCTstat, - u8 channel, u8 receiver, u8 *valid) -{ - return mct_GetMCTSysAddr_D(pMCTstat, pDCTstat, channel, receiver, valid); -} - - -u32 mct_GetMCTSysAddr_D(struct MCTStatStruc *pMCTstat, - struct DCTStatStruc *pDCTstat, - u8 Channel, u8 receiver, u8 *valid) -{ - u32 val; - u32 reg_off = 0; - u32 reg; - u32 dword; - u32 dev = pDCTstat->dev_dct; - - *valid = 0; - - - if (!pDCTstat->GangedMode) { - reg_off = 0x100 * Channel; - } - - /* get the local base addr of the chipselect */ - reg = 0x40 + (receiver << 2) + reg_off; - val = Get_NB32(dev, reg); - - val &= ~0x0F; - - /* unganged mode DCT0+DCT1, sys addr of DCT1 = node - * base+DctSelBaseAddr+local ca base*/ - if ((Channel) && (pDCTstat->GangedMode == 0) && (pDCTstat->DIMMValidDCT[0] > 0)) { - reg = 0x110; - dword = Get_NB32(dev, reg); - dword &= 0xfffff800; - dword <<= 8; /* scale [47:27] of F2x110[31:11] to [39:8]*/ - val += dword; - - /* if DCTSelBaseAddr < Hole, and eax > HoleBase, then add Hole size to test address */ - if ((val >= pDCTstat->DCTHoleBase) && (pDCTstat->DCTHoleBase > dword)) { - dword = (~(pDCTstat->DCTHoleBase >> (24 - 8)) + 1) & 0xFF; - dword <<= (24 - 8); - val += dword; - } - } else { - /* sys addr = node base+local cs base */ - val += pDCTstat->DCTSysBase; - - /* New stuff */ - if (pDCTstat->DCTHoleBase && (val >= pDCTstat->DCTHoleBase)) { - val -= pDCTstat->DCTSysBase; - dword = Get_NB32(pDCTstat->dev_map, 0xF0); /* get Hole Offset */ - val += (dword & 0x0000ff00) << (24-8-8); - } - } - - /* New stuff */ - val += ((1 << 21) >> 8); /* Add 2MB offset to avoid compat area */ - if (val >= MCT_TRNG_KEEPOUT_START) { - while (val < MCT_TRNG_KEEPOUT_END) - val += (1 << (15-8)); /* add 32K */ - } - - /* Add a node seed */ - val += (((1 * pDCTstat->Node_ID) << 20) >> 8); /* Add 1MB per node to avoid aliases */ - - /* HW remap disabled? */ - if (!(pDCTstat->Status & (1 << SB_HWHole))) { - if (!(pDCTstat->Status & (1 << SB_SWNodeHole))) { - /* SW memhole disabled */ - u32 lo, hi; - _RDMSR(TOP_MEM, &lo, &hi); - lo >>= 8; - if ((val >= lo) && (val < _4GB_RJ8)) { - val = 0; - *valid = 0; - goto exitGetAddr; - } else { - *valid = 1; - goto exitGetAddrWNoError; - } - } else { - *valid = 1; - goto exitGetAddrWNoError; - } - } else { - *valid = 1; - goto exitGetAddrWNoError; - } - -exitGetAddrWNoError: - - /* Skip if Address is in UMA region */ - dword = pMCTstat->Sub4GCacheTop; - dword >>= 8; - if (dword != 0) { - if ((val >= dword) && (val < _4GB_RJ8)) { - val = 0; - *valid = 0; - } else { - *valid = 1; - } - } - print_debug_dqs("mct_GetMCTSysAddr_D: receiver ", receiver, 2); - print_debug_dqs("mct_GetMCTSysAddr_D: Channel ", Channel, 2); - print_debug_dqs("mct_GetMCTSysAddr_D: base_addr ", val, 2); - print_debug_dqs("mct_GetMCTSysAddr_D: valid ", *valid, 2); - print_debug_dqs("mct_GetMCTSysAddr_D: status ", pDCTstat->Status, 2); - print_debug_dqs("mct_GetMCTSysAddr_D: HoleBase ", pDCTstat->DCTHoleBase, 2); - print_debug_dqs("mct_GetMCTSysAddr_D: Cachetop ", pMCTstat->Sub4GCacheTop, 2); - -exitGetAddr: - return val; -} - - -void mct_Write1LTestPattern_D(struct MCTStatStruc *pMCTstat, - struct DCTStatStruc *pDCTstat, - u32 TestAddr, u8 pattern) -{ - - u8 *buf; - - /* Issue the stream of writes. When F2x11C[MctWrLimit] is reached - * (or when F2x11C[FlushWr] is set again), all the writes are written - * to DRAM. - */ - - SetUpperFSbase(TestAddr); - - if (pattern) - buf = (u8 *)pDCTstat->PtrPatternBufB; - else - buf = (u8 *)pDCTstat->PtrPatternBufA; - - WriteLNTestPattern(TestAddr << 8, buf, 1); -} - - -void mct_Read1LTestPattern_D(struct MCTStatStruc *pMCTstat, - struct DCTStatStruc *pDCTstat, u32 addr) -{ - /* BIOS issues the remaining (Ntrain - 2) reads after checking that - * F2x11C[PrefDramTrainMode] is cleared. These reads must be to - * consecutive cache lines (i.e., 64 bytes apart) and must not cross - * a naturally aligned 4KB boundary. These reads hit the prefetches and - * read the data from the prefetch buffer. - */ - - /* get data from DIMM */ - SetUpperFSbase(addr); - - /* 1st move causes read fill (to exclusive or shared)*/ - read32_fs(addr << 8); -} diff --git a/src/northbridge/amd/amdmct/mct/mctecc_d.c b/src/northbridge/amd/amdmct/mct/mctecc_d.c deleted file mode 100644 index 8eb7bf54b7..0000000000 --- a/src/northbridge/amd/amdmct/mct/mctecc_d.c +++ /dev/null @@ -1,314 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007-2008 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - - -#include "mct_d.h" - -static void setSyncOnUnEccEn_D(struct MCTStatStruc *pMCTstat, - struct DCTStatStruc *pDCTstatA); -#ifdef UNUSED_CODE -static u32 GetScrubAddr_D(u32 Node); -#endif -static u8 isDramECCEn_D(struct DCTStatStruc *pDCTstat); - - -/* Initialize ECC modes of Integrated Dram+Memory Controllers of a network of - * Hammer processors. Use Dram background scrubber to fast initialize ECC bits - * of all dram. - * - * Notes: - * - * Order that items are set: - * 1. eccen bit in NB - * 2. Scrub Base - * 3. Temp Node Base - * 4. Temp Node Limit - * 5. Redir bit in NB - * 6. Scrub CTL - * - * Conditions for setting background scrubber. - * 1. node is present - * 2. node has dram functioning (WE = RE = 1) - * 3. all eccdimms (or bit 17 of offset 90,fn 2) - * 4. no chip-select gap exists - * - * The dram background scrubber is used under very controlled circumstances to - * initialize all the ECC bits on the DIMMs of the entire dram address map - * (including hidden or lost dram and dram above 4GB). We will turn the scrub - * rate up to maximum, which should clear 4GB of dram in about 2.7 seconds. - * We will activate the scrubbers of all nodes with ecc dram and let them run in - * parallel, thereby reducing even further the time required to condition dram. - * Finally, we will go through each node and either disable background scrubber, - * or set the scrub rate to the user setup specified rate. - * - * To allow the NB to scrub, we need to wait a time period long enough to - * guarantee that the NB scrubs the entire dram on its node. Do do this, we - * simply sample the scrub ADDR once, for an initial value, then we sample and poll until the polled value of scrub ADDR - * has wrapped around at least once: Scrub ADDRi+1 < Scrub ADDRi. Since we let all - * Nodes run in parallel, we need to guarantee that all nodes have wrapped. To do - * this efficiently, we need only to sample one of the nodes, the node with the - * largest ammount of dram populated is the one which will take the longest amount - * of time (the scrub rate is set to max, the same rate, on all nodes). So, - * during setup of scrub Base, we determine how much memory and which node has - * the largest memory installed. - * - * Scrubbing should not ordinarily be enabled on a Node with a chip-select gap - * (aka SW memhole, cs hoisting, etc..).To init ECC memory on this node, the - * scrubber is used in two steps. First, the Dram Limit for the node is adjusted - * down to the bottom of the gap, and that ECC dram is initialized. Second, the - * original Limit is restored, the Scrub base is set to 4GB, and scrubber is - * allowed to run until the Scrub Addr wraps around to zero. - */ -u8 ECCInit_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstatA) -{ - u8 Node; - u8 AllECC; - u16 OB_NBECC; - u32 curBase; - u16 OB_ECCRedir; - u32 LDramECC; - u32 OF_ScrubCTL; - u8 MemClrECC; - - u32 dev; - u32 reg; - u32 val; - u16 nvbits; - - mctHookBeforeECC(); - - /* Construct these booleans, based on setup options, for easy handling - later in this procedure */ - OB_NBECC = mctGet_NVbits(NV_NBECC); /* MCA ECC (MCE) enable bit */ - - OB_ECCRedir = mctGet_NVbits(NV_ECCRedir); /* ECC Redirection */ - - mctGet_NVbits(NV_ChipKill); /* ECC Chip-kill mode */ - - OF_ScrubCTL = 0; /* Scrub CTL for Dcache, L2, and dram */ - nvbits = mctGet_NVbits(NV_DCBKScrub); - mct_AdjustScrub_D(pDCTstatA, &nvbits); - OF_ScrubCTL |= (u32) nvbits << 16; - - nvbits = mctGet_NVbits(NV_L2BKScrub); - OF_ScrubCTL |= (u32) nvbits << 8; - - nvbits = mctGet_NVbits(NV_DramBKScrub); - OF_ScrubCTL |= nvbits; - - AllECC = 1; - MemClrECC = 0; - for (Node = 0; Node < MAX_NODES_SUPPORTED; Node++) { - struct DCTStatStruc *pDCTstat; - pDCTstat = pDCTstatA + Node; - LDramECC = 0; - if (NodePresent_D(Node)) { /*If Node is present */ - dev = pDCTstat->dev_map; - reg = 0x40+(Node << 3); /* Dram Base Node 0 + index */ - val = Get_NB32(dev, reg); - - /* WE/RE is checked */ - if ((val & 3) == 3) { /* Node has dram populated */ - /* Negate 'all nodes/dimms ECC' flag if non ecc - memory populated */ - if (pDCTstat->Status & (1 << SB_ECCDIMMs)) { - LDramECC = isDramECCEn_D(pDCTstat); - if (pDCTstat->ErrCode != SC_RunningOK) { - pDCTstat->Status &= ~(1 << SB_ECCDIMMs); - if (!OB_NBECC) { - pDCTstat->ErrStatus |= (1 << SB_DramECCDis); - } - AllECC = 0; - LDramECC =0; - } - } else { - AllECC = 0; - } - if (LDramECC) { /* if ECC is enabled on this dram */ - if (OB_NBECC) { - mct_EnableDatIntlv_D(pMCTstat, pDCTstat); - dev = pDCTstat->dev_nbmisc; - reg =0x44; /* MCA NB Configuration */ - val = Get_NB32(dev, reg); - val |= 1 << 22; /* EccEn */ - Set_NB32(dev, reg, val); - DCTMemClr_Init_D(pMCTstat, pDCTstat); - MemClrECC = 1; - print_tx(" ECC enabled on node: ", Node); - } - } /* this node has ECC enabled dram */ - } else { - LDramECC = 0; - } /* Node has Dram */ - - if (MemClrECC) { - MCTMemClrSync_D(pMCTstat, pDCTstatA); - } - } /* if Node present */ - } - - if (AllECC) - pMCTstat->GStatus |= 1 << GSB_ECCDIMMs; - else - pMCTstat->GStatus &= ~(1 << GSB_ECCDIMMs); - - /* Program the Dram BKScrub CTL to the proper (user selected) value.*/ - /* Reset MC4_STS. */ - for (Node = 0; Node < MAX_NODES_SUPPORTED; Node++) { - struct DCTStatStruc *pDCTstat; - pDCTstat = pDCTstatA + Node; - LDramECC = 0; - if (NodePresent_D(Node)) { /* If Node is present */ - reg = 0x40+(Node << 3); /* Dram Base Node 0 + index */ - val = Get_NB32(pDCTstat->dev_map, reg); - curBase = val & 0xffff0000; - /*WE/RE is checked because memory config may have been */ - if ((val & 3) == 3) { /* Node has dram populated */ - if (isDramECCEn_D(pDCTstat)) { /* if ECC is enabled on this dram */ - dev = pDCTstat->dev_nbmisc; - val = curBase << 8; - if (OB_ECCRedir) { - val |= (1<<0); /* enable redirection */ - } - Set_NB32(dev, 0x5C, val); /* Dram Scrub Addr Low */ - val = curBase >> 24; - Set_NB32(dev, 0x60, val); /* Dram Scrub Addr High */ - Set_NB32(dev, 0x58, OF_ScrubCTL); /*Scrub Control */ - - /* Divisor should not be set deeper than - * divide by 16 when Dcache scrubber or - * L2 scrubber is enabled. - */ - if ((OF_ScrubCTL & (0x1F << 16)) || (OF_ScrubCTL & (0x1F << 8))) { - val = Get_NB32(dev, 0x84); - if ((val & 0xE0000000) > 0x80000000) { /* Get F3x84h[31:29]ClkDivisor for C1 */ - val &= 0x1FFFFFFF; /* If ClkDivisor is deeper than divide-by-16 */ - val |= 0x80000000; /* set it to divide-by-16 */ - Set_NB32(dev, 0x84, val); - } - } - } /* this node has ECC enabled dram */ - } /*Node has Dram */ - } /*if Node present */ - } - - if (mctGet_NVbits(NV_SyncOnUnEccEn)) - setSyncOnUnEccEn_D(pMCTstat, pDCTstatA); - - mctHookAfterECC(); - for (Node = 0; Node < MAX_NODES_SUPPORTED; Node++) { - struct DCTStatStruc *pDCTstat; - pDCTstat = pDCTstatA + Node; - if (NodePresent_D(Node)) { - print_tx("ECCInit: Node ", Node); - print_tx("ECCInit: Status ", pDCTstat->Status); - print_tx("ECCInit: ErrStatus ", pDCTstat->ErrStatus); - print_tx("ECCInit: ErrCode ", pDCTstat->ErrCode); - print_t("ECCInit: Done\n"); - } - } - return MemClrECC; -} - - -static void setSyncOnUnEccEn_D(struct MCTStatStruc *pMCTstat, - struct DCTStatStruc *pDCTstatA) -{ - u32 Node; - u32 reg; - u32 dev; - u32 val; - - for (Node = 0; Node < MAX_NODES_SUPPORTED; Node++) { - struct DCTStatStruc *pDCTstat; - pDCTstat = pDCTstatA + Node; - if (NodePresent_D(Node)) { /* If Node is present*/ - reg = 0x40+(Node << 3); /* Dram Base Node 0 + index*/ - val = Get_NB32(pDCTstat->dev_map, reg); - /*WE/RE is checked because memory config may have been*/ - if ((val & 3) == 3) { /* Node has dram populated*/ - if (isDramECCEn_D(pDCTstat)) { - /*if ECC is enabled on this dram*/ - dev = pDCTstat->dev_nbmisc; - reg = 0x44; /* MCA NB Configuration*/ - val = Get_NB32(dev, reg); - val |= (1 << SyncOnUcEccEn); - Set_NB32(dev, reg, val); - } - } /* Node has Dram*/ - } /* if Node present*/ - } -} - -#ifdef UNUSED_CODE -static u32 GetScrubAddr_D(u32 Node) -{ - /* Get the current 40-bit Scrub ADDR address, scaled to 32-bits, - * of the specified Node. - */ - - u32 reg; - u32 regx; - u32 lo, hi; - u32 val; - u32 dev = PA_NBMISC(Node); - - - reg = 0x60; /* Scrub Addr High */ - hi = Get_NB32(dev, reg); - - regx = 0x5C; /* Scrub Addr Low */ - lo = Get_NB32(dev, regx); - /* Scrub Addr High again, detect 32-bit wrap */ - val = Get_NB32(dev, reg); - if (val != hi) { - hi = val; /* Scrub Addr Low again, if wrap occurred */ - lo = Get_NB32(dev, regx); - } - - val = hi << 24; - val |= lo >> 8; - - return val; /* ScrubAddr[39:8] */ -} -#endif - -static u8 isDramECCEn_D(struct DCTStatStruc *pDCTstat) -{ - u32 reg; - u32 val; - u8 i; - u32 dev = pDCTstat->dev_dct; - u8 ch_end; - u8 isDimmECCEn = 0; - - if (pDCTstat->GangedMode) { - ch_end = 1; - } else { - ch_end = 2; - } - for (i = 0; i < ch_end; i++) { - if (pDCTstat->DIMMValidDCT[i] > 0) { - reg = 0x90 + i * 0x100; /* Dram Config Low */ - val = Get_NB32(dev, reg); - if (val & (1 << DimmEcEn)) { - /* set local flag 'dram ecc capable' */ - isDimmECCEn = 1; - break; - } - } - } - return isDimmECCEn; -} diff --git a/src/northbridge/amd/amdmct/mct/mctgr.c b/src/northbridge/amd/amdmct/mct/mctgr.c deleted file mode 100644 index 41a479b21e..0000000000 --- a/src/northbridge/amd/amdmct/mct/mctgr.c +++ /dev/null @@ -1,84 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - - -static const u8 Tab_GRCLKDis[] = { 8,0,8,8,0,0,8,0 }; - - -u32 mct_AdjustMemClkDis_GR(struct DCTStatStruc *pDCTstat, u32 dct, - u32 DramTimingLo) -{ - /* Greayhound format -> Griffin format */ - u32 NewDramTimingLo; - u32 dev = pDCTstat->dev_dct; - u32 reg; - u32 reg_off = 0x100 * dct; - u32 val; - int i; - - DramTimingLo = val; - /* Dram Timing Low (owns Clock Enable bits) */ - NewDramTimingLo = Get_NB32(dev, 0x88 + reg_off); - if (mctGet_NVbits(NV_AllMemClks) == 0) { - /*Special Jedec SPD diagnostic bit - "enable all clocks"*/ - if (!(pDCTstat->Status & (1<DIMMValidDCT[dct] & (1< Griffin format */ - /*FIXME - BurstLength32 must be 0 when F3x44[DramEccEn]=1. */ -/* - ; mov cx,PA_NBMISC+44h ;MCA NB Configuration - ; call Get_NB32n_D - ; bt eax,22 ;EccEn - ; .if (CARRY?) - ; btr eax,BurstLength32 - ; .endif -*/ - return val; -} - - -void mct_AdjustMemHoist_GR(struct DCTStatStruc *pDCTstat, u32 base, u32 HoleSize) -{ - u32 val; - if (base >= pDCTstat->DCTHoleBase) { - u32 dev = pDCTstat->dev_dct; - base += HoleSize; - base >>= 27 - 8; - val = Get_NB32(dev, 0x110); - val &= ~(0xfff<<11); - val |= (base & 0xfff)<<11; - Set_NB32(dev, 0x110, val); - } -} diff --git a/src/northbridge/amd/amdmct/mct/mcthdi.c b/src/northbridge/amd/amdmct/mct/mcthdi.c deleted file mode 100644 index b67282ef60..0000000000 --- a/src/northbridge/amd/amdmct/mct/mcthdi.c +++ /dev/null @@ -1,30 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include "mct_d.h" - -void mct_DramInit_Hw_D(struct MCTStatStruc *pMCTstat, - struct DCTStatStruc *pDCTstat, u8 dct) -{ - u32 val; - u32 reg; - u32 dev = pDCTstat->dev_dct; - - /*flag for selecting HW/SW DRAM Init HW DRAM Init */ - reg = 0x90 + 0x100 * dct; /*DRAM Configuration Low */ - val = Get_NB32(dev, reg); - val |= (1< -#include - -static void SetMTRRrangeWB_D(u32 Base, u32 *pLimit, u32 *pMtrrAddr); -static void SetMTRRrange_D(u32 Base, u32 *pLimit, u32 *pMtrrAddr, u16 MtrrType); - -void CPUMemTyping_D(struct MCTStatStruc *pMCTstat, - struct DCTStatStruc *pDCTstatA) -{ - /* BSP only. Set the fixed MTRRs for common legacy ranges. - * Set TOP_MEM and TOM2. - * Set some variable MTRRs with WB Uncacheable type. - */ - - u32 Bottom32bIO, Bottom40bIO, Cache32bTOP; - u32 val; - u32 addr; - u32 lo, hi; - - /* Set temporary top of memory from Node structure data. - * Adjust temp top of memory down to accommodate 32-bit IO space. - * Bottom40bIO = top of memory, right justified 8 bits - * (defines dram versus IO space type) - * Bottom32bIO = sub 4GB top of memory, right justified 8 bits - * (defines dram versus IO space type) - * Cache32bTOP = sub 4GB top of WB cacheable memory, - * right justified 8 bits - */ - - val = mctGet_NVbits(NV_BottomIO); - if (val == 0) - val++; - - Bottom32bIO = val << (24-8); - - val = pMCTstat->SysLimit + 1; - if (val <= _4GB_RJ8) { - Bottom40bIO = 0; - if (Bottom32bIO >= val) - Bottom32bIO = val; - } else { - Bottom40bIO = val; - } - - Cache32bTOP = Bottom32bIO; - - /*====================================================================== - Set default values for CPU registers - ======================================================================*/ - - /* NOTE : For coreboot, we don't need to set mtrr enables here because - they are still enable from cache_as_ram.inc */ - - addr = MTRR_FIX_64K_00000; - lo = 0x1E1E1E1E; - hi = lo; - _WRMSR(addr, lo, hi); /* 0 - 512K = WB Mem */ - addr = MTRR_FIX_16K_80000; - _WRMSR(addr, lo, hi); /* 512K - 640K = WB Mem */ - - /*====================================================================== - Set variable MTRR values - ======================================================================*/ - /* NOTE: for coreboot change from 0x200 to 0x204: coreboot is using - 0x200, 0x201 for [1M, CONFIG_TOP_MEM) - 0x202, 0x203 for ROM Caching - */ - addr = MTRR_PHYS_BASE(2); /* MTRR phys base 2*/ - /* use TOP_MEM as limit*/ - /* Limit = TOP_MEM|TOM2*/ - /* Base = 0*/ - print_tx("\t CPUMemTyping: Cache32bTOP:", Cache32bTOP); - SetMTRRrangeWB_D(0, &Cache32bTOP, &addr); - /* Base */ - /* Limit */ - /* MtrrAddr */ - if (addr == -1) /* ran out of MTRRs?*/ - pMCTstat->GStatus |= 1<Sub4GCacheTop = Cache32bTOP<<8; - - /*====================================================================== - Set TOP_MEM and TOM2 CPU registers - ======================================================================*/ - addr = TOP_MEM; - lo = Bottom32bIO<<8; - hi = Bottom32bIO>>24; - _WRMSR(addr, lo, hi); - print_tx("\t CPUMemTyping: Bottom32bIO:", Bottom32bIO); - print_tx("\t CPUMemTyping: Bottom40bIO:", Bottom40bIO); - if (Bottom40bIO) { - hi = Bottom40bIO >> 24; - lo = Bottom40bIO << 8; - if (mctSetNodeBoundary_D()) - lo &= 0xC0000000; - addr += 3; /* TOM2 */ - _WRMSR(addr, lo, hi); - } - addr = SYSCFG_MSR; /* SYS_CFG */ - _RDMSR(addr, &lo, &hi); - if (Bottom40bIO) { - lo |= SYSCFG_MSR_TOM2En; /* MtrrTom2En = 1 */ - lo |= SYSCFG_MSR_TOM2WB; /* Tom2ForceMemTypeWB */ - } else { - lo &= ~SYSCFG_MSR_TOM2En; /* MtrrTom2En = 0 */ - lo &= ~SYSCFG_MSR_TOM2WB; /* Tom2ForceMemTypeWB */ - } - _WRMSR(addr, lo, hi); -} - - -static void SetMTRRrangeWB_D(u32 Base, u32 *pLimit, u32 *pMtrrAddr) -{ - /*set WB type*/ - SetMTRRrange_D(Base, pLimit, pMtrrAddr, 6); -} - - -static void SetMTRRrange_D(u32 Base, u32 *pLimit, u32 *pMtrrAddr, u16 MtrrType) -{ - /* Program MTRRs to describe given range as given cache type. - * Use MTRR pairs starting with the given MTRRphys Base address, - * and use as many as is required up to (excluding) MSR 020C, which - * is reserved for OS. - * - * "Limit" in the context of this procedure is not the numerically - * correct limit, but rather the Last address+1, for purposes of coding - * efficiency and readability. Size of a region is then Limit-Base. - * - * 1. Size of each range must be a power of two - * 2. Each range must be naturally aligned (Base is same as size) - * - * There are two code paths: the ascending path and descending path - * (analogous to bsf and bsr), where the next limit is a function of the - * next set bit in a forward or backward sequence of bits (as a function - * of the Limit). We start with the ascending path, to ensure that - * regions are naturally aligned, then we switch to the descending path - * to maximize MTRR usage efficiency. Base = 0 is a special case where we - * start with the descending path. Correct Mask for region is - * 2comp(Size-1)-1, which is 2comp(Limit-Base-1)-1 - */ - - u32 curBase, curLimit, curSize; - u32 val, valx; - u32 addr; - - val = curBase = Base; - curLimit = *pLimit; - addr = *pMtrrAddr; - while ((addr >= 0x200) && (addr < 0x20C) && (val < *pLimit)) { - /* start with "ascending" code path */ - /* alignment (largest block size)*/ - valx = 1 << bsf(curBase); - curSize = valx; - - /* largest legal limit, given current non-zero range Base*/ - valx += curBase; - if ((curBase == 0) || (*pLimit < valx)) { - /* flop direction to "descending" code path*/ - valx = 1<>24; - val <<= 8; - - /* now program the MTRR */ - val |= MtrrType; /* set cache type (UC or WB)*/ - _WRMSR(addr, val, valx); /* prog. MTRR with current region Base*/ - val = ((~(curSize - 1))+1) - 1; /* Size-1*/ /*Mask = 2comp(Size-1)-1*/ - valx = (val >> 24) | (0xff00); /* GH have 48 bits addr */ - val <<= 8; - val |= (1 << 11); /* set MTRR valid*/ - addr++; - _WRMSR(addr, val, valx); /* prog. MTRR with current region Mask*/ - val = curLimit; - curBase = val; /* next Base = current Limit (loop exit)*/ - addr++; /* next MTRR pair addr */ - } - if (val < *pLimit) { - *pLimit = val; - addr = -1; - } - *pMtrrAddr = addr; -} - -void UMAMemTyping_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstatA) -{ -/* UMA memory size may need splitting the MTRR configuration into two - Before training use NB_BottomIO or the physical memory size to set the MTRRs. - After training, add UMAMemTyping function to reconfigure the MTRRs based on - NV_BottomUMA (for UMA systems only). - This two-step process allows all memory to be cached for training -*/ - u32 Bottom32bIO, Cache32bTOP; - u32 val; - u32 addr; - u32 lo, hi; - - /*====================================================================== - * Adjust temp top of memory down to accommodate UMA memory start - *======================================================================*/ - /* Bottom32bIO = sub 4GB top of memory, right justified 8 bits - * (defines dram versus IO space type) - * Cache32bTOP = sub 4GB top of WB cacheable memory, right justified 8 bits */ - - Bottom32bIO = pMCTstat->Sub4GCacheTop >> 8; - - val = mctGet_NVbits(NV_BottomUMA); - if (val == 0) - val++; - - val <<= (24-8); - if (val < Bottom32bIO) { - Cache32bTOP = val; - pMCTstat->Sub4GCacheTop = val; - - /*====================================================================== - * Clear variable MTRR values - *======================================================================*/ - addr = MTRR_PHYS_BASE(0); - lo = 0; - hi = lo; - while (addr < MTRR_PHYS_BASE(6)) { - _WRMSR(addr, lo, hi); /* prog. MTRR with current region Mask */ - addr++; /* next MTRR pair addr */ - } - - /*====================================================================== - * Set variable MTRR values - *======================================================================*/ - print_tx("\t UMAMemTyping_D: Cache32bTOP:", Cache32bTOP); - SetMTRRrangeWB_D(0, &Cache32bTOP, &addr); - if (addr == -1) /* ran out of MTRRs?*/ - pMCTstat->GStatus |= 1<, Raptor Engineering - * Copyright (C) 2007 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include "mct_d.h" - -void InterleaveNodes_D(struct MCTStatStruc *pMCTstat, - struct DCTStatStruc *pDCTstatA) -{ - - /* Applies Node memory interleaving if enabled and if all criteria are met. */ - u8 Node; - u32 Base; - u32 MemSize, MemSize0 = 0; - u32 Dct0MemSize = 0, DctSelBase, DctSelBaseOffset = 0; - u8 Nodes; - u8 NodesWmem; - u8 DoIntlv; - u8 _NdIntCap; - u8 _SWHole; - u32 HWHoleSz; - u32 DramHoleAddrReg; - u32 HoleBase; - u32 dev0; - u32 reg0; - u32 val; - u8 i; - struct DCTStatStruc *pDCTstat; - - DoIntlv = mctGet_NVbits(NV_NodeIntlv); - - _NdIntCap = 0; - HWHoleSz = 0; /*For HW remapping, NOT Node hoisting. */ - - pDCTstat = pDCTstatA + 0; - dev0 = pDCTstat->dev_host; - Nodes = ((Get_NB32(dev0, 0x60) >> 4) & 0x7) + 1; - - - dev0 = pDCTstat->dev_map; - reg0 = 0x40; - - NodesWmem = 0; - Node = 0; - - while (DoIntlv && (Node < Nodes)) { - pDCTstat = pDCTstatA + Node; - if (pMCTstat->GStatus & (1 << GSB_SpIntRemapHole)) { - pMCTstat->GStatus |= 1 << GSB_HWHole; - _SWHole = 0; - } else if (pDCTstat->Status & (1 << SB_SWNodeHole)) { - _SWHole = 1; - } else { - _SWHole = 0; - } - - if (!_SWHole) { - Base = Get_NB32(dev0, reg0); - if (Base & 1) { - NodesWmem++; - Base &= 0xFFFF0000; /* Base[39:8] */ - - if (pDCTstat->Status & (1 << SB_HWHole)) { - - /* to get true amount of dram, - * subtract out memory hole if HW dram remapping */ - DramHoleAddrReg = Get_NB32(pDCTstat->dev_map, 0xF0); - HWHoleSz = DramHoleAddrReg >> 16; - HWHoleSz = (((~HWHoleSz) + 1) & 0xFF); - HWHoleSz <<= 24-8; - } - /* check to see if the amount of memory on each channel - * are the same on all nodes */ - - DctSelBase = Get_NB32(pDCTstat->dev_dct, 0x114); - if (DctSelBase) { - DctSelBase <<= 8; - if (pDCTstat->Status & (1 << SB_HWHole)) { - if (DctSelBase >= 0x1000000) { - DctSelBase -= HWHoleSz; - } - } - DctSelBaseOffset -= Base; - if (Node == 0) { - Dct0MemSize = DctSelBase; - } else if (DctSelBase != Dct0MemSize) { - break; - } - } - - MemSize = Get_NB32(dev0, reg0 + 4); - MemSize &= 0xFFFF0000; - MemSize += 0x00010000; - MemSize -= Base; - if (pDCTstat->Status & (1 << SB_HWHole)) { - MemSize -= HWHoleSz; - } - if (Node == 0) { - MemSize0 = MemSize; - } else if (MemSize0 != MemSize) { - break; - } - } else { - break; - } - } else { - break; - } - Node++; - reg0 += 8; - } - - if (Node == Nodes) { - /* if all nodes have memory and no Node had SW memhole */ - if (Nodes == 2 || Nodes == 4 || Nodes == 8) - _NdIntCap = 1; - } - - if (!_NdIntCap) - DoIntlv = 0; - - - if (pMCTstat->GStatus & 1 << (GSB_SpIntRemapHole)) { - HWHoleSz = pMCTstat->HoleBase; - if (HWHoleSz == 0) { - HWHoleSz = mctGet_NVbits(NV_BottomIO) & 0xFF; - HWHoleSz <<= 24-8; - } - HWHoleSz = ((~HWHoleSz) + 1) & 0x00FF0000; - } - - if (DoIntlv) { - MCTMemClr_D(pMCTstat,pDCTstatA); - /* Program Interleaving enabled on Node 0 map only.*/ - MemSize0 <<= bsf(Nodes); /* MemSize = MemSize*2 (or 4, or 8) */ - Dct0MemSize <<= bsf(Nodes); - MemSize0 += HWHoleSz; - Base = ((Nodes - 1) << 8) | 3; - reg0 = 0x40; - Node = 0; - while (Node < Nodes) { - Set_NB32(dev0, reg0, Base); - MemSize = MemSize0; - MemSize--; - MemSize &= 0xFFFF0000; - MemSize |= Node << 8; /* set IntlvSel[2:0] field */ - MemSize |= Node; /* set DstNode[2:0] field */ - Set_NB32(dev0, reg0 + 4, MemSize0); - reg0 += 8; - Node++; - } - - /* set base/limit to F1x120/124 per Node */ - Node = 0; - while (Node < Nodes) { - pDCTstat = pDCTstatA + Node; - pDCTstat->NodeSysBase = 0; - MemSize = MemSize0; - MemSize -= HWHoleSz; - MemSize--; - pDCTstat->NodeSysLimit = MemSize; - Set_NB32(pDCTstat->dev_map, 0x120, Node << 21); - MemSize = MemSize0; - MemSize--; - MemSize >>= 19; - val = Base; - val &= 0x700; - val <<= 13; - val |= MemSize; - Set_NB32(pDCTstat->dev_map, 0x124, val); - - if (pMCTstat->GStatus & (1 << GSB_HWHole)) { - HoleBase = pMCTstat->HoleBase; - if (Dct0MemSize >= HoleBase) { - val = HWHoleSz; - if (Node == 0) { - val += Dct0MemSize; - } - } else { - val = HWHoleSz + Dct0MemSize; - } - - val >>= 8; /* DramHoleOffset */ - HoleBase <<= 8; /* DramHoleBase */ - val |= HoleBase; - val |= 1 << DramMemHoistValid; - val |= 1 << DramHoleValid; - Set_NB32(pDCTstat->dev_map, 0xF0, val); - } - - - Set_NB32(pDCTstat->dev_dct, 0x114, Dct0MemSize >> 8); /* DctSelBaseOffset */ - val = Get_NB32(pDCTstat->dev_dct, 0x110); - val &= 0x7FF; - val |= Dct0MemSize >> 8; - Set_NB32(pDCTstat->dev_dct, 0x110, val); /* DctSelBaseAddr */ - print_tx("InterleaveNodes: DRAM Controller Select Low Register = ", val); - Node++; - } - - - /* Copy Node 0 into other Nodes' CSRs */ - Node = 1; - while (Node < Nodes) { - pDCTstat = pDCTstatA + Node; - - for (i = 0x40; i <= 0x80; i++) { - val = Get_NB32(dev0, i); - Set_NB32(pDCTstat->dev_map, i, val); - } - - val = Get_NB32(dev0, 0xF0); - Set_NB32(pDCTstat->dev_map, 0xF0, val); - Node++; - } - pMCTstat->GStatus = (1 << GSB_NodeIntlv); - } - print_tx("InterleaveNodes_D: Status ", pDCTstat->Status); - print_tx("InterleaveNodes_D: ErrStatus ", pDCTstat->ErrStatus); - print_tx("InterleaveNodes_D: ErrCode ", pDCTstat->ErrCode); - print_t("InterleaveNodes_D: Done\n"); -} diff --git a/src/northbridge/amd/amdmct/mct/mctpro_d.c b/src/northbridge/amd/amdmct/mct/mctpro_d.c deleted file mode 100644 index 83937330f8..0000000000 --- a/src/northbridge/amd/amdmct/mct/mctpro_d.c +++ /dev/null @@ -1,396 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007 Advanced Micro Devices, Inc. - * Copyright (C) 2015 Timothy Pearson , Raptor Engineering - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include "mct_d.h" - -void EarlySampleSupport_D(void) -{ -} - -u32 procOdtWorkaround(struct DCTStatStruc *pDCTstat, u32 dct, u32 val) -{ - uint64_t tmp; - tmp = pDCTstat->LogicalCPUID; - if ((tmp == AMD_DR_A0A) || (tmp == AMD_DR_A1B) || (tmp == AMD_DR_A2)) { - val &= 0x0FFFFFFF; - if (pDCTstat->MAdimms[dct] > 1) - val |= 0x10000000; - } - - return val; -} - - -u32 OtherTiming_A_D(struct DCTStatStruc *pDCTstat, u32 val) -{ - /* Bug#10695:One MEMCLK Bubble Writes Don't Do X4 X8 Switching Correctly - * Solution: BIOS should set DRAM Timing High[Twrwr] > 00b - * (F2x[1, 0]8C[1:0] > 00b). Silicon Status: Fixed in Rev B - * FIXME: check if this is still required. - */ - uint64_t tmp; - tmp = pDCTstat->LogicalCPUID; - if ((tmp == AMD_DR_A0A) || (tmp == AMD_DR_A1B) || (tmp == AMD_DR_A2)) { - if (!(val & (3<<12))) - val |= 1<<12; - } - return val; -} - - -void mct_ForceAutoPrecharge_D(struct DCTStatStruc *pDCTstat, u32 dct) -{ - uint64_t tmp; - u32 reg; - u32 reg_off; - u32 dev; - u32 val; - - tmp = pDCTstat->LogicalCPUID; - if ((tmp == AMD_DR_A0A) || (tmp == AMD_DR_A1B) || (tmp == AMD_DR_A2)) { - if (CheckNBCOFAutoPrechg(pDCTstat, dct)) { - dev = pDCTstat->dev_dct; - reg_off = 0x100 * dct; - reg = 0x90 + reg_off; /* Dram Configuration Lo */ - val = Get_NB32(dev, reg); - val |= 1<GangedMode) - val |= 1<NodePresent) break; - - tmp = pDCTstat->LogicalCPUID; - if ((tmp == AMD_DR_A0A) || (tmp == AMD_DR_A1B) || (tmp == AMD_DR_A2)) { - dev = pDCTstat->dev_dct; - reg = 0x11c; - val = Get_NB32(dev, reg); - val &= ~(1<LogicalCPUID; - if ((tmp == AMD_DR_A0A) || (tmp == AMD_DR_A1B) || (tmp == AMD_DR_A2)) { - - dev = pDCTstat->dev_dct; - index = 0; - - for (Channel = 0; Channel < 2; Channel++) { - index_reg = 0x98 + 0x100 * Channel; - val = Get_NB32_index_wait(dev, index_reg, 0x0d004007); - val |= 0x3ff; - Set_NB32_index_wait(dev, index_reg, 0x0d0f4f07, val); - } - - for (Channel = 0; Channel < 2; Channel++) { - if (pDCTstat->GangedMode && Channel) - break; - reg_off = 0x100 * Channel; - reg = 0x78 + reg_off; - val = Get_NB32(dev, reg); - val &= ~(0x07); - val |= 5; - Set_NB32(dev, reg, val); - } - - for (Channel = 0; Channel < 2; Channel++) { - reg_off = 0x100 * Channel; - val = 0; - index_reg = 0x98 + reg_off; - for (index = 0x30; index < (0x45 + 1); index++) { - Set_NB32_index_wait(dev, index_reg, index, val); - } - } - - } -} - - -u32 Modify_D3CMP(struct DCTStatStruc *pDCTstat, u32 dct, u32 value) -{ - /* Errata#189: Reads To Phy Driver Calibration Register and Phy - * Predriver Calibration Register Do Not Return Bit 27. - * Solution: See #41322 for details. - * BIOS can modify bit 27 of the Phy Driver Calibration register - * as follows: - * 1. Read F2x[1, 0]9C_x09 - * 2. Read F2x[1, 0]9C_x0D004201 - * 3. Set F2x[1, 0]9C_x09[27] = F2x[1, 0]9C_x0D004201[10] - * BIOS can modify bit 27 of the Phy Predriver Calibration register - * as follows: - * 1. Read F2x[1, 0]9C_x0A - * 2. Read F2x[1, 0]9C_x0D004209 - * 3. Set F2x[1, 0]9C_x0A[27] = F2x[1, 0]9C_x0D004209[10] - * Silicon Status: Fixed planned for DR-B0 - */ - - u32 dev; - u32 index_reg; - u32 index; - u32 val; - uint64_t tmp; - - tmp = pDCTstat->LogicalCPUID; - if ((tmp == AMD_DR_A0A) || (tmp == AMD_DR_A1B) || (tmp == AMD_DR_A2)) { - dev = pDCTstat->dev_dct; - index_reg = 0x98 + 0x100 * dct; - index = 0x0D004201; - val = Get_NB32_index_wait(dev, index_reg, index); - value &= ~(1<<27); - value |= ((val >> 10) & 1) << 27; - } - return value; -} - - -void SyncSetting(struct DCTStatStruc *pDCTstat) -{ - /* Errata#198: AddrCmdSetup, CsOdtSetup, and CkeSetup Require Identical - * Programming For Both Channels in Ganged Mode - * Solution: The BIOS must program the following DRAM timing parameters - * the same for both channels: - * 1. F2x[1, 0]9C_x04[21] (AddrCmdSetup) - * 2. F2x[1, 0]9C_x04[15] (CsOdtSetup) - * 3. F2x[1, 0]9C_x04[5]) (CkeSetup) - * That is, if the AddrCmdSetup, CsOdtSetup, or CkeSetup is - * set to 1'b1 for one of the controllers, then the corresponding - * AddrCmdSetup, CsOdtSetup, or CkeSetup must be set to 1'b1 for the - * other controller. - * Silicon Status: Fix TBD - */ - - uint64_t tmp; - tmp = pDCTstat->LogicalCPUID; - if ((tmp == AMD_DR_A0A) || (tmp == AMD_DR_A1B) || (tmp == AMD_DR_A2)) { - pDCTstat->CH_ODC_CTL[1] = pDCTstat->CH_ODC_CTL[0]; - pDCTstat->CH_ADDR_TMG[1] = pDCTstat->CH_ADDR_TMG[0]; - } -} - - -u32 CheckNBCOFAutoPrechg(struct DCTStatStruc *pDCTstat, u32 dct) -{ - u32 ret = 0; - u32 lo, hi; - u32 msr; - u32 val; - u32 valx, valy; - u32 NbDid; - - /* 3 * (Fn2xD4[NBFid]+4)/(2^NbDid)/(3+Fn2x94[MemClkFreq]) */ - msr = 0xC0010071; - _RDMSR(msr, &lo, &hi); - NbDid = (lo >> 22) & 1; - - val = Get_NB32(pDCTstat->dev_dct, 0x94 + 0x100 * dct); - valx = ((val & 0x07) + 3) << NbDid; - print_tx("MemClk:", valx >> NbDid); - - val = Get_NB32(pDCTstat->dev_nbmisc, 0xd4); - valy = ((val & 0x1f) + 4) * 3; - print_tx("NB COF:", valy >> NbDid); - - val = valy/valx; - if ((val == 3) && (valy % valx)) /* 3 < NClk/MemClk < 4 */ - ret = 1; - - return ret; -} - - -void mct_BeforeDramInit_D(struct DCTStatStruc *pDCTstat, u32 dct) -{ - uint64_t tmp; - u32 Speed; - u32 ch, ch_start, ch_end; - u32 index_reg; - u32 dev; - u32 val; - - tmp = pDCTstat->LogicalCPUID; - if ((tmp == AMD_DR_A0A) || (tmp == AMD_DR_A1B) || (tmp == AMD_DR_A2)) { - Speed = pDCTstat->Speed; - /* MemClkFreq = 333MHz or 533MHz */ - if ((Speed == 3) || (Speed == 2)) { - if (pDCTstat->GangedMode) { - ch_start = 0; - ch_end = 2; - } else { - ch_start = dct; - ch_end = dct+1; - } - dev = pDCTstat->dev_dct; - - for (ch = ch_start; ch < ch_end; ch++) { - index_reg = 0x98 + 0x100 * ch; - val = Get_NB32_index(dev, index_reg, 0x0D00E001); - val &= ~(0xf0); - val |= 0x80; - Set_NB32_index(dev, index_reg, 0x0D01E001, val); - } - } - - } -} - -#ifdef UNUSED_CODE -/* Callback not required */ -static u8 mct_AdjustDelay_D(struct DCTStatStruc *pDCTstat, u8 dly) -{ - u8 skip = 0; - dly &= 0x1f; - if ((dly >= MIN_FENCE) && (dly <= MAX_FENCE)) - skip = 1; - - return skip; -} -#endif - -u8 mct_checkFenceHoleAdjust_D(struct MCTStatStruc *pMCTstat, - struct DCTStatStruc *pDCTstat, u8 DQSDelay, - u8 ChipSel, u8 *result) -{ - u8 ByteLane; - uint64_t tmp; - - tmp = pDCTstat->LogicalCPUID; - if ((tmp == AMD_DR_A0A) || (tmp == AMD_DR_A1B) || (tmp == AMD_DR_A2)) { - if (pDCTstat->Direction == DQS_WRITEDIR) { - if ((pDCTstat->Speed == 2) || (pDCTstat->Speed == 3)) { - if (DQSDelay == 13) { - if (*result == 0xFF) { - for (ByteLane = 0; ByteLane < 8; ByteLane++) { - pDCTstat->DQSDelay = 13; - pDCTstat->ByteLane = ByteLane; - /* store the value into the data structure */ - StoreDQSDatStrucVal_D(pMCTstat, pDCTstat, ChipSel); - } - return 1; - } - } - } - if (mct_AdjustDQSPosDelay_D(pDCTstat, DQSDelay)) { - *result = 0; - } - } - } - return 0; -} - - -u8 mct_AdjustDQSPosDelay_D(struct DCTStatStruc *pDCTstat, u8 dly) -{ - u8 skip = 0; - - dly &= 0x1f; - if ((dly >= MIN_DQS_WR_FENCE) && (dly <= MAX_DQS_WR_FENCE)) - skip = 1; - - return skip; - -} - -#ifdef UNUSED_CODE -static u8 mctDoAxRdPtrInit_D(struct DCTStatStruc *pDCTstat, u8 *Rdtr) -{ - u32 tmp; - - tmp = pDCTstat->LogicalCPUID; - if ((tmp == AMD_DR_A0A) || (tmp == AMD_DR_A1B) || (tmp == AMD_DR_A2)) { - *Rdtr = 5; - return 1; - } - return 0; -} -#endif - -void mct_AdjustScrub_D(struct DCTStatStruc *pDCTstat, u16 *scrub_request) { - - /* Erratum #202: disable DCache scrubber for Ax parts */ - - if (pDCTstat->LogicalCPUID & (AMD_DR_Ax)) { - *scrub_request = 0; - pDCTstat->ErrStatus |= 1 << SB_DCBKScrubDis; - } -} - -void beforeInterleaveChannels_D(struct DCTStatStruc *pDCTstatA, u8 *enabled) { - if (pDCTstatA->LogicalCPUID & (AMD_DR_Ax)) - *enabled = 0; -} diff --git a/src/northbridge/amd/amdmct/mct/mctsrc.c b/src/northbridge/amd/amdmct/mct/mctsrc.c deleted file mode 100644 index 406547e0f8..0000000000 --- a/src/northbridge/amd/amdmct/mct/mctsrc.c +++ /dev/null @@ -1,1090 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007-2008 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include - -#include "mct_d.h" - -/****************************************************************************** - Description: Receiver En and DQS Timing Training feature for DDR 2 MCT -******************************************************************************/ - -static void dqsTrainRcvrEn_SW(struct MCTStatStruc *pMCTstat, - struct DCTStatStruc *pDCTstat, u8 Pass); -static u8 mct_SavePassRcvEnDly_D(struct DCTStatStruc *pDCTstat, - u8 rcvrEnDly, u8 Channel, - u8 receiver, u8 Pass); -static u8 mct_CompareTestPatternQW0_D(struct MCTStatStruc *pMCTstat, - struct DCTStatStruc *pDCTstat, - u32 addr, u8 channel, - u8 pattern, u8 Pass); -static void mct_InitDQSPos4RcvrEn_D(struct MCTStatStruc *pMCTstat, - struct DCTStatStruc *pDCTstat); -static void InitDQSPos4RcvrEn_D(struct MCTStatStruc *pMCTstat, - struct DCTStatStruc *pDCTstat, u8 Channel); -static void CalcEccDQSRcvrEn_D(struct MCTStatStruc *pMCTstat, - struct DCTStatStruc *pDCTstat, u8 Channel); -static void mct_SetFinalRcvrEnDly_D(struct DCTStatStruc *pDCTstat, - u8 RcvrEnDly, u8 where, - u8 Channel, u8 Receiver, - u32 dev, u32 index_reg, - u8 Addl_Index, u8 Pass); -static void mct_SetMaxLatency_D(struct DCTStatStruc *pDCTstat, u8 Channel, u8 DQSRcvEnDly); -static void fenceDynTraining_D(struct MCTStatStruc *pMCTstat, - struct DCTStatStruc *pDCTstat, u8 dct); -static void mct_DisableDQSRcvEn_D(struct DCTStatStruc *pDCTstat); - -/* Warning: These must be located so they do not cross a logical 16-bit - segment boundary! */ -const u32 TestPattern0_D[] = { - 0xaaaaaaaa, 0xaaaaaaaa, 0xaaaaaaaa, 0xaaaaaaaa, - 0xaaaaaaaa, 0xaaaaaaaa, 0xaaaaaaaa, 0xaaaaaaaa, - 0xaaaaaaaa, 0xaaaaaaaa, 0xaaaaaaaa, 0xaaaaaaaa, - 0xaaaaaaaa, 0xaaaaaaaa, 0xaaaaaaaa, 0xaaaaaaaa, -}; -const u32 TestPattern1_D[] = { - 0x55555555, 0x55555555, 0x55555555, 0x55555555, - 0x55555555, 0x55555555, 0x55555555, 0x55555555, - 0x55555555, 0x55555555, 0x55555555, 0x55555555, - 0x55555555, 0x55555555, 0x55555555, 0x55555555, -}; -const u32 TestPattern2_D[] = { - 0x12345678, 0x87654321, 0x23456789, 0x98765432, - 0x59385824, 0x30496724, 0x24490795, 0x99938733, - 0x40385642, 0x38465245, 0x29432163, 0x05067894, - 0x12349045, 0x98723467, 0x12387634, 0x34587623, -}; - -static void SetupRcvrPattern(struct MCTStatStruc *pMCTstat, - struct DCTStatStruc *pDCTstat, u32 *buffer, u8 pass) -{ - /* - * 1. Copy the alpha and Beta patterns from ROM to Cache, - * aligning on 16 byte boundary - * 2. Set the ptr to DCTStatstruc.PtrPatternBufA for Alpha - * 3. Set the ptr to DCTStatstruc.PtrPatternBufB for Beta - */ - - u32 *buf_a; - u32 *buf_b; - u32 *p_A; - u32 *p_B; - u8 i; - - buf_a = (u32 *)(((u32)buffer + 0x10) & (0xfffffff0)); - buf_b = buf_a + 32; //?? - p_A = (u32 *)SetupDqsPattern_1PassB(pass); - p_B = (u32 *)SetupDqsPattern_1PassA(pass); - - for (i = 0; i < 16; i++) { - buf_a[i] = p_A[i]; - buf_b[i] = p_B[i]; - } - - pDCTstat->PtrPatternBufA = (u32)buf_a; - pDCTstat->PtrPatternBufB = (u32)buf_b; -} - - -void mct_TrainRcvrEn_D(struct MCTStatStruc *pMCTstat, - struct DCTStatStruc *pDCTstat, u8 Pass) -{ - if (mct_checkNumberOfDqsRcvEn_1Pass(Pass)) - dqsTrainRcvrEn_SW(pMCTstat, pDCTstat, Pass); -} - - -static void dqsTrainRcvrEn_SW(struct MCTStatStruc *pMCTstat, - struct DCTStatStruc *pDCTstat, u8 Pass) -{ - u8 Channel, RcvrEnDly, RcvrEnDlyRmin; - u8 Test0, Test1, CurrTest, CurrTestSide0, CurrTestSide1; - u8 CTLRMaxDelay, _2Ranks, PatternA, PatternB; - u8 Addl_Index = 0; - u8 Receiver; - u8 _DisableDramECC = 0, _Wrap32Dis = 0, _SSE2 = 0; - u8 RcvrEnDlyLimit, Final_Value, MaxDelay_CH[2]; - u32 TestAddr0, TestAddr1, TestAddr0B, TestAddr1B; - u32 PatternBuffer[64+4]; /* FIXME: need increase 8? */ - u32 Errors; - - u32 val; - u32 reg; - u32 dev; - u32 index_reg; - u32 ch_start, ch_end, ch; - u32 msr; - CRx_TYPE cr4; - u32 lo, hi; - - u8 valid; - u32 tmp; - u8 LastTest; - - print_debug_dqs("\nTrainRcvEn: Node", pDCTstat->Node_ID, 0); - print_debug_dqs("TrainRcvEn: Pass", Pass, 0); - - - dev = pDCTstat->dev_dct; - ch_start = 0; - if (!pDCTstat->GangedMode) { - ch_end = 2; - } else { - ch_end = 1; - } - - for (ch = ch_start; ch < ch_end; ch++) { - reg = 0x78 + (0x100 * ch); - val = Get_NB32(dev, reg); - val &= ~(0x3ff << 22); - val |= (0x0c8 << 22); /* Max Rd Lat */ - Set_NB32(dev, reg, val); - } - - Final_Value = 1; - if (Pass == FirstPass) { - mct_InitDQSPos4RcvrEn_D(pMCTstat, pDCTstat); - } else { - pDCTstat->DimmTrainFail = 0; - pDCTstat->CSTrainFail = ~pDCTstat->CSPresent; - } - print_t("TrainRcvrEn: 1\n"); - - cr4 = read_cr4(); - if (cr4 & (1 << 9)) { /* save the old value */ - _SSE2 = 1; - } - cr4 |= (1 << 9); /* OSFXSR enable SSE2 */ - write_cr4(cr4); - print_t("TrainRcvrEn: 2\n"); - - msr = HWCR_MSR; - _RDMSR(msr, &lo, &hi); - //FIXME: Why use SSEDIS - if (lo & (1 << 17)) { /* save the old value */ - _Wrap32Dis = 1; - } - lo |= (1 << 17); /* HWCR.wrap32dis */ - lo &= ~(1 << 15); /* SSEDIS */ - _WRMSR(msr, lo, hi); /* Setting wrap32dis allows 64-bit memory references in real mode */ - print_t("TrainRcvrEn: 3\n"); - - _DisableDramECC = mct_DisableDimmEccEn_D(pMCTstat, pDCTstat); - - - if (pDCTstat->Speed == 1) { - pDCTstat->T1000 = 5000; /* get the T1000 figure (cycle time (ns)*1K */ - } else if (pDCTstat->Speed == 2) { - pDCTstat->T1000 = 3759; - } else if (pDCTstat->Speed == 3) { - pDCTstat->T1000 = 3003; - } else if (pDCTstat->Speed == 4) { - pDCTstat->T1000 = 2500; - } else if (pDCTstat->Speed == 5) { - pDCTstat->T1000 = 1876; - } else { - pDCTstat->T1000 = 0; - } - - SetupRcvrPattern(pMCTstat, pDCTstat, PatternBuffer, Pass); - print_t("TrainRcvrEn: 4\n"); - - Errors = 0; - dev = pDCTstat->dev_dct; - CTLRMaxDelay = 0; - - for (Channel = 0; Channel < 2; Channel++) { - print_debug_dqs("\tTrainRcvEn51: Node ", pDCTstat->Node_ID, 1); - print_debug_dqs("\tTrainRcvEn51: Channel ", Channel, 1); - pDCTstat->Channel = Channel; - - MaxDelay_CH[Channel] = 0; - index_reg = 0x98 + 0x100 * Channel; - - Receiver = mct_InitReceiver_D(pDCTstat, Channel); - /* There are four receiver pairs, loosely associated with chipselects. */ - for (; Receiver < 8; Receiver += 2) { - Addl_Index = (Receiver >> 1) * 3 + 0x10; - LastTest = DQS_FAIL; - - /* mct_ModifyIndex_D */ - RcvrEnDlyRmin = RcvrEnDlyLimit = 0xff; - - print_debug_dqs("\t\tTrainRcvEnd52: index ", Addl_Index, 2); - - if (!mct_RcvrRankEnabled_D(pMCTstat, pDCTstat, Channel, Receiver)) { - print_t("\t\t\tRank not enabled_D\n"); - continue; - } - - TestAddr0 = mct_GetRcvrSysAddr_D(pMCTstat, pDCTstat, Channel, Receiver, &valid); - if (!valid) { /* Address not supported on current CS */ - print_t("\t\t\tAddress not supported on current CS\n"); - continue; - } - - TestAddr0B = TestAddr0 + (BigPagex8_RJ8 << 3); - - if (mct_RcvrRankEnabled_D(pMCTstat, pDCTstat, Channel, Receiver+1)) { - TestAddr1 = mct_GetRcvrSysAddr_D(pMCTstat, pDCTstat, Channel, Receiver+1, &valid); - if (!valid) { /* Address not supported on current CS */ - print_t("\t\t\tAddress not supported on current CS+1\n"); - continue; - } - TestAddr1B = TestAddr1 + (BigPagex8_RJ8 << 3); - _2Ranks = 1; - } else { - _2Ranks = TestAddr1 = TestAddr1B = 0; - } - - print_debug_dqs("\t\tTrainRcvEn53: TestAddr0 ", TestAddr0, 2); - print_debug_dqs("\t\tTrainRcvEn53: TestAddr0B ", TestAddr0B, 2); - print_debug_dqs("\t\tTrainRcvEn53: TestAddr1 ", TestAddr1, 2); - print_debug_dqs("\t\tTrainRcvEn53: TestAddr1B ", TestAddr1B, 2); - - /* - * Get starting RcvrEnDly value - */ - RcvrEnDly = mct_Get_Start_RcvrEnDly_1Pass(Pass); - - /* mct_GetInitFlag_D*/ - if (Pass == FirstPass) { - pDCTstat->DqsRcvEn_Pass = 0; - } else { - pDCTstat->DqsRcvEn_Pass = 0xFF; - } - pDCTstat->DqsRcvEn_Saved = 0; - - - while (RcvrEnDly < RcvrEnDlyLimit) { /* sweep Delay value here */ - print_debug_dqs("\t\t\tTrainRcvEn541: RcvrEnDly ", RcvrEnDly, 3); - - /* callback not required - if (mct_AdjustDelay_D(pDCTstat, RcvrEnDly)) - goto skipDly; - */ - - /* Odd steps get another pattern such that even - and odd steps alternate. The pointers to the - patterns will be swaped at the end of the loop - so that they correspond. */ - if (RcvrEnDly & 1) { - PatternA = 1; - PatternB = 0; - } else { - /* Even step */ - PatternA = 0; - PatternB = 1; - } - - mct_Write1LTestPattern_D(pMCTstat, pDCTstat, TestAddr0, PatternA); /* rank 0 of DIMM, testpattern 0 */ - mct_Write1LTestPattern_D(pMCTstat, pDCTstat, TestAddr0B, PatternB); /* rank 0 of DIMM, testpattern 1 */ - if (_2Ranks) { - mct_Write1LTestPattern_D(pMCTstat, pDCTstat, TestAddr1, PatternA); /*rank 1 of DIMM, testpattern 0 */ - mct_Write1LTestPattern_D(pMCTstat, pDCTstat, TestAddr1B, PatternB); /*rank 1 of DIMM, testpattern 1 */ - } - - mct_SetRcvrEnDly_D(pDCTstat, RcvrEnDly, 0, Channel, Receiver, dev, index_reg, Addl_Index, Pass); - - CurrTest = DQS_FAIL; - CurrTestSide0 = DQS_FAIL; - CurrTestSide1 = DQS_FAIL; - - mct_Read1LTestPattern_D(pMCTstat, pDCTstat, TestAddr0); /*cache fills */ - Test0 = mct_CompareTestPatternQW0_D(pMCTstat, pDCTstat, TestAddr0, Channel, PatternA, Pass);/* ROM vs cache compare */ - proc_IOCLFLUSH_D(TestAddr0); - ResetDCTWrPtr_D(dev, index_reg, Addl_Index); - - print_debug_dqs("\t\t\tTrainRcvEn542: Test0 result ", Test0, 3); - - // != 0x00 mean pass - - if (Test0 == DQS_PASS) { - mct_Read1LTestPattern_D(pMCTstat, pDCTstat, TestAddr0B); /*cache fills */ - /* ROM vs cache compare */ - Test1 = mct_CompareTestPatternQW0_D(pMCTstat, pDCTstat, TestAddr0B, Channel, PatternB, Pass); - proc_IOCLFLUSH_D(TestAddr0B); - ResetDCTWrPtr_D(dev, index_reg, Addl_Index); - - print_debug_dqs("\t\t\tTrainRcvEn543: Test1 result ", Test1, 3); - - if (Test1 == DQS_PASS) { - CurrTestSide0 = DQS_PASS; - } - } - if (_2Ranks) { - mct_Read1LTestPattern_D(pMCTstat, pDCTstat, TestAddr1); /*cache fills */ - /* ROM vs cache compare */ - Test0 = mct_CompareTestPatternQW0_D(pMCTstat, pDCTstat, TestAddr1, Channel, PatternA, Pass); - proc_IOCLFLUSH_D(TestAddr1); - ResetDCTWrPtr_D(dev, index_reg, Addl_Index); - - print_debug_dqs("\t\t\tTrainRcvEn544: Test0 result ", Test0, 3); - - if (Test0 == DQS_PASS) { - mct_Read1LTestPattern_D(pMCTstat, pDCTstat, TestAddr1B); /*cache fills */ - /* ROM vs cache compare */ - Test1 = mct_CompareTestPatternQW0_D(pMCTstat, pDCTstat, TestAddr1B, Channel, PatternB, Pass); - proc_IOCLFLUSH_D(TestAddr1B); - ResetDCTWrPtr_D(dev, index_reg, Addl_Index); - - print_debug_dqs("\t\t\tTrainRcvEn545: Test1 result ", Test1, 3); - if (Test1 == DQS_PASS) { - CurrTestSide1 = DQS_PASS; - } - } - } - - if (_2Ranks) { - if ((CurrTestSide0 == DQS_PASS) && (CurrTestSide1 == DQS_PASS)) { - CurrTest = DQS_PASS; - } - } else if (CurrTestSide0 == DQS_PASS) { - CurrTest = DQS_PASS; - } - - - /* record first pass DqsRcvEn to stack */ - valid = mct_SavePassRcvEnDly_D(pDCTstat, RcvrEnDly, Channel, Receiver, Pass); - - /* Break(1:RevF,2:DR) or not(0) FIXME: This comment deosn't make sense */ - if (valid == 2 || (LastTest == DQS_FAIL && valid == 1)) { - RcvrEnDlyRmin = RcvrEnDly; - break; - } - - LastTest = CurrTest; - - /* swap the rank 0 pointers */ - tmp = TestAddr0; - TestAddr0 = TestAddr0B; - TestAddr0B = tmp; - - /* swap the rank 1 pointers */ - tmp = TestAddr1; - TestAddr1 = TestAddr1B; - TestAddr1B = tmp; - - print_debug_dqs("\t\t\tTrainRcvEn56: RcvrEnDly ", RcvrEnDly, 3); - - RcvrEnDly++; - - } /* while RcvrEnDly */ - - print_debug_dqs("\t\tTrainRcvEn61: RcvrEnDly ", RcvrEnDly, 2); - print_debug_dqs("\t\tTrainRcvEn61: RcvrEnDlyRmin ", RcvrEnDlyRmin, 3); - print_debug_dqs("\t\tTrainRcvEn61: RcvrEnDlyLimit ", RcvrEnDlyLimit, 3); - if (RcvrEnDlyRmin == RcvrEnDlyLimit) { - /* no passing window */ - pDCTstat->ErrStatus |= 1 << SB_NORCVREN; - Errors |= 1 << SB_NORCVREN; - pDCTstat->ErrCode = SC_FatalErr; - } - - if (RcvrEnDly > (RcvrEnDlyLimit - 1)) { - /* passing window too narrow, too far delayed*/ - pDCTstat->ErrStatus |= 1 << SB_SmallRCVR; - Errors |= 1 << SB_SmallRCVR; - pDCTstat->ErrCode = SC_FatalErr; - RcvrEnDly = RcvrEnDlyLimit - 1; - pDCTstat->CSTrainFail |= 1 << Receiver; - pDCTstat->DimmTrainFail |= 1 << (Receiver + Channel); - } - - // CHB_D0_B0_RCVRDLY set in mct_Average_RcvrEnDly_Pass - mct_Average_RcvrEnDly_Pass(pDCTstat, RcvrEnDly, RcvrEnDlyLimit, Channel, Receiver, Pass); - - mct_SetFinalRcvrEnDly_D(pDCTstat, RcvrEnDly, Final_Value, Channel, Receiver, dev, index_reg, Addl_Index, Pass); - - if (pDCTstat->ErrStatus & (1 << SB_SmallRCVR)) { - Errors |= 1 << SB_SmallRCVR; - } - - RcvrEnDly += Pass1MemClkDly; - if (RcvrEnDly > CTLRMaxDelay) { - CTLRMaxDelay = RcvrEnDly; - } - - } /* while Receiver */ - - MaxDelay_CH[Channel] = CTLRMaxDelay; - } /* for Channel */ - - CTLRMaxDelay = MaxDelay_CH[0]; - if (MaxDelay_CH[1] > CTLRMaxDelay) - CTLRMaxDelay = MaxDelay_CH[1]; - - for (Channel = 0; Channel < 2; Channel++) { - mct_SetMaxLatency_D(pDCTstat, Channel, CTLRMaxDelay); /* program Ch A/B MaxAsyncLat to correspond with max delay */ - } - - ResetDCTWrPtr_D(dev, index_reg, Addl_Index); - - if (_DisableDramECC) { - mct_EnableDimmEccEn_D(pMCTstat, pDCTstat, _DisableDramECC); - } - - if (Pass == FirstPass) { - /*Disable DQSRcvrEn training mode */ - print_t("TrainRcvrEn: mct_DisableDQSRcvEn_D\n"); - mct_DisableDQSRcvEn_D(pDCTstat); - } - - if (!_Wrap32Dis) { - msr = HWCR_MSR; - _RDMSR(msr, &lo, &hi); - lo &= ~(1<<17); /* restore HWCR.wrap32dis */ - _WRMSR(msr, lo, hi); - } - if (!_SSE2) { - cr4 = read_cr4(); - cr4 &= ~(1<<9); /* restore cr4.OSFXSR */ - write_cr4(cr4); - } - -#if DQS_TRAIN_DEBUG > 0 - { - u8 Channel; - printk(BIOS_DEBUG, "TrainRcvrEn: CH_MaxRdLat:\n"); - for (Channel = 0; Channel < 2; Channel++) { - printk(BIOS_DEBUG, "Channel: %02x: %02x\n", Channel, pDCTstat->CH_MaxRdLat[Channel]); - } - } -#endif - -#if DQS_TRAIN_DEBUG > 0 - { - u8 val; - u8 Channel, Receiver; - u8 i; - u8 *p; - - printk(BIOS_DEBUG, "TrainRcvrEn: CH_D_B_RCVRDLY:\n"); - for (Channel = 0; Channel < 2; Channel++) { - printk(BIOS_DEBUG, "Channel: %02x\n", Channel); - for (Receiver = 0; Receiver < 8; Receiver+=2) { - printk(BIOS_DEBUG, "\t\tReceiver: %02x: ", Receiver); - p = pDCTstat->persistentData.CH_D_B_RCVRDLY[Channel][Receiver>>1]; - for (i = 0; i < 8; i++) { - val = p[i]; - printk(BIOS_DEBUG, "%02x ", val); - } - printk(BIOS_DEBUG, "\n"); - } - } - } -#endif - - print_tx("TrainRcvrEn: Status ", pDCTstat->Status); - print_tx("TrainRcvrEn: ErrStatus ", pDCTstat->ErrStatus); - print_tx("TrainRcvrEn: ErrCode ", pDCTstat->ErrCode); - print_t("TrainRcvrEn: Done\n"); -} - - -u8 mct_InitReceiver_D(struct DCTStatStruc *pDCTstat, u8 dct) -{ - if (pDCTstat->DIMMValidDCT[dct] == 0) { - return 8; - } else { - return 0; - } -} - - -static void mct_SetFinalRcvrEnDly_D(struct DCTStatStruc *pDCTstat, u8 RcvrEnDly, u8 where, u8 Channel, u8 Receiver, u32 dev, u32 index_reg, u8 Addl_Index, u8 Pass/*, u8 *p*/) -{ - /* - * Program final DqsRcvEnDly to additional index for DQS receiver - * enabled delay - */ - mct_SetRcvrEnDly_D(pDCTstat, RcvrEnDly, where, Channel, Receiver, dev, index_reg, Addl_Index, Pass); -} - - -static void mct_DisableDQSRcvEn_D(struct DCTStatStruc *pDCTstat) -{ - u8 ch_end, ch; - u32 reg; - u32 dev; - u32 val; - - dev = pDCTstat->dev_dct; - if (pDCTstat->GangedMode) { - ch_end = 1; - } else { - ch_end = 2; - } - - for (ch = 0; ch < ch_end; ch++) { - reg = 0x78 + 0x100 * ch; - val = Get_NB32(dev, reg); - val &= ~(1 << DqsRcvEnTrain); - Set_NB32(dev, reg, val); - } -} - - -/* mct_ModifyIndex_D - * Function only used once so it was inlined. - */ - - -/* mct_GetInitFlag_D - * Function only used once so it was inlined. - */ - - -void mct_SetRcvrEnDly_D(struct DCTStatStruc *pDCTstat, u8 RcvrEnDly, - u8 FinalValue, u8 Channel, u8 Receiver, u32 dev, - u32 index_reg, u8 Addl_Index, u8 Pass) -{ - u32 index; - u8 i; - u8 *p; - u32 val; - - if (RcvrEnDly == 0xFE) { - /*set the boudary flag */ - pDCTstat->Status |= 1 << SB_DQSRcvLimit; - } - - /* DimmOffset not needed for CH_D_B_RCVRDLY array */ - - - for (i = 0; i < 8; i++) { - if (FinalValue) { - /*calculate dimm offset */ - p = pDCTstat->persistentData.CH_D_B_RCVRDLY[Channel][Receiver >> 1]; - RcvrEnDly = p[i]; - } - - /* if flag = 0, set DqsRcvEn value to reg. */ - /* get the register index from table */ - index = Table_DQSRcvEn_Offset[i >> 1]; - index += Addl_Index; /* DIMMx DqsRcvEn byte0 */ - val = Get_NB32_index_wait(dev, index_reg, index); - if (i & 1) { - /* odd byte lane */ - val &= ~(0xFF << 16); - val |= (RcvrEnDly << 16); - } else { - /* even byte lane */ - val &= ~0xFF; - val |= RcvrEnDly; - } - Set_NB32_index_wait(dev, index_reg, index, val); - } - -} - -static void mct_SetMaxLatency_D(struct DCTStatStruc *pDCTstat, u8 Channel, u8 DQSRcvEnDly) -{ - u32 dev; - u32 reg; - u16 SubTotal; - u32 index_reg; - u32 reg_off; - u32 val; - u32 valx; - - if (pDCTstat->GangedMode) - Channel = 0; - - dev = pDCTstat->dev_dct; - reg_off = 0x100 * Channel; - index_reg = 0x98 + reg_off; - - /* Multiply the CAS Latency by two to get a number of 1/2 MEMCLKs units.*/ - val = Get_NB32(dev, 0x88 + reg_off); - SubTotal = ((val & 0x0f) + 1) << 1; /* SubTotal is 1/2 Memclk unit */ - - /* If registered DIMMs are being used then - * add 1 MEMCLK to the sub-total. - */ - val = Get_NB32(dev, 0x90 + reg_off); - if (!(val & (1 << UnBuffDimm))) - SubTotal += 2; - - /* If the address prelaunch is setup for 1/2 MEMCLKs then - * add 1, else add 2 to the sub-total. - * if (AddrCmdSetup || CsOdtSetup || CkeSetup) then K := K + 2; - */ - val = Get_NB32_index_wait(dev, index_reg, 0x04); - if (!(val & 0x00202020)) - SubTotal += 1; - else - SubTotal += 2; - - /* If the F2x[1, 0]78[RdPtrInit] field is 4, 5, 6 or 7 MEMCLKs, - * then add 4, 3, 2, or 1 MEMCLKs, respectively to the sub-total. */ - val = Get_NB32(dev, 0x78 + reg_off); - SubTotal += 8 - (val & 0x0f); - - /* Convert bits 7-5 (also referred to as the course delay) of - * the current (or worst case) DQS receiver enable delay to - * 1/2 MEMCLKs units, rounding up, and add this to the sub-total. - */ - SubTotal += DQSRcvEnDly >> 5; /*BOZO-no rounding up */ - - /* Add 5.5 to the sub-total. 5.5 represents part of the - * processor specific constant delay value in the DRAM - * clock domain. - */ - SubTotal <<= 1; /*scale 1/2 MemClk to 1/4 MemClk */ - SubTotal += 11; /*add 5.5 1/2MemClk */ - - /* Convert the sub-total (in 1/2 MEMCLKs) to northbridge - * clocks (NCLKs) as follows (assuming DDR400 and assuming - * that no P-state or link speed changes have occurred). - */ - - /* New formula: - * SubTotal *= 3*(Fn2xD4[NBFid]+4)/(3+Fn2x94[MemClkFreq])/2 */ - val = Get_NB32(dev, 0x94 + reg_off); - - /* SubTotal div 4 to scale 1/4 MemClk back to MemClk */ - val &= 7; - if (val == 4) { - val++; /* adjust for DDR2-1066 */ - } - valx = (val + 3) << 2; - - val = Get_NB32(pDCTstat->dev_nbmisc, 0xD4); - SubTotal *= ((val & 0x1f) + 4) * 3; - - SubTotal /= valx; - if (SubTotal % valx) { /* round up */ - SubTotal++; - } - - /* Add 5 NCLKs to the sub-total. 5 represents part of the - * processor specific constant value in the northbridge - * clock domain. - */ - SubTotal += 5; - - pDCTstat->CH_MaxRdLat[Channel] = SubTotal; - if (pDCTstat->GangedMode) { - pDCTstat->CH_MaxRdLat[1] = SubTotal; - } - - /* Program the F2x[1, 0]78[MaxRdLatency] register with - * the total delay value (in NCLKs). - */ - - reg = 0x78 + reg_off; - val = Get_NB32(dev, reg); - val &= ~(0x3ff << 22); - val |= (SubTotal & 0x3ff) << 22; - - /* program MaxRdLatency to correspond with current delay */ - Set_NB32(dev, reg, val); -} - - -static u8 mct_SavePassRcvEnDly_D(struct DCTStatStruc *pDCTstat, - u8 rcvrEnDly, u8 Channel, - u8 receiver, u8 Pass) -{ - u8 i; - u8 mask_Saved, mask_Pass; - u8 *p; - - /* calculate dimm offset - * not needed for CH_D_B_RCVRDLY array - */ - - /* cmp if there has new DqsRcvEnDly to be recorded */ - mask_Pass = pDCTstat->DqsRcvEn_Pass; - - if (Pass == SecondPass) { - mask_Pass = ~mask_Pass; - } - - mask_Saved = pDCTstat->DqsRcvEn_Saved; - if (mask_Pass != mask_Saved) { - - /* find desired stack offset according to channel/dimm/byte */ - if (Pass == SecondPass) { - // FIXME: SecondPass is never used for Barcelona p = pDCTstat->persistentData.CH_D_B_RCVRDLY_1[Channel][receiver>>1]; - p = 0; // Keep the compiler happy. - } else { - mask_Saved &= mask_Pass; - p = pDCTstat->persistentData.CH_D_B_RCVRDLY[Channel][receiver>>1]; - } - for (i = 0; i < 8; i++) { - /* cmp per byte lane */ - if (mask_Pass & (1 << i)) { - if (!(mask_Saved & (1 << i))) { - /* save RcvEnDly to stack, according to - the related Dimm/byte lane */ - p[i] = (u8)rcvrEnDly; - mask_Saved |= 1 << i; - } - } - } - pDCTstat->DqsRcvEn_Saved = mask_Saved; - } - return mct_SaveRcvEnDly_D_1Pass(pDCTstat, Pass); -} - - -static u8 mct_CompareTestPatternQW0_D(struct MCTStatStruc *pMCTstat, - struct DCTStatStruc *pDCTstat, - u32 addr, u8 channel, - u8 pattern, u8 Pass) -{ - /* Compare only the first beat of data. Since target addrs are cache - * line aligned, the Channel parameter is used to determine which - * cache QW to compare. - */ - - u8 *test_buf; - u8 i; - u8 result; - u8 value; - - - if (Pass == FirstPass) { - if (pattern == 1) { - test_buf = (u8 *)TestPattern1_D; - } else { - test_buf = (u8 *)TestPattern0_D; - } - } else { // Second Pass - test_buf = (u8 *)TestPattern2_D; - } - - SetUpperFSbase(addr); - addr <<= 8; - - if ((pDCTstat->Status & (1<DqsRcvEn_Pass |= (1<DqsRcvEn_Pass &= ~(1<DqsRcvEn_Pass != 0) { - result = DQS_PASS; - } else { - result = DQS_FAIL; - } - - } else { - /* if second pass, at least one byte lane fail - * ,then DQS_FAIL = 1 and will set to related reg. - */ - if (pDCTstat->DqsRcvEn_Pass != 0xFF) { - result = DQS_FAIL; - } else { - result = DQS_PASS; - } - } - - /* if second pass, we can't find the fail until FFh, - * then let it fail to save the final delay - */ - if ((Pass == SecondPass) && (pDCTstat->Status & (1 << SB_DQSRcvLimit))) { - result = DQS_FAIL; - pDCTstat->DqsRcvEn_Pass = 0; - } - - /* second pass needs to be inverted - * FIXME? this could be inverted in the above code to start with... - */ - if (Pass == SecondPass) { - if (result == DQS_PASS) { - result = DQS_FAIL; - } else if (result == DQS_FAIL) { /* FIXME: doesn't need to be else if */ - result = DQS_PASS; - } - } - - - return result; -} - - - -static void mct_InitDQSPos4RcvrEn_D(struct MCTStatStruc *pMCTstat, - struct DCTStatStruc *pDCTstat) -{ - /* Initialize the DQS Positions in preparation for - * Receiver Enable Training. - * Write Position is 1/2 Memclock Delay - * Read Position is 1/2 Memclock Delay - */ - u8 i; - for (i = 0; i < 2; i++) { - InitDQSPos4RcvrEn_D(pMCTstat, pDCTstat, i); - } -} - - -static void InitDQSPos4RcvrEn_D(struct MCTStatStruc *pMCTstat, - struct DCTStatStruc *pDCTstat, u8 Channel) -{ - /* Initialize the DQS Positions in preparation for - * Receiver Enable Training. - * Write Position is no Delay - * Read Position is 1/2 Memclock Delay - */ - - u8 i, j; - u32 dword; - u8 dn = 2; // TODO: Rev C could be 4 - u32 dev = pDCTstat->dev_dct; - u32 index_reg = 0x98 + 0x100 * Channel; - - - // FIXME: add Cx support - dword = 0x00000000; - for (i = 1; i <= 3; i++) { - for (j = 0; j < dn; j++) - /* DIMM0 Write Data Timing Low */ - /* DIMM0 Write ECC Timing */ - Set_NB32_index_wait(dev, index_reg, i + 0x100 * j, dword); - } - - /* errata #180 */ - dword = 0x2f2f2f2f; - for (i = 5; i <= 6; i++) { - for (j = 0; j < dn; j++) - /* DIMM0 Read DQS Timing Control Low */ - Set_NB32_index_wait(dev, index_reg, i + 0x100 * j, dword); - } - - dword = 0x0000002f; - for (j = 0; j < dn; j++) - /* DIMM0 Read DQS ECC Timing Control */ - Set_NB32_index_wait(dev, index_reg, 7 + 0x100 * j, dword); -} - - -void SetEccDQSRcvrEn_D(struct DCTStatStruc *pDCTstat, u8 Channel) -{ - u32 dev; - u32 index_reg; - u32 index; - u8 ChipSel; - u8 *p; - u32 val; - - dev = pDCTstat->dev_dct; - index_reg = 0x98 + Channel * 0x100; - index = 0x12; - p = pDCTstat->persistentData.CH_D_BC_RCVRDLY[Channel]; - print_debug_dqs("\t\tSetEccDQSRcvrPos: Channel ", Channel, 2); - for (ChipSel = 0; ChipSel < MAX_CS_SUPPORTED; ChipSel += 2) { - val = p[ChipSel>>1]; - Set_NB32_index_wait(dev, index_reg, index, val); - print_debug_dqs_pair("\t\tSetEccDQSRcvrPos: ChipSel ", - ChipSel, " rcvr_delay ", val, 2); - index += 3; - } -} - - -static void CalcEccDQSRcvrEn_D(struct MCTStatStruc *pMCTstat, - struct DCTStatStruc *pDCTstat, u8 Channel) -{ - u8 ChipSel; - u16 EccDQSLike; - u8 EccDQSScale; - u32 val, val0, val1; - - EccDQSLike = pDCTstat->CH_EccDQSLike[Channel]; - EccDQSScale = pDCTstat->CH_EccDQSScale[Channel]; - - for (ChipSel = 0; ChipSel < MAX_CS_SUPPORTED; ChipSel += 2) { - if (mct_RcvrRankEnabled_D(pMCTstat, pDCTstat, Channel, ChipSel)) { - u8 *p; - p = pDCTstat->persistentData.CH_D_B_RCVRDLY[Channel][ChipSel>>1]; - - /* DQS Delay Value of Data Bytelane - * most like ECC byte lane */ - val0 = p[EccDQSLike & 0x07]; - /* DQS Delay Value of Data Bytelane - * 2nd most like ECC byte lane */ - val1 = p[(EccDQSLike>>8) & 0x07]; - - if (val0 > val1) { - val = val0 - val1; - } else { - val = val1 - val0; - } - - val *= ~EccDQSScale; - val >>= 8; // /256 - - if (val0 > val1) { - val -= val1; - } else { - val += val0; - } - - pDCTstat->persistentData.CH_D_BC_RCVRDLY[Channel][ChipSel>>1] = val; - } - } - SetEccDQSRcvrEn_D(pDCTstat, Channel); -} - -void mctSetEccDQSRcvrEn_D(struct MCTStatStruc *pMCTstat, - struct DCTStatStruc *pDCTstatA) -{ - u8 Node; - u8 i; - - for (Node = 0; Node < MAX_NODES_SUPPORTED; Node++) { - struct DCTStatStruc *pDCTstat; - pDCTstat = pDCTstatA + Node; - if (!pDCTstat->NodePresent) - break; - if (pDCTstat->DCTSysLimit) { - for (i = 0; i < 2; i++) - CalcEccDQSRcvrEn_D(pMCTstat, pDCTstat, i); - } - } -} - - -void phyAssistedMemFnceTraining(struct MCTStatStruc *pMCTstat, - struct DCTStatStruc *pDCTstatA) -{ - - u8 Node = 0; - struct DCTStatStruc *pDCTstat; - - // FIXME: skip for Ax - while (Node < MAX_NODES_SUPPORTED) { - pDCTstat = pDCTstatA + Node; - - if (pDCTstat->DCTSysLimit) { - fenceDynTraining_D(pMCTstat, pDCTstat, 0); - fenceDynTraining_D(pMCTstat, pDCTstat, 1); - } - Node++; - } -} - - -static void fenceDynTraining_D(struct MCTStatStruc *pMCTstat, - struct DCTStatStruc *pDCTstat, u8 dct) -{ - u16 avRecValue; - u32 val; - u32 dev; - u32 index_reg = 0x98 + 0x100 * dct; - u32 index; - - /* BIOS first programs a seed value to the phase recovery engine - * (recommended 19) registers. - * Dram Phase Recovery Control Register (F2x[1,0]9C_x[51:50] and - * F2x[1,0]9C_x52.) . - */ - - dev = pDCTstat->dev_dct; - for (index = 0x50; index <= 0x52; index ++) { - val = (FenceTrnFinDlySeed & 0x1F); - if (index != 0x52) { - val |= val << 8 | val << 16 | val << 24; - } - Set_NB32_index_wait(dev, index_reg, index, val); - } - - - /* Set F2x[1,0]9C_x08[PhyFenceTrEn]=1. */ - val = Get_NB32_index_wait(dev, index_reg, 0x08); - val |= 1 << PhyFenceTrEn; - Set_NB32_index_wait(dev, index_reg, 0x08, val); - - /* Wait 200 MEMCLKs. */ - mct_Wait(50000); /* wait 200us */ - - /* Clear F2x[1,0]9C_x08[PhyFenceTrEn]=0. */ - val = Get_NB32_index_wait(dev, index_reg, 0x08); - val &= ~(1 << PhyFenceTrEn); - Set_NB32_index_wait(dev, index_reg, 0x08, val); - - /* BIOS reads the phase recovery engine registers - * F2x[1,0]9C_x[51:50] and F2x[1,0]9C_x52. */ - avRecValue = 0; - for (index = 0x50; index <= 0x52; index ++) { - val = Get_NB32_index_wait(dev, index_reg, index); - avRecValue += val & 0x7F; - if (index != 0x52) { - avRecValue += (val >> 8) & 0x7F; - avRecValue += (val >> 16) & 0x7F; - avRecValue += (val >> 24) & 0x7F; - } - } - - val = avRecValue / 9; - if (avRecValue % 9) - val++; - avRecValue = val; - - /* Write the (averaged value -8) to F2x[1,0]9C_x0C[PhyFence]. */ - avRecValue -= 8; - val = Get_NB32_index_wait(dev, index_reg, 0x0C); - val &= ~(0x1F << 16); - val |= (avRecValue & 0x1F) << 16; - Set_NB32_index_wait(dev, index_reg, 0x0C, val); - - /* Rewrite F2x[1,0]9C_x04-DRAM Address/Command Timing Control Register - * delays (both channels). */ - val = Get_NB32_index_wait(dev, index_reg, 0x04); - Set_NB32_index_wait(dev, index_reg, 0x04, val); -} - - -void mct_Wait(u32 cycles) -{ - u32 saved; - u32 hi, lo, msr; - - /* Wait # of 50ns cycles - This seems like a hack to me... */ - - cycles <<= 3; /* x8 (number of 1.25ns ticks) */ - - msr = 0x10; /* TSC */ - _RDMSR(msr, &lo, &hi); - saved = lo; - do { - _RDMSR(msr, &lo, &hi); - } while (lo - saved < cycles); -} diff --git a/src/northbridge/amd/amdmct/mct/mctsrc1p.c b/src/northbridge/amd/amdmct/mct/mctsrc1p.c deleted file mode 100644 index 8ae60253ab..0000000000 --- a/src/northbridge/amd/amdmct/mct/mctsrc1p.c +++ /dev/null @@ -1,91 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include "mct_d.h" - -u8 mct_checkNumberOfDqsRcvEn_1Pass(u8 pass) -{ - u8 ret = 1; - if (pass == SecondPass) - ret = 0; - - return ret; -} - - -u32 SetupDqsPattern_1PassA(u8 pass) -{ - return (u32) TestPattern1_D; -} - - -u32 SetupDqsPattern_1PassB(u8 pass) -{ - return (u32) TestPattern0_D; -} - -u8 mct_Get_Start_RcvrEnDly_1Pass(u8 pass) -{ - return 0; -} - -static u8 mct_Average_RcvrEnDly_1Pass(struct DCTStatStruc *pDCTstat, u8 Channel, u8 Receiver, - u8 Pass) -{ - u8 i, MaxValue; - u8 *p; - u8 val; - - MaxValue = 0; - p = pDCTstat->persistentData.CH_D_B_RCVRDLY[Channel][Receiver >> 1]; - - for (i = 0; i < 8; i++) { - /* get left value from DCTStatStruc.CHA_D0_B0_RCVRDLY*/ - val = p[i]; - /* get right value from DCTStatStruc.CHA_D0_B0_RCVRDLY_1*/ - val += Pass1MemClkDly; - /* write back the value to stack */ - if (val > MaxValue) - MaxValue = val; - - p[i] = val; - } - - return MaxValue; -} - -#ifdef UNUSED_CODE -static u8 mct_AdjustFinalDQSRcvValue_1Pass(u8 val_1p, u8 val_2p) -{ - return (val_1p & 0xff) + ((val_2p & 0xff)<<8); -} -#endif - -u8 mct_SaveRcvEnDly_D_1Pass(struct DCTStatStruc *pDCTstat, u8 pass) -{ - u8 ret; - ret = 0; - if ((pDCTstat->DqsRcvEn_Pass == 0xff) && (pass== FirstPass)) - ret = 2; - return ret; -} - -u8 mct_Average_RcvrEnDly_Pass(struct DCTStatStruc *pDCTstat, - u8 RcvrEnDly, u8 RcvrEnDlyLimit, - u8 Channel, u8 Receiver, u8 Pass) - -{ - return mct_Average_RcvrEnDly_1Pass(pDCTstat, Channel, Receiver, Pass); -} diff --git a/src/northbridge/amd/amdmct/mct/mctsrc2p.c b/src/northbridge/amd/amdmct/mct/mctsrc2p.c deleted file mode 100644 index ab278e9199..0000000000 --- a/src/northbridge/amd/amdmct/mct/mctsrc2p.c +++ /dev/null @@ -1,130 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - - -u8 mct_checkNumberOfDqsRcvEn_Pass(u8 pass) -{ - return 1; -} - - -u32 SetupDqsPattern_PassA(u8 Pass) -{ - u32 ret; - if (Pass == FirstPass) - ret = (u32) TestPattern1_D; - else - ret = (u32) TestPattern2_D; - - return ret; -} - - -u32 SetupDqsPattern_PassB(u8 Pass) -{ - u32 ret; - if (Pass == FirstPass) - ret = (u32) TestPattern0_D; - else - ret = (u32) TestPattern2_D; - - return ret; -} - - -u8 mct_Get_Start_RcvrEnDly_Pass(struct DCTStatStruc *pDCTstat, - u8 Channel, u8 Receiver, - u8 Pass) -{ - u8 RcvrEnDly; - - if (Pass == FirstPass) - RcvrEnDly = 0; - else { - u8 max = 0; - u8 val; - u8 i; - u8 *p = pDCTstat->persistentData.CH_D_B_RCVRDLY[Channel][Receiver>>1]; - u8 bn; - bn = 8; - - for (i = 0; i < bn; i++) { - val = p[i]; - if (val > max) { - max = val; - } - } - RcvrEnDly = max; -// while (1) {; } -// RcvrEnDly += secPassOffset; //FIXME Why - } - - return RcvrEnDly; -} - - - -u8 mct_Average_RcvrEnDly_Pass(struct DCTStatStruc *pDCTstat, - u8 RcvrEnDly, u8 RcvrEnDlyLimit, - u8 Channel, u8 Receiver, u8 Pass) -{ - u8 i; - u8 *p; - u8 *p_1; - u8 val; - u8 val_1; - u8 valid = 1; - u8 bn; - - bn = 8; - - p = pDCTstat->persistentData.CH_D_B_RCVRDLY[Channel][Receiver>>1]; - - if (Pass == SecondPass) { /* second pass must average values */ - //FIXME: which byte? - p_1 = pDCTstat->B_RCVRDLY_1; -// p_1 = pDCTstat->persistentData.CH_D_B_RCVRDLY_1[Channel][Receiver>>1]; - for (i = 0; i < bn; i++) { - val = p[i]; - /* left edge */ - if (val != (RcvrEnDlyLimit - 1)) { - val -= Pass1MemClkDly; - val_1 = p_1[i]; - val += val_1; - val >>= 1; - p[i] = val; - } else { - valid = 0; - break; - } - } - if (!valid) { - pDCTstat->ErrStatus |= 1<DimmTrainFail &= ~(1<<(Receiver + Channel)); - } - } else { - for (i = 0; i < bn; i++) { - val = p[i]; - /* Add 1/2 Memlock delay */ - val += 0x5; // NOTE: middle value with DQSRCVEN_SAVED_GOOD_TIMES - p[i] = val; - pDCTstat->DimmTrainFail &= ~(1<<(Receiver + Channel)); - } - } - - return RcvrEnDly; -} diff --git a/src/northbridge/amd/amdmct/mct/mcttmrl.c b/src/northbridge/amd/amdmct/mct/mcttmrl.c deleted file mode 100644 index 6ec4d648d8..0000000000 --- a/src/northbridge/amd/amdmct/mct/mcttmrl.c +++ /dev/null @@ -1,409 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include - -#include "mct_d.h" - -/* - * Description: Max Read Latency Training feature for DDR 2 MCT - */ - -static u8 CompareMaxRdLatTestPattern_D(u32 pattern_buf, u32 addr); -static u32 GetMaxRdLatTestAddr_D(struct MCTStatStruc *pMCTstat, - struct DCTStatStruc *pDCTstat, u8 Channel, - u8 *MaxRcvrEnDly, u8 *valid); -u8 mct_GetStartMaxRdLat_D(struct MCTStatStruc *pMCTstat, - struct DCTStatStruc *pDCTstat, u8 Channel, - u8 DQSRcvEnDly, u32 *Margin); -static void maxRdLatencyTrain_D(struct MCTStatStruc *pMCTstat, - struct DCTStatStruc *pDCTstat); -static void mct_setMaxRdLatTrnVal_D(struct DCTStatStruc *pDCTstat, u8 Channel, - u16 MaxRdLatVal); - -/*Warning: These must be located so they do not cross a logical 16-bit - segment boundary!*/ -static const u32 TestMaxRdLAtPattern_D[] = { - 0x6E0E3FAC, 0x0C3CFF52, - 0x4A688181, 0x49C5B613, - 0x7C780BA6, 0x5C1650E3, - 0x0C4F9D76, 0x0C6753E6, - 0x205535A5, 0xBABFB6CA, - 0x610E6E5F, 0x0C5F1C87, - 0x488493CE, 0x14C9C383, - 0xF5B9A5CD, 0x9CE8F615, - - 0xAAD714B5, 0xC38F1B4C, - 0x72ED647C, 0x669F7562, - 0x5233F802, 0x4A898B30, - 0x10A40617, 0x3326B465, - 0x55386E04, 0xC807E3D3, - 0xAB49E193, 0x14B4E63A, - 0x67DF2495, 0xEA517C45, - 0x7624CE51, 0xF8140C51, - - 0x4824BD23, 0xB61DD0C9, - 0x072BCFBE, 0xE8F3807D, - 0x919EA373, 0x25E30C47, - 0xFEB12958, 0x4DA80A5A, - 0xE9A0DDF8, 0x792B0076, - 0xE81C73DC, 0xF025B496, - 0x1DB7E627, 0x808594FE, - 0x82668268, 0x655C7783, -}; - - -static u32 SetupMaxRdPattern(struct MCTStatStruc *pMCTstat, - struct DCTStatStruc *pDCTstat, - u32 *buffer) -{ - /* 1. Copy the alpha and Beta patterns from ROM to Cache, - * aligning on 16 byte boundary - * 2. Set the ptr to Cacheable copy in DCTStatstruc.PtrPatternBufA - * for Alpha - * 3. Set the ptr to Cacheable copy in DCTStatstruc.PtrPatternBufB - * for Beta - */ - - u32 *buf; - u8 i; - - buf = (u32 *)(((u32)buffer + 0x10) & (0xfffffff0)); - - for (i = 0; i < (16 * 3); i++) { - buf[i] = TestMaxRdLAtPattern_D[i]; - } - - return (u32)buf; - -} - - -void TrainMaxReadLatency_D(struct MCTStatStruc *pMCTstat, - struct DCTStatStruc *pDCTstatA) -{ - u8 Node; - - for (Node = 0; Node < MAX_NODES_SUPPORTED; Node++) { - struct DCTStatStruc *pDCTstat; - pDCTstat = pDCTstatA + Node; - - if (!pDCTstat->NodePresent) - break; - - if (pDCTstat->DCTSysLimit) - maxRdLatencyTrain_D(pMCTstat, pDCTstat); - } -} - - -static void maxRdLatencyTrain_D(struct MCTStatStruc *pMCTstat, - struct DCTStatStruc *pDCTstat) -{ - u8 Channel; - u32 TestAddr0; - u8 _DisableDramECC = 0, _Wrap32Dis = 0, _SSE2 = 0; - u16 MaxRdLatDly; - u8 RcvrEnDly = 0; - u32 PatternBuffer[60]; // FIXME: why not 48 + 4 - u32 Margin; - u32 addr; - CRx_TYPE cr4; - u32 lo, hi; - - u8 valid; - u32 pattern_buf; - - cr4 = read_cr4(); - if (cr4 & (1<<9)) { /* save the old value */ - _SSE2 = 1; - } - cr4 |= (1<<9); /* OSFXSR enable SSE2 */ - write_cr4(cr4); - - addr = HWCR_MSR; - _RDMSR(addr, &lo, &hi); - if (lo & (1<<17)) { /* save the old value */ - _Wrap32Dis = 1; - } - lo |= (1<<17); /* HWCR.wrap32dis */ - lo &= ~(1<<15); /* SSEDIS */ - /* Setting wrap32dis allows 64-bit memory references in - real mode */ - _WRMSR(addr, lo, hi); - - _DisableDramECC = mct_DisableDimmEccEn_D(pMCTstat, pDCTstat); - - pattern_buf = SetupMaxRdPattern(pMCTstat, pDCTstat, PatternBuffer); - - for (Channel = 0; Channel < 2; Channel++) { - print_debug_dqs("\tMaxRdLatencyTrain51: Channel ",Channel, 1); - pDCTstat->Channel = Channel; - - if ((pDCTstat->Status & (1 << SB_128bitmode)) && Channel) - break; /*if ganged mode, skip DCT 1 */ - - TestAddr0 = GetMaxRdLatTestAddr_D(pMCTstat, pDCTstat, Channel, &RcvrEnDly, &valid); - if (!valid) /* Address not supported on current CS */ - continue; - /* rank 1 of DIMM, testpattern 0 */ - WriteMaxRdLat1CLTestPattern_D(pattern_buf, TestAddr0); - - MaxRdLatDly = mct_GetStartMaxRdLat_D(pMCTstat, pDCTstat, Channel, RcvrEnDly, &Margin); - print_debug_dqs("\tMaxRdLatencyTrain52: MaxRdLatDly start ", MaxRdLatDly, 2); - print_debug_dqs("\tMaxRdLatencyTrain52: MaxRdLatDly Margin ", Margin, 2); - while (MaxRdLatDly < MAX_RD_LAT) { /* sweep Delay value here */ - mct_setMaxRdLatTrnVal_D(pDCTstat, Channel, MaxRdLatDly); - ReadMaxRdLat1CLTestPattern_D(TestAddr0); - if (CompareMaxRdLatTestPattern_D(pattern_buf, TestAddr0) == DQS_PASS) - break; - SetTargetWTIO_D(TestAddr0); - FlushMaxRdLatTestPattern_D(TestAddr0); - ResetTargetWTIO_D(); - MaxRdLatDly++; - } - print_debug_dqs("\tMaxRdLatencyTrain53: MaxRdLatDly end ", MaxRdLatDly, 2); - mct_setMaxRdLatTrnVal_D(pDCTstat, Channel, MaxRdLatDly + Margin); - } - - if (_DisableDramECC) { - mct_EnableDimmEccEn_D(pMCTstat, pDCTstat, _DisableDramECC); - } - - if (!_Wrap32Dis) { - addr = HWCR_MSR; - _RDMSR(addr, &lo, &hi); - lo &= ~(1<<17); /* restore HWCR.wrap32dis */ - _WRMSR(addr, lo, hi); - } - if (!_SSE2) { - cr4 = read_cr4(); - cr4 &= ~(1<<9); /* restore cr4.OSFXSR */ - write_cr4(cr4); - } - -#if DQS_TRAIN_DEBUG > 0 - { - u8 Channel; - printk(BIOS_DEBUG, "maxRdLatencyTrain: CH_MaxRdLat:\n"); - for (Channel = 0; Channel < 2; Channel++) { - printk(BIOS_DEBUG, "Channel: %02x: %02x\n", Channel, pDCTstat->CH_MaxRdLat[Channel]); - } - } -#endif - -} - -static void mct_setMaxRdLatTrnVal_D(struct DCTStatStruc *pDCTstat, - u8 Channel, u16 MaxRdLatVal) -{ - u8 i; - u32 reg; - u32 dev; - u32 val; - - if (pDCTstat->GangedMode) { - Channel = 0; // for safe - for (i = 0; i < 2; i++) - pDCTstat->CH_MaxRdLat[i] = MaxRdLatVal; - } else { - pDCTstat->CH_MaxRdLat[Channel] = MaxRdLatVal; - } - - dev = pDCTstat->dev_dct; - reg = 0x78 + Channel * 0x100; - val = Get_NB32(dev, reg); - val &= ~(0x3ff<<22); - val |= MaxRdLatVal << 22; - /* program MaxRdLatency to correspond with current delay */ - Set_NB32(dev, reg, val); - -} - - -static u8 CompareMaxRdLatTestPattern_D(u32 pattern_buf, u32 addr) -{ - /* Compare only the first beat of data. Since target addrs are cache - * line aligned, the Channel parameter is used to determine which cache - * QW to compare. - */ - - u32 *test_buf = (u32 *)pattern_buf; - u32 addr_lo; - u32 val, val_test; - int i; - u8 ret = DQS_PASS; - - SetUpperFSbase(addr); - addr_lo = addr << 8; - - _EXECFENCE; - for (i = 0; i < (16*3); i++) { - val = read32_fs(addr_lo); - val_test = test_buf[i]; - - print_debug_dqs_pair("\t\t\t\t\t\ttest_buf = ", (u32)test_buf, " value = ", val_test, 5); - print_debug_dqs_pair("\t\t\t\t\t\ttaddr_lo = ", addr_lo, " value = ", val, 5); - if (val != val_test) { - ret = DQS_FAIL; - break; - } - addr_lo += 4; - } - - return ret; -} - -static u32 GetMaxRdLatTestAddr_D(struct MCTStatStruc *pMCTstat, - struct DCTStatStruc *pDCTstat, - u8 Channel, u8 *MaxRcvrEnDly, - u8 *valid) -{ - u8 Max = 0; - - u8 Channel_Max = 0; - u8 d; - u8 d_Max = 0; - - u8 Byte; - u32 TestAddr0 = 0; - u8 ch, ch_start, ch_end; - u8 bn; - - bn = 8; - - if (pDCTstat->Status & (1 << SB_128bitmode)) { - ch_start = 0; - ch_end = 2; - } else { - ch_start = Channel; - ch_end = Channel + 1; - } - - *valid = 0; - - for (ch = ch_start; ch < ch_end; ch++) { - for (d = 0; d < 4; d++) { - for (Byte = 0; Byte < bn; Byte++) { - u8 tmp; - tmp = pDCTstat->persistentData.CH_D_B_RCVRDLY[ch][d][Byte]; - if (tmp > Max) { - Max = tmp; - Channel_Max = Channel; - d_Max = d; - } - } - } - } - - if (mct_RcvrRankEnabled_D(pMCTstat, pDCTstat, Channel_Max, d_Max << 1)) { - TestAddr0 = mct_GetMCTSysAddr_D(pMCTstat, pDCTstat, Channel_Max, d_Max << 1, valid); - } - - if (*valid) - *MaxRcvrEnDly = Max; - - return TestAddr0; - -} - -u8 mct_GetStartMaxRdLat_D(struct MCTStatStruc *pMCTstat, - struct DCTStatStruc *pDCTstat, - u8 Channel, u8 DQSRcvEnDly, u32 *Margin) -{ - u32 SubTotal; - u32 val; - u32 valx; - u32 valxx; - u32 index_reg; - u32 reg_off; - u32 dev; - - if (pDCTstat->GangedMode) - Channel = 0; - - index_reg = 0x98 + 0x100 * Channel; - - reg_off = 0x100 * Channel; - dev = pDCTstat->dev_dct; - - /* Multiply the CAS Latency by two to get a number of 1/2 MEMCLKs units.*/ - val = Get_NB32(dev, 0x88 + reg_off); - SubTotal = ((val & 0x0f) + 1) << 1; /* SubTotal is 1/2 Memclk unit */ - - /* If registered DIMMs are being used then add 1 MEMCLK to the sub-total*/ - val = Get_NB32(dev, 0x90 + reg_off); - if (!(val & (1 << UnBuffDimm))) - SubTotal += 2; - - /*If the address prelaunch is setup for 1/2 MEMCLKs then add 1, - * else add 2 to the sub-total. if (AddrCmdSetup || CsOdtSetup - * || CkeSetup) then K := K + 2; */ - val = Get_NB32_index_wait(dev, index_reg, 0x04); - if (!(val & 0x00202020)) - SubTotal += 1; - else - SubTotal += 2; - - /* If the F2x[1, 0]78[RdPtrInit] field is 4, 5, 6 or 7 MEMCLKs, - * then add 4, 3, 2, or 1 MEMCLKs, respectively to the sub-total. */ - val = Get_NB32(dev, 0x78 + reg_off); - SubTotal += 8 - (val & 0x0f); - - /* Convert bits 7-5 (also referred to as the course delay) of the current - * (or worst case) DQS receiver enable delay to 1/2 MEMCLKs units, - * rounding up, and add this to the sub-total. */ - SubTotal += DQSRcvEnDly >> 5; /*BOZO-no rounding up */ - - SubTotal <<= 1; /*scale 1/2 MemClk to 1/4 MemClk */ - - /* Convert the sub-total (in 1/2 MEMCLKs) to northbridge clocks (NCLKs) - * as follows (assuming DDR400 and assuming that no P-state or link speed - * changes have occurred). */ - - /*New formula: - SubTotal *= 3*(Fn2xD4[NBFid]+4)/(3+Fn2x94[MemClkFreq])/2 */ - val = Get_NB32(dev, 0x94 + reg_off); - /* SubTotal div 4 to scale 1/4 MemClk back to MemClk */ - val &= 7; - if (val == 4) { - val++; /* adjust for DDR2-1066 */ - } - valx = (val + 3) << 2; /* SubTotal div 4 to scale 1/4 MemClk back to MemClk */ - - - val = Get_NB32(pDCTstat->dev_nbmisc, 0xD4); - val = ((val & 0x1f) + 4) * 3; - - /* Calculate 1 MemClk + 1 NCLK delay in NCLKs for margin */ - valxx = val << 2; - valxx /= valx; - if (valxx % valx) - valxx++; /* round up */ - valxx++; /* add 1NCLK */ - *Margin = valxx; /* one MemClk delay in NCLKs and one additional NCLK */ - - val *= SubTotal; - - val /= valx; - if (val % valx) - val++; /* round up */ - - - - return val; -} diff --git a/src/northbridge/amd/amdmct/mct_ddr3/Makefile.inc b/src/northbridge/amd/amdmct/mct_ddr3/Makefile.inc deleted file mode 100644 index 65c146a662..0000000000 --- a/src/northbridge/amd/amdmct/mct_ddr3/Makefile.inc +++ /dev/null @@ -1,31 +0,0 @@ -ifeq ($(CONFIG_NORTHBRIDGE_AMD_AMDFAM10),y) - -# DDR3 -romstage-$(CONFIG_HAVE_ACPI_RESUME) += s3utils.c -romstage-y += mct_d.c mctmtr_d.c mctcsi_d.c mctecc_d.c mctdqs_d.c mctsrc.c -romstage-y += mctsdi.c mctprod.c mctproc.c mctprob.c mcthwl.c mctwl.c -romstage-y += mport_d.c mutilc_d.c modtrdim.c mhwlc_d.c mctrci.c mctsrc1p.c -romstage-y += mcttmrl.c mcthdi.c mctndi_d.c mctchi_d.c modtrd.c mct_d_gcc.c - -ifeq ($(CONFIG_CPU_SOCKET_TYPE), 0x11) -romstage-y += mctardk5.c -endif -ifeq ($(CONFIG_CPU_SOCKET_TYPE), 0x13) -romstage-y += mctardk5.c -endif -ifeq ($(CONFIG_CPU_SOCKET_TYPE), 0x14) -romstage-y += mctardk5.c -endif -ifeq ($(CONFIG_CPU_SOCKET_TYPE), 0x15) -romstage-y += mctardk5.c -endif -ifeq ($(CONFIG_CPU_SOCKET_TYPE), 0x16) -romstage-y += mctardk5.c -endif -ifeq ($(CONFIG_CPU_SOCKET_TYPE), 0x12) -romstage-y += mctardk6.c -endif - -ramstage-$(CONFIG_HAVE_ACPI_RESUME) += s3utils.c - -endif diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c deleted file mode 100644 index fa8c71447b..0000000000 --- a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c +++ /dev/null @@ -1,8220 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2015-2017 Raptor Engineering, LLC - * Copyright (C) 2010 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -/* Description: Main memory controller system configuration for DDR 3 */ - -/* KNOWN ISSUES - ERRATA - * - * Trtp is not calculated correctly when the controller is in 64-bit mode, it - * is 1 busclock off. No fix planned. The controller is not ordinarily in - * 64-bit mode. - * - * 32 Byte burst not supported. No fix planned. The controller is not - * ordinarily in 64-bit mode. - * - * Trc precision does not use extra Jedec defined fractional component. - * InsteadTrc (course) is rounded up to nearest 1 ns. - * - * Mini and Micro DIMM not supported. Only RDIMM, UDIMM, SO-DIMM defined types - * supported. - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include "s3utils.h" -#include "mct_d_gcc.h" -#include "mct_d.h" - -static u8 ReconfigureDIMMspare_D(struct MCTStatStruc *pMCTstat, - struct DCTStatStruc *pDCTstatA); -static void DQSTiming_D(struct MCTStatStruc *pMCTstat, - struct DCTStatStruc *pDCTstatA, - uint8_t allow_config_restore); -static void LoadDQSSigTmgRegs_D(struct MCTStatStruc *pMCTstat, - struct DCTStatStruc *pDCTstatA); -static void HTMemMapInit_D(struct MCTStatStruc *pMCTstat, - struct DCTStatStruc *pDCTstatA); -static void SyncDCTsReady_D(struct MCTStatStruc *pMCTstat, - struct DCTStatStruc *pDCTstatA); -static void ClearDCT_D(struct MCTStatStruc *pMCTstat, - struct DCTStatStruc *pDCTstat, u8 dct); -static u8 AutoCycTiming_D(struct MCTStatStruc *pMCTstat, - struct DCTStatStruc *pDCTstat, u8 dct); -static void GetPresetmaxF_D(struct MCTStatStruc *pMCTstat, - struct DCTStatStruc *pDCTstat); -static void SPDGetTCL_D(struct MCTStatStruc *pMCTstat, - struct DCTStatStruc *pDCTstat, u8 dct); -static u8 AutoConfig_D(struct MCTStatStruc *pMCTstat, - struct DCTStatStruc *pDCTstat, u8 dct); -static void SPDSetBanks_D(struct MCTStatStruc *pMCTstat, - struct DCTStatStruc *pDCTstat, u8 dct); -static void StitchMemory_D(struct MCTStatStruc *pMCTstat, - struct DCTStatStruc *pDCTstat, u8 dct); -static u16 Get_Fk_D(u8 k); -static u8 Get_DIMMAddress_D(struct DCTStatStruc *pDCTstat, u8 i); -static void mct_preInitDCT(struct MCTStatStruc *pMCTstat, - struct DCTStatStruc *pDCTstat); -static void mct_initDCT(struct MCTStatStruc *pMCTstat, - struct DCTStatStruc *pDCTstat); -static void mct_DramInit(struct MCTStatStruc *pMCTstat, - struct DCTStatStruc *pDCTstat, u8 dct); -static void mct_SyncDCTsReady(struct DCTStatStruc *pDCTstat); -static void Get_Trdrd(struct MCTStatStruc *pMCTstat, - struct DCTStatStruc *pDCTstat, u8 dct); -static void mct_AfterGetCLT(struct MCTStatStruc *pMCTstat, - struct DCTStatStruc *pDCTstat, u8 dct); -static u8 mct_SPDCalcWidth(struct MCTStatStruc *pMCTstat,\ - struct DCTStatStruc *pDCTstat, u8 dct); -static void mct_AfterStitchMemory(struct MCTStatStruc *pMCTstat, - struct DCTStatStruc *pDCTstat, u8 dct); -static u8 mct_DIMMPresence(struct MCTStatStruc *pMCTstat, - struct DCTStatStruc *pDCTstat, u8 dct); -static void Set_OtherTiming(struct MCTStatStruc *pMCTstat, - struct DCTStatStruc *pDCTstat, u8 dct); -static void Get_Twrwr(struct MCTStatStruc *pMCTstat, - struct DCTStatStruc *pDCTstat, u8 dct); -static void Get_Twrrd(struct MCTStatStruc *pMCTstat, - struct DCTStatStruc *pDCTstat, u8 dct); -static void Get_TrwtTO(struct MCTStatStruc *pMCTstat, - struct DCTStatStruc *pDCTstat, u8 dct); -static void Get_TrwtWB(struct MCTStatStruc *pMCTstat, - struct DCTStatStruc *pDCTstat); -static void Get_DqsRcvEnGross_Diff(struct DCTStatStruc *pDCTstat, - u32 dev, uint8_t dct, u32 index_reg); -static void Get_WrDatGross_Diff(struct DCTStatStruc *pDCTstat, u8 dct, - u32 dev, u32 index_reg); -static u16 Get_DqsRcvEnGross_MaxMin(struct DCTStatStruc *pDCTstat, - u32 dev, uint8_t dct, u32 index_reg, u32 index); -static void mct_FinalMCT_D(struct MCTStatStruc *pMCTstat, - struct DCTStatStruc *pDCTstat); -static u16 Get_WrDatGross_MaxMin(struct DCTStatStruc *pDCTstat, u8 dct, - u32 dev, u32 index_reg, u32 index); -static void mct_InitialMCT_D(struct MCTStatStruc *pMCTstat, - struct DCTStatStruc *pDCTstat); -static void mct_init(struct MCTStatStruc *pMCTstat, - struct DCTStatStruc *pDCTstat); -static void clear_legacy_Mode(struct MCTStatStruc *pMCTstat, - struct DCTStatStruc *pDCTstat); -static void mct_HTMemMapExt(struct MCTStatStruc *pMCTstat, - struct DCTStatStruc *pDCTstatA); -static void SetCSTriState(struct MCTStatStruc *pMCTstat, - struct DCTStatStruc *pDCTstat, u8 dct); -static void SetCKETriState(struct MCTStatStruc *pMCTstat, - struct DCTStatStruc *pDCTstat, u8 dct); -static void SetODTTriState(struct MCTStatStruc *pMCTstat, - struct DCTStatStruc *pDCTstat, u8 dct); -static void InitDDRPhy(struct MCTStatStruc *pMCTstat, - struct DCTStatStruc *pDCTstat, u8 dct); -static u32 mct_NodePresent_D(void); -static void mct_OtherTiming(struct MCTStatStruc *pMCTstat, - struct DCTStatStruc *pDCTstatA); -static void mct_ResetDataStruct_D(struct MCTStatStruc *pMCTstat, - struct DCTStatStruc *pDCTstatA); -static void mct_EarlyArbEn_D(struct MCTStatStruc *pMCTstat, - struct DCTStatStruc *pDCTstat, u8 dct); -static void mct_BeforeDramInit_Prod_D(struct MCTStatStruc *pMCTstat, - struct DCTStatStruc *pDCTstat, u8 dct); -static void mct_ProgramODT_D(struct MCTStatStruc *pMCTstat, - struct DCTStatStruc *pDCTstat, u8 dct); -void mct_ClrClToNB_D(struct MCTStatStruc *pMCTstat, - struct DCTStatStruc *pDCTstat); -static u8 CheckNBCOFEarlyArbEn(struct MCTStatStruc *pMCTstat, - struct DCTStatStruc *pDCTstat); -void mct_ClrWbEnhWsbDis_D(struct MCTStatStruc *pMCTstat, - struct DCTStatStruc *pDCTstat); -static void mct_BeforeDQSTrain_D(struct MCTStatStruc *pMCTstat, - struct DCTStatStruc *pDCTstatA); -static void AfterDramInit_D(struct DCTStatStruc *pDCTstat, u8 dct); -static void mct_ResetDLL_D(struct MCTStatStruc *pMCTstat, - struct DCTStatStruc *pDCTstat, u8 dct); -static u32 mct_DisDllShutdownSR(struct MCTStatStruc *pMCTstat, - struct DCTStatStruc *pDCTstat, u32 DramConfigLo, u8 dct); -static void mct_EnDllShutdownSR(struct MCTStatStruc *pMCTstat, - struct DCTStatStruc *pDCTstat, u8 dct); -void ChangeMemClk(struct MCTStatStruc *pMCTstat, - struct DCTStatStruc *pDCTstat); - -static u8 Get_Latency_Diff(struct MCTStatStruc *pMCTstat, - struct DCTStatStruc *pDCTstat, u8 dct); -static void SyncSetting(struct DCTStatStruc *pDCTstat); -static uint8_t crcCheck(struct DCTStatStruc *pDCTstat, uint8_t dimm); - -uint8_t is_ecc_enabled(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstat); - -/*See mctAutoInitMCT header for index relationships to CL and T*/ -static const u16 Table_F_k[] = {00,200,266,333,400,533 }; -static const u8 Tab_BankAddr[] = {0x3F,0x01,0x09,0x3F,0x3F,0x11,0x0A,0x19,0x12,0x1A,0x21,0x22,0x23}; -const u8 Table_DQSRcvEn_Offset[] = {0x00,0x01,0x10,0x11,0x2}; - -/**************************************************************************** - Describe how platform maps MemClk pins to logical DIMMs. The MemClk pins - are identified based on BKDG definition of Fn2x88[MemClkDis] bitmap. - AGESA will base on this value to disable unused MemClk to save power. - - If MEMCLK_MAPPING or MEMCLK_MAPPING contains all zeroes, AGESA will use - default MemClkDis setting based on package type. - - Example: - BKDG definition of Fn2x88[MemClkDis] bitmap for AM3 package is like below: - Bit AM3/S1g3 pin name - 0 M[B,A]_CLK_H/L[0] - 1 M[B,A]_CLK_H/L[1] - 2 M[B,A]_CLK_H/L[2] - 3 M[B,A]_CLK_H/L[3] - 4 M[B,A]_CLK_H/L[4] - 5 M[B,A]_CLK_H/L[5] - 6 M[B,A]_CLK_H/L[6] - 7 M[B,A]_CLK_H/L[7] - - And platform has the following routing: - CS0 M[B,A]_CLK_H/L[4] - CS1 M[B,A]_CLK_H/L[2] - CS2 M[B,A]_CLK_H/L[3] - CS3 M[B,A]_CLK_H/L[5] - - Then: - ; CS0 CS1 CS2 CS3 CS4 CS5 CS6 CS7 - MEMCLK_MAPPING EQU 00010000b, 00000100b, 00001000b, 00100000b, 00000000b, 00000000b, 00000000b, 00000000b -*/ - -/* ========================================================================================== - * Set up clock pin to DIMM mappings, - * NOTE: If you are not sure about the pin mappings, you can keep all MemClk signals active, - * just set all entries in the relevant table(s) to 0xff. - * ========================================================================================== - */ -static const u8 Tab_L1CLKDis[] = {0x20, 0x20, 0x10, 0x10, 0x08, 0x08, 0x04, 0x04}; -static const u8 Tab_AM3CLKDis[] = {0xFF, 0xFF, 0xFF, 0xFF, 0x00, 0x00, 0x00, 0x00}; -static const u8 Tab_S1CLKDis[] = {0xA2, 0xA2, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}; - -/* C32: Enable CS0 - CS3 clocks (DIMM0 - DIMM1) */ -static const u8 Tab_C32CLKDis[] = {0xFF, 0xFF, 0xFF, 0xFF, 0x00, 0x00, 0x00, 0x00}; - -/* G34: Enable CS0 - CS3 clocks (DIMM0 - DIMM1) */ -static const u8 Tab_G34CLKDis[] = {0xFF, 0xFF, 0xFF, 0xFF, 0x00, 0x00, 0x00, 0x00}; - -/* FM2: Enable all the clocks for the dimms */ -static const u8 Tab_FM2CLKDis[] = {0xFF, 0xFF, 0xFF, 0xFF, 0x00, 0x00, 0x00, 0x00}; - -static const u8 Tab_ManualCLKDis[]= {0x10, 0x04, 0x08, 0x20, 0x00, 0x00, 0x00, 0x00}; -/* ========================================================================================== */ - -static const u8 Table_Comp_Rise_Slew_20x[] = {7, 3, 2, 2, 0xFF}; -static const u8 Table_Comp_Rise_Slew_15x[] = {7, 7, 3, 2, 0xFF}; -static const u8 Table_Comp_Fall_Slew_20x[] = {7, 5, 3, 2, 0xFF}; -static const u8 Table_Comp_Fall_Slew_15x[] = {7, 7, 5, 3, 0xFF}; - -uint8_t dct_ddr_voltage_index(struct DCTStatStruc *pDCTstat, uint8_t dct) -{ - uint8_t dimm; - uint8_t ddr_voltage_index = 0; - - /* If no DIMMs are present on this DCT, report 1.5V operation and skip checking the hardware */ - if (pDCTstat->DIMMValidDCT[dct] == 0) - return 0x1; - - /* Find current DDR supply voltage for this DCT */ - for (dimm = 0; dimm < MAX_DIMMS_SUPPORTED; dimm++) { - if (pDCTstat->DIMMValidDCT[dct] & (1 << dimm)) - ddr_voltage_index |= pDCTstat->DimmConfiguredVoltage[dimm]; - } - if (ddr_voltage_index > 0x7) { - printk(BIOS_DEBUG, "%s: Insufficient DDR supply voltage indicated! Configuring processor for 1.25V operation, but this attempt may fail...\n", __func__); - ddr_voltage_index = 0x4; - } - if (ddr_voltage_index == 0x0) { - printk(BIOS_DEBUG, "%s: No DDR supply voltage indicated! Configuring processor for 1.5V operation, but this attempt may fail...\n", __func__); - ddr_voltage_index = 0x1; - } - - return ddr_voltage_index; -} - -static uint16_t fam15h_mhz_to_memclk_config(uint16_t freq) -{ - uint16_t fam15h_freq_tab[] = {0, 0, 0, 0, 333, 0, 400, 0, 0, 0, 533, 0, 0, 0, 667, 0, 0, 0, 800, 0, 0, 0, 933}; - uint16_t iter; - - /* Compute the index value for the given frequency */ - for (iter = 0; iter <= 0x16; iter++) { - if (fam15h_freq_tab[iter] == freq) { - freq = iter; - break; - } - } - if (freq == 0) - freq = 0x4; - - return freq; -} - -static uint16_t fam10h_mhz_to_memclk_config(uint16_t freq) -{ - uint16_t fam10h_freq_tab[] = {0, 0, 0, 400, 533, 667, 800}; - uint16_t iter; - - /* Compute the index value for the given frequency */ - for (iter = 0; iter <= 0x6; iter++) { - if (fam10h_freq_tab[iter] == freq) { - freq = iter; - break; - } - } - if (freq == 0) - freq = 0x3; - - return freq; -} - -static inline uint8_t is_model10_1f(void) -{ - uint8_t model101f = 0; - uint32_t family; - - family = cpuid_eax(0x80000001); - family = ((family & 0x0ff000) >> 12); - - if (family >= 0x10 && family <= 0x1f) - /* Model 0x10 to 0x1f */ - model101f = 1; - - return model101f; -} - -uint8_t is_ecc_enabled(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstat) -{ - uint8_t ecc_enabled = 1; - - if (!pMCTstat->try_ecc) - ecc_enabled = 0; - - if (pDCTstat->NodePresent && (pDCTstat->DIMMValidDCT[0] || pDCTstat->DIMMValidDCT[1])) - if (!(pDCTstat->Status & (1 << SB_ECCDIMMs))) - ecc_enabled = 0; - - return !!ecc_enabled; -} - -uint8_t get_available_lane_count(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstat) -{ - if (is_ecc_enabled(pMCTstat, pDCTstat)) - return 9; - else - return 8; -} - -uint16_t mhz_to_memclk_config(uint16_t freq) -{ - if (is_fam15h()) - return fam15h_mhz_to_memclk_config(freq); - else - return fam10h_mhz_to_memclk_config(freq) + 1; -} - -uint32_t fam10h_address_timing_compensation_code(struct DCTStatStruc *pDCTstat, uint8_t dct) -{ - uint8_t MaxDimmsInstallable = mctGet_NVbits(NV_MAX_DIMMS_PER_CH); - - uint8_t package_type; - uint32_t calibration_code = 0; - - package_type = mctGet_NVbits(NV_PACK_TYPE); - uint16_t MemClkFreq = (Get_NB32_DCT(pDCTstat->dev_dct, dct, 0x94) & 0x7) + 1; - - /* Obtain number of DIMMs on channel */ - uint8_t dimm_count = pDCTstat->MAdimms[dct]; - uint8_t rank_count_dimm0; - uint8_t rank_count_dimm1; - - if (package_type == PT_GR) { - /* Socket G34 */ - if (pDCTstat->Status & (1 << SB_Registered)) { - /* RDIMM */ - /* Fam10h BKDG Rev. 3.62 section 2.8.9.5.8 Tables 60 - 61 */ - if (MaxDimmsInstallable == 1) { - if (MemClkFreq == 0x4) { - /* DDR3-800 */ - calibration_code = 0x00000000; - } else if (MemClkFreq == 0x5) { - /* DDR3-1066 */ - calibration_code = 0x003c3c3c; - } else if (MemClkFreq == 0x6) { - /* DDR3-1333 */ - calibration_code = 0x003a3a3a; - } - } else if (MaxDimmsInstallable == 2) { - if (dimm_count == 1) { - /* 1 DIMM detected */ - if (MemClkFreq == 0x4) { - /* DDR3-800 */ - calibration_code = 0x00000000; - } else if (MemClkFreq == 0x5) { - /* DDR3-1066 */ - calibration_code = 0x003c3c3c; - } else if (MemClkFreq == 0x6) { - /* DDR3-1333 */ - calibration_code = 0x003a3a3a; - } - } else if (dimm_count == 2) { - /* 2 DIMMs detected */ - if (MemClkFreq == 0x4) { - /* DDR3-800 */ - calibration_code = 0x00000000; - } else if (MemClkFreq == 0x5) { - /* DDR3-1066 */ - calibration_code = 0x003a3c3a; - } else if (MemClkFreq == 0x6) { - /* DDR3-1333 */ - calibration_code = 0x00383a38; - } - } - } else if (MaxDimmsInstallable == 3) { - /* TODO - * 3 DIMM/channel support unimplemented - */ - } - } else { - /* UDIMM */ - /* Fam10h BKDG Rev. 3.62 section 2.8.9.5.8 Table 56 */ - if (dimm_count == 1) { - /* 1 DIMM detected */ - rank_count_dimm0 = pDCTstat->DimmRanks[(1 * 2) + dct]; - - if (MemClkFreq == 0x4) { - /* DDR3-800 */ - if (rank_count_dimm0 == 1) - calibration_code = 0x00000000; - else - calibration_code = 0x003b0000; - } else if (MemClkFreq == 0x5) { - /* DDR3-1066 */ - if (rank_count_dimm0 == 1) - calibration_code = 0x00000000; - else - calibration_code = 0x00380000; - } else if (MemClkFreq == 0x6) { - /* DDR3-1333 */ - if (rank_count_dimm0 == 1) - calibration_code = 0x00000000; - else - calibration_code = 0x00360000; - } - } else if (dimm_count == 2) { - /* 2 DIMMs detected */ - rank_count_dimm0 = pDCTstat->DimmRanks[(0 * 2) + dct]; - rank_count_dimm1 = pDCTstat->DimmRanks[(1 * 2) + dct]; - - if (MemClkFreq == 0x4) { - /* DDR3-800 */ - calibration_code = 0x00390039; - } else if (MemClkFreq == 0x5) { - /* DDR3-1066 */ - calibration_code = 0x00350037; - } else if (MemClkFreq == 0x6) { - /* DDR3-1333 */ - calibration_code = 0x00000035; - } - } - } - } else { - /* TODO - * Other socket support unimplemented - */ - } - - return calibration_code; -} - -static uint32_t fam15h_phy_predriver_calibration_code(struct DCTStatStruc *pDCTstat, uint8_t dct, uint8_t drive_strength) -{ - uint8_t lrdimm = 0; - uint8_t package_type; - uint8_t ddr_voltage_index; - uint32_t calibration_code = 0; - uint16_t MemClkFreq = Get_NB32_DCT(pDCTstat->dev_dct, dct, 0x94) & 0x1f; - - ddr_voltage_index = dct_ddr_voltage_index(pDCTstat, dct); - package_type = mctGet_NVbits(NV_PACK_TYPE); - - if (!lrdimm) { - /* Not an LRDIMM */ - if ((package_type == PT_M2) || (package_type == PT_GR)) { - /* Socket AM3 or G34 */ - if (ddr_voltage_index & 0x4) { - /* 1.25V */ - /* Fam15h BKDG Rev. 3.14 section 2.10.5.3.4 Table 43 */ - if ((MemClkFreq == 0x4) || (MemClkFreq == 0x6)) { - /* DDR3-667 - DDR3-800 */ - if (drive_strength == 0x0) - calibration_code = 0xfff; - else if (drive_strength == 0x1) - calibration_code = 0xb6d; - else if (drive_strength == 0x2) - calibration_code = 0x924; - else if (drive_strength == 0x3) - calibration_code = 0x6db; - } else if ((MemClkFreq == 0xa) || (MemClkFreq == 0xe)) { - /* DDR3-1066 - DDR3-1333 */ - if (drive_strength == 0x0) - calibration_code = 0xfff; - else if (drive_strength == 0x1) - calibration_code = 0xfff; - else if (drive_strength == 0x2) - calibration_code = 0xdb6; - else if (drive_strength == 0x3) - calibration_code = 0x924; - } else if ((MemClkFreq == 0x12) || (MemClkFreq == 0x16)) { - /* DDR3-1600 - DDR3-1866 */ - if (drive_strength == 0x0) - calibration_code = 0xfff; - else if (drive_strength == 0x1) - calibration_code = 0xfff; - else if (drive_strength == 0x2) - calibration_code = 0xfff; - else if (drive_strength == 0x3) - calibration_code = 0xfff; - } - } else if (ddr_voltage_index & 0x2) { - /* 1.35V */ - /* Fam15h BKDG Rev. 3.14 section 2.10.5.3.4 Table 42 */ - if ((MemClkFreq == 0x4) || (MemClkFreq == 0x6)) { - /* DDR3-667 - DDR3-800 */ - if (drive_strength == 0x0) - calibration_code = 0xfff; - else if (drive_strength == 0x1) - calibration_code = 0x924; - else if (drive_strength == 0x2) - calibration_code = 0x6db; - else if (drive_strength == 0x3) - calibration_code = 0x492; - } else if ((MemClkFreq == 0xa) || (MemClkFreq == 0xe)) { - /* DDR3-1066 - DDR3-1333 */ - if (drive_strength == 0x0) - calibration_code = 0xfff; - else if (drive_strength == 0x1) - calibration_code = 0xdb6; - else if (drive_strength == 0x2) - calibration_code = 0xbd6; - else if (drive_strength == 0x3) - calibration_code = 0x6db; - } else if ((MemClkFreq == 0x12) || (MemClkFreq == 0x16)) { - /* DDR3-1600 - DDR3-1866 */ - if (drive_strength == 0x0) - calibration_code = 0xfff; - else if (drive_strength == 0x1) - calibration_code = 0xfff; - else if (drive_strength == 0x2) - calibration_code = 0xfff; - else if (drive_strength == 0x3) - calibration_code = 0xdb6; - } - } else if (ddr_voltage_index & 0x1) { - /* 1.5V */ - /* Fam15h BKDG Rev. 3.14 section 2.10.5.3.4 Table 41 */ - if ((MemClkFreq == 0x4) || (MemClkFreq == 0x6)) { - /* DDR3-667 - DDR3-800 */ - if (drive_strength == 0x0) - calibration_code = 0xb6d; - else if (drive_strength == 0x1) - calibration_code = 0x6db; - else if (drive_strength == 0x2) - calibration_code = 0x492; - else if (drive_strength == 0x3) - calibration_code = 0x492; - } else if ((MemClkFreq == 0xa) || (MemClkFreq == 0xe)) { - /* DDR3-1066 - DDR3-1333 */ - if (drive_strength == 0x0) - calibration_code = 0xfff; - else if (drive_strength == 0x1) - calibration_code = 0x924; - else if (drive_strength == 0x2) - calibration_code = 0x6db; - else if (drive_strength == 0x3) - calibration_code = 0x6db; - } else if ((MemClkFreq == 0x12) || (MemClkFreq == 0x16)) { - /* DDR3-1600 - DDR3-1866 */ - if (drive_strength == 0x0) - calibration_code = 0xfff; - else if (drive_strength == 0x1) - calibration_code = 0xfff; - else if (drive_strength == 0x2) - calibration_code = 0xfff; - else if (drive_strength == 0x3) - calibration_code = 0xb6d; - } - } - } else if (package_type == PT_C3) { - /* Socket C32 */ - if (ddr_voltage_index & 0x4) { - /* 1.25V */ - /* Fam15h BKDG Rev. 3.14 section 2.10.5.3.4 Table 46 */ - if ((MemClkFreq == 0x4) || (MemClkFreq == 0x6)) { - /* DDR3-667 - DDR3-800 */ - if (drive_strength == 0x0) - calibration_code = 0xfff; - else if (drive_strength == 0x1) - calibration_code = 0xb6d; - else if (drive_strength == 0x2) - calibration_code = 0x924; - else if (drive_strength == 0x3) - calibration_code = 0x6db; - } else if (MemClkFreq == 0xa) { - /* DDR3-1066 */ - if (drive_strength == 0x0) - calibration_code = 0xfff; - else if (drive_strength == 0x1) - calibration_code = 0xfff; - else if (drive_strength == 0x2) - calibration_code = 0xdb6; - else if (drive_strength == 0x3) - calibration_code = 0x924; - } else if (MemClkFreq == 0xe) { - /* DDR3-1333 */ - if (drive_strength == 0x0) - calibration_code = 0xb6d; - else if (drive_strength == 0x1) - calibration_code = 0x6db; - else if (drive_strength == 0x2) - calibration_code = 0x492; - else if (drive_strength == 0x3) - calibration_code = 0x492; - } else if ((MemClkFreq == 0x12) || (MemClkFreq == 0x16)) { - /* DDR3-1600 - DDR3-1866 */ - if (drive_strength == 0x0) - calibration_code = 0xfff; - else if (drive_strength == 0x1) - calibration_code = 0xfff; - else if (drive_strength == 0x2) - calibration_code = 0xfff; - else if (drive_strength == 0x3) - calibration_code = 0xfff; - } - } else if (ddr_voltage_index & 0x2) { - /* 1.35V */ - /* Fam15h BKDG Rev. 3.14 section 2.10.5.3.4 Table 45 */ - if ((MemClkFreq == 0x4) || (MemClkFreq == 0x6)) { - /* DDR3-667 - DDR3-800 */ - if (drive_strength == 0x0) - calibration_code = 0xfff; - else if (drive_strength == 0x1) - calibration_code = 0x924; - else if (drive_strength == 0x2) - calibration_code = 0x6db; - else if (drive_strength == 0x3) - calibration_code = 0x492; - } else if (MemClkFreq == 0xa) { - /* DDR3-1066 */ - if (drive_strength == 0x0) - calibration_code = 0xfff; - else if (drive_strength == 0x1) - calibration_code = 0xdb6; - else if (drive_strength == 0x2) - calibration_code = 0xb6d; - else if (drive_strength == 0x3) - calibration_code = 0x6db; - } else if (MemClkFreq == 0xe) { - /* DDR3-1333 */ - if (drive_strength == 0x0) - calibration_code = 0xfff; - else if (drive_strength == 0x1) - calibration_code = 0x924; - else if (drive_strength == 0x2) - calibration_code = 0x6db; - else if (drive_strength == 0x3) - calibration_code = 0x492; - } else if ((MemClkFreq == 0x12) || (MemClkFreq == 0x16)) { - /* DDR3-1600 - DDR3-1866 */ - if (drive_strength == 0x0) - calibration_code = 0xfff; - else if (drive_strength == 0x1) - calibration_code = 0xfff; - else if (drive_strength == 0x2) - calibration_code = 0xfff; - else if (drive_strength == 0x3) - calibration_code = 0xdb6; - } - } else if (ddr_voltage_index & 0x1) { - /* 1.5V */ - /* Fam15h BKDG Rev. 3.14 section 2.10.5.3.4 Table 44 */ - if ((MemClkFreq == 0x4) || (MemClkFreq == 0x6)) { - /* DDR3-667 - DDR3-800 */ - if (drive_strength == 0x0) - calibration_code = 0xb6d; - else if (drive_strength == 0x1) - calibration_code = 0x6db; - else if (drive_strength == 0x2) - calibration_code = 0x492; - else if (drive_strength == 0x3) - calibration_code = 0x492; - } else if (MemClkFreq == 0xa) { - /* DDR3-1066 */ - if (drive_strength == 0x0) - calibration_code = 0xfff; - else if (drive_strength == 0x1) - calibration_code = 0x924; - else if (drive_strength == 0x2) - calibration_code = 0x6db; - else if (drive_strength == 0x3) - calibration_code = 0x6db; - } else if (MemClkFreq == 0xe) { - /* DDR3-1333 */ - if (drive_strength == 0x0) - calibration_code = 0xb6d; - else if (drive_strength == 0x1) - calibration_code = 0x6db; - else if (drive_strength == 0x2) - calibration_code = 0x492; - else if (drive_strength == 0x3) - calibration_code = 0x492; - } else if ((MemClkFreq == 0x12) || (MemClkFreq == 0x16)) { - /* DDR3-1600 - DDR3-1866 */ - if (drive_strength == 0x0) - calibration_code = 0xfff; - else if (drive_strength == 0x1) - calibration_code = 0xfff; - else if (drive_strength == 0x2) - calibration_code = 0xfff; - else if (drive_strength == 0x3) - calibration_code = 0xb6d; - } - } - } else if (package_type == PT_FM2) { - /* Socket FM2 */ - if (ddr_voltage_index & 0x1) { - /* 1.5V */ - /* Fam15h BKDG Rev. 3.12 section 2.9.5.4.4 Table 22 */ - if ((MemClkFreq == 0x4) || (MemClkFreq == 0x6)) { - /* DDR3-667 - DDR3-800 */ - calibration_code = 0xb24; - } else if (MemClkFreq >= 0xa) { - /* DDR3-1066 or higher */ - calibration_code = 0xff6; - } - } - } - } else { - /* LRDIMM */ - - /* TODO - * Implement LRDIMM support - * See Fam15h BKDG Rev. 3.14 section 2.10.5.3.4 Tables 47 - 49 - */ - } - - return calibration_code; -} - -static uint32_t fam15h_phy_predriver_cmd_addr_calibration_code(struct DCTStatStruc *pDCTstat, uint8_t dct, uint8_t drive_strength) -{ - uint8_t ddr_voltage_index; - uint32_t calibration_code = 0; - uint16_t MemClkFreq = Get_NB32_DCT(pDCTstat->dev_dct, dct, 0x94) & 0x1f; - - ddr_voltage_index = dct_ddr_voltage_index(pDCTstat, dct); - - if (ddr_voltage_index & 0x4) { - /* 1.25V */ - /* Fam15h BKDG Rev. 3.14 section 2.10.5.3.4 Table 52 */ - if ((MemClkFreq == 0x4) || (MemClkFreq == 0x6)) { - /* DDR3-667 - DDR3-800 */ - if (drive_strength == 0x0) - calibration_code = 0x492; - else if (drive_strength == 0x1) - calibration_code = 0x492; - else if (drive_strength == 0x2) - calibration_code = 0x492; - else if (drive_strength == 0x3) - calibration_code = 0x492; - } else if ((MemClkFreq == 0xa) || (MemClkFreq == 0xe)) { - /* DDR3-1066 - DDR3-1333 */ - if (drive_strength == 0x0) - calibration_code = 0xdad; - else if (drive_strength == 0x1) - calibration_code = 0x924; - else if (drive_strength == 0x2) - calibration_code = 0x6db; - else if (drive_strength == 0x3) - calibration_code = 0x492; - } else if ((MemClkFreq == 0x12) || (MemClkFreq == 0x16)) { - /* DDR3-1600 - DDR3-1866 */ - if (drive_strength == 0x0) - calibration_code = 0xff6; - else if (drive_strength == 0x1) - calibration_code = 0xdad; - else if (drive_strength == 0x2) - calibration_code = 0xb64; - else if (drive_strength == 0x3) - calibration_code = 0xb64; - } - } else if (ddr_voltage_index & 0x2) { - /* 1.35V */ - /* Fam15h BKDG Rev. 3.14 section 2.10.5.3.4 Table 51 */ - if ((MemClkFreq == 0x4) || (MemClkFreq == 0x6)) { - /* DDR3-667 - DDR3-800 */ - if (drive_strength == 0x0) - calibration_code = 0x492; - else if (drive_strength == 0x1) - calibration_code = 0x492; - else if (drive_strength == 0x2) - calibration_code = 0x492; - else if (drive_strength == 0x3) - calibration_code = 0x492; - } else if ((MemClkFreq == 0xa) || (MemClkFreq == 0xe)) { - /* DDR3-1066 - DDR3-1333 */ - if (drive_strength == 0x0) - calibration_code = 0x924; - else if (drive_strength == 0x1) - calibration_code = 0x6db; - else if (drive_strength == 0x2) - calibration_code = 0x6db; - else if (drive_strength == 0x3) - calibration_code = 0x6db; - } else if ((MemClkFreq == 0x12) || (MemClkFreq == 0x16)) { - /* DDR3-1600 - DDR3-1866 */ - if (drive_strength == 0x0) - calibration_code = 0xb6d; - else if (drive_strength == 0x1) - calibration_code = 0xb6d; - else if (drive_strength == 0x2) - calibration_code = 0x924; - else if (drive_strength == 0x3) - calibration_code = 0x924; - } - } else if (ddr_voltage_index & 0x1) { - /* 1.5V */ - /* Fam15h BKDG Rev. 3.14 section 2.10.5.3.4 Table 50 */ - if ((MemClkFreq == 0x4) || (MemClkFreq == 0x6)) { - /* DDR3-667 - DDR3-800 */ - if (drive_strength == 0x0) - calibration_code = 0x492; - else if (drive_strength == 0x1) - calibration_code = 0x492; - else if (drive_strength == 0x2) - calibration_code = 0x492; - else if (drive_strength == 0x3) - calibration_code = 0x492; - } else if ((MemClkFreq == 0xa) || (MemClkFreq == 0xe)) { - /* DDR3-1066 - DDR3-1333 */ - if (drive_strength == 0x0) - calibration_code = 0x6db; - else if (drive_strength == 0x1) - calibration_code = 0x6db; - else if (drive_strength == 0x2) - calibration_code = 0x6db; - else if (drive_strength == 0x3) - calibration_code = 0x6db; - } else if ((MemClkFreq == 0x12) || (MemClkFreq == 0x16)) { - /* DDR3-1600 - DDR3-1866 */ - if (drive_strength == 0x0) - calibration_code = 0xb6d; - else if (drive_strength == 0x1) - calibration_code = 0xb6d; - else if (drive_strength == 0x2) - calibration_code = 0xb6d; - else if (drive_strength == 0x3) - calibration_code = 0xb6d; - } - } - - return calibration_code; -} - -static uint32_t fam15h_phy_predriver_clk_calibration_code(struct DCTStatStruc *pDCTstat, uint8_t dct, uint8_t drive_strength) -{ - uint8_t ddr_voltage_index; - uint32_t calibration_code = 0; - uint16_t MemClkFreq = Get_NB32_DCT(pDCTstat->dev_dct, dct, 0x94) & 0x1f; - - ddr_voltage_index = dct_ddr_voltage_index(pDCTstat, dct); - - if (ddr_voltage_index & 0x4) { - /* 1.25V */ - /* Fam15h BKDG Rev. 3.14 section 2.10.5.3.4 Table 55 */ - if ((MemClkFreq == 0x4) || (MemClkFreq == 0x6)) { - /* DDR3-667 - DDR3-800 */ - if (drive_strength == 0x0) - calibration_code = 0xdad; - else if (drive_strength == 0x1) - calibration_code = 0xdad; - else if (drive_strength == 0x2) - calibration_code = 0x924; - else if (drive_strength == 0x3) - calibration_code = 0x924; - } else if ((MemClkFreq == 0xa) || (MemClkFreq == 0xe)) { - /* DDR3-1066 - DDR3-1333 */ - if (drive_strength == 0x0) - calibration_code = 0xff6; - else if (drive_strength == 0x1) - calibration_code = 0xff6; - else if (drive_strength == 0x2) - calibration_code = 0xff6; - else if (drive_strength == 0x3) - calibration_code = 0xff6; - } else if ((MemClkFreq == 0x12) || (MemClkFreq == 0x16)) { - /* DDR3-1600 - DDR3-1866 */ - if (drive_strength == 0x0) - calibration_code = 0xff6; - else if (drive_strength == 0x1) - calibration_code = 0xff6; - else if (drive_strength == 0x2) - calibration_code = 0xff6; - else if (drive_strength == 0x3) - calibration_code = 0xff6; - } - } else if (ddr_voltage_index & 0x2) { - /* 1.35V */ - /* Fam15h BKDG Rev. 3.14 section 2.10.5.3.4 Table 54 */ - if ((MemClkFreq == 0x4) || (MemClkFreq == 0x6)) { - /* DDR3-667 - DDR3-800 */ - if (drive_strength == 0x0) - calibration_code = 0xdad; - else if (drive_strength == 0x1) - calibration_code = 0xdad; - else if (drive_strength == 0x2) - calibration_code = 0x924; - else if (drive_strength == 0x3) - calibration_code = 0x924; - } else if ((MemClkFreq == 0xa) || (MemClkFreq == 0xe)) { - /* DDR3-1066 - DDR3-1333 */ - if (drive_strength == 0x0) - calibration_code = 0xff6; - else if (drive_strength == 0x1) - calibration_code = 0xff6; - else if (drive_strength == 0x2) - calibration_code = 0xff6; - else if (drive_strength == 0x3) - calibration_code = 0xdad; - } else if ((MemClkFreq == 0x12) || (MemClkFreq == 0x16)) { - /* DDR3-1600 - DDR3-1866 */ - if (drive_strength == 0x0) - calibration_code = 0xff6; - else if (drive_strength == 0x1) - calibration_code = 0xff6; - else if (drive_strength == 0x2) - calibration_code = 0xff6; - else if (drive_strength == 0x3) - calibration_code = 0xdad; - } - } else if (ddr_voltage_index & 0x1) { - /* 1.5V */ - /* Fam15h BKDG Rev. 3.14 section 2.10.5.3.4 Table 53 */ - if ((MemClkFreq == 0x4) || (MemClkFreq == 0x6)) { - /* DDR3-667 - DDR3-800 */ - if (drive_strength == 0x0) - calibration_code = 0x924; - else if (drive_strength == 0x1) - calibration_code = 0x924; - else if (drive_strength == 0x2) - calibration_code = 0x924; - else if (drive_strength == 0x3) - calibration_code = 0x924; - } else if ((MemClkFreq == 0xa) || (MemClkFreq == 0xe)) { - /* DDR3-1066 - DDR3-1333 */ - if (drive_strength == 0x0) - calibration_code = 0xff6; - else if (drive_strength == 0x1) - calibration_code = 0xff6; - else if (drive_strength == 0x2) - calibration_code = 0xff6; - else if (drive_strength == 0x3) - calibration_code = 0xb6d; - } else if ((MemClkFreq == 0x12) || (MemClkFreq == 0x16)) { - /* DDR3-1600 - DDR3-1866 */ - if (drive_strength == 0x0) - calibration_code = 0xff6; - else if (drive_strength == 0x1) - calibration_code = 0xff6; - else if (drive_strength == 0x2) - calibration_code = 0xff6; - else if (drive_strength == 0x3) - calibration_code = 0xff6; - } - } - - return calibration_code; -} - -uint32_t fam15h_output_driver_compensation_code(struct DCTStatStruc *pDCTstat, uint8_t dct) -{ - uint8_t MaxDimmsInstallable = mctGet_NVbits(NV_MAX_DIMMS_PER_CH); - - uint8_t package_type; - uint32_t calibration_code = 0; - - package_type = mctGet_NVbits(NV_PACK_TYPE); - uint16_t MemClkFreq = Get_NB32_DCT(pDCTstat->dev_dct, dct, 0x94) & 0x1f; - - /* Obtain number of DIMMs on channel */ - uint8_t dimm_count = pDCTstat->MAdimms[dct]; - uint8_t rank_count_dimm0; - uint8_t rank_count_dimm1; - - if (package_type == PT_GR) { - /* Socket G34 */ - if (pDCTstat->Status & (1 << SB_Registered)) { - /* RDIMM */ - /* Fam15h BKDG Rev. 3.14 section 2.10.5.3.4 Table 74 */ - if (MaxDimmsInstallable == 1) { - rank_count_dimm0 = pDCTstat->DimmRanks[(1 * 2) + dct]; - - if (MemClkFreq == 0x4) { - /* DDR3-667 */ - calibration_code = 0x00112222; - } else if (MemClkFreq == 0x6) { - /* DDR3-800 */ - calibration_code = 0x10112222; - } else if (MemClkFreq == 0xa) { - /* DDR3-1066 */ - calibration_code = 0x20112222; - } else if ((MemClkFreq == 0xe) || (MemClkFreq == 0x12)) { - /* DDR3-1333 - DDR3-1600 */ - calibration_code = 0x30112222; - } else if (MemClkFreq == 0x16) { - /* DDR3-1866 */ - calibration_code = 0x30332222; - } - - if (rank_count_dimm0 == 4) { - calibration_code &= ~(0xff << 16); - calibration_code |= 0x22 << 16; - } - } else if (MaxDimmsInstallable == 2) { - rank_count_dimm0 = pDCTstat->DimmRanks[(0 * 2) + dct]; - rank_count_dimm1 = pDCTstat->DimmRanks[(1 * 2) + dct]; - - if (dimm_count == 1) { - /* 1 DIMM detected */ - if (MemClkFreq == 0x4) { - /* DDR3-667 */ - calibration_code = 0x00112222; - } else if (MemClkFreq == 0x6) { - /* DDR3-800 */ - calibration_code = 0x10112222; - } else if (MemClkFreq == 0xa) { - /* DDR3-1066 */ - calibration_code = 0x20112222; - } else if ((MemClkFreq == 0xe) || (MemClkFreq == 0x12)) { - /* DDR3-1333 - DDR3-1600 */ - calibration_code = 0x30112222; - } - - if ((rank_count_dimm0 == 4) || (rank_count_dimm1 == 4)) { - calibration_code &= ~(0xff << 16); - calibration_code |= 0x22 << 16; - } - } else if (dimm_count == 2) { - /* 2 DIMMs detected */ - rank_count_dimm0 = pDCTstat->DimmRanks[(0 * 2) + dct]; - rank_count_dimm1 = pDCTstat->DimmRanks[(1 * 2) + dct]; - - if (MemClkFreq == 0x4) { - /* DDR3-667 */ - calibration_code = 0x10222222; - } else if (MemClkFreq == 0x6) { - /* DDR3-800 */ - calibration_code = 0x20222222; - } else if (MemClkFreq == 0xa) { - /* DDR3-1066 */ - calibration_code = 0x30222222; - } else if (MemClkFreq == 0xe) { - /* DDR3-1333 */ - calibration_code = 0x30222222; - } else if (MemClkFreq == 0x12) { - /* DDR3-1600 */ - calibration_code = 0x30222222; - } - } - } else if (MaxDimmsInstallable == 3) { - /* TODO - * 3 DIMM/channel support unimplemented - */ - } - } else if (pDCTstat->Status & (1 << SB_LoadReduced)) { - /* LRDIMM */ - /* TODO - * LRDIMM support unimplemented - */ - } else { - /* UDIMM */ - /* Fam15h BKDG Rev. 3.14 section 2.10.5.3.4 Table 73 */ - if (MaxDimmsInstallable == 1) { - if (MemClkFreq == 0x4) { - /* DDR3-667 */ - calibration_code = 0x00112222; - } else if (MemClkFreq == 0x6) { - /* DDR3-800 */ - calibration_code = 0x10112222; - } else if (MemClkFreq == 0xa) { - /* DDR3-1066 */ - calibration_code = 0x20112222; - } else if ((MemClkFreq == 0xe) || (MemClkFreq == 0x12)) { - /* DDR3-1333 - DDR3-1600 */ - calibration_code = 0x30112222; - } else if (MemClkFreq == 0x16) { - /* DDR3-1866 */ - calibration_code = 0x30332222; - } - } else if (MaxDimmsInstallable == 2) { - if (dimm_count == 1) { - /* 1 DIMM detected */ - if (MemClkFreq == 0x4) { - /* DDR3-667 */ - calibration_code = 0x00112222; - } else if (MemClkFreq == 0x6) { - /* DDR3-800 */ - calibration_code = 0x10112222; - } else if (MemClkFreq == 0xa) { - /* DDR3-1066 */ - calibration_code = 0x20112222; - } else if ((MemClkFreq == 0xe) || (MemClkFreq == 0x12)) { - /* DDR3-1333 - DDR3-1600 */ - calibration_code = 0x30112222; - } - } else if (dimm_count == 2) { - /* 2 DIMMs detected */ - rank_count_dimm0 = pDCTstat->DimmRanks[(0 * 2) + dct]; - rank_count_dimm1 = pDCTstat->DimmRanks[(1 * 2) + dct]; - - if (MemClkFreq == 0x4) { - /* DDR3-667 */ - calibration_code = 0x10222222; - } else if (MemClkFreq == 0x6) { - /* DDR3-800 */ - calibration_code = 0x20222222; - } else if (MemClkFreq == 0xa) { - /* DDR3-1066 */ - calibration_code = 0x30222222; - } else if (MemClkFreq == 0xe) { - /* DDR3-1333 */ - calibration_code = 0x30222222; - } else if (MemClkFreq == 0x12) { - /* DDR3-1600 */ - if ((rank_count_dimm0 == 1) && (rank_count_dimm1 == 1)) - calibration_code = 0x30222222; - else - calibration_code = 0x30112222; - } - } - } else if (MaxDimmsInstallable == 3) { - /* TODO - * 3 DIMM/channel support unimplemented - */ - } - } - } else if (package_type == PT_C3) { - /* Socket C32 */ - if (pDCTstat->Status & (1 << SB_Registered)) { - /* RDIMM */ - /* Fam15h BKDG Rev. 3.14 section 2.10.5.3.4 Table 77 */ - if (MaxDimmsInstallable == 1) { - rank_count_dimm0 = pDCTstat->DimmRanks[(1 * 2) + dct]; - - if (MemClkFreq == 0x4) { - /* DDR3-667 */ - calibration_code = 0x00112222; - } else if (MemClkFreq == 0x6) { - /* DDR3-800 */ - calibration_code = 0x10112222; - } else if (MemClkFreq == 0xa) { - /* DDR3-1066 */ - calibration_code = 0x20112222; - } else if ((MemClkFreq == 0xe) || (MemClkFreq == 0x12)) { - /* DDR3-1333 - DDR3-1600 */ - calibration_code = 0x30112222; - } - - if (rank_count_dimm0 == 4) { - calibration_code &= ~(0xff << 16); - calibration_code |= 0x22 << 16; - } - } else if (MaxDimmsInstallable == 2) { - rank_count_dimm0 = pDCTstat->DimmRanks[(0 * 2) + dct]; - rank_count_dimm1 = pDCTstat->DimmRanks[(1 * 2) + dct]; - - if (dimm_count == 1) { - /* 1 DIMM detected */ - if (MemClkFreq == 0x4) { - /* DDR3-667 */ - calibration_code = 0x00112222; - } else if (MemClkFreq == 0x6) { - /* DDR3-800 */ - calibration_code = 0x10112222; - } else if (MemClkFreq == 0xa) { - /* DDR3-1066 */ - calibration_code = 0x20112222; - } else if ((MemClkFreq == 0xe) || (MemClkFreq == 0x12)) { - /* DDR3-1333 - DDR3-1600 */ - calibration_code = 0x30112222; - } - - if ((rank_count_dimm0 == 4) || (rank_count_dimm1 == 4)) { - calibration_code &= ~(0xff << 16); - calibration_code |= 0x22 << 16; - } - } else if (dimm_count == 2) { - /* 2 DIMMs detected */ - rank_count_dimm0 = pDCTstat->DimmRanks[(0 * 2) + dct]; - rank_count_dimm1 = pDCTstat->DimmRanks[(1 * 2) + dct]; - - if (MemClkFreq == 0x4) { - /* DDR3-667 */ - calibration_code = 0x10222222; - } else if (MemClkFreq == 0x6) { - /* DDR3-800 */ - calibration_code = 0x20222222; - } else if (MemClkFreq == 0xa) { - /* DDR3-1066 */ - calibration_code = 0x30222222; - } else if (MemClkFreq == 0xe) { - /* DDR3-1333 */ - calibration_code = 0x30222222; - } else if (MemClkFreq == 0x12) { - /* DDR3-1600 */ - calibration_code = 0x30222222; - } - } - } else if (MaxDimmsInstallable == 3) { - /* TODO - * 3 DIMM/channel support unimplemented - */ - } - } else if (pDCTstat->Status & (1 << SB_LoadReduced)) { - /* LRDIMM */ - /* TODO - * LRDIMM support unimplemented - */ - } else { - /* UDIMM */ - /* Fam15h BKDG Rev. 3.14 section 2.10.5.3.4 Table 73 */ - if (MaxDimmsInstallable == 1) { - if (MemClkFreq == 0x4) { - /* DDR3-667 */ - calibration_code = 0x00112222; - } else if (MemClkFreq == 0x6) { - /* DDR3-800 */ - calibration_code = 0x10112222; - } else if (MemClkFreq == 0xa) { - /* DDR3-1066 */ - calibration_code = 0x20112222; - } else if ((MemClkFreq == 0xe) || (MemClkFreq == 0x12)) { - /* DDR3-1333 - DDR3-1600 */ - calibration_code = 0x30112222; - } - } else if (MaxDimmsInstallable == 2) { - if (dimm_count == 1) { - /* 1 DIMM detected */ - if (MemClkFreq == 0x4) { - /* DDR3-667 */ - calibration_code = 0x00112222; - } else if (MemClkFreq == 0x6) { - /* DDR3-800 */ - calibration_code = 0x10112222; - } else if (MemClkFreq == 0xa) { - /* DDR3-1066 */ - calibration_code = 0x20112222; - } else if ((MemClkFreq == 0xe) || (MemClkFreq == 0x12)) { - /* DDR3-1333 - DDR3-1600 */ - calibration_code = 0x30112222; - } - } else if (dimm_count == 2) { - /* 2 DIMMs detected */ - rank_count_dimm0 = pDCTstat->DimmRanks[(0 * 2) + dct]; - rank_count_dimm1 = pDCTstat->DimmRanks[(1 * 2) + dct]; - - if (MemClkFreq == 0x4) { - /* DDR3-667 */ - calibration_code = 0x10222222; - } else if (MemClkFreq == 0x6) { - /* DDR3-800 */ - calibration_code = 0x20222222; - } else if (MemClkFreq == 0xa) { - /* DDR3-1066 */ - calibration_code = 0x30222222; - } else if (MemClkFreq == 0xe) { - /* DDR3-1333 */ - calibration_code = 0x30222222; - } else if (MemClkFreq == 0x12) { - /* DDR3-1600 */ - if ((rank_count_dimm0 == 1) && (rank_count_dimm1 == 1)) - calibration_code = 0x30222222; - else - calibration_code = 0x30112222; - } - } - } else if (MaxDimmsInstallable == 3) { - /* TODO - * 3 DIMM/channel support unimplemented - */ - } - } - } else if (package_type == PT_FM2) { - /* Socket FM2 */ - /* Assume UDIMM */ - /* Fam15h Model10h BKDG Rev. 3.12 section 2.9.5.6.6 Table 32 */ - if (MaxDimmsInstallable == 1) { - rank_count_dimm0 = pDCTstat->DimmRanks[(1 * 2) + dct]; - - if (MemClkFreq == 0x4) { - /* DDR3-667 */ - calibration_code = 0x00112222; - } else if (MemClkFreq == 0x6) { - /* DDR3-800 */ - calibration_code = 0x10112222; - } else if (MemClkFreq == 0xa) { - /* DDR3-1066 */ - calibration_code = 0x20112222; - } else if (MemClkFreq >= 0xe) { - /* DDR3-1333 or higher */ - calibration_code = 0x30112222; - } - } else if (MaxDimmsInstallable == 2) { - rank_count_dimm0 = pDCTstat->DimmRanks[(0 * 2) + dct]; - rank_count_dimm1 = pDCTstat->DimmRanks[(1 * 2) + dct]; - - if (dimm_count == 1) { - /* 1 DIMM detected */ - if ((MemClkFreq == 0x4) || (MemClkFreq == 0x6)) { - /* DDR3-667 or DDR3-800 */ - calibration_code = 0x00112222; - } else if (MemClkFreq == 0xa) { - /* DDR3-1066 */ - calibration_code = 0x10112222; - } else if (MemClkFreq == 0xe) { - /* DDR3-1333 */ - calibration_code = 0x20112222; - } else if (MemClkFreq >= 0x12) { - /* DDR3-1600 or higher */ - calibration_code = 0x30112222; - } - } else if (dimm_count == 2) { - /* 2 DIMMs detected */ - rank_count_dimm0 = pDCTstat->DimmRanks[(0 * 2) + dct]; - rank_count_dimm1 = pDCTstat->DimmRanks[(1 * 2) + dct]; - - if (MemClkFreq == 0x4) { - /* DDR3-667 */ - calibration_code = 0x10222322; - } else if (MemClkFreq == 0x6) { - /* DDR3-800 */ - calibration_code = 0x20222322; - } else if (MemClkFreq >= 0xa) { - /* DDR3-1066 or higher */ - calibration_code = 0x30222322; - } - } - } else if (MaxDimmsInstallable == 3) { - /* TODO - * 3 DIMM/channel support unimplemented - */ - } - } else { - /* TODO - * Other socket support unimplemented - */ - } - - return calibration_code; -} - -uint32_t fam15h_address_timing_compensation_code(struct DCTStatStruc *pDCTstat, uint8_t dct) -{ - uint8_t MaxDimmsInstallable = mctGet_NVbits(NV_MAX_DIMMS_PER_CH); - - uint8_t package_type; - uint32_t calibration_code = 0; - - package_type = mctGet_NVbits(NV_PACK_TYPE); - uint16_t MemClkFreq = Get_NB32_DCT(pDCTstat->dev_dct, dct, 0x94) & 0x1f; - - /* Obtain number of DIMMs on channel */ - uint8_t dimm_count = pDCTstat->MAdimms[dct]; - uint8_t rank_count_dimm0; - uint8_t rank_count_dimm1; - - if (package_type == PT_GR) { - /* Socket G34 */ - if (pDCTstat->Status & (1 << SB_Registered)) { - /* RDIMM */ - /* Fam15h BKDG Rev. 3.14 section 2.10.5.3.4 Table 74 */ - if (MaxDimmsInstallable == 1) { - if ((MemClkFreq == 0x4) || (MemClkFreq == 0x6)) { - /* DDR3-667 - DDR3-800 */ - calibration_code = 0x00000000; - } else if (MemClkFreq == 0xa) { - /* DDR3-1066 */ - calibration_code = 0x003c3c3c; - } else if (MemClkFreq == 0xe) { - /* DDR3-1333 */ - calibration_code = 0x003a3a3a; - } else if ((MemClkFreq == 0x12) || (MemClkFreq == 0x16)) { - /* DDR3-1600 - DDR3-1866 */ - calibration_code = 0x00393939; - } - } else if (MaxDimmsInstallable == 2) { - if (dimm_count == 1) { - /* 1 DIMM detected */ - if ((MemClkFreq == 0x4) || (MemClkFreq == 0x6)) { - /* DDR3-667 - DDR3-800 */ - calibration_code = 0x00000000; - } else if (MemClkFreq == 0xa) { - /* DDR3-1066 */ - calibration_code = 0x00393c39; - } else if (MemClkFreq == 0xe) { - /* DDR3-1333 */ - calibration_code = 0x00373a37; - } else if (MemClkFreq == 0x12) { - /* DDR3-1600 */ - calibration_code = 0x00363936; - } - } else if (dimm_count == 2) { - /* 2 DIMMs detected */ - if ((MemClkFreq == 0x4) || (MemClkFreq == 0x6)) { - /* DDR3-667 - DDR3-800 */ - calibration_code = 0x00000000; - } else if (MemClkFreq == 0xa) { - /* DDR3-1066 */ - calibration_code = 0x003a3c3a; - } else if (MemClkFreq == 0xe) { - /* DDR3-1333 */ - calibration_code = 0x00383a38; - } else if (MemClkFreq == 0x12) { - /* DDR3-1600 */ - calibration_code = 0x00353935; - } - } - } else if (MaxDimmsInstallable == 3) { - /* TODO - * 3 DIMM/channel support unimplemented - */ - } - } else if (pDCTstat->Status & (1 << SB_LoadReduced)) { - /* LRDIMM */ - /* TODO - * LRDIMM support unimplemented - */ - } else { - /* UDIMM */ - /* Fam15h BKDG Rev. 3.14 section 2.10.5.3.4 Table 76 */ - if (MaxDimmsInstallable == 1) { - rank_count_dimm0 = pDCTstat->DimmRanks[(1 * 2) + dct]; - - if (MemClkFreq == 0x4) { - /* DDR3-667 */ - if (rank_count_dimm0 == 1) - calibration_code = 0x00000000; - else - calibration_code = 0x003b0000; - } else if (MemClkFreq == 0x6) { - /* DDR3-800 */ - if (rank_count_dimm0 == 1) - calibration_code = 0x00000000; - else - calibration_code = 0x003b0000; - } else if (MemClkFreq == 0xa) { - /* DDR3-1066 */ - calibration_code = 0x00383837; - } else if (MemClkFreq == 0xe) { - /* DDR3-1333 */ - calibration_code = 0x00363635; - } else if (MemClkFreq == 0x12) { - /* DDR3-1600 */ - if (rank_count_dimm0 == 1) - calibration_code = 0x00353533; - else - calibration_code = 0x00003533; - } else if (MemClkFreq == 0x16) { - /* DDR3-1866 */ - calibration_code = 0x00333330; - } - } else if (MaxDimmsInstallable == 2) { - if (dimm_count == 1) { - /* 1 DIMM detected */ - rank_count_dimm0 = pDCTstat->DimmRanks[(1 * 2) + dct]; - - if (MemClkFreq == 0x4) { - /* DDR3-667 */ - if (rank_count_dimm0 == 1) - calibration_code = 0x00000000; - else - calibration_code = 0x003b0000; - } else if (MemClkFreq == 0x6) { - /* DDR3-800 */ - if (rank_count_dimm0 == 1) - calibration_code = 0x00000000; - else - calibration_code = 0x003b0000; - } else if (MemClkFreq == 0xa) { - /* DDR3-1066 */ - calibration_code = 0x00383837; - } else if (MemClkFreq == 0xe) { - /* DDR3-1333 */ - calibration_code = 0x00363635; - } else if (MemClkFreq == 0x12) { - /* DDR3-1600 */ - if (rank_count_dimm0 == 1) - calibration_code = 0x00353533; - else - calibration_code = 0x00003533; - } - } else if (dimm_count == 2) { - /* 2 DIMMs detected */ - rank_count_dimm0 = pDCTstat->DimmRanks[(0 * 2) + dct]; - rank_count_dimm1 = pDCTstat->DimmRanks[(1 * 2) + dct]; - - if (MemClkFreq == 0x4) { - /* DDR3-667 */ - calibration_code = 0x00390039; - } else if (MemClkFreq == 0x6) { - /* DDR3-800 */ - calibration_code = 0x00390039; - } else if (MemClkFreq == 0xa) { - /* DDR3-1066 */ - calibration_code = 0x003a3a3a; - } else if (MemClkFreq == 0xe) { - /* DDR3-1333 */ - calibration_code = 0x00003939; - } else if (MemClkFreq == 0x12) { - /* DDR3-1600 */ - if ((rank_count_dimm0 == 1) && (rank_count_dimm1 == 1)) - calibration_code = 0x00003738; - } - } - } else if (MaxDimmsInstallable == 3) { - /* TODO - * 3 DIMM/channel support unimplemented - */ - } - } - } else if (package_type == PT_C3) { - /* Socket C32 */ - if (pDCTstat->Status & (1 << SB_Registered)) { - /* RDIMM */ - /* Fam15h BKDG Rev. 3.14 section 2.10.5.3.4 Table 77 */ - if (MaxDimmsInstallable == 1) { - if ((MemClkFreq == 0x4) || (MemClkFreq == 0x6)) { - /* DDR3-667 - DDR3-800 */ - calibration_code = 0x00000000; - } else if (MemClkFreq == 0xa) { - /* DDR3-1066 */ - calibration_code = 0x003c3c3c; - } else if (MemClkFreq == 0xe) { - /* DDR3-1333 */ - calibration_code = 0x003a3a3a; - } else if ((MemClkFreq == 0x12) || (MemClkFreq == 0x16)) { - /* DDR3-1600 - DDR3-1866 */ - calibration_code = 0x00393939; - } - } else if (MaxDimmsInstallable == 2) { - if (dimm_count == 1) { - /* 1 DIMM detected */ - if ((MemClkFreq == 0x4) || (MemClkFreq == 0x6)) { - /* DDR3-667 - DDR3-800 */ - calibration_code = 0x00000000; - } else if (MemClkFreq == 0xa) { - /* DDR3-1066 */ - calibration_code = 0x00393c39; - } else if (MemClkFreq == 0xe) { - /* DDR3-1333 */ - calibration_code = 0x00373a37; - } else if (MemClkFreq == 0x12) { - /* DDR3-1600 */ - calibration_code = 0x00363936; - } - } else if (dimm_count == 2) { - /* 2 DIMMs detected */ - if ((MemClkFreq == 0x4) || (MemClkFreq == 0x6)) { - /* DDR3-667 - DDR3-800 */ - calibration_code = 0x00000000; - } else if (MemClkFreq == 0xa) { - /* DDR3-1066 */ - calibration_code = 0x003a3c3a; - } else if (MemClkFreq == 0xe) { - /* DDR3-1333 */ - calibration_code = 0x00383a38; - } else if (MemClkFreq == 0x12) { - /* DDR3-1600 */ - calibration_code = 0x00353935; - } - } - } else if (MaxDimmsInstallable == 3) { - /* TODO - * 3 DIMM/channel support unimplemented - */ - } - } else if (pDCTstat->Status & (1 << SB_LoadReduced)) { - /* LRDIMM */ - /* TODO - * LRDIMM support unimplemented - */ - } else { - /* UDIMM */ - /* Fam15h BKDG Rev. 3.14 section 2.10.5.3.4 Table 76 */ - if (MaxDimmsInstallable == 1) { - rank_count_dimm0 = pDCTstat->DimmRanks[(1 * 2) + dct]; - - if (MemClkFreq == 0x4) { - /* DDR3-667 */ - if (rank_count_dimm0 == 1) - calibration_code = 0x00000000; - else - calibration_code = 0x003b0000; - } else if (MemClkFreq == 0x6) { - /* DDR3-800 */ - if (rank_count_dimm0 == 1) - calibration_code = 0x00000000; - else - calibration_code = 0x003b0000; - } else if (MemClkFreq == 0xa) { - /* DDR3-1066 */ - calibration_code = 0x00383837; - } else if (MemClkFreq == 0xe) { - /* DDR3-1333 */ - calibration_code = 0x00363635; - } else if (MemClkFreq == 0x12) { - /* DDR3-1600 */ - if (rank_count_dimm0 == 1) - calibration_code = 0x00353533; - else - calibration_code = 0x00003533; - } else if (MemClkFreq == 0x16) { - /* DDR3-1866 */ - calibration_code = 0x00333330; - } - } else if (MaxDimmsInstallable == 2) { - if (dimm_count == 1) { - /* 1 DIMM detected */ - rank_count_dimm0 = pDCTstat->DimmRanks[(1 * 2) + dct]; - - if (MemClkFreq == 0x4) { - /* DDR3-667 */ - if (rank_count_dimm0 == 1) - calibration_code = 0x00000000; - else - calibration_code = 0x003b0000; - } else if (MemClkFreq == 0x6) { - /* DDR3-800 */ - if (rank_count_dimm0 == 1) - calibration_code = 0x00000000; - else - calibration_code = 0x003b0000; - } else if (MemClkFreq == 0xa) { - /* DDR3-1066 */ - calibration_code = 0x00383837; - } else if (MemClkFreq == 0xe) { - /* DDR3-1333 */ - calibration_code = 0x00363635; - } else if (MemClkFreq == 0x12) { - /* DDR3-1600 */ - if (rank_count_dimm0 == 1) - calibration_code = 0x00353533; - else - calibration_code = 0x00003533; - } - } else if (dimm_count == 2) { - /* 2 DIMMs detected */ - rank_count_dimm0 = pDCTstat->DimmRanks[(0 * 2) + dct]; - rank_count_dimm1 = pDCTstat->DimmRanks[(1 * 2) + dct]; - - if (MemClkFreq == 0x4) { - /* DDR3-667 */ - calibration_code = 0x00390039; - } else if (MemClkFreq == 0x6) { - /* DDR3-800 */ - calibration_code = 0x00390039; - } else if (MemClkFreq == 0xa) { - /* DDR3-1066 */ - calibration_code = 0x003a3a3a; - } else if (MemClkFreq == 0xe) { - /* DDR3-1333 */ - calibration_code = 0x00003939; - } else if (MemClkFreq == 0x12) { - /* DDR3-1600 */ - if ((rank_count_dimm0 == 1) && (rank_count_dimm1 == 1)) - calibration_code = 0x00003738; - } - } - } else if (MaxDimmsInstallable == 3) { - /* TODO - * 3 DIMM/channel support unimplemented - */ - } - } - } else if (package_type == PT_FM2) { - /* Socket FM2 */ - /* Assume UDIMM */ - /* Fam15h Model10h BKDG Rev. 3.12 section 2.9.5.6.6 Table 32 */ - if (dimm_count == 1) { - /* 1 DIMM detected */ - rank_count_dimm0 = pDCTstat->DimmRanks[(1 * 2) + dct]; - - if ((MemClkFreq == 0x4) || (MemClkFreq == 0x6)) { - /* DDR3-667 or DDR3-800 */ - if (rank_count_dimm0 == 1) - calibration_code = 0x00000000; - else - calibration_code = 0x003b0000; - } else if (MemClkFreq == 0xa) { - /* DDR3-1066 */ - if (rank_count_dimm0 == 1) - calibration_code = 0x00000000; - else - calibration_code = 0x00380000; - } else if (MemClkFreq == 0xe) { - /* DDR3-1333 */ - if (rank_count_dimm0 == 1) - calibration_code = 0x00000000; - else - calibration_code = 0x00360000; - } else if (MemClkFreq >= 0x12) { - /* DDR3-1600 or higher */ - calibration_code = 0x00000000; - } - - } else if (dimm_count == 2) { - /* 2 DIMMs detected */ - rank_count_dimm0 = pDCTstat->DimmRanks[(0 * 2) + dct]; - rank_count_dimm1 = pDCTstat->DimmRanks[(1 * 2) + dct]; - - if ((MemClkFreq == 0x4) || (MemClkFreq == 0x6)) { - /* DDR3-667 or DDR3-800 */ - calibration_code = 0x00390039; - } else if (MemClkFreq == 0xa) { - /* DDR3-1066 */ - calibration_code = 0x00350037; - } else if (MemClkFreq == 0xe) { - /* DDR3-1333 */ - calibration_code = 0x00000035; - } else if (MemClkFreq == 0x12) { - /* DDR3-1600 */ - calibration_code = 0x0000002b; - } else if (MemClkFreq > 0x12) { - /* DDR3-1866 or greater */ - calibration_code = 0x00000031; - } - } else if (MaxDimmsInstallable == 3) { - /* TODO - * 3 DIMM/channel support unimplemented - */ - } - } else { - /* TODO - * Other socket support unimplemented - */ - } - - return calibration_code; -} - -uint8_t fam15h_slow_access_mode(struct DCTStatStruc *pDCTstat, uint8_t dct) -{ - uint8_t MaxDimmsInstallable = mctGet_NVbits(NV_MAX_DIMMS_PER_CH); - - uint8_t package_type; - uint32_t slow_access = 0; - - package_type = mctGet_NVbits(NV_PACK_TYPE); - uint16_t MemClkFreq = Get_NB32_DCT(pDCTstat->dev_dct, dct, 0x94) & 0x1f; - - /* Obtain number of DIMMs on channel */ - uint8_t dimm_count = pDCTstat->MAdimms[dct]; - uint8_t rank_count_dimm0; - uint8_t rank_count_dimm1; - - if (package_type == PT_GR) { - /* Socket G34 */ - if (pDCTstat->Status & (1 << SB_Registered)) { - /* RDIMM */ - /* Fam15h BKDG Rev. 3.14 section 2.10.5.3.4 Table 74 */ - slow_access = 0; - } else if (pDCTstat->Status & (1 << SB_LoadReduced)) { - /* LRDIMM */ - /* Fam15h BKDG Rev. 3.14 section 2.10.5.3.4 Table 75 */ - slow_access = 0; - } else { - /* UDIMM */ - /* Fam15h BKDG Rev. 3.14 section 2.10.5.3.4 Table 73 */ - if (MaxDimmsInstallable == 1) { - rank_count_dimm0 = pDCTstat->DimmRanks[(1 * 2) + dct]; - - if ((MemClkFreq == 0x4) || (MemClkFreq == 0x6) - || (MemClkFreq == 0xa) | (MemClkFreq == 0xe)) { - /* DDR3-667 - DDR3-1333 */ - slow_access = 0; - } else if ((MemClkFreq == 0x12) || (MemClkFreq == 0x16)) { - /* DDR3-1600 - DDR3-1866 */ - if (rank_count_dimm0 == 1) - slow_access = 0; - else - slow_access = 1; - } - } else if (MaxDimmsInstallable == 2) { - if (dimm_count == 1) { - /* 1 DIMM detected */ - rank_count_dimm0 = pDCTstat->DimmRanks[(1 * 2) + dct]; - - if ((MemClkFreq == 0x4) || (MemClkFreq == 0x6) - || (MemClkFreq == 0xa) | (MemClkFreq == 0xe)) { - /* DDR3-667 - DDR3-1333 */ - slow_access = 0; - } else if (MemClkFreq == 0x12) { - /* DDR3-1600 */ - if (rank_count_dimm0 == 1) - slow_access = 0; - else - slow_access = 1; - } - } else if (dimm_count == 2) { - /* 2 DIMMs detected */ - rank_count_dimm0 = pDCTstat->DimmRanks[(0 * 2) + dct]; - rank_count_dimm1 = pDCTstat->DimmRanks[(1 * 2) + dct]; - - if ((MemClkFreq == 0x4) || (MemClkFreq == 0x6) - || (MemClkFreq == 0xa)) { - /* DDR3-667 - DDR3-1066 */ - slow_access = 0; - } else if ((MemClkFreq == 0xe) || (MemClkFreq == 0x12)) { - /* DDR3-1333 - DDR3-1600 */ - slow_access = 1; - } - } - } else if (MaxDimmsInstallable == 3) { - /* TODO - * 3 DIMM/channel support unimplemented - */ - } - } - } else if (package_type == PT_C3) { - /* Socket C32 */ - if (pDCTstat->Status & (1 << SB_Registered)) { - /* RDIMM */ - /* Fam15h BKDG Rev. 3.14 section 2.10.5.3.4 Table 77 */ - slow_access = 0; - } else if (pDCTstat->Status & (1 << SB_LoadReduced)) { - /* LRDIMM */ - /* Fam15h BKDG Rev. 3.14 section 2.10.5.3.4 Table 78 */ - slow_access = 0; - } else { - /* UDIMM */ - /* Fam15h BKDG Rev. 3.14 section 2.10.5.3.4 Table 76 */ - if (MaxDimmsInstallable == 1) { - rank_count_dimm0 = pDCTstat->DimmRanks[(1 * 2) + dct]; - - if ((MemClkFreq == 0x4) || (MemClkFreq == 0x6) - || (MemClkFreq == 0xa) | (MemClkFreq == 0xe)) { - /* DDR3-667 - DDR3-1333 */ - slow_access = 0; - } else if ((MemClkFreq == 0x12) || (MemClkFreq == 0x16)) { - /* DDR3-1600 - DDR3-1866 */ - if (rank_count_dimm0 == 1) - slow_access = 0; - else - slow_access = 1; - } - } else if (MaxDimmsInstallable == 2) { - if (dimm_count == 1) { - /* 1 DIMM detected */ - rank_count_dimm0 = pDCTstat->DimmRanks[(1 * 2) + dct]; - - if ((MemClkFreq == 0x4) || (MemClkFreq == 0x6) - || (MemClkFreq == 0xa) | (MemClkFreq == 0xe)) { - /* DDR3-667 - DDR3-1333 */ - slow_access = 0; - } else if (MemClkFreq == 0x12) { - /* DDR3-1600 */ - if (rank_count_dimm0 == 1) - slow_access = 0; - else - slow_access = 1; - } - } else if (dimm_count == 2) { - /* 2 DIMMs detected */ - rank_count_dimm0 = pDCTstat->DimmRanks[(0 * 2) + dct]; - rank_count_dimm1 = pDCTstat->DimmRanks[(1 * 2) + dct]; - - if ((MemClkFreq == 0x4) || (MemClkFreq == 0x6) - || (MemClkFreq == 0xa)) { - /* DDR3-667 - DDR3-1066 */ - slow_access = 0; - } else if ((MemClkFreq == 0xe) || (MemClkFreq == 0x12)) { - /* DDR3-1333 - DDR3-1600 */ - slow_access = 1; - } - } - } else if (MaxDimmsInstallable == 3) { - /* TODO - * 3 DIMM/channel support unimplemented - */ - } - } - } else if (package_type == PT_FM2) { - /* Socket FM2 */ - /* UDIMM */ - /* Fam15h Model10 BKDG Rev. 3.12 section 2.9.5.6.6 Table 32 */ - if (MaxDimmsInstallable == 1) { - rank_count_dimm0 = pDCTstat->DimmRanks[(1 * 2) + dct]; - - if ((MemClkFreq == 0x4) || (MemClkFreq == 0x6) - || (MemClkFreq == 0xa) | (MemClkFreq == 0xe)) { - /* DDR3-667 - DDR3-1333 */ - slow_access = 0; - } else if (MemClkFreq >= 0x12) { - /* DDR3-1600 or higher */ - if (rank_count_dimm0 == 1) - slow_access = 0; - else - slow_access = 1; - } - } else if (MaxDimmsInstallable == 2) { - if (dimm_count == 1) { - /* 1 DIMM detected */ - rank_count_dimm0 = pDCTstat->DimmRanks[(1 * 2) + dct]; - - if ((MemClkFreq == 0x4) || (MemClkFreq == 0x6) - || (MemClkFreq == 0xa) | (MemClkFreq == 0xe)) { - /* DDR3-667 - DDR3-1333 */ - slow_access = 0; - } else if (MemClkFreq >= 0x12) { - /* DDR3-1600 or higher */ - if (rank_count_dimm0 == 1) - slow_access = 0; - else - slow_access = 1; - } - } else if (dimm_count == 2) { - /* 2 DIMMs detected */ - rank_count_dimm0 = pDCTstat->DimmRanks[(0 * 2) + dct]; - rank_count_dimm1 = pDCTstat->DimmRanks[(1 * 2) + dct]; - - if ((MemClkFreq == 0x4) || (MemClkFreq == 0x6) - || (MemClkFreq == 0xa)) { - /* DDR3-667 - DDR3-1066 */ - slow_access = 0; - } else if (MemClkFreq >= 0xe) { - /* DDR3-1333 or higher */ - slow_access = 1; - } - } - } else if (MaxDimmsInstallable == 3) { - /* TODO - * 3 DIMM/channel support unimplemented - */ - } - } else { - /* TODO - * Other socket support unimplemented - */ - } - - return slow_access; -} - -static uint8_t fam15h_odt_tristate_enable_code(struct DCTStatStruc *pDCTstat, uint8_t dct) -{ - uint8_t MaxDimmsInstallable = mctGet_NVbits(NV_MAX_DIMMS_PER_CH); - - uint8_t package_type; - uint8_t odt_tristate_code = 0; - - package_type = mctGet_NVbits(NV_PACK_TYPE); - - /* Obtain number of DIMMs on channel */ - uint8_t dimm_count = pDCTstat->MAdimms[dct]; - uint8_t rank_count_dimm0; - uint8_t rank_count_dimm1; - - if (package_type == PT_GR) { - /* Socket G34 */ - if (pDCTstat->Status & (1 << SB_Registered)) { - /* RDIMM */ - /* Fam15h BKDG Rev. 3.14 section 2.10.5.10.1 Table 104 */ - if (MaxDimmsInstallable == 1) { - rank_count_dimm0 = pDCTstat->DimmRanks[(1 * 2) + dct]; - - if (rank_count_dimm0 == 1) - odt_tristate_code = 0xe; - else - odt_tristate_code = 0xa; - } else if (MaxDimmsInstallable == 2) { - if (dimm_count == 1) { - /* 1 DIMM detected */ - rank_count_dimm1 = pDCTstat->DimmRanks[(1 * 2) + dct]; - - if (rank_count_dimm1 == 1) - odt_tristate_code = 0xd; - else - odt_tristate_code = 0x5; - } else if (dimm_count == 2) { - /* 2 DIMMs detected */ - rank_count_dimm0 = pDCTstat->DimmRanks[(0 * 2) + dct]; - rank_count_dimm1 = pDCTstat->DimmRanks[(1 * 2) + dct]; - - if ((rank_count_dimm0 == 1) && (rank_count_dimm1 == 1)) - odt_tristate_code = 0xc; - else if ((rank_count_dimm0 == 1) && (rank_count_dimm1 >= 2)) - odt_tristate_code = 0x4; - else if ((rank_count_dimm0 >= 2) && (rank_count_dimm1 == 1)) - odt_tristate_code = 0x8; - else - odt_tristate_code = 0x0; - } - } else if (MaxDimmsInstallable == 3) { - /* TODO - * 3 DIMM/channel support unimplemented - */ - } - } else if (pDCTstat->Status & (1 << SB_LoadReduced)) { - /* LRDIMM */ - - /* TODO - * Implement LRDIMM support - * See Fam15h BKDG Rev. 3.14 section 2.10.5.10.1 Table 105 - */ - } else { - /* UDIMM */ - /* Fam15h BKDG Rev. 3.14 section 2.10.5.10.1 Table 103 */ - if (MaxDimmsInstallable == 1) { - rank_count_dimm0 = pDCTstat->DimmRanks[(1 * 2) + dct]; - - if (rank_count_dimm0 == 1) - odt_tristate_code = 0xe; - else - odt_tristate_code = 0xa; - } else if (MaxDimmsInstallable == 2) { - if (dimm_count == 1) { - /* 1 DIMM detected */ - rank_count_dimm0 = pDCTstat->DimmRanks[(1 * 2) + dct]; - - if (rank_count_dimm0 == 1) - odt_tristate_code = 0xd; - else - odt_tristate_code = 0x5; - } else if (dimm_count == 2) { - /* 2 DIMMs detected */ - rank_count_dimm0 = pDCTstat->DimmRanks[(0 * 2) + dct]; - rank_count_dimm1 = pDCTstat->DimmRanks[(1 * 2) + dct]; - - if ((rank_count_dimm0 == 1) && (rank_count_dimm1 == 1)) - odt_tristate_code = 0xc; - else if ((rank_count_dimm0 == 1) && (rank_count_dimm1 == 2)) - odt_tristate_code = 0x4; - else if ((rank_count_dimm0 == 2) && (rank_count_dimm1 == 1)) - odt_tristate_code = 0x8; - else - odt_tristate_code = 0x0; - } - } else if (MaxDimmsInstallable == 3) { - /* TODO - * 3 DIMM/channel support unimplemented - */ - } - } - } else if (package_type == PT_C3) { - /* Socket C32 */ - if (pDCTstat->Status & (1 << SB_Registered)) { - /* RDIMM */ - /* Fam15h BKDG Rev. 3.14 section 2.10.5.10.1 Table 107 */ - if (MaxDimmsInstallable == 1) { - rank_count_dimm0 = pDCTstat->DimmRanks[(1 * 2) + dct]; - - if (rank_count_dimm0 == 1) - odt_tristate_code = 0xe; - else - odt_tristate_code = 0xa; - } else if (MaxDimmsInstallable == 2) { - if (dimm_count == 1) { - /* 1 DIMM detected */ - rank_count_dimm1 = pDCTstat->DimmRanks[(1 * 2) + dct]; - - if (rank_count_dimm1 == 1) - odt_tristate_code = 0xd; - else - odt_tristate_code = 0x5; - } else if (dimm_count == 2) { - /* 2 DIMMs detected */ - rank_count_dimm0 = pDCTstat->DimmRanks[(0 * 2) + dct]; - rank_count_dimm1 = pDCTstat->DimmRanks[(1 * 2) + dct]; - - if ((rank_count_dimm0 == 1) && (rank_count_dimm1 == 1)) - odt_tristate_code = 0xc; - else if ((rank_count_dimm0 == 1) && (rank_count_dimm1 >= 2)) - odt_tristate_code = 0x4; - else if ((rank_count_dimm0 >= 2) && (rank_count_dimm1 == 1)) - odt_tristate_code = 0x8; - else - odt_tristate_code = 0x0; - } - } else if (MaxDimmsInstallable == 3) { - /* TODO - * 3 DIMM/channel support unimplemented - */ - } - } else if (pDCTstat->Status & (1 << SB_LoadReduced)) { - /* LRDIMM */ - - /* TODO - * Implement LRDIMM support - * See Fam15h BKDG Rev. 3.14 section 2.10.5.10.1 Table 108 - */ - } else { - /* UDIMM */ - /* Fam15h BKDG Rev. 3.14 section 2.10.5.10.1 Table 106 */ - if (MaxDimmsInstallable == 1) { - rank_count_dimm0 = pDCTstat->DimmRanks[(1 * 2) + dct]; - - if (rank_count_dimm0 == 1) - odt_tristate_code = 0xe; - else - odt_tristate_code = 0xa; - } else if (MaxDimmsInstallable == 2) { - if (dimm_count == 1) { - /* 1 DIMM detected */ - rank_count_dimm0 = pDCTstat->DimmRanks[(1 * 2) + dct]; - - if (rank_count_dimm0 == 1) - odt_tristate_code = 0xd; - else - odt_tristate_code = 0x5; - } else if (dimm_count == 2) { - /* 2 DIMMs detected */ - rank_count_dimm0 = pDCTstat->DimmRanks[(0 * 2) + dct]; - rank_count_dimm1 = pDCTstat->DimmRanks[(1 * 2) + dct]; - - if ((rank_count_dimm0 == 1) && (rank_count_dimm1 == 1)) - odt_tristate_code = 0xc; - else if ((rank_count_dimm0 == 1) && (rank_count_dimm1 == 2)) - odt_tristate_code = 0x4; - else if ((rank_count_dimm0 == 2) && (rank_count_dimm1 == 1)) - odt_tristate_code = 0x8; - else - odt_tristate_code = 0x0; - } - } else if (MaxDimmsInstallable == 3) { - /* TODO - * 3 DIMM/channel support unimplemented - */ - } - } - } else if (package_type == PT_FM2) { - /* Socket FM2 */ - /* UDIMM */ - odt_tristate_code = 0x0; - } else { - /* TODO - * Other socket support unimplemented - */ - } - - return odt_tristate_code; -} - -static uint8_t fam15h_cs_tristate_enable_code(struct DCTStatStruc *pDCTstat, uint8_t dct) -{ - uint8_t MaxDimmsInstallable = mctGet_NVbits(NV_MAX_DIMMS_PER_CH); - - uint8_t package_type; - uint8_t cs_tristate_code = 0; - - package_type = mctGet_NVbits(NV_PACK_TYPE); - - /* Obtain number of DIMMs on channel */ - uint8_t dimm_count = pDCTstat->MAdimms[dct]; - uint8_t rank_count_dimm0; - uint8_t rank_count_dimm1; - - if (package_type == PT_GR) { - /* Socket G34 */ - if (pDCTstat->Status & (1 << SB_Registered)) { - /* RDIMM */ - /* Fam15h BKDG Rev. 3.14 section 2.10.5.10.1 Table 104 */ - if (MaxDimmsInstallable == 1) { - rank_count_dimm0 = pDCTstat->DimmRanks[(1 * 2) + dct]; - - if (rank_count_dimm0 < 4) - cs_tristate_code = 0xfc; - else - cs_tristate_code = 0xcc; - } else if (MaxDimmsInstallable == 2) { - if (dimm_count == 1) { - /* 1 DIMM detected */ - rank_count_dimm1 = pDCTstat->DimmRanks[(1 * 2) + dct]; - - if (rank_count_dimm1 < 4) - cs_tristate_code = 0xf3; - else - cs_tristate_code = 0x33; - } else if (dimm_count == 2) { - /* 2 DIMMs detected */ - rank_count_dimm0 = pDCTstat->DimmRanks[(0 * 2) + dct]; - rank_count_dimm1 = pDCTstat->DimmRanks[(1 * 2) + dct]; - - if ((rank_count_dimm0 < 4) && (rank_count_dimm1 < 4)) - cs_tristate_code = 0xf0; - else if ((rank_count_dimm0 < 4) && (rank_count_dimm1 == 4)) - cs_tristate_code = 0x30; - else if ((rank_count_dimm0 == 4) && (rank_count_dimm1 < 4)) - cs_tristate_code = 0xc0; - else - cs_tristate_code = 0x0; - } - } else if (MaxDimmsInstallable == 3) { - /* TODO - * 3 DIMM/channel support unimplemented - */ - } - } else if (pDCTstat->Status & (1 << SB_LoadReduced)) { - /* LRDIMM */ - - /* TODO - * Implement LRDIMM support - * See Fam15h BKDG Rev. 3.14 section 2.10.5.10.1 Table 105 - */ - } else { - /* UDIMM */ - /* Fam15h BKDG Rev. 3.14 section 2.10.5.10.1 Table 103 */ - if (MaxDimmsInstallable == 1) { - rank_count_dimm0 = pDCTstat->DimmRanks[(1 * 2) + dct]; - - if (rank_count_dimm0 == 1) - cs_tristate_code = 0xfe; - else - cs_tristate_code = 0xfc; - } else if (MaxDimmsInstallable == 2) { - if (dimm_count == 1) { - /* 1 DIMM detected */ - rank_count_dimm0 = pDCTstat->DimmRanks[(1 * 2) + dct]; - - if (rank_count_dimm0 == 1) - cs_tristate_code = 0xfb; - else - cs_tristate_code = 0xf3; - } else if (dimm_count == 2) { - /* 2 DIMMs detected */ - rank_count_dimm0 = pDCTstat->DimmRanks[(0 * 2) + dct]; - rank_count_dimm1 = pDCTstat->DimmRanks[(1 * 2) + dct]; - - if ((rank_count_dimm0 == 1) && (rank_count_dimm1 == 1)) - cs_tristate_code = 0xfa; - else if ((rank_count_dimm0 == 1) && (rank_count_dimm1 == 2)) - cs_tristate_code = 0xf2; - else if ((rank_count_dimm0 == 2) && (rank_count_dimm1 == 1)) - cs_tristate_code = 0xf8; - else - cs_tristate_code = 0xf0; - } - } else if (MaxDimmsInstallable == 3) { - /* TODO - * 3 DIMM/channel support unimplemented - */ - } - } - } else if (package_type == PT_C3) { - /* Socket C32 */ - if (pDCTstat->Status & (1 << SB_Registered)) { - /* RDIMM */ - /* Fam15h BKDG Rev. 3.14 section 2.10.5.10.1 Table 107 */ - if (MaxDimmsInstallable == 1) { - rank_count_dimm0 = pDCTstat->DimmRanks[(1 * 2) + dct]; - - if (rank_count_dimm0 < 4) - cs_tristate_code = 0xfc; - else - cs_tristate_code = 0xcc; - } else if (MaxDimmsInstallable == 2) { - if (dimm_count == 1) { - /* 1 DIMM detected */ - rank_count_dimm1 = pDCTstat->DimmRanks[(1 * 2) + dct]; - - if (rank_count_dimm1 < 4) - cs_tristate_code = 0xf3; - else - cs_tristate_code = 0x33; - } else if (dimm_count == 2) { - /* 2 DIMMs detected */ - rank_count_dimm0 = pDCTstat->DimmRanks[(0 * 2) + dct]; - rank_count_dimm1 = pDCTstat->DimmRanks[(1 * 2) + dct]; - - if ((rank_count_dimm0 < 4) && (rank_count_dimm1 < 4)) - cs_tristate_code = 0xf0; - else if ((rank_count_dimm0 < 4) && (rank_count_dimm1 == 4)) - cs_tristate_code = 0x30; - else if ((rank_count_dimm0 == 4) && (rank_count_dimm1 < 4)) - cs_tristate_code = 0xc0; - else - cs_tristate_code = 0x0; - } - } else if (MaxDimmsInstallable == 3) { - /* TODO - * 3 DIMM/channel support unimplemented - */ - } - } else if (pDCTstat->Status & (1 << SB_LoadReduced)) { - /* LRDIMM */ - - /* TODO - * Implement LRDIMM support - * See Fam15h BKDG Rev. 3.14 section 2.10.5.10.1 Table 108 - */ - } else { - /* UDIMM */ - /* Fam15h BKDG Rev. 3.14 section 2.10.5.10.1 Table 106 */ - if (MaxDimmsInstallable == 1) { - rank_count_dimm0 = pDCTstat->DimmRanks[(1 * 2) + dct]; - - if (rank_count_dimm0 == 1) - cs_tristate_code = 0xfe; - else - cs_tristate_code = 0xfc; - } else if (MaxDimmsInstallable == 2) { - if (dimm_count == 1) { - /* 1 DIMM detected */ - rank_count_dimm0 = pDCTstat->DimmRanks[(1 * 2) + dct]; - - if (rank_count_dimm0 == 1) - cs_tristate_code = 0xfb; - else - cs_tristate_code = 0xf3; - } else if (dimm_count == 2) { - /* 2 DIMMs detected */ - rank_count_dimm0 = pDCTstat->DimmRanks[(0 * 2) + dct]; - rank_count_dimm1 = pDCTstat->DimmRanks[(1 * 2) + dct]; - - if ((rank_count_dimm0 == 1) && (rank_count_dimm1 == 1)) - cs_tristate_code = 0xfa; - else if ((rank_count_dimm0 == 1) && (rank_count_dimm1 == 2)) - cs_tristate_code = 0xf2; - else if ((rank_count_dimm0 == 2) && (rank_count_dimm1 == 1)) - cs_tristate_code = 0xf8; - else - cs_tristate_code = 0xf0; - } - } else if (MaxDimmsInstallable == 3) { - /* TODO - * 3 DIMM/channel support unimplemented - */ - } - } - } else if (package_type == PT_FM2) { - /* Socket FM2 */ - /* UDIMM */ - cs_tristate_code = 0x0; - } else { - /* TODO - * Other socket support unimplemented - */ - } - - return cs_tristate_code; -} - -void set_2t_configuration(struct MCTStatStruc *pMCTstat, - struct DCTStatStruc *pDCTstat, u8 dct) -{ - printk(BIOS_DEBUG, "%s: Start\n", __func__); - - uint32_t dev; - uint32_t reg; - uint32_t dword; - - uint8_t enable_slow_access_mode = 0; - dev = pDCTstat->dev_dct; - - if (is_fam15h()) { - if (pDCTstat->_2Tmode) - enable_slow_access_mode = 1; - } else { - if (pDCTstat->_2Tmode == 2) - enable_slow_access_mode = 1; - } - - reg = 0x94; /* DRAM Configuration High */ - dword = Get_NB32_DCT(dev, dct, reg); - if (enable_slow_access_mode) - dword |= (0x1 << 20); /* Set 2T CMD mode */ - else - dword &= ~(0x1 << 20); /* Clear 2T CMD mode */ - Set_NB32_DCT(dev, dct, reg, dword); - - printk(BIOS_DEBUG, "%s: Done\n", __func__); -} - -void precise_ndelay_fam15(struct MCTStatStruc *pMCTstat, uint32_t nanoseconds) { - msr_t tsc_msr; - uint64_t cycle_count = (((uint64_t)pMCTstat->TSCFreq) * nanoseconds) / 1000; - uint64_t start_timestamp; - uint64_t current_timestamp; - - tsc_msr = rdmsr(TSC_MSR); - start_timestamp = (((uint64_t)tsc_msr.hi) << 32) | tsc_msr.lo; - do { - tsc_msr = rdmsr(TSC_MSR); - current_timestamp = (((uint64_t)tsc_msr.hi) << 32) | tsc_msr.lo; - } while ((current_timestamp - start_timestamp) < cycle_count); -} - -void precise_memclk_delay_fam15(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstat, uint8_t dct, uint32_t clocks) { - uint16_t memclk_freq; - uint32_t delay_ns; - uint16_t fam15h_freq_tab[] = {0, 0, 0, 0, 333, 0, 400, 0, 0, 0, 533, 0, 0, 0, 667, 0, 0, 0, 800, 0, 0, 0, 933}; - - memclk_freq = Get_NB32_DCT(pDCTstat->dev_dct, dct, 0x94) & 0x1f; - - if (fam15h_freq_tab[memclk_freq] == 0) { - printk(BIOS_DEBUG, "ERROR: precise_memclk_delay_fam15 for DCT %d (delay %d clocks) failed to obtain valid memory frequency!" - " (pDCTstat: %p pDCTstat->dev_dct: %08x memclk_freq: %02x)\n", dct, clocks, pDCTstat, pDCTstat->dev_dct, memclk_freq); - } - delay_ns = (((uint64_t)clocks * 1000) / fam15h_freq_tab[memclk_freq]); - precise_ndelay_fam15(pMCTstat, delay_ns); -} - -static void read_spd_bytes(struct MCTStatStruc *pMCTstat, - struct DCTStatStruc *pDCTstat, uint8_t dimm) -{ - uint8_t addr; - uint16_t byte; - - addr = Get_DIMMAddress_D(pDCTstat, dimm); - pDCTstat->spd_data.spd_address[dimm] = addr; - - for (byte = 0; byte < 256; byte++) { - pDCTstat->spd_data.spd_bytes[dimm][byte] = mctRead_SPD(addr, byte); - } -} - -#ifdef DEBUG_DIMM_SPD -static void dump_spd_bytes(struct MCTStatStruc *pMCTstat, - struct DCTStatStruc *pDCTstat, uint8_t dimm) -{ - uint16_t byte; - - printk(BIOS_DEBUG, "SPD dump for DIMM %d\n ", dimm); - for (byte = 0; byte < 16; byte++) { - printk(BIOS_DEBUG, "%02x ", byte); - } - for (byte = 0; byte < 256; byte++) { - if ((byte & 0xf) == 0x0) { - printk(BIOS_DEBUG, "\n%02x ", byte >> 4); - } - printk(BIOS_DEBUG, "%02x ", pDCTstat->spd_data.spd_bytes[dimm][byte]); - } - printk(BIOS_DEBUG, "\n"); -} -#endif - -static void set_up_cc6_storage_fam15(struct MCTStatStruc *pMCTstat, - struct DCTStatStruc *pDCTstat, uint8_t num_nodes) -{ - uint8_t interleaved; - uint8_t destination_node; - int8_t range; - int8_t max_range; - uint8_t max_node; - uint64_t max_range_limit; - uint8_t byte; - uint32_t dword; - uint32_t dword2; - uint64_t qword; - - interleaved = 0; - if (pMCTstat->GStatus & (1 << GSB_NodeIntlv)) - interleaved = 1; - - printk(BIOS_INFO, - "%s: Initializing CC6 DRAM storage area for node %d" - " (interleaved: %d)\n", - __func__, pDCTstat->Node_ID, interleaved); - - /* Find highest DRAM range (DramLimitAddr) */ - max_node = 0; - max_range = -1; - max_range_limit = 0; - for (range = 0; range < 8; range++) { - dword = Get_NB32(pDCTstat->dev_map, 0x40 + (range * 0x8)); - if (!(dword & 0x3)) - continue; - - dword = Get_NB32(pDCTstat->dev_map, 0x44 + (range * 0x8)); - dword2 = Get_NB32(pDCTstat->dev_map, 0x144 + (range * 0x8)); - qword = 0xffffff; - qword |= ((((uint64_t)dword) >> 16) & 0xffff) << 24; - qword |= (((uint64_t)dword2) & 0xff) << 40; - - if (qword > max_range_limit) { - max_range = range; - max_range_limit = qword; - max_node = dword & 0x7; - } - } - - if (max_range >= 0) { - printk(BIOS_INFO, - "%s:\toriginal (node %d) max_range_limit: %16llx DRAM" - " limit: %16llx\n", - __func__, max_node, max_range_limit, - (((uint64_t)(Get_NB32(pDCTstat->dev_map, 0x124) - & 0x1fffff)) << 27) | 0x7ffffff); - - if (interleaved) - /* Move upper limit down by 16M * the number of nodes */ - max_range_limit -= (0x1000000ULL * num_nodes); - else - /* Move upper limit down by 16M */ - max_range_limit -= 0x1000000ULL; - - printk(BIOS_INFO, "%s:\tnew max_range_limit: %16llx\n", - __func__, max_range_limit); - - /* Disable the range */ - dword = Get_NB32(pDCTstat->dev_map, 0x40 + (max_range * 0x8)); - byte = dword & 0x3; - dword &= ~(0x3); - Set_NB32(pDCTstat->dev_map, 0x40 + (max_range * 0x8), dword); - - /* Store modified range */ - dword = Get_NB32(pDCTstat->dev_map, 0x44 + (max_range * 0x8)); - dword &= ~(0xffff << 16); /* DramLimit[39:24] = max_range_limit[39:24] */ - dword |= ((max_range_limit >> 24) & 0xffff) << 16; - Set_NB32(pDCTstat->dev_map, 0x44 + (max_range * 0x8), dword); - - dword = Get_NB32(pDCTstat->dev_map, 0x144 + (max_range * 0x8)); - dword &= ~0xff; /* DramLimit[47:40] = max_range_limit[47:40] */ - dword |= (max_range_limit >> 40) & 0xff; - Set_NB32(pDCTstat->dev_map, 0x144 + (max_range * 0x8), dword); - - /* Reenable the range */ - dword = Get_NB32(pDCTstat->dev_map, 0x40 + (max_range * 0x8)); - dword |= byte; - Set_NB32(pDCTstat->dev_map, 0x40 + (max_range * 0x8), dword); - } - - /* Determine save state destination node */ - if (interleaved) - destination_node = Get_NB32(pDCTstat->dev_host, 0x60) & 0x7; - else - destination_node = max_node; - - /* Set save state destination node */ - dword = Get_NB32(pDCTstat->dev_link, 0x128); - dword &= ~(0x3f << 12); /* CoreSaveStateDestNode = destination_node */ - dword |= (destination_node & 0x3f) << 12; - Set_NB32(pDCTstat->dev_link, 0x128, dword); - - printk(BIOS_INFO, "%s:\tTarget node: %d\n", __func__, destination_node); - - printk(BIOS_INFO, "%s:\tDone\n", __func__); -} - -static void lock_dram_config(struct MCTStatStruc *pMCTstat, - struct DCTStatStruc *pDCTstat) -{ - uint32_t dword; - - dword = Get_NB32(pDCTstat->dev_dct, 0x118); - dword |= 0x1 << 19; /* LockDramCfg = 1 */ - Set_NB32(pDCTstat->dev_dct, 0x118, dword); -} - -static void set_cc6_save_enable(struct MCTStatStruc *pMCTstat, - struct DCTStatStruc *pDCTstat, uint8_t enable) -{ - uint32_t dword; - - dword = Get_NB32(pDCTstat->dev_dct, 0x118); - dword &= ~(0x1 << 18); /* CC6SaveEn = enable */ - dword |= (enable & 0x1) << 18; - Set_NB32(pDCTstat->dev_dct, 0x118, dword); -} - -void mctAutoInitMCT_D(struct MCTStatStruc *pMCTstat, - struct DCTStatStruc *pDCTstatA) -{ - /* - * Memory may be mapped contiguously all the way up to 4GB (depending on setup - * options). It is the responsibility of PCI subsystem to create an uncacheable - * IO region below 4GB and to adjust TOP_MEM downward prior to any IO mapping or - * accesses. It is the same responsibility of the CPU sub-system prior to - * accessing LAPIC. - * - * Slot Number is an external convention, and is determined by OEM with accompanying - * silk screening. OEM may choose to use Slot number convention which is consistent - * with DIMM number conventions. All AMD engineering platforms do. - * - * Build Requirements: - * 1. MCT_SEG0_START and MCT_SEG0_END macros to begin and end the code segment, - * defined in mcti.inc. - * - * Run-Time Requirements: - * 1. Complete Hypertransport Bus Configuration - * 2. SMBus Controller Initialized - * 1. BSP in Big Real Mode - * 2. Stack at SS:SP, located somewhere between A000:0000 and F000:FFFF - * 3. Checksummed or Valid NVRAM bits - * 4. MCG_CTL = -1, MC4_CTL_EN = 0 for all CPUs - * 5. MCi_STS from shutdown/warm reset recorded (if desired) prior to entry - * 6. All var MTRRs reset to zero - * 7. State of NB_CFG.DisDatMsk set properly on all CPUs - * 8. All CPUs at 2GHz Speed (unless DQS training is not installed). - * 9. All cHT links at max Speed/Width (unless DQS training is not installed). - * - * - * Global relationship between index values and item values: - * - * pDCTstat.CASL pDCTstat.Speed - * j CL(j) k F(k) - * -------------------------- - * 0 2.0 - - - * 1 3.0 1 200 MHz - * 2 4.0 2 266 MHz - * 3 5.0 3 333 MHz - * 4 6.0 4 400 MHz - * 5 7.0 5 533 MHz - * 6 8.0 6 667 MHz - * 7 9.0 7 800 MHz - */ - u8 Node, NodesWmem; - u32 node_sys_base; - uint8_t dimm; - uint8_t nvram; - uint8_t enable_cc6; - uint8_t ecc_enabled; - uint8_t allow_config_restore; - - uint8_t s3resume = acpi_is_wakeup_s3(); - -restartinit: - - if (!mctGet_NVbits(NV_ECC_CAP) || !mctGet_NVbits(NV_ECC)) - pMCTstat->try_ecc = 0; - else - pMCTstat->try_ecc = 1; - - mctInitMemGPIOs_A_D(); /* Set any required GPIOs*/ - if (s3resume) { - printk(BIOS_DEBUG, "mctAutoInitMCT_D: mct_ForceNBPState0_En_Fam15\n"); - for (Node = 0; Node < MAX_NODES_SUPPORTED; Node++) { - struct DCTStatStruc *pDCTstat; - pDCTstat = pDCTstatA + Node; - - mct_ForceNBPState0_En_Fam15(pMCTstat, pDCTstat); - } - -#if CONFIG(HAVE_ACPI_RESUME) - printk(BIOS_DEBUG, "mctAutoInitMCT_D: Restoring DCT configuration from NVRAM\n"); - if (restore_mct_information_from_nvram(0) != 0) - printk(BIOS_CRIT, "%s: ERROR: Unable to restore DCT configuration from NVRAM\n", __func__); - pMCTstat->GStatus |= 1 << GSB_ConfigRestored; -#endif - - if (is_fam15h()) { - printk(BIOS_DEBUG, "mctAutoInitMCT_D: mct_ForceNBPState0_Dis_Fam15\n"); - for (Node = 0; Node < MAX_NODES_SUPPORTED; Node++) { - struct DCTStatStruc *pDCTstat; - pDCTstat = pDCTstatA + Node; - - mct_ForceNBPState0_Dis_Fam15(pMCTstat, pDCTstat); - } - } - } else { - NodesWmem = 0; - node_sys_base = 0; - for (Node = 0; Node < MAX_NODES_SUPPORTED; Node++) { - struct DCTStatStruc *pDCTstat; - pDCTstat = pDCTstatA + Node; - - /* Zero out data structures to avoid false detection of DIMMs */ - memset(pDCTstat, 0, sizeof(struct DCTStatStruc)); - - /* Initialize data structures */ - pDCTstat->Node_ID = Node; - pDCTstat->dev_host = PA_HOST(Node); - pDCTstat->dev_map = PA_MAP(Node); - pDCTstat->dev_dct = PA_DCT(Node); - pDCTstat->dev_nbmisc = PA_NBMISC(Node); - pDCTstat->dev_link = PA_LINK(Node); - pDCTstat->dev_nbctl = PA_NBCTL(Node); - pDCTstat->NodeSysBase = node_sys_base; - - if (mctGet_NVbits(NV_PACK_TYPE) == PT_GR) { - uint32_t dword; - pDCTstat->Dual_Node_Package = 1; - - /* Get the internal node number */ - dword = Get_NB32(pDCTstat->dev_nbmisc, 0xe8); - dword = (dword >> 30) & 0x3; - pDCTstat->Internal_Node_ID = dword; - } else { - pDCTstat->Dual_Node_Package = 0; - } - - printk(BIOS_DEBUG, "%s: mct_init Node %d\n", __func__, Node); - mct_init(pMCTstat, pDCTstat); - mctNodeIDDebugPort_D(); - pDCTstat->NodePresent = NodePresent_D(Node); - if (pDCTstat->NodePresent) { - pDCTstat->LogicalCPUID = mctGetLogicalCPUID_D(Node); - - printk(BIOS_DEBUG, "%s: mct_InitialMCT_D\n", __func__); - mct_InitialMCT_D(pMCTstat, pDCTstat); - - printk(BIOS_DEBUG, "%s: mctSMBhub_Init\n", __func__); - mctSMBhub_Init(Node); /* Switch SMBUS crossbar to proper node */ - - printk(BIOS_DEBUG, "%s: mct_preInitDCT\n", __func__); - mct_preInitDCT(pMCTstat, pDCTstat); - } - node_sys_base = pDCTstat->NodeSysBase; - node_sys_base += (pDCTstat->NodeSysLimit + 2) & ~0x0F; - } - - /* If the boot fails make sure training is attempted after reset */ - nvram = 0; - set_option("allow_spd_nvram_cache_restore", &nvram); - -#if CONFIG(DIMM_VOLTAGE_SET_SUPPORT) - printk(BIOS_DEBUG, "%s: DIMMSetVoltage\n", __func__); - DIMMSetVoltages(pMCTstat, pDCTstatA); /* Set the DIMM voltages (mainboard specific) */ -#endif - if (!CONFIG(DIMM_VOLTAGE_SET_SUPPORT)) { - /* Assume 1.5V operation */ - for (Node = 0; Node < MAX_NODES_SUPPORTED; Node++) { - struct DCTStatStruc *pDCTstat; - pDCTstat = pDCTstatA + Node; - - if (!pDCTstat->NodePresent) - continue; - - for (dimm = 0; dimm < MAX_DIMMS_SUPPORTED; dimm++) { - if (pDCTstat->DIMMValid & (1 << dimm)) - pDCTstat->DimmConfiguredVoltage[dimm] = 0x1; - } - } - } - - /* If DIMM configuration has not changed since last boot restore training values */ - allow_config_restore = 1; - for (Node = 0; Node < MAX_NODES_SUPPORTED; Node++) { - struct DCTStatStruc *pDCTstat; - pDCTstat = pDCTstatA + Node; - - if (pDCTstat->NodePresent) - if (!pDCTstat->spd_data.nvram_spd_match) - allow_config_restore = 0; - } - - /* FIXME - * Stability issues have arisen on multiple Family 15h systems - * when configuration restoration is enabled. In all cases these - * stability issues resolved by allowing the RAM to go through a - * full training cycle. - * - * Debug and reenable this! - */ - allow_config_restore = 0; - - for (Node = 0; Node < MAX_NODES_SUPPORTED; Node++) { - struct DCTStatStruc *pDCTstat; - pDCTstat = pDCTstatA + Node; - - if (pDCTstat->NodePresent) { - printk(BIOS_DEBUG, "%s: mctSMBhub_Init\n", __func__); - mctSMBhub_Init(Node); /* Switch SMBUS crossbar to proper node*/ - - printk(BIOS_DEBUG, "%s: mct_initDCT\n", __func__); - mct_initDCT(pMCTstat, pDCTstat); - if (pDCTstat->ErrCode == SC_FatalErr) { - goto fatalexit; /* any fatal errors?*/ - } else if (pDCTstat->ErrCode < SC_StopError) { - NodesWmem++; - } - } - } - if (NodesWmem == 0) { - printk(BIOS_ALERT, "Unable to detect valid memory on any nodes. Halting!\n"); - goto fatalexit; - } - - printk(BIOS_DEBUG, "mctAutoInitMCT_D: SyncDCTsReady_D\n"); - SyncDCTsReady_D(pMCTstat, pDCTstatA); /* Make sure DCTs are ready for accesses.*/ - - printk(BIOS_DEBUG, "mctAutoInitMCT_D: HTMemMapInit_D\n"); - HTMemMapInit_D(pMCTstat, pDCTstatA); /* Map local memory into system address space.*/ - mctHookAfterHTMap(); - - if (!is_fam15h()) { - printk(BIOS_DEBUG, "mctAutoInitMCT_D: CPUMemTyping_D\n"); - CPUMemTyping_D(pMCTstat, pDCTstatA); /* Map dram into WB/UC CPU cacheability */ - } - - printk(BIOS_DEBUG, "mctAutoInitMCT_D: mctHookAfterCPU\n"); - mctHookAfterCPU(); /* Setup external northbridge(s) */ - - /* FIXME - * Previous training values should only be used if the current desired - * speed is the same as the speed used in the previous boot. - * How to get the desired speed at this point in the code? - */ - - printk(BIOS_DEBUG, "mctAutoInitMCT_D: DQSTiming_D\n"); - DQSTiming_D(pMCTstat, pDCTstatA, allow_config_restore); /* Get Receiver Enable and DQS signal timing*/ - - if (!is_fam15h()) { - printk(BIOS_DEBUG, "mctAutoInitMCT_D: UMAMemTyping_D\n"); - UMAMemTyping_D(pMCTstat, pDCTstatA); /* Fix up for UMA sizing */ - } - - if (!allow_config_restore) { - printk(BIOS_DEBUG, "mctAutoInitMCT_D: :OtherTiming\n"); - mct_OtherTiming(pMCTstat, pDCTstatA); - } - - if (ReconfigureDIMMspare_D(pMCTstat, pDCTstatA)) { /* RESET# if 1st pass of DIMM spare enabled*/ - goto restartinit; - } - - InterleaveNodes_D(pMCTstat, pDCTstatA); - InterleaveChannels_D(pMCTstat, pDCTstatA); - - ecc_enabled = 1; - for (Node = 0; Node < MAX_NODES_SUPPORTED; Node++) { - struct DCTStatStruc *pDCTstat; - pDCTstat = pDCTstatA + Node; - - if (pDCTstat->NodePresent) - if (!is_ecc_enabled(pMCTstat, pDCTstat)) - ecc_enabled = 0; - } - - if (ecc_enabled) { - printk(BIOS_DEBUG, "mctAutoInitMCT_D: ECCInit_D\n"); - if (!ECCInit_D(pMCTstat, pDCTstatA)) { /* Setup ECC control and ECC check-bits*/ - /* Memory was not cleared during ECC setup */ - /* mctDoWarmResetMemClr_D(); */ - printk(BIOS_DEBUG, "mctAutoInitMCT_D: MCTMemClr_D\n"); - MCTMemClr_D(pMCTstat,pDCTstatA); - } - } - - if (is_fam15h()) { - printk(BIOS_DEBUG, "mctAutoInitMCT_D: CPUMemTyping_D\n"); - CPUMemTyping_D(pMCTstat, pDCTstatA); /* Map dram into WB/UC CPU cacheability */ - - printk(BIOS_DEBUG, "mctAutoInitMCT_D: UMAMemTyping_D\n"); - UMAMemTyping_D(pMCTstat, pDCTstatA); /* Fix up for UMA sizing */ - - printk(BIOS_DEBUG, "mctAutoInitMCT_D: mct_ForceNBPState0_Dis_Fam15\n"); - for (Node = 0; Node < MAX_NODES_SUPPORTED; Node++) { - struct DCTStatStruc *pDCTstat; - pDCTstat = pDCTstatA + Node; - - mct_ForceNBPState0_Dis_Fam15(pMCTstat, pDCTstat); - } - } - - if (is_fam15h()) { - enable_cc6 = 0; - if (get_option(&nvram, "cpu_cc6_state") == CB_SUCCESS) - enable_cc6 = !!nvram; - - if (enable_cc6) { - uint8_t num_nodes; - - num_nodes = 0; - for (Node = 0; Node < MAX_NODES_SUPPORTED; Node++) { - struct DCTStatStruc *pDCTstat; - pDCTstat = pDCTstatA + Node; - - if (pDCTstat->NodePresent) - num_nodes++; - } - - for (Node = 0; Node < MAX_NODES_SUPPORTED; Node++) { - struct DCTStatStruc *pDCTstat; - pDCTstat = pDCTstatA + Node; - - if (pDCTstat->NodePresent) - set_up_cc6_storage_fam15(pMCTstat, pDCTstat, num_nodes); - } - - for (Node = 0; Node < MAX_NODES_SUPPORTED; Node++) { - struct DCTStatStruc *pDCTstat; - pDCTstat = pDCTstatA + Node; - - if (pDCTstat->NodePresent) { - set_cc6_save_enable(pMCTstat, pDCTstat, 1); - lock_dram_config(pMCTstat, pDCTstat); - } - } - } - } - - mct_FinalMCT_D(pMCTstat, pDCTstatA); - printk(BIOS_DEBUG, "mctAutoInitMCT_D Done: Global Status: %x\n", pMCTstat->GStatus); - } - - return; - -fatalexit: - die("mct_d: fatalexit"); -} - -void initialize_mca(uint8_t bsp, uint8_t suppress_errors) { - uint8_t node; - uint32_t mc4_status_high; - uint32_t mc4_status_low; - - for (node = 0; node < MAX_NODES_SUPPORTED; node++) { - if (bsp && (node > 0)) - break; - - mc4_status_high = pci_read_config32(PCI_DEV(0, 0x18 + node, 3), 0x4c); - mc4_status_low = pci_read_config32(PCI_DEV(0, 0x18 + node, 3), 0x48); - if ((mc4_status_high & (0x1 << 31)) && (mc4_status_high != 0xffffffff)) { - if (!suppress_errors) - printk(BIOS_WARNING, "WARNING: MC4 Machine Check Exception detected on node %d!\n" - "Signature: %08x%08x\n", node, mc4_status_high, mc4_status_low); - - /* Clear MC4 error status */ - pci_write_config32(PCI_DEV(0, 0x18 + node, 3), 0x48, 0x0); - pci_write_config32(PCI_DEV(0, 0x18 + node, 3), 0x4c, 0x0); - } - } -} - -static u8 ReconfigureDIMMspare_D(struct MCTStatStruc *pMCTstat, - struct DCTStatStruc *pDCTstatA) -{ - u8 ret; - - if (mctGet_NVbits(NV_CS_SpareCTL)) { - if (MCT_DIMM_SPARE_NO_WARM) { - /* Do no warm-reset DIMM spare */ - if (pMCTstat->GStatus & (1 << GSB_EnDIMMSpareNW)) { - LoadDQSSigTmgRegs_D(pMCTstat, pDCTstatA); - ret = 0; - } else { - mct_ResetDataStruct_D(pMCTstat, pDCTstatA); - pMCTstat->GStatus |= 1 << GSB_EnDIMMSpareNW; - ret = 1; - } - } else { - /* Do warm-reset DIMM spare */ - if (mctGet_NVbits(NV_DQSTrainCTL)) - mctWarmReset_D(); - ret = 0; - } - } else { - ret = 0; - } - - return ret; -} - -/* Enable or disable phy-assisted training mode - * Phy-assisted training mode applies to the follow DRAM training procedures: - * Write Levelization Training (2.10.5.8.1) - * DQS Receiver Enable Training (2.10.5.8.2) - */ -void fam15EnableTrainingMode(struct MCTStatStruc *pMCTstat, - struct DCTStatStruc *pDCTstat, uint8_t dct, uint8_t enable) -{ - uint8_t index; - uint32_t dword; - uint32_t index_reg = 0x98; - uint32_t dev = pDCTstat->dev_dct; - - if (enable) { - /* Enable training mode */ - dword = Get_NB32_DCT(dev, dct, 0x78); /* DRAM Control */ - dword &= ~(0x1 << 17); /* AddrCmdTriEn = 0 */ - Set_NB32_DCT(dev, dct, 0x78, dword); /* DRAM Control */ - - dword = Get_NB32_DCT(dev, dct, 0x8c); /* DRAM Timing High */ - dword |= (0x1 << 18); /* DisAutoRefresh = 1 */ - Set_NB32_DCT(dev, dct, 0x8c, dword); /* DRAM Timing High */ - - dword = Get_NB32_DCT(dev, dct, 0x94); /* DRAM Configuration High */ - dword &= ~(0xf << 24); /* DcqBypassMax = 0 */ - dword &= ~(0x1 << 22); /* BankSwizzleMode = 0 */ - dword &= ~(0x1 << 15); /* PowerDownEn = 0 */ - dword &= ~(0x3 << 10); /* ZqcsInterval = 0 */ - Set_NB32_DCT(dev, dct, 0x94, dword); /* DRAM Configuration High */ - - dword = Get_NB32_index_wait_DCT(dev, dct, index_reg, 0x0000000d); - dword &= ~(0xf << 16); /* RxMaxDurDllNoLock = 0 */ - dword &= ~(0xf); /* TxMaxDurDllNoLock = 0 */ - Set_NB32_index_wait_DCT(dev, dct, index_reg, 0x0000000d, dword); - - for (index = 0; index < 0x9; index++) { - dword = Get_NB32_index_wait_DCT(dev, dct, index_reg, 0x0d0f0010 | (index << 8)); - dword &= ~(0x1 << 12); /* EnRxPadStandby = 0 */ - Set_NB32_index_wait_DCT(dev, dct, index_reg, 0x0d0f0010 | (index << 8), dword); - } - - dword = Get_NB32_DCT(dev, dct, 0xa4); /* DRAM Controller Temperature Throttle */ - dword &= ~(0x1 << 11); /* BwCapEn = 0 */ - dword &= ~(0x1 << 8); /* ODTSEn = 0 */ - Set_NB32_DCT(dev, dct, 0xa4, dword); /* DRAM Controller Temperature Throttle */ - - dword = Get_NB32_DCT(dev, dct, 0x110); /* DRAM Controller Select Low */ - dword &= ~(0x1 << 2); /* DctSelIntLvEn = 0 */ - Set_NB32_DCT(dev, dct, 0x110, dword); /* DRAM Controller Select Low */ - - dword = Get_NB32_DCT(pDCTstat->dev_nbmisc, dct, 0x58); /* Scrub Rate Control */ - dword &= ~(0x1f << 24); /* L3Scrub = 0 */ - dword &= ~(0x1f); /* DramScrub = 0 */ - Set_NB32_DCT(pDCTstat->dev_nbmisc, dct, 0x58, dword); /* Scrub Rate Control */ - - dword = Get_NB32_DCT(pDCTstat->dev_nbmisc, dct, 0x5c); /* DRAM Scrub Address Low */ - dword &= ~(0x1); /* ScrubReDirEn = 0 */ - Set_NB32_DCT(pDCTstat->dev_nbmisc, dct, 0x5c, dword); /* DRAM Scrub Address Low */ - - dword = Get_NB32_DCT(pDCTstat->dev_nbmisc, dct, 0x1b8); /* L3 Control 1 */ - dword |= (0x1 << 4); /* L3ScrbRedirDis = 1 */ - Set_NB32_DCT(pDCTstat->dev_nbmisc, dct, 0x1b8, dword); /* L3 Control 1 */ - - /* Fam15h BKDG section 2.10.5.5.1 */ - dword = Get_NB32_DCT(dev, dct, 0x218); /* DRAM Timing 5 */ - dword &= ~(0xf << 24); /* TrdrdSdSc = 0xb */ - dword |= (0xb << 24); - dword &= ~(0xf << 16); /* TrdrdSdDc = 0xb */ - dword |= (0xb << 16); - dword &= ~(0xf); /* TrdrdDd = 0xb */ - dword |= 0xb; - Set_NB32_DCT(dev, dct, 0x218, dword); /* DRAM Timing 5 */ - - /* Fam15h BKDG section 2.10.5.5.2 */ - dword = Get_NB32_DCT(dev, dct, 0x214); /* DRAM Timing 4 */ - dword &= ~(0xf << 16); /* TwrwrSdSc = 0xb */ - dword |= (0xb << 16); - dword &= ~(0xf << 8); /* TwrwrSdDc = 0xb */ - dword |= (0xb << 8); - dword &= ~(0xf); /* TwrwrDd = 0xb */ - dword |= 0xb; - Set_NB32_DCT(dev, dct, 0x214, dword); /* DRAM Timing 4 */ - - /* Fam15h BKDG section 2.10.5.5.3 */ - dword = Get_NB32_DCT(dev, dct, 0x218); /* DRAM Timing 5 */ - dword &= ~(0xf << 8); /* Twrrd = 0xb */ - dword |= (0xb << 8); - Set_NB32_DCT(dev, dct, 0x218, dword); /* DRAM Timing 5 */ - - /* Fam15h BKDG section 2.10.5.5.4 */ - dword = Get_NB32_DCT(dev, dct, 0x21c); /* DRAM Timing 6 */ - dword &= ~(0x1f << 8); /* TrwtTO = 0x16 */ - dword |= (0x16 << 8); - dword &= ~(0x1f << 16); /* TrwtWB = TrwtTO + 1 */ - dword |= ((((dword >> 8) & 0x1f) + 1) << 16); - Set_NB32_DCT(dev, dct, 0x21c, dword); /* DRAM Timing 6 */ - } else { - /* Disable training mode */ - uint8_t lane; - uint8_t dimm; - int16_t max_cdd_we_delta; - int16_t cdd_trwtto_we_delta; - uint8_t receiver; - uint8_t lane_count; - uint8_t x4_present = 0; - uint8_t x8_present = 0; - uint8_t memclk_index; - uint8_t interleave_channels = 0; - uint16_t trdrdsddc; - uint16_t trdrddd; - uint16_t cdd_trdrddd; - uint16_t twrwrsddc; - uint16_t twrwrdd; - uint16_t cdd_twrwrdd; - uint16_t twrrd; - uint16_t cdd_twrrd; - uint16_t cdd_trwtto; - uint16_t trwtto; - uint8_t first_dimm; - uint16_t delay; - uint16_t delay2; - uint8_t min_value; - uint8_t write_early; - uint8_t read_odt_delay; - uint8_t write_odt_delay; - uint8_t buffer_data_delay; - int16_t latency_difference; - uint16_t difference; - uint16_t current_total_delay_1[MAX_BYTE_LANES]; - uint16_t current_total_delay_2[MAX_BYTE_LANES]; - uint8_t ddr_voltage_index; - uint8_t max_dimms_installable; - - /* FIXME - * This should be platform configurable - */ - uint8_t dimm_event_l_pin_support = 0; - - ddr_voltage_index = dct_ddr_voltage_index(pDCTstat, dct); - max_dimms_installable = mctGet_NVbits(NV_MAX_DIMMS_PER_CH); - - lane_count = get_available_lane_count(pMCTstat, pDCTstat); - - if (pDCTstat->Dimmx4Present & ((dct)?0xaa:0x55)) - x4_present = 1; - if (pDCTstat->Dimmx8Present & ((dct)?0xaa:0x55)) - x8_present = 1; - memclk_index = Get_NB32_DCT(dev, dct, 0x94) & 0x1f; - - if (pDCTstat->DIMMValidDCT[0] && pDCTstat->DIMMValidDCT[1] && mctGet_NVbits(NV_Unganged)) - interleave_channels = 1; - - dword = Get_NB32_DCT(dev, dct, 0x240); - delay = (dword >> 4) & 0xf; - if (delay > 6) - read_odt_delay = delay - 6; - else - read_odt_delay = 0; - delay = (dword >> 12) & 0x7; - if (delay > 6) - write_odt_delay = delay - 6; - else - write_odt_delay = 0; - - dword = (Get_NB32_DCT(dev, dct, 0xa8) >> 24) & 0x3; - write_early = dword / 2; - - latency_difference = Get_NB32_DCT(dev, dct, 0x200) & 0x1f; - dword = Get_NB32_DCT(dev, dct, 0x20c) & 0x1f; - latency_difference -= dword; - - if (pDCTstat->Status & (1 << SB_LoadReduced)) { - /* LRDIMM */ - - /* TODO - * Implement LRDIMM support - * See Fam15h BKDG Rev. 3.14 section 2.10.5.5 - */ - } else { - buffer_data_delay = 0; - } - - /* TODO: - * Adjust trdrdsddc if four-rank DIMMs are installed per - * section 2.10.5.5.1 of the Family 15h BKDG. - * cdd_trdrdsddc will also need to be calculated in that process. - */ - trdrdsddc = 3; - - /* Calculate the Critical Delay Difference for TrdrdDd */ - cdd_trdrddd = 0; - first_dimm = 1; - for (receiver = 0; receiver < 8; receiver += 2) { - dimm = (receiver >> 1); - - if (!mct_RcvrRankEnabled_D(pMCTstat, pDCTstat, dct, receiver)) - continue; - - read_dqs_receiver_enable_control_registers(current_total_delay_2, dev, dct, dimm, index_reg); - - if (first_dimm) { - memcpy(current_total_delay_1, current_total_delay_2, sizeof(current_total_delay_1)); - first_dimm = 0; - } - - for (lane = 0; lane < lane_count; lane++) { - if (current_total_delay_1[lane] > current_total_delay_2[lane]) - difference = current_total_delay_1[lane] - current_total_delay_2[lane]; - else - difference = current_total_delay_2[lane] - current_total_delay_1[lane]; - - if (difference > cdd_trdrddd) - cdd_trdrddd = difference; - } - } - - /* Convert the difference to MEMCLKs */ - cdd_trdrddd = (((cdd_trdrddd + (1 << 6) - 1) >> 6) & 0xf); - - /* Calculate Trdrddd */ - delay = (read_odt_delay + 3) * 2; - delay2 = cdd_trdrddd + 7; - if (delay2 > delay) - delay = delay2; - trdrddd = (delay + 1) / 2; /* + 1 is equivalent to ceiling function here */ - if (trdrdsddc > trdrddd) - trdrddd = trdrdsddc; - - /* TODO: - * Adjust twrwrsddc if four-rank DIMMs are installed per - * section 2.10.5.5.1 of the Family 15h BKDG. - * cdd_twrwrsddc will also need to be calculated in that process. - */ - twrwrsddc = 4; - - /* Calculate the Critical Delay Difference for TwrwrDd */ - cdd_twrwrdd = 0; - first_dimm = 1; - for (receiver = 0; receiver < 8; receiver += 2) { - dimm = (receiver >> 1); - - if (!mct_RcvrRankEnabled_D(pMCTstat, pDCTstat, dct, receiver)) - continue; - - read_dqs_write_timing_control_registers(current_total_delay_2, dev, dct, dimm, index_reg); - - if (first_dimm) { - memcpy(current_total_delay_1, current_total_delay_2, sizeof(current_total_delay_1)); - first_dimm = 0; - } - - for (lane = 0; lane < lane_count; lane++) { - if (current_total_delay_1[lane] > current_total_delay_2[lane]) - difference = current_total_delay_1[lane] - current_total_delay_2[lane]; - else - difference = current_total_delay_2[lane] - current_total_delay_1[lane]; - - if (difference > cdd_twrwrdd) - cdd_twrwrdd = difference; - } - } - - /* Convert the difference to MEMCLKs */ - cdd_twrwrdd = (((cdd_twrwrdd + (1 << 6) - 1) >> 6) & 0xf); - - /* Calculate Twrwrdd */ - delay = (write_odt_delay + 3) * 2; - delay2 = cdd_twrwrdd + 7; - if (delay2 > delay) - delay = delay2; - twrwrdd = (delay + 1) / 2; /* + 1 is equivalent to ceiling function here */ - if (twrwrsddc > twrwrdd) - twrwrdd = twrwrsddc; - - dword = Get_NB32_DCT(dev, dct, 0x78); /* DRAM Control */ - dword |= (0x1 << 17); /* AddrCmdTriEn = 1 */ - Set_NB32_DCT(dev, dct, 0x78, dword); /* DRAM Control */ - - dword = Get_NB32_DCT(dev, dct, 0x8c); /* DRAM Timing High */ - dword &= ~(0x1 << 18); /* DisAutoRefresh = 0 */ - Set_NB32_DCT(dev, dct, 0x8c, dword); /* DRAM Timing High */ - - /* Configure power saving options */ - dword = Get_NB32_DCT(dev, dct, 0xa8); /* Dram Miscellaneous 2 */ - dword |= (0x1 << 22); /* PrtlChPDEnhEn = 0x1 */ - dword |= (0x1 << 21); /* AggrPDEn = 0x1 */ - Set_NB32_DCT(dev, dct, 0xa8, dword); /* Dram Miscellaneous 2 */ - - /* Configure partial power down delay */ - dword = Get_NB32(dev, 0x244); /* DRAM Controller Miscellaneous 3 */ - dword &= ~0xf; /* PrtlChPDDynDly = 0x2 */ - dword |= 0x2; - Set_NB32(dev, 0x244, dword); /* DRAM Controller Miscellaneous 3 */ - - /* Configure power save delays */ - delay = 0xa; - delay2 = 0x3; - - /* Family 15h BKDG Table 214 */ - if ((pDCTstat->Status & (1 << SB_Registered)) - || (pDCTstat->Status & (1 << SB_LoadReduced))) { - if (memclk_index <= 0x6) { - if (ddr_voltage_index < 0x4) - /* 1.5 or 1.35V */ - delay2 = 0x3; - else - /* 1.25V */ - delay2 = 0x4; - } - else if ((memclk_index == 0xa) - || (memclk_index == 0xe)) - delay2 = 0x4; - else if (memclk_index == 0x12) - delay2 = 0x5; - else if (memclk_index == 0x16) - delay2 = 0x6; - } else { - if (memclk_index <= 0x6) - delay2 = 0x3; - else if ((memclk_index == 0xa) - || (memclk_index == 0xe)) - delay2 = 0x4; - else if (memclk_index == 0x12) - delay2 = 0x5; - else if (memclk_index == 0x16) - delay2 = 0x6; - } - - /* Family 15h BKDG Table 215 */ - if (memclk_index <= 0x6) - delay = 0xa; - else if (memclk_index == 0xa) - delay = 0xd; - else if (memclk_index == 0xe) - delay = 0x10; - else if (memclk_index == 0x12) - delay = 0x14; - else if (memclk_index == 0x16) - delay = 0x17; - - dword = Get_NB32_DCT(dev, dct, 0x248); /* Dram Power Management 0 */ - dword &= ~(0x3f << 24); /* AggrPDDelay = 0x0 */ - dword &= ~(0x3f << 16); /* PchgPDEnDelay = 0x1 */ - dword |= (0x1 << 16); - dword &= ~(0x1f << 8); /* Txpdll = delay */ - dword |= ((delay & 0x1f) << 8); - dword &= ~0xf; /* Txp = delay2 */ - dword |= delay2 & 0xf; - Set_NB32_DCT(dev, dct, 0x248, dword); /* Dram Power Management 0 */ - - /* Family 15h BKDG Table 216 */ - if (memclk_index <= 0x6) { - delay = 0x5; - delay2 = 0x3; - } else if (memclk_index == 0xa) { - delay = 0x6; - delay2 = 0x3; - } else if (memclk_index == 0xe) { - delay = 0x7; - delay2 = 0x4; - } else if (memclk_index == 0x12) { - delay = 0x8; - delay2 = 0x4; - } else if (memclk_index == 0x16) { - delay = 0xa; - delay2 = 0x5; - } - - dword = Get_NB32_DCT(dev, dct, 0x24c); /* Dram Power Management 1 */ - dword &= ~(0x3f << 24); /* Tcksrx = delay */ - dword |= ((delay & 0x3f) << 24); - dword &= ~(0x3f << 16); /* Tcksre = delay */ - dword |= ((delay & 0x3f) << 16); - dword &= ~(0x3f << 8); /* Tckesr = delay2 + 1 */ - dword |= (((delay2 + 1) & 0x3f) << 8); - dword &= ~0xf; /* Tpd = delay2 */ - dword |= delay2 & 0xf; - Set_NB32_DCT(dev, dct, 0x24c, dword); /* Dram Power Management 1 */ - - dword = Get_NB32_DCT(dev, dct, 0x94); /* DRAM Configuration High */ - dword |= (0xf << 24); /* DcqBypassMax = 0xf */ - dword |= (0x1 << 22); /* BankSwizzleMode = 1 */ - dword |= (0x1 << 15); /* PowerDownEn = 1 */ - dword &= ~(0x3 << 10); /* ZqcsInterval = 0x2 */ - dword |= (0x2 << 10); - Set_NB32_DCT(dev, dct, 0x94, dword); /* DRAM Configuration High */ - - if (x4_present && x8_present) { - /* Mixed channel of 4x and 8x DIMMs */ - dword = Get_NB32_index_wait_DCT(dev, dct, index_reg, 0x0000000d); - dword &= ~(0x3 << 24); /* RxDLLWakeupTime = 0 */ - dword &= ~(0x7 << 20); /* RxCPUpdPeriod = 0 */ - dword &= ~(0xf << 16); /* RxMaxDurDllNoLock = 0 */ - dword &= ~(0x3 << 8); /* TxDLLWakeupTime = 0 */ - dword &= ~(0x7 << 4); /* TxCPUpdPeriod = 0 */ - dword &= ~(0xf); /* TxMaxDurDllNoLock = 0 */ - Set_NB32_index_wait_DCT(dev, dct, index_reg, 0x0000000d, dword); - } else { - dword = Get_NB32_index_wait_DCT(dev, dct, index_reg, 0x0000000d); - dword &= ~(0x3 << 24); /* RxDLLWakeupTime = 3 */ - dword |= (0x3 << 24); - dword &= ~(0x7 << 20); /* RxCPUpdPeriod = 3 */ - dword |= (0x3 << 20); - dword &= ~(0xf << 16); /* RxMaxDurDllNoLock = 7 */ - dword |= (0x7 << 16); - dword &= ~(0x3 << 8); /* TxDLLWakeupTime = 3 */ - dword |= (0x3 << 8); - dword &= ~(0x7 << 4); /* TxCPUpdPeriod = 3 */ - dword |= (0x3 << 4); - dword &= ~(0xf); /* TxMaxDurDllNoLock = 7 */ - dword |= 0x7; - Set_NB32_index_wait_DCT(dev, dct, index_reg, 0x0000000d, dword); - } - - if ((memclk_index <= 0x12) && (x4_present != x8_present)) { - /* MemClkFreq <= 800MHz - * Not a mixed channel of x4 and x8 DIMMs - */ - for (index = 0; index < 0x9; index++) { - dword = Get_NB32_index_wait_DCT(dev, dct, index_reg, 0x0d0f0010 | (index << 8)); - dword |= (0x1 << 12); /* EnRxPadStandby = 1 */ - Set_NB32_index_wait_DCT(dev, dct, index_reg, 0x0d0f0010 | (index << 8), dword); - } - } else { - for (index = 0; index < 0x9; index++) { - dword = Get_NB32_index_wait_DCT(dev, dct, index_reg, 0x0d0f0010 | (index << 8)); - dword &= ~(0x1 << 12); /* EnRxPadStandby = 0 */ - Set_NB32_index_wait_DCT(dev, dct, index_reg, 0x0d0f0010 | (index << 8), dword); - } - } - - /* Calculate the Critical Delay Difference for Twrrd */ - cdd_twrrd = 0; - for (receiver = 0; receiver < 8; receiver += 2) { - dimm = (receiver >> 1); - - if (!mct_RcvrRankEnabled_D(pMCTstat, pDCTstat, dct, receiver)) - continue; - - read_dqs_write_timing_control_registers(current_total_delay_1, dev, dct, dimm, index_reg); - read_dqs_receiver_enable_control_registers(current_total_delay_2, dev, dct, dimm, index_reg); - - for (lane = 0; lane < lane_count; lane++) { - if (current_total_delay_1[lane] > current_total_delay_2[lane]) - difference = current_total_delay_1[lane] - current_total_delay_2[lane]; - else - difference = current_total_delay_2[lane] - current_total_delay_1[lane]; - - if (difference > cdd_twrrd) - cdd_twrrd = difference; - } - } - - /* Convert the difference to MEMCLKs */ - cdd_twrrd = (((cdd_twrrd + (1 << 6) - 1) >> 6) & 0xf); - - /* Fam15h BKDG section 2.10.5.5.3 */ - if (pDCTstat->Status & (1 << SB_LoadReduced)) { - /* LRDIMM */ - - /* TODO - * Implement LRDIMM support - * See Fam15h BKDG Rev. 3.14 section 2.10.5.5 - */ - twrrd = 0xb; - } else { - max_cdd_we_delta = (((int16_t)cdd_twrrd + 1 - ((int16_t)write_early * 2)) + 1) / 2; - if (max_cdd_we_delta < 0) - max_cdd_we_delta = 0; - if (((uint16_t)max_cdd_we_delta) > write_odt_delay) - dword = max_cdd_we_delta; - else - dword = write_odt_delay; - dword += 3; - if (latency_difference < dword) { - dword -= latency_difference; - if (dword < 1) - twrrd = 1; - else - twrrd = dword; - } else { - twrrd = 1; - } - } - - /* Calculate the Critical Delay Difference for TrwtTO */ - cdd_trwtto = 0; - for (receiver = 0; receiver < 8; receiver += 2) { - dimm = (receiver >> 1); - - if (!mct_RcvrRankEnabled_D(pMCTstat, pDCTstat, dct, receiver)) - continue; - - read_dqs_receiver_enable_control_registers(current_total_delay_1, dev, dct, dimm, index_reg); - read_dqs_write_timing_control_registers(current_total_delay_2, dev, dct, dimm, index_reg); - - for (lane = 0; lane < lane_count; lane++) { - if (current_total_delay_1[lane] > current_total_delay_2[lane]) - difference = current_total_delay_1[lane] - current_total_delay_2[lane]; - else - difference = current_total_delay_2[lane] - current_total_delay_1[lane]; - - if (difference > cdd_trwtto) - cdd_trwtto = difference; - } - } - - /* Convert the difference to MEMCLKs */ - cdd_trwtto = (((cdd_trwtto + (1 << 6) - 1) >> 6) & 0xf); - - /* Fam15h BKDG section 2.10.5.5.4 */ - if (max_dimms_installable == 1) - min_value = 0; - else - min_value = read_odt_delay + buffer_data_delay; - cdd_trwtto_we_delta = (((int16_t)cdd_trwtto - 1 + ((int16_t)write_early * 2)) + 1) / 2; - cdd_trwtto_we_delta += latency_difference + 3; - if (cdd_trwtto_we_delta < 0) - cdd_trwtto_we_delta = 0; - if ((cdd_trwtto_we_delta) > min_value) - trwtto = cdd_trwtto_we_delta; - else - trwtto = min_value; - - dword = Get_NB32_DCT(dev, dct, 0xa4); /* DRAM Controller Temperature Throttle */ - dword &= ~(0x1 << 11); /* BwCapEn = 0 */ - dword &= ~(0x1 << 8); /* ODTSEn = dimm_event_l_pin_support */ - dword |= (dimm_event_l_pin_support & 0x1) << 8; - Set_NB32_DCT(dev, dct, 0xa4, dword); /* DRAM Controller Temperature Throttle */ - - dword = Get_NB32_DCT(dev, dct, 0x110); /* DRAM Controller Select Low */ - dword &= ~(0x1 << 2); /* DctSelIntLvEn = interleave_channels */ - dword |= (interleave_channels & 0x1) << 2; - dword |= (0x3 << 6); /* DctSelIntLvAddr = 0x3 */ - Set_NB32_DCT(dev, dct, 0x110, dword); /* DRAM Controller Select Low */ - - /* NOTE - * ECC-related setup is performed as part of ECCInit_D and must not be located here, - * otherwise semi-random lockups will occur due to misconfigured scrubbing hardware! - */ - - /* Fam15h BKDG section 2.10.5.5.2 */ - dword = Get_NB32_DCT(dev, dct, 0x214); /* DRAM Timing 4 */ - dword &= ~(0xf << 16); /* TwrwrSdSc = 0x1 */ - dword |= (0x1 << 16); - dword &= ~(0xf << 8); /* TwrwrSdDc = twrwrsddc */ - dword |= ((twrwrsddc & 0xf) << 8); - dword &= ~(0xf); /* TwrwrDd = twrwrdd */ - dword |= (twrwrdd & 0xf); - Set_NB32_DCT(dev, dct, 0x214, dword); /* DRAM Timing 4 */ - - /* Fam15h BKDG section 2.10.5.5.3 */ - dword = Get_NB32_DCT(dev, dct, 0x218); /* DRAM Timing 5 */ - dword &= ~(0xf << 24); /* TrdrdSdSc = 0x1 */ - dword |= (0x1 << 24); - dword &= ~(0xf << 16); /* TrdrdSdDc = trdrdsddc */ - dword |= ((trdrdsddc & 0xf) << 16); - dword &= ~(0xf << 8); /* Twrrd = twrrd */ - dword |= ((twrrd & 0xf) << 8); - dword &= ~(0xf); /* TrdrdDd = trdrddd */ - dword |= (trdrddd & 0xf); - Set_NB32_DCT(dev, dct, 0x218, dword); /* DRAM Timing 5 */ - - /* Fam15h BKDG section 2.10.5.5.4 */ - dword = Get_NB32_DCT(dev, dct, 0x21c); /* DRAM Timing 6 */ - dword &= ~(0x1f << 8); /* TrwtTO = trwtto */ - dword |= ((trwtto & 0x1f) << 8); - dword &= ~(0x1f << 16); /* TrwtWB = TrwtTO + 1 */ - dword |= ((((dword >> 8) & 0x1f) + 1) << 16); - Set_NB32_DCT(dev, dct, 0x21c, dword); /* DRAM Timing 6 */ - - /* Enable prefetchers */ - dword = Get_NB32(dev, 0x11c); /* Memory Controller Configuration High */ - dword &= ~(0x1 << 13); /* PrefIoDis = 0 */ - dword &= ~(0x1 << 12); /* PrefCpuDis = 0 */ - Set_NB32(dev, 0x11c, dword); /* Memory Controller Configuration High */ - } -} - -static void exit_training_mode_fam15(struct MCTStatStruc *pMCTstat, - struct DCTStatStruc *pDCTstatA) -{ - uint8_t node; - uint8_t dct; - - for (node = 0; node < MAX_NODES_SUPPORTED; node++) { - struct DCTStatStruc *pDCTstat; - pDCTstat = pDCTstatA + node; - - if (pDCTstat->NodePresent) - for (dct = 0; dct < 2; dct++) - fam15EnableTrainingMode(pMCTstat, pDCTstat, dct, 0); - } -} - -static void DQSTiming_D(struct MCTStatStruc *pMCTstat, - struct DCTStatStruc *pDCTstatA, uint8_t allow_config_restore) -{ - uint8_t Node; - u8 nv_DQSTrainCTL; - uint8_t retry_requested; - - if (pMCTstat->GStatus & (1 << GSB_EnDIMMSpareNW)) { - return; - } - - /* Set initial TCWL offset to zero */ - for (Node = 0; Node < MAX_NODES_SUPPORTED; Node++) { - uint8_t dct; - struct DCTStatStruc *pDCTstat; - pDCTstat = pDCTstatA + Node; - for (dct = 0; dct < 2; dct++) - pDCTstat->tcwl_delay[dct] = 0; - } - -retry_dqs_training_and_levelization: - nv_DQSTrainCTL = !allow_config_restore; - - mct_BeforeDQSTrain_D(pMCTstat, pDCTstatA); - phyAssistedMemFnceTraining(pMCTstat, pDCTstatA, -1); - - if (is_fam15h()) { - struct DCTStatStruc *pDCTstat; - for (Node = 0; Node < MAX_NODES_SUPPORTED; Node++) { - pDCTstat = pDCTstatA + Node; - if (pDCTstat->NodePresent) { - if (pDCTstat->DIMMValidDCT[0]) - InitPhyCompensation(pMCTstat, pDCTstat, 0); - if (pDCTstat->DIMMValidDCT[1]) - InitPhyCompensation(pMCTstat, pDCTstat, 1); - } - } - } - - mctHookBeforeAnyTraining(pMCTstat, pDCTstatA); - if (!is_fam15h()) { - /* TODO: should be in mctHookBeforeAnyTraining */ - _WRMSR(MTRR_FIX_4K_E0000, 0x04040404, 0x04040404); - _WRMSR(MTRR_FIX_4K_E8000, 0x04040404, 0x04040404); - _WRMSR(MTRR_FIX_4K_F0000, 0x04040404, 0x04040404); - _WRMSR(MTRR_FIX_4K_F8000, 0x04040404, 0x04040404); - } - - if (nv_DQSTrainCTL) { - mct_WriteLevelization_HW(pMCTstat, pDCTstatA, FirstPass); - - if (is_fam15h()) { - /* Receiver Enable Training Pass 1 */ - TrainReceiverEn_D(pMCTstat, pDCTstatA, FirstPass); - } - - mct_WriteLevelization_HW(pMCTstat, pDCTstatA, SecondPass); - - if (is_fam15h()) { - - /* TODO: - * Determine why running TrainReceiverEn_D in SecondPass - * mode yields less stable training values than when run - * in FirstPass mode as in the HACK below. - */ - TrainReceiverEn_D(pMCTstat, pDCTstatA, FirstPass); - } else { - TrainReceiverEn_D(pMCTstat, pDCTstatA, FirstPass); - } - - mct_TrainDQSPos_D(pMCTstat, pDCTstatA); - - /* Determine if DQS training requested a retrain attempt */ - retry_requested = 0; - for (Node = 0; Node < MAX_NODES_SUPPORTED; Node++) { - struct DCTStatStruc *pDCTstat; - pDCTstat = pDCTstatA + Node; - - if (pDCTstat->NodePresent) { - if (pDCTstat->TrainErrors & (1 << SB_FatalError)) { - printk(BIOS_ERR, "DIMM training FAILED! Restarting system..."); - soft_reset(); - } - if (pDCTstat->TrainErrors & (1 << SB_RetryConfigTrain)) { - retry_requested = 1; - - /* Clear previous errors */ - pDCTstat->TrainErrors &= ~(1 << SB_RetryConfigTrain); - pDCTstat->TrainErrors &= ~(1 << SB_NODQSPOS); - pDCTstat->ErrStatus &= ~(1 << SB_RetryConfigTrain); - pDCTstat->ErrStatus &= ~(1 << SB_NODQSPOS); - } - } - } - - /* Retry training and levelization if requested */ - if (retry_requested) { - printk(BIOS_DEBUG, "%s: Restarting training on algorithm request\n", __func__); - /* Reset frequency to minimum */ - for (Node = 0; Node < MAX_NODES_SUPPORTED; Node++) { - struct DCTStatStruc *pDCTstat; - pDCTstat = pDCTstatA + Node; - if (pDCTstat->NodePresent) { - uint8_t original_target_freq = pDCTstat->TargetFreq; - uint8_t original_auto_speed = pDCTstat->DIMMAutoSpeed; - pDCTstat->TargetFreq = mhz_to_memclk_config(mctGet_NVbits(NV_MIN_MEMCLK)); - pDCTstat->Speed = pDCTstat->DIMMAutoSpeed = pDCTstat->TargetFreq; - SetTargetFreq(pMCTstat, pDCTstatA, Node); - pDCTstat->TargetFreq = original_target_freq; - pDCTstat->DIMMAutoSpeed = original_auto_speed; - } - } - /* Apply any DIMM timing changes */ - for (Node = 0; Node < MAX_NODES_SUPPORTED; Node++) { - struct DCTStatStruc *pDCTstat; - pDCTstat = pDCTstatA + Node; - if (pDCTstat->NodePresent) { - AutoCycTiming_D(pMCTstat, pDCTstat, 0); - if (!pDCTstat->GangedMode) - if (pDCTstat->DIMMValidDCT[1] > 0) - AutoCycTiming_D(pMCTstat, pDCTstat, 1); - } - } - goto retry_dqs_training_and_levelization; - } - - TrainMaxRdLatency_En_D(pMCTstat, pDCTstatA); - - if (is_fam15h()) - exit_training_mode_fam15(pMCTstat, pDCTstatA); - else - mctSetEccDQSRcvrEn_D(pMCTstat, pDCTstatA); - } else { - mct_WriteLevelization_HW(pMCTstat, pDCTstatA, FirstPass); - - mct_WriteLevelization_HW(pMCTstat, pDCTstatA, SecondPass); - -#if CONFIG(HAVE_ACPI_RESUME) - printk(BIOS_DEBUG, "mctAutoInitMCT_D: Restoring DIMM training configuration from NVRAM\n"); - if (restore_mct_information_from_nvram(1) != 0) - printk(BIOS_CRIT, "%s: ERROR: Unable to restore DCT configuration from NVRAM\n", __func__); -#endif - - if (is_fam15h()) - exit_training_mode_fam15(pMCTstat, pDCTstatA); - - pMCTstat->GStatus |= 1 << GSB_ConfigRestored; - } - - if (is_fam15h()) { - struct DCTStatStruc *pDCTstat; - - /* Switch DCT control register to DCT 0 per Erratum 505 */ - for (Node = 0; Node < MAX_NODES_SUPPORTED; Node++) { - pDCTstat = pDCTstatA + Node; - if (pDCTstat->NodePresent) { - fam15h_switch_dct(pDCTstat->dev_map, 0); - } - } - } - - /* FIXME - currently uses calculated value TrainMaxReadLatency_D(pMCTstat, pDCTstatA); */ - mctHookAfterAnyTraining(); -} - -static void LoadDQSSigTmgRegs_D(struct MCTStatStruc *pMCTstat, - struct DCTStatStruc *pDCTstatA) -{ - u8 Node, Receiver, Channel, Dir, DIMM; - u32 dev; - u32 index_reg; - u32 reg; - u32 index; - u32 val; - u8 ByteLane; - u8 txdqs; - - for (Node = 0; Node < MAX_NODES_SUPPORTED; Node++) { - struct DCTStatStruc *pDCTstat; - pDCTstat = pDCTstatA + Node; - - if (pDCTstat->DCTSysLimit) { - dev = pDCTstat->dev_dct; - for (Channel = 0;Channel < 2; Channel++) { - /* there are four receiver pairs, - loosely associated with chipselects.*/ - index_reg = 0x98; - for (Receiver = 0; Receiver < 8; Receiver += 2) { - /* Set Receiver Enable Values */ - mct_SetRcvrEnDly_D(pDCTstat, - 0, /* RcvrEnDly */ - 1, /* FinalValue, From stack */ - Channel, - Receiver, - dev, index_reg, - (Receiver >> 1) * 3 + 0x10, /* Addl_Index */ - 2); /* Pass Second Pass ? */ - /* Restore Write levelization training data */ - for (ByteLane = 0; ByteLane < 9; ByteLane ++) { - txdqs = pDCTstat->persistentData.CH_D_B_TxDqs[Channel][Receiver >> 1][ByteLane]; - index = Table_DQSRcvEn_Offset[ByteLane >> 1]; - index += (Receiver >> 1) * 3 + 0x10 + 0x20; /* Addl_Index */ - val = Get_NB32_index_wait_DCT(dev, Channel, 0x98, index); - if (ByteLane & 1) { /* odd byte lane */ - val &= ~(0xFF << 16); - val |= txdqs << 16; - } else { - val &= ~0xFF; - val |= txdqs; - } - Set_NB32_index_wait_DCT(dev, Channel, 0x98, index, val); - } - } - } - for (Channel = 0; Channel < 2; Channel++) { - SetEccDQSRcvrEn_D(pDCTstat, Channel); - } - - for (Channel = 0; Channel < 2; Channel++) { - u8 *p; - index_reg = 0x98; - - /* NOTE: - * when 400, 533, 667, it will support dimm0/1/2/3, - * and set conf for dimm0, hw will copy to dimm1/2/3 - * set for dimm1, hw will copy to dimm3 - * Rev A/B only support DIMM0/1 when 800MHz and above - * + 0x100 to next dimm - * Rev C support DIMM0/1/2/3 when 800MHz and above - * + 0x100 to next dimm - */ - for (DIMM = 0; DIMM < 4; DIMM++) { - if (DIMM == 0) { - index = 0; /* CHA Write Data Timing Low */ - } else { - if (pDCTstat->Speed >= mhz_to_memclk_config(mctGet_NVbits(NV_MIN_MEMCLK))) { - index = 0x100 * DIMM; - } else { - break; - } - } - for (Dir = 0; Dir < 2; Dir++) {/* RD/WR */ - p = pDCTstat->CH_D_DIR_B_DQS[Channel][DIMM][Dir]; - val = stream_to_int(p); /* CHA Read Data Timing High */ - Set_NB32_index_wait_DCT(dev, Channel, index_reg, index+1, val); - val = stream_to_int(p+4); /* CHA Write Data Timing High */ - Set_NB32_index_wait_DCT(dev, Channel, index_reg, index+2, val); - val = *(p+8); /* CHA Write ECC Timing */ - Set_NB32_index_wait_DCT(dev, Channel, index_reg, index+3, val); - index += 4; - } - } - } - - for (Channel = 0; Channel < 2; Channel++) { - reg = 0x78; - val = Get_NB32_DCT(dev, Channel, reg); - val &= ~(0x3ff<<22); - val |= ((u32) pDCTstat->CH_MaxRdLat[Channel][0] << 22); - val &= ~(1<HoleBase == 0) { - DramHoleBase = mctGet_NVbits(NV_BottomIO); - } else { - DramHoleBase = pMCTstat->HoleBase >> (24-8); - } - - BottomIO = DramHoleBase << (24-8); - - NextBase = 0; - pDCTstat = pDCTstatA + 0; - dev = pDCTstat->dev_map; - - for (Node = 0; Node < MAX_NODES_SUPPORTED; Node++) { - pDCTstat = pDCTstatA + Node; - devx = pDCTstat->dev_map; - DramSelBaseAddr = 0; - if (!pDCTstat->GangedMode) { - DramSelBaseAddr = pDCTstat->NodeSysLimit - pDCTstat->DCTSysLimit; - /*In unganged mode, we must add DCT0 and DCT1 to DCTSysLimit */ - val = pDCTstat->NodeSysLimit; - if ((val & 0xFF) == 0xFE) { - DramSelBaseAddr++; - val++; - } - pDCTstat->DCTSysLimit = val; - } - - base = pDCTstat->DCTSysBase; - limit = pDCTstat->DCTSysLimit; - if (limit > base) { - base += NextBase; - limit += NextBase; - DramSelBaseAddr += NextBase; - printk(BIOS_DEBUG, " Node: %02x base: %02x limit: %02x BottomIO: %02x\n", Node, base, limit, BottomIO); - - if (_MemHoleRemap) { - if ((base < BottomIO) && (limit >= BottomIO)) { - /* HW Dram Remap */ - pDCTstat->Status |= 1 << SB_HWHole; - pMCTstat->GStatus |= 1 << GSB_HWHole; - pDCTstat->DCTSysBase = base; - pDCTstat->DCTSysLimit = limit; - pDCTstat->DCTHoleBase = BottomIO; - pMCTstat->HoleBase = BottomIO; - HoleSize = _4GB_RJ8 - BottomIO; /* HoleSize[39:8] */ - if ((DramSelBaseAddr > 0) && (DramSelBaseAddr < BottomIO)) - base = DramSelBaseAddr; - val = ((base + HoleSize) >> (24-8)) & 0xFF; - val <<= 8; /* shl 16, rol 24 */ - val |= DramHoleBase << 24; - val |= 1 << DramHoleValid; - Set_NB32(devx, 0xF0, val); /* Dram Hole Address Reg */ - pDCTstat->DCTSysLimit += HoleSize; - base = pDCTstat->DCTSysBase; - limit = pDCTstat->DCTSysLimit; - } else if (base == BottomIO) { - /* SW Node Hoist */ - pMCTstat->GStatus |= 1<Status |= 1<GStatus |= 1<HoleBase = base; - limit -= base; - base = _4GB_RJ8; - limit += base; - pDCTstat->DCTSysBase = base; - pDCTstat->DCTSysLimit = limit; - } else { - /* No Remapping. Normal Contiguous mapping */ - pDCTstat->DCTSysBase = base; - pDCTstat->DCTSysLimit = limit; - } - } else { - /*No Remapping. Normal Contiguous mapping*/ - pDCTstat->DCTSysBase = base; - pDCTstat->DCTSysLimit = limit; - } - base |= 3; /* set WE,RE fields*/ - pMCTstat->SysLimit = limit; - } - Set_NB32(dev, 0x40 + (Node << 3), base); /* [Node] + Dram Base 0 */ - - val = limit & 0xFFFF0000; - val |= Node; - Set_NB32(dev, 0x44 + (Node << 3), val); /* set DstNode */ - - printk(BIOS_DEBUG, " Node: %02x base: %02x limit: %02x\n", Node, base, limit); - limit = pDCTstat->DCTSysLimit; - if (limit) { - NextBase = (limit & 0xFFFF0000) + 0x10000; - } - } - - /* Copy dram map from Node 0 to Node 1-7 */ - for (Node = 1; Node < MAX_NODES_SUPPORTED; Node++) { - u32 reg; - pDCTstat = pDCTstatA + Node; - devx = pDCTstat->dev_map; - - if (pDCTstat->NodePresent) { - printk(BIOS_DEBUG, " Copy dram map from Node 0 to Node %02x\n", Node); - reg = 0x40; /*Dram Base 0*/ - do { - val = Get_NB32(dev, reg); - Set_NB32(devx, reg, val); - reg += 4; - } while (reg < 0x80); - } else { - break; /* stop at first absent Node */ - } - } - - /*Copy dram map to F1x120/124*/ - mct_HTMemMapExt(pMCTstat, pDCTstatA); -} - -void MCTMemClr_D(struct MCTStatStruc *pMCTstat, - struct DCTStatStruc *pDCTstatA) -{ - - /* Initiates a memory clear operation for all node. The mem clr - * is done in parallel. After the memclr is complete, all processors - * status are checked to ensure that memclr has completed. - */ - u8 Node; - uint32_t dword; - struct DCTStatStruc *pDCTstat; - - if (!mctGet_NVbits(NV_DQSTrainCTL)) { - /* FIXME: callback to wrapper: mctDoWarmResetMemClr_D */ - } else { /* NV_DQSTrainCTL == 1 */ - for (Node = 0; Node < MAX_NODES_SUPPORTED; Node++) { - pDCTstat = pDCTstatA + Node; - - if (pDCTstat->NodePresent) { - DCTMemClr_Init_D(pMCTstat, pDCTstat); - } - } - for (Node = 0; Node < MAX_NODES_SUPPORTED; Node++) { - pDCTstat = pDCTstatA + Node; - - if (pDCTstat->NodePresent) { - DCTMemClr_Sync_D(pMCTstat, pDCTstat); - } - } - } - - for (Node = 0; Node < MAX_NODES_SUPPORTED; Node++) { - pDCTstat = pDCTstatA + Node; - - /* Enable prefetchers */ - dword = Get_NB32(pDCTstat->dev_dct, 0x11c); /* Memory Controller Configuration High */ - dword &= ~(0x1 << 13); /* PrefIoDis = 0 */ - dword &= ~(0x1 << 12); /* PrefCpuDis = 0 */ - Set_NB32(pDCTstat->dev_dct, 0x11c, dword); /* Memory Controller Configuration High */ - } -} - -void DCTMemClr_Init_D(struct MCTStatStruc *pMCTstat, - struct DCTStatStruc *pDCTstat) -{ - u32 val; - u32 dev; - uint32_t dword; - - /* Initiates a memory clear operation on one node */ - if (pDCTstat->DCTSysLimit) { - dev = pDCTstat->dev_dct; - - /* Disable prefetchers */ - dword = Get_NB32(dev, 0x11c); /* Memory Controller Configuration High */ - dword |= 0x1 << 13; /* PrefIoDis = 1 */ - dword |= 0x1 << 12; /* PrefCpuDis = 1 */ - Set_NB32(dev, 0x11c, dword); /* Memory Controller Configuration High */ - - do { - val = Get_NB32(dev, 0x110); - } while (val & (1 << MemClrBusy)); - - val |= (1 << MemClrInit); - Set_NB32(dev, 0x110, val); - } -} - -void DCTMemClr_Sync_D(struct MCTStatStruc *pMCTstat, - struct DCTStatStruc *pDCTstat) -{ - uint32_t dword; - uint32_t dev = pDCTstat->dev_dct; - - printk(BIOS_DEBUG, "%s: Start\n", __func__); - - /* Ensure that a memory clear operation has completed on one node */ - if (pDCTstat->DCTSysLimit) { - printk(BIOS_DEBUG, "%s: Waiting for memory clear to complete", __func__); - do { - dword = Get_NB32(dev, 0x110); - - printk(BIOS_DEBUG, "."); - } while (dword & (1 << MemClrBusy)); - - printk(BIOS_DEBUG, "\n"); - do { - printk(BIOS_DEBUG, "."); - dword = Get_NB32(dev, 0x110); - } while (!(dword & (1 << Dr_MemClrStatus))); - printk(BIOS_DEBUG, "\n"); - } - - /* Enable prefetchers */ - dword = Get_NB32(dev, 0x11c); /* Memory Controller Configuration High */ - dword &= ~(0x1 << 13); /* PrefIoDis = 0 */ - dword &= ~(0x1 << 12); /* PrefCpuDis = 0 */ - Set_NB32(dev, 0x11c, dword); /* Memory Controller Configuration High */ - - printk(BIOS_DEBUG, "%s: Done\n", __func__); -} - -u8 NodePresent_D(u8 Node) -{ - /* - * Determine if a single Hammer Node exists within the network. - */ - u32 dev; - u32 val; - u32 dword; - u8 ret = 0; - - dev = PA_HOST(Node); /*test device/vendor id at host bridge */ - val = Get_NB32(dev, 0); - dword = mct_NodePresent_D(); /* FIXME: BOZO -11001022h rev for F */ - if (val == dword) { /* AMD Hammer Family CPU HT Configuration */ - if (oemNodePresent_D(Node, &ret)) - goto finish; - /* Node ID register */ - val = Get_NB32(dev, 0x60); - val &= 0x07; - dword = Node; - if (val == dword) /* current nodeID = requested nodeID ? */ - ret = 1; - } -finish: - return ret; -} - -static void DCTPreInit_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstat, u8 dct) -{ - /* - * Run DCT pre-initialization tasks - */ - uint32_t dword; - - /* Reset DCT registers */ - ClearDCT_D(pMCTstat, pDCTstat, dct); - pDCTstat->stopDCT[dct] = 1; /* preload flag with 'disable' */ - - if (!is_fam15h()) { - /* Enable DDR3 support */ - dword = Get_NB32_DCT(pDCTstat->dev_dct, dct, 0x94); - dword |= 1 << Ddr3Mode; - Set_NB32_DCT(pDCTstat->dev_dct, dct, 0x94, dword); - } - - /* Read the SPD information into the data structures */ - if (mct_DIMMPresence(pMCTstat, pDCTstat, dct) < SC_StopError) { - printk(BIOS_DEBUG, "\t\tDCTPreInit_D: mct_DIMMPresence Done\n"); - } -} - -static void DCTInit_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstat, u8 dct) -{ - /* - * Initialize DRAM on single Athlon 64/Opteron Node. - */ - uint32_t dword; - - if (!is_fam15h()) { - /* (Re)-enable DDR3 support */ - dword = Get_NB32_DCT(pDCTstat->dev_dct, dct, 0x94); - dword |= 1 << Ddr3Mode; - Set_NB32_DCT(pDCTstat->dev_dct, dct, 0x94, dword); - } - - if (mct_SPDCalcWidth(pMCTstat, pDCTstat, dct) < SC_StopError) { - printk(BIOS_DEBUG, "\t\tDCTInit_D: mct_SPDCalcWidth Done\n"); - if (AutoCycTiming_D(pMCTstat, pDCTstat, dct) < SC_StopError) { - printk(BIOS_DEBUG, "\t\tDCTInit_D: AutoCycTiming_D Done\n"); - - /* SkewMemClk must be set before MemClkFreqVal is set - * This relies on DCTInit_D being called for DCT 1 after - * it has already been called for DCT 0... - */ - if (is_fam15h()) { - /* Set memory clock skew if needed */ - if (dct == 1) { - if (!pDCTstat->stopDCT[0]) { - printk(BIOS_DEBUG, "\t\tDCTInit_D: enabling intra-channel clock skew\n"); - dword = Get_NB32_index_wait_DCT(pDCTstat->dev_dct, 0, 0x98, 0x0d0fe00a); - dword |= (0x1 << 4); /* SkewMemClk = 1 */ - Set_NB32_index_wait_DCT(pDCTstat->dev_dct, 0, 0x98, 0x0d0fe00a, dword); - } - } - } - - if (AutoConfig_D(pMCTstat, pDCTstat, dct) < SC_StopError) { - printk(BIOS_DEBUG, "\t\tDCTInit_D: AutoConfig_D Done\n"); - if (PlatformSpec_D(pMCTstat, pDCTstat, dct) < SC_StopError) { - printk(BIOS_DEBUG, "\t\tDCTInit_D: PlatformSpec_D Done\n"); - pDCTstat->stopDCT[dct] = 0; - } - } - } - } -} - -static void DCTFinalInit_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstat, u8 dct) -{ - uint32_t dword; - - /* Finalize DRAM init on a single node */ - if (!pDCTstat->stopDCT[dct]) { - if (!(pMCTstat->GStatus & (1 << GSB_EnDIMMSpareNW))) { - printk(BIOS_DEBUG, "\t\tDCTFinalInit_D: StartupDCT_D Start\n"); - StartupDCT_D(pMCTstat, pDCTstat, dct); - printk(BIOS_DEBUG, "\t\tDCTFinalInit_D: StartupDCT_D Done\n"); - } - } - - if (pDCTstat->stopDCT[dct]) { - dword = 1 << DisDramInterface; - Set_NB32_DCT(pDCTstat->dev_dct, dct, 0x94, dword); - - dword = Get_NB32_DCT(pDCTstat->dev_dct, dct, 0x90); - dword &= ~(1 << ParEn); - Set_NB32_DCT(pDCTstat->dev_dct, dct, 0x90, dword); - - /* To maximize power savings when DisDramInterface = 1b, - * all of the MemClkDis bits should also be set. - */ - Set_NB32_DCT(pDCTstat->dev_dct, dct, 0x88, 0xff000000); - } else { - mct_EnDllShutdownSR(pMCTstat, pDCTstat, dct); - } -} - -static void SyncDCTsReady_D(struct MCTStatStruc *pMCTstat, - struct DCTStatStruc *pDCTstatA) -{ - /* Wait (and block further access to dram) for all DCTs to be ready, - * by polling all InitDram bits and waiting for possible memory clear - * operations to be complete. Read MemClkFreqVal bit to see if - * the DIMMs are present in this node. - */ - u8 Node; - u32 val; - - for (Node = 0; Node < MAX_NODES_SUPPORTED; Node++) { - struct DCTStatStruc *pDCTstat; - pDCTstat = pDCTstatA + Node; - mct_SyncDCTsReady(pDCTstat); - } - - if (!is_fam15h()) { - /* v6.1.3 */ - /* re-enable phy compensation engine when dram init is completed on all nodes. */ - for (Node = 0; Node < MAX_NODES_SUPPORTED; Node++) { - struct DCTStatStruc *pDCTstat; - pDCTstat = pDCTstatA + Node; - if (pDCTstat->NodePresent) { - if (pDCTstat->DIMMValidDCT[0] > 0 || pDCTstat->DIMMValidDCT[1] > 0) { - /* re-enable phy compensation engine when dram init on both DCTs is completed. */ - val = Get_NB32_index_wait(pDCTstat->dev_dct, 0x98, 0x8); - val &= ~(1 << DisAutoComp); - Set_NB32_index_wait(pDCTstat->dev_dct, 0x98, 0x8, val); - } - } - } - } - - /* wait 750us before any memory access can be made. */ - mct_Wait(15000); -} - -void StartupDCT_D(struct MCTStatStruc *pMCTstat, - struct DCTStatStruc *pDCTstat, u8 dct) -{ - /* Read MemClkFreqVal bit to see if the DIMMs are present in this node. - * If the DIMMs are present then set the DRAM Enable bit for this node. - * - * Setting dram init starts up the DCT state machine, initializes the - * dram devices with MRS commands, and kicks off any - * HW memory clear process that the chip is capable of. The sooner - * that dram init is set for all nodes, the faster the memory system - * initialization can complete. Thus, the init loop is unrolled into - * two loops so as to start the processes for non BSP nodes sooner. - * This procedure will not wait for the process to finish. - * Synchronization is handled elsewhere. - */ - u32 val; - u32 dev; - - dev = pDCTstat->dev_dct; - val = Get_NB32_DCT(dev, dct, 0x94); - if (val & (1<GStatus & (1 << GSB_EnDIMMSpareNW))) - mct_DramInit(pMCTstat, pDCTstat, dct); - AfterDramInit_D(pDCTstat, dct); - mctHookAfterDramInit(); /* generalized Hook*/ - } -} - -static void ClearDCT_D(struct MCTStatStruc *pMCTstat, - struct DCTStatStruc *pDCTstat, u8 dct) -{ - u32 reg_end; - u32 dev = pDCTstat->dev_dct; - u32 reg = 0x40; - u32 val = 0; - - if (pMCTstat->GStatus & (1 << GSB_EnDIMMSpareNW)) { - reg_end = 0x78; - } else { - reg_end = 0xA4; - } - - while (reg < reg_end) { - if ((reg & 0xFF) == 0x84) { - if (is_fam15h()) { - val = Get_NB32_DCT(dev, dct, reg); - val &= ~(0x1 << 23); /* Clear PchgPDModeSel */ - val &= ~0x3; /* Clear BurstCtrl */ - } - } - if ((reg & 0xFF) == 0x90) { - if (pDCTstat->LogicalCPUID & AMD_DR_Dx) { - val = Get_NB32_DCT(dev, dct, reg); /* get DRAMConfigLow */ - val |= 0x08000000; /* preserve value of DisDllShutdownSR for only Rev.D */ - } - } - Set_NB32_DCT(dev, dct, reg, val); - val = 0; - reg += 4; - } - - val = 0; - dev = pDCTstat->dev_map; - reg = 0xF0; - Set_NB32(dev, reg, val); -} - -void SPD2ndTiming(struct MCTStatStruc *pMCTstat, - struct DCTStatStruc *pDCTstat, u8 dct) -{ - u8 i; - u16 Twr, Trtp; - u16 Trp, Trrd, Trcd, Tras, Trc; - u8 Trfc[4]; - u16 Tfaw; - u16 Tcwl; /* Fam15h only */ - u32 DramTimingLo, DramTimingHi; - u8 tCK16x; - u16 Twtr; - uint8_t Etr[2]; - u8 LDIMM; - u8 MTB16x; - u8 byte; - u32 dword; - u32 dev; - u32 val; - - printk(BIOS_DEBUG, "%s: Start\n", __func__); - - /* Gather all DIMM mini-max values for cycle timing data */ - Trp = 0; - Trrd = 0; - Trcd = 0; - Trtp = 0; - Tras = 0; - Trc = 0; - Twr = 0; - Twtr = 0; - for (i = 0; i < 2; i++) - Etr[i] = 0; - for (i = 0; i < 4; i++) - Trfc[i] = 0; - Tfaw = 0; - - for (i = 0; i< MAX_DIMMS_SUPPORTED; i++) { - LDIMM = i >> 1; - if (pDCTstat->DIMMValid & (1 << i)) { - val = pDCTstat->spd_data.spd_bytes[dct + i][SPD_MTBDivisor]; /* MTB = Dividend/Divisor */ - MTB16x = ((pDCTstat->spd_data.spd_bytes[dct + i][SPD_MTBDividend] & 0xff) << 4); - MTB16x /= val; /* transfer to MTB*16 */ - - byte = pDCTstat->spd_data.spd_bytes[dct + i][SPD_tRPmin]; - val = byte * MTB16x; - if (Trp < val) - Trp = val; - - byte = pDCTstat->spd_data.spd_bytes[dct + i][SPD_tRRDmin]; - val = byte * MTB16x; - if (Trrd < val) - Trrd = val; - - byte = pDCTstat->spd_data.spd_bytes[dct + i][SPD_tRCDmin]; - val = byte * MTB16x; - if (Trcd < val) - Trcd = val; - - byte = pDCTstat->spd_data.spd_bytes[dct + i][SPD_tRTPmin]; - val = byte * MTB16x; - if (Trtp < val) - Trtp = val; - - byte = pDCTstat->spd_data.spd_bytes[dct + i][SPD_tWRmin]; - val = byte * MTB16x; - if (Twr < val) - Twr = val; - - byte = pDCTstat->spd_data.spd_bytes[dct + i][SPD_tWTRmin]; - val = byte * MTB16x; - if (Twtr < val) - Twtr = val; - - val = pDCTstat->spd_data.spd_bytes[dct + i][SPD_Upper_tRAS_tRC] & 0xff; - val >>= 4; - val <<= 8; - val |= pDCTstat->spd_data.spd_bytes[dct + i][SPD_tRCmin] & 0xff; - val *= MTB16x; - if (Trc < val) - Trc = val; - - byte = pDCTstat->spd_data.spd_bytes[dct + i][SPD_Density] & 0xf; - if (Trfc[LDIMM] < byte) - Trfc[LDIMM] = byte; - - val = pDCTstat->spd_data.spd_bytes[dct + i][SPD_Upper_tRAS_tRC] & 0xf; - val <<= 8; - val |= (pDCTstat->spd_data.spd_bytes[dct + i][SPD_tRASmin] & 0xff); - val *= MTB16x; - if (Tras < val) - Tras = val; - - val = pDCTstat->spd_data.spd_bytes[dct + i][SPD_Upper_tFAW] & 0xf; - val <<= 8; - val |= pDCTstat->spd_data.spd_bytes[dct + i][SPD_tFAWmin] & 0xff; - val *= MTB16x; - if (Tfaw < val) - Tfaw = val; - - /* Determine if the DIMMs on this channel support 95°C ETR */ - if (pDCTstat->spd_data.spd_bytes[dct + i][SPD_Thermal] & 0x1) - Etr[dct] = 1; - } /* Dimm Present */ - } - - /* Convert DRAM CycleTiming values and store into DCT structure */ - byte = pDCTstat->DIMMAutoSpeed; - if (is_fam15h()) { - if (byte == 0x16) - tCK16x = 17; - else if (byte == 0x12) - tCK16x = 20; - else if (byte == 0xe) - tCK16x = 24; - else if (byte == 0xa) - tCK16x = 30; - else if (byte == 0x6) - tCK16x = 40; - else - tCK16x = 48; - } else { - if (byte == 7) - tCK16x = 20; - else if (byte == 6) - tCK16x = 24; - else if (byte == 5) - tCK16x = 30; - else - tCK16x = 40; - } - - /* Notes: - 1. All secondary time values given in SPDs are in binary with units of ns. - 2. Some time values are scaled by 16, in order to have least count of 0.25 ns - (more accuracy). JEDEC SPD spec. shows which ones are x1 and x4. - 3. Internally to this SW, cycle time, tCK16x, is scaled by 16 to match time values - */ - - /* Tras */ - pDCTstat->DIMMTras = (u16)Tras; - val = Tras / tCK16x; - if (Tras % tCK16x) { /* round up number of busclocks */ - val++; - } - if (val < Min_TrasT) - val = Min_TrasT; - else if (val > Max_TrasT) - val = Max_TrasT; - pDCTstat->Tras = val; - - /* Trp */ - pDCTstat->DIMMTrp = Trp; - val = Trp / tCK16x; - if (Trp % tCK16x) { /* round up number of busclocks */ - val++; - } - if (val < Min_TrpT) - val = Min_TrpT; - else if (val > Max_TrpT) - val = Max_TrpT; - pDCTstat->Trp = val; - - /* Trrd */ - pDCTstat->DIMMTrrd = Trrd; - val = Trrd / tCK16x; - if (Trrd % tCK16x) { /* round up number of busclocks */ - val++; - } - if (val < Min_TrrdT) - val = Min_TrrdT; - else if (val > Max_TrrdT) - val = Max_TrrdT; - pDCTstat->Trrd = val; - - /* Trcd */ - pDCTstat->DIMMTrcd = Trcd; - val = Trcd / tCK16x; - if (Trcd % tCK16x) { /* round up number of busclocks */ - val++; - } - if (val < Min_TrcdT) - val = Min_TrcdT; - else if (val > Max_TrcdT) - val = Max_TrcdT; - pDCTstat->Trcd = val; - - /* Trc */ - pDCTstat->DIMMTrc = Trc; - val = Trc / tCK16x; - if (Trc % tCK16x) { /* round up number of busclocks */ - val++; - } - if (val < Min_TrcT) - val = Min_TrcT; - else if (val > Max_TrcT) - val = Max_TrcT; - pDCTstat->Trc = val; - - /* Trtp */ - pDCTstat->DIMMTrtp = Trtp; - val = Trtp / tCK16x; - if (Trtp % tCK16x) { - val ++; - } - if (val < Min_TrtpT) - val = Min_TrtpT; - else if (val > Max_TrtpT) - val = Max_TrtpT; - pDCTstat->Trtp = val; - - /* Twr */ - pDCTstat->DIMMTwr = Twr; - val = Twr / tCK16x; - if (Twr % tCK16x) { /* round up number of busclocks */ - val++; - } - if (val < Min_TwrT) - val = Min_TwrT; - else if (val > Max_TwrT) - val = Max_TwrT; - pDCTstat->Twr = val; - - /* Twtr */ - pDCTstat->DIMMTwtr = Twtr; - val = Twtr / tCK16x; - if (Twtr % tCK16x) { /* round up number of busclocks */ - val++; - } - if (val < Min_TwtrT) - val = Min_TwtrT; - else if (val > Max_TwtrT) - val = Max_TwtrT; - pDCTstat->Twtr = val; - - /* Trfc0-Trfc3 */ - for (i = 0; i < 4; i++) - pDCTstat->Trfc[i] = Trfc[i]; - - /* Tfaw */ - pDCTstat->DIMMTfaw = Tfaw; - val = Tfaw / tCK16x; - if (Tfaw % tCK16x) { /* round up number of busclocks */ - val++; - } - if (val < Min_TfawT) - val = Min_TfawT; - else if (val > Max_TfawT) - val = Max_TfawT; - pDCTstat->Tfaw = val; - - mctAdjustAutoCycTmg_D(); - - if (is_fam15h()) { - /* Compute Tcwl (Fam15h BKDG v3.14 Table 203) */ - if (pDCTstat->Speed <= 0x6) - Tcwl = 0x5; - else if (pDCTstat->Speed == 0xa) - Tcwl = 0x6; - else if (pDCTstat->Speed == 0xe) - Tcwl = 0x7; - else if (pDCTstat->Speed == 0x12) - Tcwl = 0x8; - else if (pDCTstat->Speed == 0x16) - Tcwl = 0x9; - else - Tcwl = 0x5; /* Power-on default */ - - /* Apply offset */ - Tcwl += pDCTstat->tcwl_delay[dct]; - } - - /* Program DRAM Timing values */ - if (is_fam15h()) { - dev = pDCTstat->dev_dct; - - dword = Get_NB32_DCT(dev, dct, 0x8c); /* DRAM Timing High */ - if (Etr[dct]) - val = 3; /* Tref = 3.9us */ - else - val = 2; /* Tref = 7.8us */ - dword &= ~(0x3 << 16); - dword |= (val & 0x3) << 16; - Set_NB32_DCT(dev, dct, 0x8c, dword); /* DRAM Timing High */ - - dword = Get_NB32_DCT(dev, dct, 0x200); /* DRAM Timing 0 */ - dword &= ~(0x3f1f1f1f); - dword |= (pDCTstat->Tras & 0x3f) << 24; /* Tras */ - val = pDCTstat->Trp; - val = mct_AdjustSPDTimings(pMCTstat, pDCTstat, val); - dword |= (val & 0x1f) << 16; /* Trp */ - dword |= (pDCTstat->Trcd & 0x1f) << 8; /* Trcd */ - dword |= (pDCTstat->CASL & 0x1f); /* Tcl */ - Set_NB32_DCT(dev, dct, 0x200, dword); /* DRAM Timing 0 */ - - dword = Get_NB32_DCT(dev, dct, 0x204); /* DRAM Timing 1 */ - dword &= ~(0x0f3f0f3f); - dword |= (pDCTstat->Trtp & 0xf) << 24; /* Trtp */ - if (pDCTstat->Tfaw != 0) { - val = pDCTstat->Tfaw; - val = mct_AdjustSPDTimings(pMCTstat, pDCTstat, val); - if ((val > 0x5) && (val < 0x2b)) - dword |= (val & 0x3f) << 16; /* FourActWindow */ - } - dword |= (pDCTstat->Trrd & 0xf) << 8; /* Trrd */ - dword |= (pDCTstat->Trc & 0x3f); /* Trc */ - Set_NB32_DCT(dev, dct, 0x204, dword); /* DRAM Timing 1 */ - - /* Trfc0-Trfc3 */ - for (i = 0; i < 4; i++) - if (pDCTstat->Trfc[i] == 0x0) - pDCTstat->Trfc[i] = 0x1; - dword = Get_NB32_DCT(dev, dct, 0x208); /* DRAM Timing 2 */ - dword &= ~(0x07070707); - dword |= (pDCTstat->Trfc[3] & 0x7) << 24; /* Trfc3 */ - dword |= (pDCTstat->Trfc[2] & 0x7) << 16; /* Trfc2 */ - dword |= (pDCTstat->Trfc[1] & 0x7) << 8; /* Trfc1 */ - dword |= (pDCTstat->Trfc[0] & 0x7); /* Trfc0 */ - Set_NB32_DCT(dev, dct, 0x208, dword); /* DRAM Timing 2 */ - - dword = Get_NB32_DCT(dev, dct, 0x20c); /* DRAM Timing 3 */ - dword &= ~(0x00000f00); - dword |= (pDCTstat->Twtr & 0xf) << 8; /* Twtr */ - dword &= ~(0x0000001f); - dword |= (Tcwl & 0x1f); /* Tcwl */ - Set_NB32_DCT(dev, dct, 0x20c, dword); /* DRAM Timing 3 */ - - dword = Get_NB32_DCT(dev, dct, 0x22c); /* DRAM Timing 10 */ - dword &= ~(0x0000001f); - dword |= (pDCTstat->Twr & 0x1f); /* Twr */ - Set_NB32_DCT(dev, dct, 0x22c, dword); /* DRAM Timing 10 */ - - if (pDCTstat->Speed > mhz_to_memclk_config(mctGet_NVbits(NV_MIN_MEMCLK))) { - /* Enable phy-assisted training mode */ - fam15EnableTrainingMode(pMCTstat, pDCTstat, dct, 1); - } - - /* Other setup (not training specific) */ - dword = Get_NB32_DCT(dev, dct, 0x90); /* DRAM Configuration Low */ - dword &= ~(0x1 << 23); /* ForceAutoPchg = 0 */ - dword &= ~(0x1 << 20); /* DynPageCloseEn = 0 */ - Set_NB32_DCT(dev, dct, 0x90, dword); /* DRAM Configuration Low */ - - Set_NB32_DCT(dev, dct, 0x228, 0x14141414); /* DRAM Timing 9 */ - } else { - DramTimingLo = 0; /* Dram Timing Low init */ - val = pDCTstat->CASL - 4; /* pDCTstat.CASL to reg. definition */ - DramTimingLo |= val; - - val = pDCTstat->Trcd - Bias_TrcdT; - DramTimingLo |= val<<4; - - val = pDCTstat->Trp - Bias_TrpT; - val = mct_AdjustSPDTimings(pMCTstat, pDCTstat, val); - DramTimingLo |= val<<7; - - val = pDCTstat->Trtp - Bias_TrtpT; - DramTimingLo |= val<<10; - - val = pDCTstat->Tras - Bias_TrasT; - DramTimingLo |= val<<12; - - val = pDCTstat->Trc - Bias_TrcT; - DramTimingLo |= val<<16; - - val = pDCTstat->Trrd - Bias_TrrdT; - DramTimingLo |= val<<22; - - DramTimingHi = 0; /* Dram Timing High init */ - val = pDCTstat->Twtr - Bias_TwtrT; - DramTimingHi |= val<<8; - - val = 2; /* Tref = 7.8us */ - DramTimingHi |= val<<16; - - val = 0; - for (i = 4; i > 0; i--) { - val <<= 3; - val |= Trfc[i-1]; - } - DramTimingHi |= val << 20; - - dev = pDCTstat->dev_dct; - /* Twr */ - val = pDCTstat->Twr; - if (val == 10) - val = 9; - else if (val == 12) - val = 10; - val = mct_AdjustSPDTimings(pMCTstat, pDCTstat, val); - val -= Bias_TwrT; - val <<= 4; - dword = Get_NB32_DCT(dev, dct, 0x84); - dword &= ~0x70; - dword |= val; - Set_NB32_DCT(dev, dct, 0x84, dword); - - /* Tfaw */ - val = pDCTstat->Tfaw; - val = mct_AdjustSPDTimings(pMCTstat, pDCTstat, val); - val -= Bias_TfawT; - val >>= 1; - val <<= 28; - dword = Get_NB32_DCT(dev, dct, 0x94); - dword &= ~0xf0000000; - dword |= val; - Set_NB32_DCT(dev, dct, 0x94, dword); - - /* dev = pDCTstat->dev_dct; */ - - if (pDCTstat->Speed > mhz_to_memclk_config(mctGet_NVbits(NV_MIN_MEMCLK))) { - val = Get_NB32_DCT(dev, dct, 0x88); - val &= 0xFF000000; - DramTimingLo |= val; - } - Set_NB32_DCT(dev, dct, 0x88, DramTimingLo); /*DCT Timing Low*/ - - if (pDCTstat->Speed > mhz_to_memclk_config(mctGet_NVbits(NV_MIN_MEMCLK))) { - DramTimingHi |= 1 << DisAutoRefresh; - } - DramTimingHi |= 0x000018FF; - Set_NB32_DCT(dev, dct, 0x8c, DramTimingHi); /*DCT Timing Hi*/ - } - - /* dump_pci_device(PCI_DEV(0, 0x18+pDCTstat->Node_ID, 2)); */ - - printk(BIOS_DEBUG, "%s: Done\n", __func__); -} - -static u8 AutoCycTiming_D(struct MCTStatStruc *pMCTstat, - struct DCTStatStruc *pDCTstat, uint8_t dct) -{ - /* Initialize DCT Timing registers as per DIMM SPD. - * For primary timing (T, CL) use best case T value. - * For secondary timing params., use most aggressive settings - * of slowest DIMM. - * - * There are three components to determining "maximum frequency": - * SPD component, Bus load component, and "Preset" max frequency - * component. - * - * The SPD component is a function of the min cycle time specified - * by each DIMM, and the interaction of cycle times from all DIMMs - * in conjunction with CAS latency. The SPD component only applies - * when user timing mode is 'Auto'. - * - * The Bus load component is a limiting factor determined by electrical - * characteristics on the bus as a result of varying number of device - * loads. The Bus load component is specific to each platform but may - * also be a function of other factors. The bus load component only - * applies when user timing mode is 'Auto'. - * - * The Preset component is subdivided into three items and is - * the minimum of the set: Silicon revision, user limit - * setting when user timing mode is 'Auto' and memclock mode - * is 'Limit', OEM build specification of the maximum - * frequency. The Preset component is only applies when user - * timing mode is 'Auto'. - */ - - printk(BIOS_DEBUG, "%s: Start\n", __func__); - - /* Get primary timing (CAS Latency and Cycle Time) */ - if (pDCTstat->Speed == 0) { - mctGet_MaxLoadFreq(pDCTstat); - - /* and Factor in presets (setup options, Si cap, etc.) */ - GetPresetmaxF_D(pMCTstat, pDCTstat); - - /* Go get best T and CL as specified by DIMM mfgs. and OEM */ - SPDGetTCL_D(pMCTstat, pDCTstat, dct); - - /* skip callback mctForce800to1067_D */ - pDCTstat->Speed = pDCTstat->DIMMAutoSpeed; - pDCTstat->CASL = pDCTstat->DIMMCASL; - - } - mct_AfterGetCLT(pMCTstat, pDCTstat, dct); - - SPD2ndTiming(pMCTstat, pDCTstat, dct); - - printk(BIOS_DEBUG, "AutoCycTiming: Status %x\n", pDCTstat->Status); - printk(BIOS_DEBUG, "AutoCycTiming: ErrStatus %x\n", pDCTstat->ErrStatus); - printk(BIOS_DEBUG, "AutoCycTiming: ErrCode %x\n", pDCTstat->ErrCode); - printk(BIOS_DEBUG, "AutoCycTiming: Done\n\n"); - - mctHookAfterAutoCycTmg(); - - return pDCTstat->ErrCode; -} - -static void GetPresetmaxF_D(struct MCTStatStruc *pMCTstat, - struct DCTStatStruc *pDCTstat) -{ - /* Get max frequency from OEM platform definition, from any user - * override (limiting) of max frequency, and from any Si Revision - * Specific information. Return the least of these three in - * DCTStatStruc.PresetmaxFreq. - */ - /* TODO: Set the proper max frequency in wrappers/mcti_d.c. */ - u16 proposedFreq; - u16 word; - - printk(BIOS_DEBUG, "%s: Start\n", __func__); - - /* Get CPU Si Revision defined limit (NPT) */ - if (is_fam15h()) - proposedFreq = 933; - else - proposedFreq = 800; /* Rev F0 programmable max memclock is */ - - /*Get User defined limit if "limit" mode */ - if (mctGet_NVbits(NV_MCTUSRTMGMODE) == 1) { - word = Get_Fk_D(mctGet_NVbits(NV_MemCkVal) + 1); - if (word < proposedFreq) - proposedFreq = word; - - /* Get Platform defined limit */ - word = mctGet_NVbits(NV_MAX_MEMCLK); - if (word < proposedFreq) - proposedFreq = word; - - word = pDCTstat->PresetmaxFreq; - if (word > proposedFreq) - word = proposedFreq; - - pDCTstat->PresetmaxFreq = word; - } - /* Check F3xE8[DdrMaxRate] for maximum DRAM data rate support */ - - printk(BIOS_DEBUG, "%s: Done\n", __func__); -} - -static void SPDGetTCL_D(struct MCTStatStruc *pMCTstat, - struct DCTStatStruc *pDCTstat, uint8_t dct) -{ - /* Find the best T and CL primary timing parameter pair, per Mfg., - * for the given set of DIMMs, and store into DCTStatStruc - * (.DIMMAutoSpeed and .DIMMCASL). See "Global relationship between - * index values and item values" for definition of CAS latency - * index (j) and Frequency index (k). - */ - u8 i, CASLatLow, CASLatHigh; - u16 tAAmin16x; - u8 MTB16x; - u16 tCKmin16x; - u16 tCKproposed16x; - u8 CLactual, CLdesired, CLT_Fail; - uint16_t min_frequency_tck16x; - - u8 byte = 0, bytex = 0; - - CASLatLow = 0xFF; - CASLatHigh = 0xFF; - tAAmin16x = 0; - tCKmin16x = 0; - CLT_Fail = 0; - - printk(BIOS_DEBUG, "%s: Start\n", __func__); - - if (is_fam15h()) { - uint16_t minimum_frequency_mhz = mctGet_NVbits(NV_MIN_MEMCLK); - if (minimum_frequency_mhz == 0) - minimum_frequency_mhz = 333; - min_frequency_tck16x = 16000 / minimum_frequency_mhz; - } else { - min_frequency_tck16x = 40; - } - - for (i = 0; i < MAX_DIMMS_SUPPORTED; i++) { - if (pDCTstat->DIMMValid & (1 << i)) { - /* Step 1: Determine the common set of supported CAS Latency - * values for all modules on the memory channel using the CAS - * Latencies Supported in SPD bytes 14 and 15. - */ - byte = pDCTstat->spd_data.spd_bytes[dct + i][SPD_CASLow]; - CASLatLow &= byte; - byte = pDCTstat->spd_data.spd_bytes[dct + i][SPD_CASHigh]; - CASLatHigh &= byte; - /* Step 2: Determine tAAmin(all) which is the largest tAAmin - value for all modules on the memory channel (SPD byte 16). */ - byte = pDCTstat->spd_data.spd_bytes[dct + i][SPD_MTBDivisor]; - - MTB16x = ((pDCTstat->spd_data.spd_bytes[dct + i][SPD_MTBDividend] & 0xFF)<<4); - MTB16x /= byte; /* transfer to MTB*16 */ - - byte = pDCTstat->spd_data.spd_bytes[dct + i][SPD_tAAmin]; - if (tAAmin16x < byte * MTB16x) - tAAmin16x = byte * MTB16x; - /* Step 3: Determine tCKmin(all) which is the largest tCKmin - value for all modules on the memory channel (SPD byte 12). */ - byte = pDCTstat->spd_data.spd_bytes[dct + i][SPD_tCKmin]; - - if (tCKmin16x < byte * MTB16x) - tCKmin16x = byte * MTB16x; - } - } - /* calculate tCKproposed16x (proposed clock period in ns * 16) */ - tCKproposed16x = 16000 / pDCTstat->PresetmaxFreq; - if (tCKmin16x > tCKproposed16x) - tCKproposed16x = tCKmin16x; - - /* TODO: get user manual tCK16x(Freq.) and overwrite current tCKproposed16x if manual. */ - if (is_fam15h()) { - if (tCKproposed16x == 17) - pDCTstat->TargetFreq = 0x16; - else if (tCKproposed16x <= 20) { - pDCTstat->TargetFreq = 0x12; - tCKproposed16x = 20; - } else if (tCKproposed16x <= 24) { - pDCTstat->TargetFreq = 0xe; - tCKproposed16x = 24; - } else if (tCKproposed16x <= 30) { - pDCTstat->TargetFreq = 0xa; - tCKproposed16x = 30; - } else if (tCKproposed16x <= 40) { - pDCTstat->TargetFreq = 0x6; - tCKproposed16x = 40; - } else { - pDCTstat->TargetFreq = 0x4; - tCKproposed16x = 48; - } - } else { - if (tCKproposed16x == 20) - pDCTstat->TargetFreq = 7; - else if (tCKproposed16x <= 24) { - pDCTstat->TargetFreq = 6; - tCKproposed16x = 24; - } else if (tCKproposed16x <= 30) { - pDCTstat->TargetFreq = 5; - tCKproposed16x = 30; - } else { - pDCTstat->TargetFreq = 4; - tCKproposed16x = 40; - } - } - /* Running through this loop twice: - - First time find tCL at target frequency - - Second time find tCL at 400MHz */ - - for (;;) { - CLT_Fail = 0; - /* Step 4: For a proposed tCK value (tCKproposed) between tCKmin(all) and tCKmax, - determine the desired CAS Latency. If tCKproposed is not a standard JEDEC - value (2.5, 1.875, 1.5, or 1.25 ns) then tCKproposed must be adjusted to the - next lower standard tCK value for calculating CLdesired. - CLdesired = ceiling (tAAmin(all) / tCKproposed) - where tAAmin is defined in Byte 16. The ceiling function requires that the - quotient be rounded up always. */ - CLdesired = tAAmin16x / tCKproposed16x; - if (tAAmin16x % tCKproposed16x) - CLdesired ++; - /* Step 5: Chose an actual CAS Latency (CLactual) that is greather than or equal - to CLdesired and is supported by all modules on the memory channel as - determined in step 1. If no such value exists, choose a higher tCKproposed - value and repeat steps 4 and 5 until a solution is found. */ - for (i = 0, CLactual = 4; i < 15; i++, CLactual++) { - if ((CASLatHigh << 8 | CASLatLow) & (1 << i)) { - if (CLdesired <= CLactual) - break; - } - } - if (i == 15) - CLT_Fail = 1; - /* Step 6: Once the calculation of CLactual is completed, the BIOS must also - verify that this CAS Latency value does not exceed tAAmax, which is 20 ns - for all DDR3 speed grades, by multiplying CLactual times tCKproposed. If - not, choose a lower CL value and repeat steps 5 and 6 until a solution is found. */ - if (CLactual * tCKproposed16x > 320) - CLT_Fail = 1; - /* get CL and T */ - if (!CLT_Fail) { - bytex = CLactual; - if (is_fam15h()) { - if (tCKproposed16x == 17) - byte = 0x16; - else if (tCKproposed16x == 20) - byte = 0x12; - else if (tCKproposed16x == 24) - byte = 0xe; - else if (tCKproposed16x == 30) - byte = 0xa; - else if (tCKproposed16x == 40) - byte = 0x6; - else - byte = 0x4; - } else { - if (tCKproposed16x == 20) - byte = 7; - else if (tCKproposed16x == 24) - byte = 6; - else if (tCKproposed16x == 30) - byte = 5; - else - byte = 4; - } - } else { - /* mctHookManualCLOverride */ - /* TODO: */ - } - - if (tCKproposed16x != min_frequency_tck16x) { - if (pMCTstat->GStatus & (1 << GSB_EnDIMMSpareNW)) { - pDCTstat->DIMMAutoSpeed = byte; - pDCTstat->DIMMCASL = bytex; - break; - } else { - pDCTstat->TargetCASL = bytex; - tCKproposed16x = min_frequency_tck16x; - } - } else { - pDCTstat->DIMMAutoSpeed = byte; - pDCTstat->DIMMCASL = bytex; - break; - } - } - - printk(BIOS_DEBUG, "SPDGetTCL_D: DIMMCASL %x\n", pDCTstat->DIMMCASL); - printk(BIOS_DEBUG, "SPDGetTCL_D: DIMMAutoSpeed %x\n", pDCTstat->DIMMAutoSpeed); - - printk(BIOS_DEBUG, "SPDGetTCL_D: Status %x\n", pDCTstat->Status); - printk(BIOS_DEBUG, "SPDGetTCL_D: ErrStatus %x\n", pDCTstat->ErrStatus); - printk(BIOS_DEBUG, "SPDGetTCL_D: ErrCode %x\n", pDCTstat->ErrCode); - printk(BIOS_DEBUG, "SPDGetTCL_D: Done\n\n"); -} - -u8 PlatformSpec_D(struct MCTStatStruc *pMCTstat, - struct DCTStatStruc *pDCTstat, u8 dct) -{ - if (!is_fam15h()) { - mctGet_PS_Cfg_D(pMCTstat, pDCTstat, dct); - - if (pDCTstat->GangedMode == 1) { - mctGet_PS_Cfg_D(pMCTstat, pDCTstat, 1); - mct_BeforePlatformSpec(pMCTstat, pDCTstat, 1); - } - - set_2t_configuration(pMCTstat, pDCTstat, dct); - - mct_BeforePlatformSpec(pMCTstat, pDCTstat, dct); - mct_PlatformSpec(pMCTstat, pDCTstat, dct); - if (pDCTstat->DIMMAutoSpeed == mhz_to_memclk_config(mctGet_NVbits(NV_MIN_MEMCLK))) - InitPhyCompensation(pMCTstat, pDCTstat, dct); - } - mctHookAfterPSCfg(); - - return pDCTstat->ErrCode; -} - -static u8 AutoConfig_D(struct MCTStatStruc *pMCTstat, - struct DCTStatStruc *pDCTstat, u8 dct) -{ - u32 DramControl, DramTimingLo, Status; - u32 DramConfigLo, DramConfigHi, DramConfigMisc, DramConfigMisc2; - u32 val; - u32 dev; - u16 word; - u32 dword; - u8 byte; - uint32_t offset; - - DramConfigLo = 0; - DramConfigHi = 0; - DramConfigMisc = 0; - DramConfigMisc2 = 0; - - /* set bank addressing and Masks, plus CS pops */ - SPDSetBanks_D(pMCTstat, pDCTstat, dct); - if (pDCTstat->ErrCode == SC_StopError) - goto AutoConfig_exit; - - /* map chip-selects into local address space */ - StitchMemory_D(pMCTstat, pDCTstat, dct); - InterleaveBanks_D(pMCTstat, pDCTstat, dct); - - /* temp image of status (for convenience). RO usage! */ - Status = pDCTstat->Status; - - dev = pDCTstat->dev_dct; - - /* Build Dram Control Register Value */ - DramConfigMisc2 = Get_NB32_DCT(dev, dct, 0xa8); /* Dram Miscellaneous 2 */ - DramControl = Get_NB32_DCT(dev, dct, 0x78); /* Dram Control */ - - /* FIXME: Skip mct_checkForDxSupport */ - /* REV_CALL mct_DoRdPtrInit if not Dx */ - if (pDCTstat->LogicalCPUID & AMD_DR_Bx) - val = 5; - else - val = 6; - DramControl &= ~0xFF; - DramControl |= val; /* RdPtrInit = 6 for Cx CPU */ - - if (mctGet_NVbits(NV_CLKHZAltVidC3)) - DramControl |= 1<<16; /* check */ - - DramControl |= 0x00002A00; - - /* FIXME: Skip for Ax versions */ - /* callback not required - if (!mctParityControl_D()) */ - if (Status & (1 << SB_128bitmode)) - DramConfigLo |= 1 << Width128; /* 128-bit mode (normal) */ - - word = dct; - dword = X4Dimm; - while (word < 8) { - if (pDCTstat->Dimmx4Present & (1 << word)) - DramConfigLo |= 1 << dword; /* X4Dimm[3:0] */ - word++; - word++; - dword++; - } - - if (Status & (1 << SB_Registered)) { - /* Registered DIMMs */ - if (!is_fam15h()) { - DramConfigLo |= 1 << ParEn; - } - } else { - /* Unbuffered DIMMs */ - DramConfigLo |= 1 << UnBuffDimm; - } - - if (mctGet_NVbits(NV_ECC_CAP)) - if (Status & (1 << SB_ECCDIMMs)) - if (mctGet_NVbits(NV_ECC)) - DramConfigLo |= 1 << DimmEcEn; - - DramConfigLo = mct_DisDllShutdownSR(pMCTstat, pDCTstat, DramConfigLo, dct); - - /* Build Dram Config Hi Register Value */ - if (is_fam15h()) - offset = 0x0; - else - offset = 0x1; - dword = pDCTstat->Speed; - DramConfigHi |= dword - offset; /* get MemClk encoding */ - DramConfigHi |= 1 << MemClkFreqVal; - - if (!is_fam15h()) - if (Status & (1 << SB_Registered)) - if ((pDCTstat->Dimmx4Present != 0) && (pDCTstat->Dimmx8Present != 0)) - /* set only if x8 Registered DIMMs in System*/ - DramConfigHi |= 1 << RDqsEn; - - if (pDCTstat->LogicalCPUID & AMD_FAM15_ALL) { - DramConfigLo |= 1 << 25; /* PendRefPaybackS3En = 1 */ - DramConfigLo |= 1 << 24; /* StagRefEn = 1 */ - DramConfigHi |= 1 << 16; /* PowerDownMode = 1 */ - } else { - if (mctGet_NVbits(NV_CKE_CTL)) - /*Chip Select control of CKE*/ - DramConfigHi |= 1 << 16; - } - - if (!is_fam15h()) { - /* Control Bank Swizzle */ - if (0) /* call back not needed mctBankSwizzleControl_D()) */ - DramConfigHi &= ~(1 << BankSwizzleMode); - else - DramConfigHi |= 1 << BankSwizzleMode; /* recommended setting (default) */ - } - - /* Check for Quadrank DIMM presence */ - if (pDCTstat->DimmQRPresent != 0) { - byte = mctGet_NVbits(NV_4RANKType); - if (byte == 2) - DramConfigHi |= 1 << 17; /* S4 (4-Rank SO-DIMMs) */ - else if (byte == 1) - DramConfigHi |= 1 << 18; /* R4 (4-Rank Registered DIMMs) */ - } - - if (0) /* call back not needed mctOverrideDcqBypMax_D) */ - val = mctGet_NVbits(NV_BYPMAX); - else - val = 0x0f; /* recommended setting (default) */ - DramConfigHi |= val << 24; - - if (pDCTstat->LogicalCPUID & (AMD_DR_Dx | AMD_DR_Cx | AMD_DR_Bx | AMD_FAM15_ALL)) - DramConfigHi |= 1 << DcqArbBypassEn; - - /* Build MemClkDis Value from Dram Timing Lo and - Dram Config Misc Registers - 1. We will assume that MemClkDis field has been preset prior to this - point. - 2. We will only set MemClkDis bits if a DIMM is NOT present AND if: - NV_AllMemClks <>0 AND SB_DiagClks == 0 */ - - /* Dram Timing Low (owns Clock Enable bits) */ - DramTimingLo = Get_NB32_DCT(dev, dct, 0x88); - if (mctGet_NVbits(NV_AllMemClks) == 0) { - /* Special Jedec SPD diagnostic bit - "enable all clocks" */ - if (!(pDCTstat->Status & (1<CSPresent & (1<Node_ID, 2)); */ - - printk(BIOS_DEBUG, "AutoConfig: Status %x\n", pDCTstat->Status); - printk(BIOS_DEBUG, "AutoConfig: ErrStatus %x\n", pDCTstat->ErrStatus); - printk(BIOS_DEBUG, "AutoConfig: ErrCode %x\n", pDCTstat->ErrCode); - printk(BIOS_DEBUG, "AutoConfig: Done\n\n"); - -AutoConfig_exit: - return pDCTstat->ErrCode; -} - -static void SPDSetBanks_D(struct MCTStatStruc *pMCTstat, - struct DCTStatStruc *pDCTstat, u8 dct) -{ - /* Set bank addressing, program Mask values and build a chip-select - * population map. This routine programs PCI 0:24N:2x80 config register - * and PCI 0:24N:2x60,64,68,6C config registers (CS Mask 0-3). - */ - u8 ChipSel, Rows, Cols, Ranks, Banks; - u32 BankAddrReg, csMask; - - u32 val; - u32 reg; - u32 dev; - u8 byte; - u16 word; - u32 dword; - - dev = pDCTstat->dev_dct; - - BankAddrReg = 0; - for (ChipSel = 0; ChipSel < MAX_CS_SUPPORTED; ChipSel+=2) { - byte = ChipSel; - if ((pDCTstat->Status & (1 << SB_64MuxedMode)) && ChipSel >=4) - byte -= 3; - - if (pDCTstat->DIMMValid & (1<spd_data.spd_bytes[ChipSel + dct][SPD_Addressing]; - Rows = (byte >> 3) & 0x7; /* Rows:0b = 12-bit,... */ - Cols = byte & 0x7; /* Cols:0b = 9-bit,... */ - - byte = pDCTstat->spd_data.spd_bytes[ChipSel + dct][SPD_Density]; - Banks = (byte >> 4) & 7; /* Banks:0b = 3-bit,... */ - - byte = pDCTstat->spd_data.spd_bytes[ChipSel + dct][SPD_Organization]; - Ranks = ((byte >> 3) & 7) + 1; - - /* Configure Bank encoding - * Use a 6-bit key into a lookup table. - * Key (index) = RRRBCC, where CC is the number of Columns minus 9, - * RRR is the number of Rows minus 12, and B is the number of banks - * minus 3. - */ - byte = Cols; - if (Banks == 1) - byte |= 4; - - byte |= Rows << 3; /* RRRBCC internal encode */ - - for (dword = 0; dword < 13; dword++) { - if (byte == Tab_BankAddr[dword]) - break; - } - - if (dword > 12) - continue; - - /* bit no. of CS field in address mapping reg.*/ - dword <<= (ChipSel<<1); - BankAddrReg |= dword; - - /* Mask value=(2pow(rows+cols+banks+3)-1)>>8, - or 2pow(rows+cols+banks-5)-1*/ - csMask = 0; - - byte = Rows + Cols; /* cl = rows+cols*/ - byte += 21; /* row:12+col:9 */ - byte -= 2; /* 3 banks - 5 */ - - if (pDCTstat->Status & (1 << SB_128bitmode)) - byte++; /* double mask size if in 128-bit mode*/ - - csMask |= 1 << byte; - csMask--; - - /*set ChipSelect population indicator even bits*/ - pDCTstat->CSPresent |= (1<= 2) - /*set ChipSelect population indicator odd bits*/ - pDCTstat->CSPresent |= 1 << (ChipSel + 1); - - reg = 0x60+(ChipSel<<1); /*Dram CS Mask Register */ - val = csMask; - val &= 0x1FF83FE0; /* Mask out reserved bits.*/ - Set_NB32_DCT(dev, dct, reg, val); - } else { - if (pDCTstat->DIMMSPDCSE & (1<CSTestFail |= (1<Status & (1 << SB_128bitmode)) { - SetCSTriState(pMCTstat, pDCTstat, 1); /* force dct1) */ - SetCKETriState(pMCTstat, pDCTstat, 1); /* force dct1) */ - SetODTTriState(pMCTstat, pDCTstat, 1); /* force dct1) */ - } - - word = pDCTstat->CSPresent; - mctGetCS_ExcludeMap(); /* mask out specified chip-selects */ - word ^= pDCTstat->CSPresent; - pDCTstat->CSTestFail |= word; /* enable ODT to disabled DIMMs */ - if (!pDCTstat->CSPresent) - pDCTstat->ErrCode = SC_StopError; - - reg = 0x80; /* Bank Addressing Register */ - Set_NB32_DCT(dev, dct, reg, BankAddrReg); - - pDCTstat->CSPresent_DCT[dct] = pDCTstat->CSPresent; - /* dump_pci_device(PCI_DEV(0, 0x18+pDCTstat->Node_ID, 2)); */ - - printk(BIOS_DEBUG, "SPDSetBanks: CSPresent %x\n", pDCTstat->CSPresent_DCT[dct]); - printk(BIOS_DEBUG, "SPDSetBanks: Status %x\n", pDCTstat->Status); - printk(BIOS_DEBUG, "SPDSetBanks: ErrStatus %x\n", pDCTstat->ErrStatus); - printk(BIOS_DEBUG, "SPDSetBanks: ErrCode %x\n", pDCTstat->ErrCode); - printk(BIOS_DEBUG, "SPDSetBanks: Done\n\n"); -} - -static void SPDCalcWidth_D(struct MCTStatStruc *pMCTstat, - struct DCTStatStruc *pDCTstat) -{ - /* Per SPDs, check the symmetry of DIMM pairs (DIMM on Channel A - * matching with DIMM on Channel B), the overall DIMM population, - * and determine the width mode: 64-bit, 64-bit muxed, 128-bit. - */ - u8 i; - u8 byte, byte1; - - /* Check Symmetry of Channel A and Channel B DIMMs - (must be matched for 128-bit mode).*/ - for (i = 0; i < MAX_DIMMS_SUPPORTED; i += 2) { - if ((pDCTstat->DIMMValid & (1 << i)) && (pDCTstat->DIMMValid & (1<<(i+1)))) { - byte = pDCTstat->spd_data.spd_bytes[i][SPD_Addressing] & 0x7; - byte1 = pDCTstat->spd_data.spd_bytes[i + 1][SPD_Addressing] & 0x7; - if (byte != byte1) { - pDCTstat->ErrStatus |= (1<spd_data.spd_bytes[i][SPD_Density] & 0x0f; - byte1 = pDCTstat->spd_data.spd_bytes[i + 1][SPD_Density] & 0x0f; - if (byte != byte1) { - pDCTstat->ErrStatus |= (1<spd_data.spd_bytes[i][SPD_Organization] & 0x7; - byte1 = pDCTstat->spd_data.spd_bytes[i + 1][SPD_Organization] & 0x7; - if (byte != byte1) { - pDCTstat->ErrStatus |= (1<spd_data.spd_bytes[i][SPD_Organization] >> 3) & 0x7; - byte1 = (pDCTstat->spd_data.spd_bytes[i + 1][SPD_Organization] >> 3) & 0x7; - if (byte != byte1) { - pDCTstat->ErrStatus |= (1<spd_data.spd_bytes[i][SPD_DMBANKS] & 7; /* #ranks-1 */ - byte1 = pDCTstat->spd_data.spd_bytes[i + 1][SPD_DMBANKS] & 7; /* #ranks-1 */ - if (byte != byte1) { - pDCTstat->ErrStatus |= (1<dev_dct; - - _DSpareEn = 0; - - /* CS Sparing 1 = enabled, 0 = disabled */ - if (mctGet_NVbits(NV_CS_SpareCTL) & 1) { - if (MCT_DIMM_SPARE_NO_WARM) { - /* Do no warm-reset DIMM spare */ - if (pMCTstat->GStatus & 1 << GSB_EnDIMMSpareNW) { - word = pDCTstat->CSPresent; - val = bsf(word); - word &= ~(1<ErrStatus |= 1 << SB_SpareDis; - } - } else { - if (!mctGet_NVbits(NV_DQSTrainCTL)) { /*DQS Training 1 = enabled, 0 = disabled */ - word = pDCTstat->CSPresent; - val = bsf(word); - word &= ~(1 << val); - if (word) - /* Make sure at least two chip-selects are available */ - _DSpareEn = 1; - else - pDCTstat->ErrStatus |= 1 << SB_SpareDis; - } - } - } - - nxtcsBase = 0; /* Next available cs base ADDR[39:8] */ - for (p = 0; p < MAX_DIMMS_SUPPORTED; p++) { - BiggestBank = 0; - for (q = 0; q < MAX_CS_SUPPORTED; q++) { /* from DIMMS to CS */ - if (pDCTstat->CSPresent & (1 << q)) { /* bank present? */ - reg = 0x40 + (q << 2); /* Base[q] reg.*/ - val = Get_NB32_DCT(dev, dct, reg); - if (!(val & 3)) { /* (CSEnable|Spare == 1)bank is enabled already? */ - reg = 0x60 + (q << 1); /*Mask[q] reg.*/ - val = Get_NB32_DCT(dev, dct, reg); - val >>= 19; - val++; - val <<= 19; - if (val > BiggestBank) { - /*Bingo! possibly Map this chip-select next! */ - BiggestBank = val; - b = q; - } - } - } /*if bank present */ - } /* while q */ - if (BiggestBank !=0) { - curcsBase = nxtcsBase; /* curcsBase = nxtcsBase*/ - /* DRAM CS Base b Address Register offset */ - reg = 0x40 + (b << 2); - if (_DSpareEn) { - BiggestBank = 0; - val = 1 << Spare; /* Spare Enable*/ - } else { - val = curcsBase; - val |= 1 << CSEnable; /* Bank Enable */ - } - if (((reg - 0x40) >> 2) & 1) { - if (!(pDCTstat->Status & (1 << SB_Registered))) { - u16 dimValid; - dimValid = pDCTstat->DIMMValid; - if (dct & 1) - dimValid <<= 1; - if ((dimValid & pDCTstat->MirrPresU_NumRegR) != 0) { - val |= 1 << onDimmMirror; - } - } - } - Set_NB32_DCT(dev, dct, reg, val); - if (_DSpareEn) - _DSpareEn = 0; - else - /* let nxtcsBase+=Size[b] */ - nxtcsBase += BiggestBank; - } - - /* bank present but disabled?*/ - if (pDCTstat->CSTestFail & (1 << p)) { - /* DRAM CS Base b Address Register offset */ - reg = (p << 2) + 0x40; - val = 1 << TestFail; - Set_NB32_DCT(dev, dct, reg, val); - } - } - - if (nxtcsBase) { - pDCTstat->DCTSysLimit = nxtcsBase - 1; - mct_AfterStitchMemory(pMCTstat, pDCTstat, dct); - } - - /* dump_pci_device(PCI_DEV(0, 0x18+pDCTstat->Node_ID, 2)); */ - - printk(BIOS_DEBUG, "StitchMemory: Status %x\n", pDCTstat->Status); - printk(BIOS_DEBUG, "StitchMemory: ErrStatus %x\n", pDCTstat->ErrStatus); - printk(BIOS_DEBUG, "StitchMemory: ErrCode %x\n", pDCTstat->ErrCode); - printk(BIOS_DEBUG, "StitchMemory: Done\n\n"); -} - -static u16 Get_Fk_D(u8 k) -{ - return Table_F_k[k]; /* FIXME: k or k<<1 ? */ -} - -static u8 DIMMPresence_D(struct MCTStatStruc *pMCTstat, - struct DCTStatStruc *pDCTstat) -{ - /* Check DIMMs present, verify checksum, flag SDRAM type, - * build population indicator bitmaps, and preload bus loading - * of DIMMs into DCTStatStruc. - * MAAload = number of devices on the "A" bus. - * MABload = number of devices on the "B" bus. - * MAAdimms = number of DIMMs on the "A" bus slots. - * MABdimms = number of DIMMs on the "B" bus slots. - * DATAAload = number of ranks on the "A" bus slots. - * DATABload = number of ranks on the "B" bus slots. - */ - u16 i, j, k; - u8 smbaddr; - u8 SPDCtrl; - u16 RegDIMMPresent, LRDIMMPresent, MaxDimms; - u8 devwidth; - u16 DimmSlots; - u8 byte = 0, bytex; - uint8_t crc_status; - - /* preload data structure with addrs */ - mctGet_DIMMAddr(pDCTstat, pDCTstat->Node_ID); - - DimmSlots = MaxDimms = mctGet_NVbits(NV_MAX_DIMMS); - - SPDCtrl = mctGet_NVbits(NV_SPDCHK_RESTRT); - - RegDIMMPresent = 0; - LRDIMMPresent = 0; - pDCTstat->DimmQRPresent = 0; - - for (i = 0; i < MAX_DIMMS_SUPPORTED; i++) { - if (i >= MaxDimms) - break; - - if ((pDCTstat->DimmQRPresent & (1 << i)) || (i < DimmSlots)) { - int status; - smbaddr = Get_DIMMAddress_D(pDCTstat, i); - status = mctRead_SPD(smbaddr, SPD_ByteUse); - if (status >= 0) { - /* Verify result */ - status = mctRead_SPD(smbaddr, SPD_ByteUse); - } - if (status >= 0) { /* SPD access is ok */ - pDCTstat->DIMMPresent |= 1 << i; - read_spd_bytes(pMCTstat, pDCTstat, i); -#ifdef DEBUG_DIMM_SPD - dump_spd_bytes(pMCTstat, pDCTstat, i); -#endif - crc_status = crcCheck(pDCTstat, i); - if (!crc_status) { - /* Try again in case there was a transient glitch */ - read_spd_bytes(pMCTstat, pDCTstat, i); - crc_status = crcCheck(pDCTstat, i); - } - if ((crc_status) || (SPDCtrl == 2)) { /* CRC is OK */ - byte = pDCTstat->spd_data.spd_bytes[i][SPD_TYPE]; - if (byte == JED_DDR3SDRAM) { - /*Dimm is 'Present'*/ - pDCTstat->DIMMValid |= 1 << i; - } - } else { - printk(BIOS_WARNING, "Node %d DIMM %d: SPD checksum invalid\n", pDCTstat->Node_ID, i); - pDCTstat->DIMMSPDCSE = 1 << i; - if (SPDCtrl == 0) { - pDCTstat->ErrStatus |= 1 << SB_DIMMChkSum; - pDCTstat->ErrCode = SC_StopError; - } else { - /*if NV_SPDCHK_RESTRT is set to 1, ignore faulty SPD checksum*/ - pDCTstat->ErrStatus |= 1<spd_data.spd_bytes[i][SPD_TYPE]; - if (byte == JED_DDR3SDRAM) - pDCTstat->DIMMValid |= 1 << i; - } - } - - /* Zero DIMM SPD data cache if DIMM not present / valid */ - if (!(pDCTstat->DIMMValid & (1 << i))) - memset(pDCTstat->spd_data.spd_bytes[i], 0, sizeof(pDCTstat->spd_data.spd_bytes[i])); - - /* Get module information for SMBIOS */ - if (pDCTstat->DIMMValid & (1 << i)) { - pDCTstat->DimmManufacturerID[i] = 0; - for (k = 0; k < 8; k++) - pDCTstat->DimmManufacturerID[i] |= ((uint64_t)pDCTstat->spd_data.spd_bytes[i][SPD_MANID_START + k]) << (k * 8); - for (k = 0; k < SPD_PARTN_LENGTH; k++) - pDCTstat->DimmPartNumber[i][k] = pDCTstat->spd_data.spd_bytes[i][SPD_PARTN_START + k]; - pDCTstat->DimmPartNumber[i][SPD_PARTN_LENGTH] = 0; - pDCTstat->DimmRevisionNumber[i] = 0; - for (k = 0; k < 2; k++) - pDCTstat->DimmRevisionNumber[i] |= ((uint16_t)pDCTstat->spd_data.spd_bytes[i][SPD_REVNO_START + k]) << (k * 8); - pDCTstat->DimmSerialNumber[i] = 0; - for (k = 0; k < 4; k++) - pDCTstat->DimmSerialNumber[i] |= ((uint32_t)pDCTstat->spd_data.spd_bytes[i][SPD_SERIAL_START + k]) << (k * 8); - pDCTstat->DimmRows[i] = (pDCTstat->spd_data.spd_bytes[i][SPD_Addressing] & 0x38) >> 3; - pDCTstat->DimmCols[i] = pDCTstat->spd_data.spd_bytes[i][SPD_Addressing] & 0x7; - pDCTstat->DimmRanks[i] = ((pDCTstat->spd_data.spd_bytes[i][SPD_Organization] & 0x38) >> 3) + 1; - pDCTstat->DimmBanks[i] = 1ULL << (((pDCTstat->spd_data.spd_bytes[i][SPD_Density] & 0x70) >> 4) + 3); - pDCTstat->DimmWidth[i] = 1ULL << ((pDCTstat->spd_data.spd_bytes[i][SPD_BusWidth] & 0x7) + 3); - pDCTstat->DimmChipSize[i] = 1ULL << ((pDCTstat->spd_data.spd_bytes[i][SPD_Density] & 0xf) + 28); - pDCTstat->DimmChipWidth[i] = 1ULL << ((pDCTstat->spd_data.spd_bytes[i][SPD_Organization] & 0x7) + 2); - } - /* Check supported voltage(s) */ - pDCTstat->DimmSupportedVoltages[i] = pDCTstat->spd_data.spd_bytes[i][SPD_Voltage] & 0x7; - pDCTstat->DimmSupportedVoltages[i] ^= 0x1; /* Invert LSB to convert from SPD format to internal bitmap format */ - /* Check module type */ - byte = pDCTstat->spd_data.spd_bytes[i][SPD_DIMMTYPE] & 0x7; - if (byte == JED_RDIMM || byte == JED_MiniRDIMM) { - RegDIMMPresent |= 1 << i; - pDCTstat->DimmRegistered[i] = 1; - } else { - pDCTstat->DimmRegistered[i] = 0; - } - if (byte == JED_LRDIMM) { - LRDIMMPresent |= 1 << i; - pDCTstat->DimmLoadReduced[i] = 1; - } else { - pDCTstat->DimmLoadReduced[i] = 0; - } - /* Check ECC capable */ - byte = pDCTstat->spd_data.spd_bytes[i][SPD_BusWidth]; - if (byte & JED_ECC) { - /* DIMM is ECC capable */ - pDCTstat->DimmECCPresent |= 1 << i; - } - /* Check if x4 device */ - devwidth = pDCTstat->spd_data.spd_bytes[i][SPD_Organization] & 0x7; /* 0:x4,1:x8,2:x16 */ - if (devwidth == 0) { - /* DIMM is made with x4 or x16 drams */ - pDCTstat->Dimmx4Present |= 1 << i; - } else if (devwidth == 1) { - pDCTstat->Dimmx8Present |= 1 << i; - } else if (devwidth == 2) { - pDCTstat->Dimmx16Present |= 1 << i; - } - - byte = (pDCTstat->spd_data.spd_bytes[i][SPD_Organization] >> 3); - byte &= 7; - if (byte == 3) { /* 4ranks */ - /* if any DIMMs are QR, we have to make two passes through DIMMs*/ - if (pDCTstat->DimmQRPresent == 0) { - MaxDimms <<= 1; - } - if (i < DimmSlots) { - pDCTstat->DimmQRPresent |= (1 << i) | (1 << (i+4)); - } else { - pDCTstat->MAdimms[i & 1] --; - } - byte = 1; /* upper two ranks of QR DIMM will be counted on another DIMM number iteration*/ - } else if (byte == 1) { /* 2ranks */ - pDCTstat->DimmDRPresent |= 1 << i; - } - bytex = devwidth; - if (devwidth == 0) - bytex = 16; - else if (devwidth == 1) - bytex = 8; - else if (devwidth == 2) - bytex = 4; - - byte++; /* al+1 = rank# */ - if (byte == 2) - bytex <<= 1; /*double Addr bus load value for dual rank DIMMs*/ - - j = i & (1<<0); - pDCTstat->DATAload[j] += byte; /*number of ranks on DATA bus*/ - pDCTstat->MAload[j] += bytex; /*number of devices on CMD/ADDR bus*/ - pDCTstat->MAdimms[j]++; /*number of DIMMs on A bus */ - - /* check address mirror support for unbuffered dimm */ - /* check number of registers on a dimm for registered dimm */ - byte = pDCTstat->spd_data.spd_bytes[i][SPD_AddressMirror]; - if (RegDIMMPresent & (1 << i)) { - if ((byte & 3) > 1) - pDCTstat->MirrPresU_NumRegR |= 1 << i; - } else { - if ((byte & 1) == 1) - pDCTstat->MirrPresU_NumRegR |= 1 << i; - } - /* Get byte62: Reference Raw Card information. We dont need it now. */ - /* byte = pDCTstat->spd_data.spd_bytes[i][SPD_RefRawCard]; */ - /* Get Byte65/66 for register manufacture ID code */ - if ((0x97 == pDCTstat->spd_data.spd_bytes[i][SPD_RegManufactureID_H]) && - (0x80 == pDCTstat->spd_data.spd_bytes[i][SPD_RegManufactureID_L])) { - if (0x16 == pDCTstat->spd_data.spd_bytes[i][SPD_RegManRevID]) - pDCTstat->RegMan2Present |= 1 << i; - else - pDCTstat->RegMan1Present |= 1 << i; - } - /* Get control word value for RC3 */ - byte = pDCTstat->spd_data.spd_bytes[i][70]; - pDCTstat->CtrlWrd3 |= ((byte >> 4) & 0xf) << (i << 2); /* RC3 = SPD byte 70 [7:4] */ - /* Get control word values for RC4 and RC5 */ - byte = pDCTstat->spd_data.spd_bytes[i][71]; - pDCTstat->CtrlWrd4 |= (byte & 0xf) << (i << 2); /* RC4 = SPD byte 71 [3:0] */ - pDCTstat->CtrlWrd5 |= ((byte >> 4) & 0xf) << (i << 2); /* RC5 = SPD byte 71 [7:4] */ - } - } - } - printk(BIOS_DEBUG, "\t DIMMPresence: DIMMValid=%x\n", pDCTstat->DIMMValid); - printk(BIOS_DEBUG, "\t DIMMPresence: DIMMPresent=%x\n", pDCTstat->DIMMPresent); - printk(BIOS_DEBUG, "\t DIMMPresence: RegDIMMPresent=%x\n", RegDIMMPresent); - printk(BIOS_DEBUG, "\t DIMMPresence: LRDIMMPresent=%x\n", LRDIMMPresent); - printk(BIOS_DEBUG, "\t DIMMPresence: DimmECCPresent=%x\n", pDCTstat->DimmECCPresent); - printk(BIOS_DEBUG, "\t DIMMPresence: DimmPARPresent=%x\n", pDCTstat->DimmPARPresent); - printk(BIOS_DEBUG, "\t DIMMPresence: Dimmx4Present=%x\n", pDCTstat->Dimmx4Present); - printk(BIOS_DEBUG, "\t DIMMPresence: Dimmx8Present=%x\n", pDCTstat->Dimmx8Present); - printk(BIOS_DEBUG, "\t DIMMPresence: Dimmx16Present=%x\n", pDCTstat->Dimmx16Present); - printk(BIOS_DEBUG, "\t DIMMPresence: DimmPlPresent=%x\n", pDCTstat->DimmPlPresent); - printk(BIOS_DEBUG, "\t DIMMPresence: DimmDRPresent=%x\n", pDCTstat->DimmDRPresent); - printk(BIOS_DEBUG, "\t DIMMPresence: DimmQRPresent=%x\n", pDCTstat->DimmQRPresent); - printk(BIOS_DEBUG, "\t DIMMPresence: DATAload[0]=%x\n", pDCTstat->DATAload[0]); - printk(BIOS_DEBUG, "\t DIMMPresence: MAload[0]=%x\n", pDCTstat->MAload[0]); - printk(BIOS_DEBUG, "\t DIMMPresence: MAdimms[0]=%x\n", pDCTstat->MAdimms[0]); - printk(BIOS_DEBUG, "\t DIMMPresence: DATAload[1]=%x\n", pDCTstat->DATAload[1]); - printk(BIOS_DEBUG, "\t DIMMPresence: MAload[1]=%x\n", pDCTstat->MAload[1]); - printk(BIOS_DEBUG, "\t DIMMPresence: MAdimms[1]=%x\n", pDCTstat->MAdimms[1]); - - if (pDCTstat->DIMMValid != 0) { /* If any DIMMs are present...*/ - if (RegDIMMPresent != 0) { - if ((RegDIMMPresent ^ pDCTstat->DIMMValid) !=0) { - /* module type DIMM mismatch (reg'ed, unbuffered) */ - pDCTstat->ErrStatus |= 1<ErrCode = SC_StopError; - } else{ - /* all DIMMs are registered */ - pDCTstat->Status |= 1<DIMMValid) !=0) { - /* module type DIMM mismatch (reg'ed, unbuffered) */ - pDCTstat->ErrStatus |= 1<ErrCode = SC_StopError; - } else{ - /* all DIMMs are registered */ - pDCTstat->Status |= 1<DimmECCPresent != 0) { - if ((pDCTstat->DimmECCPresent ^ pDCTstat->DIMMValid) == 0) { - /* all DIMMs are ECC capable */ - pDCTstat->Status |= 1<DimmPARPresent != 0) { - if ((pDCTstat->DimmPARPresent ^ pDCTstat->DIMMValid) == 0) { - /*all DIMMs are Parity capable */ - pDCTstat->Status |= 1<ErrStatus |= 1<ErrCode = SC_StopError; - } - - printk(BIOS_DEBUG, "\t DIMMPresence: Status %x\n", pDCTstat->Status); - printk(BIOS_DEBUG, "\t DIMMPresence: ErrStatus %x\n", pDCTstat->ErrStatus); - printk(BIOS_DEBUG, "\t DIMMPresence: ErrCode %x\n", pDCTstat->ErrCode); - printk(BIOS_DEBUG, "\t DIMMPresence: Done\n\n"); - - mctHookAfterDIMMpre(); - - return pDCTstat->ErrCode; -} - -static u8 Get_DIMMAddress_D(struct DCTStatStruc *pDCTstat, u8 i) -{ - u8 *p; - - p = pDCTstat->DIMMAddr; - /* mct_BeforeGetDIMMAddress(); */ - return p[i]; -} - -static void mct_preInitDCT(struct MCTStatStruc *pMCTstat, - struct DCTStatStruc *pDCTstat) -{ - u8 err_code; - uint8_t nvram; - uint8_t allow_config_restore; - - /* Preconfigure DCT0 */ - DCTPreInit_D(pMCTstat, pDCTstat, 0); - - /* Configure DCT1 if unganged and enabled*/ - if (!pDCTstat->GangedMode) { - if (pDCTstat->DIMMValidDCT[1] > 0) { - err_code = pDCTstat->ErrCode; /* save DCT0 errors */ - pDCTstat->ErrCode = 0; - DCTPreInit_D(pMCTstat, pDCTstat, 1); - if (pDCTstat->ErrCode == 2) /* DCT1 is not Running */ - pDCTstat->ErrCode = err_code; /* Using DCT0 Error code to update pDCTstat.ErrCode */ - } - } - -#if CONFIG(HAVE_ACPI_RESUME) - calculate_and_store_spd_hashes(pMCTstat, pDCTstat); - - if (load_spd_hashes_from_nvram(pMCTstat, pDCTstat) < 0) { - pDCTstat->spd_data.nvram_spd_match = 0; - } else { - compare_nvram_spd_hashes(pMCTstat, pDCTstat); - } -#else - pDCTstat->spd_data.nvram_spd_match = 0; -#endif - - /* Check to see if restoration of SPD data from NVRAM is allowed */ - allow_config_restore = 0; - if (get_option(&nvram, "allow_spd_nvram_cache_restore") == CB_SUCCESS) - allow_config_restore = !!nvram; - -#if CONFIG(HAVE_ACPI_RESUME) - if (pMCTstat->nvram_checksum != calculate_nvram_mct_hash()) - allow_config_restore = 0; -#else - allow_config_restore = 0; -#endif - - if (!allow_config_restore) - pDCTstat->spd_data.nvram_spd_match = 0; -} - -static void mct_initDCT(struct MCTStatStruc *pMCTstat, - struct DCTStatStruc *pDCTstat) -{ - u32 val; - u8 err_code; - - /* Config. DCT0 for Ganged or unganged mode */ - DCTInit_D(pMCTstat, pDCTstat, 0); - DCTFinalInit_D(pMCTstat, pDCTstat, 0); - if (pDCTstat->ErrCode == SC_FatalErr) { - /* Do nothing goto exitDCTInit; any fatal errors? */ - } else { - /* Configure DCT1 if unganged and enabled */ - if (!pDCTstat->GangedMode) { - if (pDCTstat->DIMMValidDCT[1] > 0) { - err_code = pDCTstat->ErrCode; /* save DCT0 errors */ - pDCTstat->ErrCode = 0; - DCTInit_D(pMCTstat, pDCTstat, 1); - DCTFinalInit_D(pMCTstat, pDCTstat, 1); - if (pDCTstat->ErrCode == 2) /* DCT1 is not Running */ - pDCTstat->ErrCode = err_code; /* Using DCT0 Error code to update pDCTstat.ErrCode */ - } else { - val = 1 << DisDramInterface; - Set_NB32_DCT(pDCTstat->dev_dct, 1, 0x94, val); - - val = Get_NB32_DCT(pDCTstat->dev_dct, 1, 0x90); - val &= ~(1 << ParEn); - Set_NB32_DCT(pDCTstat->dev_dct, 1, 0x90, val); - - /* To maximize power savings when DisDramInterface = 1b, - * all of the MemClkDis bits should also be set. - */ - Set_NB32_DCT(pDCTstat->dev_dct, 1, 0x88, 0xff000000); - } - } - } -} - -static void mct_DramInit(struct MCTStatStruc *pMCTstat, - struct DCTStatStruc *pDCTstat, u8 dct) -{ - mct_BeforeDramInit_Prod_D(pMCTstat, pDCTstat, dct); - mct_DramInit_Sw_D(pMCTstat, pDCTstat, dct); - /* mct_DramInit_Hw_D(pMCTstat, pDCTstat, dct); */ -} - -static u8 mct_setMode(struct MCTStatStruc *pMCTstat, - struct DCTStatStruc *pDCTstat) -{ - u8 byte; - u8 bytex; - u32 val; - u32 reg; - - byte = bytex = pDCTstat->DIMMValid; - bytex &= 0x55; /* CHA DIMM pop */ - pDCTstat->DIMMValidDCT[0] = bytex; - - byte &= 0xAA; /* CHB DIMM popa */ - byte >>= 1; - pDCTstat->DIMMValidDCT[1] = byte; - - if (byte != bytex) { - pDCTstat->ErrStatus &= ~(1 << SB_DimmMismatchO); - } else { - byte = mctGet_NVbits(NV_Unganged); - if (byte) - pDCTstat->ErrStatus |= (1 << SB_DimmMismatchO); /* Set temp. to avoid setting of ganged mode */ - - if ((!(pDCTstat->ErrStatus & (1 << SB_DimmMismatchO))) && (pDCTstat->LogicalCPUID & AMD_FAM10_ALL)) { - /* Ganged channel mode not supported on Family 15h or higher */ - pDCTstat->GangedMode = 1; - /* valid 128-bit mode population. */ - pDCTstat->Status |= 1 << SB_128bitmode; - reg = 0x110; - val = Get_NB32(pDCTstat->dev_dct, reg); - val |= 1 << DctGangEn; - Set_NB32(pDCTstat->dev_dct, reg, val); - } - if (byte) /* NV_Unganged */ - pDCTstat->ErrStatus &= ~(1 << SB_DimmMismatchO); /* Clear so that there is no DIMM mismatch error */ - } - - return pDCTstat->ErrCode; -} - -u32 Get_NB32(u32 dev, u32 reg) -{ - return pci_read_config32(dev, reg); -} - -void Set_NB32(u32 dev, u32 reg, u32 val) -{ - pci_write_config32(dev, reg, val); -} - - -u32 Get_NB32_index(u32 dev, u32 index_reg, u32 index) -{ - u32 dword; - - Set_NB32(dev, index_reg, index); - dword = Get_NB32(dev, index_reg+0x4); - - return dword; -} - -void Set_NB32_index(u32 dev, u32 index_reg, u32 index, u32 data) -{ - Set_NB32(dev, index_reg, index); - Set_NB32(dev, index_reg + 0x4, data); -} - -u32 Get_NB32_index_wait(u32 dev, u32 index_reg, u32 index) -{ - u32 dword; - - index &= ~(1 << DctAccessWrite); - Set_NB32(dev, index_reg, index); - do { - dword = Get_NB32(dev, index_reg); - } while (!(dword & (1 << DctAccessDone))); - dword = Get_NB32(dev, index_reg + 0x4); - - return dword; -} - -void Set_NB32_index_wait(u32 dev, u32 index_reg, u32 index, u32 data) -{ - u32 dword; - - Set_NB32(dev, index_reg + 0x4, data); - index |= (1 << DctAccessWrite); - Set_NB32(dev, index_reg, index); - do { - dword = Get_NB32(dev, index_reg); - } while (!(dword & (1 << DctAccessDone))); - -} - -u8 mct_BeforePlatformSpec(struct MCTStatStruc *pMCTstat, - struct DCTStatStruc *pDCTstat, u8 dct) -{ - printk(BIOS_DEBUG, "%s: Start\n", __func__); - - /* mct_checkForCxDxSupport_D */ - if (pDCTstat->LogicalCPUID & AMD_DR_GT_Bx) { - /* Family 10h Errata 322: Address and Command Fine Delay Values May Be Incorrect */ - /* 1. Write 00000000h to F2x[1,0]9C_xD08E000 */ - Set_NB32_index_wait_DCT(pDCTstat->dev_dct, dct, 0x98, 0x0D08E000, 0); - /* 2. If DRAM Configuration Register[MemClkFreq] (F2x[1,0]94[2:0]) is - greater than or equal to 011b (DDR-800 and higher), - then write 00000080h to F2x[1,0]9C_xD02E001, - else write 00000090h to F2x[1,0]9C_xD02E001. */ - if (pDCTstat->Speed >= mhz_to_memclk_config(mctGet_NVbits(NV_MIN_MEMCLK))) - Set_NB32_index_wait_DCT(pDCTstat->dev_dct, dct, 0x98, 0x0D02E001, 0x80); - else - Set_NB32_index_wait_DCT(pDCTstat->dev_dct, dct, 0x98, 0x0D02E001, 0x90); - } - - printk(BIOS_DEBUG, "%s: Done\n", __func__); - - return pDCTstat->ErrCode; -} - -u8 mct_PlatformSpec(struct MCTStatStruc *pMCTstat, - struct DCTStatStruc *pDCTstat, u8 dct) -{ - /* Get platform specific config/timing values from the interface layer - * and program them into DCT. - */ - - printk(BIOS_DEBUG, "%s: Start\n", __func__); - - u32 dev = pDCTstat->dev_dct; - u32 index_reg; - u8 i, i_start, i_end; - - if (pDCTstat->GangedMode) { - SyncSetting(pDCTstat); - /* mct_SetupSync_D */ - i_start = 0; - i_end = 2; - } else { - i_start = dct; - i_end = dct + 1; - } - for (i = i_start; i < i_end; i++) { - index_reg = 0x98; - Set_NB32_index_wait_DCT(dev, i, index_reg, 0x00, pDCTstat->CH_ODC_CTL[i]); /* Channel A/B Output Driver Compensation Control */ - Set_NB32_index_wait_DCT(dev, i, index_reg, 0x04, pDCTstat->CH_ADDR_TMG[i]); /* Channel A/B Output Driver Compensation Control */ - printk(BIOS_SPEW, "Programmed DCT %d timing/termination pattern %08x %08x\n", dct, pDCTstat->CH_ADDR_TMG[i], pDCTstat->CH_ODC_CTL[i]); - } - - printk(BIOS_DEBUG, "%s: Done\n", __func__); - - return pDCTstat->ErrCode; -} - -static void mct_SyncDCTsReady(struct DCTStatStruc *pDCTstat) -{ - u32 dev; - u32 val; - - if (pDCTstat->NodePresent) { - dev = pDCTstat->dev_dct; - - if ((pDCTstat->DIMMValidDCT[0]) || (pDCTstat->DIMMValidDCT[1])) { - /* This Node has DRAM */ - do { - val = Get_NB32(dev, 0x110); - } while (!(val & (1 << DramEnabled))); - } - } /* Node is present */ -} - -static void mct_AfterGetCLT(struct MCTStatStruc *pMCTstat, - struct DCTStatStruc *pDCTstat, u8 dct) -{ - if (!pDCTstat->GangedMode) { - if (dct == 0) { - pDCTstat->DIMMValid = pDCTstat->DIMMValidDCT[dct]; - if (pDCTstat->DIMMValidDCT[dct] == 0) - pDCTstat->ErrCode = SC_StopError; - } else { - pDCTstat->CSPresent = 0; - pDCTstat->CSTestFail = 0; - pDCTstat->DIMMValid = pDCTstat->DIMMValidDCT[dct]; - if (pDCTstat->DIMMValidDCT[dct] == 0) - pDCTstat->ErrCode = SC_StopError; - } - } -} - -static u8 mct_SPDCalcWidth(struct MCTStatStruc *pMCTstat, - struct DCTStatStruc *pDCTstat, u8 dct) -{ - u8 ret; - u32 val; - - if (dct == 0) { - SPDCalcWidth_D(pMCTstat, pDCTstat); - ret = mct_setMode(pMCTstat, pDCTstat); - } else { - ret = pDCTstat->ErrCode; - } - - if (pDCTstat->DIMMValidDCT[0] == 0) { - val = Get_NB32_DCT(pDCTstat->dev_dct, 0, 0x94); - val |= 1 << DisDramInterface; - Set_NB32_DCT(pDCTstat->dev_dct, 0, 0x94, val); - - val = Get_NB32_DCT(pDCTstat->dev_dct, 0, 0x90); - val &= ~(1 << ParEn); - Set_NB32_DCT(pDCTstat->dev_dct, 0, 0x90, val); - } - if (pDCTstat->DIMMValidDCT[1] == 0) { - val = Get_NB32_DCT(pDCTstat->dev_dct, 1, 0x94); - val |= 1 << DisDramInterface; - Set_NB32_DCT(pDCTstat->dev_dct, 1, 0x94, val); - - val = Get_NB32_DCT(pDCTstat->dev_dct, 1, 0x90); - val &= ~(1 << ParEn); - Set_NB32_DCT(pDCTstat->dev_dct, 1, 0x90, val); - } - - printk(BIOS_DEBUG, "SPDCalcWidth: Status %x\n", pDCTstat->Status); - printk(BIOS_DEBUG, "SPDCalcWidth: ErrStatus %x\n", pDCTstat->ErrStatus); - printk(BIOS_DEBUG, "SPDCalcWidth: ErrCode %x\n", pDCTstat->ErrCode); - printk(BIOS_DEBUG, "SPDCalcWidth: Done\n"); - /* Disable dram interface before DRAM init */ - - return ret; -} - -static void mct_AfterStitchMemory(struct MCTStatStruc *pMCTstat, - struct DCTStatStruc *pDCTstat, u8 dct) -{ - u32 val; - u32 dword; - u32 dev; - u32 reg; - u8 _MemHoleRemap; - u32 DramHoleBase; - - _MemHoleRemap = mctGet_NVbits(NV_MemHole); - DramHoleBase = mctGet_NVbits(NV_BottomIO); - DramHoleBase <<= 8; - /* Increase hole size so;[31:24]to[31:16] - * it has granularity of 128MB shl eax,8 - * Set 'effective' bottom IOmov DramHoleBase,eax - */ - pMCTstat->HoleBase = (DramHoleBase & 0xFFFFF800) << 8; - - /* In unganged mode, we must add DCT0 and DCT1 to DCTSysLimit */ - if (!pDCTstat->GangedMode) { - dev = pDCTstat->dev_dct; - pDCTstat->NodeSysLimit += pDCTstat->DCTSysLimit; - /* if DCT0 and DCT1 both exist, set DctSelBaseAddr[47:27] to the top of DCT0 */ - if (dct == 0) { - if (pDCTstat->DIMMValidDCT[1] > 0) { - dword = pDCTstat->DCTSysLimit + 1; - dword += pDCTstat->NodeSysBase; - dword >>= 8; /* scale [39:8] to [47:27],and to F2x110[31:11] */ - if ((dword >= DramHoleBase) && _MemHoleRemap) { - pMCTstat->HoleBase = (DramHoleBase & 0xFFFFF800) << 8; - val = pMCTstat->HoleBase; - val >>= 16; - val = (((~val) & 0xFF) + 1); - val <<= 8; - dword += val; - } - reg = 0x110; - val = Get_NB32(dev, reg); - val &= 0x7F; - val |= dword; - val |= 3; /* Set F2x110[DctSelHiRngEn], F2x110[DctSelHi] */ - Set_NB32(dev, reg, val); - - reg = 0x114; - val = dword; - Set_NB32(dev, reg, val); - } - } else { - /* Program the DctSelBaseAddr value to 0 - if DCT 0 is disabled */ - if (pDCTstat->DIMMValidDCT[0] == 0) { - dword = pDCTstat->NodeSysBase; - dword >>= 8; - if ((dword >= DramHoleBase) && _MemHoleRemap) { - pMCTstat->HoleBase = (DramHoleBase & 0xFFFFF800) << 8; - val = pMCTstat->HoleBase; - val >>= 8; - val &= ~(0xFFFF); - val |= (((~val) & 0xFFFF) + 1); - dword += val; - } - reg = 0x114; - val = dword; - Set_NB32(dev, reg, val); - - reg = 0x110; - val |= 3; /* Set F2x110[DctSelHiRngEn], F2x110[DctSelHi] */ - Set_NB32(dev, reg, val); - } - } - } else { - pDCTstat->NodeSysLimit += pDCTstat->DCTSysLimit; - } - printk(BIOS_DEBUG, "AfterStitch pDCTstat->NodeSysBase = %x\n", pDCTstat->NodeSysBase); - printk(BIOS_DEBUG, "mct_AfterStitchMemory: pDCTstat->NodeSysLimit = %x\n", pDCTstat->NodeSysLimit); -} - -static u8 mct_DIMMPresence(struct MCTStatStruc *pMCTstat, - struct DCTStatStruc *pDCTstat, u8 dct) -{ - u8 ret; - - if (dct == 0) - ret = DIMMPresence_D(pMCTstat, pDCTstat); - else - ret = pDCTstat->ErrCode; - - return ret; -} - -/* mct_BeforeGetDIMMAddress inline in C */ - -static void mct_OtherTiming(struct MCTStatStruc *pMCTstat, - struct DCTStatStruc *pDCTstatA) -{ - u8 Node; - - for (Node = 0; Node < MAX_NODES_SUPPORTED; Node++) { - struct DCTStatStruc *pDCTstat; - pDCTstat = pDCTstatA + Node; - if (pDCTstat->NodePresent) { - if (pDCTstat->DIMMValidDCT[0]) { - pDCTstat->DIMMValid = pDCTstat->DIMMValidDCT[0]; - Set_OtherTiming(pMCTstat, pDCTstat, 0); - } - if (pDCTstat->DIMMValidDCT[1] && !pDCTstat->GangedMode) { - pDCTstat->DIMMValid = pDCTstat->DIMMValidDCT[1]; - Set_OtherTiming(pMCTstat, pDCTstat, 1); - } - } /* Node is present*/ - } /* while Node */ -} - -static void Set_OtherTiming(struct MCTStatStruc *pMCTstat, - struct DCTStatStruc *pDCTstat, u8 dct) -{ - u32 reg; - u32 val; - u32 dword; - u32 dev = pDCTstat->dev_dct; - - Get_DqsRcvEnGross_Diff(pDCTstat, dev, dct, 0x98); - Get_WrDatGross_Diff(pDCTstat, dct, dev, 0x98); - Get_Trdrd(pMCTstat, pDCTstat, dct); - Get_Twrwr(pMCTstat, pDCTstat, dct); - Get_Twrrd(pMCTstat, pDCTstat, dct); - Get_TrwtTO(pMCTstat, pDCTstat, dct); - Get_TrwtWB(pMCTstat, pDCTstat); - - if (!is_fam15h()) { - reg = 0x8c; /* Dram Timing Hi */ - val = Get_NB32_DCT(dev, dct, reg); - val &= 0xffff0300; - dword = pDCTstat->TrwtTO; - val |= dword << 4; - dword = pDCTstat->Twrrd & 3; - val |= dword << 10; - dword = pDCTstat->Twrwr & 3; - val |= dword << 12; - dword = (pDCTstat->Trdrd - 0x3) & 3; - val |= dword << 14; - dword = pDCTstat->TrwtWB; - val |= dword; - Set_NB32_DCT(dev, dct, reg, val); - - reg = 0x78; - val = Get_NB32_DCT(dev, dct, reg); - val &= 0xffffc0ff; - dword = pDCTstat->Twrrd >> 2; - val |= dword << 8; - dword = pDCTstat->Twrwr >> 2; - val |= dword << 10; - dword = (pDCTstat->Trdrd - 0x3) >> 2; - val |= dword << 12; - Set_NB32_DCT(dev, dct, reg, val); - } -} - -static void Get_Trdrd(struct MCTStatStruc *pMCTstat, - struct DCTStatStruc *pDCTstat, u8 dct) -{ - int8_t Trdrd; - - Trdrd = ((int8_t)(pDCTstat->DqsRcvEnGrossMax - pDCTstat->DqsRcvEnGrossMin) >> 1) + 1; - if (Trdrd > 8) - Trdrd = 8; - if (Trdrd < 3) - Trdrd = 3; - pDCTstat->Trdrd = Trdrd; -} - -static void Get_Twrwr(struct MCTStatStruc *pMCTstat, - struct DCTStatStruc *pDCTstat, u8 dct) -{ - int8_t Twrwr = 0; - - Twrwr = ((int8_t)(pDCTstat->WrDatGrossMax - pDCTstat->WrDatGrossMin) >> 1) + 2; - - if (Twrwr < 2) - Twrwr = 2; - else if (Twrwr > 9) - Twrwr = 9; - - pDCTstat->Twrwr = Twrwr; -} - -static void Get_Twrrd(struct MCTStatStruc *pMCTstat, - struct DCTStatStruc *pDCTstat, u8 dct) -{ - u8 LDplus1; - int8_t Twrrd; - - LDplus1 = Get_Latency_Diff(pMCTstat, pDCTstat, dct); - - Twrrd = ((int8_t)(pDCTstat->WrDatGrossMax - pDCTstat->DqsRcvEnGrossMin) >> 1) + 4 - LDplus1; - - if (Twrrd < 2) - Twrrd = 2; - else if (Twrrd > 10) - Twrrd = 10; - pDCTstat->Twrrd = Twrrd; -} - -static void Get_TrwtTO(struct MCTStatStruc *pMCTstat, - struct DCTStatStruc *pDCTstat, u8 dct) -{ - u8 LDplus1; - int8_t TrwtTO; - - LDplus1 = Get_Latency_Diff(pMCTstat, pDCTstat, dct); - - TrwtTO = ((int8_t)(pDCTstat->DqsRcvEnGrossMax - pDCTstat->WrDatGrossMin) >> 1) + LDplus1; - - pDCTstat->TrwtTO = TrwtTO; -} - -static void Get_TrwtWB(struct MCTStatStruc *pMCTstat, - struct DCTStatStruc *pDCTstat) -{ - /* TrwtWB ensures read-to-write data-bus turnaround. - This value should be one more than the programmed TrwtTO.*/ - pDCTstat->TrwtWB = pDCTstat->TrwtTO; -} - -static u8 Get_Latency_Diff(struct MCTStatStruc *pMCTstat, - struct DCTStatStruc *pDCTstat, u8 dct) -{ - u32 dev = pDCTstat->dev_dct; - u32 val1, val2; - - val1 = Get_NB32_DCT(dev, dct, 0x88) & 0xF; - val2 = (Get_NB32_DCT(dev, dct, 0x84) >> 20) & 7; - - return val1 - val2; -} - -static void Get_DqsRcvEnGross_Diff(struct DCTStatStruc *pDCTstat, - u32 dev, uint8_t dct, u32 index_reg) -{ - u8 Smallest, Largest; - u32 val; - u8 byte, bytex; - - /* The largest DqsRcvEnGrossDelay of any DIMM minus the - DqsRcvEnGrossDelay of any other DIMM is equal to the Critical - Gross Delay Difference (CGDD) */ - /* DqsRcvEn byte 1,0 */ - val = Get_DqsRcvEnGross_MaxMin(pDCTstat, dev, dct, index_reg, 0x10); - Largest = val & 0xFF; - Smallest = (val >> 8) & 0xFF; - - /* DqsRcvEn byte 3,2 */ - val = Get_DqsRcvEnGross_MaxMin(pDCTstat, dev, dct, index_reg, 0x11); - byte = val & 0xFF; - bytex = (val >> 8) & 0xFF; - if (bytex < Smallest) - Smallest = bytex; - if (byte > Largest) - Largest = byte; - - /* DqsRcvEn byte 5,4 */ - val = Get_DqsRcvEnGross_MaxMin(pDCTstat, dev, dct, index_reg, 0x20); - byte = val & 0xFF; - bytex = (val >> 8) & 0xFF; - if (bytex < Smallest) - Smallest = bytex; - if (byte > Largest) - Largest = byte; - - /* DqsRcvEn byte 7,6 */ - val = Get_DqsRcvEnGross_MaxMin(pDCTstat, dev, dct, index_reg, 0x21); - byte = val & 0xFF; - bytex = (val >> 8) & 0xFF; - if (bytex < Smallest) - Smallest = bytex; - if (byte > Largest) - Largest = byte; - - if (pDCTstat->DimmECCPresent> 0) { - /*DqsRcvEn Ecc */ - val = Get_DqsRcvEnGross_MaxMin(pDCTstat, dev, dct, index_reg, 0x12); - byte = val & 0xFF; - bytex = (val >> 8) & 0xFF; - if (bytex < Smallest) - Smallest = bytex; - if (byte > Largest) - Largest = byte; - } - - pDCTstat->DqsRcvEnGrossMax = Largest; - pDCTstat->DqsRcvEnGrossMin = Smallest; -} - -static void Get_WrDatGross_Diff(struct DCTStatStruc *pDCTstat, - u8 dct, u32 dev, u32 index_reg) -{ - u8 Smallest = 0, Largest = 0; - u32 val; - u8 byte, bytex; - - /* The largest WrDatGrossDlyByte of any DIMM minus the - WrDatGrossDlyByte of any other DIMM is equal to CGDD */ - if (pDCTstat->DIMMValid & (1 << 0)) { - val = Get_WrDatGross_MaxMin(pDCTstat, dct, dev, index_reg, 0x01); /* WrDatGrossDlyByte byte 0,1,2,3 for DIMM0 */ - Largest = val & 0xFF; - Smallest = (val >> 8) & 0xFF; - } - if (pDCTstat->DIMMValid & (1 << 2)) { - val = Get_WrDatGross_MaxMin(pDCTstat, dct, dev, index_reg, 0x101); /* WrDatGrossDlyByte byte 0,1,2,3 for DIMM1 */ - byte = val & 0xFF; - bytex = (val >> 8) & 0xFF; - if (bytex < Smallest) - Smallest = bytex; - if (byte > Largest) - Largest = byte; - } - - /* If Cx, 2 more dimm need to be checked to find out the largest and smallest */ - if (pDCTstat->LogicalCPUID & AMD_DR_Cx) { - if (pDCTstat->DIMMValid & (1 << 4)) { - val = Get_WrDatGross_MaxMin(pDCTstat, dct, dev, index_reg, 0x201); /* WrDatGrossDlyByte byte 0,1,2,3 for DIMM2 */ - byte = val & 0xFF; - bytex = (val >> 8) & 0xFF; - if (bytex < Smallest) - Smallest = bytex; - if (byte > Largest) - Largest = byte; - } - if (pDCTstat->DIMMValid & (1 << 6)) { - val = Get_WrDatGross_MaxMin(pDCTstat, dct, dev, index_reg, 0x301); /* WrDatGrossDlyByte byte 0,1,2,3 for DIMM2 */ - byte = val & 0xFF; - bytex = (val >> 8) & 0xFF; - if (bytex < Smallest) - Smallest = bytex; - if (byte > Largest) - Largest = byte; - } - } - - pDCTstat->WrDatGrossMax = Largest; - pDCTstat->WrDatGrossMin = Smallest; -} - -static u16 Get_DqsRcvEnGross_MaxMin(struct DCTStatStruc *pDCTstat, - u32 dev, uint8_t dct, u32 index_reg, - u32 index) -{ - u8 Smallest, Largest; - u8 i; - u8 byte; - u32 val; - u16 word; - u8 ecc_reg = 0; - - Smallest = 7; - Largest = 0; - - if (index == 0x12) - ecc_reg = 1; - - for (i = 0; i < 8; i+=2) { - if (pDCTstat->DIMMValid & (1 << i)) { - val = Get_NB32_index_wait_DCT(dev, dct, index_reg, index); - val &= 0x00E000E0; - byte = (val >> 5) & 0xFF; - if (byte < Smallest) - Smallest = byte; - if (byte > Largest) - Largest = byte; - if (!(ecc_reg)) { - byte = (val >> (16 + 5)) & 0xFF; - if (byte < Smallest) - Smallest = byte; - if (byte > Largest) - Largest = byte; - } - } - index += 3; - } /* while ++i */ - - word = Smallest; - word <<= 8; - word |= Largest; - - return word; -} - -static u16 Get_WrDatGross_MaxMin(struct DCTStatStruc *pDCTstat, - u8 dct, u32 dev, u32 index_reg, - u32 index) -{ - u8 Smallest, Largest; - u8 i, j; - u32 val; - u8 byte; - u16 word; - - Smallest = 3; - Largest = 0; - for (i = 0; i < 2; i++) { - val = Get_NB32_index_wait_DCT(dev, dct, index_reg, index); - val &= 0x60606060; - val >>= 5; - for (j = 0; j < 4; j++) { - byte = val & 0xFF; - if (byte < Smallest) - Smallest = byte; - if (byte > Largest) - Largest = byte; - val >>= 8; - } /* while ++j */ - index++; - } /*while ++i*/ - - if (pDCTstat->DimmECCPresent > 0) { - index++; - val = Get_NB32_index_wait_DCT(dev, dct, index_reg, index); - val &= 0x00000060; - val >>= 5; - byte = val & 0xFF; - if (byte < Smallest) - Smallest = byte; - if (byte > Largest) - Largest = byte; - } - - word = Smallest; - word <<= 8; - word |= Largest; - - return word; -} - -static void mct_PhyController_Config(struct MCTStatStruc *pMCTstat, - struct DCTStatStruc *pDCTstat, u8 dct) -{ - uint8_t index; - uint32_t dword; - u32 index_reg = 0x98; - u32 dev = pDCTstat->dev_dct; - - if (pDCTstat->LogicalCPUID & (AMD_DR_DAC2_OR_C3 | AMD_RB_C3 | AMD_FAM15_ALL)) { - if (is_fam15h()) { - /* Set F2x[1, 0]98_x0D0F0F13 DllDisEarlyU and DllDisEarlyL to save power */ - for (index = 0; index < 0x9; index++) { - dword = Get_NB32_index_wait_DCT(dev, dct, index_reg, 0x0d0f0013 | (index << 8)); - dword |= (0x1 << 1); /* DllDisEarlyU = 1 */ - dword |= 0x1; /* DllDisEarlyL = 1 */ - Set_NB32_index_wait_DCT(dev, dct, index_reg, 0x0d0f0013 | (index << 8), dword); - } - } - - if (pDCTstat->Dimmx4Present == 0) { - /* Set bit7 RxDqsUDllPowerDown to register F2x[1, 0]98_x0D0F0F13 for - * additional power saving when x4 DIMMs are not present. - */ - for (index = 0; index < 0x9; index++) { - dword = Get_NB32_index_wait_DCT(dev, dct, index_reg, 0x0d0f0013 | (index << 8)); - dword |= (0x1 << 7); /* RxDqsUDllPowerDown = 1 */ - Set_NB32_index_wait_DCT(dev, dct, index_reg, 0x0d0f0013 | (index << 8), dword); - } - } - } - - if (pDCTstat->LogicalCPUID & (AMD_DR_DAC2_OR_C3 | AMD_FAM15_ALL)) { - if (pDCTstat->DimmECCPresent == 0) { - /* Set bit4 PwrDn to register F2x[1, 0]98_x0D0F0830 for power saving */ - dword = Get_NB32_index_wait_DCT(dev, dct, index_reg, 0x0d0f0830); - dword |= 1 << 4; /* BIOS should set this bit if ECC DIMMs are not present */ - Set_NB32_index_wait_DCT(dev, dct, index_reg, 0x0d0f0830, dword); - } - } - -} - -static void mct_FinalMCT_D(struct MCTStatStruc *pMCTstat, - struct DCTStatStruc *pDCTstatA) -{ - u8 Node; - struct DCTStatStruc *pDCTstat; - u32 val; - - for (Node = 0; Node < MAX_NODES_SUPPORTED; Node++) { - pDCTstat = pDCTstatA + Node; - - if (pDCTstat->NodePresent) { - mct_PhyController_Config(pMCTstat, pDCTstat, 0); - mct_PhyController_Config(pMCTstat, pDCTstat, 1); - - if (!is_fam15h()) { - /* Family 10h CPUs */ - mct_ExtMCTConfig_Cx(pDCTstat); - mct_ExtMCTConfig_Bx(pDCTstat); - mct_ExtMCTConfig_Dx(pDCTstat); - } else { - /* Family 15h CPUs */ - uint8_t nvram; - uint8_t enable_experimental_memory_speed_boost; - - /* Check to see if cache partitioning is allowed */ - enable_experimental_memory_speed_boost = 0; - if (get_option(&nvram, "experimental_memory_speed_boost") == CB_SUCCESS) - enable_experimental_memory_speed_boost = !!nvram; - - val = 0x0ce00f00; /* FlushWrOnStpGnt = 0x0 */ - val |= 0x10 << 2; /* MctWrLimit = 0x10 */ - val |= 0x1; /* DctWrLimit = 0x1 */ - Set_NB32(pDCTstat->dev_dct, 0x11c, val); - - val = Get_NB32(pDCTstat->dev_dct, 0x1b0); - val &= ~0x3; /* AdapPrefMissRatio = 0x1 */ - val |= 0x1; - val &= ~(0x3 << 2); /* AdapPrefPositiveStep = 0x0 */ - val &= ~(0x3 << 4); /* AdapPrefNegativeStep = 0x0 */ - val &= ~(0x7 << 8); /* CohPrefPrbLmt = 0x1 */ - val |= (0x1 << 8); - val |= (0x1 << 12); /* EnSplitDctLimits = 0x1 */ - if (enable_experimental_memory_speed_boost) - val |= (0x1 << 20); /* DblPrefEn = 0x1 */ - val |= (0x7 << 22); /* PrefFourConf = 0x7 */ - val |= (0x7 << 25); /* PrefFiveConf = 0x7 */ - val &= ~(0xf << 28); /* DcqBwThrotWm = 0x0 */ - Set_NB32(pDCTstat->dev_dct, 0x1b0, val); - - uint8_t wm1; - uint8_t wm2; - - switch (pDCTstat->Speed) { - case 0x4: - wm1 = 0x3; - wm2 = 0x4; - break; - case 0x6: - wm1 = 0x3; - wm2 = 0x5; - break; - case 0xa: - wm1 = 0x4; - wm2 = 0x6; - break; - case 0xe: - wm1 = 0x5; - wm2 = 0x8; - break; - case 0x12: - wm1 = 0x6; - wm2 = 0x9; - break; - default: - wm1 = 0x7; - wm2 = 0xa; - break; - } - - val = Get_NB32(pDCTstat->dev_dct, 0x1b4); - val &= ~(0x3ff); - val |= ((wm2 & 0x1f) << 5); - val |= (wm1 & 0x1f); - Set_NB32(pDCTstat->dev_dct, 0x1b4, val); - } - } - } - - /* ClrClToNB_D postponed until we're done executing from ROM */ - mct_ClrWbEnhWsbDis_D(pMCTstat, pDCTstat); - - /* set F3x8C[DisFastTprWr] on all DR, if L3Size = 0 */ - if (pDCTstat->LogicalCPUID & AMD_DR_ALL) { - if (!(cpuid_edx(0x80000006) & 0xFFFC0000)) { - val = Get_NB32(pDCTstat->dev_nbmisc, 0x8C); - val |= 1 << 24; - Set_NB32(pDCTstat->dev_nbmisc, 0x8C, val); - } - } -} - -void mct_ForceNBPState0_En_Fam15(struct MCTStatStruc *pMCTstat, - struct DCTStatStruc *pDCTstat) -{ - /* Force the NB P-state to P0 */ - uint32_t dword; - uint32_t dword2; - - dword = Get_NB32(pDCTstat->dev_nbctl, 0x174); - if (!(dword & 0x1)) { - dword = Get_NB32(pDCTstat->dev_nbctl, 0x170); - pDCTstat->SwNbPstateLoDis = (dword >> 14) & 0x1; - pDCTstat->NbPstateDisOnP0 = (dword >> 13) & 0x1; - pDCTstat->NbPstateThreshold = (dword >> 9) & 0x7; - pDCTstat->NbPstateHi = (dword >> 6) & 0x3; - dword &= ~(0x1 << 14); /* SwNbPstateLoDis = 0 */ - dword &= ~(0x1 << 13); /* NbPstateDisOnP0 = 0 */ - dword &= ~(0x7 << 9); /* NbPstateThreshold = 0 */ - dword &= ~(0x3 << 3); /* NbPstateLo = NbPstateMaxVal */ - dword |= ((dword & 0x3) << 3); - Set_NB32(pDCTstat->dev_nbctl, 0x170, dword); - - if (!is_model10_1f()) { - /* Wait until CurNbPState == NbPstateLo */ - do { - dword2 = Get_NB32(pDCTstat->dev_nbctl, 0x174); - } while (((dword2 >> 19) & 0x7) != (dword & 0x3)); - } - dword = Get_NB32(pDCTstat->dev_nbctl, 0x170); - dword &= ~(0x3 << 6); /* NbPstateHi = 0 */ - dword |= (0x3 << 14); /* SwNbPstateLoDis = 1 */ - Set_NB32(pDCTstat->dev_nbctl, 0x170, dword); - - if (!is_model10_1f()) { - /* Wait until CurNbPState == 0 */ - do { - dword2 = Get_NB32(pDCTstat->dev_nbctl, 0x174); - } while (((dword2 >> 19) & 0x7) != 0); - } - } -} - -void mct_ForceNBPState0_Dis_Fam15(struct MCTStatStruc *pMCTstat, - struct DCTStatStruc *pDCTstat) -{ - /* Restore normal NB P-state functionailty */ - uint32_t dword; - - dword = Get_NB32(pDCTstat->dev_nbctl, 0x174); - if (!(dword & 0x1)) { - dword = Get_NB32(pDCTstat->dev_nbctl, 0x170); - dword &= ~(0x1 << 14); /* SwNbPstateLoDis*/ - dword |= ((pDCTstat->SwNbPstateLoDis & 0x1) << 14); - dword &= ~(0x1 << 13); /* NbPstateDisOnP0 */ - dword |= ((pDCTstat->NbPstateDisOnP0 & 0x1) << 13); - dword &= ~(0x7 << 9); /* NbPstateThreshold */ - dword |= ((pDCTstat->NbPstateThreshold & 0x7) << 9); - dword &= ~(0x3 << 6); /* NbPstateHi */ - dword |= ((pDCTstat->NbPstateHi & 0x3) << 3); - Set_NB32(pDCTstat->dev_nbctl, 0x170, dword); - } -} - -static void mct_InitialMCT_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstat) -{ - if (is_fam15h()) { - msr_t p0_state_msr; - uint8_t cpu_fid; - uint8_t cpu_did; - uint32_t cpu_divisor; - uint8_t boost_states; - - /* Retrieve the number of boost states */ - boost_states = (Get_NB32(pDCTstat->dev_link, 0x15c) >> 2) & 0x7; - - /* Retrieve and store the TSC frequency (P0 COF) */ - p0_state_msr = rdmsr(PSTATE_0_MSR + boost_states); - cpu_fid = p0_state_msr.lo & 0x3f; - cpu_did = (p0_state_msr.lo >> 6) & 0x7; - cpu_divisor = (0x1 << cpu_did); - pMCTstat->TSCFreq = (100 * (cpu_fid + 0x10)) / cpu_divisor; - - printk(BIOS_DEBUG, "mct_InitialMCT_D: mct_ForceNBPState0_En_Fam15\n"); - mct_ForceNBPState0_En_Fam15(pMCTstat, pDCTstat); - } else { - /* K10 BKDG v3.62 section 2.8.9.2 */ - printk(BIOS_DEBUG, "mct_InitialMCT_D: clear_legacy_Mode\n"); - clear_legacy_Mode(pMCTstat, pDCTstat); - - /* Northbridge configuration */ - mct_SetClToNB_D(pMCTstat, pDCTstat); - mct_SetWbEnhWsbDis_D(pMCTstat, pDCTstat); - } -} - -static u32 mct_NodePresent_D(void) -{ - u32 val; - if (is_fam15h()) { - if (is_model10_1f()) { - val = 0x14001022; - } else { - val = 0x16001022; - } - } else { - val = 0x12001022; - } - return val; -} - -static void mct_init(struct MCTStatStruc *pMCTstat, - struct DCTStatStruc *pDCTstat) -{ - u32 lo, hi; - u32 addr; - - pDCTstat->GangedMode = 0; - pDCTstat->DRPresent = 1; - - /* enable extend PCI configuration access */ - addr = NB_CFG_MSR; - _RDMSR(addr, &lo, &hi); - if (hi & (1 << (46-32))) { - pDCTstat->Status |= 1 << SB_ExtConfig; - } else { - hi |= 1 << (46-32); - _WRMSR(addr, lo, hi); - } -} - -static void clear_legacy_Mode(struct MCTStatStruc *pMCTstat, - struct DCTStatStruc *pDCTstat) -{ - u32 reg; - u32 val; - u32 dev = pDCTstat->dev_dct; - - /* Clear Legacy BIOS Mode bit */ - reg = 0x94; - val = Get_NB32_DCT(dev, 0, reg); - val &= ~(1<dev_map; - - /* Copy dram map from F1x40/44,F1x48/4c, - to F1x120/124(Node0),F1x120/124(Node1),...*/ - for (Node = 0; Node < MAX_NODES_SUPPORTED; Node++) { - pDCTstat = pDCTstatA + Node; - devx = pDCTstat->dev_map; - - /* get base/limit from Node0 */ - reg = 0x40 + (Node << 3); /* Node0/Dram Base 0 */ - val = Get_NB32(dev, reg); - Drambase = val >> (16 + 3); - - reg = 0x44 + (Node << 3); /* Node0/Dram Base 0 */ - val = Get_NB32(dev, reg); - Dramlimit = val >> (16 + 3); - - /* set base/limit to F1x120/124 per Node */ - if (pDCTstat->NodePresent) { - reg = 0x120; /* F1x120,DramBase[47:27] */ - val = Get_NB32(devx, reg); - val &= 0xFFE00000; - val |= Drambase; - Set_NB32(devx, reg, val); - - reg = 0x124; - val = Get_NB32(devx, reg); - val &= 0xFFE00000; - val |= Dramlimit; - Set_NB32(devx, reg, val); - - if (pMCTstat->GStatus & (1 << GSB_HWHole)) { - reg = 0xF0; - val = Get_NB32(devx, reg); - val |= (1 << DramMemHoistValid); - val &= ~(0xFF << 24); - dword = (pMCTstat->HoleBase >> (24 - 8)) & 0xFF; - dword <<= 24; - val |= dword; - Set_NB32(devx, reg, val); - } - - } - } -} - -static void SetCSTriState(struct MCTStatStruc *pMCTstat, - struct DCTStatStruc *pDCTstat, u8 dct) -{ - u32 val; - u32 dev = pDCTstat->dev_dct; - u32 index_reg = 0x98; - u16 word; - - if (is_fam15h()) { - word = fam15h_cs_tristate_enable_code(pDCTstat, dct); - } else { - /* Tri-state unused chipselects when motherboard - termination is available */ - - /* FIXME: skip for Ax */ - - word = pDCTstat->CSPresent; - if (pDCTstat->Status & (1 << SB_Registered)) { - word |= (word & 0x55) << 1; - } - word = (~word) & 0xff; - } - - val = Get_NB32_index_wait_DCT(dev, dct, index_reg, 0x0000000c); - val &= ~0xff; - val |= word; - Set_NB32_index_wait_DCT(dev, dct, index_reg, 0x0000000c, val); -} - -static void SetCKETriState(struct MCTStatStruc *pMCTstat, - struct DCTStatStruc *pDCTstat, u8 dct) -{ - u32 val; - u32 dev; - u32 index_reg = 0x98; - u16 word; - - /* Tri-state unused CKEs when motherboard termination is available */ - - /* FIXME: skip for Ax */ - - dev = pDCTstat->dev_dct; - word = pDCTstat->CSPresent; - - val = Get_NB32_index_wait_DCT(dev, dct, index_reg, 0x0000000c); - val &= ~(0x3 << 12); - if ((word & 0x55) == 0) - val |= 1 << 12; - if ((word & 0xaa) == 0) - val |= 1 << 13; - Set_NB32_index_wait_DCT(dev, dct, index_reg, 0x0000000c, val); -} - -static void SetODTTriState(struct MCTStatStruc *pMCTstat, - struct DCTStatStruc *pDCTstat, u8 dct) -{ - u32 val; - u32 dev; - u32 index_reg = 0x98; - u8 cs; - u8 odt; - - dev = pDCTstat->dev_dct; - - if (is_fam15h()) { - odt = fam15h_odt_tristate_enable_code(pDCTstat, dct); - } else { - /* FIXME: skip for Ax */ - - /* Tri-state unused ODTs when motherboard termination is available */ - odt = 0x0f; /* ODT tri-state setting */ - - if (pDCTstat->Status & (1 <CSPresent & (1 << cs)) { - odt &= ~(1 << (cs / 2)); - if (mctGet_NVbits(NV_4RANKType) != 0) { /* quad-rank capable platform */ - if (pDCTstat->CSPresent & (1 << (cs + 1))) - odt &= ~(4 << (cs / 2)); - } - } - } - } else { /* AM3 package */ - val = ~(pDCTstat->CSPresent); - odt = val & 9; /* swap bits 1 and 2 */ - if (val & (1 << 1)) - odt |= 1 << 2; - if (val & (1 << 2)) - odt |= 1 << 1; - } - } - - val = Get_NB32_index_wait_DCT(dev, dct, index_reg, 0x0000000c); - val &= ~(0xf << 8); /* ODTTri = odt */ - val |= (odt & 0xf) << 8; - Set_NB32_index_wait_DCT(dev, dct, index_reg, 0x0000000c, val); -} - -/* Family 15h */ -static void InitDDRPhy(struct MCTStatStruc *pMCTstat, - struct DCTStatStruc *pDCTstat, u8 dct) -{ - uint8_t index; - uint32_t dword; - uint8_t ddr_voltage_index; - uint8_t amd_voltage_level_index = 0; - uint32_t index_reg = 0x98; - uint32_t dev = pDCTstat->dev_dct; - - printk(BIOS_DEBUG, "%s: Start\n", __func__); - - /* Find current DDR supply voltage for this DCT */ - ddr_voltage_index = dct_ddr_voltage_index(pDCTstat, dct); - - /* Fam15h BKDG v3.14 section 2.10.5.3 - * The remainder of the Phy Initialization algorithm picks up in phyAssistedMemFnceTraining - */ - Set_NB32_index_wait_DCT(dev, dct, index_reg, 0x0000000b, 0x80000000); - Set_NB32_index_wait_DCT(dev, dct, index_reg, 0x0d0fe013, 0x00000118); - - /* Program desired VDDIO level */ - if (ddr_voltage_index & 0x4) { - /* 1.25V */ - amd_voltage_level_index = 0x2; - } else if (ddr_voltage_index & 0x2) { - /* 1.35V */ - amd_voltage_level_index = 0x1; - } else if (ddr_voltage_index & 0x1) { - /* 1.50V */ - amd_voltage_level_index = 0x0; - } - - /* D18F2x9C_x0D0F_0[F,8:0]1F_dct[1:0][RxVioLvl] */ - for (index = 0; index < 0x9; index++) { - dword = Get_NB32_index_wait_DCT(dev, dct, index_reg, 0x0d0f001f | (index << 8)); - dword &= ~(0x3 << 3); - dword |= (amd_voltage_level_index << 3); - Set_NB32_index_wait_DCT(dev, dct, index_reg, 0x0d0f001f | (index << 8), dword); - } - - /* D18F2x9C_x0D0F_[C,8,2][2:0]1F_dct[1:0][RxVioLvl] */ - for (index = 0; index < 0x3; index++) { - dword = Get_NB32_index_wait_DCT(dev, dct, index_reg, 0x0d0f201f | (index << 8)); - dword &= ~(0x3 << 3); - dword |= (amd_voltage_level_index << 3); - Set_NB32_index_wait_DCT(dev, dct, index_reg, 0x0d0f201f | (index << 8), dword); - } - for (index = 0; index < 0x2; index++) { - dword = Get_NB32_index_wait_DCT(dev, dct, index_reg, 0x0d0f801f | (index << 8)); - dword &= ~(0x3 << 3); - dword |= (amd_voltage_level_index << 3); - Set_NB32_index_wait_DCT(dev, dct, index_reg, 0x0d0f801f | (index << 8), dword); - } - for (index = 0; index < 0x1; index++) { - dword = Get_NB32_index_wait_DCT(dev, dct, index_reg, 0x0d0fc01f | (index << 8)); - dword &= ~(0x3 << 3); - dword |= (amd_voltage_level_index << 3); - Set_NB32_index_wait_DCT(dev, dct, index_reg, 0x0d0fc01f | (index << 8), dword); - } - - /* D18F2x9C_x0D0F_4009_dct[1:0][CmpVioLvl, ComparatorAdjust] */ - /* NOTE: CmpVioLvl and ComparatorAdjust only take effect when set on DCT 0 */ - dword = Get_NB32_index_wait_DCT(dev, 0, index_reg, 0x0d0f4009); - dword &= ~(0x0000c00c); - dword |= (amd_voltage_level_index << 14); - dword |= (amd_voltage_level_index << 2); - Set_NB32_index_wait_DCT(dev, 0, index_reg, 0x0d0f4009, dword); - - printk(BIOS_DEBUG, "%s: Done\n", __func__); -} - -void InitPhyCompensation(struct MCTStatStruc *pMCTstat, - struct DCTStatStruc *pDCTstat, u8 dct) -{ - u8 i; - u32 index_reg = 0x98; - u32 dev = pDCTstat->dev_dct; - u32 valx = 0; - uint8_t index; - uint32_t dword; - const u8 *p; - - printk(BIOS_DEBUG, "%s: DCT %d: Start\n", __func__, dct); - - if (is_fam15h()) { - /* Algorithm detailed in the Fam15h BKDG Rev. 3.14 section 2.10.5.3.4 */ - uint32_t tx_pre; - uint32_t drive_strength; - - /* Program D18F2x9C_x0D0F_E003_dct[1:0][DisAutoComp] */ - dword = Get_NB32_index_wait_DCT(dev, dct, index_reg, 0x0d0fe003); - dword |= (0x1 << 14); - Set_NB32_index_wait_DCT(dev, dct, index_reg, 0x0d0fe003, dword); - - /* Program D18F2x9C_x0D0F_E003_dct[1:0][DisablePredriverCal] */ - /* NOTE: DisablePredriverCal only takes effect when set on DCT 0 */ - dword = Get_NB32_index_wait_DCT(dev, 0, index_reg, 0x0d0fe003); - dword |= (0x1 << 13); - Set_NB32_index_wait_DCT(dev, 0, index_reg, 0x0d0fe003, dword); - - /* Determine TxPreP/TxPreN for data lanes (Stage 1) */ - dword = Get_NB32_index_wait_DCT(dev, dct, index_reg, 0x00000000); - drive_strength = (dword >> 20) & 0x7; /* DqsDrvStren */ - tx_pre = fam15h_phy_predriver_calibration_code(pDCTstat, dct, drive_strength); - - /* Program TxPreP/TxPreN for data lanes (Stage 1) */ - for (index = 0; index < 0x9; index++) { - dword = Get_NB32_index_wait_DCT(dev, dct, index_reg, 0x0d0f0006 | (index << 8)); - dword &= ~(0xffff); - dword |= tx_pre; - Set_NB32_index_wait_DCT(dev, dct, index_reg, 0x0d0f0006 | (index << 8), dword); - } - - /* Determine TxPreP/TxPreN for data lanes (Stage 2) */ - dword = Get_NB32_index_wait_DCT(dev, dct, index_reg, 0x00000000); - drive_strength = (dword >> 16) & 0x7; /* DataDrvStren */ - tx_pre = fam15h_phy_predriver_calibration_code(pDCTstat, dct, drive_strength); - - /* Program TxPreP/TxPreN for data lanes (Stage 2) */ - for (index = 0; index < 0x9; index++) { - dword = Get_NB32_index_wait_DCT(dev, dct, index_reg, 0x0d0f000a | (index << 8)); - dword &= ~(0xffff); - dword |= tx_pre; - Set_NB32_index_wait_DCT(dev, dct, index_reg, 0x0d0f000a | (index << 8), dword); - } - for (index = 0; index < 0x9; index++) { - dword = Get_NB32_index_wait_DCT(dev, dct, index_reg, 0x0d0f0002 | (index << 8)); - dword &= ~(0xffff); - dword |= (0x8000 | tx_pre); - Set_NB32_index_wait_DCT(dev, dct, index_reg, 0x0d0f0002 | (index << 8), dword); - } - - /* Determine TxPreP/TxPreN for command/address lines (Stage 1) */ - dword = Get_NB32_index_wait_DCT(dev, dct, index_reg, 0x00000000); - drive_strength = (dword >> 4) & 0x7; /* CsOdtDrvStren */ - tx_pre = fam15h_phy_predriver_cmd_addr_calibration_code(pDCTstat, dct, drive_strength); - - /* Program TxPreP/TxPreN for command/address lines (Stage 1) */ - dword = Get_NB32_index_wait_DCT(dev, dct, index_reg, 0x0d0f8006); - dword &= ~(0xffff); - dword |= tx_pre; - Set_NB32_index_wait_DCT(dev, dct, index_reg, 0x0d0f8006, dword); - dword = Get_NB32_index_wait_DCT(dev, dct, index_reg, 0x0d0f800a); - dword &= ~(0xffff); - dword |= tx_pre; - Set_NB32_index_wait_DCT(dev, dct, index_reg, 0x0d0f800a, dword); - dword = Get_NB32_index_wait_DCT(dev, dct, index_reg, 0x0d0f8002); - dword &= ~(0xffff); - dword |= (0x8000 | tx_pre); - Set_NB32_index_wait_DCT(dev, dct, index_reg, 0x0d0f8002, dword); - - /* Determine TxPreP/TxPreN for command/address lines (Stage 2) */ - dword = Get_NB32_index_wait_DCT(dev, dct, index_reg, 0x00000000); - drive_strength = (dword >> 8) & 0x7; /* AddrCmdDrvStren */ - tx_pre = fam15h_phy_predriver_cmd_addr_calibration_code(pDCTstat, dct, drive_strength); - - /* Program TxPreP/TxPreN for command/address lines (Stage 2) */ - dword = Get_NB32_index_wait_DCT(dev, dct, index_reg, 0x0d0f8106); - dword &= ~(0xffff); - dword |= tx_pre; - Set_NB32_index_wait_DCT(dev, dct, index_reg, 0x0d0f8106, dword); - dword = Get_NB32_index_wait_DCT(dev, dct, index_reg, 0x0d0f810a); - dword &= ~(0xffff); - dword |= tx_pre; - Set_NB32_index_wait_DCT(dev, dct, index_reg, 0x0d0f810a, dword); - dword = Get_NB32_index_wait_DCT(dev, dct, index_reg, 0x0d0fc006); - dword &= ~(0xffff); - dword |= tx_pre; - Set_NB32_index_wait_DCT(dev, dct, index_reg, 0x0d0fc006, dword); - dword = Get_NB32_index_wait_DCT(dev, dct, index_reg, 0x0d0fc00a); - dword &= ~(0xffff); - dword |= tx_pre; - Set_NB32_index_wait_DCT(dev, dct, index_reg, 0x0d0fc00a, dword); - dword = Get_NB32_index_wait_DCT(dev, dct, index_reg, 0x0d0fc00e); - dword &= ~(0xffff); - dword |= tx_pre; - Set_NB32_index_wait_DCT(dev, dct, index_reg, 0x0d0fc00e, dword); - dword = Get_NB32_index_wait_DCT(dev, dct, index_reg, 0x0d0fc012); - dword &= ~(0xffff); - dword |= tx_pre; - Set_NB32_index_wait_DCT(dev, dct, index_reg, 0x0d0fc012, dword); - dword = Get_NB32_index_wait_DCT(dev, dct, index_reg, 0x0d0f8102); - dword &= ~(0xffff); - dword |= (0x8000 | tx_pre); - Set_NB32_index_wait_DCT(dev, dct, index_reg, 0x0d0f8102, dword); - - /* Determine TxPreP/TxPreN for command/address lines (Stage 3) */ - dword = Get_NB32_index_wait_DCT(dev, dct, index_reg, 0x00000000); - drive_strength = (dword >> 0) & 0x7; /* CkeDrvStren */ - tx_pre = fam15h_phy_predriver_cmd_addr_calibration_code(pDCTstat, dct, drive_strength); - - /* Program TxPreP/TxPreN for command/address lines (Stage 3) */ - dword = Get_NB32_index_wait_DCT(dev, dct, index_reg, 0x0d0fc002); - dword &= ~(0xffff); - dword |= (0x8000 | tx_pre); - Set_NB32_index_wait_DCT(dev, dct, index_reg, 0x0d0fc002, dword); - - /* Determine TxPreP/TxPreN for clock lines */ - dword = Get_NB32_index_wait_DCT(dev, dct, index_reg, 0x00000000); - drive_strength = (dword >> 12) & 0x7; /* ClkDrvStren */ - tx_pre = fam15h_phy_predriver_clk_calibration_code(pDCTstat, dct, drive_strength); - - /* Program TxPreP/TxPreN for clock lines */ - dword = Get_NB32_index_wait_DCT(dev, dct, index_reg, 0x0d0f2002); - dword &= ~(0xffff); - dword |= (0x8000 | tx_pre); - Set_NB32_index_wait_DCT(dev, dct, index_reg, 0x0d0f2002, dword); - dword = Get_NB32_index_wait_DCT(dev, dct, index_reg, 0x0d0f2102); - dword &= ~(0xffff); - dword |= (0x8000 | tx_pre); - Set_NB32_index_wait_DCT(dev, dct, index_reg, 0x0d0f2102, dword); - dword = Get_NB32_index_wait_DCT(dev, dct, index_reg, 0x0d0f2202); - dword &= ~(0xffff); - dword |= (0x8000 | tx_pre); - Set_NB32_index_wait_DCT(dev, dct, index_reg, 0x0d0f2202, dword); - - if (!is_model10_1f()) { - /* Be extra safe and wait for the predriver calibration - * to be applied to the hardware. The BKDG does not - * require this, but it does take some time for the - * data to propagate, so it's probably a good idea. - */ - uint8_t predriver_cal_pending = 1; - printk(BIOS_DEBUG, "Waiting for predriver calibration to be applied..."); - while (predriver_cal_pending) { - predriver_cal_pending = 0; - for (index = 0; index < 0x9; index++) { - if (Get_NB32_index_wait_DCT(dev, dct, index_reg, 0x0d0f0002 | (index << 8)) & 0x8000) - predriver_cal_pending = 1; - } - } - printk(BIOS_DEBUG, "done!\n"); - } - } else { - dword = Get_NB32_index_wait_DCT(dev, dct, index_reg, 0x00); - dword = 0; - for (i = 0; i < 6; i++) { - switch (i) { - case 0: - case 4: - p = Table_Comp_Rise_Slew_15x; - valx = p[(dword >> 16) & 3]; - break; - case 1: - case 5: - p = Table_Comp_Fall_Slew_15x; - valx = p[(dword >> 16) & 3]; - break; - case 2: - p = Table_Comp_Rise_Slew_20x; - valx = p[(dword >> 8) & 3]; - break; - case 3: - p = Table_Comp_Fall_Slew_20x; - valx = p[(dword >> 8) & 3]; - break; - } - dword |= valx << (5 * i); - } - - Set_NB32_index_wait_DCT(dev, dct, index_reg, 0x0a, dword); - } - - printk(BIOS_DEBUG, "%s: DCT %d: Done\n", __func__, dct); -} - -static void mct_EarlyArbEn_D(struct MCTStatStruc *pMCTstat, - struct DCTStatStruc *pDCTstat, u8 dct) -{ - printk(BIOS_DEBUG, "%s: Start\n", __func__); - - if (!is_fam15h()) { - u32 reg; - u32 val; - u32 dev = pDCTstat->dev_dct; - - /* GhEnhancement #18429 modified by askar: For low NB CLK : - * Memclk ratio, the DCT may need to arbitrate early to avoid - * unnecessary bubbles. - * bit 19 of F2x[1,0]78 Dram Control Register, set this bit only when - * NB CLK : Memclk ratio is between 3:1 (inclusive) to 4:5 (inclusive) - */ - reg = 0x78; - val = Get_NB32_DCT(dev, dct, reg); - - if (pDCTstat->LogicalCPUID & (AMD_DR_Cx | AMD_DR_Dx)) - val |= (1 << EarlyArbEn); - else if (CheckNBCOFEarlyArbEn(pMCTstat, pDCTstat)) - val |= (1 << EarlyArbEn); - - Set_NB32_DCT(dev, dct, reg, val); - } - - printk(BIOS_DEBUG, "%s: Done\n", __func__); -} - -static u8 CheckNBCOFEarlyArbEn(struct MCTStatStruc *pMCTstat, - struct DCTStatStruc *pDCTstat) -{ - u32 reg; - u32 val; - u32 tmp; - u32 rem; - u32 dev = pDCTstat->dev_dct; - u32 hi, lo; - u8 NbDid = 0; - - /* Check if NB COF >= 4*Memclk, if it is not, return a fatal error - */ - - /* 3*(Fn2xD4[NBFid]+4)/(2^NbDid)/(3+Fn2x94[MemClkFreq]) */ - _RDMSR(MSR_COFVID_STS, &lo, &hi); - if (lo & (1 << 22)) - NbDid |= 1; - - reg = 0x94; - val = Get_NB32_DCT(dev, 0, reg); - if (!(val & (1 << MemClkFreqVal))) - val = Get_NB32_DCT(dev, 1, reg); /* get the DCT1 value */ - - val &= 0x07; - val += 3; - if (NbDid) - val <<= 1; - tmp = val; - - dev = pDCTstat->dev_nbmisc; - reg = 0xD4; - val = Get_NB32(dev, reg); - val &= 0x1F; - val += 3; - val *= 3; - val = val / tmp; - rem = val % tmp; - tmp >>= 1; - - /* Yes this could be nicer but this was how the asm was.... */ - if (val < 3) { /* NClk:MemClk < 3:1 */ - return 0; - } else if (val > 4) { /* NClk:MemClk >= 5:1 */ - return 0; - } else if ((val == 4) && (rem > tmp)) { /* NClk:MemClk > 4.5:1 */ - return 0; - } else { - return 1; /* 3:1 <= NClk:MemClk <= 4.5:1*/ - } -} - -static void mct_ResetDataStruct_D(struct MCTStatStruc *pMCTstat, - struct DCTStatStruc *pDCTstatA) -{ - uint8_t Node; - struct DCTStatStruc *pDCTstat; - - /* Initialize Data structures by clearing all entries to 0 */ - memset(pMCTstat, 0, sizeof(*pMCTstat)); - - for (Node = 0; Node < 8; Node++) { - pDCTstat = pDCTstatA + Node; - memset(pDCTstat, 0, sizeof(*pDCTstat) - sizeof(pDCTstat->persistentData)); - } -} - -static void mct_BeforeDramInit_Prod_D(struct MCTStatStruc *pMCTstat, - struct DCTStatStruc *pDCTstat, u8 dct) -{ - printk(BIOS_DEBUG, "%s: Start\n", __func__); - - mct_ProgramODT_D(pMCTstat, pDCTstat, dct); - - printk(BIOS_DEBUG, "%s: Done\n", __func__); -} - -static void mct_ProgramODT_D(struct MCTStatStruc *pMCTstat, - struct DCTStatStruc *pDCTstat, u8 dct) -{ - u8 i; - u32 dword; - u32 dev = pDCTstat->dev_dct; - - printk(BIOS_DEBUG, "%s: Start\n", __func__); - - uint8_t MaxDimmsInstallable = mctGet_NVbits(NV_MAX_DIMMS_PER_CH); - - if (is_fam15h()) { - /* Obtain number of DIMMs on channel */ - uint8_t dimm_count = pDCTstat->MAdimms[dct]; - uint8_t rank_count_dimm0; - uint8_t rank_count_dimm1; - uint32_t odt_pattern_0; - uint32_t odt_pattern_1; - uint32_t odt_pattern_2; - uint32_t odt_pattern_3; - uint8_t write_odt_duration; - uint8_t read_odt_duration; - uint8_t write_odt_delay; - uint8_t read_odt_delay; - - /* NOTE - * Rank count per DIMM and DCT is encoded by pDCTstat->DimmRanks[( * 2) + dct] - */ - - /* Select appropriate ODT pattern for installed DIMMs - * Refer to the Fam15h BKDG Rev. 3.14, page 149 onwards - */ - if (pDCTstat->Status & (1 << SB_Registered)) { - if (MaxDimmsInstallable == 2) { - if (dimm_count == 1) { - /* 1 DIMM detected */ - rank_count_dimm1 = pDCTstat->DimmRanks[(1 * 2) + dct]; - if (rank_count_dimm1 == 1) { - odt_pattern_0 = 0x00000000; - odt_pattern_1 = 0x00000000; - odt_pattern_2 = 0x00000000; - odt_pattern_3 = 0x00020000; - } else if (rank_count_dimm1 == 2) { - odt_pattern_0 = 0x00000000; - odt_pattern_1 = 0x00000000; - odt_pattern_2 = 0x00000000; - odt_pattern_3 = 0x08020000; - } else if (rank_count_dimm1 == 4) { - odt_pattern_0 = 0x00000000; - odt_pattern_1 = 0x00000000; - odt_pattern_2 = 0x020a0000; - odt_pattern_3 = 0x080a0000; - } else { - /* Fallback */ - odt_pattern_0 = 0x00000000; - odt_pattern_1 = 0x00000000; - odt_pattern_2 = 0x00000000; - odt_pattern_3 = 0x08020000; - } - } else { - /* 2 DIMMs detected */ - rank_count_dimm0 = pDCTstat->DimmRanks[(0 * 2) + dct]; - rank_count_dimm1 = pDCTstat->DimmRanks[(1 * 2) + dct]; - if ((rank_count_dimm0 < 4) && (rank_count_dimm1 < 4)) { - odt_pattern_0 = 0x00000000; - odt_pattern_1 = 0x01010202; - odt_pattern_2 = 0x00000000; - odt_pattern_3 = 0x09030603; - } else if ((rank_count_dimm0 < 4) && (rank_count_dimm1 == 4)) { - odt_pattern_0 = 0x01010000; - odt_pattern_1 = 0x01010a0a; - odt_pattern_2 = 0x01090000; - odt_pattern_3 = 0x01030e0b; - } else if ((rank_count_dimm0 == 4) && (rank_count_dimm1 < 4)) { - odt_pattern_0 = 0x00000202; - odt_pattern_1 = 0x05050202; - odt_pattern_2 = 0x00000206; - odt_pattern_3 = 0x0d070203; - } else if ((rank_count_dimm0 == 4) && (rank_count_dimm1 == 4)) { - odt_pattern_0 = 0x05050a0a; - odt_pattern_1 = 0x05050a0a; - odt_pattern_2 = 0x050d0a0e; - odt_pattern_3 = 0x05070a0b; - } else { - /* Fallback */ - odt_pattern_0 = 0x00000000; - odt_pattern_1 = 0x00000000; - odt_pattern_2 = 0x00000000; - odt_pattern_3 = 0x00000000; - } - } - } else { - /* FIXME - * 3 DIMMs per channel UNIMPLEMENTED - */ - odt_pattern_0 = 0x00000000; - odt_pattern_1 = 0x00000000; - odt_pattern_2 = 0x00000000; - odt_pattern_3 = 0x00000000; - } - } else if (pDCTstat->Status & (1 << SB_LoadReduced)) { - /* TODO - * Load reduced dimms UNIMPLEMENTED - */ - odt_pattern_0 = 0x00000000; - odt_pattern_1 = 0x00000000; - odt_pattern_2 = 0x00000000; - odt_pattern_3 = 0x00000000; - } else { - if (MaxDimmsInstallable == 2) { - if (dimm_count == 1) { - /* 1 DIMM detected */ - rank_count_dimm1 = pDCTstat->DimmRanks[(1 * 2) + dct]; - if (rank_count_dimm1 == 1) { - odt_pattern_0 = 0x00000000; - odt_pattern_1 = 0x00000000; - odt_pattern_2 = 0x00000000; - odt_pattern_3 = 0x00020000; - } else if (rank_count_dimm1 == 2) { - odt_pattern_0 = 0x00000000; - odt_pattern_1 = 0x00000000; - odt_pattern_2 = 0x00000000; - odt_pattern_3 = 0x08020000; - } else { - /* Fallback */ - odt_pattern_0 = 0x00000000; - odt_pattern_1 = 0x00000000; - odt_pattern_2 = 0x00000000; - odt_pattern_3 = 0x08020000; - } - } else { - /* 2 DIMMs detected */ - odt_pattern_0 = 0x00000000; - odt_pattern_1 = 0x01010202; - odt_pattern_2 = 0x00000000; - odt_pattern_3 = 0x09030603; - } - } else { - /* FIXME - * 3 DIMMs per channel UNIMPLEMENTED - */ - odt_pattern_0 = 0x00000000; - odt_pattern_1 = 0x00000000; - odt_pattern_2 = 0x00000000; - odt_pattern_3 = 0x00000000; - } - } - - if (pDCTstat->Status & (1 << SB_LoadReduced)) { - /* TODO - * Load reduced dimms UNIMPLEMENTED - */ - write_odt_duration = 0x0; - read_odt_duration = 0x0; - write_odt_delay = 0x0; - read_odt_delay = 0x0; - } else { - uint8_t tcl; - uint8_t tcwl; - tcl = Get_NB32_DCT(dev, dct, 0x200) & 0x1f; - tcwl = Get_NB32_DCT(dev, dct, 0x20c) & 0x1f; - - write_odt_duration = 0x6; - read_odt_duration = 0x6; - write_odt_delay = 0x0; - if (tcl > tcwl) - read_odt_delay = tcl - tcwl; - else - read_odt_delay = 0x0; - } - - /* Program ODT pattern */ - Set_NB32_DCT(dev, dct, 0x230, odt_pattern_1); - Set_NB32_DCT(dev, dct, 0x234, odt_pattern_0); - Set_NB32_DCT(dev, dct, 0x238, odt_pattern_3); - Set_NB32_DCT(dev, dct, 0x23c, odt_pattern_2); - dword = Get_NB32_DCT(dev, dct, 0x240); - dword &= ~(0x7 << 12); /* WrOdtOnDuration = write_odt_duration */ - dword |= (write_odt_duration & 0x7) << 12; - dword &= ~(0x7 << 8); /* WrOdtTrnOnDly = write_odt_delay */ - dword |= (write_odt_delay & 0x7) << 8; - dword &= ~(0xf << 4); /* RdOdtOnDuration = read_odt_duration */ - dword |= (read_odt_duration & 0xf) << 4; - dword &= ~(0xf); /* RdOdtTrnOnDly = read_odt_delay */ - dword |= (read_odt_delay & 0xf); - Set_NB32_DCT(dev, dct, 0x240, dword); - - printk(BIOS_SPEW, "Programmed DCT %d ODT pattern %08x %08x %08x %08x\n", dct, odt_pattern_0, odt_pattern_1, odt_pattern_2, odt_pattern_3); - } else if (pDCTstat->LogicalCPUID & AMD_DR_Dx) { - if (pDCTstat->Speed == 3) - dword = 0x00000800; - else - dword = 0x00000000; - for (i = 0; i < 2; i++) { - Set_NB32_DCT(dev, i, 0x98, 0x0D000030); - Set_NB32_DCT(dev, i, 0x9C, dword); - Set_NB32_DCT(dev, i, 0x98, 0x4D040F30); - - /* Obtain number of DIMMs on channel */ - uint8_t dimm_count = pDCTstat->MAdimms[i]; - uint8_t rank_count_dimm0; - uint8_t rank_count_dimm1; - uint32_t odt_pattern_0; - uint32_t odt_pattern_1; - uint32_t odt_pattern_2; - uint32_t odt_pattern_3; - - /* Select appropriate ODT pattern for installed DIMMs - * Refer to the Fam10h BKDG Rev. 3.62, page 120 onwards - */ - if (pDCTstat->Status & (1 << SB_Registered)) { - if (MaxDimmsInstallable == 2) { - if (dimm_count == 1) { - /* 1 DIMM detected */ - rank_count_dimm1 = pDCTstat->DimmRanks[(1 * 2) + i]; - if (rank_count_dimm1 == 1) { - odt_pattern_0 = 0x00000000; - odt_pattern_1 = 0x00000000; - odt_pattern_2 = 0x00000000; - odt_pattern_3 = 0x00020000; - } else if (rank_count_dimm1 == 2) { - odt_pattern_0 = 0x00000000; - odt_pattern_1 = 0x00000000; - odt_pattern_2 = 0x00000000; - odt_pattern_3 = 0x02080000; - } else if (rank_count_dimm1 == 4) { - odt_pattern_0 = 0x00000000; - odt_pattern_1 = 0x00000000; - odt_pattern_2 = 0x020a0000; - odt_pattern_3 = 0x080a0000; - } else { - /* Fallback */ - odt_pattern_0 = 0x00000000; - odt_pattern_1 = 0x00000000; - odt_pattern_2 = 0x00000000; - odt_pattern_3 = 0x00000000; - } - } else { - /* 2 DIMMs detected */ - rank_count_dimm0 = pDCTstat->DimmRanks[(0 * 2) + i]; - rank_count_dimm1 = pDCTstat->DimmRanks[(1 * 2) + i]; - if ((rank_count_dimm0 < 4) && (rank_count_dimm1 < 4)) { - odt_pattern_0 = 0x00000000; - odt_pattern_1 = 0x01010202; - odt_pattern_2 = 0x00000000; - odt_pattern_3 = 0x09030603; - } else if ((rank_count_dimm0 < 4) && (rank_count_dimm1 == 4)) { - odt_pattern_0 = 0x01010000; - odt_pattern_1 = 0x01010a0a; - odt_pattern_2 = 0x01090000; - odt_pattern_3 = 0x01030e0b; - } else if ((rank_count_dimm0 == 4) && (rank_count_dimm1 < 4)) { - odt_pattern_0 = 0x00000202; - odt_pattern_1 = 0x05050202; - odt_pattern_2 = 0x00000206; - odt_pattern_3 = 0x0d070203; - } else if ((rank_count_dimm0 == 4) && (rank_count_dimm1 == 4)) { - odt_pattern_0 = 0x05050a0a; - odt_pattern_1 = 0x05050a0a; - odt_pattern_2 = 0x050d0a0e; - odt_pattern_3 = 0x05070a0b; - } else { - /* Fallback */ - odt_pattern_0 = 0x00000000; - odt_pattern_1 = 0x00000000; - odt_pattern_2 = 0x00000000; - odt_pattern_3 = 0x00000000; - } - } - } else { - /* FIXME - * 3 DIMMs per channel UNIMPLEMENTED - */ - odt_pattern_0 = 0x00000000; - odt_pattern_1 = 0x00000000; - odt_pattern_2 = 0x00000000; - odt_pattern_3 = 0x00000000; - } - } else { - if (MaxDimmsInstallable == 2) { - if (dimm_count == 1) { - /* 1 DIMM detected */ - rank_count_dimm1 = pDCTstat->DimmRanks[(1 * 2) + i]; - if (rank_count_dimm1 == 1) { - odt_pattern_0 = 0x00000000; - odt_pattern_1 = 0x00000000; - odt_pattern_2 = 0x00000000; - odt_pattern_3 = 0x00020000; - } else if (rank_count_dimm1 == 2) { - odt_pattern_0 = 0x00000000; - odt_pattern_1 = 0x00000000; - odt_pattern_2 = 0x00000000; - odt_pattern_3 = 0x02080000; - } else { - /* Fallback */ - odt_pattern_0 = 0x00000000; - odt_pattern_1 = 0x00000000; - odt_pattern_2 = 0x00000000; - odt_pattern_3 = 0x00000000; - } - } else { - /* 2 DIMMs detected */ - odt_pattern_0 = 0x00000000; - odt_pattern_1 = 0x01010202; - odt_pattern_2 = 0x00000000; - odt_pattern_3 = 0x09030603; - } - } else { - /* FIXME - * 3 DIMMs per channel UNIMPLEMENTED - */ - odt_pattern_0 = 0x00000000; - odt_pattern_1 = 0x00000000; - odt_pattern_2 = 0x00000000; - odt_pattern_3 = 0x00000000; - } - } - - /* Program ODT pattern */ - Set_NB32_index_wait_DCT(dev, i, 0xf0, 0x180, odt_pattern_1); - Set_NB32_index_wait_DCT(dev, i, 0xf0, 0x181, odt_pattern_0); - Set_NB32_index_wait_DCT(dev, i, 0xf0, 0x182, odt_pattern_3); - Set_NB32_index_wait_DCT(dev, i, 0xf0, 0x183, odt_pattern_2); - - printk(BIOS_SPEW, "Programmed ODT pattern %08x %08x %08x %08x\n", odt_pattern_0, odt_pattern_1, odt_pattern_2, odt_pattern_3); - } - } - - printk(BIOS_DEBUG, "%s: Done\n", __func__); -} - -static void mct_EnDllShutdownSR(struct MCTStatStruc *pMCTstat, - struct DCTStatStruc *pDCTstat, u8 dct) -{ - u32 dev = pDCTstat->dev_dct, val; - - /* Write 0000_07D0h to register F2x[1, 0]98_x4D0FE006 */ - if (pDCTstat->LogicalCPUID & (AMD_DR_DAC2_OR_C3)) { - Set_NB32_DCT(dev, dct, 0x9C, 0x1C); - Set_NB32_DCT(dev, dct, 0x98, 0x4D0FE006); - Set_NB32_DCT(dev, dct, 0x9C, 0x13D); - Set_NB32_DCT(dev, dct, 0x98, 0x4D0FE007); - - val = Get_NB32_DCT(dev, dct, 0x90); - val &= ~(1 << 27/* DisDllShutdownSR */); - Set_NB32_DCT(dev, dct, 0x90, val); - } -} - -static u32 mct_DisDllShutdownSR(struct MCTStatStruc *pMCTstat, - struct DCTStatStruc *pDCTstat, u32 DramConfigLo, u8 dct) -{ - u32 dev = pDCTstat->dev_dct; - - /* Write 0000_07D0h to register F2x[1, 0]98_x4D0FE006 */ - if (pDCTstat->LogicalCPUID & (AMD_DR_DAC2_OR_C3)) { - Set_NB32_DCT(dev, dct, 0x9C, 0x7D0); - Set_NB32_DCT(dev, dct, 0x98, 0x4D0FE006); - Set_NB32_DCT(dev, dct, 0x9C, 0x190); - Set_NB32_DCT(dev, dct, 0x98, 0x4D0FE007); - - DramConfigLo |= /* DisDllShutdownSR */ 1 << 27; - } - - return DramConfigLo; -} - -void mct_SetClToNB_D(struct MCTStatStruc *pMCTstat, - struct DCTStatStruc *pDCTstat) -{ - u32 lo, hi; - u32 msr; - - /* FIXME: Maybe check the CPUID? - not for now. */ - /* pDCTstat->LogicalCPUID; */ - - msr = BU_CFG2_MSR; - _RDMSR(msr, &lo, &hi); - lo |= 1 << ClLinesToNbDis; - _WRMSR(msr, lo, hi); -} - -void mct_ClrClToNB_D(struct MCTStatStruc *pMCTstat, - struct DCTStatStruc *pDCTstat) -{ - - u32 lo, hi; - u32 msr; - - /* FIXME: Maybe check the CPUID? - not for now. */ - /* pDCTstat->LogicalCPUID; */ - - msr = BU_CFG2_MSR; - _RDMSR(msr, &lo, &hi); - if (!pDCTstat->ClToNB_flag) - lo &= ~(1<LogicalCPUID; */ - - msr = BU_CFG_MSR; - _RDMSR(msr, &lo, &hi); - hi |= (1 << WbEnhWsbDis_D); - _WRMSR(msr, lo, hi); -} - -void mct_ClrWbEnhWsbDis_D(struct MCTStatStruc *pMCTstat, - struct DCTStatStruc *pDCTstat) -{ - u32 lo, hi; - u32 msr; - - /* FIXME: Maybe check the CPUID? - not for now. */ - /* pDCTstat->LogicalCPUID; */ - - msr = BU_CFG_MSR; - _RDMSR(msr, &lo, &hi); - hi &= ~(1 << WbEnhWsbDis_D); - _WRMSR(msr, lo, hi); -} - -void ProgDramMRSReg_D(struct MCTStatStruc *pMCTstat, - struct DCTStatStruc *pDCTstat, u8 dct) -{ - u32 DramMRS, dword; - u8 byte; - - DramMRS = 0; - - /* Set chip select CKE control mode */ - if (mctGet_NVbits(NV_CKE_CTL)) { - if (pDCTstat->CSPresent == 3) { - u16 word; - word = pDCTstat->DIMMSPDCSE; - if (dct == 0) - word &= 0b01010100; - else - word &= 0b10101000; - if (word == 0) - DramMRS |= 1 << 23; - } - } - - if (is_fam15h()) { - DramMRS |= (0x1 << 23); /* PchgPDModeSel = 1 */ - } else { - /* - DRAM MRS Register - DrvImpCtrl: drive impedance control.01b(34 ohm driver; Ron34 = Rzq/7) - */ - DramMRS |= 1 << 2; - /* Dram nominal termination: */ - byte = pDCTstat->MAdimms[dct]; - if (!(pDCTstat->Status & (1 << SB_Registered))) { - DramMRS |= 1 << 7; /* 60 ohms */ - if (byte & 2) { - if (pDCTstat->Speed < 6) - DramMRS |= 1 << 8; /* 40 ohms */ - else - DramMRS |= 1 << 9; /* 30 ohms */ - } - } - /* Dram dynamic termination: Disable(1DIMM), 120ohm(>=2DIMM) */ - if (!(pDCTstat->Status & (1 << SB_Registered))) { - if (byte >= 2) { - if (pDCTstat->Speed == 7) - DramMRS |= 1 << 10; - else - DramMRS |= 1 << 11; - } - } else { - DramMRS |= mct_DramTermDyn_RDimm(pMCTstat, pDCTstat, byte); - } - - /* Qoff = 0, output buffers enabled */ - /* Tcwl */ - DramMRS |= (pDCTstat->Speed - 4) << 20; - /* ASR = 1, auto self refresh */ - /* SRT = 0 */ - DramMRS |= 1 << 18; - } - - /* burst length control */ - if (pDCTstat->Status & (1 << SB_128bitmode)) - DramMRS |= 1 << 1; - - dword = Get_NB32_DCT(pDCTstat->dev_dct, dct, 0x84); - if (is_fam15h()) { - dword &= ~0x00800003; - dword |= DramMRS; - } else { - dword &= ~0x00fc2f8f; - dword |= DramMRS; - } - Set_NB32_DCT(pDCTstat->dev_dct, dct, 0x84, dword); -} - -void mct_SetDramConfigHi_D(struct MCTStatStruc *pMCTstat, - struct DCTStatStruc *pDCTstat, u32 dct, u32 DramConfigHi) -{ - /* Bug#15114: Comp. update interrupted by Freq. change can cause - * subsequent update to be invalid during any MemClk frequency change: - * Solution: From the bug report: - * 1. A software-initiated frequency change should be wrapped into the - * following sequence : - * a) Disable Compensation (F2[1, 0]9C_x08[30]) - * b) Reset the Begin Compensation bit (D3CMP->COMP_CONFIG[0]) in - * all the compensation engines - * c) Do frequency change - * d) Enable Compensation (F2[1, 0]9C_x08[30]) - * 2. A software-initiated Disable Compensation should always be - * followed by step b) of the above steps. - * Silicon Status: Fixed In Rev B0 - * - * Errata#177: DRAM Phy Automatic Compensation Updates May Be Invalid - * Solution: BIOS should disable the phy automatic compensation prior - * to initiating a memory clock frequency change as follows: - * 1. Disable PhyAutoComp by writing 1'b1 to F2x[1, 0]9C_x08[30] - * 2. Reset the Begin Compensation bits by writing 32'h0 to - * F2x[1, 0]9C_x4D004F00 - * 3. Perform frequency change - * 4. Enable PhyAutoComp by writing 1'b0 to F2x[1, 0]9C_08[30] - * In addition, any time software disables the automatic phy - * compensation it should reset the begin compensation bit per step 2. - * Silicon Status: Fixed in DR-B0 - */ - - u32 dev = pDCTstat->dev_dct; - u32 index_reg = 0x98; - u32 index; - - uint32_t dword; - - printk(BIOS_DEBUG, "%s: Start\n", __func__); - - if (is_fam15h()) { - /* Initial setup for frequency change - * 9C_x0000_0004 must be configured before MemClkFreqVal is set - */ - - /* Program D18F2x9C_x0D0F_E006_dct[1:0][PllLockTime] = 0x190 */ - dword = Get_NB32_index_wait_DCT(pDCTstat->dev_dct, dct, index_reg, 0x0d0fe006); - dword &= ~(0x0000ffff); - dword |= 0x00000190; - Set_NB32_index_wait_DCT(pDCTstat->dev_dct, dct, index_reg, 0x0d0fe006, dword); - - dword = Get_NB32_DCT(dev, dct, 0x94); - dword &= ~(1 << MemClkFreqVal); - Set_NB32_DCT(dev, dct, 0x94, dword); - - dword = DramConfigHi; - dword &= ~(1 << MemClkFreqVal); - Set_NB32_DCT(dev, dct, 0x94, dword); - - mctGet_PS_Cfg_D(pMCTstat, pDCTstat, dct); - set_2t_configuration(pMCTstat, pDCTstat, dct); - mct_BeforePlatformSpec(pMCTstat, pDCTstat, dct); - mct_PlatformSpec(pMCTstat, pDCTstat, dct); - } else { - index = 0x08; - dword = Get_NB32_index_wait_DCT(dev, dct, index_reg, index); - if (!(dword & (1 << DisAutoComp))) - Set_NB32_index_wait_DCT(dev, dct, index_reg, index, dword | (1 << DisAutoComp)); - - mct_Wait(100); - } - - printk(BIOS_DEBUG, "mct_SetDramConfigHi_D: DramConfigHi: %08x\n", DramConfigHi); - - /* Program the DRAM Configuration High register */ - Set_NB32_DCT(dev, dct, 0x94, DramConfigHi); - - if (is_fam15h()) { - /* Wait until F2x[1, 0]94[FreqChgInProg]=0. */ - do { - printk(BIOS_DEBUG, "*"); - dword = Get_NB32_DCT(pDCTstat->dev_dct, dct, 0x94); - } while (dword & (1 << FreqChgInProg)); - printk(BIOS_DEBUG, "\n"); - - /* Program D18F2x9C_x0D0F_E006_dct[1:0][PllLockTime] = 0xf */ - dword = Get_NB32_index_wait_DCT(pDCTstat->dev_dct, dct, index_reg, 0x0d0fe006); - dword &= ~(0x0000ffff); - dword |= 0x0000000f; - Set_NB32_index_wait_DCT(pDCTstat->dev_dct, dct, index_reg, 0x0d0fe006, dword); - } - - /* Clear MC4 error status */ - pci_write_config32(pDCTstat->dev_nbmisc, 0x48, 0x0); - pci_write_config32(pDCTstat->dev_nbmisc, 0x4c, 0x0); - - printk(BIOS_DEBUG, "%s: Done\n", __func__); -} - -static void mct_BeforeDQSTrain_D(struct MCTStatStruc *pMCTstat, - struct DCTStatStruc *pDCTstatA) -{ - if (!is_fam15h()) { - u8 Node; - struct DCTStatStruc *pDCTstat; - - /* Errata 178 - * - * Bug#15115: Uncertainty In The Sync Chain Leads To Setup Violations - * In TX FIFO - * Solution: BIOS should program DRAM Control Register[RdPtrInit] = - * 5h, (F2x[1, 0]78[3:0] = 5h). - * Silicon Status: Fixed In Rev B0 - * - * Bug#15880: Determine validity of reset settings for DDR PHY timing. - * Solution: At least, set WrDqs fine delay to be 0 for DDR3 training. - */ - for (Node = 0; Node < 8; Node++) { - pDCTstat = pDCTstatA + Node; - - if (pDCTstat->NodePresent) { - mct_BeforeDQSTrainSamp(pDCTstat); /* only Bx */ - mct_ResetDLL_D(pMCTstat, pDCTstat, 0); - mct_ResetDLL_D(pMCTstat, pDCTstat, 1); - } - } - } -} - -/* Erratum 350 */ -static void mct_ResetDLL_D(struct MCTStatStruc *pMCTstat, - struct DCTStatStruc *pDCTstat, u8 dct) -{ - u8 Receiver; - u32 dev = pDCTstat->dev_dct; - u32 addr; - u32 lo, hi; - u8 wrap32dis = 0; - u8 valid = 0; - - /* Skip reset DLL for B3 */ - if (pDCTstat->LogicalCPUID & AMD_DR_B3) { - return; - } - - /* Skip reset DLL for Family 15h */ - if (is_fam15h()) { - return; - } - - addr = HWCR_MSR; - _RDMSR(addr, &lo, &hi); - if (lo & (1<<17)) { /* save the old value */ - wrap32dis = 1; - } - lo |= (1<<17); /* HWCR.wrap32dis */ - /* Setting wrap32dis allows 64-bit memory references in 32bit mode */ - _WRMSR(addr, lo, hi); - - pDCTstat->Channel = dct; - Receiver = mct_InitReceiver_D(pDCTstat, dct); - /* there are four receiver pairs, loosely associated with chipselects.*/ - for (; Receiver < 8; Receiver += 2) { - if (mct_RcvrRankEnabled_D(pMCTstat, pDCTstat, dct, Receiver)) { - addr = mct_GetRcvrSysAddr_D(pMCTstat, pDCTstat, dct, Receiver, &valid); - if (valid) { - mct_Read1LTestPattern_D(pMCTstat, pDCTstat, addr); /* cache fills */ - - /* Write 0000_8000h to register F2x[1,0]9C_xD080F0C */ - Set_NB32_index_wait_DCT(dev, dct, 0x98, 0xD080F0C, 0x00008000); - mct_Wait(80); /* wait >= 300ns */ - - /* Write 0000_0000h to register F2x[1,0]9C_xD080F0C */ - Set_NB32_index_wait_DCT(dev, dct, 0x98, 0xD080F0C, 0x00000000); - mct_Wait(800); /* wait >= 2us */ - break; - } - } - } - - if (!wrap32dis) { - addr = HWCR_MSR; - _RDMSR(addr, &lo, &hi); - lo &= ~(1<<17); /* restore HWCR.wrap32dis */ - _WRMSR(addr, lo, hi); - } -} - -void mct_EnableDatIntlv_D(struct MCTStatStruc *pMCTstat, - struct DCTStatStruc *pDCTstat) -{ - u32 dev = pDCTstat->dev_dct; - u32 val; - - /* Enable F2x110[DctDatIntlv] */ - /* Call back not required mctHookBeforeDatIntlv_D() */ - /* FIXME Skip for Ax */ - if (!pDCTstat->GangedMode) { - val = Get_NB32(dev, 0x110); - val |= 1 << 5; /* DctDatIntlv */ - Set_NB32(dev, 0x110, val); - - /* FIXME Skip for Cx */ - dev = pDCTstat->dev_nbmisc; - val = Get_NB32(dev, 0x8C); /* NB Configuration Hi */ - val |= 1 << (36-32); /* DisDatMask */ - Set_NB32(dev, 0x8C, val); - } -} - -void SetDllSpeedUp_D(struct MCTStatStruc *pMCTstat, - struct DCTStatStruc *pDCTstat, u8 dct) -{ - if (!is_fam15h()) { - u32 val; - u32 dev = pDCTstat->dev_dct; - - if (pDCTstat->Speed >= mhz_to_memclk_config(800)) { /* DDR1600 and above */ - /* Set bit13 PowerDown to register F2x[1, 0]98_x0D080F10 */ - Set_NB32_DCT(dev, dct, 0x98, 0x0D080F10); - val = Get_NB32_DCT(dev, dct, 0x9C); - val |= 1 < 13; - Set_NB32_DCT(dev, dct, 0x9C, val); - Set_NB32_DCT(dev, dct, 0x98, 0x4D080F10); - - /* Set bit13 PowerDown to register F2x[1, 0]98_x0D080F11 */ - Set_NB32_DCT(dev, dct, 0x98, 0x0D080F11); - val = Get_NB32_DCT(dev, dct, 0x9C); - val |= 1 < 13; - Set_NB32_DCT(dev, dct, 0x9C, val); - Set_NB32_DCT(dev, dct, 0x98, 0x4D080F11); - - /* Set bit13 PowerDown to register F2x[1, 0]98_x0D088F30 */ - Set_NB32_DCT(dev, dct, 0x98, 0x0D088F30); - val = Get_NB32_DCT(dev, dct, 0x9C); - val |= 1 < 13; - Set_NB32_DCT(dev, dct, 0x9C, val); - Set_NB32_DCT(dev, dct, 0x98, 0x4D088F30); - - /* Set bit13 PowerDown to register F2x[1, 0]98_x0D08CF30 */ - Set_NB32_DCT(dev, dct, 0x98, 0x0D08CF30); - val = Get_NB32_DCT(dev, dct, 0x9C); - val |= 1 < 13; - Set_NB32_DCT(dev, dct, 0x9C, val); - Set_NB32_DCT(dev, dct, 0x98, 0x4D08CF30); - } - } -} - -static void SyncSetting(struct DCTStatStruc *pDCTstat) -{ - /* set F2x78[ChSetupSync] when F2x[1, 0]9C_x04[AddrCmdSetup, CsOdtSetup, - * CkeSetup] setups for one DCT are all 0s and at least one of the setups, - * F2x[1, 0]9C_x04[AddrCmdSetup, CsOdtSetup, CkeSetup], of the other - * controller is 1 - */ - u32 cha, chb; - u32 dev = pDCTstat->dev_dct; - u32 val; - - cha = pDCTstat->CH_ADDR_TMG[0] & 0x0202020; - chb = pDCTstat->CH_ADDR_TMG[1] & 0x0202020; - - if ((cha != chb) && ((cha == 0) || (chb == 0))) { - val = Get_NB32(dev, 0x78); - val |= 1 << ChSetupSync; - Set_NB32(dev, 0x78, val); - } -} - -static void AfterDramInit_D(struct DCTStatStruc *pDCTstat, u8 dct) { - - u32 val; - u32 dev = pDCTstat->dev_dct; - - if (pDCTstat->LogicalCPUID & (AMD_DR_B2 | AMD_DR_B3)) { - mct_Wait(10000); /* Wait 50 us*/ - val = Get_NB32(dev, 0x110); - if (!(val & (1 << DramEnabled))) { - /* If 50 us expires while DramEnable =0 then do the following */ - val = Get_NB32_DCT(dev, dct, 0x90); - val &= ~(1 << Width128); /* Program Width128 = 0 */ - Set_NB32_DCT(dev, dct, 0x90, val); - - val = Get_NB32_index_wait_DCT(dev, dct, 0x98, 0x05); /* Perform dummy CSR read to F2x09C_x05 */ - - if (pDCTstat->GangedMode) { - val = Get_NB32_DCT(dev, dct, 0x90); - val |= 1 << Width128; /* Program Width128 = 0 */ - Set_NB32_DCT(dev, dct, 0x90, val); - } - } - } -} - -/* ========================================================== - * 6-bit Bank Addressing Table - * RR = rows-13 binary - * B = Banks-2 binary - * CCC = Columns-9 binary - * ========================================================== - * DCT CCCBRR Rows Banks Columns 64-bit CS Size - * Encoding - * 0000 000000 13 2 9 128MB - * 0001 001000 13 2 10 256MB - * 0010 001001 14 2 10 512MB - * 0011 010000 13 2 11 512MB - * 0100 001100 13 3 10 512MB - * 0101 001101 14 3 10 1GB - * 0110 010001 14 2 11 1GB - * 0111 001110 15 3 10 2GB - * 1000 010101 14 3 11 2GB - * 1001 010110 15 3 11 4GB - * 1010 001111 16 3 10 4GB - * 1011 010111 16 3 11 8GB - */ -uint8_t crcCheck(struct DCTStatStruc *pDCTstat, uint8_t dimm) -{ - u16 crc_calc = spd_ddr3_calc_crc(pDCTstat->spd_data.spd_bytes[dimm], - sizeof(pDCTstat->spd_data.spd_bytes[dimm])); - u16 checksum_spd = pDCTstat->spd_data.spd_bytes[dimm][SPD_byte_127] << 8 - | pDCTstat->spd_data.spd_bytes[dimm][SPD_byte_126]; - - return crc_calc == checksum_spd; -} - -int32_t abs(int32_t val) -{ - if (val < 0) - return -val; - return val; -} diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.h b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.h deleted file mode 100644 index 952a66f71a..0000000000 --- a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.h +++ /dev/null @@ -1,1165 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2015-2017 Raptor Engineering, LLC - * Copyright (C) 2010 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -/* - * Description: Include file for all generic DDR 3 MCT files. - */ -#ifndef MCT_D_H -#define MCT_D_H - -#define DQS_TRAIN_DEBUG 0 - -#include -#include - -/*=========================================================================== - CPU - K8/FAM10 -===========================================================================*/ -#define PT_L1 0 /* CPU Package Type */ -#define PT_M2 1 -#define PT_S1 2 -#define PT_GR 3 -#define PT_AS 4 -#define PT_C3 5 -#define PT_FM2 6 - -#define J_MIN 0 /* j loop constraint. 1 = CL 2.0 T*/ -#define J_MAX 5 /* j loop constraint. 5 = CL 7.0 T*/ -#define K_MIN 1 /* k loop constraint. 1 = 200 MHz*/ -#define K_MAX 5 /* k loop constraint. 5 = 533 MHz*/ -#define CL_DEF 2 /* Default value for failsafe operation. 2 = CL 4.0 T*/ -#define T_DEF 1 /* Default value for failsafe operation. 1 = 5ns (cycle time)*/ - -#define BSCRate 1 /* reg bit field = rate of dram scrubber for ecc*/ - /* memory initialization (ecc and check-bits).*/ - /* 1 = 40 ns/64 bytes.*/ -#define FirstPass 1 /* First pass through RcvEn training*/ -#define SecondPass 2 /* Second pass through Rcven training*/ - -#define RCVREN_MARGIN 6 /* number of DLL taps to delay beyond first passing position*/ -#define MAXASYNCLATCTL_2 2 /* Max Async Latency Control value*/ -#define MAXASYNCLATCTL_3 3 /* Max Async Latency Control value*/ - -#define DQS_FAIL 1 -#define DQS_PASS 0 -#define DQS_WRITEDIR 1 -#define DQS_READDIR 0 -#define MIN_DQS_WNDW 3 -#define secPassOffset 6 -#define Pass1MemClkDly 0x20 /* Add 1/2 Memlock delay */ -#define MAX_RD_LAT 0x3FF -#define MIN_FENCE 14 -#define MAX_FENCE 20 -#define MIN_DQS_WR_FENCE 14 -#define MAX_DQS_WR_FENCE 20 -#define FenceTrnFinDlySeed 19 -#define EarlyArbEn 19 - -#define PA_HOST(Node) ((((0x18+Node) << 3)+0) << 12) /* Node 0 Host Bus function PCI Address bits [15:0]*/ -#define PA_MAP(Node) ((((0x18+Node) << 3)+1) << 12) /* Node 0 MAP function PCI Address bits [15:0]*/ -#define PA_DCT(Node) ((((0x18+Node) << 3)+2) << 12) /* Node 0 DCT function PCI Address bits [15:0]*/ -/* #define PA_EXT_DCT (((00 << 3)+4) << 8) */ /*Node 0 DCT extended configuration registers*/ -/* #define PA_DCTADDL (((00 << 3)+2) << 8) */ /*Node x DCT function, Additional Registers PCI Address bits [15:0]*/ -/* #define PA_EXT_DCTADDL (((00 << 3)+5) << 8) */ /*Node x DCT function, Additional Registers PCI Address bits [15:0]*/ - -#define PA_NBMISC(Node) ((((0x18+Node) << 3)+3) << 12) /*Node 0 Misc PCI Address bits [15:0]*/ -#define PA_LINK(Node) ((((0x18+Node) << 3)+4) << 12) /*Node 0 Link Control bits [15:0]*/ -#define PA_NBCTL(Node) ((((0x18+Node) << 3)+5) << 12) /*Node 0 NB Control PCI Address bits [15:0]*/ -/* #define PA_NBDEVOP (((00 << 3)+3) << 8) */ /*Node 0 Misc PCI Address bits [15:0]*/ - -#define DCC_EN 1 /* X:2:0x94[19]*/ -#define ILD_Lmt 3 /* X:2:0x94[18:16]*/ - -#define EncodedTSPD 0x00191709 /* encodes which SPD byte to get T from*/ - /* versus CL X, CL X-.5, and CL X-1*/ - -#define Bias_TrpT 5 /* bias to convert bus clocks to bit field value*/ -#define Bias_TrrdT 4 -#define Bias_TrcdT 5 -#define Bias_TrasT 15 -#define Bias_TrcT 11 -#define Bias_TrtpT 4 -#define Bias_TwrT 4 -#define Bias_TwtrT 4 -#define Bias_TfawT 14 - -#define Min_TrpT 5 /* min programmable value in busclocks */ -#define Max_TrpT 12 /* max programmable value in busclocks */ -#define Min_TrrdT 4 -#define Max_TrrdT 7 -#define Min_TrcdT 5 -#define Max_TrcdT 12 -#define Min_TrasT 15 -#define Max_TrasT 30 -#define Min_TrcT 11 -#define Max_TrcT 42 -#define Min_TrtpT 4 -#define Max_TrtpT 7 -#define Min_TwrT 5 -#define Max_TwrT 12 -#define Min_TwtrT 4 -#define Max_TwtrT 7 -#define Min_TfawT 16 -#define Max_TfawT 32 - -/*common register bit names*/ -#define DramHoleValid 0 /* func 1, offset F0h, bit 0*/ -#define DramMemHoistValid 1 /* func 1, offset F0h, bit 1*/ -#define CSEnable 0 /* func 2, offset 40h-5C, bit 0*/ -#define Spare 1 /* func 2, offset 40h-5C, bit 1*/ -#define TestFail 2 /* func 2, offset 40h-5C, bit 2*/ -#define DqsRcvEnTrain 18 /* func 2, offset 78h, bit 18*/ -#define EnDramInit 31 /* func 2, offset 7Ch, bit 31*/ -#define PchgPDModeSel 23 /* func 2, offset 84h, bit 23 */ -#define DisAutoRefresh 18 /* func 2, offset 8Ch, bit 18*/ -#define InitDram 0 /* func 2, offset 90h, bit 0*/ -#define BurstLength32 10 /* func 2, offset 90h, bit 10*/ -#define Width128 11 /* func 2, offset 90h, bit 11*/ -#define X4Dimm 12 /* func 2, offset 90h, bit 12*/ -#define UnBuffDimm 16 /* func 2, offset 90h, bit 16*/ -#define DimmEcEn 19 /* func 2, offset 90h, bit 19*/ -#define MemClkFreqVal ((is_fam15h())?7:3) /* func 2, offset 94h, bit 3 or 7*/ -#define RDqsEn 12 /* func 2, offset 94h, bit 12*/ -#define DisDramInterface 14 /* func 2, offset 94h, bit 14*/ -#define PowerDownEn 15 /* func 2, offset 94h, bit 15*/ -#define DctAccessWrite 30 /* func 2, offset 98h, bit 30*/ -#define DctAccessDone 31 /* func 2, offset 98h, bit 31*/ -#define MemClrStatus 0 /* func 2, offset A0h, bit 0*/ -#define PwrSavingsEn 10 /* func 2, offset A0h, bit 10*/ -#define Mod64BitMux 4 /* func 2, offset A0h, bit 4*/ -#define DisableJitter 1 /* func 2, offset A0h, bit 1*/ -#define MemClrDis 1 /* func 3, offset F8h, FNC 4, bit 1*/ -#define SyncOnUcEccEn 2 /* func 3, offset 44h, bit 2*/ -#define Dr_MemClrStatus 10 /* func 3, offset 110h, bit 10*/ -#define MemClrBusy 9 /* func 3, offset 110h, bit 9*/ -#define DctGangEn 4 /* func 3, offset 110h, bit 4*/ -#define MemClrInit 3 /* func 3, offset 110h, bit 3*/ -#define SendZQCmd 29 /* func 2, offset 7Ch, bit 29 */ -#define AssertCke 28 /* func 2, offset 7Ch, bit 28*/ -#define DeassertMemRstX 27 /* func 2, offset 7Ch, bit 27*/ -#define SendMrsCmd 26 /* func 2, offset 7Ch, bit 26*/ -#define SendAutoRefresh 25 /* func 2, offset 7Ch, bit 25*/ -#define SendPchgAll 24 /* func 2, offset 7Ch, bit 24*/ -#define DisDqsBar 6 /* func 2, offset 90h, bit 6*/ -#define DramEnabled 8 /* func 2, offset 110h, bit 8*/ -#define LegacyBiosMode 9 /* func 2, offset 94h, bit 9*/ -#define PrefDramTrainMode 28 /* func 2, offset 11Ch, bit 28*/ -#define FlushWr 30 /* func 2, offset 11Ch, bit 30*/ -#define DisAutoComp 30 /* func 2, offset 9Ch, Index 8, bit 30*/ -#define DqsRcvTrEn 13 /* func 2, offset 9Ch, Index 8, bit 13*/ -#define ForceAutoPchg 23 /* func 2, offset 90h, bit 23*/ -#define ClLinesToNbDis 15 /* Bu_CFG2, bit 15*/ -#define WbEnhWsbDis_D (48-32) -#define PhyFenceTrEn 3 /* func 2, offset 9Ch, Index 8, bit 3 */ -#define ParEn 8 /* func 2, offset 90h, bit 8 */ -#define DcqArbBypassEn 19 /* func 2, offset 94h, bit 19 */ -#define ActiveCmdAtRst 1 /* func 2, offset A8H, bit 1 */ -#define FlushWrOnStpGnt 29 /* func 2, offset 11Ch, bit 29 */ -#define BankSwizzleMode 22 /* func 2, offset 94h, bit 22 */ -#define ChSetupSync 15 /* func 2, offset 78h, bit 15 */ - -#define Ddr3Mode 8 /* func 2, offset 94h, bit 8 */ -#define EnterSelfRef 17 /* func 2, offset 90h, bit 17 */ -#define onDimmMirror 3 /* func 2, offset 5C:40h, bit 3 */ -#define OdtSwizzle 6 /* func 2, offset A8h, bit 6 */ -#define FreqChgInProg 21 /* func 2, offset 94h, bit 21 */ -#define ExitSelfRef 1 /* func 2, offset 90h, bit 1 */ - -#define SubMemclkRegDly 5 /* func 2, offset A8h, bit 5 */ -#define Ddr3FourSocketCh 2 /* func 2, offset A8h, bit 2 */ -#define SendControlWord 30 /* func 2, offset 7Ch, bit 30 */ - -#define NB_GfxNbPstateDis 62 /* MSRC001_001F Northbridge Configuration Register (NB_CFG) bit 62 GfxNbPstateDis disable northbridge p-state transitions */ -/*============================================================================= - SW Initialization -============================================================================*/ -#define DLL_Enable 1 -#define OCD_Default 2 -#define OCD_Exit 3 - -/*============================================================================= - Jedec DDR II -=============================================================================*/ -#define SPD_ByteUse 0 -#define SPD_TYPE 2 /*SPD byte read location*/ - #define JED_DDRSDRAM 0x07 /*Jedec defined bit field*/ - #define JED_DDR2SDRAM 0x08 /*Jedec defined bit field*/ - #define JED_DDR3SDRAM 0x0B /* Jedec defined bit field*/ - -#define SPD_DIMMTYPE 3 -#define SPD_ATTRIB 21 - #define JED_DIFCKMSK 0x20 /*Differential Clock Input*/ - #define JED_REGADCMSK 0x11 /*Registered Address/Control*/ - #define JED_PROBEMSK 0x40 /*Analysis Probe installed*/ - #define JED_RDIMM 0x1 /* RDIMM */ - #define JED_MiniRDIMM 0x5 /* Mini-RDIMM */ - #define JED_LRDIMM 0xb /* Load-reduced DIMM */ -#define SPD_Density 4 /* Bank address bits,SDRAM capacity */ -#define SPD_Addressing 5 /* Row/Column address bits */ -#define SPD_Voltage 6 /* Supported voltage bitfield */ -#define SPD_Organization 7 /* rank#,Device width */ -#define SPD_BusWidth 8 /* ECC, Bus width */ - #define JED_ECC 8 /* ECC capability */ - -#define SPD_MTBDividend 10 -#define SPD_MTBDivisor 11 -#define SPD_tCKmin 12 -#define SPD_CASLow 14 -#define SPD_CASHigh 15 -#define SPD_tAAmin 16 - -#define SPD_DEVATTRIB 22 -#define SPD_EDCTYPE 11 - #define JED_ADRCPAR 0x04 - -#define SPD_tWRmin 17 -#define SPD_tRCDmin 18 -#define SPD_tRRDmin 19 -#define SPD_tRPmin 20 -#define SPD_Upper_tRAS_tRC 21 -#define SPD_tRASmin 22 -#define SPD_tRCmin 23 -#define SPD_tWTRmin 26 -#define SPD_tRTPmin 27 -#define SPD_Upper_tFAW 28 -#define SPD_tFAWmin 29 -#define SPD_Thermal 31 - -#define SPD_RefRawCard 62 -#define SPD_AddressMirror 63 -#define SPD_RegManufactureID_L 65 /* not used */ -#define SPD_RegManufactureID_H 66 /* not used */ -#define SPD_RegManRevID 67 /* not used */ - -#define SPD_byte_126 126 -#define SPD_byte_127 127 - -#define SPD_ROWSZ 3 -#define SPD_COLSZ 4 -#define SPD_LBANKS 17 /*number of [logical] banks on each device*/ -#define SPD_DMBANKS 5 /*number of physical banks on dimm*/ - #define SPDPLBit 4 /* Dram package bit*/ -#define SPD_BANKSZ 31 /*capacity of physical bank*/ -#define SPD_DEVWIDTH 13 -#define SPD_CASLAT 18 -#define SPD_TRP 27 -#define SPD_TRRD 28 -#define SPD_TRCD 29 -#define SPD_TRAS 30 -#define SPD_TWR 36 -#define SPD_TWTR 37 -#define SPD_TRTP 38 -#define SPD_TRCRFC 40 -#define SPD_TRC 41 -#define SPD_TRFC 42 - -#define SPD_MANDATEYR 93 /*Module Manufacturing Year (BCD)*/ - -#define SPD_MANDATEWK 94 /*Module Manufacturing Week (BCD)*/ - -#define SPD_MANID_START 117 -#define SPD_SERIAL_START 122 -#define SPD_PARTN_START 128 -#define SPD_PARTN_LENGTH 18 -#define SPD_REVNO_START 146 - -/*----------------------------- - Jedec DDR II related equates ------------------------------*/ -#define MYEAR06 6 /* Manufacturing Year BCD encoding of 2006 - 06d*/ -#define MWEEK24 0x24 /* Manufacturing Week BCD encoding of June - 24d*/ - -/*============================================================================= - Macros -=============================================================================*/ - -#define _2GB_RJ8 (2<<(30-8)) -#define _4GB_RJ8 (4<<(30-8)) -#define _4GB_RJ4 (4<<(30-4)) - -#define BigPagex8_RJ8 (1<<(17+3-8)) /*128KB * 8 >> 8 */ - -/*============================================================================= - Global MCT Status Structure -=============================================================================*/ -struct MCTStatStruc { - u32 GStatus; /* Global Status bitfield*/ - u32 HoleBase; /* If not zero, BASE[39:8] (system address) - of sub 4GB dram hole for HW remapping.*/ - u32 Sub4GCacheTop; /* If not zero, the 32-bit top of cacheable memory.*/ - u32 SysLimit; /* LIMIT[39:8] (system address)*/ - uint32_t TSCFreq; - uint16_t nvram_checksum; - uint8_t try_ecc; -} __attribute__((packed, aligned(4))); - -/*============================================================================= - Global MCT Configuration Status Word (GStatus) -=============================================================================*/ -/*These should begin at bit 0 of GStatus[31:0]*/ -#define GSB_MTRRshort 0 /* Ran out of MTRRs while mapping memory*/ -#define GSB_ECCDIMMs 1 /* All banks of all Nodes are ECC capable*/ -#define GSB_DramECCDis 2 /* Dram ECC requested but not enabled.*/ -#define GSB_SoftHole 3 /* A Node Base gap was created*/ -#define GSB_HWHole 4 /* A HW dram remap was created*/ -#define GSB_NodeIntlv 5 /* Node Memory interleaving was enabled*/ -#define GSB_SpIntRemapHole 16 /* Special condition for Node Interleave and HW remapping*/ -#define GSB_EnDIMMSpareNW 17 /* Indicates that DIMM Spare can be used without a warm reset */ - /* NOTE: This is a local bit used by memory code */ -#define GSB_ConfigRestored 18 /* Training configuration was restored from NVRAM */ - -/*=============================================================================== - Local DCT Status structure (a structure for each DCT) -===============================================================================*/ -#include "mwlc_d.h" /* I have to */ - -struct amd_spd_node_data { - uint8_t spd_bytes[MAX_DIMMS_SUPPORTED][256]; /* [DIMM][byte] */ - uint8_t spd_address[MAX_DIMMS_SUPPORTED]; /* [DIMM] */ - uint64_t spd_hash[MAX_DIMMS_SUPPORTED]; /* [DIMM] */ - uint64_t nvram_spd_hash[MAX_DIMMS_SUPPORTED]; /* [DIMM] */ - uint8_t nvram_spd_match; - uint8_t nvram_memclk[2]; /* [channel] */ -} __attribute__((packed, aligned(4))); - -struct DCTPersistentStatStruc { - u8 CH_D_B_TxDqs[2][4][9]; /* [A/B] [DIMM1-4] [DQS] */ - /* CHA DIMM0 Byte 0 - 7 TxDqs */ - /* CHA DIMM0 Byte 0 - 7 TxDqs */ - /* CHA DIMM1 Byte 0 - 7 TxDqs */ - /* CHA DIMM1 Byte 0 - 7 TxDqs */ - /* CHB DIMM0 Byte 0 - 7 TxDqs */ - /* CHB DIMM0 Byte 0 - 7 TxDqs */ - /* CHB DIMM1 Byte 0 - 7 TxDqs */ - /* CHB DIMM1 Byte 0 - 7 TxDqs */ - u16 HostBiosSrvc1; /* Word sized general purpose field for use by host BIOS. Scratch space.*/ - u32 HostBiosSrvc2; /* Dword sized general purpose field for use by host BIOS. Scratch space.*/ -} __attribute__((packed, aligned(4))); - -struct DCTStatStruc { /* A per Node structure*/ -/* DCTStatStruct_F - start */ - u8 Node_ID; /* Node ID of current controller */ - uint8_t Internal_Node_ID; /* Internal Node ID of the current controller */ - uint8_t Dual_Node_Package; /* 1 = Dual node package (G34) */ - uint8_t stopDCT[2]; /* Set if the DCT will be stopped */ - u8 ErrCode; /* Current error condition of Node - 0= no error - 1= Variance Error, DCT is running but not in an optimal configuration. - 2= Stop Error, DCT is NOT running - 3= Fatal Error, DCT/MCT initialization has been halted.*/ - u32 ErrStatus; /* Error Status bit Field */ - u32 Status; /* Status bit Field*/ - u8 DIMMAddr[8]; /* SPD address of DIMM controlled by MA0_CS_L[0,1]*/ - /* SPD address of..MB0_CS_L[0,1]*/ - /* SPD address of..MA1_CS_L[0,1]*/ - /* SPD address of..MB1_CS_L[0,1]*/ - /* SPD address of..MA2_CS_L[0,1]*/ - /* SPD address of..MB2_CS_L[0,1]*/ - /* SPD address of..MA3_CS_L[0,1]*/ - /* SPD address of..MB3_CS_L[0,1]*/ - u16 DIMMPresent; /*For each bit n 0..7, 1 = DIMM n is present. - DIMM# Select Signal - 0 MA0_CS_L[0,1] - 1 MB0_CS_L[0,1] - 2 MA1_CS_L[0,1] - 3 MB1_CS_L[0,1] - 4 MA2_CS_L[0,1] - 5 MB2_CS_L[0,1] - 6 MA3_CS_L[0,1] - 7 MB3_CS_L[0,1]*/ - u16 DIMMValid; /* For each bit n 0..7, 1 = DIMM n is valid and is/will be configured*/ - u16 DIMMMismatch; /* For each bit n 0..7, 1 = DIMM n is mismatched, channel B is always considered the mismatch */ - u16 DIMMSPDCSE; /* For each bit n 0..7, 1 = DIMM n SPD checksum error*/ - u16 DimmECCPresent; /* For each bit n 0..7, 1 = DIMM n is ECC capable.*/ - u16 DimmPARPresent; /* For each bit n 0..7, 1 = DIMM n is ADR/CMD Parity capable.*/ - u16 Dimmx4Present; /* For each bit n 0..7, 1 = DIMM n contains x4 data devices.*/ - u16 Dimmx8Present; /* For each bit n 0..7, 1 = DIMM n contains x8 data devices.*/ - u16 Dimmx16Present; /* For each bit n 0..7, 1 = DIMM n contains x16 data devices.*/ - u16 DIMM2Kpage; /* For each bit n 0..7, 1 = DIMM n contains 1K page devices.*/ - u8 MAload[2]; /* Number of devices loading MAA bus*/ - /* Number of devices loading MAB bus*/ - u8 MAdimms[2]; /*Number of DIMMs loading CH A*/ - /* Number of DIMMs loading CH B*/ - u8 DATAload[2]; /*Number of ranks loading CH A DATA*/ - /* Number of ranks loading CH B DATA*/ - u8 DIMMAutoSpeed; /*Max valid Mfg. Speed of DIMMs - 1 = 200MHz - 2 = 266MHz - 3 = 333MHz - 4 = 400MHz - 5 = 533MHz*/ - u8 DIMMCASL; /* Min valid Mfg. CL bitfield - 0 = 2.0 - 1 = 3.0 - 2 = 4.0 - 3 = 5.0 - 4 = 6.0 */ - u16 DIMMTrcd; /* Minimax Trcd*40 (ns) of DIMMs*/ - u16 DIMMTrp; /* Minimax Trp*40 (ns) of DIMMs*/ - u16 DIMMTrtp; /* Minimax Trtp*40 (ns) of DIMMs*/ - u16 DIMMTras; /* Minimax Tras*40 (ns) of DIMMs*/ - u16 DIMMTrc; /* Minimax Trc*40 (ns) of DIMMs*/ - u16 DIMMTwr; /* Minimax Twr*40 (ns) of DIMMs*/ - u16 DIMMTrrd; /* Minimax Trrd*40 (ns) of DIMMs*/ - u16 DIMMTwtr; /* Minimax Twtr*40 (ns) of DIMMs*/ - u8 Speed; /* Bus Speed (to set Controller) - 1 = 200MHz - 2 = 266MHz - 3 = 333MHz - 4 = 400MHz */ - u8 CASL; /* CAS latency DCT setting - 0 = 2.0 - 1 = 3.0 - 2 = 4.0 - 3 = 5.0 - 4 = 6.0 */ - u8 Trcd; /* DCT Trcd (busclocks) */ - u8 Trp; /* DCT Trp (busclocks) */ - u8 Trtp; /* DCT Trtp (busclocks) */ - u8 Tras; /* DCT Tras (busclocks) */ - u8 Trc; /* DCT Trc (busclocks) */ - u8 Twr; /* DCT Twr (busclocks) */ - u8 Trrd; /* DCT Trrd (busclocks) */ - u8 Twtr; /* DCT Twtr (busclocks) */ - u8 Trfc[4]; /* DCT Logical DIMM0 Trfc - 0 = 75ns (for 256Mb devs) - 1 = 105ns (for 512Mb devs) - 2 = 127.5ns (for 1Gb devs) - 3 = 195ns (for 2Gb devs) - 4 = 327.5ns (for 4Gb devs) */ - /* DCT Logical DIMM1 Trfc (see Trfc0 for format) */ - /* DCT Logical DIMM2 Trfc (see Trfc0 for format) */ - /* DCT Logical DIMM3 Trfc (see Trfc0 for format) */ - u16 CSPresent; /* For each bit n 0..7, 1 = Chip-select n is present */ - u16 CSTestFail; /* For each bit n 0..7, 1 = Chip-select n is present but disabled */ - u32 DCTSysBase; /* BASE[39:8] (system address) of this Node's DCTs. */ - u32 DCTHoleBase; /* If not zero, BASE[39:8] (system address) of dram hole for HW remapping. Dram hole exists on this Node's DCTs. */ - u32 DCTSysLimit; /* LIMIT[39:8] (system address) of this Node's DCTs */ - u16 PresetmaxFreq; /* Maximum OEM defined DDR frequency - 200 = 200MHz (DDR400) - 266 = 266MHz (DDR533) - 333 = 333MHz (DDR667) - 400 = 400MHz (DDR800) */ - u8 _2Tmode; /* 1T or 2T CMD mode (slow access mode) - 1 = 1T - 2 = 2T */ - u8 TrwtTO; /* DCT TrwtTO (busclocks)*/ - u8 Twrrd; /* DCT Twrrd (busclocks)*/ - u8 Twrwr; /* DCT Twrwr (busclocks)*/ - u8 Trdrd; /* DCT Trdrd (busclocks)*/ - u32 CH_ODC_CTL[2]; /* Output Driver Strength (see BKDG FN2:Offset 9Ch, index 00h*/ - u32 CH_ADDR_TMG[2]; /* Address Bus Timing (see BKDG FN2:Offset 9Ch, index 04h*/ - /* Output Driver Strength (see BKDG FN2:Offset 9Ch, index 20h*/ - /* Address Bus Timing (see BKDG FN2:Offset 9Ch, index 24h*/ - u16 CH_EccDQSLike[2]; /* CHA DQS ECC byte like...*/ - u8 CH_EccDQSScale[2]; /* CHA DQS ECC byte scale*/ - /* CHA DQS ECC byte like...*/ - /* CHA DQS ECC byte scale*/ - u8 MaxAsyncLat; /* Max Asynchronous Latency (ns)*/ - /* NOTE: Not used in Barcelona - u8 CH_D_RCVRDLY[2][4]; */ - /* CHA DIMM 0 - 4 Receiver Enable Delay*/ - /* CHB DIMM 0 - 4 Receiver Enable Delay */ - /* NOTE: Not used in Barcelona - u8 CH_D_B_DQS[2][2][8]; */ - /* CHA Byte 0-7 Write DQS Delay */ - /* CHA Byte 0-7 Read DQS Delay */ - /* CHB Byte 0-7 Write DQS Delay */ - /* CHB Byte 0-7 Read DQS Delay */ - u32 PtrPatternBufA; /* Ptr on stack to aligned DQS testing pattern*/ - u32 PtrPatternBufB; /* Ptr on stack to aligned DQS testing pattern*/ - u8 Channel; /* Current Channel (0= CH A, 1 = CH B)*/ - u8 ByteLane; /* Current Byte Lane (0..7)*/ - u8 Direction; /* Current DQS-DQ training write direction (0 = read, 1 = write)*/ - u8 Pattern; /* Current pattern*/ - u8 DQSDelay; /* Current DQS delay value*/ - u32 TrainErrors; /* Current Training Errors*/ - - u32 AMC_TSC_DeltaLo; /* Time Stamp Counter measurement of AMC, Low dword*/ - u32 AMC_TSC_DeltaHi; /* Time Stamp Counter measurement of AMC, High dword*/ - /* NOTE: Not used in Barcelona - */ - u8 CH_D_DIR_MaxMin_B_Dly[2][2][2][8]; - /* CH A byte lane 0 - 7 minimum filtered window passing DQS delay value*/ - /* CH A byte lane 0 - 7 maximum filtered window passing DQS delay value*/ - /* CH B byte lane 0 - 7 minimum filtered window passing DQS delay value*/ - /* CH B byte lane 0 - 7 maximum filtered window passing DQS delay value*/ - /* CH A byte lane 0 - 7 minimum filtered window passing DQS delay value*/ - /* CH A byte lane 0 - 7 maximum filtered window passing DQS delay value*/ - /* CH B byte lane 0 - 7 minimum filtered window passing DQS delay value*/ - /* CH B byte lane 0 - 7 maximum filtered window passing DQS delay value*/ - uint64_t LogicalCPUID; /* The logical CPUID of the node*/ - u16 DimmQRPresent; /* QuadRank DIMM present?*/ - u16 DimmTrainFail; /* Bitmap showing which dimms failed training*/ - u16 CSTrainFail; /* Bitmap showing which chipselects failed training*/ - u16 DimmYr06; /* Bitmap indicating which Dimms have a manufactur's year code <= 2006*/ - u16 DimmWk2406; /* Bitmap indicating which Dimms have a manufactur's week code <= 24 of 2006 (June)*/ - u16 DimmDRPresent; /* Bitmap indicating that Dual Rank Dimms are present*/ - u16 DimmPlPresent; /* Bitmap indicating that Planar (1) or Stacked (0) Dimms are present.*/ - u16 ChannelTrainFai; /* Bitmap showing the channel information about failed Chip Selects - 0 in any bit field indicates Channel 0 - 1 in any bit field indicates Channel 1 */ - u16 DIMMTfaw; /* Minimax Tfaw*16 (ns) of DIMMs */ - u8 Tfaw; /* DCT Tfaw (busclocks) */ - u16 CSUsrTestFail; /* Chip selects excluded by user */ -/* DCTStatStruct_F - end */ - - u16 CH_MaxRdLat[2][2]; /* Max Read Latency (nclks) [dct][pstate] */ - /* Max Read Latency (ns) for DCT 1*/ - u8 CH_D_DIR_B_DQS[2][4][2][9]; /* [A/B] [DIMM1-4] [R/W] [DQS] */ - /* CHA DIMM0 Byte 0 - 7 and Check Write DQS Delay*/ - /* CHA DIMM0 Byte 0 - 7 and Check Read DQS Delay*/ - /* CHA DIMM1 Byte 0 - 7 and Check Write DQS Delay*/ - /* CHA DIMM1 Byte 0 - 7 and Check Read DQS Delay*/ - /* CHB DIMM0 Byte 0 - 7 and Check Write DQS Delay*/ - /* CHB DIMM0 Byte 0 - 7 and Check Read DQS Delay*/ - /* CHB DIMM1 Byte 0 - 7 and Check Write DQS Delay*/ - /* CHB DIMM1 Byte 0 - 7 and Check Read DQS Delay*/ - u16 CH_D_B_RCVRDLY[2][4][8]; /* [A/B] [DIMM0-3] [DQS] */ - /* CHA DIMM 0 Receiver Enable Delay*/ - /* CHA DIMM 1 Receiver Enable Delay*/ - /* CHA DIMM 2 Receiver Enable Delay*/ - /* CHA DIMM 3 Receiver Enable Delay*/ - - /* CHB DIMM 0 Receiver Enable Delay*/ - /* CHB DIMM 1 Receiver Enable Delay*/ - /* CHB DIMM 2 Receiver Enable Delay*/ - /* CHB DIMM 3 Receiver Enable Delay*/ - u16 CH_D_BC_RCVRDLY[2][4]; - /* CHA DIMM 0 - 4 Check Byte Receiver Enable Delay*/ - /* CHB DIMM 0 - 4 Check Byte Receiver Enable Delay*/ - u8 DIMMValidDCT[2]; /* DIMM# in DCT0*/ - /* DIMM# in DCT1*/ - u16 CSPresent_DCT[2]; /* DCT# CS mapping */ - u16 MirrPresU_NumRegR; /* Address mapping from edge connect to DIMM present for unbuffered dimm - Number of registers on the dimm for registered dimm */ - u8 MaxDCTs; /* Max number of DCTs in system*/ - /* NOTE: removed u8 DCT. Use ->dev_ for pci R/W; */ /*DCT pointer*/ - u8 GangedMode; /* Ganged mode enabled, 0 = disabled, 1 = enabled*/ - u8 DRPresent; /* Family 10 present flag, 0 = not Fam10, 1 = Fam10*/ - u32 NodeSysLimit; /* BASE[39:8],for DCT0+DCT1 system address*/ - u8 WrDatGrossH; - u8 DqsRcvEnGrossL; - /* NOTE: Not used - u8 NodeSpeed */ /* Bus Speed (to set Controller) */ - /* 1 = 200MHz */ - /* 2 = 266MHz */ - /* 3 = 333MHz */ - /* NOTE: Not used - u8 NodeCASL */ /* CAS latency DCT setting */ - /* 0 = 2.0 */ - /* 1 = 3.0 */ - /* 2 = 4.0 */ - /* 3 = 5.0 */ - /* 4 = 6.0 */ - u8 TrwtWB; - u8 CurrRcvrCHADelay; /* for keep current RcvrEnDly of chA*/ - u16 T1000; /* get the T1000 figure (cycle time (ns)*1K)*/ - u8 DqsRcvEn_Pass; /* for TrainRcvrEn byte lane pass flag*/ - u8 DqsRcvEn_Saved; /* for TrainRcvrEn byte lane saved flag*/ - u8 SeedPass1Remainder; /* for Phy assisted DQS receiver enable training*/ - - /* for second pass - Second pass should never run for Fam10*/ - /* NOTE: Not used for Barcelona - u8 CH_D_B_RCVRDLY_1[2][4][8]; */ /* CHA DIMM 0 Receiver Enable Delay */ - /* CHA DIMM 1 Receiver Enable Delay*/ - /* CHA DIMM 2 Receiver Enable Delay*/ - /* CHA DIMM 3 Receiver Enable Delay*/ - - /* CHB DIMM 0 Receiver Enable Delay*/ - /* CHB DIMM 1 Receiver Enable Delay*/ - /* CHB DIMM 2 Receiver Enable Delay*/ - /* CHB DIMM 3 Receiver Enable Delay*/ - - u8 ClToNB_flag; /* is used to restore ClLinesToNbDis bit after memory */ - u32 NodeSysBase; /* for channel interleave usage */ - - /* Fam15h specific backup variables */ - uint8_t SwNbPstateLoDis; - uint8_t NbPstateDisOnP0; - uint8_t NbPstateThreshold; - uint8_t NbPstateHi; - - /* New for LB Support */ - u8 NodePresent; - u32 dev_host; - u32 dev_map; - u32 dev_dct; - u32 dev_nbmisc; - u32 dev_link; - u32 dev_nbctl; - u8 TargetFreq; - u8 TargetCASL; - uint32_t CtrlWrd3; - uint32_t CtrlWrd4; - uint32_t CtrlWrd5; - u8 DqsRdWrPos_Saved; - u8 DqsRcvEnGrossMax; - u8 DqsRcvEnGrossMin; - u8 WrDatGrossMax; - u8 WrDatGrossMin; - uint8_t tcwl_delay[2]; - - u16 RegMan1Present; /* DIMM present bitmap of Register manufacture 1 */ - u16 RegMan2Present; /* DIMM present bitmap of Register manufacture 2 */ - - struct _sMCTStruct *C_MCTPtr; - struct _sDCTStruct *C_DCTPtr[2]; - /* struct _sDCTStruct *C_DCT1Ptr; */ - - struct _sMCTStruct s_C_MCTPtr; - struct _sDCTStruct s_C_DCTPtr[2]; - /* struct _sDCTStruct s_C_DCT1Ptr[8]; */ - - /* DIMM supported voltage bitmap ([2:0]: 1.25V, 1.35V, 1.5V) */ - uint8_t DimmSupportedVoltages[MAX_DIMMS_SUPPORTED]; - uint32_t DimmConfiguredVoltage[MAX_DIMMS_SUPPORTED]; /* mV */ - - uint8_t DimmRows[MAX_DIMMS_SUPPORTED]; - uint8_t DimmCols[MAX_DIMMS_SUPPORTED]; - uint8_t DimmRanks[MAX_DIMMS_SUPPORTED]; - uint8_t DimmBanks[MAX_DIMMS_SUPPORTED]; - uint8_t DimmWidth[MAX_DIMMS_SUPPORTED]; - uint64_t DimmChipSize[MAX_DIMMS_SUPPORTED]; - uint32_t DimmChipWidth[MAX_DIMMS_SUPPORTED]; - uint8_t DimmRegistered[MAX_DIMMS_SUPPORTED]; - uint8_t DimmLoadReduced[MAX_DIMMS_SUPPORTED]; - - uint64_t DimmManufacturerID[MAX_DIMMS_SUPPORTED]; - char DimmPartNumber[MAX_DIMMS_SUPPORTED][SPD_PARTN_LENGTH+1]; - uint16_t DimmRevisionNumber[MAX_DIMMS_SUPPORTED]; - uint32_t DimmSerialNumber[MAX_DIMMS_SUPPORTED]; - - struct amd_spd_node_data spd_data; - - /* NOTE: This must remain the last entry in this structure */ - struct DCTPersistentStatStruc persistentData; -} __attribute__((packed, aligned(4))); - -struct amd_s3_persistent_mct_channel_data { - /* Stage 1 (1 dword) */ - uint32_t f2x110; - - /* Stage 2 (88 dwords) */ - uint32_t f1x40; - uint32_t f1x44; - uint32_t f1x48; - uint32_t f1x4c; - uint32_t f1x50; - uint32_t f1x54; - uint32_t f1x58; - uint32_t f1x5c; - uint32_t f1x60; - uint32_t f1x64; - uint32_t f1x68; - uint32_t f1x6c; - uint32_t f1x70; - uint32_t f1x74; - uint32_t f1x78; - uint32_t f1x7c; - uint32_t f1xf0; - uint32_t f1x120; - uint32_t f1x124; - uint32_t f2x10c; - uint32_t f2x114; - uint32_t f2x118; - uint32_t f2x11c; - uint32_t f2x1b0; - uint32_t f3x44; - uint64_t msr0000020[16]; - uint64_t msr00000250; - uint64_t msr00000258; - uint64_t msr0000026[8]; - uint64_t msr000002ff; - uint64_t msrc0010010; - uint64_t msrc001001a; - uint64_t msrc001001d; - uint64_t msrc001001f; - - /* Stage 3 (21 dwords) */ - uint32_t f2x40; - uint32_t f2x44; - uint32_t f2x48; - uint32_t f2x4c; - uint32_t f2x50; - uint32_t f2x54; - uint32_t f2x58; - uint32_t f2x5c; - uint32_t f2x60; - uint32_t f2x64; - uint32_t f2x68; - uint32_t f2x6c; - uint32_t f2x78; - uint32_t f2x7c; - uint32_t f2x80; - uint32_t f2x84; - uint32_t f2x88; - uint32_t f2x8c; - uint32_t f2x90; - uint32_t f2xa4; - uint32_t f2xa8; - - /* Stage 4 (1 dword) */ - uint32_t f2x94; - - /* Stage 6 (33 dwords) */ - uint32_t f2x9cx0d0f0_f_8_0_0_8_4_0[9][3]; /* [lane][setting] */ - uint32_t f2x9cx00; - uint32_t f2x9cx0a; - uint32_t f2x9cx0c; - - /* Stage 7 (1 dword) */ - uint32_t f2x9cx04; - - /* Stage 9 (2 dwords) */ - uint32_t f2x9cx0d0fe006; - uint32_t f2x9cx0d0fe007; - - /* Stage 10 (78 dwords) */ - uint32_t f2x9cx10[12]; - uint32_t f2x9cx20[12]; - uint32_t f2x9cx3_0_0_3_1[4][3]; /* [dimm][setting] */ - uint32_t f2x9cx3_0_0_7_5[4][3]; /* [dimm][setting] */ - uint32_t f2x9cx0d; - uint32_t f2x9cx0d0f0_f_0_13[9]; /* [lane] */ - uint32_t f2x9cx0d0f0_f_0_30[9]; /* [lane] */ - uint32_t f2x9cx0d0f2_f_0_30[4]; /* [pad select] */ - uint32_t f2x9cx0d0f8_8_4_0[2][3]; /* [offset][pad select] */ - uint32_t f2x9cx0d0f812f; - - /* Stage 11 (24 dwords) */ - uint32_t f2x9cx30[12]; - uint32_t f2x9cx40[12]; - - /* Other (3 dwords) */ - uint32_t f3x58; - uint32_t f3x5c; - uint32_t f3x60; - - /* Family 15h-specific registers (91 dwords) */ - uint32_t f2x200; - uint32_t f2x204; - uint32_t f2x208; - uint32_t f2x20c; - uint32_t f2x210[4]; /* [nb pstate] */ - uint32_t f2x214; - uint32_t f2x218; - uint32_t f2x21c; - uint32_t f2x22c; - uint32_t f2x230; - uint32_t f2x234; - uint32_t f2x238; - uint32_t f2x23c; - uint32_t f2x240; - uint32_t f2x9cx0d0fe003; - uint32_t f2x9cx0d0fe013; - uint32_t f2x9cx0d0f0_8_0_1f[9]; /* [lane]*/ - uint32_t f2x9cx0d0f201f; - uint32_t f2x9cx0d0f211f; - uint32_t f2x9cx0d0f221f; - uint32_t f2x9cx0d0f801f; - uint32_t f2x9cx0d0f811f; - uint32_t f2x9cx0d0f821f; - uint32_t f2x9cx0d0fc01f; - uint32_t f2x9cx0d0fc11f; - uint32_t f2x9cx0d0fc21f; - uint32_t f2x9cx0d0f4009; - uint32_t f2x9cx0d0f0_8_0_02[9]; /* [lane]*/ - uint32_t f2x9cx0d0f0_8_0_06[9]; /* [lane]*/ - uint32_t f2x9cx0d0f0_8_0_0a[9]; /* [lane]*/ - uint32_t f2x9cx0d0f2002; - uint32_t f2x9cx0d0f2102; - uint32_t f2x9cx0d0f2202; - uint32_t f2x9cx0d0f8002; - uint32_t f2x9cx0d0f8006; - uint32_t f2x9cx0d0f800a; - uint32_t f2x9cx0d0f8102; - uint32_t f2x9cx0d0f8106; - uint32_t f2x9cx0d0f810a; - uint32_t f2x9cx0d0fc002; - uint32_t f2x9cx0d0fc006; - uint32_t f2x9cx0d0fc00a; - uint32_t f2x9cx0d0fc00e; - uint32_t f2x9cx0d0fc012; - uint32_t f2x9cx0d0f2031; - uint32_t f2x9cx0d0f2131; - uint32_t f2x9cx0d0f2231; - uint32_t f2x9cx0d0f8031; - uint32_t f2x9cx0d0f8131; - uint32_t f2x9cx0d0f8231; - uint32_t f2x9cx0d0fc031; - uint32_t f2x9cx0d0fc131; - uint32_t f2x9cx0d0fc231; - uint32_t f2x9cx0d0f0_0_f_31[9]; /* [lane] */ - uint32_t f2x9cx0d0f8021; - uint32_t f2x9cx0d0fe00a; - - /* TOTAL: 343 dwords */ -} __attribute__((packed, aligned(4))); - -struct amd_s3_persistent_node_data { - uint32_t node_present; - uint64_t spd_hash[MAX_DIMMS_SUPPORTED]; - uint8_t memclk[2]; - struct amd_s3_persistent_mct_channel_data channel[2]; -} __attribute__((packed, aligned(4))); - -struct amd_s3_persistent_data { - struct amd_s3_persistent_node_data node[MAX_NODES_SUPPORTED]; - uint16_t nvram_checksum; -} __attribute__((packed, aligned(4))); - -/*=============================================================================== - Local Error Status Codes (DCTStatStruc.ErrCode) -===============================================================================*/ -#define SC_RunningOK 0 -#define SC_VarianceErr 1 /* Running non-optimally*/ -#define SC_StopError 2 /* Not Running*/ -#define SC_FatalErr 3 /* Fatal Error, MCTB has exited immediately*/ - -/*=============================================================================== - Local Error Status (DCTStatStruc.ErrStatus[31:0]) -===============================================================================*/ -#define SB_NoDimms 0 -#define SB_DIMMChkSum 1 -#define SB_DimmMismatchM 2 /* dimm module type(buffer) mismatch*/ -#define SB_DimmMismatchT 3 /* dimm CL/T mismatch*/ -#define SB_DimmMismatchO 4 /* dimm organization mismatch (128-bit)*/ -#define SB_NoTrcTrfc 5 /* SPD missing Trc or Trfc info*/ -#define SB_NoCycTime 6 /* SPD missing byte 23 or 25*/ -#define SB_BkIntDis 7 /* Bank interleave requested but not enabled*/ -#define SB_DramECCDis 8 /* Dram ECC requested but not enabled*/ -#define SB_SpareDis 9 /* Online spare requested but not enabled*/ -#define SB_MinimumMode 10 /* Running in Minimum Mode*/ -#define SB_NORCVREN 11 /* No DQS Receiver Enable pass window found*/ -#define SB_CHA2BRCVREN 12 /* DQS Rcvr En pass window CHA to CH B too large*/ -#define SB_SmallRCVR 13 /* DQS Rcvr En pass window too small (far right of dynamic range)*/ -#define SB_NODQSPOS 14 /* No DQS-DQ passing positions*/ -#define SB_SMALLDQS 15 /* DQS-DQ passing window too small*/ -#define SB_DCBKScrubDis 16 /* DCache scrub requested but not enabled */ -#define SB_RetryConfigTrain 17 /* Retry configuration and training */ -#define SB_FatalError 18 /* Fatal training error detected */ - -/*=============================================================================== - Local Configuration Status (DCTStatStruc.Status[31:0]) -===============================================================================*/ -#define SB_Registered 0 /* All DIMMs are Registered*/ -#define SB_LoadReduced 1 /* All DIMMs are Load-Reduced*/ -#define SB_ECCDIMMs 2 /* All banks ECC capable*/ -#define SB_PARDIMMs 3 /* All banks Addr/CMD Parity capable*/ -#define SB_DiagClks 4 /* Jedec ALL slots clock enable diag mode*/ -#define SB_128bitmode 5 /* DCT in 128-bit mode operation*/ -#define SB_64MuxedMode 6 /* DCT in 64-bit mux'ed mode.*/ -#define SB_2TMode 7 /* 2T CMD timing mode is enabled.*/ -#define SB_SWNodeHole 8 /* Remapping of Node Base on this Node to create a gap.*/ -#define SB_HWHole 9 /* Memory Hole created on this Node using HW remapping.*/ -#define SB_Over400MHz 10 /* DCT freq >= 400MHz flag*/ -#define SB_DQSPos_Pass2 11 /* Using for TrainDQSPos DIMM0/1, when freq >= 400MHz*/ -#define SB_DQSRcvLimit 12 /* Using for DQSRcvEnTrain to know we have reached to upper bound.*/ -#define SB_ExtConfig 13 /* Indicator the default setting for extend PCI configuration support*/ - - -/*=============================================================================== - NVRAM/run-time-configurable Items -===============================================================================*/ -/*Platform Configuration*/ -#define NV_PACK_TYPE 0 /* CPU Package Type (2-bits) - 0 = NPT L1 - 1 = NPT M2 - 2 = NPT S1*/ -#define NV_MAX_NODES 1 /* Number of Nodes/Sockets (4-bits)*/ -#define NV_MAX_DIMMS 2 /* Number of DIMM slots for the specified Node ID (4-bits)*/ -#define NV_MAX_MEMCLK 3 /* Maximum platform demonstrated Memclock (10-bits) - 200 = 200MHz (DDR400) - 266 = 266MHz (DDR533) - 333 = 333MHz (DDR667) - 400 = 400MHz (DDR800)*/ -#define NV_MIN_MEMCLK 4 /* Minimum platform demonstrated Memclock (10-bits) */ -#define NV_ECC_CAP 5 /* Bus ECC capable (1-bits) - 0 = Platform not capable - 1 = Platform is capable*/ -#define NV_4RANKType 6 /* Quad Rank DIMM slot type (2-bits) - 0 = Normal - 1 = R4 (4-Rank Registered DIMMs in AMD server configuration) - 2 = S4 (Unbuffered SO-DIMMs)*/ -#define NV_BYPMAX 7 /* Value to set DcqBypassMax field (See Function 2, Offset 94h, [27:24] of BKDG for field definition). - 4 = 4 times bypass (normal for non-UMA systems) - 7 = 7 times bypass (normal for UMA systems)*/ -#define NV_RDWRQBYP 8 /* Value to set RdWrQByp field (See Function 2, Offset A0h, [3:2] of BKDG for field definition). - 2 = 8 times (normal for non-UMA systems) - 3 = 16 times (normal for UMA systems)*/ - - -/*Dram Timing*/ -#define NV_MCTUSRTMGMODE 10 /* User Memclock Mode (2-bits) - 0 = Auto, no user limit - 1 = Auto, user limit provided in NV_MemCkVal - 2 = Manual, user value provided in NV_MemCkVal*/ -#define NV_MemCkVal 11 /* Memory Clock Value (2-bits) - 0 = 200MHz - 1 = 266MHz - 2 = 333MHz - 3 = 400MHz*/ - -/*Dram Configuration*/ -#define NV_BankIntlv 20 /* Dram Bank (chip-select) Interleaving (1-bits) - 0 = disable - 1 = enable*/ -#define NV_AllMemClks 21 /* Turn on All DIMM clocks (1-bits) - 0 = normal - 1 = enable all memclocks*/ -#define NV_SPDCHK_RESTRT 22 /* SPD Check control bitmap (1-bits) - 0 = Exit current node init if any DIMM has SPD checksum error - 1 = Ignore faulty SPD checksums (Note: DIMM cannot be enabled)*/ -#define NV_DQSTrainCTL 23 /* DQS Signal Timing Training Control - 0 = skip DQS training - 1 = perform DQS training*/ -#define NV_NodeIntlv 24 /* Node Memory Interleaving (1-bits) - 0 = disable - 1 = enable*/ -#define NV_BurstLen32 25 /* BurstLength32 for 64-bit mode (1-bits) - 0 = disable (normal) - 1 = enable (4 beat burst when width is 64-bits)*/ - -/*Dram Power*/ -#define NV_CKE_PDEN 30 /* CKE based power down mode (1-bits) - 0 = disable - 1 = enable*/ -#define NV_CKE_CTL 31 /* CKE based power down control (1-bits) - 0 = per Channel control - 1 = per Chip select control*/ -#define NV_CLKHZAltVidC3 32 /* Memclock tri-stating during C3 and Alt VID (1-bits) - 0 = disable - 1 = enable*/ - -/*Memory Map/Mgt.*/ -#define NV_BottomIO 40 /* Bottom of 32-bit IO space (8-bits) - NV_BottomIO[7:0]=Addr[31:24]*/ -#define NV_BottomUMA 41 /* Bottom of shared graphics dram (8-bits) - NV_BottomUMA[7:0]=Addr[31:24]*/ -#define NV_MemHole 42 /* Memory Hole Remapping (1-bits) - 0 = disable - 1 = enable */ - -/*ECC*/ -#define NV_ECC 50 /* Dram ECC enable*/ -#define NV_NBECC 52 /* ECC MCE enable*/ -#define NV_ChipKill 53 /* Chip-Kill ECC Mode enable*/ -#define NV_ECCRedir 54 /* Dram ECC Redirection enable*/ -#define NV_DramBKScrub 55 /* Dram ECC Background Scrubber CTL*/ -#define NV_L2BKScrub 56 /* L2 ECC Background Scrubber CTL*/ -#define NV_L3BKScrub 57 /* L3 ECC Background Scrubber CTL*/ -#define NV_DCBKScrub 58 /* DCache ECC Background Scrubber CTL*/ -#define NV_CS_SpareCTL 59 /* Chip Select Spare Control bit 0: - 0 = disable Spare - 1 = enable Spare */ - /* Chip Select Spare Control bit 1-4: - Reserved, must be zero*/ -#define NV_SyncOnUnEccEn 61 /* SyncOnUnEccEn control - 0 = disable - 1 = enable*/ -#define NV_Unganged 62 - -#define NV_ChannelIntlv 63 /* Channel Interleaving (3-bits) - xx0b = disable - yy1b = enable with DctSelIntLvAddr set to yyb */ - -#define NV_MAX_DIMMS_PER_CH 64 /* Maximum number of DIMMs per channel */ - -/*=============================================================================== - CBMEM storage -===============================================================================*/ -struct amdmct_memory_info { - struct MCTStatStruc mct_stat; - struct DCTStatStruc dct_stat[MAX_NODES_SUPPORTED]; - uint16_t ecc_enabled; - uint16_t ecc_scrub_rate; -} __attribute__((packed, aligned(4))); - -extern const u8 Table_DQSRcvEn_Offset[]; -extern const u32 TestPattern0_D[]; -extern const u32 TestPattern1_D[]; -extern const u32 TestPattern2_D[]; - -u32 Get_NB32(u32 dev, u32 reg); -void Set_NB32(u32 dev, u32 reg, u32 val); -u32 Get_NB32_index(u32 dev, u32 index_reg, u32 index); -void Set_NB32_index(u32 dev, u32 index_reg, u32 index, u32 data); -u32 Get_NB32_index_wait(u32 dev, u32 index_reg, u32 index); -void Set_NB32_index_wait(u32 dev, u32 index_reg, u32 index, u32 data); -u32 OtherTiming_A_D(struct DCTStatStruc *pDCTstat, u32 val); -void mct_ForceAutoPrecharge_D(struct DCTStatStruc *pDCTstat, u32 dct); -u32 Modify_D3CMP(struct DCTStatStruc *pDCTstat, u32 dct, u32 value); -u8 mct_checkNumberOfDqsRcvEn_1Pass(u8 pass); -u32 SetupDqsPattern_1PassA(u8 Pass); -u32 SetupDqsPattern_1PassB(u8 Pass); -u8 mct_Get_Start_RcvrEnDly_1Pass(u8 Pass); -u16 mct_Average_RcvrEnDly_Pass(struct DCTStatStruc *pDCTstat, u16 RcvrEnDly, u16 RcvrEnDlyLimit, u8 Channel, u8 Receiver, u8 Pass); -void initialize_mca(uint8_t bsp, uint8_t suppress_errors); -void CPUMemTyping_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstatA); -void UMAMemTyping_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstatA); -uint64_t mctGetLogicalCPUID(u32 Node); -u8 ECCInit_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstatA); -void TrainReceiverEn_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstatA, u8 Pass); -void TrainMaxRdLatency_En_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstatA); -void mct_TrainDQSPos_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstatA); -void mctSetEccDQSRcvrEn_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstatA); -void TrainMaxReadLatency_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstatA); -void mct_EndDQSTraining_D(struct MCTStatStruc *pMCTstat,struct DCTStatStruc *pDCTstatA); -void mct_SetRcvrEnDly_D(struct DCTStatStruc *pDCTstat, u16 RcvrEnDly, u8 FinalValue, u8 Channel, u8 Receiver, u32 dev, u32 index_reg, u8 Addl_Index, u8 Pass); -void SetEccDQSRcvrEn_D(struct DCTStatStruc *pDCTstat, u8 Channel); -void mctGet_PS_Cfg_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstat, u32 dct); -void InterleaveBanks_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstat, u8 dct); -void mct_SetDramConfigHi_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstat, u32 dct, u32 DramConfigHi); -void mct_DramInit_Hw_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstat, u8 dct); -void mct_SetClToNB_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstat); -void mct_SetWbEnhWsbDis_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstat); -void mct_ForceNBPState0_En_Fam15(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstat); -void mct_ForceNBPState0_Dis_Fam15(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstat); -void mct_TrainRcvrEn_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstat, u8 Pass); -void mct_EnableDimmEccEn_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstat, u8 _DisableDramECC); -u32 procOdtWorkaround(struct DCTStatStruc *pDCTstat, u32 dct, u32 val); -void mct_BeforeDramInit_D(struct DCTStatStruc *pDCTstat, u32 dct); -void DIMMSetVoltages(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstatA); -void InterleaveNodes_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstatA); -void InterleaveChannels_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstatA); -void mct_BeforeDQSTrain_Samp_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstat); - -void phyAssistedMemFnceTraining(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstatA, int16_t Node); -u8 mct_SaveRcvEnDly_D_1Pass(struct DCTStatStruc *pDCTstat, u8 pass); -u8 mct_InitReceiver_D(struct DCTStatStruc *pDCTstat, u8 dct); -void mct_Wait(u32 cycles); -u8 mct_RcvrRankEnabled_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstat, u8 Channel, u8 ChipSel); -u32 mct_GetRcvrSysAddr_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstat, u8 channel, u8 receiver, u8 *valid); -void mct_Read1LTestPattern_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstat, u32 addr); -void mctAutoInitMCT_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstatA); -void calculate_spd_hash(uint8_t *spd_data, uint64_t *spd_hash); -int8_t load_spd_hashes_from_nvram(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstat); -int8_t restore_mct_information_from_nvram(uint8_t training_only); -uint16_t calculate_nvram_mct_hash(void); - -uint32_t fam10h_address_timing_compensation_code(struct DCTStatStruc *pDCTstat, uint8_t dct); -uint32_t fam15h_output_driver_compensation_code(struct DCTStatStruc *pDCTstat, uint8_t dct); -uint32_t fam15h_address_timing_compensation_code(struct DCTStatStruc *pDCTstat, uint8_t dct); -uint8_t fam15h_slow_access_mode(struct DCTStatStruc *pDCTstat, uint8_t dct); -void precise_memclk_delay_fam15(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstat, uint8_t dct, uint32_t clocks); -void mct_EnableDatIntlv_D(struct MCTStatStruc *pMCTstat, - struct DCTStatStruc *pDCTstat); -void SetDllSpeedUp_D(struct MCTStatStruc *pMCTstat, - struct DCTStatStruc *pDCTstat, u8 dct); -uint8_t get_available_lane_count(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstat); -void read_dqs_receiver_enable_control_registers(uint16_t *current_total_delay, uint32_t dev, uint8_t dct, uint8_t dimm, uint32_t index_reg); -void read_dqs_write_timing_control_registers(uint16_t *current_total_delay, uint32_t dev, uint8_t dct, uint8_t dimm, uint32_t index_reg); -void fam15EnableTrainingMode(struct MCTStatStruc *pMCTstat, - struct DCTStatStruc *pDCTstat, uint8_t dct, uint8_t enable); -void read_dqs_read_data_timing_registers(uint16_t *delay, uint32_t dev, - uint8_t dct, uint8_t dimm, uint32_t index_reg); -void write_dqs_read_data_timing_registers(uint16_t *delay, uint32_t dev, - uint8_t dct, uint8_t dimm, uint32_t index_reg); -void dqsTrainMaxRdLatency_SW_Fam15(struct MCTStatStruc *pMCTstat, - struct DCTStatStruc *pDCTstat); -void proc_IOCLFLUSH_D(u32 addr_hi); -u8 ChipSelPresent_D(struct MCTStatStruc *pMCTstat, - struct DCTStatStruc *pDCTstat, - u8 Channel, u8 ChipSel); -void mct_Write1LTestPattern_D(struct MCTStatStruc *pMCTstat, - struct DCTStatStruc *pDCTstat, - u32 TestAddr, u8 pattern); -u8 NodePresent_D(u8 Node); -void DCTMemClr_Init_D(struct MCTStatStruc *pMCTstat, - struct DCTStatStruc *pDCTstat); -void DCTMemClr_Sync_D(struct MCTStatStruc *pMCTstat, - struct DCTStatStruc *pDCTstat); -void SPD2ndTiming(struct MCTStatStruc *pMCTstat, - struct DCTStatStruc *pDCTstat, u8 dct); -void ProgDramMRSReg_D(struct MCTStatStruc *pMCTstat, - struct DCTStatStruc *pDCTstat, u8 dct); -u8 PlatformSpec_D(struct MCTStatStruc *pMCTstat, - struct DCTStatStruc *pDCTstat, u8 dct); -void StartupDCT_D(struct MCTStatStruc *pMCTstat, - struct DCTStatStruc *pDCTstat, u8 dct); -uint16_t mhz_to_memclk_config(uint16_t freq); -void SetTargetFreq(struct MCTStatStruc *pMCTstat, - struct DCTStatStruc *pDCTstatA, uint8_t Node); -void mct_WriteLevelization_HW(struct MCTStatStruc *pMCTstat, - struct DCTStatStruc *pDCTstatA, uint8_t Pass); -uint8_t AgesaHwWlPhase1(struct MCTStatStruc *pMCTstat, - struct DCTStatStruc *pDCTstat, u8 dct, u8 dimm, u8 pass); -uint8_t AgesaHwWlPhase2(struct MCTStatStruc *pMCTstat, - struct DCTStatStruc *pDCTstat, uint8_t dct, uint8_t dimm, uint8_t pass); -uint8_t AgesaHwWlPhase3(struct MCTStatStruc *pMCTstat, - struct DCTStatStruc *pDCTstat, u8 dct, u8 dimm, u8 pass); -void EnableZQcalibration(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstat); -void DisableZQcalibration(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstat); -void PrepareC_MCT(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstat); -void PrepareC_DCT(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstat, u8 dct); -void Restore_OnDimmMirror(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstat); -void Clear_OnDimmMirror(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstat); -void MCTMemClr_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstatA); -void mct_BeforeDQSTrainSamp(struct DCTStatStruc *pDCTstat); -void mct_ExtMCTConfig_Bx(struct DCTStatStruc *pDCTstat); -void mct_ExtMCTConfig_Cx(struct DCTStatStruc *pDCTstat); -void mct_ExtMCTConfig_Dx(struct DCTStatStruc *pDCTstat); -u32 mct_SetDramConfigMisc2(struct DCTStatStruc *pDCTstat, - uint8_t dct, uint32_t misc2, uint32_t DramControl); - -uint8_t dct_ddr_voltage_index(struct DCTStatStruc *pDCTstat, uint8_t dct); -void mct_DramControlReg_Init_D(struct MCTStatStruc *pMCTstat, - struct DCTStatStruc *pDCTstat, uint8_t dct); -void precise_ndelay_fam15(struct MCTStatStruc *pMCTstat, uint32_t nanoseconds); -void FreqChgCtrlWrd(struct MCTStatStruc *pMCTstat, - struct DCTStatStruc *pDCTstat, uint8_t dct); -u32 mct_MR1Odt_RDimm(struct MCTStatStruc *pMCTstat, - struct DCTStatStruc *pDCTstat, u8 dct, u32 MrsChipSel); -void mct_DramInit_Sw_D(struct MCTStatStruc *pMCTstat, - struct DCTStatStruc *pDCTstat, u8 dct); -void print_debug_dqs(const char *str, u32 val, u8 level); -void print_debug_dqs_pair(const char *str, u32 val, const char *str2, u32 val2, u8 level); -u8 mct_DisableDimmEccEn_D(struct MCTStatStruc *pMCTstat, - struct DCTStatStruc *pDCTstat); -void ResetDCTWrPtr_D(u32 dev, uint8_t dct, u32 index_reg, u32 index); -void Calc_SetMaxRdLatency_D_Fam15(struct MCTStatStruc *pMCTstat, - struct DCTStatStruc *pDCTstat, uint8_t dct, uint8_t calc_min); -void write_dram_dqs_training_pattern_fam15(struct MCTStatStruc *pMCTstat, - struct DCTStatStruc *pDCTstat, uint8_t dct, - uint8_t Receiver, uint8_t lane, uint8_t stop_on_error); -void read_dram_dqs_training_pattern_fam15(struct MCTStatStruc *pMCTstat, - struct DCTStatStruc *pDCTstat, uint8_t dct, - uint8_t Receiver, uint8_t lane, uint8_t stop_on_error); -void write_dqs_receiver_enable_control_registers(uint16_t *current_total_delay, uint32_t dev, uint8_t dct, uint8_t dimm, uint32_t index_reg); - -uint32_t fenceDynTraining_D(struct MCTStatStruc *pMCTstat, - struct DCTStatStruc *pDCTstat, uint8_t dct); -int32_t abs(int32_t val); -void SetTargetWTIO_D(u32 TestAddr); -void ResetTargetWTIO_D(void); -u32 mct_GetMCTSysAddr_D(struct MCTStatStruc *pMCTstat, - struct DCTStatStruc *pDCTstat, - u8 Channel, u8 receiver, u8 *valid); -void set_2t_configuration(struct MCTStatStruc *pMCTstat, - struct DCTStatStruc *pDCTstat, u8 dct); -u8 mct_BeforePlatformSpec(struct MCTStatStruc *pMCTstat, - struct DCTStatStruc *pDCTstat, u8 dct); -u8 mct_PlatformSpec(struct MCTStatStruc *pMCTstat, - struct DCTStatStruc *pDCTstat, u8 dct); -void InitPhyCompensation(struct MCTStatStruc *pMCTstat, - struct DCTStatStruc *pDCTstat, u8 dct); -u32 mct_MR1(struct MCTStatStruc *pMCTstat, - struct DCTStatStruc *pDCTstat, u8 dct, u32 MrsChipSel); -u32 mct_MR2(struct MCTStatStruc *pMCTstat, - struct DCTStatStruc *pDCTstat, u8 dct, u32 MrsChipSel); -uint8_t fam15_rttwr(struct DCTStatStruc *pDCTstat, uint8_t dct, uint8_t dimm, uint8_t rank, uint8_t package_type); -uint8_t fam15_rttnom(struct DCTStatStruc *pDCTstat, uint8_t dct, uint8_t dimm, uint8_t rank, uint8_t package_type); -uint8_t fam15_dimm_dic(struct DCTStatStruc *pDCTstat, uint8_t dct, uint8_t dimm, uint8_t rank, uint8_t package_type); -u32 mct_DramTermDyn_RDimm(struct MCTStatStruc *pMCTstat, - struct DCTStatStruc *pDCTstat, u8 dimm); - -void restore_mct_data_from_save_variable(struct amd_s3_persistent_data* persistent_data, uint8_t training_only); -#endif diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mct_d_gcc.c b/src/northbridge/amd/amdmct/mct_ddr3/mct_d_gcc.c deleted file mode 100644 index ccea732709..0000000000 --- a/src/northbridge/amd/amdmct/mct_ddr3/mct_d_gcc.c +++ /dev/null @@ -1,296 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2010 Advanced Micro Devices, Inc. - * Copyright (C) 2015 Timothy Pearson , Raptor Engineering - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include "mct_d_gcc.h" -#include -#include - -void _WRMSR(u32 addr, u32 lo, u32 hi) -{ - __asm__ volatile ( - "wrmsr" - : - :"c"(addr),"a"(lo), "d" (hi) - ); -} - -void _RDMSR(u32 addr, u32 *lo, u32 *hi) -{ - __asm__ volatile ( - "rdmsr" - :"=a"(*lo), "=d" (*hi) - :"c"(addr) - ); -} - -void _RDTSC(u32 *lo, u32 *hi) -{ - __asm__ volatile ( - "rdtsc" - : "=a" (*lo), "=d"(*hi) - ); -} - -void _cpu_id(u32 addr, u32 *val) -{ - __asm__ volatile( - "cpuid" - : "=a" (val[0]), - "=b" (val[1]), - "=c" (val[2]), - "=d" (val[3]) - : "0" (addr)); - -} - -u32 bsr(u32 x) -{ - u8 i; - u32 ret = 0; - - for (i = 31; i > 0; i--) { - if (x & (1<= 0; i--) { - val <<= 8; - valx = *(p+i); - val |= valx; - } - - return val; -} - -u8 oemNodePresent_D(u8 Node, u8 *ret) -{ - *ret = 0; - return 0; -} diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mct_d_gcc.h b/src/northbridge/amd/amdmct/mct_ddr3/mct_d_gcc.h deleted file mode 100644 index 629e6e639b..0000000000 --- a/src/northbridge/amd/amdmct/mct_ddr3/mct_d_gcc.h +++ /dev/null @@ -1,50 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2010 Advanced Micro Devices, Inc. - * Copyright (C) 2015 Timothy Pearson , Raptor Engineering - * Copyright (C) 2016 Damien Zammit - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ -#ifndef MCT_D_GCC_H -#define MCT_D_GCC_H - -#include -#include - -void _WRMSR(u32 addr, u32 lo, u32 hi); -void _RDMSR(u32 addr, u32 *lo, u32 *hi); -void _RDTSC(u32 *lo, u32 *hi); -void _cpu_id(u32 addr, u32 *val); -u32 bsr(u32 x); -u32 bsf(u32 x); -#define _MFENCE asm volatile ("mfence") -#define _SFENCE asm volatile ("sfence") - -/* prevent speculative execution of following instructions */ -#define _EXECFENCE asm volatile ("outb %al, $0xed") - -u32 SetUpperFSbase(u32 addr_hi); - -void proc_MFENCE(void); -void proc_CLFLUSH(u32 addr_hi); -void WriteLNTestPattern(u32 addr_lo, u8 *buf_a, u32 line_num); -u32 read32_fs(u32 addr_lo); -uint64_t read64_fs(uint32_t addr_lo); -void FlushDQSTestPattern_L9(u32 addr_lo); -__attribute__((noinline)) void FlushDQSTestPattern_L18(u32 addr_lo); -void ReadMaxRdLat1CLTestPattern_D(u32 addr); -void WriteMaxRdLat1CLTestPattern_D(u32 buf, u32 addr); -void FlushMaxRdLatTestPattern_D(u32 addr); -u32 stream_to_int(u8 *p); -u8 oemNodePresent_D(u8 Node, u8 *ret); - -#endif diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mctardk5.c b/src/northbridge/amd/amdmct/mct_ddr3/mctardk5.c deleted file mode 100644 index e8116340c4..0000000000 --- a/src/northbridge/amd/amdmct/mct_ddr3/mctardk5.c +++ /dev/null @@ -1,100 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2010 Advanced Micro Devices, Inc. - * Copyright (C) 2015 Timothy Pearson , Raptor Engineering - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -/* AM3/ASB2/C32/G34 DDR3 */ - -#include -#include -#include "mct_d.h" -#include "mct_d_gcc.h" - -static uint8_t is_fam15h(void) -{ - uint8_t fam15h = 0; - uint32_t family; - - family = cpuid_eax(0x80000001); - family = ((family & 0xf00000) >> 16) | ((family & 0xf00) >> 8); - - if (family >= 0x6f) - /* Family 15h or later */ - fam15h = 1; - - return fam15h; -} - -static void Get_ChannelPS_Cfg0_D(u8 MAAdimms, u8 Speed, u8 MAAload, - u32 *ODC_CTL, - u8 *CMDmode); - -void mctGet_PS_Cfg_D(struct MCTStatStruc *pMCTstat, - struct DCTStatStruc *pDCTstat, u32 dct) -{ - if (is_fam15h()) { - pDCTstat->CH_ADDR_TMG[dct] = fam15h_address_timing_compensation_code(pDCTstat, dct); - pDCTstat->CH_ODC_CTL[dct] = fam15h_output_driver_compensation_code(pDCTstat, dct); - pDCTstat->_2Tmode = fam15h_slow_access_mode(pDCTstat, dct); - } else { - Get_ChannelPS_Cfg0_D(pDCTstat->MAdimms[dct], pDCTstat->Speed, - pDCTstat->MAload[dct], - &(pDCTstat->CH_ODC_CTL[dct]), - &pDCTstat->_2Tmode); - - if (pDCTstat->Status & (1 << SB_Registered)) { - pDCTstat->_2Tmode = 1; /* Disable slow access mode */ - } - pDCTstat->CH_ADDR_TMG[dct] = fam10h_address_timing_compensation_code(pDCTstat, dct); - - pDCTstat->CH_ODC_CTL[dct] |= 0x20000000; /* 60ohms */ - } - - pDCTstat->CH_EccDQSLike[0] = 0x0403; - pDCTstat->CH_EccDQSScale[0] = 0x70; - pDCTstat->CH_EccDQSLike[1] = 0x0403; - pDCTstat->CH_EccDQSScale[1] = 0x70; -} - -/* - * In: MAAdimms - number of DIMMs on the channel - * : Speed - Speed (see DCTStatstruc.Speed for definition) - * : MAAload - number of address bus loads on the channel - * Out: AddrTmgCTL - Address Timing Control Register Value - * : ODC_CTL - Output Driver Compensation Control Register Value - * : CMDmode - CMD mode - */ -static void Get_ChannelPS_Cfg0_D(u8 MAAdimms, u8 Speed, u8 MAAload, - u32 *ODC_CTL, - u8 *CMDmode) -{ - *ODC_CTL = 0; - *CMDmode = 1; - - if (MAAdimms == 1) { - *ODC_CTL = 0x00113222; - *CMDmode = 1; - } else /* if (MAAdimms == 0) */ { - if (Speed == 4) { - *CMDmode = 1; - } else if (Speed == 5) { - *CMDmode = 1; - } else if (Speed == 6) { - *CMDmode = 2; - } else { - *CMDmode = 2; - } - *ODC_CTL = 0x00223323; - } -} diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mctardk6.c b/src/northbridge/amd/amdmct/mct_ddr3/mctardk6.c deleted file mode 100644 index d6480ab91a..0000000000 --- a/src/northbridge/amd/amdmct/mct_ddr3/mctardk6.c +++ /dev/null @@ -1,114 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2010 Advanced Micro Devices, Inc. - * Copyright (C) 2015 Timothy Pearson , Raptor Engineering - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -/* The socket type Fr2, G (1207) are not tested. - */ - -static void Get_ChannelPS_Cfg0_D(u8 MAAdimms, u8 Speed, u8 MAAload, - u8 DATAAload, u32 *AddrTmgCTL, u32 *ODC_CTL, - u8 *CMDmode); - - -void mctGet_PS_Cfg_D(struct MCTStatStruc *pMCTstat, - struct DCTStatStruc *pDCTstat, u32 dct) -{ - Get_ChannelPS_Cfg0_D(pDCTstat->MAdimms[dct], pDCTstat->Speed, - pDCTstat->MAload[dct], pDCTstat->DATAload[dct], - &(pDCTstat->CH_ADDR_TMG[dct]), &(pDCTstat->CH_ODC_CTL[dct]), - &pDCTstat->_2Tmode); - - if (pDCTstat->GangedMode == 1 && dct == 0) - Get_ChannelPS_Cfg0_D(pDCTstat->MAdimms[1], pDCTstat->Speed, - pDCTstat->MAload[1], pDCTstat->DATAload[1], - &(pDCTstat->CH_ADDR_TMG[1]), &(pDCTstat->CH_ODC_CTL[1]), - &pDCTstat->_2Tmode); - - pDCTstat->CH_EccDQSLike[0] = 0x0302; - pDCTstat->CH_EccDQSLike[1] = 0x0302; - -} - -/* - * In: MAAdimms - number of DIMMs on the channel - * : Speed - Speed (see DCTStatstruc.Speed for definition) - * : MAAload - number of address bus loads on the channel - * : DATAAload - number of ranks on the channel - * Out: AddrTmgCTL - Address Timing Control Register Value - * : ODC_CTL - Output Driver Compensation Control Register Value - * : CMDmode - CMD mode - */ -static void Get_ChannelPS_Cfg0_D(u8 MAAdimms, u8 Speed, u8 MAAload, - u8 DATAAload, u32 *AddrTmgCTL, u32 *ODC_CTL, - u8 *CMDmode) -{ - *AddrTmgCTL = 0; - *ODC_CTL = 0; - *CMDmode = 1; - - if (mctGet_NVbits(NV_MAX_DIMMS) == 4) { - if (Speed == 4) { - *AddrTmgCTL = 0x00000000; - } else if (Speed == 5) { - *AddrTmgCTL = 0x003C3C3C; - if (MAAdimms > 1) - *AddrTmgCTL = 0x003A3C3A; - } else if (Speed == 6) { - if (MAAdimms == 1) - *AddrTmgCTL = 0x003A3A3A; - else - *AddrTmgCTL = 0x00383A38; - } else { - if (MAAdimms == 1) - *AddrTmgCTL = 0x00373937; - else - *AddrTmgCTL = 0x00353935; - } - } else { - if (Speed == 4) { - *AddrTmgCTL = 0x00000000; - if (MAAdimms == 3) - *AddrTmgCTL = 0x00380038; - } else if (Speed == 5) { - if (MAAdimms == 1) - *AddrTmgCTL = 0x003C3C3C; - else if (MAAdimms == 2) - *AddrTmgCTL = 0x003A3C3A; - else - *AddrTmgCTL = 0x00373C37; - } else if (Speed == 6) { - if (MAAdimms == 1) - *AddrTmgCTL = 0x003A3A3A; - else if (MAAdimms == 2) - *AddrTmgCTL = 0x00383A38; - else - *AddrTmgCTL = 0x00343A34; - } else { - if (MAAdimms == 1) - *AddrTmgCTL = 0x00393939; - else if (MAAdimms == 2) - *AddrTmgCTL = 0x00363936; - else - *AddrTmgCTL = 0x00303930; - } - } - - if ((MAAdimms == 1) && (MAAload < 4)) - *ODC_CTL = 0x20113222; - else - *ODC_CTL = 0x20223222; - - *CMDmode = 1; -} diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mctchi_d.c b/src/northbridge/amd/amdmct/mct_ddr3/mctchi_d.c deleted file mode 100644 index d458f3a48e..0000000000 --- a/src/northbridge/amd/amdmct/mct_ddr3/mctchi_d.c +++ /dev/null @@ -1,123 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2010 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include "mct_d.h" -#include "mct_d_gcc.h" -#include - -void InterleaveChannels_D(struct MCTStatStruc *pMCTstat, - struct DCTStatStruc *pDCTstatA) -{ - - u8 Node; - u32 DramBase, DctSelBase; - u8 DctSelIntLvAddr, DctSelHi; - u8 HoleValid = 0; - u32 HoleSize, HoleBase = 0; - u32 val, tmp; - u32 dct0_size, dct1_size; - struct DCTStatStruc *pDCTstat; - - /* HoleValid - indicates whether the current Node contains hole. - * HoleSize - indicates whether there is IO hole in the whole system - * memory. - */ - - /* call back to wrapper not needed ManualChannelInterleave_D(); */ - /* call back - DctSelIntLvAddr = mctGet_NVbits(NV_ChannelIntlv);*/ /* override interleave */ - /* Manually set: typ = 5, otherwise typ = 7. */ - DctSelIntLvAddr = mctGet_NVbits(NV_ChannelIntlv); /* typ = 5: Hash*: exclusive OR of address bits[20:16, 6]. */ - - if (DctSelIntLvAddr & 1) { - DctSelIntLvAddr >>= 1; - HoleSize = 0; - if ((pMCTstat->GStatus & (1 << GSB_SoftHole)) || - (pMCTstat->GStatus & (1 << GSB_HWHole))) { - if (pMCTstat->HoleBase) { - HoleBase = pMCTstat->HoleBase >> 8; - HoleSize = HoleBase & 0xFFFF0000; - HoleSize |= ((~HoleBase) + 1) & 0xFFFF; - } - } - Node = 0; - while (Node < MAX_NODES_SUPPORTED) { - pDCTstat = pDCTstatA + Node; - val = Get_NB32(pDCTstat->dev_map, 0xF0); - if (val & (1 << DramHoleValid)) - HoleValid = 1; - if (!pDCTstat->GangedMode && pDCTstat->DIMMValidDCT[0] && pDCTstat->DIMMValidDCT[1]) { - DramBase = pDCTstat->NodeSysBase >> 8; - dct1_size = ((pDCTstat->NodeSysLimit) + 2) >> 8; - dct0_size = Get_NB32(pDCTstat->dev_dct, 0x114); - if (dct0_size >= 0x10000) { - dct0_size -= HoleSize; - } - - dct0_size -= DramBase; - dct1_size -= dct0_size; - DctSelHi = 0x05; /* DctSelHiRngEn = 1, DctSelHi = 0 */ - if (dct1_size == dct0_size) { - dct1_size = 0; - DctSelHi = 0x04; /* DctSelHiRngEn = 0 */ - } else if (dct1_size > dct0_size) { - dct1_size = dct0_size; - DctSelHi = 0x07; /* DctSelHiRngEn = 1, DctSelHi = 1 */ - } - dct0_size = dct1_size; - dct0_size += DramBase; - dct0_size += dct1_size; - if (dct0_size >= HoleBase) /* if DctSelBaseAddr > HoleBase */ - dct0_size += HoleSize; - DctSelBase = dct0_size; - - if (dct1_size == 0) - dct0_size = 0; - dct0_size -= dct1_size; /* DctSelBaseOffset = DctSelBaseAddr - Interleaved region */ - Set_NB32(pDCTstat->dev_dct, 0x114, dct0_size); - - if (dct1_size == 0) - dct1_size = DctSelBase; - val = Get_NB32(pDCTstat->dev_dct, 0x110); - val &= 0x7F8; - val |= dct1_size; - val |= DctSelHi; - val |= (DctSelIntLvAddr << 6) & 0xFF; - Set_NB32(pDCTstat->dev_dct, 0x110, val); - - if (HoleValid) { - tmp = DramBase; - val = DctSelBase; - if (val < HoleBase) { /* DctSelBaseAddr < DramHoleBase */ - val -= DramBase; - val >>= 1; - tmp += val; - } - tmp += HoleSize; - val = Get_NB32(pDCTstat->dev_map, 0xF0); /* DramHoleOffset */ - val &= 0xFFFF007F; - val |= (tmp & ~0xFFFF007F); - Set_NB32(pDCTstat->dev_map, 0xF0, val); - } - } - printk(BIOS_DEBUG, "InterleaveChannels_D: Node %x\n", Node); - printk(BIOS_DEBUG, "InterleaveChannels_D: Status %x\n", pDCTstat->Status); - printk(BIOS_DEBUG, "InterleaveChannels_D: ErrStatus %x\n", pDCTstat->ErrStatus); - printk(BIOS_DEBUG, "InterleaveChannels_D: ErrCode %x\n", pDCTstat->ErrCode); - Node++; - } - } - printk(BIOS_DEBUG, "InterleaveChannels_D: Done\n\n"); -} diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mctcsi_d.c b/src/northbridge/amd/amdmct/mct_ddr3/mctcsi_d.c deleted file mode 100644 index 85e7930b24..0000000000 --- a/src/northbridge/amd/amdmct/mct_ddr3/mctcsi_d.c +++ /dev/null @@ -1,144 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2010 Advanced Micro Devices, Inc. - * Copyright (C) 2015 Timothy Pearson , Raptor Engineering - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -/* Low swap bit vs bank size encoding (physical, not logical address bit) - * ;To calculate the number by hand, add the number of Bank address bits - * ;(2 or 3) to the number of column address bits, plus 3 (the logical - * ;page size), and subtract 8. - */ - -#include -#include "mct_d.h" -#include "mct_d_gcc.h" -#include - -static const u8 Tab_int_D[] = {6,7,7,8,8,8,8,8,9,9,8,9}; - -void InterleaveBanks_D(struct MCTStatStruc *pMCTstat, - struct DCTStatStruc *pDCTstat, u8 dct) -{ - u8 ChipSel, EnChipSels; - u32 AddrLoMask, AddrHiMask; - u32 AddrLoMaskN, AddrHiMaskN, MemSize = 0; - u8 DoIntlv, _CsIntCap; - u32 BitDelta, BankEncd = 0; - - u32 dev; - u32 reg; - u32 val; - u32 val_lo, val_hi; - - DoIntlv = mctGet_NVbits(NV_BankIntlv); - _CsIntCap = 0; - EnChipSels = 0; - - dev = pDCTstat->dev_dct; - - ChipSel = 0; /* Find out if current configuration is capable */ - while (DoIntlv && (ChipSel < MAX_CS_SUPPORTED)) { - reg = 0x40+(ChipSel<<2); /* Dram CS Base 0 */ - val = Get_NB32_DCT(dev, dct, reg); - if (val & (1<>1)<<2); /*Dram CS Mask 0 */ - val = Get_NB32_DCT(dev, dct, reg); - val >>= 19; - val &= 0x3ff; - val++; - if (EnChipSels == 1) - MemSize = val; - else - /*If mask sizes not same then skip */ - if (val != MemSize) - break; - reg = 0x80; /*Dram Bank Addressing */ - val = Get_NB32_DCT(dev, dct, reg); - val >>= (ChipSel>>1)<<2; - val &= 0x0f; - if (EnChipSels == 1) - BankEncd = val; - else - /*If number of Rows/Columns not equal, skip */ - if (val != BankEncd) - break; - } - ChipSel++; - } - if (ChipSel == MAX_CS_SUPPORTED) { - if ((EnChipSels == 2) || (EnChipSels == 4) || (EnChipSels == 8)) - _CsIntCap = 1; - } - - if (DoIntlv) { - if (!_CsIntCap) { - pDCTstat->ErrStatus |= 1<Status & (1<>= BitDelta; - val |= val_lo; - val |= val_hi; - Set_NB32_DCT(dev, dct, reg, val); - - if (ChipSel & 1) - continue; - - reg = 0x60 + ((ChipSel>>1)<<2); /* Dram CS Mask 0 */ - val = Get_NB32_DCT(dev, dct, reg); - val_lo = val & AddrLoMask; - val_hi = val & AddrHiMask; - val &= AddrLoMaskN; - val &= AddrHiMaskN; - val_lo <<= BitDelta; - val_hi >>= BitDelta; - val |= val_lo; - val |= val_hi; - Set_NB32_DCT(dev, dct, reg, val); - } - } - } /* DoIntlv */ - - /* dump_pci_device(PCI_DEV(0, 0x18+pDCTstat->Node_ID, 2)); */ - - printk(BIOS_DEBUG, "InterleaveBanks_D: Status %x\n", pDCTstat->Status); - printk(BIOS_DEBUG, "InterleaveBanks_D: ErrStatus %x\n", pDCTstat->ErrStatus); - printk(BIOS_DEBUG, "InterleaveBanks_D: ErrCode %x\n", pDCTstat->ErrCode); - printk(BIOS_DEBUG, "InterleaveBanks_D: Done\n\n"); -} diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c b/src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c deleted file mode 100644 index d34b2dc2ba..0000000000 --- a/src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c +++ /dev/null @@ -1,2493 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2010 Advanced Micro Devices, Inc. - * Copyright (C) 2015 - 2016 Raptor Engineering, LLC - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include -#include -#include -#include -#include -#include "mct_d.h" -#include "mct_d_gcc.h" - -static void CalcEccDQSPos_D(struct MCTStatStruc *pMCTstat, - struct DCTStatStruc *pDCTstat, u16 like, - u8 scale, u8 ChipSel); -static void GetDQSDatStrucVal_D(struct MCTStatStruc *pMCTstat, - struct DCTStatStruc *pDCTstat, u8 ChipSel); -static void WriteDQSTestPattern_D(struct MCTStatStruc *pMCTstat, - struct DCTStatStruc *pDCTstat, - u32 TestAddr_lo); -static void WriteL18TestPattern_D(struct DCTStatStruc *pDCTstat, - u32 TestAddr_lo); -static void WriteL9TestPattern_D(struct DCTStatStruc *pDCTstat, - u32 TestAddr_lo); -static u16 CompareDQSTestPattern_D(struct MCTStatStruc *pMCTstat, - struct DCTStatStruc *pDCTstat, - u32 addr_lo); -static void FlushDQSTestPattern_D(struct DCTStatStruc *pDCTstat, - u32 addr_lo); -static void mct_SetDQSDelayCSR_D(struct MCTStatStruc *pMCTstat, - struct DCTStatStruc *pDCTstat, - u8 ChipSel); -static void SetupDqsPattern_D(struct MCTStatStruc *pMCTstat, - struct DCTStatStruc *pDCTstat, - u32 *buffer); - -static void StoreDQSDatStrucVal_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstat, u8 ChipSel); - -static uint8_t is_fam15h(void) -{ - uint8_t fam15h = 0; - uint32_t family; - - family = cpuid_eax(0x80000001); - family = ((family & 0xf00000) >> 16) | ((family & 0xf00) >> 8); - - if (family >= 0x6f) - /* Family 15h or later */ - fam15h = 1; - - return fam15h; -} - -#define DQS_TRAIN_DEBUG 0 -// #define PRINT_PASS_FAIL_BITMAPS 1 - -void print_debug_dqs(const char *str, u32 val, u8 level) -{ -#if DQS_TRAIN_DEBUG > 0 - if (DQS_TRAIN_DEBUG >= level) { - printk(BIOS_DEBUG, "%s%x\n", str, val); - } -#endif -} - -void print_debug_dqs_pair(const char *str, u32 val, const char *str2, u32 val2, u8 level) -{ -#if DQS_TRAIN_DEBUG > 0 - if (DQS_TRAIN_DEBUG >= level) { - printk(BIOS_DEBUG, "%s%08x%s%08x\n", str, val, str2, val2); - } -#endif -} - -/*Warning: These must be located so they do not cross a logical 16-bit segment boundary!*/ -static const u32 TestPatternJD1a_D[] = { - 0x00000000,0x00000000,0xFFFFFFFF,0xFFFFFFFF, /* QW0-1, ALL-EVEN */ - 0x00000000,0x00000000,0x00000000,0x00000000, /* QW2-3, ALL-EVEN */ - 0x00000000,0x00000000,0xFFFFFFFF,0xFFFFFFFF, /* QW4-5, ALL-EVEN */ - 0x00000000,0x00000000,0x00000000,0x00000000, /* QW6-7, ALL-EVEN */ - 0xFeFeFeFe,0xFeFeFeFe,0x01010101,0x01010101, /* QW0-1, DQ0-ODD */ - 0xFeFeFeFe,0xFeFeFeFe,0x01010101,0x01010101, /* QW2-3, DQ0-ODD */ - 0x01010101,0x01010101,0xFeFeFeFe,0xFeFeFeFe, /* QW4-5, DQ0-ODD */ - 0xFeFeFeFe,0xFeFeFeFe,0x01010101,0x01010101, /* QW6-7, DQ0-ODD */ - 0x02020202,0x02020202,0x02020202,0x02020202, /* QW0-1, DQ1-ODD */ - 0xFdFdFdFd,0xFdFdFdFd,0xFdFdFdFd,0xFdFdFdFd, /* QW2-3, DQ1-ODD */ - 0xFdFdFdFd,0xFdFdFdFd,0x02020202,0x02020202, /* QW4-5, DQ1-ODD */ - 0x02020202,0x02020202,0x02020202,0x02020202, /* QW6-7, DQ1-ODD */ - 0x04040404,0x04040404,0xfBfBfBfB,0xfBfBfBfB, /* QW0-1, DQ2-ODD */ - 0x04040404,0x04040404,0x04040404,0x04040404, /* QW2-3, DQ2-ODD */ - 0xfBfBfBfB,0xfBfBfBfB,0xfBfBfBfB,0xfBfBfBfB, /* QW4-5, DQ2-ODD */ - 0xfBfBfBfB,0xfBfBfBfB,0xfBfBfBfB,0xfBfBfBfB, /* QW6-7, DQ2-ODD */ - 0x08080808,0x08080808,0xF7F7F7F7,0xF7F7F7F7, /* QW0-1, DQ3-ODD */ - 0x08080808,0x08080808,0x08080808,0x08080808, /* QW2-3, DQ3-ODD */ - 0xF7F7F7F7,0xF7F7F7F7,0x08080808,0x08080808, /* QW4-5, DQ3-ODD */ - 0xF7F7F7F7,0xF7F7F7F7,0xF7F7F7F7,0xF7F7F7F7, /* QW6-7, DQ3-ODD */ - 0x10101010,0x10101010,0x10101010,0x10101010, /* QW0-1, DQ4-ODD */ - 0xeFeFeFeF,0xeFeFeFeF,0x10101010,0x10101010, /* QW2-3, DQ4-ODD */ - 0xeFeFeFeF,0xeFeFeFeF,0xeFeFeFeF,0xeFeFeFeF, /* QW4-5, DQ4-ODD */ - 0xeFeFeFeF,0xeFeFeFeF,0x10101010,0x10101010, /* QW6-7, DQ4-ODD */ - 0xdFdFdFdF,0xdFdFdFdF,0xdFdFdFdF,0xdFdFdFdF, /* QW0-1, DQ5-ODD */ - 0xdFdFdFdF,0xdFdFdFdF,0x20202020,0x20202020, /* QW2-3, DQ5-ODD */ - 0xdFdFdFdF,0xdFdFdFdF,0xdFdFdFdF,0xdFdFdFdF, /* QW4-5, DQ5-ODD */ - 0xdFdFdFdF,0xdFdFdFdF,0xdFdFdFdF,0xdFdFdFdF, /* QW6-7, DQ5-ODD */ - 0xBfBfBfBf,0xBfBfBfBf,0xBfBfBfBf,0xBfBfBfBf, /* QW0-1, DQ6-ODD */ - 0x40404040,0x40404040,0xBfBfBfBf,0xBfBfBfBf, /* QW2-3, DQ6-ODD */ - 0x40404040,0x40404040,0xBfBfBfBf,0xBfBfBfBf, /* QW4-5, DQ6-ODD */ - 0x40404040,0x40404040,0xBfBfBfBf,0xBfBfBfBf, /* QW6-7, DQ6-ODD */ - 0x80808080,0x80808080,0x7F7F7F7F,0x7F7F7F7F, /* QW0-1, DQ7-ODD */ - 0x80808080,0x80808080,0x7F7F7F7F,0x7F7F7F7F, /* QW2-3, DQ7-ODD */ - 0x80808080,0x80808080,0x7F7F7F7F,0x7F7F7F7F, /* QW4-5, DQ7-ODD */ - 0x80808080,0x80808080,0x80808080,0x80808080 /* QW6-7, DQ7-ODD */ -}; -static const u32 TestPatternJD1b_D[] = { - 0x00000000,0x00000000,0x00000000,0x00000000, /* QW0,CHA-B, ALL-EVEN */ - 0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF, /* QW1,CHA-B, ALL-EVEN */ - 0x00000000,0x00000000,0x00000000,0x00000000, /* QW2,CHA-B, ALL-EVEN */ - 0x00000000,0x00000000,0x00000000,0x00000000, /* QW3,CHA-B, ALL-EVEN */ - 0x00000000,0x00000000,0x00000000,0x00000000, /* QW4,CHA-B, ALL-EVEN */ - 0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF, /* QW5,CHA-B, ALL-EVEN */ - 0x00000000,0x00000000,0x00000000,0x00000000, /* QW6,CHA-B, ALL-EVEN */ - 0x00000000,0x00000000,0x00000000,0x00000000, /* QW7,CHA-B, ALL-EVEN */ - 0xFeFeFeFe,0xFeFeFeFe,0xFeFeFeFe,0xFeFeFeFe, /* QW0,CHA-B, DQ0-ODD */ - 0x01010101,0x01010101,0x01010101,0x01010101, /* QW1,CHA-B, DQ0-ODD */ - 0xFeFeFeFe,0xFeFeFeFe,0xFeFeFeFe,0xFeFeFeFe, /* QW2,CHA-B, DQ0-ODD */ - 0x01010101,0x01010101,0x01010101,0x01010101, /* QW3,CHA-B, DQ0-ODD */ - 0x01010101,0x01010101,0x01010101,0x01010101, /* QW4,CHA-B, DQ0-ODD */ - 0xFeFeFeFe,0xFeFeFeFe,0xFeFeFeFe,0xFeFeFeFe, /* QW5,CHA-B, DQ0-ODD */ - 0xFeFeFeFe,0xFeFeFeFe,0xFeFeFeFe,0xFeFeFeFe, /* QW6,CHA-B, DQ0-ODD */ - 0x01010101,0x01010101,0x01010101,0x01010101, /* QW7,CHA-B, DQ0-ODD */ - 0x02020202,0x02020202,0x02020202,0x02020202, /* QW0,CHA-B, DQ1-ODD */ - 0x02020202,0x02020202,0x02020202,0x02020202, /* QW1,CHA-B, DQ1-ODD */ - 0xFdFdFdFd,0xFdFdFdFd,0xFdFdFdFd,0xFdFdFdFd, /* QW2,CHA-B, DQ1-ODD */ - 0xFdFdFdFd,0xFdFdFdFd,0xFdFdFdFd,0xFdFdFdFd, /* QW3,CHA-B, DQ1-ODD */ - 0xFdFdFdFd,0xFdFdFdFd,0xFdFdFdFd,0xFdFdFdFd, /* QW4,CHA-B, DQ1-ODD */ - 0x02020202,0x02020202,0x02020202,0x02020202, /* QW5,CHA-B, DQ1-ODD */ - 0x02020202,0x02020202,0x02020202,0x02020202, /* QW6,CHA-B, DQ1-ODD */ - 0x02020202,0x02020202,0x02020202,0x02020202, /* QW7,CHA-B, DQ1-ODD */ - 0x04040404,0x04040404,0x04040404,0x04040404, /* QW0,CHA-B, DQ2-ODD */ - 0xfBfBfBfB,0xfBfBfBfB,0xfBfBfBfB,0xfBfBfBfB, /* QW1,CHA-B, DQ2-ODD */ - 0x04040404,0x04040404,0x04040404,0x04040404, /* QW2,CHA-B, DQ2-ODD */ - 0x04040404,0x04040404,0x04040404,0x04040404, /* QW3,CHA-B, DQ2-ODD */ - 0xfBfBfBfB,0xfBfBfBfB,0xfBfBfBfB,0xfBfBfBfB, /* QW4,CHA-B, DQ2-ODD */ - 0xfBfBfBfB,0xfBfBfBfB,0xfBfBfBfB,0xfBfBfBfB, /* QW5,CHA-B, DQ2-ODD */ - 0xfBfBfBfB,0xfBfBfBfB,0xfBfBfBfB,0xfBfBfBfB, /* QW6,CHA-B, DQ2-ODD */ - 0xfBfBfBfB,0xfBfBfBfB,0xfBfBfBfB,0xfBfBfBfB, /* QW7,CHA-B, DQ2-ODD */ - 0x08080808,0x08080808,0x08080808,0x08080808, /* QW0,CHA-B, DQ3-ODD */ - 0xF7F7F7F7,0xF7F7F7F7,0xF7F7F7F7,0xF7F7F7F7, /* QW1,CHA-B, DQ3-ODD */ - 0x08080808,0x08080808,0x08080808,0x08080808, /* QW2,CHA-B, DQ3-ODD */ - 0x08080808,0x08080808,0x08080808,0x08080808, /* QW3,CHA-B, DQ3-ODD */ - 0xF7F7F7F7,0xF7F7F7F7,0xF7F7F7F7,0xF7F7F7F7, /* QW4,CHA-B, DQ3-ODD */ - 0x08080808,0x08080808,0x08080808,0x08080808, /* QW5,CHA-B, DQ3-ODD */ - 0xF7F7F7F7,0xF7F7F7F7,0xF7F7F7F7,0xF7F7F7F7, /* QW6,CHA-B, DQ3-ODD */ - 0xF7F7F7F7,0xF7F7F7F7,0xF7F7F7F7,0xF7F7F7F7, /* QW7,CHA-B, DQ3-ODD */ - 0x10101010,0x10101010,0x10101010,0x10101010, /* QW0,CHA-B, DQ4-ODD */ - 0x10101010,0x10101010,0x10101010,0x10101010, /* QW1,CHA-B, DQ4-ODD */ - 0xeFeFeFeF,0xeFeFeFeF,0xeFeFeFeF,0xeFeFeFeF, /* QW2,CHA-B, DQ4-ODD */ - 0x10101010,0x10101010,0x10101010,0x10101010, /* QW3,CHA-B, DQ4-ODD */ - 0xeFeFeFeF,0xeFeFeFeF,0xeFeFeFeF,0xeFeFeFeF, /* QW4,CHA-B, DQ4-ODD */ - 0xeFeFeFeF,0xeFeFeFeF,0xeFeFeFeF,0xeFeFeFeF, /* QW5,CHA-B, DQ4-ODD */ - 0xeFeFeFeF,0xeFeFeFeF,0xeFeFeFeF,0xeFeFeFeF, /* QW6,CHA-B, DQ4-ODD */ - 0x10101010,0x10101010,0x10101010,0x10101010, /* QW7,CHA-B, DQ4-ODD */ - 0xdFdFdFdF,0xdFdFdFdF,0xdFdFdFdF,0xdFdFdFdF, /* QW0,CHA-B, DQ5-ODD */ - 0xdFdFdFdF,0xdFdFdFdF,0xdFdFdFdF,0xdFdFdFdF, /* QW1,CHA-B, DQ5-ODD */ - 0xdFdFdFdF,0xdFdFdFdF,0xdFdFdFdF,0xdFdFdFdF, /* QW2,CHA-B, DQ5-ODD */ - 0x20202020,0x20202020,0x20202020,0x20202020, /* QW3,CHA-B, DQ5-ODD */ - 0xdFdFdFdF,0xdFdFdFdF,0xdFdFdFdF,0xdFdFdFdF, /* QW4,CHA-B, DQ5-ODD */ - 0xdFdFdFdF,0xdFdFdFdF,0xdFdFdFdF,0xdFdFdFdF, /* QW5,CHA-B, DQ5-ODD */ - 0xdFdFdFdF,0xdFdFdFdF,0xdFdFdFdF,0xdFdFdFdF, /* QW6,CHA-B, DQ5-ODD */ - 0xdFdFdFdF,0xdFdFdFdF,0xdFdFdFdF,0xdFdFdFdF, /* QW7,CHA-B, DQ5-ODD */ - 0xBfBfBfBf,0xBfBfBfBf,0xBfBfBfBf,0xBfBfBfBf, /* QW0,CHA-B, DQ6-ODD */ - 0xBfBfBfBf,0xBfBfBfBf,0xBfBfBfBf,0xBfBfBfBf, /* QW1,CHA-B, DQ6-ODD */ - 0x40404040,0x40404040,0x40404040,0x40404040, /* QW2,CHA-B, DQ6-ODD */ - 0xBfBfBfBf,0xBfBfBfBf,0xBfBfBfBf,0xBfBfBfBf, /* QW3,CHA-B, DQ6-ODD */ - 0x40404040,0x40404040,0x40404040,0x40404040, /* QW4,CHA-B, DQ6-ODD */ - 0xBfBfBfBf,0xBfBfBfBf,0xBfBfBfBf,0xBfBfBfBf, /* QW5,CHA-B, DQ6-ODD */ - 0x40404040,0x40404040,0x40404040,0x40404040, /* QW6,CHA-B, DQ6-ODD */ - 0xBfBfBfBf,0xBfBfBfBf,0xBfBfBfBf,0xBfBfBfBf, /* QW7,CHA-B, DQ6-ODD */ - 0x80808080,0x80808080,0x80808080,0x80808080, /* QW0,CHA-B, DQ7-ODD */ - 0x7F7F7F7F,0x7F7F7F7F,0x7F7F7F7F,0x7F7F7F7F, /* QW1,CHA-B, DQ7-ODD */ - 0x80808080,0x80808080,0x80808080,0x80808080, /* QW2,CHA-B, DQ7-ODD */ - 0x7F7F7F7F,0x7F7F7F7F,0x7F7F7F7F,0x7F7F7F7F, /* QW3,CHA-B, DQ7-ODD */ - 0x80808080,0x80808080,0x80808080,0x80808080, /* QW4,CHA-B, DQ7-ODD */ - 0x7F7F7F7F,0x7F7F7F7F,0x7F7F7F7F,0x7F7F7F7F, /* QW5,CHA-B, DQ7-ODD */ - 0x80808080,0x80808080,0x80808080,0x80808080, /* QW6,CHA-B, DQ7-ODD */ - 0x80808080,0x80808080,0x80808080,0x80808080 /* QW7,CHA-B, DQ7-ODD */ -}; - -void TrainReceiverEn_D(struct MCTStatStruc *pMCTstat, - struct DCTStatStruc *pDCTstatA, u8 Pass) -{ - u8 Node; - struct DCTStatStruc *pDCTstat; - u32 val; - - for (Node = 0; Node < MAX_NODES_SUPPORTED; Node++) { - pDCTstat = pDCTstatA + Node; - - if (pDCTstat->DCTSysLimit) { - if (!is_fam15h()) { - val = Get_NB32_DCT(pDCTstat->dev_dct, 0, 0x78); - val |= 1 <dev_dct, 0, 0x78, val); - val = Get_NB32_DCT(pDCTstat->dev_dct, 1, 0x78); - val |= 1 <dev_dct, 1, 0x78, val); - } - mct_TrainRcvrEn_D(pMCTstat, pDCTstat, Pass); - } - } -} - -void TrainMaxRdLatency_En_D(struct MCTStatStruc *pMCTstat, - struct DCTStatStruc *pDCTstatA) -{ - uint8_t node; - struct DCTStatStruc *pDCTstat; - - for (node = 0; node < MAX_NODES_SUPPORTED; node++) { - pDCTstat = pDCTstatA + node; - - if (pDCTstat->DCTSysLimit) { - if (is_fam15h()) { - dqsTrainMaxRdLatency_SW_Fam15(pMCTstat, pDCTstat); - } else { - /* FIXME - * Implement Family 10h MaxRdLatency training - */ - } - } - } -} - -static void SetEccDQSRdWrPos_D_Fam10(struct MCTStatStruc *pMCTstat, - struct DCTStatStruc *pDCTstat, u8 ChipSel) -{ - u8 channel; - u8 direction; - - for (channel = 0; channel < 2; channel++) { - for (direction = 0; direction < 2; direction++) { - pDCTstat->Channel = channel; /* Channel A or B */ - pDCTstat->Direction = direction; /* Read or write */ - CalcEccDQSPos_D(pMCTstat, pDCTstat, pDCTstat->CH_EccDQSLike[channel], pDCTstat->CH_EccDQSScale[channel], ChipSel); - print_debug_dqs_pair("\t\tSetEccDQSRdWrPos: channel ", channel, direction == DQS_READDIR? " R dqs_delay":" W dqs_delay", pDCTstat->DQSDelay, 2); - pDCTstat->ByteLane = 8; - StoreDQSDatStrucVal_D(pMCTstat, pDCTstat, ChipSel); - mct_SetDQSDelayCSR_D(pMCTstat, pDCTstat, ChipSel); - } - } -} - -static void CalcEccDQSPos_D(struct MCTStatStruc *pMCTstat, - struct DCTStatStruc *pDCTstat, - u16 like, u8 scale, u8 ChipSel) -{ - uint8_t DQSDelay0, DQSDelay1; - int16_t delay_differential; - uint16_t DQSDelay; - - if (pDCTstat->Status & (1 << SB_Registered)) { - pDCTstat->ByteLane = 0x2; - GetDQSDatStrucVal_D(pMCTstat, pDCTstat, ChipSel); - DQSDelay0 = pDCTstat->DQSDelay; - - pDCTstat->ByteLane = 0x3; - GetDQSDatStrucVal_D(pMCTstat, pDCTstat, ChipSel); - DQSDelay1 = pDCTstat->DQSDelay; - - if (pDCTstat->Direction == DQS_READDIR) { - DQSDelay = DQSDelay1; - } else { - delay_differential = (int16_t)DQSDelay1 - (int16_t)DQSDelay0; - delay_differential += (int16_t)DQSDelay1; - - DQSDelay = delay_differential; - } - } else { - pDCTstat->ByteLane = like & 0xff; - GetDQSDatStrucVal_D(pMCTstat, pDCTstat, ChipSel); - DQSDelay0 = pDCTstat->DQSDelay; - - pDCTstat->ByteLane = (like >> 8) & 0xff; - GetDQSDatStrucVal_D(pMCTstat, pDCTstat, ChipSel); - DQSDelay1 = pDCTstat->DQSDelay; - - if (DQSDelay0 > DQSDelay1) { - DQSDelay = DQSDelay0 - DQSDelay1; - } else { - DQSDelay = DQSDelay1 - DQSDelay0; - } - - DQSDelay = DQSDelay * (~scale); - - DQSDelay += 0x80; /* round it */ - - DQSDelay >>= 8; /* 256 */ - - if (DQSDelay0 > DQSDelay1) { - DQSDelay = DQSDelay1 - DQSDelay; - } else { - DQSDelay += DQSDelay1; - } - } - - pDCTstat->DQSDelay = (u8)DQSDelay; -} - -static void read_dqs_write_data_timing_registers(uint16_t *delay, uint32_t dev, uint8_t dct, uint8_t dimm, uint32_t index_reg) -{ - uint32_t dword; - uint32_t mask; - - if (is_fam15h()) - mask = 0xff; - else - mask = 0x7f; - - /* Lanes 0 - 3 */ - dword = Get_NB32_index_wait_DCT(dev, dct, index_reg, 0x1 | (dimm << 8)); - delay[3] = (dword >> 24) & mask; - delay[2] = (dword >> 16) & mask; - delay[1] = (dword >> 8) & mask; - delay[0] = dword & mask; - - /* Lanes 4 - 7 */ - dword = Get_NB32_index_wait_DCT(dev, dct, index_reg, 0x2 | (dimm << 8)); - delay[7] = (dword >> 24) & mask; - delay[6] = (dword >> 16) & mask; - delay[5] = (dword >> 8) & mask; - delay[4] = dword & mask; - - /* Lane 8 (ECC) */ - dword = Get_NB32_index_wait_DCT(dev, dct, index_reg, 0x3 | (dimm << 8)); - delay[8] = dword & mask; -} - -static void write_dqs_write_data_timing_registers(uint16_t *delay, uint32_t dev, uint8_t dct, uint8_t dimm, uint32_t index_reg) -{ - uint32_t dword; - uint32_t mask; - - if (is_fam15h()) - mask = 0xff; - else - mask = 0x7f; - - /* Lanes 0 - 3 */ - dword = Get_NB32_index_wait_DCT(dev, dct, index_reg, 0x1 | (dimm << 8)); - dword &= ~(mask << 24); - dword &= ~(mask << 16); - dword &= ~(mask << 8); - dword &= ~mask; - dword |= (delay[3] & mask) << 24; - dword |= (delay[2] & mask) << 16; - dword |= (delay[1] & mask) << 8; - dword |= delay[0] & mask; - Set_NB32_index_wait_DCT(dev, dct, index_reg, 0x1 | (dimm << 8), dword); - - /* Lanes 4 - 7 */ - dword = Get_NB32_index_wait_DCT(dev, dct, index_reg, 0x2 | (dimm << 8)); - dword &= ~(mask << 24); - dword &= ~(mask << 16); - dword &= ~(mask << 8); - dword &= ~mask; - dword |= (delay[7] & mask) << 24; - dword |= (delay[6] & mask) << 16; - dword |= (delay[5] & mask) << 8; - dword |= delay[4] & mask; - Set_NB32_index_wait_DCT(dev, dct, index_reg, 0x2 | (dimm << 8), dword); - - /* Lane 8 (ECC) */ - dword = Get_NB32_index_wait_DCT(dev, dct, index_reg, 0x3 | (dimm << 8)); - dword &= ~mask; - dword |= delay[8] & mask; - Set_NB32_index_wait_DCT(dev, dct, index_reg, 0x3 | (dimm << 8), dword); -} - -/* DQS Position Training - * Algorithm detailed in the Fam10h BKDG Rev. 3.62 section 2.8.9.9.3 - */ -static void TrainDQSRdWrPos_D_Fam10(struct MCTStatStruc *pMCTstat, - struct DCTStatStruc *pDCTstat) -{ - u32 Errors; - u8 Channel; - u8 Receiver; - u8 _DisableDramECC = 0; - u32 PatternBuffer[304]; /* 288 + 16 */ - u8 _Wrap32Dis = 0, _SSE2 = 0; - - u32 dev; - u32 addr; - u8 valid; - CRx_TYPE cr4; - u32 lo, hi; - u32 index_reg; - uint32_t TestAddr; - - uint8_t dual_rank; - uint8_t iter; - uint8_t lane; - uint16_t bytelane_test_results; - uint16_t current_write_dqs_delay[MAX_BYTE_LANES]; - uint16_t current_read_dqs_delay[MAX_BYTE_LANES]; - uint16_t write_dqs_delay_stepping_done[MAX_BYTE_LANES]; - uint8_t dqs_read_results_array[2][MAX_BYTE_LANES][64]; /* [rank][lane][step] */ - uint8_t dqs_write_results_array[2][MAX_BYTE_LANES][128]; /* [rank][lane][step] */ - - uint8_t last_pos = 0; - uint8_t cur_count = 0; - uint8_t best_pos = 0; - uint8_t best_count = 0; - - print_debug_dqs("\nTrainDQSRdWrPos: Node_ID ", pDCTstat->Node_ID, 0); - cr4 = read_cr4(); - if (cr4 & (1<<9)) { - _SSE2 = 1; - } - cr4 |= (1<<9); /* OSFXSR enable SSE2 */ - write_cr4(cr4); - - addr = HWCR_MSR; - _RDMSR(addr, &lo, &hi); - if (lo & (1<<17)) { - _Wrap32Dis = 1; - } - lo |= (1<<17); /* HWCR.wrap32dis */ - _WRMSR(addr, lo, hi); /* allow 64-bit memory references in real mode */ - - /* Disable ECC correction of reads on the dram bus. */ - _DisableDramECC = mct_DisableDimmEccEn_D(pMCTstat, pDCTstat); - - SetupDqsPattern_D(pMCTstat, pDCTstat, PatternBuffer); - - /* mct_BeforeTrainDQSRdWrPos_D */ - - dev = pDCTstat->dev_dct; - pDCTstat->Direction = DQS_READDIR; - - /* 2.8.9.9.3 (2) - * Loop over each channel, lane, and rank - */ - - /* NOTE - * The BKDG originally stated to iterate over lane, then rank, however this process is quite slow - * compared to an equivalent loop over rank, then lane as the latter allows multiple lanes to be - * tested simultaneously, thus improving performance by around 8x. - */ - - Errors = 0; - for (Channel = 0; Channel < 2; Channel++) { - print_debug_dqs("\tTrainDQSRdWrPos: 1 Channel ", Channel, 1); - pDCTstat->Channel = Channel; - - if (pDCTstat->DIMMValidDCT[Channel] == 0) /* mct_BeforeTrainDQSRdWrPos_D */ - continue; - - index_reg = 0x98; - - dual_rank = 0; - Receiver = mct_InitReceiver_D(pDCTstat, Channel); - /* There are four receiver pairs, loosely associated with chipselects. - * This is essentially looping over each rank of each DIMM. - */ - for (; Receiver < 8; Receiver++) { - if ((Receiver & 0x1) == 0) { - /* Even rank of DIMM */ - if (mct_RcvrRankEnabled_D(pMCTstat, pDCTstat, Channel, Receiver+1)) - dual_rank = 1; - else - dual_rank = 0; - } - - if (!mct_RcvrRankEnabled_D(pMCTstat, pDCTstat, Channel, Receiver)) { - continue; - } - - /* Select the base test address for the current rank */ - TestAddr = mct_GetMCTSysAddr_D(pMCTstat, pDCTstat, Channel, Receiver, &valid); - if (!valid) { /* Address not supported on current CS */ - continue; - } - - print_debug_dqs("\t\t\t\tTrainDQSRdWrPos: 14 TestAddr ", TestAddr, 4); - SetUpperFSbase(TestAddr); /* fs:eax = far ptr to target */ - - print_debug_dqs("\t\t\t\tTrainDQSRdWrPos: 12 Receiver ", Receiver, 2); - - /* 2.8.9.9.3 (DRAM Write Data Timing Loop) - * Iterate over all possible DQS delay values (0x0 - 0x7f) - */ - uint8_t test_write_dqs_delay = 0; - uint8_t test_read_dqs_delay = 0; - uint8_t passing_dqs_delay_found[MAX_BYTE_LANES]; - - /* Initialize variables */ - for (lane = 0; lane < MAX_BYTE_LANES; lane++) { - current_write_dqs_delay[lane] = 0; - passing_dqs_delay_found[lane] = 0; - write_dqs_delay_stepping_done[lane] = 0; - } - - for (test_write_dqs_delay = 0; test_write_dqs_delay < 128; test_write_dqs_delay++) { - print_debug_dqs("\t\t\t\tTrainDQSRdWrPos: 16 test_write_dqs_delay ", test_write_dqs_delay, 6); - - /* Break out of loop if passing window already found, */ - if (write_dqs_delay_stepping_done[0] && write_dqs_delay_stepping_done[1] - && write_dqs_delay_stepping_done[2] && write_dqs_delay_stepping_done[3] - && write_dqs_delay_stepping_done[4] && write_dqs_delay_stepping_done[5] - && write_dqs_delay_stepping_done[6] && write_dqs_delay_stepping_done[7]) - break; - - /* Commit the current Write Data Timing settings to the hardware registers */ - write_dqs_write_data_timing_registers(current_write_dqs_delay, dev, Channel, (Receiver >> 1), index_reg); - - /* Write the DRAM training pattern to the base test address */ - WriteDQSTestPattern_D(pMCTstat, pDCTstat, TestAddr << 8); - - /* 2.8.9.9.3 (DRAM Read DQS Timing Control Loop) - * Iterate over all possible DQS delay values (0x0 - 0x3f) - */ - for (test_read_dqs_delay = 0; test_read_dqs_delay < 64; test_read_dqs_delay++) { - print_debug_dqs("\t\t\t\t\tTrainDQSRdWrPos: 161 test_read_dqs_delay ", test_read_dqs_delay, 6); - - /* Initialize Read DQS Timing Control settings for this iteration */ - for (lane = 0; lane < MAX_BYTE_LANES; lane++) - if (!write_dqs_delay_stepping_done[lane]) - current_read_dqs_delay[lane] = test_read_dqs_delay; - - /* Commit the current Read DQS Timing Control settings to the hardware registers */ - write_dqs_read_data_timing_registers(current_read_dqs_delay, dev, Channel, (Receiver >> 1), index_reg); - - /* Initialize test result variable */ - bytelane_test_results = 0xff; - - /* Read the DRAM training pattern from the base test address three times - * NOTE - * While the BKDG states to read three times this is probably excessive! - * Decrease training time by only reading the test pattern once per iteration - */ - for (iter = 0; iter < 1; iter++) { - /* Flush caches */ - SetTargetWTIO_D(TestAddr); - FlushDQSTestPattern_D(pDCTstat, TestAddr << 8); - ResetTargetWTIO_D(); - - /* Read and compare pattern */ - bytelane_test_results &= (CompareDQSTestPattern_D(pMCTstat, pDCTstat, TestAddr << 8) & 0xff); /* [Lane 7 :: Lane 0] 0 = fail, 1 = pass */ - - /* If all lanes have already failed testing bypass remaining re-read attempt(s) */ - if (bytelane_test_results == 0x0) - break; - } - - /* Store any lanes that passed testing for later use */ - for (lane = 0; lane < 8; lane++) - if (!write_dqs_delay_stepping_done[lane]) - dqs_read_results_array[Receiver & 0x1][lane][test_read_dqs_delay] = (!!(bytelane_test_results & (1 << lane))); - - print_debug_dqs("\t\t\t\t\tTrainDQSRdWrPos: 162 bytelane_test_results ", bytelane_test_results, 6); - } - - for (lane = 0; lane < MAX_BYTE_LANES; lane++) { - if (write_dqs_delay_stepping_done[lane]) - continue; - - /* Determine location and length of longest consecutive string of passing values - * Output is stored in best_pos and best_count - */ - last_pos = 0; - cur_count = 0; - best_pos = 0; - best_count = 0; - for (iter = 0; iter < 64; iter++) { - if ((dqs_read_results_array[Receiver & 0x1][lane][iter]) && (iter < 63)) { - /* Pass */ - cur_count++; - } else { - /* Failure or end of loop */ - if (cur_count > best_count) { - best_count = cur_count; - best_pos = last_pos; - } - cur_count = 0; - last_pos = iter; - } - } - - if (best_count > 2) { - /* Exit the DRAM Write Data Timing Loop after programming the Read DQS Timing Control - * register with the center of the passing window - */ - current_read_dqs_delay[lane] = (best_pos + (best_count / 2)); - passing_dqs_delay_found[lane] = 1; - - /* Commit the current Read DQS Timing Control settings to the hardware registers */ - write_dqs_read_data_timing_registers(current_read_dqs_delay, dev, Channel, (Receiver >> 1), index_reg); - - /* Exit the DRAM Write Data Timing Loop */ - write_dqs_delay_stepping_done[lane] = 1; - - print_debug_dqs("\t\t\t\tTrainDQSRdWrPos: 142 largest passing region ", best_count, 4); - print_debug_dqs("\t\t\t\tTrainDQSRdWrPos: 143 largest passing region start ", best_pos, 4); - } - - /* Increment the DQS Write Delay value if needed for the next DRAM Write Data Timing Loop iteration */ - if (!write_dqs_delay_stepping_done[lane]) - current_write_dqs_delay[lane]++; - } - } - - /* Flag failure(s) if present */ - for (lane = 0; lane < 8; lane++) { - if (!passing_dqs_delay_found[lane]) { - print_debug_dqs("\t\t\t\tTrainDQSRdWrPos: 121 Unable to find passing region for lane ", lane, 2); - - /* Flag absence of passing window */ - Errors |= 1 << SB_NODQSPOS; - } - } - - /* Iterate over all possible Write Data Timing values (0x0 - 0x7f) - * Note that the Read DQS Timing Control was calibrated / centered in the prior nested loop - */ - for (test_write_dqs_delay = 0; test_write_dqs_delay < 128; test_write_dqs_delay++) { - /* Initialize Write Data Timing settings for this iteration */ - for (lane = 0; lane < MAX_BYTE_LANES; lane++) - current_write_dqs_delay[lane] = test_write_dqs_delay; - - /* Commit the current Write Data Timing settings to the hardware registers */ - write_dqs_write_data_timing_registers(current_write_dqs_delay, dev, Channel, (Receiver >> 1), index_reg); - - /* Write the DRAM training pattern to the base test address */ - WriteDQSTestPattern_D(pMCTstat, pDCTstat, TestAddr << 8); - - /* Flush caches */ - SetTargetWTIO_D(TestAddr); - FlushDQSTestPattern_D(pDCTstat, TestAddr << 8); - ResetTargetWTIO_D(); - - /* Read and compare pattern from the base test address */ - bytelane_test_results = (CompareDQSTestPattern_D(pMCTstat, pDCTstat, TestAddr << 8) & 0xff); /* [Lane 7 :: Lane 0] 0 = fail, 1 = pass */ - - /* Store any lanes that passed testing for later use */ - for (lane = 0; lane < 8; lane++) - dqs_write_results_array[Receiver & 0x1][lane][test_write_dqs_delay] = (!!(bytelane_test_results & (1 << lane))); - } - - for (lane = 0; lane < 8; lane++) { - if ((!dual_rank) || (dual_rank && (Receiver & 0x1))) { - -#ifdef PRINT_PASS_FAIL_BITMAPS - for (iter = 0; iter < 64; iter++) { - if (dqs_read_results_array[0][lane][iter]) - printk(BIOS_DEBUG, "+"); - else - printk(BIOS_DEBUG, "."); - } - printk(BIOS_DEBUG, "\n"); - for (iter = 0; iter < 64; iter++) { - if (dqs_read_results_array[1][lane][iter]) - printk(BIOS_DEBUG, "+"); - else - printk(BIOS_DEBUG, "."); - } - printk(BIOS_DEBUG, "\n\n"); - for (iter = 0; iter < 128; iter++) { - if (dqs_write_results_array[0][lane][iter]) - printk(BIOS_DEBUG, "+"); - else - printk(BIOS_DEBUG, "."); - } - printk(BIOS_DEBUG, "\n"); - for (iter = 0; iter < 128; iter++) { - if (dqs_write_results_array[1][lane][iter]) - printk(BIOS_DEBUG, "+"); - else - printk(BIOS_DEBUG, "."); - } - printk(BIOS_DEBUG, "\n\n"); -#endif - - /* Base rank of single-rank DIMM, or odd rank of dual-rank DIMM */ - if (dual_rank) { - /* Intersect the passing windows of both ranks */ - for (iter = 0; iter < 64; iter++) - if (!dqs_read_results_array[1][lane][iter]) - dqs_read_results_array[0][lane][iter] = 0; - for (iter = 0; iter < 128; iter++) - if (!dqs_write_results_array[1][lane][iter]) - dqs_write_results_array[0][lane][iter] = 0; - } - - /* Determine location and length of longest consecutive string of passing values for read DQS timing - * Output is stored in best_pos and best_count - */ - last_pos = 0; - cur_count = 0; - best_pos = 0; - best_count = 0; - for (iter = 0; iter < 64; iter++) { - if ((dqs_read_results_array[0][lane][iter]) && (iter < 63)) { - /* Pass */ - cur_count++; - } else { - /* Failure or end of loop */ - if (cur_count > best_count) { - best_count = cur_count; - best_pos = last_pos; - } - cur_count = 0; - last_pos = iter; - } - } - print_debug_dqs("\t\t\t\tTrainDQSRdWrPos: 144 largest read passing region ", best_count, 4); - if (best_count > 0) { - if (best_count < MIN_DQS_WNDW) { - /* Flag excessively small passing window */ - Errors |= 1 << SB_SMALLDQS; - } - - /* Find the center of the passing window */ - current_read_dqs_delay[lane] = (best_pos + (best_count / 2)); - - /* Commit the current Read DQS Timing Control settings to the hardware registers */ - write_dqs_read_data_timing_registers(current_read_dqs_delay, dev, Channel, (Receiver >> 1), index_reg); - - /* Save the final Read DQS Timing Control settings for later use */ - pDCTstat->CH_D_DIR_B_DQS[Channel][Receiver >> 1][DQS_READDIR][lane] = current_read_dqs_delay[lane]; - } else { - print_debug_dqs("\t\t\t\tTrainDQSRdWrPos: 122 Unable to find read passing region for lane ", lane, 2); - - /* Flag absence of passing window */ - Errors |= 1 << SB_NODQSPOS; - } - - /* Determine location and length of longest consecutive string of passing values for write DQS timing - * Output is stored in best_pos and best_count - */ - last_pos = 0; - cur_count = 0; - best_pos = 0; - best_count = 0; - for (iter = 0; iter < 128; iter++) { - if ((dqs_write_results_array[0][lane][iter]) && (iter < 127)) { - /* Pass */ - cur_count++; - } else { - /* Failure or end of loop */ - if (cur_count > best_count) { - best_count = cur_count; - best_pos = last_pos; - } - cur_count = 0; - last_pos = iter; - } - } - print_debug_dqs("\t\t\t\tTrainDQSRdWrPos: 145 largest write passing region ", best_count, 4); - if (best_count > 0) { - if (best_count < MIN_DQS_WNDW) { - /* Flag excessively small passing window */ - Errors |= 1 << SB_SMALLDQS; - } - - /* Find the center of the passing window */ - current_write_dqs_delay[lane] = (best_pos + (best_count / 2)); - - /* Commit the current Write Data Timing settings to the hardware registers */ - write_dqs_write_data_timing_registers(current_write_dqs_delay, dev, Channel, (Receiver >> 1), index_reg); - - /* Save the final Write Data Timing settings for later use */ - pDCTstat->CH_D_DIR_B_DQS[Channel][Receiver >> 1][DQS_WRITEDIR][lane] = current_write_dqs_delay[lane]; - } else { - print_debug_dqs("\t\t\t\tTrainDQSRdWrPos: 123 Unable to find write passing region for lane ", lane, 2); - - /* Flag absence of passing window */ - Errors |= 1 << SB_NODQSPOS; - } - } - } - - } - } - - pDCTstat->TrainErrors |= Errors; - pDCTstat->ErrStatus |= Errors; - -#if DQS_TRAIN_DEBUG > 0 - { - u8 val; - u8 i; - u8 ChannelDTD, ReceiverDTD, Dir; - u8 *p; - - for (Dir = 0; Dir < 2; Dir++) { - if (Dir == 1) { - printk(BIOS_DEBUG, "TrainDQSRdWrPos: CH_D_DIR_B_DQS WR:\n"); - } else { - printk(BIOS_DEBUG, "TrainDQSRdWrPos: CH_D_DIR_B_DQS RD:\n"); - } - for (ChannelDTD = 0; ChannelDTD < 2; ChannelDTD++) { - printk(BIOS_DEBUG, "Channel: %02x\n", ChannelDTD); - for (ReceiverDTD = 0; ReceiverDTD < MAX_CS_SUPPORTED; ReceiverDTD += 2) { - printk(BIOS_DEBUG, "\t\tReceiver: %02x:", ReceiverDTD); - p = pDCTstat->CH_D_DIR_B_DQS[ChannelDTD][ReceiverDTD >> 1][Dir]; - for (i = 0; i < 8; i++) { - val = p[i]; - printk(BIOS_DEBUG, " %02x", val); - } - printk(BIOS_DEBUG, "\n"); - } - } - } - - } -#endif - if (_DisableDramECC) { - mct_EnableDimmEccEn_D(pMCTstat, pDCTstat, _DisableDramECC); - } - if (!_Wrap32Dis) { - addr = HWCR_MSR; - _RDMSR(addr, &lo, &hi); - lo &= ~(1<<17); /* restore HWCR.wrap32dis */ - _WRMSR(addr, lo, hi); - } - if (!_SSE2) { - cr4 = read_cr4(); - cr4 &= ~(1<<9); /* restore cr4.OSFXSR */ - write_cr4(cr4); - } - - printk(BIOS_DEBUG, "TrainDQSRdWrPos: Status %x\n", pDCTstat->Status); - printk(BIOS_DEBUG, "TrainDQSRdWrPos: TrainErrors %x\n", pDCTstat->TrainErrors); - printk(BIOS_DEBUG, "TrainDQSRdWrPos: ErrStatus %x\n", pDCTstat->ErrStatus); - printk(BIOS_DEBUG, "TrainDQSRdWrPos: ErrCode %x\n", pDCTstat->ErrCode); - printk(BIOS_DEBUG, "TrainDQSRdWrPos: Done\n\n"); -} - -/* Calcuate and set MaxRdLatency - * Algorithm detailed in the Fam15h BKDG Rev. 3.14 section 2.10.5.8.5 - */ -void Calc_SetMaxRdLatency_D_Fam15(struct MCTStatStruc *pMCTstat, - struct DCTStatStruc *pDCTstat, uint8_t dct, uint8_t calc_min) -{ - uint8_t dimm; - uint8_t lane; - uint32_t dword; - uint32_t dword2; - uint32_t max_delay; - uint8_t mem_clk = 0; - uint8_t nb_pstate; - uint32_t nb_clk; - uint32_t p = 0; - uint32_t n = 0; - uint32_t t = 0; - uint16_t current_phy_phase_delay[MAX_BYTE_LANES]; - uint16_t current_read_dqs_delay[MAX_BYTE_LANES]; - - uint32_t index_reg = 0x98; - uint32_t dev = pDCTstat->dev_dct; - uint16_t fam15h_freq_tab[] = {0, 0, 0, 0, 333, 0, 400, 0, 0, 0, 533, 0, 0, 0, 667, 0, 0, 0, 800, 0, 0, 0, 933}; - -#if DQS_TRAIN_DEBUG > 0 - printk(BIOS_DEBUG, "%s: Start\n", __func__); -#endif - - uint8_t lane_count; - lane_count = get_available_lane_count(pMCTstat, pDCTstat); - - mem_clk = Get_NB32_DCT(dev, dct, 0x94) & 0x1f; - if (fam15h_freq_tab[mem_clk] == 0) { - pDCTstat->CH_MaxRdLat[dct][0] = 0x55; - pDCTstat->CH_MaxRdLat[dct][1] = 0x55; - return; - } - - /* P is specified in PhyCLKs (1/2 MEMCLKs) */ - for (nb_pstate = 0; nb_pstate < 2; nb_pstate++) { - /* 2.10.5.8.5 (2) */ - dword = Get_NB32_index_wait_DCT(dev, dct, index_reg, 0x00000004); - if ((!(dword & (0x1 << 21))) && (!(dword & (0x1 << 13))) && (!(dword & (0x1 << 5)))) - p += 1; - else - p += 2; - - /* 2.10.5.8.5 (3) */ - dword = Get_NB32_DCT_NBPstate(dev, dct, nb_pstate, 0x210) & 0xf; /* Retrieve RdPtrInit */ - p += (9 - dword); - - /* 2.10.5.8.5 (4) */ - if (!calc_min) - p += 5; - - /* 2.10.5.8.5 (5) */ - dword = Get_NB32_DCT(dev, dct, 0xa8); - dword2 = Get_NB32_DCT(dev, dct, 0x90); - if ((!(dword & (0x1 << 5))) && (!(dword2 & (0x1 << 16)))) - p += 2; - - /* 2.10.5.8.5 (6) */ - dword = Get_NB32_DCT(dev, dct, 0x200) & 0x1f; /* Retrieve Tcl */ - p += (2 * (dword - 1)); - - /* 2.10.5.8.5 (7) */ - max_delay = 0; - for (dimm = 0; dimm < 4; dimm++) { - if (!mct_RcvrRankEnabled_D(pMCTstat, pDCTstat, dct, dimm * 2)) - continue; - - read_dqs_receiver_enable_control_registers(current_phy_phase_delay, dev, dct, dimm, index_reg); - read_dqs_read_data_timing_registers(current_read_dqs_delay, dev, dct, dimm, index_reg); - for (lane = 0; lane < lane_count; lane++) - if ((current_phy_phase_delay[lane] + current_read_dqs_delay[lane]) > max_delay) - max_delay = (current_phy_phase_delay[lane] + current_read_dqs_delay[lane]); - } - p += (max_delay >> 5); - - /* 2.10.5.8.5 (8) */ - if (!calc_min) - p += 5; - - /* 2.10.5.8.5 (9) */ - t += 800; - - /* 2.10.5.8.5 (10) */ - dword = Get_NB32(pDCTstat->dev_nbctl, (0x160 + (nb_pstate * 4))); /* Retrieve NbDid, NbFid */ - nb_clk = (200 * (((dword >> 1) & 0x1f) + 0x4)) / (((dword >> 7) & 0x1)?2:1); - n = (((((uint64_t)p * 1000000000000ULL)/(((uint64_t)fam15h_freq_tab[mem_clk] * 1000000ULL) * 2)) + ((uint64_t)t)) * ((uint64_t)nb_clk * 1000)) / 1000000000ULL; - - /* 2.10.5.8.5 (11) */ - if (!calc_min) - n -= 1; - - /* 2.10.5.8.5 (12) */ - if (!calc_min) { - dword = Get_NB32_DCT_NBPstate(dev, dct, nb_pstate, 0x210); - dword &= ~(0x3ff << 22); - dword |= (((n - 1) & 0x3ff) << 22); - Set_NB32_DCT_NBPstate(dev, dct, nb_pstate, 0x210, dword); - } - - /* Save result for later use */ - pDCTstat->CH_MaxRdLat[dct][nb_pstate] = n - 1; - -#if DQS_TRAIN_DEBUG > 0 - printk(BIOS_DEBUG, "%s: CH_MaxRdLat[%d][%d]: %03x\n", __func__, dct, nb_pstate, pDCTstat->CH_MaxRdLat[dct][nb_pstate]); -#endif - } - -#if DQS_TRAIN_DEBUG > 0 - printk(BIOS_DEBUG, "%s: Done\n", __func__); -#endif -} - -static void start_dram_dqs_training_pattern_fam15(struct MCTStatStruc *pMCTstat, - struct DCTStatStruc *pDCTstat, uint8_t dct, uint8_t Receiver) -{ - uint32_t dword; - uint32_t dev = pDCTstat->dev_dct; - - /* 2.10.5.7.1.1 - * It appears that the DCT only supports 8-beat burst length mode, - * so do nothing here... - */ - - /* Wait for CmdSendInProg == 0 */ - do { - dword = Get_NB32_DCT(dev, dct, 0x250); - } while (dword & (0x1 << 12)); - - /* Set CmdTestEnable = 1 */ - dword = Get_NB32_DCT(dev, dct, 0x250); - dword |= (0x1 << 2); - Set_NB32_DCT(dev, dct, 0x250, dword); - - /* 2.10.5.8.6.1.1 Send Activate Command (Target A) */ - dword = Get_NB32_DCT(dev, dct, 0x28c); - dword &= ~(0xff << 22); /* CmdChipSelect = Receiver */ - dword |= ((0x1 << Receiver) << 22); - dword &= ~(0x7 << 19); /* CmdBank = 0 */ - dword &= ~(0x3ffff); /* CmdAddress = 0 */ - dword |= (0x1 << 31); /* SendActCmd = 1 */ - Set_NB32_DCT(dev, dct, 0x28c, dword); - - /* Wait for SendActCmd == 0 */ - do { - dword = Get_NB32_DCT(dev, dct, 0x28c); - } while (dword & (0x1 << 31)); - - /* Wait 75 MEMCLKs. */ - precise_memclk_delay_fam15(pMCTstat, pDCTstat, dct, 75); - - /* 2.10.5.8.6.1.1 Send Activate Command (Target B) */ - dword = Get_NB32_DCT(dev, dct, 0x28c); - dword &= ~(0xff << 22); /* CmdChipSelect = Receiver */ - dword |= ((0x1 << Receiver) << 22); - dword &= ~(0x7 << 19); /* CmdBank = 1 */ - dword |= (0x1 << 19); - dword &= ~(0x3ffff); /* CmdAddress = 0 */ - dword |= (0x1 << 31); /* SendActCmd = 1 */ - Set_NB32_DCT(dev, dct, 0x28c, dword); - - /* Wait for SendActCmd == 0 */ - do { - dword = Get_NB32_DCT(dev, dct, 0x28c); - } while (dword & (0x1 << 31)); - - /* Wait 75 MEMCLKs. */ - precise_memclk_delay_fam15(pMCTstat, pDCTstat, dct, 75); -} - -static void stop_dram_dqs_training_pattern_fam15(struct MCTStatStruc *pMCTstat, - struct DCTStatStruc *pDCTstat, uint8_t dct, uint8_t Receiver) -{ - uint32_t dword; - uint32_t dev = pDCTstat->dev_dct; - - /* 2.10.5.8.6.1.1 Send Precharge Command */ - /* Wait 25 MEMCLKs. */ - precise_memclk_delay_fam15(pMCTstat, pDCTstat, dct, 25); - - dword = Get_NB32_DCT(dev, dct, 0x28c); - dword &= ~(0xff << 22); /* CmdChipSelect = Receiver */ - dword |= ((0x1 << Receiver) << 22); - dword &= ~(0x7 << 19); /* CmdBank = 0 */ - dword &= ~(0x3ffff); /* CmdAddress = 0x400 */ - dword |= 0x400; - dword |= (0x1 << 30); /* SendPchgCmd = 1 */ - Set_NB32_DCT(dev, dct, 0x28c, dword); - - /* Wait for SendPchgCmd == 0 */ - do { - dword = Get_NB32_DCT(dev, dct, 0x28c); - } while (dword & (0x1 << 30)); - - /* Wait 25 MEMCLKs. */ - precise_memclk_delay_fam15(pMCTstat, pDCTstat, dct, 25); - - /* Set CmdTestEnable = 0 */ - dword = Get_NB32_DCT(dev, dct, 0x250); - dword &= ~(0x1 << 2); - Set_NB32_DCT(dev, dct, 0x250, dword); -} - -void read_dram_dqs_training_pattern_fam15(struct MCTStatStruc *pMCTstat, - struct DCTStatStruc *pDCTstat, uint8_t dct, - uint8_t Receiver, uint8_t lane, uint8_t stop_on_error) -{ - uint32_t dword; - uint32_t dev = pDCTstat->dev_dct; - - start_dram_dqs_training_pattern_fam15(pMCTstat, pDCTstat, dct, Receiver); - - /* 2.10.5.8.6.1.2 */ - /* Configure DQMask */ - if (lane < 4) { - Set_NB32_DCT(dev, dct, 0x274, ~(0xff << (lane * 8))); - Set_NB32_DCT(dev, dct, 0x278, ~0x0); - dword = Get_NB32_DCT(dev, dct, 0x27c); - dword |= 0xff; /* EccMask = 0xff */ - Set_NB32_DCT(dev, dct, 0x27c, dword); - } else if (lane < 8) { - Set_NB32_DCT(dev, dct, 0x274, ~0x0); - Set_NB32_DCT(dev, dct, 0x278, ~(0xff << ((lane - 4) * 8))); - dword = Get_NB32_DCT(dev, dct, 0x27c); - dword |= 0xff; /* EccMask = 0xff */ - Set_NB32_DCT(dev, dct, 0x27c, dword); - } else if (lane == 8) { - Set_NB32_DCT(dev, dct, 0x274, ~0x0); - Set_NB32_DCT(dev, dct, 0x278, ~0x0); - dword = Get_NB32_DCT(dev, dct, 0x27c); - dword &= ~(0xff); /* EccMask = 0x0 */ - Set_NB32_DCT(dev, dct, 0x27c, dword); - } else if (lane == 0xff) { - Set_NB32_DCT(dev, dct, 0x274, ~0xffffffff); - Set_NB32_DCT(dev, dct, 0x278, ~0xffffffff); - dword = Get_NB32_DCT(dev, dct, 0x27c); - if (get_available_lane_count(pMCTstat, pDCTstat) < 9) - dword |= 0xff; /* EccMask = 0xff */ - else - dword &= ~(0xff); /* EccMask = 0x0 */ - Set_NB32_DCT(dev, dct, 0x27c, dword); - } else { - Set_NB32_DCT(dev, dct, 0x274, ~0x0); - Set_NB32_DCT(dev, dct, 0x278, ~0x0); - dword = Get_NB32_DCT(dev, dct, 0x27c); - dword |= 0xff; /* EccMask = 0xff */ - Set_NB32_DCT(dev, dct, 0x27c, dword); - } - - dword = Get_NB32_DCT(dev, dct, 0x270); - dword &= ~(0x7ffff); /* DataPrbsSeed = 55555 */ -// dword |= (0x55555); - dword |= (0x44443); /* Use AGESA seed */ - Set_NB32_DCT(dev, dct, 0x270, dword); - - /* 2.10.5.8.4 */ - dword = Get_NB32_DCT(dev, dct, 0x260); - dword &= ~(0x1fffff); /* CmdCount = 256 */ - dword |= 256; - Set_NB32_DCT(dev, dct, 0x260, dword); - - /* Configure Target A */ - dword = Get_NB32_DCT(dev, dct, 0x254); - dword &= ~(0x7 << 24); /* TgtChipSelect = Receiver */ - dword |= (Receiver & 0x7) << 24; - dword &= ~(0x7 << 21); /* TgtBank = 0 */ - dword &= ~(0x3ff); /* TgtAddress = 0 */ - Set_NB32_DCT(dev, dct, 0x254, dword); - - /* Configure Target B */ - dword = Get_NB32_DCT(dev, dct, 0x258); - dword &= ~(0x7 << 24); /* TgtChipSelect = Receiver */ - dword |= (Receiver & 0x7) << 24; - dword &= ~(0x7 << 21); /* TgtBank = 1 */ - dword |= (0x1 << 21); - dword &= ~(0x3ff); /* TgtAddress = 0 */ - Set_NB32_DCT(dev, dct, 0x258, dword); - - dword = Get_NB32_DCT(dev, dct, 0x250); - dword |= (0x1 << 3); /* ResetAllErr = 1 */ - dword &= ~(0x1 << 4); /* StopOnErr = stop_on_error */ - dword |= (stop_on_error & 0x1) << 4; - dword &= ~(0x3 << 8); /* CmdTgt = 1 (Alternate between Target A and Target B) */ - dword |= (0x1 << 8); - dword &= ~(0x7 << 5); /* CmdType = 0 (Read) */ - dword |= (0x1 << 11); /* SendCmd = 1 */ - Set_NB32_DCT(dev, dct, 0x250, dword); - - /* 2.10.5.8.6.1.2 Wait for TestStatus == 1 and CmdSendInProg == 0 */ - do { - dword = Get_NB32_DCT(dev, dct, 0x250); - } while ((dword & (0x1 << 12)) || (!(dword & (0x1 << 10)))); - - dword = Get_NB32_DCT(dev, dct, 0x250); - dword &= ~(0x1 << 11); /* SendCmd = 0 */ - Set_NB32_DCT(dev, dct, 0x250, dword); - - stop_dram_dqs_training_pattern_fam15(pMCTstat, pDCTstat, dct, Receiver); -} - -void write_dram_dqs_training_pattern_fam15(struct MCTStatStruc *pMCTstat, - struct DCTStatStruc *pDCTstat, uint8_t dct, - uint8_t Receiver, uint8_t lane, uint8_t stop_on_error) -{ - uint32_t dword; - uint32_t dev = pDCTstat->dev_dct; - - start_dram_dqs_training_pattern_fam15(pMCTstat, pDCTstat, dct, Receiver); - - /* 2.10.5.8.6.1.2 */ - /* Configure DQMask */ - if (lane < 4) { - Set_NB32_DCT(dev, dct, 0x274, ~(0xff << (lane * 8))); - Set_NB32_DCT(dev, dct, 0x278, ~0x0); - dword = Get_NB32_DCT(dev, dct, 0x27c); - dword |= 0xff; /* EccMask = 0xff */ - Set_NB32_DCT(dev, dct, 0x27c, dword); - } else if (lane < 8) { - Set_NB32_DCT(dev, dct, 0x274, ~0x0); - Set_NB32_DCT(dev, dct, 0x278, ~(0xff << ((lane - 4) * 8))); - dword = Get_NB32_DCT(dev, dct, 0x27c); - dword |= 0xff; /* EccMask = 0xff */ - Set_NB32_DCT(dev, dct, 0x27c, dword); - } else if (lane == 8) { - Set_NB32_DCT(dev, dct, 0x274, ~0x0); - Set_NB32_DCT(dev, dct, 0x278, ~0x0); - dword = Get_NB32_DCT(dev, dct, 0x27c); - dword &= ~(0xff); /* EccMask = 0x0 */ - Set_NB32_DCT(dev, dct, 0x27c, dword); - } else if (lane == 0xff) { - Set_NB32_DCT(dev, dct, 0x274, ~0xffffffff); - Set_NB32_DCT(dev, dct, 0x278, ~0xffffffff); - dword = Get_NB32_DCT(dev, dct, 0x27c); - if (get_available_lane_count(pMCTstat, pDCTstat) < 9) - dword |= 0xff; /* EccMask = 0xff */ - else - dword &= ~(0xff); /* EccMask = 0x0 */ - Set_NB32_DCT(dev, dct, 0x27c, dword); - } else { - Set_NB32_DCT(dev, dct, 0x274, ~0x0); - Set_NB32_DCT(dev, dct, 0x278, ~0x0); - dword = Get_NB32_DCT(dev, dct, 0x27c); - dword |= 0xff; /* EccMask = 0xff */ - Set_NB32_DCT(dev, dct, 0x27c, dword); - } - - dword = Get_NB32_DCT(dev, dct, 0x270); - dword &= ~(0x7ffff); /* DataPrbsSeed = 55555 */ -// dword |= (0x55555); - dword |= (0x44443); /* Use AGESA seed */ - Set_NB32_DCT(dev, dct, 0x270, dword); - - /* 2.10.5.8.4 */ - dword = Get_NB32_DCT(dev, dct, 0x260); - dword &= ~(0x1fffff); /* CmdCount = 256 */ - dword |= 256; - Set_NB32_DCT(dev, dct, 0x260, dword); - - /* Configure Target A */ - dword = Get_NB32_DCT(dev, dct, 0x254); - dword &= ~(0x7 << 24); /* TgtChipSelect = Receiver */ - dword |= (Receiver & 0x7) << 24; - dword &= ~(0x7 << 21); /* TgtBank = 0 */ - dword &= ~(0x3ff); /* TgtAddress = 0 */ - Set_NB32_DCT(dev, dct, 0x254, dword); - - /* Configure Target B */ - dword = Get_NB32_DCT(dev, dct, 0x258); - dword &= ~(0x7 << 24); /* TgtChipSelect = Receiver */ - dword |= (Receiver & 0x7) << 24; - dword &= ~(0x7 << 21); /* TgtBank = 1 */ - dword |= (0x1 << 21); - dword &= ~(0x3ff); /* TgtAddress = 0 */ - Set_NB32_DCT(dev, dct, 0x258, dword); - - dword = Get_NB32_DCT(dev, dct, 0x250); - dword |= (0x1 << 3); /* ResetAllErr = 1 */ - dword &= ~(0x1 << 4); /* StopOnErr = stop_on_error */ - dword |= (stop_on_error & 0x1) << 4; - dword &= ~(0x3 << 8); /* CmdTgt = 1 (Alternate between Target A and Target B) */ - dword |= (0x1 << 8); - dword &= ~(0x7 << 5); /* CmdType = 1 (Write) */ - dword |= (0x1 << 5); - dword |= (0x1 << 11); /* SendCmd = 1 */ - Set_NB32_DCT(dev, dct, 0x250, dword); - - /* 2.10.5.8.6.1.2 Wait for TestStatus == 1 and CmdSendInProg == 0 */ - do { - dword = Get_NB32_DCT(dev, dct, 0x250); - } while ((dword & (0x1 << 12)) || (!(dword & (0x1 << 10)))); - - dword = Get_NB32_DCT(dev, dct, 0x250); - dword &= ~(0x1 << 11); /* SendCmd = 0 */ - Set_NB32_DCT(dev, dct, 0x250, dword); - - stop_dram_dqs_training_pattern_fam15(pMCTstat, pDCTstat, dct, Receiver); -} - -#define LANE_DIFF 1 - -/* DQS Position Training - * Algorithm detailed in the Fam15h BKDG Rev. 3.14 section 2.10.5.8.4 - */ -static uint8_t TrainDQSRdWrPos_D_Fam15(struct MCTStatStruc *pMCTstat, - struct DCTStatStruc *pDCTstat, - uint8_t dct, uint8_t receiver_start, - uint8_t receiver_end, uint8_t lane_start) -{ - uint8_t dimm; - uint8_t lane; - uint32_t dword; - uint32_t Errors; - uint8_t Receiver; - uint8_t dual_rank; - uint8_t write_iter; - uint8_t read_iter; - uint8_t check_antiphase; - uint8_t passing_read_dqs_delay_found; - uint8_t passing_write_dqs_delay_found; - uint16_t initial_write_dqs_delay[MAX_BYTE_LANES]; - uint16_t initial_read_dqs_delay[MAX_BYTE_LANES]; - uint16_t initial_write_data_timing[MAX_BYTE_LANES]; - uint16_t current_write_data_delay[MAX_BYTE_LANES]; - uint16_t current_read_dqs_delay[MAX_BYTE_LANES]; - uint16_t current_write_dqs_delay[MAX_BYTE_LANES]; - uint8_t passing_dqs_delay_found[MAX_BYTE_LANES]; - /* [rank][lane][write step][read step + 16] */ - uint8_t dqs_results_array[2][LANE_DIFF][32][48]; - - uint8_t last_pos = 0; - uint8_t cur_count = 0; - uint8_t best_pos = 0; - uint8_t best_count = 0; - - uint32_t index_reg = 0x98; - uint32_t dev = pDCTstat->dev_dct; - - uint8_t lane_end = lane_start + LANE_DIFF; - - uint8_t lane_count; - lane_count = get_available_lane_count(pMCTstat, pDCTstat); - - /* Calculate and program MaxRdLatency */ - Calc_SetMaxRdLatency_D_Fam15(pMCTstat, pDCTstat, dct, 0); - - Errors = 0; - dual_rank = 0; - - /* There are four receiver pairs, loosely associated with chipselects. - * This is essentially looping over each rank within each DIMM. - */ - for (Receiver = receiver_start; Receiver < receiver_end; Receiver++) { - dimm = (Receiver >> 1); - if ((Receiver & 0x1) == 0) { - /* Even rank of DIMM */ - if (mct_RcvrRankEnabled_D(pMCTstat, pDCTstat, dct, Receiver+1)) - dual_rank = 1; - else - dual_rank = 0; - } - - if (!mct_RcvrRankEnabled_D(pMCTstat, pDCTstat, dct, Receiver)) { - continue; - } - -#if DQS_TRAIN_DEBUG > 0 - printk(BIOS_DEBUG, "TrainDQSRdWrPos: Training DQS read/write position for receiver %d (DIMM %d)\n", Receiver, dimm); -#endif - - /* Initialize variables */ - for (lane = lane_start; lane < lane_end; lane++) { - passing_dqs_delay_found[lane] = 0; - } - if ((Receiver & 0x1) == 0) { - /* Even rank of DIMM */ - memset(dqs_results_array, 0, sizeof(dqs_results_array)); - - /* Read initial read / write DQS delays */ - read_dqs_write_timing_control_registers(initial_write_dqs_delay, dev, dct, dimm, index_reg); - read_dqs_read_data_timing_registers(initial_read_dqs_delay, dev, dct, dimm, index_reg); - - /* Read current settings of other (previously trained) lanes */ - read_dqs_write_data_timing_registers(initial_write_data_timing, dev, dct, dimm, index_reg); - } - - /* Initialize iterators */ - memcpy(current_write_data_delay, initial_write_data_timing, sizeof(current_write_data_delay)); - - for (lane = lane_start; lane < lane_end; lane++) { - passing_read_dqs_delay_found = 0; - passing_write_dqs_delay_found = 0; - - /* 2.10.5.8.4 (2) - * For each Write Data Delay value from Write DQS Delay to Write DQS Delay + 1 UI - */ - for (current_write_data_delay[lane] = initial_write_dqs_delay[lane]; current_write_data_delay[lane] < (initial_write_dqs_delay[lane] + 0x20); current_write_data_delay[lane]++) { - print_debug_dqs("\t\t\t\tTrainDQSRdWrPos: 16 current_write_data_delay[lane] ", current_write_data_delay[lane], 6); - - /* 2.10.5.8.4 (2 A) - * Commit the current Write Data Timing settings to the hardware registers - */ - write_dqs_write_data_timing_registers(current_write_data_delay, dev, dct, dimm, index_reg); - - /* 2.10.5.8.4 (2 B) - * Write the DRAM training pattern to the test address - */ - write_dram_dqs_training_pattern_fam15(pMCTstat, pDCTstat, dct, Receiver, lane, 0); - - /* Read current settings of other (previously trained) lanes */ - read_dqs_read_data_timing_registers(current_read_dqs_delay, dev, dct, dimm, index_reg); - - /* 2.10.5.8.4 (2 C) - * For each Read DQS Delay value from 0 to 1 UI - */ - for (current_read_dqs_delay[lane] = 0; current_read_dqs_delay[lane] < 0x20; current_read_dqs_delay[lane]++) { - print_debug_dqs("\t\t\t\t\tTrainDQSRdWrPos: 161 current_read_dqs_delay[lane] ", current_read_dqs_delay[lane], 6); - - if (current_read_dqs_delay[lane] >= (32 - 16)) { - check_antiphase = 1; - } else { - check_antiphase = 0; - } - - /* 2.10.5.8.4 (2 A i) - * Commit the current Read DQS Timing Control settings to the hardware registers - */ - write_dqs_read_data_timing_registers(current_read_dqs_delay, dev, dct, dimm, index_reg); - - /* 2.10.5.8.4 (2 A ii) - * Read the DRAM training pattern from the test address - */ - read_dram_dqs_training_pattern_fam15(pMCTstat, pDCTstat, dct, Receiver, lane, ((check_antiphase == 0)?1:0)); - - if (check_antiphase == 0) { - /* Check for early abort before analyzing per-nibble status */ - dword = Get_NB32_DCT(dev, dct, 0x264); - if ((dword & 0x1ffffff) != 0) { - print_debug_dqs("\t\t\t\t\tTrainDQSRdWrPos: 162 early abort: F2x264 ", dword, 6); - dqs_results_array[Receiver & 0x1][lane - lane_start][current_write_data_delay[lane] - initial_write_dqs_delay[lane]][current_read_dqs_delay[lane] + 16] = 0; /* Fail */ - continue; - } - } - - /* 2.10.5.8.4 (2 A iii) - * Record pass / fail status - */ - dword = Get_NB32_DCT(dev, dct, 0x268) & 0x3ffff; - print_debug_dqs("\t\t\t\t\tTrainDQSRdWrPos: 163 read results: F2x268 ", dword, 6); - if (dword & (0x3 << (lane * 2))) - dqs_results_array[Receiver & 0x1][lane - lane_start][current_write_data_delay[lane] - initial_write_dqs_delay[lane]][current_read_dqs_delay[lane] + 16] = 0; /* Fail */ - else - dqs_results_array[Receiver & 0x1][lane - lane_start][current_write_data_delay[lane] - initial_write_dqs_delay[lane]][current_read_dqs_delay[lane] + 16] = 1; /* Pass */ - if (check_antiphase == 1) { - /* Check antiphase results */ - dword = Get_NB32_DCT(dev, dct, 0x26c) & 0x3ffff; - if (dword & (0x3 << (lane * 2))) - dqs_results_array[Receiver & 0x1][lane - lane_start][current_write_data_delay[lane] - initial_write_dqs_delay[lane]][16 - (32 - current_read_dqs_delay[lane])] = 0; /* Fail */ - else - dqs_results_array[Receiver & 0x1][lane - lane_start][current_write_data_delay[lane] - initial_write_dqs_delay[lane]][16 - (32 - current_read_dqs_delay[lane])] = 1; /* Pass */ - } - } - } - - if (dual_rank && (Receiver & 0x1)) { - /* Overlay the previous rank test results with the current rank */ - for (write_iter = 0; write_iter < 32; write_iter++) { - for (read_iter = 0; read_iter < 48; read_iter++) { - if ((dqs_results_array[0][lane - lane_start][write_iter][read_iter]) - && (dqs_results_array[1][lane - lane_start][write_iter][read_iter])) - dqs_results_array[1][lane - lane_start][write_iter][read_iter] = 1; - else - dqs_results_array[1][lane - lane_start][write_iter][read_iter] = 0; - } - } - } - - /* Determine location and length of longest consecutive string of read passing values - * Output is stored in best_pos and best_count - */ - last_pos = 0; - cur_count = 0; - best_pos = 0; - best_count = 0; - for (write_iter = 0; write_iter < 32; write_iter++) { - for (read_iter = 0; read_iter < 48; read_iter++) { - if ((dqs_results_array[Receiver & 0x1][lane - lane_start][write_iter][read_iter]) && (read_iter < 47)) { - /* Pass */ - cur_count++; - } else { - /* Failure or end of loop */ - if (cur_count > best_count) { - best_count = cur_count; - best_pos = last_pos; - } - cur_count = 0; - last_pos = read_iter + 1; - } - } - last_pos = 0; - } - - if (best_count > 2) { - uint16_t region_center = (best_pos + (best_count / 2)); - - if (region_center < 16) { - printk(BIOS_WARNING, "TrainDQSRdWrPos: negative DQS recovery delay detected!" - " Attempting to continue but your system may be unstable...\n"); - region_center = 0; - } else { - region_center -= 16; - } - - /* Restore current settings of other (previously trained) lanes to the active array */ - memcpy(current_read_dqs_delay, initial_read_dqs_delay, sizeof(current_read_dqs_delay)); - - /* Program the Read DQS Timing Control register with the center of the passing window */ - current_read_dqs_delay[lane] = region_center; - passing_dqs_delay_found[lane] = 1; - - /* Commit the current Read DQS Timing Control settings to the hardware registers */ - write_dqs_read_data_timing_registers(current_read_dqs_delay, dev, dct, dimm, index_reg); - - /* Save the final Read DQS Timing Control settings for later use */ - pDCTstat->CH_D_DIR_B_DQS[dct][Receiver >> 1][DQS_READDIR][lane] = current_read_dqs_delay[lane]; - - print_debug_dqs("\t\t\t\tTrainDQSRdWrPos: 142 largest read passing region ", best_count, 4); - print_debug_dqs("\t\t\t\tTrainDQSRdWrPos: 143 largest read passing region start ", best_pos, 4); - print_debug_dqs("\t\t\t\tTrainDQSRdWrPos: 144 largest read passing region center (raw hardware value) ", region_center, 4); - } else { - /* Restore current settings of other (previously trained) lanes to the active array */ - memcpy(current_read_dqs_delay, initial_read_dqs_delay, sizeof(current_read_dqs_delay)); - - /* Reprogram the Read DQS Timing Control register with the original settings */ - write_dqs_read_data_timing_registers(initial_read_dqs_delay, dev, dct, dimm, index_reg); - } - - /* Determine location and length of longest consecutive string of write passing values - * Output is stored in best_pos and best_count - */ - last_pos = 0; - cur_count = 0; - best_pos = 0; - best_count = 0; - for (read_iter = 0; read_iter < 48; read_iter++) { - for (write_iter = 0; write_iter < 32; write_iter++) { - if ((dqs_results_array[Receiver & 0x1][lane - lane_start][write_iter][read_iter]) && (write_iter < 31)) { - /* Pass */ - cur_count++; - } else { - /* Failure or end of loop */ - if (cur_count > best_count) { - best_count = cur_count; - best_pos = last_pos; - } - cur_count = 0; - last_pos = write_iter + 1; - } - } - last_pos = 0; - } - - if (best_count > 2) { - /* Restore current settings of other (previously trained) lanes to the active array */ - memcpy(current_write_dqs_delay, initial_write_data_timing, sizeof(current_write_data_delay)); - - /* Program the Write DQS Timing Control register with the optimal region within the passing window */ - if (pDCTstat->Status & (1 << SB_LoadReduced)) - current_write_dqs_delay[lane] = ((best_pos + initial_write_dqs_delay[lane]) + (best_count / 3)); - else - current_write_dqs_delay[lane] = ((best_pos + initial_write_dqs_delay[lane]) + (best_count / 2)); - passing_write_dqs_delay_found = 1; - - /* Commit the current Write DQS Timing Control settings to the hardware registers */ - write_dqs_write_data_timing_registers(current_write_dqs_delay, dev, dct, dimm, index_reg); - - /* Save the final Write Data Timing settings for later use */ - pDCTstat->CH_D_DIR_B_DQS[dct][Receiver >> 1][DQS_WRITEDIR][lane] = current_write_dqs_delay[lane]; - - print_debug_dqs("\t\t\t\tTrainDQSRdWrPos: 145 largest write passing region ", best_count, 4); - print_debug_dqs("\t\t\t\tTrainDQSRdWrPos: 146 largest write passing region start ", best_pos, 4); - } else { - /* Restore current settings of other (previously trained) lanes to the active array */ - memcpy(current_write_dqs_delay, initial_write_data_timing, sizeof(current_write_data_delay)); - - /* Reprogram the Write DQS Timing Control register with the original settings */ - write_dqs_write_data_timing_registers(current_write_dqs_delay, dev, dct, dimm, index_reg); - } - - if (passing_read_dqs_delay_found && passing_write_dqs_delay_found) - passing_dqs_delay_found[lane] = 1; - } - -#ifdef PRINT_PASS_FAIL_BITMAPS - for (lane = lane_start; lane < lane_end; lane++) { - for (write_iter = 0; write_iter < 32; write_iter++) { - for (read_iter = 0; read_iter < 48; read_iter++) { - if (dqs_results_array[Receiver & 0x1][lane - lane_start][write_iter][read_iter]) { - printk(BIOS_DEBUG, "+"); - } else { - if (read_iter < 16) - printk(BIOS_DEBUG, ":"); - else - printk(BIOS_DEBUG, "."); - } - } - printk(BIOS_DEBUG, "\n"); - } - printk(BIOS_DEBUG, "\n\n"); - } -#endif - - /* Flag failure(s) if present */ - for (lane = lane_start; lane < lane_end; lane++) { - if (!passing_dqs_delay_found[lane]) { - print_debug_dqs("\t\t\t\tTrainDQSRdWrPos: 121 Unable to find passing region for lane ", lane, 2); - - /* Flag absence of passing window */ - Errors |= 1 << SB_NODQSPOS; - } - } - - pDCTstat->TrainErrors |= Errors; - pDCTstat->ErrStatus |= Errors; - -#if DQS_TRAIN_DEBUG > 0 - { - u8 val; - u8 i; - u8 ChannelDTD, ReceiverDTD, Dir; - u8 *p; - - for (Dir = 0; Dir < 2; Dir++) { - if (Dir == 1) { - printk(BIOS_DEBUG, "TrainDQSRdWrPos: CH_D_DIR_B_DQS WR:\n"); - } else { - printk(BIOS_DEBUG, "TrainDQSRdWrPos: CH_D_DIR_B_DQS RD:\n"); - } - for (ChannelDTD = 0; ChannelDTD < 2; ChannelDTD++) { - printk(BIOS_DEBUG, "Channel: %02x\n", ChannelDTD); - for (ReceiverDTD = 0; ReceiverDTD < MAX_CS_SUPPORTED; ReceiverDTD += 2) { - printk(BIOS_DEBUG, "\t\tReceiver: %02x:", ReceiverDTD); - p = pDCTstat->CH_D_DIR_B_DQS[ChannelDTD][ReceiverDTD >> 1][Dir]; - for (i = 0; i < 8; i++) { - val = p[i]; - printk(BIOS_DEBUG, " %02x", val); - } - printk(BIOS_DEBUG, "\n"); - } - } - } - - } -#endif - } - - /* Return 1 on success, 0 on failure */ - return !Errors; -} - -/* DQS Receiver Enable Cycle Training - * Algorithm detailed in the Fam15h BKDG Rev. 3.14 section 2.10.5.8.3 - */ -static void TrainDQSReceiverEnCyc_D_Fam15(struct MCTStatStruc *pMCTstat, - struct DCTStatStruc *pDCTstat) -{ - u32 Errors; - u8 Receiver; - u8 _DisableDramECC = 0; - u8 _Wrap32Dis = 0, _SSE2 = 0; - - u32 addr; - CRx_TYPE cr4; - u32 lo, hi; - - uint8_t dct; - uint8_t prev; - uint8_t dimm; - uint8_t lane; - uint32_t dword; - uint32_t rx_en_offset; - uint8_t internal_lane; - uint8_t dct_training_success; - uint8_t lane_success_count; - uint16_t initial_phy_phase_delay[MAX_BYTE_LANES]; - uint16_t current_phy_phase_delay[MAX_BYTE_LANES]; - uint16_t current_read_dqs_delay[MAX_BYTE_LANES]; - uint8_t lane_training_success[MAX_BYTE_LANES]; - uint8_t dqs_results_array[1024]; - - uint16_t ren_step = 0x40; - uint32_t index_reg = 0x98; - uint32_t dev = pDCTstat->dev_dct; - - uint8_t lane_count; - lane_count = get_available_lane_count(pMCTstat, pDCTstat); - - print_debug_dqs("\nTrainDQSReceiverEnCyc: Node_ID ", pDCTstat->Node_ID, 0); - cr4 = read_cr4(); - if (cr4 & (1<<9)) { - _SSE2 = 1; - } - cr4 |= (1<<9); /* OSFXSR enable SSE2 */ - write_cr4(cr4); - - addr = HWCR_MSR; - _RDMSR(addr, &lo, &hi); - if (lo & (1<<17)) { - _Wrap32Dis = 1; - } - lo |= (1<<17); /* HWCR.wrap32dis */ - _WRMSR(addr, lo, hi); /* allow 64-bit memory references in real mode */ - - /* Disable ECC correction of reads on the dram bus. */ - _DisableDramECC = mct_DisableDimmEccEn_D(pMCTstat, pDCTstat); - - Errors = 0; - - for (dct = 0; dct < 2; dct++) { - /* Program D18F2x9C_x0D0F_E003_dct[1:0][DisAutoComp, DisablePredriverCal] */ - /* NOTE: DisablePredriverCal only takes effect when set on DCT 0 */ - dword = Get_NB32_index_wait_DCT(dev, dct, index_reg, 0x0d0fe003); - dword &= ~(0x3 << 13); - dword |= (0x1 << 13); - Set_NB32_index_wait_DCT(dev, dct, index_reg, 0x0d0fe003, dword); - } - - for (dct = 0; dct < 2; dct++) { - /* 2.10.5.6 */ - fam15EnableTrainingMode(pMCTstat, pDCTstat, dct, 1); - - /* 2.10.5.8.3 */ - Receiver = mct_InitReceiver_D(pDCTstat, dct); - - /* Indicate success unless training the DCT explicitly fails */ - dct_training_success = 1; - - /* There are four receiver pairs, loosely associated with chipselects. - * This is essentially looping over each DIMM. - */ - for (; Receiver < 8; Receiver += 2) { - dimm = (Receiver >> 1); - - if (!mct_RcvrRankEnabled_D(pMCTstat, pDCTstat, dct, Receiver)) { - continue; - } - - /* Initialize variables */ - memset(lane_training_success, 0, sizeof(lane_training_success)); - memset(current_phy_phase_delay, 0, sizeof(current_phy_phase_delay)); - - /* 2.10.5.8.3 (2) */ - read_dqs_receiver_enable_control_registers(initial_phy_phase_delay, dev, dct, dimm, index_reg); - - /* Reset the read data timing registers to 1UI before calculating MaxRdLatency */ - for (internal_lane = 0; internal_lane < MAX_BYTE_LANES; internal_lane++) - current_read_dqs_delay[internal_lane] = 0x20; - write_dqs_read_data_timing_registers(current_read_dqs_delay, dev, dct, dimm, index_reg); - - for (lane = 0; lane < lane_count; lane++) { - /* Initialize variables */ - memset(dqs_results_array, 0, sizeof(dqs_results_array)); - lane_success_count = 0; - - /* 2.10.5.8.3 (1) */ - dword = Get_NB32_index_wait_DCT(dev, dct, index_reg, 0x0d0f0030 | (lane << 8)); - dword |= (0x1 << 8); /* BlockRxDqsLock = 1 */ - Set_NB32_index_wait_DCT(dev, dct, index_reg, 0x0d0f0030 | (lane << 8), dword); - - /* 2.10.5.8.3 (3) */ - rx_en_offset = (initial_phy_phase_delay[lane] + 0x10) % 0x40; - - /* 2.10.5.8.3 (4) */ -#if DQS_TRAIN_DEBUG > 0 - printk(BIOS_DEBUG, "TrainDQSReceiverEnCyc_D_Fam15 Receiver %d lane %d initial phy delay %04x: iterating from %04x to %04x\n", Receiver, lane, initial_phy_phase_delay[lane], rx_en_offset, 0x3ff); -#endif - for (current_phy_phase_delay[lane] = rx_en_offset; current_phy_phase_delay[lane] < 0x3ff; current_phy_phase_delay[lane] += ren_step) { -#if DQS_TRAIN_DEBUG > 0 - printk(BIOS_DEBUG, "%s: Receiver %d lane %d current phy delay: %04x\n", __func__, Receiver, lane, current_phy_phase_delay[lane]); -#endif - - /* 2.10.5.8.3 (4 A) */ - write_dqs_receiver_enable_control_registers(current_phy_phase_delay, dev, dct, dimm, index_reg); - - /* Calculate and program MaxRdLatency */ - Calc_SetMaxRdLatency_D_Fam15(pMCTstat, pDCTstat, dct, 0); - - /* 2.10.5.8.3 (4 B) */ - dqs_results_array[current_phy_phase_delay[lane]] = - TrainDQSRdWrPos_D_Fam15(pMCTstat, pDCTstat, dct, - Receiver, Receiver + 2, - lane); - - if (dqs_results_array[current_phy_phase_delay[lane]]) - lane_success_count++; - - /* Don't bother testing larger values if the end of the passing window was already found */ - if (!dqs_results_array[current_phy_phase_delay[lane]] && (lane_success_count > 1)) - break; - } - - uint16_t phase_delay; - for (phase_delay = 0; phase_delay < 0x3ff; phase_delay++) - if (dqs_results_array[phase_delay]) - lane_training_success[lane] = 1; - - if (!lane_training_success[lane]) { - if (pDCTstat->tcwl_delay[dct] >= 1) { - Errors |= 1 << SB_FatalError; - printk(BIOS_ERR, "%s: lane %d failed to train! " - "Training for receiver %d on DCT %d aborted\n", - __func__, lane, Receiver, dct); - } - - /* Restore BlockRxDqsLock setting to normal operation in preparation for retraining */ - dword = Get_NB32_index_wait_DCT(dev, dct, index_reg, 0x0d0f0030 | (lane << 8)); - dword &= ~(0x1 << 8); /* BlockRxDqsLock = 0 */ - Set_NB32_index_wait_DCT(dev, dct, index_reg, 0x0d0f0030 | (lane << 8), dword); - - break; - } - -#ifdef PRINT_PASS_FAIL_BITMAPS - for (phase_delay = 0; phase_delay < 0x3ff; phase_delay++) { - if (dqs_results_array[phase_delay]) - printk(BIOS_DEBUG, "+"); - else - printk(BIOS_DEBUG, "."); - } - printk(BIOS_DEBUG, "\n"); -#endif - - /* 2.10.5.8.3 (5) */ - prev = dqs_results_array[rx_en_offset]; - for (current_phy_phase_delay[lane] = rx_en_offset + ren_step; current_phy_phase_delay[lane] < 0x3ff; current_phy_phase_delay[lane] += ren_step) { - if ((dqs_results_array[current_phy_phase_delay[lane]] == 0) && (prev == 1)) { - /* Restore last known good delay */ - current_phy_phase_delay[lane] -= ren_step; - - /* 2.10.5.8.3 (5 A B) */ - if (current_phy_phase_delay[lane] < 0x10) - current_phy_phase_delay[lane] = 0x0; - else - current_phy_phase_delay[lane] -= 0x10; - - /* Update hardware registers with final values */ - write_dqs_receiver_enable_control_registers(current_phy_phase_delay, dev, dct, dimm, index_reg); - TrainDQSRdWrPos_D_Fam15(pMCTstat, pDCTstat, dct, - Receiver, Receiver + 2, - lane); - break; - } - prev = dqs_results_array[current_phy_phase_delay[lane]]; - } - - /* 2.10.5.8.3 (6) */ - dword = Get_NB32_index_wait_DCT(dev, dct, index_reg, 0x0d0f0030 | (lane << 8)); - dword &= ~(0x1 << 8); /* BlockRxDqsLock = 0 */ - Set_NB32_index_wait_DCT(dev, dct, index_reg, 0x0d0f0030 | (lane << 8), dword); - } - - for (lane = 0; lane < lane_count; lane++) { - if (!lane_training_success[lane]) { - dct_training_success = 0; - Errors |= 1 << SB_NODQSPOS; - } - } - -#if DQS_TRAIN_DEBUG > 0 - printk(BIOS_DEBUG, "TrainDQSReceiverEnCyc_D_Fam15 DQS receiver enable timing: "); - for (lane = 0; lane < lane_count; lane++) { - printk(BIOS_DEBUG, " %03x", current_phy_phase_delay[lane]); - } - printk(BIOS_DEBUG, "\n"); -#endif - } - - if (!dct_training_success) { - if (pDCTstat->tcwl_delay[dct] < 1) { - /* Increase TCWL */ - pDCTstat->tcwl_delay[dct]++; - /* Request retraining */ - Errors |= 1 << SB_RetryConfigTrain; - } - } - } - - pDCTstat->TrainErrors |= Errors; - pDCTstat->ErrStatus |= Errors; - -#if DQS_TRAIN_DEBUG > 0 - { - u8 val; - u8 i; - u8 ChannelDTD, ReceiverDTD, Dir; - u8 *p; - - for (Dir = 0; Dir < 2; Dir++) { - if (Dir == 1) { - printk(BIOS_DEBUG, "TrainDQSRdWrPos: CH_D_DIR_B_DQS WR:\n"); - } else { - printk(BIOS_DEBUG, "TrainDQSRdWrPos: CH_D_DIR_B_DQS RD:\n"); - } - for (ChannelDTD = 0; ChannelDTD < 2; ChannelDTD++) { - printk(BIOS_DEBUG, "Channel: %02x\n", ChannelDTD); - for (ReceiverDTD = 0; ReceiverDTD < MAX_CS_SUPPORTED; ReceiverDTD += 2) { - printk(BIOS_DEBUG, "\t\tReceiver: %02x:", ReceiverDTD); - p = pDCTstat->CH_D_DIR_B_DQS[ChannelDTD][ReceiverDTD >> 1][Dir]; - for (i = 0; i < 8; i++) { - val = p[i]; - printk(BIOS_DEBUG, " %02x", val); - } - printk(BIOS_DEBUG, "\n"); - } - } - } - - } -#endif - if (_DisableDramECC) { - mct_EnableDimmEccEn_D(pMCTstat, pDCTstat, _DisableDramECC); - } - if (!_Wrap32Dis) { - addr = HWCR_MSR; - _RDMSR(addr, &lo, &hi); - lo &= ~(1<<17); /* restore HWCR.wrap32dis */ - _WRMSR(addr, lo, hi); - } - if (!_SSE2) { - cr4 = read_cr4(); - cr4 &= ~(1<<9); /* restore cr4.OSFXSR */ - write_cr4(cr4); - } - - printk(BIOS_DEBUG, "TrainDQSReceiverEnCyc: Status %x\n", pDCTstat->Status); - printk(BIOS_DEBUG, "TrainDQSReceiverEnCyc: TrainErrors %x\n", pDCTstat->TrainErrors); - printk(BIOS_DEBUG, "TrainDQSReceiverEnCyc: ErrStatus %x\n", pDCTstat->ErrStatus); - printk(BIOS_DEBUG, "TrainDQSReceiverEnCyc: ErrCode %x\n", pDCTstat->ErrCode); - printk(BIOS_DEBUG, "TrainDQSReceiverEnCyc: Done\n\n"); -} - -static void SetupDqsPattern_D(struct MCTStatStruc *pMCTstat, - struct DCTStatStruc *pDCTstat, u32 *buffer) -{ - /* 1. Set the Pattern type (0 or 1) in DCTStatstruc.Pattern - * 2. Copy the pattern from ROM to Cache, aligning on 16 byte boundary - * 3. Set the ptr to Cacheable copy in DCTStatstruc.PtrPatternBufA - */ - - u32 *buf; - u16 i; - - buf = (u32 *)(((u32)buffer + 0x10) & (0xfffffff0)); - if (pDCTstat->Status & (1<Pattern = 1; /* 18 cache lines, alternating qwords */ - for (i = 0; i < 16*18; i++) - buf[i] = TestPatternJD1b_D[i]; - } else { - pDCTstat->Pattern = 0; /* 9 cache lines, sequential qwords */ - for (i = 0; i < 16*9; i++) - buf[i] = TestPatternJD1a_D[i]; - } - pDCTstat->PtrPatternBufA = (u32)buf; -} - -static void StoreDQSDatStrucVal_D(struct MCTStatStruc *pMCTstat, - struct DCTStatStruc *pDCTstat, u8 ChipSel) -{ - /* Store the DQSDelay value, found during a training sweep, into the DCT - * status structure for this node - */ - - /* When 400, 533, 667, it will support dimm0/1/2/3, - * and set conf for dimm0, hw will copy to dimm1/2/3 - * set for dimm1, hw will copy to dimm3 - * Rev A/B only support DIMM0/1 when 800MHz and above + 0x100 to next dimm - * Rev C support DIMM0/1/2/3 when 800MHz and above + 0x100 to next dimm - */ - - /* FindDQSDatDimmVal_D is not required since we use an array */ - u8 dn = 0; - - dn = ChipSel>>1; /* if odd or even logical DIMM */ - - pDCTstat->CH_D_DIR_B_DQS[pDCTstat->Channel][dn][pDCTstat->Direction][pDCTstat->ByteLane] = - pDCTstat->DQSDelay; -} - -static void GetDQSDatStrucVal_D(struct MCTStatStruc *pMCTstat, - struct DCTStatStruc *pDCTstat, u8 ChipSel) -{ - u8 dn = 0; - - /* When 400, 533, 667, it will support dimm0/1/2/3, - * and set conf for dimm0, hw will copy to dimm1/2/3 - * set for dimm1, hw will copy to dimm3 - * Rev A/B only support DIMM0/1 when 800MHz and above + 0x100 to next dimm - * Rev C support DIMM0/1/2/3 when 800MHz and above + 0x100 to next dimm - */ - - /* FindDQSDatDimmVal_D is not required since we use an array */ - dn = ChipSel >> 1; /*if odd or even logical DIMM */ - - pDCTstat->DQSDelay = - pDCTstat->CH_D_DIR_B_DQS[pDCTstat->Channel][dn][pDCTstat->Direction][pDCTstat->ByteLane]; -} - -/* FindDQSDatDimmVal_D is not required since we use an array */ - -void proc_IOCLFLUSH_D(u32 addr_hi) -{ - SetTargetWTIO_D(addr_hi); - proc_CLFLUSH(addr_hi); - ResetTargetWTIO_D(); -} - -u8 ChipSelPresent_D(struct MCTStatStruc *pMCTstat, - struct DCTStatStruc *pDCTstat, - u8 Channel, u8 ChipSel) -{ - u32 val; - u32 reg; - u32 dev = pDCTstat->dev_dct; - uint8_t dct = 0; - u8 ret = 0; - - if (!pDCTstat->GangedMode) - dct = Channel; - else - dct = 0; - - if (ChipSel < MAX_CS_SUPPORTED) { - reg = 0x40 + (ChipSel << 2); - val = Get_NB32_DCT(dev, dct, reg); - if (val & (1 << 0)) - ret = 1; - } - - return ret; -} - -/* proc_CLFLUSH_D located in mct_gcc.h */ - -static void WriteDQSTestPattern_D(struct MCTStatStruc *pMCTstat, - struct DCTStatStruc *pDCTstat, - u32 TestAddr_lo) -{ - /* Write a pattern of 72 bit times (per DQ), to test dram functionality. - * The pattern is a stress pattern which exercises both ISI and - * crosstalk. The number of cache lines to fill is dependent on DCT - * width mode and burstlength. - * Mode BL Lines Pattern no. - * ----+---+------------------- - * 64 4 9 0 - * 64 8 9 0 - * 64M 4 9 0 - * 64M 8 9 0 - * 128 4 18 1 - * 128 8 N/A - - */ - if (pDCTstat->Pattern == 0) - WriteL9TestPattern_D(pDCTstat, TestAddr_lo); - else - WriteL18TestPattern_D(pDCTstat, TestAddr_lo); -} - -static void WriteL18TestPattern_D(struct DCTStatStruc *pDCTstat, - u32 TestAddr_lo) -{ - u8 *buf; - - buf = (u8 *)pDCTstat->PtrPatternBufA; - WriteLNTestPattern(TestAddr_lo, buf, 18); - -} - -static void WriteL9TestPattern_D(struct DCTStatStruc *pDCTstat, - u32 TestAddr_lo) -{ - u8 *buf; - - buf = (u8 *)pDCTstat->PtrPatternBufA; - WriteLNTestPattern(TestAddr_lo, buf, 9); -} - -static u16 CompareDQSTestPattern_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstat, u32 addr_lo) -{ - /* Compare a pattern of 72 bit times (per DQ), to test dram functionality. - * The pattern is a stress pattern which exercises both ISI and - * crosstalk. The number of cache lines to fill is dependent on DCT - * width mode and burstlength. - * Mode BL Lines Pattern no. - * ----+---+------------------- - * 64 4 9 0 - * 64 8 9 0 - * 64M 4 9 0 - * 64M 8 9 0 - * 128 4 18 1 - * 128 8 N/A - - */ - - u32 *test_buf; - u16 MEn1Results, bitmap; - u8 bytelane; - u8 i; - u32 value; - u8 j; - u32 value_test; - u32 value_r = 0, value_r_test = 0; - u8 pattern, channel, BeatCnt; - struct DCTStatStruc *ptrAddr; - - ptrAddr = pDCTstat; - pattern = pDCTstat->Pattern; - channel = pDCTstat->Channel; - test_buf = (u32 *)pDCTstat->PtrPatternBufA; - - if (pattern && channel) { - addr_lo += 8; /* second channel */ - test_buf += 2; - } - - bytelane = 0; /* bytelane counter */ - bitmap = 0xFFFF; /* bytelane test bitmap, 1 = pass */ - MEn1Results = 0xFFFF; - BeatCnt = 0; - for (i = 0; i < (9 * 64 / 4); i++) { /* sizeof testpattern. /4 due to next loop */ - value = read32_fs(addr_lo); - value_test = *test_buf; - - print_debug_dqs_pair("\t\t\t\t\t\ttest_buf = ", (u32)test_buf, " value = ", value_test, 7); - print_debug_dqs_pair("\t\t\t\t\t\ttaddr_lo = ", addr_lo, " value = ", value, 7); - - if (pDCTstat->Direction == DQS_READDIR) { - if (BeatCnt != 0) { - value_r = *test_buf; - if (pattern) /* if multi-channel */ - value_r_test = read32_fs(addr_lo - 16); - else - value_r_test = read32_fs(addr_lo - 8); - } - print_debug_dqs_pair("\t\t\t\t\t\t\ttest_buf = ", (u32)test_buf, " value_r_test = ", value_r, 7); - print_debug_dqs_pair("\t\t\t\t\t\t\ttaddr_lo = ", addr_lo, " value_r = ", value_r_test, 7); - } - - for (j = 0; j < (4 * 8); j += 8) { /* go through a 32bit data, on 1 byte step. */ - if (((value >> j) & 0xff) != ((value_test >> j) & 0xff)) { - bitmap &= ~(1 << bytelane); - } - - if (pDCTstat->Direction == DQS_READDIR) { - if (BeatCnt != 0) { - if (((value_r >> j) & 0xff) != ((value_r_test >> j) & 0xff)) { - MEn1Results &= ~(1 << bytelane); - } - } - } - bytelane++; - bytelane &= 0x7; - } - - print_debug_dqs("\t\t\t\t\t\tbitmap = ", bitmap, 7); - print_debug_dqs("\t\t\t\t\t\tMEn1Results = ", MEn1Results, 7); - - if (!bitmap) - break; - - if (bytelane == 0) { - BeatCnt += 4; - if (!(pDCTstat->Status & (1 << SB_128bitmode))) { - if (BeatCnt == 8) BeatCnt = 0; /* 8 beat burst */ - } else { - if (BeatCnt == 4) BeatCnt = 0; /* 4 beat burst */ - } - if (pattern == 1) { /* dual channel */ - addr_lo += 8; /* skip over other channel's data */ - test_buf += 2; - } - } - addr_lo += 4; - test_buf += 1; - } - - if (pDCTstat->Direction == DQS_READDIR) { - bitmap &= 0xFF; - bitmap |= MEn1Results << 8; - } - - print_debug_dqs("\t\t\t\t\t\tbitmap = ", bitmap, 6); - - return bitmap; -} - -static void FlushDQSTestPattern_D(struct DCTStatStruc *pDCTstat, - u32 addr_lo) -{ - /* Flush functions in mct_gcc.h */ - if (pDCTstat->Pattern == 0) { - FlushDQSTestPattern_L9(addr_lo); - } else { - FlushDQSTestPattern_L18(addr_lo); - } -} - -void SetTargetWTIO_D(u32 TestAddr) -{ - u32 lo, hi; - hi = TestAddr >> 24; - lo = TestAddr << 8; - _WRMSR(MTRR_IORR0_BASE, lo, hi); /* IORR0 Base */ - hi = 0xFF; - lo = 0xFC000800; /* 64MB Mask */ - _WRMSR(MTRR_IORR0_MASK, lo, hi); /* IORR0 Mask */ -} - -void ResetTargetWTIO_D(void) -{ - u32 lo, hi; - - hi = 0; - lo = 0; - _WRMSR(MTRR_IORR0_MASK, lo, hi); /* IORR0 Mask */ -} - -u32 SetUpperFSbase(u32 addr_hi) -{ - /* Set the upper 32-bits of the Base address, 4GB aligned) for the - * FS selector. - */ - u32 lo, hi; - u32 addr; - lo = 0; - hi = addr_hi>>24; - addr = FS_Base; - _WRMSR(addr, lo, hi); - return addr_hi << 8; -} - -void ResetDCTWrPtr_D(u32 dev, uint8_t dct, u32 index_reg, u32 index) -{ - u32 val; - - val = Get_NB32_index_wait_DCT(dev, dct, index_reg, index); - Set_NB32_index_wait_DCT(dev, dct, index_reg, index, val); -} - -void mct_TrainDQSPos_D(struct MCTStatStruc *pMCTstat, - struct DCTStatStruc *pDCTstatA) -{ - u8 Node; - u8 ChipSel; - struct DCTStatStruc *pDCTstat; - - for (Node = 0; Node < MAX_NODES_SUPPORTED; Node++) { - pDCTstat = pDCTstatA + Node; - if (pDCTstat->DCTSysLimit) { - if (is_fam15h()) { - TrainDQSReceiverEnCyc_D_Fam15(pMCTstat, pDCTstat); - } else { - TrainDQSRdWrPos_D_Fam10(pMCTstat, pDCTstat); - for (ChipSel = 0; ChipSel < MAX_CS_SUPPORTED; ChipSel += 2) { - SetEccDQSRdWrPos_D_Fam10(pMCTstat, pDCTstat, ChipSel); - } - } - } - } -} - -/* mct_BeforeTrainDQSRdWrPos_D - * Function is inline. - */ -u8 mct_DisableDimmEccEn_D(struct MCTStatStruc *pMCTstat, - struct DCTStatStruc *pDCTstat) -{ - u8 _DisableDramECC = 0; - u32 val; - u32 reg; - u32 dev; - - /*Disable ECC correction of reads on the dram bus. */ - - dev = pDCTstat->dev_dct; - reg = 0x90; - val = Get_NB32_DCT(dev, 0, reg); - if (val & (1<GangedMode) { - val = Get_NB32_DCT(dev, 1, reg); - if (val & (1<dev_dct; - - if ((_DisableDramECC & 0x01) == 0x01) { - val = Get_NB32_DCT(dev, 0, 0x90); - val |= (1<DQSDelay; - u32 dev = pDCTstat->dev_dct; - u32 index; - - ByteLane = pDCTstat->ByteLane; - - if (!(pDCTstat->DqsRdWrPos_Saved & (1 << ByteLane))) { - /* Channel is offset */ - if (ByteLane < 4) { - index = 1; - } else if (ByteLane <8) { - index = 2; - } else { - index = 3; - } - - if (pDCTstat->Direction == DQS_READDIR) { - index += 4; - } - - /* get the proper register index */ - shift = ByteLane % 4; - shift <<= 3; /* get bit position of bytelane, 8 bit */ - - index += (ChipSel>>1) << 8; - - val = Get_NB32_index_wait_DCT(dev, pDCTstat->Channel, index_reg, index); - if (ByteLane < 8) { - if (pDCTstat->Direction == DQS_WRITEDIR) { - dqs_delay += pDCTstat->persistentData.CH_D_B_TxDqs[pDCTstat->Channel][ChipSel>>1][ByteLane]; - } else { - dqs_delay <<= 1; - } - } - val &= ~(0x7f << shift); - val |= (dqs_delay << shift); - Set_NB32_index_wait_DCT(dev, pDCTstat->Channel, index_reg, index, val); - } -} - -u8 mct_RcvrRankEnabled_D(struct MCTStatStruc *pMCTstat, - struct DCTStatStruc *pDCTstat, - u8 Channel, u8 ChipSel) -{ - u8 ret; - - ret = ChipSelPresent_D(pMCTstat, pDCTstat, Channel, ChipSel); - return ret; -} - -u32 mct_GetRcvrSysAddr_D(struct MCTStatStruc *pMCTstat, - struct DCTStatStruc *pDCTstat, - u8 channel, u8 receiver, u8 *valid) -{ - return mct_GetMCTSysAddr_D(pMCTstat, pDCTstat, channel, receiver, valid); -} - -u32 mct_GetMCTSysAddr_D(struct MCTStatStruc *pMCTstat, - struct DCTStatStruc *pDCTstat, - u8 Channel, u8 receiver, u8 *valid) -{ - u32 val; - uint8_t dct = 0; - u32 reg; - u32 dword; - u32 dev = pDCTstat->dev_dct; - - *valid = 0; - - - if (!pDCTstat->GangedMode) { - dct = Channel; - } - - /* get the local base addr of the chipselect */ - reg = 0x40 + (receiver << 2); - val = Get_NB32_DCT(dev, dct, reg); - - val &= ~0xe007c01f; - - /* unganged mode DCT0+DCT1, sys addr of DCT1 = node - * base+DctSelBaseAddr+local ca base*/ - if ((Channel) && (pDCTstat->GangedMode == 0) && (pDCTstat->DIMMValidDCT[0] > 0)) { - reg = 0x110; - dword = Get_NB32(dev, reg); - dword &= 0xfffff800; - dword <<= 8; /* scale [47:27] of F2x110[31:11] to [39:8]*/ - val += dword; - - /* if DCTSelBaseAddr < Hole, and eax > HoleBase, then add Hole size to test address */ - if ((val >= pDCTstat->DCTHoleBase) && (pDCTstat->DCTHoleBase > dword)) { - dword = (~(pDCTstat->DCTHoleBase >> (24 - 8)) + 1) & 0xFF; - dword <<= (24 - 8); - val += dword; - } - } else { - /* sys addr = node base+local cs base */ - val += pDCTstat->DCTSysBase; - - /* New stuff */ - if (pDCTstat->DCTHoleBase && (val >= pDCTstat->DCTHoleBase)) { - val -= pDCTstat->DCTSysBase; - dword = Get_NB32(pDCTstat->dev_map, 0xF0); /* get Hole Offset */ - val += (dword & 0x0000ff00) << (24-8-8); - } - } - - /* New stuff */ - val += ((1 << 21) >> 8); /* Add 2MB offset to avoid compat area */ - if (val >= MCT_TRNG_KEEPOUT_START) { - while (val < MCT_TRNG_KEEPOUT_END) - val += (1 << (15-8)); /* add 32K */ - } - - /* Add a node seed */ - val += (((1 * pDCTstat->Node_ID) << 20) >> 8); /* Add 1MB per node to avoid aliases */ - - /* HW remap disabled? */ - if (!(pDCTstat->Status & (1 << SB_HWHole))) { - if (!(pDCTstat->Status & (1 << SB_SWNodeHole))) { - /* SW memhole disabled */ - u32 lo, hi; - _RDMSR(TOP_MEM, &lo, &hi); - lo >>= 8; - if ((val >= lo) && (val < _4GB_RJ8)) { - val = 0; - *valid = 0; - goto exitGetAddr; - } else { - *valid = 1; - goto exitGetAddrWNoError; - } - } else { - *valid = 1; - goto exitGetAddrWNoError; - } - } else { - *valid = 1; - goto exitGetAddrWNoError; - } - -exitGetAddrWNoError: - - /* Skip if Address is in UMA region */ - dword = pMCTstat->Sub4GCacheTop; - dword >>= 8; - if (dword != 0) { - if ((val >= dword) && (val < _4GB_RJ8)) { - val = 0; - *valid = 0; - } else { - *valid = 1; - } - } - print_debug_dqs("mct_GetMCTSysAddr_D: receiver ", receiver, 2); - print_debug_dqs("mct_GetMCTSysAddr_D: Channel ", Channel, 2); - print_debug_dqs("mct_GetMCTSysAddr_D: base_addr ", val, 2); - print_debug_dqs("mct_GetMCTSysAddr_D: valid ", *valid, 2); - print_debug_dqs("mct_GetMCTSysAddr_D: status ", pDCTstat->Status, 2); - print_debug_dqs("mct_GetMCTSysAddr_D: SysBase ", pDCTstat->DCTSysBase, 2); - print_debug_dqs("mct_GetMCTSysAddr_D: HoleBase ", pDCTstat->DCTHoleBase, 2); - print_debug_dqs("mct_GetMCTSysAddr_D: Cachetop ", pMCTstat->Sub4GCacheTop, 2); - -exitGetAddr: - return val; -} - -void mct_Write1LTestPattern_D(struct MCTStatStruc *pMCTstat, - struct DCTStatStruc *pDCTstat, - u32 TestAddr, u8 pattern) -{ - - u8 *buf; - - /* Issue the stream of writes. When F2x11C[MctWrLimit] is reached - * (or when F2x11C[FlushWr] is set again), all the writes are written - * to DRAM. - */ - - SetUpperFSbase(TestAddr); - - if (pattern) - buf = (u8 *)pDCTstat->PtrPatternBufB; - else - buf = (u8 *)pDCTstat->PtrPatternBufA; - - WriteLNTestPattern(TestAddr << 8, buf, 1); -} - -void mct_Read1LTestPattern_D(struct MCTStatStruc *pMCTstat, - struct DCTStatStruc *pDCTstat, u32 addr) -{ - u32 value; - - /* BIOS issues the remaining (Ntrain - 2) reads after checking that - * F2x11C[PrefDramTrainMode] is cleared. These reads must be to - * consecutive cache lines (i.e., 64 bytes apart) and must not cross - * a naturally aligned 4KB boundary. These reads hit the prefetches and - * read the data from the prefetch buffer. - */ - - /* get data from DIMM */ - SetUpperFSbase(addr); - - /* 1st move causes read fill (to exclusive or shared)*/ - value = read32_fs(addr << 8); -} diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mctecc_d.c b/src/northbridge/amd/amdmct/mct_ddr3/mctecc_d.c deleted file mode 100644 index 4c33b9e4b6..0000000000 --- a/src/northbridge/amd/amdmct/mct_ddr3/mctecc_d.c +++ /dev/null @@ -1,389 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2010 Advanced Micro Devices, Inc. - * Copyright (C) 2015 - 2016 Raptor Engineering, LLC - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include -#include - -#include "mct_d.h" -#include "mct_d_gcc.h" - -static void setSyncOnUnEccEn_D(struct MCTStatStruc *pMCTstat, - struct DCTStatStruc *pDCTstatA); -static u8 isDramECCEn_D(struct DCTStatStruc *pDCTstat); - -static uint8_t is_fam15h(void) -{ - uint8_t fam15h = 0; - uint32_t family; - - family = cpuid_eax(0x80000001); - family = ((family & 0xf00000) >> 16) | ((family & 0xf00) >> 8); - - if (family >= 0x6f) - /* Family 15h or later */ - fam15h = 1; - - return fam15h; -} - -/* Initialize ECC modes of Integrated Dram+Memory Controllers of a network of - * Hammer processors. Use Dram background scrubber to fast initialize ECC bits - * of all dram. - * - * Notes: - * - * Order that items are set: - * 1. eccen bit in NB - * 2. Scrub Base - * 3. Temp Node Base - * 4. Temp Node Limit - * 5. Redir bit in NB - * 6. Scrub CTL - * - * Conditions for setting background scrubber. - * 1. node is present - * 2. node has dram functioning (WE = RE = 1) - * 3. all eccdimms (or bit 17 of offset 90,fn 2) - * 4. no chip-select gap exists - * - * The dram background scrubber is used under very controlled circumstances to - * initialize all the ECC bits on the DIMMs of the entire dram address map - * (including hidden or lost dram and dram above 4GB). We will turn the scrub - * rate up to maximum, which should clear 4GB of dram in about 2.7 seconds. - * We will activate the scrubbers of all nodes with ecc dram and let them run in - * parallel, thereby reducing even further the time required to condition dram. - * Finally, we will go through each node and either disable background scrubber, - * or set the scrub rate to the user setup specified rate. - * - * To allow the NB to scrub, we need to wait a time period long enough to - * guarantee that the NB scrubs the entire dram on its node. Do do this, we - * simply sample the scrub ADDR once, for an initial value, then we sample and poll until the polled value of scrub ADDR - * has wrapped around at least once: Scrub ADDRi+1 < Scrub ADDRi. Since we let all - * Nodes run in parallel, we need to guarantee that all nodes have wrapped. To do - * this efficiently, we need only to sample one of the nodes, the node with the - * largest ammount of dram populated is the one which will take the longest amount - * of time (the scrub rate is set to max, the same rate, on all nodes). So, - * during setup of scrub Base, we determine how much memory and which node has - * the largest memory installed. - * - * Scrubbing should not ordinarily be enabled on a Node with a chip-select gap - * (aka SW memhole, cs hoisting, etc..).To init ECC memory on this node, the - * scrubber is used in two steps. First, the Dram Limit for the node is adjusted - * down to the bottom of the gap, and that ECC dram is initialized. Second, the - * original Limit is restored, the Scrub base is set to 4GB, and scrubber is - * allowed to run until the Scrub Addr wraps around to zero. - */ -u8 ECCInit_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstatA) -{ - u8 Node; - u8 AllECC; - u16 OB_NBECC; - u32 curBase; - u16 OB_ECCRedir; - u32 LDramECC; - u32 OF_ScrubCTL; - u16 OB_ChipKill; - u8 MemClrECC; - - u32 dev; - u32 reg; - u32 val; - u16 nvbits; - - uint32_t dword; - uint8_t sync_flood_on_dram_err[MAX_NODES_SUPPORTED]; - uint8_t sync_flood_on_any_uc_err[MAX_NODES_SUPPORTED]; - - mctHookBeforeECC(); - - /* Construct these booleans, based on setup options, for easy handling - later in this procedure */ - OB_NBECC = mctGet_NVbits(NV_NBECC); /* MCA ECC (MCE) enable bit */ - - OB_ECCRedir = mctGet_NVbits(NV_ECCRedir); /* ECC Redirection */ - - OB_ChipKill = mctGet_NVbits(NV_ChipKill); /* ECC Chip-kill mode */ - OF_ScrubCTL = 0; /* Scrub CTL for Dcache, L2, and dram */ - - if (!is_fam15h()) { - nvbits = mctGet_NVbits(NV_DCBKScrub); - /* mct_AdjustScrub_D(pDCTstatA, &nvbits); */ /* Need not adjust */ - OF_ScrubCTL |= (u32) nvbits << 16; - - nvbits = mctGet_NVbits(NV_L2BKScrub); - OF_ScrubCTL |= (u32) nvbits << 8; - } - - nvbits = mctGet_NVbits(NV_L3BKScrub); - OF_ScrubCTL |= (nvbits & 0x1f) << 24; /* L3Scrub = NV_L3BKScrub */ - - nvbits = mctGet_NVbits(NV_DramBKScrub); - OF_ScrubCTL |= nvbits; /* DramScrub = NV_DramBKScrub */ - - /* Prevent lockups on DRAM errors during ECC init */ - for (Node = 0; Node < MAX_NODES_SUPPORTED; Node++) { - struct DCTStatStruc *pDCTstat; - pDCTstat = pDCTstatA + Node; - - if (NodePresent_D(Node)) { - dword = Get_NB32(pDCTstat->dev_nbmisc, 0x44); - sync_flood_on_dram_err[Node] = (dword >> 30) & 0x1; - sync_flood_on_any_uc_err[Node] = (dword >> 21) & 0x1; - dword &= ~(0x1 << 30); - dword &= ~(0x1 << 21); - Set_NB32(pDCTstat->dev_nbmisc, 0x44, dword); - - uint32_t mc4_status_high = pci_read_config32(pDCTstat->dev_nbmisc, 0x4c); - uint32_t mc4_status_low = pci_read_config32(pDCTstat->dev_nbmisc, 0x48); - if ((mc4_status_high & (0x1 << 31)) && (mc4_status_high != 0xffffffff)) { - printk(BIOS_WARNING, "WARNING: MC4 Machine Check Exception detected!\n" - "Signature: %08x%08x\n", mc4_status_high, mc4_status_low); - } - - /* Clear MC4 error status */ - pci_write_config32(pDCTstat->dev_nbmisc, 0x48, 0x0); - pci_write_config32(pDCTstat->dev_nbmisc, 0x4c, 0x0); - } - } - - AllECC = 1; - MemClrECC = 0; - for (Node = 0; Node < MAX_NODES_SUPPORTED; Node++) { - struct DCTStatStruc *pDCTstat; - pDCTstat = pDCTstatA + Node; - LDramECC = 0; - if (NodePresent_D(Node)) { /*If Node is present */ - dev = pDCTstat->dev_map; - reg = 0x40+(Node << 3); /* Dram Base Node 0 + index */ - val = Get_NB32(dev, reg); - - /* WE/RE is checked */ - if ((val & 3) == 3) { /* Node has dram populated */ - /* Negate 'all nodes/dimms ECC' flag if non ecc - memory populated */ - if (pDCTstat->Status & (1 << SB_ECCDIMMs)) { - LDramECC = isDramECCEn_D(pDCTstat); - if (pDCTstat->ErrCode != SC_RunningOK) { - pDCTstat->Status &= ~(1 << SB_ECCDIMMs); - if (!OB_NBECC) { - pDCTstat->ErrStatus |= (1 << SB_DramECCDis); - } - AllECC = 0; - LDramECC = 0; - } - } else { - AllECC = 0; - } - if (LDramECC) { /* if ECC is enabled on this dram */ - if (OB_NBECC) { - mct_EnableDatIntlv_D(pMCTstat, pDCTstat); - val = Get_NB32(pDCTstat->dev_dct, 0x110); - val |= 1 << 5; /* DctDatIntLv = 1 */ - Set_NB32(pDCTstat->dev_dct, 0x110, val); - dev = pDCTstat->dev_nbmisc; - reg = 0x44; /* MCA NB Configuration */ - val = Get_NB32(dev, reg); - val |= 1 << 22; /* EccEn */ - Set_NB32(dev, reg, val); - DCTMemClr_Init_D(pMCTstat, pDCTstat); - MemClrECC = 1; - printk(BIOS_DEBUG, " ECC enabled on node: %02x\n", Node); - } - } /* this node has ECC enabled dram */ - - if (MemClrECC) { - DCTMemClr_Sync_D(pMCTstat, pDCTstat); - } - } else { - LDramECC = 0; - } /* Node has Dram */ - } /* if Node present */ - } - - if (AllECC) - pMCTstat->GStatus |= 1 << GSB_ECCDIMMs; - else - pMCTstat->GStatus &= ~(1 << GSB_ECCDIMMs); - - /* Program the Dram BKScrub CTL to the proper (user selected) value.*/ - /* Reset MC4_STS. */ - for (Node = 0; Node < MAX_NODES_SUPPORTED; Node++) { - struct DCTStatStruc *pDCTstat; - pDCTstat = pDCTstatA + Node; - LDramECC = 0; - if (NodePresent_D(Node)) { /* If Node is present */ - reg = 0x40+(Node << 3); /* Dram Base Node 0 + index */ - val = Get_NB32(pDCTstat->dev_map, reg); - curBase = val & 0xffff0000; - /*WE/RE is checked because memory config may have been */ - if ((val & 3) == 3) { /* Node has dram populated */ - if (isDramECCEn_D(pDCTstat)) { /* if ECC is enabled on this dram */ - dev = pDCTstat->dev_nbmisc; - val = curBase << 8; - if (OB_ECCRedir) { - val |= (1 << 0); /* Enable redirection */ - } - Set_NB32(dev, 0x5c, val); /* Dram Scrub Addr Low */ - val = curBase >> 24; - Set_NB32(dev, 0x60, val); /* Dram Scrub Addr High */ - - /* Set scrub rate controls */ - if (is_fam15h()) { - /* Erratum 505 */ - fam15h_switch_dct(pDCTstat->dev_map, 0); - } - Set_NB32(dev, 0x58, OF_ScrubCTL); /* Scrub Control */ - if (is_fam15h()) { - fam15h_switch_dct(pDCTstat->dev_map, 1); /* Erratum 505 */ - Set_NB32(dev, 0x58, OF_ScrubCTL); /* Scrub Control */ - fam15h_switch_dct(pDCTstat->dev_map, 0); /* Erratum 505 */ - } - - if (!is_fam15h()) { - /* Divisor should not be set deeper than - * divide by 16 when Dcache scrubber or - * L2 scrubber is enabled. - */ - if ((OF_ScrubCTL & (0x1F << 16)) || (OF_ScrubCTL & (0x1F << 8))) { - val = Get_NB32(dev, 0x84); - if ((val & 0xE0000000) > 0x80000000) { /* Get F3x84h[31:29]ClkDivisor for C1 */ - val &= 0x1FFFFFFF; /* If ClkDivisor is deeper than divide-by-16 */ - val |= 0x80000000; /* set it to divide-by-16 */ - Set_NB32(dev, 0x84, val); - } - } - } - - if (pDCTstat->LogicalCPUID & (AMD_DR_GT_D0 | AMD_FAM15_ALL)) { - /* Set up message triggered C1E */ - val = pci_read_config32(pDCTstat->dev_nbmisc, 0xd4); - val &= ~(0x1 << 15); /* StutterScrubEn = DRAM scrub enabled */ - val |= (mctGet_NVbits(NV_DramBKScrub)?1:0) << 15; - pci_write_config32(pDCTstat->dev_nbmisc, 0xd4, val); - } - } /* this node has ECC enabled dram */ - } /*Node has Dram */ - } /*if Node present */ - } - - /* Restore previous MCA error handling settings */ - for (Node = 0; Node < MAX_NODES_SUPPORTED; Node++) { - struct DCTStatStruc *pDCTstat; - pDCTstat = pDCTstatA + Node; - - if (NodePresent_D(Node)) { - dev = pDCTstat->dev_map; - reg = 0x40 + (Node << 3); /* Dram Base Node 0 + index */ - val = Get_NB32(dev, reg); - - /* WE/RE is checked */ - if ((val & 0x3) == 0x3) { /* Node has dram populated */ - uint32_t mc4_status_high = pci_read_config32(pDCTstat->dev_nbmisc, 0x4c); - uint32_t mc4_status_low = pci_read_config32(pDCTstat->dev_nbmisc, 0x48); - if ((mc4_status_high & (0x1 << 31)) && (mc4_status_high != 0xffffffff)) { - printk(BIOS_WARNING, "WARNING: MC4 Machine Check Exception detected!\n" - "Signature: %08x%08x\n", mc4_status_high, mc4_status_low); - } - - /* Clear MC4 error status */ - pci_write_config32(pDCTstat->dev_nbmisc, 0x48, 0x0); - pci_write_config32(pDCTstat->dev_nbmisc, 0x4c, 0x0); - - /* Restore previous MCA error handling settings */ - dword = Get_NB32(pDCTstat->dev_nbmisc, 0x44); - dword |= (sync_flood_on_dram_err[Node] & 0x1) << 30; - dword |= (sync_flood_on_any_uc_err[Node] & 0x1) << 21; - Set_NB32(pDCTstat->dev_nbmisc, 0x44, dword); - } - } - } - - if (mctGet_NVbits(NV_SyncOnUnEccEn)) - setSyncOnUnEccEn_D(pMCTstat, pDCTstatA); - - mctHookAfterECC(); - for (Node = 0; Node < MAX_NODES_SUPPORTED; Node++) { - struct DCTStatStruc *pDCTstat; - pDCTstat = pDCTstatA + Node; - if (NodePresent_D(Node)) { - printk(BIOS_DEBUG, "ECCInit: Node %02x\n", Node); - printk(BIOS_DEBUG, "ECCInit: Status %x\n", pDCTstat->Status); - printk(BIOS_DEBUG, "ECCInit: ErrStatus %x\n", pDCTstat->ErrStatus); - printk(BIOS_DEBUG, "ECCInit: ErrCode %x\n", pDCTstat->ErrCode); - printk(BIOS_DEBUG, "ECCInit: Done\n"); - } - } - return MemClrECC; -} - -static void setSyncOnUnEccEn_D(struct MCTStatStruc *pMCTstat, - struct DCTStatStruc *pDCTstatA) -{ - u32 Node; - u32 reg; - u32 dev; - u32 val; - - for (Node = 0; Node < MAX_NODES_SUPPORTED; Node++) { - struct DCTStatStruc *pDCTstat; - pDCTstat = pDCTstatA + Node; - if (NodePresent_D(Node)) { /* If Node is present*/ - reg = 0x40+(Node << 3); /* Dram Base Node 0 + index*/ - val = Get_NB32(pDCTstat->dev_map, reg); - /*WE/RE is checked because memory config may have been*/ - if ((val & 3) == 3) { /* Node has dram populated*/ - if (isDramECCEn_D(pDCTstat)) { - /*if ECC is enabled on this dram*/ - dev = pDCTstat->dev_nbmisc; - reg = 0x44; /* MCA NB Configuration*/ - val = Get_NB32(dev, reg); - val |= (1 << SyncOnUcEccEn); - Set_NB32(dev, reg, val); - } - } /* Node has Dram*/ - } /* if Node present*/ - } -} - -static u8 isDramECCEn_D(struct DCTStatStruc *pDCTstat) -{ - u32 reg; - u32 val; - u8 i; - u32 dev = pDCTstat->dev_dct; - u8 ch_end; - u8 isDimmECCEn = 0; - - if (pDCTstat->GangedMode) { - ch_end = 1; - } else { - ch_end = 2; - } - for (i = 0; i < ch_end; i++) { - if (pDCTstat->DIMMValidDCT[i] > 0) { - reg = 0x90; /* Dram Config Low */ - val = Get_NB32_DCT(dev, i, reg); - if (val & (1 << DimmEcEn)) { - /* set local flag 'dram ecc capable' */ - isDimmECCEn = 1; - break; - } - } - } - return isDimmECCEn; -} diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mcthdi.c b/src/northbridge/amd/amdmct/mct_ddr3/mcthdi.c deleted file mode 100644 index c821ec0628..0000000000 --- a/src/northbridge/amd/amdmct/mct_ddr3/mcthdi.c +++ /dev/null @@ -1,33 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2010 Advanced Micro Devices, Inc. - * Copyright (C) 2015 Timothy Pearson , Raptor Engineering - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include "mct_d.h" -#include "mct_d_gcc.h" - -void mct_DramInit_Hw_D(struct MCTStatStruc *pMCTstat, - struct DCTStatStruc *pDCTstat, u8 dct) -{ - u32 val; - u32 reg; - u32 dev = pDCTstat->dev_dct; - - /*flag for selecting HW/SW DRAM Init HW DRAM Init */ - reg = 0x90; /*DRAM Configuration Low */ - val = Get_NB32_DCT(dev, dct, reg); - val |= (1<, Raptor Engineering - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include -#include -#include "mct_d.h" -#include "mct_d_gcc.h" - -static uint8_t is_fam15h(void) -{ - uint8_t fam15h = 0; - uint32_t family; - - family = cpuid_eax(0x80000001); - family = ((family & 0xf00000) >> 16) | ((family & 0xf00) >> 8); - - if (family >= 0x6f) - /* Family 15h or later */ - fam15h = 1; - - return fam15h; -} - -static void SetEccWrDQS_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstat) -{ - u8 ByteLane, DimmNum, OddByte, Addl_Index, Channel; - u8 EccRef1, EccRef2, EccDQSScale; - u32 val; - u16 word; - - for (Channel = 0; Channel < 2; Channel ++) { - for (DimmNum = 0; DimmNum < C_MAX_DIMMS; DimmNum ++) { /* we use DimmNum instead of DimmNumx3 */ - for (ByteLane = 0; ByteLane < 9; ByteLane ++) { - /* Get RxEn initial value from WrDqs */ - if (ByteLane & 1) - OddByte = 1; - else - OddByte = 0; - if (ByteLane < 2) - Addl_Index = 0x30; - else if (ByteLane < 4) - Addl_Index = 0x31; - else if (ByteLane < 6) - Addl_Index = 0x40; - else if (ByteLane < 8) - Addl_Index = 0x41; - else - Addl_Index = 0x32; - Addl_Index += DimmNum * 3; - - val = Get_NB32_index_wait_DCT(pDCTstat->dev_dct, Channel, 0x98, Addl_Index); - if (OddByte) - val >>= 16; - /* Save WrDqs to stack for later usage */ - pDCTstat->persistentData.CH_D_B_TxDqs[Channel][DimmNum][ByteLane] = val & 0xFF; - EccDQSScale = pDCTstat->CH_EccDQSScale[Channel]; - word = pDCTstat->CH_EccDQSLike[Channel]; - if ((word & 0xFF) == ByteLane) EccRef1 = val & 0xFF; - if (((word >> 8) & 0xFF) == ByteLane) EccRef2 = val & 0xFF; - } - } - } -} - -static void EnableAutoRefresh_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstat) -{ - u32 val; - - val = Get_NB32_DCT(pDCTstat->dev_dct, 0, 0x8C); - val &= ~(1 << DisAutoRefresh); - Set_NB32_DCT(pDCTstat->dev_dct, 0, 0x8C, val); - - val = Get_NB32_DCT(pDCTstat->dev_dct, 1, 0x8C); - val &= ~(1 << DisAutoRefresh); - Set_NB32_DCT(pDCTstat->dev_dct, 1, 0x8C, val); -} - -static void DisableAutoRefresh_D(struct MCTStatStruc *pMCTstat, - struct DCTStatStruc *pDCTstat) -{ - u32 val; - - val = Get_NB32_DCT(pDCTstat->dev_dct, 0, 0x8C); - val |= 1 << DisAutoRefresh; - Set_NB32_DCT(pDCTstat->dev_dct, 0, 0x8C, val); - - val = Get_NB32_DCT(pDCTstat->dev_dct, 1, 0x8C); - val |= 1 << DisAutoRefresh; - Set_NB32_DCT(pDCTstat->dev_dct, 1, 0x8C, val); -} - - -static uint8_t PhyWLPass1(struct MCTStatStruc *pMCTstat, - struct DCTStatStruc *pDCTstat, u8 dct) -{ - u8 dimm; - u16 DIMMValid; - uint8_t status = 0; - void *DCTPtr; - - dct &= 1; - - DCTPtr = (void *)(pDCTstat->C_DCTPtr[dct]); - pDCTstat->DIMMValid = pDCTstat->DIMMValidDCT[dct]; - pDCTstat->CSPresent = pDCTstat->CSPresent_DCT[dct]; - - if (pDCTstat->GangedMode & 1) - pDCTstat->CSPresent = pDCTstat->CSPresent_DCT[0]; - - if (pDCTstat->DIMMValid) { - DIMMValid = pDCTstat->DIMMValid; - PrepareC_DCT(pMCTstat, pDCTstat, dct); - for (dimm = 0; dimm < MAX_DIMMS_SUPPORTED; dimm ++) { - if (DIMMValid & (1 << (dimm << 1))) { - status |= AgesaHwWlPhase1(pMCTstat, pDCTstat, dct, dimm, FirstPass); - status |= AgesaHwWlPhase2(pMCTstat, pDCTstat, dct, dimm, FirstPass); - status |= AgesaHwWlPhase3(pMCTstat, pDCTstat, dct, dimm, FirstPass); - } - } - } - - return status; -} - -static uint8_t PhyWLPass2(struct MCTStatStruc *pMCTstat, - struct DCTStatStruc *pDCTstat, uint8_t dct, uint8_t final) -{ - u8 dimm; - u16 DIMMValid; - uint8_t status = 0; - void *DCTPtr; - - dct &= 1; - - DCTPtr = (void *)&(pDCTstat->C_DCTPtr[dct]); /* todo: */ - pDCTstat->DIMMValid = pDCTstat->DIMMValidDCT[dct]; - pDCTstat->CSPresent = pDCTstat->CSPresent_DCT[dct]; - - if (pDCTstat->GangedMode & 1) - pDCTstat->CSPresent = pDCTstat->CSPresent_DCT[0]; - - if (pDCTstat->DIMMValid) { - DIMMValid = pDCTstat->DIMMValid; - PrepareC_DCT(pMCTstat, pDCTstat, dct); - pDCTstat->Speed = pDCTstat->DIMMAutoSpeed = pDCTstat->TargetFreq; - pDCTstat->CASL = pDCTstat->DIMMCASL = pDCTstat->TargetCASL; - SPD2ndTiming(pMCTstat, pDCTstat, dct); - if (!is_fam15h()) { - ProgDramMRSReg_D(pMCTstat, pDCTstat, dct); - PlatformSpec_D(pMCTstat, pDCTstat, dct); - fenceDynTraining_D(pMCTstat, pDCTstat, dct); - } - Restore_OnDimmMirror(pMCTstat, pDCTstat); - StartupDCT_D(pMCTstat, pDCTstat, dct); - Clear_OnDimmMirror(pMCTstat, pDCTstat); - SetDllSpeedUp_D(pMCTstat, pDCTstat, dct); - DisableAutoRefresh_D(pMCTstat, pDCTstat); - for (dimm = 0; dimm < MAX_DIMMS_SUPPORTED; dimm ++) { - if (DIMMValid & (1 << (dimm << 1))) { - status |= AgesaHwWlPhase1(pMCTstat, pDCTstat, dct, dimm, SecondPass); - status |= AgesaHwWlPhase2(pMCTstat, pDCTstat, dct, dimm, SecondPass); - status |= AgesaHwWlPhase3(pMCTstat, pDCTstat, dct, dimm, SecondPass); - } - } - } - - return status; -} - -static uint16_t fam15h_next_highest_memclk_freq(uint16_t memclk_freq) -{ - uint16_t fam15h_next_highest_freq_tab[] = {0, 0, 0, 0, 0x6, 0, 0xa, 0, 0, 0, 0xe, 0, 0, 0, 0x12, 0, 0, 0, 0x16, 0, 0, 0, 0x16}; - return fam15h_next_highest_freq_tab[memclk_freq]; -} - -/* Write Levelization Training - * Algorithm detailed in the Fam10h BKDG Rev. 3.62 section 2.8.9.9.1 - */ -static void WriteLevelization_HW(struct MCTStatStruc *pMCTstat, - struct DCTStatStruc *pDCTstatA, uint8_t Node, uint8_t Pass) -{ - uint8_t status; - uint8_t timeout; - uint16_t final_target_freq; - - struct DCTStatStruc *pDCTstat; - pDCTstat = pDCTstatA + Node; - - pDCTstat->C_MCTPtr = &(pDCTstat->s_C_MCTPtr); - pDCTstat->C_DCTPtr[0] = &(pDCTstat->s_C_DCTPtr[0]); - pDCTstat->C_DCTPtr[1] = &(pDCTstat->s_C_DCTPtr[1]); - - /* Disable auto refresh by configuring F2x[1, 0]8C[DisAutoRefresh] = 1 */ - DisableAutoRefresh_D(pMCTstat, pDCTstat); - - /* Disable ZQ calibration short command by F2x[1,0]94[ZqcsInterval]=00b */ - DisableZQcalibration(pMCTstat, pDCTstat); - PrepareC_MCT(pMCTstat, pDCTstat); - - if (pDCTstat->GangedMode & (1 << 0)) { - pDCTstat->DIMMValidDCT[1] = pDCTstat->DIMMValidDCT[0]; - } - - if (Pass == FirstPass) { - timeout = 0; - do { - status = 0; - timeout++; - status |= PhyWLPass1(pMCTstat, pDCTstat, 0); - status |= PhyWLPass1(pMCTstat, pDCTstat, 1); - if (status) - printk(BIOS_INFO, - "%s: Retrying write levelling due to invalid value(s) detected in first phase\n", - __func__); - } while (status && (timeout < 8)); - if (status) - printk(BIOS_INFO, - "%s: Uncorrectable invalid value(s) detected in first phase of write levelling\n", - __func__); - } - - if (Pass == SecondPass) { - if (pDCTstat->TargetFreq > mhz_to_memclk_config(mctGet_NVbits(NV_MIN_MEMCLK))) { - /* 8.Prepare the memory subsystem for the target MEMCLK frequency. - * NOTE: BIOS must program both DCTs to the same frequency. - * NOTE: Fam15h steps the frequency, Fam10h slams the frequency. - */ - uint8_t global_phy_training_status = 0; - final_target_freq = pDCTstat->TargetFreq; - - while (pDCTstat->Speed != final_target_freq) { - if (is_fam15h()) - pDCTstat->TargetFreq = fam15h_next_highest_memclk_freq(pDCTstat->Speed); - else - pDCTstat->TargetFreq = final_target_freq; - SetTargetFreq(pMCTstat, pDCTstatA, Node); - timeout = 0; - do { - status = 0; - timeout++; - status |= PhyWLPass2(pMCTstat, pDCTstat, 0, (pDCTstat->TargetFreq == final_target_freq)); - status |= PhyWLPass2(pMCTstat, pDCTstat, 1, (pDCTstat->TargetFreq == final_target_freq)); - if (status) - printk(BIOS_INFO, - "%s: Retrying write levelling due to invalid value(s) detected in last phase\n", - __func__); - } while (status && (timeout < 8)); - global_phy_training_status |= status; - } - - pDCTstat->TargetFreq = final_target_freq; - - if (global_phy_training_status) - printk(BIOS_WARNING, - "%s: Uncorrectable invalid value(s) detected in second phase of write levelling; " - "continuing but system may be unstable!\n", - __func__); - - uint8_t dct; - for (dct = 0; dct < 2; dct++) { - sDCTStruct *pDCTData = pDCTstat->C_DCTPtr[dct]; - memcpy(pDCTData->WLGrossDelayFinalPass, pDCTData->WLGrossDelayPrevPass, sizeof(pDCTData->WLGrossDelayPrevPass)); - memcpy(pDCTData->WLFineDelayFinalPass, pDCTData->WLFineDelayPrevPass, sizeof(pDCTData->WLFineDelayPrevPass)); - pDCTData->WLCriticalGrossDelayFinalPass = pDCTData->WLCriticalGrossDelayPrevPass; - } - } - } - - SetEccWrDQS_D(pMCTstat, pDCTstat); - EnableAutoRefresh_D(pMCTstat, pDCTstat); - EnableZQcalibration(pMCTstat, pDCTstat); -} - -void mct_WriteLevelization_HW(struct MCTStatStruc *pMCTstat, - struct DCTStatStruc *pDCTstatA, uint8_t Pass) -{ - u8 Node; - - for (Node = 0; Node < MAX_NODES_SUPPORTED; Node++) { - struct DCTStatStruc *pDCTstat; - pDCTstat = pDCTstatA + Node; - - if (pDCTstat->NodePresent) { - mctSMBhub_Init(Node); - Clear_OnDimmMirror(pMCTstat, pDCTstat); - WriteLevelization_HW(pMCTstat, pDCTstatA, Node, Pass); - Restore_OnDimmMirror(pMCTstat, pDCTstat); - } - } -} diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mctmtr_d.c b/src/northbridge/amd/amdmct/mct_ddr3/mctmtr_d.c deleted file mode 100644 index 73370e715b..0000000000 --- a/src/northbridge/amd/amdmct/mct_ddr3/mctmtr_d.c +++ /dev/null @@ -1,256 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2010 Advanced Micro Devices, Inc. - * Copyright (C) 2015 Timothy Pearson , Raptor Engineering - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include -#include - -#include "mct_d.h" -#include "mct_d_gcc.h" - -static void SetMTRRrangeWB_D(u32 Base, u32 *pLimit, u32 *pMtrrAddr); -static void SetMTRRrange_D(u32 Base, u32 *pLimit, u32 *pMtrrAddr, u16 MtrrType); - -void CPUMemTyping_D(struct MCTStatStruc *pMCTstat, - struct DCTStatStruc *pDCTstatA) -{ - /* BSP only. Set the fixed MTRRs for common legacy ranges. - * Set TOP_MEM and TOM2. - * Set some variable MTRRs with WB Uncacheable type. - */ - - u32 Bottom32bIO, Bottom40bIO, Cache32bTOP; - u32 val; - u32 addr; - u32 lo, hi; - - /* Set temporary top of memory from Node structure data. - * Adjust temp top of memory down to accommodate 32-bit IO space. - * Bottom40bIO = top of memory, right justified 8 bits - * (defines dram versus IO space type) - * Bottom32bIO = sub 4GB top of memory, right justified 8 bits - * (defines dram versus IO space type) - * Cache32bTOP = sub 4GB top of WB cacheable memory, - * right justified 8 bits - */ - - val = mctGet_NVbits(NV_BottomIO); - if (val == 0) - val++; - - Bottom32bIO = val << (24-8); - - val = pMCTstat->SysLimit + 1; - if (val <= _4GB_RJ8) { - Bottom40bIO = 0; - if (Bottom32bIO >= val) - Bottom32bIO = val; - } else { - Bottom40bIO = val; - } - - Cache32bTOP = Bottom32bIO; - - /*====================================================================== - Set default values for CPU registers - ======================================================================*/ - - /* NOTE : For coreboot, we don't need to set mtrr enables here because - they are still enable from cache_as_ram.inc */ - - addr = MTRR_FIX_64K_00000; - lo = 0x1E1E1E1E; - hi = lo; - _WRMSR(addr, lo, hi); /* 0 - 512K = WB Mem */ - addr = MTRR_FIX_16K_80000; - _WRMSR(addr, lo, hi); /* 512K - 640K = WB Mem */ - - /*====================================================================== - Set variable MTRR values - ======================================================================*/ - /* NOTE: for coreboot change from 0x200 to 0x204: coreboot is using - 0x200, 0x201 for [1M, CONFIG_TOP_MEM) - 0x202, 0x203 for ROM Caching - */ - addr = MTRR_PHYS_BASE(2); /* MTRR phys base 2*/ - /* use TOP_MEM as limit*/ - /* Limit = TOP_MEM|TOM2*/ - /* Base = 0*/ - printk(BIOS_DEBUG, "\t CPUMemTyping: Cache32bTOP:%x\n", Cache32bTOP); - SetMTRRrangeWB_D(0, &Cache32bTOP, &addr); - /* Base */ - /* Limit */ - /* MtrrAddr */ - if (addr == -1) /* ran out of MTRRs?*/ - pMCTstat->GStatus |= 1<Sub4GCacheTop = Cache32bTOP<<8; - - /*====================================================================== - Set TOP_MEM and TOM2 CPU registers - ======================================================================*/ - addr = TOP_MEM; - lo = Bottom32bIO<<8; - hi = Bottom32bIO>>24; - _WRMSR(addr, lo, hi); - printk(BIOS_DEBUG, "\t CPUMemTyping: Bottom32bIO:%x\n", Bottom32bIO); - printk(BIOS_DEBUG, "\t CPUMemTyping: Bottom40bIO:%x\n", Bottom40bIO); - if (Bottom40bIO) { - hi = Bottom40bIO >> 24; - lo = Bottom40bIO << 8; - addr += 3; /* TOM2 */ - _WRMSR(addr, lo, hi); - } - addr = SYSCFG_MSR; /* SYS_CFG */ - _RDMSR(addr, &lo, &hi); - if (Bottom40bIO) { - lo |= SYSCFG_MSR_TOM2En; /* MtrrTom2En = 1 */ - lo |= SYSCFG_MSR_TOM2WB; /* Tom2ForceMemTypeWB */ - } else { - lo &= ~SYSCFG_MSR_TOM2En; /* MtrrTom2En = 0 */ - lo &= ~SYSCFG_MSR_TOM2WB; /* Tom2ForceMemTypeWB */ - } - _WRMSR(addr, lo, hi); -} - -static void SetMTRRrangeWB_D(u32 Base, u32 *pLimit, u32 *pMtrrAddr) -{ - /*set WB type*/ - SetMTRRrange_D(Base, pLimit, pMtrrAddr, 6); -} - -static void SetMTRRrange_D(u32 Base, u32 *pLimit, u32 *pMtrrAddr, u16 MtrrType) -{ - /* Program MTRRs to describe given range as given cache type. - * Use MTRR pairs starting with the given MTRRphys Base address, - * and use as many as is required up to (excluding) MSR 020C, which - * is reserved for OS. - * - * "Limit" in the context of this procedure is not the numerically - * correct limit, but rather the Last address+1, for purposes of coding - * efficiency and readability. Size of a region is then Limit-Base. - * - * 1. Size of each range must be a power of two - * 2. Each range must be naturally aligned (Base is same as size) - * - * There are two code paths: the ascending path and descending path - * (analogous to bsf and bsr), where the next limit is a function of the - * next set bit in a forward or backward sequence of bits (as a function - * of the Limit). We start with the ascending path, to ensure that - * regions are naturally aligned, then we switch to the descending path - * to maximize MTRR usage efficiency. Base = 0 is a special case where we - * start with the descending path. Correct Mask for region is - * 2comp(Size-1)-1, which is 2comp(Limit-Base-1)-1 - */ - - u32 curBase, curLimit, curSize; - u32 val, valx; - u32 addr; - - val = curBase = Base; - curLimit = *pLimit; - addr = *pMtrrAddr; - while ((addr >= 0x200) && (addr < 0x20C) && (val < *pLimit)) { - /* start with "ascending" code path */ - /* alignment (largest block size)*/ - valx = 1 << bsf(curBase); - curSize = valx; - - /* largest legal limit, given current non-zero range Base*/ - valx += curBase; - if ((curBase == 0) || (*pLimit < valx)) { - /* flop direction to "descending" code path*/ - valx = 1<>24; - val <<= 8; - - /* now program the MTRR */ - val |= MtrrType; /* set cache type (UC or WB)*/ - _WRMSR(addr, val, valx); /* prog. MTRR with current region Base*/ - val = ((~(curSize - 1))+1) - 1; /* Size-1*/ /*Mask = 2comp(Size-1)-1*/ - valx = (val >> 24) | (0xff00); /* GH have 48 bits addr */ - val <<= 8; - val |= (1 << 11); /* set MTRR valid*/ - addr++; - _WRMSR(addr, val, valx); /* prog. MTRR with current region Mask*/ - val = curLimit; - curBase = val; /* next Base = current Limit (loop exit)*/ - addr++; /* next MTRR pair addr */ - } - if (val < *pLimit) { - *pLimit = val; - addr = -1; - } - *pMtrrAddr = addr; -} - -void UMAMemTyping_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstatA) -{ - /* UMA memory size may need splitting the MTRR configuration into two - * Before training use NB_BottomIO or the physical memory size to set the MTRRs. - * After training, add UMAMemTyping function to reconfigure the MTRRs based on - * NV_BottomUMA (for UMA systems only). - * This two-step process allows all memory to be cached for training - */ - - u32 Bottom32bIO, Cache32bTOP; - u32 val; - u32 addr; - u32 lo, hi; - - /*====================================================================== - * Adjust temp top of memory down to accommodate UMA memory start - *======================================================================*/ - /* Bottom32bIO = sub 4GB top of memory, right justified 8 bits - * (defines dram versus IO space type) - * Cache32bTOP = sub 4GB top of WB cacheable memory, right justified 8 bits */ - - Bottom32bIO = pMCTstat->Sub4GCacheTop >> 8; - - val = mctGet_NVbits(NV_BottomUMA); - if (val == 0) - val++; - - val <<= (24-8); - if (val < Bottom32bIO) { - Cache32bTOP = val; - pMCTstat->Sub4GCacheTop = val; - - /*====================================================================== - * Clear variable MTRR values - *======================================================================*/ - addr = MTRR_PHYS_BASE(0); - lo = 0; - hi = lo; - while (addr < MTRR_PHYS_BASE(6)) { - _WRMSR(addr, lo, hi); /* prog. MTRR with current region Mask */ - addr++; /* next MTRR pair addr */ - } - - /*====================================================================== - * Set variable MTRR values - *======================================================================*/ - printk(BIOS_DEBUG, "\t UMAMemTyping_D: Cache32bTOP:%x\n", Cache32bTOP); - SetMTRRrangeWB_D(0, &Cache32bTOP, &addr); - if (addr == -1) /* ran out of MTRRs?*/ - pMCTstat->GStatus |= 1<, Raptor Engineering - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include - -#include "mct_d.h" -#include "mct_d_gcc.h" - -void InterleaveNodes_D(struct MCTStatStruc *pMCTstat, - struct DCTStatStruc *pDCTstatA) -{ - /* Applies Node memory interleaving if enabled and if all criteria are met. */ - u8 Node; - u32 Base; - u32 MemSize, MemSize0 = 0; - u32 Dct0MemSize = 0, DctSelBase, DctSelBaseOffset = 0; - u8 Nodes; - u8 NodesWmem; - u8 DoIntlv; - u8 _NdIntCap; - u8 _SWHole; - u32 HWHoleSz; - u32 DramHoleAddrReg; - u32 HoleBase; - u32 dev0; - u32 reg0; - u32 val; - u8 i; - struct DCTStatStruc *pDCTstat; - - DoIntlv = mctGet_NVbits(NV_NodeIntlv); - - _NdIntCap = 0; - HWHoleSz = 0; /*For HW remapping, NOT Node hoisting. */ - - pDCTstat = pDCTstatA + 0; - dev0 = pDCTstat->dev_host; - Nodes = ((Get_NB32(dev0, 0x60) >> 4) & 0x7) + 1; - - dev0 = pDCTstat->dev_map; - reg0 = 0x40; - - NodesWmem = 0; - Node = 0; - - while (DoIntlv && (Node < Nodes)) { - pDCTstat = pDCTstatA + Node; - if (pMCTstat->GStatus & (1 << GSB_SpIntRemapHole)) { - pMCTstat->GStatus |= 1 << GSB_HWHole; - _SWHole = 0; - } else if (pDCTstat->Status & (1 << SB_SWNodeHole)) { - _SWHole = 1; - } else { - _SWHole = 0; - } - - if (!_SWHole) { - Base = Get_NB32(dev0, reg0); - if (Base & 1) { - NodesWmem++; - Base &= 0xFFFF0000; /* Base[39:8] */ - - if (pDCTstat->Status & (1 << SB_HWHole)) { - - /* to get true amount of dram, - * subtract out memory hole if HW dram remapping */ - DramHoleAddrReg = Get_NB32(pDCTstat->dev_map, 0xF0); - HWHoleSz = DramHoleAddrReg >> 16; - HWHoleSz = (((~HWHoleSz) + 1) & 0xFF); - HWHoleSz <<= 24-8; - } - /* check to see if the amount of memory on each channel - * are the same on all nodes */ - - DctSelBase = Get_NB32(pDCTstat->dev_dct, 0x114); - if (DctSelBase) { - DctSelBase <<= 8; - if (pDCTstat->Status & (1 << SB_HWHole)) { - if (DctSelBase >= 0x1000000) { - DctSelBase -= HWHoleSz; - } - } - DctSelBaseOffset -= Base; - if (Node == 0) { - Dct0MemSize = DctSelBase; - } else if (DctSelBase != Dct0MemSize) { - break; - } - } - - MemSize = Get_NB32(dev0, reg0 + 4); - MemSize &= 0xFFFF0000; - MemSize += 0x00010000; - MemSize -= Base; - if (pDCTstat->Status & (1 << SB_HWHole)) { - MemSize -= HWHoleSz; - } - if (Node == 0) { - MemSize0 = MemSize; - } else if (MemSize0 != MemSize) { - break; - } - } else { - break; - } - } else { - break; - } - Node++; - reg0 += 8; - } - - if (Node == Nodes) { - /* if all nodes have memory and no Node had SW memhole */ - if (Nodes == 2 || Nodes == 4 || Nodes == 8) - _NdIntCap = 1; - } - - if (!_NdIntCap) - DoIntlv = 0; - - if (pMCTstat->GStatus & 1 << (GSB_SpIntRemapHole)) { - HWHoleSz = pMCTstat->HoleBase; - if (HWHoleSz == 0) { - HWHoleSz = mctGet_NVbits(NV_BottomIO) & 0xFF; - HWHoleSz <<= 24-8; - } - HWHoleSz = ((~HWHoleSz) + 1) & 0x00FF0000; - } - - if (DoIntlv) { - MCTMemClr_D(pMCTstat, pDCTstatA); - /* Program Interleaving enabled on Node 0 map only.*/ - MemSize0 <<= bsf(Nodes); /* MemSize = MemSize*2 (or 4, or 8) */ - Dct0MemSize <<= bsf(Nodes); - MemSize0 += HWHoleSz; - Base = ((Nodes - 1) << 8) | 3; - reg0 = 0x40; - Node = 0; - while (Node < Nodes) { - Set_NB32(dev0, reg0, Base); - MemSize = MemSize0; - MemSize--; - MemSize &= 0xFFFF0000; - MemSize |= Node << 8; /* set IntlvSel[2:0] field */ - MemSize |= Node; /* set DstNode[2:0] field */ - Set_NB32(dev0, reg0 + 4, MemSize0); - reg0 += 8; - Node++; - } - - /* set base/limit to F1x120/124 per Node */ - Node = 0; - while (Node < Nodes) { - pDCTstat = pDCTstatA + Node; - pDCTstat->NodeSysBase = 0; - MemSize = MemSize0; - MemSize -= HWHoleSz; - MemSize--; - pDCTstat->NodeSysLimit = MemSize; - Set_NB32(pDCTstat->dev_map, 0x120, Node << 21); - MemSize = MemSize0; - MemSize--; - MemSize >>= 19; - val = Base; - val &= 0x700; - val <<= 13; - val |= MemSize; - Set_NB32(pDCTstat->dev_map, 0x124, val); - - if (pMCTstat->GStatus & (1 << GSB_HWHole)) { - HoleBase = pMCTstat->HoleBase; - if (Dct0MemSize >= HoleBase) { - val = HWHoleSz; - if (Node == 0) { - val += Dct0MemSize; - } - } else { - val = HWHoleSz + Dct0MemSize; - } - - val >>= 8; /* DramHoleOffset */ - HoleBase <<= 8; /* DramHoleBase */ - val |= HoleBase; - val |= 1 << DramMemHoistValid; - val |= 1 << DramHoleValid; - Set_NB32(pDCTstat->dev_map, 0xF0, val); - } - - Set_NB32(pDCTstat->dev_dct, 0x114, Dct0MemSize >> 8); /* DctSelBaseOffset */ - val = Get_NB32(pDCTstat->dev_dct, 0x110); - val &= 0x7FF; - val |= Dct0MemSize >> 8; - Set_NB32(pDCTstat->dev_dct, 0x110, val); /* DctSelBaseAddr */ - printk(BIOS_DEBUG, "InterleaveNodes: DRAM Controller Select Low Register = %x\n", val); - Node++; - } - - /* Copy Node 0 into other Nodes' CSRs */ - Node = 1; - while (Node < Nodes) { - pDCTstat = pDCTstatA + Node; - - for (i = 0x40; i <= 0x80; i++) { - val = Get_NB32(dev0, i); - Set_NB32(pDCTstat->dev_map, i, val); - } - - val = Get_NB32(dev0, 0xF0); - Set_NB32(pDCTstat->dev_map, 0xF0, val); - Node++; - } - pMCTstat->GStatus = (1 << GSB_NodeIntlv); - } - printk(BIOS_DEBUG, "InterleaveNodes_D: Status %x\n", pDCTstat->Status); - printk(BIOS_DEBUG, "InterleaveNodes_D: ErrStatus %x\n", pDCTstat->ErrStatus); - printk(BIOS_DEBUG, "InterleaveNodes_D: ErrCode %x\n", pDCTstat->ErrCode); - printk(BIOS_DEBUG, "InterleaveNodes_D: Done\n\n"); -} diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mctprob.c b/src/northbridge/amd/amdmct/mct_ddr3/mctprob.c deleted file mode 100644 index 3cb75675df..0000000000 --- a/src/northbridge/amd/amdmct/mct_ddr3/mctprob.c +++ /dev/null @@ -1,45 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2010 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include - -#include "mct_d.h" -#include "mct_d_gcc.h" - -void mct_BeforeDQSTrainSamp(struct DCTStatStruc *pDCTstat) -{ - u32 val; - - if (pDCTstat->LogicalCPUID & AMD_DR_Bx) { - Set_NB32(pDCTstat->dev_dct, 0x98, 0x0D004007); - val = Get_NB32(pDCTstat->dev_dct, 0x9C); - val |= 0x3FF; - Set_NB32(pDCTstat->dev_dct, 0x9C, val); - Set_NB32(pDCTstat->dev_dct, 0x98, 0x4D0F4F07); - - Set_NB32(pDCTstat->dev_dct, 0x198, 0x0D004007); - val = Get_NB32(pDCTstat->dev_dct, 0x19C); - val |= 0x3FF; - Set_NB32(pDCTstat->dev_dct, 0x19C, val); - Set_NB32(pDCTstat->dev_dct, 0x198, 0x4D0F4F07); - } -} - -void mct_ExtMCTConfig_Bx(struct DCTStatStruc *pDCTstat) -{ - if (pDCTstat->LogicalCPUID & (AMD_DR_Bx)) { - Set_NB32(pDCTstat->dev_dct, 0x11C, 0x0FE40FC0 | 1 << 29/* FlushWrOnStpGnt */); - } -} diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mctproc.c b/src/northbridge/amd/amdmct/mct_ddr3/mctproc.c deleted file mode 100644 index ddaaaab8d5..0000000000 --- a/src/northbridge/amd/amdmct/mct_ddr3/mctproc.c +++ /dev/null @@ -1,113 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2010 Advanced Micro Devices, Inc. - * Copyright (C) 2015 Timothy Pearson , Raptor Engineering - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include - -#include "mct_d.h" -#include "mct_d_gcc.h" - -/* mct_SetDramConfigMisc2_Cx & mct_SetDramConfigMisc2_Dx */ -u32 mct_SetDramConfigMisc2(struct DCTStatStruc *pDCTstat, - uint8_t dct, uint32_t misc2, uint32_t DramControl) -{ - u32 val; - - uint8_t MaxDimmsInstallable = mctGet_NVbits(NV_MAX_DIMMS_PER_CH); - - if (pDCTstat->LogicalCPUID & AMD_FAM15_ALL) { - uint8_t cs_mux_45; - uint8_t cs_mux_67; - uint32_t f2x80; - - misc2 &= ~(0x1 << 28); /* FastSelfRefEntryDis = 0x0 */ - if (MaxDimmsInstallable == 3) { - /* FIXME 3 DIMMS per channel unimplemented */ - cs_mux_45 = 0; - } else { - uint32_t f2x60 = Get_NB32_DCT(pDCTstat->dev_dct, dct, 0x60); - f2x80 = Get_NB32_DCT(pDCTstat->dev_dct, dct, 0x80); - if ((((f2x80 & 0xf) == 0x7) || ((f2x80 & 0xf) == 0x9)) - && ((f2x60 & 0x3) == 0x3)) - cs_mux_45 = 1; - else if ((((f2x80 & 0xf) == 0xa) || ((f2x80 & 0xf) == 0xb)) - && ((f2x60 & 0x3) > 0x1)) - cs_mux_45 = 1; - else - cs_mux_45 = 0; - } - - if (MaxDimmsInstallable == 1) { - cs_mux_67 = 0; - } else if (MaxDimmsInstallable == 2) { - uint32_t f2x64 = Get_NB32_DCT(pDCTstat->dev_dct, dct, 0x64); - f2x80 = Get_NB32_DCT(pDCTstat->dev_dct, dct, 0x80); - if (((((f2x80 >> 4) & 0xf) == 0x7) || (((f2x80 >> 4) & 0xf) == 0x9)) - && ((f2x64 & 0x3) == 0x3)) - cs_mux_67 = 1; - else if (((((f2x80 >> 4) & 0xf) == 0xa) || (((f2x80 >> 4) & 0xf) == 0xb)) - && ((f2x64 & 0x3) > 0x1)) - cs_mux_67 = 1; - else - cs_mux_67 = 0; - } else { - /* FIXME 3 DIMMS per channel unimplemented */ - cs_mux_67 = 0; - } - - misc2 &= ~(0x1 << 27); /* CsMux67 = cs_mux_67 */ - misc2 |= ((cs_mux_67 & 0x1) << 27); - misc2 &= ~(0x1 << 26); /* CsMux45 = cs_mux_45 */ - misc2 |= ((cs_mux_45 & 0x1) << 26); - } else if (pDCTstat->LogicalCPUID & (AMD_DR_Dx | AMD_DR_Cx)) { - if (pDCTstat->Status & (1 << SB_Registered)) { - misc2 |= 1 << SubMemclkRegDly; - if (mctGet_NVbits(NV_MAX_DIMMS) == 8) - misc2 |= 1 << Ddr3FourSocketCh; - else - misc2 &= ~(1 << Ddr3FourSocketCh); - } - - if (pDCTstat->LogicalCPUID & AMD_DR_Cx) - misc2 |= 1 << OdtSwizzle; - - val = DramControl; - val &= 7; - val = ((~val) & 0xff) + 1; - val += 6; - val &= 0x7; - misc2 &= 0xfff8ffff; - misc2 |= val << 16; /* DataTxFifoWrDly */ - if (pDCTstat->LogicalCPUID & AMD_DR_Dx) - misc2 |= 1 << 7; /* ProgOdtEn */ - } - return misc2; -} - -void mct_ExtMCTConfig_Cx(struct DCTStatStruc *pDCTstat) -{ - u32 val; - - if (pDCTstat->LogicalCPUID & (AMD_DR_Cx)) { - /* Revision C */ - Set_NB32(pDCTstat->dev_dct, 0x11c, 0x0ce00fc0 | 1 << 29/* FlushWrOnStpGnt */); - - val = Get_NB32(pDCTstat->dev_dct, 0x1b0); - val &= ~0x73f; - val |= 0x101; /* BKDG recommended settings */ - - Set_NB32(pDCTstat->dev_dct, 0x1b0, val); - } -} diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mctprod.c b/src/northbridge/amd/amdmct/mct_ddr3/mctprod.c deleted file mode 100644 index b203942058..0000000000 --- a/src/northbridge/amd/amdmct/mct_ddr3/mctprod.c +++ /dev/null @@ -1,66 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2015 Timothy Pearson , Raptor Engineering - * Copyright (C) 2010 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include - -#include "mct_d.h" -#include "mct_d_gcc.h" - -void mct_ExtMCTConfig_Dx(struct DCTStatStruc *pDCTstat) -{ - uint32_t dword; - - if (pDCTstat->LogicalCPUID & AMD_DR_Dx) { - dword = 0x0ce00f00 | 0x1 << 29; /* FlushWrOnStpGnt */ - if (!(pDCTstat->GangedMode)) - dword |= 0x18 << 2; /* MctWrLimit = 0x18 for unganged mode */ - else - dword |= 0x10 << 2; /* MctWrLimit = 0x10 for ganged mode */ - Set_NB32(pDCTstat->dev_dct, 0x11c, dword); - - dword = Get_NB32(pDCTstat->dev_dct, 0x1b0); - dword &= ~0x3; /* AdapPrefMissRatio = 0x1 */ - dword |= 0x1; - dword &= ~(0x3 << 2); /* AdapPrefPositiveStep = 0x0 */ - dword &= ~(0x3 << 4); /* AdapPrefNegativeStep = 0x0 */ - dword &= ~(0x7 << 8); /* CohPrefPrbLmt = 0x1 */ - dword |= (0x1 << 8); - dword |= (0x7 << 22); /* PrefFourConf = 0x7 */ - dword |= (0x7 << 25); /* PrefFiveConf = 0x7 */ - - if (!(pDCTstat->GangedMode)) - dword |= (0x1 << 12); /* EnSplitDctLimits = 0x1 */ - else - dword &= ~(0x1 << 12); /* EnSplitDctLimits = 0x0 */ - - dword &= ~(0xf << 28); /* DcqBwThrotWm = ... */ - switch (pDCTstat->Speed) { - case 4: - dword |= (0x5 << 28); /* ...5 for DDR800 */ - break; - case 5: - dword |= (0x6 << 28); /* ...6 for DDR1066 */ - break; - case 6: - dword |= (0x8 << 28); /* ...8 for DDR800 */ - break; - default: - dword |= (0x9 << 28); /* ...9 for DDR1600 */ - break; - } - Set_NB32(pDCTstat->dev_dct, 0x1b0, dword); - } -} diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mctrci.c b/src/northbridge/amd/amdmct/mct_ddr3/mctrci.c deleted file mode 100644 index 93cfb4bf1b..0000000000 --- a/src/northbridge/amd/amdmct/mct_ddr3/mctrci.c +++ /dev/null @@ -1,474 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2010 Advanced Micro Devices, Inc. - * Copyright (C) 2015 - 2016 Raptor Engineering, LLC - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include - -#include "mct_d.h" -#include "mct_d_gcc.h" - -static uint8_t is_fam15h(void) -{ - uint8_t fam15h = 0; - uint32_t family; - - family = cpuid_eax(0x80000001); - family = ((family & 0xf00000) >> 16) | ((family & 0xf00) >> 8); - - if (family >= 0x6f) - /* Family 15h or later */ - fam15h = 1; - - return fam15h; -} - -static uint8_t fam15h_rdimm_rc2_ibt_code(struct DCTStatStruc *pDCTstat, uint8_t dct) -{ - uint8_t MaxDimmsInstallable = mctGet_NVbits(NV_MAX_DIMMS_PER_CH); - - uint8_t package_type; - uint8_t control_code = 0; - - package_type = mctGet_NVbits(NV_PACK_TYPE); - uint16_t MemClkFreq = Get_NB32_DCT(pDCTstat->dev_dct, dct, 0x94) & 0x1f; - - /* Obtain number of DIMMs on channel */ - uint8_t dimm_count = pDCTstat->MAdimms[dct]; - - /* FIXME - * Assume there is only one register on the RDIMM for now - */ - uint8_t num_registers = 1; - - if (package_type == PT_GR) { - /* Socket G34 */ - /* Fam15h BKDG Rev. 3.14 section 2.10.5.7.1.2.1 Table 85 */ - if (MaxDimmsInstallable == 1) { - if ((MemClkFreq == 0x4) || (MemClkFreq == 0x6)) { - /* DDR3-667 - DDR3-800 */ - control_code = 0x1; - } else if ((MemClkFreq == 0xa) || (MemClkFreq == 0xe)) { - /* DDR3-1066 - DDR3-1333 */ - if (num_registers == 1) { - control_code = 0x0; - } else { - control_code = 0x1; - } - } else if ((MemClkFreq == 0x12) || (MemClkFreq == 0x16)) { - /* DDR3-1600 - DDR3-1866 */ - control_code = 0x0; - } - } else if (MaxDimmsInstallable == 2) { - if (dimm_count == 1) { - /* 1 DIMM detected */ - if ((MemClkFreq == 0x4) || (MemClkFreq == 0x6)) { - /* DDR3-667 - DDR3-800 */ - control_code = 0x1; - } else if ((MemClkFreq >= 0xa) && (MemClkFreq <= 0x12)) { - /* DDR3-1066 - DDR3-1600 */ - if (num_registers == 1) { - control_code = 0x0; - } else { - control_code = 0x1; - } - } - } else if (dimm_count == 2) { - /* 2 DIMMs detected */ - if (num_registers == 1) { - control_code = 0x1; - } else { - control_code = 0x8; - } - } - } else if (MaxDimmsInstallable == 3) { - /* TODO - * 3 DIMM/channel support unimplemented - */ - } - } else if (package_type == PT_C3) { - /* Socket C32 */ - /* Fam15h BKDG Rev. 3.14 section 2.10.5.7.1.2.1 Table 86 */ - if (MaxDimmsInstallable == 1) { - if ((MemClkFreq == 0x4) || (MemClkFreq == 0x6)) { - /* DDR3-667 - DDR3-800 */ - control_code = 0x1; - } else if ((MemClkFreq == 0xa) || (MemClkFreq == 0xe)) { - /* DDR3-1066 - DDR3-1333 */ - if (num_registers == 1) { - control_code = 0x0; - } else { - control_code = 0x1; - } - } else if ((MemClkFreq == 0x12) || (MemClkFreq == 0x16)) { - /* DDR3-1600 - DDR3-1866 */ - control_code = 0x0; - } - } else if (MaxDimmsInstallable == 2) { - if (dimm_count == 1) { - /* 1 DIMM detected */ - if ((MemClkFreq == 0x4) || (MemClkFreq == 0x6)) { - /* DDR3-667 - DDR3-800 */ - control_code = 0x1; - } else if ((MemClkFreq >= 0xa) && (MemClkFreq <= 0x12)) { - /* DDR3-1066 - DDR3-1600 */ - if (num_registers == 1) { - control_code = 0x0; - } else { - control_code = 0x1; - } - } - } else if (dimm_count == 2) { - /* 2 DIMMs detected */ - if (num_registers == 1) { - control_code = 0x1; - } else { - control_code = 0x8; - } - } - } else if (MaxDimmsInstallable == 3) { - /* TODO - * 3 DIMM/channel support unimplemented - */ - } - } else { - /* TODO - * Other socket support unimplemented - */ - } - - printk(BIOS_SPEW, "%s: DCT %d IBT code: %01x\n", __func__, dct, control_code); - return control_code; -} - -static uint16_t memclk_to_freq(uint16_t memclk) { - uint16_t fam10h_freq_tab[] = {0, 0, 0, 400, 533, 667, 800}; - uint16_t fam15h_freq_tab[] = {0, 0, 0, 0, 333, 0, 400, 0, 0, 0, 533, 0, 0, 0, 667, 0, 0, 0, 800, 0, 0, 0, 933}; - - uint16_t mem_freq = 0; - - if (is_fam15h()) { - if (memclk < 0x17) { - mem_freq = fam15h_freq_tab[memclk]; - } - } else { - if ((memclk > 0x0) && (memclk < 0x8)) { - mem_freq = fam10h_freq_tab[memclk - 1]; - } - } - - return mem_freq; -} - -static uint8_t rc_word_chip_select_lower_bit(void) { - if (is_fam15h()) { - return 21; - } else { - return 20; - } -} - -static uint32_t rc_word_address_to_ctl_bits(uint32_t address) { - if (is_fam15h()) { - return (((address >> 3) & 0x1) << 2) << 18 | (address & 0x7); - } else { - return (((address >> 3) & 0x1) << 2) << 16 | (address & 0x7); - } -} - -static uint32_t rc_word_value_to_ctl_bits(uint32_t value) { - if (is_fam15h()) { - return ((value >> 2) & 0x3) << 18 | ((value & 0x3) << 3); - } else { - return ((value >> 2) & 0x3) << 16 | ((value & 0x3) << 3); - } -} - -static u32 mct_ControlRC(struct MCTStatStruc *pMCTstat, - struct DCTStatStruc *pDCTstat, uint8_t dct, u32 MrsChipSel, u32 CtrlWordNum) -{ - u8 Dimms, DimmNum; - u32 val; - uint8_t ddr_voltage_index; - uint16_t mem_freq; - uint8_t package_type = mctGet_NVbits(NV_PACK_TYPE); - uint8_t MaxDimmsInstallable = mctGet_NVbits(NV_MAX_DIMMS_PER_CH); - - DimmNum = (MrsChipSel >> rc_word_chip_select_lower_bit()) & 0x7; - - if (dct == 1) - DimmNum++; - - mem_freq = memclk_to_freq(pDCTstat->DIMMAutoSpeed); - Dimms = pDCTstat->MAdimms[dct]; - - ddr_voltage_index = dct_ddr_voltage_index(pDCTstat, dct); - - val = 0; - if (CtrlWordNum == 0) - val = 0x2; - else if (CtrlWordNum == 1) { - if (!((pDCTstat->DimmDRPresent | pDCTstat->DimmQRPresent) & (1 << DimmNum))) - val = 0xc; /* if single rank, set DBA1 and DBA0 */ - } else if (CtrlWordNum == 2) { - if (is_fam15h()) { - val = (fam15h_rdimm_rc2_ibt_code(pDCTstat, dct) & 0x1) << 2; - } else { - if (package_type == PT_GR) { - /* Socket G34 */ - if (MaxDimmsInstallable == 2) { - if (Dimms > 1) - val = 0x4; - } - } - else if (package_type == PT_C3) { - /* Socket C32 */ - if (MaxDimmsInstallable == 2) { - if (Dimms > 1) - val = 0x4; - } - } - } - } else if (CtrlWordNum == 3) { - val = (pDCTstat->CtrlWrd3 >> (DimmNum << 2)) & 0xff; - } else if (CtrlWordNum == 4) { - val = (pDCTstat->CtrlWrd4 >> (DimmNum << 2)) & 0xff; - } else if (CtrlWordNum == 5) { - val = (pDCTstat->CtrlWrd5 >> (DimmNum << 2)) & 0xff; - } else if (CtrlWordNum == 6) { - val = ((pDCTstat->spd_data.spd_bytes[DimmNum][72] & 0xf) >> (DimmNum << 2)) & 0xff; - } else if (CtrlWordNum == 7) { - val = (((pDCTstat->spd_data.spd_bytes[DimmNum][72] >> 4) & 0xf) >> (DimmNum << 2)) & 0xff; - } else if (CtrlWordNum == 8) { - if (is_fam15h()) { - val = (fam15h_rdimm_rc2_ibt_code(pDCTstat, dct) & 0xe) >> 1; - } else { - if (package_type == PT_GR) { - /* Socket G34 */ - if (MaxDimmsInstallable == 2) { - val = 0x0; - } - } - else if (package_type == PT_C3) { - /* Socket C32 */ - if (MaxDimmsInstallable == 2) { - val = 0x0; - } - } - } - } else if (CtrlWordNum == 9) { - val = 0xd; /* DBA1, DBA0, DA3 = 0 */ - } else if (CtrlWordNum == 10) { - val = 0x0; /* Lowest operating frequency */ - } else if (CtrlWordNum == 11) { - if (ddr_voltage_index & 0x4) - val = 0x2; /* 1.25V */ - else if (ddr_voltage_index & 0x2) - val = 0x1; /* 1.35V */ - else - val = 0x0; /* 1.5V */ - } else if (CtrlWordNum == 12) { - val = ((pDCTstat->spd_data.spd_bytes[DimmNum][75] & 0xf) >> (DimmNum << 2)) & 0xff; - } else if (CtrlWordNum == 13) { - val = (((pDCTstat->spd_data.spd_bytes[DimmNum][75] >> 4) & 0xf) >> (DimmNum << 2)) & 0xff; - } else if (CtrlWordNum == 14) { - val = ((pDCTstat->spd_data.spd_bytes[DimmNum][76] & 0xf) >> (DimmNum << 2)) & 0xff; - } else if (CtrlWordNum == 15) { - val = (((pDCTstat->spd_data.spd_bytes[DimmNum][76] >> 4) & 0xf) >> (DimmNum << 2)) & 0xff; - } - val &= 0xf; - - printk(BIOS_SPEW, "%s: Preparing to send DCT %d DIMM %d RC%d: %02x\n", __func__, dct, DimmNum >> 1, CtrlWordNum, val); - - val = MrsChipSel | rc_word_value_to_ctl_bits(val); - val |= rc_word_address_to_ctl_bits(CtrlWordNum); - - return val; -} - -static void mct_SendCtrlWrd(struct MCTStatStruc *pMCTstat, - struct DCTStatStruc *pDCTstat, uint8_t dct, uint32_t val) -{ - u32 dev = pDCTstat->dev_dct; - - val |= Get_NB32_DCT(dev, dct, 0x7c) & ~0xffffff; - val |= 1 << SendControlWord; - Set_NB32_DCT(dev, dct, 0x7c, val); - - do { - val = Get_NB32_DCT(dev, dct, 0x7c); - } while (val & (1 << SendControlWord)); -} - -void mct_DramControlReg_Init_D(struct MCTStatStruc *pMCTstat, - struct DCTStatStruc *pDCTstat, uint8_t dct) -{ - u8 MrsChipSel; - u32 dev = pDCTstat->dev_dct; - u32 val, cw; - - printk(BIOS_SPEW, "%s: Start\n", __func__); - - if (!is_fam15h()) { - mct_Wait(1600); - mct_Wait(1200); - } - - pDCTstat->CSPresent = pDCTstat->CSPresent_DCT[dct]; - if (pDCTstat->GangedMode & 1) - pDCTstat->CSPresent = pDCTstat->CSPresent_DCT[0]; - - for (MrsChipSel = 0; MrsChipSel < 8; MrsChipSel += 2) { - if (pDCTstat->CSPresent & (1 << MrsChipSel)) { - val = Get_NB32_DCT(dev, dct, 0xa8); - val &= ~(0xff << 8); - - switch (MrsChipSel) { - case 0: - case 1: - val |= 3 << 8; - break; - case 2: - case 3: - val |= (3 << 2) << 8; - break; - case 4: - case 5: - val |= (3 << 4) << 8; - break; - case 6: - case 7: - val |= (3 << 6) << 8; - break; - } - Set_NB32_DCT(dev, dct, 0xa8, val); - printk(BIOS_SPEW, "%s: F2xA8: %08x\n", __func__, val); - - if (is_fam15h()) { - for (cw = 0; cw <=15; cw ++) { - val = mct_ControlRC(pMCTstat, pDCTstat, dct, MrsChipSel << rc_word_chip_select_lower_bit(), cw); - mct_SendCtrlWrd(pMCTstat, pDCTstat, dct, val); - if ((cw == 2) || (cw == 8) || (cw == 10)) - precise_ndelay_fam15(pMCTstat, 6000); - } - } else { - for (cw = 0; cw <=15; cw ++) { - mct_Wait(1600); - val = mct_ControlRC(pMCTstat, pDCTstat, dct, MrsChipSel << rc_word_chip_select_lower_bit(), cw); - mct_SendCtrlWrd(pMCTstat, pDCTstat, dct, val); - } - } - } - } - - mct_Wait(1200); - - printk(BIOS_SPEW, "%s: Done\n", __func__); -} - -void FreqChgCtrlWrd(struct MCTStatStruc *pMCTstat, - struct DCTStatStruc *pDCTstat, uint8_t dct) -{ - u32 SaveSpeed = pDCTstat->DIMMAutoSpeed; - u32 MrsChipSel; - u32 dev = pDCTstat->dev_dct; - u32 val; - uint16_t mem_freq; - - pDCTstat->CSPresent = pDCTstat->CSPresent_DCT[dct]; - if (pDCTstat->GangedMode & 1) - pDCTstat->CSPresent = pDCTstat->CSPresent_DCT[0]; - - pDCTstat->DIMMAutoSpeed = pDCTstat->TargetFreq; - mem_freq = memclk_to_freq(pDCTstat->TargetFreq); - for (MrsChipSel = 0; MrsChipSel < 8; MrsChipSel += 2) { - if (pDCTstat->CSPresent & (1 << MrsChipSel)) { - /* 2. Program F2x[1, 0]A8[CtrlWordCS]=bit mask for target chip selects. */ - val = Get_NB32_DCT(dev, dct, 0xa8); - val &= ~(0xff << 8); - - switch (MrsChipSel) { - case 0: - case 1: - val |= 3 << 8; - break; - case 2: - case 3: - val |= (3 << 2) << 8; - break; - case 4: - case 5: - val |= (3 << 4) << 8; - break; - case 6: - case 7: - val |= (3 << 6) << 8; - break; - } - Set_NB32_DCT(dev, dct, 0xa8, val); - - /* Resend control word 10 */ - uint8_t freq_ctl_val = 0; - mct_Wait(1600); - switch (mem_freq) { - case 333: - case 400: - freq_ctl_val = 0x0; - break; - case 533: - freq_ctl_val = 0x1; - break; - case 667: - freq_ctl_val = 0x2; - break; - case 800: - freq_ctl_val = 0x3; - break; - case 933: - freq_ctl_val = 0x4; - break; - } - - printk(BIOS_SPEW, "Preparing to send DCT %d DIMM %d RC%d: %02x (F2xA8: %08x)\n", dct, MrsChipSel >> 1, 10, freq_ctl_val, val); - - mct_SendCtrlWrd(pMCTstat, pDCTstat, dct, (MrsChipSel << rc_word_chip_select_lower_bit()) | rc_word_address_to_ctl_bits(10) | rc_word_value_to_ctl_bits(freq_ctl_val)); - - if (is_fam15h()) - precise_ndelay_fam15(pMCTstat, 6000); - else - mct_Wait(1600); - - /* Resend control word 2 */ - val = mct_ControlRC(pMCTstat, pDCTstat, dct, MrsChipSel << rc_word_chip_select_lower_bit(), 2); - mct_SendCtrlWrd(pMCTstat, pDCTstat, dct, val); - - if (is_fam15h()) - precise_ndelay_fam15(pMCTstat, 6000); - else - mct_Wait(1600); - - /* Resend control word 8 */ - val = mct_ControlRC(pMCTstat, pDCTstat, dct, MrsChipSel << rc_word_chip_select_lower_bit(), 8); - mct_SendCtrlWrd(pMCTstat, pDCTstat, dct, val); - - if (is_fam15h()) - precise_ndelay_fam15(pMCTstat, 6000); - else - mct_Wait(1600); - } - } - pDCTstat->DIMMAutoSpeed = SaveSpeed; -} diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mctsdi.c b/src/northbridge/amd/amdmct/mct_ddr3/mctsdi.c deleted file mode 100644 index f215695580..0000000000 --- a/src/northbridge/amd/amdmct/mct_ddr3/mctsdi.c +++ /dev/null @@ -1,1210 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2010 Advanced Micro Devices, Inc. - * Copyright (C) 2015 Timothy Pearson , Raptor Engineering - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include - -#include "mct_d.h" -#include "mct_d_gcc.h" - -static uint8_t is_fam15h(void) -{ - uint8_t fam15h = 0; - uint32_t family; - - family = cpuid_eax(0x80000001); - family = ((family & 0xf00000) >> 16) | ((family & 0xf00) >> 8); - - if (family >= 0x6f) - /* Family 15h or later */ - fam15h = 1; - - return fam15h; -} - -uint8_t fam15_dimm_dic(struct DCTStatStruc *pDCTstat, uint8_t dct, uint8_t dimm, uint8_t rank, uint8_t package_type) -{ - uint8_t dic; - - /* Calculate DIC based on recommendations in MR1_dct[1:0] */ - if (pDCTstat->Status & (1 << SB_LoadReduced)) { - /* TODO - * LRDIMM unimplemented - */ - dic = 0x0; - } else { - dic = 0x1; - } - - return dic; -} - -uint8_t fam15_rttwr(struct DCTStatStruc *pDCTstat, uint8_t dct, uint8_t dimm, uint8_t rank, uint8_t package_type) -{ - uint8_t term = 0; - uint8_t number_of_dimms = pDCTstat->MAdimms[dct]; - uint8_t frequency_index; - uint8_t rank_count = pDCTstat->DimmRanks[(dimm * 2) + dct]; - - uint8_t rank_count_dimm0; - uint8_t rank_count_dimm1; - uint8_t rank_count_dimm2; - - if (is_fam15h()) - frequency_index = Get_NB32_DCT(pDCTstat->dev_dct, dct, 0x94) & 0x1f; - else - frequency_index = Get_NB32_DCT(pDCTstat->dev_dct, dct, 0x94) & 0x7; - - uint8_t MaxDimmsInstallable = mctGet_NVbits(NV_MAX_DIMMS_PER_CH); - - if (is_fam15h()) { - if (pDCTstat->Status & (1 << SB_LoadReduced)) { - /* TODO - * LRDIMM unimplemented - */ - } else if (pDCTstat->Status & (1 << SB_Registered)) { - /* RDIMM */ - if (package_type == PT_GR) { - /* Socket G34: Fam15h BKDG v3.14 Table 57 */ - if (MaxDimmsInstallable == 1) { - if ((frequency_index == 0x4) || (frequency_index == 0x6) - || (frequency_index == 0xa) || (frequency_index == 0xe)) { - /* DDR3-667 - DDR3-1333 */ - if (rank_count < 3) - term = 0x0; - else - term = 0x2; - } else { - /* DDR3-1600 */ - term = 0x0; - } - } else if (MaxDimmsInstallable == 2) { - rank_count_dimm0 = pDCTstat->DimmRanks[(0 * 2) + dct]; - rank_count_dimm1 = pDCTstat->DimmRanks[(1 * 2) + dct]; - - if ((frequency_index == 0x4) || (frequency_index == 0x6)) { - /* DDR3-667 - DDR3-800 */ - if ((number_of_dimms == 1) && ((rank_count_dimm0 < 4) - && (rank_count_dimm1 < 4))) - term = 0x0; - else - term = 0x2; - } else if (frequency_index == 0xa) { - /* DDR3-1066 */ - if (number_of_dimms == 1) { - if ((rank_count_dimm0 < 4) && (rank_count_dimm1 < 4)) - term = 0x0; - else - term = 0x2; - } else { - term = 0x1; - } - } else if (frequency_index == 0xe) { - /* DDR3-1333 */ - term = 0x2; - } else { - /* DDR3-1600 */ - if (number_of_dimms == 1) - term = 0x0; - else - term = 0x1; - } - } else if (MaxDimmsInstallable == 3) { - rank_count_dimm2 = pDCTstat->DimmRanks[(2 * 2) + dct]; - - if ((frequency_index == 0xa) || (frequency_index == 0xe)) { - /* DDR3-1066 - DDR3-1333 */ - if (rank_count_dimm2 < 4) - term = 0x1; - else - term = 0x2; - } else if (frequency_index == 0x12) { - /* DDR3-1600 */ - term = 0x1; - } else { - term = 0x2; - } - } - } else if (package_type == PT_C3) { - /* Socket C32: Fam15h BKDG v3.14 Table 60 */ - if (MaxDimmsInstallable == 1) { - if ((frequency_index == 0x4) || (frequency_index == 0x6) - || (frequency_index == 0xa) || (frequency_index == 0xe)) { - /* DDR3-667 - DDR3-1333 */ - if (rank_count < 3) - term = 0x0; - else - term = 0x2; - } else { - /* DDR3-1600 */ - term = 0x0; - } - } else if (MaxDimmsInstallable == 2) { - rank_count_dimm0 = pDCTstat->DimmRanks[(0 * 2) + dct]; - rank_count_dimm1 = pDCTstat->DimmRanks[(1 * 2) + dct]; - - if ((frequency_index == 0x4) || (frequency_index == 0x6)) { - /* DDR3-667 - DDR3-800 */ - if ((number_of_dimms == 1) && ((rank_count_dimm0 < 4) - && (rank_count_dimm1 < 4))) - term = 0x0; - else - term = 0x2; - } else if (frequency_index == 0xa) { - /* DDR3-1066 */ - if (number_of_dimms == 1) { - if ((rank_count_dimm0 < 4) && (rank_count_dimm1 < 4)) - term = 0x0; - else - term = 0x2; - } else { - term = 0x1; - } - } else if (frequency_index == 0xe) { - /* DDR3-1333 */ - term = 0x2; - } else { - /* DDR3-1600 */ - if (number_of_dimms == 1) - term = 0x0; - else - term = 0x1; - } - } else if (MaxDimmsInstallable == 3) { - rank_count_dimm2 = pDCTstat->DimmRanks[(2 * 2) + dct]; - - if ((frequency_index == 0xa) || (frequency_index == 0xe)) { - /* DDR3-1066 - DDR3-1333 */ - if (rank_count_dimm2 < 4) - term = 0x1; - else - term = 0x2; - } else if (frequency_index == 0x12) { - /* DDR3-1600 */ - term = 0x1; - } else { - term = 0x2; - } - } - } else { - /* TODO - * Other sockets unimplemented - */ - } - } else { - /* UDIMM */ - if (package_type == PT_GR) { - /* Socket G34: Fam15h BKDG v3.14 Table 56 */ - if (MaxDimmsInstallable == 1) { - term = 0x0; - } else if (MaxDimmsInstallable == 2) { - if ((number_of_dimms == 2) && (frequency_index == 0x12)) { - term = 0x1; - } else if (number_of_dimms == 1) { - term = 0x0; - } else { - term = 0x2; - } - } else if (MaxDimmsInstallable == 3) { - if (number_of_dimms == 1) { - if (frequency_index <= 0xa) { - term = 0x2; - } else { - if (rank_count < 3) { - term = 0x1; - } else { - term = 0x2; - } - } - } else if (number_of_dimms == 2) { - term = 0x2; - } - } - } else if (package_type == PT_C3) { - /* Socket C32: Fam15h BKDG v3.14 Table 59 */ - if (MaxDimmsInstallable == 1) { - term = 0x0; - } else if (MaxDimmsInstallable == 2) { - if ((number_of_dimms == 2) && (frequency_index == 0x12)) { - term = 0x1; - } else if (number_of_dimms == 1) { - term = 0x0; - } else { - term = 0x2; - } - } else if (MaxDimmsInstallable == 3) { - if (number_of_dimms == 1) { - if (frequency_index <= 0xa) { - term = 0x2; - } else { - if (rank_count < 3) { - term = 0x1; - } else { - term = 0x2; - } - } - } else if (number_of_dimms == 2) { - term = 0x2; - } - } - } else if (package_type == PT_FM2) { - /* Socket FM2: Fam15h Model10 BKDG 3.12 Table 32 */ - if (MaxDimmsInstallable == 1) { - term = 0x0; - } else if (MaxDimmsInstallable == 2) { - if ((number_of_dimms == 2) && (frequency_index >= 0x12)) { - term = 0x1; - } else if (number_of_dimms == 1) { - term = 0x0; - } else { - term = 0x2; - } - } - } else { - /* TODO - * Other sockets unimplemented - */ - } - } - } - - printk(BIOS_INFO, "DIMM %d RttWr: %01x\n", dimm, term); - - return term; -} - -uint8_t fam15_rttnom(struct DCTStatStruc *pDCTstat, uint8_t dct, uint8_t dimm, uint8_t rank, uint8_t package_type) -{ - uint8_t term = 0; - uint8_t number_of_dimms = pDCTstat->MAdimms[dct]; - uint8_t frequency_index; - - uint8_t rank_count_dimm0; - uint8_t rank_count_dimm1; - - if (is_fam15h()) - frequency_index = Get_NB32_DCT(pDCTstat->dev_dct, dct, 0x94) & 0x1f; - else - frequency_index = Get_NB32_DCT(pDCTstat->dev_dct, dct, 0x94) & 0x7; - - uint8_t MaxDimmsInstallable = mctGet_NVbits(NV_MAX_DIMMS_PER_CH); - - if (is_fam15h()) { - if (pDCTstat->Status & (1 << SB_LoadReduced)) { - /* TODO - * LRDIMM unimplemented - */ - } else if (pDCTstat->Status & (1 << SB_Registered)) { - /* RDIMM */ - if (package_type == PT_GR) { - /* Socket G34: Fam15h BKDG v3.14 Table 57 */ - if (MaxDimmsInstallable == 1) { - rank_count_dimm0 = pDCTstat->DimmRanks[(0 * 2) + dct]; - - if ((frequency_index == 0x4) || (frequency_index == 0x6)) { - /* DDR3-667 - DDR3-800 */ - if (rank_count_dimm0 < 4) { - term = 0x2; - } else { - if (!rank) - term = 0x2; - else - term = 0x0; - } - } else if (frequency_index == 0xa) { - /* DDR3-1066 */ - term = 0x1; - } else if (frequency_index == 0xe) { - /* DDR3-1333 */ - if (rank_count_dimm0 < 4) { - term = 0x1; - } else { - if (!rank) - term = 0x3; - else - term = 0x0; - } - } else { - term = 0x3; - } - } else if (MaxDimmsInstallable == 2) { - rank_count_dimm0 = pDCTstat->DimmRanks[(0 * 2) + dct]; - rank_count_dimm1 = pDCTstat->DimmRanks[(1 * 2) + dct]; - - if ((frequency_index == 0x4) || (frequency_index == 0x6)) { - /* DDR3-667 - DDR3-800 */ - if (number_of_dimms == 1) { - if ((rank_count_dimm0 < 4) && (rank_count_dimm1 < 4)) - term = 0x2; - else if (rank) - term = 0x0; - else - term = 0x2; - } else { - if ((rank_count_dimm0 < 4) && (rank_count_dimm1 < 4)) { - term = 0x3; - } else { - if (rank_count_dimm0 == 4) { - if (rank_count_dimm1 == 1) - term = 0x5; - else - term = 0x1; - } else if (rank_count_dimm1 == 4) { - if (rank_count_dimm0 == 1) - term = 0x5; - else - term = 0x1; - } - if (rank) - term = 0x0; - } - } - } else if (frequency_index == 0xa) { - /* DDR3-1066 */ - if (number_of_dimms == 1) { - if ((rank_count_dimm0 < 4) && (rank_count_dimm1 < 4)) - term = 0x1; - else if (rank) - term = 0x0; - else - term = 0x1; - } else { - if ((rank_count_dimm0 < 4) && (rank_count_dimm1 < 4)) { - term = 0x3; - } else { - if (rank_count_dimm0 == 4) { - if (rank_count_dimm1 == 1) - term = 0x5; - else - term = 0x1; - } else if (rank_count_dimm1 == 4) { - if (rank_count_dimm0 == 1) - term = 0x5; - else - term = 0x1; - } - if (rank) - term = 0x0; - } - } - } else if (frequency_index == 0xe) { - /* DDR3-1333 */ - if (number_of_dimms == 1) { - if ((rank_count_dimm0 < 4) && (rank_count_dimm1 < 4)) - term = 0x1; - else if (rank) - term = 0x0; - else - term = 0x3; - } else { - term = 0x5; - } - } else { - /* DDR3-1600 */ - if (number_of_dimms == 1) - term = 0x3; - else - term = 0x4; - } - } else if (MaxDimmsInstallable == 3) { - /* TODO - * 3 DIMM/channel support unimplemented - */ - } - } else if (package_type == PT_C3) { - /* Socket C32: Fam15h BKDG v3.14 Table 60 */ - if (MaxDimmsInstallable == 1) { - rank_count_dimm0 = pDCTstat->DimmRanks[(0 * 2) + dct]; - - if ((frequency_index == 0x4) || (frequency_index == 0x6)) { - /* DDR3-667 - DDR3-800 */ - if (rank_count_dimm0 < 4) { - term = 0x2; - } else { - if (!rank) - term = 0x2; - else - term = 0x0; - } - } else if (frequency_index == 0xa) { - /* DDR3-1066 */ - term = 0x1; - } else if (frequency_index == 0xe) { - /* DDR3-1333 */ - if (rank_count_dimm0 < 4) { - term = 0x1; - } else { - if (!rank) - term = 0x3; - else - term = 0x0; - } - } else { - term = 0x3; - } - } else if (MaxDimmsInstallable == 2) { - rank_count_dimm0 = pDCTstat->DimmRanks[(0 * 2) + dct]; - rank_count_dimm1 = pDCTstat->DimmRanks[(1 * 2) + dct]; - - if ((frequency_index == 0x4) || (frequency_index == 0x6)) { - /* DDR3-667 - DDR3-800 */ - if (number_of_dimms == 1) { - if ((rank_count_dimm0 < 4) && (rank_count_dimm1 < 4)) - term = 0x2; - else if (rank) - term = 0x0; - else - term = 0x2; - } else { - if ((rank_count_dimm0 < 4) && (rank_count_dimm1 < 4)) { - term = 0x3; - } else { - if (rank_count_dimm0 == 4) { - if (rank_count_dimm1 == 1) - term = 0x5; - else - term = 0x1; - } else if (rank_count_dimm1 == 4) { - if (rank_count_dimm0 == 1) - term = 0x5; - else - term = 0x1; - } - if (rank) - term = 0x0; - } - } - } else if (frequency_index == 0xa) { - /* DDR3-1066 */ - if (number_of_dimms == 1) { - if ((rank_count_dimm0 < 4) && (rank_count_dimm1 < 4)) - term = 0x1; - else if (rank) - term = 0x0; - else - term = 0x1; - } else { - if ((rank_count_dimm0 < 4) && (rank_count_dimm1 < 4)) { - term = 0x3; - } else { - if (rank_count_dimm0 == 4) { - if (rank_count_dimm1 == 1) - term = 0x5; - else - term = 0x1; - } else if (rank_count_dimm1 == 4) { - if (rank_count_dimm0 == 1) - term = 0x5; - else - term = 0x1; - } - if (rank) - term = 0x0; - } - } - } else if (frequency_index == 0xe) { - /* DDR3-1333 */ - if (number_of_dimms == 1) { - if ((rank_count_dimm0 < 4) && (rank_count_dimm1 < 4)) - term = 0x1; - else if (rank) - term = 0x0; - else - term = 0x3; - } else { - term = 0x5; - } - } else { - /* DDR3-1600 */ - if (number_of_dimms == 1) - term = 0x3; - else - term = 0x4; - } - } else if (MaxDimmsInstallable == 3) { - /* TODO - * 3 DIMM/channel support unimplemented - */ - } - } else { - /* TODO - * Other sockets unimplemented - */ - } - } else { - /* UDIMM */ - if (package_type == PT_GR) { - /* Socket G34: Fam15h BKDG v3.14 Table 56 */ - if (MaxDimmsInstallable == 1) { - if ((frequency_index == 0x4) || (frequency_index == 0x6)) - term = 0x2; - else if ((frequency_index == 0xa) || (frequency_index == 0xe)) - term = 0x1; - else - term = 0x3; - } - if (MaxDimmsInstallable == 2) { - if (number_of_dimms == 1) { - if (frequency_index <= 0x6) { - term = 0x2; - } else if (frequency_index <= 0xe) { - term = 0x1; - } else { - term = 0x3; - } - } else { - if (frequency_index <= 0xa) { - term = 0x3; - } else if (frequency_index <= 0xe) { - term = 0x5; - } else { - term = 0x4; - } - } - } else if (MaxDimmsInstallable == 3) { - if (number_of_dimms == 1) { - term = 0x0; - } else if (number_of_dimms == 2) { - if (frequency_index <= 0xa) { - if (rank == 1) { - term = 0x0; - } else { - term = 0x3; - } - } else if (frequency_index <= 0xe) { - if (rank == 1) { - term = 0x0; - } else { - term = 0x5; - } - } - } - } - } else if (package_type == PT_C3) { - /* Socket C32: Fam15h BKDG v3.14 Table 62 */ - if (MaxDimmsInstallable == 1) { - if ((frequency_index == 0x4) || (frequency_index == 0x6)) - term = 0x2; - else if ((frequency_index == 0xa) || (frequency_index == 0xe)) - term = 0x1; - else - term = 0x3; - } - if (MaxDimmsInstallable == 2) { - if (number_of_dimms == 1) { - if (frequency_index <= 0x6) { - term = 0x2; - } else if (frequency_index <= 0xe) { - term = 0x1; - } else { - term = 0x3; - } - } else { - if (frequency_index <= 0xa) { - term = 0x3; - } else if (frequency_index <= 0xe) { - term = 0x5; - } else { - term = 0x4; - } - } - } else if (MaxDimmsInstallable == 3) { - if (number_of_dimms == 1) { - term = 0x0; - } else if (number_of_dimms == 2) { - if (frequency_index <= 0xa) { - if (rank == 1) { - term = 0x0; - } else { - term = 0x3; - } - } else if (frequency_index <= 0xe) { - if (rank == 1) { - term = 0x0; - } else { - term = 0x5; - } - } - } - } - } else if (package_type == PT_FM2) { - /* Socket FM2: Fam15h Model10 BKDG 3.12 Table 32 */ - if (MaxDimmsInstallable == 1) { - if ((frequency_index == 0x4) - || (frequency_index == 0x6) - || (frequency_index == 0xa)) - term = 0x4; - else if (frequency_index == 0xe) - term = 0x3; - else if (frequency_index >= 0x12) - term = 0x2; - } - if (MaxDimmsInstallable == 2) { - if (number_of_dimms == 1) { - if (frequency_index <= 0xa) { - term = 0x4; - } else if (frequency_index <= 0xe) { - term = 0x3; - } else { - term = 0x2; - } - } else { - if (frequency_index <= 0xa) { - term = 0x2; - } else if (frequency_index <= 0xe) { - term = 0x1; - } else { - term = 0x0; - } - } - } - } else { - /* TODO - * Other sockets unimplemented - */ - } - } - } - - printk(BIOS_INFO, "DIMM %d RttNom: %01x\n", dimm, term); - return term; -} - -static void mct_DCTAccessDone(struct DCTStatStruc *pDCTstat, u8 dct) -{ - u32 dev = pDCTstat->dev_dct; - u32 val; - - printk(BIOS_DEBUG, "%s: Start\n", __func__); - - do { - val = Get_NB32_DCT(dev, dct, 0x98); - } while (!(val & (1 << DctAccessDone))); - - printk(BIOS_DEBUG, "%s: Done\n", __func__); -} - -static u32 swapAddrBits(struct DCTStatStruc *pDCTstat, u32 MR_register_setting, u8 MrsChipSel, u8 dct) -{ - u16 word; - u32 ret; - - if (!(pDCTstat->Status & (1 << SB_Registered))) { - word = pDCTstat->MirrPresU_NumRegR; - if (dct == 0) { - word &= 0x55; - word <<= 1; - } else - word &= 0xAA; - - if (word & (1 << MrsChipSel)) { - /* A3<->A4,A5<->A6,A7<->A8,BA0<->BA1 */ - ret = 0; - if (MR_register_setting & (1 << 3)) ret |= 1 << 4; - if (MR_register_setting & (1 << 4)) ret |= 1 << 3; - if (MR_register_setting & (1 << 5)) ret |= 1 << 6; - if (MR_register_setting & (1 << 6)) ret |= 1 << 5; - if (MR_register_setting & (1 << 7)) ret |= 1 << 8; - if (MR_register_setting & (1 << 8)) ret |= 1 << 7; - if (is_fam15h()) { - if (MR_register_setting & (1 << 18)) ret |= 1 << 19; - if (MR_register_setting & (1 << 19)) ret |= 1 << 18; - MR_register_setting &= ~0x000c01f8; - } else { - if (MR_register_setting & (1 << 16)) ret |= 1 << 17; - if (MR_register_setting & (1 << 17)) ret |= 1 << 16; - MR_register_setting &= ~0x000301f8; - } - MR_register_setting |= ret; - } - } - return MR_register_setting; -} - -static void mct_SendMrsCmd(struct DCTStatStruc *pDCTstat, u8 dct, u32 EMRS) -{ - u32 dev = pDCTstat->dev_dct; - u32 val; - - printk(BIOS_DEBUG, "%s: Start\n", __func__); - - val = Get_NB32_DCT(dev, dct, 0x7c); - val &= ~0x00ffffff; - val |= EMRS; - val |= 1 << SendMrsCmd; - Set_NB32_DCT(dev, dct, 0x7c, val); - - do { - val = Get_NB32_DCT(dev, dct, 0x7c); - } while (val & (1 << SendMrsCmd)); - - printk(BIOS_DEBUG, "%s: Done\n", __func__); -} - -u32 mct_MR2(struct MCTStatStruc *pMCTstat, - struct DCTStatStruc *pDCTstat, u8 dct, u32 MrsChipSel) -{ - u32 dev = pDCTstat->dev_dct; - u32 dword, ret; - - /* The formula for chip select number is: CS = dimm*2+rank */ - uint8_t dimm = MrsChipSel / 2; - uint8_t rank = MrsChipSel % 2; - - if (is_fam15h()) { - uint8_t package_type = mctGet_NVbits(NV_PACK_TYPE); - - /* FIXME: These parameters should be configurable - * For now, err on the side of caution and enable automatic 2x refresh - * when the DDR temperature rises above the internal limits - */ - uint8_t force_2x_self_refresh = 0; /* ASR */ - uint8_t auto_2x_self_refresh = 1; /* SRT */ - - ret = 0x80000; - ret |= (MrsChipSel << 21); - - /* Set self refresh parameters */ - ret |= (force_2x_self_refresh << 6); - ret |= (auto_2x_self_refresh << 7); - - /* Obtain Tcwl, adjust, and set CWL with the adjusted value */ - dword = Get_NB32_DCT(dev, dct, 0x20c) & 0x1f; - dword -= pDCTstat->tcwl_delay[dct]; - ret |= ((dword - 5) << 3); - - /* Obtain and set RttWr */ - ret |= (fam15_rttwr(pDCTstat, dct, dimm, rank, package_type) << 9); - } else { - ret = 0x20000; - ret |= (MrsChipSel << 20); - - /* program MrsAddress[5:3]=CAS write latency (CWL): - * based on F2x[1,0]84[Tcwl] */ - dword = Get_NB32_DCT(dev, dct, 0x84); - dword = mct_AdjustSPDTimings(pMCTstat, pDCTstat, dword); - - ret |= ((dword >> 20) & 7) << 3; - - /* program MrsAddress[6]=auto self refresh method (ASR): - * based on F2x[1,0]84[ASR] - * program MrsAddress[7]=self refresh temperature range (SRT): - * based on F2x[1,0]84[ASR and SRT] - */ - ret |= ((dword >> 18) & 3) << 6; - - /* program MrsAddress[10:9]=dynamic termination during writes (RTT_WR) - * based on F2x[1,0]84[DramTermDyn] - */ - ret |= ((dword >> 10) & 3) << 9; - } - - printk(BIOS_SPEW, "Going to send DCT %d DIMM %d rank %d MR2 control word %08x\n", dct, dimm, rank, ret); - - return ret; -} - -static u32 mct_MR3(struct MCTStatStruc *pMCTstat, - struct DCTStatStruc *pDCTstat, u8 dct, u32 MrsChipSel) -{ - u32 dev = pDCTstat->dev_dct; - u32 dword, ret; - - /* The formula for chip select number is: CS = dimm*2+rank */ - uint8_t dimm = MrsChipSel / 2; - uint8_t rank = MrsChipSel % 2; - - if (is_fam15h()) { - ret = 0xc0000; - ret |= (MrsChipSel << 21); - - /* Program MPR and MPRLoc to 0 */ - // ret |= 0x0; /* MPR */ - // ret |= (0x0 << 2); /* MPRLoc */ - } else { - ret = 0x30000; - ret |= (MrsChipSel << 20); - - /* program MrsAddress[1:0]=multi purpose register address location - * (MPR Location):based on F2x[1,0]84[MprLoc] - * program MrsAddress[2]=multi purpose register - * (MPR):based on F2x[1,0]84[MprEn] - */ - dword = Get_NB32_DCT(dev, dct, 0x84); - ret |= (dword >> 24) & 7; - } - - printk(BIOS_SPEW, "Going to send DCT %d DIMM %d rank %d MR3 control word %08x\n", dct, dimm, rank, ret); - - return ret; -} - -u32 mct_MR1(struct MCTStatStruc *pMCTstat, - struct DCTStatStruc *pDCTstat, u8 dct, u32 MrsChipSel) -{ - u32 dev = pDCTstat->dev_dct; - u32 dword, ret; - - /* The formula for chip select number is: CS = dimm*2+rank */ - uint8_t dimm = MrsChipSel / 2; - uint8_t rank = MrsChipSel % 2; - - if (is_fam15h()) { - uint8_t package_type = mctGet_NVbits(NV_PACK_TYPE); - - /* Set defaults */ - uint8_t qoff = 0; /* Enable output buffers */ - uint8_t wrlvl = 0; /* Disable write levelling */ - uint8_t tqds = 0; - uint8_t rttnom = 0; - uint8_t dic = 0; - uint8_t additive_latency = 0; - uint8_t dll_enable = 0; - - ret = 0x40000; - ret |= (MrsChipSel << 21); - - /* Determine if TQDS should be set */ - if ((pDCTstat->Dimmx8Present & (1 << dimm)) - && (((dimm & 0x1)?(pDCTstat->Dimmx4Present&0x55):(pDCTstat->Dimmx4Present&0xaa)) != 0x0) - && (pDCTstat->Status & (1 << SB_LoadReduced))) - tqds = 1; - - /* Obtain RttNom */ - rttnom = fam15_rttnom(pDCTstat, dct, dimm, rank, package_type); - - /* Obtain DIC */ - dic = fam15_dimm_dic(pDCTstat, dct, dimm, rank, package_type); - - /* Load data into MRS word */ - ret |= (qoff & 0x1) << 12; - ret |= (tqds & 0x1) << 11; - ret |= ((rttnom & 0x4) >> 2) << 9; - ret |= ((rttnom & 0x2) >> 1) << 6; - ret |= ((rttnom & 0x1) >> 0) << 2; - ret |= (wrlvl & 0x1) << 7; - ret |= ((dic & 0x2) >> 1) << 5; - ret |= ((dic & 0x1) >> 0) << 1; - ret |= (additive_latency & 0x3) << 3; - ret |= (dll_enable & 0x1); - } else { - ret = 0x10000; - ret |= (MrsChipSel << 20); - - /* program MrsAddress[5,1]=output driver impedance control (DIC): - * based on F2x[1,0]84[DrvImpCtrl] - */ - dword = Get_NB32_DCT(dev, dct, 0x84); - if (dword & (1 << 3)) - ret |= 1 << 5; - if (dword & (1 << 2)) - ret |= 1 << 1; - - /* program MrsAddress[9,6,2]=nominal termination resistance of ODT (RTT): - * based on F2x[1,0]84[DramTerm] - */ - if (!(pDCTstat->Status & (1 << SB_Registered))) { - if (dword & (1 << 9)) - ret |= 1 << 9; - if (dword & (1 << 8)) - ret |= 1 << 6; - if (dword & (1 << 7)) - ret |= 1 << 2; - } else { - ret |= mct_MR1Odt_RDimm(pMCTstat, pDCTstat, dct, MrsChipSel); - } - - /* program MrsAddress[11]=TDQS: based on F2x[1,0]94[RDqsEn] */ - if (Get_NB32_DCT(dev, dct, 0x94) & (1 << RDqsEn)) { - u8 bit; - /* Set TDQS = 1b for x8 DIMM, TDQS = 0b for x4 DIMM, when mixed x8 & x4 */ - bit = (ret >> 21) << 1; - if ((dct & 1) != 0) - bit ++; - if (pDCTstat->Dimmx8Present & (1 << bit)) - ret |= 1 << 11; - } - - /* program MrsAddress[12]=QOFF: based on F2x[1,0]84[Qoff] */ - if (dword & (1 << 13)) - ret |= 1 << 12; - } - - printk(BIOS_SPEW, "Going to send DCT %d DIMM %d rank %d MR1 control word %08x\n", dct, dimm, rank, ret); - - return ret; -} - -static u32 mct_MR0(struct MCTStatStruc *pMCTstat, - struct DCTStatStruc *pDCTstat, u8 dct, u32 MrsChipSel) -{ - u32 dev = pDCTstat->dev_dct; - u32 dword, ret, dword2; - - /* The formula for chip select number is: CS = dimm*2+rank */ - uint8_t dimm = MrsChipSel / 2; - uint8_t rank = MrsChipSel % 2; - - if (is_fam15h()) { - ret = 0x00000; - ret |= (MrsChipSel << 21); - - /* Set defaults */ - uint8_t ppd = 0; - uint8_t wr_ap = 0; - uint8_t dll_reset = 1; - uint8_t test_mode = 0; - uint8_t cas_latency = 0; - uint8_t read_burst_type = 1; - uint8_t burst_length = 0; - - /* Obtain PchgPDModeSel */ - dword = Get_NB32_DCT(dev, dct, 0x84); - ppd = (dword >> 23) & 0x1; - - /* Obtain Twr */ - dword = Get_NB32_DCT(dev, dct, 0x22c) & 0x1f; - - /* Calculate wr_ap (Fam15h BKDG v3.14 Table 82) */ - if (dword == 0x10) - wr_ap = 0x0; - else if (dword == 0x5) - wr_ap = 0x1; - else if (dword == 0x6) - wr_ap = 0x2; - else if (dword == 0x7) - wr_ap = 0x3; - else if (dword == 0x8) - wr_ap = 0x4; - else if (dword == 0xa) - wr_ap = 0x5; - else if (dword == 0xc) - wr_ap = 0x6; - else if (dword == 0xe) - wr_ap = 0x7; - - /* Obtain Tcl */ - dword = Get_NB32_DCT(dev, dct, 0x200) & 0x1f; - - /* Calculate cas_latency (Fam15h BKDG v3.14 Table 83) */ - if (dword == 0x5) - cas_latency = 0x2; - else if (dword == 0x6) - cas_latency = 0x4; - else if (dword == 0x7) - cas_latency = 0x6; - else if (dword == 0x8) - cas_latency = 0x8; - else if (dword == 0x9) - cas_latency = 0xa; - else if (dword == 0xa) - cas_latency = 0xc; - else if (dword == 0xb) - cas_latency = 0xe; - else if (dword == 0xc) - cas_latency = 0x1; - else if (dword == 0xd) - cas_latency = 0x3; - else if (dword == 0xe) - cas_latency = 0x5; - else if (dword == 0xf) - cas_latency = 0x7; - else if (dword == 0x10) - cas_latency = 0x9; - - /* Obtain BurstCtrl */ - burst_length = Get_NB32_DCT(dev, dct, 0x84) & 0x3; - - /* Load data into MRS word */ - ret |= (ppd & 0x1) << 12; - ret |= (wr_ap & 0x7) << 9; - ret |= (dll_reset & 0x1) << 8; - ret |= (test_mode & 0x1) << 7; - ret |= ((cas_latency & 0xe) >> 1) << 4; - ret |= ((cas_latency & 0x1) >> 0) << 2; - ret |= (read_burst_type & 0x1) << 3; - ret |= (burst_length & 0x3); - } else { - ret = 0x00000; - ret |= (MrsChipSel << 20); - - /* program MrsAddress[1:0]=burst length and control method - (BL):based on F2x[1,0]84[BurstCtrl] */ - dword = Get_NB32_DCT(dev, dct, 0x84); - ret |= dword & 3; - - /* program MrsAddress[3]=1 (BT):interleaved */ - ret |= 1 << 3; - - /* program MrsAddress[6:4,2]=read CAS latency - (CL):based on F2x[1,0]88[Tcl] */ - dword2 = Get_NB32_DCT(dev, dct, 0x88); - ret |= (dword2 & 0x7) << 4; /* F2x88[2:0] to MrsAddress[6:4] */ - ret |= ((dword2 & 0x8) >> 3) << 2; /* F2x88[3] to MrsAddress[2] */ - - /* program MrsAddress[12]=0 (PPD):slow exit */ - if (dword & (1 << 23)) - ret |= 1 << 12; - - /* program MrsAddress[11:9]=write recovery for auto-precharge - (WR):based on F2x[1,0]84[Twr] */ - ret |= ((dword >> 4) & 7) << 9; - - /* program MrsAddress[8]=1 (DLL):DLL reset - just issue DLL reset at first time */ - ret |= 1 << 8; - } - - printk(BIOS_SPEW, "Going to send DCT %d DIMM %d rank %d MR0 control word %08x\n", dct, dimm, rank, ret); - - return ret; -} - -static void mct_SendZQCmd(struct DCTStatStruc *pDCTstat, u8 dct) -{ - u32 dev = pDCTstat->dev_dct; - u32 dword; - - printk(BIOS_DEBUG, "%s: Start\n", __func__); - - /*1.Program MrsAddress[10]=1 - 2.Set SendZQCmd = 1 - */ - dword = Get_NB32_DCT(dev, dct, 0x7C); - dword &= ~0xFFFFFF; - dword |= 1 << 10; - dword |= 1 << SendZQCmd; - Set_NB32_DCT(dev, dct, 0x7C, dword); - - /* Wait for SendZQCmd = 0 */ - do { - dword = Get_NB32_DCT(dev, dct, 0x7C); - } while (dword & (1 << SendZQCmd)); - - /* 4.Wait 512 MEMCLKs */ - mct_Wait(300); - - printk(BIOS_DEBUG, "%s: Done\n", __func__); -} - -void mct_DramInit_Sw_D(struct MCTStatStruc *pMCTstat, - struct DCTStatStruc *pDCTstat, u8 dct) -{ - u8 MrsChipSel; - u32 dword; - u32 dev = pDCTstat->dev_dct; - - printk(BIOS_DEBUG, "%s: Start\n", __func__); - - if (pDCTstat->DIMMAutoSpeed == mhz_to_memclk_config(mctGet_NVbits(NV_MIN_MEMCLK))) { - /* 3.Program F2x[1,0]7C[EnDramInit]=1 */ - dword = Get_NB32_DCT(dev, dct, 0x7c); - dword |= 1 << EnDramInit; - Set_NB32_DCT(dev, dct, 0x7c, dword); - mct_DCTAccessDone(pDCTstat, dct); - - /* 4.wait 200us */ - mct_Wait(40000); - - /* 5.Program F2x[1, 0]7C[DeassertMemRstX] = 1. */ - dword = Get_NB32_DCT(dev, dct, 0x7c); - dword |= 1 << DeassertMemRstX; - Set_NB32_DCT(dev, dct, 0x7c, dword); - - /* 6.wait 500us */ - mct_Wait(200000); - - /* 7.Program F2x[1,0]7C[AssertCke]=1 */ - dword = Get_NB32_DCT(dev, dct, 0x7c); - dword |= 1 << AssertCke; - Set_NB32_DCT(dev, dct, 0x7c, dword); - - /* 8.wait 360ns */ - mct_Wait(80); - - /* Set up address parity */ - if ((pDCTstat->Status & (1 << SB_Registered)) - || (pDCTstat->Status & (1 << SB_LoadReduced))) { - if (is_fam15h()) { - dword = Get_NB32_DCT(dev, dct, 0x90); - dword |= 1 << ParEn; - Set_NB32_DCT(dev, dct, 0x90, dword); - } - } - - /* The following steps are performed with registered DIMMs only and - * must be done for each chip select pair */ - if (pDCTstat->Status & (1 << SB_Registered)) - mct_DramControlReg_Init_D(pMCTstat, pDCTstat, dct); - - /* The following steps are performed with load reduced DIMMs only and - * must be done for each DIMM */ - // if (pDCTstat->Status & (1 << SB_LoadReduced)) - /* TODO - * Implement LRDIMM configuration - */ - } - - pDCTstat->CSPresent = pDCTstat->CSPresent_DCT[dct]; - if (pDCTstat->GangedMode & 1) - pDCTstat->CSPresent = pDCTstat->CSPresent_DCT[0]; - - /* The following steps are performed once for unbuffered DIMMs and once for each - * chip select on registered DIMMs: */ - for (MrsChipSel = 0; MrsChipSel < 8; MrsChipSel++) { - if (pDCTstat->CSPresent & (1 << MrsChipSel)) { - u32 EMRS; - /* 13.Send EMRS(2) */ - EMRS = mct_MR2(pMCTstat, pDCTstat, dct, MrsChipSel); - EMRS = swapAddrBits(pDCTstat, EMRS, MrsChipSel, dct); - mct_SendMrsCmd(pDCTstat, dct, EMRS); - /* 14.Send EMRS(3). Ordinarily at this time, MrsAddress[2:0]=000b */ - EMRS= mct_MR3(pMCTstat, pDCTstat, dct, MrsChipSel); - EMRS = swapAddrBits(pDCTstat, EMRS, MrsChipSel, dct); - mct_SendMrsCmd(pDCTstat, dct, EMRS); - /* 15.Send EMRS(1) */ - EMRS= mct_MR1(pMCTstat, pDCTstat, dct, MrsChipSel); - EMRS = swapAddrBits(pDCTstat, EMRS, MrsChipSel, dct); - mct_SendMrsCmd(pDCTstat, dct, EMRS); - /* 16.Send MRS with MrsAddress[8]=1(reset the DLL) */ - EMRS= mct_MR0(pMCTstat, pDCTstat, dct, MrsChipSel); - EMRS = swapAddrBits(pDCTstat, EMRS, MrsChipSel, dct); - mct_SendMrsCmd(pDCTstat, dct, EMRS); - - if (pDCTstat->DIMMAutoSpeed == mhz_to_memclk_config(mctGet_NVbits(NV_MIN_MEMCLK))) - if (!(pDCTstat->Status & (1 << SB_Registered))) - break; /* For UDIMM, only send MR commands once per channel */ - } - if (pDCTstat->LogicalCPUID & (AMD_DR_Bx/* | AMD_RB_C0 */)) /* TODO: We dont support RB_C0 now. need to be added and tested. */ - if (!(pDCTstat->Status & (1 << SB_Registered))) - MrsChipSel ++; - } - - if (pDCTstat->DIMMAutoSpeed == mhz_to_memclk_config(mctGet_NVbits(NV_MIN_MEMCLK))) { - /* 17.Send two ZQCL commands */ - mct_SendZQCmd(pDCTstat, dct); - mct_SendZQCmd(pDCTstat, dct); - - /* 18.Program F2x[1,0]7C[EnDramInit]=0 */ - dword = Get_NB32_DCT(dev, dct, 0x7C); - dword &= ~(1 << EnDramInit); - Set_NB32_DCT(dev, dct, 0x7C, dword); - mct_DCTAccessDone(pDCTstat, dct); - } - - printk(BIOS_DEBUG, "%s: Done\n", __func__); -} diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mctsrc.c b/src/northbridge/amd/amdmct/mct_ddr3/mctsrc.c deleted file mode 100644 index dbb989fe3d..0000000000 --- a/src/northbridge/amd/amdmct/mct_ddr3/mctsrc.c +++ /dev/null @@ -1,2438 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2010 Advanced Micro Devices, Inc. - * Copyright (C) 2015 - 2016 Raptor Engineering, LLC - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -/****************************************************************************** - Description: Receiver En and DQS Timing Training feature for DDR 3 MCT -******************************************************************************/ - -#include -#include -#include -#include -#include -#include -#include -#include "mct_d.h" -#include "mct_d_gcc.h" - -static void dqsTrainRcvrEn_SW_Fam10(struct MCTStatStruc *pMCTstat, - struct DCTStatStruc *pDCTstat, u8 Pass); -static void dqsTrainRcvrEn_SW_Fam15(struct MCTStatStruc *pMCTstat, - struct DCTStatStruc *pDCTstat, u8 Pass); -static void mct_InitDQSPos4RcvrEn_D(struct MCTStatStruc *pMCTstat, - struct DCTStatStruc *pDCTstat); -static void InitDQSPos4RcvrEn_D(struct MCTStatStruc *pMCTstat, - struct DCTStatStruc *pDCTstat, u8 Channel); -static void CalcEccDQSRcvrEn_D(struct MCTStatStruc *pMCTstat, - struct DCTStatStruc *pDCTstat, u8 Channel); -static void mct_SetMaxLatency_D(struct DCTStatStruc *pDCTstat, u8 Channel, u16 DQSRcvEnDly); -static void mct_DisableDQSRcvEn_D(struct DCTStatStruc *pDCTstat); - -static uint8_t is_fam15h(void) -{ - uint8_t fam15h = 0; - uint32_t family; - - family = cpuid_eax(0x80000001); - family = ((family & 0xf00000) >> 16) | ((family & 0xf00) >> 8); - - if (family >= 0x6f) - /* Family 15h or later */ - fam15h = 1; - - return fam15h; -} - -/* Warning: These must be located so they do not cross a logical 16-bit - segment boundary! */ -const u32 TestPattern0_D[] = { - 0x55555555, 0x55555555, 0x55555555, 0x55555555, - 0x55555555, 0x55555555, 0x55555555, 0x55555555, - 0x55555555, 0x55555555, 0x55555555, 0x55555555, - 0x55555555, 0x55555555, 0x55555555, 0x55555555, -}; -const u32 TestPattern1_D[] = { - 0xaaaaaaaa, 0xaaaaaaaa, 0xaaaaaaaa, 0xaaaaaaaa, - 0xaaaaaaaa, 0xaaaaaaaa, 0xaaaaaaaa, 0xaaaaaaaa, - 0xaaaaaaaa, 0xaaaaaaaa, 0xaaaaaaaa, 0xaaaaaaaa, - 0xaaaaaaaa, 0xaaaaaaaa, 0xaaaaaaaa, 0xaaaaaaaa, -}; -const u32 TestPattern2_D[] = { - 0x12345678, 0x87654321, 0x23456789, 0x98765432, - 0x59385824, 0x30496724, 0x24490795, 0x99938733, - 0x40385642, 0x38465245, 0x29432163, 0x05067894, - 0x12349045, 0x98723467, 0x12387634, 0x34587623, -}; - -static void SetupRcvrPattern(struct MCTStatStruc *pMCTstat, - struct DCTStatStruc *pDCTstat, u32 *buffer, u8 pass) -{ - /* - * 1. Copy the alpha and Beta patterns from ROM to Cache, - * aligning on 16 byte boundary - * 2. Set the ptr to DCTStatstruc.PtrPatternBufA for Alpha - * 3. Set the ptr to DCTStatstruc.PtrPatternBufB for Beta - */ - u32 *buf_a; - u32 *buf_b; - u32 *p_A; - u32 *p_B; - u8 i; - - buf_a = (u32 *)(((u32)buffer + 0x10) & (0xfffffff0)); - buf_b = buf_a + 32; /* ?? */ - p_A = (u32 *)SetupDqsPattern_1PassB(pass); - p_B = (u32 *)SetupDqsPattern_1PassA(pass); - - for (i = 0; i < 16; i++) { - buf_a[i] = p_A[i]; - buf_b[i] = p_B[i]; - } - - pDCTstat->PtrPatternBufA = (u32)buf_a; - pDCTstat->PtrPatternBufB = (u32)buf_b; -} - -void mct_TrainRcvrEn_D(struct MCTStatStruc *pMCTstat, - struct DCTStatStruc *pDCTstat, u8 Pass) -{ - if (mct_checkNumberOfDqsRcvEn_1Pass(Pass)) { - if (is_fam15h()) - dqsTrainRcvrEn_SW_Fam15(pMCTstat, pDCTstat, Pass); - else - dqsTrainRcvrEn_SW_Fam10(pMCTstat, pDCTstat, Pass); - } -} - -static uint16_t fam15_receiver_enable_training_seed(struct DCTStatStruc *pDCTstat, uint8_t dct, uint8_t dimm, uint8_t rank, uint8_t package_type) -{ - uint32_t dword; - uint16_t seed = 0; - - uint8_t MaxDimmsInstallable = mctGet_NVbits(NV_MAX_DIMMS_PER_CH); - - uint8_t channel = dct; - if (package_type == PT_GR) { - /* Get the internal node number */ - dword = Get_NB32(pDCTstat->dev_nbmisc, 0xe8); - dword = (dword >> 30) & 0x3; - if (dword == 1) { - channel += 2; - } - } - - if (pDCTstat->Status & (1 << SB_Registered)) { - if (package_type == PT_GR) { - /* Socket G34: Fam15h BKDG v3.14 Table 99 */ - if (MaxDimmsInstallable == 1) { - if (channel == 0) - seed = 0x43; - else if (channel == 1) - seed = 0x3f; - else if (channel == 2) - seed = 0x3a; - else if (channel == 3) - seed = 0x35; - } else if (MaxDimmsInstallable == 2) { - if (channel == 0) - seed = 0x54; - else if (channel == 1) - seed = 0x4d; - else if (channel == 2) - seed = 0x45; - else if (channel == 3) - seed = 0x40; - } else if (MaxDimmsInstallable == 3) { - if (channel == 0) - seed = 0x6b; - else if (channel == 1) - seed = 0x5e; - else if (channel == 2) - seed = 0x4b; - else if (channel == 3) - seed = 0x3d; - } - } else if (package_type == PT_C3) { - /* Socket C32: Fam15h BKDG v3.14 Table 100 */ - if ((MaxDimmsInstallable == 1) || (MaxDimmsInstallable == 2)) { - if (channel == 0) - seed = 0x3f; - else if (channel == 1) - seed = 0x3e; - } else if (MaxDimmsInstallable == 3) { - if (channel == 0) - seed = 0x47; - else if (channel == 1) - seed = 0x38; - } - } - } else if (pDCTstat->Status & (1 << SB_LoadReduced)) { - if (package_type == PT_GR) { - /* Socket G34: Fam15h BKDG v3.14 Table 99 */ - if (MaxDimmsInstallable == 1) { - if (channel == 0) - seed = 0x123; - else if (channel == 1) - seed = 0x122; - else if (channel == 2) - seed = 0x112; - else if (channel == 3) - seed = 0x102; - } - } else if (package_type == PT_C3) { - /* Socket C32: Fam15h BKDG v3.14 Table 100 */ - if (channel == 0) - seed = 0x132; - else if (channel == 1) - seed = 0x122; - } - } else { - if (package_type == PT_GR) { - /* Socket G34: Fam15h BKDG v3.14 Table 99 */ - if (MaxDimmsInstallable == 1) { - if (channel == 0) - seed = 0x3e; - else if (channel == 1) - seed = 0x38; - else if (channel == 2) - seed = 0x37; - else if (channel == 3) - seed = 0x31; - } else if (MaxDimmsInstallable == 2) { - if (channel == 0) - seed = 0x51; - else if (channel == 1) - seed = 0x4a; - else if (channel == 2) - seed = 0x46; - else if (channel == 3) - seed = 0x3f; - } else if (MaxDimmsInstallable == 3) { - if (channel == 0) - seed = 0x5e; - else if (channel == 1) - seed = 0x52; - else if (channel == 2) - seed = 0x48; - else if (channel == 3) - seed = 0x3c; - } - } else if (package_type == PT_C3) { - /* Socket C32: Fam15h BKDG v3.14 Table 100 */ - if ((MaxDimmsInstallable == 1) || (MaxDimmsInstallable == 2)) { - if (channel == 0) - seed = 0x39; - else if (channel == 1) - seed = 0x32; - } else if (MaxDimmsInstallable == 3) { - if (channel == 0) - seed = 0x45; - else if (channel == 1) - seed = 0x37; - } - } else if (package_type == PT_M2) { - /* Socket AM3: Fam15h BKDG v3.14 Table 101 */ - seed = 0x3a; - } else if (package_type == PT_FM2) { - /* Socket FM2: Fam15h Model10 BKDG 3.12 Table 43 */ - seed = 0x32; - } - } - - printk(BIOS_DEBUG, "%s: using seed: %04x\n", __func__, seed); - - return seed; -} - -void read_dqs_write_timing_control_registers(uint16_t *current_total_delay, uint32_t dev, uint8_t dct, uint8_t dimm, uint32_t index_reg) -{ - uint8_t lane; - uint32_t dword; - - for (lane = 0; lane < MAX_BYTE_LANES; lane++) { - uint32_t wdt_reg; - if ((lane == 0) || (lane == 1)) - wdt_reg = 0x30; - if ((lane == 2) || (lane == 3)) - wdt_reg = 0x31; - if ((lane == 4) || (lane == 5)) - wdt_reg = 0x40; - if ((lane == 6) || (lane == 7)) - wdt_reg = 0x41; - if (lane == 8) - wdt_reg = 0x32; - wdt_reg += dimm * 3; - dword = Get_NB32_index_wait_DCT(dev, dct, index_reg, wdt_reg); - if ((lane == 7) || (lane == 5) || (lane == 3) || (lane == 1)) - current_total_delay[lane] = (dword & 0x00ff0000) >> 16; - if ((lane == 8) || (lane == 6) || (lane == 4) || (lane == 2) || (lane == 0)) - current_total_delay[lane] = dword & 0x000000ff; - } -} - -#ifdef UNUSED_CODE -static void write_dqs_write_timing_control_registers(uint16_t *current_total_delay, uint32_t dev, uint8_t dct, uint8_t dimm, uint32_t index_reg) -{ - uint8_t lane; - uint32_t dword; - - for (lane = 0; lane < MAX_BYTE_LANES; lane++) { - uint32_t ret_reg; - if ((lane == 0) || (lane == 1)) - ret_reg = 0x30; - if ((lane == 2) || (lane == 3)) - ret_reg = 0x31; - if ((lane == 4) || (lane == 5)) - ret_reg = 0x40; - if ((lane == 6) || (lane == 7)) - ret_reg = 0x41; - if (lane == 8) - ret_reg = 0x32; - ret_reg += dimm * 3; - dword = Get_NB32_index_wait_DCT(dev, dct, index_reg, ret_reg); - if ((lane == 7) || (lane == 5) || (lane == 3) || (lane == 1)) { - dword &= ~(0xff << 16); - dword |= (current_total_delay[lane] & 0xff) << 16; - } - if ((lane == 8) || (lane == 6) || (lane == 4) || (lane == 2) || (lane == 0)) { - dword &= ~0xff; - dword |= current_total_delay[lane] & 0xff; - } - Set_NB32_index_wait_DCT(dev, dct, index_reg, ret_reg, dword); - } -} -#endif - -static void write_write_data_timing_control_registers(uint16_t *current_total_delay, uint32_t dev, uint8_t dct, uint8_t dimm, uint32_t index_reg) -{ - uint8_t lane; - uint32_t dword; - - for (lane = 0; lane < MAX_BYTE_LANES; lane++) { - uint32_t wdt_reg; - - /* Calculate Write Data Timing register location */ - if ((lane == 0) || (lane == 1) || (lane == 2) || (lane == 3)) - wdt_reg = 0x1; - if ((lane == 4) || (lane == 5) || (lane == 6) || (lane == 7)) - wdt_reg = 0x2; - if (lane == 8) - wdt_reg = 0x3; - wdt_reg |= (dimm << 8); - - /* Set Write Data Timing register values */ - dword = Get_NB32_index_wait_DCT(dev, dct, index_reg, wdt_reg); - if ((lane == 7) || (lane == 3)) { - dword &= ~(0x7f << 24); - dword |= (current_total_delay[lane] & 0x7f) << 24; - } - if ((lane == 6) || (lane == 2)) { - dword &= ~(0x7f << 16); - dword |= (current_total_delay[lane] & 0x7f) << 16; - } - if ((lane == 5) || (lane == 1)) { - dword &= ~(0x7f << 8); - dword |= (current_total_delay[lane] & 0x7f) << 8; - } - if ((lane == 8) || (lane == 4) || (lane == 0)) { - dword &= ~0x7f; - dword |= current_total_delay[lane] & 0x7f; - } - Set_NB32_index_wait_DCT(dev, dct, index_reg, wdt_reg, dword); - } -} - -void read_dqs_receiver_enable_control_registers(uint16_t *current_total_delay, uint32_t dev, uint8_t dct, uint8_t dimm, uint32_t index_reg) -{ - uint8_t lane; - uint32_t mask; - uint32_t dword; - - if (is_fam15h()) - mask = 0x3ff; - else - mask = 0x1ff; - - for (lane = 0; lane < MAX_BYTE_LANES; lane++) { - uint32_t ret_reg; - if ((lane == 0) || (lane == 1)) - ret_reg = 0x10; - if ((lane == 2) || (lane == 3)) - ret_reg = 0x11; - if ((lane == 4) || (lane == 5)) - ret_reg = 0x20; - if ((lane == 6) || (lane == 7)) - ret_reg = 0x21; - if (lane == 8) - ret_reg = 0x12; - ret_reg += dimm * 3; - dword = Get_NB32_index_wait_DCT(dev, dct, index_reg, ret_reg); - if ((lane == 7) || (lane == 5) || (lane == 3) || (lane == 1)) { - current_total_delay[lane] = (dword & (mask << 16)) >> 16; - } - if ((lane == 8) || (lane == 6) || (lane == 4) || (lane == 2) || (lane == 0)) { - current_total_delay[lane] = dword & mask; - } - } -} - -void write_dqs_receiver_enable_control_registers(uint16_t *current_total_delay, uint32_t dev, uint8_t dct, uint8_t dimm, uint32_t index_reg) -{ - uint8_t lane; - uint32_t mask; - uint32_t dword; - - if (is_fam15h()) - mask = 0x3ff; - else - mask = 0x1ff; - - for (lane = 0; lane < MAX_BYTE_LANES; lane++) { - uint32_t ret_reg; - if ((lane == 0) || (lane == 1)) - ret_reg = 0x10; - if ((lane == 2) || (lane == 3)) - ret_reg = 0x11; - if ((lane == 4) || (lane == 5)) - ret_reg = 0x20; - if ((lane == 6) || (lane == 7)) - ret_reg = 0x21; - if (lane == 8) - ret_reg = 0x12; - ret_reg += dimm * 3; - dword = Get_NB32_index_wait_DCT(dev, dct, index_reg, ret_reg); - if ((lane == 7) || (lane == 5) || (lane == 3) || (lane == 1)) { - dword &= ~(mask << 16); - dword |= (current_total_delay[lane] & mask) << 16; - } - if ((lane == 8) || (lane == 6) || (lane == 4) || (lane == 2) || (lane == 0)) { - dword &= ~mask; - dword |= current_total_delay[lane] & mask; - } - Set_NB32_index_wait_DCT(dev, dct, index_reg, ret_reg, dword); - } -} - -static void read_dram_phase_recovery_control_registers(uint16_t *current_total_delay, uint32_t dev, uint8_t dct, uint8_t dimm, uint32_t index_reg) -{ - uint8_t lane; - uint32_t dword; - - for (lane = 0; lane < MAX_BYTE_LANES; lane++) { - uint32_t prc_reg; - - /* Calculate DRAM Phase Recovery Control register location */ - if ((lane == 0) || (lane == 1) || (lane == 2) || (lane == 3)) - prc_reg = 0x50; - if ((lane == 4) || (lane == 5) || (lane == 6) || (lane == 7)) - prc_reg = 0x51; - if (lane == 8) - prc_reg = 0x52; - - dword = Get_NB32_index_wait_DCT(dev, dct, index_reg, prc_reg); - if ((lane == 7) || (lane == 3)) { - current_total_delay[lane] = (dword >> 24) & 0x7f; - } - if ((lane == 6) || (lane == 2)) { - current_total_delay[lane] = (dword >> 16) & 0x7f; - } - if ((lane == 5) || (lane == 1)) { - current_total_delay[lane] = (dword >> 8) & 0x7f; - } - if ((lane == 8) || (lane == 4) || (lane == 0)) { - current_total_delay[lane] = dword & 0x7f; - } - } -} - -static void write_dram_phase_recovery_control_registers(uint16_t *current_total_delay, uint32_t dev, uint8_t dct, uint8_t dimm, uint32_t index_reg) -{ - uint8_t lane; - uint32_t dword; - - for (lane = 0; lane < MAX_BYTE_LANES; lane++) { - uint32_t prc_reg; - - /* Calculate DRAM Phase Recovery Control register location */ - if ((lane == 0) || (lane == 1) || (lane == 2) || (lane == 3)) - prc_reg = 0x50; - if ((lane == 4) || (lane == 5) || (lane == 6) || (lane == 7)) - prc_reg = 0x51; - if (lane == 8) - prc_reg = 0x52; - - /* Set DRAM Phase Recovery Control register values */ - dword = Get_NB32_index_wait_DCT(dev, dct, index_reg, prc_reg); - if ((lane == 7) || (lane == 3)) { - dword &= ~(0x7f << 24); - dword |= (current_total_delay[lane] & 0x7f) << 24; - } - if ((lane == 6) || (lane == 2)) { - dword &= ~(0x7f << 16); - dword |= (current_total_delay[lane] & 0x7f) << 16; - } - if ((lane == 5) || (lane == 1)) { - dword &= ~(0x7f << 8); - dword |= (current_total_delay[lane] & 0x7f) << 8; - } - if ((lane == 8) || (lane == 4) || (lane == 0)) { - dword &= ~0x7f; - dword |= current_total_delay[lane] & 0x7f; - } - Set_NB32_index_wait_DCT(dev, dct, index_reg, prc_reg, dword); - } -} - -void read_dqs_read_data_timing_registers(uint16_t *delay, uint32_t dev, uint8_t dct, uint8_t dimm, uint32_t index_reg) -{ - uint8_t shift; - uint32_t dword; - uint32_t mask; - - if (is_fam15h()) { - mask = 0x3e; - shift = 1; - } - else { - mask = 0x3f; - shift = 0; - } - - /* Lanes 0 - 3 */ - dword = Get_NB32_index_wait_DCT(dev, dct, index_reg, 0x5 | (dimm << 8)); - delay[3] = ((dword >> 24) & mask) >> shift; - delay[2] = ((dword >> 16) & mask) >> shift; - delay[1] = ((dword >> 8) & mask) >> shift; - delay[0] = (dword & mask) >> shift; - - /* Lanes 4 - 7 */ - dword = Get_NB32_index_wait_DCT(dev, dct, index_reg, 0x6 | (dimm << 8)); - delay[7] = ((dword >> 24) & mask) >> shift; - delay[6] = ((dword >> 16) & mask) >> shift; - delay[5] = ((dword >> 8) & mask) >> shift; - delay[4] = (dword & mask) >> shift; - - /* Lane 8 (ECC) */ - dword = Get_NB32_index_wait_DCT(dev, dct, index_reg, 0x7 | (dimm << 8)); - delay[8] = (dword & mask) >> shift; -} - -void write_dqs_read_data_timing_registers(uint16_t *delay, uint32_t dev, uint8_t dct, uint8_t dimm, uint32_t index_reg) -{ - uint8_t shift; - uint32_t dword; - uint32_t mask; - - if (is_fam15h()) { - mask = 0x3e; - shift = 1; - } - else { - mask = 0x3f; - shift = 0; - } - - /* Lanes 0 - 3 */ - dword = Get_NB32_index_wait_DCT(dev, dct, index_reg, 0x5 | (dimm << 8)); - dword &= ~(mask << 24); - dword &= ~(mask << 16); - dword &= ~(mask << 8); - dword &= ~mask; - dword |= ((delay[3] << shift) & mask) << 24; - dword |= ((delay[2] << shift) & mask) << 16; - dword |= ((delay[1] << shift) & mask) << 8; - dword |= (delay[0] << shift) & mask; - Set_NB32_index_wait_DCT(dev, dct, index_reg, 0x5 | (dimm << 8), dword); - - /* Lanes 4 - 7 */ - dword = Get_NB32_index_wait_DCT(dev, dct, index_reg, 0x6 | (dimm << 8)); - dword &= ~(mask << 24); - dword &= ~(mask << 16); - dword &= ~(mask << 8); - dword &= ~mask; - dword |= ((delay[7] << shift) & mask) << 24; - dword |= ((delay[6] << shift) & mask) << 16; - dword |= ((delay[5] << shift) & mask) << 8; - dword |= (delay[4] << shift) & mask; - Set_NB32_index_wait_DCT(dev, dct, index_reg, 0x6 | (dimm << 8), dword); - - /* Lane 8 (ECC) */ - dword = Get_NB32_index_wait_DCT(dev, dct, index_reg, 0x7 | (dimm << 8)); - dword &= ~mask; - dword |= (delay[8] << shift) & mask; - Set_NB32_index_wait_DCT(dev, dct, index_reg, 0x7 | (dimm << 8), dword); -} - -static uint32_t convert_testaddr_and_channel_to_address(struct DCTStatStruc *pDCTstat, uint32_t testaddr, uint8_t channel) -{ - SetUpperFSbase(testaddr); - testaddr <<= 8; - - if ((pDCTstat->Status & (1<Node_ID, 0); - print_debug_dqs("TrainRcvEn: Pass", Pass, 0); - - dev = pDCTstat->dev_dct; - ch_start = 0; - if (!pDCTstat->GangedMode) { - ch_end = 2; - } else { - ch_end = 1; - } - - for (ch = ch_start; ch < ch_end; ch++) { - reg = 0x78; - val = Get_NB32_DCT(dev, ch, reg); - val &= ~(0x3ff << 22); - val |= (0x0c8 << 22); /* MaxRdLatency = 0xc8 */ - Set_NB32_DCT(dev, ch, reg, val); - } - - if (Pass == FirstPass) { - mct_InitDQSPos4RcvrEn_D(pMCTstat, pDCTstat); - } else { - pDCTstat->DimmTrainFail = 0; - pDCTstat->CSTrainFail = ~pDCTstat->CSPresent; - } - - cr4 = read_cr4(); - if (cr4 & (1 << 9)) { /* save the old value */ - _SSE2 = 1; - } - cr4 |= (1 << 9); /* OSFXSR enable SSE2 */ - write_cr4(cr4); - - msr = rdmsr(HWCR_MSR); - /* FIXME: Why use SSEDIS */ - if (msr.lo & (1 << 17)) { /* save the old value */ - _Wrap32Dis = 1; - } - msr.lo |= (1 << 17); /* HWCR.wrap32dis */ - msr.lo &= ~(1 << 15); /* SSEDIS */ - wrmsr(HWCR_MSR, msr); /* Setting wrap32dis allows 64-bit memory - references in real mode */ - - _DisableDramECC = mct_DisableDimmEccEn_D(pMCTstat, pDCTstat); - - SetupRcvrPattern(pMCTstat, pDCTstat, PatternBuffer, Pass); - - Errors = 0; - dev = pDCTstat->dev_dct; - - for (Channel = 0; Channel < 2; Channel++) { - print_debug_dqs("\tTrainRcvEn51: Node ", pDCTstat->Node_ID, 1); - print_debug_dqs("\tTrainRcvEn51: Channel ", Channel, 1); - pDCTstat->Channel = Channel; - - CTLRMaxDelay = 0; - MaxDelay_CH[Channel] = 0; - index_reg = 0x98; - - Receiver = mct_InitReceiver_D(pDCTstat, Channel); - /* There are four receiver pairs, loosely associated with chipselects. - * This is essentially looping over each DIMM. - */ - for (; Receiver < 8; Receiver += 2) { - Addl_Index = (Receiver >> 1) * 3 + 0x10; - dimm = (Receiver >> 1); - - print_debug_dqs("\t\tTrainRcvEnd52: index ", Addl_Index, 2); - - if (!mct_RcvrRankEnabled_D(pMCTstat, pDCTstat, Channel, Receiver)) { - continue; - } - - /* Clear data structures */ - for (lane = 0; lane < 8; lane++) { - data_test_pass_prev[lane] = 0; - trained[lane] = 0; - } - - /* 2.8.9.9.2 (1, 6) - * Retrieve gross and fine timing fields from write DQS registers - */ - read_dqs_write_timing_control_registers(current_total_delay, dev, Channel, dimm, index_reg); - - /* 2.8.9.9.2 (1) - * Program the Write Data Timing and Write ECC Timing register to - * the values stored in the DQS Write Timing Control register - * for each lane - */ - write_write_data_timing_control_registers(current_total_delay, dev, Channel, dimm, index_reg); - - /* 2.8.9.9.2 (2) - * Program the Read DQS Timing Control and the Read DQS ECC Timing Control registers - * to 1/2 MEMCLK for all lanes - */ - for (lane = 0; lane < MAX_BYTE_LANES; lane++) { - uint32_t rdt_reg; - if ((lane == 0) || (lane == 1) || (lane == 2) || (lane == 3)) - rdt_reg = 0x5; - if ((lane == 4) || (lane == 5) || (lane == 6) || (lane == 7)) - rdt_reg = 0x6; - if (lane == 8) - rdt_reg = 0x7; - rdt_reg |= (dimm << 8); - if (lane == 8) - dword = 0x0000003f; - else - dword = 0x3f3f3f3f; - Set_NB32_index_wait_DCT(dev, Channel, index_reg, rdt_reg, dword); - } - - /* 2.8.9.9.2 (3) - * Select two test addresses for each rank present - */ - TestAddr0 = mct_GetRcvrSysAddr_D(pMCTstat, pDCTstat, Channel, Receiver, &valid); - if (!valid) { /* Address not supported on current CS */ - continue; - } - - TestAddr0B = TestAddr0 + (BigPagex8_RJ8 << 3); - - if (mct_RcvrRankEnabled_D(pMCTstat, pDCTstat, Channel, Receiver+1)) { - TestAddr1 = mct_GetRcvrSysAddr_D(pMCTstat, pDCTstat, Channel, Receiver+1, &valid); - if (!valid) { /* Address not supported on current CS */ - continue; - } - TestAddr1B = TestAddr1 + (BigPagex8_RJ8 << 3); - _2Ranks = 1; - } else { - _2Ranks = TestAddr1 = TestAddr1B = 0; - } - - print_debug_dqs("\t\tTrainRcvEn53: TestAddr0 ", TestAddr0, 2); - print_debug_dqs("\t\tTrainRcvEn53: TestAddr0B ", TestAddr0B, 2); - print_debug_dqs("\t\tTrainRcvEn53: TestAddr1 ", TestAddr1, 2); - print_debug_dqs("\t\tTrainRcvEn53: TestAddr1B ", TestAddr1B, 2); - - /* 2.8.9.9.2 (4, 5) - * Write 1 cache line of the appropriate test pattern to each test address - */ - mct_Write1LTestPattern_D(pMCTstat, pDCTstat, TestAddr0, 0); /* rank 0 of DIMM, testpattern 0 */ - mct_Write1LTestPattern_D(pMCTstat, pDCTstat, TestAddr0B, 1); /* rank 0 of DIMM, testpattern 1 */ - if (_2Ranks) { - mct_Write1LTestPattern_D(pMCTstat, pDCTstat, TestAddr1, 0); /*rank 1 of DIMM, testpattern 0 */ - mct_Write1LTestPattern_D(pMCTstat, pDCTstat, TestAddr1B, 1); /*rank 1 of DIMM, testpattern 1 */ - } - -#if DQS_TRAIN_DEBUG > 0 - for (lane = 0; lane < 8; lane++) { - print_debug_dqs("\t\tTrainRcvEn54: lane: ", lane, 2); - print_debug_dqs("\t\tTrainRcvEn54: current_total_delay ", current_total_delay[lane], 2); - } -#endif - - /* 2.8.9.9.2 (6) - * Write gross and fine timing fields to read DQS registers - */ - write_dqs_receiver_enable_control_registers(current_total_delay, dev, Channel, dimm, index_reg); - - /* 2.8.9.9.2 (7) - * Loop over all delay values up to 1 MEMCLK (0x40 delay steps) from the initial delay values - * - * FIXME - * It is not clear if training should be discontinued if any test failures occur in the first - * 1 MEMCLK window, or if it should be discontinued if no successes occur in the first 1 MEMCLK - * window. Therefore, loop over up to 2 MEMCLK (0x80 delay steps) to be on the safe side. - */ - uint16_t current_delay_step; - - for (current_delay_step = 0; current_delay_step < 0x80; current_delay_step++) { - print_debug_dqs("\t\t\tTrainRcvEn541: current_delay_step ", current_delay_step, 3); - - /* 2.8.9.9.2 (7 D) - * Terminate if all lanes are trained - */ - uint8_t all_lanes_trained = 1; - for (lane = 0; lane < 8; lane++) - if (!trained[lane]) - all_lanes_trained = 0; - - if (all_lanes_trained) - break; - - /* 2.8.9.9.2 (7 A) - * Loop over all ranks - */ - for (rank = 0; rank < (_2Ranks + 1); rank++) { - /* 2.8.9.9.2 (7 A a-d) - * Read the first test address of the current rank - * Store the first data beat for analysis - * Reset read pointer in the DRAM controller FIFO - * Read the second test address of the current rank - * Store the first data beat for analysis - * Reset read pointer in the DRAM controller FIFO - */ - if (rank & 1) { - /* 2.8.9.9.2 (7 D) - * Invert read instructions to alternate data read order on the bus - */ - proc_IOCLFLUSH_D((rank == 0)?TestAddr0B:TestAddr1B); - result_qword2 = read64_fs(convert_testaddr_and_channel_to_address(pDCTstat, (rank == 0)?TestAddr0B:TestAddr1B, Channel)); - write_dqs_receiver_enable_control_registers(current_total_delay, dev, Channel, dimm, index_reg); - proc_IOCLFLUSH_D((rank == 0)?TestAddr0:TestAddr1); - result_qword1 = read64_fs(convert_testaddr_and_channel_to_address(pDCTstat, (rank == 0)?TestAddr0:TestAddr1, Channel)); - write_dqs_receiver_enable_control_registers(current_total_delay, dev, Channel, dimm, index_reg); - } else { - proc_IOCLFLUSH_D((rank == 0)?TestAddr0:TestAddr1); - result_qword1 = read64_fs(convert_testaddr_and_channel_to_address(pDCTstat, (rank == 0)?TestAddr0:TestAddr1, Channel)); - write_dqs_receiver_enable_control_registers(current_total_delay, dev, Channel, dimm, index_reg); - proc_IOCLFLUSH_D((rank == 0)?TestAddr0B:TestAddr1B); - result_qword2 = read64_fs(convert_testaddr_and_channel_to_address(pDCTstat, (rank == 0)?TestAddr0B:TestAddr1B, Channel)); - write_dqs_receiver_enable_control_registers(current_total_delay, dev, Channel, dimm, index_reg); - } - /* 2.8.9.9.2 (7 A e) - * Compare both read patterns and flag passing ranks/lanes - */ - uint8_t result_lane_byte1; - uint8_t result_lane_byte2; - for (lane = 0; lane < 8; lane++) { - if (trained[lane] == 1) { -#if DQS_TRAIN_DEBUG > 0 - print_debug_dqs("\t\t\t\t\t\t\t\t lane already trained: ", lane, 4); -#endif - continue; - } - - result_lane_byte1 = (result_qword1 >> (lane * 8)) & 0xff; - result_lane_byte2 = (result_qword2 >> (lane * 8)) & 0xff; - if ((result_lane_byte1 == 0x55) && (result_lane_byte2 == 0xaa)) - data_test_pass_sr[rank][lane] = 1; - else - data_test_pass_sr[rank][lane] = 0; -#if DQS_TRAIN_DEBUG > 0 - print_debug_dqs_pair("\t\t\t\t\t\t\t\t ", 0x55, " | ", result_lane_byte1, 4); - print_debug_dqs_pair("\t\t\t\t\t\t\t\t ", 0xaa, " | ", result_lane_byte2, 4); -#endif - } - } - - /* 2.8.9.9.2 (7 B) - * If DIMM is dual rank, only use delays that pass testing for both ranks - */ - for (lane = 0; lane < 8; lane++) { - if (_2Ranks) { - if ((data_test_pass_sr[0][lane]) && (data_test_pass_sr[1][lane])) - data_test_pass[lane] = 1; - else - data_test_pass[lane] = 0; - } else { - data_test_pass[lane] = data_test_pass_sr[0][lane]; - } - } - - /* 2.8.9.9.2 (7 E) - * For each lane, update the DQS receiver delay setting in support of next iteration - */ - for (lane = 0; lane < 8; lane++) { - if (trained[lane] == 1) - continue; - - /* 2.8.9.9.2 (7 C a) - * Save the total delay of the first success after a failure for later use - */ - if ((data_test_pass[lane] == 1) && (data_test_pass_prev[lane] == 0)) { - candidate_total_delay[lane] = current_total_delay[lane]; - window_det_toggle[lane] = 0; - } - - /* 2.8.9.9.2 (7 C b) - * If the current delay failed testing add 1/8 UI to the current delay - */ - if (data_test_pass[lane] == 0) - current_total_delay[lane] += 0x4; - - /* 2.8.9.9.2 (7 C c) - * If the current delay passed testing alternately add either 1/32 UI or 1/4 UI to the current delay - * If 1.25 UI of delay have been added with no failures the lane is considered trained - */ - if (data_test_pass[lane] == 1) { - /* See if lane is trained */ - if ((current_total_delay[lane] - candidate_total_delay[lane]) >= 0x28) { - trained[lane] = 1; - - /* Calculate and set final lane delay value - * The final delay is the candidate delay + 7/8 UI - */ - current_total_delay[lane] = candidate_total_delay[lane] + 0x1c; - } else { - if (window_det_toggle[lane] == 0) { - current_total_delay[lane] += 0x1; - window_det_toggle[lane] = 1; - } else { - current_total_delay[lane] += 0x8; - window_det_toggle[lane] = 0; - } - } - } - } - - /* Update delays in hardware */ - write_dqs_receiver_enable_control_registers(current_total_delay, dev, Channel, dimm, index_reg); - - /* Save previous results for comparison in the next iteration */ - for (lane = 0; lane < 8; lane++) - data_test_pass_prev[lane] = data_test_pass[lane]; - } - -#if DQS_TRAIN_DEBUG > 0 - for (lane = 0; lane < 8; lane++) - print_debug_dqs_pair("\t\tTrainRcvEn55: Lane ", lane, " current_total_delay ", current_total_delay[lane], 2); -#endif - - /* Find highest delay value and save for later use */ - for (lane = 0; lane < 8; lane++) - if (current_total_delay[lane] > CTLRMaxDelay) - CTLRMaxDelay = current_total_delay[lane]; - - /* See if any lanes failed training, and set error flags appropriately - * For all trained lanes, save delay values for later use - */ - for (lane = 0; lane < 8; lane++) { - if (trained[lane]) { - pDCTstat->CH_D_B_RCVRDLY[Channel][Receiver >> 1][lane] = current_total_delay[lane]; - } else { - printk(BIOS_WARNING, "TrainRcvrEn: WARNING: Lane %d of receiver %d on channel %d failed training!\n", lane, Receiver, Channel); - - /* Set error flags */ - pDCTstat->ErrStatus |= 1 << SB_NORCVREN; - Errors |= 1 << SB_NORCVREN; - pDCTstat->ErrCode = SC_FatalErr; - pDCTstat->CSTrainFail |= 1 << Receiver; - pDCTstat->DimmTrainFail |= 1 << (Receiver + Channel); - } - } - - /* 2.8.9.9.2 (8) - * Flush the receiver FIFO - * Write one full cache line of non-0x55/0xaa data to one of the test addresses, then read it back to flush the FIFO - */ - /* FIXME - * This does not seem to be needed, and has a tendency to lock up the - * boot process while attempting to write the test pattern. - */ - } - MaxDelay_CH[Channel] = CTLRMaxDelay; - } - - CTLRMaxDelay = MaxDelay_CH[0]; - if (MaxDelay_CH[1] > CTLRMaxDelay) - CTLRMaxDelay = MaxDelay_CH[1]; - - for (Channel = 0; Channel < 2; Channel++) { - mct_SetMaxLatency_D(pDCTstat, Channel, CTLRMaxDelay); /* program Ch A/B MaxAsyncLat to correspond with max delay */ - } - - for (Channel = 0; Channel < 2; Channel++) { - ResetDCTWrPtr_D(dev, Channel, index_reg, Addl_Index); - } - - if (_DisableDramECC) { - mct_EnableDimmEccEn_D(pMCTstat, pDCTstat, _DisableDramECC); - } - - if (Pass == FirstPass) { - /*Disable DQSRcvrEn training mode */ - mct_DisableDQSRcvEn_D(pDCTstat); - } - - if (!_Wrap32Dis) { - msr = rdmsr(HWCR_MSR); - msr.lo &= ~(1<<17); /* restore HWCR.wrap32dis */ - wrmsr(HWCR_MSR, msr); - } - if (!_SSE2) { - cr4 = read_cr4(); - cr4 &= ~(1<<9); /* restore cr4.OSFXSR */ - write_cr4(cr4); - } - -#if DQS_TRAIN_DEBUG > 0 - { - u8 ChannelDTD; - printk(BIOS_DEBUG, "TrainRcvrEn: CH_MaxRdLat:\n"); - for (ChannelDTD = 0; ChannelDTD < 2; ChannelDTD++) { - printk(BIOS_DEBUG, "Channel:%x: %x\n", - ChannelDTD, pDCTstat->CH_MaxRdLat[ChannelDTD][0]); - } - } -#endif - -#if DQS_TRAIN_DEBUG > 0 - { - u16 valDTD; - u8 ChannelDTD, ReceiverDTD; - u8 i; - u16 *p; - - printk(BIOS_DEBUG, "TrainRcvrEn: CH_D_B_RCVRDLY:\n"); - for (ChannelDTD = 0; ChannelDTD < 2; ChannelDTD++) { - printk(BIOS_DEBUG, "Channel:%x\n", ChannelDTD); - for (ReceiverDTD = 0; ReceiverDTD < 8; ReceiverDTD+=2) { - printk(BIOS_DEBUG, "\t\tReceiver:%x:", ReceiverDTD); - p = pDCTstat->CH_D_B_RCVRDLY[ChannelDTD][ReceiverDTD>>1]; - for (i = 0; i < 8; i++) { - valDTD = p[i]; - printk(BIOS_DEBUG, " %03x", valDTD); - } - printk(BIOS_DEBUG, "\n"); - } - } - } -#endif - - printk(BIOS_DEBUG, "TrainRcvrEn: Status %x\n", pDCTstat->Status); - printk(BIOS_DEBUG, "TrainRcvrEn: ErrStatus %x\n", pDCTstat->ErrStatus); - printk(BIOS_DEBUG, "TrainRcvrEn: ErrCode %x\n", pDCTstat->ErrCode); - printk(BIOS_DEBUG, "TrainRcvrEn: Done\n\n"); -} - -/* DQS Receiver Enable Training Pattern Generation (Family 15h) - * Algorithm detailed in: - * The Fam15h BKDG Rev. 3.14 section 2.10.5.8.2 (4) - */ -static void generate_dram_receiver_enable_training_pattern_fam15(struct MCTStatStruc *pMCTstat, - struct DCTStatStruc *pDCTstat, uint8_t dct, uint8_t Receiver) -{ - uint32_t dword; - uint32_t dev = pDCTstat->dev_dct; - - /* 2.10.5.7.1.1 - * It appears that the DCT only supports 8-beat burst length mode, - * so do nothing here... - */ - - /* Wait for CmdSendInProg == 0 */ - do { - dword = Get_NB32_DCT(dev, dct, 0x250); - } while (dword & (0x1 << 12)); - - /* Set CmdTestEnable = 1 */ - dword = Get_NB32_DCT(dev, dct, 0x250); - dword |= (0x1 << 2); - Set_NB32_DCT(dev, dct, 0x250, dword); - - /* 2.10.5.8.6.1.1 Send Activate Command */ - dword = Get_NB32_DCT(dev, dct, 0x28c); - dword &= ~(0xff << 22); /* CmdChipSelect = Receiver */ - dword |= ((0x1 << Receiver) << 22); - dword &= ~(0x7 << 19); /* CmdBank = 0 */ - dword &= ~(0x3ffff); /* CmdAddress = 0 */ - dword |= (0x1 << 31); /* SendActCmd = 1 */ - Set_NB32_DCT(dev, dct, 0x28c, dword); - - /* Wait for SendActCmd == 0 */ - do { - dword = Get_NB32_DCT(dev, dct, 0x28c); - } while (dword & (0x1 << 31)); - - /* Wait 75 MEMCLKs. */ - precise_memclk_delay_fam15(pMCTstat, pDCTstat, dct, 75); - - /* 2.10.5.8.6.1.2 */ - Set_NB32_DCT(dev, dct, 0x274, 0x0); /* DQMask = 0 */ - Set_NB32_DCT(dev, dct, 0x278, 0x0); - - dword = Get_NB32_DCT(dev, dct, 0x27c); - dword &= ~(0xff); /* EccMask = 0 */ - if (pDCTstat->DimmECCPresent == 0) - dword |= 0xff; /* EccMask = 0xff */ - Set_NB32_DCT(dev, dct, 0x27c, dword); - - /* 2.10.5.8.6.1.2 */ - dword = Get_NB32_DCT(dev, dct, 0x270); - dword &= ~(0x7ffff); /* DataPrbsSeed = 55555 */ - dword |= (0x44443); /* Use AGESA seed */ - Set_NB32_DCT(dev, dct, 0x270, dword); - - /* 2.10.5.8.2 (4) */ - dword = Get_NB32_DCT(dev, dct, 0x260); - dword &= ~(0x1fffff); /* CmdCount = 192 */ - dword |= 192; - Set_NB32_DCT(dev, dct, 0x260, dword); - - /* Configure Target A */ - dword = Get_NB32_DCT(dev, dct, 0x254); - dword &= ~(0x7 << 24); /* TgtChipSelect = Receiver */ - dword |= (Receiver & 0x7) << 24; - dword &= ~(0x7 << 21); /* TgtBank = 0 */ - dword &= ~(0x3ff); /* TgtAddress = 0 */ - Set_NB32_DCT(dev, dct, 0x254, dword); - - dword = Get_NB32_DCT(dev, dct, 0x250); - dword |= (0x1 << 3); /* ResetAllErr = 1 */ - dword &= ~(0x1 << 4); /* StopOnErr = 0 */ - dword &= ~(0x3 << 8); /* CmdTgt = 0 (Target A) */ - dword &= ~(0x7 << 5); /* CmdType = 0 (Read) */ - dword |= (0x1 << 11); /* SendCmd = 1 */ - Set_NB32_DCT(dev, dct, 0x250, dword); - - /* 2.10.5.8.6.1.2 Wait for TestStatus == 1 and CmdSendInProg == 0 */ - do { - dword = Get_NB32_DCT(dev, dct, 0x250); - } while ((dword & (0x1 << 12)) || (!(dword & (0x1 << 10)))); - - dword = Get_NB32_DCT(dev, dct, 0x250); - dword &= ~(0x1 << 11); /* SendCmd = 0 */ - Set_NB32_DCT(dev, dct, 0x250, dword); - - /* 2.10.5.8.6.1.1 Send Precharge Command */ - /* Wait 25 MEMCLKs. */ - precise_memclk_delay_fam15(pMCTstat, pDCTstat, dct, 25); - - dword = Get_NB32_DCT(dev, dct, 0x28c); - dword &= ~(0xff << 22); /* CmdChipSelect = Receiver */ - dword |= ((0x1 << Receiver) << 22); - dword &= ~(0x7 << 19); /* CmdBank = 0 */ - dword &= ~(0x3ffff); /* CmdAddress = 0x400 */ - dword |= 0x400; - dword |= (0x1 << 30); /* SendPchgCmd = 1 */ - Set_NB32_DCT(dev, dct, 0x28c, dword); - - /* Wait for SendPchgCmd == 0 */ - do { - dword = Get_NB32_DCT(dev, dct, 0x28c); - } while (dword & (0x1 << 30)); - - /* Wait 25 MEMCLKs. */ - precise_memclk_delay_fam15(pMCTstat, pDCTstat, dct, 25); - - /* Set CmdTestEnable = 0 */ - dword = Get_NB32_DCT(dev, dct, 0x250); - dword &= ~(0x1 << 2); - Set_NB32_DCT(dev, dct, 0x250, dword); -} - -/* DQS Receiver Enable Training (Family 15h) - * Algorithm detailed in: - * The Fam15h BKDG Rev. 3.14 section 2.10.5.8.2 - * This algorithm runs once at the lowest supported MEMCLK, - * then once again at the highest supported MEMCLK. - */ -static void dqsTrainRcvrEn_SW_Fam15(struct MCTStatStruc *pMCTstat, - struct DCTStatStruc *pDCTstat, u8 Pass) -{ - u8 Channel; - u8 _2Ranks; - u8 Addl_Index = 0; - u8 Receiver; - u8 _DisableDramECC = 0, _Wrap32Dis = 0, _SSE2 = 0; - u32 Errors; - - u32 val; - u32 dev; - u32 index_reg; - u32 ch_start, ch_end, ch; - u32 msr; - CRx_TYPE cr4; - u32 lo, hi; - - uint32_t dword; - uint8_t dimm; - uint8_t rank; - uint8_t lane; - uint8_t nibble; - uint8_t mem_clk; - uint16_t min_mem_clk; - uint16_t initial_seed; - uint8_t train_both_nibbles; - uint16_t current_total_delay[MAX_BYTE_LANES]; - uint16_t nibble0_current_total_delay[MAX_BYTE_LANES]; - uint16_t dqs_ret_pass1_total_delay[MAX_BYTE_LANES]; - uint16_t rank0_current_total_delay[MAX_BYTE_LANES]; - uint16_t phase_recovery_delays[MAX_BYTE_LANES]; - uint16_t seed[MAX_BYTE_LANES]; - uint16_t seed_gross[MAX_BYTE_LANES]; - uint16_t seed_fine[MAX_BYTE_LANES]; - uint16_t seed_pre_gross[MAX_BYTE_LANES]; - - uint8_t package_type = mctGet_NVbits(NV_PACK_TYPE); - uint16_t fam15h_freq_tab[] = {0, 0, 0, 0, 333, 0, 400, 0, 0, 0, 533, 0, 0, 0, 667, 0, 0, 0, 800, 0, 0, 0, 933}; - - uint8_t lane_count; - lane_count = get_available_lane_count(pMCTstat, pDCTstat); - - print_debug_dqs("\nTrainRcvEn: Node", pDCTstat->Node_ID, 0); - print_debug_dqs("TrainRcvEn: Pass", Pass, 0); - - min_mem_clk = mctGet_NVbits(NV_MIN_MEMCLK); - - train_both_nibbles = 0; - if (pDCTstat->Dimmx4Present) - if (is_fam15h()) - train_both_nibbles = 1; - - dev = pDCTstat->dev_dct; - index_reg = 0x98; - ch_start = 0; - ch_end = 2; - - for (ch = ch_start; ch < ch_end; ch++) { - uint8_t max_rd_latency = 0x55; - uint8_t p_state; - - /* 2.10.5.6 */ - fam15EnableTrainingMode(pMCTstat, pDCTstat, ch, 1); - - /* 2.10.5.2 */ - for (p_state = 0; p_state < 3; p_state++) { - val = Get_NB32_DCT_NBPstate(dev, ch, p_state, 0x210); - val &= ~(0x3ff << 22); /* MaxRdLatency = max_rd_latency */ - val |= (max_rd_latency & 0x3ff) << 22; - Set_NB32_DCT_NBPstate(dev, ch, p_state, 0x210, val); - } - } - - if (Pass != FirstPass) { - pDCTstat->DimmTrainFail = 0; - pDCTstat->CSTrainFail = ~pDCTstat->CSPresent; - } - - cr4 = read_cr4(); - if (cr4 & (1 << 9)) { /* save the old value */ - _SSE2 = 1; - } - cr4 |= (1 << 9); /* OSFXSR enable SSE2 */ - write_cr4(cr4); - - msr = HWCR_MSR; - _RDMSR(msr, &lo, &hi); - /* FIXME: Why use SSEDIS */ - if (lo & (1 << 17)) { /* save the old value */ - _Wrap32Dis = 1; - } - lo |= (1 << 17); /* HWCR.wrap32dis */ - lo &= ~(1 << 15); /* SSEDIS */ - _WRMSR(msr, lo, hi); /* Setting wrap32dis allows 64-bit memory references in real mode */ - - _DisableDramECC = mct_DisableDimmEccEn_D(pMCTstat, pDCTstat); - - Errors = 0; - dev = pDCTstat->dev_dct; - - for (Channel = 0; Channel < 2; Channel++) { - print_debug_dqs("\tTrainRcvEn51: Node ", pDCTstat->Node_ID, 1); - print_debug_dqs("\tTrainRcvEn51: Channel ", Channel, 1); - pDCTstat->Channel = Channel; - - mem_clk = Get_NB32_DCT(dev, Channel, 0x94) & 0x1f; - - Receiver = mct_InitReceiver_D(pDCTstat, Channel); - /* There are four receiver pairs, loosely associated with chipselects. - * This is essentially looping over each DIMM. - */ - for (; Receiver < 8; Receiver += 2) { - Addl_Index = (Receiver >> 1) * 3 + 0x10; - dimm = (Receiver >> 1); - - print_debug_dqs("\t\tTrainRcvEnd52: index ", Addl_Index, 2); - - if (!mct_RcvrRankEnabled_D(pMCTstat, pDCTstat, Channel, Receiver)) { - continue; - } - - /* Retrieve the total delay values from pass 1 of DQS receiver enable training */ - if (Pass != FirstPass) { - read_dqs_receiver_enable_control_registers(dqs_ret_pass1_total_delay, dev, Channel, dimm, index_reg); - } - - /* 2.10.5.8.2 - * Loop over all ranks - */ - if (mct_RcvrRankEnabled_D(pMCTstat, pDCTstat, Channel, Receiver+1)) - _2Ranks = 1; - else - _2Ranks = 0; - for (rank = 0; rank < (_2Ranks + 1); rank++) { - for (nibble = 0; nibble < (train_both_nibbles + 1); nibble++) { - /* 2.10.5.8.2 (1) - * Specify the target DIMM and nibble to be trained - */ - dword = Get_NB32_index_wait_DCT(dev, Channel, index_reg, 0x00000008); - dword &= ~(0x3 << 4); /* TrDimmSel = dimm */ - dword |= ((dimm & 0x3) << 4); - dword &= ~(0x1 << 2); /* TrNibbleSel = nibble */ - dword |= ((nibble & 0x1) << 2); - Set_NB32_index_wait_DCT(dev, Channel, index_reg, 0x00000008, dword); - - /* 2.10.5.8.2 (2) - * Retrieve gross and fine timing fields from write DQS registers - */ - read_dqs_write_timing_control_registers(current_total_delay, dev, Channel, dimm, index_reg); - - /* 2.10.5.8.2.1 - * Generate the DQS Receiver Enable Training Seed Values - */ - if (Pass == FirstPass) { - initial_seed = fam15_receiver_enable_training_seed(pDCTstat, Channel, dimm, rank, package_type); - - /* Adjust seed for the minimum platform supported frequency */ - initial_seed = (uint16_t) (((((uint64_t) initial_seed) * - fam15h_freq_tab[mem_clk] * 100) / (min_mem_clk * 100))); - - for (lane = 0; lane < lane_count; lane++) { - uint16_t wl_pass1_delay; - wl_pass1_delay = current_total_delay[lane]; - - seed[lane] = initial_seed + wl_pass1_delay; - } - } else { - uint8_t addr_prelaunch = 0; /* TODO: Fetch the correct value from RC2[0] */ - uint16_t register_delay; - int16_t seed_prescaling; - - memcpy(current_total_delay, dqs_ret_pass1_total_delay, sizeof(current_total_delay)); - if ((pDCTstat->Status & (1 << SB_Registered))) { - if (addr_prelaunch) - register_delay = 0x30; - else - register_delay = 0x20; - } else if ((pDCTstat->Status & (1 << SB_LoadReduced))) { - /* TODO - * Load reduced DIMM support unimplemented - */ - register_delay = 0x0; - } else { - register_delay = 0x0; - } - - for (lane = 0; lane < lane_count; lane++) { - seed_prescaling = current_total_delay[lane] - register_delay - 0x20; - seed[lane] = (uint16_t) (register_delay + ((((uint64_t) seed_prescaling) * fam15h_freq_tab[mem_clk] * 100) / (min_mem_clk * 100))); - } - } - - for (lane = 0; lane < lane_count; lane++) { - seed_gross[lane] = (seed[lane] >> 5) & 0x1f; - seed_fine[lane] = seed[lane] & 0x1f; - - /*if (seed_gross[lane] == 0) - seed_pre_gross[lane] = 0; - else */if (seed_gross[lane] & 0x1) - seed_pre_gross[lane] = 1; - else - seed_pre_gross[lane] = 2; - - /* Calculate phase recovery delays */ - phase_recovery_delays[lane] = ((seed_pre_gross[lane] & 0x1f) << 5) | (seed_fine[lane] & 0x1f); - - /* Set the gross delay. - * NOTE: While the BKDG states to only program DqsRcvEnGrossDelay, this appears - * to have been a misprint as DqsRcvEnFineDelay should be set to zero as well. - */ - current_total_delay[lane] = ((seed_gross[lane] & 0x1f) << 5); - } - - /* 2.10.5.8.2 (2) / 2.10.5.8.2.1 (5 6) - * Program PhRecFineDly and PhRecGrossDly - */ - write_dram_phase_recovery_control_registers(phase_recovery_delays, dev, Channel, dimm, index_reg); - - /* 2.10.5.8.2 (2) / 2.10.5.8.2.1 (7) - * Program the DQS Receiver Enable delay values for each lane - */ - write_dqs_receiver_enable_control_registers(current_total_delay, dev, Channel, dimm, index_reg); - - /* 2.10.5.8.2 (3) - * Program DqsRcvTrEn = 1 - */ - dword = Get_NB32_index_wait_DCT(dev, Channel, index_reg, 0x00000008); - dword |= (0x1 << 13); - Set_NB32_index_wait_DCT(dev, Channel, index_reg, 0x00000008, dword); - - /* 2.10.5.8.2 (4) - * Issue 192 read requests to the target rank - */ - generate_dram_receiver_enable_training_pattern_fam15(pMCTstat, pDCTstat, Channel, Receiver + (rank & 0x1)); - - /* 2.10.5.8.2 (5) - * Program DqsRcvTrEn = 0 - */ - dword = Get_NB32_index_wait_DCT(dev, Channel, index_reg, 0x00000008); - dword &= ~(0x1 << 13); - Set_NB32_index_wait_DCT(dev, Channel, index_reg, 0x00000008, dword); - - /* 2.10.5.8.2 (6) - * Read PhRecGrossDly, PhRecFineDly - */ - read_dram_phase_recovery_control_registers(phase_recovery_delays, dev, Channel, dimm, index_reg); - - /* 2.10.5.8.2 (7) - * Calculate and program the DQS Receiver Enable delay values - */ - for (lane = 0; lane < lane_count; lane++) { - current_total_delay[lane] = (phase_recovery_delays[lane] & 0x1f); - current_total_delay[lane] |= ((seed_gross[lane] + ((phase_recovery_delays[lane] >> 5) & 0x1f) - seed_pre_gross[lane] + 1) << 5); - if (nibble == 1) { - /* 2.10.5.8.2 (1) - * Average the trained values of both nibbles on x4 DIMMs - */ - current_total_delay[lane] = (nibble0_current_total_delay[lane] + current_total_delay[lane]) / 2; - } - } - -#if DQS_TRAIN_DEBUG > 1 - for (lane = 0; lane < 8; lane++) - printk(BIOS_DEBUG, "\t\tTrainRcvEn55: Channel: %d dimm: %d nibble: %d lane %d current_total_delay: %04x CH_D_B_RCVRDLY: %04x\n", - Channel, dimm, nibble, lane, current_total_delay[lane], pDCTstat->CH_D_B_RCVRDLY[Channel][dimm][lane]); -#endif - write_dqs_receiver_enable_control_registers(current_total_delay, dev, Channel, dimm, index_reg); - - if (nibble == 0) { - /* Back up the Nibble 0 delays for later use */ - memcpy(nibble0_current_total_delay, current_total_delay, sizeof(current_total_delay)); - } - - /* Exit nibble training if current DIMM is not x4 */ - if ((pDCTstat->Dimmx4Present & (1 << (dimm + Channel))) == 0) - break; - } - - if (_2Ranks) { - if (rank == 0) { - /* Back up the Rank 0 delays for later use */ - memcpy(rank0_current_total_delay, current_total_delay, sizeof(current_total_delay)); - } - if (rank == 1) { - /* 2.10.5.8.2 (8) - * Compute the average delay across both ranks and program the result into - * the DQS Receiver Enable delay registers - */ - for (lane = 0; lane < lane_count; lane++) { - current_total_delay[lane] = (rank0_current_total_delay[lane] + current_total_delay[lane]) / 2; - if (lane == 8) - pDCTstat->CH_D_BC_RCVRDLY[Channel][dimm] = current_total_delay[lane]; - else - pDCTstat->CH_D_B_RCVRDLY[Channel][dimm][lane] = current_total_delay[lane]; - } - write_dqs_receiver_enable_control_registers(current_total_delay, dev, Channel, dimm, index_reg); - } - } else { - /* Save the current delay for later use by other routines */ - for (lane = 0; lane < lane_count; lane++) { - if (lane == 8) - pDCTstat->CH_D_BC_RCVRDLY[Channel][dimm] = current_total_delay[lane]; - else - pDCTstat->CH_D_B_RCVRDLY[Channel][dimm][lane] = current_total_delay[lane]; - } - } - } - -#if DQS_TRAIN_DEBUG > 0 - for (lane = 0; lane < 8; lane++) - print_debug_dqs_pair("\t\tTrainRcvEn56: Lane ", lane, " current_total_delay ", current_total_delay[lane], 2); -#endif - } - } - - /* Calculate and program MaxRdLatency for both channels */ - Calc_SetMaxRdLatency_D_Fam15(pMCTstat, pDCTstat, 0, 0); - Calc_SetMaxRdLatency_D_Fam15(pMCTstat, pDCTstat, 1, 0); - - if (_DisableDramECC) { - mct_EnableDimmEccEn_D(pMCTstat, pDCTstat, _DisableDramECC); - } - - if (Pass == FirstPass) { - /*Disable DQSRcvrEn training mode */ - mct_DisableDQSRcvEn_D(pDCTstat); - } - - if (!_Wrap32Dis) { - msr = HWCR_MSR; - _RDMSR(msr, &lo, &hi); - lo &= ~(1<<17); /* restore HWCR.wrap32dis */ - _WRMSR(msr, lo, hi); - } - if (!_SSE2) { - cr4 = read_cr4(); - cr4 &= ~(1<<9); /* restore cr4.OSFXSR */ - write_cr4(cr4); - } - -#if DQS_TRAIN_DEBUG > 0 - { - u8 ChannelDTD; - printk(BIOS_DEBUG, "TrainRcvrEn: CH_MaxRdLat:\n"); - for (ChannelDTD = 0; ChannelDTD < 2; ChannelDTD++) { - printk(BIOS_DEBUG, "Channel:%x: %x\n", - ChannelDTD, pDCTstat->CH_MaxRdLat[ChannelDTD][0]); - } - } -#endif - -#if DQS_TRAIN_DEBUG > 0 - { - u16 valDTD; - u8 ChannelDTD, ReceiverDTD; - u8 i; - u16 *p; - - printk(BIOS_DEBUG, "TrainRcvrEn: CH_D_B_RCVRDLY:\n"); - for (ChannelDTD = 0; ChannelDTD < 2; ChannelDTD++) { - printk(BIOS_DEBUG, "Channel:%x\n", ChannelDTD); - for (ReceiverDTD = 0; ReceiverDTD < 8; ReceiverDTD+=2) { - printk(BIOS_DEBUG, "\t\tReceiver:%x:", ReceiverDTD); - p = pDCTstat->CH_D_B_RCVRDLY[ChannelDTD][ReceiverDTD>>1]; - for (i = 0; i < 8; i++) { - valDTD = p[i]; - printk(BIOS_DEBUG, " %03x", valDTD); - } - printk(BIOS_DEBUG, "\n"); - } - } - } -#endif - - printk(BIOS_DEBUG, "TrainRcvrEn: Status %x\n", pDCTstat->Status); - printk(BIOS_DEBUG, "TrainRcvrEn: ErrStatus %x\n", pDCTstat->ErrStatus); - printk(BIOS_DEBUG, "TrainRcvrEn: ErrCode %x\n", pDCTstat->ErrCode); - printk(BIOS_DEBUG, "TrainRcvrEn: Done\n\n"); -} - -static void write_max_read_latency_to_registers(struct MCTStatStruc *pMCTstat, - struct DCTStatStruc *pDCTstat, uint8_t dct, uint16_t *latency) -{ - uint32_t dword; - uint8_t nb_pstate; - - for (nb_pstate = 0; nb_pstate < 2; nb_pstate++) { - dword = Get_NB32_DCT_NBPstate(pDCTstat->dev_dct, dct, nb_pstate, 0x210); - dword &= ~(0x3ff << 22); - dword |= ((latency[nb_pstate] & 0x3ff) << 22); - Set_NB32_DCT_NBPstate(pDCTstat->dev_dct, dct, nb_pstate, 0x210, dword); - } -} - -/* DQS MaxRdLatency Training (Family 15h) - * Algorithm detailed in: - * The Fam15h BKDG Rev. 3.14 section 2.10.5.8.5.1 - * This algorithm runs at the highest supported MEMCLK. - */ -void dqsTrainMaxRdLatency_SW_Fam15(struct MCTStatStruc *pMCTstat, - struct DCTStatStruc *pDCTstat) -{ - u8 Channel; - u8 Receiver; - u8 _DisableDramECC = 0, _Wrap32Dis = 0, _SSE2 = 0; - u32 Errors; - - u32 dev; - u32 index_reg; - u32 ch_start, ch_end; - u32 msr; - CRx_TYPE cr4; - u32 lo, hi; - - uint32_t dword; - uint8_t dimm; - uint8_t lane; - uint8_t mem_clk; - uint32_t nb_clk; - uint8_t nb_pstate; - uint16_t current_total_delay[MAX_BYTE_LANES]; - uint16_t current_rdqs_total_delay[MAX_BYTE_LANES]; - uint8_t current_worst_case_total_delay_dimm; - uint16_t current_worst_case_total_delay_value; - - uint8_t lane_count; - lane_count = get_available_lane_count(pMCTstat, pDCTstat); - - uint16_t fam15h_freq_tab[] = {0, 0, 0, 0, 333, 0, 400, 0, 0, 0, 533, 0, 0, 0, 667, 0, 0, 0, 800, 0, 0, 0, 933}; - - print_debug_dqs("\nTrainMaxRdLatency: Node", pDCTstat->Node_ID, 0); - - dev = pDCTstat->dev_dct; - index_reg = 0x98; - ch_start = 0; - ch_end = 2; - - cr4 = read_cr4(); - if (cr4 & (1 << 9)) { /* save the old value */ - _SSE2 = 1; - } - cr4 |= (1 << 9); /* OSFXSR enable SSE2 */ - write_cr4(cr4); - - msr = HWCR_MSR; - _RDMSR(msr, &lo, &hi); - /* FIXME: Why use SSEDIS */ - if (lo & (1 << 17)) { /* save the old value */ - _Wrap32Dis = 1; - } - lo |= (1 << 17); /* HWCR.wrap32dis */ - lo &= ~(1 << 15); /* SSEDIS */ - _WRMSR(msr, lo, hi); /* Setting wrap32dis allows 64-bit memory references in real mode */ - - _DisableDramECC = mct_DisableDimmEccEn_D(pMCTstat, pDCTstat); - - Errors = 0; - dev = pDCTstat->dev_dct; - - for (Channel = 0; Channel < 2; Channel++) { - print_debug_dqs("\tTrainMaxRdLatency51: Node ", pDCTstat->Node_ID, 1); - print_debug_dqs("\tTrainMaxRdLatency51: Channel ", Channel, 1); - pDCTstat->Channel = Channel; - - if (pDCTstat->DIMMValidDCT[Channel] == 0) - continue; - - mem_clk = Get_NB32_DCT(dev, Channel, 0x94) & 0x1f; - - Receiver = mct_InitReceiver_D(pDCTstat, Channel); - - /* Find DIMM with worst case receiver enable delays */ - current_worst_case_total_delay_dimm = 0; - current_worst_case_total_delay_value = 0; - - /* There are four receiver pairs, loosely associated with chipselects. - * This is essentially looping over each DIMM. - */ - for (; Receiver < 8; Receiver += 2) { - dimm = (Receiver >> 1); - - print_debug_dqs("\t\tTrainMaxRdLatency52: Receiver ", Receiver, 2); - - if (!mct_RcvrRankEnabled_D(pMCTstat, pDCTstat, Channel, Receiver)) { - continue; - } - - /* Retrieve the total delay values from pass 1 of DQS receiver enable training */ - read_dqs_receiver_enable_control_registers(current_total_delay, dev, Channel, dimm, index_reg); - read_dqs_read_data_timing_registers(current_rdqs_total_delay, dev, Channel, dimm, index_reg); - - for (lane = 0; lane < lane_count; lane++) { - current_total_delay[lane] += current_rdqs_total_delay[lane]; - if (current_total_delay[lane] > current_worst_case_total_delay_value) { - current_worst_case_total_delay_dimm = dimm; - current_worst_case_total_delay_value = current_total_delay[lane]; - } - } - -#if DQS_TRAIN_DEBUG > 0 - for (lane = 0; lane < lane_count; lane++) - print_debug_dqs_pair("\t\tTrainMaxRdLatency56: Lane ", lane, " current_total_delay ", current_total_delay[lane], 2); -#endif - } - - /* 2.10.5.8.5.1.1 */ - Calc_SetMaxRdLatency_D_Fam15(pMCTstat, pDCTstat, Channel, 1); - - /* 2.10.5.8.5.1.[2,3] - * Write the DRAM training pattern to the test address - */ - write_dram_dqs_training_pattern_fam15(pMCTstat, pDCTstat, Channel, current_worst_case_total_delay_dimm << 1, 0xff, 0); - - /* 2.10.5.8.5.1.4 - * Incrementally test each MaxRdLatency candidate - */ - for (; pDCTstat->CH_MaxRdLat[Channel][0] < 0x3ff; pDCTstat->CH_MaxRdLat[Channel][0]++) { - write_max_read_latency_to_registers(pMCTstat, pDCTstat, Channel, pDCTstat->CH_MaxRdLat[Channel]); - read_dram_dqs_training_pattern_fam15(pMCTstat, pDCTstat, Channel, current_worst_case_total_delay_dimm << 1, 0xff, 0); - dword = Get_NB32_DCT(dev, Channel, 0x268) & 0x3ffff; - if (!dword) - break; - Set_NB32_index_wait_DCT(dev, Channel, index_reg, 0x00000050, 0x13131313); - } - dword = Get_NB32_DCT(dev, Channel, 0x268) & 0x3ffff; - if (dword) - printk(BIOS_ERR, "WARNING: MaxRdLatency training FAILED! Attempting to continue but your system may be unstable...\n"); - - /* 2.10.5.8.5.1.5 */ - nb_pstate = 0; - mem_clk = Get_NB32_DCT(dev, Channel, 0x94) & 0x1f; - if (fam15h_freq_tab[mem_clk] == 0) { - return; - } - dword = Get_NB32(pDCTstat->dev_nbctl, (0x160 + (nb_pstate * 4))); /* Retrieve NbDid, NbFid */ - nb_clk = (200 * (((dword >> 1) & 0x1f) + 0x4)) / (((dword >> 7) & 0x1)?2:1); - - pDCTstat->CH_MaxRdLat[Channel][0]++; - pDCTstat->CH_MaxRdLat[Channel][0] += ((((uint64_t)15 * 100000000000ULL) / ((uint64_t)fam15h_freq_tab[mem_clk] * 1000000ULL)) - * ((uint64_t)nb_clk * 1000)) / 1000000000ULL; - - write_max_read_latency_to_registers(pMCTstat, pDCTstat, Channel, pDCTstat->CH_MaxRdLat[Channel]); - } - - if (_DisableDramECC) { - mct_EnableDimmEccEn_D(pMCTstat, pDCTstat, _DisableDramECC); - } - - if (!_Wrap32Dis) { - msr = HWCR_MSR; - _RDMSR(msr, &lo, &hi); - lo &= ~(1<<17); /* restore HWCR.wrap32dis */ - _WRMSR(msr, lo, hi); - } - if (!_SSE2) { - cr4 = read_cr4(); - cr4 &= ~(1<<9); /* restore cr4.OSFXSR */ - write_cr4(cr4); - } - -#if DQS_TRAIN_DEBUG > 0 - { - u8 ChannelDTD; - printk(BIOS_DEBUG, "TrainMaxRdLatency: CH_MaxRdLat:\n"); - for (ChannelDTD = 0; ChannelDTD < 2; ChannelDTD++) { - printk(BIOS_DEBUG, "Channel:%x: %x\n", - ChannelDTD, pDCTstat->CH_MaxRdLat[ChannelDTD][0]); - } - } -#endif - - printk(BIOS_DEBUG, "TrainMaxRdLatency: Status %x\n", pDCTstat->Status); - printk(BIOS_DEBUG, "TrainMaxRdLatency: ErrStatus %x\n", pDCTstat->ErrStatus); - printk(BIOS_DEBUG, "TrainMaxRdLatency: ErrCode %x\n", pDCTstat->ErrCode); - printk(BIOS_DEBUG, "TrainMaxRdLatency: Done\n\n"); -} - -u8 mct_InitReceiver_D(struct DCTStatStruc *pDCTstat, u8 dct) -{ - if (pDCTstat->DIMMValidDCT[dct] == 0) { - return 8; - } else { - return 0; - } -} - -static void mct_DisableDQSRcvEn_D(struct DCTStatStruc *pDCTstat) -{ - u8 ch_end, ch; - u32 reg; - u32 dev; - u32 val; - - dev = pDCTstat->dev_dct; - if (pDCTstat->GangedMode) { - ch_end = 1; - } else { - ch_end = 2; - } - - for (ch = 0; ch < ch_end; ch++) { - reg = 0x78; - val = Get_NB32_DCT(dev, ch, reg); - val &= ~(1 << DqsRcvEnTrain); - Set_NB32_DCT(dev, ch, reg, val); - } -} - -/* mct_ModifyIndex_D - * Function only used once so it was inlined. - */ - -/* mct_GetInitFlag_D - * Function only used once so it was inlined. - */ - -/* Set F2x[1, 0]9C_x[2B:10] DRAM DQS Receiver Enable Timing Control Registers - * See BKDG Rev. 3.62 page 268 for more information - */ -void mct_SetRcvrEnDly_D(struct DCTStatStruc *pDCTstat, u16 RcvrEnDly, - u8 FinalValue, u8 Channel, u8 Receiver, u32 dev, - u32 index_reg, u8 Addl_Index, u8 Pass) -{ - u32 index; - u8 i; - u16 *p; - u32 val; - - if (RcvrEnDly == 0x1fe) { - /*set the boundary flag */ - pDCTstat->Status |= 1 << SB_DQSRcvLimit; - } - - /* DimmOffset not needed for CH_D_B_RCVRDLY array */ - for (i = 0; i < 8; i++) { - if (FinalValue) { - /*calculate dimm offset */ - p = pDCTstat->CH_D_B_RCVRDLY[Channel][Receiver >> 1]; - RcvrEnDly = p[i]; - } - - /* if flag = 0, set DqsRcvEn value to reg. */ - /* get the register index from table */ - index = Table_DQSRcvEn_Offset[i >> 1]; - index += Addl_Index; /* DIMMx DqsRcvEn byte0 */ - val = Get_NB32_index_wait_DCT(dev, Channel, index_reg, index); - if (i & 1) { - /* odd byte lane */ - val &= ~(0x1ff << 16); - val |= ((RcvrEnDly & 0x1ff) << 16); - } else { - /* even byte lane */ - val &= ~0x1ff; - val |= (RcvrEnDly & 0x1ff); - } - Set_NB32_index_wait_DCT(dev, Channel, index_reg, index, val); - } - -} - -/* Calculate MaxRdLatency - * Algorithm detailed in the Fam10h BKDG Rev. 3.62 section 2.8.9.9.5 - */ -static void mct_SetMaxLatency_D(struct DCTStatStruc *pDCTstat, u8 Channel, u16 DQSRcvEnDly) -{ - u32 dev; - u32 reg; - u32 SubTotal; - u32 index_reg; - u32 val; - - uint8_t cpu_val_n; - uint8_t cpu_val_p; - - u16 freq_tab[] = {400, 533, 667, 800}; - - /* Set up processor-dependent values */ - if (pDCTstat->LogicalCPUID & AMD_DR_Dx) { - /* Revision D and above */ - cpu_val_n = 4; - cpu_val_p = 29; - } else if (pDCTstat->LogicalCPUID & AMD_DR_Cx) { - /* Revision C */ - uint8_t package_type = mctGet_NVbits(NV_PACK_TYPE); - if ((package_type == PT_L1) /* Socket F (1207) */ - || (package_type == PT_M2) /* Socket AM3 */ - || (package_type == PT_S1)) { /* Socket S1g */ - cpu_val_n = 10; - cpu_val_p = 11; - } else { - cpu_val_n = 4; - cpu_val_p = 29; - } - } else { - /* Revision B and below */ - cpu_val_n = 10; - cpu_val_p = 11; - } - - if (pDCTstat->GangedMode) - Channel = 0; - - dev = pDCTstat->dev_dct; - index_reg = 0x98; - - /* Multiply the CAS Latency by two to get a number of 1/2 MEMCLKs units.*/ - val = Get_NB32_DCT(dev, Channel, 0x88); - SubTotal = ((val & 0x0f) + 4) << 1; /* SubTotal is 1/2 Memclk unit */ - - /* If registered DIMMs are being used then - * add 1 MEMCLK to the sub-total. - */ - val = Get_NB32_DCT(dev, Channel, 0x90); - if (!(val & (1 << UnBuffDimm))) - SubTotal += 2; - - /* If the address prelaunch is setup for 1/2 MEMCLKs then - * add 1, else add 2 to the sub-total. - * if (AddrCmdSetup || CsOdtSetup || CkeSetup) then K := K + 2; - */ - val = Get_NB32_index_wait_DCT(dev, Channel, index_reg, 0x04); - if (!(val & 0x00202020)) - SubTotal += 1; - else - SubTotal += 2; - - /* If the F2x[1, 0]78[RdPtrInit] field is 4, 5, 6 or 7 MEMCLKs, - * then add 4, 3, 2, or 1 MEMCLKs, respectively to the sub-total. */ - val = Get_NB32_DCT(dev, Channel, 0x78); - SubTotal += 8 - (val & 0x0f); - - /* Convert bits 7-5 (also referred to as the coarse delay) of - * the current (or worst case) DQS receiver enable delay to - * 1/2 MEMCLKs units, rounding up, and add this to the sub-total. - */ - SubTotal += DQSRcvEnDly >> 5; /* Retrieve gross delay portion of value */ - - /* Add "P" to the sub-total. "P" represents part of the - * processor specific constant delay value in the DRAM - * clock domain. - */ - SubTotal <<= 1; /*scale 1/2 MemClk to 1/4 MemClk */ - SubTotal += cpu_val_p; /*add "P" 1/2MemClk */ - SubTotal >>= 1; /*scale 1/4 MemClk back to 1/2 MemClk */ - - /* Convert the sub-total (in 1/2 MEMCLKs) to northbridge - * clocks (NCLKs) - */ - SubTotal *= 200 * ((Get_NB32(pDCTstat->dev_nbmisc, 0xd4) & 0x1f) + 4); - SubTotal /= freq_tab[((Get_NB32_DCT(pDCTstat->dev_dct, Channel, 0x94) & 0x7) - 3)]; - SubTotal = (SubTotal + (2 - 1)) / 2; /* Round up */ - - /* Add "N" NCLKs to the sub-total. "N" represents part of the - * processor specific constant value in the northbridge - * clock domain. - */ - SubTotal += (cpu_val_n) / 2; - - pDCTstat->CH_MaxRdLat[Channel][0] = SubTotal; - if (pDCTstat->GangedMode) { - pDCTstat->CH_MaxRdLat[1][0] = SubTotal; - } - - /* Program the F2x[1, 0]78[MaxRdLatency] register with - * the total delay value (in NCLKs). - */ - reg = 0x78; - val = Get_NB32_DCT(dev, Channel, reg); - val &= ~(0x3ff << 22); - val |= (SubTotal & 0x3ff) << 22; - - /* program MaxRdLatency to correspond with current delay */ - Set_NB32_DCT(dev, Channel, reg, val); -} - -static void mct_InitDQSPos4RcvrEn_D(struct MCTStatStruc *pMCTstat, - struct DCTStatStruc *pDCTstat) -{ - /* Initialize the DQS Positions in preparation for - * Receiver Enable Training. - * Write Position is 1/2 Memclock Delay - * Read Position is 1/2 Memclock Delay - */ - u8 i; - for (i = 0; i < 2; i++) { - InitDQSPos4RcvrEn_D(pMCTstat, pDCTstat, i); - } -} - -static void InitDQSPos4RcvrEn_D(struct MCTStatStruc *pMCTstat, - struct DCTStatStruc *pDCTstat, u8 Channel) -{ - /* Initialize the DQS Positions in preparation for - * Receiver Enable Training. - * Write Position is no Delay - * Read Position is 1/2 Memclock Delay - */ - - u8 i, j; - u32 dword; - u8 dn = 4; /* TODO: Rev C could be 4 */ - u32 dev = pDCTstat->dev_dct; - u32 index_reg = 0x98; - - /* FIXME: add Cx support */ - dword = 0x00000000; - for (i = 1; i <= 3; i++) { - for (j = 0; j < dn; j++) - /* DIMM0 Write Data Timing Low */ - /* DIMM0 Write ECC Timing */ - Set_NB32_index_wait_DCT(dev, Channel, index_reg, i + 0x100 * j, dword); - } - - /* errata #180 */ - dword = 0x2f2f2f2f; - for (i = 5; i <= 6; i++) { - for (j = 0; j < dn; j++) - /* DIMM0 Read DQS Timing Control Low */ - Set_NB32_index_wait_DCT(dev, Channel, index_reg, i + 0x100 * j, dword); - } - - dword = 0x0000002f; - for (j = 0; j < dn; j++) - /* DIMM0 Read DQS ECC Timing Control */ - Set_NB32_index_wait_DCT(dev, Channel, index_reg, 7 + 0x100 * j, dword); -} - -void SetEccDQSRcvrEn_D(struct DCTStatStruc *pDCTstat, u8 Channel) -{ - u32 dev; - u32 index_reg; - u32 index; - u8 ChipSel; - u16 *p; - u32 val; - - dev = pDCTstat->dev_dct; - index_reg = 0x98; - index = 0x12; - p = pDCTstat->CH_D_BC_RCVRDLY[Channel]; - print_debug_dqs("\t\tSetEccDQSRcvrPos: Channel ", Channel, 2); - for (ChipSel = 0; ChipSel < MAX_CS_SUPPORTED; ChipSel += 2) { - val = p[ChipSel>>1]; - Set_NB32_index_wait_DCT(dev, Channel, index_reg, index, val); - print_debug_dqs_pair("\t\tSetEccDQSRcvrPos: ChipSel ", - ChipSel, " rcvr_delay ", val, 2); - index += 3; - } -} - -static void CalcEccDQSRcvrEn_D(struct MCTStatStruc *pMCTstat, - struct DCTStatStruc *pDCTstat, u8 Channel) -{ - u8 ChipSel; - u16 EccDQSLike; - u8 EccDQSScale; - u32 val, val0, val1; - int16_t delay_differential; - - EccDQSLike = pDCTstat->CH_EccDQSLike[Channel]; - EccDQSScale = pDCTstat->CH_EccDQSScale[Channel]; - - for (ChipSel = 0; ChipSel < MAX_CS_SUPPORTED; ChipSel += 2) { - if (mct_RcvrRankEnabled_D(pMCTstat, pDCTstat, Channel, ChipSel)) { - u16 *p; - p = pDCTstat->CH_D_B_RCVRDLY[Channel][ChipSel>>1]; - - if (pDCTstat->Status & (1 << SB_Registered)) { - val0 = p[0x2]; - val1 = p[0x3]; - - delay_differential = (int16_t)val1 - (int16_t)val0; - delay_differential += (int16_t)val1; - - val = delay_differential; - } else { - /* DQS Delay Value of Data Bytelane - * most like ECC byte lane */ - val0 = p[EccDQSLike & 0x07]; - /* DQS Delay Value of Data Bytelane - * 2nd most like ECC byte lane */ - val1 = p[(EccDQSLike>>8) & 0x07]; - - if (val0 > val1) { - val = val0 - val1; - } else { - val = val1 - val0; - } - - val *= ~EccDQSScale; - val >>= 8; /* /256 */ - - if (val0 > val1) { - val -= val1; - } else { - val += val0; - } - } - - pDCTstat->CH_D_BC_RCVRDLY[Channel][ChipSel>>1] = val; - } - } - SetEccDQSRcvrEn_D(pDCTstat, Channel); -} - -/* 2.8.9.9.4 - * ECC Byte Lane Training - * DQS Receiver Enable Delay - */ -void mctSetEccDQSRcvrEn_D(struct MCTStatStruc *pMCTstat, - struct DCTStatStruc *pDCTstatA) -{ - u8 Node; - u8 i; - - for (Node = 0; Node < MAX_NODES_SUPPORTED; Node++) { - struct DCTStatStruc *pDCTstat; - pDCTstat = pDCTstatA + Node; - if (!pDCTstat->NodePresent) - break; - if (pDCTstat->DCTSysLimit) { - for (i = 0; i < 2; i++) - CalcEccDQSRcvrEn_D(pMCTstat, pDCTstat, i); - } - } -} - -void phyAssistedMemFnceTraining(struct MCTStatStruc *pMCTstat, - struct DCTStatStruc *pDCTstatA, int16_t single_node_number) -{ - u8 Node = 0; - struct DCTStatStruc *pDCTstat; - - printk(BIOS_DEBUG, "%s: Start\n", __func__); - - uint8_t start_node = 0; - uint8_t end_node = MAX_NODES_SUPPORTED; - - if (single_node_number >= 0) { - start_node = single_node_number; - end_node = single_node_number + 1; - } - - /* FIXME: skip for Ax */ - for (Node = start_node; Node < end_node; Node++) { - pDCTstat = pDCTstatA + Node; - if (!pDCTstat->NodePresent) - continue; - - if (pDCTstat->DCTSysLimit) { - if (is_fam15h()) { - /* Fam15h BKDG v3.14 section 2.10.5.3.3 - * This picks up where InitDDRPhy left off - */ - uint8_t dct; - uint8_t index; - uint32_t dword; - uint32_t datc_backup; - uint32_t training_dword; - uint32_t fence2_config_dword; - uint32_t fence_tx_pad_config_dword; - uint32_t index_reg = 0x98; - uint32_t dev = pDCTstat->dev_dct; - - for (dct = 0; dct < 2; dct++) { - if (!pDCTstat->DIMMValidDCT[dct]) - continue; - - printk(BIOS_SPEW, "%s: training node %d DCT %d\n", __func__, Node, dct); - - /* Back up D18F2x9C_x0000_0004_dct[1:0] */ - datc_backup = Get_NB32_index_wait_DCT(dev, dct, index_reg, 0x00000004); - - /* FenceTrSel = 0x2 */ - dword = Get_NB32_index_wait_DCT(dev, dct, index_reg, 0x00000008); - dword &= ~(0x3 << 6); - dword |= (0x2 << 6); - Set_NB32_index_wait_DCT(dev, dct, index_reg, 0x00000008, dword); - - /* Set phase recovery seed values */ - Set_NB32_index_wait_DCT(dev, dct, index_reg, 0x00000050, 0x13131313); - Set_NB32_index_wait_DCT(dev, dct, index_reg, 0x00000051, 0x13131313); - Set_NB32_index_wait_DCT(dev, dct, index_reg, 0x00000052, 0x00000013); - - training_dword = fenceDynTraining_D(pMCTstat, pDCTstat, dct); - - /* Save calculated fence value to the TX DLL */ - dword = Get_NB32_index_wait_DCT(dev, dct, index_reg, 0x0000000c); - dword &= ~(0x1f << 26); - dword |= ((training_dword & 0x1f) << 26); - Set_NB32_index_wait_DCT(dev, dct, index_reg, 0x0000000c, dword); - - /* D18F2x9C_x0D0F_0[F,8:0]0F_dct[1:0][AlwaysEnDllClks]=0x1 */ - for (index = 0; index < 0x9; index++) { - dword = Get_NB32_index_wait_DCT(dev, dct, index_reg, 0x0d0f000f | (index << 8)); - dword &= ~(0x7 << 12); - dword |= (0x1 << 12); - Set_NB32_index_wait_DCT(dev, dct, index_reg, 0x0d0f000f | (index << 8), dword); - } - - /* FenceTrSel = 0x1 */ - dword = Get_NB32_index_wait_DCT(dev, dct, index_reg, 0x00000008); - dword &= ~(0x3 << 6); - dword |= (0x1 << 6); - Set_NB32_index_wait_DCT(dev, dct, index_reg, 0x00000008, dword); - - /* Set phase recovery seed values */ - Set_NB32_index_wait_DCT(dev, dct, index_reg, 0x00000050, 0x13131313); - Set_NB32_index_wait_DCT(dev, dct, index_reg, 0x00000051, 0x13131313); - Set_NB32_index_wait_DCT(dev, dct, index_reg, 0x00000052, 0x00000013); - - training_dword = fenceDynTraining_D(pMCTstat, pDCTstat, dct); - - /* Save calculated fence value to the RX DLL */ - dword = Get_NB32_index_wait_DCT(dev, dct, index_reg, 0x0000000c); - dword &= ~(0x1f << 21); - dword |= ((training_dword & 0x1f) << 21); - Set_NB32_index_wait_DCT(dev, dct, index_reg, 0x0000000c, dword); - - /* D18F2x9C_x0D0F_0[F,8:0]0F_dct[1:0][AlwaysEnDllClks]=0x0 */ - for (index = 0; index < 0x9; index++) { - dword = Get_NB32_index_wait_DCT(dev, dct, index_reg, 0x0d0f000f | (index << 8)); - dword &= ~(0x7 << 12); - Set_NB32_index_wait_DCT(dev, dct, index_reg, 0x0d0f000f | (index << 8), dword); - } - - /* FenceTrSel = 0x3 */ - dword = Get_NB32_index_wait_DCT(dev, dct, index_reg, 0x00000008); - dword &= ~(0x3 << 6); - dword |= (0x3 << 6); - Set_NB32_index_wait_DCT(dev, dct, index_reg, 0x00000008, dword); - - /* Set phase recovery seed values */ - Set_NB32_index_wait_DCT(dev, dct, index_reg, 0x00000050, 0x13131313); - Set_NB32_index_wait_DCT(dev, dct, index_reg, 0x00000051, 0x13131313); - Set_NB32_index_wait_DCT(dev, dct, index_reg, 0x00000052, 0x00000013); - - fence_tx_pad_config_dword = fenceDynTraining_D(pMCTstat, pDCTstat, dct); - - /* Save calculated fence value to the TX Pad */ - dword = Get_NB32_index_wait_DCT(dev, dct, index_reg, 0x0000000c); - dword &= ~(0x1f << 16); - dword |= ((fence_tx_pad_config_dword & 0x1f) << 16); - Set_NB32_index_wait_DCT(dev, dct, index_reg, 0x0000000c, dword); - - /* Program D18F2x9C_x0D0F_[C,8,2][2:0]31_dct[1:0] */ - training_dword = fence_tx_pad_config_dword; - if (fence_tx_pad_config_dword < 16) - training_dword |= (0x1 << 4); - else - training_dword = 0; - for (index = 0; index < 0x3; index++) { - dword = Get_NB32_index_wait_DCT(dev, dct, index_reg, 0x0d0f2031 | (index << 8)); - dword &= ~(0x1f); - dword |= (training_dword & 0x1f); - Set_NB32_index_wait_DCT(dev, dct, index_reg, 0x0d0f2031 | (index << 8), dword); - } - for (index = 0; index < 0x3; index++) { - dword = Get_NB32_index_wait_DCT(dev, dct, index_reg, 0x0d0f8031 | (index << 8)); - dword &= ~(0x1f); - dword |= (training_dword & 0x1f); - Set_NB32_index_wait_DCT(dev, dct, index_reg, 0x0d0f8031 | (index << 8), dword); - } - for (index = 0; index < 0x3; index++) { - dword = Get_NB32_index_wait_DCT(dev, dct, index_reg, 0x0d0fc031 | (index << 8)); - dword &= ~(0x1f); - dword |= (training_dword & 0x1f); - Set_NB32_index_wait_DCT(dev, dct, index_reg, 0x0d0fc031 | (index << 8), dword); - } - - /* Assemble Fence2 configuration word (Fam15h BKDG v3.14 page 331) */ - dword = Get_NB32_index_wait_DCT(dev, dct, index_reg, 0x0000000c); - fence2_config_dword = 0; - - /* TxPad */ - training_dword = (dword >> 16) & 0x1f; - if (training_dword < 16) - training_dword |= 0x10; - else - training_dword = 0; - fence2_config_dword |= training_dword; - - /* RxDll */ - training_dword = (dword >> 21) & 0x1f; - if (training_dword < 16) - training_dword |= 0x10; - else - training_dword = 0; - fence2_config_dword |= (training_dword << 10); - - /* TxDll */ - training_dword = (dword >> 26) & 0x1f; - if (training_dword < 16) - training_dword |= 0x10; - else - training_dword = 0; - fence2_config_dword |= (training_dword << 5); - - /* Program D18F2x9C_x0D0F_0[F,8:0]31_dct[1:0] */ - for (index = 0; index < 0x9; index++) { - dword = Get_NB32_index_wait_DCT(dev, dct, index_reg, 0x0d0f0031 | (index << 8)); - dword &= ~(0x7fff); - dword |= fence2_config_dword; - Set_NB32_index_wait_DCT(dev, dct, index_reg, 0x0d0f0031 | (index << 8), dword); - } - - /* Restore D18F2x9C_x0000_0004_dct[1:0] */ - Set_NB32_index_wait_DCT(dev, dct, index_reg, 0x00000004, datc_backup); - - printk(BIOS_SPEW, "%s: done training node %d DCT %d\n", __func__, Node, dct); - } - } else { - fenceDynTraining_D(pMCTstat, pDCTstat, 0); - fenceDynTraining_D(pMCTstat, pDCTstat, 1); - } - } - } - - printk(BIOS_DEBUG, "%s: Done\n", __func__); -} - -uint32_t fenceDynTraining_D(struct MCTStatStruc *pMCTstat, - struct DCTStatStruc *pDCTstat, uint8_t dct) -{ - u16 avRecValue; - u32 val; - u32 dev; - u32 index_reg = 0x98; - u32 index; - - dev = pDCTstat->dev_dct; - - if (is_fam15h()) { - /* Set F2x[1,0]9C_x08[PhyFenceTrEn] */ - val = Get_NB32_index_wait_DCT(dev, dct, index_reg, 0x08); - val |= 1 << PhyFenceTrEn; - Set_NB32_index_wait_DCT(dev, dct, index_reg, 0x08, val); - - /* Wait 2000 MEMCLKs */ - precise_memclk_delay_fam15(pMCTstat, pDCTstat, dct, 2000); - - /* Clear F2x[1,0]9C_x08[PhyFenceTrEn] */ - val = Get_NB32_index_wait_DCT(dev, dct, index_reg, 0x08); - val &= ~(1 << PhyFenceTrEn); - Set_NB32_index_wait_DCT(dev, dct, index_reg, 0x08, val); - - /* BIOS reads the phase recovery engine registers - * F2x[1,0]9C_x[51:50] and F2x[1,0]9C_x52. - * Average the fine delay components only. - */ - avRecValue = 0; - for (index = 0x50; index <= 0x52; index++) { - val = Get_NB32_index_wait_DCT(dev, dct, index_reg, index); - avRecValue += val & 0x1f; - if (index != 0x52) { - avRecValue += (val >> 8) & 0x1f; - avRecValue += (val >> 16) & 0x1f; - avRecValue += (val >> 24) & 0x1f; - } - } - - val = avRecValue / 9; - if (avRecValue % 9) - val++; - avRecValue = val; - - if (avRecValue < 6) - avRecValue = 0; - else - avRecValue -= 6; - - return avRecValue; - } else { - /* BIOS first programs a seed value to the phase recovery engine - * (recommended 19) registers. - * Dram Phase Recovery Control Register (F2x[1,0]9C_x[51:50] and - * F2x[1,0]9C_x52.) . - */ - for (index = 0x50; index <= 0x52; index ++) { - val = (FenceTrnFinDlySeed & 0x1F); - if (index != 0x52) { - val |= val << 8 | val << 16 | val << 24; - } - Set_NB32_index_wait_DCT(dev, dct, index_reg, index, val); - } - - /* Set F2x[1,0]9C_x08[PhyFenceTrEn]=1. */ - val = Get_NB32_index_wait_DCT(dev, dct, index_reg, 0x08); - val |= 1 << PhyFenceTrEn; - Set_NB32_index_wait_DCT(dev, dct, index_reg, 0x08, val); - - /* Wait 200 MEMCLKs. */ - mct_Wait(50000); /* wait 200us */ - - /* Clear F2x[1,0]9C_x08[PhyFenceTrEn]=0. */ - val = Get_NB32_index_wait_DCT(dev, dct, index_reg, 0x08); - val &= ~(1 << PhyFenceTrEn); - Set_NB32_index_wait_DCT(dev, dct, index_reg, 0x08, val); - - /* BIOS reads the phase recovery engine registers - * F2x[1,0]9C_x[51:50] and F2x[1,0]9C_x52. */ - avRecValue = 0; - for (index = 0x50; index <= 0x52; index ++) { - val = Get_NB32_index_wait_DCT(dev, dct, index_reg, index); - avRecValue += val & 0x7F; - if (index != 0x52) { - avRecValue += (val >> 8) & 0x7F; - avRecValue += (val >> 16) & 0x7F; - avRecValue += (val >> 24) & 0x7F; - } - } - - val = avRecValue / 9; - if (avRecValue % 9) - val++; - avRecValue = val; - - /* Write the (averaged value -8) to F2x[1,0]9C_x0C[PhyFence]. */ - /* inlined mct_AdjustFenceValue() */ - /* TODO: The RBC0 is not supported. */ - /* if (pDCTstat->LogicalCPUID & AMD_RB_C0) - avRecValue -= 3; - else - */ - if (pDCTstat->LogicalCPUID & AMD_DR_Dx) - avRecValue -= 8; - else if (pDCTstat->LogicalCPUID & AMD_DR_Cx) - avRecValue -= 8; - else if (pDCTstat->LogicalCPUID & AMD_DR_Bx) - avRecValue -= 8; - - val = Get_NB32_index_wait_DCT(dev, dct, index_reg, 0x0C); - val &= ~(0x1F << 16); - val |= (avRecValue & 0x1F) << 16; - Set_NB32_index_wait_DCT(dev, dct, index_reg, 0x0C, val); - - /* Rewrite F2x[1,0]9C_x04-DRAM Address/Command Timing Control Register - * delays (both channels). - */ - val = Get_NB32_index_wait_DCT(dev, dct, index_reg, 0x04); - Set_NB32_index_wait_DCT(dev, dct, index_reg, 0x04, val); - - return avRecValue; - } -} - -void mct_Wait(u32 cycles) -{ - u32 saved; - u32 hi, lo, msr; - - /* Wait # of 50ns cycles - This seems like a hack to me... */ - - cycles <<= 3; /* x8 (number of 1.25ns ticks) */ - - msr = TSC_MSR; /* TSC */ - _RDMSR(msr, &lo, &hi); - saved = lo; - do { - _RDMSR(msr, &lo, &hi); - } while (lo - saved < cycles); -} diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mctsrc1p.c b/src/northbridge/amd/amdmct/mct_ddr3/mctsrc1p.c deleted file mode 100644 index 98aadddc6c..0000000000 --- a/src/northbridge/amd/amdmct/mct_ddr3/mctsrc1p.c +++ /dev/null @@ -1,104 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2010 Advanced Micro Devices, Inc. - * Copyright (C) 2015 Timothy Pearson , Raptor Engineering - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include - -#include "mct_d.h" -#include "mct_d_gcc.h" - -static uint8_t is_fam15h(void) -{ - uint8_t fam15h = 0; - uint32_t family; - - family = cpuid_eax(0x80000001); - family = ((family & 0xf00000) >> 16) | ((family & 0xf00) >> 8); - - if (family >= 0x6f) - /* Family 15h or later */ - fam15h = 1; - - return fam15h; -} - -u8 mct_checkNumberOfDqsRcvEn_1Pass(u8 pass) -{ - u8 ret = 1; - - if (is_fam15h()) { - /* Fam15h needs two passes */ - ret = 1; - } else { - if (pass == SecondPass) - ret = 0; - } - - return ret; -} - -u32 SetupDqsPattern_1PassA(u8 pass) -{ - return (u32) TestPattern1_D; -} - -u32 SetupDqsPattern_1PassB(u8 pass) -{ - return (u32) TestPattern0_D; -} - -static u16 mct_Average_RcvrEnDly_1Pass(struct DCTStatStruc *pDCTstat, u8 Channel, u8 Receiver, - u8 Pass) -{ - u16 i, MaxValue; - u16 *p; - u16 val; - - MaxValue = 0; - p = pDCTstat->CH_D_B_RCVRDLY[Channel][Receiver >> 1]; - - for (i = 0; i < 8; i++) { - /* get left value from DCTStatStruc.CHA_D0_B0_RCVRDLY*/ - val = p[i]; - /* get right value from DCTStatStruc.CHA_D0_B0_RCVRDLY_1*/ - val += Pass1MemClkDly; - /* write back the value to stack */ - if (val > MaxValue) - MaxValue = val; - - p[i] = val; - } - /* pDCTstat->DimmTrainFail &= ~(1<DqsRcvEn_Pass == 0xff) && (pass== FirstPass)) - ret = 2; - return ret; -} - -u16 mct_Average_RcvrEnDly_Pass(struct DCTStatStruc *pDCTstat, - u16 RcvrEnDly, u16 RcvrEnDlyLimit, - u8 Channel, u8 Receiver, u8 Pass) - -{ - return mct_Average_RcvrEnDly_1Pass(pDCTstat, Channel, Receiver, Pass); -} diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mctsrc2p.c b/src/northbridge/amd/amdmct/mct_ddr3/mctsrc2p.c deleted file mode 100644 index 8eeb93ff78..0000000000 --- a/src/northbridge/amd/amdmct/mct_ddr3/mctsrc2p.c +++ /dev/null @@ -1,126 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2010 Advanced Micro Devices, Inc. - * Copyright (C) 2015 Timothy Pearson , Raptor Engineering - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -u8 mct_checkNumberOfDqsRcvEn_Pass(u8 pass) -{ - return 1; -} - -u32 SetupDqsPattern_PassA(u8 Pass) -{ - u32 ret; - if (Pass == FirstPass) - ret = (u32) TestPattern1_D; - else - ret = (u32) TestPattern2_D; - - return ret; -} - -u32 SetupDqsPattern_PassB(u8 Pass) -{ - u32 ret; - if (Pass == FirstPass) - ret = (u32) TestPattern0_D; - else - ret = (u32) TestPattern2_D; - - return ret; -} - -u8 mct_Get_Start_RcvrEnDly_Pass(struct DCTStatStruc *pDCTstat, - u8 Channel, u8 Receiver, - u8 Pass) -{ - u8 RcvrEnDly; - - if (Pass == FirstPass) - RcvrEnDly = 0; - else { - u8 max = 0; - u8 val; - u8 i; - u8 *p = pDCTstat->persistentData.CH_D_B_RCVRDLY[Channel][Receiver>>1]; - u8 bn; - bn = 8; - - for (i = 0; i < bn; i++) { - val = p[i]; - - if (val > max) { - max = val; - } - } - RcvrEnDly = max; - } - - return RcvrEnDly; -} - -u16 mct_Average_RcvrEnDly_Pass(struct DCTStatStruc *pDCTstat, - u16 RcvrEnDly, u16 RcvrEnDlyLimit, - u8 Channel, u8 Receiver, u8 Pass) -{ - u8 i; - u16 *p; - u16 *p_1; - u16 val; - u16 val_1; - u8 valid = 1; - u8 bn; - - bn = 8; - - p = pDCTstat->persistentData.CH_D_B_RCVRDLY[Channel][Receiver>>1]; - - if (Pass == SecondPass) { /* second pass must average values */ - /* FIXME: which byte? */ - p_1 = pDCTstat->B_RCVRDLY_1; - /* p_1 = pDCTstat->persistentData.CH_D_B_RCVRDLY_1[Channel][Receiver>>1]; */ - for (i = 0; i < bn; i++) { - val = p[i]; - /* left edge */ - if (val != (RcvrEnDlyLimit - 1)) { - val -= Pass1MemClkDly; - val_1 = p_1[i]; - val += val_1; - val >>= 1; - p[i] = val; - } else { - valid = 0; - break; - } - } - if (!valid) { - pDCTstat->ErrStatus |= 1<DimmTrainFail &= ~(1<<(Receiver + Channel)); - } - } else { - for (i = 0; i < bn; i++) { - val = p[i]; - /* Add 1/2 Memlock delay */ - /* val += Pass1MemClkDly; */ - val += 0x5; /* NOTE: middle value with DQSRCVEN_SAVED_GOOD_TIMES */ - /* val += 0x02; */ - p[i] = val; - pDCTstat->DimmTrainFail &= ~(1<<(Receiver + Channel)); - } - } - - return RcvrEnDly; -} diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mcttmrl.c b/src/northbridge/amd/amdmct/mct_ddr3/mcttmrl.c deleted file mode 100644 index b6ab65e2f8..0000000000 --- a/src/northbridge/amd/amdmct/mct_ddr3/mcttmrl.c +++ /dev/null @@ -1,398 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2010 Advanced Micro Devices, Inc. - * Copyright (C) 2015 Timothy Pearson , Raptor Engineering - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -/* - * Description: Max Read Latency Training feature for DDR 3 MCT - */ - -#include -#include -#include -#include -#include "mct_d.h" -#include "mct_d_gcc.h" - -static u8 CompareMaxRdLatTestPattern_D(u32 pattern_buf, u32 addr); -static u32 GetMaxRdLatTestAddr_D(struct MCTStatStruc *pMCTstat, - struct DCTStatStruc *pDCTstat, u8 Channel, - u8 *MaxRcvrEnDly, u8 *valid); -u8 mct_GetStartMaxRdLat_D(struct MCTStatStruc *pMCTstat, - struct DCTStatStruc *pDCTstat, u8 Channel, - u8 DQSRcvEnDly, u32 *Margin); -static void maxRdLatencyTrain_D(struct MCTStatStruc *pMCTstat, - struct DCTStatStruc *pDCTstat); -static void mct_setMaxRdLatTrnVal_D(struct DCTStatStruc *pDCTstat, u8 Channel, - u16 MaxRdLatVal); - -/*Warning: These must be located so they do not cross a logical 16-bit - segment boundary!*/ -static const u32 TestMaxRdLAtPattern_D[] = { - 0x6E0E3FAC, 0x0C3CFF52, - 0x4A688181, 0x49C5B613, - 0x7C780BA6, 0x5C1650E3, - 0x0C4F9D76, 0x0C6753E6, - 0x205535A5, 0xBABFB6CA, - 0x610E6E5F, 0x0C5F1C87, - 0x488493CE, 0x14C9C383, - 0xF5B9A5CD, 0x9CE8F615, - - 0xAAD714B5, 0xC38F1B4C, - 0x72ED647C, 0x669F7562, - 0x5233F802, 0x4A898B30, - 0x10A40617, 0x3326B465, - 0x55386E04, 0xC807E3D3, - 0xAB49E193, 0x14B4E63A, - 0x67DF2495, 0xEA517C45, - 0x7624CE51, 0xF8140C51, - - 0x4824BD23, 0xB61DD0C9, - 0x072BCFBE, 0xE8F3807D, - 0x919EA373, 0x25E30C47, - 0xFEB12958, 0x4DA80A5A, - 0xE9A0DDF8, 0x792B0076, - 0xE81C73DC, 0xF025B496, - 0x1DB7E627, 0x808594FE, - 0x82668268, 0x655C7783, -}; - -static u32 SetupMaxRdPattern(struct MCTStatStruc *pMCTstat, - struct DCTStatStruc *pDCTstat, - u32 *buffer) -{ - /* 1. Copy the alpha and Beta patterns from ROM to Cache, - * aligning on 16 byte boundary - * 2. Set the ptr to Cacheable copy in DCTStatstruc.PtrPatternBufA - * for Alpha - * 3. Set the ptr to Cacheable copy in DCTStatstruc.PtrPatternBufB - * for Beta - */ - u32 *buf; - u8 i; - - buf = (u32 *)(((u32)buffer + 0x10) & (0xfffffff0)); - - for (i = 0; i < (16 * 3); i++) { - buf[i] = TestMaxRdLAtPattern_D[i]; - } - - return (u32)buf; -} - -void TrainMaxReadLatency_D(struct MCTStatStruc *pMCTstat, - struct DCTStatStruc *pDCTstatA) -{ - u8 Node; - - for (Node = 0; Node < MAX_NODES_SUPPORTED; Node++) { - struct DCTStatStruc *pDCTstat; - pDCTstat = pDCTstatA + Node; - - if (!pDCTstat->NodePresent) - break; - - if (pDCTstat->DCTSysLimit) - maxRdLatencyTrain_D(pMCTstat, pDCTstat); - } -} - -static void maxRdLatencyTrain_D(struct MCTStatStruc *pMCTstat, - struct DCTStatStruc *pDCTstat) -{ - u8 Channel; - u32 TestAddr0; - u8 _DisableDramECC = 0, _Wrap32Dis = 0, _SSE2 = 0; - u16 MaxRdLatDly; - u8 RcvrEnDly = 0; - u32 PatternBuffer[60]; /* FIXME: why not 48 + 4 */ - u32 Margin; - u32 addr; - CRx_TYPE cr4; - u32 lo, hi; - - u8 valid; - u32 pattern_buf; - - cr4 = read_cr4(); - if (cr4 & (1<<9)) { /* save the old value */ - _SSE2 = 1; - } - cr4 |= (1<<9); /* OSFXSR enable SSE2 */ - write_cr4(cr4); - - addr = HWCR_MSR; - _RDMSR(addr, &lo, &hi); - if (lo & (1<<17)) { /* save the old value */ - _Wrap32Dis = 1; - } - lo |= (1<<17); /* HWCR.wrap32dis */ - lo &= ~(1<<15); /* SSEDIS */ - /* Setting wrap32dis allows 64-bit memory references in - real mode */ - _WRMSR(addr, lo, hi); - - _DisableDramECC = mct_DisableDimmEccEn_D(pMCTstat, pDCTstat); - - pattern_buf = SetupMaxRdPattern(pMCTstat, pDCTstat, PatternBuffer); - - for (Channel = 0; Channel < 2; Channel++) { - print_debug_dqs("\tMaxRdLatencyTrain51: Channel ",Channel, 1); - pDCTstat->Channel = Channel; - - if ((pDCTstat->Status & (1 << SB_128bitmode)) && Channel) - break; /*if ganged mode, skip DCT 1 */ - - TestAddr0 = GetMaxRdLatTestAddr_D(pMCTstat, pDCTstat, Channel, &RcvrEnDly, &valid); - if (!valid) /* Address not supported on current CS */ - continue; - /* rank 1 of DIMM, testpattern 0 */ - WriteMaxRdLat1CLTestPattern_D(pattern_buf, TestAddr0); - - MaxRdLatDly = mct_GetStartMaxRdLat_D(pMCTstat, pDCTstat, Channel, RcvrEnDly, &Margin); - print_debug_dqs("\tMaxRdLatencyTrain52: MaxRdLatDly start ", MaxRdLatDly, 2); - print_debug_dqs("\tMaxRdLatencyTrain52: MaxRdLatDly Margin ", Margin, 2); - while (MaxRdLatDly < MAX_RD_LAT) { /* sweep Delay value here */ - mct_setMaxRdLatTrnVal_D(pDCTstat, Channel, MaxRdLatDly); - ReadMaxRdLat1CLTestPattern_D(TestAddr0); - if (CompareMaxRdLatTestPattern_D(pattern_buf, TestAddr0) == DQS_PASS) - break; - SetTargetWTIO_D(TestAddr0); - FlushMaxRdLatTestPattern_D(TestAddr0); - ResetTargetWTIO_D(); - MaxRdLatDly++; - } - print_debug_dqs("\tMaxRdLatencyTrain53: MaxRdLatDly end ", MaxRdLatDly, 2); - mct_setMaxRdLatTrnVal_D(pDCTstat, Channel, MaxRdLatDly + Margin); - } - - if (_DisableDramECC) { - mct_EnableDimmEccEn_D(pMCTstat, pDCTstat, _DisableDramECC); - } - - if (!_Wrap32Dis) { - addr = HWCR_MSR; - _RDMSR(addr, &lo, &hi); - lo &= ~(1<<17); /* restore HWCR.wrap32dis */ - _WRMSR(addr, lo, hi); - } - if (!_SSE2) { - cr4 = read_cr4(); - cr4 &= ~(1<<9); /* restore cr4.OSFXSR */ - write_cr4(cr4); - } - -#if DQS_TRAIN_DEBUG > 0 - { - u8 ChannelDTD; - printk(BIOS_DEBUG, "maxRdLatencyTrain: CH_MaxRdLat:\n"); - for (ChannelDTD = 0; ChannelDTD < 2; ChannelDTD++) { - printk(BIOS_DEBUG, "Channel: %02x: %02x\n", ChannelDTD, pDCTstat->CH_MaxRdLat[ChannelDTD][0]); - } - } -#endif -} - -static void mct_setMaxRdLatTrnVal_D(struct DCTStatStruc *pDCTstat, - u8 Channel, u16 MaxRdLatVal) -{ - u8 i; - u32 reg; - u32 dev; - u32 val; - - if (pDCTstat->GangedMode) { - Channel = 0; /* for safe */ - for (i = 0; i < 2; i++) - pDCTstat->CH_MaxRdLat[i][0] = MaxRdLatVal; - } else { - pDCTstat->CH_MaxRdLat[Channel][0] = MaxRdLatVal; - } - - dev = pDCTstat->dev_dct; - reg = 0x78; - val = Get_NB32_DCT(dev, Channel, reg); - val &= ~(0x3ff<<22); - val |= MaxRdLatVal<<22; - /* program MaxRdLatency to correspond with current delay */ - Set_NB32_DCT(dev, Channel, reg, val); -} - -static u8 CompareMaxRdLatTestPattern_D(u32 pattern_buf, u32 addr) -{ - /* Compare only the first beat of data. Since target addrs are cache - * line aligned, the Channel parameter is used to determine which cache - * QW to compare. - */ - - u32 *test_buf = (u32 *)pattern_buf; - u32 addr_lo; - u32 val, val_test; - int i; - u8 ret = DQS_PASS; - - SetUpperFSbase(addr); - addr_lo = addr<<8; - - _EXECFENCE; - for (i = 0; i < 16*3; i++) { - val = read32_fs(addr_lo); - val_test = test_buf[i]; - - print_debug_dqs_pair("\t\t\t\t\t\ttest_buf = ", (u32)test_buf, " value = ", val_test, 5); - print_debug_dqs_pair("\t\t\t\t\t\ttaddr_lo = ", addr_lo, " value = ", val, 5); - if (val != val_test) { - ret = DQS_FAIL; - break; - } - addr_lo += 4; - } - - return ret; -} - -static u32 GetMaxRdLatTestAddr_D(struct MCTStatStruc *pMCTstat, - struct DCTStatStruc *pDCTstat, - u8 Channel, u8 *MaxRcvrEnDly, - u8 *valid) -{ - u8 Max = 0; - - u8 Channel_Max = 0; - u8 d; - u8 d_Max = 0; - - u8 Byte; - u32 TestAddr0 = 0; - u8 ch, ch_start, ch_end; - u8 bn; - - bn = 8; - - if (pDCTstat->Status & (1 << SB_128bitmode)) { - ch_start = 0; - ch_end = 2; - } else { - ch_start = Channel; - ch_end = Channel + 1; - } - - *valid = 0; - - for (ch = ch_start; ch < ch_end; ch++) { - for (d = 0; d < 4; d++) { - for (Byte = 0; Byte < bn; Byte++) { - u8 tmp; - tmp = pDCTstat->CH_D_B_RCVRDLY[ch][d][Byte]; - if (tmp > Max) { - Max = tmp; - Channel_Max = Channel; - d_Max = d; - } - } - } - } - - if (mct_RcvrRankEnabled_D(pMCTstat, pDCTstat, Channel_Max, d_Max << 1)) { - TestAddr0 = mct_GetMCTSysAddr_D(pMCTstat, pDCTstat, Channel_Max, d_Max << 1, valid); - } - - if (*valid) - *MaxRcvrEnDly = Max; - - return TestAddr0; -} - -u8 mct_GetStartMaxRdLat_D(struct MCTStatStruc *pMCTstat, - struct DCTStatStruc *pDCTstat, - u8 Channel, u8 DQSRcvEnDly, u32 *Margin) -{ - u32 SubTotal; - u32 val; - u32 valx; - u32 valxx; - u32 index_reg; - u32 dev; - - if (pDCTstat->GangedMode) - Channel = 0; - - index_reg = 0x98; - - dev = pDCTstat->dev_dct; - - /* Multiply the CAS Latency by two to get a number of 1/2 MEMCLKs units.*/ - val = Get_NB32_DCT(dev, Channel, 0x88); - SubTotal = ((val & 0x0f) + 1) << 1; /* SubTotal is 1/2 Memclk unit */ - - /* If registered DIMMs are being used then add 1 MEMCLK to the sub-total*/ - val = Get_NB32_DCT(dev, Channel, 0x90); - if (!(val & (1 << UnBuffDimm))) - SubTotal += 2; - - /*If the address prelaunch is setup for 1/2 MEMCLKs then add 1, - * else add 2 to the sub-total. if (AddrCmdSetup || CsOdtSetup - * || CkeSetup) then K := K + 2; */ - val = Get_NB32_index_wait_DCT(dev, Channel, index_reg, 0x04); - if (!(val & 0x00202020)) - SubTotal += 1; - else - SubTotal += 2; - - /* If the F2x[1, 0]78[RdPtrInit] field is 4, 5, 6 or 7 MEMCLKs, - * then add 4, 3, 2, or 1 MEMCLKs, respectively to the sub-total. */ - val = Get_NB32_DCT(dev, Channel, 0x78); - SubTotal += 8 - (val & 0x0f); - - /* Convert bits 7-5 (also referred to as the course delay) of the current - * (or worst case) DQS receiver enable delay to 1/2 MEMCLKs units, - * rounding up, and add this to the sub-total. */ - SubTotal += DQSRcvEnDly >> 5; /*BOZO-no rounding up */ - - SubTotal <<= 1; /*scale 1/2 MemClk to 1/4 MemClk */ - - /* Convert the sub-total (in 1/2 MEMCLKs) to northbridge clocks (NCLKs) - * as follows (assuming DDR400 and assuming that no P-state or link speed - * changes have occurred). */ - - /*New formula: - SubTotal *= 3*(Fn2xD4[NBFid]+4)/(3+Fn2x94[MemClkFreq])/2 */ - val = Get_NB32_DCT(dev, Channel, 0x94); - /* SubTotal div 4 to scale 1/4 MemClk back to MemClk */ - val &= 7; - if (val >= 3) { - val <<= 1; - } else - val += 3; - valx = (val) << 2; /* SubTotal div 4 to scale 1/4 MemClk back to MemClk */ - - val = Get_NB32(pDCTstat->dev_nbmisc, 0xD4); - val = ((val & 0x1f) + 4) * 3; - - /* Calculate 1 MemClk + 1 NCLK delay in NCLKs for margin */ - valxx = val << 2; - valxx /= valx; - if (valxx % valx) - valxx++; /* round up */ - valxx++; /* add 1NCLK */ - *Margin = valxx; /* one MemClk delay in NCLKs and one additional NCLK */ - - val *= SubTotal; - - val /= valx; - if (val % valx) - val++; /* round up */ - - return val; -} diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mctwl.c b/src/northbridge/amd/amdmct/mct_ddr3/mctwl.c deleted file mode 100644 index 82523e01b8..0000000000 --- a/src/northbridge/amd/amdmct/mct_ddr3/mctwl.c +++ /dev/null @@ -1,509 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2010 Advanced Micro Devices, Inc. - * Copyright (C) 2015 - 2016 Raptor Engineering, LLC - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include - -#include "mct_d.h" -#include "mct_d_gcc.h" - -static uint8_t is_fam15h(void) -{ - uint8_t fam15h = 0; - uint32_t family; - - family = cpuid_eax(0x80000001); - family = ((family & 0xf00000) >> 16) | ((family & 0xf00) >> 8); - - if (family >= 0x6f) - /* Family 15h or later */ - fam15h = 1; - - return fam15h; -} - -static void AgesaDelay(u32 msec) -{ - mct_Wait(msec*10); -} - -void PrepareC_MCT(struct MCTStatStruc *pMCTstat, - struct DCTStatStruc *pDCTstat) -{ - pDCTstat->C_MCTPtr->AgesaDelay = AgesaDelay; -} - -void PrepareC_DCT(struct MCTStatStruc *pMCTstat, - struct DCTStatStruc *pDCTstat, u8 dct) -{ - u8 dimm; - u16 DimmValid; - u16 Dimmx8Present; - - dct &= 1; - - pDCTstat->C_DCTPtr[dct]->DctTrain = dct; - - if (dct == 1) { - Dimmx8Present = pDCTstat->Dimmx8Present >> 1; - } else - Dimmx8Present = pDCTstat->Dimmx8Present; - Dimmx8Present &= 0x55; - - pDCTstat->C_DCTPtr[dct]->MaxDimmsInstalled = pDCTstat->MAdimms[dct]; - DimmValid = pDCTstat->DIMMValidDCT[dct]; - - pDCTstat->C_DCTPtr[dct]->NodeId = pDCTstat->Node_ID; - pDCTstat->C_DCTPtr[dct]->LogicalCPUID = pDCTstat->LogicalCPUID; - - for (dimm = 0; dimm < MAX_DIMMS; dimm++) { - if (DimmValid & (1 << (dimm << 1))) - pDCTstat->C_DCTPtr[dct]->DimmPresent[dimm] = 1; - if (Dimmx8Present & (1 << (dimm << 1))) - pDCTstat->C_DCTPtr[dct]->DimmX8Present[dimm] = 1; - } - - if (pDCTstat->GangedMode & (1 << 0)) - pDCTstat->C_DCTPtr[dct]->CurrDct = 0; - else - pDCTstat->C_DCTPtr[dct]->CurrDct = dct; - - pDCTstat->C_DCTPtr[dct]->DctCSPresent = pDCTstat->CSPresent_DCT[dct]; - if (!(pDCTstat->GangedMode & (1 << 0)) && (dct == 1)) - pDCTstat->C_DCTPtr[dct]->DctCSPresent = pDCTstat->CSPresent_DCT[0]; - - if (pDCTstat->Status & (1 << SB_Registered)) { - pDCTstat->C_DCTPtr[dct]->Status[DCT_STATUS_REGISTERED] = 1; - pDCTstat->C_DCTPtr[dct]->Status[DCT_STATUS_OnDimmMirror] = 0; - } else { - if (pDCTstat->MirrPresU_NumRegR > 0) - pDCTstat->C_DCTPtr[dct]->Status[DCT_STATUS_OnDimmMirror] = 1; - pDCTstat->C_DCTPtr[dct]->Status[DCT_STATUS_REGISTERED] = 0; - } - - if (pDCTstat->Status & (1 << SB_LoadReduced)) { - pDCTstat->C_DCTPtr[dct]->Status[DCT_STATUS_LOAD_REDUCED] = 1; - } else { - pDCTstat->C_DCTPtr[dct]->Status[DCT_STATUS_LOAD_REDUCED] = 0; - } - - pDCTstat->C_DCTPtr[dct]->RegMan1Present = pDCTstat->RegMan1Present; - - for (dimm = 0; dimm < MAX_TOTAL_DIMMS; dimm++) { - u8 DimmRanks; - if (DimmValid & (1 << (dimm << 1))) { - DimmRanks = 1; - if (pDCTstat->DimmDRPresent & (1 << ((dimm << 1) + dct))) - DimmRanks = 2; - else if (pDCTstat->DimmQRPresent & (1 << ((dimm << 1) + dct))) - DimmRanks = 4; - } else - DimmRanks = 0; - pDCTstat->C_DCTPtr[dct]->DimmRanks[dimm] = DimmRanks; - } -} - -void EnableZQcalibration(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstat) -{ - u32 val; - - val = Get_NB32_DCT(pDCTstat->dev_dct, 0, 0x94); - val |= 1 << 11; - Set_NB32_DCT(pDCTstat->dev_dct, 0, 0x94, val); - - val = Get_NB32_DCT(pDCTstat->dev_dct, 1, 0x94); - val |= 1 << 11; - Set_NB32_DCT(pDCTstat->dev_dct, 1, 0x94, val); -} - -void DisableZQcalibration(struct MCTStatStruc *pMCTstat, - struct DCTStatStruc *pDCTstat) -{ - u32 val; - - val = Get_NB32_DCT(pDCTstat->dev_dct, 0, 0x94); - val &= ~(1 << 11); - val &= ~(1 << 10); - Set_NB32_DCT(pDCTstat->dev_dct, 0, 0x94, val); - - val = Get_NB32_DCT(pDCTstat->dev_dct, 1, 0x94); - val &= ~(1 << 11); - val &= ~(1 << 10); - Set_NB32_DCT(pDCTstat->dev_dct, 1, 0x94, val); -} - -static void EnterSelfRefresh(struct MCTStatStruc *pMCTstat, - struct DCTStatStruc *pDCTstat) -{ - u8 DCT0Present, DCT1Present; - u32 val; - - DCT0Present = pDCTstat->DIMMValidDCT[0]; - if (pDCTstat->GangedMode) - DCT1Present = 0; - else - DCT1Present = pDCTstat->DIMMValidDCT[1]; - - /* Program F2x[1, 0]90[EnterSelfRefresh]=1. */ - if (DCT0Present) { - val = Get_NB32_DCT(pDCTstat->dev_dct, 0, 0x90); - val |= 1 << EnterSelfRef; - Set_NB32_DCT(pDCTstat->dev_dct, 0, 0x90, val); - } - if (DCT1Present) { - val = Get_NB32_DCT(pDCTstat->dev_dct, 1, 0x90); - val |= 1 << EnterSelfRef; - Set_NB32_DCT(pDCTstat->dev_dct, 1, 0x90, val); - } - /* Wait until the hardware resets F2x[1, 0]90[EnterSelfRefresh]=0. */ - if (DCT0Present) - do { - val = Get_NB32_DCT(pDCTstat->dev_dct, 0, 0x90); - } while (val & (1 <dev_dct, 1, 0x90); - } while (val & (1 <DIMMValidDCT[0]; - if (pDCTstat->GangedMode) - DCT1Present = 0; - else - DCT1Present = pDCTstat->DIMMValidDCT[1]; - - if (is_fam15h()) { - /* Program D18F2x9C_x0D0F_E006_dct[1:0][PllLockTime] = 0x190 */ - if (DCT0Present) { - dword = Get_NB32_index_wait_DCT(pDCTstat->dev_dct, 0, 0x98, 0x0d0fe006); - dword &= ~(0x0000ffff); - dword |= 0x00000190; - Set_NB32_index_wait_DCT(pDCTstat->dev_dct, 0, 0x98, 0x0d0fe006, dword); - } - if (DCT1Present) { - dword = Get_NB32_index_wait_DCT(pDCTstat->dev_dct, 1, 0x98, 0x0d0fe006); - dword &= ~(0x0000ffff); - dword |= 0x00000190; - Set_NB32_index_wait_DCT(pDCTstat->dev_dct, 1, 0x98, 0x0d0fe006, dword); - } - } else { - /* Program F2x[1, 0]9C[DisAutoComp]=1. */ - if (DCT0Present) { - dword = Get_NB32_index_wait_DCT(pDCTstat->dev_dct, 0, 0x98, 8); - dword |= 1 << DisAutoComp; - Set_NB32_index_wait_DCT(pDCTstat->dev_dct, 0, 0x98, 8, dword); - mct_Wait(100); /* Wait for 5us */ - } - if (DCT1Present) { - dword = Get_NB32_index_wait_DCT(pDCTstat->dev_dct, 1, 0x98, 8); - dword |= 1 << DisAutoComp; - Set_NB32_index_wait_DCT(pDCTstat->dev_dct, 1, 0x98, 8, dword); - mct_Wait(100); /* Wait for 5us */ - } - } - - /* Program F2x[1, 0]94[MemClkFreqVal] = 0. */ - if (DCT0Present) { - dword = Get_NB32_DCT(pDCTstat->dev_dct, 0, 0x94); - dword &= ~(1 << MemClkFreqVal); - Set_NB32_DCT(pDCTstat->dev_dct, 0, 0x94, dword); - } - if (DCT1Present) { - dword = Get_NB32_DCT(pDCTstat->dev_dct, 1, 0x94); - dword &= ~(1 << MemClkFreqVal); - Set_NB32_DCT(pDCTstat->dev_dct, 1, 0x94, dword); - } - - /* Program F2x[1, 0]94[MemClkFreq] to specify the target MEMCLK frequency. */ - if (is_fam15h()) { - offset = 0x0; - mask = 0x1f; - } else { - offset = 0x1; - mask = 0x7; - } - if (DCT0Present) { - dword = Get_NB32_DCT(pDCTstat->dev_dct, 0, 0x94); - dword &= ~mask; - dword |= (pDCTstat->TargetFreq - offset) & mask; - Set_NB32_DCT(pDCTstat->dev_dct, 0, 0x94, dword); - } - if (DCT1Present) { - dword = Get_NB32_DCT(pDCTstat->dev_dct, 1, 0x94); - dword &= ~mask; - dword |= (pDCTstat->TargetFreq - offset) & mask; - Set_NB32_DCT(pDCTstat->dev_dct, 1, 0x94, dword); - } - - if (is_fam15h()) { - if (DCT0Present) { - mctGet_PS_Cfg_D(pMCTstat, pDCTstat, 0); - set_2t_configuration(pMCTstat, pDCTstat, 0); - mct_BeforePlatformSpec(pMCTstat, pDCTstat, 0); - mct_PlatformSpec(pMCTstat, pDCTstat, 0); - } - if (DCT1Present) { - mctGet_PS_Cfg_D(pMCTstat, pDCTstat, 1); - set_2t_configuration(pMCTstat, pDCTstat, 1); - mct_BeforePlatformSpec(pMCTstat, pDCTstat, 1); - mct_PlatformSpec(pMCTstat, pDCTstat, 1); - } - } - - /* Program F2x[1, 0]94[MemClkFreqVal] = 1. */ - if (DCT0Present) { - dword = Get_NB32_DCT(pDCTstat->dev_dct, 0, 0x94); - dword |= 1 << MemClkFreqVal; - Set_NB32_DCT(pDCTstat->dev_dct, 0, 0x94, dword); - } - if (DCT1Present) { - dword = Get_NB32_DCT(pDCTstat->dev_dct, 1, 0x94); - dword |= 1 << MemClkFreqVal; - Set_NB32_DCT(pDCTstat->dev_dct, 1, 0x94, dword); - } - - /* Wait until F2x[1, 0]94[FreqChgInProg]=0. */ - if (DCT0Present) - do { - dword = Get_NB32_DCT(pDCTstat->dev_dct, 0, 0x94); - } while (dword & (1 << FreqChgInProg)); - if (DCT1Present) - do { - dword = Get_NB32_DCT(pDCTstat->dev_dct, 1, 0x94); - } while (dword & (1 << FreqChgInProg)); - - if (is_fam15h()) { - /* Program D18F2x9C_x0D0F_E006_dct[1:0][PllLockTime] = 0xf */ - if (DCT0Present) { - dword = Get_NB32_index_wait_DCT(pDCTstat->dev_dct, 0, 0x98, 0x0d0fe006); - dword &= ~(0x0000ffff); - dword |= 0x0000000f; - Set_NB32_index_wait_DCT(pDCTstat->dev_dct, 0, 0x98, 0x0d0fe006, dword); - } - if (DCT1Present) { - dword = Get_NB32_index_wait_DCT(pDCTstat->dev_dct, 1, 0x98, 0x0d0fe006); - dword &= ~(0x0000ffff); - dword |= 0x0000000f; - Set_NB32_index_wait_DCT(pDCTstat->dev_dct, 1, 0x98, 0x0d0fe006, dword); - } - } else { - /* Program F2x[1, 0]9C[DisAutoComp] = 0. */ - if (DCT0Present) { - dword = Get_NB32_index_wait_DCT(pDCTstat->dev_dct, 0, 0x98, 8); - dword &= ~(1 << DisAutoComp); - Set_NB32_index_wait_DCT(pDCTstat->dev_dct, 0, 0x98, 8, dword); - mct_Wait(15000); /* Wait for 750us */ - } - if (DCT1Present) { - dword = Get_NB32_index_wait_DCT(pDCTstat->dev_dct, 1, 0x98, 8); - dword &= ~(1 << DisAutoComp); - Set_NB32_index_wait_DCT(pDCTstat->dev_dct, 1, 0x98, 8, dword); - mct_Wait(15000); /* Wait for 750us */ - } - } - - printk(BIOS_DEBUG, "%s: Done\n", __func__); -} - -/* - * the DRAM controller to bring the DRAMs out of self refresh mode. - */ -static void ExitSelfRefresh(struct MCTStatStruc *pMCTstat, - struct DCTStatStruc *pDCTstat) -{ - u8 DCT0Present, DCT1Present; - u32 val; - - DCT0Present = pDCTstat->DIMMValidDCT[0]; - if (pDCTstat->GangedMode) - DCT1Present = 0; - else - DCT1Present = pDCTstat->DIMMValidDCT[1]; - - /* Program F2x[1, 0]90[ExitSelfRef]=1 for both DCTs. */ - if (DCT0Present) { - val = Get_NB32_DCT(pDCTstat->dev_dct, 0, 0x90); - val |= 1 << ExitSelfRef; - Set_NB32_DCT(pDCTstat->dev_dct, 0, 0x90, val); - } - if (DCT1Present) { - val = Get_NB32_DCT(pDCTstat->dev_dct, 1, 0x90); - val |= 1 << ExitSelfRef; - Set_NB32_DCT(pDCTstat->dev_dct, 1, 0x90, val); - } - /* Wait until the hardware resets F2x[1, 0]90[ExitSelfRef]=0. */ - if (DCT0Present) - do { - val = Get_NB32_DCT(pDCTstat->dev_dct, 0, 0x90); - } while (val & (1 << ExitSelfRef)); - if (DCT1Present) - do { - val = Get_NB32_DCT(pDCTstat->dev_dct, 1, 0x90); - } while (val & (1 << ExitSelfRef)); -} - -void SetTargetFreq(struct MCTStatStruc *pMCTstat, - struct DCTStatStruc *pDCTstatA, uint8_t Node) -{ - uint32_t dword; - uint8_t package_type = mctGet_NVbits(NV_PACK_TYPE); - - printk(BIOS_DEBUG, "%s: Start\n", __func__); - - struct DCTStatStruc *pDCTstat; - pDCTstat = pDCTstatA + Node; - - printk(BIOS_DEBUG, "%s: Node %d: New frequency code: %04x\n", __func__, Node, pDCTstat->TargetFreq); - - if (is_fam15h()) { - /* Program F2x[1, 0]90[DisDllShutDownSR]=1. */ - if (pDCTstat->DIMMValidDCT[0]) { - dword = Get_NB32_DCT(pDCTstat->dev_dct, 0, 0x90); - dword |= (0x1 << 27); - Set_NB32_DCT(pDCTstat->dev_dct, 0, 0x90, dword); - } - if (pDCTstat->DIMMValidDCT[1]) { - dword = Get_NB32_DCT(pDCTstat->dev_dct, 1, 0x90); - dword |= (0x1 << 27); - Set_NB32_DCT(pDCTstat->dev_dct, 1, 0x90, dword); - } - } - - /* Program F2x[1,0]90[EnterSelfRefresh]=1. - * Wait until the hardware resets F2x[1,0]90[EnterSelfRefresh]=0. - */ - EnterSelfRefresh(pMCTstat, pDCTstat); - - /* - * Program F2x[1,0]9C_x08[DisAutoComp]=1 - * Program F2x[1,0]94[MemClkFreqVal] = 0. - * Program F2x[1,0]94[MemClkFreq] to specify the target MEMCLK frequency. - * Program F2x[1,0]94[MemClkFreqVal] = 1. - * Wait until F2x[1,0]94[FreqChgInProg]=0. - * Program F2x[1,0]9C_x08[DisAutoComp]=0 - */ - ChangeMemClk(pMCTstat, pDCTstat); - - if (is_fam15h()) { - uint8_t dct; - for (dct = 0; dct < 2; dct++) { - if (pDCTstat->DIMMValidDCT[dct]) { - phyAssistedMemFnceTraining(pMCTstat, pDCTstatA, Node); - InitPhyCompensation(pMCTstat, pDCTstat, dct); - } - } - } - - /* Program F2x[1,0]90[ExitSelfRef]=1 for both DCTs. - * Wait until the hardware resets F2x[1, 0]90[ExitSelfRef]=0. - */ - ExitSelfRefresh(pMCTstat, pDCTstat); - - if (is_fam15h()) { - if ((package_type == PT_C3) || (package_type == PT_GR)) { - /* Socket C32 or G34 */ - /* Program F2x[1, 0]90[DisDllShutDownSR]=0. */ - if (pDCTstat->DIMMValidDCT[0]) { - dword = Get_NB32_DCT(pDCTstat->dev_dct, 0, 0x90); - dword &= ~(0x1 << 27); - Set_NB32_DCT(pDCTstat->dev_dct, 0, 0x90, dword); - } - if (pDCTstat->DIMMValidDCT[1]) { - dword = Get_NB32_DCT(pDCTstat->dev_dct, 1, 0x90); - dword &= ~(0x1 << 27); - Set_NB32_DCT(pDCTstat->dev_dct, 1, 0x90, dword); - } - } - } - - /* wait for 500 MCLKs after ExitSelfRef, 500*2.5ns = 1250ns */ - mct_Wait(250); - - if (pDCTstat->Status & (1 << SB_Registered)) { - u8 DCT0Present, DCT1Present; - - DCT0Present = pDCTstat->DIMMValidDCT[0]; - if (pDCTstat->GangedMode) - DCT1Present = 0; - else - DCT1Present = pDCTstat->DIMMValidDCT[1]; - - if (!DCT1Present) - pDCTstat->CSPresent = pDCTstat->CSPresent_DCT[0]; - else if (pDCTstat->GangedMode) - pDCTstat->CSPresent = 0; - else - pDCTstat->CSPresent = pDCTstat->CSPresent_DCT[1]; - - if (pDCTstat->DIMMValidDCT[0]) { - FreqChgCtrlWrd(pMCTstat, pDCTstat, 0); - } - if (pDCTstat->DIMMValidDCT[1]) { - FreqChgCtrlWrd(pMCTstat, pDCTstat, 1); - } - } - - printk(BIOS_DEBUG, "%s: Done\n", __func__); -} - -static void Modify_OnDimmMirror(struct DCTStatStruc *pDCTstat, u8 dct, u8 set) -{ - u32 val; - u32 reg = 0x44; - while (reg < 0x60) { - val = Get_NB32_DCT(pDCTstat->dev_dct, dct, reg); - if (val & (1 << CSEnable)) - set ? (val |= 1 << onDimmMirror) : (val &= ~(1<dev_dct, dct, reg, val); - reg += 8; - } -} - -void Restore_OnDimmMirror(struct MCTStatStruc *pMCTstat, - struct DCTStatStruc *pDCTstat) -{ - if (pDCTstat->LogicalCPUID & (AMD_DR_Bx /* | AMD_RB_C0 */)) { /* We dont support RB-C0 now */ - if (pDCTstat->MirrPresU_NumRegR & 0x55) - Modify_OnDimmMirror(pDCTstat, 0, 1); /* dct = 0, set */ - if (pDCTstat->MirrPresU_NumRegR & 0xAA) - Modify_OnDimmMirror(pDCTstat, 1, 1); /* dct = 1, set */ - } -} -void Clear_OnDimmMirror(struct MCTStatStruc *pMCTstat, - struct DCTStatStruc *pDCTstat) -{ - if (pDCTstat->LogicalCPUID & (AMD_DR_Bx /* | AMD_RB_C0 */)) { /* We dont support RB-C0 now */ - if (pDCTstat->MirrPresU_NumRegR & 0x55) - Modify_OnDimmMirror(pDCTstat, 0, 0); /* dct = 0, clear */ - if (pDCTstat->MirrPresU_NumRegR & 0xAA) - Modify_OnDimmMirror(pDCTstat, 1, 0); /* dct = 1, clear */ - } -} diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mhwlc_d.c b/src/northbridge/amd/amdmct/mct_ddr3/mhwlc_d.c deleted file mode 100644 index 353aa7a1cf..0000000000 --- a/src/northbridge/amd/amdmct/mct_ddr3/mhwlc_d.c +++ /dev/null @@ -1,1519 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2010 Advanced Micro Devices, Inc. - * Copyright (C) 2015 - 2016 Raptor Engineering, LLC - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include -#include - -#include "mct_d.h" -#include "mct_d_gcc.h" -#include "mwlc_d.h" - -u32 swapAddrBits_wl(struct DCTStatStruc *pDCTstat, uint8_t dct, uint32_t MRSValue); -u32 swapBankBits(struct DCTStatStruc *pDCTstat, uint8_t dct, uint32_t MRSValue); -void prepareDimms(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstat, - u8 dct, u8 dimm, BOOL wl); -void programODT(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstat, uint8_t dct, u8 dimm); -void procConfig(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstat, uint8_t dct, uint8_t dimm, uint8_t pass, uint8_t nibble); -void setWLByteDelay(struct DCTStatStruc *pDCTstat, uint8_t dct, u8 ByteLane, u8 dimm, u8 targetAddr, uint8_t pass, uint8_t lane_count); -void getWLByteDelay(struct DCTStatStruc *pDCTstat, uint8_t dct, u8 ByteLane, u8 dimm, uint8_t pass, uint8_t nibble, uint8_t lane_count); - -#define MAX_LANE_COUNT 9 - -/*----------------------------------------------------------------------------- - * uint8_t AgesaHwWlPhase1(SPDStruct *SPDData,MCTStruct *MCTData, DCTStruct *DCTData, - * u8 Dimm, u8 Pass) - * - * Description: - * This function initialized Hardware based write levelization phase 1 - * - * Parameters: - * IN OUT *SPDData - Pointer to buffer with information about each DIMMs - * SPD information - * *MCTData - Pointer to buffer with runtime parameters, - * *DCTData - Pointer to buffer with information about each DCT - * - * IN DIMM - Logical DIMM number - * Pass - First or Second Pass - * OUT - *----------------------------------------------------------------------------- - */ -uint8_t AgesaHwWlPhase1(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstat, - u8 dct, u8 dimm, u8 pass) -{ - u8 ByteLane; - u32 Value, Addr; - uint8_t nibble = 0; - uint8_t train_both_nibbles; - u16 Addl_Data_Offset, Addl_Data_Port; - sMCTStruct *pMCTData = pDCTstat->C_MCTPtr; - sDCTStruct *pDCTData = pDCTstat->C_DCTPtr[dct]; - uint8_t lane_count; - - lane_count = get_available_lane_count(pMCTstat, pDCTstat); - - pDCTData->WLPass = pass; - /* 1. Specify the target DIMM that is to be trained by programming - * F2x[1, 0]9C_x08[TrDimmSel]. - */ - set_DCT_ADDR_Bits(pDCTData, dct, pDCTData->NodeId, FUN_DCT, - DRAM_ADD_DCT_PHY_CONTROL_REG, TrDimmSelStart, - TrDimmSelEnd, (u32)dimm); - - train_both_nibbles = 0; - if (pDCTstat->Dimmx4Present) - if (is_fam15h()) - train_both_nibbles = 1; - - for (nibble = 0; nibble < (train_both_nibbles + 1); nibble++) { - printk(BIOS_SPEW, "AgesaHwWlPhase1: training nibble %d\n", nibble); - - if (is_fam15h()) { - /* Program F2x[1, 0]9C_x08[WrtLvTrEn]=0 */ - set_DCT_ADDR_Bits(pDCTData, dct, pDCTData->NodeId, FUN_DCT, - DRAM_ADD_DCT_PHY_CONTROL_REG, WrtLvTrEn, WrtLvTrEn, 0); - - /* Set TrNibbleSel */ - set_DCT_ADDR_Bits(pDCTData, dct, pDCTData->NodeId, FUN_DCT, - DRAM_ADD_DCT_PHY_CONTROL_REG, 2, - 2, (uint32_t)nibble); - } - - /* 2. Prepare the DIMMs for write levelization using DDR3-defined - * MR commands. */ - prepareDimms(pMCTstat, pDCTstat, dct, dimm, TRUE); - - /* 3. After the DIMMs are configured, BIOS waits 40 MEMCLKs to - * satisfy DDR3-defined internal DRAM timing. - */ - if (is_fam15h()) - precise_memclk_delay_fam15(pMCTstat, pDCTstat, dct, 40); - else - pMCTData->AgesaDelay(40); - - /* 4. Configure the processor's DDR phy for write levelization training: */ - procConfig(pMCTstat, pDCTstat, dct, dimm, pass, nibble); - - /* 5. Begin write levelization training: - * Program F2x[1, 0]9C_x08[WrtLvTrEn]=1. */ - if (pDCTData->LogicalCPUID & (AMD_DR_Cx | AMD_DR_Dx | AMD_FAM15_ALL)) - { - set_DCT_ADDR_Bits(pDCTData, dct, pDCTData->NodeId, FUN_DCT, - DRAM_ADD_DCT_PHY_CONTROL_REG, WrtLvTrEn, WrtLvTrEn, 1); - } - else - { - /* Broadcast write to all D3Dbyte chipset register offset 0xc - * Set bit 0 (wrTrain) - * Program bit 4 to nibble being trained (only matters for x4dimms) - * retain value of 3:2 (Trdimmsel) - * reset bit 5 (FrzPR) - */ - if (dct) - { - Addl_Data_Offset = 0x198; - Addl_Data_Port = 0x19C; - } - else - { - Addl_Data_Offset = 0x98; - Addl_Data_Port = 0x9C; - } - Addr = 0x0D00000C; - AmdMemPCIWriteBits(MAKE_SBDFO(0,0,24+(pDCTData->NodeId),FUN_DCT,Addl_Data_Offset), 31, 0, &Addr); - while ((get_Bits(pDCTData,FUN_DCT,pDCTData->NodeId, FUN_DCT, Addl_Data_Offset, - DctAccessDone, DctAccessDone)) == 0); - AmdMemPCIReadBits(MAKE_SBDFO(0,0,24+(pDCTData->NodeId),FUN_DCT,Addl_Data_Port), 31, 0, &Value); - Value = bitTestSet(Value, 0); /* enable WL training */ - Value = bitTestReset(Value, 4); /* for x8 only */ - Value = bitTestReset(Value, 5); /* for hardware WL training */ - AmdMemPCIWriteBits(MAKE_SBDFO(0,0,24+(pDCTData->NodeId),FUN_DCT,Addl_Data_Port), 31, 0, &Value); - Addr = 0x4D030F0C; - AmdMemPCIWriteBits(MAKE_SBDFO(0,0,24+(pDCTData->NodeId),FUN_DCT,Addl_Data_Offset), 31, 0, &Addr); - while ((get_Bits(pDCTData,FUN_DCT,pDCTData->NodeId, FUN_DCT, Addl_Data_Offset, - DctAccessDone, DctAccessDone)) == 0); - } - - if (is_fam15h()) - proc_MFENCE(); - - /* Wait 200 MEMCLKs. If executing pass 2, wait 32 MEMCLKs. */ - if (is_fam15h()) - precise_memclk_delay_fam15(pMCTstat, pDCTstat, dct, 200); - else - pMCTData->AgesaDelay(140); - - /* Program F2x[1, 0]9C_x08[WrtLevelTrEn]=0. */ - set_DCT_ADDR_Bits(pDCTData, dct, pDCTData->NodeId, FUN_DCT, - DRAM_ADD_DCT_PHY_CONTROL_REG, WrtLvTrEn, WrtLvTrEn, 0); - - /* Read from registers F2x[1, 0]9C_x[51:50] and F2x[1, 0]9C_x52 - * to get the gross and fine delay settings - * for the target DIMM and save these values. */ - for (ByteLane = 0; ByteLane < lane_count; ByteLane++) { - getWLByteDelay(pDCTstat, dct, ByteLane, dimm, pass, nibble, lane_count); - } - - pDCTData->WLCriticalGrossDelayPrevPass = 0x0; - - /* Exit nibble training if current DIMM is not x4 */ - if ((pDCTstat->Dimmx4Present & (1 << (dimm + dct))) == 0) - break; - } - - return 0; -} - -uint8_t AgesaHwWlPhase2(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstat, - uint8_t dct, uint8_t dimm, uint8_t pass) -{ - u8 ByteLane; - uint8_t status = 0; - sDCTStruct *pDCTData = pDCTstat->C_DCTPtr[dct]; - uint8_t lane_count; - - lane_count = get_available_lane_count(pMCTstat, pDCTstat); - - assert(lane_count <= MAX_LANE_COUNT); - - if (is_fam15h()) { - int32_t gross_diff[MAX_LANE_COUNT]; - int32_t cgd = pDCTData->WLCriticalGrossDelayPrevPass; - uint8_t index = (uint8_t)(lane_count * dimm); - - printk(BIOS_SPEW, "\toriginal critical gross delay: %d\n", cgd); - - /* FIXME - * For now, disable CGD adjustment as it seems to interfere with registered DIMM training - */ - - /* Calculate the Critical Gross Delay */ - for (ByteLane = 0; ByteLane < lane_count; ByteLane++) { - /* Calculate the gross delay differential for this lane */ - gross_diff[ByteLane] = pDCTData->WLSeedGrossDelay[index+ByteLane] + pDCTData->WLGrossDelay[index+ByteLane]; - gross_diff[ByteLane] -= pDCTData->WLSeedPreGrossDelay[index+ByteLane]; - - /* WrDqDqsEarly values greater than 2 are reserved */ - if (gross_diff[ByteLane] < -2) - gross_diff[ByteLane] = -2; - - /* Update the Critical Gross Delay */ - if (gross_diff[ByteLane] < cgd) - cgd = gross_diff[ByteLane]; - } - - printk(BIOS_SPEW, "\tnew critical gross delay: %d\n", cgd); - - pDCTData->WLCriticalGrossDelayPrevPass = cgd; - - if (pDCTstat->Speed != pDCTstat->TargetFreq) { - /* FIXME - * Using the Pass 1 training values causes major phy training problems on - * all Family 15h processors I tested (Pass 1 values are randomly too high, - * and Pass 2 cannot lock). - * Figure out why this is and fix it, then remove the bypass code below... - */ - if (pass == FirstPass) { - for (ByteLane = 0; ByteLane < lane_count; ByteLane++) { - pDCTData->WLGrossDelay[index+ByteLane] = pDCTData->WLSeedGrossDelay[index+ByteLane]; - pDCTData->WLFineDelay[index+ByteLane] = pDCTData->WLSeedFineDelay[index+ByteLane]; - } - return 0; - } - } - - /* Compensate for occasional noise/instability causing sporadic training failure */ - for (ByteLane = 0; ByteLane < lane_count; ByteLane++) { - uint8_t faulty_value_detected = 0; - uint16_t total_delay_seed = ((pDCTData->WLSeedGrossDelay[index+ByteLane] & 0x1f) << 5) | (pDCTData->WLSeedFineDelay[index+ByteLane] & 0x1f); - uint16_t total_delay_phy = ((pDCTData->WLGrossDelay[index+ByteLane] & 0x1f) << 5) | (pDCTData->WLFineDelay[index+ByteLane] & 0x1f); - if (pass == FirstPass) { - /* Allow a somewhat higher step threshold on the first pass - * For the most part, as long as the phy isn't stepping - * several clocks at once the values are probably valid. - */ - if (abs(total_delay_phy - total_delay_seed) > 0x30) - faulty_value_detected = 1; - } else { - /* Stepping memory clocks between adjacent allowed frequencies - * should not yield large phy value differences... - */ - - if (abs(total_delay_phy - total_delay_seed) > 0x20) - faulty_value_detected = 1; - } - if (faulty_value_detected) { - printk(BIOS_INFO, "%s: overriding faulty phy value (seed: %04x phy: %04x step: %04x)\n", __func__, - total_delay_seed, total_delay_phy, abs(total_delay_phy - total_delay_seed)); - pDCTData->WLGrossDelay[index+ByteLane] = pDCTData->WLSeedGrossDelay[index+ByteLane]; - pDCTData->WLFineDelay[index+ByteLane] = pDCTData->WLSeedFineDelay[index+ByteLane]; - status = 1; - } - } - } - - return status; -} - -uint8_t AgesaHwWlPhase3(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstat, - u8 dct, u8 dimm, u8 pass) -{ - u8 ByteLane; - sMCTStruct *pMCTData = pDCTstat->C_MCTPtr; - sDCTStruct *pDCTData = pDCTstat->C_DCTPtr[dct]; - uint8_t lane_count; - - lane_count = get_available_lane_count(pMCTstat, pDCTstat); - - assert(lane_count <= MAX_LANE_COUNT); - - if (is_fam15h()) { - uint32_t dword; - int32_t gross_diff[MAX_LANE_COUNT]; - int32_t cgd = pDCTData->WLCriticalGrossDelayPrevPass; - uint8_t index = (uint8_t)(lane_count * dimm); - - /* Apply offset(s) if needed */ - if (cgd < 0) { - dword = Get_NB32_DCT(pDCTstat->dev_dct, dct, 0xa8); - dword &= ~(0x3 << 24); /* WrDqDqsEarly = abs(cgd) */ - dword |= ((abs(cgd) & 0x3) << 24); - Set_NB32_DCT(pDCTstat->dev_dct, dct, 0xa8, dword); - - for (ByteLane = 0; ByteLane < lane_count; ByteLane++) { - /* Calculate the gross delay differential for this lane */ - gross_diff[ByteLane] = pDCTData->WLSeedGrossDelay[index+ByteLane] + pDCTData->WLGrossDelay[index+ByteLane]; - gross_diff[ByteLane] -= pDCTData->WLSeedPreGrossDelay[index+ByteLane]; - - /* Prevent underflow in the presence of noise / instability */ - if (gross_diff[ByteLane] < cgd) - gross_diff[ByteLane] = cgd; - - pDCTData->WLGrossDelay[index+ByteLane] = (gross_diff[ByteLane] + (abs(cgd) & 0x3)); - } - } else { - dword = Get_NB32_DCT(pDCTstat->dev_dct, dct, 0xa8); - dword &= ~(0x3 << 24); /* WrDqDqsEarly = pDCTData->WrDqsGrossDlyBaseOffset */ - dword |= ((pDCTData->WrDqsGrossDlyBaseOffset & 0x3) << 24); - Set_NB32_DCT(pDCTstat->dev_dct, dct, 0xa8, dword); - } - } - - /* Write the adjusted gross and fine delay settings - * to the target DIMM. */ - for (ByteLane = 0; ByteLane < lane_count; ByteLane++) { - setWLByteDelay(pDCTstat, dct, ByteLane, dimm, 1, pass, lane_count); - } - - /* 6. Configure DRAM Phy Control Register so that the phy stops driving - * write levelization ODT. */ - set_DCT_ADDR_Bits(pDCTData, dct, pDCTData->NodeId, FUN_DCT, - DRAM_ADD_DCT_PHY_CONTROL_REG, WrLvOdtEn, WrLvOdtEn, 0); - - if (is_fam15h()) - proc_MFENCE(); - - /* Wait 10 MEMCLKs to allow for ODT signal settling. */ - if (is_fam15h()) - precise_memclk_delay_fam15(pMCTstat, pDCTstat, dct, 10); - else - pMCTData->AgesaDelay(10); - - /* 7. Program the target DIMM back to normal operation by configuring - * the following (See section 2.8.5.4.1.1 - * [Phy Assisted Write Levelization] on page 97 pass 1, step #2): - * Configure all ranks of the target DIMM for normal operation. - * Enable the output drivers of all ranks of the target DIMM. - * For a two DIMM system, program the Rtt value for the target DIMM - * to the normal operating termination: - */ - prepareDimms(pMCTstat, pDCTstat, dct, dimm, FALSE); - - return 0; -} - -/*---------------------------------------------------------------------------- - * LOCAL FUNCTIONS - * - *---------------------------------------------------------------------------- - */ - -/*----------------------------------------------------------------------------- - * u32 swapAddrBits_wl(struct DCTStatStruc *pDCTstat, uint8_t dct, u32 MRSValue) - * - * Description: - * This function swaps the bits in MSR register value - * - * Parameters: - * IN OUT *DCTData - Pointer to buffer with information about each DCT - * IN u32: MRS value - * OUT u32: Swapped BANK BITS - * - * ---------------------------------------------------------------------------- - */ -u32 swapAddrBits_wl(struct DCTStatStruc *pDCTstat, uint8_t dct, uint32_t MRSValue) -{ - sDCTStruct *pDCTData = pDCTstat->C_DCTPtr[dct]; - u32 tempW, tempW1; - - if (is_fam15h()) - tempW1 = get_Bits(pDCTData, dct, pDCTData->NodeId, - FUN_DCT, DRAM_INIT, MrsChipSelStartFam15, MrsChipSelEndFam15); - else - tempW1 = get_Bits(pDCTData, dct, pDCTData->NodeId, - FUN_DCT, DRAM_INIT, MrsChipSelStartFam10, MrsChipSelEndFam10); - if (tempW1 & 1) - { - if ((pDCTData->Status[DCT_STATUS_OnDimmMirror])) - { - /* swap A3/A4,A5/A6,A7/A8 */ - tempW = MRSValue; - tempW1 = MRSValue; - tempW &= 0x0A8; - tempW1 &= 0x0150; - MRSValue &= 0xFE07; - MRSValue |= (tempW << 1); - MRSValue |= (tempW1 >> 1); - } - } - return MRSValue; -} - -/*----------------------------------------------------------------------------- - * u32 swapBankBits(struct DCTStatStruc *pDCTstat, uint8_t dct, u32 MRSValue) - * - * Description: - * This function swaps the bits in MSR register value - * - * Parameters: - * IN OUT *DCTData - Pointer to buffer with information about each DCT - * IN u32: MRS value - * OUT u32: Swapped BANK BITS - * - * ---------------------------------------------------------------------------- - */ -u32 swapBankBits(struct DCTStatStruc *pDCTstat, uint8_t dct, u32 MRSValue) -{ - sDCTStruct *pDCTData = pDCTstat->C_DCTPtr[dct]; - u32 tempW, tempW1; - - if (is_fam15h()) - tempW1 = get_Bits(pDCTData, dct, pDCTData->NodeId, - FUN_DCT, DRAM_INIT, MrsChipSelStartFam15, MrsChipSelEndFam15); - else - tempW1 = get_Bits(pDCTData, dct, pDCTData->NodeId, - FUN_DCT, DRAM_INIT, MrsChipSelStartFam10, MrsChipSelEndFam10); - if (tempW1 & 1) - { - if ((pDCTData->Status[DCT_STATUS_OnDimmMirror])) - { - /* swap BA0/BA1 */ - tempW = MRSValue; - tempW1 = MRSValue; - tempW &= 0x01; - tempW1 &= 0x02; - MRSValue = 0; - MRSValue |= (tempW << 1); - MRSValue |= (tempW1 >> 1); - } - } - return MRSValue; -} - -static uint16_t unbuffered_dimm_nominal_termination_emrs(uint8_t number_of_dimms, uint8_t frequency_index, uint8_t rank_count, uint8_t rank) -{ - uint16_t term; - - uint8_t MaxDimmsInstallable = mctGet_NVbits(NV_MAX_DIMMS_PER_CH); - - if (number_of_dimms == 1) { - if (MaxDimmsInstallable < 3) { - term = 0x04; /* Rtt_Nom = RZQ/4 = 60 Ohm */ - } else { - if (rank_count == 1) { - term = 0x04; /* Rtt_Nom = RZQ/4 = 60 Ohm */ - } else { - if (rank == 0) - term = 0x04; /* Rtt_Nom = RZQ/4 = 60 Ohm */ - else - term = 0x00; /* Rtt_Nom = OFF */ - } - } - } else { - if (frequency_index < 5) - term = 0x0044; /* Rtt_Nom = RZQ/6 = 40 Ohm */ - else - term = 0x0204; /* Rtt_Nom = RZQ/8 = 30 Ohm */ - } - - return term; -} - -static uint16_t unbuffered_dimm_dynamic_termination_emrs(uint8_t number_of_dimms, uint8_t frequency_index, uint8_t rank_count) -{ - uint16_t term; - - uint8_t MaxDimmsInstallable = mctGet_NVbits(NV_MAX_DIMMS_PER_CH); - - if (number_of_dimms == 1) { - if (MaxDimmsInstallable < 3) { - term = 0x00; /* Rtt_WR = off */ - } else { - if (rank_count == 1) - term = 0x00; /* Rtt_WR = off */ - else - term = 0x200; /* Rtt_WR = RZQ/4 = 60 Ohm */ - } - } else { - term = 0x400; /* Rtt_WR = RZQ/2 = 120 Ohm */ - } - - return term; -} - -/*----------------------------------------------------------------------------- - * void prepareDimms(sMCTStruct *pMCTData, sDCTStruct *DCTData, u8 Dimm, BOOL WL) - * - * Description: - * This function prepares DIMMS for training - * Fam10h: BKDG Rev. 3.62 section 2.8.9.9.1 - * Fam15h: BKDG Rev. 3.14 section 2.10.5.8.1 - * ---------------------------------------------------------------------------- - */ -void prepareDimms(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstat, - u8 dct, u8 dimm, BOOL wl) -{ - u32 tempW, tempW1, tempW2, MrsBank; - u8 rank, currDimm, MemClkFreq; - sMCTStruct *pMCTData = pDCTstat->C_MCTPtr; - sDCTStruct *pDCTData = pDCTstat->C_DCTPtr[dct]; - uint8_t package_type = mctGet_NVbits(NV_PACK_TYPE); - uint8_t number_of_dimms = pDCTData->MaxDimmsInstalled; - - if (is_fam15h()) { - MemClkFreq = get_Bits(pDCTData, dct, pDCTData->NodeId, - FUN_DCT, DRAM_CONFIG_HIGH, 0, 4); - } else { - MemClkFreq = get_Bits(pDCTData, dct, pDCTData->NodeId, - FUN_DCT, DRAM_CONFIG_HIGH, 0, 2); - } - /* Configure the DCT to send initialization MR commands to the target DIMM - * by programming the F2x[1,0]7C register using the following steps. - */ - rank = 0; - while ((rank < pDCTData->DimmRanks[dimm]) && (rank < 2)) - { - /* Program F2x[1, 0]7C[MrsChipSel[2:0]] for the current rank to be trained. */ - if (is_fam15h()) - set_Bits(pDCTData, dct, pDCTData->NodeId, FUN_DCT, - DRAM_INIT, MrsChipSelStartFam15, MrsChipSelEndFam15, dimm*2+rank); - else - set_Bits(pDCTData, dct, pDCTData->NodeId, FUN_DCT, - DRAM_INIT, MrsChipSelStartFam10, MrsChipSelEndFam10, dimm*2+rank); - - /* Program F2x[1, 0]7C[MrsBank[2:0]] for the appropriate internal DRAM - * register that defines the required DDR3-defined function for write - * levelization. - */ - MrsBank = swapBankBits(pDCTstat, dct, 1); - if (is_fam15h()) - set_Bits(pDCTData, dct, pDCTData->NodeId, FUN_DCT, - DRAM_INIT, MrsBankStartFam15, MrsBankEndFam15, MrsBank); - else - set_Bits(pDCTData, dct, pDCTData->NodeId, FUN_DCT, - DRAM_INIT, MrsBankStartFam10, MrsBankEndFam10, MrsBank); - - /* Program F2x[1, 0]7C[MrsAddress[15:0]] to the required DDR3-defined function - * for write levelization. - */ - tempW = 0;/* DLL_DIS = 0, DIC = 0, AL = 0, TDQS = 0 */ - - /* Retrieve normal settings of the MRS control word and clear Rtt_Nom */ - if (is_fam15h()) { - tempW = mct_MR1(pMCTstat, pDCTstat, dct, dimm*2+rank) & 0xffff; - tempW &= ~(0x0244); - } else { - /* Set TDQS = 1b for x8 DIMM, TDQS = 0b for x4 DIMM, when mixed x8 & x4 */ - tempW2 = get_Bits(pDCTData, dct, pDCTData->NodeId, - FUN_DCT, DRAM_CONFIG_HIGH, RDqsEn, RDqsEn); - if (tempW2) - { - if (pDCTData->DimmX8Present[dimm]) - tempW |= 0x800; - } - } - - /* determine Rtt_Nom for WL & Normal mode */ - if (is_fam15h()) { - if (wl) { - if (number_of_dimms > 1) { - if (rank == 0) { - /* Get Rtt_WR for the current DIMM and rank */ - tempW2 = fam15_rttwr(pDCTstat, dct, dimm, rank, package_type); - } else { - tempW2 = fam15_rttnom(pDCTstat, dct, dimm, rank, package_type); - } - } else { - tempW2 = fam15_rttnom(pDCTstat, dct, dimm, rank, package_type); - } - } else { - tempW2 = fam15_rttnom(pDCTstat, dct, dimm, rank, package_type); - } - tempW1 = 0; - tempW1 |= ((tempW2 & 0x4) >> 2) << 9; - tempW1 |= ((tempW2 & 0x2) >> 1) << 6; - tempW1 |= ((tempW2 & 0x1) >> 0) << 2; - } else { - if (pDCTData->Status[DCT_STATUS_REGISTERED]) { - tempW1 = RttNomTargetRegDimm(pMCTData, pDCTData, dimm, wl, MemClkFreq, rank); - } else { - if (wl) { - if (number_of_dimms > 1) { - if (rank == 0) { - /* Get Rtt_WR for the current DIMM and rank */ - uint16_t dynamic_term = unbuffered_dimm_dynamic_termination_emrs(pDCTData->MaxDimmsInstalled, MemClkFreq, pDCTData->DimmRanks[dimm]); - - /* Convert dynamic termination code to corresponding nominal termination code */ - if (dynamic_term == 0x200) - tempW1 = 0x04; - else if (dynamic_term == 0x400) - tempW1 = 0x40; - else - tempW1 = 0x0; - } else { - tempW1 = unbuffered_dimm_nominal_termination_emrs(pDCTData->MaxDimmsInstalled, MemClkFreq, pDCTData->DimmRanks[dimm], rank); - } - } else { - tempW1 = unbuffered_dimm_nominal_termination_emrs(pDCTData->MaxDimmsInstalled, MemClkFreq, pDCTData->DimmRanks[dimm], rank); - } - } else { - tempW1 = unbuffered_dimm_nominal_termination_emrs(pDCTData->MaxDimmsInstalled, MemClkFreq, pDCTData->DimmRanks[dimm], rank); - } - } - } - - /* Apply Rtt_Nom to the MRS control word */ - tempW = tempW|tempW1; - - /* All ranks of the target DIMM are set to write levelization mode. */ - if (wl) - { - tempW1 = bitTestSet(tempW, MRS_Level); - if (rank == 0) - { - /* Enable the output driver of the first rank of the target DIMM. */ - tempW = tempW1; - } - else - { - /* Disable the output drivers of all other ranks for - * the target DIMM. - */ - tempW = bitTestSet(tempW1, Qoff); - } - } - - /* Program MrsAddress[5,1]=output driver impedance control (DIC) */ - if (is_fam15h()) { - tempW1 = fam15_dimm_dic(pDCTstat, dct, dimm, rank, package_type); - } else { - /* Read DIC from F2x[1,0]84[DrvImpCtrl] */ - tempW1 = get_Bits(pDCTData, dct, pDCTData->NodeId, - FUN_DCT, DRAM_MRS_REGISTER, DrvImpCtrlStart, DrvImpCtrlEnd); - } - - /* Apply DIC to the MRS control word */ - if (bitTest(tempW1, 1)) - tempW = bitTestSet(tempW, 5); - if (bitTest(tempW1, 0)) - tempW = bitTestSet(tempW, 1); - - tempW = swapAddrBits_wl(pDCTstat, dct, tempW); - - if (is_fam15h()) - set_Bits(pDCTData, dct, pDCTData->NodeId, FUN_DCT, - DRAM_INIT, MrsAddressStartFam15, MrsAddressEndFam15, tempW); - else - set_Bits(pDCTData, dct, pDCTData->NodeId, FUN_DCT, - DRAM_INIT, MrsAddressStartFam10, MrsAddressEndFam10, tempW); - - /* Program F2x[1, 0]7C[SendMrsCmd]=1 to initiate the command to - * the specified DIMM. - */ - set_Bits(pDCTData, dct, pDCTData->NodeId, FUN_DCT, - DRAM_INIT, SendMrsCmd, SendMrsCmd, 1); - /* Wait for F2x[1, 0]7C[SendMrsCmd] to be cleared by hardware. */ - while ((get_Bits(pDCTData, dct, pDCTData->NodeId, - FUN_DCT, DRAM_INIT, SendMrsCmd, SendMrsCmd)) == 0x1) - { - } - - /* Program F2x[1, 0]7C[MrsBank[2:0]] for the appropriate internal DRAM - * register that defines the required DDR3-defined function for Rtt_WR. - */ - MrsBank = swapBankBits(pDCTstat, dct, 2); - if (is_fam15h()) - set_Bits(pDCTData, dct, pDCTData->NodeId, FUN_DCT, - DRAM_INIT, MrsBankStartFam15, MrsBankEndFam15, MrsBank); - else - set_Bits(pDCTData, dct, pDCTData->NodeId, FUN_DCT, - DRAM_INIT, MrsBankStartFam10, MrsBankEndFam10, MrsBank); - - /* Program F2x[1, 0]7C[MrsAddress[15:0]] to the required DDR3-defined function - * for Rtt_WR (DRAMTermDyn). - */ - tempW = 0;/* PASR = 0,*/ - - /* Retrieve normal settings of the MRS control word and clear Rtt_WR */ - if (is_fam15h()) { - tempW = mct_MR2(pMCTstat, pDCTstat, dct, dimm*2+rank) & 0xffff; - tempW &= ~(0x0600); - } else { - /* program MrsAddress[7,6,5:3]=SRT,ASR,CWL, - * based on F2x[1,0]84[19,18,22:20]=,SRT,ASR,Tcwl */ - tempW1 = get_Bits(pDCTData, dct, pDCTData->NodeId, - FUN_DCT, DRAM_MRS_REGISTER, PCI_MIN_LOW, PCI_MAX_HIGH); - if (bitTest(tempW1,19)) - {tempW = bitTestSet(tempW, 7);} - if (bitTest(tempW1,18)) - {tempW = bitTestSet(tempW, 6);} - /* tempW = tempW|(((tempW1 >> 20) & 0x7)<< 3); */ - tempW = tempW|((tempW1&0x00700000) >> 17); - /* workaround for DR-B0 */ - if ((pDCTData->LogicalCPUID & AMD_DR_Bx) && (pDCTData->Status[DCT_STATUS_REGISTERED])) - tempW+=0x8; - } - - /* determine Rtt_WR for WL & Normal mode */ - if (is_fam15h()) { - tempW1 = (fam15_rttwr(pDCTstat, dct, dimm, rank, package_type) << 9); - } else { - if (pDCTData->Status[DCT_STATUS_REGISTERED]) - tempW1 = RttWrRegDimm(pMCTData, pDCTData, dimm, wl, MemClkFreq, rank); - else - tempW1 = unbuffered_dimm_dynamic_termination_emrs(pDCTData->MaxDimmsInstalled, MemClkFreq, pDCTData->DimmRanks[dimm]); - } - - /* Apply Rtt_WR to the MRS control word */ - tempW = tempW|tempW1; - tempW = swapAddrBits_wl(pDCTstat, dct, tempW); - if (is_fam15h()) - set_Bits(pDCTData, dct, pDCTData->NodeId, FUN_DCT, - DRAM_INIT, MrsAddressStartFam15, MrsAddressEndFam15, tempW); - else - set_Bits(pDCTData, dct, pDCTData->NodeId, FUN_DCT, - DRAM_INIT, MrsAddressStartFam10, MrsAddressEndFam10, tempW); - - /* Program F2x[1, 0]7C[SendMrsCmd]=1 to initiate the command to - the specified DIMM.*/ - set_Bits(pDCTData, dct, pDCTData->NodeId, FUN_DCT, - DRAM_INIT, SendMrsCmd, SendMrsCmd, 1); - - /* Wait for F2x[1, 0]7C[SendMrsCmd] to be cleared by hardware. */ - while ((get_Bits(pDCTData, dct, pDCTData->NodeId, - FUN_DCT, DRAM_INIT, SendMrsCmd, SendMrsCmd)) == 0x1) - { - } - - rank++; - } - - /* Configure the non-target DIMM normally. */ - currDimm = 0; - while (currDimm < MAX_LDIMMS) - { - if (pDCTData->DimmPresent[currDimm]) - { - if (currDimm != dimm) - { - rank = 0; - while ((rank < pDCTData->DimmRanks[currDimm]) && (rank < 2)) - { - /* Program F2x[1, 0]7C[MrsChipSel[2:0]] for the current rank - * to be trained. - */ - if (is_fam15h()) - set_Bits(pDCTData, dct, pDCTData->NodeId, - FUN_DCT, DRAM_INIT, MrsChipSelStartFam15, MrsChipSelEndFam15, currDimm*2+rank); - else - set_Bits(pDCTData, dct, pDCTData->NodeId, - FUN_DCT, DRAM_INIT, MrsChipSelStartFam10, MrsChipSelEndFam10, currDimm*2+rank); - - /* Program F2x[1, 0]7C[MrsBank[2:0]] for the appropriate internal - * DRAM register that defines the required DDR3-defined function - * for write levelization. - */ - MrsBank = swapBankBits(pDCTstat, dct, 1); - if (is_fam15h()) - set_Bits(pDCTData, dct, pDCTData->NodeId, - FUN_DCT, DRAM_INIT, MrsBankStartFam15, MrsBankEndFam15, MrsBank); - else - set_Bits(pDCTData, dct, pDCTData->NodeId, - FUN_DCT, DRAM_INIT, MrsBankStartFam10, MrsBankEndFam10, MrsBank); - - /* Program F2x[1, 0]7C[MrsAddress[15:0]] to the required - * DDR3-defined function for write levelization. - */ - tempW = 0;/* DLL_DIS = 0, DIC = 0, AL = 0, TDQS = 0, Level = 0, Qoff = 0 */ - - /* Retrieve normal settings of the MRS control word and clear Rtt_Nom */ - if (is_fam15h()) { - tempW = mct_MR1(pMCTstat, pDCTstat, dct, currDimm*2+rank) & 0xffff; - tempW &= ~(0x0244); - } else { - /* Set TDQS = 1b for x8 DIMM, TDQS = 0b for x4 DIMM, when mixed x8 & x4 */ - tempW2 = get_Bits(pDCTData, dct, pDCTData->NodeId, - FUN_DCT, DRAM_CONFIG_HIGH, RDqsEn, RDqsEn); - if (tempW2) - { - if (pDCTData->DimmX8Present[currDimm]) - tempW |= 0x800; - } - } - - /* determine Rtt_Nom for WL & Normal mode */ - if (is_fam15h()) { - tempW2 = fam15_rttnom(pDCTstat, dct, dimm, rank, package_type); - tempW1 = 0; - tempW1 |= ((tempW2 & 0x4) >> 2) << 9; - tempW1 |= ((tempW2 & 0x2) >> 1) << 6; - tempW1 |= ((tempW2 & 0x1) >> 0) << 2; - } else { - if (pDCTData->Status[DCT_STATUS_REGISTERED]) - tempW1 = RttNomNonTargetRegDimm(pMCTData, pDCTData, currDimm, wl, MemClkFreq, rank); - else - tempW1 = unbuffered_dimm_nominal_termination_emrs(pDCTData->MaxDimmsInstalled, MemClkFreq, pDCTData->DimmRanks[currDimm], rank); - } - - /* Apply Rtt_Nom to the MRS control word */ - tempW = tempW|tempW1; - - /* Program MrsAddress[5,1]=output driver impedance control (DIC) */ - if (is_fam15h()) { - tempW1 = fam15_dimm_dic(pDCTstat, dct, dimm, rank, package_type); - } else { - /* Read DIC from F2x[1,0]84[DrvImpCtrl] */ - tempW1 = get_Bits(pDCTData, dct, pDCTData->NodeId, - FUN_DCT, DRAM_MRS_REGISTER, DrvImpCtrlStart, DrvImpCtrlEnd); - } - - /* Apply DIC to the MRS control word */ - if (bitTest(tempW1,1)) - {tempW = bitTestSet(tempW, 5);} - if (bitTest(tempW1,0)) - {tempW = bitTestSet(tempW, 1);} - - tempW = swapAddrBits_wl(pDCTstat, dct, tempW); - - if (is_fam15h()) - set_Bits(pDCTData, dct, pDCTData->NodeId, - FUN_DCT, DRAM_INIT, MrsAddressStartFam15, MrsAddressEndFam15, tempW); - else - set_Bits(pDCTData, dct, pDCTData->NodeId, - FUN_DCT, DRAM_INIT, MrsAddressStartFam10, MrsAddressEndFam10, tempW); - - /* Program F2x[1, 0]7C[SendMrsCmd]=1 to initiate the command - * to the specified DIMM. - */ - set_Bits(pDCTData, dct, pDCTData->NodeId, - FUN_DCT, DRAM_INIT, SendMrsCmd, SendMrsCmd, 1); - - /* Wait for F2x[1, 0]7C[SendMrsCmd] to be cleared by hardware. */ - while ((get_Bits(pDCTData, dct, - pDCTData->NodeId, FUN_DCT, DRAM_INIT, - SendMrsCmd, SendMrsCmd)) == 1); - - /* Program F2x[1, 0]7C[MrsBank[2:0]] for the appropriate internal DRAM - * register that defines the required DDR3-defined function for Rtt_WR. - */ - MrsBank = swapBankBits(pDCTstat, dct, 2); - if (is_fam15h()) - set_Bits(pDCTData, dct, pDCTData->NodeId, FUN_DCT, - DRAM_INIT, MrsBankStartFam15, MrsBankEndFam15, MrsBank); - else - set_Bits(pDCTData, dct, pDCTData->NodeId, FUN_DCT, - DRAM_INIT, MrsBankStartFam10, MrsBankEndFam10, MrsBank); - - /* Program F2x[1, 0]7C[MrsAddress[15:0]] to the required DDR3-defined function - * for Rtt_WR (DRAMTermDyn). - */ - tempW = 0;/* PASR = 0,*/ - - /* Retrieve normal settings of the MRS control word and clear Rtt_WR */ - if (is_fam15h()) { - tempW = mct_MR2(pMCTstat, pDCTstat, dct, currDimm*2+rank) & 0xffff; - tempW &= ~(0x0600); - } else { - /* program MrsAddress[7,6,5:3]=SRT,ASR,CWL, - * based on F2x[1,0]84[19,18,22:20]=,SRT,ASR,Tcwl */ - tempW1 = get_Bits(pDCTData, dct, pDCTData->NodeId, - FUN_DCT, DRAM_MRS_REGISTER, PCI_MIN_LOW, PCI_MAX_HIGH); - if (bitTest(tempW1,19)) - {tempW = bitTestSet(tempW, 7);} - if (bitTest(tempW1,18)) - {tempW = bitTestSet(tempW, 6);} - /* tempW = tempW|(((tempW1 >> 20) & 0x7) << 3); */ - tempW = tempW|((tempW1&0x00700000) >> 17); - /* workaround for DR-B0 */ - if ((pDCTData->LogicalCPUID & AMD_DR_Bx) && (pDCTData->Status[DCT_STATUS_REGISTERED])) - tempW+=0x8; - } - - /* determine Rtt_WR for WL & Normal mode */ - if (is_fam15h()) { - tempW1 = (fam15_rttwr(pDCTstat, dct, dimm, rank, package_type) << 9); - } else { - if (pDCTData->Status[DCT_STATUS_REGISTERED]) - tempW1 = RttWrRegDimm(pMCTData, pDCTData, currDimm, wl, MemClkFreq, rank); - else - tempW1 = unbuffered_dimm_dynamic_termination_emrs(pDCTData->MaxDimmsInstalled, MemClkFreq, pDCTData->DimmRanks[currDimm]); - } - - /* Apply Rtt_WR to the MRS control word */ - tempW = tempW|tempW1; - tempW = swapAddrBits_wl(pDCTstat, dct, tempW); - if (is_fam15h()) - set_Bits(pDCTData, dct, pDCTData->NodeId, FUN_DCT, - DRAM_INIT, MrsAddressStartFam15, MrsAddressEndFam15, tempW); - else - set_Bits(pDCTData, dct, pDCTData->NodeId, FUN_DCT, - DRAM_INIT, MrsAddressStartFam10, MrsAddressEndFam10, tempW); - - /* Program F2x[1, 0]7C[SendMrsCmd]=1 to initiate the command to - the specified DIMM.*/ - set_Bits(pDCTData, dct, pDCTData->NodeId, FUN_DCT, - DRAM_INIT, SendMrsCmd, SendMrsCmd, 1); - - /* Wait for F2x[1, 0]7C[SendMrsCmd] to be cleared by hardware. */ - while ((get_Bits(pDCTData, dct, pDCTData->NodeId, - FUN_DCT, DRAM_INIT, SendMrsCmd, SendMrsCmd)) == 0x1) - { - } - rank++; - } - } - } - currDimm++; - } -} - -/*----------------------------------------------------------------------------- - * void programODT(sMCTStruct *pMCTData, DCTStruct *DCTData, u8 dimm) - * - * Description: - * This function programs the ODT values for the NB - * - * Parameters: - * IN OUT *DCTData - Pointer to buffer with information about each DCT - * IN - * OUT - * ---------------------------------------------------------------------------- - */ -void programODT(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstat, uint8_t dct, uint8_t dimm) -{ - sMCTStruct *pMCTData = pDCTstat->C_MCTPtr; - sDCTStruct *pDCTData = pDCTstat->C_DCTPtr[dct]; - - u8 WrLvOdt1 = 0; - - if (is_fam15h()) { - /* On Family15h processors, the value for the specific CS being targeted - * is taken from F2x238 / F2x23C as appropriate, then loaded into F2x9C_x0000_0008 - */ - - /* Convert DIMM number to CS */ - uint32_t dword; - uint8_t cs; - uint8_t rank = 0; - - cs = (dimm * 2) + rank; - - /* Fetch preprogammed ODT pattern from configuration registers */ - dword = Get_NB32_DCT(pDCTstat->dev_dct, dct, ((cs > 3)?0x23c:0x238)); - if ((cs == 7) || (cs == 3)) - WrLvOdt1 = ((dword >> 24) & 0xf); - else if ((cs == 6) || (cs == 2)) - WrLvOdt1 = ((dword >> 16) & 0xf); - else if ((cs == 5) || (cs == 1)) - WrLvOdt1 = ((dword >> 8) & 0xf); - else if ((cs == 4) || (cs == 0)) - WrLvOdt1 = (dword & 0xf); - } else { - if (pDCTData->Status[DCT_STATUS_REGISTERED]) { - WrLvOdt1 = WrLvOdtRegDimm(pMCTData, pDCTData, dimm); - } else { - if ((pDCTData->DctCSPresent & 0x05) == 0x05) { - WrLvOdt1 = 0x03; - } else if (bitTest((u32)pDCTData->DctCSPresent,(u8)(dimm*2+1))) { - WrLvOdt1 = (u8)bitTestSet(WrLvOdt1, dimm+2); - } else { - WrLvOdt1 = (u8)bitTestSet(WrLvOdt1, dimm); - } - } - } - - set_DCT_ADDR_Bits(pDCTData, dct, pDCTData->NodeId, FUN_DCT, - DRAM_ADD_DCT_PHY_CONTROL_REG, 8, 11, (u32)WrLvOdt1); - - printk(BIOS_SPEW, "Programmed DCT %d write levelling ODT pattern %08x from DIMM %d data\n", dct, WrLvOdt1, dimm); - -} - -#ifdef UNUSED_CODE -static uint16_t fam15h_next_lowest_memclk_freq(uint16_t memclk_freq) -{ - uint16_t fam15h_next_lowest_freq_tab[] = {0, 0, 0, 0, 0x4, 0, 0x4, 0, 0, 0, 0x6, 0, 0, 0, 0xa, 0, 0, 0, 0xe, 0, 0, 0, 0x12}; - return fam15h_next_lowest_freq_tab[memclk_freq]; -} -#endif - -/*----------------------------------------------------------------------------- - * void procConfig(MCTStruct *MCTData,DCTStruct *DCTData, u8 Dimm, u8 Pass, u8 Nibble) - * - * Description: - * This function programs the ODT values for the NB - * - * Parameters: - * IN OUT *DCTData - Pointer to buffer with information about each DCT - * *MCTData - Pointer to buffer with runtime parameters, - * IN Dimm - Logical DIMM - * Pass - First of Second Pass - * OUT - * ---------------------------------------------------------------------------- - */ -void procConfig(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstat, uint8_t dct, uint8_t dimm, uint8_t pass, uint8_t nibble) -{ - u8 ByteLane, MemClkFreq; - int32_t Seed_Gross; - int32_t Seed_Fine; - uint8_t Seed_PreGross; - u32 Value, Addr; - uint32_t dword; - u16 Addl_Data_Offset, Addl_Data_Port; - sMCTStruct *pMCTData = pDCTstat->C_MCTPtr; - sDCTStruct *pDCTData = pDCTstat->C_DCTPtr[dct]; - uint16_t fam10h_freq_tab[] = {0, 0, 0, 400, 533, 667, 800}; - uint16_t fam15h_freq_tab[] = {0, 0, 0, 0, 333, 0, 400, 0, 0, 0, 533, 0, 0, 0, 667, 0, 0, 0, 800, 0, 0, 0, 933}; - uint8_t lane_count; - - lane_count = get_available_lane_count(pMCTstat, pDCTstat); - - assert(lane_count <= MAX_LANE_COUNT); - - if (is_fam15h()) { - /* MemClkFreq: 0x4: 333MHz; 0x6: 400MHz; 0xa: 533MHz; 0xe: 667MHz; 0x12: 800MHz; 0x16: 933MHz */ - MemClkFreq = get_Bits(pDCTData, dct, pDCTData->NodeId, - FUN_DCT, DRAM_CONFIG_HIGH, 0, 4); - } else { - /* MemClkFreq: 3: 400MHz; 4: 533MHz; 5: 667MHz; 6: 800MHz */ - MemClkFreq = get_Bits(pDCTData, dct, pDCTData->NodeId, - FUN_DCT, DRAM_CONFIG_HIGH, 0, 2); - } - - /* Program F2x[1, 0]9C_x08[WrLvOdt[3:0]] to the proper ODT settings for the - * current memory subsystem configuration. - */ - programODT(pMCTstat, pDCTstat, dct, dimm); - - /* Program F2x[1,0]9C_x08[WrLvOdtEn]=1 */ - if (pDCTData->LogicalCPUID & (AMD_DR_Cx | AMD_DR_Dx | AMD_FAM15_ALL)) { - set_DCT_ADDR_Bits(pDCTData, dct, pDCTData->NodeId, FUN_DCT, - DRAM_ADD_DCT_PHY_CONTROL_REG, WrLvOdtEn, WrLvOdtEn, (u32)1); - } - else - { - /* Program WrLvOdtEn = 1 through set bit 12 of D3CSODT reg offset 0 for Rev.B */ - if (dct) - { - Addl_Data_Offset = 0x198; - Addl_Data_Port = 0x19C; - } - else - { - Addl_Data_Offset = 0x98; - Addl_Data_Port = 0x9C; - } - Addr = 0x0D008000; - AmdMemPCIWriteBits(MAKE_SBDFO(0,0,24+(pDCTData->NodeId),FUN_DCT,Addl_Data_Offset), 31, 0, &Addr); - while ((get_Bits(pDCTData,FUN_DCT,pDCTData->NodeId, FUN_DCT, Addl_Data_Offset, - DctAccessDone, DctAccessDone)) == 0); - AmdMemPCIReadBits(MAKE_SBDFO(0,0,24+(pDCTData->NodeId),FUN_DCT,Addl_Data_Port), 31, 0, &Value); - Value = bitTestSet(Value, 12); - AmdMemPCIWriteBits(MAKE_SBDFO(0,0,24+(pDCTData->NodeId),FUN_DCT,Addl_Data_Port), 31, 0, &Value); - Addr = 0x4D088F00; - AmdMemPCIWriteBits(MAKE_SBDFO(0,0,24+(pDCTData->NodeId),FUN_DCT,Addl_Data_Offset), 31, 0, &Addr); - while ((get_Bits(pDCTData,FUN_DCT,pDCTData->NodeId, FUN_DCT, Addl_Data_Offset, - DctAccessDone, DctAccessDone)) == 0); - } - - if (is_fam15h()) - proc_MFENCE(); - - /* Wait 10 MEMCLKs to allow for ODT signal settling. */ - if (is_fam15h()) - precise_memclk_delay_fam15(pMCTstat, pDCTstat, dct, 10); - else - pMCTData->AgesaDelay(10); - - /* Program write levelling seed values */ - if (pass == 1) - { - /* Pass 1 */ - if (is_fam15h()) { - uint8_t AddrCmdPrelaunch = 0; /* TODO: Fetch the correct value from RC2[0] */ - uint8_t package_type = mctGet_NVbits(NV_PACK_TYPE); - uint16_t Seed_Total = 0; - pDCTData->WrDqsGrossDlyBaseOffset = 0x0; - if (package_type == PT_GR) { - /* Socket G34: Fam15h BKDG v3.14 Table 96 */ - if (pDCTData->Status[DCT_STATUS_REGISTERED]) { - /* TODO - * Implement mainboard-specific seed and - * WrDqsGrossDly base overrides. - * 0x41 and 0x0 are the "stock" values - */ - Seed_Total = 0x41; - pDCTData->WrDqsGrossDlyBaseOffset = 0x2; - } else if (pDCTData->Status[DCT_STATUS_LOAD_REDUCED]) { - Seed_Total = 0x0; - } else { - Seed_Total = 0xf; - } - } else if (package_type == PT_C3) { - /* Socket C32: Fam15h BKDG v3.14 Table 97 */ - if (pDCTData->Status[DCT_STATUS_REGISTERED]) { - Seed_Total = 0x3e; - } else if (pDCTData->Status[DCT_STATUS_LOAD_REDUCED]) { - Seed_Total = 0x0; - } else { - Seed_Total = 0x12; - } - } else if (package_type == PT_M2) { - /* Socket AM3: Fam15h BKDG v3.14 Table 98 */ - Seed_Total = 0xf; - } else if (package_type == PT_FM2) { - /* Socket FM2: Fam15h M10 BKDG 3.12 Table 42 */ - Seed_Total = 0x15; - } - if (pDCTData->Status[DCT_STATUS_REGISTERED]) - Seed_Total += ((AddrCmdPrelaunch)?0x10:0x0); - - /* Adjust seed for the minimum platform supported frequency */ - Seed_Total = (int32_t) (((((int64_t) Seed_Total) * - fam15h_freq_tab[MemClkFreq] * 100) / (mctGet_NVbits(NV_MIN_MEMCLK) * 100))); - - Seed_Gross = (Seed_Total >> 5) & 0x1f; - Seed_Fine = Seed_Total & 0x1f; - - /* Save seed values for later use */ - for (ByteLane = 0; ByteLane < lane_count; ByteLane++) { - pDCTData->WLSeedGrossDelay[lane_count*dimm+ByteLane] = Seed_Gross; - pDCTData->WLSeedFineDelay[lane_count*dimm+ByteLane] = Seed_Fine; - - if (Seed_Gross == 0) - Seed_PreGross = 0; - else if (Seed_Gross & 0x1) - Seed_PreGross = 1; - else - Seed_PreGross = 2; - - pDCTData->WLSeedPreGrossDelay[lane_count*dimm+ByteLane] = Seed_PreGross; - } - } else { - if (pDCTData->Status[DCT_STATUS_REGISTERED]) { - uint8_t AddrCmdPrelaunch = 0; /* TODO: Fetch the correct value from RC2[0] */ - - /* The seed values below assume Pass 1 utilizes a 400MHz clock frequency (DDR3-800) */ - if (AddrCmdPrelaunch == 0) { - Seed_Gross = 0x02; - Seed_Fine = 0x01; - } else { - Seed_Gross = 0x02; - Seed_Fine = 0x11; - } - } else { - if (MemClkFreq == 6) { - /* DDR-800 */ - Seed_Gross = 0x00; - Seed_Fine = 0x1a; - } else { - /* Use settings for DDR-400 (interpolated from BKDG) */ - Seed_Gross = 0x00; - Seed_Fine = 0x0d; - } - } - } - for (ByteLane = 0; ByteLane < lane_count; ByteLane++) - { - /* Program an initialization value to registers F2x[1, 0]9C_x[51:50] and - * F2x[1, 0]9C_x52 to set the gross and fine delay for all the byte lane fields - * If the target frequency is different than 400MHz, BIOS must - * execute two training passes for each DIMM. - * For pass 1 at a 400MHz MEMCLK frequency, use an initial total delay value - * of 01Fh. This represents a 1UI (UI=.5MEMCLK) delay and is determined - * by design. - */ - pDCTData->WLGrossDelay[lane_count*dimm+ByteLane] = Seed_Gross; - pDCTData->WLFineDelay[lane_count*dimm+ByteLane] = Seed_Fine; - printk(BIOS_SPEW, "\tLane %02x initial seed: %04x\n", ByteLane, ((Seed_Gross & 0x1f) << 5) | (Seed_Fine & 0x1f)); - } - } else { - if (nibble == 0) { - /* Pass 2 */ - /* From BKDG, Write Leveling Seed Value. */ - if (is_fam15h()) { - uint32_t RegisterDelay; - int32_t SeedTotal[MAX_LANE_COUNT]; - int32_t SeedTotalPreScaling[MAX_LANE_COUNT]; - uint32_t WrDqDqsEarly; - uint8_t AddrCmdPrelaunch = 0; /* TODO: Fetch the correct value from RC2[0] */ - - if (pDCTData->Status[DCT_STATUS_REGISTERED]) { - if (AddrCmdPrelaunch) - RegisterDelay = 0x30; - else - RegisterDelay = 0x20; - } else { - RegisterDelay = 0; - } - - /* Retrieve WrDqDqsEarly */ - dword = Get_NB32_DCT(pDCTstat->dev_dct, dct, 0xa8); - WrDqDqsEarly = (dword >> 24) & 0x3; - - /* FIXME - * Ignore WrDqDqsEarly for now to work around training issues - */ - WrDqDqsEarly = 0; - - /* Generate new seed values */ - for (ByteLane = 0; ByteLane < lane_count; ByteLane++) { - /* Calculate adjusted seed values */ - SeedTotal[ByteLane] = (pDCTData->WLFineDelayPrevPass[lane_count*dimm+ByteLane] & 0x1f) | - ((pDCTData->WLGrossDelayPrevPass[lane_count*dimm+ByteLane] & 0x1f) << 5); - SeedTotalPreScaling[ByteLane] = (SeedTotal[ByteLane] - RegisterDelay - (0x20 * WrDqDqsEarly)); - SeedTotal[ByteLane] = (int32_t) (RegisterDelay + ((((int64_t) SeedTotalPreScaling[ByteLane]) * - fam15h_freq_tab[MemClkFreq] * 100) / (fam15h_freq_tab[pDCTData->WLPrevMemclkFreq[dimm]] * 100))); - } - - /* Generate register values from seeds */ - for (ByteLane = 0; ByteLane < lane_count; ByteLane++) { - printk(BIOS_SPEW, "\tLane %02x scaled delay: %04x\n", ByteLane, SeedTotal[ByteLane]); - - if (SeedTotal[ByteLane] >= 0) { - Seed_Gross = SeedTotal[ByteLane] / 32; - Seed_Fine = SeedTotal[ByteLane] % 32; - } else { - Seed_Gross = (SeedTotal[ByteLane] / 32) - 1; - Seed_Fine = (SeedTotal[ByteLane] % 32) + 32; - } - - /* The BKDG-recommended algorithm causes problems with registered DIMMs on some systems - * due to the long register delays causing premature total delay wrap-around. - * Attempt to work around this... - */ - Seed_PreGross = Seed_Gross; - - /* Save seed values for later use */ - pDCTData->WLSeedGrossDelay[lane_count*dimm+ByteLane] = Seed_Gross; - pDCTData->WLSeedFineDelay[lane_count*dimm+ByteLane] = Seed_Fine; - pDCTData->WLSeedPreGrossDelay[lane_count*dimm+ByteLane] = Seed_PreGross; - - pDCTData->WLGrossDelay[lane_count*dimm+ByteLane] = Seed_PreGross; - pDCTData->WLFineDelay[lane_count*dimm+ByteLane] = Seed_Fine; - - printk(BIOS_SPEW, "\tLane %02x new seed: %04x\n", ByteLane, ((pDCTData->WLGrossDelay[lane_count*dimm+ByteLane] & 0x1f) << 5) | (pDCTData->WLFineDelay[lane_count*dimm+ByteLane] & 0x1f)); - } - } else { - uint32_t RegisterDelay; - uint32_t SeedTotalPreScaling; - uint32_t SeedTotal; - uint8_t AddrCmdPrelaunch = 0; /* TODO: Fetch the correct value from RC2[0] */ - for (ByteLane = 0; ByteLane < lane_count; ByteLane++) - { - if (pDCTData->Status[DCT_STATUS_REGISTERED]) { - if (AddrCmdPrelaunch == 0) - RegisterDelay = 0x20; - else - RegisterDelay = 0x30; - } else { - RegisterDelay = 0; - } - SeedTotalPreScaling = ((pDCTData->WLFineDelay[lane_count*dimm+ByteLane] & 0x1f) | - (pDCTData->WLGrossDelay[lane_count*dimm+ByteLane] << 5)) - RegisterDelay; - /* SeedTotalPreScaling = (the total delay value in F2x[1, 0]9C_x[4A:30] from pass 1 of write levelization - training) - RegisterDelay. */ - SeedTotal = (uint16_t) ((((uint64_t) SeedTotalPreScaling) * - fam10h_freq_tab[MemClkFreq] * 100) / (fam10h_freq_tab[3] * 100)); - Seed_Gross = SeedTotal / 32; - Seed_Fine = SeedTotal & 0x1f; - if (Seed_Gross == 0) - Seed_Gross = 0; - else if (Seed_Gross & 0x1) - Seed_Gross = 1; - else - Seed_Gross = 2; - - /* The BKDG-recommended algorithm causes problems with registered DIMMs on some systems - * due to the long register delays causing premature total delay wrap-around. - * Attempt to work around this... - */ - SeedTotal = ((Seed_Gross & 0x1f) << 5) | (Seed_Fine & 0x1f); - SeedTotal += RegisterDelay; - Seed_Gross = SeedTotal / 32; - Seed_Fine = SeedTotal & 0x1f; - - pDCTData->WLGrossDelay[lane_count*dimm+ByteLane] = Seed_Gross; - pDCTData->WLFineDelay[lane_count*dimm+ByteLane] = Seed_Fine; - - printk(BIOS_SPEW, "\tLane %02x new seed: %04x\n", ByteLane, ((pDCTData->WLGrossDelay[lane_count*dimm+ByteLane] & 0x1f) << 5) | (pDCTData->WLFineDelay[lane_count*dimm+ByteLane] & 0x1f)); - } - } - - /* Save initial seeds for upper nibble pass */ - for (ByteLane = 0; ByteLane < lane_count; ByteLane++) { - pDCTData->WLSeedPreGrossPrevNibble[lane_count*dimm+ByteLane] = pDCTData->WLSeedPreGrossDelay[lane_count*dimm+ByteLane]; - pDCTData->WLSeedGrossPrevNibble[lane_count*dimm+ByteLane] = pDCTData->WLGrossDelay[lane_count*dimm+ByteLane]; - pDCTData->WLSeedFinePrevNibble[lane_count*dimm+ByteLane] = pDCTData->WLFineDelay[lane_count*dimm+ByteLane]; - } - } else { - /* Restore seed values from lower nibble pass */ - if (is_fam15h()) { - for (ByteLane = 0; ByteLane < lane_count; ByteLane++) { - pDCTData->WLSeedGrossDelay[lane_count*dimm+ByteLane] = pDCTData->WLSeedGrossPrevNibble[lane_count*dimm+ByteLane]; - pDCTData->WLSeedFineDelay[lane_count*dimm+ByteLane] = pDCTData->WLSeedFinePrevNibble[lane_count*dimm+ByteLane]; - pDCTData->WLSeedPreGrossDelay[lane_count*dimm+ByteLane] = pDCTData->WLSeedPreGrossPrevNibble[lane_count*dimm+ByteLane]; - - pDCTData->WLGrossDelay[lane_count*dimm+ByteLane] = pDCTData->WLSeedPreGrossPrevNibble[lane_count*dimm+ByteLane]; - pDCTData->WLFineDelay[lane_count*dimm+ByteLane] = pDCTData->WLSeedFinePrevNibble[lane_count*dimm+ByteLane]; - - printk(BIOS_SPEW, "\tLane %02x new seed: %04x\n", ByteLane, ((pDCTData->WLGrossDelay[lane_count*dimm+ByteLane] & 0x1f) << 5) | (pDCTData->WLFineDelay[lane_count*dimm+ByteLane] & 0x1f)); - } - } else { - for (ByteLane = 0; ByteLane < lane_count; ByteLane++) { - pDCTData->WLGrossDelay[lane_count*dimm+ByteLane] = pDCTData->WLSeedGrossPrevNibble[lane_count*dimm+ByteLane]; - pDCTData->WLFineDelay[lane_count*dimm+ByteLane] = pDCTData->WLSeedFinePrevNibble[lane_count*dimm+ByteLane]; - - printk(BIOS_SPEW, "\tLane %02x new seed: %04x\n", ByteLane, ((pDCTData->WLGrossDelay[lane_count*dimm+ByteLane] & 0x1f) << 5) | (pDCTData->WLFineDelay[lane_count*dimm+ByteLane] & 0x1f)); - } - } - } - } - - pDCTData->WLPrevMemclkFreq[dimm] = MemClkFreq; - setWLByteDelay(pDCTstat, dct, ByteLane, dimm, 0, pass, lane_count); -} - -/*----------------------------------------------------------------------------- - * void setWLByteDelay(struct DCTStatStruc *pDCTstat, uint8_t dct, u8 ByteLane, u8 Dimm, uint8_t lane_count){ - * - * Description: - * This function writes the write levelization byte delay for the Phase - * Recovery control registers - * - * Parameters: - * IN OUT *DCTData - Pointer to buffer with information about each DCT - * IN Dimm - Dimm Number - * DCTData->WLGrossDelay[index+ByteLane] - gross write delay for each - * logical DIMM - * DCTData->WLFineDelay[index+ByteLane] - fine write delay for each - * logical DIMM - * ByteLane - target byte lane to write - * targetAddr - 0: write to DRAM phase recovery control register - * 1: write to DQS write register - * OUT - * - *----------------------------------------------------------------------------- - */ -void setWLByteDelay(struct DCTStatStruc *pDCTstat, uint8_t dct, u8 ByteLane, u8 dimm, u8 targetAddr, uint8_t pass, uint8_t lane_count) -{ - sDCTStruct *pDCTData = pDCTstat->C_DCTPtr[dct]; - u8 fineStartLoc, fineEndLoc, grossStartLoc, grossEndLoc, tempB, index, offsetAddr; - u32 addr, fineDelayValue, grossDelayValue, ValueLow, ValueHigh, EccValue, tempW; - - if (targetAddr == 0) - { - index = (u8)(lane_count * dimm); - ValueLow = 0; - ValueHigh = 0; - ByteLane = 0; - EccValue = 0; - while (ByteLane < lane_count) - { - /* This subtract 0xC workaround might be temporary. */ - if ((pDCTData->WLPass == 2) && (pDCTData->RegMan1Present & (1 << (dimm*2+dct)))) { - tempW = (pDCTData->WLGrossDelay[index+ByteLane] << 5) | pDCTData->WLFineDelay[index+ByteLane]; - tempW -= 0xC; - pDCTData->WLGrossDelay[index+ByteLane] = (u8)(tempW >> 5); - pDCTData->WLFineDelay[index+ByteLane] = (u8)(tempW & 0x1F); - } - grossDelayValue = pDCTData->WLGrossDelay[index+ByteLane]; - /* Adjust seed gross delay overflow (greater than 3): - * - Program seed gross delay as 2 (gross is 4 or 6) or 1 (gross is 5). - * - Keep original seed gross delay for later reference. - */ - if (grossDelayValue >= 3) - grossDelayValue = (grossDelayValue&1)? 1 : 2; - fineDelayValue = pDCTData->WLFineDelay[index+ByteLane]; - if (ByteLane < 4) - ValueLow |= ((grossDelayValue << 5) | fineDelayValue) << 8*ByteLane; - else if (ByteLane < 8) - ValueHigh |= ((grossDelayValue << 5) | fineDelayValue) << 8*(ByteLane-4); - else - EccValue = ((grossDelayValue << 5) | fineDelayValue); - ByteLane++; - } - set_DCT_ADDR_Bits(pDCTData, dct, pDCTData->NodeId, FUN_DCT, - DRAM_CONT_ADD_PHASE_REC_CTRL_LOW, 0, 31, (u32)ValueLow); - set_DCT_ADDR_Bits(pDCTData, dct, pDCTData->NodeId, FUN_DCT, - DRAM_CONT_ADD_PHASE_REC_CTRL_HIGH, 0, 31, (u32)ValueHigh); - set_DCT_ADDR_Bits(pDCTData, dct, pDCTData->NodeId, FUN_DCT, - DRAM_CONT_ADD_ECC_PHASE_REC_CTRL, 0, 31, (u32)EccValue); - } - else - { - /* Fam10h BKDG: Rev. 3.62 2.8.9.9.1 (6) - * Fam15h BKDG: Rev. 3.14 2.10.5.8.1 - */ - index = (u8)(lane_count * dimm); - grossDelayValue = pDCTData->WLGrossDelay[index+ByteLane]; - fineDelayValue = pDCTData->WLFineDelay[index+ByteLane]; - - tempB = 0; - offsetAddr = (u8)(3 * dimm); - if (ByteLane < 2) { - tempB = (u8)(16 * ByteLane); - addr = DRAM_CONT_ADD_DQS_TIMING_CTRL_BL_01; - } else if (ByteLane <4) { - tempB = (u8)(16 * ByteLane); - addr = DRAM_CONT_ADD_DQS_TIMING_CTRL_BL_01 + 1; - } else if (ByteLane <6) { - tempB = (u8)(16 * ByteLane); - addr = DRAM_CONT_ADD_DQS_TIMING_CTRL_BL_45; - } else if (ByteLane <8) { - tempB = (u8)(16 * ByteLane); - addr = DRAM_CONT_ADD_DQS_TIMING_CTRL_BL_45 + 1; - } else { - tempB = 0; - addr = DRAM_CONT_ADD_DQS_TIMING_CTRL_BL_01 + 2; - } - addr += offsetAddr; - - fineStartLoc = (u8)(tempB % 32); - fineEndLoc = (u8)(fineStartLoc + 4); - grossStartLoc = (u8)(fineEndLoc + 1); - grossEndLoc = (u8)(grossStartLoc + 2); - - set_DCT_ADDR_Bits(pDCTData, dct, pDCTData->NodeId, FUN_DCT, - (u16)addr, fineStartLoc, fineEndLoc,(u32)fineDelayValue); - set_DCT_ADDR_Bits(pDCTData, dct, pDCTData->NodeId, FUN_DCT, - (u16)addr, grossStartLoc, grossEndLoc, (u32)grossDelayValue); - - pDCTData->WLFineDelayPrevPass[index+ByteLane] = fineDelayValue; - pDCTData->WLGrossDelayPrevPass[index+ByteLane] = grossDelayValue; - if (pass == FirstPass) { - pDCTData->WLFineDelayFirstPass[index+ByteLane] = fineDelayValue; - pDCTData->WLGrossDelayFirstPass[index+ByteLane] = grossDelayValue; - pDCTData->WLCriticalGrossDelayFirstPass = pDCTData->WLCriticalGrossDelayPrevPass; - } - } - -} - -/*----------------------------------------------------------------------------- - * void getWLByteDelay(struct DCTStatStruc *pDCTstat, uint8_t dct, u8 ByteLane, u8 Dimm, u8 Nibble, uint8_t lane_count) - * - * Description: - * This function reads the write levelization byte delay from the Phase - * Recovery control registers - * - * Parameters: - * IN OUT *DCTData - Pointer to buffer with information about each DCT - * IN Dimm - Dimm Number - * ByteLane - target byte lane to read - * OUT - * DCTData->WLGrossDelay[index+ByteLane] - gross write delay for current - * byte for logical DIMM - * DCTData->WLFineDelay[index+ByteLane] - fine write delay for current - * byte for logical DIMM - * - *----------------------------------------------------------------------------- - */ -void getWLByteDelay(struct DCTStatStruc *pDCTstat, uint8_t dct, u8 ByteLane, u8 dimm, uint8_t pass, uint8_t nibble, uint8_t lane_count) -{ - sDCTStruct *pDCTData = pDCTstat->C_DCTPtr[dct]; - u8 fineStartLoc, fineEndLoc, grossStartLoc, grossEndLoc, tempB, tempB1, index; - u32 addr, fine, gross; - tempB = 0; - index = (u8)(lane_count*dimm); - if (ByteLane < 4) { - tempB = (u8)(8 * ByteLane); - addr = DRAM_CONT_ADD_PHASE_REC_CTRL_LOW; - } else if (ByteLane < 8) { - tempB1 = (u8)(ByteLane - 4); - tempB = (u8)(8 * tempB1); - addr = DRAM_CONT_ADD_PHASE_REC_CTRL_HIGH; - } else { - tempB = 0; - addr = DRAM_CONT_ADD_ECC_PHASE_REC_CTRL; - } - fineStartLoc = tempB; - fineEndLoc = (u8)(fineStartLoc + 4); - grossStartLoc = (u8)(fineEndLoc + 1); - grossEndLoc = (u8)(grossStartLoc + 1); - - fine = get_ADD_DCT_Bits(pDCTData, dct, pDCTData->NodeId, - FUN_DCT, (u16)addr, fineStartLoc, fineEndLoc); - gross = get_ADD_DCT_Bits(pDCTData, dct, pDCTData->NodeId, - FUN_DCT, (u16)addr, grossStartLoc, grossEndLoc); - - printk(BIOS_SPEW, "\tLane %02x nibble %01x raw readback: %04x\n", ByteLane, nibble, ((gross & 0x1f) << 5) | (fine & 0x1f)); - - /* Adjust seed gross delay overflow (greater than 3): - * - Adjust the trained gross delay to the original seed gross delay. - */ - if (pDCTData->WLGrossDelay[index+ByteLane] >= 3) - { - gross += pDCTData->WLGrossDelay[index+ByteLane]; - if (pDCTData->WLGrossDelay[index+ByteLane] & 1) - gross -= 1; - else - gross -= 2; - } - else if ((pDCTData->WLGrossDelay[index+ByteLane] == 0) && (gross == 3)) - { - /* If seed gross delay is 0 but PRE result gross delay is 3, it is negative. - * We will then round the negative number to 0. - */ - gross = 0; - fine = 0; - } - printk(BIOS_SPEW, "\tLane %02x nibble %01x adjusted value (pre nibble): %04x\n", ByteLane, nibble, ((gross & 0x1f) << 5) | (fine & 0x1f)); - - /* Nibble adjustments */ - if (nibble == 0) { - pDCTData->WLFineDelay[index+ByteLane] = (uint8_t)fine; - pDCTData->WLGrossDelay[index+ByteLane] = (uint8_t)gross; - } else { - uint32_t WLTotalDelay = ((pDCTData->WLGrossDelay[index+ByteLane] & 0x1f) << 5) | (pDCTData->WLFineDelay[index+ByteLane] & 0x1f); - WLTotalDelay += ((gross & 0x1f) << 5) | (fine & 0x1f); - WLTotalDelay /= 2; - pDCTData->WLFineDelay[index+ByteLane] = (uint8_t)(WLTotalDelay & 0x1f); - pDCTData->WLGrossDelay[index+ByteLane] = (uint8_t)((WLTotalDelay >> 5) & 0x1f); - } - printk(BIOS_SPEW, "\tLane %02x nibble %01x adjusted value (post nibble): %04x\n", ByteLane, nibble, ((pDCTData->WLGrossDelay[index+ByteLane] & 0x1f) << 5) | (pDCTData->WLFineDelay[index+ByteLane] & 0x1f)); -} diff --git a/src/northbridge/amd/amdmct/mct_ddr3/modtrd.c b/src/northbridge/amd/amdmct/mct_ddr3/modtrd.c deleted file mode 100644 index 954dd6f2ef..0000000000 --- a/src/northbridge/amd/amdmct/mct_ddr3/modtrd.c +++ /dev/null @@ -1,95 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2010 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include - -#include "mct_d.h" -#include "mct_d_gcc.h" - -u32 mct_MR1Odt_RDimm(struct MCTStatStruc *pMCTstat, - struct DCTStatStruc *pDCTstat, u8 dct, u32 MrsChipSel) -{ - u8 Speed = pDCTstat->Speed; - u32 ret; - u8 DimmsInstalled, DimmNum, ChipSelect; - - ChipSelect = (MrsChipSel >> 20) & 0xF; - DimmNum = ChipSelect & 0xFE; - DimmsInstalled = pDCTstat->MAdimms[dct]; - if (dct == 1) - DimmNum ++; - ret = 0; - - if (mctGet_NVbits(NV_MAX_DIMMS) == 4) { - if (DimmsInstalled == 1) - ret |= 1 << 2; - else { - if (pDCTstat->CSPresent & 0xF0) { - if (pDCTstat->DimmQRPresent & (1 << DimmNum)) { - if (!(ChipSelect & 1)) - ret |= 1 << 2; - } else - ret |= 0x204; - } else { - if (Speed < 6) - ret |= 0x44; - else - ret |= 0x204; - } - } - } else if (DimmsInstalled == 1) - ret |= 1 << 2; - else if (Speed < 6) - ret |= 0x44; - else - ret |= 0x204; - - //ret = 0; - return ret; -} - -u32 mct_DramTermDyn_RDimm(struct MCTStatStruc *pMCTstat, - struct DCTStatStruc *pDCTstat, u8 dimm) -{ - u8 DimmsInstalled = dimm; - u32 DramTermDyn = 0; - u8 Speed = pDCTstat->Speed; - - if (mctGet_NVbits(NV_MAX_DIMMS) == 4) { - if (pDCTstat->CSPresent & 0xF0) { - if (DimmsInstalled == 1) - if (Speed == 7) - DramTermDyn |= 1 << 10; - else - DramTermDyn |= 1 << 11; - else - if (Speed == 4) - DramTermDyn |= 1 << 11; - else - DramTermDyn |= 1 << 10; - } else { - if (DimmsInstalled != 1) { - if (Speed == 7) - DramTermDyn |= 1 << 10; - else - DramTermDyn |= 1 << 11; - } - } - } else { - if (DimmsInstalled != 1) - DramTermDyn |= 1 << 11; - } - return DramTermDyn; -} diff --git a/src/northbridge/amd/amdmct/mct_ddr3/modtrdim.c b/src/northbridge/amd/amdmct/mct_ddr3/modtrdim.c deleted file mode 100644 index 06bfdba84f..0000000000 --- a/src/northbridge/amd/amdmct/mct_ddr3/modtrdim.c +++ /dev/null @@ -1,262 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2010 Advanced Micro Devices, Inc. - * Copyright (C) 2015 Timothy Pearson , Raptor Engineering - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -/* This file contains functions for odt setting on registered DDR3 dimms */ - -#include -#include - -#include "mct_d.h" -#include "mct_d_gcc.h" - -/** - * - * - * This function set Rtt_Nom for registered DDR3 dimms on targeted dimm. - * - * @param *pMCTData - * @param[in] *pDCTData - Pointer to buffer with information about each DCT - * @param dimm - targeted dimm - * @param wl - current mode, either write levelization mode or normal mode - * @param MemClkFreq - current frequency - * @param rank - * - * @return tempW1 - Rtt_Nom - */ -u32 RttNomTargetRegDimm (sMCTStruct *pMCTData, sDCTStruct *pDCTData, u8 dimm, BOOL wl, u8 MemClkFreq, u8 rank) -{ - u32 tempW1; - tempW1 = 0; - if (wl) { - switch (mctGet_NVbits(NV_MAX_DIMMS_PER_CH)) { - case 2: - /* 2 dimms per channel */ - if (pDCTData->MaxDimmsInstalled == 1) { - if ((pDCTData->DimmRanks[dimm] == 2) && (rank == 0)) { - tempW1 = 0x00; /* Rtt_Nom = OFF */ - } else if (pDCTData->DimmRanks[dimm] == 4) { - if (rank == 1) { - tempW1 = 0x00; /* Rtt_Nom = OFF on second and forth rank of QR dimm */ - } else { - if (MemClkFreq == 6) { - tempW1 = 0x04; /* Rtt_Nom = 60 ohms */ - } else { - tempW1 = 0x40; /* Rtt_Nom = 120 ohms */ - } - } - } else { - tempW1 = 0x04; /* Rtt_Nom = 60 ohms */ - } - } else if (pDCTData->MaxDimmsInstalled == 2) { - if (((pDCTData->DimmRanks[dimm] == 2) || (pDCTData->DimmRanks[dimm] == 4)) && (rank == 1)) { - tempW1 = 0x00; /* Rtt_Nom = OFF */ - } else if ((pDCTData->DimmRanks[dimm] == 4) || (pDCTData->DctCSPresent & 0xF0)) { - if (MemClkFreq == 3) { - tempW1 = 0x40; /* Rtt_Nom = 120 ohms */ - } else { - tempW1 = 0x04; /* Rtt_Nom = 60 ohms */ - } - } else { - if (MemClkFreq == 6) { - tempW1 = 0x04; /* Rtt_Nom = 60 ohms */ - } else { - tempW1 = 0x40; /* Rtt_Nom = 120 ohms */ - } - } - } - break; - case 3: - /* 3 dimms per channel */ - /* QR not supported in this case on L1 package. */ - if (pDCTData->MaxDimmsInstalled == 1) { - if ((pDCTData->DimmRanks[dimm] == 2) && (rank == 1)) { - tempW1 = 0x00; /* Rtt_Nom = OFF */ - } else { - tempW1 = 0x04; /* Rtt_Nom = 60 ohms */ - } - } else { - tempW1 = 0x40; /* Rtt_Nom = 120 ohms */ - } - break; - default: - die("modtrdim.c: WTF?"); - } - } else { - switch (mctGet_NVbits(NV_MAX_DIMMS_PER_CH)) { - case 2: - /* 2 dimms per channel */ - if ((pDCTData->DimmRanks[dimm] == 4) && (rank == 1)) { - tempW1 = 0x00; /* Rtt_Nom = OFF */ - } else if ((pDCTData->MaxDimmsInstalled == 1) || (pDCTData->DimmRanks[dimm] == 4)) { - tempW1 = 0x04; /* Rtt_Nom = 60 ohms */ - } else { - if (pDCTData->DctCSPresent & 0xF0) { - tempW1 = 0x0204; /* Rtt_Nom = 30 ohms */ - } else { - if (MemClkFreq < 5) { - tempW1 = 0x44; /* Rtt_Nom = 40 ohms */ - } else { - tempW1 = 0x0204; /* Rtt_Nom = 30 ohms */ - } - } - } - break; - case 3: - /* 3 dimms per channel */ - /* L1 package does not support QR dimms this case. */ - if (rank == 1) { - tempW1 = 0x00; /* Rtt_Nom = OFF */ - } else if (pDCTData->MaxDimmsInstalled == 1) { - tempW1 = 0x04; /* Rtt_Nom = 60 ohms */ - } else if ((MemClkFreq < 5) || (pDCTData->MaxDimmsInstalled == 3)) { - tempW1 = 0x44; /* Rtt_Nom = 40 ohms */ - } else { - tempW1 = 0x0204; /* Rtt_Nom = 30 ohms */ - } - break; - default: - die("modtrdim.c: WTF?"); - } - } - return tempW1; -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * - * This function set Rtt_Nom for registered DDR3 dimms on non-targeted dimm. - * - * @param *pMCTData - * @param[in] *pDCTData - Pointer to buffer with information about each DCT - * @param dimm - non-targeted dimm - * @param wl - current mode, either write levelization mode or normal mode - * @param MemClkFreq - current frequency - * @param rank - * - * @return tempW1 - Rtt_Nom - */ -u32 RttNomNonTargetRegDimm (sMCTStruct *pMCTData, sDCTStruct *pDCTData, u8 dimm, BOOL wl, u8 MemClkFreq, u8 rank) -{ - if ((wl) && (mctGet_NVbits(NV_MAX_DIMMS_PER_CH) == 2) && (pDCTData->DimmRanks[dimm] == 2) && (rank == 1)) { - return 0x00; /* for non-target dimm during WL, the second rank of a DR dimm need to have Rtt_Nom = OFF */ - } else { - return RttNomTargetRegDimm (pMCTData, pDCTData, dimm, FALSE, MemClkFreq, rank); /* otherwise, the same as target dimm in normal mode. */ - } -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * - * This function set Rtt_Wr for registered DDR3 dimms. - * - * @param pMCTData - * @param[in] *pDCTData - Pointer to buffer with information about each DCT - * @param dimm - targeted dimm - * @param wl - current mode, either write levelization mode or normal mode - * @param MemClkFreq - current frequency - * @param rank - * - * @return tempW1 - Rtt_Wr - */ - -u32 RttWrRegDimm (sMCTStruct *pMCTData, sDCTStruct *pDCTData, u8 dimm, BOOL wl, u8 MemClkFreq, u8 rank) -{ - u32 tempW1; - tempW1 = 0; - if (wl) { - tempW1 = 0x00; /* Rtt_WR = OFF */ - } else { - switch (mctGet_NVbits(NV_MAX_DIMMS_PER_CH)) { - case 2: - if (pDCTData->MaxDimmsInstalled == 1) { - if (pDCTData->DimmRanks[dimm] != 4) { - tempW1 = 0x00; - } else { - if (MemClkFreq == 6) { - tempW1 = 0x200; /* Rtt_WR = 60 ohms */ - } else { - tempW1 = 0x400; /* Rtt_WR = 120 ohms */ - } - } - } else { - if ((pDCTData->DimmRanks[dimm] == 4) || (pDCTData->DctCSPresent & 0xF0)) { - if (MemClkFreq == 3) { - tempW1 = 0x400; /* Rtt_WR = 120 ohms */ - } else { - tempW1 = 0x200; /* Rtt_WR = 60 ohms */ - } - } else { - if (MemClkFreq == 6) { - tempW1 = 0x200; /* Rtt_WR = 60 ohms */ - } else { - tempW1 = 0x400; /* Rtt_Nom = 120 ohms */ - } - } - } - break; - case 3: - if (pDCTData->MaxDimmsInstalled == 1) { - tempW1 = 0x00; /* Rtt_WR = OFF */ - } else { - tempW1 = 0x400; /* Rtt_Nom = 120 ohms */ - } - break; - default: - die("modtrdim.c: WTF?"); - } - } - return tempW1; -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * - * This function set WrLvOdt for registered DDR3 dimms. - * - * @param *pMCTData - * @param[in] *pDCTData - Pointer to buffer with information about each DCT - * @param dimm - targeted dimm - * - * @return WrLvOdt - */ -u8 WrLvOdtRegDimm (sMCTStruct *pMCTData, sDCTStruct *pDCTData, u8 dimm) -{ - u8 WrLvOdt1, i; - WrLvOdt1 = 0; - i = 0; - while (i < 8) { - if (pDCTData->DctCSPresent & (1 << i)) { - WrLvOdt1 = (u8)bitTestSet(WrLvOdt1, i/2); - } - i += 2; - } - if (mctGet_NVbits(NV_MAX_DIMMS_PER_CH) == 2) { - if ((pDCTData->DimmRanks[dimm] == 4) && (pDCTData->MaxDimmsInstalled != 1)) { - if (dimm >= 2) { - WrLvOdt1 = (u8)bitTestReset (WrLvOdt1, (dimm - 2)); - } else { - WrLvOdt1 = (u8)bitTestReset (WrLvOdt1, (dimm + 2)); - } - } else if ((pDCTData->DimmRanks[dimm] == 2) && (pDCTData->MaxDimmsInstalled == 1)) { - /* the case for one DR on a 2 dimms per channel is special */ - WrLvOdt1 = 0x8; - } - } - return WrLvOdt1; -} diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mport_d.c b/src/northbridge/amd/amdmct/mct_ddr3/mport_d.c deleted file mode 100644 index 999cb94f24..0000000000 --- a/src/northbridge/amd/amdmct/mct_ddr3/mport_d.c +++ /dev/null @@ -1,42 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2010 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include - -#include "mct_d.h" -#include "mct_d_gcc.h" -#include "mwlc_d.h" - -void AmdMemPCIRead(SBDFO loc, u32 *Value) -{ - /* Convert SBDFO into a CF8 Address */ - loc = (loc >> 4 & 0xFFFFFF00) | (loc & 0xFF) | ((loc & 0xF00) << 16); - loc |= 0x80000000; - - outl(loc, 0xCF8); - - *Value = inl(0xCFC); -} - -void AmdMemPCIWrite(SBDFO loc, u32 *Value) -{ - /* Convert SBDFO into a CF8 Address */ - loc = (loc >> 4 & 0xFFFFFF00) | (loc & 0xFF) | ((loc & 0xF00) << 16); - loc |= 0x80000000; - - outl(loc, 0xCF8); - outl(*Value, 0xCFC); -} diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mutilc_d.c b/src/northbridge/amd/amdmct/mct_ddr3/mutilc_d.c deleted file mode 100644 index 0420b660b9..0000000000 --- a/src/northbridge/amd/amdmct/mct_ddr3/mutilc_d.c +++ /dev/null @@ -1,374 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2010 Advanced Micro Devices, Inc. - * Copyright (C) 2015 Timothy Pearson , Raptor Engineering - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -/* This file contains functions for common utility functions */ - -#include -#include - -#include "mct_d.h" -#include "mct_d_gcc.h" -#include "mwlc_d.h" - -static uint8_t is_fam15h(void) -{ - uint8_t fam15h = 0; - uint32_t family; - - family = cpuid_eax(0x80000001); - family = ((family & 0xf00000) >> 16) | ((family & 0xf00) >> 8); - - if (family >= 0x6f) - /* Family 15h or later */ - fam15h = 1; - - return fam15h; -} - -void AmdMemPCIReadBits(SBDFO loc, u8 highbit, u8 lowbit, u32 *pValue) -{ - /* ASSERT(highbit < 32 && lowbit < 32 && highbit >= lowbit && (loc & 3) == 0); */ - - AmdMemPCIRead(loc, pValue); - *pValue = *pValue >> lowbit; /* Shift */ - - /* A 1<<32 == 1<<0 due to x86 SHL instruction, so skip if that is the case */ - if ((highbit-lowbit) != 31) - *pValue &= (((u32)1 << (highbit-lowbit+1))-1); -} - -void AmdMemPCIWriteBits(SBDFO loc, u8 highbit, u8 lowbit, u32 *pValue) -{ - u32 temp, mask; - - /* ASSERT(highbit < 32 && lowbit < 32 && highbit >= lowbit && (loc & 3) == 0); */ - - /* A 1<<32 == 1<<0 due to x86 SHL instruction, so skip if that is the case */ - if ((highbit-lowbit) != 31) - mask = (((u32)1 << (highbit-lowbit+1))-1); - else - mask = (u32)0xFFFFFFFF; - - AmdMemPCIRead(loc, &temp); - temp &= ~(mask << lowbit); - temp |= (*pValue & mask) << lowbit; - AmdMemPCIWrite(loc, &temp); -} - -/*----------------------------------------------------------------------------- - * u32 bitTestSet(u32 csMask,u32 tempD) - * - * Description: - * This routine sets a bit in a u32 - * - * Parameters: - * IN csMask = Target value in which the bit will be set - * IN tempD = Bit that will be set - * OUT value = Target value with the bit set - *----------------------------------------------------------------------------- - */ -u32 bitTestSet(u32 csMask,u32 tempD) -{ - u32 localTemp; - /* ASSERT(tempD < 32); */ - localTemp = 1; - csMask |= localTemp << tempD; - return csMask; -} - -/*----------------------------------------------------------------------------- - * u32 bitTestReset(u32 csMask,u32 tempD) - * - * Description: - * This routine re-sets a bit in a u32 - * - * Parameters: - * IN csMask = Target value in which the bit will be re-set - * IN tempD = Bit that will be re-set - * OUT value = Target value with the bit re-set - *----------------------------------------------------------------------------- - */ -u32 bitTestReset(u32 csMask,u32 tempD) -{ - u32 temp, localTemp; - /* ASSERT(tempD < 32); */ - localTemp = 1; - temp = localTemp << tempD; - temp = ~temp; - csMask &= temp; - return csMask; -} - -/*----------------------------------------------------------------------------- - * u32 get_Bits(DCTStruct *DCTData, u8 DCT, u8 Node, u8 func, u16 offset, - * u8 low, u8 high) - * - * Description: - * This routine Gets the PCT bits from the specified Node, DCT and PCI address - * - * Parameters: - * IN OUT *DCTData - Pointer to buffer with information about each DCT - * IN DCT - DCT number - * - 1 indicates DCT 1 - * - 0 indicates DCT 0 - * - 2 both DCTs - * Node - Node number - * Func - PCI Function number - * Offset - PCI register number - * Low - Low bit of the bit field - * High - High bit of the bit field - * - * OUT value = Value read from PCI space - *----------------------------------------------------------------------------- - */ -u32 get_Bits(sDCTStruct *pDCTData, - u8 dct, u8 node, u8 func, - u16 offset, u8 low, u8 high) -{ - u32 temp; - uint32_t dword; - - /* ASSERT(node < MAX_NODES); */ - if (dct == BOTH_DCTS) - { - /* Registers exist on DCT0 only */ - if (is_fam15h()) - { - /* Select DCT 0 */ - AmdMemPCIRead(MAKE_SBDFO(0,0,24+node,1,0x10c), &dword); - dword &= ~0x1; - AmdMemPCIWrite(MAKE_SBDFO(0,0,24+node,1,0x10c), &dword); - } - - AmdMemPCIReadBits(MAKE_SBDFO(0,0,24+node,func,offset), high, low, &temp); - } - else - { - if (is_fam15h()) - { - /* Select DCT */ - AmdMemPCIRead(MAKE_SBDFO(0,0,24+node,1,0x10c), &dword); - dword &= ~0x1; - dword |= (dct & 0x1); - AmdMemPCIWrite(MAKE_SBDFO(0,0,24+node,1,0x10c), &dword); - - /* Read from the selected DCT */ - AmdMemPCIReadBits(MAKE_SBDFO(0,0,24+node,func,offset), high, low, &temp); - } - else - { - if (dct == 1) - { - /* Read from dct 1 */ - offset += 0x100; - AmdMemPCIReadBits(MAKE_SBDFO(0,0,24+node,func,offset), high, low, &temp); - } - else - { - /* Read from dct 0 */ - AmdMemPCIReadBits(MAKE_SBDFO(0,0,24+node,func,offset), high, low, &temp); - } - } - } - return temp; -} - -/*----------------------------------------------------------------------------- - * void set_Bits(DCTStruct *DCTData,u8 DCT,u8 Node,u8 func, u16 offset, - * u8 low, u8 high, u32 value) - * - * Description: - * This routine Sets the PCT bits from the specified Node, DCT and PCI address - * - * Parameters: - * IN OUT *DCTData - Pointer to buffer with information about each DCT - * IN DCT - DCT number - * - 1 indicates DCT 1 - * - 0 indicates DCT 0 - * - 2 both DCTs - * Node - Node number - * Func - PCI Function number - * Offset - PCI register number - * Low - Low bit of the bit field - * High - High bit of the bit field - * - * OUT - *----------------------------------------------------------------------------- - */ -void set_Bits(sDCTStruct *pDCTData, - u8 dct, u8 node, u8 func, - u16 offset, u8 low, u8 high, u32 value) -{ - u32 temp; - uint32_t dword; - - temp = value; - - if (dct == BOTH_DCTS) - { - /* Registers exist on DCT0 only */ - if (is_fam15h()) - { - /* Select DCT 0 */ - AmdMemPCIRead(MAKE_SBDFO(0,0,24+node,1,0x10c), &dword); - dword &= ~0x1; - AmdMemPCIWrite(MAKE_SBDFO(0,0,24+node,1,0x10c), &dword); - } - - AmdMemPCIWriteBits(MAKE_SBDFO(0,0,24+node,func,offset), high, low, &temp); - } - else - { - if (is_fam15h()) - { - /* Select DCT */ - AmdMemPCIRead(MAKE_SBDFO(0,0,24+node,1,0x10c), &dword); - dword &= ~0x1; - dword |= (dct & 0x1); - AmdMemPCIWrite(MAKE_SBDFO(0,0,24+node,1,0x10c), &dword); - - /* Write to the selected DCT */ - AmdMemPCIWriteBits(MAKE_SBDFO(0,0,24+node,func,offset), high, low, &temp); - } - else - { - if (dct == 1) - { - /* Write to dct 1 */ - offset += 0x100; - AmdMemPCIWriteBits(MAKE_SBDFO(0,0,24+node,func,offset), high, low, &temp); - } - else - { - /* Write to dct 0 */ - AmdMemPCIWriteBits(MAKE_SBDFO(0,0,24+node,func,offset), high, low, &temp); - } - } - } -} - -/*------------------------------------------------- - * u32 get_ADD_DCT_Bits(DCTStruct *DCTData,u8 DCT,u8 Node,u8 func, - * u16 offset,u8 low, u8 high) - * - * Description: - * This routine gets the Additional PCT register from Function 2 by specified - * Node, DCT and PCI address - * - * Parameters: - * IN OUT *DCTData - Pointer to buffer with information about each DCT - * IN DCT - DCT number - * - 1 indicates DCT 1 - * - 0 indicates DCT 0 - * - 2 both DCTs - * Node - Node number - * Func - PCI Function number - * Offset - Additional PCI register number - * Low - Low bit of the bit field - * High - High bit of the bit field - * - * OUT - *------------------------------------------------- - */ -u32 get_ADD_DCT_Bits(sDCTStruct *pDCTData, - u8 dct, u8 node, u8 func, - u16 offset, u8 low, u8 high) -{ - u32 tempD; - tempD = offset; - tempD = bitTestReset(tempD,DctAccessWrite); - set_Bits(pDCTData, dct, node, FUN_DCT, DRAM_CONTROLLER_ADD_DATA_OFFSET_REG, - PCI_MIN_LOW, PCI_MAX_HIGH, offset); - while ((get_Bits(pDCTData,dct, node, FUN_DCT, DRAM_CONTROLLER_ADD_DATA_OFFSET_REG, - DctAccessDone, DctAccessDone)) == 0); - return (get_Bits(pDCTData, dct, node, FUN_DCT, DRAM_CONTROLLER_ADD_DATA_PORT_REG, - low, high)); -} - -/*------------------------------------------------- - * void set_DCT_ADDR_Bits(DCTStruct *DCTData, u8 DCT,u8 Node,u8 func, - * u16 offset,u8 low, u8 high, u32 value) - * - * Description: - * This routine sets the Additional PCT register from Function 2 by specified - * Node, DCT and PCI address - * - * Parameters: - * IN OUT *DCTData - Pointer to buffer with information about each DCT - * IN DCT - DCT number - * - 1 indicates DCT 1 - * - 0 indicates DCT 0 - * - 2 both DCTs - * Node - Node number - * Func - PCI Function number - * Offset - Additional PCI register number - * Low - Low bit of the bit field - * High - High bit of the bit field - * - * OUT - *------------------------------------------------- - */ -void set_DCT_ADDR_Bits(sDCTStruct *pDCTData, - u8 dct, u8 node, u8 func, - u16 offset, u8 low, u8 high, u32 value) -{ - u32 tempD; - - set_Bits(pDCTData, dct, node, FUN_DCT, DRAM_CONTROLLER_ADD_DATA_OFFSET_REG, - PCI_MIN_LOW, PCI_MAX_HIGH, offset); - while ((get_Bits(pDCTData,dct, node, FUN_DCT, DRAM_CONTROLLER_ADD_DATA_OFFSET_REG, - DctAccessDone, DctAccessDone)) == 0); - - set_Bits(pDCTData, dct, node, FUN_DCT, DRAM_CONTROLLER_ADD_DATA_PORT_REG, - low, high, value); - tempD = offset; - tempD = bitTestSet(tempD,DctAccessWrite); - set_Bits(pDCTData, dct, node, FUN_DCT,DRAM_CONTROLLER_ADD_DATA_OFFSET_REG, - PCI_MIN_LOW, PCI_MAX_HIGH, tempD); - while ((get_Bits(pDCTData,dct, pDCTData->NodeId, FUN_DCT, - DRAM_CONTROLLER_ADD_DATA_OFFSET_REG, DctAccessDone, - DctAccessDone)) == 0); -} - -/*------------------------------------------------- - * BOOL bitTest(u32 value, u8 bitLoc) - * - * Description: - * This routine tests the value to determine if the bitLoc is set - * - * Parameters: - * IN Value - value to be tested - * bitLoc - bit location to be tested - * OUT TRUE - bit is set - * FALSE - bit is clear - *------------------------------------------------- - */ -BOOL bitTest(u32 value, u8 bitLoc) -{ - u32 tempD, compD; - tempD = value; - compD = 0; - compD = bitTestSet(compD,bitLoc); - tempD &= compD; - if (compD == tempD) - { - return TRUE; - } - else - { - return FALSE; - } -} diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mwlc_d.h b/src/northbridge/amd/amdmct/mct_ddr3/mwlc_d.h deleted file mode 100644 index aa0446f090..0000000000 --- a/src/northbridge/amd/amdmct/mct_ddr3/mwlc_d.h +++ /dev/null @@ -1,192 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2010 Advanced Micro Devices, Inc. - * Copyright (C) 2015 Timothy Pearson , Raptor Engineering - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ -/* IBV defined Structure */ /* IBV Specific Options */ -#ifndef MWLC_D_H -#define MWLC_D_H - -#include - -#define MAX_TOTAL_DIMMS 8 /* Maximum Number of DIMMs in systems */ - /* (DCT0 + DCT1) */ -#define MAX_DIMMS 4 /* Maximum Number of DIMMs on each DCT */ -#define MAX_LDIMMS 4 /* Maximum number of Logical DIMMs per DCT */ - -/*MCT Max variables */ -#define MAX_ERRORS 32 /* Maximum number of Errors Reported */ -#define MAX_STATUS 32 /* Maximum number of Status variables*/ -#define MAX_BYTE_LANES (8+1) /* Maximum number of Byte Lanes - include ECC */ - -#define C_MAX_DIMMS 4 /* Maximum Number of DIMMs on each DCT */ - -/* STATUS Definition */ -#define DCT_STATUS_REGISTERED 3 /* Registered DIMMs support */ -#define DCT_STATUS_LOAD_REDUCED 4 /* Load-Reduced DIMMs support */ -#define DCT_STATUS_OnDimmMirror 24 /* OnDimmMirror support */ - -/* PCI Definitions */ -#define FUN_HT 0 /* Function 0 Access */ -#define FUN_MAP 1 /* Function 1 Access */ -#define FUN_DCT 2 /* Function 2 Access */ -#define FUN_MISC 3 /* Function 3 Access */ -#define FUN_ADD_DCT 0xF /* Function 2 Additional Register Access */ -#define BOTH_DCTS 2 /* The access is independent of DCTs */ -#define PCI_MIN_LOW 0 /* Lowest possible PCI register location */ -#define PCI_MAX_HIGH 31 /* Highest possible PCI register location */ - -/*Function 2 */ -/* #define DRAM_INIT 0x7C */ -#define DRAM_MRS_REGISTER 0x84 -#define DRAM_CONFIG_HIGH 0x94 -#define DRAM_CONTROLLER_ADD_DATA_OFFSET_REG 0x98 -#define DRAM_CONTROLLER_ADD_DATA_PORT_REG 0x9C - -/*Function 2 Additional DRAM control registers */ -#define DRAM_ADD_DCT_PHY_CONTROL_REG 0x8 -#define DRAM_CONT_ADD_DQS_TIMING_CTRL_BL_01 0x30 -#define DRAM_CONT_ADD_DQS_TIMING_CTRL_BL_45 0x40 -#define DRAM_CONT_ADD_PHASE_REC_CTRL_LOW 0x50 -#define DRAM_CONT_ADD_PHASE_REC_CTRL_HIGH 0x51 -#define DRAM_CONT_ADD_ECC_PHASE_REC_CTRL 0x52 -#define DRAM_CONT_ADD_WRITE_LEV_ERROR_REG 0x53 - -/* CPU Register definitions */ - -/* Register Bit Location */ -#define DctAccessDone 31 -#define DctAccessWrite 30 -#define RDqsEn 12 -#define TrDimmSelStart 4 -#define TrDimmSelEnd 5 -#define WrLvTrMode 1 -#define TrNibbleSel 2 -#define WrLvOdtEn 12 -#define WrLvErrStart 0 -#define WrLvErrEnd 8 -#define SendMrsCmd 26 -#define Qoff 12 -#define MRS_Level 7 -#define MrsAddressStartFam10 0 -#define MrsAddressEndFam10 15 -#define MrsAddressStartFam15 0 -#define MrsAddressEndFam15 17 -#define MrsBankStartFam10 16 -#define MrsBankEndFam10 18 -#define MrsBankStartFam15 18 -#define MrsBankEndFam15 20 -#define MrsChipSelStartFam10 20 -#define MrsChipSelEndFam10 22 -#define MrsChipSelStartFam15 21 -#define MrsChipSelEndFam15 23 -#define ASR 18 -#define SRT 19 -#define DramTermDynStart 10 -#define DramTermDynEnd 11 -#define WrtLvTrMode 1 -#define TrNibbleSel 2 -#define TrDimmSelStart 4 -#define TrDimmSelEnd 5 -#define WrtLvTrEn 0 -#define DrvImpCtrlStart 2 -#define DrvImpCtrlEnd 3 -#define DramTermNbStart 7 -#define DramTermNbEnd 9 -#define onDimmMirror 3 - -typedef struct _sMCTStruct -{ - void (*AgesaDelay)(u32 delayval); /* IBV defined Delay Function */ -} __attribute__((packed, aligned(4))) sMCTStruct; - -/* DCT 0 and DCT 1 Data structure */ -typedef struct _sDCTStruct -{ - u8 NodeId; /* Node ID */ - u8 DctTrain; /* Current DCT being trained */ - u8 CurrDct; /* Current DCT number (0 or 1) */ - u8 DctCSPresent; /* Current DCT CS mapping */ - uint8_t WrDqsGrossDlyBaseOffset; - int32_t WLSeedGrossDelay[MAX_BYTE_LANES*MAX_LDIMMS]; /* Write Levelization Seed Gross Delay */ - /* per byte Lane Per Logical DIMM*/ - int32_t WLSeedFineDelay[MAX_BYTE_LANES*MAX_LDIMMS]; /* Write Levelization Seed Fine Delay */ - /* per byte Lane Per Logical DIMM*/ - int32_t WLSeedPreGrossDelay[MAX_BYTE_LANES*MAX_LDIMMS]; /* Write Levelization Seed Pre-Gross Delay */ - /* per byte Lane Per Logical DIMM*/ - uint8_t WLSeedPreGrossPrevNibble[MAX_BYTE_LANES*MAX_LDIMMS]; - uint8_t WLSeedGrossPrevNibble[MAX_BYTE_LANES*MAX_LDIMMS]; - uint8_t WLSeedFinePrevNibble[MAX_BYTE_LANES*MAX_LDIMMS]; - /* per byte Lane Per Logical DIMM*/ - u8 WLGrossDelay[MAX_BYTE_LANES*MAX_LDIMMS]; /* Write Levelization Gross Delay */ - /* per byte Lane Per Logical DIMM*/ - u8 WLFineDelay[MAX_BYTE_LANES*MAX_LDIMMS]; /* Write Levelization Fine Delay */ - /* per byte Lane Per Logical DIMM*/ - u8 WLGrossDelayFirstPass[MAX_BYTE_LANES*MAX_LDIMMS]; /* First-Pass Write Levelization Gross Delay */ - /* per byte Lane Per Logical DIMM*/ - u8 WLFineDelayFirstPass[MAX_BYTE_LANES*MAX_LDIMMS]; /* First-Pass Write Levelization Fine Delay */ - /* per byte Lane Per Logical DIMM*/ - u8 WLGrossDelayPrevPass[MAX_BYTE_LANES*MAX_LDIMMS]; /* Previous Pass Write Levelization Gross Delay */ - /* per byte Lane Per Logical DIMM*/ - u8 WLFineDelayPrevPass[MAX_BYTE_LANES*MAX_LDIMMS]; /* Previous Pass Write Levelization Fine Delay */ - /* per byte Lane Per Logical DIMM*/ - u8 WLGrossDelayFinalPass[MAX_BYTE_LANES*MAX_LDIMMS]; /* Final-Pass Write Levelization Gross Delay */ - /* per byte Lane Per Logical DIMM*/ - u8 WLFineDelayFinalPass[MAX_BYTE_LANES*MAX_LDIMMS]; /* Final-Pass Write Levelization Fine Delay */ - /* per byte Lane Per Logical DIMM*/ - int32_t WLCriticalGrossDelayFirstPass; - int32_t WLCriticalGrossDelayPrevPass; - int32_t WLCriticalGrossDelayFinalPass; - uint16_t WLPrevMemclkFreq[MAX_TOTAL_DIMMS]; - u16 RegMan1Present; - u8 DimmPresent[MAX_TOTAL_DIMMS];/* Indicates which DIMMs are present */ - /* from Total Number of DIMMs(per Node)*/ - u8 DimmX8Present[MAX_TOTAL_DIMMS]; /* Which DIMMs x8 devices */ - u8 Status[MAX_STATUS]; /* Status for DCT0 and 1 */ - u8 ErrCode[MAX_ERRORS]; /* Major Error codes for DCT0 and 1 */ - u8 ErrStatus[MAX_ERRORS]; /* Minor Error codes for DCT0 and 1 */ - u8 DimmValid[MAX_TOTAL_DIMMS]; /* Indicates which DIMMs are valid for */ - /* Total Number of DIMMs(per Node) */ - u8 WLTotalDelay[MAX_BYTE_LANES];/* Write Levelization Total Delay */ - /* per byte lane */ - u8 MaxDimmsInstalled; /* Max Dimms Installed for current DCT */ - u8 DimmRanks[MAX_TOTAL_DIMMS]; /* Total Number of Ranks(per Dimm) */ - uint64_t LogicalCPUID; - u8 WLPass; -} __attribute__((packed, aligned(4))) sDCTStruct; - -void set_DCT_ADDR_Bits(sDCTStruct *pDCTData, - u8 dct, u8 node, u8 func, - u16 offset, u8 low, u8 high, u32 value); -void AmdMemPCIWriteBits(SBDFO loc, u8 highbit, u8 lowbit, u32 *pValue); -u32 get_Bits(sDCTStruct *pDCTData, - u8 dct, u8 node, u8 func, - u16 offset, u8 low, u8 high); -void AmdMemPCIReadBits(SBDFO loc, u8 highbit, u8 lowbit, u32 *pValue); -u32 bitTestSet(u32 csMask,u32 tempD); -u32 bitTestReset(u32 csMask,u32 tempD); -void set_Bits(sDCTStruct *pDCTData, - u8 dct, u8 node, u8 func, - u16 offset, u8 low, u8 high, u32 value); -BOOL bitTest(u32 value, u8 bitLoc); -u32 RttNomNonTargetRegDimm (sMCTStruct *pMCTData, sDCTStruct *pDCTData, u8 dimm, BOOL wl, u8 MemClkFreq, u8 rank); -u32 RttNomTargetRegDimm (sMCTStruct *pMCTData, sDCTStruct *pDCTData, u8 dimm, BOOL wl, u8 MemClkFreq, u8 rank); -u32 RttWrRegDimm (sMCTStruct *pMCTData, sDCTStruct *pDCTData, u8 dimm, BOOL wl, u8 MemClkFreq, u8 rank); -u8 WrLvOdtRegDimm (sMCTStruct *pMCTData, sDCTStruct *pDCTData, u8 dimm); -u32 get_ADD_DCT_Bits(sDCTStruct *pDCTData, - u8 dct, u8 node, u8 func, - u16 offset, u8 low, u8 high); -void AmdMemPCIRead(SBDFO loc, u32 *Value); -void AmdMemPCIWrite(SBDFO loc, u32 *Value); - -#endif diff --git a/src/northbridge/amd/amdmct/mct_ddr3/s3utils.c b/src/northbridge/amd/amdmct/mct_ddr3/s3utils.c deleted file mode 100644 index 52032e9362..0000000000 --- a/src/northbridge/amd/amdmct/mct_ddr3/s3utils.c +++ /dev/null @@ -1,1237 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2015 Timothy Pearson , Raptor Engineering - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include "mct_d.h" -#include "mct_d_gcc.h" - -#include "s3utils.h" - -#define S3NV_FILE_NAME "s3nv" - -static uint8_t is_fam15h(void) -{ - uint8_t fam15h = 0; - uint32_t family; - - family = cpuid_eax(0x80000001); - family = ((family & 0xf00000) >> 16) | ((family & 0xf00) >> 8); - - if (family >= 0x6f) - /* Family 15h or later */ - fam15h = 1; - - return fam15h; -} - -static ssize_t get_s3nv_file_offset(void); - -ssize_t get_s3nv_file_offset(void) -{ - struct region_device s3nv_region; - struct cbfsf s3nv_cbfs_file; - if (cbfs_boot_locate(&s3nv_cbfs_file, S3NV_FILE_NAME, NULL)) { - printk(BIOS_DEBUG, "S3 state file not found in CBFS: %s\n", S3NV_FILE_NAME); - return -1; - } - cbfs_file_data(&s3nv_region, &s3nv_cbfs_file); - - return s3nv_region.region.offset; -} - -#if ENV_PCI_SIMPLE_DEVICE -static uint32_t read_config32_dct(pci_devfn_t dev, uint8_t node, uint8_t dct, - uint32_t reg) -#else -static uint32_t read_config32_dct(struct device *dev, uint8_t node, uint8_t dct, - uint32_t reg) -#endif -{ - if (is_fam15h()) { - uint32_t dword; -#if ENV_PCI_SIMPLE_DEVICE - pci_devfn_t dev_fn1 = PCI_DEV(0, 0x18 + node, 1); -#else - struct device *dev_fn1 = pcidev_on_root(0x18 + node, 1); -#endif - - /* Select DCT */ - dword = pci_read_config32(dev_fn1, 0x10c); - dword &= ~0x1; - dword |= (dct & 0x1); - pci_write_config32(dev_fn1, 0x10c, dword); - } else { - /* Apply offset */ - reg += dct * 0x100; - } - - return pci_read_config32(dev, reg); -} - -#if ENV_PCI_SIMPLE_DEVICE -static void write_config32_dct(pci_devfn_t dev, uint8_t node, uint8_t dct, - uint32_t reg, uint32_t value) -#else -static void write_config32_dct(struct device *dev, uint8_t node, uint8_t dct, - uint32_t reg, uint32_t value) -#endif -{ - if (is_fam15h()) { - uint32_t dword; -#if ENV_PCI_SIMPLE_DEVICE - pci_devfn_t dev_fn1 = PCI_DEV(0, 0x18 + node, 1); -#else - struct device *dev_fn1 = pcidev_on_root(0x18 + node, 1); -#endif - - /* Select DCT */ - dword = pci_read_config32(dev_fn1, 0x10c); - dword &= ~0x1; - dword |= (dct & 0x1); - pci_write_config32(dev_fn1, 0x10c, dword); - } else { - /* Apply offset */ - reg += dct * 0x100; - } - - pci_write_config32(dev, reg, value); -} - -#if ENV_PCI_SIMPLE_DEVICE -static uint32_t read_amd_dct_index_register(pci_devfn_t dev, - uint32_t index_ctl_reg, uint32_t index) -#else -static uint32_t read_amd_dct_index_register(struct device *dev, - uint32_t index_ctl_reg, uint32_t index) -#endif -{ - uint32_t dword; - - index &= ~(1 << 30); - pci_write_config32(dev, index_ctl_reg, index); - do { - dword = pci_read_config32(dev, index_ctl_reg); - } while (!(dword & (1 << 31))); - dword = pci_read_config32(dev, index_ctl_reg + 0x04); - - return dword; -} - -#if ENV_PCI_SIMPLE_DEVICE -static uint32_t read_amd_dct_index_register_dct(pci_devfn_t dev, uint8_t node, - uint8_t dct, uint32_t index_ctl_reg, uint32_t index) -#else -static uint32_t read_amd_dct_index_register_dct(struct device *dev, - uint8_t node, uint8_t dct, uint32_t index_ctl_reg, - uint32_t index) -#endif -{ - if (is_fam15h()) { - uint32_t dword; -#if ENV_PCI_SIMPLE_DEVICE - pci_devfn_t dev_fn1 = PCI_DEV(0, 0x18 + node, 1); -#else - struct device *dev_fn1 = pcidev_on_root(0x18 + node, 1); -#endif - - /* Select DCT */ - dword = pci_read_config32(dev_fn1, 0x10c); - dword &= ~0x1; - dword |= (dct & 0x1); - pci_write_config32(dev_fn1, 0x10c, dword); - } else { - /* Apply offset */ - index_ctl_reg += dct * 0x100; - } - - return read_amd_dct_index_register(dev, index_ctl_reg, index); -} - -/* Non-cryptographic 64-bit hash function taken from Stack Overflow: - * http://stackoverflow.com/a/13326345 - * Any 64-bit hash with sufficiently low collision potential - * could be used instead. - */ -void calculate_spd_hash(uint8_t *spd_data, uint64_t *spd_hash) -{ - const unsigned long long prime = 2654435789ULL; - uint16_t byte; - *spd_hash = 104395301; - - for (byte = 0; byte < 256; byte++) - *spd_hash += (spd_data[byte] * prime) ^ (*spd_hash >> 23); - - *spd_hash = *spd_hash ^ (*spd_hash << 37); -} - -uint16_t calculate_nvram_mct_hash(void) -{ - uint32_t nvram; - uint16_t ret; - - ret = 0; - if (get_option(&nvram, "max_mem_clock") == CB_SUCCESS) - ret |= nvram & 0xf; - if (get_option(&nvram, "minimum_memory_voltage") == CB_SUCCESS) - ret |= (nvram & 0x3) << 4; - if (get_option(&nvram, "ECC_memory") == CB_SUCCESS) - ret |= (nvram & 0x1) << 6; - if (get_option(&nvram, "ECC_redirection") == CB_SUCCESS) - ret |= (nvram & 0x1) << 7; - if (get_option(&nvram, "ecc_scrub_rate") == CB_SUCCESS) - ret |= (nvram & 0x1) << 8; - if (get_option(&nvram, "interleave_chip_selects") == CB_SUCCESS) - ret |= (nvram & 0x1) << 9; - if (get_option(&nvram, "interleave_nodes") == CB_SUCCESS) - ret |= (nvram & 0x1) << 10; - if (get_option(&nvram, "interleave_memory_channels") == CB_SUCCESS) - ret |= (nvram & 0x1) << 11; - if (get_option(&nvram, "cpu_c_states") == CB_SUCCESS) - ret |= (nvram & 0x1) << 12; - if (get_option(&nvram, "cpu_cc6_state") == CB_SUCCESS) - ret |= (nvram & 0x1) << 13; - - return ret; -} - -static struct amd_s3_persistent_data *map_s3nv_in_nvram(void) -{ - ssize_t s3nv_offset; - ssize_t s3nv_file_offset; - void *s3nv_cbfs_file_ptr; - struct amd_s3_persistent_data *persistent_data; - - /* Obtain CBFS file offset */ - s3nv_offset = get_s3nv_file_offset(); - if (s3nv_offset == -1) - return NULL; - - /* Align flash pointer to nearest boundary */ - s3nv_file_offset = s3nv_offset; - s3nv_offset &= ~(CONFIG_S3_DATA_SIZE-1); - s3nv_offset += CONFIG_S3_DATA_SIZE; - s3nv_file_offset = s3nv_offset - s3nv_file_offset; - - /* Map data structure in CBFS and restore settings */ - s3nv_cbfs_file_ptr = cbfs_boot_map_with_leak(S3NV_FILE_NAME, CBFS_TYPE_RAW, NULL); - if (!s3nv_cbfs_file_ptr) { - printk(BIOS_DEBUG, "S3 state file could not be mapped: %s\n", S3NV_FILE_NAME); - return NULL; - } - persistent_data = (s3nv_cbfs_file_ptr + s3nv_file_offset); - - return persistent_data; -} - -int8_t load_spd_hashes_from_nvram(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstat) -{ - struct amd_s3_persistent_data *persistent_data; - - persistent_data = map_s3nv_in_nvram(); - if (!persistent_data) - return -1; - - memcpy(pDCTstat->spd_data.nvram_spd_hash, persistent_data->node[pDCTstat->Node_ID].spd_hash, sizeof(pDCTstat->spd_data.nvram_spd_hash)); - memcpy(pDCTstat->spd_data.nvram_memclk, persistent_data->node[pDCTstat->Node_ID].memclk, sizeof(pDCTstat->spd_data.nvram_memclk)); - - pMCTstat->nvram_checksum = persistent_data->nvram_checksum; - - return 0; -} - -static uint64_t rdmsr_uint64_t(unsigned long index) { - msr_t msr = rdmsr(index); - return (((uint64_t)msr.hi) << 32) | ((uint64_t)msr.lo); -} - -static void wrmsr_uint64_t(unsigned long index, uint64_t value) -{ - msr_t msr; - msr.hi = (value & 0xffffffff00000000ULL) >> 32; - msr.lo = (value & 0xffffffff); - wrmsr(index, msr); -} - -static uint32_t read_config32_dct_nbpstate(struct device *dev, uint8_t node, - uint8_t dct, uint8_t nb_pstate, - uint32_t reg) -{ - uint32_t dword; - struct device *dev_fn1 = pcidev_on_root(0x18 + node, 1); - - /* Select DCT */ - dword = pci_read_config32(dev_fn1, 0x10c); - dword &= ~0x1; - dword |= (dct & 0x1); - pci_write_config32(dev_fn1, 0x10c, dword); - - /* Select NB Pstate index */ - dword = pci_read_config32(dev_fn1, 0x10c); - dword &= ~(0x3 << 4); - dword |= (nb_pstate & 0x3) << 4; - pci_write_config32(dev_fn1, 0x10c, dword); - - return pci_read_config32(dev, reg); -} - -static void copy_cbmem_spd_data_to_save_variable(struct amd_s3_persistent_data *persistent_data, uint8_t *restored) -{ - uint8_t node; - uint8_t dimm; - uint8_t channel; - struct amdmct_memory_info *mem_info; - mem_info = cbmem_find(CBMEM_ID_AMDMCT_MEMINFO); - if (mem_info == NULL) { - /* can't find amdmct information in cbmem */ - for (node = 0; node < MAX_NODES_SUPPORTED; node++) - for (dimm = 0; dimm < MAX_DIMMS_SUPPORTED; dimm++) - persistent_data->node[node].spd_hash[dimm] = 0xffffffffffffffffULL; - - return; - } - - for (node = 0; node < MAX_NODES_SUPPORTED; node++) - for (dimm = 0; dimm < MAX_DIMMS_SUPPORTED; dimm++) - calculate_spd_hash(mem_info->dct_stat[node].spd_data.spd_bytes[dimm], &persistent_data->node[node].spd_hash[dimm]); - - for (node = 0; node < MAX_NODES_SUPPORTED; node++) - for (channel = 0; channel < 2; channel++) - persistent_data->node[node].memclk[channel] = mem_info->dct_stat[node].Speed; - - persistent_data->nvram_checksum = calculate_nvram_mct_hash(); - - if (restored) { - if (mem_info->mct_stat.GStatus & (1 << GSB_ConfigRestored)) - *restored = 1; - else - *restored = 0; - } -} - -void copy_mct_data_to_save_variable(struct amd_s3_persistent_data *persistent_data) -{ - uint8_t i; - uint8_t j; - uint8_t node; - uint8_t channel; - - /* Zero out data structure */ - memset(persistent_data, 0, sizeof(struct amd_s3_persistent_data)); - - /* Load data from DCTs into data structure */ - for (node = 0; node < MAX_NODES_SUPPORTED; node++) { - struct device *dev_fn1 = pcidev_on_root(0x18 + node, 1); - struct device *dev_fn2 = pcidev_on_root(0x18 + node, 2); - struct device *dev_fn3 = pcidev_on_root(0x18 + node, 3); - /* Test for node presence */ - if ((!dev_fn1) || (pci_read_config32(dev_fn1, PCI_VENDOR_ID) == 0xffffffff)) { - persistent_data->node[node].node_present = 0; - continue; - } - persistent_data->node[node].node_present = 1; - - for (channel = 0; channel < 2; channel++) { - struct amd_s3_persistent_mct_channel_data *data = &persistent_data->node[node].channel[channel]; - - /* Stage 1 */ - data->f2x110 = pci_read_config32(dev_fn2, 0x110); - - /* Stage 2 */ - data->f1x40 = read_config32_dct(dev_fn1, node, channel, 0x40); - data->f1x44 = read_config32_dct(dev_fn1, node, channel, 0x44); - data->f1x48 = read_config32_dct(dev_fn1, node, channel, 0x48); - data->f1x4c = read_config32_dct(dev_fn1, node, channel, 0x4c); - data->f1x50 = read_config32_dct(dev_fn1, node, channel, 0x50); - data->f1x54 = read_config32_dct(dev_fn1, node, channel, 0x54); - data->f1x58 = read_config32_dct(dev_fn1, node, channel, 0x58); - data->f1x5c = read_config32_dct(dev_fn1, node, channel, 0x5c); - data->f1x60 = read_config32_dct(dev_fn1, node, channel, 0x60); - data->f1x64 = read_config32_dct(dev_fn1, node, channel, 0x64); - data->f1x68 = read_config32_dct(dev_fn1, node, channel, 0x68); - data->f1x6c = read_config32_dct(dev_fn1, node, channel, 0x6c); - data->f1x70 = read_config32_dct(dev_fn1, node, channel, 0x70); - data->f1x74 = read_config32_dct(dev_fn1, node, channel, 0x74); - data->f1x78 = read_config32_dct(dev_fn1, node, channel, 0x78); - data->f1x7c = read_config32_dct(dev_fn1, node, channel, 0x7c); - data->f1xf0 = pci_read_config32(dev_fn1, 0xf0); - data->f1x120 = pci_read_config32(dev_fn1, 0x120); - data->f1x124 = pci_read_config32(dev_fn1, 0x124); - data->f2x10c = pci_read_config32(dev_fn2, 0x10c); - data->f2x114 = pci_read_config32(dev_fn2, 0x114); - data->f2x118 = pci_read_config32(dev_fn2, 0x118); - data->f2x11c = pci_read_config32(dev_fn2, 0x11c); - data->f2x1b0 = pci_read_config32(dev_fn2, 0x1b0); - data->f3x44 = pci_read_config32(dev_fn3, 0x44); - for (i = 0; i < 16; i++) { - data->msr0000020[i] = - rdmsr_uint64_t(MTRR_PHYS_BASE(0) | i); - } - data->msr00000250 = rdmsr_uint64_t(MTRR_FIX_64K_00000); - data->msr00000258 = rdmsr_uint64_t(MTRR_FIX_16K_80000); - for (i = 0; i < 8; i++) - data->msr0000026[i] = rdmsr_uint64_t(0x00000260 | (i + 8)); - data->msr000002ff = rdmsr_uint64_t(MTRR_DEF_TYPE_MSR); - data->msrc0010010 = rdmsr_uint64_t(SYSCFG_MSR); - data->msrc001001a = rdmsr_uint64_t(TOP_MEM); - data->msrc001001d = rdmsr_uint64_t(TOP_MEM2); - data->msrc001001f = rdmsr_uint64_t(NB_CFG_MSR); - - /* Stage 3 */ - data->f2x40 = read_config32_dct(dev_fn2, node, channel, 0x40); - data->f2x44 = read_config32_dct(dev_fn2, node, channel, 0x44); - data->f2x48 = read_config32_dct(dev_fn2, node, channel, 0x48); - data->f2x4c = read_config32_dct(dev_fn2, node, channel, 0x4c); - data->f2x50 = read_config32_dct(dev_fn2, node, channel, 0x50); - data->f2x54 = read_config32_dct(dev_fn2, node, channel, 0x54); - data->f2x58 = read_config32_dct(dev_fn2, node, channel, 0x58); - data->f2x5c = read_config32_dct(dev_fn2, node, channel, 0x5c); - data->f2x60 = read_config32_dct(dev_fn2, node, channel, 0x60); - data->f2x64 = read_config32_dct(dev_fn2, node, channel, 0x64); - data->f2x68 = read_config32_dct(dev_fn2, node, channel, 0x68); - data->f2x6c = read_config32_dct(dev_fn2, node, channel, 0x6c); - data->f2x78 = read_config32_dct(dev_fn2, node, channel, 0x78); - data->f2x7c = read_config32_dct(dev_fn2, node, channel, 0x7c); - data->f2x80 = read_config32_dct(dev_fn2, node, channel, 0x80); - data->f2x84 = read_config32_dct(dev_fn2, node, channel, 0x84); - data->f2x88 = read_config32_dct(dev_fn2, node, channel, 0x88); - data->f2x8c = read_config32_dct(dev_fn2, node, channel, 0x8c); - data->f2x90 = read_config32_dct(dev_fn2, node, channel, 0x90); - data->f2xa4 = read_config32_dct(dev_fn2, node, channel, 0xa4); - data->f2xa8 = read_config32_dct(dev_fn2, node, channel, 0xa8); - - /* Family 15h-specific configuration */ - if (is_fam15h()) { - data->f2x200 = read_config32_dct(dev_fn2, node, channel, 0x200); - data->f2x204 = read_config32_dct(dev_fn2, node, channel, 0x204); - data->f2x208 = read_config32_dct(dev_fn2, node, channel, 0x208); - data->f2x20c = read_config32_dct(dev_fn2, node, channel, 0x20c); - for (i = 0; i < 4; i++) - data->f2x210[i] = read_config32_dct_nbpstate(dev_fn2, node, channel, i, 0x210); - data->f2x214 = read_config32_dct(dev_fn2, node, channel, 0x214); - data->f2x218 = read_config32_dct(dev_fn2, node, channel, 0x218); - data->f2x21c = read_config32_dct(dev_fn2, node, channel, 0x21c); - data->f2x22c = read_config32_dct(dev_fn2, node, channel, 0x22c); - data->f2x230 = read_config32_dct(dev_fn2, node, channel, 0x230); - data->f2x234 = read_config32_dct(dev_fn2, node, channel, 0x234); - data->f2x238 = read_config32_dct(dev_fn2, node, channel, 0x238); - data->f2x23c = read_config32_dct(dev_fn2, node, channel, 0x23c); - data->f2x240 = read_config32_dct(dev_fn2, node, channel, 0x240); - - data->f2x9cx0d0fe003 = read_amd_dct_index_register_dct(dev_fn2, node, channel, 0x98, 0x0d0fe003); - data->f2x9cx0d0fe013 = read_amd_dct_index_register_dct(dev_fn2, node, channel, 0x98, 0x0d0fe013); - for (i = 0; i < 9; i++) - data->f2x9cx0d0f0_8_0_1f[i] = read_amd_dct_index_register_dct(dev_fn2, node, channel, 0x98, 0x0d0f001f | (i << 8)); - data->f2x9cx0d0f201f = read_amd_dct_index_register_dct(dev_fn2, node, channel, 0x98, 0x0d0f201f); - data->f2x9cx0d0f211f = read_amd_dct_index_register_dct(dev_fn2, node, channel, 0x98, 0x0d0f211f); - data->f2x9cx0d0f221f = read_amd_dct_index_register_dct(dev_fn2, node, channel, 0x98, 0x0d0f221f); - data->f2x9cx0d0f801f = read_amd_dct_index_register_dct(dev_fn2, node, channel, 0x98, 0x0d0f801f); - data->f2x9cx0d0f811f = read_amd_dct_index_register_dct(dev_fn2, node, channel, 0x98, 0x0d0f811f); - data->f2x9cx0d0f821f = read_amd_dct_index_register_dct(dev_fn2, node, channel, 0x98, 0x0d0f821f); - data->f2x9cx0d0fc01f = read_amd_dct_index_register_dct(dev_fn2, node, channel, 0x98, 0x0d0fc01f); - data->f2x9cx0d0fc11f = read_amd_dct_index_register_dct(dev_fn2, node, channel, 0x98, 0x0d0fc11f); - data->f2x9cx0d0fc21f = read_amd_dct_index_register_dct(dev_fn2, node, channel, 0x98, 0x0d0fc21f); - data->f2x9cx0d0f4009 = read_amd_dct_index_register_dct(dev_fn2, node, channel, 0x98, 0x0d0f4009); - for (i = 0; i < 9; i++) - data->f2x9cx0d0f0_8_0_02[i] = read_amd_dct_index_register_dct(dev_fn2, node, channel, 0x98, 0x0d0f0002 | (i << 8)); - for (i = 0; i < 9; i++) - data->f2x9cx0d0f0_8_0_06[i] = read_amd_dct_index_register_dct(dev_fn2, node, channel, 0x98, 0x0d0f0006 | (i << 8)); - for (i = 0; i < 9; i++) - data->f2x9cx0d0f0_8_0_0a[i] = read_amd_dct_index_register_dct(dev_fn2, node, channel, 0x98, 0x0d0f000a | (i << 8)); - - data->f2x9cx0d0f2002 = read_amd_dct_index_register_dct(dev_fn2, node, channel, 0x98, 0x0d0f2002); - data->f2x9cx0d0f2102 = read_amd_dct_index_register_dct(dev_fn2, node, channel, 0x98, 0x0d0f2102); - data->f2x9cx0d0f2202 = read_amd_dct_index_register_dct(dev_fn2, node, channel, 0x98, 0x0d0f2202); - data->f2x9cx0d0f8002 = read_amd_dct_index_register_dct(dev_fn2, node, channel, 0x98, 0x0d0f8002); - data->f2x9cx0d0f8006 = read_amd_dct_index_register_dct(dev_fn2, node, channel, 0x98, 0x0d0f8006); - data->f2x9cx0d0f800a = read_amd_dct_index_register_dct(dev_fn2, node, channel, 0x98, 0x0d0f800a); - data->f2x9cx0d0f8102 = read_amd_dct_index_register_dct(dev_fn2, node, channel, 0x98, 0x0d0f8102); - data->f2x9cx0d0f8106 = read_amd_dct_index_register_dct(dev_fn2, node, channel, 0x98, 0x0d0f8106); - data->f2x9cx0d0f810a = read_amd_dct_index_register_dct(dev_fn2, node, channel, 0x98, 0x0d0f810a); - data->f2x9cx0d0fc002 = read_amd_dct_index_register_dct(dev_fn2, node, channel, 0x98, 0x0d0fc002); - data->f2x9cx0d0fc006 = read_amd_dct_index_register_dct(dev_fn2, node, channel, 0x98, 0x0d0fc006); - data->f2x9cx0d0fc00a = read_amd_dct_index_register_dct(dev_fn2, node, channel, 0x98, 0x0d0fc00a); - data->f2x9cx0d0fc00e = read_amd_dct_index_register_dct(dev_fn2, node, channel, 0x98, 0x0d0fc00e); - data->f2x9cx0d0fc012 = read_amd_dct_index_register_dct(dev_fn2, node, channel, 0x98, 0x0d0fc012); - - data->f2x9cx0d0f2031 = read_amd_dct_index_register_dct(dev_fn2, node, channel, 0x98, 0x0d0f2031); - data->f2x9cx0d0f2131 = read_amd_dct_index_register_dct(dev_fn2, node, channel, 0x98, 0x0d0f2131); - data->f2x9cx0d0f2231 = read_amd_dct_index_register_dct(dev_fn2, node, channel, 0x98, 0x0d0f2231); - data->f2x9cx0d0f8031 = read_amd_dct_index_register_dct(dev_fn2, node, channel, 0x98, 0x0d0f8031); - data->f2x9cx0d0f8131 = read_amd_dct_index_register_dct(dev_fn2, node, channel, 0x98, 0x0d0f8131); - data->f2x9cx0d0f8231 = read_amd_dct_index_register_dct(dev_fn2, node, channel, 0x98, 0x0d0f8231); - data->f2x9cx0d0fc031 = read_amd_dct_index_register_dct(dev_fn2, node, channel, 0x98, 0x0d0fc031); - data->f2x9cx0d0fc131 = read_amd_dct_index_register_dct(dev_fn2, node, channel, 0x98, 0x0d0fc131); - data->f2x9cx0d0fc231 = read_amd_dct_index_register_dct(dev_fn2, node, channel, 0x98, 0x0d0fc231); - for (i = 0; i < 9; i++) - data->f2x9cx0d0f0_0_f_31[i] = read_amd_dct_index_register_dct(dev_fn2, node, channel, 0x98, 0x0d0f0031 | (i << 8)); - - data->f2x9cx0d0f8021 = read_amd_dct_index_register_dct(dev_fn2, node, channel, 0x98, 0x0d0f8021); - - if (channel == 1) - data->f2x9cx0d0fe00a = read_amd_dct_index_register_dct(dev_fn2, node, channel, 0x98, 0x0d0fe00a); - } - - /* Stage 4 */ - data->f2x94 = read_config32_dct(dev_fn2, node, channel, 0x94); - - /* Stage 6 */ - for (i = 0; i < 9; i++) - for (j = 0; j < 3; j++) - data->f2x9cx0d0f0_f_8_0_0_8_4_0[i][j] = read_amd_dct_index_register_dct(dev_fn2, node, channel, 0x98, 0x0d0f0000 | (i << 8) | (j * 4)); - data->f2x9cx00 = read_amd_dct_index_register_dct(dev_fn2, node, channel, 0x98, 0x00); - data->f2x9cx0a = read_amd_dct_index_register_dct(dev_fn2, node, channel, 0x98, 0x0a); - data->f2x9cx0c = read_amd_dct_index_register_dct(dev_fn2, node, channel, 0x98, 0x0c); - - /* Stage 7 */ - data->f2x9cx04 = read_amd_dct_index_register_dct(dev_fn2, node, channel, 0x98, 0x04); - - /* Stage 9 */ - data->f2x9cx0d0fe006 = read_amd_dct_index_register_dct(dev_fn2, node, channel, 0x98, 0x0d0fe006); - data->f2x9cx0d0fe007 = read_amd_dct_index_register_dct(dev_fn2, node, channel, 0x98, 0x0d0fe007); - - /* Stage 10 */ - for (i = 0; i < 12; i++) - data->f2x9cx10[i] = read_amd_dct_index_register_dct(dev_fn2, node, channel, 0x98, 0x10 + i); - for (i = 0; i < 12; i++) - data->f2x9cx20[i] = read_amd_dct_index_register_dct(dev_fn2, node, channel, 0x98, 0x20 + i); - for (i = 0; i < 4; i++) - for (j = 0; j < 3; j++) - data->f2x9cx3_0_0_3_1[i][j] = read_amd_dct_index_register_dct(dev_fn2, node, channel, 0x98, (0x01 + i) + (0x100 * j)); - for (i = 0; i < 4; i++) - for (j = 0; j < 3; j++) - data->f2x9cx3_0_0_7_5[i][j] = read_amd_dct_index_register_dct(dev_fn2, node, channel, 0x98, (0x05 + i) + (0x100 * j)); - data->f2x9cx0d = read_amd_dct_index_register_dct(dev_fn2, node, channel, 0x98, 0x0d); - for (i = 0; i < 9; i++) - data->f2x9cx0d0f0_f_0_13[i] = read_amd_dct_index_register_dct(dev_fn2, node, channel, 0x98, 0x0d0f0013 | (i << 8)); - for (i = 0; i < 9; i++) - data->f2x9cx0d0f0_f_0_30[i] = read_amd_dct_index_register_dct(dev_fn2, node, channel, 0x98, 0x0d0f0030 | (i << 8)); - for (i = 0; i < 4; i++) - data->f2x9cx0d0f2_f_0_30[i] = read_amd_dct_index_register_dct(dev_fn2, node, channel, 0x98, 0x0d0f2030 | (i << 8)); - for (i = 0; i < 2; i++) - for (j = 0; j < 3; j++) - data->f2x9cx0d0f8_8_4_0[i][j] = read_amd_dct_index_register_dct(dev_fn2, node, channel, 0x98, 0x0d0f0000 | (i << 8) | (j * 4)); - data->f2x9cx0d0f812f = read_amd_dct_index_register_dct(dev_fn2, node, channel, 0x98, 0x0d0f812f); - - /* Stage 11 */ - if (CONFIG(DIMM_DDR3)) { - for (i = 0; i < 12; i++) - data->f2x9cx30[i] = read_amd_dct_index_register_dct(dev_fn2, node, channel, 0x98, 0x30 + i); - for (i = 0; i < 12; i++) - data->f2x9cx40[i] = read_amd_dct_index_register_dct(dev_fn2, node, channel, 0x98, 0x40 + i); - } - - /* Other */ - /* ECC scrub rate control */ - data->f3x58 = read_config32_dct(dev_fn3, node, 0, 0x58); - - /* ECC scrub location */ - write_config32_dct(dev_fn3, node, 0, 0x58, 0x0); /* Disable sequential scrub to work around non-atomic location read */ - data->f3x5c = read_config32_dct(dev_fn3, node, 0, 0x5c); - data->f3x60 = read_config32_dct(dev_fn3, node, 0, 0x60); - write_config32_dct(dev_fn3, node, 0, 0x58, data->f3x58); /* Re-enable sequential scrub */ - } - } -} - -static void write_config32_dct_nbpstate(pci_devfn_t dev, uint8_t node, - uint8_t dct, uint8_t nb_pstate, - uint32_t reg, uint32_t value) -{ - uint32_t dword; - pci_devfn_t dev_fn1 = PCI_DEV(0, 0x18 + node, 1); - - /* Select DCT */ - dword = pci_read_config32(dev_fn1, 0x10c); - dword &= ~0x1; - dword |= (dct & 0x1); - pci_write_config32(dev_fn1, 0x10c, dword); - - /* Select NB Pstate index */ - dword = pci_read_config32(dev_fn1, 0x10c); - dword &= ~(0x3 << 4); - dword |= (nb_pstate & 0x3) << 4; - pci_write_config32(dev_fn1, 0x10c, dword); - - pci_write_config32(dev, reg, value); -} - -static void write_amd_dct_index_register(pci_devfn_t dev, - uint32_t index_ctl_reg, uint32_t index, - uint32_t value) -{ - uint32_t dword; - - pci_write_config32(dev, index_ctl_reg + 0x04, value); - index |= (1 << 30); - pci_write_config32(dev, index_ctl_reg, index); - do { - dword = pci_read_config32(dev, index_ctl_reg); - } while (!(dword & (1 << 31))); -} - -static void write_amd_dct_index_register_dct(pci_devfn_t dev, uint8_t node, - uint8_t dct, - uint32_t index_ctl_reg, - uint32_t index, uint32_t value) -{ - if (is_fam15h()) { - uint32_t dword; - pci_devfn_t dev_fn1 = PCI_DEV(0, 0x18 + node, 1); - - /* Select DCT */ - dword = pci_read_config32(dev_fn1, 0x10c); - dword &= ~0x1; - dword |= (dct & 0x1); - pci_write_config32(dev_fn1, 0x10c, dword); - } else { - /* Apply offset */ - index_ctl_reg += dct * 0x100; - } - - return write_amd_dct_index_register(dev, index_ctl_reg, index, value); -} - -void restore_mct_data_from_save_variable(struct amd_s3_persistent_data *persistent_data, uint8_t training_only) -{ - uint8_t i; - uint8_t j; - uint8_t node; - uint8_t channel; - uint8_t ganged; - uint8_t dct_enabled; - uint32_t dword; - - if (training_only) { - /* Only restore the Receiver Enable and DQS training registers */ - for (node = 0; node < MAX_NODES_SUPPORTED; node++) { - for (channel = 0; channel < 2; channel++) { - struct amd_s3_persistent_mct_channel_data *data = &persistent_data->node[node].channel[channel]; - if (!persistent_data->node[node].node_present) - continue; - - /* Restore training parameters */ - for (i = 0; i < 4; i++) - for (j = 0; j < 3; j++) - write_amd_dct_index_register_dct(PCI_DEV(0, 0x18 + node, 2), node, channel, 0x98, (0x01 + i) + (0x100 * j), data->f2x9cx3_0_0_3_1[i][j]); - for (i = 0; i < 4; i++) - for (j = 0; j < 3; j++) - write_amd_dct_index_register_dct(PCI_DEV(0, 0x18 + node, 2), node, channel, 0x98, (0x05 + i) + (0x100 * j), data->f2x9cx3_0_0_7_5[i][j]); - - for (i = 0; i < 12; i++) - write_amd_dct_index_register_dct(PCI_DEV(0, 0x18 + node, 2), node, channel, 0x98, 0x10 + i, data->f2x9cx10[i]); - for (i = 0; i < 12; i++) - write_amd_dct_index_register_dct(PCI_DEV(0, 0x18 + node, 2), node, channel, 0x98, 0x20 + i, data->f2x9cx20[i]); - - if (CONFIG(DIMM_DDR3)) { - for (i = 0; i < 12; i++) - write_amd_dct_index_register_dct(PCI_DEV(0, 0x18 + node, 2), node, channel, 0x98, 0x30 + i, data->f2x9cx30[i]); - for (i = 0; i < 12; i++) - write_amd_dct_index_register_dct(PCI_DEV(0, 0x18 + node, 2), node, channel, 0x98, 0x40 + i, data->f2x9cx40[i]); - } - - /* Restore MaxRdLatency */ - if (is_fam15h()) { - for (i = 0; i < 4; i++) - write_config32_dct_nbpstate(PCI_DEV(0, 0x18 + node, 2), node, channel, i, 0x210, data->f2x210[i]); - } else { - write_config32_dct(PCI_DEV(0, 0x18 + node, 2), node, channel, 0x78, data->f2x78); - } - - /* Other timing control registers */ - write_config32_dct(PCI_DEV(0, 0x18 + node, 2), node, channel, 0x8c, data->f2x8c); - } - } - - return; - } - - /* Load data from data structure into DCTs */ - /* Stage 1 */ - for (node = 0; node < MAX_NODES_SUPPORTED; node++) { - for (channel = 0; channel < 2; channel++) { - struct amd_s3_persistent_mct_channel_data *data = &persistent_data->node[node].channel[channel]; - if (!persistent_data->node[node].node_present) - continue; - - pci_write_config32(PCI_DEV(0, 0x18 + node, 2), 0x110, data->f2x110); - } - } - - /* Stage 2 */ - for (node = 0; node < MAX_NODES_SUPPORTED; node++) { - for (channel = 0; channel < 2; channel++) { - struct amd_s3_persistent_mct_channel_data *data = &persistent_data->node[node].channel[channel]; - if (!persistent_data->node[node].node_present) - continue; - - write_config32_dct(PCI_DEV(0, 0x18 + node, 1), node, channel, 0x40, data->f1x40); - write_config32_dct(PCI_DEV(0, 0x18 + node, 1), node, channel, 0x44, data->f1x44); - write_config32_dct(PCI_DEV(0, 0x18 + node, 1), node, channel, 0x48, data->f1x48); - write_config32_dct(PCI_DEV(0, 0x18 + node, 1), node, channel, 0x4c, data->f1x4c); - write_config32_dct(PCI_DEV(0, 0x18 + node, 1), node, channel, 0x50, data->f1x50); - write_config32_dct(PCI_DEV(0, 0x18 + node, 1), node, channel, 0x54, data->f1x54); - write_config32_dct(PCI_DEV(0, 0x18 + node, 1), node, channel, 0x58, data->f1x58); - write_config32_dct(PCI_DEV(0, 0x18 + node, 1), node, channel, 0x5c, data->f1x5c); - write_config32_dct(PCI_DEV(0, 0x18 + node, 1), node, channel, 0x60, data->f1x60); - write_config32_dct(PCI_DEV(0, 0x18 + node, 1), node, channel, 0x64, data->f1x64); - write_config32_dct(PCI_DEV(0, 0x18 + node, 1), node, channel, 0x68, data->f1x68); - write_config32_dct(PCI_DEV(0, 0x18 + node, 1), node, channel, 0x6c, data->f1x6c); - write_config32_dct(PCI_DEV(0, 0x18 + node, 1), node, channel, 0x70, data->f1x70); - write_config32_dct(PCI_DEV(0, 0x18 + node, 1), node, channel, 0x74, data->f1x74); - write_config32_dct(PCI_DEV(0, 0x18 + node, 1), node, channel, 0x78, data->f1x78); - write_config32_dct(PCI_DEV(0, 0x18 + node, 1), node, channel, 0x7c, data->f1x7c); - write_config32_dct(PCI_DEV(0, 0x18 + node, 1), node, channel, 0xf0, data->f1xf0); - write_config32_dct(PCI_DEV(0, 0x18 + node, 1), node, channel, 0x120, data->f1x120); - write_config32_dct(PCI_DEV(0, 0x18 + node, 1), node, channel, 0x124, data->f1x124); - write_config32_dct(PCI_DEV(0, 0x18 + node, 2), node, channel, 0x10c, data->f2x10c); - write_config32_dct(PCI_DEV(0, 0x18 + node, 2), node, channel, 0x114, data->f2x114); - if (is_fam15h()) - /* Do not set LockDramCfg or CC6SaveEn at this time */ - write_config32_dct(PCI_DEV(0, 0x18 + node, 2), node, channel, 0x118, data->f2x118 & ~(0x3 << 18)); - else - write_config32_dct(PCI_DEV(0, 0x18 + node, 2), node, channel, 0x118, data->f2x118); - write_config32_dct(PCI_DEV(0, 0x18 + node, 2), node, channel, 0x11c, data->f2x11c); - write_config32_dct(PCI_DEV(0, 0x18 + node, 2), node, channel, 0x1b0, data->f2x1b0); - write_config32_dct(PCI_DEV(0, 0x18 + node, 3), node, channel, 0x44, data->f3x44); - for (i = 0; i < 16; i++) { - wrmsr_uint64_t(MTRR_PHYS_BASE(0) | i, - data->msr0000020[i]); - } - wrmsr_uint64_t(MTRR_FIX_64K_00000, data->msr00000250); - wrmsr_uint64_t(MTRR_FIX_16K_80000, data->msr00000258); - /* FIXME - * Restoring these MSRs causes a hang on resume due to - * destroying CAR while still executing from CAR! - * For now, skip restoration... - */ - // for (i = 0; i < 8; i++) - // wrmsr_uint64_t(0x00000260 | (i + 8), data->msr0000026[i]); - wrmsr_uint64_t(MTRR_DEF_TYPE_MSR, data->msr000002ff); - wrmsr_uint64_t(SYSCFG_MSR, data->msrc0010010); - wrmsr_uint64_t(TOP_MEM, data->msrc001001a); - wrmsr_uint64_t(TOP_MEM2, data->msrc001001d); - wrmsr_uint64_t(NB_CFG_MSR, data->msrc001001f); - } - } - - /* Stage 3 */ - for (node = 0; node < MAX_NODES_SUPPORTED; node++) { - for (channel = 0; channel < 2; channel++) { - struct amd_s3_persistent_mct_channel_data *data = &persistent_data->node[node].channel[channel]; - if (!persistent_data->node[node].node_present) - continue; - - if (is_fam15h()) - ganged = 0; - else - ganged = !!(data->f2x110 & 0x10); - if ((ganged == 1) && (channel > 0)) - continue; - - write_config32_dct(PCI_DEV(0, 0x18 + node, 2), node, channel, 0x40, data->f2x40); - write_config32_dct(PCI_DEV(0, 0x18 + node, 2), node, channel, 0x44, data->f2x44); - write_config32_dct(PCI_DEV(0, 0x18 + node, 2), node, channel, 0x48, data->f2x48); - write_config32_dct(PCI_DEV(0, 0x18 + node, 2), node, channel, 0x4c, data->f2x4c); - write_config32_dct(PCI_DEV(0, 0x18 + node, 2), node, channel, 0x50, data->f2x50); - write_config32_dct(PCI_DEV(0, 0x18 + node, 2), node, channel, 0x54, data->f2x54); - write_config32_dct(PCI_DEV(0, 0x18 + node, 2), node, channel, 0x58, data->f2x58); - write_config32_dct(PCI_DEV(0, 0x18 + node, 2), node, channel, 0x5c, data->f2x5c); - write_config32_dct(PCI_DEV(0, 0x18 + node, 2), node, channel, 0x60, data->f2x60); - write_config32_dct(PCI_DEV(0, 0x18 + node, 2), node, channel, 0x64, data->f2x64); - write_config32_dct(PCI_DEV(0, 0x18 + node, 2), node, channel, 0x68, data->f2x68); - write_config32_dct(PCI_DEV(0, 0x18 + node, 2), node, channel, 0x6c, data->f2x6c); - write_config32_dct(PCI_DEV(0, 0x18 + node, 2), node, channel, 0x78, data->f2x78); - write_config32_dct(PCI_DEV(0, 0x18 + node, 2), node, channel, 0x7c, data->f2x7c); - write_config32_dct(PCI_DEV(0, 0x18 + node, 2), node, channel, 0x80, data->f2x80); - write_config32_dct(PCI_DEV(0, 0x18 + node, 2), node, channel, 0x84, data->f2x84); - write_config32_dct(PCI_DEV(0, 0x18 + node, 2), node, channel, 0x88, data->f2x88); - write_config32_dct(PCI_DEV(0, 0x18 + node, 2), node, channel, 0x8c, data->f2x8c); - write_config32_dct(PCI_DEV(0, 0x18 + node, 2), node, channel, 0x90, data->f2x90); - write_config32_dct(PCI_DEV(0, 0x18 + node, 2), node, channel, 0xa4, data->f2xa4); - write_config32_dct(PCI_DEV(0, 0x18 + node, 2), node, channel, 0xa8, data->f2xa8); - } - } - - /* Family 15h-specific configuration */ - if (is_fam15h()) { - for (node = 0; node < MAX_NODES_SUPPORTED; node++) { - for (channel = 0; channel < 2; channel++) { - struct amd_s3_persistent_mct_channel_data *data = &persistent_data->node[node].channel[channel]; - if (!persistent_data->node[node].node_present) - continue; - - /* Initialize DCT */ - write_amd_dct_index_register_dct(PCI_DEV(0, 0x18 + node, 2), node, channel, 0x98, 0x0000000b, 0x80000000); - dword = read_amd_dct_index_register_dct(PCI_DEV(0, 0x18 + node, 2), node, channel, 0x98, 0x0d0fe013); - dword &= ~0xffff; - dword |= 0x118; - write_amd_dct_index_register_dct(PCI_DEV(0, 0x18 + node, 2), node, channel, 0x98, 0x0d0fe013, dword); - - /* Restore values */ - write_config32_dct(PCI_DEV(0, 0x18 + node, 2), node, channel, 0x200, data->f2x200); - write_config32_dct(PCI_DEV(0, 0x18 + node, 2), node, channel, 0x204, data->f2x204); - write_config32_dct(PCI_DEV(0, 0x18 + node, 2), node, channel, 0x208, data->f2x208); - write_config32_dct(PCI_DEV(0, 0x18 + node, 2), node, channel, 0x20c, data->f2x20c); - for (i = 0; i < 4; i++) - write_config32_dct_nbpstate(PCI_DEV(0, 0x18 + node, 2), node, channel, i, 0x210, data->f2x210[i]); - write_config32_dct(PCI_DEV(0, 0x18 + node, 2), node, channel, 0x214, data->f2x214); - write_config32_dct(PCI_DEV(0, 0x18 + node, 2), node, channel, 0x218, data->f2x218); - write_config32_dct(PCI_DEV(0, 0x18 + node, 2), node, channel, 0x21c, data->f2x21c); - write_config32_dct(PCI_DEV(0, 0x18 + node, 2), node, channel, 0x22c, data->f2x22c); - write_config32_dct(PCI_DEV(0, 0x18 + node, 2), node, channel, 0x230, data->f2x230); - write_config32_dct(PCI_DEV(0, 0x18 + node, 2), node, channel, 0x234, data->f2x234); - write_config32_dct(PCI_DEV(0, 0x18 + node, 2), node, channel, 0x238, data->f2x238); - write_config32_dct(PCI_DEV(0, 0x18 + node, 2), node, channel, 0x23c, data->f2x23c); - write_config32_dct(PCI_DEV(0, 0x18 + node, 2), node, channel, 0x240, data->f2x240); - - write_amd_dct_index_register_dct(PCI_DEV(0, 0x18 + node, 2), node, channel, 0x98, 0x0d0fe013, data->f2x9cx0d0fe013); - for (i = 0; i < 9; i++) - write_amd_dct_index_register_dct(PCI_DEV(0, 0x18 + node, 2), node, channel, 0x98, 0x0d0f001f | (i << 8), data->f2x9cx0d0f0_8_0_1f[i]); - write_amd_dct_index_register_dct(PCI_DEV(0, 0x18 + node, 2), node, channel, 0x98, 0x0d0f201f, data->f2x9cx0d0f201f); - write_amd_dct_index_register_dct(PCI_DEV(0, 0x18 + node, 2), node, channel, 0x98, 0x0d0f211f, data->f2x9cx0d0f211f); - write_amd_dct_index_register_dct(PCI_DEV(0, 0x18 + node, 2), node, channel, 0x98, 0x0d0f221f, data->f2x9cx0d0f221f); - write_amd_dct_index_register_dct(PCI_DEV(0, 0x18 + node, 2), node, channel, 0x98, 0x0d0f801f, data->f2x9cx0d0f801f); - write_amd_dct_index_register_dct(PCI_DEV(0, 0x18 + node, 2), node, channel, 0x98, 0x0d0f811f, data->f2x9cx0d0f811f); - write_amd_dct_index_register_dct(PCI_DEV(0, 0x18 + node, 2), node, channel, 0x98, 0x0d0f821f, data->f2x9cx0d0f821f); - write_amd_dct_index_register_dct(PCI_DEV(0, 0x18 + node, 2), node, channel, 0x98, 0x0d0fc01f, data->f2x9cx0d0fc01f); - write_amd_dct_index_register_dct(PCI_DEV(0, 0x18 + node, 2), node, channel, 0x98, 0x0d0fc11f, data->f2x9cx0d0fc11f); - write_amd_dct_index_register_dct(PCI_DEV(0, 0x18 + node, 2), node, channel, 0x98, 0x0d0fc21f, data->f2x9cx0d0fc21f); - write_amd_dct_index_register_dct(PCI_DEV(0, 0x18 + node, 2), node, channel, 0x98, 0x0d0f4009, data->f2x9cx0d0f4009); - - write_amd_dct_index_register_dct(PCI_DEV(0, 0x18 + node, 2), node, channel, 0x98, 0x0d0f2031, data->f2x9cx0d0f2031); - write_amd_dct_index_register_dct(PCI_DEV(0, 0x18 + node, 2), node, channel, 0x98, 0x0d0f2131, data->f2x9cx0d0f2131); - write_amd_dct_index_register_dct(PCI_DEV(0, 0x18 + node, 2), node, channel, 0x98, 0x0d0f2231, data->f2x9cx0d0f2231); - write_amd_dct_index_register_dct(PCI_DEV(0, 0x18 + node, 2), node, channel, 0x98, 0x0d0f8031, data->f2x9cx0d0f8031); - write_amd_dct_index_register_dct(PCI_DEV(0, 0x18 + node, 2), node, channel, 0x98, 0x0d0f8131, data->f2x9cx0d0f8131); - write_amd_dct_index_register_dct(PCI_DEV(0, 0x18 + node, 2), node, channel, 0x98, 0x0d0f8231, data->f2x9cx0d0f8231); - write_amd_dct_index_register_dct(PCI_DEV(0, 0x18 + node, 2), node, channel, 0x98, 0x0d0fc031, data->f2x9cx0d0fc031); - write_amd_dct_index_register_dct(PCI_DEV(0, 0x18 + node, 2), node, channel, 0x98, 0x0d0fc131, data->f2x9cx0d0fc131); - write_amd_dct_index_register_dct(PCI_DEV(0, 0x18 + node, 2), node, channel, 0x98, 0x0d0fc231, data->f2x9cx0d0fc231); - for (i = 0; i < 9; i++) - write_amd_dct_index_register_dct(PCI_DEV(0, 0x18 + node, 2), node, channel, 0x98, 0x0d0f0031 | (i << 8), data->f2x9cx0d0f0_0_f_31[i]); - - write_amd_dct_index_register_dct(PCI_DEV(0, 0x18 + node, 2), node, channel, 0x98, 0x0d0f8021, data->f2x9cx0d0f8021); - - if (channel == 1) - write_amd_dct_index_register_dct(PCI_DEV(0, 0x18 + node, 2), node, channel, 0x98, 0x0d0fe00a, data->f2x9cx0d0fe00a); - } - } - } - - /* Stage 4 */ - for (node = 0; node < MAX_NODES_SUPPORTED; node++) { - for (channel = 0; channel < 2; channel++) { - struct amd_s3_persistent_mct_channel_data *data = &persistent_data->node[node].channel[channel]; - if (!persistent_data->node[node].node_present) - continue; - - if (is_fam15h()) - ganged = 0; - else - ganged = !!(data->f2x110 & 0x10); - if ((ganged == 1) && (channel > 0)) - continue; - - if (is_fam15h()) { - /* Program PllLockTime = 0x190 */ - dword = read_amd_dct_index_register_dct(PCI_DEV(0, 0x18 + node, 2), node, channel, 0x98, 0x0d0fe006); - dword &= ~0xffff; - dword |= 0x190; - write_amd_dct_index_register_dct(PCI_DEV(0, 0x18 + node, 2), node, channel, 0x98, 0x0d0fe006, dword); - - /* Program MemClkFreqVal = 0 */ - dword = read_config32_dct(PCI_DEV(0, 0x18 + node, 2), node, channel, 0x94); - dword &= (0x1 << 7); - write_config32_dct(PCI_DEV(0, 0x18 + node, 2), node, channel, 0x94, dword); - - /* Restore DRAM Address/Timing Control Register */ - write_amd_dct_index_register_dct(PCI_DEV(0, 0x18 + node, 2), node, channel, 0x98, 0x04, data->f2x9cx04); - } else { - /* Disable PHY auto-compensation engine */ - dword = read_amd_dct_index_register_dct(PCI_DEV(0, 0x18 + node, 2), node, channel, 0x98, 0x08); - if (!(dword & (1 << 30))) { - dword |= (1 << 30); - write_amd_dct_index_register_dct(PCI_DEV(0, 0x18 + node, 2), node, channel, 0x98, 0x08, dword); - - /* Wait for 5us */ - mct_Wait(100); - } - } - - /* Restore DRAM Configuration High Register */ - write_config32_dct(PCI_DEV(0, 0x18 + node, 2), node, channel, 0x94, data->f2x94); - } - } - - /* Stage 5 */ - for (node = 0; node < MAX_NODES_SUPPORTED; node++) { - for (channel = 0; channel < 2; channel++) { - struct amd_s3_persistent_mct_channel_data *data = &persistent_data->node[node].channel[channel]; - if (!persistent_data->node[node].node_present) - continue; - - if (is_fam15h()) - ganged = 0; - else - ganged = !!(data->f2x110 & 0x10); - if ((ganged == 1) && (channel > 0)) - continue; - - dct_enabled = !(data->f2x94 & (1 << 14)); - if (!dct_enabled) - continue; - - /* Wait for any pending PHY frequency changes to complete */ - do { - dword = read_config32_dct(PCI_DEV(0, 0x18 + node, 2), node, channel, 0x94); - } while (dword & (1 << 21)); - - if (is_fam15h()) { - /* Program PllLockTime = 0xf */ - dword = read_amd_dct_index_register_dct(PCI_DEV(0, 0x18 + node, 2), node, channel, 0x98, 0x0d0fe006); - dword &= ~0xffff; - dword |= 0xf; - write_amd_dct_index_register_dct(PCI_DEV(0, 0x18 + node, 2), node, channel, 0x98, 0x0d0fe006, dword); - } else { - /* Enable PHY auto-compensation engine */ - dword = read_amd_dct_index_register_dct(PCI_DEV(0, 0x18 + node, 2), node, channel, 0x98, 0x08); - dword &= ~(1 << 30); - write_amd_dct_index_register_dct(PCI_DEV(0, 0x18 + node, 2), node, channel, 0x98, 0x08, dword); - } - } - } - - /* Wait for 750us */ - mct_Wait(15000); - - /* Stage 6 */ - for (node = 0; node < MAX_NODES_SUPPORTED; node++) { - for (channel = 0; channel < 2; channel++) { - struct amd_s3_persistent_mct_channel_data *data = &persistent_data->node[node].channel[channel]; - if (!persistent_data->node[node].node_present) - continue; - - for (i = 0; i < 9; i++) - for (j = 0; j < 3; j++) - write_amd_dct_index_register_dct(PCI_DEV(0, 0x18 + node, 2), node, channel, 0x98, 0x0d0f0000 | (i << 8) | (j * 4), data->f2x9cx0d0f0_f_8_0_0_8_4_0[i][j]); - write_amd_dct_index_register_dct(PCI_DEV(0, 0x18 + node, 2), node, channel, 0x98, 0x00, data->f2x9cx00); - write_amd_dct_index_register_dct(PCI_DEV(0, 0x18 + node, 2), node, channel, 0x98, 0x0a, data->f2x9cx0a); - write_amd_dct_index_register_dct(PCI_DEV(0, 0x18 + node, 2), node, channel, 0x98, 0x0c, data->f2x9cx0c); - } - } - - /* Family 15h-specific configuration */ - if (is_fam15h()) { - for (node = 0; node < MAX_NODES_SUPPORTED; node++) { - for (channel = 0; channel < 2; channel++) { - struct amd_s3_persistent_mct_channel_data *data = &persistent_data->node[node].channel[channel]; - if (!persistent_data->node[node].node_present) - continue; - - dword = read_amd_dct_index_register_dct(PCI_DEV(0, 0x18 + node, 2), node, channel, 0x98, 0x0d0fe003); - dword |= (0x3 << 13); /* DisAutoComp, DisablePredriverCal = 1 */ - write_amd_dct_index_register_dct(PCI_DEV(0, 0x18 + node, 2), node, channel, 0x98, 0x0d0fe003, dword); - - for (i = 0; i < 9; i++) - write_amd_dct_index_register_dct(PCI_DEV(0, 0x18 + node, 2), node, channel, 0x98, 0x0d0f0006 | (i << 8), data->f2x9cx0d0f0_8_0_06[i]); - for (i = 0; i < 9; i++) - write_amd_dct_index_register_dct(PCI_DEV(0, 0x18 + node, 2), node, channel, 0x98, 0x0d0f000a | (i << 8), data->f2x9cx0d0f0_8_0_0a[i]); - for (i = 0; i < 9; i++) - write_amd_dct_index_register_dct(PCI_DEV(0, 0x18 + node, 2), node, channel, 0x98, 0x0d0f0002 | (i << 8), (0x8000 | data->f2x9cx0d0f0_8_0_02[i])); - - write_amd_dct_index_register_dct(PCI_DEV(0, 0x18 + node, 2), node, channel, 0x98, 0x0d0f8006, data->f2x9cx0d0f8006); - write_amd_dct_index_register_dct(PCI_DEV(0, 0x18 + node, 2), node, channel, 0x98, 0x0d0f800a, data->f2x9cx0d0f800a); - write_amd_dct_index_register_dct(PCI_DEV(0, 0x18 + node, 2), node, channel, 0x98, 0x0d0f8106, data->f2x9cx0d0f8106); - write_amd_dct_index_register_dct(PCI_DEV(0, 0x18 + node, 2), node, channel, 0x98, 0x0d0f810a, data->f2x9cx0d0f810a); - write_amd_dct_index_register_dct(PCI_DEV(0, 0x18 + node, 2), node, channel, 0x98, 0x0d0fc006, data->f2x9cx0d0fc006); - write_amd_dct_index_register_dct(PCI_DEV(0, 0x18 + node, 2), node, channel, 0x98, 0x0d0fc00a, data->f2x9cx0d0fc00a); - write_amd_dct_index_register_dct(PCI_DEV(0, 0x18 + node, 2), node, channel, 0x98, 0x0d0fc00e, data->f2x9cx0d0fc00e); - write_amd_dct_index_register_dct(PCI_DEV(0, 0x18 + node, 2), node, channel, 0x98, 0x0d0fc012, data->f2x9cx0d0fc012); - write_amd_dct_index_register_dct(PCI_DEV(0, 0x18 + node, 2), node, channel, 0x98, 0x0d0f8002, (0x8000 | data->f2x9cx0d0f8002)); - write_amd_dct_index_register_dct(PCI_DEV(0, 0x18 + node, 2), node, channel, 0x98, 0x0d0f8102, (0x8000 | data->f2x9cx0d0f8102)); - write_amd_dct_index_register_dct(PCI_DEV(0, 0x18 + node, 2), node, channel, 0x98, 0x0d0fc002, (0x8000 | data->f2x9cx0d0fc002)); - write_amd_dct_index_register_dct(PCI_DEV(0, 0x18 + node, 2), node, channel, 0x98, 0x0d0f2002, (0x8000 | data->f2x9cx0d0f2002)); - write_amd_dct_index_register_dct(PCI_DEV(0, 0x18 + node, 2), node, channel, 0x98, 0x0d0f2102, (0x8000 | data->f2x9cx0d0f2102)); - write_amd_dct_index_register_dct(PCI_DEV(0, 0x18 + node, 2), node, channel, 0x98, 0x0d0f2202, (0x8000 | data->f2x9cx0d0f2202)); - - write_amd_dct_index_register_dct(PCI_DEV(0, 0x18 + node, 2), node, channel, 0x98, 0x0d0fe003, data->f2x9cx0d0fe003); - } - } - } - - /* Stage 7 */ - for (node = 0; node < MAX_NODES_SUPPORTED; node++) { - for (channel = 0; channel < 2; channel++) { - struct amd_s3_persistent_mct_channel_data *data = &persistent_data->node[node].channel[channel]; - if (!persistent_data->node[node].node_present) - continue; - - if (is_fam15h()) - ganged = 0; - else - ganged = !!(data->f2x110 & 0x10); - if ((ganged == 1) && (channel > 0)) - continue; - - if (!is_fam15h()) - write_amd_dct_index_register_dct(PCI_DEV(0, 0x18 + node, 2), node, channel, 0x98, 0x04, data->f2x9cx04); - } - } - - /* Stage 8 */ - for (node = 0; node < MAX_NODES_SUPPORTED; node++) { - for (channel = 0; channel < 2; channel++) { - struct amd_s3_persistent_mct_channel_data *data = &persistent_data->node[node].channel[channel]; - if (!persistent_data->node[node].node_present) - continue; - - dct_enabled = !(data->f2x94 & (1 << 14)); - if (!dct_enabled) - continue; - - if (is_fam15h()) - ganged = 0; - else - ganged = !!(data->f2x110 & 0x10); - if ((ganged == 1) && (channel > 0)) - continue; - - printk(BIOS_SPEW, "Taking DIMMs out of self refresh node: %d channel: %d\n", node, channel); - - /* Exit self refresh mode */ - dword = read_config32_dct(PCI_DEV(0, 0x18 + node, 2), node, channel, 0x90); - dword |= (1 << 1); - write_config32_dct(PCI_DEV(0, 0x18 + node, 2), node, channel, 0x90, dword); - } - } - - /* Stage 9 */ - for (node = 0; node < MAX_NODES_SUPPORTED; node++) { - for (channel = 0; channel < 2; channel++) { - struct amd_s3_persistent_mct_channel_data *data = &persistent_data->node[node].channel[channel]; - if (!persistent_data->node[node].node_present) - continue; - - dct_enabled = !(data->f2x94 & (1 << 14)); - if (!dct_enabled) - continue; - - printk(BIOS_SPEW, "Waiting for DIMMs to exit self refresh node: %d channel: %d\n", node, channel); - - /* Wait for transition from self refresh mode to complete */ - do { - dword = read_config32_dct(PCI_DEV(0, 0x18 + node, 2), node, channel, 0x90); - } while (dword & (1 << 1)); - - /* Restore registers */ - write_amd_dct_index_register_dct(PCI_DEV(0, 0x18 + node, 2), node, channel, 0x98, 0x0d0fe006, data->f2x9cx0d0fe006); - write_amd_dct_index_register_dct(PCI_DEV(0, 0x18 + node, 2), node, channel, 0x98, 0x0d0fe007, data->f2x9cx0d0fe007); - } - } - - /* Stage 10 */ - for (node = 0; node < MAX_NODES_SUPPORTED; node++) { - for (channel = 0; channel < 2; channel++) { - struct amd_s3_persistent_mct_channel_data *data = &persistent_data->node[node].channel[channel]; - if (!persistent_data->node[node].node_present) - continue; - - for (i = 0; i < 12; i++) - write_amd_dct_index_register_dct(PCI_DEV(0, 0x18 + node, 2), node, channel, 0x98, 0x10 + i, data->f2x9cx10[i]); - for (i = 0; i < 12; i++) - write_amd_dct_index_register_dct(PCI_DEV(0, 0x18 + node, 2), node, channel, 0x98, 0x20 + i, data->f2x9cx20[i]); - for (i = 0; i < 4; i++) - for (j = 0; j < 3; j++) - write_amd_dct_index_register_dct(PCI_DEV(0, 0x18 + node, 2), node, channel, 0x98, (0x01 + i) + (0x100 * j), data->f2x9cx3_0_0_3_1[i][j]); - for (i = 0; i < 4; i++) - for (j = 0; j < 3; j++) - write_amd_dct_index_register_dct(PCI_DEV(0, 0x18 + node, 2), node, channel, 0x98, (0x05 + i) + (0x100 * j), data->f2x9cx3_0_0_7_5[i][j]); - write_amd_dct_index_register_dct(PCI_DEV(0, 0x18 + node, 2), node, channel, 0x98, 0x0d, data->f2x9cx0d); - for (i = 0; i < 9; i++) - write_amd_dct_index_register_dct(PCI_DEV(0, 0x18 + node, 2), node, channel, 0x98, 0x0d0f0013 | (i << 8), data->f2x9cx0d0f0_f_0_13[i]); - for (i = 0; i < 9; i++) - write_amd_dct_index_register_dct(PCI_DEV(0, 0x18 + node, 2), node, channel, 0x98, 0x0d0f0030 | (i << 8), data->f2x9cx0d0f0_f_0_30[i]); - for (i = 0; i < 4; i++) - write_amd_dct_index_register_dct(PCI_DEV(0, 0x18 + node, 2), node, channel, 0x98, 0x0d0f2030 | (i << 8), data->f2x9cx0d0f2_f_0_30[i]); - for (i = 0; i < 2; i++) - for (j = 0; j < 3; j++) - write_amd_dct_index_register_dct(PCI_DEV(0, 0x18 + node, 2), node, channel, 0x98, 0x0d0f0000 | (i << 8) | (j * 4), data->f2x9cx0d0f8_8_4_0[i][j]); - write_amd_dct_index_register_dct(PCI_DEV(0, 0x18 + node, 2), node, channel, 0x98, 0x0d0f812f, data->f2x9cx0d0f812f); - } - } - - /* Stage 11 */ - if (CONFIG(DIMM_DDR3)) { - for (node = 0; node < MAX_NODES_SUPPORTED; node++) { - for (channel = 0; channel < 2; channel++) { - struct amd_s3_persistent_mct_channel_data *data = &persistent_data->node[node].channel[channel]; - if (!persistent_data->node[node].node_present) - continue; - - for (i = 0; i < 12; i++) - write_amd_dct_index_register_dct(PCI_DEV(0, 0x18 + node, 2), node, channel, 0x98, 0x30 + i, data->f2x9cx30[i]); - for (i = 0; i < 12; i++) - write_amd_dct_index_register_dct(PCI_DEV(0, 0x18 + node, 2), node, channel, 0x98, 0x40 + i, data->f2x9cx40[i]); - } - } - } - - /* Other */ - for (node = 0; node < MAX_NODES_SUPPORTED; node++) { - for (channel = 0; channel < 2; channel++) { - struct amd_s3_persistent_mct_channel_data *data = &persistent_data->node[node].channel[channel]; - if (!persistent_data->node[node].node_present) - continue; - - /* ECC scrub location */ - write_config32_dct(PCI_DEV(0, 0x18 + node, 3), node, 0, 0x5c, data->f3x5c); - write_config32_dct(PCI_DEV(0, 0x18 + node, 3), node, 0, 0x60, data->f3x60); - - /* ECC scrub rate control */ - write_config32_dct(PCI_DEV(0, 0x18 + node, 3), node, 0, 0x58, data->f3x58); - - if (is_fam15h()) - /* Set LockDramCfg and CC6SaveEn */ - write_config32_dct(PCI_DEV(0, 0x18 + node, 2), node, channel, 0x118, data->f2x118); - } - } -} - -int8_t save_mct_information_to_nvram(void) -{ - uint8_t nvram; - uint8_t restored = 0; - - if (acpi_is_wakeup_s3()) - return 0; - - printk(BIOS_DEBUG, "Writing AMD DCT configuration to Flash\n"); - - struct spi_flash flash; - ssize_t s3nv_offset; - struct amd_s3_persistent_data *persistent_data; - - /* Allocate temporary data structures */ - persistent_data = malloc(sizeof(struct amd_s3_persistent_data)); - if (!persistent_data) { - printk(BIOS_DEBUG, "Could not allocate S3 data structure in RAM\n"); - return -1; - } - - /* Obtain MCT configuration data */ - copy_mct_data_to_save_variable(persistent_data); - - /* Save RAM SPD data at the same time */ - copy_cbmem_spd_data_to_save_variable(persistent_data, &restored); - - if (restored) { - /* Allow training bypass if DIMM configuration is unchanged on next boot */ - nvram = 1; - set_option("allow_spd_nvram_cache_restore", &nvram); - - printk(BIOS_DEBUG, "Hardware configuration unchanged since last boot; skipping write\n"); - free(persistent_data); - return 0; - } - - /* Obtain CBFS file offset */ - s3nv_offset = get_s3nv_file_offset(); - if (s3nv_offset == -1) { - free(persistent_data); - return -1; - } - - /* Align flash pointer to nearest boundary */ - s3nv_offset &= ~(CONFIG_S3_DATA_SIZE-1); - s3nv_offset += CONFIG_S3_DATA_SIZE; - - /* Initialize SPI and detect devices */ - spi_init(); - if (spi_flash_probe(0, 0, &flash)) { - printk(BIOS_DEBUG, "Could not find SPI device\n"); - return -1; - } - - spi_flash_volatile_group_begin(&flash); - - /* Erase and write data structure */ - spi_flash_erase(&flash, s3nv_offset, CONFIG_S3_DATA_SIZE); - spi_flash_write(&flash, s3nv_offset, - sizeof(struct amd_s3_persistent_data), persistent_data); - - /* Deallocate temporary data structures */ - free(persistent_data); - - spi_flash_volatile_group_end(&flash); - - /* Allow training bypass if DIMM configuration is unchanged on next boot */ - nvram = 1; - set_option("allow_spd_nvram_cache_restore", &nvram); - - return 0; -} - -int8_t restore_mct_information_from_nvram(uint8_t training_only) -{ - struct amd_s3_persistent_data *persistent_data; - - persistent_data = map_s3nv_in_nvram(); - if (!persistent_data) - return -1; - - restore_mct_data_from_save_variable(persistent_data, training_only); - - return 0; -} - -void calculate_and_store_spd_hashes(struct MCTStatStruc *pMCTstat, - struct DCTStatStruc *pDCTstat) -{ - uint8_t dimm; - - for (dimm = 0; dimm < MAX_DIMMS_SUPPORTED; dimm++) { - calculate_spd_hash(pDCTstat->spd_data.spd_bytes[dimm], &pDCTstat->spd_data.spd_hash[dimm]); - } -} - -void compare_nvram_spd_hashes(struct MCTStatStruc *pMCTstat, - struct DCTStatStruc *pDCTstat) -{ - uint8_t dimm; - - pDCTstat->spd_data.nvram_spd_match = 1; - for (dimm = 0; dimm < MAX_DIMMS_SUPPORTED; dimm++) { - if (pDCTstat->spd_data.spd_hash[dimm] != pDCTstat->spd_data.nvram_spd_hash[dimm]) - pDCTstat->spd_data.nvram_spd_match = 0; - } -} diff --git a/src/northbridge/amd/amdmct/mct_ddr3/s3utils.h b/src/northbridge/amd/amdmct/mct_ddr3/s3utils.h deleted file mode 100644 index d13cb23c80..0000000000 --- a/src/northbridge/amd/amdmct/mct_ddr3/s3utils.h +++ /dev/null @@ -1,31 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2015 Timothy Pearson , Raptor Engineering - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ -#ifndef S3UTILS_H -#define S3UTILS_H - -#include "../wrappers/mcti.h" -#include "mct_d.h" - -#ifdef __RAMSTAGE__ -int8_t save_mct_information_to_nvram(void); -void copy_mct_data_to_save_variable(struct amd_s3_persistent_data* persistent_data); -#endif - -void calculate_and_store_spd_hashes(struct MCTStatStruc *pMCTstat, - struct DCTStatStruc *pDCTstat); -void compare_nvram_spd_hashes(struct MCTStatStruc *pMCTstat, - struct DCTStatStruc *pDCTstat); - -#endif diff --git a/src/northbridge/amd/amdmct/wrappers/Makefile.inc b/src/northbridge/amd/amdmct/wrappers/Makefile.inc deleted file mode 100644 index 5773067138..0000000000 --- a/src/northbridge/amd/amdmct/wrappers/Makefile.inc +++ /dev/null @@ -1,5 +0,0 @@ -ifeq ($(CONFIG_NORTHBRIDGE_AMD_AMDFAM10),y) - -romstage-y += mcti_d.c - -endif diff --git a/src/northbridge/amd/amdmct/wrappers/mcti.h b/src/northbridge/amd/amdmct/wrappers/mcti.h deleted file mode 100644 index cc0e1b29b2..0000000000 --- a/src/northbridge/amd/amdmct/wrappers/mcti.h +++ /dev/null @@ -1,153 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007 Advanced Micro Devices, Inc. - * Copyright (C) 2015 Timothy Pearson , Raptor Engineering - * Copyright (C) 2016 Damien Zammit - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef MCTI_H -#define MCTI_H - -#include -#include -#include - -struct DCTStatStruc; -struct MCTStatStruc; - -#define SERVER 0 -#define DESKTOP 1 -//#define MOBILE 2 -#define REV_F 0 -#define REV_DR 1 -#define REV_FDR 2 - -/*---------------------------------------------------------------------------- -COMMENT OUT ALL BUT 1 -----------------------------------------------------------------------------*/ -//#define BUILD_VERSION REV_F /*BIOS supports rev F only*/ -//#define BUILD_VERSION REV_DR /*BIOS supports rev 10 only*/ -//#define BUILD_VERSION REV_FDR /*BIOS supports both rev F and 10*/ - -/*---------------------------------------------------------------------------- -COMMENT OUT ALL BUT 1 -----------------------------------------------------------------------------*/ -#ifndef SYSTEM_TYPE -#define SYSTEM_TYPE SERVER -//#define SYSTEM_TYPE DESKTOP -//#define SYSTEM_TYPE MOBILE -#endif - -/*---------------------------------------------------------------------------- -UPDATE AS NEEDED -----------------------------------------------------------------------------*/ -#ifndef MAX_NODES_SUPPORTED -#define MAX_NODES_SUPPORTED 8 -#endif - -#ifndef MAX_DIMMS_SUPPORTED -#if CONFIG(DIMM_DDR3) - #define MAX_DIMMS_SUPPORTED 6 -#else - #define MAX_DIMMS_SUPPORTED 8 -#endif -#endif - -#ifndef MAX_CS_SUPPORTED -#define MAX_CS_SUPPORTED 8 -#endif - -#ifndef MCT_DIMM_SPARE_NO_WARM -#define MCT_DIMM_SPARE_NO_WARM 0 -#endif - -#ifndef MEM_MAX_LOAD_FREQ -#if CONFIG(DIMM_DDR3) - #define MEM_MAX_LOAD_FREQ 933 - #define MEM_MIN_PLATFORM_FREQ_FAM10 400 - #define MEM_MIN_PLATFORM_FREQ_FAM15 333 -#else /* AMD_FAM10_DDR2 */ - #define MEM_MAX_LOAD_FREQ 400 - #define MEM_MIN_PLATFORM_FREQ_FAM10 200 - /* DDR2 not available on Family 15h */ - #define MEM_MIN_PLATFORM_FREQ_FAM15 0 -#endif -#endif - -#define MCT_TRNG_KEEPOUT_START 0x00000C00 -#define MCT_TRNG_KEEPOUT_END 0x00000CFF - -#define NVRAM_DDR2_800 0 -#define NVRAM_DDR2_667 1 -#define NVRAM_DDR2_533 2 -#define NVRAM_DDR2_400 3 - -#define NVRAM_DDR3_1600 0 -#define NVRAM_DDR3_1333 1 -#define NVRAM_DDR3_1066 2 -#define NVRAM_DDR3_800 3 - -/* The recommended maximum GFX Upper Memory Area - * size is 256M, however, to be on the safe side - * move TOM down by 512M. - */ -#define MAXIMUM_GFXUMA_SIZE 0x20000000 - -/* Do not allow less than 16M of DRAM in 32-bit space. - * This number is not hardware constrained and can be - * changed as needed. - */ -#define MINIMUM_DRAM_BELOW_4G 0x1000000 - -static const uint16_t ddr2_limits[4] = {400, 333, 266, 200}; -static const uint16_t ddr3_limits[16] = {933, 800, 666, 533, 400, 333, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}; - -#if CONFIG(DIMM_DDR3) - #include -#else - #include -#endif - -#if CONFIG(DIMM_DDR2) -void mctSaveDQSSigTmg_D(void); -void mctGetDQSSigTmg_D(void); -u8 mctSetNodeBoundary_D(void); -#endif -u16 mctGet_NVbits(u8 index); -void mctHookAfterDIMMpre(void); -void mctGet_MaxLoadFreq(struct DCTStatStruc *pDCTstat); -void mctAdjustAutoCycTmg_D(void); -void mctHookAfterAutoCycTmg(void); -void mctGetCS_ExcludeMap(void); -void mctHookBeforeECC(void); -void mctHookAfterECC(void); -void mctHookAfterAutoCfg(void); -void mctHookAfterPSCfg(void); -void mctHookAfterHTMap(void); -void mctHookAfterCPU(void); -void mctInitMemGPIOs_A_D(void); -void mctNodeIDDebugPort_D(void); -void mctWarmReset_D(void); -void mctHookBeforeDramInit(void); -void mctHookAfterDramInit(void); -void mctHookBeforeAnyTraining(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstatA); -void mctHookAfterAnyTraining(void); -uint64_t mctGetLogicalCPUID_D(u8 node); - -#if CONFIG(DIMM_DDR3) -void vErratum372(struct DCTStatStruc *pDCTstat); -void vErratum414(struct DCTStatStruc *pDCTstat); -u32 mct_AdjustSPDTimings(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstatA, u32 val); -#endif - -#endif diff --git a/src/northbridge/amd/amdmct/wrappers/mcti_d.c b/src/northbridge/amd/amdmct/wrappers/mcti_d.c deleted file mode 100644 index b8042fe46d..0000000000 --- a/src/northbridge/amd/amdmct/wrappers/mcti_d.c +++ /dev/null @@ -1,543 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2015 Timothy Pearson , Raptor Engineering - * Copyright (C) 2007-2008 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -/* Call-backs */ - -#include -#include -#include -#include - -#include "mcti.h" - -#define NVRAM_DDR2_800 0 -#define NVRAM_DDR2_667 1 -#define NVRAM_DDR2_533 2 -#define NVRAM_DDR2_400 3 - -#define NVRAM_DDR3_1600 0 -#define NVRAM_DDR3_1333 1 -#define NVRAM_DDR3_1066 2 -#define NVRAM_DDR3_800 3 - -static inline uint8_t isfam15h(void) -{ - uint8_t fam15h = 0; - uint32_t family; - - family = cpuid_eax(0x80000001); - family = ((family & 0xf00000) >> 16) | ((family & 0xf00) >> 8); - - if (family >= 0x6f) - /* Family 15h or later */ - fam15h = 1; - - return fam15h; -} - -/* The recommended maximum GFX Upper Memory Area - * size is 256M, however, to be on the safe side - * move TOM down by 512M. - */ -#define MAXIMUM_GFXUMA_SIZE 0x20000000 - -/* Do not allow less than 16M of DRAM in 32-bit space. - * This number is not hardware constrained and can be - * changed as needed. - */ -#define MINIMUM_DRAM_BELOW_4G 0x1000000 - -u16 mctGet_NVbits(u8 index) -{ - u16 val = 0; - int nvram; - - switch (index) { - case NV_PACK_TYPE: -#if CONFIG_CPU_SOCKET_TYPE == 0x10 /* Socket F */ - val = 0; -#elif CONFIG_CPU_SOCKET_TYPE == 0x11 /* AM3 */ - val = 1; -#elif CONFIG_CPU_SOCKET_TYPE == 0x13 /* ASB2 */ - val = 4; -#elif CONFIG_CPU_SOCKET_TYPE == 0x14 /* C32 */ - val = 5; -#elif CONFIG_CPU_SOCKET_TYPE == 0x15 /* G34 */ - val = 3; -#elif CONFIG_CPU_SOCKET_TYPE == 0x16 /* FM2 */ - val = 6; -//#elif SYSTEM_TYPE == MOBILE -// val = 2; -#endif - break; - case NV_MAX_NODES: - val = MAX_NODES_SUPPORTED; - break; - case NV_MAX_DIMMS: - val = MAX_DIMMS_SUPPORTED; - //val = 8; - break; - case NV_MAX_DIMMS_PER_CH: - /* FIXME - * Mainboards need to be able to specify the maximum number of DIMMs installable per channel - * For now assume a maximum of 2 DIMMs per channel can be installed - */ - val = 2; - break; - case NV_MAX_MEMCLK: - /* Maximum platform supported memclk */ - val = MEM_MAX_LOAD_FREQ; - - if (get_option(&nvram, "max_mem_clock") == CB_SUCCESS) { - int limit = val; - if (CONFIG(DIMM_DDR3)) - limit = ddr3_limits[nvram & 0xf]; - else if (CONFIG(DIMM_DDR2)) - limit = ddr2_limits[nvram & 0x3]; - val = min(limit, val); - } - break; - case NV_MIN_MEMCLK: - /* Minimum platform supported memclk */ - if (isfam15h()) - val = MEM_MIN_PLATFORM_FREQ_FAM15; - else - val = MEM_MIN_PLATFORM_FREQ_FAM10; - break; - case NV_ECC_CAP: -#if SYSTEM_TYPE == SERVER - val = 1; /* memory bus ECC capable */ -#else - val = 0; /* memory bus ECC not capable */ -#endif - break; - case NV_4RANKType: - /* Quad Rank DIMM slot type */ - val = 0; /* normal */ - //val = 1; /* R4 (registered DIMMs in AMD server configuration) */ - //val = 2; /* S4 (Unbuffered SO-DIMMS) */ - break; - case NV_BYPMAX: -#if !CONFIG(GFXUMA) - val = 4; -#elif CONFIG(GFXUMA) - val = 7; -#endif - break; - case NV_RDWRQBYP: -#if !CONFIG(GFXUMA) - val = 2; -#elif CONFIG(GFXUMA) - val = 3; -#endif - break; - case NV_MCTUSRTMGMODE: - val = 0; /* Automatic (recommended) */ - //val = 1; /* Limited */ - //val = 2; /* Manual */ - break; - case NV_MemCkVal: - //val = 0; /* 200MHz */ - //val = 1; /* 266MHz */ - val = 2; /* 333MHz */ - break; - case NV_BankIntlv: - /* Bank (chip select) interleaving */ - //val = 0; /* disabled */ - val = 1; /* enabled (recommended) */ - - if (get_option(&nvram, "interleave_chip_selects") == CB_SUCCESS) - val = !!nvram; - break; - case NV_MemHole: - //val = 0; /* Disabled */ - val = 1; /* Enabled (recommended) */ - break; - case NV_AllMemClks: - val = 0; /* Normal (only to slots that have enabled DIMMs) */ - //val = 1; /* Enable all memclocks */ - break; - case NV_SPDCHK_RESTRT: - val = 0; /* Exit current node initialization if any DIMM has SPD checksum error */ - //val = 1; /* Ignore faulty SPD checksum (DIMM will still be disabled), continue current node initialization */ - //val = 2; /* Override faulty SPD checksum (DIMM will be enabled), continue current node initialization */ - - if (get_option(&nvram, "dimm_spd_checksum") == CB_SUCCESS) - val = nvram & 0x3; - - if (val > 2) - val = 2; - - break; - case NV_DQSTrainCTL: - //val = 0; /*Skip dqs training */ - val = 1; /* Perform dqs training */ - break; - case NV_NodeIntlv: - val = 0; /* Disabled (recommended) */ - //val = 1; /* Enable */ - - if (get_option(&nvram, "interleave_nodes") == CB_SUCCESS) - val = !!nvram; - break; - case NV_BurstLen32: -#if !CONFIG(GFXUMA) - val = 0; /* 64 byte mode */ -#elif CONFIG(GFXUMA) - val = 1; /* 32 byte mode */ -#endif - break; - case NV_CKE_PDEN: - //val = 0; /* Disable */ - val = 1; /* Enable */ - break; - case NV_CKE_CTL: - val = 0; /* per channel control */ - //val = 1; /* per chip select control */ - break; - case NV_CLKHZAltVidC3: - val = 0; /* disable */ - //val = 1; /* enable */ - break; - case NV_BottomIO: - case NV_BottomUMA: - /* address bits [31:24] */ -#if !CONFIG(GFXUMA) - val = (CONFIG_MMCONF_BASE_ADDRESS >> 24); -#elif CONFIG(GFXUMA) - #if (CONFIG_MMCONF_BASE_ADDRESS < (MAXIMUM_GFXUMA_SIZE + MINIMUM_DRAM_BELOW_4G)) - #error "MMCONF_BASE_ADDRESS is too small" - #endif - val = ((CONFIG_MMCONF_BASE_ADDRESS - MAXIMUM_GFXUMA_SIZE) >> 24); -#endif - break; - case NV_ECC: -#if (SYSTEM_TYPE == SERVER) - val = 1; /* Enable */ -#else - val = 0; /* Disable */ -#endif - - if (get_option(&nvram, "ECC_memory") == CB_SUCCESS) - val = !!nvram; - break; - case NV_NBECC: -#if (SYSTEM_TYPE == SERVER) - val = 1; /* Enable */ -#else - val = 0; /* Disable */ -#endif - break; - case NV_ChipKill: -#if (SYSTEM_TYPE == SERVER) - val = 1; /* Enable */ -#else - val = 0; /* Disable */ -#endif - break; - case NV_ECCRedir: - /* - * 0: Disable - * 1: Enable - */ - val = 0; - - if (get_option(&nvram, "ECC_redirection") == CB_SUCCESS) - val = !!nvram; - break; - case NV_DramBKScrub: - /* - * 0x00: Disabled - * 0x01: 40ns - * 0x02: 80ns - * 0x03: 160ns - * 0x04: 320ns - * 0x05: 640ns - * 0x06: 1.28us - * 0x07: 2.56us - * 0x08: 5.12us - * 0x09: 10.2us - * 0x0a: 20.5us - * 0x0b: 41us - * 0x0c: 81.9us - * 0x0d: 163.8us - * 0x0e: 327.7us - * 0x0f: 655.4us - * 0x10: 1.31ms - * 0x11: 2.62ms - * 0x12: 5.24ms - * 0x13: 10.49ms - * 0x14: 20.97sms - * 0x15: 42ms - * 0x16: 84ms - */ - val = 0; - - if ((get_option(&nvram, "ecc_scrub_rate") == CB_SUCCESS) && (nvram <= 0x16)) - val = nvram; - break; - case NV_L2BKScrub: - val = 0; /* Disabled - See L2Scrub in BKDG */ - break; - case NV_L3BKScrub: - val = 0; /* Disabled - See L3Scrub in BKDG */ - break; - case NV_DCBKScrub: - val = 0; /* Disabled - See DcacheScrub in BKDG */ - break; - case NV_CS_SpareCTL: - val = 0; /* Disabled */ - //val = 1; /* Enabled */ - break; - case NV_SyncOnUnEccEn: - val = 0; /* Disabled */ - //val = 1; /* Enabled */ - break; - case NV_Unganged: - /* channel interleave is better performance than ganged mode at this time */ - val = 1; /* Enabled */ - //val = 0; /* Disabled */ - - if (get_option(&nvram, "interleave_memory_channels") == CB_SUCCESS) - val = !!nvram; - break; - case NV_ChannelIntlv: - val = 5; /* Not currently checked in mctchi_d.c */ - /* Bit 0 = 0 - Disable - * 1 - Enable - * Bits[2:1] = 00b - Address bits 6 - * 01b - Address bits 1 - * 10b - Hash*, XOR of address bits [20:16, 6] - * 11b - Hash*, XOR of address bits [20:16, 9] - */ - break; - } - - return val; -} - - -void mctHookAfterDIMMpre(void) -{ -} - - -void mctGet_MaxLoadFreq(struct DCTStatStruc *pDCTstat) -{ - pDCTstat->PresetmaxFreq = mctGet_NVbits(NV_MAX_MEMCLK); - - /* Determine the number of installed DIMMs */ - int ch1_count = 0; - int ch2_count = 0; - uint8_t ch1_registered = 0; - uint8_t ch2_registered = 0; - uint8_t ch1_voltage = 0; - uint8_t ch2_voltage = 0; - uint8_t highest_rank_count[2]; - uint8_t dimm; - int i; - for (i = 0; i < 15; i = i + 2) { - if (pDCTstat->DIMMValid & (1 << i)) - ch1_count++; - if (pDCTstat->DIMMValid & (1 << (i + 1))) - ch2_count++; - } - for (i = 0; i < MAX_DIMMS_SUPPORTED; i = i + 2) { - if (pDCTstat->DimmRegistered[i]) - ch1_registered = 1; - if (pDCTstat->DimmRegistered[i + 1]) - ch2_registered = 1; - } - if (CONFIG(DEBUG_RAM_SETUP)) { - printk(BIOS_DEBUG, "mctGet_MaxLoadFreq: Channel 1: %d DIMM(s) detected\n", ch1_count); - printk(BIOS_DEBUG, "mctGet_MaxLoadFreq: Channel 2: %d DIMM(s) detected\n", ch2_count); - } - -#if CONFIG(DIMM_DDR3) - for (i = 0; i < MAX_DIMMS_SUPPORTED; i = i + 2) { - if (pDCTstat->DIMMValid & (1 << i)) - ch1_voltage |= pDCTstat->DimmConfiguredVoltage[i]; - if (pDCTstat->DIMMValid & (1 << (i + 1))) - ch2_voltage |= pDCTstat->DimmConfiguredVoltage[i + 1]; - } -#endif - - for (i = 0; i < 2; i++) { - highest_rank_count[i] = 0x0; - for (dimm = 0; dimm < MAX_DIMMS_SUPPORTED; dimm++) { - if (pDCTstat->DimmRanks[dimm] > highest_rank_count[i]) - highest_rank_count[i] = pDCTstat->DimmRanks[dimm]; - } - } - - /* Set limits if needed */ - pDCTstat->PresetmaxFreq = mct_MaxLoadFreq(max(ch1_count, ch2_count), max(highest_rank_count[0], highest_rank_count[1]), (ch1_registered || ch2_registered), (ch1_voltage | ch2_voltage), pDCTstat->PresetmaxFreq); -} - -void mctAdjustAutoCycTmg_D(void) -{ -} - - -void mctHookAfterAutoCycTmg(void) -{ -} - - -void mctGetCS_ExcludeMap(void) -{ -} - - -void mctHookAfterAutoCfg(void) -{ -} - - -void mctHookAfterPSCfg(void) -{ -} - - -void mctHookAfterHTMap(void) -{ -} - - -void mctHookAfterCPU(void) -{ -} - - -#if CONFIG(DIMM_DDR2) -void mctSaveDQSSigTmg_D(void) -{ -} - -void mctGetDQSSigTmg_D(void) -{ -} -#endif - -void mctHookBeforeECC(void) -{ -} - -void mctHookAfterECC(void) -{ -} - -#ifdef UNUSED_CODE -void mctInitMemGPIOs_A(void) -{ -} -#endif - - -void mctInitMemGPIOs_A_D(void) -{ -} - - -void mctNodeIDDebugPort_D(void) -{ -} - - -void mctWarmReset_D(void) -{ -} - - -void mctHookBeforeDramInit(void) -{ -} - - -void mctHookAfterDramInit(void) -{ -} - -#if CONFIG(DIMM_DDR3) -void vErratum372(struct DCTStatStruc *pDCTstat) -{ - msr_t msr = rdmsr(NB_CFG_MSR); - - int nbPstate1supported = !(msr.hi & (1 << (NB_GfxNbPstateDis -32))); - - // is this the right way to check for NB pstate 1 or DDR3-1333 ? - if (((pDCTstat->PresetmaxFreq == 1333)||(nbPstate1supported)) - && (!pDCTstat->GangedMode)) { - /* DisableCf8ExtCfg */ - msr.hi &= ~(3 << (51 - 32)); - wrmsr(NB_CFG_MSR, msr); - } -} - -void vErratum414(struct DCTStatStruc *pDCTstat) -{ - int dct = 0; - for (; dct < 2 ; dct++) { - int dRAMConfigHi = Get_NB32(pDCTstat->dev_dct,0x94 + (0x100 * dct)); - int powerDown = dRAMConfigHi & (1 << PowerDownEn); - int ddr3 = dRAMConfigHi & (1 << Ddr3Mode); - int dRAMMRS = Get_NB32(pDCTstat->dev_dct,0x84 + (0x100 * dct)); - int pchgPDModeSel = dRAMMRS & (1 << PchgPDModeSel); - if (powerDown && ddr3 && pchgPDModeSel) - Set_NB32(pDCTstat->dev_dct,0x84 + (0x100 * dct), dRAMMRS & ~(1 << PchgPDModeSel)); - } -} -#endif - - -void mctHookBeforeAnyTraining(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstatA) -{ -#if CONFIG(DIMM_DDR3) - /* FIXME : as of 25.6.2010 errata 350 and 372 should apply to ((RB|BL|DA)-C[23])|(HY-D[01])|(PH-E0) but I don't find constants for all of them */ - if (pDCTstatA->LogicalCPUID & (AMD_DRBH_Cx | AMD_DR_Dx)) { - vErratum372(pDCTstatA); - vErratum414(pDCTstatA); - } -#endif -} - -#if CONFIG(DIMM_DDR3) -u32 mct_AdjustSPDTimings(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstatA, u32 val) -{ - if (pDCTstatA->LogicalCPUID & AMD_DR_Bx) { - if (pDCTstatA->Status & (1 << SB_Registered)) { - val ++; - } - } - return val; -} -#endif - -void mctHookAfterAnyTraining(void) -{ -} - -uint64_t mctGetLogicalCPUID_D(u8 node) -{ - return mctGetLogicalCPUID(node); -} - -#if CONFIG(DIMM_DDR2) -u8 mctSetNodeBoundary_D(void) -{ - return 0; -} -#endif From 6059c9d133554488339f3772527752bfa789500f Mon Sep 17 00:00:00 2001 From: Patrick Georgi Date: Tue, 19 Nov 2019 17:18:33 +0100 Subject: [PATCH 0302/1242] Documentation/releases: Drop reference to piratenpad Piratenpad is dead. Change-Id: Id9cfb68f6c6e05d1af2a526c817713a92220d370 Signed-off-by: Patrick Georgi Reviewed-on: https://review.coreboot.org/c/coreboot/+/36958 Reviewed-by: HAOUAS Elyes Tested-by: build bot (Jenkins) --- Documentation/releases/checklist.md | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) diff --git a/Documentation/releases/checklist.md b/Documentation/releases/checklist.md index f25f336c00..2c55957ee8 100644 --- a/Documentation/releases/checklist.md +++ b/Documentation/releases/checklist.md @@ -83,9 +83,7 @@ release notes that are in the making and ask people to test the hardware they have to make sure it's working with the current master branch, from which the release will ultimately be derived from. -People should also be encouraged to provide additions to the -release notes, for example by putting them on some [collaborative -editor](https://www.piratenpad.de). +People should be encouraged to provide additions to the release notes. The final release notes will reside in coreboot's Documentation/releases directory, so asking for additions to that through the regular Gerrit From bc29bd0de65f1c2054117d42a9e3241ed4c3db80 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ky=C3=B6sti=20M=C3=A4lkki?= Date: Wed, 20 Nov 2019 22:26:54 +0200 Subject: [PATCH 0303/1242] device: Add back dummy HT_CHAIN_UNITID_BASE MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This should be defined by mainboard. Add a dummy default to fix master while HyperTransport files are still around referencing this. Change-Id: I58188a200a2cad5fa20affee1844117ba71ac338 Signed-off-by: Kyösti Mälkki Reviewed-on: https://review.coreboot.org/c/coreboot/+/37036 Reviewed-by: Aaron Durbin Reviewed-by: Arthur Heymans Tested-by: build bot (Jenkins) --- src/device/Kconfig | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/src/device/Kconfig b/src/device/Kconfig index 7f00c0b4e8..9ae3bbd1de 100644 --- a/src/device/Kconfig +++ b/src/device/Kconfig @@ -499,6 +499,14 @@ config HYPERTRANSPORT_PLUGIN_SUPPORT bool default n +config HT_CHAIN_UNITID_BASE + int + default 0 + +config HT_CHAIN_END_UNITID_BASE + int + default 0 + config PCIX_PLUGIN_SUPPORT bool default y From 298619f6d9adde49b4279c906b0d20a41f919a61 Mon Sep 17 00:00:00 2001 From: Arthur Heymans Date: Tue, 19 Nov 2019 18:33:48 +0100 Subject: [PATCH 0304/1242] mb/*/*: Drop Intel Rangeley mainboards MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Relocatable ramstage, postcar stage and C_ENVIRONMENT_BOOTBLOCK are now mandatory features, which this platform lacks. Change-Id: Id38eada2d08426520261d4824990a49f8302976b Signed-off-by: Arthur Heymans Reviewed-on: https://review.coreboot.org/c/coreboot/+/36979 Tested-by: build bot (Jenkins) Reviewed-by: HAOUAS Elyes Reviewed-by: Kyösti Mälkki Reviewed-by: Angel Pons Reviewed-by: David Hendricks --- src/mainboard/adi/Kconfig | 16 -- src/mainboard/adi/Kconfig.name | 2 - src/mainboard/adi/rcc-dff/Kconfig | 76 -------- src/mainboard/adi/rcc-dff/Kconfig.name | 2 - src/mainboard/adi/rcc-dff/Makefile.inc | 16 -- src/mainboard/adi/rcc-dff/acpi/ec.asl | 0 src/mainboard/adi/rcc-dff/acpi/mainboard.asl | 26 --- src/mainboard/adi/rcc-dff/acpi/platform.asl | 22 --- src/mainboard/adi/rcc-dff/acpi/superio.asl | 0 src/mainboard/adi/rcc-dff/acpi/thermal.asl | 0 src/mainboard/adi/rcc-dff/acpi_tables.c | 74 -------- src/mainboard/adi/rcc-dff/board_info.txt | 4 - src/mainboard/adi/rcc-dff/cmos.layout | 104 ----------- src/mainboard/adi/rcc-dff/config_seabios | 5 - src/mainboard/adi/rcc-dff/devicetree.cb | 62 ------ src/mainboard/adi/rcc-dff/dsdt.asl | 54 ------ src/mainboard/adi/rcc-dff/fadt.c | 36 ---- src/mainboard/adi/rcc-dff/gpio.h | 174 ----------------- src/mainboard/adi/rcc-dff/irq_tables.c | 63 ------- src/mainboard/adi/rcc-dff/irqroute.c | 19 -- src/mainboard/adi/rcc-dff/irqroute.h | 71 ------- src/mainboard/adi/rcc-dff/romstage.c | 81 -------- src/mainboard/adi/rcc-dff/thermal.h | 29 --- src/mainboard/intel/littleplains/Kconfig | 67 ------- src/mainboard/intel/littleplains/Kconfig.name | 2 - src/mainboard/intel/littleplains/Makefile.inc | 16 -- src/mainboard/intel/littleplains/acpi/ec.asl | 0 .../intel/littleplains/acpi/mainboard.asl | 26 --- .../intel/littleplains/acpi/platform.asl | 22 --- .../intel/littleplains/acpi/superio.asl | 0 .../intel/littleplains/acpi/thermal.asl | 0 .../intel/littleplains/acpi_tables.c | 74 -------- .../intel/littleplains/board_info.txt | 4 - src/mainboard/intel/littleplains/cmos.layout | 104 ----------- .../intel/littleplains/config_seabios | 5 - .../intel/littleplains/devicetree.cb | 62 ------ src/mainboard/intel/littleplains/dsdt.asl | 54 ------ src/mainboard/intel/littleplains/fadt.c | 35 ---- src/mainboard/intel/littleplains/gpio.h | 176 ------------------ src/mainboard/intel/littleplains/irq_tables.c | 63 ------- src/mainboard/intel/littleplains/irqroute.c | 19 -- src/mainboard/intel/littleplains/irqroute.h | 69 ------- src/mainboard/intel/littleplains/romstage.c | 81 -------- src/mainboard/intel/littleplains/thermal.h | 29 --- src/mainboard/intel/mohonpeak/Kconfig | 76 -------- src/mainboard/intel/mohonpeak/Kconfig.name | 2 - src/mainboard/intel/mohonpeak/Makefile.inc | 16 -- src/mainboard/intel/mohonpeak/acpi/ec.asl | 0 .../intel/mohonpeak/acpi/mainboard.asl | 26 --- .../intel/mohonpeak/acpi/platform.asl | 22 --- .../intel/mohonpeak/acpi/superio.asl | 0 .../intel/mohonpeak/acpi/thermal.asl | 0 src/mainboard/intel/mohonpeak/acpi_tables.c | 74 -------- src/mainboard/intel/mohonpeak/board_info.txt | 4 - src/mainboard/intel/mohonpeak/cmos.layout | 104 ----------- src/mainboard/intel/mohonpeak/config_seabios | 5 - src/mainboard/intel/mohonpeak/devicetree.cb | 62 ------ src/mainboard/intel/mohonpeak/dsdt.asl | 54 ------ src/mainboard/intel/mohonpeak/fadt.c | 35 ---- src/mainboard/intel/mohonpeak/gpio.h | 174 ----------------- src/mainboard/intel/mohonpeak/irq_tables.c | 63 ------- src/mainboard/intel/mohonpeak/irqroute.c | 19 -- src/mainboard/intel/mohonpeak/irqroute.h | 71 ------- src/mainboard/intel/mohonpeak/romstage.c | 81 -------- src/mainboard/intel/mohonpeak/thermal.h | 29 --- 65 files changed, 2761 deletions(-) delete mode 100644 src/mainboard/adi/Kconfig delete mode 100644 src/mainboard/adi/Kconfig.name delete mode 100644 src/mainboard/adi/rcc-dff/Kconfig delete mode 100644 src/mainboard/adi/rcc-dff/Kconfig.name delete mode 100644 src/mainboard/adi/rcc-dff/Makefile.inc delete mode 100644 src/mainboard/adi/rcc-dff/acpi/ec.asl delete mode 100644 src/mainboard/adi/rcc-dff/acpi/mainboard.asl delete mode 100644 src/mainboard/adi/rcc-dff/acpi/platform.asl delete mode 100644 src/mainboard/adi/rcc-dff/acpi/superio.asl delete mode 100644 src/mainboard/adi/rcc-dff/acpi/thermal.asl delete mode 100644 src/mainboard/adi/rcc-dff/acpi_tables.c delete mode 100644 src/mainboard/adi/rcc-dff/board_info.txt delete mode 100644 src/mainboard/adi/rcc-dff/cmos.layout delete mode 100644 src/mainboard/adi/rcc-dff/config_seabios delete mode 100644 src/mainboard/adi/rcc-dff/devicetree.cb delete mode 100644 src/mainboard/adi/rcc-dff/dsdt.asl delete mode 100644 src/mainboard/adi/rcc-dff/fadt.c delete mode 100644 src/mainboard/adi/rcc-dff/gpio.h delete mode 100644 src/mainboard/adi/rcc-dff/irq_tables.c delete mode 100644 src/mainboard/adi/rcc-dff/irqroute.c delete mode 100644 src/mainboard/adi/rcc-dff/irqroute.h delete mode 100644 src/mainboard/adi/rcc-dff/romstage.c delete mode 100644 src/mainboard/adi/rcc-dff/thermal.h delete mode 100644 src/mainboard/intel/littleplains/Kconfig delete mode 100644 src/mainboard/intel/littleplains/Kconfig.name delete mode 100644 src/mainboard/intel/littleplains/Makefile.inc delete mode 100644 src/mainboard/intel/littleplains/acpi/ec.asl delete mode 100644 src/mainboard/intel/littleplains/acpi/mainboard.asl delete mode 100644 src/mainboard/intel/littleplains/acpi/platform.asl delete mode 100644 src/mainboard/intel/littleplains/acpi/superio.asl delete mode 100644 src/mainboard/intel/littleplains/acpi/thermal.asl delete mode 100644 src/mainboard/intel/littleplains/acpi_tables.c delete mode 100644 src/mainboard/intel/littleplains/board_info.txt delete mode 100644 src/mainboard/intel/littleplains/cmos.layout delete mode 100644 src/mainboard/intel/littleplains/config_seabios delete mode 100644 src/mainboard/intel/littleplains/devicetree.cb delete mode 100644 src/mainboard/intel/littleplains/dsdt.asl delete mode 100644 src/mainboard/intel/littleplains/fadt.c delete mode 100644 src/mainboard/intel/littleplains/gpio.h delete mode 100644 src/mainboard/intel/littleplains/irq_tables.c delete mode 100644 src/mainboard/intel/littleplains/irqroute.c delete mode 100644 src/mainboard/intel/littleplains/irqroute.h delete mode 100644 src/mainboard/intel/littleplains/romstage.c delete mode 100644 src/mainboard/intel/littleplains/thermal.h delete mode 100644 src/mainboard/intel/mohonpeak/Kconfig delete mode 100644 src/mainboard/intel/mohonpeak/Kconfig.name delete mode 100644 src/mainboard/intel/mohonpeak/Makefile.inc delete mode 100644 src/mainboard/intel/mohonpeak/acpi/ec.asl delete mode 100644 src/mainboard/intel/mohonpeak/acpi/mainboard.asl delete mode 100644 src/mainboard/intel/mohonpeak/acpi/platform.asl delete mode 100644 src/mainboard/intel/mohonpeak/acpi/superio.asl delete mode 100644 src/mainboard/intel/mohonpeak/acpi/thermal.asl delete mode 100644 src/mainboard/intel/mohonpeak/acpi_tables.c delete mode 100644 src/mainboard/intel/mohonpeak/board_info.txt delete mode 100644 src/mainboard/intel/mohonpeak/cmos.layout delete mode 100644 src/mainboard/intel/mohonpeak/config_seabios delete mode 100644 src/mainboard/intel/mohonpeak/devicetree.cb delete mode 100644 src/mainboard/intel/mohonpeak/dsdt.asl delete mode 100644 src/mainboard/intel/mohonpeak/fadt.c delete mode 100644 src/mainboard/intel/mohonpeak/gpio.h delete mode 100644 src/mainboard/intel/mohonpeak/irq_tables.c delete mode 100644 src/mainboard/intel/mohonpeak/irqroute.c delete mode 100644 src/mainboard/intel/mohonpeak/irqroute.h delete mode 100644 src/mainboard/intel/mohonpeak/romstage.c delete mode 100644 src/mainboard/intel/mohonpeak/thermal.h diff --git a/src/mainboard/adi/Kconfig b/src/mainboard/adi/Kconfig deleted file mode 100644 index 5079d96acd..0000000000 --- a/src/mainboard/adi/Kconfig +++ /dev/null @@ -1,16 +0,0 @@ -if VENDOR_ADI - -choice - prompt "Mainboard model" - -source "src/mainboard/adi/*/Kconfig.name" - -endchoice - -source "src/mainboard/adi/*/Kconfig" - -config MAINBOARD_VENDOR - string - default "ADI" - -endif # VENDOR_ADI diff --git a/src/mainboard/adi/Kconfig.name b/src/mainboard/adi/Kconfig.name deleted file mode 100644 index 72689ca225..0000000000 --- a/src/mainboard/adi/Kconfig.name +++ /dev/null @@ -1,2 +0,0 @@ -config VENDOR_ADI - bool "ADI" diff --git a/src/mainboard/adi/rcc-dff/Kconfig b/src/mainboard/adi/rcc-dff/Kconfig deleted file mode 100644 index e7be77c0ec..0000000000 --- a/src/mainboard/adi/rcc-dff/Kconfig +++ /dev/null @@ -1,76 +0,0 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2013-2014 Sage Electronic Engineering, LLC. -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; version 2 of the License. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## - -if BOARD_ADI_RCC_DFF - -config BOARD_SPECIFIC_OPTIONS - def_bool y - select NORTHBRIDGE_INTEL_FSP_RANGELEY - select SOUTHBRIDGE_INTEL_FSP_RANGELEY - select BOARD_ROMSIZE_KB_2048 #actual chip is 8MB - select HAVE_ACPI_TABLES - select HAVE_OPTION_TABLE - select HAVE_FSP_BIN if FSP_PACKAGE_DEFAULT - -config MAINBOARD_DIR - string - default adi/rcc-dff - -config MAINBOARD_PART_NUMBER - string - default "ADI RCC-DFF" - -config MAX_CPUS - int - default 16 - -config FSP_FILE - string - default "../intel/fsp/rangeley/FvFsp.bin" - -config CBFS_SIZE - hex - default 0x00200000 - -config ENABLE_FSP_FAST_BOOT - bool - depends on HAVE_FSP_BIN - default y - -config VIRTUAL_ROM_SIZE - hex - depends on ENABLE_FSP_FAST_BOOT - default 0x400000 - -config FSP_PACKAGE_DEFAULT - bool "Configure defaults for the Intel FSP package" - default n - -config UART_FOR_CONSOLE - int - default 1 - help - The Mohon Peak board uses COM2 (2f8) for the serial console. - -config PAYLOAD_CONFIGFILE - string - depends on PAYLOAD_SEABIOS - default "$(top)/src/mainboard/$(MAINBOARDDIR)/config_seabios" - help - The Avoton/Rangeley chip does not allow devices to write into the 0xe000 - segment. This means that USB/SATA devices will not work in SeaBIOS unless - we put the SeaBIOS buffer area down in the 0x9000 segment. - -endif # BOARD_ADI_RCC_DFF diff --git a/src/mainboard/adi/rcc-dff/Kconfig.name b/src/mainboard/adi/rcc-dff/Kconfig.name deleted file mode 100644 index 13d3eb79d3..0000000000 --- a/src/mainboard/adi/rcc-dff/Kconfig.name +++ /dev/null @@ -1,2 +0,0 @@ -config BOARD_ADI_RCC_DFF - bool "ADI RCC-DFF" diff --git a/src/mainboard/adi/rcc-dff/Makefile.inc b/src/mainboard/adi/rcc-dff/Makefile.inc deleted file mode 100644 index c34ef4b006..0000000000 --- a/src/mainboard/adi/rcc-dff/Makefile.inc +++ /dev/null @@ -1,16 +0,0 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2014 Sage Electronics Engineering, LLC. -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; version 2 of the License. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## - -ramstage-y += irqroute.c diff --git a/src/mainboard/adi/rcc-dff/acpi/ec.asl b/src/mainboard/adi/rcc-dff/acpi/ec.asl deleted file mode 100644 index e69de29bb2..0000000000 diff --git a/src/mainboard/adi/rcc-dff/acpi/mainboard.asl b/src/mainboard/adi/rcc-dff/acpi/mainboard.asl deleted file mode 100644 index aecc2b6905..0000000000 --- a/src/mainboard/adi/rcc-dff/acpi/mainboard.asl +++ /dev/null @@ -1,26 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 Google Inc. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -// #define ACPI_INCLUDE_PMIO 1 /* uncomment to enable PMIO block in soc.asl */ -// #define ACPI_INCLUDE_GPIO 1 /* uncomment to enable GPIO block in soc.asl */ - -Device (PWRB) -{ - Name(_HID, EisaId("PNP0C0C")) - - // Wake - Name(_PRW, Package(){0x1d, 0x05}) -} diff --git a/src/mainboard/adi/rcc-dff/acpi/platform.asl b/src/mainboard/adi/rcc-dff/acpi/platform.asl deleted file mode 100644 index 059cd740ff..0000000000 --- a/src/mainboard/adi/rcc-dff/acpi/platform.asl +++ /dev/null @@ -1,22 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007-2009 coresystems GmbH - * Copyright (C) 2012 The Chromium OS Authors. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -/* The _WAK method is called on system wakeup */ - -Method(_WAK,1) -{ - Return(Package(){0,0}) -} diff --git a/src/mainboard/adi/rcc-dff/acpi/superio.asl b/src/mainboard/adi/rcc-dff/acpi/superio.asl deleted file mode 100644 index e69de29bb2..0000000000 diff --git a/src/mainboard/adi/rcc-dff/acpi/thermal.asl b/src/mainboard/adi/rcc-dff/acpi/thermal.asl deleted file mode 100644 index e69de29bb2..0000000000 diff --git a/src/mainboard/adi/rcc-dff/acpi_tables.c b/src/mainboard/adi/rcc-dff/acpi_tables.c deleted file mode 100644 index a0ebbba53c..0000000000 --- a/src/mainboard/adi/rcc-dff/acpi_tables.c +++ /dev/null @@ -1,74 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2012 The Chromium OS Authors. All rights reserved. - * Copyright (C) 2013 Sage Electronic Engineering, LLC. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include - -static global_nvs_t *gnvs_; - -void acpi_create_gnvs(global_nvs_t *gnvs) -{ - gnvs_ = gnvs; - memset((void *)gnvs, 0, sizeof(*gnvs)); - gnvs->apic = 1; - gnvs->mpen = 1; /* Enable Multi Processing */ - gnvs->pcnt = dev_count_cpu(); - - /* Enable USB ports in S3 */ - gnvs->s3u0 = 1; - gnvs->s3u1 = 1; - - /* - * Enable Front USB ports in S5 by default - * to be consistent with back port behavior - */ - gnvs->s5u0 = 1; - gnvs->s5u1 = 1; - - /* IGD Displays */ - gnvs->ndid = 3; - gnvs->did[0] = 0x80000100; - gnvs->did[1] = 0x80000240; - gnvs->did[2] = 0x80000410; - gnvs->did[3] = 0x80000410; - gnvs->did[4] = 0x00000005; - -} - -unsigned long acpi_fill_madt(unsigned long current) -{ - /* Local APICs */ - current = acpi_create_madt_lapics(current); - - /* IOAPIC */ - current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, - 2, IO_APIC_ADDR, 0); - - /* INT_SRC_OVR */ - current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) - current, 0, 0, 2, 0); - current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) - current, 0, 9, 9, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_HIGH); - - return current; -} diff --git a/src/mainboard/adi/rcc-dff/board_info.txt b/src/mainboard/adi/rcc-dff/board_info.txt deleted file mode 100644 index f49af8aac5..0000000000 --- a/src/mainboard/adi/rcc-dff/board_info.txt +++ /dev/null @@ -1,4 +0,0 @@ -Category: eval -ROM protocol: SPI -Flashrom support: y -Release year: 2014 diff --git a/src/mainboard/adi/rcc-dff/cmos.layout b/src/mainboard/adi/rcc-dff/cmos.layout deleted file mode 100644 index 7c623c0085..0000000000 --- a/src/mainboard/adi/rcc-dff/cmos.layout +++ /dev/null @@ -1,104 +0,0 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2007-2008 coresystems GmbH -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; version 2 of the License. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## - -# ----------------------------------------------------------------- -entries - -# ----------------------------------------------------------------- -# Status Register A -# ----------------------------------------------------------------- -# Status Register B -# ----------------------------------------------------------------- -# Status Register C -#96 4 r 0 status_c_rsvd -#100 1 r 0 uf_flag -#101 1 r 0 af_flag -#102 1 r 0 pf_flag -#103 1 r 0 irqf_flag -# ----------------------------------------------------------------- -# Status Register D -#104 7 r 0 status_d_rsvd -#111 1 r 0 valid_cmos_ram -# ----------------------------------------------------------------- -# Diagnostic Status Register -#112 8 r 0 diag_rsvd1 - -# ----------------------------------------------------------------- -0 120 r 0 reserved_memory -#120 264 r 0 unused - -# ----------------------------------------------------------------- -# RTC_BOOT_BYTE (coreboot hardcoded) -384 1 e 4 boot_option -388 4 h 0 reboot_counter -#390 2 r 0 unused? - -# ----------------------------------------------------------------- -# coreboot config options: console -#392 3 r 0 unused -395 4 e 6 debug_level -#399 1 r 0 unused - -# coreboot config options: cpu -400 1 e 2 hyper_threading -#401 7 r 0 unused - -# coreboot config options: southbridge -408 1 e 1 nmi -409 2 e 7 power_on_after_fail -#411 5 r 0 unused - -# MRC Scrambler Seed values -896 32 r 0 mrc_scrambler_seed -928 32 r 0 mrc_scrambler_seed_s3 - -# coreboot config options: check sums -984 16 h 0 check_sum -#1000 24 r 0 amd_reserved - -#save timestamps in pre-ram boot areas -1720 64 h 0 timestamp_value1 -1784 64 h 0 timestamp_value2 -1848 64 h 0 timestamp_value3 -1912 64 h 0 timestamp_value4 -1976 64 h 0 timestamp_value5 - -# ----------------------------------------------------------------- - -enumerations - -#ID value text -1 0 Disable -1 1 Enable -2 0 Enable -2 1 Disable -4 0 Fallback -4 1 Normal -6 0 Emergency -6 1 Alert -6 2 Critical -6 3 Error -6 4 Warning -6 5 Notice -6 6 Info -6 7 Debug -6 8 Spew -7 0 Disable -7 1 Enable -7 2 Keep -# ----------------------------------------------------------------- -checksums - -checksum 392 415 984 diff --git a/src/mainboard/adi/rcc-dff/config_seabios b/src/mainboard/adi/rcc-dff/config_seabios deleted file mode 100644 index f688f2b530..0000000000 --- a/src/mainboard/adi/rcc-dff/config_seabios +++ /dev/null @@ -1,5 +0,0 @@ -# The Avoton/Rangeley chip does not allow devices to write into the 0xe000 -# segment. This means that USB/SATA devices will not work in SeaBIOS unless -# we put the SeaBIOS buffer area down in the 0x9000 segment. - -# CONFIG_MALLOC_UPPERMEMORY is not set diff --git a/src/mainboard/adi/rcc-dff/devicetree.cb b/src/mainboard/adi/rcc-dff/devicetree.cb deleted file mode 100644 index 0cb73f8a02..0000000000 --- a/src/mainboard/adi/rcc-dff/devicetree.cb +++ /dev/null @@ -1,62 +0,0 @@ -# -# This file is part of the coreboot project. -# -# Copyright (C) 2013 Sage Electronic Engineering, LLC. -# -# This program is free software; you can redistribute it and/or modify -# it under the terms of the GNU General Public License as published by -# the Free Software Foundation; version 2 of the License. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -chip northbridge/intel/fsp_rangeley - - device cpu_cluster 0 on - chip cpu/intel/fsp_model_406dx - device lapic 0 on end - # Magic APIC ID to locate this chip - device lapic 0xACAC off end - - register "c1_battery" = "3" # ACPI(C1) = MWAIT(C3) - register "c2_battery" = "4" # ACPI(C2) = MWAIT(C6) - register "c3_battery" = "5" # ACPI(C3) = MWAIT(C7) - - register "c1_acpower" = "3" # ACPI(C1) = MWAIT(C3) - register "c2_acpower" = "4" # ACPI(C2) = MWAIT(C6) - register "c3_acpower" = "5" # ACPI(C3) = MWAIT(C7) - end - end - - device domain 0 on - device pci 00.0 on end # host bridge - device pci 1.0 on end # PCIe Port #1 - device pci 2.0 on end # PCIe Port #2 - device pci 3.0 on end # PCIe Port #3 - device pci 4.0 on end # PCIe Port #4 - chip southbridge/intel/fsp_rangeley # Rangeley SB - - register "ide_legacy_combined" = "0x0" - register "sata_ahci" = "0x1" - register "sata_port_map" = "0x0f" - - register "fadt_pm_profile" = "PM_DESKTOP" - register "fadt_boot_arch" = "ACPI_FADT_LEGACY_FREE" - - device pci 0b.0 on end # IQIA - device pci 0e.0 on end # RAS - device pci 13.0 on end # SMBus 1 - device pci 14.0 on end # GbE 0 - device pci 14.1 on end # GbE 1 - device pci 14.2 on end # GbE 2 - device pci 14.3 on end # GbE 3 - device pci 16.0 on end # USB EHCI - device pci 17.0 on end # SATA 2.0 - device pci 18.0 on end # SATA 3.0 - device pci 1f.0 on end # LPC bridge - device pci 1f.3 on end # SMBus 0 - end - end -end diff --git a/src/mainboard/adi/rcc-dff/dsdt.asl b/src/mainboard/adi/rcc-dff/dsdt.asl deleted file mode 100644 index 4aad8a8b15..0000000000 --- a/src/mainboard/adi/rcc-dff/dsdt.asl +++ /dev/null @@ -1,54 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007-2009 coresystems GmbH - * Copyright (C) 2011 The ChromiumOS Authors. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -DefinitionBlock( - "dsdt.aml", - "DSDT", - 0x02, // DSDT revision: ACPI v2.0 and up - OEM_ID, - ACPI_TABLE_CREATOR, - 0x20110725 // OEM revision -) -{ - // Include mainboard configuration - #include - - // Include debug methods - #include - - // Some generic macros - #include - #include "acpi/platform.asl" - - // global NVS and variables - #include - - #include "acpi/thermal.asl" - - #include - - Scope (\_SB) { - Device (PCI0) - { - #include - #include - } - } - - /* Chipset specific sleep states */ - #include -} diff --git a/src/mainboard/adi/rcc-dff/fadt.c b/src/mainboard/adi/rcc-dff/fadt.c deleted file mode 100644 index cc88e58351..0000000000 --- a/src/mainboard/adi/rcc-dff/fadt.c +++ /dev/null @@ -1,36 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2014 Sage Electronic Engineering, LLC. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include - -void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt) -{ - acpi_fill_in_fadt(fadt,facs,dsdt); - -#define PLATFORM_HAS_FADT_CUSTOMIZATIONS 0 - - - /* - * Platform specific customizations go here. - * Update the #define above if customizations are added. - */ - - -#if PLATFORM_HAS_FADT_CUSTOMIZATIONS - header->checksum = acpi_checksum((void *) fadt, sizeof(acpi_fadt_t)); -#endif - -} diff --git a/src/mainboard/adi/rcc-dff/gpio.h b/src/mainboard/adi/rcc-dff/gpio.h deleted file mode 100644 index 852734fce6..0000000000 --- a/src/mainboard/adi/rcc-dff/gpio.h +++ /dev/null @@ -1,174 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 The Chromium OS Authors. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef ADI_RCC_DFF_GPIO_H -#define ADI_RCC_DFF_GPIO_H - -#include - -/* Core GPIO */ -const struct soc_gpio soc_gpio_mode = { - .gpio15 = GPIO_MODE_GPIO, /* Board ID GPIO */ - .gpio17 = GPIO_MODE_GPIO, /* Board ID GPIO */ -}; - -const struct soc_gpio soc_gpio_direction = { - .gpio15 = GPIO_DIR_INPUT, /* Board ID GPIO */ - .gpio17 = GPIO_DIR_INPUT, /* Board ID GPIO */ -}; - -const struct soc_gpio soc_gpio_level = { -}; - -const struct soc_gpio soc_gpio_tpe = { -}; - -const struct soc_gpio soc_gpio_tne = { -}; - -const struct soc_gpio soc_gpio_ts = { -}; - -/* Keep the CFIO struct in register order, not gpio order. */ -const struct soc_cfio soc_cfio_core[] = { - { 0x8000, 0x0000, 0x0004, 0x040c }, /* CFIO gpios_28 */ - { 0x8000, 0x0000, 0x0002, 0x040c }, /* CFIO gpios_27 */ - { 0x8500, 0x0000, 0x0002, 0x040c }, /* CFIO gpios_26 */ - { 0x8480, 0x0000, 0x0002, 0x040c }, /* CFIO gpios_21 */ - { 0x8480, 0x0000, 0x0002, 0x040c }, /* CFIO gpios_22 */ - { 0x8480, 0x0000, 0x0002, 0x040c }, /* CFIO gpios_23 */ - { 0x8000, 0x0000, 0x0004, 0x040c }, /* CFIO gpios_25 */ - { 0x8480, 0x0000, 0x0002, 0x040c }, /* CFIO gpios_24 */ - { 0x80c028, 0x30003, 0x0004, 0x040c }, /* CFIO gpios_19 */ - { 0x80c028, 0x30003, 0x0004, 0x040c }, /* CFIO gpios_20 */ - { 0xc028, 0x30003, 0x0004, 0x040c }, /* CFIO gpios_18 */ - { 0x04a9, 0x30003, 0x0002, 0x040c }, /* CFIO gpios_17 */ - { 0x80c028, 0x30003, 0x0004, 0x040c }, /* CFIO gpios_7 */ - { 0xc028, 0x30003, 0x0004, 0x040c }, /* CFIO gpios_4 */ - { 0xc028, 0x30003, 0x0004, 0x040c }, /* CFIO gpios_5 */ - { 0xc528, 0x30003, 0x0002, 0x040c }, /* CFIO gpios_6 */ - { 0xc028, 0x30003, 0x0004, 0x040c }, /* CFIO gpios_1 */ - { 0xc028, 0x20002, 0x0004, 0x040c }, /* CFIO gpios_2 */ - { 0xc028, 0x20002, 0x0004, 0x040c }, /* CFIO gpios_3 */ - { 0xc528, 0x30003, 0x0002, 0x040c }, /* CFIO gpios_0 */ - { 0x0000, 0x0000, 0x0000, 0x0000 }, /* CFIO Reserved */ - { 0xc4a8, 0x30003, 0x0002, 0x040c }, /* CFIO gpios_10 */ - { 0xc4a8, 0x30003, 0x0002, 0x040c }, /* CFIO gpios_13 */ - { 0xc4a8, 0x30003, 0x0000, 0x040c }, /* CFIO gpios_14 */ - { 0xc4a8, 0x30003, 0x0002, 0x040c }, /* CFIO gpios_11 */ - { 0xc4a8, 0x30003, 0x0000, 0x040c }, /* CFIO gpios_8 */ - { 0xc4a8, 0x30003, 0x0002, 0x040c }, /* CFIO gpios_9 */ - { 0xc4a8, 0x30003, 0x0000, 0x040c }, /* CFIO gpios_12 */ - { 0xc4a8, 0x30003, 0x0002, 0x040c }, /* CFIO gpios_29 */ - { 0xc4a8, 0x30003, 0x0002, 0x040c }, /* CFIO gpios_30 */ - { 0x04a9, 0x30003, 0x0002, 0x040c }, /* CFIO gpios_15 */ - { 0xc028, 0x30003, 0x0004, 0x040c }, /* CFIO gpios_16 */ -}; - -/* SUS GPIO */ -const struct soc_gpio soc_gpio_sus_mode = { - .gpio2 = GPIO_MODE_GPIO, -}; - -const struct soc_gpio soc_gpio_sus_direction = { - .gpio2 = GPIO_DIR_INPUT, -}; - -const struct soc_gpio soc_gpio_sus_level = { -}; - -const struct soc_gpio soc_gpio_sus_tpe = { -}; - -const struct soc_gpio soc_gpio_sus_tne = { -}; - -const struct soc_gpio soc_gpio_sus_ts = { -}; - -const struct soc_gpio soc_gpio_sus_we = { -}; - - -/* Keep the CFIO struct in register order, not gpio order. */ -const struct soc_cfio soc_cfio_sus[] = { - { 0xc028, 0x30003, 0x0004, 0x040c }, /* CFIO SUS gpios_21 */ - { 0xc028, 0x30003, 0x0004, 0x040c }, /* CFIO SUS gpios_20 */ - { 0xc028, 0x30003, 0x0004, 0x040c }, /* CFIO SUS gpios_19 */ - { 0xc028, 0x30003, 0x0004, 0x040c }, /* CFIO SUS gpios_22 */ - { 0xc4a8, 0x30003, 0x0002, 0x040c }, /* CFIO SUS gpios_17 */ - { 0xc4a8, 0x30003, 0x0002, 0x040c }, /* CFIO SUS gpios_18 */ - { 0x0000, 0x0000, 0x0000, 0x0000 }, /* CFIO Reserved */ - { 0x0000, 0x0000, 0x0000, 0x0000 }, /* CFIO Reserved */ - { 0x0000, 0x0000, 0x0000, 0x0000 }, /* CFIO Reserved */ - { 0xc4a8, 0x30003, 0x0002, 0x040c }, /* CFIO SUS gpios_14 */ - { 0xc028, 0x30003, 0x0004, 0x040c }, /* CFIO SUS gpios_13 */ - { 0xc028, 0x30003, 0x0004, 0x040c }, /* CFIO SUS gpios_15 */ - { 0xc028, 0x30003, 0x0004, 0x040c }, /* CFIO SUS gpios_16 */ - { 0xc4a8, 0x30003, 0x0002, 0x040c }, /* CFIO SUS gpios_25 */ - { 0xc4a8, 0x30003, 0x0002, 0x040c }, /* CFIO SUS gpios_24 */ - { 0xc4a8, 0x30003, 0x0002, 0x040c }, /* CFIO SUS gpios_26 */ - { 0xc4a8, 0x30003, 0x0002, 0x040c }, /* CFIO SUS gpios_27 */ - { 0xc4a8, 0x30003, 0x0002, 0x040c }, /* CFIO SUS gpios_23 */ - { 0xc4a8, 0x30003, 0x0003, 0x040c }, /* CFIO SUS gpios_2 */ - { 0xc4a8, 0x30003, 0x0003, 0x040c }, /* CFIO SUS gpios_1 */ - { 0x8050, 0x0000, 0x0004, 0x040c }, /* CFIO SUS gpios_7 */ - { 0x0000, 0x0000, 0x0000, 0x0000 }, /* CFIO Reserved */ - { 0x0000, 0x0000, 0x0000, 0x0000 }, /* CFIO Reserved */ - { 0xc028, 0x30003, 0x0004, 0x040c }, /* CFIO SUS gpios_3 */ - { 0xc4a8, 0x30003, 0x0003, 0x040c }, /* CFIO SUS gpios_0 */ - { 0x0000, 0x0000, 0x0000, 0x0000 }, /* CFIO Reserved */ - { 0x0000, 0x0000, 0x0000, 0x0000 }, /* CFIO Reserved */ - { 0x8000, 0x0000, 0x0004, 0x040c }, /* CFIO SUS gpios_12 */ - { 0x8050, 0x0000, 0x0004, 0x040c }, /* CFIO SUS gpios_6 */ - { 0xc028, 0x30003, 0x0004, 0x040c }, /* CFIO SUS gpios_10 */ - { 0xc4a8, 0x30003, 0x0002, 0x040c }, /* CFIO SUS gpios_9 */ - { 0xc4a8, 0x30003, 0x0002, 0x040c }, /* CFIO SUS gpios_8 */ - { 0x0000, 0x0000, 0x0000, 0x0000 }, /* CFIO Reserved */ - { 0x0000, 0x0000, 0x0000, 0x0000 }, /* CFIO Reserved */ - { 0x8050, 0x0000, 0x0004, 0x040c }, /* CFIO SUS gpios_4 */ - { 0xc4a8, 0x30003, 0x0002, 0x040c }, /* CFIO SUS gpios_11 */ - { 0x0000, 0x0000, 0x0000, 0x0000 }, /* CFIO Reserved */ - { 0x0000, 0x0000, 0x0000, 0x0000 }, /* CFIO Reserved */ - { 0x0000, 0x0000, 0x0000, 0x0000 }, /* CFIO Reserved */ - { 0x0000, 0x0000, 0x0000, 0x0000 }, /* CFIO Reserved */ - { 0xc028, 0x30003, 0x0004, 0x040c }, /* CFIO SUS gpios_5 */ -}; - -const struct soc_gpio_map gpio_map = { - .core = { - .mode = &soc_gpio_mode, - .direction = &soc_gpio_direction, - .level = &soc_gpio_level, - .tpe = &soc_gpio_tpe, - .tne = &soc_gpio_tne, - .ts = &soc_gpio_ts, - .cfio_init = &soc_cfio_core[0], - .cfio_entrynum = sizeof(soc_cfio_core) / sizeof(struct soc_cfio), - }, - .sus = { - .mode = &soc_gpio_sus_mode, - .direction = &soc_gpio_sus_direction, - .level = &soc_gpio_sus_level, - .tpe = &soc_gpio_sus_tpe, - .tne = &soc_gpio_sus_tne, - .ts = &soc_gpio_sus_ts, - .we = &soc_gpio_sus_we, - .cfio_init = &soc_cfio_sus[0], - .cfio_entrynum = sizeof(soc_cfio_sus) / sizeof(struct soc_cfio), - }, -}; - -#endif /* ADI_RCC_DFF_GPIO_H */ diff --git a/src/mainboard/adi/rcc-dff/irq_tables.c b/src/mainboard/adi/rcc-dff/irq_tables.c deleted file mode 100644 index bca68ea548..0000000000 --- a/src/mainboard/adi/rcc-dff/irq_tables.c +++ /dev/null @@ -1,63 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007-2009 coresystems GmbH - * Copyright (C) 2011 The ChromiumOS Authors. All rights reserved. - * Copyright (C) 2013, Intel Corporation. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include - -#define PIRQA 0x08 -#define PIRQB 0x09 -#define PIRQC 0x0a -#define PIRQD 0x0b -#define PIRQE 0x0c -#define PIRQF 0x0d -#define PIRQG 0x0e -#define PIRQH 0x0f - -#define PCI_IRQS 0xDCF0 - -const struct irq_routing_table intel_irq_routing_table = { - PIRQ_SIGNATURE, /* u32 signature */ - PIRQ_VERSION, /* u16 version */ - 32+16*CONFIG_IRQ_SLOT_COUNT, /* There can be total 18 devices on the bus */ - 0x00, /* Where the interrupt router lies (bus) */ - (0x1f << 3)|0x0, /* Where the interrupt router lies (dev) */ - 0, /* IRQs devoted exclusively to PCI usage */ - 0x8086, /* Vendor */ - 0x0F1C, /* Device */ - 0, /* miniport */ - { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */ - 0x86, /* u8 checksum. */ - { - /* bus, dev|fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */ - {0x00,(0x01 << 3)|0x0, {{PIRQA, PCI_IRQS}, {PIRQB, PCI_IRQS}, {PIRQC, PCI_IRQS}, {PIRQD, PCI_IRQS}}, 0x0, 0x0}, // PCIE Port 1: INTA-PIRQA, INTB-PIRQB, INTC-PIRQC, INTD-PIRQD - {0x00,(0x02 << 3)|0x0, {{PIRQA, PCI_IRQS}, {PIRQB, PCI_IRQS}, {PIRQC, PCI_IRQS}, {PIRQD, PCI_IRQS}}, 0x0, 0x0}, // PCIE Port 2: INTA-PIRQA, INTB-PIRQB, INTC-PIRQC, INTD-PIRQD - {0x00,(0x03 << 3)|0x0, {{PIRQE, PCI_IRQS}, {PIRQF, PCI_IRQS}, {PIRQG, PCI_IRQS}, {PIRQH, PCI_IRQS}}, 0x0, 0x0}, // PCIE Port 3: INTA-PIRQE, INTB-PIRQF, INTC-PIRQG, INTD-PIRQH - {0x00,(0x04 << 3)|0x0, {{PIRQE, PCI_IRQS}, {PIRQF, PCI_IRQS}, {PIRQG, PCI_IRQS}, {PIRQH, PCI_IRQS}}, 0x0, 0x0}, // PCIE Port 4: INTA-PIRQE, INTB-PIRQF, INTC-PIRQG, INTD-PIRQH - {0x00,(0x0b << 3)|0x0, {{PIRQA, PCI_IRQS}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, // IQAT INTA-PIRQA - {0x00,(0x0f << 3)|0x0, {{PIRQA, PCI_IRQS}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, // RCEC INTA-PIRQA - {0x00,(0x13 << 3)|0x0, {{PIRQA, PCI_IRQS}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, // SMBUS #1 INTA-PIRQA - {0x00,(0x14 << 3)|0x0, {{PIRQE, PCI_IRQS}, {PIRQF, PCI_IRQS}, {PIRQG, PCI_IRQS}, {PIRQH, PCI_IRQS}}, 0x0, 0x0}, // GbE, INTA-PIRQE, INTB-PIRQF, INTC-PIRQG, INTD-PIRQH - {0x00,(0x16 << 3)|0x0, {{PIRQH, PCI_IRQS}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, // EHCI INTA-PIRQH - {0x00,(0x17 << 3)|0x0, {{PIRQD, PCI_IRQS}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, // SATA2 INTA-PIRQD - {0x00,(0x18 << 3)|0x0, {{PIRQD, PCI_IRQS}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, // SATA3 INTA-PIRQD - {0x00,(0x1f << 3)|0x0, {{0x00, 0x0000}, {PIRQC, PCI_IRQS}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, // LPC/SMBUS #0 INTB - PIRQC - } -}; - -unsigned long write_pirq_routing_table(unsigned long addr) -{ - return copy_pirq_routing_table(addr, &intel_irq_routing_table); -} diff --git a/src/mainboard/adi/rcc-dff/irqroute.c b/src/mainboard/adi/rcc-dff/irqroute.c deleted file mode 100644 index 2bf03cef68..0000000000 --- a/src/mainboard/adi/rcc-dff/irqroute.c +++ /dev/null @@ -1,19 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2013 Google Inc. - * Copyright (C) 2014 Sage Electronics Engineering, LLC. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include "irqroute.h" - -DEFINE_IRQ_ROUTES; diff --git a/src/mainboard/adi/rcc-dff/irqroute.h b/src/mainboard/adi/rcc-dff/irqroute.h deleted file mode 100644 index 43a69d9620..0000000000 --- a/src/mainboard/adi/rcc-dff/irqroute.h +++ /dev/null @@ -1,71 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2013 Google Inc. - * Copyright (C) 2014 Sage Electronics Engineering, LLC. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef IRQROUTE_H -#define IRQROUTE_H - -#include -#include - -/* - * IR01h PCIe INT(ABCD) - PIRQ ABCD - * IR02h PCIe INT(ABCD) - PIRQ ABCD - * IR03h PCIe INT(ABCD) - PIRQ ABCD - * IR04h PCIe INT(ABCD) - PIRQ ABCD - * IR0Bh IQIA INT(ABCD) - PIRQ EFGH - * IR0Eh RAS INT(A) - PIRQ A - * IR13h SMBUS1 INT(A) - PIRQ B - * IR15h GBE INT(A) - PIRQ CDEF - * IR1Dh EHCI INT(A) - PIRQ G - * IR13h SATA2.0 INT(A) - PIRQ H - * IR13h SATA3.0 INT(A) - PIRQ A - * IR1Fh LPC INT(ABCD) - PIRQ HGBC - */ - - /* Devices set as A, A, A, A evaluate as 0, and don't get set */ -#define PCI_DEV_PIRQ_ROUTES \ - PCI_DEV_PIRQ_ROUTE(PCIE_PORT1_DEV, A, B, C, D), \ - PCI_DEV_PIRQ_ROUTE(PCIE_PORT2_DEV, D, C, B, A), \ - PCI_DEV_PIRQ_ROUTE(PCIE_PORT3_DEV, E, F, G, H), \ - PCI_DEV_PIRQ_ROUTE(PCIE_PORT4_DEV, H, G, F, E), \ - PCI_DEV_PIRQ_ROUTE(IQAT_DEV, E, F, G, H), \ - PCI_DEV_PIRQ_ROUTE(HOST_BRIDGE_DEV, H, A, A, A), \ - PCI_DEV_PIRQ_ROUTE(RCEC_DEV, A, A, A, B), \ - PCI_DEV_PIRQ_ROUTE(SMBUS1_DEV, B, A, A, A), \ - PCI_DEV_PIRQ_ROUTE(GBE_DEV, C, D, E, F), \ - PCI_DEV_PIRQ_ROUTE(USB2_DEV, G, A, A, A), \ - PCI_DEV_PIRQ_ROUTE(SATA2_DEV, H, A, A, A), \ - PCI_DEV_PIRQ_ROUTE(SATA3_DEV, A, A, A, B), \ - PCI_DEV_PIRQ_ROUTE(PCU_DEV, H, G, B, C) - -/* - * Route each PIRQ[A-H] to a PIC IRQ[0-15] - * Reserved: 0, 1, 2, 8, 13 - * PS2 keyboard: 12 - * ACPI/SCI: 9 - * Floppy: 6 - */ -#define PIRQ_PIC_ROUTES \ - PIRQ_PIC(A, 10), \ - PIRQ_PIC(B, 11), \ - PIRQ_PIC(C, 10), \ - PIRQ_PIC(D, 11), \ - PIRQ_PIC(E, 14), \ - PIRQ_PIC(F, 15), \ - PIRQ_PIC(G, 14), \ - PIRQ_PIC(H, 15) - -#endif /* IRQROUTE_H */ diff --git a/src/mainboard/adi/rcc-dff/romstage.c b/src/mainboard/adi/rcc-dff/romstage.c deleted file mode 100644 index 08dd02de2e..0000000000 --- a/src/mainboard/adi/rcc-dff/romstage.c +++ /dev/null @@ -1,81 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007-2010 coresystems GmbH - * Copyright (C) 2011 The ChromiumOS Authors. All rights reserved. - * Copyright (C) 2013-2014 Sage Electronic Engineering, LLC. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include "gpio.h" - -static void interrupt_routing_config(void) -{ - u8 *ilb_base = (u8 *)(pci_read_config32(SOC_LPC_DEV, IBASE) & ~0xf); - - /* - * Initialize Interrupt Routings for each device in ilb_base_address. - * IR01 map to PCIe device 0x01 ... IR31 to device 0x1F. - * PIRQ_A maps to IRQ 16 ... PIRQ_H maps tp IRQ 23. - * This should match devicetree and the ACPI IRQ routing/ - */ - write32(ilb_base + ILB_ACTL, 0x0000); /* ACTL bit 2:0 SCIS IRQ9 */ - write16(ilb_base + ILB_IR01, 0x3210); /* IR01h IR(ABCD) - PIRQ(ABCD) */ - write16(ilb_base + ILB_IR02, 0x3210); /* IR02h IR(ABCD) - PIRQ(ABCD) */ - write16(ilb_base + ILB_IR03, 0x7654); /* IR03h IR(ABCD) - PIRQ(EFGH) */ - write16(ilb_base + ILB_IR04, 0x7654); /* IR04h IR(ABCD) - PIRQ(EFGH) */ - write16(ilb_base + ILB_IR20, 0x7654); /* IR14h IR(ABCD) - PIRQ(EFGH) */ - write16(ilb_base + ILB_IR22, 0x0007); /* IR16h IR(A) - PIRQ(H) */ - write16(ilb_base + ILB_IR23, 0x0003); /* IR17h IR(A) - PIRQ(D) */ - write16(ilb_base + ILB_IR24, 0x0003); /* IR18h IR(A) - PIRQ(D) */ - write16(ilb_base + ILB_IR31, 0x0020); /* IR1Fh IR(B) - PIRQ(C) */ -} - -/** - * /brief mainboard call for setup that needs to be done before fsp init - * - */ -void early_mainboard_romstage_entry(void) -{ - setup_soc_gpios(&gpio_map); -} - -/** - * /brief mainboard call for setup that needs to be done after fsp init - * - */ -void late_mainboard_romstage_entry(void) -{ - interrupt_routing_config(); -} - -/** - * Get function disables - most of these will be done automatically - * @param mask pointer to the function-disable bitfield - */ -void get_func_disables(uint32_t *mask) -{ - -} - -void romstage_fsp_rt_buffer_callback(FSP_INIT_RT_BUFFER *FspRtBuffer) -{ - /* No overrides needed */ - return; -} diff --git a/src/mainboard/adi/rcc-dff/thermal.h b/src/mainboard/adi/rcc-dff/thermal.h deleted file mode 100644 index 186a29207f..0000000000 --- a/src/mainboard/adi/rcc-dff/thermal.h +++ /dev/null @@ -1,29 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 The Chromium OS Authors. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef ADI_RCC_DFF_THERMAL_H -#define ADI_RCC_DFF_THERMAL_H - - -/* Temperature which OS will shutdown at */ -#define CRITICAL_TEMPERATURE 100 - -/* Temperature which OS will throttle CPU */ -#define PASSIVE_TEMPERATURE 90 - -/* Tj_max value for calculating PECI CPU temperature */ -#define MAX_TEMPERATURE 100 - -#endif diff --git a/src/mainboard/intel/littleplains/Kconfig b/src/mainboard/intel/littleplains/Kconfig deleted file mode 100644 index b5a57b798b..0000000000 --- a/src/mainboard/intel/littleplains/Kconfig +++ /dev/null @@ -1,67 +0,0 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2013-2014 Sage Electronic Engineering, LLC. -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; version 2 of the License. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## - -if BOARD_INTEL_LITTLEPLAINS - -config BOARD_SPECIFIC_OPTIONS - def_bool y - select NORTHBRIDGE_INTEL_FSP_RANGELEY - select SOUTHBRIDGE_INTEL_FSP_RANGELEY - select BOARD_ROMSIZE_KB_8192 - select HAVE_ACPI_TABLES - select HAVE_OPTION_TABLE - select HAVE_FSP_BIN if FSP_PACKAGE_DEFAULT - -config MAINBOARD_DIR - string - default intel/littleplains - -config MAINBOARD_PART_NUMBER - string - default "Little Plains" - -config MAX_CPUS - int - default 16 - -config CBFS_SIZE - hex - default 0x400000 - -config ENABLE_FSP_FAST_BOOT - bool - depends on HAVE_FSP_BIN - default y - -config FSP_PACKAGE_DEFAULT - bool "Configure defaults for the Intel FSP package" - default n - -config UART_FOR_CONSOLE - int - default 1 - help - The Little Plains board uses COM2 (2f8) for the serial console. - -config PAYLOAD_CONFIGFILE - string - depends on PAYLOAD_SEABIOS - default "$(top)/src/mainboard/$(MAINBOARDDIR)/config_seabios" - help - The Avoton/Rangeley chip does not allow devices to write into the 0xe000 - segment. This means that USB/SATA devices will not work in SeaBIOS unless - we put the SeaBIOS buffer area down in the 0x9000 segment. - -endif # BOARD_INTEL_LITTLEPLAINS diff --git a/src/mainboard/intel/littleplains/Kconfig.name b/src/mainboard/intel/littleplains/Kconfig.name deleted file mode 100644 index 8019eeefc8..0000000000 --- a/src/mainboard/intel/littleplains/Kconfig.name +++ /dev/null @@ -1,2 +0,0 @@ -config BOARD_INTEL_LITTLEPLAINS - bool "Little Plains" diff --git a/src/mainboard/intel/littleplains/Makefile.inc b/src/mainboard/intel/littleplains/Makefile.inc deleted file mode 100644 index c34ef4b006..0000000000 --- a/src/mainboard/intel/littleplains/Makefile.inc +++ /dev/null @@ -1,16 +0,0 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2014 Sage Electronics Engineering, LLC. -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; version 2 of the License. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## - -ramstage-y += irqroute.c diff --git a/src/mainboard/intel/littleplains/acpi/ec.asl b/src/mainboard/intel/littleplains/acpi/ec.asl deleted file mode 100644 index e69de29bb2..0000000000 diff --git a/src/mainboard/intel/littleplains/acpi/mainboard.asl b/src/mainboard/intel/littleplains/acpi/mainboard.asl deleted file mode 100644 index aecc2b6905..0000000000 --- a/src/mainboard/intel/littleplains/acpi/mainboard.asl +++ /dev/null @@ -1,26 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 Google Inc. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -// #define ACPI_INCLUDE_PMIO 1 /* uncomment to enable PMIO block in soc.asl */ -// #define ACPI_INCLUDE_GPIO 1 /* uncomment to enable GPIO block in soc.asl */ - -Device (PWRB) -{ - Name(_HID, EisaId("PNP0C0C")) - - // Wake - Name(_PRW, Package(){0x1d, 0x05}) -} diff --git a/src/mainboard/intel/littleplains/acpi/platform.asl b/src/mainboard/intel/littleplains/acpi/platform.asl deleted file mode 100644 index 059cd740ff..0000000000 --- a/src/mainboard/intel/littleplains/acpi/platform.asl +++ /dev/null @@ -1,22 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007-2009 coresystems GmbH - * Copyright (C) 2012 The Chromium OS Authors. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -/* The _WAK method is called on system wakeup */ - -Method(_WAK,1) -{ - Return(Package(){0,0}) -} diff --git a/src/mainboard/intel/littleplains/acpi/superio.asl b/src/mainboard/intel/littleplains/acpi/superio.asl deleted file mode 100644 index e69de29bb2..0000000000 diff --git a/src/mainboard/intel/littleplains/acpi/thermal.asl b/src/mainboard/intel/littleplains/acpi/thermal.asl deleted file mode 100644 index e69de29bb2..0000000000 diff --git a/src/mainboard/intel/littleplains/acpi_tables.c b/src/mainboard/intel/littleplains/acpi_tables.c deleted file mode 100644 index a0ebbba53c..0000000000 --- a/src/mainboard/intel/littleplains/acpi_tables.c +++ /dev/null @@ -1,74 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2012 The Chromium OS Authors. All rights reserved. - * Copyright (C) 2013 Sage Electronic Engineering, LLC. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include - -static global_nvs_t *gnvs_; - -void acpi_create_gnvs(global_nvs_t *gnvs) -{ - gnvs_ = gnvs; - memset((void *)gnvs, 0, sizeof(*gnvs)); - gnvs->apic = 1; - gnvs->mpen = 1; /* Enable Multi Processing */ - gnvs->pcnt = dev_count_cpu(); - - /* Enable USB ports in S3 */ - gnvs->s3u0 = 1; - gnvs->s3u1 = 1; - - /* - * Enable Front USB ports in S5 by default - * to be consistent with back port behavior - */ - gnvs->s5u0 = 1; - gnvs->s5u1 = 1; - - /* IGD Displays */ - gnvs->ndid = 3; - gnvs->did[0] = 0x80000100; - gnvs->did[1] = 0x80000240; - gnvs->did[2] = 0x80000410; - gnvs->did[3] = 0x80000410; - gnvs->did[4] = 0x00000005; - -} - -unsigned long acpi_fill_madt(unsigned long current) -{ - /* Local APICs */ - current = acpi_create_madt_lapics(current); - - /* IOAPIC */ - current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, - 2, IO_APIC_ADDR, 0); - - /* INT_SRC_OVR */ - current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) - current, 0, 0, 2, 0); - current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) - current, 0, 9, 9, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_HIGH); - - return current; -} diff --git a/src/mainboard/intel/littleplains/board_info.txt b/src/mainboard/intel/littleplains/board_info.txt deleted file mode 100644 index f49af8aac5..0000000000 --- a/src/mainboard/intel/littleplains/board_info.txt +++ /dev/null @@ -1,4 +0,0 @@ -Category: eval -ROM protocol: SPI -Flashrom support: y -Release year: 2014 diff --git a/src/mainboard/intel/littleplains/cmos.layout b/src/mainboard/intel/littleplains/cmos.layout deleted file mode 100644 index 7c623c0085..0000000000 --- a/src/mainboard/intel/littleplains/cmos.layout +++ /dev/null @@ -1,104 +0,0 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2007-2008 coresystems GmbH -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; version 2 of the License. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## - -# ----------------------------------------------------------------- -entries - -# ----------------------------------------------------------------- -# Status Register A -# ----------------------------------------------------------------- -# Status Register B -# ----------------------------------------------------------------- -# Status Register C -#96 4 r 0 status_c_rsvd -#100 1 r 0 uf_flag -#101 1 r 0 af_flag -#102 1 r 0 pf_flag -#103 1 r 0 irqf_flag -# ----------------------------------------------------------------- -# Status Register D -#104 7 r 0 status_d_rsvd -#111 1 r 0 valid_cmos_ram -# ----------------------------------------------------------------- -# Diagnostic Status Register -#112 8 r 0 diag_rsvd1 - -# ----------------------------------------------------------------- -0 120 r 0 reserved_memory -#120 264 r 0 unused - -# ----------------------------------------------------------------- -# RTC_BOOT_BYTE (coreboot hardcoded) -384 1 e 4 boot_option -388 4 h 0 reboot_counter -#390 2 r 0 unused? - -# ----------------------------------------------------------------- -# coreboot config options: console -#392 3 r 0 unused -395 4 e 6 debug_level -#399 1 r 0 unused - -# coreboot config options: cpu -400 1 e 2 hyper_threading -#401 7 r 0 unused - -# coreboot config options: southbridge -408 1 e 1 nmi -409 2 e 7 power_on_after_fail -#411 5 r 0 unused - -# MRC Scrambler Seed values -896 32 r 0 mrc_scrambler_seed -928 32 r 0 mrc_scrambler_seed_s3 - -# coreboot config options: check sums -984 16 h 0 check_sum -#1000 24 r 0 amd_reserved - -#save timestamps in pre-ram boot areas -1720 64 h 0 timestamp_value1 -1784 64 h 0 timestamp_value2 -1848 64 h 0 timestamp_value3 -1912 64 h 0 timestamp_value4 -1976 64 h 0 timestamp_value5 - -# ----------------------------------------------------------------- - -enumerations - -#ID value text -1 0 Disable -1 1 Enable -2 0 Enable -2 1 Disable -4 0 Fallback -4 1 Normal -6 0 Emergency -6 1 Alert -6 2 Critical -6 3 Error -6 4 Warning -6 5 Notice -6 6 Info -6 7 Debug -6 8 Spew -7 0 Disable -7 1 Enable -7 2 Keep -# ----------------------------------------------------------------- -checksums - -checksum 392 415 984 diff --git a/src/mainboard/intel/littleplains/config_seabios b/src/mainboard/intel/littleplains/config_seabios deleted file mode 100644 index f688f2b530..0000000000 --- a/src/mainboard/intel/littleplains/config_seabios +++ /dev/null @@ -1,5 +0,0 @@ -# The Avoton/Rangeley chip does not allow devices to write into the 0xe000 -# segment. This means that USB/SATA devices will not work in SeaBIOS unless -# we put the SeaBIOS buffer area down in the 0x9000 segment. - -# CONFIG_MALLOC_UPPERMEMORY is not set diff --git a/src/mainboard/intel/littleplains/devicetree.cb b/src/mainboard/intel/littleplains/devicetree.cb deleted file mode 100644 index 0cb73f8a02..0000000000 --- a/src/mainboard/intel/littleplains/devicetree.cb +++ /dev/null @@ -1,62 +0,0 @@ -# -# This file is part of the coreboot project. -# -# Copyright (C) 2013 Sage Electronic Engineering, LLC. -# -# This program is free software; you can redistribute it and/or modify -# it under the terms of the GNU General Public License as published by -# the Free Software Foundation; version 2 of the License. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -chip northbridge/intel/fsp_rangeley - - device cpu_cluster 0 on - chip cpu/intel/fsp_model_406dx - device lapic 0 on end - # Magic APIC ID to locate this chip - device lapic 0xACAC off end - - register "c1_battery" = "3" # ACPI(C1) = MWAIT(C3) - register "c2_battery" = "4" # ACPI(C2) = MWAIT(C6) - register "c3_battery" = "5" # ACPI(C3) = MWAIT(C7) - - register "c1_acpower" = "3" # ACPI(C1) = MWAIT(C3) - register "c2_acpower" = "4" # ACPI(C2) = MWAIT(C6) - register "c3_acpower" = "5" # ACPI(C3) = MWAIT(C7) - end - end - - device domain 0 on - device pci 00.0 on end # host bridge - device pci 1.0 on end # PCIe Port #1 - device pci 2.0 on end # PCIe Port #2 - device pci 3.0 on end # PCIe Port #3 - device pci 4.0 on end # PCIe Port #4 - chip southbridge/intel/fsp_rangeley # Rangeley SB - - register "ide_legacy_combined" = "0x0" - register "sata_ahci" = "0x1" - register "sata_port_map" = "0x0f" - - register "fadt_pm_profile" = "PM_DESKTOP" - register "fadt_boot_arch" = "ACPI_FADT_LEGACY_FREE" - - device pci 0b.0 on end # IQIA - device pci 0e.0 on end # RAS - device pci 13.0 on end # SMBus 1 - device pci 14.0 on end # GbE 0 - device pci 14.1 on end # GbE 1 - device pci 14.2 on end # GbE 2 - device pci 14.3 on end # GbE 3 - device pci 16.0 on end # USB EHCI - device pci 17.0 on end # SATA 2.0 - device pci 18.0 on end # SATA 3.0 - device pci 1f.0 on end # LPC bridge - device pci 1f.3 on end # SMBus 0 - end - end -end diff --git a/src/mainboard/intel/littleplains/dsdt.asl b/src/mainboard/intel/littleplains/dsdt.asl deleted file mode 100644 index 4aad8a8b15..0000000000 --- a/src/mainboard/intel/littleplains/dsdt.asl +++ /dev/null @@ -1,54 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007-2009 coresystems GmbH - * Copyright (C) 2011 The ChromiumOS Authors. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -DefinitionBlock( - "dsdt.aml", - "DSDT", - 0x02, // DSDT revision: ACPI v2.0 and up - OEM_ID, - ACPI_TABLE_CREATOR, - 0x20110725 // OEM revision -) -{ - // Include mainboard configuration - #include - - // Include debug methods - #include - - // Some generic macros - #include - #include "acpi/platform.asl" - - // global NVS and variables - #include - - #include "acpi/thermal.asl" - - #include - - Scope (\_SB) { - Device (PCI0) - { - #include - #include - } - } - - /* Chipset specific sleep states */ - #include -} diff --git a/src/mainboard/intel/littleplains/fadt.c b/src/mainboard/intel/littleplains/fadt.c deleted file mode 100644 index 3d8db00f9f..0000000000 --- a/src/mainboard/intel/littleplains/fadt.c +++ /dev/null @@ -1,35 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2014 Sage Electronic Engineering, LLC. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include - -void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt) -{ - acpi_fill_in_fadt(fadt,facs,dsdt); - -#define PLATFORM_HAS_FADT_CUSTOMIZATIONS 0 - - - /* - * Platform specific customizations go here. - * Update the #define above if customizations are added. - */ - - -#if PLATFORM_HAS_FADT_CUSTOMIZATIONS - header->checksum = acpi_checksum((void *) fadt, sizeof(acpi_fadt_t)); -#endif -} diff --git a/src/mainboard/intel/littleplains/gpio.h b/src/mainboard/intel/littleplains/gpio.h deleted file mode 100644 index 6fabe6ecec..0000000000 --- a/src/mainboard/intel/littleplains/gpio.h +++ /dev/null @@ -1,176 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 The Chromium OS Authors. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef LITTLEPLAINS_GPIO_H -#define LITTLEPLAINS_GPIO_H - -#include - -/* Core GPIO */ -const struct soc_gpio soc_gpio_mode = { - .gpio15 = GPIO_MODE_GPIO, /* Board ID GPIO */ - .gpio17 = GPIO_MODE_GPIO, /* Board ID GPIO */ -}; - -const struct soc_gpio soc_gpio_direction = { - .gpio15 = GPIO_DIR_INPUT, /* Board ID GPIO */ - .gpio17 = GPIO_DIR_INPUT, /* Board ID GPIO */ -}; - -const struct soc_gpio soc_gpio_level = { -}; - -const struct soc_gpio soc_gpio_tpe = { -}; - -const struct soc_gpio soc_gpio_tne = { -}; - -const struct soc_gpio soc_gpio_ts = { -}; - -/* Keep the CFIO struct in register order, not gpio order. */ -const struct soc_cfio soc_cfio_core[] = { - { 0x8000, 0x0000, 0x0004, 0x040c }, /* CFIO gpios_28 */ - { 0x8000, 0x0000, 0x0002, 0x040c }, /* CFIO gpios_27 */ - { 0x8500, 0x0000, 0x0002, 0x040c }, /* CFIO gpios_26 */ - { 0x8480, 0x0000, 0x0002, 0x040c }, /* CFIO gpios_21 */ - { 0x8480, 0x0000, 0x0002, 0x040c }, /* CFIO gpios_22 */ - { 0x8480, 0x0000, 0x0002, 0x040c }, /* CFIO gpios_23 */ - { 0x8000, 0x0000, 0x0004, 0x040c }, /* CFIO gpios_25 */ - { 0x8480, 0x0000, 0x0002, 0x040c }, /* CFIO gpios_24 */ - { 0x80c028, 0x30003, 0x0004, 0x040c }, /* CFIO gpios_19 */ - { 0x80c028, 0x30003, 0x0004, 0x040c }, /* CFIO gpios_20 */ - { 0xc028, 0x30003, 0x0004, 0x040c }, /* CFIO gpios_18 */ - { 0x04a9, 0x30003, 0x0002, 0x040c }, /* CFIO gpios_17 */ - { 0x80c028, 0x30003, 0x0004, 0x040c }, /* CFIO gpios_7 */ - { 0xc028, 0x30003, 0x0004, 0x040c }, /* CFIO gpios_4 */ - { 0xc028, 0x30003, 0x0004, 0x040c }, /* CFIO gpios_5 */ - { 0xc528, 0x30003, 0x0002, 0x040c }, /* CFIO gpios_6 */ - { 0xc028, 0x30003, 0x0004, 0x040c }, /* CFIO gpios_1 */ - { 0xc028, 0x20002, 0x0004, 0x040c }, /* CFIO gpios_2 */ - { 0xc028, 0x20002, 0x0004, 0x040c }, /* CFIO gpios_3 */ - { 0xc528, 0x30003, 0x0002, 0x040c }, /* CFIO gpios_0 */ - { 0x0000, 0x0000, 0x0000, 0x0000 }, /* CFIO Reserved */ - { 0xc4a8, 0x30003, 0x0002, 0x040c }, /* CFIO gpios_10 */ - { 0xc4a8, 0x30003, 0x0002, 0x040c }, /* CFIO gpios_13 */ - { 0xc4a8, 0x30003, 0x0000, 0x040c }, /* CFIO gpios_14 */ - { 0xc4a8, 0x30003, 0x0002, 0x040c }, /* CFIO gpios_11 */ - { 0xc4a8, 0x30003, 0x0000, 0x040c }, /* CFIO gpios_8 */ - { 0xc4a8, 0x30003, 0x0002, 0x040c }, /* CFIO gpios_9 */ - { 0xc4a8, 0x30003, 0x0000, 0x040c }, /* CFIO gpios_12 */ - { 0xc4a8, 0x30003, 0x0002, 0x040c }, /* CFIO gpios_29 */ - { 0xc4a8, 0x30003, 0x0002, 0x040c }, /* CFIO gpios_30 */ - { 0x04a9, 0x30003, 0x0002, 0x040c }, /* CFIO gpios_15 */ - { 0xc028, 0x30003, 0x0004, 0x040c }, /* CFIO gpios_16 */ -}; - -/* SUS GPIO */ -const struct soc_gpio soc_gpio_sus_mode = { - .gpio2 = GPIO_MODE_GPIO, - .gpio19 = GPIO_MODE_GPIO -}; - -const struct soc_gpio soc_gpio_sus_direction = { - .gpio2 = GPIO_DIR_INPUT, - .gpio19 = GPIO_DIR_INPUT -}; - -const struct soc_gpio soc_gpio_sus_level = { -}; - -const struct soc_gpio soc_gpio_sus_tpe = { -}; - -const struct soc_gpio soc_gpio_sus_tne = { -}; - -const struct soc_gpio soc_gpio_sus_ts = { -}; - -const struct soc_gpio soc_gpio_sus_we = { -}; - - -/* Keep the CFIO struct in register order, not gpio order. */ -const struct soc_cfio soc_cfio_sus[] = { - { 0xc028, 0x30003, 0x0004, 0x040c }, /* CFIO SUS gpios_21 */ - { 0xc028, 0x30003, 0x0004, 0x040c }, /* CFIO SUS gpios_20 */ - { 0xc028, 0x30003, 0x0004, 0x040c }, /* CFIO SUS gpios_19 */ - { 0xc028, 0x30003, 0x0004, 0x040c }, /* CFIO SUS gpios_22 */ - { 0xc4a8, 0x30003, 0x0002, 0x040c }, /* CFIO SUS gpios_17 */ - { 0xc4a8, 0x30003, 0x0002, 0x040c }, /* CFIO SUS gpios_18 */ - { 0x0000, 0x0000, 0x0000, 0x0000 }, /* CFIO Reserved */ - { 0x0000, 0x0000, 0x0000, 0x0000 }, /* CFIO Reserved */ - { 0x0000, 0x0000, 0x0000, 0x0000 }, /* CFIO Reserved */ - { 0xc4a8, 0x30003, 0x0002, 0x040c }, /* CFIO SUS gpios_14 */ - { 0xc028, 0x30003, 0x0004, 0x040c }, /* CFIO SUS gpios_13 */ - { 0xc028, 0x30003, 0x0004, 0x040c }, /* CFIO SUS gpios_15 */ - { 0xc028, 0x30003, 0x0004, 0x040c }, /* CFIO SUS gpios_16 */ - { 0xc4a8, 0x30003, 0x0002, 0x040c }, /* CFIO SUS gpios_25 */ - { 0xc4a8, 0x30003, 0x0002, 0x040c }, /* CFIO SUS gpios_24 */ - { 0xc4a8, 0x30003, 0x0002, 0x040c }, /* CFIO SUS gpios_26 */ - { 0xc4a8, 0x30003, 0x0002, 0x040c }, /* CFIO SUS gpios_27 */ - { 0xc4a8, 0x30003, 0x0002, 0x040c }, /* CFIO SUS gpios_23 */ - { 0xc4a8, 0x30003, 0x0003, 0x040c }, /* CFIO SUS gpios_2 */ - { 0xc4a8, 0x30003, 0x0003, 0x040c }, /* CFIO SUS gpios_1 */ - { 0x8050, 0x0000, 0x0004, 0x040c }, /* CFIO SUS gpios_7 */ - { 0x0000, 0x0000, 0x0000, 0x0000 }, /* CFIO Reserved */ - { 0x0000, 0x0000, 0x0000, 0x0000 }, /* CFIO Reserved */ - { 0xc028, 0x30003, 0x0004, 0x040c }, /* CFIO SUS gpios_3 */ - { 0xc4a8, 0x30003, 0x0003, 0x040c }, /* CFIO SUS gpios_0 */ - { 0x0000, 0x0000, 0x0000, 0x0000 }, /* CFIO Reserved */ - { 0x0000, 0x0000, 0x0000, 0x0000 }, /* CFIO Reserved */ - { 0x8000, 0x0000, 0x0004, 0x040c }, /* CFIO SUS gpios_12 */ - { 0x8050, 0x0000, 0x0004, 0x040c }, /* CFIO SUS gpios_6 */ - { 0xc028, 0x30003, 0x0004, 0x040c }, /* CFIO SUS gpios_10 */ - { 0xc4a8, 0x30003, 0x0002, 0x040c }, /* CFIO SUS gpios_9 */ - { 0xc4a8, 0x30003, 0x0002, 0x040c }, /* CFIO SUS gpios_8 */ - { 0x0000, 0x0000, 0x0000, 0x0000 }, /* CFIO Reserved */ - { 0x0000, 0x0000, 0x0000, 0x0000 }, /* CFIO Reserved */ - { 0x8050, 0x0000, 0x0004, 0x040c }, /* CFIO SUS gpios_4 */ - { 0xc4a8, 0x30003, 0x0002, 0x040c }, /* CFIO SUS gpios_11 */ - { 0x0000, 0x0000, 0x0000, 0x0000 }, /* CFIO Reserved */ - { 0x0000, 0x0000, 0x0000, 0x0000 }, /* CFIO Reserved */ - { 0x0000, 0x0000, 0x0000, 0x0000 }, /* CFIO Reserved */ - { 0x0000, 0x0000, 0x0000, 0x0000 }, /* CFIO Reserved */ - { 0xc028, 0x30003, 0x0004, 0x040c }, /* CFIO SUS gpios_5 */ -}; - -const struct soc_gpio_map gpio_map = { - .core = { - .mode = &soc_gpio_mode, - .direction = &soc_gpio_direction, - .level = &soc_gpio_level, - .tpe = &soc_gpio_tpe, - .tne = &soc_gpio_tne, - .ts = &soc_gpio_ts, - .cfio_init = &soc_cfio_core[0], - .cfio_entrynum = sizeof(soc_cfio_core) / sizeof(struct soc_cfio), - }, - .sus = { - .mode = &soc_gpio_sus_mode, - .direction = &soc_gpio_sus_direction, - .level = &soc_gpio_sus_level, - .tpe = &soc_gpio_sus_tpe, - .tne = &soc_gpio_sus_tne, - .ts = &soc_gpio_sus_ts, - .we = &soc_gpio_sus_we, - .cfio_init = &soc_cfio_sus[0], - .cfio_entrynum = sizeof(soc_cfio_sus) / sizeof(struct soc_cfio), - }, -}; - -#endif /* LITTLEPLAINS_GPIO_H */ diff --git a/src/mainboard/intel/littleplains/irq_tables.c b/src/mainboard/intel/littleplains/irq_tables.c deleted file mode 100644 index bca68ea548..0000000000 --- a/src/mainboard/intel/littleplains/irq_tables.c +++ /dev/null @@ -1,63 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007-2009 coresystems GmbH - * Copyright (C) 2011 The ChromiumOS Authors. All rights reserved. - * Copyright (C) 2013, Intel Corporation. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include - -#define PIRQA 0x08 -#define PIRQB 0x09 -#define PIRQC 0x0a -#define PIRQD 0x0b -#define PIRQE 0x0c -#define PIRQF 0x0d -#define PIRQG 0x0e -#define PIRQH 0x0f - -#define PCI_IRQS 0xDCF0 - -const struct irq_routing_table intel_irq_routing_table = { - PIRQ_SIGNATURE, /* u32 signature */ - PIRQ_VERSION, /* u16 version */ - 32+16*CONFIG_IRQ_SLOT_COUNT, /* There can be total 18 devices on the bus */ - 0x00, /* Where the interrupt router lies (bus) */ - (0x1f << 3)|0x0, /* Where the interrupt router lies (dev) */ - 0, /* IRQs devoted exclusively to PCI usage */ - 0x8086, /* Vendor */ - 0x0F1C, /* Device */ - 0, /* miniport */ - { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */ - 0x86, /* u8 checksum. */ - { - /* bus, dev|fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */ - {0x00,(0x01 << 3)|0x0, {{PIRQA, PCI_IRQS}, {PIRQB, PCI_IRQS}, {PIRQC, PCI_IRQS}, {PIRQD, PCI_IRQS}}, 0x0, 0x0}, // PCIE Port 1: INTA-PIRQA, INTB-PIRQB, INTC-PIRQC, INTD-PIRQD - {0x00,(0x02 << 3)|0x0, {{PIRQA, PCI_IRQS}, {PIRQB, PCI_IRQS}, {PIRQC, PCI_IRQS}, {PIRQD, PCI_IRQS}}, 0x0, 0x0}, // PCIE Port 2: INTA-PIRQA, INTB-PIRQB, INTC-PIRQC, INTD-PIRQD - {0x00,(0x03 << 3)|0x0, {{PIRQE, PCI_IRQS}, {PIRQF, PCI_IRQS}, {PIRQG, PCI_IRQS}, {PIRQH, PCI_IRQS}}, 0x0, 0x0}, // PCIE Port 3: INTA-PIRQE, INTB-PIRQF, INTC-PIRQG, INTD-PIRQH - {0x00,(0x04 << 3)|0x0, {{PIRQE, PCI_IRQS}, {PIRQF, PCI_IRQS}, {PIRQG, PCI_IRQS}, {PIRQH, PCI_IRQS}}, 0x0, 0x0}, // PCIE Port 4: INTA-PIRQE, INTB-PIRQF, INTC-PIRQG, INTD-PIRQH - {0x00,(0x0b << 3)|0x0, {{PIRQA, PCI_IRQS}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, // IQAT INTA-PIRQA - {0x00,(0x0f << 3)|0x0, {{PIRQA, PCI_IRQS}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, // RCEC INTA-PIRQA - {0x00,(0x13 << 3)|0x0, {{PIRQA, PCI_IRQS}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, // SMBUS #1 INTA-PIRQA - {0x00,(0x14 << 3)|0x0, {{PIRQE, PCI_IRQS}, {PIRQF, PCI_IRQS}, {PIRQG, PCI_IRQS}, {PIRQH, PCI_IRQS}}, 0x0, 0x0}, // GbE, INTA-PIRQE, INTB-PIRQF, INTC-PIRQG, INTD-PIRQH - {0x00,(0x16 << 3)|0x0, {{PIRQH, PCI_IRQS}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, // EHCI INTA-PIRQH - {0x00,(0x17 << 3)|0x0, {{PIRQD, PCI_IRQS}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, // SATA2 INTA-PIRQD - {0x00,(0x18 << 3)|0x0, {{PIRQD, PCI_IRQS}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, // SATA3 INTA-PIRQD - {0x00,(0x1f << 3)|0x0, {{0x00, 0x0000}, {PIRQC, PCI_IRQS}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, // LPC/SMBUS #0 INTB - PIRQC - } -}; - -unsigned long write_pirq_routing_table(unsigned long addr) -{ - return copy_pirq_routing_table(addr, &intel_irq_routing_table); -} diff --git a/src/mainboard/intel/littleplains/irqroute.c b/src/mainboard/intel/littleplains/irqroute.c deleted file mode 100644 index 2bf03cef68..0000000000 --- a/src/mainboard/intel/littleplains/irqroute.c +++ /dev/null @@ -1,19 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2013 Google Inc. - * Copyright (C) 2014 Sage Electronics Engineering, LLC. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include "irqroute.h" - -DEFINE_IRQ_ROUTES; diff --git a/src/mainboard/intel/littleplains/irqroute.h b/src/mainboard/intel/littleplains/irqroute.h deleted file mode 100644 index eb44fde6cf..0000000000 --- a/src/mainboard/intel/littleplains/irqroute.h +++ /dev/null @@ -1,69 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2013 Google Inc. - * Copyright (C) 2014 Sage Electronics Engineering, LLC. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef IRQROUTE_H -#define IRQROUTE_H - -#include -#include - -/* - * IR01h PCIe INT(ABCD) - PIRQ ABCD - * IR02h PCIe INT(ABCD) - PIRQ ABCD - * IR03h PCIe INT(ABCD) - PIRQ ABCD - * IR04h PCIe INT(ABCD) - PIRQ ABCD - * IR0Bh IQIA INT(ABCD) - PIRQ EFGH - * IR0Eh RAS INT(A) - PIRQ A - * IR13h SMBUS1 INT(A) - PIRQ B - * IR15h GBE INT(A) - PIRQ CDEF - * IR1Dh EHCI INT(A) - PIRQ G - * IR13h SATA2.0 INT(A) - PIRQ H - * IR13h SATA3.0 INT(A) - PIRQ A - * IR1Fh LPC INT(ABCD) - PIRQ HGBC - */ -#define PCI_DEV_PIRQ_ROUTES \ - PCI_DEV_PIRQ_ROUTE(PCIE_PORT1_DEV, A, B, C, D), \ - PCI_DEV_PIRQ_ROUTE(PCIE_PORT2_DEV, D, C, B, A), \ - PCI_DEV_PIRQ_ROUTE(PCIE_PORT3_DEV, E, F, G, H), \ - PCI_DEV_PIRQ_ROUTE(PCIE_PORT4_DEV, H, G, F, E), \ - PCI_DEV_PIRQ_ROUTE(IQAT_DEV, E, F, G, H), \ - PCI_DEV_PIRQ_ROUTE(HOST_BRIDGE_DEV, H, A, A, A), \ - PCI_DEV_PIRQ_ROUTE(RCEC_DEV, A, A, A, B), \ - PCI_DEV_PIRQ_ROUTE(SMBUS1_DEV, B, A, A, A), \ - PCI_DEV_PIRQ_ROUTE(GBE_DEV, C, D, E, F), \ - PCI_DEV_PIRQ_ROUTE(USB2_DEV, G, A, A, A), \ - PCI_DEV_PIRQ_ROUTE(SATA2_DEV, H, A, A, A), \ - PCI_DEV_PIRQ_ROUTE(SATA3_DEV, A, A, A, B), \ - PCI_DEV_PIRQ_ROUTE(PCU_DEV, H, G, B, C) - -/* - * Route each PIRQ[A-H] to a PIC IRQ[0-15] - * Reserved: 0, 1, 2, 8, 13 - * PS2 keyboard: 12 - * ACPI/SCI: 9 - * Floppy: 6 - */ -#define PIRQ_PIC_ROUTES \ - PIRQ_PIC(A, 10), \ - PIRQ_PIC(B, 11), \ - PIRQ_PIC(C, 10), \ - PIRQ_PIC(D, 11), \ - PIRQ_PIC(E, 14), \ - PIRQ_PIC(F, 15), \ - PIRQ_PIC(G, 14), \ - PIRQ_PIC(H, 15) - -#endif /* IRQROUTE_H */ diff --git a/src/mainboard/intel/littleplains/romstage.c b/src/mainboard/intel/littleplains/romstage.c deleted file mode 100644 index 08dd02de2e..0000000000 --- a/src/mainboard/intel/littleplains/romstage.c +++ /dev/null @@ -1,81 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007-2010 coresystems GmbH - * Copyright (C) 2011 The ChromiumOS Authors. All rights reserved. - * Copyright (C) 2013-2014 Sage Electronic Engineering, LLC. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include "gpio.h" - -static void interrupt_routing_config(void) -{ - u8 *ilb_base = (u8 *)(pci_read_config32(SOC_LPC_DEV, IBASE) & ~0xf); - - /* - * Initialize Interrupt Routings for each device in ilb_base_address. - * IR01 map to PCIe device 0x01 ... IR31 to device 0x1F. - * PIRQ_A maps to IRQ 16 ... PIRQ_H maps tp IRQ 23. - * This should match devicetree and the ACPI IRQ routing/ - */ - write32(ilb_base + ILB_ACTL, 0x0000); /* ACTL bit 2:0 SCIS IRQ9 */ - write16(ilb_base + ILB_IR01, 0x3210); /* IR01h IR(ABCD) - PIRQ(ABCD) */ - write16(ilb_base + ILB_IR02, 0x3210); /* IR02h IR(ABCD) - PIRQ(ABCD) */ - write16(ilb_base + ILB_IR03, 0x7654); /* IR03h IR(ABCD) - PIRQ(EFGH) */ - write16(ilb_base + ILB_IR04, 0x7654); /* IR04h IR(ABCD) - PIRQ(EFGH) */ - write16(ilb_base + ILB_IR20, 0x7654); /* IR14h IR(ABCD) - PIRQ(EFGH) */ - write16(ilb_base + ILB_IR22, 0x0007); /* IR16h IR(A) - PIRQ(H) */ - write16(ilb_base + ILB_IR23, 0x0003); /* IR17h IR(A) - PIRQ(D) */ - write16(ilb_base + ILB_IR24, 0x0003); /* IR18h IR(A) - PIRQ(D) */ - write16(ilb_base + ILB_IR31, 0x0020); /* IR1Fh IR(B) - PIRQ(C) */ -} - -/** - * /brief mainboard call for setup that needs to be done before fsp init - * - */ -void early_mainboard_romstage_entry(void) -{ - setup_soc_gpios(&gpio_map); -} - -/** - * /brief mainboard call for setup that needs to be done after fsp init - * - */ -void late_mainboard_romstage_entry(void) -{ - interrupt_routing_config(); -} - -/** - * Get function disables - most of these will be done automatically - * @param mask pointer to the function-disable bitfield - */ -void get_func_disables(uint32_t *mask) -{ - -} - -void romstage_fsp_rt_buffer_callback(FSP_INIT_RT_BUFFER *FspRtBuffer) -{ - /* No overrides needed */ - return; -} diff --git a/src/mainboard/intel/littleplains/thermal.h b/src/mainboard/intel/littleplains/thermal.h deleted file mode 100644 index 14f5fa7dd2..0000000000 --- a/src/mainboard/intel/littleplains/thermal.h +++ /dev/null @@ -1,29 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 The Chromium OS Authors. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef LITTLEPLAINS_THERMAL_H -#define LITTLEPLAINS_THERMAL_H - - -/* Temperature which OS will shutdown at */ -#define CRITICAL_TEMPERATURE 100 - -/* Temperature which OS will throttle CPU */ -#define PASSIVE_TEMPERATURE 90 - -/* Tj_max value for calculating PECI CPU temperature */ -#define MAX_TEMPERATURE 100 - -#endif diff --git a/src/mainboard/intel/mohonpeak/Kconfig b/src/mainboard/intel/mohonpeak/Kconfig deleted file mode 100644 index de91ca4835..0000000000 --- a/src/mainboard/intel/mohonpeak/Kconfig +++ /dev/null @@ -1,76 +0,0 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2013-2014 Sage Electronic Engineering, LLC. -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; version 2 of the License. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## - -if BOARD_INTEL_MOHONPEAK - -config BOARD_SPECIFIC_OPTIONS - def_bool y - select NORTHBRIDGE_INTEL_FSP_RANGELEY - select SOUTHBRIDGE_INTEL_FSP_RANGELEY - select BOARD_ROMSIZE_KB_2048 #actual chip is 8MB - select HAVE_ACPI_TABLES - select HAVE_OPTION_TABLE - select HAVE_FSP_BIN if FSP_PACKAGE_DEFAULT - -config MAINBOARD_DIR - string - default intel/mohonpeak - -config MAINBOARD_PART_NUMBER - string - default "Mohon Peak CRB" - -config MAX_CPUS - int - default 16 - -config FSP_FILE - string - default "../intel/fsp/rangeley/FvFsp.bin" - -config CBFS_SIZE - hex - default 0x00200000 - -config ENABLE_FSP_FAST_BOOT - bool - depends on HAVE_FSP_BIN - default y - -config VIRTUAL_ROM_SIZE - hex - depends on ENABLE_FSP_FAST_BOOT - default 0x400000 - -config FSP_PACKAGE_DEFAULT - bool "Configure defaults for the Intel FSP package" - default n - -config UART_FOR_CONSOLE - int - default 1 - help - The Mohon Peak board uses COM2 (2f8) for the serial console. - -config PAYLOAD_CONFIGFILE - string - depends on PAYLOAD_SEABIOS - default "$(top)/src/mainboard/$(MAINBOARDDIR)/config_seabios" - help - The Avoton/Rangeley chip does not allow devices to write into the 0xe000 - segment. This means that USB/SATA devices will not work in SeaBIOS unless - we put the SeaBIOS buffer area down in the 0x9000 segment. - -endif # BOARD_INTEL_MOHONPEAK diff --git a/src/mainboard/intel/mohonpeak/Kconfig.name b/src/mainboard/intel/mohonpeak/Kconfig.name deleted file mode 100644 index 2fc6540d06..0000000000 --- a/src/mainboard/intel/mohonpeak/Kconfig.name +++ /dev/null @@ -1,2 +0,0 @@ -config BOARD_INTEL_MOHONPEAK - bool "Mohon Peak CRB" diff --git a/src/mainboard/intel/mohonpeak/Makefile.inc b/src/mainboard/intel/mohonpeak/Makefile.inc deleted file mode 100644 index c34ef4b006..0000000000 --- a/src/mainboard/intel/mohonpeak/Makefile.inc +++ /dev/null @@ -1,16 +0,0 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2014 Sage Electronics Engineering, LLC. -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; version 2 of the License. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## - -ramstage-y += irqroute.c diff --git a/src/mainboard/intel/mohonpeak/acpi/ec.asl b/src/mainboard/intel/mohonpeak/acpi/ec.asl deleted file mode 100644 index e69de29bb2..0000000000 diff --git a/src/mainboard/intel/mohonpeak/acpi/mainboard.asl b/src/mainboard/intel/mohonpeak/acpi/mainboard.asl deleted file mode 100644 index aecc2b6905..0000000000 --- a/src/mainboard/intel/mohonpeak/acpi/mainboard.asl +++ /dev/null @@ -1,26 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 Google Inc. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -// #define ACPI_INCLUDE_PMIO 1 /* uncomment to enable PMIO block in soc.asl */ -// #define ACPI_INCLUDE_GPIO 1 /* uncomment to enable GPIO block in soc.asl */ - -Device (PWRB) -{ - Name(_HID, EisaId("PNP0C0C")) - - // Wake - Name(_PRW, Package(){0x1d, 0x05}) -} diff --git a/src/mainboard/intel/mohonpeak/acpi/platform.asl b/src/mainboard/intel/mohonpeak/acpi/platform.asl deleted file mode 100644 index 059cd740ff..0000000000 --- a/src/mainboard/intel/mohonpeak/acpi/platform.asl +++ /dev/null @@ -1,22 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007-2009 coresystems GmbH - * Copyright (C) 2012 The Chromium OS Authors. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -/* The _WAK method is called on system wakeup */ - -Method(_WAK,1) -{ - Return(Package(){0,0}) -} diff --git a/src/mainboard/intel/mohonpeak/acpi/superio.asl b/src/mainboard/intel/mohonpeak/acpi/superio.asl deleted file mode 100644 index e69de29bb2..0000000000 diff --git a/src/mainboard/intel/mohonpeak/acpi/thermal.asl b/src/mainboard/intel/mohonpeak/acpi/thermal.asl deleted file mode 100644 index e69de29bb2..0000000000 diff --git a/src/mainboard/intel/mohonpeak/acpi_tables.c b/src/mainboard/intel/mohonpeak/acpi_tables.c deleted file mode 100644 index a0ebbba53c..0000000000 --- a/src/mainboard/intel/mohonpeak/acpi_tables.c +++ /dev/null @@ -1,74 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2012 The Chromium OS Authors. All rights reserved. - * Copyright (C) 2013 Sage Electronic Engineering, LLC. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include - -static global_nvs_t *gnvs_; - -void acpi_create_gnvs(global_nvs_t *gnvs) -{ - gnvs_ = gnvs; - memset((void *)gnvs, 0, sizeof(*gnvs)); - gnvs->apic = 1; - gnvs->mpen = 1; /* Enable Multi Processing */ - gnvs->pcnt = dev_count_cpu(); - - /* Enable USB ports in S3 */ - gnvs->s3u0 = 1; - gnvs->s3u1 = 1; - - /* - * Enable Front USB ports in S5 by default - * to be consistent with back port behavior - */ - gnvs->s5u0 = 1; - gnvs->s5u1 = 1; - - /* IGD Displays */ - gnvs->ndid = 3; - gnvs->did[0] = 0x80000100; - gnvs->did[1] = 0x80000240; - gnvs->did[2] = 0x80000410; - gnvs->did[3] = 0x80000410; - gnvs->did[4] = 0x00000005; - -} - -unsigned long acpi_fill_madt(unsigned long current) -{ - /* Local APICs */ - current = acpi_create_madt_lapics(current); - - /* IOAPIC */ - current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, - 2, IO_APIC_ADDR, 0); - - /* INT_SRC_OVR */ - current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) - current, 0, 0, 2, 0); - current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) - current, 0, 9, 9, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_HIGH); - - return current; -} diff --git a/src/mainboard/intel/mohonpeak/board_info.txt b/src/mainboard/intel/mohonpeak/board_info.txt deleted file mode 100644 index f49af8aac5..0000000000 --- a/src/mainboard/intel/mohonpeak/board_info.txt +++ /dev/null @@ -1,4 +0,0 @@ -Category: eval -ROM protocol: SPI -Flashrom support: y -Release year: 2014 diff --git a/src/mainboard/intel/mohonpeak/cmos.layout b/src/mainboard/intel/mohonpeak/cmos.layout deleted file mode 100644 index 7c623c0085..0000000000 --- a/src/mainboard/intel/mohonpeak/cmos.layout +++ /dev/null @@ -1,104 +0,0 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2007-2008 coresystems GmbH -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; version 2 of the License. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## - -# ----------------------------------------------------------------- -entries - -# ----------------------------------------------------------------- -# Status Register A -# ----------------------------------------------------------------- -# Status Register B -# ----------------------------------------------------------------- -# Status Register C -#96 4 r 0 status_c_rsvd -#100 1 r 0 uf_flag -#101 1 r 0 af_flag -#102 1 r 0 pf_flag -#103 1 r 0 irqf_flag -# ----------------------------------------------------------------- -# Status Register D -#104 7 r 0 status_d_rsvd -#111 1 r 0 valid_cmos_ram -# ----------------------------------------------------------------- -# Diagnostic Status Register -#112 8 r 0 diag_rsvd1 - -# ----------------------------------------------------------------- -0 120 r 0 reserved_memory -#120 264 r 0 unused - -# ----------------------------------------------------------------- -# RTC_BOOT_BYTE (coreboot hardcoded) -384 1 e 4 boot_option -388 4 h 0 reboot_counter -#390 2 r 0 unused? - -# ----------------------------------------------------------------- -# coreboot config options: console -#392 3 r 0 unused -395 4 e 6 debug_level -#399 1 r 0 unused - -# coreboot config options: cpu -400 1 e 2 hyper_threading -#401 7 r 0 unused - -# coreboot config options: southbridge -408 1 e 1 nmi -409 2 e 7 power_on_after_fail -#411 5 r 0 unused - -# MRC Scrambler Seed values -896 32 r 0 mrc_scrambler_seed -928 32 r 0 mrc_scrambler_seed_s3 - -# coreboot config options: check sums -984 16 h 0 check_sum -#1000 24 r 0 amd_reserved - -#save timestamps in pre-ram boot areas -1720 64 h 0 timestamp_value1 -1784 64 h 0 timestamp_value2 -1848 64 h 0 timestamp_value3 -1912 64 h 0 timestamp_value4 -1976 64 h 0 timestamp_value5 - -# ----------------------------------------------------------------- - -enumerations - -#ID value text -1 0 Disable -1 1 Enable -2 0 Enable -2 1 Disable -4 0 Fallback -4 1 Normal -6 0 Emergency -6 1 Alert -6 2 Critical -6 3 Error -6 4 Warning -6 5 Notice -6 6 Info -6 7 Debug -6 8 Spew -7 0 Disable -7 1 Enable -7 2 Keep -# ----------------------------------------------------------------- -checksums - -checksum 392 415 984 diff --git a/src/mainboard/intel/mohonpeak/config_seabios b/src/mainboard/intel/mohonpeak/config_seabios deleted file mode 100644 index f688f2b530..0000000000 --- a/src/mainboard/intel/mohonpeak/config_seabios +++ /dev/null @@ -1,5 +0,0 @@ -# The Avoton/Rangeley chip does not allow devices to write into the 0xe000 -# segment. This means that USB/SATA devices will not work in SeaBIOS unless -# we put the SeaBIOS buffer area down in the 0x9000 segment. - -# CONFIG_MALLOC_UPPERMEMORY is not set diff --git a/src/mainboard/intel/mohonpeak/devicetree.cb b/src/mainboard/intel/mohonpeak/devicetree.cb deleted file mode 100644 index 0cb73f8a02..0000000000 --- a/src/mainboard/intel/mohonpeak/devicetree.cb +++ /dev/null @@ -1,62 +0,0 @@ -# -# This file is part of the coreboot project. -# -# Copyright (C) 2013 Sage Electronic Engineering, LLC. -# -# This program is free software; you can redistribute it and/or modify -# it under the terms of the GNU General Public License as published by -# the Free Software Foundation; version 2 of the License. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -chip northbridge/intel/fsp_rangeley - - device cpu_cluster 0 on - chip cpu/intel/fsp_model_406dx - device lapic 0 on end - # Magic APIC ID to locate this chip - device lapic 0xACAC off end - - register "c1_battery" = "3" # ACPI(C1) = MWAIT(C3) - register "c2_battery" = "4" # ACPI(C2) = MWAIT(C6) - register "c3_battery" = "5" # ACPI(C3) = MWAIT(C7) - - register "c1_acpower" = "3" # ACPI(C1) = MWAIT(C3) - register "c2_acpower" = "4" # ACPI(C2) = MWAIT(C6) - register "c3_acpower" = "5" # ACPI(C3) = MWAIT(C7) - end - end - - device domain 0 on - device pci 00.0 on end # host bridge - device pci 1.0 on end # PCIe Port #1 - device pci 2.0 on end # PCIe Port #2 - device pci 3.0 on end # PCIe Port #3 - device pci 4.0 on end # PCIe Port #4 - chip southbridge/intel/fsp_rangeley # Rangeley SB - - register "ide_legacy_combined" = "0x0" - register "sata_ahci" = "0x1" - register "sata_port_map" = "0x0f" - - register "fadt_pm_profile" = "PM_DESKTOP" - register "fadt_boot_arch" = "ACPI_FADT_LEGACY_FREE" - - device pci 0b.0 on end # IQIA - device pci 0e.0 on end # RAS - device pci 13.0 on end # SMBus 1 - device pci 14.0 on end # GbE 0 - device pci 14.1 on end # GbE 1 - device pci 14.2 on end # GbE 2 - device pci 14.3 on end # GbE 3 - device pci 16.0 on end # USB EHCI - device pci 17.0 on end # SATA 2.0 - device pci 18.0 on end # SATA 3.0 - device pci 1f.0 on end # LPC bridge - device pci 1f.3 on end # SMBus 0 - end - end -end diff --git a/src/mainboard/intel/mohonpeak/dsdt.asl b/src/mainboard/intel/mohonpeak/dsdt.asl deleted file mode 100644 index 4aad8a8b15..0000000000 --- a/src/mainboard/intel/mohonpeak/dsdt.asl +++ /dev/null @@ -1,54 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007-2009 coresystems GmbH - * Copyright (C) 2011 The ChromiumOS Authors. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -DefinitionBlock( - "dsdt.aml", - "DSDT", - 0x02, // DSDT revision: ACPI v2.0 and up - OEM_ID, - ACPI_TABLE_CREATOR, - 0x20110725 // OEM revision -) -{ - // Include mainboard configuration - #include - - // Include debug methods - #include - - // Some generic macros - #include - #include "acpi/platform.asl" - - // global NVS and variables - #include - - #include "acpi/thermal.asl" - - #include - - Scope (\_SB) { - Device (PCI0) - { - #include - #include - } - } - - /* Chipset specific sleep states */ - #include -} diff --git a/src/mainboard/intel/mohonpeak/fadt.c b/src/mainboard/intel/mohonpeak/fadt.c deleted file mode 100644 index 3d8db00f9f..0000000000 --- a/src/mainboard/intel/mohonpeak/fadt.c +++ /dev/null @@ -1,35 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2014 Sage Electronic Engineering, LLC. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include - -void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt) -{ - acpi_fill_in_fadt(fadt,facs,dsdt); - -#define PLATFORM_HAS_FADT_CUSTOMIZATIONS 0 - - - /* - * Platform specific customizations go here. - * Update the #define above if customizations are added. - */ - - -#if PLATFORM_HAS_FADT_CUSTOMIZATIONS - header->checksum = acpi_checksum((void *) fadt, sizeof(acpi_fadt_t)); -#endif -} diff --git a/src/mainboard/intel/mohonpeak/gpio.h b/src/mainboard/intel/mohonpeak/gpio.h deleted file mode 100644 index 29eb75e4b9..0000000000 --- a/src/mainboard/intel/mohonpeak/gpio.h +++ /dev/null @@ -1,174 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 The Chromium OS Authors. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef MOHONPEAK_GPIO_H -#define MOHONPEAK_GPIO_H - -#include - -/* Core GPIO */ -const struct soc_gpio soc_gpio_mode = { - .gpio15 = GPIO_MODE_GPIO, /* Board ID GPIO */ - .gpio17 = GPIO_MODE_GPIO, /* Board ID GPIO */ -}; - -const struct soc_gpio soc_gpio_direction = { - .gpio15 = GPIO_DIR_INPUT, /* Board ID GPIO */ - .gpio17 = GPIO_DIR_INPUT, /* Board ID GPIO */ -}; - -const struct soc_gpio soc_gpio_level = { -}; - -const struct soc_gpio soc_gpio_tpe = { -}; - -const struct soc_gpio soc_gpio_tne = { -}; - -const struct soc_gpio soc_gpio_ts = { -}; - -/* Keep the CFIO struct in register order, not gpio order. */ -const struct soc_cfio soc_cfio_core[] = { - { 0x8000, 0x0000, 0x0004, 0x040c }, /* CFIO gpios_28 */ - { 0x8000, 0x0000, 0x0002, 0x040c }, /* CFIO gpios_27 */ - { 0x8500, 0x0000, 0x0002, 0x040c }, /* CFIO gpios_26 */ - { 0x8480, 0x0000, 0x0002, 0x040c }, /* CFIO gpios_21 */ - { 0x8480, 0x0000, 0x0002, 0x040c }, /* CFIO gpios_22 */ - { 0x8480, 0x0000, 0x0002, 0x040c }, /* CFIO gpios_23 */ - { 0x8000, 0x0000, 0x0004, 0x040c }, /* CFIO gpios_25 */ - { 0x8480, 0x0000, 0x0002, 0x040c }, /* CFIO gpios_24 */ - { 0x80c028, 0x30003, 0x0004, 0x040c }, /* CFIO gpios_19 */ - { 0x80c028, 0x30003, 0x0004, 0x040c }, /* CFIO gpios_20 */ - { 0xc028, 0x30003, 0x0004, 0x040c }, /* CFIO gpios_18 */ - { 0x04a9, 0x30003, 0x0002, 0x040c }, /* CFIO gpios_17 */ - { 0x80c028, 0x30003, 0x0004, 0x040c }, /* CFIO gpios_7 */ - { 0xc028, 0x30003, 0x0004, 0x040c }, /* CFIO gpios_4 */ - { 0xc028, 0x30003, 0x0004, 0x040c }, /* CFIO gpios_5 */ - { 0xc528, 0x30003, 0x0002, 0x040c }, /* CFIO gpios_6 */ - { 0xc028, 0x30003, 0x0004, 0x040c }, /* CFIO gpios_1 */ - { 0xc028, 0x20002, 0x0004, 0x040c }, /* CFIO gpios_2 */ - { 0xc028, 0x20002, 0x0004, 0x040c }, /* CFIO gpios_3 */ - { 0xc528, 0x30003, 0x0002, 0x040c }, /* CFIO gpios_0 */ - { 0x0000, 0x0000, 0x0000, 0x0000 }, /* CFIO Reserved */ - { 0xc4a8, 0x30003, 0x0002, 0x040c }, /* CFIO gpios_10 */ - { 0xc4a8, 0x30003, 0x0002, 0x040c }, /* CFIO gpios_13 */ - { 0xc4a8, 0x30003, 0x0000, 0x040c }, /* CFIO gpios_14 */ - { 0xc4a8, 0x30003, 0x0002, 0x040c }, /* CFIO gpios_11 */ - { 0xc4a8, 0x30003, 0x0000, 0x040c }, /* CFIO gpios_8 */ - { 0xc4a8, 0x30003, 0x0002, 0x040c }, /* CFIO gpios_9 */ - { 0xc4a8, 0x30003, 0x0000, 0x040c }, /* CFIO gpios_12 */ - { 0xc4a8, 0x30003, 0x0002, 0x040c }, /* CFIO gpios_29 */ - { 0xc4a8, 0x30003, 0x0002, 0x040c }, /* CFIO gpios_30 */ - { 0x04a9, 0x30003, 0x0002, 0x040c }, /* CFIO gpios_15 */ - { 0xc028, 0x30003, 0x0004, 0x040c }, /* CFIO gpios_16 */ -}; - -/* SUS GPIO */ -const struct soc_gpio soc_gpio_sus_mode = { - .gpio2 = GPIO_MODE_GPIO, -}; - -const struct soc_gpio soc_gpio_sus_direction = { - .gpio2 = GPIO_DIR_INPUT, -}; - -const struct soc_gpio soc_gpio_sus_level = { -}; - -const struct soc_gpio soc_gpio_sus_tpe = { -}; - -const struct soc_gpio soc_gpio_sus_tne = { -}; - -const struct soc_gpio soc_gpio_sus_ts = { -}; - -const struct soc_gpio soc_gpio_sus_we = { -}; - - -/* Keep the CFIO struct in register order, not gpio order. */ -const struct soc_cfio soc_cfio_sus[] = { - { 0xc028, 0x30003, 0x0004, 0x040c }, /* CFIO SUS gpios_21 */ - { 0xc028, 0x30003, 0x0004, 0x040c }, /* CFIO SUS gpios_20 */ - { 0xc028, 0x30003, 0x0004, 0x040c }, /* CFIO SUS gpios_19 */ - { 0xc028, 0x30003, 0x0004, 0x040c }, /* CFIO SUS gpios_22 */ - { 0xc4a8, 0x30003, 0x0002, 0x040c }, /* CFIO SUS gpios_17 */ - { 0xc4a8, 0x30003, 0x0002, 0x040c }, /* CFIO SUS gpios_18 */ - { 0x0000, 0x0000, 0x0000, 0x0000 }, /* CFIO Reserved */ - { 0x0000, 0x0000, 0x0000, 0x0000 }, /* CFIO Reserved */ - { 0x0000, 0x0000, 0x0000, 0x0000 }, /* CFIO Reserved */ - { 0xc4a8, 0x30003, 0x0002, 0x040c }, /* CFIO SUS gpios_14 */ - { 0xc028, 0x30003, 0x0004, 0x040c }, /* CFIO SUS gpios_13 */ - { 0xc028, 0x30003, 0x0004, 0x040c }, /* CFIO SUS gpios_15 */ - { 0xc028, 0x30003, 0x0004, 0x040c }, /* CFIO SUS gpios_16 */ - { 0xc4a8, 0x30003, 0x0002, 0x040c }, /* CFIO SUS gpios_25 */ - { 0xc4a8, 0x30003, 0x0002, 0x040c }, /* CFIO SUS gpios_24 */ - { 0xc4a8, 0x30003, 0x0002, 0x040c }, /* CFIO SUS gpios_26 */ - { 0xc4a8, 0x30003, 0x0002, 0x040c }, /* CFIO SUS gpios_27 */ - { 0xc4a8, 0x30003, 0x0002, 0x040c }, /* CFIO SUS gpios_23 */ - { 0xc4a8, 0x30003, 0x0003, 0x040c }, /* CFIO SUS gpios_2 */ - { 0xc4a8, 0x30003, 0x0003, 0x040c }, /* CFIO SUS gpios_1 */ - { 0x8050, 0x0000, 0x0004, 0x040c }, /* CFIO SUS gpios_7 */ - { 0x0000, 0x0000, 0x0000, 0x0000 }, /* CFIO Reserved */ - { 0x0000, 0x0000, 0x0000, 0x0000 }, /* CFIO Reserved */ - { 0xc028, 0x30003, 0x0004, 0x040c }, /* CFIO SUS gpios_3 */ - { 0xc4a8, 0x30003, 0x0003, 0x040c }, /* CFIO SUS gpios_0 */ - { 0x0000, 0x0000, 0x0000, 0x0000 }, /* CFIO Reserved */ - { 0x0000, 0x0000, 0x0000, 0x0000 }, /* CFIO Reserved */ - { 0x8000, 0x0000, 0x0004, 0x040c }, /* CFIO SUS gpios_12 */ - { 0x8050, 0x0000, 0x0004, 0x040c }, /* CFIO SUS gpios_6 */ - { 0xc028, 0x30003, 0x0004, 0x040c }, /* CFIO SUS gpios_10 */ - { 0xc4a8, 0x30003, 0x0002, 0x040c }, /* CFIO SUS gpios_9 */ - { 0xc4a8, 0x30003, 0x0002, 0x040c }, /* CFIO SUS gpios_8 */ - { 0x0000, 0x0000, 0x0000, 0x0000 }, /* CFIO Reserved */ - { 0x0000, 0x0000, 0x0000, 0x0000 }, /* CFIO Reserved */ - { 0x8050, 0x0000, 0x0004, 0x040c }, /* CFIO SUS gpios_4 */ - { 0xc4a8, 0x30003, 0x0002, 0x040c }, /* CFIO SUS gpios_11 */ - { 0x0000, 0x0000, 0x0000, 0x0000 }, /* CFIO Reserved */ - { 0x0000, 0x0000, 0x0000, 0x0000 }, /* CFIO Reserved */ - { 0x0000, 0x0000, 0x0000, 0x0000 }, /* CFIO Reserved */ - { 0x0000, 0x0000, 0x0000, 0x0000 }, /* CFIO Reserved */ - { 0xc028, 0x30003, 0x0004, 0x040c }, /* CFIO SUS gpios_5 */ -}; - -const struct soc_gpio_map gpio_map = { - .core = { - .mode = &soc_gpio_mode, - .direction = &soc_gpio_direction, - .level = &soc_gpio_level, - .tpe = &soc_gpio_tpe, - .tne = &soc_gpio_tne, - .ts = &soc_gpio_ts, - .cfio_init = &soc_cfio_core[0], - .cfio_entrynum = sizeof(soc_cfio_core) / sizeof(struct soc_cfio), - }, - .sus = { - .mode = &soc_gpio_sus_mode, - .direction = &soc_gpio_sus_direction, - .level = &soc_gpio_sus_level, - .tpe = &soc_gpio_sus_tpe, - .tne = &soc_gpio_sus_tne, - .ts = &soc_gpio_sus_ts, - .we = &soc_gpio_sus_we, - .cfio_init = &soc_cfio_sus[0], - .cfio_entrynum = sizeof(soc_cfio_sus) / sizeof(struct soc_cfio), - }, -}; - -#endif /* MOHONPEAK_GPIO_H */ diff --git a/src/mainboard/intel/mohonpeak/irq_tables.c b/src/mainboard/intel/mohonpeak/irq_tables.c deleted file mode 100644 index bca68ea548..0000000000 --- a/src/mainboard/intel/mohonpeak/irq_tables.c +++ /dev/null @@ -1,63 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007-2009 coresystems GmbH - * Copyright (C) 2011 The ChromiumOS Authors. All rights reserved. - * Copyright (C) 2013, Intel Corporation. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include - -#define PIRQA 0x08 -#define PIRQB 0x09 -#define PIRQC 0x0a -#define PIRQD 0x0b -#define PIRQE 0x0c -#define PIRQF 0x0d -#define PIRQG 0x0e -#define PIRQH 0x0f - -#define PCI_IRQS 0xDCF0 - -const struct irq_routing_table intel_irq_routing_table = { - PIRQ_SIGNATURE, /* u32 signature */ - PIRQ_VERSION, /* u16 version */ - 32+16*CONFIG_IRQ_SLOT_COUNT, /* There can be total 18 devices on the bus */ - 0x00, /* Where the interrupt router lies (bus) */ - (0x1f << 3)|0x0, /* Where the interrupt router lies (dev) */ - 0, /* IRQs devoted exclusively to PCI usage */ - 0x8086, /* Vendor */ - 0x0F1C, /* Device */ - 0, /* miniport */ - { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */ - 0x86, /* u8 checksum. */ - { - /* bus, dev|fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */ - {0x00,(0x01 << 3)|0x0, {{PIRQA, PCI_IRQS}, {PIRQB, PCI_IRQS}, {PIRQC, PCI_IRQS}, {PIRQD, PCI_IRQS}}, 0x0, 0x0}, // PCIE Port 1: INTA-PIRQA, INTB-PIRQB, INTC-PIRQC, INTD-PIRQD - {0x00,(0x02 << 3)|0x0, {{PIRQA, PCI_IRQS}, {PIRQB, PCI_IRQS}, {PIRQC, PCI_IRQS}, {PIRQD, PCI_IRQS}}, 0x0, 0x0}, // PCIE Port 2: INTA-PIRQA, INTB-PIRQB, INTC-PIRQC, INTD-PIRQD - {0x00,(0x03 << 3)|0x0, {{PIRQE, PCI_IRQS}, {PIRQF, PCI_IRQS}, {PIRQG, PCI_IRQS}, {PIRQH, PCI_IRQS}}, 0x0, 0x0}, // PCIE Port 3: INTA-PIRQE, INTB-PIRQF, INTC-PIRQG, INTD-PIRQH - {0x00,(0x04 << 3)|0x0, {{PIRQE, PCI_IRQS}, {PIRQF, PCI_IRQS}, {PIRQG, PCI_IRQS}, {PIRQH, PCI_IRQS}}, 0x0, 0x0}, // PCIE Port 4: INTA-PIRQE, INTB-PIRQF, INTC-PIRQG, INTD-PIRQH - {0x00,(0x0b << 3)|0x0, {{PIRQA, PCI_IRQS}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, // IQAT INTA-PIRQA - {0x00,(0x0f << 3)|0x0, {{PIRQA, PCI_IRQS}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, // RCEC INTA-PIRQA - {0x00,(0x13 << 3)|0x0, {{PIRQA, PCI_IRQS}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, // SMBUS #1 INTA-PIRQA - {0x00,(0x14 << 3)|0x0, {{PIRQE, PCI_IRQS}, {PIRQF, PCI_IRQS}, {PIRQG, PCI_IRQS}, {PIRQH, PCI_IRQS}}, 0x0, 0x0}, // GbE, INTA-PIRQE, INTB-PIRQF, INTC-PIRQG, INTD-PIRQH - {0x00,(0x16 << 3)|0x0, {{PIRQH, PCI_IRQS}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, // EHCI INTA-PIRQH - {0x00,(0x17 << 3)|0x0, {{PIRQD, PCI_IRQS}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, // SATA2 INTA-PIRQD - {0x00,(0x18 << 3)|0x0, {{PIRQD, PCI_IRQS}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, // SATA3 INTA-PIRQD - {0x00,(0x1f << 3)|0x0, {{0x00, 0x0000}, {PIRQC, PCI_IRQS}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, // LPC/SMBUS #0 INTB - PIRQC - } -}; - -unsigned long write_pirq_routing_table(unsigned long addr) -{ - return copy_pirq_routing_table(addr, &intel_irq_routing_table); -} diff --git a/src/mainboard/intel/mohonpeak/irqroute.c b/src/mainboard/intel/mohonpeak/irqroute.c deleted file mode 100644 index 2bf03cef68..0000000000 --- a/src/mainboard/intel/mohonpeak/irqroute.c +++ /dev/null @@ -1,19 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2013 Google Inc. - * Copyright (C) 2014 Sage Electronics Engineering, LLC. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include "irqroute.h" - -DEFINE_IRQ_ROUTES; diff --git a/src/mainboard/intel/mohonpeak/irqroute.h b/src/mainboard/intel/mohonpeak/irqroute.h deleted file mode 100644 index 43a69d9620..0000000000 --- a/src/mainboard/intel/mohonpeak/irqroute.h +++ /dev/null @@ -1,71 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2013 Google Inc. - * Copyright (C) 2014 Sage Electronics Engineering, LLC. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef IRQROUTE_H -#define IRQROUTE_H - -#include -#include - -/* - * IR01h PCIe INT(ABCD) - PIRQ ABCD - * IR02h PCIe INT(ABCD) - PIRQ ABCD - * IR03h PCIe INT(ABCD) - PIRQ ABCD - * IR04h PCIe INT(ABCD) - PIRQ ABCD - * IR0Bh IQIA INT(ABCD) - PIRQ EFGH - * IR0Eh RAS INT(A) - PIRQ A - * IR13h SMBUS1 INT(A) - PIRQ B - * IR15h GBE INT(A) - PIRQ CDEF - * IR1Dh EHCI INT(A) - PIRQ G - * IR13h SATA2.0 INT(A) - PIRQ H - * IR13h SATA3.0 INT(A) - PIRQ A - * IR1Fh LPC INT(ABCD) - PIRQ HGBC - */ - - /* Devices set as A, A, A, A evaluate as 0, and don't get set */ -#define PCI_DEV_PIRQ_ROUTES \ - PCI_DEV_PIRQ_ROUTE(PCIE_PORT1_DEV, A, B, C, D), \ - PCI_DEV_PIRQ_ROUTE(PCIE_PORT2_DEV, D, C, B, A), \ - PCI_DEV_PIRQ_ROUTE(PCIE_PORT3_DEV, E, F, G, H), \ - PCI_DEV_PIRQ_ROUTE(PCIE_PORT4_DEV, H, G, F, E), \ - PCI_DEV_PIRQ_ROUTE(IQAT_DEV, E, F, G, H), \ - PCI_DEV_PIRQ_ROUTE(HOST_BRIDGE_DEV, H, A, A, A), \ - PCI_DEV_PIRQ_ROUTE(RCEC_DEV, A, A, A, B), \ - PCI_DEV_PIRQ_ROUTE(SMBUS1_DEV, B, A, A, A), \ - PCI_DEV_PIRQ_ROUTE(GBE_DEV, C, D, E, F), \ - PCI_DEV_PIRQ_ROUTE(USB2_DEV, G, A, A, A), \ - PCI_DEV_PIRQ_ROUTE(SATA2_DEV, H, A, A, A), \ - PCI_DEV_PIRQ_ROUTE(SATA3_DEV, A, A, A, B), \ - PCI_DEV_PIRQ_ROUTE(PCU_DEV, H, G, B, C) - -/* - * Route each PIRQ[A-H] to a PIC IRQ[0-15] - * Reserved: 0, 1, 2, 8, 13 - * PS2 keyboard: 12 - * ACPI/SCI: 9 - * Floppy: 6 - */ -#define PIRQ_PIC_ROUTES \ - PIRQ_PIC(A, 10), \ - PIRQ_PIC(B, 11), \ - PIRQ_PIC(C, 10), \ - PIRQ_PIC(D, 11), \ - PIRQ_PIC(E, 14), \ - PIRQ_PIC(F, 15), \ - PIRQ_PIC(G, 14), \ - PIRQ_PIC(H, 15) - -#endif /* IRQROUTE_H */ diff --git a/src/mainboard/intel/mohonpeak/romstage.c b/src/mainboard/intel/mohonpeak/romstage.c deleted file mode 100644 index 08dd02de2e..0000000000 --- a/src/mainboard/intel/mohonpeak/romstage.c +++ /dev/null @@ -1,81 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007-2010 coresystems GmbH - * Copyright (C) 2011 The ChromiumOS Authors. All rights reserved. - * Copyright (C) 2013-2014 Sage Electronic Engineering, LLC. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include "gpio.h" - -static void interrupt_routing_config(void) -{ - u8 *ilb_base = (u8 *)(pci_read_config32(SOC_LPC_DEV, IBASE) & ~0xf); - - /* - * Initialize Interrupt Routings for each device in ilb_base_address. - * IR01 map to PCIe device 0x01 ... IR31 to device 0x1F. - * PIRQ_A maps to IRQ 16 ... PIRQ_H maps tp IRQ 23. - * This should match devicetree and the ACPI IRQ routing/ - */ - write32(ilb_base + ILB_ACTL, 0x0000); /* ACTL bit 2:0 SCIS IRQ9 */ - write16(ilb_base + ILB_IR01, 0x3210); /* IR01h IR(ABCD) - PIRQ(ABCD) */ - write16(ilb_base + ILB_IR02, 0x3210); /* IR02h IR(ABCD) - PIRQ(ABCD) */ - write16(ilb_base + ILB_IR03, 0x7654); /* IR03h IR(ABCD) - PIRQ(EFGH) */ - write16(ilb_base + ILB_IR04, 0x7654); /* IR04h IR(ABCD) - PIRQ(EFGH) */ - write16(ilb_base + ILB_IR20, 0x7654); /* IR14h IR(ABCD) - PIRQ(EFGH) */ - write16(ilb_base + ILB_IR22, 0x0007); /* IR16h IR(A) - PIRQ(H) */ - write16(ilb_base + ILB_IR23, 0x0003); /* IR17h IR(A) - PIRQ(D) */ - write16(ilb_base + ILB_IR24, 0x0003); /* IR18h IR(A) - PIRQ(D) */ - write16(ilb_base + ILB_IR31, 0x0020); /* IR1Fh IR(B) - PIRQ(C) */ -} - -/** - * /brief mainboard call for setup that needs to be done before fsp init - * - */ -void early_mainboard_romstage_entry(void) -{ - setup_soc_gpios(&gpio_map); -} - -/** - * /brief mainboard call for setup that needs to be done after fsp init - * - */ -void late_mainboard_romstage_entry(void) -{ - interrupt_routing_config(); -} - -/** - * Get function disables - most of these will be done automatically - * @param mask pointer to the function-disable bitfield - */ -void get_func_disables(uint32_t *mask) -{ - -} - -void romstage_fsp_rt_buffer_callback(FSP_INIT_RT_BUFFER *FspRtBuffer) -{ - /* No overrides needed */ - return; -} diff --git a/src/mainboard/intel/mohonpeak/thermal.h b/src/mainboard/intel/mohonpeak/thermal.h deleted file mode 100644 index cc95fdb0c6..0000000000 --- a/src/mainboard/intel/mohonpeak/thermal.h +++ /dev/null @@ -1,29 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 The Chromium OS Authors. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef MOHONPEAK_THERMAL_H -#define MOHONPEAK_THERMAL_H - - -/* Temperature which OS will shutdown at */ -#define CRITICAL_TEMPERATURE 100 - -/* Temperature which OS will throttle CPU */ -#define PASSIVE_TEMPERATURE 90 - -/* Tj_max value for calculating PECI CPU temperature */ -#define MAX_TEMPERATURE 100 - -#endif From c2c634a089fa990418c363e2ff2e5ff70bdd3580 Mon Sep 17 00:00:00 2001 From: Arthur Heymans Date: Tue, 19 Nov 2019 18:37:28 +0100 Subject: [PATCH 0305/1242] nb/sb/cpu: Drop Intel Rangeley support MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Relocatable ramstage, postcar stage and C_ENVIRONMENT_BOOTBLOCK are now mandatory features, which this platform lacks. Change-Id: I41589118579988617677cf48af5401bc35b23e05 Signed-off-by: Arthur Heymans Reviewed-on: https://review.coreboot.org/c/coreboot/+/36980 Tested-by: build bot (Jenkins) Reviewed-by: HAOUAS Elyes Reviewed-by: Kyösti Mälkki Reviewed-by: Angel Pons Reviewed-by: David Hendricks --- src/cpu/intel/Makefile.inc | 1 - src/cpu/intel/fsp_model_406dx/Kconfig | 63 -- src/cpu/intel/fsp_model_406dx/Makefile.inc | 27 - src/cpu/intel/fsp_model_406dx/acpi.c | 321 -------- src/cpu/intel/fsp_model_406dx/bootblock.c | 89 --- src/cpu/intel/fsp_model_406dx/chip.h | 30 - src/cpu/intel/fsp_model_406dx/model_406dx.h | 87 --- .../intel/fsp_model_406dx/model_406dx_init.c | 169 ----- src/include/device/pci_ids.h | 2 - src/northbridge/intel/fsp_rangeley/Kconfig | 88 --- .../intel/fsp_rangeley/Makefile.inc | 34 - src/northbridge/intel/fsp_rangeley/acpi.c | 71 -- .../intel/fsp_rangeley/acpi/hostbridge.asl | 131 ---- .../intel/fsp_rangeley/acpi/rangeley.asl | 36 - src/northbridge/intel/fsp_rangeley/chip.h | 69 -- .../intel/fsp_rangeley/fsp/Kconfig | 45 -- .../intel/fsp_rangeley/fsp/Makefile.inc | 17 - .../intel/fsp_rangeley/fsp/chipset_fsp_util.c | 160 ---- .../intel/fsp_rangeley/fsp/chipset_fsp_util.h | 48 -- src/northbridge/intel/fsp_rangeley/memmap.c | 42 -- .../intel/fsp_rangeley/northbridge.c | 251 ------ .../intel/fsp_rangeley/northbridge.h | 69 -- .../intel/fsp_rangeley/port_access.c | 65 -- src/southbridge/intel/common/watchdog.c | 9 +- src/southbridge/intel/fsp_rangeley/Kconfig | 60 -- .../intel/fsp_rangeley/Makefile.inc | 33 - src/southbridge/intel/fsp_rangeley/acpi.c | 195 ----- .../intel/fsp_rangeley/acpi/globalnvs.asl | 181 ----- .../intel/fsp_rangeley/acpi/irq_helper.h | 57 -- .../intel/fsp_rangeley/acpi/irqlinks.asl | 487 ------------ .../intel/fsp_rangeley/acpi/irqroute.asl | 39 - .../intel/fsp_rangeley/acpi/lpc.asl | 226 ------ .../intel/fsp_rangeley/acpi/pcie.asl | 165 ---- .../intel/fsp_rangeley/acpi/pcie_port.asl | 25 - .../intel/fsp_rangeley/acpi/sata.asl | 77 -- .../intel/fsp_rangeley/acpi/soc.asl | 272 ------- .../intel/fsp_rangeley/acpi/usb.asl | 48 -- src/southbridge/intel/fsp_rangeley/chip.h | 84 --- .../intel/fsp_rangeley/early_init.c | 76 -- .../intel/fsp_rangeley/early_smbus.c | 57 -- .../intel/fsp_rangeley/early_usb.c | 41 - src/southbridge/intel/fsp_rangeley/gpio.c | 105 --- src/southbridge/intel/fsp_rangeley/gpio.h | 124 --- src/southbridge/intel/fsp_rangeley/irq.h | 162 ---- src/southbridge/intel/fsp_rangeley/lpc.c | 461 ------------ src/southbridge/intel/fsp_rangeley/nvs.h | 151 ---- src/southbridge/intel/fsp_rangeley/pci_devs.h | 135 ---- src/southbridge/intel/fsp_rangeley/romstage.c | 137 ---- src/southbridge/intel/fsp_rangeley/romstage.h | 28 - src/southbridge/intel/fsp_rangeley/sata.c | 122 --- src/southbridge/intel/fsp_rangeley/smbus.c | 81 -- src/southbridge/intel/fsp_rangeley/soc.c | 96 --- src/southbridge/intel/fsp_rangeley/soc.h | 401 ---------- src/southbridge/intel/fsp_rangeley/spi.c | 712 ------------------ src/vendorcode/intel/Kconfig | 1 - .../intel/fsp1_0/rangeley/include/fspapi.h | 67 -- .../fsp1_0/rangeley/include/fspbootmode.h | 54 -- .../intel/fsp1_0/rangeley/include/fspffs.h | 507 ------------- .../intel/fsp1_0/rangeley/include/fspfv.h | 249 ------ .../intel/fsp1_0/rangeley/include/fspguid.h | 69 -- .../intel/fsp1_0/rangeley/include/fsphob.h | 544 ------------- .../fsp1_0/rangeley/include/fspinfoheader.h | 62 -- .../fsp1_0/rangeley/include/fspplatform.h | 114 --- .../fsp1_0/rangeley/include/fspsupport.h | 95 --- .../intel/fsp1_0/rangeley/include/fsptypes.h | 183 ----- .../intel/fsp1_0/rangeley/include/fspvpd.h | 89 --- .../intel/fsp1_0/rangeley/srx/fsp_support.c | 288 ------- .../intel/fsp1_0/rangeley/srx/fsphob.c | 198 ----- 68 files changed, 2 insertions(+), 9280 deletions(-) delete mode 100644 src/cpu/intel/fsp_model_406dx/Kconfig delete mode 100644 src/cpu/intel/fsp_model_406dx/Makefile.inc delete mode 100644 src/cpu/intel/fsp_model_406dx/acpi.c delete mode 100644 src/cpu/intel/fsp_model_406dx/bootblock.c delete mode 100644 src/cpu/intel/fsp_model_406dx/chip.h delete mode 100644 src/cpu/intel/fsp_model_406dx/model_406dx.h delete mode 100644 src/cpu/intel/fsp_model_406dx/model_406dx_init.c delete mode 100644 src/northbridge/intel/fsp_rangeley/Kconfig delete mode 100644 src/northbridge/intel/fsp_rangeley/Makefile.inc delete mode 100644 src/northbridge/intel/fsp_rangeley/acpi.c delete mode 100644 src/northbridge/intel/fsp_rangeley/acpi/hostbridge.asl delete mode 100644 src/northbridge/intel/fsp_rangeley/acpi/rangeley.asl delete mode 100644 src/northbridge/intel/fsp_rangeley/chip.h delete mode 100644 src/northbridge/intel/fsp_rangeley/fsp/Kconfig delete mode 100644 src/northbridge/intel/fsp_rangeley/fsp/Makefile.inc delete mode 100644 src/northbridge/intel/fsp_rangeley/fsp/chipset_fsp_util.c delete mode 100644 src/northbridge/intel/fsp_rangeley/fsp/chipset_fsp_util.h delete mode 100644 src/northbridge/intel/fsp_rangeley/memmap.c delete mode 100644 src/northbridge/intel/fsp_rangeley/northbridge.c delete mode 100644 src/northbridge/intel/fsp_rangeley/northbridge.h delete mode 100644 src/northbridge/intel/fsp_rangeley/port_access.c delete mode 100644 src/southbridge/intel/fsp_rangeley/Kconfig delete mode 100644 src/southbridge/intel/fsp_rangeley/Makefile.inc delete mode 100644 src/southbridge/intel/fsp_rangeley/acpi.c delete mode 100644 src/southbridge/intel/fsp_rangeley/acpi/globalnvs.asl delete mode 100644 src/southbridge/intel/fsp_rangeley/acpi/irq_helper.h delete mode 100644 src/southbridge/intel/fsp_rangeley/acpi/irqlinks.asl delete mode 100644 src/southbridge/intel/fsp_rangeley/acpi/irqroute.asl delete mode 100644 src/southbridge/intel/fsp_rangeley/acpi/lpc.asl delete mode 100644 src/southbridge/intel/fsp_rangeley/acpi/pcie.asl delete mode 100644 src/southbridge/intel/fsp_rangeley/acpi/pcie_port.asl delete mode 100644 src/southbridge/intel/fsp_rangeley/acpi/sata.asl delete mode 100644 src/southbridge/intel/fsp_rangeley/acpi/soc.asl delete mode 100644 src/southbridge/intel/fsp_rangeley/acpi/usb.asl delete mode 100644 src/southbridge/intel/fsp_rangeley/chip.h delete mode 100644 src/southbridge/intel/fsp_rangeley/early_init.c delete mode 100644 src/southbridge/intel/fsp_rangeley/early_smbus.c delete mode 100644 src/southbridge/intel/fsp_rangeley/early_usb.c delete mode 100644 src/southbridge/intel/fsp_rangeley/gpio.c delete mode 100644 src/southbridge/intel/fsp_rangeley/gpio.h delete mode 100644 src/southbridge/intel/fsp_rangeley/irq.h delete mode 100644 src/southbridge/intel/fsp_rangeley/lpc.c delete mode 100644 src/southbridge/intel/fsp_rangeley/nvs.h delete mode 100644 src/southbridge/intel/fsp_rangeley/pci_devs.h delete mode 100644 src/southbridge/intel/fsp_rangeley/romstage.c delete mode 100644 src/southbridge/intel/fsp_rangeley/romstage.h delete mode 100644 src/southbridge/intel/fsp_rangeley/sata.c delete mode 100644 src/southbridge/intel/fsp_rangeley/smbus.c delete mode 100644 src/southbridge/intel/fsp_rangeley/soc.c delete mode 100644 src/southbridge/intel/fsp_rangeley/soc.h delete mode 100644 src/southbridge/intel/fsp_rangeley/spi.c delete mode 100644 src/vendorcode/intel/fsp1_0/rangeley/include/fspapi.h delete mode 100644 src/vendorcode/intel/fsp1_0/rangeley/include/fspbootmode.h delete mode 100644 src/vendorcode/intel/fsp1_0/rangeley/include/fspffs.h delete mode 100644 src/vendorcode/intel/fsp1_0/rangeley/include/fspfv.h delete mode 100644 src/vendorcode/intel/fsp1_0/rangeley/include/fspguid.h delete mode 100644 src/vendorcode/intel/fsp1_0/rangeley/include/fsphob.h delete mode 100644 src/vendorcode/intel/fsp1_0/rangeley/include/fspinfoheader.h delete mode 100644 src/vendorcode/intel/fsp1_0/rangeley/include/fspplatform.h delete mode 100644 src/vendorcode/intel/fsp1_0/rangeley/include/fspsupport.h delete mode 100644 src/vendorcode/intel/fsp1_0/rangeley/include/fsptypes.h delete mode 100644 src/vendorcode/intel/fsp1_0/rangeley/include/fspvpd.h delete mode 100644 src/vendorcode/intel/fsp1_0/rangeley/srx/fsp_support.c delete mode 100644 src/vendorcode/intel/fsp1_0/rangeley/srx/fsphob.c diff --git a/src/cpu/intel/Makefile.inc b/src/cpu/intel/Makefile.inc index 484e241312..904b61bba0 100644 --- a/src/cpu/intel/Makefile.inc +++ b/src/cpu/intel/Makefile.inc @@ -13,7 +13,6 @@ subdirs-$(CONFIG_CPU_INTEL_SOCKET_MPGA604) += socket_mPGA604 subdirs-$(CONFIG_NORTHBRIDGE_INTEL_NEHALEM) += model_2065x subdirs-$(CONFIG_NORTHBRIDGE_INTEL_SANDYBRIDGE) += model_206ax subdirs-$(CONFIG_NORTHBRIDGE_INTEL_HASWELL) += haswell -subdirs-$(CONFIG_NORTHBRIDGE_INTEL_FSP_RANGELEY) += fsp_model_406dx subdirs-$(CONFIG_CPU_INTEL_SLOT_1) += slot_1 subdirs-$(CONFIG_CPU_INTEL_SOCKET_LGA775) += socket_LGA775 diff --git a/src/cpu/intel/fsp_model_406dx/Kconfig b/src/cpu/intel/fsp_model_406dx/Kconfig deleted file mode 100644 index 3e71469947..0000000000 --- a/src/cpu/intel/fsp_model_406dx/Kconfig +++ /dev/null @@ -1,63 +0,0 @@ -## -## This file is part of the coreboot project. -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; version 2 of the License. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## - -config CPU_INTEL_FSP_MODEL_406DX - bool - -if CPU_INTEL_FSP_MODEL_406DX - -config CPU_SPECIFIC_OPTIONS - def_bool y - select PLATFORM_USES_FSP1_0 - select ARCH_BOOTBLOCK_X86_32 - select ARCH_VERSTAGE_X86_32 - select ARCH_ROMSTAGE_X86_32 - select ARCH_RAMSTAGE_X86_32 - select SMP - select MMX - select SSE2 - select UDELAY_TSC - select SUPPORT_CPU_UCODE_IN_CBFS - select MICROCODE_BLOB_NOT_IN_BLOB_REPO - select PARALLEL_CPU_INIT - select TSC_SYNC_MFENCE - select TSC_MONOTONIC_TIMER - select CPU_INTEL_COMMON - select CPU_INTEL_COMMON_TIMEBASE - select NO_SMM - - # Microcode header files are delivered in FSP package - select USES_MICROCODE_HEADER_FILES if HAVE_FSP_BIN - -choice - prompt "Rangeley CPU Stepping" - default FSP_MODEL_406DX_B0 - -config FSP_MODEL_406DX_A1 - bool "A1" - -config FSP_MODEL_406DX_B0 - bool "B0" - -endchoice - -config BOOTBLOCK_CPU_INIT - string - default "cpu/intel/fsp_model_406dx/bootblock.c" - -#set up microcode for rangeley POSTGOLD4 release -config CPU_MICROCODE_HEADER_FILES - string - default "../intel/cpu/rangeley/microcode/microcode-m01406d000e.h ../intel/cpu/rangeley/microcode/microcode-m01406d8128.h" - -endif #CPU_INTEL_FSP_MODEL_406DX diff --git a/src/cpu/intel/fsp_model_406dx/Makefile.inc b/src/cpu/intel/fsp_model_406dx/Makefile.inc deleted file mode 100644 index a3ebe3da06..0000000000 --- a/src/cpu/intel/fsp_model_406dx/Makefile.inc +++ /dev/null @@ -1,27 +0,0 @@ -# -# This file is part of the coreboot project. -# -# This program is free software; you can redistribute it and/or modify -# it under the terms of the GNU General Public License as published by -# the Free Software Foundation; version 2 of the License. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# - -ramstage-y += model_406dx_init.c -subdirs-y += ../../x86/name - -subdirs-y += ../../x86/tsc -subdirs-y += ../../x86/mtrr -subdirs-y += ../../x86/lapic -subdirs-y += ../../x86/cache -subdirs-y += ../../x86/smm -subdirs-y += ../microcode -subdirs-y += ../turbo - -ramstage-y += acpi.c - -CPPFLAGS_romstage += -I$(src)/cpu/intel/fsp_model_406dx diff --git a/src/cpu/intel/fsp_model_406dx/acpi.c b/src/cpu/intel/fsp_model_406dx/acpi.c deleted file mode 100644 index 078905deac..0000000000 --- a/src/cpu/intel/fsp_model_406dx/acpi.c +++ /dev/null @@ -1,321 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include "model_406dx.h" -#include "chip.h" - -static int get_cores_per_package(void) -{ - struct cpuinfo_x86 c; - struct cpuid_result result; - int cores = 1; - - get_fms(&c, cpuid_eax(1)); - if (c.x86 != 6) - return 1; - - result = cpuid_ext(0xb, 1); - cores = result.ebx & 0xff; - - return cores; -} - -static void generate_C_state_entries(void) -{ - struct cpu_info *info; - struct cpu_driver *cpu; - struct device *lapic; - struct cpu_intel_model_406dx_config *conf = NULL; - - /* Find the SpeedStep CPU in the device tree using magic APIC ID */ - lapic = dev_find_lapic(SPEEDSTEP_APIC_MAGIC); - if (!lapic) - return; - conf = lapic->chip_info; - if (!conf) - return; - - /* Find CPU map of supported C-states */ - info = cpu_info(); - if (!info) - return; - cpu = find_cpu_driver(info->cpu); - if (!cpu || !cpu->cstates) - return; - - acpigen_emit_byte(0x14); /* MethodOp */ - acpigen_write_len_f(); /* PkgLength */ - acpigen_emit_namestring("_CST"); - acpigen_emit_byte(0x00); /* No Arguments */ - - /* If running on AC power */ - acpigen_emit_byte(0xa0); /* IfOp */ - acpigen_write_len_f(); /* PkgLength */ - acpigen_emit_namestring("PWRS"); - acpigen_emit_byte(0xa4); /* ReturnOp */ - acpigen_pop_len(); - - /* Else on battery power */ - acpigen_emit_byte(0xa4); /* ReturnOp */ - acpigen_pop_len(); -} - -static acpi_tstate_t tss_table_fine[] = { - { 100, 1000, 0, 0x00, 0 }, - { 94, 940, 0, 0x1f, 0 }, - { 88, 880, 0, 0x1e, 0 }, - { 82, 820, 0, 0x1d, 0 }, - { 75, 760, 0, 0x1c, 0 }, - { 69, 700, 0, 0x1b, 0 }, - { 63, 640, 0, 0x1a, 0 }, - { 57, 580, 0, 0x19, 0 }, - { 50, 520, 0, 0x18, 0 }, - { 44, 460, 0, 0x17, 0 }, - { 38, 400, 0, 0x16, 0 }, - { 32, 340, 0, 0x15, 0 }, - { 25, 280, 0, 0x14, 0 }, - { 19, 220, 0, 0x13, 0 }, - { 13, 160, 0, 0x12, 0 }, -}; - -static acpi_tstate_t tss_table_coarse[] = { - { 100, 1000, 0, 0x00, 0 }, - { 88, 875, 0, 0x1f, 0 }, - { 75, 750, 0, 0x1e, 0 }, - { 63, 625, 0, 0x1d, 0 }, - { 50, 500, 0, 0x1c, 0 }, - { 38, 375, 0, 0x1b, 0 }, - { 25, 250, 0, 0x1a, 0 }, - { 13, 125, 0, 0x19, 0 }, -}; - -static void generate_T_state_entries(int core, int cores_per_package) -{ - /* Indicate SW_ALL coordination for T-states */ - acpigen_write_TSD_package(core, cores_per_package, SW_ALL); - - /* Indicate FFixedHW so OS will use MSR */ - acpigen_write_empty_PTC(); - - /* Set a T-state limit that can be modified in NVS */ - acpigen_write_TPC("\\TLVL"); - - /* - * CPUID.(EAX=6):EAX[5] indicates support - * for extended throttle levels. - */ - if (cpuid_eax(6) & (1 << 5)) - acpigen_write_TSS_package( - ARRAY_SIZE(tss_table_fine), tss_table_fine); - else - acpigen_write_TSS_package( - ARRAY_SIZE(tss_table_coarse), tss_table_coarse); -} - -static int calculate_power(int tdp, int p1_ratio, int ratio) -{ - u32 m; - u32 power; - - /* - * M = ((1.1 - ((p1_ratio - ratio) * 0.00625)) / 1.1) ^ 2 - * - * Power = (ratio / p1_ratio) * m * tdp - */ - - m = (110000 - ((p1_ratio - ratio) * 625)) / 11; - m = (m * m) / 1000; - - power = ((ratio * 100000 / p1_ratio) / 100); - power *= (m / 100) * (tdp / 1000); - power /= 1000; - - return (int)power; -} - -static int get_core_frequency_mhz(int ratio) -{ - int fsb, core_freq; - - /* Get BCLK - different SKUs can have different BCLK */ - fsb = get_timer_fsb(); - - printk(BIOS_DEBUG, "BCLK:%d MHz ratio:%d\n", fsb, ratio); - - core_freq = DIV_ROUND_CLOSEST(fsb * ratio, 100) * 100; - printk(BIOS_DEBUG, "core frequency for ratio(%d) %dMHz\n", ratio, core_freq); - return core_freq; -} - -static void generate_P_state_entries(int core, int cores_per_package) -{ - int ratio_min, ratio_max, ratio_turbo, ratio_step; - int coord_type, power_max, num_entries; - int ratio, power, clock, clock_max; - msr_t msr; - - /* Rangeley uses hardware only control */ - coord_type = HW_ALL; - - /* Get bus ratio limits and calculate clock speeds */ - msr = rdmsr(MSR_PLATFORM_INFO); - ratio_min = (msr.hi >> (40-32)) & 0xff; /* Max Efficiency Ratio */ - - /* Determine if this CPU has configurable TDP */ - if (cpu_config_tdp_levels()) { - /* Set max ratio to nominal TDP ratio */ - msr = rdmsr(MSR_CONFIG_TDP_NOMINAL); - ratio_max = msr.lo & 0xff; - } else { - /* Max Non-Turbo Ratio */ - ratio_max = (msr.lo >> 8) & 0xff; - } - clock_max = get_core_frequency_mhz(ratio_max); - - /* Calculate CPU TDP in mW */ - msr = rdmsr(MSR_PKG_POWER_SKU_UNIT); - power_max = 2 << ((msr.lo & 0xf) - 1); - - - /* Write _PCT indicating use of FFixedHW */ - acpigen_write_empty_PCT(); - - /* Write _PPC with no limit on supported P-state */ - acpigen_write_PPC_NVS(); - - /* Write PSD indicating configured coordination type */ - acpigen_write_PSD_package(core, cores_per_package, coord_type); - - /* Add P-state entries in _PSS table */ - acpigen_write_name("_PSS"); - - /* Determine ratio points */ - ratio_step = PSS_RATIO_STEP; - num_entries = (ratio_max - ratio_min) / ratio_step; - while (num_entries > PSS_MAX_ENTRIES-1) { - ratio_step <<= 1; - num_entries >>= 1; - } - - /* P[T] is Turbo state if enabled */ - if (get_turbo_state() == TURBO_ENABLED) { - /* _PSS package count including Turbo */ - acpigen_write_package(num_entries + 2); - - msr = rdmsr(MSR_TURBO_RATIO_LIMIT); - ratio_turbo = msr.lo & 0xff; - - /* Add entry for Turbo ratio */ - acpigen_write_PSS_package( - clock_max + 1, /*MHz*/ - power_max, /*mW*/ - PSS_LATENCY_TRANSITION, /*lat1*/ - PSS_LATENCY_BUSMASTER, /*lat2*/ - ratio_turbo << 8, /*control*/ - ratio_turbo << 8); /*status*/ - } else { - /* _PSS package count without Turbo */ - acpigen_write_package(num_entries + 1); - } - - /* First regular entry is max non-turbo ratio */ - acpigen_write_PSS_package( - clock_max, /*MHz*/ - power_max, /*mW*/ - PSS_LATENCY_TRANSITION, /*lat1*/ - PSS_LATENCY_BUSMASTER, /*lat2*/ - ratio_max << 8, /*control*/ - ratio_max << 8); /*status*/ - - /* Generate the remaining entries */ - for (ratio = ratio_min + ((num_entries - 1) * ratio_step); - ratio >= ratio_min; ratio -= ratio_step) { - - /* Calculate power at this ratio */ - power = calculate_power(power_max, ratio_max, ratio); - clock = get_core_frequency_mhz(ratio); - - acpigen_write_PSS_package( - clock, /*MHz*/ - power, /*mW*/ - PSS_LATENCY_TRANSITION, /*lat1*/ - PSS_LATENCY_BUSMASTER, /*lat2*/ - ratio << 8, /*control*/ - ratio << 8); /*status*/ - } - - /* Fix package length */ - acpigen_pop_len(); -} - -void generate_cpu_entries(struct device *device) -{ - int coreID, cpuID, pcontrol_blk = PMB0_BASE, plen = 6; - int totalcores = dev_count_cpu(); - int cores_per_package = get_cores_per_package(); - int numcpus = totalcores/cores_per_package; - - printk(BIOS_DEBUG, "Found %d CPU(s) with %d core(s) each.\n", - numcpus, cores_per_package); - - for (cpuID = 1; cpuID <= numcpus; cpuID++) { - for (coreID = 1; coreID <= cores_per_package; coreID++) { - if (coreID > 1) { - pcontrol_blk = 0; - plen = 0; - } - - /* Generate processor \_PR.CPUx */ - acpigen_write_processor( - (cpuID-1)*cores_per_package+coreID-1, - pcontrol_blk, plen); - - /* Generate P-state tables */ - generate_P_state_entries( - cpuID-1, cores_per_package); - - /* Generate C-state tables */ - generate_C_state_entries(); - - /* Generate T-state tables */ - generate_T_state_entries( - cpuID-1, cores_per_package); - - acpigen_pop_len(); - } - } - - /* PPKG is usually used for thermal management - of the first and only package. */ - acpigen_write_processor_package("PPKG", 0, cores_per_package); - - /* Add a method to notify processor nodes */ - acpigen_write_processor_cnot(cores_per_package); -} - -struct chip_operations cpu_intel_model_406dx_ops = { - CHIP_NAME("Intel Rangeley CPU") -}; diff --git a/src/cpu/intel/fsp_model_406dx/bootblock.c b/src/cpu/intel/fsp_model_406dx/bootblock.c deleted file mode 100644 index 045b0f628c..0000000000 --- a/src/cpu/intel/fsp_model_406dx/bootblock.c +++ /dev/null @@ -1,89 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include -#include -#include -#include -#include -#include - -#include "model_406dx.h" - -/* - * check for a warm reset and do a hard reset instead. - */ -static void check_for_warm_reset(void) -{ - - /* - * Check if INIT# is asserted by port 0xCF9 and whether RCBA has been - * set. If either is true, then this is a warm reset so execute a - * Hard Reset - */ - if ((inb(0xcf9) == 0x04) || - (pci_io_read_config32(SOC_LPC_DEV, RCBA) - & RCBA_ENABLE)) { - outb(0x00, 0xcf9); - outb(0x06, 0xcf9); - } -} - -static void set_var_mtrr(int reg, uint32_t base, uint32_t size, int type) -{ - /* Bit Bit 32-35 of MTRRphysMask should be set to 1 */ - msr_t basem, maskm; - basem.lo = base | type; - basem.hi = 0; - wrmsr(MTRR_PHYS_BASE(reg), basem); - maskm.lo = ~(size - 1) | MTRR_PHYS_MASK_VALID; - maskm.hi = (1 << (CONFIG_CPU_ADDR_BITS - 32)) - 1; - wrmsr(MTRR_PHYS_MASK(reg), maskm); -} - -static void enable_rom_caching(void) -{ - msr_t msr; - - disable_cache(); - set_var_mtrr(1, CACHE_ROM_BASE, CACHE_ROM_SIZE, MTRR_TYPE_WRPROT); - enable_cache(); - - /* Enable Variable MTRRs */ - msr.hi = 0x00000000; - msr.lo = 0x00000800; - wrmsr(MTRR_DEF_TYPE_MSR, msr); -} - -static void set_no_evict_mode_msr(void) -{ - msr_t msr; - msr.hi = 0x00000000; - msr.lo = 0x00000000; - - wrmsr(MSR_NO_EVICT_MODE, msr); -} - -static void bootblock_cpu_init(void) -{ - /* Check for Warm Reset */ - check_for_warm_reset(); - - /* Load microcode before any caching. */ - intel_update_microcode_from_cbfs(); - - enable_rom_caching(); - set_no_evict_mode_msr(); -} diff --git a/src/cpu/intel/fsp_model_406dx/chip.h b/src/cpu/intel/fsp_model_406dx/chip.h deleted file mode 100644 index aaaed160ad..0000000000 --- a/src/cpu/intel/fsp_model_406dx/chip.h +++ /dev/null @@ -1,30 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef CPU_FSP_MODEL406DX_CHIP_H -#define CPU_FSP_MODEL406DX_CHIP_H - -/* Magic value used to locate this chip in the device tree */ -#define SPEEDSTEP_APIC_MAGIC 0xACAC - -struct cpu_intel_fsp_model_406dx_config { - int c1_battery; /* ACPI C1 on Battery Power */ - int c2_battery; /* ACPI C2 on Battery Power */ - int c3_battery; /* ACPI C3 on Battery Power */ - - int c1_acpower; /* ACPI C1 on AC Power */ - int c2_acpower; /* ACPI C2 on AC Power */ - int c3_acpower; /* ACPI C3 on AC Power */ -}; - -#endif /* CPU_FSP_MODEL406DX_CHIP_H */ diff --git a/src/cpu/intel/fsp_model_406dx/model_406dx.h b/src/cpu/intel/fsp_model_406dx/model_406dx.h deleted file mode 100644 index adfec562ef..0000000000 --- a/src/cpu/intel/fsp_model_406dx/model_406dx.h +++ /dev/null @@ -1,87 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef _CPU_INTEL_MODEL_406DX_H -#define _CPU_INTEL_MODEL_406DX_H - - -#define MSR_FEATURE_CONFIG 0x13c -#define MSR_FLEX_RATIO 0x194 -#define FLEX_RATIO_LOCK (1 << 20) -#define FLEX_RATIO_EN (1 << 16) -#define MSR_TEMPERATURE_TARGET 0x1a2 -#define MSR_LT_LOCK_MEMORY 0x2e7 - -#define MSR_NO_EVICT_MODE 0x2e0 -#define MSR_PIC_MSG_CONTROL 0x2e -#define MSR_PLATFORM_INFO 0xce -#define PLATFORM_INFO_SET_TDP (1 << 29) -#define MSR_PKG_CST_CONFIG_CONTROL 0xe2 -#define MSR_PMG_IO_CAPTURE_BASE 0xe4 - -#define MSR_MISC_PWR_MGMT 0x1aa -#define MISC_PWR_MGMT_EIST_HW_DIS (1 << 0) -#define MSR_TURBO_RATIO_LIMIT 0x1ad -#define MSR_POWER_CTL 0x1fc - -#define MSR_PKGC3_IRTL 0x60a -#define MSR_PKGC6_IRTL 0x60b -#define MSR_PKGC7_IRTL 0x60c -#define IRTL_VALID (1 << 15) -#define IRTL_1_NS (0 << 10) -#define IRTL_32_NS (1 << 10) -#define IRTL_1024_NS (2 << 10) -#define IRTL_32768_NS (3 << 10) -#define IRTL_1048576_NS (4 << 10) -#define IRTL_33554432_NS (5 << 10) -#define IRTL_RESPONSE_MASK (0x3ff) - -/* long duration in low dword, short duration in high dword */ -#define MSR_PKG_POWER_LIMIT 0x610 -#define PKG_POWER_LIMIT_MASK 0x7fff -#define PKG_POWER_LIMIT_EN (1 << 15) -#define PKG_POWER_LIMIT_CLAMP (1 << 16) -#define PKG_POWER_LIMIT_TIME_SHIFT 17 -#define PKG_POWER_LIMIT_TIME_MASK 0x7f - -#define MSR_PP0_CURRENT_CONFIG 0x601 -#define PP0_CURRENT_LIMIT (112 << 3) /* 112 A */ -#define MSR_PP1_CURRENT_CONFIG 0x602 -#define PP1_CURRENT_LIMIT_SNB (35 << 3) /* 35 A */ -#define PP1_CURRENT_LIMIT_IVB (50 << 3) /* 50 A */ -#define MSR_PKG_POWER_SKU_UNIT 0x606 -#define MSR_PKG_POWER_SKU 0x614 -#define MSR_PP0_POWER_LIMIT 0x638 -#define MSR_PP1_POWER_LIMIT 0x640 - -#define IVB_CONFIG_TDP_MIN_CPUID 0x306a2 -#define MSR_CONFIG_TDP_NOMINAL 0x648 -#define MSR_CONFIG_TDP_LEVEL1 0x649 -#define MSR_CONFIG_TDP_LEVEL2 0x64a -#define MSR_CONFIG_TDP_CONTROL 0x64b -#define MSR_TURBO_ACTIVATION_RATIO 0x64c - -/* P-state configuration */ -#define PSS_MAX_ENTRIES 8 -#define PSS_RATIO_STEP 2 -#define PSS_LATENCY_TRANSITION 10 -#define PSS_LATENCY_BUSMASTER 10 - -#ifndef __ROMCC__ -/* Lock MSRs */ -void intel_model_406dx_finalize_smm(void); -int cpu_config_tdp_levels(void); -#endif - -#endif /* _CPU_INTEL_MODEL_406DX_H */ diff --git a/src/cpu/intel/fsp_model_406dx/model_406dx_init.c b/src/cpu/intel/fsp_model_406dx/model_406dx_init.c deleted file mode 100644 index 94925106f8..0000000000 --- a/src/cpu/intel/fsp_model_406dx/model_406dx_init.c +++ /dev/null @@ -1,169 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include "model_406dx.h" -#include "chip.h" - -int cpu_config_tdp_levels(void) -{ - msr_t platform_info; - - /* Minimum CPU revision */ - if (cpuid_eax(1) < IVB_CONFIG_TDP_MIN_CPUID) - return 0; - - /* Bits 34:33 indicate how many levels supported */ - platform_info = rdmsr(MSR_PLATFORM_INFO); - return (platform_info.hi >> 1) & 3; -} - -static void configure_misc(void) -{ - msr_t msr; - - msr = rdmsr(IA32_MISC_ENABLE); - msr.lo |= (1 << 0); /* Fast String enable */ - msr.lo |= (1 << 3); /* TM1/TM2/EMTTM enable */ - msr.lo |= (1 << 16); /* Enhanced SpeedStep Enable */ - wrmsr(IA32_MISC_ENABLE, msr); - - /* Disable Thermal interrupts */ - msr.lo = 0; - msr.hi = 0; - wrmsr(IA32_THERM_INTERRUPT, msr); -} - -static void configure_mca(void) -{ - msr_t msr; - int i; - - msr.lo = msr.hi = 0; - /* This should only be done on a cold boot */ - for (i = 0; i < 6; i++) - wrmsr(IA32_MC0_STATUS + (i * 4), msr); -} - -/* - * Initialize any extra cores/threads in this package. - */ -static void intel_cores_init(struct device *cpu) -{ - struct cpuid_result result; - unsigned int threads_per_package, threads_per_core, i; - - /* Logical processors (threads) per core */ - result = cpuid_ext(0xb, 0); - threads_per_core = result.ebx & 0xffff; - - /* Logical processors (threads) per package */ - result = cpuid_ext(0xb, 1); - threads_per_package = result.ebx & 0xffff; - - /* Only initialize extra cores from BSP */ - if (cpu->path.apic.apic_id) - return; - - printk(BIOS_DEBUG, "CPU: %u has %u cores, %u threads per core\n", - cpu->path.apic.apic_id, threads_per_package/threads_per_core, - threads_per_core); - - for (i = 1; i < threads_per_package; ++i) { - struct device_path cpu_path; - struct device *new; - - /* Build the CPU device path */ - cpu_path.type = DEVICE_PATH_APIC; - cpu_path.apic.apic_id = - cpu->path.apic.apic_id + i; - - /* Update APIC ID if no hyperthreading */ - if (threads_per_core == 1) - cpu_path.apic.apic_id <<= 1; - - /* Allocate the new CPU device structure */ - new = alloc_dev(cpu->bus, &cpu_path); - if (!new) - continue; - - printk(BIOS_DEBUG, "CPU: %u has core %u\n", - cpu->path.apic.apic_id, - new->path.apic.apic_id); - - /* Start the new CPU */ - if (is_smp_boot() && !start_cpu(new)) { - /* Record the error in cpu? */ - printk(BIOS_ERR, "CPU %u would not start!\n", - new->path.apic.apic_id); - } - } -} - -static void model_406dx_init(struct device *cpu) -{ - char processor_name[49]; - - /* Turn on caching if we haven't already */ - x86_enable_cache(); - - /* Load microcode */ - if (CONFIG(SUPPORT_CPU_UCODE_IN_CBFS)) - intel_update_microcode_from_cbfs(); - - /* Clear out pending MCEs */ - configure_mca(); - - /* Print processor name */ - fill_processor_name(processor_name); - printk(BIOS_INFO, "CPU: %s.\n", processor_name); - - x86_mtrr_check(); - - /* Enable the local CPU APICs */ - setup_lapic(); - - /* Set virtualization based on Kconfig option */ - set_vmx_and_lock(); - - /* Configure Enhanced SpeedStep and Thermal Sensors */ - configure_misc(); - - /* Start up extra cores */ - intel_cores_init(cpu); -} - -static struct device_operations cpu_dev_ops = { - .init = model_406dx_init, -}; - -static const struct cpu_device_id cpu_table[] = { - { X86_VENDOR_INTEL, 0x406d0 }, /* Intel Avoton/Rangeley A1 */ - { X86_VENDOR_INTEL, 0x406d8 }, /* Intel Avoton/Rangeley B0 */ - { 0, 0 }, -}; - -static const struct cpu_driver driver __cpu_driver = { - .ops = &cpu_dev_ops, - .id_table = cpu_table, -}; diff --git a/src/include/device/pci_ids.h b/src/include/device/pci_ids.h index 70cf3aa339..18d6f601c1 100644 --- a/src/include/device/pci_ids.h +++ b/src/include/device/pci_ids.h @@ -2583,8 +2583,6 @@ #define PCI_DEVICE_ID_INTEL_COUGARPOINT_LPC_MAX 0x1c5f #define PCI_DEVICE_ID_INTEL_PANTHERPOINT_LPC_MIN 0x1e41 #define PCI_DEVICE_ID_INTEL_PANTHERPOINT_LPC_MAX 0x1e5f -#define PCI_DEVICE_ID_INTEL_RANGELEY_LPC_MIN 0x1f38 -#define PCI_DEVICE_ID_INTEL_RANGELEY_LPC_MAX 0x1f3b #define PCI_DEVICE_ID_INTEL_TGP_LPC 0x27bc /* Intel 82801E (C-ICH) */ diff --git a/src/northbridge/intel/fsp_rangeley/Kconfig b/src/northbridge/intel/fsp_rangeley/Kconfig deleted file mode 100644 index bc7352641c..0000000000 --- a/src/northbridge/intel/fsp_rangeley/Kconfig +++ /dev/null @@ -1,88 +0,0 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2010 Google Inc. -## Copyright (C) 2013 Sage Electronic Engineering, LLC. -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; version 2 of the License. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## - -config NORTHBRIDGE_INTEL_FSP_RANGELEY - bool - select CPU_INTEL_FSP_MODEL_406DX - -if NORTHBRIDGE_INTEL_FSP_RANGELEY - -config MMCONF_BASE_ADDRESS - hex - default 0xe0000000 - -choice - prompt "Set TSEG Size" - default SET_TSEG_1MB if SET_DEFAULT_TSEG_1MB - default SET_TSEG_2MB if SET_DEFAULT_TSEG_2MB - default SET_TSEG_4MB if SET_DEFAULT_TSEG_4MB - default SET_TSEG_8MB if SET_DEFAULT_TSEG_8MB - -config SET_TSEG_1MB - bool "1 MB" - help - Set the TSEG area to 1 MB. - -config SET_TSEG_2MB - bool "2 MB" - help - Set the TSEG area to 2 MB. - -config SET_TSEG_4MB - bool "4 MB" - help - Set the TSEG area to 4 MB. - -config SET_TSEG_8MB - bool "8 MB" - help - Set the TSEG area to 8 MB. -endchoice - -config SMM_TSEG_SIZE - hex - default 0x200000 if SET_TSEG_2MB - default 0x400000 if SET_TSEG_4MB - default 0x800000 if SET_TSEG_8MB - default 0x100000 # SET_TSEG_1MB - -config SMM_RESERVED_SIZE - hex - default 0x200000 if SET_TSEG_2MB - default 0x400000 if SET_TSEG_4MB - default 0x800000 if SET_TSEG_8MB - default 0x100000 # SET_TSEG_1MB - -config SET_DEFAULT_TSEG_1MB - bool - default n - -config SET_DEFAULT_TSEG_2MB - bool - default n - -config SET_DEFAULT_TSEG_4MB - bool - default n - -config SET_DEFAULT_TSEG_8MB - bool - default n - -# Rangeley Specific FSP Kconfig -source src/northbridge/intel/fsp_rangeley/fsp/Kconfig - -endif # NORTHBRIDGE_INTEL_FSP_RANGELEY diff --git a/src/northbridge/intel/fsp_rangeley/Makefile.inc b/src/northbridge/intel/fsp_rangeley/Makefile.inc deleted file mode 100644 index f02e3c4aec..0000000000 --- a/src/northbridge/intel/fsp_rangeley/Makefile.inc +++ /dev/null @@ -1,34 +0,0 @@ -# -# This file is part of the coreboot project. -# -# Copyright (C) 2010 Google Inc. -# Copyright (C) 2013-2014 Sage Electronic Engineering, LLC. -# -# This program is free software; you can redistribute it and/or modify -# it under the terms of the GNU General Public License as published by -# the Free Software Foundation; version 2 of the License. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# - -ifeq ($(CONFIG_NORTHBRIDGE_INTEL_FSP_RANGELEY),y) - -subdirs-y += fsp -ramstage-y += northbridge.c - -ramstage-y += acpi.c -ramstage-y += port_access.c - -romstage-y += memmap.c -romstage-y += ../../../arch/x86/walkcbfs.S -romstage-y += port_access.c - -CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR) - -CPPFLAGS_common += -I$(src)/northbridge/intel/fsp_rangeley/ -CPPFLAGS_common += -I$(src)/northbridge/intel/fsp_rangeley/fsp - -endif diff --git a/src/northbridge/intel/fsp_rangeley/acpi.c b/src/northbridge/intel/fsp_rangeley/acpi.c deleted file mode 100644 index 0c52d52588..0000000000 --- a/src/northbridge/intel/fsp_rangeley/acpi.c +++ /dev/null @@ -1,71 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007-2009 coresystems GmbH - * Copyright (C) 2012 The Chromium OS Authors - * Copyright (C) 2013 Sage Electronic Engineering, LLC - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include -#include -#include -#include - -#include "northbridge.h" - -unsigned long acpi_fill_mcfg(unsigned long current) -{ - struct device *dev; - u32 pciexbar = 0; - u32 pciexbar_reg; - int max_buses; - int pci_dev_id; - - for (pci_dev_id = PCI_DEVICE_ID_RG_MIN; pci_dev_id <= PCI_DEVICE_ID_RG_MAX; pci_dev_id++) { - dev = dev_find_device(PCI_VENDOR_ID_INTEL, pci_dev_id, 0); - if (dev) - break; - } - - if (!dev) - return current; - - pciexbar_reg = sideband_read(B_UNIT, BECREG); - - /* MMCFG not supported or not enabled. */ - if (!(pciexbar_reg & (1 << 0))) - return current; - - /* 256MB ECAM range */ - pciexbar = pciexbar_reg & ((1 << 31)|(1 << 30)|(1 << 29)|(1 << 28)); - max_buses = 256; - - current += acpi_create_mcfg_mmconfig((acpi_mcfg_mmconfig_t *) current, - pciexbar, 0x0, 0x0, max_buses - 1); - - return current; -} - -void northbridge_acpi_fill_ssdt_generator(struct device *device) -{ - u32 bmbound; - char pscope[] = "\\_SB.PCI0"; - - bmbound = sideband_read(B_UNIT, BMBOUND); - acpigen_write_scope(pscope); - acpigen_write_name_dword("BMBD", bmbound); - acpigen_pop_len(); - generate_cpu_entries(device); -} diff --git a/src/northbridge/intel/fsp_rangeley/acpi/hostbridge.asl b/src/northbridge/intel/fsp_rangeley/acpi/hostbridge.asl deleted file mode 100644 index 4e9bc324c6..0000000000 --- a/src/northbridge/intel/fsp_rangeley/acpi/hostbridge.asl +++ /dev/null @@ -1,131 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007-2009 coresystems GmbH - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -Name(_HID,EISAID("PNP0A08")) // PCIe -Name(_CID,EISAID("PNP0A03")) // PCI - -Name(_BBN, 0) - -// This is in the SSDT and can be accessed by the DSDT -External (BMBD) - -// Current Resource Settings -Name (MCRS, ResourceTemplate() -{ - // Bus Numbers - WordBusNumber (ResourceProducer, MinFixed, MaxFixed, PosDecode, - 0x0000, 0x0000, 0x00ff, 0x0000, 0x0100,,, PB00) - - // IO Region 0 - DWordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, - 0x0000, 0x0000, 0x0cf7, 0x0000, 0x0cf8,,, PI00) - - // PCI Config Space - Io (Decode16, 0x0cf8, 0x0cf8, 0x0001, 0x0008) - - // IO Region 1 - DWordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, - 0x0000, 0x0d00, 0xffff, 0x0000, 0xf300,,, PI01) - - // VGA memory (0xa0000-0xbffff) - DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, - Cacheable, ReadWrite, - 0x00000000, 0x000a0000, 0x000bffff, 0x00000000, - 0x00020000,,, ASEG) - - // OPROM reserved (0xd0000-0xd3fff) - DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, - Cacheable, ReadWrite, - 0x00000000, 0x000d0000, 0x000d3fff, 0x00000000, - 0x00004000,,, OPR0) - - // OPROM reserved (0xd4000-0xd7fff) - DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, - Cacheable, ReadWrite, - 0x00000000, 0x000d4000, 0x000d7fff, 0x00000000, - 0x00004000,,, OPR1) - - // OPROM reserved (0xd8000-0xdbfff) - DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, - Cacheable, ReadWrite, - 0x00000000, 0x000d8000, 0x000dbfff, 0x00000000, - 0x00004000,,, OPR2) - - // OPROM reserved (0xdc000-0xdffff) - DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, - Cacheable, ReadWrite, - 0x00000000, 0x000dc000, 0x000dffff, 0x00000000, - 0x00004000,,, OPR3) - - // BIOS Extension (0xe0000-0xe3fff) - DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, - Cacheable, ReadWrite, - 0x00000000, 0x000e0000, 0x000e3fff, 0x00000000, - 0x00004000,,, ESG0) - - // BIOS Extension (0xe4000-0xe7fff) - DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, - Cacheable, ReadWrite, - 0x00000000, 0x000e4000, 0x000e7fff, 0x00000000, - 0x00004000,,, ESG1) - - // BIOS Extension (0xe8000-0xebfff) - DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, - Cacheable, ReadWrite, - 0x00000000, 0x000e8000, 0x000ebfff, 0x00000000, - 0x00004000,,, ESG2) - - // BIOS Extension (0xec000-0xeffff) - DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, - Cacheable, ReadWrite, - 0x00000000, 0x000ec000, 0x000effff, 0x00000000, - 0x00004000,,, ESG3) - - // System BIOS (0xf0000-0xfffff) - DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, - Cacheable, ReadWrite, - 0x00000000, 0x000f0000, 0x000fffff, 0x00000000, - 0x00010000,,, FSEG) - - // PCI Memory Region (Top of memory-CONFIG_MMCONF_BASE_ADDRESS) - DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, - Cacheable, ReadWrite, - 0x00000000, 0x00000000, 0, 0x00000000, - 0,,, PM01) - - // TPM Area (0xfed40000-0xfed44fff) - DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, - Cacheable, ReadWrite, - 0x00000000, 0xfed40000, 0xfed44fff, 0x00000000, - 0x00005000,,, TPMR) -}) // End MCRS - -Method (_CRS, 0, Serialized) -{ - // Find PCI resource area in MCRS - CreateDwordField(MCRS, ^PM01._MIN, PMIN) - CreateDwordField(MCRS, ^PM01._MAX, PMAX) - CreateDwordField(MCRS, ^PM01._LEN, PLEN) - - // Fix up PCI memory region - // Start with Top of Lower Usable DRAM - // Memory goes from BMBOUND to CONFIG_MMCONF_BASE_ADDRESS (PM01 above) - Store (BMBD, PMIN) - Store (Subtract(CONFIG_MMCONF_BASE_ADDRESS, 1), PMAX) - Add(Subtract(PMAX, PMIN), 1, PLEN) // Store Memory Size - - Return (MCRS) -} // End _CRS diff --git a/src/northbridge/intel/fsp_rangeley/acpi/rangeley.asl b/src/northbridge/intel/fsp_rangeley/acpi/rangeley.asl deleted file mode 100644 index ba74fcb696..0000000000 --- a/src/northbridge/intel/fsp_rangeley/acpi/rangeley.asl +++ /dev/null @@ -1,36 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007-2009 coresystems GmbH - * Copyright (C) 2013 Sage Electronic Engineering, LLC. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include "../northbridge.h" -#include "hostbridge.asl" - -/* PCI Device Resource Consumption */ -Device (PDRC) -{ - Name (_HID, EISAID("PNP0C02")) - Name (_UID, 1) - - Name (PDRS, ResourceTemplate() { - Memory32Fixed(ReadWrite, DEFAULT_ECBASE, 0x10000000) - }) - - // Current Resource Settings - Method (_CRS, 0, Serialized) - { - Return(PDRS) - } -} diff --git a/src/northbridge/intel/fsp_rangeley/chip.h b/src/northbridge/intel/fsp_rangeley/chip.h deleted file mode 100644 index 9c7d5a2b14..0000000000 --- a/src/northbridge/intel/fsp_rangeley/chip.h +++ /dev/null @@ -1,69 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007-2008 coresystems GmbH - * Copyright (C) 2015 Intel Corporation - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef _FSP_RANGELEY_CHIP_H_ -#define _FSP_RANGELEY_CHIP_H_ - -#include -#include - -struct northbridge_intel_fsp_rangeley_config { - - /* Set the CPGC exp_loop_cnt field for RMT execution 2^(exp_loop_cnt -1) */ - /* Valid values: 0 - 15 */ - uint8_t MrcRmtCpgcExpLoopCntValue; - /* Set the CPGC num_bursts field for RMT execution 2^(num_bursts -1) */ - /* Valid values: 0 - 15 */ - uint8_t MrcRmtCpgcNumBursts; - /* DIMM SPD SMBus Addresses */ - uint8_t SpdBaseAddress_0_0; - uint8_t SpdBaseAddress_0_1; - uint8_t SpdBaseAddress_1_0; - uint8_t SpdBaseAddress_1_1; - - uint8_t EnableLan; - uint8_t EnableSata2; - uint8_t EnableSata3; - uint8_t EnableIQAT; - uint8_t EnableUsb20; - uint8_t PrintDebugMessages; - uint8_t Fastboot; - uint8_t EccSupport; - uint8_t SpdWriteProtect; - /* Enable = Memory Down, Disable = DIMM */ - uint8_t MemoryDown; - /* Enable the Rank Margin Tool, needs PrintDebugMessages */ - uint8_t MrcRmtSupport; - - /* PCIe port bifurcation control */ - uint8_t Bifurcation; - #define BIFURCATION_4_4_4_4 0 - #define BIFURCATION_4_4_8 1 - #define BIFURCATION_8_4_4 2 - #define BIFURCATION_8_8 3 - #define BIFURCATION_16 4 - - /* PCIe port de-emphasis control */ - uint8_t PcdPcieRootPort1DeEmphasis; - uint8_t PcdPcieRootPort2DeEmphasis; - uint8_t PcdPcieRootPort3DeEmphasis; - uint8_t PcdPcieRootPort4DeEmphasis; - #define DE_EMPHASIS_DEFAULT 0 - #define DE_EMPHASIS_MINUS_6_0_DB 1 - #define DE_EMPHASIS_MINUS_3_5_DB 2 -}; - -#endif diff --git a/src/northbridge/intel/fsp_rangeley/fsp/Kconfig b/src/northbridge/intel/fsp_rangeley/fsp/Kconfig deleted file mode 100644 index 67ed66b9ed..0000000000 --- a/src/northbridge/intel/fsp_rangeley/fsp/Kconfig +++ /dev/null @@ -1,45 +0,0 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2014 Sage Electronic Engineering, LLC. -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; version 2 of the License. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## - -config RANGELEY_FSP_SPECIFIC_OPTIONS - def_bool y - select PLATFORM_USES_FSP1_0 - select USE_GENERIC_FSP_CAR_INC - select FSP_USES_UPD - select ENABLE_MRC_CACHE #rangeley FSP always needs MRC data - -config FSP_FILE - string - default "../intel/fsp/rangeley/FvFsp.bin" - help - The path and filename of the Intel FSP binary for this platform. - -config FSP_LOC - hex - default 0xfff80000 - help - The location in CBFS that the FSP is located. This must match the - value that is set in the FSP binary. If the FSP needs to be moved, - rebase the FSP with Intel's BCT (tool). - - The Rangeley FSP is built with a preferred base address of 0xFFF80000 - -config DCACHE_RAM_BASE - hex - default 0xfef00000 - -config DCACHE_RAM_SIZE - hex - default 0x4000 diff --git a/src/northbridge/intel/fsp_rangeley/fsp/Makefile.inc b/src/northbridge/intel/fsp_rangeley/fsp/Makefile.inc deleted file mode 100644 index 09c5bc506d..0000000000 --- a/src/northbridge/intel/fsp_rangeley/fsp/Makefile.inc +++ /dev/null @@ -1,17 +0,0 @@ -# -# This file is part of the coreboot project. -# -# Copyright (C) 2014 Sage Electronic Engineering, LLC. -# -# This program is free software; you can redistribute it and/or modify -# it under the terms of the GNU General Public License as published by -# the Free Software Foundation; version 2 of the License. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# - -ramstage-y += chipset_fsp_util.c -romstage-y += chipset_fsp_util.c diff --git a/src/northbridge/intel/fsp_rangeley/fsp/chipset_fsp_util.c b/src/northbridge/intel/fsp_rangeley/fsp/chipset_fsp_util.c deleted file mode 100644 index 9acce5b8b9..0000000000 --- a/src/northbridge/intel/fsp_rangeley/fsp/chipset_fsp_util.c +++ /dev/null @@ -1,160 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2013-2014 Sage Electronic Engineering, LLC. - * Copyright (C) 2015 Intel Corporation - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include "../chip.h" - -/* Copy the default UPD region and settings to a buffer for modification */ -static void GetUpdDefaultFromFsp - (FSP_INFO_HEADER *FspInfo, UPD_DATA_REGION *UpdData) -{ - VPD_DATA_REGION *VpdDataRgnPtr; - UPD_DATA_REGION *UpdDataRgnPtr; - VpdDataRgnPtr = (VPD_DATA_REGION *)(UINT32)(FspInfo->CfgRegionOffset - + FspInfo->ImageBase); - UpdDataRgnPtr = (UPD_DATA_REGION *)(UINT32) - (VpdDataRgnPtr->PcdUpdRegionOffset + FspInfo->ImageBase); - memcpy((void *)UpdData, (void *)UpdDataRgnPtr, sizeof(UPD_DATA_REGION)); -} - -typedef struct northbridge_intel_fsp_rangeley_config config_t; - -/** - * Update the UPD data based on values from devicetree.cb - * - * @param UpdData Pointer to the UPD Data structure - */ -static void ConfigureDefaultUpdData(UPD_DATA_REGION *UpdData) -{ - DEVTREE_CONST struct device *dev; - DEVTREE_CONST config_t *config; - printk(BIOS_DEBUG, "Configure Default UPD Data\n"); - - dev = pcidev_path_on_root(SOC_DEVFN_SOC); - config = dev->chip_info; - - /* Set SPD addresses */ - if (config->SpdBaseAddress_0_0) { - UpdData->PcdSpdBaseAddress_0_0 = config->SpdBaseAddress_0_0; - } - if (config->SpdBaseAddress_0_1) { - UpdData->PcdSpdBaseAddress_0_1 = config->SpdBaseAddress_0_1; - } - if (config->SpdBaseAddress_1_0) { - UpdData->PcdSpdBaseAddress_1_0 = config->SpdBaseAddress_1_0; - } - if (config->SpdBaseAddress_1_1) { - UpdData->PcdSpdBaseAddress_1_1 = config->SpdBaseAddress_1_1; - } - if (config->EccSupport) { - UpdData->PcdEccSupport = config->EccSupport; - } - if (config->PrintDebugMessages) { - UpdData->PcdPrintDebugMessages = config->PrintDebugMessages; - } - if (config->Bifurcation) { - UpdData->PcdBifurcation = config->Bifurcation; - } - if (config->MemoryDown) { - UpdData->PcdMemoryDown = config->MemoryDown; - } - - UpdData->PcdMrcInitTsegSize = CONFIG_SMM_TSEG_SIZE >> 20; - - if (config->MrcRmtCpgcExpLoopCntValue) { - UpdData->PcdMrcRmtCpgcExpLoopCntValue = - config->MrcRmtCpgcExpLoopCntValue; - } - if (config->MrcRmtCpgcNumBursts) { - UpdData->PcdMrcRmtCpgcNumBursts = config->MrcRmtCpgcNumBursts; - } - if (CONFIG(ENABLE_FSP_FAST_BOOT)) - UpdData->PcdFastboot = UPD_ENABLE; - - /* - * Loop through all the SOC devices in the devicetree - * enabling and disabling them as requested. - */ - for (; dev; dev = dev->sibling) { - - if (dev->path.type != DEVICE_PATH_PCI) - continue; - - switch (dev->path.pci.devfn) { - case SOC_DEVFN_GBE1: - case SOC_DEVFN_GBE2: - case SOC_DEVFN_GBE3: - case SOC_DEVFN_GBE4: - UpdData->PcdEnableLan |= dev->enabled; - printk(BIOS_DEBUG, "PcdEnableLan %d\n", - UpdData->PcdEnableLan); - break; - case SOC_DEVFN_SATA2: - UpdData->PcdEnableSata2 = dev->enabled; - printk(BIOS_DEBUG, "PcdEnableSata2 %d\n", - UpdData->PcdEnableSata2); - break; - case SOC_DEVFN_SATA3: - UpdData->PcdEnableSata3 = dev->enabled; - printk(BIOS_DEBUG, "PcdEnableSata3 %d\n", - UpdData->PcdEnableSata3); - break; - case SOC_DEVFN_IQAT: - UpdData->PcdEnableIQAT |= dev->enabled; - printk(BIOS_DEBUG, "PcdEnableIQAT %d\n", - UpdData->PcdEnableIQAT); - break; - case SOC_DEVFN_USB2: - UpdData->PcdEnableUsb20 = dev->enabled; - printk(BIOS_DEBUG, "PcdEnableUsb20 %d\n", - UpdData->PcdEnableUsb20); - break; - } - } - - /* Set PCIe de-emphasis */ - UPD_DEFAULT_CHECK(PcdPcieRootPort1DeEmphasis); - UPD_DEFAULT_CHECK(PcdPcieRootPort2DeEmphasis); - UPD_DEFAULT_CHECK(PcdPcieRootPort3DeEmphasis); - UPD_DEFAULT_CHECK(PcdPcieRootPort4DeEmphasis); -} - -/* Set up the Rangeley specific structures for the call into the FSP */ -void chipset_fsp_early_init(FSP_INIT_PARAMS *pFspInitParams, - FSP_INFO_HEADER *fsp_ptr) -{ - FSP_INIT_RT_BUFFER *pFspRtBuffer = pFspInitParams->RtBufferPtr; - - /* Initialize the UPD Data */ - GetUpdDefaultFromFsp (fsp_ptr, pFspRtBuffer->Common.UpdDataRgnPtr); - ConfigureDefaultUpdData(pFspRtBuffer->Common.UpdDataRgnPtr); - pFspInitParams->NvsBufferPtr = NULL; - pFspRtBuffer->Common.BootMode = BOOT_WITH_FULL_CONFIGURATION; - - /* Find the fastboot cache that was saved in the ROM */ - pFspInitParams->NvsBufferPtr = find_and_set_fastboot_cache(); - - return; -} diff --git a/src/northbridge/intel/fsp_rangeley/fsp/chipset_fsp_util.h b/src/northbridge/intel/fsp_rangeley/fsp/chipset_fsp_util.h deleted file mode 100644 index b9d64c15f6..0000000000 --- a/src/northbridge/intel/fsp_rangeley/fsp/chipset_fsp_util.h +++ /dev/null @@ -1,48 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2013-2014 Sage Electronic Engineering, LLC. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef CHIPSET_FSP_UTIL_H -#define CHIPSET_FSP_UTIL_H - -#include -#include -#include -#include -#include -#include -#include -#include - -#define FSP_RESERVE_MEMORY_SIZE 0x200000 - -#define FSP_INFO_HEADER_GUID \ - { \ - 0x912740BE, 0x2284, 0x4734, {0xB9, 0x71, 0x84, 0xB0, 0x27, 0x35, 0x3F, 0x0C} \ - } - -#define FSP_NON_VOLATILE_STORAGE_HOB_GUID \ - { \ - 0x721acf02, 0x4d77, 0x4c2a, { 0xb3, 0xdc, 0x27, 0xb, 0x7b, 0xa9, 0xe4, 0xb0} \ - } - -/* - *The FSP Image ID is different for each platform's FSP and - * can be used to verify that the right FSP binary is loaded. - * For the Rangeley FSP, the Image Id is "AVN-FSP0". - */ -#define FSP_IMAGE_ID_DWORD0 0x2d4e5641 /* 'AVN-' */ -#define FSP_IMAGE_ID_DWORD1 0x30505346 /* 'FSP0' */ - -#endif /* CHIPSET_FSP_UTIL_H */ diff --git a/src/northbridge/intel/fsp_rangeley/memmap.c b/src/northbridge/intel/fsp_rangeley/memmap.c deleted file mode 100644 index 275ddd3ac1..0000000000 --- a/src/northbridge/intel/fsp_rangeley/memmap.c +++ /dev/null @@ -1,42 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 Google Inc. - * Copyright (C) 2013-2014 Sage Electronic Engineering, LLC. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include - -#include "northbridge.h" - -static uintptr_t smm_region_start(void) -{ - /* - * Calculate the top of usable (low) DRAM. - * The FSP's reserved memory sits just below the SMM region, - * allowing calculation of the top of usable memory. - */ - uintptr_t tom = sideband_read(B_UNIT, BMBOUND); - uintptr_t bsmmrrl = sideband_read(B_UNIT, BSMMRRL) << 20; - if (bsmmrrl) { - tom = bsmmrrl; - } - - return tom; -} - -void *cbmem_top_chipset(void) -{ - return (void *) (smm_region_start() - FSP_RESERVE_MEMORY_SIZE); -} diff --git a/src/northbridge/intel/fsp_rangeley/northbridge.c b/src/northbridge/intel/fsp_rangeley/northbridge.c deleted file mode 100644 index 4ebbe7ec15..0000000000 --- a/src/northbridge/intel/fsp_rangeley/northbridge.c +++ /dev/null @@ -1,251 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007-2009 coresystems GmbH - * Copyright (C) 2011 The ChromiumOS Authors. All rights reserved. - * Copyright (C) 2013-2014 Sage Electronic Engineering, LLC. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include "chip.h" -#include "northbridge.h" - -static int bridge_revision_id = -1; - -int bridge_silicon_revision(void) -{ - if (bridge_revision_id < 0) { - uint8_t stepping = cpuid_eax(1) & 0xf; - uint8_t bridge_id = pci_read_config16( - pcidev_on_root(0, 0), - PCI_DEVICE_ID) & 0xf0; - bridge_revision_id = bridge_id | stepping; - } - return bridge_revision_id; -} - -/* Reserve everything between A segment and 1MB: - * - * 0xa0000 - 0xbffff: legacy VGA - * 0xc0000 - 0xcffff: VGA OPROM (needed by kernel) - * 0xe0000 - 0xfffff: SeaBIOS, if used, otherwise DMI - */ -static const int legacy_hole_base_k = 0xa0000 / 1024; -static const int legacy_hole_size_k = 384; - -static int get_pcie_bar(u32 *base) -{ - struct device *dev; - u32 pciexbar_reg; - - *base = 0; - - dev = pcidev_on_root(0, 0); - if (!dev) - return 0; - - pciexbar_reg = sideband_read(B_UNIT, BECREG); - - if (!(pciexbar_reg & (1 << 0))) - return 0; - - *base = pciexbar_reg & ((1 << 31) | (1 << 30) | (1 << 29) | - (1 << 28)); - return 256; - -} - -static void add_fixed_resources(struct device *dev, int index) -{ - struct resource *resource; - - resource = new_resource(dev, index++); /* Local APIC */ - resource->base = LAPIC_DEFAULT_BASE; - resource->size = 0x00001000; - resource->flags = IORESOURCE_MEM | IORESOURCE_RESERVE | - IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED; - - mmio_resource(dev, index++, legacy_hole_base_k, legacy_hole_size_k); -} - -static void mc_add_dram_resources(struct device *dev) -{ - u32 tomlow, bmbound, bsmmrrl, bsmmrrh; - u64 bmbound_hi; - int index = 0; - - /* - * These are the host memory ranges : - * - 0 -> SMM (SMMRRL) : cacheable - * - SMM -> LOW TOM (BMBOUND) : cacheable WP - * - 4GB -> HIGH TOM (BMBOUND_HI): cacheable - * - */ - - tomlow = bmbound = sideband_read(B_UNIT, BMBOUND); - printk(BIOS_SPEW, "Top of Low Used DRAM (BMBOUND): 0x%08x\n", bmbound); - - bmbound_hi = (u64)(sideband_read(B_UNIT, BMBOUND_HI)) << 4; - printk(BIOS_SPEW, "Top of Upper Used DRAM (BMBOUND_HI): 0x%llx\n", bmbound_hi); - - bsmmrrl = sideband_read(B_UNIT, BSMMRRL) << 20; - bsmmrrh = ((sideband_read(B_UNIT, BSMMRRH) + 1) << 20) - 1; - if (bsmmrrl) { - tomlow = bsmmrrl; - printk(BIOS_DEBUG, "SMM memory location: 0x%x SMM memory size: 0x%x\n", bsmmrrl, (bsmmrrh - bsmmrrl + 1)); - printk(BIOS_DEBUG, "Subtracting %dM for SMM\n", (bmbound - bsmmrrl) >> 20); - } - tomlow -= FSP_RESERVE_MEMORY_SIZE; - printk(BIOS_SPEW, "Available memory below 4GB: 0x%08x (%dM)\n", tomlow, tomlow >> 20); - - /* Report the memory regions. */ - ram_resource(dev, index++, 0, legacy_hole_base_k); - ram_resource(dev, index++, legacy_hole_base_k + legacy_hole_size_k, - ((tomlow >> 10) - (legacy_hole_base_k + legacy_hole_size_k))); - - mmio_resource(dev, index++, tomlow >> 10, (bmbound - bsmmrrl) >> 10); - - if (bmbound_hi > 0x100000000) { - ram_resource(dev, index++, 0x100000000 >> 10, (bmbound_hi - 0x100000000) >> 10); - printk(BIOS_INFO, "Available memory above 4GB: %lluM\n", (bmbound_hi - 0x100000000) >> 20); - } - - add_fixed_resources(dev, index); -} - -static void mc_read_resources(struct device *dev) -{ - u32 pcie_config_base; - int buses; - - /* Call the normal read_resources */ - pci_dev_read_resources(dev); - - /* We use 0xcf as an unused index for our PCIe bar so that we find it again */ - buses = get_pcie_bar(&pcie_config_base); - if (buses) { - struct resource *resource = new_resource(dev, 0xcf); - mmconf_resource_init(resource, pcie_config_base, buses); - } - - /* Calculate and add DRAM resources. */ - mc_add_dram_resources(dev); -} - -static void pci_domain_set_resources(struct device *dev) -{ - /* - * Assign memory resources for PCI devices - */ - mc_add_dram_resources(dev); - - assign_resources(dev->link_list); -} - -static void mc_set_resources(struct device *dev) -{ - /* Call the normal set_resources */ - pci_dev_set_resources(dev); -} - -static void northbridge_init(struct device *dev) -{ -} - -static void northbridge_enable(struct device *dev) -{ -} - -static struct pci_operations intel_pci_ops = { - .set_subsystem = pci_dev_set_subsystem, -}; - -static struct device_operations pci_domain_ops = { - .read_resources = pci_domain_read_resources, - .set_resources = pci_domain_set_resources, - .enable_resources = NULL, - .init = NULL, - .scan_bus = pci_domain_scan_bus, -}; - -static struct device_operations mc_ops = { - .read_resources = mc_read_resources, - .set_resources = mc_set_resources, - .enable_resources = pci_dev_enable_resources, - .init = northbridge_init, - .acpi_fill_ssdt_generator = northbridge_acpi_fill_ssdt_generator, - .enable = northbridge_enable, - .scan_bus = 0, - .ops_pci = &intel_pci_ops, -}; - -/* - * The following entries are taken from Intel document number 510524, rev 1.6: - * Rangeley SoC External Design Specification (EDS) - * Section 10.3 PCI Configuration Space - * Table 10-6. PCI Devices and Functions - * - * These are the Device ID values for the item at bus 0, device 0, function 0. - */ -static const unsigned short pci_device_ids[] = { - 0x1f00, 0x1f01, 0x1f02, 0x1f03, - 0x1f04, 0x1f05, 0x1f06, 0x1f07, - 0x1f08, 0x1f09, 0x1f0a, 0x1f0b, - 0x1f0c, 0x1f0d, 0x1f0e, 0x1f0f, - 0, /* -- END OF LIST -- */ -}; - -static const struct pci_driver mc_driver __pci_driver = { - .ops = &mc_ops, - .vendor = PCI_VENDOR_ID_INTEL, - .devices = pci_device_ids, -}; - -static void cpu_bus_init(struct device *dev) -{ - initialize_cpus(dev->link_list); -} - -static struct device_operations cpu_bus_ops = { - .read_resources = DEVICE_NOOP, - .set_resources = DEVICE_NOOP, - .enable_resources = DEVICE_NOOP, - .init = cpu_bus_init, - .scan_bus = 0, -}; - -static void enable_dev(struct device *dev) -{ - /* Set the operations if it is a special bus type */ - if (dev->path.type == DEVICE_PATH_DOMAIN) { - dev->ops = &pci_domain_ops; - } else if (dev->path.type == DEVICE_PATH_CPU_CLUSTER) { - dev->ops = &cpu_bus_ops; - } -} - -struct chip_operations northbridge_intel_fsp_rangeley_ops = { - CHIP_NAME("Intel Rangeley Northbridge") - .enable_dev = enable_dev, -}; diff --git a/src/northbridge/intel/fsp_rangeley/northbridge.h b/src/northbridge/intel/fsp_rangeley/northbridge.h deleted file mode 100644 index fd5fa05a39..0000000000 --- a/src/northbridge/intel/fsp_rangeley/northbridge.h +++ /dev/null @@ -1,69 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007-2008 coresystems GmbH - * Copyright (C) 2011 Google Inc. - * Copyright (C) 2013 Sage Electronic Engineering, LLC. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef __NORTHBRIDGE_INTEL_RANGELEY_NORTHBRIDGE_H__ -#define __NORTHBRIDGE_INTEL_RANGELEY_NORTHBRIDGE_H__ - -#define DEFAULT_ECBASE CONFIG_MMCONF_BASE_ADDRESS - -/* Everything below this line is ignored in the DSDT */ -#ifndef __ACPI__ - -#include - -/* Device 0:0.0 PCI configuration space (Host Bridge) */ - -/* SideBand B-UNIT */ -#define B_UNIT 3 - #define BNOCACHE 0x23 - #define BNOCACHECTL 0x24 - #define BMBOUND 0x25 - #define BMBOUND_HI 0x26 - #define BECREG 0x27 - #define BMISC 0x28 - #define BSMMRRL 0x2E - #define BSMMRRH 0x2F - #define BIMR0L 0x80 - #define BIMR0H 0x81 - #define BIMR0RAC 0x82 - #define BIMR0WAC 0x83 - -/* SideBand C-UNIT */ -#define C_UNIT 8 - -/* SideBand D-UNIT */ -#define D_UNIT 1 - -/* SideBand P-UNIT */ -#define P_UNIT 4 - -#ifndef __ASSEMBLER__ - -#define PCI_DEVICE_ID_RG_MIN 0x1F00 -#define PCI_DEVICE_ID_RG_MAX 0x1F0F -#define SKPAD 0xFC - -int bridge_silicon_revision(void); -void rangeley_late_initialization(void); -u32 sideband_read(int port, int reg); -void sideband_write(int port, int reg, long data); - -void northbridge_acpi_fill_ssdt_generator(struct device *device); - -#endif /* #ifndef __ASSEMBLER__ */ -#endif /* #ifndef __ACPI__ */ -#endif /* __NORTHBRIDGE_INTEL_RANGELEY_NORTHBRIDGE_H__ */ diff --git a/src/northbridge/intel/fsp_rangeley/port_access.c b/src/northbridge/intel/fsp_rangeley/port_access.c deleted file mode 100644 index 75d1bb2b05..0000000000 --- a/src/northbridge/intel/fsp_rangeley/port_access.c +++ /dev/null @@ -1,65 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2009-2010 iWave Systems - * Copyright (C) 2013 Sage Electronic Engineering, LLC. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#define __SIMPLE_DEVICE__ - -#include -#include -#include -#include -#include "northbridge.h" - -/* - * Restricted Access Regions: - * - * MCR - Message Control Register - * 31 24 16 8 4 0 - * ---------------------------------------------------------------------------- - * | | | Target | Write | | - * | Opcode | Port | register | byte | Reserved | - * | | | Address | Enables | | - * ---------------------------------------------------------------------------- - * - * MDR - Message Data Register - * 31 0 - * ---------------------------------------------------------------------------- - * | | - * | Data | - * | | - * ---------------------------------------------------------------------------- - */ - -#define MSG_OPCODE_READ (0x10 << 24) -#define MSG_OPCODE_WRITE (0x11 << 24) - -#define MCR 0xD0 -#define MDR 0xD4 -#define MCRE 0xD8 - -u32 sideband_read(int port, int reg) -{ - pci_write_config32(PCI_DEV(0, 0, 0), MCR, - (MSG_OPCODE_READ | (port << 16) | (reg << 8))); - return pci_read_config32(PCI_DEV(0, 0, 0), MDR); -} - -void sideband_write(int port, int reg, long data) -{ - pci_write_config32(PCI_DEV(0, 0, 0), MDR, data); - pci_write_config32(PCI_DEV(0, 0, 0), MCR, - (MSG_OPCODE_WRITE | (port << 16) | (reg << 8) | (0xF << 4))); - pci_read_config32(PCI_DEV(0, 0, 0), MDR); -} diff --git a/src/southbridge/intel/common/watchdog.c b/src/southbridge/intel/common/watchdog.c index 778a7a9f7f..2eaedab2e8 100644 --- a/src/southbridge/intel/common/watchdog.c +++ b/src/southbridge/intel/common/watchdog.c @@ -37,13 +37,8 @@ void watchdog_off(void) value = pci_read_config16(dev, PCI_COMMAND); - if (CONFIG(SOUTHBRIDGE_INTEL_FSP_RANGELEY)) { - /* Enable I/O space. */ - value |= PCI_COMMAND_IO; - } else { - /* Disable interrupt. */ - value |= PCI_COMMAND_INT_DISABLE; - } + /* Disable interrupt. */ + value |= PCI_COMMAND_INT_DISABLE; pci_write_config16(dev, PCI_COMMAND, value); /* Disable the watchdog timer. */ diff --git a/src/southbridge/intel/fsp_rangeley/Kconfig b/src/southbridge/intel/fsp_rangeley/Kconfig deleted file mode 100644 index 076a2bce55..0000000000 --- a/src/southbridge/intel/fsp_rangeley/Kconfig +++ /dev/null @@ -1,60 +0,0 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2011 Google Inc. -## Copyright (C) 2013-2014 Sage Electronic Engineering, LLC. -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; version 2 of the License. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## - -config SOUTHBRIDGE_INTEL_FSP_RANGELEY - bool - -if SOUTHBRIDGE_INTEL_FSP_RANGELEY - -config SOUTH_BRIDGE_OPTIONS # dummy - def_bool y - select ACPI_INTEL_HARDWARE_SLEEP_VALUES - select IOAPIC - select USE_WATCHDOG_ON_BOOT - select PCIEXP_ASPM - select PCIEXP_COMMON_CLOCK - select SPI_FLASH - select INTEL_DESCRIPTOR_MODE_CAPABLE - select SOUTHBRIDGE_INTEL_COMMON_SMBUS - select SOUTHBRIDGE_INTEL_COMMON_WATCHDOG - select SOUTHBRIDGE_INTEL_COMMON_PMBASE - select SOUTHBRIDGE_INTEL_COMMON_RTC - select SOUTHBRIDGE_INTEL_COMMON_RESET - select SOUTHBRIDGE_INTEL_COMMON_USB_DEBUG - -config EHCI_BAR - hex - default 0xfef00000 - -config SERIRQ_CONTINUOUS_MODE - bool - default n - help - If you set this option to y, the serial IRQ machine will be - operated in continuous mode. - -config HPET_MIN_TICKS - hex - default 0x80 - -config IFD_BIN_PATH - string - depends on HAVE_IFD_BIN - default "../intel/mainboard/intel/rangeley" - help - The path and filename to the descriptor.bin file. - -endif diff --git a/src/southbridge/intel/fsp_rangeley/Makefile.inc b/src/southbridge/intel/fsp_rangeley/Makefile.inc deleted file mode 100644 index 67a51af15a..0000000000 --- a/src/southbridge/intel/fsp_rangeley/Makefile.inc +++ /dev/null @@ -1,33 +0,0 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2010 Google Inc. -## Copyright (C) 2013-2014 Sage Electronic Engineering, LLC. -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; version 2 of the License. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## - -ifeq ($(CONFIG_SOUTHBRIDGE_INTEL_FSP_RANGELEY),y) - -ramstage-y += soc.c -ramstage-y += lpc.c -ramstage-y += sata.c -ramstage-y += spi.c -ramstage-y += smbus.c -ramstage-y += acpi.c - -romstage-y += early_usb.c early_smbus.c gpio.c early_init.c -romstage-y += romstage.c - -bootblock-$(CONFIG_USBDEBUG) += usb_debug.c -romstage-$(CONFIG_USBDEBUG) += usb_debug.c -ramstage-$(CONFIG_USBDEBUG) += usb_debug.c - -endif diff --git a/src/southbridge/intel/fsp_rangeley/acpi.c b/src/southbridge/intel/fsp_rangeley/acpi.c deleted file mode 100644 index 5605d41bc7..0000000000 --- a/src/southbridge/intel/fsp_rangeley/acpi.c +++ /dev/null @@ -1,195 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007-2009 coresystems GmbH - * Copyright (C) 2014 Sage Electronic Engineering, LLC. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include "chip.h" - - -/** - * Fill in the FADT with generic values that can be overridden later. - */ - -typedef struct southbridge_intel_fsp_rangeley_config config_t; - -void acpi_fill_in_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt) -{ - acpi_header_t *header = &(fadt->header); - struct device *lpcdev = pcidev_path_on_root(SOC_LPC_DEVFN); - u16 pmbase = pci_read_config16(lpcdev, ABASE) & 0xfff0; - config_t *config = lpcdev->chip_info; - - memset((void *) fadt, 0, sizeof(acpi_fadt_t)); - - /* - * Reference section 5.2.9 Fixed ACPI Description Table (FADT) - * in the ACPI 3.0b specification. - */ - - /* FADT Header Structure */ - memcpy(header->signature, "FACP", 4); - header->length = sizeof(acpi_fadt_t); - header->revision = get_acpi_table_revision(FADT); - memcpy(header->oem_id, OEM_ID, 6); - memcpy(header->oem_table_id, ACPI_TABLE_CREATOR, 8); - memcpy(header->asl_compiler_id, ASLC, 4); - header->asl_compiler_revision = asl_revision; - - /* ACPI Pointers */ - fadt->firmware_ctrl = (unsigned long) facs; - fadt->dsdt = (unsigned long) dsdt; - - fadt->reserved = 0; /* reserved, should be 0 ACPI 3.0 */ - fadt->preferred_pm_profile = config->fadt_pm_profile; /* unknown is default */ - - /* System Management */ - fadt->sci_int = 0x09; - fadt->smi_cmd = 0x00; /* disable SMM */ - fadt->acpi_enable = 0x00; /* unused if SMI_CMD = 0 */ - fadt->acpi_disable = 0x00; /* unused if SMI_CMD = 0 */ - - /* Enable ACPI */ - outl(inl(pmbase + PM1_CNT) | SCI_EN, pmbase + PM1_CNT); - - /* Power Control */ - fadt->s4bios_req = 0x00; - fadt->pstate_cnt = 0x00; - - /* Control Registers - Base Address */ - fadt->pm1a_evt_blk = pmbase + PM1_STS; - fadt->pm1b_evt_blk = 0x00; /* Not Used */ - fadt->pm1a_cnt_blk = pmbase + PM1_CNT; - fadt->pm1b_cnt_blk = 0x00; /* Not Used */ - fadt->pm2_cnt_blk = pmbase + PM2A_CNT_BLK; - fadt->pm_tmr_blk = pmbase + PM1_TMR; - fadt->gpe0_blk = pmbase + GPE0_STS; - fadt->gpe1_blk = 0x00; /* Not Used */ - - /* Control Registers - Length */ - fadt->pm1_evt_len = 4; /* 32 bits */ - fadt->pm1_cnt_len = 2; /* 32 bit register, 16 bits used */ - fadt->pm2_cnt_len = 1; /* 8 bits */ - fadt->pm_tmr_len = 4; /* 32 bits */ - fadt->gpe0_blk_len = 8; /* 64 bits */ - fadt->gpe1_blk_len = 0; - fadt->gpe1_base = 0; - fadt->cst_cnt = 0; - fadt->p_lvl2_lat = ACPI_FADT_C2_NOT_SUPPORTED; - fadt->p_lvl3_lat = ACPI_FADT_C3_NOT_SUPPORTED; - fadt->flush_size = 0; /* set to 0 if WBINVD is 1 in flags */ - fadt->flush_stride = 0; /* set to 0 if WBINVD is 1 in flags */ - fadt->duty_offset = 1; - fadt->duty_width = 0; - - /* RTC Registers */ - fadt->day_alrm = 0x0D; - fadt->mon_alrm = 0x00; - fadt->century = 0x00; - fadt->iapc_boot_arch = config->fadt_boot_arch; /* legacy free default */ - - fadt->flags = ACPI_FADT_WBINVD | ACPI_FADT_C1_SUPPORTED | - ACPI_FADT_C2_MP_SUPPORTED | ACPI_FADT_SLEEP_BUTTON | - ACPI_FADT_RESET_REGISTER | ACPI_FADT_SLEEP_TYPE | - ACPI_FADT_S4_RTC_WAKE | ACPI_FADT_PLATFORM_CLOCK; - - /* Reset Register */ - fadt->reset_reg.space_id = ACPI_ADDRESS_SPACE_IO; - fadt->reset_reg.bit_width = 8; - fadt->reset_reg.bit_offset = 0; - fadt->reset_reg.access_size = ACPI_ACCESS_SIZE_BYTE_ACCESS; - fadt->reset_reg.addrl = 0xCF9; - fadt->reset_reg.addrh = 0x00; - fadt->reset_value = 6; - - fadt->ARM_boot_arch = 0; /* MUST be 0 ACPI 3.0 */ - fadt->FADT_MinorVersion = 0; /* MUST be 0 ACPI 3.0 */ - - /* Extended ACPI Pointers */ - fadt->x_firmware_ctl_l = (unsigned long)facs; - fadt->x_firmware_ctl_h = 0x00; - fadt->x_dsdt_l = (unsigned long)dsdt; - fadt->x_dsdt_h = 0x00; - - /* PM1 Status & PM1 Enable */ - fadt->x_pm1a_evt_blk.space_id = ACPI_ADDRESS_SPACE_IO; - fadt->x_pm1a_evt_blk.bit_width = 32; - fadt->x_pm1a_evt_blk.bit_offset = 0; - fadt->x_pm1a_evt_blk.access_size = ACPI_ACCESS_SIZE_DWORD_ACCESS; - fadt->x_pm1a_evt_blk.addrl = fadt->pm1a_evt_blk; - fadt->x_pm1a_evt_blk.addrh = 0x00; - - fadt->x_pm1b_evt_blk.space_id = ACPI_ADDRESS_SPACE_IO; - fadt->x_pm1b_evt_blk.bit_width = 0; - fadt->x_pm1b_evt_blk.bit_offset = 0; - fadt->x_pm1b_evt_blk.access_size = 0; - fadt->x_pm1b_evt_blk.addrl = fadt->pm1b_evt_blk; - fadt->x_pm1b_evt_blk.addrh = 0x00; - - /* PM1 Control Registers */ - fadt->x_pm1a_cnt_blk.space_id = ACPI_ADDRESS_SPACE_IO; - fadt->x_pm1a_cnt_blk.bit_width = 16; - fadt->x_pm1a_cnt_blk.bit_offset = 0; - fadt->x_pm1a_cnt_blk.access_size = ACPI_ACCESS_SIZE_WORD_ACCESS; - fadt->x_pm1a_cnt_blk.addrl = fadt->pm1a_cnt_blk; - fadt->x_pm1a_cnt_blk.addrh = 0x00; - - fadt->x_pm1b_cnt_blk.space_id = ACPI_ADDRESS_SPACE_IO; - fadt->x_pm1b_cnt_blk.bit_width = 0; - fadt->x_pm1b_cnt_blk.bit_offset = 0; - fadt->x_pm1b_cnt_blk.access_size = 0; - fadt->x_pm1b_cnt_blk.addrl = fadt->pm1b_cnt_blk; - fadt->x_pm1b_cnt_blk.addrh = 0x00; - - /* PM2 Control Registers */ - fadt->x_pm2_cnt_blk.space_id = ACPI_ADDRESS_SPACE_IO; - fadt->x_pm2_cnt_blk.bit_width = 8; - fadt->x_pm2_cnt_blk.bit_offset = 0; - fadt->x_pm2_cnt_blk.access_size = ACPI_ACCESS_SIZE_BYTE_ACCESS; - fadt->x_pm2_cnt_blk.addrl = fadt->pm2_cnt_blk; - fadt->x_pm2_cnt_blk.addrh = 0x00; - - /* PM1 Timer Register */ - fadt->x_pm_tmr_blk.space_id = ACPI_ADDRESS_SPACE_IO; - fadt->x_pm_tmr_blk.bit_width = 32; - fadt->x_pm_tmr_blk.bit_offset = 0; - fadt->x_pm_tmr_blk.access_size = ACPI_ACCESS_SIZE_DWORD_ACCESS; - fadt->x_pm_tmr_blk.addrl = fadt->pm_tmr_blk; - fadt->x_pm_tmr_blk.addrh = 0x00; - - /* General-Purpose Event Registers */ - fadt->x_gpe0_blk.space_id = ACPI_ADDRESS_SPACE_IO; - fadt->x_gpe0_blk.bit_width = 64; /* EventStatus + EventEnable */ - fadt->x_gpe0_blk.bit_offset = 0; - fadt->x_gpe0_blk.access_size = ACPI_ACCESS_SIZE_DWORD_ACCESS; - fadt->x_gpe0_blk.addrl = fadt->gpe0_blk; - fadt->x_gpe0_blk.addrh = 0x00; - - fadt->x_gpe1_blk.space_id = ACPI_ADDRESS_SPACE_IO; - fadt->x_gpe1_blk.bit_width = 0; - fadt->x_gpe1_blk.bit_offset = 0; - fadt->x_gpe1_blk.access_size = 0; - fadt->x_gpe1_blk.addrl = fadt->gpe1_blk; - fadt->x_gpe1_blk.addrh = 0x00; - - header->checksum = - acpi_checksum((void *) fadt, sizeof(acpi_fadt_t)); -} diff --git a/src/southbridge/intel/fsp_rangeley/acpi/globalnvs.asl b/src/southbridge/intel/fsp_rangeley/acpi/globalnvs.asl deleted file mode 100644 index 2c47fe58c2..0000000000 --- a/src/southbridge/intel/fsp_rangeley/acpi/globalnvs.asl +++ /dev/null @@ -1,181 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007-2009 coresystems GmbH - * Copyright (C) 2012 The Chromium OS Authors - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -/* Global Variables */ - -Name(\PICM, 0) // IOAPIC/8259 -Name(\DSEN, 1) // Display Output Switching Enable - -/* Global ACPI memory region. This region is used for passing information - * between coreboot (aka "the system bios"), ACPI, and the SMI handler. - * Since we don't know where this will end up in memory at ACPI compile time, - * we have to fix it up in coreboot's ACPI creation phase. - */ - - -External(NVSA) -OperationRegion (GNVS, SystemMemory, NVSA, 0xf00) -Field (GNVS, ByteAcc, NoLock, Preserve) -{ - /* Miscellaneous */ - Offset (0x00), - OSYS, 16, // 0x00 - Operating System - SMIF, 8, // 0x02 - SMI function - PRM0, 8, // 0x03 - SMI function parameter - PRM1, 8, // 0x04 - SMI function parameter - SCIF, 8, // 0x05 - SCI function - PRM2, 8, // 0x06 - SCI function parameter - PRM3, 8, // 0x07 - SCI function parameter - LCKF, 8, // 0x08 - Global Lock function for EC - PRM4, 8, // 0x09 - Lock function parameter - PRM5, 8, // 0x0a - Lock function parameter - P80D, 32, // 0x0b - Debug port (IO 0x80) value - LIDS, 8, // 0x0f - LID state (open = 1) - PWRS, 8, // 0x10 - Power State (AC = 1) - /* Processor Identification */ - Offset (0x28), - APIC, 8, // 0x28 - APIC Enabled by coreboot - MPEN, 8, // 0x29 - Multi Processor Enable - PCP0, 8, // 0x2a - PDC CPU/CORE 0 - PCP1, 8, // 0x2b - PDC CPU/CORE 1 - PPCM, 8, // 0x2c - Max. PPC state - PCNT, 8, // 0x2d - Processor count - /* Super I/O & CMOS config */ - Offset (0x32), - NATP, 8, // 0x32 - - S5U0, 8, // 0x33 - Enable USB0 in S5 - S5U1, 8, // 0x34 - Enable USB1 in S5 - S3U0, 8, // 0x35 - Enable USB0 in S3 - S3U1, 8, // 0x36 - Enable USB1 in S3 - S33G, 8, // 0x37 - Enable 3G in S3 - CMEM, 32, // 0x38 - CBMEM TOC - /* Integrated Graphics Device */ - Offset (0x3c), - IGDS, 8, // 0x3c - IGD state (primary = 1) - TLST, 8, // 0x3d - Display Toggle List pointer - CADL, 8, // 0x3e - Currently Attached Devices List - PADL, 8, // 0x3f - Previously Attached Devices List - CSTE, 16, // 0x40 - Current display state - NSTE, 16, // 0x42 - Next display state - SSTE, 16, // 0x44 - Set display state - Offset (0x46), - NDID, 8, // 0x46 - Number of Device IDs - DID1, 32, // 0x47 - Device ID 1 - DID2, 32, // 0x4b - Device ID 2 - DID3, 32, // 0x4f - Device ID 3 - DID4, 32, // 0x53 - Device ID 4 - DID5, 32, // 0x57 - Device ID 5 - /* Backlight Control */ - Offset (0x64), - BLCS, 8, // 0x64 - Backlight control possible? - BRTL, 8, // 0x65 - Brightness Level - ODDS, 8, // 0x66 - /* Ambient Light Sensors */ - Offset (0x6e), - ALSE, 8, // 0x6e - ALS enable - ALAF, 8, // 0x6f - Ambient light adjustment factor - LLOW, 8, // 0x70 - LUX Low - LHIH, 8, // 0x71 - LUX High - /* EMA */ - Offset (0x78), - EMAE, 8, // 0x78 - EMA enable - EMAP, 16, // 0x79 - EMA pointer - EMAL, 16, // 0x7b - EMA length - /* MEF */ - Offset (0x82), - MEFE, 8, // 0x82 - MEF enable - /* TPM support */ - Offset (0x8c), - TPMP, 8, // 0x8c - TPM - TPME, 8, // 0x8d - TPM enable - /* SATA */ - Offset (0x96), - GTF0, 56, // 0x96 - GTF task file buffer for port 0 - GTF1, 56, // 0x9d - GTF task file buffer for port 1 - GTF2, 56, // 0xa4 - GTF task file buffer for port 2 - IDEM, 8, // 0xab - IDE mode (compatible / enhanced) - IDET, 8, // 0xac - IDE - /* IGD OpRegion */ - Offset (0xb4), - ASLB, 32, // 0xb4 - IGD OpRegion Base Address - IBTT, 8, // 0xb8 - IGD boot panel device - IPAT, 8, // 0xb9 - IGD panel type cmos option - ITVF, 8, // 0xba - IGD TV format cmos option - ITVM, 8, // 0xbb - IGD TV minor format option - IPSC, 8, // 0xbc - IGD panel scaling - IBLC, 8, // 0xbd - IGD BLC config - IBIA, 8, // 0xbe - IGD BIA config - ISSC, 8, // 0xbf - IGD SSC config - I409, 8, // 0xc0 - IGD 0409 modified settings - I509, 8, // 0xc1 - IGD 0509 modified settings - I609, 8, // 0xc2 - IGD 0609 modified settings - I709, 8, // 0xc3 - IGD 0709 modified settings - IDMM, 8, // 0xc4 - IGD Power conservation feature - IDMS, 8, // 0xc5 - IGD DVMT memory size - IF1E, 8, // 0xc6 - IGD function 1 enable - HVCO, 8, // 0xc7 - IGD HPLL VCO - NXD1, 32, // 0xc8 - IGD _DGS next DID1 - NXD2, 32, // 0xcc - IGD _DGS next DID2 - NXD3, 32, // 0xd0 - IGD _DGS next DID3 - NXD4, 32, // 0xd4 - IGD _DGS next DID4 - NXD5, 32, // 0xd8 - IGD _DGS next DID5 - NXD6, 32, // 0xdc - IGD _DGS next DID6 - NXD7, 32, // 0xe0 - IGD _DGS next DID7 - NXD8, 32, // 0xe4 - IGD _DGS next DID8 - - ISCI, 8, // 0xe8 - IGD SMI/SCI mode (0: SCI) - PAVP, 8, // 0xe9 - IGD PAVP data - Offset (0xeb), - OSCC, 8, // 0xeb - PCIe OSC control - NPCE, 8, // 0xec - native pcie support - PLFL, 8, // 0xed - platform flavor - BREV, 8, // 0xee - board revision - DPBM, 8, // 0xef - digital port b mode - DPCM, 8, // 0xf0 - digital port c mode - DPDM, 8, // 0xf1 - digital port d mode - ALFP, 8, // 0xf2 - active lfp - IMON, 8, // 0xf3 - current graphics turbo imon value - MMIO, 8, // 0xf4 - 64bit mmio support -} - -/* Set flag to enable USB charging in S3 */ -Method (S3UE) -{ - Store (One, \S3U0) - Store (One, \S3U1) -} - -/* Set flag to disable USB charging in S3 */ -Method (S3UD) -{ - Store (Zero, \S3U0) - Store (Zero, \S3U1) -} - -/* Set flag to enable USB charging in S5 */ -Method (S5UE) -{ - Store (One, \S5U0) - Store (One, \S5U1) -} - -/* Set flag to disable USB charging in S5 */ -Method (S5UD) -{ - Store (Zero, \S5U0) - Store (Zero, \S5U1) -} diff --git a/src/southbridge/intel/fsp_rangeley/acpi/irq_helper.h b/src/southbridge/intel/fsp_rangeley/acpi/irq_helper.h deleted file mode 100644 index 904f4360c3..0000000000 --- a/src/southbridge/intel/fsp_rangeley/acpi/irq_helper.h +++ /dev/null @@ -1,57 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2013 Google Inc. - * Copyright (C) 2014 Sage Electronics Engineering, LLC. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -/* - * This file intentionally gets included multiple times, to set pic and apic - * modes, so should not have guard statements added. - */ - -/* - * This file will use irqroute.asl and mainboard/irqroute.h - * to generate the ACPI IRQ routing for the mainboard being compiled. - * This method uses #defines in irqroute.h along with the macros contained - * in this file to generate an IRQ routing for each PCI device in the system. - */ -#undef PCI_DEV_PIRQ_ROUTES -#undef ACPI_DEV_IRQ -#undef PCI_DEV_PIRQ_ROUTE -#undef PIRQ_PIC_ROUTES -#undef PIRQ_PIC -#undef IRQROUTE_H - -#if defined(PIC_MODE) - -#define ACPI_DEV_IRQ(dev_, pin_, pin_name_) \ - Package() { ## dev_ ## ffff, pin_, \_SB.PCI0.LPCB.LNK ## pin_name_, 0 } - -#else /* defined(PIC_MODE) */ - -#define ACPI_DEV_IRQ(dev_, pin_, pin_name_) \ - Package() { ## dev_ ## ffff, pin_, 0, PIRQ ## pin_name_ ## _APIC_IRQ } - -#endif - -#define PCI_DEV_PIRQ_ROUTE(dev_, a_, b_, c_, d_) \ - ACPI_DEV_IRQ(dev_, 0, a_), \ - ACPI_DEV_IRQ(dev_, 1, b_), \ - ACPI_DEV_IRQ(dev_, 2, c_), \ - ACPI_DEV_IRQ(dev_, 3, d_) - -/* Empty PIRQ_PIC definition. */ -#define PIRQ_PIC(pirq_, pic_irq_) - -/* Include the mainboard irq route definition */ -#include "irqroute.h" diff --git a/src/southbridge/intel/fsp_rangeley/acpi/irqlinks.asl b/src/southbridge/intel/fsp_rangeley/acpi/irqlinks.asl deleted file mode 100644 index 2d029242d8..0000000000 --- a/src/southbridge/intel/fsp_rangeley/acpi/irqlinks.asl +++ /dev/null @@ -1,487 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007-2009 coresystems GmbH - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -Device (LNKA) -{ - Name (_HID, EISAID("PNP0C0F")) - Name (_UID, 1) - - // Disable method - Method (_DIS, 0, Serialized) - { - Store (0x80, PRTA) - } - - // Possible Resource Settings for this Link - Name (_PRS, ResourceTemplate() - { - IRQ(Level, ActiveLow, Shared) - { 3, 4, 5, 6, 7, 10, 12, 14, 15 } - }) - - // Current Resource Settings for this link - Method (_CRS, 0, Serialized) - { - Name (RTLA, ResourceTemplate() - { - IRQ(Level, ActiveLow, Shared) {} - }) - CreateWordField(RTLA, 1, IRQ0) - - // Clear the WordField - Store (Zero, IRQ0) - - // Set the bit from PRTA - ShiftLeft(1, And(PRTA, 0x0f), IRQ0) - - Return (RTLA) - } - - // Set Resource Setting for this IRQ link - Method (_SRS, 1, Serialized) - { - CreateWordField(Arg0, 1, IRQ0) - - // Which bit is set? - FindSetRightBit(IRQ0, Local0) - - Decrement(Local0) - Store(Local0, PRTA) - } - - // Status - Method (_STA, 0, Serialized) - { - If(And(PRTA, 0x80)) { - Return (0x9) - } Else { - Return (0xb) - } - } -} - -Device (LNKB) -{ - Name (_HID, EISAID("PNP0C0F")) - Name (_UID, 2) - - // Disable method - Method (_DIS, 0, Serialized) - { - Store (0x80, PRTB) - } - - // Possible Resource Settings for this Link - Name (_PRS, ResourceTemplate() - { - IRQ(Level, ActiveLow, Shared) - { 3, 4, 5, 6, 7, 11, 12, 14, 15 } - }) - - // Current Resource Settings for this link - Method (_CRS, 0, Serialized) - { - Name (RTLB, ResourceTemplate() - { - IRQ(Level, ActiveLow, Shared) {} - }) - CreateWordField(RTLB, 1, IRQ0) - - // Clear the WordField - Store (Zero, IRQ0) - - // Set the bit from PRTB - ShiftLeft(1, And(PRTB, 0x0f), IRQ0) - - Return (RTLB) - } - - // Set Resource Setting for this IRQ link - Method (_SRS, 1, Serialized) - { - CreateWordField(Arg0, 1, IRQ0) - - // Which bit is set? - FindSetRightBit(IRQ0, Local0) - - Decrement(Local0) - Store(Local0, PRTB) - } - - // Status - Method (_STA, 0, Serialized) - { - If(And(PRTB, 0x80)) { - Return (0x9) - } Else { - Return (0xb) - } - } -} - -Device (LNKC) -{ - Name (_HID, EISAID("PNP0C0F")) - Name (_UID, 3) - - // Disable method - Method (_DIS, 0, Serialized) - { - Store (0x80, PRTC) - } - - // Possible Resource Settings for this Link - Name (_PRS, ResourceTemplate() - { - IRQ(Level, ActiveLow, Shared) - { 3, 4, 5, 6, 7, 10, 12, 14, 15 } - }) - - // Current Resource Settings for this link - Method (_CRS, 0, Serialized) - { - Name (RTLC, ResourceTemplate() - { - IRQ(Level, ActiveLow, Shared) {} - }) - CreateWordField(RTLC, 1, IRQ0) - - // Clear the WordField - Store (Zero, IRQ0) - - // Set the bit from PRTC - ShiftLeft(1, And(PRTC, 0x0f), IRQ0) - - Return (RTLC) - } - - // Set Resource Setting for this IRQ link - Method (_SRS, 1, Serialized) - { - CreateWordField(Arg0, 1, IRQ0) - - // Which bit is set? - FindSetRightBit(IRQ0, Local0) - - Decrement(Local0) - Store(Local0, PRTC) - } - - // Status - Method (_STA, 0, Serialized) - { - If(And(PRTC, 0x80)) { - Return (0x9) - } Else { - Return (0xb) - } - } -} - -Device (LNKD) -{ - Name (_HID, EISAID("PNP0C0F")) - Name (_UID, 4) - - // Disable method - Method (_DIS, 0, Serialized) - { - Store (0x80, PRTD) - } - - // Possible Resource Settings for this Link - Name (_PRS, ResourceTemplate() - { - IRQ(Level, ActiveLow, Shared) - { 3, 4, 5, 6, 7, 11, 12, 14, 15 } - }) - - // Current Resource Settings for this link - Method (_CRS, 0, Serialized) - { - Name (RTLD, ResourceTemplate() - { - IRQ(Level, ActiveLow, Shared) {} - }) - CreateWordField(RTLD, 1, IRQ0) - - // Clear the WordField - Store (Zero, IRQ0) - - // Set the bit from PRTD - ShiftLeft(1, And(PRTD, 0x0f), IRQ0) - - Return (RTLD) - } - - // Set Resource Setting for this IRQ link - Method (_SRS, 1, Serialized) - { - CreateWordField(Arg0, 1, IRQ0) - - // Which bit is set? - FindSetRightBit(IRQ0, Local0) - - Decrement(Local0) - Store(Local0, PRTD) - } - - // Status - Method (_STA, 0, Serialized) - { - If(And(PRTD, 0x80)) { - Return (0x9) - } Else { - Return (0xb) - } - } -} - -Device (LNKE) -{ - Name (_HID, EISAID("PNP0C0F")) - Name (_UID, 5) - - // Disable method - Method (_DIS, 0, Serialized) - { - Store (0x80, PRTE) - } - - // Possible Resource Settings for this Link - Name (_PRS, ResourceTemplate() - { - IRQ(Level, ActiveLow, Shared) - { 3, 4, 5, 6, 7, 10, 12, 14, 15 } - }) - - // Current Resource Settings for this link - Method (_CRS, 0, Serialized) - { - Name (RTLE, ResourceTemplate() - { - IRQ(Level, ActiveLow, Shared) {} - }) - CreateWordField(RTLE, 1, IRQ0) - - // Clear the WordField - Store (Zero, IRQ0) - - // Set the bit from PRTE - ShiftLeft(1, And(PRTE, 0x0f), IRQ0) - - Return (RTLE) - } - - // Set Resource Setting for this IRQ link - Method (_SRS, 1, Serialized) - { - CreateWordField(Arg0, 1, IRQ0) - - // Which bit is set? - FindSetRightBit(IRQ0, Local0) - - Decrement(Local0) - Store(Local0, PRTE) - } - - // Status - Method (_STA, 0, Serialized) - { - If(And(PRTE, 0x80)) { - Return (0x9) - } Else { - Return (0xb) - } - } -} - -Device (LNKF) -{ - Name (_HID, EISAID("PNP0C0F")) - Name (_UID, 6) - - // Disable method - Method (_DIS, 0, Serialized) - { - Store (0x80, PRTF) - } - - // Possible Resource Settings for this Link - Name (_PRS, ResourceTemplate() - { - IRQ(Level, ActiveLow, Shared) - { 3, 4, 5, 6, 7, 11, 12, 14, 15 } - }) - - // Current Resource Settings for this link - Method (_CRS, 0, Serialized) - { - Name (RTLF, ResourceTemplate() - { - IRQ(Level, ActiveLow, Shared) {} - }) - CreateWordField(RTLF, 1, IRQ0) - - // Clear the WordField - Store (Zero, IRQ0) - - // Set the bit from PRTF - ShiftLeft(1, And(PRTF, 0x0f), IRQ0) - - Return (RTLF) - } - - // Set Resource Setting for this IRQ link - Method (_SRS, 1, Serialized) - { - CreateWordField(Arg0, 1, IRQ0) - - // Which bit is set? - FindSetRightBit(IRQ0, Local0) - - Decrement(Local0) - Store(Local0, PRTF) - } - - // Status - Method (_STA, 0, Serialized) - { - If(And(PRTF, 0x80)) { - Return (0x9) - } Else { - Return (0xb) - } - } -} - -Device (LNKG) -{ - Name (_HID, EISAID("PNP0C0F")) - Name (_UID, 7) - - // Disable method - Method (_DIS, 0, Serialized) - { - Store (0x80, PRTG) - } - - // Possible Resource Settings for this Link - Name (_PRS, ResourceTemplate() - { - IRQ(Level, ActiveLow, Shared) - { 3, 4, 5, 6, 7, 10, 12, 14, 15 } - }) - - // Current Resource Settings for this link - Method (_CRS, 0, Serialized) - { - Name (RTLG, ResourceTemplate() - { - IRQ(Level, ActiveLow, Shared) {} - }) - CreateWordField(RTLG, 1, IRQ0) - - // Clear the WordField - Store (Zero, IRQ0) - - // Set the bit from PRTG - ShiftLeft(1, And(PRTG, 0x0f), IRQ0) - - Return (RTLG) - } - - // Set Resource Setting for this IRQ link - Method (_SRS, 1, Serialized) - { - CreateWordField(Arg0, 1, IRQ0) - - // Which bit is set? - FindSetRightBit(IRQ0, Local0) - - Decrement(Local0) - Store(Local0, PRTG) - } - - // Status - Method (_STA, 0, Serialized) - { - If(And(PRTG, 0x80)) { - Return (0x9) - } Else { - Return (0xb) - } - } -} - -Device (LNKH) -{ - Name (_HID, EISAID("PNP0C0F")) - Name (_UID, 8) - - // Disable method - Method (_DIS, 0, Serialized) - { - Store (0x80, PRTH) - } - - // Possible Resource Settings for this Link - Name (_PRS, ResourceTemplate() - { - IRQ(Level, ActiveLow, Shared) - { 3, 4, 5, 6, 7, 11, 12, 14, 15 } - }) - - // Current Resource Settings for this link - Method (_CRS, 0, Serialized) - { - Name (RTLH, ResourceTemplate() - { - IRQ(Level, ActiveLow, Shared) {} - }) - CreateWordField(RTLH, 1, IRQ0) - - // Clear the WordField - Store (Zero, IRQ0) - - // Set the bit from PRTH - ShiftLeft(1, And(PRTH, 0x0f), IRQ0) - - Return (RTLH) - } - - // Set Resource Setting for this IRQ link - Method (_SRS, 1, Serialized) - { - CreateWordField(Arg0, 1, IRQ0) - - // Which bit is set? - FindSetRightBit(IRQ0, Local0) - - Decrement(Local0) - Store(Local0, PRTH) - } - - // Status - Method (_STA, 0, Serialized) - { - If(And(PRTH, 0x80)) { - Return (0x9) - } Else { - Return (0xb) - } - } -} diff --git a/src/southbridge/intel/fsp_rangeley/acpi/irqroute.asl b/src/southbridge/intel/fsp_rangeley/acpi/irqroute.asl deleted file mode 100644 index b523a7632f..0000000000 --- a/src/southbridge/intel/fsp_rangeley/acpi/irqroute.asl +++ /dev/null @@ -1,39 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007-2009 coresystems GmbH - * Copyright (C) 2013 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -// PCI Interrupt Routing -Method(_PRT) -{ - /* - * PICM comes from _PIC, which returns the following: - * 0 - PIC mode - * 1 - APIC mode - * 2 - SAPIC mode - */ - If (PICM) { - Return (Package() { - #undef PIC_MODE - #include "irq_helper.h" - PCI_DEV_PIRQ_ROUTES - }) - } Else { - Return (Package() { - #define PIC_MODE - #include "irq_helper.h" - PCI_DEV_PIRQ_ROUTES - }) - } -} diff --git a/src/southbridge/intel/fsp_rangeley/acpi/lpc.asl b/src/southbridge/intel/fsp_rangeley/acpi/lpc.asl deleted file mode 100644 index a896dadc98..0000000000 --- a/src/southbridge/intel/fsp_rangeley/acpi/lpc.asl +++ /dev/null @@ -1,226 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007-2009 coresystems GmbH - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -// Intel LPC Bus Device - 0:1f.0 - -Device (LPCB) -{ - Name(_ADR, 0x001f0000) - - OperationRegion(LPC0, PCI_Config, 0x00, 0x100) - Field (LPC0, AnyAcc, NoLock, Preserve) - { - Offset (0x40), - PMBS, 16, // ABASE - Offset (0x60), // Interrupt Routing Registers - PRTA, 8, - PRTB, 8, - PRTC, 8, - PRTD, 8, - Offset (0x68), - PRTE, 8, - PRTF, 8, - PRTG, 8, - PRTH, 8, - - Offset (0x80), // IO Decode Ranges - IOD0, 8, - IOD1, 8, - - Offset (0xb8), // GPIO Routing Control - GR00, 2, - GR01, 2, - GR02, 2, - GR03, 2, - GR04, 2, - GR05, 2, - GR06, 2, - GR07, 2, - GR08, 2, - GR09, 2, - GR10, 2, - GR11, 2, - GR12, 2, - GR13, 2, - GR14, 2, - GR15, 2, - - Offset (0xf0), // RCBA - RCEN, 1, - , 13, - RCBA, 18, - } - - #include "irqlinks.asl" - - #include "acpi/ec.asl" - - Device (DMAC) // DMA Controller - { - Name(_HID, EISAID("PNP0200")) - Name(_CRS, ResourceTemplate() - { - IO (Decode16, 0x00, 0x00, 0x01, 0x20) - IO (Decode16, 0x81, 0x81, 0x01, 0x11) - IO (Decode16, 0x93, 0x93, 0x01, 0x0d) - IO (Decode16, 0xc0, 0xc0, 0x01, 0x20) - DMA (Compatibility, NotBusMaster, Transfer8_16) { 4 } - }) - } - - Device (FWH) // Firmware Hub - { - Name (_HID, EISAID("INT0800")) - Name (_CRS, ResourceTemplate() - { - Memory32Fixed(ReadOnly, 0xff000000, 0x01000000) - }) - } - - Device (HPET) - { - Name (_HID, EISAID("PNP0103")) - Name (_CID, 0x010CD041) - - Name(BUF0, ResourceTemplate() - { - Memory32Fixed(ReadOnly, CONFIG_HPET_ADDRESS, 0x400, FED0) - }) - - Method (_STA, 0) // Device Status - { - If (HPTE) { - // Note: Ancient versions of Windows don't want - // to see the HPET in order to work right - If (LGreaterEqual(OSYS, 2001)) { - Return (0xf) // Enable and show device - } Else { - Return (0xb) // Enable and don't show device - } - } - - Return (0x0) // Not enabled, don't show. - } - - Method (_CRS, 0, Serialized) // Current resources - { - If (HPTE) { - CreateDWordField(BUF0, \_SB.PCI0.LPCB.HPET.FED0._BAS, HPT0) - If (Lequal(HPAS, 1)) { - Add(CONFIG_HPET_ADDRESS, 0x1000, HPT0) - } - - If (Lequal(HPAS, 2)) { - Add(CONFIG_HPET_ADDRESS, 0x2000, HPT0) - } - - If (Lequal(HPAS, 3)) { - Add(CONFIG_HPET_ADDRESS, 0x3000, HPT0) - } - } - - Return (BUF0) - } - } - - Device(PIC) // 8259 Interrupt Controller - { - Name(_HID,EISAID("PNP0000")) - Name(_CRS, ResourceTemplate() - { - IO (Decode16, 0x20, 0x20, 0x01, 0x02) - IO (Decode16, 0x24, 0x24, 0x01, 0x02) - IO (Decode16, 0x28, 0x28, 0x01, 0x02) - IO (Decode16, 0x2c, 0x2c, 0x01, 0x02) - IO (Decode16, 0x30, 0x30, 0x01, 0x02) - IO (Decode16, 0x34, 0x34, 0x01, 0x02) - IO (Decode16, 0x38, 0x38, 0x01, 0x02) - IO (Decode16, 0x3c, 0x3c, 0x01, 0x02) - IO (Decode16, 0xa0, 0xa0, 0x01, 0x02) - IO (Decode16, 0xa4, 0xa4, 0x01, 0x02) - IO (Decode16, 0xa8, 0xa8, 0x01, 0x02) - IO (Decode16, 0xac, 0xac, 0x01, 0x02) - IO (Decode16, 0xb0, 0xb0, 0x01, 0x02) - IO (Decode16, 0xb4, 0xb4, 0x01, 0x02) - IO (Decode16, 0xb8, 0xb8, 0x01, 0x02) - IO (Decode16, 0xbc, 0xbc, 0x01, 0x02) - IO (Decode16, 0x4d0, 0x4d0, 0x01, 0x02) - IRQNoFlags () { 2 } - }) - } - - Device(MATH) // FPU - { - Name (_HID, EISAID("PNP0C04")) - Name (_CRS, ResourceTemplate() - { - IO (Decode16, 0xf0, 0xf0, 0x01, 0x01) - IRQNoFlags() { 13 } - }) - } - - Device(LDRC) // LPC device: Resource consumption - { - Name (_HID, EISAID("PNP0C02")) - Name (_UID, 2) - - Name (RBUF, ResourceTemplate() - { - IO (Decode16, 0x2e, 0x2e, 0x1, 0x02) // First SuperIO - IO (Decode16, 0x4e, 0x4e, 0x1, 0x02) // Second SuperIO - IO (Decode16, 0x61, 0x61, 0x1, 0x01) // NMI Status - IO (Decode16, 0x63, 0x63, 0x1, 0x01) // CPU Reserved - IO (Decode16, 0x65, 0x65, 0x1, 0x01) // CPU Reserved - IO (Decode16, 0x67, 0x67, 0x1, 0x01) // CPU Reserved - IO (Decode16, 0x80, 0x80, 0x1, 0x01) // Port 80 Post - IO (Decode16, 0x92, 0x92, 0x1, 0x01) // CPU Reserved - IO (Decode16, 0xb2, 0xb2, 0x1, 0x02) // SWSMI - //IO (Decode16, 0x800, 0x800, 0x1, 0x10) // ACPI I/O trap - IO (Decode16, DEFAULT_ABASE, DEFAULT_ABASE, 0x1, 0x80) // ICH7-M ACPI - IO (Decode16, DEFAULT_GPIOBASE, DEFAULT_GPIOBASE, 0x1, 0x40) // ICH7-M GPIO - }) - - Method (_CRS, 0, NotSerialized) - { - Return (RBUF) - } - } - - Device (RTC) // Real Time Clock - { - Name (_HID, EISAID("PNP0B00")) - Name (_CRS, ResourceTemplate() - { - IO (Decode16, 0x70, 0x70, 1, 8) -// Disable as Windows doesn't like it, and systems don't seem to use it. -// IRQNoFlags() { 8 } - }) - } - - Device (TIMR) // Intel 8254 timer - { - Name(_HID, EISAID("PNP0100")) - Name(_CRS, ResourceTemplate() - { - IO (Decode16, 0x40, 0x40, 0x01, 0x04) - IO (Decode16, 0x50, 0x50, 0x10, 0x04) - IRQNoFlags() {0} - }) - } - - // Include mainboard's superio.asl file. - #include "acpi/superio.asl" -} diff --git a/src/southbridge/intel/fsp_rangeley/acpi/pcie.asl b/src/southbridge/intel/fsp_rangeley/acpi/pcie.asl deleted file mode 100644 index bc236b8d8f..0000000000 --- a/src/southbridge/intel/fsp_rangeley/acpi/pcie.asl +++ /dev/null @@ -1,165 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007-2009 coresystems GmbH - * Copyright (C) 2012 The Chromium OS Authors. All Rights Reserved. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -/* Intel 6/7 Series PCH PCIe support */ - -// PCI Express Ports - -Method (IRQM, 1, Serialized) { - - /* Interrupt Map INTA->INTA, INTB->INTB, INTC->INTC, INTD->INTD */ - Name (IQAA, Package() { - Package() { 0x0000ffff, 0, 0, 16 }, - Package() { 0x0000ffff, 1, 0, 17 }, - Package() { 0x0000ffff, 2, 0, 18 }, - Package() { 0x0000ffff, 3, 0, 19 } }) - Name (IQAP, Package() { - Package() { 0x0000ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 }, - Package() { 0x0000ffff, 1, \_SB.PCI0.LPCB.LNKB, 0 }, - Package() { 0x0000ffff, 2, \_SB.PCI0.LPCB.LNKC, 0 }, - Package() { 0x0000ffff, 3, \_SB.PCI0.LPCB.LNKD, 0 } }) - - /* Interrupt Map INTA->INTB, INTB->INTC, INTC->INTD, INTD->INTA */ - Name (IQBA, Package() { - Package() { 0x0000ffff, 0, 0, 17 }, - Package() { 0x0000ffff, 1, 0, 18 }, - Package() { 0x0000ffff, 2, 0, 19 }, - Package() { 0x0000ffff, 3, 0, 16 } }) - Name (IQBP, Package() { - Package() { 0x0000ffff, 0, \_SB.PCI0.LPCB.LNKB, 0 }, - Package() { 0x0000ffff, 1, \_SB.PCI0.LPCB.LNKC, 0 }, - Package() { 0x0000ffff, 2, \_SB.PCI0.LPCB.LNKD, 0 }, - Package() { 0x0000ffff, 3, \_SB.PCI0.LPCB.LNKA, 0 } }) - - /* Interrupt Map INTA->INTC, INTB->INTD, INTC->INTA, INTD->INTB */ - Name (IQCA, Package() { - Package() { 0x0000ffff, 0, 0, 18 }, - Package() { 0x0000ffff, 1, 0, 19 }, - Package() { 0x0000ffff, 2, 0, 16 }, - Package() { 0x0000ffff, 3, 0, 17 } }) - Name (IQCP, Package() { - Package() { 0x0000ffff, 0, \_SB.PCI0.LPCB.LNKC, 0 }, - Package() { 0x0000ffff, 1, \_SB.PCI0.LPCB.LNKD, 0 }, - Package() { 0x0000ffff, 2, \_SB.PCI0.LPCB.LNKA, 0 }, - Package() { 0x0000ffff, 3, \_SB.PCI0.LPCB.LNKB, 0 } }) - - /* Interrupt Map INTA->INTD, INTB->INTA, INTC->INTB, INTD->INTC */ - Name (IQDA, Package() { - Package() { 0x0000ffff, 0, 0, 19 }, - Package() { 0x0000ffff, 1, 0, 16 }, - Package() { 0x0000ffff, 2, 0, 17 }, - Package() { 0x0000ffff, 3, 0, 18 } }) - Name (IQDP, Package() { - Package() { 0x0000ffff, 0, \_SB.PCI0.LPCB.LNKD, 0 }, - Package() { 0x0000ffff, 1, \_SB.PCI0.LPCB.LNKA, 0 }, - Package() { 0x0000ffff, 2, \_SB.PCI0.LPCB.LNKB, 0 }, - Package() { 0x0000ffff, 3, \_SB.PCI0.LPCB.LNKC, 0 } }) - - Switch (ToInteger (Arg0)) { - /* PCIe Root Port 1 */ - Case (Package() { 1 }) { - If (PICM) { - Return (IQAA) - } Else { - Return (IQAP) - } - } - - /* PCIe Root Port 2 */ - Case (Package() { 2 }) { - If (PICM) { - Return (IQBA) - } Else { - Return (IQBP) - } - } - - /* PCIe Root Port 3 */ - Case (Package() { 3 }) { - If (PICM) { - Return (IQCA) - } Else { - Return (IQCP) - } - } - - /* PCIe Root Port 4 */ - Case (Package() { 4 }) { - If (PICM) { - Return (IQDA) - } Else { - Return (IQDP) - } - } - - Default { - If (PICM) { - Return (IQDA) - } Else { - Return (IQDP) - } - } - } -} - -Device (RP01) -{ - Name (_ADR, 0x00010000) - - #include "pcie_port.asl" - - Method (_PRT) - { - Return (IRQM (RPPN)) - } -} - -Device (RP02) -{ - Name (_ADR, 0x00020000) - - #include "pcie_port.asl" - - Method (_PRT) - { - Return (IRQM (RPPN)) - } -} - -Device (RP03) -{ - Name (_ADR, 0x00030000) - - #include "pcie_port.asl" - - Method (_PRT) - { - Return (IRQM (RPPN)) - } -} - -Device (RP04) -{ - Name (_ADR, 0x00040000) - - #include "pcie_port.asl" - - Method (_PRT) - { - Return (IRQM (RPPN)) - } -} diff --git a/src/southbridge/intel/fsp_rangeley/acpi/pcie_port.asl b/src/southbridge/intel/fsp_rangeley/acpi/pcie_port.asl deleted file mode 100644 index 32ddeadde5..0000000000 --- a/src/southbridge/intel/fsp_rangeley/acpi/pcie_port.asl +++ /dev/null @@ -1,25 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2012 The Chromium OS Authors. All Rights Reserved. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -/* Included in each PCIe Root Port device */ - -OperationRegion (RPCS, PCI_Config, 0x00, 0xFF) -Field (RPCS, AnyAcc, NoLock, Preserve) -{ - Offset (0x4c), // Link Capabilities - , 24, - RPPN, 8, // Root Port Number -} diff --git a/src/southbridge/intel/fsp_rangeley/acpi/sata.asl b/src/southbridge/intel/fsp_rangeley/acpi/sata.asl deleted file mode 100644 index 3855633a67..0000000000 --- a/src/southbridge/intel/fsp_rangeley/acpi/sata.asl +++ /dev/null @@ -1,77 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007-2009 coresystems GmbH - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -// Intel SATA Controller 0:17.0 - -// Note: Some BIOSes put the S-ATA code into an SSDT to make it easily -// pluggable - -Device (SATA) -{ - Name (_ADR, 0x00170000) - - Device (PRID) - { - Name (_ADR, 0) - - // Get Timing Mode - Method (_GTM, 0, Serialized) - { - Name(PBUF, Buffer(20) { - 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, - 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, - 0x00,0x00,0x00,0x00 }) - - CreateDwordField (PBUF, 0, PIO0) - CreateDwordField (PBUF, 4, DMA0) - CreateDwordField (PBUF, 8, PIO1) - CreateDwordField (PBUF, 12, DMA1) - CreateDwordField (PBUF, 16, FLAG) - - // TODO fill return structure - - Return (PBUF) - } - - // Set Timing Mode - Method (_STM, 3) - { - CreateDwordField (Arg0, 0, PIO0) - CreateDwordField (Arg0, 4, DMA0) - CreateDwordField (Arg0, 8, PIO1) - CreateDwordField (Arg0, 12, DMA1) - CreateDwordField (Arg0, 16, FLAG) - - // TODO: Do the deed - } - - Device (DSK0) - { - Name (_ADR, 0) - // TODO: _RMV ? - // TODO: _GTF ? - } - - Device (DSK1) - { - Name (_ADR, 1) - - // TODO: _RMV ? - // TODO: _GTF ? - } - - } -} diff --git a/src/southbridge/intel/fsp_rangeley/acpi/soc.asl b/src/southbridge/intel/fsp_rangeley/acpi/soc.asl deleted file mode 100644 index f22d48d139..0000000000 --- a/src/southbridge/intel/fsp_rangeley/acpi/soc.asl +++ /dev/null @@ -1,272 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007-2009 coresystems GmbH - * Copyright (C) 2014 Sage Electronic Engineering, LLC. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -/* Intel Rangeley support */ - -#include "../soc.h" - -Scope(\) -{ - // IO-Trap at 0x800. This is the ACPI->SMI communication interface. - - OperationRegion(IO_T, SystemIO, 0x800, 0x10) - Field(IO_T, ByteAcc, NoLock, Preserve) - { - Offset(0x8), - TRP0, 8 // IO-Trap at 0x808 - } - -#ifdef ACPI_INCLUDE_PMIO - // PCH Power Management Registers, located at PMBASE (0x1f.0 0x40.l) - OperationRegion(PMIO, SystemIO, DEFAULT_ABASE, 0x80) - Field(PMIO, ByteAcc, NoLock, Preserve) - { - Offset(0x20), // GPE0_STS - , 16, - GS00, 1, // GPIO00 SCI/Wake Status - GS01, 1, // GPIO01 SCI/Wake Status - GS02, 1, // GPIO02 SCI/Wake Status - GS03, 1, // GPIO03 SCI/Wake Status - GS04, 1, // GPIO04 SCI/Wake Status - GS05, 1, // GPIO05 SCI/Wake Status - GS06, 1, // GPIO06 SCI/Wake Status - GS07, 1, // GPIO07 SCI/Wake Status - GS08, 1, // GPIO08 SCI/Wake Status - GS09, 1, // GPIO09 SCI/Wake Status - GS10, 1, // GPIO10 SCI/Wake Status - GS11, 1, // GPIO11 SCI/Wake Status - GS12, 1, // GPIO12 SCI/Wake Status - GS13, 1, // GPIO13 SCI/Wake Status - GS14, 1, // GPIO14 SCI/Wake Status - GS15, 1, // GPIO15 SCI/Wake Status - Offset(0x28), // GPE0_EN - , 16, - GE00, 1, // GPIO00 SCI/Wake Enable - GE01, 1, // GPIO01 SCI/Wake Enable - GE02, 1, // GPIO02 SCI/Wake Enable - GE03, 1, // GPIO03 SCI/Wake Enable - GE04, 1, // GPIO04 SCI/Wake Enable - GE05, 1, // GPIO05 SCI/Wake Enable - GE06, 1, // GPIO06 SCI/Wake Enable - GE07, 1, // GPIO07 SCI/Wake Enable - GE08, 1, // GPIO08 SCI/Wake Enable - GE09, 1, // GPIO09 SCI/Wake Enable - GE10, 1, // GPIO10 SCI/Wake Enable - GE11, 1, // GPIO11 SCI/Wake Enable - GE12, 1, // GPIO12 SCI/Wake Enable - GE13, 1, // GPIO13 SCI/Wake Enable - GE14, 1, // GPIO14 SCI/Wake Enable - GE15, 1, // GPIO15 SCI/Wake Enable - Offset(0x42), // General Purpose Control - , 1, // skip 1 bit - GPEC, 1, // SWGPE_CTRL - } -#endif - -#ifdef ACPI_INCLUDE_GPIO - // GPIO IO mapped registers (0x1f.0 reg 0x48.l) - OperationRegion(GPIO, SystemIO, DEFAULT_GPIOBASE, 0x6c) - Field(GPIO, ByteAcc, NoLock, Preserve) - { - Offset(0x00), // GPIO Use Select - GU00, 8, - GU01, 8, - GU02, 8, - GU03, 8, - Offset(0x04), // GPIO IO Select - GIO0, 8, - GIO1, 8, - GIO2, 8, - GIO3, 8, - Offset(0x0c), // GPIO Level - GP00, 1, - GP01, 1, - GP02, 1, - GP0e, 1, - GP04, 1, - GP05, 1, - GP06, 1, - GP07, 1, - GP08, 1, - GP09, 1, - GP10, 1, - GP11, 1, - GP12, 1, - GP13, 1, - GP14, 1, - GP15, 1, - GP16, 1, - GP17, 1, - GP18, 1, - GP19, 1, - GP20, 1, - GP21, 1, - GP22, 1, - GP23, 1, - GP24, 1, - GP25, 1, - GP26, 1, - GP27, 1, - GP28, 1, - GP29, 1, - GP30, 1, - GP31, 1, - Offset(0x18), // GPIO Blink - GB00, 8, - GB01, 8, - GB02, 8, - GB03, 8, - Offset(0x2c), // GPIO Invert - GIV0, 8, - GIV1, 8, - GIV2, 8, - GIV3, 8, - Offset(0x30), // GPIO Use Select 2 - GU04, 8, - GU05, 8, - GU06, 8, - GU07, 8, - Offset(0x34), // GPIO IO Select 2 - GIO4, 8, - GIO5, 8, - GIO6, 8, - GIO7, 8, - Offset(0x38), // GPIO Level 2 - GP32, 1, - GP33, 1, - GP34, 1, - GP35, 1, - GP36, 1, - GP37, 1, - GP38, 1, - GP39, 1, - GP40, 1, - GP41, 1, - GP42, 1, - GP43, 1, - GP44, 1, - GP45, 1, - GP46, 1, - GP47, 1, - GP48, 1, - GP49, 1, - GP50, 1, - GP51, 1, - GP52, 1, - GP53, 1, - GP54, 1, - GP55, 1, - GP56, 1, - GP57, 1, - GP58, 1, - GP59, 1, - GP60, 1, - GP61, 1, - GP62, 1, - GP63, 1, - Offset(0x40), // GPIO Use Select 3 - GU08, 8, - GU09, 4, - Offset(0x44), // GPIO IO Select 3 - GIO8, 8, - GIO9, 4, - Offset(0x48), // GPIO Level 3 - GP64, 1, - GP65, 1, - GP66, 1, - GP67, 1, - GP68, 1, - GP69, 1, - GP70, 1, - GP71, 1, - GP72, 1, - GP73, 1, - GP74, 1, - GP75, 1, - } -#endif - - // ICH7 Root Complex Register Block. Memory Mapped through RCBA) - OperationRegion(RCRB, SystemMemory, DEFAULT_RCBA, 0x4000) - Field(RCRB, DWordAcc, Lock, Preserve) - { - Offset(0x0000), // Backbone - Offset(0x1000), // Chipset - Offset(0x3000), // Legacy Configuration Registers - Offset(0x3404), // High Performance Timer Configuration - HPAS, 2, // Address Select - , 5, - HPTE, 1, // Address Enable - Offset(0x3418), // FD (Function Disable) - , 1, // Reserved - PCID, 1, // PCI bridge disable - SA1D, 1, // SATA1 disable - SMBD, 1, // SMBUS disable - HDAD, 1, // Azalia disable - , 8, // Reserved - EH2D, 1, // EHCI #2 disable - LPBD, 1, // LPC bridge disable - EH1D, 1, // EHCI #1 disable - RP1D, 1, // Root Port 1 disable - RP2D, 1, // Root Port 2 disable - RP3D, 1, // Root Port 3 disable - RP4D, 1, // Root Port 4 disable - TTRD, 1, // Thermal sensor registers disable - SA2D, 1, // SATA2 disable - Offset(0x3428), // FD2 (Function Disable 2) - BDFD, 1, // Display BDF - ME1D, 1, // ME Interface 1 disable - ME2D, 1, // ME Interface 2 disable - IDRD, 1, // IDE redirect disable - KTCT, 1, // Keyboard Text redirect disable - } -} - -// PCI Express Ports 0:[1-4].0 -#include "pcie.asl" - -// USB 0:16.0 -#include "usb.asl" - -// LPC Bridge 0:1f.0 -#include "lpc.asl" - -// SATA 0:17.0 -#include "sata.asl" - -// SMBus 0:1f.3 -#include - -// IRQ routing for each PCI device -#include "irqroute.asl" - -Method (_OSC, 4) -{ - /* Check for proper GUID */ - If (LEqual (Arg0, ToUUID("33DB4D5B-1FF7-401C-9657-7441C03DD766"))) - { - /* Let OS control everything */ - Return (Arg3) - } - Else - { - /* Unrecognized UUID */ - CreateDWordField (Arg3, 0, CDW1) - Or (CDW1, 4, CDW1) - Return (Arg3) - } -} diff --git a/src/southbridge/intel/fsp_rangeley/acpi/usb.asl b/src/southbridge/intel/fsp_rangeley/acpi/usb.asl deleted file mode 100644 index a1cd09d186..0000000000 --- a/src/southbridge/intel/fsp_rangeley/acpi/usb.asl +++ /dev/null @@ -1,48 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007-2009 coresystems GmbH - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -/* Intel Rangeley USB support */ - -// EHCI Controller 0:16.0 - -Device (EHC1) -{ - Name(_ADR, 0x00160000) - - Name (_PRW, Package(){ 13, 4 }) // Power Resources for Wake - - // Leave USB ports on for to allow Wake from USB - - Method(_S3D,0) // Highest D State in S3 State - { - Return (2) - } - - Method(_S4D,0) // Highest D State in S4 State - { - Return (2) - } - - Device (HUB7) - { - Name (_ADR, 0x00000000) - - Device (PRT1) { Name (_ADR, 1) } // USB Port 0 - Device (PRT2) { Name (_ADR, 2) } // USB Port 1 - Device (PRT3) { Name (_ADR, 3) } // USB Port 2 - Device (PRT4) { Name (_ADR, 4) } // USB Port 3 - } -} diff --git a/src/southbridge/intel/fsp_rangeley/chip.h b/src/southbridge/intel/fsp_rangeley/chip.h deleted file mode 100644 index 3eef5a9046..0000000000 --- a/src/southbridge/intel/fsp_rangeley/chip.h +++ /dev/null @@ -1,84 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2008-2009 coresystems GmbH - * Copyright (C) 2014 Sage Electronic Engineering, LLC. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef SOUTHBRIDGE_INTEL_RANGELEY_CHIP_H -#define SOUTHBRIDGE_INTEL_RANGELEY_CHIP_H - -#include - -struct southbridge_intel_fsp_rangeley_config { - - /** - * GPI Routing configuration - * - * Only the lower two bits have a meaning: - * 00: No effect - * 01: SMI# (if corresponding ALT_GPI_SMI_EN bit is also set) - * 10: SCI (if corresponding GPIO_EN bit is also set) - * 11: reserved - */ - uint8_t gpi0_routing; - uint8_t gpi1_routing; - uint8_t gpi2_routing; - uint8_t gpi3_routing; - uint8_t gpi4_routing; - uint8_t gpi5_routing; - uint8_t gpi6_routing; - uint8_t gpi7_routing; - uint8_t gpi8_routing; - uint8_t gpi9_routing; - uint8_t gpi10_routing; - uint8_t gpi11_routing; - uint8_t gpi12_routing; - uint8_t gpi13_routing; - uint8_t gpi14_routing; - uint8_t gpi15_routing; - - uint32_t gpe0_en; - uint16_t alt_gp_smi_en; - - /* IDE configuration */ - uint32_t ide_legacy_combined; - uint32_t sata_ahci; - uint8_t sata_port_map; - uint32_t sata_port0_gen3_tx; - uint32_t sata_port1_gen3_tx; - - uint32_t gen1_dec; - uint32_t gen2_dec; - uint32_t gen3_dec; - uint32_t gen4_dec; - - /* Enable linear PCIe Root Port function numbers starting at zero */ - uint8_t pcie_port_coalesce; - - /* Override PCIe ASPM */ - uint8_t pcie_aspm_f0; - uint8_t pcie_aspm_f1; - uint8_t pcie_aspm_f2; - uint8_t pcie_aspm_f3; - uint8_t pcie_aspm_f4; - uint8_t pcie_aspm_f5; - uint8_t pcie_aspm_f6; - uint8_t pcie_aspm_f7; - - /* ACPI configuration */ - uint8_t fadt_pm_profile; - uint16_t fadt_boot_arch; - -}; - -#endif /* SOUTHBRIDGE_INTEL_RANGELEY_CHIP_H */ diff --git a/src/southbridge/intel/fsp_rangeley/early_init.c b/src/southbridge/intel/fsp_rangeley/early_init.c deleted file mode 100644 index cec7a318bc..0000000000 --- a/src/southbridge/intel/fsp_rangeley/early_init.c +++ /dev/null @@ -1,76 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007-2010 coresystems GmbH - * Copyright (C) 2011 Google Inc - * Copyright (C) 2013-2014 Sage Electronic Engineering, LLC. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include "pci_devs.h" -#include "soc.h" - -static void rangeley_setup_bars(void) -{ - /* Setting up Southbridge. */ - printk(BIOS_DEBUG, "Setting up static southbridge registers..."); - pci_write_config32(LPC_BDF, RCBA, (uintptr_t)DEFAULT_RCBA | RCBA_ENABLE); - pci_write_config32(LPC_BDF, ABASE, DEFAULT_ABASE | SET_BAR_ENABLE); - pci_write_config32(LPC_BDF, PBASE, DEFAULT_PBASE | SET_BAR_ENABLE); - printk(BIOS_DEBUG, " done.\n"); - - printk(BIOS_DEBUG, "Disabling Watchdog timer..."); - /* Disable the watchdog reboot and turn off the watchdog timer */ - write8((void *)(DEFAULT_PBASE + PMC_CFG), - read8((void *)(DEFAULT_PBASE + PMC_CFG)) | NO_REBOOT); // disable reboot on timer trigger - outw(inw(DEFAULT_ABASE + TCO1_CNT) | TCO_TMR_HALT, - DEFAULT_ABASE + TCO1_CNT); // disable watchdog timer - - printk(BIOS_DEBUG, " done.\n"); - -} - -static void reset_rtc(void) -{ - uint32_t pbase = pci_read_config32(LPC_BDF, PBASE) & - 0xfffffff0; - uint32_t gen_pmcon1 = read32((void *)(pbase + GEN_PMCON1)); - int rtc_failed = !!(gen_pmcon1 & RPS); - - if (rtc_failed) { - printk(BIOS_DEBUG, - "RTC Failure detected. Resetting Date to %s\n", - coreboot_dmi_date); - - /* Clear the power failure flag */ - write32((void *)(DEFAULT_PBASE + GEN_PMCON1), - gen_pmcon1 & ~RPS); - } - - cmos_init(rtc_failed); -} - -void rangeley_sb_early_initialization(void) -{ - /* Setup all BARs required for early PCIe and raminit */ - rangeley_setup_bars(); - - reset_rtc(); -} diff --git a/src/southbridge/intel/fsp_rangeley/early_smbus.c b/src/southbridge/intel/fsp_rangeley/early_smbus.c deleted file mode 100644 index da0c54be3f..0000000000 --- a/src/southbridge/intel/fsp_rangeley/early_smbus.c +++ /dev/null @@ -1,57 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2008-2009 coresystems GmbH - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include -#include -#include -#include "soc.h" - -void enable_smbus(void) -{ - pci_devfn_t dev; - - /* Set the SMBus device statically. */ - dev = PCI_DEV(0x0, 0x1f, 0x3); - - /* Check to make sure we've got the right device. */ - if (pci_read_config16(dev, 0x0) != 0x8086) { - die("SMBus controller not found!"); - } - - /* Set SMBus I/O base. */ - pci_write_config32(dev, SMB_BASE, - SMBUS_IO_BASE | PCI_BASE_ADDRESS_SPACE_IO); - - /* Set SMBus enable. */ - pci_write_config8(dev, HOSTC, HST_EN); - - /* Set SMBus I/O space enable. */ - pci_write_config16(dev, PCI_COMMAND, PCI_COMMAND_IO); - - /* Disable interrupt generation. */ - outb(0, SMBUS_IO_BASE + SMBHSTCTL); - - /* Clear any lingering errors, so transactions can run. */ - outb(inb(SMBUS_IO_BASE + SMBHSTSTAT), SMBUS_IO_BASE + SMBHSTSTAT); - printk(BIOS_DEBUG, "SMBus controller enabled.\n"); -} - -int smbus_read_byte(unsigned int device, unsigned int address) -{ - return do_smbus_read_byte(SMBUS_IO_BASE, device, address); -} diff --git a/src/southbridge/intel/fsp_rangeley/early_usb.c b/src/southbridge/intel/fsp_rangeley/early_usb.c deleted file mode 100644 index 0b10ef6e05..0000000000 --- a/src/southbridge/intel/fsp_rangeley/early_usb.c +++ /dev/null @@ -1,41 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2008-2009 coresystems GmbH - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include "soc.h" - -#define SOC_EHCI1_TEMP_BAR0 0xe8000000 - -/* - * Setup USB controller MMIO BAR to prevent the - * reference code from resetting the controller. - * - * The BAR will be re-assigned during device - * enumeration so these are only temporary. - */ -void enable_usb_bar(void) -{ - pci_devfn_t usb0 = SOC_EHCI1_DEV; - u32 cmd; - - /* USB Controller 0 */ - pci_write_config32(usb0, PCI_BASE_ADDRESS_0, - SOC_EHCI1_TEMP_BAR0); - cmd = pci_read_config32(usb0, PCI_COMMAND); - cmd |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY; - pci_write_config32(usb0, PCI_COMMAND, cmd); -} diff --git a/src/southbridge/intel/fsp_rangeley/gpio.c b/src/southbridge/intel/fsp_rangeley/gpio.c deleted file mode 100644 index 6db431cb16..0000000000 --- a/src/southbridge/intel/fsp_rangeley/gpio.c +++ /dev/null @@ -1,105 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 The Chromium OS Authors. All rights reserved. - * Copyright (C) 2013 Sage Electronic Engineering, LLC. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include -#include - -#include "soc.h" -#include "gpio.h" - -#define MAX_GPIO_NUMBER 31 /* zero based */ - -void setup_soc_gpios(const struct soc_gpio_map *gpio) -{ - u16 gpiobase = pci_read_config16(SOC_LPC_DEV, GBASE) & ~0xf; - u32 *cfiobase = (u32 *)(pci_read_config32(SOC_LPC_DEV, IOBASE) & ~0xf); - u32 cfio_cnt = 0; - - - /* GPIO */ - if (gpio->core.level) - outl(*((u32*)gpio->core.level), gpiobase + GPIO_SC_GP_LVL); - if (gpio->core.mode) - outl(*((u32*)gpio->core.mode), gpiobase + GPIO_SC_USE_SEL); - if (gpio->core.direction) - outl(*((u32*)gpio->core.direction), gpiobase + GPIO_SC_IO_SEL); - if (gpio->core.tpe) - outl(*((u32*)gpio->core.tpe), gpiobase + GPIO_SC_TPE); - if (gpio->core.tne) - outl(*((u32*)gpio->core.tne), gpiobase + GPIO_SC_TNE); - if (gpio->core.ts) - outl(*((u32*)gpio->core.ts), gpiobase + GPIO_SC_TS); - - /* GPIO SUS Well Set 1 */ - if (gpio->sus.level) - outl(*((u32*)gpio->sus.level), gpiobase + GPIO_SUS_GP_LVL); - if (gpio->sus.mode) - outl(*((u32*)gpio->sus.mode), gpiobase + GPIO_SUS_USE_SEL); - if (gpio->sus.direction) - outl(*((u32*)gpio->sus.direction), gpiobase + GPIO_SUS_IO_SEL); - if (gpio->sus.tpe) - outl(*((u32*)gpio->sus.tpe), gpiobase + GPIO_SUS_TPE); - if (gpio->sus.tne) - outl(*((u32*)gpio->sus.tne), gpiobase + GPIO_SUS_TNE); - if (gpio->sus.ts) - outl(*((u32*)gpio->sus.ts), gpiobase + GPIO_SUS_TS); - if (gpio->sus.we) - outl(*((u32*)gpio->sus.we), gpiobase + GPIO_SUS_WE); - - /* GPIO PAD Settings */ - /* CFIO Core Well Set 1 */ - if ((gpio->core.cfio_init != NULL) && (gpio->core.cfio_entrynum != 0)) { - write32(cfiobase + (0x0700 / sizeof(u32)), (u32)0x01001002); - for (cfio_cnt = 0; cfio_cnt < gpio->core.cfio_entrynum; cfio_cnt++) { - if (!((u32)gpio->core.cfio_init[cfio_cnt].pad_conf_0)) - continue; - write32(cfiobase + ((CFIO_PAD_CONF0 + (16*cfio_cnt))/sizeof(u32)), (u32)gpio->core.cfio_init[cfio_cnt].pad_conf_0); - write32(cfiobase + ((CFIO_PAD_CONF1 + (16*cfio_cnt))/sizeof(u32)), (u32)gpio->core.cfio_init[cfio_cnt].pad_conf_1); - write32(cfiobase + ((CFIO_PAD_VAL + (16*cfio_cnt))/sizeof(u32)), (u32)gpio->core.cfio_init[cfio_cnt].pad_val); - write32(cfiobase + ((CFIO_PAD_DFT + (16*cfio_cnt))/sizeof(u32)), (u32)gpio->core.cfio_init[cfio_cnt].pad_dft); - } - write32(cfiobase + (0x0700 / sizeof(u32)), (u32)0x01041002); - } - - /* CFIO SUS Well Set 1 */ - if ((gpio->sus.cfio_init != NULL) && (gpio->sus.cfio_entrynum != 0)) { - write32(cfiobase + (0x1700 / sizeof(u32)), (u32)0x01001002); - for (cfio_cnt = 0; cfio_cnt < gpio->sus.cfio_entrynum; cfio_cnt++) { - if (!((u32)gpio->sus.cfio_init[cfio_cnt].pad_conf_0)) - continue; - write32(cfiobase + ((CFIO_PAD_CONF0 + 0x1000 + (16*cfio_cnt))/sizeof(u32)), (u32)gpio->sus.cfio_init[cfio_cnt].pad_conf_0); - write32(cfiobase + ((CFIO_PAD_CONF1 + 0x1000 + (16*cfio_cnt))/sizeof(u32)), (u32)gpio->sus.cfio_init[cfio_cnt].pad_conf_1); - write32(cfiobase + ((CFIO_PAD_VAL + 0x1000 + (16*cfio_cnt))/sizeof(u32)), (u32)gpio->sus.cfio_init[cfio_cnt].pad_val); - write32(cfiobase + ((CFIO_PAD_DFT + 0x1000 + (16*cfio_cnt))/sizeof(u32)), (u32)gpio->sus.cfio_init[cfio_cnt].pad_dft); - } - write32(cfiobase + (0x1700 / sizeof(u32)), (u32)0x01041002); - } -} - -int get_gpio(int gpio_num) -{ - u16 gpio_base = pci_read_config16(SOC_LPC_DEV, GBASE) & ~0xf; - int bit; - - if (gpio_num > MAX_GPIO_NUMBER) - return 0; /* Ignore wrong GPIO numbers. */ - - bit = gpio_num % 32; - - return (inl(gpio_base + GPIO_SC_USE_SEL) >> bit) & 1; -} diff --git a/src/southbridge/intel/fsp_rangeley/gpio.h b/src/southbridge/intel/fsp_rangeley/gpio.h deleted file mode 100644 index 6a27fea861..0000000000 --- a/src/southbridge/intel/fsp_rangeley/gpio.h +++ /dev/null @@ -1,124 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 The Chromium OS Authors. All rights reserved. - * Copyright (C) 2013 Sage Electronic Engineering, LLC. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef INTEL_RANGELEY_GPIO_H -#define INTEL_RANGELEY_GPIO_H - -#define GPIO_MODE_NATIVE 0 -#define GPIO_MODE_GPIO 1 -#define GPIO_MODE_NONE 1 - -#define GPIO_DIR_OUTPUT 0 -#define GPIO_DIR_INPUT 1 - -#define GPIO_LEVEL_LOW 0 -#define GPIO_LEVEL_HIGH 1 - -#define GPIO_TPE_DISABLE 0 -#define GPIO_TPE_ENABLE 1 - -#define GPIO_TNE_DISABLE 0 -#define GPIO_TNE_ENABLE 1 - -#define GPIO_TS_DISABLE 0 -#define GPIO_TS_ENABLE 1 - -#define GPIO_WE_DISABLE 0 -#define GPIO_WE_ENABLE 1 - -struct soc_gpio { - u32 gpio0 : 1; - u32 gpio1 : 1; - u32 gpio2 : 1; - u32 gpio3 : 1; - u32 gpio4 : 1; - u32 gpio5 : 1; - u32 gpio6 : 1; - u32 gpio7 : 1; - u32 gpio8 : 1; - u32 gpio9 : 1; - u32 gpio10 : 1; - u32 gpio11 : 1; - u32 gpio12 : 1; - u32 gpio13 : 1; - u32 gpio14 : 1; - u32 gpio15 : 1; - u32 gpio16 : 1; - u32 gpio17 : 1; - u32 gpio18 : 1; - u32 gpio19 : 1; - u32 gpio20 : 1; - u32 gpio21 : 1; - u32 gpio22 : 1; - u32 gpio23 : 1; - u32 gpio24 : 1; - u32 gpio25 : 1; - u32 gpio26 : 1; - u32 gpio27 : 1; - u32 gpio28 : 1; - u32 gpio29 : 1; - u32 gpio30 : 1; - u32 gpio31 : 1; -} __packed; - -struct soc_cfio { - u32 pad_conf_0; - u32 pad_conf_1; - u32 pad_val; - u32 pad_dft; -} __packed; - -struct soc_gpio_map { - /* GPIO core */ - struct { - const struct soc_gpio *mode; - const struct soc_gpio *direction; - const struct soc_gpio *level; - const struct soc_gpio *tpe; - const struct soc_gpio *tne; - const struct soc_gpio *ts; - const struct soc_cfio *cfio_init; - const u32 cfio_entrynum; - }core; - - /* GPIO SUS */ - struct { - const struct soc_gpio *mode; - const struct soc_gpio *direction; - const struct soc_gpio *level; - const struct soc_gpio *tpe; - const struct soc_gpio *tne; - const struct soc_gpio *ts; - const struct soc_gpio *we; - const struct soc_cfio *cfio_init; - const u32 cfio_entrynum; - }sus; - - -}; - -/* Configure GPIOs with mainboard provided settings */ -void setup_soc_gpios(const struct soc_gpio_map *gpio); - -/* Get GPIO pin value */ -int get_gpio(int gpio_num); -/* - * Get a number comprised of multiple GPIO values. gpio_num_array points to - * the array of GPIO pin numbers to scan, terminated by -1. - */ -unsigned int get_gpios(const int *gpio_num_array); - -#endif diff --git a/src/southbridge/intel/fsp_rangeley/irq.h b/src/southbridge/intel/fsp_rangeley/irq.h deleted file mode 100644 index 18e650fae4..0000000000 --- a/src/southbridge/intel/fsp_rangeley/irq.h +++ /dev/null @@ -1,162 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2013 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef _RANGELEY_IRQ_H_ -#define _RANGELEY_IRQ_H_ - -#define PIRQA_APIC_IRQ 16 -#define PIRQB_APIC_IRQ 17 -#define PIRQC_APIC_IRQ 18 -#define PIRQD_APIC_IRQ 19 -#define PIRQE_APIC_IRQ 20 -#define PIRQF_APIC_IRQ 21 -#define PIRQG_APIC_IRQ 22 -#define PIRQH_APIC_IRQ 23 -/* The below IRQs are for when devices are in ACPI mode. Active low. */ -#define LPE_DMA0_IRQ 24 -#define LPE_DMA1_IRQ 25 -#define LPE_SSP0_IRQ 26 -#define LPE_SSP1_IRQ 27 -#define LPE_SSP2_IRQ 28 -#define LPE_IPC2HOST_IRQ 29 -#define LPSS_I2C1_IRQ 32 -#define LPSS_I2C2_IRQ 33 -#define LPSS_I2C3_IRQ 34 -#define LPSS_I2C4_IRQ 35 -#define LPSS_I2C5_IRQ 36 -#define LPSS_I2C6_IRQ 37 -#define LPSS_I2C7_IRQ 38 -#define LPSS_HSUART1_IRQ 39 -#define LPSS_HSUART2_IRQ 40 -#define LPSS_SPI_IRQ 41 -#define LPSS_DMA1_IRQ 42 -#define LPSS_DMA2_IRQ 43 -#define SCC_EMMC_IRQ 44 -#define SCC_SDIO_IRQ 46 -#define SCC_SD_IRQ 47 -#define GPIO_NC_IRQ 48 -#define GPIO_SC_IRQ 49 -#define GPIO_SUS_IRQ 50 -/* GPIO direct / dedicated IRQs. */ -#define GPIO_S0_DED_IRQ_0 51 -#define GPIO_S0_DED_IRQ_1 52 -#define GPIO_S0_DED_IRQ_2 53 -#define GPIO_S0_DED_IRQ_3 54 -#define GPIO_S0_DED_IRQ_4 55 -#define GPIO_S0_DED_IRQ_5 56 -#define GPIO_S0_DED_IRQ_6 57 -#define GPIO_S0_DED_IRQ_7 58 -#define GPIO_S0_DED_IRQ_8 59 -#define GPIO_S0_DED_IRQ_9 60 -#define GPIO_S0_DED_IRQ_10 61 -#define GPIO_S0_DED_IRQ_11 62 -#define GPIO_S0_DED_IRQ_12 63 -#define GPIO_S0_DED_IRQ_13 64 -#define GPIO_S0_DED_IRQ_14 65 -#define GPIO_S0_DED_IRQ_15 66 -#define GPIO_S5_DED_IRQ_0 67 -#define GPIO_S5_DED_IRQ_1 68 -#define GPIO_S5_DED_IRQ_2 69 -#define GPIO_S5_DED_IRQ_3 70 -#define GPIO_S5_DED_IRQ_4 71 -#define GPIO_S5_DED_IRQ_5 72 -#define GPIO_S5_DED_IRQ_6 73 -#define GPIO_S5_DED_IRQ_7 74 -#define GPIO_S5_DED_IRQ_8 75 -#define GPIO_S5_DED_IRQ_9 76 -#define GPIO_S5_DED_IRQ_10 77 -#define GPIO_S5_DED_IRQ_11 78 -#define GPIO_S5_DED_IRQ_12 79 -#define GPIO_S5_DED_IRQ_13 80 -#define GPIO_S5_DED_IRQ_14 81 -#define GPIO_S5_DED_IRQ_15 82 -/* DIRQs - Two levels of expansion to evaluate to numeric constants for ASL. */ -#define _GPIO_S0_DED_IRQ(slot) GPIO_S0_DED_IRQ_##slot -#define _GPIO_S5_DED_IRQ(slot) GPIO_S5_DED_IRQ_##slot -#define GPIO_S0_DED_IRQ(slot) _GPIO_S0_DED_IRQ(slot) -#define GPIO_S5_DED_IRQ(slot) _GPIO_S5_DED_IRQ(slot) - -/* PIC IRQ settings. */ -#define PIRQ_PIC_IRQ3 0x3 -#define PIRQ_PIC_IRQ4 0x4 -#define PIRQ_PIC_IRQ5 0x5 -#define PIRQ_PIC_IRQ6 0x6 -#define PIRQ_PIC_IRQ7 0x7 -#define PIRQ_PIC_IRQ9 0x9 -#define PIRQ_PIC_IRQ10 0xa -#define PIRQ_PIC_IRQ11 0xb -#define PIRQ_PIC_IRQ12 0xc -#define PIRQ_PIC_IRQ14 0xe -#define PIRQ_PIC_IRQ15 0xf -#define PIRQ_PIC_IRQDISABLE 0x80 -#define PIRQ_PIC_UNKNOWN_UNUSED 0xff - - -/* Overloaded term, but these values determine the per device route. */ -#define PIRQA 0 -#define PIRQB 1 -#define PIRQC 2 -#define PIRQD 3 -#define PIRQE 4 -#define PIRQF 5 -#define PIRQG 6 -#define PIRQH 7 - -/* These registers live behind the ILB_BASE_ADDRESS */ -#define ACTL 0x00 -# define SCIS_MASK 0x07 -# define SCIS_IRQ9 0x00 -# define SCIS_IRQ10 0x01 -# define SCIS_IRQ11 0x02 -# define SCIS_IRQ20 0x04 -# define SCIS_IRQ21 0x05 -# define SCIS_IRQ22 0x06 -# define SCIS_IRQ23 0x07 - -/* In each mainboard directory there should exist a header file irqroute.h that - * defines the PCI_DEV_PIRQ_ROUTES and PIRQ_PIC_ROUTES macros which - * consist of PCI_DEV_PIRQ_ROUTE and PIRQ_PIC entries. */ - -#if !defined(__ASSEMBLER__) && !defined(__ACPI__) -#include - -#define NUM_OF_PCI_DEVS 32 -#define NUM_PIRQS 8 - -struct rangeley_irq_route { - /* Per device configuration. */ - uint16_t pcidev[NUM_OF_PCI_DEVS]; - /* Route path for each internal PIRQx in PIC mode. */ - uint8_t pic[NUM_PIRQS]; -}; - -extern const struct rangeley_irq_route global_rangeley_irq_route; - -#define DEFINE_IRQ_ROUTES \ - const struct rangeley_irq_route global_rangeley_irq_route = { \ - .pcidev = { PCI_DEV_PIRQ_ROUTES, }, \ - .pic = { PIRQ_PIC_ROUTES, }, \ - } - -#define PCI_DEV_PIRQ_ROUTE(dev_, a_, b_, c_, d_) \ - [dev_] = ((PIRQ ## d_) << 12) | ((PIRQ ## c_) << 8) | \ - ((PIRQ ## b_) << 4) | ((PIRQ ## a_) << 0) - -#define PIRQ_PIC(pirq_, pic_irq_) \ - [PIRQ ## pirq_] = PIRQ_PIC_IRQ ## pic_irq_ - -#endif /* !defined(__ASSEMBLER__) && !defined(__ACPI__) */ - -#endif /* _RANGELEY_IRQ_H_ */ diff --git a/src/southbridge/intel/fsp_rangeley/lpc.c b/src/southbridge/intel/fsp_rangeley/lpc.c deleted file mode 100644 index d12c379ae6..0000000000 --- a/src/southbridge/intel/fsp_rangeley/lpc.c +++ /dev/null @@ -1,461 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2008-2009 coresystems GmbH - * Copyright (C) 2013 Sage Electronic Engineering, LLC. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include "chip.h" -#include "soc.h" -#include "irq.h" -#include "nvs.h" - -#define NMI_OFF 0 - -typedef struct southbridge_intel_fsp_rangeley_config config_t; - -static void soc_enable_apic(struct device *dev) -{ - int i; - u32 reg32; - volatile u32 *ioapic_index = (volatile u32 *)(IO_APIC_ADDR); - volatile u32 *ioapic_data = (volatile u32 *)(IO_APIC_ADDR + 0x10); - u8 *ilb_base = (u8 *)(pci_read_config32(dev, IBASE) & ~0x0f); - - /* - * Enable ACPI I/O and power management. - * Set SCI IRQ to IRQ9 - */ - write32(ilb_base + ILB_OIC, 0x100); /* AEN */ - reg32 = read32(ilb_base + ILB_OIC); /* Read back per BWG */ - write32(ilb_base + ILB_ACTL, 0); /* ACTL bit 2:0 SCIS IRQ9 */ - - *ioapic_index = 0; - *ioapic_data = (1 << 25); - - /* Affirm full set of redirection table entries ("write once") */ - *ioapic_index = 1; - reg32 = *ioapic_data; - *ioapic_index = 1; - *ioapic_data = reg32; - - *ioapic_index = 0; - reg32 = *ioapic_data; - printk(BIOS_DEBUG, "Southbridge APIC ID = %x\n", (reg32 >> 24) & 0x0f); - if (reg32 != (1 << 25)) - die("APIC Error\n"); - - printk(BIOS_SPEW, "Dumping IOAPIC registers\n"); - for (i=0; i<3; i++) { - *ioapic_index = i; - printk(BIOS_SPEW, " reg 0x%04x:", i); - reg32 = *ioapic_data; - printk(BIOS_SPEW, " 0x%08x\n", reg32); - } - - *ioapic_index = 3; /* Select Boot Configuration register. */ - *ioapic_data = 1; /* Use Processor System Bus to deliver interrupts. */ -} - -static void soc_enable_serial_irqs(struct device *dev) -{ - u8 *ibase; - - ibase = (u8 *)(pci_read_config32(dev, IBASE) & ~0xF); - - /* Set packet length and toggle silent mode bit for one frame. */ - write8(ibase + ILB_SERIRQ_CNTL, (1 << 7)); - -#if !CONFIG(SERIRQ_CONTINUOUS_MODE) - write8(ibase + ILB_SERIRQ_CNTL, 0); -#endif -} - -/* - * Write PCI config space IRQ assignments. PCI devices have the INT_LINE - * (0x3C) and INT_PIN (0x3D) registers which report interrupt routing - * information to operating systems and drivers. The INT_PIN register is - * generally read only and reports which interrupt pin A - D it uses. The - * INT_LINE register is configurable and reports which IRQ (generally the - * PIC IRQs 1 - 15) it will use. This needs to take interrupt pin swizzling - * on devices that are downstream on a PCI bridge into account. - * - * This function will loop through all enabled PCI devices and program the - * INT_LINE register with the correct PIC IRQ number for the INT_PIN that it - * uses. It then configures each interrupt in the pic to be level triggered. - */ -static void write_pci_config_irqs(void) -{ - struct device *irq_dev; - struct device *targ_dev; - uint8_t int_line = 0; - uint8_t original_int_pin = 0; - uint8_t new_int_pin = 0; - uint16_t current_bdf = 0; - uint16_t parent_bdf = 0; - uint8_t pirq = 0; - uint8_t device_num = 0; - const struct rangeley_irq_route *ir = &global_rangeley_irq_route; - - if (ir == NULL) { - printk(BIOS_WARNING, "Warning: Can't write PCI IRQ assignments because" - " 'global_rangeley_irq_route' structure does not exist\n"); - return; - } - - /* - * Loop through all enabled devices and program their - * INT_LINE, INT_PIN registers from values taken from - * the Interrupt Route registers in the ILB - */ - printk(BIOS_DEBUG, "PCI_CFG IRQ: Write PCI config space IRQ assignments\n"); - for (irq_dev = all_devices; irq_dev; irq_dev = irq_dev->next) { - - if ((irq_dev->path.type != DEVICE_PATH_PCI) || - (!irq_dev->enabled)) - continue; - - current_bdf = irq_dev->path.pci.devfn | - irq_dev->bus->secondary << 8; - - /* - * Step 1: Get the INT_PIN and device structure to look for - * in the pirq_data table defined in the mainboard directory. - */ - targ_dev = NULL; - new_int_pin = get_pci_irq_pins(irq_dev, &targ_dev); - if (targ_dev == NULL || new_int_pin < 1) - continue; - - /* Get the original INT_PIN for record keeping */ - original_int_pin = pci_read_config8(irq_dev, PCI_INTERRUPT_PIN); - - parent_bdf = targ_dev->path.pci.devfn - | targ_dev->bus->secondary << 8; - device_num = PCI_SLOT(parent_bdf); - - if (ir->pcidev[device_num] == 0) { - printk(BIOS_WARNING, - "Warning: PCI Device %d does not have an IRQ entry, skipping it\n", - device_num); - continue; - } - - /* Find the PIRQ that is attached to the INT_PIN this device uses */ - pirq = (ir->pcidev[device_num] >> ((new_int_pin - 1) * 4)) & 0xF; - - /* Get the INT_LINE this device/function will use */ - int_line = ir->pic[pirq]; - - if (int_line != PIRQ_PIC_IRQDISABLE) { - /* Set this IRQ to level triggered since it is used by a PCI device */ - i8259_configure_irq_trigger(int_line, IRQ_LEVEL_TRIGGERED); - /* Set the Interrupt Line register in PCI config space */ - pci_write_config8(irq_dev, PCI_INTERRUPT_LINE, int_line); - } else { - /* Set the Interrupt line register as "unknown or unused" */ - pci_write_config8(irq_dev, PCI_INTERRUPT_LINE, - PIRQ_PIC_UNKNOWN_UNUSED); - } - - printk(BIOS_SPEW, "\tINT_PIN\t\t: %d (%s)\n", - original_int_pin, pin_to_str(original_int_pin)); - if (parent_bdf != current_bdf) - printk(BIOS_SPEW, "\tSwizzled to\t: %d (%s)\n", - new_int_pin, pin_to_str(new_int_pin)); - printk(BIOS_SPEW, "\tPIRQ\t\t: %c\n" - "\tINT_LINE\t: 0x%X (IRQ %d)\n", - 'A' + pirq, int_line, int_line); - } - printk(BIOS_DEBUG, "PCI_CFG IRQ: Finished writing PCI config space IRQ assignments\n"); -} - -static void soc_pirq_init(struct device *dev) -{ - int i, j; - int pirq; - u8 *ibase = (u8 *)(pci_read_config32(dev, IBASE) & ~0xF); - u8 *pr_base = ibase + 0x08; - u16 *ir_base = (u16 *)(ibase + 0x20); - u32 *actl = (u32 *)ibase; - const struct rangeley_irq_route *ir = &global_rangeley_irq_route; - - /* Set up the PIRQ PIC routing based on static config. */ - printk(BIOS_SPEW, "Start writing IRQ assignments\n" - "PIRQ\tA\tB\tC\tD\tE\tF\tG\tH\n" - "IRQ "); - for (i = 0; i < NUM_PIRQS; i++) { - write8(pr_base + i*sizeof(ir->pic[i]), ir->pic[i]); - printk(BIOS_SPEW, "\t%d", ir->pic[i]); - } - printk(BIOS_SPEW, "\n\n"); - - /* Set up the per device PIRQ routing based on static config. */ - printk(BIOS_SPEW, "\t\t\tPIRQ[A-H] routed to each INT_PIN[A-D]\n" - "Dev\tINTA (IRQ)\tINTB (IRQ)\tINTC (IRQ)\tINTD (IRQ)\n"); - for (i = 0; i < NUM_OF_PCI_DEVS; i++) { - write16(ir_base + i, ir->pcidev[i]); - - /* If the entry is more than just 0, print it out */ - if (ir->pcidev[i]) { - printk(BIOS_SPEW, " %d: ", i); - for (j = 0; j < 4; j++) { - pirq = (ir->pcidev[i] >> (j * 4)) & 0xF; - printk(BIOS_SPEW, "\t%-4c (%d)", 'A' + pirq, ir->pic[pirq]); - } - printk(BIOS_SPEW, "\n"); - } - } - - /* Route SCI to IRQ9 */ - write32(actl, (read32(actl) & ~SCIS_MASK) | SCIS_IRQ9); - printk(BIOS_SPEW, "Finished writing IRQ assignments\n"); - - /* Write IRQ assignments to PCI config space */ - write_pci_config_irqs(); -} - -static void soc_power_options(struct device *dev) -{ - u8 reg8; - u16 pmbase; - u32 reg32; - - /* Get the chip configuration */ - config_t *config = dev->chip_info; - - int nmi_option; - - /* Set up NMI on errors. */ - reg8 = inb(0x61); - reg8 &= 0x0f; /* Higher Nibble must be 0 */ - reg8 &= ~(1 << 3); /* IOCHK# NMI Enable */ - // reg8 &= ~(1 << 2); /* PCI SERR# Enable */ - reg8 |= (1 << 2); /* PCI SERR# Disable for now */ - outb(reg8, 0x61); - - reg8 = inb(0x70); - nmi_option = NMI_OFF; - get_option(&nmi_option, "nmi"); - if (nmi_option) { - printk(BIOS_INFO, "NMI sources enabled.\n"); - reg8 &= ~(1 << 7); /* Set NMI. */ - } else { - printk(BIOS_INFO, "NMI sources disabled.\n"); - reg8 |= (1 << 7); /* Can't mask NMI from PCI-E and NMI_NOW */ - } - outb(reg8, 0x70); - - pmbase = pci_read_config16(dev, ABASE) & ~0xf; - - outl(config->gpe0_en, pmbase + GPE0_EN); - outw(config->alt_gp_smi_en, pmbase + ALT_GP_SMI_EN); - - /* Set up power management block and determine sleep mode */ - reg32 = inl(pmbase + PM1_CNT); // PM1_CNT - reg32 &= ~(7 << 10); // SLP_TYP - reg32 |= (1 << 0); // SCI_EN - outl(reg32, pmbase + PM1_CNT); -} - -/* Disable the HPET, Clear the counter, and re-enable it. */ -static void enable_hpet(void) -{ - write8((u8 *)HPET_GCFG, 0x00); - write32((u32 *)HPET_MCV, 0x00000000); - write32((u32 *)(HPET_MCV + 0x04), 0x00000000); - write8((u8 *)HPET_GCFG, 0x01); -} - -static void soc_disable_smm_only_flashing(struct device *dev) -{ - u8 reg8; - - printk(BIOS_SPEW, "Enabling BIOS updates outside of SMM... "); - reg8 = pci_read_config8(dev, 0xdc); /* BIOS_CNTL */ - reg8 &= ~(1 << 5); - pci_write_config8(dev, 0xdc, reg8); -} - -static void lpc_init(struct device *dev) -{ - printk(BIOS_DEBUG, "soc: lpc_init\n"); - - /* Set the value for PCI command register. */ - pci_write_config16(dev, PCI_COMMAND, 0x000f); - - /* IO APIC initialization. */ - soc_enable_apic(dev); - - soc_enable_serial_irqs(dev); - - /* Setup the PIRQ. */ - soc_pirq_init(dev); - - /* Setup power options. */ - soc_power_options(dev); - - /* Initialize power management */ - switch (soc_silicon_type()) { - case SOC_TYPE_RANGELEY: - break; - default: - printk(BIOS_DEBUG, "Unknown Chipset: 0x%04x\n", dev->device); - } - - /* Initialize ISA DMA. */ - isa_dma_init(); - - /* Initialize the High Precision Event Timers, if present. */ - enable_hpet(); - - setup_i8259(); - - /* Interrupt 9 should be level triggered (SCI) */ - i8259_configure_irq_trigger(9, 1); - - soc_disable_smm_only_flashing(dev); -} - -static void soc_lpc_read_resources(struct device *dev) -{ - struct resource *res; - config_t *config = dev->chip_info; - u8 io_index = 0; - - /* Get the normal PCI resources of this device. */ - pci_dev_read_resources(dev); - - /* Add an extra subtractive resource for both memory and I/O. */ - res = new_resource(dev, IOINDEX_SUBTRACTIVE(io_index++, 0)); - res->base = 0; - res->size = 0x1000; - res->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE | - IORESOURCE_ASSIGNED | IORESOURCE_FIXED; - - res = new_resource(dev, IOINDEX_SUBTRACTIVE(io_index++, 0)); - res->base = 0xff800000; - res->size = 0x00800000; /* 8 MB for flash */ - res->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE | - IORESOURCE_ASSIGNED | IORESOURCE_FIXED; - - res = new_resource(dev, 3); /* IOAPIC */ - res->base = IO_APIC_ADDR; - res->size = 0x00001000; - res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; - - /* Set SOC IO decode ranges if required.*/ - if ((config->gen1_dec & 0xFFFC) > 0x1000) { - res = new_resource(dev, IOINDEX_SUBTRACTIVE(io_index++, 0)); - res->base = config->gen1_dec & 0xFFFC; - res->size = (config->gen1_dec >> 16) & 0xFC; - res->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE | - IORESOURCE_ASSIGNED | IORESOURCE_FIXED; - } - - if ((config->gen2_dec & 0xFFFC) > 0x1000) { - res = new_resource(dev, IOINDEX_SUBTRACTIVE(io_index++, 0)); - res->base = config->gen2_dec & 0xFFFC; - res->size = (config->gen2_dec >> 16) & 0xFC; - res->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE | - IORESOURCE_ASSIGNED | IORESOURCE_FIXED; - } - - if ((config->gen3_dec & 0xFFFC) > 0x1000) { - res = new_resource(dev, IOINDEX_SUBTRACTIVE(io_index++, 0)); - res->base = config->gen3_dec & 0xFFFC; - res->size = (config->gen3_dec >> 16) & 0xFC; - res->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE | - IORESOURCE_ASSIGNED | IORESOURCE_FIXED; - } - - if ((config->gen4_dec & 0xFFFC) > 0x1000) { - res = new_resource(dev, IOINDEX_SUBTRACTIVE(io_index++, 0)); - res->base = config->gen4_dec & 0xFFFC; - res->size = (config->gen4_dec >> 16) & 0xFC; - res->flags = IORESOURCE_IO| IORESOURCE_SUBTRACTIVE | - IORESOURCE_ASSIGNED | IORESOURCE_FIXED; - } -} - -static void soc_lpc_enable_resources(struct device *dev) -{ - return pci_dev_enable_resources(dev); -} - -static void soc_lpc_enable(struct device *dev) -{ - soc_enable(dev); -} - -static void southbridge_inject_dsdt(struct device *dev) -{ - global_nvs_t *gnvs = cbmem_add (CBMEM_ID_ACPI_GNVS, sizeof(*gnvs)); - - if (gnvs) { - memset(gnvs, 0, sizeof(*gnvs)); - acpi_create_gnvs(gnvs); - - /* And tell SMI about it */ - if (CONFIG(HAVE_SMI_HANDLER)) - smm_setup_structures(gnvs, NULL, NULL); - - /* Add it to DSDT. */ - acpigen_write_scope("\\"); - acpigen_write_name_dword("NVSA", (u32) gnvs); - acpigen_pop_len(); - } -} - -static struct pci_operations pci_ops = { - .set_subsystem = pci_dev_set_subsystem, -}; - -static struct device_operations device_ops = { - .read_resources = soc_lpc_read_resources, - .set_resources = pci_dev_set_resources, - .enable_resources = soc_lpc_enable_resources, - .init = lpc_init, - .write_acpi_tables = acpi_write_hpet, - .acpi_inject_dsdt_generator = southbridge_inject_dsdt, - .enable = soc_lpc_enable, - .scan_bus = scan_static_bus, - .ops_pci = &pci_ops, -}; - -/* IDs for LPC device of Intel 89xx Series Chipset */ -static const unsigned short pci_device_ids[] = { 0x1F38, 0x1F39, 0x1F3A, 0x1F3B, - 0 }; - -static const struct pci_driver soc_lpc __pci_driver = { - .ops = &device_ops, - .vendor = PCI_VENDOR_ID_INTEL, - .devices = pci_device_ids, -}; diff --git a/src/southbridge/intel/fsp_rangeley/nvs.h b/src/southbridge/intel/fsp_rangeley/nvs.h deleted file mode 100644 index 47fca685ce..0000000000 --- a/src/southbridge/intel/fsp_rangeley/nvs.h +++ /dev/null @@ -1,151 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2008-2009 coresystems GmbH - * Copyright (C) 2011 Google Inc - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -typedef struct { - /* Miscellaneous */ - u16 osys; /* 0x00 - Operating System */ - u8 smif; /* 0x02 - SMI function call ("TRAP") */ - u8 prm0; /* 0x03 - SMI function call parameter */ - u8 prm1; /* 0x04 - SMI function call parameter */ - u8 scif; /* 0x05 - SCI function call (via _L00) */ - u8 prm2; /* 0x06 - SCI function call parameter */ - u8 prm3; /* 0x07 - SCI function call parameter */ - u8 lckf; /* 0x08 - Global Lock function for EC */ - u8 prm4; /* 0x09 - Lock function parameter */ - u8 prm5; /* 0x0a - Lock function parameter */ - u32 p80d; /* 0x0b - Debug port (IO 0x80) value */ - u8 lids; /* 0x0f - LID state (open = 1) */ - u8 pwrs; /* 0x10 - Power state (AC = 1) */ - /* Thermal policy */ - u8 tlvl; /* 0x11 - Throttle Level Limit */ - u8 flvl; /* 0x12 - Current FAN Level */ - u8 tcrt; /* 0x13 - Critical Threshold */ - u8 tpsv; /* 0x14 - Passive Threshold */ - u8 tmax; /* 0x15 - CPU Tj_max */ - u8 f0of; /* 0x16 - FAN 0 OFF Threshold */ - u8 f0on; /* 0x17 - FAN 0 ON Threshold */ - u8 f0pw; /* 0x18 - FAN 0 PWM value */ - u8 f1of; /* 0x19 - FAN 1 OFF Threshold */ - u8 f1on; /* 0x1a - FAN 1 ON Threshold */ - u8 f1pw; /* 0x1b - FAN 1 PWM value */ - u8 f2of; /* 0x1c - FAN 2 OFF Threshold */ - u8 f2on; /* 0x1d - FAN 2 ON Threshold */ - u8 f2pw; /* 0x1e - FAN 2 PWM value */ - u8 f3of; /* 0x1f - FAN 3 OFF Threshold */ - u8 f3on; /* 0x20 - FAN 3 ON Threshold */ - u8 f3pw; /* 0x21 - FAN 3 PWM value */ - u8 f4of; /* 0x22 - FAN 4 OFF Threshold */ - u8 f4on; /* 0x23 - FAN 4 ON Threshold */ - u8 f4pw; /* 0x24 - FAN 4 PWM value */ - u8 tmps; /* 0x25 - Temperature Sensor ID */ - u8 rsvd3[2]; - /* Processor Identification */ - u8 apic; /* 0x28 - APIC enabled */ - u8 mpen; /* 0x29 - MP capable/enabled */ - u8 pcp0; /* 0x2a - PDC CPU/CORE 0 */ - u8 pcp1; /* 0x2b - PDC CPU/CORE 1 */ - u8 ppcm; /* 0x2c - Max. PPC state */ - u8 pcnt; /* 0x2d - Processor Count */ - u8 rsvd4[4]; - /* Super I/O & CMOS config */ - u8 natp; /* 0x32 - SIO type */ - u8 s5u0; /* 0x33 - Enable USB0 in S5 */ - u8 s5u1; /* 0x34 - Enable USB1 in S5 */ - u8 s3u0; /* 0x35 - Enable USB0 in S3 */ - u8 s3u1; /* 0x36 - Enable USB1 in S3 */ - u8 s33g; /* 0x37 - Enable S3 in 3G */ - u32 obsolete_cmem; /* 0x38 - CBMEM TOC */ - /* Integrated Graphics Device */ - u8 igds; /* 0x3c - IGD state */ - u8 tlst; /* 0x3d - Display Toggle List Pointer */ - u8 cadl; /* 0x3e - currently attached devices */ - u8 padl; /* 0x3f - previously attached devices */ - u16 cste; /* 0x40 - current display state */ - u16 nste; /* 0x42 - next display state */ - u16 sste; /* 0x44 - set display state */ - u8 ndid; /* 0x46 - number of device ids */ - u32 did[5]; /* 0x47 - 5b device id 1..5 */ - u8 rsvd5[0x9]; - /* Backlight Control */ - u8 blcs; /* 0x64 - Backlight Control possible */ - u8 brtl; - u8 odds; - u8 rsvd6[0x7]; - /* Ambient Light Sensors*/ - u8 alse; /* 0x6e - ALS enable */ - u8 alaf; - u8 llow; - u8 lhih; - u8 rsvd7[0x6]; - /* Extended Mobile Access */ - u8 emae; /* 0x78 - EMA enable */ - u16 emap; /* 0x79 - EMA pointer */ - u16 emal; /* 0x7a - EMA Length */ - u8 rsvd8[0x5]; - /* MEF */ - u8 mefe; /* 0x82 - MEF enable */ - u8 rsvd9[0x9]; - /* TPM support */ - u8 tpmp; /* 0x8c - TPM */ - u8 tpme; - u8 rsvd10[8]; - /* SATA */ - u8 gtf0[7]; /* 0x96 - GTF task file buffer for port 0 */ - u8 gtf1[7]; - u8 gtf2[7]; - u8 idem; - u8 idet; - u8 rsvd11[7]; - /* IGD OpRegion (not implemented yet) */ - u32 aslb; /* 0xb4 - IGD OpRegion Base Address */ - u8 ibtt; /* 0xb8 - IGD boot type */ - u8 ipat; /* 0xb9 - IGD panel type */ - u8 itvf; /* 0xba - IGD TV format */ - u8 itvm; /* 0xbb - IGD TV minor format */ - u8 ipsc; /* 0xbc - IGD Panel Scaling */ - u8 iblc; /* 0xbd - IGD BLC configuration */ - u8 ibia; /* 0xbe - IGD BIA configuration */ - u8 issc; /* 0xbf - IGD SSC configuration */ - u8 i409; /* 0xc0 - IGD 0409 modified settings */ - u8 i509; /* 0xc1 - IGD 0509 modified settings */ - u8 i609; /* 0xc2 - IGD 0609 modified settings */ - u8 i709; /* 0xc3 - IGD 0709 modified settings */ - u8 idmm; /* 0xc4 - IGD Power Conservation */ - u8 idms; /* 0xc5 - IGD DVMT memory size */ - u8 if1e; /* 0xc6 - IGD Function 1 Enable */ - u8 hvco; /* 0xc7 - IGD HPLL VCO */ - u32 nxd[8]; /* 0xc8 - IGD next state DIDx for _DGS */ - u8 isci; /* 0xe8 - IGD SMI/SCI mode (0: SCI) */ - u8 pavp; /* 0xe9 - IGD PAVP data */ - u8 rsvd12; /* 0xea - rsvd */ - u8 oscc; /* 0xeb - PCIe OSC control */ - u8 npce; /* 0xec - native pcie support */ - u8 plfl; /* 0xed - platform flavor */ - u8 brev; /* 0xee - board revision */ - u8 dpbm; /* 0xef - digital port b mode */ - u8 dpcm; /* 0xf0 - digital port c mode */ - u8 dpdm; /* 0xf1 - digital port c mode */ - u8 alfp; /* 0xf2 - active lfp */ - u8 imon; /* 0xf3 - current graphics turbo imon value */ - u8 mmio; /* 0xf4 - 64bit mmio support */ - u8 rsvd13[11]; /* 0xf5 - rsvd */ - -} __packed global_nvs_t; - -void acpi_create_gnvs(global_nvs_t *gnvs); - -/* Used in SMM to find the ACPI GNVS address */ -global_nvs_t *smm_get_gnvs(void); diff --git a/src/southbridge/intel/fsp_rangeley/pci_devs.h b/src/southbridge/intel/fsp_rangeley/pci_devs.h deleted file mode 100644 index c5ef6b8c6f..0000000000 --- a/src/southbridge/intel/fsp_rangeley/pci_devs.h +++ /dev/null @@ -1,135 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2013 Google Inc. - * Copyright (C) 2013-2014 Sage Electronic Engineering, LLC. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef _RANGELEY_PCI_DEVS_H_ -#define _RANGELEY_PCI_DEVS_H_ - -#include - -#define BUS0 0 - -/* All these devices live on bus 0 with the associated device and function */ - -/* Host Bridge */ -#define SOC_DEV 0x0 -#define SOC_FUNC 0 -# define SOC_DEVFN_SOC PCI_DEVFN(SOC_DEV,SOC_FUNC) - -/* PCIE Port 1 */ -#define PCIE_PORT1_DEV 0x1 -#define PCIE_PORT1_FUNC 0 -# define SOC_DEVFN_PCIE_PORT1 PCI_DEVFN(PCIE_PORT1_DEV,PCIE_PORT1_FUNC) - -/* PCIE Port 2 */ -#define PCIE_PORT2_DEV 0x2 -#define PCIE_PORT2_FUNC 0 -# define SOC_DEVFN_PCIE_PORT2 PCI_DEVFN(PCIE_PORT2_DEV,PCIE_PORT2_FUNC) - -/* PCIE Port 3 */ -#define PCIE_PORT3_DEV 0x3 -#define PCIE_PORT3_FUNC 0 -# define SOC_DEVFN_PCIE_PORT3 PCI_DEVFN(PCIE_PORT3_DEV,PCIE_PORT3_FUNC) - -/* PCIE Port 4 */ -#define PCIE_PORT4_DEV 0x4 -#define PCIE_PORT4_FUNC 0 -# define SOC_DEVFN_PCIE_PORT4 PCI_DEVFN(PCIE_PORT4_DEV,PCIE_PORT4_FUNC) - -/* Host Bridge, Fabric, and RAS Registers */ -#define HOST_BRIDGE_DEV 0xe -#define HOST_BRIDGE_FUNC 0 -# define SOC_DEVFN_HOST_BRIDGE PCI_DEVFN(HOST_BRIDGE_DEV,HOST_BRIDGE_FUNC) - -/* Root Complex Event Collector (RCEC) */ -#define RCEC_DEV 0xf -#define RCEC_FUNC 0 -# define SOC_DEVFN_RCEC PCI_DEVFN(RCEC_DEV,RCEC_FUNC) - -/* SMBus 2.0 1 */ -#define SMBUS1_DEV 0x13 -#define SMBUS1_FUNC 0 -# define SOC_DEVFN_SMBUS1 PCI_DEVFN(SMBUS1_DEV,SMBUS1_FUNC) - -/* Gigabit Ethernet (GbE) */ -#define GBE_DEV 0x14 -#define GBE1_DEV GBE_DEV -#define GBE1_FUNC 0 -# define SOC_DEVFN_GBE1 PCI_DEVFN(GBE1_DEV,GBE1_FUNC) -#define GBE2_DEV GBE_DEV -#define GBE2_FUNC 1 -# define SOC_DEVFN_GBE2 PCI_DEVFN(GBE2_DEV,GBE2_FUNC) -#define GBE3_DEV GBE_DEV -#define GBE3_FUNC 2 -# define SOC_DEVFN_GBE3 PCI_DEVFN(GBE3_DEV,GBE3_FUNC) -#define GBE4_DEV GBE_DEV -#define GBE4_FUNC 3 -# define SOC_DEVFN_GBE4 PCI_DEVFN(GBE4_DEV,GBE4_FUNC) - -/* USB 2.0 */ -#define USB2_DEV 0x16 -#define USB2_FUNC 0 -# define SOC_DEVFN_USB2 PCI_DEVFN(USB2_DEV,USB2_FUNC) - -/* SATA Gen 2 */ -#define SATA2_DEV 0x17 -#define SATA2_FUNC 0 -# define SOC_DEVFN_SATA2 PCI_DEVFN(SATA2_DEV,SATA2_FUNC) - -/* SATA Gen 3 */ -#define SATA3_DEV 0x18 -#define SATA3_FUNC 0 -# define SOC_DEVFN_SATA3 PCI_DEVFN(SATA3_DEV,SATA3_FUNC) - -/* Platform Control Unit (PCU) */ -#define PCU_DEV 0x1f - -/* Low Pin Count (LPC/ISA) */ -#define LPC_DEV PCU_DEV -#define LPC_FUNC 0 -# define SOC_DEVFN_LPC PCI_DEVFN(LPC_DEV,LPC_FUNC) -# define LPC_BDF PCI_DEV(BUS0, LPC_DEV, LPC_FUNC) - -/* SMBus 2.0 0 */ -#define SMBUS0_DEV PCU_DEV -#define SMBUS0_FUNC 3 -# define SOC_DEVFN_SMBUS0 PCI_DEVFN(SMBUS0_DEV,SMBUS0_FUNC) - -/* Intel QuickAssist Integrated Accelerator (IQIA) */ -#define IQAT_DEV 0xb -#define IQAT_FUNC 0 -# define SOC_DEVFN_IQAT PCI_DEVFN(IQAT_DEV,IQAT_FUNC) - -#define SOC_DEVID 0x1f08 -#define PCIE_PORT1_DEVID 0x1f10 -#define PCIE_PORT2_DEVID 0x1f11 -#define PCIE_PORT3_DEVID 0x1f12 -#define PCIE_PORT4_DEVID 0x1f13 -#define HOST_BRIDGE_DEVID 0x1f14 -#define RCEC_DEVID 0x1f16 -#define SMBUS1_DEVID 0x1f15 -#define GBE_DEVID 0x1f41 -#define GBE1_DEVID GBE_DEVID -#define GBE2_DEVID GBE_DEVID -#define GBE3_DEVID GBE_DEVID -#define GBE4_DEVID GBE_DEVID -#define USB2_DEVID 0x1f2c -#define SATA2_DEVID 0x1f22 -#define SATA3_DEVID 0x1f32 -#define LPC_DEVID 0x1f38 -#define SMBUS0_DEVID 0x1f3c -#define IQAT_DEVID 0x1f18 - -#endif /* _RANGELEY_PCI_DEVS_H_ */ diff --git a/src/southbridge/intel/fsp_rangeley/romstage.c b/src/southbridge/intel/fsp_rangeley/romstage.c deleted file mode 100644 index f52a75205a..0000000000 --- a/src/southbridge/intel/fsp_rangeley/romstage.c +++ /dev/null @@ -1,137 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2013 Google Inc. - * Copyright (C) 2013-2014 Sage Electronic Engineering, LLC. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include "southbridge/intel/fsp_rangeley/soc.h" -#include "southbridge/intel/fsp_rangeley/gpio.h" -#include "southbridge/intel/fsp_rangeley/romstage.h" -#include -#include -#include "gpio.h" - -void main(FSP_INFO_HEADER *fsp_info_header) -{ - uint32_t fd_mask = 0; - uint32_t *func_dis = (uint32_t *)(DEFAULT_PBASE + PBASE_FUNC_DIS); - - /* - * Do not use the Serial Console before it is setup. - * This causes the I/O to clog and a side effect is - * that the reset button stops functioning. So - * instead just use outb so it doesn't output to the - * console when CONFIG_CONSOLE_POST. - */ - outb(0x40, 0x80); - - timestamp_init(get_initial_timestamp()); - timestamp_add_now(TS_START_ROMSTAGE); - - /* Rangeley UART POR state is enabled */ - console_init(); - post_code(0x41); - - /* Enable GPIOs BAR */ - pci_write_config32(SOC_LPC_DEV, GBASE, DEFAULT_GPIOBASE|0x02); - - early_mainboard_romstage_entry(); - - post_code(0x42); - rangeley_sb_early_initialization(); - - post_code(0x46); - /* Program any required function disables */ - get_func_disables(&fd_mask); - - if (fd_mask != 0) { - write32(func_dis, read32(func_dis) | fd_mask); - /* Ensure posted write hits. */ - read32(func_dis); - } - - timestamp_add_now(TS_BEFORE_INITRAM); - - /* - * Call early init to initialize memory and chipset. This function returns - * to the romstage_main_continue function with a pointer to the HOB - * structure. - */ - post_code(0x47); - printk(BIOS_DEBUG, "Starting the Intel FSP (early_init)\n"); - fsp_early_init(fsp_info_header); - die("Uh Oh! fsp_early_init should not return here.\n"); -} - -/******************************************************************************* - * The FSP early_init function returns to this function. - * Memory is setup and the stack is set by the FSP. - */ -void romstage_main_continue(EFI_STATUS status, void *hob_list_ptr) { - void *cbmem_hob_ptr; - - timestamp_add_now(TS_AFTER_INITRAM); - - post_code(0x48); - printk(BIOS_DEBUG, "%s status: %x hob_list_ptr: %x\n", - __func__, (u32) status, (u32) hob_list_ptr); - - /* FSP reconfigures USB, so reinit it to have debug */ - if (CONFIG(USBDEBUG_IN_PRE_RAM)) - usbdebug_hw_init(true); - - printk(BIOS_DEBUG, "FSP Status: 0x%0x\n", (u32)status); - - post_code(0x4b); - late_mainboard_romstage_entry(); - - post_code(0x4c); - - /* Decode E0000 and F0000 segment to DRAM */ - sideband_write(B_UNIT, BMISC, sideband_read(B_UNIT, BMISC) | (1 << 1) | (1 << 0)); - - cbmem_recovery(0); - - /* Save the HOB pointer in CBMEM to be used in ramstage*/ - cbmem_hob_ptr = cbmem_add(CBMEM_ID_HOB_POINTER, sizeof(*hob_list_ptr)); - if (cbmem_hob_ptr == NULL) - die("Could not allocate cbmem for HOB pointer"); - *(u32*)cbmem_hob_ptr = (u32)hob_list_ptr; - post_code(0x4e); - - if (CONFIG(SMM_TSEG)) - smm_list_regions(); - - /* Load the ramstage. */ - post_code(0x4f); - run_ramstage(); - while (1); -} - -uint64_t get_initial_timestamp(void) -{ - return 0; -} diff --git a/src/southbridge/intel/fsp_rangeley/romstage.h b/src/southbridge/intel/fsp_rangeley/romstage.h deleted file mode 100644 index 7921d8041b..0000000000 --- a/src/southbridge/intel/fsp_rangeley/romstage.h +++ /dev/null @@ -1,28 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2013 Google Inc. - * Copyright (C) 2014 Sage Electronic Engineering, LLC. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef _RANGELEY_ROMSTAGE_H_ -#define _RANGELEY_ROMSTAGE_H_ - -#include -#include - -void main(FSP_INFO_HEADER *fsp_info_header); -void early_mainboard_romstage_entry(void); -void late_mainboard_romstage_entry(void); -void get_func_disables(uint32_t *mask); - -#endif /* _RANGELEY_ROMSTAGE_H_ */ diff --git a/src/southbridge/intel/fsp_rangeley/sata.c b/src/southbridge/intel/fsp_rangeley/sata.c deleted file mode 100644 index 604c56636a..0000000000 --- a/src/southbridge/intel/fsp_rangeley/sata.c +++ /dev/null @@ -1,122 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2008-2009 coresystems GmbH - * Copyright (C) 2013 Sage Electronic Engineering, LLC. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include -#include -#include -#include -#include "chip.h" -#include "soc.h" - -typedef struct southbridge_intel_fsp_rangeley_config config_t; - -static void sata_init(struct device *dev) -{ - u32 reg32; - u16 reg16; - u32 *abar; - - /* Get the chip configuration */ - config_t *config = dev->chip_info; - - printk(BIOS_DEBUG, "SATA: Initializing...\n"); - - if (config == NULL) { - printk(BIOS_ERR, "SATA: ERROR: Device not in devicetree.cb!\n"); - return; - } - - /* SATA configuration is handled by the FSP */ - - /* Enable BARs */ - pci_write_config16(dev, PCI_COMMAND, 0x0007); - - if (config->ide_legacy_combined) { - printk(BIOS_DEBUG, "SATA: Controller in combined mode.\n"); - - /* Set the controller mode */ - reg16 = pci_read_config16(dev, SATA_MAP); - reg16 &= ~(3 << 6); - pci_write_config16(dev, SATA_MAP, reg16); - - /* No AHCI: clear AHCI base */ - pci_write_config32(dev, 0x24, 0x00000000); - - /* And without AHCI BAR no memory decoding */ - reg16 = pci_read_config16(dev, PCI_COMMAND); - reg16 &= ~PCI_COMMAND_MEMORY; - pci_write_config16(dev, PCI_COMMAND, reg16); - } else if (config->sata_ahci) { - printk(BIOS_DEBUG, "SATA: Controller in AHCI mode.\n"); - - /* Set the controller mode */ - reg16 = pci_read_config16(dev, SATA_MAP); - reg16 &= ~(3 << 6); - reg16 |= (1 << 6); - pci_write_config16(dev, SATA_MAP, reg16); - - /* Initialize AHCI memory-mapped space */ - abar = (u32 *)pci_read_config32(dev, PCI_BASE_ADDRESS_5); - printk(BIOS_DEBUG, "ABAR: %p\n", abar); - - /* Enable AHCI Mode */ - reg32 = read32(abar + 0x01); - reg32 |= (1 << 31); - write32(abar + 0x01, reg32); - } else { - printk(BIOS_DEBUG, "SATA: Controller in plain mode.\n"); - } - - /* Spin up the drives as early as possible via the Port Enable */ - reg16 = pci_read_config16(dev, SATA_PSC); - reg16 &= ~0x3f; - pci_write_config16(dev, SATA_PSC, reg16); - reg16 = pci_read_config16(dev, SATA_PSC); - reg16 |= 0x3f; - pci_write_config16(dev, SATA_PSC, reg16); - -} - -static void sata_enable(struct device *dev) -{ -} - -static struct pci_operations sata_pci_ops = { - .set_subsystem = pci_dev_set_subsystem, -}; - -static struct device_operations sata_ops = { - .read_resources = pci_dev_read_resources, - .set_resources = pci_dev_set_resources, - .enable_resources = pci_dev_enable_resources, - .init = sata_init, - .enable = sata_enable, - .scan_bus = 0, - .ops_pci = &sata_pci_ops, -}; - -static const unsigned short pci_device_ids[] = { 0x1f20, 0x1f21, 0x1f22, 0x1f23, - 0x1f30, 0x1f31, 0x1f32, 0x1f33, - 0 }; - -static const struct pci_driver soc_sata __pci_driver = { - .ops = &sata_ops, - .vendor = PCI_VENDOR_ID_INTEL, - .devices = pci_device_ids, -}; diff --git a/src/southbridge/intel/fsp_rangeley/smbus.c b/src/southbridge/intel/fsp_rangeley/smbus.c deleted file mode 100644 index 610ce0cb85..0000000000 --- a/src/southbridge/intel/fsp_rangeley/smbus.c +++ /dev/null @@ -1,81 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2008-2009 coresystems GmbH - * Copyright (C) 2013 Sage Electronic Engineering, LLC. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include -#include -#include -#include -#include "soc.h" - -static int lsmbus_read_byte(struct device *dev, u8 address) -{ - u16 device; - struct resource *res; - struct bus *pbus; - - device = dev->path.i2c.device; - pbus = get_pbus_smbus(dev); - res = find_resource(pbus->dev, 0x20); - - return do_smbus_read_byte(res->base, device, address); -} - -static struct smbus_bus_operations lops_smbus_bus = { - .read_byte = lsmbus_read_byte, -}; - -static struct pci_operations smbus_pci_ops = { - .set_subsystem = pci_dev_set_subsystem, -}; - -static void rangeley_smbus_read_resources(struct device *dev) -{ - struct resource *res; - - /* - * The SMBus has two BARS. - * BAR0 - MMIO, not used at boot time - * BAR4 - IO, Used to talk to the SMBUS during boot, so we maintain - * the default setting in the resource allocator. - */ - - res = pci_get_resource(dev, PCI_BASE_ADDRESS_0); - - res = new_resource(dev, PCI_BASE_ADDRESS_4); - res->base = SMBUS_IO_BASE; - res->size = 32; - res->flags = IORESOURCE_IO | IORESOURCE_FIXED | IORESOURCE_RESERVE | - IORESOURCE_STORED | IORESOURCE_ASSIGNED; - -} - -static struct device_operations smbus_ops = { - .read_resources = rangeley_smbus_read_resources, - .set_resources = pci_dev_set_resources, - .enable_resources = pci_dev_enable_resources, - .init = 0, - .scan_bus = scan_smbus, - .ops_smbus_bus = &lops_smbus_bus, - .ops_pci = &smbus_pci_ops, -}; - -static const struct pci_driver rangeley_smbus __pci_driver = { - .ops = &smbus_ops, - .vendor = PCI_VENDOR_ID_INTEL, - .device = 0x1F3C, -}; diff --git a/src/southbridge/intel/fsp_rangeley/soc.c b/src/southbridge/intel/fsp_rangeley/soc.c deleted file mode 100644 index 3512f196d3..0000000000 --- a/src/southbridge/intel/fsp_rangeley/soc.c +++ /dev/null @@ -1,96 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2008-2009 coresystems GmbH - * Copyright (C) 2012 The Chromium OS Authors. All rights reserved. - * Copyright (C) 2013 Sage Electronic Engineering, LLC. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include -#include - -#include "soc.h" - -static int soc_revision_id = -1; -static int soc_type = -1; - -int soc_silicon_revision(void) -{ - if (soc_revision_id < 0) - soc_revision_id = pci_read_config8( - pcidev_on_root(0x1f, 0), - PCI_REVISION_ID); - return soc_revision_id; -} - -int soc_silicon_type(void) -{ - if (soc_type < 0) - soc_type = pci_read_config8( - pcidev_on_root(0x1f, 0), - PCI_DEVICE_ID + 1); - return soc_type; -} - -int soc_silicon_supported(int type, int rev) -{ - int cur_type = soc_silicon_type(); - int cur_rev = soc_silicon_revision(); - - switch (type) { - case SOC_TYPE_RANGELEY: - if (cur_type == SOC_TYPE_RANGELEY && cur_rev >= rev) - return 1; - } - - return 0; -} - -/* Set bit in Function Disable register to hide this device */ -static void soc_hide_devfn(unsigned int devfn) -{ -/* TODO Function Disable. */ -} - - - - -void soc_enable(struct device *dev) -{ - u32 reg32; - - if (!dev->enabled) { - printk(BIOS_DEBUG, "%s: Disabling device\n", dev_path(dev)); - - /* Ensure memory, IO, and bus master are all disabled */ - reg32 = pci_read_config32(dev, PCI_COMMAND); - reg32 &= ~(PCI_COMMAND_MASTER | - PCI_COMMAND_MEMORY | PCI_COMMAND_IO); - pci_write_config32(dev, PCI_COMMAND, reg32); - - /* Hide this device if possible */ - soc_hide_devfn(dev->path.pci.devfn); - } else { - /* Enable SERR */ - reg32 = pci_read_config32(dev, PCI_COMMAND); - reg32 |= PCI_COMMAND_SERR; - pci_write_config32(dev, PCI_COMMAND, reg32); - } -} - -struct chip_operations southbridge_intel_fsp_rangeley_ops = { - CHIP_NAME("Intel Rangeley Southbridge") - .enable_dev = soc_enable, -}; diff --git a/src/southbridge/intel/fsp_rangeley/soc.h b/src/southbridge/intel/fsp_rangeley/soc.h deleted file mode 100644 index ce5e056514..0000000000 --- a/src/southbridge/intel/fsp_rangeley/soc.h +++ /dev/null @@ -1,401 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2008-2009 coresystems GmbH - * Copyright (C) 2012 The Chromium OS Authors. All rights reserved. - * Copyright (C) 2013-2014 Sage Electronic Engineering, LLC. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef SOUTHBRIDGE_INTEL_RANGELEY_SOC_H -#define SOUTHBRIDGE_INTEL_RANGELEY_SOC_H - -#include - -/* SOC types */ -#define SOC_TYPE_RANGELEY 0x1F - -/* - * It does not matter where we put the SMBus I/O base, as long as we - * keep it consistent and don't interfere with other devices. Stage2 - * will relocate this anyways. - * Our solution is to have SMB initialization move the I/O to SMBUS_IO_BASE - * again. But handling static BARs is a generic problem that should be - * solved in the device allocator. - */ - -/* Southbridge internal device IO BARs (Set to match FSP settings) */ -#define SMBUS_IO_BASE 0xefa0 -#define SMBUS_SLAVE_ADDR 0x24 -#define DEFAULT_GPIOBASE 0x0500 -#define DEFAULT_ABASE 0x0400 - -/* Southbridge internal device MEM BARs (Set to match FSP settings) */ -#define DEFAULT_IBASE 0xfed08000 -#define DEFAULT_PBASE 0xfed03000 - -#include - -#ifndef __ACPI__ -#define DEBUG_PERIODIC_SMIS 0 - -void intel_soc_finalize_smm(void); - -#if !defined(__ROMCC__) -#include -void soc_enable(struct device *dev); -void acpi_fill_in_fadt(acpi_fadt_t *fadt, acpi_facs_t *facs, void *dsdt); -#endif - -int soc_silicon_revision(void); -int soc_silicon_type(void); -int soc_silicon_supported(int type, int rev); - - -void soc_log_state(void); -void enable_smbus(void); -void enable_usb_bar(void); -void rangeley_sb_early_initialization(void); - -#if ENV_ROMSTAGE -int smbus_read_byte(unsigned int device, unsigned int address); -#endif - -#define MAINBOARD_POWER_OFF 0 -#define MAINBOARD_POWER_ON 1 -#define MAINBOARD_POWER_KEEP 2 - -#define SOC_EHCI1_DEV PCI_DEV(0, 0x1d, 0) -#define PCIE_DEV_SLOT0 1 -#define PCIE_DEV_SLOT1 2 -#define PCIE_DEV_SLOT2 3 -#define PCIE_DEV_SLOT3 4 - -/* PCI Configuration Space (D31:F0): LPC */ -#define SOC_LPC_DEV PCI_DEV(0, 0x1f, 0) -#define SOC_LPC_DEVFN PCI_DEVFN(0x1f, 0) - - -/* Southbridge IO BARs */ -#define ABASE 0x40 /* IO BAR */ -#define PBASE 0x44 /* MEM BAR */ -#define GBASE 0x48 /* IO BAR */ -#define IOBASE 0x4C /* MEM BAR */ -#define IBASE 0x50 /* MEM BAR */ -#define SBASE 0x54 /* MEM BAR */ -#define MPBASE 0x58 /* MEM BAR */ -#define SET_BAR_ENABLE 0x02 - -/* Rangeley ILB defines */ -#define ILB_ACTL 0 -#define ILB_PIRQA_ROUT 0x8 -#define ILB_PIRQB_ROUT 0x9 -#define ILB_PIRQC_ROUT 0xA -#define ILB_PIRQD_ROUT 0xB -#define ILB_PIRQE_ROUT 0xC -#define ILB_PIRQF_ROUT 0xD -#define ILB_PIRQG_ROUT 0xE -#define ILB_PIRQH_ROUT 0xF -#define ILB_SERIRQ_CNTL 0x10 -#define ILB_IR00 0x20 -#define ILB_IR01 0x22 -#define ILB_IR02 0x24 -#define ILB_IR03 0x26 -#define ILB_IR04 0x28 -#define ILB_IR05 0x2A -#define ILB_IR06 0x2C -#define ILB_IR07 0x2E -#define ILB_IR08 0x30 -#define ILB_IR09 0x32 -#define ILB_IR10 0x34 -#define ILB_IR11 0x36 -#define ILB_IR12 0x38 -#define ILB_IR13 0x3A -#define ILB_IR14 0x3C -#define ILB_IR15 0x3E -#define ILB_IR16 0x40 -#define ILB_IR17 0x42 -#define ILB_IR18 0x44 -#define ILB_IR19 0x46 -#define ILB_IR20 0x48 -#define ILB_IR21 0x4A -#define ILB_IR22 0x4C -#define ILB_IR23 0x4E -#define ILB_IR24 0x50 -#define ILB_IR25 0x52 -#define ILB_IR26 0x54 -#define ILB_IR27 0x56 -#define ILB_IR28 0x58 -#define ILB_IR29 0x5A -#define ILB_IR30 0x5C -#define ILB_IR31 0x5E -#define ILB_OIC 0x60 - -/* PCI Configuration Space (D31:F2/5) */ -#define SOC_SATA_DEV PCI_DEV(0, 0x17, 0) -#define SOC_SATA2_DEV PCI_DEV(0, 0x18, 0) - -#define SATA_SIRI 0xa0 /* SATA Indexed Register Index */ -#define SATA_SIRD 0xa4 /* SATA Indexed Register Data */ -#define SATA_SP 0xd0 /* Scratchpad */ -#define SATA_MAP 0x90 -#define SATA_PSC 0x92 - -/* SATA IOBP Registers */ -#define SATA_IOBP_SP0G3IR 0xea000151 -#define SATA_IOBP_SP1G3IR 0xea000051 - -/* PCI Configuration Space (D31:F3): SMBus */ -#define SOC_SMBUS_DEV PCI_DEV(0, 0x1f, 3) -#define SMB_BASE 0x20 -#define HOSTC 0x40 -#define SMB_RCV_SLVA 0x09 - -/* HOSTC bits */ -#define I2C_EN (1 << 2) -#define SMB_SMI_EN (1 << 1) -#define HST_EN (1 << 0) - -/* Root Port configuration space hide */ -#define RPFN_HIDE(port) (1 << (((port) * 4) + 3)) -/* Get the function number assigned to a Root Port */ -#define RPFN_FNGET(reg,port) (((reg) >> ((port) * 4)) & 7) -/* Set the function number for a Root Port */ -#define RPFN_FNSET(port,func) (((func) & 7) << ((port) * 4)) -/* Root Port function number mask */ -#define RPFN_FNMASK(port) (7 << ((port) * 4)) - - -#define NOINT 0 -#define INTA 1 -#define INTB 2 -#define INTC 3 -#define INTD 4 - -#define DIR_IDR 12 /* Interrupt D Pin Offset */ -#define DIR_ICR 8 /* Interrupt C Pin Offset */ -#define DIR_IBR 4 /* Interrupt B Pin Offset */ -#define DIR_IAR 0 /* Interrupt A Pin Offset */ - -#define PIRQA 0 -#define PIRQB 1 -#define PIRQC 2 -#define PIRQD 3 -#define PIRQE 4 -#define PIRQF 5 -#define PIRQG 6 -#define PIRQH 7 - -/* IO Buffer Programming */ -#define IOBPIRI 0x2330 -#define IOBPD 0x2334 -#define IOBPS 0x2338 -#define IOBPS_RW_BX ((1 << 9)|(1 << 10)) -#define IOBPS_WRITE_AX ((1 << 9)|(1 << 10)) -#define IOBPS_READ_AX ((1 << 8)|(1 << 9)|(1 << 10)) - - - -#define DIR_ROUTE(x,a,b,c,d) \ - RCBA32(x) = (((d) << DIR_IDR) | ((c) << DIR_ICR) | \ - ((b) << DIR_IBR) | ((a) << DIR_IAR)) - -/* PBASE Registers */ -#define PMC_CFG 0x08 -#define SPS (1 << 5) -#define NO_REBOOT (1 << 4) -#define SX_ENT_TO_EN (1 << 3) -#define TIMING_T581 (1 << 0) - -#define GEN_PMCON1 0x20 -# define DISB (1 << 23) -# define MEM_SR (1 << 21) -# define SRS (1 << 20) -# define CTS (1 << 19) -# define MS4V (1 << 18) -# define PWR_FLR (1 << 16) -# define PME_B0_S5_DIS (1 << 15) -# define SUS_PWR_FLR (1 << 14) -# define WOL_EN_OVRD (1 << 13) -# define DIS_SLP_X_STRCH_SUS_UP (1 << 12) -# define GEN_RST_STS (1 << 9) -# define RPS (1 << 2) -# define AFTERG3_EN (1 << 0) - -/* Function Disable PBASE + 0x34 */ -#define PBASE_FUNC_DIS 0x34 -#define PBASE_DISABLE_QUICKASSIST (1 << 0) -#define PBASE_DISABLE_GBE(x) (1 << (12 + x)) -#define PBASE_DISABLE_SATA2 (1 << 22) -#define PBASE_DISABLE_EHCI (1 << 23) -#define PBASE_DISABLE_SATA3 (1 << 23) - -/* GPIOBASE */ -#define GPIO_SC_USE_SEL 0x00 -#define GPIO_SC_IO_SEL 0x04 -#define GPIO_SC_GP_LVL 0x08 -#define GPIO_SC_TPE 0x0c -#define GPIO_SC_TNE 0x10 -#define GPIO_SC_TS 0x14 -#define GPIO_SUS_USE_SEL 0x80 -#define GPIO_SUS_IO_SEL 0x84 -#define GPIO_SUS_GP_LVL 0x88 -#define GPIO_SUS_TPE 0x8c -#define GPIO_SUS_TNE 0x90 -#define GPIO_SUS_TS 0x94 -#define GPIO_SUS_WE 0x98 - -/* IOBASE */ -#define CFIO_PAD_CONF0 0x00 -#define CFIO_PAD_CONF1 0x04 -#define CFIO_PAD_VAL 0x08 -#define CFIO_PAD_DFT 0x0C - -/* ACPI BASE */ -#define PM1_STS 0x00 -#define WAK_STS (1 << 15) -#define PCIEXPWAK_STS (1 << 14) -#define PRBTNOR_STS (1 << 11) -#define RTC_STS (1 << 10) -#define PWRBTN_STS (1 << 8) -#define GBL_STS (1 << 5) -#define BM_STS (1 << 4) -#define TMROF_STS (1 << 0) -#define PM1_EN 0x02 -#define PCIEXPWAK_DIS (1 << 14) -#define RTC_EN (1 << 10) -#define PWRBTN_EN (1 << 8) -#define GBL_EN (1 << 5) -#define TMROF_EN (1 << 0) -#define PM1_CNT 0x04 -#define GBL_RLS (1 << 2) -#define BM_RLD (1 << 1) -#define SCI_EN (1 << 0) -#define PM1_TMR 0x08 -#define PROC_CNT 0x10 -#define LV2 0x14 -#define LV3 0x15 -#define LV4 0x16 -#define PM2_CNT 0x50 // mobile only -#define GPE0_STS 0x20 -#define PME_B0_STS (1 << 13) -#define PME_STS (1 << 11) -#define BATLOW_STS (1 << 10) -#define PCI_EXP_STS (1 << 9) -#define RI_STS (1 << 8) -#define SMB_WAK_STS (1 << 7) -#define TCOSCI_STS (1 << 6) -#define SWGPE_STS (1 << 2) -#define HOT_PLUG_STS (1 << 1) -#define GPE0_EN 0x28 -#define PME_B0_EN (1 << 13) -#define PME_EN (1 << 11) -#define TCOSCI_EN (1 << 6) -#define SMI_EN 0x30 -#define INTEL_USB2_EN (1 << 18) // Intel-Specific USB2 SMI logic -#define LEGACY_USB2_EN (1 << 17) // Legacy USB2 SMI logic -#define PERIODIC_EN (1 << 14) // SMI on PERIODIC_STS in SMI_STS -#define TCO_EN (1 << 13) // Enable TCO Logic (BIOSWE et al) -#define MCSMI_EN (1 << 11) // Trap microcontroller range access -#define BIOS_RLS (1 << 7) // asserts SCI on bit set -#define SWSMI_TMR_EN (1 << 6) // start software smi timer on bit set -#define APMC_EN (1 << 5) // Writes to APM_CNT cause SMI# -#define SLP_SMI_EN (1 << 4) // Write to SLP_EN in PM1_CNT asserts SMI# -#define LEGACY_USB_EN (1 << 3) // Legacy USB circuit SMI logic -#define BIOS_EN (1 << 2) // Assert SMI# on setting GBL_RLS bit -#define EOS (1 << 1) // End of SMI (deassert SMI#) -#define GBL_SMI_EN (1 << 0) // SMI# generation at all? -#define SMI_STS 0x34 -#define ALT_GP_SMI_EN 0x38 -#define ALT_GP_SMI_STS 0x3a -#define GPE_CNTL 0x42 -#define DEVACT_STS 0x44 -#define PM2A_CNT_BLK 0x50 -#define SS_CNT 0x50 -#define C3_RES 0x54 -#define TCO1_STS 0x64 -#define DMISCI_STS (1 << 9) -#define TCO2_STS 0x66 -#define TCO1_CNT 0x68 -#define TCO_TMR_HALT (1 << 11) -#define TCO_LOCK (1 << 12) - -/* - * SPI Opcode Menu setup for SPIBAR lockdown - * should support most common flash chips. - */ - -#define SPI_OPMENU_0 0x01 /* WRSR: Write Status Register */ -#define SPI_OPTYPE_0 0x01 /* Write, no address */ - -#define SPI_OPMENU_1 0x02 /* BYPR: Byte Program */ -#define SPI_OPTYPE_1 0x03 /* Write, address required */ - -#define SPI_OPMENU_2 0x03 /* READ: Read Data */ -#define SPI_OPTYPE_2 0x02 /* Read, address required */ - -#define SPI_OPMENU_3 0x05 /* RDSR: Read Status Register */ -#define SPI_OPTYPE_3 0x00 /* Read, no address */ - -#define SPI_OPMENU_4 0x20 /* SE20: Sector Erase 0x20 */ -#define SPI_OPTYPE_4 0x03 /* Write, address required */ - -#define SPI_OPMENU_5 0x9f /* RDID: Read ID */ -#define SPI_OPTYPE_5 0x00 /* Read, no address */ - -#define SPI_OPMENU_6 0xd8 /* BED8: Block Erase 0xd8 */ -#define SPI_OPTYPE_6 0x03 /* Write, address required */ - -#define SPI_OPMENU_7 0x0b /* FAST: Fast Read */ -#define SPI_OPTYPE_7 0x02 /* Read, address required */ - -#define SPI_OPMENU_UPPER ((SPI_OPMENU_7 << 24) | (SPI_OPMENU_6 << 16) | \ - (SPI_OPMENU_5 << 8) | SPI_OPMENU_4) -#define SPI_OPMENU_LOWER ((SPI_OPMENU_3 << 24) | (SPI_OPMENU_2 << 16) | \ - (SPI_OPMENU_1 << 8) | SPI_OPMENU_0) - -#define SPI_OPTYPE ((SPI_OPTYPE_7 << 14) | (SPI_OPTYPE_6 << 12) | \ - (SPI_OPTYPE_5 << 10) | (SPI_OPTYPE_4 << 8) | \ - (SPI_OPTYPE_3 << 6) | (SPI_OPTYPE_2 << 4) | \ - (SPI_OPTYPE_1 << 2) | (SPI_OPTYPE_0)) - -#define SPI_OPPREFIX ((0x50 << 8) | 0x06) /* EWSR and WREN */ - -#define SPIBAR_HSFS 0x04 /* SPI hardware sequence status */ -#define SPIBAR_HSFS_SCIP (1 << 5) /* SPI Cycle In Progress */ -#define SPIBAR_HSFS_AEL (1 << 2) /* SPI Access Error Log */ -#define SPIBAR_HSFS_FCERR (1 << 1) /* SPI Flash Cycle Error */ -#define SPIBAR_HSFS_FDONE (1 << 0) /* SPI Flash Cycle Done */ -#define SPIBAR_HSFC 0x06 /* SPI hardware sequence control */ -#define SPIBAR_HSFC_BYTE_COUNT(c) (((c - 1) & 0x3f) << 8) -#define SPIBAR_HSFC_CYCLE_READ (0 << 1) /* Read cycle */ -#define SPIBAR_HSFC_CYCLE_WRITE (2 << 1) /* Write cycle */ -#define SPIBAR_HSFC_CYCLE_ERASE (3 << 1) /* Erase cycle */ -#define SPIBAR_HSFC_GO (1 << 0) /* GO: start SPI transaction */ -#define SPIBAR_FADDR 0x08 /* SPI flash address */ -#define SPIBAR_FDATA(n) (0x3810 + (4 * n)) /* SPI flash data */ - -/* HPET Registers - Base is set in hardware to 0xFED00000 */ -#define HPET_GCID 0xFED00000 /* General Capabilities and ID */ -#define HPET_GCFG 0xFED00010 /* General Configuration */ -#define HPET_GIS 0xFED00020 /* General Interrupt Status */ -#define HPET_MCV 0xFED000F0 /* Main Counter Value */ -#define HPET_T0C 0xFED00100 /* Timer 0 Configuration and Capabilities */ -#define HPET_T0CV_L 0xFED00108 /* Lower Timer 0 Comparator Value */ -#define HPET_T0CV_U 0xFED0010C /* Upper Timer 0 Comparator Value */ -#define HPET_T1C 0xFED00120 /* Timer 1 Configuration and Capabilities */ -#define HPET_T1CV 0xFED00128 /* Timer 1 Comparator Value */ -#define HPET_T2C 0xFED00140 /* Timer 2 Configuration and Capabilities */ -#define HPET_T2CV 0xFED00148 /* Timer 2 Comparator Value */ - - -#endif /* __ACPI__ */ -#endif /* SOUTHBRIDGE_INTEL_RANGELEY_SOC_H */ diff --git a/src/southbridge/intel/fsp_rangeley/spi.c b/src/southbridge/intel/fsp_rangeley/spi.c deleted file mode 100644 index f58677ba27..0000000000 --- a/src/southbridge/intel/fsp_rangeley/spi.c +++ /dev/null @@ -1,712 +0,0 @@ -/* - * Copyright (c) 2011 The Chromium OS Authors. - * Copyright (C) 2013, Intel Corporation. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but without any warranty; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -/* This file is derived from the flashrom project. */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include - -static int ich_status_poll(u16 bitmask, int wait_til_set); - -typedef struct spi_slave ich_spi_slave; - -static int ichspi_lock = 0; - -typedef struct ich7_spi_regs { - uint16_t spis; - uint16_t spic; - uint32_t spia; - uint64_t spid[8]; - uint64_t _pad; - uint32_t bbar; - uint16_t preop; - uint16_t optype; - uint8_t opmenu[8]; -} __packed ich7_spi_regs; - -typedef struct ich9_spi_regs { - uint32_t bfpr; // 0 - uint16_t hsfs; // 4 - uint16_t hsfc; // 6 - uint32_t faddr; // 8 - uint32_t _reserved0; // 0xC - uint32_t fdata[16]; // 0x10 - uint32_t frap; // 0x50 - uint32_t freg[5]; // 0x54 - uint32_t _reserved1[3]; // 0x67 - uint32_t pr[5]; // 0x74 - uint32_t _reserved2[2]; // 0x88 - uint8_t ssfs; // 0x90 - uint8_t ssfc[3]; // 0x91 - uint16_t preop; // 0x94 - uint16_t optype; // 0x96 - uint8_t opmenu[8]; // 0x98 - uint32_t bbar; // 0xB0 - uint8_t _reserved3[12]; - uint32_t fdoc; - uint32_t fdod; - uint8_t _reserved4[8]; - uint32_t afc; - uint32_t lvscc; - uint32_t uvscc; - uint8_t _reserved5[4]; - uint32_t fpb; - uint8_t _reserved6[28]; - uint32_t srdl; - uint32_t srdc; - uint32_t srd; -} __packed ich9_spi_regs; - -typedef struct ich10_spi_regs { - uint32_t bfpr; - uint16_t hsfs; - uint16_t hsfc; - uint32_t faddr; - uint32_t _reserved0; - uint32_t fdata[16]; - uint32_t fracc; - uint32_t freg[5]; - uint32_t _reserved1[3]; - uint32_t pr[5]; - uint32_t _reserved2[2]; - uint8_t ssfs; - uint8_t ssfc[3]; - uint16_t preop; - uint16_t optype; - uint8_t opmenu[8]; - uint8_t _reserved3[16]; - uint32_t fdoc; - uint32_t fdod; - uint8_t _reserved4[8]; - uint32_t afc; - uint32_t lvscc; - uint32_t uvscc; - uint8_t _reserved5[4]; - uint32_t fpb; - uint8_t _reserved6[36]; - uint32_t scs; - uint32_t bcr; - uint32_t tcgc; -} __packed ich10_spi_regs; - -typedef struct ich_spi_controller { - int locked; - - uint8_t *opmenu; - int menubytes; - uint16_t *preop; - uint16_t *optype; - uint32_t *addr; - uint8_t *data; - unsigned int databytes; - uint8_t *status; - uint16_t *control; - uint32_t *bbar; - uint8_t *bcr; -} ich_spi_controller; - -static ich_spi_controller cntlr; - -enum { - SPIS_SCIP = 0x0001, - SPIS_GRANT = 0x0002, - SPIS_CDS = 0x0004, - SPIS_FCERR = 0x0008, - SSFS_AEL = 0x0010, - SPIS_LOCK = 0x8000, - SPIS_RESERVED_MASK = 0x7ff0, - SSFS_RESERVED_MASK = 0x7fe2 -}; - -enum { - SPIC_SCGO = 0x000002, - SPIC_ACS = 0x000004, - SPIC_SPOP = 0x000008, - SPIC_DBC = 0x003f00, - SPIC_DS = 0x004000, - SPIC_SME = 0x008000, - SSFC_SCF_MASK = 0x070000, - SSFC_RESERVED = 0xf80000 -}; - -enum { - HSFS_FDONE = 0x0001, - HSFS_FCERR = 0x0002, - HSFS_AEL = 0x0004, - HSFS_BERASE_MASK = 0x0018, - HSFS_BERASE_SHIFT = 3, - HSFS_SCIP = 0x0020, - HSFS_FDOPSS = 0x2000, - HSFS_FDV = 0x4000, - HSFS_FLOCKDN = 0x8000 -}; - -enum { - HSFC_FGO = 0x0001, - HSFC_FCYCLE_MASK = 0x0006, - HSFC_FCYCLE_SHIFT = 1, - HSFC_FDBC_MASK = 0x3f00, - HSFC_FDBC_SHIFT = 8, - HSFC_FSMIE = 0x8000 -}; - -enum { - BCR_BIOSWE = 0x0001, - BCR_BLE = 0x0002, - BCR_SRC_MASK = 0x000c, - BCR_SRC_SHIFT = 0x0002, - BCR_SRC_NO_PREF = 0x0000, - BCR_SRC_NO_PREF_CACHE = 0x0004, - BCR_SRC_EN_PREF_CACHE = 0x0008, - BCR_TSS = 0x0010, - BCR_SMMBWP = 0x0020, - BCR_RESERVED_MASK = 0xffc0 -}; - -enum { - SPI_OPCODE_TYPE_READ_NO_ADDRESS = 0, - SPI_OPCODE_TYPE_WRITE_NO_ADDRESS = 1, - SPI_OPCODE_TYPE_READ_WITH_ADDRESS = 2, - SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS = 3, -}; - -#if CONFIG(DEBUG_SPI_FLASH) - -static u8 readb_(const void *addr) -{ - u8 v = read8(addr); - printk(BIOS_DEBUG, "read %2.2x from %4.4x\n", - v, ((unsigned int) addr & 0xffff) - 0xf020); - return v; -} - -static u16 readw_(const void *addr) -{ - u16 v = read16(addr); - printk(BIOS_DEBUG, "read %4.4x from %4.4x\n", - v, ((unsigned int) addr & 0xffff) - 0xf020); - return v; -} - -static u32 readl_(const void *addr) -{ - u32 v = read32(addr); - printk(BIOS_DEBUG, "read %8.8x from %4.4x\n", - v, ((unsigned int) addr & 0xffff) - 0xf020); - return v; -} - -static void writeb_(u8 b, const void *addr) -{ - write8(addr, b); - printk(BIOS_DEBUG, "wrote %2.2x to %4.4x\n", - b, ((unsigned int) addr & 0xffff) - 0xf020); -} - -static void writew_(u16 b, const void *addr) -{ - write16(addr, b); - printk(BIOS_DEBUG, "wrote %4.4x to %4.4x\n", - b, ((unsigned int) addr & 0xffff) - 0xf020); -} - -static void writel_(u32 b, const void *addr) -{ - write32((unsigned long)addr, b); - printk(BIOS_DEBUG, "wrote %8.8x to %4.4x\n", - b, ((unsigned int) addr & 0xffff) - 0xf020); -} - -#else /* CONFIG_DEBUG_SPI_FLASH ^^^ enabled vvv NOT enabled */ - -#define readb_(a) read8(a) -#define readw_(a) read16(a) -#define readl_(a) read32(a) -#define writeb_(val, addr) write8(addr, val) -#define writew_(val, addr) write16(addr, val) -#define writel_(val, addr) write32(addr, val) - -#endif /* CONFIG_DEBUG_SPI_FLASH ^^^ NOT enabled */ - -static void write_reg(const void *value, void *dest, uint32_t size) -{ - const uint8_t *bvalue = value; - uint8_t *bdest = dest; - - while (size >= 4) { - writel_(*(const uint32_t *)bvalue, bdest); - bdest += 4; bvalue += 4; size -= 4; - } - while (size) { - writeb_(*bvalue, bdest); - bdest++; bvalue++; size--; - } -} - -static void read_reg(const void *src, void *value, uint32_t size) -{ - const uint8_t *bsrc = src; - uint8_t *bvalue = value; - - while (size >= 4) { - *(uint32_t *)bvalue = readl_(bsrc); - bsrc += 4; bvalue += 4; size -= 4; - } - while (size) { - *bvalue = readb_(bsrc); - bsrc++; bvalue++; size--; - } -} - -static void ich_set_bbar(uint32_t minaddr) -{ - const uint32_t bbar_mask = 0x00ffff00; - uint32_t ichspi_bbar; - - if (cntlr.bbar == NULL) - return; - - minaddr &= bbar_mask; - ichspi_bbar = readl_(cntlr.bbar) & ~bbar_mask; - ichspi_bbar |= minaddr; - writel_(ichspi_bbar, cntlr.bbar); -} - -/* - * Check if this device ID matches one of supported Intel SOC devices. - * - * Return the ICH version if there is a match, or zero otherwise. - */ -static inline int get_ich_version(uint16_t device_id) -{ - - if ((device_id >= PCI_DEVICE_ID_INTEL_RANGELEY_LPC_MIN && - device_id <= PCI_DEVICE_ID_INTEL_RANGELEY_LPC_MAX)) - return 10; - - return 0; -} - -#define MENU_BYTES member_size(struct ich10_spi_regs, opmenu) - -void spi_init(void) -{ - int ich_version = 0; - uint8_t bios_cntl; - uint32_t ids; - uint16_t vendor_id, device_id; - -#ifdef __SIMPLE_DEVICE__ - pci_devfn_t dev = PCI_DEV(0, 31, 0); -#else - struct device *dev = pcidev_on_root(31, 0); -#endif - ids = pci_read_config32(dev, 0); - vendor_id = ids; - device_id = (ids >> 16); - - if (vendor_id != PCI_VENDOR_ID_INTEL) { - printk(BIOS_DEBUG, "SPI: No SOC found.\n"); - return; - } - - ich_version = get_ich_version(device_id); - - if (!ich_version) { - printk(BIOS_DEBUG, "SPI: No known SOC found.\n"); - return; - } - - switch (ich_version) { - case 10: - { - uint8_t *spibase; /* SPI Base Address */ - uint32_t sbase; /* SPI Base Address Register */ - sbase = pci_read_config32(dev, 0x54); - /* Bits 31-9 are the base address, 8-4 are reserved, 3-0 are used. */ - spibase = (uint8_t *)(sbase & 0xffffff00); - ich10_spi_regs *ich10_spi = - (ich10_spi_regs *)(spibase); - ichspi_lock = readw_(&ich10_spi->hsfs) & HSFS_FLOCKDN; - cntlr.opmenu = ich10_spi->opmenu; - cntlr.menubytes = sizeof(ich10_spi->opmenu); - cntlr.optype = &ich10_spi->optype; - cntlr.addr = &ich10_spi->faddr; - cntlr.data = (uint8_t *)ich10_spi->fdata; - cntlr.databytes = sizeof(ich10_spi->fdata); - cntlr.status = &ich10_spi->ssfs; - cntlr.control = (uint16_t *)ich10_spi->ssfc; - cntlr.bbar = NULL; - cntlr.preop = &ich10_spi->preop; - cntlr.bcr = (uint8_t *)&ich10_spi->bcr; - break; - } - default: - printk(BIOS_DEBUG, "ICH SPI: Unrecognized ICH version %d.\n", ich_version); - } - - ich_set_bbar(0); - - /* Disable the BIOS write protect so write commands are allowed. */ - switch (ich_version) { - case 10: - { - /* Deassert SMM BIOS write protect(SMM BWP) and assert enable flash write(BIOSWE) */ - bios_cntl = readb_(cntlr.bcr); - bios_cntl &= ~BCR_SMMBWP; - bios_cntl |= BCR_BIOSWE; - writeb_(bios_cntl, cntlr.bcr); - break; - } - - default: - break; - } -} - -typedef struct spi_transaction { - const uint8_t *out; - uint32_t bytesout; - uint8_t *in; - uint32_t bytesin; - uint8_t type; - uint8_t opcode; - uint32_t offset; -} spi_transaction; - -static inline void spi_use_out(spi_transaction *trans, unsigned int bytes) -{ - trans->out += bytes; - trans->bytesout -= bytes; -} - -static inline void spi_use_in(spi_transaction *trans, unsigned int bytes) -{ - trans->in += bytes; - trans->bytesin -= bytes; -} - -static void spi_setup_type(spi_transaction *trans) -{ - trans->type = 0xFF; - - /* Try to guess spi type from read/write sizes. */ - if (trans->bytesin == 0) { - if (trans->bytesout > 4) - /* - * If bytesin = 0 and bytesout > 4, we presume this is - * a write data operation, which is accompanied by an - * address. - */ - trans->type = SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS; - else - trans->type = SPI_OPCODE_TYPE_WRITE_NO_ADDRESS; - return; - } - - if (trans->bytesout == 1) { /* and bytesin is > 0 */ - trans->type = SPI_OPCODE_TYPE_READ_NO_ADDRESS; - return; - } - - if (trans->bytesout == 4) { /* and bytesin is > 0 */ - trans->type = SPI_OPCODE_TYPE_READ_WITH_ADDRESS; - } - - /* Fast read command is called with 5 bytes instead of 4 */ - if (trans->out[0] == SPI_OPCODE_FAST_READ && trans->bytesout == 5) { - trans->type = SPI_OPCODE_TYPE_READ_WITH_ADDRESS; - --trans->bytesout; - } -} - -static int spi_setup_opcode(spi_transaction *trans) -{ - uint16_t optypes; - uint8_t opmenu[MENU_BYTES]; - - trans->opcode = trans->out[0]; - spi_use_out(trans, 1); - if (!ichspi_lock) { - /* The lock is off, so just use index 0. */ - writeb_(trans->opcode, cntlr.opmenu); - optypes = readw_(cntlr.optype); - optypes = (optypes & 0xfffc) | (trans->type & 0x3); - writew_(optypes, cntlr.optype); - return 0; - } else { - /* The lock is on. See if what we need is on the menu. */ - uint8_t optype; - uint16_t opcode_index; - - /* Write Enable is handled as atomic prefix */ - if (trans->opcode == SPI_OPCODE_WREN) - return 0; - - read_reg(cntlr.opmenu, opmenu, sizeof(opmenu)); - for (opcode_index = 0; opcode_index < ARRAY_SIZE(opmenu); opcode_index++) { - if (opmenu[opcode_index] == trans->opcode) - break; - } - - if (opcode_index == ARRAY_SIZE(opmenu)) { - printk(BIOS_DEBUG, "ICH SPI: Opcode %x not found\n", - trans->opcode); - return -1; - } - - optypes = readw_(cntlr.optype); - optype = (optypes >> (opcode_index * 2)) & 0x3; - if (trans->type == SPI_OPCODE_TYPE_WRITE_NO_ADDRESS && - optype == SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS && - trans->bytesout >= 3) { - /* We guessed wrong earlier. Fix it up. */ - trans->type = optype; - } - if (optype != trans->type) { - printk(BIOS_DEBUG, "ICH SPI: Transaction doesn't fit type %d\n", - optype); - return -1; - } - return opcode_index; - } -} - -static int spi_setup_offset(spi_transaction *trans) -{ - /* Separate the SPI address and data. */ - switch (trans->type) { - case SPI_OPCODE_TYPE_READ_NO_ADDRESS: - case SPI_OPCODE_TYPE_WRITE_NO_ADDRESS: - return 0; - case SPI_OPCODE_TYPE_READ_WITH_ADDRESS: - case SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS: - trans->offset = ((uint32_t)trans->out[0] << 16) | - ((uint32_t)trans->out[1] << 8) | - ((uint32_t)trans->out[2] << 0); - spi_use_out(trans, 3); - return 1; - default: - printk(BIOS_DEBUG, "Unrecognized SPI transaction type %#x\n", trans->type); - return -1; - } -} - -/* - * Wait for up to 60ms til status register bit(s) turn 1 (in case wait_til_set - * below is True) or 0. In case the wait was for the bit(s) to set - write - * those bits back, which would cause resetting them. - * - * Return the last read status value on success or -1 on failure. - */ -static int ich_status_poll(u16 bitmask, int wait_til_set) -{ - int timeout = 60000; /* This will result in 600 ms */ - u16 status = 0; - - while (timeout--) { - status = readw_(cntlr.status); - if (wait_til_set ^ ((status & bitmask) == 0)) { - if (wait_til_set) - writew_((status & bitmask), cntlr.status); - return status; - } - udelay(10); - } - - printk(BIOS_DEBUG, "ICH SPI: SCIP timeout, read %x, expected %x\n", - status, bitmask); - return -1; -} - -static int spi_ctrlr_xfer(const struct spi_slave *slave, const void *dout, - size_t bytesout, void *din, size_t bytesin) -{ - uint16_t control; - int16_t opcode_index; - int with_address; - int status; - - spi_transaction trans = { - dout, bytesout, - din, bytesin, - 0xff, 0xff, 0 - }; - - /* There has to always at least be an opcode. */ - if (!bytesout || !dout) { - printk(BIOS_DEBUG, "ICH SPI: No opcode for transfer\n"); - return -1; - } - /* Make sure if we read something we have a place to put it. */ - if (bytesin != 0 && !din) { - printk(BIOS_DEBUG, "ICH SPI: Read but no target buffer\n"); - return -1; - } - - if (ich_status_poll(SPIS_SCIP, 0) == -1) - return -1; - - writew_(SPIS_CDS | SPIS_FCERR, cntlr.status); - - spi_setup_type(&trans); - if ((opcode_index = spi_setup_opcode(&trans)) < 0) - return -1; - if ((with_address = spi_setup_offset(&trans)) < 0) - return -1; - - if (!ichspi_lock && trans.opcode == SPI_OPCODE_WREN) { - /* - * Treat Write Enable as Atomic Pre-Op if possible - * in order to prevent the Management Engine from - * issuing a transaction between WREN and DATA. - */ - writew_(trans.opcode, cntlr.preop); - return 0; - } - - /* Preset control fields */ - control = SPIC_SCGO | ((opcode_index & 0x07) << 4); - - /* Issue atomic preop cycle if needed */ - if (readw_(cntlr.preop)) - control |= SPIC_ACS; - - if (!trans.bytesout && !trans.bytesin) { - /* SPI addresses are 24 bit only */ - if (with_address) - writel_(trans.offset & 0x00FFFFFF, cntlr.addr); - - /* - * This is a 'no data' command (like Write Enable), its - * bitesout size was 1, decremented to zero while executing - * spi_setup_opcode() above. Tell the chip to send the - * command. - */ - writew_(control, cntlr.control); - - /* wait for the result */ - status = ich_status_poll(SPIS_CDS | SPIS_FCERR, 1); - if (status == -1) - return -1; - - if (status & SPIS_FCERR) { - printk(BIOS_DEBUG, "ICH SPI: Command transaction error\n"); - return -1; - } - - goto spi_xfer_exit; - } - - /* - * Check if this is a write command attempting to transfer more bytes - * than the controller can handle. Iterations for writes are not - * supported here because each SPI write command needs to be preceded - * and followed by other SPI commands, and this sequence is controlled - * by the SPI chip driver. - */ - if (trans.bytesout > cntlr.databytes) { - printk(BIOS_DEBUG, "ICH SPI: Too much to write. Does your SPI chip driver use" - " spi_crop_chunk()?\n"); - return -1; - } - - /* - * Read or write up to databytes bytes at a time until everything has - * been sent. - */ - while (trans.bytesout || trans.bytesin) { - uint32_t data_length; - - /* SPI addresses are 24 bit only */ - writel_(trans.offset & 0x00FFFFFF, cntlr.addr); - - if (trans.bytesout) - data_length = min(trans.bytesout, cntlr.databytes); - else - data_length = min(trans.bytesin, cntlr.databytes); - - /* Program data into FDATA0 to N */ - if (trans.bytesout) { - write_reg(trans.out, cntlr.data, data_length); - spi_use_out(&trans, data_length); - if (with_address) - trans.offset += data_length; - } - - /* Add proper control fields' values */ - control &= ~((cntlr.databytes - 1) << 8); - control |= SPIC_DS; - control |= (data_length - 1) << 8; - - /* write it */ - writew_(control, cntlr.control); - - /* Wait for Cycle Done Status or Flash Cycle Error. */ - status = ich_status_poll(SPIS_CDS | SPIS_FCERR, 1); - if (status == -1) - return -1; - - if (status & SPIS_FCERR) { - printk(BIOS_DEBUG, "ICH SPI: Data transaction error\n"); - return -1; - } - - if (trans.bytesin) { - read_reg(cntlr.data, trans.in, data_length); - spi_use_in(&trans, data_length); - if (with_address) - trans.offset += data_length; - } - } - -spi_xfer_exit: - /* Clear atomic preop now that xfer is done */ - writew_(0, cntlr.preop); - - return 0; -} - -static int xfer_vectors(const struct spi_slave *slave, - struct spi_op vectors[], size_t count) -{ - return spi_flash_vector_helper(slave, vectors, count, spi_ctrlr_xfer); -} - -static const struct spi_ctrlr spi_ctrlr = { - .xfer_vector = xfer_vectors, - .max_xfer_size = member_size(ich10_spi_regs, fdata), -}; - -const struct spi_ctrlr_buses spi_ctrlr_bus_map[] = { - { - .ctrlr = &spi_ctrlr, - .bus_start = 0, - .bus_end = 0, - }, -}; - -const size_t spi_ctrlr_bus_map_count = ARRAY_SIZE(spi_ctrlr_bus_map); diff --git a/src/vendorcode/intel/Kconfig b/src/vendorcode/intel/Kconfig index f341cfd7c5..027f12b66e 100644 --- a/src/vendorcode/intel/Kconfig +++ b/src/vendorcode/intel/Kconfig @@ -17,7 +17,6 @@ config FSP_VENDORCODE_HEADER_PATH string default "fsp1_0/baytrail" if SOC_INTEL_FSP_BAYTRAIL - default "fsp1_0/rangeley" if CPU_INTEL_FSP_MODEL_406DX config UEFI_2_4_BINDING def_bool n diff --git a/src/vendorcode/intel/fsp1_0/rangeley/include/fspapi.h b/src/vendorcode/intel/fsp1_0/rangeley/include/fspapi.h deleted file mode 100644 index 5009246db4..0000000000 --- a/src/vendorcode/intel/fsp1_0/rangeley/include/fspapi.h +++ /dev/null @@ -1,67 +0,0 @@ -/** - -Copyright (C) 2013, Intel Corporation - -Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - -* Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. -* Redistributions in binary form must reproduce the above copyright notice, this - list of conditions and the following disclaimer in the documentation and/or - other materials provided with the distribution. -* Neither the name of Intel Corporation nor the names of its contributors may - be used to endorse or promote products derived from this software without - specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE - LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF - THE POSSIBILITY OF SUCH DAMAGE. - -**/ - -#ifndef _FSP_API_H_ -#define _FSP_API_H_ - -#include - -#pragma pack(1) - -typedef VOID (* CONTINUATION_PROC)(EFI_STATUS Status, VOID *HobListPtr); - -typedef struct { - VOID *NvsBufferPtr; - VOID *RtBufferPtr; - CONTINUATION_PROC ContinuationFunc; -} FSP_INIT_PARAMS; - -typedef struct { - UINT32 *StackTop; - UINT32 BootMode; /* Refer to boot mode defined in MdePkg\Include\Pi\PiBootMode.h */ - VOID *UpdDataRgnPtr; - UINT32 Reserved[7]; -} FSP_INIT_RT_COMMON_BUFFER; - -typedef enum { - EnumInitPhaseAfterPciEnumeration = 0x20, - EnumInitPhaseReadyToBoot = 0x40 -} FSP_INIT_PHASE; - -typedef struct { - FSP_INIT_PHASE Phase; -} NOTIFY_PHASE_PARAMS; - -#pragma pack() - -typedef FSP_STATUS (FSPAPI *FSP_FSP_INIT) (FSP_INIT_PARAMS *FspInitParamPtr); -typedef FSP_STATUS (FSPAPI *FSP_NOTFY_PHASE) (NOTIFY_PHASE_PARAMS *NotifyPhaseParamPtr); - -#endif /* _FSP_API_H_ */ diff --git a/src/vendorcode/intel/fsp1_0/rangeley/include/fspbootmode.h b/src/vendorcode/intel/fsp1_0/rangeley/include/fspbootmode.h deleted file mode 100644 index 16cddf073d..0000000000 --- a/src/vendorcode/intel/fsp1_0/rangeley/include/fspbootmode.h +++ /dev/null @@ -1,54 +0,0 @@ -/** @file - -Copyright (C) 2013, Intel Corporation - -Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - -* Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. -* Redistributions in binary form must reproduce the above copyright notice, this - list of conditions and the following disclaimer in the documentation and/or - other materials provided with the distribution. -* Neither the name of Intel Corporation nor the names of its contributors may - be used to endorse or promote products derived from this software without - specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE - LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF - THE POSSIBILITY OF SUCH DAMAGE. - -**/ - -#ifndef __PI_BOOT_MODE_H__ -#define __PI_BOOT_MODE_H__ - -/// -/// EFI boot mode -/// -typedef UINT32 EFI_BOOT_MODE; - -// -// 0x21 - 0xf..f are reserved. -// -#define BOOT_WITH_FULL_CONFIGURATION 0x00 -#define BOOT_WITH_MINIMAL_CONFIGURATION 0x01 -#define BOOT_ASSUMING_NO_CONFIGURATION_CHANGES 0x02 -#define BOOT_WITH_FULL_CONFIGURATION_PLUS_DIAGNOSTICS 0x03 -#define BOOT_WITH_DEFAULT_SETTINGS 0x04 -#define BOOT_ON_S4_RESUME 0x05 -#define BOOT_ON_S5_RESUME 0x06 -#define BOOT_ON_S2_RESUME 0x10 -#define BOOT_ON_S3_RESUME 0x11 -#define BOOT_ON_FLASH_UPDATE 0x12 -#define BOOT_IN_RECOVERY_MODE 0x20 - -#endif diff --git a/src/vendorcode/intel/fsp1_0/rangeley/include/fspffs.h b/src/vendorcode/intel/fsp1_0/rangeley/include/fspffs.h deleted file mode 100644 index 9e8244dc17..0000000000 --- a/src/vendorcode/intel/fsp1_0/rangeley/include/fspffs.h +++ /dev/null @@ -1,507 +0,0 @@ -/** @file - -Copyright (C) 2013, Intel Corporation - -Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - -* Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. -* Redistributions in binary form must reproduce the above copyright notice, this - list of conditions and the following disclaimer in the documentation and/or - other materials provided with the distribution. -* Neither the name of Intel Corporation nor the names of its contributors may - be used to endorse or promote products derived from this software without - specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE - LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF - THE POSSIBILITY OF SUCH DAMAGE. - -**/ - -#ifndef __PI_FIRMWARE_FILE_H__ -#define __PI_FIRMWARE_FILE_H__ - -#include - -#pragma pack(1) -/// -/// Used to verify the integrity of the file. -/// -typedef union { - struct { - /// - /// The IntegrityCheck.Checksum.Header field is an 8-bit checksum of the file - /// header. The State and IntegrityCheck.Checksum.File fields are assumed - /// to be zero and the checksum is calculated such that the entire header sums to zero. - /// - UINT8 Header; - /// - /// If the FFS_ATTRIB_CHECKSUM (see definition below) bit of the Attributes - /// field is set to one, the IntegrityCheck.Checksum.File field is an 8-bit - /// checksum of the file data. - /// If the FFS_ATTRIB_CHECKSUM bit of the Attributes field is cleared to zero, - /// the IntegrityCheck.Checksum.File field must be initialized with a value of - /// 0xAA. The IntegrityCheck.Checksum.File field is valid any time the - /// EFI_FILE_DATA_VALID bit is set in the State field. - /// - UINT8 File; - } Checksum; - /// - /// This is the full 16 bits of the IntegrityCheck field. - /// - UINT16 Checksum16; -} EFI_FFS_INTEGRITY_CHECK; - -/// -/// FFS_FIXED_CHECKSUM is the checksum value used when the -/// FFS_ATTRIB_CHECKSUM attribute bit is clear. -/// -#define FFS_FIXED_CHECKSUM 0xAA - -typedef UINT8 EFI_FV_FILETYPE; -typedef UINT8 EFI_FFS_FILE_ATTRIBUTES; -typedef UINT8 EFI_FFS_FILE_STATE; - -/// -/// File Types Definitions -/// -#define EFI_FV_FILETYPE_ALL 0x00 -#define EFI_FV_FILETYPE_RAW 0x01 -#define EFI_FV_FILETYPE_FREEFORM 0x02 -#define EFI_FV_FILETYPE_SECURITY_CORE 0x03 -#define EFI_FV_FILETYPE_PEI_CORE 0x04 -#define EFI_FV_FILETYPE_DXE_CORE 0x05 -#define EFI_FV_FILETYPE_PEIM 0x06 -#define EFI_FV_FILETYPE_DRIVER 0x07 -#define EFI_FV_FILETYPE_COMBINED_PEIM_DRIVER 0x08 -#define EFI_FV_FILETYPE_APPLICATION 0x09 -#define EFI_FV_FILETYPE_SMM 0x0A -#define EFI_FV_FILETYPE_FIRMWARE_VOLUME_IMAGE 0x0B -#define EFI_FV_FILETYPE_COMBINED_SMM_DXE 0x0C -#define EFI_FV_FILETYPE_SMM_CORE 0x0D -#define EFI_FV_FILETYPE_OEM_MIN 0xc0 -#define EFI_FV_FILETYPE_OEM_MAX 0xdf -#define EFI_FV_FILETYPE_DEBUG_MIN 0xe0 -#define EFI_FV_FILETYPE_DEBUG_MAX 0xef -#define EFI_FV_FILETYPE_FFS_MIN 0xf0 -#define EFI_FV_FILETYPE_FFS_MAX 0xff -#define EFI_FV_FILETYPE_FFS_PAD 0xf0 -/// -/// FFS File Attributes. -/// -#define FFS_ATTRIB_LARGE_FILE 0x01 -#define FFS_ATTRIB_FIXED 0x04 -#define FFS_ATTRIB_DATA_ALIGNMENT 0x38 -#define FFS_ATTRIB_CHECKSUM 0x40 - -/// -/// FFS File State Bits. -/// -#define EFI_FILE_HEADER_CONSTRUCTION 0x01 -#define EFI_FILE_HEADER_VALID 0x02 -#define EFI_FILE_DATA_VALID 0x04 -#define EFI_FILE_MARKED_FOR_UPDATE 0x08 -#define EFI_FILE_DELETED 0x10 -#define EFI_FILE_HEADER_INVALID 0x20 - - -/// -/// Each file begins with the header that describe the -/// contents and state of the files. -/// -typedef struct { - /// - /// This GUID is the file name. It is used to uniquely identify the file. - /// - EFI_GUID Name; - /// - /// Used to verify the integrity of the file. - /// - EFI_FFS_INTEGRITY_CHECK IntegrityCheck; - /// - /// Identifies the type of file. - /// - EFI_FV_FILETYPE Type; - /// - /// Declares various file attribute bits. - /// - EFI_FFS_FILE_ATTRIBUTES Attributes; - /// - /// The length of the file in bytes, including the FFS header. - /// - UINT8 Size[3]; - /// - /// Used to track the state of the file throughout the life of the file from creation to deletion. - /// - EFI_FFS_FILE_STATE State; -} EFI_FFS_FILE_HEADER; - -typedef struct { - /// - /// This GUID is the file name. It is used to uniquely identify the file. There may be only - /// one instance of a file with the file name GUID of Name in any given firmware - /// volume, except if the file type is EFI_FV_FILETYPE_FFS_PAD. - /// - EFI_GUID Name; - - /// - /// Used to verify the integrity of the file. - /// - EFI_FFS_INTEGRITY_CHECK IntegrityCheck; - - /// - /// Identifies the type of file. - /// - EFI_FV_FILETYPE Type; - - /// - /// Declares various file attribute bits. - /// - EFI_FFS_FILE_ATTRIBUTES Attributes; - - /// - /// The length of the file in bytes, including the FFS header. - /// The length of the file data is either (Size - sizeof(EFI_FFS_FILE_HEADER)). This calculation means a - /// zero-length file has a Size of 24 bytes, which is sizeof(EFI_FFS_FILE_HEADER). - /// Size is not required to be a multiple of 8 bytes. Given a file F, the next file header is - /// located at the next 8-byte aligned firmware volume offset following the last byte of the file F. - /// - UINT8 Size[3]; - - /// - /// Used to track the state of the file throughout the life of the file from creation to deletion. - /// - EFI_FFS_FILE_STATE State; - - /// - /// If FFS_ATTRIB_LARGE_FILE is set in Attributes, then ExtendedSize exists and Size must be set to zero. - /// If FFS_ATTRIB_LARGE_FILE is not set then EFI_FFS_FILE_HEADER is used. - /// - UINT32 ExtendedSize; -} EFI_FFS_FILE_HEADER2; - -#define IS_FFS_FILE2(FfsFileHeaderPtr) \ - (((((EFI_FFS_FILE_HEADER *) (UINTN) FfsFileHeaderPtr)->Attributes) & FFS_ATTRIB_LARGE_FILE) == FFS_ATTRIB_LARGE_FILE) - -#define FFS_FILE_SIZE(FfsFileHeaderPtr) \ - ((UINT32) (*((UINT32 *) ((EFI_FFS_FILE_HEADER *) (UINTN) FfsFileHeaderPtr)->Size) & 0x00ffffff)) - -#define FFS_FILE2_SIZE(FfsFileHeaderPtr) \ - (((EFI_FFS_FILE_HEADER2 *) (UINTN) FfsFileHeaderPtr)->ExtendedSize) - -typedef UINT8 EFI_SECTION_TYPE; - -/// -/// Pseudo type. It is used as a wild card when retrieving sections. -/// The section type EFI_SECTION_ALL matches all section types. -/// -#define EFI_SECTION_ALL 0x00 - -/// -/// Encapsulation section Type values. -/// -#define EFI_SECTION_COMPRESSION 0x01 - -#define EFI_SECTION_GUID_DEFINED 0x02 - -#define EFI_SECTION_DISPOSABLE 0x03 - -/// -/// Leaf section Type values. -/// -#define EFI_SECTION_PE32 0x10 -#define EFI_SECTION_PIC 0x11 -#define EFI_SECTION_TE 0x12 -#define EFI_SECTION_DXE_DEPEX 0x13 -#define EFI_SECTION_VERSION 0x14 -#define EFI_SECTION_USER_INTERFACE 0x15 -#define EFI_SECTION_COMPATIBILITY16 0x16 -#define EFI_SECTION_FIRMWARE_VOLUME_IMAGE 0x17 -#define EFI_SECTION_FREEFORM_SUBTYPE_GUID 0x18 -#define EFI_SECTION_RAW 0x19 -#define EFI_SECTION_PEI_DEPEX 0x1B -#define EFI_SECTION_SMM_DEPEX 0x1C - -/// -/// Common section header. -/// -typedef struct { - /// - /// A 24-bit unsigned integer that contains the total size of the section in bytes, - /// including the EFI_COMMON_SECTION_HEADER. - /// - UINT8 Size[3]; - EFI_SECTION_TYPE Type; - /// - /// Declares the section type. - /// -} EFI_COMMON_SECTION_HEADER; - -typedef struct { - /// - /// A 24-bit unsigned integer that contains the total size of the section in bytes, - /// including the EFI_COMMON_SECTION_HEADER. - /// - UINT8 Size[3]; - - EFI_SECTION_TYPE Type; - - /// - /// If Size is 0xFFFFFF, then ExtendedSize contains the size of the section. If - /// Size is not equal to 0xFFFFFF, then this field does not exist. - /// - UINT32 ExtendedSize; -} EFI_COMMON_SECTION_HEADER2; - -/// -/// Leaf section type that contains an -/// IA-32 16-bit executable image. -/// -typedef EFI_COMMON_SECTION_HEADER EFI_COMPATIBILITY16_SECTION; -typedef EFI_COMMON_SECTION_HEADER2 EFI_COMPATIBILITY16_SECTION2; - -/// -/// CompressionType of EFI_COMPRESSION_SECTION. -/// -#define EFI_NOT_COMPRESSED 0x00 -#define EFI_STANDARD_COMPRESSION 0x01 -/// -/// An encapsulation section type in which the -/// section data is compressed. -/// -typedef struct { - /// - /// Usual common section header. CommonHeader.Type = EFI_SECTION_COMPRESSION. - /// - EFI_COMMON_SECTION_HEADER CommonHeader; - /// - /// The UINT32 that indicates the size of the section data after decompression. - /// - UINT32 UncompressedLength; - /// - /// Indicates which compression algorithm is used. - /// - UINT8 CompressionType; -} EFI_COMPRESSION_SECTION; - -typedef struct { - /// - /// Usual common section header. CommonHeader.Type = EFI_SECTION_COMPRESSION. - /// - EFI_COMMON_SECTION_HEADER2 CommonHeader; - /// - /// UINT32 that indicates the size of the section data after decompression. - /// - UINT32 UncompressedLength; - /// - /// Indicates which compression algorithm is used. - /// - UINT8 CompressionType; -} EFI_COMPRESSION_SECTION2; - -/// -/// An encapsulation section type in which the section data is disposable. -/// A disposable section is an encapsulation section in which the section data may be disposed of during -/// the process of creating or updating a firmware image without significant impact on the usefulness of -/// the file. The Type field in the section header is set to EFI_SECTION_DISPOSABLE. This -/// allows optional or descriptive data to be included with the firmware file which can be removed in -/// order to conserve space. The contents of this section are implementation specific, but might contain -/// debug data or detailed integration instructions. -/// -typedef EFI_COMMON_SECTION_HEADER EFI_DISPOSABLE_SECTION; -typedef EFI_COMMON_SECTION_HEADER2 EFI_DISPOSABLE_SECTION2; - -/// -/// The leaf section which could be used to determine the dispatch order of DXEs. -/// -typedef EFI_COMMON_SECTION_HEADER EFI_DXE_DEPEX_SECTION; -typedef EFI_COMMON_SECTION_HEADER2 EFI_DXE_DEPEX_SECTION2; - -/// -/// The leaf section which contains a PI FV. -/// -typedef EFI_COMMON_SECTION_HEADER EFI_FIRMWARE_VOLUME_IMAGE_SECTION; -typedef EFI_COMMON_SECTION_HEADER2 EFI_FIRMWARE_VOLUME_IMAGE_SECTION2; - -/// -/// The leaf section which contains a single GUID. -/// -typedef struct { - /// - /// Common section header. CommonHeader.Type = EFI_SECTION_FREEFORM_SUBTYPE_GUID. - /// - EFI_COMMON_SECTION_HEADER CommonHeader; - /// - /// This GUID is defined by the creator of the file. It is a vendor-defined file type. - /// - EFI_GUID SubTypeGuid; -} EFI_FREEFORM_SUBTYPE_GUID_SECTION; - -typedef struct { - /// - /// The common section header. CommonHeader.Type = EFI_SECTION_FREEFORM_SUBTYPE_GUID. - /// - EFI_COMMON_SECTION_HEADER2 CommonHeader; - /// - /// This GUID is defined by the creator of the file. It is a vendor-defined file type. - /// - EFI_GUID SubTypeGuid; -} EFI_FREEFORM_SUBTYPE_GUID_SECTION2; - -/// -/// Attributes of EFI_GUID_DEFINED_SECTION. -/// -#define EFI_GUIDED_SECTION_PROCESSING_REQUIRED 0x01 -#define EFI_GUIDED_SECTION_AUTH_STATUS_VALID 0x02 -/// -/// The leaf section which is encapsulation defined by specific GUID. -/// -typedef struct { - /// - /// The common section header. CommonHeader.Type = EFI_SECTION_GUID_DEFINED. - /// - EFI_COMMON_SECTION_HEADER CommonHeader; - /// - /// The GUID that defines the format of the data that follows. It is a vendor-defined section type. - /// - EFI_GUID SectionDefinitionGuid; - /// - /// Contains the offset in bytes from the beginning of the common header to the first byte of the data. - /// - UINT16 DataOffset; - /// - /// The bit field that declares some specific characteristics of the section contents. - /// - UINT16 Attributes; -} EFI_GUID_DEFINED_SECTION; - -typedef struct { - /// - /// The common section header. CommonHeader.Type = EFI_SECTION_GUID_DEFINED. - /// - EFI_COMMON_SECTION_HEADER2 CommonHeader; - /// - /// The GUID that defines the format of the data that follows. It is a vendor-defined section type. - /// - EFI_GUID SectionDefinitionGuid; - /// - /// Contains the offset in bytes from the beginning of the common header to the first byte of the data. - /// - UINT16 DataOffset; - /// - /// The bit field that declares some specific characteristics of the section contents. - /// - UINT16 Attributes; -} EFI_GUID_DEFINED_SECTION2; - -/// -/// The leaf section which contains PE32+ image. -/// -typedef EFI_COMMON_SECTION_HEADER EFI_PE32_SECTION; -typedef EFI_COMMON_SECTION_HEADER2 EFI_PE32_SECTION2; - -/// -/// The leaf section used to determine the dispatch order of PEIMs. -/// -typedef EFI_COMMON_SECTION_HEADER EFI_PEI_DEPEX_SECTION; -typedef EFI_COMMON_SECTION_HEADER2 EFI_PEI_DEPEX_SECTION2; - -/// -/// A leaf section type that contains a position-independent-code (PIC) image. -/// A PIC image section is a leaf section that contains a position-independent-code (PIC) image. -/// In addition to normal PE32+ images that contain relocation information, PEIM executables may be -/// PIC and are referred to as PIC images. A PIC image is the same as a PE32+ image except that all -/// relocation information has been stripped from the image and the image can be moved and will -/// execute correctly without performing any relocation or other fix-ups. EFI_PIC_SECTION2 must -/// be used if the section is 16MB or larger. -/// -typedef EFI_COMMON_SECTION_HEADER EFI_PIC_SECTION; -typedef EFI_COMMON_SECTION_HEADER2 EFI_PIC_SECTION2; - -/// -/// The leaf section which constains the position-independent-code image. -/// -typedef EFI_COMMON_SECTION_HEADER EFI_TE_SECTION; -typedef EFI_COMMON_SECTION_HEADER2 EFI_TE_SECTION2; - -/// -/// The leaf section which contains an array of zero or more bytes. -/// -typedef EFI_COMMON_SECTION_HEADER EFI_RAW_SECTION; -typedef EFI_COMMON_SECTION_HEADER2 EFI_RAW_SECTION2; - -/// -/// The SMM dependency expression section is a leaf section that contains a dependency expression that -/// is used to determine the dispatch order for SMM drivers. Before the SMRAM invocation of the -/// SMM driver's entry point, this dependency expression must evaluate to TRUE. See the Platform -/// Initialization Specification, Volume 2, for details regarding the format of the dependency expression. -/// The dependency expression may refer to protocols installed in either the UEFI or the SMM protocol -/// database. EFI_SMM_DEPEX_SECTION2 must be used if the section is 16MB or larger. -/// -typedef EFI_COMMON_SECTION_HEADER EFI_SMM_DEPEX_SECTION; -typedef EFI_COMMON_SECTION_HEADER2 EFI_SMM_DEPEX_SECTION2; - -/// -/// The leaf section which contains a unicode string that -/// is human readable file name. -/// -typedef struct { - EFI_COMMON_SECTION_HEADER CommonHeader; - - /// - /// Array of unicode string. - /// - CHAR16 FileNameString[1]; -} EFI_USER_INTERFACE_SECTION; - -typedef struct { - EFI_COMMON_SECTION_HEADER2 CommonHeader; - CHAR16 FileNameString[1]; -} EFI_USER_INTERFACE_SECTION2; - -/// -/// The leaf section which contains a numeric build number and -/// an optional unicode string that represents the file revision. -/// -typedef struct { - EFI_COMMON_SECTION_HEADER CommonHeader; - UINT16 BuildNumber; - - /// - /// Array of unicode string. - /// - CHAR16 VersionString[1]; -} EFI_VERSION_SECTION; - -typedef struct { - EFI_COMMON_SECTION_HEADER2 CommonHeader; - /// - /// A UINT16 that represents a particular build. Subsequent builds have monotonically - /// increasing build numbers relative to earlier builds. - /// - UINT16 BuildNumber; - CHAR16 VersionString[1]; -} EFI_VERSION_SECTION2; - -#define IS_SECTION2(SectionHeaderPtr) \ - ((UINT32) (*((UINT32 *) ((EFI_COMMON_SECTION_HEADER *) (UINTN) SectionHeaderPtr)->Size) & 0x00ffffff) == 0x00ffffff) - -#define SECTION_SIZE(SectionHeaderPtr) \ - ((UINT32) (*((UINT32 *) ((EFI_COMMON_SECTION_HEADER *) (UINTN) SectionHeaderPtr)->Size) & 0x00ffffff)) - -#define SECTION2_SIZE(SectionHeaderPtr) \ - (((EFI_COMMON_SECTION_HEADER2 *) (UINTN) SectionHeaderPtr)->ExtendedSize) - -#pragma pack() - -#endif diff --git a/src/vendorcode/intel/fsp1_0/rangeley/include/fspfv.h b/src/vendorcode/intel/fsp1_0/rangeley/include/fspfv.h deleted file mode 100644 index 9688cf472e..0000000000 --- a/src/vendorcode/intel/fsp1_0/rangeley/include/fspfv.h +++ /dev/null @@ -1,249 +0,0 @@ -/** @file - -Copyright (C) 2013, Intel Corporation - -Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - -* Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. -* Redistributions in binary form must reproduce the above copyright notice, this - list of conditions and the following disclaimer in the documentation and/or - other materials provided with the distribution. -* Neither the name of Intel Corporation nor the names of its contributors may - be used to endorse or promote products derived from this software without - specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE - LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF - THE POSSIBILITY OF SUCH DAMAGE. - -**/ - -#ifndef __PI_FIRMWAREVOLUME_H__ -#define __PI_FIRMWAREVOLUME_H__ - -#include - -/// -/// EFI_FV_FILE_ATTRIBUTES -/// -typedef UINT32 EFI_FV_FILE_ATTRIBUTES; - -// -// Value of EFI_FV_FILE_ATTRIBUTES. -// -#define EFI_FV_FILE_ATTRIB_ALIGNMENT 0x0000001F -#define EFI_FV_FILE_ATTRIB_FIXED 0x00000100 -#define EFI_FV_FILE_ATTRIB_MEMORY_MAPPED 0x00000200 - -/// -/// type of EFI FVB attribute -/// -typedef UINT32 EFI_FVB_ATTRIBUTES_2; - -// -// Attributes bit definitions -// -#define EFI_FVB2_READ_DISABLED_CAP 0x00000001 -#define EFI_FVB2_READ_ENABLED_CAP 0x00000002 -#define EFI_FVB2_READ_STATUS 0x00000004 -#define EFI_FVB2_WRITE_DISABLED_CAP 0x00000008 -#define EFI_FVB2_WRITE_ENABLED_CAP 0x00000010 -#define EFI_FVB2_WRITE_STATUS 0x00000020 -#define EFI_FVB2_LOCK_CAP 0x00000040 -#define EFI_FVB2_LOCK_STATUS 0x00000080 -#define EFI_FVB2_STICKY_WRITE 0x00000200 -#define EFI_FVB2_MEMORY_MAPPED 0x00000400 -#define EFI_FVB2_ERASE_POLARITY 0x00000800 -#define EFI_FVB2_READ_LOCK_CAP 0x00001000 -#define EFI_FVB2_READ_LOCK_STATUS 0x00002000 -#define EFI_FVB2_WRITE_LOCK_CAP 0x00004000 -#define EFI_FVB2_WRITE_LOCK_STATUS 0x00008000 -#define EFI_FVB2_ALIGNMENT 0x001F0000 -#define EFI_FVB2_ALIGNMENT_1 0x00000000 -#define EFI_FVB2_ALIGNMENT_2 0x00010000 -#define EFI_FVB2_ALIGNMENT_4 0x00020000 -#define EFI_FVB2_ALIGNMENT_8 0x00030000 -#define EFI_FVB2_ALIGNMENT_16 0x00040000 -#define EFI_FVB2_ALIGNMENT_32 0x00050000 -#define EFI_FVB2_ALIGNMENT_64 0x00060000 -#define EFI_FVB2_ALIGNMENT_128 0x00070000 -#define EFI_FVB2_ALIGNMENT_256 0x00080000 -#define EFI_FVB2_ALIGNMENT_512 0x00090000 -#define EFI_FVB2_ALIGNMENT_1K 0x000A0000 -#define EFI_FVB2_ALIGNMENT_2K 0x000B0000 -#define EFI_FVB2_ALIGNMENT_4K 0x000C0000 -#define EFI_FVB2_ALIGNMENT_8K 0x000D0000 -#define EFI_FVB2_ALIGNMENT_16K 0x000E0000 -#define EFI_FVB2_ALIGNMENT_32K 0x000F0000 -#define EFI_FVB2_ALIGNMENT_64K 0x00100000 -#define EFI_FVB2_ALIGNMENT_128K 0x00110000 -#define EFI_FVB2_ALIGNMENT_256K 0x00120000 -#define EFI_FVB2_ALIGNMENT_512K 0x00130000 -#define EFI_FVB2_ALIGNMENT_1M 0x00140000 -#define EFI_FVB2_ALIGNMENT_2M 0x00150000 -#define EFI_FVB2_ALIGNMENT_4M 0x00160000 -#define EFI_FVB2_ALIGNMENT_8M 0x00170000 -#define EFI_FVB2_ALIGNMENT_16M 0x00180000 -#define EFI_FVB2_ALIGNMENT_32M 0x00190000 -#define EFI_FVB2_ALIGNMENT_64M 0x001A0000 -#define EFI_FVB2_ALIGNMENT_128M 0x001B0000 -#define EFI_FVB2_ALIGNMENT_256M 0x001C0000 -#define EFI_FVB2_ALIGNMENT_512M 0x001D0000 -#define EFI_FVB2_ALIGNMENT_1G 0x001E0000 -#define EFI_FVB2_ALIGNMENT_2G 0x001F0000 - - -typedef struct { - /// - /// The number of sequential blocks which are of the same size. - /// - UINT32 NumBlocks; - /// - /// The size of the blocks. - /// - UINT32 Length; -} EFI_FV_BLOCK_MAP_ENTRY; - -/// -/// Describes the features and layout of the firmware volume. -/// -typedef struct { - /// - /// The first 16 bytes are reserved to allow for the reset vector of - /// processors whose reset vector is at address 0. - /// - UINT8 ZeroVector[16]; - /// - /// Declares the file system with which the firmware volume is formatted. - /// - EFI_GUID FileSystemGuid; - /// - /// Length in bytes of the complete firmware volume, including the header. - /// - UINT64 FvLength; - /// - /// Set to EFI_FVH_SIGNATURE - /// - UINT32 Signature; - /// - /// Declares capabilities and power-on defaults for the firmware volume. - /// - EFI_FVB_ATTRIBUTES_2 Attributes; - /// - /// Length in bytes of the complete firmware volume header. - /// - UINT16 HeaderLength; - /// - /// A 16-bit checksum of the firmware volume header. A valid header sums to zero. - /// - UINT16 Checksum; - /// - /// Offset, relative to the start of the header, of the extended header - /// (EFI_FIRMWARE_VOLUME_EXT_HEADER) or zero if there is no extended header. - /// - UINT16 ExtHeaderOffset; - /// - /// This field must always be set to zero. - /// - UINT8 Reserved[1]; - /// - /// Set to 2. Future versions of this specification may define new header fields and will - /// increment the Revision field accordingly. - /// - UINT8 Revision; - /// - /// An array of run-length encoded FvBlockMapEntry structures. The array is - /// terminated with an entry of {0,0}. - /// - EFI_FV_BLOCK_MAP_ENTRY BlockMap[1]; -} EFI_FIRMWARE_VOLUME_HEADER; - -#define EFI_FVH_SIGNATURE SIGNATURE_32 ('_', 'F', 'V', 'H') - -/// -/// Firmware Volume Header Revision definition -/// -#define EFI_FVH_REVISION 0x02 - -/// -/// Extension header pointed by ExtHeaderOffset of volume header. -/// -typedef struct { - /// - /// Firmware volume name. - /// - EFI_GUID FvName; - /// - /// Size of the rest of the extension header, including this structure. - /// - UINT32 ExtHeaderSize; -} EFI_FIRMWARE_VOLUME_EXT_HEADER; - -/// -/// Entry struture for describing FV extension header -/// -typedef struct { - /// - /// Size of this header extension. - /// - UINT16 ExtEntrySize; - /// - /// Type of the header. - /// - UINT16 ExtEntryType; -} EFI_FIRMWARE_VOLUME_EXT_ENTRY; - -#define EFI_FV_EXT_TYPE_OEM_TYPE 0x01 -/// -/// This extension header provides a mapping between a GUID and an OEM file type. -/// -typedef struct { - /// - /// Standard extension entry, with the type EFI_FV_EXT_TYPE_OEM_TYPE. - /// - EFI_FIRMWARE_VOLUME_EXT_ENTRY Hdr; - /// - /// A bit mask, one bit for each file type between 0xC0 (bit 0) and 0xDF (bit 31). If a bit - /// is '1', then the GUID entry exists in Types. If a bit is '0' then no GUID entry exists in Types. - /// - UINT32 TypeMask; - /// - /// An array of GUIDs, each GUID representing an OEM file type. - /// - /// EFI_GUID Types[1]; - /// -} EFI_FIRMWARE_VOLUME_EXT_ENTRY_OEM_TYPE; - -#define EFI_FV_EXT_TYPE_GUID_TYPE 0x0002 - -/// -/// This extension header EFI_FIRMWARE_VOLUME_EXT_ENTRY_GUID_TYPE provides a vendor specific -/// GUID FormatType type which includes a length and a successive series of data bytes. -/// -typedef struct { - /// - /// Standard extension entry, with the type EFI_FV_EXT_TYPE_OEM_TYPE. - /// - EFI_FIRMWARE_VOLUME_EXT_ENTRY Hdr; - /// - /// Vendor-specific GUID. - /// - EFI_GUID FormatType; - /// - /// An arry of bytes of length Length. - /// - /// UINT8 Data[1]; - /// -} EFI_FIRMWARE_VOLUME_EXT_ENTRY_GUID_TYPE; - -#endif diff --git a/src/vendorcode/intel/fsp1_0/rangeley/include/fspguid.h b/src/vendorcode/intel/fsp1_0/rangeley/include/fspguid.h deleted file mode 100644 index b9a6183d73..0000000000 --- a/src/vendorcode/intel/fsp1_0/rangeley/include/fspguid.h +++ /dev/null @@ -1,69 +0,0 @@ -/** @file - -Copyright (C) 2014, Intel Corporation - -Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - -* Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. -* Redistributions in binary form must reproduce the above copyright notice, this - list of conditions and the following disclaimer in the documentation and/or - other materials provided with the distribution. -* Neither the name of Intel Corporation nor the names of its contributors may - be used to endorse or promote products derived from this software without - specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE - LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF - THE POSSIBILITY OF SUCH DAMAGE. - -**/ - -#ifndef __FSP_GUID_H__ -#define __FSP_GUID_H__ - -/** - - FSP specific GUID HOB definitions - - **/ -#define FSP_INFO_HEADER_GUID \ - { \ - 0x912740BE, 0x2284, 0x4734, {0xB9, 0x71, 0x84, 0xB0, 0x27, 0x35, 0x3F, 0x0C} \ - } - -#define FSP_NON_VOLATILE_STORAGE_HOB_GUID \ - { \ - 0x721acf02, 0x4d77, 0x4c2a, { 0xb3, 0xdc, 0x27, 0xb, 0x7b, 0xa9, 0xe4, 0xb0 } \ - } - -#define FSP_BOOTLOADER_TEMPORARY_MEMORY_HOB_GUID \ - { \ - 0xbbcff46c, 0xc8d3, 0x4113, { 0x89, 0x85, 0xb9, 0xd4, 0xf3, 0xb3, 0xf6, 0x4e } \ - } - -#define FSP_HOB_RESOURCE_OWNER_FSP_GUID \ - { \ - 0x69a79759, 0x1373, 0x4367, { 0xa6, 0xc4, 0xc7, 0xf5, 0x9e, 0xfd, 0x98, 0x6e } \ - } - -#define FSP_HOB_RESOURCE_OWNER_TSEG_GUID \ - { \ - 0xd038747c, 0xd00c, 0x4980, { 0xb3, 0x19, 0x49, 0x01, 0x99, 0xa4, 0x7d, 0x55 } \ - } - -#define FSP_HOB_RESOURCE_OWNER_GRAPHICS_GUID \ - { \ - 0x9c7c3aa7, 0x5332, 0x4917, { 0x82, 0xb9, 0x56, 0xa5, 0xf3, 0xe6, 0x2a, 0x07 } \ - } - -#endif diff --git a/src/vendorcode/intel/fsp1_0/rangeley/include/fsphob.h b/src/vendorcode/intel/fsp1_0/rangeley/include/fsphob.h deleted file mode 100644 index a4200c53c1..0000000000 --- a/src/vendorcode/intel/fsp1_0/rangeley/include/fsphob.h +++ /dev/null @@ -1,544 +0,0 @@ -/** @file - -Copyright (C) 2013, Intel Corporation - -Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - -* Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. -* Redistributions in binary form must reproduce the above copyright notice, this - list of conditions and the following disclaimer in the documentation and/or - other materials provided with the distribution. -* Neither the name of Intel Corporation nor the names of its contributors may - be used to endorse or promote products derived from this software without - specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE - LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF - THE POSSIBILITY OF SUCH DAMAGE. - -**/ - -#ifndef __PI_HOB_H__ -#define __PI_HOB_H__ - -#include - -// -// HobType of EFI_HOB_GENERIC_HEADER. -// -#define EFI_HOB_TYPE_MEMORY_ALLOCATION 0x0002 -#define EFI_HOB_TYPE_RESOURCE_DESCRIPTOR 0x0003 -#define EFI_HOB_TYPE_GUID_EXTENSION 0x0004 -#define EFI_HOB_TYPE_UNUSED 0xFFFE -#define EFI_HOB_TYPE_END_OF_HOB_LIST 0xFFFF - -/// -/// Describes the format and size of the data inside the HOB. -/// All HOBs must contain this generic HOB header. -/// -typedef struct { - /// - /// Identifies the HOB data structure type. - /// - UINT16 HobType; - /// - /// The length in bytes of the HOB. - /// - UINT16 HobLength; - /// - /// This field must always be set to zero. - /// - UINT32 Reserved; -} EFI_HOB_GENERIC_HEADER; - -/// -/// Enumeration of memory types introduced in UEFI. -/// -typedef enum { - /// - /// Not used. - /// - EfiReservedMemoryType, - /// - /// The code portions of a loaded application. - /// (Note that UEFI OS loaders are UEFI applications.) - /// - EfiLoaderCode, - /// - /// The data portions of a loaded application and the default data allocation - /// type used by an application to allocate pool memory. - /// - EfiLoaderData, - /// - /// The code portions of a loaded Boot Services Driver. - /// - EfiBootServicesCode, - /// - /// The data portions of a loaded Boot Serves Driver, and the default data - /// allocation type used by a Boot Services Driver to allocate pool memory. - /// - EfiBootServicesData, - /// - /// The code portions of a loaded Runtime Services Driver. - /// - EfiRuntimeServicesCode, - /// - /// The data portions of a loaded Runtime Services Driver and the default - /// data allocation type used by a Runtime Services Driver to allocate pool memory. - /// - EfiRuntimeServicesData, - /// - /// Free (unallocated) memory. - /// - EfiConventionalMemory, - /// - /// Memory in which errors have been detected. - /// - EfiUnusableMemory, - /// - /// Memory that holds the ACPI tables. - /// - EfiACPIReclaimMemory, - /// - /// Address space reserved for use by the firmware. - /// - EfiACPIMemoryNVS, - /// - /// Used by system firmware to request that a memory-mapped IO region - /// be mapped by the OS to a virtual address so it can be accessed by EFI runtime services. - /// - EfiMemoryMappedIO, - /// - /// System memory-mapped IO region that is used to translate memory - /// cycles to IO cycles by the processor. - /// - EfiMemoryMappedIOPortSpace, - /// - /// Address space reserved by the firmware for code that is part of the processor. - /// - EfiPalCode, - EfiMaxMemoryType -} EFI_MEMORY_TYPE; - -/// -/// EFI_HOB_MEMORY_ALLOCATION_HEADER describes the -/// various attributes of the logical memory allocation. The type field will be used for -/// subsequent inclusion in the UEFI memory map. -/// -typedef struct { - /// - /// A GUID that defines the memory allocation region's type and purpose, as well as - /// other fields within the memory allocation HOB. This GUID is used to define the - /// additional data within the HOB that may be present for the memory allocation HOB. - /// Type EFI_GUID is defined in InstallProtocolInterface() in the UEFI 2.0 - /// specification. - /// - EFI_GUID Name; - - /// - /// The base address of memory allocated by this HOB. Type - /// EFI_PHYSICAL_ADDRESS is defined in AllocatePages() in the UEFI 2.0 - /// specification. - /// - EFI_PHYSICAL_ADDRESS MemoryBaseAddress; - - /// - /// The length in bytes of memory allocated by this HOB. - /// - UINT64 MemoryLength; - - /// - /// Defines the type of memory allocated by this HOB. The memory type definition - /// follows the EFI_MEMORY_TYPE definition. Type EFI_MEMORY_TYPE is defined - /// in AllocatePages() in the UEFI 2.0 specification. - /// - EFI_MEMORY_TYPE MemoryType; - - /// - /// Padding for Itanium processor family - /// - UINT8 Reserved[4]; -} EFI_HOB_MEMORY_ALLOCATION_HEADER; - -/// -/// Describes all memory ranges used during the HOB producer -/// phase that exist outside the HOB list. This HOB type -/// describes how memory is used, not the physical attributes of memory. -/// -typedef struct { - /// - /// The HOB generic header. Header.HobType = EFI_HOB_TYPE_MEMORY_ALLOCATION. - /// - EFI_HOB_GENERIC_HEADER Header; - /// - /// An instance of the EFI_HOB_MEMORY_ALLOCATION_HEADER that describes the - /// various attributes of the logical memory allocation. - /// - EFI_HOB_MEMORY_ALLOCATION_HEADER AllocDescriptor; - // - // Additional data pertaining to the "Name" Guid memory - // may go here. - // -} EFI_HOB_MEMORY_ALLOCATION; - -/// -/// The resource type. -/// -typedef UINT32 EFI_RESOURCE_TYPE; - -// -// Value of ResourceType in EFI_HOB_RESOURCE_DESCRIPTOR. -// -#define EFI_RESOURCE_SYSTEM_MEMORY 0x00000000 -#define EFI_RESOURCE_MEMORY_MAPPED_IO 0x00000001 -#define EFI_RESOURCE_IO 0x00000002 -#define EFI_RESOURCE_FIRMWARE_DEVICE 0x00000003 -#define EFI_RESOURCE_MEMORY_MAPPED_IO_PORT 0x00000004 -#define EFI_RESOURCE_MEMORY_RESERVED 0x00000005 -#define EFI_RESOURCE_IO_RESERVED 0x00000006 -#define EFI_RESOURCE_MAX_MEMORY_TYPE 0x00000007 - -/// -/// A type of recount attribute type. -/// -typedef UINT32 EFI_RESOURCE_ATTRIBUTE_TYPE; - -// -// These types can be ORed together as needed. -// -// The first three enumerations describe settings -// -#define EFI_RESOURCE_ATTRIBUTE_PRESENT 0x00000001 -#define EFI_RESOURCE_ATTRIBUTE_INITIALIZED 0x00000002 -#define EFI_RESOURCE_ATTRIBUTE_TESTED 0x00000004 -// -// The rest of the settings describe capabilities -// -#define EFI_RESOURCE_ATTRIBUTE_SINGLE_BIT_ECC 0x00000008 -#define EFI_RESOURCE_ATTRIBUTE_MULTIPLE_BIT_ECC 0x00000010 -#define EFI_RESOURCE_ATTRIBUTE_ECC_RESERVED_1 0x00000020 -#define EFI_RESOURCE_ATTRIBUTE_ECC_RESERVED_2 0x00000040 -#define EFI_RESOURCE_ATTRIBUTE_READ_PROTECTED 0x00000080 -#define EFI_RESOURCE_ATTRIBUTE_WRITE_PROTECTED 0x00000100 -#define EFI_RESOURCE_ATTRIBUTE_EXECUTION_PROTECTED 0x00000200 -#define EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE 0x00000400 -#define EFI_RESOURCE_ATTRIBUTE_WRITE_COMBINEABLE 0x00000800 -#define EFI_RESOURCE_ATTRIBUTE_WRITE_THROUGH_CACHEABLE 0x00001000 -#define EFI_RESOURCE_ATTRIBUTE_WRITE_BACK_CACHEABLE 0x00002000 -#define EFI_RESOURCE_ATTRIBUTE_16_BIT_IO 0x00004000 -#define EFI_RESOURCE_ATTRIBUTE_32_BIT_IO 0x00008000 -#define EFI_RESOURCE_ATTRIBUTE_64_BIT_IO 0x00010000 -#define EFI_RESOURCE_ATTRIBUTE_UNCACHED_EXPORTED 0x00020000 - -/// -/// Describes the resource properties of all fixed, -/// nonrelocatable resource ranges found on the processor -/// host bus during the HOB producer phase. -/// -typedef struct { - /// - /// The HOB generic header. Header.HobType = EFI_HOB_TYPE_RESOURCE_DESCRIPTOR. - /// - EFI_HOB_GENERIC_HEADER Header; - /// - /// A GUID representing the owner of the resource. This GUID is used by HOB - /// consumer phase components to correlate device ownership of a resource. - /// - EFI_GUID Owner; - /// - /// The resource type enumeration as defined by EFI_RESOURCE_TYPE. - /// - EFI_RESOURCE_TYPE ResourceType; - /// - /// Resource attributes as defined by EFI_RESOURCE_ATTRIBUTE_TYPE. - /// - EFI_RESOURCE_ATTRIBUTE_TYPE ResourceAttribute; - /// - /// The physical start address of the resource region. - /// - EFI_PHYSICAL_ADDRESS PhysicalStart; - /// - /// The number of bytes of the resource region. - /// - UINT64 ResourceLength; -} EFI_HOB_RESOURCE_DESCRIPTOR; - -/// -/// Allows writers of executable content in the HOB producer phase to -/// maintain and manage HOBs with specific GUID. -/// -typedef struct { - /// - /// The HOB generic header. Header.HobType = EFI_HOB_TYPE_GUID_EXTENSION. - /// - EFI_HOB_GENERIC_HEADER Header; - /// - /// A GUID that defines the contents of this HOB. - /// - EFI_GUID Name; - // - // Guid specific data goes here - // -} EFI_HOB_GUID_TYPE; - -/// -/// Union of all the possible HOB Types. -/// -typedef union { - EFI_HOB_GENERIC_HEADER *Header; - EFI_HOB_MEMORY_ALLOCATION *MemoryAllocation; - EFI_HOB_RESOURCE_DESCRIPTOR *ResourceDescriptor; - EFI_HOB_GUID_TYPE *Guid; - UINT8 *Raw; -} EFI_PEI_HOB_POINTERS; - - -/** - Returns the type of a HOB. - - This macro returns the HobType field from the HOB header for the - HOB specified by HobStart. - - @param HobStart A pointer to a HOB. - - @return HobType. - -**/ -#define GET_HOB_TYPE(HobStart) \ - (((EFI_HOB_GENERIC_HEADER *)(HobStart))->HobType) - -/** - Returns the length, in bytes, of a HOB. - - This macro returns the HobLength field from the HOB header for the - HOB specified by HobStart. - - @param HobStart A pointer to a HOB. - - @return HobLength. - -**/ -#define GET_HOB_LENGTH(HobStart) \ - (((EFI_HOB_GENERIC_HEADER *)(HobStart))->HobLength) - -/** - Returns a pointer to the next HOB in the HOB list. - - This macro returns a pointer to HOB that follows the - HOB specified by HobStart in the HOB List. - - @param HobStart A pointer to a HOB. - - @return A pointer to the next HOB in the HOB list. - -**/ -#define GET_NEXT_HOB(HobStart) \ - (VOID *)((UINT8 *)(HobStart) + GET_HOB_LENGTH(HobStart)) - -/** - Determines if a HOB is the last HOB in the HOB list. - - This macro determine if the HOB specified by HobStart is the - last HOB in the HOB list. If HobStart is last HOB in the HOB list, - then TRUE is returned. Otherwise, FALSE is returned. - - @param HobStart A pointer to a HOB. - - @retval TRUE The HOB specified by HobStart is the last HOB in the HOB list. - @retval FALSE The HOB specified by HobStart is not the last HOB in the HOB list. - -**/ -#define END_OF_HOB_LIST(HobStart) (GET_HOB_TYPE(HobStart) == (UINT16)EFI_HOB_TYPE_END_OF_HOB_LIST) - -/** - Returns a pointer to data buffer from a HOB of type EFI_HOB_TYPE_GUID_EXTENSION. - - This macro returns a pointer to the data buffer in a HOB specified by HobStart. - HobStart is assumed to be a HOB of type EFI_HOB_TYPE_GUID_EXTENSION. - - @param GuidHob A pointer to a HOB. - - @return A pointer to the data buffer in a HOB. - -**/ -#define GET_GUID_HOB_DATA(HobStart) \ - (VOID *)((UINT8 *)(HobStart) + sizeof(EFI_HOB_GUID_TYPE)) - -/** - Returns the size of the data buffer from a HOB of type EFI_HOB_TYPE_GUID_EXTENSION. - - This macro returns the size, in bytes, of the data buffer in a HOB specified by HobStart. - HobStart is assumed to be a HOB of type EFI_HOB_TYPE_GUID_EXTENSION. - - @param GuidHob A pointer to a HOB. - - @return The size of the data buffer. -**/ -#define GET_GUID_HOB_DATA_SIZE(HobStart) \ - (UINT16)(GET_HOB_LENGTH(HobStart) - sizeof(EFI_HOB_GUID_TYPE)) - -/** - Returns the pointer to the HOB list. - - This function returns the pointer to first HOB in the list. - - If the pointer to the HOB list is NULL, then ASSERT(). - - @return The pointer to the HOB list. - -**/ -VOID * -EFIAPI -GetHobList ( - VOID - ); - -/** - Returns the next instance of a HOB type from the starting HOB. - - This function searches the first instance of a HOB type from the starting HOB pointer. - If there does not exist such HOB type from the starting HOB pointer, it will return NULL. - In contrast with macro GET_NEXT_HOB(), this function does not skip the starting HOB pointer - unconditionally: it returns HobStart back if HobStart itself meets the requirement; - caller is required to use GET_NEXT_HOB() if it wishes to skip current HobStart. - - If HobStart is NULL, then ASSERT(). - - @param Type The HOB type to return. - @param HobStart The starting HOB pointer to search from. - - @return The next instance of a HOB type from the starting HOB. - -**/ -VOID * -EFIAPI -GetNextHob ( - UINT16 Type, - CONST VOID *HobStart - ); - -/** - Returns the first instance of a HOB type among the whole HOB list. - - This function searches the first instance of a HOB type among the whole HOB list. - If there does not exist such HOB type in the HOB list, it will return NULL. - - If the pointer to the HOB list is NULL, then ASSERT(). - - @param Type The HOB type to return. - - @return The next instance of a HOB type from the starting HOB. - -**/ -VOID * -EFIAPI -GetFirstHob ( - UINT16 Type - ); - -/** - Returns the next instance of the matched GUID HOB from the starting HOB. - - This function searches the first instance of a HOB from the starting HOB pointer. - Such HOB should satisfy two conditions: - its HOB type is EFI_HOB_TYPE_GUID_EXTENSION and its GUID Name equals to the input Guid. - If there does not exist such HOB from the starting HOB pointer, it will return NULL. - Caller is required to apply GET_GUID_HOB_DATA () and GET_GUID_HOB_DATA_SIZE () - to extract the data section and its size info respectively. - In contrast with macro GET_NEXT_HOB(), this function does not skip the starting HOB pointer - unconditionally: it returns HobStart back if HobStart itself meets the requirement; - caller is required to use GET_NEXT_HOB() if it wishes to skip current HobStart. - - If Guid is NULL, then ASSERT(). - If HobStart is NULL, then ASSERT(). - - @param Guid The GUID to match with in the HOB list. - @param HobStart A pointer to a Guid. - - @return The next instance of the matched GUID HOB from the starting HOB. - -**/ -VOID * -EFIAPI -GetNextGuidHob ( - CONST EFI_GUID *Guid, - CONST VOID *HobStart - ); - -/** - Returns the first instance of the matched GUID HOB among the whole HOB list. - - This function searches the first instance of a HOB among the whole HOB list. - Such HOB should satisfy two conditions: - its HOB type is EFI_HOB_TYPE_GUID_EXTENSION and its GUID Name equals to the input Guid. - If there does not exist such HOB from the starting HOB pointer, it will return NULL. - Caller is required to apply GET_GUID_HOB_DATA () and GET_GUID_HOB_DATA_SIZE () - to extract the data section and its size info respectively. - - If the pointer to the HOB list is NULL, then ASSERT(). - If Guid is NULL, then ASSERT(). - - @param Guid The GUID to match with in the HOB list. - - @return The first instance of the matched GUID HOB among the whole HOB list. - -**/ -VOID * -EFIAPI -GetFirstGuidHob ( - CONST EFI_GUID *Guid - ); - -/** - Compares two GUIDs. - - This function compares Guid1 to Guid2. If the GUIDs are identical then TRUE is returned. - If there are any bit differences in the two GUIDs, then FALSE is returned. - - If Guid1 is NULL, then ASSERT(). - If Guid2 is NULL, then ASSERT(). - - @param Guid1 A pointer to a 128 bit GUID. - @param Guid2 A pointer to a 128 bit GUID. - - @retval TRUE Guid1 and Guid2 are identical. - @retval FALSE Guid1 and Guid2 are not identical. - -**/ -BOOLEAN -EFIAPI -CompareGuid ( - CONST EFI_GUID *Guid1, - CONST EFI_GUID *Guid2 - ); - -/** - Reads a 64-bit value from memory that may be unaligned. - - This function returns the 64-bit value pointed to by Buffer. The function - guarantees that the read operation does not produce an alignment fault. - - If the Buffer is NULL, then ASSERT(). - - @param Buffer Pointer to a 64-bit value that may be unaligned. - - @return The 64-bit value read from Buffer. - -**/ -UINT64 -EFIAPI -ReadUnaligned64 ( - CONST UINT64 *Buffer - ); - -#endif diff --git a/src/vendorcode/intel/fsp1_0/rangeley/include/fspinfoheader.h b/src/vendorcode/intel/fsp1_0/rangeley/include/fspinfoheader.h deleted file mode 100644 index 28382cf20e..0000000000 --- a/src/vendorcode/intel/fsp1_0/rangeley/include/fspinfoheader.h +++ /dev/null @@ -1,62 +0,0 @@ -/*++ - -Copyright (C) 2013, Intel Corporation - -Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - -* Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. -* Redistributions in binary form must reproduce the above copyright notice, this - list of conditions and the following disclaimer in the documentation and/or - other materials provided with the distribution. -* Neither the name of Intel Corporation nor the names of its contributors may - be used to endorse or promote products derived from this software without - specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE - LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF - THE POSSIBILITY OF SUCH DAMAGE. - -**/ - -#ifndef _FSP_INFO_HEADER_H_ -#define _FSP_INFO_HEADER_H_ - -#pragma pack(1) - -typedef struct { - - UINT32 Signature; // Off 0x94 - UINT32 HeaderLength; - UINT8 Reserved1[3]; - UINT8 HeaderRevision; - UINT32 ImageRevision; - - CHAR8 ImageId[8]; // Off 0xA4 - UINT32 ImageSize; - UINT32 ImageBase; - - UINT32 ImageAttribute; // Off 0xB4 - UINT32 CfgRegionOffset; - UINT32 CfgRegionSize; - UINT32 ApiEntryNum; - - UINT32 NemInitEntry; // Off 0xC4 - UINT32 FspInitEntry; - UINT32 NotifyPhaseEntry; - UINT32 Reserved2; - -} FSP_INFO_HEADER; - -#pragma pack() - -#endif diff --git a/src/vendorcode/intel/fsp1_0/rangeley/include/fspplatform.h b/src/vendorcode/intel/fsp1_0/rangeley/include/fspplatform.h deleted file mode 100644 index c35dca0c96..0000000000 --- a/src/vendorcode/intel/fsp1_0/rangeley/include/fspplatform.h +++ /dev/null @@ -1,114 +0,0 @@ -/** - -Copyright (C) 2013 - 2015, Intel Corporation - -Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - -* Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. -* Redistributions in binary form must reproduce the above copyright notice, this - list of conditions and the following disclaimer in the documentation and/or - other materials provided with the distribution. -* Neither the name of Intel Corporation nor the names of its contributors may - be used to endorse or promote products derived from this software without - specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE - LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF - THE POSSIBILITY OF SUCH DAMAGE. - -**/ - -#ifndef _FSP_PLATFORM_H_ -#define _FSP_PLATFORM_H_ - -#include "fsptypes.h" -#include "fspapi.h" - -// -// Maximum number of SDRAM channels supported by each CPU -// -#define MAX_CHANNELS 2 -// -// Maximum number of DIMM sockets supported by each channel -// -#define MAX_DIMMS 2 - -#pragma pack(1) -// -// SPD DDR3 structure -// -typedef struct { - UINT8 DRAMDeviceType; // 2 DRAM Device Type - UINT8 ModuleType; // 3 Module Type - UINT8 SDRAMDensityAndBanks; // 4 SDRAM Density and Banks - UINT8 SDRAMAddressing; // 5 SDRAM Addressing - UINT8 VDD; // 6 Module Nominal Voltage - UINT8 ModuleOrganization; // 7 Module Organization - UINT8 ModuleMemoryBusWidth; // 8 Module Memory Bus Width - UINT8 TimebaseDividend; // 10 Medium Timebase (MTB) Dividend - UINT8 TimebaseDivisor; // 11 Medium Timebase (MTB) Divisor - UINT8 SDRAMMinimumCycleTime; // 12 SDRAM Minimum Cycle Time (tCKmin) - UINT8 CASLatenciesLSB; // 14 CAS Latencies Supported, Least Significant Byte - UINT8 CASLatenciesMSB; // 15 CAS Latencies Supported, Most Significant Byte - UINT8 MinimumCASLatencyTime; // 16 Minimum CAS Latency Time (tAAmin) - UINT8 MinimumWriteRecoveryTime; // 17 Minimum Write Recovery Time (tWRmin) - UINT8 MinimumRASToCASDelayTime; // 18 Minimum RAS# to CAS# Delay Time (tRCDmin) - UINT8 MinimumRowToRowDelayTime; // 19 Minimum Row Active to Row Active Delay Time (tRRDmin) - UINT8 MinimumRowPrechargeDelayTime; // 20 Minimum Row Precharge Delay Time (tRPmin) - UINT8 UpperNibblesFortRASAndtRC; // 21 Upper Nibbles for tRAS and tRC - UINT8 tRASmin; // 22 Minimum Active to Precharge Delay Time (tRASmin), Least Significant Byte - UINT8 tRCmin; // 23 Minimum Active to Active/Refresh Delay Time (tRCmin), Least Significant Byte - UINT8 tRFCminLeastSignificantByte; // 24 Minimum Refresh Recovery Delay Time (tRFCmin), Least Significant Byte - UINT8 tRFCminMostSignificantByte; // 25 Minimum Refresh Recovery Delay Time (tRFCmin), Most Significant Byte - UINT8 tWTRmin; // 26 Minimum Internal Write to Read Command Delay Time (tWTRmin) - UINT8 tRTPmin; // 27 Minimum Internal Read to Precharge Command Delay Time (tRTPmin) - UINT8 UpperNibbleFortFAW; // 28 Upper Nibble for tFAW - UINT8 tFAWmin; // 29 Minimum Four Activate Window Delay Time (tFAWmin) - UINT8 SdramThermalRefreshOption; // 31 SdramThermalRefreshOption - UINT8 ModuleThermalSensor; // 32 ModuleThermalSensor - UINT8 SDRAMDeviceType; // 33 SDRAM Device Type - UINT8 tCKminFine; // 34 Fine Offset for SDRAM Minimum Cycle Time (tCKmin) - UINT8 tAAminFine; // 35 Fine Offset for Minimum CAS Latency Time (tAAmin) - UINT8 MACCount; // 41 Maximum Activate Count - UINT8 ReferenceRawCardUsed; // 62 Reference Raw Card Used - UINT8 AddressMappingEdgeConnector; // 63 Address Mapping from Edge Connector to DRAM - UINT8 ModuleManufacturerIdCodeLsb; // 117 Module Manufacturer ID Code, Least Significant Byte - UINT8 ModuleManufacturerIdCodeMsb; // 118 Module Manufacturer ID Code, Most Significant Byte - UINT8 ModuleManufacturingLocation; // 119 Module Manufacturing Location - UINT8 ModuleManufacturingDateYear; // 120 Module Manufacturing Date Year - UINT8 ModuleManufacturingDateWW; // 121 Module Manufacturing Date creation work week - UINT8 ModuleSerialNumberA; // 122 Module Serial Number A - UINT8 ModuleSerialNumberB; // 123 Module Serial Number B - UINT8 ModuleSerialNumberC; // 124 Module Serial Number C - UINT8 ModuleSerialNumberD; // 125 Module Serial Number D - UINT8 DramManufacturerIdLsb; // 148 DRAM Manufacturer ID Code, LSB - UINT8 DramManufacturerIdMsb; // 149 DRAM Manufacturer ID Code, MSB -} MEM_DOWN_DIMM_SPD_DATA; - -typedef struct { - UINT32 MemoryDownDimmPopulation; // 0 - Empty, 1 - DIMM populated - MEM_DOWN_DIMM_SPD_DATA MemoryDownDimmSpdData; -} MEM_DOWN_DIMM_CONFIG; - -typedef struct { - CONST MEM_DOWN_DIMM_CONFIG *MemDownDimmConfig[MAX_CHANNELS][MAX_DIMMS]; -} FSP_INIT_RT_PLATFORM_BUFFER; - -typedef struct { - FSP_INIT_RT_COMMON_BUFFER Common; - FSP_INIT_RT_PLATFORM_BUFFER Platform; -} FSP_INIT_RT_BUFFER; - -#pragma pack() - -#endif \ No newline at end of file diff --git a/src/vendorcode/intel/fsp1_0/rangeley/include/fspsupport.h b/src/vendorcode/intel/fsp1_0/rangeley/include/fspsupport.h deleted file mode 100644 index dbbbf779dc..0000000000 --- a/src/vendorcode/intel/fsp1_0/rangeley/include/fspsupport.h +++ /dev/null @@ -1,95 +0,0 @@ -/** @file - -Copyright (C) 2013 - 2014, Intel Corporation - -Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - -* Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. -* Redistributions in binary form must reproduce the above copyright notice, this - list of conditions and the following disclaimer in the documentation and/or - other materials provided with the distribution. -* Neither the name of Intel Corporation nor the names of its contributors may - be used to endorse or promote products derived from this software without - specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE - LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF - THE POSSIBILITY OF SUCH DAMAGE. - -**/ - -#ifndef __FSP_SUPPORT_H__ -#define __FSP_SUPPORT_H__ - -#include "fsptypes.h" -#include "fspfv.h" -#include "fspffs.h" -#include "fspapi.h" -#include "fsphob.h" -#include "fspguid.h" -#include "fspplatform.h" -#include "fspinfoheader.h" -#include "fspbootmode.h" -#include "fspvpd.h" - -UINT32 -GetUsableLowMemTop ( - CONST VOID *HobListPtr - ); - -UINT64 -GetUsableHighMemTop ( - CONST VOID *HobListPtr - ); - -VOID * -GetGuidHobDataBuffer ( - CONST VOID *HobListPtr, - UINT32 *Length, - EFI_GUID *Guid - ); - -VOID -GetFspReservedMemoryFromGuid ( - CONST VOID *HobListPtr, - EFI_PHYSICAL_ADDRESS *FspMemoryBase, - UINT64 *FspMemoryLength, - EFI_GUID *FspReservedMemoryGuid - ); - -UINT32 -GetTsegReservedMemory ( - CONST VOID *HobListPtr, - UINT32 *Length -); - -UINT32 -GetFspReservedMemory ( - CONST VOID *HobListPtr, - UINT32 *Length -); - -VOID* -GetFspNvsDataBuffer ( - CONST VOID *HobListPtr, - UINT32 *Length - ); - -VOID * -GetBootloaderTempMemoryBuffer ( - CONST VOID *HobListPtr, - UINT32 *Length - ); - - -#endif diff --git a/src/vendorcode/intel/fsp1_0/rangeley/include/fsptypes.h b/src/vendorcode/intel/fsp1_0/rangeley/include/fsptypes.h deleted file mode 100644 index da19250632..0000000000 --- a/src/vendorcode/intel/fsp1_0/rangeley/include/fsptypes.h +++ /dev/null @@ -1,183 +0,0 @@ -/****************************************************************************** - -Copyright (C) 2013, Intel Corporation - -Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - -* Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. -* Redistributions in binary form must reproduce the above copyright notice, this - list of conditions and the following disclaimer in the documentation and/or - other materials provided with the distribution. -* Neither the name of Intel Corporation nor the names of its contributors may - be used to endorse or promote products derived from this software without - specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE - LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF - THE POSSIBILITY OF SUCH DAMAGE. - - *****************************************************************************/ - -/** \file fsptypes.h - * - * - */ - -#ifndef __FSP_TYPES_H__ -#define __FSP_TYPES_H__ - -/// -/// 8-byte unsigned value. -/// -typedef unsigned long long UINT64; -/// -/// 8-byte signed value. -/// -typedef long long INT64; -/// -/// 4-byte unsigned value. -/// -typedef unsigned int UINT32; -/// -/// 4-byte signed value. -/// -typedef int INT32; -/// -/// 2-byte unsigned value. -/// -typedef unsigned short UINT16; -/// -/// 2-byte Character. Unless otherwise specified all strings are stored in the -/// UTF-16 encoding format as defined by Unicode 2.1 and ISO/IEC 10646 standards. -/// -typedef unsigned short CHAR16; -/// -/// 2-byte signed value. -/// -typedef short INT16; -/// -/// Logical Boolean. 1-byte value containing 0 for FALSE or a 1 for TRUE. Other -/// values are undefined. -/// -typedef unsigned char BOOLEAN; -/// -/// 1-byte unsigned value. -/// -typedef unsigned char UINT8; -/// -/// 1-byte Character -/// -typedef char CHAR8; -/// -/// 1-byte signed value -/// -typedef char INT8; - -typedef void VOID; - -typedef UINT64 EFI_PHYSICAL_ADDRESS; - -typedef struct { - UINT32 Data1; - UINT16 Data2; - UINT16 Data3; - UINT8 Data4[8]; -} EFI_GUID; - -#define CONST const -#define STATIC static - -#define TRUE ((BOOLEAN)(1==1)) -#define FALSE ((BOOLEAN)(0==1)) - -static inline void DebugDeadLoop(void) { - for (;;); -} - -#define FSPAPI __attribute__((cdecl)) -#define EFIAPI __attribute__((cdecl)) - -#define _ASSERT(Expression) DebugDeadLoop() -#define ASSERT(Expression) \ - do { \ - if (!(Expression)) { \ - _ASSERT (Expression); \ - } \ - } while (FALSE) - -typedef UINT32 FSP_STATUS; -typedef UINT32 EFI_STATUS; - -/// -/// Compatiable with EFI_STATUS defined in PI Spec. -#define FSP_SUCCESS 0 -#define FSP_INVALID_PARAMETER 0x80000002 -#define FSP_UNSUPPORTED 0x80000003 -#define FSP_DEVICE_ERROR 0x80000007 -#define FSP_NOT_FOUND 0x8000000E -#define FSP_ALREADY_STARTED 0x80000014 - -/** - Returns a 16-bit signature built from 2 ASCII characters. - - This macro returns a 16-bit value built from the two ASCII characters specified - by A and B. - - @param A The first ASCII character. - @param B The second ASCII character. - - @return A 16-bit value built from the two ASCII characters specified by A and B. - -**/ -#define SIGNATURE_16(A, B) ((A) | (B << 8)) - -/** - Returns a 32-bit signature built from 4 ASCII characters. - - This macro returns a 32-bit value built from the four ASCII characters specified - by A, B, C, and D. - - @param A The first ASCII character. - @param B The second ASCII character. - @param C The third ASCII character. - @param D The fourth ASCII character. - - @return A 32-bit value built from the two ASCII characters specified by A, B, - C and D. - -**/ -#define SIGNATURE_32(A, B, C, D) (SIGNATURE_16 (A, B) | (SIGNATURE_16 (C, D) << 16)) - -/** - Returns a 64-bit signature built from 8 ASCII characters. - - This macro returns a 64-bit value built from the eight ASCII characters specified - by A, B, C, D, E, F, G,and H. - - @param A The first ASCII character. - @param B The second ASCII character. - @param C The third ASCII character. - @param D The fourth ASCII character. - @param E The fifth ASCII character. - @param F The sixth ASCII character. - @param G The seventh ASCII character. - @param H The eighth ASCII character. - - @return A 64-bit value built from the two ASCII characters specified by A, B, - C, D, E, F, G and H. - -**/ -#define SIGNATURE_64(A, B, C, D, E, F, G, H) \ - (SIGNATURE_32 (A, B, C, D) | ((UINT64) (SIGNATURE_32 (E, F, G, H)) << 32)) - -#endif diff --git a/src/vendorcode/intel/fsp1_0/rangeley/include/fspvpd.h b/src/vendorcode/intel/fsp1_0/rangeley/include/fspvpd.h deleted file mode 100644 index 4ba1a28cfa..0000000000 --- a/src/vendorcode/intel/fsp1_0/rangeley/include/fspvpd.h +++ /dev/null @@ -1,89 +0,0 @@ -/** @file - -Copyright (C) 2015, Intel Corporation - -Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - -* Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. -* Redistributions in binary form must reproduce the above copyright notice, this - list of conditions and the following disclaimer in the documentation and/or - other materials provided with the distribution. -* Neither the name of Intel Corporation nor the names of its contributors may - be used to endorse or promote products derived from this software without - specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE - LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF - THE POSSIBILITY OF SUCH DAMAGE. - - This file is automatically generated. Please do NOT modify !!! - -**/ - -#ifndef __FSP_VPD_H__ -#define __FSP_VPD_H__ - -#pragma pack(1) - - - -typedef struct _UPD_DATA_REGION { - UINT64 Signature; /* Offset 0x0000 */ - UINT64 Reserved; /* Offset 0x0008 */ - UINT8 UnusedUpdSpace0[16]; /* Offset 0x0010 */ - UINT8 PcdMrcInitTsegSize; /* Offset 0x0020 */ - UINT8 PcdMemoryDown; /* Offset 0x0021 */ - UINT8 PcdMrcRmtSupport; /* Offset 0x0022 */ - UINT8 PcdMrcRmtCpgcExpLoopCntValue; /* Offset 0x0023 */ - UINT8 PcdMrcRmtCpgcNumBursts; /* Offset 0x0024 */ - UINT8 PcdSpdBaseAddress_0_0; /* Offset 0x0025 */ - UINT8 PcdSpdBaseAddress_0_1; /* Offset 0x0026 */ - UINT8 PcdSpdBaseAddress_1_0; /* Offset 0x0027 */ - UINT8 PcdSpdBaseAddress_1_1; /* Offset 0x0028 */ - UINT8 PcdExtendedTemperatureEnable; /* Offset 0x0029 */ - UINT8 UnusedUpdSpace1[6]; /* Offset 0x002A */ - UINT8 PcdEnableLan; /* Offset 0x0030 */ - UINT8 PcdEnableSata2; /* Offset 0x0031 */ - UINT8 PcdEnableSata3; /* Offset 0x0032 */ - UINT8 PcdEnableIQAT; /* Offset 0x0033 */ - UINT8 PcdEnableUsb20; /* Offset 0x0034 */ - UINT8 PcdBifurcation; /* Offset 0x0035 */ - UINT8 PcdPcieRootPort1DeEmphasis; /* Offset 0x0036 */ - UINT8 PcdPcieRootPort2DeEmphasis; /* Offset 0x0037 */ - UINT8 PcdPcieRootPort3DeEmphasis; /* Offset 0x0038 */ - UINT8 PcdPcieRootPort4DeEmphasis; /* Offset 0x0039 */ - UINT8 UnusedUpdSpace2[6]; /* Offset 0x003A */ - UINT8 PcdPrintDebugMessages; /* Offset 0x0040 */ - UINT8 PcdFastboot; /* Offset 0x0041 */ - UINT8 PcdEccSupport; /* Offset 0x0042 */ - UINT8 PcdSerialPortBaudRate; /* Offset 0x0043 */ - UINT8 PcdCustomerRevision[32]; /* Offset 0x0044 */ - UINT8 UnusedUpdSpace3[12]; /* Offset 0x0064 */ - UINT16 PcdRegionTerminator; /* Offset 0x0070 */ -} UPD_DATA_REGION; - -#define VPD_IMAGE_ID 0x562D474E524E5641 /* 'AVNRNG-V' */ -#define VPD_IMAGE_REV 0x00000140 - -typedef struct _VPD_DATA_REGION { - UINT64 PcdVpdRegionSign; /* Offset 0x0000 */ - UINT32 PcdImageRevision; /* Offset 0x0008 */ - UINT32 PcdUpdRegionOffset; /* Offset 0x000C */ - UINT8 UnusedVpdSpace0[16]; /* Offset 0x0010 */ - UINT32 PcdFspReservedMemoryLength; /* Offset 0x0020 */ - UINT8 PcdSpdWriteProtect; /* Offset 0x0024 */ -} VPD_DATA_REGION; - -#pragma pack() - -#endif diff --git a/src/vendorcode/intel/fsp1_0/rangeley/srx/fsp_support.c b/src/vendorcode/intel/fsp1_0/rangeley/srx/fsp_support.c deleted file mode 100644 index 68e6fa0e85..0000000000 --- a/src/vendorcode/intel/fsp1_0/rangeley/srx/fsp_support.c +++ /dev/null @@ -1,288 +0,0 @@ -/** @file - -Copyright (C) 2013 - 2014, Intel Corporation - -Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - -* Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. -* Redistributions in binary form must reproduce the above copyright notice, this - list of conditions and the following disclaimer in the documentation and/or - other materials provided with the distribution. -* Neither the name of Intel Corporation nor the names of its contributors may - be used to endorse or promote products derived from this software without - specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE - LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF - THE POSSIBILITY OF SUCH DAMAGE. - -**/ - -#include -#include -#include "fspsupport.h" - -/** - This function retrieves the top of usable low memory. - - @param HobListPtr A HOB list pointer. - - @retval Usable low memory top. - -**/ -UINT32 -GetUsableLowMemTop ( - CONST VOID *HobStart -) -{ - EFI_PEI_HOB_POINTERS Hob; - UINT32 MemLen; - /* - * Get the HOB list for processing - */ - Hob.Raw = (VOID *)HobStart; - - /* - * Collect memory ranges - */ - MemLen = 0x100000; - while (!END_OF_HOB_LIST(Hob.Raw)) { - if (Hob.Header->HobType == EFI_HOB_TYPE_RESOURCE_DESCRIPTOR) { - if (Hob.ResourceDescriptor->ResourceType == EFI_RESOURCE_SYSTEM_MEMORY) { - /* - * Need memory above 1MB to be collected here - */ - if (Hob.ResourceDescriptor->PhysicalStart >= 0x100000 && - Hob.ResourceDescriptor->PhysicalStart < (EFI_PHYSICAL_ADDRESS) 0x100000000) { - MemLen += (UINT32) (Hob.ResourceDescriptor->ResourceLength); - } - } - } - Hob.Raw = GET_NEXT_HOB(Hob.Raw); - } - - return MemLen; -} - -/** - This function retrieves the top of usable high memory. - - @param HobListPtr A HOB list pointer. - - @retval Usable high memory top. - -**/ -UINT64 -GetUsableHighMemTop ( - CONST VOID *HobStart -) -{ - EFI_PEI_HOB_POINTERS Hob; - UINT64 MemTop; - /* - * Get the HOB list for processing - */ - Hob.Raw = (VOID *)HobStart; - - /* - * Collect memory ranges - */ - MemTop = 0x100000000; - while (!END_OF_HOB_LIST(Hob.Raw)) { - if (Hob.Header->HobType == EFI_HOB_TYPE_RESOURCE_DESCRIPTOR) { - if (Hob.ResourceDescriptor->ResourceType == EFI_RESOURCE_SYSTEM_MEMORY) { - /* - * Need memory above 1MB to be collected here - */ - if (Hob.ResourceDescriptor->PhysicalStart >= (EFI_PHYSICAL_ADDRESS) 0x100000000) { - MemTop += (UINT32) (Hob.ResourceDescriptor->ResourceLength); - } - } - } - Hob.Raw = GET_NEXT_HOB(Hob.Raw); - } - - return MemTop; -} - -/** - This function retrieves a special reserved memory region. - - @param HobListPtr A HOB list pointer. - @param Length A pointer to the GUID HOB data buffer length. If the GUID HOB is - located, the length will be updated. - @param OwnerGuid A pointer to the owner guild. - @retval Reserved region start address. 0 if this region does not exist. - -**/ -VOID -GetFspReservedMemoryFromGuid ( - CONST VOID *HobListPtr, - EFI_PHYSICAL_ADDRESS *Base, - UINT64 *Length, - EFI_GUID *OwnerGuid -) -{ - EFI_PEI_HOB_POINTERS Hob; - - /* - * Get the HOB list for processing - */ - Hob.Raw = (VOID *)HobListPtr; - - /* - * Collect memory ranges - */ - while (!END_OF_HOB_LIST(Hob.Raw)) { - if (Hob.Header->HobType == EFI_HOB_TYPE_RESOURCE_DESCRIPTOR) { - if (Hob.ResourceDescriptor->ResourceType == EFI_RESOURCE_MEMORY_RESERVED) { - if (CompareGuid(&Hob.ResourceDescriptor->Owner, OwnerGuid)) { - *Base = (EFI_PHYSICAL_ADDRESS) (Hob.ResourceDescriptor->PhysicalStart); - *Length = (UINT64) (Hob.ResourceDescriptor->ResourceLength); - break; - } - } - } - Hob.Raw = GET_NEXT_HOB(Hob.Raw); - } -} - -/** - This function retrieves the TSEG reserved normal memory. - - @param HobListPtr A HOB list pointer. - @param Length A pointer to the TSEG reserved memory length buffer. If the GUID HOB is - located, the length will be updated. - @param Guid A pointer to owner HOB GUID. - @retval NULL Failed to find the TSEG reserved memory. - @retval others TSEG reserved memory base. - -**/ -UINT32 -GetTsegReservedMemory ( - CONST VOID *HobListPtr, - UINT32 *Length -) -{ - const EFI_GUID TsegOwnerHobGuid = FSP_HOB_RESOURCE_OWNER_TSEG_GUID; - UINT64 Length64 = 0; - EFI_PHYSICAL_ADDRESS Base = 0; - - GetFspReservedMemoryFromGuid (HobListPtr, &Base, &Length64, (EFI_GUID *)&TsegOwnerHobGuid); - if ((Length != NULL) && (Base != 0)) { - *Length = (UINT32)Length64; - } - return (UINT32)Base; -} - -/** - This function retrieves the FSP reserved normal memory. - - @param HobListPtr A HOB list pointer. - @param Length A pointer to the FSP reserved memory length buffer. If the GUID HOB is - located, the length will be updated. - @param Guid A pointer to owner HOB GUID. - @retval NULL Failed to find the FSP reserved memory. - @retval others FSP reserved memory base. - -**/ -UINT32 -GetFspReservedMemory ( - CONST VOID *HobListPtr, - UINT32 *Length -) -{ - const EFI_GUID FspOwnerHobGuid = FSP_HOB_RESOURCE_OWNER_FSP_GUID; - UINT64 Length64 = 0; - EFI_PHYSICAL_ADDRESS Base = 0; - - GetFspReservedMemoryFromGuid (HobListPtr, &Base, &Length64, (EFI_GUID *)&FspOwnerHobGuid); - if ((Length != NULL) && (Base != 0)) { - *Length = (UINT32)Length64; - } - return (UINT32)Base; -} - - -/** - This function retrieves a GUIDed HOB data buffer and size. - - @param HobListPtr A HOB list pointer. - @param Length A pointer to the GUID HOB data buffer length. If the - GUID HOB is located, the length will be updated. - @param Guid A pointer to HOB GUID. - @retval NULL Failed to find the GUID HOB. - @retval others GUID HOB data buffer pointer. - -**/ -VOID * -GetGuidHobDataBuffer ( - CONST VOID *HobListPtr, - UINT32 *Length, - EFI_GUID *Guid -) -{ - UINT8 *GuidHob; - - /* FSP NVS DATA HOB */ - GuidHob = GetNextGuidHob(Guid, HobListPtr); - if (GuidHob == NULL) { - return NULL; - } else { - if (Length) { - *Length = GET_GUID_HOB_DATA_SIZE (GuidHob); - } - return GET_GUID_HOB_DATA (GuidHob); - } -} - -/** - This function retrieves FSP Non-volatile Storage HOB buffer and size. - - @param HobListPtr A HOB list pointer. - @param Length A pointer to the NVS data buffer length. If the FSP NVS - HOB is located, the length will be updated. - @retval NULL Failed to find the NVS HOB. - @retval others FSP NVS data buffer pointer. - -**/ -VOID * -GetFspNvsDataBuffer ( - CONST VOID *HobListPtr, - UINT32 *Length -) -{ - const EFI_GUID FspNvsHobGuid = FSP_NON_VOLATILE_STORAGE_HOB_GUID; - return GetGuidHobDataBuffer (HobListPtr, Length, (EFI_GUID *)&FspNvsHobGuid); -} - - -/** - This function retrieves Bootloader temporary stack buffer and size. - - @param HobListPtr A HOB list pointer. - @param Length A pointer to the Bootloader temporary stack length. - If the HOB is located, the length will be updated. - @retval NULL Failed to find the Bootloader temporary stack HOB. - @retval others Bootloader temporary stackbuffer pointer. - -**/ -VOID * -GetBootloaderTempMemoryBuffer ( - CONST VOID *HobListPtr, - UINT32 *Length -) -{ - const EFI_GUID FspBootloaderTemporaryMemoryHobGuid = FSP_BOOTLOADER_TEMPORARY_MEMORY_HOB_GUID; - return GetGuidHobDataBuffer (HobListPtr, Length, (EFI_GUID *)&FspBootloaderTemporaryMemoryHobGuid); -} diff --git a/src/vendorcode/intel/fsp1_0/rangeley/srx/fsphob.c b/src/vendorcode/intel/fsp1_0/rangeley/srx/fsphob.c deleted file mode 100644 index bbcf753dce..0000000000 --- a/src/vendorcode/intel/fsp1_0/rangeley/srx/fsphob.c +++ /dev/null @@ -1,198 +0,0 @@ -/****************************************************************************** - -Copyright (C) 2013, Intel Corporation - -Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - -* Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. -* Redistributions in binary form must reproduce the above copyright notice, this - list of conditions and the following disclaimer in the documentation and/or - other materials provided with the distribution. -* Neither the name of Intel Corporation nor the names of its contributors may - be used to endorse or promote products derived from this software without - specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE - LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF - THE POSSIBILITY OF SUCH DAMAGE. - - ******************************************************************************/ - -/*********************************************************************** - * - * fsphob.c - * - * HOB infrastructure code. - * - **********************************************************************/ -#include - -#include "fsptypes.h" -#include "fsphob.h" - -// -// Pointer to the HOB should be initialized with the output of FSP INIT PARAMS -// -extern volatile void *FspHobListPtr; - -/** - Reads a 64-bit value from memory that may be unaligned. - - This function returns the 64-bit value pointed to by Buffer. The function - guarantees that the read operation does not produce an alignment fault. - - If the Buffer is NULL, then ASSERT(). - - @param Buffer Pointer to a 64-bit value that may be unaligned. - - @return The 64-bit value read from Buffer. - -**/ -UINT64 -EFIAPI -ReadUnaligned64 ( - CONST UINT64 *Buffer - ) -{ - ASSERT (Buffer != NULL); - - return *Buffer; -} - -/** - Compares two GUIDs. - - This function compares Guid1 to Guid2. If the GUIDs are identical then TRUE is returned. - If there are any bit differences in the two GUIDs, then FALSE is returned. - - If Guid1 is NULL, then ASSERT(). - If Guid2 is NULL, then ASSERT(). - - @param Guid1 A pointer to a 128 bit GUID. - @param Guid2 A pointer to a 128 bit GUID. - - @retval TRUE Guid1 and Guid2 are identical. - @retval FALSE Guid1 and Guid2 are not identical. - -**/ -BOOLEAN -EFIAPI -CompareGuid ( - CONST EFI_GUID *Guid1, - CONST EFI_GUID *Guid2 - ) -{ - UINT64 LowPartOfGuid1; - UINT64 LowPartOfGuid2; - UINT64 HighPartOfGuid1; - UINT64 HighPartOfGuid2; - - LowPartOfGuid1 = ReadUnaligned64 ((CONST UINT64*) Guid1); - LowPartOfGuid2 = ReadUnaligned64 ((CONST UINT64*) Guid2); - HighPartOfGuid1 = ReadUnaligned64 ((CONST UINT64*) Guid1 + 1); - HighPartOfGuid2 = ReadUnaligned64 ((CONST UINT64*) Guid2 + 1); - - return (BOOLEAN) (LowPartOfGuid1 == LowPartOfGuid2 && HighPartOfGuid1 == HighPartOfGuid2); -} - -/** - Returns the pointer to the HOB list. -**/ -VOID * -EFIAPI -GetHobList ( - VOID - ) -{ - ASSERT (FspHobListPtr != NULL); - return ((VOID *)FspHobListPtr); -} - -/** - Returns the next instance of a HOB type from the starting HOB. -**/ -VOID * -EFIAPI -GetNextHob ( - UINT16 Type, - CONST VOID *HobStart - ) -{ - EFI_PEI_HOB_POINTERS Hob; - - ASSERT (HobStart != NULL); - - Hob.Raw = (UINT8 *) HobStart; - // - // Parse the HOB list until end of list or matching type is found. - // - while (!END_OF_HOB_LIST(Hob.Raw)) { - if (Hob.Header->HobType == Type) { - return Hob.Raw; - } - Hob.Raw = GET_NEXT_HOB(Hob.Raw); - } - return NULL; -} - -/** - Returns the first instance of a HOB type among the whole HOB list. -**/ -VOID * -EFIAPI -GetFirstHob ( - UINT16 Type - ) -{ - VOID *HobList; - - HobList = GetHobList (); - return GetNextHob (Type, HobList); -} - -/** - Returns the next instance of the matched GUID HOB from the starting HOB. -**/ -VOID * -EFIAPI -GetNextGuidHob ( - CONST EFI_GUID *Guid, - CONST VOID *HobStart - ) -{ - EFI_PEI_HOB_POINTERS GuidHob; - - GuidHob.Raw = (UINT8 *) HobStart; - while ((GuidHob.Raw = GetNextHob (EFI_HOB_TYPE_GUID_EXTENSION, GuidHob.Raw)) != NULL) { - if (CompareGuid (Guid, &GuidHob.Guid->Name)) { - break; - } - GuidHob.Raw = GET_NEXT_HOB(GuidHob.Raw); - } - return GuidHob.Raw; -} - -/** - Returns the first instance of the matched GUID HOB among the whole HOB list. -**/ -VOID * -EFIAPI -GetFirstGuidHob ( - CONST EFI_GUID *Guid - ) -{ - VOID *HobList; - - HobList = GetHobList (); - return GetNextGuidHob (Guid, HobList); -} From eb5147027e974ba365aa4706935c7c9582cf7619 Mon Sep 17 00:00:00 2001 From: Arthur Heymans Date: Tue, 19 Nov 2019 18:42:40 +0100 Subject: [PATCH 0306/1242] mb/*/*: Drop FSP_BAYTRAIL support MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Relocatable ramstage, postcar stage and C_ENVIRONMENT_BOOTBLOCK are now mandatory features, which this platform lacks. Change-Id: I08c21fd7e5cf8996911c3912bdbaf12d6450db42 Signed-off-by: Arthur Heymans Reviewed-on: https://review.coreboot.org/c/coreboot/+/36981 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki Reviewed-by: HAOUAS Elyes Reviewed-by: David Hendricks Reviewed-by: Werner Zeh --- src/mainboard/esd/Kconfig | 16 - src/mainboard/esd/Kconfig.name | 2 - src/mainboard/esd/atom15/Kconfig | 64 --- src/mainboard/esd/atom15/Kconfig.name | 2 - src/mainboard/esd/atom15/Makefile.inc | 17 - src/mainboard/esd/atom15/acpi/ec.asl | 0 src/mainboard/esd/atom15/acpi/mainboard.asl | 20 - src/mainboard/esd/atom15/acpi/superio.asl | 0 src/mainboard/esd/atom15/acpi_tables.c | 48 --- src/mainboard/esd/atom15/board_info.txt | 4 - src/mainboard/esd/atom15/cmos.layout | 108 ------ src/mainboard/esd/atom15/devicetree.cb | 93 ----- src/mainboard/esd/atom15/dsdt.asl | 54 --- src/mainboard/esd/atom15/fadt.c | 29 -- src/mainboard/esd/atom15/gpio.c | 231 ----------- src/mainboard/esd/atom15/irqroute.c | 18 - src/mainboard/esd/atom15/irqroute.h | 82 ---- src/mainboard/esd/atom15/mainboard.c | 41 -- src/mainboard/esd/atom15/romstage.c | 78 ---- src/mainboard/intel/bayleybay_fsp/Kconfig | 67 ---- .../intel/bayleybay_fsp/Kconfig.name | 5 - .../intel/bayleybay_fsp/Makefile.inc | 17 - src/mainboard/intel/bayleybay_fsp/acpi/ec.asl | 0 .../intel/bayleybay_fsp/acpi/mainboard.asl | 20 - .../intel/bayleybay_fsp/acpi/superio.asl | 0 .../intel/bayleybay_fsp/acpi_tables.c | 58 --- .../intel/bayleybay_fsp/board_info.txt | 5 - .../intel/bayleybay_fsp/chromeos.fmd | 37 -- src/mainboard/intel/bayleybay_fsp/cmos.layout | 97 ----- .../intel/bayleybay_fsp/devicetree.cb | 76 ---- src/mainboard/intel/bayleybay_fsp/dsdt.asl | 54 --- src/mainboard/intel/bayleybay_fsp/fadt.c | 29 -- src/mainboard/intel/bayleybay_fsp/gpio.c | 220 ----------- src/mainboard/intel/bayleybay_fsp/irqroute.c | 18 - src/mainboard/intel/bayleybay_fsp/irqroute.h | 82 ---- src/mainboard/intel/bayleybay_fsp/mainboard.c | 35 -- src/mainboard/intel/bayleybay_fsp/romstage.c | 168 -------- src/mainboard/intel/bayleybay_fsp/thermal.h | 29 -- src/mainboard/intel/minnowmax/Kconfig | 64 --- src/mainboard/intel/minnowmax/Kconfig.name | 2 - src/mainboard/intel/minnowmax/Makefile.inc | 17 - src/mainboard/intel/minnowmax/acpi/ec.asl | 0 .../intel/minnowmax/acpi/mainboard.asl | 20 - .../intel/minnowmax/acpi/superio.asl | 0 src/mainboard/intel/minnowmax/acpi_tables.c | 48 --- src/mainboard/intel/minnowmax/board_info.txt | 4 - src/mainboard/intel/minnowmax/cmos.layout | 108 ------ src/mainboard/intel/minnowmax/devicetree.cb | 93 ----- src/mainboard/intel/minnowmax/dsdt.asl | 54 --- src/mainboard/intel/minnowmax/fadt.c | 29 -- src/mainboard/intel/minnowmax/gpio.c | 232 ----------- src/mainboard/intel/minnowmax/irqroute.c | 18 - src/mainboard/intel/minnowmax/irqroute.h | 83 ---- src/mainboard/intel/minnowmax/mainboard.c | 41 -- src/mainboard/intel/minnowmax/romstage.c | 140 ------- src/mainboard/opencellular/rotundu/Kconfig | 106 ----- .../opencellular/rotundu/Kconfig.name | 7 - .../opencellular/rotundu/Makefile.inc | 19 - .../opencellular/rotundu/acpi/ec.asl | 0 .../opencellular/rotundu/acpi/mainboard.asl | 20 - .../opencellular/rotundu/acpi/superio.asl | 0 .../opencellular/rotundu/acpi_tables.c | 56 --- .../opencellular/rotundu/board_info.txt | 4 - .../opencellular/rotundu/chromeos.fmd | 37 -- .../opencellular/rotundu/cmos.default | 1 - .../opencellular/rotundu/cmos.layout | 97 ----- src/mainboard/opencellular/rotundu/dsdt.asl | 54 --- src/mainboard/opencellular/rotundu/fadt.c | 29 -- src/mainboard/opencellular/rotundu/irqroute.c | 18 - src/mainboard/opencellular/rotundu/irqroute.h | 84 ---- .../opencellular/rotundu/mainboard.c | 42 -- src/mainboard/opencellular/rotundu/romstage.c | 56 --- .../rotundu/variants/rotundu/devicetree.cb | 85 ---- .../rotundu/variants/rotundu/gpio.c | 362 ----------------- .../rotundu/variants/supabrckv1/devicetree.cb | 85 ---- .../rotundu/variants/supabrckv1/gpio.c | 365 ------------------ .../opencellular/rotundu/vboot-16M.fmd | 30 -- .../opencellular/rotundu/vboot-8M.fmd | 30 -- src/mainboard/siemens/mc_tcu3/Kconfig | 59 --- src/mainboard/siemens/mc_tcu3/Kconfig.name | 2 - src/mainboard/siemens/mc_tcu3/Makefile.inc | 19 - src/mainboard/siemens/mc_tcu3/acpi/ec.asl | 0 .../siemens/mc_tcu3/acpi/mainboard.asl | 20 - .../siemens/mc_tcu3/acpi/superio.asl | 0 src/mainboard/siemens/mc_tcu3/acpi_tables.c | 58 --- src/mainboard/siemens/mc_tcu3/board_info.txt | 4 - src/mainboard/siemens/mc_tcu3/cmos.layout | 119 ------ src/mainboard/siemens/mc_tcu3/devicetree.cb | 83 ---- src/mainboard/siemens/mc_tcu3/dsdt.asl | 54 --- src/mainboard/siemens/mc_tcu3/fadt.c | 29 -- src/mainboard/siemens/mc_tcu3/gpio.c | 220 ----------- src/mainboard/siemens/mc_tcu3/irqroute.c | 18 - src/mainboard/siemens/mc_tcu3/irqroute.h | 82 ---- src/mainboard/siemens/mc_tcu3/lcd_panel.c | 173 --------- src/mainboard/siemens/mc_tcu3/lcd_panel.h | 31 -- src/mainboard/siemens/mc_tcu3/mainboard.c | 79 ---- src/mainboard/siemens/mc_tcu3/romstage.c | 202 ---------- src/mainboard/siemens/mc_tcu3/thermal.h | 29 -- 98 files changed, 5745 deletions(-) delete mode 100644 src/mainboard/esd/Kconfig delete mode 100644 src/mainboard/esd/Kconfig.name delete mode 100644 src/mainboard/esd/atom15/Kconfig delete mode 100644 src/mainboard/esd/atom15/Kconfig.name delete mode 100644 src/mainboard/esd/atom15/Makefile.inc delete mode 100644 src/mainboard/esd/atom15/acpi/ec.asl delete mode 100644 src/mainboard/esd/atom15/acpi/mainboard.asl delete mode 100644 src/mainboard/esd/atom15/acpi/superio.asl delete mode 100644 src/mainboard/esd/atom15/acpi_tables.c delete mode 100644 src/mainboard/esd/atom15/board_info.txt delete mode 100644 src/mainboard/esd/atom15/cmos.layout delete mode 100644 src/mainboard/esd/atom15/devicetree.cb delete mode 100644 src/mainboard/esd/atom15/dsdt.asl delete mode 100644 src/mainboard/esd/atom15/fadt.c delete mode 100644 src/mainboard/esd/atom15/gpio.c delete mode 100644 src/mainboard/esd/atom15/irqroute.c delete mode 100644 src/mainboard/esd/atom15/irqroute.h delete mode 100644 src/mainboard/esd/atom15/mainboard.c delete mode 100644 src/mainboard/esd/atom15/romstage.c delete mode 100644 src/mainboard/intel/bayleybay_fsp/Kconfig delete mode 100644 src/mainboard/intel/bayleybay_fsp/Kconfig.name delete mode 100644 src/mainboard/intel/bayleybay_fsp/Makefile.inc delete mode 100644 src/mainboard/intel/bayleybay_fsp/acpi/ec.asl delete mode 100644 src/mainboard/intel/bayleybay_fsp/acpi/mainboard.asl delete mode 100644 src/mainboard/intel/bayleybay_fsp/acpi/superio.asl delete mode 100644 src/mainboard/intel/bayleybay_fsp/acpi_tables.c delete mode 100644 src/mainboard/intel/bayleybay_fsp/board_info.txt delete mode 100644 src/mainboard/intel/bayleybay_fsp/chromeos.fmd delete mode 100644 src/mainboard/intel/bayleybay_fsp/cmos.layout delete mode 100644 src/mainboard/intel/bayleybay_fsp/devicetree.cb delete mode 100644 src/mainboard/intel/bayleybay_fsp/dsdt.asl delete mode 100644 src/mainboard/intel/bayleybay_fsp/fadt.c delete mode 100644 src/mainboard/intel/bayleybay_fsp/gpio.c delete mode 100644 src/mainboard/intel/bayleybay_fsp/irqroute.c delete mode 100644 src/mainboard/intel/bayleybay_fsp/irqroute.h delete mode 100644 src/mainboard/intel/bayleybay_fsp/mainboard.c delete mode 100644 src/mainboard/intel/bayleybay_fsp/romstage.c delete mode 100644 src/mainboard/intel/bayleybay_fsp/thermal.h delete mode 100644 src/mainboard/intel/minnowmax/Kconfig delete mode 100644 src/mainboard/intel/minnowmax/Kconfig.name delete mode 100644 src/mainboard/intel/minnowmax/Makefile.inc delete mode 100644 src/mainboard/intel/minnowmax/acpi/ec.asl delete mode 100644 src/mainboard/intel/minnowmax/acpi/mainboard.asl delete mode 100644 src/mainboard/intel/minnowmax/acpi/superio.asl delete mode 100644 src/mainboard/intel/minnowmax/acpi_tables.c delete mode 100644 src/mainboard/intel/minnowmax/board_info.txt delete mode 100644 src/mainboard/intel/minnowmax/cmos.layout delete mode 100644 src/mainboard/intel/minnowmax/devicetree.cb delete mode 100644 src/mainboard/intel/minnowmax/dsdt.asl delete mode 100644 src/mainboard/intel/minnowmax/fadt.c delete mode 100644 src/mainboard/intel/minnowmax/gpio.c delete mode 100644 src/mainboard/intel/minnowmax/irqroute.c delete mode 100644 src/mainboard/intel/minnowmax/irqroute.h delete mode 100644 src/mainboard/intel/minnowmax/mainboard.c delete mode 100644 src/mainboard/intel/minnowmax/romstage.c delete mode 100644 src/mainboard/opencellular/rotundu/Kconfig delete mode 100644 src/mainboard/opencellular/rotundu/Kconfig.name delete mode 100644 src/mainboard/opencellular/rotundu/Makefile.inc delete mode 100644 src/mainboard/opencellular/rotundu/acpi/ec.asl delete mode 100644 src/mainboard/opencellular/rotundu/acpi/mainboard.asl delete mode 100644 src/mainboard/opencellular/rotundu/acpi/superio.asl delete mode 100644 src/mainboard/opencellular/rotundu/acpi_tables.c delete mode 100644 src/mainboard/opencellular/rotundu/board_info.txt delete mode 100644 src/mainboard/opencellular/rotundu/chromeos.fmd delete mode 100644 src/mainboard/opencellular/rotundu/cmos.default delete mode 100644 src/mainboard/opencellular/rotundu/cmos.layout delete mode 100644 src/mainboard/opencellular/rotundu/dsdt.asl delete mode 100644 src/mainboard/opencellular/rotundu/fadt.c delete mode 100644 src/mainboard/opencellular/rotundu/irqroute.c delete mode 100644 src/mainboard/opencellular/rotundu/irqroute.h delete mode 100644 src/mainboard/opencellular/rotundu/mainboard.c delete mode 100644 src/mainboard/opencellular/rotundu/romstage.c delete mode 100644 src/mainboard/opencellular/rotundu/variants/rotundu/devicetree.cb delete mode 100644 src/mainboard/opencellular/rotundu/variants/rotundu/gpio.c delete mode 100644 src/mainboard/opencellular/rotundu/variants/supabrckv1/devicetree.cb delete mode 100644 src/mainboard/opencellular/rotundu/variants/supabrckv1/gpio.c delete mode 100644 src/mainboard/opencellular/rotundu/vboot-16M.fmd delete mode 100644 src/mainboard/opencellular/rotundu/vboot-8M.fmd delete mode 100644 src/mainboard/siemens/mc_tcu3/Kconfig delete mode 100644 src/mainboard/siemens/mc_tcu3/Kconfig.name delete mode 100644 src/mainboard/siemens/mc_tcu3/Makefile.inc delete mode 100644 src/mainboard/siemens/mc_tcu3/acpi/ec.asl delete mode 100644 src/mainboard/siemens/mc_tcu3/acpi/mainboard.asl delete mode 100644 src/mainboard/siemens/mc_tcu3/acpi/superio.asl delete mode 100644 src/mainboard/siemens/mc_tcu3/acpi_tables.c delete mode 100644 src/mainboard/siemens/mc_tcu3/board_info.txt delete mode 100644 src/mainboard/siemens/mc_tcu3/cmos.layout delete mode 100644 src/mainboard/siemens/mc_tcu3/devicetree.cb delete mode 100644 src/mainboard/siemens/mc_tcu3/dsdt.asl delete mode 100644 src/mainboard/siemens/mc_tcu3/fadt.c delete mode 100644 src/mainboard/siemens/mc_tcu3/gpio.c delete mode 100644 src/mainboard/siemens/mc_tcu3/irqroute.c delete mode 100644 src/mainboard/siemens/mc_tcu3/irqroute.h delete mode 100644 src/mainboard/siemens/mc_tcu3/lcd_panel.c delete mode 100644 src/mainboard/siemens/mc_tcu3/lcd_panel.h delete mode 100644 src/mainboard/siemens/mc_tcu3/mainboard.c delete mode 100644 src/mainboard/siemens/mc_tcu3/romstage.c delete mode 100644 src/mainboard/siemens/mc_tcu3/thermal.h diff --git a/src/mainboard/esd/Kconfig b/src/mainboard/esd/Kconfig deleted file mode 100644 index 3b9eb5818a..0000000000 --- a/src/mainboard/esd/Kconfig +++ /dev/null @@ -1,16 +0,0 @@ -if VENDOR_ESD - -choice - prompt "Mainboard model" - -source "src/mainboard/esd/*/Kconfig.name" - -endchoice - -source "src/mainboard/esd/*/Kconfig" - -config MAINBOARD_VENDOR - string - default "esd" - -endif # VENDOR_ESD diff --git a/src/mainboard/esd/Kconfig.name b/src/mainboard/esd/Kconfig.name deleted file mode 100644 index a44d854f3e..0000000000 --- a/src/mainboard/esd/Kconfig.name +++ /dev/null @@ -1,2 +0,0 @@ -config VENDOR_ESD - bool "electronic system design" diff --git a/src/mainboard/esd/atom15/Kconfig b/src/mainboard/esd/atom15/Kconfig deleted file mode 100644 index 5726461539..0000000000 --- a/src/mainboard/esd/atom15/Kconfig +++ /dev/null @@ -1,64 +0,0 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2013-2014 Sage Electronic Engineering, LLC. -## Copyright (C) 2014 Intel Corporation -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; version 2 of the License. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## - -if BOARD_ESD_ATOM15 - -config BOARD_SPECIFIC_OPTIONS - def_bool y - select SOC_INTEL_FSP_BAYTRAIL - select BOARD_ROMSIZE_KB_8192 - select HAVE_ACPI_TABLES - select HAVE_OPTION_TABLE - -config MAINBOARD_DIR - string - default "esd/atom15" - -config MAINBOARD_PART_NUMBER - string - default "esd atom15" - -config MAX_CPUS - int - default 16 - -config FSP_FILE - string - default "../intel/fsp/baytrail/BAYTRAIL_FSP.fd" - -config CBFS_SIZE - hex - default 0x00300000 - -config ENABLE_FSP_FAST_BOOT - bool - depends on HAVE_FSP_BIN - default y - -config VIRTUAL_ROM_SIZE - hex - depends on ENABLE_FSP_FAST_BOOT - default 0x800000 - -config POST_DEVICE - bool - default n - -config VGA_BIOS - bool - default y if FSP_PACKAGE_DEFAULT - -endif # BOARD_ESD_ATOM15 diff --git a/src/mainboard/esd/atom15/Kconfig.name b/src/mainboard/esd/atom15/Kconfig.name deleted file mode 100644 index cab7e864db..0000000000 --- a/src/mainboard/esd/atom15/Kconfig.name +++ /dev/null @@ -1,2 +0,0 @@ -config BOARD_ESD_ATOM15 - bool "Atom15" diff --git a/src/mainboard/esd/atom15/Makefile.inc b/src/mainboard/esd/atom15/Makefile.inc deleted file mode 100644 index 3074df2138..0000000000 --- a/src/mainboard/esd/atom15/Makefile.inc +++ /dev/null @@ -1,17 +0,0 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2013 Google Inc. -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; version 2 of the License. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## - -ramstage-y += gpio.c -ramstage-y += irqroute.c diff --git a/src/mainboard/esd/atom15/acpi/ec.asl b/src/mainboard/esd/atom15/acpi/ec.asl deleted file mode 100644 index e69de29bb2..0000000000 diff --git a/src/mainboard/esd/atom15/acpi/mainboard.asl b/src/mainboard/esd/atom15/acpi/mainboard.asl deleted file mode 100644 index b032ee189d..0000000000 --- a/src/mainboard/esd/atom15/acpi/mainboard.asl +++ /dev/null @@ -1,20 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 Google Inc. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -Device (PWRB) -{ - Name(_HID, EisaId("PNP0C0C")) -} diff --git a/src/mainboard/esd/atom15/acpi/superio.asl b/src/mainboard/esd/atom15/acpi/superio.asl deleted file mode 100644 index e69de29bb2..0000000000 diff --git a/src/mainboard/esd/atom15/acpi_tables.c b/src/mainboard/esd/atom15/acpi_tables.c deleted file mode 100644 index fe95a3106c..0000000000 --- a/src/mainboard/esd/atom15/acpi_tables.c +++ /dev/null @@ -1,48 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2012 Google Inc. - * Copyright (C) 2013-2014 Sage Electronic Engineering, LLC. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include - -void acpi_create_gnvs(global_nvs_t *gnvs) -{ - acpi_init_gnvs(gnvs); - - /* No TPM Present */ - gnvs->tpmp = 0; - -} - -unsigned long acpi_fill_madt(unsigned long current) -{ - /* Local APICs */ - current = acpi_create_madt_lapics(current); - - /* IOAPIC */ - current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, - 2, IO_APIC_ADDR, 0); - - current = acpi_madt_irq_overrides(current); - - return current; -} diff --git a/src/mainboard/esd/atom15/board_info.txt b/src/mainboard/esd/atom15/board_info.txt deleted file mode 100644 index b5099b325d..0000000000 --- a/src/mainboard/esd/atom15/board_info.txt +++ /dev/null @@ -1,4 +0,0 @@ -Category: sbc -ROM protocol: SPI -Flashrom support: y -Release year: 2015 diff --git a/src/mainboard/esd/atom15/cmos.layout b/src/mainboard/esd/atom15/cmos.layout deleted file mode 100644 index 4cb5106191..0000000000 --- a/src/mainboard/esd/atom15/cmos.layout +++ /dev/null @@ -1,108 +0,0 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2007-2008 coresystems GmbH -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; version 2 of the License. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## - -# ----------------------------------------------------------------- -entries - -# ----------------------------------------------------------------- -# Status Register A -# ----------------------------------------------------------------- -# Status Register B -# ----------------------------------------------------------------- -# Status Register C -#96 4 r 0 status_c_rsvd -#100 1 r 0 uf_flag -#101 1 r 0 af_flag -#102 1 r 0 pf_flag -#103 1 r 0 irqf_flag -# ----------------------------------------------------------------- -# Status Register D -#104 7 r 0 status_d_rsvd -#111 1 r 0 valid_cmos_ram -# ----------------------------------------------------------------- -# Diagnostic Status Register -#112 8 r 0 diag_rsvd1 - -# ----------------------------------------------------------------- -0 120 r 0 reserved_memory -#120 264 r 0 unused - -# ----------------------------------------------------------------- -# RTC_BOOT_BYTE (coreboot hardcoded) -384 1 e 4 boot_option -388 4 h 0 reboot_counter -#390 2 r 0 unused? - -# ----------------------------------------------------------------- -# coreboot config options: console -#392 3 r 0 unused -395 4 e 6 debug_level -#399 1 r 0 unused - -# coreboot config options: cpu -400 1 e 2 hyper_threading -#401 7 r 0 unused - -# coreboot config options: southbridge -408 1 e 1 nmi -409 2 e 7 power_on_after_fail -411 2 e 8 use_xhci_over_ehci -#413 3 r 0 unused - -# MRC Scrambler Seed values -896 32 r 0 mrc_scrambler_seed -928 32 r 0 mrc_scrambler_seed_s3 - -# coreboot config options: check sums -984 16 h 0 check_sum -#1000 24 r 0 amd_reserved - -#save timestamps in pre-ram boot areas -1720 64 h 0 timestamp_value1 -1784 64 h 0 timestamp_value2 -1848 64 h 0 timestamp_value3 -1912 64 h 0 timestamp_value4 -1976 64 h 0 timestamp_value5 - -# ----------------------------------------------------------------- - -enumerations - -#ID value text -1 0 Disable -1 1 Enable -2 0 Enable -2 1 Disable -4 0 Fallback -4 1 Normal -6 0 Emergency -6 1 Alert -6 2 Critical -6 3 Error -6 4 Warning -6 5 Notice -6 6 Info -6 7 Debug -6 8 Spew -7 0 Disable -7 1 Enable -7 2 Keep -8 0 EHCI -8 1 XHCI -8 2 Default -# ----------------------------------------------------------------- -checksums - -checksum 392 415 984 diff --git a/src/mainboard/esd/atom15/devicetree.cb b/src/mainboard/esd/atom15/devicetree.cb deleted file mode 100644 index 5b9a0472f0..0000000000 --- a/src/mainboard/esd/atom15/devicetree.cb +++ /dev/null @@ -1,93 +0,0 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2013-2014 Sage Electronic Engineering, LLC. -## Copyright (C) 2014 Intel Corporation -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; version 2 of the License. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## - -chip soc/intel/fsp_baytrail - - #### ACPI Register Settings #### - register "fadt_pm_profile" = "PM_UNSPECIFIED" - register "fadt_boot_arch" = "ACPI_FADT_LEGACY_FREE" - - #### FSP register settings #### - register "PcdSataMode" = "SATA_MODE_AHCI" - register "PcdMrcInitSPDAddr1" = "SPD_ADDR_DEFAULT" - register "PcdMrcInitSPDAddr2" = "SPD_ADDR_DEFAULT" - register "PcdMrcInitMmioSize" = "MMIO_SIZE_DEFAULT" - register "PcdeMMCBootMode" = "EMMC_FOLLOWS_DEVICETREE" - register "PcdIgdDvmt50PreAlloc" = "IGD_MEMSIZE_DEFAULT" - register "PcdApertureSize" = "APERTURE_SIZE_DEFAULT" - register "PcdGttSize" = "GTT_SIZE_DEFAULT" - register "PcdLpssSioEnablePciMode" = "LPSS_PCI_MODE_DEFAULT" - register "AzaliaAutoEnable" = "AZALIA_FOLLOWS_DEVICETREE" - register "LpeAcpiModeEnable" = "LPE_ACPI_MODE_DISABLED" - register "IgdRenderStandby" = "IGD_RENDER_STANDBY_ENABLE" - register "EnableMemoryDown" = "MEMORY_DOWN_ENABLE" - register "DRAMSpeed" = "DRAM_SPEED_1066MHZ" - register "DRAMType" = "DRAM_TYPE_DDR3L" - register "DIMM0Enable" = "DIMM0_ENABLE" - register "DIMM1Enable" = "DIMM1_DISABLE" - register "DIMMDWidth" = "DIMM_DWIDTH_X16" - register "DIMMDensity" = "DIMM_DENSITY_4G_BIT" - register "DIMMBusWidth" = "DIMM_BUS_WIDTH_64BIT" - register "DIMMSides" = "DIMM_SIDES_1RANK" - register "DIMMtCL" = "8" - register "DIMMtRPtRCD" = "8" - register "DIMMtWR" = "8" - register "DIMMtWTR" = "4" - register "DIMMtRRD" = "6" - register "DIMMtRTP" = "4" - register "DIMMtFAW" = "27" - - device cpu_cluster 0 on - device lapic 0 on end - end - - device domain 0 on - device pci 00.0 on end # 8086 0F00 - SoC router - - device pci 02.0 off end # 8086 0F31 - GFX - - device pci 03.0 off end # 8086 0F38 - MIPI - - - device pci 10.0 off end # 8086 0F14 - EMMC Port - - device pci 11.0 off end # 8086 0F15 - SDIO Port - - device pci 12.0 on end # 8086 0F16 - SD Port MicroSD on SD3 - device pci 13.0 off end # 8086 0F23 - SATA AHCI - - device pci 14.0 off end # 8086 0F35 - USB XHCI - - device pci 15.0 off end # 8086 0F28 - LP Engine Audio - - device pci 17.0 off end # 8086 0F50 - MMC Port - - device pci 18.0 on end # 8086 0F40 - SIO - DMA - - device pci 18.1 on end # 8086 0F41 - I2C Port 1 (0) - - device pci 18.2 on end # 8086 0F42 - I2C Port 2 (1) - - device pci 18.3 on end # 8086 0F43 - I2C Port 3 (2) - - device pci 18.4 on end # 8086 0F44 - I2C Port 4 (3) - - device pci 18.5 on end # 8086 0F45 - I2C Port 5 (4) - - device pci 18.6 on end # 8086 0F46 - I2C Port 6 (5) EEPROM - device pci 18.7 off end # 8086 0F47 - I2C Port 7 (6) - - device pci 1a.0 off end # 8086 0F18 - TXE - - device pci 1b.0 off end # 8086 0F04 - HD Audio - - device pci 1c.0 on end # 8086 0F48 - PCIe Port 1 (0) - - device pci 1c.1 off end # 8086 0F4A - PCIe Port 2 (1) - - device pci 1c.2 on end # 8086 0F4C - PCIe Port 3 (2) ETHERNET - device pci 1c.3 on end # 8086 0F4E - PCIe Port 4 (3) CAN - device pci 1d.0 on end # 8086 0F34 - USB EHCI - Enabling EHCI - - device pci 1e.0 on end # 8086 0F06 - SIO - DMA - - device pci 1e.1 on end # 8086 0F08 - PWM 1 - - device pci 1e.2 on end # 8086 0F09 - PWM 2 - - device pci 1e.3 on end # 8086 0F0A - HSUART 1 Alternate uart - device pci 1e.4 off end # 8086 0F0C - HSUART 2 - - device pci 1e.5 off end # 8086 0F0E - SPI - - device pci 1f.0 on end # 8086 0F1C - LPC bridge No connector - device pci 1f.3 on end # 8086 0F12 - SMBus 0 SPC - end -end diff --git a/src/mainboard/esd/atom15/dsdt.asl b/src/mainboard/esd/atom15/dsdt.asl deleted file mode 100644 index bea6af7973..0000000000 --- a/src/mainboard/esd/atom15/dsdt.asl +++ /dev/null @@ -1,54 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007-2009 coresystems GmbH - * Copyright (C) 2011 Google Inc. - * Copyright (C) 2014 Sage Electronic Engineering, LLC. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#define INCLUDE_LPE 1 -#define INCLUDE_SCC 1 -#define INCLUDE_EHCI 1 -#define INCLUDE_XHCI 1 -#define INCLUDE_LPSS 1 - - -#include -DefinitionBlock( - "dsdt.aml", - "DSDT", - 0x02, // DSDT revision: ACPI v2.0 and up - OEM_ID, - ACPI_TABLE_CREATOR, - 0x20110725 // OEM revision -) -{ - // Some generic macros - #include - - // global NVS and variables - #include - - #include - - Scope (\_SB) { - Device (PCI0) - { - #include - } - } - - /* Chipset specific sleep states */ - #include - - #include "acpi/mainboard.asl" -} diff --git a/src/mainboard/esd/atom15/fadt.c b/src/mainboard/esd/atom15/fadt.c deleted file mode 100644 index 49e0d30264..0000000000 --- a/src/mainboard/esd/atom15/fadt.c +++ /dev/null @@ -1,29 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007-2009 coresystems GmbH - * Copyright (C) 2013-2014 Sage Electronic Engineering, LLC. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include - -void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt) -{ - acpi_header_t *header = &(fadt->header); - - acpi_fill_in_fadt(fadt,facs,dsdt); - - /* Platform specific customizations go here */ - - header->checksum = acpi_checksum((void *) fadt, sizeof(acpi_fadt_t)); -} diff --git a/src/mainboard/esd/atom15/gpio.c b/src/mainboard/esd/atom15/gpio.c deleted file mode 100644 index bc33517d41..0000000000 --- a/src/mainboard/esd/atom15/gpio.c +++ /dev/null @@ -1,231 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2013 Google Inc. - * Copyright (C) 2014 Sage Electronic Engineering, LLC. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include "irqroute.h" - -/* - * For multiplexed functions, look in EDS: - * 10.3 Ball Name and Function by Location - * - * The pads list is in the BWG_VOL2 Rev1p2: - * Note that Pad # is not the same as GPIO# - * 37 GPIO Handling: - * Table 37-1. SCORE Pads List - * Table 37-2. SSUSORE Pads List - */ - -/* NCORE GPIOs */ -static const struct soc_gpio_map gpncore_gpio_map[] = { - GPIO_FUNC2, /* GPIO_S0_NC[00] - HDMI_HPD */ - GPIO_FUNC2, /* GPIO_S0_NC[01] - HDMI_DDCDAT */ - GPIO_FUNC2, /* GPIO_S0_NC[02] - HDMI_DDCCLK */ - GPIO_NC, /* GPIO_S0_NC[03] - No Connect */ - GPIO_NC, /* GPIO_S0_NC[04] - No Connect */ - GPIO_NC, /* GPIO_S0_NC[05] - No Connect */ - GPIO_NC, /* GPIO_S0_NC[06] - No Connect */ - GPIO_FUNC2, /* GPIO_S0_NC[07] - DDI1_DDCDAT */ - GPIO_NC, /* GPIO_S0_NC[08] - No Connect */ - GPIO_NC, /* GPIO_S0_NC[09] - No Connect */ - GPIO_NC, /* GPIO_S0_NC[10] - No Connect */ - GPIO_NC, /* GPIO_S0_NC[11] - No Connect */ - GPIO_FUNC(0, PULL_UP, 20K), /* GPIO_S0_NC[12] - TP15 */ - GPIO_NC, /* GPIO_S0_NC[13] - No Connect */ - GPIO_NC, /* GPIO_S0_NC[14] - No Connect */ - GPIO_NC, /* GPIO_S0_NC[15] - No Connect */ - GPIO_NC, /* GPIO_S0_NC[16] - No Connect */ - GPIO_NC, /* GPIO_S0_NC[17] - No Connect */ - GPIO_NC, /* GPIO_S0_NC[18] - No Connect */ - GPIO_NC, /* GPIO_S0_NC[19] - No Connect */ - GPIO_NC, /* GPIO_S0_NC[20] - No Connect */ - GPIO_NC, /* GPIO_S0_NC[21] - No Connect */ - GPIO_NC, /* GPIO_S0_NC[22] - No Connect */ - GPIO_NC, /* GPIO_S0_NC[23] - No Connect */ - GPIO_NC, /* GPIO_S0_NC[24] - No Connect */ - GPIO_NC, /* GPIO_S0_NC[25] - No Connect */ - GPIO_NC, /* GPIO_S0_NC[26] - No Connect */ - GPIO_END -}; - -/* SCORE GPIOs (GPIO_S0_SC_XX)*/ -static const struct soc_gpio_map gpscore_gpio_map[] = { - GPIO_FUNC1, /* GPIO_S0_SC[000] - SATA_GP0 */ - GPIO_FUNC1, /* GPIO_S0_SC[001] - SATA_GP1 */ - GPIO_FUNC1, /* GPIO_S0_SC[002] - SATA_LED_B */ - GPIO_FUNC1, /* GPIO_S0_SC[003] - PCIE_CLKREQ_0 */ - GPIO_FUNC1, /* GPIO_S0_SC[004] - PCIE_CLKREQ_1 */ - GPIO_FUNC1, /* GPIO_S0_SC[005] - PCIE_CLKREQ_2 */ - GPIO_FUNC1, /* GPIO_S0_SC[006] - PCIE_CLKREQ_3 */ - GPIO_FUNC2, /* GPIO_S0_SC[007] - SD3_WP */ - GPIO_NC, /* GPIO_S0_SC[008] - No Connect */ - GPIO_NC, /* GPIO_S0_SC[009] - No Connect */ - GPIO_NC, /* GPIO_S0_SC[010] - No Connect */ - GPIO_NC, /* GPIO_S0_SC[011] - No Connect */ - GPIO_NC, /* GPIO_S0_SC[012] - No Connect */ - GPIO_NC, /* GPIO_S0_SC[013] - No Connect */ - GPIO_NC, /* GPIO_S0_SC[014] - No Connect */ - GPIO_NC, /* GPIO_S0_SC[015] - No Connect */ - GPIO_NC, /* GPIO_S0_SC[016] - No Connect */ - GPIO_NC, /* GPIO_S0_SC[017] - No Connect */ - GPIO_NC, /* GPIO_S0_SC[018] - No Connect */ - GPIO_NC, /* GPIO_S0_SC[019] - No Connect */ - GPIO_NC, /* GPIO_S0_SC[020] - No Connect */ - GPIO_NC, /* GPIO_S0_SC[021] - No Connect */ - GPIO_NC, /* GPIO_S0_SC[022] - No Connect */ - GPIO_NC, /* GPIO_S0_SC[023] - No Connect */ - GPIO_NC, /* GPIO_S0_SC[024] - No Connect */ - GPIO_NC, /* GPIO_S0_SC[025] - No Connect */ - GPIO_NC, /* GPIO_S0_SC[026] - No Connect */ - GPIO_NC, /* GPIO_S0_SC[027] - No Connect */ - GPIO_NC, /* GPIO_S0_SC[028] - No Connect */ - GPIO_NC, /* GPIO_S0_SC[029] - No Connect */ - GPIO_NC, /* GPIO_S0_SC[030] - No Connect */ - GPIO_NC, /* GPIO_S0_SC[031] - No Connect */ - GPIO_NC, /* GPIO_S0_SC[032] - No Connect */ - GPIO_FUNC1, /* GPIO_S0_SC[033] - SD3_CLK */ - GPIO_FUNC1, /* GPIO_S0_SC[034] - SD3_D0 */ - GPIO_FUNC1, /* GPIO_S0_SC[035] - SD3_D1 */ - GPIO_FUNC1, /* GPIO_S0_SC[036] - SD3_D2 */ - GPIO_FUNC1, /* GPIO_S0_SC[037] - SD3_D3 */ - GPIO_FUNC1, /* GPIO_S0_SC[038] - SD3_CD# */ - GPIO_FUNC1, /* GPIO_S0_SC[039] - SD3_CMD */ - GPIO_FUNC1, /* GPIO_S0_SC[040] - No Connect */ - GPIO_FUNC1, /* GPIO_S0_SC[041] - /SD3_PWREN */ - GPIO_NC, /* GPIO_S0_SC[042] - No Connect */ - GPIO_NC, /* GPIO_S0_SC[043] - No Connect */ - GPIO_NC, /* GPIO_S0_SC[044] - No Connect */ - GPIO_NC, /* GPIO_S0_SC[045] - No Connect */ - GPIO_NC, /* GPIO_S0_SC[046] - No Connect */ - GPIO_NC, /* GPIO_S0_SC[047] - No Connect */ - GPIO_NC, /* GPIO_S0_SC[048] - No Connect */ - GPIO_NC, /* GPIO_S0_SC[049] - No Connect */ - GPIO_NC, /* GPIO_S0_SC[050] - No Connect */ - GPIO_FUNC1, /* GPIO_S0_SC[051] - PCU_SMB_DATA */ - GPIO_FUNC1, /* GPIO_S0_SC[052] - PCU_SMB_CLK */ - GPIO_FUNC1, /* GPIO_S0_SC[053] - PCU_SMB_ALERT */ - GPIO_FUNC1, /* GPIO_S0_SC[054] - ILB_8254_SPKR */ - GPIO_NC, /* GPIO_S0_SC[055] - No Connect */ - GPIO_FUNC0, /* GPIO_S0_SC[056] - GPIO_S0_SC_56 */ - GPIO_FUNC1, /* GPIO_S0_SC[057] - PCU_UART3_TXD */ - GPIO_NC, /* GPIO_S0_SC[058] - No Connect */ - GPIO_NC, /* GPIO_S0_SC[059] - No Connect */ - GPIO_NC, /* GPIO_S0_SC[060] - No Connect */ - GPIO_FUNC1, /* GPIO_S0_SC[061] - PCU_UART3_RXD */ - GPIO_FUNC1, /* GPIO_S0_SC[062] - LPE_I2S_CLK */ - GPIO_FUNC1, /* GPIO_S0_SC[063] - LPE_I2S_FRM */ - GPIO_FUNC1, /* GPIO_S0_SC[064] - LPE_I2S_DATIN */ - GPIO_FUNC1, /* GPIO_S0_SC[065] - LPE_I2S_DATOUT */ - GPIO_FUNC1, /* GPIO_S0_SC[066] - SOC_SIO_SPI_CS1 */ - GPIO_FUNC1, /* GPIO_S0_SC[067] - SOC_SIO_SPI_MISO */ - GPIO_FUNC1, /* GPIO_S0_SC[068] - SOC_SIO_SPI_MOSI */ - GPIO_FUNC1, /* GPIO_S0_SC[069] - SOC_SIO_SPI_CLK */ - GPIO_FUNC1, /* GPIO_S0_SC[070] - SIO_UART1_RXD */ - GPIO_FUNC1, /* GPIO_S0_SC[071] - SIO_UART1_TXD */ - GPIO_NC, /* GPIO_S0_SC[072] - No Connect */ - GPIO_NC, /* GPIO_S0_SC[073] - No Connect */ - GPIO_NC, /* GPIO_S0_SC[074] - No Connect */ - GPIO_NC, /* GPIO_S0_SC[075] - No Connect */ - GPIO_NC, /* GPIO_S0_SC[076] - No Connect */ - GPIO_NC, /* GPIO_S0_SC[077] - No Connect */ - GPIO_NC, /* GPIO_S0_SC[078] - No Connect */ - GPIO_NC, /* GPIO_S0_SC[079] - No Connect */ - GPIO_NC, /* GPIO_S0_SC[080] - No Connect */ - GPIO_NC, /* GPIO_S0_SC[081] - No Connect */ - GPIO_NC, /* GPIO_S0_SC[082] - No Connect */ - GPIO_NC, /* GPIO_S0_SC[083] - No Connect */ - GPIO_NC, /* GPIO_S0_SC[084] - No Connect */ - GPIO_NC, /* GPIO_S0_SC[085] - No Connect */ - GPIO_NC, /* GPIO_S0_SC[086] - No Connect */ - GPIO_NC, /* GPIO_S0_SC[087] - No Connect */ - GPIO_NC, /* GPIO_S0_SC[088] - No Connect */ - GPIO_NC, /* GPIO_S0_SC[089] - No Connect */ - GPIO_FUNC1, /* GPIO_S0_SC[090] - EXP_I2C_SDA */ - GPIO_FUNC1, /* GPIO_S0_SC[091] - EXP_I2C_SCL */ - GPIO_FUNC1, /* GPIO_S0_SC[092] - 0R GND? */ - GPIO_FUNC1, /* GPIO_S0_SC[093] - 0R GND? */ - GPIO_FUNC1, /* GPIO_S0_SC[094] - SOC_PWM0 */ - GPIO_FUNC1, /* GPIO_S0_SC[095] - SOC_PWM1 */ - GPIO_NC, /* GPIO_S0_SC[096] - No Connect */ - GPIO_NC, /* GPIO_S0_SC[097] - No Connect */ - GPIO_NC, /* GPIO_S0_SC[098] - No Connect */ - GPIO_NC, /* GPIO_S0_SC[099] - No Connect */ - GPIO_NC, /* GPIO_S0_SC[100] - No Connect */ - GPIO_NC, /* GPIO_S0_SC[101] - No Connect */ - GPIO_END -}; - -/* SSUS GPIOs (GPIO_S5) */ -static const struct soc_gpio_map gpssus_gpio_map[] = { - GPIO_NC, /* GPIO_S5[00] - No Connect */ - GPIO_FUNC6, /* GPIO_S5[01] - PMC_WAKE_PCIE[1] */ - GPIO_FUNC6, /* GPIO_S5[02] - PMC_WAKE_PCIE[2] */ - GPIO_FUNC6, /* GPIO_S5[03] - PMC_WAKE_PCIE[3] */ - GPIO_NC, /* GPIO_S5[04] - No Connect */ - GPIO_NC, /* GPIO_S5[05] - No Connect */ - GPIO_NC, /* GPIO_S5[06] - No Connect */ - GPIO_NC, /* GPIO_S5[07] - No Connect */ - GPIO_NC, /* GPIO_S5[08] - No Connect */ - GPIO_NC, /* GPIO_S5[09] - No Connect */ - GPIO_OUT_HIGH, /* GPIO_S5[10] - GPIO_S5_10_UNLOCK */ - GPIO_FUNC0, /* GPIO_S5[11] - SUSPWRDNACK */ - GPIO_NC, /* GPIO_S5[12] - No Connect */ - GPIO_NC, /* GPIO_S5[13] - No Connect */ - GPIO_FUNC1, /* GPIO_S5[14] - GPIO_S514_J20 */ - GPIO_FUNC0, /* GPIO_S5[15] - PMC_WAKE_PCIE[0] */ - GPIO_FUNC(1, PULL_UP, 2K), /* GPIO_S5[16] - No Connect */ - GPIO_NC, /* GPIO_S5[17] - No Connect */ - GPIO_FUNC1, /* GPIO_S5[18] - T360 */ - GPIO_FUNC0, /* GPIO_S5[19] - SOC_USB_HOST_OC0 */ - GPIO_FUNC0, /* GPIO_S5[20] - SOC_USB_HOST_OC1 */ - GPIO_FUNC0, /* GPIO_S5[21] - SOC_SPI_CS1B */ - GPIO_NC, /* GPIO_S5[22] - No Connect */ - GPIO_NC, /* GPIO_S5[23] - No Connect */ - GPIO_NC, /* GPIO_S5[24] - No Connect */ - GPIO_NC, /* GPIO_S5[25] - No Connect */ - GPIO_NC, /* GPIO_S5[26] - No Connect */ - GPIO_FUNC(0, PULL_DISABLE, 10K), /* GPIO_S5[27] - SW450-1 */ - GPIO_FUNC(0, PULL_DISABLE, 10K), /* GPIO_S5[28] - SW450-2 */ - GPIO_FUNC(0, PULL_DISABLE, 10K), /* GPIO_S5[29] - SW450-3 */ - GPIO_FUNC(0, PULL_DISABLE, 10K), /* GPIO_S5[30] - SW450-4 */ - GPIO_NC, /* GPIO_S5[31] - No Connect */ - GPIO_NC, /* GPIO_S5[32] - No Connect */ - GPIO_NC, /* GPIO_S5[33] - No Connect */ - GPIO_NC, /* GPIO_S5[34] - No Connect */ - GPIO_NC, /* GPIO_S5[35] - No Connect */ - GPIO_NC, /* GPIO_S5[36] - No Connect */ - GPIO_NC, /* GPIO_S5[37] - No Connect */ - GPIO_NC, /* GPIO_S5[38] - No Connect */ - GPIO_NC, /* GPIO_S5[39] - No Connect */ - GPIO_NC, /* GPIO_S5[40] - No Connect */ - GPIO_NC, /* GPIO_S5[41] - No Connect */ - GPIO_NC, /* GPIO_S5[42] - No Connect */ - GPIO_NC, /* GPIO_S5[43] - No Connect */ - GPIO_END -}; - -static struct soc_gpio_config gpio_config = { - .ncore = gpncore_gpio_map, - .score = gpscore_gpio_map, - .ssus = gpssus_gpio_map, - .core_dirq = NULL, - .sus_dirq = NULL, -}; - -struct soc_gpio_config* mainboard_get_gpios(void) -{ - return &gpio_config; -} diff --git a/src/mainboard/esd/atom15/irqroute.c b/src/mainboard/esd/atom15/irqroute.c deleted file mode 100644 index db8c512a43..0000000000 --- a/src/mainboard/esd/atom15/irqroute.c +++ /dev/null @@ -1,18 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2013 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include "irqroute.h" - -DEFINE_IRQ_ROUTES; diff --git a/src/mainboard/esd/atom15/irqroute.h b/src/mainboard/esd/atom15/irqroute.h deleted file mode 100644 index d68af9fe28..0000000000 --- a/src/mainboard/esd/atom15/irqroute.h +++ /dev/null @@ -1,82 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2013 Google Inc. - * Copyright (C) 2014 Sage Electronic Engineering, LLC. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef IRQROUTE_H -#define IRQROUTE_H - -#include -#include - -/* - *IR02h GFX INT(A) - PIRQ A - *IR10h EMMC INT(ABCD) - PIRQ DEFG - *IR11h SDIO INT(A) - PIRQ B - *IR12h SD INT(A) - PIRQ C - *IR13h SATA INT(A) - PIRQ D - *IR14h XHCI INT(A) - PIRQ E - *IR15h LP Audio INT(A) - PIRQ F - *IR17h MMC INT(A) - PIRQ F - *IR18h SIO INT(ABCD) - PIRQ BADC - *IR1Ah TXE INT(A) - PIRQ F - *IR1Bh HD Audio INT(A) - PIRQ G - *IR1Ch PCIe INT(ABCD) - PIRQ EFGH - *IR1Dh EHCI INT(A) - PIRQ D - *IR1Eh SIO INT(ABCD) - PIRQ BDEF - *IR1Fh LPC INT(ABCD) - PIRQ HGBC - */ - -/* PCIe bridge routing */ -#define BRIDGE1_DEV PCIE_DEV - -/* PCI bridge IRQs need to be updated in both tables and need to match */ -#define PCIE_BRIDGE_IRQ_ROUTES \ - PCIE_BRIDGE_DEV(RP, BRIDGE1_DEV, E, F, G, H) - -#define PCI_DEV_PIRQ_ROUTES \ - PCI_DEV_PIRQ_ROUTE(GFX_DEV, A, A, A, A), \ - PCI_DEV_PIRQ_ROUTE(EMMC_DEV, D, E, F, G), \ - PCI_DEV_PIRQ_ROUTE(SDIO_DEV, B, A, A, A), \ - PCI_DEV_PIRQ_ROUTE(SD_DEV, C, A, A, A), \ - PCI_DEV_PIRQ_ROUTE(SATA_DEV, D, A, A, A), \ - PCI_DEV_PIRQ_ROUTE(XHCI_DEV, E, A, A, A), \ - PCI_DEV_PIRQ_ROUTE(LPE_DEV, F, A, A, A), \ - PCI_DEV_PIRQ_ROUTE(MMC45_DEV, F, A, A, A), \ - PCI_DEV_PIRQ_ROUTE(SIO1_DEV, B, A, D, C), \ - PCI_DEV_PIRQ_ROUTE(TXE_DEV, F, A, A, A), \ - PCI_DEV_PIRQ_ROUTE(HDA_DEV, G, A, A, A), \ - PCI_DEV_PIRQ_ROUTE(BRIDGE1_DEV, E, F, G, H), \ - PCI_DEV_PIRQ_ROUTE(EHCI_DEV, D, A, A, A), \ - PCI_DEV_PIRQ_ROUTE(SIO2_DEV, B, D, E, F), \ - PCI_DEV_PIRQ_ROUTE(PCU_DEV, H, G, B, C) - -/* - * Route each PIRQ[A-H] to a PIC IRQ[0-15] - * Reserved: 0, 1, 2, 8, 13 - * PS2 keyboard: 12 - * ACPI/SCI: 9 - * Floppy: 6 - */ -#define PIRQ_PIC_ROUTES \ - PIRQ_PIC(A, 3), \ - PIRQ_PIC(B, 5), \ - PIRQ_PIC(C, 7), \ - PIRQ_PIC(D, 10), \ - PIRQ_PIC(E, 11), \ - PIRQ_PIC(F, 12), \ - PIRQ_PIC(G, 14), \ - PIRQ_PIC(H, 15) - -#endif /* IRQROUTE_H */ diff --git a/src/mainboard/esd/atom15/mainboard.c b/src/mainboard/esd/atom15/mainboard.c deleted file mode 100644 index 0fe1259420..0000000000 --- a/src/mainboard/esd/atom15/mainboard.c +++ /dev/null @@ -1,41 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007-2009 coresystems GmbH - * Copyright (C) 2011 The ChromiumOS Authors. All rights reserved. - * Copyright (C) 2014 Sage Electronic Engineering, LLC - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include - -/* - * mainboard_enable is executed as first thing after enumerate_buses(). - * This is the earliest point to add customization. - */ -static void mainboard_enable(struct device *dev) -{ -} - -/* - * mainboard_final is executed as one of the last items before loading the - * payload. - * - * This is the latest point to add customization. - */ -static void mainboard_final(void *chip_info) -{ -} - -struct chip_operations mainboard_ops = { - .enable_dev = mainboard_enable, - .final = mainboard_final, -}; diff --git a/src/mainboard/esd/atom15/romstage.c b/src/mainboard/esd/atom15/romstage.c deleted file mode 100644 index c89a1e2efa..0000000000 --- a/src/mainboard/esd/atom15/romstage.c +++ /dev/null @@ -1,78 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2013 Google Inc. - * Copyright (C) 2013 Sage Electronic Engineering, LLC. - * Copyright (C) 2014 Intel Corporation - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include -#include -#include -#include - -/** - * /brief mainboard call for setup that needs to be done before fsp init - * - */ -void early_mainboard_romstage_entry() -{ - -} - -/** - * Get function disables - most of these will be done automatically - * @param fd_mask - * @param fd2_mask - */ -void get_func_disables(uint32_t *fd_mask, uint32_t *fd2_mask) -{ - -} - -/** - * /brief mainboard call for setup that needs to be done after fsp init - * - */ -void late_mainboard_romstage_entry() -{ - - configure_ssus_gpio(27, PAD_FUNC0 | PAD_PULL_DISABLE, PAD_VAL_INPUT); - configure_ssus_gpio(28, PAD_FUNC0 | PAD_PULL_DISABLE, PAD_VAL_INPUT); - configure_ssus_gpio(29, PAD_FUNC0 | PAD_PULL_DISABLE, PAD_VAL_INPUT); - configure_ssus_gpio(30, PAD_FUNC0 | PAD_PULL_DISABLE, PAD_VAL_INPUT); - - printk(0, "SW450: %d %d %d %d\n", - read_ssus_gpio(27), - read_ssus_gpio(28), - read_ssus_gpio(29), - read_ssus_gpio(30)); - -} - -void romstage_fsp_rt_buffer_callback(FSP_INIT_RT_BUFFER *FspRtBuffer) -{ - UPD_DATA_REGION *UpdData = FspRtBuffer->Common.UpdDataRgnPtr; - u8 use_xhci = UpdData->PcdEnableXhci; - - /* Update XHCI UPD value if required */ - get_option(&use_xhci, "use_xhci_over_ehci"); - if ((use_xhci < 2) && (use_xhci != UpdData->PcdEnableXhci)) { - UpdData->PcdEnableXhci = use_xhci; - printk(FSP_INFO_LEVEL, "Xhci updated from CMOS:\t\t\t%s\n", - UpdData->PcdEnableXhci?"Enabled":"Disabled"); - } - - return; -} diff --git a/src/mainboard/intel/bayleybay_fsp/Kconfig b/src/mainboard/intel/bayleybay_fsp/Kconfig deleted file mode 100644 index 4a08fb1f78..0000000000 --- a/src/mainboard/intel/bayleybay_fsp/Kconfig +++ /dev/null @@ -1,67 +0,0 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2013-2014 Sage Electronic Engineering, LLC. -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; version 2 of the License. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## - -if BOARD_INTEL_BAYLEYBAY_FSP || BOARD_INTEL_BAKERSPORT_FSP - -config BOARD_SPECIFIC_OPTIONS - def_bool y - select SOC_INTEL_FSP_BAYTRAIL - select BOARD_ROMSIZE_KB_2048 - select HAVE_ACPI_TABLES - select HAVE_OPTION_TABLE - select ENABLE_BUILTIN_COM1 if FSP_PACKAGE_DEFAULT - select HAVE_FSP_BIN if FSP_PACKAGE_DEFAULT - -config MAINBOARD_DIR - string - default "intel/bayleybay_fsp" - -config MAINBOARD_PART_NUMBER - string - default "Bakersport CRB (FSP)" if BOARD_INTEL_BAKERSPORT_FSP - default "Bayley Bay CRB (FSP)" - -config MAX_CPUS - int - default 16 - -config FSP_FILE - string - default "../intel/fsp/baytrail/BAYTRAIL_FSP_ECC.fd" if BOARD_INTEL_BAKERSPORT_FSP - default "../intel/fsp/baytrail/BAYTRAIL_FSP.fd" - -config CBFS_SIZE - hex - default 0x00200000 - -config ENABLE_FSP_FAST_BOOT - bool - depends on HAVE_FSP_BIN - default y - -config VIRTUAL_ROM_SIZE - hex - depends on ENABLE_FSP_FAST_BOOT - default 0x800000 - -config FSP_PACKAGE_DEFAULT - bool "Configure defaults for the Intel FSP package" - default n - -config VGA_BIOS - bool - default y if FSP_PACKAGE_DEFAULT - -endif # BOARD_INTEL_BAYLEYBAY_FSP || BOARD_INTEL_BAKERSPORT_FSP diff --git a/src/mainboard/intel/bayleybay_fsp/Kconfig.name b/src/mainboard/intel/bayleybay_fsp/Kconfig.name deleted file mode 100644 index 524c616ac2..0000000000 --- a/src/mainboard/intel/bayleybay_fsp/Kconfig.name +++ /dev/null @@ -1,5 +0,0 @@ -config BOARD_INTEL_BAKERSPORT_FSP - bool "Bakersport FSP-based CRB" - -config BOARD_INTEL_BAYLEYBAY_FSP - bool "Bayley Bay FSP-based CRB" diff --git a/src/mainboard/intel/bayleybay_fsp/Makefile.inc b/src/mainboard/intel/bayleybay_fsp/Makefile.inc deleted file mode 100644 index 3074df2138..0000000000 --- a/src/mainboard/intel/bayleybay_fsp/Makefile.inc +++ /dev/null @@ -1,17 +0,0 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2013 Google Inc. -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; version 2 of the License. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## - -ramstage-y += gpio.c -ramstage-y += irqroute.c diff --git a/src/mainboard/intel/bayleybay_fsp/acpi/ec.asl b/src/mainboard/intel/bayleybay_fsp/acpi/ec.asl deleted file mode 100644 index e69de29bb2..0000000000 diff --git a/src/mainboard/intel/bayleybay_fsp/acpi/mainboard.asl b/src/mainboard/intel/bayleybay_fsp/acpi/mainboard.asl deleted file mode 100644 index b032ee189d..0000000000 --- a/src/mainboard/intel/bayleybay_fsp/acpi/mainboard.asl +++ /dev/null @@ -1,20 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 Google Inc. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -Device (PWRB) -{ - Name(_HID, EisaId("PNP0C0C")) -} diff --git a/src/mainboard/intel/bayleybay_fsp/acpi/superio.asl b/src/mainboard/intel/bayleybay_fsp/acpi/superio.asl deleted file mode 100644 index e69de29bb2..0000000000 diff --git a/src/mainboard/intel/bayleybay_fsp/acpi_tables.c b/src/mainboard/intel/bayleybay_fsp/acpi_tables.c deleted file mode 100644 index d81798c6b0..0000000000 --- a/src/mainboard/intel/bayleybay_fsp/acpi_tables.c +++ /dev/null @@ -1,58 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2012 Google Inc. - * Copyright (C) 2013-2014 Sage Electronic Engineering, LLC. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include - -void acpi_create_gnvs(global_nvs_t *gnvs) -{ - acpi_init_gnvs(gnvs); - - /* Enable USB ports in S3 */ - gnvs->s3u0 = 1; - gnvs->s3u1 = 1; - - /* Disable USB ports in S5 */ - gnvs->s5u0 = 0; - gnvs->s5u1 = 0; - - /* TPM Present */ - gnvs->tpmp = 0; - - /* Enable DPTF */ - gnvs->dpte = 0; -} - -unsigned long acpi_fill_madt(unsigned long current) -{ - /* Local APICs */ - current = acpi_create_madt_lapics(current); - - /* IOAPIC */ - current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, - 2, IO_APIC_ADDR, 0); - - current = acpi_madt_irq_overrides(current); - - return current; -} diff --git a/src/mainboard/intel/bayleybay_fsp/board_info.txt b/src/mainboard/intel/bayleybay_fsp/board_info.txt deleted file mode 100644 index 69232e6d6e..0000000000 --- a/src/mainboard/intel/bayleybay_fsp/board_info.txt +++ /dev/null @@ -1,5 +0,0 @@ -Board name: Bayley Bay -Category: eval -ROM protocol: SPI -ROM socketed: n -Release year: 2014 diff --git a/src/mainboard/intel/bayleybay_fsp/chromeos.fmd b/src/mainboard/intel/bayleybay_fsp/chromeos.fmd deleted file mode 100644 index 7be08dc27b..0000000000 --- a/src/mainboard/intel/bayleybay_fsp/chromeos.fmd +++ /dev/null @@ -1,37 +0,0 @@ -FLASH@0xff800000 0x800000 { - SI_ALL@0x0 0x300000 { - SI_DESC@0x0 0x1000 - SI_ME@0x1000 0x2ff000 - } - SI_BIOS@0x300000 0x500000 { - RW_SECTION_A@0x0 0xf0000 { - VBLOCK_A@0x0 0x10000 - FW_MAIN_A(CBFS)@0x10000 0xc0000 - RW_FWID_A@0xeffc0 0x40 - } - RW_SECTION_B@0xf0000 0xf0000 { - VBLOCK_B@0x0 0x10000 - FW_MAIN_B(CBFS)@0x10000 0xc0000 - RW_FWID_B@0xeffc0 0x40 - } - RW_MRC_CACHE@0x1e0000 0x10000 - RW_ELOG(PRESERVE)@0x1f0000 0x4000 - RW_SHARED@0x1f4000 0x4000 { - SHARED_DATA@0x0 0x2000 - VBLOCK_DEV@0x2000 0x2000 - } - RW_VPD(PRESERVE)@0x1f8000 0x2000 - RW_UNUSED@0x1fa000 0x106000 - WP_RO@0x300000 0x200000 { - RO_VPD(PRESERVE)@0x0 0x4000 - RO_UNUSED@0x4000 0xc000 - RO_SECTION@0x10000 0x1f0000 { - FMAP@0x0 0x800 - RO_FRID@0x800 0x40 - RO_FRID_PAD@0x840 0x7c0 - GBB@0x1000 0xef000 - COREBOOT(CBFS)@0xf0000 0x100000 - } - } - } -} diff --git a/src/mainboard/intel/bayleybay_fsp/cmos.layout b/src/mainboard/intel/bayleybay_fsp/cmos.layout deleted file mode 100644 index 61b99327e6..0000000000 --- a/src/mainboard/intel/bayleybay_fsp/cmos.layout +++ /dev/null @@ -1,97 +0,0 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2007-2008 coresystems GmbH -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; version 2 of the License. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## - -# ----------------------------------------------------------------- -entries - -# ----------------------------------------------------------------- -# Status Register A -# ----------------------------------------------------------------- -# Status Register B -# ----------------------------------------------------------------- -# Status Register C -#96 4 r 0 status_c_rsvd -#100 1 r 0 uf_flag -#101 1 r 0 af_flag -#102 1 r 0 pf_flag -#103 1 r 0 irqf_flag -# ----------------------------------------------------------------- -# Status Register D -#104 7 r 0 status_d_rsvd -#111 1 r 0 valid_cmos_ram -# ----------------------------------------------------------------- -# Diagnostic Status Register -#112 8 r 0 diag_rsvd1 - -# ----------------------------------------------------------------- -0 120 r 0 reserved_memory -#120 264 r 0 unused - -# ----------------------------------------------------------------- -# RTC_BOOT_BYTE (coreboot hardcoded) -384 1 e 4 boot_option -388 4 h 0 reboot_counter -#390 2 r 0 unused? - -# ----------------------------------------------------------------- -# coreboot config options: console -#392 3 r 0 unused -395 4 e 6 debug_level -#399 1 r 0 unused - -# coreboot config options: cpu -400 1 e 2 hyper_threading -#401 7 r 0 unused - -# coreboot config options: southbridge -408 1 e 1 nmi -409 2 e 7 power_on_after_fail -#411 5 r 0 unused - -# MRC Scrambler Seed values -896 32 r 0 mrc_scrambler_seed -928 32 r 0 mrc_scrambler_seed_s3 - -# coreboot config options: check sums -984 16 h 0 check_sum -#1000 24 r 0 amd_reserved - -# ----------------------------------------------------------------- - -enumerations - -#ID value text -1 0 Disable -1 1 Enable -2 0 Enable -2 1 Disable -4 0 Fallback -4 1 Normal -6 0 Emergency -6 1 Alert -6 2 Critical -6 3 Error -6 4 Warning -6 5 Notice -6 6 Info -6 7 Debug -6 8 Spew -7 0 Disable -7 1 Enable -7 2 Keep -# ----------------------------------------------------------------- -checksums - -checksum 392 415 984 diff --git a/src/mainboard/intel/bayleybay_fsp/devicetree.cb b/src/mainboard/intel/bayleybay_fsp/devicetree.cb deleted file mode 100644 index 28caa54104..0000000000 --- a/src/mainboard/intel/bayleybay_fsp/devicetree.cb +++ /dev/null @@ -1,76 +0,0 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2013-2014 Sage Electronic Engineering, LLC. -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; version 2 of the License. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## - -chip soc/intel/fsp_baytrail - - #### ACPI Register Settings #### - register "fadt_pm_profile" = "PM_MOBILE" - register "fadt_boot_arch" = "ACPI_FADT_LEGACY_DEVICES | ACPI_FADT_8042" - - #### FSP register settings #### - register "PcdSataMode" = "SATA_MODE_AHCI" - register "PcdMrcInitSPDAddr1" = "SPD_ADDR_DEFAULT" - register "PcdMrcInitSPDAddr2" = "SPD_ADDR_DEFAULT" - register "PcdMrcInitMmioSize" = "MMIO_SIZE_DEFAULT" - register "PcdeMMCBootMode" = "EMMC_FOLLOWS_DEVICETREE" - register "PcdIgdDvmt50PreAlloc" = "IGD_MEMSIZE_DEFAULT" - register "PcdApertureSize" = "APERTURE_SIZE_DEFAULT" - register "PcdGttSize" = "GTT_SIZE_DEFAULT" - register "PcdLpssSioEnablePciMode" = "LPSS_PCI_MODE_DEFAULT" - register "AzaliaAutoEnable" = "AZALIA_FOLLOWS_DEVICETREE" - register "LpeAcpiModeEnable" = "LPE_ACPI_MODE_DISABLED" - - device cpu_cluster 0 on - device lapic 0 on end - end - - device domain 0 on - device pci 00.0 on end # 8086 0F00 - SoC router - device pci 02.0 on end # 8086 0F31 - GFX - device pci 03.0 off end # 8086 0F38 - MIPI - camera interface - - device pci 10.0 off end # 8086 0F14 - EMMC 4.1 Port (MMC1 pins) - (DO NOT USE) - Only 1 EMMC port at a time - device pci 11.0 on end # 8086 0F15 - SDIO Port (SD2 pins) - device pci 12.0 on end # 8086 0F16 - SD Port (SD3 pins) - device pci 13.0 on end # 8086 0F23 - SATA AHCI (0F20, 0F21, 0F22, 0F23) - device pci 14.0 on end # 8086 0F35 - USB XHCI - Only 1 USB controller at a time - device pci 15.0 off end # 8086 0F28 - LP Engine Audio - device pci 16.0 off end # 8086 0F37 - OTG controller - device pci 17.0 on end # 8086 0F50 - EMMC 4.5 Port (MMC1 pins) - Only 1 EMMC port at a time - device pci 18.0 on end # 8086 0F40 - SIO - DMA - device pci 18.1 on end # 8086 0F41 - I2C Port 1 - device pci 18.2 on end # 8086 0F42 - I2C Port 2 - device pci 18.3 on end # 8086 0F43 - I2C Port 3 - device pci 18.4 on end # 8086 0F44 - I2C Port 4 - device pci 18.5 on end # 8086 0F45 - I2C Port 5 - device pci 18.6 on end # 8086 0F46 - I2C Port 6 - device pci 18.7 on end # 8086 0F47 - I2C Port 7 - device pci 1a.0 on end # 8086 0F18 - Trusted Execution Engine - device pci 1b.0 on end # 8086 0F04 - HD Audio - device pci 1c.0 on end # 8086 0F48 - PCIe Root Port 1 (x4 slot) - device pci 1c.1 on end # 8086 0F4A - PCIe Root Port 2 (half mini pcie slot) - device pci 1c.2 on end # 8086 0F4C - PCIe Root Port 3 (front x1 slot) - device pci 1c.3 on end # 8086 0F4E - PCIe Root Port 4 (rear x1 slot) - device pci 1d.0 off end # 8086 0F34 - USB EHCI - Only 1 USB controller at a time - device pci 1e.0 on end # 8086 0F06 - SIO - DMA - device pci 1e.1 on end # 8086 0F08 - PWM 1 - device pci 1e.2 on end # 8086 0F09 - PWM 2 - device pci 1e.3 on end # 8086 0F0A - HSUART 1 - device pci 1e.4 on end # 8086 0F0C - HSUART 2 - device pci 1e.5 on end # 8086 0F0E - SPI - device pci 1f.0 on end # 8086 0F1C - LPC bridge - device pci 1f.3 on end # 8086 0F12 - SMBus 0 - end -end diff --git a/src/mainboard/intel/bayleybay_fsp/dsdt.asl b/src/mainboard/intel/bayleybay_fsp/dsdt.asl deleted file mode 100644 index bea6af7973..0000000000 --- a/src/mainboard/intel/bayleybay_fsp/dsdt.asl +++ /dev/null @@ -1,54 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007-2009 coresystems GmbH - * Copyright (C) 2011 Google Inc. - * Copyright (C) 2014 Sage Electronic Engineering, LLC. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#define INCLUDE_LPE 1 -#define INCLUDE_SCC 1 -#define INCLUDE_EHCI 1 -#define INCLUDE_XHCI 1 -#define INCLUDE_LPSS 1 - - -#include -DefinitionBlock( - "dsdt.aml", - "DSDT", - 0x02, // DSDT revision: ACPI v2.0 and up - OEM_ID, - ACPI_TABLE_CREATOR, - 0x20110725 // OEM revision -) -{ - // Some generic macros - #include - - // global NVS and variables - #include - - #include - - Scope (\_SB) { - Device (PCI0) - { - #include - } - } - - /* Chipset specific sleep states */ - #include - - #include "acpi/mainboard.asl" -} diff --git a/src/mainboard/intel/bayleybay_fsp/fadt.c b/src/mainboard/intel/bayleybay_fsp/fadt.c deleted file mode 100644 index 8fee54b63e..0000000000 --- a/src/mainboard/intel/bayleybay_fsp/fadt.c +++ /dev/null @@ -1,29 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007-2009 coresystems GmbH - * Copyright (C) 2013 Sage Electronic Engineering, LLC. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include - -void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt) -{ - acpi_header_t *header = &(fadt->header); - - acpi_fill_in_fadt(fadt,facs,dsdt); - - /* Platform specific customizations go here */ - - header->checksum = acpi_checksum((void *) fadt, sizeof(acpi_fadt_t)); -} diff --git a/src/mainboard/intel/bayleybay_fsp/gpio.c b/src/mainboard/intel/bayleybay_fsp/gpio.c deleted file mode 100644 index 27b22c5e17..0000000000 --- a/src/mainboard/intel/bayleybay_fsp/gpio.c +++ /dev/null @@ -1,220 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2013 Google Inc. - * Copyright (C) 2014 Sage Electronic Engineering, LLC. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include "irqroute.h" - -/* NCORE GPIOs */ -static const struct soc_gpio_map gpncore_gpio_map[] = { - GPIO_FUNC2, /* GPIO 0 */ - GPIO_FUNC2, /* GPIO 1 */ - GPIO_FUNC2, /* GPIO 2 */ - GPIO_FUNC2, /* GPIO 3 */ - GPIO_FUNC2, /* GPIO 4 */ - GPIO_FUNC2, /* GPIO 5 */ - GPIO_FUNC2, /* GPIO 6 */ - GPIO_FUNC2, /* GPIO 7 */ - GPIO_FUNC2, /* GPIO 8 */ - GPIO_FUNC2, /* GPIO 9 */ - GPIO_FUNC2, /* GPIO 10 */ - GPIO_FUNC2, /* GPIO 11 */ - GPIO_FUNC2, /* GPIO 12 */ - GPIO_FUNC2, /* GPIO 13 */ - GPIO_FUNC2, /* GPIO 14 */ - GPIO_FUNC2, /* GPIO 15 */ - GPIO_FUNC2, /* GPIO 16 */ - GPIO_FUNC2, /* GPIO 17 */ - GPIO_FUNC2, /* GPIO 18 */ - GPIO_FUNC2, /* GPIO 19 */ - GPIO_FUNC2, /* GPIO 20 */ - GPIO_FUNC2, /* GPIO 21 */ - GPIO_FUNC2, /* GPIO 22 */ - GPIO_FUNC2, /* GPIO 23 */ - GPIO_FUNC2, /* GPIO 24 */ - GPIO_FUNC2, /* GPIO 25 */ - GPIO_FUNC2, /* GPIO 26 */ - GPIO_END -}; - -/* SCORE GPIOs (GPIO_S0_SC_XX)*/ -static const struct soc_gpio_map gpscore_gpio_map[] = { - GPIO_FUNC1, /* GPIO_S0_SC[000] SATA_GP[0] - - - */ - GPIO_FUNC2, /* GPIO_S0_SC[001] SATA_GP[1] SATA_DEVSLP[0] - - */ - GPIO_FUNC1, /* GPIO_S0_SC[002] SATA_LED# - - - */ - GPIO_FUNC1, /* GPIO_S0_SC[003] PCIE_CLKREQ[0]# - - - */ - GPIO_FUNC1, /* GPIO_S0_SC[004] PCIE_CLKREQ[1]# - - - */ - GPIO_FUNC1, /* GPIO_S0_SC[005] PCIE_CLKREQ[2]# - - - */ - GPIO_FUNC1, /* GPIO_S0_SC[006] PCIE_CLKREQ[3]# - - - */ - GPIO_NC, /* GPIO_S0_SC[007] RESERVED SD3_WP - - */ - GPIO_FUNC2, /* GPIO_S0_SC[008] I2S0_CLK HDA_RST# - - */ - GPIO_FUNC2, /* GPIO_S0_SC[009] I2S0_FRM HDA_SYNC - - */ - GPIO_FUNC2, /* GPIO_S0_SC[010] I2S0_DATAOUT HDA_CLK - - */ - GPIO_FUNC2, /* GPIO_S0_SC[011] I2S0_DATAIN HDA_SDO - - */ - GPIO_FUNC2, /* GPIO_S0_SC[012] I2S1_CLK HDA_SDI[0] - - */ - GPIO_NC, /* GPIO_S0_SC[013] I2S1_FRM HDA_SDI[1] - - */ - GPIO_DEFAULT, /* GPIO_S0_SC[014] I2S1_DATAOUT RESERVED - - */ - GPIO_DEFAULT, /* GPIO_S0_SC[015] I2S1_DATAIN RESERVED - - */ - GPIO_NC, /* GPIO_S0_SC[016] MMC1_CLK - MMC1_45_CLK - */ - GPIO_NC, /* GPIO_S0_SC[017] MMC1_D[0] - MMC1_45_D[0] - */ - GPIO_NC, /* GPIO_S0_SC[018] MMC1_D[1] - MMC1_45_D[1] - */ - GPIO_NC, /* GPIO_S0_SC[019] MMC1_D[2] - MMC1_45_D[2] - */ - GPIO_NC, /* GPIO_S0_SC[020] MMC1_D[3] - MMC1_45_D[3] - */ - GPIO_NC, /* GPIO_S0_SC[021] MMC1_D[4] - MMC1_45_D[4] - */ - GPIO_NC, /* GPIO_S0_SC[022] MMC1_D[5] - MMC1_45_D[5] - */ - GPIO_NC, /* GPIO_S0_SC[023] MMC1_D[6] - MMC1_45_D[6] - */ - GPIO_NC, /* GPIO_S0_SC[024] MMC1_D[7] - MMC1_45_D[7] - */ - GPIO_NC, /* GPIO_S0_SC[025] MMC1_CMD - MMC1_45_CMD - */ - GPIO_NC, /* GPIO_S0_SC[026] MMC1_RST# SATA_DEVSLP[0] MMC1_45_RST# - */ - GPIO_FUNC1, /* GPIO_S0_SC[027] SD2_CLK - - - */ - GPIO_FUNC1, /* GPIO_S0_SC[028] SD2_D[0] - - - */ - GPIO_FUNC1, /* GPIO_S0_SC[029] SD2_D[1] - - - */ - GPIO_FUNC1, /* GPIO_S0_SC[030] SD2_D[2] - - - */ - GPIO_FUNC1, /* GPIO_S0_SC[031] SD2_D[3]_CD# - - - */ - GPIO_FUNC1, /* GPIO_S0_SC[032] SD2_CMD - - - */ - GPIO_NC, /* GPIO_S0_SC[033] SD3_CLK - - - */ - GPIO_NC, /* GPIO_S0_SC[034] SD3_D[0] - - - */ - GPIO_NC, /* GPIO_S0_SC[035] SD3_D[1] - - - */ - GPIO_NC, /* GPIO_S0_SC[036] SD3_D[2] - - - */ - GPIO_NC, /* GPIO_S0_SC[037] SD3_D[3] - - - */ - GPIO_NC, /* GPIO_S0_SC[038] SD3_CD# - - - */ - GPIO_NC, /* GPIO_S0_SC[039] SD3_CMD - - - */ - GPIO_NC, /* GPIO_S0_SC[040] SD3_1P8EN - - - */ - GPIO_NC, /* GPIO_S0_SC[041] SD3_PWREN# - - - */ - GPIO_FUNC1, /* GPIO_S0_SC[042] ILB_LPC_AD[0] - - - */ - GPIO_FUNC1, /* GPIO_S0_SC[043] ILB_LPC_AD[1] - - - */ - GPIO_FUNC1, /* GPIO_S0_SC[044] ILB_LPC_AD[2] - - - */ - GPIO_FUNC1, /* GPIO_S0_SC[045] ILB_LPC_AD[3] - - - */ - GPIO_FUNC1, /* GPIO_S0_SC[046] ILB_LPC_FRAME# - - - */ - GPIO_FUNC1, /* GPIO_S0_SC[047] ILB_LPC_CLK[0] - - - */ - GPIO_FUNC1, /* GPIO_S0_SC[048] ILB_LPC_CLK[1] - - - */ - GPIO_FUNC1, /* GPIO_S0_SC[049] ILB_LPC_CLKRUN# - - - */ - GPIO_FUNC1, /* GPIO_S0_SC[050] ILB_LPC_SERIRQ - - - */ - GPIO_FUNC1, /* GPIO_S0_SC[051] PCU_SMB_DATA - - - */ - GPIO_FUNC1, /* GPIO_S0_SC[052] PCU_SMB_CLK - - - */ - GPIO_FUNC1, /* GPIO_S0_SC[053] PCU_SMB_ALERT# - - - */ - GPIO_FUNC1, /* GPIO_S0_SC[054] ILB_8254_SPKR RESERVED - - */ - GPIO_DEFAULT, /* GPIO_S0_SC[055] RESERVED - - - */ - GPIO_DEFAULT, /* GPIO_S0_SC[056] RESERVED - - - */ - GPIO_FUNC1, /* GPIO_S0_SC[057] PCU_UART_TXD - - - */ - GPIO_DEFAULT, /* GPIO_S0_SC[058] RESERVED - - - */ - GPIO_DEFAULT, /* GPIO_S0_SC[059] RESERVED - - - */ - GPIO_DEFAULT, /* GPIO_S0_SC[060] RESERVED - - - */ - GPIO_FUNC1, /* GPIO_S0_SC[061] PCU_UART_RXD - - - */ - GPIO_FUNC1, /* GPIO_S0_SC[062] LPE_I2S2_CLK SATA_DEVSLP[1] RESERVED - */ - GPIO_FUNC1, /* GPIO_S0_SC[063] LPE_I2S2_FRM RESERVED - - */ - GPIO_FUNC1, /* GPIO_S0_SC[064] LPE_I2S2_DATAIN - - - */ - GPIO_FUNC1, /* GPIO_S0_SC[065] LPE_I2S2_DATAOUT - - - */ - GPIO_FUNC1, /* GPIO_S0_SC[066] SIO_SPI_CS# - - - */ - GPIO_FUNC1, /* GPIO_S0_SC[067] SIO_SPI_MISO - - - */ - GPIO_FUNC1, /* GPIO_S0_SC[068] SIO_SPI_MOSI - - - */ - GPIO_FUNC1, /* GPIO_S0_SC[069] SIO_SPI_CLK - - - */ - GPIO_FUNC1, /* GPIO_S0_SC[070] SIO_UART1_RXD RESERVED - - */ - GPIO_FUNC1, /* GPIO_S0_SC[071] SIO_UART1_TXD RESERVED - - */ - GPIO_FUNC1, /* GPIO_S0_SC[072] SIO_UART1_RTS# - - - */ - GPIO_FUNC1, /* GPIO_S0_SC[073] SIO_UART1_CTS# - - - */ - GPIO_FUNC1, /* GPIO_S0_SC[074] SIO_UART2_RXD - - - */ - GPIO_FUNC1, /* GPIO_S0_SC[075] SIO_UART2_TXD - - - */ - GPIO_FUNC1, /* GPIO_S0_SC[076] SIO_UART2_RTS# - - - */ - GPIO_FUNC1, /* GPIO_S0_SC[077] SIO_UART2_CTS# - - - */ - GPIO_FUNC1, /* GPIO_S0_SC[078] SIO_I2C0_DATA - - - */ - GPIO_FUNC1, /* GPIO_S0_SC[079] SIO_I2C0_CLK - - - */ - GPIO_FUNC1, /* GPIO_S0_SC[080] SIO_I2C1_DATA - - - */ - GPIO_FUNC1, /* GPIO_S0_SC[081] SIO_I2C1_CLK RESERVED - - */ - GPIO_FUNC1, /* GPIO_S0_SC[082] SIO_I2C2_DATA - - - */ - GPIO_FUNC1, /* GPIO_S0_SC[083] SIO_I2C2_CLK - - - */ - GPIO_FUNC1, /* GPIO_S0_SC[084] SIO_I2C3_DATA - - - */ - GPIO_FUNC1, /* GPIO_S0_SC[085] SIO_I2C3_CLK - - - */ - GPIO_FUNC1, /* GPIO_S0_SC[086] SIO_I2C4_DATA - - - */ - GPIO_FUNC1, /* GPIO_S0_SC[087] SIO_I2C4_CLK - - - */ - GPIO_FUNC1, /* GPIO_S0_SC[088] SIO_I2C5_DATA - - - */ - GPIO_FUNC1, /* GPIO_S0_SC[089] SIO_I2C5_CLK - - - */ - GPIO_FUNC1, /* GPIO_S0_SC[090] SIO_I2C6_DATA ILB_NMI - - */ - GPIO_FUNC1, /* GPIO_S0_SC[091] SIO_I2C6_CLK SD3_WP - - */ - GPIO_FUNC1, /* RESERVED GPIO_S0_SC[092] - - - */ - GPIO_FUNC1, /* RESERVED GPIO_S0_SC[093] - - - */ - GPIO_DEFAULT, /* GPIO_S0_SC[094] SIO_PWM[0] - - - */ - GPIO_DEFAULT, /* GPIO_S0_SC[095] SIO_PWM[1] - - - */ - GPIO_FUNC1, /* GPIO_S0_SC[096] PMC_PLT_CLK[0] - - - */ - GPIO_FUNC1, /* GPIO_S0_SC[097] PMC_PLT_CLK[1] - - - */ - GPIO_FUNC1, /* GPIO_S0_SC[098] PMC_PLT_CLK[2] - - - */ - GPIO_FUNC1, /* GPIO_S0_SC[099] PMC_PLT_CLK[3] - - - */ - GPIO_FUNC1, /* GPIO_S0_SC[100] PMC_PLT_CLK[4] - - - */ - GPIO_DEFAULT, /* GPIO_S0_SC[101] PMC_PLT_CLK[5] - - - */ - GPIO_END -}; - -/* SSUS GPIOs (GPIO_S5) */ -static const struct soc_gpio_map gpssus_gpio_map[] = { - GPIO_DEFAULT, /* GPIO_S5[00] RESERVED - - - */ - GPIO_DEFAULT, /* GPIO_S5[01] RESERVED RESERVED RESERVED PMC_WAKE_PCIE[1]# */ - GPIO_DEFAULT, /* GPIO_S5[02] RESERVED RESERVED RESERVED PMC_WAKE_PCIE[2]# */ - GPIO_DEFAULT, /* GPIO_S5[03] RESERVED RESERVED RESERVED PMC_WAKE_PCIE[3]# */ - GPIO_DEFAULT, /* GPIO_S5[04] RESERVED RESERVED RESERVED RESERVED */ - GPIO_DEFAULT, /* GPIO_S5[05] PMC_SUSCLK[1] RESERVED RESERVED RESERVED */ - GPIO_DEFAULT, /* GPIO_S5[06] PMC_SUSCLK[2] RESERVED RESERVED RESERVED */ - GPIO_DEFAULT, /* GPIO_S5[07] PMC_SUSCLK[3] RESERVED RESERVED RESERVED */ - GPIO_NC, /* GPIO_S5[08] RESERVED RESERVED RESERVED RESERVED */ - GPIO_NC, /* GPIO_S5[09] RESERVED RESERVED RESERVED RESERVED */ - GPIO_NC, /* GPIO_S5[10] RESERVED RESERVED RESERVED - */ - GPIO_DEFAULT, /* PMC_SUSPWRDNACK GPIO_S5[11] - - - */ - GPIO_FUNC0, /* PMC_SUSCLK[0] GPIO_S5[12] - - - */ - GPIO_FUNC1, /* RESERVED GPIO_S5[13] - - - */ - GPIO_FUNC1, /* RESERVED GPIO_S5[14] USB_ULPI_RST# - - */ - GPIO_FUNC0, /* PMC_WAKE_PCIE[0]# GPIO_S5[15] - - - */ - GPIO_FUNC0, /* PMC_PWRBTN# GPIO_S5[16] - - - */ - GPIO_DEFAULT, /* RESERVED GPIO_S5[17] - - - */ - GPIO_FUNC1, /* PMC_SUS_STAT# GPIO_S5[18] - - - */ - GPIO_FUNC0, /* USB_OC[0]# GPIO_S5[19] - - - */ - GPIO_FUNC0, /* USB_OC[1]# GPIO_S5[20] - - - */ - GPIO_FUNC0, /* PCU_SPI_CS[1]# GPIO_S5[21] - - - */ - GPIO_DEFAULT, /* GPIO_S5[22] RESERVED RESERVED RESERVED RESERVED */ - GPIO_DEFAULT, /* GPIO_S5[23] RESERVED RESERVED RESERVED RESERVED */ - GPIO_DEFAULT, /* GPIO_S5[24] RESERVED RESERVED RESERVED RESERVED */ - GPIO_DEFAULT, /* GPIO_S5[25] RESERVED RESERVED RESERVED RESERVED */ - GPIO_DEFAULT, /* GPIO_S5[26] RESERVED RESERVED RESERVED RESERVED */ - GPIO_DEFAULT, /* GPIO_S5[27] RESERVED RESERVED RESERVED RESERVED */ - GPIO_DEFAULT, /* GPIO_S5[28] RESERVED RESERVED RESERVED RESERVED */ - GPIO_DEFAULT, /* GPIO_S5[29] RESERVED RESERVED RESERVED RESERVED */ - GPIO_DEFAULT, /* GPIO_S5[30] RESERVED RESERVED RESERVED RESERVED */ - GPIO_DEFAULT, /* GPIO_S5[31] USB_ULPI_CLK RESERVED RESERVED - */ - GPIO_DEFAULT, /* GPIO_S5[32] USB_ULPI_DATA[0] RESERVED RESERVED - */ - GPIO_DEFAULT, /* GPIO_S5[33] USB_ULPI_DATA[1] RESERVED RESERVED - */ - GPIO_DEFAULT, /* GPIO_S5[34] USB_ULPI_DATA[2] RESERVED RESERVED - */ - GPIO_DEFAULT, /* GPIO_S5[35] USB_ULPI_DATA[3] RESERVED RESERVED - */ - GPIO_DEFAULT, /* GPIO_S5[36] USB_ULPI_DATA[4] RESERVED RESERVED - */ - GPIO_DEFAULT, /* GPIO_S5[37] USB_ULPI_DATA[5] RESERVED RESERVED - */ - GPIO_NC, /* GPIO_S5[38] USB_ULPI_DATA[6] RESERVED RESERVED - */ - GPIO_NC, /* GPIO_S5[39] USB_ULPI_DATA[7] RESERVED RESERVED - */ - GPIO_NC, /* GPIO_S5[40] USB_ULPI_DIR RESERVED RESERVED - */ - GPIO_NC, /* GPIO_S5[41] USB_ULPI_NXT RESERVED RESERVED - */ - GPIO_DEFAULT, /* GPIO_S5[42] USB_ULPI_STP RESERVED RESERVED - */ - GPIO_DEFAULT, /* GPIO_S5[43] USB_ULPI_REFCLK RESERVED RESERVED - */ - GPIO_END -}; - -static struct soc_gpio_config gpio_config = { - .ncore = gpncore_gpio_map, - .score = gpscore_gpio_map, - .ssus = gpssus_gpio_map, - .core_dirq = NULL, - .sus_dirq = NULL, -}; - -struct soc_gpio_config* mainboard_get_gpios(void) -{ - return &gpio_config; -} diff --git a/src/mainboard/intel/bayleybay_fsp/irqroute.c b/src/mainboard/intel/bayleybay_fsp/irqroute.c deleted file mode 100644 index db8c512a43..0000000000 --- a/src/mainboard/intel/bayleybay_fsp/irqroute.c +++ /dev/null @@ -1,18 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2013 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include "irqroute.h" - -DEFINE_IRQ_ROUTES; diff --git a/src/mainboard/intel/bayleybay_fsp/irqroute.h b/src/mainboard/intel/bayleybay_fsp/irqroute.h deleted file mode 100644 index febbcc8257..0000000000 --- a/src/mainboard/intel/bayleybay_fsp/irqroute.h +++ /dev/null @@ -1,82 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2013 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef IRQROUTE_H -#define IRQROUTE_H - -#include -#include - -/* - *IR02h GFX INT(A) - PIRQ A - *IR10h EMMC INT(ABCD) - PIRQ DEFG - *IR11h SDIO INT(A) - PIRQ B - *IR12h SD INT(A) - PIRQ C - *IR13h SATA INT(A) - PIRQ D - *IR14h XHCI INT(A) - PIRQ E - *IR15h LP Audio INT(A) - PIRQ F - *IR17h MMC INT(A) - PIRQ F - *IR18h SIO INT(ABCD) - PIRQ BADC - *IR1Ah TXE INT(A) - PIRQ F - *IR1Bh HD Audio INT(A) - PIRQ G - *IR1Ch PCIe INT(ABCD) - PIRQ EFGH - *IR1Dh EHCI INT(A) - PIRQ D - *IR1Eh SIO INT(ABCD) - PIRQ BDEF - *IR1Fh LPC INT(ABCD) - PIRQ HGBC - */ - -/* PCIe bridge routing */ -#define BRIDGE1_DEV PCIE_DEV - -/* PCI bridge IRQs need to be updated in both tables and need to match */ -#define PCIE_BRIDGE_IRQ_ROUTES \ - PCIE_BRIDGE_DEV(RP, BRIDGE1_DEV, E, F, G, H) - -/* Devices set as A, A, A, A evaluate as 0, and don't get set */ -#define PCI_DEV_PIRQ_ROUTES \ - PCI_DEV_PIRQ_ROUTE(GFX_DEV, A, A, A, B), \ - PCI_DEV_PIRQ_ROUTE(EMMC_DEV, D, E, F, G), \ - PCI_DEV_PIRQ_ROUTE(SDIO_DEV, B, A, A, A), \ - PCI_DEV_PIRQ_ROUTE(SD_DEV, C, A, A, A), \ - PCI_DEV_PIRQ_ROUTE(SATA_DEV, D, A, A, A), \ - PCI_DEV_PIRQ_ROUTE(XHCI_DEV, E, A, A, A), \ - PCI_DEV_PIRQ_ROUTE(LPE_DEV, F, A, A, A), \ - PCI_DEV_PIRQ_ROUTE(MMC45_DEV, F, A, A, A), \ - PCI_DEV_PIRQ_ROUTE(SIO1_DEV, B, A, D, C), \ - PCI_DEV_PIRQ_ROUTE(TXE_DEV, F, A, A, A), \ - PCI_DEV_PIRQ_ROUTE(HDA_DEV, G, A, A, A), \ - PCI_DEV_PIRQ_ROUTE(BRIDGE1_DEV, E, F, G, H), \ - PCI_DEV_PIRQ_ROUTE(EHCI_DEV, D, A, A, A), \ - PCI_DEV_PIRQ_ROUTE(SIO2_DEV, B, D, E, F), \ - PCI_DEV_PIRQ_ROUTE(PCU_DEV, H, G, B, C) - -/* - * Route each PIRQ[A-H] to a PIC IRQ[0-15] - * Reserved: 0, 1, 2, 8, 13 - * PS2 keyboard: 12 - * ACPI/SCI: 9 - * Floppy: 6 - */ -#define PIRQ_PIC_ROUTES \ - PIRQ_PIC(A, 4), \ - PIRQ_PIC(B, 5), \ - PIRQ_PIC(C, 7), \ - PIRQ_PIC(D, 10), \ - PIRQ_PIC(E, 11), \ - PIRQ_PIC(F, 12), \ - PIRQ_PIC(G, 14), \ - PIRQ_PIC(H, 15) - -#endif /* IRQROUTE_H */ diff --git a/src/mainboard/intel/bayleybay_fsp/mainboard.c b/src/mainboard/intel/bayleybay_fsp/mainboard.c deleted file mode 100644 index f6ba0355ee..0000000000 --- a/src/mainboard/intel/bayleybay_fsp/mainboard.c +++ /dev/null @@ -1,35 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007-2009 coresystems GmbH - * Copyright (C) 2011 The ChromiumOS Authors. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include -#if CONFIG(VGA_ROM_RUN) -#include -#endif - -/* - * mainboard_enable is executed as first thing after enumerate_buses(). - * This is the earliest point to add customization. - */ -static void mainboard_enable(struct device *dev) -{ - -} - -struct chip_operations mainboard_ops = { - .enable_dev = mainboard_enable, -}; diff --git a/src/mainboard/intel/bayleybay_fsp/romstage.c b/src/mainboard/intel/bayleybay_fsp/romstage.c deleted file mode 100644 index a6ccd960b1..0000000000 --- a/src/mainboard/intel/bayleybay_fsp/romstage.c +++ /dev/null @@ -1,168 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2013 Google Inc. - * Copyright (C) 2013 Sage Electronic Engineering, LLC. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -/** - * /brief mainboard call for setup that needs to be done before fsp init - * - */ -void early_mainboard_romstage_entry() -{ - -} - -/** - * Get function disables - most of these will be done automatically - * @param fd_mask - * @param fd2_mask - */ -void get_func_disables(uint32_t *fd_mask, uint32_t *fd2_mask) -{ - -} - -/** - * /brief mainboard call for setup that needs to be done after fsp init - * - */ -void late_mainboard_romstage_entry() -{ - -} - -const uint32_t mAzaliaVerbTableData13[] = { -/* - *ALC262 Verb Table - 10EC0262 - */ - /* Pin Complex (NID 0x11) */ - 0x01171CF0, - 0x01171D11, - 0x01171E11, - 0x01171F41, - /* Pin Complex (NID 0x12) */ - 0x01271CF0, - 0x01271D11, - 0x01271E11, - 0x01271F41, - /* Pin Complex (NID 0x14) */ - 0x01471C10, - 0x01471D40, - 0x01471E01, - 0x01471F01, - /* Pin Complex (NID 0x15) */ - 0x01571CF0, - 0x01571D11, - 0x01571E11, - 0x01571F41, - /* Pin Complex (NID 0x16) */ - 0x01671CF0, - 0x01671D11, - 0x01671E11, - 0x01671F41, - /* Pin Complex (NID 0x18) */ - 0x01871C20, - 0x01871D98, - 0x01871EA1, - 0x01871F01, - /* Pin Complex (NID 0x19) */ - 0x01971C21, - 0x01971D98, - 0x01971EA1, - 0x01971F02, - /* Pin Complex (NID 0x1A) */ - 0x01A71C2F, - 0x01A71D30, - 0x01A71E81, - 0x01A71F01, - /* Pin Complex (NID 0x1B) */ - 0x01B71C1F, - 0x01B71D40, - 0x01B71E21, - 0x01B71F02, - /* Pin Complex (NID 0x1C) */ - 0x01C71CF0, - 0x01C71D11, - 0x01C71E11, - 0x01C71F41, - /* Pin Complex (NID 0x1D) */ - 0x01D71C01, - 0x01D71DC6, - 0x01D71E14, - 0x01D71F40, - /* Pin Complex (NID 0x1E) */ - 0x01E71CF0, - 0x01E71D11, - 0x01E71E11, - 0x01E71F41, - /* Pin Complex (NID 0x1F) */ - 0x01F71CF0, - 0x01F71D11, - 0x01F71E11, - 0x01F71F41 }; - -const PCH_AZALIA_VERB_TABLE mAzaliaVerbTable[] = { { -/* - * VerbTable: (RealTek ALC262) - * Revision ID = 0xFF, support all steps - * Codec Verb Table For AZALIA - * Codec Address: CAd value (0/1/2) - * Codec Vendor: 0x10EC0262 - */ - { - 0x10EC0262, /* Vendor ID/Device IDA */ - 0x0000, /* SubSystem ID */ - 0xFF, /* Revision IDA */ - 0x01, /* Front panel support (1=yes, 2=no) */ - 0x000B, /* Number of Rear Jacks = 11 */ - 0x0002 /* Number of Front Jacks = 2 */ - }, - (uint32_t *)mAzaliaVerbTableData13 } }; - -const PCH_AZALIA_CONFIG mainboard_AzaliaConfig = { - .Pme = 1, - .DS = 1, - .DA = 0, - .HdmiCodec = 1, - .AzaliaVCi = 1, - .Rsvdbits = 0, - .AzaliaVerbTableNum = 1, - .AzaliaVerbTable = (PCH_AZALIA_VERB_TABLE *)mAzaliaVerbTable, - .ResetWaitTimer = 300 }; - -/** /brief customize fsp parameters here if needed - */ -void romstage_fsp_rt_buffer_callback(FSP_INIT_RT_BUFFER *FspRtBuffer) -{ - UPD_DATA_REGION *UpdData = FspRtBuffer->Common.UpdDataRgnPtr; - - /* Initialize the Azalia Verb Tables to mainboard specific version */ - UpdData->AzaliaConfigPtr = (UINT32)&mainboard_AzaliaConfig; - - /* Disable 2nd DIMM on Bakersport*/ -#if CONFIG(BOARD_INTEL_BAKERSPORT_FSP) - UpdData->PcdMrcInitSPDAddr2 = 0x00; /* cannot use SPD_ADDR_DISABLED at this point */ -#endif -} diff --git a/src/mainboard/intel/bayleybay_fsp/thermal.h b/src/mainboard/intel/bayleybay_fsp/thermal.h deleted file mode 100644 index 3973ca8fe9..0000000000 --- a/src/mainboard/intel/bayleybay_fsp/thermal.h +++ /dev/null @@ -1,29 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 The Chromium OS Authors. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef MAINBOARD_THERMAL_H -#define MAINBOARD_THERMAL_H - - -/* Temperature which OS will shutdown at */ -#define CRITICAL_TEMPERATURE 100 - -/* Temperature which OS will throttle CPU */ -#define PASSIVE_TEMPERATURE 90 - -/* Tj_max value for calculating PECI CPU temperature */ -#define MAX_TEMPERATURE 100 - -#endif /* MAINBOARD_THERMAL_H */ diff --git a/src/mainboard/intel/minnowmax/Kconfig b/src/mainboard/intel/minnowmax/Kconfig deleted file mode 100644 index ca24c92aa6..0000000000 --- a/src/mainboard/intel/minnowmax/Kconfig +++ /dev/null @@ -1,64 +0,0 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2013-2014 Sage Electronic Engineering, LLC. -## Copyright (C) 2014 Intel Corporation -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; version 2 of the License. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## - -if BOARD_INTEL_MINNOWMAX - -config BOARD_SPECIFIC_OPTIONS - def_bool y - select SOC_INTEL_FSP_BAYTRAIL - select BOARD_ROMSIZE_KB_8192 - select HAVE_ACPI_TABLES - select HAVE_OPTION_TABLE - -config MAINBOARD_DIR - string - default "intel/minnowmax" - -config MAINBOARD_PART_NUMBER - string - default "Minnow Max" - -config MAX_CPUS - int - default 16 - -config FSP_FILE - string - default "../intel/fsp/baytrail/BAYTRAIL_FSP.fd" - -config CBFS_SIZE - hex - default 0x00300000 - -config ENABLE_FSP_FAST_BOOT - bool - depends on HAVE_FSP_BIN - default y - -config VIRTUAL_ROM_SIZE - hex - depends on ENABLE_FSP_FAST_BOOT - default 0x800000 - -config POST_DEVICE - bool - default n - -config VGA_BIOS - bool - default y if FSP_PACKAGE_DEFAULT - -endif # BOARD_INTEL_MINNOWMAX diff --git a/src/mainboard/intel/minnowmax/Kconfig.name b/src/mainboard/intel/minnowmax/Kconfig.name deleted file mode 100644 index abe9225960..0000000000 --- a/src/mainboard/intel/minnowmax/Kconfig.name +++ /dev/null @@ -1,2 +0,0 @@ -config BOARD_INTEL_MINNOWMAX - bool "Minnow Max" diff --git a/src/mainboard/intel/minnowmax/Makefile.inc b/src/mainboard/intel/minnowmax/Makefile.inc deleted file mode 100644 index 3074df2138..0000000000 --- a/src/mainboard/intel/minnowmax/Makefile.inc +++ /dev/null @@ -1,17 +0,0 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2013 Google Inc. -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; version 2 of the License. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## - -ramstage-y += gpio.c -ramstage-y += irqroute.c diff --git a/src/mainboard/intel/minnowmax/acpi/ec.asl b/src/mainboard/intel/minnowmax/acpi/ec.asl deleted file mode 100644 index e69de29bb2..0000000000 diff --git a/src/mainboard/intel/minnowmax/acpi/mainboard.asl b/src/mainboard/intel/minnowmax/acpi/mainboard.asl deleted file mode 100644 index b032ee189d..0000000000 --- a/src/mainboard/intel/minnowmax/acpi/mainboard.asl +++ /dev/null @@ -1,20 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 Google Inc. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -Device (PWRB) -{ - Name(_HID, EisaId("PNP0C0C")) -} diff --git a/src/mainboard/intel/minnowmax/acpi/superio.asl b/src/mainboard/intel/minnowmax/acpi/superio.asl deleted file mode 100644 index e69de29bb2..0000000000 diff --git a/src/mainboard/intel/minnowmax/acpi_tables.c b/src/mainboard/intel/minnowmax/acpi_tables.c deleted file mode 100644 index fe95a3106c..0000000000 --- a/src/mainboard/intel/minnowmax/acpi_tables.c +++ /dev/null @@ -1,48 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2012 Google Inc. - * Copyright (C) 2013-2014 Sage Electronic Engineering, LLC. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include - -void acpi_create_gnvs(global_nvs_t *gnvs) -{ - acpi_init_gnvs(gnvs); - - /* No TPM Present */ - gnvs->tpmp = 0; - -} - -unsigned long acpi_fill_madt(unsigned long current) -{ - /* Local APICs */ - current = acpi_create_madt_lapics(current); - - /* IOAPIC */ - current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, - 2, IO_APIC_ADDR, 0); - - current = acpi_madt_irq_overrides(current); - - return current; -} diff --git a/src/mainboard/intel/minnowmax/board_info.txt b/src/mainboard/intel/minnowmax/board_info.txt deleted file mode 100644 index 5af79f8de4..0000000000 --- a/src/mainboard/intel/minnowmax/board_info.txt +++ /dev/null @@ -1,4 +0,0 @@ -Category: sbc -ROM protocol: SPI -Flashrom support: y -Release year: 2014 diff --git a/src/mainboard/intel/minnowmax/cmos.layout b/src/mainboard/intel/minnowmax/cmos.layout deleted file mode 100644 index 4cb5106191..0000000000 --- a/src/mainboard/intel/minnowmax/cmos.layout +++ /dev/null @@ -1,108 +0,0 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2007-2008 coresystems GmbH -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; version 2 of the License. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## - -# ----------------------------------------------------------------- -entries - -# ----------------------------------------------------------------- -# Status Register A -# ----------------------------------------------------------------- -# Status Register B -# ----------------------------------------------------------------- -# Status Register C -#96 4 r 0 status_c_rsvd -#100 1 r 0 uf_flag -#101 1 r 0 af_flag -#102 1 r 0 pf_flag -#103 1 r 0 irqf_flag -# ----------------------------------------------------------------- -# Status Register D -#104 7 r 0 status_d_rsvd -#111 1 r 0 valid_cmos_ram -# ----------------------------------------------------------------- -# Diagnostic Status Register -#112 8 r 0 diag_rsvd1 - -# ----------------------------------------------------------------- -0 120 r 0 reserved_memory -#120 264 r 0 unused - -# ----------------------------------------------------------------- -# RTC_BOOT_BYTE (coreboot hardcoded) -384 1 e 4 boot_option -388 4 h 0 reboot_counter -#390 2 r 0 unused? - -# ----------------------------------------------------------------- -# coreboot config options: console -#392 3 r 0 unused -395 4 e 6 debug_level -#399 1 r 0 unused - -# coreboot config options: cpu -400 1 e 2 hyper_threading -#401 7 r 0 unused - -# coreboot config options: southbridge -408 1 e 1 nmi -409 2 e 7 power_on_after_fail -411 2 e 8 use_xhci_over_ehci -#413 3 r 0 unused - -# MRC Scrambler Seed values -896 32 r 0 mrc_scrambler_seed -928 32 r 0 mrc_scrambler_seed_s3 - -# coreboot config options: check sums -984 16 h 0 check_sum -#1000 24 r 0 amd_reserved - -#save timestamps in pre-ram boot areas -1720 64 h 0 timestamp_value1 -1784 64 h 0 timestamp_value2 -1848 64 h 0 timestamp_value3 -1912 64 h 0 timestamp_value4 -1976 64 h 0 timestamp_value5 - -# ----------------------------------------------------------------- - -enumerations - -#ID value text -1 0 Disable -1 1 Enable -2 0 Enable -2 1 Disable -4 0 Fallback -4 1 Normal -6 0 Emergency -6 1 Alert -6 2 Critical -6 3 Error -6 4 Warning -6 5 Notice -6 6 Info -6 7 Debug -6 8 Spew -7 0 Disable -7 1 Enable -7 2 Keep -8 0 EHCI -8 1 XHCI -8 2 Default -# ----------------------------------------------------------------- -checksums - -checksum 392 415 984 diff --git a/src/mainboard/intel/minnowmax/devicetree.cb b/src/mainboard/intel/minnowmax/devicetree.cb deleted file mode 100644 index 873b5898e7..0000000000 --- a/src/mainboard/intel/minnowmax/devicetree.cb +++ /dev/null @@ -1,93 +0,0 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2013-2014 Sage Electronic Engineering, LLC. -## Copyright (C) 2014 Intel Corporation -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; version 2 of the License. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## - -chip soc/intel/fsp_baytrail - - #### ACPI Register Settings #### - register "fadt_pm_profile" = "PM_UNSPECIFIED" - register "fadt_boot_arch" = "ACPI_FADT_LEGACY_FREE" - - #### FSP register settings #### - register "PcdSataMode" = "SATA_MODE_AHCI" - register "PcdMrcInitSPDAddr1" = "SPD_ADDR_DEFAULT" - register "PcdMrcInitSPDAddr2" = "SPD_ADDR_DEFAULT" - register "PcdMrcInitMmioSize" = "MMIO_SIZE_DEFAULT" - register "PcdeMMCBootMode" = "EMMC_FOLLOWS_DEVICETREE" - register "PcdIgdDvmt50PreAlloc" = "IGD_MEMSIZE_DEFAULT" - register "PcdApertureSize" = "APERTURE_SIZE_DEFAULT" - register "PcdGttSize" = "GTT_SIZE_DEFAULT" - register "PcdLpssSioEnablePciMode" = "LPSS_PCI_MODE_DEFAULT" - register "AzaliaAutoEnable" = "AZALIA_FOLLOWS_DEVICETREE" - register "LpeAcpiModeEnable" = "LPE_ACPI_MODE_DISABLED" - register "IgdRenderStandby" = "IGD_RENDER_STANDBY_ENABLE" - register "EnableMemoryDown" = "MEMORY_DOWN_ENABLE" - register "DRAMSpeed" = "DRAM_SPEED_1066MHZ" - register "DRAMType" = "DRAM_TYPE_DDR3L" - register "DIMM0Enable" = "DIMM0_ENABLE" - register "DIMM1Enable" = "DIMM1_DISABLE" - register "DIMMDWidth" = "DIMM_DWIDTH_X16" - register "DIMMDensity" = "DIMM_DENSITY_2G_BIT" # Setting for 1GB board - modified runtime for 2GB board in romstage.c to DIMM_DENSITY_4G_BIT - register "DIMMBusWidth" = "DIMM_BUS_WIDTH_64BIT" - register "DIMMSides" = "DIMM_SIDES_1RANK" - register "DIMMtCL" = "11" - register "DIMMtRPtRCD" = "11" - register "DIMMtWR" = "12" - register "DIMMtWTR" = "6" - register "DIMMtRRD" = "6" - register "DIMMtRTP" = "6" - register "DIMMtFAW" = "20" - - device cpu_cluster 0 on - device lapic 0 on end - end - - device domain 0 on - device pci 00.0 on end # 8086 0F00 - SoC router - - device pci 02.0 on end # 8086 0F31 - GFX micro HDMI - device pci 03.0 off end # 8086 0F38 - MIPI - - - device pci 10.0 off end # 8086 0F14 - EMMC Port - - device pci 11.0 off end # 8086 0F15 - SDIO Port - - device pci 12.0 on end # 8086 0F16 - SD Port MicroSD on SD3 - device pci 13.0 on end # 8086 0F23 - SATA AHCI Onboard & HSEC - device pci 14.0 on end # 8086 0F35 - USB XHCI - Onboard & HSEC - Enabling both EHCI and XHCI will default to EHCI if not changed at runtime - device pci 15.0 on end # 8086 0F28 - LP Engine Audio LSEC - device pci 17.0 off end # 8086 0F50 - MMC Port - - device pci 18.0 on end # 8086 0F40 - SIO - DMA - - device pci 18.1 off end # 8086 0F41 - I2C Port 1 (0) - - device pci 18.2 on end # 8086 0F42 - I2C Port 2 (1) - (testpoints) - device pci 18.3 off end # 8086 0F43 - I2C Port 3 (2) - - device pci 18.4 off end # 8086 0F44 - I2C Port 4 (3) - - device pci 18.5 off end # 8086 0F45 - I2C Port 5 (4) - - device pci 18.6 on end # 8086 0F46 - I2C Port 6 (5) LSEC - device pci 18.7 on end # 8086 0F47 - I2C Port 7 (6) HSEC - device pci 1a.0 on end # 8086 0F18 - TXE - - device pci 1b.0 off end # 8086 0F04 - HD Audio - - device pci 1c.0 on end # 8086 0F48 - PCIe Port 1 (0) Must remain on - device pci 1c.1 on end # 8086 0F4A - PCIe Port 2 (1) Onboard GBE (some models) - device pci 1c.2 on end # 8086 0F4C - PCIe Port 3 (2) Onboard GBE - device pci 1c.3 on end # 8086 0F4E - PCIe Port 4 (3) HSEC - device pci 1d.0 on end # 8086 0F34 - USB EHCI - Enabling both EHCI and XHCI will default to EHCI if not changed at runtime - device pci 1e.0 on end # 8086 0F06 - SIO - DMA - - device pci 1e.1 on end # 8086 0F08 - PWM 1 LSEC - device pci 1e.2 on end # 8086 0F09 - PWM 2 LSEC - device pci 1e.3 on end # 8086 0F0A - HSUART 1 LSEC - device pci 1e.4 on end # 8086 0F0C - HSUART 2 LSEC - device pci 1e.5 on end # 8086 0F0E - SPI LSEC - device pci 1f.0 on end # 8086 0F1C - LPC bridge No connector - device pci 1f.3 on end # 8086 0F12 - SMBus 0 SPC - end -end diff --git a/src/mainboard/intel/minnowmax/dsdt.asl b/src/mainboard/intel/minnowmax/dsdt.asl deleted file mode 100644 index bea6af7973..0000000000 --- a/src/mainboard/intel/minnowmax/dsdt.asl +++ /dev/null @@ -1,54 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007-2009 coresystems GmbH - * Copyright (C) 2011 Google Inc. - * Copyright (C) 2014 Sage Electronic Engineering, LLC. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#define INCLUDE_LPE 1 -#define INCLUDE_SCC 1 -#define INCLUDE_EHCI 1 -#define INCLUDE_XHCI 1 -#define INCLUDE_LPSS 1 - - -#include -DefinitionBlock( - "dsdt.aml", - "DSDT", - 0x02, // DSDT revision: ACPI v2.0 and up - OEM_ID, - ACPI_TABLE_CREATOR, - 0x20110725 // OEM revision -) -{ - // Some generic macros - #include - - // global NVS and variables - #include - - #include - - Scope (\_SB) { - Device (PCI0) - { - #include - } - } - - /* Chipset specific sleep states */ - #include - - #include "acpi/mainboard.asl" -} diff --git a/src/mainboard/intel/minnowmax/fadt.c b/src/mainboard/intel/minnowmax/fadt.c deleted file mode 100644 index 4194bfc324..0000000000 --- a/src/mainboard/intel/minnowmax/fadt.c +++ /dev/null @@ -1,29 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007-2009 coresystems GmbH - * Copyright (C) 2013-2014 Sage Electronic Engineering, LLC. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include - -void acpi_create_fadt(acpi_fadt_t *fadt, acpi_facs_t *facs, void *dsdt) -{ - acpi_header_t *header = &(fadt->header); - - acpi_fill_in_fadt(fadt, facs, dsdt); - - /* Platform specific customizations go here */ - - header->checksum = acpi_checksum((void *) fadt, sizeof(acpi_fadt_t)); -} diff --git a/src/mainboard/intel/minnowmax/gpio.c b/src/mainboard/intel/minnowmax/gpio.c deleted file mode 100644 index b0f78c8b57..0000000000 --- a/src/mainboard/intel/minnowmax/gpio.c +++ /dev/null @@ -1,232 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2013 Google Inc. - * Copyright (C) 2014 Sage Electronic Engineering, LLC. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include "irqroute.h" - -/* - * For multiplexed functions, look in EDS: - * 10.3 Ball Name and Function by Location - * - * The pads list is in the BWG_VOL2 Rev1p2: - * Note that Pad # is not the same as GPIO# - * 37 GPIO Handling: - * Table 37-1. SCORE Pads List - * Table 37-2. SSUSORE Pads List - */ - -/* NCORE GPIOs */ -static const struct soc_gpio_map gpncore_gpio_map[] = { - GPIO_FUNC2, // GPIO_S0_NC[00] - HDMI_HPD - GPIO_FUNC2, // GPIO_S0_NC[01] - HDMI_DDCDAT - GPIO_FUNC2, // GPIO_S0_NC[02] - HDMI_DDCCLK - GPIO_NC, // GPIO_S0_NC[03] - No Connect - GPIO_NC, // GPIO_S0_NC[04] - No Connect - GPIO_NC, // GPIO_S0_NC[05] - No Connect - GPIO_NC, // GPIO_S0_NC[06] - No Connect - GPIO_FUNC2, // GPIO_S0_NC[07] - DDI1_DDCDAT - GPIO_NC, // GPIO_S0_NC[08] - No Connect - GPIO_NC, // GPIO_S0_NC[09] - No Connect - GPIO_NC, // GPIO_S0_NC[10] - No Connect - GPIO_NC, // GPIO_S0_NC[11] - No Connect - GPIO_FUNC(0, PULL_UP, 20K), // GPIO_S0_NC[12] - TP15 - GPIO_NC, // GPIO_S0_NC[13] - No Connect - GPIO_NC, // GPIO_S0_NC[14] - No Connect - GPIO_NC, // GPIO_S0_NC[15] - No Connect - GPIO_NC, // GPIO_S0_NC[16] - No Connect - GPIO_NC, // GPIO_S0_NC[17] - No Connect - GPIO_NC, // GPIO_S0_NC[18] - No Connect - GPIO_NC, // GPIO_S0_NC[19] - No Connect - GPIO_NC, // GPIO_S0_NC[20] - No Connect - GPIO_NC, // GPIO_S0_NC[21] - No Connect - GPIO_NC, // GPIO_S0_NC[22] - No Connect - GPIO_NC, // GPIO_S0_NC[23] - No Connect - GPIO_NC, // GPIO_S0_NC[24] - No Connect - GPIO_NC, // GPIO_S0_NC[25] - No Connect - GPIO_NC, // GPIO_S0_NC[26] - No Connect - GPIO_END -}; - -/* SCORE GPIOs (GPIO_S0_SC_XX) */ -static const struct soc_gpio_map gpscore_gpio_map[] = { - GPIO_FUNC1, // GPIO_S0_SC[000] - SATA_GP0 - GPIO_FUNC1, // GPIO_S0_SC[001] - SATA_GP1 - GPIO_FUNC1, // GPIO_S0_SC[002] - SATA_LED_B - GPIO_FUNC1, // GPIO_S0_SC[003] - PCIE_CLKREQ_0 - GPIO_FUNC1, // GPIO_S0_SC[004] - PCIE_CLKREQ_1 - GPIO_FUNC1, // GPIO_S0_SC[005] - PCIE_CLKREQ_2 - GPIO_FUNC1, // GPIO_S0_SC[006] - PCIE_CLKREQ_3 - GPIO_FUNC2, // GPIO_S0_SC[007] - SD3_WP - GPIO_NC, // GPIO_S0_SC[008] - No Connect - GPIO_NC, // GPIO_S0_SC[009] - No Connect - GPIO_NC, // GPIO_S0_SC[010] - No Connect - GPIO_NC, // GPIO_S0_SC[011] - No Connect - GPIO_NC, // GPIO_S0_SC[012] - No Connect - GPIO_NC, // GPIO_S0_SC[013] - No Connect - GPIO_NC, // GPIO_S0_SC[014] - No Connect - GPIO_NC, // GPIO_S0_SC[015] - No Connect - GPIO_NC, // GPIO_S0_SC[016] - No Connect - GPIO_NC, // GPIO_S0_SC[017] - No Connect - GPIO_NC, // GPIO_S0_SC[018] - No Connect - GPIO_NC, // GPIO_S0_SC[019] - No Connect - GPIO_NC, // GPIO_S0_SC[020] - No Connect - GPIO_NC, // GPIO_S0_SC[021] - No Connect - GPIO_NC, // GPIO_S0_SC[022] - No Connect - GPIO_NC, // GPIO_S0_SC[023] - No Connect - GPIO_NC, // GPIO_S0_SC[024] - No Connect - GPIO_NC, // GPIO_S0_SC[025] - No Connect - GPIO_NC, // GPIO_S0_SC[026] - No Connect - GPIO_NC, // GPIO_S0_SC[027] - No Connect - GPIO_NC, // GPIO_S0_SC[028] - No Connect - GPIO_NC, // GPIO_S0_SC[029] - No Connect - GPIO_NC, // GPIO_S0_SC[030] - No Connect - GPIO_NC, // GPIO_S0_SC[031] - No Connect - GPIO_NC, // GPIO_S0_SC[032] - No Connect - GPIO_FUNC1, // GPIO_S0_SC[033] - SD3_CLK - GPIO_FUNC1, // GPIO_S0_SC[034] - SD3_D0 - GPIO_FUNC1, // GPIO_S0_SC[035] - SD3_D1 - GPIO_FUNC1, // GPIO_S0_SC[036] - SD3_D2 - GPIO_FUNC1, // GPIO_S0_SC[037] - SD3_D3 - GPIO_FUNC1, // GPIO_S0_SC[038] - SD3_CD# - GPIO_FUNC1, // GPIO_S0_SC[039] - SD3_CMD - GPIO_FUNC1, // GPIO_S0_SC[040] - TP12 (SD3_1P8EN) - GPIO_FUNC1, // GPIO_S0_SC[041] - TP11 (/SD3_PWREN) - GPIO_NC, // GPIO_S0_SC[042] - No Connect - GPIO_NC, // GPIO_S0_SC[043] - No Connect - GPIO_NC, // GPIO_S0_SC[044] - No Connect - GPIO_NC, // GPIO_S0_SC[045] - No Connect - GPIO_NC, // GPIO_S0_SC[046] - No Connect - GPIO_NC, // GPIO_S0_SC[047] - No Connect - GPIO_NC, // GPIO_S0_SC[048] - No Connect - GPIO_NC, // GPIO_S0_SC[049] - No Connect - GPIO_NC, // GPIO_S0_SC[050] - No Connect - GPIO_FUNC1, // GPIO_S0_SC[051] - PCU_SMB_DATA - GPIO_FUNC1, // GPIO_S0_SC[052] - PCU_SMB_CLK - GPIO_FUNC1, // GPIO_S0_SC[053] - PCU_SMB_ALERT - GPIO_FUNC1, // GPIO_S0_SC[054] - ILB_8254_SPKR - GPIO_FUNC(0, PULL_UP, 20K), // GPIO_S0_SC[055] - TP8 (GPIO_S0_SC_55) - GPIO_FUNC0, // GPIO_S0_SC[056] - GPIO_S0_SC_56 - GPIO_FUNC1, // GPIO_S0_SC[057] - PCU_UART3_TXD - GPIO_FUNC(0, PULL_UP, 20K), // GPIO_S0_SC[058] - TP9 (GPIO_S0_SC_58) - GPIO_FUNC0, // GPIO_S0_SC[059] - HDMI_DCDC_ENB - GPIO_FUNC0, // GPIO_S0_SC[060] - HDMI_LDSW_ENB - GPIO_FUNC1, // GPIO_S0_SC[061] - PCU_UART3_RXD - GPIO_FUNC1, // GPIO_S0_SC[062] - LPE_I2S_CLK - GPIO_FUNC1, // GPIO_S0_SC[063] - LPE_I2S_FRM - GPIO_FUNC1, // GPIO_S0_SC[064] - LPE_I2S_DATIN - GPIO_FUNC1, // GPIO_S0_SC[065] - LPE_I2S_DATOUT - GPIO_FUNC1, // GPIO_S0_SC[066] - SOC_SIO_SPI_CS1 - GPIO_FUNC1, // GPIO_S0_SC[067] - SOC_SIO_SPI_MISO - GPIO_FUNC1, // GPIO_S0_SC[068] - SOC_SIO_SPI_MOSI - GPIO_FUNC1, // GPIO_S0_SC[069] - SOC_SIO_SPI_CLK - GPIO_FUNC1, // GPIO_S0_SC[070] - SIO_UART1_RXD - GPIO_FUNC1, // GPIO_S0_SC[071] - SIO_UART1_TXD - GPIO_FUNC1, // GPIO_S0_SC[072] - SIO_UART1_RTSB - GPIO_FUNC1, // GPIO_S0_SC[073] - SIO_UART1_CTSB - GPIO_FUNC1, // GPIO_S0_SC[074] - SIO_UART2_RXD - GPIO_FUNC1, // GPIO_S0_SC[075] - SIO_UART2_TXD - GPIO_NC, // GPIO_S0_SC[076] - No Connect - GPIO_NC, // GPIO_S0_SC[077] - No Connect - GPIO_NC, // GPIO_S0_SC[078] - No Connect - GPIO_NC, // GPIO_S0_SC[079] - No Connect - GPIO_FUNC1, // GPIO_S0_SC[080] - TP6 (SIO_I2C1_SDA) - GPIO_FUNC1, // GPIO_S0_SC[081] - TP5 (SIO_I2C1_SCL) - GPIO_NC, // GPIO_S0_SC[082] - No Connect - GPIO_NC, // GPIO_S0_SC[083] - No Connect - GPIO_NC, // GPIO_S0_SC[084] - No Connect - GPIO_NC, // GPIO_S0_SC[085] - No Connect - GPIO_NC, // GPIO_S0_SC[086] - No Connect - GPIO_NC, // GPIO_S0_SC[087] - No Connect - GPIO_FUNC1, // GPIO_S0_SC[088] - LSS_I2C_SDA - GPIO_FUNC1, // GPIO_S0_SC[089] - LSS_I2C_SCL - GPIO_FUNC1, // GPIO_S0_SC[090] - EXP_I2C_SDA - GPIO_FUNC1, // GPIO_S0_SC[091] - EXP_I2C_SCL - GPIO_FUNC(1, PULL_UP, 20K), // GPIO_S0_SC[092] - TP13 - GPIO_FUNC(1, PULL_UP, 20K), // GPIO_S0_SC[093] - TP16 - GPIO_FUNC1, // GPIO_S0_SC[094] - SOC_PWM0 - GPIO_FUNC1, // GPIO_S0_SC[095] - SOC_PWM1 - GPIO_NC, // GPIO_S0_SC[096] - No Connect - GPIO_NC, // GPIO_S0_SC[097] - No Connect - GPIO_NC, // GPIO_S0_SC[098] - No Connect - GPIO_NC, // GPIO_S0_SC[099] - No Connect - GPIO_NC, // GPIO_S0_SC[100] - No Connect - GPIO_NC, // GPIO_S0_SC[101] - No Connect - GPIO_END -}; - -/* SSUS GPIOs (GPIO_S5) */ -static const struct soc_gpio_map gpssus_gpio_map[] = { - GPIO_FUNC(0, PULL_UP, 20K), // GPIO_S5[00] - SOC_GPIO_S5_0 - GPIO_FUNC(0, PULL_UP, 20K), // GPIO_S5[01] - SOC_GPIO_S5_1 - GPIO_FUNC(0, PULL_UP, 20K), // GPIO_S5[02] - SOC_GPIO_S5_2 - GPIO_FUNC6, // GPIO_S5[03] - mPCIE_WAKEB - GPIO_NC, // GPIO_S5[04] - No Connect - GPIO_INPUT, // GPIO_S5[05] - BOM_OP1 - // Memory: 0=1GB 1=2GB or 4GB - GPIO_INPUT, // GPIO_S5[06] - BOM_OP2 - GPIO_INPUT, // GPIO_S5[07] - BOM_OP3 - GPIO_OUT_HIGH_LEGACY, // GPIO_S5[08] - SOC_USB_HOST_EN0 - GPIO_OUT_HIGH_LEGACY, // GPIO_S5[09] - SOC_USB_HOST_EN1 - GPIO_OUT_HIGH_LEGACY, // GPIO_S5[10] - GPIO_S5_10_UNLOCK - GPIO_FUNC0, // GPIO_S5[11] - SUSPWRDNACK (TP14) - GPIO_FUNC0, // GPIO_S5[12] - PMC_SUSCLK0 - GPIO_FUNC1, // GPIO_S5[13] - PMC_SLP_S0IX (TP10) - GPIO_FUNC1, // GPIO_S5[14] - GPIO_S514_J20 - GPIO_FUNC0, // GPIO_S5[15] - PMC_PCIE_WAKE_R - GPIO_FUNC0, // GPIO_S5[16] - PMC_PWRBTN - GPIO_NC, // GPIO_S5[17] - No Connect - GPIO_FUNC1, // GPIO_S5[18] - LPCPD_L (TP7) - GPIO_FUNC0, // GPIO_S5[19] - SOC_USB_HOST_OC0 - GPIO_FUNC0, // GPIO_S5[20] - SOC_USB_HOST_OC1 - GPIO_FUNC0, // GPIO_S5[21] - SOC_SPI_CS1B - GPIO_INPUT_PD, // GPIO_S5[22] - NC or LED D2 - GPIO_FUNC(0, PULL_UP, 20K), // GPIO_S5[23] - XDP_H_OBSDATA_A0 - GPIO_FUNC(0, PULL_UP, 20K), // GPIO_S5[24] - XDP_H_OBSDATA_A1 - GPIO_FUNC(0, PULL_UP, 20K), // GPIO_S5[25] - XDP_H_OBSDATA_A2 - GPIO_FUNC(0, PULL_UP, 20K), // GPIO_S5[26] - XDP_H_OBSDATA_A3 - GPIO_FUNC(0, PULL_UP, 20K), // GPIO_S5[27] - EXP_GPIO1 - GPIO_FUNC(0, PULL_UP, 20K), // GPIO_S5[28] - EXP_GPIO2 - GPIO_FUNC(0, PULL_UP, 20K), // GPIO_S5[29] - EXP_GPIO3 - GPIO_FUNC(0, PULL_UP, 20K), // GPIO_S5[30] - EXP_GPIO4 - GPIO_NC, // GPIO_S5[31] - No Connect - GPIO_NC, // GPIO_S5[32] - No Connect - GPIO_NC, // GPIO_S5[33] - No Connect - GPIO_NC, // GPIO_S5[34] - No Connect - GPIO_NC, // GPIO_S5[35] - No Connect - GPIO_NC, // GPIO_S5[36] - No Connect - GPIO_NC, // GPIO_S5[37] - No Connect - GPIO_NC, // GPIO_S5[38] - No Connect - GPIO_NC, // GPIO_S5[39] - No Connect - GPIO_NC, // GPIO_S5[40] - No Connect - GPIO_NC, // GPIO_S5[41] - No Connect - GPIO_NC, // GPIO_S5[42] - No Connect - GPIO_NC, // GPIO_S5[43] - No Connect - GPIO_END -}; - -static struct soc_gpio_config gpio_config = { - .ncore = gpncore_gpio_map, - .score = gpscore_gpio_map, - .ssus = gpssus_gpio_map, - .core_dirq = NULL, - .sus_dirq = NULL, -}; - -struct soc_gpio_config *mainboard_get_gpios(void) -{ - return &gpio_config; -} diff --git a/src/mainboard/intel/minnowmax/irqroute.c b/src/mainboard/intel/minnowmax/irqroute.c deleted file mode 100644 index db8c512a43..0000000000 --- a/src/mainboard/intel/minnowmax/irqroute.c +++ /dev/null @@ -1,18 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2013 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include "irqroute.h" - -DEFINE_IRQ_ROUTES; diff --git a/src/mainboard/intel/minnowmax/irqroute.h b/src/mainboard/intel/minnowmax/irqroute.h deleted file mode 100644 index 20281b7e3f..0000000000 --- a/src/mainboard/intel/minnowmax/irqroute.h +++ /dev/null @@ -1,83 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2013 Google Inc. - * Copyright (C) 2014 Sage Electronic Engineering, LLC. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef IRQROUTE_H -#define IRQROUTE_H - -#include -#include - -/* - *IR02h GFX INT(A) - PIRQ A - *IR10h EMMC INT(ABCD) - PIRQ DEFG - *IR11h SDIO INT(A) - PIRQ B - *IR12h SD INT(A) - PIRQ C - *IR13h SATA INT(A) - PIRQ D - *IR14h XHCI INT(A) - PIRQ E - *IR15h LP Audio INT(A) - PIRQ F - *IR17h MMC INT(A) - PIRQ F - *IR18h SIO INT(ABCD) - PIRQ BADC - *IR1Ah TXE INT(A) - PIRQ F - *IR1Bh HD Audio INT(A) - PIRQ G - *IR1Ch PCIe INT(ABCD) - PIRQ EFGH - *IR1Dh EHCI INT(A) - PIRQ D - *IR1Eh SIO INT(ABCD) - PIRQ BDEF - *IR1Fh LPC INT(ABCD) - PIRQ HGBC - */ - -/* PCIe bridge routing */ -#define BRIDGE1_DEV PCIE_DEV - -/* PCI bridge IRQs need to be updated in both tables and need to match */ -#define PCIE_BRIDGE_IRQ_ROUTES \ - PCIE_BRIDGE_DEV(RP, BRIDGE1_DEV, E, F, G, H) - -/* Devices set as A, A, A, A evaluate as 0, and don't get set */ -#define PCI_DEV_PIRQ_ROUTES \ - PCI_DEV_PIRQ_ROUTE(GFX_DEV, A, A, A, B), \ - PCI_DEV_PIRQ_ROUTE(EMMC_DEV, D, E, F, G), \ - PCI_DEV_PIRQ_ROUTE(SDIO_DEV, B, A, A, A), \ - PCI_DEV_PIRQ_ROUTE(SD_DEV, C, A, A, A), \ - PCI_DEV_PIRQ_ROUTE(SATA_DEV, D, A, A, A), \ - PCI_DEV_PIRQ_ROUTE(XHCI_DEV, E, A, A, A), \ - PCI_DEV_PIRQ_ROUTE(LPE_DEV, F, A, A, A), \ - PCI_DEV_PIRQ_ROUTE(MMC45_DEV, F, A, A, A), \ - PCI_DEV_PIRQ_ROUTE(SIO1_DEV, B, A, D, C), \ - PCI_DEV_PIRQ_ROUTE(TXE_DEV, F, A, A, A), \ - PCI_DEV_PIRQ_ROUTE(HDA_DEV, G, A, A, A), \ - PCI_DEV_PIRQ_ROUTE(BRIDGE1_DEV, E, F, G, H), \ - PCI_DEV_PIRQ_ROUTE(EHCI_DEV, D, A, A, A), \ - PCI_DEV_PIRQ_ROUTE(SIO2_DEV, B, D, E, F), \ - PCI_DEV_PIRQ_ROUTE(PCU_DEV, H, G, B, C) - -/* - * Route each PIRQ[A-H] to a PIC IRQ[0-15] - * Reserved: 0, 1, 2, 8, 13 - * PS2 keyboard: 12 - * ACPI/SCI: 9 - * Floppy: 6 - */ -#define PIRQ_PIC_ROUTES \ - PIRQ_PIC(A, 3), \ - PIRQ_PIC(B, 5), \ - PIRQ_PIC(C, 7), \ - PIRQ_PIC(D, 10), \ - PIRQ_PIC(E, 11), \ - PIRQ_PIC(F, 12), \ - PIRQ_PIC(G, 14), \ - PIRQ_PIC(H, 15) - -#endif /* IRQROUTE_H */ diff --git a/src/mainboard/intel/minnowmax/mainboard.c b/src/mainboard/intel/minnowmax/mainboard.c deleted file mode 100644 index 0fe1259420..0000000000 --- a/src/mainboard/intel/minnowmax/mainboard.c +++ /dev/null @@ -1,41 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007-2009 coresystems GmbH - * Copyright (C) 2011 The ChromiumOS Authors. All rights reserved. - * Copyright (C) 2014 Sage Electronic Engineering, LLC - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include - -/* - * mainboard_enable is executed as first thing after enumerate_buses(). - * This is the earliest point to add customization. - */ -static void mainboard_enable(struct device *dev) -{ -} - -/* - * mainboard_final is executed as one of the last items before loading the - * payload. - * - * This is the latest point to add customization. - */ -static void mainboard_final(void *chip_info) -{ -} - -struct chip_operations mainboard_ops = { - .enable_dev = mainboard_enable, - .final = mainboard_final, -}; diff --git a/src/mainboard/intel/minnowmax/romstage.c b/src/mainboard/intel/minnowmax/romstage.c deleted file mode 100644 index 38b7e0d6ff..0000000000 --- a/src/mainboard/intel/minnowmax/romstage.c +++ /dev/null @@ -1,140 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2013 Google Inc. - * Copyright (C) 2013 Sage Electronic Engineering, LLC. - * Copyright (C) 2014 Intel Corporation - * Copyright (C) 2018 CMR Surgical Limited - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include -#include -#include -#include -#include - -/** - * /brief mainboard call for setup that needs to be done before fsp init - * - */ -void early_mainboard_romstage_entry(void) -{ - -} - -/** - * Get function disables - most of these will be done automatically - * @param fd_mask - * @param fd2_mask - */ -void get_func_disables(uint32_t *fd_mask, uint32_t *fd2_mask) -{ - -} - -/** - * /brief mainboard call for setup that needs to be done after fsp init - * - */ -void late_mainboard_romstage_entry(void) -{ - -} - -/* Set up the default soldered down memory config for 1GB */ -static const MEMORY_DOWN_DATA minnowmax_memory_config[] = { - /* 1066 */ - { - .EnableMemoryDown = 1, - .DRAMSpeed = 1, /* DRAM Speed: 0=800, 1=1066, 2=1333, 3=1600*/ - .DRAMType = 1, /* DRAM Type: 0=DDR3, 1=DDR3L, 2=DDR3U, 4=LPDDR2, 5=LPDDR3, 6=DDR4*/ - .DIMM0Enable = 1, /* DIMM 0 Enable */ - .DIMM1Enable = 0, /* DIMM 1 Enable */ - .DIMMDWidth = 1, /* DRAM device data width: 0=x8, 1=x16, 2=x32*/ - .DIMMDensity = 1, /* DRAM device data density: 0=1Gb, 1=2Gb, 2=4Gb, 3=8Gb */ - .DIMMBusWidth = 3, /* DIMM Bus Width: 0=8bit, 1=16bit, 2=32bit, 3=64bit */ - .DIMMSides = 0, /* Ranks Per DIMM: 0=1rank, 1=2rank */ - .DIMMtCL = 11, /* tCL */ - .DIMMtRPtRCD = 11, /* tRP and tRCD in DRAM clk - 5:12.5ns, 6:15ns, etc. */ - .DIMMtWR = 12, /* tWR in DRAM clk */ - .DIMMtWTR = 6, /* tWTR in DRAM clk */ - .DIMMtRRD = 6, /* tRRD in DRAM clk */ - .DIMMtRTP = 6, /* tRTP in DRAM clk */ - .DIMMtFAW = 20, /* tFAW in DRAM clk */ - }, - /* 1333 */ - { - .EnableMemoryDown = 1, - .DRAMSpeed = 2, /* DRAM Speed: 0=800, 1=1066, 2=1333, 3=1600*/ - .DRAMType = 1, /* DRAM Type: 0=DDR3, 1=DDR3L, 2=DDR3U, 4=LPDDR2, 5=LPDDR3, 6=DDR4*/ - .DIMM0Enable = 1, /* DIMM 0 Enable */ - .DIMM1Enable = 0, /* DIMM 1 Enable */ - .DIMMDWidth = 1, /* DRAM device data width: 0=x8, 1=x16, 2=x32*/ - .DIMMDensity = 1, /* DRAM device data density: 0=1Gb, 1=2Gb, 2=4Gb, 3=8Gb */ - .DIMMBusWidth = 3, /* DIMM Bus Width: 0=8bit, 1=16bit, 2=32bit, 3=64bit */ - .DIMMSides = 0, /* Ranks Per DIMM: 0=1rank, 1=2rank */ - .DIMMtCL = 9, /* tCL */ - .DIMMtRPtRCD = 9, /* tRP and tRCD in DRAM clk - 5:12.5ns, 6:15ns, etc. */ - .DIMMtWR = 10, /* tWR in DRAM clk */ - .DIMMtWTR = 5, /* tWTR in DRAM clk */ - .DIMMtRRD = 4, /* tRRD in DRAM clk */ - .DIMMtRTP = 5, /* tRTP in DRAM clk */ - .DIMMtFAW = 30, /* tFAW in DRAM clk */ - } -}; - -void romstage_fsp_rt_buffer_callback(FSP_INIT_RT_BUFFER *FspRtBuffer) -{ - UPD_DATA_REGION *UpdData = FspRtBuffer->Common.UpdDataRgnPtr; - u8 use_xhci = UpdData->PcdEnableXhci; - u8 gpio5 = 0; - int is_1333_sku; - - /* - * The E3827 and E3845 SKUs are fused at 1333MHz DDR3 speeds. There's - * no good way of knowing the SKU'ing so frequency is used as a proxy. - * The E3805, E3815, E3825, and E3826 are all <= 1460MHz while the - * E3827 and E3845 are 1750MHz and 1910MHz, respectively. - */ - is_1333_sku = !!(tsc_freq_mhz() >= 1700); - - printk(BIOS_INFO, "Using %d MHz DDR3 settings.\n", - is_1333_sku ? 1333 : 1066); - - /* Set up soldered down memory parameters for 1GB */ - UpdData->PcdMemoryParameters = minnowmax_memory_config[is_1333_sku]; - - /* - * Minnow Max Board - * Read SSUS gpio 5 to determine memory type - * 0 : 1GB SKU uses 2Gb density memory - * 1 : 2GB SKU uses 4Gb density memory - * - * devicetree.cb assumes 1GB SKU board - */ - configure_ssus_gpio(5, PAD_FUNC0 | PAD_PULL_DISABLE, PAD_VAL_INPUT); - gpio5 = read_ssus_gpio(5); - if (gpio5) - UpdData->PcdMemoryParameters.DIMMDensity - += (DIMM_DENSITY_4G_BIT - DIMM_DENSITY_2G_BIT); - printk(BIOS_NOTICE, "%s GB Minnowboard Max detected.\n", - gpio5 ? "2 / 4" : "1"); - /* Update XHCI UPD value if required */ - get_option(&use_xhci, "use_xhci_over_ehci"); - if ((use_xhci < 2) && (use_xhci != UpdData->PcdEnableXhci)) { - UpdData->PcdEnableXhci = use_xhci; - printk(FSP_INFO_LEVEL, "Xhci updated from CMOS:\t\t\t%s\n", - UpdData->PcdEnableXhci?"Enabled":"Disabled"); - } -} diff --git a/src/mainboard/opencellular/rotundu/Kconfig b/src/mainboard/opencellular/rotundu/Kconfig deleted file mode 100644 index ddacbe747c..0000000000 --- a/src/mainboard/opencellular/rotundu/Kconfig +++ /dev/null @@ -1,106 +0,0 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2013-2014 Sage Electronic Engineering, LLC. -## Copyright (C) 2014 Intel Corporation -## Copyright (C) 2017-present Facebook, Inc. -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; version 2 of the License. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## - -config BOARD_OPENCELLULAR_BASEBOARD_ROTUNDU - def_bool n - select SOC_INTEL_FSP_BAYTRAIL - select BOARD_ROMSIZE_KB_8192 - select HAVE_ACPI_TABLES - select HAVE_OPTION_TABLE - select ENABLE_BUILTIN_COM1 - select ENABLE_FSP_FAST_BOOT - select USE_BLOBS - select HAVE_FSP_BIN if FSP_PACKAGE_DEFAULT - select MAINBOARD_HAS_LPC_TPM - select MAINBOARD_HAS_TPM1 - -if BOARD_OPENCELLULAR_BASEBOARD_ROTUNDU - -config VBOOT - select MRC_CACHE_FMAP - select VBOOT_VBNV_CMOS - select VBOOT_NO_BOARD_SUPPORT - select GBB_FLAG_DISABLE_LID_SHUTDOWN - select GBB_FLAG_DISABLE_PD_SOFTWARE_SYNC - select GBB_FLAG_DISABLE_EC_SOFTWARE_SYNC - select GBB_FLAG_DISABLE_FWMP - -config GBB_HWID - string - depends on VBOOT - default "ROTUNDU" if BOARD_OPENCELLULAR_ROTUNDU - default "SUPABRCKV1" if BOARD_OPENCELLULAR_SUPABRCKV1 - -config VARIANT_DIR - string - default "rotundu" if BOARD_OPENCELLULAR_ROTUNDU - default "supabrckv1" if BOARD_OPENCELLULAR_SUPABRCKV1 - -config MAINBOARD_PART_NUMBER - string - default "Rotundu" if BOARD_OPENCELLULAR_ROTUNDU - default "Supabrck v1" if BOARD_OPENCELLULAR_SUPABRCKV1 - -config DEVICETREE - string - default "variants/$(CONFIG_VARIANT_DIR)/devicetree.cb" - -config MAINBOARD_DIR - string - default "opencellular/rotundu" - -config MAINBOARD_VENDOR - string - default "OpenCellular" - -config MAX_CPUS - int - default 16 - -config FSP_LOC - hex - default 0xfffb0000 - -config FMDFILE - string - depends on VBOOT - default "src/mainboard/$(CONFIG_MAINBOARD_DIR)/vboot-8M.fmd" if BOARD_ROMSIZE_KB_8192 - default "src/mainboard/$(CONFIG_MAINBOARD_DIR)/vboot-16M.fmd" if BOARD_ROMSIZE_KB_16384 - -config CBFS_SIZE - hex - default 0x00140000 if BOARD_ROMSIZE_KB_8192 - default 0x003effc0 if BOARD_ROMSIZE_KB_16384 - -config VIRTUAL_ROM_SIZE - hex - depends on ENABLE_FSP_FAST_BOOT - default 0x800000 - -config FSP_PACKAGE_DEFAULT - bool "Configure defaults for the Intel FSP package" - default n - -config VGA_BIOS - bool - default y if FSP_PACKAGE_DEFAULT - -config VGA_BIOS_ID - string - default "8086,0f31" - -endif # BOARD_OPENCELLULAR_ROTUNDU diff --git a/src/mainboard/opencellular/rotundu/Kconfig.name b/src/mainboard/opencellular/rotundu/Kconfig.name deleted file mode 100644 index 1346b94b04..0000000000 --- a/src/mainboard/opencellular/rotundu/Kconfig.name +++ /dev/null @@ -1,7 +0,0 @@ -config BOARD_OPENCELLULAR_ROTUNDU - bool "OpenCellular Rotundu (GBCv1)" - select BOARD_OPENCELLULAR_BASEBOARD_ROTUNDU - -config BOARD_OPENCELLULAR_SUPABRCKV1 - bool "OpenCellular Supabrck V1 (BRCK)" - select BOARD_OPENCELLULAR_BASEBOARD_ROTUNDU diff --git a/src/mainboard/opencellular/rotundu/Makefile.inc b/src/mainboard/opencellular/rotundu/Makefile.inc deleted file mode 100644 index 2aee2286f5..0000000000 --- a/src/mainboard/opencellular/rotundu/Makefile.inc +++ /dev/null @@ -1,19 +0,0 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2013 Google Inc. -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; version 2 of the License. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## - -ramstage-y += variants/$(VARIANT_DIR)/gpio.c -ramstage-y += irqroute.c - -subdirs-y += variants/$(VARIANT_DIR) diff --git a/src/mainboard/opencellular/rotundu/acpi/ec.asl b/src/mainboard/opencellular/rotundu/acpi/ec.asl deleted file mode 100644 index e69de29bb2..0000000000 diff --git a/src/mainboard/opencellular/rotundu/acpi/mainboard.asl b/src/mainboard/opencellular/rotundu/acpi/mainboard.asl deleted file mode 100644 index b032ee189d..0000000000 --- a/src/mainboard/opencellular/rotundu/acpi/mainboard.asl +++ /dev/null @@ -1,20 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 Google Inc. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -Device (PWRB) -{ - Name(_HID, EisaId("PNP0C0C")) -} diff --git a/src/mainboard/opencellular/rotundu/acpi/superio.asl b/src/mainboard/opencellular/rotundu/acpi/superio.asl deleted file mode 100644 index e69de29bb2..0000000000 diff --git a/src/mainboard/opencellular/rotundu/acpi_tables.c b/src/mainboard/opencellular/rotundu/acpi_tables.c deleted file mode 100644 index 7f6abd9685..0000000000 --- a/src/mainboard/opencellular/rotundu/acpi_tables.c +++ /dev/null @@ -1,56 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2012 Google Inc. - * Copyright (C) 2013-2014 Sage Electronic Engineering, LLC. - * Copyright (C) 2017-present Facebook, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include -#include -#include -#include - -void acpi_create_gnvs(global_nvs_t *gnvs) -{ - acpi_init_gnvs(gnvs); - - /* Enable USB ports in S3 */ - gnvs->s3u0 = 1; - gnvs->s3u1 = 1; - - /* Disable USB ports in S5 */ - gnvs->s5u0 = 0; - gnvs->s5u1 = 0; - - /* TPM Present */ - gnvs->tpmp = 1; - - /* Enable DPTF */ - gnvs->dpte = 0; -} - -unsigned long acpi_fill_madt(unsigned long current) -{ - /* Local APICs */ - current = acpi_create_madt_lapics(current); - - /* IOAPIC */ - current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, - 2, IO_APIC_ADDR, 0); - - current = acpi_madt_irq_overrides(current); - - return current; -} diff --git a/src/mainboard/opencellular/rotundu/board_info.txt b/src/mainboard/opencellular/rotundu/board_info.txt deleted file mode 100644 index 115b8be273..0000000000 --- a/src/mainboard/opencellular/rotundu/board_info.txt +++ /dev/null @@ -1,4 +0,0 @@ -Board name: Rotundu -Category: sbc -ROM protocol: SPI -ROM socketed: n diff --git a/src/mainboard/opencellular/rotundu/chromeos.fmd b/src/mainboard/opencellular/rotundu/chromeos.fmd deleted file mode 100644 index 7be08dc27b..0000000000 --- a/src/mainboard/opencellular/rotundu/chromeos.fmd +++ /dev/null @@ -1,37 +0,0 @@ -FLASH@0xff800000 0x800000 { - SI_ALL@0x0 0x300000 { - SI_DESC@0x0 0x1000 - SI_ME@0x1000 0x2ff000 - } - SI_BIOS@0x300000 0x500000 { - RW_SECTION_A@0x0 0xf0000 { - VBLOCK_A@0x0 0x10000 - FW_MAIN_A(CBFS)@0x10000 0xc0000 - RW_FWID_A@0xeffc0 0x40 - } - RW_SECTION_B@0xf0000 0xf0000 { - VBLOCK_B@0x0 0x10000 - FW_MAIN_B(CBFS)@0x10000 0xc0000 - RW_FWID_B@0xeffc0 0x40 - } - RW_MRC_CACHE@0x1e0000 0x10000 - RW_ELOG(PRESERVE)@0x1f0000 0x4000 - RW_SHARED@0x1f4000 0x4000 { - SHARED_DATA@0x0 0x2000 - VBLOCK_DEV@0x2000 0x2000 - } - RW_VPD(PRESERVE)@0x1f8000 0x2000 - RW_UNUSED@0x1fa000 0x106000 - WP_RO@0x300000 0x200000 { - RO_VPD(PRESERVE)@0x0 0x4000 - RO_UNUSED@0x4000 0xc000 - RO_SECTION@0x10000 0x1f0000 { - FMAP@0x0 0x800 - RO_FRID@0x800 0x40 - RO_FRID_PAD@0x840 0x7c0 - GBB@0x1000 0xef000 - COREBOOT(CBFS)@0xf0000 0x100000 - } - } - } -} diff --git a/src/mainboard/opencellular/rotundu/cmos.default b/src/mainboard/opencellular/rotundu/cmos.default deleted file mode 100644 index 6c96947e2a..0000000000 --- a/src/mainboard/opencellular/rotundu/cmos.default +++ /dev/null @@ -1 +0,0 @@ -debug_level=Error diff --git a/src/mainboard/opencellular/rotundu/cmos.layout b/src/mainboard/opencellular/rotundu/cmos.layout deleted file mode 100644 index 9ef1102c17..0000000000 --- a/src/mainboard/opencellular/rotundu/cmos.layout +++ /dev/null @@ -1,97 +0,0 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2007-2008 coresystems GmbH -## Copyright (C) 2017-present Facebook, Inc. -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; version 2 of the License. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## - -# ----------------------------------------------------------------- -entries - -# ----------------------------------------------------------------- -# Status Register A -# ----------------------------------------------------------------- -# Status Register B -# ----------------------------------------------------------------- -# Status Register C -#96 4 r 0 status_c_rsvd -#100 1 r 0 uf_flag -#101 1 r 0 af_flag -#102 1 r 0 pf_flag -#103 1 r 0 irqf_flag -# ----------------------------------------------------------------- -# Status Register D -#104 7 r 0 status_d_rsvd -#111 1 r 0 valid_cmos_ram -# ----------------------------------------------------------------- -# Diagnostic Status Register -#112 8 r 0 diag_rsvd1 - -# ----------------------------------------------------------------- -0 120 r 0 reserved_memory -#120 264 r 0 unused - -# ----------------------------------------------------------------- -# RTC_BOOT_BYTE (coreboot hardcoded) -384 1 e 4 boot_option -#390 2 r 0 unused? - -# ----------------------------------------------------------------- -# coreboot config options: console -395 4 e 6 debug_level -#399 1 r 0 unused - -# coreboot config options: cpu -#401 7 r 0 unused - -# coreboot config options: southbridge -408 1 e 1 nmi -411 2 e 8 use_xhci_over_ehci -#413 3 r 0 unused - -# MRC Scrambler Seed values -928 32 r 0 mrc_scrambler_seed_s3 - -# coreboot config options: check sums -984 16 h 0 check_sum -#1000 24 r 0 amd_reserved - -# ----------------------------------------------------------------- - -enumerations - -#ID value text -1 0 Disable -1 1 Enable -2 0 Enable -2 1 Disable -4 0 Fallback -4 1 Normal -6 1 Emergency -6 2 Alert -6 3 Critical -6 4 Error -6 5 Warning -6 6 Notice -6 7 Info -6 8 Debug -6 9 Spew -7 0 Disable -7 1 Enable -7 2 Keep -8 0 EHCI -8 1 XHCI -8 2 Default -# ----------------------------------------------------------------- -checksums - -checksum 392 415 984 diff --git a/src/mainboard/opencellular/rotundu/dsdt.asl b/src/mainboard/opencellular/rotundu/dsdt.asl deleted file mode 100644 index bea6af7973..0000000000 --- a/src/mainboard/opencellular/rotundu/dsdt.asl +++ /dev/null @@ -1,54 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007-2009 coresystems GmbH - * Copyright (C) 2011 Google Inc. - * Copyright (C) 2014 Sage Electronic Engineering, LLC. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#define INCLUDE_LPE 1 -#define INCLUDE_SCC 1 -#define INCLUDE_EHCI 1 -#define INCLUDE_XHCI 1 -#define INCLUDE_LPSS 1 - - -#include -DefinitionBlock( - "dsdt.aml", - "DSDT", - 0x02, // DSDT revision: ACPI v2.0 and up - OEM_ID, - ACPI_TABLE_CREATOR, - 0x20110725 // OEM revision -) -{ - // Some generic macros - #include - - // global NVS and variables - #include - - #include - - Scope (\_SB) { - Device (PCI0) - { - #include - } - } - - /* Chipset specific sleep states */ - #include - - #include "acpi/mainboard.asl" -} diff --git a/src/mainboard/opencellular/rotundu/fadt.c b/src/mainboard/opencellular/rotundu/fadt.c deleted file mode 100644 index 4194bfc324..0000000000 --- a/src/mainboard/opencellular/rotundu/fadt.c +++ /dev/null @@ -1,29 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007-2009 coresystems GmbH - * Copyright (C) 2013-2014 Sage Electronic Engineering, LLC. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include - -void acpi_create_fadt(acpi_fadt_t *fadt, acpi_facs_t *facs, void *dsdt) -{ - acpi_header_t *header = &(fadt->header); - - acpi_fill_in_fadt(fadt, facs, dsdt); - - /* Platform specific customizations go here */ - - header->checksum = acpi_checksum((void *) fadt, sizeof(acpi_fadt_t)); -} diff --git a/src/mainboard/opencellular/rotundu/irqroute.c b/src/mainboard/opencellular/rotundu/irqroute.c deleted file mode 100644 index db8c512a43..0000000000 --- a/src/mainboard/opencellular/rotundu/irqroute.c +++ /dev/null @@ -1,18 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2013 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include "irqroute.h" - -DEFINE_IRQ_ROUTES; diff --git a/src/mainboard/opencellular/rotundu/irqroute.h b/src/mainboard/opencellular/rotundu/irqroute.h deleted file mode 100644 index 9feaa0ed9e..0000000000 --- a/src/mainboard/opencellular/rotundu/irqroute.h +++ /dev/null @@ -1,84 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2013 Google Inc. - * Copyright (C) 2014 Sage Electronic Engineering, LLC. - * Copyright (C) 2017-present Facebook, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef IRQROUTE_H -#define IRQROUTE_H - -#include -#include - -/* - *IR02h GFX INT(A) - PIRQ A - *IR10h EMMC INT(ABCD) - PIRQ DEFG - *IR11h SDIO INT(A) - PIRQ B - *IR12h SD INT(A) - PIRQ C - *IR13h SATA INT(A) - PIRQ D - *IR14h XHCI INT(A) - PIRQ E - *IR15h LP Audio INT(A) - PIRQ F - *IR17h MMC INT(A) - PIRQ F - *IR18h SIO INT(ABCD) - PIRQ BADC - *IR1Ah TXE INT(A) - PIRQ F - *IR1Bh HD Audio INT(A) - PIRQ G - *IR1Ch PCIe INT(ABCD) - PIRQ EFGH - *IR1Dh EHCI INT(A) - PIRQ D - *IR1Eh SIO INT(ABCD) - PIRQ BDEF - *IR1Fh LPC INT(ABCD) - PIRQ HGBC - */ - -/* PCIe bridge routing */ -#define BRIDGE1_DEV PCIE_DEV - -/* PCI bridge IRQs need to be updated in both tables and need to match */ -#define PCIE_BRIDGE_IRQ_ROUTES \ - PCIE_BRIDGE_DEV(RP, BRIDGE1_DEV, E, F, G, H) - -/* Devices set as A, A, A, A evaluate as 0, and don't get set */ -#define PCI_DEV_PIRQ_ROUTES \ - PCI_DEV_PIRQ_ROUTE(GFX_DEV, A, A, A, B), \ - PCI_DEV_PIRQ_ROUTE(EMMC_DEV, D, E, F, G), \ - PCI_DEV_PIRQ_ROUTE(SDIO_DEV, B, A, A, A), \ - PCI_DEV_PIRQ_ROUTE(SD_DEV, C, A, A, A), \ - PCI_DEV_PIRQ_ROUTE(SATA_DEV, D, A, A, A), \ - PCI_DEV_PIRQ_ROUTE(XHCI_DEV, E, A, A, A), \ - PCI_DEV_PIRQ_ROUTE(LPE_DEV, F, A, A, A), \ - PCI_DEV_PIRQ_ROUTE(MMC45_DEV, F, A, A, A), \ - PCI_DEV_PIRQ_ROUTE(SIO1_DEV, B, A, D, C), \ - PCI_DEV_PIRQ_ROUTE(TXE_DEV, F, A, A, A), \ - PCI_DEV_PIRQ_ROUTE(HDA_DEV, G, A, A, A), \ - PCI_DEV_PIRQ_ROUTE(BRIDGE1_DEV, E, F, G, H), \ - PCI_DEV_PIRQ_ROUTE(EHCI_DEV, D, A, A, A), \ - PCI_DEV_PIRQ_ROUTE(SIO2_DEV, B, D, E, F), \ - PCI_DEV_PIRQ_ROUTE(PCU_DEV, H, G, B, C) - -/* - * Route each PIRQ[A-H] to a PIC IRQ[0-15] - * Reserved: 0, 1, 2, 8, 13 - * PS2 keyboard: 12 - * ACPI/SCI: 9 - * Floppy: 6 - */ -#define PIRQ_PIC_ROUTES \ - PIRQ_PIC(A, 4), \ - PIRQ_PIC(B, 5), \ - PIRQ_PIC(C, 7), \ - PIRQ_PIC(D, 10), \ - PIRQ_PIC(E, 11), \ - PIRQ_PIC(F, 12), \ - PIRQ_PIC(G, 14), \ - PIRQ_PIC(H, 15) - -#endif /* IRQROUTE_H */ diff --git a/src/mainboard/opencellular/rotundu/mainboard.c b/src/mainboard/opencellular/rotundu/mainboard.c deleted file mode 100644 index 53c98002e9..0000000000 --- a/src/mainboard/opencellular/rotundu/mainboard.c +++ /dev/null @@ -1,42 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007-2009 coresystems GmbH - * Copyright (C) 2011 The ChromiumOS Authors. All rights reserved. - * Copyright (C) 2014 Sage Electronic Engineering, LLC - * Copyright (C) 2017-present Facebook, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include - -/* - * mainboard_enable is executed as first thing after enumerate_buses(). - * This is the earliest point to add customization. - */ -static void mainboard_enable(struct device *dev) -{ -} - -/* - * mainboard_final is executed as one of the last items before loading the - * payload. - * - * This is the latest point to add customization. - */ -static void mainboard_final(void *chip_info) -{ -} - -struct chip_operations mainboard_ops = { - .enable_dev = mainboard_enable, - .final = mainboard_final, -}; diff --git a/src/mainboard/opencellular/rotundu/romstage.c b/src/mainboard/opencellular/rotundu/romstage.c deleted file mode 100644 index b5c3bc8fc3..0000000000 --- a/src/mainboard/opencellular/rotundu/romstage.c +++ /dev/null @@ -1,56 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2013 Google Inc. - * Copyright (C) 2013 Sage Electronic Engineering, LLC. - * Copyright (C) 2014 Intel Corporation - * Copyright (C) 2017-present Facebook, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include -#include -#include - -/** - * /brief mainboard call for setup that needs to be done before fsp init - * - */ -void early_mainboard_romstage_entry(void) -{ - -} - -/** - * Get function disables - most of these will be done automatically - * @param fd_mask - * @param fd2_mask - */ -void get_func_disables(uint32_t *fd_mask, uint32_t *fd2_mask) -{ - -} - -/** - * /brief mainboard call for setup that needs to be done after fsp init - * - */ -void late_mainboard_romstage_entry(void) -{ - -} - -void romstage_fsp_rt_buffer_callback(FSP_INIT_RT_BUFFER *FspRtBuffer) -{ - printk(BIOS_NOTICE, "This is the OpenCellular Rotundu GBC board.\n"); -} diff --git a/src/mainboard/opencellular/rotundu/variants/rotundu/devicetree.cb b/src/mainboard/opencellular/rotundu/variants/rotundu/devicetree.cb deleted file mode 100644 index 7eeac7ad84..0000000000 --- a/src/mainboard/opencellular/rotundu/variants/rotundu/devicetree.cb +++ /dev/null @@ -1,85 +0,0 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2013-2014 Sage Electronic Engineering, LLC. -## Copyright (C) 2014 Intel Corporation -## Copyright (C) 2017-present Facebook, Inc. -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; version 2 of the License. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## - -chip soc/intel/fsp_baytrail - - #### ACPI Register Settings #### - register "fadt_pm_profile" = "PM_UNSPECIFIED" - register "fadt_boot_arch" = "ACPI_FADT_LEGACY_FREE" - - #### FSP register settings #### - register "PcdSataMode" = "SATA_MODE_AHCI" - register "PcdMrcInitSPDAddr1" = "0xa0" - register "PcdMrcInitSPDAddr2" = "0xa2" - register "PcdMrcInitMmioSize" = "MMIO_SIZE_DEFAULT" - register "PcdeMMCBootMode" = "EMMC_DISABLED" - register "PcdIgdDvmt50PreAlloc" = "IGD_MEMSIZE_DEFAULT" - register "PcdApertureSize" = "APERTURE_SIZE_DEFAULT" - register "PcdGttSize" = "GTT_SIZE_DEFAULT" - register "PcdLpssSioEnablePciMode" = "LPSS_PCI_MODE_DEFAULT" - register "AzaliaAutoEnable" = "AZALIA_FOLLOWS_DEVICETREE" - register "LpeAcpiModeEnable" = "LPE_ACPI_MODE_DISABLED" - register "EnableMemoryDown" = "MEMORY_DOWN_DISABLE" - register "DIMM0Enable" = "DIMM0_ENABLE" - register "DIMM1Enable" = "DIMM1_DISABLE" - - device cpu_cluster 0 on - device lapic 0 on end - end - - device domain 0 on - device pci 00.0 on end # 8086 0F00 - SoC router - device pci 02.0 on end # 8086 0F31 - GFX - device pci 03.0 off end # 8086 0F38 - MIPI - camera interface - - device pci 10.0 off end # 8086 0F14 - EMMC 4.1 Port (MMC1 pins) - (DO NOT USE) - Only 1 EMMC port at a time - device pci 11.0 off end # 8086 0F15 - SDIO Port (SD2 pins) - device pci 12.0 off end # 8086 0F16 - SD Port (SD3 pins) - device pci 13.0 on end # 8086 0F23 - SATA AHCI (0F20, 0F21, 0F22, 0F23) - device pci 14.0 on end # 8086 0F35 - USB XHCI - Only 1 USB controller at a time - device pci 15.0 off end # 8086 0F28 - LP Engine Audio - device pci 16.0 off end # 8086 0F37 - OTG controller - device pci 17.0 off end # 8086 0F50 - EMMC 4.5 Port (MMC1 pins) - Only 1 EMMC port at a time - device pci 18.0 on end # 8086 0F40 - SIO - DMA - device pci 18.1 on end # 8086 0F41 - I2C Port 1 - device pci 18.2 off end # 8086 0F42 - I2C Port 2 - device pci 18.3 on end # 8086 0F43 - I2C Port 3 - device pci 18.4 off end # 8086 0F44 - I2C Port 4 - device pci 18.5 off end # 8086 0F45 - I2C Port 5 - device pci 18.6 off end # 8086 0F46 - I2C Port 6 - device pci 18.7 off end # 8086 0F47 - I2C Port 7 - device pci 1a.0 on end # 8086 0F18 - Trusted Execution Engine - device pci 1b.0 off end # 8086 0F04 - HD Audio - device pci 1c.0 on end # 8086 0F48 - PCIe Root Port 1 (RADIO CARD) - device pci 1c.1 on end # 8086 0F4A - PCIe Root Port 2 (GBE PHY 1) - device pci 1c.2 on end # 8086 0F4C - PCIe Root Port 3 (GBE PHY 2) - device pci 1c.3 off end # 8086 0F4E - PCIe Root Port 4 (NC) - device pci 1d.0 off end # 8086 0F34 - USB EHCI - Only 1 USB controller at a time - device pci 1e.0 on end # 8086 0F06 - SIO - DMA - device pci 1e.1 off end # 8086 0F08 - PWM 1 - device pci 1e.2 off end # 8086 0F09 - PWM 2 - device pci 1e.3 on end # 8086 0F0A - HSUART 1 - device pci 1e.4 off end # 8086 0F0C - HSUART 2 - device pci 1e.5 off end # 8086 0F0E - SPI - device pci 1f.0 on - chip drivers/pc80/tpm - device pnp 0c31.0 on end - end - end # 8086 0F1C - LPC bridge - device pci 1f.3 on end # 8086 0F12 - SMBus 0 - end -end diff --git a/src/mainboard/opencellular/rotundu/variants/rotundu/gpio.c b/src/mainboard/opencellular/rotundu/variants/rotundu/gpio.c deleted file mode 100644 index 78d1ad6ae2..0000000000 --- a/src/mainboard/opencellular/rotundu/variants/rotundu/gpio.c +++ /dev/null @@ -1,362 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2013 Google Inc. - * Copyright (C) 2014 Sage Electronic Engineering, LLC. - * Copyright (C) 2017-present Facebook, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include "../../irqroute.h" - -/* NCORE GPIOs */ -static const struct soc_gpio_map gpncore_gpio_map[] = { - - GPIO_FUNC2, /* GPIO 0 */ - GPIO_FUNC2, /* GPIO 1 */ - GPIO_FUNC2, /* GPIO 2 */ - GPIO_FUNC2, /* GPIO 3 */ - GPIO_FUNC2, /* GPIO 4 */ - GPIO_FUNC2, /* GPIO 5 */ - GPIO_FUNC2, /* GPIO 6 */ - GPIO_FUNC2, /* GPIO 7 */ - GPIO_FUNC2, /* GPIO 8 */ - GPIO_FUNC2, /* GPIO 9 */ - GPIO_FUNC2, /* GPIO 10 */ - GPIO_FUNC2, /* GPIO 11 */ - GPIO_FUNC2, /* GPIO 12 */ - GPIO_FUNC2, /* GPIO 13 */ - GPIO_FUNC2, /* GPIO 14 */ - GPIO_FUNC2, /* GPIO 15 */ - GPIO_FUNC2, /* GPIO 16 */ - GPIO_FUNC2, /* GPIO 17 */ - GPIO_FUNC2, /* GPIO 18 */ - GPIO_FUNC2, /* GPIO 19 */ - GPIO_FUNC2, /* GPIO 20 */ - GPIO_FUNC2, /* GPIO 21 */ - GPIO_FUNC2, /* GPIO 22 */ - GPIO_FUNC2, /* GPIO 23 */ - GPIO_FUNC2, /* GPIO 24 */ - GPIO_FUNC2, /* GPIO 25 */ - GPIO_FUNC2, /* GPIO 26 */ - GPIO_END}; - -/* SCORE GPIOs (GPIO_S0_SC_XX) */ -static const struct soc_gpio_map gpscore_gpio_map[] = { - GPIO_NC, - /* GPIO_S0_SC[000] SATA_GP[0] */ - GPIO_NC, - /* GPIO_S0_SC[001] SATA_GP[1] SATA_DEVSLP[0]*/ - GPIO_FUNC1, - /* GPIO_S0_SC[002] SATA_LED# */ - GPIO_FUNC1, - /* GPIO_S0_SC[003] PCIE_CLKREQ[0]# */ - GPIO_FUNC1, - /* GPIO_S0_SC[004] PCIE_CLKREQ[1]# */ - GPIO_FUNC1, - /* GPIO_S0_SC[005] PCIE_CLKREQ[2]# */ - GPIO_FUNC1, - /* GPIO_S0_SC[006] PCIE_CLKREQ[3]# */ - GPIO_FUNC2, - /* GPIO_S0_SC[007] RESERVED SD3_WP */ - GPIO_NC, - /* GPIO_S0_SC[008] I2S0_CLK HDA_RST#*/ - GPIO_NC, - /* GPIO_S0_SC[009] I2S0_FRM HDA_SYNC*/ - GPIO_NC, - /* GPIO_S0_SC[010] I2S0_DATAOUT HDA_CLK */ - GPIO_NC, - /* GPIO_S0_SC[011] I2S0_DATAIN HDA_SDO */ - GPIO_NC, - /* GPIO_S0_SC[012] I2S1_CLK HDA_SDI[0]*/ - GPIO_NC, - /* GPIO_S0_SC[013] I2S1_FRM HDA_SDI[1]*/ - GPIO_NC, - /* GPIO_S0_SC[014] I2S1_DATAOUT RESERVED*/ - GPIO_DEFAULT, - /* GPIO_S0_SC[015] I2S1_DATAIN RESERVED*/ - GPIO_NC, - /* GPIO_S0_SC[016] MMC1_CLK MMC1_45_CLK */ - GPIO_NC, - /* GPIO_S0_SC[017] MMC1_D[0] MMC1_45_D[0] */ - GPIO_NC, - /* GPIO_S0_SC[018] MMC1_D[1] MMC1_45_D[1] */ - GPIO_NC, - /* GPIO_S0_SC[019] MMC1_D[2] MMC1_45_D[2] */ - GPIO_NC, - /* GPIO_S0_SC[020] MMC1_D[3] MMC1_45_D[3] */ - GPIO_NC, - /* GPIO_S0_SC[021] MMC1_D[4] MMC1_45_D[4] */ - GPIO_NC, - /* GPIO_S0_SC[022] MMC1_D[5] MMC1_45_D[5] */ - GPIO_NC, - /* GPIO_S0_SC[023] MMC1_D[6] MMC1_45_D[6] */ - GPIO_NC, - /* GPIO_S0_SC[024] MMC1_D[7] MMC1_45_D[7] */ - GPIO_NC, - /* GPIO_S0_SC[025] MMC1_CMD MMC1_45_CMD */ - GPIO_NC, - /* GPIO_S0_SC[026] MMC1_RST# SATA_DEVSLP[0] MMC1_45_RST# */ - GPIO_NC, - /* GPIO_S0_SC[027] SD2_CLK */ - GPIO_NC, - /* GPIO_S0_SC[028] SD2_D[0] */ - GPIO_NC, - /* GPIO_S0_SC[029] SD2_D[1] */ - GPIO_NC, - /* GPIO_S0_SC[030] SD2_D[2] */ - GPIO_NC, - /* GPIO_S0_SC[031] SD2_D[3]_CD# */ - GPIO_NC, - /* GPIO_S0_SC[032] SD2_CMD */ - GPIO_NC, - /* GPIO_S0_SC[033] SD3_CLK */ - GPIO_NC, - /* GPIO_S0_SC[034] SD3_D[0] */ - GPIO_NC, - /* GPIO_S0_SC[035] SD3_D[1] */ - GPIO_NC, - /* GPIO_S0_SC[036] SD3_D[2] */ - GPIO_NC, - /* GPIO_S0_SC[037] SD3_D[3] */ - GPIO_NC, - /* GPIO_S0_SC[038] SD3_CD# */ - GPIO_NC, - /* GPIO_S0_SC[039] SD3_CMD */ - GPIO_FUNC1, - /* GPIO_S0_SC[040] SD3_1P8EN */ - GPIO_FUNC1, - /* GPIO_S0_SC[041] SD3_PWREN# */ - GPIO_FUNC1, - /* GPIO_S0_SC[042] ILB_LPC_AD[0] */ - GPIO_FUNC1, - /* GPIO_S0_SC[043] ILB_LPC_AD[1] */ - GPIO_FUNC1, - /* GPIO_S0_SC[044] ILB_LPC_AD[2] */ - GPIO_FUNC1, - /* GPIO_S0_SC[045] ILB_LPC_AD[3] */ - GPIO_FUNC1, - /* GPIO_S0_SC[046] ILB_LPC_FRAME# */ - GPIO_FUNC1, - /* GPIO_S0_SC[047] ILB_LPC_CLK[0] */ - GPIO_NC, - /* GPIO_S0_SC[048] ILB_LPC_CLK[1] */ - GPIO_FUNC1, - /* GPIO_S0_SC[049] ILB_LPC_CLKRUN# */ - GPIO_FUNC1, - /* GPIO_S0_SC[050] ILB_LPC_SERIRQ */ - GPIO_FUNC1, - /* GPIO_S0_SC[051] PCU_SMB_DATA */ - GPIO_FUNC1, - /* GPIO_S0_SC[052] PCU_SMB_CLK */ - GPIO_FUNC1, - /* GPIO_S0_SC[053] PCU_SMB_ALERT# */ - GPIO_NC, - /* GPIO_S0_SC[054] ILB_8254_SPKR RESERVED*/ - GPIO_DEFAULT, - /* GPIO_S0_SC[055] RESERVED */ - GPIO_DEFAULT, - /* GPIO_S0_SC[056] RESERVED */ - GPIO_FUNC1, - /* GPIO_S0_SC[057] PCU_UART_TXD */ - GPIO_DEFAULT, - /* GPIO_S0_SC[058] RESERVED */ - GPIO_DEFAULT, - /* GPIO_S0_SC[059] RESERVED */ - GPIO_DEFAULT, - /* GPIO_S0_SC[060] RESERVED */ - GPIO_FUNC1, - /* GPIO_S0_SC[061] PCU_UART_RXD */ - GPIO_NC, - /* GPIO_S0_SC[062] LPE_I2S2_CLK SATA_DEVSLP[1] RESERVED */ - GPIO_FUNC1, - /* GPIO_S0_SC[063] LPE_I2S2_FRM RESERVED*/ - GPIO_NC, - /* GPIO_S0_SC[064] LPE_I2S2_DATAIN */ - GPIO_FUNC1, - /* GPIO_S0_SC[065] LPE_I2S2_DATAOUT*/ - GPIO_NC, - /* GPIO_S0_SC[066] SIO_SPI_CS# */ - GPIO_NC, - /* GPIO_S0_SC[067] SIO_SPI_MISO */ - GPIO_NC, - /* GPIO_S0_SC[068] SIO_SPI_MOSI */ - GPIO_NC, - /* GPIO_S0_SC[069] SIO_SPI_CLK */ - GPIO_FUNC1, - /* GPIO_S0_SC[070] SIO_UART1_RXD RESERVED*/ - GPIO_FUNC1, - /* GPIO_S0_SC[071] SIO_UART1_TXD RESERVED*/ - GPIO_NC, - /* GPIO_S0_SC[072] SIO_UART1_RTS# */ - GPIO_DEFAULT, - /* GPIO_S0_SC[073] SIO_UART1_CTS# */ - GPIO_NC, - /* GPIO_S0_SC[074] SIO_UART2_RXD */ - GPIO_NC, - /* GPIO_S0_SC[075] SIO_UART2_TXD */ - GPIO_NC, - /* GPIO_S0_SC[076] SIO_UART2_RTS# */ - GPIO_NC, - /* GPIO_S0_SC[077] SIO_UART2_CTS# */ - GPIO_FUNC1, - /* GPIO_S0_SC[078] SIO_I2C0_DATA */ - GPIO_FUNC1, - /* GPIO_S0_SC[079] SIO_I2C0_CLK */ - GPIO_NC, - /* GPIO_S0_SC[080] SIO_I2C1_DATA */ - GPIO_NC, - /* GPIO_S0_SC[081] SIO_I2C1_CLK RESERVED*/ - GPIO_FUNC1, - /* GPIO_S0_SC[082] SIO_I2C2_DATA */ - GPIO_FUNC1, - /* GPIO_S0_SC[083] SIO_I2C2_CLK */ - GPIO_NC, - /* GPIO_S0_SC[084] SIO_I2C3_DATA */ - GPIO_NC, - /* GPIO_S0_SC[085] SIO_I2C3_CLK */ - GPIO_NC, - /* GPIO_S0_SC[086] SIO_I2C4_DATA */ - GPIO_NC, - /* GPIO_S0_SC[087] SIO_I2C4_CLK */ - GPIO_NC, - /* GPIO_S0_SC[088] SIO_I2C5_DATA */ - GPIO_NC, - /* GPIO_S0_SC[089] SIO_I2C5_CLK */ - GPIO_NC, - /* GPIO_S0_SC[090] SIO_I2C6_DATA ILB_NMI */ - GPIO_NC, - /* GPIO_S0_SC[091] SIO_I2C6_CLK SD3_WP */ - GPIO_NC, - /* RESERVED GPIO_S0_SC[092] */ - GPIO_NC, - /* RESERVED GPIO_S0_SC[093] */ - GPIO_NC, - /* GPIO_S0_SC[094] SIO_PWM[0] */ - GPIO_NC, - /* GPIO_S0_SC[095] SIO_PWM[1] */ - GPIO_NC, - /* GPIO_S0_SC[096] PMC_PLT_CLK[0] */ - GPIO_NC, - /* GPIO_S0_SC[097] PMC_PLT_CLK[1] */ - GPIO_NC, - /* GPIO_S0_SC[098] PMC_PLT_CLK[2] */ - GPIO_NC, - /* GPIO_S0_SC[099] PMC_PLT_CLK[3] */ - GPIO_NC, - /* GPIO_S0_SC[100] PMC_PLT_CLK[4] */ - GPIO_NC, - /* GPIO_S0_SC[101] PMC_PLT_CLK[5]*/ - GPIO_END}; - -/* SSUS GPIOs (GPIO_S5) */ -static const struct soc_gpio_map gpssus_gpio_map[] = { - GPIO_DEFAULT, - /* GPIO_S5[00] RESERVED- */ - GPIO_NC, - /* GPIO_S5[01] RESERVED RESERVED RESERVED PMC_WAKE_PCIE[1]# */ - GPIO_DEFAULT, - /* GPIO_S5[02] RESERVED RESERVED RESERVED PMC_WAKE_PCIE[2]# */ - GPIO_DEFAULT, - /* GPIO_S5[03] RESERVED RESERVED RESERVED PMC_WAKE_PCIE[3]# */ - GPIO_DEFAULT, - /* GPIO_S5[04] RESERVED RESERVED RESERVED RESERVED */ - GPIO_DEFAULT, - /* GPIO_S5[05] PMC_SUSCLK[1] RESERVED RESERVED RESERVED */ - GPIO_DEFAULT, - /* GPIO_S5[06] PMC_SUSCLK[2] RESERVED RESERVED RESERVED */ - GPIO_DEFAULT, - /* GPIO_S5[07] PMC_SUSCLK[3] RESERVED RESERVED RESERVED */ - GPIO_DEFAULT, - /* GPIO_S5[08] RESERVED RESERVED RESERVED RESERVED */ - GPIO_NC, - /* GPIO_S5[09] RESERVED RESERVED RESERVED RESERVED */ - GPIO_NC, - /* GPIO_S5[10] RESERVED RESERVED RESERVED*/ - GPIO_DEFAULT, - /* PMC_SUSPWRDNACK GPIO_S5[11]*/ - GPIO_NC, - /* PMC_SUSCLK[0] GPIO_S5[12]*/ - GPIO_NC, - /* RESERVED GPIO_S5[13]*/ - GPIO_FUNC2, - /* RESERVED GPIO_S5[14] USB_ULPI_RST#*/ - GPIO_FUNC0, - /* PMC_WAKE_PCIE[0]# GPIO_S5[15]*/ - GPIO_FUNC0, - /* PMC_PWRBTN# GPIO_S5[16]*/ - GPIO_FUNC1, - /* RESERVED GPIO_S5[17]*/ - GPIO_FUNC0, - /* PMC_SUS_STAT# GPIO_S5[18]*/ - GPIO_FUNC0, - /* USB_OC[0]# GPIO_S5[19]*/ - GPIO_FUNC0, - /* USB_OC[1]# GPIO_S5[20]*/ - GPIO_NC, - /* PCU_SPI_CS[1]# GPIO_S5[21]*/ - GPIO_NC, - /* GPIO_S5[22] RESERVED RESERVED RESERVED RESERVED */ - GPIO_NC, - /* GPIO_S5[23] RESERVED RESERVED RESERVED RESERVED */ - GPIO_NC, - /* GPIO_S5[24] RESERVED RESERVED RESERVED RESERVED */ - GPIO_DEFAULT, - /* GPIO_S5[25] RESERVED RESERVED RESERVED RESERVED */ - GPIO_NC, - /* GPIO_S5[26] RESERVED RESERVED RESERVED RESERVED */ - GPIO_NC, - /* GPIO_S5[27] RESERVED RESERVED RESERVED RESERVED */ - GPIO_NC, - /* GPIO_S5[28] RESERVED RESERVED RESERVED RESERVED */ - GPIO_NC, - /* GPIO_S5[29] RESERVED RESERVED RESERVED RESERVED */ - GPIO_NC, - /* GPIO_S5[30] RESERVED RESERVED RESERVED RESERVED */ - GPIO_FUNC1, - /* GPIO_S5[31] USB_ULPI_CLK RESERVED RESERVED*/ - GPIO_NC, - /* GPIO_S5[32] USB_ULPI_DATA[0] RESERVED RESERVED*/ - GPIO_NC, - /* GPIO_S5[33] USB_ULPI_DATA[1] RESERVED RESERVED*/ - GPIO_NC, - /* GPIO_S5[34] USB_ULPI_DATA[2] RESERVED RESERVED*/ - GPIO_NC, - /* GPIO_S5[35] USB_ULPI_DATA[3] RESERVED RESERVED*/ - GPIO_NC, - /* GPIO_S5[36] USB_ULPI_DATA[4] RESERVED RESERVED*/ - GPIO_NC, - /* GPIO_S5[37] USB_ULPI_DATA[5] RESERVED RESERVED*/ - GPIO_NC, - /* GPIO_S5[38] USB_ULPI_DATA[6] RESERVED RESERVED*/ - GPIO_NC, - /* GPIO_S5[39] USB_ULPI_DATA[7] RESERVED RESERVED*/ - GPIO_NC, - /* GPIO_S5[40] USB_ULPI_DIR RESERVED RESERVED*/ - GPIO_NC, - /* GPIO_S5[41] USB_ULPI_NXT RESERVED RESERVED*/ - GPIO_NC, - /* GPIO_S5[42] USB_ULPI_STP RESERVED RESERVED*/ - GPIO_NC, - /* GPIO_S5[43] USB_ULPI_REFCLK RESERVED RESERVED*/ - GPIO_END}; - -static struct soc_gpio_config gpio_config = { - .ncore = gpncore_gpio_map, - .score = gpscore_gpio_map, - .ssus = gpssus_gpio_map, - .core_dirq = NULL, - .sus_dirq = NULL, -}; - -struct soc_gpio_config *mainboard_get_gpios(void) { return &gpio_config; } diff --git a/src/mainboard/opencellular/rotundu/variants/supabrckv1/devicetree.cb b/src/mainboard/opencellular/rotundu/variants/supabrckv1/devicetree.cb deleted file mode 100644 index c0bd2f0fe2..0000000000 --- a/src/mainboard/opencellular/rotundu/variants/supabrckv1/devicetree.cb +++ /dev/null @@ -1,85 +0,0 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2013-2014 Sage Electronic Engineering, LLC. -## Copyright (C) 2014 Intel Corporation -## Copyright (C) 2017-present Facebook, Inc. -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; version 2 of the License. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## - -chip soc/intel/fsp_baytrail - - #### ACPI Register Settings #### - register "fadt_pm_profile" = "PM_UNSPECIFIED" - register "fadt_boot_arch" = "ACPI_FADT_LEGACY_FREE" - - #### FSP register settings #### - register "PcdSataMode" = "SATA_MODE_AHCI" - register "PcdMrcInitSPDAddr1" = "0xa0" - register "PcdMrcInitSPDAddr2" = "0xa2" - register "PcdMrcInitMmioSize" = "MMIO_SIZE_DEFAULT" - register "PcdeMMCBootMode" = "EMMC_FOLLOWS_DEVICETREE" - register "PcdIgdDvmt50PreAlloc" = "IGD_MEMSIZE_DEFAULT" - register "PcdApertureSize" = "APERTURE_SIZE_DEFAULT" - register "PcdGttSize" = "GTT_SIZE_DEFAULT" - register "PcdLpssSioEnablePciMode" = "LPSS_PCI_MODE_DEFAULT" - register "AzaliaAutoEnable" = "AZALIA_FOLLOWS_DEVICETREE" - register "LpeAcpiModeEnable" = "LPE_ACPI_MODE_DISABLED" - register "EnableMemoryDown" = "MEMORY_DOWN_DISABLE" - register "DIMM0Enable" = "DIMM0_ENABLE" - register "DIMM1Enable" = "DIMM1_DISABLE" - - device cpu_cluster 0 on - device lapic 0 on end - end - - device domain 0 on - device pci 00.0 on end # 8086 0F00 - SoC router - device pci 02.0 on end # 8086 0F31 - GFX - device pci 03.0 off end # 8086 0F38 - MIPI - camera interface - - device pci 10.0 off end # 8086 0F14 - EMMC 4.1 Port (MMC1 pins) - (DO NOT USE) - Only 1 EMMC port at a time - device pci 11.0 off end # 8086 0F15 - SDIO Port (SD2 pins) - device pci 12.0 off end # 8086 0F16 - SD Port (SD3 pins) - device pci 13.0 on end # 8086 0F23 - SATA AHCI (0F20, 0F21, 0F22, 0F23) - device pci 14.0 on end # 8086 0F35 - USB XHCI - Only 1 USB controller at a time - device pci 15.0 off end # 8086 0F28 - LP Engine Audio - device pci 16.0 off end # 8086 0F37 - OTG controller - device pci 17.0 on end # 8086 0F50 - EMMC 4.5 Port (MMC1 pins) - Only 1 EMMC port at a time - device pci 18.0 on end # 8086 0F40 - SIO - DMA - device pci 18.1 on end # 8086 0F41 - I2C Port 1 - device pci 18.2 off end # 8086 0F42 - I2C Port 2 - device pci 18.3 on end # 8086 0F43 - I2C Port 3 - device pci 18.4 off end # 8086 0F44 - I2C Port 4 - device pci 18.5 off end # 8086 0F45 - I2C Port 5 - device pci 18.6 off end # 8086 0F46 - I2C Port 6 - device pci 18.7 off end # 8086 0F47 - I2C Port 7 - device pci 1a.0 on end # 8086 0F18 - Trusted Execution Engine - device pci 1b.0 off end # 8086 0F04 - HD Audio - device pci 1c.0 on end # 8086 0F48 - PCIe Root Port 1 (RADIO CARD) - device pci 1c.1 on end # 8086 0F4A - PCIe Root Port 2 (GBE PHY 1) - device pci 1c.2 on end # 8086 0F4C - PCIe Root Port 3 (GBE PHY 2) - device pci 1c.3 off end # 8086 0F4E - PCIe Root Port 4 (NC) - device pci 1d.0 off end # 8086 0F34 - USB EHCI - Only 1 USB controller at a time - device pci 1e.0 on end # 8086 0F06 - SIO - DMA - device pci 1e.1 off end # 8086 0F08 - PWM 1 - device pci 1e.2 off end # 8086 0F09 - PWM 2 - device pci 1e.3 on end # 8086 0F0A - HSUART 1 - device pci 1e.4 off end # 8086 0F0C - HSUART 2 - device pci 1e.5 off end # 8086 0F0E - SPI - device pci 1f.0 on - chip drivers/pc80/tpm - device pnp 0c31.0 on end - end - end # 8086 0F1C - LPC bridge - device pci 1f.3 on end # 8086 0F12 - SMBus 0 - end -end diff --git a/src/mainboard/opencellular/rotundu/variants/supabrckv1/gpio.c b/src/mainboard/opencellular/rotundu/variants/supabrckv1/gpio.c deleted file mode 100644 index c9d54268f7..0000000000 --- a/src/mainboard/opencellular/rotundu/variants/supabrckv1/gpio.c +++ /dev/null @@ -1,365 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2013 Google Inc. - * Copyright (C) 2014 Sage Electronic Engineering, LLC. - * Copyright (C) 2017-present Facebook, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include "../../irqroute.h" - -#define GPIO_FUNC3_PULL_UP_20K GPIO_FUNC(3, PULL_UP, 20K) -#define GPIO_FUNC3_PULL_DOWN_20K GPIO_FUNC(3, PULL_DOWN, 20K) - -/* NCORE GPIOs */ -static const struct soc_gpio_map gpncore_gpio_map[] = { - - GPIO_FUNC2, /* GPIO 0 */ - GPIO_FUNC2, /* GPIO 1 */ - GPIO_FUNC2, /* GPIO 2 */ - GPIO_FUNC2, /* GPIO 3 */ - GPIO_FUNC2, /* GPIO 4 */ - GPIO_FUNC2, /* GPIO 5 */ - GPIO_FUNC2, /* GPIO 6 */ - GPIO_FUNC2, /* GPIO 7 */ - GPIO_FUNC2, /* GPIO 8 */ - GPIO_FUNC2, /* GPIO 9 */ - GPIO_FUNC2, /* GPIO 10 */ - GPIO_FUNC2, /* GPIO 11 */ - GPIO_FUNC2, /* GPIO 12 */ - GPIO_FUNC2, /* GPIO 13 */ - GPIO_FUNC2, /* GPIO 14 */ - GPIO_FUNC2, /* GPIO 15 */ - GPIO_FUNC2, /* GPIO 16 */ - GPIO_FUNC2, /* GPIO 17 */ - GPIO_FUNC2, /* GPIO 18 */ - GPIO_FUNC2, /* GPIO 19 */ - GPIO_FUNC2, /* GPIO 20 */ - GPIO_FUNC2, /* GPIO 21 */ - GPIO_FUNC2, /* GPIO 22 */ - GPIO_FUNC2, /* GPIO 23 */ - GPIO_FUNC2, /* GPIO 24 */ - GPIO_FUNC2, /* GPIO 25 */ - GPIO_FUNC2, /* GPIO 26 */ - GPIO_END}; - -/* SCORE GPIOs (GPIO_S0_SC_XX) */ -static const struct soc_gpio_map gpscore_gpio_map[] = { - GPIO_NC, - /* GPIO_S0_SC[000] SATA_GP[0] */ - GPIO_NC, - /* GPIO_S0_SC[001] SATA_GP[1] SATA_DEVSLP[0]*/ - GPIO_FUNC1, - /* GPIO_S0_SC[002] SATA_LED# */ - GPIO_FUNC1, - /* GPIO_S0_SC[003] PCIE_CLKREQ[0]# */ - GPIO_FUNC1, - /* GPIO_S0_SC[004] PCIE_CLKREQ[1]# */ - GPIO_FUNC1, - /* GPIO_S0_SC[005] PCIE_CLKREQ[2]# */ - GPIO_FUNC1, - /* GPIO_S0_SC[006] PCIE_CLKREQ[3]# */ - GPIO_FUNC2, - /* GPIO_S0_SC[007] RESERVED SD3_WP */ - GPIO_NC, - /* GPIO_S0_SC[008] I2S0_CLK HDA_RST#*/ - GPIO_NC, - /* GPIO_S0_SC[009] I2S0_FRM HDA_SYNC*/ - GPIO_NC, - /* GPIO_S0_SC[010] I2S0_DATAOUT HDA_CLK */ - GPIO_NC, - /* GPIO_S0_SC[011] I2S0_DATAIN HDA_SDO */ - GPIO_NC, - /* GPIO_S0_SC[012] I2S1_CLK HDA_SDI[0]*/ - GPIO_NC, - /* GPIO_S0_SC[013] I2S1_FRM HDA_SDI[1]*/ - GPIO_NC, - /* GPIO_S0_SC[014] I2S1_DATAOUT RESERVED*/ - GPIO_DEFAULT, - /* GPIO_S0_SC[015] I2S1_DATAIN RESERVED*/ - GPIO_FUNC3_PULL_DOWN_20K, - /* GPIO_S0_SC[016] MMC1_CLK MMC1_45_CLK */ - GPIO_FUNC3_PULL_UP_20K, - /* GPIO_S0_SC[017] MMC1_D[0] MMC1_45_D[0] */ - GPIO_FUNC3_PULL_UP_20K, - /* GPIO_S0_SC[018] MMC1_D[1] MMC1_45_D[1] */ - GPIO_FUNC3_PULL_UP_20K, - /* GPIO_S0_SC[019] MMC1_D[2] MMC1_45_D[2] */ - GPIO_FUNC3_PULL_UP_20K, - /* GPIO_S0_SC[020] MMC1_D[3] MMC1_45_D[3] */ - GPIO_FUNC3_PULL_UP_20K, - /* GPIO_S0_SC[021] MMC1_D[4] MMC1_45_D[4] */ - GPIO_FUNC3_PULL_UP_20K, - /* GPIO_S0_SC[022] MMC1_D[5] MMC1_45_D[5] */ - GPIO_FUNC3_PULL_UP_20K, - /* GPIO_S0_SC[023] MMC1_D[6] MMC1_45_D[6] */ - GPIO_FUNC3_PULL_UP_20K, - /* GPIO_S0_SC[024] MMC1_D[7] MMC1_45_D[7] */ - GPIO_FUNC3_PULL_UP_20K, - /* GPIO_S0_SC[025] MMC1_CMD MMC1_45_CMD */ - GPIO_FUNC3_PULL_DOWN_20K, - /* GPIO_S0_SC[026] MMC1_RST# SATA_DEVSLP[0] MMC1_45_RST# */ - GPIO_NC, - /* GPIO_S0_SC[027] SD2_CLK */ - GPIO_NC, - /* GPIO_S0_SC[028] SD2_D[0] */ - GPIO_NC, - /* GPIO_S0_SC[029] SD2_D[1] */ - GPIO_NC, - /* GPIO_S0_SC[030] SD2_D[2] */ - GPIO_NC, - /* GPIO_S0_SC[031] SD2_D[3]_CD# */ - GPIO_NC, - /* GPIO_S0_SC[032] SD2_CMD */ - GPIO_NC, - /* GPIO_S0_SC[033] SD3_CLK */ - GPIO_NC, - /* GPIO_S0_SC[034] SD3_D[0] */ - GPIO_NC, - /* GPIO_S0_SC[035] SD3_D[1] */ - GPIO_NC, - /* GPIO_S0_SC[036] SD3_D[2] */ - GPIO_NC, - /* GPIO_S0_SC[037] SD3_D[3] */ - GPIO_NC, - /* GPIO_S0_SC[038] SD3_CD# */ - GPIO_NC, - /* GPIO_S0_SC[039] SD3_CMD */ - GPIO_FUNC1, - /* GPIO_S0_SC[040] SD3_1P8EN */ - GPIO_FUNC1, - /* GPIO_S0_SC[041] SD3_PWREN# */ - GPIO_FUNC1, - /* GPIO_S0_SC[042] ILB_LPC_AD[0] */ - GPIO_FUNC1, - /* GPIO_S0_SC[043] ILB_LPC_AD[1] */ - GPIO_FUNC1, - /* GPIO_S0_SC[044] ILB_LPC_AD[2] */ - GPIO_FUNC1, - /* GPIO_S0_SC[045] ILB_LPC_AD[3] */ - GPIO_FUNC1, - /* GPIO_S0_SC[046] ILB_LPC_FRAME# */ - GPIO_FUNC1, - /* GPIO_S0_SC[047] ILB_LPC_CLK[0] */ - GPIO_NC, - /* GPIO_S0_SC[048] ILB_LPC_CLK[1] */ - GPIO_FUNC1, - /* GPIO_S0_SC[049] ILB_LPC_CLKRUN# */ - GPIO_FUNC1, - /* GPIO_S0_SC[050] ILB_LPC_SERIRQ */ - GPIO_FUNC1, - /* GPIO_S0_SC[051] PCU_SMB_DATA */ - GPIO_FUNC1, - /* GPIO_S0_SC[052] PCU_SMB_CLK */ - GPIO_FUNC1, - /* GPIO_S0_SC[053] PCU_SMB_ALERT# */ - GPIO_NC, - /* GPIO_S0_SC[054] ILB_8254_SPKR RESERVED*/ - GPIO_DEFAULT, - /* GPIO_S0_SC[055] RESERVED */ - GPIO_DEFAULT, - /* GPIO_S0_SC[056] RESERVED */ - GPIO_FUNC1, - /* GPIO_S0_SC[057] PCU_UART_TXD */ - GPIO_DEFAULT, - /* GPIO_S0_SC[058] RESERVED */ - GPIO_DEFAULT, - /* GPIO_S0_SC[059] RESERVED */ - GPIO_DEFAULT, - /* GPIO_S0_SC[060] RESERVED */ - GPIO_FUNC1, - /* GPIO_S0_SC[061] PCU_UART_RXD */ - GPIO_NC, - /* GPIO_S0_SC[062] LPE_I2S2_CLK SATA_DEVSLP[1] RESERVED */ - GPIO_FUNC1, - /* GPIO_S0_SC[063] LPE_I2S2_FRM RESERVED*/ - GPIO_NC, - /* GPIO_S0_SC[064] LPE_I2S2_DATAIN */ - GPIO_FUNC1, - /* GPIO_S0_SC[065] LPE_I2S2_DATAOUT*/ - GPIO_NC, - /* GPIO_S0_SC[066] SIO_SPI_CS# */ - GPIO_NC, - /* GPIO_S0_SC[067] SIO_SPI_MISO */ - GPIO_NC, - /* GPIO_S0_SC[068] SIO_SPI_MOSI */ - GPIO_NC, - /* GPIO_S0_SC[069] SIO_SPI_CLK */ - GPIO_FUNC1, - /* GPIO_S0_SC[070] SIO_UART1_RXD RESERVED*/ - GPIO_FUNC1, - /* GPIO_S0_SC[071] SIO_UART1_TXD RESERVED*/ - GPIO_NC, - /* GPIO_S0_SC[072] SIO_UART1_RTS# */ - GPIO_DEFAULT, - /* GPIO_S0_SC[073] SIO_UART1_CTS# */ - GPIO_NC, - /* GPIO_S0_SC[074] SIO_UART2_RXD */ - GPIO_NC, - /* GPIO_S0_SC[075] SIO_UART2_TXD */ - GPIO_NC, - /* GPIO_S0_SC[076] SIO_UART2_RTS# */ - GPIO_NC, - /* GPIO_S0_SC[077] SIO_UART2_CTS# */ - GPIO_FUNC1, - /* GPIO_S0_SC[078] SIO_I2C0_DATA */ - GPIO_FUNC1, - /* GPIO_S0_SC[079] SIO_I2C0_CLK */ - GPIO_NC, - /* GPIO_S0_SC[080] SIO_I2C1_DATA */ - GPIO_NC, - /* GPIO_S0_SC[081] SIO_I2C1_CLK RESERVED*/ - GPIO_FUNC1, - /* GPIO_S0_SC[082] SIO_I2C2_DATA */ - GPIO_FUNC1, - /* GPIO_S0_SC[083] SIO_I2C2_CLK */ - GPIO_NC, - /* GPIO_S0_SC[084] SIO_I2C3_DATA */ - GPIO_NC, - /* GPIO_S0_SC[085] SIO_I2C3_CLK */ - GPIO_NC, - /* GPIO_S0_SC[086] SIO_I2C4_DATA */ - GPIO_NC, - /* GPIO_S0_SC[087] SIO_I2C4_CLK */ - GPIO_NC, - /* GPIO_S0_SC[088] SIO_I2C5_DATA */ - GPIO_NC, - /* GPIO_S0_SC[089] SIO_I2C5_CLK */ - GPIO_NC, - /* GPIO_S0_SC[090] SIO_I2C6_DATA ILB_NMI */ - GPIO_NC, - /* GPIO_S0_SC[091] SIO_I2C6_CLK SD3_WP */ - GPIO_NC, - /* RESERVED GPIO_S0_SC[092] */ - GPIO_NC, - /* RESERVED GPIO_S0_SC[093] */ - GPIO_NC, - /* GPIO_S0_SC[094] SIO_PWM[0] */ - GPIO_NC, - /* GPIO_S0_SC[095] SIO_PWM[1] */ - GPIO_NC, - /* GPIO_S0_SC[096] PMC_PLT_CLK[0] */ - GPIO_NC, - /* GPIO_S0_SC[097] PMC_PLT_CLK[1] */ - GPIO_NC, - /* GPIO_S0_SC[098] PMC_PLT_CLK[2] */ - GPIO_NC, - /* GPIO_S0_SC[099] PMC_PLT_CLK[3] */ - GPIO_NC, - /* GPIO_S0_SC[100] PMC_PLT_CLK[4] */ - GPIO_NC, - /* GPIO_S0_SC[101] PMC_PLT_CLK[5]*/ - GPIO_END}; - -/* SSUS GPIOs (GPIO_S5) */ -static const struct soc_gpio_map gpssus_gpio_map[] = { - GPIO_DEFAULT, - /* GPIO_S5[00] RESERVED- */ - GPIO_NC, - /* GPIO_S5[01] RESERVED RESERVED RESERVED PMC_WAKE_PCIE[1]# */ - GPIO_DEFAULT, - /* GPIO_S5[02] RESERVED RESERVED RESERVED PMC_WAKE_PCIE[2]# */ - GPIO_DEFAULT, - /* GPIO_S5[03] RESERVED RESERVED RESERVED PMC_WAKE_PCIE[3]# */ - GPIO_DEFAULT, - /* GPIO_S5[04] RESERVED RESERVED RESERVED RESERVED */ - GPIO_DEFAULT, - /* GPIO_S5[05] PMC_SUSCLK[1] RESERVED RESERVED RESERVED */ - GPIO_DEFAULT, - /* GPIO_S5[06] PMC_SUSCLK[2] RESERVED RESERVED RESERVED */ - GPIO_DEFAULT, - /* GPIO_S5[07] PMC_SUSCLK[3] RESERVED RESERVED RESERVED */ - GPIO_DEFAULT, - /* GPIO_S5[08] RESERVED RESERVED RESERVED RESERVED */ - GPIO_NC, - /* GPIO_S5[09] RESERVED RESERVED RESERVED RESERVED */ - GPIO_NC, - /* GPIO_S5[10] RESERVED RESERVED RESERVED*/ - GPIO_DEFAULT, - /* PMC_SUSPWRDNACK GPIO_S5[11]*/ - GPIO_NC, - /* PMC_SUSCLK[0] GPIO_S5[12]*/ - GPIO_NC, - /* RESERVED GPIO_S5[13]*/ - GPIO_FUNC2, - /* RESERVED GPIO_S5[14] USB_ULPI_RST#*/ - GPIO_FUNC0, - /* PMC_WAKE_PCIE[0]# GPIO_S5[15]*/ - GPIO_FUNC0, - /* PMC_PWRBTN# GPIO_S5[16]*/ - GPIO_FUNC1, - /* RESERVED GPIO_S5[17]*/ - GPIO_FUNC0, - /* PMC_SUS_STAT# GPIO_S5[18]*/ - GPIO_FUNC0, - /* USB_OC[0]# GPIO_S5[19]*/ - GPIO_FUNC0, - /* USB_OC[1]# GPIO_S5[20]*/ - GPIO_NC, - /* PCU_SPI_CS[1]# GPIO_S5[21]*/ - GPIO_NC, - /* GPIO_S5[22] RESERVED RESERVED RESERVED RESERVED */ - GPIO_NC, - /* GPIO_S5[23] RESERVED RESERVED RESERVED RESERVED */ - GPIO_NC, - /* GPIO_S5[24] RESERVED RESERVED RESERVED RESERVED */ - GPIO_DEFAULT, - /* GPIO_S5[25] RESERVED RESERVED RESERVED RESERVED */ - GPIO_NC, - /* GPIO_S5[26] RESERVED RESERVED RESERVED RESERVED */ - GPIO_NC, - /* GPIO_S5[27] RESERVED RESERVED RESERVED RESERVED */ - GPIO_NC, - /* GPIO_S5[28] RESERVED RESERVED RESERVED RESERVED */ - GPIO_NC, - /* GPIO_S5[29] RESERVED RESERVED RESERVED RESERVED */ - GPIO_NC, - /* GPIO_S5[30] RESERVED RESERVED RESERVED RESERVED */ - GPIO_FUNC1, - /* GPIO_S5[31] USB_ULPI_CLK RESERVED RESERVED*/ - GPIO_NC, - /* GPIO_S5[32] USB_ULPI_DATA[0] RESERVED RESERVED*/ - GPIO_NC, - /* GPIO_S5[33] USB_ULPI_DATA[1] RESERVED RESERVED*/ - GPIO_NC, - /* GPIO_S5[34] USB_ULPI_DATA[2] RESERVED RESERVED*/ - GPIO_NC, - /* GPIO_S5[35] USB_ULPI_DATA[3] RESERVED RESERVED*/ - GPIO_NC, - /* GPIO_S5[36] USB_ULPI_DATA[4] RESERVED RESERVED*/ - GPIO_NC, - /* GPIO_S5[37] USB_ULPI_DATA[5] RESERVED RESERVED*/ - GPIO_NC, - /* GPIO_S5[38] USB_ULPI_DATA[6] RESERVED RESERVED*/ - GPIO_NC, - /* GPIO_S5[39] USB_ULPI_DATA[7] RESERVED RESERVED*/ - GPIO_NC, - /* GPIO_S5[40] USB_ULPI_DIR RESERVED RESERVED*/ - GPIO_NC, - /* GPIO_S5[41] USB_ULPI_NXT RESERVED RESERVED*/ - GPIO_NC, - /* GPIO_S5[42] USB_ULPI_STP RESERVED RESERVED*/ - GPIO_NC, - /* GPIO_S5[43] USB_ULPI_REFCLK RESERVED RESERVED*/ - GPIO_END}; - -static struct soc_gpio_config gpio_config = { - .ncore = gpncore_gpio_map, - .score = gpscore_gpio_map, - .ssus = gpssus_gpio_map, - .core_dirq = NULL, - .sus_dirq = NULL, -}; - -struct soc_gpio_config *mainboard_get_gpios(void) { return &gpio_config; } diff --git a/src/mainboard/opencellular/rotundu/vboot-16M.fmd b/src/mainboard/opencellular/rotundu/vboot-16M.fmd deleted file mode 100644 index c1bedbf64b..0000000000 --- a/src/mainboard/opencellular/rotundu/vboot-16M.fmd +++ /dev/null @@ -1,30 +0,0 @@ -FLASH 16M { - SI_ALL@0x0 0x300000 { - SI_DESC@0x0 0x1000 - SI_ME@0x1000 0x2ff000 - } - SI_BIOS@0x300000 0xd00000 { - RW_SECTION_B@0x0 0x400000 { - VBLOCK_B@0x0 0x10000 - FW_MAIN_B(CBFS)@0x10000 0x3effc0 - RW_FWID_B@0x3fffc0 0x40 - } - RW_SECTION_A@0x400000 0x400000 { - VBLOCK_A@0x0 0x10000 - FW_MAIN_A(CBFS)@0x10000 0x3effc0 - RW_FWID_A@0x3fffc0 0x40 - } - RW_MRC_CACHE@0x800000 0x10000 - RW_VPD(PRESERVE)@0x810000 0x2000 - WP_RO@0x812000 0x4ee000 { - RO_VPD(PRESERVE)@0x0 0x4000 - RO_SECTION@0x4000 0x4ea000 { - FMAP@0x0 0x800 - RO_FRID@0x800 0x40 - RO_FRID_PAD@0x840 0x7c0 - GBB@0x1000 0xef000 - COREBOOT(CBFS)@0xf0000 0x3fa000 - } - } - } -} diff --git a/src/mainboard/opencellular/rotundu/vboot-8M.fmd b/src/mainboard/opencellular/rotundu/vboot-8M.fmd deleted file mode 100644 index 42b8b3151d..0000000000 --- a/src/mainboard/opencellular/rotundu/vboot-8M.fmd +++ /dev/null @@ -1,30 +0,0 @@ -FLASH 8M { - SI_ALL@0x0 0x300000 { - SI_DESC@0x0 0x1000 - SI_ME@0x1000 0x2ff000 - } - SI_BIOS@0x300000 0x500000 { - RW_SECTION_B@0x0 0x150040 { - VBLOCK_B@0x0 0x10000 - FW_MAIN_B(CBFS)@0x10000 0x140000 - RW_FWID_B@0x150000 0x40 - } - RW_SECTION_A@0x150040 0x150040 { - VBLOCK_A@0x0 0x10000 - FW_MAIN_A(CBFS)@0x10000 0x140000 - RW_FWID_A@0x150000 0x40 - } - RW_MRC_CACHE@0x2a0080 0x10000 - RW_VPD(PRESERVE)@0x2b0080 0x2000 - WP_RO@0x2b2080 0x24df80 { - RO_VPD(PRESERVE)@0x0 0x4000 - RO_SECTION@0x4000 0x249f80 { - FMAP@0x0 0x800 - RO_FRID@0x800 0x40 - RO_FRID_PAD@0x840 0x7c0 - GBB@0x1000 0xef000 - COREBOOT(CBFS)@0xf0000 0x159f80 - } - } - } -} diff --git a/src/mainboard/siemens/mc_tcu3/Kconfig b/src/mainboard/siemens/mc_tcu3/Kconfig deleted file mode 100644 index 8e01cdec4f..0000000000 --- a/src/mainboard/siemens/mc_tcu3/Kconfig +++ /dev/null @@ -1,59 +0,0 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2013-2014 Sage Electronic Engineering, LLC. -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; version 2 of the License. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## - -if BOARD_SIEMENS_MC_TCU3 - -config BOARD_SPECIFIC_OPTIONS - def_bool y - select SOC_INTEL_FSP_BAYTRAIL - select BOARD_ROMSIZE_KB_16384 - select HAVE_ACPI_TABLES - select HAVE_OPTION_TABLE - select ENABLE_BUILTIN_COM1 - select HAVE_FSP_BIN if FSP_PACKAGE_DEFAULT - select ENABLE_FSP_FAST_BOOT - select DRIVER_INTEL_I210 - select SOC_INTEL_FSP_BAYTRAIL_MD - select USE_BLOBS - select CBFS_AUTOGEN_ATTRIBUTES - select USE_SIEMENS_HWILIB - select DRIVERS_I2C_PTN3460 - -config MAINBOARD_DIR - string - default "siemens/mc_tcu3" - -config MAINBOARD_PART_NUMBER - string - default "MC_TCU3 (FSP)" - - -config MAX_CPUS - int - default 16 - -config CBFS_SIZE - hex - default 0x00e00000 - -config FSP_PACKAGE_DEFAULT - bool "Configure defaults for the Intel FSP package" - default n - -config VGA_BIOS - bool - default y if FSP_PACKAGE_DEFAULT - -endif # BOARD_SIEMENS_MC_TCU3 diff --git a/src/mainboard/siemens/mc_tcu3/Kconfig.name b/src/mainboard/siemens/mc_tcu3/Kconfig.name deleted file mode 100644 index cf644e5550..0000000000 --- a/src/mainboard/siemens/mc_tcu3/Kconfig.name +++ /dev/null @@ -1,2 +0,0 @@ -config BOARD_SIEMENS_MC_TCU3 - bool "MB TCU3" diff --git a/src/mainboard/siemens/mc_tcu3/Makefile.inc b/src/mainboard/siemens/mc_tcu3/Makefile.inc deleted file mode 100644 index 3de042242b..0000000000 --- a/src/mainboard/siemens/mc_tcu3/Makefile.inc +++ /dev/null @@ -1,19 +0,0 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2013 Google Inc. -## Copyright (C) 2017 Siemens AG -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; version 2 of the License. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## - -ramstage-y += gpio.c -ramstage-y += irqroute.c -ramstage-y += lcd_panel.c diff --git a/src/mainboard/siemens/mc_tcu3/acpi/ec.asl b/src/mainboard/siemens/mc_tcu3/acpi/ec.asl deleted file mode 100644 index e69de29bb2..0000000000 diff --git a/src/mainboard/siemens/mc_tcu3/acpi/mainboard.asl b/src/mainboard/siemens/mc_tcu3/acpi/mainboard.asl deleted file mode 100644 index b032ee189d..0000000000 --- a/src/mainboard/siemens/mc_tcu3/acpi/mainboard.asl +++ /dev/null @@ -1,20 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 Google Inc. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -Device (PWRB) -{ - Name(_HID, EisaId("PNP0C0C")) -} diff --git a/src/mainboard/siemens/mc_tcu3/acpi/superio.asl b/src/mainboard/siemens/mc_tcu3/acpi/superio.asl deleted file mode 100644 index e69de29bb2..0000000000 diff --git a/src/mainboard/siemens/mc_tcu3/acpi_tables.c b/src/mainboard/siemens/mc_tcu3/acpi_tables.c deleted file mode 100644 index d81798c6b0..0000000000 --- a/src/mainboard/siemens/mc_tcu3/acpi_tables.c +++ /dev/null @@ -1,58 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2012 Google Inc. - * Copyright (C) 2013-2014 Sage Electronic Engineering, LLC. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include - -void acpi_create_gnvs(global_nvs_t *gnvs) -{ - acpi_init_gnvs(gnvs); - - /* Enable USB ports in S3 */ - gnvs->s3u0 = 1; - gnvs->s3u1 = 1; - - /* Disable USB ports in S5 */ - gnvs->s5u0 = 0; - gnvs->s5u1 = 0; - - /* TPM Present */ - gnvs->tpmp = 0; - - /* Enable DPTF */ - gnvs->dpte = 0; -} - -unsigned long acpi_fill_madt(unsigned long current) -{ - /* Local APICs */ - current = acpi_create_madt_lapics(current); - - /* IOAPIC */ - current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, - 2, IO_APIC_ADDR, 0); - - current = acpi_madt_irq_overrides(current); - - return current; -} diff --git a/src/mainboard/siemens/mc_tcu3/board_info.txt b/src/mainboard/siemens/mc_tcu3/board_info.txt deleted file mode 100644 index 264dc3eace..0000000000 --- a/src/mainboard/siemens/mc_tcu3/board_info.txt +++ /dev/null @@ -1,4 +0,0 @@ -Board name: TCU3 -Category: misc -ROM protocol: SPI -ROM socketed: n diff --git a/src/mainboard/siemens/mc_tcu3/cmos.layout b/src/mainboard/siemens/mc_tcu3/cmos.layout deleted file mode 100644 index 3c5bc3b03d..0000000000 --- a/src/mainboard/siemens/mc_tcu3/cmos.layout +++ /dev/null @@ -1,119 +0,0 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2007-2008 coresystems GmbH -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; version 2 of the License. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## - -# ----------------------------------------------------------------- -entries - -#start-bit length config config-ID name -#0 8 r 0 seconds -#8 8 r 0 alarm_seconds -#16 8 r 0 minutes -#24 8 r 0 alarm_minutes -#32 8 r 0 hours -#40 8 r 0 alarm_hours -#48 8 r 0 day_of_week -#56 8 r 0 day_of_month -#64 8 r 0 month -#72 8 r 0 year -# ----------------------------------------------------------------- -# Status Register A -#80 4 r 0 rate_select -#84 3 r 0 REF_Clock -#87 1 r 0 UIP -# ----------------------------------------------------------------- -# Status Register B -#88 1 r 0 auto_switch_DST -#89 1 r 0 24_hour_mode -#90 1 r 0 binary_values_enable -#91 1 r 0 square-wave_out_enable -#92 1 r 0 update_finished_enable -#93 1 r 0 alarm_interrupt_enable -#94 1 r 0 periodic_interrupt_enable -#95 1 r 0 disable_clock_updates -# ----------------------------------------------------------------- -# Status Register C -#96 4 r 0 status_c_rsvd -#100 1 r 0 uf_flag -#101 1 r 0 af_flag -#102 1 r 0 pf_flag -#103 1 r 0 irqf_flag -# ----------------------------------------------------------------- -# Status Register D -#104 7 r 0 status_d_rsvd -#111 1 r 0 valid_cmos_ram -# ----------------------------------------------------------------- -# Diagnostic Status Register -#112 8 r 0 diag_rsvd1 - -# ----------------------------------------------------------------- -0 120 r 0 reserved_memory -#120 264 r 0 unused - -# ----------------------------------------------------------------- -# RTC_BOOT_BYTE (coreboot hardcoded) -384 1 e 4 boot_option -388 4 h 0 reboot_counter -#390 2 r 0 unused? - -# ----------------------------------------------------------------- -# coreboot config options: console -#392 3 r 0 unused -395 4 e 6 debug_level -#399 1 r 0 unused - -# coreboot config options: cpu -400 1 e 2 hyper_threading -#401 7 r 0 unused - -# coreboot config options: southbridge -408 1 e 1 nmi -409 2 e 7 power_on_after_fail -#411 5 r 0 unused - -# MRC Scrambler Seed values -896 32 r 0 mrc_scrambler_seed -928 32 r 0 mrc_scrambler_seed_s3 - -# coreboot config options: check sums -984 16 h 0 check_sum -#1000 24 r 0 amd_reserved - -# ----------------------------------------------------------------- - -enumerations - -#ID value text -1 0 Disable -1 1 Enable -2 0 Enable -2 1 Disable -4 0 Fallback -4 1 Normal -6 0 Emergency -6 1 Alert -6 2 Critical -6 3 Error -6 4 Warning -6 5 Notice -6 6 Info -6 7 Debug -6 8 Spew -7 0 Disable -7 1 Enable -7 2 Keep -# ----------------------------------------------------------------- -checksums - -checksum 392 415 984 diff --git a/src/mainboard/siemens/mc_tcu3/devicetree.cb b/src/mainboard/siemens/mc_tcu3/devicetree.cb deleted file mode 100644 index a1416e490e..0000000000 --- a/src/mainboard/siemens/mc_tcu3/devicetree.cb +++ /dev/null @@ -1,83 +0,0 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2013-2014 Sage Electronic Engineering, LLC. -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; version 2 of the License. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## - -chip soc/intel/fsp_baytrail - - #### ACPI Register Settings #### - register "fadt_pm_profile" = "PM_MOBILE" - register "fadt_boot_arch" = "ACPI_FADT_LEGACY_DEVICES | ACPI_FADT_8042" - - #### FSP register settings #### - register "PcdSataMode" = "SATA_MODE_AHCI" - register "PcdMrcInitSPDAddr1" = "SPD_ADDR_DEFAULT" - register "PcdMrcInitSPDAddr2" = "SPD_ADDR_DEFAULT" - register "PcdMrcInitMmioSize" = "MMIO_SIZE_DEFAULT" - register "PcdeMMCBootMode" = "EMMC_FOLLOWS_DEVICETREE" - register "PcdIgdDvmt50PreAlloc" = "IGD_MEMSIZE_DEFAULT" - register "PcdApertureSize" = "APERTURE_SIZE_DEFAULT" - register "PcdGttSize" = "GTT_SIZE_DEFAULT" - register "PcdLpssSioEnablePciMode" = "LPSS_PCI_MODE_DEFAULT" - register "AzaliaAutoEnable" = "AZALIA_FOLLOWS_DEVICETREE" - register "LpeAcpiModeEnable" = "LPE_ACPI_MODE_DISABLED" - - device cpu_cluster 0 on - device lapic 0 on end - end - - device domain 0 on - device pci 00.0 on end # 8086 0F00 - SoC router - device pci 02.0 on end # 8086 0F31 - GFX - device pci 03.0 off end # 8086 0F38 - MIPI - camera interface - - device pci 10.0 off end # 8086 0F14 - EMMC 4.1 Port (MMC1 pins) - (DO NOT USE) - Only 1 EMMC port at a time - device pci 11.0 on end # 8086 0F15 - SDIO Port (SD2 pins) - device pci 12.0 on end # 8086 0F16 - SD Port (SD3 pins) - device pci 13.0 on end # 8086 0F23 - SATA AHCI (0F20, 0F21, 0F22, 0F23) - device pci 14.0 on end # 8086 0F35 - USB XHCI - Only 1 USB controller at a time - device pci 15.0 off end # 8086 0F28 - LP Engine Audio - device pci 16.0 off end # 8086 0F37 - OTG controller - device pci 17.0 on end # 8086 0F50 - EMMC 4.5 Port (MMC1 pins) - Only 1 EMMC port at a time - device pci 18.0 on end # 8086 0F40 - SIO - DMA - device pci 18.1 on # 8086 0F41 - I2C Port 1 - # Enable external display bridge (eDP to LVDS) - chip drivers/i2c/ptn3460 - device i2c 0x20 on end # PTN3460 DP2LVDS Bridge - end - end - device pci 18.2 on end # 8086 0F42 - I2C Port 2 - device pci 18.3 on end # 8086 0F43 - I2C Port 3 - device pci 18.4 on end # 8086 0F44 - I2C Port 4 - device pci 18.5 on end # 8086 0F45 - I2C Port 5 - device pci 18.6 on end # 8086 0F46 - I2C Port 6 - device pci 18.7 on end # 8086 0F47 - I2C Port 7 - device pci 1a.0 on end # 8086 0F18 - Trusted Execution Engine - device pci 1b.0 on end # 8086 0F04 - HD Audio - device pci 1c.0 on # 8086 0F48 - PCIe Root Port 1 (x4 slot) - device pci 0.0 on end # 8086 1538 - Intel i210 MACPHY - end - device pci 1c.1 on end # 8086 0F4A - PCIe Root Port 2 (half mini pcie slot) - device pci 1c.2 on end # 8086 0F4C - PCIe Root Port 3 (front x1 slot) - device pci 1c.3 on end # 8086 0F4E - PCIe Root Port 4 (rear x1 slot) - device pci 1d.0 off end # 8086 0F34 - USB EHCI - Only 1 USB controller at a time - device pci 1e.0 on end # 8086 0F06 - SIO - DMA - device pci 1e.1 on end # 8086 0F08 - PWM 1 - device pci 1e.2 on end # 8086 0F09 - PWM 2 - device pci 1e.3 on end # 8086 0F0A - HSUART 1 - device pci 1e.4 on end # 8086 0F0C - HSUART 2 - device pci 1e.5 on end # 8086 0F0E - SPI - device pci 1f.0 on end # 8086 0F1C - LPC bridge - device pci 1f.3 on end # 8086 0F12 - SMBus 0 - end -end diff --git a/src/mainboard/siemens/mc_tcu3/dsdt.asl b/src/mainboard/siemens/mc_tcu3/dsdt.asl deleted file mode 100644 index bea6af7973..0000000000 --- a/src/mainboard/siemens/mc_tcu3/dsdt.asl +++ /dev/null @@ -1,54 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007-2009 coresystems GmbH - * Copyright (C) 2011 Google Inc. - * Copyright (C) 2014 Sage Electronic Engineering, LLC. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#define INCLUDE_LPE 1 -#define INCLUDE_SCC 1 -#define INCLUDE_EHCI 1 -#define INCLUDE_XHCI 1 -#define INCLUDE_LPSS 1 - - -#include -DefinitionBlock( - "dsdt.aml", - "DSDT", - 0x02, // DSDT revision: ACPI v2.0 and up - OEM_ID, - ACPI_TABLE_CREATOR, - 0x20110725 // OEM revision -) -{ - // Some generic macros - #include - - // global NVS and variables - #include - - #include - - Scope (\_SB) { - Device (PCI0) - { - #include - } - } - - /* Chipset specific sleep states */ - #include - - #include "acpi/mainboard.asl" -} diff --git a/src/mainboard/siemens/mc_tcu3/fadt.c b/src/mainboard/siemens/mc_tcu3/fadt.c deleted file mode 100644 index 8fee54b63e..0000000000 --- a/src/mainboard/siemens/mc_tcu3/fadt.c +++ /dev/null @@ -1,29 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007-2009 coresystems GmbH - * Copyright (C) 2013 Sage Electronic Engineering, LLC. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include - -void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt) -{ - acpi_header_t *header = &(fadt->header); - - acpi_fill_in_fadt(fadt,facs,dsdt); - - /* Platform specific customizations go here */ - - header->checksum = acpi_checksum((void *) fadt, sizeof(acpi_fadt_t)); -} diff --git a/src/mainboard/siemens/mc_tcu3/gpio.c b/src/mainboard/siemens/mc_tcu3/gpio.c deleted file mode 100644 index 23c6f963e4..0000000000 --- a/src/mainboard/siemens/mc_tcu3/gpio.c +++ /dev/null @@ -1,220 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2013 Google Inc. - * Copyright (C) 2014 Sage Electronic Engineering, LLC. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include "irqroute.h" - -/* NCORE GPIOs */ -static const struct soc_gpio_map gpncore_gpio_map[] = { - GPIO_FUNC2, /* GPIO 0 */ - GPIO_FUNC2, /* GPIO 1 */ - GPIO_FUNC2, /* GPIO 2 */ - GPIO_FUNC2, /* GPIO 3 */ - GPIO_FUNC2, /* GPIO 4 */ - GPIO_FUNC2, /* GPIO 5 */ - GPIO_FUNC2, /* GPIO 6 */ - GPIO_FUNC2, /* GPIO 7 */ - GPIO_FUNC2, /* GPIO 8 */ - GPIO_FUNC2, /* GPIO 9 */ - GPIO_FUNC2, /* GPIO 10 */ - GPIO_FUNC2, /* GPIO 11 */ - GPIO_FUNC2, /* GPIO 12 */ - GPIO_FUNC2, /* GPIO 13 */ - GPIO_FUNC2, /* GPIO 14 */ - GPIO_FUNC2, /* GPIO 15 */ - GPIO_FUNC2, /* GPIO 16 */ - GPIO_FUNC2, /* GPIO 17 */ - GPIO_FUNC2, /* GPIO 18 */ - GPIO_FUNC2, /* GPIO 19 */ - GPIO_FUNC2, /* GPIO 20 */ - GPIO_FUNC2, /* GPIO 21 */ - GPIO_FUNC2, /* GPIO 22 */ - GPIO_FUNC2, /* GPIO 23 */ - GPIO_FUNC2, /* GPIO 24 */ - GPIO_FUNC2, /* GPIO 25 */ - GPIO_FUNC2, /* GPIO 26 */ - GPIO_END -}; - -/* SCORE GPIOs (GPIO_S0_SC_XX)*/ -static const struct soc_gpio_map gpscore_gpio_map[] = { - GPIO_FUNC1, /* GPIO_S0_SC[000] SATA_GP[0] .*/ - GPIO_FUNC2, /* GPIO_S0_SC[001] SATA_GP[1] SATA_DEVSLP[0] .*/ - GPIO_FUNC1, /* GPIO_S0_SC[002] SATA_LED# */ - GPIO_FUNC1, /* GPIO_S0_SC[003] PCIE_CLKREQ[0]# */ - GPIO_FUNC1, /* GPIO_S0_SC[004] PCIE_CLKREQ[1]# */ - GPIO_FUNC1, /* GPIO_S0_SC[005] PCIE_CLKREQ[2]# */ - GPIO_FUNC1, /* GPIO_S0_SC[006] PCIE_CLKREQ[3]# */ - GPIO_NC, /* GPIO_S0_SC[007] RESERVED SD3_WP */ - GPIO_FUNC2, /* GPIO_S0_SC[008] I2S0_CLK HDA_RST# */ - GPIO_FUNC2, /* GPIO_S0_SC[009] I2S0_FRM HDA_SYNC */ - GPIO_FUNC2, /* GPIO_S0_SC[010] I2S0_DATAOUT HDA_CLK */ - GPIO_FUNC2, /* GPIO_S0_SC[011] I2S0_DATAIN HDA_SDO */ - GPIO_FUNC2, /* GPIO_S0_SC[012] I2S1_CLK HDA_SDI[0] */ - GPIO_NC, /* GPIO_S0_SC[013] I2S1_FRM HDA_SDI[1] */ - GPIO_DEFAULT, /* GPIO_S0_SC[014] I2S1_DATAOUT RESERVED */ - GPIO_DEFAULT, /* GPIO_S0_SC[015] I2S1_DATAIN RESERVED */ - GPIO_NC, /* GPIO_S0_SC[016] MMC1_CLK MMC1_45_CLK */ - GPIO_NC, /* GPIO_S0_SC[017] MMC1_D[0] MMC1_45_D[0] */ - GPIO_NC, /* GPIO_S0_SC[018] MMC1_D[1] MMC1_45_D[1] */ - GPIO_NC, /* GPIO_S0_SC[019] MMC1_D[2] MMC1_45_D[2] */ - GPIO_NC, /* GPIO_S0_SC[020] MMC1_D[3] MMC1_45_D[3] */ - GPIO_NC, /* GPIO_S0_SC[021] MMC1_D[4] MMC1_45_D[4] */ - GPIO_NC, /* GPIO_S0_SC[022] MMC1_D[5] MMC1_45_D[5] */ - GPIO_NC, /* GPIO_S0_SC[023] MMC1_D[6] MMC1_45_D[6] */ - GPIO_NC, /* GPIO_S0_SC[024] MMC1_D[7] MMC1_45_D[7] */ - GPIO_NC, /* GPIO_S0_SC[025] MMC1_CMD MMC1_45_CMD */ - GPIO_NC, /* GPIO_S0_SC[026] MMC1_RST# SATA_DEVSLP[0] MMC1_45_RST# */ - GPIO_FUNC1, /* GPIO_S0_SC[027] SD2_CLK */ - GPIO_FUNC1, /* GPIO_S0_SC[028] SD2_D[0] */ - GPIO_FUNC1, /* GPIO_S0_SC[029] SD2_D[1] */ - GPIO_FUNC1, /* GPIO_S0_SC[030] SD2_D[2] */ - GPIO_FUNC1, /* GPIO_S0_SC[031] SD2_D[3]_CD# */ - GPIO_FUNC1, /* GPIO_S0_SC[032] SD2_CMD */ - GPIO_NC, /* GPIO_S0_SC[033] SD3_CLK */ - GPIO_NC, /* GPIO_S0_SC[034] SD3_D[0] */ - GPIO_NC, /* GPIO_S0_SC[035] SD3_D[1] */ - GPIO_NC, /* GPIO_S0_SC[036] SD3_D[2] */ - GPIO_NC, /* GPIO_S0_SC[037] SD3_D[3] */ - GPIO_NC, /* GPIO_S0_SC[038] SD3_CD# */ - GPIO_NC, /* GPIO_S0_SC[039] SD3_CMD */ - GPIO_NC, /* GPIO_S0_SC[040] SD3_1P8EN */ - GPIO_NC, /* GPIO_S0_SC[041] SD3_PWREN# */ - GPIO_FUNC1, /* GPIO_S0_SC[042] ILB_LPC_AD[0] */ - GPIO_FUNC1, /* GPIO_S0_SC[043] ILB_LPC_AD[1] */ - GPIO_FUNC1, /* GPIO_S0_SC[044] ILB_LPC_AD[2] */ - GPIO_FUNC1, /* GPIO_S0_SC[045] ILB_LPC_AD[3] */ - GPIO_FUNC1, /* GPIO_S0_SC[046] ILB_LPC_FRAME# */ - GPIO_FUNC1, /* GPIO_S0_SC[047] ILB_LPC_CLK[0] */ - GPIO_FUNC1, /* GPIO_S0_SC[048] ILB_LPC_CLK[1] */ - GPIO_FUNC1, /* GPIO_S0_SC[049] ILB_LPC_CLKRUN# */ - GPIO_FUNC1, /* GPIO_S0_SC[050] ILB_LPC_SERIRQ */ - GPIO_FUNC1, /* GPIO_S0_SC[051] PCU_SMB_DATA */ - GPIO_FUNC1, /* GPIO_S0_SC[052] PCU_SMB_CLK */ - GPIO_FUNC1, /* GPIO_S0_SC[053] PCU_SMB_ALERT# */ - GPIO_FUNC1, /* GPIO_S0_SC[054] ILB_8254_SPKR RESERVED */ - GPIO_OUT_HIGH, /* GPIO_S0_SC[055] RESERVED */ - GPIO_FUNC0, /* GPIO_S0_SC[056] RESERVED */ - GPIO_FUNC1, /* GPIO_S0_SC[057] PCU_UART_TXD */ - GPIO_OUT_LOW, /* GPIO_S0_SC[058] RESERVED */ - GPIO_OUT_LOW, /* GPIO_S0_SC[059] RESERVED */ - GPIO_OUT_LOW, /* GPIO_S0_SC[060] RESERVED */ - GPIO_FUNC1, /* GPIO_S0_SC[061] PCU_UART_RXD */ - GPIO_FUNC1, /* GPIO_S0_SC[062] LPE_I2S2_CLK SATA_DEVSLP[1] RESERVED */ - GPIO_FUNC1, /* GPIO_S0_SC[063] LPE_I2S2_FRM RESERVED */ - GPIO_FUNC1, /* GPIO_S0_SC[064] LPE_I2S2_DATAIN */ - GPIO_FUNC1, /* GPIO_S0_SC[065] LPE_I2S2_DATAOUT */ - GPIO_FUNC1, /* GPIO_S0_SC[066] SIO_SPI_CS# */ - GPIO_FUNC1, /* GPIO_S0_SC[067] SIO_SPI_MISO */ - GPIO_FUNC1, /* GPIO_S0_SC[068] SIO_SPI_MOSI */ - GPIO_FUNC1, /* GPIO_S0_SC[069] SIO_SPI_CLK */ - GPIO_FUNC1, /* GPIO_S0_SC[070] SIO_UART1_RXD RESERVED */ - GPIO_FUNC1, /* GPIO_S0_SC[071] SIO_UART1_TXD RESERVED */ - GPIO_FUNC1, /* GPIO_S0_SC[072] SIO_UART1_RTS# */ - GPIO_FUNC1, /* GPIO_S0_SC[073] SIO_UART1_CTS# */ - GPIO_FUNC1, /* GPIO_S0_SC[074] SIO_UART2_RXD */ - GPIO_OUT_LOW, /* GPIO_S0_SC[075] SIO_UART2_TXD */ - GPIO_FUNC1, /* GPIO_S0_SC[076] SIO_UART2_RTS# */ - GPIO_FUNC1, /* GPIO_S0_SC[077] SIO_UART2_CTS# */ - GPIO_FUNC1, /* GPIO_S0_SC[078] SIO_I2C0_DATA */ - GPIO_FUNC1, /* GPIO_S0_SC[079] SIO_I2C0_CLK */ - GPIO_FUNC1, /* GPIO_S0_SC[080] SIO_I2C1_DATA */ - GPIO_FUNC1, /* GPIO_S0_SC[081] SIO_I2C1_CLK RESERVED */ - GPIO_FUNC1, /* GPIO_S0_SC[082] SIO_I2C2_DATA */ - GPIO_FUNC1, /* GPIO_S0_SC[083] SIO_I2C2_CLK */ - GPIO_FUNC1, /* GPIO_S0_SC[084] SIO_I2C3_DATA */ - GPIO_FUNC1, /* GPIO_S0_SC[085] SIO_I2C3_CLK */ - GPIO_FUNC1, /* GPIO_S0_SC[086] SIO_I2C4_DATA */ - GPIO_FUNC1, /* GPIO_S0_SC[087] SIO_I2C4_CLK */ - GPIO_FUNC1, /* GPIO_S0_SC[088] SIO_I2C5_DATA */ - GPIO_FUNC1, /* GPIO_S0_SC[089] SIO_I2C5_CLK */ - GPIO_FUNC1, /* GPIO_S0_SC[090] SIO_I2C6_DATA ILB_NMI */ - GPIO_FUNC1, /* GPIO_S0_SC[091] SIO_I2C6_CLK SD3_WP */ - GPIO_FUNC1, /* RESERVED GPIO_S0_SC[092] */ - GPIO_FUNC1, /* RESERVED GPIO_S0_SC[093] */ - GPIO_FUNC1, /* GPIO_S0_SC[094] SIO_PWM[0] */ - GPIO_FUNC1, /* GPIO_S0_SC[095] SIO_PWM[1] */ - GPIO_FUNC1, /* GPIO_S0_SC[096] PMC_PLT_CLK[0] */ - GPIO_FUNC1, /* GPIO_S0_SC[097] PMC_PLT_CLK[1] */ - GPIO_FUNC1, /* GPIO_S0_SC[098] PMC_PLT_CLK[2] */ - GPIO_FUNC1, /* GPIO_S0_SC[099] PMC_PLT_CLK[3] */ - GPIO_FUNC1, /* GPIO_S0_SC[100] PMC_PLT_CLK[4] */ - GPIO_DEFAULT, /* GPIO_S0_SC[101] PMC_PLT_CLK[5] */ - GPIO_END -}; - -/* SSUS GPIOs (GPIO_S5) */ -static const struct soc_gpio_map gpssus_gpio_map[] = { - GPIO_INPUT_PD_10K, /* GPIO_S5[00] RESERVED */ - GPIO_INPUT_PD_10K, /* GPIO_S5[01] RESERVED RESERVED RESERVED PMC_WAKE_PCIE[1]# */ - GPIO_INPUT_PD_10K, /* GPIO_S5[02] RESERVED RESERVED RESERVED PMC_WAKE_PCIE[2]# */ - GPIO_INPUT_PD_10K, /* GPIO_S5[03] RESERVED RESERVED RESERVED PMC_WAKE_PCIE[3]# */ - GPIO_INPUT_PD_10K, /* GPIO_S5[04] RESERVED RESERVED RESERVED RESERVED */ - GPIO_INPUT_PD_10K, /* GPIO_S5[05] PMC_SUSCLK[1] RESERVED RESERVED RESERVED */ - GPIO_INPUT_PD_10K, /* GPIO_S5[06] PMC_SUSCLK[2] RESERVED RESERVED RESERVED */ - GPIO_INPUT_PD_10K, /* GPIO_S5[07] PMC_SUSCLK[3] RESERVED RESERVED RESERVED */ - GPIO_INPUT_PU_10K, /* GPIO_S5[08] RESERVED RESERVED RESERVED RESERVED */ - GPIO_INPUT_PU_10K, /* GPIO_S5[09] RESERVED RESERVED ESERVED RESERVED */ - GPIO_OUT_HIGH, /* GPIO_S5[10] RESERVED RESERVED RESERVED */ - GPIO_DEFAULT, /* PMC_SUSPWRDNACK GPIO_S5[11] - - */ - GPIO_DEFAULT, /* PMC_SUSCLK[0] GPIO_S5[12] - - */ - GPIO_DEFAULT, /* RESERVED GPIO_S5[13] - - */ - GPIO_DEFAULT, /* RESERVED GPIO_S5[14] USB_ULPI_RST# - */ - GPIO_DEFAULT, /* PMC_WAKE_PCIE[0]# GPIO_S5[15] - - */ - GPIO_DEFAULT, /* PMC_PWRBTN# GPIO_S5[16] - - */ - GPIO_DEFAULT, /* RESERVED GPIO_S5[17] - - */ - GPIO_DEFAULT, /* PMC_SUS_STAT# GPIO_S5[18] - - */ - GPIO_DEFAULT, /* USB_OC[0]# GPIO_S5[19] - - */ - GPIO_DEFAULT, /* USB_OC[1]# GPIO_S5[20] - - */ - GPIO_DEFAULT, /* PCU_SPI_CS[1]# GPIO_S5[21] - */ - GPIO_DEFAULT, /* GPIO_S5[22] RESERVED RESERVED RESERVED RESERVED */ - GPIO_DEFAULT, /* GPIO_S5[23] RESERVED RESERVED RESERVED RESERVED */ - GPIO_DEFAULT, /* GPIO_S5[24] RESERVED RESERVED RESERVED RESERVED */ - GPIO_DEFAULT, /* GPIO_S5[25] RESERVED RESERVED RESERVED RESERVED */ - GPIO_DEFAULT, /* GPIO_S5[26] RESERVED RESERVED RESERVED RESERVED */ - GPIO_DEFAULT, /* GPIO_S5[27] RESERVED RESERVED ESERVED RESERVED */ - GPIO_DEFAULT, /* GPIO_S5[28] RESERVED RESERVED RESERVED RESERVED */ - GPIO_DEFAULT, /* GPIO_S5[29] RESERVED RESERVED RESERVED RESERVED */ - GPIO_DEFAULT, /* GPIO_S5[30] RESERVED RESERVED RESERVED RESERVED */ - GPIO_OUT_LOW, /* GPIO_S5[31] USB_ULPI_CLK RESERVED RESERVED */ - GPIO_INPUT_PD_10K, /* GPIO_S5[32] USB_ULPI_DATA[0] RESERVED RESERVED */ - GPIO_INPUT_PD_10K, /* GPIO_S5[33] USB_ULPI_DATA[1] RESERVED RESERVED */ - GPIO_INPUT_PD_10K, /* GPIO_S5[34] USB_ULPI_DATA[2] RESERVED RESERVED */ - GPIO_INPUT_PD_10K, /* GPIO_S5[35] USB_ULPI_DATA[3] RESERVED RESERVED */ - GPIO_INPUT_PD_10K, /* GPIO_S5[36] USB_ULPI_DATA[4] RESERVED RESERVED */ - GPIO_INPUT_PD_10K, /* GPIO_S5[37] USB_ULPI_DATA[5] RESERVED RESERVED */ - GPIO_INPUT_PD_10K, /* GPIO_S5[38] USB_ULPI_DATA[6] RESERVED RESERVED */ - GPIO_INPUT_PD_10K, /* GPIO_S5[39] USB_ULPI_DATA[7] RESERVED RESERVED */ - GPIO_INPUT_PD_20K, /* GPIO_S5[40] USB_ULPI_DIR RESERVED RESERVED */ - GPIO_INPUT_PD_20K, /* GPIO_S5[41] USB_ULPI_NXT RESERVED RESERVED */ - GPIO_INPUT_PD_20K, /* GPIO_S5[42] USB_ULPI_STP RESERVED RESERVED */ - GPIO_INPUT_PD_20K, /* GPIO_S5[43] USB_ULPI_REFCLK RESERVED RESERVED */ - GPIO_END -}; - -static struct soc_gpio_config gpio_config = { - .ncore = gpncore_gpio_map, - .score = gpscore_gpio_map, - .ssus = gpssus_gpio_map, - .core_dirq = NULL, - .sus_dirq = NULL, -}; - -struct soc_gpio_config* mainboard_get_gpios(void) -{ - return &gpio_config; -} diff --git a/src/mainboard/siemens/mc_tcu3/irqroute.c b/src/mainboard/siemens/mc_tcu3/irqroute.c deleted file mode 100644 index db8c512a43..0000000000 --- a/src/mainboard/siemens/mc_tcu3/irqroute.c +++ /dev/null @@ -1,18 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2013 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include "irqroute.h" - -DEFINE_IRQ_ROUTES; diff --git a/src/mainboard/siemens/mc_tcu3/irqroute.h b/src/mainboard/siemens/mc_tcu3/irqroute.h deleted file mode 100644 index 41b990bd85..0000000000 --- a/src/mainboard/siemens/mc_tcu3/irqroute.h +++ /dev/null @@ -1,82 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2013 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef IRQROUTE_H -#define IRQROUTE_H - -#include -#include - -/* - *IR02h GFX INT(A) - PIRQ A - *IR10h EMMC INT(ABCD) - PIRQ DEFG - *IR11h SDIO INT(A) - PIRQ B - *IR12h SD INT(A) - PIRQ C - *IR13h SATA INT(A) - PIRQ D - *IR14h XHCI INT(A) - PIRQ E - *IR15h LP Audio INT(A) - PIRQ F - *IR17h MMC INT(A) - PIRQ F - *IR18h SIO INT(ABCD) - PIRQ BADC - *IR1Ah TXE INT(A) - PIRQ F - *IR1Bh HD Audio INT(A) - PIRQ G - *IR1Ch PCIe INT(ABCD) - PIRQ EFGH - *IR1Dh EHCI INT(A) - PIRQ D - *IR1Eh SIO INT(ABCD) - PIRQ BDEF - *IR1Fh LPC INT(ABCD) - PIRQ HGBC - */ - -/* PCIe bridge routing */ -#define BRIDGE1_DEV PCIE_DEV - -/* PCI bridge IRQs need to be updated in both tables and need to match */ -#define PCIE_BRIDGE_IRQ_ROUTES \ - PCIE_BRIDGE_DEV(RP, BRIDGE1_DEV, E, F, G, H) - -/* Devices set as A, A, A, A evaluate as 0, and don't get set */ -#define PCI_DEV_PIRQ_ROUTES \ - PCI_DEV_PIRQ_ROUTE(GFX_DEV, A, A, A, B), \ - PCI_DEV_PIRQ_ROUTE(EMMC_DEV, D, E, F, G), \ - PCI_DEV_PIRQ_ROUTE(SDIO_DEV, B, A, A, A), \ - PCI_DEV_PIRQ_ROUTE(SD_DEV, C, A, A, A), \ - PCI_DEV_PIRQ_ROUTE(SATA_DEV, D, A, A, A), \ - PCI_DEV_PIRQ_ROUTE(XHCI_DEV, E, A, A, A), \ - PCI_DEV_PIRQ_ROUTE(LPE_DEV, F, A, A, A), \ - PCI_DEV_PIRQ_ROUTE(MMC45_DEV, F, A, A, A), \ - PCI_DEV_PIRQ_ROUTE(SIO1_DEV, B, A, D, C), \ - PCI_DEV_PIRQ_ROUTE(TXE_DEV, F, A, A, A), \ - PCI_DEV_PIRQ_ROUTE(HDA_DEV, G, A, A, A), \ - PCI_DEV_PIRQ_ROUTE(BRIDGE1_DEV, E, F, G, H), \ - PCI_DEV_PIRQ_ROUTE(EHCI_DEV, D, A, A, A), \ - PCI_DEV_PIRQ_ROUTE(SIO2_DEV, B, D, E, F), \ - PCI_DEV_PIRQ_ROUTE(PCU_DEV, H, G, B, C) - -/* - * Route each PIRQ[A-H] to a PIC IRQ[0-15] - * Reserved: 0, 1, 2, 8, 13 - * PS2 keyboard: 12 - * ACPI/SCI: 9 - * Floppy: 6 - */ -#define PIRQ_PIC_ROUTES \ - PIRQ_PIC(A, 4), \ - PIRQ_PIC(B, 5), \ - PIRQ_PIC(C, 7), \ - PIRQ_PIC(D, 10), \ - PIRQ_PIC(E, 11), \ - PIRQ_PIC(F, 12), \ - PIRQ_PIC(G, 14), \ - PIRQ_PIC(H, 15) - -#endif /* IRQROUTE_H */ diff --git a/src/mainboard/siemens/mc_tcu3/lcd_panel.c b/src/mainboard/siemens/mc_tcu3/lcd_panel.c deleted file mode 100644 index c4660ee8cc..0000000000 --- a/src/mainboard/siemens/mc_tcu3/lcd_panel.c +++ /dev/null @@ -1,173 +0,0 @@ -/* -* This file is part of the coreboot project. - * - * Copyright (C) 2014-2019 Siemens AG - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include -#include -#include -#include - -#include "soc/gpio.h" -#include "lcd_panel.h" - -# define MAX_HWI_NAME_LENGTH 20 - -/** \brief Reads GPIOs used for LCD panel encoding and returns the 4 bit value - * @param no parameters - * @return LCD panel type encoded in 4 bits - */ -static u8 get_lcd_panel_type(void) -{ - u8 lcd_type_gpio; - - lcd_type_gpio = ((read_ssus_gpio(LCD_TYPE_GPIO_BIT3) << 3) | - (read_ssus_gpio(LCD_TYPE_GPIO_BIT2) << 2) | - (read_ssus_gpio(LCD_TYPE_GPIO_BIT1) << 1) | - (read_ssus_gpio(LCD_TYPE_GPIO_BIT0))); - /* There is an inverter in this signals so we need to invert them as well */ - return ((~lcd_type_gpio) & 0x0f); -} -/** \brief This function checks which LCD panel type is used with the mainboard - * and provides the name of the matching EDID data set in CBFS. - * @param Pointer to the filename in CBFS where the EDID data is located - * @return CB_SUCCESS on success otherwise CB_ERR - */ -static enum cb_err get_hwi_filename(char *hwi_block) -{ - u8 lcd_type; - enum cb_err ret = CB_SUCCESS; - - lcd_type = get_lcd_panel_type(); - printk(BIOS_INFO, "LCD: Found panel type %d\n", lcd_type); - - switch (lcd_type) { - case LCD_PANEL_TYPE_10_INCH: - strcpy(hwi_block, "hwinfo10.hex"); - break; - case LCD_PANEL_TYPE_12_INCH: - strcpy(hwi_block, "hwinfo12.hex"); - break; - case LCD_PANEL_TYPE_15_INCH: - strcpy(hwi_block, "hwinfo15.hex"); - break; - case LCD_PANEL_TYPE_19_INCH: - strcpy(hwi_block, "hwinfo19.hex"); - break; - case LCD_PANEL_TYPE_EDID: - strcpy(hwi_block, "hwinfo.hex"); - break; - default: - printk(BIOS_ERR, "LCD: No supported panel found.\n"); - ret = CB_ERR; - break; - } - return ret; -} - -/** \brief This function provides EDID data to the driver for DP2LVDS Bridge (PTN3460) - * @param edid_data pointer to EDID data in driver -*/ -enum cb_err mb_get_edid(uint8_t edid_data[0x80]) -{ - char hwi_block[MAX_HWI_NAME_LENGTH]; - - if (get_hwi_filename(hwi_block) != CB_SUCCESS) - return CB_ERR; - - if (hwilib_find_blocks(hwi_block) != CB_SUCCESS) { - printk(BIOS_ERR, "LCD: Info block \"%s\" not found!\n", hwi_block); - return CB_ERR; - } - - /* Get EDID data from hwinfo block */ - if (hwilib_get_field(Edid, edid_data, PTN_EDID_LEN) != PTN_EDID_LEN) { - printk(BIOS_ERR, "LCD: No EDID data available in %s\n", hwi_block); - return CB_ERR; - } - return CB_SUCCESS; -} - -/** \brief This function provides EDID block [0..6] to the driver for DP2LVDS Bridge (PTN3460) - * which has to be used. -*/ -uint8_t mb_select_edid_table(void) -{ - return 6; /* With this mainboard we use EDID block 6 for emulation in PTN3460. */ -} - -/** \brief Function to enable mainboard to adjust the config data of PTN3460. - * @param *cfg_ptr Pointer to the PTN config structure to modify. - * @return -1 on error; PTN_CFG_MODIFIED if data was modified and needs to be updated. -*/ -int mb_adjust_cfg(struct ptn_3460_config *cfg) -{ - char hwi_block[MAX_HWI_NAME_LENGTH]; - uint8_t disp_con = 0, color_depth = 0; - uint8_t hwid[4], tcu31_hwid[4] = {7, 9, 2, 0}; - - if (get_hwi_filename(hwi_block) != CB_SUCCESS) - return -1; - if (hwilib_find_blocks(hwi_block) != CB_SUCCESS) { - printk(BIOS_ERR, "LCD: Info block \"%s\" not found!\n", hwi_block); - return -1; - } - - if (hwilib_get_field(PF_DisplCon, &disp_con, sizeof(disp_con)) != sizeof(disp_con)) { - printk(BIOS_ERR, "LCD: Missing panel features from %s\n", hwi_block); - return -1; - } - if (hwilib_get_field(PF_Color_Depth, &color_depth, - sizeof(color_depth)) != sizeof(color_depth)) { - printk(BIOS_ERR, "LCD: Missing panel features from %s\n", hwi_block); - return -1; - } - /* Set up configuration data according to the hwinfo block we got. */ - cfg->dp_interface_ctrl = 0x00; - cfg->lvds_interface_ctrl1 = 0x00; - if (disp_con == PF_DISPLCON_LVDS_DUAL) { - /* Turn on dual LVDS lane and clock. */ - cfg->lvds_interface_ctrl1 |= 0x0b; - } - if (color_depth == PF_COLOR_DEPTH_6BIT) { - /* Use 18 bits per pixel. */ - cfg->lvds_interface_ctrl1 |= 0x20; - } - /* No clock spreading, 300 mV LVDS swing. */ - cfg->lvds_interface_ctrl2 = 0x03; - /* Swap LVDS even and odd lanes for HW-ID 7.9.2.0 only. */ - if (hwilib_get_field(HWID, hwid, sizeof(hwid)) == sizeof(hwid) && - !(memcmp(hwid, tcu31_hwid, sizeof(hwid)))) { - /* Swap LVDS even and odd lane. */ - cfg->lvds_interface_ctrl3 = 0x01; - } else { - /* no LVDS lane swap */ - cfg->lvds_interface_ctrl3 = 0x00; - } - /* Delay T2 (VDD to LVDS active) by 16 ms. */ - cfg->t2_delay = 1; - /* 500 ms from LVDS to backlight active. */ - cfg->t3_timing = 10; - /* 1 second re-power delay. */ - cfg->t12_timing = 20; - /* 150 ms backlight off to LVDS inactive. */ - cfg->t4_timing = 3; - /* Delay T5 (LVDS to VDD inactive) by 16 ms. */ - cfg->t5_delay = 1; - /* Enable backlight control. */ - cfg->backlight_ctrl = 0; - - return PTN_CFG_MODIFIED; -} diff --git a/src/mainboard/siemens/mc_tcu3/lcd_panel.h b/src/mainboard/siemens/mc_tcu3/lcd_panel.h deleted file mode 100644 index e119d7aaef..0000000000 --- a/src/mainboard/siemens/mc_tcu3/lcd_panel.h +++ /dev/null @@ -1,31 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2014-2019 Siemens AG - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef _LCD_PANEL_H_ -#define _LCD_PANEL_H_ - -/* This GPIOs are used for LCD panel type encoding */ -#define LCD_TYPE_GPIO_BIT0 40 -#define LCD_TYPE_GPIO_BIT1 41 -#define LCD_TYPE_GPIO_BIT2 42 -#define LCD_TYPE_GPIO_BIT3 43 - -#define LCD_PANEL_TYPE_10_INCH 4 -#define LCD_PANEL_TYPE_12_INCH 7 -#define LCD_PANEL_TYPE_15_INCH 6 -#define LCD_PANEL_TYPE_19_INCH 1 -#define LCD_PANEL_TYPE_EDID 15 - -#endif /* _LCD_PANEL_H_ */ diff --git a/src/mainboard/siemens/mc_tcu3/mainboard.c b/src/mainboard/siemens/mc_tcu3/mainboard.c deleted file mode 100644 index 7950572e99..0000000000 --- a/src/mainboard/siemens/mc_tcu3/mainboard.c +++ /dev/null @@ -1,79 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007-2009 coresystems GmbH - * Copyright (C) 2011 The ChromiumOS Authors. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include -#include -#if CONFIG(VGA_ROM_RUN) -#include -#endif -#include -#include - -/** \brief This function will search for a MAC address which can be assigned - * to a MACPHY. - * @param dev pointer to PCI device - * @param mac buffer where to store the MAC address - * @return cb_err CB_ERR or CB_SUCCESS - */ -enum cb_err mainboard_get_mac_address(struct device *dev, uint8_t mac[6]) -{ - uint8_t mac_adr[6]; - uint32_t i; - - /* Open main hwinfo block */ - if (hwilib_find_blocks("hwinfo.hex") != CB_SUCCESS) - return CB_ERR; - /* Get first MAC address from hwinfo. */ - if (hwilib_get_field(Mac1, mac_adr, sizeof(mac_adr)) != sizeof(mac_adr)) - return CB_ERR; - /* Ensure the first MAC-Address is not completely 0x00 or 0xff */ - for (i = 0; i < 6; i++) { - if (mac_adr[i] != 0xFF) - break; - } - if (i == 6){ - return CB_ERR; - } - for (i = 0; i < 6; i++) { - if (mac_adr[i] != 0x00) - break; - } - if (i == 6){ - return CB_ERR; - } else { - memcpy(mac, mac_adr, 6); - return CB_SUCCESS; - } -} - -/* - * mainboard_enable is executed as first thing after enumerate_buses(). - * This is the earliest point to add customization. - */ -static void mainboard_enable(struct device *dev) -{ -} - -static void mainboard_final(void *chip_info) -{ -} - -struct chip_operations mainboard_ops = { - .enable_dev = mainboard_enable, - .final = mainboard_final, -}; diff --git a/src/mainboard/siemens/mc_tcu3/romstage.c b/src/mainboard/siemens/mc_tcu3/romstage.c deleted file mode 100644 index 41d0d046f4..0000000000 --- a/src/mainboard/siemens/mc_tcu3/romstage.c +++ /dev/null @@ -1,202 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2013 Google Inc. - * Copyright (C) 2013 Sage Electronic Engineering, LLC. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -/** - * /brief mainboard call for setup that needs to be done before fsp init - * - */ -void early_mainboard_romstage_entry() -{ - -} - -/** - * Get function disables - most of these will be done automatically - * @param fd_mask - * @param fd2_mask - */ -void get_func_disables(uint32_t *fd_mask, uint32_t *fd2_mask) -{ - -} - -/** - * /brief mainboard call for setup that needs to be done after fsp init - * - */ -void late_mainboard_romstage_entry() -{ - -} - -const uint32_t mAzaliaVerbTableData13[] = { -/* - *ALC262 Verb Table - 10EC0262 - */ - /* Pin Complex (NID 0x11) */ - 0x01171CF0, - 0x01171D11, - 0x01171E11, - 0x01171F41, - /* Pin Complex (NID 0x12) */ - 0x01271CF0, - 0x01271D11, - 0x01271E11, - 0x01271F41, - /* Pin Complex (NID 0x14) */ - 0x01471C10, - 0x01471D40, - 0x01471E01, - 0x01471F01, - /* Pin Complex (NID 0x15) */ - 0x01571CF0, - 0x01571D11, - 0x01571E11, - 0x01571F41, - /* Pin Complex (NID 0x16) */ - 0x01671CF0, - 0x01671D11, - 0x01671E11, - 0x01671F41, - /* Pin Complex (NID 0x18) */ - 0x01871C20, - 0x01871D98, - 0x01871EA1, - 0x01871F01, - /* Pin Complex (NID 0x19) */ - 0x01971C21, - 0x01971D98, - 0x01971EA1, - 0x01971F02, - /* Pin Complex (NID 0x1A) */ - 0x01A71C2F, - 0x01A71D30, - 0x01A71E81, - 0x01A71F01, - /* Pin Complex (NID 0x1B) */ - 0x01B71C1F, - 0x01B71D40, - 0x01B71E21, - 0x01B71F02, - /* Pin Complex (NID 0x1C) */ - 0x01C71CF0, - 0x01C71D11, - 0x01C71E11, - 0x01C71F41, - /* Pin Complex (NID 0x1D) */ - 0x01D71C01, - 0x01D71DC6, - 0x01D71E14, - 0x01D71F40, - /* Pin Complex (NID 0x1E) */ - 0x01E71CF0, - 0x01E71D11, - 0x01E71E11, - 0x01E71F41, - /* Pin Complex (NID 0x1F) */ - 0x01F71CF0, - 0x01F71D11, - 0x01F71E11, - 0x01F71F41 }; - -const PCH_AZALIA_VERB_TABLE mAzaliaVerbTable[] = { { -/* - * VerbTable: (RealTek ALC262) - * Revision ID = 0xFF, support all steps - * Codec Verb Table For AZALIA - * Codec Address: CAd value (0/1/2) - * Codec Vendor: 0x10EC0262 - */ - { - 0x10EC0262, /* Vendor ID/Device IDA */ - 0x0000, /* SubSystem ID */ - 0xFF, /* Revision IDA */ - 0x01, /* Front panel support (1 = yes, 2 = no) */ - 0x000B, /* Number of Rear Jacks = 11 */ - 0x0002 /* Number of Front Jacks = 2 */ - }, - (uint32_t *)mAzaliaVerbTableData13 } }; - -const PCH_AZALIA_CONFIG mainboard_AzaliaConfig = { - .Pme = 1, - .DS = 1, - .DA = 0, - .HdmiCodec = 1, - .AzaliaVCi = 1, - .Rsvdbits = 0, - .AzaliaVerbTableNum = 1, - .AzaliaVerbTable = (PCH_AZALIA_VERB_TABLE *)mAzaliaVerbTable, - .ResetWaitTimer = 300 }; - -/** /brief customize fsp parameters here if needed - */ -void romstage_fsp_rt_buffer_callback(FSP_INIT_RT_BUFFER *FspRtBuffer) -{ - uint8_t spd[0x80]; - UPD_DATA_REGION *UpdData = FspRtBuffer->Common.UpdDataRgnPtr; - - /* Initialize the Azalia Verb Tables to mainboard specific version. */ - UpdData->AzaliaConfigPtr = (UINT32)&mainboard_AzaliaConfig; - - /* Get SPD data from hwinfo block and set up memory down */ - /* parameters for FSP accordingly. */ - if (hwilib_find_blocks("hwinfo.hex")) { - printk(BIOS_ERR, - "HWInfo not found, use default timings for DDR3.\n"); - return; - } - - if (hwilib_get_field(SPD, spd, sizeof(spd)) != sizeof(spd)) { - printk(BIOS_ERR, - "SPD not found in HWInfo, use defaults for DDR3.\n"); - return; - } - /*Set up DDR timings from HWInfo. */ - UpdData->PcdMemoryParameters.EnableMemoryDown = 1; - UpdData->PcdMemoryParameters.DRAMType = spd[2]; - UpdData->PcdMemoryParameters.DIMM0Enable = spd[3] & 0x01; - UpdData->PcdMemoryParameters.DIMM1Enable = (spd[3] >> 1) & 0x01; - UpdData->PcdMemoryParameters.DIMMDensity = spd[4]; - UpdData->PcdMemoryParameters.DIMMDWidth = spd[5]; - UpdData->PcdMemoryParameters.DIMMSides = spd[7]; - UpdData->PcdMemoryParameters.DIMMBusWidth = spd[8]; - UpdData->PcdMemoryParameters.DRAMSpeed = spd[12]; - UpdData->PcdMemoryParameters.DIMMtCL = spd[14]; - UpdData->PcdMemoryParameters.DIMMtWR = spd[17]; - UpdData->PcdMemoryParameters.DIMMtRPtRCD = spd[18]; - UpdData->PcdMemoryParameters.DIMMtRRD = spd[19]; - UpdData->PcdMemoryParameters.DIMMtWTR = spd[26]; - UpdData->PcdMemoryParameters.DIMMtRTP = spd[27]; - UpdData->PcdMemoryParameters.DIMMtFAW = spd[28]; - - /*If one need output from MRC to be used in Intel RMT, simply */ - /*enable the following line */ - //UpdData->PcdMrcDebugMsg = 1; -} diff --git a/src/mainboard/siemens/mc_tcu3/thermal.h b/src/mainboard/siemens/mc_tcu3/thermal.h deleted file mode 100644 index 3973ca8fe9..0000000000 --- a/src/mainboard/siemens/mc_tcu3/thermal.h +++ /dev/null @@ -1,29 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 The Chromium OS Authors. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef MAINBOARD_THERMAL_H -#define MAINBOARD_THERMAL_H - - -/* Temperature which OS will shutdown at */ -#define CRITICAL_TEMPERATURE 100 - -/* Temperature which OS will throttle CPU */ -#define PASSIVE_TEMPERATURE 90 - -/* Tj_max value for calculating PECI CPU temperature */ -#define MAX_TEMPERATURE 100 - -#endif /* MAINBOARD_THERMAL_H */ From d9802111122d6273c711eccd352d29d7f34ba4e2 Mon Sep 17 00:00:00 2001 From: Arthur Heymans Date: Tue, 19 Nov 2019 18:46:44 +0100 Subject: [PATCH 0307/1242] soc/intel/fsp_baytrail: Drop support MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Relocatable ramstage, postcar stage and C_ENVIRONMENT_BOOTBLOCK are now mandatory features, which this platform lacks. Change-Id: I0b0344f1ebed12207a77c985f27893a1353c0925 Signed-off-by: Arthur Heymans Reviewed-on: https://review.coreboot.org/c/coreboot/+/36982 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki Reviewed-by: Angel Pons Reviewed-by: HAOUAS Elyes Reviewed-by: David Hendricks --- src/include/reg_script.h | 5 +- src/lib/reg_script.c | 3 +- src/soc/intel/fsp_baytrail/Kconfig | 117 --- src/soc/intel/fsp_baytrail/Makefile.inc | 70 -- src/soc/intel/fsp_baytrail/acpi.c | 577 -------------- .../intel/fsp_baytrail/acpi/device_nvs.asl | 82 -- src/soc/intel/fsp_baytrail/acpi/globalnvs.asl | 99 --- src/soc/intel/fsp_baytrail/acpi/gpio.asl | 105 --- src/soc/intel/fsp_baytrail/acpi/irq_helper.h | 124 --- src/soc/intel/fsp_baytrail/acpi/irqlinks.asl | 487 ------------ src/soc/intel/fsp_baytrail/acpi/irqroute.asl | 45 -- src/soc/intel/fsp_baytrail/acpi/lpc.asl | 138 ---- src/soc/intel/fsp_baytrail/acpi/lpe.asl | 114 --- src/soc/intel/fsp_baytrail/acpi/lpss.asl | 707 ------------------ src/soc/intel/fsp_baytrail/acpi/platform.asl | 32 - src/soc/intel/fsp_baytrail/acpi/scc.asl | 182 ----- .../intel/fsp_baytrail/acpi/southcluster.asl | 294 -------- src/soc/intel/fsp_baytrail/acpi/usb.asl | 48 -- src/soc/intel/fsp_baytrail/acpi/xhci.asl | 31 - .../intel/fsp_baytrail/bootblock/bootblock.c | 126 ---- src/soc/intel/fsp_baytrail/chip.c | 78 -- src/soc/intel/fsp_baytrail/chip.h | 360 --------- src/soc/intel/fsp_baytrail/cpu.c | 185 ----- src/soc/intel/fsp_baytrail/fsp/Kconfig | 37 - src/soc/intel/fsp_baytrail/fsp/Makefile.inc | 17 - .../intel/fsp_baytrail/fsp/chipset_fsp_util.c | 329 -------- .../intel/fsp_baytrail/fsp/chipset_fsp_util.h | 55 -- src/soc/intel/fsp_baytrail/gfx.c | 115 --- src/soc/intel/fsp_baytrail/gpio.c | 372 --------- src/soc/intel/fsp_baytrail/i2c.c | 294 -------- src/soc/intel/fsp_baytrail/include/soc/acpi.h | 36 - .../intel/fsp_baytrail/include/soc/baytrail.h | 65 -- .../fsp_baytrail/include/soc/device_nvs.h | 61 -- src/soc/intel/fsp_baytrail/include/soc/ehci.h | 40 - src/soc/intel/fsp_baytrail/include/soc/gfx.h | 44 -- src/soc/intel/fsp_baytrail/include/soc/gpio.h | 442 ----------- src/soc/intel/fsp_baytrail/include/soc/i2c.h | 23 - .../intel/fsp_baytrail/include/soc/iomap.h | 89 --- src/soc/intel/fsp_baytrail/include/soc/iosf.h | 346 --------- src/soc/intel/fsp_baytrail/include/soc/irq.h | 164 ---- src/soc/intel/fsp_baytrail/include/soc/lpc.h | 109 --- src/soc/intel/fsp_baytrail/include/soc/msr.h | 34 - src/soc/intel/fsp_baytrail/include/soc/nvs.h | 72 -- .../intel/fsp_baytrail/include/soc/pattrs.h | 60 -- .../intel/fsp_baytrail/include/soc/pci_devs.h | 216 ------ src/soc/intel/fsp_baytrail/include/soc/pcie.h | 98 --- src/soc/intel/fsp_baytrail/include/soc/pmc.h | 292 -------- .../intel/fsp_baytrail/include/soc/ramstage.h | 30 - .../intel/fsp_baytrail/include/soc/romstage.h | 34 - src/soc/intel/fsp_baytrail/include/soc/smm.h | 21 - src/soc/intel/fsp_baytrail/include/soc/spi.h | 63 -- src/soc/intel/fsp_baytrail/include/soc/xhci.h | 52 -- src/soc/intel/fsp_baytrail/iosf.c | 274 ------- src/soc/intel/fsp_baytrail/lpe.c | 186 ----- src/soc/intel/fsp_baytrail/lpss.c | 152 ---- src/soc/intel/fsp_baytrail/memmap.c | 52 -- src/soc/intel/fsp_baytrail/northcluster.c | 200 ----- src/soc/intel/fsp_baytrail/placeholders.c | 23 - src/soc/intel/fsp_baytrail/pmutil.c | 383 ---------- src/soc/intel/fsp_baytrail/ramstage.c | 159 ---- .../intel/fsp_baytrail/romstage/Makefile.inc | 20 - src/soc/intel/fsp_baytrail/romstage/pmc.c | 35 - .../fsp_baytrail/romstage/report_platform.c | 84 --- .../intel/fsp_baytrail/romstage/romstage.c | 277 ------- src/soc/intel/fsp_baytrail/romstage/uart.c | 34 - src/soc/intel/fsp_baytrail/smihandler.c | 395 ---------- src/soc/intel/fsp_baytrail/smm.c | 141 ---- src/soc/intel/fsp_baytrail/southcluster.c | 616 --------------- src/soc/intel/fsp_baytrail/spi.c | 584 --------------- src/soc/intel/fsp_baytrail/tsc_freq.c | 72 -- src/vendorcode/intel/Kconfig | 4 - src/vendorcode/intel/Makefile.inc | 9 - .../fsp1_0/baytrail/absf/minnowmax_1gb.absf | 328 -------- .../fsp1_0/baytrail/absf/minnowmax_2gb.absf | 328 -------- .../intel/fsp1_0/baytrail/include/azalia.h | 66 -- .../intel/fsp1_0/baytrail/include/fsp.h | 69 -- .../intel/fsp1_0/baytrail/include/fspapi.h | 65 -- .../intel/fsp1_0/baytrail/include/fspffs.h | 506 ------------- .../intel/fsp1_0/baytrail/include/fspfv.h | 247 ------ .../intel/fsp1_0/baytrail/include/fsphob.h | 542 -------------- .../fsp1_0/baytrail/include/fspinfoheader.h | 62 -- .../fsp1_0/baytrail/include/fspplatform.h | 78 -- .../intel/fsp1_0/baytrail/include/fsptypes.h | 116 --- .../intel/fsp1_0/baytrail/include/fspvpd.h | 126 ---- .../intel/fsp1_0/baytrail/srx/board_fsp.c | 186 ----- .../intel/fsp1_0/baytrail/srx/fsphob.c | 198 ----- 86 files changed, 3 insertions(+), 14233 deletions(-) delete mode 100644 src/soc/intel/fsp_baytrail/Kconfig delete mode 100644 src/soc/intel/fsp_baytrail/Makefile.inc delete mode 100644 src/soc/intel/fsp_baytrail/acpi.c delete mode 100644 src/soc/intel/fsp_baytrail/acpi/device_nvs.asl delete mode 100644 src/soc/intel/fsp_baytrail/acpi/globalnvs.asl delete mode 100644 src/soc/intel/fsp_baytrail/acpi/gpio.asl delete mode 100644 src/soc/intel/fsp_baytrail/acpi/irq_helper.h delete mode 100644 src/soc/intel/fsp_baytrail/acpi/irqlinks.asl delete mode 100644 src/soc/intel/fsp_baytrail/acpi/irqroute.asl delete mode 100644 src/soc/intel/fsp_baytrail/acpi/lpc.asl delete mode 100644 src/soc/intel/fsp_baytrail/acpi/lpe.asl delete mode 100644 src/soc/intel/fsp_baytrail/acpi/lpss.asl delete mode 100644 src/soc/intel/fsp_baytrail/acpi/platform.asl delete mode 100644 src/soc/intel/fsp_baytrail/acpi/scc.asl delete mode 100644 src/soc/intel/fsp_baytrail/acpi/southcluster.asl delete mode 100644 src/soc/intel/fsp_baytrail/acpi/usb.asl delete mode 100644 src/soc/intel/fsp_baytrail/acpi/xhci.asl delete mode 100644 src/soc/intel/fsp_baytrail/bootblock/bootblock.c delete mode 100644 src/soc/intel/fsp_baytrail/chip.c delete mode 100644 src/soc/intel/fsp_baytrail/chip.h delete mode 100644 src/soc/intel/fsp_baytrail/cpu.c delete mode 100644 src/soc/intel/fsp_baytrail/fsp/Kconfig delete mode 100644 src/soc/intel/fsp_baytrail/fsp/Makefile.inc delete mode 100644 src/soc/intel/fsp_baytrail/fsp/chipset_fsp_util.c delete mode 100644 src/soc/intel/fsp_baytrail/fsp/chipset_fsp_util.h delete mode 100644 src/soc/intel/fsp_baytrail/gfx.c delete mode 100644 src/soc/intel/fsp_baytrail/gpio.c delete mode 100644 src/soc/intel/fsp_baytrail/i2c.c delete mode 100644 src/soc/intel/fsp_baytrail/include/soc/acpi.h delete mode 100644 src/soc/intel/fsp_baytrail/include/soc/baytrail.h delete mode 100644 src/soc/intel/fsp_baytrail/include/soc/device_nvs.h delete mode 100644 src/soc/intel/fsp_baytrail/include/soc/ehci.h delete mode 100644 src/soc/intel/fsp_baytrail/include/soc/gfx.h delete mode 100644 src/soc/intel/fsp_baytrail/include/soc/gpio.h delete mode 100644 src/soc/intel/fsp_baytrail/include/soc/i2c.h delete mode 100644 src/soc/intel/fsp_baytrail/include/soc/iomap.h delete mode 100644 src/soc/intel/fsp_baytrail/include/soc/iosf.h delete mode 100644 src/soc/intel/fsp_baytrail/include/soc/irq.h delete mode 100644 src/soc/intel/fsp_baytrail/include/soc/lpc.h delete mode 100644 src/soc/intel/fsp_baytrail/include/soc/msr.h delete mode 100644 src/soc/intel/fsp_baytrail/include/soc/nvs.h delete mode 100644 src/soc/intel/fsp_baytrail/include/soc/pattrs.h delete mode 100644 src/soc/intel/fsp_baytrail/include/soc/pci_devs.h delete mode 100644 src/soc/intel/fsp_baytrail/include/soc/pcie.h delete mode 100644 src/soc/intel/fsp_baytrail/include/soc/pmc.h delete mode 100644 src/soc/intel/fsp_baytrail/include/soc/ramstage.h delete mode 100644 src/soc/intel/fsp_baytrail/include/soc/romstage.h delete mode 100644 src/soc/intel/fsp_baytrail/include/soc/smm.h delete mode 100644 src/soc/intel/fsp_baytrail/include/soc/spi.h delete mode 100644 src/soc/intel/fsp_baytrail/include/soc/xhci.h delete mode 100644 src/soc/intel/fsp_baytrail/iosf.c delete mode 100644 src/soc/intel/fsp_baytrail/lpe.c delete mode 100644 src/soc/intel/fsp_baytrail/lpss.c delete mode 100644 src/soc/intel/fsp_baytrail/memmap.c delete mode 100644 src/soc/intel/fsp_baytrail/northcluster.c delete mode 100644 src/soc/intel/fsp_baytrail/placeholders.c delete mode 100644 src/soc/intel/fsp_baytrail/pmutil.c delete mode 100644 src/soc/intel/fsp_baytrail/ramstage.c delete mode 100644 src/soc/intel/fsp_baytrail/romstage/Makefile.inc delete mode 100644 src/soc/intel/fsp_baytrail/romstage/pmc.c delete mode 100644 src/soc/intel/fsp_baytrail/romstage/report_platform.c delete mode 100644 src/soc/intel/fsp_baytrail/romstage/romstage.c delete mode 100644 src/soc/intel/fsp_baytrail/romstage/uart.c delete mode 100644 src/soc/intel/fsp_baytrail/smihandler.c delete mode 100644 src/soc/intel/fsp_baytrail/smm.c delete mode 100644 src/soc/intel/fsp_baytrail/southcluster.c delete mode 100644 src/soc/intel/fsp_baytrail/spi.c delete mode 100644 src/soc/intel/fsp_baytrail/tsc_freq.c delete mode 100644 src/vendorcode/intel/fsp1_0/baytrail/absf/minnowmax_1gb.absf delete mode 100644 src/vendorcode/intel/fsp1_0/baytrail/absf/minnowmax_2gb.absf delete mode 100644 src/vendorcode/intel/fsp1_0/baytrail/include/azalia.h delete mode 100644 src/vendorcode/intel/fsp1_0/baytrail/include/fsp.h delete mode 100644 src/vendorcode/intel/fsp1_0/baytrail/include/fspapi.h delete mode 100644 src/vendorcode/intel/fsp1_0/baytrail/include/fspffs.h delete mode 100644 src/vendorcode/intel/fsp1_0/baytrail/include/fspfv.h delete mode 100644 src/vendorcode/intel/fsp1_0/baytrail/include/fsphob.h delete mode 100644 src/vendorcode/intel/fsp1_0/baytrail/include/fspinfoheader.h delete mode 100644 src/vendorcode/intel/fsp1_0/baytrail/include/fspplatform.h delete mode 100644 src/vendorcode/intel/fsp1_0/baytrail/include/fsptypes.h delete mode 100644 src/vendorcode/intel/fsp1_0/baytrail/include/fspvpd.h delete mode 100644 src/vendorcode/intel/fsp1_0/baytrail/srx/board_fsp.c delete mode 100644 src/vendorcode/intel/fsp1_0/baytrail/srx/fsphob.c diff --git a/src/include/reg_script.h b/src/include/reg_script.h index c6fdd523ee..1d0c0d68dc 100644 --- a/src/include/reg_script.h +++ b/src/include/reg_script.h @@ -369,8 +369,7 @@ struct reg_script_bus_entry { REG_RES_RXW32(bar_, reg_, 0xffffffff, value_) -#if CONFIG(SOC_INTEL_BAYTRAIL) || \ -CONFIG(SOC_INTEL_FSP_BAYTRAIL) +#if CONFIG(SOC_INTEL_BAYTRAIL) /* * IO Sideband Function */ @@ -394,7 +393,7 @@ CONFIG(SOC_INTEL_FSP_BAYTRAIL) REG_SCRIPT_IOSF(POLL, unit_, reg_, mask_, value_, timeout_) #define REG_IOSF_XOR(unit_, reg_, value_) \ REG_IOSF_RXW(unit_, reg_, 0xffffffff, value_) -#endif /* CONFIG_SOC_INTEL_BAYTRAIL || CONFIG_SOC_INTEL_FSP_BAYTRAIL*/ +#endif /* CONFIG_SOC_INTEL_BAYTRAIL */ /* * CPU Model Specific Register diff --git a/src/lib/reg_script.c b/src/lib/reg_script.c index 5f4fa9fa11..299fd75028 100644 --- a/src/lib/reg_script.c +++ b/src/lib/reg_script.c @@ -28,8 +28,7 @@ #include #endif -#define HAS_IOSF (CONFIG(SOC_INTEL_BAYTRAIL) || \ - CONFIG(SOC_INTEL_FSP_BAYTRAIL)) +#define HAS_IOSF (CONFIG(SOC_INTEL_BAYTRAIL)) #if HAS_IOSF #include /* TODO: wrap in -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include "chip.h" - -#define MWAIT_RES(state, sub_state) \ - { \ - .addrl = (((state) << 4) | (sub_state)), \ - .space_id = ACPI_ADDRESS_SPACE_FIXED, \ - .bit_width = ACPI_FFIXEDHW_VENDOR_INTEL, \ - .bit_offset = ACPI_FFIXEDHW_CLASS_MWAIT, \ - .access_size = ACPI_FFIXEDHW_FLAG_HW_COORD, \ - } - -/* C-state map without S0ix */ -static acpi_cstate_t cstate_map[] = { - { - /* C1 */ - .ctype = 1, /* ACPI C1 */ - .latency = 1, - .power = 1000, - .resource = MWAIT_RES(0, 0), - }, - { - /* C6NS with no L2 shrink */ - /* NOTE: this substate is above CPUID limit */ - .ctype = 2, /* ACPI C2 */ - .latency = 500, - .power = 10, - .resource = MWAIT_RES(5, 1), - }, - { - /* C6FS with full L2 shrink */ - .ctype = 3, /* ACPI C3 */ - .latency = 1500, /* 1.5ms worst case */ - .power = 10, - .resource = MWAIT_RES(5, 2), - } -}; - -void acpi_init_gnvs(global_nvs_t *gnvs) -{ - /* CPU core count */ - gnvs->pcnt = dev_count_cpu(); - - /* Top of Low Memory (start of resource allocation) */ - gnvs->tolm = nc_read_top_of_low_memory(); - -#if CONFIG(CONSOLE_CBMEM) - /* Update the mem console pointer. */ - gnvs->cbmc = (u32)cbmem_find(CBMEM_ID_CONSOLE); -#endif -} - -static int acpi_sci_irq(void) -{ - u32 *actl = (u32 *)(ILB_BASE_ADDRESS + ACTL); - int scis; - static int sci_irq; - - if (sci_irq) - return sci_irq; - - /* Determine how SCI is routed. */ - scis = read32(actl) & SCIS_MASK; - switch (scis) { - case SCIS_IRQ9: - case SCIS_IRQ10: - case SCIS_IRQ11: - sci_irq = scis - SCIS_IRQ9 + 9; - break; - case SCIS_IRQ20: - case SCIS_IRQ21: - case SCIS_IRQ22: - case SCIS_IRQ23: - sci_irq = scis - SCIS_IRQ20 + 20; - break; - default: - printk(BIOS_DEBUG, "Invalid SCI route! Defaulting to IRQ9.\n"); - sci_irq = 9; - break; - } - - printk(BIOS_DEBUG, "SCI is IRQ%d\n", sci_irq); - return sci_irq; -} - -unsigned long acpi_fill_mcfg(unsigned long current) -{ - current += acpi_create_mcfg_mmconfig((acpi_mcfg_mmconfig_t *)current, - MCFG_BASE_ADDRESS, 0, 0, 255); - return current; -} - -/** - * Fill in the fadt with generic values that can be overridden later. - */ - -typedef struct soc_intel_fsp_baytrail_config config_t; - -void acpi_fill_in_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt) -{ - acpi_header_t *header = &(fadt->header); - struct device *lpcdev = pcidev_path_on_root(PCH_DEVFN_LPC); - u16 pmbase = pci_read_config16(lpcdev, ABASE) & 0xfff0; - config_t *config = config_of(lpcdev); - - memset((void *) fadt, 0, sizeof(acpi_fadt_t)); - - /* - * Reference section 5.2.9 Fixed ACPI Description Table (FADT) - * in the ACPI 3.0b specification. - */ - - /* FADT Header Structure */ - memcpy(header->signature, "FACP", 4); - header->length = sizeof(acpi_fadt_t); - header->revision = get_acpi_table_revision(FADT); - memcpy(header->oem_id, OEM_ID, 6); - memcpy(header->oem_table_id, ACPI_TABLE_CREATOR, 8); - memcpy(header->asl_compiler_id, ASLC, 4); - header->asl_compiler_revision = asl_revision; - - /* ACPI Pointers */ - fadt->firmware_ctrl = (unsigned long) facs; - fadt->dsdt = (unsigned long) dsdt; - - fadt->reserved = 0; /* reserved, should be 0 ACPI 3.0 */ - fadt->preferred_pm_profile = config->fadt_pm_profile; /* unknown is default */ - - /* System Management */ - fadt->sci_int = acpi_sci_irq(); - - fadt->smi_cmd = APM_CNT; - fadt->acpi_enable = APM_CNT_ACPI_ENABLE; - fadt->acpi_disable = APM_CNT_ACPI_DISABLE; - - /* Power Control */ - fadt->s4bios_req = 0x00; - fadt->pstate_cnt = 0x00; - - /* Control Registers - Base Address */ - fadt->pm1a_evt_blk = pmbase + PM1_STS; - fadt->pm1b_evt_blk = 0x00; /* Not Used */ - fadt->pm1a_cnt_blk = pmbase + PM1_CNT; - fadt->pm1b_cnt_blk = 0x00; /* Not Used */ - fadt->pm2_cnt_blk = pmbase + PM2A_CNT_BLK; - fadt->pm_tmr_blk = pmbase + PM1_TMR; - fadt->gpe0_blk = pmbase + GPE0_STS; - fadt->gpe1_blk = 0x00; /* Not Used */ - - /* Control Registers - Length */ - fadt->pm1_evt_len = 4; /* 32 bits */ - fadt->pm1_cnt_len = 2; /* 32 bit register, 16 bits used */ - fadt->pm2_cnt_len = 1; /* 8 bits */ - fadt->pm_tmr_len = 4; /* 32 bits */ - fadt->gpe0_blk_len = 8; /* 64 bits */ - fadt->gpe1_blk_len = 0; - fadt->gpe1_base = 0; - fadt->cst_cnt = 0; - fadt->p_lvl2_lat = ACPI_FADT_C2_NOT_SUPPORTED; - fadt->p_lvl3_lat = ACPI_FADT_C3_NOT_SUPPORTED; - fadt->flush_size = 0; /* set to 0 if WBINVD is 1 in flags */ - fadt->flush_stride = 0; /* set to 0 if WBINVD is 1 in flags */ - fadt->duty_offset = 1; - fadt->duty_width = 0; - - /* RTC Registers */ - fadt->day_alrm = 0x0D; - fadt->mon_alrm = 0x00; - fadt->century = 0x00; - fadt->iapc_boot_arch = config->fadt_boot_arch; /* legacy free default */ - - fadt->flags = ACPI_FADT_WBINVD | ACPI_FADT_C1_SUPPORTED | - ACPI_FADT_C2_MP_SUPPORTED | ACPI_FADT_SLEEP_BUTTON | - ACPI_FADT_RESET_REGISTER | ACPI_FADT_SLEEP_TYPE | - ACPI_FADT_S4_RTC_WAKE | ACPI_FADT_PLATFORM_CLOCK; - - /* Reset Register */ - fadt->reset_reg.space_id = ACPI_ADDRESS_SPACE_IO; - fadt->reset_reg.bit_width = 8; - fadt->reset_reg.bit_offset = 0; - fadt->reset_reg.access_size = ACPI_ACCESS_SIZE_BYTE_ACCESS; - fadt->reset_reg.addrl = 0xCF9; - fadt->reset_reg.addrh = 0x00; - fadt->reset_value = 6; - - fadt->ARM_boot_arch = 0; /* MUST be 0 ACPI 3.0 */ - fadt->FADT_MinorVersion = 0; /* MUST be 0 ACPI 3.0 */ - - /* Extended ACPI Pointers */ - fadt->x_firmware_ctl_l = (unsigned long)facs; - fadt->x_firmware_ctl_h = 0x00; - fadt->x_dsdt_l = (unsigned long)dsdt; - fadt->x_dsdt_h = 0x00; - - /* PM1 Status & PM1 Enable */ - fadt->x_pm1a_evt_blk.space_id = ACPI_ADDRESS_SPACE_IO; - fadt->x_pm1a_evt_blk.bit_width = 32; - fadt->x_pm1a_evt_blk.bit_offset = 0; - fadt->x_pm1a_evt_blk.access_size = ACPI_ACCESS_SIZE_DWORD_ACCESS; - fadt->x_pm1a_evt_blk.addrl = fadt->pm1a_evt_blk; - fadt->x_pm1a_evt_blk.addrh = 0x00; - - fadt->x_pm1b_evt_blk.space_id = ACPI_ADDRESS_SPACE_IO; - fadt->x_pm1b_evt_blk.bit_width = 0; - fadt->x_pm1b_evt_blk.bit_offset = 0; - fadt->x_pm1b_evt_blk.access_size = 0; - fadt->x_pm1b_evt_blk.addrl = fadt->pm1b_evt_blk; - fadt->x_pm1b_evt_blk.addrh = 0x00; - - /* PM1 Control Registers */ - fadt->x_pm1a_cnt_blk.space_id = ACPI_ADDRESS_SPACE_IO; - fadt->x_pm1a_cnt_blk.bit_width = 16; - fadt->x_pm1a_cnt_blk.bit_offset = 0; - fadt->x_pm1a_cnt_blk.access_size = ACPI_ACCESS_SIZE_WORD_ACCESS; - fadt->x_pm1a_cnt_blk.addrl = fadt->pm1a_cnt_blk; - fadt->x_pm1a_cnt_blk.addrh = 0x00; - - fadt->x_pm1b_cnt_blk.space_id = ACPI_ADDRESS_SPACE_IO; - fadt->x_pm1b_cnt_blk.bit_width = 0; - fadt->x_pm1b_cnt_blk.bit_offset = 0; - fadt->x_pm1b_cnt_blk.access_size = 0; - fadt->x_pm1b_cnt_blk.addrl = fadt->pm1b_cnt_blk; - fadt->x_pm1b_cnt_blk.addrh = 0x00; - - /* PM2 Control Registers */ - fadt->x_pm2_cnt_blk.space_id = ACPI_ADDRESS_SPACE_IO; - fadt->x_pm2_cnt_blk.bit_width = 8; - fadt->x_pm2_cnt_blk.bit_offset = 0; - fadt->x_pm2_cnt_blk.access_size = ACPI_ACCESS_SIZE_BYTE_ACCESS; - fadt->x_pm2_cnt_blk.addrl = fadt->pm2_cnt_blk; - fadt->x_pm2_cnt_blk.addrh = 0x00; - - /* PM1 Timer Register */ - fadt->x_pm_tmr_blk.space_id = ACPI_ADDRESS_SPACE_IO; - fadt->x_pm_tmr_blk.bit_width = 32; - fadt->x_pm_tmr_blk.bit_offset = 0; - fadt->x_pm_tmr_blk.access_size = ACPI_ACCESS_SIZE_DWORD_ACCESS; - fadt->x_pm_tmr_blk.addrl = fadt->pm_tmr_blk; - fadt->x_pm_tmr_blk.addrh = 0x00; - - /* General-Purpose Event Registers */ - fadt->x_gpe0_blk.space_id = ACPI_ADDRESS_SPACE_IO; - fadt->x_gpe0_blk.bit_width = 64; /* EventStatus + EventEnable */ - fadt->x_gpe0_blk.bit_offset = 0; - fadt->x_gpe0_blk.access_size = ACPI_ACCESS_SIZE_DWORD_ACCESS; - fadt->x_gpe0_blk.addrl = fadt->gpe0_blk; - fadt->x_gpe0_blk.addrh = 0x00; - - fadt->x_gpe1_blk.space_id = ACPI_ADDRESS_SPACE_IO; - fadt->x_gpe1_blk.bit_width = 0; - fadt->x_gpe1_blk.bit_offset = 0; - fadt->x_gpe1_blk.access_size = 0; - fadt->x_gpe1_blk.addrl = fadt->gpe1_blk; - fadt->x_gpe1_blk.addrh = 0x00; - - header->checksum = - acpi_checksum((void *) fadt, sizeof(acpi_fadt_t)); -} -static acpi_tstate_t baytrail_tss_table[] = { - { 100, 1000, 0, 0x00, 0 }, - { 88, 875, 0, 0x1e, 0 }, - { 75, 750, 0, 0x1c, 0 }, - { 63, 625, 0, 0x1a, 0 }, - { 50, 500, 0, 0x18, 0 }, - { 38, 375, 0, 0x16, 0 }, - { 25, 250, 0, 0x14, 0 }, - { 13, 125, 0, 0x12, 0 }, -}; - -static void generate_T_state_entries(int core, int cores_per_package) -{ - /* Indicate SW_ALL coordination for T-states */ - acpigen_write_TSD_package(core, cores_per_package, SW_ALL); - - /* Indicate FFixedHW so OS will use MSR */ - acpigen_write_empty_PTC(); - - /* Set NVS controlled T-state limit */ - acpigen_write_TPC("\\TLVL"); - - /* Write TSS table for MSR access */ - acpigen_write_TSS_package( - ARRAY_SIZE(baytrail_tss_table), baytrail_tss_table); -} - -static int calculate_power(int tdp, int p1_ratio, int ratio) -{ - u32 m; - u32 power; - - /* - * M = ((1.1 - ((p1_ratio - ratio) * 0.00625)) / 1.1) ^ 2 - * - * Power = (ratio / p1_ratio) * m * tdp - */ - - m = (110000 - ((p1_ratio - ratio) * 625)) / 11; - m = (m * m) / 1000; - - power = ((ratio * 100000 / p1_ratio) / 100); - power *= (m / 100) * (tdp / 1000); - power /= 1000; - - return (int)power; -} - -static void generate_P_state_entries(int core, int cores_per_package) -{ - int ratio_min, ratio_max, ratio_turbo, ratio_step, ratio_range_2; - int coord_type, power_max, power_unit, num_entries; - int ratio, power, clock, clock_max; - int vid, vid_turbo, vid_min, vid_max, vid_range_2; - u32 control_status; - const struct pattrs *pattrs = pattrs_get(); - msr_t msr; - - /* Inputs from CPU attributes */ - ratio_max = pattrs->iacore_ratios[IACORE_MAX]; - ratio_min = pattrs->iacore_ratios[IACORE_LFM]; - vid_max = pattrs->iacore_vids[IACORE_MAX]; - vid_min = pattrs->iacore_vids[IACORE_LFM]; - - /* Hardware coordination of P-states */ - coord_type = HW_ALL; - - /* Max Non-Turbo Frequency */ - clock_max = (ratio_max * pattrs->bclk_khz) / 1000; - - /* Calculate CPU TDP in mW */ - msr = rdmsr(MSR_PKG_POWER_SKU_UNIT); - power_unit = 1 << (msr.lo & 0xf); - msr = rdmsr(MSR_PKG_POWER_LIMIT); - power_max = ((msr.lo & 0x7fff) / power_unit) * 1000; - - /* Write _PCT indicating use of FFixedHW */ - acpigen_write_empty_PCT(); - - /* Write _PPC with NVS specified limit on supported P-state */ - acpigen_write_PPC_NVS(); - - /* Write PSD indicating configured coordination type */ - acpigen_write_PSD_package(core, 1, coord_type); - - /* Add P-state entries in _PSS table */ - acpigen_write_name("_PSS"); - - /* Determine ratio points */ - ratio_step = 1; - num_entries = (ratio_max - ratio_min) / ratio_step; - while (num_entries > 15) { /* ACPI max is 15 ratios */ - ratio_step <<= 1; - num_entries >>= 1; - } - - /* P[T] is Turbo state if enabled */ - if (get_turbo_state() == TURBO_ENABLED) { - /* _PSS package count including Turbo */ - acpigen_write_package(num_entries + 2); - - ratio_turbo = pattrs->iacore_ratios[IACORE_TURBO]; - vid_turbo = pattrs->iacore_vids[IACORE_TURBO]; - control_status = (ratio_turbo << 8) | vid_turbo; - - /* Add entry for Turbo ratio */ - acpigen_write_PSS_package( - clock_max + 1, /*MHz*/ - power_max, /*mW*/ - 10, /*lat1*/ - 10, /*lat2*/ - control_status, /*control*/ - control_status); /*status*/ - } else { - /* _PSS package count without Turbo */ - acpigen_write_package(num_entries + 1); - ratio_turbo = ratio_max; - vid_turbo = vid_max; - } - - /* First regular entry is max non-turbo ratio */ - control_status = (ratio_max << 8) | vid_max; - acpigen_write_PSS_package( - clock_max, /*MHz*/ - power_max, /*mW*/ - 10, /*lat1*/ - 10, /*lat2*/ - control_status, /*control */ - control_status); /*status*/ - - /* Set up ratio and vid ranges for VID calculation */ - ratio_range_2 = (ratio_turbo - ratio_min) * 2; - vid_range_2 = (vid_turbo - vid_min) * 2; - - /* Generate the remaining entries */ - for (ratio = ratio_min + ((num_entries - 1) * ratio_step); - ratio >= ratio_min; ratio -= ratio_step) { - - /* Calculate VID for this ratio */ - vid = ((ratio - ratio_min) * vid_range_2) / - ratio_range_2 + vid_min; - /* Round up if remainder */ - if (((ratio - ratio_min) * vid_range_2) % ratio_range_2) - vid++; - - /* Calculate power at this ratio */ - power = calculate_power(power_max, ratio_max, ratio); - clock = (ratio * pattrs->bclk_khz) / 1000; - control_status = (ratio << 8) | (vid & 0xff); - - acpigen_write_PSS_package( - clock, /*MHz*/ - power, /*mW*/ - 10, /*lat1*/ - 10, /*lat2*/ - control_status, /*control*/ - control_status); /*status*/ - } - - /* Fix package length */ - acpigen_pop_len(); -} - -void generate_cpu_entries(struct device *device) -{ - int core; - int pcontrol_blk = get_pmbase(), plen = 6; - const struct pattrs *pattrs = pattrs_get(); - - for (core=0; corenum_cpus; core++) { - if (core > 0) { - pcontrol_blk = 0; - plen = 0; - } - - /* Generate processor \_PR.CPUx */ - acpigen_write_processor( - core, pcontrol_blk, plen); - - /* Generate P-state tables */ - generate_P_state_entries( - core, pattrs->num_cpus); - - /* Generate C-state tables */ - acpigen_write_CST_package( - cstate_map, ARRAY_SIZE(cstate_map)); - - /* Generate T-state tables */ - generate_T_state_entries( - core, pattrs->num_cpus); - - acpigen_pop_len(); - } - - /* PPKG is usually used for thermal management - of the first and only package. */ - acpigen_write_processor_package("PPKG", 0, pattrs->num_cpus); - - /* Add a method to notify processor nodes */ - acpigen_write_processor_cnot(pattrs->num_cpus); -} - -unsigned long acpi_madt_irq_overrides(unsigned long current) -{ - int sci_irq = acpi_sci_irq(); - acpi_madt_irqoverride_t *irqovr; - uint16_t sci_flags = MP_IRQ_TRIGGER_LEVEL; - - /* INT_SRC_OVR */ - irqovr = (void *)current; - current += acpi_create_madt_irqoverride(irqovr, 0, 0, 2, 0); - - if (sci_irq >= 20) - sci_flags |= MP_IRQ_POLARITY_LOW; - else - sci_flags |= MP_IRQ_POLARITY_HIGH; - - irqovr = (void *)current; - current += acpi_create_madt_irqoverride(irqovr, 0, sci_irq, sci_irq, - sci_flags); - - return current; -} - -unsigned long southcluster_write_acpi_tables(struct device *device, - unsigned long current, - struct acpi_rsdp *rsdp) -{ - acpi_header_t *ssdt2; - - current = acpi_write_hpet(device, current, rsdp); - current = acpi_align_current(current); - - ssdt2 = (acpi_header_t *)current; - memset(ssdt2, 0, sizeof(acpi_header_t)); - acpi_create_serialio_ssdt(ssdt2); - if (ssdt2->length) { - current += ssdt2->length; - acpi_add_table(rsdp, ssdt2); - printk(BIOS_DEBUG, "ACPI: * SSDT2 @ %p Length %x\n",ssdt2, - ssdt2->length); - current = acpi_align_current(current); - } else { - ssdt2 = NULL; - printk(BIOS_DEBUG, "ACPI: * SSDT2 not generated.\n"); - } - - printk(BIOS_DEBUG, "current = %lx\n", current); - - return current; -} - -void southcluster_inject_dsdt(struct device *device) -{ - global_nvs_t *gnvs; - - gnvs = cbmem_find(CBMEM_ID_ACPI_GNVS); - if (!gnvs) { - gnvs = cbmem_add(CBMEM_ID_ACPI_GNVS, sizeof (*gnvs)); - if (gnvs) - memset(gnvs, 0, sizeof(*gnvs)); - } - - if (gnvs) { - acpi_create_gnvs(gnvs); - /* And tell SMI about it */ - smm_setup_structures(gnvs, NULL, NULL); - - /* Add it to DSDT. */ - acpigen_write_scope("\\"); - acpigen_write_name_dword("NVSA", (u32) gnvs); - acpigen_pop_len(); - } -} diff --git a/src/soc/intel/fsp_baytrail/acpi/device_nvs.asl b/src/soc/intel/fsp_baytrail/acpi/device_nvs.asl deleted file mode 100644 index 54978cd2c0..0000000000 --- a/src/soc/intel/fsp_baytrail/acpi/device_nvs.asl +++ /dev/null @@ -1,82 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2013 Google Inc. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -/* Device Enabled in ACPI Mode */ - -S0EN, 8, // SDMA Enable -S1EN, 8, // I2C1 Enable -S2EN, 8, // I2C2 Enable -S3EN, 8, // I2C3 Enable -S4EN, 8, // I2C4 Enable -S5EN, 8, // I2C5 Enable -S6EN, 8, // I2C6 Enable -S7EN, 8, // I2C7 Enable -S8EN, 8, // SDMA2 Enable -S9EN, 8, // SPI Enable -SAEN, 8, // PWM1 Enable -SBEN, 8, // PWM2 Enable -SCEN, 8, // UART2 Enable -SDEN, 8, // UART2 Enable -C0EN, 8, // MMC Enable -C1EN, 8, // SDIO Enable -C2EN, 8, // SD Card Enable -LPEN, 8, // LPE Enable - -/* BAR 0 */ - -S0B0, 32, // SDMA BAR0 -S1B0, 32, // I2C1 BAR0 -S2B0, 32, // I2C2 BAR0 -S3B0, 32, // I2C3 BAR0 -S4B0, 32, // I2C4 BAR0 -S5B0, 32, // I2C5 BAR0 -S6B0, 32, // I2C6 BAR0 -S7B0, 32, // I2C7 BAR0 -S8B0, 32, // SDMA2 BAR0 -S9B0, 32, // SPI BAR0 -SAB0, 32, // PWM1 BAR0 -SBB0, 32, // PWM2 BAR0 -SCB0, 32, // UART1 BAR0 -SDB0, 32, // UART2 BAR0 -C0B0, 32, // MMC BAR0 -C1B0, 32, // SDIO BAR0 -C2B0, 32, // SD Card BAR0 -LPB0, 32, // LPE BAR0 - -/* BAR 1 */ - -S0B1, 32, // SDMA BAR1 -S1B1, 32, // I2C1 BAR1 -S2B1, 32, // I2C2 BAR1 -S3B1, 32, // I2C3 BAR1 -S4B1, 32, // I2C4 BAR1 -S5B1, 32, // I2C5 BAR1 -S6B1, 32, // I2C6 BAR1 -S7B1, 32, // I2C7 BAR1 -S8B1, 32, // SDMA2 BAR1 -S9B1, 32, // SPI BAR1 -SAB1, 32, // PWM1 BAR1 -SBB1, 32, // PWM2 BAR1 -SCB1, 32, // UART1 BAR1 -SDB1, 32, // UART2 BAR1 -C0B1, 32, // MMC BAR1 -C1B1, 32, // SDIO BAR1 -C2B1, 32, // SD Card BAR1 -LPB1, 32, // LPE BAR1 - -/* Extra */ - -LPFW, 32, // LPE BAR2 Firmware diff --git a/src/soc/intel/fsp_baytrail/acpi/globalnvs.asl b/src/soc/intel/fsp_baytrail/acpi/globalnvs.asl deleted file mode 100644 index c4d91a3c16..0000000000 --- a/src/soc/intel/fsp_baytrail/acpi/globalnvs.asl +++ /dev/null @@ -1,99 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2013 Google Inc. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -/* Global Variables */ - -Name(\PICM, 0) // IOAPIC/8259 - -/* Global ACPI memory region. This region is used for passing information - * between coreboot (aka "the system bios"), ACPI, and the SMI handler. - * Since we don't know where this will end up in memory at ACPI compile time, - * we have to fix it up in coreboot's ACPI creation phase. - */ - - -External(NVSA) -OperationRegion (GNVS, SystemMemory, NVSA, 0x2000) -Field (GNVS, ByteAcc, NoLock, Preserve) -{ - /* Miscellaneous */ - Offset (0x00), - OSYS, 16, // 0x00 - Operating System - SMIF, 8, // 0x02 - SMI function - PRM0, 8, // 0x03 - SMI function parameter - PRM1, 8, // 0x04 - SMI function parameter - SCIF, 8, // 0x05 - SCI function - PRM2, 8, // 0x06 - SCI function parameter - PRM3, 8, // 0x07 - SCI function parameter - LCKF, 8, // 0x08 - Global Lock function for EC - PRM4, 8, // 0x09 - Lock function parameter - PRM5, 8, // 0x0a - Lock function parameter - P80D, 32, // 0x0b - Debug port (IO 0x80) value - LIDS, 8, // 0x0f - LID state (open = 1) - PWRS, 8, // 0x10 - Power State (AC = 1) - PCNT, 8, // 0x11 - Processor count - TPMP, 8, // 0x12 - TPM Present and Enabled - TLVL, 8, // 0x13 - Throttle Level - PPCM, 8, // 0x14 - Maximum P-state usable by OS - - /* Device Config */ - Offset (0x20), - S5U0, 8, // 0x20 - Enable USB0 in S5 - S5U1, 8, // 0x21 - Enable USB1 in S5 - S3U0, 8, // 0x22 - Enable USB0 in S3 - S3U1, 8, // 0x23 - Enable USB1 in S3 - TACT, 8, // 0x24 - Thermal Active trip point - TPSV, 8, // 0x25 - Thermal Passive trip point - TCRT, 8, // 0x26 - Thermal Critical trip point - DPTE, 8, // 0x27 - Enable DPTF - - /* Base addresses */ - Offset (0x30), - CMEM, 32, // 0x30 - CBMEM TOC - TOLM, 32, // 0x34 - Top of Low Memory - CBMC, 32, // 0x38 - coreboot mem console pointer - - Offset (0x1000), - #include -} - -/* Set flag to enable USB charging in S3 */ -Method (S3UE) -{ - Store (One, \S3U0) - Store (One, \S3U1) -} - -/* Set flag to disable USB charging in S3 */ -Method (S3UD) -{ - Store (Zero, \S3U0) - Store (Zero, \S3U1) -} - -/* Set flag to enable USB charging in S5 */ -Method (S5UE) -{ - Store (One, \S5U0) - Store (One, \S5U1) -} - -/* Set flag to disable USB charging in S5 */ -Method (S5UD) -{ - Store (Zero, \S5U0) - Store (Zero, \S5U1) -} diff --git a/src/soc/intel/fsp_baytrail/acpi/gpio.asl b/src/soc/intel/fsp_baytrail/acpi/gpio.asl deleted file mode 100644 index d0e9be5366..0000000000 --- a/src/soc/intel/fsp_baytrail/acpi/gpio.asl +++ /dev/null @@ -1,105 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2013 Google Inc. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include - -/* SouthCluster GPIO */ -Device (GPSC) -{ - Name (_HID, "INT33FC") - Name (_CID, "INT33FC") - Name (_UID, 1) - - Name (RBUF, ResourceTemplate() - { - Memory32Fixed (ReadWrite, 0, 0x1000, RMEM) - Interrupt (ResourceConsumer, Level, ActiveLow, Shared,,,) - { - GPIO_SC_IRQ - } - }) - - Method (_CRS) - { - CreateDwordField (^RBUF, ^RMEM._BAS, RBAS) - Add (IO_BASE_ADDRESS, IO_BASE_OFFSET_GPSCORE, RBAS) - Return (^RBUF) - } - - Method (_STA) - { - Return (0xF) - } -} - -/* NorthCluster GPIO */ -Device (GPNC) -{ - Name (_HID, "INT33FC") - Name (_CID, "INT33FC") - Name (_UID, 2) - - Name (RBUF, ResourceTemplate() - { - Memory32Fixed (ReadWrite, 0, 0x1000, RMEM) - Interrupt (ResourceConsumer, Level, ActiveLow, Shared,,,) - { - GPIO_NC_IRQ - } - }) - - Method (_CRS) - { - CreateDwordField (^RBUF, ^RMEM._BAS, RBAS) - Add (IO_BASE_ADDRESS, IO_BASE_OFFSET_GPNCORE, RBAS) - Return (^RBUF) - } - - Method (_STA) - { - Return (0xF) - } -} - -/* SUS GPIO */ -Device (GPSS) -{ - Name (_HID, "INT33FC") - Name (_CID, "INT33FC") - Name (_UID, 3) - - Name (RBUF, ResourceTemplate() - { - Memory32Fixed (ReadWrite, 0, 0x1000, RMEM) - Interrupt (ResourceConsumer, Level, ActiveLow, Shared,,,) - { - GPIO_SUS_IRQ - } - }) - - Method (_CRS) - { - CreateDwordField (^RBUF, ^RMEM._BAS, RBAS) - Add (IO_BASE_ADDRESS, IO_BASE_OFFSET_GPSSUS, RBAS) - Return (^RBUF) - } - - Method (_STA) - { - Return (0xF) - } -} diff --git a/src/soc/intel/fsp_baytrail/acpi/irq_helper.h b/src/soc/intel/fsp_baytrail/acpi/irq_helper.h deleted file mode 100644 index 8d18aeaeb3..0000000000 --- a/src/soc/intel/fsp_baytrail/acpi/irq_helper.h +++ /dev/null @@ -1,124 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2013 Google Inc. - * Copyright (C) 2014 Sage Electronics Engineering, LLC. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - - -/* - * This file intentionally gets included multiple times, to set pic and apic - * modes, so should not have guard statements added. - */ - -/* - * This file will use arch/x86/acpi/irqroute.asl and mainboard/irqroute.h - * to generate the ACPI IRQ routing for the mainboard being compiled. - * This method uses #defines in irqroute.h along with the macros contained - * in this file to generate an IRQ routing for each PCI device in the system. - */ - -#undef PCI_DEV_PIRQ_ROUTES -#undef ACPI_DEV_IRQ -#undef PCI_DEV_PIRQ_ROUTE -#undef PIRQ_PIC_ROUTES -#undef PIRQ_PIC -#undef IRQROUTE_H -#undef ROOTPORT_METHODS -#undef RP_METHOD -#undef ROOTPORT_IRQ_ROUTES -#undef RP_IRQ_ROUTES - -#if defined(PIC_MODE) - -#define ACPI_DEV_IRQ(dev_, pin_, pin_name_) \ - Package() { ## dev_ ## ffff, pin_, \_SB.PCI0.LPCB.LNK ## pin_name_, 0 } - -#define RP_IRQ_ROUTES(prefix_, func_, a_, b_, c_, d_) \ -Name(prefix_ ## func_ ## P, Package() \ -{ \ - ACPI_DEV_IRQ(0x0000, 0, a_), \ - ACPI_DEV_IRQ(0x0000, 1, b_), \ - ACPI_DEV_IRQ(0x0000, 2, c_), \ - ACPI_DEV_IRQ(0x0000, 3, d_), \ -}) - -/* define as blank so ROOTPORT_METHODS only gets inserted once */ -#define ROOTPORT_METHODS(prefix_, dev_) - -#else /* defined(PIC_MODE) */ - -#define ACPI_DEV_IRQ(dev_, pin_, pin_name_) \ - Package() { ## dev_ ## ffff, pin_, 0, PIRQ ## pin_name_ ## _APIC_IRQ } - -#define RP_IRQ_ROUTES(prefix_, func_, a_, b_, c_, d_) \ -Name(prefix_ ## func_ ## A, Package() \ -{ \ - ACPI_DEV_IRQ(0x0000, 0, a_), \ - ACPI_DEV_IRQ(0x0000, 1, b_), \ - ACPI_DEV_IRQ(0x0000, 2, c_), \ - ACPI_DEV_IRQ(0x0000, 3, d_), \ -}) - -#define ROOTPORT_METHODS(prefix_, dev_) \ - RP_METHOD(prefix_, dev_, 0) \ - RP_METHOD(prefix_, dev_, 1) \ - RP_METHOD(prefix_, dev_, 2) \ - RP_METHOD(prefix_, dev_, 3) \ - RP_METHOD(prefix_, dev_, 4) \ - RP_METHOD(prefix_, dev_, 5) \ - RP_METHOD(prefix_, dev_, 6) \ - RP_METHOD(prefix_, dev_, 7) - -#endif /* defined(PIC_MODE) */ - -#define PCI_DEV_PIRQ_ROUTE(dev_, a_, b_, c_, d_) \ - ACPI_DEV_IRQ(dev_, 0, a_), \ - ACPI_DEV_IRQ(dev_, 1, b_), \ - ACPI_DEV_IRQ(dev_, 2, c_), \ - ACPI_DEV_IRQ(dev_, 3, d_) - -#define PCIE_BRIDGE_DEV(prefix_, dev_, a_, b_, c_, d_) \ - ROOTPORT_IRQ_ROUTES(prefix_, a_, b_, c_, d_) \ - ROOTPORT_METHODS(prefix_, dev_) - -#define ROOTPORT_IRQ_ROUTES(prefix_, a_, b_, c_, d_) \ - RP_IRQ_ROUTES(prefix_, 0, a_, b_, c_, d_) \ - RP_IRQ_ROUTES(prefix_, 1, b_, c_, d_, a_) \ - RP_IRQ_ROUTES(prefix_, 2, c_, d_, a_, b_) \ - RP_IRQ_ROUTES(prefix_, 3, d_, a_, b_, c_) \ - RP_IRQ_ROUTES(prefix_, 4, a_, b_, c_, d_) \ - RP_IRQ_ROUTES(prefix_, 5, b_, c_, d_, a_) \ - RP_IRQ_ROUTES(prefix_, 6, c_, d_, a_, b_) \ - RP_IRQ_ROUTES(prefix_, 7, d_, a_, b_, c_) - -#define RP_METHOD(prefix_, dev_, func_)\ -Device(prefix_ ## 0 ## func_) \ -{ \ - Name(_ADR, dev_ ## 000 ## func_) \ - Name(_PRW, Package() { \ - 0, 0 \ - }) \ - Method(_PRT,0) { \ - If(PICM) { \ - Return (prefix_ ## func_ ## A) \ - } Else { \ - Return (prefix_ ## func_ ## P) \ - } \ - } \ -} - -/* Empty PIRQ_PIC definition. */ -#define PIRQ_PIC(pirq_, pic_irq_) - -/* Include the mainboard irq route definition */ -#include "irqroute.h" diff --git a/src/soc/intel/fsp_baytrail/acpi/irqlinks.asl b/src/soc/intel/fsp_baytrail/acpi/irqlinks.asl deleted file mode 100644 index 2d029242d8..0000000000 --- a/src/soc/intel/fsp_baytrail/acpi/irqlinks.asl +++ /dev/null @@ -1,487 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007-2009 coresystems GmbH - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -Device (LNKA) -{ - Name (_HID, EISAID("PNP0C0F")) - Name (_UID, 1) - - // Disable method - Method (_DIS, 0, Serialized) - { - Store (0x80, PRTA) - } - - // Possible Resource Settings for this Link - Name (_PRS, ResourceTemplate() - { - IRQ(Level, ActiveLow, Shared) - { 3, 4, 5, 6, 7, 10, 12, 14, 15 } - }) - - // Current Resource Settings for this link - Method (_CRS, 0, Serialized) - { - Name (RTLA, ResourceTemplate() - { - IRQ(Level, ActiveLow, Shared) {} - }) - CreateWordField(RTLA, 1, IRQ0) - - // Clear the WordField - Store (Zero, IRQ0) - - // Set the bit from PRTA - ShiftLeft(1, And(PRTA, 0x0f), IRQ0) - - Return (RTLA) - } - - // Set Resource Setting for this IRQ link - Method (_SRS, 1, Serialized) - { - CreateWordField(Arg0, 1, IRQ0) - - // Which bit is set? - FindSetRightBit(IRQ0, Local0) - - Decrement(Local0) - Store(Local0, PRTA) - } - - // Status - Method (_STA, 0, Serialized) - { - If(And(PRTA, 0x80)) { - Return (0x9) - } Else { - Return (0xb) - } - } -} - -Device (LNKB) -{ - Name (_HID, EISAID("PNP0C0F")) - Name (_UID, 2) - - // Disable method - Method (_DIS, 0, Serialized) - { - Store (0x80, PRTB) - } - - // Possible Resource Settings for this Link - Name (_PRS, ResourceTemplate() - { - IRQ(Level, ActiveLow, Shared) - { 3, 4, 5, 6, 7, 11, 12, 14, 15 } - }) - - // Current Resource Settings for this link - Method (_CRS, 0, Serialized) - { - Name (RTLB, ResourceTemplate() - { - IRQ(Level, ActiveLow, Shared) {} - }) - CreateWordField(RTLB, 1, IRQ0) - - // Clear the WordField - Store (Zero, IRQ0) - - // Set the bit from PRTB - ShiftLeft(1, And(PRTB, 0x0f), IRQ0) - - Return (RTLB) - } - - // Set Resource Setting for this IRQ link - Method (_SRS, 1, Serialized) - { - CreateWordField(Arg0, 1, IRQ0) - - // Which bit is set? - FindSetRightBit(IRQ0, Local0) - - Decrement(Local0) - Store(Local0, PRTB) - } - - // Status - Method (_STA, 0, Serialized) - { - If(And(PRTB, 0x80)) { - Return (0x9) - } Else { - Return (0xb) - } - } -} - -Device (LNKC) -{ - Name (_HID, EISAID("PNP0C0F")) - Name (_UID, 3) - - // Disable method - Method (_DIS, 0, Serialized) - { - Store (0x80, PRTC) - } - - // Possible Resource Settings for this Link - Name (_PRS, ResourceTemplate() - { - IRQ(Level, ActiveLow, Shared) - { 3, 4, 5, 6, 7, 10, 12, 14, 15 } - }) - - // Current Resource Settings for this link - Method (_CRS, 0, Serialized) - { - Name (RTLC, ResourceTemplate() - { - IRQ(Level, ActiveLow, Shared) {} - }) - CreateWordField(RTLC, 1, IRQ0) - - // Clear the WordField - Store (Zero, IRQ0) - - // Set the bit from PRTC - ShiftLeft(1, And(PRTC, 0x0f), IRQ0) - - Return (RTLC) - } - - // Set Resource Setting for this IRQ link - Method (_SRS, 1, Serialized) - { - CreateWordField(Arg0, 1, IRQ0) - - // Which bit is set? - FindSetRightBit(IRQ0, Local0) - - Decrement(Local0) - Store(Local0, PRTC) - } - - // Status - Method (_STA, 0, Serialized) - { - If(And(PRTC, 0x80)) { - Return (0x9) - } Else { - Return (0xb) - } - } -} - -Device (LNKD) -{ - Name (_HID, EISAID("PNP0C0F")) - Name (_UID, 4) - - // Disable method - Method (_DIS, 0, Serialized) - { - Store (0x80, PRTD) - } - - // Possible Resource Settings for this Link - Name (_PRS, ResourceTemplate() - { - IRQ(Level, ActiveLow, Shared) - { 3, 4, 5, 6, 7, 11, 12, 14, 15 } - }) - - // Current Resource Settings for this link - Method (_CRS, 0, Serialized) - { - Name (RTLD, ResourceTemplate() - { - IRQ(Level, ActiveLow, Shared) {} - }) - CreateWordField(RTLD, 1, IRQ0) - - // Clear the WordField - Store (Zero, IRQ0) - - // Set the bit from PRTD - ShiftLeft(1, And(PRTD, 0x0f), IRQ0) - - Return (RTLD) - } - - // Set Resource Setting for this IRQ link - Method (_SRS, 1, Serialized) - { - CreateWordField(Arg0, 1, IRQ0) - - // Which bit is set? - FindSetRightBit(IRQ0, Local0) - - Decrement(Local0) - Store(Local0, PRTD) - } - - // Status - Method (_STA, 0, Serialized) - { - If(And(PRTD, 0x80)) { - Return (0x9) - } Else { - Return (0xb) - } - } -} - -Device (LNKE) -{ - Name (_HID, EISAID("PNP0C0F")) - Name (_UID, 5) - - // Disable method - Method (_DIS, 0, Serialized) - { - Store (0x80, PRTE) - } - - // Possible Resource Settings for this Link - Name (_PRS, ResourceTemplate() - { - IRQ(Level, ActiveLow, Shared) - { 3, 4, 5, 6, 7, 10, 12, 14, 15 } - }) - - // Current Resource Settings for this link - Method (_CRS, 0, Serialized) - { - Name (RTLE, ResourceTemplate() - { - IRQ(Level, ActiveLow, Shared) {} - }) - CreateWordField(RTLE, 1, IRQ0) - - // Clear the WordField - Store (Zero, IRQ0) - - // Set the bit from PRTE - ShiftLeft(1, And(PRTE, 0x0f), IRQ0) - - Return (RTLE) - } - - // Set Resource Setting for this IRQ link - Method (_SRS, 1, Serialized) - { - CreateWordField(Arg0, 1, IRQ0) - - // Which bit is set? - FindSetRightBit(IRQ0, Local0) - - Decrement(Local0) - Store(Local0, PRTE) - } - - // Status - Method (_STA, 0, Serialized) - { - If(And(PRTE, 0x80)) { - Return (0x9) - } Else { - Return (0xb) - } - } -} - -Device (LNKF) -{ - Name (_HID, EISAID("PNP0C0F")) - Name (_UID, 6) - - // Disable method - Method (_DIS, 0, Serialized) - { - Store (0x80, PRTF) - } - - // Possible Resource Settings for this Link - Name (_PRS, ResourceTemplate() - { - IRQ(Level, ActiveLow, Shared) - { 3, 4, 5, 6, 7, 11, 12, 14, 15 } - }) - - // Current Resource Settings for this link - Method (_CRS, 0, Serialized) - { - Name (RTLF, ResourceTemplate() - { - IRQ(Level, ActiveLow, Shared) {} - }) - CreateWordField(RTLF, 1, IRQ0) - - // Clear the WordField - Store (Zero, IRQ0) - - // Set the bit from PRTF - ShiftLeft(1, And(PRTF, 0x0f), IRQ0) - - Return (RTLF) - } - - // Set Resource Setting for this IRQ link - Method (_SRS, 1, Serialized) - { - CreateWordField(Arg0, 1, IRQ0) - - // Which bit is set? - FindSetRightBit(IRQ0, Local0) - - Decrement(Local0) - Store(Local0, PRTF) - } - - // Status - Method (_STA, 0, Serialized) - { - If(And(PRTF, 0x80)) { - Return (0x9) - } Else { - Return (0xb) - } - } -} - -Device (LNKG) -{ - Name (_HID, EISAID("PNP0C0F")) - Name (_UID, 7) - - // Disable method - Method (_DIS, 0, Serialized) - { - Store (0x80, PRTG) - } - - // Possible Resource Settings for this Link - Name (_PRS, ResourceTemplate() - { - IRQ(Level, ActiveLow, Shared) - { 3, 4, 5, 6, 7, 10, 12, 14, 15 } - }) - - // Current Resource Settings for this link - Method (_CRS, 0, Serialized) - { - Name (RTLG, ResourceTemplate() - { - IRQ(Level, ActiveLow, Shared) {} - }) - CreateWordField(RTLG, 1, IRQ0) - - // Clear the WordField - Store (Zero, IRQ0) - - // Set the bit from PRTG - ShiftLeft(1, And(PRTG, 0x0f), IRQ0) - - Return (RTLG) - } - - // Set Resource Setting for this IRQ link - Method (_SRS, 1, Serialized) - { - CreateWordField(Arg0, 1, IRQ0) - - // Which bit is set? - FindSetRightBit(IRQ0, Local0) - - Decrement(Local0) - Store(Local0, PRTG) - } - - // Status - Method (_STA, 0, Serialized) - { - If(And(PRTG, 0x80)) { - Return (0x9) - } Else { - Return (0xb) - } - } -} - -Device (LNKH) -{ - Name (_HID, EISAID("PNP0C0F")) - Name (_UID, 8) - - // Disable method - Method (_DIS, 0, Serialized) - { - Store (0x80, PRTH) - } - - // Possible Resource Settings for this Link - Name (_PRS, ResourceTemplate() - { - IRQ(Level, ActiveLow, Shared) - { 3, 4, 5, 6, 7, 11, 12, 14, 15 } - }) - - // Current Resource Settings for this link - Method (_CRS, 0, Serialized) - { - Name (RTLH, ResourceTemplate() - { - IRQ(Level, ActiveLow, Shared) {} - }) - CreateWordField(RTLH, 1, IRQ0) - - // Clear the WordField - Store (Zero, IRQ0) - - // Set the bit from PRTH - ShiftLeft(1, And(PRTH, 0x0f), IRQ0) - - Return (RTLH) - } - - // Set Resource Setting for this IRQ link - Method (_SRS, 1, Serialized) - { - CreateWordField(Arg0, 1, IRQ0) - - // Which bit is set? - FindSetRightBit(IRQ0, Local0) - - Decrement(Local0) - Store(Local0, PRTH) - } - - // Status - Method (_STA, 0, Serialized) - { - If(And(PRTH, 0x80)) { - Return (0x9) - } Else { - Return (0xb) - } - } -} diff --git a/src/soc/intel/fsp_baytrail/acpi/irqroute.asl b/src/soc/intel/fsp_baytrail/acpi/irqroute.asl deleted file mode 100644 index 4f3a744ff5..0000000000 --- a/src/soc/intel/fsp_baytrail/acpi/irqroute.asl +++ /dev/null @@ -1,45 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007-2009 coresystems GmbH - * Copyright (C) 2013 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -// PCI Interrupt Routing -Method(_PRT) -{ - /* - * PICM comes from _PIC, which returns the following: - * 0 - PIC mode - * 1 - APIC mode - * 2 - SAPIC mode - */ - If (PICM) { - Return (Package() { - #undef PIC_MODE - #include "irq_helper.h" - PCI_DEV_PIRQ_ROUTES - }) - } Else { - Return (Package() { - #define PIC_MODE - #include "irq_helper.h" - PCI_DEV_PIRQ_ROUTES - }) - } - -} - -PCIE_BRIDGE_IRQ_ROUTES -#undef PIC_MODE -#include "irq_helper.h" -PCIE_BRIDGE_IRQ_ROUTES diff --git a/src/soc/intel/fsp_baytrail/acpi/lpc.asl b/src/soc/intel/fsp_baytrail/acpi/lpc.asl deleted file mode 100644 index 7cdf1aa5d0..0000000000 --- a/src/soc/intel/fsp_baytrail/acpi/lpc.asl +++ /dev/null @@ -1,138 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007-2009 coresystems GmbH - * Copyright (C) 2013 Google Inc. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -// Intel LPC Bus Device - 0:1f.0 - -Device (LPCB) -{ - Name(_ADR, 0x001f0000) - - #include "irqlinks.asl" - - #include "acpi/ec.asl" - - Device (DMAC) // DMA Controller - { - Name(_HID, EISAID("PNP0200")) - Name(_CRS, ResourceTemplate() - { - IO (Decode16, 0x00, 0x00, 0x01, 0x20) - IO (Decode16, 0x81, 0x81, 0x01, 0x11) - IO (Decode16, 0x93, 0x93, 0x01, 0x0d) - IO (Decode16, 0xc0, 0xc0, 0x01, 0x20) - DMA (Compatibility, NotBusMaster, Transfer8_16) { 4 } - }) - } - - Device (FWH) // Firmware Hub - { - Name (_HID, EISAID("INT0800")) - Name (_CRS, ResourceTemplate() - { - Memory32Fixed(ReadOnly, 0xff000000, 0x01000000) - }) - } - - Device (HPET) - { - Name (_HID, EISAID("PNP0103")) - Name (_CID, 0x010CD041) - - Method (_STA, 0) // Device Status - { - Return (0xf) // Enable and show device - } - - Name(_CRS, ResourceTemplate() - { - Memory32Fixed(ReadOnly, CONFIG_HPET_ADDRESS, 0x400) - }) - } - - Device(PIC) // 8259 Interrupt Controller - { - Name(_HID,EISAID("PNP0000")) - Name(_CRS, ResourceTemplate() - { - IO (Decode16, 0x20, 0x20, 0x01, 0x02) - IO (Decode16, 0x24, 0x24, 0x01, 0x02) - IO (Decode16, 0x28, 0x28, 0x01, 0x02) - IO (Decode16, 0x2c, 0x2c, 0x01, 0x02) - IO (Decode16, 0x30, 0x30, 0x01, 0x02) - IO (Decode16, 0x34, 0x34, 0x01, 0x02) - IO (Decode16, 0x38, 0x38, 0x01, 0x02) - IO (Decode16, 0x3c, 0x3c, 0x01, 0x02) - IO (Decode16, 0xa0, 0xa0, 0x01, 0x02) - IO (Decode16, 0xa4, 0xa4, 0x01, 0x02) - IO (Decode16, 0xa8, 0xa8, 0x01, 0x02) - IO (Decode16, 0xac, 0xac, 0x01, 0x02) - IO (Decode16, 0xb0, 0xb0, 0x01, 0x02) - IO (Decode16, 0xb4, 0xb4, 0x01, 0x02) - IO (Decode16, 0xb8, 0xb8, 0x01, 0x02) - IO (Decode16, 0xbc, 0xbc, 0x01, 0x02) - IO (Decode16, 0x4d0, 0x4d0, 0x01, 0x02) - IRQNoFlags () { 2 } - }) - } - - Device(LDRC) // LPC device: Resource consumption - { - Name (_HID, EISAID("PNP0C02")) - Name (_UID, 2) - - Name (RBUF, ResourceTemplate() - { - IO (Decode16, 0x61, 0x61, 0x1, 0x01) // NMI Status - IO (Decode16, 0x63, 0x63, 0x1, 0x01) // CPU Reserved - IO (Decode16, 0x65, 0x65, 0x1, 0x01) // CPU Reserved - IO (Decode16, 0x67, 0x67, 0x1, 0x01) // CPU Reserved - IO (Decode16, 0x80, 0x80, 0x1, 0x01) // Port 80 Post - IO (Decode16, 0x92, 0x92, 0x1, 0x01) // CPU Reserved - IO (Decode16, 0xb2, 0xb2, 0x1, 0x02) // SWSMI - }) - - Method (_CRS, 0, NotSerialized) - { - Return (RBUF) - } - } - - Device (RTC) // Real Time Clock - { - Name (_HID, EISAID("PNP0B00")) - Name (_CRS, ResourceTemplate() - { - IO (Decode16, 0x70, 0x70, 1, 8) -// Disable as Windows doesn't like it, and systems don't seem to use it. -// IRQNoFlags() { 8 } - }) - } - - Device (TIMR) // Intel 8254 timer - { - Name(_HID, EISAID("PNP0100")) - Name(_CRS, ResourceTemplate() - { - IO (Decode16, 0x40, 0x40, 0x01, 0x04) - IO (Decode16, 0x50, 0x50, 0x10, 0x04) - IRQNoFlags() {0} - }) - } - - // Include mainboard's superio.asl file. - #include "acpi/superio.asl" -} diff --git a/src/soc/intel/fsp_baytrail/acpi/lpe.asl b/src/soc/intel/fsp_baytrail/acpi/lpe.asl deleted file mode 100644 index d1dbd3a4b2..0000000000 --- a/src/soc/intel/fsp_baytrail/acpi/lpe.asl +++ /dev/null @@ -1,114 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2014 Google Inc. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -Device (LPEA) -{ - Name (_HID, "80860F28") - Name (_CID, "80860F28") - Name (_UID, 1) - Name (_DDN, "Low Power Audio Controller") - Name (_PR0, Package () { PLPE }) - - Name (RBUF, ResourceTemplate() - { - Memory32Fixed (ReadWrite, 0, 0x00200000, BAR0) - Memory32Fixed (ReadWrite, 0, 0x00001000, BAR1) - Memory32Fixed (ReadWrite, 0, 0x00100000, BAR2) - Interrupt (ResourceConsumer, Level, ActiveLow, Exclusive,,,) - { - LPE_DMA0_IRQ - } - Interrupt (ResourceConsumer, Level, ActiveLow, Exclusive,,,) - { - LPE_DMA1_IRQ - } - Interrupt (ResourceConsumer, Level, ActiveLow, Exclusive,,,) - { - LPE_SSP0_IRQ - } - Interrupt (ResourceConsumer, Level, ActiveLow, Exclusive,,,) - { - LPE_SSP1_IRQ - } - Interrupt (ResourceConsumer, Level, ActiveLow, Exclusive,,,) - { - LPE_SSP2_IRQ - } - Interrupt (ResourceConsumer, Level, ActiveLow, Exclusive,,,) - { - LPE_IPC2HOST_IRQ - } - }) - - Method (_CRS) - { - /* Update BAR0 from NVS */ - CreateDwordField (^RBUF, ^BAR0._BAS, BAS0) - Store (\LPB0, BAS0) - - /* Update BAR1 from NVS */ - CreateDwordField (^RBUF, ^BAR1._BAS, BAS1) - Store (\LPB1, BAS1) - - /* Update LPE FW from NVS */ - CreateDwordField (^RBUF, ^BAR2._BAS, BAS2) - Store (\LPFW, BAS2) - - /* Append any Mainboard defined GPIOs */ - If (CondRefOf (^GBUF, Local0)) { - ConcatenateResTemplate (^RBUF, Local0, Local1) - Return (Local1) - } - - Return (^RBUF) - } - - Method (_STA) - { - If (LEqual (\LPEN, 1)) { - Return (0xF) - } Else { - Return (0x0) - } - } - - OperationRegion (KEYS, SystemMemory, LPB1, 0x100) - Field (KEYS, DWordAcc, NoLock, WriteAsZeros) - { - Offset (0x84), - PSAT, 32, - } - - PowerResource (PLPE, 0, 0) - { - Method (_STA) - { - Return (1) - } - - Method (_OFF) - { - Or (PSAT, 0x00000003, PSAT) - Or (PSAT, 0x00000000, PSAT) - } - - Method (_ON) - { - And (PSAT, 0xfffffffc, PSAT) - Or (PSAT, 0x00000000, PSAT) - } - } -} diff --git a/src/soc/intel/fsp_baytrail/acpi/lpss.asl b/src/soc/intel/fsp_baytrail/acpi/lpss.asl deleted file mode 100644 index 6cac06a13e..0000000000 --- a/src/soc/intel/fsp_baytrail/acpi/lpss.asl +++ /dev/null @@ -1,707 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2013 Google Inc. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -Device (SDM1) -{ - Name (_HID, "INTL9C60") - Name (_UID, 1) - Name (_DDN, "DMA Controller #1") - - Name (RBUF, ResourceTemplate() - { - Memory32Fixed (ReadWrite, 0, 0x1000, BAR0) - Interrupt (ResourceConsumer, Level, ActiveLow, Exclusive,,,) - { - LPSS_DMA1_IRQ - } - }) - - Method (_CRS) - { - CreateDwordField (^RBUF, ^BAR0._BAS, RBAS) - Store (\S0B0, RBAS) - Return (^RBUF) - } - - Method (_STA) - { - If (LEqual (\S0EN, 1)) { - Return (0xF) - } Else { - Return (0x0) - } - } -} - -Device (SDM2) -{ - Name (_HID, "INTL9C60") - Name (_UID, 2) - Name (_DDN, "DMA Controller #2") - - Name (RBUF, ResourceTemplate() - { - Memory32Fixed (ReadWrite, 0, 0x1000, BAR0) - Interrupt (ResourceConsumer, Level, ActiveLow, Exclusive,,,) - { - LPSS_DMA2_IRQ - } - }) - - Method (_CRS) - { - CreateDwordField (^RBUF, ^BAR0._BAS, RBAS) - Store (\S8B0, RBAS) - Return (^RBUF) - } - - Method (_STA) - { - If (LEqual (\S8EN, 1)) { - Return (0xF) - } Else { - Return (0x0) - } - } -} - -Device (I2C1) -{ - Name (_HID, "80860F41") - Name (_UID, 1) - Name (_DDN, "I2C Controller #1") - - /* Standard Mode: HCNT, LCNT, SDA Hold Time */ - Name (SSCN, Package () { 0x200, 0x200, 0x6 }) - - /* Fast Mode: HCNT, LCNT, SDA Hold Time */ - Name (FMCN, Package () { 0x55, 0x99, 0x6 }) - - Name (RBUF, ResourceTemplate() - { - Memory32Fixed (ReadWrite, 0, 0x1000, BAR0) - Interrupt (ResourceConsumer, Level, ActiveLow, Exclusive,,,) - { - LPSS_I2C1_IRQ - } - FixedDMA (0x10, 0x0, Width32Bit, ) - FixedDMA (0x11, 0x1, Width32Bit, ) - }) - - Method (_CRS) - { - CreateDwordField (^RBUF, ^BAR0._BAS, RBAS) - Store (\S1B0, RBAS) - Return (^RBUF) - } - - Method (_STA) - { - If (LEqual (\S1EN, 1)) { - Return (0xF) - } Else { - Return (0x0) - } - } - - OperationRegion (KEYS, SystemMemory, S1B1, 0x100) - Field (KEYS, DWordAcc, NoLock, WriteAsZeros) - { - Offset (0x84), - PSAT, 32, - } - - Method (_PS3) - { - Or (PSAT, 0x00000003, PSAT) - Or (PSAT, 0x00000000, PSAT) - } - - Method (_PS0) - { - And (PSAT, 0xfffffffc, PSAT) - Or (PSAT, 0x00000000, PSAT) - } -} - -Device (I2C2) -{ - Name (_HID, "80860F41") - Name (_UID, 2) - Name (_DDN, "I2C Controller #2") - - /* Standard Mode: HCNT, LCNT, SDA Hold Time */ - Name (SSCN, Package () { 0x200, 0x200, 0x6 }) - - /* Fast Mode: HCNT, LCNT, SDA Hold Time */ - Name (FMCN, Package () { 0x55, 0x99, 0x6 }) - - Name (RBUF, ResourceTemplate() - { - Memory32Fixed (ReadWrite, 0, 0x1000, BAR0) - Interrupt (ResourceConsumer, Level, ActiveLow, Exclusive,,,) - { - LPSS_I2C2_IRQ - } - FixedDMA (0x10, 0x0, Width32Bit, ) - FixedDMA (0x11, 0x1, Width32Bit, ) - }) - - Method (_CRS) - { - CreateDwordField (^RBUF, ^BAR0._BAS, RBAS) - Store (\S2B0, RBAS) - Return (^RBUF) - } - - Method (_STA) - { - If (LEqual (\S2EN, 1)) { - Return (0xF) - } Else { - Return (0x0) - } - } - - OperationRegion (KEYS, SystemMemory, S2B1, 0x100) - Field (KEYS, DWordAcc, NoLock, WriteAsZeros) - { - Offset (0x84), - PSAT, 32, - } - - Method (_PS3) - { - Or (PSAT, 0x00000003, PSAT) - Or (PSAT, 0x00000000, PSAT) - } - - Method (_PS0) - { - And (PSAT, 0xfffffffc, PSAT) - Or (PSAT, 0x00000000, PSAT) - } -} - -Device (I2C3) -{ - Name (_HID, "80860F41") - Name (_UID, 3) - Name (_DDN, "I2C Controller #3") - - /* Standard Mode: HCNT, LCNT, SDA Hold Time */ - Name (SSCN, Package () { 0x200, 0x200, 0x6 }) - - /* Fast Mode: HCNT, LCNT, SDA Hold Time */ - Name (FMCN, Package () { 0x55, 0x99, 0x6 }) - - Name (RBUF, ResourceTemplate() - { - Memory32Fixed (ReadWrite, 0, 0x1000, BAR0) - Interrupt (ResourceConsumer, Level, ActiveLow, Exclusive,,,) - { - LPSS_I2C3_IRQ - } - FixedDMA (0x10, 0x0, Width32Bit, ) - FixedDMA (0x11, 0x1, Width32Bit, ) - }) - - Method (_CRS) - { - CreateDwordField (^RBUF, ^BAR0._BAS, RBAS) - Store (\S3B0, RBAS) - Return (^RBUF) - } - - Method (_STA) - { - If (LEqual (\S3EN, 1)) { - Return (0xF) - } Else { - Return (0x0) - } - } - - OperationRegion (KEYS, SystemMemory, S3B1, 0x100) - Field (KEYS, DWordAcc, NoLock, WriteAsZeros) - { - Offset (0x84), - PSAT, 32, - } - - Method (_PS3) - { - Or (PSAT, 0x00000003, PSAT) - Or (PSAT, 0x00000000, PSAT) - } - - Method (_PS0) - { - And (PSAT, 0xfffffffc, PSAT) - Or (PSAT, 0x00000000, PSAT) - } -} - -Device (I2C4) -{ - Name (_HID, "80860F41") - Name (_UID, 4) - Name (_DDN, "I2C Controller #4") - - /* Standard Mode: HCNT, LCNT, SDA Hold Time */ - Name (SSCN, Package () { 0x200, 0x200, 0x6 }) - - /* Fast Mode: HCNT, LCNT, SDA Hold Time */ - Name (FMCN, Package () { 0x55, 0x99, 0x6 }) - - Name (RBUF, ResourceTemplate() - { - Memory32Fixed (ReadWrite, 0, 0x1000, BAR0) - Interrupt (ResourceConsumer, Level, ActiveLow, Exclusive,,,) - { - LPSS_I2C4_IRQ - } - FixedDMA (0x10, 0x0, Width32Bit, ) - FixedDMA (0x11, 0x1, Width32Bit, ) - }) - - Method (_CRS) - { - CreateDwordField (^RBUF, ^BAR0._BAS, RBAS) - Store (\S4B0, RBAS) - Return (^RBUF) - } - - Method (_STA) - { - If (LEqual (\S4EN, 1)) { - Return (0xF) - } Else { - Return (0x0) - } - } - - OperationRegion (KEYS, SystemMemory, S4B1, 0x100) - Field (KEYS, DWordAcc, NoLock, WriteAsZeros) - { - Offset (0x84), - PSAT, 32, - } - - Method (_PS3) - { - Or (PSAT, 0x00000003, PSAT) - Or (PSAT, 0x00000000, PSAT) - } - - Method (_PS0) - { - And (PSAT, 0xfffffffc, PSAT) - Or (PSAT, 0x00000000, PSAT) - } -} - -Device (I2C5) -{ - Name (_HID, "80860F41") - Name (_UID, 5) - Name (_DDN, "I2C Controller #5") - - /* Standard Mode: HCNT, LCNT, SDA Hold Time */ - Name (SSCN, Package () { 0x200, 0x200, 0x6 }) - - /* Fast Mode: HCNT, LCNT, SDA Hold Time */ - Name (FMCN, Package () { 0x55, 0x99, 0x6 }) - - Name (RBUF, ResourceTemplate() - { - Memory32Fixed (ReadWrite, 0, 0x1000, BAR0) - Interrupt (ResourceConsumer, Level, ActiveLow, Exclusive,,,) - { - LPSS_I2C5_IRQ - } - FixedDMA (0x10, 0x0, Width32Bit, ) - FixedDMA (0x11, 0x1, Width32Bit, ) - }) - - Method (_CRS) - { - CreateDwordField (^RBUF, ^BAR0._BAS, RBAS) - Store (\S5B0, RBAS) - Return (^RBUF) - } - - Method (_STA) - { - If (LEqual (\S5EN, 1)) { - Return (0xF) - } Else { - Return (0x0) - } - } - - OperationRegion (KEYS, SystemMemory, S5B1, 0x100) - Field (KEYS, DWordAcc, NoLock, WriteAsZeros) - { - Offset (0x84), - PSAT, 32, - } - - Method (_PS3) - { - Or (PSAT, 0x00000003, PSAT) - Or (PSAT, 0x00000000, PSAT) - } - - Method (_PS0) - { - And (PSAT, 0xfffffffc, PSAT) - Or (PSAT, 0x00000000, PSAT) - } -} - -Device (I2C6) -{ - Name (_HID, "80860F41") - Name (_UID, 6) - Name (_DDN, "I2C Controller #6") - - /* Standard Mode: HCNT, LCNT, SDA Hold Time */ - Name (SSCN, Package () { 0x200, 0x200, 0x6 }) - - /* Fast Mode: HCNT, LCNT, SDA Hold Time */ - Name (FMCN, Package () { 0x55, 0x99, 0x6 }) - - Name (RBUF, ResourceTemplate() - { - Memory32Fixed (ReadWrite, 0, 0x1000, BAR0) - Interrupt (ResourceConsumer, Level, ActiveLow, Exclusive,,,) - { - LPSS_I2C6_IRQ - } - FixedDMA (0x10, 0x0, Width32Bit, ) - FixedDMA (0x11, 0x1, Width32Bit, ) - }) - - Method (_CRS) - { - CreateDwordField (^RBUF, ^BAR0._BAS, RBAS) - Store (\S6B0, RBAS) - Return (^RBUF) - } - - Method (_STA) - { - If (LEqual (\S6EN, 1)) { - Return (0xF) - } Else { - Return (0x0) - } - } - - OperationRegion (KEYS, SystemMemory, S6B1, 0x100) - Field (KEYS, DWordAcc, NoLock, WriteAsZeros) - { - Offset (0x84), - PSAT, 32, - } - - Method (_PS3) - { - Or (PSAT, 0x00000003, PSAT) - Or (PSAT, 0x00000000, PSAT) - } - - Method (_PS0) - { - And (PSAT, 0xfffffffc, PSAT) - Or (PSAT, 0x00000000, PSAT) - } -} - -Device (I2C7) -{ - Name (_HID, "80860F41") - Name (_UID, 7) - Name (_DDN, "I2C Controller #7") - - /* Standard Mode: HCNT, LCNT, SDA Hold Time */ - Name (SSCN, Package () { 0x200, 0x200, 0x6 }) - - /* Fast Mode: HCNT, LCNT, SDA Hold Time */ - Name (FMCN, Package () { 0x55, 0x99, 0x6 }) - - Name (RBUF, ResourceTemplate() - { - Memory32Fixed (ReadWrite, 0, 0x1000, BAR0) - Interrupt (ResourceConsumer, Level, ActiveLow, Exclusive,,,) - { - LPSS_I2C7_IRQ - } - FixedDMA (0x10, 0x0, Width32Bit, ) - FixedDMA (0x11, 0x1, Width32Bit, ) - }) - - Method (_CRS) - { - CreateDwordField (^RBUF, ^BAR0._BAS, RBAS) - Store (\S7B0, RBAS) - Return (^RBUF) - } - - Method (_STA) - { - If (LEqual (\S7EN, 1)) { - Return (0xF) - } Else { - Return (0x0) - } - } - - OperationRegion (KEYS, SystemMemory, S7B1, 0x100) - Field (KEYS, DWordAcc, NoLock, WriteAsZeros) - { - Offset (0x84), - PSAT, 32, - } - - Method (_PS3) - { - Or (PSAT, 0x00000003, PSAT) - Or (PSAT, 0x00000000, PSAT) - } - - Method (_PS0) - { - And (PSAT, 0xfffffffc, PSAT) - Or (PSAT, 0x00000000, PSAT) - } -} - -Device (SPI1) -{ - Name (_HID, "80860F0E") - Name (_UID, 1) - Name (_DDN, "SPI Controller #2") - - Name (RBUF, ResourceTemplate() - { - Memory32Fixed (ReadWrite, 0, 0x1000, BAR0) - Interrupt (ResourceConsumer, Level, ActiveLow, Exclusive,,,) - { - LPSS_SPI_IRQ - } - FixedDMA (0x0, 0x0, Width32Bit, ) - FixedDMA (0x1, 0x1, Width32Bit, ) - }) - - Method (_CRS) - { - CreateDwordField (^RBUF, ^BAR0._BAS, RBAS) - Store (\S9B0, RBAS) - Return (^RBUF) - } - - Method (_STA) - { - If (LEqual (\S9EN, 1)) { - Return (0xF) - } Else { - Return (0x0) - } - } - - OperationRegion (KEYS, SystemMemory, S9B1, 0x100) - Field (KEYS, DWordAcc, NoLock, WriteAsZeros) - { - Offset (0x84), - PSAT, 32, - } - - Method (_PS3) - { - Or (PSAT, 0x00000003, PSAT) - Or (PSAT, 0x00000000, PSAT) - } - - Method (_PS0) - { - And (PSAT, 0xfffffffc, PSAT) - Or (PSAT, 0x00000000, PSAT) - } -} - -Device (PWM1) -{ - Name (_HID, "80860F09") - Name (_UID, 1) - Name (_DDN, "PWM Controller #1") - - Name (RBUF, ResourceTemplate() - { - Memory32Fixed (ReadWrite, 0, 0x1000, BAR0) - }) - - Method (_CRS) - { - CreateDwordField (^RBUF, ^BAR0._BAS, RBAS) - Store (\SAB0, RBAS) - Return (^RBUF) - } - - Method (_STA) - { - If (LEqual (\SAEN, 1)) { - Return (0xF) - } Else { - Return (0x0) - } - } -} - -Device (PWM2) -{ - Name (_HID, "80860F09") - Name (_UID, 2) - Name (_DDN, "PWM Controller #2") - - Name (RBUF, ResourceTemplate() - { - Memory32Fixed (ReadWrite, 0, 0x1000, BAR0) - }) - - Method (_CRS) - { - CreateDwordField (^RBUF, ^BAR0._BAS, RBAS) - Store (\SBB0, RBAS) - Return (^RBUF) - } - - Method (_STA) - { - If (LEqual (\SBEN, 1)) { - Return (0xF) - } Else { - Return (0x0) - } - } -} - -Device (UAR1) -{ - Name (_HID, "80860F0A") - Name (_UID, 1) - Name (_DDN, "HS-UART Controller #1") - - Name (RBUF, ResourceTemplate() - { - Memory32Fixed (ReadWrite, 0, 0x1000, BAR0) - Interrupt (ResourceConsumer, Level, ActiveLow, Exclusive,,,) - { - LPSS_HSUART1_IRQ - } - FixedDMA (0x2, 0x2, Width32Bit, ) - FixedDMA (0x3, 0x3, Width32Bit, ) - }) - - Method (_CRS) - { - CreateDwordField (^RBUF, ^BAR0._BAS, RBAS) - Store (\SCB0, RBAS) - Return (^RBUF) - } - - Method (_STA) - { - If (LEqual (\SCEN, 1)) { - Return (0xF) - } Else { - Return (0x0) - } - } - - OperationRegion (KEYS, SystemMemory, SCB1, 0x100) - Field (KEYS, DWordAcc, NoLock, WriteAsZeros) - { - Offset (0x84), - PSAT, 32, - } - - Method (_PS3) - { - Or (PSAT, 0x00000003, PSAT) - Or (PSAT, 0x00000000, PSAT) - } - - Method (_PS0) - { - And (PSAT, 0xfffffffc, PSAT) - Or (PSAT, 0x00000000, PSAT) - } -} - -Device (UAR2) -{ - Name (_HID, "80860F0A") - Name (_UID, 2) - Name (_DDN, "HS-UART Controller #2") - - Name (RBUF, ResourceTemplate() - { - Memory32Fixed (ReadWrite, 0, 0x1000, BAR0) - Interrupt (ResourceConsumer, Level, ActiveLow, Exclusive,,,) - { - LPSS_HSUART2_IRQ - } - FixedDMA (0x4, 0x4, Width32Bit, ) - FixedDMA (0x5, 0x5, Width32Bit, ) - }) - - Method (_CRS) - { - CreateDwordField (^RBUF, ^BAR0._BAS, RBAS) - Store (\SDB0, RBAS) - Return (^RBUF) - } - - Method (_STA) - { - If (LEqual (\SDEN, 1)) { - Return (0xF) - } Else { - Return (0x0) - } - } - - OperationRegion (KEYS, SystemMemory, SDB1, 0x100) - Field (KEYS, DWordAcc, NoLock, WriteAsZeros) - { - Offset (0x84), - PSAT, 32, - } - - Method (_PS3) - { - Or (PSAT, 0x00000003, PSAT) - Or (PSAT, 0x00000000, PSAT) - } - - Method (_PS0) - { - And (PSAT, 0xfffffffc, PSAT) - Or (PSAT, 0x00000000, PSAT) - } -} diff --git a/src/soc/intel/fsp_baytrail/acpi/platform.asl b/src/soc/intel/fsp_baytrail/acpi/platform.asl deleted file mode 100644 index 01be3514fd..0000000000 --- a/src/soc/intel/fsp_baytrail/acpi/platform.asl +++ /dev/null @@ -1,32 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007-2009 coresystems GmbH - * Copyright (C) 2012 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include - -/* The _PTS method (Prepare To Sleep) is called before the OS is - * entering a sleep state. The sleep state number is passed in Arg0 - */ - -Method(_PTS,1) -{ -} - -/* The _WAK method is called on system wakeup */ - -Method(_WAK,1) -{ - Return(Package(){0,0}) -} diff --git a/src/soc/intel/fsp_baytrail/acpi/scc.asl b/src/soc/intel/fsp_baytrail/acpi/scc.asl deleted file mode 100644 index c26511c751..0000000000 --- a/src/soc/intel/fsp_baytrail/acpi/scc.asl +++ /dev/null @@ -1,182 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2013 Google Inc. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -Device (EMMC) -{ - Name (_HID, "80860F14") - Name (_CID, "PNP0D40") - Name (_UID, 1) - Name (_DDN, "eMMC Controller 4.5") - - Name (RBUF, ResourceTemplate() - { - Memory32Fixed (ReadWrite, 0, 0x1000, BAR0) - Interrupt (ResourceConsumer, Level, ActiveLow, Exclusive,,,) - { - SCC_EMMC_IRQ - } - }) - - Method (_CRS) - { - CreateDwordField (^RBUF, ^BAR0._BAS, RBAS) - Store (\C0B0, RBAS) - Return (^RBUF) - } - - Method (_STA) - { - If (LEqual (\C0EN, 1)) { - Return (0xF) - } Else { - Return (0x0) - } - } - - OperationRegion (KEYS, SystemMemory, C0B1, 0x100) - Field (KEYS, DWordAcc, NoLock, WriteAsZeros) - { - Offset (0x84), - PSAT, 32, - } - - Method (_PS3) - { - Or (PSAT, 0x00000003, PSAT) - Or (PSAT, 0x00000000, PSAT) - } - - Method (_PS0) - { - And (PSAT, 0xfffffffc, PSAT) - Or (PSAT, 0x00000000, PSAT) - } - - Device (EM45) - { - /* Slot 0, Function 8 */ - Name (_ADR, 0x8) - - Method (_RMV, 0, NotSerialized) - { - Return (0) - } - } -} - -Device (SDIO) -{ - Name (_HID, "INT33BB") - Name (_CID, "PNP0D40") - Name (_UID, 2) - Name (_DDN, "SDIO Controller") - - Name (RBUF, ResourceTemplate() - { - Memory32Fixed (ReadWrite, 0, 0x1000, BAR0) - Interrupt (ResourceConsumer, Level, ActiveLow, Exclusive,,,) - { - SCC_SDIO_IRQ - } - }) - - Method (_CRS) - { - CreateDwordField (^RBUF, ^BAR0._BAS, RBAS) - Store (\C1B0, RBAS) - Return (^RBUF) - } - - Method (_STA) - { - If (LEqual (\C1EN, 1)) { - Return (0xF) - } Else { - Return (0x0) - } - } - - OperationRegion (KEYS, SystemMemory, C1B1, 0x100) - Field (KEYS, DWordAcc, NoLock, WriteAsZeros) - { - Offset (0x84), - PSAT, 32, - } - - Method (_PS3) - { - Or (PSAT, 0x00000003, PSAT) - Or (PSAT, 0x00000000, PSAT) - } - - Method (_PS0) - { - And (PSAT, 0xfffffffc, PSAT) - Or (PSAT, 0x00000000, PSAT) - } -} - -Device (SDCD) -{ - Name (_HID, "80860F16") - Name (_CID, "PNP0D40") - Name (_UID, 3) - Name (_DDN, "SD Card Controller") - - Name (RBUF, ResourceTemplate() - { - Memory32Fixed (ReadWrite, 0, 0x1000, BAR0) - Interrupt (ResourceConsumer, Level, ActiveLow, Exclusive,,,) - { - SCC_SD_IRQ - } - }) - - Method (_CRS) - { - CreateDwordField (^RBUF, ^BAR0._BAS, RBAS) - Store (\C2B0, RBAS) - Return (^RBUF) - } - - Method (_STA) - { - If (LEqual (\C2EN, 1)) { - Return (0xF) - } Else { - Return (0x0) - } - } - - OperationRegion (KEYS, SystemMemory, C2B1, 0x100) - Field (KEYS, DWordAcc, NoLock, WriteAsZeros) - { - Offset (0x84), - PSAT, 32, - } - - Method (_PS3) - { - Or (PSAT, 0x00000003, PSAT) - Or (PSAT, 0x00000000, PSAT) - } - - Method (_PS0) - { - And (PSAT, 0xfffffffc, PSAT) - Or (PSAT, 0x00000000, PSAT) - } -} diff --git a/src/soc/intel/fsp_baytrail/acpi/southcluster.asl b/src/soc/intel/fsp_baytrail/acpi/southcluster.asl deleted file mode 100644 index ef4523b004..0000000000 --- a/src/soc/intel/fsp_baytrail/acpi/southcluster.asl +++ /dev/null @@ -1,294 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2013 Google Inc. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include "../include/soc/baytrail.h" - -Scope(\) -{ - // IO-Trap at 0x800. This is the ACPI->SMI communication interface. - - OperationRegion(IO_T, SystemIO, 0x800, 0x10) - Field(IO_T, ByteAcc, NoLock, Preserve) - { - Offset(0x8), - TRP0, 8 // IO-Trap at 0x808 - } - - // Intel Legacy Block - OperationRegion(ILBS, SystemMemory, ILB_BASE_ADDRESS, ILB_BASE_SIZE) - Field (ILBS, AnyAcc, NoLock, Preserve) - { - Offset (0x8), - PRTA, 8, - PRTB, 8, - PRTC, 8, - PRTD, 8, - PRTE, 8, - PRTF, 8, - PRTG, 8, - PRTH, 8, - } -} - -Name(_HID,EISAID("PNP0A08")) // PCIe -Name(_CID,EISAID("PNP0A03")) // PCI - -Name(_BBN, 0) - -Name (MCRS, ResourceTemplate() -{ - // Bus Numbers - WordBusNumber (ResourceProducer, MinFixed, MaxFixed, PosDecode, - 0x0000, 0x0000, 0x00ff, 0x0000, 0x0100,,, PB00) - - // IO Region 0 - DWordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, - 0x0000, 0x0000, 0x0cf7, 0x0000, 0x0cf8,,, PI00) - - // PCI Config Space - Io (Decode16, 0x0cf8, 0x0cf8, 0x0001, 0x0008) - - // IO Region 1 - DWordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, - 0x0000, 0x0d00, 0xffff, 0x0000, 0xf300,,, PI01) - - // VGA memory (0xa0000-0xbffff) - DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, - Cacheable, ReadWrite, - 0x00000000, 0x000a0000, 0x000bffff, 0x00000000, - 0x00020000,,, ASEG) - - // OPROM reserved (0xc0000-0xc3fff) - DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, - Cacheable, ReadWrite, - 0x00000000, 0x000c0000, 0x000c3fff, 0x00000000, - 0x00004000,,, OPR0) - - // OPROM reserved (0xc4000-0xc7fff) - DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, - Cacheable, ReadWrite, - 0x00000000, 0x000c4000, 0x000c7fff, 0x00000000, - 0x00004000,,, OPR1) - - // OPROM reserved (0xc8000-0xcbfff) - DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, - Cacheable, ReadWrite, - 0x00000000, 0x000c8000, 0x000cbfff, 0x00000000, - 0x00004000,,, OPR2) - - // OPROM reserved (0xcc000-0xcffff) - DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, - Cacheable, ReadWrite, - 0x00000000, 0x000cc000, 0x000cffff, 0x00000000, - 0x00004000,,, OPR3) - - // OPROM reserved (0xd0000-0xd3fff) - DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, - Cacheable, ReadWrite, - 0x00000000, 0x000d0000, 0x000d3fff, 0x00000000, - 0x00004000,,, OPR4) - - // OPROM reserved (0xd4000-0xd7fff) - DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, - Cacheable, ReadWrite, - 0x00000000, 0x000d4000, 0x000d7fff, 0x00000000, - 0x00004000,,, OPR5) - - // OPROM reserved (0xd8000-0xdbfff) - DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, - Cacheable, ReadWrite, - 0x00000000, 0x000d8000, 0x000dbfff, 0x00000000, - 0x00004000,,, OPR6) - - // OPROM reserved (0xdc000-0xdffff) - DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, - Cacheable, ReadWrite, - 0x00000000, 0x000dc000, 0x000dffff, 0x00000000, - 0x00004000,,, OPR7) - - // BIOS Extension (0xe0000-0xe3fff) - DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, - Cacheable, ReadWrite, - 0x00000000, 0x000e0000, 0x000e3fff, 0x00000000, - 0x00004000,,, ESG0) - - // BIOS Extension (0xe4000-0xe7fff) - DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, - Cacheable, ReadWrite, - 0x00000000, 0x000e4000, 0x000e7fff, 0x00000000, - 0x00004000,,, ESG1) - - // BIOS Extension (0xe8000-0xebfff) - DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, - Cacheable, ReadWrite, - 0x00000000, 0x000e8000, 0x000ebfff, 0x00000000, - 0x00004000,,, ESG2) - - // BIOS Extension (0xec000-0xeffff) - DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, - Cacheable, ReadWrite, - 0x00000000, 0x000ec000, 0x000effff, 0x00000000, - 0x00004000,,, ESG3) - - // System BIOS (0xf0000-0xfffff) - DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, - Cacheable, ReadWrite, - 0x00000000, 0x000f0000, 0x000fffff, 0x00000000, - 0x00010000,,, FSEG) - - // PCI Memory Region (Top of memory-CONFIG_MMCONF_BASE_ADDRESS) - DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, - Cacheable, ReadWrite, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000,,, PMEM) - - // TPM Area (0xfed40000-0xfed44fff) - DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, - Cacheable, ReadWrite, - 0x00000000, 0xfed40000, 0xfed44fff, 0x00000000, - 0x00005000,,, TPMR) - - // High PCI Memory Region - QwordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, - Cacheable, ReadWrite, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000,,, UMEM) -}) - -Method (_CRS, 0, Serialized) -{ - // Update PCI resource area - CreateDwordField(MCRS, ^PMEM._MIN, PMIN) - CreateDwordField(MCRS, ^PMEM._MAX, PMAX) - CreateDwordField(MCRS, ^PMEM._LEN, PLEN) - - // TOLM is BMBOUND accessible from IOSF so is saved in NVS - Store (\TOLM, PMIN) - Store (Subtract(CONFIG_MMCONF_BASE_ADDRESS, 1), PMAX) - Add (Subtract (PMAX, PMIN), 1, PLEN) - - // Update High PCI resource area - CreateQwordField(MCRS, ^UMEM._MIN, UMIN) - CreateQwordField(MCRS, ^UMEM._MAX, UMAX) - CreateQwordField(MCRS, ^UMEM._LEN, ULEN) - - Store(0x40000000 * 48, UMIN) // Set base address to 48GB - Store(0x40000000 * 16, ULEN) // Allocate 16GB for PCI space - Add(UMIN, Subtract(ULEN, 1), UMAX) - - Return (MCRS) -} - -/* Device Resource Consumption */ -Device (PDRC) -{ - Name (_HID, EISAID("PNP0C02")) - Name (_UID, 1) - - Name (PDRS, ResourceTemplate() { - Memory32Fixed(ReadWrite, ABORT_BASE_ADDRESS, ABORT_BASE_SIZE) - Memory32Fixed(ReadWrite, MCFG_BASE_ADDRESS, MCFG_BASE_SIZE) - Memory32Fixed(ReadWrite, PMC_BASE_ADDRESS, PMC_BASE_SIZE) - Memory32Fixed(ReadWrite, ILB_BASE_ADDRESS, ILB_BASE_SIZE) - Memory32Fixed(ReadWrite, SPI_BASE_ADDRESS, SPI_BASE_SIZE) - Memory32Fixed(ReadWrite, MPHY_BASE_ADDRESS, MPHY_BASE_SIZE) - Memory32Fixed(ReadWrite, PUNIT_BASE_ADDRESS, PUNIT_BASE_SIZE) - Memory32Fixed(ReadWrite, RCBA_BASE_ADDRESS, RCBA_BASE_SIZE) - }) - - // Current Resource Settings - Method (_CRS, 0, Serialized) - { - Return(PDRS) - } -} - -Method (_OSC, 4) -{ - /* Check for proper GUID */ - If (LEqual (Arg0, ToUUID("33DB4D5B-1FF7-401C-9657-7441C03DD766"))) - { - /* Let OS control everything */ - Return (Arg3) - } - Else - { - /* Unrecognized UUID */ - CreateDWordField (Arg3, 0, CDW1) - Or (CDW1, 4, CDW1) - Return (Arg3) - } -} - -/* IOSF MBI Interface for kernel access */ -Device (IOSF) -{ - Name (_HID, "INT33BD") - Name (_CID, "INT33BD") - Name (_UID, 1) - - Name (RBUF, ResourceTemplate () - { - /* MCR / MDR / MCRX */ - Memory32Fixed (ReadWrite, 0, 12, RBAR) - }) - - Method (_CRS) - { - CreateDwordField (^RBUF, ^RBAR._BAS, RBAS) - Store (Add (MCFG_BASE_ADDRESS, 0xD0), RBAS) - Return (^RBUF) - } -} - -// LPC Bridge 0:1f.0 -#include "lpc.asl" - -#if INCLUDE_EHCI -// USB EHCI 0:1d.0 -#include "usb.asl" -#endif - -#if INCLUDE_XHCI -// USB XHCI 0:14.0 -#include "xhci.asl" -#endif - -// IRQ routing for each PCI device -#include "irqroute.asl" - -Scope (\_SB) -{ - // GPIO Devices - #include "gpio.asl" - -#if INCLUDE_LPSS - // LPSS Devices - #include "lpss.asl" -#endif - -#if INCLUDE_SCC - // SCC Devices - #include "scc.asl" -#endif - -#if INCLUDE_LPE - // LPE Device - #include "lpe.asl" -#endif -} diff --git a/src/soc/intel/fsp_baytrail/acpi/usb.asl b/src/soc/intel/fsp_baytrail/acpi/usb.asl deleted file mode 100644 index c60bfcec46..0000000000 --- a/src/soc/intel/fsp_baytrail/acpi/usb.asl +++ /dev/null @@ -1,48 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007-2009 coresystems GmbH - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -/* Intel Baytrail USB support */ - -// EHCI Controller 0:1d.0 - -Device (EHC1) -{ - Name(_ADR, 0x001d0000) - - Name (_PRW, Package(){ 13, 4 }) // Power Resources for Wake - - // Leave USB ports on for to allow Wake from USB - - Method(_S3D,0) // Highest D State in S3 State - { - Return (2) - } - - Method(_S4D,0) // Highest D State in S4 State - { - Return (2) - } - - Device (HUB7) - { - Name (_ADR, 0x00000000) - - Device (PRT1) { Name (_ADR, 1) } // USB Port 0 - Device (PRT2) { Name (_ADR, 2) } // USB Port 1 - Device (PRT3) { Name (_ADR, 3) } // USB Port 2 - Device (PRT4) { Name (_ADR, 4) } // USB Port 3 - } -} diff --git a/src/soc/intel/fsp_baytrail/acpi/xhci.asl b/src/soc/intel/fsp_baytrail/acpi/xhci.asl deleted file mode 100644 index dbd34474f8..0000000000 --- a/src/soc/intel/fsp_baytrail/acpi/xhci.asl +++ /dev/null @@ -1,31 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2014 Google Inc. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -Device (XHCI) -{ - Name (_ADR, 0x00140000) - Name (_PRW, Package () { 0x0d, 3 }) - Name (_S3D, 3) /* Highest D state in S3 state */ - - Device (RHUB) - { - Name (_ADR, 0x00000000) - Device (PRT1) { Name (_ADR, 1) } - Device (PRT2) { Name (_ADR, 2) } - Device (PRT3) { Name (_ADR, 3) } - Device (PRT4) { Name (_ADR, 4) } - } -} diff --git a/src/soc/intel/fsp_baytrail/bootblock/bootblock.c b/src/soc/intel/fsp_baytrail/bootblock/bootblock.c deleted file mode 100644 index 5351a0162f..0000000000 --- a/src/soc/intel/fsp_baytrail/bootblock/bootblock.c +++ /dev/null @@ -1,126 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2013 Google, Inc. - * Copyright (C) 2013-2014 Sage Electronic Engineering LLC. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -/* - * check for a warm reset and do a hard reset instead. - */ -static void check_for_warm_reset(void) -{ - - /* - * Check if INIT# is asserted by port 0xCF9 and whether RCBA has been set. - * If either is true, then this is a warm reset so execute a Hard Reset - */ - if ((inb(0xcf9) == 0x04) || - (pci_io_read_config32(LPC_BDF, RCBA) & RCBA_ENABLE)) { - outb(0x00, 0xcf9); - outb(0x06, 0xcf9); - } -} - -static void set_var_mtrr(int reg, uint32_t base, uint32_t size, int type) -{ - msr_t basem, maskm; - basem.lo = base | type; - basem.hi = 0; - wrmsr(MTRR_PHYS_BASE(reg), basem); - maskm.lo = ~(size - 1) | MTRR_PHYS_MASK_VALID; - maskm.hi = (1 << (CONFIG_CPU_ADDR_BITS - 32)) - 1; - wrmsr(MTRR_PHYS_MASK(reg), maskm); -} - -/* - * Enable Prefetching and Caching. - */ -static void enable_spi_prefetch(void) -{ - u32 *bcr = (u32 *)(SPI_BASE_ADDRESS + BCR); - /* Enable caching and prefetching in the SPI controller. */ - write32(bcr, (read32(bcr) & ~SRC_MASK) | SRC_CACHE_PREFETCH); -} - -static void enable_rom_caching(void) -{ - msr_t msr; - - disable_cache(); - set_var_mtrr(1, CACHE_ROM_BASE, CACHE_ROM_SIZE, MTRR_TYPE_WRPROT); - enable_cache(); - - /* Enable Variable MTRRs */ - msr.hi = 0x00000000; - msr.lo = 0x00000800; - wrmsr(MTRR_DEF_TYPE_MSR, msr); -} - -static void setup_mmconfig(void) -{ - uint32_t reg; - - /* Set up the MMCONF range. The register lives in the BUNIT. The - * IO variant of the config access needs to be used initially to - * properly configure as the IOSF access registers live in PCI - * config space. */ - reg = 0; - /* Clear the extended register. */ - pci_io_write_config32(IOSF_PCI_DEV, MCRX_REG, reg); - reg = CONFIG_MMCONF_BASE_ADDRESS | 1; - pci_io_write_config32(IOSF_PCI_DEV, MDR_REG, reg); - reg = IOSF_OPCODE(IOSF_OP_WRITE_BUNIT) | IOSF_PORT(IOSF_PORT_BUNIT) | - IOSF_REG(BUNIT_MMCONF_REG) | IOSF_BYTE_EN; - pci_io_write_config32(IOSF_PCI_DEV, MCR_REG, reg); -} - -static const uint8_t lpc_pads[12] = { - 70, 68, 67, 66, 69, 71, 65, 72, 86, 90, 88, 92, -}; - -static void set_up_lpc_pads(void) -{ - uint32_t reg = IO_BASE_ADDRESS | SET_BAR_ENABLE; - pci_write_config32(LPC_BDF, IOBASE, reg); - - for (reg = 0; reg < 12; reg++) - score_select_func(lpc_pads[reg], 1); -} - -static void bootblock_cpu_init(void) -{ - check_for_warm_reset(); - - /* Load microcode before any caching. */ - intel_update_microcode_from_cbfs(); - - /* Allow memory-mapped PCI config access. */ - setup_mmconfig(); - enable_rom_caching(); - enable_spi_prefetch(); - set_up_lpc_pads(); -} diff --git a/src/soc/intel/fsp_baytrail/chip.c b/src/soc/intel/fsp_baytrail/chip.c deleted file mode 100644 index 3ca26add30..0000000000 --- a/src/soc/intel/fsp_baytrail/chip.c +++ /dev/null @@ -1,78 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2013 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include -#include -#include -#include -#include "chip.h" - -static void pci_domain_set_resources(struct device *dev) -{ - assign_resources(dev->link_list); -} - -static struct device_operations pci_domain_ops = { - .read_resources = pci_domain_read_resources, - .set_resources = pci_domain_set_resources, - .enable_resources = NULL, - .init = NULL, - .scan_bus = pci_domain_scan_bus, -}; - -static struct device_operations cpu_bus_ops = { - .read_resources = DEVICE_NOOP, - .set_resources = DEVICE_NOOP, - .enable_resources = DEVICE_NOOP, - .init = baytrail_init_cpus, - .scan_bus = NULL, -}; - -static void enable_dev(struct device *dev) -{ - printk(BIOS_DEBUG, "enable_dev(%s, %d)\n", - dev_name(dev), dev->path.type); - - /* Set the operations if it is a special bus type */ - if (dev->path.type == DEVICE_PATH_DOMAIN) { - dev->ops = &pci_domain_ops; - } else if (dev->path.type == DEVICE_PATH_CPU_CLUSTER) { - dev->ops = &cpu_bus_ops; - } else if (dev->path.type == DEVICE_PATH_PCI) { - /* Handle south cluster enablement. */ - if (PCI_SLOT(dev->path.pci.devfn) > GFX_DEV && - (dev->ops == NULL || dev->ops->enable == NULL)) { - southcluster_enable_dev(dev); - } - } -} - -/* Called at BS_DEV_INIT_CHIPS time -- very early. Just after BS_PRE_DEVICE. */ -static void soc_init(void *chip_info) -{ - baytrail_init_pre_device(); -} - -struct chip_operations soc_intel_fsp_baytrail_ops = { - CHIP_NAME("Intel BayTrail SoC") - .enable_dev = enable_dev, - .init = soc_init, -}; - -struct pci_operations soc_pci_ops = { - .set_subsystem = &pci_dev_set_subsystem, -}; diff --git a/src/soc/intel/fsp_baytrail/chip.h b/src/soc/intel/fsp_baytrail/chip.h deleted file mode 100644 index e3167885b2..0000000000 --- a/src/soc/intel/fsp_baytrail/chip.h +++ /dev/null @@ -1,360 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2013 Google Inc. - * Copyright (C) 2013-2014 Sage Electronic Engineering, LLC. - * Copyright (C) 2014-2015 Intel Corporation - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef _FSP_BAYTRAIL_CHIP_H_ -#define _FSP_BAYTRAIL_CHIP_H_ - -#include -#include -#include - -/* The devicetree parser expects chip.h to reside directly in the path - * specified by the devicetree. */ - -struct soc_intel_fsp_baytrail_config { - -/* ***** UPD Configuration ***** */ - - /* Spd addresses */ - uint8_t PcdMrcInitSPDAddr1; - uint8_t PcdMrcInitSPDAddr2; - #define SPD_ADDR_DEFAULT UPD_SPD_ADDR_DEFAULT - #define SPD_ADDR_DISABLED UPD_SPD_ADDR_DISABLED - - /* SataMode - * NOTE: These are offset by 1 to set 0 as "use default". This is so that - * if the register value is not set in the devicetree.cb file, the default - * value gets used. This is fixed up in the chipset_fsp_util.c code. - * - * 0x0 "IDE" - * 0x1 "AHCI" - */ - uint8_t PcdSataMode; - #define SATA_MODE_DEFAULT UPD_DEFAULT - #define SATA_MODE_IDE INCREMENT_FOR_DEFAULT(0) - #define SATA_MODE_AHCI INCREMENT_FOR_DEFAULT(1) - - /* - * MrcInitMmioSize - * 0x400, "1.0 GB"s - * 0x600, "1.5 GB" - * 0x800, "2.0 GB" - */ - uint16_t PcdMrcInitMmioSize; - #define MMIO_SIZE_DEFAULT UPD_DEFAULT - #define MMIO_SIZE_1_0_GB INCREMENT_FOR_DEFAULT(0x400) - #define MMIO_SIZE_1_5_GB INCREMENT_FOR_DEFAULT(0x600) - #define MMIO_SIZE_2_0_GB INCREMENT_FOR_DEFAULT(0x800) - - /* - * eMMCBootMode - * NOTE: These are offset by 1 to set 0 as "use default". This is so that - * if the register value is not set in the devicetree.cb file, the default - * value gets used. This is fixed up in the chipset_fsp_util.c code - * - * 0x0 "Disabled" - * 0x1 "Auto" - * 0x2 "eMMC 4.1" - * 0x3 "eMMC 4.5" - */ - uint8_t PcdeMMCBootMode; - #define EMMC_USE_DEFAULT UPD_DEFAULT - #define EMMC_DISABLED UPD_DISABLE - #define EMMC_AUTO INCREMENT_FOR_DEFAULT(1) - #define EMMC_4_1 INCREMENT_FOR_DEFAULT(2) - #define EMMC_4_5 INCREMENT_FOR_DEFAULT(3) - #define EMMC_FOLLOWS_DEVICETREE UPD_USE_DEVICETREE - - /* - * IgdDvmt50PreAlloc - * 0x01, "32 MB" - * 0x02, "64 MB" - * 0x03, "96 MB" - * 0x04, "128 MB" - * 0x05, "160 MB" - * 0x06, "192 MB" - * 0x07, "224 MB" - * 0x08, "256 MB" - * 0x09, "288 MB" - * 0x0A, "320 MB" - * 0x0B, "352 MB" - * 0x0C, "384 MB" - * 0x0D, "416 MB" - * 0x0E, "448 MB" - * 0x0F, "480 MB" - * 0x10, "512 MB" - */ - uint8_t PcdIgdDvmt50PreAlloc; - #define IGD_MEMSIZE_DEFAULT UPD_DEFAULT - #define IGD_MEMSIZE_32MB INCREMENT_FOR_DEFAULT(0x01) - #define IGD_MEMSIZE_64MB INCREMENT_FOR_DEFAULT(0x02) - #define IGD_MEMSIZE_96MB INCREMENT_FOR_DEFAULT(0x03) - #define IGD_MEMSIZE_128MB INCREMENT_FOR_DEFAULT(0x04) - #define IGD_MEMSIZE_160MB INCREMENT_FOR_DEFAULT(0x05) - #define IGD_MEMSIZE_192MB INCREMENT_FOR_DEFAULT(0x06) - #define IGD_MEMSIZE_224MB INCREMENT_FOR_DEFAULT(0x07) - #define IGD_MEMSIZE_256MB INCREMENT_FOR_DEFAULT(0x08) - #define IGD_MEMSIZE_288MB INCREMENT_FOR_DEFAULT(0x09) - #define IGD_MEMSIZE_320MB INCREMENT_FOR_DEFAULT(0x0A) - #define IGD_MEMSIZE_352MB INCREMENT_FOR_DEFAULT(0x0B) - #define IGD_MEMSIZE_384MB INCREMENT_FOR_DEFAULT(0x0C) - #define IGD_MEMSIZE_416MB INCREMENT_FOR_DEFAULT(0x0D) - #define IGD_MEMSIZE_448MB INCREMENT_FOR_DEFAULT(0x0E) - #define IGD_MEMSIZE_480MB INCREMENT_FOR_DEFAULT(0x0F) - #define IGD_MEMSIZE_512MB INCREMENT_FOR_DEFAULT(0x10) - #define IGD_MEMSIZE_MULTIPLIER 32 - - /* - * Selection 0x1 , "128 MB" - * Selection 0x2 , "256 MB" - * Selection 0x3 , "512 MB" - */ - uint8_t PcdApertureSize; - #define APERTURE_SIZE_DEFAULT UPD_DEFAULT - #define APERTURE_SIZE_128MB INCREMENT_FOR_DEFAULT(1) - #define APERTURE_SIZE_256MB INCREMENT_FOR_DEFAULT(2) - #define APERTURE_SIZE_512MB INCREMENT_FOR_DEFAULT(3) - #define APERTURE_SIZE_BASE 64 - - /* - * Selection 0x1 , "1 MB" - * Selection 0x2 , "2 MB" - */ - uint8_t PcdGttSize; - #define GTT_SIZE_DEFAULT UPD_DEFAULT - #define GTT_SIZE_1MB INCREMENT_FOR_DEFAULT(1) - #define GTT_SIZE_2MB INCREMENT_FOR_DEFAULT(2) - - /* - * Enable PCI Mode for LPSS SIO devices. - * If disabled, LPSS SIO devices will run in ACPI mode. - */ - uint8_t PcdLpssSioEnablePciMode; - #define LPSS_PCI_MODE_DEFAULT UPD_DEFAULT - #define LPSS_PCI_MODE_DISABLE UPD_DISABLE - #define LPSS_PCI_MODE_ENABLE UPD_ENABLE - - /* modifiers for various enables */ - uint8_t AzaliaAutoEnable; - #define AZALIA_FOLLOWS_DEVICETREE UPD_USE_DEVICETREE - #define AZALIA_FSP_AUTO_ENABLE UPD_ENABLE - - uint8_t LpeAcpiModeEnable; - #define LPE_ACPI_MODE_DISABLED UPD_DISABLE - #define LPE_ACPI_MODE_ENABLED UPD_ENABLE - - uint32_t SerialDebugPortAddress; - #define SerialDebugPortAddress_DEFAULT UPD_DEFAULT - - uint8_t SerialDebugPortType; - #define SERIAL_DEBUG_PORT_DEFAULT UPD_DEFAULT - #define SERIAL_DEBUG_PORT_TYPE_NONE INCREMENT_FOR_DEFAULT(0) - #define SERIAL_DEBUG_PORT_TYPE_IO INCREMENT_FOR_DEFAULT(1) - #define SERIAL_DEBUG_PORT_TYPE_MMIO INCREMENT_FOR_DEFAULT(2) - - uint8_t PcdMrcDebugMsg; - #define MRC_DEBUG_MSG_DEFAULT UPD_DEFAULT - #define MRC_DEBUG_MSG_DISABLE UPD_DISABLE - #define MRC_DEBUG_MSG_ENABLE UPD_ENABLE - - uint8_t PcdSccEnablePciMode; - #define SCC_PCI_MODE_DEFAULT UPD_DEFAULT - #define SCC_PCI_MODE_DISABLE UPD_DISABLE - #define SCC_PCI_MODE_ENABLE UPD_ENABLE - - uint8_t IgdRenderStandby; - #define IGD_RENDER_STANDBY_DEFAULT UPD_DEFAULT - #define IGD_RENDER_STANDBY_DISABLE UPD_DISABLE - #define IGD_RENDER_STANDBY_ENABLE UPD_ENABLE - - uint8_t TxeUmaEnable; - #define TXE_UMA_DEFAULT UPD_DEFAULT - #define TXE_UMA_DISABLE UPD_DISABLE - #define TXE_UMA_ENABLE UPD_ENABLE - - /* - * PcdOsSelection - * Selection 0x1 , "Android" - * Selection 0x4 , "Linux OS" - */ - uint8_t PcdOsSelection; - #define OS_SELECTION_DEFAULT UPD_DEFAULT - #define OS_SELECTION_ANDROID INCREMENT_FOR_DEFAULT(1) - #define OS_SELECTION_LINUX INCREMENT_FOR_DEFAULT(4) - - /* PcdEMMC45DDR50Enabled */ - uint8_t PcdEMMC45DDR50Enabled; - #define EMMC45_DDR50_DEFAULT UPD_DEFAULT - #define EMMC45_DDR50_DISABLE UPD_DISABLE - #define EMMC45_DDR50_ENABLE UPD_ENABLE - - /* PcdEMMC45HS200Enabled */ - uint8_t PcdEMMC45HS200Enabled; - #define EMMC45_HS200_DEFAULT UPD_DEFAULT - #define EMMC45_HS200_DISABLE UPD_DISABLE - #define EMMC45_HS200_ENABLE UPD_ENABLE - - /* PcdEMMC45RetuneTimerValue */ - uint8_t PcdEMMC45RetuneTimerValue; - #define EMMC45_RETURN_TIMER_DEFAULT UPD_DEFAULT - - /* PcdEnableIgd */ - uint8_t PcdEnableIgd; - #define ENABLE_IGD_DEFAULT UPD_DEFAULT - #define ENABLE_IGD_DISABLE UPD_DISABLE - #define ENABLE_IGD_ENABLE UPD_ENABLE - - /* AutoSelfRefreshEnable */ - uint8_t AutoSelfRefreshEnable; - #define AUTO_SELF_REFRESH_DEFAULT UPD_DEFAULT - #define AUTO_SELF_REFRESH_DISABLE UPD_DISABLE - #define AUTO_SELF_REFRESH_ENABLE UPD_ENABLE - - /* APTaskTimeoutCnt */ - uint16_t APTaskTimeoutCnt; - #define AP_TASK_TIMEOUT_CNT_DEFAULT UPD_DEFAULT - - /* Memory down data */ - uint8_t EnableMemoryDown; - #define MEMORY_DOWN_DEFAULT UPD_DEFAULT - #define MEMORY_DOWN_DISABLE UPD_DISABLE - #define MEMORY_DOWN_ENABLE UPD_ENABLE - - /* - * PcdDRAMSpeed - * Selection 0x0 , "800 MHz" - * Selection 0x1 , "1066 MHz" - * Selection 0x2 , "1333 MHz" - * Selection 0x3 , "1600 MHz" - */ - uint8_t DRAMSpeed; - #define DRAM_SPEED_DEFAULT UPD_DEFAULT - #define DRAM_SPEED_800MHZ INCREMENT_FOR_DEFAULT(0) - #define DRAM_SPEED_1066MHZ INCREMENT_FOR_DEFAULT(1) - #define DRAM_SPEED_1333MHZ INCREMENT_FOR_DEFAULT(2) - #define DRAM_SPEED_1600MHZ INCREMENT_FOR_DEFAULT(3) - - /* - * PcdDRAMType - * Selection 0x0 , "DDR3" - * Selection 0x1 , "DDR3L" - * Selection 0x2 , "DDR3U" - * Selection 0x4 , "LPDDR2" - * Selection 0x5 , "LPDDR3" - * Selection 0x6 , "DDR4" - */ - uint8_t DRAMType; - #define DRAM_TYPE_DEFAULT UPD_DEFAULT - #define DRAM_TYPE_DDR3 INCREMENT_FOR_DEFAULT(0) - #define DRAM_TYPE_DDR3L INCREMENT_FOR_DEFAULT(1) - - uint8_t DIMM0Enable; - #define DIMM0_ENABLE_DEFAULT UPD_DEFAULT - #define DIMM0_DISABLE UPD_DISABLE - #define DIMM0_ENABLE UPD_ENABLE - - uint8_t DIMM1Enable; - #define DIMM1_ENABLE_DEFAULT UPD_DEFAULT - #define DIMM1_DISABLE UPD_DISABLE - #define DIMM1_ENABLE UPD_ENABLE - - /* - * PcdDIMMDWidth - * Selection 0x0 , "x8" - * Selection 0x1 , "x16" - * Selection 0x2 , "x32" - */ - uint8_t DIMMDWidth; - #define DIMM_DWIDTH_DEFAULT UPD_DEFAULT - #define DIMM_DWIDTH_X8 INCREMENT_FOR_DEFAULT(0) - #define DIMM_DWIDTH_X16 INCREMENT_FOR_DEFAULT(1) - #define DIMM_DWIDTH_X32 INCREMENT_FOR_DEFAULT(2) - - /* - * PcdDIMMDensity - * Selection 0x0 , "1 Gbit" - * Selection 0x1 , "2 Gbit" - * Selection 0x2 , "4 Gbit" - * Selection 0x3 , "8 Gbit" - */ - uint8_t DIMMDensity; - #define DIMM_DENSITY_DEFAULT UPD_DEFAULT - #define DIMM_DENSITY_1G_BIT INCREMENT_FOR_DEFAULT(0) - #define DIMM_DENSITY_2G_BIT INCREMENT_FOR_DEFAULT(1) - #define DIMM_DENSITY_4G_BIT INCREMENT_FOR_DEFAULT(2) - #define DIMM_DENSITY_8G_BIT INCREMENT_FOR_DEFAULT(3) - - /* - * PcdDIMMBusWidth - * Selection 0x0 , "8 bits" - * Selection 0x1 , "16 bits" - * Selection 0x2 , "32 bits" - * Selection 0x3 , "64 bits" - */ - uint8_t DIMMBusWidth; - #define DIMM_BUS_WIDTH_DEFAULT UPD_DEFAULT - #define DIMM_BUS_WIDTH_8BIT INCREMENT_FOR_DEFAULT(0) - #define DIMM_BUS_WIDTH_16BIT INCREMENT_FOR_DEFAULT(1) - #define DIMM_BUS_WIDTH_32BIT INCREMENT_FOR_DEFAULT(2) - #define DIMM_BUS_WIDTH_64BIT INCREMENT_FOR_DEFAULT(3) - - /* - * PcdDIMMSides - * Selection 0x0 , "1 Ranks" - * Selection 0x1 , "2 Ranks" - */ - uint8_t DIMMSides; - #define DIMM_SIDES_DEFAULT UPD_DEFAULT - #define DIMM_SIDES_1RANK INCREMENT_FOR_DEFAULT(0) - #define DIMM_SIDES_2RANK INCREMENT_FOR_DEFAULT(1) - - uint8_t DIMMtCL; - #define DIMM_TCL_DEFAULT UPD_DEFAULT - - uint8_t DIMMtRPtRCD; - #define DIMM_TRP_TRCD_DEFAULT UPD_DEFAULT - - uint8_t DIMMtWR; - #define DIMM_TWR_DEFAULT UPD_DEFAULT - - uint8_t DIMMtWTR; - #define DIMM_TWTR_DEFAULT UPD_DEFAULT - - uint8_t DIMMtRRD; - #define DIMM_TRRD_DEFAULT UPD_DEFAULT - - uint8_t DIMMtRTP; - #define DIMM_TRTP_DEFAULT UPD_DEFAULT - - uint8_t DIMMtFAW; - #define DIMM_TFAW_DEFAULT UPD_DEFAULT - - /* LPE Audio Clock configuration. */ - int lpe_codec_clk_freq; /* 19 or 25 are valid. */ - int lpe_codec_clk_num; /* Platform clock pins. [0:5] are valid. */ - - /* Structure for designware I2C controller */ - struct dw_i2c_bus_config i2c[CONFIG_SOC_INTEL_I2C_DEV_MAX]; - -/* ***** ACPI configuration ***** */ - /* Options for these are in src/arch/x86/include/arch/acpi.h */ - uint8_t fadt_pm_profile; - uint16_t fadt_boot_arch; - -}; - -#endif /* _FSP_BAYTRAIL_CHIP_H_ */ diff --git a/src/soc/intel/fsp_baytrail/cpu.c b/src/soc/intel/fsp_baytrail/cpu.c deleted file mode 100644 index 787a41015a..0000000000 --- a/src/soc/intel/fsp_baytrail/cpu.c +++ /dev/null @@ -1,185 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2013 Google Inc. - * Copyright (C) 2014 Sage Electronic Engineering, LLC. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include -#include -#include - -/* Core level MSRs */ -static const struct reg_script core_msr_script[] = { - /* Dynamic L2 shrink enable and threshold */ - REG_MSR_RMW(MSR_PKG_CST_CONFIG_CONTROL, ~0x3f000f, 0xe0008), - /* Disable C1E */ - REG_MSR_RMW(MSR_POWER_CTL, ~0x2, 0), - REG_MSR_OR(MSR_POWER_MISC, 0x44), - REG_SCRIPT_END -}; - -static void baytrail_core_init(struct device *cpu) -{ - printk(BIOS_DEBUG, "Init BayTrail core.\n"); - - /* On bay trail the turbo disable bit is actually scoped at building - * block level -- not package. For non-bsp cores that are within a - * building block enable turbo. The cores within the BSP's building - * block will just see it already enabled and move on. */ - if (lapicid()) - enable_turbo(); - - /* Set core MSRs */ - reg_script_run(core_msr_script); - - /* Set this core to max frequency ratio */ - set_max_freq(); -} - -static struct device_operations cpu_dev_ops = { - .init = baytrail_core_init, -}; - -static const struct cpu_device_id cpu_table[] = { - { X86_VENDOR_INTEL, 0x30671 }, - { X86_VENDOR_INTEL, 0x30672 }, - { X86_VENDOR_INTEL, 0x30673 }, - { X86_VENDOR_INTEL, 0x30678 }, - { X86_VENDOR_INTEL, 0x30679 }, - { 0, 0 }, -}; - -static const struct cpu_driver driver __cpu_driver = { - .ops = &cpu_dev_ops, - .id_table = cpu_table, -}; - -/* - * MP and SMM loading initialization. - */ - -struct smm_relocation_params { - msr_t smrr_base; - msr_t smrr_mask; -}; - -static struct smm_relocation_params smm_reloc_params; - -static void pre_mp_init(void) -{ - x86_mtrr_check(); - - /* Enable the local CPU apics */ - setup_lapic(); -} - -static int get_cpu_count(void) -{ - const struct pattrs *pattrs = pattrs_get(); - - return pattrs->num_cpus; -} - -static void fill_in_relocation_params(struct smm_relocation_params *params) -{ - uintptr_t tseg_base; - size_t tseg_size; - - /* All range registers are aligned to 4KiB */ - const u32 rmask = ~(4 * KiB - 1); - - smm_region(&tseg_base, &tseg_size); - - /* SMRR has 32-bits of valid address aligned to 4KiB. */ - params->smrr_base.lo = (tseg_base & rmask) | MTRR_TYPE_WRBACK; - params->smrr_base.hi = 0; - params->smrr_mask.lo = (~(tseg_size - 1) & rmask) | MTRR_PHYS_MASK_VALID; - params->smrr_mask.hi = 0; -} - -static void get_smm_info(uintptr_t *perm_smbase, size_t *perm_smsize, - size_t *smm_save_state_size) -{ - printk(BIOS_DEBUG, "Setting up SMI for CPU\n"); - - fill_in_relocation_params(&smm_reloc_params); - - smm_subregion(SMM_SUBREGION_HANDLER, perm_smbase, perm_smsize); - - *smm_save_state_size = sizeof(em64t100_smm_state_save_area_t); -} - -static void get_microcode_info(const void **microcode, int *parallel) -{ - const struct pattrs *pattrs = pattrs_get(); - - *microcode = pattrs->microcode_patch; - *parallel = 1; -} - -static void relocation_handler(int cpu, uintptr_t curr_smbase, - uintptr_t staggered_smbase) -{ - struct smm_relocation_params *relo_params = &smm_reloc_params; - em64t100_smm_state_save_area_t *smm_state; - - /* Set up SMRR. */ - wrmsr(IA32_SMRR_PHYS_BASE, relo_params->smrr_base); - wrmsr(IA32_SMRR_PHYS_MASK, relo_params->smrr_mask); - - smm_state = (void *)(SMM_EM64T100_SAVE_STATE_OFFSET + curr_smbase); - smm_state->smbase = staggered_smbase; -} - -static void enable_smis(void) -{ - if (CONFIG(HAVE_SMI_HANDLER)) - smm_southbridge_enable_smi(); -} - -static const struct mp_ops mp_ops = { - .pre_mp_init = pre_mp_init, - .get_cpu_count = get_cpu_count, - .get_smm_info = get_smm_info, - .get_microcode_info = get_microcode_info, - .pre_mp_smm_init = smm_southbridge_clear_state, - .relocation_handler = relocation_handler, - .post_mp_init = enable_smis, -}; - -void baytrail_init_cpus(struct device *dev) -{ - struct bus *cpu_bus = dev->link_list; - - if (mp_init_with_smm(cpu_bus, &mp_ops)) { - printk(BIOS_ERR, "MP initialization failure.\n"); - } -} diff --git a/src/soc/intel/fsp_baytrail/fsp/Kconfig b/src/soc/intel/fsp_baytrail/fsp/Kconfig deleted file mode 100644 index 3fe358ec89..0000000000 --- a/src/soc/intel/fsp_baytrail/fsp/Kconfig +++ /dev/null @@ -1,37 +0,0 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2014 Sage Electronic Engineering, LLC. -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; version 2 of the License. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## - -config BAYTRAIL_FSP_SPECIFIC_OPTIONS - def_bool y - select PLATFORM_USES_FSP1_0 - select USE_GENERIC_FSP_CAR_INC - select FSP_USES_UPD - -config FSP_FILE - string - default "../intel/fsp/baytrail/BAYTRAIL_FSP.fd" - help - The path and filename of the Intel FSP binary for this platform. - -config FSP_LOC - hex - default 0xfffc0000 - help - The location in CBFS that the FSP is located. This must match the - value that is set in the FSP binary. If the FSP needs to be moved, - rebase the FSP with Intel's BCT (tool). - - The Bay Trail FSP is built with a preferred base address of - 0xFFFC0000. diff --git a/src/soc/intel/fsp_baytrail/fsp/Makefile.inc b/src/soc/intel/fsp_baytrail/fsp/Makefile.inc deleted file mode 100644 index 024dd70855..0000000000 --- a/src/soc/intel/fsp_baytrail/fsp/Makefile.inc +++ /dev/null @@ -1,17 +0,0 @@ -# -# This file is part of the coreboot project. -# -# Copyright (C) 2014 Sage Electronic Engineering, LLC. -# -# This program is free software; you can redistribute it and/or modify -# it under the terms of the GNU General Public License as published by -# the Free Software Foundation; version 2 of the License. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# - -romstage-y += chipset_fsp_util.c -ramstage-y += chipset_fsp_util.c diff --git a/src/soc/intel/fsp_baytrail/fsp/chipset_fsp_util.c b/src/soc/intel/fsp_baytrail/fsp/chipset_fsp_util.c deleted file mode 100644 index 01c876d3b8..0000000000 --- a/src/soc/intel/fsp_baytrail/fsp/chipset_fsp_util.c +++ /dev/null @@ -1,329 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2013-2014 Sage Electronic Engineering, LLC. - * Copyright (C) 2014-2015 Intel Corporation - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include "../chip.h" -#include -#include -#include -#include - -/* Copy the default UPD region and settings to a buffer for modification */ -static void GetUpdDefaultFromFsp (FSP_INFO_HEADER *FspInfo, UPD_DATA_REGION *UpdData) -{ - VPD_DATA_REGION *VpdDataRgnPtr; - UPD_DATA_REGION *UpdDataRgnPtr; - VpdDataRgnPtr = (VPD_DATA_REGION *)(UINT32)(FspInfo->CfgRegionOffset + FspInfo->ImageBase); - UpdDataRgnPtr = (UPD_DATA_REGION *)(UINT32)(VpdDataRgnPtr->PcdUpdRegionOffset + FspInfo->ImageBase); - memcpy((void *)UpdData, (void *)UpdDataRgnPtr, sizeof(UPD_DATA_REGION)); -} - -/* default to just enabling HDMI audio */ -const PCH_AZALIA_CONFIG mAzaliaConfig = { - .Pme = 1, - .DS = 1, - .DA = 0, - .HdmiCodec = 1, - .AzaliaVCi = 1, - .Rsvdbits = 0, - .AzaliaVerbTableNum = 0, - .AzaliaVerbTable = NULL, - .ResetWaitTimer = 300 -}; - -typedef struct soc_intel_fsp_baytrail_config config_t; - -static const char *acpi_pci_mode_strings[] = { - "Disabled", - "Enabled in PCI Mode", - "Enabled in ACPI Mode" -}; - -static const char *emmc_mode_strings[] = { - "Disabled", - "Auto", - "eMMC 4.1", - "eMMC 4.5" -}; - -/** - * Update the UPD data based on values from devicetree.cb - * - * @param UpdData Pointer to the UPD Data structure - */ -static void ConfigureDefaultUpdData(FSP_INFO_HEADER *FspInfo, UPD_DATA_REGION *UpdData) -{ - DEVTREE_CONST struct device *dev; - DEVTREE_CONST config_t *config; - printk(FSP_INFO_LEVEL, "Configure Default UPD Data\n"); - - dev = pcidev_path_on_root(SOC_DEVFN_SOC); - config = config_of(dev); - - /* Set up default verb tables - Just HDMI audio */ - UpdData->AzaliaConfigPtr = (UINT32)&mAzaliaConfig; - - /* Set SPD addresses */ - UPD_SPD_CHECK(PcdMrcInitSPDAddr1); - UPD_SPD_CHECK(PcdMrcInitSPDAddr2); - - UPD_DEFAULT_CHECK(PcdSataMode); - UPD_DEFAULT_CHECK(PcdLpssSioEnablePciMode); - UPD_DEFAULT_CHECK(PcdMrcInitMmioSize); - UPD_DEFAULT_CHECK(PcdIgdDvmt50PreAlloc); - UPD_DEFAULT_CHECK(PcdApertureSize); - UPD_DEFAULT_CHECK(PcdGttSize); - UPD_DEFAULT_CHECK(SerialDebugPortAddress); - UPD_DEFAULT_CHECK(SerialDebugPortType); - UPD_DEFAULT_CHECK(PcdMrcDebugMsg); - UPD_DEFAULT_CHECK(PcdSccEnablePciMode); - UPD_DEFAULT_CHECK(IgdRenderStandby); - UPD_DEFAULT_CHECK(TxeUmaEnable); - UPD_DEFAULT_CHECK(PcdOsSelection); - UPD_DEFAULT_CHECK(PcdEMMC45DDR50Enabled); - UPD_DEFAULT_CHECK(PcdEMMC45HS200Enabled); - UPD_DEFAULT_CHECK(PcdEMMC45RetuneTimerValue); - UPD_DEFAULT_CHECK(PcdEnableIgd); - UPD_DEFAULT_CHECK(AutoSelfRefreshEnable); - UPD_DEFAULT_CHECK(APTaskTimeoutCnt); - - if (config->PcdeMMCBootMode == EMMC_FOLLOWS_DEVICETREE) - UpdData->PcdeMMCBootMode = 0; - else if ((config->PcdeMMCBootMode != EMMC_USE_DEFAULT)) - UpdData->PcdeMMCBootMode = config->PcdeMMCBootMode - EMMC_DISABLED; - - UpdData->PcdMrcInitTsegSize = CONFIG_SMM_TSEG_SIZE >> 20; - - printk(FSP_INFO_LEVEL, "GTT Size:\t\t%d MB\n", UpdData->PcdGttSize); - printk(FSP_INFO_LEVEL, "Tseg Size:\t\t%d MB\n", UpdData->PcdMrcInitTsegSize); - printk(FSP_INFO_LEVEL, "Aperture Size:\t\t%d MB\n", - APERTURE_SIZE_BASE << UpdData->PcdApertureSize); - printk(FSP_INFO_LEVEL, "IGD Memory Size:\t%d MB\n", - UpdData->PcdIgdDvmt50PreAlloc * IGD_MEMSIZE_MULTIPLIER); - printk(FSP_INFO_LEVEL, "MMIO Size:\t\t%d MB\n", UpdData->PcdMrcInitMmioSize); - - /* Advance dev to PCI device 0.0 */ - for (dev = &dev_root; dev; dev = dev_find_next_pci_device(dev)){ - if (dev->path.type != DEVICE_PATH_PCI) - continue; - if (dev->path.pci.devfn == PCI_DEVFN(0x0,0)) - break; - } - - /* - * Loop through all the SOC devices in the devicetree - * enabling and disabling them as requested. - */ - for (; dev; dev = dev->sibling) { - - if (dev->path.type != DEVICE_PATH_PCI) - continue; - - switch (dev->path.pci.devfn) { - UPD_DEVICE_CHECK(SOC_DEVFN_SDIO, PcdEnableSdio, "Sdio:\t\t\t"); - UPD_DEVICE_CHECK(SOC_DEVFN_SD, PcdEnableSdcard, "Sdcard:\t\t\t"); - UPD_DEVICE_CHECK(SOC_DEVFN_SIO_DMA1, PcdEnableDma0, "SIO Dma 0:\t\t"); - UPD_DEVICE_CHECK(SOC_DEVFN_I2C1, PcdEnableI2C0, "SIO I2C0:\t\t"); - UPD_DEVICE_CHECK(SOC_DEVFN_I2C2, PcdEnableI2C1, "SIO I2C1:\t\t"); - UPD_DEVICE_CHECK(SOC_DEVFN_I2C3, PcdEnableI2C2, "SIO I2C2:\t\t"); - UPD_DEVICE_CHECK(SOC_DEVFN_I2C4, PcdEnableI2C3, "SIO I2C3:\t\t"); - UPD_DEVICE_CHECK(SOC_DEVFN_I2C5, PcdEnableI2C4, "SIO I2C4:\t\t"); - UPD_DEVICE_CHECK(SOC_DEVFN_I2C6, PcdEnableI2C5, "SIO I2C5:\t\t"); - UPD_DEVICE_CHECK(SOC_DEVFN_I2C7, PcdEnableI2C6, "SIO I2C6:\t\t"); - UPD_DEVICE_CHECK(SOC_DEVFN_SIO_DMA2, PcdEnableDma1, "SIO Dma1:\t\t"); - UPD_DEVICE_CHECK(SOC_DEVFN_PWM1, PcdEnablePwm0, "Pwm0:\t\t\t"); - UPD_DEVICE_CHECK(SOC_DEVFN_PWM2, PcdEnablePwm1, "Pwm1:\t\t\t"); - UPD_DEVICE_CHECK(SOC_DEVFN_HSUART1, PcdEnableHsuart0, "Hsuart0:\t\t"); - UPD_DEVICE_CHECK(SOC_DEVFN_HSUART2, PcdEnableHsuart1, "Hsuart1:\t\t"); - UPD_DEVICE_CHECK(SOC_DEVFN_SPI, PcdEnableSpi, "Spi:\t\t\t"); - UPD_DEVICE_CHECK(SOC_DEVFN_SATA, PcdEnableSata, "SATA:\t\t\t"); - UPD_DEVICE_CHECK(SOC_DEVFN_HDA, PcdEnableAzalia, "Azalia:\t\t\t"); - - case SOC_DEVFN_MIPI: /* Camera / Image Signal Processing */ - if (FspInfo->ImageRevision >= FSP_GOLD3_REV_ID) { - UpdData->ISPEnable = dev->enabled; - } else { - /* Gold2 and earlier FSP: ISPEnable is the field */ - /* next to PcdGttSize in UPD_DATA_REGION struct */ - *(&(UpdData->PcdGttSize)+sizeof(UINT8)) = dev->enabled; - printk (FSP_INFO_LEVEL, - "Baytrail Gold2 or earlier FSP, adjust ISPEnable offset.\n"); - } - printk(FSP_INFO_LEVEL, "MIPI/ISP:\t\t%s\n", - dev->enabled?"Enabled":"Disabled"); - break; - case SOC_DEVFN_EMMC: /* EMMC 4.1*/ - if ((dev->enabled) && - (config->PcdeMMCBootMode == EMMC_FOLLOWS_DEVICETREE)) - UpdData->PcdeMMCBootMode = EMMC_4_1 - EMMC_DISABLED; - break; - case SOC_DEVFN_MMC45: /* MMC 4.5*/ - if ((dev->enabled) && - (config->PcdeMMCBootMode == EMMC_FOLLOWS_DEVICETREE)) - UpdData->PcdeMMCBootMode = EMMC_4_5 - EMMC_DISABLED; - break; - case SOC_DEVFN_XHCI: - UpdData->PcdEnableXhci = dev->enabled; - break; - case SOC_DEVFN_EHCI: - UpdData->PcdEnableXhci = !(dev->enabled); - break; - - case SOC_DEVFN_LPE: - if (dev->enabled) - UpdData->PcdEnableLpe = config->LpeAcpiModeEnable; - else - UpdData->PcdEnableLpe = 0; - break; - } - } - - if (UpdData->PcdEnableLpe < sizeof(acpi_pci_mode_strings) / sizeof (char *)) - printk(FSP_INFO_LEVEL, "Lpe:\t\t\t%s\n", - acpi_pci_mode_strings[UpdData->PcdEnableLpe]); - else - printk(FSP_INFO_LEVEL, "Lpe:\t\t\tUnknown (0x%02x)\n", - UpdData->PcdEnableLpe); - - if (UpdData->PcdeMMCBootMode < sizeof(emmc_mode_strings) / sizeof (char *)) - printk(FSP_INFO_LEVEL, "eMMC Mode:\t\t%s\n", - emmc_mode_strings[UpdData->PcdeMMCBootMode]); - else - printk(FSP_INFO_LEVEL, "eMMC Mode:\t\tUnknown (0x%02x)\n", - UpdData->PcdeMMCBootMode); - - - if (UpdData->PcdEnableSata) - printk(FSP_INFO_LEVEL, "SATA Mode:\t\t%s\n", - UpdData->PcdSataMode?"AHCI":"IDE"); - - printk(FSP_INFO_LEVEL, "Xhci:\t\t\t%s\n", - UpdData->PcdEnableXhci?"Enabled":"Disabled"); - - /* - * set memory down parameters - * Skip setting values if memory down is disabled - * Skip setting values if FSP is earlier than gold 3 - */ - if (FspInfo->ImageRevision >= FSP_GOLD3_REV_ID) { - UPD_MEMDOWN_CHECK(EnableMemoryDown, DECREMENT_FOR_DEFAULT); - if (UpdData->PcdMemoryParameters.EnableMemoryDown) { - UPD_MEMDOWN_CHECK(DRAMSpeed, DECREMENT_FOR_DEFAULT); - UPD_MEMDOWN_CHECK(DRAMType, DECREMENT_FOR_DEFAULT); - UPD_MEMDOWN_CHECK(DIMM0Enable, DECREMENT_FOR_DEFAULT); - UPD_MEMDOWN_CHECK(DIMM1Enable, DECREMENT_FOR_DEFAULT); - UPD_MEMDOWN_CHECK(DIMMDWidth, DECREMENT_FOR_DEFAULT); - UPD_MEMDOWN_CHECK(DIMMDensity, DECREMENT_FOR_DEFAULT); - UPD_MEMDOWN_CHECK(DIMMBusWidth, DECREMENT_FOR_DEFAULT); - UPD_MEMDOWN_CHECK(DIMMSides, DECREMENT_FOR_DEFAULT); - UPD_MEMDOWN_CHECK(DIMMtCL, NO_DECREMENT_FOR_DEFAULT); - UPD_MEMDOWN_CHECK(DIMMtRPtRCD, NO_DECREMENT_FOR_DEFAULT); - UPD_MEMDOWN_CHECK(DIMMtWR, NO_DECREMENT_FOR_DEFAULT); - UPD_MEMDOWN_CHECK(DIMMtWTR, NO_DECREMENT_FOR_DEFAULT); - UPD_MEMDOWN_CHECK(DIMMtRRD, NO_DECREMENT_FOR_DEFAULT); - UPD_MEMDOWN_CHECK(DIMMtRTP, NO_DECREMENT_FOR_DEFAULT); - UPD_MEMDOWN_CHECK(DIMMtFAW, NO_DECREMENT_FOR_DEFAULT); - - printk (FSP_INFO_LEVEL, - "Memory Down Data Existed : %s\n"\ - "- Speed (0: 800, 1: 1066, 2: 1333, 3: 1600): %d\n"\ - "- Type (0: DDR3, 1: DDR3L) : %d\n"\ - "- DIMM0 : %s\n"\ - "- DIMM1 : %s\n"\ - "- Width : x%d\n"\ - "- Density : %dGbit\n" - "- BudWidth : %dbit\n"\ - "- Rank # : %d\n"\ - "- tCL : %02X\n"\ - "- tRPtRCD : %02X\n"\ - "- tWR : %02X\n"\ - "- tWTR : %02X\n"\ - "- tRRD : %02X\n"\ - "- tRTP : %02X\n"\ - "- tFAW : %02X\n" - , (UpdData->PcdMemoryParameters.EnableMemoryDown) ? "Enabled" : "Disabled" - , UpdData->PcdMemoryParameters.DRAMSpeed - , UpdData->PcdMemoryParameters.DRAMType - , (UpdData->PcdMemoryParameters.DIMM0Enable) ? "Enabled" : "Disabled" - , (UpdData->PcdMemoryParameters.DIMM1Enable) ? "Enabled" : "Disabled" - , 8 << (UpdData->PcdMemoryParameters.DIMMDWidth) - , 1 << (UpdData->PcdMemoryParameters.DIMMDensity) - , 8 << (UpdData->PcdMemoryParameters.DIMMBusWidth) - , (UpdData->PcdMemoryParameters.DIMMSides) + 1 - , UpdData->PcdMemoryParameters.DIMMtCL - , UpdData->PcdMemoryParameters.DIMMtRPtRCD - , UpdData->PcdMemoryParameters.DIMMtWR - , UpdData->PcdMemoryParameters.DIMMtWTR - , UpdData->PcdMemoryParameters.DIMMtRRD - , UpdData->PcdMemoryParameters.DIMMtRTP - , UpdData->PcdMemoryParameters.DIMMtFAW - ); - } - } -} - -/* Set up the Baytrail specific structures for the call into the FSP */ -void chipset_fsp_early_init(FSP_INIT_PARAMS *pFspInitParams, - FSP_INFO_HEADER *fsp_ptr) -{ - FSP_INIT_RT_BUFFER *pFspRtBuffer = pFspInitParams->RtBufferPtr; - uint32_t prev_sleep_state; - - /* Get previous sleep state but don't clear */ - prev_sleep_state = chipset_prev_sleep_state(0); - printk(BIOS_INFO, "prev_sleep_state = S%d\n", prev_sleep_state); - - /* Initialize the UPD Data */ - GetUpdDefaultFromFsp (fsp_ptr, pFspRtBuffer->Common.UpdDataRgnPtr); - ConfigureDefaultUpdData(fsp_ptr, pFspRtBuffer->Common.UpdDataRgnPtr); - pFspInitParams->NvsBufferPtr = NULL; - - /* Find the fastboot cache that was saved in the ROM */ - if (CONFIG(ENABLE_MRC_CACHE)) - pFspInitParams->NvsBufferPtr = find_and_set_fastboot_cache(); - - if (prev_sleep_state == ACPI_S3) { - /* S3 resume */ - if (pFspInitParams->NvsBufferPtr == NULL) { - /* If waking from S3 and no cache then. */ - printk(BIOS_WARNING, "No MRC cache found in S3 resume path.\n"); - post_code(POST_RESUME_FAILURE); - /* Clear Sleep Type */ - outl(inl(ACPI_BASE_ADDRESS + PM1_CNT) & - ~(SLP_TYP), ACPI_BASE_ADDRESS + PM1_CNT); - /* Reboot */ - printk(BIOS_WARNING, "Rebooting..\n" ); - system_reset(); - /* Should not reach here.. */ - die("Reboot System\n"); - } - pFspRtBuffer->Common.BootMode = BOOT_ON_S3_RESUME; - } else { - /* Not S3 resume */ - pFspRtBuffer->Common.BootMode = BOOT_WITH_FULL_CONFIGURATION; - } - - return; -} diff --git a/src/soc/intel/fsp_baytrail/fsp/chipset_fsp_util.h b/src/soc/intel/fsp_baytrail/fsp/chipset_fsp_util.h deleted file mode 100644 index f75cc4e93d..0000000000 --- a/src/soc/intel/fsp_baytrail/fsp/chipset_fsp_util.h +++ /dev/null @@ -1,55 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2013-2014 Sage Electronic Engineering, LLC. - * Copyright (C) 2014 Intel Corporation - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef CHIPSET_FSP_UTIL_H -#define CHIPSET_FSP_UTIL_H - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#define FSP_INFO_HEADER_GUID \ - { \ - 0x912740BE, 0x2284, 0x4734, {0xB9, 0x71, 0x84, 0xB0, 0x27, 0x35, 0x3F, 0x0C} \ - } - -/* - * The FSP Image ID is different for each platform's FSP and - * can be used to verify that the right FSP binary is loaded. - * For the Bay Trail FSP, the Image Id is "VLYVIEW0". - */ -#define FSP_IMAGE_ID_DWORD0 0x56594C56 /* 'VLYV' */ -#define FSP_IMAGE_ID_DWORD1 0x30574549 /* 'IEW0' */ - -/* Revision of the FSP binary */ -#define FSP_GOLD3_REV_ID 0x00000303 - -#define NO_DECREMENT_FOR_DEFAULT 0 -#define DECREMENT_FOR_DEFAULT 1 - -#define UPD_MEMDOWN_CHECK(member, adjust) \ - if (config->member != UPD_DEFAULT) { \ - UpdData->PcdMemoryParameters.member = config->member - adjust; \ - } - -#endif /* CHIPSET_FSP_UTIL_H */ diff --git a/src/soc/intel/fsp_baytrail/gfx.c b/src/soc/intel/fsp_baytrail/gfx.c deleted file mode 100644 index dab997275d..0000000000 --- a/src/soc/intel/fsp_baytrail/gfx.c +++ /dev/null @@ -1,115 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright 2013 Google Inc. - * Copyright (C) 2016 Siemens AG - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#define GFX_TIMEOUT 100000 /* 100ms */ - -static const struct reg_script gpu_pre_vbios_script[] = { - /* Make sure GFX is bus master with MMIO access */ - REG_PCI_OR32(PCI_COMMAND, PCI_COMMAND_MASTER|PCI_COMMAND_MEMORY), - /* Display */ - REG_IOSF_WRITE(IOSF_PORT_PMC, PUNIT_PWRGT_CONTROL, 0xc0), - REG_IOSF_POLL(IOSF_PORT_PMC, PUNIT_PWRGT_STATUS, 0xc0, 0xc0, - GFX_TIMEOUT), - /* Tx/Rx Lanes */ - REG_IOSF_WRITE(IOSF_PORT_PMC, PUNIT_PWRGT_CONTROL, 0xfff0c0), - REG_IOSF_POLL(IOSF_PORT_PMC, PUNIT_PWRGT_STATUS, 0xfff0c0, 0xfff0c0, - GFX_TIMEOUT), - /* Common Lane */ - REG_IOSF_WRITE(IOSF_PORT_PMC, PUNIT_PWRGT_CONTROL, 0xfffcc0), - REG_IOSF_POLL(IOSF_PORT_PMC, PUNIT_PWRGT_STATUS, 0xfffcc0, 0xfffcc0, - GFX_TIMEOUT), - /* Ungating Tx only */ - REG_IOSF_WRITE(IOSF_PORT_PMC, PUNIT_PWRGT_CONTROL, 0xf00cc0), - REG_IOSF_POLL(IOSF_PORT_PMC, PUNIT_PWRGT_STATUS, 0xfffcc0, 0xf00cc0, - GFX_TIMEOUT), - /* Ungating Common Lane only */ - REG_IOSF_WRITE(IOSF_PORT_PMC, PUNIT_PWRGT_CONTROL, 0xf000c0), - REG_IOSF_POLL(IOSF_PORT_PMC, PUNIT_PWRGT_STATUS, 0xffffc0, 0xf000c0, - GFX_TIMEOUT), - /* Ungating Display */ - REG_IOSF_WRITE(IOSF_PORT_PMC, PUNIT_PWRGT_CONTROL, 0xf00000), - REG_IOSF_POLL(IOSF_PORT_PMC, PUNIT_PWRGT_STATUS, 0xfffff0, 0xf00000, - GFX_TIMEOUT), - REG_SCRIPT_END -}; - -static const struct reg_script gfx_post_vbios_script[] = { - /* Deassert Render Force-Wake */ - REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0x1300b0, 0x80000000), - REG_RES_POLL32(PCI_BASE_ADDRESS_0, 0x1300b4, 0x8000, 0, GFX_TIMEOUT), - /* Deassert Media Force-Wake */ - REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0x1300b8, 0x80000000), - REG_RES_POLL32(PCI_BASE_ADDRESS_0, 0x1300bc, 0x8000, 0, GFX_TIMEOUT), - /* Set Lock bits */ - REG_PCI_RMW32(GGC, 0xffffffff, 1), - REG_PCI_RMW32(GSM_BASE, 0xffffffff, 1), - REG_PCI_RMW32(GTT_BASE, 0xffffffff, 1), - REG_SCRIPT_END -}; - -static inline void gfx_run_script(struct device *dev, const struct reg_script *ops) -{ - reg_script_run_on_dev(dev, ops); -} - -static void gfx_pre_vbios_init(struct device *dev) -{ - printk(BIOS_INFO, "GFX: Pre VBIOS Init\n"); - gfx_run_script(dev, gpu_pre_vbios_script); -} - -static void gfx_post_vbios_init(struct device *dev) -{ - printk(BIOS_INFO, "GFX: Post VBIOS Init\n"); - gfx_run_script(dev, gfx_post_vbios_script); -} - -static void gfx_init(struct device *dev) -{ - /* Pre VBIOS Init */ - gfx_pre_vbios_init(dev); - - /* Run VBIOS */ - pci_dev_init(dev); - - /* Post VBIOS Init */ - gfx_post_vbios_init(dev); -} - -static struct device_operations gfx_device_ops = { - .read_resources = pci_dev_read_resources, - .set_resources = pci_dev_set_resources, - .enable_resources = pci_dev_enable_resources, - .init = gfx_init, - .ops_pci = &soc_pci_ops, -}; - -static const struct pci_driver gfx_driver __pci_driver = { - .ops = &gfx_device_ops, - .vendor = PCI_VENDOR_ID_INTEL, - .device = GFX_DEVID, -}; diff --git a/src/soc/intel/fsp_baytrail/gpio.c b/src/soc/intel/fsp_baytrail/gpio.c deleted file mode 100644 index 3e2499accd..0000000000 --- a/src/soc/intel/fsp_baytrail/gpio.c +++ /dev/null @@ -1,372 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2013 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include -#include -#include -#include - -/* - * GPIO-to-Pad LUTs - * - * These tables translate the GPIO number to the pad configuration register - * for that GPIO in the memory-mapped pad configuration registers. - * See the tables: - * PCU iLB GPIO CFIO_SCORE Address Map - * PCU iLB GPIO CFIO_SSUS Address Map - */ -static const u8 gpncore_gpio_to_pad[GPNCORE_COUNT] = - { 19, 18, 17, 20, 21, 22, 24, 25, /* [ 0: 7] */ - 23, 16, 14, 15, 12, 26, 27, 1, /* [ 8:15] */ - 4, 8, 11, 0, 3, 6, 10, 13, /* [16:23] */ - 2, 5, 9 }; /* [24:26] */ - -static const u8 gpscore_gpio_to_pad[GPSCORE_COUNT] = - { 85, 89, 93, 96, 99, 102, 98, 101, /* [ 0: 7] */ - 34, 37, 36, 38, 39, 35, 40, 84, /* [ 8: 15] */ - 62, 61, 64, 59, 54, 56, 60, 55, /* [16: 23] */ - 63, 57, 51, 50, 53, 47, 52, 49, /* [24: 31] */ - 48, 43, 46, 41, 45, 42, 58, 44, /* [32: 39] */ - 95, 105, 70, 68, 67, 66, 69, 71, /* [40: 47] */ - 65, 72, 86, 90, 88, 92, 103, 77, /* [48: 55] */ - 79, 83, 78, 81, 80, 82, 13, 12, /* [56: 63] */ - 15, 14, 17, 18, 19, 16, 2, 1, /* [64: 71] */ - 0, 4, 6, 7, 9, 8, 33, 32, /* [72: 79] */ - 31, 30, 29, 27, 25, 28, 26, 23, /* [80: 87] */ - 21, 20, 24, 22, 5, 3, 10, 11, /* [88: 95] */ - 106, 87, 91, 104, 97, 100 }; /* [96:101] */ - -static const u8 gpssus_gpio_to_pad[GPSSUS_COUNT] = - { 29, 33, 30, 31, 32, 34, 36, 35, /* [ 0: 7] */ - 38, 37, 18, 7, 11, 20, 17, 1, /* [ 8:15] */ - 8, 10, 19, 12, 0, 2, 23, 39, /* [16:23] */ - 28, 27, 22, 21, 24, 25, 26, 51, /* [24:31] */ - 56, 54, 49, 55, 48, 57, 50, 58, /* [32:39] */ - 52, 53, 59, 40 }; /* [40:43] */ - - -/* GPIO bank descriptions */ -static const struct gpio_bank gpncore_bank = { - .gpio_count = GPNCORE_COUNT, - .gpio_to_pad = gpncore_gpio_to_pad, - .legacy_base = GP_LEGACY_BASE_NONE, - .pad_base = GPNCORE_PAD_BASE, - .has_wake_en = 0, - .gpio_f1_range_start = GPNCORE_GPIO_F1_RANGE_START, - .gpio_f1_range_end = GPNCORE_GPIO_F1_RANGE_END, -}; - -static const struct gpio_bank gpscore_bank = { - .gpio_count = GPSCORE_COUNT, - .gpio_to_pad = gpscore_gpio_to_pad, - .legacy_base = GPSCORE_LEGACY_BASE, - .pad_base = GPSCORE_PAD_BASE, - .has_wake_en = 0, - .gpio_f1_range_start = GPSCORE_GPIO_F1_RANGE_START, - .gpio_f1_range_end = GPSCORE_GPIO_F1_RANGE_END, -}; - -static const struct gpio_bank gpssus_bank = { - .gpio_count = GPSSUS_COUNT, - .gpio_to_pad = gpssus_gpio_to_pad, - .legacy_base = GPSSUS_LEGACY_BASE, - .pad_base = GPSSUS_PAD_BASE, - .has_wake_en = 1, - .gpio_f1_range_start = GPSSUS_GPIO_F1_RANGE_START, - .gpio_f1_range_end = GPSSUS_GPIO_F1_RANGE_END, -}; - - -static void setup_gpios(const struct soc_gpio_map *gpios, - const struct gpio_bank *bank) -{ - const struct soc_gpio_map *config; - int gpio = 0; - u32 reg, pad_conf0, *regmmio; - u8 set, bit; - - u32 use_sel[4] = {0}; - u32 io_sel[4] = {0}; - u32 gp_lvl[4] = {0}; - u32 tpe[4] = {0}; - u32 tne[4] = {0}; - u32 wake_en[4] = {0}; - - if (!gpios) - return; - - for (config = gpios; config->pad_conf0 != GPIO_LIST_END; - config++, gpio++) { - if (gpio > bank->gpio_count) - break; - - set = gpio >> 5; - bit = gpio % 32; - - if (bank->legacy_base != GP_LEGACY_BASE_NONE) { - /* Legacy IO configuration */ - use_sel[set] |= config->use_sel << bit; - io_sel[set] |= config->io_sel << bit; - gp_lvl[set] |= config->gp_lvl << bit; - tpe[set] |= config->tpe << bit; - tne[set] |= config->tne << bit; - - /* Some banks do not have wake_en ability */ - if (bank->has_wake_en) - wake_en[set] |= config->wake_en << bit; - } - - /* Pad configuration registers */ - regmmio = (u32 *)(bank->pad_base + 16 * - bank->gpio_to_pad[gpio]); - - /* Add correct func to GPIO pad config */ - pad_conf0 = config->pad_conf0; - if (config->is_gpio) - { - if (gpio >= bank->gpio_f1_range_start && - gpio <= bank->gpio_f1_range_end) - pad_conf0 |= PAD_FUNC1; - else - pad_conf0 |= PAD_FUNC0; - } - -#ifdef GPIO_DEBUG - printk(BIOS_DEBUG, "Write Pad: Base(%p) - %x %x %x\n", - regmmio, pad_conf0, config->pad_conf1, config->pad_val); -#endif - - write32(regmmio + (PAD_CONF0_REG/sizeof(u32)), pad_conf0); - write32(regmmio + (PAD_CONF1_REG/sizeof(u32)), - config->pad_conf1); - write32(regmmio + (PAD_VAL_REG/sizeof(u32)), config->pad_val); - } - - if (bank->legacy_base != GP_LEGACY_BASE_NONE) - for (set = 0; set <= (bank->gpio_count - 1) / 32; ++set) { - reg = bank->legacy_base + 0x20 * set; - -#ifdef GPIO_DEBUG - printk(BIOS_DEBUG, - "Write GPIO: Reg(%x) - %x %x %x %x %x\n", - reg, use_sel[set], io_sel[set], gp_lvl[set], - tpe[set], tne[set]); -#endif - - outl(use_sel[set], reg + LEGACY_USE_SEL_REG); - outl(io_sel[set], reg + LEGACY_IO_SEL_REG); - outl(gp_lvl[set], reg + LEGACY_GP_LVL_REG); - outl(tpe[set], reg + LEGACY_TPE_REG); - outl(tne[set], reg + LEGACY_TNE_REG); - - /* TS registers are WOC */ - outl(0, reg + LEGACY_TS_REG); - - if (bank->has_wake_en) - outl(wake_en[set], reg + LEGACY_WAKE_EN_REG); - } -} - -static void setup_gpio_route(const struct soc_gpio_map *sus, - const struct soc_gpio_map *core) -{ - uint32_t route_reg = 0; - int i; - - /* FIXME: SCI interrupts should be routed regardlessy. */ - if (!CONFIG(HAVE_SMI_HANDLER)) - return; - - for (i = 0; i < 8; i++) { - /* SMI takes precedence and wake_en implies SCI. */ - if (sus[i].smi) { - route_reg |= ROUTE_SMI << (2 * i); - } else if (sus[i].sci) { - route_reg |= ROUTE_SCI << (2 * i); - } - - if (core[i].smi) { - route_reg |= ROUTE_SMI << (2 * (i + 8)); - } else if (core[i].sci) { - route_reg |= ROUTE_SCI << (2 * (i + 8)); - } - } - - smm_southcluster_save_gpio_route(route_reg); -} - -static void setup_dirqs(const u8 dirq[GPIO_MAX_DIRQS], - const struct gpio_bank *bank) -{ - u32 *reg = (u32 *)(bank->pad_base + PAD_BASE_DIRQ_OFFSET); - u32 val; - int i; - - /* Write all four DIRQ registers */ - for (i=0; i<4; ++i) { - val = dirq[i * 4 + 3] << 24 | dirq[i * 4 + 2] << 16 | - dirq[i * 4 + 1] << 8 | dirq[i * 4]; - write32(reg + i, val); -#ifdef GPIO_DEBUG - printk(BIOS_DEBUG, "Write DIRQ reg(%x) - %x\n", - reg + i, val); -#endif - } -} - -void setup_soc_gpios(struct soc_gpio_config *config) -{ - if (config) { - setup_gpios(config->ncore, &gpncore_bank); - setup_gpios(config->score, &gpscore_bank); - setup_gpios(config->ssus, &gpssus_bank); - setup_gpio_route(config->ssus, config->score); - - if (config->core_dirq) - setup_dirqs(*config->core_dirq, &gpscore_bank); - if (config->sus_dirq) - setup_dirqs(*config->sus_dirq, &gpssus_bank); - } - -} - -struct soc_gpio_config* __weak mainboard_get_gpios(void) -{ - printk(BIOS_DEBUG, "Default/empty GPIO config\n"); - return NULL; -} - -/** \brief returns the input / output value from an SCORE GPIO - * - * @param gpio_num The GPIO number being read - * @return The current input or output value of the GPIO - */ -uint8_t read_score_gpio(uint8_t gpio_num) -{ - uint8_t retval = 0; - if (gpio_num < GPSCORE_COUNT) - retval = score_get_gpio(gpscore_gpio_to_pad[gpio_num]); - - return retval; -} - -/** \brief sets an output SCORE GPIO to desired value - * - * @param gpio_num The GPIO number being read - * @param val The value this output must be set to (0 or 1) - * @return void - */ -void write_score_gpio(uint8_t gpio_num, uint8_t val) -{ - if (gpio_num < GPSCORE_COUNT) - score_set_gpio(gpscore_gpio_to_pad[gpio_num], val); -} - -/** \brief returns the input / output value from an SSUS GPIO - * - * @param gpio_num The GPIO number being read - * @return The current input or output value of the GPIO - */ -uint8_t read_ssus_gpio(uint8_t gpio_num) -{ - uint8_t retval = 0; - if (gpio_num < GPSSUS_COUNT) - retval = ssus_get_gpio(gpssus_gpio_to_pad[gpio_num]); - - return retval; -} - -/** \brief sets an output SSUS GPIO to desired value - * - * @param gpio_num The GPIO number being read - * @param val The value this output must be set to (0 or 1) - * @return void - */ -void write_ssus_gpio(uint8_t gpio_num, uint8_t val) -{ - if (gpio_num < GPSSUS_COUNT) - ssus_set_gpio(gpssus_gpio_to_pad[gpio_num], val); -} - -/** \brief Sets up the function, pulls, and Input/Output of a Baytrail - * SSUS (S5) or SCORE (S0) GPIO - * - * @param ssus_gpio 1 if SSUS GPIO is being configured 0 if SCORE GPIO - * @param gpio_num The GPIO number being configured - * @param pconf0 function, pull direction, and pull value - * function: PAD_FUNC0 - PAD_FUNC7 - * pull assign: PAD_PULL_DISABLE / PAD_PULL_UP / PAD_PULL_DOWN - * pull_value: PAD_PU_2K / PAD_PU_10K / PAD_PU_20K / PAD_PU_40K - * @param pad_val input / output state and pad value - * io state: PAD_VAL_INPUT / PAD_VAL_OUTPUT - * pad value: PAD_VAL_HIGH / PAD_VAL_LOW - */ -static void configure_ssus_score_gpio(uint8_t ssus_gpio, uint8_t gpio_num, - uint32_t pconf0, uint32_t pad_val) -{ - uint32_t reg; - uint32_t *pad_addr; - if (ssus_gpio) - pad_addr = ssus_pconf0(gpssus_gpio_to_pad[gpio_num]); - else - pad_addr = score_pconf0(gpscore_gpio_to_pad[gpio_num]); - - if ((ssus_gpio && gpio_num >= GPSSUS_COUNT) || - (gpio_num >= GPSCORE_COUNT)){ - printk(BIOS_WARNING,"Warning: Invalid %s GPIO specified (%d)\n", - ssus_gpio ? "SSUS" : "SCORE", gpio_num); - return; - } - - /* - * Pad Configuration 0 Register - * 2:0 - func_pin_mux - * 8:7 - Pull assignment: 00 - Non pull 01 - Pull Up 10 - Pull down - * 11 - reserved - * 10:9 - Pull strength: 00 - 2K 01 - 10K 10 - 20K 11 - 40K - */ - reg = PAD_CONFIG0_DEFAULT; - reg |= pconf0 & 0x787; - write32(pad_addr + (PAD_CONF0_REG/sizeof(u32)), reg); - - /* - * Pad Value Register - * 0: Pad value - * 1: output enable (0 is enabled) - * 2: input enable (0 is enabled) - */ - reg = read32(pad_addr + (PAD_VAL_REG/sizeof(u32))); - reg &= ~0x7; - reg |= pad_val & 0x7; - write32(pad_addr + (PAD_VAL_REG/sizeof(u32)), reg); -} - -/** \brief Sets up the function, pulls, and Input/Output of a Baytrail S5 GPIO - * - */ -void configure_ssus_gpio(uint8_t gpio_num, uint32_t pconf0, uint32_t pad_val) -{ - configure_ssus_score_gpio(1, gpio_num, pconf0, pad_val); -} - -/** \brief Sets up the function, pulls, and Input/Output of a Baytrail S5 GPIO - * - */ -void configure_score_gpio(uint8_t gpio_num, uint32_t pconf0, uint32_t pad_val) -{ - configure_ssus_score_gpio(0, gpio_num, pconf0, pad_val); -} diff --git a/src/soc/intel/fsp_baytrail/i2c.c b/src/soc/intel/fsp_baytrail/i2c.c deleted file mode 100644 index 37ce2d0b21..0000000000 --- a/src/soc/intel/fsp_baytrail/i2c.c +++ /dev/null @@ -1,294 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2014-2019 Siemens AG - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include "chip.h" - -/* Convert I2C bus number to PCI device and function */ -int dw_i2c_soc_bus_to_devfn(unsigned int bus) -{ - if (bus <= 6) - return PCI_DEVFN(SIO1_DEV, bus + 1); - else - return -1; -} - -/* Convert PCI device and function to I2C bus number */ -int dw_i2c_soc_dev_to_bus(struct device *dev) -{ - pci_devfn_t devfn = dev->path.pci.devfn; - if ((devfn >= SOC_DEVFN_I2C1) && (devfn <= SOC_DEVFN_I2C7)) - return PCI_FUNC(devfn) - 1; - else - return -1; -} - -/* Getting I2C bus configuration from devicetree config */ -const struct dw_i2c_bus_config *dw_i2c_get_soc_cfg(unsigned int bus) -{ - const struct soc_intel_fsp_baytrail_config *config; - const struct device *dev = pcidev_path_on_root(SOC_DEVFN_SOC); - - if (dev && dev->chip_info) { - config = dev->chip_info; - return &config->i2c[bus]; - } - - die("Could not find SA_DEV_ROOT devicetree config!\n"); -} - -#if !ENV_RAMSTAGE -static int lpss_i2c_early_init_bus(unsigned int bus) -{ - const struct dw_i2c_bus_config *config; - const struct device *tree_dev; - pci_devfn_t dev; - int devfn; - uintptr_t base; - - /* Find the PCI device for this bus controller */ - devfn = dw_i2c_soc_bus_to_devfn(bus); - if (devfn < 0) { - printk(BIOS_ERR, "I2C%u device not found\n", bus); - return -1; - } - - /* Look up the controller device in the devicetree */ - dev = PCI_DEV(0, PCI_SLOT(devfn), PCI_FUNC(devfn)); - tree_dev = pcidev_path_on_root(devfn); - if (!tree_dev || !tree_dev->enabled) { - printk(BIOS_ERR, "I2C%u device not enabled\n", bus); - return -1; - } - - /* Skip if not enabled for early init */ - config = dw_i2c_get_soc_cfg(bus); - if (!config || !config->early_init) { - printk(BIOS_DEBUG, "I2C%u not enabled for early init\n", bus); - return -1; - } - - /* Prepare early base address for access before memory */ - base = EARLY_I2C_BASE(bus); - pci_write_config32(dev, PCI_BASE_ADDRESS_0, base); - pci_write_config32(dev, PCI_COMMAND, - PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER); - - /* Take device out of reset */ - write32((void *)((uint32_t)base + I2C_SOFTWARE_RESET), I2C_RESET_APB | I2C_RESET_FUNC); - - /* Initialize the controller */ - if (dw_i2c_init(bus, config) < 0) { - printk(BIOS_ERR, "I2C%u failed to initialize\n", bus); - return -1; - } - - return 0; -} - -uintptr_t dw_i2c_base_address(unsigned int bus) -{ - int devfn; - pci_devfn_t dev; - uintptr_t base; - - /* Find device+function for this controller */ - devfn = dw_i2c_soc_bus_to_devfn(bus); - if (devfn < 0) - return 0; - - /* Form a PCI address for this device */ - dev = PCI_DEV(0, PCI_SLOT(devfn), PCI_FUNC(devfn)); - - /* Read the first base address for this device */ - base = pci_read_config32(dev, PCI_BASE_ADDRESS_0) & 0xfffffff0; - - /* Attempt to initialize bus if base is not set yet */ - if (!base && !lpss_i2c_early_init_bus(bus)) - base = pci_read_config32(dev, PCI_BASE_ADDRESS_0) & 0xfffffff0; - return base; -} -#else - -uintptr_t dw_i2c_base_address(unsigned int bus) -{ - int devfn; - struct device *dev; - struct resource *bar = NULL; - - /* bus -> devfn */ - devfn = dw_i2c_soc_bus_to_devfn(bus); - - if (devfn < 0) - return (uintptr_t)NULL; - - /* devfn -> dev */ - dev = pcidev_path_on_root(devfn); - if (dev && dev->enabled) { - /* dev -> bar0 */ - bar = find_resource(dev, PCI_BASE_ADDRESS_0); - } - - if (bar) - return bar->base; - else - return (uintptr_t)NULL; -} - -static void i2c_enable_acpi_mode(struct device *dev, int iosf_reg, int nvs_index) -{ - struct resource *bar; - global_nvs_t *gnvs; - uint32_t val; - - /* Find ACPI NVS to update BARs */ - gnvs = (global_nvs_t *)cbmem_find(CBMEM_ID_ACPI_GNVS); - if (!gnvs) { - printk(BIOS_ERR, "Unable to locate Global NVS\n"); - return; - } - - /* Save BAR0 and BAR1 to ACPI NVS */ - bar = find_resource(dev, PCI_BASE_ADDRESS_0); - if (bar) - gnvs->dev.lpss_bar0[nvs_index] = (uint32_t)bar->base; - - bar = find_resource(dev, PCI_BASE_ADDRESS_1); - if (bar) - gnvs->dev.lpss_bar1[nvs_index] = (uint32_t)bar->base; - - /* Device is enabled in ACPI mode */ - gnvs->dev.lpss_en[nvs_index] = 1; - - /* Put device in ACPI mode */ - val = iosf_lpss_read(iosf_reg); - val |= (LPSS_CTL_PCI_CFG_DIS | LPSS_CTL_ACPI_INT_EN); - iosf_lpss_write(iosf_reg, val); - val = pci_read_config32(dev, PCI_COMMAND); - val |= PCI_COMMAND_INT_DISABLE; - pci_write_config32(dev, PCI_COMMAND, val); -} - -static void dev_enable_snoop_and_pm(struct device *dev, int iosf_reg) -{ - uint32_t val; - - val = iosf_lpss_read(iosf_reg); - val &= ~(LPSS_CTL_SNOOP | LPSS_CTL_NOSNOOP); - val |= (LPSS_CTL_SNOOP | LPSS_CTL_PM_CAP_PRSNT); - iosf_lpss_write(iosf_reg, val); -} - -static void dev_ctl_reg(struct device *dev, int *iosf_reg, int *nvs_index) -{ - int bus; - - bus = dw_i2c_soc_dev_to_bus(dev); - if (bus >= 0) { - *iosf_reg = LPSS_I2C1_CTL + (bus * 8); - *nvs_index = bus + 1; - } else { - - *iosf_reg = -1; - *nvs_index = -1; - } -} - -static void i2c_disable_resets(struct device *dev) -{ - uint32_t base; - - printk(BIOS_DEBUG, "Releasing I2C device from reset.\n"); - base = pci_read_config32(dev, PCI_BASE_ADDRESS_0) & 0xfffffff0; - write32((void *)(base + I2C_SOFTWARE_RESET), I2C_RESET_APB | I2C_RESET_FUNC); -} - -static void i2c_lpss_init(struct device *dev) -{ - struct soc_intel_fsp_baytrail_config *config = dev->chip_info; - int iosf_reg, nvs_index; - - dev_ctl_reg(dev, &iosf_reg, &nvs_index); - - if (iosf_reg < 0) { - int slot = PCI_SLOT(dev->path.pci.devfn); - int func = PCI_FUNC(dev->path.pci.devfn); - printk(BIOS_DEBUG, "Could not find iosf_reg for %02x.%01x\n", - slot, func); - return; - } - dev_enable_snoop_and_pm(dev, iosf_reg); - i2c_disable_resets(dev); - - if (config && (config->PcdLpssSioEnablePciMode == LPSS_PCI_MODE_DISABLE)) - i2c_enable_acpi_mode(dev, iosf_reg, nvs_index); -} -/* - * This function ensures that the device is actually out of reset and - * it is ready for initialization sequence. - */ -static void dw_i2c_device_init(struct device *dev) -{ - int bus = dw_i2c_soc_dev_to_bus(dev); - - if (bus < 0) - return; - - if (!dw_i2c_base_address(bus)) - return; - i2c_lpss_init(dev); - dw_i2c_dev_init(dev); -} - -static struct device_operations i2c_dev_ops = { - .read_resources = pci_dev_read_resources, - .set_resources = pci_dev_set_resources, - .enable_resources = pci_dev_enable_resources, - .scan_bus = scan_smbus, - .ops_i2c_bus = &dw_i2c_bus_ops, - .ops_pci = &pci_dev_ops_pci, - .init = dw_i2c_device_init, - .acpi_fill_ssdt_generator = dw_i2c_acpi_fill_ssdt, -}; - -static const unsigned short pci_device_ids[] = { - I2C1_DEVID, - I2C2_DEVID, - I2C3_DEVID, - I2C4_DEVID, - I2C5_DEVID, - I2C6_DEVID, - I2C7_DEVID, - 0 -}; - -static const struct pci_driver pch_i2c __pci_driver = { - .ops = &i2c_dev_ops, - .vendor = PCI_VENDOR_ID_INTEL, - .devices = pci_device_ids, -}; -#endif diff --git a/src/soc/intel/fsp_baytrail/include/soc/acpi.h b/src/soc/intel/fsp_baytrail/include/soc/acpi.h deleted file mode 100644 index 917419e4df..0000000000 --- a/src/soc/intel/fsp_baytrail/include/soc/acpi.h +++ /dev/null @@ -1,36 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2013 Google, Inc. - * Copyright (C) 2013 Sage Electronic Engineering, LLC. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef _BAYTRAIL_ACPI_H_ -#define _BAYTRAIL_ACPI_H_ - -#include -#include -#include - -void acpi_create_serialio_ssdt(acpi_header_t *ssdt); -void acpi_fill_in_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt); -unsigned long acpi_madt_irq_overrides(unsigned long current); -void acpi_init_gnvs(global_nvs_t *gnvs); - -#ifndef __SIMPLE_DEVICE__ -unsigned long southcluster_write_acpi_tables(struct device *device, - unsigned long current, - struct acpi_rsdp *rsdp); -void southcluster_inject_dsdt(struct device *device); -#endif - -#endif /* _BAYTRAIL_ACPI_H_ */ diff --git a/src/soc/intel/fsp_baytrail/include/soc/baytrail.h b/src/soc/intel/fsp_baytrail/include/soc/baytrail.h deleted file mode 100644 index de902aac6f..0000000000 --- a/src/soc/intel/fsp_baytrail/include/soc/baytrail.h +++ /dev/null @@ -1,65 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007-2008 coresystems GmbH - * Copyright (C) 2011 Google Inc. - * Copyright (C) 2013 Sage Electronic Engineering, LLC. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef __SOC_INTEL_FSP_BAYTRAIL_BAYTRAIL_H__ -#define __SOC_INTEL_FSP_BAYTRAIL_BAYTRAIL_H__ - -#define DEFAULT_ECBASE CONFIG_MMCONF_BASE_ADDRESS -#define CPU_MICROCODE_CBFS_LEN 0x26000 - -/* Southbridge internal device IO BARs (Set to match FSP settings) */ -#define SMBUS_IO_BASE 0xefa0 -#define SMBUS_SLAVE_ADDR 0x24 -#define DEFAULT_GPIOBASE 0x0500 -#define DEFAULT_ABASE 0x0400 - -/* Southbridge internal device MEM BARs (Set to match FSP settings) */ -#define DEFAULT_IBASE 0xfed08000 -#define DEFAULT_PBASE 0xfed03000 -#ifndef __ACPI__ -#define DEFAULT_RCBA ((u8 *)0xfed1c000) -#else -#define DEFAULT_RCBA 0xfed1c000 -#endif - -/* Device 0:0.0 PCI configuration space (Host Bridge) */ -#define SKPAD 0xFC - -/* SOC types */ -#define SOC_TYPE_BAYTRAIL 0x0F1C - -/* Everything below this line is ignored in the DSDT */ -#ifndef __ACPI__ -#ifndef __ASSEMBLER__ -#include - -int bridge_silicon_revision(void); -void rangeley_early_initialization(void); -void set_max_freq(void); - -/* soc.c */ -int soc_silicon_revision(void); -int soc_silicon_type(void); -int soc_silicon_supported(int type, int rev); -void soc_enable(struct device *dev); - -void report_platform_info(void); - -#endif /* __ASSEMBLER__ */ -#endif /* __ACPI__ */ - -#endif diff --git a/src/soc/intel/fsp_baytrail/include/soc/device_nvs.h b/src/soc/intel/fsp_baytrail/include/soc/device_nvs.h deleted file mode 100644 index ec1e568bfd..0000000000 --- a/src/soc/intel/fsp_baytrail/include/soc/device_nvs.h +++ /dev/null @@ -1,61 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2013 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef _BAYTRAIL_DEVICE_NVS_H_ -#define _BAYTRAIL_DEVICE_NVS_H_ - -#include - -#define LPSS_NVS_SIO_DMA1 0 -#define LPSS_NVS_I2C1 1 -#define LPSS_NVS_I2C2 2 -#define LPSS_NVS_I2C3 3 -#define LPSS_NVS_I2C4 4 -#define LPSS_NVS_I2C5 5 -#define LPSS_NVS_I2C6 6 -#define LPSS_NVS_I2C7 7 -#define LPSS_NVS_SIO_DMA2 8 -#define LPSS_NVS_SPI 9 -#define LPSS_NVS_PWM1 10 -#define LPSS_NVS_PWM2 11 -#define LPSS_NVS_HSUART1 12 -#define LPSS_NVS_HSUART2 13 - -#define SCC_NVS_MMC 0 -#define SCC_NVS_SDIO 1 -#define SCC_NVS_SD 2 - -typedef struct { - /* Device Enabled in ACPI Mode */ - u8 lpss_en[14]; - u8 scc_en[3]; - u8 lpe_en; - - /* BAR 0 */ - u32 lpss_bar0[14]; - u32 scc_bar0[3]; - u32 lpe_bar0; - - /* BAR 1 */ - u32 lpss_bar1[14]; - u32 scc_bar1[3]; - u32 lpe_bar1; - - /* Extra */ - u32 lpe_fw; /* LPE Firmware */ - u8 rsvd1[3930]; /* Add padding so sizeof(device_nvs_t) == 0x1000 */ -} __packed device_nvs_t; - -#endif diff --git a/src/soc/intel/fsp_baytrail/include/soc/ehci.h b/src/soc/intel/fsp_baytrail/include/soc/ehci.h deleted file mode 100644 index fe990b7017..0000000000 --- a/src/soc/intel/fsp_baytrail/include/soc/ehci.h +++ /dev/null @@ -1,40 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2013 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef BAYTRAIL_EHCI_H -#define BAYTRAIL_EHCI_H - -/* EHCI PCI Registers */ -#define EHCI_CMD_STS 0x04 -# define INTRDIS (1 << 10) -#define EHCI_SBRN_FLA_PWC 0x60 -# define PORTWKIMP (1 << 16) -# define PORTWKCAPMASK (0x3ff << 17) -#define EHCI_USB2PDO 0x64 - -/* EHCI Memory Registers */ -#define USB2CMD 0x20 -# define USB2CMD_ASE (1 << 5) -# define USB2CMD_PSE (1 << 4) -# define USB2CMD_HCRESET (1 << 1) -# define USB2CMD_RS (1 << 0) -#define USB2STS 0x24 -# define USB2STS_HCHALT (1 << 12) - -/* RCBA EHCI Registers */ -#define RCBA_FUNC_DIS 0x220 -# define RCBA_EHCI_DIS (1 << 0) - -#endif /* BAYTRAIL_EHCI_H */ diff --git a/src/soc/intel/fsp_baytrail/include/soc/gfx.h b/src/soc/intel/fsp_baytrail/include/soc/gfx.h deleted file mode 100644 index e7fc8ca604..0000000000 --- a/src/soc/intel/fsp_baytrail/include/soc/gfx.h +++ /dev/null @@ -1,44 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2013 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef _BAYTRAIL_GFX_H_ -#define _BAYTRAIL_GFX_H_ - -/* - * PCI config registers. - */ - -#define GGC 0x50 -# define GGC_VGA_DISABLE (1 << 1) -# define GGC_GTT_SIZE_MASK (3 << 8) -# define GGC_GTT_SIZE_0MB (0 << 8) -# define GGC_GTT_SIZE_1MB (1 << 8) -# define GGC_GTT_SIZE_2MB (2 << 8) -# define GGC_GSM_SIZE_MASK (0x1f << 3) -# define GGC_GSM_SIZE_0MB (0 << 3) -# define GGC_GSM_SIZE_32MB (1 << 3) -# define GGC_GSM_SIZE_64MB (2 << 3) -# define GGC_GSM_SIZE_128MB (4 << 3) - -#define GSM_BASE 0x5c -#define GTT_BASE 0x70 - -#define MSAC 0x62 -#define APERTURE_SIZE_MASK (3 << 1) -#define APERTURE_SIZE_128MB (0 << 1) -#define APERTURE_SIZE_256MB (1 << 1) -#define APERTURE_SIZE_512MB (3 << 1) - -#endif /* _BAYTRAIL_GFX_H_ */ diff --git a/src/soc/intel/fsp_baytrail/include/soc/gpio.h b/src/soc/intel/fsp_baytrail/include/soc/gpio.h deleted file mode 100644 index 137ec95f14..0000000000 --- a/src/soc/intel/fsp_baytrail/include/soc/gpio.h +++ /dev/null @@ -1,442 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2013 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef _BAYTRAIL_GPIO_H_ -#define _BAYTRAIL_GPIO_H_ - -#include -#include -#include - -/* #define GPIO_DEBUG */ - -/* Pad base, ex. PAD_CONF0[n]= PAD_BASE+16*n */ -#define GPSCORE_PAD_BASE (IO_BASE_ADDRESS + IO_BASE_OFFSET_GPSCORE) -#define GPNCORE_PAD_BASE (IO_BASE_ADDRESS + IO_BASE_OFFSET_GPNCORE) -#define GPSSUS_PAD_BASE (IO_BASE_ADDRESS + IO_BASE_OFFSET_GPSSUS) - -/* DIRQ registers start at pad base + 0x980 */ -#define PAD_BASE_DIRQ_OFFSET 0x980 - -/* Pad register offset */ -#define PAD_CONF0_REG 0x0 -#define PAD_CONF1_REG 0x4 -#define PAD_VAL_REG 0x8 - -/* Legacy IO register base */ -#define GPSCORE_LEGACY_BASE (GPIO_BASE_ADDRESS + 0x00) -#define GPSSUS_LEGACY_BASE (GPIO_BASE_ADDRESS + 0x80) -/* Some banks have no legacy GPIO interface */ -#define GP_LEGACY_BASE_NONE 0xFFFF - -#define LEGACY_USE_SEL_REG 0x00 -#define LEGACY_IO_SEL_REG 0x04 -#define LEGACY_GP_LVL_REG 0x08 -#define LEGACY_TPE_REG 0x0C -#define LEGACY_TNE_REG 0x10 -#define LEGACY_TS_REG 0x14 -#define LEGACY_WAKE_EN_REG 0x18 - -/* Number of GPIOs in each bank */ -#define GPNCORE_COUNT 27 -#define GPSCORE_COUNT 102 -#define GPSSUS_COUNT 44 - -/* GPIO legacy IO register settings */ -#define GPIO_USE_MMIO 0 -#define GPIO_USE_LEGACY 1 - -#define GPIO_DIR_OUTPUT 0 -#define GPIO_DIR_INPUT 1 - -#define GPIO_LEVEL_LOW 0 -#define GPIO_LEVEL_HIGH 1 - -#define GPIO_PEDGE_DISABLE 0 -#define GPIO_PEDGE_ENABLE 1 - -#define GPIO_NEDGE_DISABLE 0 -#define GPIO_NEDGE_ENABLE 1 - -/* config0[29] - Disable second mask */ -#define PAD_MASK2_DISABLE (1 << 29) - -/* config0[27] - Direct Irq En */ -#define PAD_IRQ_EN (1 << 27) - -/* config0[26] - gd_tne */ -#define PAD_TNE_IRQ (1 << 26) - -/* config0[25] - gd_tpe */ -#define PAD_TPE_IRQ (1 << 25) - -/* config0[24] - Gd Level */ -#define PAD_LEVEL_IRQ (1 << 24) -#define PAD_EDGE_IRQ (0 << 24) - -/* config0[17] - Slow clkgate / glitch filter */ -#define PAD_SLOWGF_ENABLE (1 << 17) - -/* config0[16] - Fast clkgate / glitch filter */ -#define PAD_FASTGF_ENABLE (1 << 16) - -/* config0[15] - Hysteresis enable (inverted) */ -#define PAD_HYST_DISABLE (1 << 15) -#define PAD_HYST_ENABLE (0 << 15) - -/* config0[14:13] - Hysteresis control */ -#define PAD_HYST_CTRL_DEFAULT (2 << 13) - -/* config0[11] - Bypass Flop */ -#define PAD_FLOP_BYPASS (1 << 11) -#define PAD_FLOP_ENABLE (0 << 11) - -/* config0[10:9] - Pull str */ -#define PAD_PU_2K (0 << 9) -#define PAD_PU_10K (1 << 9) -#define PAD_PU_20K (2 << 9) -#define PAD_PU_40K (3 << 9) - -/* config0[8:7] - Pull assign */ -#define PAD_PULL_DISABLE (0 << 7) -#define PAD_PULL_UP (1 << 7) -#define PAD_PULL_DOWN (2 << 7) - -/* config0[2:0] - Func. pin mux */ -#define PAD_FUNC0 0x0 -#define PAD_FUNC1 0x1 -#define PAD_FUNC2 0x2 -#define PAD_FUNC3 0x3 -#define PAD_FUNC4 0x4 -#define PAD_FUNC5 0x5 -#define PAD_FUNC6 0x6 - -/* pad config0 power-on values - We will not often want to change these */ -#define PAD_CONFIG0_DEFAULT (PAD_MASK2_DISABLE | PAD_SLOWGF_ENABLE | \ - PAD_FASTGF_ENABLE | PAD_HYST_DISABLE | \ - PAD_HYST_CTRL_DEFAULT | PAD_FLOP_BYPASS) - -/* pad config1 reg power-on values - Shouldn't need to change this */ -#define PAD_CONFIG1_DEFAULT 0x8000 - -/* pad_val[2] - Iinenb - active low */ -#define PAD_VAL_INPUT_DISABLE (1 << 2) -#define PAD_VAL_INPUT_ENABLE (0 << 2) - -/* pad_val[1] - Ioutenb - active low */ -#define PAD_VAL_OUTPUT_DISABLE (1 << 1) -#define PAD_VAL_OUTPUT_ENABLE (0 << 1) - -/* Input / Output state should usually be mutually exclusive */ -#define PAD_VAL_INPUT (PAD_VAL_INPUT_ENABLE | PAD_VAL_OUTPUT_DISABLE) -#define PAD_VAL_OUTPUT (PAD_VAL_OUTPUT_ENABLE | PAD_VAL_INPUT_DISABLE) - -/* pad_val[0] - Value */ -#define PAD_VAL_HIGH (1 << 0) -#define PAD_VAL_LOW (0 << 0) - -/* pad_val reg power-on default varies by pad, and apparently can cause issues - * if not set correctly, even if the pin isn't configured as GPIO. */ -#define PAD_VAL_DEFAULT PAD_VAL_INPUT - -/* Configure GPIOs as MMIO by default */ -#define GPIO_INPUT_PU_10K \ - { .pad_conf0 = PAD_PU_10K | PAD_PULL_UP | PAD_CONFIG0_DEFAULT, \ - .pad_conf1 = PAD_CONFIG1_DEFAULT, \ - .pad_val = PAD_VAL_INPUT, \ - .use_sel = GPIO_USE_MMIO, \ - .is_gpio = 1 } - -#define GPIO_INPUT_PD_10K \ - { .pad_conf0 = PAD_PU_10K | PAD_PULL_DOWN | PAD_CONFIG0_DEFAULT, \ - .pad_conf1 = PAD_CONFIG1_DEFAULT, \ - .pad_val = PAD_VAL_INPUT, \ - .use_sel = GPIO_USE_MMIO, \ - .is_gpio = 1 } - -#define GPIO_INPUT_PU_20K \ - { .pad_conf0 = PAD_PU_20K | PAD_PULL_UP | PAD_CONFIG0_DEFAULT, \ - .pad_conf1 = PAD_CONFIG1_DEFAULT, \ - .pad_val = PAD_VAL_INPUT, \ - .use_sel = GPIO_USE_MMIO, \ - .is_gpio = 1 } - -#define GPIO_INPUT_PD_20K \ - { .pad_conf0 = PAD_PU_20K | PAD_PULL_DOWN | PAD_CONFIG0_DEFAULT, \ - .pad_conf1 = PAD_CONFIG1_DEFAULT, \ - .pad_val = PAD_VAL_INPUT, \ - .use_sel = GPIO_USE_MMIO, \ - .is_gpio = 1 } - -#define GPIO_INPUT_NOPU \ - { .pad_conf0 = PAD_PU_20K | PAD_PULL_DISABLE | PAD_CONFIG0_DEFAULT, \ - .pad_conf1 = PAD_CONFIG1_DEFAULT, \ - .pad_val = PAD_VAL_INPUT, \ - .use_sel = GPIO_USE_MMIO, \ - .is_gpio = 1 } - -#define GPIO_INPUT_LEGACY_NOPU \ - { .pad_conf0 = PAD_PU_20K | PAD_PULL_DISABLE | PAD_CONFIG0_DEFAULT, \ - .pad_conf1 = PAD_CONFIG1_DEFAULT, \ - .pad_val = PAD_VAL_INPUT, \ - .use_sel = GPIO_USE_LEGACY, \ - .io_sel = GPIO_DIR_INPUT, \ - .is_gpio = 1 } - -/* Direct / dedicated IRQ input - pass signal directly to apic */ -#define GPIO_DIRQ \ - { .pad_conf0 = PAD_PU_20K | PAD_PULL_DISABLE | PAD_CONFIG0_DEFAULT \ - | PAD_FUNC0 | PAD_IRQ_EN | PAD_TPE_IRQ | PAD_LEVEL_IRQ, \ - .pad_conf1 = PAD_CONFIG1_DEFAULT, \ - .pad_val = PAD_VAL_INPUT, } - -#define GPIO_OUT_LOW_LEGACY \ - { .pad_conf0 = PAD_PULL_DISABLE | PAD_CONFIG0_DEFAULT, \ - .pad_conf1 = PAD_CONFIG1_DEFAULT, \ - .pad_val = PAD_VAL_OUTPUT | PAD_VAL_LOW, \ - .use_sel = GPIO_USE_LEGACY, \ - .io_sel = GPIO_DIR_OUTPUT, \ - .gp_lvl = GPIO_LEVEL_LOW, \ - .is_gpio = 1 } - -#define GPIO_OUT_HIGH_LEGACY \ - { .pad_conf0 = PAD_PULL_DISABLE | PAD_CONFIG0_DEFAULT, \ - .pad_conf1 = PAD_CONFIG1_DEFAULT, \ - .pad_val = PAD_VAL_OUTPUT | PAD_VAL_HIGH, \ - .use_sel = GPIO_USE_LEGACY, \ - .io_sel = GPIO_DIR_OUTPUT, \ - .gp_lvl = GPIO_LEVEL_HIGH, \ - .is_gpio = 1 } - -#define GPIO_OUT_LOW \ - { .pad_conf0 = PAD_PULL_DISABLE | PAD_CONFIG0_DEFAULT, \ - .pad_conf1 = PAD_CONFIG1_DEFAULT, \ - .pad_val = PAD_VAL_OUTPUT | PAD_VAL_LOW, \ - .use_sel = GPIO_USE_MMIO, \ - .io_sel = GPIO_DIR_OUTPUT, \ - .gp_lvl = GPIO_LEVEL_LOW, \ - .is_gpio = 1 } - -#define GPIO_OUT_HIGH \ - { .pad_conf0 = PAD_PULL_DISABLE | PAD_CONFIG0_DEFAULT, \ - .pad_conf1 = PAD_CONFIG1_DEFAULT, \ - .pad_val = PAD_VAL_OUTPUT | PAD_VAL_HIGH, \ - .use_sel = GPIO_USE_MMIO, \ - .io_sel = GPIO_DIR_OUTPUT, \ - .gp_lvl = GPIO_LEVEL_HIGH, \ - .is_gpio = 1 } - -/* Define no-pull / PU / PD configs for each functional config option */ -#define GPIO_FUNC(_func, _pudir, _str) \ - { .use_sel = GPIO_USE_MMIO, \ - .pad_conf0 = PAD_FUNC##_func | PAD_##_pudir | PAD_PU_##_str | \ - PAD_CONFIG0_DEFAULT, \ - .pad_conf1 = PAD_CONFIG1_DEFAULT, \ - .pad_val = PAD_VAL_DEFAULT } - -/* Default functional configs -- no PU */ -#define GPIO_FUNC0 GPIO_FUNC(0, PULL_DISABLE, 20K) -#define GPIO_FUNC1 GPIO_FUNC(1, PULL_DISABLE, 20K) -#define GPIO_FUNC2 GPIO_FUNC(2, PULL_DISABLE, 20K) -#define GPIO_FUNC3 GPIO_FUNC(3, PULL_DISABLE, 20K) -#define GPIO_FUNC4 GPIO_FUNC(4, PULL_DISABLE, 20K) -#define GPIO_FUNC5 GPIO_FUNC(5, PULL_DISABLE, 20K) -#define GPIO_FUNC6 GPIO_FUNC(6, PULL_DISABLE, 20K) - -/* ACPI GPIO routing. Assume everything is externally pulled and negative edge - * triggered. SCI implies WAKE, but WAKE doesn't imply SCI. */ -#define GPIO_ACPI_SCI \ - { .pad_conf0 = PAD_PULL_DISABLE | PAD_CONFIG0_DEFAULT | PAD_FUNC0, \ - .pad_conf1 = PAD_CONFIG1_DEFAULT, \ - .pad_val = PAD_VAL_INPUT, \ - .use_sel = GPIO_USE_LEGACY, \ - .io_sel = GPIO_DIR_INPUT, \ - .tne = 1, \ - .sci = 1, \ - .wake_en = 1, } -#define GPIO_ACPI_WAKE \ - { .pad_conf0 = PAD_PULL_DISABLE | PAD_CONFIG0_DEFAULT | PAD_FUNC0, \ - .pad_conf1 = PAD_CONFIG1_DEFAULT, \ - .pad_val = PAD_VAL_INPUT, \ - .use_sel = GPIO_USE_LEGACY, \ - .io_sel = GPIO_DIR_INPUT, \ - .tne = 1, \ - .wake_en = 1, } -#define GPIO_ACPI_SMI \ - { .pad_conf0 = PAD_PULL_DISABLE | PAD_CONFIG0_DEFAULT | PAD_FUNC0, \ - .pad_conf1 = PAD_CONFIG1_DEFAULT, \ - .pad_val = PAD_VAL_INPUT, \ - .use_sel = GPIO_USE_LEGACY, \ - .io_sel = GPIO_DIR_INPUT, \ - .tne = 1, \ - .smi = 1} - -/* End marker */ -#define GPIO_LIST_END 0xffffffff - -#define GPIO_END \ - { .pad_conf0 = GPIO_LIST_END } - -/* Common default GPIO settings */ -#define GPIO_INPUT GPIO_INPUT_NOPU -#define GPIO_INPUT_LEGACY GPIO_INPUT_LEGACY_NOPU -#define GPIO_INPUT_PU GPIO_INPUT_PU_20K -#define GPIO_INPUT_PD GPIO_INPUT_PD_20K -#define GPIO_NC GPIO_INPUT_PU_20K -#define GPIO_DEFAULT GPIO_FUNC0 - -/* 16 DirectIRQs per supported bank */ -#define GPIO_MAX_DIRQS 16 - -/* Most pins are GPIO function 0. Some banks have a range of pins with GPIO - * function 1. Indicate first / last GPIOs with function 1. */ -#define GPIO_NONE 255 -/* All NCORE GPIOs are function 0 */ -#define GPNCORE_GPIO_F1_RANGE_START GPIO_NONE -#define GPNCORE_GPIO_F1_RANGE_END GPIO_NONE -/* SCORE GPIO [92:93] are function 1 */ -#define GPSCORE_GPIO_F1_RANGE_START 92 -#define GPSCORE_GPIO_F1_RANGE_END 93 -/* SSUS GPIO [11:21] are function 1 */ -#define GPSSUS_GPIO_F1_RANGE_START 11 -#define GPSSUS_GPIO_F1_RANGE_END 21 - -struct soc_gpio_map { - u32 pad_conf0; - u32 pad_conf1; - u32 pad_val; - u32 use_sel : 1; - u32 io_sel : 1; - u32 gp_lvl : 1; - u32 tpe : 1; - u32 tne : 1; - u32 wake_en : 1; - u32 smi : 1; - u32 is_gpio : 1; - u32 sci : 1; -} __packed; - -struct soc_gpio_config { - const struct soc_gpio_map *ncore; - const struct soc_gpio_map *score; - const struct soc_gpio_map *ssus; - const u8 (*core_dirq)[GPIO_MAX_DIRQS]; - const u8 (*sus_dirq)[GPIO_MAX_DIRQS]; -}; - -/* Description of GPIO 'bank' ex. {ncore, score. ssus} */ -struct gpio_bank { - const int gpio_count; - const u8 *gpio_to_pad; - const int legacy_base; - const unsigned long pad_base; - const u8 has_wake_en :1; - const u8 gpio_f1_range_start; - const u8 gpio_f1_range_end; -}; - -void smm_southcluster_save_gpio_route(uint32_t route); -void setup_soc_gpios(struct soc_gpio_config *config); -/* This function is weak and can be overridden by a mainboard function. */ -struct soc_gpio_config* mainboard_get_gpios(void); -uint8_t read_score_gpio(uint8_t gpio_num); -void write_score_gpio(uint8_t gpio_num, uint8_t val); -uint8_t read_ssus_gpio(uint8_t gpio_num); -void write_ssus_gpio(uint8_t gpio_num, uint8_t val); -void configure_ssus_gpio(uint8_t gpio_num, uint32_t pconf0, uint32_t pad_val); -void configure_score_gpio(uint8_t gpio_num, uint32_t pconf0, uint32_t pad_val); - -/* Functions / defines for changing GPIOs in romstage */ -/* SCORE Pad definitions. */ -#define UART_RXD_PAD 82 -#define UART_TXD_PAD 83 -#define PCU_SMB_CLK_PAD 88 -#define PCU_SMB_DATA_PAD 90 - -static inline uint32_t *score_pconf0(int pad_num) -{ - return (uint32_t *)(GPSCORE_PAD_BASE + pad_num * 16); -} - -static inline uint32_t *ssus_pconf0(int pad_num) -{ - return (uint32_t *)(GPSSUS_PAD_BASE + pad_num * 16); -} - -static inline void score_select_func(int pad, int func) -{ - uint32_t reg; - uint32_t *pconf0_addr = score_pconf0(pad); - - reg = read32(pconf0_addr); - reg &= ~0x7; - reg |= func & 0x7; - write32(pconf0_addr, reg); -} - -static inline void ssus_select_func(int pad, int func) -{ - uint32_t reg; - uint32_t *pconf0_addr = ssus_pconf0(pad); - - reg = read32(pconf0_addr); - reg &= ~0x7; - reg |= func & 0x7; - write32(pconf0_addr, reg); -} - - -/* These functions require that the input pad be configured as an input GPIO */ -static inline int score_get_gpio(int pad) -{ - uint32_t *val_addr = score_pconf0(pad) + (PAD_VAL_REG/sizeof(uint32_t)); - - return read32(val_addr) & PAD_VAL_HIGH; -} - -static inline int ssus_get_gpio(int pad) -{ - uint32_t *val_addr = ssus_pconf0(pad) + (PAD_VAL_REG/sizeof(uint32_t)); - - return read32(val_addr) & PAD_VAL_HIGH; -} - -/* These functions require that the output pad is configured as an output */ -/* GPIO and is mapped to memory space and not IO space. */ -static inline void score_set_gpio(int pad, int val) -{ - uint32_t *val_addr = score_pconf0(pad) + (PAD_VAL_REG/sizeof(uint32_t)); - - write32(val_addr, ((read32(val_addr) & ~0x1) | val)); -} - -static inline void ssus_set_gpio(int pad, int val) -{ - uint32_t *val_addr = ssus_pconf0(pad) + (PAD_VAL_REG/sizeof(uint32_t)); - - write32(val_addr, ((read32(val_addr) & ~0x1) | val)); -} - -static inline void ssus_disable_internal_pull(int pad) -{ - uint32_t reg; - uint32_t *pconf0_addr = ssus_pconf0(pad); - - reg = read32(pconf0_addr); - reg &= ~(0xf << 7); - write32(pconf0_addr, reg); -} - -#endif /* _BAYTRAIL_GPIO_H_ */ diff --git a/src/soc/intel/fsp_baytrail/include/soc/i2c.h b/src/soc/intel/fsp_baytrail/include/soc/i2c.h deleted file mode 100644 index 3a4ff2c32b..0000000000 --- a/src/soc/intel/fsp_baytrail/include/soc/i2c.h +++ /dev/null @@ -1,23 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2014-2019 Siemens AG - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef __SOC_INTEL_FSP_BAYTRAIL_I2C_H__ -#define __SOC_INTEL_FSP_BAYTRAIL_I2C_H__ - -#define I2C_SOFTWARE_RESET 0x804 -#define I2C_RESET_APB (1 << 1) -#define I2C_RESET_FUNC (1 << 0) - -#endif /* __SOC_INTEL_FSP_BAYTRAIL_I2C_H__ */ diff --git a/src/soc/intel/fsp_baytrail/include/soc/iomap.h b/src/soc/intel/fsp_baytrail/include/soc/iomap.h deleted file mode 100644 index d54d3fcc29..0000000000 --- a/src/soc/intel/fsp_baytrail/include/soc/iomap.h +++ /dev/null @@ -1,89 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2013 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef _BAYTRAIL_IOMAP_H_ -#define _BAYTRAIL_IOMAP_H_ - -/* - * Memory Mapped IO bases. - */ - -/* PCI Configuration Space */ -#define MCFG_BASE_ADDRESS CONFIG_MMCONF_BASE_ADDRESS -#define MCFG_BASE_SIZE 0x10000000 - -/* Transactions in this range will abort */ -#define ABORT_BASE_ADDRESS 0xfeb00000 -#define ABORT_BASE_SIZE 0x00100000 - -/* Power Management Controller */ -#define PMC_BASE_ADDRESS 0xfed03000 -#define PMC_BASE_SIZE 0x400 - -/* IO Memory */ -#define IO_BASE_ADDRESS 0xfed0c000 -#define IO_BASE_OFFSET_GPSCORE 0x0000 -#define IO_BASE_OFFSET_GPNCORE 0x1000 -#define IO_BASE_OFFSET_GPSSUS 0x2000 -#define IO_BASE_SIZE 0x4000 - -/* Intel Legacy Block */ -#define ILB_BASE_ADDRESS 0xfed08000 -#define ILB_BASE_SIZE 0x400 - -/* SPI Bus */ -#define SPI_BASE_ADDRESS 0xfed01000 -#define SPI_BASE_SIZE 0x400 - -/* MODPHY */ -#define MPHY_BASE_ADDRESS 0xfef00000 -#define MPHY_BASE_SIZE 0x100000 - -/* Power Management Unit */ -#define PUNIT_BASE_ADDRESS 0xfed05000 -#define PUNIT_BASE_SIZE 0x800 - -/* Root Complex Base Address */ -#define RCBA_BASE_ADDRESS 0xfed1c000 -#define RCBA_BASE_SIZE 0x400 - -/* High Performance Event Timer */ -#define HPET_BASE_ADDRESS 0xfed00000 -#define HPET_BASE_SIZE 0x400 - -/* Temporary Base Address */ -#define TEMP_BASE_ADDRESS 0xfd000000 -#define EARLY_I2C_BASE_ADDRESS 0xfe020000 -#define EARLY_I2C_BASE(x) (EARLY_I2C_BASE_ADDRESS + (0x2000 * (x))) - -/* - * IO Port bases. - */ -#define ACPI_BASE_ADDRESS 0x0400 -#define ACPI_BASE_SIZE 0x80 - -#define GPIO_BASE_ADDRESS 0x0500 -#define GPIO_BASE_SIZE 0x100 - -#define SMBUS_BASE_ADDRESS 0xefa0 - -#ifndef __ACPI__ -#include - -/* Read Top of Low Memory (BMBOUND) */ -uint32_t nc_read_top_of_low_memory(void); -#endif - -#endif /* _BAYTRAIL_IOMAP_H_ */ diff --git a/src/soc/intel/fsp_baytrail/include/soc/iosf.h b/src/soc/intel/fsp_baytrail/include/soc/iosf.h deleted file mode 100644 index 0982da68db..0000000000 --- a/src/soc/intel/fsp_baytrail/include/soc/iosf.h +++ /dev/null @@ -1,346 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2013 Google, Inc. - * Copyright (C) 2016 Siemens AG - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef _BAYTRAIL_IOSF_H_ -#define _BAYTRAIL_IOSF_H_ - -#include -#include - -/* - * The Bay Trail SoC has a message network called IOSF Sideband. The access - * routines are through 3 registers in PCI config space of 00:00.0: - * MCR - control register - * MDR - data register - * MCRX - control register extension - * The extension register is only used for addresses that don't fit into the - * 8 bit register address. - */ - -#ifndef PCI_DEV -#define PCI_DEV(SEGBUS, DEV, FN) ( \ - (((SEGBUS) & 0xFFF) << 20) | \ - (((DEV) & 0x1F) << 15) | \ - (((FN) & 0x07) << 12)) -#endif -#define IOSF_PCI_DEV PCI_DEV(0,SOC_DEV,SOC_FUNC) - -#define MCR_REG 0xd0 -#define IOSF_OPCODE(x) ((x) << 24) -#define IOSF_PORT(x) ((0xff & (x)) << 16) -#define IOSF_REG(x) ((0xff & (x)) << 8) -#define IOSF_REG_UPPER(x) (((~0xff) & (x))) -#define IOSF_BYTE_EN_0 0x10 -#define IOSF_BYTE_EN_1 0x20 -#define IOSF_BYTE_EN_2 0x40 -#define IOSF_BYTE_EN_3 0x80 -#define IOSF_BYTE_EN \ - (IOSF_BYTE_EN_0 | IOSF_BYTE_EN_1 | IOSF_BYTE_EN_2 | IOSF_BYTE_EN_3) -#define MDR_REG 0xd4 -#define MCRX_REG 0xd8 - -uint32_t iosf_aunit_read(int reg); -void iosf_aunit_write(int reg, uint32_t val); -uint32_t iosf_cpu_bus_read(int reg); -void iosf_cpu_bus_write(int reg, uint32_t val); -uint32_t iosf_bunit_read(int reg); -void iosf_bunit_write(int reg, uint32_t val); -uint32_t iosf_dunit_read(int reg); -void iosf_dunit_write(int reg, uint32_t val); -/* Some registers are per channel while the globals live in dunit 0 */ -uint32_t iosf_dunit_ch0_read(int reg); -uint32_t iosf_dunit_ch1_read(int reg); -uint32_t iosf_punit_read(int reg); -void iosf_punit_write(int reg, uint32_t val); -uint32_t iosf_usbphy_read(int reg); -void iosf_usbphy_write(int reg, uint32_t val); -uint32_t iosf_ushphy_read(int reg); -void iosf_ushphy_write(int reg, uint32_t val); -uint32_t iosf_sec_read(int reg); -void iosf_sec_write(int reg, uint32_t val); -uint32_t iosf_port45_read(int reg); -void iosf_port45_write(int reg, uint32_t val); -uint32_t iosf_port46_read(int reg); -void iosf_port46_write(int reg, uint32_t val); -uint32_t iosf_port47_read(int reg); -void iosf_port47_write(int reg, uint32_t val); -uint32_t iosf_port55_read(int reg); -void iosf_port55_write(int reg, uint32_t val); -uint32_t iosf_port58_read(int reg); -void iosf_port58_write(int reg, uint32_t val); -uint32_t iosf_port59_read(int reg); -void iosf_port59_write(int reg, uint32_t val); -uint32_t iosf_port5a_read(int reg); -void iosf_port5a_write(int reg, uint32_t val); -uint32_t iosf_lpss_read(int reg); -void iosf_lpss_write(int reg, uint32_t val); -uint32_t iosf_ccu_read(int reg); -void iosf_ccu_write(int reg, uint32_t val); -uint32_t iosf_score_read(int reg); -void iosf_score_write(int reg, uint32_t val); -uint32_t iosf_scc_read(int reg); -void iosf_scc_write(int reg, uint32_t val); -uint32_t iosf_porta2_read(int reg); -void iosf_porta2_write(int reg, uint32_t val); -uint32_t iosf_ssus_read(int reg); -void iosf_ssus_write(int reg, uint32_t val); - -/* IOSF ports. */ -#define IOSF_PORT_AUNIT 0x00 /* IO Arbiter unit */ -#define IOSF_PORT_SYSMEMC 0x01 /* System Memory Controller */ -#define IOSF_PORT_DUNIT_CH0 0x07 /* DUNIT Channel 0 */ -#define IOSF_PORT_CPU_BUS 0x02 /* CPU Bus Interface Controller */ -#define IOSF_PORT_BUNIT 0x03 /* System Memory Arbiter/Bunit */ -#define IOSF_PORT_PMC 0x04 /* Power Management Controller */ -#define IOSF_PORT_GFX 0x06 /* Graphics Adapter */ -#define IOSF_PORT_DUNIT_CH1 0x07 /* DUNIT Channel 1 */ -#define IOSF_PORT_SYSMEMIO 0x0c /* System Memory IO */ -#define IOSF_PORT_USBPHY 0x43 /* USB PHY */ -#define IOSF_PORT_SEC 0x44 /* SEC */ -#define IOSF_PORT_0x45 0x45 -#define IOSF_PORT_0x46 0x46 -#define IOSF_PORT_0x47 0x47 -#define IOSF_PORT_SCORE 0x48 /* SCORE */ -#define IOSF_PORT_0x55 0x55 -#define IOSF_PORT_0x58 0x58 -#define IOSF_PORT_0x59 0x59 -#define IOSF_PORT_0x5a 0x5a -#define IOSF_PORT_USHPHY 0x61 /* USB XHCI PHY */ -#define IOSF_PORT_SCC 0x63 /* Storage Control Cluster */ -#define IOSF_PORT_LPSS 0xa0 /* LPSS - Low Power Subsystem */ -#define IOSF_PORT_0xa2 0xa2 -#define IOSF_PORT_SATAPHY 0xa3 /* SATA PHY */ -#define IOSF_PORT_PCIEPHY 0xa3 /* PCIE PHY */ -#define IOSF_PORT_SSUS 0xa8 /* SUS */ -#define IOSF_PORT_CCU 0xa9 /* Clock control unit. */ - -/* Read and write opcodes differ per port. */ -#define IOSF_OP_READ_AUNIT 0x10 -#define IOSF_OP_WRITE_AUNIT (IOSF_OP_READ_AUNIT | 1) -#define IOSF_OP_READ_SYSMEMC 0x10 -#define IOSF_OP_WRITE_SYSMEMC (IOSF_OP_READ_SYSMEMC | 1) -#define IOSF_OP_READ_CPU_BUS 0x10 -#define IOSF_OP_WRITE_CPU_BUS (IOSF_OP_READ_CPU_BUS | 1) -#define IOSF_OP_READ_BUNIT 0x10 -#define IOSF_OP_WRITE_BUNIT (IOSF_OP_READ_BUNIT | 1) -#define IOSF_OP_READ_PMC 0x06 -#define IOSF_OP_WRITE_PMC (IOSF_OP_READ_PMC | 1) -#define IOSF_OP_READ_GFX 0x00 -#define IOSF_OP_WRITE_GFX (IOSF_OP_READ_GFX | 1) -#define IOSF_OP_READ_SYSMEMIO 0x06 -#define IOSF_OP_WRITE_SYSMEMIO (IOSF_OP_READ_SYSMEMIO | 1) -#define IOSF_OP_READ_USBPHY 0x06 -#define IOSF_OP_WRITE_USBPHY (IOSF_OP_READ_USBPHY | 1) -#define IOSF_OP_READ_SEC 0x04 -#define IOSF_OP_WRITE_SEC (IOSF_OP_READ_SEC | 1) -#define IOSF_OP_READ_0x45 0x06 -#define IOSF_OP_WRITE_0x45 (IOSF_OP_READ_0x45 | 1) -#define IOSF_OP_READ_0x46 0x06 -#define IOSF_OP_WRITE_0x46 (IOSF_OP_READ_0x46 | 1) -#define IOSF_OP_READ_0x47 0x06 -#define IOSF_OP_WRITE_0x47 (IOSF_OP_READ_0x47 | 1) -#define IOSF_OP_READ_SCORE 0x06 -#define IOSF_OP_WRITE_SCORE (IOSF_OP_READ_SCORE | 1) -#define IOSF_OP_READ_0x55 0x04 -#define IOSF_OP_WRITE_0x55 (IOSF_OP_READ_0x55 | 1) -#define IOSF_OP_READ_0x58 0x06 -#define IOSF_OP_WRITE_0x58 (IOSF_OP_READ_0x58 | 1) -#define IOSF_OP_READ_0x59 0x06 -#define IOSF_OP_WRITE_0x59 (IOSF_OP_READ_0x59 | 1) -#define IOSF_OP_READ_0x5a 0x04 -#define IOSF_OP_WRITE_0x5a (IOSF_OP_READ_0x5a | 1) -#define IOSF_OP_READ_USHPHY 0x06 -#define IOSF_OP_WRITE_USHPHY (IOSF_OP_READ_USHPHY | 1) -#define IOSF_OP_READ_SCC 0x06 -#define IOSF_OP_WRITE_SCC (IOSF_OP_READ_SCC | 1) -#define IOSF_OP_READ_LPSS 0x06 -#define IOSF_OP_WRITE_LPSS (IOSF_OP_READ_LPSS | 1) -#define IOSF_OP_READ_0xa2 0x06 -#define IOSF_OP_WRITE_0xa2 (IOSF_OP_READ_0xa2 | 1) -#define IOSF_OP_READ_SATAPHY 0x00 -#define IOSF_OP_WRITE_SATAPHY (IOSF_OP_READ_SATAPHY | 1) -#define IOSF_OP_READ_PCIEPHY 0x00 -#define IOSF_OP_WRITE_PCIEPHY (IOSF_OP_READ_PCIEPHY | 1) -#define IOSF_OP_READ_SSUS 0x10 -#define IOSF_OP_WRITE_SSUS (IOSF_OP_READ_SSUS | 1) -#define IOSF_OP_READ_CCU 0x06 -#define IOSF_OP_WRITE_CCU (IOSF_OP_READ_CCU | 1) - -/* - * BUNIT Registers. - */ - -#define BNOCACHE 0x23 -/* BMBOUND has a 128MiB granularity. Highest address is 0xf8000000. */ -#define BUNIT_BMBOUND 0x25 -/* BMBOUND_HI describes the available RAM above 4GiB. It has a - * 256MiB granularity. Physical address bits 35:28 are compared with 31:24 - * bits in the BMBOUND_HI register. Also note that since BMBOUND has 128MiB - * granularity care needs to be taken with the e820 map to account for a hole - * in the RAM. */ -#define BUNIT_BMBOUND_HI 0x26 -#define BUNIT_MMCONF_REG 0x27 -/* The SMMRR registers define the SMM region in MiB granularity. */ -#define BUNIT_SMRCP 0x2b -#define BUNIT_SMRRAC 0x2c -#define BUNIT_SMRWAC 0x2d -#define BUNIT_SMRRL 0x2e -#define BUNIT_SMRRH 0x2f -# define BUNIT_SMRR_ENABLE (1 << 31) - -/* SA ID bits. */ -#define SAI_IA_UNTRUSTED (1 << 0) -#define SAI_IA_SMM (1 << 2) -#define SAI_IA_BOOT (1 << 4) - -/* - * DUNIT Registers. - */ - -#define DRP 0x00 -# define DRP_DIMM0_RANK0_EN (0x01 << 0) -# define DRP_DIMM0_RANK1_EN (0x01 << 1) -# define DRP_DIMM1_RANK0_EN (0x01 << 2) -# define DRP_DIMM1_RANK1_EN (0x01 << 3) -# define DRP_RANK_MASK (DRP_DIMM0_RANK0_EN | DRP_DIMM0_RANK1_EN | \ - DRP_DIMM1_RANK0_EN | DRP_DIMM1_RANK1_EN) -#define DTR0 0x01 -# define DTR0_SPEED_MASK 0x03 -# define DTR0_SPEED_800 0x00 -# define DTR0_SPEED_1066 0x01 -# define DTR0_SPEED_1333 0x02 -# define DTR0_SPEED_1600 0x03 - -/* - * PUNIT Registers - */ -#define SB_BIOS_CONFIG 0x06 -# define SB_BIOS_CONFIG_ECC_EN (1 << 31) -# define SB_BIOS_CONFIG_DUAL_CH_DIS (1 << 30) -# define SB_BIOS_CONFIG_EFF_ECC (1 << 29) -# define SB_BIOS_CONFIG_EFF_DUAL_CH_DIS (1 << 28) -# define SB_BIOS_CONFIG_PERF_MODE (1 << 17) -# define SB_BIOS_CONFIG_PDM_MODE (1 << 16) -# define SB_BIOS_CONFIG_DDRIO_PWRGATE (1 << 8) -# define SB_BIOS_CONFIG_GFX_TURBO_DIS (1 << 7) -# define SB_BIOS_CONFIG_PS2_EN_VNN (1 << 3) -# define SB_BIOS_CONFIG_PS2_EN_VCC (1 << 2) -# define SB_BIOS_CONFIG_PCIE_PLLOFFOK (1 << 1) -# define SB_BIOS_CONFIG_USB_CACHING_EN (1 << 0) -#define BIOS_RESET_CPL 0x05 -# define BIOS_RESET_CPL_ALL_DONE (1 << 1) -# define BIOS_RESET_CPL_RESET_DONE (1 << 0) -#define PUNIT_PWRGT_CONTROL 0x60 -#define PUNIT_PWRGT_STATUS 0x61 -#define PUNIT_GPU_EC_VIRUS 0xd2 - -#define PUNIT_SOC_POWER_BUDGET 0x02 -#define PUNIT_SOC_ENERGY_CREDIT 0x03 -#define PUNIT_PTMC 0x80 -#define PUNIT_GFXT 0x88 -#define PUNIT_VEDT 0x89 -#define PUNIT_ISPT 0x8c -#define PUNIT_PTPS 0xb2 -#define PUNIT_TE_AUX0 0xb5 -#define PUNIT_TE_AUX1 0xb6 -#define PUNIT_TE_AUX2 0xb7 -#define PUNIT_TE_AUX3 0xb8 -#define PUNIT_TTE_VRIccMax 0xb9 -#define PUNIT_TTE_VRHot 0xba -#define PUNIT_TTE_XXPROCHOT 0xbb -#define PUNIT_TTE_SLM0 0xbc -#define PUNIT_TTE_SLM1 0xbd -#define PUNIT_TTE_SWT 0xbf - -/* - * LPSS Registers - */ -#define LPSS_SIO_DMA1_CTL 0x280 -#define LPSS_I2C1_CTL 0x288 -#define LPSS_I2C2_CTL 0x290 -#define LPSS_I2C3_CTL 0x298 -#define LPSS_I2C4_CTL 0x2a0 -#define LPSS_I2C5_CTL 0x2a8 -#define LPSS_I2C6_CTL 0x2b0 -#define LPSS_I2C7_CTL 0x2b8 -#define LPSS_SIO_DMA2_CTL 0x240 -#define LPSS_PWM1_CTL 0x248 -#define LPSS_PWM2_CTL 0x250 -#define LPSS_HSUART1_CTL 0x258 -#define LPSS_HSUART2_CTL 0x260 -#define LPSS_SPI_CTL 0x268 -# define LPSS_CTL_ACPI_INT_EN (1 << 21) -# define LPSS_CTL_PCI_CFG_DIS (1 << 20) -# define LPSS_CTL_SNOOP (1 << 18) -# define LPSS_CTL_NOSNOOP (1 << 19) -# define LPSS_CTL_PM_CAP_PRSNT (1 << 1) - -/* - * SCC Registers - */ -#define SCC_SD_CTL 0x504 -#define SCC_SDIO_CTL 0x508 -#define SCC_MMC_CTL 0x50c -# define SCC_CTL_PCI_CFG_DIS (1 << 0) -# define SCC_CTL_ACPI_INT_EN (1 << 1) - -/* - * CCU Registers - */ - -#define PLT_CLK_CTRL_0 0x3c -#define PLT_CLK_CTRL_1 0x40 -#define PLT_CLK_CTRL_2 0x44 -#define PLT_CLK_CTRL_3 0x48 -#define PLT_CLK_CTRL_4 0x4c -#define PLT_CLK_CTRL_5 0x50 -# define PLT_CLK_CTRL_19P2MHZ_FREQ (0 << 1) -# define PLT_CLK_CTRL_25MHZ_FREQ (1 << 1) -# define PLT_CLK_CTRL_SELECT_FREQ (1 << 0) - -/* - * USBPHY Registers - */ -#define USBPHY_COMPBG 0x7f04 -#define USBPHY_PER_PORT_LANE0 0x4100 -#define USBPHY_PER_PORT_RCOMP_HS_PULLUP0 0x4122 -#define USBPHY_PER_PORT_LANE1 0x4200 -#define USBPHY_PER_PORT_RCOMP_HS_PULLUP1 0x4222 -#define USBPHY_PER_PORT_LANE2 0x4300 -#define USBPHY_PER_PORT_RCOMP_HS_PULLUP2 0x4322 -#define USBPHY_PER_PORT_LANE3 0x4400 -#define USBPHY_PER_PORT_RCOMP_HS_PULLUP3 0x4422 - -/* - * USHPHY Registers - */ -#define USHPHY_CDN_PLL_CONTROL 0x03c0 -#define USHPHY_CDN_VCO_START_CAL_POINT 0x0054 -#define USHPHY_CCDRLF 0x8040 -#define USHPHY_PEAKING_AMP_CONFIG_DIAG 0x80a8 -#define USHPHY_OFFSET_COR_CONFIG_DIAG 0x80b0 -#define USHPHY_VGA_GAIN_CONFIG_DIAG 0x8080 -#define USHPHY_REE_DAC_CONTROL 0x80b8 -#define USHPHY_CDN_U1_POWER_STATE_DEF 0x0000 - -/* - * LPE Registers - */ -#define LPE_PCICFGCTR1 0x0500 -# define LPE_PCICFGCTR1_PCI_CFG_DIS (1 << 0) -# define LPE_PCICFGCTR1_ACPI_INT_EN (1 << 1) - -#endif /* _BAYTRAIL_IOSF_H_ */ diff --git a/src/soc/intel/fsp_baytrail/include/soc/irq.h b/src/soc/intel/fsp_baytrail/include/soc/irq.h deleted file mode 100644 index de8fc03cde..0000000000 --- a/src/soc/intel/fsp_baytrail/include/soc/irq.h +++ /dev/null @@ -1,164 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2013 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef _BAYTRAIL_IRQ_H_ -#define _BAYTRAIL_IRQ_H_ - -#define PIRQA_APIC_IRQ 16 -#define PIRQB_APIC_IRQ 17 -#define PIRQC_APIC_IRQ 18 -#define PIRQD_APIC_IRQ 19 -#define PIRQE_APIC_IRQ 20 -#define PIRQF_APIC_IRQ 21 -#define PIRQG_APIC_IRQ 22 -#define PIRQH_APIC_IRQ 23 -/* The below IRQs are for when devices are in ACPI mode. Active low. */ -#define LPE_DMA0_IRQ 24 -#define LPE_DMA1_IRQ 25 -#define LPE_SSP0_IRQ 26 -#define LPE_SSP1_IRQ 27 -#define LPE_SSP2_IRQ 28 -#define LPE_IPC2HOST_IRQ 29 -#define LPSS_I2C1_IRQ 32 -#define LPSS_I2C2_IRQ 33 -#define LPSS_I2C3_IRQ 34 -#define LPSS_I2C4_IRQ 35 -#define LPSS_I2C5_IRQ 36 -#define LPSS_I2C6_IRQ 37 -#define LPSS_I2C7_IRQ 38 -#define LPSS_HSUART1_IRQ 39 -#define LPSS_HSUART2_IRQ 40 -#define LPSS_SPI_IRQ 41 -#define LPSS_DMA1_IRQ 42 -#define LPSS_DMA2_IRQ 43 -#define SCC_EMMC_IRQ 44 -#define SCC_SDIO_IRQ 46 -#define SCC_SD_IRQ 47 -#define GPIO_NC_IRQ 48 -#define GPIO_SC_IRQ 49 -#define GPIO_SUS_IRQ 50 -/* GPIO direct / dedicated IRQs. */ -#define GPIO_S0_DED_IRQ_0 51 -#define GPIO_S0_DED_IRQ_1 52 -#define GPIO_S0_DED_IRQ_2 53 -#define GPIO_S0_DED_IRQ_3 54 -#define GPIO_S0_DED_IRQ_4 55 -#define GPIO_S0_DED_IRQ_5 56 -#define GPIO_S0_DED_IRQ_6 57 -#define GPIO_S0_DED_IRQ_7 58 -#define GPIO_S0_DED_IRQ_8 59 -#define GPIO_S0_DED_IRQ_9 60 -#define GPIO_S0_DED_IRQ_10 61 -#define GPIO_S0_DED_IRQ_11 62 -#define GPIO_S0_DED_IRQ_12 63 -#define GPIO_S0_DED_IRQ_13 64 -#define GPIO_S0_DED_IRQ_14 65 -#define GPIO_S0_DED_IRQ_15 66 -#define GPIO_S5_DED_IRQ_0 67 -#define GPIO_S5_DED_IRQ_1 68 -#define GPIO_S5_DED_IRQ_2 69 -#define GPIO_S5_DED_IRQ_3 70 -#define GPIO_S5_DED_IRQ_4 71 -#define GPIO_S5_DED_IRQ_5 72 -#define GPIO_S5_DED_IRQ_6 73 -#define GPIO_S5_DED_IRQ_7 74 -#define GPIO_S5_DED_IRQ_8 75 -#define GPIO_S5_DED_IRQ_9 76 -#define GPIO_S5_DED_IRQ_10 77 -#define GPIO_S5_DED_IRQ_11 78 -#define GPIO_S5_DED_IRQ_12 79 -#define GPIO_S5_DED_IRQ_13 80 -#define GPIO_S5_DED_IRQ_14 81 -#define GPIO_S5_DED_IRQ_15 82 -/* DIRQs - Two levels of expansion to evaluate to numeric constants for ASL. */ -#define _GPIO_S0_DED_IRQ(slot) GPIO_S0_DED_IRQ_##slot -#define _GPIO_S5_DED_IRQ(slot) GPIO_S5_DED_IRQ_##slot -#define GPIO_S0_DED_IRQ(slot) _GPIO_S0_DED_IRQ(slot) -#define GPIO_S5_DED_IRQ(slot) _GPIO_S5_DED_IRQ(slot) - -/* PIC IRQ settings. */ -#define PIRQ_PIC_IRQ3 0x3 -#define PIRQ_PIC_IRQ4 0x4 -#define PIRQ_PIC_IRQ5 0x5 -#define PIRQ_PIC_IRQ6 0x6 -#define PIRQ_PIC_IRQ7 0x7 -#define PIRQ_PIC_IRQ9 0x9 -#define PIRQ_PIC_IRQ10 0xa -#define PIRQ_PIC_IRQ11 0xb -#define PIRQ_PIC_IRQ12 0xc -#define PIRQ_PIC_IRQ14 0xe -#define PIRQ_PIC_IRQ15 0xf -#define PIRQ_PIC_IRQDISABLE 0x80 -#define PIRQ_PIC_UNKNOWN_UNUSED 0xff - -/* Overloaded term, but these values determine the per device route. */ -#define PIRQA 0 -#define PIRQB 1 -#define PIRQC 2 -#define PIRQD 3 -#define PIRQE 4 -#define PIRQF 5 -#define PIRQG 6 -#define PIRQH 7 - -/* These registers live behind the ILB_BASE_ADDRESS */ -#define ACTL 0x00 -# define SCIS_MASK 0x07 -# define SCIS_IRQ9 0x00 -# define SCIS_IRQ10 0x01 -# define SCIS_IRQ11 0x02 -# define SCIS_IRQ20 0x04 -# define SCIS_IRQ21 0x05 -# define SCIS_IRQ22 0x06 -# define SCIS_IRQ23 0x07 - -/* In each mainboard directory there should exist a header file irqroute.h that - * defines the PCI_DEV_PIRQ_ROUTES and PIRQ_PIC_ROUTES macros which - * consist of PCI_DEV_PIRQ_ROUTE and PIRQ_PIC entries. */ - -#if !defined(__ASSEMBLER__) && !defined(__ACPI__) -#include - -#define NUM_OF_PCI_DEVS 32 -#define NUM_PIRQS 8 - -struct baytrail_irq_route { - /* Per device configuration. */ - uint16_t pcidev[NUM_OF_PCI_DEVS]; - /* Route path for each internal PIRQx in PIC mode. */ - uint8_t pic[NUM_PIRQS]; -}; - -extern const struct baytrail_irq_route global_baytrail_irq_route; - -#define DEFINE_IRQ_ROUTES \ - const struct baytrail_irq_route global_baytrail_irq_route = { \ - .pcidev = { PCI_DEV_PIRQ_ROUTES, }, \ - .pic = { PIRQ_PIC_ROUTES, }, \ - } - -#define PCI_DEV_PIRQ_ROUTE(dev_, a_, b_, c_, d_) \ - [dev_] = ((PIRQ ## d_) << 12) | ((PIRQ ## c_) << 8) | \ - ((PIRQ ## b_) << 4) | ((PIRQ ## a_) << 0) - -#define PIRQ_PIC(pirq_, pic_irq_) \ - [PIRQ ## pirq_] = PIRQ_PIC_IRQ ## pic_irq_ - -/* used for ACPI only */ -#define PCIE_BRIDGE_DEV(prefix_, dev_, a_, b_, c_, d_) - -#endif /* !defined(__ASSEMBLER__) && !defined(__ACPI__) */ - -#endif /* _BAYTRAIL_IRQ_H_ */ diff --git a/src/soc/intel/fsp_baytrail/include/soc/lpc.h b/src/soc/intel/fsp_baytrail/include/soc/lpc.h deleted file mode 100644 index defd34a2f5..0000000000 --- a/src/soc/intel/fsp_baytrail/include/soc/lpc.h +++ /dev/null @@ -1,109 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2013 Google Inc. - * Copyright (C) 2013-2014 Sage Electronic Engineering, LLC. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef _BAYTRAIL_LPC_H_ -#define _BAYTRAIL_LPC_H_ - -/* PCI config registers in LPC bridge. */ -#define REVID 0x08 -#define ABASE 0x40 /* IO BAR */ -#define PBASE 0x44 /* MEM BAR */ -#define GBASE 0x48 /* IO BAR */ -#define IOBASE 0x4c /* MEM BAR */ -#define IBASE 0x50 /* MEM BAR */ -#define SBASE 0x54 /* MEM BAR */ -#define MPBASE 0x58 /* MEM BAR */ -#define PUBASE 0x5c -#define SET_BAR_ENABLE 0x02 -#define UART_CONT 0x80 -#define RCBA 0xf0 -#define RCBA_ENABLE 0x01 - -#define ILB_ACTL 0 -#define ILB_MC 0x4 -#define ILB_PIRQA_ROUT 0x8 -#define ILB_PIRQB_ROUT 0x9 -#define ILB_PIRQC_ROUT 0xA -#define ILB_PIRQD_ROUT 0xB -#define ILB_PIRQE_ROUT 0xC -#define ILB_PIRQF_ROUT 0xD -#define ILB_PIRQG_ROUT 0xE -#define ILB_PIRQH_ROUT 0xF -#define ILB_SERIRQ_CNTL 0x10 -#define SCNT_CONTINUOUS_MODE (1 << 7) -#define SCNT_QUIET_MODE 0 -#define ILB_IR00 0x20 -#define ILB_IR01 0x22 -#define ILB_IR02 0x24 -#define ILB_IR03 0x26 -#define ILB_IR04 0x28 -#define ILB_IR05 0x2A -#define ILB_IR06 0x2C -#define ILB_IR07 0x2E -#define ILB_IR08 0x30 -#define ILB_IR09 0x32 -#define ILB_IR10 0x34 -#define ILB_IR11 0x36 -#define ILB_IR12 0x38 -#define ILB_IR13 0x3A -#define ILB_IR14 0x3C -#define ILB_IR15 0x3E -#define ILB_IR16 0x40 -#define ILB_IR17 0x42 -#define ILB_IR18 0x44 -#define ILB_IR19 0x46 -#define ILB_IR20 0x48 -#define ILB_IR21 0x4A -#define ILB_IR22 0x4C -#define ILB_IR23 0x4E -#define ILB_IR24 0x50 -#define ILB_IR25 0x52 -#define ILB_IR26 0x54 -#define ILB_IR27 0x56 -#define ILB_IR28 0x58 -#define ILB_IR29 0x5A -#define ILB_IR30 0x5C -#define ILB_IR31 0x5E -#define ILB_OIC 0x60 -#define SIRQEN (1 << 12) -#define AEN (1 << 8) - -#define RID_A_STEPPING_START 1 -#define RID_B_STEPPING_START 5 -#define RID_C_STEPPING_START 0xe -#define RID_D_STEPPING_START 0x11 - -enum baytrail_stepping { - STEP_A0, - STEP_A1, - STEP_B0, - STEP_B1, - STEP_B2, - STEP_B3, - STEP_C0, - STEP_D0, -}; - -/* Registers behind the RCBA_BASE_ADDRESS bar. */ -#define GCS 0x00 -# define BILD (1 << 0) - -/* Default IO range claimed by the LPC devices. The upper bound is exclusive. */ -#define LPC_DEFAULT_IO_RANGE_LOWER 0 -#define LPC_DEFAULT_IO_RANGE_UPPER 0x1000 -#define IO_APIC_RANGE_SIZE 0x1000 - -#endif /* _BAYTRAIL_LPC_H_ */ diff --git a/src/soc/intel/fsp_baytrail/include/soc/msr.h b/src/soc/intel/fsp_baytrail/include/soc/msr.h deleted file mode 100644 index 8edab59bdf..0000000000 --- a/src/soc/intel/fsp_baytrail/include/soc/msr.h +++ /dev/null @@ -1,34 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2013 Google, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef _BAYTRAIL_MSR_H_ -#define _BAYTRAIL_MSR_H_ - -#define MSR_BSEL_CR_OVERCLOCK_CONTROL 0xcd -#define MSR_PLATFORM_INFO 0xce -#define MSR_PKG_CST_CONFIG_CONTROL 0xe2 -#define MSR_POWER_MISC 0x120 -#define MSR_POWER_CTL 0x1fc -#define MSR_PKG_POWER_SKU_UNIT 0x606 -#define MSR_PKG_POWER_LIMIT 0x610 -#define MSR_IACORE_RATIOS 0x66a -#define MSR_IACORE_TURBO_RATIOS 0x66c -#define MSR_IACORE_VIDS 0x66b -#define MSR_IACORE_TURBO_VIDS 0x66d - -/* Read BCLK from MSR */ -unsigned int bus_freq_khz(void); - -#endif /* _BAYTRAIL_MSR_H_ */ diff --git a/src/soc/intel/fsp_baytrail/include/soc/nvs.h b/src/soc/intel/fsp_baytrail/include/soc/nvs.h deleted file mode 100644 index df2fc60d71..0000000000 --- a/src/soc/intel/fsp_baytrail/include/soc/nvs.h +++ /dev/null @@ -1,72 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2008-2009 coresystems GmbH - * Copyright (C) 2011 Google Inc - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef _BAYTRAIL_NVS_H_ -#define _BAYTRAIL_NVS_H_ - -#include - -typedef struct { - /* Miscellaneous */ - u16 osys; /* 0x00 - Operating System */ - u8 smif; /* 0x02 - SMI function call ("TRAP") */ - u8 prm0; /* 0x03 - SMI function call parameter */ - u8 prm1; /* 0x04 - SMI function call parameter */ - u8 scif; /* 0x05 - SCI function call (via _L00) */ - u8 prm2; /* 0x06 - SCI function call parameter */ - u8 prm3; /* 0x07 - SCI function call parameter */ - u8 lckf; /* 0x08 - Global Lock function for EC */ - u8 prm4; /* 0x09 - Lock function parameter */ - u8 prm5; /* 0x0a - Lock function parameter */ - u32 p80d; /* 0x0b - Debug port (IO 0x80) value */ - u8 lids; /* 0x0f - LID state (open = 1) */ - u8 pwrs; /* 0x10 - Power state (AC = 1) */ - u8 pcnt; /* 0x11 - Processor Count */ - u8 tpmp; /* 0x12 - TPM Present and Enabled */ - u8 tlvl; /* 0x13 - Throttle Level */ - u8 ppcm; /* 0x14 - Maximum P-state usable by OS */ - u8 rsvd1[11]; - - /* Device Config */ - u8 s5u0; /* 0x20 - Enable USB0 in S5 */ - u8 s5u1; /* 0x21 - Enable USB1 in S5 */ - u8 s3u0; /* 0x22 - Enable USB0 in S3 */ - u8 s3u1; /* 0x23 - Enable USB1 in S3 */ - u8 tact; /* 0x24 - Thermal Active trip point */ - u8 tpsv; /* 0x25 - Thermal Passive trip point */ - u8 tcrt; /* 0x26 - Thermal Critical trip point */ - u8 dpte; /* 0x27 - Enable DPTF */ - u8 rsvd2[8]; - - /* Base Addresses */ - u32 obsolete_cmem; /* 0x30 - CBMEM TOC */ - u32 tolm; /* 0x34 - Top of Low Memory */ - u32 cbmc; /* 0x38 - coreboot memconsole */ - u8 rsvd3[196]; - - /* Pad 0x0100-0x0fff */ - u8 rsvd4[3840]; - - /* Baytrail LPSS (0x1000) */ - device_nvs_t dev; -} __packed global_nvs_t; - -void acpi_create_gnvs(global_nvs_t *gnvs); - -/* Used in SMM to find the ACPI GNVS address */ -global_nvs_t *smm_get_gnvs(void); - -#endif /* _BAYTRAIL_NVS_H_ */ diff --git a/src/soc/intel/fsp_baytrail/include/soc/pattrs.h b/src/soc/intel/fsp_baytrail/include/soc/pattrs.h deleted file mode 100644 index 7b46345a47..0000000000 --- a/src/soc/intel/fsp_baytrail/include/soc/pattrs.h +++ /dev/null @@ -1,60 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2013 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef _PATTRS_H_ -#define _PATTRS_H_ - -#include -#include - -enum { - IACORE_MIN, - IACORE_LFM, - IACORE_MAX, - IACORE_TURBO, - IACORE_END -}; - -/* The pattrs structure is a common place to stash pertinent information - * about the processor or platform. Instead of going to the source (msrs, cpuid) - * every time an attribute is needed use the pattrs structure. - */ -struct pattrs { - msr_t platform_id; - msr_t platform_info; - int iacore_ratios[IACORE_END]; - int iacore_vids[IACORE_END]; - uint32_t cpuid; - int revid; - int stepping; - const void *microcode_patch; - int address_bits; - int num_cpus; - unsigned int bclk_khz; -}; - -/* This is just to hide the abstraction w/o relying on how the underlying - * storage is allocated. */ -#define PATTRS_GLOB_NAME __global_pattrs -#define DEFINE_PATTRS struct pattrs PATTRS_GLOB_NAME -extern DEFINE_PATTRS; - -static inline const struct pattrs *pattrs_get(void) -{ - return &PATTRS_GLOB_NAME; -} - - -#endif /* _PATTRS_H_ */ diff --git a/src/soc/intel/fsp_baytrail/include/soc/pci_devs.h b/src/soc/intel/fsp_baytrail/include/soc/pci_devs.h deleted file mode 100644 index 5e5b8071df..0000000000 --- a/src/soc/intel/fsp_baytrail/include/soc/pci_devs.h +++ /dev/null @@ -1,216 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2013 Google Inc. - * Copyright (C) 2013 Sage Electronic Engineering, LLC. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef _BAYTRAIL_PCI_DEVS_H_ -#define _BAYTRAIL_PCI_DEVS_H_ - -#include - -#define BUS0 0 - -/* All these devices live on bus 0 with the associated device and function */ - -/* SoC transaction router */ -#define SOC_DEV 0x0 -#define SOC_FUNC 0 -# define SOC_DEVFN_SOC PCI_DEVFN(SOC_DEV,SOC_FUNC) - - -/* Graphics and Display */ -#define GFX_DEV 0x2 -#define GFX_FUNC 0 -# define SOC_DEVFN_GFX PCI_DEVFN(GFX_DEV,GFX_FUNC) - -/* MIPI */ -#define MIPI_DEV 0x3 -#define MIPI_FUNC 0 -# define SOC_DEVFN_MIPI PCI_DEVFN(MIPI_DEV,MIPI_FUNC) - - -/* SDIO Port */ -#define EMMC_DEV 0x10 -#define EMMC_FUNC 0 -# define SOC_DEVFN_EMMC PCI_DEVFN(EMMC_DEV,EMMC_FUNC) - -/* SDIO Port */ -#define SDIO_DEV 0x11 -#define SDIO_FUNC 0 -# define SOC_DEVFN_SDIO PCI_DEVFN(SDIO_DEV,SDIO_FUNC) - -/* SD Port */ -#define SD_DEV 0x12 -#define SD_FUNC 0 -# define SOC_DEVFN_SD PCI_DEVFN(SD_DEV,SD_FUNC) - -/* SATA */ -#define SATA_DEV 0x13 -#define SATA_FUNC 0 -# define SOC_DEVFN_SATA PCI_DEVFN(SATA_DEV,SATA_FUNC) - -/* xHCI */ -#define XHCI_DEV 0x14 -#define XHCI_FUNC 0 -# define XHCI_FUS_REG 0xE0 -# define XHCI_FUNC_DISABLE (1 << 0) -# define XHCI_USB2PR_REG 0xD0 -# define SOC_DEVFN_XHCI PCI_DEVFN(XHCI_DEV,XHCI_FUNC) - -/* LPE Audio */ -#define LPE_DEV 0x15 -#define LPE_FUNC 0 -# define SOC_DEVFN_LPE PCI_DEVFN(LPE_DEV,LPE_FUNC) - -/* OTG */ -#define OTG_DEV 0x16 -#define OTG_FUNC 0 -# define SOC_DEVFN_OTG PCI_DEVFN(LPE_DEV,LPE_FUNC) - -/* MMC Port */ -#define MMC45_DEV 0x17 -#define MMC45_FUNC 0 -# define SOC_DEVFN_MMC45 PCI_DEVFN(MMC45_DEV,MMC45_FUNC) - -/* Serial IO 1 */ -#define SIO1_DEV 0x18 -# define SIO_DMA1_DEV SIO1_DEV -# define SIO_DMA1_FUNC 0 -# define I2C1_DEV SIO1_DEV -# define I2C1_FUNC 1 -# define I2C2_DEV SIO1_DEV -# define I2C2_FUNC 2 -# define I2C3_DEV SIO1_DEV -# define I2C3_FUNC 3 -# define I2C4_DEV SIO1_DEV -# define I2C4_FUNC 4 -# define I2C5_DEV SIO1_DEV -# define I2C5_FUNC 5 -# define I2C6_DEV SIO1_DEV -# define I2C6_FUNC 6 -# define I2C7_DEV SIO1_DEV -# define I2C7_FUNC 7 -# define SOC_DEVFN_SIO_DMA1 PCI_DEVFN(SIO_DMA1_DEV,SIO_DMA1_FUNC) -# define SOC_DEVFN_I2C1 PCI_DEVFN(I2C1_DEV,I2C1_FUNC) -# define SOC_DEVFN_I2C2 PCI_DEVFN(I2C2_DEV,I2C2_FUNC) -# define SOC_DEVFN_I2C3 PCI_DEVFN(I2C3_DEV,I2C3_FUNC) -# define SOC_DEVFN_I2C4 PCI_DEVFN(I2C4_DEV,I2C4_FUNC) -# define SOC_DEVFN_I2C5 PCI_DEVFN(I2C5_DEV,I2C5_FUNC) -# define SOC_DEVFN_I2C6 PCI_DEVFN(I2C6_DEV,I2C6_FUNC) -# define SOC_DEVFN_I2C7 PCI_DEVFN(I2C7_DEV,I2C7_FUNC) - -#define PCH_DEV_SLOT_I2C1 I2C1_DEV - -/* Trusted Execution Engine */ -#define TXE_DEV 0x1a -#define TXE_FUNC 0 -# define SOC_DEVFN_TXE PCI_DEVFN(TXE_DEV,TXE_FUNC) - -/* HD Audio */ -#define HDA_DEV 0x1b -#define HDA_FUNC 0 -# define SOC_DEVFN_HDA PCI_DEVFN(HDA_DEV,HDA_FUNC) - -/* PCIe Ports */ -#define PCIE_DEV 0x1c -# define PCIE_PORT1_DEV PCIE_DEV -# define PCIE_PORT1_FUNC 0 -# define PCIE_PORT2_DEV PCIE_DEV -# define PCIE_PORT2_FUNC 1 -# define PCIE_PORT3_DEV PCIE_DEV -# define PCIE_PORT3_FUNC 2 -# define PCIE_PORT4_DEV PCIE_DEV -# define PCIE_PORT4_FUNC 3 -# define SOC_DEVFN_PCIE_PORT1 PCI_DEVFN(PCIE_DEV,PCIE_PORT1_FUNC) -# define SOC_DEVFN_PCIE_PORT2 PCI_DEVFN(PCIE_DEV,PCIE_PORT2_FUNC) -# define SOC_DEVFN_PCIE_PORT3 PCI_DEVFN(PCIE_DEV,PCIE_PORT3_FUNC) -# define SOC_DEVFN_PCIE_PORT4 PCI_DEVFN(PCIE_DEV,PCIE_PORT4_FUNC) - -/* EHCI */ -#define EHCI_DEV 0x1d -#define EHCI_FUNC 0 -# define SOC_DEVFN_EHCI PCI_DEVFN(EHCI_DEV,EHCI_FUNC) - -/* Serial IO 2 */ -#define SIO2_DEV 0x1e -# define SIO_DMA2_DEV SIO2_DEV -# define SIO_DMA2_FUNC 0 -# define PWM1_DEV SIO2_DEV -# define PWM1_FUNC 1 -# define PWM2_DEV SIO2_DEV -# define PWM2_FUNC 2 -# define HSUART1_DEV SIO2_DEV -# define HSUART1_FUNC 3 -# define HSUART2_DEV SIO2_DEV -# define HSUART2_FUNC 4 -# define SPI_DEV SIO2_DEV -# define SPI_FUNC 5 -# define SOC_DEVFN_SIO_DMA2 PCI_DEVFN(SIO_DMA2_DEV,SIO_DMA2_FUNC) -# define SOC_DEVFN_PWM1 PCI_DEVFN(PWM1_DEV,PWM1_FUNC) -# define SOC_DEVFN_PWM2 PCI_DEVFN(PWM2_DEV,PWM2_FUNC) -# define SOC_DEVFN_HSUART1 PCI_DEVFN(HSUART1_DEV,HSUART1_FUNC) -# define SOC_DEVFN_HSUART2 PCI_DEVFN(HSUART2_DEV,HSUART2_FUNC) -# define SOC_DEVFN_SPI PCI_DEVFN(SPI_DEV,SPI_FUNC) - - -/* Platform Controller Unit */ -#define PCU_DEV 0x1f -# define LPC_DEV PCU_DEV -# define LPC_FUNC 0 -# define PCH_DEVFN_LPC PCI_DEVFN(LPC_DEV,LPC_FUNC) -# define LPC_BDF PCI_DEV(0, LPC_DEV, LPC_FUNC) - -# define SMBUS_DEV PCU_DEV -# define SMBUS_FUNC 3 -# define SOC_DEVFN_SMBUS PCI_DEVFN(SMBUS_DEV,SMBUS_FUNC) - -#define SOC_DEVID 0x0f00 -#define GFX_DEVID 0x0f31 -#define MIPI_DEVID 0x0f38 -#define EMMC_DEVID 0x0f14 -#define SDIO_DEVID 0x0f15 -#define SD_DEVID 0x0f16 -#define IDE1_DEVID 0x0f20 -#define IDE2_DEVID 0x0f21 -#define AHCI1_DEVID 0x0f22 -#define AHCI2_DEVID 0x0f23 -#define XHCI_DEVID 0x0f35 -#define LPE_DEVID 0x0f28 -#define OTG_DEVID 0x0f37 -#define MMC45_DEVID 0x0f50 -#define SIO_DMA1_DEVID 0x0f40 -#define I2C1_DEVID 0x0f41 -#define I2C2_DEVID 0x0f42 -#define I2C3_DEVID 0x0f43 -#define I2C4_DEVID 0x0f44 -#define I2C5_DEVID 0x0f45 -#define I2C6_DEVID 0x0f46 -#define I2C7_DEVID 0x0f47 -#define TXE_DEVID 0x0f18 -#define HDA_DEVID 0x0f04 -#define PCIE_PORT1_DEVID 0x0f48 -#define PCIE_PORT2_DEVID 0x0f4a -#define PCIE_PORT3_DEVID 0x0f4c -#define PCIE_PORT4_DEVID 0x0f4e -#define EHCI_DEVID 0x0f34 -#define SIO_DMA2_DEVID 0x0f06 -#define PWM1_DEVID 0x0f08 -#define PWM2_DEVID 0x0f09 -#define HSUART1_DEVID 0x0f0a -#define HSUART2_DEVID 0x0f0c -#define SPI_DEVID 0xf0e -#define LPC_DEVID 0x0f1c -#define SMBUS_DEVID 0x0f12 - -#endif /* _BAYTRAIL_PCI_DEVS_H_ */ diff --git a/src/soc/intel/fsp_baytrail/include/soc/pcie.h b/src/soc/intel/fsp_baytrail/include/soc/pcie.h deleted file mode 100644 index 9d2d3de53e..0000000000 --- a/src/soc/intel/fsp_baytrail/include/soc/pcie.h +++ /dev/null @@ -1,98 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2013 Google, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef _BAYTRAIL_PCIE_H_ -#define _BAYTRAIL_PCIE_H_ - -/* PCIe root port config space registers. */ -#define XCAP 0x40 -# define SI (1 << 24) -#define DCAP 0x44 -# define MPS_MASK 0x7 -#define DCTL_DSTS 0x48 -# define URE (1 << 3) -# define FEE (1 << 2) -# define NFE (1 << 1) -# define CEE (1 << 0) -#define LCAP 0x4c -# define L1EXIT_SHIFT 15 -# define L1EXIT_MASK (0x7 << L1EXIT_SHIFT) -#define LCTL 0x50 -# define CCC (1 << 6) -# define RL (1 << 5) -# define LD (1 << 4) -#define LSTS 0x52 -#define SLCAP 0x54 -# define SLN_SHIFT 19 -# define SLS_SHIFT 15 -# define SLV_SHIFT 7 -# define HPC (1 << 6) -# define HPS (1 << 5) -#define SLCTL_SLSTS 0x58 -# define PDS (1 << 22) -#define DCAP2 0x64 -# define OBFFS (0x3 << 18) -# define LTRMS (1 << 11) -#define DSTS2 0x68 -# define OBFFEN (3 << 13) -# define LTRME (1 << 10) -# define CTD (1 << 4) -#define CHCFG 0xd0 -# define UPSD (1 << 24) -# define UNRS (1 << 15) -# define UPRS (1 << 14) -#define MPC2 0xd4 -# define IPF (1 << 11) -# define LSTP (1 << 6) -# define EOIFD (1 << 1) -#define MPC 0xd8 -# define CCEL_SHIFT 15 -# define CCEL_MASK (0x7 << CCEL_SHIFT) -#define RPPGEN 0xe0 -# define RPSCGEN (1 << 15) -# define LCLKREQEN (1 << 13) -# define BBCLKREQEN (1 << 12) -# define SRDLCGEN (1 << 11) -# define SRDBCGEN (1 << 10) -# define RPDLCGEN (1 << 9) -# define RPDBCGEN (1 << 8) -#define PWRCTL 0xe8 -# define RPL1SQPOL (1 << 1) -# define RPDTSQPOL (1 << 0) -#define PHYCTL2_IOSFBCTL 0xf4 -# define PLL_OFF_EN (1 << 8) -# define TDFT (3 << 14) -# define TXCFGCHWAIT (3 << 12) -# define SIID (3 << 26) -#define STRPFUSECFG 0xfc -# define LANECFG_SHIFT 14 -# define LANECFG_MASK (0x3 << LANECFG_SHIFT) -#define AERCH 0x100 -#define NFTS 0x314 -#define L0SC 0x318 -#define CFG2 0x320 -# define CSREN (1 << 22) -# define LATGC_SHIFT 6 -# define LATGC_MASK (0x7 << LATGC_SHIFT) -#define PCIEDBG 0x324 -# define SPCE (1 << 5) -#define PCIESTS1 0x328 -#define PCIEALC 0x338 -#define RTP 0x33c -#define PHYCTL4 0x408 -# define SQDIS (1 << 27) - - -#endif /* _BAYTRAIL_PCIE_H_ */ diff --git a/src/soc/intel/fsp_baytrail/include/soc/pmc.h b/src/soc/intel/fsp_baytrail/include/soc/pmc.h deleted file mode 100644 index 9e588addae..0000000000 --- a/src/soc/intel/fsp_baytrail/include/soc/pmc.h +++ /dev/null @@ -1,292 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2013 Google Inc. - * Copyright (C) 2013-2014 Sage Electronic Engineering, LLC. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef _BAYTRAIL_PMC_H_ -#define _BAYTRAIL_PMC_H_ - -#include - -#define IOCOM1 0x3f8 - -/* Memory mapped IO registers behind PMC_BASE_ADDRESS */ -#define PRSTS 0x00 -# define PMC_WDT_STS (1 << 15) -# define SEC_GBLRST_STS (1 << 7) -# define SEC_WDT_STS (1 << 6) -# define WOL_OVR_WK_STS (1 << 5) -# define PMC_WAKE_STS (1 << 4) -#define PMC_CFG 0x08 -# define SPS (1 << 5) -# define NO_REBOOT (1 << 4) -# define SX_ENT_TO_EN (1 << 3) -# define TIMING_T581_SHIFT (0) -# define TIMING_T581_MASK (3 << TIMING_T581_SHIFT) -# define TIMING_T581_10uS (0 << TIMING_T581_SHIFT) -# define TIMING_T581_100uS (1 << TIMING_T581_SHIFT) -# define TIMING_T581_1mS (2 << TIMING_T581_SHIFT) -# define TIMING_T581_10mS (3 << TIMING_T581_SHIFT) -#define VLV_PM_STS 0x0c -# define PMC_MSG_FULL_STS (1 << 24) -# define PMC_MSG_4_FULL_STS (1 << 23) -# define PMC_MSG_3_FULL_STS (1 << 22) -# define PMC_MSG_2_FULL_STS (1 << 21) -# define PMC_MSG_1_FULL_STS (1 << 20) -# define CODE_REQ (1 << 8) -# define HPR_ENT_TO (1 << 2) -# define SX_ENT_TO (1 << 1) -#define GEN_PMCON1 0x20 -# define UART_EN (1 << 24) -# define DISB (1 << 23) -# define MEM_SR (1 << 21) -# define SRS (1 << 20) -# define CTS (1 << 19) -# define MS4V (1 << 18) -# define PWR_FLR (1 << 16) -# define PME_B0_S5_DIS (1 << 15) -# define SUS_PWR_FLR (1 << 14) -# define WOL_EN_OVRD (1 << 13) -# define DIS_SLP_X_STRCH_SUS_UP (1 << 12) -# define GEN_RST_STS (1 << 9) -# define RPS (1 << 2) -# define AFTERG3_EN (1 << 0) -#define GEN_PMCON2 0x24 -# define SLPSX_STR_POL_LOCK (1 << 18) -# define BIOS_PCI_EXP_EN (1 << 10) -# define PWRBTN_LVL (1 << 9) -# define SMI_LOCK (1 << 4) -#define ETR 0x48 -# define CF9LOCK (1 << 31) -# define LTR_DEF (1 << 22) -# define IGNORE_HPET (1 << 21) -# define CF9GR (1 << 20) -# define CWORWRE (1 << 18) -#define FUNC_DIS 0x34 -# define SIO_DMA2_DIS (1 << 0) -# define PWM1_DIS (1 << 1) -# define PWM2_DIS (1 << 2) -# define HSUART1_DIS (1 << 3) -# define HSUART2_DIS (1 << 4) -# define SPI_DIS (1 << 5) -# define SDIO_DIS (1 << 9) -# define SD_DIS (1 << 10) -# define MMC_DIS (1 << 11) -# define HDA_DIS (1 << 12) -# define LPE_DIS (1 << 13) -# define OTG_DIS (1 << 14) -# define XHCI_DIS (1 << 15) -# define SATA_DIS (1 << 17) -# define EHCI_DIS (1 << 18) -# define TXE_DIS (1 << 19) -# define PCIE_PORT1_DIS (1 << 20) -# define PCIE_PORT2_DIS (1 << 21) -# define PCIE_PORT3_DIS (1 << 22) -# define PCIE_PORT4_DIS (1 << 23) -# define SIO_DMA1_DIS (1 << 24) -# define I2C1_DIS (1 << 25) -# define I2C2_DIS (1 << 26) -# define I2C3_DIS (1 << 27) -# define I2C4_DIS (1 << 28) -# define I2C5_DIS (1 << 29) -# define I2C6_DIS (1 << 30) -# define I2C7_DIS (1 << 31) -#define FUNC_DIS2 0x38 -# define USH_SS_PHY_DIS (1 << 2) -# define OTG_SS_PHY_DIS (1 << 1) -# define SMBUS_DIS (1 << 0) -#define GPIO_ROUT 0x58 -# define ROUTE_MASK 3 -# define ROUTE_NONE 0 -# define ROUTE_SMI 1 -# define ROUTE_SCI 2 -#define PLT_CLK_CTL_0 0x60 -#define PLT_CLK_CTL_1 0x64 -#define PLT_CLK_CTL_2 0x68 -#define PLT_CLK_CTL_3 0x6c -#define PLT_CLK_CTL_4 0x70 -#define PLT_CLK_CTL_5 0x74 -# define CLK_FREQ_25MHZ (0x0 << 2) -# define CLK_FREQ_19P2MHZ (0x1 << 2) -# define CLK_CTL_D3_LPE (0x0 << 0) -# define CLK_CTL_ON (0x1 << 0) -# define CLK_CTL_OFF (0x2 << 0) -#define PME_STS 0xc0 -#define GPE_LEVEL_EDGE 0xc4 -# define GPE_EDGE 0 -# define GPE_LEVEL 1 -#define GPE_POLARITY 0xc8 -# define GPE_ACTIVE_HIGH 1 -# define GPE_ACTIVE_LOW 0 -#define LOCK 0xcc - -/* IO Mapped registers behind ACPI_BASE_ADDRESS */ -#define PM1_STS 0x00 -#define WAK_STS (1 << 15) -#define PCIEXPWAK_STS (1 << 14) -#define USB_STS (1 << 13) -#define PRBTNOR_STS (1 << 11) -#define RTC_STS (1 << 10) -#define PWRBTN_STS (1 << 8) -#define GBL_STS (1 << 5) -#define TMROF_STS (1 << 0) -#define PM1_EN 0x02 -#define PCIEXPWAK_DIS (1 << 14) -#define USB_WAKE_EN (1 << 13) -#define RTC_EN (1 << 10) -#define PWRBTN_EN (1 << 8) -#define GBL_EN (1 << 5) -#define TMROF_EN (1 << 0) -#define PM1_CNT 0x04 -#define GBL_RLS (1 << 2) -#define BM_RLD (1 << 1) -#define SCI_EN (1 << 0) -#define PM1_TMR 0x08 -#define GPE0_STS 0x20 -#define CORE_GPIO_STS7 (1 << 31) -#define CORE_GPIO_STS6 (1 << 30) -#define CORE_GPIO_STS5 (1 << 29) -#define CORE_GPIO_STS4 (1 << 28) -#define CORE_GPIO_STS3 (1 << 27) -#define CORE_GPIO_STS2 (1 << 26) -#define CORE_GPIO_STS1 (1 << 25) -#define CORE_GPIO_STS0 (1 << 24) -#define SUS_GPIO_STS7 (1 << 23) -#define SUS_GPIO_STS6 (1 << 22) -#define SUS_GPIO_STS5 (1 << 21) -#define SUS_GPIO_STS4 (1 << 20) -#define SUS_GPIO_STS3 (1 << 19) -#define SUS_GPIO_STS2 (1 << 18) -#define SUS_GPIO_STS1 (1 << 17) -#define SUS_GPIO_STS0 (1 << 16) -#define PME_B0_STS_BIT 13 -#define PME_B0_STS (1 << PME_B0_STS_BIT) -#define BATLOW_STS (1 << 10) -#define PCI_EXP_STS (1 << 9) -#define PCIE_WAKE3_STS (1 << 8) -#define PCIE_WAKE2_STS (1 << 7) -#define PCIE_WAKE1_STS (1 << 6) -#define GUNIT_SCI_STS (1 << 5) -#define PUNIT_SCI_STS (1 << 4) -#define PCIE_WAKE0_STS (1 << 3) -#define SWGPE_STS (1 << 2) -#define HOT_PLUG_STS (1 << 1) -#define GPE0_EN 0x28 -#define CORE_GPIO_EN7 (1 << 31) -#define CORE_GPIO_EN6 (1 << 30) -#define CORE_GPIO_EN5 (1 << 29) -#define CORE_GPIO_EN4 (1 << 28) -#define CORE_GPIO_EN3 (1 << 27) -#define CORE_GPIO_EN2 (1 << 26) -#define CORE_GPIO_EN1 (1 << 25) -#define CORE_GPIO_EN0 (1 << 24) -#define SUS_GPIO_EN7_BIT 23 -#define SUS_GPIO_EN7 (1 << SUS_GPIO_EN7_BIT) -#define SUS_GPIO_EN6_BIT 22 -#define SUS_GPIO_EN6 (1 << SUS_GPIO_EN6_BIT) -#define SUS_GPIO_EN5_BIT 21 -#define SUS_GPIO_EN5 (1 << SUS_GPIO_EN5_BIT) -#define SUS_GPIO_EN4_BIT 20 -#define SUS_GPIO_EN4 (1 << SUS_GPIO_EN4_BIT) -#define SUS_GPIO_EN3_BIT 19 -#define SUS_GPIO_EN3 (1 << SUS_GPIO_EN3_BIT) -#define SUS_GPIO_EN2_BIT 18 -#define SUS_GPIO_EN2 (1 << SUS_GPIO_EN2_BIT) -#define SUS_GPIO_EN1_BIT 17 -#define SUS_GPIO_EN1 (1 << SUS_GPIO_EN1_BIT) -#define SUS_GPIO_EN0_BIT 16 -#define SUS_GPIO_EN0 (1 << SUS_GPIO_EN0_BIT) -#define PME_B0_EN (1 << 13) -#define BATLOW_EN (1 << 10) -#define PCI_EXP_EN (1 << 9) -#define PCIE_WAKE3_EN (1 << 8) -#define PCIE_WAKE2_EN (1 << 7) -#define PCIE_WAKE1_EN (1 << 6) -#define PCIE_WAKE0_EN (1 << 3) -#define SWGPE_EN (1 << 2) -#define HOT_PLUG_EN (1 << 1) -#define _ACPI_ENABLE_WAKE_SUS_GPIO(x) SUS_GPIO_EN##x##_BIT -#define ACPI_ENABLE_WAKE_SUS_GPIO(x) _ACPI_ENABLE_WAKE_SUS_GPIO(x) -#define SMI_EN 0x30 -#define INTEL_USB2_EN (1 << 18) // Intel-Specific USB2 SMI logic -#define USB_EN (1 << 17) // Legacy USB2 SMI logic -#define PERIODIC_EN (1 << 14) // SMI on PERIODIC_STS in SMI_STS -#define TCO_EN (1 << 13) // Enable TCO Logic (BIOSWE et al) -#define BIOS_RLS (1 << 7) // asserts SCI on bit set -#define SWSMI_TMR_EN (1 << 6) // start software smi timer on bit set -#define APMC_EN (1 << 5) // Writes to APM_CNT cause SMI# -#define SLP_SMI_EN (1 << 4) // Write to SLP_EN in PM1_CNT asserts SMI# -#define BIOS_EN (1 << 2) // Assert SMI# on setting GBL_RLS bit -#define EOS (1 << 1) // End of SMI (deassert SMI#) -#define GBL_SMI_EN (1 << 0) // SMI# generation at all? -#define SMI_STS 0x34 -#define ALT_GPIO_SMI 0x38 -#define UPRWC 0x3c -# define UPRWC_WR_EN (1 << 1) // USB Per-Port Registers Write Enable -#define GPE_CTRL 0x40 -#define PM2A_CNT_BLK 0x50 -#define TCO_RLD 0x60 -#define TCO_STS 0x64 -# define SECOND_TO_STS (1 << 17) -# define TCO_TIMEOUT (1 << 3) -#define TCO1_CNT 0x68 -# define TCO_LOCK (1 << 12) -# define TCO_TMR_HALT (1 << 11) -#define TCO_TMR 0x70 - -/* I/O ports */ -#define RST_CNT 0xcf9 -# define FULL_RST (1 << 3) -# define RST_CPU (1 << 2) -# define SYS_RST (1 << 1) - -#if !defined(__ASSEMBLER__) && !defined(__ACPI__) - -/* Track power state from reset to log events. */ -struct chipset_power_state { - uint16_t pm1_sts; - uint16_t pm1_en; - uint32_t pm1_cnt; - uint32_t gpe0_sts; - uint32_t gpe0_en; - uint32_t tco_sts; - uint32_t prsts; - uint32_t gen_pmcon1; - uint32_t gen_pmcon2; -} __packed; - -/* Power Management Utility Functions. */ -uint16_t get_pmbase(void); -uint32_t clear_smi_status(void); -uint16_t clear_pm1_status(void); -uint32_t clear_tco_status(void); -uint32_t clear_gpe_status(void); -uint32_t clear_alt_status(void); -void clear_pmc_status(void); -void enable_smi(uint32_t mask); -void disable_smi(uint32_t mask); -void enable_pm1(uint16_t events); -void enable_pm1_control(uint32_t mask); -void disable_pm1_control(uint32_t mask); -void enable_gpe(uint32_t mask); -void disable_gpe(uint32_t mask); -void disable_all_gpe(void); - -uint32_t chipset_prev_sleep_state(uint32_t clear); - -void southcluster_log_state(void); - -#endif /* !defined(__ASSEMBLER__) && !defined(__ACPI__) */ - -#endif /* _BAYTRAIL_PMC_H_ */ diff --git a/src/soc/intel/fsp_baytrail/include/soc/ramstage.h b/src/soc/intel/fsp_baytrail/include/soc/ramstage.h deleted file mode 100644 index 45fda9e937..0000000000 --- a/src/soc/intel/fsp_baytrail/include/soc/ramstage.h +++ /dev/null @@ -1,30 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2013 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef _BAYTRAIL_RAMSTAGE_H_ -#define _BAYTRAIL_RAMSTAGE_H_ - -#include - -/* The baytrail_init_pre_device() function is called prior to device - * initialization, but it's after console and cbmem has been reinitialized. */ -void baytrail_init_pre_device(void); -void baytrail_init_cpus(struct device *dev); -void southcluster_enable_dev(struct device *dev); -void scc_enable_acpi_mode(struct device *dev, int iosf_reg, int nvs_index); - -extern struct pci_operations soc_pci_ops; - -#endif /* _BAYTRAIL_RAMSTAGE_H_ */ diff --git a/src/soc/intel/fsp_baytrail/include/soc/romstage.h b/src/soc/intel/fsp_baytrail/include/soc/romstage.h deleted file mode 100644 index dce953993a..0000000000 --- a/src/soc/intel/fsp_baytrail/include/soc/romstage.h +++ /dev/null @@ -1,34 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2013 Google Inc. - * Copyright (C) 2014 Sage Electronic Engineering, LLC. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef _BAYTRAIL_ROMSTAGE_H_ -#define _BAYTRAIL_ROMSTAGE_H_ - -#include -#include - -void main(FSP_INFO_HEADER *fsp_info_header); - -#define NUM_ROMSTAGE_TS 4 - -void tco_disable(void); -void punit_init(void); -void early_mainboard_romstage_entry(void); -void late_mainboard_romstage_entry(void); -void get_func_disables(uint32_t *mask, uint32_t *mask2); -void byt_config_com1_and_enable(void); - -#endif /* _BAYTRAIL_ROMSTAGE_H_ */ diff --git a/src/soc/intel/fsp_baytrail/include/soc/smm.h b/src/soc/intel/fsp_baytrail/include/soc/smm.h deleted file mode 100644 index b6e24a8a0f..0000000000 --- a/src/soc/intel/fsp_baytrail/include/soc/smm.h +++ /dev/null @@ -1,21 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2013 Google Inc. - * Copyright (C) 2014 Sage Electronic Engineering, LLC. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef _BAYTRAIL_SMM_H_ -#define _BAYTRAIL_SMM_H_ - - -#endif /* _BAYTRAIL_SMM_H_ */ diff --git a/src/soc/intel/fsp_baytrail/include/soc/spi.h b/src/soc/intel/fsp_baytrail/include/soc/spi.h deleted file mode 100644 index 1ac0b59e56..0000000000 --- a/src/soc/intel/fsp_baytrail/include/soc/spi.h +++ /dev/null @@ -1,63 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2013 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef _BAYTRAIL_SPI_H_ -#define _BAYTRAIL_SPI_H_ - -#include - -/* These registers live behind SPI_BASE_ADDRESS. */ -#define HSFSTS 0x04 -# define FLOCKDN (0x1 << 15) -#define PREOP 0x94 -#define OPTYPE 0x96 -#define OPMENU0 0x98 -#define OPMENU1 0x9c -#define LVSCC 0xc4 -# define VCL (0x1 << 23) -# define EO(x) (((x) & 0xff) << 8) -# define WG_1_BYTE (0x0 << 2) -# define WG_64_BYTE (0x1 << 2) -# define BES_256_BYTE (0x0 << 0) -# define BES_4_KB (0x1 << 0) -# define BES_8_KB (0x2 << 0) -# define BES_64_KB (0x3 << 0) -#define UVSCC 0xc8 -#define SCS 0xf8 -# define SMIWPEN (0x1 << 7) -#define BCR 0xfc -# define EISS (0x1 << 5) -# define SRC_MASK (0x3 << 2) -# define SRC_CACHE_NO_PREFETCH (0x0 << 2) -# define SRC_NO_CACHE_NO_PREFETCH (0x1 << 2) -# define SRC_CACHE_PREFETCH (0x2 << 2) -# define BCR_LE (0x1 << 1) -# define BCR_WPD (0x1 << 0) - -/* - * SPI lockdown configuration. - */ -struct spi_config { - uint16_t preop; - uint16_t optype; - uint32_t opmenu[2]; - uint32_t lvscc; - uint32_t uvscc; -}; - -/* Return 0 on success < 0 on failure. */ -int mainboard_get_spi_config(struct spi_config *cfg); - -#endif /* _BAYTRAIL_SPI_H_ */ diff --git a/src/soc/intel/fsp_baytrail/include/soc/xhci.h b/src/soc/intel/fsp_baytrail/include/soc/xhci.h deleted file mode 100644 index d509b51a6a..0000000000 --- a/src/soc/intel/fsp_baytrail/include/soc/xhci.h +++ /dev/null @@ -1,52 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2013 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef BAYTRAIL_XHCI_H -#define BAYTRAIL_XHCI_H - -/* XHCI PCI Registers */ -#define XHCI_PWR_CTL_STS 0x74 -#define XHCI_USB2PR 0xd0 -#define XHCI_USB2PRM 0xd4 -#define XHCI_USB3PR 0xd8 -#define XHCI_USB3PRM 0xdc -#define XHCI_USB2PDO 0xe4 -#define XHCI_USB3PDO 0xe8 - -/* XHCI Memory Registers */ -#define XHCI_USB3_PORTSC(port) (0x4e0 + (port * 0x10)) -# define XHCI_USB3_PORTSC_CHST (0x7f << 17) -# define XHCI_USB3_PORTSC_WCE (1 << 25) /* Wake on Connect */ -# define XHCI_USB3_PORTSC_WDE (1 << 26) /* Wake on Disconnect */ -# define XHCI_USB3_PORTSC_WOE (1 << 27) /* Wake on Overcurrent */ -# define XHCI_USB3_PORTSC_WRC (1 << 19) /* Warm Reset Complete */ -# define XHCI_USB3_PORTSC_LWS (1 << 16) /* Link Write Strobe */ -# define XHCI_USB3_PORTSC_PED (1 << 1) /* Port Enabled/Disabled */ -# define XHCI_USB3_PORTSC_WPR (1 << 31) /* Warm Port Reset */ -# define XHCI_USB3_PORTSC_PLS (0xf << 5) /* Port Link State */ -# define XHCI_PLSR_DISABLED (4 << 5) /* Port is disabled */ -# define XHCI_PLSR_RXDETECT (5 << 5) /* Port is disconnected */ -# define XHCI_PLSR_POLLING (7 << 5) /* Port is polling */ -# define XHCI_PLSW_ENABLE (5 << 5) /* Enable port */ - -/* The Fuse register is incorrect for Baytrail-M so use hardcoded values */ -#define BYTM_USB2_PORT_COUNT 4 -#define BYTM_USB2_PORT_MAP 0xf -#define BYTM_USB3_PORT_COUNT 1 -#define BYTM_USB3_PORT_MAP 0x1 - -#define XHCI_RESET_TIMEOUT 100000 /* 100ms */ - -#endif /* BAYTRAIL_XHCI_H */ diff --git a/src/soc/intel/fsp_baytrail/iosf.c b/src/soc/intel/fsp_baytrail/iosf.c deleted file mode 100644 index 25f82ababd..0000000000 --- a/src/soc/intel/fsp_baytrail/iosf.c +++ /dev/null @@ -1,274 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2013 Google, Inc. - * Copyright (C) 2014 Sage Electronic Engineering, LLC. - * Copyright (C) 2016 Siemens AG - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include - -static inline void write_iosf_reg(int reg, uint32_t value) -{ - pci_s_write_config32(IOSF_PCI_DEV, reg, value); -} - -static inline uint32_t read_iosf_reg(int reg) -{ - return pci_s_read_config32(IOSF_PCI_DEV, reg); -} - -/* Common sequences for all the port accesses. */ -static uint32_t iosf_read_port(uint32_t cr, int reg) -{ - cr |= IOSF_REG(reg) | IOSF_BYTE_EN; - write_iosf_reg(MCRX_REG, IOSF_REG_UPPER(reg)); - write_iosf_reg(MCR_REG, cr); - return read_iosf_reg(MDR_REG); -} - -static void iosf_write_port(uint32_t cr, int reg, uint32_t val) -{ - cr |= IOSF_REG(reg) | IOSF_BYTE_EN; - write_iosf_reg(MDR_REG, val); - write_iosf_reg(MCRX_REG, IOSF_REG_UPPER(reg)); - write_iosf_reg(MCR_REG, cr); -} - -#define IOSF_READ(port) \ - IOSF_OPCODE(IOSF_OP_READ_##port) | IOSF_PORT(IOSF_PORT_##port) -#define IOSF_WRITE(port) \ - IOSF_OPCODE(IOSF_OP_WRITE_##port) | IOSF_PORT(IOSF_PORT_##port) - -uint32_t iosf_bunit_read(int reg) -{ - return iosf_read_port(IOSF_READ(BUNIT), reg); -} - -void iosf_bunit_write(int reg, uint32_t val) -{ - iosf_write_port(IOSF_WRITE(BUNIT), reg, val); -} - -uint32_t iosf_dunit_read(int reg) -{ - return iosf_read_port(IOSF_READ(SYSMEMC), reg); -} - -uint32_t iosf_dunit_ch0_read(int reg) -{ - return iosf_dunit_read(reg); -} - -uint32_t iosf_dunit_ch1_read(int reg) -{ - uint32_t cr = IOSF_OPCODE(IOSF_OP_READ_SYSMEMC) | - IOSF_PORT(IOSF_PORT_DUNIT_CH1); - return iosf_read_port(cr, reg); -} - -void iosf_dunit_write(int reg, uint32_t val) -{ - iosf_write_port(IOSF_WRITE(SYSMEMC), reg, val); -} - -uint32_t iosf_punit_read(int reg) -{ - return iosf_read_port(IOSF_READ(PMC), reg); -} - -void iosf_punit_write(int reg, uint32_t val) -{ - iosf_write_port(IOSF_WRITE(PMC), reg, val); -} - -uint32_t iosf_usbphy_read(int reg) -{ - return iosf_read_port(IOSF_READ(USBPHY), reg); -} - -void iosf_usbphy_write(int reg, uint32_t val) -{ - return iosf_write_port(IOSF_WRITE(USBPHY), reg, val); -} - -uint32_t iosf_ushphy_read(int reg) -{ - return iosf_read_port(IOSF_READ(USHPHY), reg); -} - -void iosf_ushphy_write(int reg, uint32_t val) -{ - return iosf_write_port(IOSF_WRITE(USHPHY), reg, val); -} - -uint32_t iosf_lpss_read(int reg) -{ - return iosf_read_port(IOSF_READ(LPSS), reg); -} - -void iosf_lpss_write(int reg, uint32_t val) -{ - return iosf_write_port(IOSF_WRITE(LPSS), reg, val); -} - -uint32_t iosf_ccu_read(int reg) -{ - return iosf_read_port(IOSF_READ(CCU), reg); -} - -void iosf_ccu_write(int reg, uint32_t val) -{ - return iosf_write_port(IOSF_WRITE(CCU), reg, val); -} - -uint32_t iosf_score_read(int reg) -{ - return iosf_read_port(IOSF_READ(SCORE), reg); -} - -void iosf_score_write(int reg, uint32_t val) -{ - return iosf_write_port(IOSF_WRITE(SCORE), reg, val); -} - -uint32_t iosf_scc_read(int reg) -{ - return iosf_read_port(IOSF_READ(SCC), reg); -} - -void iosf_scc_write(int reg, uint32_t val) -{ - return iosf_write_port(IOSF_WRITE(SCC), reg, val); -} - -uint32_t iosf_aunit_read(int reg) -{ - return iosf_read_port(IOSF_READ(AUNIT), reg); -} - -void iosf_aunit_write(int reg, uint32_t val) -{ - return iosf_write_port(IOSF_WRITE(AUNIT), reg, val); -} - -uint32_t iosf_cpu_bus_read(int reg) -{ - return iosf_read_port(IOSF_READ(CPU_BUS), reg); -} - -void iosf_cpu_bus_write(int reg, uint32_t val) -{ - return iosf_write_port(IOSF_WRITE(CPU_BUS), reg, val); -} - -uint32_t iosf_sec_read(int reg) -{ - return iosf_read_port(IOSF_READ(SEC), reg); -} - -void iosf_sec_write(int reg, uint32_t val) -{ - return iosf_write_port(IOSF_WRITE(SEC), reg, val); -} - -uint32_t iosf_port45_read(int reg) -{ - return iosf_read_port(IOSF_READ(0x45), reg); -} - -void iosf_port45_write(int reg, uint32_t val) -{ - return iosf_write_port(IOSF_WRITE(0x45), reg, val); -} - -uint32_t iosf_port46_read(int reg) -{ - return iosf_read_port(IOSF_READ(0x46), reg); -} - -void iosf_port46_write(int reg, uint32_t val) -{ - return iosf_write_port(IOSF_WRITE(0x46), reg, val); -} - -uint32_t iosf_port47_read(int reg) -{ - return iosf_read_port(IOSF_READ(0x47), reg); -} - -void iosf_port47_write(int reg, uint32_t val) -{ - return iosf_write_port(IOSF_WRITE(0x47), reg, val); -} - -uint32_t iosf_port55_read(int reg) -{ - return iosf_read_port(IOSF_READ(0x55), reg); -} - -void iosf_port55_write(int reg, uint32_t val) -{ - return iosf_write_port(IOSF_WRITE(0x55), reg, val); -} - -uint32_t iosf_port58_read(int reg) -{ - return iosf_read_port(IOSF_READ(0x58), reg); -} - -void iosf_port58_write(int reg, uint32_t val) -{ - return iosf_write_port(IOSF_WRITE(0x58), reg, val); -} - -uint32_t iosf_port59_read(int reg) -{ - return iosf_read_port(IOSF_READ(0x59), reg); -} - -void iosf_port59_write(int reg, uint32_t val) -{ - return iosf_write_port(IOSF_WRITE(0x59), reg, val); -} - -uint32_t iosf_port5a_read(int reg) -{ - return iosf_read_port(IOSF_READ(0x5a), reg); -} - -void iosf_port5a_write(int reg, uint32_t val) -{ - return iosf_write_port(IOSF_WRITE(0x5a), reg, val); -} - -uint32_t iosf_porta2_read(int reg) -{ - return iosf_read_port(IOSF_READ(0xa2), reg); -} - -void iosf_porta2_write(int reg, uint32_t val) -{ - return iosf_write_port(IOSF_WRITE(0xa2), reg, val); -} - -uint32_t iosf_ssus_read(int reg) -{ - return iosf_read_port(IOSF_READ(SSUS), reg); -} - -void iosf_ssus_write(int reg, uint32_t val) -{ - return iosf_write_port(IOSF_WRITE(SSUS), reg, val); -} diff --git a/src/soc/intel/fsp_baytrail/lpe.c b/src/soc/intel/fsp_baytrail/lpe.c deleted file mode 100644 index 91f8880a18..0000000000 --- a/src/soc/intel/fsp_baytrail/lpe.c +++ /dev/null @@ -1,186 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2013 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include -#include -#include -#include -#include -#include -#include "chip.h" - - -/* The LPE audio devices needs 1MiB of memory reserved aligned to a 512MiB - * address. Just take 1MiB @ 512MiB. */ -#define FIRMWARE_PHYS_BASE (512 << 20) -#define FIRMWARE_PHYS_LENGTH (1 << 20) -#define FIRMWARE_PCI_REG_BASE 0xa8 -#define FIRMWARE_PCI_REG_LENGTH 0xac -#define FIRMWARE_REG_BASE_C0 0x144000 -#define FIRMWARE_REG_LENGTH_C0 (FIRMWARE_REG_BASE_C0 + 4) - -static void assign_device_nvs(struct device *dev, u32 *field, unsigned int index) -{ - struct resource *res; - - res = find_resource(dev, index); - if (res) - *field = res->base; -} - -static void lpe_enable_acpi_mode(struct device *dev) -{ - static const struct reg_script ops[] = { - /* Disable PCI interrupt, enable Memory and Bus Master */ - REG_PCI_OR32(PCI_COMMAND, - PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER | (1<<10)), - /* Enable ACPI mode */ - REG_IOSF_OR(IOSF_PORT_0x58, LPE_PCICFGCTR1, - LPE_PCICFGCTR1_PCI_CFG_DIS | - LPE_PCICFGCTR1_ACPI_INT_EN), - REG_SCRIPT_END - }; - global_nvs_t *gnvs; - - /* Find ACPI NVS to update BARs */ - gnvs = (global_nvs_t *)cbmem_find(CBMEM_ID_ACPI_GNVS); - if (!gnvs) { - printk(BIOS_ERR, "Unable to locate Global NVS\n"); - return; - } - - /* Save BAR0, BAR1, and firmware base to ACPI NVS */ - assign_device_nvs(dev, &gnvs->dev.lpe_bar0, PCI_BASE_ADDRESS_0); - assign_device_nvs(dev, &gnvs->dev.lpe_bar1, PCI_BASE_ADDRESS_1); - assign_device_nvs(dev, &gnvs->dev.lpe_fw, FIRMWARE_PCI_REG_BASE); - - /* Device is enabled in ACPI mode */ - gnvs->dev.lpe_en = 1; - - /* Put device in ACPI mode */ - reg_script_run_on_dev(dev, ops); -} - -static void setup_codec_clock(struct device *dev) -{ - uint32_t reg; - u32 *clk_reg; - struct soc_intel_fsp_baytrail_config *config; - const char *freq_str; - - config = config_of(dev); - switch (config->lpe_codec_clk_freq) { - case 19: - freq_str = "19.2"; - reg = CLK_FREQ_19P2MHZ; - break; - case 25: - freq_str = "25"; - reg = CLK_FREQ_25MHZ; - break; - default: - printk(BIOS_DEBUG, "LPE codec clock not required.\n"); - return; - } - - /* Default to always running. */ - reg |= CLK_CTL_ON; - - if (config->lpe_codec_clk_num < 0 || config->lpe_codec_clk_num > 5) { - printk(BIOS_DEBUG, "Invalid LPE codec clock number.\n"); - return; - } - - printk(BIOS_DEBUG, "LPE Audio codec clock set to %sMHz.\n", freq_str); - - clk_reg = (u32 *)(PMC_BASE_ADDRESS + PLT_CLK_CTL_0); - clk_reg += config->lpe_codec_clk_num; - - write32(clk_reg, (read32(clk_reg) & ~0x7) | reg); -} - -static void lpe_stash_firmware_info(struct device *dev) -{ - struct resource *res; - struct resource *mmio; - const struct pattrs *pattrs = pattrs_get(); - - res = find_resource(dev, FIRMWARE_PCI_REG_BASE); - if (res == NULL) { - printk(BIOS_DEBUG, "LPE Firmware memory not found.\n"); - return; - } - - /* Continue using old way of informing firmware address / size. */ - pci_write_config32(dev, FIRMWARE_PCI_REG_BASE, res->base); - pci_write_config32(dev, FIRMWARE_PCI_REG_LENGTH, res->size); - - /* C0 and later steppings use an offset in the MMIO space. */ - if (pattrs->stepping >= STEP_C0) { - mmio = find_resource(dev, PCI_BASE_ADDRESS_0); - write32((u32 *)(uintptr_t)(mmio->base + FIRMWARE_REG_BASE_C0), - res->base); - write32((u32 *)(uintptr_t)(mmio->base + FIRMWARE_REG_LENGTH_C0), - res->size); - } -} - -static void lpe_init(struct device *dev) -{ - struct soc_intel_fsp_baytrail_config *config = config_of(dev); - - lpe_stash_firmware_info(dev); - - setup_codec_clock(dev); - - if (config->LpeAcpiModeEnable == LPE_ACPI_MODE_ENABLED) - lpe_enable_acpi_mode(dev); -} - -static void lpe_read_resources(struct device *dev) -{ - pci_dev_read_resources(dev); - - reserved_ram_resource(dev, FIRMWARE_PCI_REG_BASE, - FIRMWARE_PHYS_BASE >> 10, - FIRMWARE_PHYS_LENGTH >> 10); -} - -static const struct device_operations device_ops = { - .read_resources = lpe_read_resources, - .set_resources = pci_dev_set_resources, - .enable_resources = pci_dev_enable_resources, - .init = lpe_init, - .enable = NULL, - .scan_bus = NULL, - .ops_pci = &soc_pci_ops, -}; - -static const struct pci_driver southcluster __pci_driver = { - .ops = &device_ops, - .vendor = PCI_VENDOR_ID_INTEL, - .device = LPE_DEVID, -}; diff --git a/src/soc/intel/fsp_baytrail/lpss.c b/src/soc/intel/fsp_baytrail/lpss.c deleted file mode 100644 index 2ad6fb3804..0000000000 --- a/src/soc/intel/fsp_baytrail/lpss.c +++ /dev/null @@ -1,152 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2013 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include -#include - -#include "chip.h" - -static void dev_enable_acpi_mode(struct device *dev, int iosf_reg, int nvs_index) -{ - struct reg_script ops[] = { - /* Disable PCI interrupt, enable Memory and Bus Master */ - REG_PCI_OR32(PCI_COMMAND, - PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER | (1<<10)), - /* Enable ACPI mode */ - REG_IOSF_OR(IOSF_PORT_LPSS, iosf_reg, - LPSS_CTL_PCI_CFG_DIS | LPSS_CTL_ACPI_INT_EN), - REG_SCRIPT_END - }; - struct resource *bar; - global_nvs_t *gnvs; - - /* Find ACPI NVS to update BARs */ - gnvs = (global_nvs_t *)cbmem_find(CBMEM_ID_ACPI_GNVS); - if (!gnvs) { - printk(BIOS_ERR, "Unable to locate Global NVS\n"); - return; - } - - /* Save BAR0 and BAR1 to ACPI NVS */ - bar = find_resource(dev, PCI_BASE_ADDRESS_0); - if (bar) - gnvs->dev.lpss_bar0[nvs_index] = (u32)bar->base; - - bar = find_resource(dev, PCI_BASE_ADDRESS_1); - if (bar) - gnvs->dev.lpss_bar1[nvs_index] = (u32)bar->base; - - /* Device is enabled in ACPI mode */ - gnvs->dev.lpss_en[nvs_index] = 1; - - /* Put device in ACPI mode */ - reg_script_run_on_dev(dev, ops); -} - -static void dev_enable_snoop_and_pm(struct device *dev, int iosf_reg) -{ - struct reg_script ops[] = { - REG_IOSF_RMW(IOSF_PORT_LPSS, iosf_reg, - ~(LPSS_CTL_SNOOP | LPSS_CTL_NOSNOOP), - LPSS_CTL_SNOOP | LPSS_CTL_PM_CAP_PRSNT), - REG_SCRIPT_END, - }; - - reg_script_run_on_dev(dev, ops); -} - -static void dev_ctl_reg(struct device *dev, int *iosf_reg, int *nvs_index) -{ - *iosf_reg = -1; - *nvs_index = -1; -#define SET_IOSF_REG(name_) \ - case PCI_DEVFN(name_ ## _DEV, name_ ## _FUNC): \ - *iosf_reg = LPSS_ ## name_ ## _CTL; \ - *nvs_index = LPSS_NVS_ ## name_ - - switch (dev->path.pci.devfn) { - SET_IOSF_REG(SIO_DMA1); - break; - SET_IOSF_REG(SIO_DMA2); - break; - SET_IOSF_REG(PWM1); - break; - SET_IOSF_REG(PWM2); - break; - SET_IOSF_REG(HSUART1); - break; - SET_IOSF_REG(HSUART2); - break; - SET_IOSF_REG(SPI); - break; - } -} - -static void lpss_init(struct device *dev) -{ - struct soc_intel_fsp_baytrail_config *config = config_of(dev); - int iosf_reg, nvs_index; - - dev_ctl_reg(dev, &iosf_reg, &nvs_index); - - if (iosf_reg < 0) { - int slot = PCI_SLOT(dev->path.pci.devfn); - int func = PCI_FUNC(dev->path.pci.devfn); - printk(BIOS_DEBUG, "Could not find iosf_reg for %02x.%01x\n", - slot, func); - return; - } - dev_enable_snoop_and_pm(dev, iosf_reg); - - if (config->PcdLpssSioEnablePciMode == LPSS_PCI_MODE_DISABLE) - dev_enable_acpi_mode(dev, iosf_reg, nvs_index); -} - -static struct device_operations device_ops = { - .read_resources = pci_dev_read_resources, - .set_resources = pci_dev_set_resources, - .enable_resources = pci_dev_enable_resources, - .init = lpss_init, - .enable = NULL, - .scan_bus = NULL, - .ops_pci = &soc_pci_ops, -}; - -static const unsigned short pci_device_ids[] = { - SIO_DMA1_DEVID, - SIO_DMA2_DEVID, - PWM1_DEVID, - PWM2_DEVID, - HSUART1_DEVID, - HSUART2_DEVID, - SPI_DEVID, - 0, -}; - -static const struct pci_driver southcluster __pci_driver = { - .ops = &device_ops, - .vendor = PCI_VENDOR_ID_INTEL, - .devices = pci_device_ids, -}; diff --git a/src/soc/intel/fsp_baytrail/memmap.c b/src/soc/intel/fsp_baytrail/memmap.c deleted file mode 100644 index d8dcf49acb..0000000000 --- a/src/soc/intel/fsp_baytrail/memmap.c +++ /dev/null @@ -1,52 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2013 Google, Inc. - * Copyright (C) 2014 Sage Electronic Engineering, LLC. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include -#include -#include - -static uintptr_t smm_region_start(void) -{ - return (iosf_bunit_read(BUNIT_SMRRL) & 0xFFFF) << 20; -} - -static size_t smm_region_size(void) -{ - return CONFIG_SMM_TSEG_SIZE; -} - -/** @brief get the top of usable low memory from the FSP's HOB list - * - * The FSP's reserved memory sits just below the SMM region. The memory - * region below it is usable memory. - * - * The entire memory map is shown in northcluster.c - * - * @return pointer to the first byte of reserved memory - */ - -void *cbmem_top_chipset(void) -{ - return find_fsp_reserved_mem(*(void **)CBMEM_FSP_HOB_PTR); -} - -void smm_region(uintptr_t *start, size_t *size) -{ - *start = smm_region_start(); - *size = smm_region_size(); -} diff --git a/src/soc/intel/fsp_baytrail/northcluster.c b/src/soc/intel/fsp_baytrail/northcluster.c deleted file mode 100644 index 474ba84890..0000000000 --- a/src/soc/intel/fsp_baytrail/northcluster.c +++ /dev/null @@ -1,200 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2013 Google Inc. - * Copyright (C) 2013-2014 Sage Electronic Engineering, LLC. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -static const int legacy_hole_base_k = 0xa0000 / 1024; -static const int legacy_hole_size_k = 384; - -/* Host Memory Map: - * - * +--------------------------+ BMBOUND_HI - * | Usable DRAM | - * +--------------------------+ 4GiB - * | PCI Address Space | - * +--------------------------+ BMBOUND - * | TPM | - * +--------------------------+ IMR2 - * | TXE | - * +--------------------------+ IMR1 - * | iGD | - * +--------------------------+ - * | GTT | - * +--------------------------+ SMMRRH, IRM0 - * | TSEG | - * +--------------------------+ SMMRRL - * | FSP | - * +--------------------------+ SMMRRL - 2MB - * | Usable DRAM | - * +--------------------------+ FFFFF - * | ROM Area | - * +--------------------------+ A0000 - * | Usable DRAM | - * +--------------------------+ 0 - * - * Note that there are really only a few regions that need to enumerated w.r.t. - * coreboot's resource model: - * - * +--------------------------+ BMBOUND_HI - * | Cacheable/Usable | - * +--------------------------+ 4GiB - * - * +--------------------------+ BMBOUND - * | Uncacheable/Reserved | - * +--------------------------+ SMMRRH - * | Cacheable/Reserved | - * +--------------------------+ SMMRRL - 2MB - * | Cacheable/Usable | - * +--------------------------+ 0 - */ - -/* - * Get the top of low memory for use by ACPI - */ -uint32_t nc_read_top_of_low_memory(void) -{ - uint32_t fsp_mem_base = 0; - GetLowMemorySize(&fsp_mem_base); - - return fsp_mem_base; -} - -static int get_pcie_bar(u32 *base) -{ - u32 pciexbar_reg; - - *base = 0; - - pciexbar_reg = iosf_bunit_read(BUNIT_MMCONF_REG); - - if (!(pciexbar_reg & (1 << 0))) - return 0; - - *base = pciexbar_reg & ((1 << 31) | (1 << 30) | (1 << 29) | - (1 << 28)); - return 256; - -} - -static void add_fixed_resources(struct device *dev, int index) -{ - struct resource *resource; - - resource = new_resource(dev, index++); /* Local APIC */ - resource->base = LAPIC_DEFAULT_BASE; - resource->size = 0x00001000; - resource->flags = IORESOURCE_MEM | IORESOURCE_RESERVE | - IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED; - - mmio_resource(dev, index++, legacy_hole_base_k, legacy_hole_size_k); -} - -static void mc_add_dram_resources(struct device *dev) -{ - u32 bmbound, bsmmrrl; - int index = 0; - uint64_t highmem_size = 0; - uint32_t fsp_mem_base = 0; - - GetHighMemorySize(&highmem_size); - fsp_mem_base=(uint32_t)cbmem_top(); - - bmbound = iosf_bunit_read(BUNIT_BMBOUND); - bsmmrrl = iosf_bunit_read(BUNIT_SMRRL) << 20; - - if (bsmmrrl){ - printk(BIOS_DEBUG, "UMA, GTT & SMM memory location: 0x%x\n" - "UMA, GTT & SMM memory size: %dM\n", - bsmmrrl, (bmbound - bsmmrrl) >> 20); - - printk(BIOS_DEBUG, "FSP memory location: 0x%x\nFSP memory size: %dM\n", - fsp_mem_base, (bsmmrrl - fsp_mem_base) >> 20); - } - - printk(BIOS_INFO, "Available memory below 4GB: 0x%08x (%dM)\n", - fsp_mem_base, fsp_mem_base >> 20); - - /* Report the memory regions. */ - ram_resource(dev, index++, 0, legacy_hole_base_k); - ram_resource(dev, index++, legacy_hole_base_k + legacy_hole_size_k, - ((fsp_mem_base >> 10) - (legacy_hole_base_k + legacy_hole_size_k))); - - /* Mark SMM & FSP regions reserved */ - mmio_resource(dev, index++, fsp_mem_base >> 10, - (bmbound - fsp_mem_base) >> 10); - - if (highmem_size) { - ram_resource(dev, index++, 0x100000000 >> 10, highmem_size >> 10); - } - printk(BIOS_INFO, "Available memory above 4GB: %lluM\n", - highmem_size >> 20); - - add_fixed_resources(dev, index); -} - -static void nc_read_resources(struct device *dev) -{ - u32 pcie_config_base; - int buses; - - /* Call the normal read_resources */ - pci_dev_read_resources(dev); - - /* We use 0xcf as an unused index for our PCIe bar so that we find it again */ - buses = get_pcie_bar(&pcie_config_base); - if (buses) { - struct resource *resource = new_resource(dev, 0xcf); - mmconf_resource_init(resource, pcie_config_base, buses); - } - - /* Calculate and add DRAM resources. */ - mc_add_dram_resources(dev); -} - -static void nc_enable(struct device *dev) -{ - print_fsp_info(); -} - -static struct device_operations nc_ops = { - .read_resources = nc_read_resources, - .acpi_fill_ssdt_generator = generate_cpu_entries, - .set_resources = DEVICE_NOOP, - .enable_resources = NULL, - .init = NULL, - .enable = &nc_enable, - .scan_bus = NULL, - .ops_pci = &soc_pci_ops, -}; - -static const struct pci_driver nc_driver __pci_driver = { - .ops = &nc_ops, - .vendor = PCI_VENDOR_ID_INTEL, - .device = SOC_DEVID, -}; diff --git a/src/soc/intel/fsp_baytrail/placeholders.c b/src/soc/intel/fsp_baytrail/placeholders.c deleted file mode 100644 index e9a8757557..0000000000 --- a/src/soc/intel/fsp_baytrail/placeholders.c +++ /dev/null @@ -1,23 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include - - -void acpi_create_serialio_ssdt(acpi_header_t *ssdt) {} - -/* Rmodules don't like weak symbols. */ -u32 map_oprom_vendev(u32 vendev) { return vendev; } diff --git a/src/soc/intel/fsp_baytrail/pmutil.c b/src/soc/intel/fsp_baytrail/pmutil.c deleted file mode 100644 index 10838e3a99..0000000000 --- a/src/soc/intel/fsp_baytrail/pmutil.c +++ /dev/null @@ -1,383 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2013 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include -#include -#include -#include - -#include -#include -#include -#include -#include - -#if defined(__SIMPLE_DEVICE__) - -static const pci_devfn_t pcu_dev = PCI_DEV(0, PCU_DEV, 0); - -static inline pci_devfn_t get_pcu_dev(void) -{ - return pcu_dev; -} - -#else /* !__SIMPLE_DEVICE__ */ -#include -#include - -static struct device *pcu_dev; -static struct device *get_pcu_dev(void) -{ - if (pcu_dev == NULL) - pcu_dev = pcidev_on_root(PCU_DEV, 0); - return pcu_dev; -} -#endif - -uint16_t get_pmbase(void) -{ - return pci_read_config16(get_pcu_dev(), ABASE) & 0xfff8; -} - -static void print_num_status_bits(int num_bits, uint32_t status, - const char *bit_names[]) -{ - int i; - - if (!status) - return; - - for (i = num_bits - 1; i >= 0; i--) { - if (status & (1 << i)) { - if (bit_names[i]) - printk(BIOS_DEBUG, "%s ", bit_names[i]); - else - printk(BIOS_DEBUG, "BIT%d ", i); - } - } -} - -static void print_status_bits(uint32_t status, const char *bit_names[]) -{ - print_num_status_bits(32, status, bit_names); -} - -static uint32_t print_smi_status(uint32_t smi_sts) -{ - static const char *smi_sts_bits[] = { - [2] = "BIOS", - [4] = "SLP_SMI", - [5] = "APM", - [6] = "SWSMI_TMR", - [8] = "PM1", - [9] = "GPE0", - [12] = "DEVMON", - [13] = "TCO", - [14] = "PERIODIC", - [15] = "ILB", - [16] = "SMBUS_SMI", - [17] = "LEGACY_USB2", - [18] = "INTEL_USB2", - [20] = "PCI_EXP_SMI", - [26] = "SPI", - [28] = "PUNIT", - [29] = "GUNIT", - }; - - if (!smi_sts) - return 0; - - printk(BIOS_DEBUG, "SMI_STS: "); - print_status_bits(smi_sts, smi_sts_bits); - printk(BIOS_DEBUG, "\n"); - - return smi_sts; -} - -static uint32_t reset_smi_status(void) -{ - uint16_t pmbase = get_pmbase(); - uint32_t smi_sts = inl(pmbase + SMI_STS); - outl(smi_sts, pmbase + SMI_STS); - return smi_sts; -} - -uint32_t clear_smi_status(void) -{ - return print_smi_status(reset_smi_status()); -} - -void enable_smi(uint32_t mask) -{ - uint16_t pmbase = get_pmbase(); - uint32_t smi_en = inl(pmbase + SMI_EN); - smi_en |= mask; - outl(smi_en, pmbase + SMI_EN); -} - -void disable_smi(uint32_t mask) -{ - uint16_t pmbase = get_pmbase(); - uint32_t smi_en = inl(pmbase + SMI_EN); - smi_en &= ~mask; - outl(smi_en, pmbase + SMI_EN); -} - -void enable_pm1_control(uint32_t mask) -{ - uint16_t pmbase = get_pmbase(); - uint32_t pm1_cnt = inl(pmbase + PM1_CNT); - pm1_cnt |= mask; - outl(pm1_cnt, pmbase + PM1_CNT); -} - -void disable_pm1_control(uint32_t mask) -{ - uint16_t pmbase = get_pmbase(); - uint32_t pm1_cnt = inl(pmbase + PM1_CNT); - pm1_cnt &= ~mask; - outl(pm1_cnt, pmbase + PM1_CNT); -} - -static uint16_t reset_pm1_status(void) -{ - uint16_t pmbase = get_pmbase(); - uint16_t pm1_sts = inw(pmbase + PM1_STS); - outw(pm1_sts, pmbase + PM1_STS); - return pm1_sts; -} - -static uint16_t print_pm1_status(uint16_t pm1_sts) -{ - static const char *pm1_sts_bits[] = { - [0] = "TMROF", - [5] = "GBL", - [8] = "PWRBTN", - [10] = "RTC", - [11] = "PRBTNOR", - [13] = "USB", - [14] = "PCIEXPWAK", - [15] = "WAK", - }; - - if (!pm1_sts) - return 0; - - printk(BIOS_SPEW, "PM1_STS: "); - print_status_bits(pm1_sts, pm1_sts_bits); - printk(BIOS_SPEW, "\n"); - - return pm1_sts; -} - -uint16_t clear_pm1_status(void) -{ - return print_pm1_status(reset_pm1_status()); -} - -void enable_pm1(uint16_t events) -{ - outw(events, get_pmbase() + PM1_EN); -} - -static uint32_t print_tco_status(uint32_t tco_sts) -{ - static const char *tco_sts_bits[] = { - [3] = "TIMEOUT", - [17] = "SECOND_TO", - }; - - if (!tco_sts) - return 0; - - printk(BIOS_DEBUG, "TCO_STS: "); - print_status_bits(tco_sts, tco_sts_bits); - printk(BIOS_DEBUG, "\n"); - - return tco_sts; -} - -static uint32_t reset_tco_status(void) -{ - uint16_t pmbase = get_pmbase(); - uint32_t tco_sts = inl(pmbase + TCO_STS); - uint32_t tco_en = inl(pmbase + TCO1_CNT); - - outl(tco_sts, pmbase + TCO_STS); - return tco_sts & tco_en; -} - -uint32_t clear_tco_status(void) -{ - return print_tco_status(reset_tco_status()); -} - -void enable_gpe(uint32_t mask) -{ - uint16_t pmbase = get_pmbase(); - uint32_t gpe0_en = inl(pmbase + GPE0_EN); - gpe0_en |= mask; - outl(gpe0_en, pmbase + GPE0_EN); -} - -void disable_gpe(uint32_t mask) -{ - uint16_t pmbase = get_pmbase(); - uint32_t gpe0_en = inl(pmbase + GPE0_EN); - gpe0_en &= ~mask; - outl(gpe0_en, pmbase + GPE0_EN); -} - -void disable_all_gpe(void) -{ - disable_gpe(~0); -} - - -static uint32_t reset_gpe_status(void) -{ - uint16_t pmbase = get_pmbase(); - uint32_t gpe_sts = inl(pmbase + GPE0_STS); - outl(gpe_sts, pmbase + GPE0_STS); - return gpe_sts; -} - -static uint32_t print_gpe_sts(uint32_t gpe_sts) -{ - static const char *gpe_sts_bits[] = { - [1] = "HOTPLUG", - [2] = "SWGPE", - [3] = "PCIE_WAKE0", - [4] = "PUNIT", - [5] = "GUNIT", - [6] = "PCIE_WAKE1", - [7] = "PCIE_WAKE2", - [8] = "PCIE_WAKE3", - [9] = "PCI_EXP", - [10] = "BATLOW", - [13] = "PME_B0", - [16] = "SUS_GPIO_0", - [17] = "SUS_GPIO_1", - [18] = "SUS_GPIO_2", - [19] = "SUS_GPIO_3", - [20] = "SUS_GPIO_4", - [21] = "SUS_GPIO_5", - [22] = "SUS_GPIO_6", - [23] = "SUS_GPIO_7", - [24] = "CORE_GPIO_0", - [25] = "CORE_GPIO_1", - [26] = "CORE_GPIO_2", - [27] = "CORE_GPIO_3", - [28] = "CORE_GPIO_4", - [29] = "CORE_GPIO_5", - [30] = "CORE_GPIO_6", - [31] = "CORE_GPIO_7", - }; - - if (!gpe_sts) - return gpe_sts; - - printk(BIOS_DEBUG, "GPE0a_STS: "); - print_status_bits(gpe_sts, gpe_sts_bits); - printk(BIOS_DEBUG, "\n"); - - return gpe_sts; -} - -uint32_t clear_gpe_status(void) -{ - return print_gpe_sts(reset_gpe_status()); -} - -static uint32_t reset_alt_status(void) -{ - uint16_t pmbase = get_pmbase(); - uint32_t alt_gpio_smi = inl(pmbase + ALT_GPIO_SMI); - outl(alt_gpio_smi, pmbase + ALT_GPIO_SMI); - return alt_gpio_smi; -} - -static uint32_t print_alt_sts(uint32_t alt_gpio_smi) -{ - uint32_t alt_gpio_sts; - static const char *alt_gpio_smi_sts_bits[] = { - [0] = "SUS_GPIO_0", - [1] = "SUS_GPIO_1", - [2] = "SUS_GPIO_2", - [3] = "SUS_GPIO_3", - [4] = "SUS_GPIO_4", - [5] = "SUS_GPIO_5", - [6] = "SUS_GPIO_6", - [7] = "SUS_GPIO_7", - [8] = "CORE_GPIO_0", - [9] = "CORE_GPIO_1", - [10] = "CORE_GPIO_2", - [11] = "CORE_GPIO_3", - [12] = "CORE_GPIO_4", - [13] = "CORE_GPIO_5", - [14] = "CORE_GPIO_6", - [15] = "CORE_GPIO_7", - }; - - /* Status bits are in the upper 16 bits. */ - alt_gpio_sts = alt_gpio_smi >> 16; - if (!alt_gpio_sts) - return alt_gpio_smi; - - printk(BIOS_DEBUG, "ALT_GPIO_SMI: "); - print_num_status_bits(16, alt_gpio_sts, alt_gpio_smi_sts_bits); - printk(BIOS_DEBUG, "\n"); - - return alt_gpio_smi; -} - -uint32_t clear_alt_status(void) -{ - return print_alt_sts(reset_alt_status()); -} - -void clear_pmc_status(void) -{ - uint32_t prsts; - uint32_t gen_pmcon1; - - prsts = read32((u32 *)(PMC_BASE_ADDRESS + PRSTS)); - gen_pmcon1 = read32((u32 *)(PMC_BASE_ADDRESS + GEN_PMCON1)); - - /* Clear the status bits. The RPS field is cleared on a 0 write. */ - write32((u32 *)(PMC_BASE_ADDRESS + GEN_PMCON1), gen_pmcon1 & ~RPS); - write32((u32 *)(PMC_BASE_ADDRESS + PRSTS), prsts); -} - -int vbnv_cmos_failed(void) -{ - uint32_t gen_pmcon1; - int rtc_fail; - struct chipset_power_state *ps = cbmem_find(CBMEM_ID_POWER_STATE); - - if (ps != NULL) - gen_pmcon1 = ps->gen_pmcon1; - else - gen_pmcon1 = read32((u32 *)(PMC_BASE_ADDRESS + GEN_PMCON1)); - - rtc_fail = !!(gen_pmcon1 & RPS); - - if (rtc_fail) - printk(BIOS_DEBUG, "RTC failure.\n"); - - return rtc_fail; -} diff --git a/src/soc/intel/fsp_baytrail/ramstage.c b/src/soc/intel/fsp_baytrail/ramstage.c deleted file mode 100644 index 754c5f5c45..0000000000 --- a/src/soc/intel/fsp_baytrail/ramstage.c +++ /dev/null @@ -1,159 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2013 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include -#include -#include -#include -#include - -/* Global PATTRS */ -DEFINE_PATTRS; - -#define SHOW_PATTRS 1 - -static void detect_num_cpus(struct pattrs *attrs) -{ - int ecx = 0; - - while (1) { - struct cpuid_result leaf_b; - - leaf_b = cpuid_ext(0xb, ecx); - - /* Bay Trail doesn't have hyperthreading so just determine the - * number of cores by from level type (ecx[15:8] == * 2). */ - if ((leaf_b.ecx & 0xff00) == 0x0200) { - attrs->num_cpus = leaf_b.ebx & 0xffff; - break; - } - ecx++; - } -} - -static inline void fill_in_msr(msr_t *msr, int idx) -{ - *msr = rdmsr(idx); - if (SHOW_PATTRS) { - printk(BIOS_DEBUG, "msr(%x) = %08x%08x\n", - idx, msr->hi, msr->lo); - } -} - -static const char *stepping_str[] = { - "A0", "A1", "B0", "B1", "B2", "B3", "C0", "D0", -}; - -static void fill_in_pattrs(void) -{ - struct device *dev; - msr_t msr; - struct pattrs *attrs = (struct pattrs *)pattrs_get(); - - attrs->cpuid = cpuid_eax(1); - dev = pcidev_on_root(LPC_DEV, LPC_FUNC); - attrs->revid = pci_read_config8(dev, REVID); - /* The revision to stepping IDs have two values per metal stepping. */ - if (attrs->revid >= RID_D_STEPPING_START) { - attrs->stepping = (attrs->revid - RID_D_STEPPING_START) / 2; - attrs->stepping += STEP_D0; - } else if (attrs->revid >= RID_C_STEPPING_START) { - attrs->stepping = (attrs->revid - RID_C_STEPPING_START) / 2; - attrs->stepping += STEP_C0; - } else if (attrs->revid >= RID_B_STEPPING_START) { - attrs->stepping = (attrs->revid - RID_B_STEPPING_START) / 2; - attrs->stepping += STEP_B0; - } else { - attrs->stepping = (attrs->revid - RID_A_STEPPING_START) / 2; - attrs->stepping += STEP_A0; - } - - attrs->microcode_patch = intel_microcode_find(); - attrs->address_bits = cpuid_eax(0x80000008) & 0xff; - detect_num_cpus(attrs); - - if (SHOW_PATTRS) { - printk(BIOS_DEBUG, - "CPUID: %08x\nCores: %d\nRevision ID: %02x\nStepping: %s\n", - attrs->cpuid, attrs->num_cpus, attrs->revid, - (attrs->stepping >= ARRAY_SIZE(stepping_str)) ? "??" : - stepping_str[attrs->stepping]); - } - - fill_in_msr(&attrs->platform_id, IA32_PLATFORM_ID); - fill_in_msr(&attrs->platform_info, MSR_PLATFORM_INFO); - - /* Set IA core speed ratio and voltages */ - msr = rdmsr(MSR_IACORE_RATIOS); - attrs->iacore_ratios[IACORE_MIN] = msr.lo & 0x7f; - attrs->iacore_ratios[IACORE_LFM] = (msr.lo >> 8) & 0x7f; - attrs->iacore_ratios[IACORE_MAX] = (msr.lo >> 16) & 0x7f; - msr = rdmsr(MSR_IACORE_TURBO_RATIOS); - attrs->iacore_ratios[IACORE_TURBO] = (msr.lo & 0xff); /* 1 core max */ - - msr = rdmsr(MSR_IACORE_VIDS); - attrs->iacore_vids[IACORE_MIN] = msr.lo & 0x7f; - attrs->iacore_vids[IACORE_LFM] = (msr.lo >> 8) & 0x7f; - attrs->iacore_vids[IACORE_MAX] = (msr.lo >> 16) & 0x7f; - msr = rdmsr(MSR_IACORE_TURBO_VIDS); - attrs->iacore_vids[IACORE_TURBO] = (msr.lo & 0xff); /* 1 core max */ - - /* Set bus clock speed */ - attrs->bclk_khz = bus_freq_khz(); -} - -static void s3_resume_prepare(void) -{ - global_nvs_t *gnvs; - - gnvs = cbmem_add(CBMEM_ID_ACPI_GNVS, sizeof(global_nvs_t)); - if (gnvs == NULL) - return; - - if (!acpi_is_wakeup_s3()) - memset(gnvs, 0, sizeof(global_nvs_t)); -} - -void baytrail_init_pre_device(void) -{ - struct soc_gpio_config *config; - - fill_in_pattrs(); - - /* Allow for SSE instructions to be executed. */ - write_cr4(read_cr4() | CR4_OSFXSR | CR4_OSXMMEXCPT); - - /* Indicate S3 resume to rest of ramstage. */ - s3_resume_prepare(); - - /* Get GPIO initial states from mainboard */ - config = mainboard_get_gpios(); - setup_soc_gpios(config); -} diff --git a/src/soc/intel/fsp_baytrail/romstage/Makefile.inc b/src/soc/intel/fsp_baytrail/romstage/Makefile.inc deleted file mode 100644 index c47dfb5c16..0000000000 --- a/src/soc/intel/fsp_baytrail/romstage/Makefile.inc +++ /dev/null @@ -1,20 +0,0 @@ -# -# This file is part of the coreboot project. -# -# Copyright (C) 2013 Google Inc. -# Copyright (C) 2014 Sage Electronic Engineering, LLC. -# -# This program is free software; you can redistribute it and/or modify -# it under the terms of the GNU General Public License as published by -# the Free Software Foundation; version 2 of the License. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# - -romstage-y += romstage.c -romstage-y += pmc.c -romstage-y += report_platform.c -romstage-$(CONFIG_ENABLE_BUILTIN_COM1) += uart.c diff --git a/src/soc/intel/fsp_baytrail/romstage/pmc.c b/src/soc/intel/fsp_baytrail/romstage/pmc.c deleted file mode 100644 index dab31bf314..0000000000 --- a/src/soc/intel/fsp_baytrail/romstage/pmc.c +++ /dev/null @@ -1,35 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2013 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include "../chip.h" - -void tco_disable(void) -{ - uint32_t reg; - - reg = inl(ACPI_BASE_ADDRESS + TCO1_CNT); - reg |= TCO_TMR_HALT; - outl(reg, ACPI_BASE_ADDRESS + TCO1_CNT); -} diff --git a/src/soc/intel/fsp_baytrail/romstage/report_platform.c b/src/soc/intel/fsp_baytrail/romstage/report_platform.c deleted file mode 100644 index 2b5dad7ab7..0000000000 --- a/src/soc/intel/fsp_baytrail/romstage/report_platform.c +++ /dev/null @@ -1,84 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2012 Google Inc. - * Copyright (C) 2013 Sage Electronic Engineering, LLC. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include -#include -#include -#include -#include - -static void print_dram_info(void) -{ - const int mrc_ver_reg = 0xf0; - const uint32_t soc_dev = PCI_DEV(0, SOC_DEV, SOC_FUNC); - uint32_t reg; - int num_channels; - int speed; - uint32_t ch0; - uint32_t ch1; - - reg = pci_read_config32(soc_dev, mrc_ver_reg); - - printk(BIOS_INFO, "MRC v%d.%02d\n", (reg >> 8) & 0xff, reg & 0xff); - - /* Number of channels enabled and DDR3 type. Determine number of - * channels by the keying of the rank enable bits [3:0]. * */ - ch0 = iosf_dunit_ch0_read(DRP); - ch1 = iosf_dunit_ch1_read(DRP); - num_channels = 0; - if (ch0 & DRP_RANK_MASK) - num_channels++; - if (ch1 & DRP_RANK_MASK) - num_channels++; - - printk(BIOS_INFO, "%d channels of %sDDR3 @ ", num_channels, - (reg & (1 << 22)) ? "LP" : ""); - - /* DRAM frequency -- all channels run at same frequency. */ - reg = iosf_dunit_read(DTR0); - switch (reg & 0x3) { - case 0: - speed = 800; break; - case 1: - speed = 1066; break; - case 2: - speed = 1333; break; - case 3: - speed = 1600; break; - } - printk(BIOS_INFO, "%dMHz\n", speed); -} - -#define VARIANT_ID_BYTE 18 -#define VARIANT_ID_MASK 7 -void report_platform_info(void) -{ - const char *baytrail_variants[4] = { - "Bay Trail-I (ISG/embedded)", - "Bay Trail-T (Tablet)", - "Bay Trail-D (Desktop)", - "Bay Trail-M (Mobile)", - }; - msr_t platform_id = rdmsr(IA32_PLATFORM_ID); - uint8_t variant = (platform_id.hi >> VARIANT_ID_BYTE) & VARIANT_ID_MASK; - - printk(BIOS_INFO, "Baytrail Chip Variant: %s\n", variant < 4 ? - baytrail_variants[variant] : "Unknown"); - print_dram_info(); - -} diff --git a/src/soc/intel/fsp_baytrail/romstage/romstage.c b/src/soc/intel/fsp_baytrail/romstage/romstage.c deleted file mode 100644 index f347591599..0000000000 --- a/src/soc/intel/fsp_baytrail/romstage/romstage.c +++ /dev/null @@ -1,277 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2013 Google Inc. - * Copyright (C) 2013-2014 Sage Electronic Engineering, LLC. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -/* Return 0, 3, 4 or 5 to indicate the previous sleep state. */ -uint32_t chipset_prev_sleep_state(uint32_t clear) -{ - /* Default to S0. */ - uint32_t prev_sleep_state = ACPI_S0; - uint32_t pm1_sts; - uint32_t pm1_cnt; - uint32_t gen_pmcon1; - - /* Read Power State */ - pm1_sts = inw(ACPI_BASE_ADDRESS + PM1_STS); - pm1_cnt = inl(ACPI_BASE_ADDRESS + PM1_CNT); - gen_pmcon1 = read32((u32 *)(PMC_BASE_ADDRESS + GEN_PMCON1)); - - printk(BIOS_DEBUG, "PM1_STS = 0x%x PM1_CNT = 0x%x GEN_PMCON1 = 0x%x\n", - pm1_sts, pm1_cnt, gen_pmcon1); - - if (pm1_sts & WAK_STS) { - switch (acpi_sleep_from_pm1(pm1_cnt)) { - case ACPI_S3: - if (CONFIG(HAVE_ACPI_RESUME)) - prev_sleep_state = ACPI_S3; - break; - case ACPI_S4: - prev_sleep_state = ACPI_S4; - break; - - case ACPI_S5: - prev_sleep_state = ACPI_S5; - break; - } - /* If set Clear SLP_TYP. */ - if (clear == 1) { - outl(pm1_cnt & ~(SLP_TYP), ACPI_BASE_ADDRESS + PM1_CNT); - } - } - - if (gen_pmcon1 & (PWR_FLR | SUS_PWR_FLR)) { - prev_sleep_state = ACPI_S5; - } - - return prev_sleep_state; -} - -static void program_base_addresses(void) -{ - uint32_t reg; - - /* Memory Mapped IO registers. */ - reg = PMC_BASE_ADDRESS | SET_BAR_ENABLE; - pci_write_config32(LPC_BDF, PBASE, reg); - reg = IO_BASE_ADDRESS | SET_BAR_ENABLE; - pci_write_config32(LPC_BDF, IOBASE, reg); - reg = ILB_BASE_ADDRESS | SET_BAR_ENABLE; - pci_write_config32(LPC_BDF, IBASE, reg); - reg = SPI_BASE_ADDRESS | SET_BAR_ENABLE; - pci_write_config32(LPC_BDF, SBASE, reg); - reg = MPHY_BASE_ADDRESS | SET_BAR_ENABLE; - pci_write_config32(LPC_BDF, MPBASE, reg); - reg = PUNIT_BASE_ADDRESS | SET_BAR_ENABLE; - pci_write_config32(LPC_BDF, PUBASE, reg); - reg = RCBA_BASE_ADDRESS | RCBA_ENABLE; - pci_write_config32(LPC_BDF, RCBA, reg); - - /* IO Port Registers. */ - reg = ACPI_BASE_ADDRESS | SET_BAR_ENABLE; - pci_write_config32(LPC_BDF, ABASE, reg); - reg = GPIO_BASE_ADDRESS | SET_BAR_ENABLE; - pci_write_config32(LPC_BDF, GBASE, reg); -} - -static void spi_init(void) -{ - uint32_t *scs = (uint32_t *)(SPI_BASE_ADDRESS + SCS); - uint32_t *bcr = (uint32_t *)(SPI_BASE_ADDRESS + BCR); - uint32_t reg; - - /* Disable generating SMI when setting WPD bit. */ - write32(scs, read32(scs) & ~SMIWPEN); - /* - * Enable caching and prefetching in the SPI controller. Disable - * the SMM-only BIOS write and set WPD bit. - */ - reg = (read32(bcr) & ~SRC_MASK) | SRC_CACHE_PREFETCH | BCR_WPD; - reg &= ~EISS; - write32(bcr, reg); -} - -static void baytrail_rtc_init(void) -{ - uint32_t *pbase = (uint32_t *)(pci_read_config32(LPC_BDF, PBASE) & 0xfffffff0); - uint32_t gen_pmcon1 = read32(pbase + (GEN_PMCON1/sizeof(u32))); - int rtc_failed = !!(gen_pmcon1 & RPS); - - if (rtc_failed) { - printk(BIOS_DEBUG, - "RTC Failure detected. Resetting Date to %s\n", - coreboot_dmi_date); - - write32((uint32_t *)(DEFAULT_PBASE + GEN_PMCON1), gen_pmcon1 & ~RPS); - } - - cmos_init(rtc_failed); -} - -/* Entry from cache-as-ram.inc. */ -void main(FSP_INFO_HEADER *fsp_info_header) -{ - uint32_t *func_dis = (uint32_t *)(PMC_BASE_ADDRESS + FUNC_DIS); - uint32_t *func_dis2 = (uint32_t *)(PMC_BASE_ADDRESS + FUNC_DIS2); - uint32_t fd_mask = 0; - uint32_t fd2_mask = 0; - - post_code(0x40); - - timestamp_init(get_initial_timestamp()); - timestamp_add_now(TS_START_ROMSTAGE); - - program_base_addresses(); - - post_code(0x41); - tco_disable(); - - post_code(0x42); - if (CONFIG(ENABLE_BUILTIN_COM1)) - byt_config_com1_and_enable(); - - post_code(0x43); - console_init(); - - spi_init(); - baytrail_rtc_init(); - - /* Call into mainboard. */ - early_mainboard_romstage_entry(); - - set_max_freq(); - - post_code(0x44); - - /* Program any required function disables */ - get_func_disables(&fd_mask, &fd2_mask); - - if (fd_mask != 0) { - write32(func_dis, read32(func_dis) | fd_mask); - /* Ensure posted write hits. */ - read32(func_dis); - } - - if (fd2_mask != 0) { - write32(func_dis2, read32(func_dis2) | fd2_mask); - /* Ensure posted write hits. */ - read32(func_dis2); - } - - post_code(0x47); - - timestamp_add_now(TS_BEFORE_INITRAM); - - /* - * Call early init to initialize memory and chipset. This function returns - * to the romstage_main_continue function with a pointer to the HOB - * structure. - */ - post_code(0x48); - printk(BIOS_DEBUG, "Starting the Intel FSP (early_init)\n"); - fsp_early_init(fsp_info_header); - die_with_post_code(POST_INVALID_VENDOR_BINARY, - "Uh Oh! fsp_early_init should not return here.\n"); -} - -/******************************************************************************* - * The FSP early_init function returns to this function. - * Memory is setup and the stack is set by the FSP. - */ -void romstage_main_continue(EFI_STATUS status, void *hob_list_ptr) -{ - void *cbmem_hob_ptr; - uint32_t prev_sleep_state; - - timestamp_add_now(TS_AFTER_INITRAM); - - post_code(0x4a); - printk(BIOS_DEBUG, "%s status: %x hob_list_ptr: %x\n", - __func__, (u32) status, (u32) hob_list_ptr); - - /* FSP reconfigures USB, so reinit it to have debug */ - if (CONFIG(USBDEBUG_IN_PRE_RAM)) - usbdebug_hw_init(true); - - printk(BIOS_DEBUG, "FSP Status: 0x%0x\n", (u32)status); - - /* Get previous sleep state again and clear */ - prev_sleep_state = chipset_prev_sleep_state(1); - printk(BIOS_DEBUG, "%s: prev_sleep_state = S%d\n", __func__, prev_sleep_state); - - report_platform_info(); - - post_code(0x4b); - - late_mainboard_romstage_entry(); - post_code(0x4c); - - cbmem_recovery(prev_sleep_state == ACPI_S3); - - /* Save the HOB pointer in CBMEM to be used in ramstage*/ - cbmem_hob_ptr = cbmem_add(CBMEM_ID_HOB_POINTER, sizeof(*hob_list_ptr)); - if (cbmem_hob_ptr == NULL) - die("Could not allocate cbmem for HOB pointer"); - *(u32*)cbmem_hob_ptr = (u32)hob_list_ptr; - post_code(0x4e); - - romstage_handoff_init(prev_sleep_state == ACPI_S3); - - if (CONFIG(SMM_TSEG)) - smm_list_regions(); - - /* Load the ramstage. */ - post_code(0x4f); - run_ramstage(); - while (1); -} - -uint64_t get_initial_timestamp(void) -{ - return 0; -} - -int vboot_platform_is_resuming(void) -{ - return !!romstage_handoff_is_resume(); -} diff --git a/src/soc/intel/fsp_baytrail/romstage/uart.c b/src/soc/intel/fsp_baytrail/romstage/uart.c deleted file mode 100644 index dbd6e9df10..0000000000 --- a/src/soc/intel/fsp_baytrail/romstage/uart.c +++ /dev/null @@ -1,34 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2013 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include -#include -#include -#include - -void byt_config_com1_and_enable(void) -{ - uint32_t reg; - - /* Enable the legacy UART hardware. */ - reg = 1; - pci_write_config32(PCI_DEV(0, LPC_DEV, 0), UART_CONT, reg); - - /* Set up the pads to select the UART function */ - score_select_func(UART_RXD_PAD, 1); - score_select_func(UART_TXD_PAD, 1); -} diff --git a/src/soc/intel/fsp_baytrail/smihandler.c b/src/soc/intel/fsp_baytrail/smihandler.c deleted file mode 100644 index 1a8fb4b6e6..0000000000 --- a/src/soc/intel/fsp_baytrail/smihandler.c +++ /dev/null @@ -1,395 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2013 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include - -/* GNVS needs to be set by coreboot initiating a software SMI. */ -static global_nvs_t *gnvs; -static int smm_initialized; - -int southbridge_io_trap_handler(int smif) -{ - switch (smif) { - case 0x32: - printk(BIOS_DEBUG, "OS Init\n"); - /* gnvs->smif: - * On success, the IO Trap Handler returns 0 - * On failure, the IO Trap Handler returns a value != 0 - */ - gnvs->smif = 0; - return 1; /* IO trap handled */ - } - - /* Not handled */ - return 0; -} - -void southbridge_smi_set_eos(void) -{ - enable_smi(EOS); -} - -global_nvs_t *smm_get_gnvs(void) -{ - return gnvs; -} - -static void busmaster_disable_on_bus(int bus) -{ - int slot, func; - unsigned int val; - unsigned char hdr; - - for (slot = 0; slot < 0x20; slot++) { - for (func = 0; func < 8; func++) { - u32 reg32; - pci_devfn_t dev = PCI_DEV(bus, slot, func); - - val = pci_read_config32(dev, PCI_VENDOR_ID); - - if (val == 0xffffffff || val == 0x00000000 || - val == 0x0000ffff || val == 0xffff0000) - continue; - - /* Disable Bus Mastering for this one device */ - reg32 = pci_read_config32(dev, PCI_COMMAND); - reg32 &= ~PCI_COMMAND_MASTER; - pci_write_config32(dev, PCI_COMMAND, reg32); - - /* If this is a bridge, then follow it. */ - hdr = pci_read_config8(dev, PCI_HEADER_TYPE); - hdr &= 0x7f; - if (hdr == PCI_HEADER_TYPE_BRIDGE || - hdr == PCI_HEADER_TYPE_CARDBUS) { - unsigned int buses; - buses = pci_read_config32(dev, PCI_PRIMARY_BUS); - busmaster_disable_on_bus((buses >> 8) & 0xff); - } - } - } -} - -static void southbridge_smi_sleep(void) -{ - uint32_t reg32; - uint8_t slp_typ; - uint16_t pmbase = get_pmbase(); - - /* First, disable further SMIs */ - disable_smi(SLP_SMI_EN); - - /* Figure out SLP_TYP */ - reg32 = inl(pmbase + PM1_CNT); - printk(BIOS_SPEW, "SMI#: SLP = 0x%08x\n", reg32); - slp_typ = acpi_sleep_from_pm1(reg32); - - /* Do any mainboard sleep handling */ - mainboard_smi_sleep(slp_typ); - - /* Log S3, S4, and S5 entry */ - if (slp_typ >= ACPI_S3) - elog_gsmi_add_event_byte(ELOG_TYPE_ACPI_ENTER, slp_typ); - - /* Next, do the deed. - */ - - switch (slp_typ) { - case ACPI_S0: - printk(BIOS_DEBUG, "SMI#: Entering S0 (On)\n"); - break; - case ACPI_S1: - printk(BIOS_DEBUG, "SMI#: Entering S1 (Assert STPCLK#)\n"); - break; - case ACPI_S3: - printk(BIOS_DEBUG, "SMI#: Entering S3 (Suspend-To-RAM)\n"); - - /* Invalidate the cache before going to S3 */ - wbinvd(); - break; - case ACPI_S4: - printk(BIOS_DEBUG, "SMI#: Entering S4 (Suspend-To-Disk)\n"); - break; - case ACPI_S5: - printk(BIOS_DEBUG, "SMI#: Entering S5 (Soft Power off)\n"); - - /* Disable all GPE */ - disable_all_gpe(); - - /* also iterates over all bridges on bus 0 */ - busmaster_disable_on_bus(0); - break; - default: - printk(BIOS_DEBUG, "SMI#: ERROR: SLP_TYP reserved\n"); - break; - } - - /* Write back to the SLP register to cause the originally intended - * event again. We need to set BIT13 (SLP_EN) though to make the - * sleep happen. - */ - enable_pm1_control(SLP_EN); - - /* Make sure to stop executing code here for S3/S4/S5 */ - if (slp_typ >= ACPI_S3) - halt(); - - /* In most sleep states, the code flow of this function ends at - * the line above. However, if we entered sleep state S1 and wake - * up again, we will continue to execute code in this function. - */ - reg32 = inl(pmbase + PM1_CNT); - if (reg32 & SCI_EN) { - /* The OS is not an ACPI OS, so we set the state to S0 */ - disable_pm1_control(SLP_EN | SLP_TYP); - } -} - -/* - * Look for Synchronous IO SMI and use save state from that - * core in case we are not running on the same core that - * initiated the IO transaction. - */ -static em64t100_smm_state_save_area_t *smi_apmc_find_state_save(uint8_t cmd) -{ - em64t100_smm_state_save_area_t *state; - int node; - - /* Check all nodes looking for the one that issued the IO */ - for (node = 0; node < CONFIG_MAX_CPUS; node++) { - state = smm_get_save_state(node); - - /* Check for Synchronous IO (bit0==1) */ - if (!(state->io_misc_info & (1 << 0))) - continue; - - /* Make sure it was a write (bit4==0) */ - if (state->io_misc_info & (1 << 4)) - continue; - - /* Check for APMC IO port */ - if (((state->io_misc_info >> 16) & 0xff) != APM_CNT) - continue; - - /* Check AX against the requested command */ - if ((state->rax & 0xff) != cmd) - continue; - - return state; - } - - return NULL; -} - -static void southbridge_smi_gsmi(void) -{ - u32 *ret, *param; - uint8_t sub_command; - em64t100_smm_state_save_area_t *io_smi = - smi_apmc_find_state_save(APM_CNT_ELOG_GSMI); - - if (!io_smi) - return; - - /* Command and return value in EAX */ - ret = (u32*)&io_smi->rax; - sub_command = (uint8_t)(*ret >> 8); - - /* Parameter buffer in EBX */ - param = (u32*)&io_smi->rbx; - - /* drivers/elog/gsmi.c */ - *ret = gsmi_exec(sub_command, param); -} - -static void southbridge_smi_apmc(void) -{ - uint8_t reg8; - em64t100_smm_state_save_area_t *state; - - /* Emulate B2 register as the FADT / Linux expects it */ - - reg8 = inb(APM_CNT); - switch (reg8) { - case APM_CNT_CST_CONTROL: - /* Calling this function seems to cause - * some kind of race condition in Linux - * and causes a kernel oops - */ - printk(BIOS_DEBUG, "C-state control\n"); - break; - case APM_CNT_PST_CONTROL: - /* Calling this function seems to cause - * some kind of race condition in Linux - * and causes a kernel oops - */ - printk(BIOS_DEBUG, "P-state control\n"); - break; - case APM_CNT_ACPI_DISABLE: - disable_pm1_control(SCI_EN); - printk(BIOS_DEBUG, "SMI#: ACPI disabled.\n"); - break; - case APM_CNT_ACPI_ENABLE: - enable_pm1_control(SCI_EN); - printk(BIOS_DEBUG, "SMI#: ACPI enabled.\n"); - break; - case APM_CNT_GNVS_UPDATE: - if (smm_initialized) { - printk(BIOS_DEBUG, - "SMI#: SMM structures already initialized!\n"); - return; - } - state = smi_apmc_find_state_save(reg8); - if (state) { - /* EBX in the state save contains the GNVS pointer */ - gnvs = (global_nvs_t *)((uint32_t)state->rbx); - smm_initialized = 1; - printk(BIOS_DEBUG, "SMI#: Setting GNVS to %p\n", gnvs); - } - break; - case APM_CNT_ELOG_GSMI: - if (CONFIG(ELOG_GSMI)) - southbridge_smi_gsmi(); - break; - } - - mainboard_smi_apmc(reg8); -} - -static void southbridge_smi_pm1(void) -{ - uint16_t pm1_sts = clear_pm1_status(); - - /* While OSPM is not active, poweroff immediately - * on a power button event. - */ - if (pm1_sts & PWRBTN_STS) { - // power button pressed - elog_gsmi_add_event(ELOG_TYPE_POWER_BUTTON); - disable_pm1_control(-1UL); - enable_pm1_control(SLP_EN | (SLP_TYP_S5 << SLP_TYP_SHIFT)); - } -} - -static void southbridge_smi_gpe0(void) -{ - clear_gpe_status(); -} - -static void southbridge_smi_tco(void) -{ - uint32_t tco_sts = clear_tco_status(); - - /* Any TCO event? */ - if (!tco_sts) - return; - - if (tco_sts & TCO_TIMEOUT) { /* TIMEOUT */ - /* Handle TCO timeout */ - printk(BIOS_DEBUG, "TCO Timeout.\n"); - } -} - -static void southbridge_smi_periodic(void) -{ - uint32_t reg32; - - reg32 = inl(get_pmbase() + SMI_EN); - - /* Are periodic SMIs enabled? */ - if ((reg32 & PERIODIC_EN) == 0) - return; - - printk(BIOS_DEBUG, "Periodic SMI.\n"); -} - -typedef void (*smi_handler_t)(void); - -static const smi_handler_t southbridge_smi[32] = { - NULL, // [0] reserved - NULL, // [1] reserved - NULL, // [2] BIOS_STS - NULL, // [3] LEGACY_USB_STS - southbridge_smi_sleep, // [4] SLP_SMI_STS - southbridge_smi_apmc, // [5] APM_STS - NULL, // [6] SWSMI_TMR_STS - NULL, // [7] reserved - southbridge_smi_pm1, // [8] PM1_STS - southbridge_smi_gpe0, // [9] GPE0_STS - NULL, // [10] reserved - NULL, // [11] reserved - NULL, // [12] reserved - southbridge_smi_tco, // [13] TCO_STS - southbridge_smi_periodic, // [14] PERIODIC_STS - NULL, // [15] SERIRQ_SMI_STS - NULL, // [16] SMBUS_SMI_STS - NULL, // [17] LEGACY_USB2_STS - NULL, // [18] INTEL_USB2_STS - NULL, // [19] reserved - NULL, // [20] PCI_EXP_SMI_STS - NULL, // [21] reserved - NULL, // [22] reserved - NULL, // [23] reserved - NULL, // [24] reserved - NULL, // [25] reserved - NULL, // [26] SPI_STS - NULL, // [27] reserved - NULL, // [28] PUNIT - NULL, // [29] GUNIT - NULL, // [30] reserved - NULL // [31] reserved -}; - -void southbridge_smi_handler(void) -{ - int i; - uint32_t smi_sts; - - /* We need to clear the SMI status registers, or we won't see what's - * happening in the following calls. - */ - smi_sts = clear_smi_status(); - - /* Call SMI sub handler for each of the status bits */ - for (i = 0; i < ARRAY_SIZE(southbridge_smi); i++) { - if (!(smi_sts & (1 << i))) - continue; - - if (southbridge_smi[i] != NULL) { - southbridge_smi[i](); - } else { - printk(BIOS_DEBUG, - "SMI_STS[%d] occurred, but no " - "handler available.\n", i); - } - } - - /* The GPIO SMI events do not have a status bit in SMI_STS. Therefore, - * these events need to be cleared and checked unconditionally. */ - mainboard_smi_gpi(clear_alt_status()); -} diff --git a/src/soc/intel/fsp_baytrail/smm.c b/src/soc/intel/fsp_baytrail/smm.c deleted file mode 100644 index fbfd094c93..0000000000 --- a/src/soc/intel/fsp_baytrail/smm.c +++ /dev/null @@ -1,141 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2013 Google Inc. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -/* Save the gpio route register. The settings are committed from - * smm_southbridge_enable_smi(). */ -static uint32_t gpio_route; - -void smm_southcluster_save_gpio_route(uint32_t route) -{ - gpio_route = route; -} - -void smm_southbridge_clear_state(void) -{ - uint32_t smi_en; - - /* Log events from chipset before clearing */ - if (CONFIG(ELOG)) - southcluster_log_state(); - - printk(BIOS_DEBUG, "Initializing Southbridge SMI..."); - printk(BIOS_SPEW, " pmbase = 0x%04x\n", get_pmbase()); - - smi_en = inl(get_pmbase() + SMI_EN); - if (smi_en & APMC_EN) { - printk(BIOS_INFO, "SMI# handler already enabled?\n"); - return; - } - - /* Dump and clear status registers */ - clear_smi_status(); - clear_pm1_status(); - clear_tco_status(); - clear_gpe_status(); - clear_alt_status(); - clear_pmc_status(); -} - -static void smm_southcluster_route_gpios(void) -{ - u32 *gpio_rout = (u32 *)(PMC_BASE_ADDRESS + GPIO_ROUT); - const unsigned short alt_gpio_smi = ACPI_BASE_ADDRESS + ALT_GPIO_SMI; - uint32_t alt_gpio_reg = 0; - uint32_t route_reg = gpio_route; - int i; - - printk(BIOS_DEBUG, "GPIO_ROUT = %08x\n", route_reg); - - /* Start the routing for the specific gpios. */ - write32(gpio_rout, route_reg); - - /* Enable SMIs for the gpios that are set to trigger the SMI. */ - for (i = 0; i < 16; i++) { - if ((route_reg & ROUTE_MASK) == ROUTE_SMI) { - alt_gpio_reg |= (1 << i); - } - route_reg >>= 2; - } - printk(BIOS_DEBUG, "ALT_GPIO_SMI = %08x\n", alt_gpio_reg); - - outl(alt_gpio_reg, alt_gpio_smi); -} - -void smm_southbridge_enable_smi(void) -{ - - printk(BIOS_DEBUG, "Enabling SMIs.\n"); - /* Configure events Disable pcie wake. */ - enable_pm1(PWRBTN_EN | GBL_EN | PCIEXPWAK_DIS); - disable_gpe(PME_B0_EN); - - /* Set up the GPIO route. */ - smm_southcluster_route_gpios(); - - /* Enable SMI generation: - * - on APMC writes (io 0xb2) - * - on writes to SLP_EN (sleep states) - * - on writes to GBL_RLS (bios commands) - * No SMIs: - * - on TCO events - * - on microcontroller writes (io 0x62/0x66) - */ - enable_smi(APMC_EN | SLP_SMI_EN | GBL_SMI_EN | EOS); -} - -void smm_setup_structures(void *gnvs, void *tcg, void *smi1) -{ - /* - * Issue SMI to set the gnvs pointer in SMM. - * tcg and smi1 are unused. - * - * EAX = APM_CNT_GNVS_UPDATE - * EBX = gnvs pointer - * EDX = APM_CNT - */ - asm volatile ( - "outb %%al, %%dx\n\t" - : /* ignore result */ - : "a" (APM_CNT_GNVS_UPDATE), - "b" ((uint32_t)gnvs), - "d" (APM_CNT) - ); -} - -static void finalize_chipset(void *unused) -{ - printk(BIOS_DEBUG, "Finalizing SMM.\n"); - /* Lock sleep stretching policy and set SMI lock. */ - write32((void *)(PMC_BASE_ADDRESS + GEN_PMCON2), - read32((void *)(PMC_BASE_ADDRESS + GEN_PMCON2)) - | SLPSX_STR_POL_LOCK | SMI_LOCK); - outb(APM_CNT_FINALIZE, APM_CNT); -} - -BOOT_STATE_INIT_ENTRY(BS_OS_RESUME, BS_ON_ENTRY, finalize_chipset, NULL); -BOOT_STATE_INIT_ENTRY(BS_PAYLOAD_LOAD, BS_ON_EXIT, finalize_chipset, NULL); diff --git a/src/soc/intel/fsp_baytrail/southcluster.c b/src/soc/intel/fsp_baytrail/southcluster.c deleted file mode 100644 index 59411ec5f8..0000000000 --- a/src/soc/intel/fsp_baytrail/southcluster.c +++ /dev/null @@ -1,616 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2008-2009 coresystems GmbH - * Copyright (C) 2013 Google Inc. - * Copyright (C) 2013-2014 Sage Electronic Engineering, LLC. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include "chip.h" -#include - -typedef struct soc_intel_fsp_baytrail_config config_t; - -static inline void -add_mmio_resource(struct device *dev, int i, unsigned long addr, unsigned long size) -{ - mmio_resource(dev, i, addr >> 10, size >> 10); -} - -static void sc_add_mmio_resources(struct device *dev) -{ - add_mmio_resource(dev, 0xfeb, ABORT_BASE_ADDRESS, ABORT_BASE_SIZE); - add_mmio_resource(dev, PBASE, PMC_BASE_ADDRESS, PMC_BASE_SIZE); - add_mmio_resource(dev, IOBASE, IO_BASE_ADDRESS, IO_BASE_SIZE); - add_mmio_resource(dev, IBASE, ILB_BASE_ADDRESS, ILB_BASE_SIZE); - add_mmio_resource(dev, SBASE, SPI_BASE_ADDRESS, SPI_BASE_SIZE); - add_mmio_resource(dev, MPBASE, MPHY_BASE_ADDRESS, MPHY_BASE_SIZE); - add_mmio_resource(dev, PUBASE, PUNIT_BASE_ADDRESS, PUNIT_BASE_SIZE); - add_mmio_resource(dev, RCBA, RCBA_BASE_ADDRESS, RCBA_BASE_SIZE); - add_mmio_resource(dev, 0xfff, 0xffffffff - CONFIG_VIRTUAL_ROM_SIZE + 1, - CONFIG_VIRTUAL_ROM_SIZE); /* BIOS ROM */ - add_mmio_resource(dev, 0xfec, IO_APIC_ADDR, 0x00001000); /* IOAPIC */ -} - -/* Default IO range claimed by the LPC device. The upper bound is exclusive. */ -#define LPC_DEFAULT_IO_RANGE_LOWER 0 -#define LPC_DEFAULT_IO_RANGE_UPPER 0x1000 - -static void sc_enable_ioapic(struct device *dev) -{ - int i; - u32 reg32; - volatile u32 *ioapic_index = (u32 *)(IO_APIC_ADDR); - volatile u32 *ioapic_data = (u32 *)(IO_APIC_ADDR + 0x10); - u8 *ilb_base = (u8 *)(pci_read_config32(dev, IBASE) & ~0x0f); - - /* - * Enable ACPI I/O and power management. - * Set SCI IRQ to IRQ9 - */ - write32(ilb_base + ILB_OIC, 0x100); /* AEN */ - reg32 = read32(ilb_base + ILB_OIC); /* Read back per BWG */ - write32(ilb_base + ILB_ACTL, 0); /* ACTL bit 2:0 SCIS IRQ9 */ - - *ioapic_index = 0; - *ioapic_data = (1 << 25); - - /* affirm full set of redirection table entries ("write once") */ - *ioapic_index = 1; - reg32 = *ioapic_data; - *ioapic_index = 1; - *ioapic_data = reg32; - - *ioapic_index = 0; - reg32 = *ioapic_data; - printk(BIOS_DEBUG, "Southbridge APIC ID = %x\n", (reg32 >> 24) & 0x0f); - if (reg32 != (1 << 25)) - die_with_post_code(POST_HW_INIT_FAILURE, "APIC Error\n"); - - printk(BIOS_SPEW, "Dumping IOAPIC registers\n"); - for (i=0; i<3; i++) { - *ioapic_index = i; - printk(BIOS_SPEW, " reg 0x%04x:", i); - reg32 = *ioapic_data; - printk(BIOS_SPEW, " 0x%08x\n", reg32); - } - - *ioapic_index = 3; /* Select Boot Configuration register. */ - *ioapic_data = 1; /* Use Processor System Bus to deliver interrupts. */ -} - -static void sc_enable_serial_irqs(struct device *dev) -{ -#ifdef SETUPSERIQ /* NOT defined. Remove when the TODO is done. */ - /* - * TODO: SERIRQ seems to have a number of problems on baytrail. - * With it enabled, we get some spurious interrupts (ps2) - * in seabios. It also caused IOCHK# NMIs. Remove it - * until we understand how it needs to be configured. - */ - u8 reg8; - u8 *ibase = (u8 *)(pci_read_config32(dev, IBASE) & ~0xF); - - /* - * Disable the IOCHK# NMI. Let the NMI handler enable it if it needs. - */ - reg8 = inb(0x61); - reg8 &= 0x0f; /* Higher Nibble must be 0 */ - reg8 |= (1 << 3); /* IOCHK# NMI Disable for now */ - outb(reg8, 0x61); - - write32(ibase + ILB_OIC, read32(ibase + ILB_OIC) | SIRQEN); - write8(ibase + ILB_SERIRQ_CNTL, SCNT_CONTINUOUS_MODE); - -#if !CONFIG(SERIRQ_CONTINUOUS_MODE) - /* - * SoC requires that the System BIOS first set the SERIRQ logic to - * continuous mode operation for at least one frame before switching - * it into quiet mode operation. - */ - outb(0x00, 0xED); /* I/O Delay to get the 1 frame */ - write8(ibase + ILB_SERIRQ_CNTL, SCNT_QUIET_MODE); -#endif -#endif /* DON'T SET UP IRQS */ -} - -/* - * Write PCI config space IRQ assignments. PCI devices have the INT_LINE - * (0x3C) and INT_PIN (0x3D) registers which report interrupt routing - * information to operating systems and drivers. The INT_PIN register is - * generally read only and reports which interrupt pin A - D it uses. The - * INT_LINE register is configurable and reports which IRQ (generally the - * PIC IRQs 1 - 15) it will use. This needs to take interrupt pin swizzling - * on devices that are downstream on a PCI bridge into account. - * - * This function will loop through all enabled PCI devices and program the - * INT_LINE register with the correct PIC IRQ number for the INT_PIN that it - * uses. It then configures each interrupt in the pic to be level triggered. - */ -static void write_pci_config_irqs(void) -{ - struct device *irq_dev; - struct device *targ_dev; - uint8_t int_line = 0; - uint8_t original_int_pin = 0; - uint8_t new_int_pin = 0; - uint16_t current_bdf = 0; - uint16_t parent_bdf = 0; - uint8_t pirq = 0; - uint8_t device_num = 0; - const struct baytrail_irq_route *ir = &global_baytrail_irq_route; - - if (ir == NULL) { - printk(BIOS_WARNING, "Warning: Can't write PCI IRQ assignments because" - " 'global_baytrail_irq_route' structure does not exist\n"); - return; - } - - /* - * Loop through all enabled devices and program their - * INT_LINE, INT_PIN registers from values taken from - * the Interrupt Route registers in the ILB - */ - printk(BIOS_DEBUG, "PCI_CFG IRQ: Write PCI config space IRQ assignments\n"); - for (irq_dev = all_devices; irq_dev; irq_dev = irq_dev->next) { - - if ((irq_dev->path.type != DEVICE_PATH_PCI) || - (!irq_dev->enabled)) - continue; - - current_bdf = irq_dev->path.pci.devfn | - irq_dev->bus->secondary << 8; - - /* - * Step 1: Get the INT_PIN and device structure to look for - * in the pirq_data table defined in the mainboard directory. - */ - targ_dev = NULL; - new_int_pin = get_pci_irq_pins(irq_dev, &targ_dev); - if (targ_dev == NULL || new_int_pin < 1) - continue; - - /* - * Adjust the INT routing for the PCIe root ports - * See 'Interrupt Generated for INT[A-D] Interrupts' - * Table 241 in Document Number: 538136, Rev. 3.9 - */ - if (PCI_SLOT(targ_dev->path.pci.devfn) == PCIE_DEV && - targ_dev != irq_dev) - new_int_pin = ((new_int_pin - 1 + - PCI_FUNC(targ_dev->path.pci.devfn)) % 4) + 1; - - /* Get the original INT_PIN for record keeping */ - original_int_pin = pci_read_config8(irq_dev, PCI_INTERRUPT_PIN); - - parent_bdf = targ_dev->path.pci.devfn - | targ_dev->bus->secondary << 8; - device_num = PCI_SLOT(parent_bdf); - - if (ir->pcidev[device_num] == 0) { - printk(BIOS_WARNING, - "Warning: PCI Device %d does not have an IRQ entry, skipping it\n", - device_num); - continue; - } - - /* Find the PIRQ that is attached to the INT_PIN this device uses */ - pirq = (ir->pcidev[device_num] >> ((new_int_pin - 1) * 4)) & 0xF; - - /* Get the INT_LINE this device/function will use */ - int_line = ir->pic[pirq]; - - if (int_line != PIRQ_PIC_IRQDISABLE) { - /* Set this IRQ to level triggered since it is used by a PCI device */ - i8259_configure_irq_trigger(int_line, IRQ_LEVEL_TRIGGERED); - /* Set the Interrupt Line register in PCI config space */ - pci_write_config8(irq_dev, PCI_INTERRUPT_LINE, int_line); - } else { - /* Set the Interrupt line register as "unknown or unused" */ - pci_write_config8(irq_dev, PCI_INTERRUPT_LINE, - PIRQ_PIC_UNKNOWN_UNUSED); - } - - printk(BIOS_SPEW, "\tINT_PIN\t\t: %d (%s)\n", - original_int_pin, pin_to_str(original_int_pin)); - if (parent_bdf != current_bdf) - printk(BIOS_SPEW, "\tSwizzled to\t: %d (%s)\n", - new_int_pin, pin_to_str(new_int_pin)); - printk(BIOS_SPEW, "\tPIRQ\t\t: %c\n" - "\tINT_LINE\t: 0x%X (IRQ %d)\n", - 'A' + pirq, int_line, int_line); - } - printk(BIOS_DEBUG, "PCI_CFG IRQ: Finished writing PCI config space IRQ assignments\n"); -} - -static void sc_pirq_init(struct device *dev) -{ - int i, j; - int pirq; - u8 *pr_base = (u8 *)(ILB_BASE_ADDRESS + 0x08); - u16 *ir_base = (u16 *)(ILB_BASE_ADDRESS + 0x20); - u32 *actl = (u32 *)(ILB_BASE_ADDRESS + ACTL); - const struct baytrail_irq_route *ir = &global_baytrail_irq_route; - - /* Set up the PIRQ PIC routing based on static config. */ - printk(BIOS_SPEW, "Start writing IRQ assignments\n" - "PIRQ\tA\tB\tC\tD\tE\tF\tG\tH\n" - "IRQ "); - for (i = 0; i < NUM_PIRQS; i++) { - write8(pr_base + i, ir->pic[i]); - printk(BIOS_SPEW, "\t%d", ir->pic[i]); - } - printk(BIOS_SPEW, "\n\n"); - - /* Set up the per device PIRQ routing based on static config. */ - printk(BIOS_SPEW, "\t\t\tPIRQ[A-H] routed to each INT_PIN[A-D]\n" - "Dev\tINTA (IRQ)\tINTB (IRQ)\tINTC (IRQ)\tINTD (IRQ)\n"); - for (i = 0; i < NUM_OF_PCI_DEVS; i++) { - write16(ir_base + i, ir->pcidev[i]); - - /* If the entry is more than just 0, print it out */ - if (ir->pcidev[i]) { - printk(BIOS_SPEW, " %d: ", i); - for (j = 0; j < 4; j++) { - pirq = (ir->pcidev[i] >> (j * 4)) & 0xF; - printk(BIOS_SPEW, "\t%-4c (%d)", 'A' + pirq, ir->pic[pirq]); - } - printk(BIOS_SPEW, "\n"); - } - } - - /* Route SCI to IRQ9 */ - write32(actl, (read32(actl) & ~SCIS_MASK) | SCIS_IRQ9); - printk(BIOS_SPEW, "Finished writing IRQ assignments\n"); - - /* Write IRQ assignments to PCI config space */ - write_pci_config_irqs(); -} - -static inline int io_range_in_default(int base, int size) -{ - /* Does it start above the range? */ - if (base >= LPC_DEFAULT_IO_RANGE_UPPER) - return 0; - - /* Is it entirely contained? */ - if (base >= LPC_DEFAULT_IO_RANGE_LOWER && - (base + size) < LPC_DEFAULT_IO_RANGE_UPPER) - return 1; - - /* This will return not in range for partial overlaps. */ - return 0; -} - -/* - * Note: this function assumes there is no overlap with the default LPC device's - * claimed range: LPC_DEFAULT_IO_RANGE_LOWER -> LPC_DEFAULT_IO_RANGE_UPPER. - */ -static void sc_add_io_resource(struct device *dev, int base, int size, int index) -{ - struct resource *res; - - if (io_range_in_default(base, size)) - return; - - res = new_resource(dev, index); - res->base = base; - res->size = size; - res->flags = IORESOURCE_IO | IORESOURCE_ASSIGNED | - IORESOURCE_FIXED; -} - -static void sc_add_io_resources(struct device *dev) -{ - struct resource *res; - u8 io_index = 0; - - /* - * Add the default claimed IO range for the LPC device - * and mark it as subtractive decode. - */ - res = new_resource(dev, IOINDEX_SUBTRACTIVE(io_index++, 0)); - res->base = LPC_DEFAULT_IO_RANGE_LOWER; - res->size = LPC_DEFAULT_IO_RANGE_UPPER - LPC_DEFAULT_IO_RANGE_LOWER; - res->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE | - IORESOURCE_ASSIGNED | IORESOURCE_FIXED; - - /* GPIO */ - sc_add_io_resource(dev, GPIO_BASE_ADDRESS, GPIO_BASE_SIZE, GBASE); - - /* ACPI */ - sc_add_io_resource(dev, ACPI_BASE_ADDRESS, ACPI_BASE_SIZE, ABASE); -} - -static void sc_read_resources(struct device *dev) -{ - /* Get the normal PCI resources of this device. */ - pci_dev_read_resources(dev); - - /* Add non-standard MMIO resources. */ - sc_add_mmio_resources(dev); - - /* Add IO resources. */ - sc_add_io_resources(dev); -} - -static void enable_hpet(void) -{ -} - -static void sc_init(struct device *dev) -{ - u8 *ibase; - - printk(BIOS_DEBUG, "soc: southcluster_init\n"); - - ibase = (u8 *)(pci_read_config32(dev, IBASE) & ~0xF); - - write8(ibase + ILB_MC, 0); - - /* Set the value for PCI command register. */ - pci_write_config16(dev, PCI_COMMAND, - PCI_COMMAND_IO | PCI_COMMAND_MEMORY | - PCI_COMMAND_MASTER | PCI_COMMAND_SPECIAL); - - /* IO APIC initialization. */ - sc_enable_ioapic(dev); - - sc_enable_serial_irqs(dev); - - /* Setup the PIRQ. */ - sc_pirq_init(dev); - - /* Initialize the High Precision Event Timers, if present. */ - enable_hpet(); - - /* Initialize ISA DMA. */ - isa_dma_init(); - - setup_i8259(); - - setup_i8254(); -} - -/* - * Common code for the south cluster devices. - */ - -/* Set bit in function disable register to hide this device. */ -static void sc_disable_devfn(struct device *dev) -{ - u32 *func_dis = (u32 *)(PMC_BASE_ADDRESS + FUNC_DIS); - u32 *func_dis2 = (u32 *)(PMC_BASE_ADDRESS + FUNC_DIS2); - uint32_t fd_mask = 0; - uint32_t fd2_mask = 0; - -#define SET_DIS_MASK(name_) \ - case PCI_DEVFN(name_ ## _DEV, name_ ## _FUNC): \ - fd_mask |= name_ ## _DIS -#define SET_DIS_MASK2(name_) \ - case PCI_DEVFN(name_ ## _DEV, name_ ## _FUNC): \ - fd2_mask |= name_ ## _DIS - - switch (dev->path.pci.devfn) { - SET_DIS_MASK(LPE); - break; - SET_DIS_MASK(TXE); - break; - SET_DIS_MASK(PCIE_PORT1); - break; - SET_DIS_MASK(PCIE_PORT2); - break; - SET_DIS_MASK(PCIE_PORT3); - break; - SET_DIS_MASK(PCIE_PORT4); - break; - SET_DIS_MASK2(SMBUS); - break; - SET_DIS_MASK(OTG); - /* Disable OTG PHY when OTG is not available. */ - fd2_mask |= OTG_SS_PHY_DIS; - break; - } - - if (fd_mask != 0) { - write32(func_dis, read32(func_dis) | fd_mask); - /* Ensure posted write hits. */ - read32(func_dis); - } - - if (fd2_mask != 0) { - write32(func_dis2, read32(func_dis2) | fd2_mask); - /* Ensure posted write hits. */ - read32(func_dis2); - } -} - -static inline void set_d3hot_bits(struct device *dev, int offset) -{ - uint32_t reg8; - printk(BIOS_DEBUG, "Power management CAP offset 0x%x.\n", offset); - reg8 = pci_read_config8(dev, offset + 4); - reg8 |= 0x3; - pci_write_config8(dev, offset + 4, reg8); -} - -/* Parts of the audio subsystem are powered by the HDA device. Therefore, one - * cannot put HDA into D3Hot. Instead perform this workaround to make some of - * the audio paths work for LPE audio. */ -static void hda_work_around(struct device *dev) -{ - u32 *gctl = (u32 *)(TEMP_BASE_ADDRESS + 0x8); - - /* Need to set magic register 0x43 to 0xd7 in config space. */ - pci_write_config8(dev, 0x43, 0xd7); - - /* Need to set bit 0 of GCTL to take the device out of reset. However, - * that requires setting up the 64-bit BAR. */ - pci_write_config32(dev, PCI_BASE_ADDRESS_0, TEMP_BASE_ADDRESS); - pci_write_config32(dev, PCI_BASE_ADDRESS_1, 0); - pci_write_config8(dev, PCI_COMMAND, PCI_COMMAND_MEMORY); - write32(gctl, read32(gctl) | 0x1); - pci_write_config8(dev, PCI_COMMAND, 0); - pci_write_config32(dev, PCI_BASE_ADDRESS_0, 0); -} - -static int place_device_in_d3hot(struct device *dev) -{ - unsigned int offset; - - /* Parts of the HDA block are used for LPE audio as well. - * Therefore assume the HDA will never be put into D3Hot. */ - if (dev->path.pci.devfn == PCI_DEVFN(HDA_DEV, HDA_FUNC)) { - hda_work_around(dev); - return 0; - } - - offset = pci_find_capability(dev, PCI_CAP_ID_PM); - - if (offset != 0) { - set_d3hot_bits(dev, offset); - return 0; - } - - /* For some reason some of the devices don't have the capability - * pointer set correctly. Work around this by hard coding the offset. */ -#define DEV_CASE(name_) \ - case PCI_DEVFN(name_ ## _DEV, name_ ## _FUNC) - - switch (dev->path.pci.devfn) { - DEV_CASE(MIPI): - DEV_CASE(SDIO): - DEV_CASE(EMMC): - DEV_CASE(SD): - DEV_CASE(MMC45): - DEV_CASE(LPE): - DEV_CASE(SIO_DMA1): - DEV_CASE(I2C1): - DEV_CASE(I2C2): - DEV_CASE(I2C3): - DEV_CASE(I2C4): - DEV_CASE(I2C5): - DEV_CASE(I2C6): - DEV_CASE(I2C7): - DEV_CASE(SIO_DMA2): - DEV_CASE(PWM1): - DEV_CASE(PWM2): - DEV_CASE(HSUART1): - DEV_CASE(HSUART2): - DEV_CASE(SPI): - DEV_CASE(OTG): - offset = 0x80; - break; - DEV_CASE(SATA): - DEV_CASE(XHCI): - DEV_CASE(EHCI): - offset = 0x70; - break; - DEV_CASE(HDA): - DEV_CASE(SMBUS): - offset = 0x50; - break; - DEV_CASE(TXE): - /* TXE cannot be placed in D3Hot. */ - return 0; - break; - DEV_CASE(PCIE_PORT1): - DEV_CASE(PCIE_PORT2): - DEV_CASE(PCIE_PORT3): - DEV_CASE(PCIE_PORT4): - offset = 0xa0; - break; - } - - if (offset != 0) { - set_d3hot_bits(dev, offset); - return 0; - } - - return -1; -} - -/* Common PCI device function disable. */ -void southcluster_enable_dev(struct device *dev) -{ - uint32_t reg32; - - if (!dev->enabled) { - int slot = PCI_SLOT(dev->path.pci.devfn); - int func = PCI_FUNC(dev->path.pci.devfn); - printk(BIOS_DEBUG, "%s: Disabling device: %02x.%01x\n", - dev_path(dev), slot, func); - - /* Ensure memory, io, and bus master are all disabled */ - reg32 = pci_read_config32(dev, PCI_COMMAND); - reg32 &= ~(PCI_COMMAND_MASTER | - PCI_COMMAND_MEMORY | PCI_COMMAND_IO); - pci_write_config32(dev, PCI_COMMAND, reg32); - - /* Place device in D3Hot */ - if (place_device_in_d3hot(dev) < 0) { - printk(BIOS_WARNING, - "Could not place %02x.%01x into D3Hot. " - "Keeping device visible.\n", slot, func); - return; - } - /* Disable this device if possible */ - sc_disable_devfn(dev); - } else { - /* Enable SERR */ - reg32 = pci_read_config32(dev, PCI_COMMAND); - reg32 |= PCI_COMMAND_SERR; - pci_write_config32(dev, PCI_COMMAND, reg32); - } -} - -static struct device_operations device_ops = { - .read_resources = sc_read_resources, - .set_resources = pci_dev_set_resources, - .acpi_inject_dsdt_generator = southcluster_inject_dsdt, - .write_acpi_tables = southcluster_write_acpi_tables, - .enable_resources = NULL, - .init = sc_init, - .enable = southcluster_enable_dev, - .scan_bus = scan_static_bus, - .ops_pci = &soc_pci_ops, -}; - -static const struct pci_driver southcluster __pci_driver = { - .ops = &device_ops, - .vendor = PCI_VENDOR_ID_INTEL, - .device = LPC_DEVID, -}; diff --git a/src/soc/intel/fsp_baytrail/spi.c b/src/soc/intel/fsp_baytrail/spi.c deleted file mode 100644 index 8aa6290386..0000000000 --- a/src/soc/intel/fsp_baytrail/spi.c +++ /dev/null @@ -1,584 +0,0 @@ -/* - * Copyright (c) 2011 The Chromium OS Authors. - * Copyright (C) 2013-2014 Sage Electronic Engineering, LLC. - * Copyright (C) 2016 Siemens AG - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but without any warranty; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -/* This file is derived from the flashrom project. */ -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include - -typedef struct spi_slave ich_spi_slave; - -static int g_ichspi_lock CAR_GLOBAL = 0; - -typedef struct ich9_spi_regs { - uint32_t bfpr; - uint16_t hsfs; - uint16_t hsfc; - uint32_t faddr; - uint32_t _reserved0; - uint32_t fdata[16]; - uint32_t frap; - uint32_t freg[5]; - uint32_t _reserved1[3]; - uint32_t pr[5]; - uint32_t _reserved2[2]; - uint8_t ssfs; - uint8_t ssfc[3]; - uint16_t preop; - uint16_t optype; - uint8_t opmenu[8]; - uint8_t _reserved3[16]; - uint32_t fdoc; - uint32_t fdod; - uint8_t _reserved4[8]; - uint32_t afc; - uint32_t lvscc; - uint32_t uvscc; - uint8_t _reserved5[4]; - uint32_t fpb; - uint8_t _reserved6[28]; - uint32_t srdl; - uint32_t srdc; - uint32_t srd; -} __packed ich9_spi_regs; - -typedef struct ich_spi_controller { - int locked; - - uint8_t *opmenu; - int menubytes; - uint16_t *preop; - uint16_t *optype; - uint32_t *addr; - uint8_t *data; - unsigned int databytes; - uint8_t *status; - uint16_t *control; -} ich_spi_controller; - -static ich_spi_controller g_cntlr CAR_GLOBAL; - -enum { - SPIS_SCIP = 0x0001, - SPIS_GRANT = 0x0002, - SPIS_CDS = 0x0004, - SPIS_FCERR = 0x0008, - SSFS_AEL = 0x0010, - SPIS_LOCK = 0x8000, - SPIS_RESERVED_MASK = 0x7ff0, - SSFS_RESERVED_MASK = 0x7fe2 -}; - -enum { - SPIC_SCGO = 0x000002, - SPIC_ACS = 0x000004, - SPIC_SPOP = 0x000008, - SPIC_DBC = 0x003f00, - SPIC_DS = 0x004000, - SPIC_SME = 0x008000, - SSFC_SCF_MASK = 0x070000, - SSFC_RESERVED = 0xf80000 -}; - -enum { - HSFS_FDONE = 0x0001, - HSFS_FCERR = 0x0002, - HSFS_AEL = 0x0004, - HSFS_BERASE_MASK = 0x0018, - HSFS_BERASE_SHIFT = 3, - HSFS_SCIP = 0x0020, - HSFS_FDOPSS = 0x2000, - HSFS_FDV = 0x4000, - HSFS_FLOCKDN = 0x8000 -}; - -enum { - HSFC_FGO = 0x0001, - HSFC_FCYCLE_MASK = 0x0006, - HSFC_FCYCLE_SHIFT = 1, - HSFC_FDBC_MASK = 0x3f00, - HSFC_FDBC_SHIFT = 8, - HSFC_FSMIE = 0x8000 -}; - -enum { - SPI_OPCODE_TYPE_READ_NO_ADDRESS = 0, - SPI_OPCODE_TYPE_WRITE_NO_ADDRESS = 1, - SPI_OPCODE_TYPE_READ_WITH_ADDRESS = 2, - SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS = 3 -}; - -#define SPI_OFFSET_MASK 0x3ff - -static uint8_t readb_(const void *addr) -{ - uint8_t v = read8(addr); - if (CONFIG(DEBUG_SPI_FLASH)) { - printk(BIOS_DEBUG, "SPI: read %2.2x from %4.4x\n", - v, (((uint32_t) addr) & SPI_OFFSET_MASK)); - } - return v; -} - -static uint16_t readw_(const void *addr) -{ - uint16_t v = read16(addr); - if (CONFIG(DEBUG_SPI_FLASH)) { - printk(BIOS_DEBUG, "SPI: read %4.4x from %4.4x\n", - v, (((uint32_t) addr) & SPI_OFFSET_MASK)); - } - return v; -} - -static uint32_t readl_(const void *addr) -{ - uint32_t v = read32(addr); - if (CONFIG(DEBUG_SPI_FLASH)) { - printk(BIOS_DEBUG, "SPI: read %8.8x from %4.4x\n", - v, (((uint32_t) addr) & SPI_OFFSET_MASK)); - } - return v; -} - -static void writeb_(uint8_t b, void *addr) -{ - write8(addr, b); - if (CONFIG(DEBUG_SPI_FLASH)) { - printk(BIOS_DEBUG, "SPI: wrote %2.2x to %4.4x\n", - b, (((uint32_t) addr) & SPI_OFFSET_MASK)); - } -} - -static void writew_(uint16_t b, void *addr) -{ - write16(addr, b); - if (CONFIG(DEBUG_SPI_FLASH)) { - printk(BIOS_DEBUG, "SPI: wrote %4.4x to %4.4x\n", - b, (((uint32_t) addr) & SPI_OFFSET_MASK)); - } -} - -static void writel_(uint32_t b, void *addr) -{ - write32(addr, b); - if (CONFIG(DEBUG_SPI_FLASH)) { - printk(BIOS_DEBUG, "SPI: wrote %8.8x to %4.4x\n", - b, (((uint32_t) addr) & SPI_OFFSET_MASK)); - } -} - -static void write_reg(const void *value, void *dest, uint32_t size) -{ - const uint8_t *bvalue = value; - uint8_t *bdest = dest; - - while (size >= 4) { - writel_(*(const uint32_t *)bvalue, bdest); - bdest += 4; bvalue += 4; size -= 4; - } - while (size) { - writeb_(*bvalue, bdest); - bdest++; bvalue++; size--; - } -} - -static void read_reg(const void *src, void *value, uint32_t size) -{ - const uint8_t *bsrc = src; - uint8_t *bvalue = value; - - while (size >= 4) { - *(uint32_t *)bvalue = readl_(bsrc); - bsrc += 4; bvalue += 4; size -= 4; - } - while (size) { - *bvalue = readb_(bsrc); - bsrc++; bvalue++; size--; - } -} - -static ich9_spi_regs *spi_regs(void) -{ - uint32_t sbase; - -#ifdef __SIMPLE_DEVICE__ - pci_devfn_t dev = PCI_DEV(0, LPC_DEV, LPC_FUNC); -#else - struct device *dev = pcidev_on_root(LPC_DEV, LPC_FUNC); -#endif - sbase = pci_read_config32(dev, SBASE); - sbase &= ~0x1ff; - - return (void *)sbase; -} - -#define MENU_BYTES member_size(struct ich9_spi_regs, opmenu) - -void spi_init(void) -{ - ich_spi_controller *cntlr = car_get_var_ptr(&g_cntlr); - ich9_spi_regs *ich9_spi = spi_regs(); - - car_set_var(g_ichspi_lock, readw_(&ich9_spi->hsfs) & HSFS_FLOCKDN); - cntlr->opmenu = ich9_spi->opmenu; - cntlr->menubytes = sizeof(ich9_spi->opmenu); - cntlr->optype = &ich9_spi->optype; - cntlr->addr = &ich9_spi->faddr; - cntlr->data = (uint8_t *)ich9_spi->fdata; - cntlr->databytes = sizeof(ich9_spi->fdata); - cntlr->status = &ich9_spi->ssfs; - cntlr->control = (uint16_t *)ich9_spi->ssfc; - cntlr->preop = &ich9_spi->preop; -} - -typedef struct spi_transaction { - const uint8_t *out; - uint32_t bytesout; - uint8_t *in; - uint32_t bytesin; - uint8_t type; - uint8_t opcode; - uint32_t offset; -} spi_transaction; - -static inline void spi_use_out(spi_transaction *trans, unsigned int bytes) -{ - trans->out += bytes; - trans->bytesout -= bytes; -} - -static inline void spi_use_in(spi_transaction *trans, unsigned int bytes) -{ - trans->in += bytes; - trans->bytesin -= bytes; -} - -static void spi_setup_type(spi_transaction *trans) -{ - trans->type = 0xFF; - - /* Try to guess spi type from read/write sizes. */ - if (trans->bytesin == 0) { - if (trans->bytesout > 4) - /* - * If bytesin = 0 and bytesout > 4, we presume this is - * a write data operation, which is accompanied by an - * address. - */ - trans->type = SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS; - else - trans->type = SPI_OPCODE_TYPE_WRITE_NO_ADDRESS; - return; - } - - if (trans->bytesout == 1) { /* and bytesin is > 0 */ - trans->type = SPI_OPCODE_TYPE_READ_NO_ADDRESS; - return; - } - - if (trans->bytesout == 4) { /* and bytesin is > 0 */ - trans->type = SPI_OPCODE_TYPE_READ_WITH_ADDRESS; - } - - /* Fast read command is called with 5 bytes instead of 4 */ - if (trans->out[0] == SPI_OPCODE_FAST_READ && trans->bytesout == 5) { - trans->type = SPI_OPCODE_TYPE_READ_WITH_ADDRESS; - --trans->bytesout; - } -} - -static int spi_setup_opcode(spi_transaction *trans) -{ - ich_spi_controller *cntlr = car_get_var_ptr(&g_cntlr); - uint16_t optypes; - uint8_t opmenu[MENU_BYTES]; - - trans->opcode = trans->out[0]; - spi_use_out(trans, 1); - if (!car_get_var(g_ichspi_lock)) { - /* The lock is off, so just use index 0. */ - writeb_(trans->opcode, cntlr->opmenu); - optypes = readw_(cntlr->optype); - optypes = (optypes & 0xfffc) | (trans->type & 0x3); - writew_(optypes, cntlr->optype); - return 0; - } else { - /* The lock is on. See if what we need is on the menu. */ - uint8_t optype; - uint16_t opcode_index; - - /* Write Enable is handled as atomic prefix */ - if (trans->opcode == SPI_OPCODE_WREN) - return 0; - - read_reg(cntlr->opmenu, opmenu, sizeof(opmenu)); - for (opcode_index = 0; opcode_index < ARRAY_SIZE(opmenu); opcode_index++) { - if (opmenu[opcode_index] == trans->opcode) - break; - } - - if (opcode_index == ARRAY_SIZE(opmenu)) { - printk(BIOS_DEBUG, "ICH SPI: Opcode %x not found\n", - trans->opcode); - return -1; - } - - optypes = readw_(cntlr->optype); - optype = (optypes >> (opcode_index * 2)) & 0x3; - if (trans->type == SPI_OPCODE_TYPE_WRITE_NO_ADDRESS && - optype == SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS && - trans->bytesout >= 3) { - /* We guessed wrong earlier. Fix it up. */ - trans->type = optype; - } - if (optype != trans->type) { - printk(BIOS_DEBUG, "ICH SPI: Transaction doesn't fit type %d\n", - optype); - return -1; - } - return opcode_index; - } -} - -static int spi_setup_offset(spi_transaction *trans) -{ - /* Separate the SPI address and data. */ - switch (trans->type) { - case SPI_OPCODE_TYPE_READ_NO_ADDRESS: - case SPI_OPCODE_TYPE_WRITE_NO_ADDRESS: - return 0; - case SPI_OPCODE_TYPE_READ_WITH_ADDRESS: - case SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS: - trans->offset = ((uint32_t)trans->out[0] << 16) | - ((uint32_t)trans->out[1] << 8) | - ((uint32_t)trans->out[2] << 0); - spi_use_out(trans, 3); - return 1; - default: - printk(BIOS_DEBUG, "Unrecognized SPI transaction type %#x\n", trans->type); - return -1; - } -} - -/* - * Wait for up to 60ms til status register bit(s) turn 1 (in case wait_til_set - * below is True) or 0. In case the wait was for the bit(s) to set - write - * those bits back, which would cause resetting them. - * - * Return the last read status value on success or -1 on failure. - */ -static int ich_status_poll(uint16_t bitmask, int wait_til_set) -{ - ich_spi_controller *cntlr = car_get_var_ptr(&g_cntlr); - int timeout = 40000; /* This will result in 400 ms */ - uint16_t status = 0; - - while (timeout--) { - status = readw_(cntlr->status); - if (wait_til_set ^ ((status & bitmask) == 0)) { - if (wait_til_set) - writew_((status & bitmask), cntlr->status); - return status; - } - udelay(10); - } - - printk(BIOS_DEBUG, "ICH SPI: SCIP timeout, read %x, expected %x\n", - status, bitmask); - return -1; -} - -static int spi_ctrlr_xfer(const struct spi_slave *slave, const void *dout, - size_t bytesout, void *din, size_t bytesin) -{ - ich_spi_controller *cntlr = car_get_var_ptr(&g_cntlr); - uint16_t control; - int16_t opcode_index; - int with_address; - int status; - - spi_transaction trans = { - dout, bytesout, - din, bytesin, - 0xff, 0xff, 0 - }; - - /* There has to always at least be an opcode. */ - if (!bytesout || !dout) { - printk(BIOS_DEBUG, "ICH SPI: No opcode for transfer\n"); - return -1; - } - /* Make sure if we read something we have a place to put it. */ - if (bytesin != 0 && !din) { - printk(BIOS_DEBUG, "ICH SPI: Read but no target buffer\n"); - return -1; - } - - if (ich_status_poll(SPIS_SCIP, 0) == -1) - return -1; - - writew_(SPIS_CDS | SPIS_FCERR, cntlr->status); - - spi_setup_type(&trans); - if ((opcode_index = spi_setup_opcode(&trans)) < 0) - return -1; - if ((with_address = spi_setup_offset(&trans)) < 0) - return -1; - - if (!car_get_var(g_ichspi_lock) && trans.opcode == SPI_OPCODE_WREN) { - /* - * Treat Write Enable as Atomic Pre-Op if possible - * in order to prevent the Management Engine from - * issuing a transaction between WREN and DATA. - */ - writew_(trans.opcode, cntlr->preop); - return 0; - } - - /* Preset control fields */ - control = SPIC_SCGO | ((opcode_index & 0x07) << 4); - - /* Issue atomic preop cycle if needed */ - if (readw_(cntlr->preop)) - control |= SPIC_ACS; - - if (!trans.bytesout && !trans.bytesin) { - /* SPI addresses are 24 bit only */ - if (with_address) - writel_(trans.offset & 0x00FFFFFF, cntlr->addr); - - /* - * This is a 'no data' command (like Write Enable), its - * bytesout size was 1, decremented to zero while executing - * spi_setup_opcode() above. Tell the chip to send the - * command. - */ - writew_(control, cntlr->control); - - /* wait for the result */ - status = ich_status_poll(SPIS_CDS | SPIS_FCERR, 1); - if (status == -1) - return -1; - - if (status & SPIS_FCERR) { - printk(BIOS_DEBUG, "ICH SPI: Command transaction error\n"); - return -1; - } - - goto spi_xfer_exit; - } - - /* - * Check if this is a write command attempting to transfer more bytes - * than the controller can handle. Iterations for writes are not - * supported here because each SPI write command needs to be preceded - * and followed by other SPI commands, and this sequence is controlled - * by the SPI chip driver. - */ - if (trans.bytesout > cntlr->databytes) { - printk(BIOS_DEBUG, "ICH SPI: Too much to write. Does your SPI chip driver use" - " spi_crop_chunk()?\n"); - return -1; - } - - /* - * Read or write up to databytes bytes at a time until everything has - * been sent. - */ - while (trans.bytesout || trans.bytesin) { - uint32_t data_length; - - /* SPI addresses are 24 bit only */ - writel_(trans.offset & 0x00FFFFFF, cntlr->addr); - - if (trans.bytesout) - data_length = min(trans.bytesout, cntlr->databytes); - else - data_length = min(trans.bytesin, cntlr->databytes); - - /* Program data into FDATA0 to N */ - if (trans.bytesout) { - write_reg(trans.out, cntlr->data, data_length); - spi_use_out(&trans, data_length); - if (with_address) - trans.offset += data_length; - } - - /* Add proper control fields' values */ - control &= ~((cntlr->databytes - 1) << 8); - control |= SPIC_DS; - control |= (data_length - 1) << 8; - - /* write it */ - writew_(control, cntlr->control); - - /* Wait for Cycle Done Status or Flash Cycle Error. */ - status = ich_status_poll(SPIS_CDS | SPIS_FCERR, 1); - if (status == -1) - return -1; - - if (status & SPIS_FCERR) { - printk(BIOS_DEBUG, "ICH SPI: Data transaction error\n"); - return -1; - } - - if (trans.bytesin) { - read_reg(cntlr->data, trans.in, data_length); - spi_use_in(&trans, data_length); - if (with_address) - trans.offset += data_length; - } - } - -spi_xfer_exit: - /* Clear atomic preop now that xfer is done */ - writew_(0, cntlr->preop); - - return 0; -} - -static int xfer_vectors(const struct spi_slave *slave, - struct spi_op vectors[], size_t count) -{ - return spi_flash_vector_helper(slave, vectors, count, spi_ctrlr_xfer); -} - -static const struct spi_ctrlr spi_ctrlr = { - .xfer_vector = xfer_vectors, - .max_xfer_size = member_size(ich9_spi_regs, fdata), -}; - -const struct spi_ctrlr_buses spi_ctrlr_bus_map[] = { - { - .ctrlr = &spi_ctrlr, - .bus_start = 0, - .bus_end = 0, - }, -}; - -const size_t spi_ctrlr_bus_map_count = ARRAY_SIZE(spi_ctrlr_bus_map); diff --git a/src/soc/intel/fsp_baytrail/tsc_freq.c b/src/soc/intel/fsp_baytrail/tsc_freq.c deleted file mode 100644 index d31ddd9be3..0000000000 --- a/src/soc/intel/fsp_baytrail/tsc_freq.c +++ /dev/null @@ -1,72 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2013 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include -#include -#include - -unsigned int bus_freq_khz(void) -{ - msr_t clk_info = rdmsr(MSR_BSEL_CR_OVERCLOCK_CONTROL); - switch (clk_info.lo & 0x3) { - case 0: - return 83333; - case 1: - return 100000; - case 2: - return 133333; - case 3: - return 116666; - default: - return 0; - } -} - -unsigned long tsc_freq_mhz(void) -{ - msr_t platform_info; - unsigned int bclk_khz = bus_freq_khz(); - - if (!bclk_khz) - return 0; - - platform_info = rdmsr(MSR_PLATFORM_INFO); - return (bclk_khz * ((platform_info.lo >> 8) & 0xff)) / 1000; -} - -void set_max_freq(void) -{ - msr_t perf_ctl; - msr_t msr; - - /* Enable speed step. */ - msr = rdmsr(IA32_MISC_ENABLE); - msr.lo |= (1 << 16); - wrmsr(IA32_MISC_ENABLE, msr); - - /* Set guaranteed ratio [21:16] from IACORE_RATIOS to bits [15:8] of - * the PERF_CTL. */ - msr = rdmsr(MSR_IACORE_RATIOS); - perf_ctl.lo = (msr.lo & 0x3f0000) >> 8; - /* Set guaranteed vid [21:16] from IACORE_VIDS to bits [7:0] of - * the PERF_CTL. */ - msr = rdmsr(MSR_IACORE_VIDS); - perf_ctl.lo |= (msr.lo & 0x7f0000) >> 16; - perf_ctl.hi = 0; - - wrmsr(IA32_PERF_CTL, perf_ctl); -} diff --git a/src/vendorcode/intel/Kconfig b/src/vendorcode/intel/Kconfig index 027f12b66e..e1458db829 100644 --- a/src/vendorcode/intel/Kconfig +++ b/src/vendorcode/intel/Kconfig @@ -14,10 +14,6 @@ ## GNU General Public License for more details. ## -config FSP_VENDORCODE_HEADER_PATH - string - default "fsp1_0/baytrail" if SOC_INTEL_FSP_BAYTRAIL - config UEFI_2_4_BINDING def_bool n diff --git a/src/vendorcode/intel/Makefile.inc b/src/vendorcode/intel/Makefile.inc index 33b2f81720..7b9ca5167e 100644 --- a/src/vendorcode/intel/Makefile.inc +++ b/src/vendorcode/intel/Makefile.inc @@ -14,15 +14,6 @@ ## GNU General Public License for more details. ## -ifneq ($(CONFIG_FSP_VENDORCODE_HEADER_PATH),) -FSP_PATH := $(call strip_quotes,$(CONFIG_FSP_VENDORCODE_HEADER_PATH)) -FSP_SRC_FILES := $(wildcard src/vendorcode/intel/$(FSP_PATH)/srx/*.c) -FSP_C_INPUTS := $(foreach file, $(FSP_SRC_FILES), $(FSP_PATH)/srx/$(notdir $(file))) -ramstage-y += $(FSP_C_INPUTS) - -CFLAGS_x86_32 += -Isrc/vendorcode/intel/$(FSP_PATH)/include -endif - ifeq ($(CONFIG_UEFI_2_4_BINDING),y) # ProccessorBind.h provided in Ia32 directory. Types are derived from ia32. # It's possible to provide our own ProcessorBind.h using posix types. However, diff --git a/src/vendorcode/intel/fsp1_0/baytrail/absf/minnowmax_1gb.absf b/src/vendorcode/intel/fsp1_0/baytrail/absf/minnowmax_1gb.absf deleted file mode 100644 index 66ab0d774c..0000000000 --- a/src/vendorcode/intel/fsp1_0/baytrail/absf/minnowmax_1gb.absf +++ /dev/null @@ -1,328 +0,0 @@ -// -// This file contains an 'Intel Peripheral Driver' and is -// licensed for Intel CPUs and chipsets under the terms of your -// license agreement with Intel or your vendor. This file must not -// be modified by end users or could render the generated boot loader -// inoperable. -// -// @file -// Boot Setting File for Platform: Bayley Bay Platform -// -// Copyright (c) 2010-2013 Intel Corporation. All rights reserved -// This software and associated documentation (if any) is furnished -// under a license and may only be used or copied in accordance -// with the terms of the license. Except as permitted by such -// license, no part of this software or documentation may be -// reproduced, stored in a retrieval system, or transmitted in any -// form or by any means without the express written consent of -// Intel Corporation. -// -// - - -GlobalDataDef - SKUID = 0 $_AS_BUILT_ = 0x01 , "DEFAULT" -EndGlobalData - -StructDef - - Find "VLV2UPDR" - Skip 24 bytes - $gPlatformFspPkgTokenSpaceGuid_PcdMrcInitTsegSize 2 bytes $_AS_BUILT_ = 0x1, 0x0 $_DEFAULT_ = 0x0001 - $gPlatformFspPkgTokenSpaceGuid_PcdMrcInitMmioSize 2 bytes $_AS_BUILT_ = 0x0, 0x8 $_DEFAULT_ = 0x0800 - $gPlatformFspPkgTokenSpaceGuid_PcdMrcInitSPDAddr1 1 byte $_AS_BUILT_ = 0x0 $_DEFAULT_ = 0xA0 - $gPlatformFspPkgTokenSpaceGuid_PcdMrcInitSPDAddr2 1 byte $_AS_BUILT_ = 0x0 $_DEFAULT_ = 0xA2 - $gPlatformFspPkgTokenSpaceGuid_PcdeMMCBootMode 1 byte $_AS_BUILT_ = 0x3 $_DEFAULT_ = 2 - $gPlatformFspPkgTokenSpaceGuid_PcdEnableSdio 1 byte $_AS_BUILT_ = 0x1 $_DEFAULT_ = 1 - $gPlatformFspPkgTokenSpaceGuid_PcdEnableSdcard 1 byte $_AS_BUILT_ = 0x1 $_DEFAULT_ = 1 - $gPlatformFspPkgTokenSpaceGuid_PcdEnableHsuart0 1 byte $_AS_BUILT_ = 0x0 $_DEFAULT_ = 0 - $gPlatformFspPkgTokenSpaceGuid_PcdEnableHsuart1 1 byte $_AS_BUILT_ = 0x1 $_DEFAULT_ = 1 - $gPlatformFspPkgTokenSpaceGuid_PcdEnableSpi 1 byte $_AS_BUILT_ = 0x1 $_DEFAULT_ = 1 - $gPlatformFspPkgTokenSpaceGuid_PcdEnableLan 1 byte $_AS_BUILT_ = 0x1 $_DEFAULT_ = 1 - $gPlatformFspPkgTokenSpaceGuid_PcdEnableSata 1 byte $_AS_BUILT_ = 0x1 $_DEFAULT_ = 1 - $gPlatformFspPkgTokenSpaceGuid_PcdSataMode 1 byte $_AS_BUILT_ = 0x1 $_DEFAULT_ = 1 - $gPlatformFspPkgTokenSpaceGuid_PcdEnableAzalia 1 byte $_AS_BUILT_ = 0x0 $_DEFAULT_ = 0 - $gPlatformFspPkgTokenSpaceGuid_AzaliaConfigPtr 4 bytes $_AS_BUILT_ = 0x0, 0x0, 0x0, 0x0 $_DEFAULT_ = 0 - $gPlatformFspPkgTokenSpaceGuid_PcdEnableXhci 1 byte $_AS_BUILT_ = 0x1 $_DEFAULT_ = 1 - $gPlatformFspPkgTokenSpaceGuid_PcdEnableLpe 1 byte $_AS_BUILT_ = 0x1 $_DEFAULT_ = 1 - $gPlatformFspPkgTokenSpaceGuid_PcdLpssSioEnablePciMode 1 byte $_AS_BUILT_ = 0x1 $_DEFAULT_ = 1 - $gPlatformFspPkgTokenSpaceGuid_PcdEnableDma0 1 byte $_AS_BUILT_ = 0x1 $_DEFAULT_ = 1 - $gPlatformFspPkgTokenSpaceGuid_PcdEnableDma1 1 byte $_AS_BUILT_ = 0x1 $_DEFAULT_ = 1 - $gPlatformFspPkgTokenSpaceGuid_PcdEnableI2C0 1 byte $_AS_BUILT_ = 0x1 $_DEFAULT_ = 1 - $gPlatformFspPkgTokenSpaceGuid_PcdEnableI2C1 1 byte $_AS_BUILT_ = 0x1 $_DEFAULT_ = 1 - $gPlatformFspPkgTokenSpaceGuid_PcdEnableI2C2 1 byte $_AS_BUILT_ = 0x1 $_DEFAULT_ = 1 - $gPlatformFspPkgTokenSpaceGuid_PcdEnableI2C3 1 byte $_AS_BUILT_ = 0x1 $_DEFAULT_ = 1 - $gPlatformFspPkgTokenSpaceGuid_PcdEnableI2C4 1 byte $_AS_BUILT_ = 0x1 $_DEFAULT_ = 1 - $gPlatformFspPkgTokenSpaceGuid_PcdEnableI2C5 1 byte $_AS_BUILT_ = 0x1 $_DEFAULT_ = 1 - $gPlatformFspPkgTokenSpaceGuid_PcdEnableI2C6 1 byte $_AS_BUILT_ = 0x1 $_DEFAULT_ = 1 - $gPlatformFspPkgTokenSpaceGuid_PcdEnablePwm0 1 byte $_AS_BUILT_ = 0x1 $_DEFAULT_ = 1 - $gPlatformFspPkgTokenSpaceGuid_PcdEnablePwm1 1 byte $_AS_BUILT_ = 0x1 $_DEFAULT_ = 1 - $gPlatformFspPkgTokenSpaceGuid_PcdEnableHsi 1 byte $_AS_BUILT_ = 0x0 $_DEFAULT_ = 0 - $gPlatformFspPkgTokenSpaceGuid_PcdIgdDvmt50PreAlloc 1 byte $_AS_BUILT_ = 0x2 $_DEFAULT_ = 2 - $gPlatformFspPkgTokenSpaceGuid_PcdApertureSize 1 byte $_AS_BUILT_ = 0x2 $_DEFAULT_ = 2 - $gPlatformFspPkgTokenSpaceGuid_PcdGttSize 1 byte $_AS_BUILT_ = 0x2 $_DEFAULT_ = 2 - $gPlatformFspPkgTokenSpaceGuid_ISPEnable 1 bytes $_AS_BUILT_ = 0x0 $_DEFAULT_ = 0 - - Find "VLYVIEW1" - $gPlatformFspPkgTokenSpaceGuid_PcdImageRevision 4 bytes $_AS_BUILT_ = 0x2, 0x3, 0x0, 0x0 $_DEFAULT_ = 0x00000302 - Skip 24 bytes - $gPlatformFspPkgTokenSpaceGuid_PcdPlatformType 1 byte $_AS_BUILT_ = 0x2 $_DEFAULT_ = 2 - $gPlatformFspPkgTokenSpaceGuid_PcdEnableSecureBoot 1 byte $_AS_BUILT_ = 0x0 $_DEFAULT_ = 2 - - $DIMM_MemDown 1 byte $_AS_BUILT_ = 0x1 $_DEFAULT_ = 0 - $DRAM_Speed 1 byte $_AS_BUILT_ = 0x1 $_DEFAULT_ = 2 - $DRAM_Type 1 byte $_AS_BUILT_ = 0x1 $_DEFAULT_ = 1 - $Rank_En_0_0 1 byte $_AS_BUILT_ = 0x1 $_DEFAULT_ = 1 - $Rank_En_1_0 1 byte $_AS_BUILT_ = 0x0 $_DEFAULT_ = 0 - $DIMM_DWidth_0_0 1 byte $_AS_BUILT_ = 0x1 $_DEFAULT_ = 0 - $DIMM_Density_0_0 1 byte $_AS_BUILT_ = 0x1 $_DEFAULT_ = 1 - $DIMM_BusWidth_0_0 1 byte $_AS_BUILT_ = 0x3 $_DEFAULT_ = 3 - $DIMM_Sides_0_0 1 byte $_AS_BUILT_ = 0x0 $_DEFAULT_ = 0 - $tCL 1 byte $_AS_BUILT_ = 0x7 $_DEFAULT_ = 9 - $tRP_tRCD 1 byte $_AS_BUILT_ = 0x7 $_DEFAULT_ = 9 - $tWR 1 byte $_AS_BUILT_ = 0x8 $_DEFAULT_ = 10 - $tWTR 1 byte $_AS_BUILT_ = 0x4 $_DEFAULT_ = 5 - $tRRD 1 byte $_AS_BUILT_ = 0x6 $_DEFAULT_ = 4 - $tRTP 1 byte $_AS_BUILT_ = 0x4 $_DEFAULT_ = 5 - $tFAW 1 byte $_AS_BUILT_ = 0x14 $_DEFAULT_ = 20 - -EndStruct - -List &DRAMSPEED - Selection 0x0 , "800 MHz" - Selection 0x1 , "1066 MHz" - Selection 0x2 , "1333 MHz" - Selection 0x3 , "1600 MHz" -EndList - -List &DRAMTYPE - Selection 0x0 , "DDR3" - Selection 0x1 , "DDR3L" - Selection 0x2 , "DDR3U" - //Selection 0x3 , "LPDDR2" - Selection 0x4 , "LPDDR2" - Selection 0x5 , "LPDDR3" - Selection 0x6 , "DDR4" -EndList - -List &DIMMDWIDTH - Selection 0x0 , "x8" - Selection 0x1 , "x16" - Selection 0x2 , "x32" -EndList - -List &DIMMDENSITY - Selection 0x0 , "1 Gbit" - Selection 0x1 , "2 Gbit" - Selection 0x2 , "4 Gbit" - Selection 0x3 , "8 Gbit" -EndList - -List &DIMMBUSWIDTH - Selection 0x0 , "8 bits" - Selection 0x1 , "16 bits" - Selection 0x2 , "32 bits" - Selection 0x3 , "64 bits" -EndList - -List &RANKPERDIMM - Selection 0x1 , "2 Ranks" - Selection 0x0 , "1 Rank" -EndList - -List &SATA_MODE - Selection 0x1 , "AHCI" - Selection 0x0 , "IDE" -EndList - -List &EMMC_MODES - Selection 0x0 , "Disabled" - Selection 0x1 , "Auto" - Selection 0x2 , "eMMC 4.1" - Selection 0x3 , "eMMC 4.5" -EndList - -List &EN_DIS - Selection 0x1 , "Enabled" - Selection 0x0 , "Disabled" -EndList - -List &EN_DIS_AUTO - Selection 0x2 , "Auto" - Selection 0x1 , "Enabled" - Selection 0x0 , "Disabled" -EndList - -List &MMIO_SIZES - Selection 0x400, "1.0 GB" - Selection 0x600, "1.5 GB" - Selection 0x800, "2.0 GB" -EndList - -List &TSEG_SIZES - Selection 0x01, "1 MB" - Selection 0x02, "2 MB" - Selection 0x04, "4 MB" - Selection 0x08, "8 MB" -EndList - -List &IGDPREALLOC_SIZES - Selection 0x01, "32 MB" - Selection 0x02, "64 MB" - Selection 0x03, "96 MB" - Selection 0x04, "128 MB" - Selection 0x05, "160 MB" - Selection 0x06, "192 MB" - Selection 0x07, "224 MB" - Selection 0x08, "256 MB" - Selection 0x09, "288 MB" - Selection 0x0A, "320 MB" - Selection 0x0B, "352 MB" - Selection 0x0C, "384 MB" - Selection 0x0D, "416 MB" - Selection 0x0E, "448 MB" - Selection 0x0F, "480 MB" - Selection 0x10, "512 MB" -EndList - -List &APERTURE_SIZES - Selection 0x1 , "128 MB" - Selection 0x2 , "256 MB" - Selection 0x3 , "512 MB" -EndList - -List >T_SIZES - Selection 0x1 , "1 MB" - Selection 0x2 , "2 MB" -EndList - -List &PCI_ACPI - Selection 0x2 , "ACPI Mode" - Selection 0x1 , "PCI Mode" - Selection 0x0 , "Disabled" -EndList - -List &PLATFORM_TYPE - Selection 0x2 , "BayleyBay Platform Type" - Selection 0x3 , "BakerSport Platform (ECC) Type" -EndList - -BeginInfoBlock - PPVer "1.0" - Description "MinnowMax" - -EndInfoBlock - -Page "Platform" - Combo $gPlatformFspPkgTokenSpaceGuid_PcdPlatformType, "Platform Type", &PLATFORM_TYPE, - Help "Select Platform Type." - Combo $gPlatformFspPkgTokenSpaceGuid_PcdEnableSecureBoot, "Enable Secure Boot", &EN_DIS_AUTO, - Help "Enable/disable secure boot. Auto by default." -EndPage - -Page "North Complex" - Combo $gPlatformFspPkgTokenSpaceGuid_PcdMrcInitTsegSize, "Tseg Size", &TSEG_SIZES, - Help "Size of memory reserved for SMRAM, in MB." - Combo $gPlatformFspPkgTokenSpaceGuid_PcdMrcInitMmioSize, "Mmio Size", &MMIO_SIZES, - Help "Size of memory address space reserved for MMIO (Memory Mapped I/O), in GB." - Combo $gPlatformFspPkgTokenSpaceGuid_PcdIgdDvmt50PreAlloc, "Internal Graphics Pre-allocated Memory ", &IGDPREALLOC_SIZES, - Help "Size of memory preallocated for internal graphics" - Combo $gPlatformFspPkgTokenSpaceGuid_PcdApertureSize, "Aperture Size", &APERTURE_SIZES, - Help "Select the Aperture Size" - Combo $gPlatformFspPkgTokenSpaceGuid_PcdGttSize, "GTT Size", >T_SIZES, - Help "Select the GTT Size" - EditNum $gPlatformFspPkgTokenSpaceGuid_PcdMrcInitSPDAddr1, "DIMM 0 SPD SMBus Address", HEX, - Help "Address of DIMM 0. 8 bits" - EditNum $gPlatformFspPkgTokenSpaceGuid_PcdMrcInitSPDAddr2, "DIMM 1 SPD SMBus Address", HEX, - Help "Address of DIMM 1. 8 bits" -EndPage - -Page "Memory Down" - Combo $DIMM_MemDown, "Enable Memory Down", &EN_DIS, - Help "Enable = Memory Down, Disable = DIMM" - Combo $DRAM_Speed, "DRAM Speed", &DRAMSPEED, - Help "DRAM Speed" - Combo $DRAM_Type, "DRAM Type", &DRAMTYPE, - Help "DRAM Type" - Combo $Rank_En_0_0, "DIMM 0 Enable", &EN_DIS, - Help "Please populate DIMM slot 0 if only one DIMM is supported." - Combo $Rank_En_1_0, "DIMM 1 Enable", &EN_DIS, - Help "DIMM 1 has to be identical to DIMM 0." - Combo $DIMM_DWidth_0_0, "DIMM_DWidth", &DIMMDWIDTH, - Help "DRAM device data width." - Combo $DIMM_Density_0_0, "DIMM_Density", &DIMMDENSITY, - Help "DRAM device data density." - Combo $DIMM_BusWidth_0_0, "DIMM_BusWidth", &DIMMBUSWIDTH, - Help "DIMM Bus Width." - Combo $DIMM_Sides_0_0, "DIMM_Sides", &RANKPERDIMM, - Help "Ranks Per DIMM. " - EditNum $tCL, "tCL", DEC, - Help "tCL" - EditNum $tRP_tRCD, "tRP_tRCD", DEC, - Help "tRP and tRCD in DRAM clk - 5:12.5ns, 6:15ns, etc." - EditNum $tWR, "tWR", DEC, - Help "tWR in DRAM clk" - EditNum $tWTR, "tWTR", DEC, - Help "tWTR in DRAM clk" - EditNum $tRRD, "tRRD", DEC, - Help "tRRD in DRAM clk" - EditNum $tRTP, "tRTP", DEC, - Help "tRTP in DRAM clk" - EditNum $tFAW, "tFAW", DEC, - Help "tFAW in DRAM clk" -EndPage - -Page "South Complex" - Combo $gPlatformFspPkgTokenSpaceGuid_PcdSataMode, "Select SATA Mode", &SATA_MODE, - Help "Select SATA boot mode. AHCI by default." - Combo $gPlatformFspPkgTokenSpaceGuid_PcdEnableXhci, "Enable XHCI", &EN_DIS, - Help "Enable/disable XHCI. If enabled, all EHCI ports will be routed to XHCI and EHCI will be disabled." - Combo $gPlatformFspPkgTokenSpaceGuid_PcdeMMCBootMode, "eMMC Boot Mode", &EMMC_MODES, - Help "Select EMMC Mode." - Combo $gPlatformFspPkgTokenSpaceGuid_PcdEnableSdio, "Enable SDIO", &EN_DIS, - Help "Enable/disable SDIO." - Combo $gPlatformFspPkgTokenSpaceGuid_PcdEnableSdcard, "Enable SD Card", &EN_DIS, - Help "Enable/disable the SD Card." - Combo $gPlatformFspPkgTokenSpaceGuid_PcdEnableHsuart0, "Enable HSUART0", &EN_DIS, - Help "Enable/disable HSUART0." - Combo $gPlatformFspPkgTokenSpaceGuid_PcdEnableHsuart1, "Enable HSUART1", &EN_DIS, - Help "Enable/disable HSUART1." - Combo $gPlatformFspPkgTokenSpaceGuid_PcdEnableSpi, "Enable SPI", &EN_DIS, - Help "Enable/disable SPI." - Combo $gPlatformFspPkgTokenSpaceGuid_PcdEnableLan, "Enable LAN", &EN_DIS, - Help "Enable/disable LAN." - Combo $gPlatformFspPkgTokenSpaceGuid_PcdEnableAzalia, "Enable Azalia", &EN_DIS_AUTO, - Help "Enable/disable Azalia. Auto by default." - Combo $gPlatformFspPkgTokenSpaceGuid_PcdEnableSata, "Enable SATA", &EN_DIS, - Help "Enable/disable SATA." - Combo $gPlatformFspPkgTokenSpaceGuid_PcdEnableLpe, "Enable LPE", &PCI_ACPI, - Help "Choose LPE Mode" - Combo $gPlatformFspPkgTokenSpaceGuid_PcdLpssSioEnablePciMode, "Enable PCI mode for LPSS SIO devices", &EN_DIS, - Help "Enable PCI Mode for LPSS SIO devices. If disabled, LPSS SIO devices will run in ACPI mode." - Combo $gPlatformFspPkgTokenSpaceGuid_PcdEnableDma0, "Enable DMA0", &EN_DIS, - Help "Enable/disable DMA0" - Combo $gPlatformFspPkgTokenSpaceGuid_PcdEnableDma1, "Enable DMA1", &EN_DIS, - Help "Enable/disable DMA1" - Combo $gPlatformFspPkgTokenSpaceGuid_PcdEnableI2C0, "Enable I2C0", &EN_DIS, - Help "Enable/disable I2C0" - Combo $gPlatformFspPkgTokenSpaceGuid_PcdEnableI2C1, "Enable I2C1", &EN_DIS, - Help "Enable/disable I2C1" - Combo $gPlatformFspPkgTokenSpaceGuid_PcdEnableI2C2, "Enable I2C2", &EN_DIS, - Help "Enable/disable I2C2" - Combo $gPlatformFspPkgTokenSpaceGuid_PcdEnableI2C3, "Enable I2C3", &EN_DIS, - Help "Enable/disable I2C3" - Combo $gPlatformFspPkgTokenSpaceGuid_PcdEnableI2C4, "Enable I2C4", &EN_DIS, - Help "Enable/disable I2C4" - Combo $gPlatformFspPkgTokenSpaceGuid_PcdEnableI2C5, "Enable I2C5", &EN_DIS, - Help "Enable/disable I2C5" - Combo $gPlatformFspPkgTokenSpaceGuid_PcdEnableI2C6, "Enable I2C6", &EN_DIS, - Help "Enable/disable I2C6" - Combo $gPlatformFspPkgTokenSpaceGuid_PcdEnablePwm0, "Enable PWM0", &EN_DIS, - Help "Enable/disable PWM0" - Combo $gPlatformFspPkgTokenSpaceGuid_PcdEnablePwm1, "Enable PWM1", &EN_DIS, - Help "Enable/disable PWM1" - Combo $gPlatformFspPkgTokenSpaceGuid_PcdEnableHsi, "Enable HSI", &EN_DIS, - Help "Enable/disable HSI" - Combo $gPlatformFspPkgTokenSpaceGuid_ISPEnable, "Enable ISP", &EN_DIS, - Help "Enable/disable ISP." -EndPage diff --git a/src/vendorcode/intel/fsp1_0/baytrail/absf/minnowmax_2gb.absf b/src/vendorcode/intel/fsp1_0/baytrail/absf/minnowmax_2gb.absf deleted file mode 100644 index 6992fe7dce..0000000000 --- a/src/vendorcode/intel/fsp1_0/baytrail/absf/minnowmax_2gb.absf +++ /dev/null @@ -1,328 +0,0 @@ -// -// This file contains an 'Intel Peripheral Driver' and is -// licensed for Intel CPUs and chipsets under the terms of your -// license agreement with Intel or your vendor. This file must not -// be modified by end users or could render the generated boot loader -// inoperable. -// -// @file -// Boot Setting File for Platform: Bayley Bay Platform -// -// Copyright (c) 2010-2013 Intel Corporation. All rights reserved -// This software and associated documentation (if any) is furnished -// under a license and may only be used or copied in accordance -// with the terms of the license. Except as permitted by such -// license, no part of this software or documentation may be -// reproduced, stored in a retrieval system, or transmitted in any -// form or by any means without the express written consent of -// Intel Corporation. -// -// - - -GlobalDataDef - SKUID = 0 $_AS_BUILT_ = 0x01 , "DEFAULT" -EndGlobalData - -StructDef - - Find "VLV2UPDR" - Skip 24 bytes - $gPlatformFspPkgTokenSpaceGuid_PcdMrcInitTsegSize 2 bytes $_AS_BUILT_ = 0x1, 0x0 $_DEFAULT_ = 0x0001 - $gPlatformFspPkgTokenSpaceGuid_PcdMrcInitMmioSize 2 bytes $_AS_BUILT_ = 0x0, 0x8 $_DEFAULT_ = 0x0800 - $gPlatformFspPkgTokenSpaceGuid_PcdMrcInitSPDAddr1 1 byte $_AS_BUILT_ = 0x0 $_DEFAULT_ = 0xA0 - $gPlatformFspPkgTokenSpaceGuid_PcdMrcInitSPDAddr2 1 byte $_AS_BUILT_ = 0x0 $_DEFAULT_ = 0xA2 - $gPlatformFspPkgTokenSpaceGuid_PcdeMMCBootMode 1 byte $_AS_BUILT_ = 0x3 $_DEFAULT_ = 2 - $gPlatformFspPkgTokenSpaceGuid_PcdEnableSdio 1 byte $_AS_BUILT_ = 0x1 $_DEFAULT_ = 1 - $gPlatformFspPkgTokenSpaceGuid_PcdEnableSdcard 1 byte $_AS_BUILT_ = 0x1 $_DEFAULT_ = 1 - $gPlatformFspPkgTokenSpaceGuid_PcdEnableHsuart0 1 byte $_AS_BUILT_ = 0x0 $_DEFAULT_ = 0 - $gPlatformFspPkgTokenSpaceGuid_PcdEnableHsuart1 1 byte $_AS_BUILT_ = 0x1 $_DEFAULT_ = 1 - $gPlatformFspPkgTokenSpaceGuid_PcdEnableSpi 1 byte $_AS_BUILT_ = 0x1 $_DEFAULT_ = 1 - $gPlatformFspPkgTokenSpaceGuid_PcdEnableLan 1 byte $_AS_BUILT_ = 0x1 $_DEFAULT_ = 1 - $gPlatformFspPkgTokenSpaceGuid_PcdEnableSata 1 byte $_AS_BUILT_ = 0x1 $_DEFAULT_ = 1 - $gPlatformFspPkgTokenSpaceGuid_PcdSataMode 1 byte $_AS_BUILT_ = 0x1 $_DEFAULT_ = 1 - $gPlatformFspPkgTokenSpaceGuid_PcdEnableAzalia 1 byte $_AS_BUILT_ = 0x0 $_DEFAULT_ = 0 - $gPlatformFspPkgTokenSpaceGuid_AzaliaConfigPtr 4 bytes $_AS_BUILT_ = 0x0, 0x0, 0x0, 0x0 $_DEFAULT_ = 0 - $gPlatformFspPkgTokenSpaceGuid_PcdEnableXhci 1 byte $_AS_BUILT_ = 0x1 $_DEFAULT_ = 1 - $gPlatformFspPkgTokenSpaceGuid_PcdEnableLpe 1 byte $_AS_BUILT_ = 0x1 $_DEFAULT_ = 1 - $gPlatformFspPkgTokenSpaceGuid_PcdLpssSioEnablePciMode 1 byte $_AS_BUILT_ = 0x1 $_DEFAULT_ = 1 - $gPlatformFspPkgTokenSpaceGuid_PcdEnableDma0 1 byte $_AS_BUILT_ = 0x1 $_DEFAULT_ = 1 - $gPlatformFspPkgTokenSpaceGuid_PcdEnableDma1 1 byte $_AS_BUILT_ = 0x1 $_DEFAULT_ = 1 - $gPlatformFspPkgTokenSpaceGuid_PcdEnableI2C0 1 byte $_AS_BUILT_ = 0x1 $_DEFAULT_ = 1 - $gPlatformFspPkgTokenSpaceGuid_PcdEnableI2C1 1 byte $_AS_BUILT_ = 0x1 $_DEFAULT_ = 1 - $gPlatformFspPkgTokenSpaceGuid_PcdEnableI2C2 1 byte $_AS_BUILT_ = 0x1 $_DEFAULT_ = 1 - $gPlatformFspPkgTokenSpaceGuid_PcdEnableI2C3 1 byte $_AS_BUILT_ = 0x1 $_DEFAULT_ = 1 - $gPlatformFspPkgTokenSpaceGuid_PcdEnableI2C4 1 byte $_AS_BUILT_ = 0x1 $_DEFAULT_ = 1 - $gPlatformFspPkgTokenSpaceGuid_PcdEnableI2C5 1 byte $_AS_BUILT_ = 0x1 $_DEFAULT_ = 1 - $gPlatformFspPkgTokenSpaceGuid_PcdEnableI2C6 1 byte $_AS_BUILT_ = 0x1 $_DEFAULT_ = 1 - $gPlatformFspPkgTokenSpaceGuid_PcdEnablePwm0 1 byte $_AS_BUILT_ = 0x1 $_DEFAULT_ = 1 - $gPlatformFspPkgTokenSpaceGuid_PcdEnablePwm1 1 byte $_AS_BUILT_ = 0x1 $_DEFAULT_ = 1 - $gPlatformFspPkgTokenSpaceGuid_PcdEnableHsi 1 byte $_AS_BUILT_ = 0x0 $_DEFAULT_ = 0 - $gPlatformFspPkgTokenSpaceGuid_PcdIgdDvmt50PreAlloc 1 byte $_AS_BUILT_ = 0x2 $_DEFAULT_ = 2 - $gPlatformFspPkgTokenSpaceGuid_PcdApertureSize 1 byte $_AS_BUILT_ = 0x2 $_DEFAULT_ = 2 - $gPlatformFspPkgTokenSpaceGuid_PcdGttSize 1 byte $_AS_BUILT_ = 0x2 $_DEFAULT_ = 2 - $gPlatformFspPkgTokenSpaceGuid_ISPEnable 1 bytes $_AS_BUILT_ = 0x0 $_DEFAULT_ = 0 - - Find "VLYVIEW1" - $gPlatformFspPkgTokenSpaceGuid_PcdImageRevision 4 bytes $_AS_BUILT_ = 0x2, 0x3, 0x0, 0x0 $_DEFAULT_ = 0x00000302 - Skip 24 bytes - $gPlatformFspPkgTokenSpaceGuid_PcdPlatformType 1 byte $_AS_BUILT_ = 0x2 $_DEFAULT_ = 2 - $gPlatformFspPkgTokenSpaceGuid_PcdEnableSecureBoot 1 byte $_AS_BUILT_ = 0x0 $_DEFAULT_ = 2 - - $DIMM_MemDown 1 byte $_AS_BUILT_ = 0x1 $_DEFAULT_ = 0 - $DRAM_Speed 1 byte $_AS_BUILT_ = 0x1 $_DEFAULT_ = 2 - $DRAM_Type 1 byte $_AS_BUILT_ = 0x1 $_DEFAULT_ = 1 - $Rank_En_0_0 1 byte $_AS_BUILT_ = 0x1 $_DEFAULT_ = 1 - $Rank_En_1_0 1 byte $_AS_BUILT_ = 0x0 $_DEFAULT_ = 0 - $DIMM_DWidth_0_0 1 byte $_AS_BUILT_ = 0x1 $_DEFAULT_ = 0 - $DIMM_Density_0_0 1 byte $_AS_BUILT_ = 0x2 $_DEFAULT_ = 1 - $DIMM_BusWidth_0_0 1 byte $_AS_BUILT_ = 0x3 $_DEFAULT_ = 3 - $DIMM_Sides_0_0 1 byte $_AS_BUILT_ = 0x0 $_DEFAULT_ = 0 - $tCL 1 byte $_AS_BUILT_ = 0x7 $_DEFAULT_ = 9 - $tRP_tRCD 1 byte $_AS_BUILT_ = 0x7 $_DEFAULT_ = 9 - $tWR 1 byte $_AS_BUILT_ = 0x8 $_DEFAULT_ = 10 - $tWTR 1 byte $_AS_BUILT_ = 0x4 $_DEFAULT_ = 5 - $tRRD 1 byte $_AS_BUILT_ = 0x6 $_DEFAULT_ = 4 - $tRTP 1 byte $_AS_BUILT_ = 0x4 $_DEFAULT_ = 5 - $tFAW 1 byte $_AS_BUILT_ = 0x14 $_DEFAULT_ = 20 - -EndStruct - -List &DRAMSPEED - Selection 0x0 , "800 MHz" - Selection 0x1 , "1066 MHz" - Selection 0x2 , "1333 MHz" - Selection 0x3 , "1600 MHz" -EndList - -List &DRAMTYPE - Selection 0x0 , "DDR3" - Selection 0x1 , "DDR3L" - Selection 0x2 , "DDR3U" - //Selection 0x3 , "LPDDR2" - Selection 0x4 , "LPDDR2" - Selection 0x5 , "LPDDR3" - Selection 0x6 , "DDR4" -EndList - -List &DIMMDWIDTH - Selection 0x0 , "x8" - Selection 0x1 , "x16" - Selection 0x2 , "x32" -EndList - -List &DIMMDENSITY - Selection 0x0 , "1 Gbit" - Selection 0x1 , "2 Gbit" - Selection 0x2 , "4 Gbit" - Selection 0x3 , "8 Gbit" -EndList - -List &DIMMBUSWIDTH - Selection 0x0 , "8 bits" - Selection 0x1 , "16 bits" - Selection 0x2 , "32 bits" - Selection 0x3 , "64 bits" -EndList - -List &RANKPERDIMM - Selection 0x1 , "2 Ranks" - Selection 0x0 , "1 Rank" -EndList - -List &SATA_MODE - Selection 0x1 , "AHCI" - Selection 0x0 , "IDE" -EndList - -List &EMMC_MODES - Selection 0x0 , "Disabled" - Selection 0x1 , "Auto" - Selection 0x2 , "eMMC 4.1" - Selection 0x3 , "eMMC 4.5" -EndList - -List &EN_DIS - Selection 0x1 , "Enabled" - Selection 0x0 , "Disabled" -EndList - -List &EN_DIS_AUTO - Selection 0x2 , "Auto" - Selection 0x1 , "Enabled" - Selection 0x0 , "Disabled" -EndList - -List &MMIO_SIZES - Selection 0x400, "1.0 GB" - Selection 0x600, "1.5 GB" - Selection 0x800, "2.0 GB" -EndList - -List &TSEG_SIZES - Selection 0x01, "1 MB" - Selection 0x02, "2 MB" - Selection 0x04, "4 MB" - Selection 0x08, "8 MB" -EndList - -List &IGDPREALLOC_SIZES - Selection 0x01, "32 MB" - Selection 0x02, "64 MB" - Selection 0x03, "96 MB" - Selection 0x04, "128 MB" - Selection 0x05, "160 MB" - Selection 0x06, "192 MB" - Selection 0x07, "224 MB" - Selection 0x08, "256 MB" - Selection 0x09, "288 MB" - Selection 0x0A, "320 MB" - Selection 0x0B, "352 MB" - Selection 0x0C, "384 MB" - Selection 0x0D, "416 MB" - Selection 0x0E, "448 MB" - Selection 0x0F, "480 MB" - Selection 0x10, "512 MB" -EndList - -List &APERTURE_SIZES - Selection 0x1 , "128 MB" - Selection 0x2 , "256 MB" - Selection 0x3 , "512 MB" -EndList - -List >T_SIZES - Selection 0x1 , "1 MB" - Selection 0x2 , "2 MB" -EndList - -List &PCI_ACPI - Selection 0x2 , "ACPI Mode" - Selection 0x1 , "PCI Mode" - Selection 0x0 , "Disabled" -EndList - -List &PLATFORM_TYPE - Selection 0x2 , "BayleyBay Platform Type" - Selection 0x3 , "BakerSport Platform (ECC) Type" -EndList - -BeginInfoBlock - PPVer "1.0" - Description "MinnowMax" - -EndInfoBlock - -Page "Platform" - Combo $gPlatformFspPkgTokenSpaceGuid_PcdPlatformType, "Platform Type", &PLATFORM_TYPE, - Help "Select Platform Type." - Combo $gPlatformFspPkgTokenSpaceGuid_PcdEnableSecureBoot, "Enable Secure Boot", &EN_DIS_AUTO, - Help "Enable/disable secure boot. Auto by default." -EndPage - -Page "North Complex" - Combo $gPlatformFspPkgTokenSpaceGuid_PcdMrcInitTsegSize, "Tseg Size", &TSEG_SIZES, - Help "Size of memory reserved for SMRAM, in MB." - Combo $gPlatformFspPkgTokenSpaceGuid_PcdMrcInitMmioSize, "Mmio Size", &MMIO_SIZES, - Help "Size of memory address space reserved for MMIO (Memory Mapped I/O), in GB." - Combo $gPlatformFspPkgTokenSpaceGuid_PcdIgdDvmt50PreAlloc, "Internal Graphics Pre-allocated Memory ", &IGDPREALLOC_SIZES, - Help "Size of memory preallocated for internal graphics" - Combo $gPlatformFspPkgTokenSpaceGuid_PcdApertureSize, "Aperture Size", &APERTURE_SIZES, - Help "Select the Aperture Size" - Combo $gPlatformFspPkgTokenSpaceGuid_PcdGttSize, "GTT Size", >T_SIZES, - Help "Select the GTT Size" - EditNum $gPlatformFspPkgTokenSpaceGuid_PcdMrcInitSPDAddr1, "DIMM 0 SPD SMBus Address", HEX, - Help "Address of DIMM 0. 8 bits" - EditNum $gPlatformFspPkgTokenSpaceGuid_PcdMrcInitSPDAddr2, "DIMM 1 SPD SMBus Address", HEX, - Help "Address of DIMM 1. 8 bits" -EndPage - -Page "Memory Down" - Combo $DIMM_MemDown, "Enable Memory Down", &EN_DIS, - Help "Enable = Memory Down, Disable = DIMM" - Combo $DRAM_Speed, "DRAM Speed", &DRAMSPEED, - Help "DRAM Speed" - Combo $DRAM_Type, "DRAM Type", &DRAMTYPE, - Help "DRAM Type" - Combo $Rank_En_0_0, "DIMM 0 Enable", &EN_DIS, - Help "Please populate DIMM slot 0 if only one DIMM is supported." - Combo $Rank_En_1_0, "DIMM 1 Enable", &EN_DIS, - Help "DIMM 1 has to be identical to DIMM 0." - Combo $DIMM_DWidth_0_0, "DIMM_DWidth", &DIMMDWIDTH, - Help "DRAM device data width." - Combo $DIMM_Density_0_0, "DIMM_Density", &DIMMDENSITY, - Help "DRAM device data density." - Combo $DIMM_BusWidth_0_0, "DIMM_BusWidth", &DIMMBUSWIDTH, - Help "DIMM Bus Width." - Combo $DIMM_Sides_0_0, "DIMM_Sides", &RANKPERDIMM, - Help "Ranks Per DIMM. " - EditNum $tCL, "tCL", DEC, - Help "tCL" - EditNum $tRP_tRCD, "tRP_tRCD", DEC, - Help "tRP and tRCD in DRAM clk - 5:12.5ns, 6:15ns, etc." - EditNum $tWR, "tWR", DEC, - Help "tWR in DRAM clk" - EditNum $tWTR, "tWTR", DEC, - Help "tWTR in DRAM clk" - EditNum $tRRD, "tRRD", DEC, - Help "tRRD in DRAM clk" - EditNum $tRTP, "tRTP", DEC, - Help "tRTP in DRAM clk" - EditNum $tFAW, "tFAW", DEC, - Help "tFAW in DRAM clk" -EndPage - -Page "South Complex" - Combo $gPlatformFspPkgTokenSpaceGuid_PcdSataMode, "Select SATA Mode", &SATA_MODE, - Help "Select SATA boot mode. AHCI by default." - Combo $gPlatformFspPkgTokenSpaceGuid_PcdEnableXhci, "Enable XHCI", &EN_DIS, - Help "Enable/disable XHCI. If enabled, all EHCI ports will be routed to XHCI and EHCI will be disabled." - Combo $gPlatformFspPkgTokenSpaceGuid_PcdeMMCBootMode, "eMMC Boot Mode", &EMMC_MODES, - Help "Select EMMC Mode." - Combo $gPlatformFspPkgTokenSpaceGuid_PcdEnableSdio, "Enable SDIO", &EN_DIS, - Help "Enable/disable SDIO." - Combo $gPlatformFspPkgTokenSpaceGuid_PcdEnableSdcard, "Enable SD Card", &EN_DIS, - Help "Enable/disable the SD Card." - Combo $gPlatformFspPkgTokenSpaceGuid_PcdEnableHsuart0, "Enable HSUART0", &EN_DIS, - Help "Enable/disable HSUART0." - Combo $gPlatformFspPkgTokenSpaceGuid_PcdEnableHsuart1, "Enable HSUART1", &EN_DIS, - Help "Enable/disable HSUART1." - Combo $gPlatformFspPkgTokenSpaceGuid_PcdEnableSpi, "Enable SPI", &EN_DIS, - Help "Enable/disable SPI." - Combo $gPlatformFspPkgTokenSpaceGuid_PcdEnableLan, "Enable LAN", &EN_DIS, - Help "Enable/disable LAN." - Combo $gPlatformFspPkgTokenSpaceGuid_PcdEnableAzalia, "Enable Azalia", &EN_DIS_AUTO, - Help "Enable/disable Azalia. Auto by default." - Combo $gPlatformFspPkgTokenSpaceGuid_PcdEnableSata, "Enable SATA", &EN_DIS, - Help "Enable/disable SATA." - Combo $gPlatformFspPkgTokenSpaceGuid_PcdEnableLpe, "Enable LPE", &PCI_ACPI, - Help "Choose LPE Mode" - Combo $gPlatformFspPkgTokenSpaceGuid_PcdLpssSioEnablePciMode, "Enable PCI mode for LPSS SIO devices", &EN_DIS, - Help "Enable PCI Mode for LPSS SIO devices. If disabled, LPSS SIO devices will run in ACPI mode." - Combo $gPlatformFspPkgTokenSpaceGuid_PcdEnableDma0, "Enable DMA0", &EN_DIS, - Help "Enable/disable DMA0" - Combo $gPlatformFspPkgTokenSpaceGuid_PcdEnableDma1, "Enable DMA1", &EN_DIS, - Help "Enable/disable DMA1" - Combo $gPlatformFspPkgTokenSpaceGuid_PcdEnableI2C0, "Enable I2C0", &EN_DIS, - Help "Enable/disable I2C0" - Combo $gPlatformFspPkgTokenSpaceGuid_PcdEnableI2C1, "Enable I2C1", &EN_DIS, - Help "Enable/disable I2C1" - Combo $gPlatformFspPkgTokenSpaceGuid_PcdEnableI2C2, "Enable I2C2", &EN_DIS, - Help "Enable/disable I2C2" - Combo $gPlatformFspPkgTokenSpaceGuid_PcdEnableI2C3, "Enable I2C3", &EN_DIS, - Help "Enable/disable I2C3" - Combo $gPlatformFspPkgTokenSpaceGuid_PcdEnableI2C4, "Enable I2C4", &EN_DIS, - Help "Enable/disable I2C4" - Combo $gPlatformFspPkgTokenSpaceGuid_PcdEnableI2C5, "Enable I2C5", &EN_DIS, - Help "Enable/disable I2C5" - Combo $gPlatformFspPkgTokenSpaceGuid_PcdEnableI2C6, "Enable I2C6", &EN_DIS, - Help "Enable/disable I2C6" - Combo $gPlatformFspPkgTokenSpaceGuid_PcdEnablePwm0, "Enable PWM0", &EN_DIS, - Help "Enable/disable PWM0" - Combo $gPlatformFspPkgTokenSpaceGuid_PcdEnablePwm1, "Enable PWM1", &EN_DIS, - Help "Enable/disable PWM1" - Combo $gPlatformFspPkgTokenSpaceGuid_PcdEnableHsi, "Enable HSI", &EN_DIS, - Help "Enable/disable HSI" - Combo $gPlatformFspPkgTokenSpaceGuid_ISPEnable, "Enable ISP", &EN_DIS, - Help "Enable/disable ISP." -EndPage diff --git a/src/vendorcode/intel/fsp1_0/baytrail/include/azalia.h b/src/vendorcode/intel/fsp1_0/baytrail/include/azalia.h deleted file mode 100644 index c58cf4ce4c..0000000000 --- a/src/vendorcode/intel/fsp1_0/baytrail/include/azalia.h +++ /dev/null @@ -1,66 +0,0 @@ -/**@file - -Copyright (C) 2013, Intel Corporation - -Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - -* Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. -* Redistributions in binary form must reproduce the above copyright notice, this - list of conditions and the following disclaimer in the documentation and/or - other materials provided with the distribution. -* Neither the name of Intel Corporation nor the names of its contributors may - be used to endorse or promote products derived from this software without - specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE - LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF - THE POSSIBILITY OF SUCH DAMAGE. - -**/ - -#ifndef _AZALIA_H_ -#define _AZALIA_H_ - -#include - -#pragma pack(1) - -typedef struct { - uint32_t VendorDeviceId; - uint16_t SubSystemId; - uint8_t RevisionId; /// 0xFF applies to all steppings - uint8_t FrontPanelSupport; - uint16_t NumberOfRearJacks; - uint16_t NumberOfFrontJacks; -} PCH_AZALIA_VERB_TABLE_HEADER; - -typedef struct { - PCH_AZALIA_VERB_TABLE_HEADER VerbTableHeader; - uint32_t *VerbTableData; -} PCH_AZALIA_VERB_TABLE; - -typedef struct { - uint8_t Pme : 1; /// 0: Disable; 1: Enable - uint8_t DS : 1; /// 0: Docking is not supported; 1:Docking is supported - uint8_t DA : 1; /// 0: Docking is not attached; 1:Docking is attached - uint8_t HdmiCodec : 1; /// 0: Disable; 1: Enable - uint8_t AzaliaVCi : 1; /// 0: Disable; 1: Enable - uint8_t Rsvdbits : 3; - uint8_t AzaliaVerbTableNum; /// Number of verb tables provided by platform - PCH_AZALIA_VERB_TABLE *AzaliaVerbTable; /// Pointer to the actual verb table(s) - uint16_t ResetWaitTimer; /// The delay timer after Azalia reset, the value is number of microseconds -} PCH_AZALIA_CONFIG; - -#pragma pack() - -#endif diff --git a/src/vendorcode/intel/fsp1_0/baytrail/include/fsp.h b/src/vendorcode/intel/fsp1_0/baytrail/include/fsp.h deleted file mode 100644 index f2e1d8fabf..0000000000 --- a/src/vendorcode/intel/fsp1_0/baytrail/include/fsp.h +++ /dev/null @@ -1,69 +0,0 @@ -/** - -Copyright (C) 2013, Intel Corporation - -Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - -* Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. -* Redistributions in binary form must reproduce the above copyright notice, this - list of conditions and the following disclaimer in the documentation and/or - other materials provided with the distribution. -* Neither the name of Intel Corporation nor the names of its contributors may - be used to endorse or promote products derived from this software without - specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE - LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF - THE POSSIBILITY OF SUCH DAMAGE. - -**/ - -/** \file fsp.h - * - * - */ -#include -#include "fsptypes.h" -#include "fspfv.h" -#include "fspffs.h" -#include "fsphob.h" -#include "fspapi.h" -#include "fspplatform.h" -#include "fspinfoheader.h" -#include "fspvpd.h" - -#define FSP_HOB_RESOURCE_OWNER_FSP_GUID \ -{ 0x69a79759, 0x1373, 0x4367, { 0xa6, 0xc4, 0xc7, 0xf5, 0x9e, 0xfd, 0x98, 0x6e } } -#define FSP_NON_VOLATILE_STORAGE_HOB_GUID \ -{ 0x721acf02, 0x4d77, 0x4c2a, { 0xb3, 0xdc, 0x27, 0xb, 0x7b, 0xa9, 0xe4, 0xb0 } } -#define FSP_HOB_RESOURCE_OWNER_TSEG_GUID \ -{ 0xd038747c, 0xd00c, 0x4980, { 0xb3, 0x19, 0x49, 0x01, 0x99, 0xa4, 0x7d, 0x55 } } -#define FSP_HOB_RESOURCE_OWNER_GRAPHICS_GUID \ -{ 0x9c7c3aa7, 0x5332, 0x4917, { 0x82, 0xb9, 0x56, 0xa5, 0xf3, 0xe6, 0x2a, 0x07 } } -#define FSP_BOOTLOADER_TEMPORARY_MEMORY_HOB_GUID \ -{ 0xbbcff46c, 0xc8d3, 0x4113, { 0x89, 0x85, 0xb9, 0xd4, 0xf3, 0xb3, 0xf6, 0x4e } } - -// -// 0x21 - 0xf..f are reserved. -// -#define BOOT_WITH_FULL_CONFIGURATION 0x00 -#define BOOT_WITH_MINIMAL_CONFIGURATION 0x01 -#define BOOT_ASSUMING_NO_CONFIGURATION_CHANGES 0x02 -#define BOOT_WITH_FULL_CONFIGURATION_PLUS_DIAGNOSTICS 0x03 -#define BOOT_WITH_DEFAULT_SETTINGS 0x04 -#define BOOT_ON_S4_RESUME 0x05 -#define BOOT_ON_S5_RESUME 0x06 -#define BOOT_ON_S2_RESUME 0x10 -#define BOOT_ON_S3_RESUME 0x11 -#define BOOT_ON_FLASH_UPDATE 0x12 -#define BOOT_IN_RECOVERY_MODE 0x20 diff --git a/src/vendorcode/intel/fsp1_0/baytrail/include/fspapi.h b/src/vendorcode/intel/fsp1_0/baytrail/include/fspapi.h deleted file mode 100644 index 26afc0efdf..0000000000 --- a/src/vendorcode/intel/fsp1_0/baytrail/include/fspapi.h +++ /dev/null @@ -1,65 +0,0 @@ -/** - -Copyright (C) 2013, Intel Corporation - -Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - -* Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. -* Redistributions in binary form must reproduce the above copyright notice, this - list of conditions and the following disclaimer in the documentation and/or - other materials provided with the distribution. -* Neither the name of Intel Corporation nor the names of its contributors may - be used to endorse or promote products derived from this software without - specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE - LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF - THE POSSIBILITY OF SUCH DAMAGE. - -**/ - -#ifndef _FSP_API_H_ -#define _FSP_API_H_ - -#pragma pack(1) - -typedef VOID (* CONTINUATION_PROC)(EFI_STATUS Status, VOID *HobListPtr); - -typedef struct { - VOID *NvsBufferPtr; - VOID *RtBufferPtr; - CONTINUATION_PROC ContinuationFunc; -} FSP_INIT_PARAMS; - -typedef struct { - UINT32 *StackTop; - UINT32 BootMode; - VOID *UpdDataRgnPtr; - UINT32 Reserved[7]; -} FSP_INIT_RT_COMMON_BUFFER; - -typedef enum { - EnumInitPhaseAfterPciEnumeration = 0x20, - EnumInitPhaseReadyToBoot = 0x40 -} FSP_INIT_PHASE; - -typedef struct { - FSP_INIT_PHASE Phase; -} NOTIFY_PHASE_PARAMS; - -#pragma pack() - -typedef FSP_STATUS (FSPAPI *FSP_FSP_INIT) (FSP_INIT_PARAMS *FspInitParamPtr); -typedef FSP_STATUS (FSPAPI *FSP_NOTFY_PHASE) (NOTIFY_PHASE_PARAMS *NotifyPhaseParamPtr); - -#endif diff --git a/src/vendorcode/intel/fsp1_0/baytrail/include/fspffs.h b/src/vendorcode/intel/fsp1_0/baytrail/include/fspffs.h deleted file mode 100644 index f3b83b2a3e..0000000000 --- a/src/vendorcode/intel/fsp1_0/baytrail/include/fspffs.h +++ /dev/null @@ -1,506 +0,0 @@ -/** - -Copyright (C) 2013, Intel Corporation - -Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - -* Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. -* Redistributions in binary form must reproduce the above copyright notice, this - list of conditions and the following disclaimer in the documentation and/or - other materials provided with the distribution. -* Neither the name of Intel Corporation nor the names of its contributors may - be used to endorse or promote products derived from this software without - specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE - LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF - THE POSSIBILITY OF SUCH DAMAGE. - -**/ - - -#ifndef __PI_FIRMWARE_FILE_H__ -#define __PI_FIRMWARE_FILE_H__ - -#pragma pack(1) -/// -/// Used to verify the integrity of the file. -/// -typedef union { - struct { - /// - /// The IntegrityCheck.Checksum.Header field is an 8-bit checksum of the file - /// header. The State and IntegrityCheck.Checksum.File fields are assumed - /// to be zero and the checksum is calculated such that the entire header sums to zero. - /// - UINT8 Header; - /// - /// If the FFS_ATTRIB_CHECKSUM (see definition below) bit of the Attributes - /// field is set to one, the IntegrityCheck.Checksum.File field is an 8-bit - /// checksum of the file data. - /// If the FFS_ATTRIB_CHECKSUM bit of the Attributes field is cleared to zero, - /// the IntegrityCheck.Checksum.File field must be initialized with a value of - /// 0xAA. The IntegrityCheck.Checksum.File field is valid any time the - /// EFI_FILE_DATA_VALID bit is set in the State field. - /// - UINT8 File; - } Checksum; - /// - /// This is the full 16 bits of the IntegrityCheck field. - /// - UINT16 Checksum16; -} EFI_FFS_INTEGRITY_CHECK; - -/// -/// FFS_FIXED_CHECKSUM is the checksum value used when the -/// FFS_ATTRIB_CHECKSUM attribute bit is clear. -/// -#define FFS_FIXED_CHECKSUM 0xAA - -typedef UINT8 EFI_FV_FILETYPE; -typedef UINT8 EFI_FFS_FILE_ATTRIBUTES; -typedef UINT8 EFI_FFS_FILE_STATE; - -/// -/// File Types Definitions -/// -#define EFI_FV_FILETYPE_ALL 0x00 -#define EFI_FV_FILETYPE_RAW 0x01 -#define EFI_FV_FILETYPE_FREEFORM 0x02 -#define EFI_FV_FILETYPE_SECURITY_CORE 0x03 -#define EFI_FV_FILETYPE_PEI_CORE 0x04 -#define EFI_FV_FILETYPE_DXE_CORE 0x05 -#define EFI_FV_FILETYPE_PEIM 0x06 -#define EFI_FV_FILETYPE_DRIVER 0x07 -#define EFI_FV_FILETYPE_COMBINED_PEIM_DRIVER 0x08 -#define EFI_FV_FILETYPE_APPLICATION 0x09 -#define EFI_FV_FILETYPE_SMM 0x0A -#define EFI_FV_FILETYPE_FIRMWARE_VOLUME_IMAGE 0x0B -#define EFI_FV_FILETYPE_COMBINED_SMM_DXE 0x0C -#define EFI_FV_FILETYPE_SMM_CORE 0x0D -#define EFI_FV_FILETYPE_OEM_MIN 0xc0 -#define EFI_FV_FILETYPE_OEM_MAX 0xdf -#define EFI_FV_FILETYPE_DEBUG_MIN 0xe0 -#define EFI_FV_FILETYPE_DEBUG_MAX 0xef -#define EFI_FV_FILETYPE_FFS_MIN 0xf0 -#define EFI_FV_FILETYPE_FFS_MAX 0xff -#define EFI_FV_FILETYPE_FFS_PAD 0xf0 -/// -/// FFS File Attributes. -/// -#define FFS_ATTRIB_LARGE_FILE 0x01 -#define FFS_ATTRIB_FIXED 0x04 -#define FFS_ATTRIB_DATA_ALIGNMENT 0x38 -#define FFS_ATTRIB_CHECKSUM 0x40 - -/// -/// FFS File State Bits. -/// -#define EFI_FILE_HEADER_CONSTRUCTION 0x01 -#define EFI_FILE_HEADER_VALID 0x02 -#define EFI_FILE_DATA_VALID 0x04 -#define EFI_FILE_MARKED_FOR_UPDATE 0x08 -#define EFI_FILE_DELETED 0x10 -#define EFI_FILE_HEADER_INVALID 0x20 - - -/// -/// Each file begins with the header that describe the -/// contents and state of the files. -/// -typedef struct { - /// - /// This GUID is the file name. It is used to uniquely identify the file. - /// - EFI_GUID Name; - /// - /// Used to verify the integrity of the file. - /// - EFI_FFS_INTEGRITY_CHECK IntegrityCheck; - /// - /// Identifies the type of file. - /// - EFI_FV_FILETYPE Type; - /// - /// Declares various file attribute bits. - /// - EFI_FFS_FILE_ATTRIBUTES Attributes; - /// - /// The length of the file in bytes, including the FFS header. - /// - UINT8 Size[3]; - /// - /// Used to track the state of the file throughout the life of the file from creation to deletion. - /// - EFI_FFS_FILE_STATE State; -} EFI_FFS_FILE_HEADER; - -typedef struct { - /// - /// This GUID is the file name. It is used to uniquely identify the file. There may be only - /// one instance of a file with the file name GUID of Name in any given firmware - /// volume, except if the file type is EFI_FV_FILETYPE_FFS_PAD. - /// - EFI_GUID Name; - - /// - /// Used to verify the integrity of the file. - /// - EFI_FFS_INTEGRITY_CHECK IntegrityCheck; - - /// - /// Identifies the type of file. - /// - EFI_FV_FILETYPE Type; - - /// - /// Declares various file attribute bits. - /// - EFI_FFS_FILE_ATTRIBUTES Attributes; - - /// - /// The length of the file in bytes, including the FFS header. - /// The length of the file data is either (Size - sizeof(EFI_FFS_FILE_HEADER)). This calculation means a - /// zero-length file has a Size of 24 bytes, which is sizeof(EFI_FFS_FILE_HEADER). - /// Size is not required to be a multiple of 8 bytes. Given a file F, the next file header is - /// located at the next 8-byte aligned firmware volume offset following the last byte of the file F. - /// - UINT8 Size[3]; - - /// - /// Used to track the state of the file throughout the life of the file from creation to deletion. - /// - EFI_FFS_FILE_STATE State; - - /// - /// If FFS_ATTRIB_LARGE_FILE is set in Attributes, then ExtendedSize exists and Size must be set to zero. - /// If FFS_ATTRIB_LARGE_FILE is not set then EFI_FFS_FILE_HEADER is used. - /// - UINT32 ExtendedSize; -} EFI_FFS_FILE_HEADER2; - -#define IS_FFS_FILE2(FfsFileHeaderPtr) \ - (((((EFI_FFS_FILE_HEADER *) (UINTN) FfsFileHeaderPtr)->Attributes) & FFS_ATTRIB_LARGE_FILE) == FFS_ATTRIB_LARGE_FILE) - -#define FFS_FILE_SIZE(FfsFileHeaderPtr) \ - ((UINT32) (*((UINT32 *) ((EFI_FFS_FILE_HEADER *) (UINTN) FfsFileHeaderPtr)->Size) & 0x00ffffff)) - -#define FFS_FILE2_SIZE(FfsFileHeaderPtr) \ - (((EFI_FFS_FILE_HEADER2 *) (UINTN) FfsFileHeaderPtr)->ExtendedSize) - -typedef UINT8 EFI_SECTION_TYPE; - -/// -/// Pseudo type. It is used as a wild card when retrieving sections. -/// The section type EFI_SECTION_ALL matches all section types. -/// -#define EFI_SECTION_ALL 0x00 - -/// -/// Encapsulation section Type values. -/// -#define EFI_SECTION_COMPRESSION 0x01 - -#define EFI_SECTION_GUID_DEFINED 0x02 - -#define EFI_SECTION_DISPOSABLE 0x03 - -/// -/// Leaf section Type values. -/// -#define EFI_SECTION_PE32 0x10 -#define EFI_SECTION_PIC 0x11 -#define EFI_SECTION_TE 0x12 -#define EFI_SECTION_DXE_DEPEX 0x13 -#define EFI_SECTION_VERSION 0x14 -#define EFI_SECTION_USER_INTERFACE 0x15 -#define EFI_SECTION_COMPATIBILITY16 0x16 -#define EFI_SECTION_FIRMWARE_VOLUME_IMAGE 0x17 -#define EFI_SECTION_FREEFORM_SUBTYPE_GUID 0x18 -#define EFI_SECTION_RAW 0x19 -#define EFI_SECTION_PEI_DEPEX 0x1B -#define EFI_SECTION_SMM_DEPEX 0x1C - -/// -/// Common section header. -/// -typedef struct { - /// - /// A 24-bit unsigned integer that contains the total size of the section in bytes, - /// including the EFI_COMMON_SECTION_HEADER. - /// - UINT8 Size[3]; - EFI_SECTION_TYPE Type; - /// - /// Declares the section type. - /// -} EFI_COMMON_SECTION_HEADER; - -typedef struct { - /// - /// A 24-bit unsigned integer that contains the total size of the section in bytes, - /// including the EFI_COMMON_SECTION_HEADER. - /// - UINT8 Size[3]; - - EFI_SECTION_TYPE Type; - - /// - /// If Size is 0xFFFFFF, then ExtendedSize contains the size of the section. If - /// Size is not equal to 0xFFFFFF, then this field does not exist. - /// - UINT32 ExtendedSize; -} EFI_COMMON_SECTION_HEADER2; - -/// -/// Leaf section type that contains an -/// IA-32 16-bit executable image. -/// -typedef EFI_COMMON_SECTION_HEADER EFI_COMPATIBILITY16_SECTION; -typedef EFI_COMMON_SECTION_HEADER2 EFI_COMPATIBILITY16_SECTION2; - -/// -/// CompressionType of EFI_COMPRESSION_SECTION. -/// -#define EFI_NOT_COMPRESSED 0x00 -#define EFI_STANDARD_COMPRESSION 0x01 -/// -/// An encapsulation section type in which the -/// section data is compressed. -/// -typedef struct { - /// - /// Usual common section header. CommonHeader.Type = EFI_SECTION_COMPRESSION. - /// - EFI_COMMON_SECTION_HEADER CommonHeader; - /// - /// The UINT32 that indicates the size of the section data after decompression. - /// - UINT32 UncompressedLength; - /// - /// Indicates which compression algorithm is used. - /// - UINT8 CompressionType; -} EFI_COMPRESSION_SECTION; - -typedef struct { - /// - /// Usual common section header. CommonHeader.Type = EFI_SECTION_COMPRESSION. - /// - EFI_COMMON_SECTION_HEADER2 CommonHeader; - /// - /// UINT32 that indicates the size of the section data after decompression. - /// - UINT32 UncompressedLength; - /// - /// Indicates which compression algorithm is used. - /// - UINT8 CompressionType; -} EFI_COMPRESSION_SECTION2; - -/// -/// An encapsulation section type in which the section data is disposable. -/// A disposable section is an encapsulation section in which the section data may be disposed of during -/// the process of creating or updating a firmware image without significant impact on the usefulness of -/// the file. The Type field in the section header is set to EFI_SECTION_DISPOSABLE. This -/// allows optional or descriptive data to be included with the firmware file which can be removed in -/// order to conserve space. The contents of this section are implementation specific, but might contain -/// debug data or detailed integration instructions. -/// -typedef EFI_COMMON_SECTION_HEADER EFI_DISPOSABLE_SECTION; -typedef EFI_COMMON_SECTION_HEADER2 EFI_DISPOSABLE_SECTION2; - -/// -/// The leaf section which could be used to determine the dispatch order of DXEs. -/// -typedef EFI_COMMON_SECTION_HEADER EFI_DXE_DEPEX_SECTION; -typedef EFI_COMMON_SECTION_HEADER2 EFI_DXE_DEPEX_SECTION2; - -/// -/// The leaf section which contains a PI FV. -/// -typedef EFI_COMMON_SECTION_HEADER EFI_FIRMWARE_VOLUME_IMAGE_SECTION; -typedef EFI_COMMON_SECTION_HEADER2 EFI_FIRMWARE_VOLUME_IMAGE_SECTION2; - -/// -/// The leaf section which contains a single GUID. -/// -typedef struct { - /// - /// Common section header. CommonHeader.Type = EFI_SECTION_FREEFORM_SUBTYPE_GUID. - /// - EFI_COMMON_SECTION_HEADER CommonHeader; - /// - /// This GUID is defined by the creator of the file. It is a vendor-defined file type. - /// - EFI_GUID SubTypeGuid; -} EFI_FREEFORM_SUBTYPE_GUID_SECTION; - -typedef struct { - /// - /// The common section header. CommonHeader.Type = EFI_SECTION_FREEFORM_SUBTYPE_GUID. - /// - EFI_COMMON_SECTION_HEADER2 CommonHeader; - /// - /// This GUID is defined by the creator of the file. It is a vendor-defined file type. - /// - EFI_GUID SubTypeGuid; -} EFI_FREEFORM_SUBTYPE_GUID_SECTION2; - -/// -/// Attributes of EFI_GUID_DEFINED_SECTION. -/// -#define EFI_GUIDED_SECTION_PROCESSING_REQUIRED 0x01 -#define EFI_GUIDED_SECTION_AUTH_STATUS_VALID 0x02 -/// -/// The leaf section which is encapsulation defined by specific GUID. -/// -typedef struct { - /// - /// The common section header. CommonHeader.Type = EFI_SECTION_GUID_DEFINED. - /// - EFI_COMMON_SECTION_HEADER CommonHeader; - /// - /// The GUID that defines the format of the data that follows. It is a vendor-defined section type. - /// - EFI_GUID SectionDefinitionGuid; - /// - /// Contains the offset in bytes from the beginning of the common header to the first byte of the data. - /// - UINT16 DataOffset; - /// - /// The bit field that declares some specific characteristics of the section contents. - /// - UINT16 Attributes; -} EFI_GUID_DEFINED_SECTION; - -typedef struct { - /// - /// The common section header. CommonHeader.Type = EFI_SECTION_GUID_DEFINED. - /// - EFI_COMMON_SECTION_HEADER2 CommonHeader; - /// - /// The GUID that defines the format of the data that follows. It is a vendor-defined section type. - /// - EFI_GUID SectionDefinitionGuid; - /// - /// Contains the offset in bytes from the beginning of the common header to the first byte of the data. - /// - UINT16 DataOffset; - /// - /// The bit field that declares some specific characteristics of the section contents. - /// - UINT16 Attributes; -} EFI_GUID_DEFINED_SECTION2; - -/// -/// The leaf section which contains PE32+ image. -/// -typedef EFI_COMMON_SECTION_HEADER EFI_PE32_SECTION; -typedef EFI_COMMON_SECTION_HEADER2 EFI_PE32_SECTION2; - -/// -/// The leaf section used to determine the dispatch order of PEIMs. -/// -typedef EFI_COMMON_SECTION_HEADER EFI_PEI_DEPEX_SECTION; -typedef EFI_COMMON_SECTION_HEADER2 EFI_PEI_DEPEX_SECTION2; - -/// -/// A leaf section type that contains a position-independent-code (PIC) image. -/// A PIC image section is a leaf section that contains a position-independent-code (PIC) image. -/// In addition to normal PE32+ images that contain relocation information, PEIM executables may be -/// PIC and are referred to as PIC images. A PIC image is the same as a PE32+ image except that all -/// relocation information has been stripped from the image and the image can be moved and will -/// execute correctly without performing any relocation or other fix-ups. EFI_PIC_SECTION2 must -/// be used if the section is 16MB or larger. -/// -typedef EFI_COMMON_SECTION_HEADER EFI_PIC_SECTION; -typedef EFI_COMMON_SECTION_HEADER2 EFI_PIC_SECTION2; - -/// -/// The leaf section which constains the position-independent-code image. -/// -typedef EFI_COMMON_SECTION_HEADER EFI_TE_SECTION; -typedef EFI_COMMON_SECTION_HEADER2 EFI_TE_SECTION2; - -/// -/// The leaf section which contains an array of zero or more bytes. -/// -typedef EFI_COMMON_SECTION_HEADER EFI_RAW_SECTION; -typedef EFI_COMMON_SECTION_HEADER2 EFI_RAW_SECTION2; - -/// -/// The SMM dependency expression section is a leaf section that contains a dependency expression that -/// is used to determine the dispatch order for SMM drivers. Before the SMRAM invocation of the -/// SMM driver's entry point, this dependency expression must evaluate to TRUE. See the Platform -/// Initialization Specification, Volume 2, for details regarding the format of the dependency expression. -/// The dependency expression may refer to protocols installed in either the UEFI or the SMM protocol -/// database. EFI_SMM_DEPEX_SECTION2 must be used if the section is 16MB or larger. -/// -typedef EFI_COMMON_SECTION_HEADER EFI_SMM_DEPEX_SECTION; -typedef EFI_COMMON_SECTION_HEADER2 EFI_SMM_DEPEX_SECTION2; - -/// -/// The leaf section which contains a unicode string that -/// is human readable file name. -/// -typedef struct { - EFI_COMMON_SECTION_HEADER CommonHeader; - - /// - /// Array of unicode string. - /// - CHAR16 FileNameString[1]; -} EFI_USER_INTERFACE_SECTION; - -typedef struct { - EFI_COMMON_SECTION_HEADER2 CommonHeader; - CHAR16 FileNameString[1]; -} EFI_USER_INTERFACE_SECTION2; - -/// -/// The leaf section which contains a numeric build number and -/// an optional unicode string that represents the file revision. -/// -typedef struct { - EFI_COMMON_SECTION_HEADER CommonHeader; - UINT16 BuildNumber; - - /// - /// Array of unicode string. - /// - CHAR16 VersionString[1]; -} EFI_VERSION_SECTION; - -typedef struct { - EFI_COMMON_SECTION_HEADER2 CommonHeader; - /// - /// A UINT16 that represents a particular build. Subsequent builds have monotonically - /// increasing build numbers relative to earlier builds. - /// - UINT16 BuildNumber; - CHAR16 VersionString[1]; -} EFI_VERSION_SECTION2; - -#define IS_SECTION2(SectionHeaderPtr) \ - ((UINT32) (*((UINT32 *) ((EFI_COMMON_SECTION_HEADER *) (UINTN) SectionHeaderPtr)->Size) & 0x00ffffff) == 0x00ffffff) - -#define SECTION_SIZE(SectionHeaderPtr) \ - ((UINT32) (*((UINT32 *) ((EFI_COMMON_SECTION_HEADER *) (UINTN) SectionHeaderPtr)->Size) & 0x00ffffff)) - -#define SECTION2_SIZE(SectionHeaderPtr) \ - (((EFI_COMMON_SECTION_HEADER2 *) (UINTN) SectionHeaderPtr)->ExtendedSize) - -#pragma pack() - -#endif diff --git a/src/vendorcode/intel/fsp1_0/baytrail/include/fspfv.h b/src/vendorcode/intel/fsp1_0/baytrail/include/fspfv.h deleted file mode 100644 index 26c00f266a..0000000000 --- a/src/vendorcode/intel/fsp1_0/baytrail/include/fspfv.h +++ /dev/null @@ -1,247 +0,0 @@ -/** - -Copyright (C) 2013, Intel Corporation - -Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - -* Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. -* Redistributions in binary form must reproduce the above copyright notice, this - list of conditions and the following disclaimer in the documentation and/or - other materials provided with the distribution. -* Neither the name of Intel Corporation nor the names of its contributors may - be used to endorse or promote products derived from this software without - specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE - LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF - THE POSSIBILITY OF SUCH DAMAGE. - -**/ - -#ifndef __PI_FIRMWAREVOLUME_H__ -#define __PI_FIRMWAREVOLUME_H__ - -/// -/// EFI_FV_FILE_ATTRIBUTES -/// -typedef UINT32 EFI_FV_FILE_ATTRIBUTES; - -// -// Value of EFI_FV_FILE_ATTRIBUTES. -// -#define EFI_FV_FILE_ATTRIB_ALIGNMENT 0x0000001F -#define EFI_FV_FILE_ATTRIB_FIXED 0x00000100 -#define EFI_FV_FILE_ATTRIB_MEMORY_MAPPED 0x00000200 - -/// -/// type of EFI FVB attribute -/// -typedef UINT32 EFI_FVB_ATTRIBUTES_2; - -// -// Attributes bit definitions -// -#define EFI_FVB2_READ_DISABLED_CAP 0x00000001 -#define EFI_FVB2_READ_ENABLED_CAP 0x00000002 -#define EFI_FVB2_READ_STATUS 0x00000004 -#define EFI_FVB2_WRITE_DISABLED_CAP 0x00000008 -#define EFI_FVB2_WRITE_ENABLED_CAP 0x00000010 -#define EFI_FVB2_WRITE_STATUS 0x00000020 -#define EFI_FVB2_LOCK_CAP 0x00000040 -#define EFI_FVB2_LOCK_STATUS 0x00000080 -#define EFI_FVB2_STICKY_WRITE 0x00000200 -#define EFI_FVB2_MEMORY_MAPPED 0x00000400 -#define EFI_FVB2_ERASE_POLARITY 0x00000800 -#define EFI_FVB2_READ_LOCK_CAP 0x00001000 -#define EFI_FVB2_READ_LOCK_STATUS 0x00002000 -#define EFI_FVB2_WRITE_LOCK_CAP 0x00004000 -#define EFI_FVB2_WRITE_LOCK_STATUS 0x00008000 -#define EFI_FVB2_ALIGNMENT 0x001F0000 -#define EFI_FVB2_ALIGNMENT_1 0x00000000 -#define EFI_FVB2_ALIGNMENT_2 0x00010000 -#define EFI_FVB2_ALIGNMENT_4 0x00020000 -#define EFI_FVB2_ALIGNMENT_8 0x00030000 -#define EFI_FVB2_ALIGNMENT_16 0x00040000 -#define EFI_FVB2_ALIGNMENT_32 0x00050000 -#define EFI_FVB2_ALIGNMENT_64 0x00060000 -#define EFI_FVB2_ALIGNMENT_128 0x00070000 -#define EFI_FVB2_ALIGNMENT_256 0x00080000 -#define EFI_FVB2_ALIGNMENT_512 0x00090000 -#define EFI_FVB2_ALIGNMENT_1K 0x000A0000 -#define EFI_FVB2_ALIGNMENT_2K 0x000B0000 -#define EFI_FVB2_ALIGNMENT_4K 0x000C0000 -#define EFI_FVB2_ALIGNMENT_8K 0x000D0000 -#define EFI_FVB2_ALIGNMENT_16K 0x000E0000 -#define EFI_FVB2_ALIGNMENT_32K 0x000F0000 -#define EFI_FVB2_ALIGNMENT_64K 0x00100000 -#define EFI_FVB2_ALIGNMENT_128K 0x00110000 -#define EFI_FVB2_ALIGNMENT_256K 0x00120000 -#define EFI_FVB2_ALIGNMENT_512K 0x00130000 -#define EFI_FVB2_ALIGNMENT_1M 0x00140000 -#define EFI_FVB2_ALIGNMENT_2M 0x00150000 -#define EFI_FVB2_ALIGNMENT_4M 0x00160000 -#define EFI_FVB2_ALIGNMENT_8M 0x00170000 -#define EFI_FVB2_ALIGNMENT_16M 0x00180000 -#define EFI_FVB2_ALIGNMENT_32M 0x00190000 -#define EFI_FVB2_ALIGNMENT_64M 0x001A0000 -#define EFI_FVB2_ALIGNMENT_128M 0x001B0000 -#define EFI_FVB2_ALIGNMENT_256M 0x001C0000 -#define EFI_FVB2_ALIGNMENT_512M 0x001D0000 -#define EFI_FVB2_ALIGNMENT_1G 0x001E0000 -#define EFI_FVB2_ALIGNMENT_2G 0x001F0000 - - -typedef struct { - /// - /// The number of sequential blocks which are of the same size. - /// - UINT32 NumBlocks; - /// - /// The size of the blocks. - /// - UINT32 Length; -} EFI_FV_BLOCK_MAP_ENTRY; - -/// -/// Describes the features and layout of the firmware volume. -/// -typedef struct { - /// - /// The first 16 bytes are reserved to allow for the reset vector of - /// processors whose reset vector is at address 0. - /// - UINT8 ZeroVector[16]; - /// - /// Declares the file system with which the firmware volume is formatted. - /// - EFI_GUID FileSystemGuid; - /// - /// Length in bytes of the complete firmware volume, including the header. - /// - UINT64 FvLength; - /// - /// Set to EFI_FVH_SIGNATURE - /// - UINT32 Signature; - /// - /// Declares capabilities and power-on defaults for the firmware volume. - /// - EFI_FVB_ATTRIBUTES_2 Attributes; - /// - /// Length in bytes of the complete firmware volume header. - /// - UINT16 HeaderLength; - /// - /// A 16-bit checksum of the firmware volume header. A valid header sums to zero. - /// - UINT16 Checksum; - /// - /// Offset, relative to the start of the header, of the extended header - /// (EFI_FIRMWARE_VOLUME_EXT_HEADER) or zero if there is no extended header. - /// - UINT16 ExtHeaderOffset; - /// - /// This field must always be set to zero. - /// - UINT8 Reserved[1]; - /// - /// Set to 2. Future versions of this specification may define new header fields and will - /// increment the Revision field accordingly. - /// - UINT8 Revision; - /// - /// An array of run-length encoded FvBlockMapEntry structures. The array is - /// terminated with an entry of {0,0}. - /// - EFI_FV_BLOCK_MAP_ENTRY BlockMap[1]; -} EFI_FIRMWARE_VOLUME_HEADER; - -#define EFI_FVH_SIGNATURE SIGNATURE_32 ('_', 'F', 'V', 'H') - -/// -/// Firmware Volume Header Revision definition -/// -#define EFI_FVH_REVISION 0x02 - -/// -/// Extension header pointed by ExtHeaderOffset of volume header. -/// -typedef struct { - /// - /// Firmware volume name. - /// - EFI_GUID FvName; - /// - /// Size of the rest of the extension header, including this structure. - /// - UINT32 ExtHeaderSize; -} EFI_FIRMWARE_VOLUME_EXT_HEADER; - -/// -/// Entry struture for describing FV extension header -/// -typedef struct { - /// - /// Size of this header extension. - /// - UINT16 ExtEntrySize; - /// - /// Type of the header. - /// - UINT16 ExtEntryType; -} EFI_FIRMWARE_VOLUME_EXT_ENTRY; - -#define EFI_FV_EXT_TYPE_OEM_TYPE 0x01 -/// -/// This extension header provides a mapping between a GUID and an OEM file type. -/// -typedef struct { - /// - /// Standard extension entry, with the type EFI_FV_EXT_TYPE_OEM_TYPE. - /// - EFI_FIRMWARE_VOLUME_EXT_ENTRY Hdr; - /// - /// A bit mask, one bit for each file type between 0xC0 (bit 0) and 0xDF (bit 31). If a bit - /// is '1', then the GUID entry exists in Types. If a bit is '0' then no GUID entry exists in Types. - /// - UINT32 TypeMask; - /// - /// An array of GUIDs, each GUID representing an OEM file type. - /// - /// EFI_GUID Types[1]; - /// -} EFI_FIRMWARE_VOLUME_EXT_ENTRY_OEM_TYPE; - -#define EFI_FV_EXT_TYPE_GUID_TYPE 0x0002 - -/// -/// This extension header EFI_FIRMWARE_VOLUME_EXT_ENTRY_GUID_TYPE provides a vendor specific -/// GUID FormatType type which includes a length and a successive series of data bytes. -/// -typedef struct { - /// - /// Standard extension entry, with the type EFI_FV_EXT_TYPE_OEM_TYPE. - /// - EFI_FIRMWARE_VOLUME_EXT_ENTRY Hdr; - /// - /// Vendor-specific GUID. - /// - EFI_GUID FormatType; - /// - /// An arry of bytes of length Length. - /// - /// UINT8 Data[1]; - /// -} EFI_FIRMWARE_VOLUME_EXT_ENTRY_GUID_TYPE; - -#endif diff --git a/src/vendorcode/intel/fsp1_0/baytrail/include/fsphob.h b/src/vendorcode/intel/fsp1_0/baytrail/include/fsphob.h deleted file mode 100644 index 04e2123b9b..0000000000 --- a/src/vendorcode/intel/fsp1_0/baytrail/include/fsphob.h +++ /dev/null @@ -1,542 +0,0 @@ -/** - -Copyright (C) 2013, Intel Corporation - -Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - -* Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. -* Redistributions in binary form must reproduce the above copyright notice, this - list of conditions and the following disclaimer in the documentation and/or - other materials provided with the distribution. -* Neither the name of Intel Corporation nor the names of its contributors may - be used to endorse or promote products derived from this software without - specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE - LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF - THE POSSIBILITY OF SUCH DAMAGE. - -**/ - -#ifndef __PI_HOB_H__ -#define __PI_HOB_H__ - -// -// HobType of EFI_HOB_GENERIC_HEADER. -// -#define EFI_HOB_TYPE_MEMORY_ALLOCATION 0x0002 -#define EFI_HOB_TYPE_RESOURCE_DESCRIPTOR 0x0003 -#define EFI_HOB_TYPE_GUID_EXTENSION 0x0004 -#define EFI_HOB_TYPE_UNUSED 0xFFFE -#define EFI_HOB_TYPE_END_OF_HOB_LIST 0xFFFF - -/// -/// Describes the format and size of the data inside the HOB. -/// All HOBs must contain this generic HOB header. -/// -typedef struct { - /// - /// Identifies the HOB data structure type. - /// - UINT16 HobType; - /// - /// The length in bytes of the HOB. - /// - UINT16 HobLength; - /// - /// This field must always be set to zero. - /// - UINT32 Reserved; -} EFI_HOB_GENERIC_HEADER; - -/// -/// Enumeration of memory types introduced in UEFI. -/// -typedef enum { - /// - /// Not used. - /// - EfiReservedMemoryType, - /// - /// The code portions of a loaded application. - /// (Note that UEFI OS loaders are UEFI applications.) - /// - EfiLoaderCode, - /// - /// The data portions of a loaded application and the default data allocation - /// type used by an application to allocate pool memory. - /// - EfiLoaderData, - /// - /// The code portions of a loaded Boot Services Driver. - /// - EfiBootServicesCode, - /// - /// The data portions of a loaded Boot Serves Driver, and the default data - /// allocation type used by a Boot Services Driver to allocate pool memory. - /// - EfiBootServicesData, - /// - /// The code portions of a loaded Runtime Services Driver. - /// - EfiRuntimeServicesCode, - /// - /// The data portions of a loaded Runtime Services Driver and the default - /// data allocation type used by a Runtime Services Driver to allocate pool memory. - /// - EfiRuntimeServicesData, - /// - /// Free (unallocated) memory. - /// - EfiConventionalMemory, - /// - /// Memory in which errors have been detected. - /// - EfiUnusableMemory, - /// - /// Memory that holds the ACPI tables. - /// - EfiACPIReclaimMemory, - /// - /// Address space reserved for use by the firmware. - /// - EfiACPIMemoryNVS, - /// - /// Used by system firmware to request that a memory-mapped IO region - /// be mapped by the OS to a virtual address so it can be accessed by EFI runtime services. - /// - EfiMemoryMappedIO, - /// - /// System memory-mapped IO region that is used to translate memory - /// cycles to IO cycles by the processor. - /// - EfiMemoryMappedIOPortSpace, - /// - /// Address space reserved by the firmware for code that is part of the processor. - /// - EfiPalCode, - EfiMaxMemoryType -} EFI_MEMORY_TYPE; - -/// -/// EFI_HOB_MEMORY_ALLOCATION_HEADER describes the -/// various attributes of the logical memory allocation. The type field will be used for -/// subsequent inclusion in the UEFI memory map. -/// -typedef struct { - /// - /// A GUID that defines the memory allocation region's type and purpose, as well as - /// other fields within the memory allocation HOB. This GUID is used to define the - /// additional data within the HOB that may be present for the memory allocation HOB. - /// Type EFI_GUID is defined in InstallProtocolInterface() in the UEFI 2.0 - /// specification. - /// - EFI_GUID Name; - - /// - /// The base address of memory allocated by this HOB. Type - /// EFI_PHYSICAL_ADDRESS is defined in AllocatePages() in the UEFI 2.0 - /// specification. - /// - EFI_PHYSICAL_ADDRESS MemoryBaseAddress; - - /// - /// The length in bytes of memory allocated by this HOB. - /// - UINT64 MemoryLength; - - /// - /// Defines the type of memory allocated by this HOB. The memory type definition - /// follows the EFI_MEMORY_TYPE definition. Type EFI_MEMORY_TYPE is defined - /// in AllocatePages() in the UEFI 2.0 specification. - /// - EFI_MEMORY_TYPE MemoryType; - - /// - /// Padding for Itanium processor family - /// - UINT8 Reserved[4]; -} EFI_HOB_MEMORY_ALLOCATION_HEADER; - -/// -/// Describes all memory ranges used during the HOB producer -/// phase that exist outside the HOB list. This HOB type -/// describes how memory is used, not the physical attributes of memory. -/// -typedef struct { - /// - /// The HOB generic header. Header.HobType = EFI_HOB_TYPE_MEMORY_ALLOCATION. - /// - EFI_HOB_GENERIC_HEADER Header; - /// - /// An instance of the EFI_HOB_MEMORY_ALLOCATION_HEADER that describes the - /// various attributes of the logical memory allocation. - /// - EFI_HOB_MEMORY_ALLOCATION_HEADER AllocDescriptor; - // - // Additional data pertaining to the "Name" Guid memory - // may go here. - // -} EFI_HOB_MEMORY_ALLOCATION; - -/// -/// The resource type. -/// -typedef UINT32 EFI_RESOURCE_TYPE; - -// -// Value of ResourceType in EFI_HOB_RESOURCE_DESCRIPTOR. -// -#define EFI_RESOURCE_SYSTEM_MEMORY 0x00000000 -#define EFI_RESOURCE_MEMORY_MAPPED_IO 0x00000001 -#define EFI_RESOURCE_IO 0x00000002 -#define EFI_RESOURCE_FIRMWARE_DEVICE 0x00000003 -#define EFI_RESOURCE_MEMORY_MAPPED_IO_PORT 0x00000004 -#define EFI_RESOURCE_MEMORY_RESERVED 0x00000005 -#define EFI_RESOURCE_IO_RESERVED 0x00000006 -#define EFI_RESOURCE_MAX_MEMORY_TYPE 0x00000007 - -/// -/// A type of recount attribute type. -/// -typedef UINT32 EFI_RESOURCE_ATTRIBUTE_TYPE; - -// -// These types can be ORed together as needed. -// -// The first three enumerations describe settings -// -#define EFI_RESOURCE_ATTRIBUTE_PRESENT 0x00000001 -#define EFI_RESOURCE_ATTRIBUTE_INITIALIZED 0x00000002 -#define EFI_RESOURCE_ATTRIBUTE_TESTED 0x00000004 -// -// The rest of the settings describe capabilities -// -#define EFI_RESOURCE_ATTRIBUTE_SINGLE_BIT_ECC 0x00000008 -#define EFI_RESOURCE_ATTRIBUTE_MULTIPLE_BIT_ECC 0x00000010 -#define EFI_RESOURCE_ATTRIBUTE_ECC_RESERVED_1 0x00000020 -#define EFI_RESOURCE_ATTRIBUTE_ECC_RESERVED_2 0x00000040 -#define EFI_RESOURCE_ATTRIBUTE_READ_PROTECTED 0x00000080 -#define EFI_RESOURCE_ATTRIBUTE_WRITE_PROTECTED 0x00000100 -#define EFI_RESOURCE_ATTRIBUTE_EXECUTION_PROTECTED 0x00000200 -#define EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE 0x00000400 -#define EFI_RESOURCE_ATTRIBUTE_WRITE_COMBINEABLE 0x00000800 -#define EFI_RESOURCE_ATTRIBUTE_WRITE_THROUGH_CACHEABLE 0x00001000 -#define EFI_RESOURCE_ATTRIBUTE_WRITE_BACK_CACHEABLE 0x00002000 -#define EFI_RESOURCE_ATTRIBUTE_16_BIT_IO 0x00004000 -#define EFI_RESOURCE_ATTRIBUTE_32_BIT_IO 0x00008000 -#define EFI_RESOURCE_ATTRIBUTE_64_BIT_IO 0x00010000 -#define EFI_RESOURCE_ATTRIBUTE_UNCACHED_EXPORTED 0x00020000 - -/// -/// Describes the resource properties of all fixed, -/// nonrelocatable resource ranges found on the processor -/// host bus during the HOB producer phase. -/// -typedef struct { - /// - /// The HOB generic header. Header.HobType = EFI_HOB_TYPE_RESOURCE_DESCRIPTOR. - /// - EFI_HOB_GENERIC_HEADER Header; - /// - /// A GUID representing the owner of the resource. This GUID is used by HOB - /// consumer phase components to correlate device ownership of a resource. - /// - EFI_GUID Owner; - /// - /// The resource type enumeration as defined by EFI_RESOURCE_TYPE. - /// - EFI_RESOURCE_TYPE ResourceType; - /// - /// Resource attributes as defined by EFI_RESOURCE_ATTRIBUTE_TYPE. - /// - EFI_RESOURCE_ATTRIBUTE_TYPE ResourceAttribute; - /// - /// The physical start address of the resource region. - /// - EFI_PHYSICAL_ADDRESS PhysicalStart; - /// - /// The number of bytes of the resource region. - /// - UINT64 ResourceLength; -} EFI_HOB_RESOURCE_DESCRIPTOR; - -/// -/// Allows writers of executable content in the HOB producer phase to -/// maintain and manage HOBs with specific GUID. -/// -typedef struct { - /// - /// The HOB generic header. Header.HobType = EFI_HOB_TYPE_GUID_EXTENSION. - /// - EFI_HOB_GENERIC_HEADER Header; - /// - /// A GUID that defines the contents of this HOB. - /// - EFI_GUID Name; - // - // Guid specific data goes here - // -} EFI_HOB_GUID_TYPE; - -/// -/// Union of all the possible HOB Types. -/// -typedef union { - EFI_HOB_GENERIC_HEADER *Header; - EFI_HOB_MEMORY_ALLOCATION *MemoryAllocation; - EFI_HOB_RESOURCE_DESCRIPTOR *ResourceDescriptor; - EFI_HOB_GUID_TYPE *Guid; - UINT8 *Raw; -} EFI_PEI_HOB_POINTERS; - - -/** - Returns the type of a HOB. - - This macro returns the HobType field from the HOB header for the - HOB specified by HobStart. - - @param HobStart A pointer to a HOB. - - @return HobType. - -**/ -#define GET_HOB_TYPE(HobStart) \ - (((EFI_HOB_GENERIC_HEADER *)(HobStart))->HobType) - -/** - Returns the length, in bytes, of a HOB. - - This macro returns the HobLength field from the HOB header for the - HOB specified by HobStart. - - @param HobStart A pointer to a HOB. - - @return HobLength. - -**/ -#define GET_HOB_LENGTH(HobStart) \ - (((EFI_HOB_GENERIC_HEADER *)(HobStart))->HobLength) - -/** - Returns a pointer to the next HOB in the HOB list. - - This macro returns a pointer to HOB that follows the - HOB specified by HobStart in the HOB List. - - @param HobStart A pointer to a HOB. - - @return A pointer to the next HOB in the HOB list. - -**/ -#define GET_NEXT_HOB(HobStart) \ - (VOID *)((UINT8 *)(HobStart) + GET_HOB_LENGTH(HobStart)) - -/** - Determines if a HOB is the last HOB in the HOB list. - - This macro determine if the HOB specified by HobStart is the - last HOB in the HOB list. If HobStart is last HOB in the HOB list, - then TRUE is returned. Otherwise, FALSE is returned. - - @param HobStart A pointer to a HOB. - - @retval TRUE The HOB specified by HobStart is the last HOB in the HOB list. - @retval FALSE The HOB specified by HobStart is not the last HOB in the HOB list. - -**/ -#define END_OF_HOB_LIST(HobStart) (GET_HOB_TYPE(HobStart) == (UINT16)EFI_HOB_TYPE_END_OF_HOB_LIST) - -/** - Returns a pointer to data buffer from a HOB of type EFI_HOB_TYPE_GUID_EXTENSION. - - This macro returns a pointer to the data buffer in a HOB specified by HobStart. - HobStart is assumed to be a HOB of type EFI_HOB_TYPE_GUID_EXTENSION. - - @param GuidHob A pointer to a HOB. - - @return A pointer to the data buffer in a HOB. - -**/ -#define GET_GUID_HOB_DATA(HobStart) \ - (VOID *)((UINT8 *)(HobStart) + sizeof(EFI_HOB_GUID_TYPE)) - -/** - Returns the size of the data buffer from a HOB of type EFI_HOB_TYPE_GUID_EXTENSION. - - This macro returns the size, in bytes, of the data buffer in a HOB specified by HobStart. - HobStart is assumed to be a HOB of type EFI_HOB_TYPE_GUID_EXTENSION. - - @param GuidHob A pointer to a HOB. - - @return The size of the data buffer. -**/ -#define GET_GUID_HOB_DATA_SIZE(HobStart) \ - (UINT16)(GET_HOB_LENGTH(HobStart) - sizeof(EFI_HOB_GUID_TYPE)) - -/** - Returns the pointer to the HOB list. - - This function returns the pointer to first HOB in the list. - - If the pointer to the HOB list is NULL, then ASSERT(). - - @return The pointer to the HOB list. - -**/ -VOID * -EFIAPI -GetHobList ( - VOID - ); - -/** - Returns the next instance of a HOB type from the starting HOB. - - This function searches the first instance of a HOB type from the starting HOB pointer. - If there does not exist such HOB type from the starting HOB pointer, it will return NULL. - In contrast with macro GET_NEXT_HOB(), this function does not skip the starting HOB pointer - unconditionally: it returns HobStart back if HobStart itself meets the requirement; - caller is required to use GET_NEXT_HOB() if it wishes to skip current HobStart. - - If HobStart is NULL, then ASSERT(). - - @param Type The HOB type to return. - @param HobStart The starting HOB pointer to search from. - - @return The next instance of a HOB type from the starting HOB. - -**/ -VOID * -EFIAPI -GetNextHob ( - UINT16 Type, - CONST VOID *HobStart - ); - -/** - Returns the first instance of a HOB type among the whole HOB list. - - This function searches the first instance of a HOB type among the whole HOB list. - If there does not exist such HOB type in the HOB list, it will return NULL. - - If the pointer to the HOB list is NULL, then ASSERT(). - - @param Type The HOB type to return. - - @return The next instance of a HOB type from the starting HOB. - -**/ -VOID * -EFIAPI -GetFirstHob ( - UINT16 Type - ); - -/** - Returns the next instance of the matched GUID HOB from the starting HOB. - - This function searches the first instance of a HOB from the starting HOB pointer. - Such HOB should satisfy two conditions: - its HOB type is EFI_HOB_TYPE_GUID_EXTENSION and its GUID Name equals to the input Guid. - If there does not exist such HOB from the starting HOB pointer, it will return NULL. - Caller is required to apply GET_GUID_HOB_DATA () and GET_GUID_HOB_DATA_SIZE () - to extract the data section and its size info respectively. - In contrast with macro GET_NEXT_HOB(), this function does not skip the starting HOB pointer - unconditionally: it returns HobStart back if HobStart itself meets the requirement; - caller is required to use GET_NEXT_HOB() if it wishes to skip current HobStart. - - If Guid is NULL, then ASSERT(). - If HobStart is NULL, then ASSERT(). - - @param Guid The GUID to match with in the HOB list. - @param HobStart A pointer to a Guid. - - @return The next instance of the matched GUID HOB from the starting HOB. - -**/ -VOID * -EFIAPI -GetNextGuidHob ( - CONST EFI_GUID *Guid, - CONST VOID *HobStart - ); - -/** - Returns the first instance of the matched GUID HOB among the whole HOB list. - - This function searches the first instance of a HOB among the whole HOB list. - Such HOB should satisfy two conditions: - its HOB type is EFI_HOB_TYPE_GUID_EXTENSION and its GUID Name equals to the input Guid. - If there does not exist such HOB from the starting HOB pointer, it will return NULL. - Caller is required to apply GET_GUID_HOB_DATA () and GET_GUID_HOB_DATA_SIZE () - to extract the data section and its size info respectively. - - If the pointer to the HOB list is NULL, then ASSERT(). - If Guid is NULL, then ASSERT(). - - @param Guid The GUID to match with in the HOB list. - - @return The first instance of the matched GUID HOB among the whole HOB list. - -**/ -VOID * -EFIAPI -GetFirstGuidHob ( - CONST EFI_GUID *Guid - ); - -/** - Compares two GUIDs. - - This function compares Guid1 to Guid2. If the GUIDs are identical then TRUE is returned. - If there are any bit differences in the two GUIDs, then FALSE is returned. - - If Guid1 is NULL, then ASSERT(). - If Guid2 is NULL, then ASSERT(). - - @param Guid1 A pointer to a 128 bit GUID. - @param Guid2 A pointer to a 128 bit GUID. - - @retval TRUE Guid1 and Guid2 are identical. - @retval FALSE Guid1 and Guid2 are not identical. - -**/ -BOOLEAN -EFIAPI -CompareGuid ( - CONST EFI_GUID *Guid1, - CONST EFI_GUID *Guid2 - ); - -/** - Reads a 64-bit value from memory that may be unaligned. - - This function returns the 64-bit value pointed to by Buffer. The function - guarantees that the read operation does not produce an alignment fault. - - If the Buffer is NULL, then ASSERT(). - - @param Buffer Pointer to a 64-bit value that may be unaligned. - - @return The 64-bit value read from Buffer. - -**/ -UINT64 -EFIAPI -ReadUnaligned64 ( - CONST UINT64 *Buffer - ); - -#endif diff --git a/src/vendorcode/intel/fsp1_0/baytrail/include/fspinfoheader.h b/src/vendorcode/intel/fsp1_0/baytrail/include/fspinfoheader.h deleted file mode 100644 index b277bcd5f7..0000000000 --- a/src/vendorcode/intel/fsp1_0/baytrail/include/fspinfoheader.h +++ /dev/null @@ -1,62 +0,0 @@ -/** - -Copyright (C) 2013, Intel Corporation - -Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - -* Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. -* Redistributions in binary form must reproduce the above copyright notice, this - list of conditions and the following disclaimer in the documentation and/or - other materials provided with the distribution. -* Neither the name of Intel Corporation nor the names of its contributors may - be used to endorse or promote products derived from this software without - specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE - LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF - THE POSSIBILITY OF SUCH DAMAGE. - -**/ - -#ifndef _FSP_INFO_HEADER_H_ -#define _FSP_INFO_HEADER_H_ - -#pragma pack(1) - -typedef struct { - - UINT32 Signature; // Off 0x94 - UINT32 HeaderLength; - UINT8 Reserved1[3]; - UINT8 HeaderRevision; - UINT32 ImageRevision; - - CHAR8 ImageId[8]; // Off 0xA4 - UINT32 ImageSize; - UINT32 ImageBase; - - UINT32 ImageAttribute; // Off 0xB4 - UINT32 CfgRegionOffset; - UINT32 CfgRegionSize; - UINT32 ApiEntryNum; - - UINT32 NemInitEntry; // Off 0xC4 - UINT32 FspInitEntry; - UINT32 NotifyPhaseEntry; - UINT32 Reserved2; - -} FSP_INFO_HEADER; - -#pragma pack() - -#endif diff --git a/src/vendorcode/intel/fsp1_0/baytrail/include/fspplatform.h b/src/vendorcode/intel/fsp1_0/baytrail/include/fspplatform.h deleted file mode 100644 index 81f7b66a4a..0000000000 --- a/src/vendorcode/intel/fsp1_0/baytrail/include/fspplatform.h +++ /dev/null @@ -1,78 +0,0 @@ -/** - -Copyright (C) 2013, Intel Corporation - -Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - -* Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. -* Redistributions in binary form must reproduce the above copyright notice, this - list of conditions and the following disclaimer in the documentation and/or - other materials provided with the distribution. -* Neither the name of Intel Corporation nor the names of its contributors may - be used to endorse or promote products derived from this software without - specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE - LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF - THE POSSIBILITY OF SUCH DAMAGE. - -**/ - -#ifndef _FSP_PLATFORM_H_ -#define _FSP_PLATFORM_H_ - -#include "fsptypes.h" -#include "fspapi.h" -#include "azalia.h" - -#pragma pack(1) - -typedef struct { - FSP_INIT_RT_COMMON_BUFFER Common; -} FSP_INIT_RT_BUFFER; - -#pragma pack() - -// -// Function prototypes for board_fsp.c -// -void -GetFspReservedMemoryFromGuid ( - uint32_t *FspMemoryBase, - uint32_t *FspMemoryLength, - EFI_GUID FspReservedMemoryGuid - ); - -void -GetFspNVStorageMemory ( - void **FspNVStorageHob, - uint16_t *DataSize - ); - -void -GetTempRamStack ( - void **TempRamStackPtr, - uint16_t *DataSize - ); - -void -GetHighMemorySize ( - uint64_t *HighMemoryLength - ); - -void -GetLowMemorySize ( - uint32_t *LowMemoryLength - ); - -#endif diff --git a/src/vendorcode/intel/fsp1_0/baytrail/include/fsptypes.h b/src/vendorcode/intel/fsp1_0/baytrail/include/fsptypes.h deleted file mode 100644 index 4a313adc5d..0000000000 --- a/src/vendorcode/intel/fsp1_0/baytrail/include/fsptypes.h +++ /dev/null @@ -1,116 +0,0 @@ -/** - -Copyright (C) 2013, Intel Corporation - -Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - -* Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. -* Redistributions in binary form must reproduce the above copyright notice, this - list of conditions and the following disclaimer in the documentation and/or - other materials provided with the distribution. -* Neither the name of Intel Corporation nor the names of its contributors may - be used to endorse or promote products derived from this software without - specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE - LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF - THE POSSIBILITY OF SUCH DAMAGE. - -**/ - -/** \file fsptypes.h - * - * - */ - -#ifndef __FSP_TYPES_H__ -#define __FSP_TYPES_H__ - -/// -/// 8-byte unsigned value. -/// -typedef unsigned long long UINT64; -/// -/// 8-byte signed value. -/// -typedef long long INT64; -/// -/// 4-byte unsigned value. -/// -typedef unsigned int UINT32; -/// -/// 4-byte signed value. -/// -typedef int INT32; -/// -/// 2-byte unsigned value. -/// -typedef unsigned short UINT16; -/// -/// 2-byte Character. Unless otherwise specified all strings are stored in the -/// UTF-16 encoding format as defined by Unicode 2.1 and ISO/IEC 10646 standards. -/// -typedef unsigned short CHAR16; -/// -/// 2-byte signed value. -/// -typedef short INT16; -/// -/// Logical Boolean. 1-byte value containing 0 for FALSE or a 1 for TRUE. Other -/// values are undefined. -/// -typedef unsigned char BOOLEAN; -/// -/// 1-byte unsigned value. -/// -typedef unsigned char UINT8; -/// -/// 1-byte Character -/// -typedef char CHAR8; -/// -/// 1-byte signed value -/// -typedef char INT8; - -typedef void VOID; - -typedef UINT64 EFI_PHYSICAL_ADDRESS; - -typedef struct { - UINT32 Data1; - UINT16 Data2; - UINT16 Data3; - UINT8 Data4[8]; -} EFI_GUID; - -#define CONST const -#define STATIC static - -#define TRUE ((BOOLEAN)(1==1)) -#define FALSE ((BOOLEAN)(0==1)) - -#define FSPAPI __attribute__((cdecl)) -#define EFIAPI __attribute__((cdecl)) - -#define ASSERT(Expression) \ - do { \ - if (!(Expression)) { \ - for (;;); \ - } \ - } while (FALSE) - -typedef UINT32 FSP_STATUS; -typedef UINT32 EFI_STATUS; - -#endif diff --git a/src/vendorcode/intel/fsp1_0/baytrail/include/fspvpd.h b/src/vendorcode/intel/fsp1_0/baytrail/include/fspvpd.h deleted file mode 100644 index 4bdcb79b72..0000000000 --- a/src/vendorcode/intel/fsp1_0/baytrail/include/fspvpd.h +++ /dev/null @@ -1,126 +0,0 @@ -/** - -Copyright (C) 2013-2015 Intel Corporation - -Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - -* Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. -* Redistributions in binary form must reproduce the above copyright notice, this - list of conditions and the following disclaimer in the documentation and/or - other materials provided with the distribution. -* Neither the name of Intel Corporation nor the names of its contributors may - be used to endorse or promote products derived from this software without - specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE - LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF - THE POSSIBILITY OF SUCH DAMAGE. - -**/ - -#ifndef __FSPVPD_H__ -#define __FSPVPD_H__ - -#pragma pack(1) - -typedef struct { - UINT8 EnableMemoryDown; - UINT8 DRAMSpeed; /* DRAM Speed */ - UINT8 DRAMType; /* DRAM Type */ - UINT8 DIMM0Enable; /* DIMM 0 Enable */ - UINT8 DIMM1Enable; /* DIMM 1 Enable */ - UINT8 DIMMDWidth; /* DRAM device data width */ - UINT8 DIMMDensity; /* DRAM device data density */ - UINT8 DIMMBusWidth; /* DIMM Bus Width */ - UINT8 DIMMSides; /* Ranks Per DIMM */ - UINT8 DIMMtCL; /* tCL */ - UINT8 DIMMtRPtRCD; /* tRP and tRCD in DRAM clk - 5:12.5ns, 6:15ns, etc. */ - UINT8 DIMMtWR; /* tWR in DRAM clk */ - UINT8 DIMMtWTR; /* tWTR in DRAM clk */ - UINT8 DIMMtRRD; /* tRRD in DRAM clk */ - UINT8 DIMMtRTP; /* tRTP in DRAM clk */ - UINT8 DIMMtFAW; /* tFAW in DRAM clk */ -} MEMORY_DOWN_DATA; - - -typedef struct _UPD_DATA_REGION { - UINT64 Signature; /* Offset 0x0000 */ - UINT32 RESERVED1; /* Offset 0x0008 */ - UINT8 Padding0[20]; /* Offset 0x000C */ - UINT16 PcdMrcInitTsegSize; /* Offset 0x0020 */ - UINT16 PcdMrcInitMmioSize; /* Offset 0x0022 */ - UINT8 PcdMrcInitSPDAddr1; /* Offset 0x0024 */ - UINT8 PcdMrcInitSPDAddr2; /* Offset 0x0025 */ - UINT8 PcdeMMCBootMode; /* Offset 0x0026 */ - UINT8 PcdEnableSdio; /* Offset 0x0027 */ - UINT8 PcdEnableSdcard; /* Offset 0x0028 */ - UINT8 PcdEnableHsuart0; /* Offset 0x0029 */ - UINT8 PcdEnableHsuart1; /* Offset 0x002A */ - UINT8 PcdEnableSpi; /* Offset 0x002B */ - UINT8 ReservedUpdSpace1; /* Offset 0x002C */ - UINT8 PcdEnableSata; /* Offset 0x002D */ - UINT8 PcdSataMode; /* Offset 0x002E */ - UINT8 PcdEnableAzalia; /* Offset 0x002F */ - UINT32 AzaliaConfigPtr; /* Offset 0x0030 */ - UINT8 PcdEnableXhci; /* Offset 0x0034 */ - UINT8 PcdEnableLpe; /* Offset 0x0035 */ - UINT8 PcdLpssSioEnablePciMode; /* Offset 0x0036 */ - UINT8 PcdEnableDma0; /* Offset 0x0037 */ - UINT8 PcdEnableDma1; /* Offset 0x0038 */ - UINT8 PcdEnableI2C0; /* Offset 0x0039 */ - UINT8 PcdEnableI2C1; /* Offset 0x003A */ - UINT8 PcdEnableI2C2; /* Offset 0x003B */ - UINT8 PcdEnableI2C3; /* Offset 0x003C */ - UINT8 PcdEnableI2C4; /* Offset 0x003D */ - UINT8 PcdEnableI2C5; /* Offset 0x003E */ - UINT8 PcdEnableI2C6; /* Offset 0x003F */ - UINT8 PcdEnablePwm0; /* Offset 0x0040 */ - UINT8 PcdEnablePwm1; /* Offset 0x0041 */ - UINT8 PcdEnableHsi; /* Offset 0x0042 */ - UINT8 PcdIgdDvmt50PreAlloc; /* Offset 0x0043 */ - UINT8 PcdApertureSize; /* Offset 0x0044 */ - UINT8 PcdGttSize; /* Offset 0x0045 */ - UINT32 SerialDebugPortAddress; /* Offset 0x0046 */ - UINT8 SerialDebugPortType; /* Offset 0x004A */ - UINT8 PcdMrcDebugMsg; /* Offset 0x004B */ - UINT8 ISPEnable; /* Offset 0x004C */ - UINT8 PcdSccEnablePciMode; /* Offset 0x004D */ - UINT8 IgdRenderStandby; /* Offset 0x004E */ - UINT8 TxeUmaEnable; /* Offset 0x004F */ - UINT8 PcdOsSelection; /* Offset 0x0050 */ - UINT8 PcdEMMC45DDR50Enabled; /* Offset 0x0051 */ - UINT8 PcdEMMC45HS200Enabled; /* Offset 0x0052 */ - UINT8 PcdEMMC45RetuneTimerValue; /* Offset 0x0053 */ - UINT8 PcdEnableIgd; /* Offset 0x0054 */ - UINT8 AutoSelfRefreshEnable; /* Offset 0x0055 */ - UINT16 APTaskTimeoutCnt; /* Offset 0x0056 */ - UINT8 UnusedUpdSpace1[152]; /* Offset 0x0058 */ - MEMORY_DOWN_DATA PcdMemoryParameters; /* Offset 0x00F0 */ - UINT16 PcdRegionTerminator; /* Offset 0x0100 */ -} UPD_DATA_REGION; - - -typedef struct _VPD_DATA_REGION { - UINT64 PcdVpdRegionSign; /* Offset 0x0000 */ - UINT32 PcdImageRevision; /* Offset 0x0008 */ - UINT32 PcdUpdRegionOffset; /* Offset 0x000C */ - UINT8 Padding0[16]; /* Offset 0x0010 */ - UINT32 PcdFspReservedMemoryLength; /* Offset 0x0020 */ - UINT8 PcdPlatformType; /* Offset 0x0024 */ - UINT8 PcdEnableSecureBoot; /* Offset 0x0025 */ - UINT8 PcdMemoryParameters[16]; /* Offset 0x0026 */ -} VPD_DATA_REGION; - -#pragma pack() - -#endif diff --git a/src/vendorcode/intel/fsp1_0/baytrail/srx/board_fsp.c b/src/vendorcode/intel/fsp1_0/baytrail/srx/board_fsp.c deleted file mode 100644 index 85673ea2f7..0000000000 --- a/src/vendorcode/intel/fsp1_0/baytrail/srx/board_fsp.c +++ /dev/null @@ -1,186 +0,0 @@ -/** - -Copyright (C) 2013, Intel Corporation - -Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - -* Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. -* Redistributions in binary form must reproduce the above copyright notice, this - list of conditions and the following disclaimer in the documentation and/or - other materials provided with the distribution. -* Neither the name of Intel Corporation nor the names of its contributors may - be used to endorse or promote products derived from this software without - specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE - LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF - THE POSSIBILITY OF SUCH DAMAGE. - -**/ - -/*********************************************************************** - * - * board_fsp.c - * - * Parse HOB to get system data. - * - **********************************************************************/ -#include "fsp.h" - -void -GetLowMemorySize ( - uint32_t *LowMemoryLength - ) -{ - EFI_PEI_HOB_POINTERS Hob; - - *LowMemoryLength = 0x100000; - - // - // Get the HOB list for processing - // - Hob.Raw = GetHobList(); - - // - // Collect memory ranges - // - while (!END_OF_HOB_LIST(Hob.Raw)) { - if (Hob.Header->HobType == EFI_HOB_TYPE_RESOURCE_DESCRIPTOR) { - if (Hob.ResourceDescriptor->ResourceType == EFI_RESOURCE_SYSTEM_MEMORY) { - // - // Need memory above 1MB to be collected here - // - if (Hob.ResourceDescriptor->PhysicalStart >= 0x100000 && - Hob.ResourceDescriptor->PhysicalStart < (EFI_PHYSICAL_ADDRESS) 0x100000000) { - *LowMemoryLength += (uint32_t) (Hob.ResourceDescriptor->ResourceLength); - } - } - } - Hob.Raw = GET_NEXT_HOB(Hob.Raw); - } - - return; -} - -void -GetHighMemorySize ( - uint64_t *HighMemoryLength - ) -{ - EFI_PEI_HOB_POINTERS Hob; - - *HighMemoryLength = 0x0; - - // - // Get the HOB list for processing - // - Hob.Raw = GetHobList(); - - // - // Collect memory ranges - // - while (!END_OF_HOB_LIST(Hob.Raw)) { - if (Hob.Header->HobType == EFI_HOB_TYPE_RESOURCE_DESCRIPTOR) { - if (Hob.ResourceDescriptor->ResourceType == EFI_RESOURCE_SYSTEM_MEMORY) { - // - // Need memory above 4GB to be collected here - // - if (Hob.ResourceDescriptor->PhysicalStart >= (EFI_PHYSICAL_ADDRESS) 0x100000000) { - *HighMemoryLength += (uint64_t) (Hob.ResourceDescriptor->ResourceLength); - } - } - } - Hob.Raw = GET_NEXT_HOB(Hob.Raw); - } - - return; -} - -void -GetFspReservedMemoryFromGuid ( - uint32_t *FspMemoryBase, - uint32_t *FspMemoryLength, - EFI_GUID FspReservedMemoryGuid - ) -{ - EFI_PEI_HOB_POINTERS Hob; - - // - // Get the HOB list for processing - // - Hob.Raw = GetHobList(); - *FspMemoryBase = 0; - *FspMemoryLength = 0; - - // - // Collect memory ranges - // - while (!END_OF_HOB_LIST(Hob.Raw)) { - if (Hob.Header->HobType == EFI_HOB_TYPE_RESOURCE_DESCRIPTOR) { - if (Hob.ResourceDescriptor->ResourceType == EFI_RESOURCE_MEMORY_RESERVED) { - if (CompareGuid(&Hob.ResourceDescriptor->Owner, &FspReservedMemoryGuid)) { - *FspMemoryBase = (uint32_t) (Hob.ResourceDescriptor->PhysicalStart); - *FspMemoryLength = (uint32_t) (Hob.ResourceDescriptor->ResourceLength); - break; - } - } - } - Hob.Raw = GET_NEXT_HOB(Hob.Raw); - } - - return; -} - -void -GetFspNVStorageMemory ( - VOID **FspNVStorageHob, - uint16_t *DataSize - ) -{ - - EFI_GUID FspNVStorageHobGuid = FSP_NON_VOLATILE_STORAGE_HOB_GUID; - uint8_t *GuidHob; - EFI_HOB_GENERIC_HEADER *GuidHobHdr; - - GuidHob = GetFirstGuidHob(&FspNVStorageHobGuid); - if (!GuidHob) { - *FspNVStorageHob = 0; - *DataSize = 0; - } else { - *FspNVStorageHob = GET_GUID_HOB_DATA (GuidHob); - GuidHobHdr = (EFI_HOB_GENERIC_HEADER *)GuidHob; - *DataSize = GET_GUID_HOB_DATA_SIZE (GuidHobHdr); - } -} - -void -GetTempRamStack ( - VOID **TempRamStackPtr, - uint16_t *DataSize - ) -{ - - EFI_GUID FspBootloaderTemporaryMemoryHobGuid = FSP_BOOTLOADER_TEMPORARY_MEMORY_HOB_GUID; - uint8_t *GuidHob; - EFI_HOB_GENERIC_HEADER *GuidHobHdr; - - GuidHob = GetFirstGuidHob(&FspBootloaderTemporaryMemoryHobGuid); - if (!GuidHob) { - *TempRamStackPtr = 0; - *DataSize = 0; - } else { - *TempRamStackPtr = GET_GUID_HOB_DATA (GuidHob); - GuidHobHdr = (EFI_HOB_GENERIC_HEADER *)GuidHob; - *DataSize = GET_GUID_HOB_DATA_SIZE (GuidHobHdr); - } -} diff --git a/src/vendorcode/intel/fsp1_0/baytrail/srx/fsphob.c b/src/vendorcode/intel/fsp1_0/baytrail/srx/fsphob.c deleted file mode 100644 index 018682e418..0000000000 --- a/src/vendorcode/intel/fsp1_0/baytrail/srx/fsphob.c +++ /dev/null @@ -1,198 +0,0 @@ -/** - -Copyright (C) 2013, Intel Corporation - -Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - -* Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. -* Redistributions in binary form must reproduce the above copyright notice, this - list of conditions and the following disclaimer in the documentation and/or - other materials provided with the distribution. -* Neither the name of Intel Corporation nor the names of its contributors may - be used to endorse or promote products derived from this software without - specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE - LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF - THE POSSIBILITY OF SUCH DAMAGE. - -**/ - -/*********************************************************************** - * - * fsphob.c - * - * HOB infrastructure code. - * - **********************************************************************/ -#include - -#include "fsptypes.h" -#include "fsphob.h" - -// -// Pointer to the HOB should be initialized with the output of FSP INIT PARAMS -// -extern volatile void *FspHobListPtr; - -/** - Reads a 64-bit value from memory that may be unaligned. - - This function returns the 64-bit value pointed to by Buffer. The function - guarantees that the read operation does not produce an alignment fault. - - If the Buffer is NULL, then ASSERT(). - - @param Buffer Pointer to a 64-bit value that may be unaligned. - - @return The 64-bit value read from Buffer. - -**/ -UINT64 -EFIAPI -ReadUnaligned64 ( - CONST UINT64 *Buffer - ) -{ - ASSERT (Buffer != NULL); - - return *Buffer; -} - -/** - Compares two GUIDs. - - This function compares Guid1 to Guid2. If the GUIDs are identical then TRUE is returned. - If there are any bit differences in the two GUIDs, then FALSE is returned. - - If Guid1 is NULL, then ASSERT(). - If Guid2 is NULL, then ASSERT(). - - @param Guid1 A pointer to a 128 bit GUID. - @param Guid2 A pointer to a 128 bit GUID. - - @retval TRUE Guid1 and Guid2 are identical. - @retval FALSE Guid1 and Guid2 are not identical. - -**/ -BOOLEAN -EFIAPI -CompareGuid ( - CONST EFI_GUID *Guid1, - CONST EFI_GUID *Guid2 - ) -{ - UINT64 LowPartOfGuid1; - UINT64 LowPartOfGuid2; - UINT64 HighPartOfGuid1; - UINT64 HighPartOfGuid2; - - LowPartOfGuid1 = ReadUnaligned64 ((CONST UINT64*) Guid1); - LowPartOfGuid2 = ReadUnaligned64 ((CONST UINT64*) Guid2); - HighPartOfGuid1 = ReadUnaligned64 ((CONST UINT64*) Guid1 + 1); - HighPartOfGuid2 = ReadUnaligned64 ((CONST UINT64*) Guid2 + 1); - - return (BOOLEAN) (LowPartOfGuid1 == LowPartOfGuid2 && HighPartOfGuid1 == HighPartOfGuid2); -} - -/** - Returns the pointer to the HOB list. -**/ -VOID * -EFIAPI -GetHobList ( - VOID - ) -{ - ASSERT (FspHobListPtr != NULL); - return ((VOID *)FspHobListPtr); -} - -/** - Returns the next instance of a HOB type from the starting HOB. -**/ -VOID * -EFIAPI -GetNextHob ( - UINT16 Type, - CONST VOID *HobStart - ) -{ - EFI_PEI_HOB_POINTERS Hob; - - ASSERT (HobStart != NULL); - - Hob.Raw = (UINT8 *) HobStart; - // - // Parse the HOB list until end of list or matching type is found. - // - while (!END_OF_HOB_LIST(Hob.Raw)) { - if (Hob.Header->HobType == Type) { - return Hob.Raw; - } - Hob.Raw = GET_NEXT_HOB(Hob.Raw); - } - return NULL; -} - -/** - Returns the first instance of a HOB type among the whole HOB list. -**/ -VOID * -EFIAPI -GetFirstHob ( - UINT16 Type - ) -{ - VOID *HobList; - - HobList = GetHobList (); - return GetNextHob (Type, HobList); -} - -/** - Returns the next instance of the matched GUID HOB from the starting HOB. -**/ -VOID * -EFIAPI -GetNextGuidHob ( - CONST EFI_GUID *Guid, - CONST VOID *HobStart - ) -{ - EFI_PEI_HOB_POINTERS GuidHob; - - GuidHob.Raw = (UINT8 *) HobStart; - while ((GuidHob.Raw = GetNextHob (EFI_HOB_TYPE_GUID_EXTENSION, GuidHob.Raw)) != NULL) { - if (CompareGuid (Guid, &GuidHob.Guid->Name)) { - break; - } - GuidHob.Raw = GET_NEXT_HOB(GuidHob.Raw); - } - return GuidHob.Raw; -} - -/** - Returns the first instance of the matched GUID HOB among the whole HOB list. -**/ -VOID * -EFIAPI -GetFirstGuidHob ( - CONST EFI_GUID *Guid - ) -{ - VOID *HobList; - - HobList = GetHobList (); - return GetNextGuidHob (Guid, HobList); -} From 433471244b7313dde6bb07d58943bfd0d9957c59 Mon Sep 17 00:00:00 2001 From: Arthur Heymans Date: Tue, 19 Nov 2019 18:48:48 +0100 Subject: [PATCH 0308/1242] mb/*/*: Remove BROADWELL_DE boards MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Relocatable ramstage, postcar stage and C_ENVIRONMENT_BOOTBLOCK are now mandatory features, which this platform lacks. Change-Id: I3d9b6bb48bfd15c0182448f774e9af1e0c944fd5 Signed-off-by: Arthur Heymans Reviewed-on: https://review.coreboot.org/c/coreboot/+/36983 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki Reviewed-by: David Hendricks Reviewed-by: Werner Zeh --- src/mainboard/facebook/watson/Kconfig | 57 ---- src/mainboard/facebook/watson/Kconfig.name | 2 - src/mainboard/facebook/watson/Makefile.inc | 16 - .../facebook/watson/acpi/mainboard.asl | 20 -- .../facebook/watson/acpi/platform.asl | 56 ---- src/mainboard/facebook/watson/acpi_tables.c | 42 --- src/mainboard/facebook/watson/board.fmd | 26 -- src/mainboard/facebook/watson/board_info.txt | 4 - src/mainboard/facebook/watson/cmos.layout | 106 ------- src/mainboard/facebook/watson/devicetree.cb | 19 -- src/mainboard/facebook/watson/dsdt.asl | 45 --- src/mainboard/facebook/watson/fadt.c | 27 -- src/mainboard/facebook/watson/irqroute.c | 18 -- src/mainboard/facebook/watson/irqroute.h | 48 --- src/mainboard/facebook/watson/mainboard.c | 40 --- src/mainboard/facebook/watson/romstage.c | 45 --- src/mainboard/facebook/watson/vboot-ro.fmd | 26 -- .../intel/camelbackmountain_fsp/Kconfig | 41 --- .../intel/camelbackmountain_fsp/Kconfig.name | 2 - .../intel/camelbackmountain_fsp/Makefile.inc | 16 - .../camelbackmountain_fsp/acpi/mainboard.asl | 20 -- .../camelbackmountain_fsp/acpi/platform.asl | 56 ---- .../intel/camelbackmountain_fsp/acpi_tables.c | 43 --- .../camelbackmountain_fsp/board_info.txt | 5 - .../intel/camelbackmountain_fsp/cmos.layout | 119 ------- .../intel/camelbackmountain_fsp/devicetree.cb | 15 - .../intel/camelbackmountain_fsp/dsdt.asl | 294 ------------------ .../intel/camelbackmountain_fsp/fadt.c | 27 -- .../intel/camelbackmountain_fsp/irqroute.c | 18 -- .../intel/camelbackmountain_fsp/irqroute.h | 48 --- .../intel/camelbackmountain_fsp/mainboard.c | 35 --- .../intel/camelbackmountain_fsp/romstage.c | 45 --- src/mainboard/ocp/Kconfig | 16 - src/mainboard/ocp/Kconfig.name | 2 - src/mainboard/ocp/monolake/Kconfig | 63 ---- src/mainboard/ocp/monolake/Kconfig.name | 2 - src/mainboard/ocp/monolake/Makefile.inc | 17 - src/mainboard/ocp/monolake/acpi/mainboard.asl | 20 -- src/mainboard/ocp/monolake/acpi/platform.asl | 56 ---- src/mainboard/ocp/monolake/acpi_tables.c | 43 --- src/mainboard/ocp/monolake/board.fmd | 22 -- src/mainboard/ocp/monolake/board_info.txt | 5 - src/mainboard/ocp/monolake/cmos.layout | 120 ------- src/mainboard/ocp/monolake/devicetree.cb | 25 -- src/mainboard/ocp/monolake/dsdt.asl | 294 ------------------ src/mainboard/ocp/monolake/fadt.c | 27 -- src/mainboard/ocp/monolake/ipmi.c | 78 ----- src/mainboard/ocp/monolake/ipmi.h | 53 ---- src/mainboard/ocp/monolake/irqroute.c | 18 -- src/mainboard/ocp/monolake/irqroute.h | 48 --- src/mainboard/ocp/monolake/mainboard.c | 97 ------ src/mainboard/ocp/monolake/romstage.c | 248 --------------- src/mainboard/ocp/monolake/vboot-ro.fmd | 22 -- src/mainboard/ocp/wedge100s/Kconfig | 61 ---- src/mainboard/ocp/wedge100s/Kconfig.name | 2 - src/mainboard/ocp/wedge100s/Makefile.inc | 16 - .../ocp/wedge100s/acpi/mainboard.asl | 20 -- src/mainboard/ocp/wedge100s/acpi/platform.asl | 56 ---- src/mainboard/ocp/wedge100s/acpi_tables.c | 43 --- src/mainboard/ocp/wedge100s/board.fmd | 27 -- src/mainboard/ocp/wedge100s/board_info.txt | 5 - src/mainboard/ocp/wedge100s/cmos.layout | 120 ------- src/mainboard/ocp/wedge100s/devicetree.cb | 74 ----- src/mainboard/ocp/wedge100s/dsdt.asl | 294 ------------------ src/mainboard/ocp/wedge100s/fadt.c | 27 -- src/mainboard/ocp/wedge100s/irqroute.c | 18 -- src/mainboard/ocp/wedge100s/irqroute.h | 48 --- src/mainboard/ocp/wedge100s/mainboard.c | 33 -- src/mainboard/ocp/wedge100s/romstage.c | 103 ------ src/mainboard/ocp/wedge100s/vboot-ro.fmd | 22 -- src/mainboard/siemens/mc_bdx1/Kconfig | 63 ---- src/mainboard/siemens/mc_bdx1/Kconfig.name | 2 - src/mainboard/siemens/mc_bdx1/Makefile.inc | 16 - .../siemens/mc_bdx1/acpi/mainboard.asl | 20 -- .../siemens/mc_bdx1/acpi/platform.asl | 56 ---- src/mainboard/siemens/mc_bdx1/acpi_tables.c | 43 --- src/mainboard/siemens/mc_bdx1/board_info.txt | 5 - src/mainboard/siemens/mc_bdx1/cmos.layout | 119 ------- src/mainboard/siemens/mc_bdx1/devicetree.cb | 40 --- src/mainboard/siemens/mc_bdx1/dsdt.asl | 294 ------------------ src/mainboard/siemens/mc_bdx1/fadt.c | 27 -- src/mainboard/siemens/mc_bdx1/gpio.h | 92 ------ src/mainboard/siemens/mc_bdx1/irqroute.c | 18 -- src/mainboard/siemens/mc_bdx1/irqroute.h | 48 --- src/mainboard/siemens/mc_bdx1/mainboard.c | 273 ---------------- src/mainboard/siemens/mc_bdx1/mc_bdx1.fmd | 25 -- src/mainboard/siemens/mc_bdx1/romstage.c | 48 --- 87 files changed, 4815 deletions(-) delete mode 100644 src/mainboard/facebook/watson/Kconfig delete mode 100644 src/mainboard/facebook/watson/Kconfig.name delete mode 100644 src/mainboard/facebook/watson/Makefile.inc delete mode 100644 src/mainboard/facebook/watson/acpi/mainboard.asl delete mode 100644 src/mainboard/facebook/watson/acpi/platform.asl delete mode 100644 src/mainboard/facebook/watson/acpi_tables.c delete mode 100644 src/mainboard/facebook/watson/board.fmd delete mode 100644 src/mainboard/facebook/watson/board_info.txt delete mode 100644 src/mainboard/facebook/watson/cmos.layout delete mode 100644 src/mainboard/facebook/watson/devicetree.cb delete mode 100644 src/mainboard/facebook/watson/dsdt.asl delete mode 100644 src/mainboard/facebook/watson/fadt.c delete mode 100644 src/mainboard/facebook/watson/irqroute.c delete mode 100644 src/mainboard/facebook/watson/irqroute.h delete mode 100644 src/mainboard/facebook/watson/mainboard.c delete mode 100644 src/mainboard/facebook/watson/romstage.c delete mode 100644 src/mainboard/facebook/watson/vboot-ro.fmd delete mode 100644 src/mainboard/intel/camelbackmountain_fsp/Kconfig delete mode 100644 src/mainboard/intel/camelbackmountain_fsp/Kconfig.name delete mode 100644 src/mainboard/intel/camelbackmountain_fsp/Makefile.inc delete mode 100644 src/mainboard/intel/camelbackmountain_fsp/acpi/mainboard.asl delete mode 100644 src/mainboard/intel/camelbackmountain_fsp/acpi/platform.asl delete mode 100644 src/mainboard/intel/camelbackmountain_fsp/acpi_tables.c delete mode 100644 src/mainboard/intel/camelbackmountain_fsp/board_info.txt delete mode 100644 src/mainboard/intel/camelbackmountain_fsp/cmos.layout delete mode 100644 src/mainboard/intel/camelbackmountain_fsp/devicetree.cb delete mode 100644 src/mainboard/intel/camelbackmountain_fsp/dsdt.asl delete mode 100644 src/mainboard/intel/camelbackmountain_fsp/fadt.c delete mode 100644 src/mainboard/intel/camelbackmountain_fsp/irqroute.c delete mode 100644 src/mainboard/intel/camelbackmountain_fsp/irqroute.h delete mode 100644 src/mainboard/intel/camelbackmountain_fsp/mainboard.c delete mode 100644 src/mainboard/intel/camelbackmountain_fsp/romstage.c delete mode 100644 src/mainboard/ocp/Kconfig delete mode 100644 src/mainboard/ocp/Kconfig.name delete mode 100644 src/mainboard/ocp/monolake/Kconfig delete mode 100644 src/mainboard/ocp/monolake/Kconfig.name delete mode 100644 src/mainboard/ocp/monolake/Makefile.inc delete mode 100644 src/mainboard/ocp/monolake/acpi/mainboard.asl delete mode 100644 src/mainboard/ocp/monolake/acpi/platform.asl delete mode 100644 src/mainboard/ocp/monolake/acpi_tables.c delete mode 100644 src/mainboard/ocp/monolake/board.fmd delete mode 100644 src/mainboard/ocp/monolake/board_info.txt delete mode 100644 src/mainboard/ocp/monolake/cmos.layout delete mode 100644 src/mainboard/ocp/monolake/devicetree.cb delete mode 100644 src/mainboard/ocp/monolake/dsdt.asl delete mode 100644 src/mainboard/ocp/monolake/fadt.c delete mode 100644 src/mainboard/ocp/monolake/ipmi.c delete mode 100644 src/mainboard/ocp/monolake/ipmi.h delete mode 100644 src/mainboard/ocp/monolake/irqroute.c delete mode 100644 src/mainboard/ocp/monolake/irqroute.h delete mode 100644 src/mainboard/ocp/monolake/mainboard.c delete mode 100644 src/mainboard/ocp/monolake/romstage.c delete mode 100644 src/mainboard/ocp/monolake/vboot-ro.fmd delete mode 100644 src/mainboard/ocp/wedge100s/Kconfig delete mode 100644 src/mainboard/ocp/wedge100s/Kconfig.name delete mode 100644 src/mainboard/ocp/wedge100s/Makefile.inc delete mode 100644 src/mainboard/ocp/wedge100s/acpi/mainboard.asl delete mode 100644 src/mainboard/ocp/wedge100s/acpi/platform.asl delete mode 100644 src/mainboard/ocp/wedge100s/acpi_tables.c delete mode 100644 src/mainboard/ocp/wedge100s/board.fmd delete mode 100644 src/mainboard/ocp/wedge100s/board_info.txt delete mode 100644 src/mainboard/ocp/wedge100s/cmos.layout delete mode 100644 src/mainboard/ocp/wedge100s/devicetree.cb delete mode 100644 src/mainboard/ocp/wedge100s/dsdt.asl delete mode 100644 src/mainboard/ocp/wedge100s/fadt.c delete mode 100644 src/mainboard/ocp/wedge100s/irqroute.c delete mode 100644 src/mainboard/ocp/wedge100s/irqroute.h delete mode 100644 src/mainboard/ocp/wedge100s/mainboard.c delete mode 100644 src/mainboard/ocp/wedge100s/romstage.c delete mode 100644 src/mainboard/ocp/wedge100s/vboot-ro.fmd delete mode 100644 src/mainboard/siemens/mc_bdx1/Kconfig delete mode 100644 src/mainboard/siemens/mc_bdx1/Kconfig.name delete mode 100644 src/mainboard/siemens/mc_bdx1/Makefile.inc delete mode 100644 src/mainboard/siemens/mc_bdx1/acpi/mainboard.asl delete mode 100644 src/mainboard/siemens/mc_bdx1/acpi/platform.asl delete mode 100644 src/mainboard/siemens/mc_bdx1/acpi_tables.c delete mode 100644 src/mainboard/siemens/mc_bdx1/board_info.txt delete mode 100644 src/mainboard/siemens/mc_bdx1/cmos.layout delete mode 100644 src/mainboard/siemens/mc_bdx1/devicetree.cb delete mode 100644 src/mainboard/siemens/mc_bdx1/dsdt.asl delete mode 100644 src/mainboard/siemens/mc_bdx1/fadt.c delete mode 100644 src/mainboard/siemens/mc_bdx1/gpio.h delete mode 100644 src/mainboard/siemens/mc_bdx1/irqroute.c delete mode 100644 src/mainboard/siemens/mc_bdx1/irqroute.h delete mode 100644 src/mainboard/siemens/mc_bdx1/mainboard.c delete mode 100644 src/mainboard/siemens/mc_bdx1/mc_bdx1.fmd delete mode 100644 src/mainboard/siemens/mc_bdx1/romstage.c diff --git a/src/mainboard/facebook/watson/Kconfig b/src/mainboard/facebook/watson/Kconfig deleted file mode 100644 index 3235b6cc99..0000000000 --- a/src/mainboard/facebook/watson/Kconfig +++ /dev/null @@ -1,57 +0,0 @@ -if BOARD_FACEBOOK_WATSON - -config BOARD_SPECIFIC_OPTIONS - def_bool y - select SOC_INTEL_FSP_BROADWELL_DE - select BOARD_ROMSIZE_KB_16384 - select HAVE_ACPI_TABLES - select HAVE_OPTION_TABLE - select INTEGRATED_UART - select SERIRQ_CONTINUOUS_MODE - select MAINBOARD_USES_IFD_GBE_REGION - select MAINBOARD_HAS_LPC_TPM - select MAINBOARD_HAS_TPM1 - select NO_UART_ON_SUPERIO - -config VBOOT - select VBOOT_VBNV_CMOS - select VBOOT_NO_BOARD_SUPPORT - select GBB_FLAG_DISABLE_LID_SHUTDOWN - select GBB_FLAG_DISABLE_PD_SOFTWARE_SYNC - select GBB_FLAG_DISABLE_EC_SOFTWARE_SYNC - select GBB_FLAG_DISABLE_FWMP - -config MAINBOARD_DIR - string - default "facebook/watson" - -config MAINBOARD_PART_NUMBER - string - default "Watson" - -config IRQ_SLOT_COUNT - int - default 18 - -config CBFS_SIZE - hex - default 0x00800000 - -config VIRTUAL_ROM_SIZE - hex - # Set to CONFIG_ROM_SIZE*2 if using concatenated flash chips. - # See FSP's Kconfig for details. - default ROM_SIZE - -config DRIVERS_UART_8250IO - def_bool n - -config FMDFILE - string - default "src/mainboard/$(CONFIG_MAINBOARD_DIR)/board.fmd" - -config ENABLE_TURBO - bool "Enable turbo frequency" - default n - -endif # BOARD_FACEBOOK_WATSON diff --git a/src/mainboard/facebook/watson/Kconfig.name b/src/mainboard/facebook/watson/Kconfig.name deleted file mode 100644 index ea6c344791..0000000000 --- a/src/mainboard/facebook/watson/Kconfig.name +++ /dev/null @@ -1,2 +0,0 @@ -config BOARD_FACEBOOK_WATSON - bool "Watson" diff --git a/src/mainboard/facebook/watson/Makefile.inc b/src/mainboard/facebook/watson/Makefile.inc deleted file mode 100644 index 1606476d80..0000000000 --- a/src/mainboard/facebook/watson/Makefile.inc +++ /dev/null @@ -1,16 +0,0 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2012 Google Inc. -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; version 2 of the License. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## - -ramstage-y += irqroute.c diff --git a/src/mainboard/facebook/watson/acpi/mainboard.asl b/src/mainboard/facebook/watson/acpi/mainboard.asl deleted file mode 100644 index 62944ef353..0000000000 --- a/src/mainboard/facebook/watson/acpi/mainboard.asl +++ /dev/null @@ -1,20 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2012 Google Inc. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -Device (PWRB) -{ - Name(_HID, EisaId("PNP0C0C")) -} diff --git a/src/mainboard/facebook/watson/acpi/platform.asl b/src/mainboard/facebook/watson/acpi/platform.asl deleted file mode 100644 index 7ffae2e6e0..0000000000 --- a/src/mainboard/facebook/watson/acpi/platform.asl +++ /dev/null @@ -1,56 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007-2009 coresystems GmbH - * Copyright (C) 2012 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -/* The APM port can be used for generating software SMIs */ - -OperationRegion (APMP, SystemIO, 0xb2, 2) -Field (APMP, ByteAcc, NoLock, Preserve) -{ - APMC, 8, // APM command - APMS, 8 // APM status -} - -/* Port 80 POST */ - -OperationRegion (POST, SystemIO, 0x80, 1) -Field (POST, ByteAcc, Lock, Preserve) -{ - DBG0, 8 -} - -Name(\APC1, Zero) // IIO IOAPIC - -Name(\PICM, Zero) // IOAPIC/8259 - -Method(_PIC, 1) -{ - Store(Arg0, PICM) -} - -/* The _PTS method (Prepare To Sleep) is called before the OS is - * entering a sleep state. The sleep state number is passed in Arg0 - */ - -Method(_PTS,1) -{ -} - -/* The _WAK method is called on system wakeup */ - -Method(_WAK,1) -{ - Return(Package(){0,0}) -} diff --git a/src/mainboard/facebook/watson/acpi_tables.c b/src/mainboard/facebook/watson/acpi_tables.c deleted file mode 100644 index 250ff58b36..0000000000 --- a/src/mainboard/facebook/watson/acpi_tables.c +++ /dev/null @@ -1,42 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2012 Google Inc. - * Copyright (C) 2015-2016 Intel Corp. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include - -unsigned long acpi_fill_madt(unsigned long current) -{ - u32 i; - - current = acpi_create_madt_lapics(current); - - current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, 8, - IOXAPIC1_BASE_ADDRESS, 0); - set_ioapic_id((u8 *)IOXAPIC1_BASE_ADDRESS, 8); - - current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, 9, - IOXAPIC2_BASE_ADDRESS, 24); - set_ioapic_id((u8 *)IOXAPIC2_BASE_ADDRESS, 9); - - current = acpi_madt_irq_overrides(current); - - for (i = 0; i < 16; i++) - current += acpi_create_madt_lapic_nmi( - (acpi_madt_lapic_nmi_t *)current, i, 0xD, 1); - - return current; -} diff --git a/src/mainboard/facebook/watson/board.fmd b/src/mainboard/facebook/watson/board.fmd deleted file mode 100644 index feeb799a8e..0000000000 --- a/src/mainboard/facebook/watson/board.fmd +++ /dev/null @@ -1,26 +0,0 @@ -FLASH@0xff000000 0x1000000 { - SI_DESC@0x0 0x1000 - UNUSED_1@0x1000 0x1000 - IDPROM@0x2000 0x400 - UNUSED_2@0x2400 0x1ec00 - SI_ME@0x21000 0x3de000 - UNUSED_3@0x400000 0x200000 - SI_BIOS@0x600000 0xA00000 { - FMAP@0x0 0x1000 - RW_MISC@0x1000 0xe000 { - RW_ELOG@0x0 0x4000 - RW_VPD@0x4000 0x2000 - RW_MISC_UNUSED@0x6000 0x5000 - RW_NVRAM@0xc000 0x2000 - } - UNIFIED_MRC_CACHE@0x10000 0x20000 { - RECOVERY_MRC_CACHE@0x0 0x10000 - RW_MRC_CACHE@0x10000 0x10000 - } - # This only exists to satisfy tools that specifically - # look for RO_VPD. - RO_VPD@0x30000 0x1000 - UNUSED_4@0x31000 0x1cf000 - COREBOOT(CBFS)@0x200000 0x800000 - } -} diff --git a/src/mainboard/facebook/watson/board_info.txt b/src/mainboard/facebook/watson/board_info.txt deleted file mode 100644 index 3278401533..0000000000 --- a/src/mainboard/facebook/watson/board_info.txt +++ /dev/null @@ -1,4 +0,0 @@ -Board name: Watson -Category: server -ROM protocol: SPI -ROM socketed: yes diff --git a/src/mainboard/facebook/watson/cmos.layout b/src/mainboard/facebook/watson/cmos.layout deleted file mode 100644 index 675370df70..0000000000 --- a/src/mainboard/facebook/watson/cmos.layout +++ /dev/null @@ -1,106 +0,0 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2007-2008 coresystems GmbH -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; version 2 of the License. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## - -# ----------------------------------------------------------------- -entries - -#start-bit length config config-ID name -#0 8 r 0 seconds -#8 8 r 0 alarm_seconds -#16 8 r 0 minutes -#24 8 r 0 alarm_minutes -#32 8 r 0 hours -#40 8 r 0 alarm_hours -#48 8 r 0 day_of_week -#56 8 r 0 day_of_month -#64 8 r 0 month -#72 8 r 0 year -# ----------------------------------------------------------------- -# Status Register A -#80 4 r 0 rate_select -#84 3 r 0 REF_Clock -#87 1 r 0 UIP -# ----------------------------------------------------------------- -# Status Register B -#88 1 r 0 auto_switch_DST -#89 1 r 0 24_hour_mode -#90 1 r 0 binary_values_enable -#91 1 r 0 square-wave_out_enable -#92 1 r 0 update_finished_enable -#93 1 r 0 alarm_interrupt_enable -#94 1 r 0 periodic_interrupt_enable -#95 1 r 0 disable_clock_updates -# ----------------------------------------------------------------- -# Status Register C -#96 4 r 0 status_c_rsvd -#100 1 r 0 uf_flag -#101 1 r 0 af_flag -#102 1 r 0 pf_flag -#103 1 r 0 irqf_flag -# ----------------------------------------------------------------- -# Status Register D -#104 7 r 0 status_d_rsvd -#111 1 r 0 valid_cmos_ram -# ----------------------------------------------------------------- -# Diagnostic Status Register -#112 8 r 0 diag_rsvd1 - -# ----------------------------------------------------------------- -0 120 r 0 reserved_memory -120 264 r 0 unused - -# ----------------------------------------------------------------- -# RTC_BOOT_BYTE (coreboot hardcoded) -384 1 e 4 boot_option -388 4 h 0 reboot_counter -#390 2 r 0 unused? - -# ----------------------------------------------------------------- -# coreboot config options: console -#392 3 r 0 unused -395 4 e 6 debug_level -#399 1 r 0 unused -416 128 r 0 vbnv - -# coreboot config options: check sums -984 16 h 0 check_sum - -# ----------------------------------------------------------------- - -enumerations - -#ID value text -1 0 Disable -1 1 Enable -2 0 Enable -2 1 Disable -4 0 Fallback -4 1 Normal -6 1 Emergency -6 2 Alert -6 3 Critical -6 4 Error -6 5 Warning -6 6 Notice -6 7 Info -6 8 Debug -6 9 Spew -7 0 Disable -7 1 Enable -7 2 Keep -# ----------------------------------------------------------------- -checksums - -checksum 392 415 984 diff --git a/src/mainboard/facebook/watson/devicetree.cb b/src/mainboard/facebook/watson/devicetree.cb deleted file mode 100644 index 92fe9c3000..0000000000 --- a/src/mainboard/facebook/watson/devicetree.cb +++ /dev/null @@ -1,19 +0,0 @@ -chip soc/intel/fsp_broadwell_de - device cpu_cluster 0 on - device lapic 0 on end - end - device domain 0 on - device pci 00.0 on end # SoC router - device pci 14.0 on end # xHCI Controller - device pci 19.0 on end # Gigabit LAN Controller - device pci 1d.0 on end # EHCI Controller - device pci 1f.0 on # LPC Bridge - chip drivers/pc80/tpm - device pnp 0c31.0 on end - end - end - device pci 1f.2 on end # SATA Controller - device pci 1f.3 on end # SMBus Controller - device pci 1f.5 on end # SATA Controller - end -end diff --git a/src/mainboard/facebook/watson/dsdt.asl b/src/mainboard/facebook/watson/dsdt.asl deleted file mode 100644 index 0d9e90dab3..0000000000 --- a/src/mainboard/facebook/watson/dsdt.asl +++ /dev/null @@ -1,45 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007-2009 coresystems GmbH - * Copyright (C) 2011 Google Inc. - * Copyright (C) 2015-2016 Intel Corp. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -DefinitionBlock( - "dsdt.aml", - "DSDT", - 0x02, // DSDT revision: ACPI v2.0 and up - OEM_ID, - ACPI_TABLE_CREATOR, - 0x20110725 // OEM revision -) -{ - #include "acpi/platform.asl" - - Name(_S0, Package() { 0x00, 0x00, 0x00, 0x00 }) - Name(_S5, Package() { 0x07, 0x00, 0x00, 0x00 }) - - Scope (\_SB) - { - Device (PCI0) - { - #include - #include - } - - #include - } - - #include "acpi/mainboard.asl" -} diff --git a/src/mainboard/facebook/watson/fadt.c b/src/mainboard/facebook/watson/fadt.c deleted file mode 100644 index 5af6056b49..0000000000 --- a/src/mainboard/facebook/watson/fadt.c +++ /dev/null @@ -1,27 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007-2009 coresystems GmbH - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include - -void acpi_create_fadt(acpi_fadt_t *fadt, acpi_facs_t *facs, void *dsdt) -{ - acpi_header_t *header = &(fadt->header); - - acpi_fill_in_fadt(fadt, facs, dsdt); - - /* Platform specific customizations go here */ - - header->checksum = acpi_checksum((void *) fadt, sizeof(acpi_fadt_t)); -} diff --git a/src/mainboard/facebook/watson/irqroute.c b/src/mainboard/facebook/watson/irqroute.c deleted file mode 100644 index f91cf0d5b3..0000000000 --- a/src/mainboard/facebook/watson/irqroute.c +++ /dev/null @@ -1,18 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2012 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include "irqroute.h" - -DEFINE_IRQ_ROUTES; diff --git a/src/mainboard/facebook/watson/irqroute.h b/src/mainboard/facebook/watson/irqroute.h deleted file mode 100644 index c3911be75b..0000000000 --- a/src/mainboard/facebook/watson/irqroute.h +++ /dev/null @@ -1,48 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2012 Google Inc. - * Copyright (C) 2015-2016 Intel Corp. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef IRQROUTE_H -#define IRQROUTE_H - -#include -#include - -#define PCI_DEV_PIRQ_ROUTES \ - PCI_DEV_PIRQ_ROUTE(XHCI_DEV, A, B, C, D), \ - PCI_DEV_PIRQ_ROUTE(ME_DEV, A, B, C, D), \ - PCI_DEV_PIRQ_ROUTE(GBE_DEV, A, B, C, D), \ - PCI_DEV_PIRQ_ROUTE(EHCI2_DEV, A, B, C, D), \ - PCI_DEV_PIRQ_ROUTE(HDA_DEV, A, B, C, D), \ - PCI_DEV_PIRQ_ROUTE(PCIE_DEV, A, B, C, D), \ - PCI_DEV_PIRQ_ROUTE(EHCI1_DEV, A, B, C, D), \ - PCI_DEV_PIRQ_ROUTE(SATA_DEV, A, B, C, D) - -/* - * Route each PIRQ[A-H] to a PIC IRQ[0-15] - * Reserved: 0, 1, 2, 8, 13 - * ACPI/SCI: 9 - */ -#define PIRQ_PIC_ROUTES \ - PIRQ_PIC(A, 5), \ - PIRQ_PIC(B, 6), \ - PIRQ_PIC(C, 7), \ - PIRQ_PIC(D, 10), \ - PIRQ_PIC(E, 11), \ - PIRQ_PIC(F, 12), \ - PIRQ_PIC(G, 14), \ - PIRQ_PIC(H, 15) - -#endif /* IRQROUTE_H */ diff --git a/src/mainboard/facebook/watson/mainboard.c b/src/mainboard/facebook/watson/mainboard.c deleted file mode 100644 index 403090a06f..0000000000 --- a/src/mainboard/facebook/watson/mainboard.c +++ /dev/null @@ -1,40 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007-2009 coresystems GmbH - * Copyright (C) 2011 Google Inc. - * Copyright (C) Facebook, Inc. and its affiliates - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include - -/* - * mainboard_enable is executed as first thing after enumerate_buses(). - * This is the earliest point to add customization. - */ -static void mainboard_enable(struct device *dev) -{ - -} - -static void mainboard_init(void *chip_info) -{ -#if !CONFIG(ENABLE_TURBO) - disable_turbo(); -#endif -} - -struct chip_operations mainboard_ops = { - .enable_dev = mainboard_enable, - .init = mainboard_init, -}; diff --git a/src/mainboard/facebook/watson/romstage.c b/src/mainboard/facebook/watson/romstage.c deleted file mode 100644 index cf52c01f04..0000000000 --- a/src/mainboard/facebook/watson/romstage.c +++ /dev/null @@ -1,45 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2013 Google Inc. - * Copyright (C) 2015 Intel Corp. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include - -/** - * /brief mainboard call for setup that needs to be done before fsp init - * - */ -void early_mainboard_romstage_entry(void) -{ - -} - -/** - * /brief mainboard call for setup that needs to be done after fsp init - * - */ -void late_mainboard_romstage_entry(void) -{ - -} - -/** - * /brief customize fsp parameters here if needed - */ -void romstage_fsp_rt_buffer_callback(FSP_INIT_RT_BUFFER *FspRtBuffer) -{ - -} diff --git a/src/mainboard/facebook/watson/vboot-ro.fmd b/src/mainboard/facebook/watson/vboot-ro.fmd deleted file mode 100644 index cc6a7c57a8..0000000000 --- a/src/mainboard/facebook/watson/vboot-ro.fmd +++ /dev/null @@ -1,26 +0,0 @@ -FLASH 16M { - SI_ALL@0x0 0x600000 { - SI_DESC@0x0 0x1000 - UNUSED_1@0x1000 0x1000 - IDPROM@0x2000 0x400 - UNUSED_2@0x2400 0x1ec00 - SI_ME@0x21000 0x3de000 - UNUSED_3@0x400000 0x200000 - } - SI_BIOS@0x600000 0xA00000 { - MISC_RW@0x0 0x20000 { - RW_MRC_CACHE@0x0 0x10000 - RW_VPD(PRESERVE)@0x010000 0x4000 - } - WP_RO@0x20000 0x9e0000 { - RO_VPD(PRESERVE)@0x0 0x4000 - RO_SECTION@0x4000 0x9dc000 { - FMAP@0x0 0x800 - RO_FRID@0x800 0x40 - RO_FRID_PAD@0x840 0x7c0 - GBB@0x1000 0x4000 - COREBOOT(CBFS)@0x5000 0x9d7000 - } - } - } -} diff --git a/src/mainboard/intel/camelbackmountain_fsp/Kconfig b/src/mainboard/intel/camelbackmountain_fsp/Kconfig deleted file mode 100644 index 696fbf440c..0000000000 --- a/src/mainboard/intel/camelbackmountain_fsp/Kconfig +++ /dev/null @@ -1,41 +0,0 @@ -if BOARD_INTEL_CAMELBACKMOUNTAIN_FSP - -config BOARD_SPECIFIC_OPTIONS - def_bool y - select SOC_INTEL_FSP_BROADWELL_DE - select BOARD_ROMSIZE_KB_2048 - select HAVE_ACPI_TABLES - select HAVE_OPTION_TABLE - select INTEGRATED_UART if FSP_PACKAGE_DEFAULT - select HAVE_FSP_BIN if FSP_PACKAGE_DEFAULT - select SERIRQ_CONTINUOUS_MODE - select MAINBOARD_USES_IFD_GBE_REGION - -config MAINBOARD_DIR - string - default "intel/camelbackmountain_fsp" - -config MAINBOARD_PART_NUMBER - string - default "Camelback Mountain CRB" - -config IRQ_SLOT_COUNT - int - default 18 - -config CBFS_SIZE - hex - default 0x00200000 - -config VIRTUAL_ROM_SIZE - hex - default 0x1000000 - -config DRIVERS_UART_8250IO - def_bool n - -config FSP_PACKAGE_DEFAULT - bool "Configure defaults for the Intel FSP package" - default n - -endif # BOARD_INTEL_CAMELBACKMOUNTAIN_FSP diff --git a/src/mainboard/intel/camelbackmountain_fsp/Kconfig.name b/src/mainboard/intel/camelbackmountain_fsp/Kconfig.name deleted file mode 100644 index 3cff0156de..0000000000 --- a/src/mainboard/intel/camelbackmountain_fsp/Kconfig.name +++ /dev/null @@ -1,2 +0,0 @@ -config BOARD_INTEL_CAMELBACKMOUNTAIN_FSP - bool "Camelback Mountain FSP-based CRB" diff --git a/src/mainboard/intel/camelbackmountain_fsp/Makefile.inc b/src/mainboard/intel/camelbackmountain_fsp/Makefile.inc deleted file mode 100644 index 1606476d80..0000000000 --- a/src/mainboard/intel/camelbackmountain_fsp/Makefile.inc +++ /dev/null @@ -1,16 +0,0 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2012 Google Inc. -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; version 2 of the License. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## - -ramstage-y += irqroute.c diff --git a/src/mainboard/intel/camelbackmountain_fsp/acpi/mainboard.asl b/src/mainboard/intel/camelbackmountain_fsp/acpi/mainboard.asl deleted file mode 100644 index 62944ef353..0000000000 --- a/src/mainboard/intel/camelbackmountain_fsp/acpi/mainboard.asl +++ /dev/null @@ -1,20 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2012 Google Inc. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -Device (PWRB) -{ - Name(_HID, EisaId("PNP0C0C")) -} diff --git a/src/mainboard/intel/camelbackmountain_fsp/acpi/platform.asl b/src/mainboard/intel/camelbackmountain_fsp/acpi/platform.asl deleted file mode 100644 index 7ffae2e6e0..0000000000 --- a/src/mainboard/intel/camelbackmountain_fsp/acpi/platform.asl +++ /dev/null @@ -1,56 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007-2009 coresystems GmbH - * Copyright (C) 2012 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -/* The APM port can be used for generating software SMIs */ - -OperationRegion (APMP, SystemIO, 0xb2, 2) -Field (APMP, ByteAcc, NoLock, Preserve) -{ - APMC, 8, // APM command - APMS, 8 // APM status -} - -/* Port 80 POST */ - -OperationRegion (POST, SystemIO, 0x80, 1) -Field (POST, ByteAcc, Lock, Preserve) -{ - DBG0, 8 -} - -Name(\APC1, Zero) // IIO IOAPIC - -Name(\PICM, Zero) // IOAPIC/8259 - -Method(_PIC, 1) -{ - Store(Arg0, PICM) -} - -/* The _PTS method (Prepare To Sleep) is called before the OS is - * entering a sleep state. The sleep state number is passed in Arg0 - */ - -Method(_PTS,1) -{ -} - -/* The _WAK method is called on system wakeup */ - -Method(_WAK,1) -{ - Return(Package(){0,0}) -} diff --git a/src/mainboard/intel/camelbackmountain_fsp/acpi_tables.c b/src/mainboard/intel/camelbackmountain_fsp/acpi_tables.c deleted file mode 100644 index 3c8d2e8afc..0000000000 --- a/src/mainboard/intel/camelbackmountain_fsp/acpi_tables.c +++ /dev/null @@ -1,43 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2012 Google Inc. - * Copyright (C) 2015-2016 Intel Corp. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include - -extern const unsigned char AmlCode[]; - -unsigned long acpi_fill_madt(unsigned long current) -{ - u32 i; - - current = acpi_create_madt_lapics(current); - - current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, 8, - IOXAPIC1_BASE_ADDRESS, 0); - set_ioapic_id((u8 *)IOXAPIC1_BASE_ADDRESS, 8); - - current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, 9, - IOXAPIC2_BASE_ADDRESS, 24); - set_ioapic_id((u8 *)IOXAPIC2_BASE_ADDRESS, 9); - - current = acpi_madt_irq_overrides(current); - - for (i = 0; i < CONFIG_MAX_CPUS; i++) - current += acpi_create_madt_lapic_nmi((acpi_madt_lapic_nmi_t *)current, i, 0xD, 1); - - return current; -} diff --git a/src/mainboard/intel/camelbackmountain_fsp/board_info.txt b/src/mainboard/intel/camelbackmountain_fsp/board_info.txt deleted file mode 100644 index 680dee8e2e..0000000000 --- a/src/mainboard/intel/camelbackmountain_fsp/board_info.txt +++ /dev/null @@ -1,5 +0,0 @@ -Board name: Camelback Mountain -Category: eval -ROM protocol: SPI -ROM socketed: yes -Release year: 2015 diff --git a/src/mainboard/intel/camelbackmountain_fsp/cmos.layout b/src/mainboard/intel/camelbackmountain_fsp/cmos.layout deleted file mode 100644 index 3c5bc3b03d..0000000000 --- a/src/mainboard/intel/camelbackmountain_fsp/cmos.layout +++ /dev/null @@ -1,119 +0,0 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2007-2008 coresystems GmbH -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; version 2 of the License. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## - -# ----------------------------------------------------------------- -entries - -#start-bit length config config-ID name -#0 8 r 0 seconds -#8 8 r 0 alarm_seconds -#16 8 r 0 minutes -#24 8 r 0 alarm_minutes -#32 8 r 0 hours -#40 8 r 0 alarm_hours -#48 8 r 0 day_of_week -#56 8 r 0 day_of_month -#64 8 r 0 month -#72 8 r 0 year -# ----------------------------------------------------------------- -# Status Register A -#80 4 r 0 rate_select -#84 3 r 0 REF_Clock -#87 1 r 0 UIP -# ----------------------------------------------------------------- -# Status Register B -#88 1 r 0 auto_switch_DST -#89 1 r 0 24_hour_mode -#90 1 r 0 binary_values_enable -#91 1 r 0 square-wave_out_enable -#92 1 r 0 update_finished_enable -#93 1 r 0 alarm_interrupt_enable -#94 1 r 0 periodic_interrupt_enable -#95 1 r 0 disable_clock_updates -# ----------------------------------------------------------------- -# Status Register C -#96 4 r 0 status_c_rsvd -#100 1 r 0 uf_flag -#101 1 r 0 af_flag -#102 1 r 0 pf_flag -#103 1 r 0 irqf_flag -# ----------------------------------------------------------------- -# Status Register D -#104 7 r 0 status_d_rsvd -#111 1 r 0 valid_cmos_ram -# ----------------------------------------------------------------- -# Diagnostic Status Register -#112 8 r 0 diag_rsvd1 - -# ----------------------------------------------------------------- -0 120 r 0 reserved_memory -#120 264 r 0 unused - -# ----------------------------------------------------------------- -# RTC_BOOT_BYTE (coreboot hardcoded) -384 1 e 4 boot_option -388 4 h 0 reboot_counter -#390 2 r 0 unused? - -# ----------------------------------------------------------------- -# coreboot config options: console -#392 3 r 0 unused -395 4 e 6 debug_level -#399 1 r 0 unused - -# coreboot config options: cpu -400 1 e 2 hyper_threading -#401 7 r 0 unused - -# coreboot config options: southbridge -408 1 e 1 nmi -409 2 e 7 power_on_after_fail -#411 5 r 0 unused - -# MRC Scrambler Seed values -896 32 r 0 mrc_scrambler_seed -928 32 r 0 mrc_scrambler_seed_s3 - -# coreboot config options: check sums -984 16 h 0 check_sum -#1000 24 r 0 amd_reserved - -# ----------------------------------------------------------------- - -enumerations - -#ID value text -1 0 Disable -1 1 Enable -2 0 Enable -2 1 Disable -4 0 Fallback -4 1 Normal -6 0 Emergency -6 1 Alert -6 2 Critical -6 3 Error -6 4 Warning -6 5 Notice -6 6 Info -6 7 Debug -6 8 Spew -7 0 Disable -7 1 Enable -7 2 Keep -# ----------------------------------------------------------------- -checksums - -checksum 392 415 984 diff --git a/src/mainboard/intel/camelbackmountain_fsp/devicetree.cb b/src/mainboard/intel/camelbackmountain_fsp/devicetree.cb deleted file mode 100644 index 30d99c22eb..0000000000 --- a/src/mainboard/intel/camelbackmountain_fsp/devicetree.cb +++ /dev/null @@ -1,15 +0,0 @@ -chip soc/intel/fsp_broadwell_de - device cpu_cluster 0 on - device lapic 0 on end - end - device domain 0 on - device pci 00.0 on end # SoC router - device pci 14.0 on end # xHCI Controller - device pci 19.0 on end # Gigabit LAN Controller - device pci 1d.0 on end # EHCI Controller - device pci 1f.0 on end # LPC Bridge - device pci 1f.2 on end # SATA Controller - device pci 1f.3 on end # SMBus Controller - device pci 1f.5 on end # SATA Controller - end -end diff --git a/src/mainboard/intel/camelbackmountain_fsp/dsdt.asl b/src/mainboard/intel/camelbackmountain_fsp/dsdt.asl deleted file mode 100644 index 1248703266..0000000000 --- a/src/mainboard/intel/camelbackmountain_fsp/dsdt.asl +++ /dev/null @@ -1,294 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007-2009 coresystems GmbH - * Copyright (C) 2011 Google Inc. - * Copyright (C) 2015-2016 Intel Corp. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -DefinitionBlock( - "dsdt.aml", - "DSDT", - 0x02, // DSDT revision: ACPI v2.0 and up - OEM_ID, - ACPI_TABLE_CREATOR, - 0x20110725 // OEM revision -) -{ - #include "acpi/platform.asl" - - Name(_S0, Package() { 0x00, 0x00, 0x00, 0x00 }) - Name(_S5, Package() { 0x07, 0x00, 0x00, 0x00 }) - - Scope (\_SB) - { - Device (PCI0) - { - #include - #include - } - - Name (PRUN, Package() { - Package() { 0x0008FFFF, 0, \_SB.PCI0.LPC0.LNKA, 0 }, - Package() { 0x0008FFFF, 1, \_SB.PCI0.LPC0.LNKB, 0 }, - Package() { 0x0008FFFF, 2, \_SB.PCI0.LPC0.LNKC, 0 }, - Package() { 0x0008FFFF, 3, \_SB.PCI0.LPC0.LNKD, 0 }, - - Package() { 0x0009FFFF, 0, \_SB.PCI0.LPC0.LNKA, 0 }, - Package() { 0x0009FFFF, 1, \_SB.PCI0.LPC0.LNKB, 0 }, - Package() { 0x0009FFFF, 2, \_SB.PCI0.LPC0.LNKC, 0 }, - Package() { 0x0009FFFF, 3, \_SB.PCI0.LPC0.LNKD, 0 }, - - Package() { 0x000AFFFF, 0, \_SB.PCI0.LPC0.LNKA, 0 }, - Package() { 0x000AFFFF, 1, \_SB.PCI0.LPC0.LNKB, 0 }, - Package() { 0x000AFFFF, 2, \_SB.PCI0.LPC0.LNKC, 0 }, - Package() { 0x000AFFFF, 3, \_SB.PCI0.LPC0.LNKD, 0 }, - - Package() { 0x000BFFFF, 0, \_SB.PCI0.LPC0.LNKA, 0 }, - Package() { 0x000BFFFF, 1, \_SB.PCI0.LPC0.LNKB, 0 }, - Package() { 0x000BFFFF, 2, \_SB.PCI0.LPC0.LNKC, 0 }, - Package() { 0x000BFFFF, 3, \_SB.PCI0.LPC0.LNKD, 0 }, - - Package() { 0x000CFFFF, 0, \_SB.PCI0.LPC0.LNKA, 0 }, - Package() { 0x000CFFFF, 1, \_SB.PCI0.LPC0.LNKB, 0 }, - Package() { 0x000CFFFF, 2, \_SB.PCI0.LPC0.LNKC, 0 }, - Package() { 0x000CFFFF, 3, \_SB.PCI0.LPC0.LNKD, 0 }, - - Package() { 0x000DFFFF, 0, \_SB.PCI0.LPC0.LNKA, 0 }, - Package() { 0x000DFFFF, 1, \_SB.PCI0.LPC0.LNKB, 0 }, - Package() { 0x000DFFFF, 2, \_SB.PCI0.LPC0.LNKC, 0 }, - Package() { 0x000DFFFF, 3, \_SB.PCI0.LPC0.LNKD, 0 }, - - Package() { 0x000EFFFF, 0, \_SB.PCI0.LPC0.LNKA, 0 }, - Package() { 0x000EFFFF, 1, \_SB.PCI0.LPC0.LNKB, 0 }, - Package() { 0x000EFFFF, 2, \_SB.PCI0.LPC0.LNKC, 0 }, - Package() { 0x000EFFFF, 3, \_SB.PCI0.LPC0.LNKD, 0 }, - - Package() { 0x000FFFFF, 0, \_SB.PCI0.LPC0.LNKA, 0 }, - Package() { 0x000FFFFF, 1, \_SB.PCI0.LPC0.LNKB, 0 }, - Package() { 0x000FFFFF, 2, \_SB.PCI0.LPC0.LNKC, 0 }, - Package() { 0x000FFFFF, 3, \_SB.PCI0.LPC0.LNKD, 0 }, - - Package() { 0x0010FFFF, 0, \_SB.PCI0.LPC0.LNKA, 0 }, - Package() { 0x0010FFFF, 1, \_SB.PCI0.LPC0.LNKB, 0 }, - Package() { 0x0010FFFF, 2, \_SB.PCI0.LPC0.LNKC, 0 }, - Package() { 0x0010FFFF, 3, \_SB.PCI0.LPC0.LNKD, 0 }, - - Package() { 0x0011FFFF, 0, \_SB.PCI0.LPC0.LNKA, 0 }, - Package() { 0x0011FFFF, 1, \_SB.PCI0.LPC0.LNKB, 0 }, - Package() { 0x0011FFFF, 2, \_SB.PCI0.LPC0.LNKC, 0 }, - Package() { 0x0011FFFF, 3, \_SB.PCI0.LPC0.LNKD, 0 }, - - Package() { 0x0012FFFF, 0, \_SB.PCI0.LPC0.LNKA, 0 }, - Package() { 0x0012FFFF, 1, \_SB.PCI0.LPC0.LNKB, 0 }, - Package() { 0x0012FFFF, 2, \_SB.PCI0.LPC0.LNKC, 0 }, - Package() { 0x0012FFFF, 3, \_SB.PCI0.LPC0.LNKD, 0 }, - - Package() { 0x0013FFFF, 0, \_SB.PCI0.LPC0.LNKA, 0 }, - Package() { 0x0013FFFF, 1, \_SB.PCI0.LPC0.LNKB, 0 }, - Package() { 0x0013FFFF, 2, \_SB.PCI0.LPC0.LNKC, 0 }, - Package() { 0x0013FFFF, 3, \_SB.PCI0.LPC0.LNKD, 0 }, - - Package() { 0x0014FFFF, 0, \_SB.PCI0.LPC0.LNKA, 0 }, - Package() { 0x0014FFFF, 1, \_SB.PCI0.LPC0.LNKB, 0 }, - Package() { 0x0014FFFF, 2, \_SB.PCI0.LPC0.LNKC, 0 }, - Package() { 0x0014FFFF, 3, \_SB.PCI0.LPC0.LNKD, 0 }, - - Package() { 0x0016FFFF, 0, \_SB.PCI0.LPC0.LNKA, 0 }, - Package() { 0x0016FFFF, 1, \_SB.PCI0.LPC0.LNKB, 0 }, - Package() { 0x0016FFFF, 2, \_SB.PCI0.LPC0.LNKC, 0 }, - Package() { 0x0016FFFF, 3, \_SB.PCI0.LPC0.LNKD, 0 }, - - Package() { 0x0017FFFF, 0, \_SB.PCI0.LPC0.LNKA, 0 }, - Package() { 0x0017FFFF, 1, \_SB.PCI0.LPC0.LNKB, 0 }, - Package() { 0x0017FFFF, 2, \_SB.PCI0.LPC0.LNKC, 0 }, - Package() { 0x0017FFFF, 3, \_SB.PCI0.LPC0.LNKD, 0 }, - - Package() { 0x0018FFFF, 0, \_SB.PCI0.LPC0.LNKA, 0 }, - Package() { 0x0018FFFF, 1, \_SB.PCI0.LPC0.LNKB, 0 }, - Package() { 0x0018FFFF, 2, \_SB.PCI0.LPC0.LNKC, 0 }, - Package() { 0x0018FFFF, 3, \_SB.PCI0.LPC0.LNKD, 0 }, - - Package() { 0x0019FFFF, 0, \_SB.PCI0.LPC0.LNKA, 0 }, - Package() { 0x0019FFFF, 1, \_SB.PCI0.LPC0.LNKB, 0 }, - Package() { 0x0019FFFF, 2, \_SB.PCI0.LPC0.LNKC, 0 }, - Package() { 0x0019FFFF, 3, \_SB.PCI0.LPC0.LNKD, 0 }, - - Package() { 0x001CFFFF, 0, \_SB.PCI0.LPC0.LNKA, 0 }, - Package() { 0x001CFFFF, 1, \_SB.PCI0.LPC0.LNKB, 0 }, - Package() { 0x001CFFFF, 2, \_SB.PCI0.LPC0.LNKC, 0 }, - Package() { 0x001CFFFF, 3, \_SB.PCI0.LPC0.LNKD, 0 }, - - Package() { 0x001DFFFF, 0, \_SB.PCI0.LPC0.LNKA, 0 }, - Package() { 0x001DFFFF, 1, \_SB.PCI0.LPC0.LNKB, 0 }, - Package() { 0x001DFFFF, 2, \_SB.PCI0.LPC0.LNKC, 0 }, - Package() { 0x001DFFFF, 3, \_SB.PCI0.LPC0.LNKD, 0 }, - - Package() { 0x001EFFFF, 0, \_SB.PCI0.LPC0.LNKA, 0 }, - Package() { 0x001EFFFF, 1, \_SB.PCI0.LPC0.LNKB, 0 }, - Package() { 0x001EFFFF, 2, \_SB.PCI0.LPC0.LNKC, 0 }, - Package() { 0x001EFFFF, 3, \_SB.PCI0.LPC0.LNKD, 0 }, - - Package() { 0x001FFFFF, 0, \_SB.PCI0.LPC0.LNKA, 0 }, - Package() { 0x001FFFFF, 1, \_SB.PCI0.LPC0.LNKB, 0 }, - Package() { 0x001FFFFF, 2, \_SB.PCI0.LPC0.LNKC, 0 }, - Package() { 0x001FFFFF, 3, \_SB.PCI0.LPC0.LNKD, 0 }, - }) - - Name (ARUN, Package() { - Package() { 0x0008FFFF, 0, 0, 16 }, - Package() { 0x0008FFFF, 1, 0, 17 }, - Package() { 0x0008FFFF, 2, 0, 18 }, - Package() { 0x0008FFFF, 3, 0, 19 }, - - Package() { 0x0009FFFF, 0, 0, 16 }, - Package() { 0x0009FFFF, 1, 0, 17 }, - Package() { 0x0009FFFF, 2, 0, 18 }, - Package() { 0x0009FFFF, 3, 0, 19 }, - - Package() { 0x000AFFFF, 0, 0, 16 }, - Package() { 0x000AFFFF, 1, 0, 17 }, - Package() { 0x000AFFFF, 2, 0, 18 }, - Package() { 0x000AFFFF, 3, 0, 19 }, - - Package() { 0x000BFFFF, 0, 0, 16 }, - Package() { 0x000BFFFF, 1, 0, 17 }, - Package() { 0x000BFFFF, 2, 0, 18 }, - Package() { 0x000BFFFF, 3, 0, 19 }, - - Package() { 0x000CFFFF, 0, 0, 16 }, - Package() { 0x000CFFFF, 1, 0, 17 }, - Package() { 0x000CFFFF, 2, 0, 18 }, - Package() { 0x000CFFFF, 3, 0, 19 }, - - Package() { 0x000DFFFF, 0, 0, 16 }, - Package() { 0x000DFFFF, 1, 0, 17 }, - Package() { 0x000DFFFF, 2, 0, 18 }, - Package() { 0x000DFFFF, 3, 0, 19 }, - - Package() { 0x000EFFFF, 0, 0, 16 }, - Package() { 0x000EFFFF, 1, 0, 17 }, - Package() { 0x000EFFFF, 2, 0, 18 }, - Package() { 0x000EFFFF, 3, 0, 19 }, - - Package() { 0x000FFFFF, 0, 0, 16 }, - Package() { 0x000FFFFF, 1, 0, 17 }, - Package() { 0x000FFFFF, 2, 0, 18 }, - Package() { 0x000FFFFF, 3, 0, 19 }, - - Package() { 0x0010FFFF, 0, 0, 16 }, - Package() { 0x0010FFFF, 1, 0, 17 }, - Package() { 0x0010FFFF, 2, 0, 18 }, - Package() { 0x0010FFFF, 3, 0, 19 }, - - Package() { 0x0011FFFF, 0, 0, 16 }, - Package() { 0x0011FFFF, 1, 0, 17 }, - Package() { 0x0011FFFF, 2, 0, 18 }, - Package() { 0x0011FFFF, 3, 0, 19 }, - - Package() { 0x0012FFFF, 0, 0, 16 }, - Package() { 0x0012FFFF, 1, 0, 17 }, - Package() { 0x0012FFFF, 2, 0, 18 }, - Package() { 0x0012FFFF, 3, 0, 19 }, - - Package() { 0x0013FFFF, 0, 0, 16 }, - Package() { 0x0013FFFF, 1, 0, 17 }, - Package() { 0x0013FFFF, 2, 0, 18 }, - Package() { 0x0013FFFF, 3, 0, 19 }, - - Package() { 0x0014FFFF, 0, 0, 16 }, - Package() { 0x0014FFFF, 1, 0, 17 }, - Package() { 0x0014FFFF, 2, 0, 18 }, - Package() { 0x0014FFFF, 3, 0, 19 }, - - Package() { 0x0016FFFF, 0, 0, 16 }, - Package() { 0x0016FFFF, 1, 0, 17 }, - Package() { 0x0016FFFF, 2, 0, 18 }, - Package() { 0x0016FFFF, 3, 0, 19 }, - - Package() { 0x0017FFFF, 0, 0, 16 }, - Package() { 0x0017FFFF, 1, 0, 17 }, - Package() { 0x0017FFFF, 2, 0, 18 }, - Package() { 0x0017FFFF, 3, 0, 19 }, - - Package() { 0x0018FFFF, 0, 0, 16 }, - Package() { 0x0018FFFF, 1, 0, 17 }, - Package() { 0x0018FFFF, 2, 0, 18 }, - Package() { 0x0018FFFF, 3, 0, 19 }, - - Package() { 0x0019FFFF, 0, 0, 16 }, - Package() { 0x0019FFFF, 1, 0, 17 }, - Package() { 0x0019FFFF, 2, 0, 18 }, - Package() { 0x0019FFFF, 3, 0, 19 }, - - Package() { 0x001CFFFF, 0, 0, 16 }, - Package() { 0x001CFFFF, 1, 0, 17 }, - Package() { 0x001CFFFF, 2, 0, 18 }, - Package() { 0x001CFFFF, 3, 0, 19 }, - - Package() { 0x001DFFFF, 0, 0, 16 }, - Package() { 0x001DFFFF, 1, 0, 17 }, - Package() { 0x001DFFFF, 2, 0, 18 }, - Package() { 0x001DFFFF, 3, 0, 19 }, - - Package() { 0x001EFFFF, 0, 0, 16 }, - Package() { 0x001EFFFF, 1, 0, 17 }, - Package() { 0x001EFFFF, 2, 0, 18 }, - Package() { 0x001EFFFF, 3, 0, 19 }, - - Package() { 0x001FFFFF, 0, 0, 16 }, - Package() { 0x001FFFFF, 1, 0, 17 }, - Package() { 0x001FFFFF, 2, 0, 18 }, - Package() { 0x001FFFFF, 3, 0, 19 }, - }) - - Device (UNC0) - { - Name (_HID, EisaId ("PNP0A03")) - Name (_UID, 0x3F) - Method (_BBN, 0, NotSerialized) - { - Return (0xff) - } - - Name (_ADR, 0x00) - Method (_STA, 0, NotSerialized) - { - Return (0xf) - } - - Name (_CRS, ResourceTemplate () - { - WordBusNumber (ResourceProducer, MinFixed, MaxFixed, PosDecode, - 0x0000, // Granularity - 0x00FF, // Range Minimum - 0x00FF, // Range Maximum - 0x0000, // Translation Offset - 0x0001, // Length - ,, ) - }) - - Method (_PRT, 0, NotSerialized) - { - If (LEqual (PICM, Zero)) - { - Return (PRUN) - } - - Return (ARUN) - } - } - } - - #include "acpi/mainboard.asl" -} diff --git a/src/mainboard/intel/camelbackmountain_fsp/fadt.c b/src/mainboard/intel/camelbackmountain_fsp/fadt.c deleted file mode 100644 index 5af6056b49..0000000000 --- a/src/mainboard/intel/camelbackmountain_fsp/fadt.c +++ /dev/null @@ -1,27 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007-2009 coresystems GmbH - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include - -void acpi_create_fadt(acpi_fadt_t *fadt, acpi_facs_t *facs, void *dsdt) -{ - acpi_header_t *header = &(fadt->header); - - acpi_fill_in_fadt(fadt, facs, dsdt); - - /* Platform specific customizations go here */ - - header->checksum = acpi_checksum((void *) fadt, sizeof(acpi_fadt_t)); -} diff --git a/src/mainboard/intel/camelbackmountain_fsp/irqroute.c b/src/mainboard/intel/camelbackmountain_fsp/irqroute.c deleted file mode 100644 index f91cf0d5b3..0000000000 --- a/src/mainboard/intel/camelbackmountain_fsp/irqroute.c +++ /dev/null @@ -1,18 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2012 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include "irqroute.h" - -DEFINE_IRQ_ROUTES; diff --git a/src/mainboard/intel/camelbackmountain_fsp/irqroute.h b/src/mainboard/intel/camelbackmountain_fsp/irqroute.h deleted file mode 100644 index c3911be75b..0000000000 --- a/src/mainboard/intel/camelbackmountain_fsp/irqroute.h +++ /dev/null @@ -1,48 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2012 Google Inc. - * Copyright (C) 2015-2016 Intel Corp. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef IRQROUTE_H -#define IRQROUTE_H - -#include -#include - -#define PCI_DEV_PIRQ_ROUTES \ - PCI_DEV_PIRQ_ROUTE(XHCI_DEV, A, B, C, D), \ - PCI_DEV_PIRQ_ROUTE(ME_DEV, A, B, C, D), \ - PCI_DEV_PIRQ_ROUTE(GBE_DEV, A, B, C, D), \ - PCI_DEV_PIRQ_ROUTE(EHCI2_DEV, A, B, C, D), \ - PCI_DEV_PIRQ_ROUTE(HDA_DEV, A, B, C, D), \ - PCI_DEV_PIRQ_ROUTE(PCIE_DEV, A, B, C, D), \ - PCI_DEV_PIRQ_ROUTE(EHCI1_DEV, A, B, C, D), \ - PCI_DEV_PIRQ_ROUTE(SATA_DEV, A, B, C, D) - -/* - * Route each PIRQ[A-H] to a PIC IRQ[0-15] - * Reserved: 0, 1, 2, 8, 13 - * ACPI/SCI: 9 - */ -#define PIRQ_PIC_ROUTES \ - PIRQ_PIC(A, 5), \ - PIRQ_PIC(B, 6), \ - PIRQ_PIC(C, 7), \ - PIRQ_PIC(D, 10), \ - PIRQ_PIC(E, 11), \ - PIRQ_PIC(F, 12), \ - PIRQ_PIC(G, 14), \ - PIRQ_PIC(H, 15) - -#endif /* IRQROUTE_H */ diff --git a/src/mainboard/intel/camelbackmountain_fsp/mainboard.c b/src/mainboard/intel/camelbackmountain_fsp/mainboard.c deleted file mode 100644 index 29f98f46c0..0000000000 --- a/src/mainboard/intel/camelbackmountain_fsp/mainboard.c +++ /dev/null @@ -1,35 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007-2009 coresystems GmbH - * Copyright (C) 2011 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include -#if CONFIG(VGA_ROM_RUN) -#include -#endif - -/* - * mainboard_enable is executed as first thing after enumerate_buses(). - * This is the earliest point to add customization. - */ -static void mainboard_enable(struct device *dev) -{ - -} - -struct chip_operations mainboard_ops = { - .enable_dev = mainboard_enable, -}; diff --git a/src/mainboard/intel/camelbackmountain_fsp/romstage.c b/src/mainboard/intel/camelbackmountain_fsp/romstage.c deleted file mode 100644 index cf52c01f04..0000000000 --- a/src/mainboard/intel/camelbackmountain_fsp/romstage.c +++ /dev/null @@ -1,45 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2013 Google Inc. - * Copyright (C) 2015 Intel Corp. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include - -/** - * /brief mainboard call for setup that needs to be done before fsp init - * - */ -void early_mainboard_romstage_entry(void) -{ - -} - -/** - * /brief mainboard call for setup that needs to be done after fsp init - * - */ -void late_mainboard_romstage_entry(void) -{ - -} - -/** - * /brief customize fsp parameters here if needed - */ -void romstage_fsp_rt_buffer_callback(FSP_INIT_RT_BUFFER *FspRtBuffer) -{ - -} diff --git a/src/mainboard/ocp/Kconfig b/src/mainboard/ocp/Kconfig deleted file mode 100644 index b748129e81..0000000000 --- a/src/mainboard/ocp/Kconfig +++ /dev/null @@ -1,16 +0,0 @@ -if VENDOR_OCP - -choice - prompt "Mainboard model" - -source "src/mainboard/ocp/*/Kconfig.name" - -endchoice - -source "src/mainboard/ocp/*/Kconfig" - -config MAINBOARD_VENDOR - string - default "Open Compute Project" - -endif # VENDOR_OCP diff --git a/src/mainboard/ocp/Kconfig.name b/src/mainboard/ocp/Kconfig.name deleted file mode 100644 index f5d8d0a8eb..0000000000 --- a/src/mainboard/ocp/Kconfig.name +++ /dev/null @@ -1,2 +0,0 @@ -config VENDOR_OCP - bool "Open Compute Project" diff --git a/src/mainboard/ocp/monolake/Kconfig b/src/mainboard/ocp/monolake/Kconfig deleted file mode 100644 index 7d85bbba70..0000000000 --- a/src/mainboard/ocp/monolake/Kconfig +++ /dev/null @@ -1,63 +0,0 @@ -if BOARD_OCP_MONOLAKE - -config BOARD_SPECIFIC_OPTIONS - def_bool y - select SOC_INTEL_FSP_BROADWELL_DE - select BOARD_ROMSIZE_KB_16384 - select HAVE_ACPI_TABLES - select HAVE_OPTION_TABLE - select INTEGRATED_UART if FSP_PACKAGE_DEFAULT - select HAVE_FSP_BIN if FSP_PACKAGE_DEFAULT - select SERIRQ_CONTINUOUS_MODE - select MAINBOARD_USES_IFD_GBE_REGION - select MAINBOARD_HAS_LPC_TPM - select MAINBOARD_HAS_TPM1 - select IPMI_KCS - select VPD - -config VBOOT - select VBOOT_VBNV_CMOS - select VBOOT_NO_BOARD_SUPPORT - select GBB_FLAG_DISABLE_LID_SHUTDOWN - select GBB_FLAG_DISABLE_PD_SOFTWARE_SYNC - select GBB_FLAG_DISABLE_EC_SOFTWARE_SYNC - select GBB_FLAG_DISABLE_FWMP - -config INTEGRATED_UART - def_bool n - -config MAINBOARD_DIR - string - default "ocp/monolake" - -config MAINBOARD_PART_NUMBER - string - default "Mono Lake" - -config IRQ_SLOT_COUNT - int - default 18 - -config CBFS_SIZE - hex - default 0x00200000 - -config VIRTUAL_ROM_SIZE - hex - default 0x1000000 - -config DRIVERS_UART_8250IO - def_bool n - -config FSP_PACKAGE_DEFAULT - bool "Configure defaults for the Intel FSP package" - default n - -config FMDFILE - string - default "src/mainboard/$(CONFIG_MAINBOARD_DIR)/board.fmd" - -config IPMI_KCS_REGISTER_SPACING - default 4 - -endif # BOARD_OCP_MONOLAKE diff --git a/src/mainboard/ocp/monolake/Kconfig.name b/src/mainboard/ocp/monolake/Kconfig.name deleted file mode 100644 index d8284257d8..0000000000 --- a/src/mainboard/ocp/monolake/Kconfig.name +++ /dev/null @@ -1,2 +0,0 @@ -config BOARD_OCP_MONOLAKE - bool "Mono Lake" diff --git a/src/mainboard/ocp/monolake/Makefile.inc b/src/mainboard/ocp/monolake/Makefile.inc deleted file mode 100644 index b6a26b0147..0000000000 --- a/src/mainboard/ocp/monolake/Makefile.inc +++ /dev/null @@ -1,17 +0,0 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2012 Google Inc. -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; version 2 of the License. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## - -ramstage-y += irqroute.c -ramstage-y += ipmi.c diff --git a/src/mainboard/ocp/monolake/acpi/mainboard.asl b/src/mainboard/ocp/monolake/acpi/mainboard.asl deleted file mode 100644 index 62944ef353..0000000000 --- a/src/mainboard/ocp/monolake/acpi/mainboard.asl +++ /dev/null @@ -1,20 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2012 Google Inc. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -Device (PWRB) -{ - Name(_HID, EisaId("PNP0C0C")) -} diff --git a/src/mainboard/ocp/monolake/acpi/platform.asl b/src/mainboard/ocp/monolake/acpi/platform.asl deleted file mode 100644 index 7ffae2e6e0..0000000000 --- a/src/mainboard/ocp/monolake/acpi/platform.asl +++ /dev/null @@ -1,56 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007-2009 coresystems GmbH - * Copyright (C) 2012 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -/* The APM port can be used for generating software SMIs */ - -OperationRegion (APMP, SystemIO, 0xb2, 2) -Field (APMP, ByteAcc, NoLock, Preserve) -{ - APMC, 8, // APM command - APMS, 8 // APM status -} - -/* Port 80 POST */ - -OperationRegion (POST, SystemIO, 0x80, 1) -Field (POST, ByteAcc, Lock, Preserve) -{ - DBG0, 8 -} - -Name(\APC1, Zero) // IIO IOAPIC - -Name(\PICM, Zero) // IOAPIC/8259 - -Method(_PIC, 1) -{ - Store(Arg0, PICM) -} - -/* The _PTS method (Prepare To Sleep) is called before the OS is - * entering a sleep state. The sleep state number is passed in Arg0 - */ - -Method(_PTS,1) -{ -} - -/* The _WAK method is called on system wakeup */ - -Method(_WAK,1) -{ - Return(Package(){0,0}) -} diff --git a/src/mainboard/ocp/monolake/acpi_tables.c b/src/mainboard/ocp/monolake/acpi_tables.c deleted file mode 100644 index 0197def7a7..0000000000 --- a/src/mainboard/ocp/monolake/acpi_tables.c +++ /dev/null @@ -1,43 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2012 Google Inc. - * Copyright (C) 2015-2016 Intel Corp. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include - -extern const unsigned char AmlCode[]; - -unsigned long acpi_fill_madt(unsigned long current) -{ - u32 i; - - current = acpi_create_madt_lapics(current); - - current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, 8, - IOXAPIC1_BASE_ADDRESS, 0); - set_ioapic_id((u8 *)IOXAPIC1_BASE_ADDRESS, 8); - - current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, 9, - IOXAPIC2_BASE_ADDRESS, 24); - set_ioapic_id((u8 *)IOXAPIC2_BASE_ADDRESS, 9); - - current = acpi_madt_irq_overrides(current); - - for (i = 0; i < 16; i++) - current += acpi_create_madt_lapic_nmi((acpi_madt_lapic_nmi_t *)current, i, 0xD, 1); - - return current; -} diff --git a/src/mainboard/ocp/monolake/board.fmd b/src/mainboard/ocp/monolake/board.fmd deleted file mode 100644 index d0265e464d..0000000000 --- a/src/mainboard/ocp/monolake/board.fmd +++ /dev/null @@ -1,22 +0,0 @@ -FLASH@0xff000000 0x1000000 { - SI_ALL@0x0 0x800000 { - SI_DESC@0x0 0x1000 - SI_ME@0x1000 0x7ff000 - } - SI_BIOS@0x800000 0x800000 { - FMAP@0x0 0x1000 - RW_MISC@0x1000 0x9000 { - RW_ELOG@0x0 0x4000 - RW_VPD@0x4000 0x2000 - RW_NVRAM@0x6000 0x2000 - } - UNUSED@0xa000 0x4000 { - # This only exists to satisfy tools that - # specifically look for RO_VPD. - RO_VPD@0x0 0x4000 - } - RW_MRC_CACHE@0xE000 0x10000 - CONSOLE@0x1E000 0x10000 - COREBOOT(CBFS)@0x2E000 0x7d2000 - } -} diff --git a/src/mainboard/ocp/monolake/board_info.txt b/src/mainboard/ocp/monolake/board_info.txt deleted file mode 100644 index 22c62cafd7..0000000000 --- a/src/mainboard/ocp/monolake/board_info.txt +++ /dev/null @@ -1,5 +0,0 @@ -Board name: Mono Lake -Category: server -ROM protocol: SPI -ROM socketed: yes -Release year: 2016 diff --git a/src/mainboard/ocp/monolake/cmos.layout b/src/mainboard/ocp/monolake/cmos.layout deleted file mode 100644 index 3aaa56b569..0000000000 --- a/src/mainboard/ocp/monolake/cmos.layout +++ /dev/null @@ -1,120 +0,0 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2007-2008 coresystems GmbH -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; version 2 of the License. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## - -# ----------------------------------------------------------------- -entries - -#start-bit length config config-ID name -#0 8 r 0 seconds -#8 8 r 0 alarm_seconds -#16 8 r 0 minutes -#24 8 r 0 alarm_minutes -#32 8 r 0 hours -#40 8 r 0 alarm_hours -#48 8 r 0 day_of_week -#56 8 r 0 day_of_month -#64 8 r 0 month -#72 8 r 0 year -# ----------------------------------------------------------------- -# Status Register A -#80 4 r 0 rate_select -#84 3 r 0 REF_Clock -#87 1 r 0 UIP -# ----------------------------------------------------------------- -# Status Register B -#88 1 r 0 auto_switch_DST -#89 1 r 0 24_hour_mode -#90 1 r 0 binary_values_enable -#91 1 r 0 square-wave_out_enable -#92 1 r 0 update_finished_enable -#93 1 r 0 alarm_interrupt_enable -#94 1 r 0 periodic_interrupt_enable -#95 1 r 0 disable_clock_updates -# ----------------------------------------------------------------- -# Status Register C -#96 4 r 0 status_c_rsvd -#100 1 r 0 uf_flag -#101 1 r 0 af_flag -#102 1 r 0 pf_flag -#103 1 r 0 irqf_flag -# ----------------------------------------------------------------- -# Status Register D -#104 7 r 0 status_d_rsvd -#111 1 r 0 valid_cmos_ram -# ----------------------------------------------------------------- -# Diagnostic Status Register -#112 8 r 0 diag_rsvd1 - -# ----------------------------------------------------------------- -0 120 r 0 reserved_memory -#120 264 r 0 unused - -# ----------------------------------------------------------------- -# RTC_BOOT_BYTE (coreboot hardcoded) -384 1 e 4 boot_option -388 4 h 0 reboot_counter -#390 2 r 0 unused? - -# ----------------------------------------------------------------- -# coreboot config options: console -#392 3 r 0 unused -395 4 e 6 debug_level -#399 1 r 0 unused - -# coreboot config options: cpu -400 1 e 2 hyper_threading -#401 7 r 0 unused - -# coreboot config options: southbridge -408 1 e 1 nmi -409 2 e 7 power_on_after_fail -#411 5 r 0 unused -416 128 r 0 vbnv - -# MRC Scrambler Seed values -896 32 r 0 mrc_scrambler_seed -928 32 r 0 mrc_scrambler_seed_s3 - -# coreboot config options: check sums -984 16 h 0 check_sum -#1000 24 r 0 amd_reserved - -# ----------------------------------------------------------------- - -enumerations - -#ID value text -1 0 Disable -1 1 Enable -2 0 Enable -2 1 Disable -4 0 Fallback -4 1 Normal -6 0 Emergency -6 1 Alert -6 2 Critical -6 3 Error -6 4 Warning -6 5 Notice -6 6 Info -6 7 Debug -6 8 Spew -7 0 Disable -7 1 Enable -7 2 Keep -# ----------------------------------------------------------------- -checksums - -checksum 392 415 984 diff --git a/src/mainboard/ocp/monolake/devicetree.cb b/src/mainboard/ocp/monolake/devicetree.cb deleted file mode 100644 index 26c95d5d67..0000000000 --- a/src/mainboard/ocp/monolake/devicetree.cb +++ /dev/null @@ -1,25 +0,0 @@ -chip soc/intel/fsp_broadwell_de - device cpu_cluster 0 on - device lapic 0 on end - end - device domain 0 on - device pci 00.0 on end # SoC router - device pci 02.2 off end # IOU0 port C, 10GbE - device pci 02.3 off end # IOU0 port D, 10GbE - device pci 14.0 on end # xHCI Controller - device pci 19.0 on end # Gigabit LAN Controller - device pci 1d.0 on end # EHCI Controller - device pci 1f.0 on - chip drivers/pc80/tpm - device pnp 0c31.0 on end - end - chip drivers/ipmi # BMC KCS - device pnp ca2.0 on end - register "bmc_i2c_address" = "0x20" - end - end # LPC Bridge - device pci 1f.2 on end # SATA Controller - device pci 1f.3 on end # SMBus Controller - device pci 1f.5 on end # SATA Controller - end -end diff --git a/src/mainboard/ocp/monolake/dsdt.asl b/src/mainboard/ocp/monolake/dsdt.asl deleted file mode 100644 index 1248703266..0000000000 --- a/src/mainboard/ocp/monolake/dsdt.asl +++ /dev/null @@ -1,294 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007-2009 coresystems GmbH - * Copyright (C) 2011 Google Inc. - * Copyright (C) 2015-2016 Intel Corp. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -DefinitionBlock( - "dsdt.aml", - "DSDT", - 0x02, // DSDT revision: ACPI v2.0 and up - OEM_ID, - ACPI_TABLE_CREATOR, - 0x20110725 // OEM revision -) -{ - #include "acpi/platform.asl" - - Name(_S0, Package() { 0x00, 0x00, 0x00, 0x00 }) - Name(_S5, Package() { 0x07, 0x00, 0x00, 0x00 }) - - Scope (\_SB) - { - Device (PCI0) - { - #include - #include - } - - Name (PRUN, Package() { - Package() { 0x0008FFFF, 0, \_SB.PCI0.LPC0.LNKA, 0 }, - Package() { 0x0008FFFF, 1, \_SB.PCI0.LPC0.LNKB, 0 }, - Package() { 0x0008FFFF, 2, \_SB.PCI0.LPC0.LNKC, 0 }, - Package() { 0x0008FFFF, 3, \_SB.PCI0.LPC0.LNKD, 0 }, - - Package() { 0x0009FFFF, 0, \_SB.PCI0.LPC0.LNKA, 0 }, - Package() { 0x0009FFFF, 1, \_SB.PCI0.LPC0.LNKB, 0 }, - Package() { 0x0009FFFF, 2, \_SB.PCI0.LPC0.LNKC, 0 }, - Package() { 0x0009FFFF, 3, \_SB.PCI0.LPC0.LNKD, 0 }, - - Package() { 0x000AFFFF, 0, \_SB.PCI0.LPC0.LNKA, 0 }, - Package() { 0x000AFFFF, 1, \_SB.PCI0.LPC0.LNKB, 0 }, - Package() { 0x000AFFFF, 2, \_SB.PCI0.LPC0.LNKC, 0 }, - Package() { 0x000AFFFF, 3, \_SB.PCI0.LPC0.LNKD, 0 }, - - Package() { 0x000BFFFF, 0, \_SB.PCI0.LPC0.LNKA, 0 }, - Package() { 0x000BFFFF, 1, \_SB.PCI0.LPC0.LNKB, 0 }, - Package() { 0x000BFFFF, 2, \_SB.PCI0.LPC0.LNKC, 0 }, - Package() { 0x000BFFFF, 3, \_SB.PCI0.LPC0.LNKD, 0 }, - - Package() { 0x000CFFFF, 0, \_SB.PCI0.LPC0.LNKA, 0 }, - Package() { 0x000CFFFF, 1, \_SB.PCI0.LPC0.LNKB, 0 }, - Package() { 0x000CFFFF, 2, \_SB.PCI0.LPC0.LNKC, 0 }, - Package() { 0x000CFFFF, 3, \_SB.PCI0.LPC0.LNKD, 0 }, - - Package() { 0x000DFFFF, 0, \_SB.PCI0.LPC0.LNKA, 0 }, - Package() { 0x000DFFFF, 1, \_SB.PCI0.LPC0.LNKB, 0 }, - Package() { 0x000DFFFF, 2, \_SB.PCI0.LPC0.LNKC, 0 }, - Package() { 0x000DFFFF, 3, \_SB.PCI0.LPC0.LNKD, 0 }, - - Package() { 0x000EFFFF, 0, \_SB.PCI0.LPC0.LNKA, 0 }, - Package() { 0x000EFFFF, 1, \_SB.PCI0.LPC0.LNKB, 0 }, - Package() { 0x000EFFFF, 2, \_SB.PCI0.LPC0.LNKC, 0 }, - Package() { 0x000EFFFF, 3, \_SB.PCI0.LPC0.LNKD, 0 }, - - Package() { 0x000FFFFF, 0, \_SB.PCI0.LPC0.LNKA, 0 }, - Package() { 0x000FFFFF, 1, \_SB.PCI0.LPC0.LNKB, 0 }, - Package() { 0x000FFFFF, 2, \_SB.PCI0.LPC0.LNKC, 0 }, - Package() { 0x000FFFFF, 3, \_SB.PCI0.LPC0.LNKD, 0 }, - - Package() { 0x0010FFFF, 0, \_SB.PCI0.LPC0.LNKA, 0 }, - Package() { 0x0010FFFF, 1, \_SB.PCI0.LPC0.LNKB, 0 }, - Package() { 0x0010FFFF, 2, \_SB.PCI0.LPC0.LNKC, 0 }, - Package() { 0x0010FFFF, 3, \_SB.PCI0.LPC0.LNKD, 0 }, - - Package() { 0x0011FFFF, 0, \_SB.PCI0.LPC0.LNKA, 0 }, - Package() { 0x0011FFFF, 1, \_SB.PCI0.LPC0.LNKB, 0 }, - Package() { 0x0011FFFF, 2, \_SB.PCI0.LPC0.LNKC, 0 }, - Package() { 0x0011FFFF, 3, \_SB.PCI0.LPC0.LNKD, 0 }, - - Package() { 0x0012FFFF, 0, \_SB.PCI0.LPC0.LNKA, 0 }, - Package() { 0x0012FFFF, 1, \_SB.PCI0.LPC0.LNKB, 0 }, - Package() { 0x0012FFFF, 2, \_SB.PCI0.LPC0.LNKC, 0 }, - Package() { 0x0012FFFF, 3, \_SB.PCI0.LPC0.LNKD, 0 }, - - Package() { 0x0013FFFF, 0, \_SB.PCI0.LPC0.LNKA, 0 }, - Package() { 0x0013FFFF, 1, \_SB.PCI0.LPC0.LNKB, 0 }, - Package() { 0x0013FFFF, 2, \_SB.PCI0.LPC0.LNKC, 0 }, - Package() { 0x0013FFFF, 3, \_SB.PCI0.LPC0.LNKD, 0 }, - - Package() { 0x0014FFFF, 0, \_SB.PCI0.LPC0.LNKA, 0 }, - Package() { 0x0014FFFF, 1, \_SB.PCI0.LPC0.LNKB, 0 }, - Package() { 0x0014FFFF, 2, \_SB.PCI0.LPC0.LNKC, 0 }, - Package() { 0x0014FFFF, 3, \_SB.PCI0.LPC0.LNKD, 0 }, - - Package() { 0x0016FFFF, 0, \_SB.PCI0.LPC0.LNKA, 0 }, - Package() { 0x0016FFFF, 1, \_SB.PCI0.LPC0.LNKB, 0 }, - Package() { 0x0016FFFF, 2, \_SB.PCI0.LPC0.LNKC, 0 }, - Package() { 0x0016FFFF, 3, \_SB.PCI0.LPC0.LNKD, 0 }, - - Package() { 0x0017FFFF, 0, \_SB.PCI0.LPC0.LNKA, 0 }, - Package() { 0x0017FFFF, 1, \_SB.PCI0.LPC0.LNKB, 0 }, - Package() { 0x0017FFFF, 2, \_SB.PCI0.LPC0.LNKC, 0 }, - Package() { 0x0017FFFF, 3, \_SB.PCI0.LPC0.LNKD, 0 }, - - Package() { 0x0018FFFF, 0, \_SB.PCI0.LPC0.LNKA, 0 }, - Package() { 0x0018FFFF, 1, \_SB.PCI0.LPC0.LNKB, 0 }, - Package() { 0x0018FFFF, 2, \_SB.PCI0.LPC0.LNKC, 0 }, - Package() { 0x0018FFFF, 3, \_SB.PCI0.LPC0.LNKD, 0 }, - - Package() { 0x0019FFFF, 0, \_SB.PCI0.LPC0.LNKA, 0 }, - Package() { 0x0019FFFF, 1, \_SB.PCI0.LPC0.LNKB, 0 }, - Package() { 0x0019FFFF, 2, \_SB.PCI0.LPC0.LNKC, 0 }, - Package() { 0x0019FFFF, 3, \_SB.PCI0.LPC0.LNKD, 0 }, - - Package() { 0x001CFFFF, 0, \_SB.PCI0.LPC0.LNKA, 0 }, - Package() { 0x001CFFFF, 1, \_SB.PCI0.LPC0.LNKB, 0 }, - Package() { 0x001CFFFF, 2, \_SB.PCI0.LPC0.LNKC, 0 }, - Package() { 0x001CFFFF, 3, \_SB.PCI0.LPC0.LNKD, 0 }, - - Package() { 0x001DFFFF, 0, \_SB.PCI0.LPC0.LNKA, 0 }, - Package() { 0x001DFFFF, 1, \_SB.PCI0.LPC0.LNKB, 0 }, - Package() { 0x001DFFFF, 2, \_SB.PCI0.LPC0.LNKC, 0 }, - Package() { 0x001DFFFF, 3, \_SB.PCI0.LPC0.LNKD, 0 }, - - Package() { 0x001EFFFF, 0, \_SB.PCI0.LPC0.LNKA, 0 }, - Package() { 0x001EFFFF, 1, \_SB.PCI0.LPC0.LNKB, 0 }, - Package() { 0x001EFFFF, 2, \_SB.PCI0.LPC0.LNKC, 0 }, - Package() { 0x001EFFFF, 3, \_SB.PCI0.LPC0.LNKD, 0 }, - - Package() { 0x001FFFFF, 0, \_SB.PCI0.LPC0.LNKA, 0 }, - Package() { 0x001FFFFF, 1, \_SB.PCI0.LPC0.LNKB, 0 }, - Package() { 0x001FFFFF, 2, \_SB.PCI0.LPC0.LNKC, 0 }, - Package() { 0x001FFFFF, 3, \_SB.PCI0.LPC0.LNKD, 0 }, - }) - - Name (ARUN, Package() { - Package() { 0x0008FFFF, 0, 0, 16 }, - Package() { 0x0008FFFF, 1, 0, 17 }, - Package() { 0x0008FFFF, 2, 0, 18 }, - Package() { 0x0008FFFF, 3, 0, 19 }, - - Package() { 0x0009FFFF, 0, 0, 16 }, - Package() { 0x0009FFFF, 1, 0, 17 }, - Package() { 0x0009FFFF, 2, 0, 18 }, - Package() { 0x0009FFFF, 3, 0, 19 }, - - Package() { 0x000AFFFF, 0, 0, 16 }, - Package() { 0x000AFFFF, 1, 0, 17 }, - Package() { 0x000AFFFF, 2, 0, 18 }, - Package() { 0x000AFFFF, 3, 0, 19 }, - - Package() { 0x000BFFFF, 0, 0, 16 }, - Package() { 0x000BFFFF, 1, 0, 17 }, - Package() { 0x000BFFFF, 2, 0, 18 }, - Package() { 0x000BFFFF, 3, 0, 19 }, - - Package() { 0x000CFFFF, 0, 0, 16 }, - Package() { 0x000CFFFF, 1, 0, 17 }, - Package() { 0x000CFFFF, 2, 0, 18 }, - Package() { 0x000CFFFF, 3, 0, 19 }, - - Package() { 0x000DFFFF, 0, 0, 16 }, - Package() { 0x000DFFFF, 1, 0, 17 }, - Package() { 0x000DFFFF, 2, 0, 18 }, - Package() { 0x000DFFFF, 3, 0, 19 }, - - Package() { 0x000EFFFF, 0, 0, 16 }, - Package() { 0x000EFFFF, 1, 0, 17 }, - Package() { 0x000EFFFF, 2, 0, 18 }, - Package() { 0x000EFFFF, 3, 0, 19 }, - - Package() { 0x000FFFFF, 0, 0, 16 }, - Package() { 0x000FFFFF, 1, 0, 17 }, - Package() { 0x000FFFFF, 2, 0, 18 }, - Package() { 0x000FFFFF, 3, 0, 19 }, - - Package() { 0x0010FFFF, 0, 0, 16 }, - Package() { 0x0010FFFF, 1, 0, 17 }, - Package() { 0x0010FFFF, 2, 0, 18 }, - Package() { 0x0010FFFF, 3, 0, 19 }, - - Package() { 0x0011FFFF, 0, 0, 16 }, - Package() { 0x0011FFFF, 1, 0, 17 }, - Package() { 0x0011FFFF, 2, 0, 18 }, - Package() { 0x0011FFFF, 3, 0, 19 }, - - Package() { 0x0012FFFF, 0, 0, 16 }, - Package() { 0x0012FFFF, 1, 0, 17 }, - Package() { 0x0012FFFF, 2, 0, 18 }, - Package() { 0x0012FFFF, 3, 0, 19 }, - - Package() { 0x0013FFFF, 0, 0, 16 }, - Package() { 0x0013FFFF, 1, 0, 17 }, - Package() { 0x0013FFFF, 2, 0, 18 }, - Package() { 0x0013FFFF, 3, 0, 19 }, - - Package() { 0x0014FFFF, 0, 0, 16 }, - Package() { 0x0014FFFF, 1, 0, 17 }, - Package() { 0x0014FFFF, 2, 0, 18 }, - Package() { 0x0014FFFF, 3, 0, 19 }, - - Package() { 0x0016FFFF, 0, 0, 16 }, - Package() { 0x0016FFFF, 1, 0, 17 }, - Package() { 0x0016FFFF, 2, 0, 18 }, - Package() { 0x0016FFFF, 3, 0, 19 }, - - Package() { 0x0017FFFF, 0, 0, 16 }, - Package() { 0x0017FFFF, 1, 0, 17 }, - Package() { 0x0017FFFF, 2, 0, 18 }, - Package() { 0x0017FFFF, 3, 0, 19 }, - - Package() { 0x0018FFFF, 0, 0, 16 }, - Package() { 0x0018FFFF, 1, 0, 17 }, - Package() { 0x0018FFFF, 2, 0, 18 }, - Package() { 0x0018FFFF, 3, 0, 19 }, - - Package() { 0x0019FFFF, 0, 0, 16 }, - Package() { 0x0019FFFF, 1, 0, 17 }, - Package() { 0x0019FFFF, 2, 0, 18 }, - Package() { 0x0019FFFF, 3, 0, 19 }, - - Package() { 0x001CFFFF, 0, 0, 16 }, - Package() { 0x001CFFFF, 1, 0, 17 }, - Package() { 0x001CFFFF, 2, 0, 18 }, - Package() { 0x001CFFFF, 3, 0, 19 }, - - Package() { 0x001DFFFF, 0, 0, 16 }, - Package() { 0x001DFFFF, 1, 0, 17 }, - Package() { 0x001DFFFF, 2, 0, 18 }, - Package() { 0x001DFFFF, 3, 0, 19 }, - - Package() { 0x001EFFFF, 0, 0, 16 }, - Package() { 0x001EFFFF, 1, 0, 17 }, - Package() { 0x001EFFFF, 2, 0, 18 }, - Package() { 0x001EFFFF, 3, 0, 19 }, - - Package() { 0x001FFFFF, 0, 0, 16 }, - Package() { 0x001FFFFF, 1, 0, 17 }, - Package() { 0x001FFFFF, 2, 0, 18 }, - Package() { 0x001FFFFF, 3, 0, 19 }, - }) - - Device (UNC0) - { - Name (_HID, EisaId ("PNP0A03")) - Name (_UID, 0x3F) - Method (_BBN, 0, NotSerialized) - { - Return (0xff) - } - - Name (_ADR, 0x00) - Method (_STA, 0, NotSerialized) - { - Return (0xf) - } - - Name (_CRS, ResourceTemplate () - { - WordBusNumber (ResourceProducer, MinFixed, MaxFixed, PosDecode, - 0x0000, // Granularity - 0x00FF, // Range Minimum - 0x00FF, // Range Maximum - 0x0000, // Translation Offset - 0x0001, // Length - ,, ) - }) - - Method (_PRT, 0, NotSerialized) - { - If (LEqual (PICM, Zero)) - { - Return (PRUN) - } - - Return (ARUN) - } - } - } - - #include "acpi/mainboard.asl" -} diff --git a/src/mainboard/ocp/monolake/fadt.c b/src/mainboard/ocp/monolake/fadt.c deleted file mode 100644 index 5af6056b49..0000000000 --- a/src/mainboard/ocp/monolake/fadt.c +++ /dev/null @@ -1,27 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007-2009 coresystems GmbH - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include - -void acpi_create_fadt(acpi_fadt_t *fadt, acpi_facs_t *facs, void *dsdt) -{ - acpi_header_t *header = &(fadt->header); - - acpi_fill_in_fadt(fadt, facs, dsdt); - - /* Platform specific customizations go here */ - - header->checksum = acpi_checksum((void *) fadt, sizeof(acpi_fadt_t)); -} diff --git a/src/mainboard/ocp/monolake/ipmi.c b/src/mainboard/ocp/monolake/ipmi.c deleted file mode 100644 index 3f178dc2cc..0000000000 --- a/src/mainboard/ocp/monolake/ipmi.c +++ /dev/null @@ -1,78 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2019 Wiwynn Corp. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ -#include -#include -#include -#include "ipmi.h" - -int is_ipmi_clear_cmos_set(ipmi_oem_rsp_t *rsp) -{ - int ret; - ipmi_oem_req_t req; - - if (rsp == NULL) { - printk(BIOS_ERR, "%s failed, null pointer parameter\n", - __func__); - return 0; - } - /* IPMI OEM get bios boot order command to check if the valid bit and - the CMOS clear bit are both set from the response BootMode byte. */ - ret = ipmi_kcs_message(BMC_KCS_BASE, IPMI_NETFN_OEM, 0x0, - IPMI_OEM_GET_BIOS_BOOT_ORDER, - (const unsigned char *) &req, sizeof(ipmi_oem_req_t), - (unsigned char *) rsp, sizeof(ipmi_oem_rsp_t)); - - if (ret < sizeof(struct ipmi_rsp) || rsp->CompletionCode) { - printk(BIOS_ERR, "IPMI: %s command failed (ret=%d resp=0x%x)\n", - __func__, ret, rsp->CompletionCode); - return 0; - } - - if (GET_VALID_BIT(rsp->Data.BootMode) && GET_CMOS_BIT(rsp->Data.BootMode)) { - printk(BIOS_INFO, "IPMI CMOS clear requested\n"); - return 1; - } - - printk(BIOS_DEBUG, "IPMI CMOS clear is not set\n"); - return 0; -} - -void clear_ipmi_flags(ipmi_oem_rsp_t *rsp_get) -{ - int ret; - ipmi_oem_req_t req; - struct ipmi_rsp rsp; - - if (rsp_get == NULL) { - printk(BIOS_ERR, "%s failed, null pointer parameter\n", - __func__); - return; - } - - req = rsp_get->Data; - CLEAR_CMOS_AND_VALID_BIT(req.BootMode); - ret = ipmi_kcs_message(BMC_KCS_BASE, IPMI_NETFN_OEM, 0x0, - IPMI_OEM_SET_BIOS_BOOT_ORDER, - (const unsigned char *) &req, sizeof(ipmi_oem_req_t), - (unsigned char *) &rsp, sizeof(rsp)); - - if (ret < sizeof(struct ipmi_rsp) || rsp.completion_code) { - printk(BIOS_ERR, "IPMI: %s command failed (ret=%d resp=0x%x)\n", - __func__, ret, rsp.completion_code); - return; - } - - printk(BIOS_INFO, "clear IPMI flags done\n"); -} diff --git a/src/mainboard/ocp/monolake/ipmi.h b/src/mainboard/ocp/monolake/ipmi.h deleted file mode 100644 index 04649111c2..0000000000 --- a/src/mainboard/ocp/monolake/ipmi.h +++ /dev/null @@ -1,53 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2019 Wiwynn Corp. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef MONOLAKE_IPMI_H -#define MONOLAKE_IPMI_H -#include - -#define IPMI_NETFN_OEM 0x30 -#define IPMI_OEM_SET_BIOS_BOOT_ORDER 0x52 -#define IPMI_OEM_GET_BIOS_BOOT_ORDER 0x53 -#define GET_CMOS_BIT(x) ((x) & (1 << 1)) -#define GET_VALID_BIT(x) ((x) & (1 << 7)) -#define CLEAR_CMOS_AND_VALID_BIT(x) ((x) &= 0x7d) -#define BMC_KCS_BASE 0xca2 -typedef struct { - u8 BootMode; /* Bit 1:CMOS clear, bit 7:valid bit. */ - u8 Boot0000; - u8 Boot0001; - u8 Boot0002; - u8 Boot0003; - u8 Boot0004; -} __packed ipmi_oem_req_t; - -typedef struct { - u16 KcsRsp; - u8 CompletionCode; - ipmi_oem_req_t Data; -} __packed ipmi_oem_rsp_t; - -/* - * IPMI get response to check if valid and CMOS clear bit - * are both set and store the IPMI response data to the parameter. - */ -int is_ipmi_clear_cmos_set(ipmi_oem_rsp_t *rsp); -/* - * Clear valid bit and CMOS clear bit from the parameter - * and set it back via IPMI. - */ -void clear_ipmi_flags(ipmi_oem_rsp_t *rsp); - -#endif diff --git a/src/mainboard/ocp/monolake/irqroute.c b/src/mainboard/ocp/monolake/irqroute.c deleted file mode 100644 index f91cf0d5b3..0000000000 --- a/src/mainboard/ocp/monolake/irqroute.c +++ /dev/null @@ -1,18 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2012 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include "irqroute.h" - -DEFINE_IRQ_ROUTES; diff --git a/src/mainboard/ocp/monolake/irqroute.h b/src/mainboard/ocp/monolake/irqroute.h deleted file mode 100644 index c3911be75b..0000000000 --- a/src/mainboard/ocp/monolake/irqroute.h +++ /dev/null @@ -1,48 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2012 Google Inc. - * Copyright (C) 2015-2016 Intel Corp. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef IRQROUTE_H -#define IRQROUTE_H - -#include -#include - -#define PCI_DEV_PIRQ_ROUTES \ - PCI_DEV_PIRQ_ROUTE(XHCI_DEV, A, B, C, D), \ - PCI_DEV_PIRQ_ROUTE(ME_DEV, A, B, C, D), \ - PCI_DEV_PIRQ_ROUTE(GBE_DEV, A, B, C, D), \ - PCI_DEV_PIRQ_ROUTE(EHCI2_DEV, A, B, C, D), \ - PCI_DEV_PIRQ_ROUTE(HDA_DEV, A, B, C, D), \ - PCI_DEV_PIRQ_ROUTE(PCIE_DEV, A, B, C, D), \ - PCI_DEV_PIRQ_ROUTE(EHCI1_DEV, A, B, C, D), \ - PCI_DEV_PIRQ_ROUTE(SATA_DEV, A, B, C, D) - -/* - * Route each PIRQ[A-H] to a PIC IRQ[0-15] - * Reserved: 0, 1, 2, 8, 13 - * ACPI/SCI: 9 - */ -#define PIRQ_PIC_ROUTES \ - PIRQ_PIC(A, 5), \ - PIRQ_PIC(B, 6), \ - PIRQ_PIC(C, 7), \ - PIRQ_PIC(D, 10), \ - PIRQ_PIC(E, 11), \ - PIRQ_PIC(F, 12), \ - PIRQ_PIC(G, 14), \ - PIRQ_PIC(H, 15) - -#endif /* IRQROUTE_H */ diff --git a/src/mainboard/ocp/monolake/mainboard.c b/src/mainboard/ocp/monolake/mainboard.c deleted file mode 100644 index dffd19f0f0..0000000000 --- a/src/mainboard/ocp/monolake/mainboard.c +++ /dev/null @@ -1,97 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007-2009 coresystems GmbH - * Copyright (C) 2011 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include "ipmi.h" -/* VPD variable for enabling/disabling FRB2 timer. */ -#define FRB2_TIMER "FRB2_TIMER" -/* VPD variable for setting FRB2 timer countdown value. */ -#define FRB2_COUNTDOWN "FRB2_COUNTDOWN" -#define VPD_LEN 10 -/* Default countdown is 15 minutes. */ -#define DEFAULT_COUNTDOWN 9000 - -static void init_frb2_wdt(void) -{ - - char val[VPD_LEN]; - /* Enable FRB2 timer by default. */ - u8 enable = 1; - uint16_t countdown; - - if (vpd_get_bool(FRB2_TIMER, VPD_RW, &enable)) { - if (!enable) { - printk(BIOS_DEBUG, "Disable FRB2 timer\n"); - ipmi_stop_bmc_wdt(BMC_KCS_BASE); - } - } - if (enable) { - if (vpd_gets(FRB2_COUNTDOWN, val, VPD_LEN, VPD_RW)) { - countdown = (uint16_t)atol(val); - printk(BIOS_DEBUG, "FRB2 timer countdown set to: %d\n", - countdown); - } else { - printk(BIOS_DEBUG, "FRB2 timer use default value: %d\n", - DEFAULT_COUNTDOWN); - countdown = DEFAULT_COUNTDOWN; - } - ipmi_init_and_start_bmc_wdt(BMC_KCS_BASE, countdown, - TIMEOUT_HARD_RESET); - } -} - -/* - * mainboard_enable is executed as first thing after enumerate_buses(). - * This is the earliest point to add customization. - */ -static void mainboard_enable(struct device *dev) -{ - ipmi_oem_rsp_t rsp; - - init_frb2_wdt(); - if (is_ipmi_clear_cmos_set(&rsp)) { - /* TODO: Should also try to restore CMOS to cmos.default - * if USE_OPTION_TABLE is set */ - cmos_init(1); - clear_ipmi_flags(&rsp); - system_reset(); - } -} - -struct chip_operations mainboard_ops = { - .enable_dev = mainboard_enable, -}; - -void smbios_fill_dimm_locator(const struct dimm_info *dimm, struct smbios_type17 *t) -{ - - char locator[64] = {0}; - - snprintf(locator, sizeof(locator), "DIMM_%c%u", 'A' + dimm->channel_num, - dimm->dimm_num); - t->device_locator = smbios_add_string(t->eos, locator); - - snprintf(locator, sizeof(locator), "_Node0_Channel%d_Dimm%d", dimm->channel_num, - dimm->dimm_num); - t->bank_locator = smbios_add_string(t->eos, locator); -} diff --git a/src/mainboard/ocp/monolake/romstage.c b/src/mainboard/ocp/monolake/romstage.c deleted file mode 100644 index ef41b7720e..0000000000 --- a/src/mainboard/ocp/monolake/romstage.c +++ /dev/null @@ -1,248 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2013 Google Inc. - * Copyright (C) 2015 Intel Corp. - * Copyright (C) 2019 Wiwynn Corp. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - - -/* Define the strings for UPD variables that could be customized */ -#define FSP_VAR_HYPERTHREADING "HyperThreading" - -static const struct gpio_config gpio_tables[] = { - /* PU_BMBUSY_N */ - {0, GPIO_MODE_GPIO, GPIO_INPUT, 0, 0, 0}, - /* SKU_BDE_ID1 */ - {1, GPIO_MODE_GPIO, GPIO_INPUT, 0, 0, 0}, - /* FM_BDXDE_ERR0_LVT3_N */ - {2, GPIO_MODE_GPIO, GPIO_INPUT, 0, 0, 0}, - /* FM_BDXDE_ERR1_LVT3_N */ - {3, GPIO_MODE_GPIO, GPIO_INPUT, 0, 0, 0}, - /* FM_CPU2PCH_THROT_LVT3 */ - {4, GPIO_MODE_GPIO, GPIO_INPUT, 0, 0, 0}, - /* FM_BDXDE_CATERR_LVT3_N */ - {5, GPIO_MODE_GPIO, GPIO_INPUT, 0, 0, 0}, - /* SKU_BDE_ID2 */ - {6, GPIO_MODE_GPIO, GPIO_INPUT, 0, 0, 0}, - /* REV_BDE_ID0 */ - {7, GPIO_MODE_GPIO, GPIO_INPUT, 0, 0, 0}, - /* RQ_BMC_PCH_NMI_NOA1_CLK */ - {8, GPIO_MODE_GPIO, GPIO_INPUT, 0, 0, 0}, - /* FM_USB_OC_5_N */ - {9, GPIO_MODE_GPIO, GPIO_INPUT, 0, 0, 0}, - /* FM_USB_OC_6_N */ - {10, GPIO_MODE_GPIO, GPIO_INPUT, 0, 0, 0}, - /* PU_SMBALERT_N */ - {11, GPIO_MODE_GPIO, GPIO_INPUT, 0, 0, 0}, - /* RQ_IBMC_PCH_SMI_LPC_N */ - {12, GPIO_MODE_GPIO, GPIO_INPUT, 0, 0, 0}, - /* NC */ - {13, GPIO_MODE_GPIO, GPIO_INPUT, 0, 0, 0}, - /* FM_LVC3_RISER1_ID4_N_PU */ - {14, GPIO_MODE_GPIO, GPIO_INPUT, 0, 0, 0}, - /* PD_P1V2_VDDQ_SEL_N */ - {15, GPIO_MODE_GPIO, GPIO_INPUT, 0, 0, 0}, - /* FM_CPU_THROTTLE_N */ - {16, GPIO_MODE_GPIO, GPIO_OUTPUT, GPIO_OUT_LEVEL_HIGH, 0, 0}, - /* SKU_BDE_ID0 */ - {17, GPIO_MODE_GPIO, GPIO_INPUT, 0, 0, 0}, - /* FM_SRC1CLKRQB */ - {18, GPIO_MODE_GPIO, GPIO_INPUT, 0, 0, 0}, - /* RST_PCIE_PCH_N */ - {19, GPIO_MODE_GPIO, GPIO_INPUT, 0, 0, 0}, - /* SMI_BMC_N_R */ - {20, GPIO_MODE_NATIVE, 0, 0, 0, 0}, - /* M_SATA0GP */ - {21, GPIO_MODE_GPIO, GPIO_INPUT, 0, 0, 0}, - /* SGPIO_SATA_CLOCK_R */ - {22, GPIO_MODE_NATIVE, 0, 0, 0, 0}, - /* TP */ - {23, GPIO_MODE_GPIO, GPIO_INPUT, 0, 0, 0}, - /* FAST_THROTTLE_N_R */ - {24, GPIO_MODE_NATIVE, 0, 0, 0, 0}, - /* BMC_READY_N */ - {25, GPIO_MODE_GPIO, GPIO_INPUT, 0, 0, 0}, - /* TP */ - {26, GPIO_MODE_GPIO, GPIO_INPUT, 0, 0, 0}, - /* FM_CPLD */ - {27, GPIO_MODE_GPIO, GPIO_INPUT, 0, 0, 0}, - /* FM_BDXDE_ME_DRIVE_N */ - {28, GPIO_MODE_NATIVE, 0, 0, 0, 0}, - /* H_BDXDE_PROCHOT_DISABLE */ - {29, GPIO_MODE_GPIO, GPIO_OUTPUT, GPIO_OUT_LEVEL_HIGH, 0, 0}, - /* SUSPWRDNACK */ - {30, GPIO_MODE_GPIO, GPIO_INPUT, 0, 0, 0}, - /* SMB_INA230_ALRT_N */ - {31, GPIO_MODE_GPIO, GPIO_INPUT, 0, 0, 0}, - /* TP */ - {32, GPIO_MODE_GPIO, GPIO_INPUT, 0, 0, 0}, - /* PD_DMI_RX_TERMINATION */ - {33, GPIO_MODE_GPIO, GPIO_OUTPUT, GPIO_OUT_LEVEL_HIGH, 0, 0}, - /* NC */ - {34, GPIO_MODE_GPIO, GPIO_INPUT, 0, 0, 0}, - /* NMI_BDE_R */ - {35, GPIO_MODE_NATIVE, 0, 0, 0, 0}, - /* FM_BIOS_ADV_FUNCTIONS */ - {36, GPIO_MODE_GPIO, GPIO_INPUT, 0, 0, 0}, - /* FM_ADR_TRIGGER_N */ - {37, GPIO_MODE_GPIO, GPIO_INPUT, 0, 0, 0}, - /* SGPIO_SATA_LOAD_R */ - {38, GPIO_MODE_NATIVE, 0, 0, 0, 0}, - /* SGPIO_SATA_DATAOUT0_R */ - {39, GPIO_MODE_NATIVE, 0, 0, 0, 0}, - /* FM_USB_OC_1_N */ - {40, GPIO_MODE_GPIO, GPIO_INPUT, 0, 0, 0}, - /* FM_USB_OC_2_N */ - {41, GPIO_MODE_GPIO, GPIO_INPUT, 0, 0, 0}, - /* FM_USB_OC_3_N */ - {42, GPIO_MODE_GPIO, GPIO_INPUT, 0, 0, 0}, - /* FM_USB_OC_4_N */ - {43, GPIO_MODE_GPIO, GPIO_INPUT, 0, 0, 0}, - /* TP */ - {44, GPIO_MODE_GPIO, GPIO_INPUT, 0, 0, 0}, - /* TP */ - {45, GPIO_MODE_GPIO, GPIO_INPUT, 0, 0, 0}, - /* FM_BIOS_POST_CMPLT_N */ - {46, GPIO_MODE_GPIO, GPIO_OUTPUT, GPIO_OUT_LEVEL_HIGH, 0, 0}, - /* NC */ - {47, GPIO_MODE_GPIO, GPIO_INPUT, 0, 0, 0}, - /* PU_SGPIO_SATA_DATAOUT1 */ - {48, GPIO_MODE_GPIO, GPIO_INPUT, 0, 0, 0}, - /* FM_XDP_PCH_OBSDATA */ - {49, GPIO_MODE_GPIO, GPIO_INPUT, 0, 0, 0}, - /* PU_GSXCLK */ - {50, GPIO_MODE_GPIO, GPIO_INPUT, 0, 0, 0}, - /* PU_GSXDOUT */ - {51, GPIO_MODE_GPIO, GPIO_INPUT, 0, 0, 0}, - /* PD_CPUSV */ - {52, GPIO_MODE_GPIO, GPIO_INPUT, 0, 0, 0}, - /* PD_GSXDIN */ - {53, GPIO_MODE_GPIO, GPIO_INPUT, 0, 0, 0}, - /* PU_GSXSREST_N */ - {54, GPIO_MODE_GPIO, GPIO_INPUT, 0, 0, 0}, - /* PU_BIOS_RCVR_BOOT_J2 */ - {55, GPIO_MODE_GPIO, GPIO_INPUT, 0, 0, 0}, - /* NC */ - {56, GPIO_MODE_GPIO, GPIO_INPUT, 0, 0, 0}, - /* PU_ME_RCVR_N */ - {57, GPIO_MODE_NATIVE, 0, 0, 0, 0}, - /* SMB_SML1_3V3SB_CLK */ - {58, GPIO_MODE_NATIVE, 0, 0, 0, 0}, - /* FM_USB_OC_0_N */ - {59, GPIO_MODE_NATIVE, 0, 0, 0, 0}, - /* SMB_SML0_3V3SB_ALERT */ - {60, GPIO_MODE_NATIVE, 0, 0, 0, 0}, - /* SLP_SUS_STAT_N */ - {61, GPIO_MODE_NATIVE, 0, 0, 0, 0}, - /* CLK_CPLD_SUSCLK_R */ - {62, GPIO_MODE_NATIVE, 0, 0, 0, 0}, - /* NC */ - {63, GPIO_MODE_GPIO, GPIO_INPUT, 0, 0, 0}, - /* NC */ - {64, GPIO_MODE_GPIO, GPIO_INPUT, 0, 0, 0}, - /* NC */ - {65, GPIO_MODE_GPIO, GPIO_INPUT, 0, 0, 0}, - /* NC */ - {66, GPIO_MODE_GPIO, GPIO_INPUT, 0, 0, 0}, - /* NC */ - {67, GPIO_MODE_GPIO, GPIO_INPUT, 0, 0, 0}, - /* REV_BDE_ID1 */ - {68, GPIO_MODE_GPIO, GPIO_INPUT, 0, 0, 0}, - /* TPM_PRSNT_N */ - {69, GPIO_MODE_GPIO, GPIO_INPUT, 0, 0, 0}, - /* NC */ - {70, GPIO_MODE_GPIO, GPIO_INPUT, 0, 0, 0}, - /* NC */ - {71, GPIO_MODE_GPIO, GPIO_INPUT, 0, 0, 0}, - /* PU_BATLOW_N */ - {72, GPIO_MODE_GPIO, GPIO_INPUT, 0, 0, 0}, - /* NC */ - {73, GPIO_MODE_GPIO, GPIO_INPUT, 0, 0, 0}, - /* PCHHOT_CPU_N */ - {74, GPIO_MODE_NATIVE, 0, 0, 0, 0}, - /* SMB_SML1_3V3SB_DAT */ - {75, GPIO_MODE_NATIVE, 0, 0, 0, 0}, - {0xff, GPIO_LIST_END, 0, 0, 0, 0}, -}; - -/** - * /brief mainboard call for setup that needs to be done before fsp init - * - */ -void early_mainboard_romstage_entry(void) -{ - /* - * Sometimes the system boots in an invalid state, where random values - * have been written to MSRs and then the MSRs are locked. - * Seems to always happen on warm reset. - * - * Power cycling or a board_reset() isn't sufficient in this case, so - * issue a full_reset() to "fix" this issue. - */ - msr_t msr = rdmsr(IA32_FEATURE_CONTROL); - if (msr.lo & 1) { - console_init(); - printk(BIOS_EMERG, "Detected broken platform state. Issuing full reset\n"); - full_reset(); - } -} - -/** - * /brief mainboard call for setup that needs to be done after fsp init - * - */ -void late_mainboard_romstage_entry(void) -{ - // IPMI through BIC - pci_write_config32(PCI_DEV(0, LPC_DEV, LPC_FUNC), LPC_GEN2_DEC, - 0x0c0ca1); - - // Initialize GPIOs - init_gpios(gpio_tables); -} - -/* - * This function sets up global variable to store VPD binary blob info, - * and use settings in the binary blob to configure UPD. - */ -static void board_configure_upd(UPD_DATA_REGION *UpdData) -{ - u8 val; - - if (vpd_get_bool(FSP_VAR_HYPERTHREADING, VPD_RW, &val)) - UpdData->HyperThreading = val; -} - -/** - * /brief customize fsp parameters, use data stored in VPD binary blob - * to configure FSP UPD variables. - */ -void romstage_fsp_rt_buffer_callback(FSP_INIT_RT_BUFFER *FspRtBuffer) -{ - UPD_DATA_REGION *UpdData = FspRtBuffer->Common.UpdDataRgnPtr; - - if (CONFIG(VPD)) - board_configure_upd(UpdData); -} diff --git a/src/mainboard/ocp/monolake/vboot-ro.fmd b/src/mainboard/ocp/monolake/vboot-ro.fmd deleted file mode 100644 index 44be3370ce..0000000000 --- a/src/mainboard/ocp/monolake/vboot-ro.fmd +++ /dev/null @@ -1,22 +0,0 @@ -FLASH 16M { - SI_ALL@0x0 0x800000 { - SI_DESC@0x0 0x1000 - SI_ME@0x1000 0x7ff000 - } - SI_BIOS@0x800000 0x800000 { - MISC_RW@0x0 0x20000 { - RW_MRC_CACHE@0x0 0x10000 - RW_VPD(PRESERVE)@0x010000 0x4000 - } - WP_RO@0x020000 0x7e0000 { - RO_VPD(PRESERVE)@0x0 0x4000 - RO_SECTION@0x4000 0x7dc000 { - FMAP@0x0 0x800 - RO_FRID@0x800 0x40 - RO_FRID_PAD@0x840 0x7c0 - GBB@0x1000 0x4000 - COREBOOT(CBFS)@0x5000 0x7d7000 - } - } - } -} diff --git a/src/mainboard/ocp/wedge100s/Kconfig b/src/mainboard/ocp/wedge100s/Kconfig deleted file mode 100644 index ef0fe88082..0000000000 --- a/src/mainboard/ocp/wedge100s/Kconfig +++ /dev/null @@ -1,61 +0,0 @@ -if BOARD_OCP_WEDGE100S - -config BOARD_SPECIFIC_OPTIONS - def_bool y - select SOC_INTEL_FSP_BROADWELL_DE - select BOARD_ROMSIZE_KB_16384 - select HAVE_ACPI_TABLES - select HAVE_OPTION_TABLE - select HAVE_FSP_BIN if FSP_PACKAGE_DEFAULT - select SERIRQ_CONTINUOUS_MODE - select FSP_EHCI1_ENABLE - select MRC_CACHE_FMAP - select ENABLE_FSP_FAST_BOOT - select MAINBOARD_HAS_LPC_TPM - select MAINBOARD_HAS_TPM1 - select DRIVERS_UART_8250IO - select SUPERIO_ITE_IT8528E - select IPMI_KCS - -config VBOOT - select VBOOT_VBNV_CMOS - select VBOOT_NO_BOARD_SUPPORT - select GBB_FLAG_DISABLE_LID_SHUTDOWN - select GBB_FLAG_DISABLE_PD_SOFTWARE_SYNC - select GBB_FLAG_DISABLE_EC_SOFTWARE_SYNC - select GBB_FLAG_DISABLE_FWMP - -config MAINBOARD_DIR - string - default "ocp/wedge100s" - -config MAINBOARD_PART_NUMBER - string - default "Wedge 100S" - -config IRQ_SLOT_COUNT - int - default 18 - -config CBFS_SIZE - hex - default 0x006fa000 if VBOOT - default 0x00200000 - -config VIRTUAL_ROM_SIZE - hex - default 0x1000000 - -config FSP_PACKAGE_DEFAULT - bool "Configure defaults for the Intel FSP package" - default n - -config FMDFILE - string - default "src/mainboard/$(CONFIG_MAINBOARD_DIR)/vboot-ro.fmd" if VBOOT - default "src/mainboard/$(CONFIG_MAINBOARD_DIR)/board.fmd" - -config INTEGRATED_UART - def_bool n - -endif # BOARD_OCP_WEDGE100S diff --git a/src/mainboard/ocp/wedge100s/Kconfig.name b/src/mainboard/ocp/wedge100s/Kconfig.name deleted file mode 100644 index 2bfc19d61b..0000000000 --- a/src/mainboard/ocp/wedge100s/Kconfig.name +++ /dev/null @@ -1,2 +0,0 @@ -config BOARD_OCP_WEDGE100S - bool "Wedge 100S" diff --git a/src/mainboard/ocp/wedge100s/Makefile.inc b/src/mainboard/ocp/wedge100s/Makefile.inc deleted file mode 100644 index 1606476d80..0000000000 --- a/src/mainboard/ocp/wedge100s/Makefile.inc +++ /dev/null @@ -1,16 +0,0 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2012 Google Inc. -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; version 2 of the License. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## - -ramstage-y += irqroute.c diff --git a/src/mainboard/ocp/wedge100s/acpi/mainboard.asl b/src/mainboard/ocp/wedge100s/acpi/mainboard.asl deleted file mode 100644 index 62944ef353..0000000000 --- a/src/mainboard/ocp/wedge100s/acpi/mainboard.asl +++ /dev/null @@ -1,20 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2012 Google Inc. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -Device (PWRB) -{ - Name(_HID, EisaId("PNP0C0C")) -} diff --git a/src/mainboard/ocp/wedge100s/acpi/platform.asl b/src/mainboard/ocp/wedge100s/acpi/platform.asl deleted file mode 100644 index 7ffae2e6e0..0000000000 --- a/src/mainboard/ocp/wedge100s/acpi/platform.asl +++ /dev/null @@ -1,56 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007-2009 coresystems GmbH - * Copyright (C) 2012 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -/* The APM port can be used for generating software SMIs */ - -OperationRegion (APMP, SystemIO, 0xb2, 2) -Field (APMP, ByteAcc, NoLock, Preserve) -{ - APMC, 8, // APM command - APMS, 8 // APM status -} - -/* Port 80 POST */ - -OperationRegion (POST, SystemIO, 0x80, 1) -Field (POST, ByteAcc, Lock, Preserve) -{ - DBG0, 8 -} - -Name(\APC1, Zero) // IIO IOAPIC - -Name(\PICM, Zero) // IOAPIC/8259 - -Method(_PIC, 1) -{ - Store(Arg0, PICM) -} - -/* The _PTS method (Prepare To Sleep) is called before the OS is - * entering a sleep state. The sleep state number is passed in Arg0 - */ - -Method(_PTS,1) -{ -} - -/* The _WAK method is called on system wakeup */ - -Method(_WAK,1) -{ - Return(Package(){0,0}) -} diff --git a/src/mainboard/ocp/wedge100s/acpi_tables.c b/src/mainboard/ocp/wedge100s/acpi_tables.c deleted file mode 100644 index 0197def7a7..0000000000 --- a/src/mainboard/ocp/wedge100s/acpi_tables.c +++ /dev/null @@ -1,43 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2012 Google Inc. - * Copyright (C) 2015-2016 Intel Corp. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include - -extern const unsigned char AmlCode[]; - -unsigned long acpi_fill_madt(unsigned long current) -{ - u32 i; - - current = acpi_create_madt_lapics(current); - - current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, 8, - IOXAPIC1_BASE_ADDRESS, 0); - set_ioapic_id((u8 *)IOXAPIC1_BASE_ADDRESS, 8); - - current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, 9, - IOXAPIC2_BASE_ADDRESS, 24); - set_ioapic_id((u8 *)IOXAPIC2_BASE_ADDRESS, 9); - - current = acpi_madt_irq_overrides(current); - - for (i = 0; i < 16; i++) - current += acpi_create_madt_lapic_nmi((acpi_madt_lapic_nmi_t *)current, i, 0xD, 1); - - return current; -} diff --git a/src/mainboard/ocp/wedge100s/board.fmd b/src/mainboard/ocp/wedge100s/board.fmd deleted file mode 100644 index 8e440810e6..0000000000 --- a/src/mainboard/ocp/wedge100s/board.fmd +++ /dev/null @@ -1,27 +0,0 @@ -FLASH@0xff000000 0x1000000 { - SI_ALL@0x0 0x800000 { - SI_DESC@0x0 0x1000 - SI_ME@0x1000 0x7ff000 - } - SI_BIOS@0x800000 0x800000 { - FMAP@0x0 0x1000 - RW_MISC@0x1000 0xe000 { - RW_ELOG@0x0 0x4000 - RW_VPD@0x4000 0x2000 - RW_MISC_UNUSED@0x6000 0x5000 - RW_NVRAM@0xc000 0x2000 -# UNIFIED_MRC_CACHE@0x10000 0x20000 { -# RECOVERY_MRC_CACHE@0x0 0x10000 -# RW_MRC_CACHE@0x10000 0x10000 -# } - } - UNUSED@0xf000 0x1000 { - # This only exists to satisfy tools that - # specifically look for RO_VPD. - RO_VPD@0x0 0x1000 - } - RW_MRC_CACHE@0x10000 0x10000 - CONSOLE@0x20000 0x10000 - COREBOOT(CBFS)@0x30000 0x7d0000 - } -} diff --git a/src/mainboard/ocp/wedge100s/board_info.txt b/src/mainboard/ocp/wedge100s/board_info.txt deleted file mode 100644 index e8c178fbe0..0000000000 --- a/src/mainboard/ocp/wedge100s/board_info.txt +++ /dev/null @@ -1,5 +0,0 @@ -Board name: Wedge 100S -Category: server -ROM protocol: SPI -ROM socketed: yes -Release year: 2017 diff --git a/src/mainboard/ocp/wedge100s/cmos.layout b/src/mainboard/ocp/wedge100s/cmos.layout deleted file mode 100644 index 3aaa56b569..0000000000 --- a/src/mainboard/ocp/wedge100s/cmos.layout +++ /dev/null @@ -1,120 +0,0 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2007-2008 coresystems GmbH -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; version 2 of the License. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## - -# ----------------------------------------------------------------- -entries - -#start-bit length config config-ID name -#0 8 r 0 seconds -#8 8 r 0 alarm_seconds -#16 8 r 0 minutes -#24 8 r 0 alarm_minutes -#32 8 r 0 hours -#40 8 r 0 alarm_hours -#48 8 r 0 day_of_week -#56 8 r 0 day_of_month -#64 8 r 0 month -#72 8 r 0 year -# ----------------------------------------------------------------- -# Status Register A -#80 4 r 0 rate_select -#84 3 r 0 REF_Clock -#87 1 r 0 UIP -# ----------------------------------------------------------------- -# Status Register B -#88 1 r 0 auto_switch_DST -#89 1 r 0 24_hour_mode -#90 1 r 0 binary_values_enable -#91 1 r 0 square-wave_out_enable -#92 1 r 0 update_finished_enable -#93 1 r 0 alarm_interrupt_enable -#94 1 r 0 periodic_interrupt_enable -#95 1 r 0 disable_clock_updates -# ----------------------------------------------------------------- -# Status Register C -#96 4 r 0 status_c_rsvd -#100 1 r 0 uf_flag -#101 1 r 0 af_flag -#102 1 r 0 pf_flag -#103 1 r 0 irqf_flag -# ----------------------------------------------------------------- -# Status Register D -#104 7 r 0 status_d_rsvd -#111 1 r 0 valid_cmos_ram -# ----------------------------------------------------------------- -# Diagnostic Status Register -#112 8 r 0 diag_rsvd1 - -# ----------------------------------------------------------------- -0 120 r 0 reserved_memory -#120 264 r 0 unused - -# ----------------------------------------------------------------- -# RTC_BOOT_BYTE (coreboot hardcoded) -384 1 e 4 boot_option -388 4 h 0 reboot_counter -#390 2 r 0 unused? - -# ----------------------------------------------------------------- -# coreboot config options: console -#392 3 r 0 unused -395 4 e 6 debug_level -#399 1 r 0 unused - -# coreboot config options: cpu -400 1 e 2 hyper_threading -#401 7 r 0 unused - -# coreboot config options: southbridge -408 1 e 1 nmi -409 2 e 7 power_on_after_fail -#411 5 r 0 unused -416 128 r 0 vbnv - -# MRC Scrambler Seed values -896 32 r 0 mrc_scrambler_seed -928 32 r 0 mrc_scrambler_seed_s3 - -# coreboot config options: check sums -984 16 h 0 check_sum -#1000 24 r 0 amd_reserved - -# ----------------------------------------------------------------- - -enumerations - -#ID value text -1 0 Disable -1 1 Enable -2 0 Enable -2 1 Disable -4 0 Fallback -4 1 Normal -6 0 Emergency -6 1 Alert -6 2 Critical -6 3 Error -6 4 Warning -6 5 Notice -6 6 Info -6 7 Debug -6 8 Spew -7 0 Disable -7 1 Enable -7 2 Keep -# ----------------------------------------------------------------- -checksums - -checksum 392 415 984 diff --git a/src/mainboard/ocp/wedge100s/devicetree.cb b/src/mainboard/ocp/wedge100s/devicetree.cb deleted file mode 100644 index 3552a6db1b..0000000000 --- a/src/mainboard/ocp/wedge100s/devicetree.cb +++ /dev/null @@ -1,74 +0,0 @@ -chip soc/intel/fsp_broadwell_de - device cpu_cluster 0 on - device lapic 0 on end - end - device domain 0 on - device pci 00.0 on end # SoC router - device pci 01.0 on # PCIe x1 - # Intel i210t - end - device pci 02.0 on # PCIe x1 - # QuickData Technology - end - device pci 02.2 on # PCIe x1 - # Intel X552 10 GbE SFP+ - end - device pci 03.0 on end # PEG 16x - device pci 05.0 on end # Vtd - device pci 05.1 on end # IIO Hotplug - device pci 05.2 on end # IIO - device pci 05.4 on end # PIC - device pci 14.0 off end # xHCI Controller - device pci 1c.0 on # PCH PCIe Gen2 x4 - # BCM56960 Switch ASIC - end - device pci 1d.0 on end # PCH EHCI Controller - device pci 1f.0 on # LPC - chip drivers/pc80/tpm - device pnp 0c31.0 on end - end - chip superio/ite/it8528e - # COM1, routed to COM-e header - device pnp 6e.1 on - io 0x60 = 0x3f8 - irq 0x70 = 4 - end - # COM2, routed to COM-e header - device pnp 6e.2 on - io 0x60 = 0x2f8 - irq 0x70 = 3 - end - device pnp 6e.4 off end - device pnp 6e.5 off end - device pnp 6e.6 off end - device pnp 6e.a off end - device pnp 6e.f off end - device pnp 6e.10 off end - device pnp 6e.11 on - io 0x60 = 0x62 - io 0x62 = 0x66 - irq 0x70 = 1 - end - device pnp 6e.12 on - io 0x60 = 0x68 - io 0x62 = 0x6c - irq 0x70 = 1 - end - device pnp 6e.13 off end - device pnp 6e.14 off end - device pnp 6e.17 off end - device pnp 6e.18 off end - device pnp 6e.19 off end - end #superio/ite/it8528e - chip drivers/ipmi - device pnp ca2.0 on end # IPMI KCS - end - end # LPC Bridge - device pci 1f.2 on end # SATA Controller - device pci 1f.3 on end # SMBus Controller - device pci 1f.5 off end # SATA Controller - device pci 1f.6 on # Thermal Management Controller - # DON'T DISABLE, CRASHES FSP MR2 - end - end -end diff --git a/src/mainboard/ocp/wedge100s/dsdt.asl b/src/mainboard/ocp/wedge100s/dsdt.asl deleted file mode 100644 index 1248703266..0000000000 --- a/src/mainboard/ocp/wedge100s/dsdt.asl +++ /dev/null @@ -1,294 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007-2009 coresystems GmbH - * Copyright (C) 2011 Google Inc. - * Copyright (C) 2015-2016 Intel Corp. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -DefinitionBlock( - "dsdt.aml", - "DSDT", - 0x02, // DSDT revision: ACPI v2.0 and up - OEM_ID, - ACPI_TABLE_CREATOR, - 0x20110725 // OEM revision -) -{ - #include "acpi/platform.asl" - - Name(_S0, Package() { 0x00, 0x00, 0x00, 0x00 }) - Name(_S5, Package() { 0x07, 0x00, 0x00, 0x00 }) - - Scope (\_SB) - { - Device (PCI0) - { - #include - #include - } - - Name (PRUN, Package() { - Package() { 0x0008FFFF, 0, \_SB.PCI0.LPC0.LNKA, 0 }, - Package() { 0x0008FFFF, 1, \_SB.PCI0.LPC0.LNKB, 0 }, - Package() { 0x0008FFFF, 2, \_SB.PCI0.LPC0.LNKC, 0 }, - Package() { 0x0008FFFF, 3, \_SB.PCI0.LPC0.LNKD, 0 }, - - Package() { 0x0009FFFF, 0, \_SB.PCI0.LPC0.LNKA, 0 }, - Package() { 0x0009FFFF, 1, \_SB.PCI0.LPC0.LNKB, 0 }, - Package() { 0x0009FFFF, 2, \_SB.PCI0.LPC0.LNKC, 0 }, - Package() { 0x0009FFFF, 3, \_SB.PCI0.LPC0.LNKD, 0 }, - - Package() { 0x000AFFFF, 0, \_SB.PCI0.LPC0.LNKA, 0 }, - Package() { 0x000AFFFF, 1, \_SB.PCI0.LPC0.LNKB, 0 }, - Package() { 0x000AFFFF, 2, \_SB.PCI0.LPC0.LNKC, 0 }, - Package() { 0x000AFFFF, 3, \_SB.PCI0.LPC0.LNKD, 0 }, - - Package() { 0x000BFFFF, 0, \_SB.PCI0.LPC0.LNKA, 0 }, - Package() { 0x000BFFFF, 1, \_SB.PCI0.LPC0.LNKB, 0 }, - Package() { 0x000BFFFF, 2, \_SB.PCI0.LPC0.LNKC, 0 }, - Package() { 0x000BFFFF, 3, \_SB.PCI0.LPC0.LNKD, 0 }, - - Package() { 0x000CFFFF, 0, \_SB.PCI0.LPC0.LNKA, 0 }, - Package() { 0x000CFFFF, 1, \_SB.PCI0.LPC0.LNKB, 0 }, - Package() { 0x000CFFFF, 2, \_SB.PCI0.LPC0.LNKC, 0 }, - Package() { 0x000CFFFF, 3, \_SB.PCI0.LPC0.LNKD, 0 }, - - Package() { 0x000DFFFF, 0, \_SB.PCI0.LPC0.LNKA, 0 }, - Package() { 0x000DFFFF, 1, \_SB.PCI0.LPC0.LNKB, 0 }, - Package() { 0x000DFFFF, 2, \_SB.PCI0.LPC0.LNKC, 0 }, - Package() { 0x000DFFFF, 3, \_SB.PCI0.LPC0.LNKD, 0 }, - - Package() { 0x000EFFFF, 0, \_SB.PCI0.LPC0.LNKA, 0 }, - Package() { 0x000EFFFF, 1, \_SB.PCI0.LPC0.LNKB, 0 }, - Package() { 0x000EFFFF, 2, \_SB.PCI0.LPC0.LNKC, 0 }, - Package() { 0x000EFFFF, 3, \_SB.PCI0.LPC0.LNKD, 0 }, - - Package() { 0x000FFFFF, 0, \_SB.PCI0.LPC0.LNKA, 0 }, - Package() { 0x000FFFFF, 1, \_SB.PCI0.LPC0.LNKB, 0 }, - Package() { 0x000FFFFF, 2, \_SB.PCI0.LPC0.LNKC, 0 }, - Package() { 0x000FFFFF, 3, \_SB.PCI0.LPC0.LNKD, 0 }, - - Package() { 0x0010FFFF, 0, \_SB.PCI0.LPC0.LNKA, 0 }, - Package() { 0x0010FFFF, 1, \_SB.PCI0.LPC0.LNKB, 0 }, - Package() { 0x0010FFFF, 2, \_SB.PCI0.LPC0.LNKC, 0 }, - Package() { 0x0010FFFF, 3, \_SB.PCI0.LPC0.LNKD, 0 }, - - Package() { 0x0011FFFF, 0, \_SB.PCI0.LPC0.LNKA, 0 }, - Package() { 0x0011FFFF, 1, \_SB.PCI0.LPC0.LNKB, 0 }, - Package() { 0x0011FFFF, 2, \_SB.PCI0.LPC0.LNKC, 0 }, - Package() { 0x0011FFFF, 3, \_SB.PCI0.LPC0.LNKD, 0 }, - - Package() { 0x0012FFFF, 0, \_SB.PCI0.LPC0.LNKA, 0 }, - Package() { 0x0012FFFF, 1, \_SB.PCI0.LPC0.LNKB, 0 }, - Package() { 0x0012FFFF, 2, \_SB.PCI0.LPC0.LNKC, 0 }, - Package() { 0x0012FFFF, 3, \_SB.PCI0.LPC0.LNKD, 0 }, - - Package() { 0x0013FFFF, 0, \_SB.PCI0.LPC0.LNKA, 0 }, - Package() { 0x0013FFFF, 1, \_SB.PCI0.LPC0.LNKB, 0 }, - Package() { 0x0013FFFF, 2, \_SB.PCI0.LPC0.LNKC, 0 }, - Package() { 0x0013FFFF, 3, \_SB.PCI0.LPC0.LNKD, 0 }, - - Package() { 0x0014FFFF, 0, \_SB.PCI0.LPC0.LNKA, 0 }, - Package() { 0x0014FFFF, 1, \_SB.PCI0.LPC0.LNKB, 0 }, - Package() { 0x0014FFFF, 2, \_SB.PCI0.LPC0.LNKC, 0 }, - Package() { 0x0014FFFF, 3, \_SB.PCI0.LPC0.LNKD, 0 }, - - Package() { 0x0016FFFF, 0, \_SB.PCI0.LPC0.LNKA, 0 }, - Package() { 0x0016FFFF, 1, \_SB.PCI0.LPC0.LNKB, 0 }, - Package() { 0x0016FFFF, 2, \_SB.PCI0.LPC0.LNKC, 0 }, - Package() { 0x0016FFFF, 3, \_SB.PCI0.LPC0.LNKD, 0 }, - - Package() { 0x0017FFFF, 0, \_SB.PCI0.LPC0.LNKA, 0 }, - Package() { 0x0017FFFF, 1, \_SB.PCI0.LPC0.LNKB, 0 }, - Package() { 0x0017FFFF, 2, \_SB.PCI0.LPC0.LNKC, 0 }, - Package() { 0x0017FFFF, 3, \_SB.PCI0.LPC0.LNKD, 0 }, - - Package() { 0x0018FFFF, 0, \_SB.PCI0.LPC0.LNKA, 0 }, - Package() { 0x0018FFFF, 1, \_SB.PCI0.LPC0.LNKB, 0 }, - Package() { 0x0018FFFF, 2, \_SB.PCI0.LPC0.LNKC, 0 }, - Package() { 0x0018FFFF, 3, \_SB.PCI0.LPC0.LNKD, 0 }, - - Package() { 0x0019FFFF, 0, \_SB.PCI0.LPC0.LNKA, 0 }, - Package() { 0x0019FFFF, 1, \_SB.PCI0.LPC0.LNKB, 0 }, - Package() { 0x0019FFFF, 2, \_SB.PCI0.LPC0.LNKC, 0 }, - Package() { 0x0019FFFF, 3, \_SB.PCI0.LPC0.LNKD, 0 }, - - Package() { 0x001CFFFF, 0, \_SB.PCI0.LPC0.LNKA, 0 }, - Package() { 0x001CFFFF, 1, \_SB.PCI0.LPC0.LNKB, 0 }, - Package() { 0x001CFFFF, 2, \_SB.PCI0.LPC0.LNKC, 0 }, - Package() { 0x001CFFFF, 3, \_SB.PCI0.LPC0.LNKD, 0 }, - - Package() { 0x001DFFFF, 0, \_SB.PCI0.LPC0.LNKA, 0 }, - Package() { 0x001DFFFF, 1, \_SB.PCI0.LPC0.LNKB, 0 }, - Package() { 0x001DFFFF, 2, \_SB.PCI0.LPC0.LNKC, 0 }, - Package() { 0x001DFFFF, 3, \_SB.PCI0.LPC0.LNKD, 0 }, - - Package() { 0x001EFFFF, 0, \_SB.PCI0.LPC0.LNKA, 0 }, - Package() { 0x001EFFFF, 1, \_SB.PCI0.LPC0.LNKB, 0 }, - Package() { 0x001EFFFF, 2, \_SB.PCI0.LPC0.LNKC, 0 }, - Package() { 0x001EFFFF, 3, \_SB.PCI0.LPC0.LNKD, 0 }, - - Package() { 0x001FFFFF, 0, \_SB.PCI0.LPC0.LNKA, 0 }, - Package() { 0x001FFFFF, 1, \_SB.PCI0.LPC0.LNKB, 0 }, - Package() { 0x001FFFFF, 2, \_SB.PCI0.LPC0.LNKC, 0 }, - Package() { 0x001FFFFF, 3, \_SB.PCI0.LPC0.LNKD, 0 }, - }) - - Name (ARUN, Package() { - Package() { 0x0008FFFF, 0, 0, 16 }, - Package() { 0x0008FFFF, 1, 0, 17 }, - Package() { 0x0008FFFF, 2, 0, 18 }, - Package() { 0x0008FFFF, 3, 0, 19 }, - - Package() { 0x0009FFFF, 0, 0, 16 }, - Package() { 0x0009FFFF, 1, 0, 17 }, - Package() { 0x0009FFFF, 2, 0, 18 }, - Package() { 0x0009FFFF, 3, 0, 19 }, - - Package() { 0x000AFFFF, 0, 0, 16 }, - Package() { 0x000AFFFF, 1, 0, 17 }, - Package() { 0x000AFFFF, 2, 0, 18 }, - Package() { 0x000AFFFF, 3, 0, 19 }, - - Package() { 0x000BFFFF, 0, 0, 16 }, - Package() { 0x000BFFFF, 1, 0, 17 }, - Package() { 0x000BFFFF, 2, 0, 18 }, - Package() { 0x000BFFFF, 3, 0, 19 }, - - Package() { 0x000CFFFF, 0, 0, 16 }, - Package() { 0x000CFFFF, 1, 0, 17 }, - Package() { 0x000CFFFF, 2, 0, 18 }, - Package() { 0x000CFFFF, 3, 0, 19 }, - - Package() { 0x000DFFFF, 0, 0, 16 }, - Package() { 0x000DFFFF, 1, 0, 17 }, - Package() { 0x000DFFFF, 2, 0, 18 }, - Package() { 0x000DFFFF, 3, 0, 19 }, - - Package() { 0x000EFFFF, 0, 0, 16 }, - Package() { 0x000EFFFF, 1, 0, 17 }, - Package() { 0x000EFFFF, 2, 0, 18 }, - Package() { 0x000EFFFF, 3, 0, 19 }, - - Package() { 0x000FFFFF, 0, 0, 16 }, - Package() { 0x000FFFFF, 1, 0, 17 }, - Package() { 0x000FFFFF, 2, 0, 18 }, - Package() { 0x000FFFFF, 3, 0, 19 }, - - Package() { 0x0010FFFF, 0, 0, 16 }, - Package() { 0x0010FFFF, 1, 0, 17 }, - Package() { 0x0010FFFF, 2, 0, 18 }, - Package() { 0x0010FFFF, 3, 0, 19 }, - - Package() { 0x0011FFFF, 0, 0, 16 }, - Package() { 0x0011FFFF, 1, 0, 17 }, - Package() { 0x0011FFFF, 2, 0, 18 }, - Package() { 0x0011FFFF, 3, 0, 19 }, - - Package() { 0x0012FFFF, 0, 0, 16 }, - Package() { 0x0012FFFF, 1, 0, 17 }, - Package() { 0x0012FFFF, 2, 0, 18 }, - Package() { 0x0012FFFF, 3, 0, 19 }, - - Package() { 0x0013FFFF, 0, 0, 16 }, - Package() { 0x0013FFFF, 1, 0, 17 }, - Package() { 0x0013FFFF, 2, 0, 18 }, - Package() { 0x0013FFFF, 3, 0, 19 }, - - Package() { 0x0014FFFF, 0, 0, 16 }, - Package() { 0x0014FFFF, 1, 0, 17 }, - Package() { 0x0014FFFF, 2, 0, 18 }, - Package() { 0x0014FFFF, 3, 0, 19 }, - - Package() { 0x0016FFFF, 0, 0, 16 }, - Package() { 0x0016FFFF, 1, 0, 17 }, - Package() { 0x0016FFFF, 2, 0, 18 }, - Package() { 0x0016FFFF, 3, 0, 19 }, - - Package() { 0x0017FFFF, 0, 0, 16 }, - Package() { 0x0017FFFF, 1, 0, 17 }, - Package() { 0x0017FFFF, 2, 0, 18 }, - Package() { 0x0017FFFF, 3, 0, 19 }, - - Package() { 0x0018FFFF, 0, 0, 16 }, - Package() { 0x0018FFFF, 1, 0, 17 }, - Package() { 0x0018FFFF, 2, 0, 18 }, - Package() { 0x0018FFFF, 3, 0, 19 }, - - Package() { 0x0019FFFF, 0, 0, 16 }, - Package() { 0x0019FFFF, 1, 0, 17 }, - Package() { 0x0019FFFF, 2, 0, 18 }, - Package() { 0x0019FFFF, 3, 0, 19 }, - - Package() { 0x001CFFFF, 0, 0, 16 }, - Package() { 0x001CFFFF, 1, 0, 17 }, - Package() { 0x001CFFFF, 2, 0, 18 }, - Package() { 0x001CFFFF, 3, 0, 19 }, - - Package() { 0x001DFFFF, 0, 0, 16 }, - Package() { 0x001DFFFF, 1, 0, 17 }, - Package() { 0x001DFFFF, 2, 0, 18 }, - Package() { 0x001DFFFF, 3, 0, 19 }, - - Package() { 0x001EFFFF, 0, 0, 16 }, - Package() { 0x001EFFFF, 1, 0, 17 }, - Package() { 0x001EFFFF, 2, 0, 18 }, - Package() { 0x001EFFFF, 3, 0, 19 }, - - Package() { 0x001FFFFF, 0, 0, 16 }, - Package() { 0x001FFFFF, 1, 0, 17 }, - Package() { 0x001FFFFF, 2, 0, 18 }, - Package() { 0x001FFFFF, 3, 0, 19 }, - }) - - Device (UNC0) - { - Name (_HID, EisaId ("PNP0A03")) - Name (_UID, 0x3F) - Method (_BBN, 0, NotSerialized) - { - Return (0xff) - } - - Name (_ADR, 0x00) - Method (_STA, 0, NotSerialized) - { - Return (0xf) - } - - Name (_CRS, ResourceTemplate () - { - WordBusNumber (ResourceProducer, MinFixed, MaxFixed, PosDecode, - 0x0000, // Granularity - 0x00FF, // Range Minimum - 0x00FF, // Range Maximum - 0x0000, // Translation Offset - 0x0001, // Length - ,, ) - }) - - Method (_PRT, 0, NotSerialized) - { - If (LEqual (PICM, Zero)) - { - Return (PRUN) - } - - Return (ARUN) - } - } - } - - #include "acpi/mainboard.asl" -} diff --git a/src/mainboard/ocp/wedge100s/fadt.c b/src/mainboard/ocp/wedge100s/fadt.c deleted file mode 100644 index 5af6056b49..0000000000 --- a/src/mainboard/ocp/wedge100s/fadt.c +++ /dev/null @@ -1,27 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007-2009 coresystems GmbH - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include - -void acpi_create_fadt(acpi_fadt_t *fadt, acpi_facs_t *facs, void *dsdt) -{ - acpi_header_t *header = &(fadt->header); - - acpi_fill_in_fadt(fadt, facs, dsdt); - - /* Platform specific customizations go here */ - - header->checksum = acpi_checksum((void *) fadt, sizeof(acpi_fadt_t)); -} diff --git a/src/mainboard/ocp/wedge100s/irqroute.c b/src/mainboard/ocp/wedge100s/irqroute.c deleted file mode 100644 index f91cf0d5b3..0000000000 --- a/src/mainboard/ocp/wedge100s/irqroute.c +++ /dev/null @@ -1,18 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2012 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include "irqroute.h" - -DEFINE_IRQ_ROUTES; diff --git a/src/mainboard/ocp/wedge100s/irqroute.h b/src/mainboard/ocp/wedge100s/irqroute.h deleted file mode 100644 index c3911be75b..0000000000 --- a/src/mainboard/ocp/wedge100s/irqroute.h +++ /dev/null @@ -1,48 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2012 Google Inc. - * Copyright (C) 2015-2016 Intel Corp. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef IRQROUTE_H -#define IRQROUTE_H - -#include -#include - -#define PCI_DEV_PIRQ_ROUTES \ - PCI_DEV_PIRQ_ROUTE(XHCI_DEV, A, B, C, D), \ - PCI_DEV_PIRQ_ROUTE(ME_DEV, A, B, C, D), \ - PCI_DEV_PIRQ_ROUTE(GBE_DEV, A, B, C, D), \ - PCI_DEV_PIRQ_ROUTE(EHCI2_DEV, A, B, C, D), \ - PCI_DEV_PIRQ_ROUTE(HDA_DEV, A, B, C, D), \ - PCI_DEV_PIRQ_ROUTE(PCIE_DEV, A, B, C, D), \ - PCI_DEV_PIRQ_ROUTE(EHCI1_DEV, A, B, C, D), \ - PCI_DEV_PIRQ_ROUTE(SATA_DEV, A, B, C, D) - -/* - * Route each PIRQ[A-H] to a PIC IRQ[0-15] - * Reserved: 0, 1, 2, 8, 13 - * ACPI/SCI: 9 - */ -#define PIRQ_PIC_ROUTES \ - PIRQ_PIC(A, 5), \ - PIRQ_PIC(B, 6), \ - PIRQ_PIC(C, 7), \ - PIRQ_PIC(D, 10), \ - PIRQ_PIC(E, 11), \ - PIRQ_PIC(F, 12), \ - PIRQ_PIC(G, 14), \ - PIRQ_PIC(H, 15) - -#endif /* IRQROUTE_H */ diff --git a/src/mainboard/ocp/wedge100s/mainboard.c b/src/mainboard/ocp/wedge100s/mainboard.c deleted file mode 100644 index 93c2a58f74..0000000000 --- a/src/mainboard/ocp/wedge100s/mainboard.c +++ /dev/null @@ -1,33 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007-2009 coresystems GmbH - * Copyright (C) 2011 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#if CONFIG(VGA_ROM_RUN) -#include -#endif - -/* - * mainboard_enable is executed as first thing after enumerate_buses(). - * This is the earliest point to add customization. - */ -static void mainboard_enable(struct device *dev) -{ - -} - -struct chip_operations mainboard_ops = { - .enable_dev = mainboard_enable, -}; diff --git a/src/mainboard/ocp/wedge100s/romstage.c b/src/mainboard/ocp/wedge100s/romstage.c deleted file mode 100644 index 108d7a1c4d..0000000000 --- a/src/mainboard/ocp/wedge100s/romstage.c +++ /dev/null @@ -1,103 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2013 Google Inc. - * Copyright (C) 2015 Intel Corp. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#define SUPERIO_DEV 0x6e -#define SERIAL_DEV PNP_DEV(SUPERIO_DEV, 1) - -/** - * /brief mainboard call for setup that needs to be done before fsp init - * - */ -void early_mainboard_romstage_entry(void) -{ - /* Decode 0x6e/0x6f on LPC bus (actually 0x6c-0x6f) */ - pci_write_config32(PCI_DEV(0x0, LPC_DEV, LPC_FUNC), LPC_GEN1_DEC, - (0 << 16) | ALIGN_DOWN(SUPERIO_DEV, 4) | 1); - - /* Decode IPMI KCS */ - pci_write_config32(PCI_DEV(0x0, LPC_DEV, LPC_FUNC), LPC_GEN2_DEC, - (0 << 16) | ALIGN_DOWN(0xca2, 4) | 1); - - if (CONFIG(CONSOLE_SERIAL)) - ite_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); - - - /* - * Sometimes the system boots in an invalid state, where random values - * have been written to MSRs and then the MSRs are locked. - * Seems to always happen on warm reset. - * - * Power cycling or a board_reset() isn't sufficient in this case, so - * issue a full_reset() to "fix" this issue. - * - * It seems to be a deficiency in the reset logic, as other - * FSP broadwell DE boards are not affected. - */ - msr_t msr = rdmsr(IA32_FEATURE_CONTROL); - if (msr.lo & 1) { - console_init(); - printk(BIOS_EMERG, "Detected broken platform state. Issuing full reset\n"); - full_reset(); - } -} - -/** - * /brief mainboard call for setup that needs to be done after fsp init - * - */ -void late_mainboard_romstage_entry(void) -{ - -} - -/** - * /brief customize fsp parameters here if needed - */ -void romstage_fsp_rt_buffer_callback(FSP_INIT_RT_BUFFER *FspRtBuffer) -{ - UPD_DATA_REGION *fsp_upd_data = FspRtBuffer->Common.UpdDataRgnPtr; - if (CONFIG(FSP_USES_UPD)) { - /* The internal UART operates on 0x3f8/0x2f8. - * As it's not wired up and conflicts with SuperIO decoding - * the same range, make sure to disable it. - */ - fsp_upd_data->SerialPortControllerInit0 = 0; - fsp_upd_data->SerialPortControllerInit1 = 0; - - /* coreboot will initialize UART. - * No need for FSP to do it again. - */ - fsp_upd_data->SerialPortConfigure = 0; - fsp_upd_data->SerialPortBaudRate = 0; - - /* Make FSP use serial IO */ - if (CONFIG(CONSOLE_SERIAL)) - fsp_upd_data->SerialPortType = 1; - else - fsp_upd_data->SerialPortType = 0; - } -} diff --git a/src/mainboard/ocp/wedge100s/vboot-ro.fmd b/src/mainboard/ocp/wedge100s/vboot-ro.fmd deleted file mode 100644 index 1413bbff29..0000000000 --- a/src/mainboard/ocp/wedge100s/vboot-ro.fmd +++ /dev/null @@ -1,22 +0,0 @@ -FLASH 16M { - SI_ALL@0x0 0x800000 { - SI_DESC@0x0 0x1000 - SI_ME@0x1000 0x7ff000 - } - SI_BIOS@0x800000 0x800000 { - MISC_RW@0x0 0x20000 { - RW_MRC_CACHE@0x0 0x10000 - RW_VPD(PRESERVE)@0x010000 0x4000 - } - WP_RO@0x020000 0x7e0000 { - RO_VPD(PRESERVE)@0x0 0x4000 - RO_SECTION@0x4000 0x7dc000 { - FMAP@0x0 0x800 - RO_FRID@0x800 0x40 - RO_FRID_PAD@0x840 0x7c0 - GBB@0x1000 0xef000 - COREBOOT(CBFS)@0xf0000 0x6ec000 - } - } - } -} diff --git a/src/mainboard/siemens/mc_bdx1/Kconfig b/src/mainboard/siemens/mc_bdx1/Kconfig deleted file mode 100644 index 006758219a..0000000000 --- a/src/mainboard/siemens/mc_bdx1/Kconfig +++ /dev/null @@ -1,63 +0,0 @@ -if BOARD_SIEMENS_MC_BDX1 - -config BOARD_SPECIFIC_OPTIONS - def_bool y - select SOC_INTEL_FSP_BROADWELL_DE - select BOARD_ROMSIZE_KB_16384 - select HAVE_ACPI_TABLES - select HAVE_OPTION_TABLE - select HAVE_FSP_BIN if FSP_PACKAGE_DEFAULT - select CBFS_AUTOGEN_ATTRIBUTES - select USE_SIEMENS_HWILIB - select DRIVER_INTEL_I210 - select DRIVER_SIEMENS_NC_FPGA - select DRIVERS_I2C_RX6110SA - select DRIVERS_I2C_PCA9538 - select MAINBOARD_HAS_TPM2 - select MAINBOARD_HAS_LPC_TPM - -config VBOOT - select VBOOT_MEASURED_BOOT - select VBOOT_VBNV_FLASH - select VBOOT_NO_BOARD_SUPPORT - select GBB_FLAG_DISABLE_LID_SHUTDOWN - select GBB_FLAG_DISABLE_PD_SOFTWARE_SYNC - select GBB_FLAG_DISABLE_EC_SOFTWARE_SYNC - select GBB_FLAG_DISABLE_FWMP - -config FMDFILE - string - default "src/mainboard/$(CONFIG_MAINBOARD_DIR)/mc_bdx1.fmd" if VBOOT - -config MAINBOARD_DIR - string - default "siemens/mc_bdx1" - -config MAINBOARD_PART_NUMBER - string - default "MC BDX1" - -config IRQ_SLOT_COUNT - int - default 18 - -config CBFS_SIZE - hex - default 0x00D00000 if !VBOOT - -config VIRTUAL_ROM_SIZE - hex - default 0x1000000 - -config INTEGRATED_UART - bool - default n - -config DRIVERS_UART_8250IO - def_bool y - -config FSP_PACKAGE_DEFAULT - bool "Configure defaults for the Intel FSP package" - default n - -endif # BOARD_SIEMENS_MC_BDX1 diff --git a/src/mainboard/siemens/mc_bdx1/Kconfig.name b/src/mainboard/siemens/mc_bdx1/Kconfig.name deleted file mode 100644 index b37cee30fc..0000000000 --- a/src/mainboard/siemens/mc_bdx1/Kconfig.name +++ /dev/null @@ -1,2 +0,0 @@ -config BOARD_SIEMENS_MC_BDX1 - bool "MC BDX1" diff --git a/src/mainboard/siemens/mc_bdx1/Makefile.inc b/src/mainboard/siemens/mc_bdx1/Makefile.inc deleted file mode 100644 index 1606476d80..0000000000 --- a/src/mainboard/siemens/mc_bdx1/Makefile.inc +++ /dev/null @@ -1,16 +0,0 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2012 Google Inc. -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; version 2 of the License. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## - -ramstage-y += irqroute.c diff --git a/src/mainboard/siemens/mc_bdx1/acpi/mainboard.asl b/src/mainboard/siemens/mc_bdx1/acpi/mainboard.asl deleted file mode 100644 index 62944ef353..0000000000 --- a/src/mainboard/siemens/mc_bdx1/acpi/mainboard.asl +++ /dev/null @@ -1,20 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2012 Google Inc. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -Device (PWRB) -{ - Name(_HID, EisaId("PNP0C0C")) -} diff --git a/src/mainboard/siemens/mc_bdx1/acpi/platform.asl b/src/mainboard/siemens/mc_bdx1/acpi/platform.asl deleted file mode 100644 index 7ffae2e6e0..0000000000 --- a/src/mainboard/siemens/mc_bdx1/acpi/platform.asl +++ /dev/null @@ -1,56 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007-2009 coresystems GmbH - * Copyright (C) 2012 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -/* The APM port can be used for generating software SMIs */ - -OperationRegion (APMP, SystemIO, 0xb2, 2) -Field (APMP, ByteAcc, NoLock, Preserve) -{ - APMC, 8, // APM command - APMS, 8 // APM status -} - -/* Port 80 POST */ - -OperationRegion (POST, SystemIO, 0x80, 1) -Field (POST, ByteAcc, Lock, Preserve) -{ - DBG0, 8 -} - -Name(\APC1, Zero) // IIO IOAPIC - -Name(\PICM, Zero) // IOAPIC/8259 - -Method(_PIC, 1) -{ - Store(Arg0, PICM) -} - -/* The _PTS method (Prepare To Sleep) is called before the OS is - * entering a sleep state. The sleep state number is passed in Arg0 - */ - -Method(_PTS,1) -{ -} - -/* The _WAK method is called on system wakeup */ - -Method(_WAK,1) -{ - Return(Package(){0,0}) -} diff --git a/src/mainboard/siemens/mc_bdx1/acpi_tables.c b/src/mainboard/siemens/mc_bdx1/acpi_tables.c deleted file mode 100644 index 0197def7a7..0000000000 --- a/src/mainboard/siemens/mc_bdx1/acpi_tables.c +++ /dev/null @@ -1,43 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2012 Google Inc. - * Copyright (C) 2015-2016 Intel Corp. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include - -extern const unsigned char AmlCode[]; - -unsigned long acpi_fill_madt(unsigned long current) -{ - u32 i; - - current = acpi_create_madt_lapics(current); - - current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, 8, - IOXAPIC1_BASE_ADDRESS, 0); - set_ioapic_id((u8 *)IOXAPIC1_BASE_ADDRESS, 8); - - current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, 9, - IOXAPIC2_BASE_ADDRESS, 24); - set_ioapic_id((u8 *)IOXAPIC2_BASE_ADDRESS, 9); - - current = acpi_madt_irq_overrides(current); - - for (i = 0; i < 16; i++) - current += acpi_create_madt_lapic_nmi((acpi_madt_lapic_nmi_t *)current, i, 0xD, 1); - - return current; -} diff --git a/src/mainboard/siemens/mc_bdx1/board_info.txt b/src/mainboard/siemens/mc_bdx1/board_info.txt deleted file mode 100644 index 15b66c195e..0000000000 --- a/src/mainboard/siemens/mc_bdx1/board_info.txt +++ /dev/null @@ -1,5 +0,0 @@ -Board name: MC BDX1 -Category: misc -ROM protocol: SPI -ROM socketed: no -Release year: 2016 diff --git a/src/mainboard/siemens/mc_bdx1/cmos.layout b/src/mainboard/siemens/mc_bdx1/cmos.layout deleted file mode 100644 index 3c5bc3b03d..0000000000 --- a/src/mainboard/siemens/mc_bdx1/cmos.layout +++ /dev/null @@ -1,119 +0,0 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2007-2008 coresystems GmbH -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; version 2 of the License. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## - -# ----------------------------------------------------------------- -entries - -#start-bit length config config-ID name -#0 8 r 0 seconds -#8 8 r 0 alarm_seconds -#16 8 r 0 minutes -#24 8 r 0 alarm_minutes -#32 8 r 0 hours -#40 8 r 0 alarm_hours -#48 8 r 0 day_of_week -#56 8 r 0 day_of_month -#64 8 r 0 month -#72 8 r 0 year -# ----------------------------------------------------------------- -# Status Register A -#80 4 r 0 rate_select -#84 3 r 0 REF_Clock -#87 1 r 0 UIP -# ----------------------------------------------------------------- -# Status Register B -#88 1 r 0 auto_switch_DST -#89 1 r 0 24_hour_mode -#90 1 r 0 binary_values_enable -#91 1 r 0 square-wave_out_enable -#92 1 r 0 update_finished_enable -#93 1 r 0 alarm_interrupt_enable -#94 1 r 0 periodic_interrupt_enable -#95 1 r 0 disable_clock_updates -# ----------------------------------------------------------------- -# Status Register C -#96 4 r 0 status_c_rsvd -#100 1 r 0 uf_flag -#101 1 r 0 af_flag -#102 1 r 0 pf_flag -#103 1 r 0 irqf_flag -# ----------------------------------------------------------------- -# Status Register D -#104 7 r 0 status_d_rsvd -#111 1 r 0 valid_cmos_ram -# ----------------------------------------------------------------- -# Diagnostic Status Register -#112 8 r 0 diag_rsvd1 - -# ----------------------------------------------------------------- -0 120 r 0 reserved_memory -#120 264 r 0 unused - -# ----------------------------------------------------------------- -# RTC_BOOT_BYTE (coreboot hardcoded) -384 1 e 4 boot_option -388 4 h 0 reboot_counter -#390 2 r 0 unused? - -# ----------------------------------------------------------------- -# coreboot config options: console -#392 3 r 0 unused -395 4 e 6 debug_level -#399 1 r 0 unused - -# coreboot config options: cpu -400 1 e 2 hyper_threading -#401 7 r 0 unused - -# coreboot config options: southbridge -408 1 e 1 nmi -409 2 e 7 power_on_after_fail -#411 5 r 0 unused - -# MRC Scrambler Seed values -896 32 r 0 mrc_scrambler_seed -928 32 r 0 mrc_scrambler_seed_s3 - -# coreboot config options: check sums -984 16 h 0 check_sum -#1000 24 r 0 amd_reserved - -# ----------------------------------------------------------------- - -enumerations - -#ID value text -1 0 Disable -1 1 Enable -2 0 Enable -2 1 Disable -4 0 Fallback -4 1 Normal -6 0 Emergency -6 1 Alert -6 2 Critical -6 3 Error -6 4 Warning -6 5 Notice -6 6 Info -6 7 Debug -6 8 Spew -7 0 Disable -7 1 Enable -7 2 Keep -# ----------------------------------------------------------------- -checksums - -checksum 392 415 984 diff --git a/src/mainboard/siemens/mc_bdx1/devicetree.cb b/src/mainboard/siemens/mc_bdx1/devicetree.cb deleted file mode 100644 index fd7d83f854..0000000000 --- a/src/mainboard/siemens/mc_bdx1/devicetree.cb +++ /dev/null @@ -1,40 +0,0 @@ -chip soc/intel/fsp_broadwell_de - device cpu_cluster 0 on - device lapic 0 on end - end - device domain 0 on - device pci 00.0 on end # SoC router - device pci 14.0 on end # xHCI Controller - device pci 19.0 on end # Gigabit LAN Controller - device pci 1d.0 on end # EHCI Controller - device pci 1f.0 on # LPC Bridge - chip drivers/pc80/tpm - device pnp 0c31.0 on end - end - end # LPC Bridge - device pci 1f.2 on end # SATA Controller - device pci 1f.3 on - # Enable external RTC chip - chip drivers/i2c/rx6110sa - register "pmon_sampling" = "PMON_SAMPL_256_MS" - register "bks_on" = "0" - register "bks_off" = "1" - register "iocut_en" = "1" - register "set_user_date" = "1" - register "user_year" = "04" - register "user_month" = "07" - register "user_day" = "01" - register "user_weekday" = "4" - device i2c 0x32 on end # RTC RX6110 SA - end - #Enable I/O expander - chip drivers/i2c/pca9538 - register "in_out" = "0xff" - register "invert" = "0x00" - register "out_val" = "0x00" - device i2c 0x71 on end # I/O expander - end - end # SMBus Controller - device pci 1f.5 on end # SATA Controller - end -end diff --git a/src/mainboard/siemens/mc_bdx1/dsdt.asl b/src/mainboard/siemens/mc_bdx1/dsdt.asl deleted file mode 100644 index 1248703266..0000000000 --- a/src/mainboard/siemens/mc_bdx1/dsdt.asl +++ /dev/null @@ -1,294 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007-2009 coresystems GmbH - * Copyright (C) 2011 Google Inc. - * Copyright (C) 2015-2016 Intel Corp. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -DefinitionBlock( - "dsdt.aml", - "DSDT", - 0x02, // DSDT revision: ACPI v2.0 and up - OEM_ID, - ACPI_TABLE_CREATOR, - 0x20110725 // OEM revision -) -{ - #include "acpi/platform.asl" - - Name(_S0, Package() { 0x00, 0x00, 0x00, 0x00 }) - Name(_S5, Package() { 0x07, 0x00, 0x00, 0x00 }) - - Scope (\_SB) - { - Device (PCI0) - { - #include - #include - } - - Name (PRUN, Package() { - Package() { 0x0008FFFF, 0, \_SB.PCI0.LPC0.LNKA, 0 }, - Package() { 0x0008FFFF, 1, \_SB.PCI0.LPC0.LNKB, 0 }, - Package() { 0x0008FFFF, 2, \_SB.PCI0.LPC0.LNKC, 0 }, - Package() { 0x0008FFFF, 3, \_SB.PCI0.LPC0.LNKD, 0 }, - - Package() { 0x0009FFFF, 0, \_SB.PCI0.LPC0.LNKA, 0 }, - Package() { 0x0009FFFF, 1, \_SB.PCI0.LPC0.LNKB, 0 }, - Package() { 0x0009FFFF, 2, \_SB.PCI0.LPC0.LNKC, 0 }, - Package() { 0x0009FFFF, 3, \_SB.PCI0.LPC0.LNKD, 0 }, - - Package() { 0x000AFFFF, 0, \_SB.PCI0.LPC0.LNKA, 0 }, - Package() { 0x000AFFFF, 1, \_SB.PCI0.LPC0.LNKB, 0 }, - Package() { 0x000AFFFF, 2, \_SB.PCI0.LPC0.LNKC, 0 }, - Package() { 0x000AFFFF, 3, \_SB.PCI0.LPC0.LNKD, 0 }, - - Package() { 0x000BFFFF, 0, \_SB.PCI0.LPC0.LNKA, 0 }, - Package() { 0x000BFFFF, 1, \_SB.PCI0.LPC0.LNKB, 0 }, - Package() { 0x000BFFFF, 2, \_SB.PCI0.LPC0.LNKC, 0 }, - Package() { 0x000BFFFF, 3, \_SB.PCI0.LPC0.LNKD, 0 }, - - Package() { 0x000CFFFF, 0, \_SB.PCI0.LPC0.LNKA, 0 }, - Package() { 0x000CFFFF, 1, \_SB.PCI0.LPC0.LNKB, 0 }, - Package() { 0x000CFFFF, 2, \_SB.PCI0.LPC0.LNKC, 0 }, - Package() { 0x000CFFFF, 3, \_SB.PCI0.LPC0.LNKD, 0 }, - - Package() { 0x000DFFFF, 0, \_SB.PCI0.LPC0.LNKA, 0 }, - Package() { 0x000DFFFF, 1, \_SB.PCI0.LPC0.LNKB, 0 }, - Package() { 0x000DFFFF, 2, \_SB.PCI0.LPC0.LNKC, 0 }, - Package() { 0x000DFFFF, 3, \_SB.PCI0.LPC0.LNKD, 0 }, - - Package() { 0x000EFFFF, 0, \_SB.PCI0.LPC0.LNKA, 0 }, - Package() { 0x000EFFFF, 1, \_SB.PCI0.LPC0.LNKB, 0 }, - Package() { 0x000EFFFF, 2, \_SB.PCI0.LPC0.LNKC, 0 }, - Package() { 0x000EFFFF, 3, \_SB.PCI0.LPC0.LNKD, 0 }, - - Package() { 0x000FFFFF, 0, \_SB.PCI0.LPC0.LNKA, 0 }, - Package() { 0x000FFFFF, 1, \_SB.PCI0.LPC0.LNKB, 0 }, - Package() { 0x000FFFFF, 2, \_SB.PCI0.LPC0.LNKC, 0 }, - Package() { 0x000FFFFF, 3, \_SB.PCI0.LPC0.LNKD, 0 }, - - Package() { 0x0010FFFF, 0, \_SB.PCI0.LPC0.LNKA, 0 }, - Package() { 0x0010FFFF, 1, \_SB.PCI0.LPC0.LNKB, 0 }, - Package() { 0x0010FFFF, 2, \_SB.PCI0.LPC0.LNKC, 0 }, - Package() { 0x0010FFFF, 3, \_SB.PCI0.LPC0.LNKD, 0 }, - - Package() { 0x0011FFFF, 0, \_SB.PCI0.LPC0.LNKA, 0 }, - Package() { 0x0011FFFF, 1, \_SB.PCI0.LPC0.LNKB, 0 }, - Package() { 0x0011FFFF, 2, \_SB.PCI0.LPC0.LNKC, 0 }, - Package() { 0x0011FFFF, 3, \_SB.PCI0.LPC0.LNKD, 0 }, - - Package() { 0x0012FFFF, 0, \_SB.PCI0.LPC0.LNKA, 0 }, - Package() { 0x0012FFFF, 1, \_SB.PCI0.LPC0.LNKB, 0 }, - Package() { 0x0012FFFF, 2, \_SB.PCI0.LPC0.LNKC, 0 }, - Package() { 0x0012FFFF, 3, \_SB.PCI0.LPC0.LNKD, 0 }, - - Package() { 0x0013FFFF, 0, \_SB.PCI0.LPC0.LNKA, 0 }, - Package() { 0x0013FFFF, 1, \_SB.PCI0.LPC0.LNKB, 0 }, - Package() { 0x0013FFFF, 2, \_SB.PCI0.LPC0.LNKC, 0 }, - Package() { 0x0013FFFF, 3, \_SB.PCI0.LPC0.LNKD, 0 }, - - Package() { 0x0014FFFF, 0, \_SB.PCI0.LPC0.LNKA, 0 }, - Package() { 0x0014FFFF, 1, \_SB.PCI0.LPC0.LNKB, 0 }, - Package() { 0x0014FFFF, 2, \_SB.PCI0.LPC0.LNKC, 0 }, - Package() { 0x0014FFFF, 3, \_SB.PCI0.LPC0.LNKD, 0 }, - - Package() { 0x0016FFFF, 0, \_SB.PCI0.LPC0.LNKA, 0 }, - Package() { 0x0016FFFF, 1, \_SB.PCI0.LPC0.LNKB, 0 }, - Package() { 0x0016FFFF, 2, \_SB.PCI0.LPC0.LNKC, 0 }, - Package() { 0x0016FFFF, 3, \_SB.PCI0.LPC0.LNKD, 0 }, - - Package() { 0x0017FFFF, 0, \_SB.PCI0.LPC0.LNKA, 0 }, - Package() { 0x0017FFFF, 1, \_SB.PCI0.LPC0.LNKB, 0 }, - Package() { 0x0017FFFF, 2, \_SB.PCI0.LPC0.LNKC, 0 }, - Package() { 0x0017FFFF, 3, \_SB.PCI0.LPC0.LNKD, 0 }, - - Package() { 0x0018FFFF, 0, \_SB.PCI0.LPC0.LNKA, 0 }, - Package() { 0x0018FFFF, 1, \_SB.PCI0.LPC0.LNKB, 0 }, - Package() { 0x0018FFFF, 2, \_SB.PCI0.LPC0.LNKC, 0 }, - Package() { 0x0018FFFF, 3, \_SB.PCI0.LPC0.LNKD, 0 }, - - Package() { 0x0019FFFF, 0, \_SB.PCI0.LPC0.LNKA, 0 }, - Package() { 0x0019FFFF, 1, \_SB.PCI0.LPC0.LNKB, 0 }, - Package() { 0x0019FFFF, 2, \_SB.PCI0.LPC0.LNKC, 0 }, - Package() { 0x0019FFFF, 3, \_SB.PCI0.LPC0.LNKD, 0 }, - - Package() { 0x001CFFFF, 0, \_SB.PCI0.LPC0.LNKA, 0 }, - Package() { 0x001CFFFF, 1, \_SB.PCI0.LPC0.LNKB, 0 }, - Package() { 0x001CFFFF, 2, \_SB.PCI0.LPC0.LNKC, 0 }, - Package() { 0x001CFFFF, 3, \_SB.PCI0.LPC0.LNKD, 0 }, - - Package() { 0x001DFFFF, 0, \_SB.PCI0.LPC0.LNKA, 0 }, - Package() { 0x001DFFFF, 1, \_SB.PCI0.LPC0.LNKB, 0 }, - Package() { 0x001DFFFF, 2, \_SB.PCI0.LPC0.LNKC, 0 }, - Package() { 0x001DFFFF, 3, \_SB.PCI0.LPC0.LNKD, 0 }, - - Package() { 0x001EFFFF, 0, \_SB.PCI0.LPC0.LNKA, 0 }, - Package() { 0x001EFFFF, 1, \_SB.PCI0.LPC0.LNKB, 0 }, - Package() { 0x001EFFFF, 2, \_SB.PCI0.LPC0.LNKC, 0 }, - Package() { 0x001EFFFF, 3, \_SB.PCI0.LPC0.LNKD, 0 }, - - Package() { 0x001FFFFF, 0, \_SB.PCI0.LPC0.LNKA, 0 }, - Package() { 0x001FFFFF, 1, \_SB.PCI0.LPC0.LNKB, 0 }, - Package() { 0x001FFFFF, 2, \_SB.PCI0.LPC0.LNKC, 0 }, - Package() { 0x001FFFFF, 3, \_SB.PCI0.LPC0.LNKD, 0 }, - }) - - Name (ARUN, Package() { - Package() { 0x0008FFFF, 0, 0, 16 }, - Package() { 0x0008FFFF, 1, 0, 17 }, - Package() { 0x0008FFFF, 2, 0, 18 }, - Package() { 0x0008FFFF, 3, 0, 19 }, - - Package() { 0x0009FFFF, 0, 0, 16 }, - Package() { 0x0009FFFF, 1, 0, 17 }, - Package() { 0x0009FFFF, 2, 0, 18 }, - Package() { 0x0009FFFF, 3, 0, 19 }, - - Package() { 0x000AFFFF, 0, 0, 16 }, - Package() { 0x000AFFFF, 1, 0, 17 }, - Package() { 0x000AFFFF, 2, 0, 18 }, - Package() { 0x000AFFFF, 3, 0, 19 }, - - Package() { 0x000BFFFF, 0, 0, 16 }, - Package() { 0x000BFFFF, 1, 0, 17 }, - Package() { 0x000BFFFF, 2, 0, 18 }, - Package() { 0x000BFFFF, 3, 0, 19 }, - - Package() { 0x000CFFFF, 0, 0, 16 }, - Package() { 0x000CFFFF, 1, 0, 17 }, - Package() { 0x000CFFFF, 2, 0, 18 }, - Package() { 0x000CFFFF, 3, 0, 19 }, - - Package() { 0x000DFFFF, 0, 0, 16 }, - Package() { 0x000DFFFF, 1, 0, 17 }, - Package() { 0x000DFFFF, 2, 0, 18 }, - Package() { 0x000DFFFF, 3, 0, 19 }, - - Package() { 0x000EFFFF, 0, 0, 16 }, - Package() { 0x000EFFFF, 1, 0, 17 }, - Package() { 0x000EFFFF, 2, 0, 18 }, - Package() { 0x000EFFFF, 3, 0, 19 }, - - Package() { 0x000FFFFF, 0, 0, 16 }, - Package() { 0x000FFFFF, 1, 0, 17 }, - Package() { 0x000FFFFF, 2, 0, 18 }, - Package() { 0x000FFFFF, 3, 0, 19 }, - - Package() { 0x0010FFFF, 0, 0, 16 }, - Package() { 0x0010FFFF, 1, 0, 17 }, - Package() { 0x0010FFFF, 2, 0, 18 }, - Package() { 0x0010FFFF, 3, 0, 19 }, - - Package() { 0x0011FFFF, 0, 0, 16 }, - Package() { 0x0011FFFF, 1, 0, 17 }, - Package() { 0x0011FFFF, 2, 0, 18 }, - Package() { 0x0011FFFF, 3, 0, 19 }, - - Package() { 0x0012FFFF, 0, 0, 16 }, - Package() { 0x0012FFFF, 1, 0, 17 }, - Package() { 0x0012FFFF, 2, 0, 18 }, - Package() { 0x0012FFFF, 3, 0, 19 }, - - Package() { 0x0013FFFF, 0, 0, 16 }, - Package() { 0x0013FFFF, 1, 0, 17 }, - Package() { 0x0013FFFF, 2, 0, 18 }, - Package() { 0x0013FFFF, 3, 0, 19 }, - - Package() { 0x0014FFFF, 0, 0, 16 }, - Package() { 0x0014FFFF, 1, 0, 17 }, - Package() { 0x0014FFFF, 2, 0, 18 }, - Package() { 0x0014FFFF, 3, 0, 19 }, - - Package() { 0x0016FFFF, 0, 0, 16 }, - Package() { 0x0016FFFF, 1, 0, 17 }, - Package() { 0x0016FFFF, 2, 0, 18 }, - Package() { 0x0016FFFF, 3, 0, 19 }, - - Package() { 0x0017FFFF, 0, 0, 16 }, - Package() { 0x0017FFFF, 1, 0, 17 }, - Package() { 0x0017FFFF, 2, 0, 18 }, - Package() { 0x0017FFFF, 3, 0, 19 }, - - Package() { 0x0018FFFF, 0, 0, 16 }, - Package() { 0x0018FFFF, 1, 0, 17 }, - Package() { 0x0018FFFF, 2, 0, 18 }, - Package() { 0x0018FFFF, 3, 0, 19 }, - - Package() { 0x0019FFFF, 0, 0, 16 }, - Package() { 0x0019FFFF, 1, 0, 17 }, - Package() { 0x0019FFFF, 2, 0, 18 }, - Package() { 0x0019FFFF, 3, 0, 19 }, - - Package() { 0x001CFFFF, 0, 0, 16 }, - Package() { 0x001CFFFF, 1, 0, 17 }, - Package() { 0x001CFFFF, 2, 0, 18 }, - Package() { 0x001CFFFF, 3, 0, 19 }, - - Package() { 0x001DFFFF, 0, 0, 16 }, - Package() { 0x001DFFFF, 1, 0, 17 }, - Package() { 0x001DFFFF, 2, 0, 18 }, - Package() { 0x001DFFFF, 3, 0, 19 }, - - Package() { 0x001EFFFF, 0, 0, 16 }, - Package() { 0x001EFFFF, 1, 0, 17 }, - Package() { 0x001EFFFF, 2, 0, 18 }, - Package() { 0x001EFFFF, 3, 0, 19 }, - - Package() { 0x001FFFFF, 0, 0, 16 }, - Package() { 0x001FFFFF, 1, 0, 17 }, - Package() { 0x001FFFFF, 2, 0, 18 }, - Package() { 0x001FFFFF, 3, 0, 19 }, - }) - - Device (UNC0) - { - Name (_HID, EisaId ("PNP0A03")) - Name (_UID, 0x3F) - Method (_BBN, 0, NotSerialized) - { - Return (0xff) - } - - Name (_ADR, 0x00) - Method (_STA, 0, NotSerialized) - { - Return (0xf) - } - - Name (_CRS, ResourceTemplate () - { - WordBusNumber (ResourceProducer, MinFixed, MaxFixed, PosDecode, - 0x0000, // Granularity - 0x00FF, // Range Minimum - 0x00FF, // Range Maximum - 0x0000, // Translation Offset - 0x0001, // Length - ,, ) - }) - - Method (_PRT, 0, NotSerialized) - { - If (LEqual (PICM, Zero)) - { - Return (PRUN) - } - - Return (ARUN) - } - } - } - - #include "acpi/mainboard.asl" -} diff --git a/src/mainboard/siemens/mc_bdx1/fadt.c b/src/mainboard/siemens/mc_bdx1/fadt.c deleted file mode 100644 index 5af6056b49..0000000000 --- a/src/mainboard/siemens/mc_bdx1/fadt.c +++ /dev/null @@ -1,27 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007-2009 coresystems GmbH - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include - -void acpi_create_fadt(acpi_fadt_t *fadt, acpi_facs_t *facs, void *dsdt) -{ - acpi_header_t *header = &(fadt->header); - - acpi_fill_in_fadt(fadt, facs, dsdt); - - /* Platform specific customizations go here */ - - header->checksum = acpi_checksum((void *) fadt, sizeof(acpi_fadt_t)); -} diff --git a/src/mainboard/siemens/mc_bdx1/gpio.h b/src/mainboard/siemens/mc_bdx1/gpio.h deleted file mode 100644 index 5b5555d204..0000000000 --- a/src/mainboard/siemens/mc_bdx1/gpio.h +++ /dev/null @@ -1,92 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2017 Siemens AG - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ -#ifndef MC_BDX1_GPIO_H_ -#define MC_BDX1_GPIO_H_ - -#include - -static const struct gpio_config mc_bdx1_gpio_config[] = { - PCH_GPIO_OUT_LOW(0), - PCH_GPIO_OUT_LOW(1), - PCH_GPIO_INPUT(2), - PCH_GPIO_INPUT(3), - PCH_GPIO_INPUT(4), - PCH_GPIO_INPUT(5), - PCH_GPIO_OUT_LOW(6), - PCH_GPIO_INPUT_INVERT(7), - PCH_GPIO_OUT_LOW(8), - PCH_GPIO_NATIVE(9), - PCH_GPIO_NATIVE(10), - PCH_GPIO_NATIVE(11), - PCH_GPIO_INPUT(12), - PCH_GPIO_NATIVE(14), - PCH_GPIO_INPUT_INVERT(15), - PCH_GPIO_OUT_LOW(16), - PCH_GPIO_NATIVE(17), - PCH_GPIO_OUT_HIGH(18), - PCH_GPIO_NATIVE(19), - PCH_GPIO_NATIVE(20), - PCH_GPIO_NATIVE(21), - PCH_GPIO_NATIVE(22), - PCH_GPIO_NATIVE(23), - PCH_GPIO_INPUT(24), - PCH_GPIO_OUT_HIGH(25), - PCH_GPIO_NATIVE(26), - PCH_GPIO_INPUT(27), - PCH_GPIO_OUT_HIGH(28), - PCH_GPIO_OUT_HIGH(29), - PCH_GPIO_NATIVE(30), - PCH_GPIO_INPUT(31), - PCH_GPIO_NATIVE(32), - PCH_GPIO_NATIVE(33), - PCH_GPIO_OUT_HIGH(35), - PCH_GPIO_NATIVE(36), - PCH_GPIO_NATIVE(37), - PCH_GPIO_NATIVE(38), - PCH_GPIO_NATIVE(39), - PCH_GPIO_INPUT(40), - PCH_GPIO_INPUT(41), - PCH_GPIO_INPUT(42), - PCH_GPIO_NATIVE(43), - PCH_GPIO_NATIVE(44), - PCH_GPIO_NATIVE(45), - PCH_GPIO_NATIVE(46), - PCH_GPIO_NATIVE(48), - PCH_GPIO_INPUT(49), - PCH_GPIO_NATIVE(50), - PCH_GPIO_NATIVE(51), - PCH_GPIO_NATIVE(52), - PCH_GPIO_NATIVE(53), - PCH_GPIO_NATIVE(54), - PCH_GPIO_NATIVE(55), - PCH_GPIO_NATIVE(57), - PCH_GPIO_NATIVE(58), - PCH_GPIO_NATIVE(59), - PCH_GPIO_NATIVE(60), - PCH_GPIO_NATIVE(61), - PCH_GPIO_NATIVE(62), - PCH_GPIO_NATIVE(65), - PCH_GPIO_OUT_LOW(67), - PCH_GPIO_NATIVE(68), - PCH_GPIO_NATIVE(69), - PCH_GPIO_NATIVE(70), - PCH_GPIO_NATIVE(71), - PCH_GPIO_INPUT(72), - PCH_GPIO_NATIVE(74), - PCH_GPIO_NATIVE(75), - PCH_GPIO_END -}; - -#endif /* MC_BDX1_GPIO_H_ */ diff --git a/src/mainboard/siemens/mc_bdx1/irqroute.c b/src/mainboard/siemens/mc_bdx1/irqroute.c deleted file mode 100644 index 9b09f4bc1e..0000000000 --- a/src/mainboard/siemens/mc_bdx1/irqroute.c +++ /dev/null @@ -1,18 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2012 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include "../mc_bdx1/irqroute.h" - -DEFINE_IRQ_ROUTES; diff --git a/src/mainboard/siemens/mc_bdx1/irqroute.h b/src/mainboard/siemens/mc_bdx1/irqroute.h deleted file mode 100644 index 3b437fee55..0000000000 --- a/src/mainboard/siemens/mc_bdx1/irqroute.h +++ /dev/null @@ -1,48 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2012 Google Inc. - * Copyright (C) 2015-2016 Intel Corp. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef IRQROUTE_H -#define IRQROUTE_H - -#include -#include - -#define PCI_DEV_PIRQ_ROUTES \ - PCI_DEV_PIRQ_ROUTE(XHCI_DEV, A, B, C, D), \ - PCI_DEV_PIRQ_ROUTE(ME_DEV, A, B, C, D), \ - PCI_DEV_PIRQ_ROUTE(GBE_DEV, A, B, C, D), \ - PCI_DEV_PIRQ_ROUTE(EHCI2_DEV, A, B, C, D), \ - PCI_DEV_PIRQ_ROUTE(HDA_DEV, A, B, C, D), \ - PCI_DEV_PIRQ_ROUTE(PCIE_DEV, A, B, C, D), \ - PCI_DEV_PIRQ_ROUTE(EHCI1_DEV, A, B, C, D), \ - PCI_DEV_PIRQ_ROUTE(SATA_DEV, A, B, C, D) - -/* - * Route each PIRQ[A-H] to a PIC IRQ[0-15] - * Reserved: 0, 1, 2, 8, 13 - * ACPI/SCI: 10 - */ -#define PIRQ_PIC_ROUTES \ - PIRQ_PIC(A, 5), \ - PIRQ_PIC(B, 6), \ - PIRQ_PIC(C, 7), \ - PIRQ_PIC(D, 10), \ - PIRQ_PIC(E, 11), \ - PIRQ_PIC(F, 12), \ - PIRQ_PIC(G, 14), \ - PIRQ_PIC(H, 15) - -#endif /* IRQROUTE_H */ diff --git a/src/mainboard/siemens/mc_bdx1/mainboard.c b/src/mainboard/siemens/mc_bdx1/mainboard.c deleted file mode 100644 index 4f9c8406c6..0000000000 --- a/src/mainboard/siemens/mc_bdx1/mainboard.c +++ /dev/null @@ -1,273 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007-2009 coresystems GmbH - * Copyright (C) 2011 Google Inc. - * Copyright (C) 2016-2018 Siemens AG - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#if CONFIG(VGA_ROM_RUN) -#include -#endif -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#define MAX_PATH_DEPTH 12 -#define MAX_NUM_MAPPINGS 10 - -/* - * SPI Opcode Menu setup for SPIBAR lock down - * should support most common flash chips. - */ -#define SPI_OPMENU_0 0x01 /* WRSR: Write Status Register */ -#define SPI_OPTYPE_0 0x01 /* Write, no address */ - -#define SPI_OPMENU_1 0x02 /* BYPR: Byte Program */ -#define SPI_OPTYPE_1 0x03 /* Write, address required */ - -#define SPI_OPMENU_2 0x03 /* READ: Read Data */ -#define SPI_OPTYPE_2 0x02 /* Read, address required */ - -#define SPI_OPMENU_3 0x05 /* RDSR: Read Status Register */ -#define SPI_OPTYPE_3 0x00 /* Read, no address */ - -#define SPI_OPMENU_4 0x20 /* SE20: Sector Erase 0x20 */ -#define SPI_OPTYPE_4 0x03 /* Write, address required */ - -#define SPI_OPMENU_5 0x9f /* RDID: Read ID */ -#define SPI_OPTYPE_5 0x00 /* Read, no address */ - -#define SPI_OPMENU_6 0xd8 /* BED8: Block Erase 0xd8 */ -#define SPI_OPTYPE_6 0x03 /* Write, address required */ - -#define SPI_OPMENU_7 0x0b /* FAST: Fast Read */ -#define SPI_OPTYPE_7 0x02 /* Read, address required */ - -#define SPI_OPMENU_UPPER ((SPI_OPMENU_7 << 24) | (SPI_OPMENU_6 << 16) | \ - (SPI_OPMENU_5 << 8) | SPI_OPMENU_4) -#define SPI_OPMENU_LOWER ((SPI_OPMENU_3 << 24) | (SPI_OPMENU_2 << 16) | \ - (SPI_OPMENU_1 << 8) | SPI_OPMENU_0) - -#define SPI_OPTYPE ((SPI_OPTYPE_7 << 14) | (SPI_OPTYPE_6 << 12) | \ - (SPI_OPTYPE_5 << 10) | (SPI_OPTYPE_4 << 8) | \ - (SPI_OPTYPE_3 << 6) | (SPI_OPTYPE_2 << 4) | \ - (SPI_OPTYPE_1 << 2) | (SPI_OPTYPE_0)) - -#define SPI_OPPREFIX ((0x50 << 8) | 0x06) /* EWSR and WREN */ - -#define SPIBAR_OFFSET 0x3800 -#define SPI_REG_PREOP 0x94 -#define SPI_REG_OPTYPE 0x96 -#define SPI_REG_OPMENU_L 0x98 -#define SPI_REG_OPMENU_H 0x9c - -/* Define the slave address for the I/O expander. */ -#define PCA9538_SLAVE_ADR 0x71 -/* - * mainboard_enable is executed as first thing after enumerate_buses(). - * This is the earliest point to add customization. - */ -static void mainboard_enable(struct device *dev) -{ - -} - -static void mainboard_init(void *chip_info) -{ - uint8_t actl = 0; - struct device *dev = pcidev_on_root(LPC_DEV, LPC_FUNC); - - /* Route SCI to IRQ 10 to free IRQ 9 slot. */ - actl = pci_read_config8(dev, ACPI_CNTL_OFFSET); - actl &= ~SCIS_MASK; - actl |= SCIS_IRQ10; - pci_write_config8(dev, ACPI_CNTL_OFFSET, actl); - - /* Enable additional I/O decoding ranges on LPC for COM 3 and COM 4 */ - pci_write_config32(dev, LPC_GEN1_DEC, 0x1C02E9); - pci_write_config32(dev, LPC_GEN2_DEC, 0x1C03E9); -} - -static void mainboard_final(void *chip_info) -{ - void *spi_base = NULL; - uint32_t rcba = 0; - struct device *dev = pcidev_on_root(LPC_DEV, LPC_FUNC); - - /* Get address of SPI controller. */ - rcba = (pci_read_config32(dev, 0xf0) & 0xffffc000); - if (!rcba) - return; - spi_base = (void *)(rcba + SPIBAR_OFFSET); - /* Setup OPCODE menu */ - write16((spi_base + SPI_REG_PREOP), SPI_OPPREFIX); - write16((spi_base + SPI_REG_OPTYPE), SPI_OPTYPE); - write32((spi_base + SPI_REG_OPMENU_L), SPI_OPMENU_LOWER); - write32((spi_base + SPI_REG_OPMENU_H), SPI_OPMENU_UPPER); - - /* Set Master Enable for on-board PCI devices. */ - dev = dev_find_device(PCI_VENDOR_ID_SIEMENS, 0x403e, 0); - if (dev) { - uint16_t cmd = pci_read_config16(dev, PCI_COMMAND); - cmd |= PCI_COMMAND_MASTER; - pci_write_config16(dev, PCI_COMMAND, cmd); - } - dev = dev_find_device(PCI_VENDOR_ID_SIEMENS, 0x403f, 0); - if (dev) { - uint16_t cmd = pci_read_config16(dev, PCI_COMMAND); - cmd |= PCI_COMMAND_MASTER; - pci_write_config16(dev, PCI_COMMAND, cmd); - } - /* Show the mainboard version well-visible on console. */ - printk(BIOS_NOTICE, "***************************\n" - "* Mainboard version: 0x%02x *\n" - "***************************\n", - pca9538_read_input()); -} - -/** \brief This function can decide if a given MAC address is valid or not. - * Currently, addresses filled with 0xff or 0x00 are not valid. - * @param mac Buffer to the MAC address to check - * @return 0 if address is not valid, otherwise 1 - */ -static uint8_t is_mac_adr_valid(uint8_t mac[6]) -{ - uint8_t buf[6]; - - memset(buf, 0, sizeof(buf)); - if (!memcmp(buf, mac, sizeof(buf))) - return 0; - memset(buf, 0xff, sizeof(buf)); - if (!memcmp(buf, mac, sizeof(buf))) - return 0; - return 1; -} - /** \brief This function will search for a MAC address which can be assigned - * to a MACPHY. - * @param dev pointer to PCI device - * @param mac buffer where to store the MAC address - * @return cb_err CB_ERR or CB_SUCCESS - */ -enum cb_err mainboard_get_mac_address(struct device *dev, uint8_t mac[6]) -{ - struct bus *parent = dev->bus; - uint8_t buf[16], mapping[16], i = 0, chain_len = 0; - - memset(buf, 0, sizeof(buf)); - memset(mapping, 0, sizeof(mapping)); - - /* The first entry in the tree is the device itself. */ - buf[0] = dev->path.pci.devfn; - chain_len = 1; - for (i = 1; i < MAX_PATH_DEPTH && parent->dev->bus->subordinate; i++) { - buf[i] = parent->dev->path.pci.devfn; - chain_len++; - parent = parent->dev->bus; - } - if (i == MAX_PATH_DEPTH) { - /* The path is deeper than MAX_PATH_DEPTH devices, error. */ - printk(BIOS_ERR, "Too many bridges for %s\n", dev_path(dev)); - return CB_ERR; - } - /* Now construct the mapping based on the device chain starting from */ - /* root bridge device to the device itself. */ - mapping[0] = 1; - mapping[1] = chain_len; - for (i = 0; i < chain_len; i++) - mapping[i + 4] = buf[chain_len - i - 1]; - - /* Open main hwinfo block */ - if (hwilib_find_blocks("hwinfo.hex") != CB_SUCCESS) - return CB_ERR; - /* Now try to find a valid MAC address in hwinfo for this mapping.*/ - for (i = 0; i < MAX_NUM_MAPPINGS; i++) { - if ((hwilib_get_field(XMac1Mapping + i, buf, 16) == 16) && - !(memcmp(buf, mapping, chain_len + 4))) { - /* There is a matching mapping available, get MAC address. */ - if ((hwilib_get_field(XMac1 + i, mac, 6) == 6) && - (is_mac_adr_valid(mac))) { - return CB_SUCCESS; - } else { - return CB_ERR; - } - } else - continue; - } - /* No MAC address found for */ - return CB_ERR; -} - -static void wait_for_legacy_dev(void *unused) -{ - uint32_t legacy_delay, us_since_boot; - struct stopwatch sw; - - /* Open main hwinfo block. */ - if (hwilib_find_blocks("hwinfo.hex") != CB_SUCCESS) - return; - - /* Get legacy delay parameter from hwinfo. */ - if (hwilib_get_field(LegacyDelay, (uint8_t *) &legacy_delay, - sizeof(legacy_delay)) != sizeof(legacy_delay)) - return; - - us_since_boot = get_us_since_boot(); - /* No need to wait if the time since boot is already long enough.*/ - if (us_since_boot > legacy_delay) - return; - stopwatch_init_msecs_expire(&sw, (legacy_delay - us_since_boot) / 1000); - printk(BIOS_NOTICE, "Wait remaining %d of %d us for legacy devices...", - legacy_delay - us_since_boot, legacy_delay); - stopwatch_wait_until_expired(&sw); - printk(BIOS_NOTICE, "done!\n"); -} - -/* - * To access the I/O expander PCA9538 we need to know its device structure. - * This function will provide it as mainboard code has the knowledge of the - * right I2C slave address for the I/O expander. - */ -struct device *pca9538_get_dev(void) -{ - struct device *dev = NULL; - - while ((dev = dev_find_path(dev, DEVICE_PATH_I2C))) { - if (dev->path.i2c.device == PCA9538_SLAVE_ADR) - break; - } - return dev; -} - - -BOOT_STATE_INIT_ENTRY(BS_DEV_ENUMERATE, BS_ON_ENTRY, wait_for_legacy_dev, NULL); - -struct chip_operations mainboard_ops = { - .enable_dev = mainboard_enable, - .init = mainboard_init, - .final = mainboard_final -}; diff --git a/src/mainboard/siemens/mc_bdx1/mc_bdx1.fmd b/src/mainboard/siemens/mc_bdx1/mc_bdx1.fmd deleted file mode 100644 index 44502f607c..0000000000 --- a/src/mainboard/siemens/mc_bdx1/mc_bdx1.fmd +++ /dev/null @@ -1,25 +0,0 @@ -FLASH@0xff000000 0x1000000 { - SI_ALL 0x300000 { - SI_DESC 0x1000 - SI_ME 0x2ff000 - } - SI_BIOS 0xd00000 { - RW_MRC_CACHE 0x10000 - RW_SHARED 0x4000 { - SHARED_DATA 0x2000 - VBLOCK_DEV 0x2000 - } - RW_VPD 0x2000 - RW_NVRAM 0x2000 - WP_RO 0xce8000 { - RO_VPD 0x4000 - RO_SECTION 0xce4000 { - FMAP 0x800 - RO_FRID 0x40 - RO_FRID_PAD 0x7c0 - GBB 0xef000 - COREBOOT(CBFS) - } - } - } -} diff --git a/src/mainboard/siemens/mc_bdx1/romstage.c b/src/mainboard/siemens/mc_bdx1/romstage.c deleted file mode 100644 index eec8f04d3d..0000000000 --- a/src/mainboard/siemens/mc_bdx1/romstage.c +++ /dev/null @@ -1,48 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2013 Google Inc. - * Copyright (C) 2015 Intel Corp. - * Copyright (C) 2017 Siemens AG - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include -#include -#include "gpio.h" - -/** - * /brief mainboard call for setup that needs to be done before fsp init - * - */ -void early_mainboard_romstage_entry(void) -{ - init_gpios(mc_bdx1_gpio_config); -} - -/** - * /brief mainboard call for setup that needs to be done after fsp init - * - */ -void late_mainboard_romstage_entry(void) -{ - -} - -/** - * /brief customize fsp parameters here if needed - */ -void romstage_fsp_rt_buffer_callback(FSP_INIT_RT_BUFFER *FspRtBuffer) -{ - -} From f67c81fc7030e278cf3dbc906f9ba5e265d843f0 Mon Sep 17 00:00:00 2001 From: Arthur Heymans Date: Tue, 19 Nov 2019 18:50:20 +0100 Subject: [PATCH 0309/1242] soc/intel/fsp_broadwell_de: Drop support MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Relocatable ramstage, postcar stage and C_ENVIRONMENT_BOOTBLOCK are now mandatory features, which this platform lacks. Change-Id: I8b6502b0894f9e2b8b1334871d7b6cde65cba7d4 Signed-off-by: Arthur Heymans Reviewed-on: https://review.coreboot.org/c/coreboot/+/36984 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki Reviewed-by: David Hendricks Reviewed-by: Werner Zeh --- src/security/intel/txt/Kconfig | 4 +- src/soc/intel/fsp_broadwell_de/Kconfig | 100 ---- src/soc/intel/fsp_broadwell_de/Makefile.inc | 51 -- src/soc/intel/fsp_broadwell_de/acpi.c | 549 ------------------ .../intel/fsp_broadwell_de/acpi/irqlinks.asl | 464 --------------- src/soc/intel/fsp_broadwell_de/acpi/lpc.asl | 92 --- src/soc/intel/fsp_broadwell_de/acpi/pcie1.asl | 465 --------------- .../fsp_broadwell_de/acpi/southcluster.asl | 349 ----------- .../intel/fsp_broadwell_de/acpi/uncore.asl | 267 --------- .../fsp_broadwell_de/bootblock/bootblock.c | 23 - src/soc/intel/fsp_broadwell_de/chip.c | 93 --- src/soc/intel/fsp_broadwell_de/chip.h | 32 - src/soc/intel/fsp_broadwell_de/cpu.c | 213 ------- src/soc/intel/fsp_broadwell_de/fsp/Kconfig | 140 ----- .../intel/fsp_broadwell_de/fsp/Makefile.inc | 17 - .../fsp_broadwell_de/fsp/chipset_fsp_util.c | 142 ----- .../fsp_broadwell_de/fsp/chipset_fsp_util.h | 35 -- src/soc/intel/fsp_broadwell_de/gpio.c | 109 ---- .../intel/fsp_broadwell_de/include/soc/acpi.h | 32 - .../include/soc/broadwell_de.h | 46 -- .../intel/fsp_broadwell_de/include/soc/gpio.h | 129 ---- .../fsp_broadwell_de/include/soc/iomap.h | 71 --- .../intel/fsp_broadwell_de/include/soc/irq.h | 98 ---- .../intel/fsp_broadwell_de/include/soc/lpc.h | 126 ---- .../fsp_broadwell_de/include/soc/memory.h | 30 - .../intel/fsp_broadwell_de/include/soc/msr.h | 42 -- .../fsp_broadwell_de/include/soc/pattrs.h | 52 -- .../fsp_broadwell_de/include/soc/pci_devs.h | 147 ----- .../fsp_broadwell_de/include/soc/ramstage.h | 32 - .../fsp_broadwell_de/include/soc/romstage.h | 28 - .../fsp_broadwell_de/include/soc/smbus.h | 48 -- .../intel/fsp_broadwell_de/include/soc/smm.h | 38 -- .../intel/fsp_broadwell_de/include/soc/ubox.h | 44 -- .../intel/fsp_broadwell_de/include/soc/vtd.h | 35 -- src/soc/intel/fsp_broadwell_de/iou_complto.c | 53 -- src/soc/intel/fsp_broadwell_de/memmap.c | 60 -- src/soc/intel/fsp_broadwell_de/northcluster.c | 156 ----- src/soc/intel/fsp_broadwell_de/pmutil.c | 173 ------ src/soc/intel/fsp_broadwell_de/ramstage.c | 129 ---- .../fsp_broadwell_de/romstage/Makefile.inc | 4 - .../intel/fsp_broadwell_de/romstage/memory.c | 61 -- .../fsp_broadwell_de/romstage/romstage.c | 216 ------- src/soc/intel/fsp_broadwell_de/smbus-imc.c | 58 -- src/soc/intel/fsp_broadwell_de/smbus.c | 96 --- src/soc/intel/fsp_broadwell_de/smbus_common.c | 150 ----- src/soc/intel/fsp_broadwell_de/smi.c | 90 --- src/soc/intel/fsp_broadwell_de/smihandler.c | 106 ---- src/soc/intel/fsp_broadwell_de/smmrelocate.c | 306 ---------- src/soc/intel/fsp_broadwell_de/southcluster.c | 301 ---------- src/soc/intel/fsp_broadwell_de/tsc_freq.c | 28 - src/soc/intel/fsp_broadwell_de/ubox.c | 30 - src/soc/intel/fsp_broadwell_de/vtd.c | 59 -- 52 files changed, 1 insertion(+), 6218 deletions(-) delete mode 100644 src/soc/intel/fsp_broadwell_de/Kconfig delete mode 100644 src/soc/intel/fsp_broadwell_de/Makefile.inc delete mode 100644 src/soc/intel/fsp_broadwell_de/acpi.c delete mode 100644 src/soc/intel/fsp_broadwell_de/acpi/irqlinks.asl delete mode 100644 src/soc/intel/fsp_broadwell_de/acpi/lpc.asl delete mode 100644 src/soc/intel/fsp_broadwell_de/acpi/pcie1.asl delete mode 100644 src/soc/intel/fsp_broadwell_de/acpi/southcluster.asl delete mode 100644 src/soc/intel/fsp_broadwell_de/acpi/uncore.asl delete mode 100644 src/soc/intel/fsp_broadwell_de/bootblock/bootblock.c delete mode 100644 src/soc/intel/fsp_broadwell_de/chip.c delete mode 100644 src/soc/intel/fsp_broadwell_de/chip.h delete mode 100644 src/soc/intel/fsp_broadwell_de/cpu.c delete mode 100644 src/soc/intel/fsp_broadwell_de/fsp/Kconfig delete mode 100644 src/soc/intel/fsp_broadwell_de/fsp/Makefile.inc delete mode 100644 src/soc/intel/fsp_broadwell_de/fsp/chipset_fsp_util.c delete mode 100644 src/soc/intel/fsp_broadwell_de/fsp/chipset_fsp_util.h delete mode 100644 src/soc/intel/fsp_broadwell_de/gpio.c delete mode 100644 src/soc/intel/fsp_broadwell_de/include/soc/acpi.h delete mode 100644 src/soc/intel/fsp_broadwell_de/include/soc/broadwell_de.h delete mode 100644 src/soc/intel/fsp_broadwell_de/include/soc/gpio.h delete mode 100644 src/soc/intel/fsp_broadwell_de/include/soc/iomap.h delete mode 100644 src/soc/intel/fsp_broadwell_de/include/soc/irq.h delete mode 100644 src/soc/intel/fsp_broadwell_de/include/soc/lpc.h delete mode 100644 src/soc/intel/fsp_broadwell_de/include/soc/memory.h delete mode 100644 src/soc/intel/fsp_broadwell_de/include/soc/msr.h delete mode 100644 src/soc/intel/fsp_broadwell_de/include/soc/pattrs.h delete mode 100644 src/soc/intel/fsp_broadwell_de/include/soc/pci_devs.h delete mode 100644 src/soc/intel/fsp_broadwell_de/include/soc/ramstage.h delete mode 100644 src/soc/intel/fsp_broadwell_de/include/soc/romstage.h delete mode 100644 src/soc/intel/fsp_broadwell_de/include/soc/smbus.h delete mode 100644 src/soc/intel/fsp_broadwell_de/include/soc/smm.h delete mode 100644 src/soc/intel/fsp_broadwell_de/include/soc/ubox.h delete mode 100644 src/soc/intel/fsp_broadwell_de/include/soc/vtd.h delete mode 100644 src/soc/intel/fsp_broadwell_de/iou_complto.c delete mode 100644 src/soc/intel/fsp_broadwell_de/memmap.c delete mode 100644 src/soc/intel/fsp_broadwell_de/northcluster.c delete mode 100644 src/soc/intel/fsp_broadwell_de/pmutil.c delete mode 100644 src/soc/intel/fsp_broadwell_de/ramstage.c delete mode 100644 src/soc/intel/fsp_broadwell_de/romstage/Makefile.inc delete mode 100644 src/soc/intel/fsp_broadwell_de/romstage/memory.c delete mode 100644 src/soc/intel/fsp_broadwell_de/romstage/romstage.c delete mode 100644 src/soc/intel/fsp_broadwell_de/smbus-imc.c delete mode 100644 src/soc/intel/fsp_broadwell_de/smbus.c delete mode 100644 src/soc/intel/fsp_broadwell_de/smbus_common.c delete mode 100644 src/soc/intel/fsp_broadwell_de/smi.c delete mode 100644 src/soc/intel/fsp_broadwell_de/smihandler.c delete mode 100644 src/soc/intel/fsp_broadwell_de/smmrelocate.c delete mode 100644 src/soc/intel/fsp_broadwell_de/southcluster.c delete mode 100644 src/soc/intel/fsp_broadwell_de/tsc_freq.c delete mode 100644 src/soc/intel/fsp_broadwell_de/ubox.c delete mode 100644 src/soc/intel/fsp_broadwell_de/vtd.c diff --git a/src/security/intel/txt/Kconfig b/src/security/intel/txt/Kconfig index 97d24fd6c9..7451cca728 100644 --- a/src/security/intel/txt/Kconfig +++ b/src/security/intel/txt/Kconfig @@ -22,7 +22,7 @@ config INTEL_TXT depends on (TPM1 || TPM2) depends on CPU_INTEL_FIRMWARE_INTERFACE_TABLE depends on PLATFORM_HAS_DRAM_CLEAR - depends on SOC_INTEL_FSP_BROADWELL_DE || SOC_INTEL_COMMON_BLOCK_SA + depends on SOC_INTEL_COMMON_BLOCK_SA if INTEL_TXT @@ -30,7 +30,6 @@ menu "Intel" config INTEL_TXT_BIOSACM_FILE string "BIOS ACM file" - default "3rdparty/blobs/soc/intel/fsp_broadwell_de/biosacm.bin" if SOC_INTEL_FSP_BROADWELL_DE default "3rdparty/blobs/soc/intel/skylake/biosacm.bin" if SOC_INTEL_COMMON_SKYLAKE_BASE help Intel TXT BIOS ACM file. This file can be obtained by privileged @@ -39,7 +38,6 @@ config INTEL_TXT_BIOSACM_FILE config INTEL_TXT_SINITACM_FILE string "SINIT ACM file" - default "3rdparty/blobs/soc/intel/fsp_broadwell_de/sinitacm.bin" if SOC_INTEL_FSP_BROADWELL_DE default "3rdparty/blobs/soc/intel/skylake/sinitacm.bin" if SOC_INTEL_COMMON_SKYLAKE_BASE help Intel TXT SINIT ACM file. This file can be obtained by privileged diff --git a/src/soc/intel/fsp_broadwell_de/Kconfig b/src/soc/intel/fsp_broadwell_de/Kconfig deleted file mode 100644 index 4c45f29618..0000000000 --- a/src/soc/intel/fsp_broadwell_de/Kconfig +++ /dev/null @@ -1,100 +0,0 @@ -config SOC_INTEL_FSP_BROADWELL_DE - bool - help - Broadwell-DE support using the Intel FSP. - -if SOC_INTEL_FSP_BROADWELL_DE - -config CPU_SPECIFIC_OPTIONS - def_bool y - select ACPI_INTEL_HARDWARE_SLEEP_VALUES - select ARCH_BOOTBLOCK_X86_32 - select ARCH_VERSTAGE_X86_32 - select ARCH_ROMSTAGE_X86_32 - select ARCH_RAMSTAGE_X86_32 - select SOUTHBRIDGE_INTEL_COMMON_SPI - select SOUTHBRIDGE_INTEL_COMMON_RESET - select SOUTHBRIDGE_INTEL_COMMON_RTC - select PARALLEL_MP - select SMP - select IOAPIC - select SSE2 - select UDELAY_TSC - select SUPPORT_CPU_UCODE_IN_CBFS - select INTEL_DESCRIPTOR_MODE_CAPABLE - select HAVE_SMI_HANDLER - select TSC_MONOTONIC_TIMER - select HAVE_FSP_BIN - select CPU_INTEL_FIRMWARE_INTERFACE_TABLE - select SOC_INTEL_COMMON - select SOC_INTEL_COMMON_BLOCK - select SOC_INTEL_COMMON_BLOCK_IMC - select BOOT_DEVICE_SUPPORTS_WRITES - select BOOT_DEVICE_SPI_FLASH_RW_NOMMAP_EARLY - -config VBOOT - select VBOOT_STARTS_IN_ROMSTAGE - -config CBFS_SIZE - hex - default 0x200000 - -config HEAP_SIZE - hex - default 0x100000 - -config BOOTBLOCK_CPU_INIT - string - default "soc/intel/fsp_broadwell_de/bootblock/bootblock.c" - -config MMCONF_BASE_ADDRESS - hex - default 0x80000000 - -config MAX_CPUS - int - default 32 - -config CPU_ADDR_BITS - int - default 36 - -config VGA_BIOS - bool - default n - -config IED_REGION_SIZE - hex - default 0x400000 - -config SMM_RESERVED_SIZE - hex - default 0x100000 - -config INTEGRATED_UART - bool "Integrated UART ports" - default y - select DRIVERS_UART_8250IO - select CONSOLE_SERIAL - help - Use Broadwell-DE Integrated UART ports @3F8h and 2F8h. - -config SERIRQ_CONTINUOUS_MODE - bool - default n - help - If you set this option to y, the serial IRQ machine will be - operated in continuous mode. - -config DIMM_SPD_SIZE - int - default 512 - -config HPET_MIN_TICKS - hex - default 0x80 - -## Broadwell-DE Specific FSP Kconfig -source src/soc/intel/fsp_broadwell_de/fsp/Kconfig - -endif # SOC_INTEL_FSP_BROADWELL_DE diff --git a/src/soc/intel/fsp_broadwell_de/Makefile.inc b/src/soc/intel/fsp_broadwell_de/Makefile.inc deleted file mode 100644 index f0944da175..0000000000 --- a/src/soc/intel/fsp_broadwell_de/Makefile.inc +++ /dev/null @@ -1,51 +0,0 @@ -ifeq ($(CONFIG_SOC_INTEL_FSP_BROADWELL_DE),y) - -subdirs-y += fsp -subdirs-y += romstage -subdirs-y += ../../../cpu/intel/microcode -subdirs-y += ../../../cpu/intel/turbo -subdirs-y += ../../../cpu/x86/cache -subdirs-y += ../../../cpu/x86/lapic -subdirs-y += ../../../cpu/x86/mtrr -subdirs-y += ../../../cpu/x86/smm -subdirs-y += ../../../cpu/x86/tsc -subdirs-y += ../../../lib/fsp - -romstage-y += gpio.c -romstage-y += memmap.c -romstage-y += tsc_freq.c -romstage-y += smbus-imc.c -romstage-y += ubox.c -romstage-y += vtd.c - -postcar-y += tsc_freq.c - -ramstage-y += acpi.c -ramstage-y += chip.c -ramstage-y += cpu.c -ramstage-y += gpio.c -ramstage-y += iou_complto.c -ramstage-y += memmap.c -ramstage-y += northcluster.c -ramstage-y += ramstage.c -ramstage-y += smbus.c -ramstage-y += smbus_common.c -ramstage-y += smi.c -ramstage-y += southcluster.c -ramstage-y += tsc_freq.c -ramstage-y += vtd.c -ramstage-y += ubox.c -ramstage-$(CONFIG_HAVE_SMI_HANDLER) += pmutil.c -ramstage-$(CONFIG_HAVE_SMI_HANDLER) += smmrelocate.c - -smm-y += pmutil.c -smm-y += smihandler.c -smm-y += tsc_freq.c - -cpu_microcode_bins += $(wildcard 3rdparty/intel-microcode/intel-ucode/06-56-*) - -CPPFLAGS_common += -I$(src)/soc/intel/fsp_broadwell_de/include -CPPFLAGS_common += -I$(src)/soc/intel/fsp_broadwell_de/fsp -CPPFLAGS_common += -I$(src)/soc/intel/fsp_broadwell_de/ - -endif # ifeq ($(CONFIG_SOC_INTEL_FSP_BROADWELL_DE),y) diff --git a/src/soc/intel/fsp_broadwell_de/acpi.c b/src/soc/intel/fsp_broadwell_de/acpi.c deleted file mode 100644 index 5349c30758..0000000000 --- a/src/soc/intel/fsp_broadwell_de/acpi.c +++ /dev/null @@ -1,549 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007-2009 coresystems GmbH - * Copyright (C) 2013 Google Inc. - * Copyright (C) 2015-2016 Intel Corp. - * Copyright (C) 2016-2018 Siemens AG - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include "chip.h" - -uint16_t get_pmbase(void) -{ - return ACPI_BASE_ADDRESS; -} - -#define MWAIT_RES(state, sub_state) \ - { \ - .addrl = (((state) << 4) | (sub_state)), \ - .space_id = ACPI_ADDRESS_SPACE_FIXED, \ - .bit_width = ACPI_FFIXEDHW_VENDOR_INTEL, \ - .bit_offset = ACPI_FFIXEDHW_CLASS_MWAIT, \ - .access_size = ACPI_FFIXEDHW_FLAG_HW_COORD, \ - } - -/* C-state map */ -static acpi_cstate_t cstate_map[] = { - { - /* C1 */ - .ctype = 1, /* ACPI C1 */ - .latency = 1, - .power = 1000, - .resource = MWAIT_RES(0, 0), - }, - { - /* C3 */ - .ctype = 2, /* ACPI C2 */ - .latency = 15, - .power = 500, - .resource = MWAIT_RES(1, 0), - }, - { - /* C6 */ - .ctype = 3, /* ACPI C3 */ - .latency = 41, - .power = 350, - .resource = MWAIT_RES(2, 0), - } -}; - -static int acpi_sci_irq(void) -{ - uint8_t actl = 0; - static uint8_t sci_irq = 0; - struct device *dev = pcidev_on_root(LPC_DEV, LPC_FUNC); - - /* If this function was already called, just return the stored value. */ - if (sci_irq) - return sci_irq; - /* Get contents of ACPI control register. */ - actl = pci_read_config8(dev, ACPI_CNTL_OFFSET) & SCIS_MASK; - /* Determine how SCI is routed. */ - switch (actl) { - case SCIS_IRQ9: - case SCIS_IRQ10: - case SCIS_IRQ11: - sci_irq = actl + 9; - break; - case SCIS_IRQ20: - case SCIS_IRQ21: - case SCIS_IRQ22: - case SCIS_IRQ23: - sci_irq = actl - SCIS_IRQ20 + 20; - break; - default: - printk(BIOS_DEBUG, "Invalid SCI route! Defaulting to IRQ9.\n"); - sci_irq = 9; - break; - } - printk(BIOS_DEBUG, "SCI is IRQ%d\n", sci_irq); - return sci_irq; -} - -unsigned long acpi_fill_mcfg(unsigned long current) -{ - current += acpi_create_mcfg_mmconfig((acpi_mcfg_mmconfig_t *)current, - MCFG_BASE_ADDRESS, 0, 0, 255); - return current; -} - -/** - * Fill in the fadt with generic values that can be overridden later. - */ - -void acpi_fill_in_fadt(acpi_fadt_t *fadt, acpi_facs_t *facs, void *dsdt) -{ - acpi_header_t *header = &(fadt->header); - u16 pmbase = get_pmbase(); - - memset((void *) fadt, 0, sizeof(acpi_fadt_t)); - - /* - * Reference section 5.2.9 Fixed ACPI Description Table (FADT) - * in the ACPI 3.0b specification. - */ - - /* FADT Header Structure */ - memcpy(header->signature, "FACP", 4); - header->length = sizeof(acpi_fadt_t); - header->revision = get_acpi_table_revision(FADT); - memcpy(header->oem_id, OEM_ID, 6); - memcpy(header->oem_table_id, ACPI_TABLE_CREATOR, 8); - memcpy(header->asl_compiler_id, ASLC, 4); - header->asl_compiler_revision = asl_revision; - - /* ACPI Pointers */ - fadt->firmware_ctrl = (unsigned long) facs; - fadt->dsdt = (unsigned long) dsdt; - - fadt->reserved = 0; /* reserved, should be 0 ACPI 3.0 */ - fadt->preferred_pm_profile = 0; - fadt->sci_int = acpi_sci_irq(); - - /* System Management */ - fadt->smi_cmd = 0x00; /* disable SMM */ - fadt->acpi_enable = 0x00; /* unused if SMI_CMD = 0 */ - fadt->acpi_disable = 0x00; /* unused if SMI_CMD = 0 */ - - /* Enable ACPI */ - outl(inl(pmbase + 4) | 0x01, pmbase + 4); - - /* Power Control */ - fadt->s4bios_req = 0x00; - fadt->pstate_cnt = 0x00; - - /* Control Registers - Base Address */ - fadt->pm1a_evt_blk = pmbase + PM1_STS; - fadt->pm1b_evt_blk = 0x00; /* Not Used */ - fadt->pm1a_cnt_blk = pmbase + PM1_CNT; - fadt->pm1b_cnt_blk = 0x00; /* Not Used */ - fadt->pm2_cnt_blk = pmbase + PM2A_CNT_BLK; - fadt->pm_tmr_blk = pmbase + PM1_TMR; - fadt->gpe0_blk = pmbase + GPE0_STS; - fadt->gpe1_blk = 0x00; /* Not Used */ - - /* Control Registers - Length */ - fadt->pm1_evt_len = 4; /* 32 bits */ - fadt->pm1_cnt_len = 2; /* 32 bit register, 16 bits used */ - fadt->pm2_cnt_len = 1; /* 8 bits */ - fadt->pm_tmr_len = 4; /* 32 bits */ - fadt->gpe0_blk_len = 8; /* 64 bits */ - fadt->gpe1_blk_len = 0; - fadt->gpe1_base = 0; - fadt->cst_cnt = 0; - fadt->p_lvl2_lat = ACPI_FADT_C2_NOT_SUPPORTED; - fadt->p_lvl3_lat = ACPI_FADT_C3_NOT_SUPPORTED; - fadt->flush_size = 0; /* set to 0 if WBINVD is 1 in flags */ - fadt->flush_stride = 0; /* set to 0 if WBINVD is 1 in flags */ - fadt->duty_offset = 1; - fadt->duty_width = 0; - - /* RTC Registers */ - fadt->day_alrm = 0x0D; - fadt->mon_alrm = 0x00; - fadt->century = 0x00; - fadt->iapc_boot_arch = ACPI_FADT_LEGACY_FREE; - - fadt->flags = ACPI_FADT_WBINVD | ACPI_FADT_C1_SUPPORTED | - ACPI_FADT_C2_MP_SUPPORTED | ACPI_FADT_SLEEP_BUTTON | - ACPI_FADT_RESET_REGISTER | ACPI_FADT_SLEEP_TYPE | - ACPI_FADT_S4_RTC_WAKE | ACPI_FADT_PLATFORM_CLOCK; - - /* Reset Register */ - fadt->reset_reg.space_id = ACPI_ADDRESS_SPACE_IO; - fadt->reset_reg.bit_width = 8; - fadt->reset_reg.bit_offset = 0; - fadt->reset_reg.access_size = ACPI_ACCESS_SIZE_BYTE_ACCESS; - fadt->reset_reg.addrl = 0xCF9; - fadt->reset_reg.addrh = 0x00; - fadt->reset_value = 6; - - fadt->ARM_boot_arch = 0; /* MUST be 0 ACPI 3.0 */ - fadt->FADT_MinorVersion = 0; /* MUST be 0 ACPI 3.0 */ - - /* Extended ACPI Pointers */ - fadt->x_firmware_ctl_l = (unsigned long)facs; - fadt->x_firmware_ctl_h = 0x00; - fadt->x_dsdt_l = (unsigned long)dsdt; - fadt->x_dsdt_h = 0x00; - - /* PM1 Status & PM1 Enable */ - fadt->x_pm1a_evt_blk.space_id = ACPI_ADDRESS_SPACE_IO; - fadt->x_pm1a_evt_blk.bit_width = fadt->pm1_evt_len * 8; - fadt->x_pm1a_evt_blk.bit_offset = 0; - fadt->x_pm1a_evt_blk.access_size = ACPI_ACCESS_SIZE_DWORD_ACCESS; - fadt->x_pm1a_evt_blk.addrl = fadt->pm1a_evt_blk; - fadt->x_pm1a_evt_blk.addrh = 0x00; - - fadt->x_pm1b_evt_blk.space_id = ACPI_ADDRESS_SPACE_IO; - fadt->x_pm1b_evt_blk.bit_width = 0; - fadt->x_pm1b_evt_blk.bit_offset = 0; - fadt->x_pm1b_evt_blk.access_size = 0; - fadt->x_pm1b_evt_blk.addrl = fadt->pm1b_evt_blk; - fadt->x_pm1b_evt_blk.addrh = 0x00; - - /* PM1 Control Registers */ - fadt->x_pm1a_cnt_blk.space_id = ACPI_ADDRESS_SPACE_IO; - fadt->x_pm1a_cnt_blk.bit_width = 16; - fadt->x_pm1a_cnt_blk.bit_offset = 0; - fadt->x_pm1a_cnt_blk.access_size = ACPI_ACCESS_SIZE_WORD_ACCESS; - fadt->x_pm1a_cnt_blk.addrl = fadt->pm1a_cnt_blk; - fadt->x_pm1a_cnt_blk.addrh = 0x00; - - fadt->x_pm1b_cnt_blk.space_id = ACPI_ADDRESS_SPACE_IO; - fadt->x_pm1b_cnt_blk.bit_width = 0; - fadt->x_pm1b_cnt_blk.bit_offset = 0; - fadt->x_pm1b_cnt_blk.access_size = 0; - fadt->x_pm1b_cnt_blk.addrl = fadt->pm1b_cnt_blk; - fadt->x_pm1b_cnt_blk.addrh = 0x00; - - /* PM2 Control Registers */ - fadt->x_pm2_cnt_blk.space_id = ACPI_ADDRESS_SPACE_IO; - fadt->x_pm2_cnt_blk.bit_width = 8; - fadt->x_pm2_cnt_blk.bit_offset = 0; - fadt->x_pm2_cnt_blk.access_size = ACPI_ACCESS_SIZE_BYTE_ACCESS; - fadt->x_pm2_cnt_blk.addrl = fadt->pm2_cnt_blk; - fadt->x_pm2_cnt_blk.addrh = 0x00; - - /* PM1 Timer Register */ - fadt->x_pm_tmr_blk.space_id = ACPI_ADDRESS_SPACE_IO; - fadt->x_pm_tmr_blk.bit_width = 32; - fadt->x_pm_tmr_blk.bit_offset = 0; - fadt->x_pm_tmr_blk.access_size = ACPI_ACCESS_SIZE_DWORD_ACCESS; - fadt->x_pm_tmr_blk.addrl = fadt->pm_tmr_blk; - fadt->x_pm_tmr_blk.addrh = 0x00; - - /* General-Purpose Event Registers */ - fadt->x_gpe0_blk.space_id = ACPI_ADDRESS_SPACE_IO; - fadt->x_gpe0_blk.bit_width = 64; /* EventStatus + EventEnable */ - fadt->x_gpe0_blk.bit_offset = 0; - fadt->x_gpe0_blk.access_size = ACPI_ACCESS_SIZE_DWORD_ACCESS; - fadt->x_gpe0_blk.addrl = fadt->gpe0_blk; - fadt->x_gpe0_blk.addrh = 0x00; - - fadt->x_gpe1_blk.space_id = ACPI_ADDRESS_SPACE_IO; - fadt->x_gpe1_blk.bit_width = 0; - fadt->x_gpe1_blk.bit_offset = 0; - fadt->x_gpe1_blk.access_size = 0; - fadt->x_gpe1_blk.addrl = fadt->gpe1_blk; - fadt->x_gpe1_blk.addrh = 0x00; -} - -static unsigned long acpi_fill_dmar(unsigned long current) -{ - uint32_t vtbar, tmp = current; - struct device *dev = pcidev_path_on_root(IIO_DEVFN_VTD); - uint16_t bdf, hpet_bdf[8]; - uint8_t i, j; - - if (!dev) - return current; - - vtbar = pci_read_config32(dev, VTBAR_OFFSET) & VTBAR_MASK; - if (!vtbar) - return current; - - current += acpi_create_dmar_drhd(current, - DRHD_INCLUDE_PCI_ALL, 0, vtbar); - /* The IIO I/O APIC is fixed on PCI 00:05.4 on Broadwell-DE */ - current += acpi_create_dmar_ds_ioapic(current, - 9, 0, 5, 4); - /* Get the PCI BDF for the PCH I/O APIC */ - dev = pcidev_path_on_root(PCH_DEVFN_LPC); - bdf = pci_read_config16(dev, 0x6c); - current += acpi_create_dmar_ds_ioapic(current, - 8, (bdf >> 8), PCI_SLOT(bdf), PCI_FUNC(bdf)); - - /* - * Check if there are different PCI paths for the 8 HPET timers - * and add every different PCI path as a separate HPET entry. - * Although the DMAR specification talks about HPET block for this - * entry, it is possible to assign a unique PCI BDF to every single - * timer within a HPET block which will result in different source - * IDs reported by a generated MSI. - * In default configuration every single timer will have the same - * PCI BDF which will result in a single HPET entry in DMAR table. - * I have checked several different systems and all of them had one - * single entry for HPET in DMAR. - */ - memset(hpet_bdf, 0, sizeof(hpet_bdf)); - /* Get all unique HPET paths. */ - for (i = 0; i < ARRAY_SIZE(hpet_bdf); i++) { - bdf = pci_read_config16(dev, 0x70 + (i * 2)); - for (j = 0; j < i; j++) { - if (hpet_bdf[j] == bdf) - break; - } - if (j == i) - hpet_bdf[i] = bdf; - } - /* Create one HPET entry in DMAR for every unique HPET PCI path. */ - for (i = 0; i < ARRAY_SIZE(hpet_bdf); i++) { - if (hpet_bdf[i]) - current += acpi_create_dmar_ds_msi_hpet(current, - 0, (hpet_bdf[i] >> 8), PCI_SLOT(hpet_bdf[i]), - PCI_FUNC(hpet_bdf[i])); - } - acpi_dmar_drhd_fixup(tmp, current); - - /* Create root port ATSR capability */ - tmp = current; - current += acpi_create_dmar_atsr(current, 0, 0); - /* Add one entry to ATSR for each PCI root port */ - dev = all_devices; - do { - dev = dev_find_class(PCI_CLASS_BRIDGE_PCI << 8, dev); - if (dev && dev->bus->secondary == 0 && - PCI_SLOT(dev->path.pci.devfn) <= 3) - current += acpi_create_dmar_ds_pci_br(current, - dev->bus->secondary, - PCI_SLOT(dev->path.pci.devfn), - PCI_FUNC(dev->path.pci.devfn)); - } while (dev); - acpi_dmar_atsr_fixup(tmp, current); - - return current; -} - -unsigned long vtd_write_acpi_tables(struct device *const dev, - unsigned long current, - struct acpi_rsdp *const rsdp) -{ - acpi_dmar_t *const dmar = (acpi_dmar_t *)current; - - /* Create DMAR table only if virtualization is enabled */ - if (!(pci_read_config32(dev, VTBAR_OFFSET) & VTBAR_ENABLED)) - return current; - - printk(BIOS_DEBUG, "ACPI: * DMAR\n"); - acpi_create_dmar(dmar, DMAR_INTR_REMAP, acpi_fill_dmar); - current += dmar->header.length; - current = acpi_align_current(current); - acpi_add_table(rsdp, dmar); - current = acpi_align_current(current); - - return current; -} - -static int calculate_power(int tdp, int p1_ratio, int ratio) -{ - u32 m; - u32 power; - - /* - * M = ((1.1 - ((p1_ratio - ratio) * 0.00625)) / 1.1) ^ 2 - * - * Power = (ratio / p1_ratio) * m * tdp - */ - - m = (110000 - ((p1_ratio - ratio) * 625)) / 11; - m = (m * m) / 1000; - - power = ((ratio * 100000 / p1_ratio) / 100); - power *= (m / 100) * (tdp / 1000); - power /= 1000; - - return (int)power; -} - -static void generate_P_state_entries(int core, int cores_per_package) -{ - int ratio_min, ratio_max, ratio_step; - int coord_type, power_max, power_unit, num_entries; - int ratio, power, clock; - int turbo; - u32 control_status; - msr_t msr; - - /* Hardware coordination of P-states */ - coord_type = HW_ALL; - - /* Check for Turbo Mode */ - turbo = get_turbo_state() == TURBO_ENABLED; - - /* CPU attributes */ - msr = rdmsr(MSR_PLATFORM_INFO); - ratio_min = (msr.hi >> 8) & 0xff; // LFM - ratio_max = (msr.lo >> 8) & 0xff; // HFM - - /* Calculate CPU TDP in mW */ - msr = rdmsr(MSR_PKG_POWER_SKU_UNIT); - power_unit = 1 << (msr.lo & 0xf); - msr = rdmsr(MSR_PKG_POWER_LIMIT); - power_max = ((msr.lo & 0x7fff) / power_unit) * 1000; - - /* Write _PCT indicating use of FFixedHW */ - acpigen_write_empty_PCT(); - - /* Write _PPC starting from first supported P-state */ - acpigen_write_PPC(0); - - /* Write PSD indicating configured coordination type */ - acpigen_write_PSD_package(core, 1, coord_type); - - /* Add P-state entries in _PSS table */ - acpigen_write_name("_PSS"); - - /* Determine ratio points */ - /* Note: There should be at most 16 performance states. If Turbo Mode - is enabled, the Max Turbo Ratio will occupy one of these states. */ - ratio_step = 1; - num_entries = (ratio_max - ratio_min) / ratio_step; - while (num_entries > (15-turbo)) { - ratio_step <<= 1; - num_entries >>= 1; - } - - if (turbo) { - /* _PSS package count (with turbo) */ - acpigen_write_package(num_entries + 2); - - /* Get Max Turbo Ratio */ - msr = rdmsr(MSR_TURBO_RATIO_LIMIT); - ratio = msr.lo & 0xff; - - acpigen_write_PSS_package( - ratio * 100, /* MHz */ - power_max, /* mW */ - 10, /* lat1 */ - 10, /* lat2 */ - ratio << 8, /* control */ - ratio << 8); /* status */ - } else { - /* _PSS package count (without turbo) */ - acpigen_write_package(num_entries + 1); - } - - /* Generate the _PSS entries */ - for (ratio = ratio_min + (num_entries * ratio_step); - ratio >= ratio_min; ratio -= ratio_step) { - - /* Calculate power at this ratio */ - power = calculate_power(power_max, ratio_max, ratio); - clock = ratio * 100; - control_status = ratio << 8; - - acpigen_write_PSS_package( - clock, /* MHz */ - power, /* mW */ - 10, /* lat1 */ - 10, /* lat2 */ - control_status, /* control */ - control_status); /* status */ - } - - /* Fix package length */ - acpigen_pop_len(); -} - -void generate_cpu_entries(struct device *device) -{ - int core; - int pcontrol_blk = get_pmbase(), plen = 6; - const struct pattrs *pattrs = pattrs_get(); - - for (core = 0; core < pattrs->num_cpus; core++) { - if (core > 0) { - pcontrol_blk = 0; - plen = 0; - } - - /* Generate processor \_PR.CP0x */ - acpigen_write_processor(core, pcontrol_blk, plen); - - /* Generate P-state tables */ - generate_P_state_entries(core, pattrs->num_cpus); - - /* Generate C-state tables */ - acpigen_write_CST_package(cstate_map, ARRAY_SIZE(cstate_map)); - - acpigen_pop_len(); - } -} - -unsigned long acpi_madt_irq_overrides(unsigned long current) -{ - int sci_irq = acpi_sci_irq(); - acpi_madt_irqoverride_t *irqovr; - uint16_t sci_flags = MP_IRQ_TRIGGER_LEVEL; - - /* INT_SRC_OVR */ - irqovr = (void *)current; - current += acpi_create_madt_irqoverride(irqovr, 0, 0, 2, 0); - - if (sci_irq >= 20) - sci_flags |= MP_IRQ_POLARITY_LOW; - else - sci_flags |= MP_IRQ_POLARITY_HIGH; - - irqovr = (void *)current; - current += acpi_create_madt_irqoverride(irqovr, 0, sci_irq, sci_irq, - sci_flags); - - return current; -} - -unsigned long southcluster_write_acpi_tables(struct device *device, - unsigned long current, - acpi_rsdp_t *rsdp) -{ - current = acpi_write_hpet(device, current, rsdp); - current = acpi_align_current(current); - - printk(BIOS_DEBUG, "current = %lx\n", current); - return current; -} diff --git a/src/soc/intel/fsp_broadwell_de/acpi/irqlinks.asl b/src/soc/intel/fsp_broadwell_de/acpi/irqlinks.asl deleted file mode 100644 index 7d02eb0437..0000000000 --- a/src/soc/intel/fsp_broadwell_de/acpi/irqlinks.asl +++ /dev/null @@ -1,464 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007-2009 coresystems GmbH - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -OperationRegion (PRR0, PCI_Config, 0x00, 0x100) -Field (PRR0, AnyAcc, NoLock, Preserve) { - Offset(0x60), - PIRA, 8, - PIRB, 8, - PIRC, 8, - PIRD, 8, - Offset(0x68), - PIRE, 8, - PIRF, 8, - PIRG, 8, - PIRH, 8 -} - -Device (LNKA) { // PCI IRQ link A - Name (_HID,EISAID("PNP0C0F")) - //Name(_UID, 1) - Method (_STA,0,NotSerialized) { - If(And(PIRA, 0x80)) { - Return (0x9) - } Else { - Return (0xB) - } // Don't display - } - - Method (_DIS,0,NotSerialized) { - Or (PIRA, 0x80, PIRA) - } - - Method (_CRS,0,Serialized) { - Name (BUF0, ResourceTemplate() {IRQ(Level,ActiveLow,Shared){0}}) - // - // Define references to buffer elements - // - CreateWordField (BUF0, 0x01, IRQW) // IRQ low - // - // Write current settings into IRQ descriptor - // - If (And(PIRA, 0x80)) { - Store (Zero, Local0) - } Else { - Store (One,Local0) - } - // - // Shift 1 by value in register 70, Save in buffer - // - ShiftLeft (Local0,And (PIRA,0x0F),IRQW) // Save in buffer - Return (BUF0) // Return Buf0 - } // End of _CRS method - - Name (_PRS, ResourceTemplate() - {IRQ(Level,ActiveLow,Shared){3,4,5,6,7,9,10,11,12,14,15}}) - - Method (_SRS,1,NotSerialized) { - CreateWordField (ARG0, 0x01, IRQW) // IRQ low - - FindSetRightBit(IRQW,Local0) // Set IRQ - If (LNotEqual (IRQW,Zero)){ - And (Local0, 0x7F,Local0) - Decrement (Local0) - } Else { - Or (Local0, 0x80,Local0) - } - Store (Local0, PIRA) - } // End of _SRS Method -} - -Device(LNKB) { // PCI IRQ link B - Name (_HID,EISAID("PNP0C0F")) - //Name(_UID, 2) - Method (_STA,0,NotSerialized) { - If (And (PIRB, 0x80)) { - Return (0x9) - } Else { - Return (0xB) - } // Don't display - } - - Method (_DIS,0,NotSerialized) { - Or (PIRB, 0x80,PIRB) - } - - Method (_CRS,0,Serialized) { - Name(BUF0, ResourceTemplate() - {IRQ(Level,ActiveLow,Shared){0}}) - // - // Define references to buffer elements - // - CreateWordField (BUF0, 0x01, IRQW) // IRQ low - // - // Write current settings into IRQ descriptor - // - If (And (PIRB, 0x80)) { - Store (Zero, Local0) - } Else { - Store (One,Local0) - } - // - // Shift 1 by value in register 70, Save in buffer - // - ShiftLeft (Local0,And (PIRB,0x0F),IRQW) // Save in buffer - Return (BUF0) // Return Buf0 - } // End of _CRS method - - Name (_PRS, - ResourceTemplate() - {IRQ(Level,ActiveLow,Shared){3,4,5,6,7,9,10,11,12,14,15}}) - - Method (_SRS,1,NotSerialized) { - CreateWordField (ARG0, 0x01, IRQW) // IRQ low - - FindSetRightBit(IRQW,Local0) // Set IRQ - If (LNotEqual(IRQW,Zero)) { - And (Local0, 0x7F, Local0) - Decrement (Local0) - } Else { - Or (Local0, 0x80, Local0) - } - Store (Local0, PIRB) - } // End of _SRS Method -} - -Device(LNKC) { // PCI IRQ link C - Name(_HID, EISAID("PNP0C0F")) - //Name(_UID, 3) - - Method (_STA,0,NotSerialized) { - If (And (PIRC, 0x80)) { - Return (0x9) - } Else { - Return (0xB) - } // Don't display - } - - Method (_DIS, 0, NotSerialized) { - Or (PIRC, 0x80, PIRC) - } - - Method (_CRS, 0, Serialized) { - Name (BUF0, ResourceTemplate() - {IRQ(Level,ActiveLow,Shared){0}}) - // - // Define references to buffer elements - // - CreateWordField (BUF0, 0x01, IRQW) // IRQ low - // - // Write current settings into IRQ descriptor - // - If (And (PIRC, 0x80)) { - Store (Zero, Local0) - } Else { - Store (One,Local0) - } - // - // Shift 1 by value in register 70, Save in buffer - // - ShiftLeft (Local0,And (PIRC,0x0F),IRQW) - Return (BUF0) - } // End of _CRS method - - Name (_PRS, ResourceTemplate() - {IRQ(Level,ActiveLow,Shared){3,4,5,6,7,9,10,11,12,14,15}}) - - Method (_SRS,1,NotSerialized) { - CreateWordField (ARG0, 0x01, IRQW) // IRQ low - FindSetRightBit(IRQW,Local0) // Set IRQ - If (LNotEqual (IRQW,Zero)) { - And (Local0, 0x7F, Local0) - Decrement (Local0) - } Else { - Or (Local0, 0x80,Local0) - } - Store (Local0, PIRC) - } // End of _SRS Method -} - -Device (LNKD) { // PCI IRQ link D - Name (_HID,EISAID ("PNP0C0F")) - - //Name(_UID, 4) - - Method (_STA, 0, NotSerialized) { - If (And (PIRD, 0x80)) { - Return (0x9) - } Else { - Return (0xB) - } // Don't display - } - - Method (_DIS, 0, NotSerialized) { - Or(PIRD, 0x80,PIRD) - } - - Method (_CRS,0,Serialized) { - Name (BUF0, ResourceTemplate() - {IRQ(Level,ActiveLow,Shared){0}}) - // - // Define references to buffer elements - // - CreateWordField (BUF0, 0x01, IRQW) // IRQ low - // - // Write current settings into IRQ descriptor - // - If (And (PIRD, 0x80)) { - Store (Zero, Local0) - } Else { - Store (One,Local0) - } - // - // Shift 1 by value in register 70, Save in buffer - // - ShiftLeft (Local0, And (PIRD,0x0F), IRQW) - Return (BUF0) // Return Buf0 - } // End of _CRS method - - Name (_PRS, ResourceTemplate() - {IRQ(Level,ActiveLow,Shared){3,4,5,6,7,9,10,11,12,14,15}}) - - Method (_SRS,1,NotSerialized) { - CreateWordField (ARG0, 0x01, IRQW) // IRQ low - FindSetRightBit (IRQW, Local0)// Set IRQ - If (LNotEqual (IRQW, Zero)) { - And (Local0, 0x7F, Local0) - Decrement (Local0) - } Else { - Or (Local0, 0x80, Local0) - } - Store(Local0, PIRD) - } // End of _SRS Method -} - -Device(LNKE) { // PCI IRQ link E - Name(_HID,EISAID("PNP0C0F")) - - //Name(_UID, 5) - - Method (_STA,0,NotSerialized) { - If (And (PIRE, 0x80)) { - Return(0x9) - } Else { - Return(0xB) - } // Don't display - } - - Method (_DIS,0,NotSerialized) { - Or (PIRE, 0x80, PIRE) - } - - Method (_CRS, 0, Serialized) { - Name (BUF0, ResourceTemplate() - {IRQ(Level,ActiveLow,Shared){0}}) - // - // Define references to buffer elements - // - CreateWordField (BUF0, 0x01, IRQW) // IRQ low - // - // Write current settings into IRQ descriptor - // - If (And (PIRE, 0x80)) { - Store (Zero, Local0) - } Else { - Store (One, Local0) - } - // - // Shift 1 by value in register 70, Save in buffer - // - ShiftLeft (Local0, And (PIRE,0x0F), IRQW) - Return (BUF0) // Return Buf0 - } // End of _CRS method - - Name(_PRS, ResourceTemplate() - {IRQ(Level,ActiveLow,Shared){3,4,5,6,7,9,10,11,12,14,15}}) - - Method (_SRS,1,NotSerialized) { - CreateWordField (ARG0, 0x01, IRQW) // IRQ low - FindSetRightBit (IRQW, Local0) // Set IRQ - If (LNotEqual (IRQW, Zero)) { - And (Local0, 0x7F, Local0) - Decrement (Local0) - } Else { - Or (Local0, 0x80, Local0) - } - Store (Local0, PIRE) - } // End of _SRS Method -} - -Device(LNKF) { // PCI IRQ link F - Name (_HID,EISAID("PNP0C0F")) - - //Name(_UID, 6) - - Method (_STA,0,NotSerialized) { - If (And (PIRF, 0x80)) { - Return (0x9) - } Else { - Return (0xB) - } // Don't display - } - - Method (_DIS,0,NotSerialized) { - Or (PIRB, 0x80, PIRF) - } - - Method (_CRS,0,Serialized) { - Name(BUF0, ResourceTemplate() - {IRQ(Level,ActiveLow,Shared){0}}) - // - // Define references to buffer elements - // - CreateWordField (BUF0, 0x01, IRQW) // IRQ low - // - // Write current settings into IRQ descriptor - // - If (And (PIRF, 0x80)) { - Store (Zero, Local0) - } Else { - Store (One, Local0) - } - // - // Shift 1 by value in register 70, Save in buffer - // - ShiftLeft (Local0, And (PIRF, 0x0F),IRQW) - Return (BUF0) - } // End of _CRS method - - Name(_PRS, ResourceTemplate() - {IRQ(Level,ActiveLow,Shared){3,4,5,6,7,9,10,11,12,14,15}}) - - Method (_SRS,1,NotSerialized) { - CreateWordField (ARG0, 0x01, IRQW) // IRQ low - FindSetRightBit (IRQW,Local0) // Set IRQ - If (LNotEqual (IRQW,Zero)) { - And (Local0, 0x7F,Local0) - Decrement (Local0) - } Else { - Or (Local0, 0x80, Local0) - } - Store (Local0, PIRF) - } // End of _SRS Method -} - -Device(LNKG) { // PCI IRQ link G - Name(_HID,EISAID("PNP0C0F")) - //Name(_UID, 7) - Method(_STA,0,NotSerialized) { - If (And (PIRG, 0x80)) { - Return (0x9) - } Else { - Return (0xB) - } // Don't display - } - - Method (_DIS, 0, NotSerialized) { - Or(PIRG, 0x80,PIRG) - } - - Method (_CRS,0,Serialized){ - Name(BUF0,ResourceTemplate() - {IRQ(Level,ActiveLow,Shared){0}}) - // - // Define references to buffer elements - // - CreateWordField (BUF0, 0x01, IRQW) // IRQ low - // - // Write current settings into IRQ descriptor - // - If (And(PIRG, 0x80)) { - Store(Zero, Local0) - } Else { - Store(One,Local0) - } - // - // Shift 1 by value in register 70, Save in buffer - // - ShiftLeft (Local0,And(PIRG,0x0F),IRQW) - Return (BUF0) - } // End of _CRS method - - Name (_PRS, ResourceTemplate() - {IRQ(Level,ActiveLow,Shared){3,4,5,6,7,9,10,11,12,14,15}}) - - Method (_SRS,1,NotSerialized) { - CreateWordField (ARG0, 0x01, IRQW) // IRQ low - FindSetRightBit(IRQW,Local0) // Set IRQ - If (LNotEqual (IRQW,Zero)) { - And (Local0, 0x7F,Local0) - Decrement (Local0) - } Else { - Or (Local0, 0x80,Local0) - } - Store (Local0, PIRG) - } // End of _SRS Method -} - -Device(LNKH) { // PCI IRQ link H - Name (_HID,EISAID("PNP0C0F")) - - //Name(_UID, 8) - - Method (_STA,0,NotSerialized) { - If (And(PIRH, 0x80)) { - Return(0x9) - } Else { - Return(0xB) - } // Don't display - } - - Method (_DIS,0,NotSerialized) { - Or(PIRH, 0x80,PIRH) - } - - Method (_CRS,0,Serialized) { - Name(BUF0, ResourceTemplate() - {IRQ(Level,ActiveLow,Shared){0}}) - // - // Define references to buffer elements - // - CreateWordField (BUF0, 0x01, IRQW) // IRQ low - // - // Write current settings into IRQ descriptor - // - If (And (PIRH, 0x80)) { - Store (Zero, Local0) - } Else { - Store (One,Local0) - } - // - // Shift 1 by value in register 70, Save in buffer - // - ShiftLeft (Local0,And(PIRH,0x0F),IRQW) - Return (BUF0) - } // End of _CRS method - - Name(_PRS, ResourceTemplate() - {IRQ(Level,ActiveLow,Shared){3,4,5,6,7,9,10,11,12,14,15}}) - - Method (_SRS,1,NotSerialized) { - CreateWordField (ARG0, 0x01, IRQW) // IRQ low - FindSetRightBit (IRQW,Local0)// Set IRQ - If (LNotEqual (IRQW,Zero)) { - And (Local0, 0x7F,Local0) - Decrement (Local0) - } Else { - Or (Local0, 0x80,Local0) - } - Store (Local0, PIRH) - } -} diff --git a/src/soc/intel/fsp_broadwell_de/acpi/lpc.asl b/src/soc/intel/fsp_broadwell_de/acpi/lpc.asl deleted file mode 100644 index ef1e655100..0000000000 --- a/src/soc/intel/fsp_broadwell_de/acpi/lpc.asl +++ /dev/null @@ -1,92 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007-2009 coresystems GmbH - * Copyright (C) 2013 Google Inc. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -/* Intel LPC Bus Device - 0:1f.0 */ - -Device (LPC0) -{ - Name(_ADR, 0x001f0000) - - #include "irqlinks.asl" - - Device (FWH) // Firmware Hub - { - Name (_HID, EISAID("INT0800")) - Name (_CRS, ResourceTemplate() - { - Memory32Fixed(ReadOnly, 0xff000000, 0x01000000) - }) - } - - Device (HPET) - { - Name (_HID, EISAID("PNP0103")) - Name (_CID, 0x010CD041) - - Method (_STA, 0) // Device Status - { - Return (0xf) // Enable and show device - } - - Name(_CRS, ResourceTemplate() - { - Memory32Fixed(ReadOnly, CONFIG_HPET_ADDRESS, 0x400) - }) - } - - Device(LDRC) // LPC device: Resource consumption - { - Name (_HID, EISAID("PNP0C02")) - Name (_UID, 2) - - Name (RBUF, ResourceTemplate() - { - IO (Decode16, 0x61, 0x61, 0x1, 0x01) // NMI Status - IO (Decode16, 0x63, 0x63, 0x1, 0x01) // CPU Reserved - IO (Decode16, 0x65, 0x65, 0x1, 0x01) // CPU Reserved - IO (Decode16, 0x67, 0x67, 0x1, 0x01) // CPU Reserved - IO (Decode16, 0x80, 0x80, 0x1, 0x01) // Port 80 Post - IO (Decode16, 0x92, 0x92, 0x1, 0x01) // CPU Reserved - IO (Decode16, 0xb2, 0xb2, 0x1, 0x02) // SWSMI - }) - - Method (_CRS, 0, NotSerialized) - { - Return (RBUF) - } - } - - Device (RTC) // Real Time Clock - { - Name (_HID, EISAID("PNP0B00")) - Name (_CRS, ResourceTemplate() - { - IO (Decode16, 0x70, 0x70, 1, 8) - }) - } - - Device (TIMR) // Intel 8254 timer - { - Name(_HID, EISAID("PNP0100")) - Name(_CRS, ResourceTemplate() - { - IO (Decode16, 0x40, 0x40, 0x01, 0x04) - IO (Decode16, 0x50, 0x50, 0x10, 0x04) - IRQNoFlags() {0} - }) - } -} diff --git a/src/soc/intel/fsp_broadwell_de/acpi/pcie1.asl b/src/soc/intel/fsp_broadwell_de/acpi/pcie1.asl deleted file mode 100644 index 950a3622db..0000000000 --- a/src/soc/intel/fsp_broadwell_de/acpi/pcie1.asl +++ /dev/null @@ -1,465 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2015-2016 Intel Corp. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -Name (PR01, Package() { - // [SL01]: PCI Express Slot 1 on 1A on PCI0 - Package() { 0x0000FFFF, 0, \_SB.PCI0.LPC0.LNKA, 0 }, - Package() { 0x0000FFFF, 1, \_SB.PCI0.LPC0.LNKB, 0 }, - Package() { 0x0000FFFF, 2, \_SB.PCI0.LPC0.LNKC, 0 }, - Package() { 0x0000FFFF, 3, \_SB.PCI0.LPC0.LNKD, 0 }, -}) - -Name (AR01, Package() { - // [SL01]: PCI Express Slot 1 on 1A on PCI0 - Package() { 0x0000FFFF, 0, 0, 16 }, - Package() { 0x0000FFFF, 1, 0, 17 }, - Package() { 0x0000FFFF, 2, 0, 18 }, - Package() { 0x0000FFFF, 3, 0, 19 }, -}) - -Name (AH01, Package() { - // [SL01]: PCI Express Slot 1 on 1A on PCI0 - Package() { 0x0000FFFF, 0, 0, 26 }, - Package() { 0x0000FFFF, 1, 0, 28 }, - Package() { 0x0000FFFF, 2, 0, 29 }, - Package() { 0x0000FFFF, 3, 0, 30 }, -}) - -Name (PR02, Package() { - // [SL02]: PCI Express Slot 2 on 1B on PCI0 - Package() { 0x0000FFFF, 0, \_SB.PCI0.LPC0.LNKA, 0 }, - Package() { 0x0000FFFF, 1, \_SB.PCI0.LPC0.LNKB, 0 }, - Package() { 0x0000FFFF, 2, \_SB.PCI0.LPC0.LNKC, 0 }, - Package() { 0x0000FFFF, 3, \_SB.PCI0.LPC0.LNKD, 0 }, -}) - -Name (AR02, Package() { - // [SL02]: PCI Express Slot 2 on 1B on PCI0 - Package() { 0x0000FFFF, 0, 0, 16 }, - Package() { 0x0000FFFF, 1, 0, 17 }, - Package() { 0x0000FFFF, 2, 0, 18 }, - Package() { 0x0000FFFF, 3, 0, 19 }, -}) - -Name (AH02, Package() { - // [SL02]: PCI Express Slot 2 on 1B on PCI0 - Package() { 0x0000FFFF, 0, 0, 27 }, - Package() { 0x0000FFFF, 1, 0, 30 }, - Package() { 0x0000FFFF, 2, 0, 28 }, - Package() { 0x0000FFFF, 3, 0, 29 }, -}) - -Name (PR03, Package() { - // [CB0I]: CB3DMA on IOSF - Package() { 0x0000FFFF, 0, \_SB.PCI0.LPC0.LNKA, 0 }, - // [CB0J]: CB3DMA on IOSF - Package() { 0x0000FFFF, 1, \_SB.PCI0.LPC0.LNKB, 0 }, - // [CB0K]: CB3DMA on IOSF - Package() { 0x0000FFFF, 2, \_SB.PCI0.LPC0.LNKC, 0 }, - // [CB0L]: CB3DMA on IOSF - Package() { 0x0000FFFF, 3, \_SB.PCI0.LPC0.LNKD, 0 }, -}) - -Name (AR03, Package() { - // [CB0I]: CB3DMA on IOSF - Package() { 0x0000FFFF, 0, 0, 16 }, - // [CB0J]: CB3DMA on IOSF - Package() { 0x0000FFFF, 1, 0, 17 }, - // [CB0K]: CB3DMA on IOSF - Package() { 0x0000FFFF, 2, 0, 18 }, - // [CB0L]: CB3DMA on IOSF - Package() { 0x0000FFFF, 3, 0, 19 }, -}) - -Name (AH03, Package() { - // [CB0I]: CB3DMA on IOSF - Package() { 0x0000FFFF, 0, 0, 32 }, - // [CB0J]: CB3DMA on IOSF - Package() { 0x0000FFFF, 1, 0, 36 }, - // [CB0K]: CB3DMA on IOSF - Package() { 0x0000FFFF, 2, 0, 37 }, - // [CB0L]: CB3DMA on IOSF - Package() { 0x0000FFFF, 3, 0, 38 }, -}) - -Name (PR04, Package() { - // [SL04]: PCI Express Slot 4 on 2B on PCI0 - Package() { 0x0000FFFF, 0, \_SB.PCI0.LPC0.LNKA, 0 }, - Package() { 0x0000FFFF, 1, \_SB.PCI0.LPC0.LNKB, 0 }, - Package() { 0x0000FFFF, 2, \_SB.PCI0.LPC0.LNKC, 0 }, - Package() { 0x0000FFFF, 3, \_SB.PCI0.LPC0.LNKD, 0 }, -}) - -Name (AR04, Package() { - // [SL04]: PCI Express Slot 4 on 2B on PCI0 - Package() { 0x0000FFFF, 0, 0, 16 }, - Package() { 0x0000FFFF, 1, 0, 17 }, - Package() { 0x0000FFFF, 2, 0, 18 }, - Package() { 0x0000FFFF, 3, 0, 19 }, -}) - -Name (AH04, Package() { - // [SL04]: PCI Express Slot 4 on 2B on PCI0 - Package() { 0x0000FFFF, 0, 0, 33 }, - Package() { 0x0000FFFF, 1, 0, 37 }, - Package() { 0x0000FFFF, 2, 0, 38 }, - Package() { 0x0000FFFF, 3, 0, 36 }, -}) - -Name (PR05, Package() { - // [SL05]: PCI Express Slot 5 on 2C on PCI0 - Package() { 0x0000FFFF, 0, \_SB.PCI0.LPC0.LNKA, 0 }, - Package() { 0x0000FFFF, 1, \_SB.PCI0.LPC0.LNKB, 0 }, - Package() { 0x0000FFFF, 2, \_SB.PCI0.LPC0.LNKC, 0 }, - Package() { 0x0000FFFF, 3, \_SB.PCI0.LPC0.LNKD, 0 }, -}) - -Name (AR05, Package() { - // [SL05]: PCI Express Slot 5 on 2C on PCI0 - Package() { 0x0000FFFF, 0, 0, 16 }, - Package() { 0x0000FFFF, 1, 0, 17 }, - Package() { 0x0000FFFF, 2, 0, 18 }, - Package() { 0x0000FFFF, 3, 0, 19 }, -}) - -Name (AH05, Package() { - // [SL05]: PCI Express Slot 5 on 2C on PCI0 - Package() { 0x0000FFFF, 0, 0, 34 }, - Package() { 0x0000FFFF, 1, 0, 37 }, - Package() { 0x0000FFFF, 2, 0, 36 }, - Package() { 0x0000FFFF, 3, 0, 38 }, -}) - -Name (PR06, Package() { - // [SL06]: PCI Express Slot 6 on 2D on PCI0 - Package() { 0x0000FFFF, 0, \_SB.PCI0.LPC0.LNKA, 0 }, - Package() { 0x0000FFFF, 1, \_SB.PCI0.LPC0.LNKB, 0 }, - Package() { 0x0000FFFF, 2, \_SB.PCI0.LPC0.LNKC, 0 }, - Package() { 0x0000FFFF, 3, \_SB.PCI0.LPC0.LNKD, 0 }, -}) - -Name (AR06, Package() { - // [SL06]: PCI Express Slot 6 on 2D on PCI0 - Package() { 0x0000FFFF, 0, 0, 16 }, - Package() { 0x0000FFFF, 1, 0, 17 }, - Package() { 0x0000FFFF, 2, 0, 18 }, - Package() { 0x0000FFFF, 3, 0, 19 }, -}) - -Name (AH06, Package() { - // [SL06]: PCI Express Slot 6 on 2D on PCI0 - Package() { 0x0000FFFF, 0, 0, 35 }, - Package() { 0x0000FFFF, 1, 0, 36 }, - Package() { 0x0000FFFF, 2, 0, 38 }, - Package() { 0x0000FFFF, 3, 0, 37 }, -}) - -Name (PR07, Package() { - // [SL07]: PCI Express Slot 7 on 3A on PCI0 - Package() { 0x0000FFFF, 0, \_SB.PCI0.LPC0.LNKA, 0 }, - Package() { 0x0000FFFF, 1, \_SB.PCI0.LPC0.LNKB, 0 }, - Package() { 0x0000FFFF, 2, \_SB.PCI0.LPC0.LNKC, 0 }, - Package() { 0x0000FFFF, 3, \_SB.PCI0.LPC0.LNKD, 0 }, -}) - -Name (AR07, Package() { - // [SL07]: PCI Express Slot 7 on 3A on PCI0 - Package() { 0x0000FFFF, 0, 0, 16 }, - Package() { 0x0000FFFF, 1, 0, 17 }, - Package() { 0x0000FFFF, 2, 0, 18 }, - Package() { 0x0000FFFF, 3, 0, 19 }, -}) - -Name (AH07, Package() { - // [SL07]: PCI Express Slot 7 on 3A on PCI0 - Package() { 0x0000FFFF, 0, 0, 40 }, - Package() { 0x0000FFFF, 1, 0, 44 }, - Package() { 0x0000FFFF, 2, 0, 45 }, - Package() { 0x0000FFFF, 3, 0, 46 }, -}) - -Name (PR08, Package() { - // [SL08]: PCI Express Slot 8 on 3B on PCI0 - Package() { 0x0000FFFF, 0, \_SB.PCI0.LPC0.LNKA, 0 }, - Package() { 0x0000FFFF, 1, \_SB.PCI0.LPC0.LNKB, 0 }, - Package() { 0x0000FFFF, 2, \_SB.PCI0.LPC0.LNKC, 0 }, - Package() { 0x0000FFFF, 3, \_SB.PCI0.LPC0.LNKD, 0 }, -}) - -Name (AR08, Package() { - // [SL08]: PCI Express Slot 8 on 3B on PCI0 - Package() { 0x0000FFFF, 0, 0, 16 }, - Package() { 0x0000FFFF, 1, 0, 17 }, - Package() { 0x0000FFFF, 2, 0, 18 }, - Package() { 0x0000FFFF, 3, 0, 19 }, -}) - -Name (AH08, Package() { - // [SL08]: PCI Express Slot 8 on 3B on PCI0 - Package() { 0x0000FFFF, 0, 0, 41 }, - Package() { 0x0000FFFF, 1, 0, 45 }, - Package() { 0x0000FFFF, 2, 0, 46 }, - Package() { 0x0000FFFF, 3, 0, 44 }, -}) - -Name (PR09, Package() { - // [SL09]: PCI Express Slot 9 on 3C on PCI0 - Package() { 0x0000FFFF, 0, \_SB.PCI0.LPC0.LNKA, 0 }, - Package() { 0x0000FFFF, 1, \_SB.PCI0.LPC0.LNKB, 0 }, - Package() { 0x0000FFFF, 2, \_SB.PCI0.LPC0.LNKC, 0 }, - Package() { 0x0000FFFF, 3, \_SB.PCI0.LPC0.LNKD, 0 }, -}) - -Name (AR09, Package() { - // [SL09]: PCI Express Slot 9 on 3C on PCI0 - Package() { 0x0000FFFF, 0, 0, 16 }, - Package() { 0x0000FFFF, 1, 0, 17 }, - Package() { 0x0000FFFF, 2, 0, 18 }, - Package() { 0x0000FFFF, 3, 0, 19 }, -}) - -Name (AH09, Package() { - // [SL09]: PCI Express Slot 9 on 3C on PCI0 - Package() { 0x0000FFFF, 0, 0, 42 }, - Package() { 0x0000FFFF, 1, 0, 45 }, - Package() { 0x0000FFFF, 2, 0, 44 }, - Package() { 0x0000FFFF, 3, 0, 46 }, -}) - -Name (PR0A, Package() { - // [SL0A]: PCI Express Slot 10 on 3D on PCI0 - Package() { 0x0000FFFF, 0, \_SB.PCI0.LPC0.LNKA, 0 }, - Package() { 0x0000FFFF, 1, \_SB.PCI0.LPC0.LNKB, 0 }, - Package() { 0x0000FFFF, 2, \_SB.PCI0.LPC0.LNKC, 0 }, - Package() { 0x0000FFFF, 3, \_SB.PCI0.LPC0.LNKD, 0 }, -}) - -Name (AR0A, Package() { - // [SL0A]: PCI Express Slot 10 on 3D on PCI0 - Package() { 0x0000FFFF, 0, 0, 16 }, - Package() { 0x0000FFFF, 1, 0, 17 }, - Package() { 0x0000FFFF, 2, 0, 18 }, - Package() { 0x0000FFFF, 3, 0, 19 }, -}) - -Name (AH0A, Package() { - // [SL0A]: PCI Express Slot 10 on 3D on PCI0 - Package() { 0x0000FFFF, 0, 0, 43 }, - Package() { 0x0000FFFF, 1, 0, 44 }, - Package() { 0x0000FFFF, 2, 0, 46 }, - Package() { 0x0000FFFF, 3, 0, 45 }, -}) - - - // PCI Express Port 1A on PCI0 -Device (BR1A) { - Name (_ADR, 0x00010000) - Method (_PRW, 0) { - Return (Package (0x02) {0x09, 0x04}) - } - Method (_PRT, 0) { - If (LEqual(PICM, Zero)) { - Return (PR01) - } - If (LEqual(APC1, One)) { - Return (AH01) - } - Return (AR01) - } - -} - -// PCI Express Port 1B on PCI0 -Device (BR1B) { - Name (_ADR, 0x00010001) - Method (_PRW, 0) { - Return (Package (0x02) {0x09, 0x04}) - } - Method (_PRT, 0) { - If (LEqual(PICM, Zero)) { - Return (PR02) - } - If (LEqual(APC1, One)) { - Return (AH02) - } - Return (AR02) - } - -} - -// PCI Express Port 2A on PCI0 -Device (BR2A) { - Name (_ADR, 0x00020000) - Method (_PRW, 0) { - Return (Package (0x02) {0x09, 0x04}) - } - Method (_PRT, 0) { - If (LEqual(PICM, Zero)) { - Return (PR03) - } - If (LEqual(APC1, One)) { - Return (AH03) - } - Return (AR03) - } - - - // CB3DMA on IOSF - Device (CB0I) { - Name (_ADR, 0x00000000) - } - - // CB3DMA on IOSF - Device (CB0J) { - Name (_ADR, 0x00000001) - } - - // CB3DMA on IOSF - Device (CB0K) { - Name (_ADR, 0x00000002) - } - - // CB3DMA on IOSF - Device (CB0L) { - Name (_ADR, 0x00000003) - } -} - -// PCI Express Port 2B on PCI0 -Device (BR2B) { - Name (_ADR, 0x00020001) - Method (_PRW, 0) { - Return (Package (0x02) {0x09, 0x04}) - } - Method (_PRT, 0) { - If (LEqual(PICM, Zero)) { - Return (PR04) - } - If (LEqual(APC1, One)) { - Return (AH04) - } - Return (AR04) - } - -} - -// PCI Express Port 2C on PCI0 -Device (BR2C) { - Name (_ADR, 0x00020002) - Method (_PRW, 0) { - Return (Package (0x02) {0x09, 0x04}) - } - Method (_PRT, 0) { - If (LEqual(PICM, Zero)) { - Return (PR05) - } - If (LEqual(APC1, One)) { - Return (AH05) - } - Return (AR05) - } - -} - -// PCI Express Port 2D on PCI0 -Device (BR2D) { - Name (_ADR, 0x00020003) - Method (_PRW, 0) { - Return (Package (0x02) {0x09, 0x04}) - } - Method (_PRT, 0) { - If (LEqual(PICM, Zero)) { - Return (PR06) - } - If (LEqual(APC1, One)) { - Return (AH06) - } - Return (AR06) - } - -} - -// PCI Express Port 3A on PCI0 -Device (BR3A) { - Name (_ADR, 0x00030000) - Method (_PRW, 0) { - Return (Package (0x02) {0x09, 0x04}) - } - Method (_PRT, 0) { - If (LEqual(PICM, Zero)) { - Return (PR07) - } - If (LEqual(APC1, One)) { - Return (AH07) - } - Return (AR07) - } - -} - -// PCI Express Port 3B on PCI0 -Device (BR3B) { - Name (_ADR, 0x00030001) - Method (_PRW, 0) { - Return (Package (0x02) {0x09, 0x04}) - } - Method (_PRT, 0) { - If (LEqual(PICM, Zero)) { - Return (PR08) - } - If (LEqual(APC1, One)) { - Return (AH08) - } - Return (AR08) - } - -} - -// PCI Express Port 3C on PCI0 -Device (BR3C) { - Name (_ADR, 0x00030002) - Method (_PRW, 0) { - Return (Package (0x02) {0x09, 0x04}) - } - Method (_PRT, 0) { - If (LEqual(PICM, Zero)) { - Return (PR09) - } - If (LEqual(APC1, One)) { - Return (AH09) - } - Return (AR09) - } - -} - -// PCI Express Port 3D on PCI0 -Device (BR3D) { - Name (_ADR, 0x00030003) - Method (_PRW, 0) { - Return (Package (0x02) {0x09, 0x04}) - } - Method (_PRT, 0) { - If (LEqual(PICM, Zero)) { - Return (PR0A) - } - If (LEqual(APC1, One)) { - Return (AH0A) - } - Return (AR0A) - } - -} diff --git a/src/soc/intel/fsp_broadwell_de/acpi/southcluster.asl b/src/soc/intel/fsp_broadwell_de/acpi/southcluster.asl deleted file mode 100644 index ff30f9f758..0000000000 --- a/src/soc/intel/fsp_broadwell_de/acpi/southcluster.asl +++ /dev/null @@ -1,349 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2013 Google Inc. - * Copyright (C) 2015-2016 Intel Corp. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include - -Name(_HID,EISAID("PNP0A08")) // PCIe -Name(_CID,EISAID("PNP0A03")) // PCI - -Name(_BBN, 0) - -Name (MCRS, ResourceTemplate() { - // Bus Numbers - WordBusNumber (ResourceProducer, MinFixed, MaxFixed, PosDecode, - 0x0000, 0x0000, 0x00fe, 0x0000, 0xff,,, PB00) - - // IO Region 0 - DWordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, - 0x0000, 0x0000, 0x0cf7, 0x0000, 0x0cf8,,, PI00) - - // PCI Config Space - Io (Decode16, 0x0cf8, 0x0cf8, 0x0001, 0x0008) - - // IO Region 1 - DWordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, - 0x0000, 0x0d00, 0xefff, 0x0000, 0xE300,,, PI01) - - // VGA memory (0xa0000-0xbffff) - DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, - Cacheable, ReadWrite, - 0x00000000, 0x000a0000, 0x000bffff, 0x00000000, - 0x00020000,,, ASEG) - - // OPROM reserved (0xc0000-0xc3fff) - DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, - Cacheable, ReadWrite, - 0x00000000, 0x000c0000, 0x000c3fff, 0x00000000, - 0x00004000,,, OPR0) - - // OPROM reserved (0xc4000-0xc7fff) - DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, - Cacheable, ReadWrite, - 0x00000000, 0x000c4000, 0x000c7fff, 0x00000000, - 0x00004000,,, OPR1) - - // OPROM reserved (0xc8000-0xcbfff) - DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, - Cacheable, ReadWrite, - 0x00000000, 0x000c8000, 0x000cbfff, 0x00000000, - 0x00004000,,, OPR2) - - // OPROM reserved (0xcc000-0xcffff) - DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, - Cacheable, ReadWrite, - 0x00000000, 0x000cc000, 0x000cffff, 0x00000000, - 0x00004000,,, OPR3) - - // OPROM reserved (0xd0000-0xd3fff) - DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, - Cacheable, ReadWrite, - 0x00000000, 0x000d0000, 0x000d3fff, 0x00000000, - 0x00004000,,, OPR4) - - // OPROM reserved (0xd4000-0xd7fff) - DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, - Cacheable, ReadWrite, - 0x00000000, 0x000d4000, 0x000d7fff, 0x00000000, - 0x00004000,,, OPR5) - - // OPROM reserved (0xd8000-0xdbfff) - DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, - Cacheable, ReadWrite, - 0x00000000, 0x000d8000, 0x000dbfff, 0x00000000, - 0x00004000,,, OPR6) - - // OPROM reserved (0xdc000-0xdffff) - DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, - Cacheable, ReadWrite, - 0x00000000, 0x000dc000, 0x000dffff, 0x00000000, - 0x00004000,,, OPR7) - - // BIOS Extension (0xe0000-0xe3fff) - DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, - Cacheable, ReadWrite, - 0x00000000, 0x000e0000, 0x000e3fff, 0x00000000, - 0x00004000,,, ESG0) - - // BIOS Extension (0xe4000-0xe7fff) - DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, - Cacheable, ReadWrite, - 0x00000000, 0x000e4000, 0x000e7fff, 0x00000000, - 0x00004000,,, ESG1) - - // BIOS Extension (0xe8000-0xebfff) - DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, - Cacheable, ReadWrite, - 0x00000000, 0x000e8000, 0x000ebfff, 0x00000000, - 0x00004000,,, ESG2) - - // BIOS Extension (0xec000-0xeffff) - DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, - Cacheable, ReadWrite, - 0x00000000, 0x000ec000, 0x000effff, 0x00000000, - 0x00004000,,, ESG3) - - // System BIOS (0xf0000-0xfffff) - DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, - Cacheable, ReadWrite, - 0x00000000, 0x000f0000, 0x000fffff, 0x00000000, - 0x00010000,,, FSEG) - - // PCI Memory Region (Top of memory-0xfeafffff) - DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, - Cacheable, ReadWrite, - 0x00000000, 0x90000000, 0xFEAFFFFF, 0x00000000, - 0x6EB00000,,, PMEM) - - DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, - Cacheable, ReadWrite, - 0x00000000, 0xfec00000, 0xfecfffff, 0x00000000, - 0x00100000,,, APIC) - - DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, - Cacheable, ReadWrite, - 0x00000000, 0xfed00000, 0xfedfffff, 0x00000000, - 0x00100000,,, PCHR) - - QWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, NonCacheable, ReadWrite, - 0x0000000000000000, // Granularity - 0x0000380000000000, // Range Minimum - 0x0000383FFFFFFFFF, // Range Maximum - 0x0000000000000000, // Translation Offset - 0x0000004000000000, // Length - ,,, AddressRangeMemory, TypeStatic) -}) - -Method (_CRS, 0, Serialized) { - Return (MCRS) -} - -/* Device Resource Consumption */ -Device (PDRC) { - Name (_HID, EISAID("PNP0C02")) - Name (_UID, 1) - - Name (PDRS, ResourceTemplate() { - Memory32Fixed(ReadWrite, ABORT_BASE_ADDRESS, ABORT_BASE_SIZE) - Memory32Fixed(ReadWrite, PSEG_BASE_ADDRESS, PSEG_BASE_SIZE) - Memory32Fixed(ReadWrite, IOXAPIC1_BASE_ADDRESS, IOXAPIC1_BASE_SIZE) - Memory32Fixed(ReadWrite, IOXAPIC2_BASE_ADDRESS, IOXAPIC2_BASE_SIZE) - Memory32Fixed(ReadWrite, PCH_BASE_ADDRESS, PCH_BASE_SIZE) - Memory32Fixed(ReadWrite, LXAPIC_BASE_ADDRESS, LXAPIC_BASE_SIZE) - Memory32Fixed(ReadWrite, FIRMWARE_BASE_ADDRESS, FIRMWARE_BASE_SIZE) - }) - - // Current Resource Settings - Method (_CRS, 0, Serialized) - { - Return(PDRS) - } -} - -Method (_OSC, 4) { - /* Check for proper GUID */ - If (LEqual (Arg0, ToUUID("33DB4D5B-1FF7-401C-9657-7441C03DD766"))) - { - /* Let OS control everything */ - Return (Arg3) - } - Else - { - /* Unrecognized UUID */ - CreateDWordField (Arg3, 0, CDW1) - Or (CDW1, 4, CDW1) - Return (Arg3) - } -} - -Name (PR00, Package() { - // [DMI0]: Legacy PCI Express Port 0 on PCI0 - Package() { 0x0000FFFF, 0, \_SB.PCI0.LPC0.LNKA, 0 }, - // [BR1A]: PCI Express Port 1A on PCI0 - // [BR1B]: PCI Express Port 1B on PCI0 - Package() { 0x0001FFFF, 0, \_SB.PCI0.LPC0.LNKA, 0 }, - // [BR2A]: PCI Express Port 2A on PCI0 - // [BR2B]: PCI Express Port 2B on PCI0 - // [BR2C]: PCI Express Port 2C on PCI0 - // [BR2D]: PCI Express Port 2D on PCI0 - Package() { 0x0002FFFF, 0, \_SB.PCI0.LPC0.LNKA, 0 }, - // [BR3A]: PCI Express Port 3A on PCI0 - // [BR3B]: PCI Express Port 3B on PCI0 - // [BR3C]: PCI Express Port 3C on PCI0 - // [BR3D]: PCI Express Port 3D on PCI0 - Package() { 0x0003FFFF, 0, \_SB.PCI0.LPC0.LNKA, 0 }, - // [CB0A]: CB3DMA on PCI0 - // [CB0E]: CB3DMA on PCI0 - Package() { 0x0004FFFF, 0, \_SB.PCI0.LPC0.LNKA, 0 }, - // [CB0B]: CB3DMA on PCI0 - // [CB0F]: CB3DMA on PCI0 - Package() { 0x0004FFFF, 1, \_SB.PCI0.LPC0.LNKB, 0 }, - // [CB0C]: CB3DMA on PCI0 - // [CB0G]: CB3DMA on PCI0 - Package() { 0x0004FFFF, 2, \_SB.PCI0.LPC0.LNKC, 0 }, - // [CB0D]: CB3DMA on PCI0 - // [CB0H]: CB3DMA on PCI0 - Package() { 0x0004FFFF, 3, \_SB.PCI0.LPC0.LNKD, 0 }, - // [IIM0]: IIOMISC on PCI0 - Package() { 0x0005FFFF, 0, \_SB.PCI0.LPC0.LNKA, 0 }, - Package() { 0x0005FFFF, 1, \_SB.PCI0.LPC0.LNKB, 0 }, - Package() { 0x0005FFFF, 2, \_SB.PCI0.LPC0.LNKC, 0 }, - Package() { 0x0005FFFF, 3, \_SB.PCI0.LPC0.LNKD, 0 }, - // [IID0]: IIODFX0 on PCI0 - Package() { 0x0006FFFF, 0, \_SB.PCI0.LPC0.LNKA, 0 }, - Package() { 0x0006FFFF, 1, \_SB.PCI0.LPC0.LNKB, 0 }, - Package() { 0x0006FFFF, 2, \_SB.PCI0.LPC0.LNKC, 0 }, - Package() { 0x0006FFFF, 3, \_SB.PCI0.LPC0.LNKD, 0 }, - // [XHCI]: xHCI controller 1 on PCH - Package() { 0x0014FFFF, 3, \_SB.PCI0.LPC0.LNKD, 0 }, - // [HECI]: ME HECI on PCH - // [IDER]: ME IDE redirect on PCH - Package() { 0x0016FFFF, 0, \_SB.PCI0.LPC0.LNKA, 0 }, - // [HEC2]: ME HECI2 on PCH - // [MEKT]: MEKT on PCH - Package() { 0x0016FFFF, 1, \_SB.PCI0.LPC0.LNKB, 0 }, - // [GBEM]: GbE Controller VPRO - Package() { 0x0019FFFF, 0, \_SB.PCI0.LPC0.LNKE, 0 }, - // [EHC2]: EHCI controller #2 on PCH - Package() { 0x001AFFFF, 2, \_SB.PCI0.LPC0.LNKC, 0 }, - // [ALZA]: High definition Audio Controller - Package() { 0x001BFFFF, 0, \_SB.PCI0.LPC0.LNKG, 0 }, - // [RP01]: Pci Express Port 1 on PCH - // [RP05]: Pci Express Port 5 on PCH - Package() { 0x001CFFFF, 0, \_SB.PCI0.LPC0.LNKA, 0 }, - // [RP02]: Pci Express Port 2 on PCH - // [RP06]: Pci Express Port 6 on PCH - Package() { 0x001CFFFF, 1, \_SB.PCI0.LPC0.LNKB, 0 }, - // [RP03]: Pci Express Port 3 on PCH - // [RP07]: Pci Express Port 7 on PCH - Package() { 0x001CFFFF, 2, \_SB.PCI0.LPC0.LNKC, 0 }, - // [RP04]: Pci Express Port 4 on PCH - // [RP08]: Pci Express Port 8 on ICH - Package() { 0x001CFFFF, 3, \_SB.PCI0.LPC0.LNKD, 0 }, - // [EHC1]: EHCI controller #1 on PCH - Package() { 0x001DFFFF, 2, \_SB.PCI0.LPC0.LNKC, 0 }, - // [SAT1]: SATA controller 1 on PCH - // [SAT2]: SATA Host controller 2 on PCH - Package() { 0x001FFFFF, 0, \_SB.PCI0.LPC0.LNKA, 0 }, - // [SMBS]: SMBus controller on PCH - // [TERM]: Thermal Subsystem on ICH - Package() { 0x001FFFFF, 2, \_SB.PCI0.LPC0.LNKC, 0 }, -}) - -Name (AR00, Package() { - // [DMI0]: Legacy PCI Express Port 0 on PCI0 - Package() { 0x0000FFFF, 0, 0, 47 }, - // [BR1A]: PCI Express Port 1A on PCI0 - // [BR1B]: PCI Express Port 1B on PCI0 - Package() { 0x0001FFFF, 0, 0, 47 }, - // [BR2A]: PCI Express Port 2A on PCI0 - // [BR2B]: PCI Express Port 2B on PCI0 - // [BR2C]: PCI Express Port 2C on PCI0 - // [BR2D]: PCI Express Port 2D on PCI0 - Package() { 0x0002FFFF, 0, 0, 47 }, - // [BR3A]: PCI Express Port 3A on PCI0 - // [BR3B]: PCI Express Port 3B on PCI0 - // [BR3C]: PCI Express Port 3C on PCI0 - // [BR3D]: PCI Express Port 3D on PCI0 - Package() { 0x0003FFFF, 0, 0, 47 }, - // [CB0A]: CB3DMA on PCI0 - // [CB0E]: CB3DMA on PCI0 - Package() { 0x0004FFFF, 0, 0, 31 }, - // [CB0B]: CB3DMA on PCI0 - // [CB0F]: CB3DMA on PCI0 - Package() { 0x0004FFFF, 1, 0, 39 }, - // [CB0C]: CB3DMA on PCI0 - // [CB0G]: CB3DMA on PCI0 - Package() { 0x0004FFFF, 2, 0, 31 }, - // [CB0D]: CB3DMA on PCI0 - // [CB0H]: CB3DMA on PCI0 - Package() { 0x0004FFFF, 3, 0, 39 }, - // [IIM0]: IIOMISC on PCI0 - Package() { 0x0005FFFF, 0, 0, 16 }, - Package() { 0x0005FFFF, 1, 0, 17 }, - Package() { 0x0005FFFF, 2, 0, 18 }, - Package() { 0x0005FFFF, 3, 0, 19 }, - // [IID0]: IIODFX0 on PCI0 - Package() { 0x0006FFFF, 0, 0, 16 }, - Package() { 0x0006FFFF, 1, 0, 17 }, - Package() { 0x0006FFFF, 2, 0, 18 }, - Package() { 0x0006FFFF, 3, 0, 19 }, - // [XHCI]: xHCI controller 1 on PCH - Package() { 0x0014FFFF, 3, 0, 19 }, - // [HECI]: ME HECI on PCH - // [IDER]: ME IDE redirect on PCH - Package() { 0x0016FFFF, 0, 0, 16 }, - // [HEC2]: ME HECI2 on PCH - // [MEKT]: MEKT on PCH - Package() { 0x0016FFFF, 1, 0, 17 }, - // [GBEM]: GbE Controller VPRO - Package() { 0x0019FFFF, 0, 0, 20 }, - // [EHC2]: EHCI controller #2 on PCH - Package() { 0x001AFFFF, 2, 0, 18 }, - // [ALZA]: High definition Audio Controller - Package() { 0x001BFFFF, 0, 0, 22 }, - // [RP01]: Pci Express Port 1 on PCH - // [RP05]: Pci Express Port 5 on PCH - Package() { 0x001CFFFF, 0, 0, 16 }, - // [RP02]: Pci Express Port 2 on PCH - // [RP06]: Pci Express Port 6 on PCH - Package() { 0x001CFFFF, 1, 0, 17 }, - // [RP03]: Pci Express Port 3 on PCH - // [RP07]: Pci Express Port 7 on PCH - Package() { 0x001CFFFF, 2, 0, 18 }, - // [RP04]: Pci Express Port 4 on PCH - // [RP08]: Pci Express Port 8 on ICH - Package() { 0x001CFFFF, 3, 0, 19 }, - // [EHC1]: EHCI controller #1 on PCH - Package() { 0x001DFFFF, 2, 0, 18 }, - // [SAT1]: SATA controller 1 on PCH - // [SAT2]: SATA Host controller 2 on PCH - Package() { 0x001FFFFF, 0, 0, 16 }, - // [SMBS]: SMBus controller on PCH - // [TERM]: Thermal Subsystem on ICH - Package() { 0x001FFFFF, 2, 0, 18 }, -}) - -// Socket 0 Root bridge -Method (_PRT, 0) { - If (LEqual(PICM, Zero)) { - Return (PR00) - } - Return (AR00) // If you disable the IOxAPIC in IIO, you should return AR00 -} - -#include "lpc.asl" diff --git a/src/soc/intel/fsp_broadwell_de/acpi/uncore.asl b/src/soc/intel/fsp_broadwell_de/acpi/uncore.asl deleted file mode 100644 index 86b1410c39..0000000000 --- a/src/soc/intel/fsp_broadwell_de/acpi/uncore.asl +++ /dev/null @@ -1,267 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2013 Google Inc. - * Copyright (C) 2015-2016 Intel Corp. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - - Name (PRUN, Package() { - Package() { 0x0008FFFF, 0, \_SB.PCI0.LPC0.LNKA, 0 }, - Package() { 0x0008FFFF, 1, \_SB.PCI0.LPC0.LNKB, 0 }, - Package() { 0x0008FFFF, 2, \_SB.PCI0.LPC0.LNKC, 0 }, - Package() { 0x0008FFFF, 3, \_SB.PCI0.LPC0.LNKD, 0 }, - - Package() { 0x0009FFFF, 0, \_SB.PCI0.LPC0.LNKA, 0 }, - Package() { 0x0009FFFF, 1, \_SB.PCI0.LPC0.LNKB, 0 }, - Package() { 0x0009FFFF, 2, \_SB.PCI0.LPC0.LNKC, 0 }, - Package() { 0x0009FFFF, 3, \_SB.PCI0.LPC0.LNKD, 0 }, - - Package() { 0x000AFFFF, 0, \_SB.PCI0.LPC0.LNKA, 0 }, - Package() { 0x000AFFFF, 1, \_SB.PCI0.LPC0.LNKB, 0 }, - Package() { 0x000AFFFF, 2, \_SB.PCI0.LPC0.LNKC, 0 }, - Package() { 0x000AFFFF, 3, \_SB.PCI0.LPC0.LNKD, 0 }, - - Package() { 0x000BFFFF, 0, \_SB.PCI0.LPC0.LNKA, 0 }, - Package() { 0x000BFFFF, 1, \_SB.PCI0.LPC0.LNKB, 0 }, - Package() { 0x000BFFFF, 2, \_SB.PCI0.LPC0.LNKC, 0 }, - Package() { 0x000BFFFF, 3, \_SB.PCI0.LPC0.LNKD, 0 }, - - Package() { 0x000CFFFF, 0, \_SB.PCI0.LPC0.LNKA, 0 }, - Package() { 0x000CFFFF, 1, \_SB.PCI0.LPC0.LNKB, 0 }, - Package() { 0x000CFFFF, 2, \_SB.PCI0.LPC0.LNKC, 0 }, - Package() { 0x000CFFFF, 3, \_SB.PCI0.LPC0.LNKD, 0 }, - - Package() { 0x000DFFFF, 0, \_SB.PCI0.LPC0.LNKA, 0 }, - Package() { 0x000DFFFF, 1, \_SB.PCI0.LPC0.LNKB, 0 }, - Package() { 0x000DFFFF, 2, \_SB.PCI0.LPC0.LNKC, 0 }, - Package() { 0x000DFFFF, 3, \_SB.PCI0.LPC0.LNKD, 0 }, - - Package() { 0x000EFFFF, 0, \_SB.PCI0.LPC0.LNKA, 0 }, - Package() { 0x000EFFFF, 1, \_SB.PCI0.LPC0.LNKB, 0 }, - Package() { 0x000EFFFF, 2, \_SB.PCI0.LPC0.LNKC, 0 }, - Package() { 0x000EFFFF, 3, \_SB.PCI0.LPC0.LNKD, 0 }, - - Package() { 0x000FFFFF, 0, \_SB.PCI0.LPC0.LNKA, 0 }, - Package() { 0x000FFFFF, 1, \_SB.PCI0.LPC0.LNKB, 0 }, - Package() { 0x000FFFFF, 2, \_SB.PCI0.LPC0.LNKC, 0 }, - Package() { 0x000FFFFF, 3, \_SB.PCI0.LPC0.LNKD, 0 }, - - Package() { 0x0010FFFF, 0, \_SB.PCI0.LPC0.LNKA, 0 }, - Package() { 0x0010FFFF, 1, \_SB.PCI0.LPC0.LNKB, 0 }, - Package() { 0x0010FFFF, 2, \_SB.PCI0.LPC0.LNKC, 0 }, - Package() { 0x0010FFFF, 3, \_SB.PCI0.LPC0.LNKD, 0 }, - - Package() { 0x0011FFFF, 0, \_SB.PCI0.LPC0.LNKA, 0 }, - Package() { 0x0011FFFF, 1, \_SB.PCI0.LPC0.LNKB, 0 }, - Package() { 0x0011FFFF, 2, \_SB.PCI0.LPC0.LNKC, 0 }, - Package() { 0x0011FFFF, 3, \_SB.PCI0.LPC0.LNKD, 0 }, - - Package() { 0x0012FFFF, 0, \_SB.PCI0.LPC0.LNKA, 0 }, - Package() { 0x0012FFFF, 1, \_SB.PCI0.LPC0.LNKB, 0 }, - Package() { 0x0012FFFF, 2, \_SB.PCI0.LPC0.LNKC, 0 }, - Package() { 0x0012FFFF, 3, \_SB.PCI0.LPC0.LNKD, 0 }, - - Package() { 0x0013FFFF, 0, \_SB.PCI0.LPC0.LNKA, 0 }, - Package() { 0x0013FFFF, 1, \_SB.PCI0.LPC0.LNKB, 0 }, - Package() { 0x0013FFFF, 2, \_SB.PCI0.LPC0.LNKC, 0 }, - Package() { 0x0013FFFF, 3, \_SB.PCI0.LPC0.LNKD, 0 }, - - Package() { 0x0014FFFF, 0, \_SB.PCI0.LPC0.LNKA, 0 }, - Package() { 0x0014FFFF, 1, \_SB.PCI0.LPC0.LNKB, 0 }, - Package() { 0x0014FFFF, 2, \_SB.PCI0.LPC0.LNKC, 0 }, - Package() { 0x0014FFFF, 3, \_SB.PCI0.LPC0.LNKD, 0 }, - - Package() { 0x0016FFFF, 0, \_SB.PCI0.LPC0.LNKA, 0 }, - Package() { 0x0016FFFF, 1, \_SB.PCI0.LPC0.LNKB, 0 }, - Package() { 0x0016FFFF, 2, \_SB.PCI0.LPC0.LNKC, 0 }, - Package() { 0x0016FFFF, 3, \_SB.PCI0.LPC0.LNKD, 0 }, - - Package() { 0x0017FFFF, 0, \_SB.PCI0.LPC0.LNKA, 0 }, - Package() { 0x0017FFFF, 1, \_SB.PCI0.LPC0.LNKB, 0 }, - Package() { 0x0017FFFF, 2, \_SB.PCI0.LPC0.LNKC, 0 }, - Package() { 0x0017FFFF, 3, \_SB.PCI0.LPC0.LNKD, 0 }, - - Package() { 0x0018FFFF, 0, \_SB.PCI0.LPC0.LNKA, 0 }, - Package() { 0x0018FFFF, 1, \_SB.PCI0.LPC0.LNKB, 0 }, - Package() { 0x0018FFFF, 2, \_SB.PCI0.LPC0.LNKC, 0 }, - Package() { 0x0018FFFF, 3, \_SB.PCI0.LPC0.LNKD, 0 }, - - Package() { 0x0019FFFF, 0, \_SB.PCI0.LPC0.LNKA, 0 }, - Package() { 0x0019FFFF, 1, \_SB.PCI0.LPC0.LNKB, 0 }, - Package() { 0x0019FFFF, 2, \_SB.PCI0.LPC0.LNKC, 0 }, - Package() { 0x0019FFFF, 3, \_SB.PCI0.LPC0.LNKD, 0 }, - - Package() { 0x001CFFFF, 0, \_SB.PCI0.LPC0.LNKA, 0 }, - Package() { 0x001CFFFF, 1, \_SB.PCI0.LPC0.LNKB, 0 }, - Package() { 0x001CFFFF, 2, \_SB.PCI0.LPC0.LNKC, 0 }, - Package() { 0x001CFFFF, 3, \_SB.PCI0.LPC0.LNKD, 0 }, - - Package() { 0x001DFFFF, 0, \_SB.PCI0.LPC0.LNKA, 0 }, - Package() { 0x001DFFFF, 1, \_SB.PCI0.LPC0.LNKB, 0 }, - Package() { 0x001DFFFF, 2, \_SB.PCI0.LPC0.LNKC, 0 }, - Package() { 0x001DFFFF, 3, \_SB.PCI0.LPC0.LNKD, 0 }, - - Package() { 0x001EFFFF, 0, \_SB.PCI0.LPC0.LNKA, 0 }, - Package() { 0x001EFFFF, 1, \_SB.PCI0.LPC0.LNKB, 0 }, - Package() { 0x001EFFFF, 2, \_SB.PCI0.LPC0.LNKC, 0 }, - Package() { 0x001EFFFF, 3, \_SB.PCI0.LPC0.LNKD, 0 }, - - Package() { 0x001FFFFF, 0, \_SB.PCI0.LPC0.LNKA, 0 }, - Package() { 0x001FFFFF, 1, \_SB.PCI0.LPC0.LNKB, 0 }, - Package() { 0x001FFFFF, 2, \_SB.PCI0.LPC0.LNKC, 0 }, - Package() { 0x001FFFFF, 3, \_SB.PCI0.LPC0.LNKD, 0 }, -}) - -Name (ARUN, Package() { - Package() { 0x0008FFFF, 0, 0, 16 }, - Package() { 0x0008FFFF, 1, 0, 17 }, - Package() { 0x0008FFFF, 2, 0, 18 }, - Package() { 0x0008FFFF, 3, 0, 19 }, - - Package() { 0x0009FFFF, 0, 0, 16 }, - Package() { 0x0009FFFF, 1, 0, 17 }, - Package() { 0x0009FFFF, 2, 0, 18 }, - Package() { 0x0009FFFF, 3, 0, 19 }, - - Package() { 0x000AFFFF, 0, 0, 16 }, - Package() { 0x000AFFFF, 1, 0, 17 }, - Package() { 0x000AFFFF, 2, 0, 18 }, - Package() { 0x000AFFFF, 3, 0, 19 }, - - Package() { 0x000BFFFF, 0, 0, 16 }, - Package() { 0x000BFFFF, 1, 0, 17 }, - Package() { 0x000BFFFF, 2, 0, 18 }, - Package() { 0x000BFFFF, 3, 0, 19 }, - - Package() { 0x000CFFFF, 0, 0, 16 }, - Package() { 0x000CFFFF, 1, 0, 17 }, - Package() { 0x000CFFFF, 2, 0, 18 }, - Package() { 0x000CFFFF, 3, 0, 19 }, - - Package() { 0x000DFFFF, 0, 0, 16 }, - Package() { 0x000DFFFF, 1, 0, 17 }, - Package() { 0x000DFFFF, 2, 0, 18 }, - Package() { 0x000DFFFF, 3, 0, 19 }, - - Package() { 0x000EFFFF, 0, 0, 16 }, - Package() { 0x000EFFFF, 1, 0, 17 }, - Package() { 0x000EFFFF, 2, 0, 18 }, - Package() { 0x000EFFFF, 3, 0, 19 }, - - Package() { 0x000FFFFF, 0, 0, 16 }, - Package() { 0x000FFFFF, 1, 0, 17 }, - Package() { 0x000FFFFF, 2, 0, 18 }, - Package() { 0x000FFFFF, 3, 0, 19 }, - - Package() { 0x0010FFFF, 0, 0, 16 }, - Package() { 0x0010FFFF, 1, 0, 17 }, - Package() { 0x0010FFFF, 2, 0, 18 }, - Package() { 0x0010FFFF, 3, 0, 19 }, - - Package() { 0x0011FFFF, 0, 0, 16 }, - Package() { 0x0011FFFF, 1, 0, 17 }, - Package() { 0x0011FFFF, 2, 0, 18 }, - Package() { 0x0011FFFF, 3, 0, 19 }, - - Package() { 0x0012FFFF, 0, 0, 16 }, - Package() { 0x0012FFFF, 1, 0, 17 }, - Package() { 0x0012FFFF, 2, 0, 18 }, - Package() { 0x0012FFFF, 3, 0, 19 }, - - Package() { 0x0013FFFF, 0, 0, 16 }, - Package() { 0x0013FFFF, 1, 0, 17 }, - Package() { 0x0013FFFF, 2, 0, 18 }, - Package() { 0x0013FFFF, 3, 0, 19 }, - - Package() { 0x0014FFFF, 0, 0, 16 }, - Package() { 0x0014FFFF, 1, 0, 17 }, - Package() { 0x0014FFFF, 2, 0, 18 }, - Package() { 0x0014FFFF, 3, 0, 19 }, - - Package() { 0x0016FFFF, 0, 0, 16 }, - Package() { 0x0016FFFF, 1, 0, 17 }, - Package() { 0x0016FFFF, 2, 0, 18 }, - Package() { 0x0016FFFF, 3, 0, 19 }, - - Package() { 0x0017FFFF, 0, 0, 16 }, - Package() { 0x0017FFFF, 1, 0, 17 }, - Package() { 0x0017FFFF, 2, 0, 18 }, - Package() { 0x0017FFFF, 3, 0, 19 }, - - Package() { 0x0018FFFF, 0, 0, 16 }, - Package() { 0x0018FFFF, 1, 0, 17 }, - Package() { 0x0018FFFF, 2, 0, 18 }, - Package() { 0x0018FFFF, 3, 0, 19 }, - - Package() { 0x0019FFFF, 0, 0, 16 }, - Package() { 0x0019FFFF, 1, 0, 17 }, - Package() { 0x0019FFFF, 2, 0, 18 }, - Package() { 0x0019FFFF, 3, 0, 19 }, - - Package() { 0x001CFFFF, 0, 0, 16 }, - Package() { 0x001CFFFF, 1, 0, 17 }, - Package() { 0x001CFFFF, 2, 0, 18 }, - Package() { 0x001CFFFF, 3, 0, 19 }, - - Package() { 0x001DFFFF, 0, 0, 16 }, - Package() { 0x001DFFFF, 1, 0, 17 }, - Package() { 0x001DFFFF, 2, 0, 18 }, - Package() { 0x001DFFFF, 3, 0, 19 }, - - Package() { 0x001EFFFF, 0, 0, 16 }, - Package() { 0x001EFFFF, 1, 0, 17 }, - Package() { 0x001EFFFF, 2, 0, 18 }, - Package() { 0x001EFFFF, 3, 0, 19 }, - - Package() { 0x001FFFFF, 0, 0, 16 }, - Package() { 0x001FFFFF, 1, 0, 17 }, - Package() { 0x001FFFFF, 2, 0, 18 }, - Package() { 0x001FFFFF, 3, 0, 19 }, -}) - -Device (UNC0) -{ - Name (_HID, EisaId ("PNP0A03")) - Name (_UID, 0x3F) - Method (_BBN, 0, NotSerialized) - { - Return (0xff) - } - - Name (_ADR, 0x00) - Method (_STA, 0, NotSerialized) - { - Return (0xf) - } - - Name (_CRS, ResourceTemplate () - { - WordBusNumber (ResourceProducer, MinFixed, MaxFixed, PosDecode, - 0x0000, // Granularity - 0x00FF, // Range Minimum - 0x00FF, // Range Maximum - 0x0000, // Translation Offset - 0x0001, // Length - ,, ) - }) - - Method (_PRT, 0, NotSerialized) - { - If (LEqual (PICM, Zero)) - { - Return (PRUN) - } - - Return (ARUN) - } -} diff --git a/src/soc/intel/fsp_broadwell_de/bootblock/bootblock.c b/src/soc/intel/fsp_broadwell_de/bootblock/bootblock.c deleted file mode 100644 index 73c3f28f0b..0000000000 --- a/src/soc/intel/fsp_broadwell_de/bootblock/bootblock.c +++ /dev/null @@ -1,23 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2013 Google, Inc. - * Copyright (C) 2015-2016 Intel Corp. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include - -static void bootblock_cpu_init(void) -{ - /* Load microcode before any caching. */ - intel_update_microcode_from_cbfs(); -} diff --git a/src/soc/intel/fsp_broadwell_de/chip.c b/src/soc/intel/fsp_broadwell_de/chip.c deleted file mode 100644 index a1978fa4e1..0000000000 --- a/src/soc/intel/fsp_broadwell_de/chip.c +++ /dev/null @@ -1,93 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2013 Google Inc. - * Copyright (C) 2015-2016 Intel Corp. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include -#include -#include -#include -#include - -#include "chip.h" - -static void pci_domain_set_resources(struct device *dev) -{ - assign_resources(dev->link_list); -} - -#if CONFIG(HAVE_ACPI_TABLES) -static const char *domain_acpi_name(const struct device *dev) -{ - if (dev->path.type == DEVICE_PATH_DOMAIN) - return "PCI0"; - return NULL; -} -#endif - -static struct device_operations pci_domain_ops = { - .read_resources = pci_domain_read_resources, - .set_resources = pci_domain_set_resources, - .enable_resources = NULL, - .init = NULL, - .scan_bus = pci_domain_scan_bus, -#if CONFIG(HAVE_ACPI_TABLES) - .acpi_name = domain_acpi_name -#endif -}; - -static struct device_operations cpu_bus_ops = { - .read_resources = DEVICE_NOOP, - .set_resources = DEVICE_NOOP, - .enable_resources = DEVICE_NOOP, - .init = broadwell_de_init_cpus, - .scan_bus = NULL, -}; - -static void enable_dev(struct device *dev) -{ - printk(BIOS_DEBUG, "enable_dev(%s, %d)\n", - dev_name(dev), dev->path.type); - - /* Set the operations if it is a special bus type */ - if (dev->path.type == DEVICE_PATH_DOMAIN) { - dev->ops = &pci_domain_ops; - } else if (dev->path.type == DEVICE_PATH_CPU_CLUSTER) { - dev->ops = &cpu_bus_ops; - } else if (dev->path.type == DEVICE_PATH_PCI) { - /* Handle south cluster enablement. */ - if (PCI_SLOT(dev->path.pci.devfn) > 0 && - (dev->ops == NULL || dev->ops->enable == NULL)) { - southcluster_enable_dev(dev); - } - } -} - -/* Called at BS_DEV_INIT_CHIPS time -- very early. Just after BS_PRE_DEVICE. */ -static void soc_init(void *chip_info) -{ - broadwell_de_init_pre_device(); -} - -struct chip_operations soc_intel_fsp_broadwell_de_ops = { - CHIP_NAME("Intel(R) Xeon(R) Processor D-1500 Product Family") - .enable_dev = enable_dev, - .init = soc_init, -}; - -struct pci_operations soc_pci_ops = { - .set_subsystem = &pci_dev_set_subsystem, -}; diff --git a/src/soc/intel/fsp_broadwell_de/chip.h b/src/soc/intel/fsp_broadwell_de/chip.h deleted file mode 100644 index bf2896238a..0000000000 --- a/src/soc/intel/fsp_broadwell_de/chip.h +++ /dev/null @@ -1,32 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2013 Google Inc. - * Copyright (C) 2015-2016 Intel Corp. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef _SOC_CHIP_H_ -#define _SOC_CHIP_H_ - -#include - -/* The devicetree parser expects chip.h to reside directly in the path - * specified by the devicetree. */ - -struct soc_intel_fsp_broadwell_de_config { - /* PCIe completion timeout value */ - int pcie_compltoval; -}; - -typedef struct soc_intel_fsp_broadwell_de_config config_t; - -#endif /* _SOC_CHIP_H_ */ diff --git a/src/soc/intel/fsp_broadwell_de/cpu.c b/src/soc/intel/fsp_broadwell_de/cpu.c deleted file mode 100644 index b94ee78d7a..0000000000 --- a/src/soc/intel/fsp_broadwell_de/cpu.c +++ /dev/null @@ -1,213 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2013 Google Inc. - * Copyright (C) 2015-2016 Intel Corp. - * Copyright (C) 2017 Siemens AG - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -/* MP initialization support. */ -static const void *microcode_patch; - -static void pre_mp_init(void) -{ - x86_mtrr_check(); - - /* Enable the local CPU apics */ - setup_lapic(); -} - -static int get_cpu_count(void) -{ - const struct pattrs *pattrs = pattrs_get(); - - return pattrs->num_cpus; -} - -static void per_cpu_smm_trigger(void) -{ - /* Relocate the SMM handler. */ - smm_relocate(); - - /* After SMM relocation a 2nd microcode load is required. */ - intel_microcode_load_unlocked(microcode_patch); -} - -static void get_microcode_info(const void **microcode, int *parallel) -{ - const struct pattrs *pattrs = pattrs_get(); - - microcode_patch = pattrs->microcode_patch; - *microcode = pattrs->microcode_patch; - *parallel = 1; -} - -static int cpu_config_tdp_levels(void) -{ - msr_t platform_info; - - /* Bits 34:33 indicate how many levels are supported. */ - platform_info = rdmsr(MSR_PLATFORM_INFO); - return (platform_info.hi >> 1) & 3; -} - -static void set_max_ratio(void) -{ - msr_t msr, perf_ctl; - - perf_ctl.hi = 0; - - /* Check for configurable TDP option. */ - if (cpu_config_tdp_levels()) { - /* Set to nominal TDP ratio. */ - msr = rdmsr(MSR_CONFIG_TDP_NOMINAL); - perf_ctl.lo = (msr.lo & 0xff) << 8; - } else { - /* Platform Info Bits 15:8 give max ratio. */ - msr = rdmsr(MSR_PLATFORM_INFO); - perf_ctl.lo = msr.lo & 0xff00; - } - wrmsr(IA32_PERF_CTL, perf_ctl); -} - -unsigned int smbios_cpu_get_max_speed_mhz(void) -{ - msr_t msr; - uint32_t uncore_max_ratio, turbo_max_ratio = 0; - - /* - * Use turbo's max ratio if it is enabled, otherwise use - * uncore's max ratio. - */ - msr = rdmsr(MSR_UNCORE_RATIO_LIMIT); - uncore_max_ratio = msr.lo & 0x7f; - if (get_turbo_state() == TURBO_ENABLED) { - msr = rdmsr(MSR_TURBO_RATIO_LIMIT); - turbo_max_ratio = msr.lo & 0xff; /* 1 core */ - } - - return MAX(uncore_max_ratio, turbo_max_ratio) * CPU_BCLK; -} - -static void alt_smm_lock(void) -{ - struct device *dev = pcidev_on_root(LPC_DEV, LPC_FUNC); - uint16_t smi_lock; - - /* There is no register to lock SMRAM region on Broadwell-DE. - Use this function to lock the SMI control bits. */ - printk(BIOS_DEBUG, "Locking SMM.\n"); - smi_lock = pci_read_config16(dev, GEN_PMCON_1); - smi_lock |= (SMI_LOCK | SMI_LOCK_GP6 | SMI_LOCK_GP22); - pci_write_config16(dev, GEN_PMCON_1, smi_lock); -} - -static void post_mp_init(void) -{ - /* Set Max Ratio */ - set_max_ratio(); - /* Now that all APs have been relocated as well as the BSP let SMIs - start flowing. */ - smm_southbridge_enable_smi(); - - /* Set SMI lock bits. */ - alt_smm_lock(); -} - -static const struct mp_ops mp_ops = { - .pre_mp_init = pre_mp_init, - .get_smm_info = smm_info, - .get_cpu_count = get_cpu_count, - .get_microcode_info = get_microcode_info, - .pre_mp_smm_init = smm_initialize, - .per_cpu_smm_trigger = per_cpu_smm_trigger, - .relocation_handler = smm_relocation_handler, - .post_mp_init = post_mp_init -}; - -void broadwell_de_init_cpus(struct device *dev) -{ - struct bus *cpu_bus = dev->link_list; - - if (mp_init_with_smm(cpu_bus, &mp_ops)) { - printk(BIOS_ERR, "MP initialization failure.\n"); - } -} - -static void configure_mca(void) -{ - msr_t msr; - int i; - int num_banks; - - msr = rdmsr(IA32_MCG_CAP); - num_banks = msr.lo & 0xff; - - /* TODO(adurbin): This should only be done on a cold boot. Also, some - of these banks are core vs package scope. For now every CPU clears - every bank. */ - msr.lo = msr.hi = 0; - for (i = 0; i < num_banks; i++) { - wrmsr(IA32_MC0_STATUS + (i * 4), msr); - wrmsr(IA32_MC0_STATUS + (i * 4) + 1, msr); - wrmsr(IA32_MC0_STATUS + (i * 4) + 2, msr); - } - - msr.lo = msr.hi = 0xffffffff; - for (i = 0; i < num_banks; i++) - wrmsr(IA32_MC0_CTL + (i * 4), msr); -} - -static void broadwell_de_core_init(struct device *cpu) -{ - printk(BIOS_DEBUG, "Init Broadwell-DE core.\n"); - configure_mca(); -} - -static struct device_operations cpu_dev_ops = { - .init = broadwell_de_core_init, -}; - -static const struct cpu_device_id cpu_table[] = { - { X86_VENDOR_INTEL, 0x50661 }, - { X86_VENDOR_INTEL, 0x50662 }, - { X86_VENDOR_INTEL, 0x50663 }, - { X86_VENDOR_INTEL, 0x50664 }, - { 0, 0 }, -}; - -static const struct cpu_driver driver __cpu_driver = { - .ops = &cpu_dev_ops, - .id_table = cpu_table, -}; diff --git a/src/soc/intel/fsp_broadwell_de/fsp/Kconfig b/src/soc/intel/fsp_broadwell_de/fsp/Kconfig deleted file mode 100644 index f958e7194f..0000000000 --- a/src/soc/intel/fsp_broadwell_de/fsp/Kconfig +++ /dev/null @@ -1,140 +0,0 @@ -config BROADWELL_DE_FSP_SPECIFIC_OPTIONS - def_bool y - select PLATFORM_USES_FSP1_0 - select USE_GENERIC_FSP_CAR_INC - select FSP_USES_UPD - -config FSP_FILE - string - default "3rdparty/fsp/BroadwellDEFspBinPkg/FspBin/BROADWELLDE_FSP.bin" - help - The path and filename of the Intel FSP binary for this platform. - -config FSP_HEADER_PATH - string - default "$(top)/3rdparty/fsp/BroadwellDEFspBinPkg/include/" - -config FSP_SRC_PATH - string - default "$(top)/3rdparty/fsp/BroadwellDEFspBinPkg/include/fspsupport.c" - -config FSP_LOC - hex - default 0xffeb0000 - help - The location in CBFS that the FSP is located. This must match the - value that is set in the FSP binary. If the FSP needs to be moved, - rebase the FSP with Intel's BCT (tool). - - The Broadwell-DE FSP is built with a preferred base address of - 0xffeb0000. - -config DCACHE_RAM_BASE - hex - default 0xfe100000 - help - This address needs to match the setup performed inside FSP. - On Broadwell-DE the FSP allocates temporary RAM starting at 0xfe100000. - -config DCACHE_RAM_SIZE - hex - default 0x8000 - help - The DCACHE is shared between FSP itself and the rest of the coreboot - stages. A size of 0x8000 works fine while providing enough space for - features like VBOOT in verstage. Further increase to a power of two - aligned value leads to errors in FSP. - -config FSP_MEMORY_DOWN - bool "Enable Memory Down" - default n - help - Load SPD data from ROM instead of trying to read from SMBus. - - If the platform has DIMM sockets, say N. If memory is down, say Y and - supply the appropriate SPD data for each Channel/DIMM. - -config FSP_MEMORY_DOWN_CH0DIMM0_SPD_PRESENT - bool "Channel 0, DIMM 0 Present" - default n - depends on FSP_MEMORY_DOWN - help - Select Y if Channel 0, DIMM 0 is present. - -config FSP_MEMORY_DOWN_CH0DIMM0_SPD_FILE - string "Channel 0, DIMM 0 SPD File" - default "spd_ch0_dimm0.bin" - depends on FSP_MEMORY_DOWN_CH0DIMM0_SPD_PRESENT - help - Path to the file which contains the SPD data for Channel 0, DIMM 0. - -config FSP_MEMORY_DOWN_CH0DIMM1_SPD_PRESENT - bool "Channel 0, DIMM 1 Present" - default n - depends on FSP_MEMORY_DOWN - help - Select Y if Channel 0, DIMM 1 is present. - -config FSP_MEMORY_DOWN_CH0DIMM1_SPD_FILE - string "Channel 0, DIMM 1 SPD File" - default "spd_ch0_dimm1.bin" - depends on FSP_MEMORY_DOWN_CH0DIMM1_SPD_PRESENT - help - Path to the file which contains the SPD data for Channel 0, DIMM 1. - -config FSP_MEMORY_DOWN_CH1DIMM0_SPD_PRESENT - bool "Channel 1, DIMM 0 Present" - default n - depends on FSP_MEMORY_DOWN - help - Select Y if Channel 1, DIMM 0 is present. - -config FSP_MEMORY_DOWN_CH1DIMM0_SPD_FILE - string "Channel 1, DIMM 0 SPD File" - default "spd_ch1_dimm0.bin" - depends on FSP_MEMORY_DOWN_CH1DIMM0_SPD_PRESENT - help - Path to the file which contains the SPD data for Channel 1, DIMM 0. - -config FSP_MEMORY_DOWN_CH1DIMM1_SPD_PRESENT - bool "Channel 1, DIMM 1 Present" - default n - depends on FSP_MEMORY_DOWN - help - Select Y if Channel 1, DIMM 1 is present. - -config FSP_MEMORY_DOWN_CH1DIMM1_SPD_FILE - string "Channel 1, DIMM 1 SPD File" - default "spd_ch1_dimm1.bin" - depends on FSP_MEMORY_DOWN_CH1DIMM1_SPD_PRESENT - help - Path to the file which contains the SPD data for Channel 1, DIMM 1. - -config FSP_HYPERTHREADING - bool "Enable Hyper-Threading" - default y - help - Enable Intel(r) Hyper-Threading Technology for the Broadwell-DE SoC. - -config FSP_EHCI1_ENABLE - bool "EHCI1 Enable" - default n - help - Enable EHCI controller 1 - -config FSP_EHCI2_ENABLE - bool "EHCI2 Enable" - default n - help - Enable EHCI controller 2 - -config FSP_DEBUG_LEVEL - int "FSP debug level (0-3)" - default 0 - range 0 3 - help - Select the debug level, where: - 0: DISABLED - 1: MINIMUM - 2: NORMAL - 3: MAXIMUM diff --git a/src/soc/intel/fsp_broadwell_de/fsp/Makefile.inc b/src/soc/intel/fsp_broadwell_de/fsp/Makefile.inc deleted file mode 100644 index 651976483e..0000000000 --- a/src/soc/intel/fsp_broadwell_de/fsp/Makefile.inc +++ /dev/null @@ -1,17 +0,0 @@ -romstage-y += chipset_fsp_util.c - -cbfs-files-$(CONFIG_FSP_MEMORY_DOWN_CH0DIMM0_SPD_PRESENT) += spd_ch0_dimm0.bin -spd_ch0_dimm0.bin-file := $(call strip_quotes,$(CONFIG_FSP_MEMORY_DOWN_CH0DIMM0_SPD_FILE)) -spd_ch0_dimm0.bin-type := spd - -cbfs-files-$(CONFIG_FSP_MEMORY_DOWN_CH0DIMM1_SPD_PRESENT) += spd_ch0_dimm1.bin -spd_ch0_dimm1.bin-file := $(call strip_quotes,$(CONFIG_FSP_MEMORY_DOWN_CH0DIMM1_SPD_FILE)) -spd_ch0_dimm1.bin-type := spd - -cbfs-files-$(CONFIG_FSP_MEMORY_DOWN_CH1DIMM0_SPD_PRESENT) += spd_ch1_dimm0.bin -spd_ch1_dimm0.bin-file := $(call strip_quotes,$(CONFIG_FSP_MEMORY_DOWN_CH1DIMM0_SPD_FILE)) -spd_ch1_dimm0.bin-type := spd - -cbfs-files-$(CONFIG_FSP_MEMORY_DOWN_CH1DIMM1_SPD_PRESENT) += spd_ch1_dimm1.bin -spd_ch1_dimm1.bin-file := $(call strip_quotes,$(CONFIG_FSP_MEMORY_DOWN_CH1DIMM1_SPD_FILE)) -spd_ch1_dimm1.bin-type := spd diff --git a/src/soc/intel/fsp_broadwell_de/fsp/chipset_fsp_util.c b/src/soc/intel/fsp_broadwell_de/fsp/chipset_fsp_util.c deleted file mode 100644 index edb313e7d5..0000000000 --- a/src/soc/intel/fsp_broadwell_de/fsp/chipset_fsp_util.c +++ /dev/null @@ -1,142 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2013-2014 Sage Electronic Engineering, LLC. - * Copyright (C) 2015-2016 Intel Corporation. All Rights Reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include "../chip.h" - -/* Copy the default UPD region and settings to a buffer for modification */ -static void GetUpdDefaultFromFsp (FSP_INFO_HEADER *FspInfo, UPD_DATA_REGION *UpdData) -{ - VPD_DATA_REGION *VpdDataRgnPtr; - UPD_DATA_REGION *UpdDataRgnPtr; - VpdDataRgnPtr = (VPD_DATA_REGION *)(UINT32)(FspInfo->CfgRegionOffset + FspInfo->ImageBase); - UpdDataRgnPtr = (UPD_DATA_REGION *)(UINT32)(VpdDataRgnPtr->PcdUpdRegionOffset + FspInfo->ImageBase); - memcpy((void *)UpdData, (void *)UpdDataRgnPtr, sizeof(UPD_DATA_REGION)); -} - -typedef struct soc_intel_fsp_broadwell_de_config config_t; - -/** - * Update the UPD data based on values from devicetree.cb - * - * @param UpdData Pointer to the UPD Data structure - */ -static void ConfigureDefaultUpdData(UPD_DATA_REGION *UpdData) -{ - /* - * Serial Port - */ - if (CONFIG(INTEGRATED_UART)) { - UpdData->SerialPortConfigure = 1; - /* values are from FSP .bsf file */ - if (CONFIG(CONSOLE_SERIAL_9600)) - UpdData->SerialPortBaudRate = 8; - else if (CONFIG(CONSOLE_SERIAL_19200)) - UpdData->SerialPortBaudRate = 9; - else if (CONFIG(CONSOLE_SERIAL_38400)) - UpdData->SerialPortBaudRate = 10; - else if (CONFIG(CONSOLE_SERIAL_57600)) - UpdData->SerialPortBaudRate = 11; - else if (CONFIG(CONSOLE_SERIAL_115200)) - UpdData->SerialPortBaudRate = 12; - } - - if (!CONFIG(CONSOLE_SERIAL)) - UpdData->SerialPortType = 0; - - UpdData->DebugOutputLevel = CONFIG_FSP_DEBUG_LEVEL; - - /* - * Memory Down - */ - if (CONFIG(FSP_MEMORY_DOWN)) { - UpdData->MemDownEnable = 1; - - if (CONFIG(FSP_MEMORY_DOWN_CH0DIMM0_SPD_PRESENT)) - UpdData->MemDownCh0Dimm0SpdPtr - = (UINT32)cbfs_boot_map_with_leak("spd_ch0_dimm0.bin", CBFS_TYPE_SPD, NULL); - if (CONFIG(FSP_MEMORY_DOWN_CH0DIMM1_SPD_PRESENT)) - UpdData->MemDownCh0Dimm1SpdPtr - = (UINT32)cbfs_boot_map_with_leak("spd_ch0_dimm1.bin", CBFS_TYPE_SPD, NULL); - if (CONFIG(FSP_MEMORY_DOWN_CH1DIMM0_SPD_PRESENT)) - UpdData->MemDownCh1Dimm0SpdPtr - = (UINT32)cbfs_boot_map_with_leak("spd_ch1_dimm0.bin", CBFS_TYPE_SPD, NULL); - if (CONFIG(FSP_MEMORY_DOWN_CH1DIMM1_SPD_PRESENT)) - UpdData->MemDownCh1Dimm1SpdPtr - = (UINT32)cbfs_boot_map_with_leak("spd_ch1_dimm1.bin", CBFS_TYPE_SPD, NULL); - } else { - UpdData->MemDownEnable = 0; - } - printk(FSP_INFO_LEVEL, "Memory Down Support: %s\n", - UpdData->MemDownEnable ? "Enabled" : "Disabled"); - - /* - * Fast Boot - */ - if (CONFIG(ENABLE_MRC_CACHE)) - UpdData->MemFastBoot = 1; - else - UpdData->MemFastBoot = 0; - - /* - * Hyper-Threading - */ - if (CONFIG(FSP_HYPERTHREADING)) - UpdData->HyperThreading = 1; - else - UpdData->HyperThreading = 0; - - /* Enable USB */ - if (CONFIG(FSP_EHCI1_ENABLE)) - UpdData->Ehci1Enable = 1; - else - UpdData->Ehci1Enable = 0; - - if (CONFIG(FSP_EHCI2_ENABLE)) - UpdData->Ehci2Enable = 1; - else - UpdData->Ehci2Enable = 0; -} - -/* Set up the Broadwell-DE specific structures for the call into the FSP */ -void chipset_fsp_early_init(FSP_INIT_PARAMS *pFspInitParams, FSP_INFO_HEADER *fsp_ptr) -{ - FSP_INIT_RT_BUFFER *pFspRtBuffer = pFspInitParams->RtBufferPtr; - - /* Initialize the UPD Data */ - GetUpdDefaultFromFsp (fsp_ptr, pFspRtBuffer->Common.UpdDataRgnPtr); - ConfigureDefaultUpdData(pFspRtBuffer->Common.UpdDataRgnPtr); - pFspInitParams->NvsBufferPtr = NULL; - -#if CONFIG(ENABLE_MRC_CACHE) - /* Find the fastboot cache that was saved in the ROM */ - pFspInitParams->NvsBufferPtr = find_and_set_fastboot_cache(); -#endif - - return; -} diff --git a/src/soc/intel/fsp_broadwell_de/fsp/chipset_fsp_util.h b/src/soc/intel/fsp_broadwell_de/fsp/chipset_fsp_util.h deleted file mode 100644 index 057d7fda0d..0000000000 --- a/src/soc/intel/fsp_broadwell_de/fsp/chipset_fsp_util.h +++ /dev/null @@ -1,35 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2013-2014 Sage Electronic Engineering, LLC. - * Copyright (C) 2015-2016 Intel Corporation - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef CHIPSET_FSP_UTIL_H -#define CHIPSET_FSP_UTIL_H - -#include - -#define FSP_INFO_HEADER_GUID \ - { \ - 0x912740BE, 0x2284, 0x4734, {0xB9, 0x71, 0x84, 0xB0, 0x27, 0x35, 0x3F, 0x0C} \ - } - -/* - * The FSP Image ID is different for each platform's FSP and - * can be used to verify that the right FSP binary is loaded. - * For the Broadwell-DE FSP, the Image Id is "BDX-DE". - */ -#define FSP_IMAGE_ID_DWORD0 ((unsigned int)(FSP_IMAGE_ID)) -#define FSP_IMAGE_ID_DWORD1 ((unsigned int)(FSP_IMAGE_ID >> 32)) - -#endif /* CHIPSET_FSP_UTIL_H */ diff --git a/src/soc/intel/fsp_broadwell_de/gpio.c b/src/soc/intel/fsp_broadwell_de/gpio.c deleted file mode 100644 index 41100e928c..0000000000 --- a/src/soc/intel/fsp_broadwell_de/gpio.c +++ /dev/null @@ -1,109 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2017 Siemens AG - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include - -/* Use a wrapper for register addresses for different banks. */ -const static struct gpio_config_regs regs[GPIO_NUM_BANKS] = { - [0] = { .use_sel = GPIO_1_USE_SEL, .io_sel = GPIO_1_IO_SEL, - .level = GPIO_1_LVL, .nmi_en = GPIO_1_NMI_EN, - .blink_en = GPIO_1_BLINK, .invert_input = GPIO_1_INVERT }, - [1] = { .use_sel = GPIO_2_USE_SEL, .io_sel = GPIO_2_IO_SEL, - .level = GPIO_2_LVL, .nmi_en = GPIO_2_NMI_EN, - .blink_en = REG_INVALID, .invert_input = REG_INVALID }, - [2] = { .use_sel = GPIO_3_USE_SEL, .io_sel = GPIO_3_IO_SEL, - .level = GPIO_3_LVL, .nmi_en = GPIO_3_NMI_EN, - .blink_en = REG_INVALID, .invert_input = REG_INVALID }, - }; - -#define SETUP_GPIO_REG(reg, bit, bank) { uint32_t val; \ - val = inl(GPIO_BASE_ADDRESS + regs[(bank)].reg); \ - val &= ~(1 << (bit)); \ - val |= ((pin->reg) << (bit)); \ - outl(val, GPIO_BASE_ADDRESS + regs[(bank)].reg); } - -/* Initialize the GPIOs as defined on mainboard level. */ -void init_gpios(const struct gpio_config config[]) -{ - uint8_t bank, bit; - const struct gpio_config *pin; - - if (!config) - return; - /* Set up every GPIO in the table to the requested function. */ - for (pin = config; pin->use_sel != GPIO_LIST_END; pin++) { - /* Skip unsupported GPIO numbers. */ - if (pin->num > MAX_GPIO_NUM || pin->num == 13) - continue; - bank = pin->num / 32; - bit = pin->num % 32; - if (pin->use_sel == GPIO_MODE_GPIO) { - /* Setting level register first avoids possible short - * pulses on the pin if the output level differs from - * the register default value. - */ - if (pin->io_sel == GPIO_OUTPUT) - SETUP_GPIO_REG(level, bit, bank); - /* Now set the GPIO direction and NMI selection. */ - SETUP_GPIO_REG(io_sel, bit, bank); - SETUP_GPIO_REG(nmi_en, bit, bank); - } - /* Now set the pin mode as requested */ - SETUP_GPIO_REG(use_sel, bit, bank); - /* The extended functions like inverting and blinking are only - * supported by GPIOs on bank 0. - */ - if (bank) - continue; - /* Blinking is available only for outputs */ - if (pin->io_sel == GPIO_OUTPUT) - SETUP_GPIO_REG(blink_en, bit, bank); - /* Inverting is available only for inputs */ - if (pin->io_sel == GPIO_INPUT) - SETUP_GPIO_REG(invert_input, bit, bank); - } -} - -/* Get GPIO pin value */ -int gpio_get(gpio_t gpio) -{ - uint8_t bank, bit; - - bank = gpio / 32; - bit = gpio % 32; - return (inl(GPIO_BASE_ADDRESS + regs[bank].level) & (1 << bit)) ? 1 : 0; -} - -/* Set GPIO pin value */ -void gpio_set(gpio_t gpio, int value) -{ - uint32_t reg; - uint8_t bank, bit; - - bank = gpio / 32; - bit = gpio % 32; - reg = inl(GPIO_BASE_ADDRESS + regs[bank].level); - reg &= ~(1 << bit); - reg |= (!!value << bit); - outl(reg, GPIO_BASE_ADDRESS + regs[bank].level); -} diff --git a/src/soc/intel/fsp_broadwell_de/include/soc/acpi.h b/src/soc/intel/fsp_broadwell_de/include/soc/acpi.h deleted file mode 100644 index 419f229938..0000000000 --- a/src/soc/intel/fsp_broadwell_de/include/soc/acpi.h +++ /dev/null @@ -1,32 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2013 Google, Inc. - * Copyright (C) 2015-2016 Intel Corp. - * Copyright (C) 2016-2018 Siemens AG - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef _SOC_ACPI_H_ -#define _SOC_ACPI_H_ - -#include - -void acpi_fill_in_fadt(acpi_fadt_t *fadt, acpi_facs_t *facs, void *dsdt); -unsigned long acpi_madt_irq_overrides(unsigned long current); -uint16_t get_pmbase(void); -unsigned long vtd_write_acpi_tables(struct device *const dev, - unsigned long current, - struct acpi_rsdp *const rsdp); -unsigned long southcluster_write_acpi_tables(struct device *device, - unsigned long start, - acpi_rsdp_t *rsdp); -#endif /* _SOC_ACPI_H_ */ diff --git a/src/soc/intel/fsp_broadwell_de/include/soc/broadwell_de.h b/src/soc/intel/fsp_broadwell_de/include/soc/broadwell_de.h deleted file mode 100644 index a44b857c1f..0000000000 --- a/src/soc/intel/fsp_broadwell_de/include/soc/broadwell_de.h +++ /dev/null @@ -1,46 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2013 Google, Inc. - * Copyright (C) 2015-2016 Intel Corp. - * Copyright (C) 2017-2018 Siemens AG - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef _SOC_BROADWELL_DE_H_ -#define _SOC_BROADWELL_DE_H_ - -uintptr_t sa_get_tseg_base(void); -size_t sa_get_tseg_size(void); - -#define VTBAR_OFFSET 0x180 -#define VTBAR_MASK 0xffffe000 -#define VTBAR_ENABLED 0x01 -#define VTBAR_SIZE 0x2000 - -#define SMM_FEATURE_CONTROL 0x58 -#define SMM_CPU_SAVE_EN (1 << 1) -#define TSEG_BASE 0xa8 /* TSEG base */ -#define TSEG_LIMIT 0xac /* TSEG limit */ - -#define IIO_LTDPR 0x290 -#define DPR_LOCK (1 << 0) -#define DPR_EPM (1 << 2) -#define DPR_PRS (1 << 1) -#define DPR_SIZE_MASK 0xff0 -#define DPR_SIZE_SHIFT 4 -#define DPR_ADDR_MASK 0xfff00000 -#define DPR_ADDR_SHIFT 20 - -/* CPU bus clock is fixed at 100MHz */ -#define CPU_BCLK 100 - -#endif /* _SOC_BROADWELL_DE_H_ */ diff --git a/src/soc/intel/fsp_broadwell_de/include/soc/gpio.h b/src/soc/intel/fsp_broadwell_de/include/soc/gpio.h deleted file mode 100644 index 1159d03910..0000000000 --- a/src/soc/intel/fsp_broadwell_de/include/soc/gpio.h +++ /dev/null @@ -1,129 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2017 Siemens AG - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ -#ifndef FSP_BROADWELL_DE_GPIO_H_ -#define FSP_BROADWELL_DE_GPIO_H_ - -#include - -/* Chipset owned GPIO configuration registers */ -#define GPIO_1_USE_SEL 0x00 -#define GPIO_1_IO_SEL 0x04 -#define GPIO_1_LVL 0x0c -#define GPIO_1_BLINK 0x18 -#define GPIO_1_NMI_EN 0x28 -#define GPIO_1_INVERT 0x2c -#define GPIO_2_USE_SEL 0x30 -#define GPIO_2_IO_SEL 0x34 -#define GPIO_2_LVL 0x38 -#define GPIO_2_NMI_EN 0x3c -#define GPIO_3_USE_SEL 0x40 -#define GPIO_3_IO_SEL 0x44 -#define GPIO_3_LVL 0x48 -#define GPIO_3_NMI_EN 0x50 -#define REG_INVALID 0xff - -/* The pin can either be a GPIO or connected to the native function. */ -#define GPIO_MODE_NATIVE 0 -#define GPIO_MODE_GPIO 1 -/* Once configured as GPIO the pin can be an input or an output. */ -#define GPIO_OUTPUT 0 -#define GPIO_INPUT 1 -#define GPIO_NMI_EN 1 -/* For output GPIO mode the pin can either drive high or low level. */ -#define GPIO_OUT_LEVEL_LOW 0 -#define GPIO_OUT_LEVEL_HIGH 1 -/* The following functions are only valid for GPIO bank 1. */ -#define GPIO_OUT_BLINK 1 -#define GPIO_IN_INVERT 1 - -#define GPIO_NUM_BANKS 3 -#define MAX_GPIO_NUM 75 /* 0 based GPIO number */ -#define GPIO_LIST_END 0xff - -/* Define possible GPIO configurations. */ -#define PCH_GPIO_END \ - { .use_sel = GPIO_LIST_END } - -#define PCH_GPIO_NATIVE(gpio) { \ - .num = (gpio), \ - .use_sel = GPIO_MODE_NATIVE } - -#define PCH_GPIO_INPUT(gpio) { \ - .num = (gpio), \ - .use_sel = GPIO_MODE_GPIO, \ - .io_sel = GPIO_INPUT } - -#define PCH_GPIO_INPUT_INVERT(gpio) { \ - .num = (gpio), \ - .use_sel = GPIO_MODE_GPIO, \ - .io_sel = GPIO_INPUT, \ - .invert_input = GPIO_IN_INVERT } - -#define PCH_GPIO_INPUT_NMI(gpio) { \ - .num = (gpio), \ - .use_sel = GPIO_MODE_GPIO, \ - .io_sel = GPIO_INPUT, \ - .nmi_en = GPIO_NMI_EN } - -#define PCH_GPIO_OUT_LOW(gpio) { \ - .num = (gpio), \ - .use_sel = GPIO_MODE_GPIO, \ - .io_sel = GPIO_OUTPUT, \ - .level = GPIO_OUT_LEVEL_LOW } - -#define PCH_GPIO_OUT_HIGH(gpio) { \ - .num = (gpio), \ - .use_sel = GPIO_MODE_GPIO, \ - .io_sel = GPIO_OUTPUT, \ - .level = GPIO_OUT_LEVEL_HIGH } - -#define PCH_GPIO_OUT_BLINK(gpio) { \ - .num = (gpio), \ - .use_sel = GPIO_MODE_GPIO, \ - .io_sel = GPIO_OUTPUT, \ - .blink_en = GPIO_OUT_BLINK } - -struct gpio_config { - uint8_t num; - uint8_t use_sel; - uint8_t io_sel; - uint8_t level; - uint8_t blink_en; - uint8_t nmi_en; - uint8_t invert_input; -} __packed; - -/* Unfortunately the register layout is not linear between different GPIO banks. - * In addition not every bank has all the functions so that some registers might - * be missing on a particular bank. To make the code better readable introduce a - * wrapper structure for the register addresses for every bank. - */ -struct gpio_config_regs { - uint8_t use_sel; - uint8_t io_sel; - uint8_t level; - uint8_t nmi_en; - uint8_t blink_en; - uint8_t invert_input; -}; - -/* Define gpio_t here to be able to use src/include/gpio.h for gpio_set() and - gpio_get().*/ -typedef uint8_t gpio_t; - -/* Configure GPIOs with mainboard provided settings */ -void init_gpios(const struct gpio_config config[]); - -#endif /* FSP_BROADWELL_DE_GPIO_H_ */ diff --git a/src/soc/intel/fsp_broadwell_de/include/soc/iomap.h b/src/soc/intel/fsp_broadwell_de/include/soc/iomap.h deleted file mode 100644 index ac04c63af7..0000000000 --- a/src/soc/intel/fsp_broadwell_de/include/soc/iomap.h +++ /dev/null @@ -1,71 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2013 Google Inc. - * Copyright (C) 2015-2016 Intel Corp. - * Copyright (C) 2017 Siemens AG - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef _SOC_IOMAP_H_ -#define _SOC_IOMAP_H_ - -/* - * Memory Mapped IO bases. - */ - -/* PCI Configuration Space */ -#define MCFG_BASE_ADDRESS CONFIG_MMCONF_BASE_ADDRESS -#define MCFG_BASE_SIZE 0x10000000 - -/* Transactions in this range will abort */ -#define ABORT_BASE_ADDRESS 0xfeb00000 -#define ABORT_BASE_SIZE 0x00010000 - -/* PSEG */ -#define PSEG_BASE_ADDRESS 0xfeb80000 -#define PSEG_BASE_SIZE 0x00080000 - -/* IOxAPIC */ -#define IOXAPIC1_BASE_ADDRESS 0xfec00000 -#define IOXAPIC1_BASE_SIZE 0x00100000 -#define IOXAPIC2_BASE_ADDRESS 0xfec01000 -#define IOXAPIC2_BASE_SIZE 0x00100000 - -/* PCH (HPET/LT/TPM/Others) */ -#define PCH_BASE_ADDRESS 0xfed00000 -#define PCH_BASE_SIZE 0x00100000 - -/* Local XAPIC */ -#define LXAPIC_BASE_ADDRESS 0xfee00000 -#define LXAPIC_BASE_SIZE 0x00100000 - -/* High Performance Event Timer */ -#define HPET_BASE_ADDRESS 0xfed00000 -#define HPET_BASE_SIZE 0x400 - -/* Firmware */ -#define FIRMWARE_BASE_ADDRESS 0xff000000 -#define FIRMWARE_BASE_SIZE 0x01000000 - -/* - * IO Port bases. - */ - -/* ACPI Base Address */ -#define ACPI_BASE_ADDRESS 0x400 -#define ACPI_BASE_SIZE 0x80 - -/* GPIO Base Address */ -#define GPIO_BASE_ADDRESS 0x500 -#define GPIO_BASE_SIZE 0x80 - -#endif /* _SOC_IOMAP_H_ */ diff --git a/src/soc/intel/fsp_broadwell_de/include/soc/irq.h b/src/soc/intel/fsp_broadwell_de/include/soc/irq.h deleted file mode 100644 index 1344f3b880..0000000000 --- a/src/soc/intel/fsp_broadwell_de/include/soc/irq.h +++ /dev/null @@ -1,98 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2013 Google Inc. - * Copyright (C) 2015-2016 Intel Corp. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef _SOC_IRQ_H_ -#define _SOC_IRQ_H_ - -#define PIRQA_APIC_IRQ 16 -#define PIRQB_APIC_IRQ 17 -#define PIRQC_APIC_IRQ 18 -#define PIRQD_APIC_IRQ 19 -#define PIRQE_APIC_IRQ 20 -#define PIRQF_APIC_IRQ 21 -#define PIRQG_APIC_IRQ 22 -#define PIRQH_APIC_IRQ 23 - -/* PIC IRQ settings. */ -#define PIRQ_PIC_IRQ3 0x3 -#define PIRQ_PIC_IRQ4 0x4 -#define PIRQ_PIC_IRQ5 0x5 -#define PIRQ_PIC_IRQ6 0x6 -#define PIRQ_PIC_IRQ7 0x7 -#define PIRQ_PIC_IRQ9 0x9 -#define PIRQ_PIC_IRQ10 0xa -#define PIRQ_PIC_IRQ11 0xb -#define PIRQ_PIC_IRQ12 0xc -#define PIRQ_PIC_IRQ14 0xe -#define PIRQ_PIC_IRQ15 0xf -#define PIRQ_PIC_IRQDISABLE 0x80 -#define PIRQ_PIC_UNKNOWN_UNUSED 0xff - -/* Overloaded term, but these values determine the per device route. */ -#define PIRQA 0 -#define PIRQB 1 -#define PIRQC 2 -#define PIRQD 3 -#define PIRQE 4 -#define PIRQF 5 -#define PIRQG 6 -#define PIRQH 7 - -#define ACPI_CNTL_OFFSET 0x44 -#define SCIS_MASK 0x07 -#define SCIS_IRQ9 0x00 -#define SCIS_IRQ10 0x01 -#define SCIS_IRQ11 0x02 -#define SCIS_IRQ20 0x04 -#define SCIS_IRQ21 0x05 -#define SCIS_IRQ22 0x06 -#define SCIS_IRQ23 0x07 - -/* In each mainboard directory there should exist a header file irqroute.h that - * defines the PCI_DEV_PIRQ_ROUTES and PIRQ_PIC_ROUTES macros which - * consist of PCI_DEV_PIRQ_ROUTE and PIRQ_PIC entries. */ - -#if !defined(__ASSEMBLER__) && !defined(__ACPI__) -#include - -#define NUM_OF_PCI_DEVS 32 -#define NUM_PIRQS 8 - -struct broadwell_de_irq_route { - /* Per device configuration. */ - uint16_t pcidev[NUM_OF_PCI_DEVS]; - /* Route path for each internal PIRQx in PIC mode. */ - uint8_t pic[NUM_PIRQS]; -}; - -extern const struct broadwell_de_irq_route global_broadwell_de_irq_route; - -#define DEFINE_IRQ_ROUTES \ - const struct broadwell_de_irq_route global_broadwell_de_irq_route = { \ - .pcidev = { PCI_DEV_PIRQ_ROUTES, }, \ - .pic = { PIRQ_PIC_ROUTES, }, \ - } - -#define PCI_DEV_PIRQ_ROUTE(dev_, a_, b_, c_, d_) \ - [dev_] = ((PIRQ ## d_) << 12) | ((PIRQ ## c_) << 8) | \ - ((PIRQ ## b_) << 4) | ((PIRQ ## a_) << 0) - -#define PIRQ_PIC(pirq_, pic_irq_) \ - [PIRQ ## pirq_] = PIRQ_PIC_IRQ ## pic_irq_ - -#endif /* !defined(__ASSEMBLER__) && !defined(__ACPI__) */ - -#endif /* _SOC_IRQ_H_ */ diff --git a/src/soc/intel/fsp_broadwell_de/include/soc/lpc.h b/src/soc/intel/fsp_broadwell_de/include/soc/lpc.h deleted file mode 100644 index 3f9c2024f7..0000000000 --- a/src/soc/intel/fsp_broadwell_de/include/soc/lpc.h +++ /dev/null @@ -1,126 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2013 Google Inc. - * Copyright (C) 2015-2016 Intel Corp. - * Copyright (C) 2017 Siemens AG - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef _SOC_LPC_H_ -#define _SOC_LPC_H_ - -#include - -/* LPC Interface Bridge PCI Configuration Registers */ -#define GPIO_BASE_ADR_OFFSET 0x48 -#define GPIO_CTRL_OFFSET 0x4c -#define GPIO_DECODE_ENABLE (1 << 4) -#define REVID 0x08 -#define PIRQ_RCR1 0x60 -#define SIRQ_CNTL 0x64 -#define SIRQ_EN 0x80 -#define SIRQ_MODE_QUIET 0x00 -#define SIRQ_MODE_CONT 0x40 -#define PIRQ_RCR2 0x68 -#define LPC_IO_DEC 0x80 -#define LPC_EN 0x82 -#define LPC_GEN1_DEC 0x84 -#define LPC_GEN2_DEC 0x88 -#define LPC_GEN3_DEC 0x8c -#define LPC_GEN4_DEC 0x90 -#define GEN_PMCON_1 0xA0 -#define SMI_LOCK (1 << 4) -#define SMI_LOCK_GP6 (1 << 5) -#define SMI_LOCK_GP22 (1 << 6) -#define GEN_PMCON_2 0xA2 -#define GEN_PMCON_3 0xA4 -#define RTC_PWR_STS (1 << 2) - -/* Default IO range claimed by the LPC device. The upper bound is exclusive. */ -#define LPC_DEFAULT_IO_RANGE_LOWER 0 -#define LPC_DEFAULT_IO_RANGE_UPPER 0x1000 - -/* IO Mapped registers behind ACPI_BASE_ADDRESS */ -#define PM1_STS 0x00 -#define WAK_STS (1 << 15) -#define PCIEXPWAK_STS (1 << 14) -#define USB_STS (1 << 13) -#define PRBTNOR_STS (1 << 11) -#define RTC_STS (1 << 10) -#define PWRBTN_STS (1 << 8) -#define GBL_STS (1 << 5) -#define TMROF_STS (1 << 0) -#define PM1_EN 0x02 -#define PCIEXPWAK_DIS (1 << 14) -#define RTC_EN (1 << 10) -#define PWRBTN_EN (1 << 8) -#define GBL_EN (1 << 5) -#define TMROF_EN (1 << 0) -#define PM1_CNT 0x04 -#define GBL_RLS (1 << 2) -#define BM_RLD (1 << 1) -#define SCI_EN (1 << 0) -#define PM1_TMR 0x08 -#define GPE0_STS 0x20 -#define PCI_EXP_STS (1 << 9) -#define RI_STS (1 << 8) -#define SMB_WAK_STS (1 << 7) -#define TCOSCI_STS (1 << 6) -#define SWGPE_STS (1 << 2) -#define HOT_PLUG_STS (1 << 1) -#define GPE0_EN 0x28 -#define SMI_EN 0x30 -#define XHCI_SMI_EN (1 << 31) -#define ME_SMI_EN (1 << 30) -#define GPIO_UNLOCK_SMI_EN (1 << 27) -#define INTEL_USB2_EN (1 << 18) -#define LEGACY_USB2_EN (1 << 17) -#define PERIODIC_EN (1 << 14) -#define TCO_EN (1 << 13) -#define MCSMI_EN (1 << 11) -#define BIOS_RLS (1 << 7) -#define SWSMI_TMR_EN (1 << 6) -#define APMC_EN (1 << 5) -#define SLP_SMI_EN (1 << 4) -#define LEGACY_USB_EN (1 << 3) -#define BIOS_EN (1 << 2) -#define EOS (1 << 1) -#define GBL_SMI_EN (1 << 0) -#define SMI_STS 0x34 -#define ALT_GPIO_SMI 0x38 -#define UPRWC 0x3c -#define UPRWC_WR_EN (1 << 1) // USB Per-Port Registers Write Enable -#define GPE_CTRL 0x40 -#define PM2A_CNT_BLK 0x50 -#define TCO_RLD 0x60 -#define TCO_STS 0x64 -#define SECOND_TO_STS (1 << 17) -#define TCO_TIMEOUT (1 << 3) -#define TCO1_CNT 0x68 -#define TCO_LOCK (1 << 12) -#define TCO_TMR_HALT (1 << 11) -#define TCO_TMR 0x70 - -/* PM1_CNT */ -void enable_pm1_control(uint32_t mask); -void disable_pm1_control(uint32_t mask); - -/* PM1 */ -uint16_t clear_pm1_status(void); -void enable_pm1(uint16_t events); -uint32_t clear_smi_status(void); - -/* SMI */ -void enable_smi(uint32_t mask); -void disable_smi(uint32_t mask); - -#endif /* _SOC_LPC_H_ */ diff --git a/src/soc/intel/fsp_broadwell_de/include/soc/memory.h b/src/soc/intel/fsp_broadwell_de/include/soc/memory.h deleted file mode 100644 index 3bdba2ef56..0000000000 --- a/src/soc/intel/fsp_broadwell_de/include/soc/memory.h +++ /dev/null @@ -1,30 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2019 Facebook, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef _SOC_MEMORY_H_ -#define _SOC_MEMORY_H_ - -/* EDS vol 2, 9.2.24 */ -#define REG_MC_BIOS_REQ 0x98 -#define REG_MC_BIOS_REQ_FREQ_MSK ((1u << 6) - 1) -#define REG_MC_MULTIPLIER 133.33f - -#define IMC_MAX_CHANNELS 2 - -#define SPD_SLAVE_ADDR(chan, slot) (2 * chan + slot) - -void save_dimm_info(void); - -#endif diff --git a/src/soc/intel/fsp_broadwell_de/include/soc/msr.h b/src/soc/intel/fsp_broadwell_de/include/soc/msr.h deleted file mode 100644 index f9fdffb2bf..0000000000 --- a/src/soc/intel/fsp_broadwell_de/include/soc/msr.h +++ /dev/null @@ -1,42 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2013 Google, Inc. - * Copyright (C) 2015-2016 Intel Corp. - * Copyright (C) 2017 Siemens AG - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef _SOC_MSR_H_ -#define _SOC_MSR_H_ - -#define MSR_CORE_THREAD_COUNT 0x35 -#define MSR_PLATFORM_INFO 0xce -#define MSR_TURBO_RATIO_LIMIT 0x1ad -#define MSR_PKG_POWER_SKU_UNIT 0x606 -#define MSR_PKG_POWER_LIMIT 0x610 -#define MSR_UNCORE_RATIO_LIMIT 0x620 -#define MSR_CONFIG_TDP_NOMINAL 0x648 - -#define SMM_MCA_CAP_MSR 0x17d -#define SMM_CPU_SVRSTR_BIT 57 -#define SMM_CPU_SVRSTR_MASK (1 << (SMM_CPU_SVRSTR_BIT - 32)) - -/* SMM save state MSRs */ -#define SMBASE_MSR 0xc20 -#define IEDBASE_MSR 0xc22 -/* MTRR_CAP_MSR bits */ -#define SMRR_SUPPORTED (1 << 11) -#define PRMRR_SUPPORTED (1 << 12) -#define MSR_PRMRR_PHYS_BASE 0x1f4 -#define MSR_PRMRR_PHYS_MASK 0x1f5 - -#endif /* _SOC_MSR_H_ */ diff --git a/src/soc/intel/fsp_broadwell_de/include/soc/pattrs.h b/src/soc/intel/fsp_broadwell_de/include/soc/pattrs.h deleted file mode 100644 index 232a4f4a7d..0000000000 --- a/src/soc/intel/fsp_broadwell_de/include/soc/pattrs.h +++ /dev/null @@ -1,52 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2013 Google Inc. - * Copyright (C) 2015-2016 Intel Corp. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef _SOC_PATTRS_H_ -#define _SOC_PATTRS_H_ - -#include -#include - -/* - * The pattrs structure is a common place to stash pertinent information - * about the processor or platform. Instead of going to the source (msrs, cpuid) - * every time an attribute is needed use the pattrs structure. - */ -struct pattrs { - msr_t platform_id; - msr_t platform_info; - uint32_t cpuid; - int revid; - int stepping; - const void *microcode_patch; - int address_bits; - int num_cpus; -}; - -/* - * This is just to hide the abstraction w/o relying on how the underlying - * storage is allocated. - */ -#define PATTRS_GLOB_NAME __global_pattrs -#define DEFINE_PATTRS struct pattrs PATTRS_GLOB_NAME -extern DEFINE_PATTRS; - -static inline const struct pattrs *pattrs_get(void) -{ - return &PATTRS_GLOB_NAME; -} - -#endif /* _SOC_PATTRS_H_ */ diff --git a/src/soc/intel/fsp_broadwell_de/include/soc/pci_devs.h b/src/soc/intel/fsp_broadwell_de/include/soc/pci_devs.h deleted file mode 100644 index 6a68b2f81f..0000000000 --- a/src/soc/intel/fsp_broadwell_de/include/soc/pci_devs.h +++ /dev/null @@ -1,147 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2013 Google Inc. - * Copyright (C) 2015-2016 Intel Corp. - * Copyright (C) 2017 Siemens AG - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef _SOC_PCI_DEVS_H_ -#define _SOC_PCI_DEVS_H_ - -#include - -#define BUS0 0 - -#define SOC_DEV 0 -#define SOC_FUNC 0 - -/* DMI2/PCIe link to PCH */ -#define PCIE_IIO_PORT_0_DEV 0x00 -#define PCIE_IIO_PORT_0_FUNC 0x00 - -/* IOU2, x8 PCIe Gen3 port */ -#define PCIE_IIO_PORT_1_DEV 0x01 -#define PCIE_IIO_PORT_1A_FUNC 0x00 -#define PCIE_IIO_PORT_1B_FUNC 0x01 - -/* IOU0: Internal IOSF bridge to 10 GbE and CBDMA */ -#define PCIE_IIO_PORT_2_DEV 0x02 -#define PCIE_IIO_PORT_2A_FUNC 0x00 -#define PCIE_IIO_PORT_2B_FUNC 0x01 -#define PCIE_IIO_PORT_2C_FUNC 0x02 -#define PCIE_IIO_PORT_2D_FUNC 0x03 - -/* IOU1: x16 PCIe Gen3 port */ -#define PCIE_IIO_PORT_3_DEV 0x03 -#define PCIE_IIO_PORT_3A_FUNC 0x00 -#define PCIE_IIO_PORT_3B_FUNC 0x01 -#define PCIE_IIO_PORT_3C_FUNC 0x02 -#define PCIE_IIO_PORT_3D_FUNC 0x03 - -#define VTD_DEV 5 -#define VTD_FUNC 0 -#define IIO_DEVFN_VTD PCI_DEVFN(VTD_DEV, VTD_FUNC) -#define VTD_PCI_DEV PCI_DEV(BUS0, VTD_DEV, VTD_FUNC) - -#define LPC_DEV 31 -#define LPC_FUNC 0 -#define PCH_DEVFN_LPC PCI_DEVFN(LPC_DEV, LPC_FUNC) - -#define SATA_DEV 31 -#define SATA_FUNC 2 - -#define SMBUS_DEV 31 -#define SMBUS_FUNC 3 - -#define SATA2_DEV 31 -#define SATA2_FUNC 5 - -#define EHCI1_DEV 29 -#define EHCI1_FUNC 0 - -#define EHCI2_DEV 26 -#define EHCI2_FUNC 0 - -#define XHCI_DEV 20 -#define XHCI_FUNC 0 -#define XHCI_FUS_REG 0xE0 -#define XHCI_FUNC_DISABLE (1 << 0) -#define XHCI_USB2PR_REG 0xD0 - -#define GBE_DEV 25 -#define GBE_FUNC 0 - -#define ME_DEV 22 -#define ME_FUNC 0 - -#define HDA_DEV 27 -#define HDA_FUNC 0 - -/* Ports from PCH block with adjustable burification settings */ -#define PCIE_DEV 28 -#define PCIE_PORT1_DEV PCIE_DEV -#define PCIE_PORT1_FUNC 0 -#define PCIE_PORT2_DEV PCIE_DEV -#define PCIE_PORT2_FUNC 1 -#define PCIE_PORT3_DEV PCIE_DEV -#define PCIE_PORT3_FUNC 2 -#define PCIE_PORT4_DEV PCIE_DEV -#define PCIE_PORT4_FUNC 3 -#define PCIE_PORT5_DEV PCIE_DEV -#define PCIE_PORT5_FUNC 4 -#define PCIE_PORT6_DEV PCIE_DEV -#define PCIE_PORT6_FUNC 5 -#define PCIE_PORT7_DEV PCIE_DEV -#define PCIE_PORT7_FUNC 6 -#define PCIE_PORT8_DEV PCIE_DEV -#define PCIE_PORT8_FUNC 7 - -/* The SMM device is located on bus 0xff (QPI) */ -#define QPI_BUS 0xff -#define SMM_DEV 0x10 -#define SMM_FUNC 0x06 - -#define IMC_DEV0 19 -#define IMC_FUNC0 0 - -#define IMC_DEV PCI_DEV(QPI_BUS, IMC_DEV0, IMC_FUNC0) - -#define PCU1_DEV 30 -#define PCU1_FUNC 01 -#define UBOX_DEV 16 -#define UBOX_FUNC 7 - - -#define SOC_DEVID 0x2F00 -#define SOC_DEVID_ES2 0x6F00 -#define VTD_DEVID 0x6f28 -#define LPC_DEVID 0x8C42 -#define LPC_DEVID_ES2 0x8C54 -#define AHCI_DEVID 0x8C02 -#define SMBUS_DEVID 0x8C22 -#define EHCI1_DEVID 0x8C26 -#define EHCI2_DEVID 0x8C2D -#define XHCI_DEVID 0x8C31 -#define GBE_DEVID 0x8C33 -#define ME_DEVID 0x8C3A -#define HDA_DEVID 0x8C20 -#define PCIE_PORT1_DEVID 0x8C10 -#define PCIE_PORT2_DEVID 0x8C12 -#define PCIE_PORT3_DEVID 0x8C14 -#define PCIE_PORT4_DEVID 0x8C16 -#define PCIE_PORT5_DEVID 0x8C18 -#define PCIE_PORT6_DEVID 0x8C1A -#define PCIE_PORT7_DEVID 0x8C1C -#define PCIE_PORT8_DEVID 0x8C1E - -#endif /* _SOC_PCI_DEVS_H_ */ diff --git a/src/soc/intel/fsp_broadwell_de/include/soc/ramstage.h b/src/soc/intel/fsp_broadwell_de/include/soc/ramstage.h deleted file mode 100644 index 69fb687276..0000000000 --- a/src/soc/intel/fsp_broadwell_de/include/soc/ramstage.h +++ /dev/null @@ -1,32 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2013 Google Inc. - * Copyright (C) 2015-2016 Intel Corp. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef _SOC_RAMSTAGE_H_ -#define _SOC_RAMSTAGE_H_ - -#include - -/* The broadwell_de_init_pre_device() function is called prior to device - * initialization, but it's after console and cbmem has been reinitialized. */ -void broadwell_de_init_pre_device(void); -void broadwell_de_init_cpus(struct device *dev); -void southcluster_enable_dev(struct device *dev); -void broadwell_de_set_dpr(const uintptr_t addr, const size_t size); -void broadwell_de_lock_dpr(void); - -extern struct pci_operations soc_pci_ops; - -#endif /* _SOC_RAMSTAGE_H_ */ diff --git a/src/soc/intel/fsp_broadwell_de/include/soc/romstage.h b/src/soc/intel/fsp_broadwell_de/include/soc/romstage.h deleted file mode 100644 index 6ee160de28..0000000000 --- a/src/soc/intel/fsp_broadwell_de/include/soc/romstage.h +++ /dev/null @@ -1,28 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2013 Google Inc. - * Copyright (C) 2015-2016 Intel Corp. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef _SOC_ROMSTAGE_H_ -#define _SOC_ROMSTAGE_H_ - -#include -#include - -#define NUM_ROMSTAGE_TS 4 - -void early_mainboard_romstage_entry(void); -void late_mainboard_romstage_entry(void); - -#endif /* _SOC_ROMSTAGE_H_ */ diff --git a/src/soc/intel/fsp_broadwell_de/include/soc/smbus.h b/src/soc/intel/fsp_broadwell_de/include/soc/smbus.h deleted file mode 100644 index 4d9d3e1f57..0000000000 --- a/src/soc/intel/fsp_broadwell_de/include/soc/smbus.h +++ /dev/null @@ -1,48 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2005 Yinghai Lu - * Copyright (C) 2009 coresystems GmbH - * Copyright (C) 2014 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef _BROADWELL_SMBUS_H_ -#define _BROADWELL_SMBUS_H_ - -/* PCI Configuration Space (D31:F3): SMBus */ -#define SMB_BASE 0x20 -#define HOSTC 0x40 -#define HST_EN (1 << 0) -#define SMB_RCV_SLVA 0x09 - -/* SMBus I/O bits. */ -#define SMBHSTSTAT 0x0 -#define SMBHSTCTL 0x2 -#define SMBHSTCMD 0x3 -#define SMBXMITADD 0x4 -#define SMBHSTDAT0 0x5 -#define SMBHSTDAT1 0x6 -#define SMBBLKDAT 0x7 -#define SMBTRNSADD 0x9 -#define SMBSLVDATA 0xa -#define SMLINK_PIN_CTL 0xe -#define SMBUS_PIN_CTL 0xf - -#define SMBUS_TIMEOUT (10 * 1000 * 100) -#define SMBUS_SLAVE_ADDR 0x24 - -int do_smbus_read_byte(unsigned int smbus_base, unsigned int device, - unsigned int address); -int do_smbus_write_byte(unsigned int smbus_base, unsigned int device, - unsigned int address, unsigned int data); - -#endif diff --git a/src/soc/intel/fsp_broadwell_de/include/soc/smm.h b/src/soc/intel/fsp_broadwell_de/include/soc/smm.h deleted file mode 100644 index 867bf60a5e..0000000000 --- a/src/soc/intel/fsp_broadwell_de/include/soc/smm.h +++ /dev/null @@ -1,38 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2014 Google Inc. - * Copyright (C) 2017 Siemens AG - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef _BROADWELL_SMM_H_ -#define _BROADWELL_SMM_H_ - -#include -#include - - -struct smm_relocation_params { - uintptr_t ied_base; - size_t ied_size; - msr_t smrr_base; - msr_t smrr_mask; - msr_t prmrr_base; - msr_t prmrr_mask; - /* The smm_save_state_in_msrs field indicates if SMM save state - locations live in MSRs. This indicates to the CPUs how to adjust - the SMMBASE and IEDBASE. */ - int smm_save_state_in_msrs; -}; - - -#endif diff --git a/src/soc/intel/fsp_broadwell_de/include/soc/ubox.h b/src/soc/intel/fsp_broadwell_de/include/soc/ubox.h deleted file mode 100644 index 3c2e6f50a6..0000000000 --- a/src/soc/intel/fsp_broadwell_de/include/soc/ubox.h +++ /dev/null @@ -1,44 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2019 Facebook, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -/* - * As per "Intel Xeon Processor D-1500 Product Family" volume 2, - * "The UBOX [Processor Utility Box] is the piece of processor logic that deals with - * the non mainstream flows in the system. This includes transactions like the register - * accesses, interrupt flows, lock flows and events. In addition, the UBOX houses - * coordination for the performance architecture, and also houses scratchpad and - * semaphore registers." - * - * In other words, this is a one-die block that has all the useful magic registers. -*/ - -#ifndef _BROADWELL_UBOX_H_ -#define _BROADWELL_UBOX_H_ - -#include -#include -#include - -#define UBOX_UART_ENABLE 0xf8 -#define UBOX_UART_ENABLE_PORT0 (1u << 0) -#define UBOX_UART_ENABLE_PORT1 (1u << 1) - -#define UBOX_SC_RESET_STATUS 0xc8 -#define UBOX_SC_BYPASS (1u << 3) - -#define UBOX_DEVHIDE0 0xb0 - -void iio_hide(DEVTREE_CONST struct device *dev); -#endif diff --git a/src/soc/intel/fsp_broadwell_de/include/soc/vtd.h b/src/soc/intel/fsp_broadwell_de/include/soc/vtd.h deleted file mode 100644 index f1087d1997..0000000000 --- a/src/soc/intel/fsp_broadwell_de/include/soc/vtd.h +++ /dev/null @@ -1,35 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2019 Facebook, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef _BROADWELL_VTD_H_ -#define _BROADWELL_VTD_H_ - -#include -#include - -#define VTD_CPUBUSNO 0x108 -#define VTD_CPUBUSNO_BUS0_MASK 0xff -#define VTD_CPUBUSNO_BUS0_SHIFT 0 -#define VTD_CPUBUSNO_BUS1_MASK 0xff -#define VTD_CPUBUSNO_BUS1_SHIFT 8 -#define VTD_CPUBUSNO_ISVALID (1u << 16) - -#define VTD_DFX1 0x804 -#define VTD_DFX1_RANGE_3F8_DISABLE (1u << 29) -#define VTD_DFX1_RANGE_2F8_DISABLE (1u << 30) - -uint8_t get_busno1(void); - -#endif diff --git a/src/soc/intel/fsp_broadwell_de/iou_complto.c b/src/soc/intel/fsp_broadwell_de/iou_complto.c deleted file mode 100644 index b092f53875..0000000000 --- a/src/soc/intel/fsp_broadwell_de/iou_complto.c +++ /dev/null @@ -1,53 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2015 Arista Networks, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include -#include -#include - -#define DEVCTL2 0xb8 - -static void iou_init(struct device *dev) -{ - /* Use config from device always present in static devicetree. */ - const config_t *config = config_of_soc(); - u16 devctl2; - - /* pcie completion timeout - EDS Vol 2, Section 7.2.54 */ - devctl2 = pci_read_config16(dev, DEVCTL2); - devctl2 = (devctl2 & ~0xf) | (config->pcie_compltoval & 0xf); - pci_write_config16(dev, DEVCTL2, devctl2); -} - -static struct device_operations iou_ops = { - .read_resources = pci_bus_read_resources, - .set_resources = pci_dev_set_resources, - .enable_resources = pci_bus_enable_resources, - .scan_bus = pci_scan_bridge, - .reset_bus = pci_bus_reset, - .init = iou_init, -}; - -static const unsigned short iou_device_ids[] = { - 0x6f02, 0x6f08, 0 }; - -static const struct pci_driver iou_driver __pci_driver = { - .ops = &iou_ops, - .vendor = PCI_VENDOR_ID_INTEL, - .devices = iou_device_ids, -}; diff --git a/src/soc/intel/fsp_broadwell_de/memmap.c b/src/soc/intel/fsp_broadwell_de/memmap.c deleted file mode 100644 index 96eb20502c..0000000000 --- a/src/soc/intel/fsp_broadwell_de/memmap.c +++ /dev/null @@ -1,60 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2013 Google, Inc. - * Copyright (C) 2015-2016 Intel Corp. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#define __SIMPLE_DEVICE__ - -#include -#include -#include -#include -#include -#include - -void *cbmem_top_chipset(void) -{ - return find_fsp_reserved_mem(*(void **)CBMEM_FSP_HOB_PTR); -} - -/* - * Get TSEG base. - */ -uintptr_t sa_get_tseg_base(void) -{ - const pci_devfn_t dev = PCI_DEV(BUS0, VTD_DEV, VTD_FUNC); - - /* All regions concerned for have 1 MiB alignment. */ - return ALIGN_DOWN(pci_read_config32(dev, TSEG_BASE), 1 * MiB); -} - -size_t sa_get_tseg_size(void) -{ - const pci_devfn_t dev = PCI_DEV(BUS0, VTD_DEV, VTD_FUNC); - - /* All regions concerned for have 1 MiB alignment. */ - size_t ret = ALIGN_DOWN(pci_read_config32(dev, TSEG_LIMIT), 1 * MiB); - - /* Lower 20bit of TSEG_LIMIT are don't care, need to add 1MiB */ - ret += 1 * MiB; - - /* Subtract base to get the size */ - return ret - sa_get_tseg_base(); -} - -void smm_region(uintptr_t *start, size_t *size) -{ - *start = sa_get_tseg_base(); - *size = sa_get_tseg_size(); -} diff --git a/src/soc/intel/fsp_broadwell_de/northcluster.c b/src/soc/intel/fsp_broadwell_de/northcluster.c deleted file mode 100644 index a630c1bba4..0000000000 --- a/src/soc/intel/fsp_broadwell_de/northcluster.c +++ /dev/null @@ -1,156 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2013 Google Inc. - * Copyright (C) 2015-2016 Intel Corp. - * Copyright (C) 2016-2018 Siemens AG - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -static const int legacy_hole_base_k = 0xa0000 / 1024; -static const int legacy_hole_size_k = 384; - -static void add_fixed_resources(struct device *dev, int index) -{ - struct resource *resource; - u32 pcie_config_base, pcie_config_size; - pcie_config_base = MCFG_BASE_ADDRESS; - pcie_config_size = MCFG_BASE_SIZE; - - printk(BIOS_DEBUG, "Adding PCIe config bar base=0x%08x " - "size=0x%x\n", pcie_config_base, pcie_config_size); - resource = new_resource(dev, index++); - resource->base = (resource_t) pcie_config_base; - resource->size = (resource_t) pcie_config_size; - resource->flags = IORESOURCE_MEM | IORESOURCE_RESERVE | - IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED; - - resource = new_resource(dev, index++); /* Local APIC */ - resource->base = LAPIC_DEFAULT_BASE; - resource->size = 0x00001000; - resource->flags = IORESOURCE_MEM | IORESOURCE_RESERVE | - IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED; - - mmio_resource(dev, index++, legacy_hole_base_k, legacy_hole_size_k); -} - -static void mc_add_dram_resources(struct device *dev) -{ - u32 fsp_mem_base, fsp_mem_len; - u32 tseg_base, tseg_length; - u32 rsv_base, rsv_length; - u32 tolm; - int index = 0; - uint64_t highmem_size = 0; - - fsp_mem_base = GetFspReservedMemory(FspHobListPtr, &fsp_mem_len); - highmem_size = GetUsableHighMemTop(FspHobListPtr) - 0x100000000L; - tseg_base = GetTsegReservedMemory(FspHobListPtr, &tseg_length); - tolm = GetPhysicalLowMemTop(FspHobListPtr); - - printk(BIOS_DEBUG, "\n\n"); - printk(BIOS_DEBUG, "fsp_mem_base: 0x%.8x\n", fsp_mem_base); - printk(BIOS_DEBUG, "fsp_mem_len: 0x%.8x\n", fsp_mem_len); - printk(BIOS_DEBUG, "tseg_base: 0x%.8x\n", tseg_base); - printk(BIOS_DEBUG, "tseg_len: 0x%.8x\n", tseg_length); - printk(BIOS_DEBUG, "highmem_size: 0x%.8x %.8x\n", - (u32)(highmem_size>>32), - (u32)(highmem_size&0xffffffff)); - printk(BIOS_DEBUG, "tolm: 0x%.8x\n", tolm); - printk(BIOS_DEBUG, "Top of system low memory: 0x%08x\n", tolm); - printk(BIOS_DEBUG, "FSP memory location: 0x%x\n (size: %dM)\n", - fsp_mem_base, fsp_mem_len >> 20); - printk(BIOS_DEBUG, "tseg: 0x%08x (size: 0x%.8x)\n", - tseg_base, tseg_length); - - /* Report the memory regions. */ - ram_resource(dev, index++, 0, legacy_hole_base_k); - ram_resource(dev, index++, legacy_hole_base_k + legacy_hole_size_k, - ((fsp_mem_base >> 10) - (legacy_hole_base_k + legacy_hole_size_k))); - - /* Mark SMM & FSP regions reserved */ - mmio_resource(dev, index++, tseg_base >> 10, tseg_length >> 10); - mmio_resource(dev, index++, fsp_mem_base >> 10, fsp_mem_len >> 10); - - /* Reserve MMIO space */ - rsv_base = fsp_mem_base + fsp_mem_len; - rsv_length = tseg_base - rsv_base; - if (rsv_length) { - mmio_resource(dev, index++, rsv_base >> 10, rsv_length >> 10); - printk(BIOS_DEBUG, "Reserved MMIO : 0x%08x length 0x%08x\n", - rsv_base, rsv_length); - } - - rsv_base = tseg_base + tseg_length; - rsv_length = tolm - rsv_base; - if (rsv_length) { - mmio_resource(dev, index++, rsv_base >> 10, rsv_length >> 10); - printk(BIOS_DEBUG, "Reserved MMIO : 0x%08x length 0x%08x\n", - rsv_base, rsv_length); - } - - if (highmem_size) { - ram_resource(dev, index++, 0x100000000 >> 10, highmem_size >> 10); - } - printk(BIOS_INFO, "Available memory above 4GB: %lluM\n", - highmem_size >> 20); - - add_fixed_resources(dev, index); -} - -static void nc_read_resources(struct device *dev) -{ - /* Call the normal read_resources */ - pci_dev_read_resources(dev); - - /* Calculate and add DRAM resources. */ - mc_add_dram_resources(dev); -} - -static void nc_enable(struct device *dev) -{ - print_fsp_info(); -} - -static struct device_operations nc_ops = { - .read_resources = nc_read_resources, - .acpi_fill_ssdt_generator = generate_cpu_entries, - .set_resources = pci_dev_set_resources, - .enable_resources = pci_dev_enable_resources, - .init = NULL, - .enable = &nc_enable, - .scan_bus = 0, - .ops_pci = &soc_pci_ops, -}; - -static const struct pci_driver nc_driver __pci_driver = { - .ops = &nc_ops, - .vendor = PCI_VENDOR_ID_INTEL, - .device = SOC_DEVID, -}; - -static const struct pci_driver nc_driver_es2 __pci_driver = { - .ops = &nc_ops, - .vendor = PCI_VENDOR_ID_INTEL, - .device = SOC_DEVID_ES2, -}; diff --git a/src/soc/intel/fsp_broadwell_de/pmutil.c b/src/soc/intel/fsp_broadwell_de/pmutil.c deleted file mode 100644 index ccab1cef33..0000000000 --- a/src/soc/intel/fsp_broadwell_de/pmutil.c +++ /dev/null @@ -1,173 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2014 Google Inc. - * Copyright (C) 2017 Siemens AG - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -/* - * Helper functions for dealing with power management registers - * and the differences between PCH variants. - */ - -#include -#include -#include -#include -#include -#include -#include -#include - -/* Print status bits with descriptive names */ -static void print_status_bits(u32 status, const char *const bit_names[]) -{ - int i; - - if (!status) - return; - - for (i = 31; i >= 0; i--) { - if (status & (1 << i)) { - if (bit_names[i]) - printk(BIOS_DEBUG, "%s ", bit_names[i]); - else - printk(BIOS_DEBUG, "BIT%d ", i); - } - } -} - -/* Enable events in PM1 control register */ -void enable_pm1_control(u32 mask) -{ - u32 pm1_cnt = inl(ACPI_BASE_ADDRESS + PM1_CNT); - pm1_cnt |= mask; - outl(pm1_cnt, ACPI_BASE_ADDRESS + PM1_CNT); -} - -/* Disable events in PM1 control register */ -void disable_pm1_control(u32 mask) -{ - u32 pm1_cnt = inl(ACPI_BASE_ADDRESS + PM1_CNT); - pm1_cnt &= ~mask; - outl(pm1_cnt, ACPI_BASE_ADDRESS + PM1_CNT); -} - -/* Clear and return PM1 status register */ -static u16 reset_pm1_status(void) -{ - u16 pm1_sts = inw(ACPI_BASE_ADDRESS + PM1_STS); - outw(pm1_sts, ACPI_BASE_ADDRESS + PM1_STS); - return pm1_sts; -} - -/* Print PM1 status bits */ -static u16 print_pm1_status(u16 pm1_sts) -{ - static const char *const pm1_sts_bits[] = { - [0] = "TMROF", - [4] = "BM", - [5] = "GBL", - [8] = "PWRBTN", - [10] = "RTC", - [11] = "PRBTNOR", - [14] = "PCIEXPWAK", - [15] = "WAK", - }; - - if (!pm1_sts) - return 0; - - printk(BIOS_SPEW, "PM1_STS: "); - print_status_bits(pm1_sts, pm1_sts_bits); - printk(BIOS_SPEW, "\n"); - - return pm1_sts; -} - -/* Print, clear, and return PM1 status */ -u16 clear_pm1_status(void) -{ - return print_pm1_status(reset_pm1_status()); -} - -/* Set the PM1 register to events */ -void enable_pm1(u16 events) -{ - outw(events, ACPI_BASE_ADDRESS + PM1_EN); -} - -/* Clear and return SMI status register */ -static u32 reset_smi_status(void) -{ - u32 smi_sts = inl(ACPI_BASE_ADDRESS + SMI_STS); - outl(smi_sts, ACPI_BASE_ADDRESS + SMI_STS); - return smi_sts; -} - -/* Print SMI status bits */ -static u32 print_smi_status(u32 smi_sts) -{ - static const char *const smi_sts_bits[] = { - [2] = "BIOS", - [3] = "LEGACY_USB", - [4] = "SLP_SMI", - [5] = "APM", - [6] = "SWSMI_TMR", - [8] = "PM1", - [9] = "GPE0", - [10] = "GPI", - [11] = "MCSMI", - [12] = "DEVMON", - [13] = "TCO", - [14] = "PERIODIC", - [15] = "SERIRQ_SMI", - [16] = "SMBUS_SMI", - [17] = "LEGACY_USB2", - [18] = "INTEL_USB2", - [20] = "PCI_EXP_SMI", - [21] = "MONITOR", - [26] = "SPI", - [27] = "GPIO_UNLOCK" - }; - - if (!smi_sts) - return 0; - - printk(BIOS_DEBUG, "SMI_STS: "); - print_status_bits(smi_sts, smi_sts_bits); - printk(BIOS_DEBUG, "\n"); - - return smi_sts; -} - -/* Print, clear, and return SMI status */ -u32 clear_smi_status(void) -{ - return print_smi_status(reset_smi_status()); -} - -/* Enable SMI event */ -void enable_smi(u32 mask) -{ - u32 smi_en = inl(ACPI_BASE_ADDRESS + SMI_EN); - smi_en |= mask; - outl(smi_en, ACPI_BASE_ADDRESS + SMI_EN); -} - -/* Disable SMI event */ -void disable_smi(u32 mask) -{ - u32 smi_en = inl(ACPI_BASE_ADDRESS + SMI_EN); - smi_en &= ~mask; - outl(smi_en, ACPI_BASE_ADDRESS + SMI_EN); -} diff --git a/src/soc/intel/fsp_broadwell_de/ramstage.c b/src/soc/intel/fsp_broadwell_de/ramstage.c deleted file mode 100644 index fd5a0392ff..0000000000 --- a/src/soc/intel/fsp_broadwell_de/ramstage.c +++ /dev/null @@ -1,129 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2013 Google Inc. - * Copyright (C) 2015-2016 Intel Corp. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -/* Global PATTRS */ -DEFINE_PATTRS; - -#define SHOW_PATTRS 1 - -static void detect_num_cpus(struct pattrs *attrs) -{ - msr_t core_thread_count = rdmsr(MSR_CORE_THREAD_COUNT); - attrs->num_cpus = core_thread_count.lo & 0xffff; -} - -static inline void fill_in_msr(msr_t *msr, int idx) -{ - *msr = rdmsr(idx); - if (SHOW_PATTRS) { - printk(BIOS_DEBUG, "msr(%x) = %08x%08x\n", - idx, msr->hi, msr->lo); - } -} - -static const char *stepping_str[] = { - "U0", "V1", "V2", "Y0" -}; - -static void fill_in_pattrs(void) -{ - struct device *dev; - struct pattrs *attrs = (struct pattrs *)pattrs_get(); - - attrs->cpuid = cpuid_eax(1); - attrs->stepping = (attrs->cpuid & 0x0F) - 1; - dev = pcidev_on_root(LPC_DEV, LPC_FUNC); - attrs->revid = pci_read_config8(dev, REVID); - attrs->microcode_patch = intel_microcode_find(); - attrs->address_bits = cpuid_eax(0x80000008) & 0xff; - detect_num_cpus(attrs); - - if (SHOW_PATTRS) { - printk(BIOS_DEBUG, "CPUID: %08x\n", attrs->cpuid); - printk(BIOS_DEBUG, "Cores: %d\n", attrs->num_cpus); - printk(BIOS_DEBUG, "Stepping: %s\n", (attrs->stepping >= ARRAY_SIZE(stepping_str)) - ? "??" : stepping_str[attrs->stepping]); - printk(BIOS_DEBUG, "Revision ID: %02x\n", attrs->revid); - } - - fill_in_msr(&attrs->platform_id, IA32_PLATFORM_ID); - fill_in_msr(&attrs->platform_info, MSR_PLATFORM_INFO); -} - -void broadwell_de_init_pre_device(void) -{ - fill_in_pattrs(); -} - -/* - * Set DPR region. - */ -void broadwell_de_set_dpr(const uintptr_t addr, const size_t size) -{ - struct device *dev; - uint32_t dpr_reg; - /* - * DMA Protected Range can be reserved below TSEG for PCODE patch - * or TXT/BootGuard related data. Rather than reporting a base address - * the DPR register reports the TOP of the region, which is the same - * as TSEG base. The region size is reported in MiB in bits 11:4. - */ - dev = pcidev_on_root(VTD_DEV, VTD_FUNC); - dpr_reg = pci_read_config32(dev, IIO_LTDPR); - if (dpr_reg & DPR_LOCK) { - printk(BIOS_ERR, "ERROR: HOSTBRIDGE[DPR] is already locked\n"); - return; - } - - dpr_reg &= ~(DPR_ADDR_MASK | DPR_SIZE_MASK); - dpr_reg |= addr & DPR_ADDR_MASK; - dpr_reg |= (size >> (20 - DPR_SIZE_SHIFT)) & DPR_SIZE_MASK; - dpr_reg |= DPR_EPM; - pci_write_config32(dev, IIO_LTDPR, dpr_reg); -} - -/* - * Lock DPR register. - */ -void broadwell_de_lock_dpr(void) -{ - struct device *dev; - uint32_t dpr_reg; - dev = pcidev_on_root(VTD_DEV, VTD_FUNC); - dpr_reg = pci_read_config32(dev, IIO_LTDPR); - if (dpr_reg & DPR_LOCK) { - printk(BIOS_ERR, "ERROR: HOSTBRIDGE[DPR] is already locked\n"); - return; - } - dpr_reg |= DPR_LOCK; - pci_write_config32(dev, IIO_LTDPR, dpr_reg); -} diff --git a/src/soc/intel/fsp_broadwell_de/romstage/Makefile.inc b/src/soc/intel/fsp_broadwell_de/romstage/Makefile.inc deleted file mode 100644 index 5c332018e0..0000000000 --- a/src/soc/intel/fsp_broadwell_de/romstage/Makefile.inc +++ /dev/null @@ -1,4 +0,0 @@ -romstage-y += romstage.c -romstage-y += memory.c - -$(obj)/soc/intel/fsp_broadwell_de/romstage/romstage.romstage.o : $(obj)/build.h diff --git a/src/soc/intel/fsp_broadwell_de/romstage/memory.c b/src/soc/intel/fsp_broadwell_de/romstage/memory.c deleted file mode 100644 index afbf97bf57..0000000000 --- a/src/soc/intel/fsp_broadwell_de/romstage/memory.c +++ /dev/null @@ -1,61 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2019 Facebook, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include -#include -#include -#include - -static uint32_t get_memory_dclk(void) -{ - uint32_t reg32 = - pci_mmio_read_config32(PCI_DEV(QPI_BUS, PCU1_DEV, PCU1_FUNC), REG_MC_BIOS_REQ); - return (reg32 & REG_MC_BIOS_REQ_FREQ_MSK) * REG_MC_MULTIPLIER; -} - -void save_dimm_info(void) -{ - int index = 0; - uint32_t dclk_mhz = 0; - - /* - * When talking to SPD chips through IMC slave offset of 0x50 is automagically added - * by hardware. Real-world slave numbers translate to: 0xa0, 0xa2, 0xa4, 0xa6. - */ - struct spd_block blk = {.addr_map = {SPD_SLAVE_ADDR(0, 0), SPD_SLAVE_ADDR(0, 1), - SPD_SLAVE_ADDR(1, 0), SPD_SLAVE_ADDR(1, 1)} }; - - get_spd_smbus(&blk); - dump_spd_info(&blk); - - dclk_mhz = get_memory_dclk(); - - /* - * The platform is limited to 2 channels and max 2 dimms per channel. - * It doesn't look like DDR3 is supported so we assume memory is all DDR4. - */ - - for (int channel = 0; channel < IMC_MAX_CHANNELS; channel++) { - for (int slot = 0; slot < CONFIG_DIMM_MAX / IMC_MAX_CHANNELS; slot++) { - dimm_attr dimm = {0}; - u8 *spd_data = blk.spd_array[index]; - if (spd_decode_ddr4(&dimm, spd_data) == SPD_STATUS_OK) - spd_add_smbios17_ddr4(channel, slot, dclk_mhz, &dimm); - index++; - } - } -} diff --git a/src/soc/intel/fsp_broadwell_de/romstage/romstage.c b/src/soc/intel/fsp_broadwell_de/romstage/romstage.c deleted file mode 100644 index 8438b1035c..0000000000 --- a/src/soc/intel/fsp_broadwell_de/romstage/romstage.c +++ /dev/null @@ -1,216 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2013 Google Inc. - * Copyright (C) 2015-2016 Intel Corp. - * Copyright (C) 2017 Siemens AG - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -static void init_rtc(void) -{ - u16 gen_pmcon3 = pci_read_config16(PCI_DEV(0, LPC_DEV, LPC_FUNC), GEN_PMCON_3); - - if (gen_pmcon3 & RTC_PWR_STS) { - printk(BIOS_DEBUG, "RTC Failure detected. Resetting Date to %s\n", - coreboot_dmi_date); - } - cmos_init(gen_pmcon3 & RTC_PWR_STS); -} - -/* Set up IO address range and enable it for the GPIO block. */ -static void setup_gpio_io_address(void) -{ - pci_write_config32(PCI_DEV(0, LPC_DEV, LPC_FUNC), GPIO_BASE_ADR_OFFSET, - GPIO_BASE_ADDRESS); - pci_write_config8(PCI_DEV(0, LPC_DEV, LPC_FUNC), GPIO_CTRL_OFFSET, - GPIO_DECODE_ENABLE); -} - - -static void enable_integrated_uart(uint8_t port) -{ - uint32_t ubox_uart_en = 0, dfx1 = 0; - pci_devfn_t ubox_dev; - - /* UBOX sits on CPUBUSNO(1) */ - ubox_dev = PCI_DEV(get_busno1(), UBOX_DEV, UBOX_FUNC); - uint32_t reset_sts = pci_mmio_read_config32(ubox_dev, UBOX_SC_RESET_STATUS); - - /* In case we are in bypass mode do nothing */ - if (reset_sts & UBOX_SC_BYPASS) - return; - - dfx1 = pci_mmio_read_config32(VTD_PCI_DEV, VTD_DFX1); - ubox_uart_en = pci_mmio_read_config32(ubox_dev, UBOX_UART_ENABLE); - - switch (port) { - case 0: - ubox_uart_en |= UBOX_UART_ENABLE_PORT0; - dfx1 |= VTD_DFX1_RANGE_3F8_DISABLE; - break; - case 1: - ubox_uart_en |= UBOX_UART_ENABLE_PORT1; - dfx1 |= VTD_DFX1_RANGE_2F8_DISABLE; - break; - default: - printk(BIOS_ERR, "incorrect port number\n"); - return; - } - - /* Disable decoding and enable the port we want */ - pci_mmio_write_config32(VTD_PCI_DEV, VTD_DFX1, dfx1); - pci_mmio_write_config32(ubox_dev, UBOX_UART_ENABLE, ubox_uart_en); -} - -static void early_iio_hide(void) -{ - DEVTREE_CONST struct device *dev; - - const pci_devfn_t iio_rootport[] = { - PCI_DEVFN(PCIE_IIO_PORT_1_DEV, PCIE_IIO_PORT_1A_FUNC), - PCI_DEVFN(PCIE_IIO_PORT_1_DEV, PCIE_IIO_PORT_1B_FUNC), - PCI_DEVFN(PCIE_IIO_PORT_2_DEV, PCIE_IIO_PORT_2A_FUNC), - PCI_DEVFN(PCIE_IIO_PORT_2_DEV, PCIE_IIO_PORT_2B_FUNC), - PCI_DEVFN(PCIE_IIO_PORT_2_DEV, PCIE_IIO_PORT_2C_FUNC), - PCI_DEVFN(PCIE_IIO_PORT_2_DEV, PCIE_IIO_PORT_2D_FUNC), - PCI_DEVFN(PCIE_IIO_PORT_3_DEV, PCIE_IIO_PORT_3A_FUNC), - PCI_DEVFN(PCIE_IIO_PORT_3_DEV, PCIE_IIO_PORT_3B_FUNC), - PCI_DEVFN(PCIE_IIO_PORT_3_DEV, PCIE_IIO_PORT_3C_FUNC), - PCI_DEVFN(PCIE_IIO_PORT_3_DEV, PCIE_IIO_PORT_3D_FUNC), - }; - - /* Walk through IIO root ports and hide if it is disabled in devtree */ - for (int i = 0; i < ARRAY_SIZE(iio_rootport); i++) { - dev = pcidev_path_on_bus(BUS0, iio_rootport[i]); - if (dev && !dev->enabled) { - printk(BIOS_DEBUG, "Hiding IIO root port: %d:%d.%d\n", - BUS0, - PCI_SLOT(iio_rootport[i]), - PCI_FUNC(iio_rootport[i])); - iio_hide(dev); - } - } - -} - -/* Entry from cache-as-ram.inc. */ -void *asmlinkage main(FSP_INFO_HEADER *fsp_info_header) -{ - post_code(0x40); - - timestamp_init(get_initial_timestamp()); - timestamp_add_now(TS_START_ROMSTAGE); - - if (!CONFIG(INTEGRATED_UART)) { - /* Enable decoding of I/O locations for Super I/O devices */ - pci_write_config16(PCI_DEV(0x0, LPC_DEV, LPC_FUNC), - LPC_IO_DEC, 0x0010); - pci_write_config16(PCI_DEV(0x0, LPC_DEV, LPC_FUNC), - LPC_EN, 0x340f); - } else { - enable_integrated_uart(CONFIG_UART_FOR_CONSOLE); - } - - /* Call into mainboard. */ - post_code(0x41); - early_mainboard_romstage_entry(); - - post_code(0x42); - console_init(); - init_rtc(); - setup_gpio_io_address(); - - /* Hide before MemoryInit since hiding later seems to break FSP */ - early_iio_hide(); - timestamp_add_now(TS_BEFORE_INITRAM); - post_code(0x48); - /* - * Call early init to initialize memory and chipset. This function returns - * to the romstage_main_continue function with a pointer to the HOB - * structure. - */ - printk(BIOS_DEBUG, "Starting the Intel FSP (early_init)\n"); - fsp_early_init(fsp_info_header); - die_with_post_code(POST_INVALID_VENDOR_BINARY, - "Uh Oh! fsp_early_init should not return here.\n"); -} - -/******************************************************************************* - * The FSP early_init function returns to this function. - * Memory is set up and the stack is set by the FSP. - */ -void romstage_main_continue(EFI_STATUS status, void *hob_list_ptr) -{ - void *cbmem_hob_ptr; - - post_code(0x4a); - timestamp_add_now(TS_AFTER_INITRAM); - printk(BIOS_DEBUG, "%s status: %x hob_list_ptr: %x\n", - __func__, (u32) status, (u32) hob_list_ptr); - - /* FSP reconfigures USB, so reinit it to have debug */ - if (CONFIG(USBDEBUG_IN_PRE_RAM)) - usbdebug_hw_init(true); - - printk(BIOS_DEBUG, "FSP Status: 0x%0x\n", (u32)status); - - post_code(0x4b); - late_mainboard_romstage_entry(); - - post_code(0x4d); - cbmem_recovery(0); - - /* Save the HOB pointer in CBMEM to be used in ramstage*/ - cbmem_hob_ptr = cbmem_add(CBMEM_ID_HOB_POINTER, sizeof(*hob_list_ptr)); - if (cbmem_hob_ptr == NULL) - die("Could not allocate cbmem for HOB pointer"); - *(u32 *)cbmem_hob_ptr = (u32)hob_list_ptr; - - if (!CONFIG(FSP_MEMORY_DOWN)) - save_dimm_info(); - - if (CONFIG(SMM_TSEG)) - smm_list_regions(); - - /* Load the ramstage. */ - post_code(0x4e); - run_ramstage(); - while (1); -} - -uint64_t get_initial_timestamp(void) -{ - return 0; -} diff --git a/src/soc/intel/fsp_broadwell_de/smbus-imc.c b/src/soc/intel/fsp_broadwell_de/smbus-imc.c deleted file mode 100644 index 61dc080c50..0000000000 --- a/src/soc/intel/fsp_broadwell_de/smbus-imc.c +++ /dev/null @@ -1,58 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2019 Facebook, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include -#include -#include -#include - -/* read word, return value on success */ -uint16_t smbus_read_word(u32 smbus_dev, u8 addr, u8 offset) -{ - uint16_t res = 0; - - if (imc_smbus_spd_xfer(IMC_DEV, addr, offset, IMC_DEVICE_EEPROM, IMC_DATA_WORD, - IMC_CONTROLLER_ID0, IMC_READ, &res) - == 0) { - return res; - } - return 0; -} - -/* read byte, return value on success */ -uint8_t smbus_read_byte(u32 smbus_dev, u8 addr, u8 offset) -{ - uint16_t res = 0; - - if (imc_smbus_spd_xfer(IMC_DEV, addr, offset, IMC_DEVICE_EEPROM, IMC_DATA_BYTE, - IMC_CONTROLLER_ID0, IMC_READ, &res) - == 0) { - return res; - } - return 0; -} - -/* write byte, return 0 on success, -1 otherwise */ -uint8_t smbus_write_byte(u32 smbus_dev, u8 addr, u8 offset, u8 value) -{ - if (imc_smbus_spd_xfer(IMC_DEV, addr, offset, IMC_DEVICE_WP_EEPROM, IMC_DATA_BYTE, - IMC_CONTROLLER_ID0, IMC_WRITE, &value) - == 0) { - return 0; - } - return -1; -} diff --git a/src/soc/intel/fsp_broadwell_de/smbus.c b/src/soc/intel/fsp_broadwell_de/smbus.c deleted file mode 100644 index 94474f713e..0000000000 --- a/src/soc/intel/fsp_broadwell_de/smbus.c +++ /dev/null @@ -1,96 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2008-2009 coresystems GmbH - * Copyright (C) 2014 Google Inc. - * Copyright (C) 2016 Siemens AG - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include - -static void pch_smbus_init(struct device *dev) -{ - struct resource *res; - - /* Set Receive Slave Address */ - res = find_resource(dev, PCI_BASE_ADDRESS_4); - if (res) - outb(SMBUS_SLAVE_ADDR, res->base + SMB_RCV_SLVA); -} - -static void pch_smbus_enable(struct device *dev) -{ - uint8_t reg8; - - reg8 = pci_read_config8(dev, HOSTC); - reg8 |= HST_EN; - pci_write_config8(dev, HOSTC, reg8); -} - -static int lsmbus_read_byte(struct device *dev, uint8_t address) -{ - uint16_t device; - struct resource *res; - struct bus *pbus; - - device = dev->path.i2c.device; - pbus = get_pbus_smbus(dev); - res = find_resource(pbus->dev, PCI_BASE_ADDRESS_4); - - return do_smbus_read_byte(res->base, device, address); -} - -static int lsmbus_write_byte(struct device *dev, uint8_t address, uint8_t data) -{ - uint16_t device; - struct resource *res; - struct bus *pbus; - - device = dev->path.i2c.device; - pbus = get_pbus_smbus(dev); - res = find_resource(pbus->dev, PCI_BASE_ADDRESS_4); - return do_smbus_write_byte(res->base, device, address, data); -} - -static struct smbus_bus_operations lops_smbus_bus = { - .read_byte = lsmbus_read_byte, - .write_byte = lsmbus_write_byte, -}; - -static struct device_operations smbus_ops = { - .read_resources = pci_dev_read_resources, - .set_resources = pci_dev_set_resources, - .enable_resources = pci_dev_enable_resources, - .scan_bus = scan_smbus, - .init = pch_smbus_init, - .enable = pch_smbus_enable, - .ops_smbus_bus = &lops_smbus_bus, -}; - -static const unsigned short pci_device_ids[] = { - SMBUS_DEVID, - 0 -}; - -static const struct pci_driver pch_smbus __pci_driver = { - .ops = &smbus_ops, - .vendor = PCI_VENDOR_ID_INTEL, - .devices = pci_device_ids, -}; diff --git a/src/soc/intel/fsp_broadwell_de/smbus_common.c b/src/soc/intel/fsp_broadwell_de/smbus_common.c deleted file mode 100644 index 0c5da4f4f4..0000000000 --- a/src/soc/intel/fsp_broadwell_de/smbus_common.c +++ /dev/null @@ -1,150 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2005 Yinghai Lu - * Copyright (C) 2008-2009 coresystems GmbH - * Copyright (C) 2014 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include -#include -#include -#include -#include -#include - -static void smbus_delay(void) -{ - inb(0x80); -} - -static int smbus_wait_until_ready(u16 smbus_base) -{ - unsigned int loops = SMBUS_TIMEOUT; - unsigned char byte; - do { - smbus_delay(); - if (--loops == 0) - break; - byte = inb(smbus_base + SMBHSTSTAT); - } while (byte & 1); - return loops ? 0 : -1; -} - -static int smbus_wait_until_done(u16 smbus_base) -{ - unsigned int loops = SMBUS_TIMEOUT; - unsigned char byte; - do { - smbus_delay(); - if (--loops == 0) - break; - byte = inb(smbus_base + SMBHSTSTAT); - } while ((byte & 1) || (byte & ~((1 << 6) | (1 << 0))) == 0); - return loops ? 0 : -1; -} - -int do_smbus_read_byte(unsigned int smbus_base, unsigned int device, unsigned int address) -{ - unsigned char global_status_register; - unsigned char byte; - - if (smbus_wait_until_ready(smbus_base) < 0) { - return SMBUS_WAIT_UNTIL_READY_TIMEOUT; - } - /* Setup transaction */ - /* Disable interrupts */ - outb(inb(smbus_base + SMBHSTCTL) & (~1), smbus_base + SMBHSTCTL); - /* Set the device I'm talking to */ - outb(((device & 0x7f) << 1) | 1, smbus_base + SMBXMITADD); - /* Set the command/address... */ - outb(address & 0xff, smbus_base + SMBHSTCMD); - /* Set up for a byte data read */ - outb((inb(smbus_base + SMBHSTCTL) & 0xe3) | (0x2 << 2), - (smbus_base + SMBHSTCTL)); - /* Clear any lingering errors, so the transaction will run */ - outb(inb(smbus_base + SMBHSTSTAT), smbus_base + SMBHSTSTAT); - - /* Clear the data byte... */ - outb(0, smbus_base + SMBHSTDAT0); - - /* Start the command */ - outb((inb(smbus_base + SMBHSTCTL) | 0x40), - smbus_base + SMBHSTCTL); - - /* Poll for transaction completion */ - if (smbus_wait_until_done(smbus_base) < 0) { - return SMBUS_WAIT_UNTIL_DONE_TIMEOUT; - } - - global_status_register = inb(smbus_base + SMBHSTSTAT); - - /* Ignore the "In Use" status... */ - global_status_register &= ~(3 << 5); - - /* Read results of transaction */ - byte = inb(smbus_base + SMBHSTDAT0); - if (global_status_register != (1 << 1)) { - return SMBUS_ERROR; - } - return byte; -} - -int do_smbus_write_byte(unsigned int smbus_base, unsigned int device, - unsigned int address, unsigned int data) -{ - unsigned char global_status_register; - - if (smbus_wait_until_ready(smbus_base) < 0) - return SMBUS_WAIT_UNTIL_READY_TIMEOUT; - - /* Setup transaction */ - /* Disable interrupts */ - outb(inb(smbus_base + SMBHSTCTL) & (~1), smbus_base + SMBHSTCTL); - /* Set the device I'm talking to */ - outb(((device & 0x7f) << 1) & ~0x01, smbus_base + SMBXMITADD); - /* Set the command/address... */ - outb(address & 0xff, smbus_base + SMBHSTCMD); - /* Set up for a byte data read */ - outb((inb(smbus_base + SMBHSTCTL) & 0xe3) | (0x2 << 2), - (smbus_base + SMBHSTCTL)); - /* Clear any lingering errors, so the transaction will run */ - outb(inb(smbus_base + SMBHSTSTAT), smbus_base + SMBHSTSTAT); - - /* Clear the data byte... */ - outb(data, smbus_base + SMBHSTDAT0); - - /* Start the command */ - outb((inb(smbus_base + SMBHSTCTL) | 0x40), - smbus_base + SMBHSTCTL); - - /* Poll for transaction completion */ - if (smbus_wait_until_done(smbus_base) < 0) { - printk(BIOS_ERR, "SMBUS transaction timeout\n"); - return SMBUS_WAIT_UNTIL_DONE_TIMEOUT; - } - - global_status_register = inb(smbus_base + SMBHSTSTAT); - - /* Ignore the "In Use" status... */ - global_status_register &= ~(3 << 5); - - /* Read results of transaction */ - if (global_status_register != (1 << 1)) { - printk(BIOS_ERR, "SMBUS transaction error\n"); - return SMBUS_ERROR; - } - - return 0; -} diff --git a/src/soc/intel/fsp_broadwell_de/smi.c b/src/soc/intel/fsp_broadwell_de/smi.c deleted file mode 100644 index 299ba531c5..0000000000 --- a/src/soc/intel/fsp_broadwell_de/smi.c +++ /dev/null @@ -1,90 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2008-2009 coresystems GmbH - * Copyright (C) 2014 Google Inc. - * Copyright (C) 2017 Siemens AG - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include -#include -#include -#include - -void smm_southbridge_clear_state(void) -{ - u32 smi_en; - - printk(BIOS_DEBUG, "Initializing Southbridge SMI..."); - printk(BIOS_SPEW, " ... pmbase = 0x%04x\n", ACPI_BASE_ADDRESS); - - smi_en = inl(ACPI_BASE_ADDRESS + SMI_EN); - if (smi_en & APMC_EN) { - printk(BIOS_INFO, "SMI# handler already enabled?\n"); - return; - } - - printk(BIOS_DEBUG, "\n"); - - /* Dump and clear status registers */ - clear_smi_status(); - clear_pm1_status(); -} - -static void southbridge_clear_smi_status(void); - -void smm_southbridge_enable_smi(void) -{ - printk(BIOS_DEBUG, "Enabling SMIs.\n"); - - /* Clear all possible set SMI status bits - before enabling SMIs. */ - southbridge_clear_smi_status(); - - /* Enable SMI generation: - - on SERIRQ-SMI (is always enabled) */ - enable_smi(EOS | GBL_SMI_EN); -} - -static void __unused southbridge_trigger_smi(void) -{ - /* - * There are several methods of raising a controlled SMI# via - * software, among them: - * - Writes to io 0xb2 (APMC) - * - Writes to the Local Apic ICR with Delivery mode SMI. - * - * Using the local apic is a bit more tricky. According to - * AMD Family 11 Processor BKDG no destination shorthand must be - * used. - * The whole SMM initialization is quite a bit hardware specific, so - * I'm not too worried about the better of the methods at the moment - */ - - /* Raise an SMI interrupt */ - printk(BIOS_SPEW, " ... raise SMI#\n"); - outb(0x00, 0xb2); -} - -static void southbridge_clear_smi_status(void) -{ - /* Clear SMI status */ - clear_smi_status(); - - /* Clear PM1 status */ - clear_pm1_status(); - - /* Set EOS bit so other SMIs can occur. */ - enable_smi(EOS); -} diff --git a/src/soc/intel/fsp_broadwell_de/smihandler.c b/src/soc/intel/fsp_broadwell_de/smihandler.c deleted file mode 100644 index bb1bbf8409..0000000000 --- a/src/soc/intel/fsp_broadwell_de/smihandler.c +++ /dev/null @@ -1,106 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2008-2009 coresystems GmbH - * Copyright (C) 2014 Google Inc. - * Copyright (C) 2017 Siemens AG - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -/** - * @brief Set the EOS bit - */ -void southbridge_smi_set_eos(void) -{ - enable_smi(EOS); -} - -static void southbridge_smi_serirq(void) -{ - -} - -typedef void (*smi_handler_t)(void); - -static smi_handler_t southbridge_smi[32] = { - NULL, // [0] reserved - NULL, // [1] reserved - NULL, // [2] BIOS_STS - NULL, // [3] LEGACY_USB_STS - NULL, // [4] SLP_SMI_STS - NULL, // [5] APM_STS - NULL, // [6] SWSMI_TMR_STS - NULL, // [7] reserved - NULL, // [8] PM1_STS - NULL, // [9] GPE0_STS - NULL, // [10] GPI_STS - NULL, // [11] MCSMI_STS - NULL, // [12] DEVMON_STS - NULL, // [13] TCO_STS - NULL, // [14] PERIODIC_STS - southbridge_smi_serirq, // [15] SERIRQ_SMI_STS - NULL, // [16] SMBUS_SMI_STS - NULL, // [17] LEGACY_USB2_STS - NULL, // [18] INTEL_USB2_STS - NULL, // [19] reserved - NULL, // [20] PCI_EXP_SMI_STS - NULL, // [21] MONITOR_STS - NULL, // [22] reserved - NULL, // [23] reserved - NULL, // [24] reserved - NULL, // [25] EL_SMI_STS - NULL, // [26] SPI_STS - NULL, // [27] reserved - NULL, // [28] reserved - NULL, // [29] reserved - NULL, // [30] reserved - NULL // [31] reserved -}; - -/** - * @brief Interrupt handler for SMI# - * - * @param smm_revision revision of the smm state save map - */ - -void southbridge_smi_handler(void) -{ - int i; - u32 smi_sts; - - /* We need to clear the SMI status registers, or we won't see what's - happening in the following calls. */ - smi_sts = clear_smi_status(); - - /* Call SMI sub handler for each of the status bits */ - for (i = 0; i < 31; i++) { - if (smi_sts & (1 << i)) { - if (southbridge_smi[i]) { - southbridge_smi[i](); - } else { - printk(BIOS_DEBUG, - "SMI_STS[%d] occurred, but no " - "handler available.\n", i); - } - } - } -} diff --git a/src/soc/intel/fsp_broadwell_de/smmrelocate.c b/src/soc/intel/fsp_broadwell_de/smmrelocate.c deleted file mode 100644 index efd42e9607..0000000000 --- a/src/soc/intel/fsp_broadwell_de/smmrelocate.c +++ /dev/null @@ -1,306 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2014 Google Inc. - * Copyright (C) 2017 Siemens AG - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#define __SIMPLE_DEVICE__ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -/* This gets filled in and used during relocation. */ -static struct smm_relocation_params smm_reloc_params; - -static inline void write_smrr(struct smm_relocation_params *relo_params) -{ - printk(BIOS_DEBUG, "Writing SMRR. base = 0x%08x, mask=0x%08x\n", - relo_params->smrr_base.lo, relo_params->smrr_mask.lo); - wrmsr(IA32_SMRR_PHYS_BASE, relo_params->smrr_base); - wrmsr(IA32_SMRR_PHYS_MASK, relo_params->smrr_mask); -} - -static inline void write_prmrr(struct smm_relocation_params *relo_params) -{ - printk(BIOS_DEBUG, "Writing PRMRR. base = 0x%08x, mask=0x%08x\n", - relo_params->prmrr_base.lo, relo_params->prmrr_mask.lo); - wrmsr(MSR_PRMRR_PHYS_BASE, relo_params->prmrr_base); - wrmsr(MSR_PRMRR_PHYS_MASK, relo_params->prmrr_mask); -} - -static void update_save_state(int cpu, uintptr_t curr_smbase, - uintptr_t staggered_smbase, - struct smm_relocation_params *relo_params) -{ - u32 smbase; - u32 iedbase; - - /* The relocated handler runs with all CPUs concurrently. Therefore - stagger the entry points adjusting SMBASE downwards by save state - size * CPU num. */ - smbase = staggered_smbase; - iedbase = relo_params->ied_base; - - printk(BIOS_DEBUG, "New SMBASE=0x%08x IEDBASE=0x%08x\n", - smbase, iedbase); - - /* - * All threads need to set IEDBASE and SMBASE to the relocated - * handler region. However, the save state location depends on the - * smm_save_state_in_msrs field in the relocation parameters. If - * smm_save_state_in_msrs is non-zero then the CPUs are relocating - * the SMM handler in parallel, and each CPUs save state area is - * located in their respective MSR space. If smm_save_state_in_msrs - * is zero then the SMM relocation is happening serially so the - * save state is at the same default location for all CPUs. - */ - if (relo_params->smm_save_state_in_msrs) { - msr_t smbase_msr; - msr_t iedbase_msr; - - smbase_msr.lo = smbase; - smbase_msr.hi = 0; - - /* According the BWG the IEDBASE MSR is in bits 63:32. It's - not clear why it differs from the SMBASE MSR. */ - iedbase_msr.lo = 0; - iedbase_msr.hi = iedbase; - - wrmsr(SMBASE_MSR, smbase_msr); - wrmsr(IEDBASE_MSR, iedbase_msr); - } else { - em64t101_smm_state_save_area_t *save_state; - - save_state = (void *)(curr_smbase + SMM_DEFAULT_SIZE - - sizeof(*save_state)); - save_state->smbase = smbase; - save_state->iedbase = iedbase; - } -} - -/* Returns 1 if SMM MSR save state was set. */ -static int bsp_setup_msr_save_state(struct smm_relocation_params *relo_params) -{ - msr_t smm_mca_cap; - - smm_mca_cap = rdmsr(SMM_MCA_CAP_MSR); - if (smm_mca_cap.hi & SMM_CPU_SVRSTR_MASK) { - uint32_t smm_feature_control; - pci_devfn_t dev = PCI_DEV(QPI_BUS, SMM_DEV, SMM_FUNC); - - /* - * SMM_FEATURE_CONTROL on Broadwell-DE is not located in - * MSR range but in PCI config space. The used PCI device is - * located on bus 0xff, which has no root bridge and hence is - * not scanned by PCI scan. Use MMIO config access to read the - * needed 32 bit register. - */ - smm_feature_control = pci_read_config32(dev, - SMM_FEATURE_CONTROL); - smm_feature_control |= SMM_CPU_SAVE_EN; - pci_write_config32(dev, - SMM_FEATURE_CONTROL, smm_feature_control); - relo_params->smm_save_state_in_msrs = 1; - } - return relo_params->smm_save_state_in_msrs; -} - -/* - * The relocation work is actually performed in SMM context, but the code - * resides in the ramstage module. This occurs by trampolining from the default - * SMRAM entry point to here. - */ -void smm_relocation_handler(int cpu, uintptr_t curr_smbase, - uintptr_t staggered_smbase) -{ - msr_t mtrr_cap; - struct smm_relocation_params *relo_params = &smm_reloc_params; - - printk(BIOS_DEBUG, "In relocation handler: CPU %d\n", cpu); - - /* Determine if the processor supports saving state in MSRs. If so, - enable it before the non-BSPs run so that SMM relocation can occur - in parallel in the non-BSP CPUs. */ - if (cpu == 0) { - /* - * If smm_save_state_in_msrs is 1 then that means this is the - * 2nd time through the relocation handler for the BSP. - * Parallel SMM handler relocation is taking place. However, - * it is desired to access other CPUs save state in the real - * SMM handler. Therefore, disable the SMM save state in MSRs - * feature. - */ - if (relo_params->smm_save_state_in_msrs) { - uint32_t smm_feature_control; - pci_devfn_t dev = PCI_DEV(QPI_BUS, SMM_DEV, SMM_FUNC); - - /* - * SMM_FEATURE_CONTROL on Broadwell-DE is not located in - * MSR range but in PCI config space. The used PCI - * device is located on bus 0xff, which has no root - * bridge and hence is not scanned by PCI scan. - * Use MMIO config access to read the needed 32 bit - * register. - */ - smm_feature_control = pci_read_config32(dev, - SMM_FEATURE_CONTROL); - smm_feature_control &= ~SMM_CPU_SAVE_EN; - pci_write_config32(dev, SMM_FEATURE_CONTROL, - smm_feature_control); - } else if (bsp_setup_msr_save_state(relo_params)) - /* - * Just return from relocation handler if MSR save - * state is enabled. In that case the BSP will come - * back into the relocation handler to setup the new - * SMBASE as well disabling SMM save state in MSRs. - */ - return; - } - - /* Make appropriate changes to the save state map. */ - update_save_state(cpu, curr_smbase, staggered_smbase, relo_params); - /* Write PRMRR and SMRR MSRs based on indicated support. */ - mtrr_cap = rdmsr(MTRR_CAP_MSR); - if (mtrr_cap.lo & SMRR_SUPPORTED) - write_smrr(relo_params); - - if (mtrr_cap.lo & PRMRR_SUPPORTED) - write_prmrr(relo_params); -} - -static void fill_in_relocation_params(struct smm_relocation_params *params) -{ - uintptr_t tseg_base; - size_t tseg_size; - u32 prmrr_base; - u32 prmrr_size; - int phys_bits; - /* All range registers are aligned to 4KiB */ - const u32 rmask = ~((1 << 12) - 1); - - /* Some of the range registers are dependent on the number of physical - address bits supported. */ - phys_bits = cpuid_eax(0x80000008) & 0xff; - /* - * The range bounded by the TSEG_BASE and TSEG_LIMIT registers - * encompasses the SMRAM range as well as the IED range. - * However, the SMRAM available to the handler is 4MiB since the IEDRAM - * lives TSEG_BASE + 4MiB. - * - * Note that address bits 19:0 are ignored and not compared. - * The result is that BASE[19:0] is effectively 00000h and LIMIT is - * effectively FFFFFh. - */ - - smm_region(&tseg_base, &tseg_size); - - /* SMRR has 32-bits of valid address aligned to 4KiB. */ - params->smrr_base.lo = (tseg_base & rmask) | MTRR_TYPE_WRBACK; - params->smrr_base.hi = 0; - params->smrr_mask.lo = (~(tseg_size - 1) & rmask) | MTRR_PHYS_MASK_VALID; - params->smrr_mask.hi = 0; - - smm_subregion(SMM_SUBREGION_CHIPSET, ¶ms->ied_base, ¶ms->ied_size); - - /* The PRMRR is at IEDBASE + 2MiB */ - prmrr_base = (params->ied_base + (2 << 20)) & rmask; - prmrr_size = params->ied_size - (2 << 20); - - /* PRMRR has 46 bits of valid address aligned to 4KiB. It's dependent - on the number of physical address bits supported. */ - params->prmrr_base.lo = prmrr_base | MTRR_TYPE_WRBACK; - params->prmrr_base.hi = 0; - params->prmrr_mask.lo = (~(prmrr_size - 1) & rmask) - | MTRR_PHYS_MASK_VALID; - params->prmrr_mask.hi = (1 << (phys_bits - 32)) - 1; -} - -static void setup_ied_area(struct smm_relocation_params *params) -{ - char *ied_base; - - struct ied_header ied = { - .signature = "INTEL RSVD", - .size = params->ied_size, - .reserved = {0}, - }; - - ied_base = (void *)params->ied_base; - - /* Place IED header at IEDBASE. */ - memcpy(ied_base, &ied, sizeof(ied)); - - /* Zero out 32KiB at IEDBASE + 1MiB */ - memset(ied_base + (1 << 20), 0, (32 << 10)); -} - -void smm_info(uintptr_t *perm_smbase, size_t *perm_smsize, - size_t *smm_save_state_size) -{ - printk(BIOS_DEBUG, "Setting up SMI for CPU\n"); - - fill_in_relocation_params(&smm_reloc_params); - - smm_subregion(SMM_SUBREGION_HANDLER, perm_smbase, perm_smsize); - - setup_ied_area(&smm_reloc_params); - - *smm_save_state_size = sizeof(em64t101_smm_state_save_area_t); -} - -void smm_initialize(void) -{ - /* Clear the SMM state in the southbridge. */ - smm_southbridge_clear_state(); - - /* Run the relocation handler for on the BSP to check and set up - parallel SMM relocation. */ - smm_initiate_relocation(); - - if (smm_reloc_params.smm_save_state_in_msrs) - printk(BIOS_DEBUG, "Doing parallel SMM relocation.\n"); -} - -/* - * The default SMM entry can happen in parallel or serially. If the - * default SMM entry is done in parallel the BSP has already setup - * the saving state to each CPU's MSRs. At least one save state size - * is required for the initial SMM entry for the BSP to determine if - * parallel SMM relocation is even feasible. - */ -void smm_relocate(void) -{ - /* - * If smm_save_state_in_msrs is non-zero then parallel SMM relocation - * shall take place. Run the relocation handler a second time on the - * BSP to do the final move. For APs, a relocation handler always - * needs to be run. - */ - if (smm_reloc_params.smm_save_state_in_msrs) - smm_initiate_relocation_parallel(); - else if (!boot_cpu()) - smm_initiate_relocation(); -} diff --git a/src/soc/intel/fsp_broadwell_de/southcluster.c b/src/soc/intel/fsp_broadwell_de/southcluster.c deleted file mode 100644 index fb8af87b62..0000000000 --- a/src/soc/intel/fsp_broadwell_de/southcluster.c +++ /dev/null @@ -1,301 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2008-2009 coresystems GmbH - * Copyright (C) 2013 Google Inc. - * Copyright (C) 2015-2016 Intel Corp. - * Copyright (C) 2017 Siemens AG - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include "chip.h" - -typedef struct soc_intel_fsp_broadwell_de_config config_t; - -static inline void -add_mmio_resource(struct device *dev, int i, unsigned long addr, - unsigned long size) -{ - mmio_resource(dev, i, addr >> 10, size >> 10); -} - -static void sc_add_mmio_resources(struct device *dev) -{ - add_mmio_resource(dev, 0xfeb0, - ABORT_BASE_ADDRESS, - ABORT_BASE_SIZE); - add_mmio_resource(dev, 0xfeb8, - PSEG_BASE_ADDRESS, - PSEG_BASE_SIZE); - add_mmio_resource(dev, 0xfec0, - IOXAPIC1_BASE_ADDRESS, - IOXAPIC1_BASE_SIZE); - add_mmio_resource(dev, 0xfec1, - IOXAPIC2_BASE_ADDRESS, - IOXAPIC2_BASE_SIZE); - add_mmio_resource(dev, 0xfed0, - PCH_BASE_ADDRESS, - PCH_BASE_SIZE); - add_mmio_resource(dev, 0xfee0, - LXAPIC_BASE_ADDRESS, - LXAPIC_BASE_SIZE); - add_mmio_resource(dev, 0xff00, - FIRMWARE_BASE_ADDRESS, - FIRMWARE_BASE_SIZE); -} - -/* - * Write PCI config space IRQ assignments. PCI devices have the INT_LINE - * (0x3C) and INT_PIN (0x3D) registers which report interrupt routing - * information to operating systems and drivers. The INT_PIN register is - * generally read only and reports which interrupt pin A - D it uses. The - * INT_LINE register is configurable and reports which IRQ (generally the - * PIC IRQs 1 - 15) it will use. This needs to take interrupt pin swizzling - * on devices that are downstream on a PCI bridge into account. - * - * This function will loop through all enabled PCI devices and program the - * INT_LINE register with the correct PIC IRQ number for the INT_PIN that it - * uses. It then configures each interrupt in the pic to be level triggered. - */ -static void write_pci_config_irqs(void) -{ - struct device *irq_dev; - struct device *targ_dev; - uint8_t int_line = 0; - uint8_t original_int_pin = 0; - uint8_t new_int_pin = 0; - uint16_t current_bdf = 0; - uint16_t parent_bdf = 0; - uint8_t pirq = 0; - uint8_t device_num = 0; - const struct broadwell_de_irq_route *ir = &global_broadwell_de_irq_route; - - if (ir == NULL) { - printk(BIOS_WARNING, "Warning: Can't write PCI IRQ assignments because" - " 'global_broadwell_de_irq_route' structure does not exist\n"); - return; - } - - /* - * Loop through all enabled devices and program their - * INT_LINE, INT_PIN registers from values taken from - * the Interrupt Route registers in the ILB - */ - printk(BIOS_DEBUG, "PCI_CFG IRQ: Write PCI config space IRQ assignments\n"); - for (irq_dev = all_devices; irq_dev; irq_dev = irq_dev->next) { - - if ((irq_dev->path.type != DEVICE_PATH_PCI) || - (!irq_dev->enabled)) - continue; - - current_bdf = irq_dev->path.pci.devfn | - irq_dev->bus->secondary << 8; - - /* - * Step 1: Get the INT_PIN and device structure to look for - * in the pirq_data table defined in the mainboard directory. - */ - targ_dev = NULL; - new_int_pin = get_pci_irq_pins(irq_dev, &targ_dev); - if (targ_dev == NULL || new_int_pin < 1) - continue; - - /* Get the original INT_PIN for record keeping */ - original_int_pin = pci_read_config8(irq_dev, PCI_INTERRUPT_PIN); - - parent_bdf = targ_dev->path.pci.devfn - | targ_dev->bus->secondary << 8; - device_num = PCI_SLOT(parent_bdf); - - if (ir->pcidev[device_num] == 0) { - printk(BIOS_WARNING, - "Warning: PCI Device %d does not have an IRQ entry, skipping it\n", - device_num); - continue; - } - - /* Find the PIRQ that is attached to the INT_PIN this device uses */ - pirq = (ir->pcidev[device_num] >> ((new_int_pin - 1) * 4)) & 0xF; - - /* Get the INT_LINE this device/function will use */ - int_line = ir->pic[pirq]; - - if (int_line != PIRQ_PIC_IRQDISABLE) { - /* Set this IRQ to level triggered since it is used by a PCI device */ - i8259_configure_irq_trigger(int_line, IRQ_LEVEL_TRIGGERED); - /* Set the Interrupt Line register in PCI config space */ - pci_write_config8(irq_dev, PCI_INTERRUPT_LINE, int_line); - } else { - /* Set the Interrupt line register as "unknown or unused" */ - pci_write_config8(irq_dev, PCI_INTERRUPT_LINE, - PIRQ_PIC_UNKNOWN_UNUSED); - } - - printk(BIOS_SPEW, "\tINT_PIN\t\t: %d (%s)\n", - original_int_pin, pin_to_str(original_int_pin)); - if (parent_bdf != current_bdf) - printk(BIOS_SPEW, "\tSwizzled to\t: %d (%s)\n", - new_int_pin, pin_to_str(new_int_pin)); - printk(BIOS_SPEW, "\tPIRQ\t\t: %c\n" - "\tINT_LINE\t: 0x%X (IRQ %d)\n", - 'A' + pirq, int_line, int_line); - } - printk(BIOS_DEBUG, "PCI_CFG IRQ: Finished writing PCI config space IRQ assignments\n"); -} - -static void sc_pirq_init(struct device *dev) -{ - int i; - const uint8_t *pirq = global_broadwell_de_irq_route.pic; - printk(BIOS_DEBUG, "Programming PIRQ[A-H] Routing Control Register\n"); - - for (i = 0; i < 8; i++) { - pci_write_config8(dev, (i < 4) ? (PIRQ_RCR1+i) : (PIRQ_RCR2+i-4), pirq[i]); - printk(BIOS_DEBUG, " PIRQ[%c]: %.2x\n" - , 'A'+i - , pci_read_config8(dev, (i < 4) ? (PIRQ_RCR1+i) : (PIRQ_RCR2+i-4)) - ); - } -} - -static void sc_add_io_resources(struct device *dev) -{ - struct resource *res; - u8 io_index = 0; - - /* - * Add the default claimed IO range for the LPC device - * and mark it as subtractive decode. - */ - res = new_resource(dev, IOINDEX_SUBTRACTIVE(io_index++, 0)); - res->base = LPC_DEFAULT_IO_RANGE_LOWER; - res->size = LPC_DEFAULT_IO_RANGE_UPPER - LPC_DEFAULT_IO_RANGE_LOWER; - res->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE | - IORESOURCE_ASSIGNED | IORESOURCE_FIXED; - - /* Add the resource for GPIOs */ - res = new_resource(dev, GPIO_BASE_ADR_OFFSET); - res->base = GPIO_BASE_ADDRESS; - res->size = GPIO_BASE_SIZE; - res->flags = IORESOURCE_IO | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; - /* There is a separated enable-bit in GPIO_CTRL-register. It was set - * already in romstage but FSP was active in the meantime and could have - * cleared it. Set it here again to enable allocated IO-space for sure. - */ - pci_write_config8(dev, GPIO_CTRL_OFFSET, GPIO_DECODE_ENABLE); -} - -static void sc_read_resources(struct device *dev) -{ - pci_dev_read_resources(dev); - sc_add_mmio_resources(dev); - sc_add_io_resources(dev); -} - -static void sc_init(struct device *dev) -{ - printk(BIOS_DEBUG, "soc: southcluster_init\n"); - - /* Set the value for PCI command register. */ - pci_write_config16(dev, PCI_COMMAND, - PCI_COMMAND_IO | PCI_COMMAND_MEMORY | - PCI_COMMAND_MASTER | PCI_COMMAND_SPECIAL); - - /* Program Serial IRQ register. */ - pci_write_config8(dev, SIRQ_CNTL, SIRQ_EN | SIRQ_MODE_CONT); - if (!CONFIG(SERIRQ_CONTINUOUS_MODE)) { - /* If SERIRQ have to operate in quiet mode, it should have been - run in continuous mode for at least one frame first. Use I/O - access to achieve the delay of at least one LPC cycle. */ - outb(inb(0x80), 0x80); - pci_write_config8(dev, SIRQ_CNTL, SIRQ_EN | SIRQ_MODE_QUIET); - } - - sc_pirq_init(dev); - write_pci_config_irqs(); - isa_dma_init(); - setup_i8259(); - setup_i8254(); -} - -/* - * Common code for the south cluster devices. - */ -void southcluster_enable_dev(struct device *dev) -{ - uint32_t reg32; - - if (dev->enabled) - return; - - const int slot = PCI_SLOT(dev->path.pci.devfn); - const int func = PCI_FUNC(dev->path.pci.devfn); - - printk(BIOS_DEBUG, "%s: Disabling device: %02x.%01x\n", dev_path(dev), slot, func); - /* Ensure memory, io, and bus master are all disabled */ - reg32 = pci_read_config32(dev, PCI_COMMAND); - reg32 &= ~(PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY | PCI_COMMAND_IO); - pci_write_config32(dev, PCI_COMMAND, reg32); -} - -#if CONFIG(HAVE_ACPI_TABLES) -static const char *lpc_acpi_name(const struct device *dev) -{ - if (dev->path.pci.devfn == PCH_DEVFN_LPC) - return "LPC0"; - else - return NULL; -} -#endif - -static struct device_operations device_ops = { - .read_resources = sc_read_resources, - .set_resources = pci_dev_set_resources, - .enable_resources = NULL, - .write_acpi_tables = southcluster_write_acpi_tables, - .init = sc_init, - .enable = southcluster_enable_dev, - .scan_bus = scan_static_bus, - .ops_pci = &soc_pci_ops, -#if CONFIG(HAVE_ACPI_TABLES) - .acpi_name = lpc_acpi_name, -#endif -}; - -static const struct pci_driver southcluster __pci_driver = { - .ops = &device_ops, - .vendor = PCI_VENDOR_ID_INTEL, - .device = LPC_DEVID, -}; - -static const struct pci_driver southcluster_es2 __pci_driver = { - .ops = &device_ops, - .vendor = PCI_VENDOR_ID_INTEL, - .device = LPC_DEVID_ES2, -}; diff --git a/src/soc/intel/fsp_broadwell_de/tsc_freq.c b/src/soc/intel/fsp_broadwell_de/tsc_freq.c deleted file mode 100644 index 4225a3ab22..0000000000 --- a/src/soc/intel/fsp_broadwell_de/tsc_freq.c +++ /dev/null @@ -1,28 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2014 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include -#include -#include - -unsigned long tsc_freq_mhz(void) -{ - msr_t platform_info; - - platform_info = rdmsr(MSR_PLATFORM_INFO); - return CPU_BCLK * ((platform_info.lo >> 8) & 0xff); -} diff --git a/src/soc/intel/fsp_broadwell_de/ubox.c b/src/soc/intel/fsp_broadwell_de/ubox.c deleted file mode 100644 index e3e55e0624..0000000000 --- a/src/soc/intel/fsp_broadwell_de/ubox.c +++ /dev/null @@ -1,30 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2019 Facebook Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#define __SIMPLE_DEVICE__ - -#include -#include - -void iio_hide(DEVTREE_CONST struct device *dev) -{ - pci_devfn_t ubox_dev; - uint8_t slot, func; - - slot = PCI_SLOT(dev->path.pci.devfn); - func = PCI_FUNC(dev->path.pci.devfn); - ubox_dev = PCI_DEV(get_busno1(), UBOX_DEV, UBOX_FUNC); - pci_or_config32(ubox_dev, UBOX_DEVHIDE0 + func * 4, 1 << slot); -} diff --git a/src/soc/intel/fsp_broadwell_de/vtd.c b/src/soc/intel/fsp_broadwell_de/vtd.c deleted file mode 100644 index 9e03e9ba6a..0000000000 --- a/src/soc/intel/fsp_broadwell_de/vtd.c +++ /dev/null @@ -1,59 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2018 Siemens AG - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include -#include -#include -#include -#include - -#if ENV_RAMSTAGE - -static void vtd_read_resources(struct device *dev) -{ - uint32_t vtbar; - - /* Add fixed MMIO resource for VT-d which was set up by the FSP. */ - vtbar = pci_read_config32(dev, VTBAR_OFFSET); - if (vtbar & VTBAR_ENABLED) { - mmio_resource(dev, VTBAR_OFFSET, - (vtbar & VTBAR_MASK) / KiB, VTBAR_SIZE / KiB); - } -} - -static struct device_operations vtd_ops = { - .read_resources = vtd_read_resources, - .set_resources = DEVICE_NOOP, - .write_acpi_tables = vtd_write_acpi_tables, -}; - -static const struct pci_driver vtd_driver __pci_driver = { - .ops = &vtd_ops, - .vendor = PCI_VENDOR_ID_INTEL, - .device = VTD_DEVID, -}; - -#endif - -uint8_t get_busno1(void) -{ - uint32_t reg32; - - /* Figure out what bus number is assigned for CPUBUSNO(1) */ - reg32 = pci_mmio_read_config32(VTD_PCI_DEV, VTD_CPUBUSNO); - return ((reg32 >> VTD_CPUBUSNO_BUS1_SHIFT) & VTD_CPUBUSNO_BUS1_MASK); -} From 15c012181d073ff68ee8fb5635ed9bde2b4fe23d Mon Sep 17 00:00:00 2001 From: Arthur Heymans Date: Tue, 19 Nov 2019 18:54:35 +0100 Subject: [PATCH 0310/1242] drivers/intel/fsp1_0: Drop support MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit No platform is using this. Change-Id: I3ea6df4d9ce9043755f319f699adc189d754df1f Signed-off-by: Arthur Heymans Reviewed-on: https://review.coreboot.org/c/coreboot/+/36985 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki Reviewed-by: David Hendricks Reviewed-by: Werner Zeh --- src/arch/x86/include/arch/early_variables.h | 7 - src/cpu/x86/car.c | 44 +-- src/drivers/intel/fsp1_0/Kconfig | 136 -------- src/drivers/intel/fsp1_0/Makefile.inc | 56 ---- src/drivers/intel/fsp1_0/cache_as_ram.inc | 119 ------- src/drivers/intel/fsp1_0/fastboot_cache.c | 248 -------------- src/drivers/intel/fsp1_0/fsp_util.c | 352 -------------------- src/drivers/intel/fsp1_0/fsp_util.h | 123 ------- src/drivers/intel/fsp1_0/fsp_values.h | 35 -- src/drivers/intel/fsp1_0/hob.c | 261 --------------- src/security/memory/memory_clear.c | 6 - 11 files changed, 1 insertion(+), 1386 deletions(-) delete mode 100644 src/drivers/intel/fsp1_0/Kconfig delete mode 100644 src/drivers/intel/fsp1_0/Makefile.inc delete mode 100644 src/drivers/intel/fsp1_0/cache_as_ram.inc delete mode 100644 src/drivers/intel/fsp1_0/fastboot_cache.c delete mode 100644 src/drivers/intel/fsp1_0/fsp_util.c delete mode 100644 src/drivers/intel/fsp1_0/fsp_util.h delete mode 100644 src/drivers/intel/fsp1_0/fsp_values.h delete mode 100644 src/drivers/intel/fsp1_0/hob.c diff --git a/src/arch/x86/include/arch/early_variables.h b/src/arch/x86/include/arch/early_variables.h index b88495c85b..7393cc94e0 100644 --- a/src/arch/x86/include/arch/early_variables.h +++ b/src/arch/x86/include/arch/early_variables.h @@ -49,15 +49,8 @@ int car_active(void); #define car_set_var(var, val) car_get_var(var) = (val) /* Get and set a CAR_GLOBAL pointing elsewhere inside CAR. */ -#if !CONFIG(PLATFORM_USES_FSP1_0) #define car_get_ptr car_get_var #define car_set_ptr car_set_var -#else -void *car_get_reloc_ptr(void *var); -void car_set_reloc_ptr(void *var, void *val); -#define car_get_ptr(var) car_get_reloc_ptr(&(var)) -#define car_set_ptr(var, val) car_set_reloc_ptr(&(var), (val)) -#endif static inline size_t car_data_size(void) { diff --git a/src/cpu/x86/car.c b/src/cpu/x86/car.c index d8767ae52e..b2dcdc85a3 100644 --- a/src/cpu/x86/car.c +++ b/src/cpu/x86/car.c @@ -18,9 +18,6 @@ #include #include -#if CONFIG(PLATFORM_USES_FSP1_0) -#include -#endif typedef void (* const car_migration_func_t)(void); extern car_migration_func_t _car_migrate_start; @@ -59,15 +56,8 @@ void *car_get_var_ptr(void *var) return var; } -#if CONFIG(PLATFORM_USES_FSP1_0) - migrated_base = (char *)find_saved_temp_mem( - *(void **)CBMEM_FSP_HOB_PTR); - /* FSP 1.0 migrates the entire DCACHE RAM */ - offset = (char *)var - (char *)CONFIG_DCACHE_RAM_BASE; -#else migrated_base = cbmem_find(CBMEM_ID_CAR_GLOBALS); offset = (char *)var - (char *)_car_start; -#endif if (migrated_base == NULL) die("CAR: Could not find migration base!\n"); @@ -75,37 +65,6 @@ void *car_get_var_ptr(void *var) return &migrated_base[offset]; } -#if CONFIG(PLATFORM_USES_FSP1_0) -/* - * When a CAR_GLOBAL points to target object inside CAR, use relative - * addressing. Such CAR_GLOBAL has to be expicitly accessed using - * car_set_reloc_ptr() and car_get_reloc_ptr() as the stored value is now - * an offset instead of the absolute address (pointer) of the target. - * - * This way discovery of objects that are not CAR_GLOBALs themselves, - * remain discoverable after CAR migration has implicitly happened. - */ -void car_set_reloc_ptr(void *var, void *val) -{ - uintptr_t *offset = car_get_var_ptr(var); - *offset = 0; - - if (val) - *offset = (uintptr_t)offset - (uintptr_t)val; -} - -void *car_get_reloc_ptr(void *var) -{ - uintptr_t *offset = car_get_var_ptr(var); - void *val = NULL; - - if (*offset) - val = (void *)((uintptr_t)offset - *offset); - - return val; -} -#endif - int car_active(void) { return !car_migrated; @@ -135,7 +94,6 @@ static void do_car_migrate_variables(void) static void car_migrate_variables(int is_recovery) { - if (!CONFIG(PLATFORM_USES_FSP1_0)) - do_car_migrate_variables(); + do_car_migrate_variables(); } ROMSTAGE_CBMEM_INIT_HOOK(car_migrate_variables) diff --git a/src/drivers/intel/fsp1_0/Kconfig b/src/drivers/intel/fsp1_0/Kconfig deleted file mode 100644 index 1a1d4f7072..0000000000 --- a/src/drivers/intel/fsp1_0/Kconfig +++ /dev/null @@ -1,136 +0,0 @@ -## -## This file is part of the coreboot project. -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; version 2 of the License. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## - -config PLATFORM_USES_FSP1_0 - bool - default n - select CAR_GLOBAL_MIGRATION - select NO_FMAP_CACHE # doesn't work with CAR_GLOBAL restrictions - help - Selected for Intel processors/platform combinations that use the - Intel Firmware Support Package (FSP) 1.0 for initialization. - -if PLATFORM_USES_FSP1_0 - -comment "Intel FSP" - -config HAVE_FSP_BIN - bool "Use Intel Firmware Support Package" - help - Select this option to add an Intel FSP binary to - the resulting coreboot image. - - Note: Without this binary, coreboot builds relying on the FSP - will not boot - -config DCACHE_RAM_BASE - hex - default 0xfef00000 - -config DCACHE_RAM_SIZE - hex - default 0x4000 - -config FSP_HEADER_PATH - string "Location of FSP headers" - help - The path to headers files that are released with the FSP binary. - -config FSP_SRC_PATH - string "Additional FSP source file" - help - Additional source files that are released with the FSP binary. - -if HAVE_FSP_BIN - -config FSP_FILE - string "Intel FSP binary path and filename" - help - The path and filename of the Intel FSP binary for this platform. - -endif #HAVE_FSP_BIN - -config FSP_LOC - hex "Intel FSP Binary location in CBFS" - help - The location in CBFS that the FSP is located. This must match the - value that is set in the FSP binary. If the FSP needs to be moved, - rebase the FSP with Intel's BCT (tool). - -config ENABLE_FSP_FAST_BOOT - bool "Enable Fast Boot" - select ENABLE_MRC_CACHE - default n - help - Enabling this feature will force the MRC data to be cached in NV - storage to be used for speeding up boot time on future reboots - and/or power cycles. - -config ENABLE_MRC_CACHE - bool - default y if HAVE_ACPI_RESUME - default n - help - Enabling this feature will cause MRC data to be cached in NV storage. - This can either be used for fast boot, or just because the FSP wants - it to be saved. - -config MRC_CACHE_FMAP - bool "Use MRC Cache in FMAP" - depends on ENABLE_MRC_CACHE - select CACHE_MRC_SETTINGS - default n - help - Use the region "RW_MRC_CACHE" in FMAP instead of "mrc.cache" in CBFS. - Your FMAP must contain a region named "RW_MRC_CACHE". - -config MRC_CACHE_SIZE - hex "Fast Boot Data Cache Size" - default 0x10000 - depends on ENABLE_MRC_CACHE - depends on !MRC_CACHE_FMAP - help - This is the amount of space in NV storage that is reserved for the - fast boot data cache storage. - - WARNING: Because this area will be erased and re-written, the size - should be a full sector of the flash ROM chip and nothing else should - be included in CBFS in any sector that the fast boot cache data is in. - -config VIRTUAL_ROM_SIZE - hex "Virtual ROM Size" - default ROM_SIZE - depends on ENABLE_MRC_CACHE - help - This is used to calculate the offset of the MRC data cache in NV - Storage for fast boot. If in doubt, leave this set to the default - which sets the virtual size equal to the ROM size. - - Example: Cougar Canyon 2 has two 8 MB SPI ROMs. When the SPI ROMs are - loaded with a 4 MB coreboot image, the virtual ROM size is 8 MB. When - the SPI ROMs are loaded with an 8 MB coreboot image, the virtual ROM - size is 16 MB. - -config USE_GENERIC_FSP_CAR_INC - bool - default n - help - The chipset can select this to use a generic cache_as_ram.inc file - that should be good for all FSP based platforms. - -config FSP_USES_UPD - bool - default n - help - If this FSP uses UPD/VPD data regions, select this in the chipset Kconfig. -endif #PLATFORM_USES_FSP1_0 diff --git a/src/drivers/intel/fsp1_0/Makefile.inc b/src/drivers/intel/fsp1_0/Makefile.inc deleted file mode 100644 index 038694950a..0000000000 --- a/src/drivers/intel/fsp1_0/Makefile.inc +++ /dev/null @@ -1,56 +0,0 @@ -# -# This file is part of the coreboot project. -# -# This program is free software; you can redistribute it and/or modify -# it under the terms of the GNU General Public License as published by -# the Free Software Foundation; version 2 of the License. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# - -ifeq ($(CONFIG_PLATFORM_USES_FSP1_0),y) - -ramstage-y += fsp_util.c hob.c -romstage-y += fsp_util.c hob.c - -ramstage-$(CONFIG_ENABLE_MRC_CACHE) += fastboot_cache.c -romstage-$(CONFIG_ENABLE_MRC_CACHE) += fastboot_cache.c - -CPPFLAGS_common += -Isrc/drivers/intel/fsp1_0 -I$(objgenerated) - -cpu_incs-$(CONFIG_USE_GENERIC_FSP_CAR_INC) += $(src)/drivers/intel/fsp1_0/cache_as_ram.inc - -ifeq ($(CONFIG_HAVE_FSP_BIN),y) -cbfs-files-y += fsp.bin -fsp.bin-file := $(call strip_quotes,$(CONFIG_FSP_FILE)) -fsp.bin-position := $(CONFIG_FSP_LOC) -fsp.bin-type := fsp -fsp.bin-options := --xip $(TXTIBB) -endif - -ifeq ($(CONFIG_ENABLE_MRC_CACHE),y) -ifneq ($(CONFIG_MRC_CACHE_FMAP),y) -$(obj)/mrc.cache: - dd if=/dev/zero count=1 \ - bs=$(shell printf "%d" $(CONFIG_MRC_CACHE_SIZE) ) | \ - tr '\000' '\377' > $@ - -cbfs-files-y += mrc.cache -mrc.cache-file := $(obj)/mrc.cache -mrc.cache-align := 0x10000 -mrc.cache-type := mrc_cache -endif -endif - -ifneq ($(call strip_quotes,$(CONFIG_FSP_SRC_PATH)),) -ramstage-y += $(call strip_quotes,$(CONFIG_FSP_SRC_PATH)) -endif - -ifneq ($(call strip_quotes,$(CONFIG_FSP_HEADER_PATH)),) -CPPFLAGS_common += -I$(CONFIG_FSP_HEADER_PATH) -endif - -endif diff --git a/src/drivers/intel/fsp1_0/cache_as_ram.inc b/src/drivers/intel/fsp1_0/cache_as_ram.inc deleted file mode 100644 index 346416fdda..0000000000 --- a/src/drivers/intel/fsp1_0/cache_as_ram.inc +++ /dev/null @@ -1,119 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include - - cmp $0, %eax - je cache_as_ram - mov $0xa0, %eax - jmp .Lhlt - -cache_as_ram: - post_code(0x20) - - /* - * Find the FSP binary in cbfs. - * Make a fake stack that has the return value back to this code. - */ - lea fake_fsp_stack, %esp - jmp find_fsp_bypass_prologue -find_fsp_ret: - /* Save the FSP location */ - mov %eax, %ebp - cmp $CONFIG_FSP_LOC, %eax - jae find_fsp_ok - mov $0xb0, %eax - jmp .Lhlt - -find_fsp_ok: - post_code(POST_FSP_TEMP_RAM_INIT) - - /* Calculate entry into FSP */ - mov 0x30(%ebp), %eax /* Load TempRamInitEntry */ - add 0x1c(%ebp), %eax /* add in the offset for the FSP base address */ - - /* - * Pass early init variables on a fake stack (no memory yet) - * as well as the return location - */ - lea CAR_init_stack, %esp - - /* call FSP binary to setup temporary stack */ - jmp *%eax - -CAR_init_done: - addl $4, %esp - cmp $0, %eax - je car_init_ok - add $0xc0, %eax - jmp .Lhlt - -car_init_ok: - - /* Save FSP_INFO_HEADER location in ebx */ - mov %ebp, %ebx - - /* - * set up bootloader stack - * ecx: stack base - * edx: stack top - */ - mov %edx, %esp - movl %esp, %ebp - - /* Clear the cbmem CAR memory region. */ - movl %ecx, %edi - movl %edx, %ecx - sub %edi, %ecx - shr $2, %ecx - xorl %eax, %eax - rep stosl - -before_romstage: - post_code(0x23) - - /* Call romstage.c main function. */ - pushl %ebx /* main takes FSP_INFO_HEADER as its argument */ - call main /* does not return */ - movb $0xB8, %ah - jmp .Lhlt - -.Lhlt: -#if CONFIG(POST_IO) - outb %al, $CONFIG_POST_IO_PORT -#endif - hlt - jmp .Lhlt - -/* - * esp is set to this location so that the call into and return from the FSP - * in find_fsp will work. - */ - .align 4 -fake_fsp_stack: - .long find_fsp_ret - -CAR_init_params: - .long dummy_microcode - .long 0 - .long CACHE_ROM_BASE /* Firmware Location */ - .long CACHE_ROM_SIZE /* Total Firmware Length */ - -CAR_init_stack: - .long CAR_init_done - .long CAR_init_params - -dummy_microcode: - .long 0 diff --git a/src/drivers/intel/fsp1_0/fastboot_cache.c b/src/drivers/intel/fsp1_0/fastboot_cache.c deleted file mode 100644 index cd0324a2e9..0000000000 --- a/src/drivers/intel/fsp1_0/fastboot_cache.c +++ /dev/null @@ -1,248 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include // hexdump -#include "fsp_util.h" - -/* convert a pointer to flash area into the offset inside the flash */ -static inline u32 to_flash_offset(void *p) { - return ((u32)p + CONFIG_VIRTUAL_ROM_SIZE); -} - -static struct mrc_data_container *next_mrc_block( - struct mrc_data_container *mrc_cache) -{ - /* MRC data blocks are aligned within the region */ - u32 mrc_size = sizeof(*mrc_cache) + mrc_cache->mrc_data_size; - if (mrc_size & (MRC_DATA_ALIGN - 1UL)) { - mrc_size &= ~(MRC_DATA_ALIGN - 1UL); - mrc_size += MRC_DATA_ALIGN; - } - - u8 *region_ptr = (u8*)mrc_cache; - region_ptr += mrc_size; - return (struct mrc_data_container *)region_ptr; -} - -static int is_mrc_cache(struct mrc_data_container *mrc_cache) -{ - return (!!mrc_cache) && (mrc_cache->mrc_signature == MRC_DATA_SIGNATURE); -} - -static u32 get_mrc_cache_region(struct mrc_data_container **mrc_region_ptr) -{ - size_t region_size; - - if (CONFIG(MRC_CACHE_FMAP)) { - struct region_device rdev; - if (fmap_locate_area_as_rdev("RW_MRC_CACHE", &rdev) == 0) { - *mrc_region_ptr = rdev_mmap_full(&rdev); - return region_device_sz(&rdev); - } - *mrc_region_ptr = NULL; - return 0; - } - *mrc_region_ptr = cbfs_boot_map_with_leak("mrc.cache", - CBFS_TYPE_MRC_CACHE, - ®ion_size); - - return region_size; -} - -/* - * Find the largest index block in the MRC cache. Return NULL if none is - * found. - */ -static struct mrc_data_container *find_current_mrc_cache_local - (struct mrc_data_container *mrc_cache, u32 region_size) -{ - u32 region_end; - u32 entry_id = 0; - struct mrc_data_container *mrc_next = mrc_cache; - - region_end = (u32) mrc_cache + region_size; - - /* Search for the last filled entry in the region */ - while (is_mrc_cache(mrc_next)) { - entry_id++; - mrc_cache = mrc_next; - mrc_next = next_mrc_block(mrc_next); - if ((u32)mrc_next >= region_end) { - /* Stay in the MRC data region */ - break; - } - } - - if (entry_id == 0) { - printk(BIOS_ERR, "%s: No valid fast boot cache found.\n", __func__); - return NULL; - } - - /* Verify checksum */ - if (mrc_cache->mrc_checksum != - compute_ip_checksum(mrc_cache->mrc_data, - mrc_cache->mrc_data_size)) { - printk(BIOS_ERR, "%s: fast boot cache checksum mismatch\n", __func__); - return NULL; - } - - printk(BIOS_DEBUG, "%s: picked entry %u from cache block\n", __func__, - entry_id - 1); - - return mrc_cache; -} - -/* find the first empty block in the MRC cache area. - * If there's none, return NULL. - * - * @mrc_cache_base - base address of the MRC cache area - * @mrc_cache - current entry (for which we need to find next) - * @region_size - total size of the MRC cache area - */ -static struct mrc_data_container *find_next_mrc_cache - (struct mrc_data_container *mrc_cache_base, - struct mrc_data_container *mrc_cache, - u32 region_size) -{ - u32 region_end = (u32) mrc_cache_base + region_size; - u32 mrc_data_size = mrc_cache->mrc_data_size; - - mrc_cache = next_mrc_block(mrc_cache); - if (((u32)mrc_cache + mrc_data_size) >= region_end) { - /* Crossed the boundary */ - mrc_cache = NULL; - printk(BIOS_DEBUG, "%s: no available entries found\n", - __func__); - } else { - printk(BIOS_DEBUG, - "%s: picked next entry from cache block at %p\n", - __func__, mrc_cache); - } - - return mrc_cache; -} - -void update_mrc_cache(void *unused) -{ - printk(BIOS_DEBUG, "Updating fast boot cache data.\n"); - struct mrc_data_container *current = cbmem_find(CBMEM_ID_MRCDATA); - struct mrc_data_container *cache, *cache_base; - u32 cache_size; - struct spi_flash flash; - - if (!current) { - printk(BIOS_ERR, "No fast boot cache in cbmem. Can't update flash.\n"); - return; - } - if (current->mrc_data_size == -1) { - printk(BIOS_ERR, "Fast boot cache data in cbmem invalid.\n"); - return; - } - - cache_size = get_mrc_cache_region(&cache_base); - if (cache_base == NULL) { - printk(BIOS_ERR, "%s: could not find fast boot cache area\n", - __func__); - return; - } - - /* - * we need to: - * 0. compare MRC data to last mrc-cache block (exit if same) - */ - cache = find_current_mrc_cache_local(cache_base, cache_size); - - if (cache && (cache->mrc_data_size == current->mrc_data_size) && - (memcmp(cache, current, cache->mrc_data_size) == 0)) { - printk(BIOS_DEBUG, - "MRC data in flash is up to date. No update.\n"); - return; - } - - /* 1. use spi_flash_probe() to find the flash, then... */ - spi_init(); - if (spi_flash_probe(0, 0, &flash)) { - printk(BIOS_DEBUG, "Could not find SPI device\n"); - return; - } - - /* 2. look up the first unused block */ - if (cache) - cache = find_next_mrc_cache(cache_base, cache, cache_size); - - /* - * 3. if no such place exists, erase entire mrc-cache range & use - * block 0. First time around the erase is not needed, but this is a - * small overhead for simpler code. - */ - if (!cache) { - printk(BIOS_DEBUG, - "Need to erase the MRC cache region of %d bytes at %p\n", - cache_size, cache_base); - - spi_flash_erase(&flash, to_flash_offset(cache_base), - cache_size); - - /* we will start at the beginning again */ - cache = cache_base; - } - /* 4. write mrc data with spi_flash_write() */ - printk(BIOS_DEBUG, "Write MRC cache update to flash at %p\n", - cache); - spi_flash_write(&flash, to_flash_offset(cache), - current->mrc_data_size + sizeof(*current), current); -} - -void *find_and_set_fastboot_cache(void) -{ - struct mrc_data_container *mrc_cache = NULL; - if (((mrc_cache = find_current_mrc_cache()) == NULL) || - (mrc_cache->mrc_data_size == -1UL)) { - printk(BIOS_DEBUG, "FSP MRC cache not present.\n"); - return NULL; - } - printk(BIOS_DEBUG, "FSP MRC cache present at %x.\n", (u32)mrc_cache); - printk(BIOS_SPEW, "Saved MRC data:\n"); - hexdump32(BIOS_SPEW, (void *)mrc_cache->mrc_data, (mrc_cache->mrc_data_size) / 4); - return (void *) mrc_cache->mrc_data; -} - -struct mrc_data_container *find_current_mrc_cache(void) -{ - struct mrc_data_container *cache_base; - u32 cache_size; - - cache_size = get_mrc_cache_region(&cache_base); - if (cache_base == NULL) { - printk(BIOS_ERR, "%s: could not find fast boot cache area\n", - __func__); - return NULL; - } - - /* - * we need to: - * 0. compare MRC data to last mrc-cache block (exit if same) - */ - return find_current_mrc_cache_local(cache_base, cache_size); -} diff --git a/src/drivers/intel/fsp1_0/fsp_util.c b/src/drivers/intel/fsp1_0/fsp_util.c deleted file mode 100644 index 4b38c01ade..0000000000 --- a/src/drivers/intel/fsp1_0/fsp_util.c +++ /dev/null @@ -1,352 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include -#include -#include -#include "fsp_util.h" -#include // hexdump -#include -#include -#include -#include - -/* Globals pointers for FSP structures */ -void *FspHobListPtr = NULL; -FSP_INFO_HEADER *fsp_header_ptr = NULL; - -void FspNotify (u32 Phase) -{ - FSP_NOTFY_PHASE NotifyPhaseProc; - NOTIFY_PHASE_PARAMS NotifyPhaseParams; - EFI_STATUS Status; - - if (fsp_header_ptr == NULL) { - fsp_header_ptr = (void *)find_fsp(); - if ((u32)fsp_header_ptr < 0xff) { - post_code(0x4F); /* output something in case there is no serial */ - die("Can't find the FSP!\n"); - } - } - - /* call FSP PEI to Notify PostPciEnumeration */ - NotifyPhaseProc = (FSP_NOTFY_PHASE)(fsp_header_ptr->ImageBase + - fsp_header_ptr->NotifyPhaseEntry); - NotifyPhaseParams.Phase = Phase; - - timestamp_add_now(Phase == EnumInitPhaseReadyToBoot ? - TS_FSP_BEFORE_FINALIZE : TS_FSP_BEFORE_ENUMERATE); - - Status = NotifyPhaseProc (&NotifyPhaseParams); - - timestamp_add_now(Phase == EnumInitPhaseReadyToBoot ? - TS_FSP_AFTER_FINALIZE : TS_FSP_AFTER_ENUMERATE); - - if (Status != 0) - printk(BIOS_ERR,"FSP API NotifyPhase failed for phase 0x%x with status: 0x%x\n", Phase, Status); -} - -/* The FSP returns here after the fsp_early_init call */ -static void ChipsetFspReturnPoint(EFI_STATUS Status, VOID *HobListPtr) -{ - *(void **)CBMEM_FSP_HOB_PTR = HobListPtr; - - if (Status == 0xFFFFFFFF) - system_reset(); - - romstage_main_continue(Status, HobListPtr); -} - -/* - * Call the FSP to do memory init. The FSP doesn't return to this function. - * The FSP returns to the romstage_main_continue(). - */ -void __noreturn fsp_early_init (FSP_INFO_HEADER *fsp_ptr) -{ - FSP_FSP_INIT FspInitApi; - FSP_INIT_PARAMS FspInitParams; - FSP_INIT_RT_BUFFER FspRtBuffer; -#if CONFIG(FSP_USES_UPD) - UPD_DATA_REGION fsp_upd_data; -#endif - - /* Load microcode before RAM init */ - if (CONFIG(SUPPORT_CPU_UCODE_IN_CBFS)) - intel_update_microcode_from_cbfs(); - - memset((void *)&FspRtBuffer, 0, sizeof(FSP_INIT_RT_BUFFER)); - FspRtBuffer.Common.StackTop = (u32 *)CONFIG_RAMTOP; - FspInitParams.NvsBufferPtr = NULL; - -#if CONFIG(FSP_USES_UPD) - FspRtBuffer.Common.UpdDataRgnPtr = &fsp_upd_data; -#endif - FspInitParams.RtBufferPtr = (FSP_INIT_RT_BUFFER *)&FspRtBuffer; - FspInitParams.ContinuationFunc = (CONTINUATION_PROC)ChipsetFspReturnPoint; - FspInitApi = (FSP_FSP_INIT)(fsp_ptr->ImageBase + fsp_ptr->FspInitEntry); - - /* Call the chipset code to fill in the chipset specific structures */ - chipset_fsp_early_init(&FspInitParams, fsp_ptr); - - /* Call back to romstage for board specific changes */ - romstage_fsp_rt_buffer_callback(&FspRtBuffer); - - post_code(POST_FSP_MEMORY_INIT); - FspInitApi(&FspInitParams); - - /* Should never return. Control will continue from ContinuationFunc */ - die("Uh Oh! FspInitApi returned"); -} - -volatile u8 *find_fsp() -{ -#if ENV_ROMSTAGE - volatile register u8 *fsp_ptr asm ("eax"); - - /* Entry point for CAR assembly routine */ - __asm__ __volatile__ ( - ".global find_fsp_bypass_prologue\n\t" - "find_fsp_bypass_prologue:\n\t" - ); -#else - volatile u8 *fsp_ptr; -#endif - - /* The FSP is stored in CBFS */ - fsp_ptr = (u8 *) CONFIG_FSP_LOC; - - /* Check the FV signature, _FVH */ - if (((EFI_FIRMWARE_VOLUME_HEADER *)fsp_ptr)->Signature == 0x4856465F) { - /* Go to the end of the FV header and align the address. */ - fsp_ptr += ((EFI_FIRMWARE_VOLUME_HEADER *)fsp_ptr)->ExtHeaderOffset; - fsp_ptr += ((EFI_FIRMWARE_VOLUME_EXT_HEADER *)fsp_ptr)->ExtHeaderSize; - fsp_ptr = (u8 *)(((u32)fsp_ptr + 7) & 0xFFFFFFF8); - } else { - fsp_ptr = (u8*)ERROR_NO_FV_SIG; - } - - /* Check the FFS GUID */ - if (((u32)fsp_ptr > 0xff) && - (((u32 *)&(((EFI_FFS_FILE_HEADER *)fsp_ptr)->Name))[0] == 0x912740BE) && - (((u32 *)&(((EFI_FFS_FILE_HEADER *)fsp_ptr)->Name))[1] == 0x47342284) && - (((u32 *)&(((EFI_FFS_FILE_HEADER *)fsp_ptr)->Name))[2] == 0xB08471B9) && - (((u32 *)&(((EFI_FFS_FILE_HEADER *)fsp_ptr)->Name))[3] == 0x0C3F3527)) { - /* Add the FFS Header size to the base to find the Raw section Header */ - fsp_ptr += sizeof(EFI_FFS_FILE_HEADER); - } else { - fsp_ptr = (u8 *)ERROR_NO_FFS_GUID; - } - - if (((u32)fsp_ptr > 0xff) && - ((EFI_RAW_SECTION *)fsp_ptr)->Type == EFI_SECTION_RAW) { - /* Add the Raw Header size to the base to find the FSP INFO Header */ - fsp_ptr += sizeof(EFI_RAW_SECTION); - } else { - fsp_ptr = (u8 *)ERROR_NO_INFO_HEADER; - } - - /* Verify that the FSP is set to the base address we're expecting.*/ - if (((u32)fsp_ptr > 0xff) && - (*(u32*)(fsp_ptr + FSP_IMAGE_BASE_LOC) != CONFIG_FSP_LOC)) { - fsp_ptr = (u8 *)ERROR_IMAGEBASE_MISMATCH; - } - - /* Verify the FSP Signature */ - if (((u32)fsp_ptr > 0xff) && - (*(u32*)(fsp_ptr + FSP_IMAGE_SIG_LOC) != FSP_SIG)){ - fsp_ptr = (u8 *)ERROR_INFO_HEAD_SIG_MISMATCH; - } - - /* Verify the FSP ID */ - if (((u32)fsp_ptr > 0xff) && - ((*(u32 *)(fsp_ptr + FSP_IMAGE_ID_LOC) != FSP_IMAGE_ID_DWORD0) || - (*(u32 *)(fsp_ptr + (FSP_IMAGE_ID_LOC + 4)) != FSP_IMAGE_ID_DWORD1))) { - fsp_ptr = (u8 *)ERROR_FSP_SIG_MISMATCH; - } - - return (fsp_ptr); -} - -/** finds the saved temporary memory information in the FSP HOB list - * - * @param hob_list_ptr pointer to the start of the hob list - * @return pointer to saved CAR MEM or NULL if not found. - */ -void *find_saved_temp_mem(void *hob_list_ptr) -{ - EFI_GUID temp_hob_guid = FSP_BOOTLOADER_TEMPORARY_MEMORY_HOB_GUID; - EFI_HOB_GUID_TYPE *saved_mem_hob = - (EFI_HOB_GUID_TYPE *) find_hob_by_guid( - hob_list_ptr, &temp_hob_guid); - - if (saved_mem_hob == NULL) - return NULL; - - return (void *) ((char *) saved_mem_hob + sizeof(EFI_HOB_GUID_TYPE)); -} - -#ifndef FSP_RESERVE_MEMORY_SIZE -/** @brief locates the HOB containing the location of the fsp reserved mem area - * - * @param hob_list_ptr pointer to the start of the hob list - * @return pointer to the start of the FSP reserved memory or NULL if not found. - */ -void *find_fsp_reserved_mem(void *hob_list_ptr) -{ - EFI_GUID fsp_reserved_guid = FSP_HOB_RESOURCE_OWNER_FSP_GUID; - EFI_HOB_RESOURCE_DESCRIPTOR *fsp_reserved_mem = - (EFI_HOB_RESOURCE_DESCRIPTOR *) find_hob_by_guid( - hob_list_ptr, &fsp_reserved_guid); - - if (fsp_reserved_mem == NULL) - return NULL; - - return (void *)((uintptr_t)fsp_reserved_mem->PhysicalStart); -} -#endif /* FSP_RESERVE_MEMORY_SIZE */ - -void print_fsp_info(void) { - - if (fsp_header_ptr == NULL) - fsp_header_ptr = (void *)find_fsp(); - - if ((u32)fsp_header_ptr < 0xff) { - post_code(0x4F); /* post code in case there is no serial */ - die("Can't find the FSP!\n"); - } - - if (FspHobListPtr == NULL) { - FspHobListPtr = (void *)*((u32 *) - cbmem_find(CBMEM_ID_HOB_POINTER)); - } - - printk(BIOS_SPEW,"fsp_header_ptr: %p\n", fsp_header_ptr); - printk(BIOS_INFO,"FSP Header Version: %d\n", fsp_header_ptr->HeaderRevision); - printk(BIOS_INFO,"FSP Revision: %d.%d\n", - (u8)((fsp_header_ptr->ImageRevision >> 8) & 0xff), - (u8)(fsp_header_ptr->ImageRevision & 0xff)); -} - -/** - * Save the FSP memory HOB (mrc data) to the MRC area in CBMEM - */ -static int save_mrc_data(void *hob_start) -{ - u32 *mrc_hob; - u32 *mrc_hob_data; - u32 mrc_hob_size; - struct mrc_data_container *mrc_data; - int output_len; - const EFI_GUID mrc_guid = FSP_NON_VOLATILE_STORAGE_HOB_GUID; - - mrc_hob = GetNextGuidHob(&mrc_guid, hob_start); - if (mrc_hob == NULL){ - printk(BIOS_DEBUG, "Memory Configure Data Hob is not present\n"); - return(0); - } - - mrc_hob_data = GET_GUID_HOB_DATA (mrc_hob); - mrc_hob_size = (u32) GET_HOB_LENGTH(mrc_hob); - - printk(BIOS_DEBUG, "Memory Configure Data Hob at %p (size = 0x%x).\n", - (void *)mrc_hob_data, mrc_hob_size); - - output_len = ALIGN_UP(mrc_hob_size, 16); - - /* Save the MRC S3/fast boot/ADR restore data to cbmem */ - mrc_data = cbmem_add (CBMEM_ID_MRCDATA, - output_len + sizeof(struct mrc_data_container)); - - /* Just return if there was a problem with getting CBMEM */ - if (mrc_data == NULL) { - printk(BIOS_WARNING, "CBMEM was not available to save the fast boot cache data.\n"); - return 0; - } - - printk(BIOS_DEBUG, "Copy FSP MRC DATA to HOB (source addr %p, dest addr %p, %u bytes)\n", - (void *)mrc_hob_data, mrc_data, output_len); - - mrc_data->mrc_signature = MRC_DATA_SIGNATURE; - mrc_data->mrc_data_size = output_len; - mrc_data->reserved = 0; - memcpy(mrc_data->mrc_data, (const void *)mrc_hob_data, mrc_hob_size); - - /* Zero the unused space in aligned buffer. */ - if (output_len > mrc_hob_size) - memset((mrc_data->mrc_data + mrc_hob_size), 0, - output_len - mrc_hob_size); - - mrc_data->mrc_checksum = compute_ip_checksum(mrc_data->mrc_data, - mrc_data->mrc_data_size); - - printk(BIOS_SPEW, "Fast boot data (includes align and checksum):\n"); - hexdump32(BIOS_SPEW, (void *)mrc_data->mrc_data, output_len / 4); - return (1); -} - -static void find_fsp_hob_update_mrc(void *unused) -{ - /* Set the global HOB list pointer */ - FspHobListPtr = (void *)*((u32 *) cbmem_find(CBMEM_ID_HOB_POINTER)); - - if (!FspHobListPtr){ - printk(BIOS_ERR, "ERROR: Could not find FSP HOB pointer in CBFS!\n"); - } else { - /* 0x0000: Print all types */ - print_hob_type_structure(0x000, FspHobListPtr); - } - - if (CONFIG(ENABLE_MRC_CACHE)) { - if (save_mrc_data(FspHobListPtr)) - update_mrc_cache(NULL); - else - printk(BIOS_DEBUG,"Not updating MRC data in flash.\n"); - } -} - -/** @brief Notify FSP for PostPciEnumeration - * - * @param unused - */ -static void fsp_after_pci_enum(void *unused) -{ - /* This call needs to be done before resource allocation. */ - printk(BIOS_DEBUG, "FspNotify(EnumInitPhaseAfterPciEnumeration)\n"); - post_code(POST_FSP_NOTIFY_BEFORE_ENUMERATE); - FspNotify(EnumInitPhaseAfterPciEnumeration); - printk(BIOS_DEBUG, - "Returned from FspNotify(EnumInitPhaseAfterPciEnumeration)\n"); -} - -/** @brief Notify FSP for ReadyToBoot - * - * @param unused - */ -static void fsp_finalize(void *unused) -{ - printk(BIOS_DEBUG, "FspNotify(EnumInitPhaseReadyToBoot)\n"); - print_fsp_info(); - post_code(POST_FSP_NOTIFY_BEFORE_FINALIZE); - FspNotify(EnumInitPhaseReadyToBoot); - printk(BIOS_DEBUG, "Returned from FspNotify(EnumInitPhaseReadyToBoot)\n"); -} - - -/* Set up for the ramstage FSP calls */ -BOOT_STATE_INIT_ENTRY(BS_DEV_ENUMERATE, BS_ON_EXIT, fsp_after_pci_enum, NULL); -BOOT_STATE_INIT_ENTRY(BS_PAYLOAD_BOOT, BS_ON_ENTRY, fsp_finalize, NULL); - -/* Update the MRC/fast boot cache as part of the late table writing stage */ -BOOT_STATE_INIT_ENTRY(BS_WRITE_TABLES, BS_ON_ENTRY, find_fsp_hob_update_mrc, NULL); diff --git a/src/drivers/intel/fsp1_0/fsp_util.h b/src/drivers/intel/fsp1_0/fsp_util.h deleted file mode 100644 index ca0e8d83d2..0000000000 --- a/src/drivers/intel/fsp1_0/fsp_util.h +++ /dev/null @@ -1,123 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef FSP_UTIL_H -#define FSP_UTIL_H - -#include -#include - -#include "fsp_values.h" - -void *find_and_set_fastboot_cache(void); - -volatile u8 *find_fsp(void); -void fsp_early_init(FSP_INFO_HEADER *fsp_info); -void FspNotify(u32 Phase); -void FspNotifyReturnPoint(EFI_STATUS Status, VOID *HobListPtr); -void romstage_fsp_rt_buffer_callback(FSP_INIT_RT_BUFFER *FspRtBuffer); -void print_fsp_info(void); -void chipset_fsp_early_init(FSP_INIT_PARAMS *FspInitParams, - FSP_INFO_HEADER *fsp_ptr); -void *find_saved_temp_mem(void *hob_list_ptr); -void *find_fsp_reserved_mem(void *hob_list_ptr); - -/* function in romstage.c */ -void romstage_main_continue(EFI_STATUS status, void *hob_list_ptr); - -/* functions in hob.c */ -void print_hob_mem_attributes(void *Hobptr); -void print_hob_type_structure(u16 Hobtype, void *Hoblistptr); -void print_hob_resource_attributes(void *Hobptr); -void print_guid_type_attributes(void *Hobptr); -const char *get_hob_type_string(void *Hobptr); -void *find_hob_by_guid(void *Hoblistptr, EFI_GUID *guid1); -uint8_t guids_are_equal(EFI_GUID *guid1, EFI_GUID *guid2); -void printguid(EFI_GUID *guid); - -/* Additional HOB types not included in the FSP: - * #define EFI_HOB_TYPE_HANDOFF 0x0001 - * #define EFI_HOB_TYPE_MEMORY_ALLOCATION 0x0002 - * #define EFI_HOB_TYPE_RESOURCE_DESCRIPTOR 0x0003 - * #define EFI_HOB_TYPE_GUID_EXTENSION 0x0004 - * #define EFI_HOB_TYPE_FV 0x0005 - * #define EFI_HOB_TYPE_CPU 0x0006 - * #define EFI_HOB_TYPE_MEMORY_POOL 0x0007 - * #define EFI_HOB_TYPE_CV 0x0008 - * #define EFI_HOB_TYPE_UNUSED 0xFFFE - * #define EFI_HOB_TYPE_END_OF_HOB_LIST 0xffff - */ -#define EFI_HOB_TYPE_HANDOFF 0x0001 -#define EFI_HOB_TYPE_MEMORY_POOL 0x0007 - -#define MRC_DATA_ALIGN 0x1000 -#define MRC_DATA_SIGNATURE (('M'<<0)|('R'<<8)|('C'<<16)|('D'<<24)) - -struct mrc_data_container { - u32 mrc_signature; // "MRCD" - u32 mrc_data_size; // Actual total size of this structure - u32 mrc_checksum; // IP style checksum - u32 reserved; // For header alignment - u8 mrc_data[0]; // Variable size, platform/run time dependent. -} __packed; - -struct mrc_data_container *find_current_mrc_cache(void); - -void update_mrc_cache(void *unused); - -/* The offset in bytes from the start of the info structure */ -#define FSP_IMAGE_SIG_LOC 0 -#define FSP_IMAGE_ID_LOC 16 -#define FSP_IMAGE_BASE_LOC 28 - -#define FSP_SIG 0x48505346 /* 'FSPH' */ - -#define ERROR_NO_FV_SIG 1 -#define ERROR_NO_FFS_GUID 2 -#define ERROR_NO_INFO_HEADER 3 -#define ERROR_IMAGEBASE_MISMATCH 4 -#define ERROR_INFO_HEAD_SIG_MISMATCH 5 -#define ERROR_FSP_SIG_MISMATCH 6 - -extern void *FspHobListPtr; - -#define UPD_DEFAULT_CHECK(member) \ - if (config->member != UPD_DEFAULT) { \ - UpdData->member = config->member - 1; \ - } \ - printk(FSP_INFO_LEVEL, #member ":\t\t0x%02x %s\n", UpdData->member, \ - config->member ? "(set)" : "(default)"); - -#define UPD_SPD_CHECK(member) \ - if (config->member == UPD_SPD_ADDR_DISABLED) { \ - UpdData->member = 0x00; \ - } else if (config->member != UPD_SPD_ADDR_DEFAULT) { \ - UpdData->member = config->member; \ - } \ - printk(FSP_INFO_LEVEL, #member ":\t\t0x%02x %s\n", UpdData->member, \ - config->member ? "(set)" : "(default)"); - -#define UPD_DEVICE_CHECK(devicename, member, statement) \ - case devicename: \ - UpdData->member = dev->enabled; \ - printk(FSP_INFO_LEVEL, statement "%s\n", \ - UpdData->member?"Enabled":"Disabled"); \ - break; - - -#ifndef FSP_BOOTLOADER_TEMPORARY_MEMORY_HOB_GUID -#define FSP_BOOTLOADER_TEMPORARY_MEMORY_HOB_GUID \ - { 0xbbcff46c, 0xc8d3, 0x4113, { 0x89, 0x85, 0xb9, 0xd4, 0xf3, 0xb3, 0xf6, 0x4e } }; -#endif - -#endif /* FSP_UTIL_H */ diff --git a/src/drivers/intel/fsp1_0/fsp_values.h b/src/drivers/intel/fsp1_0/fsp_values.h deleted file mode 100644 index a16a887760..0000000000 --- a/src/drivers/intel/fsp1_0/fsp_values.h +++ /dev/null @@ -1,35 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef FSP_VALUES_H -#define FSP_VALUES_H - -#ifndef FSP_DEBUG_LEVEL -# define FSP_DEBUG_LEVEL BIOS_SPEW -#endif - -#ifndef FSP_INFO_LEVEL -# define FSP_INFO_LEVEL BIOS_DEBUG -#endif - -#define INCREMENT_FOR_DEFAULT(x) (x+1) - -#define UPD_DEFAULT 0x00 -#define UPD_DISABLE INCREMENT_FOR_DEFAULT(0) -#define UPD_ENABLE INCREMENT_FOR_DEFAULT(1) -#define UPD_USE_DEVICETREE 0xff - -#define UPD_SPD_ADDR_DEFAULT UPD_DEFAULT -#define UPD_SPD_ADDR_DISABLED 0xFF - -#endif diff --git a/src/drivers/intel/fsp1_0/hob.c b/src/drivers/intel/fsp1_0/hob.c deleted file mode 100644 index 9b4c0a44f7..0000000000 --- a/src/drivers/intel/fsp1_0/hob.c +++ /dev/null @@ -1,261 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include "fsp_util.h" - - -/** Displays a GUID's address and value - * - * @param guid pointer to the GUID to display - */ -void printguid(EFI_GUID *guid) -{ - printk(BIOS_SPEW,"Address: %p Guid: %08lx-%04x-%04x-", - guid, (unsigned long)guid->Data1, - guid->Data2, guid->Data3); - printk(BIOS_SPEW,"%02x%02x%02x%02x%02x%02x%02x%02x\n", - guid->Data4[0], guid->Data4[1], - guid->Data4[2], guid->Data4[3], - guid->Data4[4], guid->Data4[5], - guid->Data4[6], guid->Data4[7]); -} - -void print_hob_mem_attributes(void *Hobptr) -{ - EFI_HOB_MEMORY_ALLOCATION *HobMemoryPtr = (EFI_HOB_MEMORY_ALLOCATION *)Hobptr; - EFI_MEMORY_TYPE Hobmemtype = HobMemoryPtr->AllocDescriptor.MemoryType; - u64 Hobmemaddr = HobMemoryPtr->AllocDescriptor.MemoryBaseAddress; - u64 Hobmemlength = HobMemoryPtr->AllocDescriptor.MemoryLength; - const char *Hobmemtypenames[15]; - - Hobmemtypenames[0] = "EfiReservedMemoryType"; - Hobmemtypenames[1] = "EfiLoaderCode"; - Hobmemtypenames[2] = "EfiLoaderData"; - Hobmemtypenames[3] = "EfiBootServicesCode"; - Hobmemtypenames[4] = "EfiBootServicesData"; - Hobmemtypenames[5] = "EfiRuntimeServicesCode"; - Hobmemtypenames[6] = "EfiRuntimeServicesData"; - Hobmemtypenames[7] = "EfiConventionalMemory"; - Hobmemtypenames[8] = "EfiUnusableMemory"; - Hobmemtypenames[9] = "EfiACPIReclaimMemory"; - Hobmemtypenames[10] = "EfiACPIMemoryNVS"; - Hobmemtypenames[11] = "EfiMemoryMappedIO"; - Hobmemtypenames[12] = "EfiMemoryMappedIOPortSpace"; - Hobmemtypenames[13] = "EfiPalCode"; - Hobmemtypenames[14] = "EfiMaxMemoryType"; - - printk(BIOS_SPEW, " Memory type %s (0x%x)\n", - Hobmemtypenames[(u32)Hobmemtype], (u32) Hobmemtype); - printk(BIOS_SPEW, " at location 0x%0lx with length 0x%0lx\n", - (unsigned long)Hobmemaddr, (unsigned long)Hobmemlength); -} - -void print_hob_resource_attributes(void *Hobptr) -{ - EFI_HOB_RESOURCE_DESCRIPTOR *HobResourcePtr = - (EFI_HOB_RESOURCE_DESCRIPTOR *)Hobptr; - u32 Hobrestype = HobResourcePtr->ResourceType; - u32 Hobresattr = HobResourcePtr->ResourceAttribute; - u64 Hobresaddr = HobResourcePtr->PhysicalStart; - u64 Hobreslength = HobResourcePtr->ResourceLength; - const char *Hobrestypestr = NULL; - - // HOB Resource Types - switch (Hobrestype) { - case EFI_RESOURCE_SYSTEM_MEMORY: - Hobrestypestr = "EFI_RESOURCE_SYSTEM_MEMORY"; break; - case EFI_RESOURCE_MEMORY_MAPPED_IO: - Hobrestypestr = "EFI_RESOURCE_MEMORY_MAPPED_IO"; break; - case EFI_RESOURCE_IO: - Hobrestypestr = "EFI_RESOURCE_IO"; break; - case EFI_RESOURCE_FIRMWARE_DEVICE: - Hobrestypestr = "EFI_RESOURCE_FIRMWARE_DEVICE"; break; - case EFI_RESOURCE_MEMORY_MAPPED_IO_PORT: - Hobrestypestr = "EFI_RESOURCE_MEMORY_MAPPED_IO_PORT"; break; - case EFI_RESOURCE_MEMORY_RESERVED: - Hobrestypestr = "EFI_RESOURCE_MEMORY_RESERVED"; break; - case EFI_RESOURCE_IO_RESERVED: - Hobrestypestr = "EFI_RESOURCE_IO_RESERVED"; break; - case EFI_RESOURCE_MAX_MEMORY_TYPE: - Hobrestypestr = "EFI_RESOURCE_MAX_MEMORY_TYPE"; break; - default: - Hobrestypestr = "EFI_RESOURCE_UNKNOWN"; break; - } - - printk(BIOS_SPEW, " Resource %s (0x%0x) has attributes 0x%0x\n", - Hobrestypestr, Hobrestype, Hobresattr); - printk(BIOS_SPEW, " at location 0x%0lx with length 0x%0lx\n", - (unsigned long)Hobresaddr, (unsigned long)Hobreslength); -} - -const char *get_hob_type_string(void *Hobptr) -{ - EFI_HOB_GENERIC_HEADER *HobHeaderPtr = (EFI_HOB_GENERIC_HEADER *)Hobptr; - u16 Hobtype = HobHeaderPtr->HobType; - const char *Hobtypestring = NULL; - - switch (Hobtype) { - case EFI_HOB_TYPE_HANDOFF: - Hobtypestring = "EFI_HOB_TYPE_HANDOFF"; break; - case EFI_HOB_TYPE_MEMORY_ALLOCATION: - Hobtypestring = "EFI_HOB_TYPE_MEMORY_ALLOCATION"; break; - case EFI_HOB_TYPE_RESOURCE_DESCRIPTOR: - Hobtypestring = "EFI_HOB_TYPE_RESOURCE_DESCRIPTOR"; break; - case EFI_HOB_TYPE_GUID_EXTENSION: - Hobtypestring = "EFI_HOB_TYPE_GUID_EXTENSION"; break; - case EFI_HOB_TYPE_MEMORY_POOL: - Hobtypestring = "EFI_HOB_TYPE_MEMORY_POOL"; break; - case EFI_HOB_TYPE_UNUSED: - Hobtypestring = "EFI_HOB_TYPE_UNUSED"; break; - case EFI_HOB_TYPE_END_OF_HOB_LIST: - Hobtypestring = "EFI_HOB_TYPE_END_OF_HOB_LIST"; break; - default: - Hobtypestring = "EFI_HOB_TYPE_UNRECOGNIZED"; break; - } - - return Hobtypestring; -} - -/** Displays the length, location, and GUID value of a GUID extension - * - * The EFI_HOB_GUID_TYPE is very basic - it just contains the standard - * HOB header containing the HOB type and length, and a GUID for - * identification. The rest of the data is undefined and must be known - * based on the GUID. - * - * This displays the entire HOB length, and the location of the start - * of the HOB, *NOT* the length of or the start of the data inside the HOB. - * - * @param Hobptr - */ -void print_guid_type_attributes(void *Hobptr) -{ - printk(BIOS_SPEW, " at location %p with length0x%0lx\n ", - Hobptr, (unsigned long)(((EFI_PEI_HOB_POINTERS *) \ - Hobptr)->Guid->Header.HobLength)); - printguid(&(((EFI_HOB_GUID_TYPE *)Hobptr)->Name)); - -} - -/* Print out a structure of all the HOBs - * that match a certain type: - * Print all types (0x0000) - * EFI_HOB_TYPE_HANDOFF (0x0001) - * EFI_HOB_TYPE_MEMORY_ALLOCATION (0x0002) - * EFI_HOB_TYPE_RESOURCE_DESCRIPTOR (0x0003) - * EFI_HOB_TYPE_GUID_EXTENSION (0x0004) - * EFI_HOB_TYPE_MEMORY_POOL (0x0007) - * EFI_HOB_TYPE_UNUSED (0xFFFE) - * EFI_HOB_TYPE_END_OF_HOB_LIST (0xFFFF) - */ -void print_hob_type_structure(u16 Hobtype, void *Hoblistptr) -{ - u32 *Currenthob; - u32 *Nexthob = NULL; - u8 Lasthob = 0; - u32 Currenttype; - const char *Currenttypestr; - - Currenthob = Hoblistptr; - - /* Print out HOBs of our desired type until - * the end of the HOB list - */ - printk(BIOS_DEBUG, "\n=== FSP HOB Data Structure ===\n"); - printk(BIOS_DEBUG, "FSP Hoblistptr: 0x%0x\n", - (u32) Hoblistptr); - do { - EFI_HOB_GENERIC_HEADER *CurrentHeaderPtr = - (EFI_HOB_GENERIC_HEADER *)Currenthob; - Currenttype = CurrentHeaderPtr->HobType; /* Get the type of this HOB */ - Currenttypestr = get_hob_type_string(Currenthob); - - if (Currenttype == Hobtype || Hobtype == 0x0000) { - printk(BIOS_DEBUG, "HOB 0x%0x is an %s (type 0x%0x)\n", - (u32) Currenthob, Currenttypestr, Currenttype); - switch (Currenttype) { - case EFI_HOB_TYPE_MEMORY_ALLOCATION: - print_hob_mem_attributes(Currenthob); break; - case EFI_HOB_TYPE_RESOURCE_DESCRIPTOR: - print_hob_resource_attributes(Currenthob); break; - case EFI_HOB_TYPE_GUID_EXTENSION: - print_guid_type_attributes(Currenthob); break; - } - } - - Lasthob = END_OF_HOB_LIST(Currenthob); /* Check for end of HOB list */ - if (!Lasthob) { - Nexthob = GET_NEXT_HOB(Currenthob); /* Get next HOB pointer */ - Currenthob = Nexthob; // Start on next HOB - } - } while (!Lasthob); - printk(BIOS_DEBUG, "=== End of FSP HOB Data Structure ===\n\n"); -} - - -/** Finds a HOB entry based on type and guid - * - * @param current_hob pointer to the start of the HOB list - * @param guid the GUID of the HOB entry to find - * @return pointer to the start of the requested HOB or NULL if not found. - */ -void *find_hob_by_guid(void *current_hob, EFI_GUID *guid) -{ - do { - switch (((EFI_HOB_GENERIC_HEADER *)current_hob)->HobType) { - - case EFI_HOB_TYPE_MEMORY_ALLOCATION: - if (guids_are_equal(guid, &(((EFI_HOB_MEMORY_ALLOCATION *) \ - current_hob)->AllocDescriptor.Name))) - return current_hob; - break; - case EFI_HOB_TYPE_RESOURCE_DESCRIPTOR: - if (guids_are_equal(guid, - &(((EFI_HOB_RESOURCE_DESCRIPTOR *) \ - current_hob)->Owner))) - return current_hob; - break; - case EFI_HOB_TYPE_GUID_EXTENSION: - if (guids_are_equal(guid, &(((EFI_HOB_GUID_TYPE *) \ - current_hob)->Name))) - return current_hob; - break; - } - - if (!END_OF_HOB_LIST(current_hob)) - current_hob = GET_NEXT_HOB(current_hob); /* Get next HOB pointer */ - } while (!END_OF_HOB_LIST(current_hob)); - - return NULL; -} - -/** Compares a pair of GUIDs to see if they are equal - * - * GUIDs are 128 bits long, so compare them as pairs of quadwords. - * - * @param guid1 pointer to the first of the GUIDs to compare - * @param guid2 pointer to the second of the GUIDs to compare - * @return 1 if the GUIDs were equal, 0 if GUIDs were not equal - */ -uint8_t guids_are_equal(EFI_GUID *guid1, EFI_GUID *guid2) -{ - uint64_t *guid_1 = (void *) guid1; - uint64_t *guid_2 = (void *) guid2; - - if ((*(guid_1) != *(guid_2)) || (*(guid_1 + 1) != *(guid_2 + 1))) - return 0; - - return 1; -} diff --git a/src/security/memory/memory_clear.c b/src/security/memory/memory_clear.c index 45bee91036..255ddccfaa 100644 --- a/src/security/memory/memory_clear.c +++ b/src/security/memory/memory_clear.c @@ -97,12 +97,6 @@ static void clear_memory(void *unused) cbmem_get_region(&baseptr, &size); memranges_insert(&mem, (uintptr_t)baseptr, size, BM_MEM_TABLE); - if (CONFIG(PLATFORM_USES_FSP1_0)) { - /* Protect CBMEM pointer */ - memranges_insert(&mem, CBMEM_FSP_HOB_PTR, sizeof(void *), - BM_MEM_TABLE); - } - if (CONFIG(ARCH_X86)) { /* Find space for PAE enabled memset */ pgtbl = get_free_memory_range(&mem, MEMSET_PAE_PGTL_ALIGN, From 181de282b56be4cf54118d05b319a550bc968f30 Mon Sep 17 00:00:00 2001 From: Elyes HAOUAS Date: Thu, 21 Nov 2019 08:04:38 +0100 Subject: [PATCH 0311/1242] Kconfig: Remove not found sources MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Change-Id: I3691a4162eecbd48321348e136f72b73da74e225 Signed-off-by: Elyes HAOUAS Reviewed-on: https://review.coreboot.org/c/coreboot/+/37078 Reviewed-by: Kyösti Mälkki Reviewed-by: Arthur Heymans Tested-by: build bot (Jenkins) --- src/cpu/intel/Kconfig | 1 - src/soc/intel/Kconfig | 2 -- 2 files changed, 3 deletions(-) diff --git a/src/cpu/intel/Kconfig b/src/cpu/intel/Kconfig index 10fa7019fa..c21de59ba2 100644 --- a/src/cpu/intel/Kconfig +++ b/src/cpu/intel/Kconfig @@ -9,7 +9,6 @@ source src/cpu/intel/model_6fx/Kconfig source src/cpu/intel/model_1067x/Kconfig source src/cpu/intel/model_106cx/Kconfig source src/cpu/intel/model_206ax/Kconfig -source src/cpu/intel/fsp_model_406dx/Kconfig source src/cpu/intel/model_2065x/Kconfig source src/cpu/intel/model_f2x/Kconfig source src/cpu/intel/model_f3x/Kconfig diff --git a/src/soc/intel/Kconfig b/src/soc/intel/Kconfig index b8befc0fd2..1eebeb61fb 100644 --- a/src/soc/intel/Kconfig +++ b/src/soc/intel/Kconfig @@ -5,8 +5,6 @@ source "src/soc/intel/braswell/Kconfig" source "src/soc/intel/broadwell/Kconfig" source "src/soc/intel/cannonlake/Kconfig" source "src/soc/intel/denverton_ns/Kconfig" -source "src/soc/intel/fsp_baytrail/Kconfig" -source "src/soc/intel/fsp_broadwell_de/Kconfig" source "src/soc/intel/quark/Kconfig" source "src/soc/intel/skylake/Kconfig" source "src/soc/intel/icelake/Kconfig" From eef63607b846fbbd94104f3b5e8f1d857d8f4741 Mon Sep 17 00:00:00 2001 From: Arthur Heymans Date: Wed, 20 Nov 2019 23:50:20 +0100 Subject: [PATCH 0312/1242] cpu/x86/lapic/lapic_cpu_init.c: Drop unused guards MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Both model_2065x and model_206ax use the parallel mp init codepath. Change-Id: I6440d413761361ee8b69d5c76b69409bd7528b5d Signed-off-by: Arthur Heymans Reviewed-on: https://review.coreboot.org/c/coreboot/+/37065 Reviewed-by: Kyösti Mälkki Reviewed-by: HAOUAS Elyes Tested-by: build bot (Jenkins) --- src/cpu/x86/lapic/lapic_cpu_init.c | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) diff --git a/src/cpu/x86/lapic/lapic_cpu_init.c b/src/cpu/x86/lapic/lapic_cpu_init.c index e7dfc5798d..ea6a41d670 100644 --- a/src/cpu/x86/lapic/lapic_cpu_init.c +++ b/src/cpu/x86/lapic/lapic_cpu_init.c @@ -142,9 +142,7 @@ static int lapic_start_cpu(unsigned long apicid) } return 0; } -#if !CONFIG(CPU_AMD_MODEL_10XXX) \ - && !CONFIG(CPU_INTEL_MODEL_206AX) \ - && !CONFIG(CPU_INTEL_MODEL_2065X) +#if !CONFIG(CPU_AMD_MODEL_10XXX) mdelay(10); #endif From de56a66e73442d1fb132f466bb556563bee0639d Mon Sep 17 00:00:00 2001 From: Arthur Heymans Date: Tue, 19 Nov 2019 15:51:51 +0100 Subject: [PATCH 0313/1242] cpu/amd/fam10: Drop support MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Relocatable ramstage, postcar stage and C_ENVIRONMENT_BOOTBLOCK are now mandatory features, which this platform lacks. Change-Id: I3c69f158a5667783292161815f9ae61195b5e03b Signed-off-by: Arthur Heymans Reviewed-on: https://review.coreboot.org/c/coreboot/+/36963 Reviewed-by: Kyösti Mälkki Tested-by: build bot (Jenkins) --- src/arch/x86/include/arch/cpu.h | 3 +- src/arch/x86/smbios.c | 10 - src/cpu/amd/Kconfig | 10 - src/cpu/amd/Makefile.inc | 8 - src/cpu/amd/car/cache_as_ram.inc | 648 ------ src/cpu/amd/car/disable_cache_as_ram.c | 106 - src/cpu/amd/car/post_cache_as_ram.c | 135 -- src/cpu/amd/family_10h-family_15h/Kconfig | 90 - .../amd/family_10h-family_15h/Makefile.inc | 25 - src/cpu/amd/family_10h-family_15h/defaults.h | 834 -------- src/cpu/amd/family_10h-family_15h/fidvid.c | 1102 ---------- src/cpu/amd/family_10h-family_15h/init_cpus.c | 1849 ----------------- src/cpu/amd/family_10h-family_15h/init_cpus.h | 50 - .../family_10h-family_15h/model_10xxx_init.c | 268 --- .../family_10h-family_15h/monotonic_timer.c | 91 - .../amd/family_10h-family_15h/powernow_acpi.c | 440 ---- .../family_10h-family_15h/processor_name.c | 353 ---- src/cpu/amd/family_10h-family_15h/ram_calc.c | 94 - src/cpu/amd/family_10h-family_15h/ram_calc.h | 20 - src/cpu/amd/family_10h-family_15h/tsc_freq.c | 36 - .../family_10h-family_15h/update_microcode.c | 70 - src/cpu/amd/quadcore/Makefile.inc | 1 - src/cpu/amd/quadcore/amd_sibling.c | 118 -- src/cpu/amd/quadcore/quadcore.c | 146 -- src/cpu/amd/quadcore/quadcore_id.c | 152 -- src/cpu/amd/socket_AM2r2/Kconfig | 29 - src/cpu/amd/socket_AM2r2/Makefile.inc | 13 - src/cpu/amd/socket_AM3/Kconfig | 29 - src/cpu/amd/socket_AM3/Makefile.inc | 13 - src/cpu/amd/socket_ASB2/Kconfig | 29 - src/cpu/amd/socket_ASB2/Makefile.inc | 13 - src/cpu/amd/socket_C32/Kconfig | 29 - src/cpu/amd/socket_C32/Makefile.inc | 13 - src/cpu/amd/socket_FM2/Kconfig | 29 - src/cpu/amd/socket_FM2/Makefile.inc | 13 - src/cpu/amd/socket_F_1207/Kconfig | 29 - src/cpu/amd/socket_F_1207/Makefile.inc | 13 - src/cpu/amd/socket_G34/Kconfig | 29 - src/cpu/amd/socket_G34/Makefile.inc | 14 - src/cpu/amd/socket_G34/socket_G34.c | 18 - src/cpu/x86/lapic/lapic_cpu_init.c | 2 - 41 files changed, 1 insertion(+), 6973 deletions(-) delete mode 100644 src/cpu/amd/car/cache_as_ram.inc delete mode 100644 src/cpu/amd/car/disable_cache_as_ram.c delete mode 100644 src/cpu/amd/car/post_cache_as_ram.c delete mode 100644 src/cpu/amd/family_10h-family_15h/Kconfig delete mode 100644 src/cpu/amd/family_10h-family_15h/Makefile.inc delete mode 100644 src/cpu/amd/family_10h-family_15h/defaults.h delete mode 100644 src/cpu/amd/family_10h-family_15h/fidvid.c delete mode 100644 src/cpu/amd/family_10h-family_15h/init_cpus.c delete mode 100644 src/cpu/amd/family_10h-family_15h/init_cpus.h delete mode 100644 src/cpu/amd/family_10h-family_15h/model_10xxx_init.c delete mode 100644 src/cpu/amd/family_10h-family_15h/monotonic_timer.c delete mode 100644 src/cpu/amd/family_10h-family_15h/powernow_acpi.c delete mode 100644 src/cpu/amd/family_10h-family_15h/processor_name.c delete mode 100644 src/cpu/amd/family_10h-family_15h/ram_calc.c delete mode 100644 src/cpu/amd/family_10h-family_15h/ram_calc.h delete mode 100644 src/cpu/amd/family_10h-family_15h/tsc_freq.c delete mode 100644 src/cpu/amd/family_10h-family_15h/update_microcode.c delete mode 100644 src/cpu/amd/quadcore/Makefile.inc delete mode 100644 src/cpu/amd/quadcore/amd_sibling.c delete mode 100644 src/cpu/amd/quadcore/quadcore.c delete mode 100644 src/cpu/amd/quadcore/quadcore_id.c delete mode 100644 src/cpu/amd/socket_AM2r2/Kconfig delete mode 100644 src/cpu/amd/socket_AM2r2/Makefile.inc delete mode 100644 src/cpu/amd/socket_AM3/Kconfig delete mode 100644 src/cpu/amd/socket_AM3/Makefile.inc delete mode 100644 src/cpu/amd/socket_ASB2/Kconfig delete mode 100644 src/cpu/amd/socket_ASB2/Makefile.inc delete mode 100644 src/cpu/amd/socket_C32/Kconfig delete mode 100644 src/cpu/amd/socket_C32/Makefile.inc delete mode 100644 src/cpu/amd/socket_FM2/Kconfig delete mode 100644 src/cpu/amd/socket_FM2/Makefile.inc delete mode 100644 src/cpu/amd/socket_F_1207/Kconfig delete mode 100644 src/cpu/amd/socket_F_1207/Makefile.inc delete mode 100644 src/cpu/amd/socket_G34/Kconfig delete mode 100644 src/cpu/amd/socket_G34/Makefile.inc delete mode 100644 src/cpu/amd/socket_G34/socket_G34.c diff --git a/src/arch/x86/include/arch/cpu.h b/src/arch/x86/include/arch/cpu.h index d74d6de7b5..e0e3ca1972 100644 --- a/src/arch/x86/include/arch/cpu.h +++ b/src/arch/x86/include/arch/cpu.h @@ -210,8 +210,7 @@ int cpu_have_cpuid(void); static inline bool cpu_is_amd(void) { - return CONFIG(CPU_AMD_AGESA) || CONFIG(CPU_AMD_PI) - || CONFIG(SOC_AMD_COMMON) || CONFIG(CPU_AMD_MODEL_10XXX); + return CONFIG(CPU_AMD_AGESA) || CONFIG(CPU_AMD_PI) || CONFIG(SOC_AMD_COMMON); } static inline bool cpu_is_intel(void) diff --git a/src/arch/x86/smbios.c b/src/arch/x86/smbios.c index 725d808d56..7e05408242 100644 --- a/src/arch/x86/smbios.c +++ b/src/arch/x86/smbios.c @@ -545,16 +545,6 @@ static int get_socket_type(void) return 0x13; if (CONFIG(CPU_INTEL_SOCKET_LGA775)) return 0x15; - if (CONFIG(CPU_AMD_SOCKET_AM2R2)) - return 0x17; - if (CONFIG(CPU_AMD_SOCKET_F_1207)) - return 0x18; - if (CONFIG(CPU_AMD_SOCKET_G34_NON_AGESA)) - return 0x1a; - if (CONFIG(CPU_AMD_SOCKET_AM3)) - return 0x1b; - if (CONFIG(CPU_AMD_SOCKET_C32_NON_AGESA)) - return 0x1c; return 0x02; /* Unknown */ } diff --git a/src/cpu/amd/Kconfig b/src/cpu/amd/Kconfig index 7a6d9568ce..4ade0f678e 100644 --- a/src/cpu/amd/Kconfig +++ b/src/cpu/amd/Kconfig @@ -1,12 +1,2 @@ -source src/cpu/amd/socket_AM2r2/Kconfig -source src/cpu/amd/socket_AM3/Kconfig -source src/cpu/amd/socket_C32/Kconfig -source src/cpu/amd/socket_FM2/Kconfig -source src/cpu/amd/socket_G34/Kconfig -source src/cpu/amd/socket_ASB2/Kconfig -source src/cpu/amd/socket_F_1207/Kconfig - -source src/cpu/amd/family_10h-family_15h/Kconfig - source src/cpu/amd/agesa/Kconfig source src/cpu/amd/pi/Kconfig diff --git a/src/cpu/amd/Makefile.inc b/src/cpu/amd/Makefile.inc index 72c6aa2696..5c07a665cc 100644 --- a/src/cpu/amd/Makefile.inc +++ b/src/cpu/amd/Makefile.inc @@ -1,10 +1,2 @@ -subdirs-$(CONFIG_CPU_AMD_SOCKET_F_1207) += socket_F_1207 -subdirs-$(CONFIG_CPU_AMD_SOCKET_AM2R2) += socket_AM2r2 -subdirs-$(CONFIG_CPU_AMD_SOCKET_AM3) += socket_AM3 -subdirs-$(CONFIG_CPU_AMD_SOCKET_ASB2) += socket_ASB2 -subdirs-$(CONFIG_CPU_AMD_SOCKET_C32_NON_AGESA) += socket_C32 -subdirs-$(CONFIG_CPU_AMD_SOCKET_FM2_NON_AGESA) += socket_FM2 -subdirs-$(CONFIG_CPU_AMD_SOCKET_G34_NON_AGESA) += socket_G34 - subdirs-$(CONFIG_CPU_AMD_AGESA) += agesa subdirs-$(CONFIG_CPU_AMD_PI) += pi diff --git a/src/cpu/amd/car/cache_as_ram.inc b/src/cpu/amd/car/cache_as_ram.inc deleted file mode 100644 index 2054ea3438..0000000000 --- a/src/cpu/amd/car/cache_as_ram.inc +++ /dev/null @@ -1,648 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include -#include - -#define CacheSize CONFIG_DCACHE_RAM_SIZE -#define CacheBase CONFIG_DCACHE_RAM_BASE -#define CacheSizeBSPStack CONFIG_DCACHE_BSP_TOP_STACK_SIZE -#define CacheSizeBSPSlush CONFIG_DCACHE_BSP_TOP_STACK_SLUSH - -/* For CAR with Fam10h. */ -#define CacheSizeAPStack CONFIG_DCACHE_AP_STACK_SIZE - -#define jmp_if_not_k8(x) comisd %xmm2, %xmm1; jae x -#define jmp_if_k8(x) comisd %xmm2, %xmm1; jb x -#define jmp_if_not_fam15h(x) comisd %xmm3, %xmm1; jb x -#define jmp_if_fam15h(x) comisd %xmm3, %xmm1; jae x - -#define CPUID_MASK 0x0ff00f00 -#define CPUID_VAL_FAM10_ROTATED 0x0f000010 -#define CPUID_VAL_FAM15_ROTATED 0x0f000060 - -/* - * XMM map: - * xmm1: CPU family - * xmm2: Fam10h comparison value - * xmm3: Fam15h comparison value - * xmm4: Backup EBX - * xmm5: coreboot init detect - */ - - /* Save the BIST result. */ - movl %eax, %ebp - - /* - * For normal part %ebx already contain cpu_init_detected - * from fallback call. - */ - -cache_as_ram_setup: - post_code(0xa0) - - /* Enable SSE. */ - movl %cr4, %eax - orl $(3 << 9), %eax - movl %eax, %cr4 - - /* Figure out the CPU family. */ - cvtsi2sd %ebx, %xmm4 - movl $0x01, %eax - cpuid - /* Base family is bits 8..11, extended family is bits 20..27. */ - andl $CPUID_MASK, %eax - /* Reorder bits for easier comparison by value. */ - roll $0x10, %eax - cvtsi2sd %eax, %xmm1 - movl $CPUID_VAL_FAM10_ROTATED, %eax - cvtsi2sd %eax, %xmm2 - movl $CPUID_VAL_FAM15_ROTATED, %eax - cvtsi2sd %eax, %xmm3 - cvtsd2si %xmm4, %ebx - - /* Check if cpu_init_detected. */ - movl $MTRR_DEF_TYPE_MSR, %ecx - rdmsr - andl $MTRR_DEF_TYPE_EN, %eax - movl %eax, %ebx /* We store the status. */ - cvtsi2sd %ebx, %xmm5 - - jmp_if_k8(CAR_FAM10_out_post_errata) - - /* - * For GH, CAR need to set DRAM Base/Limit registers to direct that - * to node0. - * Only BSP needed, for other nodes set during HT/memory init. - * So we need to check if it is BSP. - */ - movl $0x1b, %ecx - rdmsr - bt $8, %eax /* BSP */ - jnc CAR_FAM10_out - - /* Enable RT tables on BSP. */ - movl $0x8000c06c, %eax - movw $0xcf8, %dx - outl %eax, %dx - addw $4, %dx - inl %dx, %eax - btr $0, %eax - outl %eax, %dx - - /* Setup temporary DRAM map: [0,16M) bit 0-23. */ - movl $0x8000c144, %eax - movw $0xcf8, %dx - outl %eax, %dx - addw $4, %dx - movl $0, %eax - outl %eax, %dx - - movl $0x8000c140, %eax - movw $0xcf8, %dx - outl %eax, %dx - addw $4, %dx - movl $3, %eax - outl %eax, %dx - -CAR_FAM10_out: - - jmp_if_fam15h(CAR_FAM10_errata_applied) - /* - * Errata 193: Disable clean copybacks to L3 cache to allow cached ROM. - * Re-enable it in after RAM is initialized and before CAR is disabled. - */ - movl $BU_CFG2_MSR, %ecx - rdmsr - bts $15, %eax /* Set bit 15 in EDX:EAX (bit 15 in EAX). */ - wrmsr - - /* Erratum 343, RevGuide for Fam10h, Pub#41322 Rev. 3.33 */ - movl $BU_CFG2_MSR, %ecx - rdmsr - bts $35-32, %edx /* Set bit 35 in EDX:EAX (bit 3 in EDX). */ - wrmsr - -CAR_FAM10_errata_applied: - -#if CONFIG(MMCONF_SUPPORT) - #if (CONFIG_MMCONF_BASE_ADDRESS > 0xFFFFFFFF) - #error "MMCONF_BASE_ADDRESS too big" - #elif (CONFIG_MMCONF_BASE_ADDRESS & 0xFFFFF) - #error "MMCONF_BASE_ADDRESS not 1MB aligned" - #endif - movl $0, %edx - movl $((CONFIG_MMCONF_BASE_ADDRESS) | (1 << 0)), %eax - #if (CONFIG_MMCONF_BUS_NUMBER == 1) - #elif (CONFIG_MMCONF_BUS_NUMBER == 2) - orl $(1 << 2), %eax - #elif (CONFIG_MMCONF_BUS_NUMBER == 4) - orl $(2 << 2), %eax - #elif (CONFIG_MMCONF_BUS_NUMBER == 8) - orl $(3 << 2), %eax - #elif (CONFIG_MMCONF_BUS_NUMBER == 16) - orl $(4 << 2), %eax - #elif (CONFIG_MMCONF_BUS_NUMBER == 32) - orl $(5 << 2), %eax - #elif (CONFIG_MMCONF_BUS_NUMBER == 64) - orl $(6 << 2), %eax - #elif (CONFIG_MMCONF_BUS_NUMBER == 128) - orl $(7 << 2), %eax - #elif (CONFIG_MMCONF_BUS_NUMBER == 256) - orl $(8 << 2), %eax - #else - #error "bad MMCONF_BUS_NUMBER value" - #endif - movl $MMIO_CONF_BASE, %ecx - wrmsr -#endif - -CAR_FAM10_out_post_errata: - - /* Fam15h APIC IDs do not depend on NB config bit 54 */ - jmp_if_not_fam15h(skip_nb54_set) - movl $NB_CFG_MSR, %ecx - rdmsr - bts $(54 - 32), %edx /* Set NB config bit 54 */ - wrmsr - -skip_nb54_set: - /* On Fam15h CPUs each compute unit's MTRRs are shared between two cores */ - jmp_if_not_fam15h(skip_cu_check) - - /* Get the initial APIC ID. */ - movl $1, %eax - cpuid - movl %ebx, %eax - - /* Restore init detect */ - cvtsd2si %xmm5, %ebx - - /* Determine if this is the second core to start in a compute unit; if so, wait for first core start, clear init detect and skip MTRR init */ - bt $24, %eax - jnc skip_cu_check /* First core in the compute unit jumps to skip_cu_check */ - - /* Determine if this is the second core to start in a compute unit; if so, clear init detect and skip MTRR init */ - /* Busywait until the first core sets up the MTRRs */ -check_init_detect_1: - /* Check if cpu_init_detected. */ - movl $MTRR_DEF_TYPE_MSR, %ecx - rdmsr - andl $MTRR_DEF_TYPE_EN, %eax - cmp $0x00000000, %eax - je check_init_detect_1 /* First core has not yet started */ - -check_init_detect_2: - movl $SYSCFG_MSR, %ecx - rdmsr - andl $(SYSCFG_MSR_MtrrFixDramEn | SYSCFG_MSR_MtrrVarDramEn), %eax - cmp $0x00000000, %eax - je check_init_detect_2 /* First core has not yet started */ - - /* First core has now started */ - movl $0x00000000, %ebx /* Clear init detect flag */ - cvtsi2sd %ebx, %xmm5 - jmp fam10_mtrr_setup_complete - -skip_cu_check: - - jmp_if_not_fam15h(CAR_FAM15_errata_applied) - - /* Erratum 714, RevGuide for Fam15h, Pub#48063 Rev. 3.24 */ - movl $BU_CFG2_MSR, %ecx - rdmsr - bts $8, %eax /* Set bit 8 in EDX:EAX (bit 8 in EAX). */ - wrmsr - -CAR_FAM15_errata_applied: - - /* Set MtrrFixDramModEn for clear fixed MTRR. */ -enable_fixed_mtrr_dram_modify: - movl $SYSCFG_MSR, %ecx - rdmsr - andl $(~(SYSCFG_MSR_MtrrFixDramEn | SYSCFG_MSR_MtrrVarDramEn)), %eax - orl $SYSCFG_MSR_MtrrFixDramModEn, %eax - wrmsr - - /* Clear all MTRRs. */ - xorl %edx, %edx - movl $all_mtrr_msrs, %esi - -clear_fixed_var_mtrr: - lodsl (%esi), %eax - testl %eax, %eax - jz clear_fixed_var_mtrr_out - - movl %eax, %ecx - xorl %eax, %eax - wrmsr - - jmp clear_fixed_var_mtrr -clear_fixed_var_mtrr_out: - -/* - * 0x06 is the WB IO type for a given 4k segment. - * 0x1e is the MEM IO type for a given 4k segment (K10 and above). - * segs is the number of 4k segments in the area of the particular - * register we want to use for CAR. - * reg is the register where the IO type should be stored. - */ -.macro extractmask segs, reg -.if \segs <= 0 - /* - * The xorl here is superfluous because at the point of first execution - * of this macro, %eax and %edx are cleared. Later invocations of this - * macro will have a monotonically increasing segs parameter. - */ - xorl \reg, \reg -.else - jmp_if_k8(1f) - -.if \segs == 1 - movl $0x1e000000, \reg /* WB MEM type */ -.elseif \segs == 2 - movl $0x1e1e0000, \reg /* WB MEM type */ -.elseif \segs == 3 - movl $0x1e1e1e00, \reg /* WB MEM type */ -.elseif \segs >= 4 - movl $0x1e1e1e1e, \reg /* WB MEM type */ -.endif - jmp 2f -1: -.if \segs == 1 - movl $0x06000000, \reg /* WB IO type */ -.elseif \segs == 2 - movl $0x06060000, \reg /* WB IO type */ -.elseif \segs == 3 - movl $0x06060600, \reg /* WB IO type */ -.elseif \segs >= 4 - movl $0x06060606, \reg /* WB IO type */ -.endif -2: -.endif /* if \segs <= 0 */ -.endm - -/* - * carsize is the cache size in bytes we want to use for CAR. - * windowoffset is the 32k-aligned window into CAR size. - */ -.macro simplemask carsize, windowoffset - .set gas_bug_workaround,(((\carsize - \windowoffset) >> 12) - 4) - extractmask gas_bug_workaround, %eax - .set gas_bug_workaround,(((\carsize - \windowoffset) >> 12)) - extractmask gas_bug_workaround, %edx - /* - * Without the gas bug workaround, the entire macro would consist - * only of the two lines below: - * extractmask (((\carsize - \windowoffset) >> 12) - 4), %eax - * extractmask (((\carsize - \windowoffset) >> 12)), %edx - */ -.endm - -#if CONFIG(CPU_AMD_MODEL_10XXX) - #if CacheSize > 0x80000 - #error Invalid CAR size, must be at most 128k (processor limit is 512k). - #endif -#else - #if CacheSize > 0x10000 - #error Invalid CAR size, must be at most 64k. - #endif -#endif -#if CacheSize < 0x1000 -#error Invalid CAR size, must be at least 4k. This is a processor limitation. -#endif -#if (CacheSize & (0x1000 - 1)) -#error Invalid CAR size, is not a multiple of 4k. This is a processor limitation. -#endif - -#if CacheSize > 0x8000 - /* Enable caching for 32K-64K using fixed MTRR. */ - movl $MTRR_FIX_4K_C0000, %ecx - simplemask CacheSize, 0x8000 - wrmsr -#endif - -#if CacheSize > 0x10000 - /* Enable caching for 64K-96K using fixed MTRR. */ - movl $MTRR_FIX_4K_D0000, %ecx - simplemask CacheSize, 0x10000 - wrmsr -#endif - -#if CacheSize > 0x18000 - /* Enable caching for 96K-128K using fixed MTRR. */ - movl $MTRR_FIX_4K_D8000, %ecx - simplemask CacheSize, 0x18000 - wrmsr -#endif - - /* Enable caching for 0-32K using fixed MTRR. */ - movl $MTRR_FIX_4K_C8000, %ecx - simplemask CacheSize, 0 - wrmsr - - jmp_if_fam15h(fam15_skip_dram_mtrr_setup) - - /* Enable memory access for first MBs using top_mem. */ - movl $TOP_MEM, %ecx - xorl %edx, %edx - movl $(((CONFIG_RAMTOP) + TOP_MEM_MASK) & ~TOP_MEM_MASK) , %eax - wrmsr - -fam15_skip_dram_mtrr_setup: - -#if CONFIG_XIP_ROM_SIZE - - /* Enable write base caching so we can do execute in place (XIP) - * on the flash ROM. - */ - movl $MTRR_PHYS_BASE(1), %ecx - xorl %edx, %edx - /* - * IMPORTANT: The following calculation _must_ be done at runtime. See - * https://mail.coreboot.org/pipermail/coreboot/2010-October/060922.html - */ - movl $_program, %eax - andl $(~(CONFIG_XIP_ROM_SIZE - 1)), %eax - orl $MTRR_TYPE_WRBACK, %eax - wrmsr - - movl $MTRR_PHYS_MASK(1), %ecx - movl $0xff, %edx /* (1 << (CONFIG_CPU_ADDR_BITS - 32)) - 1 for K8 (CONFIG_CPU_ADDR_BITS = 40) */ - jmp_if_k8(wbcache_post_fam10_setup) - movl $0xffff, %edx /* (1 << (CONFIG_CPU_ADDR_BITS - 32)) - 1 for FAM10 (CONFIG_CPU_ADDR_BITS = 48) */ -wbcache_post_fam10_setup: - movl $(~(CONFIG_XIP_ROM_SIZE - 1) | MTRR_PHYS_MASK_VALID), %eax - wrmsr -#endif /* CONFIG_XIP_ROM_SIZE */ - - /* Set the default memory type and enable fixed and variable MTRRs. */ - movl $MTRR_DEF_TYPE_MSR, %ecx - xorl %edx, %edx - movl $(MTRR_DEF_TYPE_EN | MTRR_DEF_TYPE_FIX_EN), %eax - wrmsr - - /* Enable the MTRRs and IORRs in SYSCFG. */ - movl $SYSCFG_MSR, %ecx - rdmsr - orl $(SYSCFG_MSR_MtrrVarDramEn | SYSCFG_MSR_MtrrFixDramEn), %eax - wrmsr - -fam10_mtrr_setup_complete: - post_code(0xa1) - - /* Disable conversion of INVD to WBINVD (INVDWBINVD = 0) */ - mov $HWCR_MSR, %ecx - rdmsr - btr $4, %eax - wrmsr - -jmp_if_not_fam15h(fam15_car_msr_setup_complete) - /* Disable streaming store (DisSS = 1) */ - mov $LS_CFG_MSR, %ecx - rdmsr - bts $28, %eax - wrmsr - - /* Disable speculative ITLB reloads (DisSpecTlbRld = 1) */ - mov $IC_CFG_MSR, %ecx - rdmsr - bts $9, %eax - wrmsr - - /* Disable speculative DTLB reloads (DisSpecTlbRld = 1) and set DisHwPf = 1 */ - mov $DC_CFG_MSR, %ecx - rdmsr - bts $4, %eax - bts $13, %eax - wrmsr - - /* Disable CR0 combining (CombineCr0Cd = 0) */ - mov $BU_CFG3_MSR, %ecx - rdmsr - btr $49-32, %edx - wrmsr -fam15_car_msr_setup_complete: - - /* Enable cache. */ - movl %cr0, %eax - andl $(~(CR0_CacheDisable | CR0_NoWriteThrough)), %eax - movl %eax, %cr0 - - jmp_if_not_k8(CAR_skip_k8_errata_part1) - - /* Set DisFillP on BSP. */ - movl $0x8000c068, %eax - movw $0xcf8, %dx - outl %eax, %dx - addw $4, %dx - inl %dx, %eax - bts $10, %eax - outl %eax, %dx - -CAR_skip_k8_errata_part1: - - jmp_if_k8(fam10_end_part1) - - /* So we need to check if it is BSP. */ - movl $0x1b, %ecx - rdmsr - bt $8, %eax /* BSP */ - jnc CAR_FAM10_ap -fam10_end_part1: - - post_code(0xa2) - - /* Read the range with lodsl. */ - cld - movl $CacheBase, %esi - movl $(CacheSize >> 2), %ecx - rep lodsl - - /* Clear the range. */ - movl $CacheBase, %edi - movl $(CacheSize >> 2), %ecx - xorl %eax, %eax - rep stosl - - jmp_if_not_k8(CAR_skip_k8_errata_part2) - - /* Clear DisFillP on BSP. */ - movl $0x8000c068, %eax - movw $0xcf8, %dx - outl %eax, %dx - addw $4, %dx - inl %dx, %eax - btr $10, %eax - outl %eax, %dx - -CAR_skip_k8_errata_part2: - - /* Set up the stack pointer. */ - movl $(CacheBase + CacheSize), %eax - movl %eax, %esp - - /* Poison the lower stack boundary */ - movl $((CacheBase + CacheSize) - CacheSizeBSPStack), %eax - movl $0xdeadbeef, (%eax) - - post_code(0xa3) - - jmp CAR_FAM10_ap_out -CAR_FAM10_ap: - /* - * Need to set stack pointer for AP. - * It will be from: - * CacheBase + (CacheSize - (CacheSizeBSPStack + CacheSizeBSPSlush)) - * - (NodeID << CoreIDbits + CoreID) * CacheSizeAPStack - * The spacing between the BSP stack and the top of the AP - * stacks is purposefully set larger (an extra CacheSizeBSPSlush - * worth of unused space) than necessary to aid debugging when - * additional stack variables are added by future developers. - * The extra space will allow BSP overruns to be caught by - * the warning logic and easily fixed instead of crashing the - * system with no obvious clues of what went wrong. - * - * So, need to get the NodeID and CoreID at first. - * If NB_CFG_MSR bit 54 is set just use initial APIC ID, otherwise need - * to reverse it. - */ - - /* Get the coreid bits at first. */ - movl $0x80000008, %eax - cpuid - shrl $12, %ecx - andl $0x0f, %ecx - movl %ecx, %edi - - /* Get the initial APIC ID. */ - movl $1, %eax - cpuid - shrl $24, %ebx - - /* Get the nb cfg bit 54. */ - movl $NB_CFG_MSR, %ecx - rdmsr - movl %edi, %ecx /* CoreID bits */ - bt $(54 - 32), %edx - jc roll_cfg - - /* Fam10h NB config bit 54 was not set */ - rolb %cl, %bl -roll_cfg: - jmp_if_not_fam15h(ap_apicid_ready) - cmp $0x5, %ecx - jne ap_apicid_ready - - /* This is a multi-node CPU - * Adjust the maximum APIC ID to a more reasonable value - * given that no 32-core Family 15h processors exist - */ - movl %ebx, %ecx - and $0x0f, %ecx /* Get lower 4 bits of CPU number */ - and $0x60, %ebx /* Get node ID */ - shrl $0x1, %ebx /* Shift node ID part of APIC ID down by 1 */ - or %ecx, %ebx /* Recombine node ID and CPU number */ - -ap_apicid_ready: - - /* Calculate stack pointer using adjusted APIC ID stored in ebx */ - movl $CacheSizeAPStack, %eax - mull %ebx - movl $(CacheBase + (CacheSize - (CacheSizeBSPStack + CacheSizeBSPSlush))), %esp - subl %eax, %esp - - /* Restore init detect */ - cvtsd2si %xmm5, %ebx - - post_code(0xa4) - -CAR_FAM10_ap_out: - - post_code(0xa5) - - /* Disable SSE. */ - movl %cr4, %eax - andl $~(3 << 9), %eax - movl %eax, %cr4 - - post_code(0xa6) - - /* Restore the BIST result. */ - movl %ebp, %eax - - /* We need to set EBP? No need. */ - movl %esp, %ebp - pushl %ebx /* Init detected. */ - pushl %eax /* BIST */ - - post_code(0xa7) - - call cache_as_ram_main - - call post_cache_as_ram - movl %eax, %esp - - call cache_as_ram_new_stack - - /* We will not go back. */ - - post_code(0xaf) /* Should never see this POST code. */ - -all_mtrr_msrs: - /* fixed MTRR MSRs */ - .long MTRR_FIX_64K_00000 - .long MTRR_FIX_16K_80000 - .long MTRR_FIX_16K_A0000 - .long MTRR_FIX_4K_C0000 - .long MTRR_FIX_4K_C8000 - .long MTRR_FIX_4K_D0000 - .long MTRR_FIX_4K_D8000 - .long MTRR_FIX_4K_E0000 - .long MTRR_FIX_4K_E8000 - .long MTRR_FIX_4K_F0000 - .long MTRR_FIX_4K_F8000 - - /* var MTRR MSRs */ - .long MTRR_PHYS_BASE(0) - .long MTRR_PHYS_MASK(0) - .long MTRR_PHYS_BASE(1) - .long MTRR_PHYS_MASK(1) - .long MTRR_PHYS_BASE(2) - .long MTRR_PHYS_MASK(2) - .long MTRR_PHYS_BASE(3) - .long MTRR_PHYS_MASK(3) - .long MTRR_PHYS_BASE(4) - .long MTRR_PHYS_MASK(4) - .long MTRR_PHYS_BASE(5) - .long MTRR_PHYS_MASK(5) - .long MTRR_PHYS_BASE(6) - .long MTRR_PHYS_MASK(6) - .long MTRR_PHYS_BASE(7) - .long MTRR_PHYS_MASK(7) - - /* Variable IORR MTRR MSRs */ - .long IORRBase_MSR(0) - .long IORRMask_MSR(0) - .long IORRBase_MSR(1) - .long IORRMask_MSR(1) - - /* Top of memory MTRR MSRs */ - .long TOP_MEM - .long TOP_MEM2 - - .long 0x000 /* NULL, end of table */ - -cache_as_ram_setup_out: diff --git a/src/cpu/amd/car/disable_cache_as_ram.c b/src/cpu/amd/car/disable_cache_as_ram.c deleted file mode 100644 index fb632bb644..0000000000 --- a/src/cpu/amd/car/disable_cache_as_ram.c +++ /dev/null @@ -1,106 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * WARNING: this file will be used by both any AP cores and core 0 / node 0 - */ - -#include -#include -#include -#include - -static __always_inline uint32_t amd_fam1x_cpu_family(void) -{ - uint32_t family; - - family = cpuid_eax(0x80000001); - family = ((family & 0xf00000) >> 16) | ((family & 0xf00) >> 8); - - return family; -} - -static __always_inline -void disable_cache_as_ram_real(uint8_t skip_sharedc_config) -{ - msr_t msr; - uint32_t family; - - if (!skip_sharedc_config) { - /* disable cache */ - write_cr0(read_cr0() | CR0_CacheDisable); - - msr.lo = 0; - msr.hi = 0; - wrmsr(MTRR_FIX_4K_C8000, msr); - if (CONFIG_DCACHE_RAM_SIZE > 0x8000) - wrmsr(MTRR_FIX_4K_C0000, msr); - if (CONFIG_DCACHE_RAM_SIZE > 0x10000) - wrmsr(MTRR_FIX_4K_D0000, msr); - if (CONFIG_DCACHE_RAM_SIZE > 0x18000) - wrmsr(MTRR_FIX_4K_D8000, msr); - - /* disable fixed mtrr from now on, - * it will be enabled by ramstage again - */ - msr = rdmsr(SYSCFG_MSR); - msr.lo &= ~(SYSCFG_MSR_MtrrFixDramEn - | SYSCFG_MSR_MtrrFixDramModEn); - wrmsr(SYSCFG_MSR, msr); - - /* Set the default memory type and - * disable fixed and enable variable MTRRs - */ - msr.hi = 0; - msr.lo = (1 << 11); - - wrmsr(MTRR_DEF_TYPE_MSR, msr); - - enable_cache(); - } - - /* INVDWBINVD = 1 */ - msr = rdmsr(HWCR_MSR); - msr.lo |= (0x1 << 4); - wrmsr(HWCR_MSR, msr); - - family = amd_fam1x_cpu_family(); - -#if CONFIG(CPU_AMD_MODEL_10XXX) - if (family >= 0x6f) { - /* Family 15h or later */ - - /* DisSS = 0 */ - msr = rdmsr(LS_CFG_MSR); - msr.lo &= ~(0x1 << 28); - wrmsr(LS_CFG_MSR, msr); - - if (!skip_sharedc_config) { - /* DisSpecTlbRld = 0 */ - msr = rdmsr(IC_CFG_MSR); - msr.lo &= ~(0x1 << 9); - wrmsr(IC_CFG_MSR, msr); - - /* Erratum 714: SpecNbReqDis = 0 */ - msr = rdmsr(BU_CFG2_MSR); - msr.lo &= ~(0x1 << 8); - wrmsr(BU_CFG2_MSR, msr); - } - - /* DisSpecTlbRld = 0 */ - /* DisHwPf = 0 */ - msr = rdmsr(DC_CFG_MSR); - msr.lo &= ~(0x1 << 4); - msr.lo &= ~(0x1 << 13); - wrmsr(DC_CFG_MSR, msr); - } -#endif -} diff --git a/src/cpu/amd/car/post_cache_as_ram.c b/src/cpu/amd/car/post_cache_as_ram.c deleted file mode 100644 index 78e417fc13..0000000000 --- a/src/cpu/amd/car/post_cache_as_ram.c +++ /dev/null @@ -1,135 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include "cpu/amd/car/disable_cache_as_ram.c" - -// For set_sysinfo_in_ram() -#include - -#if CONFIG_RAMTOP <= 0x100000 - #error "You need to set CONFIG_RAMTOP greater than 1M" -#endif - -#if CONFIG(DEBUG_CAR) -#define print_car_debug(format, arg...) printk(BIOS_DEBUG, "%s: " format, __func__, ##arg) -#else -#define print_car_debug(format, arg...) -#endif - -static void memcpy_(void *d, const void *s, size_t len) -{ - print_car_debug(" Copy [%08x-%08x] to [%08x - %08x] ...", - (uint32_t) s, (uint32_t) (s + len - 1), - (uint32_t) d, (uint32_t) (d + len - 1)); - memcpy(d, s, len); -} - -static int memcmp_(void *d, const void *s, size_t len) -{ - print_car_debug(" Compare [%08x-%08x] with [%08x - %08x] ...", - (uint32_t) s, (uint32_t) (s + len - 1), - (uint32_t) d, (uint32_t) (d + len - 1)); - return memcmp(d, s, len); -} - -/* Disable Erratum 343 Workaround, see RevGuide for Fam10h, Pub#41322 Rev 3.33 - * and RevGuide for Fam12h, Pub#44739 Rev 3.10 - */ - -static void vErrata343(void) -{ - msr_t msr; - unsigned int uiMask = 0xFFFFFFF7; - - msr = rdmsr(BU_CFG2_MSR); - msr.hi &= uiMask; // IcDisSpecTlbWr (bit 35) = 0 - wrmsr(BU_CFG2_MSR, msr); -} - -asmlinkage void *post_cache_as_ram(void) -{ - uint32_t family = amd_fam1x_cpu_family(); - int s3resume = 0; - - /* Verify that the BSP didn't overrun the lower stack - * boundary during romstage execution - */ - volatile uint32_t *lower_stack_boundary; - lower_stack_boundary = (void *)((CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE) - - CONFIG_DCACHE_BSP_TOP_STACK_SIZE); - - if ((*lower_stack_boundary) != 0xdeadbeef) - printk(BIOS_WARNING, "BSP overran lower stack boundary. Undefined behaviour may result!\n"); - - - /* ACPI S3 is not supported without RELOCATABLE_RAMSTAGE and - * this will always return 0. */ - s3resume = acpi_is_wakeup_s3(); - - romstage_handoff_init(s3resume); - - /* from here don't store more data in CAR */ - if (family >= 0x1f && family <= 0x3f) { - /* Family 10h and 12h, 11h until shown otherwise */ - vErrata343(); - } - - size_t car_size = car_data_size(); - void *migrated_car = (void *)(CONFIG_RAMTOP - car_size); - - print_car_debug("Copying data from cache to RAM..."); - memcpy_(migrated_car, _car_global_start, car_size); - print_car_debug(" Done\n"); - - print_car_debug("Verifying data integrity in RAM..."); - if (memcmp_(migrated_car, _car_global_start, car_size) == 0) - print_car_debug(" Done\n"); - else - print_car_debug(" FAILED\n"); - - /* New stack grows right below migrated_car. */ - print_car_debug("Switching to use RAM as stack..."); - return migrated_car; -} - -asmlinkage void cache_as_ram_new_stack(void) -{ - print_car_debug("Disabling cache as RAM now\n"); - disable_cache_as_ram_real(0); // inline - - disable_cache(); - /* Enable cached access to RAM in the range 0M to CACHE_TMP_RAMTOP */ - set_var_mtrr(0, 0x00000000, CACHE_TMP_RAMTOP, MTRR_TYPE_WRBACK); - enable_cache(); - - set_sysinfo_in_ram(1); // So other core0 could start to train mem - - /*copy and execute ramstage */ - copy_and_run(); - /* We will not return */ - - print_car_debug("should not be here -\n"); -} diff --git a/src/cpu/amd/family_10h-family_15h/Kconfig b/src/cpu/amd/family_10h-family_15h/Kconfig deleted file mode 100644 index ad4f5f4ba6..0000000000 --- a/src/cpu/amd/family_10h-family_15h/Kconfig +++ /dev/null @@ -1,90 +0,0 @@ -config CPU_AMD_MODEL_10XXX - bool - select ARCH_BOOTBLOCK_X86_32 - select ARCH_VERSTAGE_X86_32 - select ARCH_ROMSTAGE_X86_32 - select ARCH_RAMSTAGE_X86_32 - select SSE2 - select TSC_SYNC_LFENCE - select UDELAY_LAPIC - select SUPPORT_CPU_UCODE_IN_CBFS - select CPU_MICROCODE_MULTIPLE_FILES - select CAR_GLOBAL_MIGRATION - -if CPU_AMD_MODEL_10XXX - -config USE_LARGE_DCACHE - bool - default y if CPU_AMD_SOCKET_G34_NON_AGESA - default y if CPU_AMD_SOCKET_FM2_NON_AGESA - default y if CPU_AMD_SOCKET_C32_NON_AGESA - default n - -config NUM_IPI_STARTS - int - default 1 - -config CPU_ADDR_BITS - int - default 48 - -config DCACHE_RAM_BASE - hex - default 0xc4000 - -config DCACHE_RAM_SIZE - hex - default 0x0c000 - -config DCACHE_BSP_TOP_STACK_SIZE - hex - default 0x4000 - -config DCACHE_BSP_TOP_STACK_SLUSH - hex - default 0x4000 if USE_LARGE_DCACHE - default 0x1000 - -config DCACHE_AP_STACK_SIZE - hex - default 0x500 - -config SET_FIDVID - bool - default y - -config MAX_PHYSICAL_CPUS - int - default 1 - -config LIFT_BSP_APIC_ID - bool - default n - -if SET_FIDVID -config SET_FIDVID_DEBUG - bool - default y - -config SET_FIDVID_STORE_AP_APICID_AT_FIRST - bool - default y - -config SET_FIDVID_CORE0_ONLY - bool - default n - -# 0: all cores -# 1: core 0 only -# 2: all but core 0 -config SET_FIDVID_CORE_RANGE - int - default 0 - -endif # SET_FIDVID - -config UDELAY_LAPIC_FIXED_FSB - int - default 200 - -endif # CPU_AMD_MODEL_10XXX diff --git a/src/cpu/amd/family_10h-family_15h/Makefile.inc b/src/cpu/amd/family_10h-family_15h/Makefile.inc deleted file mode 100644 index 7035323026..0000000000 --- a/src/cpu/amd/family_10h-family_15h/Makefile.inc +++ /dev/null @@ -1,25 +0,0 @@ -romstage-y += ../../x86/mtrr/earlymtrr.c -romstage-y += ../car/post_cache_as_ram.c - -romstage-y += init_cpus.c - -ramstage-y += model_10xxx_init.c -ramstage-y += processor_name.c - -romstage-y += update_microcode.c -romstage-y += tsc_freq.c -ramstage-y += tsc_freq.c -romstage-y += ram_calc.c -ramstage-y += ram_calc.c -ramstage-y += monotonic_timer.c -ramstage-$(CONFIG_HAVE_ACPI_TABLES) += powernow_acpi.c - -# Microcode for Family 10h, 11h, 12h, and 14h -cbfs-files-$(CONFIG_CPU_MICROCODE_CBFS_DEFAULT_BINS) += microcode_amd.bin -microcode_amd.bin-file := 3rdparty/blobs/cpu/amd/family_10h-family_14h/microcode_amd.bin -microcode_amd.bin-type := microcode - -# Microcode for Family 15h -cbfs-files-$(CONFIG_CPU_MICROCODE_CBFS_DEFAULT_BINS) += microcode_amd_fam15h.bin -microcode_amd_fam15h.bin-file := 3rdparty/blobs/cpu/amd/family_15h/microcode_amd_fam15h.bin -microcode_amd_fam15h.bin-type := microcode diff --git a/src/cpu/amd/family_10h-family_15h/defaults.h b/src/cpu/amd/family_10h-family_15h/defaults.h deleted file mode 100644 index 6b9cd19b0f..0000000000 --- a/src/cpu/amd/family_10h-family_15h/defaults.h +++ /dev/null @@ -1,834 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include - -/* - * Default MSR and errata settings. - */ -static const struct { - u32 msr; - uint64_t revision; - u32 platform; - u32 data_lo; - u32 data_hi; - u32 mask_lo; - u32 mask_hi; -} fam10_msr_default[] = { - { TOP_MEM2, (AMD_FAM10_ALL | AMD_FAM15_ALL), AMD_PTYPE_ALL, - 0x00000000, 0x00000000, - 0xFFFFFFFF, 0xFFFFFFFF }, - - { SYSCFG_MSR, (AMD_FAM10_ALL | AMD_FAM15_ALL), AMD_PTYPE_ALL, - 3 << 21, 0x00000000, - 3 << 21, 0x00000000 }, /* [MtrrTom2En]=1,[TOM2EnWB] = 1*/ - - { MC1_CTL_MASK, AMD_OR_B2, AMD_PTYPE_ALL, - 1 << 18, 0x00000000, - 1 << 18, 0x00000000 }, /* Erratum 586: [DEIBP]=1 */ - - { MC1_CTL_MASK, AMD_OR_B2, AMD_PTYPE_ALL, - 1 << 15, 0x00000000, - 1 << 15, 0x00000000 }, /* Erratum 593: [BSRP]=1 */ - - { MC1_CTL_MASK, AMD_OR_C0, AMD_PTYPE_ALL, - 1 << 15, 0x00000000, - 1 << 15, 0x00000000 }, /* Erratum 739: [BSRP]=1 */ - - { 0xc0011000, AMD_FAM15_ALL, AMD_PTYPE_ALL, - 1 << 16, 0x00000000, - 1 << 16, 0x00000000 }, /* Erratum 608: [bit 16]=1 */ - - { 0xc0011000, AMD_OR_C0, AMD_PTYPE_ALL, - 1 << 15, 0x00000000, - 1 << 15, 0x00000000 }, /* Erratum 727: [bit 15]=1 */ - - { MC4_CTL_MASK, (AMD_FAM10_ALL | AMD_FAM15_ALL), AMD_PTYPE_ALL, - 0xF << 19, 0x00000000, - 0xF << 19, 0x00000000 }, /* [RtryHt[0..3]]=1 */ - - { MC4_CTL_MASK, (AMD_FAM10_ALL | AMD_FAM15_ALL), AMD_PTYPE_ALL, - 1 << 10, 0x00000000, - 1 << 10, 0x00000000 }, /* [GartTblWkEn]=1 */ - - { DC_CFG_MSR, AMD_FAM10_ALL, AMD_PTYPE_SVR, - 0x00000000, 0x00000004, - 0x00000000, 0x0000000C }, /* Family 10h: [REQ_CTR] = 1 for Server */ - - { DC_CFG_MSR, AMD_DR_Bx, AMD_PTYPE_SVR, - 0x00000000, 0x00000000, - 0x00000000, 0x00000C00 }, /* Erratum 326 */ - - { NB_CFG_MSR, (AMD_FAM10_ALL | AMD_FAM15_ALL), AMD_PTYPE_DC | AMD_PTYPE_MC, - 0x00000000, 1 << 22, - 0x00000000, 1 << 22 }, /* [ApicInitIDLo]=1 */ - - { NB_CFG_MSR, AMD_FAM15_ALL, AMD_PTYPE_DC | AMD_PTYPE_MC, - 1 << 23, 0x00000000, - 1 << 23, 0x00000000 }, /* Erratum 663: [bit 23]=1 */ - - { BU_CFG2_MSR, AMD_DR_Bx, AMD_PTYPE_ALL, - 1 << 29, 0x00000000, - 1 << 29, 0x00000000 }, /* For Bx Smash1GPages=1 */ - - { DC_CFG_MSR, AMD_FAM10_ALL, AMD_PTYPE_ALL, - 1 << 24, 0x00000000, - 1 << 24, 0x00000000 }, /* Erratum #261 [DIS_PIGGY_BACK_SCRUB]=1 */ - - { LS_CFG_MSR, AMD_DR_GT_B0, AMD_PTYPE_ALL, - 0 << 1, 0x00000000, - 1 << 1, 0x00000000 }, /* IDX_MATCH_ALL=0 */ - - { IC_CFG_MSR, AMD_OR_C0, AMD_PTYPE_ALL, - 0x00000000, 1 << (39-32), - 0x00000000, 1 << (39-32)}, /* C0 or above [DisLoopPredictor]=1 */ - - { IC_CFG_MSR, AMD_OR_C0, AMD_PTYPE_ALL, - 0xf << 1, 0x00000000, - 0xf << 1, 0x00000000}, /* C0 or above [DisIcWayFilter]=0xf */ - - { BU_CFG_MSR, AMD_DR_LT_B3, AMD_PTYPE_ALL, - 1 << 21, 0x00000000, - 1 << 21, 0x00000000 }, /* Erratum #254 DR B1 BU_CFG_MSR[21]=1 */ - - { BU_CFG_MSR, AMD_DR_LT_B3, AMD_PTYPE_ALL, - 1 << 23, 0x00000000, - 1 << 23, 0x00000000 }, /* Erratum #309 BU_CFG_MSR[23]=1 */ - - { BU_CFG_MSR, AMD_FAM15_ALL, AMD_PTYPE_ALL, - 0 << 10, 0x00000000, - 1 << 10, 0x00000000 }, /* [DcacheAgressivePriority]=0 */ - - /* CPUID_EXT_FEATURES */ - { CPU_ID_FEATURES_MSR, (AMD_FAM10_ALL | AMD_FAM15_ALL), AMD_PTYPE_DC | AMD_PTYPE_MC, - 1 << 28, 0x00000000, - 1 << 28, 0x00000000 }, /* [HyperThreadFeatEn]=1 */ - - { CPU_ID_FEATURES_MSR, (AMD_FAM10_ALL | AMD_FAM15_ALL), AMD_PTYPE_DC, - 0x00000000, 1 << (33-32), - 0x00000000, 1 << (33-32) }, /* [ExtendedFeatEn]=1 */ - - { DE_CFG_MSR, AMD_OR_B2, AMD_PTYPE_ALL, - 1 << 10, 0x00000000, - 1 << 10, 0x00000000 }, /* Bx [ResyncPredSingleDispDis]=1 */ - - { BU_CFG2_MSR, AMD_DRBH_Cx, AMD_PTYPE_ALL, - 0x00000000, 1 << (35-32), - 0x00000000, 1 << (35-32) }, /* Erratum 343 (set to 0 after CAR, in post_cache_as_ram()/model_10xxx_init() ) */ - - { BU_CFG3_MSR, AMD_OR_B2, AMD_PTYPE_ALL, - 0x00000000, 1 << (42-32), - 0x00000000, 1 << (42-32)}, /* Bx [PwcDisableWalkerSharing]=1 */ - - { BU_CFG3_MSR, AMD_OR_C0, AMD_PTYPE_ALL, - 1 << 22, 0x00000000, - 1 << 22, 0x00000000}, /* C0 or above [PfcDoubleStride]=1 */ - - { EX_CFG_MSR, AMD_OR_C0, AMD_PTYPE_ALL, - 0x00000000, 1 << (54-32), - 0x00000000, 1 << (54-32)}, /* C0 or above [LateSbzResync]=1 */ - - { LS_CFG2_MSR, AMD_OR_C0, AMD_PTYPE_ALL, - 1 << 23, 0x00000000, - 1 << 23, 0x00000000}, /* C0 or above [DisScbThreshold]=1 */ - - { LS_CFG2_MSR, AMD_OR_C0, AMD_PTYPE_ALL, - 1 << 14, 0x00000000, - 1 << 14, 0x00000000}, /* C0 or above [ForceSmcCheckFlowStDis]=1 */ - - { LS_CFG2_MSR, AMD_OR_C0, AMD_PTYPE_ALL, - 1 << 12, 0x00000000, - 1 << 12, 0x00000000}, /* C0 or above [ForceBusLockDis]=1 */ - - { OSVW_ID_Length, AMD_DR_Bx | AMD_DR_Cx | AMD_DR_Dx, AMD_PTYPE_ALL, - 0x00000004, 0x00000000, - 0x00000004, 0x00000000}, /* B0 or Above, OSVW_ID_Length is 0004h */ - - { OSVW_Status, AMD_DR_Cx | AMD_DR_Dx, AMD_PTYPE_MC, - 0x0000000C, 0x00000000, - 0x0000000C, 0x00000000}, /* Cx and Dx multiple-link processor */ - - { OSVW_ID_Length, AMD_FAM15_ALL, AMD_PTYPE_ALL, - 0x00000005, 0x00000000, - 0x0000ffff, 0x00000000}, /* OSVW_ID_Length = 0x5 */ - - { OSVW_Status, AMD_FAM15_ALL, AMD_PTYPE_ALL, - 0x00000010, 0x00000000, - 0xffffffff, 0x00000000}, /* OsvwId4 = 0x1 */ - - { BU_CFG2_MSR, AMD_DR_Dx, AMD_PTYPE_ALL, - 0x00000000, 1 << (50-32), - 0x00000000, 1 << (50-32)}, /* D0 or Above, RdMmExtCfgQwEn*/ - - { BU_CFG2_MSR, AMD_FAM15_ALL, AMD_PTYPE_ALL, - 0x00000000, 0x0 << (36-32), - 0x00000000, 0x3 << (36-32)}, /* [ThrottleNbInterface]=0 */ - - { BU_CFG2_MSR, AMD_FAM15_ALL, AMD_PTYPE_ALL, - 1 << 10, 0x00000000, - 1 << 10, 0x00000000}, /* [VicResyncChkEn]=1 */ - - { BU_CFG2_MSR, AMD_FAM15_ALL, AMD_PTYPE_ALL, - 1 << 11, 0x00000000, - 1 << 11, 0x00000000}, /* Erratum 503: [bit 11]=1 */ - - { CPU_ID_EXT_FEATURES_MSR, AMD_DR_Dx, AMD_PTYPE_ALL, - 0x00000000, 1 << (51 - 32), - 0x00000000, 1 << (51 - 32)}, /* G34_PKG | C32_PKG | S1G4_PKG | ASB2_PKG */ - - { CPU_ID_EXT_FEATURES_MSR, AMD_FAM15_ALL, AMD_PTYPE_ALL, - 0x00000000, 1 << (56 - 32), - 0x00000000, 1 << (56 - 32)}, /* [PerfCtrExtNB]=1 */ - - { CPU_ID_EXT_FEATURES_MSR, AMD_FAM15_ALL, AMD_PTYPE_ALL, - 0x00000000, 1 << (55 - 32), - 0x00000000, 1 << (55 - 32)}, /* [PerfCtrExtCore]=1 */ - - { IBS_OP_DATA3_MSR, AMD_FAM15_ALL, AMD_PTYPE_ALL, - 0 << 16, 0x00000000, - 1 << 16, 0x00000000}, /* [IbsDcMabHit]=0 */ - - { MC4_MISC0, AMD_FAM15_ALL, AMD_PTYPE_ALL, - 0x00000000, 0x1 << (52-32), - 0x00000000, 0xf << (52-32)}, /* [LvtOffset]=1 */ - - { MC4_MISC1, AMD_FAM15_ALL, AMD_PTYPE_ALL, - 0x00000000, 0x1 << (52-32), - 0x00000000, 0xf << (52-32)}, /* [LvtOffset]=1 */ - - { MC4_MISC2, AMD_FAM15_ALL, AMD_PTYPE_ALL, - 0x00000000, 0x1 << (52-32), - 0x00000000, 0xf << (52-32)}, /* [LvtOffset]=1 */ -}; - - -/* - * Default PCI and errata settings. - */ -static const struct { - u8 function; - u16 offset; - uint64_t revision; - u32 platform; - u32 data; - u32 mask; -} fam10_pci_default[] = { - - /* Function 0 - HT Config */ - { 0, 0x68, (AMD_FAM10_ALL | AMD_FAM15_ALL), AMD_PTYPE_ALL, - 0x000e0000, 0x000e0000 }, /* [19:17] for 8bit APIC config */ - - { 0, 0x68, (AMD_FAM10_ALL | AMD_FAM15_ALL), AMD_PTYPE_ALL, - 0x00400000, 0x00600000 }, /* [22:21] DsNpReqLmt = 10b */ - - { 0, 0x68, AMD_FAM10_LT_D, AMD_PTYPE_ALL, - 0x00004000, 0x00006000 }, /* [14:13] BufRelPri = 2h */ - - { 0, 0x68, (AMD_FAM10_REV_D | AMD_FAM15_ALL), AMD_PTYPE_ALL, - 0x00002000, 0x00006000 }, /* [14:13] BufRelPri = 1h */ - - { 0, 0x68, (AMD_FAM10_ALL | AMD_FAM15_ALL), AMD_PTYPE_ALL, - 0x00000800, 0x00000800 }, /* [11] RspPassPW = 1 */ - - /* Errata 281 Workaround */ - { 0, 0x68, (AMD_DR_B0 | AMD_DR_B1), - AMD_PTYPE_SVR, 0x00200000, 0x00600000 }, /* [22:21] DsNpReqLmt0 = 01b */ - - { 0, 0x84, AMD_FAM10_ALL, AMD_PTYPE_ALL, - 0x00002000, 0x00002000 }, /* [13] LdtStopTriEn = 1 */ - - { 0, 0xA4, AMD_FAM10_ALL, AMD_PTYPE_ALL, - 0x00002000, 0x00002000 }, /* [13] LdtStopTriEn = 1 */ - - { 0, 0xC4, AMD_FAM10_ALL, AMD_PTYPE_ALL, - 0x00002000, 0x00002000 }, /* [13] LdtStopTriEn = 1 */ - - { 0, 0xE4, AMD_FAM10_ALL, AMD_PTYPE_ALL, - 0x00002000, 0x00002000 }, /* [13] LdtStopTriEn = 1 */ - - /* Link Global Retry Control Register */ - { 0, 0x150, (AMD_FAM10_ALL | AMD_FAM15_ALL), AMD_PTYPE_ALL, - 0x00073900, 0x00073f70 }, /* TotalRetryAttempts = 0x7, - HtRetryCrcDatInsDynEn = 0x1, - HtRetryCrcCmdPackDynEn = 0x1, - HtRetryCrcDatIns = 0x4, - HtRetryCrcCmdPack = 0x1, - ForceErrType = 0x0, - MultRetryErr = 0x0 */ - - /* Errata 600 */ - { 0, 0x150, AMD_OR_B2, AMD_PTYPE_ALL, - 0x00000000, 0x00000e00 }, /* HtRetryCrcDatIns = 0x0 */ - - /* Errata 351 - * System software should program the Link Extended Control Registers[LS2En] - * (F0x[18C:170][8]) to 0b for all links. System software should also - * program Link Global Extended Control Register[ForceFullT0] - * (F0x16C[15:13]) to 000b */ - - { 0, 0x170, AMD_FAM10_ALL, AMD_PTYPE_ALL, /* Fix FAM10_ALL when fixed in rev guide */ - 0x00000000, 0x00000100 }, - { 0, 0x174, AMD_FAM10_ALL, AMD_PTYPE_ALL, - 0x00000000, 0x00000100 }, - { 0, 0x178, AMD_FAM10_ALL, AMD_PTYPE_ALL, - 0x00000000, 0x00000100 }, - { 0, 0x17C, AMD_FAM10_ALL, AMD_PTYPE_ALL, - 0x00000000, 0x00000100 }, - { 0, 0x180, AMD_FAM10_ALL, AMD_PTYPE_ALL, - 0x00000000, 0x00000100 }, - { 0, 0x184, AMD_FAM10_ALL, AMD_PTYPE_ALL, - 0x00000000, 0x00000100 }, - { 0, 0x188, AMD_FAM10_ALL, AMD_PTYPE_ALL, - 0x00000000, 0x00000100 }, - { 0, 0x18C, AMD_FAM10_ALL, AMD_PTYPE_ALL, - 0x00000000, 0x00000100 }, - - /* Link Global Extended Control Register */ - { 0, 0x16C, AMD_FAM10_ALL, AMD_PTYPE_ALL, - 0x00000014, 0x0000003F }, /* [15:13] ForceFullT0 = 0b, - * Set T0Time 14h per BKDG */ - - { 0, 0x170, AMD_FAM15_ALL, AMD_PTYPE_ALL, - 0x00000100, 0x00000100 }, - { 0, 0x174, AMD_FAM15_ALL, AMD_PTYPE_ALL, - 0x00000100, 0x00000100 }, - { 0, 0x178, AMD_FAM15_ALL, AMD_PTYPE_ALL, - 0x00000100, 0x00000100 }, - { 0, 0x17C, AMD_FAM15_ALL, AMD_PTYPE_ALL, - 0x00000100, 0x00000100 }, - { 0, 0x180, AMD_FAM15_ALL, AMD_PTYPE_ALL, - 0x00000100, 0x00000100 }, - { 0, 0x184, AMD_FAM15_ALL, AMD_PTYPE_ALL, - 0x00000100, 0x00000100 }, - { 0, 0x188, AMD_FAM15_ALL, AMD_PTYPE_ALL, - 0x00000100, 0x00000100 }, - { 0, 0x18C, AMD_FAM15_ALL, AMD_PTYPE_ALL, - 0x00000100, 0x00000100 }, - - /* Link Global Extended Control Register */ - { 0, 0x16C, AMD_FAM15_ALL, AMD_PTYPE_ALL, - 0x00000014, 0x0000003F }, /* [15:13] ForceFullT0 = 111b, - * Set T0Time 26h per BKDG */ - - { 0, 0x16C, AMD_FAM15_ALL, AMD_PTYPE_ALL, - 0x7 << 13, 0x7 << 13 }, /* [15:13] ForceFullT0 = 7h */ - - { 0, 0x16C, AMD_FAM15_ALL, AMD_PTYPE_ALL, - 0x26, 0x3f }, /* [5:0] T0Time = 26h */ - - - /* Function 1 - Map Init */ - - /* Before reading F1x114_x2 or F1x114_x3 software must - * initialize the registers or NB Array MCA errors may - * occur. BIOS should initialize index 0h of F1x114_x2 and - * F1x114_x3 to prevent reads from F1x114 from generating NB - * Array MCA errors. BKDG Doc #3116 Rev 1.07 - */ - - { 1, 0x110, AMD_FAM10_ALL, AMD_PTYPE_ALL, - 0x20000000, 0xFFFFFFFF }, /* Select extended MMIO Base */ - - { 1, 0x114, AMD_FAM10_ALL, AMD_PTYPE_ALL, - 0x00000000, 0xFFFFFFFF }, /* Clear map */ - - { 1, 0x110, AMD_FAM10_ALL, AMD_PTYPE_ALL, - 0x30000000, 0xFFFFFFFF }, /* Select extended MMIO Base */ - - { 1, 0x114, AMD_FAM10_ALL, AMD_PTYPE_ALL, - 0x00000000, 0xFFFFFFFF }, /* Clear map */ - - /* Function 2 - DRAM Controller */ - - /* Function 3 - Misc. Control */ - { 3, 0x40, (AMD_FAM10_ALL | AMD_FAM15_ALL), AMD_PTYPE_ALL, - 0x00000100, 0x00000100 }, /* [8] MstrAbrtEn */ - - { 3, 0x44, (AMD_FAM10_ALL | AMD_FAM15_ALL), AMD_PTYPE_ALL, - 0x4A30005C, 0x4A30005C }, /* [30] SyncOnDramAdrParErrEn = 1, - [27] NbMcaToMstCpuEn = 1, - [25] DisPciCfgCpuErrRsp = 1, - [21] SyncOnAnyErrEn = 1, - [20] SyncOnWDTEn = 1, - [6] CpuErrDis = 1, - [4] SyncPktPropDis = 1, - [3] SyncPktGenDis = 1, - [2] SyncOnUcEccEn = 1 */ - - /* XBAR buffer settings */ - { 3, 0x6c, AMD_FAM10_ALL & ~(AMD_DR_Dx), AMD_PTYPE_ALL, - 0x00018052, 0x700780f7 }, /* IsocRspDBC = 0x0, - UpRspDBC = 0x1, - DatBuf24 = 0x1, - DnRspDBC = 0x1, - DnReqDBC = 0x1, - UpReqDBC = 0x2 */ - - /* XBAR buffer settings */ - { 3, 0x6c, AMD_DR_Dx, AMD_PTYPE_ALL, - 0x00028052, 0x700780f7 }, /* IsocRspDBC = 0x0, - UpRspDBC = 0x2, - DatBuf24 = 0x1, - DnRspDBC = 0x1, - DnReqDBC = 0x1, - UpReqDBC = 0x2 */ - - /* XBAR buffer settings */ - { 3, 0x6c, AMD_FAM15_ALL, AMD_PTYPE_ALL, - 0x10010052, 0x700700f7 }, /* IsocRspDBC = 0x1, - UpRspDBC = 0x1, - DnRspDBC = 0x1, - DnReqDBC = 0x1, - UpReqDBC = 0x2 */ - - /* Errata 281 Workaround */ - { 3, 0x6c, (AMD_DR_B0 | AMD_DR_B1), - AMD_PTYPE_SVR, 0x00010094, 0x700780F7 }, - - { 3, 0x6c, AMD_FAM10_ALL, AMD_PTYPE_UMA, - 0x60018051, 0x700780F7 }, - - { 3, 0x70, AMD_FAM10_ALL & ~(AMD_DR_Dx), AMD_PTYPE_ALL, - 0x00041153, 0x777777f7 }, /* IsocRspCBC = 0x0, - IsocPreqCBC = 0x0, - IsocReqCBC = 0x0, - UpRspCBC = 0x4, - DnPreqCBC = 0x1, - UpPreqCBC = 0x1, - DnRspCBC = 0x1, - DnReqCBC = 0x1, - UpReqCBC = 0x3 */ - - { 3, 0x70, AMD_DR_Dx, AMD_PTYPE_ALL, - 0x00051153, 0x777777f7 }, /* IsocRspCBC = 0x0, - IsocPreqCBC = 0x0, - IsocReqCBC = 0x0, - UpRspCBC = 0x5, - DnPreqCBC = 0x1, - UpPreqCBC = 0x1, - DnRspCBC = 0x1, - DnReqCBC = 0x1, - UpReqCBC = 0x3 */ - - { 3, 0x70, AMD_FAM15_ALL, AMD_PTYPE_ALL, - 0x10171155, 0x777777f7 }, /* IsocRspCBC = 0x1, - IsocPreqCBC = 0x0, - IsocReqCBC = 0x1, - UpRspCBC = 0x7, - DnPreqCBC = 0x1, - UpPreqCBC = 0x1, - DnRspCBC = 0x1, - DnReqCBC = 0x1, - UpReqCBC = 0x5 */ - - { 3, 0x70, AMD_FAM10_ALL, AMD_PTYPE_UMA, - 0x61221151, 0x777777f7 }, /* IsocRspCBC = 0x6, - IsocPreqCBC = 0x1, - IsocReqCBC = 0x2, - UpRspCBC = 0x2, - DnPreqCBC = 0x1, - UpPreqCBC = 0x1, - DnRspCBC = 0x1, - DnReqCBC = 0x1, - UpReqCBC = 0x1 */ - - { 3, 0x74, AMD_FAM10_ALL, ~AMD_PTYPE_UMA, - 0x00081111, 0xf7ff7777 }, /* DRReqCBC = 0x0, - IsocPreqCBC = 0x0, - IsocReqCBC = 0x0, - ProbeCBC = 0x8, - DnPreqCBC = 0x1, - UpPreqCBC = 0x1, - DnReqCBC = 0x1, - UpReqCBC = 0x1 */ - - { 3, 0x74, AMD_FAM10_ALL, AMD_PTYPE_UMA, - 0x00480101, 0xf7ff7777 }, /* DRReqCBC = 0x0, - IsocPreqCBC = 0x0, - IsocReqCBC = 0x4, - ProbeCBC = 0x8, - DnPreqCBC = 0x0, - UpPreqCBC = 0x1, - DnReqCBC = 0x0, - UpReqCBC = 0x1 */ - - { 3, 0x74, AMD_FAM15_ALL, AMD_PTYPE_ALL, - 0x00172111, 0xf7ff7777 }, /* DRReqCBC = 0x0, - IsocPreqCBC = 0x0, - IsocReqCBC = 0x1, - ProbeCBC = 0x7, - DnPreqCBC = 0x2, - UpPreqCBC = 0x1, - DnReqCBC = 0x1, - UpReqCBC = 0x1 */ - - { 3, 0x7c, AMD_FAM10_ALL & ~(AMD_DR_Dx), AMD_PTYPE_ALL, - 0x00090914, 0x707fff1f }, /* XBar2SriFreeListCBInc = 0x0, - Sri2XbarFreeRspDBC = 0x0, - Sri2XbarFreeXreqDBC = 0x9, - Sri2XbarFreeRspCBC = 0x0, - Sri2XbarFreeXreqCBC = 0x9, - Xbar2SriFreeListCBC = 0x14 */ - - { 3, 0x7c, AMD_DR_Dx, AMD_PTYPE_ALL, - 0x00090a18, 0x707fff1f }, /* XBar2SriFreeListCBInc = 0x0, - Sri2XbarFreeRspDBC = 0x0, - Sri2XbarFreeXreqDBC = 0x9, - Sri2XbarFreeRspCBC = 0x0, - Sri2XbarFreeXreqCBC = 0x9, - Xbar2SriFreeListCBC = 0x14 */ - - /* Errata 281 Workaround */ - { 3, 0x7C, ( AMD_DR_B0 | AMD_DR_B1), - AMD_PTYPE_SVR, 0x00144514, 0x707FFF1F }, - - { 3, 0x7c, AMD_FAM15_ALL, AMD_PTYPE_ALL, - 0x040d0f16, 0x77ffff1f }, /* XBar2SriFreeListCBInc = 0x0, - SrqExtFreeListBC = 0x8, - Sri2XbarFreeRspDBC = 0x0, - Sri2XbarFreeXreqDBC = 0xd, - Sri2XbarFreeRspCBC = 0x0, - Sri2XbarFreeXreqCBC = 0xf, - Xbar2SriFreeListCBC = 0x16 */ - - { 3, 0x7C, AMD_FAM10_ALL, AMD_PTYPE_UMA, - 0x00070814, 0x007FFF1F }, - - { 3, 0x140, AMD_FAM10_ALL, AMD_PTYPE_ALL, - 0x00800756, 0x00F3FFFF }, - - { 3, 0x140, AMD_FAM10_ALL, AMD_PTYPE_UMA, - 0x00C37756, 0x00F3FFFF }, - - { 3, 0x144, AMD_FAM10_ALL, AMD_PTYPE_UMA, - 0x00000036, 0x000000FF }, - - { 3, 0x140, AMD_FAM15_ALL, AMD_PTYPE_ALL, - 0x00a11755, 0x00f3ffff }, - - /* Errata 281 Workaround */ - { 3, 0x144, ( AMD_DR_B0 | AMD_DR_B1), - AMD_PTYPE_SVR, 0x00000001, 0x0000000F }, - /* [3:0] RspTok = 0001b */ - - { 3, 0x144, AMD_FAM15_ALL, AMD_PTYPE_ALL, - 0x00000028, 0x000000ff }, - - { 3, 0x148, AMD_FAM10_ALL, AMD_PTYPE_UMA, - 0x8000052A, 0xD5FFFFFF }, - - /* Core Interface Buffer Count */ - { 3, 0x1a0, AMD_FAM15_ALL, AMD_PTYPE_ALL, - 0x00034004, 0x00037007 }, /* CpuToNbFreeBufCnt = 0x3, - L3ToSriReqCBC = 0x4, - L3FreeListCBC = default, - CpuCmdBufCnt = 0x4 */ - - /* ACPI Power State Control Reg1 */ - { 3, 0x80, AMD_FAM10_ALL, AMD_PTYPE_ALL, - 0xE6002200, 0xFFFFFFFF }, - - /* ACPI Power State Control Reg1 */ - { 3, 0x80, AMD_FAM15_ALL, AMD_PTYPE_ALL, - 0xe20be200, 0xefefef00 }, - - /* ACPI Power State Control Reg2 */ - { 3, 0x84, AMD_FAM10_ALL, AMD_PTYPE_ALL, - 0xA0E641E6, 0xFFFFFFFF }, - - /* ACPI Power State Control Reg2 */ - { 3, 0x84, AMD_FAM15_ALL, AMD_PTYPE_ALL, - 0x01e200e2, 0xefef00ef }, - - { 3, 0xA0, AMD_FAM10_ALL, AMD_PTYPE_MOB | AMD_PTYPE_DSK, - 0x00000080, 0x00000080 }, /* [7] PSIVidEnable */ - - { 3, 0xA0, AMD_DR_Bx, AMD_PTYPE_ALL, - 0x00002800, 0x000003800 }, /* [13:11] PllLockTime = 5 */ - - { 3, 0xA0, ((AMD_FAM10_ALL | AMD_FAM15_ALL) & ~(AMD_DR_Bx)), AMD_PTYPE_ALL, - 0x00000800, 0x000003800 }, /* [13:11] PllLockTime = 1 */ - - /* Reported Temp Control Register */ - { 3, 0xA4, (AMD_FAM10_ALL | AMD_FAM15_ALL), AMD_PTYPE_ALL, - 0x00000080, 0x00000080 }, /* [7] TempSlewDnEn = 1 */ - - /* Clock Power/Timing Control 0 Register */ - { 3, 0xD4, (AMD_FAM10_ALL | AMD_FAM15_ALL), AMD_PTYPE_ALL, - 0xC0000F00, 0xF0000F00 }, /* [31] NbClkDivApplyAll = 1, - [30:28] NbClkDiv = 100b,[11:8] ClkRampHystSel = 1111b */ - - /* Clock Power/Timing Control 1 Register */ - { 3, 0xD8, (AMD_FAM10_ALL | AMD_FAM15_ALL), AMD_PTYPE_ALL, - 0x03000010, 0x0F000070 }, /* [6:4] VSRampTime = 1, - * [27:24] ReConDel = 3 */ - - /* Clock Power/Timing Control 1 Register */ - { 3, 0xD8, AMD_FAM10_ALL, AMD_PTYPE_ALL, - 0x00000006, 0x00000007 }, /* [2:0] VSSlamTime = 6 */ - - - /* Clock Power/Timing Control 2 Register */ - { 3, 0xDC, (AMD_FAM10_ALL | AMD_FAM15_ALL), AMD_PTYPE_ALL, - 0x00005000, 0x00007000 }, /* [14:12] NbsynPtrAdj = 5 */ - - - /* Extended NB MCA Config Register */ - { 3, 0x180, (AMD_FAM10_ALL | AMD_FAM15_ALL), AMD_PTYPE_ALL, - 0x007003E2, 0x007003E2 }, /* [22:20] = SyncFloodOn_Err = 7, - [9] SyncOnUncNbAryEn = 1 , - [8] SyncOnProtEn = 1, - [7] SyncFloodOnTgtAbtErr = 1, - [6] SyncFloodOnDatErr = 1, - [5] DisPciCfgCpuMstAbtRsp = 1, - [1] SyncFloodOnUsPwDataErr = 1 */ - - /* NB Configuration 2 */ - { 3, 0x188, AMD_DR_GT_B0, AMD_PTYPE_ALL, - 0x00000010, 0x00000010 }, /* EnStpGntOnFlushMaskWakeup = 0x1 */ - - /* NB Configuration 2 */ - { 3, 0x188, AMD_FAM15_ALL, AMD_PTYPE_ALL, - 0x00000200, 0x00000200 }, /* DisL3HiPriFreeListAlloc = 0x1 */ - - /* errata 346 - Fam10 C2, C3 - * System software should set F3x188[22] to 1b. */ - { 3, 0x188, AMD_DR_Cx, AMD_PTYPE_ALL, - 0x00400000, 0x00400000 }, - - /* L3 Control Register */ - { 3, 0x1b8, (AMD_FAM10_ALL | AMD_FAM15_ALL), AMD_PTYPE_ALL, - 0x00001000, 0x00001000 }, /* [12] = L3PrivReplEn */ - - /* Errata 504 workaround */ - { 3, 0x1b8, AMD_FAM15_ALL, AMD_PTYPE_ALL, - 0x00040000, 0x00040000 }, /* [18] = 1b */ - - /* IBS Control Register */ - { 3, 0x1cc, (AMD_FAM10_ALL | AMD_FAM15_ALL), AMD_PTYPE_ALL, - 0x00000100, 0x00000100 }, /* [8] = LvtOffsetVal */ - - /* Erratum 619 - Family 15h Bx - * System software should set F5x88[14] to 1b. */ - { 5, 0x88, AMD_OR_B2, AMD_PTYPE_ALL, - 1 << 14, 1 << 14 }, - - /* L3 Control 2 */ - { 3, 0x1b8, AMD_FAM15_ALL, AMD_PTYPE_ALL, - 0x00000090, 0x000001d0 }, /* ImplRdProjDelayThresh = 0x2, - ImplRdAnySubUnavail = 0x1 */ -}; - - -/* - * Default HyperTransport Phy and errata settings. - */ -static const struct { - u16 htreg; /* HT Phy Register index */ - uint64_t revision; - u32 platform; - u32 linktype; - u32 data; - u32 mask; -} fam10_htphy_default[] = { - - /* Errata 344 - Fam10 C2/C3, D0/D1 - * System software should set bit 6 of F4x1[9C, 94, 8C, 84]_x[78:70, 68:60]. */ - { 0x60, AMD_DR_Cx | AMD_DR_Dx, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL, - 0x00000040, 0x00000040 }, - { 0x61, AMD_DR_Cx | AMD_DR_Dx, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL, - 0x00000040, 0x00000040 }, - { 0x62, AMD_DR_Cx | AMD_DR_Dx, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL, - 0x00000040, 0x00000040 }, - { 0x63, AMD_DR_Cx | AMD_DR_Dx, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL, - 0x00000040, 0x00000040 }, - { 0x64, AMD_DR_Cx | AMD_DR_Dx, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL, - 0x00000040, 0x00000040 }, - { 0x65, AMD_DR_Cx | AMD_DR_Dx, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL, - 0x00000040, 0x00000040 }, - { 0x66, AMD_DR_Cx | AMD_DR_Dx, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL, - 0x00000040, 0x00000040 }, - { 0x67, AMD_DR_Cx | AMD_DR_Dx, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL, - 0x00000040, 0x00000040 }, - { 0x68, AMD_DR_Cx | AMD_DR_Dx, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL, - 0x00000040, 0x00000040 }, - - { 0x70, AMD_DR_Cx | AMD_DR_Dx, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL, - 0x00000040, 0x00000040 }, - { 0x71, AMD_DR_Cx | AMD_DR_Dx, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL, - 0x00000040, 0x00000040 }, - { 0x72, AMD_DR_Cx | AMD_DR_Dx, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL, - 0x00000040, 0x00000040 }, - { 0x73, AMD_DR_Cx | AMD_DR_Dx, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL, - 0x00000040, 0x00000040 }, - { 0x74, AMD_DR_Cx | AMD_DR_Dx, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL, - 0x00000040, 0x00000040 }, - { 0x75, AMD_DR_Cx | AMD_DR_Dx, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL, - 0x00000040, 0x00000040 }, - { 0x76, AMD_DR_Cx | AMD_DR_Dx, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL, - 0x00000040, 0x00000040 }, - { 0x77, AMD_DR_Cx | AMD_DR_Dx, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL, - 0x00000040, 0x00000040 }, - { 0x78, AMD_DR_Cx | AMD_DR_Dx, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL, - 0x00000040, 0x00000040 }, - - /* Errata 354 - Fam10 C2, C3 - * System software should set bit 6 of F4x1[9C,94,8C,84]_x[58:50, 48:40] for all links. */ - { 0x40, AMD_DR_Cx, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL, - 0x00000040, 0x00000040 }, - { 0x41, AMD_DR_Cx, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL, - 0x00000040, 0x00000040 }, - { 0x42, AMD_DR_Cx, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL, - 0x00000040, 0x00000040 }, - { 0x43, AMD_DR_Cx, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL, - 0x00000040, 0x00000040 }, - { 0x44, AMD_DR_Cx, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL, - 0x00000040, 0x00000040 }, - { 0x45, AMD_DR_Cx, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL, - 0x00000040, 0x00000040 }, - { 0x46, AMD_DR_Cx, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL, - 0x00000040, 0x00000040 }, - { 0x47, AMD_DR_Cx, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL, - 0x00000040, 0x00000040 }, - { 0x48, AMD_DR_Cx, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL, - 0x00000040, 0x00000040 }, - - { 0x50, AMD_DR_Cx, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL, - 0x00000040, 0x00000040 }, - { 0x51, AMD_DR_Cx, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL, - 0x00000040, 0x00000040 }, - { 0x52, AMD_DR_Cx, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL, - 0x00000040, 0x00000040 }, - { 0x53, AMD_DR_Cx, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL, - 0x00000040, 0x00000040 }, - { 0x54, AMD_DR_Cx, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL, - 0x00000040, 0x00000040 }, - { 0x55, AMD_DR_Cx, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL, - 0x00000040, 0x00000040 }, - { 0x56, AMD_DR_Cx, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL, - 0x00000040, 0x00000040 }, - { 0x57, AMD_DR_Cx, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL, - 0x00000040, 0x00000040 }, - { 0x58, AMD_DR_Cx, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL, - 0x00000040, 0x00000040 }, - - /* Errata 327 - Fam10 C2/C3, D0/D1 - * BIOS should set the Link Phy Impedance Register[RttCtl] - * (F4x1[9C, 94, 8C, 84]_x[D0, C0][31:29]) to 010b and - * Link Phy Impedance Register[RttIndex] - * (F4x1[9C, 94, 8C, 84]_x[D0, C0][20:16]) to 00100b */ - { 0xC0, AMD_DR_Cx | AMD_DR_Dx, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL, - 0x40040000, 0xe01F0000 }, - { 0xD0, AMD_DR_Cx | AMD_DR_Dx, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL, - 0x40040000, 0xe01F0000 }, - - { 0x520A,AMD_DR_Cx | AMD_DR_Dx, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL, - 0x00004000, 0x00006000 }, /* HT_PHY_DLL_REG */ - - { 0x530A, AMD_DR_Cx | AMD_DR_Dx, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL, - 0x00004000, 0x00006000 }, /* HT_PHY_DLL_REG */ - - { 0x520A, AMD_DR_ALL, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL, - 0x00004400, 0x00006400 }, /* HT_PHY_DLL_REG */ - - { 0x530A, AMD_DR_ALL, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL, - 0x00004400, 0x00006400 }, /* HT_PHY_DLL_REG */ - - { 0xCF, AMD_FAM10_ALL, AMD_PTYPE_ALL, HTPHY_LINKTYPE_HT3, - 0x0000005a, 0x000000ff }, /* Use common "safe" setting for K10 */ - - { 0xDF, AMD_FAM10_ALL, AMD_PTYPE_ALL, HTPHY_LINKTYPE_HT3, - 0x0000005a, 0x000000ff }, /* Use common "safe" setting for K10 */ - - { 0xCF, AMD_FAM10_ALL, AMD_PTYPE_ALL, HTPHY_LINKTYPE_HT1, - 0x0000006d, 0x000000ff }, /* HT_PHY_HT1_FIFO_PTR_OPT_VALUE */ - - { 0xDF, AMD_FAM10_ALL, AMD_PTYPE_ALL, HTPHY_LINKTYPE_HT1, - 0x0000006d, 0x000000ff }, /* HT_PHY_HT1_FIFO_PTR_OPT_VALUE */ - - /* Link Phy Receiver Loop Filter Registers */ - { 0xD1, AMD_FAM10_ALL, AMD_PTYPE_ALL, HTPHY_LINKTYPE_HT3, - 0x08040000, 0x3FFFC000 }, /* [29:22] LfcMax = 20h, - [21:14] LfcMin = 10h */ - - { 0xC1, AMD_FAM10_ALL, AMD_PTYPE_ALL, HTPHY_LINKTYPE_HT3, - 0x08040000, 0x3FFFC000 }, /* [29:22] LfcMax = 20h, - [21:14] LfcMin = 10h */ - - { 0xD1, AMD_FAM10_ALL, AMD_PTYPE_ALL, HTPHY_LINKTYPE_HT1, - 0x04020000, 0x3FFFC000 }, /* [29:22] LfcMax = 10h, - [21:14] LfcMin = 08h */ - - { 0xC1, AMD_FAM10_ALL, AMD_PTYPE_ALL, HTPHY_LINKTYPE_HT1, - 0x04020000, 0x3FFFC000 }, /* [29:22] LfcMax = 10h, - [21:14] LfcMin = 08h */ - - { 0xC0, AMD_FAM10_ALL, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL, - 0x40040000, 0xe01F0000 }, /* [31:29] RttCtl = 02h, - [20:16] RttIndex = 04h */ - - { 0xCF, AMD_FAM15_ALL, AMD_PTYPE_ALL, HTPHY_LINKTYPE_HT3, - 0x00000a2a, 0x000000ff }, /* P0RcvRdPtr = 0xa, - P0XmtRdPtr = 0x2 - P1RcvRdPtr = 0xa - P1XmtRdPtr = 0x0 */ - - { 0xDF, AMD_FAM15_ALL, AMD_PTYPE_ALL, HTPHY_LINKTYPE_HT3, - 0x00000a2a, 0x000000ff }, /* P0RcvRdPtr = 0xa, - P0XmtRdPtr = 0x2 - P1RcvRdPtr = 0xa - P1XmtRdPtr = 0x0 */ - - { 0xCF, AMD_FAM15_ALL, AMD_PTYPE_ALL, HTPHY_LINKTYPE_HT1, - 0x00000d4d, 0x000000ff }, /* P0RcvRdPtr = 0xd, - P0XmtRdPtr = 0x4 - P1RcvRdPtr = 0xd - P1XmtRdPtr = 0x0 */ - - { 0xDF, AMD_FAM15_ALL, AMD_PTYPE_ALL, HTPHY_LINKTYPE_HT1, - 0x00000d4d, 0x000000ff }, /* P0RcvRdPtr = 0xd, - P0XmtRdPtr = 0x4 - P1RcvRdPtr = 0xd - P1XmtRdPtr = 0x0 */ - - /* Link Phy Receiver Loop Filter Registers */ - { 0xD1, AMD_FAM15_ALL, AMD_PTYPE_ALL, HTPHY_LINKTYPE_HT3, - 0x08040000, 0x3FFFC000 }, /* [29:22] LfcMax = 20h, - [21:14] LfcMin = 10h */ - - { 0xC1, AMD_FAM15_ALL, AMD_PTYPE_ALL, HTPHY_LINKTYPE_HT3, - 0x08040000, 0x3FFFC000 }, /* [29:22] LfcMax = 20h, - [21:14] LfcMin = 10h */ - - { 0xD1, AMD_FAM15_ALL, AMD_PTYPE_ALL, HTPHY_LINKTYPE_HT1, - 0x04020000, 0x3FFFC000 }, /* [29:22] LfcMax = 10h, - [21:14] LfcMin = 08h */ - - { 0xC1, AMD_FAM15_ALL, AMD_PTYPE_ALL, HTPHY_LINKTYPE_HT1, - 0x04020000, 0x3FFFC000 }, /* [29:22] LfcMax = 10h, - [21:14] LfcMin = 08h */ - - { 0xC0, AMD_FAM15_ALL, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL, - 0x40040000, 0xe01F0000 }, /* [31:29] RttCtl = 02h, - [20:16] RttIndex = 04h */ - - { 0xc4, AMD_FAM15_ALL, AMD_PTYPE_ALL, HTPHY_LINKTYPE_HT3, - 0x00013480, 0x0003fc80 }, /* [17:10] DCV = 0x4d, - [7] DfeEn = 0x1 */ - - { 0xd4, AMD_FAM15_ALL, AMD_PTYPE_ALL, HTPHY_LINKTYPE_HT3, - 0x00013480, 0x0003fc80 }, /* [17:10] DCV = 0x4d, - [7] DfeEn = 0x1 */ -}; diff --git a/src/cpu/amd/family_10h-family_15h/fidvid.c b/src/cpu/amd/family_10h-family_15h/fidvid.c deleted file mode 100644 index d4dec2b1c0..0000000000 --- a/src/cpu/amd/family_10h-family_15h/fidvid.c +++ /dev/null @@ -1,1102 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ -/* - * This file initializes the CPU cores for voltage and frequency settings - * in the different power states. - */ -/* - -checklist (functions are in this file if no source file named) -Fam10 Bios and Kernel Development Guide #31116, rev 3.48, April 22, 2010 - -2.4.2.6 Requirements for p-states - -1.- F3x[84:80] According to table 100 : prep_fid_change - -2.- COF/VID : - 2.4.2.9.1 Steps 1,3-6 and warning for 2,7 if they apply - fixPsNbVidBeforeWR(...) - 2.4.2.9.1 Step 8 enable_fid_change - We do this for all nodes, I don't understand BKDG 100% on - whether this is or isn't meant by "on the local - processor". Must be OK. - 2.4.2.9.1 Steps 9-10 (repeat 1-7 and reset) romstage.c/init_cpus ? - 2.4.2.9.1 Steps 11-12 init_fidvid_stage2 - 2.4.2.9.2 DualPlane PVI : Not supported, don't know how to detect, - needs specific circuitry. - -3.- 2.4.2.7 dualPlaneOnly(dev) - -4.- 2.4.2.8 applyBoostFIDOffset(dev, nodeid) - -5.- enableNbPState1(dev) - -6.- 2.4.1.7 - a) UpdateSinglePlaneNbVid() - b) setVSRamp(), called from prep_fid_change - c) prep_fid_change - d) improperly, for lack of voltage regulator details?, - F3xA0[PsiVidEn] in defaults.h - F3xA0[PsiVid] in init_cpus.c AMD_SetupPSIVID_d (before prep_fid_change) - -7.- TODO (Core Performance Boost is only available in revision E cpus, and we - don't seem to support those yet, at least they don't have any - constant in amddefs.h ) - -8.- FIXME ? Transition to min Pstate according to 2.4.2.15.3 is required - by 2.4.2.6 after warm reset. But 2.4.2.15 states that it is not required - if the warm reset is issued by coreboot to update NbFid. So it is required - or not ? How can I tell who issued warm reset ? - coreboot transitions to P0 instead, which is not recommended, and does - not follow 2.4.2.15.2 to do so. - -9.- TODO Requires information on current delivery capability - (depends on mainboard and maybe power supply ?). One might use a config - option with the maximum number of Amperes that the board can deliver to CPU. - -10.- [Multiprocessor] TODO 2.4.2.12 - [Uniprocessor] FIXME ? We call setPStateMaxVal() in init_fidvid_stage2, - but not sure this is what is meant by "Determine the valid set of - P-states based on enabled P-states indicated - in MSRC001_00[68:64][PstateEn]" in 2.4.2.6-10 - -11.- finalPstateChange() from init_fidvid_Stage2 (BKDG says just "may", anyway) - -12.- generate ACPI for p-states. - generated in powernow_acpi.c amd_generate_powernow() - -"must also be completed" - -a.- PllLockTime set in ruleset in defaults.h - BKDG says set it "If MSRC001_00[68:64][CpuFid] is different between - any two enabled P-states", but since it does not say "only if" - I guess it is safe to do it always. - -b.- prep_fid_change(...) - - */ - -#include -#include -#include -#include -#include -#include - -static inline void print_debug_fv(const char *str, u32 val) -{ -#if CONFIG(SET_FIDVID_DEBUG) - printk(BIOS_DEBUG, "%s%x\n", str, val); -#endif -} - -static inline void print_debug_fv_8(const char *str, u8 val) -{ -#if CONFIG(SET_FIDVID_DEBUG) - printk(BIOS_DEBUG, "%s%02x\n", str, val); -#endif -} - -static inline void print_debug_fv_64(const char *str, u32 val, u32 val2) -{ -#if CONFIG(SET_FIDVID_DEBUG) - printk(BIOS_DEBUG, "%s%x%x\n", str, val, val2); -#endif -} - -struct fidvid_st { - u32 common_fid; -}; - -static void enable_fid_change(u8 fid) -{ - u32 dword; - u32 nodes; - pci_devfn_t dev; - int i; - - nodes = get_nodes(); - - for (i = 0; i < nodes; i++) { - dev = NODE_PCI(i, 3); - dword = pci_read_config32(dev, 0xd4); - dword &= ~0x1F; - dword |= (u32) fid & 0x1F; - dword |= 1 << 5; // enable - pci_write_config32(dev, 0xd4, dword); - printk(BIOS_DEBUG, "FID Change Node:%02x, F3xD4: %08x\n", i, - dword); - } -} - -static void applyBoostFIDOffset(pci_devfn_t dev, uint32_t nodeid) -{ - // BKDG 2.4.2.8 - // Fam10h revision E only, but E is apparently not supported yet, therefore untested - if ((cpuid_edx(0x80000007) & CPB_MASK) - && ((cpuid_ecx(0x80000008) & NC_MASK) == 5) ) { - u32 core = get_node_core_id_x().coreid; - u32 asymetricBoostThisCore = ((pci_read_config32(dev, 0x10C) >> (core*2))) & 3; - msr_t msr = rdmsr(PSTATE_0_MSR); - u32 cpuFid = msr.lo & PS_CPU_FID_MASK; - cpuFid = cpuFid + asymetricBoostThisCore; - msr.lo &= ~PS_CPU_FID_MASK; - msr.lo |= cpuFid; - wrmsr(PSTATE_0_MSR, msr); - } else if (is_fam15h()) { - uint32_t dword = pci_read_config32(NODE_PCI(nodeid, 4), 0x15c); - uint8_t boost_count = (dword >> 2) & 0x7; - if (boost_count > 0) { - /* Enable boost */ - dword &= ~0x3; - dword |= 0x1; - pci_write_config32(NODE_PCI(nodeid, 4), 0x15c, dword); - } - } -} - -static void enableNbPState1(pci_devfn_t dev) -{ - uint64_t cpuRev = mctGetLogicalCPUID(0xFF); - if (cpuRev & AMD_FAM10_C3) { - u32 nbPState = (pci_read_config32(dev, 0x1F0) & NB_PSTATE_MASK); - if ( nbPState){ - u32 nbVid1 = (pci_read_config32(dev, 0x1F4) & NB_VID1_MASK) >> NB_VID1_SHIFT; - u32 i; - for (i = nbPState; i < NM_PS_REG; i++) { - msr_t msr = rdmsr(PSTATE_0_MSR + i); - if (msr.hi & PS_EN_MASK ) { - msr.hi |= NB_DID_M_ON; - msr.lo &= NB_VID_MASK_OFF; - msr.lo |= ( nbVid1 << NB_VID_POS); - wrmsr(PSTATE_0_MSR + i, msr); - } - } - } - } -} - -static u8 setPStateMaxVal(pci_devfn_t dev) -{ - u8 i, maxpstate=0; - for (i = 0; i < NM_PS_REG; i++) { - msr_t msr = rdmsr(PSTATE_0_MSR + i); - if (msr.hi & PS_IDD_VALUE_MASK) { - msr.hi |= PS_EN_MASK; - wrmsr(PSTATE_0_MSR + i, msr); - } - if (msr.hi & PS_EN_MASK) { - maxpstate = i; - } - } - //FIXME: CPTC2 and HTC_REG should get max per node, not per core ? - u32 reg = pci_read_config32(dev, CPTC2); - reg &= PS_MAX_VAL_MASK; - reg |= (maxpstate << PS_MAX_VAL_POS); - pci_write_config32(dev, CPTC2,reg); - return maxpstate; -} - -static void dualPlaneOnly(pci_devfn_t dev) -{ - // BKDG 2.4.2.7 - - uint64_t cpuRev = mctGetLogicalCPUID(0xFF); - if ((mctGetProcessorPackageType() == AMD_PKGTYPE_AM3_2r2) - && (cpuRev & (AMD_DR_Cx | AMD_DR_Ex))) { - if ((pci_read_config32(dev, 0x1FC) & DUAL_PLANE_ONLY_MASK) - && (pci_read_config32(dev, 0xA0) & PVI_MODE)) { - if (cpuid_edx(CPUID_EXT_PM) & CPB_MASK) { - // revision E only, but E is apparently not supported yet, therefore untested - msr_t minPstate = rdmsr(PSTATE_1_MSR); - wrmsr(PSTATE_1_MSR, rdmsr(PSTATE_4_MSR)); - wrmsr(PSTATE_4_MSR, minPstate); - } else { - msr_t msr; - msr.lo=0; msr.hi=0; - wrmsr(PSTATE_0_MSR, rdmsr(PSTATE_4_MSR)); - wrmsr(PSTATE_4_MSR, msr); - } - - //FIXME: CPTC2 and HTC_REG should get max per node, not per core ? - u8 maxpstate = setPStateMaxVal(dev); - - u32 reg = pci_read_config32(dev, HTC_REG); - reg &= HTC_PS_LMT_MASK; - reg |= (maxpstate << PS_LIMIT_POS); - pci_write_config32(dev, HTC_REG,reg); - } - } -} - -static int vidTo100uV(u8 vid) -{ - // returns voltage corresponding to vid in tenths of mV, i.e. hundreds of uV - // BKDG #31116 rev 3.48 2.4.1.6 - int voltage; - if (vid >= 0x7c) { - voltage = 0; - } else { - voltage = (15500 - (125*vid)); - } - return voltage; -} - -static void setVSRamp(pci_devfn_t dev) -{ - /* BKDG r31116 2010-04-22 2.4.1.7 step b F3xD8[VSRampTime] - * If this field accepts 8 values between 10 and 500 us why - * does page 324 say "BIOS should set this field to 001b." - * (20 us) ? - * Shouldn't it depend on the voltage regulators, mainboard - * or something ? - */ - u32 dword; - dword = pci_read_config32(dev, 0xd8); - dword &= VSRAMP_MASK; - dword |= VSRAMP_VALUE; - pci_write_config32(dev, 0xd8, dword); -} - -static void recalculateVsSlamTimeSettingOnCorePre(pci_devfn_t dev) -{ - u8 pviModeFlag; - u8 highVoltageVid, lowVoltageVid, bValue; - u16 minimumSlamTime; - u16 vSlamTimes[7] = { 1000, 2000, 3000, 4000, 6000, 10000, 20000 }; /* Reg settings scaled by 100 */ - u32 dtemp; - msr_t msr; - - /* This function calculates the VsSlamTime using the range of possible - * voltages instead of a hardcoded 200us. - * Note: his function is called only from prep_fid_change, - * and that from init_cpus.c finalize_node_setup() - * (after set AMD MSRs and init ht ) - */ - - /* BKDG r31116 2010-04-22 2.4.1.7 step b F3xD8[VSSlamTime] */ - /* Calculate Slam Time - * Vslam = (mobileCPU?0.2:0.4)us/mV * (Vp0 - (lowest out of Vpmin or Valt)) mV - * In our case, we will scale the values by 100 to avoid - * decimals. - */ - - /* Determine if this is a PVI or SVI system */ - if (is_fam15h()) { - pviModeFlag = 0; - } else { - dtemp = pci_read_config32(dev, 0xa0); - - if (dtemp & PVI_MODE) - pviModeFlag = 1; - else - pviModeFlag = 0; - } - - /* Get P0's voltage */ - /* MSRC001_00[68:64] are not programmed yet when called from - prep_fid_change, one might use F4x1[F0:E0] instead, but - theoretically MSRC001_00[68:64] are equal to them after - reset. */ - msr = rdmsr(PSTATE_0_MSR); - highVoltageVid = (u8) ((msr.lo >> PS_CPU_VID_SHFT) & 0x7F); - if (!(msr.hi & 0x80000000)) { - printk(BIOS_ERR,"P-state info in MSRC001_0064 is invalid !!!\n"); - highVoltageVid = (u8) ((pci_read_config32(dev, 0x1E0) - >> PS_CPU_VID_SHFT) & 0x7F); - } - - /* If SVI, we only care about CPU VID. - * If PVI, determine the higher voltage b/t NB and CPU - */ - if (pviModeFlag) { - bValue = (u8) ((msr.lo >> PS_NB_VID_SHFT) & 0x7F); - if (highVoltageVid > bValue) - highVoltageVid = bValue; - } - - /* Get PSmax's index */ - msr = rdmsr(PS_LIM_REG); - bValue = (u8) ((msr.lo >> PS_MAX_VAL_SHFT) & BIT_MASK_3); - - /* Get PSmax's VID */ - msr = rdmsr(PSTATE_0_MSR + bValue); - lowVoltageVid = (u8) ((msr.lo >> PS_CPU_VID_SHFT) & 0x7F); - if (!(msr.hi & 0x80000000)) { - printk(BIOS_ERR, "P-state info in MSR%8x is invalid !!!\n", - PSTATE_0_MSR + bValue); - lowVoltageVid = (u8) ((pci_read_config32(dev, 0x1E0+(bValue*4)) - >> PS_CPU_VID_SHFT) & 0x7F); - } - - /* If SVI, we only care about CPU VID. - * If PVI, determine the higher voltage b/t NB and CPU - * BKDG 2.4.1.7 (a) - */ - if (pviModeFlag) { - bValue = (u8) ((msr.lo >> PS_NB_VID_SHFT) & 0x7F); - if (lowVoltageVid > bValue) - lowVoltageVid = bValue; - } - - /* Get AltVID */ - dtemp = pci_read_config32(dev, 0xdc); - bValue = (u8) (dtemp & BIT_MASK_7); - - /* Use the VID with the lowest voltage (higher VID) */ - if (lowVoltageVid < bValue) - lowVoltageVid = bValue; - - u8 mobileFlag = get_platform_type() & AMD_PTYPE_MOB; - minimumSlamTime = (mobileFlag?2:4) * (vidTo100uV(highVoltageVid) - vidTo100uV(lowVoltageVid)); /* * 0.01 us */ - - - /* Now round up to nearest register setting. - * Note that if we don't find a value, we - * will fall through to a value of 7 - */ - for (bValue = 0; bValue < 7; bValue++) { - if (minimumSlamTime <= vSlamTimes[bValue]) - break; - } - - /* Apply the value */ - dtemp = pci_read_config32(dev, 0xD8); - dtemp &= VSSLAM_MASK; - dtemp |= bValue; - pci_write_config32(dev, 0xd8, dtemp); -} - -static u32 nb_clk_did(uint8_t node, uint64_t cpuRev, uint8_t procPkg) { - uint8_t link0isGen3 = 0; - uint8_t offset; - if (AMD_CpuFindCapability(node, 0, &offset)) { - link0isGen3 = (AMD_checkLinkType(node, offset) & HTPHY_LINKTYPE_HT3 ); - } - /* FIXME: NB_CLKDID should be 101b for AMD_DA_C2 in package - S1g3 in link Gen3 mode, but I don't know how to tell - package S1g3 from S1g4 */ - if ((cpuRev & AMD_DA_C2) && (procPkg & AMD_PKGTYPE_S1gX) - && link0isGen3) { - return 5; /* divide clk by 128*/ - } else { - return 4; /* divide clk by 16 */ - } -} - - -static u32 power_up_down(int node, u8 procPkg) { - uint32_t dword=0; - /* from CPU rev guide #41322 rev 3.74 June 2010 Table 26 */ - u8 singleLinkFlag = ((procPkg == AMD_PKGTYPE_AM3_2r2) - || (procPkg == AMD_PKGTYPE_S1gX) - || (procPkg == AMD_PKGTYPE_ASB2)); - - if (singleLinkFlag) { - /* - * PowerStepUp=01000b - 50nS - * PowerStepDown=01000b - 50ns - */ - dword |= PW_STP_UP50 | PW_STP_DN50; - } else { - uint32_t dispRefModeEn = (pci_read_config32(NODE_PCI(node,0),0x68) >> 24) & 1; - uint32_t isocEn = 0; - int j; - for (j=0; (j<4) && (!isocEn); j++ ) { - u8 offset; - if (AMD_CpuFindCapability(node, j, &offset)) { - isocEn = (pci_read_config32(NODE_PCI(node,0),offset+4) >>12) & 1; - } - } - - if (is_fam15h()) { - /* Family 15h always uses 100ns for multilink processors */ - dword |= PW_STP_UP100 | PW_STP_DN100; - } else if (dispRefModeEn || isocEn) { - dword |= PW_STP_UP50 | PW_STP_DN50; - } else { - /* get number of cores for PowerStepUp & PowerStepDown in server - * 1 core - 400nS - 0000b - * 2 cores - 200nS - 0010b - * 3 cores - 133nS -> 100nS - 0011b - * 4 cores - 100nS - 0011b - */ - switch (get_core_num_in_bsp(node)) { - case 0: - dword |= PW_STP_UP400 | PW_STP_DN400; - break; - case 1: - case 2: - dword |= PW_STP_UP200 | PW_STP_DN200; - break; - case 3: - dword |= PW_STP_UP100 | PW_STP_DN100; - break; - default: - dword |= PW_STP_UP100 | PW_STP_DN100; - break; - } - } - } - - return dword; -} - -static void config_clk_power_ctrl_reg0(uint8_t node, uint64_t cpuRev, uint8_t procPkg) { - - pci_devfn_t dev = NODE_PCI(node, 3); - - /* Program fields in Clock Power/Control register0 (F3xD4) */ - - /* set F3xD4 Clock Power/Timing Control 0 Register - * NbClkDidApplyAll=1b - * NbClkDid=100b or 101b - * PowerStepUp= "platform dependent" - * PowerStepDown= "platform dependent" - * LinkPllLink=01b - * ClkRampHystCtl=HW default - * ClkRampHystSel=1111b - */ - uint32_t dword= pci_read_config32(dev, 0xd4); - dword &= CPTC0_MASK; - dword |= NB_CLKDID_ALL | LNK_PLL_LOCK | CLK_RAMP_HYST_SEL_VAL; - dword |= (nb_clk_did(node,cpuRev,procPkg) << NB_CLKDID_SHIFT); - - dword |= power_up_down(node, procPkg); - - pci_write_config32(dev, 0xd4, dword); - -} - -static void config_power_ctrl_misc_reg(pci_devfn_t dev, uint64_t cpuRev, - uint8_t procPkg) -{ - /* check PVI/SVI */ - uint32_t dword = pci_read_config32(dev, 0xa0); - - /* BKDG r31116 2010-04-22 2.4.1.7 step b F3xA0[VSSlamVidMod] */ - /* PllLockTime and PsiVidEn set in ruleset in defaults.h */ - if (dword & PVI_MODE) { /* PVI */ - /* set slamVidMode to 0 for PVI */ - dword &= VID_SLAM_OFF; - } else { /* SVI */ - /* set slamVidMode to 1 for SVI */ - dword |= VID_SLAM_ON; - } - /* set the rest of A0 since we're at it... */ - - if (cpuRev & (AMD_DA_Cx | AMD_RB_C3 )) { - dword |= NB_PSTATE_FORCE_ON; - } // else should we clear it ? - - - if ((procPkg == AMD_PKGTYPE_G34) || (procPkg == AMD_PKGTYPE_C32) ) { - dword |= BP_INS_TRI_EN_ON; - } - - /* TODO: look into C1E state and F3xA0[IdleExitEn]*/ - #if 0 - if (cpuRev & AMD_FAM10_C3) { - dword |= SVI_HIGH_FREQ_ON; - } - #endif - pci_write_config32(dev, 0xa0, dword); -} - -static void config_nb_syn_ptr_adj(pci_devfn_t dev, uint64_t cpuRev) -{ - /* Note the following settings are additional from the ported - * function setFidVidRegs() - */ - /* adjust FIFO between nb and core clocks to max allowed - values (min latency) */ - uint32_t nbPstate = pci_read_config32(dev,0x1f0) & NB_PSTATE_MASK; - uint8_t nbSynPtrAdj; - if ((cpuRev & (AMD_DR_Bx | AMD_DA_Cx | AMD_FAM15_ALL) ) - || ((cpuRev & AMD_RB_C3) && (nbPstate != 0))) { - nbSynPtrAdj = 5; - } else { - nbSynPtrAdj = 6; - } - - uint32_t dword = pci_read_config32(dev, 0xdc); - dword &= ~NB_SYN_PTR_ADJ_MASK; - dword |= nbSynPtrAdj << NB_SYN_PTR_ADJ_POS; - /* NbsynPtrAdj set to 5 or 6 per BKDG (needs reset) */ - pci_write_config32(dev, 0xdc, dword); -} - -static void config_acpi_pwr_state_ctrl_regs(pci_devfn_t dev, uint64_t cpuRev, - uint8_t procPkg) -{ - if (is_fam15h()) { - /* Family 15h BKDG Rev. 3.14 D18F3x80 recommended settings */ - pci_write_config32(dev, 0x80, 0xe20be281); - - /* Family 15h BKDG Rev. 3.14 D18F3x84 recommended settings */ - pci_write_config32(dev, 0x84, 0x01e200e2); - } else { - /* step 1, chapter 2.4.2.6 of AMD Fam 10 BKDG #31116 Rev 3.48 22.4.2010 */ - uint32_t dword; - uint32_t c1= 1; - if (cpuRev & (AMD_DR_Bx)) { - // will coreboot ever enable cache scrubbing ? - // if it does, will it be enough to check the current state - // or should we configure for what we'll set up later ? - dword = pci_read_config32(dev, 0x58); - uint32_t scrubbingCache = dword & - ( (0x1F << 16) // DCacheScrub - | (0x1F << 8) ); // L2Scrub - if (scrubbingCache) { - c1 = 0x80; - } else { - c1 = 0xA0; - } - } else { // rev C or later - // same doubt as cache scrubbing: ok to check current state ? - dword = pci_read_config32(dev, 0xdc); - uint32_t cacheFlushOnHalt = dword & (7 << 16); - if (!cacheFlushOnHalt) { - c1 = 0x80; - } - } - dword = (c1 << 24) | (0xE641E6); - pci_write_config32(dev, 0x84, dword); - - /* FIXME: BKDG Table 100 says if the link is at a Gen1 - * frequency and the chipset does not support a 10us minimum LDTSTOP - * assertion time, then { If ASB2 && SVI then smaf001 = F6h else - * smaf001=87h. } else ... I hardly know what it means or how to check - * it from here, so I bluntly assume it is false and code here the else, - * which is easier - */ - - uint32_t smaf001 = 0xE6; - if (cpuRev & AMD_DR_Bx ) { - smaf001 = 0xA6; - } else { - #if 0 - if (cpuRev & (AMD_RB_C3 | AMD_DA_C3)) { - smaf001 = 0xF6; - } - #endif - } - uint32_t fidvidChange = 0; - if (((cpuRev & AMD_DA_Cx) && (procPkg & AMD_PKGTYPE_S1gX)) - || (cpuRev & AMD_RB_C3) ) { - fidvidChange=0x0B; - } - dword = (0xE6 << 24) | (fidvidChange << 16) - | (smaf001 << 8) | 0x81; - pci_write_config32(dev, 0x80, dword); - } -} - -void prep_fid_change(void) -{ - u32 dword; - u32 nodes; - pci_devfn_t dev; - int i; - - /* This needs to be run before any Pstate changes are requested */ - - nodes = get_nodes(); - - for (i = 0; i < nodes; i++) { - printk(BIOS_DEBUG, "Prep FID/VID Node:%02x\n", i); - dev = NODE_PCI(i, 3); - uint64_t cpuRev = mctGetLogicalCPUID(0xFF); - u8 procPkg = mctGetProcessorPackageType(); - - setVSRamp(dev); - /* BKDG r31116 2010-04-22 2.4.1.7 step b F3xD8[VSSlamTime] */ - /* Figure out the value for VsSlamTime and program it */ - recalculateVsSlamTimeSettingOnCorePre(dev); - - config_clk_power_ctrl_reg0(i,cpuRev,procPkg); - - config_power_ctrl_misc_reg(dev,cpuRev,procPkg); - config_nb_syn_ptr_adj(dev,cpuRev); - - config_acpi_pwr_state_ctrl_regs(dev,cpuRev,procPkg); - - dword = pci_read_config32(dev, 0x80); - printk(BIOS_DEBUG, " F3x80: %08x\n", dword); - dword = pci_read_config32(dev, 0x84); - printk(BIOS_DEBUG, " F3x84: %08x\n", dword); - dword = pci_read_config32(dev, 0xd4); - printk(BIOS_DEBUG, " F3xD4: %08x\n", dword); - dword = pci_read_config32(dev, 0xd8); - printk(BIOS_DEBUG, " F3xD8: %08x\n", dword); - dword = pci_read_config32(dev, 0xdc); - printk(BIOS_DEBUG, " F3xDC: %08x\n", dword); - } -} - -static void waitCurrentPstate(u32 target_pstate) { - msr_t initial_msr = rdmsr(TSC_MSR); - msr_t pstate_msr = rdmsr(PS_STS_REG); - msr_t tsc_msr; - u8 timedout; - - /* paranoia ? I fear when we run fixPsNbVidBeforeWR we can enter a - * P1 that is a copy of P0, therefore has the same NB DID but the - * TSC will count twice per tick, so we have to wait for twice the - * count to achieve the desired timeout. But I'm likely to - * misunderstand this... - */ - u32 corrected_timeout = ((pstate_msr.lo==1) - && (!(rdmsr(PSTATE_1_MSR).lo & NB_DID_M_ON))) ? - WAIT_PSTATE_TIMEOUT*2 : WAIT_PSTATE_TIMEOUT; - msr_t timeout; - - timeout.lo = initial_msr.lo + corrected_timeout; - timeout.hi = initial_msr.hi; - if ( (((u32)0xffffffff) - initial_msr.lo) < corrected_timeout ) { - timeout.hi++; - } - - // assuming TSC ticks at 1.25 ns per tick (800 MHz) - do { - pstate_msr = rdmsr(PS_STS_REG); - tsc_msr = rdmsr(TSC_MSR); - timedout = (tsc_msr.hi > timeout.hi) - || ((tsc_msr.hi == timeout.hi) && (tsc_msr.lo > timeout.lo )); - } while ( (pstate_msr.lo != target_pstate) && (! timedout) ); - - if (pstate_msr.lo != target_pstate) { - msr_t limit_msr = rdmsr(PS_LIM_REG); - printk(BIOS_ERR, "*** APIC ID %02x: timed out waiting for P-state %01x. Current P-state %01x P-state current limit MSRC001_0061=%08x %08x\n", - cpuid_ebx(0x00000001) >> 24, target_pstate, pstate_msr.lo, limit_msr.hi, limit_msr.lo); - - do { // should we just go on instead ? - pstate_msr = rdmsr(PS_STS_REG); - } while (pstate_msr.lo != target_pstate); - } -} - -static void set_pstate(u32 nonBoostedPState) { - msr_t msr; - uint8_t skip_wait; - - // Transition P0 for calling core. - msr = rdmsr(PS_CTL_REG); - - msr.lo = nonBoostedPState; - wrmsr(PS_CTL_REG, msr); - - if (is_fam15h()) { - /* Do not wait for the first (even) set of cores to transition on Family 15h systems */ - if ((cpuid_ebx(0x00000001) & 0x01000000)) - skip_wait = 0; - else - skip_wait = 1; - } else { - skip_wait = 0; - } - - if (!skip_wait) { - /* Wait for core to transition to P0 */ - waitCurrentPstate(nonBoostedPState); - } -} - -static void UpdateSinglePlaneNbVid(void) -{ - u32 nbVid, cpuVid; - u8 i; - msr_t msr; - - /* copy higher voltage (lower VID) of NBVID & CPUVID to both */ - for (i = 0; i < 5; i++) { - msr = rdmsr(PSTATE_0_MSR + i); - nbVid = (msr.lo & PS_CPU_VID_M_ON) >> PS_CPU_VID_SHFT; - cpuVid = (msr.lo & PS_NB_VID_M_ON) >> PS_NB_VID_SHFT; - - if (nbVid != cpuVid) { - if (nbVid > cpuVid) - nbVid = cpuVid; - - msr.lo = msr.lo & PS_BOTH_VID_OFF; - msr.lo = msr.lo | (u32) ((nbVid) << PS_NB_VID_SHFT); - msr.lo = msr.lo | (u32) ((nbVid) << PS_CPU_VID_SHFT); - wrmsr(PSTATE_0_MSR + i, msr); - } - } -} - -static void fixPsNbVidBeforeWR(u32 newNbVid, u32 coreid, u32 dev, u8 pviMode) -{ - msr_t msr; - u8 startup_pstate; - - /* This function sets NbVid before the warm reset. - * Get StartupPstate from MSRC001_0071. - * Read Pstate register pointed by [StartupPstate]. - * and copy its content to P0 and P1 registers. - * Copy newNbVid to P0[NbVid]. - * transition to P1 on all cores, - * then transition to P0 on core 0. - * Wait for MSRC001_0063[CurPstate] = 000b on core 0. - * see BKDG rev 3.48 2.4.2.9.1 BIOS NB COF and VID Configuration - * for SVI and Single-Plane PVI Systems - */ - - msr = rdmsr(MSR_COFVID_STS); - startup_pstate = (msr.hi >> (32 - 32)) & 0x07; - - /* Copy startup pstate to P1 and P0 MSRs. Set the maxvid for - * this node in P0. Then transition to P1 for corex and P0 - * for core0. These setting will be cleared by the warm reset - */ - msr = rdmsr(PSTATE_0_MSR + startup_pstate); - wrmsr(PSTATE_1_MSR, msr); - wrmsr(PSTATE_0_MSR, msr); - - /* missing step 2 from BDKG , F3xDC[PstateMaxVal] = - * max(1,F3xDC[PstateMaxVal] ) because it would take - * synchronization between cores and we don't think - * PstatMaxVal is going to be 0 on cold reset anyway ? - */ - if (!(pci_read_config32(dev, 0xdc) & (~PS_MAX_VAL_MASK))) { - printk(BIOS_ERR,"F3xDC[PstateMaxVal] is zero. Northbridge voltage setting will fail. fixPsNbVidBeforeWR in fidvid.c needs fixing. See AMD # 31116 rev 3.48 BKDG 2.4.2.9.1\n"); - }; - - msr.lo &= ~0xFE000000; // clear nbvid - msr.lo |= (newNbVid << 25); - wrmsr(PSTATE_0_MSR, msr); - - if (pviMode) { /* single plane*/ - UpdateSinglePlaneNbVid(); - } - - // Transition to P1 for all APs and P0 for core0. - set_pstate(1); - - if (coreid == 0) { - set_pstate(0); - } - - /* missing step 7 (restore PstateMax to 0 if needed) because - * we skipped step 2 - */ - -} - -static u32 needs_NB_COF_VID_update(void) -{ - u8 nb_cof_vid_update; - u8 nodes; - u8 i; - - if (is_fam15h()) - return 0; - - /* If any node has nb_cof_vid_update set all nodes need an update. */ - nodes = get_nodes(); - nb_cof_vid_update = 0; - for (i = 0; i < nodes; i++) { - uint64_t cpuRev = mctGetLogicalCPUID(i); - u32 nbCofVidUpdateDefined = (cpuRev & (AMD_FAM10_LT_D)); - if (nbCofVidUpdateDefined - && (pci_read_config32(NODE_PCI(i, 3), 0x1FC) - & NB_COF_VID_UPDATE_MASK)) { - nb_cof_vid_update = 1; - break; - } - } - return nb_cof_vid_update; -} - -static u32 init_fidvid_core(u32 nodeid, u32 coreid) -{ - pci_devfn_t dev; - u32 vid_max; - u32 fid_max = 0; - u8 nb_cof_vid_update = needs_NB_COF_VID_update(); - u8 pvimode; - u32 reg1fc; - - /* Steps 1-6 of BIOS NB COF and VID Configuration - * for SVI and Single-Plane PVI Systems. BKDG 2.4.2.9 #31116 rev 3.48 - */ - dev = NODE_PCI(nodeid, 3); - if (is_fam15h()) - pvimode = 0; - else - pvimode = pci_read_config32(dev, PW_CTL_MISC) & PVI_MODE; - reg1fc = pci_read_config32(dev, 0x1FC); - - if (nb_cof_vid_update) { - vid_max = (reg1fc & SINGLE_PLANE_NB_VID_MASK ) >> SINGLE_PLANE_NB_VID_SHIFT; - fid_max = (reg1fc & SINGLE_PLANE_NB_FID_MASK ) >> SINGLE_PLANE_NB_FID_SHIFT; - - if (!pvimode) { /* SVI, dual power plane */ - vid_max = vid_max - ((reg1fc & DUAL_PLANE_NB_VID_OFF_MASK ) >> DUAL_PLANE_NB_VID_SHIFT ); - fid_max = fid_max + ((reg1fc & DUAL_PLANE_NB_FID_OFF_MASK ) >> DUAL_PLANE_NB_FID_SHIFT ); - } - /* write newNbVid to P-state Reg's NbVid always if NbVidUpdatedAll=1 */ - fixPsNbVidBeforeWR(vid_max, coreid, dev, pvimode); - - /* fid setup is handled by the BSP at the end. */ - - } else { /* ! nb_cof_vid_update */ - /* Use max values */ - if (pvimode) - UpdateSinglePlaneNbVid(); - } - - return ((nb_cof_vid_update << 16) | (fid_max << 8)); - -} - -static void init_fidvid_ap(u32 apicid, u32 nodeid, u32 coreid) -{ - u32 send; - - printk(BIOS_DEBUG, "FIDVID on AP: %02x\n", apicid); - - send = init_fidvid_core(nodeid, coreid); - send |= (apicid << 24); // ap apicid - - // Send signal to BSP about this AP max fid - // This also indicates this AP is ready for warm reset (if required). - lapic_write(LAPIC_MSG_REG, send | F10_APSTATE_RESET); -} - -static u32 calc_common_fid(u32 fid_packed, u32 fid_packed_new) -{ - u32 fidmax; - u32 fidmax_new; - - fidmax = (fid_packed >> 8) & 0xFF; - - fidmax_new = (fid_packed_new >> 8) & 0xFF; - - if (fidmax > fidmax_new) { - fidmax = fidmax_new; - } - - fid_packed &= 0xFF << 16; - fid_packed |= (fidmax << 8); - fid_packed |= fid_packed_new & (0xFF << 16); // set nb_cof_vid_update - - return fid_packed; -} - -static void init_fidvid_bsp_stage1(u32 ap_apicid, void *gp) -{ - u32 readback = 0; - u32 timeout = 1; - - struct fidvid_st *fvp = gp; - int loop; - - print_debug_fv("Wait for AP stage 1: ap_apicid = ", ap_apicid); - - loop = 100000; - while (--loop > 0) { - if (lapic_remote_read(ap_apicid, LAPIC_MSG_REG, &readback) != 0) - continue; - if (((readback & 0x3f) == F10_APSTATE_RESET) - || (is_fam15h() && ((readback & 0x3f) == F10_APSTATE_ASLEEP))) { - timeout = 0; - break; /* target ap is in stage 1 */ - } - } - - if (timeout) { - printk(BIOS_DEBUG, "%s: timed out reading from ap %02x\n", - __func__, ap_apicid); - return; - } - - print_debug_fv("\treadback = ", readback); - - fvp->common_fid = calc_common_fid(fvp->common_fid, readback); - - print_debug_fv("\tcommon_fid(packed) = ", fvp->common_fid); - -} - -static void fixPsNbVidAfterWR(u32 newNbVid, u8 NbVidUpdatedAll,u8 pviMode) -{ - msr_t msr; - u8 i; - u8 StartupPstate; - - /* BKDG 2.4.2.9.1 11-12 - * This function copies newNbVid to NbVid bits in P-state - * Registers[4:0] if its NbDid bit=0, and IddValue!=0 in case of - * NbVidUpdatedAll =0 or copies newNbVid to NbVid bits in - * P-state Registers[4:0] if its IddValue!=0 in case of - * NbVidUpdatedAll=1. Then transition to StartPstate. - */ - - /* write newNbVid to P-state Reg's NbVid if its NbDid=0 */ - for (i = 0; i < 5; i++) { - msr = rdmsr(PSTATE_0_MSR + i); - /* NbDid (bit 22 of P-state Reg) == 0 or NbVidUpdatedAll = 1 */ - if ( (msr.hi & PS_IDD_VALUE_MASK) - && (msr.hi & PS_EN_MASK) - &&(((msr.lo & PS_NB_DID_MASK) == 0) || NbVidUpdatedAll)) { - msr.lo &= PS_NB_VID_M_OFF; - msr.lo |= (newNbVid & 0x7F) << PS_NB_VID_SHFT; - wrmsr(PSTATE_0_MSR + i, msr); - } - } - - /* Not documented. Would overwrite Nb_Vids just copied - * should we just update cpu_vid or nothing at all ? - */ - if (pviMode) { //single plane - UpdateSinglePlaneNbVid(); - } - /* For each core in the system, transition all cores to StartupPstate */ - msr = rdmsr(MSR_COFVID_STS); - StartupPstate = msr.hi & 0x07; - - /* Set and wait for StartupPstate to set. */ - set_pstate(StartupPstate); - -} - -static void finalPstateChange(void) -{ - /* Enable P0 on all cores for best performance. - * Linux can slow them down later if need be. - * It is safe since they will be in C1 halt - * most of the time anyway. - */ - set_pstate(0); -} - -void init_fidvid_stage2(u32 apicid, u32 nodeid) -{ - msr_t msr; - pci_devfn_t dev; - u32 reg1fc; - u32 dtemp; - u32 nbvid; - u8 nb_cof_vid_update = needs_NB_COF_VID_update(); - u8 NbVidUpdateAll; - u8 pvimode; - - /* After warm reset finish the fid/vid setup for all cores. */ - - /* If any node has nb_cof_vid_update set all nodes need an update. */ - - dev = NODE_PCI(nodeid, 3); - if (is_fam15h()) - pvimode = 0; - else - pvimode = (pci_read_config32(dev, 0xA0) >> 8) & 1; - reg1fc = pci_read_config32(dev, 0x1FC); - nbvid = (reg1fc >> 7) & 0x7F; - NbVidUpdateAll = (reg1fc >> 1) & 1; - - if (nb_cof_vid_update) { - if (!pvimode) { /* SVI */ - nbvid = nbvid - ((reg1fc >> 17) & 0x1F); - } - /* write newNbVid to P-state Reg's NbVid if its NbDid=0 */ - fixPsNbVidAfterWR(nbvid, NbVidUpdateAll,pvimode); - } else { /* !nb_cof_vid_update */ - if (pvimode) - UpdateSinglePlaneNbVid(); - } - dtemp = pci_read_config32(dev, 0xA0); - dtemp &= PLLLOCK_OFF; - dtemp |= PLLLOCK_DFT_L; - pci_write_config32(dev, 0xA0, dtemp); - - dualPlaneOnly(dev); - applyBoostFIDOffset(dev, nodeid); - enableNbPState1(dev); - - finalPstateChange(); - - if (!is_fam15h()) { - /* Set TSC to tick at the P0 ndfid rate */ - msr = rdmsr(HWCR_MSR); - msr.lo |= 1 << 24; - wrmsr(HWCR_MSR, msr); - } -} - - -#if CONFIG(SET_FIDVID_STORE_AP_APICID_AT_FIRST) -struct ap_apicid_st { - u32 num; - // it could use 256 bytes for 64 node quad core system - u8 apicid[NODE_NUMS * 4]; -}; - -static void store_ap_apicid(unsigned int ap_apicid, void *gp) -{ - struct ap_apicid_st *p = gp; - - p->apicid[p->num++] = ap_apicid; - -} -#endif - - -int init_fidvid_bsp(u32 bsp_apicid, u32 nodes) -{ -#if CONFIG(SET_FIDVID_STORE_AP_APICID_AT_FIRST) - struct ap_apicid_st ap_apicidx; - u32 i; -#endif - struct fidvid_st fv; - - printk(BIOS_DEBUG, "FIDVID on BSP, APIC_id: %02x\n", bsp_apicid); - - /* Steps 1-6 of BIOS NB COF and VID Configuration - * for SVI and Single-Plane PVI Systems. - */ - fv.common_fid = init_fidvid_core(0, 0); - - print_debug_fv("BSP fid = ", fv.common_fid); - -#if CONFIG(SET_FIDVID_STORE_AP_APICID_AT_FIRST) && \ - !CONFIG(SET_FIDVID_CORE0_ONLY) - /* For all APs (We know the APIC ID of all APs even when the APIC ID - is lifted) remote read from AP LAPIC_MSG_REG about max fid. - Then calculate the common max fid that can be used for all - APs and BSP */ - ap_apicidx.num = 0; - - for_each_ap(bsp_apicid, CONFIG_SET_FIDVID_CORE_RANGE, -1, store_ap_apicid, &ap_apicidx); - - for (i = 0; i < ap_apicidx.num; i++) { - init_fidvid_bsp_stage1(ap_apicidx.apicid[i], &fv); - } -#else - for_each_ap(bsp_apicid, CONFIG(SET_FIDVID_CORE0_ONLY), -1, init_fidvid_bsp_stage1, &fv); -#endif - - print_debug_fv("common_fid = ", fv.common_fid); - - if (fv.common_fid & (1 << 16)) { /* check nb_cof_vid_update */ - - // Enable the common fid and other settings. - enable_fid_change((fv.common_fid >> 8) & 0x1F); - - // nbfid change need warm reset, so reset at first - return 1; - } - - return 0; // No FID/VID changes. Don't reset -} diff --git a/src/cpu/amd/family_10h-family_15h/init_cpus.c b/src/cpu/amd/family_10h-family_15h/init_cpus.c deleted file mode 100644 index ae04f2aace..0000000000 --- a/src/cpu/amd/family_10h-family_15h/init_cpus.c +++ /dev/null @@ -1,1849 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include -#include - -#include "init_cpus.h" - -#if CONFIG(HAVE_OPTION_TABLE) -#include "option_table.h" -#endif -#include - -#include -#include -#include -#include - -#include - -#include "cpu/amd/car/disable_cache_as_ram.c" - -#if CONFIG(PCI_IO_CFG_EXT) -static void set_EnableCf8ExtCfg(void) -{ - // set the NB_CFG_MSR[46]=1; - msr_t msr; - msr = rdmsr(NB_CFG_MSR); - // EnableCf8ExtCfg: We need that to access CONFIG_PCI_IO_CFG_EXT 4K range - msr.hi |= (1 << (46 - 32)); - wrmsr(NB_CFG_MSR, msr); -} -#else -static void set_EnableCf8ExtCfg(void) { } -#endif - -// #define DEBUG_HT_SETUP 1 -// #define FAM10_AP_NODE_SEQUENTIAL_START 1 - -uint32_t get_boot_apic_id(uint8_t node, uint32_t core) { - uint32_t ap_apicid; - - uint32_t nb_cfg_54; - uint32_t siblings; - uint32_t cores_found; - - uint8_t fam15h = 0; - uint8_t rev_gte_d = 0; - uint8_t dual_node = 0; - uint32_t f3xe8; - uint32_t family; - uint32_t model; - - uint32_t ApicIdCoreIdSize; - - /* Assume that all node are same stepping, otherwise we can use use - nb_cfg_54 from bsp for all nodes */ - nb_cfg_54 = read_nb_cfg_54(); - f3xe8 = pci_read_config32(NODE_PCI(0, 3), 0xe8); - - family = model = cpuid_eax(0x80000001); - model = ((model & 0xf0000) >> 12) | ((model & 0xf0) >> 4); - family = ((family & 0xf00000) >> 16) | ((family & 0xf00) >> 8); - - if (family >= 0x6f) { - /* Family 15h or later */ - fam15h = 1; - nb_cfg_54 = 1; - } - - if ((model >= 0x8) || fam15h) - /* Revision D or later */ - rev_gte_d = 1; - - if (rev_gte_d) - /* Check for dual node capability */ - if (f3xe8 & 0x20000000) - dual_node = 1; - - ApicIdCoreIdSize = (cpuid_ecx(0x80000008) >> 12 & 0xf); - if (ApicIdCoreIdSize) { - siblings = ((1 << ApicIdCoreIdSize) - 1); - } else { - siblings = 3; //quad core - } - - cores_found = get_core_num_in_bsp(node); - if (siblings > cores_found) - siblings = cores_found; - - if (dual_node) { - ap_apicid = 0; - if (fam15h) { - ap_apicid |= ((node >> 1) & 0x3) << 5; /* Node ID */ - ap_apicid |= ((node & 0x1) * (siblings + 1)) + core; /* Core ID */ - } else { - if (nb_cfg_54) { - ap_apicid |= ((node >> 1) & 0x3) << 4; /* Node ID */ - ap_apicid |= ((node & 0x1) * (siblings + 1)) + core; /* Core ID */ - } else { - ap_apicid |= node & 0x3; /* Node ID */ - ap_apicid |= (((node & 0x1) * (siblings + 1)) + core) << 4; /* Core ID */ - } - } - } else { - if (fam15h) { - ap_apicid = 0; - ap_apicid |= (node & 0x7) << 4; /* Node ID */ - ap_apicid |= core & 0xf; /* Core ID */ - } else { - ap_apicid = node * (nb_cfg_54 ? (siblings + 1) : 1) + - core * (nb_cfg_54 ? 1 : 64); - } - } - - printk(BIOS_DEBUG, "%s: using %d as APIC ID for node %d, core %d\n", __func__, ap_apicid, node, core); - - return ap_apicid; -} - -//core_range = 0 : all cores -//core range = 1 : core 0 only -//core range = 2 : cores other than core0 - -static void for_each_ap(uint32_t bsp_apicid, uint32_t core_range, int8_t node, - process_ap_t process_ap, void *gp) -{ - // here assume the OS don't change our apicid - u32 ap_apicid; - - u32 nodes; - u32 disable_siblings; - u32 cores_found; - int i, j; - - /* get_nodes define in ht_wrapper.c */ - nodes = get_nodes(); - - if (!CONFIG(LOGICAL_CPUS) || - read_option(multi_core, 0) != 0) { // 0 means multi core - disable_siblings = 1; - } else { - disable_siblings = 0; - } - - for (i = 0; i < nodes; i++) { - if ((node >= 0) && (i != node)) - continue; - - cores_found = get_core_num_in_bsp(i); - - u32 jstart, jend; - - if (core_range == 2) { - jstart = 1; - } else { - jstart = 0; - } - - if (disable_siblings || (core_range == 1)) { - jend = 0; - } else { - jend = cores_found; - } - - for (j = jstart; j <= jend; j++) { - ap_apicid = get_boot_apic_id(i, j); - -#if CONFIG(ENABLE_APIC_EXT_ID) && (CONFIG_APIC_ID_OFFSET > 0) -#if !CONFIG(LIFT_BSP_APIC_ID) - if ((i != 0) || (j != 0)) /* except bsp */ -#endif - ap_apicid += CONFIG_APIC_ID_OFFSET; -#endif - - if (ap_apicid == bsp_apicid) - continue; - - process_ap(ap_apicid, gp); - - } - } -} - -static inline int lapic_remote_read(int apicid, int reg, u32 *pvalue) -{ - int timeout; - u32 status; - int result; - lapic_wait_icr_idle(); - lapic_write(LAPIC_ICR2, SET_LAPIC_DEST_FIELD(apicid)); - lapic_write(LAPIC_ICR, LAPIC_DM_REMRD | (reg >> 4)); - -/* Extra busy check compared to lapic.h */ - timeout = 0; - do { - status = lapic_read(LAPIC_ICR) & LAPIC_ICR_BUSY; - } while (status == LAPIC_ICR_BUSY && timeout++ < 1000); - - timeout = 0; - do { - status = lapic_read(LAPIC_ICR) & LAPIC_ICR_RR_MASK; - } while (status == LAPIC_ICR_RR_INPROG && timeout++ < 1000); - - result = -1; - - if (status == LAPIC_ICR_RR_VALID) { - *pvalue = lapic_read(LAPIC_RRR); - result = 0; - } - return result; -} - -#if CONFIG(SET_FIDVID) -static void init_fidvid_ap(u32 apicid, u32 nodeid, u32 coreid); -#endif - -static __always_inline -void print_apicid_nodeid_coreid(u32 apicid, struct node_core_id id, - const char *str) -{ - printk(BIOS_DEBUG, - "%s --- { APICID = %02x NODEID = %02x COREID = %02x} ---\n", str, - apicid, id.nodeid, id.coreid); -} - -uint32_t wait_cpu_state(uint32_t apicid, uint32_t state, uint32_t state2) -{ - u32 readback = 0; - u32 timeout = 1; - int loop = 4000000; - while (--loop > 0) { - if (lapic_remote_read(apicid, LAPIC_MSG_REG, &readback) != 0) - continue; - if ((readback & 0x3f) == state || (readback & 0x3f) == state2 || (readback & 0x3f) == F10_APSTATE_RESET) { - timeout = 0; - break; //target CPU is in stage started - } - } - if (timeout) { - if (readback) { - timeout = readback; - } - } - - return timeout; -} - -static void wait_ap_started(u32 ap_apicid, void *gp) -{ - u32 timeout; - timeout = wait_cpu_state(ap_apicid, F10_APSTATE_STARTED, F10_APSTATE_ASLEEP); - printk(BIOS_DEBUG, "* AP %02x", ap_apicid); - if (timeout) { - printk(BIOS_DEBUG, " timed out:%08x\n", timeout); - } else { - printk(BIOS_DEBUG, "started\n"); - } -} - -void wait_all_other_cores_started(u32 bsp_apicid) -{ - // all aps other than core0 - printk(BIOS_DEBUG, "started ap apicid: "); - for_each_ap(bsp_apicid, 2, -1, wait_ap_started, (void *)0); - printk(BIOS_DEBUG, "\n"); -} - -void allow_all_aps_stop(u32 bsp_apicid) -{ - /* Called by the BSP to indicate AP can stop */ - - /* FIXME Do APs use this? */ - - // allow aps to stop use 6 bits for state - lapic_write(LAPIC_MSG_REG, (bsp_apicid << 24) | F10_APSTATE_STOPPED); -} - -static void wait_ap_stopped(u32 ap_apicid, void *gp) -{ - u32 timeout; - timeout = wait_cpu_state(ap_apicid, F10_APSTATE_ASLEEP, F10_APSTATE_ASLEEP); - printk(BIOS_DEBUG, "* AP %02x", ap_apicid); - if (timeout) { - printk(BIOS_DEBUG, " timed out:%08x\n", timeout); - } else { - printk(BIOS_DEBUG, "stopped\n"); - } -} - -void wait_all_other_cores_stopped(u32 bsp_apicid) -{ - // all aps other than core0 - printk(BIOS_DEBUG, "stopped ap apicid: "); - for_each_ap(bsp_apicid, 2, -1, wait_ap_stopped, (void *)0); - printk(BIOS_DEBUG, "\n"); -} - -static void enable_apic_ext_id(u32 node) -{ - u32 val; - - val = pci_read_config32(NODE_HT(node), 0x68); - val |= (HTTC_APIC_EXT_SPUR | HTTC_APIC_EXT_ID | HTTC_APIC_EXT_BRD_CST); - pci_write_config32(NODE_HT(node), 0x68, val); -} - -static void STOP_CAR_AND_CPU(uint8_t skip_sharedc_config, uint32_t apicid) -{ - msr_t msr; - uint32_t family; - - family = amd_fam1x_cpu_family(); // inline - - if (family < 0x6f) { - /* Family 10h or earlier */ - - /* Disable L2 IC to L3 connection (Only for CAR) */ - msr = rdmsr(BU_CFG2_MSR); - msr.lo &= ~(1 << ClLinesToNbDis); - wrmsr(BU_CFG2_MSR, msr); - } else { - /* Family 15h or later - * DRAM setup is delayed on Fam15 in order to prevent - * any DRAM access before ECC check bits are initialized. - * Each core also needs to have its initial DRAM map initialized - * before it is put to sleep, otherwise it will fail to wake - * in ramstage. To meet both of these goals, delay DRAM map - * setup until the last possible moment, where speculative - * memory access is highly unlikely before core halt... - */ - if (!skip_sharedc_config) { - /* Enable memory access for first MBs using top_mem */ - msr.hi = 0; - msr.lo = (CONFIG_RAMTOP + TOP_MEM_MASK) & (~TOP_MEM_MASK); - wrmsr(TOP_MEM, msr); - } - } - - disable_cache_as_ram_real(skip_sharedc_config); // inline - - /* Mark the core as sleeping */ - lapic_write(LAPIC_MSG_REG, (apicid << 24) | F10_APSTATE_ASLEEP); - - /* stop all cores except node0/core0 the bsp .... */ - stop_this_cpu(); -} - -u32 init_cpus(u32 cpu_init_detectedx, struct sys_info *sysinfo) -{ - uint32_t bsp_apicid = 0; - uint32_t apicid; - uint32_t dword; - uint8_t set_mtrrs; - uint8_t node_count; - uint8_t fam15_bsp_core1_apicid; - struct node_core_id id; - - /* Please refer to the calculations and explaination in cache_as_ram.inc - * before modifying these values */ - uint32_t max_ap_stack_region_size = CONFIG_MAX_CPUS * CONFIG_DCACHE_AP_STACK_SIZE; - uint32_t max_bsp_stack_region_size = CONFIG_DCACHE_BSP_TOP_STACK_SIZE + - CONFIG_DCACHE_BSP_TOP_STACK_SLUSH; - uint32_t bsp_stack_region_upper_boundary = CONFIG_DCACHE_RAM_BASE + - CONFIG_DCACHE_RAM_SIZE; - uint32_t bsp_stack_region_lower_boundary = bsp_stack_region_upper_boundary - - max_bsp_stack_region_size; - - void *lower_stack_region_boundary = (void *)(bsp_stack_region_lower_boundary - - max_ap_stack_region_size); - - if (((void*)(sysinfo + 1)) > lower_stack_region_boundary) - printk(BIOS_WARNING, - "sysinfo extends into stack region (sysinfo range: [%p,%p] lower stack region boundary: %p)\n", - sysinfo, sysinfo + 1, lower_stack_region_boundary); - - /* - * already set early mtrr in cache_as_ram.inc - */ - - /* that is from initial apicid, we need nodeid and coreid - later */ - id = get_node_core_id_x(); - - /* NB_CFG MSR is shared between cores, so we need make sure - core0 is done at first --- use wait_all_core0_started */ - if (id.coreid == 0) { - /* Set InitApicIdCpuIdLo / EnableCf8ExtCfg on core0 only */ - if (!is_fam15h()) - set_apicid_cpuid_lo(); - set_EnableCf8ExtCfg(); -#if CONFIG(ENABLE_APIC_EXT_ID) - enable_apic_ext_id(id.nodeid); -#endif - } - - enable_lapic(); - -#if CONFIG(ENABLE_APIC_EXT_ID) && (CONFIG_APIC_ID_OFFSET > 0) - u32 initial_apicid = get_initial_apicid(); - -#if !CONFIG(LIFT_BSP_APIC_ID) - if (initial_apicid != 0) // other than bsp -#endif - { - /* use initial APIC id to lift it */ - u32 dword = lapic_read(LAPIC_ID); - dword &= ~(0xff << 24); - dword |= - (((initial_apicid + CONFIG_APIC_ID_OFFSET) & 0xff) << 24); - - lapic_write(LAPIC_ID, dword); - } -#if CONFIG(LIFT_BSP_APIC_ID) - bsp_apicid += CONFIG_APIC_ID_OFFSET; -#endif - -#endif - - /* get the apicid, it may be lifted already */ - apicid = lapicid(); - - // show our apicid, nodeid, and coreid - if (id.coreid == 0) { - if (id.nodeid != 0) //all core0 except bsp - print_apicid_nodeid_coreid(apicid, id, " core0: "); - } else { //all other cores - print_apicid_nodeid_coreid(apicid, id, " corex: "); - } - - if (cpu_init_detectedx) { - print_apicid_nodeid_coreid(apicid, id, - "\n\n\nINIT detected from "); - printk(BIOS_DEBUG, "\nIssuing SOFT_RESET...\n"); - soft_reset(); - } - - if (id.coreid == 0) { - if (!(warm_reset_detect(id.nodeid))) //FIXME: INIT is checked above but check for more resets? - distinguish_cpu_resets(id.nodeid); // Also indicates we are started - } - // Mark the core as started. - lapic_write(LAPIC_MSG_REG, (apicid << 24) | F10_APSTATE_STARTED); - printk(BIOS_DEBUG, "CPU APICID %02x start flag set\n", apicid); - - if (apicid != bsp_apicid) { - /* Setup each AP's cores MSRs. - * This happens after HTinit. - * The BSP runs this code in it's own path. - */ - update_microcode(cpuid_eax(1)); - - cpuSetAMDMSR(id.nodeid); - - /* Set up HyperTransport probe filter support */ - if (is_gt_rev_d()) { - dword = pci_read_config32(NODE_PCI(id.nodeid, 0), 0x60); - node_count = ((dword >> 4) & 0x7) + 1; - - if (node_count > 1) { - msr_t msr = rdmsr(BU_CFG2_MSR); - msr.hi |= 1 << (42 - 32); - wrmsr(BU_CFG2_MSR, msr); - } - } - -#if CONFIG(SET_FIDVID) -#if CONFIG(LOGICAL_CPUS) && CONFIG(SET_FIDVID_CORE0_ONLY) - // Run on all AP for proper FID/VID setup. - if (id.coreid == 0) // only need set fid for core0 -#endif - { - // check warm(bios) reset to call stage2 otherwise do stage1 - if (warm_reset_detect(id.nodeid)) { - printk(BIOS_DEBUG, - "init_fidvid_stage2 apicid: %02x\n", - apicid); - init_fidvid_stage2(apicid, id.nodeid); - } else { - printk(BIOS_DEBUG, - "init_fidvid_ap(stage1) apicid: %02x\n", - apicid); - init_fidvid_ap(apicid, id.nodeid, id.coreid); - } - } -#endif - - if (is_fam15h()) { - /* core 1 on node 0 is special; to avoid corrupting the - * BSP do not alter MTRRs on that core */ - fam15_bsp_core1_apicid = 1; - if (CONFIG(ENABLE_APIC_EXT_ID) && (CONFIG_APIC_ID_OFFSET > 0)) - fam15_bsp_core1_apicid += CONFIG_APIC_ID_OFFSET; - - if (apicid == fam15_bsp_core1_apicid) - set_mtrrs = 0; - else - set_mtrrs = !!(apicid & 0x1); - } else { - set_mtrrs = 1; - } - - /* AP is ready, configure MTRRs and go to sleep */ - if (set_mtrrs) - set_var_mtrr(0, 0x00000000, CACHE_TMP_RAMTOP, MTRR_TYPE_WRBACK); - - printk(BIOS_DEBUG, "Disabling CAR on AP %02x\n", apicid); - if (is_fam15h()) { - /* Only modify the MSRs on the odd cores (the last cores to finish booting) */ - STOP_CAR_AND_CPU(!set_mtrrs, apicid); - } else { - /* Modify MSRs on all cores */ - STOP_CAR_AND_CPU(0, apicid); - } - - printk(BIOS_DEBUG, - "\nAP %02x should be halted but you are reading this....\n", - apicid); - } - - return bsp_apicid; -} - -static u32 is_core0_started(u32 nodeid) -{ - u32 htic; - pci_devfn_t device; - device = NODE_PCI(nodeid, 0); - htic = pci_read_config32(device, HT_INIT_CONTROL); - htic &= HTIC_ColdR_Detect; - return htic; -} - -void wait_all_core0_started(void) -{ - /* When core0 is started, it will distingush_cpu_resets - * So wait for that to finish */ - u32 i; - u32 nodes = get_nodes(); - - printk(BIOS_DEBUG, "core0 started: "); - for (i = 1; i < nodes; i++) { // skip bsp, because it is running on bsp - while (!is_core0_started(i)) { - } - printk(BIOS_DEBUG, " %02x", i); - } - printk(BIOS_DEBUG, "\n"); -} - -#if CONFIG_MAX_PHYSICAL_CPUS > 1 -/** - * void start_node(u32 node) - * - * start the core0 in node, so it can generate HT packet to feature code. - * - * This function starts the AP nodes core0s. wait_all_core0_started() in - * romstage.c waits for all the AP to be finished before continuing - * system init. - */ -static void start_node(u8 node) -{ - u32 val; - - /* Enable routing table */ - printk(BIOS_DEBUG, "Start node %02x", node); - -#if 0 - /* For FAM10 support, we need to set Dram base/limit for the new node */ - pci_write_config32(NODE_MP(node), 0x44, 0); - pci_write_config32(NODE_MP(node), 0x40, 3); -#endif - - /* Allow APs to make requests (ROM fetch) */ - val = pci_read_config32(NODE_HT(node), 0x6c); - val &= ~(1 << 1); - pci_write_config32(NODE_HT(node), 0x6c, val); - - printk(BIOS_DEBUG, " done.\n"); -} - -/** - * static void setup_remote_node(u32 node) - * - * Copy the BSP Address Map to each AP. - */ -static void setup_remote_node(u8 node) -{ - /* There registers can be used with F1x114_x Address Map at the - same time, So must set them even 32 node */ - static const u16 pci_reg[] = { - /* DRAM Base/Limits Registers */ - 0x44, 0x4c, 0x54, 0x5c, 0x64, 0x6c, 0x74, 0x7c, - 0x40, 0x48, 0x50, 0x58, 0x60, 0x68, 0x70, 0x78, - 0x144, 0x14c, 0x154, 0x15c, 0x164, 0x16c, 0x174, 0x17c, - 0x140, 0x148, 0x150, 0x158, 0x160, 0x168, 0x170, 0x178, - /* MMIO Base/Limits Registers */ - 0x84, 0x8c, 0x94, 0x9c, 0xa4, 0xac, 0xb4, 0xbc, - 0x80, 0x88, 0x90, 0x98, 0xa0, 0xa8, 0xb0, 0xb8, - /* IO Base/Limits Registers */ - 0xc4, 0xcc, 0xd4, 0xdc, - 0xc0, 0xc8, 0xd0, 0xd8, - /* Configuration Map Registers */ - 0xe0, 0xe4, 0xe8, 0xec, - }; - u16 i; - - printk(BIOS_DEBUG, "setup_remote_node: %02x", node); - - /* copy the default resource map from node 0 */ - for (i = 0; i < ARRAY_SIZE(pci_reg); i++) { - u32 value; - u16 reg; - reg = pci_reg[i]; - value = pci_read_config32(NODE_MP(0), reg); - pci_write_config32(NODE_MP(node), reg, value); - - } - printk(BIOS_DEBUG, " done\n"); -} -#endif /* CONFIG_MAX_PHYSICAL_CPUS > 1 */ - -//it is running on core0 of node0 -void start_other_cores(uint32_t bsp_apicid) -{ - u32 nodes; - u32 nodeid; - - // disable multi_core - if (read_option(multi_core, 0) != 0) { - printk(BIOS_DEBUG, "Skip additional core init\n"); - return; - } - - nodes = get_nodes(); - - for (nodeid = 0; nodeid < nodes; nodeid++) { - u32 cores = get_core_num_in_bsp(nodeid); - printk(BIOS_DEBUG, "init node: %02x cores: %02x pass 1\n", nodeid, cores); - if (cores > 0) { - real_start_other_core(nodeid, cores); -#ifdef FAM10_AP_NODE_SEQUENTIAL_START - printk(BIOS_DEBUG, "waiting for core start on node %d...\n", nodeid); - for_each_ap(bsp_apicid, 2, nodeid, wait_ap_started, (void *)0); - printk(BIOS_DEBUG, "...started\n"); -#endif - } - } -} - -static void AMD_Errata281(u8 node, uint64_t revision, u32 platform) -{ - /* Workaround for Transaction Scheduling Conflict in - * Northbridge Cross Bar. Implement XCS Token adjustment - * for ganged links. Also, perform fix up for the mixed - * revision case. - */ - - u32 reg, val; - u8 i; - u8 mixed = 0; - u8 nodes = get_nodes(); - - if (platform & AMD_PTYPE_SVR) { - /* For each node we need to check for a "broken" node */ - if (!(revision & (AMD_DR_B0 | AMD_DR_B1))) { - for (i = 0; i < nodes; i++) { - if (mctGetLogicalCPUID(i) & - (AMD_DR_B0 | AMD_DR_B1)) { - mixed = 1; - break; - } - } - } - - if ((revision & (AMD_DR_B0 | AMD_DR_B1)) || mixed) { - - /* F0X68[22:21] DsNpReqLmt0 = 01b */ - val = pci_read_config32(NODE_PCI(node, 0), 0x68); - val &= ~0x00600000; - val |= 0x00200000; - pci_write_config32(NODE_PCI(node, 0), 0x68, val); - - /* F3X6C */ - val = pci_read_config32(NODE_PCI(node, 3), 0x6C); - val &= ~0x700780F7; - val |= 0x00010094; - pci_write_config32(NODE_PCI(node, 3), 0x6C, val); - - /* F3X7C */ - val = pci_read_config32(NODE_PCI(node, 3), 0x7C); - val &= ~0x707FFF1F; - val |= 0x00144514; - pci_write_config32(NODE_PCI(node, 3), 0x7C, val); - - /* F3X144[3:0] RspTok = 0001b */ - val = pci_read_config32(NODE_PCI(node, 3), 0x144); - val &= ~0x0000000F; - val |= 0x00000001; - pci_write_config32(NODE_PCI(node, 3), 0x144, val); - - for (i = 0; i < 3; i++) { - reg = 0x148 + (i * 4); - val = pci_read_config32(NODE_PCI(node, 3), reg); - val &= ~0x000000FF; - val |= 0x000000DB; - pci_write_config32(NODE_PCI(node, 3), reg, val); - } - } - } -} - -static void AMD_Errata298(void) -{ - /* Workaround for L2 Eviction May Occur during operation to - * set Accessed or dirty bit. - */ - - msr_t msr; - u8 i; - u8 affectedRev = 0; - u8 nodes = get_nodes(); - - /* For each core we need to check for a "broken" node */ - for (i = 0; i < nodes; i++) { - if (mctGetLogicalCPUID(i) & (AMD_DR_B0 | AMD_DR_B1 | AMD_DR_B2)) { - affectedRev = 1; - break; - } - } - - if (affectedRev) { - msr = rdmsr(HWCR_MSR); - msr.lo |= 0x08; /* Set TlbCacheDis bit[3] */ - wrmsr(HWCR_MSR, msr); - - msr = rdmsr(BU_CFG_MSR); - msr.lo |= 0x02; /* Set TlbForceMemTypeUc bit[1] */ - wrmsr(BU_CFG_MSR, msr); - - msr = rdmsr(OSVW_ID_Length); - msr.lo |= 0x01; /* OS Visible Workaround - MSR */ - wrmsr(OSVW_ID_Length, msr); - - msr = rdmsr(OSVW_Status); - msr.lo |= 0x01; /* OS Visible Workaround - MSR */ - wrmsr(OSVW_Status, msr); - } - - if (!affectedRev && (mctGetLogicalCPUID(0xFF) & AMD_DR_B3)) { - msr = rdmsr(OSVW_ID_Length); - msr.lo |= 0x01; /* OS Visible Workaround - MSR */ - wrmsr(OSVW_ID_Length, msr); - - } -} - -static u32 get_platform_type(void) -{ - u32 ret = 0; - - switch (SYSTEM_TYPE) { - case 1: - ret |= AMD_PTYPE_DSK; - break; - case 2: - ret |= AMD_PTYPE_MOB; - break; - case 0: - ret |= AMD_PTYPE_SVR; - break; - default: - break; - } - - /* FIXME: add UMA support. */ - - /* All Fam10 are multi core */ - ret |= AMD_PTYPE_MC; - - return ret; -} - -static void AMD_SetupPSIVID_d(u32 platform_type, u8 node) -{ - u32 dword; - int i; - msr_t msr; - - if (platform_type & (AMD_PTYPE_MOB | AMD_PTYPE_DSK)) { - - /* The following code sets the PSIVID to the lowest support P state - * assuming that the VID for the lowest power state is below - * the VDD voltage regulator threshold. (This also assumes that there - * is a Pstate lower than P0) - */ - - for (i = 4; i >= 0; i--) { - msr = rdmsr(PSTATE_0_MSR + i); - /* Pstate valid? */ - if (msr.hi & PS_EN_MASK) { - dword = pci_read_config32(NODE_PCI(i, 3), 0xA0); - dword &= ~0x7F; - dword |= (msr.lo >> 9) & 0x7F; - pci_write_config32(NODE_PCI(i, 3), 0xA0, dword); - break; - } - } - } -} - -/** - * AMD_CpuFindCapability - Traverse PCI capability list to find host HT links. - * HT Phy operations are not valid on links that aren't present, so this - * prevents invalid accesses. - * - * Returns the offset of the link register. - */ -static BOOL AMD_CpuFindCapability(u8 node, u8 cap_count, u8 *offset) -{ - u32 reg; - u32 val; - - /* get start of CPU HT Host Capabilities */ - val = pci_read_config32(NODE_PCI(node, 0), 0x34); - val &= 0xFF; //reg offset of first link - - cap_count++; - - /* Traverse through the capabilities. */ - do { - reg = pci_read_config32(NODE_PCI(node, 0), val); - /* Is the capability block a HyperTransport capability block? */ - if ((reg & 0xFF) == 0x08) { - /* Is the HT capability block an HT Host Capability? */ - if ((reg & 0xE0000000) == (1 << 29)) - cap_count--; - } - - if (cap_count) - val = (reg >> 8) & 0xFF; //update reg offset - } while (cap_count && val); - - *offset = (u8) val; - - /* If requested capability found val != 0 */ - if (!cap_count) - return TRUE; - else - return FALSE; -} - -/** - * AMD_checkLinkType - Compare desired link characteristics using a logical - * link type mask. - * - * Returns the link characteristic mask. - */ -static u32 AMD_checkLinkType(u8 node, u8 regoff) -{ - uint32_t val; - uint32_t val2; - uint32_t linktype = 0; - - /* Check connect, init and coherency */ - val = pci_read_config32(NODE_PCI(node, 0), regoff + 0x18); - val &= 0x1F; - - if (val == 3) - linktype |= HTPHY_LINKTYPE_COHERENT; - - if (val == 7) - linktype |= HTPHY_LINKTYPE_NONCOHERENT; - - if (linktype) { - /* Check gen3 */ - val = pci_read_config32(NODE_PCI(node, 0), regoff + 0x08); - val = (val >> 8) & 0xf; - if (is_gt_rev_d()) { - val2 = pci_read_config32(NODE_PCI(node, 0), regoff + 0x1c); - val |= (val2 & 0x1) << 4; - } - - if (val > 6) - linktype |= HTPHY_LINKTYPE_HT3; - else - linktype |= HTPHY_LINKTYPE_HT1; - - /* Check ganged */ - val = pci_read_config32(NODE_PCI(node, 0), (((regoff - 0x80) / 0x20) << 2) + 0x170); - - if (val & 1) - linktype |= HTPHY_LINKTYPE_GANGED; - else - linktype |= HTPHY_LINKTYPE_UNGANGED; - } - - return linktype; -} - -/** - * AMD_SetHtPhyRegister - Use the HT link's HT Phy portal registers to update - * a phy setting for that link. - */ -static void AMD_SetHtPhyRegister(u8 node, u8 link, u8 entry) -{ - u32 phyReg; - u32 phyBase; - u32 val; - - /* Determine this link's portal */ - if (link > 3) - link -= 4; - - phyBase = ((u32) link << 3) | 0x180; - - /* Determine if link is connected and abort if not */ - if (!(pci_read_config32(NODE_PCI(node, 0), 0x98 + (link * 0x20)) & 0x1)) - return; - - /* Get the portal control register's initial value - * and update it to access the desired phy register - */ - phyReg = pci_read_config32(NODE_PCI(node, 4), phyBase); - - if (fam10_htphy_default[entry].htreg > 0x1FF) { - phyReg &= ~HTPHY_DIRECT_OFFSET_MASK; - phyReg |= HTPHY_DIRECT_MAP; - } else { - phyReg &= ~HTPHY_OFFSET_MASK; - } - - /* Now get the current phy register data - * LinkPhyDone = 0, LinkPhyWrite = 0 is a read - */ - phyReg |= fam10_htphy_default[entry].htreg; - pci_write_config32(NODE_PCI(node, 4), phyBase, phyReg); - - do { - val = pci_read_config32(NODE_PCI(node, 4), phyBase); - } while (!(val & HTPHY_IS_COMPLETE_MASK)); - - /* Now we have the phy register data, apply the change */ - val = pci_read_config32(NODE_PCI(node, 4), phyBase + 4); - val &= ~fam10_htphy_default[entry].mask; - val |= fam10_htphy_default[entry].data; - pci_write_config32(NODE_PCI(node, 4), phyBase + 4, val); - - /* write it through the portal to the phy - * LinkPhyDone = 0, LinkPhyWrite = 1 is a write - */ - phyReg |= HTPHY_WRITE_CMD; - pci_write_config32(NODE_PCI(node, 4), phyBase, phyReg); - - do { - val = pci_read_config32(NODE_PCI(node, 4), phyBase); - } while (!(val & HTPHY_IS_COMPLETE_MASK)); -} - -void cpuSetAMDMSR(uint8_t node_id) -{ - /* This routine loads the CPU with default settings in fam10_msr_default - * table . It must be run after Cache-As-RAM has been enabled, and - * Hypertransport initialization has taken place. Also note - * that it is run on the current processor only, and only for the current - * processor core. - */ - msr_t msr; - u8 i; - uint8_t nvram; - u32 platform; - uint64_t revision; - uint8_t enable_cpb; - - printk(BIOS_DEBUG, "cpuSetAMDMSR "); - - revision = mctGetLogicalCPUID(0xFF); - platform = get_platform_type(); - - for (i = 0; i < ARRAY_SIZE(fam10_msr_default); i++) { - if ((fam10_msr_default[i].revision & revision) && - (fam10_msr_default[i].platform & platform)) { - msr = rdmsr(fam10_msr_default[i].msr); - msr.hi &= ~fam10_msr_default[i].mask_hi; - msr.hi |= fam10_msr_default[i].data_hi; - msr.lo &= ~fam10_msr_default[i].mask_lo; - msr.lo |= fam10_msr_default[i].data_lo; - wrmsr(fam10_msr_default[i].msr, msr); - } - } - AMD_Errata298(); - - /* Revision C0 and above */ - if (revision & AMD_OR_C0) { - uint8_t enable_experimental_memory_speed_boost; - - /* Check to see if cache partitioning is allowed */ - enable_experimental_memory_speed_boost = 0; - if (get_option(&nvram, "experimental_memory_speed_boost") == CB_SUCCESS) - enable_experimental_memory_speed_boost = !!nvram; - - uint32_t f3x1fc = pci_read_config32(NODE_PCI(node_id, 3), 0x1fc); - msr = rdmsr(FP_CFG_MSR); - msr.hi &= ~(0x7 << (42-32)); /* DiDtCfg4 */ - msr.hi |= (((f3x1fc >> 17) & 0x7) << (42-32)); - msr.hi &= ~(0x1 << (41-32)); /* DiDtCfg5 */ - msr.hi |= (((f3x1fc >> 22) & 0x1) << (41-32)); - msr.hi &= ~(0x1 << (40-32)); /* DiDtCfg3 */ - msr.hi |= (((f3x1fc >> 16) & 0x1) << (40-32)); - msr.hi &= ~(0x7 << (32-32)); /* DiDtCfg1 (1) */ - msr.hi |= (((f3x1fc >> 11) & 0x7) << (32-32)); - msr.lo &= ~(0x1f << 27); /* DiDtCfg1 (2) */ - msr.lo |= (((f3x1fc >> 6) & 0x1f) << 27); - msr.lo &= ~(0x3 << 25); /* DiDtCfg2 */ - msr.lo |= (((f3x1fc >> 14) & 0x3) << 25); - msr.lo &= ~(0x1f << 18); /* DiDtCfg0 */ - msr.lo |= (((f3x1fc >> 1) & 0x1f) << 18); - msr.lo &= ~(0x1 << 16); /* DiDtMode */ - msr.lo |= ((f3x1fc & 0x1) << 16); - wrmsr(FP_CFG_MSR, msr); - - if (enable_experimental_memory_speed_boost) { - msr = rdmsr(BU_CFG3_MSR); - msr.lo |= (0x3 << 20); /* PfcStrideMul = 0x3 */ - wrmsr(BU_CFG3_MSR, msr); - } - } - - if (revision & AMD_FAM15_ALL) { - enable_cpb = 1; - if (get_option(&nvram, "cpu_core_boost") == CB_SUCCESS) - enable_cpb = !!nvram; - - if (!enable_cpb) { - /* Disable Core Performance Boost */ - msr = rdmsr(HWCR_MSR); - msr.lo |= (0x1 << 25); /* CpbDis = 1 */ - wrmsr(HWCR_MSR, msr); - } - } - - printk(BIOS_DEBUG, " done\n"); -} - -static void cpuSetAMDPCI(u8 node) -{ - /* This routine loads the CPU with default settings in fam10_pci_default - * table . It must be run after Cache-As-RAM has been enabled, and - * Hypertransport initialization has taken place. Also note - * that it is run for the first core on each node - */ - uint8_t i; - uint8_t j; - u32 platform; - u32 val; - uint8_t offset; - uint32_t dword; - uint64_t revision; - - /* FIXME - * This should be configurable - */ - uint8_t sockets = 2; - uint8_t sockets_populated = 2; - - printk(BIOS_DEBUG, "cpuSetAMDPCI %02d", node); - - revision = mctGetLogicalCPUID(node); - platform = get_platform_type(); - - AMD_SetupPSIVID_d(platform, node); /* Set PSIVID offset which is not table driven */ - - for (i = 0; i < ARRAY_SIZE(fam10_pci_default); i++) { - if ((fam10_pci_default[i].revision & revision) && - (fam10_pci_default[i].platform & platform)) { - val = pci_read_config32(NODE_PCI(node, - fam10_pci_default[i]. - function), - fam10_pci_default[i].offset); - val &= ~fam10_pci_default[i].mask; - val |= fam10_pci_default[i].data; - pci_write_config32(NODE_PCI(node, - fam10_pci_default[i]. - function), - fam10_pci_default[i].offset, val); - } - } - - if (is_fam15h()) { - if (CONFIG_CPU_SOCKET_TYPE == 0x14) { - /* Socket C32 */ - dword = pci_read_config32(NODE_PCI(node, 0), 0x84); - dword |= 0x1 << 13; /* LdtStopTriEn = 1 */ - pci_write_config32(NODE_PCI(node, 0), 0x84, dword); - - dword = pci_read_config32(NODE_PCI(node, 0), 0xa4); - dword |= 0x1 << 13; /* LdtStopTriEn = 1 */ - pci_write_config32(NODE_PCI(node, 0), 0xa4, dword); - - dword = pci_read_config32(NODE_PCI(node, 0), 0xc4); - dword |= 0x1 << 13; /* LdtStopTriEn = 1 */ - pci_write_config32(NODE_PCI(node, 0), 0xc4, dword); - - dword = pci_read_config32(NODE_PCI(node, 0), 0xe4); - dword |= 0x1 << 13; /* LdtStopTriEn = 1 */ - pci_write_config32(NODE_PCI(node, 0), 0xe4, dword); - } - else { - /* Other socket (G34, etc.) */ - dword = pci_read_config32(NODE_PCI(node, 0), 0x84); - dword &= ~(0x1 << 13); /* LdtStopTriEn = 0 */ - pci_write_config32(NODE_PCI(node, 0), 0x84, dword); - - dword = pci_read_config32(NODE_PCI(node, 0), 0xa4); - dword &= ~(0x1 << 13); /* LdtStopTriEn = 0 */ - pci_write_config32(NODE_PCI(node, 0), 0xa4, dword); - - dword = pci_read_config32(NODE_PCI(node, 0), 0xc4); - dword &= ~(0x1 << 13); /* LdtStopTriEn = 0 */ - pci_write_config32(NODE_PCI(node, 0), 0xc4, dword); - - dword = pci_read_config32(NODE_PCI(node, 0), 0xe4); - dword &= ~(0x1 << 13); /* LdtStopTriEn = 0 */ - pci_write_config32(NODE_PCI(node, 0), 0xe4, dword); - } - } - -#ifdef DEBUG_HT_SETUP - /* Dump link settings */ - for (i = 0; i < 4; i++) { - for (j = 0; j < 4; j++) { - printk(BIOS_DEBUG, "Node %d link %d: type register: %08x control register: %08x extended control sublink 0: %08x 1: %08x\n", i, j, - pci_read_config32(NODE_PCI(i, 0), 0x98 + (j * 0x20)), pci_read_config32(NODE_PCI(i, 0), 0x84 + (j * 0x20)), - pci_read_config32(NODE_PCI(i, 0), 0x170 + (j * 0x4)), pci_read_config32(NODE_PCI(i, 0), 0x180 + (j * 0x4))); - } - } -#endif - - for (i = 0; i < ARRAY_SIZE(fam10_htphy_default); i++) { - if ((fam10_htphy_default[i].revision & revision) && - (fam10_htphy_default[i].platform & platform)) { - /* HT Phy settings either apply to both sublinks or have - * separate registers for sublink zero and one, so there - * will be two table entries. So, here we only loop - * through the sublink zeros in function zero. - */ - for (j = 0; j < 4; j++) { - if (AMD_CpuFindCapability(node, j, &offset)) { - if (AMD_checkLinkType(node, offset) - & fam10_htphy_default[i].linktype) { - AMD_SetHtPhyRegister(node, j, - i); - } - } else { - /* No more capabilities, - * link not present - */ - break; - } - } - } - } - - /* FIXME: add UMA support and programXbarToSriReg(); */ - - AMD_Errata281(node, revision, platform); - - /* FIXME: if the dct phy doesn't init correct it needs to reset. - if (revision & (AMD_DR_B2 | AMD_DR_B3)) - dctPhyDiag(); */ - - if (revision & (AMD_DR_GT_D0 | AMD_FAM15_ALL)) { - /* Set up message triggered C1E */ - dword = pci_read_config32(NODE_PCI(node, 3), 0xd4); - dword &= ~(0x1 << 14); /* CacheFlushImmOnAllHalt = !is_fam15h() */ - dword |= (is_fam15h()?0:1) << 14; - pci_write_config32(NODE_PCI(node, 3), 0xd4, dword); - - dword = pci_read_config32(NODE_PCI(node, 3), 0xdc); - dword |= 0x1 << 26; /* IgnCpuPrbEn = 1 */ - dword &= ~(0x7f << 19); /* CacheFlushOnHaltTmr = 0x28 */ - dword |= 0x28 << 19; - dword |= 0x7 << 16; /* CacheFlushOnHaltCtl = 0x7 */ - pci_write_config32(NODE_PCI(node, 3), 0xdc, dword); - - dword = pci_read_config32(NODE_PCI(node, 3), 0xa0); - dword |= 0x1 << 10; /* IdleExitEn = 1 */ - pci_write_config32(NODE_PCI(node, 3), 0xa0, dword); - - if (revision & AMD_DR_GT_D0) { - dword = pci_read_config32(NODE_PCI(node, 3), 0x188); - dword |= 0x1 << 4; /* EnStpGntOnFlushMaskWakeup = 1 */ - pci_write_config32(NODE_PCI(node, 3), 0x188, dword); - } else { - dword = pci_read_config32(NODE_PCI(node, 4), 0x128); - dword &= ~(0x1 << 31); /* CstateMsgDis = 0 */ - pci_write_config32(NODE_PCI(node, 4), 0x128, dword); - } - - dword = pci_read_config32(NODE_PCI(node, 3), 0xd4); - dword |= 0x1 << 13; /* MTC1eEn = 1 */ - pci_write_config32(NODE_PCI(node, 3), 0xd4, dword); - } - - if (revision & AMD_FAM15_ALL) { - uint32_t f5x80; - uint8_t cu_enabled; - uint8_t compute_unit_count = 0; - uint8_t compute_unit_buffer_count; - - uint32_t f3xe8; - uint8_t dual_node = 0; - - f3xe8 = pci_read_config32(NODE_PCI(0, 3), 0xe8); - - /* Check for dual node capability */ - if (f3xe8 & 0x20000000) - dual_node = 1; - - /* Determine the number of active compute units on this node */ - f5x80 = pci_read_config32(NODE_PCI(node, 5), 0x80); - cu_enabled = f5x80 & 0xf; - if (cu_enabled == 0x1) - compute_unit_count = 1; - if (cu_enabled == 0x3) - compute_unit_count = 2; - if (cu_enabled == 0x7) - compute_unit_count = 3; - if (cu_enabled == 0xf) - compute_unit_count = 4; - - if (compute_unit_count == 1) - compute_unit_buffer_count = 0x1c; - else if (compute_unit_count == 2) - compute_unit_buffer_count = 0x18; - else if (compute_unit_count == 3) - compute_unit_buffer_count = 0x14; - else - compute_unit_buffer_count = 0x10; - - dword = pci_read_config32(NODE_PCI(node, 3), 0x1a0); - dword &= ~(0x1f << 4); /* L3FreeListCBC = compute_unit_buffer_count */ - dword |= (compute_unit_buffer_count << 4); - pci_write_config32(NODE_PCI(node, 3), 0x1a0, dword); - - uint8_t link; - uint8_t link_real; - uint8_t ganged; - uint8_t iolink; - uint8_t probe_filter_enabled = !!dual_node; - - /* Set up the Link Base Channel Buffer Count */ - uint8_t isoc_rsp_data; - uint8_t isoc_np_req_data; - uint8_t isoc_rsp_cmd; - uint8_t isoc_preq; - uint8_t isoc_np_req_cmd; - uint8_t free_data; - uint8_t free_cmd; - uint8_t rsp_data; - uint8_t np_req_data; - uint8_t probe_cmd; - uint8_t rsp_cmd; - uint8_t preq; - uint8_t np_req_cmd; - - /* Common settings for all links and system configurations */ - isoc_rsp_data = 0; - isoc_np_req_data = 0; - isoc_rsp_cmd = 0; - isoc_preq = 0; - isoc_np_req_cmd = 1; - free_cmd = 8; - - for (link = 0; link < 4; link++) { - if (AMD_CpuFindCapability(node, link, &offset)) { - link_real = (offset - 0x80) / 0x20; - ganged = !!(pci_read_config32(NODE_PCI(node, 0), (link_real << 2) + 0x170) & 0x1); - iolink = !!(AMD_checkLinkType(node, offset) & HTPHY_LINKTYPE_NONCOHERENT); - - if (!iolink && ganged) { - if (probe_filter_enabled) { - free_data = 0; - rsp_data = 3; - np_req_data = 3; - probe_cmd = 4; - rsp_cmd = 9; - preq = 2; - np_req_cmd = 8; - } else { - free_data = 0; - rsp_data = 3; - np_req_data = 3; - probe_cmd = 8; - rsp_cmd = 9; - preq = 2; - np_req_cmd = 4; - } - } else if (!iolink && !ganged) { - if (probe_filter_enabled) { - free_data = 0; - rsp_data = 3; - np_req_data = 3; - probe_cmd = 4; - rsp_cmd = 9; - preq = 2; - np_req_cmd = 8; - } else { - free_data = 0; - rsp_data = 3; - np_req_data = 3; - probe_cmd = 8; - rsp_cmd = 9; - preq = 2; - np_req_cmd = 4; - } - } else if (iolink && ganged) { - free_data = 0; - rsp_data = 1; - np_req_data = 0; - probe_cmd = 0; - rsp_cmd = 2; - preq = 7; - np_req_cmd = 14; - } else { - /* FIXME - * This is an educated guess as the BKDG does not specify - * the appropriate buffer counts for this case! - */ - free_data = 1; - rsp_data = 1; - np_req_data = 1; - probe_cmd = 0; - rsp_cmd = 2; - preq = 4; - np_req_cmd = 12; - } - - dword = pci_read_config32(NODE_PCI(node, 0), (link_real * 0x20) + 0x94); - dword &= ~(0x3 << 27); /* IsocRspData = isoc_rsp_data */ - dword |= ((isoc_rsp_data & 0x3) << 27); - dword &= ~(0x3 << 25); /* IsocNpReqData = isoc_np_req_data */ - dword |= ((isoc_np_req_data & 0x3) << 25); - dword &= ~(0x7 << 22); /* IsocRspCmd = isoc_rsp_cmd */ - dword |= ((isoc_rsp_cmd & 0x7) << 22); - dword &= ~(0x7 << 19); /* IsocPReq = isoc_preq */ - dword |= ((isoc_preq & 0x7) << 19); - dword &= ~(0x7 << 16); /* IsocNpReqCmd = isoc_np_req_cmd */ - dword |= ((isoc_np_req_cmd & 0x7) << 16); - pci_write_config32(NODE_PCI(node, 0), (link_real * 0x20) + 0x94, dword); - - dword = pci_read_config32(NODE_PCI(node, 0), (link_real * 0x20) + 0x90); - dword &= ~(0x1 << 31); /* LockBc = 0x1 */ - dword |= ((0x1 & 0x1) << 31); - dword &= ~(0x7 << 25); /* FreeData = free_data */ - dword |= ((free_data & 0x7) << 25); - dword &= ~(0x1f << 20); /* FreeCmd = free_cmd */ - dword |= ((free_cmd & 0x1f) << 20); - dword &= ~(0x3 << 18); /* RspData = rsp_data */ - dword |= ((rsp_data & 0x3) << 18); - dword &= ~(0x3 << 16); /* NpReqData = np_req_data */ - dword |= ((np_req_data & 0x3) << 16); - dword &= ~(0xf << 12); /* ProbeCmd = probe_cmd */ - dword |= ((probe_cmd & 0xf) << 12); - dword &= ~(0xf << 8); /* RspCmd = rsp_cmd */ - dword |= ((rsp_cmd & 0xf) << 8); - dword &= ~(0x7 << 5); /* PReq = preq */ - dword |= ((preq & 0x7) << 5); - dword &= ~(0x1f << 0); /* NpReqCmd = np_req_cmd */ - dword |= ((np_req_cmd & 0x1f) << 0); - pci_write_config32(NODE_PCI(node, 0), (link_real * 0x20) + 0x90, dword); - } - } - - /* Set up the Link to XCS Token Counts */ - uint8_t isoc_rsp_tok_1; - uint8_t isoc_preq_tok_1; - uint8_t isoc_req_tok_1; - uint8_t probe_tok_1; - uint8_t rsp_tok_1; - uint8_t preq_tok_1; - uint8_t req_tok_1; - uint8_t isoc_rsp_tok_0; - uint8_t isoc_preq_tok_0; - uint8_t isoc_req_tok_0; - uint8_t free_tokens; - uint8_t probe_tok_0; - uint8_t rsp_tok_0; - uint8_t preq_tok_0; - uint8_t req_tok_0; - - for (link = 0; link < 4; link++) { - if (AMD_CpuFindCapability(node, link, &offset)) { - link_real = (offset - 0x80) / 0x20; - ganged = !!(pci_read_config32(NODE_PCI(node, 0), (link_real << 2) + 0x170) & 0x1); - iolink = !!(AMD_checkLinkType(node, offset) & HTPHY_LINKTYPE_NONCOHERENT); - - /* Set defaults */ - isoc_rsp_tok_1 = 0; - isoc_preq_tok_1 = 0; - isoc_req_tok_1 = 0; - probe_tok_1 = !ganged; - rsp_tok_1 = !ganged; - preq_tok_1 = !ganged; - req_tok_1 = !ganged; - isoc_rsp_tok_0 = 0; - isoc_preq_tok_0 = 0; - isoc_req_tok_0 = 0; - free_tokens = 0; - probe_tok_0 = ((ganged)?2:1); - rsp_tok_0 = ((ganged)?2:1); - preq_tok_0 = ((ganged)?2:1); - req_tok_0 = ((ganged)?2:1); - - if (!iolink && ganged) { - if (!dual_node) { - isoc_rsp_tok_1 = 0; - isoc_preq_tok_1 = 0; - isoc_req_tok_1 = 0; - probe_tok_1 = 0; - rsp_tok_1 = 0; - preq_tok_1 = 0; - req_tok_1 = 0; - isoc_rsp_tok_0 = 0; - isoc_preq_tok_0 = 0; - isoc_req_tok_0 = 1; - free_tokens = 3; - probe_tok_0 = 2; - rsp_tok_0 = 2; - preq_tok_0 = 2; - req_tok_0 = 2; - } else { - if ((sockets == 1) - || ((sockets == 2) && (sockets_populated == 1))) { - isoc_rsp_tok_1 = 0; - isoc_preq_tok_1 = 0; - isoc_req_tok_1 = 0; - probe_tok_1 = 0; - rsp_tok_1 = 0; - preq_tok_1 = 0; - req_tok_1 = 0; - isoc_rsp_tok_0 = 0; - isoc_preq_tok_0 = 0; - isoc_req_tok_0 = 1; - free_tokens = 0; - probe_tok_0 = 2; - rsp_tok_0 = 2; - preq_tok_0 = 2; - req_tok_0 = 2; - } else if (((sockets == 2) && (sockets_populated == 2)) - || ((sockets == 4) && (sockets_populated == 2))) { - isoc_rsp_tok_1 = 0; - isoc_preq_tok_1 = 0; - isoc_req_tok_1 = 0; - probe_tok_1 = 0; - rsp_tok_1 = 0; - preq_tok_1 = 0; - req_tok_1 = 0; - isoc_rsp_tok_0 = 0; - isoc_preq_tok_0 = 0; - isoc_req_tok_0 = 1; - free_tokens = 0; - probe_tok_0 = 1; - rsp_tok_0 = 2; - preq_tok_0 = 2; - req_tok_0 = 2; - } else if ((sockets == 4) && (sockets_populated == 4)) { - isoc_rsp_tok_1 = 0; - isoc_preq_tok_1 = 0; - isoc_req_tok_1 = 0; - probe_tok_1 = 0; - rsp_tok_1 = 0; - preq_tok_1 = 0; - req_tok_1 = 0; - isoc_rsp_tok_0 = 0; - isoc_preq_tok_0 = 0; - isoc_req_tok_0 = 1; - free_tokens = 0; - probe_tok_0 = 2; - rsp_tok_0 = 1; - preq_tok_0 = 1; - req_tok_0 = 2; - } - } - } else if (!iolink && !ganged) { - if ((sockets == 1) - || ((sockets == 2) && (sockets_populated == 1))) { - if (probe_filter_enabled) { - isoc_rsp_tok_1 = 0; - isoc_preq_tok_1 = 0; - isoc_req_tok_1 = 0; - probe_tok_1 = 1; - rsp_tok_1 = 1; - preq_tok_1 = 1; - req_tok_1 = 1; - isoc_rsp_tok_0 = 0; - isoc_preq_tok_0 = 0; - isoc_req_tok_0 = 1; - free_tokens = 0; - probe_tok_0 = 1; - rsp_tok_0 = 2; - preq_tok_0 = 1; - req_tok_0 = 1; - } else { - isoc_rsp_tok_1 = 0; - isoc_preq_tok_1 = 0; - isoc_req_tok_1 = 0; - probe_tok_1 = 1; - rsp_tok_1 = 1; - preq_tok_1 = 1; - req_tok_1 = 1; - isoc_rsp_tok_0 = 0; - isoc_preq_tok_0 = 0; - isoc_req_tok_0 = 1; - free_tokens = 0; - probe_tok_0 = 1; - rsp_tok_0 = 1; - preq_tok_0 = 1; - req_tok_0 = 1; - } - } else if ((sockets == 2) && (sockets_populated == 2)) { - isoc_rsp_tok_1 = 0; - isoc_preq_tok_1 = 0; - isoc_req_tok_1 = 1; - probe_tok_1 = 1; - rsp_tok_1 = 1; - preq_tok_1 = 1; - req_tok_1 = 1; - isoc_rsp_tok_0 = 0; - isoc_preq_tok_0 = 0; - isoc_req_tok_0 = 1; - free_tokens = 2; - probe_tok_0 = 1; - rsp_tok_0 = 1; - preq_tok_0 = 1; - req_tok_0 = 1; - } else if ((sockets == 4) && (sockets_populated == 2)) { - isoc_rsp_tok_1 = 0; - isoc_preq_tok_1 = 0; - isoc_req_tok_1 = 1; - probe_tok_1 = 1; - rsp_tok_1 = 1; - preq_tok_1 = 1; - req_tok_1 = 1; - isoc_rsp_tok_0 = 0; - isoc_preq_tok_0 = 0; - isoc_req_tok_0 = 1; - free_tokens = 4; - probe_tok_0 = 1; - rsp_tok_0 = 1; - preq_tok_0 = 1; - req_tok_0 = 1; - } else if ((sockets == 4) && (sockets_populated == 4)) { - isoc_rsp_tok_1 = 0; - isoc_preq_tok_1 = 0; - isoc_req_tok_1 = 1; - probe_tok_1 = 1; - rsp_tok_1 = 1; - preq_tok_1 = 1; - req_tok_1 = 1; - isoc_rsp_tok_0 = 0; - isoc_preq_tok_0 = 0; - isoc_req_tok_0 = 1; - free_tokens = 0; - probe_tok_0 = 1; - rsp_tok_0 = 1; - preq_tok_0 = 1; - req_tok_0 = 1; - } - } else if (iolink && ganged) { - if (!dual_node) { - isoc_rsp_tok_1 = 0; - isoc_preq_tok_1 = 0; - isoc_req_tok_1 = 0; - probe_tok_1 = 0; - rsp_tok_1 = 0; - preq_tok_1 = 0; - req_tok_1 = 0; - isoc_rsp_tok_0 = 0; - isoc_preq_tok_0 = 0; - isoc_req_tok_0 = 1; - free_tokens = 3; - probe_tok_0 = 0; - rsp_tok_0 = 2; - preq_tok_0 = 2; - req_tok_0 = 2; - } else if ((sockets == 1) - || (sockets == 2) - || ((sockets == 4) && (sockets_populated == 2))) { - isoc_rsp_tok_1 = 0; - isoc_preq_tok_1 = 0; - isoc_req_tok_1 = 0; - probe_tok_1 = 0; - rsp_tok_1 = 0; - preq_tok_1 = 0; - req_tok_1 = 0; - isoc_rsp_tok_0 = 0; - isoc_preq_tok_0 = 0; - isoc_req_tok_0 = 1; - free_tokens = 0; - probe_tok_0 = 0; - rsp_tok_0 = 2; - preq_tok_0 = 2; - req_tok_0 = 2; - } else if ((sockets == 4) && (sockets_populated == 4)) { - isoc_rsp_tok_1 = 0; - isoc_preq_tok_1 = 0; - isoc_req_tok_1 = 0; - probe_tok_1 = 0; - rsp_tok_1 = 0; - preq_tok_1 = 0; - req_tok_1 = 0; - isoc_rsp_tok_0 = 0; - isoc_preq_tok_0 = 0; - isoc_req_tok_0 = 2; - free_tokens = 0; - probe_tok_0 = 2; - rsp_tok_0 = 2; - preq_tok_0 = 2; - req_tok_0 = 2; - } - } - - dword = pci_read_config32(NODE_PCI(node, 3), (link_real << 2) + 0x148); - dword &= ~(0x3 << 30); /* FreeTok[3:2] = free_tokens[3:2] */ - dword |= (((free_tokens >> 2) & 0x3) << 30); - dword &= ~(0x1 << 28); /* IsocRspTok1 = isoc_rsp_tok_1 */ - dword |= (((isoc_rsp_tok_1) & 0x1) << 28); - dword &= ~(0x1 << 26); /* IsocPreqTok1 = isoc_preq_tok_1 */ - dword |= (((isoc_preq_tok_1) & 0x1) << 26); - dword &= ~(0x1 << 24); /* IsocReqTok1 = isoc_req_tok_1 */ - dword |= (((isoc_req_tok_1) & 0x1) << 24); - dword &= ~(0x3 << 22); /* ProbeTok1 = probe_tok_1 */ - dword |= (((probe_tok_1) & 0x3) << 22); - dword &= ~(0x3 << 20); /* RspTok1 = rsp_tok_1 */ - dword |= (((rsp_tok_1) & 0x3) << 20); - dword &= ~(0x3 << 18); /* PReqTok1 = preq_tok_1 */ - dword |= (((preq_tok_1) & 0x3) << 18); - dword &= ~(0x3 << 16); /* ReqTok1 = req_tok_1 */ - dword |= (((req_tok_1) & 0x3) << 16); - dword &= ~(0x3 << 14); /* FreeTok[1:0] = free_tokens[1:0] */ - dword |= (((free_tokens) & 0x3) << 14); - dword &= ~(0x3 << 12); /* IsocRspTok0 = isoc_rsp_tok_0 */ - dword |= (((isoc_rsp_tok_0) & 0x3) << 12); - dword &= ~(0x3 << 10); /* IsocPreqTok0 = isoc_preq_tok_0 */ - dword |= (((isoc_preq_tok_0) & 0x3) << 10); - dword &= ~(0x3 << 8); /* IsocReqTok0 = isoc_req_tok_0 */ - dword |= (((isoc_req_tok_0) & 0x3) << 8); - dword &= ~(0x3 << 6); /* ProbeTok0 = probe_tok_0 */ - dword |= (((probe_tok_0) & 0x3) << 6); - dword &= ~(0x3 << 4); /* RspTok0 = rsp_tok_0 */ - dword |= (((rsp_tok_0) & 0x3) << 4); - dword &= ~(0x3 << 2); /* PReqTok0 = preq_tok_0 */ - dword |= (((preq_tok_0) & 0x3) << 2); - dword &= ~(0x3 << 0); /* ReqTok0 = req_tok_0 */ - dword |= (((req_tok_0) & 0x3) << 0); - pci_write_config32(NODE_PCI(node, 3), (link_real << 2) + 0x148, dword); - } - } - - /* Set up the SRI to XCS Token Count */ - uint8_t free_tok; - uint8_t up_rsp_tok; - - /* Set defaults */ - free_tok = 0xa; - up_rsp_tok = 0x3; - - if (!dual_node) { - free_tok = 0xa; - up_rsp_tok = 0x3; - } else { - if ((sockets == 1) - || ((sockets == 2) && (sockets_populated == 1))) { - if (probe_filter_enabled) { - free_tok = 0x9; - up_rsp_tok = 0x3; - } else { - free_tok = 0xa; - up_rsp_tok = 0x3; - } - } else if ((sockets == 2) && (sockets_populated == 2)) { - free_tok = 0xb; - up_rsp_tok = 0x1; - } else if ((sockets == 4) && (sockets_populated == 2)) { - free_tok = 0xa; - up_rsp_tok = 0x3; - } else if ((sockets == 4) && (sockets_populated == 4)) { - free_tok = 0x9; - up_rsp_tok = 0x1; - } - } - - dword = pci_read_config32(NODE_PCI(node, 3), 0x140); - dword &= ~(0xf << 20); /* FreeTok = free_tok */ - dword |= ((free_tok & 0xf) << 20); - dword &= ~(0x3 << 8); /* UpRspTok = up_rsp_tok */ - dword |= ((up_rsp_tok & 0x3) << 8); - pci_write_config32(NODE_PCI(node, 3), 0x140, dword); - } - - uint8_t link; - uint8_t link_real; - uint8_t isochronous; - uint8_t isochronous_link_present; - - /* Set up isochronous buffers if needed */ - isochronous_link_present = 0; - if (revision & AMD_FAM15_ALL) { - for (link = 0; link < 4; link++) { - if (AMD_CpuFindCapability(node, link, &offset)) { - link_real = (offset - 0x80) / 0x20; - isochronous = (pci_read_config32(NODE_PCI(node, 0), (link_real * 0x20) + 0x84) >> 12) & 0x1; - - if (isochronous) - isochronous_link_present = 1; - } - } - } - - uint8_t free_tok; - uint8_t up_rsp_cbc; - uint8_t isoc_preq_cbc; - uint8_t isoc_preq_tok; - uint8_t xbar_to_sri_free_list_cbc; - if (isochronous_link_present) { - /* Adjust buffer counts */ - dword = pci_read_config32(NODE_PCI(node, 3), 0x70); - isoc_preq_cbc = (dword >> 24) & 0x7; - up_rsp_cbc = (dword >> 16) & 0x7; - up_rsp_cbc--; - isoc_preq_cbc++; - dword &= ~(0x7 << 24); /* IsocPreqCBC = isoc_preq_cbc */ - dword |= ((isoc_preq_cbc & 0x7) << 24); - dword &= ~(0x7 << 16); /* UpRspCBC = up_rsp_cbc */ - dword |= ((up_rsp_cbc & 0x7) << 16); - pci_write_config32(NODE_PCI(node, 3), 0x70, dword); - - dword = pci_read_config32(NODE_PCI(node, 3), 0x74); - isoc_preq_cbc = (dword >> 24) & 0x7; - isoc_preq_cbc++; - dword &= ~(0x7 << 24); /* IsocPreqCBC = isoc_preq_cbc */ - dword |= (isoc_preq_cbc & 0x7) << 24; - pci_write_config32(NODE_PCI(node, 3), 0x74, dword); - - dword = pci_read_config32(NODE_PCI(node, 3), 0x7c); - xbar_to_sri_free_list_cbc = dword & 0x1f; - xbar_to_sri_free_list_cbc--; - dword &= ~0x1f; /* Xbar2SriFreeListCBC = xbar_to_sri_free_list_cbc */ - dword |= xbar_to_sri_free_list_cbc & 0x1f; - pci_write_config32(NODE_PCI(node, 3), 0x7c, dword); - - dword = pci_read_config32(NODE_PCI(node, 3), 0x140); - free_tok = (dword >> 20) & 0xf; - isoc_preq_tok = (dword >> 14) & 0x3; - free_tok--; - isoc_preq_tok++; - dword &= ~(0xf << 20); /* FreeTok = free_tok */ - dword |= ((free_tok & 0xf) << 20); - dword &= ~(0x3 << 14); /* IsocPreqTok = isoc_preq_tok */ - dword |= ((isoc_preq_tok & 0x3) << 14); - pci_write_config32(NODE_PCI(node, 3), 0x140, dword); - } - - printk(BIOS_DEBUG, " done\n"); -} - -#ifdef UNUSED_CODE -/* Clearing the MCA registers is apparently handled in the ramstage CPU Function 3 driver */ -static void cpuInitializeMCA(void) -{ - /* Clears Machine Check Architecture (MCA) registers, which power on - * containing unknown data, on currently running processor. - * This routine should only be executed on initial power on (cold boot), - * not across a warm reset because valid data is present at that time. - */ - - msr_t msr; - u32 reg; - u8 i; - - if (cpuid_edx(1) & 0x4080) { /* MCE and MCA (edx[7] and edx[14]) */ - msr = rdmsr(IA32_MCG_CAP); - if (msr.lo & MCG_CTL_P) { /* MCG_CTL_P bit is set? */ - msr.lo &= 0xFF; - msr.lo--; - msr.lo <<= 2; /* multiply the count by 4 */ - reg = IA32_MC0_STATUS + msr.lo; - msr.lo = msr.hi = 0; - for (i = 0; i < 4; i++) { - wrmsr(reg, msr); - reg -= 4; /* Touch status regs for each bank */ - } - } - } -} -#endif - -/** - * finalize_node_setup() - * - * Do any additional post HT init - * - */ -void finalize_node_setup(struct sys_info *sysinfo) -{ - u8 i; - u8 nodes = get_nodes(); - u32 reg; - - /* read Node0 F0_0x64 bit [8:10] to find out SbLink # */ - reg = pci_read_config32(NODE_HT(0), 0x64); - sysinfo->sblk = (reg >> 8) & 7; - sysinfo->sbbusn = 0; - sysinfo->nodes = nodes; - sysinfo->sbdn = get_sbdn(sysinfo->sbbusn); - - for (i = 0; i < nodes; i++) { - cpuSetAMDPCI(i); - } - -#if CONFIG(SET_FIDVID) - // Prep each node for FID/VID setup. - prep_fid_change(); -#endif - -#if CONFIG_MAX_PHYSICAL_CPUS > 1 - /* Skip the BSP, start at node 1 */ - for (i = 1; i < nodes; i++) { - setup_remote_node(i); - start_node(i); - } -#endif -} - -#if CONFIG(SET_FIDVID) -# include "fidvid.c" -#endif diff --git a/src/cpu/amd/family_10h-family_15h/init_cpus.h b/src/cpu/amd/family_10h-family_15h/init_cpus.h deleted file mode 100644 index 4be6ee806f..0000000000 --- a/src/cpu/amd/family_10h-family_15h/init_cpus.h +++ /dev/null @@ -1,50 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef INIT_CPUS_H -#define INIT_CPUS_H - -#include -#include -#include -#include -#include -#include "defaults.h" - -#define NODE_HT(x) NODE_PCI(x,0) -#define NODE_MP(x) NODE_PCI(x,1) -#define NODE_MC(x) NODE_PCI(x,3) -#define NODE_LC(x) NODE_PCI(x,4) - -unsigned int get_sbdn(unsigned int bus); -void cpuSetAMDMSR(uint8_t node_id); - -typedef void (*process_ap_t) (u32 apicid, void *gp); - -uint32_t get_boot_apic_id(uint8_t node, uint32_t core); -u32 init_cpus(u32 cpu_init_detectedx, struct sys_info *sysinfo); -uint8_t set_apicid_cpuid_lo(void); -void real_start_other_core(uint32_t nodeid, uint32_t cores); -void finalize_node_setup(struct sys_info *sysinfo); -uint32_t wait_cpu_state(uint32_t apicid, uint32_t state, uint32_t state2); -void start_other_cores(uint32_t bsp_apicid); -u32 get_core_num_in_bsp(u32 nodeid); - -void update_microcode(u32 cpu_deviceid); - -/* fidvid.c */ -void init_fidvid_stage2(u32 apicid, u32 nodeid); -void prep_fid_change(void); -int init_fidvid_bsp(u32 bsp_apicid, u32 nodes); - -#endif diff --git a/src/cpu/amd/family_10h-family_15h/model_10xxx_init.c b/src/cpu/amd/family_10h-family_15h/model_10xxx_init.c deleted file mode 100644 index 9c040eb983..0000000000 --- a/src/cpu/amd/family_10h-family_15h/model_10xxx_init.c +++ /dev/null @@ -1,268 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -static inline uint8_t is_gt_rev_d(void) -{ - uint8_t fam15h = 0; - uint8_t rev_gte_d = 0; - uint32_t family; - uint32_t model; - - family = model = cpuid_eax(0x80000001); - model = ((model & 0xf0000) >> 12) | ((model & 0xf0) >> 4); - family = ((family & 0xf00000) >> 16) | ((family & 0xf00) >> 8); - - if (family >= 0x6f) - /* Family 15h or later */ - fam15h = 1; - - if ((model >= 0x8) || fam15h) - /* Revision D or later */ - rev_gte_d = 1; - - return rev_gte_d; -} - -static volatile uint8_t fam15h_startup_flags[MAX_NODES_SUPPORTED][MAX_CORES_SUPPORTED] = {{ 0 }}; - -static void model_10xxx_init(struct device *dev) -{ - u8 i; - msr_t msr; - int num_banks; - struct node_core_id id; -#if CONFIG(LOGICAL_CPUS) - u32 siblings; -#endif - uint8_t delay_start; - - id = get_node_core_id(read_nb_cfg_54()); /* nb_cfg_54 can not be set */ - printk(BIOS_DEBUG, "nodeid = %02d, coreid = %02d\n", id.nodeid, id.coreid); - - if (is_fam15h()) - delay_start = !!(id.coreid & 0x1); - else - delay_start = 0; - - /* Turn on caching if we haven't already */ - x86_enable_cache(); - - if (!delay_start) { - /* Initialize all variable MTRRs except the first pair. - * This prevents Linux from having to correct an inconsistent - * MTRR setup, which would crash Family 15h CPUs due to the - * compute unit structure sharing MTRR MSRs between AP cores. - */ - msr.hi = 0x00000000; - msr.lo = 0x00000000; - - disable_cache(); - - for (i = 0x2; i < 0x10; i++) { - wrmsr(MTRR_PHYS_BASE(0) | i, msr); - } - - enable_cache(); - - /* Set up other MTRRs */ - amd_setup_mtrrs(); - } else { - while (!fam15h_startup_flags[id.nodeid][id.coreid - 1]) { - /* Wait for CU first core startup */ - } - } - - x86_mtrr_check(); - - disable_cache(); - - /* zero the machine check error status registers */ - msr = rdmsr(IA32_MCG_CAP); - num_banks = msr.lo & MCA_BANKS_MASK; - msr.lo = 0; - msr.hi = 0; - for (i = 0; i < num_banks; i++) - wrmsr(IA32_MC0_STATUS + (i * 4), msr); - - enable_cache(); - - /* Enable the local CPU APICs */ - setup_lapic(); - - /* Set the processor name string */ - init_processor_name(); - -#if CONFIG(LOGICAL_CPUS) - siblings = cpuid_ecx(0x80000008) & 0xff; - - if (siblings > 0) { - msr = rdmsr_amd(CPU_ID_FEATURES_MSR); - msr.lo |= 1 << 28; - wrmsr_amd(CPU_ID_FEATURES_MSR, msr); - - msr = rdmsr_amd(CPU_ID_EXT_FEATURES_MSR); - msr.hi |= 1 << (33 - 32); - wrmsr_amd(CPU_ID_EXT_FEATURES_MSR, msr); - } - printk(BIOS_DEBUG, "siblings = %02d, ", siblings); -#endif - - /* Set bus unit configuration */ - if (is_fam15h()) { - uint32_t f5x80; - uint8_t enabled; - uint8_t compute_unit_count = 0; - f5x80 = pci_read_config32(pcidev_on_root(0x18 + id.nodeid, 5), - 0x80); - enabled = f5x80 & 0xf; - if (enabled == 0x1) - compute_unit_count = 1; - if (enabled == 0x3) - compute_unit_count = 2; - if (enabled == 0x7) - compute_unit_count = 3; - if (enabled == 0xf) - compute_unit_count = 4; - msr = rdmsr(BU_CFG2_MSR); - msr.lo &= ~(0x3 << 6); /* ThrottleNbInterface[1:0] */ - msr.lo |= (((compute_unit_count - 1) & 0x3) << 6); - wrmsr(BU_CFG2_MSR, msr); - } else { - uint32_t f0x60; - uint32_t f0x160; - uint8_t core_count = 0; - uint8_t node_count = 0; - f0x60 = pci_read_config32(pcidev_on_root(0x18 + id.nodeid, 0), - 0x60); - core_count = (f0x60 >> 16) & 0x1f; - node_count = ((f0x60 >> 4) & 0x7) + 1; - if (is_gt_rev_d()) { - f0x160 = pci_read_config32( - pcidev_on_root(0x18 + id.nodeid, 0), 0x160); - core_count |= ((f0x160 >> 16) & 0x7) << 5; - } - core_count++; - core_count /= node_count; - msr = rdmsr(BU_CFG2_MSR); - if (is_gt_rev_d()) { - msr.hi &= ~(0x3 << (36 - 32)); /* ThrottleNbInterface[3:2] */ - msr.hi |= ((((core_count - 1) >> 2) & 0x3) << (36 - 32)); - } - msr.lo &= ~(0x3 << 6); /* ThrottleNbInterface[1:0] */ - msr.lo |= (((core_count - 1) & 0x3) << 6); - msr.lo &= ~(0x1 << 24); /* WcPlusDis = 0 */ - wrmsr(BU_CFG2_MSR, msr); - } - - /* Disable Cf8ExtCfg */ - msr = rdmsr(NB_CFG_MSR); - msr.hi &= ~(1 << (46 - 32)); - wrmsr(NB_CFG_MSR, msr); - - if (is_fam15h()) { - msr = rdmsr(BU_CFG3_MSR); - /* Set CombineCr0Cd */ - msr.hi |= (1 << (49-32)); - wrmsr(BU_CFG3_MSR, msr); - } else { - msr = rdmsr(BU_CFG2_MSR); - /* Clear ClLinesToNbDis */ - msr.lo &= ~(1 << 15); - /* Clear bit 35 as per Erratum 343 */ - msr.hi &= ~(1 << (35-32)); - wrmsr(BU_CFG2_MSR, msr); - } - - if (CONFIG(HAVE_SMI_HANDLER)) { - printk(BIOS_DEBUG, "Initializing SMM ASeg memory\n"); - - /* Set SMM base address for this CPU */ - msr = rdmsr(SMM_BASE_MSR); - msr.lo = SMM_BASE - (lapicid() * 0x400); - wrmsr(SMM_BASE_MSR, msr); - - /* Enable the SMM memory window */ - msr = rdmsr(SMM_MASK_MSR); - msr.lo |= (1 << 0); /* Enable ASEG SMRAM Range */ - wrmsr(SMM_MASK_MSR, msr); - } else { - printk(BIOS_DEBUG, "Disabling SMM ASeg memory\n"); - - /* Set SMM base address for this CPU */ - msr = rdmsr(SMM_BASE_MSR); - msr.lo = SMM_BASE - (lapicid() * 0x400); - wrmsr(SMM_BASE_MSR, msr); - - /* Disable the SMM memory window */ - msr.hi = 0x0; - msr.lo = 0x0; - wrmsr(SMM_MASK_MSR, msr); - } - - /* Set SMMLOCK to avoid exploits messing with SMM */ - msr = rdmsr(HWCR_MSR); - msr.lo |= (1 << 0); - wrmsr(HWCR_MSR, msr); - - fam15h_startup_flags[id.nodeid][id.coreid] = 1; -} - -static struct device_operations cpu_dev_ops = { - .init = model_10xxx_init, -}; - -static const struct cpu_device_id cpu_table[] = { -//AMD_GH_SUPPORT - { X86_VENDOR_AMD, 0x100f00 }, /* SH-F0 L1 */ - { X86_VENDOR_AMD, 0x100f10 }, /* M2 */ - { X86_VENDOR_AMD, 0x100f20 }, /* S1g1 */ - { X86_VENDOR_AMD, 0x100f21 }, - { X86_VENDOR_AMD, 0x100f2A }, - { X86_VENDOR_AMD, 0x100f22 }, - { X86_VENDOR_AMD, 0x100f23 }, - { X86_VENDOR_AMD, 0x100f40 }, /* RB-C0 */ - { X86_VENDOR_AMD, 0x100f42 }, /* RB-C2 */ - { X86_VENDOR_AMD, 0x100f43 }, /* RB-C3 */ - { X86_VENDOR_AMD, 0x100f52 }, /* BL-C2 */ - { X86_VENDOR_AMD, 0x100f62 }, /* DA-C2 */ - { X86_VENDOR_AMD, 0x100f63 }, /* DA-C3 */ - { X86_VENDOR_AMD, 0x100f80 }, /* HY-D0 */ - { X86_VENDOR_AMD, 0x100f81 }, /* HY-D1 */ - { X86_VENDOR_AMD, 0x100f91 }, /* HY-D1 */ - { X86_VENDOR_AMD, 0x100fa0 }, /* PH-E0 */ - { X86_VENDOR_AMD, 0x600f12 }, /* OR-B2 */ - { X86_VENDOR_AMD, 0x600f20 }, /* OR-C0 */ - { 0, 0 }, -}; - -static const struct cpu_driver model_10xxx __cpu_driver = { - .ops = &cpu_dev_ops, - .id_table = cpu_table, -}; diff --git a/src/cpu/amd/family_10h-family_15h/monotonic_timer.c b/src/cpu/amd/family_10h-family_15h/monotonic_timer.c deleted file mode 100644 index 51244b83ae..0000000000 --- a/src/cpu/amd/family_10h-family_15h/monotonic_timer.c +++ /dev/null @@ -1,91 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ -#include -#include -#include -#include -#include -#include -#include -#include - -static struct monotonic_counter { - int initialized; - uint32_t core_frequency; - struct mono_time time; - uint64_t last_value; -} mono_counter; - -static inline uint64_t read_counter_msr(void) -{ - msr_t counter_msr; - - counter_msr = rdmsr(TSC_MSR); - - return ((uint64_t)counter_msr.hi << 32) | (uint64_t)counter_msr.lo; -} - -static void init_timer(void) -{ - uint8_t model; - uint32_t cpuid_fms; - uint8_t cpufid; - uint8_t cpudid; - uint8_t boost_capable = 0; - - /* Get CPU model */ - cpuid_fms = cpuid_eax(0x80000001); - model = ((cpuid_fms & 0xf0000) >> 16) | ((cpuid_fms & 0xf0) >> 4); - - /* Get boost capability */ - if ((model == 0x8) || (model == 0x9)) { /* revision D */ - boost_capable = (pci_read_config32(pcidev_on_root(0x18, 4), - 0x15c) & 0x4) >> 2; - } - - /* Set up TSC (BKDG v3.62 section 2.9.4)*/ - msr_t msr = rdmsr(HWCR_MSR); - msr.lo |= 0x1000000; - wrmsr(HWCR_MSR, msr); - - /* Get core Pstate 0 frequency in MHz */ - msr = rdmsr(PSTATE_0_MSR + boost_capable); - cpufid = (msr.lo & 0x3f); - cpudid = (msr.lo & 0x1c0) >> 6; - mono_counter.core_frequency = (100 * (cpufid + 0x10)) / (0x01 << cpudid); - - mono_counter.last_value = read_counter_msr(); - mono_counter.initialized = 1; -} - -void timer_monotonic_get(struct mono_time *mt) -{ - uint64_t current_tick; - uint32_t usecs_elapsed = 0; - - if (!mono_counter.initialized) - init_timer(); - - current_tick = read_counter_msr(); - if (mono_counter.core_frequency != 0) - usecs_elapsed = (current_tick - mono_counter.last_value) / mono_counter.core_frequency; - - /* Update current time and tick values only if a full tick occurred. */ - if (usecs_elapsed) { - mono_time_add_usecs(&mono_counter.time, usecs_elapsed); - mono_counter.last_value = current_tick; - } - - /* Save result. */ - *mt = mono_counter.time; -} diff --git a/src/cpu/amd/family_10h-family_15h/powernow_acpi.c b/src/cpu/amd/family_10h-family_15h/powernow_acpi.c deleted file mode 100644 index 4029f723df..0000000000 --- a/src/cpu/amd/family_10h-family_15h/powernow_acpi.c +++ /dev/null @@ -1,440 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -static inline uint8_t is_fam15h(void) -{ - uint8_t fam15h = 0; - uint32_t family; - - family = cpuid_eax(0x80000001); - family = ((family & 0xf00000) >> 16) | ((family & 0xf00) >> 8); - - if (family >= 0x6f) - /* Family 15h or later */ - fam15h = 1; - - return fam15h; -} - -static void write_pstates_for_core(u8 pstate_num, u16 *pstate_feq, u32 *pstate_power, - u32 *pstate_latency, u32 *pstate_control, - u32 *pstate_status, int coreID, - uint8_t single_link) -{ - int i; - struct cpuid_result cpuid1; - - acpigen_write_empty_PCT(); - acpigen_write_name("_PSS"); - - /* add later to total sum */ - acpigen_write_package(pstate_num); - - for (i = 0;i < pstate_num; i++) - acpigen_write_PSS_package(pstate_feq[i], - pstate_power[i], - pstate_latency[i], - pstate_latency[i], - pstate_control[i], - pstate_status[i]); - - /* update the package size */ - acpigen_pop_len(); - - /* Write PPC object */ - acpigen_write_PPC(pstate_num); - - /* Write PSD indicating coordination type */ - if ((single_link) && (mctGetLogicalCPUID(0) & AMD_DR_GT_Bx)) { - /* Revision C or greater single-link processor */ - cpuid1 = cpuid(0x80000008); - acpigen_write_PSD_package(0, (cpuid1.ecx & 0xff) + 1, SW_ALL); - } else { - /* Find the local APIC ID for the specified core ID */ - struct device* cpu; - int cpu_index = 0; - for (cpu = all_devices; cpu; cpu = cpu->next) { - if ((cpu->path.type != DEVICE_PATH_APIC) || - (cpu->bus->dev->path.type != DEVICE_PATH_CPU_CLUSTER)) - continue; - if (!cpu->enabled) - continue; - if (cpu_index == coreID) - break; - cpu_index++; - } - - if (cpu) - acpigen_write_PSD_package(cpu->path.apic.apic_id, 1, SW_ANY); - } -} - -static void write_cstates_for_core(int coreID) -{ - /* Generate C state entries */ - uint8_t cstate_count = 1; - acpi_cstate_t cstate; - - if (is_fam15h()) { - cstate.ctype = 2; - cstate.latency = 100; - cstate.power = 0; - cstate.resource.space_id = ACPI_ADDRESS_SPACE_IO; - cstate.resource.bit_width = 8; - cstate.resource.bit_offset = 0; - cstate.resource.addrl = rdmsr(MSR_CSTATE_ADDRESS).lo + 1; - cstate.resource.addrh = 0; - cstate.resource.access_size = 1; - } else { - cstate.ctype = 2; - cstate.latency = 75; - cstate.power = 0; - cstate.resource.space_id = ACPI_ADDRESS_SPACE_IO; - cstate.resource.bit_width = 8; - cstate.resource.bit_offset = 0; - cstate.resource.addrl = rdmsr(MSR_CSTATE_ADDRESS).lo; - cstate.resource.addrh = 0; - cstate.resource.access_size = 1; - } - - acpigen_write_CST_package(&cstate, cstate_count); - - /* Find the local APIC ID for the specified core ID */ - if (is_fam15h()) { - struct device* cpu; - int cpu_index = 0; - for (cpu = all_devices; cpu; cpu = cpu->next) { - if ((cpu->path.type != DEVICE_PATH_APIC) || - (cpu->bus->dev->path.type != DEVICE_PATH_CPU_CLUSTER)) - continue; - if (!cpu->enabled) - continue; - if (cpu_index == coreID) - break; - cpu_index++; - } - - if (cpu) { - /* TODO - * Detect dual core status and skip CSD generation if dual core is disabled - */ - - /* Generate C state dependency entries */ - acpigen_write_CSD_package((cpu->path.apic.apic_id >> 1) & 0x7f, 2, CSD_HW_ALL, 0); - } - } -} - -/* -* For details of this algorithm, please refer to: -* Family 10h BDKG 3.62 page 69 -* Family 15h BDKG 3.14 page 74 -* -* WARNING: The core count algorithm below assumes that all processors -* are identical, with the same number of active cores. While the BKDG -* states the BIOS must enforce this coreboot does not currently do so. -* As a result it is possible that this code may break if an illegal -* processor combination is installed. If it does break please fix the -* code in the proper locations! -*/ -void amd_generate_powernow(u32 pcontrol_blk, u8 plen, u8 onlyBSP) -{ - u8 processor_brand[49]; - u32 *v; - struct cpuid_result cpuid1; - - u16 Pstate_feq[10]; - u32 Pstate_power[10]; - u32 Pstate_latency[10]; - u32 Pstate_control[10]; - u32 Pstate_status[10]; - u8 Pstate_num; - u8 cmp_cap; - u8 index; - msr_t msr; - - uint8_t nvram; - uint8_t enable_c_states; - - enable_c_states = 0; -#if CONFIG(HAVE_ACPI_TABLES) - if (get_option(&nvram, "cpu_c_states") == CB_SUCCESS) - enable_c_states = !!nvram; -#endif - - /* Get the Processor Brand String using cpuid(0x8000000x) command x=2,3,4 */ - cpuid1 = cpuid(0x80000002); - v = (u32 *) processor_brand; - v[0] = cpuid1.eax; - v[1] = cpuid1.ebx; - v[2] = cpuid1.ecx; - v[3] = cpuid1.edx; - cpuid1 = cpuid(0x80000003); - v[4] = cpuid1.eax; - v[5] = cpuid1.ebx; - v[6] = cpuid1.ecx; - v[7] = cpuid1.edx; - cpuid1 = cpuid(0x80000004); - v[8] = cpuid1.eax; - v[9] = cpuid1.ebx; - v[10] = cpuid1.ecx; - v[11] = cpuid1.edx; - processor_brand[48] = 0; - printk(BIOS_INFO, "processor_brand=%s\n", processor_brand); - - uint32_t dtemp; - uint8_t node_index; - uint8_t node_count; - uint8_t cores_per_node; - uint8_t total_core_count; - uint8_t fam15h; - uint8_t fam10h_rev_e = 0; - - /* Detect Revision E processors via method used in fidvid.c */ - if ((cpuid_edx(0x80000007) & CPB_MASK) - && ((cpuid_ecx(0x80000008) & NC_MASK) == 5)) - fam10h_rev_e = 1; - - /* - * Based on the CPU socket type, cmp_cap and pwr_lmt, get the power limit. - * socket_type : 0x10 SocketF; 0x11 AM2/ASB1; 0x12 S1G1 - * cmp_cap : 0x0 SingleCore; 0x1 DualCore; 0x2 TripleCore; 0x3 QuadCore; 0x4 QuintupleCore; 0x5 HexCore - */ - printk(BIOS_INFO, "Pstates algorithm ...\n"); - fam15h = !!(mctGetLogicalCPUID(0) & AMD_FAM15_ALL); - /* Get number of cores */ - if (fam15h) { - cmp_cap = pci_read_config32(pcidev_on_root(0x18, 5), 0x84) & - 0xff; - } else { - dtemp = pci_read_config32(pcidev_on_root(0x18, 3), 0xe8); - cmp_cap = (dtemp & 0x3000) >> 12; - if (mctGetLogicalCPUID(0) & (AMD_FAM10_REV_D | AMD_FAM15_ALL)) /* revision D or higher */ - cmp_cap |= (dtemp & 0x8000) >> 13; - } - - /* Get number of nodes */ - dtemp = pci_read_config32(pcidev_on_root(0x18, 0), 0x60); - node_count = ((dtemp & 0x70) >> 4) + 1; - cores_per_node = cmp_cap + 1; - - /* Compute total number of cores installed in system */ - total_core_count = cores_per_node * node_count; - - /* Get number of boost states */ - uint8_t boost_count = 0; - dtemp = pci_read_config32(pcidev_on_root(0x18, 4), 0x15c); - if (fam10h_rev_e) - boost_count = (dtemp >> 2) & 0x1; - else if (mctGetLogicalCPUID(0) & AMD_FAM15_ALL) - boost_count = (dtemp >> 2) & 0x7; - - /* See if the CPUID(0x80000007) returned EDX[7]==1b */ - cpuid1 = cpuid(0x80000007); - if ((cpuid1.edx & 0x80) != 0x80) { - printk(BIOS_INFO, "No valid set of P-states\n"); - return; - } - - if (fam15h) - /* Set P_LVL2 P_BLK entry */ - *(((uint8_t *)pcontrol_blk) + 0x04) = - (rdmsr(MSR_CSTATE_ADDRESS).lo + 1) & 0xff; - - uint8_t pviModeFlag; - uint8_t Pstate_max; - uint8_t cpufid; - uint8_t cpudid; - uint8_t cpuvid; - uint8_t cpuidd; - uint8_t cpuidv; - uint8_t power_step_up; - uint8_t power_step_down; - uint8_t pll_lock_time; - uint32_t expanded_cpuidv; - uint32_t core_frequency; - uint32_t core_power; - uint32_t core_latency; - uint32_t core_voltage; /* multiplied by 10000 */ - uint8_t single_link; - - /* Determine if this is a PVI or SVI system */ - dtemp = pci_read_config32(pcidev_on_root(0x18, 3), 0xA0); - - if (dtemp & PVI_MODE) - pviModeFlag = 1; - else - pviModeFlag = 0; - - /* Get PSmax's index */ - msr = rdmsr(PS_LIM_REG); - Pstate_max = (uint8_t) ((msr.lo >> PS_MAX_VAL_SHFT) & ((fam15h)?BIT_MASK_7:BIT_MASK_3)); - - /* Determine if all enabled Pstates have the same fidvid */ - uint8_t i; - uint8_t cpufid_prev = (rdmsr(PSTATE_0_MSR).lo & 0x3f); - uint8_t all_enabled_cores_have_same_cpufid = 1; - for (i = 1; i < Pstate_max; i++) { - cpufid = rdmsr(PSTATE_0_MSR + i).lo & 0x3f; - if (cpufid != cpufid_prev) { - all_enabled_cores_have_same_cpufid = 0; - break; - } - } - - /* Family 15h uses slightly different PSmax numbering */ - if (fam15h) - Pstate_max++; - - /* Populate tables with all Pstate information */ - for (Pstate_num = 0; Pstate_num < Pstate_max; Pstate_num++) { - /* Get power state information */ - msr = rdmsr(PSTATE_0_MSR + Pstate_num + boost_count); - cpufid = (msr.lo & 0x3f); - cpudid = (msr.lo & 0x1c0) >> 6; - cpuvid = (msr.lo & 0xfe00) >> 9; - cpuidd = (msr.hi & 0xff); - cpuidv = (msr.hi & 0x300) >> 8; - core_frequency = (100 * (cpufid + 0x10)) / (0x01 << cpudid); - if (pviModeFlag) { - if (cpuvid >= 0x20) { - core_voltage = 7625 - (((cpuvid - 0x20) * 10000) / 80); - } else { - core_voltage = 15500 - ((cpuvid * 10000) / 40); - } - } else { - cpuvid = cpuvid & 0x7f; - if (cpuvid >= 0x7c) - core_voltage = 0; - else - core_voltage = 15500 - ((cpuvid * 10000) / 80); - } - switch (cpuidv) { - case 0x0: - expanded_cpuidv = 1; - break; - case 0x1: - expanded_cpuidv = 10; - break; - case 0x2: - expanded_cpuidv = 100; - break; - case 0x3: - expanded_cpuidv = 1000; - break; - default: - printk(BIOS_ERR, "%s:%s:%d: Invalid cpuidv, " - "not generating pstate tables.\n", - __FILE__, __func__, __LINE__); - return; - } - core_power = (core_voltage * cpuidd) / (expanded_cpuidv * 10); - - /* Calculate transition latency */ - dtemp = pci_read_config32(pcidev_on_root(0x18, 3), 0xD4); - power_step_up = (dtemp & 0xf000000) >> 24; - power_step_down = (dtemp & 0xf00000) >> 20; - dtemp = pci_read_config32(pcidev_on_root(0x18, 3), 0xA0); - pll_lock_time = (dtemp & 0x3800) >> 11; - if (all_enabled_cores_have_same_cpufid) - core_latency = ((12 * power_step_down) + power_step_up) / 1000; - else - core_latency = (12 * (power_step_down + power_step_up) / 1000) - + pll_lock_time; - - Pstate_feq[Pstate_num] = core_frequency; - Pstate_power[Pstate_num] = core_power; - Pstate_latency[Pstate_num] = core_latency; - Pstate_control[Pstate_num] = Pstate_num; - Pstate_status[Pstate_num] = Pstate_num; - } - - /* Print Pstate frequency, power, and latency */ - for (index = 0; index < Pstate_num; index++) { - printk(BIOS_INFO, "Pstate_freq[%d] = %dMHz\t", index, - Pstate_feq[index]); - printk(BIOS_INFO, "Pstate_power[%d] = %dmw\n", index, - Pstate_power[index]); - printk(BIOS_INFO, "Pstate_latency[%d] = %dus\n", index, - Pstate_latency[index]); - } - - /* Enter processor block scope */ - char pscope[] = "\\_PR"; - acpigen_write_scope(pscope); - - for (index = 0; index < total_core_count; index++) { - /* Determine if this is a single-link processor */ - node_index = 0x18 + (index / cores_per_node); - dtemp = pci_read_config32(pcidev_on_root(node_index, 0), 0x80); - single_link = !!(((dtemp & 0xff00) >> 8) == 0); - - /* Enter processor core scope */ - uint8_t plen_cur = plen; - uint32_t pcontrol_blk_cur = pcontrol_blk; - if ((onlyBSP) && (index != 0)) { - plen_cur = 0; - pcontrol_blk_cur = 0; - } - acpigen_write_processor(index, pcontrol_blk_cur, plen_cur); - - /* Write P-state status and dependency objects */ - write_pstates_for_core(Pstate_num, Pstate_feq, Pstate_power, - Pstate_latency, Pstate_control, Pstate_status, - index, single_link); - - /* Write C-state status and dependency objects */ - if (fam15h && enable_c_states) - write_cstates_for_core(index); - - /* Exit processor core scope */ - acpigen_pop_len(); - } - - /* Exit processor block scope */ - acpigen_pop_len(); -} - -void amd_powernow_update_fadt(acpi_fadt_t * fadt) -{ - if (is_fam15h()) { - fadt->p_lvl2_lat = 101; /* NOTE: While the BKDG states this should - * be set to 100, there is no way to meet - * the other FADT requirements. I suspect - * there is an error in the BKDG for ACPI - * 1.x support; disable all FADT-based C - * states > 2... */ - fadt->p_lvl3_lat = 1001; - fadt->flags |= 0x1 << 2; /* FLAGS.PROC_C1 = 1 */ - fadt->flags |= 0x1 << 3; /* FLAGS.P_LVL2_UP = 1 */ - } else { - fadt->cst_cnt = 0; - } - fadt->pstate_cnt = 0; -} diff --git a/src/cpu/amd/family_10h-family_15h/processor_name.c b/src/cpu/amd/family_10h-family_15h/processor_name.c deleted file mode 100644 index c5e31fd59d..0000000000 --- a/src/cpu/amd/family_10h-family_15h/processor_name.c +++ /dev/null @@ -1,353 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -/* - * This code sets the Processor Name String for AMD64 CPUs. - * - * Revision Guide for AMD Family 10h Processors - * Publication # 41322 Revision: 3.17 Issue Date: February 2008 - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -/* The maximum length of CPU names is 48 bytes, including the final NULL byte. - * If you change these names your BIOS will _NOT_ pass the AMD validation and - * your mainboard will not be posted on the AMD Recommended Motherboard Website - */ - -struct str_s { - u8 Pg; - u8 NC; - u8 String; - char const *value; -}; - - -static const struct str_s String1_socket_F[] = { - {0x00, 0x01, 0x00, "Dual-Core AMD Opteron(tm) Processor 83"}, - {0x00, 0x01, 0x01, "Dual-Core AMD Opteron(tm) Processor 23"}, - {0x00, 0x03, 0x00, "Quad-Core AMD Opteron(tm) Processor 83"}, - {0x00, 0x03, 0x01, "Quad-Core AMD Opteron(tm) Processor 23"}, - {0x00, 0x05, 0x00, "Six-Core AMD Opteron(tm) Processor 84"}, - {0x00, 0x05, 0x01, "Six-Core AMD Opteron(tm) Processor 24"}, - {0x00, 0x03, 0x02, "Embedded AMD Opteron(tm) Processor 83"}, - {0x00, 0x03, 0x03, "Embedded AMD Opteron(tm) Processor 23"}, - {0x00, 0x03, 0x04, "Embedded AMD Opteron(tm) Processor 13"}, - {0x00, 0x03, 0x05, "AMD Phenom(tm) FX-"}, - {0x01, 0x01, 0x01, "Embedded AMD Opteron(tm) Processor"}, - {0, 0, 0, NULL} -}; - -static const struct str_s String2_socket_F[] = { - {0x00, 0xFF, 0x02, " EE"}, - {0x00, 0xFF, 0x0A, " SE"}, - {0x00, 0xFF, 0x0B, " HE"}, - {0x00, 0xFF, 0x0C, " EE"}, - {0x00, 0xFF, 0x0D, " Quad-Core Processor"}, - {0x00, 0xFF, 0x0F, ""}, - {0x01, 0x01, 0x01, "GF HE"}, - {0, 0, 0, NULL} -}; - - -static const struct str_s String1_socket_AM2[] = { - {0x00, 0x00, 0x00, "AMD Athlon(tm) Processor LE-"}, - {0x00, 0x00, 0x01, "AMD Sempron(tm) Processor LE-"}, - {0x00, 0x00, 0x02, "AMD Sempron(tm) 1"}, - {0x00, 0x00, 0x03, "AMD Athlon(tm) II 1"}, - {0x00, 0x01, 0x00, "Dual-Core AMD Opteron(tm) Processor 13"}, - {0x00, 0x01, 0x01, "AMD Athlon(tm)"}, - {0x00, 0x01, 0x03, "AMD Athlon(tm) II X2 2"}, - {0x00, 0x01, 0x04, "AMD Athlon(tm) II X2 B"}, - {0x00, 0x01, 0x05, "AMD Athlon(tm) II X2"}, - {0x00, 0x01, 0x07, "AMD Phenom(tm) II X2 5"}, - {0x00, 0x01, 0x0A, "AMD Phenom(tm) II X2"}, - {0x00, 0x01, 0x0B, "AMD Phenom(tm) II X2 B"}, - {0x00, 0x02, 0x00, "AMD Phenom(tm)"}, - {0x00, 0x02, 0x03, "AMD Phenom(tm) II X3 B"}, - {0x00, 0x02, 0x04, "AMD Phenom(tm) II X3"}, - {0x00, 0x02, 0x07, "AMD Athlon(tm) II X3 4"}, - {0x00, 0x02, 0x08, "AMD Phenom(tm) II X3 7"}, - {0x00, 0x02, 0x0A, "AMD Athlon(tm) II X3"}, - {0x00, 0x03, 0x00, "Quad-Core AMD Opteron(tm) Processor 13"}, - {0x00, 0x03, 0x01, "AMD Phenom(tm) FX-"}, - {0x00, 0x03, 0x02, "AMD Phenom(tm)"}, - {0x00, 0x03, 0x03, "AMD Phenom(tm) II X4 9"}, - {0x00, 0x03, 0x04, "AMD Phenom(tm) II X4 8"}, - {0x00, 0x03, 0x07, "AMD Phenom(tm) II X4 B"}, - {0x00, 0x03, 0x08, "AMD Phenom(tm) II X4"}, - {0x00, 0x03, 0x0A, "AMD Athlon(tm) II X4 6"}, - {0x00, 0x03, 0x0F, "AMD Athlon(tm) II X4"}, - {0, 0, 0, NULL} -}; - -static const struct str_s String2_socket_AM2[] = { - {0x00, 0x00, 0x00, "00"}, - {0x00, 0x00, 0x01, "10"}, - {0x00, 0x00, 0x02, "20"}, - {0x00, 0x00, 0x03, "30"}, - {0x00, 0x00, 0x04, "40"}, - {0x00, 0x00, 0x05, "50"}, - {0x00, 0x00, 0x06, "60"}, - {0x00, 0x00, 0x07, "70"}, - {0x00, 0x00, 0x08, "80"}, - {0x00, 0x00, 0x09, "90"}, - {0x00, 0x00, 0x09, " Processor"}, - {0x00, 0x00, 0x09, "u Processor"}, - {0x00, 0x01, 0x00, "00 Dual-Core Processor"}, - {0x00, 0x01, 0x01, "00e Dual-Core Processor"}, - {0x00, 0x01, 0x02, "00B Dual-Core Processor"}, - {0x00, 0x01, 0x03, "50 Dual-Core Processor"}, - {0x00, 0x01, 0x04, "50e Dual-Core Processor"}, - {0x00, 0x01, 0x05, "50B Dual-Core Processor"}, - {0x00, 0x01, 0x06, " Processor"}, - {0x00, 0x01, 0x07, "e Processor"}, - {0x00, 0x01, 0x09, "0 Processor"}, - {0x00, 0x01, 0x0A, "0e Processor"}, - {0x00, 0x01, 0x0B, "u Processor"}, - {0x00, 0x02, 0x00, "00 Triple-Core Processor"}, - {0x00, 0x02, 0x01, "00e Triple-Core Processor"}, - {0x00, 0x02, 0x02, "00B Triple-Core Processor"}, - {0x00, 0x02, 0x03, "50 Triple-Core Processor"}, - {0x00, 0x02, 0x04, "50e Triple-Core Processor"}, - {0x00, 0x02, 0x05, "50B Triple-Core Processor"}, - {0x00, 0x02, 0x06, " Processor"}, - {0x00, 0x02, 0x07, "e Processor"}, - {0x00, 0x02, 0x09, "0e Processor"}, - {0x00, 0x02, 0x0A, "0 Processor"}, - {0x00, 0x03, 0x00, "00 Quad-Core Processor"}, - {0x00, 0x03, 0x01, "00e Quad-Core Processor"}, - {0x00, 0x03, 0x02, "00B Quad-Core Processor"}, - {0x00, 0x03, 0x03, "50 Quad-Core Processor"}, - {0x00, 0x03, 0x04, "50e Quad-Core Processor"}, - {0x00, 0x03, 0x05, "50B Quad-Core Processor"}, - {0x00, 0x03, 0x06, " Processor"}, - {0x00, 0x03, 0x07, "e Processor"}, - {0x00, 0x03, 0x09, "0e Processor"}, - {0x00, 0x03, 0x0A, " SE"}, - {0x00, 0x03, 0x0B, " HE"}, - {0x00, 0x03, 0x0C, " EE"}, - {0x00, 0x03, 0x0D, " Quad-Core Processor"}, - {0x00, 0x03, 0x0E, "0 Processor"}, - {0x00, 0xFF, 0x0F, ""}, - {0, 0, 0, NULL} -}; - -static const struct str_s String1_socket_G34[] = { - {0x00, 0x07, 0x00, "AMD Opteron(tm) Processor 61"}, - {0x00, 0x0B, 0x00, "AMD Opteron(tm) Processor 61"}, - {0x01, 0x07, 0x01, "Embedded AMD Opteron(tm) Processor "}, - {0, 0, 0, NULL} -}; - -static const struct str_s String2_socket_G34[] = { - {0x00, 0x07, 0x00, " HE"}, - {0x00, 0x07, 0x01, " SE"}, - {0x00, 0x0B, 0x00, " HE"}, - {0x00, 0x0B, 0x01, " SE"}, - {0x00, 0x0B, 0x0F, ""}, - {0x01, 0x07, 0x01, " QS"}, - {0x01, 0x07, 0x02, " KS"}, - {0, 0, 0, NULL} -}; - -static const struct str_s String1_socket_C32[] = { - {0x00, 0x03, 0x00, "AMD Opteron(tm) Processor 41"}, - {0x00, 0x05, 0x00, "AMD Opteron(tm) Processor 41"}, - {0x01, 0x03, 0x01, "Embedded AMD Opteron(tm) Processor "}, - {0x01, 0x05, 0x01, "Embedded AMD Opteron(tm) Processor "}, - {0, 0, 0, NULL} -}; - -static const struct str_s String2_socket_C32[] = { - {0x00, 0x03, 0x00, " HE"}, - {0x00, 0x03, 0x01, " EE"}, - {0x00, 0x05, 0x00, " HE"}, - {0x00, 0x05, 0x01, " EE"}, - {0x01, 0x03, 0x01, "QS HE"}, - {0x01, 0x03, 0x02, "LE HE"}, - {0x01, 0x05, 0x01, "KX HE"}, - {0x01, 0x05, 0x02, "GL EE"}, - {0, 0, 0, NULL} -}; - -const char *unknown = "AMD Processor model unknown"; -const char *unknown2 = " type unknown"; -const char *sample = "AMD Engineering Sample"; -const char *thermal = "AMD Thermal Test Kit"; - - -static int strcpymax(char *dst, const char *src, int buflen) -{ - int i; - for (i = 0; i < buflen && src[i]; i++) - dst[i] = src[i]; - if (i >= buflen) - i--; - dst[i] = 0; - return i; -} - -#define NAME_STRING_MAXLEN 48 - -int init_processor_name(void) -{ - msr_t msr; - ssize_t i; - char program_string[NAME_STRING_MAXLEN]; - u32 *p_program_string = (u32 *)program_string; - uint8_t fam15h = 0; - uint32_t family; - - family = cpuid_eax(0x80000001); - family = ((family & 0xf00000) >> 16) | ((family & 0xf00) >> 8); - - if (family >= 0x6f) - /* Family 15h or later */ - fam15h = 1; - - /* null the string */ - memset(program_string, 0, sizeof(program_string)); - - if (fam15h) { - /* Family 15h or later */ - uint32_t dword; - struct device *cpu_fn5_dev = pcidev_on_root(0x18, 5); - pci_write_config32(cpu_fn5_dev, 0x194, 0); - dword = pci_read_config32(cpu_fn5_dev, 0x198); - if (dword == 0) { - strcpymax(program_string, sample, sizeof(program_string)); - } else { - /* Assemble the string from PCI configuration register contents */ - for (i = 0; i < 12; i++) { - pci_write_config32(cpu_fn5_dev, 0x194, i); - p_program_string[i] = pci_read_config32(cpu_fn5_dev, 0x198); - } - - /* Correctly place the null terminator */ - for (i = (NAME_STRING_MAXLEN - 2); i > 0; i--) { - if (program_string[i] != 0x20) - break; - } - program_string[i + 1] = 0; - } - } else { - /* variable names taken from fam10 revision guide for clarity */ - u32 BrandId; /* CPUID Fn8000_0001_EBX */ - u8 String1; /* BrandID[14:11] */ - u8 String2; /* BrandID[3:0] */ - u8 Model; /* BrandID[10:4] */ - u8 Pg; /* BrandID[15] */ - u8 PkgTyp; /* BrandID[31:28] */ - u8 NC; /* CPUID Fn8000_0008_ECX */ - const char *processor_name_string = unknown; - int j = 0, str2_checkNC = 1; - const struct str_s *str, *str2; - - /* Find out which CPU brand it is */ - BrandId = cpuid_ebx(0x80000001); - String1 = (u8)((BrandId >> 11) & 0x0F); - String2 = (u8)((BrandId >> 0) & 0x0F); - Model = (u8)((BrandId >> 4) & 0x7F); - Pg = (u8)((BrandId >> 15) & 0x01); - PkgTyp = (u8)((BrandId >> 28) & 0x0F); - NC = (u8)(cpuid_ecx(0x80000008) & 0xFF); - - if (!Model) { - processor_name_string = Pg ? thermal : sample; - goto done; - } - - switch (PkgTyp) { - case 0: /* F1207 */ - str = String1_socket_F; - str2 = String2_socket_F; - str2_checkNC = 0; - break; - case 1: /* AM2 */ - str = String1_socket_AM2; - str2 = String2_socket_AM2; - break; - case 3: /* G34 */ - str = String1_socket_G34; - str2 = String2_socket_G34; - str2_checkNC = 0; - break; - case 5: /* C32 */ - str = String1_socket_C32; - str2 = String2_socket_C32; - break; - default: - goto done; - } - - /* String1 */ - for (i = 0; str[i].value; i++) { - if ((str[i].Pg == Pg) && - (str[i].NC == NC) && - (str[i].String == String1)) { - processor_name_string = str[i].value; - break; - } - } - - if (!str[i].value) - goto done; - - j = strcpymax(program_string, processor_name_string, - sizeof(program_string)); - - /* Translate Model from 01-99 to ASCII and put it on the end. - * Numbers less than 10 should include a leading zero, e.g., 09.*/ - if (Model < 100 && j < sizeof(program_string) - 2) { - program_string[j++] = (Model / 10) + '0'; - program_string[j++] = (Model % 10) + '0'; - } - - processor_name_string = unknown2; - - /* String 2 */ - for (i = 0; str2[i].value; i++) { - if ((str2[i].Pg == Pg) && - ((str2[i].NC == NC) || !str2_checkNC) && - (str2[i].String == String2)) { - processor_name_string = str2[i].value; - break; - } - } - -done: - strcpymax(&program_string[j], processor_name_string, - sizeof(program_string) - j); - } - - printk(BIOS_DEBUG, "CPU model: %s\n", program_string); - - for (i = 0; i < 6; i++) { - msr.lo = p_program_string[(2 * i) + 0]; - msr.hi = p_program_string[(2 * i) + 1]; - wrmsr_amd(0xC0010030 + i, msr); - } - - return 0; -} diff --git a/src/cpu/amd/family_10h-family_15h/ram_calc.c b/src/cpu/amd/family_10h-family_15h/ram_calc.c deleted file mode 100644 index a1dc1f4ba6..0000000000 --- a/src/cpu/amd/family_10h-family_15h/ram_calc.c +++ /dev/null @@ -1,94 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include - -#include -#include -#include - -#include - -#include "ram_calc.h" - -static inline uint8_t is_fam15h(void) -{ - uint8_t fam15h = 0; - uint32_t family; - - family = cpuid_eax(0x80000001); - family = ((family & 0xf00000) >> 16) | ((family & 0xf00) >> 8); - - if (family >= 0x6f) - /* Family 15h or later */ - fam15h = 1; - - return fam15h; -} - -uint64_t get_uma_memory_size(uint64_t topmem) -{ - uint64_t uma_size = 0; - if (CONFIG(GFXUMA)) { - /* refer to UMA Size Consideration in 780 BDG. */ - if (topmem >= 0x40000000) /* 1GB and above system memory */ - uma_size = 0x10000000; /* 256M recommended UMA */ - - else if (topmem >= 0x20000000) /* 512M - 1023M system memory */ - uma_size = 0x8000000; /* 128M recommended UMA */ - - else if (topmem >= 0x10000000) /* 256M - 511M system memory */ - uma_size = 0x4000000; /* 64M recommended UMA */ - } - - return uma_size; -} - -uint64_t get_cc6_memory_size() -{ - uint8_t enable_cc6; - - uint64_t cc6_size = 0; - - if (is_fam15h()) { - enable_cc6 = 0; - -#if ENV_PCI_SIMPLE_DEVICE - if (pci_read_config32(PCI_DEV(0, 0x18, 2), 0x118) & (0x1 << 18)) - enable_cc6 = 1; -#else - struct device *dct_dev = pcidev_on_root(0x18, 2); - if (pci_read_config32(dct_dev, 0x118) & (0x1 << 18)) - enable_cc6 = 1; -#endif - - if (enable_cc6) { - /* Preserve the maximum possible CC6 save region - * This needs to be kept in sync with - * amdfam10_domain_read_resources() in northbridge.c - */ - cc6_size = 0x8000000; - } - } - - return cc6_size; -} - -void *cbmem_top_chipset(void) -{ - uint32_t topmem = rdmsr(TOP_MEM).lo; - - return (void *) topmem - get_uma_memory_size(topmem) - get_cc6_memory_size(); -} diff --git a/src/cpu/amd/family_10h-family_15h/ram_calc.h b/src/cpu/amd/family_10h-family_15h/ram_calc.h deleted file mode 100644 index 2b541d053e..0000000000 --- a/src/cpu/amd/family_10h-family_15h/ram_calc.h +++ /dev/null @@ -1,20 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef _AMD_MODEL_10XXX_RAM_CALC_H_ -#define _AMD_MODEL_10XXX_RAM_CALC_H_ - -uint64_t get_uma_memory_size(uint64_t topmem); -uint64_t get_cc6_memory_size(void); - -#endif diff --git a/src/cpu/amd/family_10h-family_15h/tsc_freq.c b/src/cpu/amd/family_10h-family_15h/tsc_freq.c deleted file mode 100644 index 793cc1bfad..0000000000 --- a/src/cpu/amd/family_10h-family_15h/tsc_freq.c +++ /dev/null @@ -1,36 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include -#include - -unsigned long tsc_freq_mhz(void) -{ - msr_t msr; - uint8_t cpufid; - uint8_t cpudid; - - /* On Family 10h/15h CPUs the TSC increments - * at the P0 clock rate. Read the P0 clock - * frequency from the P0 MSR and convert - * to MHz. See also the Family 15h BKDG - * Rev. 3.14 page 569. - */ - msr = rdmsr(PSTATE_0_MSR); - cpufid = (msr.lo & 0x3f); - cpudid = (msr.lo & 0x1c0) >> 6; - - return (100 * (cpufid + 0x10)) / (0x01 << cpudid); -} diff --git a/src/cpu/amd/family_10h-family_15h/update_microcode.c b/src/cpu/amd/family_10h-family_15h/update_microcode.c deleted file mode 100644 index 4a2db4e4d4..0000000000 --- a/src/cpu/amd/family_10h-family_15h/update_microcode.c +++ /dev/null @@ -1,70 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include - -struct id_mapping { - uint32_t orig_id; - uint16_t new_id; -}; - -static u16 get_equivalent_processor_rev_id(u32 orig_id) { - static const struct id_mapping id_mapping_table[] = { - /* Family 10h */ - { 0x100f00, 0x1000 }, - { 0x100f01, 0x1000 }, - { 0x100f02, 0x1000 }, - { 0x100f20, 0x1020 }, - { 0x100f21, 0x1020 }, /* DR-B1 */ - { 0x100f2A, 0x1020 }, /* DR-BA */ - { 0x100f22, 0x1022 }, /* DR-B2 */ - { 0x100f23, 0x1022 }, /* DR-B3 */ - { 0x100f42, 0x1041 }, /* RB-C2 */ - { 0x100f43, 0x1043 }, /* RB-C3 */ - { 0x100f52, 0x1041 }, /* BL-C2 */ - { 0x100f62, 0x1062 }, /* DA-C2 */ - { 0x100f63, 0x1043 }, /* DA-C3 */ - { 0x100f81, 0x1081 }, /* HY-D1 */ - { 0x100f91, 0x1081 }, /* HY-D1 */ - { 0x100fa0, 0x10A0 }, /* PH-E0 */ - - /* Family 15h */ - { 0x600f12, 0x6012 }, /* OR-B2 */ - { 0x600f20, 0x6020 }, /* OR-C0 */ - - /* Array terminator */ - { 0xffffff, 0x0000 }, - }; - - u32 new_id; - int i; - - new_id = 0; - - for (i = 0; id_mapping_table[i].orig_id != 0xffffff; i++) { - if (id_mapping_table[i].orig_id == orig_id) { - new_id = id_mapping_table[i].new_id; - break; - } - } - - return new_id; - -} - -void update_microcode(u32 cpu_deviceid) -{ - u32 equivalent_processor_rev_id = get_equivalent_processor_rev_id(cpu_deviceid); - amd_update_microcode_from_cbfs(equivalent_processor_rev_id); -} diff --git a/src/cpu/amd/quadcore/Makefile.inc b/src/cpu/amd/quadcore/Makefile.inc deleted file mode 100644 index c390b4e295..0000000000 --- a/src/cpu/amd/quadcore/Makefile.inc +++ /dev/null @@ -1 +0,0 @@ -ramstage-y += amd_sibling.c diff --git a/src/cpu/amd/quadcore/amd_sibling.c b/src/cpu/amd/quadcore/amd_sibling.c deleted file mode 100644 index ac637ff817..0000000000 --- a/src/cpu/amd/quadcore/amd_sibling.c +++ /dev/null @@ -1,118 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -extern struct device *get_node_pci(u32 nodeid, u32 fn); - -#if 0 -static int first_time = 1; -#endif - -#include "quadcore_id.c" - -static u32 get_max_siblings(u32 nodes) -{ - struct device *dev; - u32 nodeid; - u32 siblings = 0; - - //get max siblings from all the nodes - for (nodeid = 0; nodeid < nodes; nodeid++) { - int j; - dev = get_node_pci(nodeid, 3); - j = (pci_read_config32(dev, 0xe8) >> 12) & 3; - if (siblings < j) - siblings = j; - } - - return siblings; -} - - -static void enable_apic_ext_id(u32 nodes) -{ - struct device *dev; - u32 nodeid; - - //enable APIC_EXIT_ID all the nodes - for (nodeid = 0; nodeid < nodes; nodeid++) { - u32 val; - dev = get_node_pci(nodeid, 0); - val = pci_read_config32(dev, 0x68); - val |= (1 << 17)|(1 << 18); - pci_write_config32(dev, 0x68, val); - } -} - - -u32 get_apicid_base(u32 ioapic_num) -{ - u32 apicid_base; - u32 siblings; - u32 nb_cfg_54; - - u32 disable_siblings = !CONFIG(LOGICAL_CPUS); - - get_option(&disable_siblings, "multi_core"); - - siblings = get_max_siblings(sysconf.nodes); - - if (sysconf.bsp_apicid > 0) { - // IOAPIC could start from 0 - return 0; - } else if (sysconf.enabled_apic_ext_id) { - // enabled ext id but bsp = 0 - return 1; - } - - nb_cfg_54 = read_nb_cfg_54(); - - - //Construct apicid_base - - if ((!disable_siblings) && (siblings > 0)) { - /* for 8 way dual core, we will used up apicid 16:16, actually - 16 is not allowed by current kernel and the kernel will try - to get one that is small than 16 to make IOAPIC work. I don't - know when the kernel can support 256 APIC id. - (APIC_EXT_ID is enabled) */ - - //4:10 for two way 8:12 for four way 16:16 for eight way - //Use CONFIG_MAX_PHYSICAL_CPUS instead of nodes - //for better consistency? - apicid_base = nb_cfg_54 ? (siblings+1) * sysconf.nodes : - 8 * siblings + sysconf.nodes; - - } else { - apicid_base = sysconf.nodes; - } - - if ((apicid_base+ioapic_num-1) > 0xf) { - // We need to enable APIC EXT ID - printk(BIOS_SPEW, "if the IOAPIC device doesn't support 256 APIC id,\n you need to set CONFIG_ENABLE_APIC_EXT_ID in MB Option.lb so you can spare 16 id for IOAPIC\n"); - enable_apic_ext_id(sysconf.nodes); - } - - return apicid_base; -} diff --git a/src/cpu/amd/quadcore/quadcore.c b/src/cpu/amd/quadcore/quadcore.c deleted file mode 100644 index 8125fb474f..0000000000 --- a/src/cpu/amd/quadcore/quadcore.c +++ /dev/null @@ -1,146 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include -#include -#if CONFIG(HAVE_OPTION_TABLE) -#include "option_table.h" -#endif - -#include "cpu/amd/quadcore/quadcore_id.c" - -u32 get_core_num_in_bsp(u32 nodeid) -{ - u32 dword; - if (is_fam15h()) { - /* Family 15h moved CmpCap to F5x84 [7:0] */ - dword = pci_read_config32(NODE_PCI(nodeid, 5), 0x84); - dword &= 0xff; - } else { - dword = pci_read_config32(NODE_PCI(nodeid, 3), 0xe8); - dword >>= 12; - /* Bit 15 is CmpCap[2] since Revision D. */ - if ((cpuid_ecx(0x80000008) & 0xff) > 3) - dword = ((dword & 8) >> 1) | (dword & 3); - else - dword &= 3; - } - return dword; -} - -u8 set_apicid_cpuid_lo(void) -{ - // set the NB_CFG[54]=1; why the OS will be happy with that ??? - msr_t msr; - msr = rdmsr(NB_CFG_MSR); - msr.hi |= (1<<(54-32)); // InitApicIdCpuIdLo - wrmsr(NB_CFG_MSR, msr); - - return 1; -} - -void real_start_other_core(uint32_t nodeid, uint32_t cores) -{ - ssize_t i; - uint32_t dword; - - printk(BIOS_DEBUG, - "Start other core - nodeid: %02x cores: %02x\n", nodeid, cores); - - /* set PCI_DEV(0, 0x18+nodeid, 3), 0x44 bit 27 to redirect all MC4 - accesses and error logging to core0 */ - dword = pci_read_config32(NODE_PCI(nodeid, 3), 0x44); - dword |= 1 << 30; /* SyncFloodOnDramAdrParErr=1 */ - dword |= 1 << 27; /* NbMcaToMstCpuEn=1 */ - dword |= 1 << 21; /* SyncFloodOnAnyUcErr=1 */ - dword |= 1 << 20; /* SyncFloodOnWDT=1 */ - dword |= 1 << 2; /* SyncFloodOnDramUcEcc=1 */ - pci_write_config32(NODE_PCI(nodeid, 3), 0x44, dword); - if (is_fam15h()) { - uint32_t core_activation_flags = 0; - uint32_t active_cores = 0; - - /* Set PCI_DEV(0, 0x18+nodeid, 0), - * 0x1dc bits 7:1 to start cores - */ - dword = pci_read_config32(NODE_PCI(nodeid, 0), 0x1dc); - for (i = 1; i < cores + 1; i++) - core_activation_flags |= 1 << i; - /* Start the first core of each compute unit */ - active_cores |= core_activation_flags & 0x55; - pci_write_config32(NODE_PCI(nodeid, 0), 0x1dc, dword - | active_cores); - - /* Each core shares a single set of MTRR registers with - * another core in the same compute unit, therefore, it - * is important that one core in each CU starts in advance - * of the other in order to avoid one core stomping all over - * the other core's settings. - */ - - /* Wait for the first core of each compute unit to start... */ - for (i = 1; i < cores + 1; i++) { - if (!(i & 0x1)) { - uint32_t ap_apicid = - get_boot_apic_id(nodeid, i); - /* Timeout */ - wait_cpu_state(ap_apicid, F10_APSTATE_ASLEEP, - F10_APSTATE_ASLEEP); - } - } - - /* Start the second core of each compute unit */ - active_cores |= core_activation_flags & 0xaa; - pci_write_config32(NODE_PCI(nodeid, 0), 0x1dc, dword | - active_cores); - } else { - // set PCI_DEV(0, 0x18+nodeid, 0), 0x68 bit 5 to start core1 - dword = pci_read_config32(NODE_PCI(nodeid, 0), 0x68); - dword |= 1 << 5; - pci_write_config32(NODE_PCI(nodeid, 0), 0x68, dword); - - if (cores > 1) { - dword = pci_read_config32(NODE_PCI(nodeid, 0), 0x168); - for (i = 0; i < cores - 1; i++) - dword |= 1 << i; - pci_write_config32(NODE_PCI(nodeid, 0), 0x168, dword); - } - } -} - -#if (!CONFIG(CPU_AMD_MODEL_10XXX)) -//it is running on core0 of node0 -static void start_other_cores(void) -{ - u32 nodes; - u32 nodeid; - - // disable multi_core - if (read_option(multi_core, 0) != 0) { - printk(BIOS_DEBUG, "Skip additional core init\n"); - return; - } - - nodes = get_nodes(); - - for (nodeid = 0; nodeid < nodes; nodeid++) { - u32 cores = get_core_num_in_bsp(nodeid); - printk(BIOS_DEBUG, "init node: %02x cores: %02x pass 1\n", - nodeid, cores); - if (cores > 0) - real_start_other_core(nodeid, cores); - } -} -#endif diff --git a/src/cpu/amd/quadcore/quadcore_id.c b/src/cpu/amd/quadcore/quadcore_id.c deleted file mode 100644 index 7ec1bdb4f6..0000000000 --- a/src/cpu/amd/quadcore/quadcore_id.c +++ /dev/null @@ -1,152 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - - -#include -#include -#include -#include - -//called by bus_cpu_scan too -u32 read_nb_cfg_54(void) -{ - msr_t msr; - msr = rdmsr(NB_CFG_MSR); - return (msr.hi >> (54-32)) & 1; -} - -u32 get_initial_apicid(void) -{ - return (cpuid_ebx(1) >> 24) & 0xff; -} - -/* Called by amd_siblings (ramstage) as well */ -struct node_core_id get_node_core_id(u32 nb_cfg_54) -{ - struct node_core_id id; - uint8_t apicid; - uint8_t fam15h = 0; - uint8_t rev_gte_d = 0; - uint8_t dual_node = 0; - uint32_t f3xe8; - uint32_t family; - uint32_t model; - -#if ENV_PCI_SIMPLE_DEVICE - f3xe8 = pci_read_config32(NODE_PCI(0, 3), 0xe8); -#else - f3xe8 = pci_read_config32(get_node_pci(0, 3), 0xe8); -#endif - - family = model = cpuid_eax(0x80000001); - model = ((model & 0xf0000) >> 12) | ((model & 0xf0) >> 4); - family = ((family & 0xf00000) >> 16) | ((family & 0xf00) >> 8); - - if (family >= 0x6f) { - /* Family 15h or later */ - fam15h = 1; - nb_cfg_54 = 1; - } - - if ((model >= 0x8) || fam15h) - /* Revision D or later */ - rev_gte_d = 1; - - if (rev_gte_d) - /* Check for dual node capability */ - if (f3xe8 & 0x20000000) - dual_node = 1; - - /* Get the apicid via cpuid(1) ebx[31:24] - * The apicid format varies based on processor revision - */ - apicid = (cpuid_ebx(1) >> 24) & 0xff; - if (nb_cfg_54) { - if (fam15h && dual_node) { - id.coreid = apicid & 0x1f; - id.nodeid = (apicid & 0x60) >> 5; - } else if (fam15h && !dual_node) { - id.coreid = apicid & 0xf; - id.nodeid = (apicid & 0x70) >> 4; - } else if (rev_gte_d && dual_node) { - id.coreid = apicid & 0xf; - id.nodeid = (apicid & 0x30) >> 4; - } else if (rev_gte_d && !dual_node) { - id.coreid = apicid & 0x7; - id.nodeid = (apicid & 0x38) >> 3; - } else { - id.coreid = apicid & 0x3; - id.nodeid = (apicid & 0x1c) >> 2; - } - } else { - if (rev_gte_d && dual_node) { - id.coreid = (apicid & 0xf0) >> 4; - id.nodeid = apicid & 0x3; - } else if (rev_gte_d && !dual_node) { - id.coreid = (apicid & 0xe0) >> 5; - id.nodeid = apicid & 0x7; - } else { - id.coreid = (apicid & 0x60) >> 5; - id.nodeid = apicid & 0x7; - } - } - if (fam15h && dual_node) { - /* coreboot expects each separate processor die to be on a - * different nodeid. - * Since the code above returns nodeid 0 even on - * internal node 1 some fixup is needed... - */ - uint32_t f5x84; - uint8_t core_count; - -#if ENV_PCI_SIMPLE_DEVICE - f5x84 = pci_read_config32(NODE_PCI(0, 5), 0x84); -#else - f5x84 = pci_read_config32(get_node_pci(0, 5), 0x84); -#endif - core_count = (f5x84 & 0xff) + 1; - id.nodeid = id.nodeid * 2; - if (id.coreid >= core_count) { - id.nodeid += 1; - id.coreid = id.coreid - core_count; - } - } else if (rev_gte_d && dual_node) { - /* coreboot expects each separate processor die to be on a - * different nodeid. - * Since the code above returns nodeid 0 even on - * internal node 1 some fixup is needed... - */ - uint8_t core_count = (((f3xe8 & 0x00008000) >> 13) | - ((f3xe8 & 0x00003000) >> 12)) + 1; - - id.nodeid = id.nodeid * 2; - if (id.coreid >= core_count) { - id.nodeid += 1; - id.coreid = id.coreid - core_count; - } - } - - return id; -} - -#ifdef UNUSED_CODE -static u32 get_core_num(void) -{ - return (cpuid_ecx(0x80000008) & 0xff); -} -#endif - -struct node_core_id get_node_core_id_x(void) -{ - return get_node_core_id(read_nb_cfg_54()); -} diff --git a/src/cpu/amd/socket_AM2r2/Kconfig b/src/cpu/amd/socket_AM2r2/Kconfig deleted file mode 100644 index 60b11bf89b..0000000000 --- a/src/cpu/amd/socket_AM2r2/Kconfig +++ /dev/null @@ -1,29 +0,0 @@ -config CPU_AMD_SOCKET_AM2R2 - bool - select CPU_AMD_MODEL_10XXX - select PCI_IO_CFG_EXT - select X86_AMD_FIXED_MTRRS - -if CPU_AMD_SOCKET_AM2R2 - -config CPU_SOCKET_TYPE - hex - default 0x11 - -config EXT_RT_TBL_SUPPORT - bool - default n - -config CBB - hex - default 0x0 - -config CDB - hex - default 0x18 - -config XIP_ROM_SIZE - hex - default 0x80000 - -endif diff --git a/src/cpu/amd/socket_AM2r2/Makefile.inc b/src/cpu/amd/socket_AM2r2/Makefile.inc deleted file mode 100644 index 6917441967..0000000000 --- a/src/cpu/amd/socket_AM2r2/Makefile.inc +++ /dev/null @@ -1,13 +0,0 @@ -subdirs-y += ../family_10h-family_15h -subdirs-y += ../quadcore -subdirs-y += ../mtrr -subdirs-y += ../microcode -subdirs-y += ../../x86/tsc -subdirs-y += ../../x86/lapic -subdirs-y += ../../x86/cache -subdirs-y += ../../x86/pae -subdirs-y += ../../x86/mtrr -subdirs-y += ../../x86/smm -subdirs-y += ../smm - -cpu_incs-y += $(src)/cpu/amd/car/cache_as_ram.inc diff --git a/src/cpu/amd/socket_AM3/Kconfig b/src/cpu/amd/socket_AM3/Kconfig deleted file mode 100644 index 4f61685c68..0000000000 --- a/src/cpu/amd/socket_AM3/Kconfig +++ /dev/null @@ -1,29 +0,0 @@ -config CPU_AMD_SOCKET_AM3 - bool - select CPU_AMD_MODEL_10XXX - select PCI_IO_CFG_EXT - select X86_AMD_FIXED_MTRRS - -if CPU_AMD_SOCKET_AM3 - -config CPU_SOCKET_TYPE - hex - default 0x11 - -config EXT_RT_TBL_SUPPORT - bool - default n - -config CBB - hex - default 0x0 - -config CDB - hex - default 0x18 - -config XIP_ROM_SIZE - hex - default 0x80000 - -endif diff --git a/src/cpu/amd/socket_AM3/Makefile.inc b/src/cpu/amd/socket_AM3/Makefile.inc deleted file mode 100644 index 6917441967..0000000000 --- a/src/cpu/amd/socket_AM3/Makefile.inc +++ /dev/null @@ -1,13 +0,0 @@ -subdirs-y += ../family_10h-family_15h -subdirs-y += ../quadcore -subdirs-y += ../mtrr -subdirs-y += ../microcode -subdirs-y += ../../x86/tsc -subdirs-y += ../../x86/lapic -subdirs-y += ../../x86/cache -subdirs-y += ../../x86/pae -subdirs-y += ../../x86/mtrr -subdirs-y += ../../x86/smm -subdirs-y += ../smm - -cpu_incs-y += $(src)/cpu/amd/car/cache_as_ram.inc diff --git a/src/cpu/amd/socket_ASB2/Kconfig b/src/cpu/amd/socket_ASB2/Kconfig deleted file mode 100644 index 28779f5000..0000000000 --- a/src/cpu/amd/socket_ASB2/Kconfig +++ /dev/null @@ -1,29 +0,0 @@ -config CPU_AMD_SOCKET_ASB2 - bool - select CPU_AMD_MODEL_10XXX - select PCI_IO_CFG_EXT - select X86_AMD_FIXED_MTRRS - -if CPU_AMD_SOCKET_ASB2 - -config CPU_SOCKET_TYPE - hex - default 0x13 - -config EXT_RT_TBL_SUPPORT - bool - default n - -config CBB - hex - default 0x0 - -config CDB - hex - default 0x18 - -config XIP_ROM_SIZE - hex - default 0x80000 - -endif diff --git a/src/cpu/amd/socket_ASB2/Makefile.inc b/src/cpu/amd/socket_ASB2/Makefile.inc deleted file mode 100644 index 6917441967..0000000000 --- a/src/cpu/amd/socket_ASB2/Makefile.inc +++ /dev/null @@ -1,13 +0,0 @@ -subdirs-y += ../family_10h-family_15h -subdirs-y += ../quadcore -subdirs-y += ../mtrr -subdirs-y += ../microcode -subdirs-y += ../../x86/tsc -subdirs-y += ../../x86/lapic -subdirs-y += ../../x86/cache -subdirs-y += ../../x86/pae -subdirs-y += ../../x86/mtrr -subdirs-y += ../../x86/smm -subdirs-y += ../smm - -cpu_incs-y += $(src)/cpu/amd/car/cache_as_ram.inc diff --git a/src/cpu/amd/socket_C32/Kconfig b/src/cpu/amd/socket_C32/Kconfig deleted file mode 100644 index 65d1cbb345..0000000000 --- a/src/cpu/amd/socket_C32/Kconfig +++ /dev/null @@ -1,29 +0,0 @@ -config CPU_AMD_SOCKET_C32_NON_AGESA - bool - select CPU_AMD_MODEL_10XXX - select PCI_IO_CFG_EXT - select X86_AMD_FIXED_MTRRS - -if CPU_AMD_SOCKET_C32_NON_AGESA - -config CPU_SOCKET_TYPE - hex - default 0x14 - -config EXT_RT_TBL_SUPPORT - bool - default n - -config CBB - hex - default 0x0 - -config CDB - hex - default 0x18 - -config XIP_ROM_SIZE - hex - default 0x80000 - -endif diff --git a/src/cpu/amd/socket_C32/Makefile.inc b/src/cpu/amd/socket_C32/Makefile.inc deleted file mode 100644 index 6917441967..0000000000 --- a/src/cpu/amd/socket_C32/Makefile.inc +++ /dev/null @@ -1,13 +0,0 @@ -subdirs-y += ../family_10h-family_15h -subdirs-y += ../quadcore -subdirs-y += ../mtrr -subdirs-y += ../microcode -subdirs-y += ../../x86/tsc -subdirs-y += ../../x86/lapic -subdirs-y += ../../x86/cache -subdirs-y += ../../x86/pae -subdirs-y += ../../x86/mtrr -subdirs-y += ../../x86/smm -subdirs-y += ../smm - -cpu_incs-y += $(src)/cpu/amd/car/cache_as_ram.inc diff --git a/src/cpu/amd/socket_FM2/Kconfig b/src/cpu/amd/socket_FM2/Kconfig deleted file mode 100644 index a87694a137..0000000000 --- a/src/cpu/amd/socket_FM2/Kconfig +++ /dev/null @@ -1,29 +0,0 @@ -config CPU_AMD_SOCKET_FM2_NON_AGESA - bool - select CPU_AMD_MODEL_10XXX - select PCI_IO_CFG_EXT - select X86_AMD_FIXED_MTRRS - -if CPU_AMD_SOCKET_FM2_NON_AGESA - -config CPU_SOCKET_TYPE - hex - default 0x16 - -config EXT_RT_TBL_SUPPORT - bool - default n - -config CBB - hex - default 0x0 - -config CDB - hex - default 0x18 - -config XIP_ROM_SIZE - hex - default 0x80000 - -endif diff --git a/src/cpu/amd/socket_FM2/Makefile.inc b/src/cpu/amd/socket_FM2/Makefile.inc deleted file mode 100644 index 6917441967..0000000000 --- a/src/cpu/amd/socket_FM2/Makefile.inc +++ /dev/null @@ -1,13 +0,0 @@ -subdirs-y += ../family_10h-family_15h -subdirs-y += ../quadcore -subdirs-y += ../mtrr -subdirs-y += ../microcode -subdirs-y += ../../x86/tsc -subdirs-y += ../../x86/lapic -subdirs-y += ../../x86/cache -subdirs-y += ../../x86/pae -subdirs-y += ../../x86/mtrr -subdirs-y += ../../x86/smm -subdirs-y += ../smm - -cpu_incs-y += $(src)/cpu/amd/car/cache_as_ram.inc diff --git a/src/cpu/amd/socket_F_1207/Kconfig b/src/cpu/amd/socket_F_1207/Kconfig deleted file mode 100644 index c21ef556d7..0000000000 --- a/src/cpu/amd/socket_F_1207/Kconfig +++ /dev/null @@ -1,29 +0,0 @@ -config CPU_AMD_SOCKET_F_1207 - bool - select CPU_AMD_MODEL_10XXX - select PCI_IO_CFG_EXT - select X86_AMD_FIXED_MTRRS - -if CPU_AMD_SOCKET_F_1207 - -config CPU_SOCKET_TYPE - hex - default 0x10 - -config EXT_RT_TBL_SUPPORT - bool - default n - -config CBB - hex - default 0x0 - -config CDB - hex - default 0x18 - -config XIP_ROM_SIZE - hex - default 0x80000 - -endif diff --git a/src/cpu/amd/socket_F_1207/Makefile.inc b/src/cpu/amd/socket_F_1207/Makefile.inc deleted file mode 100644 index ece8d9ae98..0000000000 --- a/src/cpu/amd/socket_F_1207/Makefile.inc +++ /dev/null @@ -1,13 +0,0 @@ -subdirs-y += ../family_10h-family_15h -subdirs-y += ../quadcore -subdirs-y += ../mtrr -subdirs-y += ../microcode -subdirs-y += ../../x86/tsc -subdirs-y += ../../x86/lapic -subdirs-y += ../../x86/cache -subdirs-y += ../../x86/mtrr -subdirs-y += ../../x86/pae -subdirs-y += ../../x86/smm -subdirs-y += ../smm - -cpu_incs-y += $(src)/cpu/amd/car/cache_as_ram.inc diff --git a/src/cpu/amd/socket_G34/Kconfig b/src/cpu/amd/socket_G34/Kconfig deleted file mode 100644 index abc9726c78..0000000000 --- a/src/cpu/amd/socket_G34/Kconfig +++ /dev/null @@ -1,29 +0,0 @@ -config CPU_AMD_SOCKET_G34_NON_AGESA - bool - select CPU_AMD_MODEL_10XXX - select PCI_IO_CFG_EXT - select X86_AMD_FIXED_MTRRS - -if CPU_AMD_SOCKET_G34_NON_AGESA - -config CPU_SOCKET_TYPE - hex - default 0x15 - -config EXT_RT_TBL_SUPPORT - bool - default n - -config CBB - hex - default 0x0 - -config CDB - hex - default 0x18 - -config XIP_ROM_SIZE - hex - default 0x80000 - -endif diff --git a/src/cpu/amd/socket_G34/Makefile.inc b/src/cpu/amd/socket_G34/Makefile.inc deleted file mode 100644 index de33cd32d4..0000000000 --- a/src/cpu/amd/socket_G34/Makefile.inc +++ /dev/null @@ -1,14 +0,0 @@ -ramstage-y += socket_G34.c -subdirs-y += ../family_10h-family_15h -subdirs-y += ../quadcore -subdirs-y += ../mtrr -subdirs-y += ../microcode -subdirs-y += ../../x86/tsc -subdirs-y += ../../x86/lapic -subdirs-y += ../../x86/cache -subdirs-y += ../../x86/pae -subdirs-y += ../../x86/mtrr -subdirs-y += ../../x86/smm -subdirs-y += ../smm - -cpu_incs-y += $(src)/cpu/amd/car/cache_as_ram.inc diff --git a/src/cpu/amd/socket_G34/socket_G34.c b/src/cpu/amd/socket_G34/socket_G34.c deleted file mode 100644 index 1cac37c671..0000000000 --- a/src/cpu/amd/socket_G34/socket_G34.c +++ /dev/null @@ -1,18 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include - -struct chip_operations cpu_amd_socket_G34_ops = { - CHIP_NAME("socket G34") -}; diff --git a/src/cpu/x86/lapic/lapic_cpu_init.c b/src/cpu/x86/lapic/lapic_cpu_init.c index ea6a41d670..48350b3246 100644 --- a/src/cpu/x86/lapic/lapic_cpu_init.c +++ b/src/cpu/x86/lapic/lapic_cpu_init.c @@ -142,9 +142,7 @@ static int lapic_start_cpu(unsigned long apicid) } return 0; } -#if !CONFIG(CPU_AMD_MODEL_10XXX) mdelay(10); -#endif printk(BIOS_SPEW, "Deasserting INIT.\n"); From 7715c0dea7b4aa2b9f69923080958a93bfe4ddae Mon Sep 17 00:00:00 2001 From: Arthur Heymans Date: Wed, 20 Nov 2019 05:20:19 +0100 Subject: [PATCH 0314/1242] MAINTAINERS: Remove unsupported AMD platforms MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Change-Id: I3f8164577052298de2392e90375e132022713a6d Signed-off-by: Arthur Heymans Reviewed-on: https://review.coreboot.org/c/coreboot/+/36993 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki Reviewed-by: Angel Pons Reviewed-by: HAOUAS Elyes --- MAINTAINERS | 34 ---------------------------------- 1 file changed, 34 deletions(-) diff --git a/MAINTAINERS b/MAINTAINERS index a792673347..9c26ec5348 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -332,22 +332,6 @@ M: Tristan Corrick S: Maintained F: src/mainboard/asrock/h81m-hds/ -ASUS KFSN4-DRE & KFSN4-DRE_K8 MAINBOARDS -M: Timothy Pearson -S: Supported -F: src/mainboard/asus/kfsn4-dre/ -F: src/mainboard/asus/kfsn4-dre_k8/ - -ASUS KCMA-D8 MAINBOARD -M: Timothy Pearson -S: Supported -F: src/mainboard/asus/kcma-d8/ - -ASUS KGPE-D16 MAINBOARD -M: Timothy Pearson -S: Supported -F: src/mainboard/asus/kgpe-d16/ - ASUS MAXIMUS IV GENE-Z MAINBOARD M: Tristan Corrick S: Maintained @@ -408,24 +392,6 @@ M: Wim Vervoorn S: Maintained F: src/mainboard/portwell/m107/ -AMD FAMILY10H & FAMILY15H (NON-AGESA) CPUS & NORTHBRIDGE -M: Timothy Pearson -S: Supported -F: src/cpu/amd/family_10h-family_15h/ -F: src/northbridge/amd/amdfam10/ -F: src/northbridge/amd/amdmct/ -F: src/northbridge/amd/amdht/ - -AMD SB700 (NON-CIMX) SOUTHBRIDGE -M: Timothy Pearson -S: Supported -F: src/southbridge/amd/sb700/ - -AMD SR5650 SOUTHBRIDGE -M: Timothy Pearson -S: Supported -F: src/southbridge/amd/sr5650/ - ASPEED AST2050 DRIVER & COMMON CODE M: Timothy Pearson S: Supported From baa16e9c254b10b0a7963f197beabba5b544d41c Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ky=C3=B6sti=20M=C3=A4lkki?= Date: Tue, 5 Nov 2019 18:38:00 +0200 Subject: [PATCH 0315/1242] drivers/pc80/tpm: Replace __RAMSTAGE_ guards MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Change-Id: Ia6e161c3b4fc44292cdac692a2918c522680d60d Signed-off-by: Kyösti Mälkki Reviewed-on: https://review.coreboot.org/c/coreboot/+/36631 Reviewed-by: Arthur Heymans Reviewed-by: Aaron Durbin Tested-by: build bot (Jenkins) --- src/drivers/pc80/tpm/tis.c | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/src/drivers/pc80/tpm/tis.c b/src/drivers/pc80/tpm/tis.c index 5927377d15..1baab26b00 100644 --- a/src/drivers/pc80/tpm/tis.c +++ b/src/drivers/pc80/tpm/tis.c @@ -721,8 +721,6 @@ int tis_sendrecv(const uint8_t *sendbuf, size_t send_size, return tis_readresponse(recvbuf, recv_len); } -#ifdef __RAMSTAGE__ - /* * tis_setup_interrupt() * @@ -769,7 +767,7 @@ static void lpc_tpm_read_resources(struct device *dev) static void lpc_tpm_set_resources(struct device *dev) { tpm_config_t *config = (tpm_config_t *)dev->chip_info; - struct resource *res; + DEVTREE_CONST struct resource *res; for (res = dev->resource_list; res; res = res->next) { if (!(res->flags & IORESOURCE_ASSIGNED)) @@ -783,8 +781,10 @@ static void lpc_tpm_set_resources(struct device *dev) continue; } +#if !DEVTREE_EARLY res->flags |= IORESOURCE_STORED; report_resource_stored(dev, res, " "); +#endif } } @@ -973,8 +973,10 @@ static void lpc_tpm_fill_ssdt(struct device *dev) acpigen_pop_len(); /* Device */ acpigen_pop_len(); /* Scope */ +#if !DEVTREE_EARLY printk(BIOS_INFO, "%s.%s: %s %s\n", path, acpi_device_name(dev), dev->chip_ops->name, dev_path(dev)); +#endif } static const char *lpc_tpm_acpi_name(const struct device *dev) @@ -1006,5 +1008,3 @@ struct chip_operations drivers_pc80_tpm_ops = { CHIP_NAME("LPC TPM") .enable_dev = enable_dev }; - -#endif /* __RAMSTAGE__ */ From 35a047c4e5bce26bf355320ed61681bc07fefae9 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ky=C3=B6sti=20M=C3=A4lkki?= Date: Tue, 5 Nov 2019 18:38:00 +0200 Subject: [PATCH 0316/1242] drivers/crb: Replace __RAMSTAGE_ guards MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Change-Id: Ie2e6cdddc1edb95c442a4240267fe1fd6a11d37e Signed-off-by: Kyösti Mälkki Reviewed-on: https://review.coreboot.org/c/coreboot/+/36698 Reviewed-by: Arthur Heymans Reviewed-by: Aaron Durbin Tested-by: build bot (Jenkins) --- src/drivers/crb/tis.c | 13 +++++++------ 1 file changed, 7 insertions(+), 6 deletions(-) diff --git a/src/drivers/crb/tis.c b/src/drivers/crb/tis.c index 94bfb9ef15..b7a5df4829 100644 --- a/src/drivers/crb/tis.c +++ b/src/drivers/crb/tis.c @@ -104,8 +104,6 @@ int tis_sendrecv(const uint8_t *sendbuf, size_t sbuf_size, uint8_t *recvbuf, siz return 0; } -#ifdef __RAMSTAGE__ - static void crb_tpm_fill_ssdt(struct device *dev) { const char *path = acpi_device_path(dev); @@ -139,7 +137,7 @@ static const char *crb_tpm_acpi_name(const struct device *dev) return "TPM"; } -static struct device_operations crb_ops = { +static struct device_operations __unused crb_ops = { .read_resources = DEVICE_NOOP, .set_resources = DEVICE_NOOP, #if CONFIG(HAVE_ACPI_TABLES) @@ -151,9 +149,12 @@ static struct device_operations crb_ops = { static void enable_dev(struct device *dev) { +#if !DEVTREE_EARLY dev->ops = &crb_ops; +#endif } -struct chip_operations drivers_crb_ops = {CHIP_NAME("CRB TPM").enable_dev = enable_dev}; - -#endif /* __RAMSTAGE__ */ +struct chip_operations drivers_crb_ops = { + CHIP_NAME("CRB TPM") + .enable_dev = enable_dev +}; From 79ca4b55c5034e459e33bcce51456ea2a0420cf1 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ky=C3=B6sti=20M=C3=A4lkki?= Date: Sun, 23 Dec 2018 07:13:16 +0200 Subject: [PATCH 0317/1242] arch/x86: Remove copy_and_run() MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Nothing but a wrapper for run_ramstage() with an ugly name. Change-Id: Ie443a27cf18f829496ddadcc19c4ebec6a0b5a59 Signed-off-by: Kyösti Mälkki Reviewed-on: https://review.coreboot.org/c/coreboot/+/30389 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin --- src/arch/x86/Makefile.inc | 2 -- src/arch/x86/cbfs_and_run.c | 20 -------------------- src/arch/x86/include/arch/stages.h | 4 ---- 3 files changed, 26 deletions(-) delete mode 100644 src/arch/x86/cbfs_and_run.c diff --git a/src/arch/x86/Makefile.inc b/src/arch/x86/Makefile.inc index cc094d111f..737f254d6b 100644 --- a/src/arch/x86/Makefile.inc +++ b/src/arch/x86/Makefile.inc @@ -225,7 +225,6 @@ romstage-$(CONFIG_HAVE_ACPI_RESUME) += acpi_s3.c # environment. romstage-$(CONFIG_C_ENVIRONMENT_BOOTBLOCK) += gdt_init.S romstage-y += cbmem.c -romstage-y += cbfs_and_run.c romstage-$(CONFIG_IDT_IN_EVERY_STAGE) += exception.c romstage-$(CONFIG_IDT_IN_EVERY_STAGE) += idt.S romstage-y += memmove.c @@ -259,7 +258,6 @@ postcar-generic-ccopts += -D__POSTCAR__ postcar-$(CONFIG_HAVE_ACPI_RESUME) += acpi_s3.c postcar-y += gdt_init.S -postcar-y += cbfs_and_run.c postcar-$(CONFIG_IDT_IN_EVERY_STAGE) += exception.c postcar-$(CONFIG_IDT_IN_EVERY_STAGE) += idt.S postcar-y += exit_car.S diff --git a/src/arch/x86/cbfs_and_run.c b/src/arch/x86/cbfs_and_run.c deleted file mode 100644 index 5ca2c896e5..0000000000 --- a/src/arch/x86/cbfs_and_run.c +++ /dev/null @@ -1,20 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include - -asmlinkage void copy_and_run(void) -{ - run_ramstage(); -} diff --git a/src/arch/x86/include/arch/stages.h b/src/arch/x86/include/arch/stages.h index 3ef3cae148..0726cac1b1 100644 --- a/src/arch/x86/include/arch/stages.h +++ b/src/arch/x86/include/arch/stages.h @@ -14,8 +14,4 @@ #ifndef __ARCH_STAGES_H #define __ARCH_STAGES_H -#include - -asmlinkage void copy_and_run(void); - #endif From bd585fa89f9d0abf9c15e1495b1b3b925504456d Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ky=C3=B6sti=20M=C3=A4lkki?= Date: Wed, 3 Jul 2019 07:51:43 +0300 Subject: [PATCH 0318/1242] device/pci: Reduce scope of dev_find_slot() MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit We only keep it around because soc/intel debugging still depends on it. Change-Id: I3ea37c097bbcc3cf5c0574c7d727eae4f5bee307 Signed-off-by: Kyösti Mälkki Reviewed-on: https://review.coreboot.org/c/coreboot/+/34084 Tested-by: build bot (Jenkins) Reviewed-by: Arthur Heymans --- src/device/device_const.c | 3 ++- src/include/device/device.h | 1 - 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/src/device/device_const.c b/src/device/device_const.c index 5a3e89bfb9..c46f283608 100644 --- a/src/device/device_const.c +++ b/src/device/device_const.c @@ -34,7 +34,8 @@ DEVTREE_CONST struct device * DEVTREE_CONST all_devices = &dev_root; * @param devfn A device/function number. * @return Pointer to the device structure (if found), 0 otherwise. */ -DEVTREE_CONST struct device *dev_find_slot(unsigned int bus, + +static DEVTREE_CONST struct device *dev_find_slot(unsigned int bus, unsigned int devfn) { DEVTREE_CONST struct device *dev, *result; diff --git a/src/include/device/device.h b/src/include/device/device.h index b1c1651ec9..abcd0a453a 100644 --- a/src/include/device/device.h +++ b/src/include/device/device.h @@ -306,7 +306,6 @@ DEVTREE_CONST struct bus *pci_root_bus(void); * devices in all_devices singly-linked list as well as the time * when this function is called (secondary reflecting topology). */ -DEVTREE_CONST struct device *dev_find_slot(unsigned int bus, unsigned int devfn); DEVTREE_CONST struct device *pcidev_path_on_root_debug(pci_devfn_t devfn, const char *func); /* Robust discovery of chip_info. */ From 3382e53c64e7aef81cba23bb66bb1c615613faba Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ky=C3=B6sti=20M=C3=A4lkki?= Date: Thu, 21 Nov 2019 07:21:26 +0200 Subject: [PATCH 0319/1242] cpu/amd/microcode: Remove microcode update routine MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This was only used with native amdfam10h-15h. Change-Id: Id8e06b25c6ec716c07aee46fce10903c62b6d684 Signed-off-by: Kyösti Mälkki Reviewed-on: https://review.coreboot.org/c/coreboot/+/37073 Tested-by: build bot (Jenkins) Reviewed-by: Arthur Heymans --- src/cpu/amd/microcode/microcode.c | 225 ------------------------------ 1 file changed, 225 deletions(-) delete mode 100644 src/cpu/amd/microcode/microcode.c diff --git a/src/cpu/amd/microcode/microcode.c b/src/cpu/amd/microcode/microcode.c deleted file mode 100644 index 06939b0524..0000000000 --- a/src/cpu/amd/microcode/microcode.c +++ /dev/null @@ -1,225 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include -#include -#include -#include -#include -#include - -#define UCODE_DEBUG(fmt, args...) \ - do { printk(BIOS_DEBUG, "[microcode] "fmt, ##args); } while (0) - -#define UCODE_MAGIC 0x00414d44 -#define UCODE_EQUIV_CPU_TABLE_TYPE 0x00000000 -#define UCODE_SECTION_START_ID 0x00000001 -#define UCODE_MAGIC 0x00414d44 - -#define F1XH_MPB_MAX_SIZE 2048 -#define F15H_MPB_MAX_SIZE 4096 -#define CONT_HDR 12 -#define SECT_HDR 8 - -/* - * STRUCTURE OF A MICROCODE (UCODE) FILE - * Container Header - * Section Header - * Microcode Header - * Microcode "Blob" - * Section Header - * Microcode Header - * Microcode "Blob" - * ... - * ... - * (end of file) - * - * - * CONTAINER HEADER (offset 0 bytes from start of file) - * Total size = fixed size (12 bytes) + variable size - * [0:3] 32-bit unique ID - * [4:7] don't-care - * [8-11] Size (n) in bytes of variable portion of container header - * [12-n] don't-care - * - * SECTION HEADER (offset += 12+n) - * Total size = 8 bytes - * [0:3] Unique identifier signaling start of section (0x00000001) - * [4:7] Total size (m) of following microcode section, including microcode header - * - * MICROCODE HEADER (offset += 8) - * Total size = 64 bytes - * [0:3] Data code (32 bits) - * [4:7] Patch ID (32 bits) - * [8:9] Microcode patch data ID (16 bits) - * [10] c patch data length (8 bits) - * [11] init flag (8 bits) - * [12:15] ucode patch data cksum (32 bits) - * [16:19] nb dev ID (32 bits) - * [20:23] sb dev ID (32 bits) - * [24:25] Processor rev ID (16 bits) - * [26] nb revision ID (8 bits) - * [27] sb revision ID (8 bits) - * [28] BIOS API revision (8 bits) - * [29-31] Reserved 1 (array of three 8-bit values) - * [32-63] Match reg (array of eight 32-bit values) - * - * MICROCODE BLOB (offset += 64) - * Total size = m bytes - * - */ - -struct microcode { - uint32_t data_code; - uint32_t patch_id; - - uint16_t mc_patch_data_id; - uint8_t mc_patch_data_len; - uint8_t init_flag; - - uint32_t mc_patch_data_checksum; - - uint32_t nb_dev_id; - uint32_t sb_dev_id; - - uint16_t processor_rev_id; - uint8_t nb_rev_id; - uint8_t sb_rev_id; - - uint8_t bios_api_rev; - uint8_t reserved1[3]; - - uint32_t match_reg[8]; - - uint8_t m_patch_data[896]; - uint8_t resv2[896]; - - uint8_t x86_code_present; - uint8_t x86_code_entry[191]; -}; - -static void apply_microcode_patch(const struct microcode *m) -{ - uint32_t new_patch_id; - msr_t msr; - - /* apply patch */ - msr.hi = 0; - msr.lo = (uint32_t)m; - - wrmsr(MSR_PATCH_LOADER, msr); - - UCODE_DEBUG("patch id to apply = 0x%08x\n", m->patch_id); - - /* read the patch_id again */ - msr = rdmsr(IA32_BIOS_SIGN_ID); - new_patch_id = msr.lo; - - UCODE_DEBUG("updated to patch id = 0x%08x %s\n", new_patch_id, - (new_patch_id == m->patch_id) ? "success" : "fail"); -} - -static void amd_update_microcode(const void *ucode, size_t ucode_len, - uint32_t equivalent_processor_rev_id) -{ - const struct microcode *m; - const uint8_t *c = ucode; - const uint8_t *ucode_end = (uint8_t*)ucode + ucode_len; - const uint8_t *cur_section_hdr; - - uint32_t container_hdr_id; - uint32_t container_hdr_size; - uint32_t blob_size; - uint32_t sec_hdr_id; - - /* Container Header */ - container_hdr_id = read32(c); - if (container_hdr_id != UCODE_MAGIC) { - UCODE_DEBUG("Invalid container header ID\n"); - return; - } - - container_hdr_size = read32(c + 8); - cur_section_hdr = c + CONT_HDR + container_hdr_size; - - /* Read in first section header ID */ - sec_hdr_id = read32(cur_section_hdr); - c = cur_section_hdr + 4; - - /* Loop through sections */ - while (sec_hdr_id == UCODE_SECTION_START_ID && - c <= (ucode_end - F15H_MPB_MAX_SIZE)) { - - blob_size = read32(c); - - m = (struct microcode *)(c + 4); - - if (m->processor_rev_id == equivalent_processor_rev_id) { - apply_microcode_patch(m); - break; - } - - cur_section_hdr = c + 4 + blob_size; - sec_hdr_id = read32(cur_section_hdr); - c = cur_section_hdr + 4; - } -} - -static const char *microcode_cbfs_file[] = { - "microcode_amd.bin", - "microcode_amd_fam15h.bin", -}; - -void amd_update_microcode_from_cbfs(uint32_t equivalent_processor_rev_id) -{ - const void *ucode; - size_t ucode_len; - - uint32_t i; - - for (i = 0; i < ARRAY_SIZE(microcode_cbfs_file); i++) - { - if (equivalent_processor_rev_id == 0) { - UCODE_DEBUG("rev id not found. Skipping microcode patch!\n"); - return; - } - -#ifdef __PRE_RAM__ -#if CONFIG(HAVE_ROMSTAGE_MICROCODE_CBFS_SPINLOCK) - spin_lock(romstage_microcode_cbfs_lock()); -#endif -#endif - - ucode = cbfs_boot_map_with_leak(microcode_cbfs_file[i], - CBFS_TYPE_MICROCODE, &ucode_len); - if (!ucode) { - UCODE_DEBUG("microcode file not found. Skipping updates.\n"); -#ifdef __PRE_RAM__ -#if CONFIG(HAVE_ROMSTAGE_MICROCODE_CBFS_SPINLOCK) - spin_unlock(romstage_microcode_cbfs_lock()); -#endif -#endif - return; - } - - amd_update_microcode(ucode, ucode_len, equivalent_processor_rev_id); - -#ifdef __PRE_RAM__ -#if CONFIG(HAVE_ROMSTAGE_MICROCODE_CBFS_SPINLOCK) - spin_unlock(romstage_microcode_cbfs_lock()); -#endif -#endif - } -} From 9bb16cd9c5b0fdf198f2b78c193d1a02f4f51338 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ky=C3=B6sti=20M=C3=A4lkki?= Date: Mon, 19 Aug 2019 16:14:15 +0300 Subject: [PATCH 0320/1242] drivers/pc80/rtc: Remove CMOS spinlock MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This was only used with amdfam10h-15h, and only in romstage while commentary elsewhere says concurrent CMOS and CBFS access caused issues. We would want a cleaner approach on this, if re-implemented. Change-Id: I8512196cb55ff2b4542b1421a1bbae540450115a Signed-off-by: Kyösti Mälkki Reviewed-on: https://review.coreboot.org/c/coreboot/+/37074 Tested-by: build bot (Jenkins) Reviewed-by: Arthur Heymans Reviewed-by: Aaron Durbin --- src/drivers/pc80/rtc/mc146818rtc.c | 21 --------------------- 1 file changed, 21 deletions(-) diff --git a/src/drivers/pc80/rtc/mc146818rtc.c b/src/drivers/pc80/rtc/mc146818rtc.c index 6edffe0cd0..d3efdec16d 100644 --- a/src/drivers/pc80/rtc/mc146818rtc.c +++ b/src/drivers/pc80/rtc/mc146818rtc.c @@ -37,17 +37,6 @@ /* Don't warn for checking >= LB_CKS_RANGE_START even though it may be 0. */ #pragma GCC diagnostic ignored "-Wtype-limits" -#include - -#if (defined(__PRE_RAM__) && \ -CONFIG(HAVE_ROMSTAGE_NVRAM_CBFS_SPINLOCK)) - #define LOCK_NVRAM_CBFS_SPINLOCK() spin_lock(romstage_nvram_cbfs_lock()) - #define UNLOCK_NVRAM_CBFS_SPINLOCK() spin_unlock(romstage_nvram_cbfs_lock()) -#else - #define LOCK_NVRAM_CBFS_SPINLOCK() { } - #define UNLOCK_NVRAM_CBFS_SPINLOCK() { } -#endif - static void cmos_reset_date(void) { /* Now setup a default date equals to the build date */ @@ -274,13 +263,10 @@ enum cb_err get_option(void *dest, const char *name) if (!CONFIG(USE_OPTION_TABLE)) return CB_CMOS_OTABLE_DISABLED; - LOCK_NVRAM_CBFS_SPINLOCK(); - /* Figure out how long name is */ namelen = strnlen(name, CMOS_MAX_NAME_LENGTH); if (locate_cmos_layout(&rdev) != CB_SUCCESS) { - UNLOCK_NVRAM_CBFS_SPINLOCK(); return CB_CMOS_LAYOUT_NOT_FOUND; } ct = rdev_mmap_full(&rdev); @@ -288,7 +274,6 @@ enum cb_err get_option(void *dest, const char *name) printk(BIOS_ERR, "RTC: cmos_layout.bin could not be mapped. " "Options are disabled\n"); - UNLOCK_NVRAM_CBFS_SPINLOCK(); return CB_CMOS_LAYOUT_NOT_FOUND; } @@ -304,22 +289,18 @@ enum cb_err get_option(void *dest, const char *name) if (!found) { printk(BIOS_DEBUG, "No CMOS option '%s'.\n", name); rdev_munmap(&rdev, ct); - UNLOCK_NVRAM_CBFS_SPINLOCK(); return CB_CMOS_OPTION_NOT_FOUND; } if (!cmos_checksum_valid(LB_CKS_RANGE_START, LB_CKS_RANGE_END, LB_CKS_LOC)) { rdev_munmap(&rdev, ct); - UNLOCK_NVRAM_CBFS_SPINLOCK(); return CB_CMOS_CHECKSUM_INVALID; } if (get_cmos_value(ce->bit, ce->length, dest) != CB_SUCCESS) { rdev_munmap(&rdev, ct); - UNLOCK_NVRAM_CBFS_SPINLOCK(); return CB_CMOS_ACCESS_ERROR; } rdev_munmap(&rdev, ct); - UNLOCK_NVRAM_CBFS_SPINLOCK(); return CB_SUCCESS; } @@ -392,7 +373,6 @@ enum cb_err set_option(const char *name, void *value) namelen = strnlen(name, CMOS_MAX_NAME_LENGTH); if (locate_cmos_layout(&rdev) != CB_SUCCESS) { - UNLOCK_NVRAM_CBFS_SPINLOCK(); return CB_CMOS_LAYOUT_NOT_FOUND; } ct = rdev_mmap_full(&rdev); @@ -400,7 +380,6 @@ enum cb_err set_option(const char *name, void *value) printk(BIOS_ERR, "RTC: cmos_layout.bin could not be mapped. " "Options are disabled\n"); - UNLOCK_NVRAM_CBFS_SPINLOCK(); return CB_CMOS_LAYOUT_NOT_FOUND; } From f8dc4bc0224f18a33fcf19e3d754ac96a383a863 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ky=C3=B6sti=20M=C3=A4lkki?= Date: Mon, 19 Aug 2019 16:14:15 +0300 Subject: [PATCH 0321/1242] arch/x86: Remove spinlocks inside CAR MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This was only used with amdfam10h-15h, where cache coherency between nodes was supposed to be guaranteed with this code. We could want a cleaner and more generic approach for this, possibly utilising .data sections. Change-Id: I00da5c2b0570c26f2e3bb464274485cc2c08c8f0 Signed-off-by: Kyösti Mälkki Reviewed-on: https://review.coreboot.org/c/coreboot/+/34929 Tested-by: build bot (Jenkins) Reviewed-by: Arthur Heymans Reviewed-by: Aaron Durbin --- src/Kconfig | 16 --------------- src/arch/x86/include/arch/smp/spinlock.h | 26 ++++++------------------ src/console/printk.c | 14 ------------- 3 files changed, 6 insertions(+), 50 deletions(-) diff --git a/src/Kconfig b/src/Kconfig index ba9ae86067..8df5323cf6 100644 --- a/src/Kconfig +++ b/src/Kconfig @@ -527,22 +527,6 @@ config RESUME_PATH_SAME_AS_BOOT same path as a regular boot. e.g. an x86 system runs from the reset vector at 0xfffffff0 on both resume and warm/cold boot. -config HAVE_ROMSTAGE_CONSOLE_SPINLOCK - bool - default n - -config HAVE_ROMSTAGE_NVRAM_CBFS_SPINLOCK - bool - default n - help - This should be enabled on certain plaforms, such as the AMD - SR565x, that cannot handle concurrent CBFS accesses from - multiple APs during early startup. - -config HAVE_ROMSTAGE_MICROCODE_CBFS_SPINLOCK - bool - default n - config NO_MONOTONIC_TIMER def_bool n diff --git a/src/arch/x86/include/arch/smp/spinlock.h b/src/arch/x86/include/arch/smp/spinlock.h index f9186787af..8bdb125223 100644 --- a/src/arch/x86/include/arch/smp/spinlock.h +++ b/src/arch/x86/include/arch/smp/spinlock.h @@ -14,11 +14,6 @@ #ifndef ARCH_SMP_SPINLOCK_H #define ARCH_SMP_SPINLOCK_H -#if !defined(__PRE_RAM__) \ - || CONFIG(HAVE_ROMSTAGE_CONSOLE_SPINLOCK) \ - || CONFIG(HAVE_ROMSTAGE_NVRAM_CBFS_SPINLOCK) \ - || CONFIG(HAVE_ROMSTAGE_MICROCODE_CBFS_SPINLOCK) - /* * Your basic SMP spinlocks, allowing only a single CPU anywhere */ @@ -27,23 +22,14 @@ typedef struct { volatile unsigned int lock; } spinlock_t; -#ifdef __PRE_RAM__ -spinlock_t *romstage_console_lock(void); -void initialize_romstage_console_lock(void); -spinlock_t *romstage_nvram_cbfs_lock(void); -void initialize_romstage_nvram_cbfs_lock(void); -spinlock_t *romstage_microcode_cbfs_lock(void); -void initialize_romstage_microcode_cbfs_lock(void); -#endif - #define SPIN_LOCK_UNLOCKED { 1 } -#ifndef __PRE_RAM__ +#define STAGE_HAS_SPINLOCKS !ENV_ROMSTAGE_OR_BEFORE + +#if STAGE_HAS_SPINLOCKS + #define DECLARE_SPIN_LOCK(x) \ static spinlock_t x = SPIN_LOCK_UNLOCKED; -#else -#define DECLARE_SPIN_LOCK(x) -#endif /* * Simple spin lock operations. There are two variants, one clears IRQ's @@ -93,7 +79,7 @@ static __always_inline void cpu_relax(void) __asm__ __volatile__("rep;nop" : : : "memory"); } -#else /* !__PRE_RAM__ */ +#else #define DECLARE_SPIN_LOCK(x) #define barrier() do {} while (0) @@ -103,6 +89,6 @@ static __always_inline void cpu_relax(void) #define spin_unlock(lock) do {} while (0) #define cpu_relax() do {} while (0) -#endif /* !__PRE_RAM__ */ +#endif #endif /* ARCH_SMP_SPINLOCK_H */ diff --git a/src/console/printk.c b/src/console/printk.c index 4f9f547bc5..fd590fa6f7 100644 --- a/src/console/printk.c +++ b/src/console/printk.c @@ -23,9 +23,7 @@ #include #include -#if (!defined(__PRE_RAM__) && CONFIG(HAVE_ROMSTAGE_CONSOLE_SPINLOCK)) || !CONFIG(HAVE_ROMSTAGE_CONSOLE_SPINLOCK) DECLARE_SPIN_LOCK(console_lock) -#endif #define TRACK_CONSOLE_TIME (CONFIG(HAVE_MONOTONIC_TIMER) && \ (ENV_RAMSTAGE || !CONFIG(CAR_GLOBAL_MIGRATION))) @@ -95,13 +93,7 @@ int do_vprintk(int msg_level, const char *fmt, va_list args) return 0; DISABLE_TRACE; -#ifdef __PRE_RAM__ -#if CONFIG(HAVE_ROMSTAGE_CONSOLE_SPINLOCK) - spin_lock(romstage_console_lock()); -#endif -#else spin_lock(&console_lock); -#endif console_time_run(); @@ -114,13 +106,7 @@ int do_vprintk(int msg_level, const char *fmt, va_list args) console_time_stop(); -#ifdef __PRE_RAM__ -#if CONFIG(HAVE_ROMSTAGE_CONSOLE_SPINLOCK) - spin_unlock(romstage_console_lock()); -#endif -#else spin_unlock(&console_lock); -#endif ENABLE_TRACE; return i; From 56715ec23f6c34ae4bda3ac197aba0d90af06660 Mon Sep 17 00:00:00 2001 From: Usha P Date: Fri, 8 Nov 2019 16:00:40 +0530 Subject: [PATCH 0322/1242] soc/intel/skylake: Refactor pch_early_init() code This patch keeps required pch_early_init() function like ABASE programming, GPE and RTC init into bootblock and moves remaining functions like TCO configuration and SMBUS init into romstage/pch.c in order to maintain only required chipset programming for bootblock and verstage. TEST=Able to build and boot soraka. Change-Id: Idf7b04edc3fce147f7857591ce7d5a0cd03f43fe Signed-off-by: Usha P Reviewed-on: https://review.coreboot.org/c/coreboot/+/36672 Tested-by: build bot (Jenkins) Reviewed-by: Subrata Banik --- src/soc/intel/skylake/bootblock/bootblock.c | 3 +-- src/soc/intel/skylake/bootblock/pch.c | 14 ++-------- src/soc/intel/skylake/include/soc/bootblock.h | 2 +- src/soc/intel/skylake/include/soc/romstage.h | 1 + src/soc/intel/skylake/romstage/Makefile.inc | 1 + src/soc/intel/skylake/romstage/pch.c | 27 +++++++++++++++++++ src/soc/intel/skylake/romstage/romstage.c | 3 ++- 7 files changed, 35 insertions(+), 16 deletions(-) create mode 100644 src/soc/intel/skylake/romstage/pch.c diff --git a/src/soc/intel/skylake/bootblock/bootblock.c b/src/soc/intel/skylake/bootblock/bootblock.c index 596e3f184f..d1fbb83b8a 100644 --- a/src/soc/intel/skylake/bootblock/bootblock.c +++ b/src/soc/intel/skylake/bootblock/bootblock.c @@ -44,7 +44,6 @@ void bootblock_soc_init(void) * and abase, i2c programming and print platform info */ report_platform_info(); - pch_early_init(); - + pch_init(); gspi_early_bar_init(); } diff --git a/src/soc/intel/skylake/bootblock/pch.c b/src/soc/intel/skylake/bootblock/pch.c index c95a8d80e8..332060ed2d 100644 --- a/src/soc/intel/skylake/bootblock/pch.c +++ b/src/soc/intel/skylake/bootblock/pch.c @@ -2,7 +2,7 @@ * This file is part of the coreboot project. * * Copyright (C) 2014 Google Inc. - * Copyright (C) 2015-2018 Intel Corporation. + * Copyright (C) 2015-2019 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -24,8 +24,6 @@ #include #include #include -#include -#include #include #include #include @@ -34,8 +32,6 @@ #include #include #include -#include - #include "../chip.h" #define PCR_DMI_DMICTL 0x2234 @@ -150,7 +146,7 @@ void pch_early_iorange_init(void) pch_enable_lpc(); } -void pch_early_init(void) +void pch_init(void) { /* * Enabling ABASE for accessing PM1_STS, PM1_EN, PM1_CNT, @@ -164,12 +160,6 @@ void pch_early_init(void) */ soc_config_pwrmbase(); - /* Programming TCO_BASE_ADDRESS and TCO Timer Halt */ - tco_configure(); - - /* Program SMBUS_BASE_ADDRESS and Enable it */ - smbus_common_init(); - /* Set up GPE configuration */ pmc_gpe_init(); diff --git a/src/soc/intel/skylake/include/soc/bootblock.h b/src/soc/intel/skylake/include/soc/bootblock.h index a40f439936..302db50fb3 100644 --- a/src/soc/intel/skylake/include/soc/bootblock.h +++ b/src/soc/intel/skylake/include/soc/bootblock.h @@ -24,7 +24,7 @@ void bootblock_pch_early_init(void); /* Bootblock post console init programming */ void i2c_early_init(void); -void pch_early_init(void); +void pch_init(void); void pch_early_iorange_init(void); void report_platform_info(void); void report_memory_config(void); diff --git a/src/soc/intel/skylake/include/soc/romstage.h b/src/soc/intel/skylake/include/soc/romstage.h index 364bf52529..674652625b 100644 --- a/src/soc/intel/skylake/include/soc/romstage.h +++ b/src/soc/intel/skylake/include/soc/romstage.h @@ -21,6 +21,7 @@ void mainboard_memory_init_params(FSPM_UPD *mupd); void systemagent_early_init(void); +void pch_init(void); int smbus_read_byte(unsigned int device, unsigned int address); /* Board type */ enum board_type { diff --git a/src/soc/intel/skylake/romstage/Makefile.inc b/src/soc/intel/skylake/romstage/Makefile.inc index dff89ce2dc..1b069b6d49 100644 --- a/src/soc/intel/skylake/romstage/Makefile.inc +++ b/src/soc/intel/skylake/romstage/Makefile.inc @@ -1,3 +1,4 @@ romstage-y += ../../../../cpu/intel/car/romstage.c romstage-y += romstage.c romstage-y += systemagent.c +romstage-y += pch.c diff --git a/src/soc/intel/skylake/romstage/pch.c b/src/soc/intel/skylake/romstage/pch.c new file mode 100644 index 0000000000..88a7cc7163 --- /dev/null +++ b/src/soc/intel/skylake/romstage/pch.c @@ -0,0 +1,27 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include + +void pch_init(void) +{ + /* Programming TCO_BASE_ADDRESS and TCO Timer Halt */ + tco_configure(); + + /* Program SMBUS_BASE_ADDRESS and Enable it */ + smbus_common_init(); +} diff --git a/src/soc/intel/skylake/romstage/romstage.c b/src/soc/intel/skylake/romstage/romstage.c index a72b261a56..2904f05f01 100644 --- a/src/soc/intel/skylake/romstage/romstage.c +++ b/src/soc/intel/skylake/romstage/romstage.c @@ -146,7 +146,8 @@ void mainboard_romstage_entry(void) /* Program MCHBAR, DMIBAR, GDXBAR and EDRAMBAR */ systemagent_early_init(); - + /* Program PCH init */ + pch_init(); ps = pmc_get_power_state(); s3wake = pmc_fill_power_state(ps) == ACPI_S3; fsp_memory_init(s3wake); From 75396f67aa6f1f24007714c2c959c3eefe7d0124 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ky=C3=B6sti=20M=C3=A4lkki?= Date: Thu, 21 Nov 2019 08:09:34 +0200 Subject: [PATCH 0323/1242] Makefiles: Remove -D__PRE_RAM__ MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit All cases of testing for __PRE_RAM__ have been converted to equivalent ENV_xxx definitions from . Change-Id: Ib6cd598f17109cc1072818cebe4791f7410c3428 Signed-off-by: Kyösti Mälkki Reviewed-on: https://review.coreboot.org/c/coreboot/+/37075 Tested-by: build bot (Jenkins) Reviewed-by: Arthur Heymans Reviewed-by: Aaron Durbin --- Makefile.inc | 6 +++--- src/arch/x86/Makefile.inc | 8 ++++---- src/security/vboot/Makefile.inc | 6 ------ toolchain.inc | 2 +- 4 files changed, 8 insertions(+), 14 deletions(-) diff --git a/Makefile.inc b/Makefile.inc index fdbbdee21a..dc5272efb5 100644 --- a/Makefile.inc +++ b/Makefile.inc @@ -182,9 +182,9 @@ ramstage-postprocess=$$(eval DEPENDENCIES+=$$(addsuffix .d,$$(basename $(1)))) \ $(eval $(d)ramstage.a: $(call files-in-dir,$(d),$(filter-out %.ld,$(1))); rm -f $$@ && $(AR_ramstage) rcsT $$@ $$^ ) \ $(eval ramstage-objs:=$(d)ramstage.a $(filter-out $(filter-out %.ld, $(call files-in-dir,$(d),$(1))),$(ramstage-objs)))) -decompressor-generic-ccopts += -D__PRE_RAM__ -D__DECOMPRESSOR__ -bootblock-generic-ccopts += -D__PRE_RAM__ -D__BOOTBLOCK__ -romstage-generic-ccopts += -D__PRE_RAM__ -D__ROMSTAGE__ +decompressor-generic-ccopts += -D__DECOMPRESSOR__ +bootblock-generic-ccopts += -D__BOOTBLOCK__ +romstage-generic-ccopts += -D__ROMSTAGE__ ramstage-generic-ccopts += -D__RAMSTAGE__ ifeq ($(CONFIG_TRACE),y) ramstage-c-ccopts += -finstrument-functions diff --git a/src/arch/x86/Makefile.inc b/src/arch/x86/Makefile.inc index 737f254d6b..6f47e884a4 100644 --- a/src/arch/x86/Makefile.inc +++ b/src/arch/x86/Makefile.inc @@ -147,9 +147,9 @@ $(call src-to-obj,bootblock,$(dir)/bootblock_romcc.S): $(objgenerated)/bootblock bootblock-y += bootblock.ld $(call src-to-obj,bootblock,$(dir)/bootblock.ld): $(objgenerated)/bootblock.ld -bootblock_romccflags := -mcpu=i386 -O2 -D__PRE_RAM__ -D__BOOTBLOCK__ +bootblock_romccflags := -mcpu=i386 -O2 -D__BOOTBLOCK__ ifeq ($(CONFIG_SSE),y) -bootblock_romccflags := -mcpu=k7 -mno-mmx -msse -O2 -D__PRE_RAM__ -D__BOOTBLOCK__ +bootblock_romccflags := -mcpu=k7 -mno-mmx -msse -O2 -D__BOOTBLOCK__ endif # This is a hack in case there are no per chipset linker files. @@ -165,9 +165,9 @@ $(objgenerated)/bootblock.ld: $$(filter-out $(call src-to-obj,bootblock,src/arch $(objgenerated)/bootblock.inc: $(src)/arch/x86/$(subst ",,$(CONFIG_BOOTBLOCK_SOURCE)) $(objutil)/romcc/romcc $(OPTION_TABLE_H) $(KCONFIG_AUTOHEADER) # The open quote in the subst messes with syntax highlighting. Fix it - ") @printf " ROMCC $(subst $(obj)/,,$(@))\n" - $(CC_bootblock) -D__ROMCC__ -D__PRE_RAM__ -D__BOOTBLOCK__ $(CPPFLAGS_bootblock) -MM -MT$(objgenerated)/bootblock.inc \ + $(CC_bootblock) -D__ROMCC__ -D__BOOTBLOCK__ $(CPPFLAGS_bootblock) -MM -MT$(objgenerated)/bootblock.inc \ $< > $(objgenerated)/bootblock.inc.d - $(CC_bootblock) -D__ROMCC__ -D__PRE_RAM__ -D__BOOTBLOCK__ $(CPPFLAGS_bootblock) -E \ + $(CC_bootblock) -D__ROMCC__ -D__BOOTBLOCK__ $(CPPFLAGS_bootblock) -E \ $< -o $(objgenerated)/bootblock_romcc.c $(ROMCC) -c -S $(bootblock_romccflags) -I. $(CPPFLAGS_bootblock) $< -o $@ diff --git a/src/security/vboot/Makefile.inc b/src/security/vboot/Makefile.inc index 30c947c34d..010a06cfa7 100644 --- a/src/security/vboot/Makefile.inc +++ b/src/security/vboot/Makefile.inc @@ -22,12 +22,6 @@ ramstage-y += bootmode.c verstage-y += bootmode.c postcar-y += bootmode.c -# When VBOOT_STARTS_IN_ROMSTAGE is selected, DRAM is already up by -# the time verstage runs. -ifneq ($(CONFIG_VBOOT_STARTS_IN_ROMSTAGE),y) -verstage-generic-ccopts += -D__PRE_RAM__ -endif - verstage-generic-ccopts += -D__VERSTAGE__ ramstage-y += gbb.c diff --git a/toolchain.inc b/toolchain.inc index af085b4cad..c3aa3e50fa 100644 --- a/toolchain.inc +++ b/toolchain.inc @@ -70,7 +70,7 @@ CFLAGS_ppc64 += # stack use, we use 1.5K as heuristic, assuming that we typically have lots # of tiny stack frames and the odd large one. # -# Store larger buffers in BSS, use MAYBE_STATIC_BSS to share code with __PRE_RAM__ +# Store larger buffers in BSS, use MAYBE_STATIC_BSS to share data in cache-as-ram # on x86. # Since GCCs detection of dynamic array bounds unfortunately seems to be # very basic, you'll sometimes have to use a static upper bound for the From f5c0d612966d1ab3e8c2f1d1ae1de9ae2438bbab Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ky=C3=B6sti=20M=C3=A4lkki?= Date: Wed, 14 Aug 2019 13:02:41 +0300 Subject: [PATCH 0324/1242] intel/smm: Provide common smm_relocation_params MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Pull in all copies of smm_relocation_params structs defined for intel platforms. Pull in all the inlined MSR accessors to the header file. Change-Id: I39c6cffee95433aea1a3c783b869eedfff094413 Signed-off-by: Kyösti Mälkki Reviewed-on: https://review.coreboot.org/c/coreboot/+/34840 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin --- src/cpu/intel/common/Kconfig | 4 ++ src/cpu/intel/haswell/smmrelocate.c | 42 --------------- src/cpu/intel/smm/Makefile.inc | 1 + src/cpu/intel/smm/gen1/smmrelocate.c | 20 ------- .../soc/smm.h => cpu/intel/smm/smm_reloc.c} | 26 +-------- src/cpu/x86/Makefile.inc | 2 + src/include/cpu/intel/smm_reloc.h | 54 +++++++++++++++++++ src/mainboard/google/auron/smihandler.c | 1 - src/mainboard/google/jecht/smihandler.c | 1 - src/soc/intel/baytrail/cpu.c | 8 --- src/soc/intel/braswell/cpu.c | 9 ---- src/soc/intel/broadwell/cpu.c | 1 - src/soc/intel/broadwell/include/soc/smm.h | 38 ------------- src/soc/intel/broadwell/memmap.c | 1 - src/soc/intel/broadwell/pei_data.c | 1 - src/soc/intel/broadwell/romstage/raminit.c | 1 - src/soc/intel/broadwell/smi.c | 1 - src/soc/intel/broadwell/smihandler.c | 1 - src/soc/intel/broadwell/smmrelocate.c | 29 ---------- src/soc/intel/cannonlake/cpu.c | 1 - src/soc/intel/cannonlake/include/soc/smm.h | 39 -------------- src/soc/intel/cannonlake/smmrelocate.c | 11 ---- src/soc/intel/icelake/Kconfig | 1 + src/soc/intel/icelake/cpu.c | 1 - src/soc/intel/icelake/smmrelocate.c | 11 ---- src/soc/intel/skylake/cpu.c | 1 - src/soc/intel/skylake/include/soc/smm.h | 40 -------------- src/soc/intel/skylake/smmrelocate.c | 11 ---- src/soc/intel/tigerlake/cpu.c | 1 - src/soc/intel/tigerlake/include/soc/smm.h | 38 ------------- src/soc/intel/tigerlake/smmrelocate.c | 1 - 31 files changed, 64 insertions(+), 333 deletions(-) create mode 100644 src/cpu/intel/smm/Makefile.inc rename src/{soc/intel/icelake/include/soc/smm.h => cpu/intel/smm/smm_reloc.c} (51%) delete mode 100644 src/soc/intel/broadwell/include/soc/smm.h delete mode 100644 src/soc/intel/cannonlake/include/soc/smm.h delete mode 100644 src/soc/intel/skylake/include/soc/smm.h delete mode 100644 src/soc/intel/tigerlake/include/soc/smm.h diff --git a/src/cpu/intel/common/Kconfig b/src/cpu/intel/common/Kconfig index 4fa3affb55..0f2a65238c 100644 --- a/src/cpu/intel/common/Kconfig +++ b/src/cpu/intel/common/Kconfig @@ -26,3 +26,7 @@ config CPU_INTEL_COMMON_HYPERTHREADING bool endif + +config CPU_INTEL_COMMON_SMM + bool + default y if CPU_INTEL_COMMON diff --git a/src/cpu/intel/haswell/smmrelocate.c b/src/cpu/intel/haswell/smmrelocate.c index c33a00a95c..8419746cdc 100644 --- a/src/cpu/intel/haswell/smmrelocate.c +++ b/src/cpu/intel/haswell/smmrelocate.c @@ -45,49 +45,7 @@ #define SMRR_SUPPORTED (1 << 11) #define PRMRR_SUPPORTED (1 << 12) -struct smm_relocation_params { - uintptr_t ied_base; - size_t ied_size; - msr_t smrr_base; - msr_t smrr_mask; - msr_t prmrr_base; - msr_t prmrr_mask; - msr_t uncore_prmrr_base; - msr_t uncore_prmrr_mask; - /* The smm_save_state_in_msrs field indicates if SMM save state - * locations live in MSRs. This indicates to the CPUs how to adjust - * the SMMBASE and IEDBASE */ - int smm_save_state_in_msrs; -}; -/* This gets filled in and used during relocation. */ -static struct smm_relocation_params smm_reloc_params; - -static inline void write_smrr(struct smm_relocation_params *relo_params) -{ - printk(BIOS_DEBUG, "Writing SMRR. base = 0x%08x, mask=0x%08x\n", - relo_params->smrr_base.lo, relo_params->smrr_mask.lo); - wrmsr(IA32_SMRR_PHYS_BASE, relo_params->smrr_base); - wrmsr(IA32_SMRR_PHYS_MASK, relo_params->smrr_mask); -} - -static inline void write_prmrr(struct smm_relocation_params *relo_params) -{ - printk(BIOS_DEBUG, "Writing PRMRR. base = 0x%08x, mask=0x%08x\n", - relo_params->prmrr_base.lo, relo_params->prmrr_mask.lo); - wrmsr(MSR_PRMRR_PHYS_BASE, relo_params->prmrr_base); - wrmsr(MSR_PRMRR_PHYS_MASK, relo_params->prmrr_mask); -} - -static inline void write_uncore_prmrr(struct smm_relocation_params *relo_params) -{ - printk(BIOS_DEBUG, - "Writing UNCORE_PRMRR. base = 0x%08x, mask=0x%08x\n", - relo_params->uncore_prmrr_base.lo, - relo_params->uncore_prmrr_mask.lo); - wrmsr(MSR_UNCORE_PRMRR_PHYS_BASE, relo_params->uncore_prmrr_base); - wrmsr(MSR_UNCORE_PRMRR_PHYS_MASK, relo_params->uncore_prmrr_mask); -} static void update_save_state(int cpu, uintptr_t curr_smbase, uintptr_t staggered_smbase, diff --git a/src/cpu/intel/smm/Makefile.inc b/src/cpu/intel/smm/Makefile.inc new file mode 100644 index 0000000000..a49b796caf --- /dev/null +++ b/src/cpu/intel/smm/Makefile.inc @@ -0,0 +1 @@ +ramstage-$(CONFIG_HAVE_SMI_HANDLER) += smm_reloc.c diff --git a/src/cpu/intel/smm/gen1/smmrelocate.c b/src/cpu/intel/smm/gen1/smmrelocate.c index 5350d1c930..c177e9b952 100644 --- a/src/cpu/intel/smm/gen1/smmrelocate.c +++ b/src/cpu/intel/smm/gen1/smmrelocate.c @@ -39,17 +39,6 @@ #define C_BASE_SEG ((0 << 2) | (1 << 1) | (0 << 0)) - -struct smm_relocation_params { - uintptr_t ied_base; - size_t ied_size; - msr_t smrr_base; - msr_t smrr_mask; -}; - -/* This gets filled in and used during relocation. */ -static struct smm_relocation_params smm_reloc_params; - /* On model_6fx, model_1067x and model_106cx SMRR functions slightly differently. The MSR are at different location from the rest and need to be explicitly enabled in IA32_FEATURE_CONTROL MSR. */ @@ -88,15 +77,6 @@ static void write_smrr_alt(struct smm_relocation_params *relo_params) wrmsr(MSR_SMRR_PHYS_MASK, relo_params->smrr_mask); } -static void write_smrr(struct smm_relocation_params *relo_params) -{ - printk(BIOS_DEBUG, "Writing SMRR. base = 0x%08x, mask=0x%08x\n", - relo_params->smrr_base.lo, relo_params->smrr_mask.lo); - - wrmsr(IA32_SMRR_PHYS_BASE, relo_params->smrr_base); - wrmsr(IA32_SMRR_PHYS_MASK, relo_params->smrr_mask); -} - static void fill_in_relocation_params(struct smm_relocation_params *params) { uintptr_t tseg_base; diff --git a/src/soc/intel/icelake/include/soc/smm.h b/src/cpu/intel/smm/smm_reloc.c similarity index 51% rename from src/soc/intel/icelake/include/soc/smm.h rename to src/cpu/intel/smm/smm_reloc.c index 43931679bf..860c095abf 100644 --- a/src/soc/intel/icelake/include/soc/smm.h +++ b/src/cpu/intel/smm/smm_reloc.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2018 Intel Corp. - * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; version 2 of the License. @@ -13,26 +11,6 @@ * GNU General Public License for more details. */ -#ifndef _SOC_SMM_H_ -#define _SOC_SMM_H_ +#include -#include -#include -#include -#include - - -struct smm_relocation_params { - uintptr_t ied_base; - size_t ied_size; - msr_t smrr_base; - msr_t smrr_mask; - /* - * The smm_save_state_in_msrs field indicates if SMM save state - * locations live in MSRs. This indicates to the CPUs how to adjust - * the SMMBASE and IEDBASE - */ - int smm_save_state_in_msrs; -}; - -#endif +struct smm_relocation_params smm_reloc_params; diff --git a/src/cpu/x86/Makefile.inc b/src/cpu/x86/Makefile.inc index 9c18d44945..55d1fad7cb 100644 --- a/src/cpu/x86/Makefile.inc +++ b/src/cpu/x86/Makefile.inc @@ -6,6 +6,8 @@ ramstage-$(CONFIG_PARALLEL_MP) += mp_init.c ramstage-$(CONFIG_MIRROR_PAYLOAD_TO_RAM_BEFORE_LOADING) += mirror_payload.c ramstage-y += backup_default_smm.c +subdirs-$(CONFIG_CPU_INTEL_COMMON_SMM) += ../intel/smm + additional-dirs += $(obj)/cpu/x86 SIPI_ELF=$(obj)/cpu/x86/sipi_vector.elf diff --git a/src/include/cpu/intel/smm_reloc.h b/src/include/cpu/intel/smm_reloc.h index cb196fcd82..bef8d4eed7 100644 --- a/src/include/cpu/intel/smm_reloc.h +++ b/src/include/cpu/intel/smm_reloc.h @@ -14,7 +14,29 @@ #ifndef __INTEL_SMM_RELOC_H__ #define __INTEL_SMM_RELOC_H__ +#include #include +#include +#include + +struct smm_relocation_params { + uintptr_t ied_base; + size_t ied_size; + msr_t smrr_base; + msr_t smrr_mask; + msr_t prmrr_base; + msr_t prmrr_mask; + msr_t uncore_prmrr_base; + msr_t uncore_prmrr_mask; + /* + * The smm_save_state_in_msrs field indicates if SMM save state + * locations live in MSRs. This indicates to the CPUs how to adjust + * the SMMBASE and IEDBASE + */ + int smm_save_state_in_msrs; +}; + +extern struct smm_relocation_params smm_reloc_params; struct ied_header { char signature[10]; @@ -42,4 +64,36 @@ void smm_relocation_handler(int cpu, uintptr_t curr_smbase, uintptr_t staggered_ bool cpu_has_alternative_smrr(void); + +#define MSR_PRMRR_PHYS_BASE 0x1f4 +#define MSR_PRMRR_PHYS_MASK 0x1f5 +#define MSR_UNCORE_PRMRR_PHYS_BASE 0x2f4 +#define MSR_UNCORE_PRMRR_PHYS_MASK 0x2f5 + +static inline void write_smrr(struct smm_relocation_params *relo_params) +{ + printk(BIOS_DEBUG, "Writing SMRR. base = 0x%08x, mask=0x%08x\n", + relo_params->smrr_base.lo, relo_params->smrr_mask.lo); + wrmsr(IA32_SMRR_PHYS_BASE, relo_params->smrr_base); + wrmsr(IA32_SMRR_PHYS_MASK, relo_params->smrr_mask); +} + +static inline void write_prmrr(struct smm_relocation_params *relo_params) +{ + printk(BIOS_DEBUG, "Writing PRMRR. base = 0x%08x, mask=0x%08x\n", + relo_params->prmrr_base.lo, relo_params->prmrr_mask.lo); + wrmsr(MSR_PRMRR_PHYS_BASE, relo_params->prmrr_base); + wrmsr(MSR_PRMRR_PHYS_MASK, relo_params->prmrr_mask); +} + +static inline void write_uncore_prmrr(struct smm_relocation_params *relo_params) +{ + printk(BIOS_DEBUG, + "Writing UNCORE_PRMRR. base = 0x%08x, mask=0x%08x\n", + relo_params->uncore_prmrr_base.lo, + relo_params->uncore_prmrr_mask.lo); + wrmsr(MSR_UNCORE_PRMRR_PHYS_BASE, relo_params->uncore_prmrr_base); + wrmsr(MSR_UNCORE_PRMRR_PHYS_MASK, relo_params->uncore_prmrr_mask); +} + #endif diff --git a/src/mainboard/google/auron/smihandler.c b/src/mainboard/google/auron/smihandler.c index 4cc0aa8221..862e2c32e0 100644 --- a/src/mainboard/google/auron/smihandler.c +++ b/src/mainboard/google/auron/smihandler.c @@ -19,7 +19,6 @@ #include #include #include -#include #include #include #include diff --git a/src/mainboard/google/jecht/smihandler.c b/src/mainboard/google/jecht/smihandler.c index 8e8c9d4b5d..f324813337 100644 --- a/src/mainboard/google/jecht/smihandler.c +++ b/src/mainboard/google/jecht/smihandler.c @@ -18,7 +18,6 @@ #include #include #include -#include #include #include #include diff --git a/src/soc/intel/baytrail/cpu.c b/src/soc/intel/baytrail/cpu.c index edc4e83da5..d12ece0930 100644 --- a/src/soc/intel/baytrail/cpu.c +++ b/src/soc/intel/baytrail/cpu.c @@ -33,7 +33,6 @@ #include #include #include -#include /* Core level MSRs */ const struct reg_script core_msr_script[] = { @@ -88,13 +87,6 @@ static const struct cpu_driver driver __cpu_driver = { * MP and SMM loading initialization. */ -struct smm_relocation_params { - msr_t smrr_base; - msr_t smrr_mask; -}; - -static struct smm_relocation_params smm_reloc_params; - /* Package level MSRs */ static const struct reg_script package_msr_script[] = { /* Set Package TDP to ~7W */ diff --git a/src/soc/intel/braswell/cpu.c b/src/soc/intel/braswell/cpu.c index 665b030245..a44b9cb2e5 100644 --- a/src/soc/intel/braswell/cpu.c +++ b/src/soc/intel/braswell/cpu.c @@ -22,7 +22,6 @@ #include #include #include -#include #include #include #include @@ -34,7 +33,6 @@ #include #include #include -#include #include /* Core level MSRs */ @@ -98,13 +96,6 @@ static const struct cpu_driver driver __cpu_driver = { * MP and SMM loading initialization. */ -struct smm_relocation_params { - msr_t smrr_base; - msr_t smrr_mask; -}; - -static struct smm_relocation_params smm_reloc_params; - /* Package level MSRs */ static const struct reg_script package_msr_script[] = { /* Set Package TDP to ~7W */ diff --git a/src/soc/intel/broadwell/cpu.c b/src/soc/intel/broadwell/cpu.c index 8fe66dce5b..287b5b5532 100644 --- a/src/soc/intel/broadwell/cpu.c +++ b/src/soc/intel/broadwell/cpu.c @@ -36,7 +36,6 @@ #include #include #include -#include #include #include #include diff --git a/src/soc/intel/broadwell/include/soc/smm.h b/src/soc/intel/broadwell/include/soc/smm.h deleted file mode 100644 index 909294c6e6..0000000000 --- a/src/soc/intel/broadwell/include/soc/smm.h +++ /dev/null @@ -1,38 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2014 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef _BROADWELL_SMM_H_ -#define _BROADWELL_SMM_H_ - -#include -#include - - -struct smm_relocation_params { - uintptr_t ied_base; - size_t ied_size; - msr_t smrr_base; - msr_t smrr_mask; - msr_t prmrr_base; - msr_t prmrr_mask; - msr_t uncore_prmrr_base; - msr_t uncore_prmrr_mask; - /* The smm_save_state_in_msrs field indicates if SMM save state - * locations live in MSRs. This indicates to the CPUs how to adjust - * the SMMBASE and IEDBASE */ - int smm_save_state_in_msrs; -}; - -#endif diff --git a/src/soc/intel/broadwell/memmap.c b/src/soc/intel/broadwell/memmap.c index ad50dd35db..48492d3468 100644 --- a/src/soc/intel/broadwell/memmap.c +++ b/src/soc/intel/broadwell/memmap.c @@ -21,7 +21,6 @@ #include #include #include -#include #include static uintptr_t dpr_region_start(void) diff --git a/src/soc/intel/broadwell/pei_data.c b/src/soc/intel/broadwell/pei_data.c index f745348a7f..09753addb8 100644 --- a/src/soc/intel/broadwell/pei_data.c +++ b/src/soc/intel/broadwell/pei_data.c @@ -19,7 +19,6 @@ #include #include #include -#include static void ABI_X86 send_to_console(unsigned char b) { diff --git a/src/soc/intel/broadwell/romstage/raminit.c b/src/soc/intel/broadwell/romstage/raminit.c index c13761df3a..03b564f83a 100644 --- a/src/soc/intel/broadwell/romstage/raminit.c +++ b/src/soc/intel/broadwell/romstage/raminit.c @@ -33,7 +33,6 @@ #include #include #include -#include #include /* diff --git a/src/soc/intel/broadwell/smi.c b/src/soc/intel/broadwell/smi.c index 17196da438..2bdeecc943 100644 --- a/src/soc/intel/broadwell/smi.c +++ b/src/soc/intel/broadwell/smi.c @@ -24,7 +24,6 @@ #include #include #include -#include void smm_southbridge_clear_state(void) { diff --git a/src/soc/intel/broadwell/smihandler.c b/src/soc/intel/broadwell/smihandler.c index ca99487eb5..c2843a7cc0 100644 --- a/src/soc/intel/broadwell/smihandler.c +++ b/src/soc/intel/broadwell/smihandler.c @@ -33,7 +33,6 @@ #include #include #include -#include #include #include diff --git a/src/soc/intel/broadwell/smmrelocate.c b/src/soc/intel/broadwell/smmrelocate.c index 21c534a4c6..b5af9895f9 100644 --- a/src/soc/intel/broadwell/smmrelocate.c +++ b/src/soc/intel/broadwell/smmrelocate.c @@ -30,37 +30,8 @@ #include #include #include -#include #include -/* This gets filled in and used during relocation. */ -static struct smm_relocation_params smm_reloc_params; - -static inline void write_smrr(struct smm_relocation_params *relo_params) -{ - printk(BIOS_DEBUG, "Writing SMRR. base = 0x%08x, mask=0x%08x\n", - relo_params->smrr_base.lo, relo_params->smrr_mask.lo); - wrmsr(IA32_SMRR_PHYS_BASE, relo_params->smrr_base); - wrmsr(IA32_SMRR_PHYS_MASK, relo_params->smrr_mask); -} - -static inline void write_prmrr(struct smm_relocation_params *relo_params) -{ - printk(BIOS_DEBUG, "Writing PRMRR. base = 0x%08x, mask=0x%08x\n", - relo_params->prmrr_base.lo, relo_params->prmrr_mask.lo); - wrmsr(MSR_PRMRR_PHYS_BASE, relo_params->prmrr_base); - wrmsr(MSR_PRMRR_PHYS_MASK, relo_params->prmrr_mask); -} - -static inline void write_uncore_prmrr(struct smm_relocation_params *relo_params) -{ - printk(BIOS_DEBUG, - "Writing UNCORE_PRMRR. base = 0x%08x, mask=0x%08x\n", - relo_params->uncore_prmrr_base.lo, - relo_params->uncore_prmrr_mask.lo); - wrmsr(MSR_UNCORE_PRMRR_PHYS_BASE, relo_params->uncore_prmrr_base); - wrmsr(MSR_UNCORE_PRMRR_PHYS_MASK, relo_params->uncore_prmrr_mask); -} static void update_save_state(int cpu, uintptr_t curr_smbase, uintptr_t staggered_smbase, diff --git a/src/soc/intel/cannonlake/cpu.c b/src/soc/intel/cannonlake/cpu.c index c3a27aeb36..f01b499108 100644 --- a/src/soc/intel/cannonlake/cpu.c +++ b/src/soc/intel/cannonlake/cpu.c @@ -28,7 +28,6 @@ #include #include #include -#include #include #include #include diff --git a/src/soc/intel/cannonlake/include/soc/smm.h b/src/soc/intel/cannonlake/include/soc/smm.h deleted file mode 100644 index 95c1abd622..0000000000 --- a/src/soc/intel/cannonlake/include/soc/smm.h +++ /dev/null @@ -1,39 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2014 Google Inc. - * Copyright (C) 2017 Intel Corporation. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef _SOC_SMM_H_ -#define _SOC_SMM_H_ - -#include -#include -#include -#include - - -struct smm_relocation_params { - uintptr_t ied_base; - size_t ied_size; - msr_t smrr_base; - msr_t smrr_mask; - /* - * The smm_save_state_in_msrs field indicates if SMM save state - * locations live in MSRs. This indicates to the CPUs how to adjust - * the SMMBASE and IEDBASE - */ - int smm_save_state_in_msrs; -}; - -#endif diff --git a/src/soc/intel/cannonlake/smmrelocate.c b/src/soc/intel/cannonlake/smmrelocate.c index 6680bf3717..54e2f927b8 100644 --- a/src/soc/intel/cannonlake/smmrelocate.c +++ b/src/soc/intel/cannonlake/smmrelocate.c @@ -31,20 +31,9 @@ #include #include #include -#include #include #include "chip.h" -/* This gets filled in and used during relocation. */ -static struct smm_relocation_params smm_reloc_params; - -static inline void write_smrr(struct smm_relocation_params *relo_params) -{ - printk(BIOS_DEBUG, "Writing SMRR. base = 0x%08x, mask=0x%08x\n", - relo_params->smrr_base.lo, relo_params->smrr_mask.lo); - wrmsr(IA32_SMRR_PHYS_BASE, relo_params->smrr_base); - wrmsr(IA32_SMRR_PHYS_MASK, relo_params->smrr_mask); -} static void update_save_state(int cpu, uintptr_t curr_smbase, uintptr_t staggered_smbase, diff --git a/src/soc/intel/icelake/Kconfig b/src/soc/intel/icelake/Kconfig index 418c3171bd..cb9de149d3 100644 --- a/src/soc/intel/icelake/Kconfig +++ b/src/soc/intel/icelake/Kconfig @@ -36,6 +36,7 @@ config CPU_SPECIFIC_OPTIONS select SMP select SOC_AHCI_PORT_IMPLEMENTED_INVERT select PMC_GLOBAL_RESET_ENABLE_LOCK + select CPU_INTEL_COMMON_SMM select SOC_INTEL_COMMON select SOC_INTEL_COMMON_ACPI_WAKE_SOURCE select SOC_INTEL_COMMON_BLOCK diff --git a/src/soc/intel/icelake/cpu.c b/src/soc/intel/icelake/cpu.c index a2d9f7a6bc..e058442585 100644 --- a/src/soc/intel/icelake/cpu.c +++ b/src/soc/intel/icelake/cpu.c @@ -30,7 +30,6 @@ #include #include #include -#include #include static void soc_fsp_load(void) diff --git a/src/soc/intel/icelake/smmrelocate.c b/src/soc/intel/icelake/smmrelocate.c index 8f56ad6650..cc8a5ff2e8 100644 --- a/src/soc/intel/icelake/smmrelocate.c +++ b/src/soc/intel/icelake/smmrelocate.c @@ -30,20 +30,9 @@ #include #include #include -#include #include #include -/* This gets filled in and used during relocation. */ -static struct smm_relocation_params smm_reloc_params; - -static inline void write_smrr(struct smm_relocation_params *relo_params) -{ - printk(BIOS_DEBUG, "Writing SMRR. base = 0x%08x, mask=0x%08x\n", - relo_params->smrr_base.lo, relo_params->smrr_mask.lo); - wrmsr(IA32_SMRR_PHYS_BASE, relo_params->smrr_base); - wrmsr(IA32_SMRR_PHYS_MASK, relo_params->smrr_mask); -} static void update_save_state(int cpu, uintptr_t curr_smbase, uintptr_t staggered_smbase, diff --git a/src/soc/intel/skylake/cpu.c b/src/soc/intel/skylake/cpu.c index 7a45693ad7..f5273f6fc7 100644 --- a/src/soc/intel/skylake/cpu.c +++ b/src/soc/intel/skylake/cpu.c @@ -41,7 +41,6 @@ #include #include #include -#include #include #include diff --git a/src/soc/intel/skylake/include/soc/smm.h b/src/soc/intel/skylake/include/soc/smm.h deleted file mode 100644 index 88ce9e35c3..0000000000 --- a/src/soc/intel/skylake/include/soc/smm.h +++ /dev/null @@ -1,40 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2014 Google Inc. - * Copyright (C) 2015 Intel Corporation. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef _SOC_SMM_H_ -#define _SOC_SMM_H_ - -#include -#include -#include -#include -#include - - -struct smm_relocation_params { - uintptr_t ied_base; - size_t ied_size; - msr_t smrr_base; - msr_t smrr_mask; - /* - * The smm_save_state_in_msrs field indicates if SMM save state - * locations live in MSRs. This indicates to the CPUs how to adjust - * the SMMBASE and IEDBASE - */ - int smm_save_state_in_msrs; -}; - -#endif diff --git a/src/soc/intel/skylake/smmrelocate.c b/src/soc/intel/skylake/smmrelocate.c index e1779d1141..65d96ae954 100644 --- a/src/soc/intel/skylake/smmrelocate.c +++ b/src/soc/intel/skylake/smmrelocate.c @@ -31,20 +31,9 @@ #include #include #include -#include #include #include "chip.h" -/* This gets filled in and used during relocation. */ -static struct smm_relocation_params smm_reloc_params; - -static inline void write_smrr(struct smm_relocation_params *relo_params) -{ - printk(BIOS_DEBUG, "Writing SMRR. base = 0x%08x, mask=0x%08x\n", - relo_params->smrr_base.lo, relo_params->smrr_mask.lo); - wrmsr(IA32_SMRR_PHYS_BASE, relo_params->smrr_base); - wrmsr(IA32_SMRR_PHYS_MASK, relo_params->smrr_mask); -} static void update_save_state(int cpu, uintptr_t curr_smbase, uintptr_t staggered_smbase, diff --git a/src/soc/intel/tigerlake/cpu.c b/src/soc/intel/tigerlake/cpu.c index 4174cd2d24..5f4f081818 100644 --- a/src/soc/intel/tigerlake/cpu.c +++ b/src/soc/intel/tigerlake/cpu.c @@ -36,7 +36,6 @@ #include #include #include -#include #include static void soc_fsp_load(void) diff --git a/src/soc/intel/tigerlake/include/soc/smm.h b/src/soc/intel/tigerlake/include/soc/smm.h deleted file mode 100644 index 43931679bf..0000000000 --- a/src/soc/intel/tigerlake/include/soc/smm.h +++ /dev/null @@ -1,38 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2018 Intel Corp. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef _SOC_SMM_H_ -#define _SOC_SMM_H_ - -#include -#include -#include -#include - - -struct smm_relocation_params { - uintptr_t ied_base; - size_t ied_size; - msr_t smrr_base; - msr_t smrr_mask; - /* - * The smm_save_state_in_msrs field indicates if SMM save state - * locations live in MSRs. This indicates to the CPUs how to adjust - * the SMMBASE and IEDBASE - */ - int smm_save_state_in_msrs; -}; - -#endif diff --git a/src/soc/intel/tigerlake/smmrelocate.c b/src/soc/intel/tigerlake/smmrelocate.c index b3f98362e5..53f206d1c2 100644 --- a/src/soc/intel/tigerlake/smmrelocate.c +++ b/src/soc/intel/tigerlake/smmrelocate.c @@ -30,7 +30,6 @@ #include #include #include -#include #include #include From 490eab46a87fd7aab353f6492e22550d039e5448 Mon Sep 17 00:00:00 2001 From: Elyes HAOUAS Date: Wed, 6 Nov 2019 19:42:48 +0100 Subject: [PATCH 0325/1242] arch/acpigen.h: Correct PARENT_PREFIX encoding value The encoding value for PARENT_PREFIX is 0x5e. (ACPI specification version 6.3 page 1073) Change-Id: Ibbacb8b445157b377772f09572f87f8300a278dd Signed-off-by: Elyes HAOUAS Reviewed-on: https://review.coreboot.org/c/coreboot/+/36652 Reviewed-by: Nico Huber Tested-by: build bot (Jenkins) --- src/arch/x86/include/arch/acpigen.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/arch/x86/include/arch/acpigen.h b/src/arch/x86/include/arch/acpigen.h index 0f11226eb0..6fd9f73e05 100644 --- a/src/arch/x86/include/arch/acpigen.h +++ b/src/arch/x86/include/arch/acpigen.h @@ -87,7 +87,7 @@ enum { BANK_FIELD_OP = 0x87, DATA_REGION_OP = 0x88, ROOT_PREFIX = 0x5C, - PARENT_PREFIX = 0x5D, + PARENT_PREFIX = 0x5E, LOCAL0_OP = 0x60, LOCAL1_OP = 0x61, LOCAL2_OP = 0x62, From 9ea4c8a71ebad2aff593d6b6667510b79c4bab2a Mon Sep 17 00:00:00 2001 From: Patrick Georgi Date: Wed, 20 Nov 2019 22:07:39 +0100 Subject: [PATCH 0326/1242] util/xcompile: Only use -Wno-address-of-packed-member if supported MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit I thought gcc ignores -Wno-* stuff that it doesn't know about, but apparently not. Change-Id: If265a7bcdcfb5e83cc06b1f914dd6bab964eaca6 Signed-off-by: Patrick Georgi Reviewed-on: https://review.coreboot.org/c/coreboot/+/37037 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin Reviewed-by: Kyösti Mälkki --- util/xcompile/xcompile | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/util/xcompile/xcompile b/util/xcompile/xcompile index f3400fef49..8335c347fb 100755 --- a/util/xcompile/xcompile +++ b/util/xcompile/xcompile @@ -185,6 +185,8 @@ detect_special_flags() { testcc "$GCC" "$CFLAGS_GCC -Wl,--build-id=none" && CFLAGS_GCC="$CFLAGS_GCC -Wl,--build-id=none" + testcc "$GCC" "$CFLAGS_GCC -Wno-address-of-packed-member" && + CFLAGS_GCC="$CFLAGS_GCC -Wno-address-of-packed-member" case "$architecture" in x86) ;; @@ -219,7 +221,7 @@ SUBARCH_SUPPORTED+=${TSUPP-${TARCH}} GCC_CC_${TARCH}:=${GCC} GCC_CFLAGS_${TARCH}:=${CFLAGS_GCC} # Generally available for GCC's cc1: -GCC_CFLAGS_${TARCH}+=-Wlogical-op -Wno-address-of-packed-member +GCC_CFLAGS_${TARCH}+=-Wlogical-op GCC_ADAFLAGS_${TARCH}:=${CFLAGS_GCC} GCC_COMPILER_RT_${TARCH}:=${CC_RT_GCC} GCC_COMPILER_RT_FLAGS_${TARCH}:=${CC_RT_EXTRA_GCC} From 386d3418ef2af7f6d392994873e4fe2239f79d4a Mon Sep 17 00:00:00 2001 From: Peter Lemenkov Date: Wed, 20 Nov 2019 14:50:31 +0100 Subject: [PATCH 0327/1242] mb/lenovo/{x201,x60}/smihandler: Use mdelay instead of udelay for large values Change-Id: I7d20a850f8c2a1fcdee358c9e73d4c04eb3d7de8 Signed-off-by: Peter Lemenkov Reviewed-on: https://review.coreboot.org/c/coreboot/+/37006 Reviewed-by: HAOUAS Elyes Tested-by: build bot (Jenkins) --- src/mainboard/lenovo/x201/smihandler.c | 6 +++--- src/mainboard/lenovo/x60/smihandler.c | 2 +- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/src/mainboard/lenovo/x201/smihandler.c b/src/mainboard/lenovo/x201/smihandler.c index 4ba10b47cd..91cb0ce2d6 100644 --- a/src/mainboard/lenovo/x201/smihandler.c +++ b/src/mainboard/lenovo/x201/smihandler.c @@ -53,7 +53,7 @@ static void mainboard_smi_handle_ec_sci(void) case 0x58: /* Dock Event */ ec_clr_bit(0x03, 2); - udelay(250000); + mdelay(250); dock_connect(); ec_set_bit(0x03, 2); /* set dock LED to indicate status */ @@ -101,9 +101,9 @@ void mainboard_smi_sleep(u8 slp_typ) { if (slp_typ == 3) { u8 ec_wake = ec_read(0x32); - /* If EC wake events are enabled, enable wake on EC WAKE GPE. */ + /* If EC wake events are enabled, enable wake on EC WAKE GPE. */ if (ec_wake & 0x14) { - /* Redirect EC WAKE GPE to SCI. */ + /* Redirect EC WAKE GPE to SCI. */ gpi_route_interrupt(GPE_EC_WAKE, GPI_IS_SCI); } } diff --git a/src/mainboard/lenovo/x60/smihandler.c b/src/mainboard/lenovo/x60/smihandler.c index 0a2c7e2e6b..7aacc451c0 100644 --- a/src/mainboard/lenovo/x60/smihandler.c +++ b/src/mainboard/lenovo/x60/smihandler.c @@ -51,7 +51,7 @@ int mainboard_io_trap_handler(int smif) switch (smif) { case SMI_DOCK_CONNECT: ec_clr_bit(0x03, 2); - udelay(250000); + mdelay(250); if (!dock_connect()) { ec_set_bit(0x03, 2); /* set dock LED to indicate status */ From 45ecb0eba1452e3637e565a7d993bf717ca616a7 Mon Sep 17 00:00:00 2001 From: Matt DeVillier Date: Tue, 19 Nov 2019 14:43:59 -0600 Subject: [PATCH 0328/1242] purism/librem_skl: add/use VBT file Add VBT file extracted from vendor (AMI) firmware, use by default to ensure functional display after resume from S3 when using libgfxinit. Test: build/boot Librem 13v2/3/4,15v3/4 boards, verify functional display after resume from S3 when using libgfxinit. Change-Id: I6bc5dab60e3601d56dae4300efee255d7c58329d Signed-off-by: Matt DeVillier Reviewed-on: https://review.coreboot.org/c/coreboot/+/37068 Reviewed-by: Arthur Heymans Tested-by: build bot (Jenkins) --- src/mainboard/purism/librem_skl/Kconfig | 6 ++++++ src/mainboard/purism/librem_skl/data.vbt | Bin 0 -> 4608 bytes 2 files changed, 6 insertions(+) create mode 100644 src/mainboard/purism/librem_skl/data.vbt diff --git a/src/mainboard/purism/librem_skl/Kconfig b/src/mainboard/purism/librem_skl/Kconfig index a58ca0b718..05fd43d2de 100644 --- a/src/mainboard/purism/librem_skl/Kconfig +++ b/src/mainboard/purism/librem_skl/Kconfig @@ -5,6 +5,7 @@ config BOARD_PURISM_BASEBOARD_LIBREM_SKL select HAVE_ACPI_RESUME select HAVE_ACPI_TABLES select INTEL_LPSS_UART_FOR_CONSOLE + select INTEL_GMA_HAVE_VBT select SOC_INTEL_COMMON_BLOCK_HDA_VERB select SOC_INTEL_SKYLAKE select SPD_READ_BY_WORD @@ -55,6 +56,11 @@ config VGA_BIOS_ID default "8086,1916" if BOARD_PURISM_LIBREM13_V2 || BOARD_PURISM_LIBREM15_V3 default "8086,5916" if BOARD_PURISM_LIBREM13_V4 || BOARD_PURISM_LIBREM15_V4 +# Override the default variant behavior, since same VBT +# is used for all variants. +config INTEL_GMA_VBT_FILE + default "src/mainboard/$(MAINBOARDDIR)/data.vbt" + config DIMM_MAX int default 1 diff --git a/src/mainboard/purism/librem_skl/data.vbt b/src/mainboard/purism/librem_skl/data.vbt new file mode 100644 index 0000000000000000000000000000000000000000..3a818c463b6cab3ac816b29dec8819d2267bf860 GIT binary patch literal 4608 zcmeHKU2GIp6h1SvKeKmcw$mxfvS2+{gl&O#wm^kiWwyJ8F5S}IZmA`ju!UWuaiOIx zrufGu)}#r+?1LIKXqxz-!Ivh+Cu8JAB_V1x@#hU*Oq6J1BE}bBJ@eD8(9mv3P%)g@ zbI+YSXTE#Rxo7S@ySl%<57S+H5|OSBbSMit{GirRyO7%BJ?Xu%NMB@cd!i@Wg)yp562IW=klT6dV)=0_wc@iUg#SHikDfZrp?zZfd5V9^On{y*1p@x_PU@Vja<* z?qoa>>5KR5!k%7?#nX{=x}&>2u?LgAJ)QCPcwa|MVP!X>!z0H=hn_k(j-hBhHq#s% zEKtj2j1G^EG-4#5$6ixs41059xzT5G*+zw#AZI~zaR8hfstn-ZYBSIPhz5uVq6#hp zTnH`|3Ne<1aEh3|dRI+|iEnE4YYz1=n z%Cj`1<2DDJNdSIMhXcM^*dc^qT;SnFVGG6W9Ed)Ibv_jyBTf;YcQg2w_yY0I#J>|? zCH8t4R1>cxeu%hc+r=9WB&baS4 zT5KZbNXe1bUu)al5CB?Ter-1m_*V>RI1mrA}2 z-STwZzLuQ_N@SZ#r8~VR*T7EtfCaH_a+T%FZh#AKDFRFYt1f?JpviMdX(=sx8$3bV zb#L2T2yT@B=98eA0V{vuXT1z&y_dPEn*V0cjG4N`Wyh6L&Dj?0`@8Mk2wWe5Rh{si zuTaE`_o-s0&VE*VYa{nRNjb@jv@sZf)RmzVLJ)u$tcGQffuvP8iPk=Qoe`A{Awre; zfi6O!Ac2o9P&h*bQ2#0jk1!l$+8ARmFnot;A2Rj{!ylRUCu5w1Yb9-~#G(=oN!oJ~ zds)KwCGBI0eJ~6DUEnWrg=)W5=!l~-?L7m$ zY{|=B8yF{*7jZXbKJRzH*jDZdFYau|D zg+PB@JWGEU^#)`LP?J&BYV$4I2HHf4^w&` z`kC9;mTn-P=SAW&t-l9OZYMM2RJre_!z&Bxx!2(*p>YOas!Vr8cjJQptc!>L?o)uj E0D!i;9{>OV literal 0 HcmV?d00001 From 50155024141f48cf3048272073d352906a2be0b6 Mon Sep 17 00:00:00 2001 From: Morgan Jang Date: Wed, 6 Nov 2019 10:24:47 +0800 Subject: [PATCH 0329/1242] src/drivers/ipmi: Implement BMC Get Self Test Result function According to IPMI SPEC, it is recommended that BIOS includes provisions for checking and reporting on the basic health of BMC by executing the Get Self Test Results command and checking the result. TEST=Check the result in response data to confirm the BMC status is fine or not. Change-Id: I20349cec2e8e9420d177d725de2a5560d354fe47 Signed-off-by: Morgan Jang Reviewed-on: https://review.coreboot.org/c/coreboot/+/36638 Tested-by: build bot (Jenkins) Reviewed-by: David Hendricks --- src/drivers/ipmi/ipmi_kcs.h | 13 ++++++++ src/drivers/ipmi/ipmi_kcs_ops.c | 59 +++++++++++++++++++++++++++++++++ 2 files changed, 72 insertions(+) diff --git a/src/drivers/ipmi/ipmi_kcs.h b/src/drivers/ipmi/ipmi_kcs.h index f35802e27b..b3775219c3 100644 --- a/src/drivers/ipmi/ipmi_kcs.h +++ b/src/drivers/ipmi/ipmi_kcs.h @@ -22,6 +22,12 @@ #define IPMI_BMC_GET_DEVICE_ID 0x01 #define IPMI_IPMI_VERSION_MINOR(x) ((x) >> 4) #define IPMI_IPMI_VERSION_MAJOR(x) ((x) & 0xf) +#define IPMI_BMC_GET_SELFTEST_RESULTS 0x04 +#define IPMI_APP_SELFTEST_RESERVED 0xFF +#define IPMI_APP_SELFTEST_NO_ERROR 0x55 +#define IPMI_APP_SELFTEST_NOT_IMPLEMENTED 0x56 +#define IPMI_APP_SELFTEST_ERROR 0x57 +#define IPMI_APP_SELFTEST_FATAL_HW_ERROR 0x58 #define IPMI_NETFN_FIRMWARE 0x08 #define IPMI_NETFN_STORAGE 0x0a @@ -52,4 +58,11 @@ struct ipmi_devid_rsp { uint8_t product_id[2]; } __packed; +/* Get Self Test Results */ +struct ipmi_selftest_rsp { + struct ipmi_rsp resp; + uint8_t result; + uint8_t param; +} __packed; + #endif diff --git a/src/drivers/ipmi/ipmi_kcs_ops.c b/src/drivers/ipmi/ipmi_kcs_ops.c index 90f19dddb8..5cb8995df9 100644 --- a/src/drivers/ipmi/ipmi_kcs_ops.c +++ b/src/drivers/ipmi/ipmi_kcs_ops.c @@ -59,11 +59,34 @@ static int ipmi_get_device_id(struct device *dev, struct ipmi_devid_rsp *rsp) return 0; } +static int ipmi_get_bmc_self_test_result(struct device *dev, struct ipmi_selftest_rsp *rsp) +{ + int ret; + + ret = ipmi_kcs_message(dev->path.pnp.port, IPMI_NETFN_APPLICATION, 0, + IPMI_BMC_GET_SELFTEST_RESULTS, NULL, 0, (u8 *)rsp, + sizeof(*rsp)); + + if (ret < sizeof(struct ipmi_rsp) || rsp->resp.completion_code) { + printk(BIOS_ERR, "IPMI: %s command failed (ret=%d resp=0x%x)\n", + __func__, ret, rsp->resp.completion_code); + return 1; + } + if (ret != sizeof(*rsp)) { + printk(BIOS_ERR, "IPMI: %s response truncated\n", __func__); + return 1; + } + + return 0; +} + static void ipmi_kcs_init(struct device *dev) { struct ipmi_devid_rsp rsp; uint32_t man_id = 0, prod_id = 0; struct drivers_ipmi_config *conf = NULL; + struct ipmi_selftest_rsp selftestrsp; + uint8_t retry_count; if (!dev->enabled) return; @@ -92,6 +115,42 @@ static void ipmi_kcs_init(struct device *dev) } } + printk(BIOS_INFO, "Get BMC self test result..."); + for (retry_count = 0; retry_count < conf->bmc_boot_timeout; retry_count++) { + if (!ipmi_get_bmc_self_test_result(dev, &selftestrsp)) + break; + + mdelay(1000); + } + + switch (selftestrsp.result) { + case IPMI_APP_SELFTEST_NO_ERROR: /* 0x55 */ + printk(BIOS_DEBUG, "No Error\n"); + break; + case IPMI_APP_SELFTEST_NOT_IMPLEMENTED: /* 0x56 */ + printk(BIOS_DEBUG, "Function Not Implemented\n"); + break; + case IPMI_APP_SELFTEST_ERROR: /* 0x57 */ + printk(BIOS_ERR, "BMC: Corrupted or inaccessible data or device\n"); + /* Don't write tables if communication failed */ + dev->enabled = 0; + break; + case IPMI_APP_SELFTEST_FATAL_HW_ERROR: /* 0x58 */ + printk(BIOS_ERR, "BMC: Fatal Hardware Error\n"); + /* Don't write tables if communication failed */ + dev->enabled = 0; + break; + case IPMI_APP_SELFTEST_RESERVED: /* 0xFF */ + printk(BIOS_DEBUG, "Reserved\n"); + break; + + default: /* Other Device Specific Hardware Error */ + printk(BIOS_ERR, "BMC: Device Specific Error\n"); + /* Don't write tables if communication failed */ + dev->enabled = 0; + break; + } + if (!ipmi_get_device_id(dev, &rsp)) { /* Queried the IPMI revision from BMC */ ipmi_revision_minor = IPMI_IPMI_VERSION_MINOR(rsp.ipmi_version); From 61e3d01739fd5e7c85c084cb6c0cd0e7cb5fc89c Mon Sep 17 00:00:00 2001 From: Arthur Heymans Date: Thu, 21 Nov 2019 10:36:56 +0100 Subject: [PATCH 0330/1242] MAINTAINERS: Remove FSP1.0 and boards using it MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Change-Id: I0c6c36c7a425e8aeae272f5747ce2bdbb7caceaf Signed-off-by: Arthur Heymans Reviewed-on: https://review.coreboot.org/c/coreboot/+/37107 Reviewed-by: Kyösti Mälkki Reviewed-by: Werner Zeh Reviewed-by: Angel Pons Reviewed-by: HAOUAS Elyes Tested-by: build bot (Jenkins) --- MAINTAINERS | 52 ---------------------------------------------------- 1 file changed, 52 deletions(-) diff --git a/MAINTAINERS b/MAINTAINERS index 9c26ec5348..d4b19350b0 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -217,18 +217,10 @@ F: src/mainboard/google/parrot/ F: src/mainboard/google/slippy/ F: src/mainboard/google/stout/ -OCP MAINBOARDS -M: Philipp Deppenwiese -M: Patrick Rudolph -S: Supported -F: src/mainboard/ocp/wedge100s/ -F: src/mainboard/ocp/monolake/ - OPENCELLULAR MAINBOARDS M: Philipp Deppenwiese M: Patrick Rudolph S: Supported -F: src/mainboard/opencellular/rotundu/ F: src/mainboard/opencellular/elgon/ PURISM MAINBOARDS @@ -242,30 +234,6 @@ S: Maintained F: src/mainboard/samsung/lumpy/ F: src/mainboard/samsung/stumpy/ -INTEL MINNOWBOARD MAX MAINBOARD -M: Huang Jin -M: York Yang -S: Supported -F: src/mainboard/intel/minnowmax/ - -INTEL FSP BAYTRAIL CHIP & CRBs -M: Huang Jin -M: York Yang -M: Philipp Deppenwiese -S: Supported -F: src/soc/intel/fsp_baytrail/ -F: src/vendorcode/intel/fsp1_0/baytrail/ -F: src/mainboard/intel/bakersport_fsp/ -F: src/mainboard/intel/bayleybay_fsp/ - -INTEL FSP BROADWELL-DE SOC & CRB -M: York Yang -M: Philipp Deppenwiese -S: Supported -F: src/soc/intel/fsp_broadwell_de/ -F: src/vendorcode/intel/fsp1_0/broadwell_de/ -F: src/mainboard/intel/camelbackmountain_fsp/ - INTEL FSP DENVERTON-NS SOC & HARCUVAR CRB M: Vanessa Eusebio M: David Guckian @@ -274,24 +242,6 @@ F: src/mainboard/intel/harcuvar/ F: src/soc/intel/denverton_ns/ F: src/vendorcode/intel/fsp/fsp2_0/denverton_ns/ -FSP 1.0 RANGELEY & CRB -M: David Guckian -M: Fei Wang -S: Supported -F: src/cpu/intel/fsp_model_406dx/ -F: src/northbridge/intel/fsp_rangeley/ -F: src/southbridge/intel/fsp_rangeley/ -F: src/vendorcode/intel/fsp1_0/rangeley/ -F: src/mainboard/intel/mohonpeak/ - -INTEL FSP 1.0 -M: Huang Jin -M: York Yang -M: Philipp Deppenwiese -S: Supported -F: src/drivers/intel/fsp1_0/ -F: src/vendorcode/intel/fsp1_0/broadwell_de/ - INTEL FSP 1.1 M: Lee Leahy M: Huang Jin @@ -367,8 +317,6 @@ SIEMENS MC_xxxx MAINBOARDS M: Werner Zeh S: Maintained F: src/mainboard/siemens/mc_apl1/ -F: src/mainboard/siemens/mc_bdx1/ -F: src/mainboard/siemens/mc_tcu3/ SUPERMICRO X10SLM+-F MAINBOARD M: Tristan Corrick From 5a0edcbde1537ad9d4d94b0e5f355454c8e597cf Mon Sep 17 00:00:00 2001 From: Shelley Chen Date: Thu, 21 Nov 2019 01:20:26 -0800 Subject: [PATCH 0331/1242] mb/google/hatch/variant/kohaku: Config MEM_STRAP GPIOs Kohaku always used the default MEM_STRAPs in hatch baseboard. Adding explicit configuration for Kohaku in the event that MEM_STRAP is set differently in the baseboard gpio file. BUG=b:144895517 BRANCH=hatch TEST=None ./util/abuild/abuild -p none -t google/hatch -x -a Change-Id: I8f7105b3925f17c1741660d84c83c5d15f398a8d Signed-off-by: Shelley Chen Reviewed-on: https://review.coreboot.org/c/coreboot/+/37106 Reviewed-by: Kangheui Won Reviewed-by: Edward O'Callaghan Tested-by: build bot (Jenkins) --- .../google/hatch/variants/kohaku/gpio.c | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/src/mainboard/google/hatch/variants/kohaku/gpio.c b/src/mainboard/google/hatch/variants/kohaku/gpio.c index 87c586d5a2..61d3375d6d 100644 --- a/src/mainboard/google/hatch/variants/kohaku/gpio.c +++ b/src/mainboard/google/hatch/variants/kohaku/gpio.c @@ -55,6 +55,14 @@ static const struct pad_config gpio_table[] = { PAD_NC(GPP_E23, NONE), /* F1 : GPP_F1 ==> NC */ PAD_NC(GPP_F1, NONE), + /* F11 : PCH_MEM_STRAP2 */ + PAD_CFG_GPI(GPP_F11, NONE, PLTRST), + /* F20 : PCH_MEM_STRAP0 */ + PAD_CFG_GPI(GPP_F20, NONE, PLTRST), + /* F21 : PCH_MEM_STRAP1 */ + PAD_CFG_GPI(GPP_F21, NONE, PLTRST), + /* F22 : PCH_MEM_STRAP3 */ + PAD_CFG_GPI(GPP_F22, NONE, PLTRST), /* G0 : GPP_G0 ==> NC */ PAD_NC(GPP_G0, NONE), /* G1 : GPP_G1 ==> NC */ @@ -111,6 +119,14 @@ static const struct pad_config early_gpio_table[] = { PAD_CFG_NF(GPP_E5, NONE, PLTRST, NF1), /* F2 : MEM_CH_SEL */ PAD_CFG_GPI(GPP_F2, NONE, PLTRST), + /* F11 : PCH_MEM_STRAP2 */ + PAD_CFG_GPI(GPP_F11, NONE, PLTRST), + /* F20 : PCH_MEM_STRAP0 */ + PAD_CFG_GPI(GPP_F20, NONE, PLTRST), + /* F21 : PCH_MEM_STRAP1 */ + PAD_CFG_GPI(GPP_F21, NONE, PLTRST), + /* F22 : PCH_MEM_STRAP3 */ + PAD_CFG_GPI(GPP_F22, NONE, PLTRST), }; const struct pad_config *variant_early_gpio_table(size_t *num) From 07b402b3b9a54551201c66c0c9d7d6e393d57a74 Mon Sep 17 00:00:00 2001 From: Patrick Rudolph Date: Thu, 21 Nov 2019 09:30:21 +0100 Subject: [PATCH 0332/1242] mb/lenovo/t410: Fix I2C SPD address Use correct address for second DIMM. Tested on Lenovo T410: * Both DIMMs are found and are usable Change-Id: I8bace47f04a0e185c2901695879d4d4e12d4ce6a Signed-off-by: Patrick Rudolph Reviewed-on: https://review.coreboot.org/c/coreboot/+/37105 Reviewed-by: Arthur Heymans Reviewed-by: Paul Menzel Tested-by: build bot (Jenkins) --- src/mainboard/lenovo/t410/romstage.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/mainboard/lenovo/t410/romstage.c b/src/mainboard/lenovo/t410/romstage.c index 7c796de8ee..4908ec5e02 100644 --- a/src/mainboard/lenovo/t410/romstage.c +++ b/src/mainboard/lenovo/t410/romstage.c @@ -71,5 +71,5 @@ void mainboard_pre_raminit(void) void mainboard_get_spd_map(u8 *spd_addrmap) { spd_addrmap[0] = 0x50; - spd_addrmap[2] = 0x52; + spd_addrmap[2] = 0x51; } From eb2e0b56ee4646655c485bf8c71587fd362194f7 Mon Sep 17 00:00:00 2001 From: Arthur Heymans Date: Wed, 20 Nov 2019 23:52:21 +0100 Subject: [PATCH 0333/1242] device/hypertransport: Drop unused code MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Change-Id: I6a8b176fa6f8832f6f7bb37118861d530fdefd5e Signed-off-by: Arthur Heymans Reviewed-on: https://review.coreboot.org/c/coreboot/+/37066 Reviewed-by: Kyösti Mälkki Tested-by: build bot (Jenkins) --- src/device/hypertransport.c | 43 +---------------------------- src/include/device/hypertransport.h | 10 ------- 2 files changed, 1 insertion(+), 52 deletions(-) diff --git a/src/device/hypertransport.c b/src/device/hypertransport.c index 03e3375b91..afa94fbe78 100644 --- a/src/device/hypertransport.c +++ b/src/device/hypertransport.c @@ -466,30 +466,6 @@ end_of_chain: return next_unitid; } -unsigned int hypertransport_scan_chain(struct bus *bus) -{ - int i; - unsigned int max_devfn; - u32 ht_unitid_base[4]; - - for (i = 0; i < 4; i++) - ht_unitid_base[i] = 0x20; - - if (bus->secondary == 0) - max_devfn = (CONFIG_CDB << 3) - 1; - else - max_devfn = (0x20 << 3) - 1; - - unsigned int next_unitid = do_hypertransport_scan_chain(bus, 0, max_devfn, - ht_unitid_base, offset_unit_id(bus->secondary == 0)); - - bus->hcdn_reg = 0; - for (i = 0; i < 4; i++) - bus->hcdn_reg |= (ht_unitid_base[i] & 0xff) << (i*8); - - return next_unitid; -} - /** * Scan a PCI bridge and the buses behind the bridge. * @@ -515,28 +491,11 @@ static void hypertransport_scan_chain_x(struct bus *bus, pci_scan_bus(bus, 0x00, ((next_unitid - 1) << 3) | 7); } -void ht_scan_bridge(struct device *dev) +static void ht_scan_bridge(struct device *dev) { do_pci_scan_bridge(dev, hypertransport_scan_chain_x); } -bool ht_is_non_coherent_link(struct bus *link) -{ - u32 link_type; - do { - link_type = pci_read_config32(link->dev, link->cap + 0x18); - } while (link_type & ConnectionPending); - - if (!(link_type & LinkConnected)) - return false; - - do { - link_type = pci_read_config32(link->dev, link->cap + 0x18); - } while (!(link_type & InitComplete)); - - return !!(link_type & NonCoherent); -} - /** Default device operations for hypertransport bridges */ static struct pci_operations ht_bus_ops_pci = { .set_subsystem = 0, diff --git a/src/include/device/hypertransport.h b/src/include/device/hypertransport.h index bc8ccd48a4..382731fe86 100644 --- a/src/include/device/hypertransport.h +++ b/src/include/device/hypertransport.h @@ -3,16 +3,6 @@ #include -/* TODO: Check HT specs for better names for these. */ -#define LinkConnected (1 << 0) -#define InitComplete (1 << 1) -#define NonCoherent (1 << 2) -#define ConnectionPending (1 << 4) -bool ht_is_non_coherent_link(struct bus *link); - -unsigned int hypertransport_scan_chain(struct bus *bus); -void ht_scan_bridge(struct device *dev); - extern struct device_operations default_ht_ops_bus; #define HT_IO_HOST_ALIGN 4096 From 06f2fcc0ffc1a903f304d8a3382f3a57163989a1 Mon Sep 17 00:00:00 2001 From: Jacob Garber Date: Mon, 4 Nov 2019 09:35:15 -0700 Subject: [PATCH 0334/1242] cpu/x86/smm: Use PRIxPTR to print uintptr_t Since 'base' is a uintptr_t, it needs the PRIxPTR format specifier. This fixes a compilation error when targeting x86_64 or using Clang 9.0.0. Change-Id: Ib806e2b3cbb255ef208b361744ac4547b8ba262f Signed-off-by: Jacob Garber Reviewed-on: https://review.coreboot.org/c/coreboot/+/36785 Tested-by: build bot (Jenkins) Reviewed-by: HAOUAS Elyes --- src/cpu/x86/smm/tseg_region.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/src/cpu/x86/smm/tseg_region.c b/src/cpu/x86/smm/tseg_region.c index a8b8bb7b9a..5b5c5729d5 100644 --- a/src/cpu/x86/smm/tseg_region.c +++ b/src/cpu/x86/smm/tseg_region.c @@ -17,6 +17,7 @@ #include #include #include +#include /* * Subregions within SMM @@ -88,11 +89,11 @@ void smm_list_regions(void) return; printk(BIOS_DEBUG, "SMM Memory Map\n"); - printk(BIOS_DEBUG, "SMRAM : 0x%zx 0x%zx\n", base, size); + printk(BIOS_DEBUG, "SMRAM : 0x%" PRIxPTR " 0x%zx\n", base, size); for (i = 0; i < SMM_SUBREGION_NUM; i++) { if (smm_subregion(i, &base, &size)) continue; - printk(BIOS_DEBUG, " Subregion %d: 0x%zx 0x%zx\n", i, base, size); + printk(BIOS_DEBUG, " Subregion %d: 0x%" PRIxPTR " 0x%zx\n", i, base, size); } } From 7aeeb9bf96c947954e19d0a5e865e5b71e5d98d4 Mon Sep 17 00:00:00 2001 From: Nick Vaccaro Date: Sat, 16 Nov 2019 23:59:07 -0800 Subject: [PATCH 0335/1242] soc/intel/common/intelblocks: Define PAD_CFG0_MODE_NF7 BUG=b:142961277 BRANCH=none TEST=none Change-Id: Ibe0991b2e0d13e07d65906201597f9021cfc7156 Signed-off-by: Nick Vaccaro Reviewed-on: https://review.coreboot.org/c/coreboot/+/36907 Tested-by: build bot (Jenkins) Reviewed-by: Wonkyu Kim Reviewed-by: Subrata Banik --- src/soc/intel/common/block/include/intelblocks/gpio_defs.h | 1 + 1 file changed, 1 insertion(+) diff --git a/src/soc/intel/common/block/include/intelblocks/gpio_defs.h b/src/soc/intel/common/block/include/intelblocks/gpio_defs.h index 15df187d5b..f460bcd109 100644 --- a/src/soc/intel/common/block/include/intelblocks/gpio_defs.h +++ b/src/soc/intel/common/block/include/intelblocks/gpio_defs.h @@ -32,6 +32,7 @@ #define PAD_CFG0_MODE_NF4 (4 << 10) #define PAD_CFG0_MODE_NF5 (5 << 10) #define PAD_CFG0_MODE_NF6 (6 << 10) +#define PAD_CFG0_MODE_NF7 (7 << 10) #define PAD_CFG0_ROUTE_MASK (0xF << 17) #define PAD_CFG0_ROUTE_NMI (1 << 17) #define PAD_CFG0_ROUTE_SMI (1 << 18) From 53509cf15aeba1a7afa262ca4d3ddb77f019ba00 Mon Sep 17 00:00:00 2001 From: Johnny Lin Date: Thu, 14 Nov 2019 14:55:04 +0800 Subject: [PATCH 0336/1242] drivers/ipmi: Add IPMI get system GUID support Tested on OCP Mono Lake. Change-Id: I541a23341ccce3d45239babb3f0a8a8c8542b226 Signed-off-by: Johnny Lin Reviewed-on: https://review.coreboot.org/c/coreboot/+/36842 Tested-by: build bot (Jenkins) Reviewed-by: David Hendricks --- src/drivers/ipmi/ipmi_ops.c | 26 ++++++++++++++++++++++++++ src/drivers/ipmi/ipmi_ops.h | 8 ++++++++ 2 files changed, 34 insertions(+) diff --git a/src/drivers/ipmi/ipmi_ops.c b/src/drivers/ipmi/ipmi_ops.c index 784daeb1fb..8a189bdbe1 100644 --- a/src/drivers/ipmi/ipmi_ops.c +++ b/src/drivers/ipmi/ipmi_ops.c @@ -16,6 +16,7 @@ #include #include "ipmi_ops.h" +#include enum cb_err ipmi_init_and_start_bmc_wdt(const int port, uint16_t countdown, uint8_t action) @@ -104,3 +105,28 @@ enum cb_err ipmi_stop_bmc_wdt(const int port) return CB_SUCCESS; } + +enum cb_err ipmi_get_system_guid(const int port, uint8_t *uuid) +{ + int ret; + struct ipmi_get_system_guid_rsp rsp; + + if (uuid == NULL) { + printk(BIOS_ERR, "%s failed, null pointer parameter\n", + __func__); + return CB_ERR; + } + + ret = ipmi_kcs_message(port, IPMI_NETFN_APPLICATION, 0x0, + IPMI_BMC_GET_SYSTEM_GUID, NULL, 0, + (unsigned char *) &rsp, sizeof(rsp)); + + if (ret < sizeof(struct ipmi_rsp) || rsp.resp.completion_code) { + printk(BIOS_ERR, "IPMI: %s command failed (ret=%d resp=0x%x)\n", + __func__, ret, rsp.resp.completion_code); + return CB_ERR; + } + + memcpy(uuid, rsp.data, 16); + return CB_SUCCESS; +} diff --git a/src/drivers/ipmi/ipmi_ops.h b/src/drivers/ipmi/ipmi_ops.h index f293075e90..77fc727cc8 100644 --- a/src/drivers/ipmi/ipmi_ops.h +++ b/src/drivers/ipmi/ipmi_ops.h @@ -21,6 +21,7 @@ #define IPMI_BMC_RESET_WDG_TIMER 0x22 #define IPMI_BMC_SET_WDG_TIMER 0x24 #define IPMI_BMC_GET_WDG_TIMER 0x25 +#define IPMI_BMC_GET_SYSTEM_GUID 0x37 /* BMC watchdog timeout action */ enum ipmi_bmc_timeout_action_type { @@ -44,6 +45,10 @@ struct ipmi_wdt_rsp { uint16_t present_countdown_val; } __packed; +struct ipmi_get_system_guid_rsp { + struct ipmi_rsp resp; + uint8_t data[16]; +} __packed; /* * Initialize and start BMC FRB2 watchdog timer with the * provided timer countdown and action values. @@ -54,4 +59,7 @@ enum cb_err ipmi_init_and_start_bmc_wdt(const int port, uint16_t countdown, /* Returns CB_SUCCESS on success and CB_ERR if an error occurred */ enum cb_err ipmi_stop_bmc_wdt(const int port); +/* IPMI get BMC system GUID and store it to parameter uuid. + * Returns CB_SUCCESS on success and CB_ERR if an error occurred */ +enum cb_err ipmi_get_system_guid(const int port, uint8_t *uuid); #endif From 94146009a190383a581618fd969bf2276fb73585 Mon Sep 17 00:00:00 2001 From: Subrata Banik Date: Thu, 14 Nov 2019 11:30:43 +0530 Subject: [PATCH 0337/1242] soc/intel/icelake: Make CpuMpPpi implementation default for ICL TEST=Could able to build and boot ICL DE system Change-Id: Icd71ec99f06434896c73cff5a52cd3a5ad6ce5f3 Signed-off-by: Subrata Banik Reviewed-on: https://review.coreboot.org/c/coreboot/+/36839 Tested-by: build bot (Jenkins) Reviewed-by: Arthur Heymans --- src/soc/intel/icelake/Kconfig | 1 + src/soc/intel/icelake/fsp_params.c | 10 ++++------ 2 files changed, 5 insertions(+), 6 deletions(-) diff --git a/src/soc/intel/icelake/Kconfig b/src/soc/intel/icelake/Kconfig index cb9de149d3..a2fe5ed3da 100644 --- a/src/soc/intel/icelake/Kconfig +++ b/src/soc/intel/icelake/Kconfig @@ -60,6 +60,7 @@ config CPU_SPECIFIC_OPTIONS select UDK_2017_BINDING select DISPLAY_FSP_VERSION_INFO select HECI_DISABLE_USING_SMM + select USE_INTEL_FSP_TO_CALL_COREBOOT_PUBLISH_MP_PPI config DCACHE_RAM_BASE default 0xfef00000 diff --git a/src/soc/intel/icelake/fsp_params.c b/src/soc/intel/icelake/fsp_params.c index 62c69da2f2..448b82c7d8 100644 --- a/src/soc/intel/icelake/fsp_params.c +++ b/src/soc/intel/icelake/fsp_params.c @@ -84,12 +84,10 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd) for (i = 0; i < ARRAY_SIZE(params->Usb3OverCurrentPin); i++) params->Usb3OverCurrentPin[i] = 0; - if (CONFIG(USE_INTEL_FSP_TO_CALL_COREBOOT_PUBLISH_MP_PPI)) { - params->CpuMpPpi = (uintptr_t) mp_fill_ppi_services_data(); - params->SkipMpInit = 0; - } else { - params->SkipMpInit = !CONFIG_USE_INTEL_FSP_MP_INIT; - } + /* Mandatory to make use of CpuMpPpi implementation from ICL onwards */ + params->CpuMpPpi = (uintptr_t) mp_fill_ppi_services_data(); + /* TODO: Remove me as SkipMpInit is getting deprecated */ + params->SkipMpInit = 0; mainboard_silicon_init_params(params); From 7f8b0cd89c10621f456e3eebcd290d3946122d6d Mon Sep 17 00:00:00 2001 From: Felix Singer Date: Sun, 10 Nov 2019 11:04:08 +0100 Subject: [PATCH 0338/1242] sb/i82801ix: Use macros instead of hard-coded IDs This patch replaces hard-coded PCI IDs with macros from pci_ids.h and cleans up some code. Change-Id: Ie6ea72ac49eb015ef5cbaa98ed2b3400072000b5 Signed-off-by: Felix Singer Reviewed-on: https://review.coreboot.org/c/coreboot/+/36705 Reviewed-by: Arthur Heymans Reviewed-by: HAOUAS Elyes Tested-by: build bot (Jenkins) --- src/include/device/pci_ids.h | 14 +++++++++----- src/southbridge/intel/i82801ix/early_smbus.c | 4 ++-- src/southbridge/intel/i82801ix/hdaudio.c | 2 +- src/southbridge/intel/i82801ix/lpc.c | 12 ++++++------ src/southbridge/intel/i82801ix/pcie.c | 12 ++++++------ src/southbridge/intel/i82801ix/sata.c | 11 ++++++++--- src/southbridge/intel/i82801ix/smbus.c | 4 +--- src/southbridge/intel/i82801ix/thermal.c | 2 +- src/southbridge/intel/i82801ix/usb_ehci.c | 4 ++-- 9 files changed, 36 insertions(+), 29 deletions(-) diff --git a/src/include/device/pci_ids.h b/src/include/device/pci_ids.h index 18d6f601c1..c05640fe9c 100644 --- a/src/include/device/pci_ids.h +++ b/src/include/device/pci_ids.h @@ -2546,13 +2546,15 @@ #define PCI_DEVICE_ID_INTEL_82801HEM_LPC 0x2811 /* Intel 82801IB (ICH9) */ -#define PCI_DEVICE_ID_INTEL_82801IB_LPC 0x2918 +#define PCI_DEVICE_ID_INTEL_82801IB_LPC 0x2918 /* ICH9 */ #define PCI_DEVICE_ID_INTEL_82801IB_SATA_P0123 0x2920 /* Ports 0 - 3 */ #define PCI_DEVICE_ID_INTEL_82801IB_SATA_P01 0x2921 /* Ports 0 - 1 */ #define PCI_DEVICE_ID_INTEL_82801IB_SATA_AHCI1 0x2922 /* Ports 0 - 5 */ #define PCI_DEVICE_ID_INTEL_82801IB_SATA_AHCI2 0x2923 /* Ports 0, 1, 4, 5 */ #define PCI_DEVICE_ID_INTEL_82801IB_SATA_RAID 0x2822 /* RAID */ #define PCI_DEVICE_ID_INTEL_82801IB_SATA_P45 0x2926 /* Ports 4 - 5 */ +#define PCI_DEVICE_ID_INTEL_82801IBM_IEM_SATA_IDE_P01 0x2928 /* Ports 0 - 1 */ +#define PCI_DEVICE_ID_INTEL_82801IBM_IEM_SATA_AHCI_P0145 0x2929 /* Ports 0, 1, 4, 5 */ #define PCI_DEVICE_ID_INTEL_82801IB_SMB 0x2930 #define PCI_DEVICE_ID_INTEL_82801IB_THERMAL 0x2932 #define PCI_DEVICE_ID_INTEL_82801IB_PCI 0x244e /* DMI to PCI bridge */ @@ -2573,10 +2575,12 @@ #define PCI_DEVICE_ID_INTEL_82801IB_PCIE6 0x294a #define PCI_DEVICE_ID_INTEL_82801IB_LAN 0x29c4 -/* Intel 82801IR/IH/IO (ICH9R/ICH9DH/ICH9DO), only difference to ICH9: LPC */ -#define PCI_DEVICE_ID_INTEL_82801IR_LPC 0x2916 -#define PCI_DEVICE_ID_INTEL_82801IO_LPC 0x2914 -#define PCI_DEVICE_ID_INTEL_82801IH_LPC 0x2912 +/* Only difference to ICH9: LPC */ +#define PCI_DEVICE_ID_INTEL_82801IH_LPC 0x2912 /* ICH9DH */ +#define PCI_DEVICE_ID_INTEL_82801IO_LPC 0x2914 /* ICH9DO */ +#define PCI_DEVICE_ID_INTEL_82801IR_LPC 0x2916 /* ICH9R */ +#define PCI_DEVICE_ID_INTEL_82801IEM_LPC 0x2917 /* ICH9M-E */ +#define PCI_DEVICE_ID_INTEL_82801IBM_LPC 0x2919 /* ICH9M */ #define PCI_DEVICE_ID_INTEL_CAVECREEK_LPC 0x2310 #define PCI_DEVICE_ID_INTEL_COUGARPOINT_LPC_MIN 0x1c41 diff --git a/src/southbridge/intel/i82801ix/early_smbus.c b/src/southbridge/intel/i82801ix/early_smbus.c index 54ad3c369b..e686d48127 100644 --- a/src/southbridge/intel/i82801ix/early_smbus.c +++ b/src/southbridge/intel/i82801ix/early_smbus.c @@ -19,6 +19,7 @@ #include #include #include +#include #include #include "i82801ix.h" @@ -30,9 +31,8 @@ void enable_smbus(void) dev = PCI_DEV(0x0, 0x1f, 0x3); /* Check to make sure we've got the right device. */ - if (pci_read_config16(dev, 0x2) != 0x2930) { + if (pci_read_config16(dev, 0x2) != PCI_DEVICE_ID_INTEL_82801IB_SMB) die("SMBus controller not found!"); - } /* Set SMBus I/O base. */ pci_write_config32(dev, SMB_BASE, diff --git a/src/southbridge/intel/i82801ix/hdaudio.c b/src/southbridge/intel/i82801ix/hdaudio.c index f105a735f8..5099f167b9 100644 --- a/src/southbridge/intel/i82801ix/hdaudio.c +++ b/src/southbridge/intel/i82801ix/hdaudio.c @@ -305,5 +305,5 @@ static struct device_operations azalia_ops = { static const struct pci_driver i82801ix_azalia __pci_driver = { .ops = &azalia_ops, .vendor = PCI_VENDOR_ID_INTEL, - .device = 0x293e, + .device = PCI_DEVICE_ID_INTEL_82801IB_HD_AUDIO, }; diff --git a/src/southbridge/intel/i82801ix/lpc.c b/src/southbridge/intel/i82801ix/lpc.c index 811b4b2820..d5417307e7 100644 --- a/src/southbridge/intel/i82801ix/lpc.c +++ b/src/southbridge/intel/i82801ix/lpc.c @@ -541,12 +541,12 @@ static struct device_operations device_ops = { }; static const unsigned short pci_device_ids[] = { - 0x2912, /* ICH9DH */ - 0x2914, /* ICH9DO */ - 0x2916, /* ICH9R */ - 0x2918, /* ICH9 */ - 0x2917, /* ICH9M-E */ - 0x2919, /* ICH9M */ + PCI_DEVICE_ID_INTEL_82801IH_LPC, /* ICH9DH */ + PCI_DEVICE_ID_INTEL_82801IO_LPC, /* ICH9DO */ + PCI_DEVICE_ID_INTEL_82801IR_LPC, /* ICH9R */ + PCI_DEVICE_ID_INTEL_82801IEM_LPC, /* ICH9M-E */ + PCI_DEVICE_ID_INTEL_82801IB_LPC, /* ICH9 */ + PCI_DEVICE_ID_INTEL_82801IBM_LPC, /* ICH9M */ 0 }; diff --git a/src/southbridge/intel/i82801ix/pcie.c b/src/southbridge/intel/i82801ix/pcie.c index b1d0ecc214..bdfc84db43 100644 --- a/src/southbridge/intel/i82801ix/pcie.c +++ b/src/southbridge/intel/i82801ix/pcie.c @@ -123,12 +123,12 @@ static struct device_operations device_ops = { /* 82801Ix (ICH9DH/ICH9DO/ICH9R/ICH9/ICH9M-E/ICH9M) */ static const unsigned short pci_device_ids[] = { - 0x2940, /* Port 1 */ - 0x2942, /* Port 2 */ - 0x2944, /* Port 3 */ - 0x2946, /* Port 4 */ - 0x2948, /* Port 5 */ - 0x294a, /* Port 6 */ + PCI_DEVICE_ID_INTEL_82801IB_PCIE1, /* Port 1 */ + PCI_DEVICE_ID_INTEL_82801IB_PCIE2, /* Port 2 */ + PCI_DEVICE_ID_INTEL_82801IB_PCIE3, /* Port 3 */ + PCI_DEVICE_ID_INTEL_82801IB_PCIE4, /* Port 4 */ + PCI_DEVICE_ID_INTEL_82801IB_PCIE5, /* Port 5 */ + PCI_DEVICE_ID_INTEL_82801IB_PCIE6, /* Port 6 */ 0 }; static const struct pci_driver ich9_pcie __pci_driver = { diff --git a/src/southbridge/intel/i82801ix/sata.c b/src/southbridge/intel/i82801ix/sata.c index fa6c1df6b3..fcf4045baf 100644 --- a/src/southbridge/intel/i82801ix/sata.c +++ b/src/southbridge/intel/i82801ix/sata.c @@ -155,7 +155,8 @@ static void sata_init(struct device *const dev) const config_t *const config = dev->chip_info; const u16 devid = pci_read_config16(dev, PCI_DEVICE_ID); - const int is_mobile = (devid == 0x2928) || (devid == 0x2929); + const int is_mobile = (devid == PCI_DEVICE_ID_INTEL_82801IBM_IEM_SATA_IDE_P01) || + (devid == PCI_DEVICE_ID_INTEL_82801IBM_IEM_SATA_AHCI_P0145); u8 sata_mode; printk(BIOS_DEBUG, "i82801ix_sata: initializing...\n"); @@ -276,8 +277,12 @@ static struct device_operations sata_ops = { }; static const unsigned short pci_device_ids[] = { - 0x2920, 0x2921, 0x2922, 0x2923, - 0x2928, 0x2929, + PCI_DEVICE_ID_INTEL_82801IB_SATA_P0123, + PCI_DEVICE_ID_INTEL_82801IB_SATA_P01, + PCI_DEVICE_ID_INTEL_82801IB_SATA_AHCI1, + PCI_DEVICE_ID_INTEL_82801IB_SATA_AHCI2, + PCI_DEVICE_ID_INTEL_82801IBM_IEM_SATA_IDE_P01, + PCI_DEVICE_ID_INTEL_82801IBM_IEM_SATA_AHCI_P0145, 0, }; diff --git a/src/southbridge/intel/i82801ix/smbus.c b/src/southbridge/intel/i82801ix/smbus.c index 9bab9b25de..b8e9cfd695 100644 --- a/src/southbridge/intel/i82801ix/smbus.c +++ b/src/southbridge/intel/i82801ix/smbus.c @@ -91,10 +91,8 @@ static struct device_operations smbus_ops = { .ops_pci = &smbus_pci_ops, }; -static const unsigned short pci_device_ids[] = { 0x2930, 0 }; - static const struct pci_driver pch_smbus __pci_driver = { .ops = &smbus_ops, .vendor = PCI_VENDOR_ID_INTEL, - .devices = pci_device_ids, + .device = PCI_DEVICE_ID_INTEL_82801IB_SMB, }; diff --git a/src/southbridge/intel/i82801ix/thermal.c b/src/southbridge/intel/i82801ix/thermal.c index 2deb84d4b2..8946b020d8 100644 --- a/src/southbridge/intel/i82801ix/thermal.c +++ b/src/southbridge/intel/i82801ix/thermal.c @@ -67,5 +67,5 @@ static struct device_operations device_ops = { static const struct pci_driver ich9_thermal __pci_driver = { .ops = &device_ops, .vendor = PCI_VENDOR_ID_INTEL, - .device = 0x2932, + .device = PCI_DEVICE_ID_INTEL_82801IB_THERMAL, }; diff --git a/src/southbridge/intel/i82801ix/usb_ehci.c b/src/southbridge/intel/i82801ix/usb_ehci.c index 47254f94b9..4c875ad035 100644 --- a/src/southbridge/intel/i82801ix/usb_ehci.c +++ b/src/southbridge/intel/i82801ix/usb_ehci.c @@ -51,8 +51,8 @@ static void usb_ehci_set_subsystem(struct device *dev, unsigned int vendor, } static const unsigned short pci_device_ids[] = { - 0x293a, - 0x293c, + PCI_DEVICE_ID_INTEL_82801IB_EHCI1, + PCI_DEVICE_ID_INTEL_82801IB_EHCI2, 0 }; From 1818733faa9af615bc1d9024dee10865aaf22da0 Mon Sep 17 00:00:00 2001 From: Arthur Heymans Date: Thu, 7 Nov 2019 08:18:14 +0100 Subject: [PATCH 0339/1242] cpu/intel/smm: Drop em64t save state MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This save state is just plainly wrong in many regards and em64t100 should be used. Checked with a model 0x17 core2 CPU. Change-Id: I4d89691e87c91dd12b34a44b74849b18b4ac5369 Signed-off-by: Arthur Heymans Reviewed-on: https://review.coreboot.org/c/coreboot/+/36660 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki Reviewed-by: Angel Pons --- src/cpu/x86/smm/smihandler.c | 11 +-- src/include/cpu/intel/em64t100_save_state.h | 6 +- src/include/cpu/intel/em64t_save_state.h | 101 -------------------- 3 files changed, 7 insertions(+), 111 deletions(-) delete mode 100644 src/include/cpu/intel/em64t_save_state.h diff --git a/src/cpu/x86/smm/smihandler.c b/src/cpu/x86/smm/smihandler.c index 68b7859a04..20417d127e 100644 --- a/src/cpu/x86/smm/smihandler.c +++ b/src/cpu/x86/smm/smihandler.c @@ -18,7 +18,6 @@ #include #include #include -#include #include #include #include @@ -29,7 +28,7 @@ typedef enum { AMD64, - EM64T, + EM64T100, EM64T101, LEGACY } save_state_type_t; @@ -38,7 +37,7 @@ typedef struct { save_state_type_t type; union { amd64_smm_state_save_area_t *amd64_state_save; - em64t_smm_state_save_area_t *em64t_state_save; + em64t100_smm_state_save_area_t *em64t100_state_save; em64t101_smm_state_save_area_t *em64t101_state_save; legacy_smm_state_save_area_t *legacy_state_save; }; @@ -178,10 +177,10 @@ void smi_handler(u32 smm_revision) SMM_LEGACY_ARCH_OFFSET, node); break; case 0x00030100: - state_save.type = EM64T; - state_save.em64t_state_save = + state_save.type = EM64T100; + state_save.em64t100_state_save = smm_save_state(smm_base, - SMM_EM64T_ARCH_OFFSET, node); + SMM_EM64T100_ARCH_OFFSET, node); break; case 0x00030101: /* SandyBridge, IvyBridge, and Haswell */ state_save.type = EM64T101; diff --git a/src/include/cpu/intel/em64t100_save_state.h b/src/include/cpu/intel/em64t100_save_state.h index f76fa4badd..6e8e1d9745 100644 --- a/src/include/cpu/intel/em64t100_save_state.h +++ b/src/include/cpu/intel/em64t100_save_state.h @@ -17,10 +17,8 @@ #include #include -/* Intel Revision 30100 SMM State-Save Area - * The following processor architectures use this: - * - Bay Trail - */ +/* Intel Revision 30100 SMM State-Save Area */ + #define SMM_EM64T100_ARCH_OFFSET 0x7c00 #define SMM_EM64T100_SAVE_STATE_OFFSET \ SMM_SAVE_STATE_BEGIN(SMM_EM64T100_ARCH_OFFSET) diff --git a/src/include/cpu/intel/em64t_save_state.h b/src/include/cpu/intel/em64t_save_state.h deleted file mode 100644 index 1dd01a61a4..0000000000 --- a/src/include/cpu/intel/em64t_save_state.h +++ /dev/null @@ -1,101 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef __EM64T_SAVE_STATE_H__ -#define __EM64T_SAVE_STATE_H__ - -#include -#include - -/* Intel Core 2 (EM64T) SMM State-Save Area - * starts @ 0x7c00 - */ -#define SMM_EM64T_ARCH_OFFSET 0x7c00 -#define SMM_EM64T_SAVE_STATE_OFFSET \ - SMM_SAVE_STATE_BEGIN(SMM_EM64T_ARCH_OFFSET) -typedef struct { - u8 reserved0[256]; - u8 reserved1[208]; - - u32 gdtr_upper_base; - u32 ldtr_upper_base; - u32 idtr_upper_base; - - u8 reserved2[4]; - - u64 io_rdi; - u64 io_rip; - u64 io_rcx; - u64 io_rsi; - u64 cr4; - - u8 reserved3[68]; - - u64 gdtr_base; - u64 idtr_base; - u64 ldtr_base; - - u8 reserved4[84]; - - u32 smm_revision; - u32 smbase; - - u16 io_restart; - u16 autohalt_restart; - - u8 reserved5[24]; - - u64 r15; - u64 r14; - u64 r13; - u64 r12; - u64 r11; - u64 r10; - u64 r9; - u64 r8; - - u64 rax; - u64 rcx; - u64 rdx; - u64 rbx; - - u64 rsp; - u64 rbp; - u64 rsi; - u64 rdi; - - - u64 io_mem_addr; - u32 io_misc_info; - - u32 es_sel; - u32 cs_sel; - u32 ss_sel; - u32 ds_sel; - u32 fs_sel; - u32 gs_sel; - - u32 ldtr_sel; - u32 tr_sel; - - u64 dr7; - u64 dr6; - u64 rip; - u64 efer; - u64 rflags; - - u64 cr3; - u64 cr0; -} __packed em64t_smm_state_save_area_t; - -#endif From 4debbe74acdeb2934c9a93da70ab34a3f5169837 Mon Sep 17 00:00:00 2001 From: Arthur Heymans Date: Thu, 7 Nov 2019 08:22:35 +0100 Subject: [PATCH 0340/1242] cpu/intel/gen1/smmrelocate: Fix stale comment MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Change-Id: I91ed5f7cbcfa5c510bb8e74049ec860397d7dbba Signed-off-by: Arthur Heymans Reviewed-on: https://review.coreboot.org/c/coreboot/+/36659 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki Reviewed-by: Angel Pons Reviewed-by: Patrick Rudolph --- src/cpu/intel/smm/gen1/smmrelocate.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/src/cpu/intel/smm/gen1/smmrelocate.c b/src/cpu/intel/smm/gen1/smmrelocate.c index c177e9b952..834ec0412e 100644 --- a/src/cpu/intel/smm/gen1/smmrelocate.c +++ b/src/cpu/intel/smm/gen1/smmrelocate.c @@ -11,8 +11,7 @@ * GNU General Public License for more details. */ -/* SMM relocation with intention to work for i945-ivybridge. - Right now used for sandybridge and ivybridge. */ +/* SMM relocation for i945-ivybridge. */ #include #include From d5e7a6d9c506be28308c3df6527eab2edca219bc Mon Sep 17 00:00:00 2001 From: Arthur Heymans Date: Wed, 20 Nov 2019 12:17:18 +0100 Subject: [PATCH 0341/1242] sb/intel/ibexpeak: Decode more LPC IO ranges 3b452e0 "nb/intel/nehalem: Move PCH init to sb/intel/ibexpeak" introduced a regression where the GAME_L decode range was not set up, which is used by the WACOM digitizer on the Thinkpad X201T. Change-Id: Ie569d567a65010aa5372323f8610a1b8b5d2599d Signed-off-by: Arthur Heymans Reviewed-on: https://review.coreboot.org/c/coreboot/+/36994 Reviewed-by: Nico Huber Tested-by: build bot (Jenkins) --- src/southbridge/intel/ibexpeak/bootblock.c | 24 ++++++++++++++-------- 1 file changed, 15 insertions(+), 9 deletions(-) diff --git a/src/southbridge/intel/ibexpeak/bootblock.c b/src/southbridge/intel/ibexpeak/bootblock.c index 599e182a59..c8b1d6ef31 100644 --- a/src/southbridge/intel/ibexpeak/bootblock.c +++ b/src/southbridge/intel/ibexpeak/bootblock.c @@ -62,15 +62,21 @@ static void early_lpc_init(void) const struct device *dev = pcidev_on_root(0x1f, 0); const struct southbridge_intel_ibexpeak_config *config = NULL; - /* Add some default decode ranges: - - 0x2e/2f, 0x4e/0x4f - - EC/Mouse/KBC 60/64, 62/66 - - 0x3f8 COMA - If more are needed, update in mainboard_lpc_init hook - */ - pci_write_config16(PCH_LPC_DEV, LPC_EN, - CNF2_LPC_EN | CNF1_LPC_EN | MC_LPC_EN | KBC_LPC_EN | - COMA_LPC_EN); + /* + * Enable some common LPC IO ranges: + * - 0x2e/0x2f, 0x4e/0x4f often SuperIO + * - 0x60/0x64, 0x62/0x66 often KBC/EC + * - 0x3f0-0x3f5/0x3f7 FDD + * - 0x378-0x37f and 0x778-0x77f LPT + * - 0x2f8-0x2ff COMB + * - 0x3f8-0x3ff COMA + * - 0x208-0x20f GAMEH + * - 0x200-0x207 GAMEL + */ + pci_write_config16(PCH_LPC_DEV, LPC_EN, CNF2_LPC_EN | CNF1_LPC_EN + | MC_LPC_EN | KBC_LPC_EN | GAMEH_LPC_EN + | GAMEL_LPC_EN | FDD_LPC_EN | LPT_LPC_EN + | COMB_LPC_EN | COMA_LPC_EN); pci_write_config16(PCH_LPC_DEV, LPC_IO_DEC, 0x10); /* Clear PWR_FLR */ From 540b2adb6165a5a86bc575065445df63cf1516cf Mon Sep 17 00:00:00 2001 From: Patrick Georgi Date: Thu, 21 Nov 2019 19:06:12 +0100 Subject: [PATCH 0342/1242] src/console: Bring back support for printf'ing 64bit ints commit f96d9051c2 (Remove MIPS Architecture) accidentally enabled a MIPS special case to not support 64bit integers in printf for all platforms. This removes that MIPS-only special case entirely. Change-Id: I5245bb32b45f9bd37bd012a7b15a64fba24a4cb7 Signed-off-by: Patrick Georgi Reviewed-on: https://review.coreboot.org/c/coreboot/+/37113 Tested-by: build bot (Jenkins) Reviewed-by: Jacob Garber Reviewed-by: Julius Werner Reviewed-by: Angel Pons --- src/console/vtxprintf.c | 12 ------------ 1 file changed, 12 deletions(-) diff --git a/src/console/vtxprintf.c b/src/console/vtxprintf.c index b9e43692d8..104f4eaeb3 100644 --- a/src/console/vtxprintf.c +++ b/src/console/vtxprintf.c @@ -36,20 +36,8 @@ static int number(void (*tx_byte)(unsigned char byte, void *data), const char *digits = "0123456789abcdef"; int i; int count = 0; -#ifdef SUPPORT_64BIT_INTS unsigned long long num = inum; long long snum = num; -#else - unsigned long num = (unsigned long)inum; - long snum = (long)num; - - if (num != inum) { - /* Alert user to an incorrect result by printing #^!. */ - call_tx('#'); - call_tx('^'); - call_tx('!'); - } -#endif if (type & LARGE) digits = "0123456789ABCDEF"; From d198e2e5536079378652f638a6d148b3c8a6eb03 Mon Sep 17 00:00:00 2001 From: Patrick Georgi Date: Tue, 19 Nov 2019 17:09:30 +0100 Subject: [PATCH 0343/1242] util/release: Make signing with GPG 2 easier GPG 2 expects the GPG_TTY variable to be configured so that it can properly ask for the passphrase. If it's not already set, do so. Change-Id: I7e145a492c9eceda40cc1a1e04452a78852042d1 Signed-off-by: Patrick Georgi Reviewed-on: https://review.coreboot.org/c/coreboot/+/36953 Reviewed-by: Stefan Reinauer Tested-by: build bot (Jenkins) --- util/release/build-release | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/util/release/build-release b/util/release/build-release index 224be5b0b4..fd3f63cbc9 100755 --- a/util/release/build-release +++ b/util/release/build-release @@ -10,6 +10,10 @@ GPG_KEY_ID=$4 set -e +if [ -z "$GPG_TTY" ]; then + export GPG_TTY=$(tty) +fi + # set local + tz to be reproducible LC_ALL=C LANG=C From 54cabb977d2729d766e6751c61073ab1adb4c2f8 Mon Sep 17 00:00:00 2001 From: Patrick Georgi Date: Tue, 19 Nov 2019 17:11:04 +0100 Subject: [PATCH 0344/1242] util/release: Try reusing the local checkout for cloning git clone allows using a local repo as reference which reduces the required network traffic. Change-Id: I64722cd5dbdfc0c2bcd935715cffdb99b773711c Signed-off-by: Patrick Georgi Reviewed-on: https://review.coreboot.org/c/coreboot/+/36954 Reviewed-by: Stefan Reinauer Tested-by: build bot (Jenkins) --- util/release/build-release | 9 +++++++-- 1 file changed, 7 insertions(+), 2 deletions(-) diff --git a/util/release/build-release b/util/release/build-release index fd3f63cbc9..464388b198 100755 --- a/util/release/build-release +++ b/util/release/build-release @@ -39,10 +39,15 @@ if ! tar --sort=name -cf /dev/null /dev/null 2>/dev/null ; then fi if [ ! -d "coreboot-${VERSION_NAME}" ]; then + if [ -d .git ]; then + GIT_REF_OPTS="--reference . --dissociate" + elif [ -d ../../.git ]; then + GIT_REF_OPTS="--reference ../.. --dissociate" + fi if [ -n "${USERNAME}" ]; then - git clone "ssh://${USERNAME}@review.coreboot.org:29418/coreboot.git" "coreboot-${VERSION_NAME}" + git clone ${GIT_REF_OPTS} "ssh://${USERNAME}@review.coreboot.org:29418/coreboot.git" "coreboot-${VERSION_NAME}" else - git clone https://review.coreboot.org/coreboot.git "coreboot-${VERSION_NAME}" + git clone ${GIT_REF_OPTS} https://review.coreboot.org/coreboot.git "coreboot-${VERSION_NAME}" fi fi From 85678b8419b71eddf93aaa1579099a871ac80bbb Mon Sep 17 00:00:00 2001 From: Patrick Georgi Date: Tue, 19 Nov 2019 17:12:05 +0100 Subject: [PATCH 0345/1242] util/release: Refactor blobs list We had two _very_ long lines containing arguments that enumerate the paths where blobs are stored: Now there's a variable containing them. Change-Id: I501b27158d00ba00d1c9b9e2f00a17a8b9c3f682 Signed-off-by: Patrick Georgi Reviewed-on: https://review.coreboot.org/c/coreboot/+/36955 Reviewed-by: Stefan Reinauer Tested-by: build bot (Jenkins) --- util/release/build-release | 12 ++++++++++-- 1 file changed, 10 insertions(+), 2 deletions(-) diff --git a/util/release/build-release b/util/release/build-release index 464388b198..0d90d162e3 100755 --- a/util/release/build-release +++ b/util/release/build-release @@ -67,8 +67,16 @@ printf "%s-%s\n" "$VERSION_NAME" "$(git log --pretty=%H|head -1)" > .coreboot-v tstamp=$(git log --pretty=format:%ci -1) cd .. -tar --sort=name --mtime="$tstamp" --owner=coreboot:1000 --group=coreboot:1000 --exclude=*/.git --exclude=*/.gitignore --exclude="coreboot-${VERSION_NAME}/3rdparty/blobs" --exclude="coreboot-${VERSION_NAME}/3rdparty/fsp" --exclude="coreboot-${VERSION_NAME}/3rdparty/intel-microcode" -cvf - "coreboot-${VERSION_NAME}" |xz -9 > "coreboot-${VERSION_NAME}.tar.xz" -tar --sort=name --mtime="$tstamp" --owner=coreboot:1000 --group=coreboot:1000 --exclude=*/.git --exclude=*/.gitignore -cvf - "coreboot-${VERSION_NAME}/3rdparty/blobs" "coreboot-${VERSION_NAME}/3rdparty/fsp" "coreboot-${VERSION_NAME}/3rdparty/intel-microcode" |xz -9 > "coreboot-blobs-${VERSION_NAME}.tar.xz" +exclude_paths="3rdparty/blobs " +exclude_paths+="3rdparty/fsp " +exclude_paths+="3rdparty/intel-microcode " +for i in ${exclude_paths}; do + blobs_paths+="coreboot-${VERSION_NAME}/${i} " + exclude_opts+="--exclude=coreboot-${VERSION_NAME}/${i} " +done + +tar --sort=name --mtime="$tstamp" --owner=coreboot:1000 --group=coreboot:1000 --exclude=*/.git --exclude=*/.gitignore ${exclude_opts} -cvf - "coreboot-${VERSION_NAME}" |xz -9 > "coreboot-${VERSION_NAME}.tar.xz" +tar --sort=name --mtime="$tstamp" --owner=coreboot:1000 --group=coreboot:1000 --exclude=*/.git --exclude=*/.gitignore -cvf - ${blobs_paths} |xz -9 > "coreboot-blobs-${VERSION_NAME}.tar.xz" if [ -n "${GPG_KEY_ID}" ]; then gpg --armor --local-user "$GPG_KEY_ID" --output "coreboot-${VERSION_NAME}.tar.xz.sig" --detach-sig "coreboot-${VERSION_NAME}.tar.xz" From eb80e053b6bb5994df592dcb36d525b4174386cd Mon Sep 17 00:00:00 2001 From: Patrick Georgi Date: Tue, 19 Nov 2019 17:15:31 +0100 Subject: [PATCH 0346/1242] Documentation/releases: Update checklist Having the release notes mostly ready one week before the release allows for better review. Some statistics, the actual release date and commit ID can only be filled in on release day, but there's a tried & true technique for that: placeholders. It's also a nice touch to have the release notes of a release within its source tarballs, so push them right before creating the release (since changes in Documentation/releases won't break coreboot in any way). Change-Id: Iad7ba1ba4fc841bf437f2a997428b7f636e15422 Signed-off-by: Patrick Georgi Reviewed-on: https://review.coreboot.org/c/coreboot/+/36957 Reviewed-by: HAOUAS Elyes Reviewed-by: Stefan Reinauer Tested-by: build bot (Jenkins) --- Documentation/releases/checklist.md | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/Documentation/releases/checklist.md b/Documentation/releases/checklist.md index 2c55957ee8..ff931412f7 100644 --- a/Documentation/releases/checklist.md +++ b/Documentation/releases/checklist.md @@ -56,17 +56,18 @@ be more frequent than was needed, so we scaled it back to twice a year. and to update the release notes - [ ] Update the topic in the irc channel with the date of the upcoming release +- [ ] Finalize release notes (as much as possible), without specifying + release commit ids ### Day of release -- [ ] Update release notes, without specifying release commit ids - [ ] Select a commit ID to base the release upon, announce to IRC, ask for testing. - [ ] Test the commit selected for release +- [ ] Update release notes with actual commit id, push to repo - [ ] Run release script - [ ] Test the release from the actual release tarballs - [ ] Push signed Tag to repo - [ ] Announce that the release tag is done on IRC -- [ ] Update release notes with actual commit id, push to repo - [ ] Upload release files to web server - [ ] Upload crossgcc sources to web server - [ ] Update download page to point to files, push to repo From d653e491e133df1b9e066a3817396f739e2c5533 Mon Sep 17 00:00:00 2001 From: Patrick Georgi Date: Wed, 20 Nov 2019 16:49:41 +0100 Subject: [PATCH 0347/1242] util/release: always remove temporary files Change-Id: I8e6ff5bc72618e782ed472878bd6ea294be1b5ca Signed-off-by: Patrick Georgi Reviewed-on: https://review.coreboot.org/c/coreboot/+/37021 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer --- util/release/genrelnotes | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/util/release/genrelnotes b/util/release/genrelnotes index 25c2993658..d48a8e950d 100755 --- a/util/release/genrelnotes +++ b/util/release/genrelnotes @@ -427,8 +427,8 @@ NEW_AUTHORS=$(git log --pretty=%an "${OLD_GIT_VERSION}" 2>/dev/null | sort | \ git log --pretty=%an "${NEW_GIT_VERSION}" 2>/dev/null | \ sort | uniq > "$after_names" && \ grep -Fxv -c -f "$before_names" "$after_names") -NEW_AUTHOR_LIST=$( grep -Fxv -f "$before_names" "$after_names" && \ - rm "$before_names" "$after_names") +NEW_AUTHOR_LIST=$( grep -Fxv -f "$before_names" "$after_names") +rm -f "$before_names" "$after_names" { printf -- "- Total commits: %s\n" "$TOTAL_COMMITS" printf -- "- Total authors: %s\n" \ From 1916d68ee378c41bb60ebe0b67b2b69d6ba1166f Mon Sep 17 00:00:00 2001 From: Patrick Georgi Date: Wed, 20 Nov 2019 16:05:21 +0100 Subject: [PATCH 0348/1242] util/release: Convert board IDs into human readable names Change-Id: Ie323112d27d228849cca7894b9ebd3f4dedd2d9a Signed-off-by: Patrick Georgi Reviewed-on: https://review.coreboot.org/c/coreboot/+/37022 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer --- util/release/genrelnotes | 34 +++++++++++++++++++++++++++++++--- 1 file changed, 31 insertions(+), 3 deletions(-) diff --git a/util/release/genrelnotes b/util/release/genrelnotes index d48a8e950d..e3af48c913 100755 --- a/util/release/genrelnotes +++ b/util/release/genrelnotes @@ -202,12 +202,22 @@ show_diff () { local new local old - new="$(comm -13 <(echo "$2") <(echo "$3") | sed 's/^/* /')" + new="$(comm -13 <(echo "$2") <(echo "$3"))" + old="$(comm -23 <(echo "$2") <(echo "$3"))" + + # Allow running a postprocessor, given as 4th argument over the + # resulting diff, provide context if it's old or new data + if [ -n "$4" ]; then + new=$(echo "$new" | $4 new | sort) + old=$(echo "$old" | $4 old | sort) + fi + new="$(printf "$new" | sed 's/^/* /')" + old="$(printf "$old" | sed 's/^/* /')" + if [ -n "$new" ]; then printf "Added %s $1:\n-------------------\n%s\n\n" \ "$(echo "$new" | wc -l)" "$new" >> "$LOGFILE" fi - old="$(comm -23 <(echo "$2") <(echo "$3") | sed 's/^/* /')" if [ -n "$old" ]; then printf "Removed %s $1:\n-------------------\n%s\n\n" \ "$(echo "$old" | wc -l)" "$old" >> "$LOGFILE" @@ -400,8 +410,26 @@ get_log_dedupe "Maintainers" "MAINTAINERS" "" # Finally, get anything that was missed above get_log_dedupe "MISC" "." +# Replace VENDOR_DEVICE from stdin with their nice names on stdout +real_mainboard_names() { + local tree_version=$1 # "old" or "new" + local git_version_var=${tree_version^^}_GIT_VERSION + local git_version=${!git_version_var} + local line + + while read line; do + local file="$(git grep -l "^[[:space:]]*config\>[[:space:]]*\[[:space:]]*\ Date: Wed, 20 Nov 2019 17:15:13 +0100 Subject: [PATCH 0349/1242] util/release: Don't wildly rename Makefiles Even with four cloc invocations it's faster than doing the rename dance and messes up the tree less. It also opens up using cloc's git mode to work on a git tree instead of a checkout. Change-Id: I3ad8fc6802ecedb332359d00b28ea61c33ed2ea0 Signed-off-by: Patrick Georgi Reviewed-on: https://review.coreboot.org/c/coreboot/+/37023 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer --- util/release/genrelnotes | 27 +++++++++++++++++++++------ 1 file changed, 21 insertions(+), 6 deletions(-) diff --git a/util/release/genrelnotes b/util/release/genrelnotes index e3af48c913..c19aaa7215 100755 --- a/util/release/genrelnotes +++ b/util/release/genrelnotes @@ -226,14 +226,29 @@ show_diff () { get_sloc () { # Because cloc works on extensions, and .inc identifies as pascal, - # rename Makefile.inc, then remap the other .inc files to c - find 'src' -name 'Makefile.inc' -exec rename 's/Makefile\.inc/gnumakefile/' {} \; + # while we use it both for Makefile.inc and some files that are + # really C, do three passes: everything but .inc files, all .inc files + # that aren't Makefiles, all Makefile.inc, then combine them. - cloc --progress-rate=0 --quiet --script-lang="Bourne Shell",bash \ - --force-lang=c,inc --exclude-dir=vendorcode src + local base=`mktemp` + find src -name Makefile.inc > ${base}.mak - # Change all the makefiles back to Makefile.inc - find 'src' -name 'gnumakefile' -exec rename 's/gnumakefile/Makefile\.inc/' {} \; + cloc --progress-rate=0 --quiet \ + --script-lang="Bourne Shell",bash --exclude-ext=inc \ + --exclude-dir=vendorcode --out=${base} src + cloc --progress-rate=0 --quiet \ + --exclude-list-file=${base}.mak --force-lang=c,inc \ + --exclude-dir=vendorcode --out=${base}.c src + cloc --progress-rate=0 --quiet \ + --list-file=${base}.mak --force-lang=make,inc \ + --exclude-dir=vendorcode --out=${base}.m src + cloc --progress-rate=0 --quiet --sum-reports \ + ${base} ${base}.c ${base}.m --out ${base}.result + + echo + cat ${base}.result.lang + + rm -f ${base}* } # Start collecting data from the old and new revisions. From 1bdfe8c2805db396c7188dd5264bf80e7782b8ba Mon Sep 17 00:00:00 2001 From: Douglas Anderson Date: Wed, 20 Nov 2019 11:18:52 -0800 Subject: [PATCH 0350/1242] qualcomm: qgpt: Fixes for python3 * Binary strings should be joined with a binary string * Binary files should be opened in binary mode. * Division that wants truncation should make it explicit. I have tested that these changes let me compile. Change-Id: I7c41b80688a9c6bdb3c66561ff531311cc7ebb13 Signed-off-by: Douglas Anderson Reviewed-on: https://review.coreboot.org/c/coreboot/+/37024 Reviewed-by: Julius Werner Reviewed-by: Patrick Georgi Tested-by: build bot (Jenkins) --- util/qualcomm/qgpt.py | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/util/qualcomm/qgpt.py b/util/qualcomm/qgpt.py index 51018361e1..476ca5ca76 100755 --- a/util/qualcomm/qgpt.py +++ b/util/qualcomm/qgpt.py @@ -167,7 +167,7 @@ def UpdateGPTHeader(options, GPTBlobBuffer): # CRC of Partition Entry PartEntry = GPTBlobBuffer[options.sector_size*2:options.sector_size*2 + 128] - CalcEntryCRC = crc32(''.join(struct.pack("B", x) for x in PartEntry)) + CalcEntryCRC = crc32(b''.join(struct.pack("B", x) for x in PartEntry)) GPTBlobBuffer[i] = CalcEntryCRC & 0xFF GPTBlobBuffer[i+1] = (CalcEntryCRC>>8) & 0xFF @@ -177,7 +177,7 @@ def UpdateGPTHeader(options, GPTBlobBuffer): # CRC of Partition Table Header GPTHeader = GPTBlobBuffer[options.sector_size:options.sector_size + 92] - CalcEntryCRC = crc32(''.join(struct.pack("B", x) for x in GPTHeader)) + CalcEntryCRC = crc32(b''.join(struct.pack("B", x) for x in GPTHeader)) i = options.sector_size + 16 GPTBlobBuffer[i] = CalcEntryCRC & 0xFF @@ -209,11 +209,11 @@ if __name__ == '__main__': options.inputfile = args[0] options.outputfile = args[1] - with open(options.inputfile, 'r+') as fin: + with open(options.inputfile, 'rb+') as fin: bb_buffer = fin.read() # Round up to next sector if bootblock size not evenly divisible - options.end_lba = ((len(bb_buffer) + options.sector_size - 1) / + options.end_lba = ((len(bb_buffer) + options.sector_size - 1) // options.sector_size) # Add 3 sectors for MBR, GPT header and GPT partition entry options.end_lba += 3 From d0c52b72f3b225d13a4f7ab79bcba5ca8af166a8 Mon Sep 17 00:00:00 2001 From: Peichao Wang Date: Tue, 19 Nov 2019 11:42:42 +0800 Subject: [PATCH 0351/1242] mb/google/kahlee/treeya: Set touchpad hold time to 400ns According to SI team request, need to tune I2C bus 2 data hold time more than 300ns BUG=b:144736027 TEST=build firmware and measure I2C bus 2 data hold time Signed-off-by: Peichao Wang Change-Id: Idc58a595c77eba8544f27682a284be6aac5dbe25 Reviewed-on: https://review.coreboot.org/c/coreboot/+/36945 Reviewed-by: Patrick Georgi Reviewed-by: Martin Roth Tested-by: build bot (Jenkins) --- src/mainboard/google/kahlee/variants/treeya/devicetree.cb | 1 + 1 file changed, 1 insertion(+) diff --git a/src/mainboard/google/kahlee/variants/treeya/devicetree.cb b/src/mainboard/google/kahlee/variants/treeya/devicetree.cb index e8477eeb6a..e35f00c380 100644 --- a/src/mainboard/google/kahlee/variants/treeya/devicetree.cb +++ b/src/mainboard/google/kahlee/variants/treeya/devicetree.cb @@ -44,6 +44,7 @@ chip soc/amd/stoneyridge .speed = I2C_SPEED_FAST, .rise_time_ns = 3, .fall_time_ns = 2, + .data_hold_time_ns = 400, }" # Enable I2C3 for touchscreen at 400kHz From 0df1cccc0aed040ef8f77b3eab24ef9a98211dca Mon Sep 17 00:00:00 2001 From: Krystian Hebel Date: Tue, 19 Nov 2019 17:44:32 +0100 Subject: [PATCH 0352/1242] vendorcode/amd/pi/Makefile.inc: remove -fno-zero-initialized-in-bss MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This fixes issue that became visible after implementing post-CAR stage on top of `340e4b80904f lib/cbmem_top: Add a common cbmem_top implementation`. Compilation error was: Forbidden global variables in romstage: ffffff00 d top.2205 Signed-off-by: Krystian Hebel Change-Id: I088ac824f9b66387843ae5810fd2c75a8b16d9db Reviewed-on: https://review.coreboot.org/c/coreboot/+/36976 Reviewed-by: Kyösti Mälkki Reviewed-by: Arthur Heymans Tested-by: build bot (Jenkins) --- src/vendorcode/amd/pi/Makefile.inc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/vendorcode/amd/pi/Makefile.inc b/src/vendorcode/amd/pi/Makefile.inc index 4e8787bed2..90714aa286 100644 --- a/src/vendorcode/amd/pi/Makefile.inc +++ b/src/vendorcode/amd/pi/Makefile.inc @@ -68,7 +68,7 @@ AGESA_INC += -I$(src)/include AGESA_INC += -I$(src)/commonlib/include AGESA_INC += -I$(VBOOT_SOURCE)/firmware/include -AGESA_CFLAGS += -march=amdfam10 -mno-3dnow -fno-zero-initialized-in-bss +AGESA_CFLAGS += -march=amdfam10 -mno-3dnow AGESA_CFLAGS += -fno-strict-aliasing -D__LIBAGESA__ CFLAGS_x86_32 += $(AGESA_CFLAGS) CFLAGS_x86_64 += $(AGESA_CFLAGS) From 27cb3e0d31275e702e34a2085f9cf248b742d3cf Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ky=C3=B6sti=20M=C3=A4lkki?= Date: Tue, 8 Oct 2019 19:25:57 +0300 Subject: [PATCH 0353/1242] soc/amd: Move SCI enable outside table creation MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Preferably, coreboot tables creation is kept hardware-invariant. Change-Id: Id7f79fc959766813d60f847482567579a02db124 Signed-off-by: Kyösti Mälkki Reviewed-on: https://review.coreboot.org/c/coreboot/+/36811 Tested-by: build bot (Jenkins) Reviewed-by: Richard Spiegel Reviewed-by: Marshall Dawson --- src/soc/amd/picasso/acpi.c | 2 -- src/soc/amd/picasso/finalize.c | 9 +++++++++ src/soc/amd/stoneyridge/acpi.c | 2 -- src/soc/amd/stoneyridge/finalize.c | 9 +++++++++ 4 files changed, 18 insertions(+), 4 deletions(-) diff --git a/src/soc/amd/picasso/acpi.c b/src/soc/amd/picasso/acpi.c index 8597c4e15d..7b70ec6be4 100644 --- a/src/soc/amd/picasso/acpi.c +++ b/src/soc/amd/picasso/acpi.c @@ -98,7 +98,6 @@ void acpi_create_fadt(acpi_fadt_t *fadt, acpi_facs_t *facs, void *dsdt) fadt->s4bios_req = 0; /* Not supported */ fadt->pstate_cnt = 0; /* Not supported */ fadt->cst_cnt = 0; /* Not supported */ - acpi_disable_sci(); } else { fadt->smi_cmd = 0; /* disable system management mode */ fadt->acpi_enable = 0; /* unused if SMI_CMD = 0 */ @@ -106,7 +105,6 @@ void acpi_create_fadt(acpi_fadt_t *fadt, acpi_facs_t *facs, void *dsdt) fadt->s4bios_req = 0; /* unused if SMI_CMD = 0 */ fadt->pstate_cnt = 0; /* unused if SMI_CMD = 0 */ fadt->cst_cnt = 0x00; /* unused if SMI_CMD = 0 */ - acpi_enable_sci(); } fadt->pm1a_evt_blk = ACPI_PM_EVT_BLK; diff --git a/src/soc/amd/picasso/finalize.c b/src/soc/amd/picasso/finalize.c index 0ec7bd9218..5ea52c6eaf 100644 --- a/src/soc/amd/picasso/finalize.c +++ b/src/soc/amd/picasso/finalize.c @@ -13,12 +13,14 @@ * GNU General Public License for more details. */ +#include #include #include #include #include #include #include +#include static void per_core_finalize(void *unused) { @@ -53,6 +55,13 @@ static void soc_finalize(void *unused) { finalize_cores(); + if (!acpi_is_wakeup_s3()) { + if (CONFIG(HAVE_SMI_HANDLER)) + acpi_disable_sci(); + else + acpi_enable_sci(); + } + post_code(POST_OS_BOOT); } diff --git a/src/soc/amd/stoneyridge/acpi.c b/src/soc/amd/stoneyridge/acpi.c index d1ea24ffd5..13020ed1da 100644 --- a/src/soc/amd/stoneyridge/acpi.c +++ b/src/soc/amd/stoneyridge/acpi.c @@ -100,7 +100,6 @@ void acpi_create_fadt(acpi_fadt_t *fadt, acpi_facs_t *facs, void *dsdt) fadt->s4bios_req = 0; /* Not supported */ fadt->pstate_cnt = 0; /* Not supported */ fadt->cst_cnt = 0; /* Not supported */ - acpi_disable_sci(); } else { fadt->smi_cmd = 0; /* disable system management mode */ fadt->acpi_enable = 0; /* unused if SMI_CMD = 0 */ @@ -108,7 +107,6 @@ void acpi_create_fadt(acpi_fadt_t *fadt, acpi_facs_t *facs, void *dsdt) fadt->s4bios_req = 0; /* unused if SMI_CMD = 0 */ fadt->pstate_cnt = 0; /* unused if SMI_CMD = 0 */ fadt->cst_cnt = 0x00; /* unused if SMI_CMD = 0 */ - acpi_enable_sci(); } fadt->pm1a_evt_blk = ACPI_PM_EVT_BLK; diff --git a/src/soc/amd/stoneyridge/finalize.c b/src/soc/amd/stoneyridge/finalize.c index 0ec7bd9218..5ea52c6eaf 100644 --- a/src/soc/amd/stoneyridge/finalize.c +++ b/src/soc/amd/stoneyridge/finalize.c @@ -13,12 +13,14 @@ * GNU General Public License for more details. */ +#include #include #include #include #include #include #include +#include static void per_core_finalize(void *unused) { @@ -53,6 +55,13 @@ static void soc_finalize(void *unused) { finalize_cores(); + if (!acpi_is_wakeup_s3()) { + if (CONFIG(HAVE_SMI_HANDLER)) + acpi_disable_sci(); + else + acpi_enable_sci(); + } + post_code(POST_OS_BOOT); } From f3758b6738d2968980309257197ef4f1977dc974 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ky=C3=B6sti=20M=C3=A4lkki?= Date: Tue, 8 Oct 2019 19:25:57 +0300 Subject: [PATCH 0354/1242] AGESA,binaryPI: Move SCI enable outside table creation MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Preferably, coreboot tables creation is kept hardware-invariant. Change-Id: I37810771090dd9b0377f9a72c7a17ef1564ccf68 Signed-off-by: Kyösti Mälkki Reviewed-on: https://review.coreboot.org/c/coreboot/+/36812 Reviewed-by: Michał Żygowski Reviewed-by: Marshall Dawson Tested-by: build bot (Jenkins) --- src/southbridge/amd/agesa/hudson/fadt.c | 3 --- src/southbridge/amd/agesa/hudson/lpc.c | 12 ++++++++++++ src/southbridge/amd/pi/hudson/fadt.c | 3 --- src/southbridge/amd/pi/hudson/lpc.c | 12 ++++++++++++ 4 files changed, 24 insertions(+), 6 deletions(-) diff --git a/src/southbridge/amd/agesa/hudson/fadt.c b/src/southbridge/amd/agesa/hudson/fadt.c index 28f035c3b8..425a084a07 100644 --- a/src/southbridge/amd/agesa/hudson/fadt.c +++ b/src/southbridge/amd/agesa/hudson/fadt.c @@ -20,7 +20,6 @@ #include #include #include -#include #include #include @@ -78,7 +77,6 @@ void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt) fadt->s4bios_req = 0; /* Not supported */ fadt->pstate_cnt = 0; /* Not supported */ fadt->cst_cnt = 0; /* Not supported */ - outl(0x0, ACPI_PM1_CNT_BLK); /* clear SCI_EN */ } else { fadt->smi_cmd = 0; /* disable system management mode */ fadt->acpi_enable = 0; /* unused if SMI_CMD = 0 */ @@ -86,7 +84,6 @@ void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt) fadt->s4bios_req = 0; /* unused if SMI_CMD = 0 */ fadt->pstate_cnt = 0; /* unused if SMI_CMD = 0 */ fadt->cst_cnt = 0x00; /* unused if SMI_CMD = 0 */ - outl(0x1, ACPI_PM1_CNT_BLK); /* set SCI_EN */ } fadt->pm1a_evt_blk = ACPI_PM_EVT_BLK; diff --git a/src/southbridge/amd/agesa/hudson/lpc.c b/src/southbridge/amd/agesa/hudson/lpc.c index 4cfbb6487e..eed1aec2e3 100644 --- a/src/southbridge/amd/agesa/hudson/lpc.c +++ b/src/southbridge/amd/agesa/hudson/lpc.c @@ -23,6 +23,7 @@ #include #include #include +#include #include #include #include @@ -335,6 +336,16 @@ unsigned long acpi_fill_mcfg(unsigned long current) return current; } +static void lpc_final(struct device *dev) +{ + if (!acpi_is_wakeup_s3()) { + if (CONFIG(HAVE_SMI_HANDLER)) + outl(0x0, ACPI_PM1_CNT_BLK); /* clear SCI_EN */ + else + outl(0x1, ACPI_PM1_CNT_BLK); /* set SCI_EN */ + } +} + static struct pci_operations lops_pci = { .set_subsystem = pci_dev_set_subsystem, }; @@ -347,6 +358,7 @@ static struct device_operations lpc_ops = { .write_acpi_tables = acpi_write_hpet, #endif .init = lpc_init, + .final = lpc_final, .scan_bus = scan_static_bus, .ops_pci = &lops_pci, .acpi_name = lpc_acpi_name, diff --git a/src/southbridge/amd/pi/hudson/fadt.c b/src/southbridge/amd/pi/hudson/fadt.c index 28e20d38ca..61e046df0f 100644 --- a/src/southbridge/amd/pi/hudson/fadt.c +++ b/src/southbridge/amd/pi/hudson/fadt.c @@ -20,7 +20,6 @@ #include #include #include -#include #include #include @@ -70,7 +69,6 @@ void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt) fadt->s4bios_req = 0; /* Not supported */ fadt->pstate_cnt = 0; /* Not supported */ fadt->cst_cnt = 0; /* Not supported */ - outl(0x0, ACPI_PM1_CNT_BLK); /* clear SCI_EN */ } else { fadt->smi_cmd = 0; /* disable system management mode */ fadt->acpi_enable = 0; /* unused if SMI_CMD = 0 */ @@ -78,7 +76,6 @@ void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt) fadt->s4bios_req = 0; /* unused if SMI_CMD = 0 */ fadt->pstate_cnt = 0; /* unused if SMI_CMD = 0 */ fadt->cst_cnt = 0x00; /* unused if SMI_CMD = 0 */ - outl(0x1, ACPI_PM1_CNT_BLK); /* set SCI_EN */ } fadt->pm1a_evt_blk = ACPI_PM_EVT_BLK; diff --git a/src/southbridge/amd/pi/hudson/lpc.c b/src/southbridge/amd/pi/hudson/lpc.c index 1e080a0e8e..e65fd838b0 100644 --- a/src/southbridge/amd/pi/hudson/lpc.c +++ b/src/southbridge/amd/pi/hudson/lpc.c @@ -23,6 +23,7 @@ #include #include #include +#include #include #include #include @@ -351,6 +352,16 @@ static const char *lpc_acpi_name(const struct device *dev) return NULL; } +static void lpc_final(struct device *dev) +{ + if (!acpi_is_wakeup_s3()) { + if (CONFIG(HAVE_SMI_HANDLER)) + outl(0x0, ACPI_PM1_CNT_BLK); /* clear SCI_EN */ + else + outl(0x1, ACPI_PM1_CNT_BLK); /* set SCI_EN */ + } +} + static struct pci_operations lops_pci = { .set_subsystem = pci_dev_set_subsystem, }; @@ -363,6 +374,7 @@ static struct device_operations lpc_ops = { .write_acpi_tables = acpi_write_hpet, #endif .init = lpc_init, + .final = lpc_final, .scan_bus = scan_static_bus, .ops_pci = &lops_pci, .acpi_name = lpc_acpi_name, From 0bb83469ed29a576f8a89a6a775ce65fcf6505bb Mon Sep 17 00:00:00 2001 From: Patrick Georgi Date: Fri, 22 Nov 2019 20:58:58 +0100 Subject: [PATCH 0355/1242] Kconfig: comply to Linux 5.3's Kconfig language rules Kconfig became stricter on what it accepts, so accomodate before updating to a new release. Change-Id: I92a9e9bf0d557a7532ba533cd7776c48f2488f91 Signed-off-by: Patrick Georgi Reviewed-on: https://review.coreboot.org/c/coreboot/+/37156 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer --- payloads/external/LinuxBoot/Kconfig | 1 - src/arch/arm/Kconfig | 4 +- src/arch/arm64/Kconfig | 2 +- src/console/Kconfig | 4 +- src/cpu/amd/Kconfig | 4 +- src/cpu/amd/agesa/Kconfig | 6 +- src/cpu/amd/pi/Kconfig | 6 +- src/cpu/armltd/Kconfig | 2 +- src/cpu/intel/Kconfig | 56 +++++++++---------- src/cpu/ti/Kconfig | 2 +- src/drivers/uart/Kconfig | 4 +- src/mainboard/amd/bettong/Kconfig | 2 +- src/mainboard/amd/db-ft3b-lc/Kconfig | 2 +- src/mainboard/amd/gardenia/Kconfig | 2 +- src/mainboard/amd/inagua/Kconfig | 2 +- src/mainboard/amd/lamar/Kconfig | 2 +- src/mainboard/amd/olivehill/Kconfig | 2 +- src/mainboard/amd/olivehillplus/Kconfig | 2 +- src/mainboard/amd/padmelon/Kconfig | 2 +- src/mainboard/amd/parmer/Kconfig | 2 +- src/mainboard/amd/persimmon/Kconfig | 2 +- src/mainboard/amd/south_station/Kconfig | 2 +- src/mainboard/amd/thatcher/Kconfig | 2 +- src/mainboard/amd/union_station/Kconfig | 2 +- src/mainboard/aopen/dxplplusu/Kconfig | 2 +- src/mainboard/apple/macbook21/Kconfig | 2 +- src/mainboard/apple/macbookair4_2/Kconfig | 2 +- src/mainboard/asrock/b75pro3-m/Kconfig | 2 +- src/mainboard/asrock/e350m1/Kconfig | 2 +- src/mainboard/asrock/h81m-hds/Kconfig | 2 +- src/mainboard/asrock/imb-a180/Kconfig | 2 +- src/mainboard/asus/am1i-a/Kconfig | 2 +- src/mainboard/asus/f2a85-m/Kconfig | 2 +- src/mainboard/asus/h61m-cs/Kconfig | 2 +- src/mainboard/asus/maximus_iv_gene-z/Kconfig | 2 +- src/mainboard/asus/p2b-d/Kconfig | 2 +- src/mainboard/asus/p2b-ds/Kconfig | 2 +- src/mainboard/asus/p2b-f/Kconfig | 2 +- src/mainboard/asus/p2b-ls/Kconfig | 2 +- src/mainboard/asus/p2b/Kconfig | 2 +- src/mainboard/asus/p3b-f/Kconfig | 2 +- src/mainboard/asus/p5gc-mx/Kconfig | 2 +- src/mainboard/asus/p8h61-m_lx/Kconfig | 2 +- src/mainboard/asus/p8h61-m_pro/Kconfig | 2 +- src/mainboard/bap/ode_e20XX/Kconfig | 2 +- src/mainboard/bap/ode_e21XX/Kconfig | 2 +- src/mainboard/biostar/a68n_5200/Kconfig | 2 +- src/mainboard/biostar/am1ml/Kconfig | 2 +- src/mainboard/compulab/intense_pc/Kconfig | 2 +- src/mainboard/elmex/pcm205400/Kconfig | 2 +- src/mainboard/emulation/qemu-aarch64/Kconfig | 2 +- src/mainboard/emulation/qemu-armv7/Kconfig | 2 +- src/mainboard/emulation/qemu-i440fx/Kconfig | 2 +- src/mainboard/emulation/qemu-q35/Kconfig | 2 +- src/mainboard/emulation/qemu-riscv/Kconfig | 2 +- src/mainboard/emulation/spike-riscv/Kconfig | 2 +- .../emulation/spike-riscv/Kconfig.name | 1 - src/mainboard/facebook/fbg1701/Kconfig | 2 +- src/mainboard/foxconn/d41s/Kconfig | 2 +- src/mainboard/getac/p470/Kconfig | 2 +- src/mainboard/gigabyte/ga-945gcm-s2l/Kconfig | 2 +- src/mainboard/gigabyte/ga-b75m-d3h/Kconfig | 2 +- src/mainboard/gizmosphere/gizmo/Kconfig | 2 +- src/mainboard/gizmosphere/gizmo2/Kconfig | 2 +- src/mainboard/google/auron/Kconfig | 2 +- src/mainboard/google/beltino/Kconfig | 2 +- src/mainboard/google/butterfly/Kconfig | 2 +- src/mainboard/google/cheza/Kconfig | 2 +- src/mainboard/google/cyan/Kconfig | 2 +- src/mainboard/google/daisy/Kconfig | 2 +- src/mainboard/google/foster/Kconfig | 2 +- src/mainboard/google/gale/Kconfig | 2 +- src/mainboard/google/gru/Kconfig | 2 +- src/mainboard/google/jecht/Kconfig | 2 +- src/mainboard/google/kahlee/Kconfig | 2 +- src/mainboard/google/kukui/Kconfig | 2 +- src/mainboard/google/link/Kconfig | 2 +- src/mainboard/google/mistral/Kconfig | 2 +- src/mainboard/google/nyan/Kconfig | 2 +- src/mainboard/google/nyan_big/Kconfig | 2 +- src/mainboard/google/nyan_blaze/Kconfig | 2 +- src/mainboard/google/oak/Kconfig | 2 +- src/mainboard/google/octopus/Kconfig | 2 +- src/mainboard/google/parrot/Kconfig | 2 +- src/mainboard/google/peach_pit/Kconfig | 2 +- src/mainboard/google/rambi/Kconfig | 2 +- src/mainboard/google/reef/Kconfig | 2 +- src/mainboard/google/slippy/Kconfig | 2 +- src/mainboard/google/smaug/Kconfig | 2 +- src/mainboard/google/storm/Kconfig | 2 +- src/mainboard/google/stout/Kconfig | 2 +- src/mainboard/google/trogdor/Kconfig | 2 +- src/mainboard/google/veyron/Kconfig | 2 +- src/mainboard/google/veyron_mickey/Kconfig | 2 +- src/mainboard/google/veyron_rialto/Kconfig | 2 +- src/mainboard/hp/2570p/Kconfig | 2 +- src/mainboard/hp/2760p/Kconfig | 2 +- src/mainboard/hp/8460p/Kconfig | 2 +- src/mainboard/hp/8470p/Kconfig | 2 +- src/mainboard/hp/8770w/Kconfig | 2 +- src/mainboard/hp/abm/Kconfig | 2 +- .../hp/compaq_8200_elite_sff/Kconfig | 2 +- src/mainboard/hp/folio_9470m/Kconfig | 2 +- src/mainboard/hp/pavilion_m6_1035dx/Kconfig | 2 +- src/mainboard/hp/revolve_810_g1/Kconfig | 2 +- src/mainboard/hp/z220_sff_workstation/Kconfig | 2 +- src/mainboard/ibase/mb899/Kconfig | 2 +- src/mainboard/intel/apollolake_rvp/Kconfig | 2 +- src/mainboard/intel/baskingridge/Kconfig | 2 +- src/mainboard/intel/d510mo/Kconfig | 2 +- src/mainboard/intel/d945gclf/Kconfig | 2 +- src/mainboard/intel/dcp847ske/Kconfig | 2 +- src/mainboard/intel/emeraldlake2/Kconfig | 2 +- src/mainboard/intel/galileo/Kconfig | 2 +- src/mainboard/intel/glkrvp/Kconfig | 2 +- src/mainboard/intel/harcuvar/Kconfig | 2 +- src/mainboard/intel/leafhill/Kconfig | 2 +- src/mainboard/intel/minnow3/Kconfig | 2 +- src/mainboard/intel/strago/Kconfig | 2 +- src/mainboard/intel/wtm2/Kconfig | 2 +- src/mainboard/jetway/nf81-t56n-lf/Kconfig | 2 +- src/mainboard/kontron/986lcd-m/Kconfig | 2 +- src/mainboard/kontron/ktqm77/Kconfig | 2 +- src/mainboard/lenovo/g505s/Kconfig | 2 +- src/mainboard/lenovo/l520/Kconfig | 2 +- src/mainboard/lenovo/s230u/Kconfig | 2 +- src/mainboard/lenovo/t400/Kconfig | 2 +- src/mainboard/lenovo/t410/Kconfig | 2 +- src/mainboard/lenovo/t420/Kconfig | 2 +- src/mainboard/lenovo/t420s/Kconfig | 2 +- src/mainboard/lenovo/t430/Kconfig | 2 +- src/mainboard/lenovo/t430s/Kconfig | 2 +- src/mainboard/lenovo/t440p/Kconfig | 2 +- src/mainboard/lenovo/t520/Kconfig | 2 +- src/mainboard/lenovo/t530/Kconfig | 2 +- src/mainboard/lenovo/t60/Kconfig | 2 +- src/mainboard/lenovo/x131e/Kconfig | 2 +- src/mainboard/lenovo/x1_carbon_gen1/Kconfig | 2 +- src/mainboard/lenovo/x200/Kconfig | 2 +- src/mainboard/lenovo/x201/Kconfig | 2 +- src/mainboard/lenovo/x220/Kconfig | 2 +- src/mainboard/lenovo/x230/Kconfig | 2 +- src/mainboard/lenovo/x60/Kconfig | 2 +- src/mainboard/lippert/frontrunner-af/Kconfig | 2 +- src/mainboard/lippert/toucan-af/Kconfig | 2 +- src/mainboard/msi/ms7707/Kconfig | 2 +- src/mainboard/msi/ms7721/Kconfig | 2 +- src/mainboard/packardbell/ms2290/Kconfig | 2 +- src/mainboard/pcengines/apu1/Kconfig | 2 +- src/mainboard/pcengines/apu2/Kconfig | 2 +- src/mainboard/portwell/m107/Kconfig | 2 +- src/mainboard/purism/librem_bdw/Kconfig | 2 +- src/mainboard/roda/rk886ex/Kconfig | 2 +- src/mainboard/roda/rk9/Kconfig | 2 +- src/mainboard/samsung/lumpy/Kconfig | 2 +- src/mainboard/samsung/stumpy/Kconfig | 2 +- .../sapphire/pureplatinumh61/Kconfig | 2 +- src/mainboard/scaleway/tagada/Kconfig | 2 +- src/mainboard/siemens/mc_apl1/Kconfig | 2 +- src/mainboard/sifive/hifive-unleashed/Kconfig | 2 +- src/mainboard/ti/beaglebone/Kconfig | 2 +- src/northbridge/amd/pi/Kconfig | 6 +- src/southbridge/amd/agesa/Kconfig | 2 +- src/southbridge/amd/cimx/Kconfig | 2 +- src/southbridge/amd/pi/Kconfig | 2 +- src/vendorcode/amd/Kconfig | 2 +- src/vendorcode/eltan/security/Kconfig | 4 +- src/vendorcode/google/Kconfig | 2 +- 168 files changed, 204 insertions(+), 206 deletions(-) diff --git a/payloads/external/LinuxBoot/Kconfig b/payloads/external/LinuxBoot/Kconfig index a91288bca7..d132c7e848 100644 --- a/payloads/external/LinuxBoot/Kconfig +++ b/payloads/external/LinuxBoot/Kconfig @@ -117,7 +117,6 @@ config LINUXBOOT_KERNEL_ARCH_DEFAULT_CONFIG config LINUXBOOT_KERNEL_CUSTOM_CONFIG bool "Custom (def)config file" - help endchoice diff --git a/src/arch/arm/Kconfig b/src/arch/arm/Kconfig index 47c333bf6a..1eed2de4d0 100644 --- a/src/arch/arm/Kconfig +++ b/src/arch/arm/Kconfig @@ -18,8 +18,8 @@ config ARCH_RAMSTAGE_ARM bool select ARCH_ARM -source src/arch/arm/armv4/Kconfig -source src/arch/arm/armv7/Kconfig +source "src/arch/arm/armv4/Kconfig" +source "src/arch/arm/armv7/Kconfig" config ARM_LPAE bool diff --git a/src/arch/arm64/Kconfig b/src/arch/arm64/Kconfig index 3d1d1843e0..96a23dc41b 100644 --- a/src/arch/arm64/Kconfig +++ b/src/arch/arm64/Kconfig @@ -18,7 +18,7 @@ config ARCH_RAMSTAGE_ARM64 bool select ARCH_ARM64 -source src/arch/arm64/armv8/Kconfig +source "src/arch/arm64/armv8/Kconfig" if ARCH_ARM64 diff --git a/src/console/Kconfig b/src/console/Kconfig index e767edd4fd..b90823ecd0 100644 --- a/src/console/Kconfig +++ b/src/console/Kconfig @@ -88,7 +88,7 @@ comment "Serial port base address = 0x2e8" depends on DRIVERS_UART_8250IO && UART_FOR_CONSOLE = 3 config UART_OVERRIDE_BAUDRATE - boolean + bool help Set to "y" when the platform overrides the baudrate by providing a get_uart_baudrate routine. @@ -303,7 +303,7 @@ config SPI_CONSOLE drivers are written. config CONSOLE_OVERRIDE_LOGLEVEL - boolean + bool help Set to "y" when the platform overrides the loglevel by providing a get_console_loglevel routine. diff --git a/src/cpu/amd/Kconfig b/src/cpu/amd/Kconfig index 4ade0f678e..db8989de19 100644 --- a/src/cpu/amd/Kconfig +++ b/src/cpu/amd/Kconfig @@ -1,2 +1,2 @@ -source src/cpu/amd/agesa/Kconfig -source src/cpu/amd/pi/Kconfig +source "src/cpu/amd/agesa/Kconfig" +source "src/cpu/amd/pi/Kconfig" diff --git a/src/cpu/amd/agesa/Kconfig b/src/cpu/amd/agesa/Kconfig index b6b757f6ae..ddfe707d79 100644 --- a/src/cpu/amd/agesa/Kconfig +++ b/src/cpu/amd/agesa/Kconfig @@ -66,6 +66,6 @@ config S3_DATA_SIZE endif # CPU_AMD_AGESA -source src/cpu/amd/agesa/family14/Kconfig -source src/cpu/amd/agesa/family15tn/Kconfig -source src/cpu/amd/agesa/family16kb/Kconfig +source "src/cpu/amd/agesa/family14/Kconfig" +source "src/cpu/amd/agesa/family15tn/Kconfig" +source "src/cpu/amd/agesa/family16kb/Kconfig" diff --git a/src/cpu/amd/pi/Kconfig b/src/cpu/amd/pi/Kconfig index b33302ecef..ee6fa4bb5c 100644 --- a/src/cpu/amd/pi/Kconfig +++ b/src/cpu/amd/pi/Kconfig @@ -61,6 +61,6 @@ config S3_DATA_SIZE endif # CPU_AMD_PI -source src/cpu/amd/pi/00630F01/Kconfig -source src/cpu/amd/pi/00730F01/Kconfig -source src/cpu/amd/pi/00660F01/Kconfig +source "src/cpu/amd/pi/00630F01/Kconfig" +source "src/cpu/amd/pi/00730F01/Kconfig" +source "src/cpu/amd/pi/00660F01/Kconfig" diff --git a/src/cpu/armltd/Kconfig b/src/cpu/armltd/Kconfig index af0c5c531c..db1af75f33 100644 --- a/src/cpu/armltd/Kconfig +++ b/src/cpu/armltd/Kconfig @@ -1 +1 @@ -source src/cpu/armltd/cortex-a9/Kconfig +source "src/cpu/armltd/cortex-a9/Kconfig" diff --git a/src/cpu/intel/Kconfig b/src/cpu/intel/Kconfig index c21de59ba2..43b360bfc4 100644 --- a/src/cpu/intel/Kconfig +++ b/src/cpu/intel/Kconfig @@ -1,31 +1,31 @@ # CPU models -source src/cpu/intel/model_6xx/Kconfig -source src/cpu/intel/model_65x/Kconfig -source src/cpu/intel/model_67x/Kconfig -source src/cpu/intel/model_68x/Kconfig -source src/cpu/intel/model_6bx/Kconfig -source src/cpu/intel/model_6ex/Kconfig -source src/cpu/intel/model_6fx/Kconfig -source src/cpu/intel/model_1067x/Kconfig -source src/cpu/intel/model_106cx/Kconfig -source src/cpu/intel/model_206ax/Kconfig -source src/cpu/intel/model_2065x/Kconfig -source src/cpu/intel/model_f2x/Kconfig -source src/cpu/intel/model_f3x/Kconfig -source src/cpu/intel/model_f4x/Kconfig -source src/cpu/intel/haswell/Kconfig +source "src/cpu/intel/model_6xx/Kconfig" +source "src/cpu/intel/model_65x/Kconfig" +source "src/cpu/intel/model_67x/Kconfig" +source "src/cpu/intel/model_68x/Kconfig" +source "src/cpu/intel/model_6bx/Kconfig" +source "src/cpu/intel/model_6ex/Kconfig" +source "src/cpu/intel/model_6fx/Kconfig" +source "src/cpu/intel/model_1067x/Kconfig" +source "src/cpu/intel/model_106cx/Kconfig" +source "src/cpu/intel/model_206ax/Kconfig" +source "src/cpu/intel/model_2065x/Kconfig" +source "src/cpu/intel/model_f2x/Kconfig" +source "src/cpu/intel/model_f3x/Kconfig" +source "src/cpu/intel/model_f4x/Kconfig" +source "src/cpu/intel/haswell/Kconfig" # Sockets/Slots -source src/cpu/intel/slot_1/Kconfig -source src/cpu/intel/socket_BGA956/Kconfig -source src/cpu/intel/socket_FCBGA559/Kconfig -source src/cpu/intel/socket_m/Kconfig -source src/cpu/intel/socket_p/Kconfig -source src/cpu/intel/socket_mPGA604/Kconfig -source src/cpu/intel/socket_441/Kconfig -source src/cpu/intel/socket_LGA775/Kconfig +source "src/cpu/intel/slot_1/Kconfig" +source "src/cpu/intel/socket_BGA956/Kconfig" +source "src/cpu/intel/socket_FCBGA559/Kconfig" +source "src/cpu/intel/socket_m/Kconfig" +source "src/cpu/intel/socket_p/Kconfig" +source "src/cpu/intel/socket_mPGA604/Kconfig" +source "src/cpu/intel/socket_441/Kconfig" +source "src/cpu/intel/socket_LGA775/Kconfig" # Architecture specific features -source src/cpu/intel/fit/Kconfig -source src/cpu/intel/turbo/Kconfig -source src/cpu/intel/common/Kconfig -source src/cpu/intel/microcode/Kconfig -source src/cpu/intel/car/non-evict/Kconfig +source "src/cpu/intel/fit/Kconfig" +source "src/cpu/intel/turbo/Kconfig" +source "src/cpu/intel/common/Kconfig" +source "src/cpu/intel/microcode/Kconfig" +source "src/cpu/intel/car/non-evict/Kconfig" diff --git a/src/cpu/ti/Kconfig b/src/cpu/ti/Kconfig index 5a62219dcf..119e84bfc1 100644 --- a/src/cpu/ti/Kconfig +++ b/src/cpu/ti/Kconfig @@ -1 +1 @@ -source src/cpu/ti/am335x/Kconfig +source "src/cpu/ti/am335x/Kconfig" diff --git a/src/drivers/uart/Kconfig b/src/drivers/uart/Kconfig index 1f23a195f3..41b870fbf7 100644 --- a/src/drivers/uart/Kconfig +++ b/src/drivers/uart/Kconfig @@ -20,14 +20,14 @@ config NO_UART_ON_SUPERIO def_bool n config UART_OVERRIDE_INPUT_CLOCK_DIVIDER - boolean + bool default n help Set to "y" when the platform overrides the uart_input_clock_divider routine. config UART_OVERRIDE_REFCLK - boolean + bool default n help Set to "y" when the platform overrides the uart_platform_refclk diff --git a/src/mainboard/amd/bettong/Kconfig b/src/mainboard/amd/bettong/Kconfig index eaebfb5e8f..5f26e8777e 100644 --- a/src/mainboard/amd/bettong/Kconfig +++ b/src/mainboard/amd/bettong/Kconfig @@ -30,7 +30,7 @@ config BOARD_SPECIFIC_OPTIONS config MAINBOARD_DIR string - default amd/bettong + default "amd/bettong" config MAINBOARD_PART_NUMBER string diff --git a/src/mainboard/amd/db-ft3b-lc/Kconfig b/src/mainboard/amd/db-ft3b-lc/Kconfig index ffb3f1043f..256b5553bf 100644 --- a/src/mainboard/amd/db-ft3b-lc/Kconfig +++ b/src/mainboard/amd/db-ft3b-lc/Kconfig @@ -31,7 +31,7 @@ config BOARD_SPECIFIC_OPTIONS config MAINBOARD_DIR string - default amd/db-ft3b-lc + default "amd/db-ft3b-lc" config MAINBOARD_PART_NUMBER string diff --git a/src/mainboard/amd/gardenia/Kconfig b/src/mainboard/amd/gardenia/Kconfig index 7adc678b69..02e3e95953 100644 --- a/src/mainboard/amd/gardenia/Kconfig +++ b/src/mainboard/amd/gardenia/Kconfig @@ -26,7 +26,7 @@ config BOARD_SPECIFIC_OPTIONS config MAINBOARD_DIR string - default amd/gardenia + default "amd/gardenia" config MAINBOARD_PART_NUMBER string diff --git a/src/mainboard/amd/inagua/Kconfig b/src/mainboard/amd/inagua/Kconfig index 6d6ec4fc83..e24af4044a 100644 --- a/src/mainboard/amd/inagua/Kconfig +++ b/src/mainboard/amd/inagua/Kconfig @@ -30,7 +30,7 @@ config BOARD_SPECIFIC_OPTIONS config MAINBOARD_DIR string - default amd/inagua + default "amd/inagua" config MAINBOARD_PART_NUMBER string diff --git a/src/mainboard/amd/lamar/Kconfig b/src/mainboard/amd/lamar/Kconfig index 210b3c2836..025e5ffa80 100644 --- a/src/mainboard/amd/lamar/Kconfig +++ b/src/mainboard/amd/lamar/Kconfig @@ -31,7 +31,7 @@ config BOARD_SPECIFIC_OPTIONS config MAINBOARD_DIR string - default amd/lamar + default "amd/lamar" config MAINBOARD_PART_NUMBER string diff --git a/src/mainboard/amd/olivehill/Kconfig b/src/mainboard/amd/olivehill/Kconfig index 066d967ff4..bd9a2fee81 100644 --- a/src/mainboard/amd/olivehill/Kconfig +++ b/src/mainboard/amd/olivehill/Kconfig @@ -30,7 +30,7 @@ config BOARD_SPECIFIC_OPTIONS config MAINBOARD_DIR string - default amd/olivehill + default "amd/olivehill" config MAINBOARD_PART_NUMBER string diff --git a/src/mainboard/amd/olivehillplus/Kconfig b/src/mainboard/amd/olivehillplus/Kconfig index 5779aaf3c6..96d934702e 100644 --- a/src/mainboard/amd/olivehillplus/Kconfig +++ b/src/mainboard/amd/olivehillplus/Kconfig @@ -30,7 +30,7 @@ config BOARD_SPECIFIC_OPTIONS config MAINBOARD_DIR string - default amd/olivehillplus + default "amd/olivehillplus" config MAINBOARD_PART_NUMBER string diff --git a/src/mainboard/amd/padmelon/Kconfig b/src/mainboard/amd/padmelon/Kconfig index 3d8efb1165..e4dd90c8b3 100644 --- a/src/mainboard/amd/padmelon/Kconfig +++ b/src/mainboard/amd/padmelon/Kconfig @@ -35,7 +35,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy config MAINBOARD_DIR string - default amd/padmelon + default "amd/padmelon" config MAINBOARD_PART_NUMBER string diff --git a/src/mainboard/amd/parmer/Kconfig b/src/mainboard/amd/parmer/Kconfig index 506f9acd57..6d989b63ff 100644 --- a/src/mainboard/amd/parmer/Kconfig +++ b/src/mainboard/amd/parmer/Kconfig @@ -30,7 +30,7 @@ config BOARD_SPECIFIC_OPTIONS config MAINBOARD_DIR string - default amd/parmer + default "amd/parmer" config MAINBOARD_PART_NUMBER string diff --git a/src/mainboard/amd/persimmon/Kconfig b/src/mainboard/amd/persimmon/Kconfig index 4a4d274476..41bf3c9c2e 100644 --- a/src/mainboard/amd/persimmon/Kconfig +++ b/src/mainboard/amd/persimmon/Kconfig @@ -31,7 +31,7 @@ config BOARD_SPECIFIC_OPTIONS config MAINBOARD_DIR string - default amd/persimmon + default "amd/persimmon" config MAINBOARD_PART_NUMBER string diff --git a/src/mainboard/amd/south_station/Kconfig b/src/mainboard/amd/south_station/Kconfig index 6f1d1b41cd..a059403c7b 100644 --- a/src/mainboard/amd/south_station/Kconfig +++ b/src/mainboard/amd/south_station/Kconfig @@ -30,7 +30,7 @@ config BOARD_SPECIFIC_OPTIONS config MAINBOARD_DIR string - default amd/south_station + default "amd/south_station" config MAINBOARD_PART_NUMBER string diff --git a/src/mainboard/amd/thatcher/Kconfig b/src/mainboard/amd/thatcher/Kconfig index 7791a1d630..a957d4c965 100644 --- a/src/mainboard/amd/thatcher/Kconfig +++ b/src/mainboard/amd/thatcher/Kconfig @@ -31,7 +31,7 @@ config BOARD_SPECIFIC_OPTIONS config MAINBOARD_DIR string - default amd/thatcher + default "amd/thatcher" config MAINBOARD_PART_NUMBER string diff --git a/src/mainboard/amd/union_station/Kconfig b/src/mainboard/amd/union_station/Kconfig index 4f2cdddda6..72881b8d4c 100644 --- a/src/mainboard/amd/union_station/Kconfig +++ b/src/mainboard/amd/union_station/Kconfig @@ -29,7 +29,7 @@ config BOARD_SPECIFIC_OPTIONS config MAINBOARD_DIR string - default amd/union_station + default "amd/union_station" config MAINBOARD_PART_NUMBER string diff --git a/src/mainboard/aopen/dxplplusu/Kconfig b/src/mainboard/aopen/dxplplusu/Kconfig index 738a2ea0ae..0036915392 100644 --- a/src/mainboard/aopen/dxplplusu/Kconfig +++ b/src/mainboard/aopen/dxplplusu/Kconfig @@ -12,7 +12,7 @@ config BOARD_SPECIFIC_OPTIONS config MAINBOARD_DIR string - default aopen/dxplplusu + default "aopen/dxplplusu" config MAINBOARD_PART_NUMBER string diff --git a/src/mainboard/apple/macbook21/Kconfig b/src/mainboard/apple/macbook21/Kconfig index 84c00cfa9c..93e2d8d9b4 100644 --- a/src/mainboard/apple/macbook21/Kconfig +++ b/src/mainboard/apple/macbook21/Kconfig @@ -21,7 +21,7 @@ config BOARD_SPECIFIC_OPTIONS config MAINBOARD_DIR string - default apple/macbook21 + default "apple/macbook21" config MAINBOARD_PART_NUMBER string diff --git a/src/mainboard/apple/macbookair4_2/Kconfig b/src/mainboard/apple/macbookair4_2/Kconfig index df8ecfd79d..771f327aa0 100644 --- a/src/mainboard/apple/macbookair4_2/Kconfig +++ b/src/mainboard/apple/macbookair4_2/Kconfig @@ -17,7 +17,7 @@ config BOARD_SPECIFIC_OPTIONS config MAINBOARD_DIR string - default apple/macbookair4_2 + default "apple/macbookair4_2" config MAINBOARD_PART_NUMBER string diff --git a/src/mainboard/asrock/b75pro3-m/Kconfig b/src/mainboard/asrock/b75pro3-m/Kconfig index 878eaad098..561bea5006 100644 --- a/src/mainboard/asrock/b75pro3-m/Kconfig +++ b/src/mainboard/asrock/b75pro3-m/Kconfig @@ -31,7 +31,7 @@ config BOARD_SPECIFIC_OPTIONS config MAINBOARD_DIR string - default asrock/b75pro3-m + default "asrock/b75pro3-m" config MAINBOARD_PART_NUMBER string diff --git a/src/mainboard/asrock/e350m1/Kconfig b/src/mainboard/asrock/e350m1/Kconfig index cc380e5166..3bbc2a5150 100644 --- a/src/mainboard/asrock/e350m1/Kconfig +++ b/src/mainboard/asrock/e350m1/Kconfig @@ -32,7 +32,7 @@ config BOARD_SPECIFIC_OPTIONS config MAINBOARD_DIR string - default asrock/e350m1 + default "asrock/e350m1" config MAINBOARD_PART_NUMBER string diff --git a/src/mainboard/asrock/h81m-hds/Kconfig b/src/mainboard/asrock/h81m-hds/Kconfig index 6974cda95f..7088cbbbe6 100644 --- a/src/mainboard/asrock/h81m-hds/Kconfig +++ b/src/mainboard/asrock/h81m-hds/Kconfig @@ -41,7 +41,7 @@ config CBFS_SIZE config MAINBOARD_DIR string - default asrock/h81m-hds + default "asrock/h81m-hds" config MAINBOARD_PART_NUMBER string diff --git a/src/mainboard/asrock/imb-a180/Kconfig b/src/mainboard/asrock/imb-a180/Kconfig index 3dae526794..2391202cff 100644 --- a/src/mainboard/asrock/imb-a180/Kconfig +++ b/src/mainboard/asrock/imb-a180/Kconfig @@ -31,7 +31,7 @@ config BOARD_SPECIFIC_OPTIONS config MAINBOARD_DIR string - default asrock/imb-a180 + default "asrock/imb-a180" config MAINBOARD_PART_NUMBER string diff --git a/src/mainboard/asus/am1i-a/Kconfig b/src/mainboard/asus/am1i-a/Kconfig index d50edbec27..0aafd8ba64 100644 --- a/src/mainboard/asus/am1i-a/Kconfig +++ b/src/mainboard/asus/am1i-a/Kconfig @@ -20,7 +20,7 @@ config BOARD_SPECIFIC_OPTIONS config MAINBOARD_DIR string - default asus/am1i-a + default "asus/am1i-a" config MAINBOARD_PART_NUMBER string diff --git a/src/mainboard/asus/f2a85-m/Kconfig b/src/mainboard/asus/f2a85-m/Kconfig index 100b33cd7a..c1dd063c77 100644 --- a/src/mainboard/asus/f2a85-m/Kconfig +++ b/src/mainboard/asus/f2a85-m/Kconfig @@ -57,7 +57,7 @@ config BOARD_ASUS_F2A85_M_DDR3_VOLT_VAL config MAINBOARD_DIR string - default asus/f2a85-m + default "asus/f2a85-m" config MAINBOARD_PART_NUMBER string diff --git a/src/mainboard/asus/h61m-cs/Kconfig b/src/mainboard/asus/h61m-cs/Kconfig index 69efa9da81..6040208f27 100644 --- a/src/mainboard/asus/h61m-cs/Kconfig +++ b/src/mainboard/asus/h61m-cs/Kconfig @@ -19,7 +19,7 @@ config BOARD_SPECIFIC_OPTIONS config MAINBOARD_DIR string - default asus/h61m-cs + default "asus/h61m-cs" config MAINBOARD_PART_NUMBER string diff --git a/src/mainboard/asus/maximus_iv_gene-z/Kconfig b/src/mainboard/asus/maximus_iv_gene-z/Kconfig index a0bc31864e..be832ce044 100644 --- a/src/mainboard/asus/maximus_iv_gene-z/Kconfig +++ b/src/mainboard/asus/maximus_iv_gene-z/Kconfig @@ -36,7 +36,7 @@ config BOARD_SPECIFIC_OPTIONS config MAINBOARD_DIR string - default asus/maximus_iv_gene-z + default "asus/maximus_iv_gene-z" config MAINBOARD_PART_NUMBER string diff --git a/src/mainboard/asus/p2b-d/Kconfig b/src/mainboard/asus/p2b-d/Kconfig index e1fc2215e4..8db9b7ad43 100644 --- a/src/mainboard/asus/p2b-d/Kconfig +++ b/src/mainboard/asus/p2b-d/Kconfig @@ -29,7 +29,7 @@ config BOARD_SPECIFIC_OPTIONS config MAINBOARD_DIR string - default asus/p2b-d + default "asus/p2b-d" config MAINBOARD_PART_NUMBER string diff --git a/src/mainboard/asus/p2b-ds/Kconfig b/src/mainboard/asus/p2b-ds/Kconfig index b3c4b2dc16..8b55174f41 100644 --- a/src/mainboard/asus/p2b-ds/Kconfig +++ b/src/mainboard/asus/p2b-ds/Kconfig @@ -29,7 +29,7 @@ config BOARD_SPECIFIC_OPTIONS config MAINBOARD_DIR string - default asus/p2b-ds + default "asus/p2b-ds" config MAINBOARD_PART_NUMBER string diff --git a/src/mainboard/asus/p2b-f/Kconfig b/src/mainboard/asus/p2b-f/Kconfig index f0ab38d0ed..efe625c5d2 100644 --- a/src/mainboard/asus/p2b-f/Kconfig +++ b/src/mainboard/asus/p2b-f/Kconfig @@ -25,7 +25,7 @@ config BOARD_SPECIFIC_OPTIONS config MAINBOARD_DIR string - default asus/p2b-f + default "asus/p2b-f" config MAINBOARD_PART_NUMBER string diff --git a/src/mainboard/asus/p2b-ls/Kconfig b/src/mainboard/asus/p2b-ls/Kconfig index c39dc79bf8..60124fe750 100644 --- a/src/mainboard/asus/p2b-ls/Kconfig +++ b/src/mainboard/asus/p2b-ls/Kconfig @@ -27,7 +27,7 @@ config BOARD_SPECIFIC_OPTIONS config MAINBOARD_DIR string - default asus/p2b-ls + default "asus/p2b-ls" config MAINBOARD_PART_NUMBER string diff --git a/src/mainboard/asus/p2b/Kconfig b/src/mainboard/asus/p2b/Kconfig index f34b4ddfa6..65e7681485 100644 --- a/src/mainboard/asus/p2b/Kconfig +++ b/src/mainboard/asus/p2b/Kconfig @@ -26,7 +26,7 @@ config BOARD_SPECIFIC_OPTIONS config MAINBOARD_DIR string - default asus/p2b + default "asus/p2b" config MAINBOARD_PART_NUMBER string diff --git a/src/mainboard/asus/p3b-f/Kconfig b/src/mainboard/asus/p3b-f/Kconfig index e09adf19a9..179fed29c3 100644 --- a/src/mainboard/asus/p3b-f/Kconfig +++ b/src/mainboard/asus/p3b-f/Kconfig @@ -26,7 +26,7 @@ config BOARD_SPECIFIC_OPTIONS config MAINBOARD_DIR string - default asus/p3b-f + default "asus/p3b-f" config MAINBOARD_PART_NUMBER string diff --git a/src/mainboard/asus/p5gc-mx/Kconfig b/src/mainboard/asus/p5gc-mx/Kconfig index 193364ab72..a0e60146a0 100644 --- a/src/mainboard/asus/p5gc-mx/Kconfig +++ b/src/mainboard/asus/p5gc-mx/Kconfig @@ -34,7 +34,7 @@ config BOARD_SPECIFIC_OPTIONS config MAINBOARD_DIR string - default asus/p5gc-mx + default "asus/p5gc-mx" config MAINBOARD_PART_NUMBER string diff --git a/src/mainboard/asus/p8h61-m_lx/Kconfig b/src/mainboard/asus/p8h61-m_lx/Kconfig index 010641ac66..2210b1a59e 100644 --- a/src/mainboard/asus/p8h61-m_lx/Kconfig +++ b/src/mainboard/asus/p8h61-m_lx/Kconfig @@ -37,7 +37,7 @@ config BOARD_SPECIFIC_OPTIONS config MAINBOARD_DIR string - default asus/p8h61-m_lx + default "asus/p8h61-m_lx" config MAINBOARD_PART_NUMBER string diff --git a/src/mainboard/asus/p8h61-m_pro/Kconfig b/src/mainboard/asus/p8h61-m_pro/Kconfig index e8a6f6404a..0c8988e0c8 100644 --- a/src/mainboard/asus/p8h61-m_pro/Kconfig +++ b/src/mainboard/asus/p8h61-m_pro/Kconfig @@ -37,7 +37,7 @@ config BOARD_SPECIFIC_OPTIONS config MAINBOARD_DIR string - default asus/p8h61-m_pro + default "asus/p8h61-m_pro" config MAINBOARD_PART_NUMBER string diff --git a/src/mainboard/bap/ode_e20XX/Kconfig b/src/mainboard/bap/ode_e20XX/Kconfig index 0c37d5f390..1d526399f1 100644 --- a/src/mainboard/bap/ode_e20XX/Kconfig +++ b/src/mainboard/bap/ode_e20XX/Kconfig @@ -31,7 +31,7 @@ config BOARD_SPECIFIC_OPTIONS config MAINBOARD_DIR string - default bap/ode_e20XX + default "bap/ode_e20XX" config MAINBOARD_PART_NUMBER string diff --git a/src/mainboard/bap/ode_e21XX/Kconfig b/src/mainboard/bap/ode_e21XX/Kconfig index 3bdb573386..bf812f26ea 100644 --- a/src/mainboard/bap/ode_e21XX/Kconfig +++ b/src/mainboard/bap/ode_e21XX/Kconfig @@ -31,7 +31,7 @@ config BOARD_SPECIFIC_OPTIONS config MAINBOARD_DIR string - default bap/ode_e21XX + default "bap/ode_e21XX" config MAINBOARD_PART_NUMBER string diff --git a/src/mainboard/biostar/a68n_5200/Kconfig b/src/mainboard/biostar/a68n_5200/Kconfig index f5f23382e1..e4271d34fe 100644 --- a/src/mainboard/biostar/a68n_5200/Kconfig +++ b/src/mainboard/biostar/a68n_5200/Kconfig @@ -32,7 +32,7 @@ config BOARD_SPECIFIC_OPTIONS config MAINBOARD_DIR string - default biostar/a68n_5200 + default "biostar/a68n_5200" config MAINBOARD_PART_NUMBER string diff --git a/src/mainboard/biostar/am1ml/Kconfig b/src/mainboard/biostar/am1ml/Kconfig index a981787a60..31aa5f061b 100644 --- a/src/mainboard/biostar/am1ml/Kconfig +++ b/src/mainboard/biostar/am1ml/Kconfig @@ -33,7 +33,7 @@ config BOARD_SPECIFIC_OPTIONS config MAINBOARD_DIR string - default biostar/am1ml + default "biostar/am1ml" config MAINBOARD_PART_NUMBER string diff --git a/src/mainboard/compulab/intense_pc/Kconfig b/src/mainboard/compulab/intense_pc/Kconfig index 3326b74bf6..68a01f18bc 100644 --- a/src/mainboard/compulab/intense_pc/Kconfig +++ b/src/mainboard/compulab/intense_pc/Kconfig @@ -18,7 +18,7 @@ config BOARD_SPECIFIC_OPTIONS config MAINBOARD_DIR string - default compulab/intense_pc + default "compulab/intense_pc" config MAINBOARD_PART_NUMBER string diff --git a/src/mainboard/elmex/pcm205400/Kconfig b/src/mainboard/elmex/pcm205400/Kconfig index 850361ad90..7dc67d17ea 100644 --- a/src/mainboard/elmex/pcm205400/Kconfig +++ b/src/mainboard/elmex/pcm205400/Kconfig @@ -43,7 +43,7 @@ config BOARD_SPECIFIC_OPTIONS config MAINBOARD_DIR string - default elmex/pcm205400 + default "elmex/pcm205400" config HW_MEM_HOLE_SIZEK hex diff --git a/src/mainboard/emulation/qemu-aarch64/Kconfig b/src/mainboard/emulation/qemu-aarch64/Kconfig index ebdbf16e8c..895446ddd7 100644 --- a/src/mainboard/emulation/qemu-aarch64/Kconfig +++ b/src/mainboard/emulation/qemu-aarch64/Kconfig @@ -30,7 +30,7 @@ config BOARD_SPECIFIC_OPTIONS config MAINBOARD_DIR string - default emulation/qemu-aarch64 + default "emulation/qemu-aarch64" config MAINBOARD_PART_NUMBER string diff --git a/src/mainboard/emulation/qemu-armv7/Kconfig b/src/mainboard/emulation/qemu-armv7/Kconfig index 73b2d5dede..181f9a45a9 100644 --- a/src/mainboard/emulation/qemu-armv7/Kconfig +++ b/src/mainboard/emulation/qemu-armv7/Kconfig @@ -39,7 +39,7 @@ config BOARD_SPECIFIC_OPTIONS config MAINBOARD_DIR string - default emulation/qemu-armv7 + default "emulation/qemu-armv7" config MAINBOARD_PART_NUMBER string diff --git a/src/mainboard/emulation/qemu-i440fx/Kconfig b/src/mainboard/emulation/qemu-i440fx/Kconfig index 8632ef67c2..3c27b1e963 100644 --- a/src/mainboard/emulation/qemu-i440fx/Kconfig +++ b/src/mainboard/emulation/qemu-i440fx/Kconfig @@ -42,7 +42,7 @@ config VBOOT_VBNV_OFFSET config MAINBOARD_DIR string - default emulation/qemu-i440fx + default "emulation/qemu-i440fx" config MAINBOARD_PART_NUMBER string diff --git a/src/mainboard/emulation/qemu-q35/Kconfig b/src/mainboard/emulation/qemu-q35/Kconfig index 8b97495180..3a9bb6f04e 100644 --- a/src/mainboard/emulation/qemu-q35/Kconfig +++ b/src/mainboard/emulation/qemu-q35/Kconfig @@ -41,7 +41,7 @@ config VBOOT_VBNV_OFFSET config MAINBOARD_DIR string - default emulation/qemu-q35 + default "emulation/qemu-q35" config MAINBOARD_PART_NUMBER string diff --git a/src/mainboard/emulation/qemu-riscv/Kconfig b/src/mainboard/emulation/qemu-riscv/Kconfig index fa6dccc94c..4d4c900138 100644 --- a/src/mainboard/emulation/qemu-riscv/Kconfig +++ b/src/mainboard/emulation/qemu-riscv/Kconfig @@ -44,7 +44,7 @@ config BOARD_SPECIFIC_OPTIONS config MAINBOARD_DIR string - default emulation/qemu-riscv + default "emulation/qemu-riscv" config MAINBOARD_PART_NUMBER string diff --git a/src/mainboard/emulation/spike-riscv/Kconfig b/src/mainboard/emulation/spike-riscv/Kconfig index 03046f723f..2fe0e1798f 100644 --- a/src/mainboard/emulation/spike-riscv/Kconfig +++ b/src/mainboard/emulation/spike-riscv/Kconfig @@ -25,7 +25,7 @@ config BOARD_SPECIFIC_OPTIONS config MAINBOARD_DIR string - default emulation/spike-riscv + default "emulation/spike-riscv" config MAINBOARD_PART_NUMBER string diff --git a/src/mainboard/emulation/spike-riscv/Kconfig.name b/src/mainboard/emulation/spike-riscv/Kconfig.name index 17549c6ebb..0c0205dce6 100644 --- a/src/mainboard/emulation/spike-riscv/Kconfig.name +++ b/src/mainboard/emulation/spike-riscv/Kconfig.name @@ -1,3 +1,2 @@ config BOARD_EMULATION_SPIKE_RISCV bool "SPIKE riscv" - help diff --git a/src/mainboard/facebook/fbg1701/Kconfig b/src/mainboard/facebook/fbg1701/Kconfig index c92626b7fa..dc8dc26c81 100644 --- a/src/mainboard/facebook/fbg1701/Kconfig +++ b/src/mainboard/facebook/fbg1701/Kconfig @@ -42,7 +42,7 @@ config ONBOARD_SAMSUNG_MEM config MAINBOARD_DIR string - default facebook/fbg1701 + default "facebook/fbg1701" config MAINBOARD_PART_NUMBER string diff --git a/src/mainboard/foxconn/d41s/Kconfig b/src/mainboard/foxconn/d41s/Kconfig index 56ab34f8fd..4805fe0fd4 100644 --- a/src/mainboard/foxconn/d41s/Kconfig +++ b/src/mainboard/foxconn/d41s/Kconfig @@ -37,7 +37,7 @@ config MAX_CPUS config MAINBOARD_DIR string - default foxconn/d41s + default "foxconn/d41s" config MAINBOARD_PART_NUMBER string diff --git a/src/mainboard/getac/p470/Kconfig b/src/mainboard/getac/p470/Kconfig index f1c7d4550d..7394ea4c14 100644 --- a/src/mainboard/getac/p470/Kconfig +++ b/src/mainboard/getac/p470/Kconfig @@ -36,7 +36,7 @@ config BOARD_SPECIFIC_OPTIONS config MAINBOARD_DIR string - default getac/p470 + default "getac/p470" config MAINBOARD_PART_NUMBER string diff --git a/src/mainboard/gigabyte/ga-945gcm-s2l/Kconfig b/src/mainboard/gigabyte/ga-945gcm-s2l/Kconfig index e9ed54d828..3c373a767b 100644 --- a/src/mainboard/gigabyte/ga-945gcm-s2l/Kconfig +++ b/src/mainboard/gigabyte/ga-945gcm-s2l/Kconfig @@ -35,7 +35,7 @@ config BOARD_SPECIFIC_OPTIONS config MAINBOARD_DIR string - default gigabyte/ga-945gcm-s2l + default "gigabyte/ga-945gcm-s2l" config VARIANT_DIR string diff --git a/src/mainboard/gigabyte/ga-b75m-d3h/Kconfig b/src/mainboard/gigabyte/ga-b75m-d3h/Kconfig index ceb2dbc85f..64d9cc526e 100644 --- a/src/mainboard/gigabyte/ga-b75m-d3h/Kconfig +++ b/src/mainboard/gigabyte/ga-b75m-d3h/Kconfig @@ -28,7 +28,7 @@ config USBDEBUG_HCD_INDEX config MAINBOARD_DIR string - default gigabyte/ga-b75m-d3h + default "gigabyte/ga-b75m-d3h" config VARIANT_DIR string diff --git a/src/mainboard/gizmosphere/gizmo/Kconfig b/src/mainboard/gizmosphere/gizmo/Kconfig index 51f7fa0d5d..e195e8f0a2 100644 --- a/src/mainboard/gizmosphere/gizmo/Kconfig +++ b/src/mainboard/gizmosphere/gizmo/Kconfig @@ -31,7 +31,7 @@ config BOARD_SPECIFIC_OPTIONS config MAINBOARD_DIR string - default gizmosphere/gizmo + default "gizmosphere/gizmo" config MAINBOARD_PART_NUMBER string diff --git a/src/mainboard/gizmosphere/gizmo2/Kconfig b/src/mainboard/gizmosphere/gizmo2/Kconfig index 94158baa7a..034b6eeaf3 100644 --- a/src/mainboard/gizmosphere/gizmo2/Kconfig +++ b/src/mainboard/gizmosphere/gizmo2/Kconfig @@ -32,7 +32,7 @@ config BOARD_SPECIFIC_OPTIONS config MAINBOARD_DIR string - default gizmosphere/gizmo2 + default "gizmosphere/gizmo2" config MAINBOARD_PART_NUMBER string diff --git a/src/mainboard/google/auron/Kconfig b/src/mainboard/google/auron/Kconfig index b4ef3a83ac..b64b47eb70 100644 --- a/src/mainboard/google/auron/Kconfig +++ b/src/mainboard/google/auron/Kconfig @@ -27,7 +27,7 @@ config VBOOT config MAINBOARD_DIR string - default google/auron + default "google/auron" config VARIANT_DIR string diff --git a/src/mainboard/google/beltino/Kconfig b/src/mainboard/google/beltino/Kconfig index 9de141f539..4b18c8cfea 100644 --- a/src/mainboard/google/beltino/Kconfig +++ b/src/mainboard/google/beltino/Kconfig @@ -20,7 +20,7 @@ config VBOOT config MAINBOARD_DIR string - default google/beltino + default "google/beltino" config VARIANT_DIR string diff --git a/src/mainboard/google/butterfly/Kconfig b/src/mainboard/google/butterfly/Kconfig index 76bcc3d3b0..92fc236f9b 100644 --- a/src/mainboard/google/butterfly/Kconfig +++ b/src/mainboard/google/butterfly/Kconfig @@ -26,7 +26,7 @@ config VBOOT config MAINBOARD_DIR string - default google/butterfly + default "google/butterfly" config MAINBOARD_PART_NUMBER string diff --git a/src/mainboard/google/cheza/Kconfig b/src/mainboard/google/cheza/Kconfig index ce69fe07e7..30218ccb44 100644 --- a/src/mainboard/google/cheza/Kconfig +++ b/src/mainboard/google/cheza/Kconfig @@ -25,7 +25,7 @@ config VBOOT config MAINBOARD_DIR string - default google/cheza + default "google/cheza" config MAINBOARD_VENDOR string diff --git a/src/mainboard/google/cyan/Kconfig b/src/mainboard/google/cyan/Kconfig index 647d4e9026..bb5ffb692a 100644 --- a/src/mainboard/google/cyan/Kconfig +++ b/src/mainboard/google/cyan/Kconfig @@ -34,7 +34,7 @@ config DISPLAY_SPD_DATA config MAINBOARD_DIR string - default google/cyan + default "google/cyan" config MAINBOARD_FAMILY string diff --git a/src/mainboard/google/daisy/Kconfig b/src/mainboard/google/daisy/Kconfig index ec09d5e199..f15bd9b864 100644 --- a/src/mainboard/google/daisy/Kconfig +++ b/src/mainboard/google/daisy/Kconfig @@ -36,7 +36,7 @@ config VBOOT config MAINBOARD_DIR string - default google/daisy + default "google/daisy" config MAINBOARD_PART_NUMBER string diff --git a/src/mainboard/google/foster/Kconfig b/src/mainboard/google/foster/Kconfig index 6157519434..eefc2c085b 100644 --- a/src/mainboard/google/foster/Kconfig +++ b/src/mainboard/google/foster/Kconfig @@ -32,7 +32,7 @@ config VBOOT config MAINBOARD_DIR string - default google/foster + default "google/foster" config MAINBOARD_PART_NUMBER string diff --git a/src/mainboard/google/gale/Kconfig b/src/mainboard/google/gale/Kconfig index 5e00be0ef4..81aaabf452 100644 --- a/src/mainboard/google/gale/Kconfig +++ b/src/mainboard/google/gale/Kconfig @@ -41,7 +41,7 @@ config BOARD_VARIANT_DK01 config MAINBOARD_DIR string - default google/gale + default "google/gale" config MAINBOARD_PART_NUMBER string diff --git a/src/mainboard/google/gru/Kconfig b/src/mainboard/google/gru/Kconfig index e7db1858db..72003e0d06 100644 --- a/src/mainboard/google/gru/Kconfig +++ b/src/mainboard/google/gru/Kconfig @@ -67,7 +67,7 @@ config VBOOT config MAINBOARD_DIR string - default google/gru + default "google/gru" config MAINBOARD_VENDOR string diff --git a/src/mainboard/google/jecht/Kconfig b/src/mainboard/google/jecht/Kconfig index 041ffcebc8..41727c56a7 100644 --- a/src/mainboard/google/jecht/Kconfig +++ b/src/mainboard/google/jecht/Kconfig @@ -20,7 +20,7 @@ config VBOOT config MAINBOARD_DIR string - default google/jecht + default "google/jecht" config VARIANT_DIR diff --git a/src/mainboard/google/kahlee/Kconfig b/src/mainboard/google/kahlee/Kconfig index a83b07a6b7..8632553256 100644 --- a/src/mainboard/google/kahlee/Kconfig +++ b/src/mainboard/google/kahlee/Kconfig @@ -50,7 +50,7 @@ if BOARD_GOOGLE_BASEBOARD_KAHLEE config MAINBOARD_DIR string - default google/kahlee + default "google/kahlee" config VGA_BIOS_FILE string diff --git a/src/mainboard/google/kukui/Kconfig b/src/mainboard/google/kukui/Kconfig index c5c7a86d7e..098ce494ab 100644 --- a/src/mainboard/google/kukui/Kconfig +++ b/src/mainboard/google/kukui/Kconfig @@ -46,7 +46,7 @@ config BOARD_SPECIFIC_OPTIONS config MAINBOARD_DIR string - default google/kukui + default "google/kukui" config MAINBOARD_PART_NUMBER string diff --git a/src/mainboard/google/link/Kconfig b/src/mainboard/google/link/Kconfig index 12c5ffeb38..4a32ac2055 100644 --- a/src/mainboard/google/link/Kconfig +++ b/src/mainboard/google/link/Kconfig @@ -26,7 +26,7 @@ config VBOOT config MAINBOARD_DIR string - default google/link + default "google/link" config MAINBOARD_PART_NUMBER string diff --git a/src/mainboard/google/mistral/Kconfig b/src/mainboard/google/mistral/Kconfig index d6f9b169a3..88e67097ba 100644 --- a/src/mainboard/google/mistral/Kconfig +++ b/src/mainboard/google/mistral/Kconfig @@ -22,7 +22,7 @@ config VBOOT config MAINBOARD_DIR string - default google/mistral + default "google/mistral" config MAINBOARD_VENDOR string diff --git a/src/mainboard/google/nyan/Kconfig b/src/mainboard/google/nyan/Kconfig index 5ad945e12d..c6175452c2 100644 --- a/src/mainboard/google/nyan/Kconfig +++ b/src/mainboard/google/nyan/Kconfig @@ -35,7 +35,7 @@ config VBOOT config MAINBOARD_DIR string - default google/nyan + default "google/nyan" config MAINBOARD_PART_NUMBER string diff --git a/src/mainboard/google/nyan_big/Kconfig b/src/mainboard/google/nyan_big/Kconfig index bef25577a9..f02f694d55 100644 --- a/src/mainboard/google/nyan_big/Kconfig +++ b/src/mainboard/google/nyan_big/Kconfig @@ -37,7 +37,7 @@ config VBOOT config MAINBOARD_DIR string - default google/nyan_big + default "google/nyan_big" config MAINBOARD_PART_NUMBER string diff --git a/src/mainboard/google/nyan_blaze/Kconfig b/src/mainboard/google/nyan_blaze/Kconfig index cb001538c9..8de957d9f2 100644 --- a/src/mainboard/google/nyan_blaze/Kconfig +++ b/src/mainboard/google/nyan_blaze/Kconfig @@ -37,7 +37,7 @@ config VBOOT config MAINBOARD_DIR string - default google/nyan_blaze + default "google/nyan_blaze" config MAINBOARD_PART_NUMBER string diff --git a/src/mainboard/google/oak/Kconfig b/src/mainboard/google/oak/Kconfig index f943a4f437..264f3711e3 100644 --- a/src/mainboard/google/oak/Kconfig +++ b/src/mainboard/google/oak/Kconfig @@ -50,7 +50,7 @@ config VBOOT config MAINBOARD_DIR string - default google/oak + default "google/oak" config MAINBOARD_VENDOR string diff --git a/src/mainboard/google/octopus/Kconfig b/src/mainboard/google/octopus/Kconfig index d712600158..1177cd50f6 100644 --- a/src/mainboard/google/octopus/Kconfig +++ b/src/mainboard/google/octopus/Kconfig @@ -48,7 +48,7 @@ config CHROMEOS config MAINBOARD_DIR string - default google/octopus + default "google/octopus" config VARIANT_DIR string diff --git a/src/mainboard/google/parrot/Kconfig b/src/mainboard/google/parrot/Kconfig index daf605d436..0169beaf3f 100644 --- a/src/mainboard/google/parrot/Kconfig +++ b/src/mainboard/google/parrot/Kconfig @@ -27,7 +27,7 @@ config VBOOT config MAINBOARD_DIR string - default google/parrot + default "google/parrot" config MAINBOARD_PART_NUMBER string diff --git a/src/mainboard/google/peach_pit/Kconfig b/src/mainboard/google/peach_pit/Kconfig index fc2ceb83ad..b0b4d233bb 100644 --- a/src/mainboard/google/peach_pit/Kconfig +++ b/src/mainboard/google/peach_pit/Kconfig @@ -34,7 +34,7 @@ config VBOOT config MAINBOARD_DIR string - default google/peach_pit + default "google/peach_pit" config MAINBOARD_PART_NUMBER string diff --git a/src/mainboard/google/rambi/Kconfig b/src/mainboard/google/rambi/Kconfig index 83bcc1a2ee..fc6e28e519 100644 --- a/src/mainboard/google/rambi/Kconfig +++ b/src/mainboard/google/rambi/Kconfig @@ -23,7 +23,7 @@ config VBOOT config MAINBOARD_DIR string - default google/rambi + default "google/rambi" config VARIANT_DIR string diff --git a/src/mainboard/google/reef/Kconfig b/src/mainboard/google/reef/Kconfig index 520b78819f..5d782b1cef 100644 --- a/src/mainboard/google/reef/Kconfig +++ b/src/mainboard/google/reef/Kconfig @@ -48,7 +48,7 @@ config VBOOT config MAINBOARD_DIR string - default google/reef + default "google/reef" config VARIANT_DIR string diff --git a/src/mainboard/google/slippy/Kconfig b/src/mainboard/google/slippy/Kconfig index 13dbe19577..94ade7a546 100644 --- a/src/mainboard/google/slippy/Kconfig +++ b/src/mainboard/google/slippy/Kconfig @@ -28,7 +28,7 @@ config VBOOT config MAINBOARD_DIR string - default google/slippy + default "google/slippy" config VARIANT_DIR string diff --git a/src/mainboard/google/smaug/Kconfig b/src/mainboard/google/smaug/Kconfig index 2b9be0262a..fa08251b24 100644 --- a/src/mainboard/google/smaug/Kconfig +++ b/src/mainboard/google/smaug/Kconfig @@ -38,7 +38,7 @@ config VBOOT config MAINBOARD_DIR string - default google/smaug + default "google/smaug" config MAINBOARD_PART_NUMBER string diff --git a/src/mainboard/google/storm/Kconfig b/src/mainboard/google/storm/Kconfig index 3abea56c86..0bd8f5aad1 100644 --- a/src/mainboard/google/storm/Kconfig +++ b/src/mainboard/google/storm/Kconfig @@ -39,7 +39,7 @@ config BOARD_VARIANT_AP148 config MAINBOARD_DIR string - default google/storm + default "google/storm" config MAINBOARD_PART_NUMBER string diff --git a/src/mainboard/google/stout/Kconfig b/src/mainboard/google/stout/Kconfig index dfe687b0ff..a77964b8f8 100644 --- a/src/mainboard/google/stout/Kconfig +++ b/src/mainboard/google/stout/Kconfig @@ -25,7 +25,7 @@ config VBOOT config MAINBOARD_DIR string - default google/stout + default "google/stout" config MAINBOARD_PART_NUMBER string diff --git a/src/mainboard/google/trogdor/Kconfig b/src/mainboard/google/trogdor/Kconfig index 56b3a729c2..fba6b17667 100644 --- a/src/mainboard/google/trogdor/Kconfig +++ b/src/mainboard/google/trogdor/Kconfig @@ -25,7 +25,7 @@ config VBOOT config MAINBOARD_DIR string - default google/trogdor + default "google/trogdor" config MAINBOARD_VENDOR string diff --git a/src/mainboard/google/veyron/Kconfig b/src/mainboard/google/veyron/Kconfig index 8e29661929..5d1e616911 100644 --- a/src/mainboard/google/veyron/Kconfig +++ b/src/mainboard/google/veyron/Kconfig @@ -47,7 +47,7 @@ config VBOOT config MAINBOARD_DIR string - default google/veyron + default "google/veyron" config MAINBOARD_PART_NUMBER string diff --git a/src/mainboard/google/veyron_mickey/Kconfig b/src/mainboard/google/veyron_mickey/Kconfig index 876d70ea2b..5d15f0ec77 100644 --- a/src/mainboard/google/veyron_mickey/Kconfig +++ b/src/mainboard/google/veyron_mickey/Kconfig @@ -32,7 +32,7 @@ config VBOOT config MAINBOARD_DIR string - default google/veyron_mickey + default "google/veyron_mickey" config MAINBOARD_PART_NUMBER string diff --git a/src/mainboard/google/veyron_rialto/Kconfig b/src/mainboard/google/veyron_rialto/Kconfig index 4550c5b822..ac6f382054 100644 --- a/src/mainboard/google/veyron_rialto/Kconfig +++ b/src/mainboard/google/veyron_rialto/Kconfig @@ -32,7 +32,7 @@ config VBOOT config MAINBOARD_DIR string - default google/veyron_rialto + default "google/veyron_rialto" config MAINBOARD_PART_NUMBER string diff --git a/src/mainboard/hp/2570p/Kconfig b/src/mainboard/hp/2570p/Kconfig index 5e33aac2c2..a014b0cfc4 100644 --- a/src/mainboard/hp/2570p/Kconfig +++ b/src/mainboard/hp/2570p/Kconfig @@ -35,7 +35,7 @@ config BOARD_SPECIFIC_OPTIONS config MAINBOARD_DIR string - default hp/2570p + default "hp/2570p" config MAINBOARD_PART_NUMBER string diff --git a/src/mainboard/hp/2760p/Kconfig b/src/mainboard/hp/2760p/Kconfig index ab298369e1..935064c15d 100644 --- a/src/mainboard/hp/2760p/Kconfig +++ b/src/mainboard/hp/2760p/Kconfig @@ -35,7 +35,7 @@ config BOARD_SPECIFIC_OPTIONS config MAINBOARD_DIR string - default hp/2760p + default "hp/2760p" config MAINBOARD_PART_NUMBER string diff --git a/src/mainboard/hp/8460p/Kconfig b/src/mainboard/hp/8460p/Kconfig index ca97cd69f6..08e21fdd20 100644 --- a/src/mainboard/hp/8460p/Kconfig +++ b/src/mainboard/hp/8460p/Kconfig @@ -38,7 +38,7 @@ config BOARD_SPECIFIC_OPTIONS config MAINBOARD_DIR string - default hp/8460p + default "hp/8460p" config MAINBOARD_PART_NUMBER string diff --git a/src/mainboard/hp/8470p/Kconfig b/src/mainboard/hp/8470p/Kconfig index 5b30208b64..e084d00baa 100644 --- a/src/mainboard/hp/8470p/Kconfig +++ b/src/mainboard/hp/8470p/Kconfig @@ -36,7 +36,7 @@ config BOARD_SPECIFIC_OPTIONS config MAINBOARD_DIR string - default hp/8470p + default "hp/8470p" config MAINBOARD_PART_NUMBER string diff --git a/src/mainboard/hp/8770w/Kconfig b/src/mainboard/hp/8770w/Kconfig index 41e2ed3c6b..80f9199afc 100644 --- a/src/mainboard/hp/8770w/Kconfig +++ b/src/mainboard/hp/8770w/Kconfig @@ -35,7 +35,7 @@ config BOARD_SPECIFIC_OPTIONS config MAINBOARD_DIR string - default hp/8770w + default "hp/8770w" config MAINBOARD_PART_NUMBER string diff --git a/src/mainboard/hp/abm/Kconfig b/src/mainboard/hp/abm/Kconfig index 43cf67f2a6..5ba1b5b857 100644 --- a/src/mainboard/hp/abm/Kconfig +++ b/src/mainboard/hp/abm/Kconfig @@ -30,7 +30,7 @@ config BOARD_SPECIFIC_OPTIONS config MAINBOARD_DIR string - default hp/abm + default "hp/abm" config MAINBOARD_PART_NUMBER string diff --git a/src/mainboard/hp/compaq_8200_elite_sff/Kconfig b/src/mainboard/hp/compaq_8200_elite_sff/Kconfig index cbfb0ed387..42efd4a925 100644 --- a/src/mainboard/hp/compaq_8200_elite_sff/Kconfig +++ b/src/mainboard/hp/compaq_8200_elite_sff/Kconfig @@ -21,7 +21,7 @@ config BOARD_SPECIFIC_OPTIONS config MAINBOARD_DIR string - default hp/compaq_8200_elite_sff + default "hp/compaq_8200_elite_sff" config MAINBOARD_PART_NUMBER string diff --git a/src/mainboard/hp/folio_9470m/Kconfig b/src/mainboard/hp/folio_9470m/Kconfig index d9bb68e7e1..8759192954 100644 --- a/src/mainboard/hp/folio_9470m/Kconfig +++ b/src/mainboard/hp/folio_9470m/Kconfig @@ -21,7 +21,7 @@ config BOARD_SPECIFIC_OPTIONS config MAINBOARD_DIR string - default hp/folio_9470m + default "hp/folio_9470m" config MAINBOARD_PART_NUMBER string diff --git a/src/mainboard/hp/pavilion_m6_1035dx/Kconfig b/src/mainboard/hp/pavilion_m6_1035dx/Kconfig index 7fa04ee46d..3c67e2ad07 100644 --- a/src/mainboard/hp/pavilion_m6_1035dx/Kconfig +++ b/src/mainboard/hp/pavilion_m6_1035dx/Kconfig @@ -35,7 +35,7 @@ config BOARD_SPECIFIC_OPTIONS config MAINBOARD_DIR string - default hp/pavilion_m6_1035dx + default "hp/pavilion_m6_1035dx" config MAINBOARD_PART_NUMBER string diff --git a/src/mainboard/hp/revolve_810_g1/Kconfig b/src/mainboard/hp/revolve_810_g1/Kconfig index ce7364ce5e..26e645fb90 100644 --- a/src/mainboard/hp/revolve_810_g1/Kconfig +++ b/src/mainboard/hp/revolve_810_g1/Kconfig @@ -23,7 +23,7 @@ config BOARD_SPECIFIC_OPTIONS config MAINBOARD_DIR string - default hp/revolve_810_g1 + default "hp/revolve_810_g1" config MAINBOARD_PART_NUMBER string diff --git a/src/mainboard/hp/z220_sff_workstation/Kconfig b/src/mainboard/hp/z220_sff_workstation/Kconfig index 4598de2040..649cbb136b 100644 --- a/src/mainboard/hp/z220_sff_workstation/Kconfig +++ b/src/mainboard/hp/z220_sff_workstation/Kconfig @@ -32,7 +32,7 @@ config VBOOT_VBNV_OFFSET config MAINBOARD_DIR string - default hp/z220_sff_workstation + default "hp/z220_sff_workstation" config MAINBOARD_PART_NUMBER string diff --git a/src/mainboard/ibase/mb899/Kconfig b/src/mainboard/ibase/mb899/Kconfig index fcc2e38751..d93121dc2d 100644 --- a/src/mainboard/ibase/mb899/Kconfig +++ b/src/mainboard/ibase/mb899/Kconfig @@ -18,7 +18,7 @@ config BOARD_SPECIFIC_OPTIONS config MAINBOARD_DIR string - default ibase/mb899 + default "ibase/mb899" config MAINBOARD_PART_NUMBER string diff --git a/src/mainboard/intel/apollolake_rvp/Kconfig b/src/mainboard/intel/apollolake_rvp/Kconfig index ed7d77f211..391ce1f494 100644 --- a/src/mainboard/intel/apollolake_rvp/Kconfig +++ b/src/mainboard/intel/apollolake_rvp/Kconfig @@ -9,7 +9,7 @@ config BOARD_SPECIFIC_OPTIONS config MAINBOARD_DIR string - default intel/apollolake_rvp + default "intel/apollolake_rvp" config MAINBOARD_PART_NUMBER string diff --git a/src/mainboard/intel/baskingridge/Kconfig b/src/mainboard/intel/baskingridge/Kconfig index d5dafa0616..8268891186 100644 --- a/src/mainboard/intel/baskingridge/Kconfig +++ b/src/mainboard/intel/baskingridge/Kconfig @@ -18,7 +18,7 @@ config VBOOT config MAINBOARD_DIR string - default intel/baskingridge + default "intel/baskingridge" config MAINBOARD_PART_NUMBER string diff --git a/src/mainboard/intel/d510mo/Kconfig b/src/mainboard/intel/d510mo/Kconfig index 153c1131a9..003e009733 100644 --- a/src/mainboard/intel/d510mo/Kconfig +++ b/src/mainboard/intel/d510mo/Kconfig @@ -36,7 +36,7 @@ config MAX_CPUS config MAINBOARD_DIR string - default intel/d510mo + default "intel/d510mo" config MAINBOARD_PART_NUMBER string diff --git a/src/mainboard/intel/d945gclf/Kconfig b/src/mainboard/intel/d945gclf/Kconfig index 46d82ec5f7..683ea2de06 100644 --- a/src/mainboard/intel/d945gclf/Kconfig +++ b/src/mainboard/intel/d945gclf/Kconfig @@ -33,7 +33,7 @@ config BOARD_SPECIFIC_OPTIONS config MAINBOARD_DIR string - default intel/d945gclf + default "intel/d945gclf" config MAINBOARD_PART_NUMBER string diff --git a/src/mainboard/intel/dcp847ske/Kconfig b/src/mainboard/intel/dcp847ske/Kconfig index b1c7bab07d..9bf9e52e0c 100644 --- a/src/mainboard/intel/dcp847ske/Kconfig +++ b/src/mainboard/intel/dcp847ske/Kconfig @@ -27,7 +27,7 @@ endmenu config MAINBOARD_DIR string - default intel/dcp847ske + default "intel/dcp847ske" config MAINBOARD_PART_NUMBER string diff --git a/src/mainboard/intel/emeraldlake2/Kconfig b/src/mainboard/intel/emeraldlake2/Kconfig index 61dd1b0f3d..c37da039fc 100644 --- a/src/mainboard/intel/emeraldlake2/Kconfig +++ b/src/mainboard/intel/emeraldlake2/Kconfig @@ -19,7 +19,7 @@ config VBOOT config MAINBOARD_DIR string - default intel/emeraldlake2 + default "intel/emeraldlake2" config MAINBOARD_PART_NUMBER string diff --git a/src/mainboard/intel/galileo/Kconfig b/src/mainboard/intel/galileo/Kconfig index 84f09c4f82..2e855da87a 100644 --- a/src/mainboard/intel/galileo/Kconfig +++ b/src/mainboard/intel/galileo/Kconfig @@ -28,7 +28,7 @@ config BOARD_SPECIFIC_OPTIONS config MAINBOARD_DIR string - default intel/galileo + default "intel/galileo" config MAINBOARD_PART_NUMBER string diff --git a/src/mainboard/intel/glkrvp/Kconfig b/src/mainboard/intel/glkrvp/Kconfig index ebb5a3a07b..8ed2afff3a 100644 --- a/src/mainboard/intel/glkrvp/Kconfig +++ b/src/mainboard/intel/glkrvp/Kconfig @@ -50,7 +50,7 @@ config VBOOT config MAINBOARD_DIR string - default intel/glkrvp + default "intel/glkrvp" config VARIANT_DIR string diff --git a/src/mainboard/intel/harcuvar/Kconfig b/src/mainboard/intel/harcuvar/Kconfig index 9d43b11e07..e3cd86e8f7 100644 --- a/src/mainboard/intel/harcuvar/Kconfig +++ b/src/mainboard/intel/harcuvar/Kconfig @@ -23,7 +23,7 @@ config BOARD_SPECIFIC_OPTIONS config MAINBOARD_DIR string - default intel/harcuvar + default "intel/harcuvar" config MAINBOARD_PART_NUMBER string diff --git a/src/mainboard/intel/leafhill/Kconfig b/src/mainboard/intel/leafhill/Kconfig index e89d892631..5832570b54 100644 --- a/src/mainboard/intel/leafhill/Kconfig +++ b/src/mainboard/intel/leafhill/Kconfig @@ -9,7 +9,7 @@ config BOARD_SPECIFIC_OPTIONS config MAINBOARD_DIR string - default intel/leafhill + default "intel/leafhill" config MAINBOARD_PART_NUMBER string diff --git a/src/mainboard/intel/minnow3/Kconfig b/src/mainboard/intel/minnow3/Kconfig index 2dea6b40cc..8d95a35d8d 100644 --- a/src/mainboard/intel/minnow3/Kconfig +++ b/src/mainboard/intel/minnow3/Kconfig @@ -9,7 +9,7 @@ config BOARD_SPECIFIC_OPTIONS config MAINBOARD_DIR string - default intel/minnow3 + default "intel/minnow3" config MAINBOARD_PART_NUMBER string diff --git a/src/mainboard/intel/strago/Kconfig b/src/mainboard/intel/strago/Kconfig index 5a49e8cc0a..246add1895 100644 --- a/src/mainboard/intel/strago/Kconfig +++ b/src/mainboard/intel/strago/Kconfig @@ -24,7 +24,7 @@ config VBOOT config MAINBOARD_DIR string - default intel/strago + default "intel/strago" config MAINBOARD_PART_NUMBER string diff --git a/src/mainboard/intel/wtm2/Kconfig b/src/mainboard/intel/wtm2/Kconfig index 27545fec05..2f6b21e9ce 100644 --- a/src/mainboard/intel/wtm2/Kconfig +++ b/src/mainboard/intel/wtm2/Kconfig @@ -19,7 +19,7 @@ config VBOOT config MAINBOARD_DIR string - default intel/wtm2 + default "intel/wtm2" config MAINBOARD_PART_NUMBER string diff --git a/src/mainboard/jetway/nf81-t56n-lf/Kconfig b/src/mainboard/jetway/nf81-t56n-lf/Kconfig index 6cc06c22b4..d2dda6725f 100644 --- a/src/mainboard/jetway/nf81-t56n-lf/Kconfig +++ b/src/mainboard/jetway/nf81-t56n-lf/Kconfig @@ -32,7 +32,7 @@ config BOARD_SPECIFIC_OPTIONS config MAINBOARD_DIR string - default jetway/nf81-t56n-lf + default "jetway/nf81-t56n-lf" config MAINBOARD_PART_NUMBER string diff --git a/src/mainboard/kontron/986lcd-m/Kconfig b/src/mainboard/kontron/986lcd-m/Kconfig index 5584eb3111..1ccdf1a185 100644 --- a/src/mainboard/kontron/986lcd-m/Kconfig +++ b/src/mainboard/kontron/986lcd-m/Kconfig @@ -20,7 +20,7 @@ config BOARD_SPECIFIC_OPTIONS config MAINBOARD_DIR string - default kontron/986lcd-m + default "kontron/986lcd-m" config MAINBOARD_PART_NUMBER string diff --git a/src/mainboard/kontron/ktqm77/Kconfig b/src/mainboard/kontron/ktqm77/Kconfig index c215bdf65b..1cefa599b4 100644 --- a/src/mainboard/kontron/ktqm77/Kconfig +++ b/src/mainboard/kontron/ktqm77/Kconfig @@ -17,7 +17,7 @@ config BOARD_SPECIFIC_OPTIONS config MAINBOARD_DIR string - default kontron/ktqm77 + default "kontron/ktqm77" config MAINBOARD_PART_NUMBER string diff --git a/src/mainboard/lenovo/g505s/Kconfig b/src/mainboard/lenovo/g505s/Kconfig index b80019ecf4..a277145f2c 100644 --- a/src/mainboard/lenovo/g505s/Kconfig +++ b/src/mainboard/lenovo/g505s/Kconfig @@ -33,7 +33,7 @@ config BOARD_SPECIFIC_OPTIONS config MAINBOARD_DIR string - default lenovo/g505s + default "lenovo/g505s" config MAINBOARD_PART_NUMBER string diff --git a/src/mainboard/lenovo/l520/Kconfig b/src/mainboard/lenovo/l520/Kconfig index 4495d79bb2..a300d167de 100644 --- a/src/mainboard/lenovo/l520/Kconfig +++ b/src/mainboard/lenovo/l520/Kconfig @@ -20,7 +20,7 @@ config BOARD_SPECIFIC_OPTIONS config MAINBOARD_DIR string - default lenovo/l520 + default "lenovo/l520" config MAINBOARD_PART_NUMBER string diff --git a/src/mainboard/lenovo/s230u/Kconfig b/src/mainboard/lenovo/s230u/Kconfig index c7faebb429..662c9a5ad3 100644 --- a/src/mainboard/lenovo/s230u/Kconfig +++ b/src/mainboard/lenovo/s230u/Kconfig @@ -22,7 +22,7 @@ config BOARD_SPECIFIC_OPTIONS config MAINBOARD_DIR string - default lenovo/s230u + default "lenovo/s230u" config MAINBOARD_PART_NUMBER string diff --git a/src/mainboard/lenovo/t400/Kconfig b/src/mainboard/lenovo/t400/Kconfig index a68d1fa13e..9355540713 100644 --- a/src/mainboard/lenovo/t400/Kconfig +++ b/src/mainboard/lenovo/t400/Kconfig @@ -47,7 +47,7 @@ config FMDFILE config MAINBOARD_DIR string - default lenovo/t400 + default "lenovo/t400" config VARIANT_DIR string diff --git a/src/mainboard/lenovo/t410/Kconfig b/src/mainboard/lenovo/t410/Kconfig index 329d08de26..943bf43e0a 100644 --- a/src/mainboard/lenovo/t410/Kconfig +++ b/src/mainboard/lenovo/t410/Kconfig @@ -44,7 +44,7 @@ config FMDFILE config MAINBOARD_DIR string - default lenovo/t410 + default "lenovo/t410" config MAINBOARD_PART_NUMBER string diff --git a/src/mainboard/lenovo/t420/Kconfig b/src/mainboard/lenovo/t420/Kconfig index 5148604a68..d26ad1714b 100644 --- a/src/mainboard/lenovo/t420/Kconfig +++ b/src/mainboard/lenovo/t420/Kconfig @@ -49,7 +49,7 @@ config FMDFILE config MAINBOARD_DIR string - default lenovo/t420 + default "lenovo/t420" config MAINBOARD_PART_NUMBER string diff --git a/src/mainboard/lenovo/t420s/Kconfig b/src/mainboard/lenovo/t420s/Kconfig index 190f35e4b5..89f84fccd8 100644 --- a/src/mainboard/lenovo/t420s/Kconfig +++ b/src/mainboard/lenovo/t420s/Kconfig @@ -48,7 +48,7 @@ config FMDFILE config MAINBOARD_DIR string - default lenovo/t420s + default "lenovo/t420s" config MAINBOARD_PART_NUMBER string diff --git a/src/mainboard/lenovo/t430/Kconfig b/src/mainboard/lenovo/t430/Kconfig index 7137b5eb73..78da38502b 100644 --- a/src/mainboard/lenovo/t430/Kconfig +++ b/src/mainboard/lenovo/t430/Kconfig @@ -28,7 +28,7 @@ config BOARD_SPECIFIC_OPTIONS config MAINBOARD_DIR string - default lenovo/t430 + default "lenovo/t430" config MAINBOARD_PART_NUMBER string diff --git a/src/mainboard/lenovo/t430s/Kconfig b/src/mainboard/lenovo/t430s/Kconfig index 0c7d0756ba..36f03ae468 100644 --- a/src/mainboard/lenovo/t430s/Kconfig +++ b/src/mainboard/lenovo/t430s/Kconfig @@ -29,7 +29,7 @@ config BOARD_SPECIFIC_OPTIONS config MAINBOARD_DIR string - default lenovo/t430s + default "lenovo/t430s" config VARIANT_DIR string diff --git a/src/mainboard/lenovo/t440p/Kconfig b/src/mainboard/lenovo/t440p/Kconfig index bf821f3d0c..faaa73a78c 100644 --- a/src/mainboard/lenovo/t440p/Kconfig +++ b/src/mainboard/lenovo/t440p/Kconfig @@ -25,7 +25,7 @@ config BOARD_SPECIFIC_OPTIONS config MAINBOARD_DIR string - default lenovo/t440p + default "lenovo/t440p" config MAINBOARD_PART_NUMBER string diff --git a/src/mainboard/lenovo/t520/Kconfig b/src/mainboard/lenovo/t520/Kconfig index d4934d6685..a6183d9f08 100644 --- a/src/mainboard/lenovo/t520/Kconfig +++ b/src/mainboard/lenovo/t520/Kconfig @@ -49,7 +49,7 @@ config VARIANT_DIR config MAINBOARD_DIR string - default lenovo/t520 + default "lenovo/t520" config DEVICETREE string diff --git a/src/mainboard/lenovo/t530/Kconfig b/src/mainboard/lenovo/t530/Kconfig index f63a12054f..d1ba6a8fd0 100644 --- a/src/mainboard/lenovo/t530/Kconfig +++ b/src/mainboard/lenovo/t530/Kconfig @@ -35,7 +35,7 @@ config VARIANT_DIR config MAINBOARD_DIR string - default lenovo/t530 + default "lenovo/t530" config DEVICETREE string diff --git a/src/mainboard/lenovo/t60/Kconfig b/src/mainboard/lenovo/t60/Kconfig index 436b035a1e..58d41a6b57 100644 --- a/src/mainboard/lenovo/t60/Kconfig +++ b/src/mainboard/lenovo/t60/Kconfig @@ -25,7 +25,7 @@ config BOARD_SPECIFIC_OPTIONS config MAINBOARD_DIR string - default lenovo/t60 + default "lenovo/t60" config VARIANT_DIR string diff --git a/src/mainboard/lenovo/x131e/Kconfig b/src/mainboard/lenovo/x131e/Kconfig index e7da8d0d77..2cf3a8f95d 100644 --- a/src/mainboard/lenovo/x131e/Kconfig +++ b/src/mainboard/lenovo/x131e/Kconfig @@ -23,7 +23,7 @@ config BOARD_SPECIFIC_OPTIONS config MAINBOARD_DIR string - default lenovo/x131e + default "lenovo/x131e" config MAINBOARD_PART_NUMBER string diff --git a/src/mainboard/lenovo/x1_carbon_gen1/Kconfig b/src/mainboard/lenovo/x1_carbon_gen1/Kconfig index a15cadf202..91ba20817c 100644 --- a/src/mainboard/lenovo/x1_carbon_gen1/Kconfig +++ b/src/mainboard/lenovo/x1_carbon_gen1/Kconfig @@ -28,7 +28,7 @@ config BOARD_SPECIFIC_OPTIONS config MAINBOARD_DIR string - default lenovo/x1_carbon_gen1 + default "lenovo/x1_carbon_gen1" config MAINBOARD_PART_NUMBER string diff --git a/src/mainboard/lenovo/x200/Kconfig b/src/mainboard/lenovo/x200/Kconfig index 5e88c21c2f..432c805078 100644 --- a/src/mainboard/lenovo/x200/Kconfig +++ b/src/mainboard/lenovo/x200/Kconfig @@ -44,7 +44,7 @@ config FMDFILE config MAINBOARD_DIR string - default lenovo/x200 + default "lenovo/x200" config VARIANT_DIR string diff --git a/src/mainboard/lenovo/x201/Kconfig b/src/mainboard/lenovo/x201/Kconfig index e40c0d3e41..a94d24ed75 100644 --- a/src/mainboard/lenovo/x201/Kconfig +++ b/src/mainboard/lenovo/x201/Kconfig @@ -44,7 +44,7 @@ config FMDFILE config MAINBOARD_DIR string - default lenovo/x201 + default "lenovo/x201" config MAINBOARD_PART_NUMBER string diff --git a/src/mainboard/lenovo/x220/Kconfig b/src/mainboard/lenovo/x220/Kconfig index c80c2520b2..b20255e1cc 100644 --- a/src/mainboard/lenovo/x220/Kconfig +++ b/src/mainboard/lenovo/x220/Kconfig @@ -43,7 +43,7 @@ config VBOOT_VBNV_OFFSET config MAINBOARD_DIR string - default lenovo/x220 + default "lenovo/x220" config VARIANT_DIR string diff --git a/src/mainboard/lenovo/x230/Kconfig b/src/mainboard/lenovo/x230/Kconfig index a043efcd70..e7edf6bb61 100644 --- a/src/mainboard/lenovo/x230/Kconfig +++ b/src/mainboard/lenovo/x230/Kconfig @@ -29,7 +29,7 @@ config BOARD_SPECIFIC_OPTIONS config MAINBOARD_DIR string - default lenovo/x230 + default "lenovo/x230" config MAINBOARD_PART_NUMBER string diff --git a/src/mainboard/lenovo/x60/Kconfig b/src/mainboard/lenovo/x60/Kconfig index a1a5fec7c0..1815892d4a 100644 --- a/src/mainboard/lenovo/x60/Kconfig +++ b/src/mainboard/lenovo/x60/Kconfig @@ -28,7 +28,7 @@ config BOARD_SPECIFIC_OPTIONS config MAINBOARD_DIR string - default lenovo/x60 + default "lenovo/x60" config MAINBOARD_PART_NUMBER string diff --git a/src/mainboard/lippert/frontrunner-af/Kconfig b/src/mainboard/lippert/frontrunner-af/Kconfig index f8a3f3a2ec..92d77434f5 100644 --- a/src/mainboard/lippert/frontrunner-af/Kconfig +++ b/src/mainboard/lippert/frontrunner-af/Kconfig @@ -33,7 +33,7 @@ config BOARD_SPECIFIC_OPTIONS config MAINBOARD_DIR string - default lippert/frontrunner-af + default "lippert/frontrunner-af" config MAINBOARD_PART_NUMBER string diff --git a/src/mainboard/lippert/toucan-af/Kconfig b/src/mainboard/lippert/toucan-af/Kconfig index 67efdfea9b..74b335a9fa 100644 --- a/src/mainboard/lippert/toucan-af/Kconfig +++ b/src/mainboard/lippert/toucan-af/Kconfig @@ -35,7 +35,7 @@ config BOARD_SPECIFIC_OPTIONS config MAINBOARD_DIR string - default lippert/toucan-af + default "lippert/toucan-af" config MAINBOARD_PART_NUMBER string diff --git a/src/mainboard/msi/ms7707/Kconfig b/src/mainboard/msi/ms7707/Kconfig index 4923bbfdea..c1a1b4c748 100644 --- a/src/mainboard/msi/ms7707/Kconfig +++ b/src/mainboard/msi/ms7707/Kconfig @@ -16,7 +16,7 @@ config BOARD_SPECIFIC_OPTIONS config MAINBOARD_DIR string - default msi/ms7707 + default "msi/ms7707" config MAINBOARD_PART_NUMBER string diff --git a/src/mainboard/msi/ms7721/Kconfig b/src/mainboard/msi/ms7721/Kconfig index 5fa4768083..1fee74790e 100644 --- a/src/mainboard/msi/ms7721/Kconfig +++ b/src/mainboard/msi/ms7721/Kconfig @@ -33,7 +33,7 @@ config BOARD_SPECIFIC_OPTIONS config MAINBOARD_DIR string - default msi/ms7721 + default "msi/ms7721" config MAINBOARD_PART_NUMBER string diff --git a/src/mainboard/packardbell/ms2290/Kconfig b/src/mainboard/packardbell/ms2290/Kconfig index a104fecd8c..6a613849ea 100644 --- a/src/mainboard/packardbell/ms2290/Kconfig +++ b/src/mainboard/packardbell/ms2290/Kconfig @@ -16,7 +16,7 @@ config BOARD_SPECIFIC_OPTIONS config MAINBOARD_DIR string - default packardbell/ms2290 + default "packardbell/ms2290" config MAINBOARD_PART_NUMBER string diff --git a/src/mainboard/pcengines/apu1/Kconfig b/src/mainboard/pcengines/apu1/Kconfig index 07aaa8c1b6..3396845559 100644 --- a/src/mainboard/pcengines/apu1/Kconfig +++ b/src/mainboard/pcengines/apu1/Kconfig @@ -35,7 +35,7 @@ config BOARD_SPECIFIC_OPTIONS config MAINBOARD_DIR string - default pcengines/apu1 + default "pcengines/apu1" config MAINBOARD_PART_NUMBER string diff --git a/src/mainboard/pcengines/apu2/Kconfig b/src/mainboard/pcengines/apu2/Kconfig index 6c3958b30e..0437c84d28 100644 --- a/src/mainboard/pcengines/apu2/Kconfig +++ b/src/mainboard/pcengines/apu2/Kconfig @@ -36,7 +36,7 @@ config BOARD_SPECIFIC_OPTIONS config MAINBOARD_DIR string - default pcengines/apu2 + default "pcengines/apu2" config VARIANT_DIR string diff --git a/src/mainboard/portwell/m107/Kconfig b/src/mainboard/portwell/m107/Kconfig index e5e3ff590a..a89daa1309 100644 --- a/src/mainboard/portwell/m107/Kconfig +++ b/src/mainboard/portwell/m107/Kconfig @@ -51,7 +51,7 @@ endchoice config MAINBOARD_DIR string - default portwell/m107 + default "portwell/m107" config MAINBOARD_PART_NUMBER string diff --git a/src/mainboard/purism/librem_bdw/Kconfig b/src/mainboard/purism/librem_bdw/Kconfig index 224bde0e67..466e03ec7a 100644 --- a/src/mainboard/purism/librem_bdw/Kconfig +++ b/src/mainboard/purism/librem_bdw/Kconfig @@ -40,7 +40,7 @@ config PCIEXP_AER config MAINBOARD_DIR string - default purism/librem_bdw + default "purism/librem_bdw" config MAINBOARD_VENDOR string diff --git a/src/mainboard/roda/rk886ex/Kconfig b/src/mainboard/roda/rk886ex/Kconfig index 563b77392e..9d08c96a03 100644 --- a/src/mainboard/roda/rk886ex/Kconfig +++ b/src/mainboard/roda/rk886ex/Kconfig @@ -22,7 +22,7 @@ config BOARD_SPECIFIC_OPTIONS config MAINBOARD_DIR string - default roda/rk886ex + default "roda/rk886ex" config MAINBOARD_PART_NUMBER string diff --git a/src/mainboard/roda/rk9/Kconfig b/src/mainboard/roda/rk9/Kconfig index fd29739701..7516255f5b 100644 --- a/src/mainboard/roda/rk9/Kconfig +++ b/src/mainboard/roda/rk9/Kconfig @@ -19,7 +19,7 @@ config BOARD_SPECIFIC_OPTIONS config MAINBOARD_DIR string - default roda/rk9 + default "roda/rk9" config MAINBOARD_PART_NUMBER string diff --git a/src/mainboard/samsung/lumpy/Kconfig b/src/mainboard/samsung/lumpy/Kconfig index 2d1544b12a..f87ba8f739 100644 --- a/src/mainboard/samsung/lumpy/Kconfig +++ b/src/mainboard/samsung/lumpy/Kconfig @@ -29,7 +29,7 @@ config VBOOT config MAINBOARD_DIR string - default samsung/lumpy + default "samsung/lumpy" config MAINBOARD_PART_NUMBER string diff --git a/src/mainboard/samsung/stumpy/Kconfig b/src/mainboard/samsung/stumpy/Kconfig index a2919f94e0..5deb0f0722 100644 --- a/src/mainboard/samsung/stumpy/Kconfig +++ b/src/mainboard/samsung/stumpy/Kconfig @@ -25,7 +25,7 @@ config VBOOT config MAINBOARD_DIR string - default samsung/stumpy + default "samsung/stumpy" config MAINBOARD_PART_NUMBER string diff --git a/src/mainboard/sapphire/pureplatinumh61/Kconfig b/src/mainboard/sapphire/pureplatinumh61/Kconfig index 6d27b3f1bd..0e289c18d4 100644 --- a/src/mainboard/sapphire/pureplatinumh61/Kconfig +++ b/src/mainboard/sapphire/pureplatinumh61/Kconfig @@ -18,7 +18,7 @@ config BOARD_SPECIFIC_OPTIONS config MAINBOARD_DIR string - default sapphire/pureplatinumh61 + default "sapphire/pureplatinumh61" config MAINBOARD_PART_NUMBER string diff --git a/src/mainboard/scaleway/tagada/Kconfig b/src/mainboard/scaleway/tagada/Kconfig index 9530505c42..25cb7e13d7 100644 --- a/src/mainboard/scaleway/tagada/Kconfig +++ b/src/mainboard/scaleway/tagada/Kconfig @@ -26,7 +26,7 @@ config BOARD_SPECIFIC_OPTIONS config MAINBOARD_DIR string - default scaleway/tagada + default "scaleway/tagada" config MAINBOARD_PART_NUMBER string diff --git a/src/mainboard/siemens/mc_apl1/Kconfig b/src/mainboard/siemens/mc_apl1/Kconfig index 0b8cff3318..52883b8bf5 100644 --- a/src/mainboard/siemens/mc_apl1/Kconfig +++ b/src/mainboard/siemens/mc_apl1/Kconfig @@ -13,7 +13,7 @@ if BOARD_SIEMENS_BASEBOARD_MC_APL1 config MAINBOARD_DIR string - default siemens/mc_apl1 + default "siemens/mc_apl1" config VARIANT_DIR string diff --git a/src/mainboard/sifive/hifive-unleashed/Kconfig b/src/mainboard/sifive/hifive-unleashed/Kconfig index fc9bc1eeb9..460fdfb234 100644 --- a/src/mainboard/sifive/hifive-unleashed/Kconfig +++ b/src/mainboard/sifive/hifive-unleashed/Kconfig @@ -26,7 +26,7 @@ config HEAP_SIZE config MAINBOARD_DIR string - default sifive/hifive-unleashed + default "sifive/hifive-unleashed" config MAINBOARD_PART_NUMBER string diff --git a/src/mainboard/ti/beaglebone/Kconfig b/src/mainboard/ti/beaglebone/Kconfig index 322ac0c296..70096229b9 100644 --- a/src/mainboard/ti/beaglebone/Kconfig +++ b/src/mainboard/ti/beaglebone/Kconfig @@ -23,7 +23,7 @@ config BOARD_SPECIFIC_OPTIONS config MAINBOARD_DIR string - default ti/beaglebone + default "ti/beaglebone" config MAINBOARD_PART_NUMBER string diff --git a/src/northbridge/amd/pi/Kconfig b/src/northbridge/amd/pi/Kconfig index 65c655689a..c0df2a1abd 100644 --- a/src/northbridge/amd/pi/Kconfig +++ b/src/northbridge/amd/pi/Kconfig @@ -41,9 +41,9 @@ config S3_VGA_ROM_RUN bool default n -source src/northbridge/amd/pi/00630F01/Kconfig -source src/northbridge/amd/pi/00730F01/Kconfig -source src/northbridge/amd/pi/00660F01/Kconfig +source "src/northbridge/amd/pi/00630F01/Kconfig" +source "src/northbridge/amd/pi/00730F01/Kconfig" +source "src/northbridge/amd/pi/00660F01/Kconfig" config HW_MEM_HOLE_SIZEK hex diff --git a/src/southbridge/amd/agesa/Kconfig b/src/southbridge/amd/agesa/Kconfig index e5bc990bf9..7162c27bff 100644 --- a/src/southbridge/amd/agesa/Kconfig +++ b/src/southbridge/amd/agesa/Kconfig @@ -13,4 +13,4 @@ # GNU General Public License for more details. # -source src/southbridge/amd/agesa/hudson/Kconfig +source "src/southbridge/amd/agesa/hudson/Kconfig" diff --git a/src/southbridge/amd/cimx/Kconfig b/src/southbridge/amd/cimx/Kconfig index 62a717be54..3e12327708 100644 --- a/src/southbridge/amd/cimx/Kconfig +++ b/src/southbridge/amd/cimx/Kconfig @@ -17,4 +17,4 @@ config AMD_SB_CIMX bool default n -source src/southbridge/amd/cimx/sb800/Kconfig +source "src/southbridge/amd/cimx/sb800/Kconfig" diff --git a/src/southbridge/amd/pi/Kconfig b/src/southbridge/amd/pi/Kconfig index 2fb509c7eb..531b460ea5 100644 --- a/src/southbridge/amd/pi/Kconfig +++ b/src/southbridge/amd/pi/Kconfig @@ -13,4 +13,4 @@ # GNU General Public License for more details. # -source src/southbridge/amd/pi/hudson/Kconfig +source "src/southbridge/amd/pi/hudson/Kconfig" diff --git a/src/vendorcode/amd/Kconfig b/src/vendorcode/amd/Kconfig index 44b3940fa7..10a49473a1 100644 --- a/src/vendorcode/amd/Kconfig +++ b/src/vendorcode/amd/Kconfig @@ -44,7 +44,7 @@ config CPU_AMD_AGESA_OPENSOURCE endchoice if CPU_AMD_AGESA_BINARY_PI -source src/vendorcode/amd/pi/Kconfig +source "src/vendorcode/amd/pi/Kconfig" endif config AGESA_EXTRA_TIMESTAMPS diff --git a/src/vendorcode/eltan/security/Kconfig b/src/vendorcode/eltan/security/Kconfig index 1cc0365720..9a89381d73 100644 --- a/src/vendorcode/eltan/security/Kconfig +++ b/src/vendorcode/eltan/security/Kconfig @@ -19,8 +19,8 @@ if USE_VENDORCODE_ELTAN menu "Eltan Security Settings" -source src/vendorcode/eltan/security/mboot/Kconfig -source src/vendorcode/eltan/security/verified_boot/Kconfig +source "src/vendorcode/eltan/security/mboot/Kconfig" +source "src/vendorcode/eltan/security/verified_boot/Kconfig" endmenu diff --git a/src/vendorcode/google/Kconfig b/src/vendorcode/google/Kconfig index fcb28dfc97..498d0edb08 100644 --- a/src/vendorcode/google/Kconfig +++ b/src/vendorcode/google/Kconfig @@ -12,7 +12,7 @@ ## GNU General Public License for more details. ## -source src/vendorcode/google/chromeos/Kconfig +source "src/vendorcode/google/chromeos/Kconfig" config GOOGLE_SMBIOS_MAINBOARD_VERSION bool From d64b04609d34e272cb06e9c8f27f4321558e8330 Mon Sep 17 00:00:00 2001 From: rkanabar Date: Fri, 30 Aug 2019 11:40:08 +0530 Subject: [PATCH 0356/1242] util/ifdtool: Add Jasperlake platform support under IFDv2 Change-Id: I4963ab249a8e0b31c014e92edf1e0a4a4f638084 Signed-off-by: rkanabar Reviewed-on: https://review.coreboot.org/c/coreboot/+/37111 Reviewed-by: Subrata Banik Reviewed-by: V Sowmya Reviewed-by: Aamir Bohra Tested-by: build bot (Jenkins) --- util/ifdtool/ifdtool.c | 3 +++ util/ifdtool/ifdtool.h | 1 + 2 files changed, 4 insertions(+) diff --git a/util/ifdtool/ifdtool.c b/util/ifdtool/ifdtool.c index a6d0ffa778..a59f36b886 100644 --- a/util/ifdtool/ifdtool.c +++ b/util/ifdtool/ifdtool.c @@ -217,6 +217,7 @@ static int is_platform_ifd_2(void) PLATFORM_CNL, PLATFORM_ICL, PLATFORM_TGL, + PLATFORM_JSL, }; unsigned int i; @@ -1637,6 +1638,8 @@ int main(int argc, char *argv[]) platform = PLATFORM_GLK; } else if (!strcmp(optarg, "icl")) { platform = PLATFORM_ICL; + } else if (!strcmp(optarg, "jsl")) { + platform = PLATFORM_JSL; } else if (!strcmp(optarg, "sklkbl")) { platform = PLATFORM_SKLKBL; } else if (!strcmp(optarg, "tgl")) { diff --git a/util/ifdtool/ifdtool.h b/util/ifdtool/ifdtool.h index 2f5b3c3f2e..aecd8fa643 100644 --- a/util/ifdtool/ifdtool.h +++ b/util/ifdtool/ifdtool.h @@ -57,6 +57,7 @@ enum platform { PLATFORM_CNL, PLATFORM_GLK, PLATFORM_ICL, + PLATFORM_JSL, PLATFORM_SKLKBL, PLATFORM_TGL, }; From 21c9aa125cffbc6458b7c4f442927e372da7aefb Mon Sep 17 00:00:00 2001 From: Arthur Heymans Date: Wed, 20 Nov 2019 12:24:25 +0100 Subject: [PATCH 0357/1242] sb/intel/i82801ix: Update comment on default decoded IO ranges Now the comment matches what is programmed into LPC_EN. Change-Id: Ia01cf4bd068a593fc91e9ac12d0adf42d4ee937b Signed-off-by: Arthur Heymans Reviewed-on: https://review.coreboot.org/c/coreboot/+/36995 Reviewed-by: Patrick Rudolph Tested-by: build bot (Jenkins) --- src/southbridge/intel/i82801ix/early_init.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/src/southbridge/intel/i82801ix/early_init.c b/src/southbridge/intel/i82801ix/early_init.c index 51ce9e859e..92db7d833c 100644 --- a/src/southbridge/intel/i82801ix/early_init.c +++ b/src/southbridge/intel/i82801ix/early_init.c @@ -76,6 +76,8 @@ void i82801ix_lpc_decode(void) * - 0x378-0x37f and 0x778-0x77f LPT * - 0x2f8-0x2ff COMB * - 0x3f8-0x3ff COMA + * - 0x208-0x20f GAMEH + * - 0x200-0x207 GAMEL */ pci_write_config16(d31f0, D31F0_LPC_IODEC, 0x0010); pci_write_config16(d31f0, D31F0_LPC_EN, 0x3f0f); From cc6809c8b1b5f726c8541b9c4bc33dcbe2536172 Mon Sep 17 00:00:00 2001 From: Patrick Georgi Date: Sat, 23 Nov 2019 11:13:46 +0100 Subject: [PATCH 0358/1242] mb/google/octopus: disable fmap cache for all octopus devices Meep was just the first one to fail, but the others aren't any better. Change-Id: I177c50cfe7593a5b2ad770ce1ab1191d2dff93d2 Signed-off-by: Patrick Georgi Reviewed-on: https://review.coreboot.org/c/coreboot/+/37163 Reviewed-by: Arthur Heymans Tested-by: build bot (Jenkins) --- src/mainboard/google/octopus/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/mainboard/google/octopus/Kconfig b/src/mainboard/google/octopus/Kconfig index 1177cd50f6..65a641b1e6 100644 --- a/src/mainboard/google/octopus/Kconfig +++ b/src/mainboard/google/octopus/Kconfig @@ -22,7 +22,7 @@ config BOARD_GOOGLE_BASEBOARD_OCTOPUS select MAINBOARD_HAS_SPI_TPM_CR50 select MAINBOARD_HAS_TPM2 select GOOGLE_SMBIOS_MAINBOARD_VERSION - select NO_FMAP_CACHE if BOARD_GOOGLE_MEEP + select NO_FMAP_CACHE if BOARD_GOOGLE_BASEBOARD_OCTOPUS From 878b68581405fc221b6da37b898c28f63f62c359 Mon Sep 17 00:00:00 2001 From: Elyes HAOUAS Date: Fri, 18 Oct 2019 19:52:22 +0200 Subject: [PATCH 0359/1242] soc/intel/broadwell: Fix 'dead increment' Dead increment spotted out using clang-tools. Change-Id: Icfab0b9ce97722fe97a0306cb45fbc2bd072bad6 Signed-off-by: Elyes HAOUAS Reviewed-on: https://review.coreboot.org/c/coreboot/+/36130 Tested-by: build bot (Jenkins) Reviewed-by: Angel Pons --- src/soc/intel/broadwell/sata.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/src/soc/intel/broadwell/sata.c b/src/soc/intel/broadwell/sata.c index e47a78de6c..f4773e186b 100644 --- a/src/soc/intel/broadwell/sata.c +++ b/src/soc/intel/broadwell/sata.c @@ -75,8 +75,7 @@ static void sata_init(struct device *dev) pci_write_config32(dev, 0x98, reg32); /* Setup register 9Ch */ - reg16 = 0; /* Disable alternate ID */ - reg16 = 1 << 5; /* BWG step 12 */ + reg16 = (1 << 5); /* BWG step 12 */ pci_write_config16(dev, 0x9c, reg16); /* SATA Initialization register */ From 689256797e0dc157046888f83bf64ae410df7f14 Mon Sep 17 00:00:00 2001 From: Arthur Heymans Date: Fri, 22 Nov 2019 23:06:33 +0100 Subject: [PATCH 0360/1242] Drop superfluous C_ENVIRONMENT_BOOTBLOCK checks MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Some guarding is not needed because the linker drops the code, other guarding is not needed because all platforms using the code now have C_ENVIRONMENT_BOOTBLOCK. Change-Id: I3b1a94e709aa291e1156c854874d7bf461981f32 Signed-off-by: Arthur Heymans Reviewed-on: https://review.coreboot.org/c/coreboot/+/37157 Tested-by: build bot (Jenkins) Reviewed-by: HAOUAS Elyes Reviewed-by: Kyösti Mälkki --- src/cpu/intel/model_1067x/Kconfig | 2 +- src/cpu/intel/model_6fx/Kconfig | 2 +- src/cpu/intel/socket_LGA775/Makefile.inc | 4 ---- src/mainboard/facebook/fbg1701/Makefile.inc | 4 ++-- src/mainboard/portwell/m107/Makefile.inc | 2 +- src/vendorcode/eltan/security/verified_boot/Makefile.inc | 2 +- 6 files changed, 6 insertions(+), 10 deletions(-) diff --git a/src/cpu/intel/model_1067x/Kconfig b/src/cpu/intel/model_1067x/Kconfig index 564a428bbc..79dda288b6 100644 --- a/src/cpu/intel/model_1067x/Kconfig +++ b/src/cpu/intel/model_1067x/Kconfig @@ -12,4 +12,4 @@ config CPU_INTEL_MODEL_1067X select SUPPORT_CPU_UCODE_IN_CBFS select CPU_INTEL_COMMON select CPU_INTEL_COMMON_TIMEBASE - select SETUP_XIP_CACHE if C_ENVIRONMENT_BOOTBLOCK + select SETUP_XIP_CACHE diff --git a/src/cpu/intel/model_6fx/Kconfig b/src/cpu/intel/model_6fx/Kconfig index cfd3e7c6e0..e3d327ca02 100644 --- a/src/cpu/intel/model_6fx/Kconfig +++ b/src/cpu/intel/model_6fx/Kconfig @@ -13,4 +13,4 @@ config CPU_INTEL_MODEL_6FX select SUPPORT_CPU_UCODE_IN_CBFS select CPU_INTEL_COMMON select CPU_INTEL_COMMON_TIMEBASE - select SETUP_XIP_CACHE if C_ENVIRONMENT_BOOTBLOCK + select SETUP_XIP_CACHE diff --git a/src/cpu/intel/socket_LGA775/Makefile.inc b/src/cpu/intel/socket_LGA775/Makefile.inc index a7984a9dfb..2f1c6b49ea 100644 --- a/src/cpu/intel/socket_LGA775/Makefile.inc +++ b/src/cpu/intel/socket_LGA775/Makefile.inc @@ -13,13 +13,9 @@ subdirs-y += ../microcode subdirs-y += ../hyperthreading subdirs-y += ../speedstep -ifneq ($(CONFIG_C_ENVIRONMENT_BOOTBLOCK),y) -cpu_incs-y += $(src)/cpu/intel/car/p4-netburst/cache_as_ram.S -else bootblock-y += ../car/p4-netburst/cache_as_ram.S bootblock-y += ../car/bootblock.c bootblock-y += ../../x86/early_reset.S -endif postcar-y += ../car/p4-netburst/exit_car.S diff --git a/src/mainboard/facebook/fbg1701/Makefile.inc b/src/mainboard/facebook/fbg1701/Makefile.inc index ac4e571653..07b3e351af 100644 --- a/src/mainboard/facebook/fbg1701/Makefile.inc +++ b/src/mainboard/facebook/fbg1701/Makefile.inc @@ -16,13 +16,13 @@ ## ifneq ($(filter y,$(CONFIG_VENDORCODE_ELTAN_VBOOT) $(CONFIG_VENDORCODE_ELTAN_MBOOT)),) -bootblock-$(CONFIG_C_ENVIRONMENT_BOOTBLOCK) += board_verified_boot.c +bootblock-y += board_verified_boot.c postcar-y += board_verified_boot.c ramstage-y += board_verified_boot.c romstage-y += board_verified_boot.c endif -bootblock-$(CONFIG_C_ENVIRONMENT_BOOTBLOCK) += com_init.c +bootblock-y += com_init.c ramstage-y += cpld.c ramstage-y += gpio.c diff --git a/src/mainboard/portwell/m107/Makefile.inc b/src/mainboard/portwell/m107/Makefile.inc index 7d4725efe4..5d88549ab5 100644 --- a/src/mainboard/portwell/m107/Makefile.inc +++ b/src/mainboard/portwell/m107/Makefile.inc @@ -15,7 +15,7 @@ ## GNU General Public License for more details. ## -bootblock-$(CONFIG_C_ENVIRONMENT_BOOTBLOCK) += com_init.c +bootblock-y += com_init.c ramstage-y += gpio.c ramstage-y += hda_verb.c diff --git a/src/vendorcode/eltan/security/verified_boot/Makefile.inc b/src/vendorcode/eltan/security/verified_boot/Makefile.inc index 357e520298..97d8f81c91 100644 --- a/src/vendorcode/eltan/security/verified_boot/Makefile.inc +++ b/src/vendorcode/eltan/security/verified_boot/Makefile.inc @@ -17,7 +17,7 @@ ifneq ($(filter y,$(CONFIG_VENDORCODE_ELTAN_VBOOT) $(CONFIG_VENDORCODE_ELTAN_MBO CPPFLAGS_common += -I$(src)/security/vboot -bootblock-$(CONFIG_C_ENVIRONMENT_BOOTBLOCK) += vboot_check.c +bootblock-y += vboot_check.c postcar-y += vboot_check.c romstage-y += vboot_check.c ramstage-y += vboot_check.c From c05b1a66b320ab0341aae16c217316bec4092f5e Mon Sep 17 00:00:00 2001 From: Arthur Heymans Date: Fri, 22 Nov 2019 21:01:30 +0100 Subject: [PATCH 0361/1242] Kconfig: Drop the C_ENVIRONMENT_BOOTBLOCK symbol MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The romcc bootblock will be deprecated soon and most platforms use C_ENVIRONMENT_BOOTBLOCK already. This patch drops the CONFIG_C_ENVIRONMENT_BOOTBLOCK symbol and adds CONFIG_ROMCC_BOOTBLOCK where needed. Change-Id: I773a76aade623303b7cd95ebe9b0411e5a7ecbaf Signed-off-by: Arthur Heymans Reviewed-on: https://review.coreboot.org/c/coreboot/+/37154 Tested-by: build bot (Jenkins) Reviewed-by: HAOUAS Elyes Reviewed-by: Kyösti Mälkki Reviewed-by: Michał Żygowski --- src/Kconfig | 4 +--- src/arch/arm/Kconfig | 1 - src/arch/arm64/Kconfig | 1 - src/arch/ppc64/Kconfig | 1 - src/arch/riscv/Kconfig | 1 - src/arch/x86/Kconfig | 8 ++++---- src/arch/x86/Makefile.inc | 10 ++++++---- src/arch/x86/assembly_entry.S | 11 +++++------ src/arch/x86/bootblock_crt0.S | 3 +-- src/arch/x86/bootblock_romcc.S | 2 +- src/arch/x86/car.ld | 6 +++--- src/arch/x86/include/arch/cpu.h | 5 ++--- src/arch/x86/memlayout.ld | 3 +-- src/console/Kconfig | 2 +- src/cpu/intel/car/non-evict/cache_as_ram.S | 2 +- src/cpu/intel/car/p3/cache_as_ram.S | 2 +- src/cpu/intel/car/romstage.c | 4 ++-- src/cpu/intel/microcode/Kconfig | 2 +- src/cpu/intel/model_206ax/Kconfig | 1 - src/cpu/intel/slot_1/Kconfig | 1 + src/cpu/intel/socket_mPGA604/Kconfig | 1 - src/cpu/qemu-x86/Kconfig | 1 - src/cpu/x86/16bit/entry16.inc | 2 +- src/cpu/x86/Kconfig | 2 +- src/lib/Makefile.inc | 4 +++- src/northbridge/amd/agesa/Kconfig | 1 + src/northbridge/amd/pi/Kconfig | 1 + src/northbridge/intel/gm45/Kconfig | 1 - src/northbridge/intel/haswell/Kconfig | 1 - src/northbridge/intel/i945/Kconfig | 1 - src/northbridge/intel/nehalem/Kconfig | 1 - src/northbridge/intel/pineview/Kconfig | 1 - src/northbridge/intel/x4x/Kconfig | 1 - src/security/vboot/Kconfig | 2 +- src/soc/amd/picasso/Kconfig | 2 -- src/soc/amd/stoneyridge/Kconfig | 2 -- src/soc/intel/apollolake/Kconfig | 1 - src/soc/intel/baytrail/Kconfig | 1 + src/soc/intel/braswell/Kconfig | 1 - src/soc/intel/broadwell/Kconfig | 1 - src/soc/intel/cannonlake/Kconfig | 1 - src/soc/intel/denverton_ns/Kconfig | 1 - src/soc/intel/icelake/Kconfig | 1 - src/soc/intel/quark/Kconfig | 6 ------ src/soc/intel/skylake/Kconfig | 1 - src/soc/intel/tigerlake/Kconfig | 1 - .../eltan/security/verified_boot/vboot_check.c | 2 +- 47 files changed, 41 insertions(+), 70 deletions(-) diff --git a/src/Kconfig b/src/Kconfig index 8df5323cf6..2e06299af3 100644 --- a/src/Kconfig +++ b/src/Kconfig @@ -1177,9 +1177,7 @@ config BOOTBLOCK_CUSTOM # src/lib/bootblock.c#main() C entry point. bool -config C_ENVIRONMENT_BOOTBLOCK - # To be selected by arch or platform if a C environment is available during the - # bootblock. Normally this signifies availability of RW memory (e.g. SRAM). +config ROMCC_BOOTBLOCK bool ############################################################################### diff --git a/src/arch/arm/Kconfig b/src/arch/arm/Kconfig index 1eed2de4d0..ed838a5b2b 100644 --- a/src/arch/arm/Kconfig +++ b/src/arch/arm/Kconfig @@ -4,7 +4,6 @@ config ARCH_ARM config ARCH_BOOTBLOCK_ARM bool select ARCH_ARM - select C_ENVIRONMENT_BOOTBLOCK config ARCH_VERSTAGE_ARM bool diff --git a/src/arch/arm64/Kconfig b/src/arch/arm64/Kconfig index 96a23dc41b..588e8cea6d 100644 --- a/src/arch/arm64/Kconfig +++ b/src/arch/arm64/Kconfig @@ -4,7 +4,6 @@ config ARCH_ARM64 config ARCH_BOOTBLOCK_ARM64 bool select ARCH_ARM64 - select C_ENVIRONMENT_BOOTBLOCK config ARCH_VERSTAGE_ARM64 bool diff --git a/src/arch/ppc64/Kconfig b/src/arch/ppc64/Kconfig index 0699e910ce..44dbb1d778 100644 --- a/src/arch/ppc64/Kconfig +++ b/src/arch/ppc64/Kconfig @@ -5,7 +5,6 @@ config ARCH_BOOTBLOCK_PPC64 bool select ARCH_PPC64 select BOOTBLOCK_CUSTOM - select C_ENVIRONMENT_BOOTBLOCK config ARCH_VERSTAGE_PPC64 bool diff --git a/src/arch/riscv/Kconfig b/src/arch/riscv/Kconfig index f2ca571c97..8369afee6d 100644 --- a/src/arch/riscv/Kconfig +++ b/src/arch/riscv/Kconfig @@ -77,7 +77,6 @@ config ARCH_RISCV_PMP config ARCH_BOOTBLOCK_RISCV bool default n - select C_ENVIRONMENT_BOOTBLOCK config ARCH_VERSTAGE_RISCV bool diff --git a/src/arch/x86/Kconfig b/src/arch/x86/Kconfig index 24a2065c0e..a788bc0e23 100644 --- a/src/arch/x86/Kconfig +++ b/src/arch/x86/Kconfig @@ -23,7 +23,7 @@ config ARCH_BOOTBLOCK_X86_32 bool default n select ARCH_X86 - select BOOTBLOCK_CUSTOM if !C_ENVIRONMENT_BOOTBLOCK + select BOOTBLOCK_CUSTOM if ROMCC_BOOTBLOCK config ARCH_VERSTAGE_X86_32 bool @@ -47,7 +47,7 @@ config ARCH_BOOTBLOCK_X86_64 bool default n select ARCH_X86 - select BOOTBLOCK_CUSTOM if !C_ENVIRONMENT_BOOTBLOCK + select BOOTBLOCK_CUSTOM if ROMCC_BOOTBLOCK config ARCH_VERSTAGE_X86_64 bool @@ -199,7 +199,7 @@ config ID_SECTION_OFFSET hex default 0x80 -# 64KiB default bootblock size when employing C_ENVIRONMENT_BOOTBLOCK. +# 64KiB default bootblock size config C_ENV_BOOTBLOCK_SIZE hex default 0x10000 @@ -239,7 +239,7 @@ config ROMSTAGE_DEBUG_SPINLOOP choice prompt "Bootblock behaviour" default BOOTBLOCK_SIMPLE - depends on !C_ENVIRONMENT_BOOTBLOCK + depends on ROMCC_BOOTBLOCK config BOOTBLOCK_SIMPLE bool "Always load fallback" diff --git a/src/arch/x86/Makefile.inc b/src/arch/x86/Makefile.inc index 6f47e884a4..423c35116b 100644 --- a/src/arch/x86/Makefile.inc +++ b/src/arch/x86/Makefile.inc @@ -116,7 +116,7 @@ bootblock-$(CONFIG_X86_TOP4G_BOOTMEDIA_MAP) += mmap_boot.c bootblock-y += id.S $(call src-to-obj,bootblock,$(dir)/id.S): $(obj)/build.h -ifeq ($(CONFIG_C_ENVIRONMENT_BOOTBLOCK),y) +ifneq ($(CONFIG_ROMCC_BOOTBLOCK),y) bootblock-y += bootblock_crt0.S @@ -128,7 +128,7 @@ endif bootblock-$(CONFIG_ARCH_BOOTBLOCK_X86_32) += walkcbfs.S -else # !C_ENVIRONMENT_BOOTBLOCK +else # ROMCC_BOOTBLOCK # x86-specific linker flags ifeq ($(CONFIG_ARCH_BOOTBLOCK_X86_32),y) @@ -178,7 +178,7 @@ $(objcbfs)/bootblock.debug: $$(bootblock-objs) $(filter-out %.ld,$(bootblock-objs)) \ -T $(call src-to-obj,bootblock,src/arch/x86/bootblock.ld) -endif # C_ENVIRONMENT_BOOTBLOCK +endif # ROMCC_BOOTBLOCK endif # CONFIG_ARCH_BOOTBLOCK_X86_32 / CONFIG_ARCH_BOOTBLOCK_X86_64 @@ -223,7 +223,9 @@ ifeq ($(CONFIG_ARCH_ROMSTAGE_X86_32)$(CONFIG_ARCH_ROMSTAGE_X86_64),y) romstage-$(CONFIG_HAVE_ACPI_RESUME) += acpi_s3.c # gdt_init.S is included by entry32.inc when romstage is the first C # environment. -romstage-$(CONFIG_C_ENVIRONMENT_BOOTBLOCK) += gdt_init.S +ifneq ($(CONFIG_ROMCC_BOOTBLOCK),y) +romstage-y += gdt_init.S +endif romstage-y += cbmem.c romstage-$(CONFIG_IDT_IN_EVERY_STAGE) += exception.c romstage-$(CONFIG_IDT_IN_EVERY_STAGE) += idt.S diff --git a/src/arch/x86/assembly_entry.S b/src/arch/x86/assembly_entry.S index d9d6d4ecef..9d6f5a42b4 100644 --- a/src/arch/x86/assembly_entry.S +++ b/src/arch/x86/assembly_entry.S @@ -13,14 +13,13 @@ #include -#if CONFIG(C_ENVIRONMENT_BOOTBLOCK) +#if !CONFIG(ROMCC_BOOTBLOCK) /* - * This path is for stages that are post bootblock when employing - * CONFIG_C_ENVIRONMENT_BOOTBLOCK. The gdt is reloaded to accommodate - * platforms that are executing out of CAR. In order to continue with - * C code execution one needs to set stack pointer and clear CAR_GLOBAL - * variables that are stage specific. + * This path is for stages that are post bootblock. The gdt is reloaded + * to accommodate platforms that are executing out of CAR. In order to + * continue with C code execution one needs to set stack pointer and + * clear .bss variables that are stage specific. */ .section ".text._start", "ax", @progbits .global _start diff --git a/src/arch/x86/bootblock_crt0.S b/src/arch/x86/bootblock_crt0.S index 9fcb5c4e4a..325673162c 100644 --- a/src/arch/x86/bootblock_crt0.S +++ b/src/arch/x86/bootblock_crt0.S @@ -11,8 +11,7 @@ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * - * This is the modern bootblock. It is used by platforms which select - * C_ENVIRONMENT_BOOTBLOCK, and it prepares the system for C environment runtime + * This is the modern bootblock. It prepares the system for C environment runtime * setup. The actual setup is done by hardware-specific code. * * It provides a bootflow similar to other architectures, and thus is considered diff --git a/src/arch/x86/bootblock_romcc.S b/src/arch/x86/bootblock_romcc.S index 05b34c6c5a..7d6f42f08a 100644 --- a/src/arch/x86/bootblock_romcc.S +++ b/src/arch/x86/bootblock_romcc.S @@ -20,7 +20,7 @@ * - timestamp.inc: store TSC in MMX registers * - generated/bootblock.inc: ROMCC part of the bootblock * - * This is used on platforms which do not select C_ENVIRONMENT_BOOTBLOCK, and it + * This is used on platforms which select ROMCC_BOOTBLOCK, and it * tries to do the absolute minimum before walking CBFS and jumping to romstage. * * This file assembles the bootblock program by the order of the includes. Thus, diff --git a/src/arch/x86/car.ld b/src/arch/x86/car.ld index 3680250993..483a908816 100644 --- a/src/arch/x86/car.ld +++ b/src/arch/x86/car.ld @@ -36,7 +36,7 @@ /* Stack for CAR stages. Since it persists across all stages that * use CAR it can be reused. The chipset/SoC is expected to provide * the stack size. */ -#if CONFIG(C_ENVIRONMENT_BOOTBLOCK) +#if !CONFIG(ROMCC_BOOTBLOCK) _car_stack = .; . += CONFIG_DCACHE_BSP_STACK_SIZE; _ecar_stack = .; @@ -90,7 +90,7 @@ _ebss = .; _car_unallocated_start = .; -#if !CONFIG(C_ENVIRONMENT_BOOTBLOCK) +#if CONFIG(ROMCC_BOOTBLOCK) _car_stack = .; _ecar_stack = _car_region_end; #endif @@ -121,6 +121,6 @@ _bogus = ASSERT((CONFIG_DCACHE_RAM_SIZE == 0) || (SIZEOF(.car.data) <= CONFIG_DC #if CONFIG(PAGING_IN_CACHE_AS_RAM) _bogus2 = ASSERT(_pagetables == ALIGN(_pagetables, 4096), "_pagetables aren't 4KiB aligned"); #endif -#if CONFIG(C_ENVIRONMENT_BOOTBLOCK) +#if !CONFIG(ROMCC_BOOTBLOCK) _bogus3 = ASSERT(CONFIG_DCACHE_BSP_STACK_SIZE > 0x0, "BSP stack size not configured"); #endif diff --git a/src/arch/x86/include/arch/cpu.h b/src/arch/x86/include/arch/cpu.h index e0e3ca1972..50d636b1f6 100644 --- a/src/arch/x86/include/arch/cpu.h +++ b/src/arch/x86/include/arch/cpu.h @@ -288,9 +288,8 @@ static inline void get_fms(struct cpuinfo_x86 *c, uint32_t tfms) #define asmlinkage __attribute__((regparm(0))) /* - * When using CONFIG_C_ENVIRONMENT_BOOTBLOCK the car_stage_entry() - * is the symbol jumped to for each stage after bootblock using - * cache-as-ram. + * When not using a romcc bootblock the car_stage_entry() is the symbol + * jumped to for each stage after bootblock using cache-as-ram. */ asmlinkage void car_stage_entry(void); diff --git a/src/arch/x86/memlayout.ld b/src/arch/x86/memlayout.ld index 9fd9889911..f8ae9f3918 100644 --- a/src/arch/x86/memlayout.ld +++ b/src/arch/x86/memlayout.ld @@ -49,8 +49,7 @@ SECTIONS #include EARLY_MEMLAYOUT #elif ENV_BOOTBLOCK - /* This is for C_ENVIRONMENT_BOOTBLOCK. arch/x86/bootblock.ld contains - * the logic for the romcc linking. */ + /* arch/x86/bootblock.ld contains the logic for the ROMCC_BOOTBLOCK linking. */ BOOTBLOCK(0xffffffff - CONFIG_C_ENV_BOOTBLOCK_SIZE + 1, CONFIG_C_ENV_BOOTBLOCK_SIZE) diff --git a/src/console/Kconfig b/src/console/Kconfig index b90823ecd0..9151a32a11 100644 --- a/src/console/Kconfig +++ b/src/console/Kconfig @@ -5,7 +5,7 @@ config NO_BOOTBLOCK_CONSOLE config BOOTBLOCK_CONSOLE bool "Enable early (bootblock) console output." - depends on C_ENVIRONMENT_BOOTBLOCK && !NO_BOOTBLOCK_CONSOLE + depends on !ROMCC_BOOTBLOCK && !NO_BOOTBLOCK_CONSOLE default y help Use console during the bootblock if supported diff --git a/src/cpu/intel/car/non-evict/cache_as_ram.S b/src/cpu/intel/car/non-evict/cache_as_ram.S index cd6972062c..5a668c42df 100644 --- a/src/cpu/intel/car/non-evict/cache_as_ram.S +++ b/src/cpu/intel/car/non-evict/cache_as_ram.S @@ -29,7 +29,7 @@ _cache_as_ram_setup: bootblock_pre_c_entry: -#if CONFIG(C_ENVIRONMENT_BOOTBLOCK) +#if !CONFIG(ROMCC_BOOTBLOCK) movl $cache_as_ram, %esp /* return address */ jmp check_mtrr /* Check if CPU properly reset */ #endif diff --git a/src/cpu/intel/car/p3/cache_as_ram.S b/src/cpu/intel/car/p3/cache_as_ram.S index a3487dbe34..23df701e08 100644 --- a/src/cpu/intel/car/p3/cache_as_ram.S +++ b/src/cpu/intel/car/p3/cache_as_ram.S @@ -18,7 +18,7 @@ #define CACHE_AS_RAM_SIZE CONFIG_DCACHE_RAM_SIZE #define CACHE_AS_RAM_BASE CONFIG_DCACHE_RAM_BASE -#if CONFIG(C_ENVIRONMENT_BOOTBLOCK) +#if !CONFIG(ROMCC_BOOTBLOCK) #if ((CONFIG_C_ENV_BOOTBLOCK_SIZE & (CONFIG_C_ENV_BOOTBLOCK_SIZE - 1)) != 0) #error "CONFIG_C_ENV_BOOTBLOCK_SIZE must be a power of 2!" #endif diff --git a/src/cpu/intel/car/romstage.c b/src/cpu/intel/car/romstage.c index 9d196356e3..1f8eb9a10e 100644 --- a/src/cpu/intel/car/romstage.c +++ b/src/cpu/intel/car/romstage.c @@ -71,8 +71,8 @@ static void romstage_main(unsigned long bist) /* We do not return here. */ } -#if !CONFIG(C_ENVIRONMENT_BOOTBLOCK) -/* This wrapper enables easy transition towards C_ENVIRONMENT_BOOTBLOCK, +#if CONFIG(ROMCC_BOOTBLOCK) +/* This wrapper enables easy transition away from ROMCC_BOOTBLOCK * keeping changes in cache_as_ram.S easy to manage. */ asmlinkage void bootblock_c_entry_bist(uint64_t base_timestamp, uint32_t bist) diff --git a/src/cpu/intel/microcode/Kconfig b/src/cpu/intel/microcode/Kconfig index b78389215d..73afe0bb45 100644 --- a/src/cpu/intel/microcode/Kconfig +++ b/src/cpu/intel/microcode/Kconfig @@ -1,7 +1,7 @@ config MICROCODE_UPDATE_PRE_RAM bool depends on SUPPORT_CPU_UCODE_IN_CBFS - default y if C_ENVIRONMENT_BOOTBLOCK + default y if !ROMCC_BOOTBLOCK help Select this option if you want to update the microcode during the cache as ram setup. diff --git a/src/cpu/intel/model_206ax/Kconfig b/src/cpu/intel/model_206ax/Kconfig index f316329552..e31260588e 100644 --- a/src/cpu/intel/model_206ax/Kconfig +++ b/src/cpu/intel/model_206ax/Kconfig @@ -21,7 +21,6 @@ config CPU_SPECIFIC_OPTIONS select CPU_INTEL_COMMON_TIMEBASE select PARALLEL_MP select NO_FIXED_XIP_ROM_SIZE - select C_ENVIRONMENT_BOOTBLOCK config SMM_TSEG_SIZE hex diff --git a/src/cpu/intel/slot_1/Kconfig b/src/cpu/intel/slot_1/Kconfig index 10001bdc5f..00af79a440 100644 --- a/src/cpu/intel/slot_1/Kconfig +++ b/src/cpu/intel/slot_1/Kconfig @@ -27,6 +27,7 @@ config SLOT_SPECIFIC_OPTIONS # dummy select UDELAY_TSC select TSC_MONOTONIC_TIMER select UNKNOWN_TSC_RATE + select ROMCC_BOOTBLOCK config DCACHE_RAM_BASE hex diff --git a/src/cpu/intel/socket_mPGA604/Kconfig b/src/cpu/intel/socket_mPGA604/Kconfig index a2ebeb2325..176ae9e08a 100644 --- a/src/cpu/intel/socket_mPGA604/Kconfig +++ b/src/cpu/intel/socket_mPGA604/Kconfig @@ -11,7 +11,6 @@ config SOCKET_SPECIFIC_OPTIONS # dummy select UDELAY_TSC select TSC_MONOTONIC_TIMER select SIPI_VECTOR_IN_ROM - select C_ENVIRONMENT_BOOTBLOCK select CPU_INTEL_COMMON select CPU_INTEL_COMMON_TIMEBASE diff --git a/src/cpu/qemu-x86/Kconfig b/src/cpu/qemu-x86/Kconfig index 7504233bda..e6025b5653 100644 --- a/src/cpu/qemu-x86/Kconfig +++ b/src/cpu/qemu-x86/Kconfig @@ -21,5 +21,4 @@ config CPU_QEMU_X86 select UDELAY_TSC select TSC_MONOTONIC_TIMER select UNKNOWN_TSC_RATE - select C_ENVIRONMENT_BOOTBLOCK select SMM_ASEG diff --git a/src/cpu/x86/16bit/entry16.inc b/src/cpu/x86/16bit/entry16.inc index 9e00c55a92..e0babd5a5a 100644 --- a/src/cpu/x86/16bit/entry16.inc +++ b/src/cpu/x86/16bit/entry16.inc @@ -29,7 +29,7 @@ #include -#if CONFIG(C_ENVIRONMENT_BOOTBLOCK) || \ +#if !CONFIG(ROMCC_BOOTBLOCK) || \ CONFIG(SIPI_VECTOR_IN_ROM) /* Symbol _start16bit must be aligned to 4kB to start AP CPUs with * Startup IPI message without RAM. diff --git a/src/cpu/x86/Kconfig b/src/cpu/x86/Kconfig index 85ebd831ea..efb5fa96e9 100644 --- a/src/cpu/x86/Kconfig +++ b/src/cpu/x86/Kconfig @@ -77,7 +77,7 @@ config XIP_ROM_SIZE config SETUP_XIP_CACHE bool - depends on C_ENVIRONMENT_BOOTBLOCK + depends on !ROMCC_BOOTBLOCK depends on !NO_XIP_EARLY_STAGES help Select this option to set up an MTRR to cache XIP stages loaded diff --git a/src/lib/Makefile.inc b/src/lib/Makefile.inc index dc0c46d460..b444ea3c86 100644 --- a/src/lib/Makefile.inc +++ b/src/lib/Makefile.inc @@ -268,7 +268,9 @@ postcar-$(CONFIG_COLLECT_TIMESTAMPS) += timestamp.c postcar-$(CONFIG_GENERIC_UDELAY) += timer.c # Use program.ld for all the platforms which use C fo the bootblock. -bootblock-$(CONFIG_C_ENVIRONMENT_BOOTBLOCK) += program.ld +ifneq ($(CONFIG_ROMCC_BOOTBLOCK),y) +bootblock-y += program.ld +endif decompressor-y += program.ld postcar-y += program.ld diff --git a/src/northbridge/amd/agesa/Kconfig b/src/northbridge/amd/agesa/Kconfig index e1e129a97d..50dba252fe 100644 --- a/src/northbridge/amd/agesa/Kconfig +++ b/src/northbridge/amd/agesa/Kconfig @@ -17,6 +17,7 @@ config NORTHBRIDGE_AMD_AGESA bool default CPU_AMD_AGESA select CBMEM_TOP_BACKUP + select ROMCC_BOOTBLOCK if NORTHBRIDGE_AMD_AGESA diff --git a/src/northbridge/amd/pi/Kconfig b/src/northbridge/amd/pi/Kconfig index c0df2a1abd..4fbcd4aad4 100644 --- a/src/northbridge/amd/pi/Kconfig +++ b/src/northbridge/amd/pi/Kconfig @@ -18,6 +18,7 @@ config NORTHBRIDGE_AMD_PI default y if CPU_AMD_PI default n select CBMEM_TOP_BACKUP + select ROMCC_BOOTBLOCK if NORTHBRIDGE_AMD_PI diff --git a/src/northbridge/intel/gm45/Kconfig b/src/northbridge/intel/gm45/Kconfig index 4877fa9d6b..69b055e96c 100644 --- a/src/northbridge/intel/gm45/Kconfig +++ b/src/northbridge/intel/gm45/Kconfig @@ -26,7 +26,6 @@ config NORTHBRIDGE_SPECIFIC_OPTIONS # dummy select INTEL_GMA_ACPI select INTEL_GMA_SSC_ALTERNATE_REF select PARALLEL_MP - select C_ENVIRONMENT_BOOTBLOCK config VBOOT select VBOOT_STARTS_IN_BOOTBLOCK diff --git a/src/northbridge/intel/haswell/Kconfig b/src/northbridge/intel/haswell/Kconfig index aad2674241..6dc4ef03d7 100644 --- a/src/northbridge/intel/haswell/Kconfig +++ b/src/northbridge/intel/haswell/Kconfig @@ -19,7 +19,6 @@ config NORTHBRIDGE_INTEL_HASWELL select CACHE_MRC_SETTINGS select INTEL_DDI select INTEL_GMA_ACPI - select C_ENVIRONMENT_BOOTBLOCK select BOOTBLOCK_CONSOLE if NORTHBRIDGE_INTEL_HASWELL diff --git a/src/northbridge/intel/i945/Kconfig b/src/northbridge/intel/i945/Kconfig index a0550ec3c7..c22275a6b1 100644 --- a/src/northbridge/intel/i945/Kconfig +++ b/src/northbridge/intel/i945/Kconfig @@ -27,7 +27,6 @@ config NORTHBRIDGE_SPECIFIC_OPTIONS # dummy select INTEL_EDID select HAVE_VGA_TEXT_FRAMEBUFFER if MAINBOARD_DO_NATIVE_VGA_INIT select PARALLEL_MP - select C_ENVIRONMENT_BOOTBLOCK config NORTHBRIDGE_INTEL_SUBTYPE_I945GC def_bool n diff --git a/src/northbridge/intel/nehalem/Kconfig b/src/northbridge/intel/nehalem/Kconfig index 7b56841336..a119b817ae 100644 --- a/src/northbridge/intel/nehalem/Kconfig +++ b/src/northbridge/intel/nehalem/Kconfig @@ -21,7 +21,6 @@ config NORTHBRIDGE_INTEL_NEHALEM select INTEL_GMA_ACPI select CACHE_MRC_SETTINGS select HAVE_DEBUG_RAM_SETUP - select C_ENVIRONMENT_BOOTBLOCK if NORTHBRIDGE_INTEL_NEHALEM diff --git a/src/northbridge/intel/pineview/Kconfig b/src/northbridge/intel/pineview/Kconfig index edf4f2321e..73060363f5 100644 --- a/src/northbridge/intel/pineview/Kconfig +++ b/src/northbridge/intel/pineview/Kconfig @@ -28,7 +28,6 @@ config NORTHBRIDGE_SPECIFIC_OPTIONS # dummy select INTEL_EDID if MAINBOARD_DO_NATIVE_VGA_INIT select INTEL_GMA_ACPI select PARALLEL_MP - select C_ENVIRONMENT_BOOTBLOCK config VGA_BIOS_ID string diff --git a/src/northbridge/intel/x4x/Kconfig b/src/northbridge/intel/x4x/Kconfig index 2a54e2495e..247686ade3 100644 --- a/src/northbridge/intel/x4x/Kconfig +++ b/src/northbridge/intel/x4x/Kconfig @@ -26,7 +26,6 @@ config NORTHBRIDGE_SPECIFIC_OPTIONS # dummy select INTEL_GMA_ACPI select CACHE_MRC_SETTINGS select PARALLEL_MP - select C_ENVIRONMENT_BOOTBLOCK config CBFS_SIZE hex diff --git a/src/security/vboot/Kconfig b/src/security/vboot/Kconfig index df1b7e478a..a829443098 100644 --- a/src/security/vboot/Kconfig +++ b/src/security/vboot/Kconfig @@ -95,7 +95,7 @@ config VBOOT_VBNV_FLASH config VBOOT_STARTS_IN_BOOTBLOCK bool default n - depends on C_ENVIRONMENT_BOOTBLOCK + depends on !ROMCC_BOOTBLOCK help Firmware verification happens during the end of or right after the bootblock. This implies that a static VBOOT2_WORK() buffer must be diff --git a/src/soc/amd/picasso/Kconfig b/src/soc/amd/picasso/Kconfig index 5f9792b28a..e192818a0b 100644 --- a/src/soc/amd/picasso/Kconfig +++ b/src/soc/amd/picasso/Kconfig @@ -49,7 +49,6 @@ config CPU_SPECIFIC_OPTIONS select SOC_AMD_COMMON_BLOCK_HDA select SOC_AMD_COMMON_BLOCK_SATA select SOC_AMD_COMMON_BLOCK_S3 - select C_ENVIRONMENT_BOOTBLOCK select BOOT_DEVICE_SUPPORTS_WRITES if BOOT_DEVICE_SPI_FLASH select BOOT_DEVICE_SPI_FLASH_RW_NOMMAP_EARLY if BOOT_DEVICE_SPI_FLASH select PARALLEL_MP @@ -82,7 +81,6 @@ config DCACHE_RAM_SIZE default 0x10000 config DCACHE_BSP_STACK_SIZE - depends on C_ENVIRONMENT_BOOTBLOCK hex default 0x4000 help diff --git a/src/soc/amd/stoneyridge/Kconfig b/src/soc/amd/stoneyridge/Kconfig index 0d6f2ff0bc..cbf88df902 100644 --- a/src/soc/amd/stoneyridge/Kconfig +++ b/src/soc/amd/stoneyridge/Kconfig @@ -69,7 +69,6 @@ config CPU_SPECIFIC_OPTIONS select SOC_AMD_COMMON_BLOCK_PSP select SOC_AMD_COMMON_BLOCK_CAR select SOC_AMD_COMMON_BLOCK_S3 - select C_ENVIRONMENT_BOOTBLOCK select BOOT_DEVICE_SUPPORTS_WRITES if BOOT_DEVICE_SPI_FLASH select BOOT_DEVICE_SPI_FLASH_RW_NOMMAP_EARLY if BOOT_DEVICE_SPI_FLASH select PARALLEL_MP @@ -98,7 +97,6 @@ config DCACHE_RAM_SIZE default 0x10000 config DCACHE_BSP_STACK_SIZE - depends on C_ENVIRONMENT_BOOTBLOCK hex default 0x4000 help diff --git a/src/soc/intel/apollolake/Kconfig b/src/soc/intel/apollolake/Kconfig index 026f6da669..0b3b30a4f8 100644 --- a/src/soc/intel/apollolake/Kconfig +++ b/src/soc/intel/apollolake/Kconfig @@ -38,7 +38,6 @@ config CPU_SPECIFIC_OPTIONS select ACPI_NHLT select SOC_INTEL_COMMON_NHLT # Misc options - select C_ENVIRONMENT_BOOTBLOCK select CACHE_MRC_SETTINGS select COMMON_FADT select FSP_PLATFORM_MEMORY_SETTINGS_VERSIONS diff --git a/src/soc/intel/baytrail/Kconfig b/src/soc/intel/baytrail/Kconfig index 397e86768c..fac14cbd3b 100644 --- a/src/soc/intel/baytrail/Kconfig +++ b/src/soc/intel/baytrail/Kconfig @@ -37,6 +37,7 @@ config CPU_SPECIFIC_OPTIONS select INTEL_GMA_SWSMISCI select CPU_INTEL_COMMON select CPU_HAS_L2_ENABLE_MSR + select ROMCC_BOOTBLOCK config VBOOT select VBOOT_MUST_REQUEST_DISPLAY diff --git a/src/soc/intel/braswell/Kconfig b/src/soc/intel/braswell/Kconfig index 7ea01863ae..f08b58982a 100644 --- a/src/soc/intel/braswell/Kconfig +++ b/src/soc/intel/braswell/Kconfig @@ -46,7 +46,6 @@ config CPU_SPECIFIC_OPTIONS select INTEL_GMA_SWSMISCI select CPU_INTEL_COMMON select SOUTHBRIDGE_INTEL_COMMON_SMBUS - select C_ENVIRONMENT_BOOTBLOCK config DCACHE_BSP_STACK_SIZE hex diff --git a/src/soc/intel/broadwell/Kconfig b/src/soc/intel/broadwell/Kconfig index 095ed988c6..07bcf22b1d 100644 --- a/src/soc/intel/broadwell/Kconfig +++ b/src/soc/intel/broadwell/Kconfig @@ -41,7 +41,6 @@ config CPU_SPECIFIC_OPTIONS select HAVE_POWER_STATE_AFTER_FAILURE select HAVE_POWER_STATE_PREVIOUS_AFTER_FAILURE select NO_FIXED_XIP_ROM_SIZE - select C_ENVIRONMENT_BOOTBLOCK config PCIEXP_ASPM bool diff --git a/src/soc/intel/cannonlake/Kconfig b/src/soc/intel/cannonlake/Kconfig index 5731cff916..5c91ac142f 100644 --- a/src/soc/intel/cannonlake/Kconfig +++ b/src/soc/intel/cannonlake/Kconfig @@ -58,7 +58,6 @@ config CPU_SPECIFIC_OPTIONS select ARCH_VERSTAGE_X86_32 select BOOT_DEVICE_SPI_FLASH_RW_NOMMAP_EARLY if BOOT_DEVICE_SPI_FLASH select BOOT_DEVICE_SUPPORTS_WRITES - select C_ENVIRONMENT_BOOTBLOCK select CACHE_MRC_SETTINGS select COMMON_FADT select CPU_INTEL_COMMON diff --git a/src/soc/intel/denverton_ns/Kconfig b/src/soc/intel/denverton_ns/Kconfig index cb3713d3b0..0ce0d5bdd1 100644 --- a/src/soc/intel/denverton_ns/Kconfig +++ b/src/soc/intel/denverton_ns/Kconfig @@ -32,7 +32,6 @@ config CPU_SPECIFIC_OPTIONS select SOC_INTEL_COMMON select SOC_INTEL_COMMON_RESET select PLATFORM_USES_FSP2_0 - select C_ENVIRONMENT_BOOTBLOCK select IOAPIC select HAVE_SMI_HANDLER select CACHE_MRC_SETTINGS diff --git a/src/soc/intel/icelake/Kconfig b/src/soc/intel/icelake/Kconfig index a2fe5ed3da..7f1cd893a3 100644 --- a/src/soc/intel/icelake/Kconfig +++ b/src/soc/intel/icelake/Kconfig @@ -14,7 +14,6 @@ config CPU_SPECIFIC_OPTIONS select ARCH_VERSTAGE_X86_32 select BOOT_DEVICE_SPI_FLASH_RW_NOMMAP_EARLY if BOOT_DEVICE_SPI_FLASH select BOOT_DEVICE_SUPPORTS_WRITES - select C_ENVIRONMENT_BOOTBLOCK select CACHE_MRC_SETTINGS select COMMON_FADT select CPU_INTEL_FIRMWARE_INTERFACE_TABLE diff --git a/src/soc/intel/quark/Kconfig b/src/soc/intel/quark/Kconfig index 461d230371..099c7ddc9d 100644 --- a/src/soc/intel/quark/Kconfig +++ b/src/soc/intel/quark/Kconfig @@ -26,7 +26,6 @@ config CPU_SPECIFIC_OPTIONS select ARCH_RAMSTAGE_X86_32 select ARCH_ROMSTAGE_X86_32 select ARCH_VERSTAGE_X86_32 - select C_ENVIRONMENT_BOOTBLOCK select NO_MMCONF_SUPPORT select REG_SCRIPT select PLATFORM_USES_FSP2_0 @@ -226,11 +225,6 @@ config RMU_LOC The location in CBFS that the RMU is located. It must match the strap-determined base address. -##### -# Bootblock -# The following options support the C_ENVIRONMENT_BOOTBLOCK. -##### - config DCACHE_BSP_STACK_SIZE hex default 0x4000 diff --git a/src/soc/intel/skylake/Kconfig b/src/soc/intel/skylake/Kconfig index f5f1e30aaa..032ded4025 100644 --- a/src/soc/intel/skylake/Kconfig +++ b/src/soc/intel/skylake/Kconfig @@ -30,7 +30,6 @@ config CPU_SPECIFIC_OPTIONS select CPU_INTEL_COMMON select CPU_INTEL_FIRMWARE_INTERFACE_TABLE select CPU_INTEL_COMMON_HYPERTHREADING - select C_ENVIRONMENT_BOOTBLOCK select FSP_M_XIP select FSP_T_XIP if FSP_CAR select GENERIC_GPIO_LIB diff --git a/src/soc/intel/tigerlake/Kconfig b/src/soc/intel/tigerlake/Kconfig index 2824e52558..9c5fc984c9 100644 --- a/src/soc/intel/tigerlake/Kconfig +++ b/src/soc/intel/tigerlake/Kconfig @@ -14,7 +14,6 @@ config CPU_SPECIFIC_OPTIONS select ARCH_VERSTAGE_X86_32 select BOOT_DEVICE_SPI_FLASH_RW_NOMMAP_EARLY if BOOT_DEVICE_SPI_FLASH select BOOT_DEVICE_SUPPORTS_WRITES - select C_ENVIRONMENT_BOOTBLOCK select CACHE_MRC_SETTINGS select COMMON_FADT select CPU_INTEL_FIRMWARE_INTERFACE_TABLE diff --git a/src/vendorcode/eltan/security/verified_boot/vboot_check.c b/src/vendorcode/eltan/security/verified_boot/vboot_check.c index 9fb83707bf..bc502c9d53 100644 --- a/src/vendorcode/eltan/security/verified_boot/vboot_check.c +++ b/src/vendorcode/eltan/security/verified_boot/vboot_check.c @@ -276,7 +276,7 @@ void verified_boot_early_check(void) { printk(BIOS_SPEW, "%s: processing early items\n", __func__); - if (!CONFIG(C_ENVIRONMENT_BOOTBLOCK) && + if (CONFIG(ROMCC_BOOTBLOCK) && CONFIG(VENDORCODE_ELTAN_VBOOT_SIGNED_MANIFEST)) { printk(BIOS_SPEW, "%s: check the manifest\n", __func__); if (verified_boot_check_manifest() != 0) From df0c731e688f55caf61fa721d32f1725e241aca5 Mon Sep 17 00:00:00 2001 From: Arthur Heymans Date: Fri, 22 Nov 2019 21:02:51 +0100 Subject: [PATCH 0362/1242] mb/Kconfig: Add a warning on boards with a ROMCC_BOOTLOCK MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This feature and therefore the boards using it, will be deprecated soon. Change-Id: I1e970dd0613702346b5764d2b56012a72ed62cde Signed-off-by: Arthur Heymans Reviewed-on: https://review.coreboot.org/c/coreboot/+/37155 Reviewed-by: HAOUAS Elyes Reviewed-by: Patrick Georgi Reviewed-by: Angel Pons Reviewed-by: Kyösti Mälkki Tested-by: build bot (Jenkins) --- src/mainboard/Kconfig | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/src/mainboard/Kconfig b/src/mainboard/Kconfig index c88d31719e..97086b7cd6 100644 --- a/src/mainboard/Kconfig +++ b/src/mainboard/Kconfig @@ -1,5 +1,9 @@ comment "Important: Run 'make distclean' before switching boards" +if ROMCC_BOOTBLOCK +comment "Systems with ROMCC bootblocks will be deprecated soon!" +endif + choice prompt "Mainboard vendor" default VENDOR_EMULATION From 1fa240a3c5d2a6e8cd63eff24f227abc3333753b Mon Sep 17 00:00:00 2001 From: Arthur Heymans Date: Tue, 12 Nov 2019 12:05:38 +0100 Subject: [PATCH 0363/1242] cpu/intel/slot_1: Move to C_ENVIRONMENT_BOOTBLOCK MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Console is not yet enabled in bootblock. This will be done in a different CL. Change-Id: Ic751d42a1969fb79fb50366f766d8796846a0bc4 Signed-off-by: Arthur Heymans Reviewed-on: https://review.coreboot.org/c/coreboot/+/36774 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki --- src/cpu/intel/car/p3/cache_as_ram.S | 4 ---- src/cpu/intel/slot_1/Kconfig | 9 ++++++++- src/cpu/intel/slot_1/Makefile.inc | 3 ++- src/northbridge/intel/i440bx/Kconfig | 1 + src/southbridge/intel/i82371eb/Kconfig | 5 ----- src/southbridge/intel/i82371eb/Makefile.inc | 2 ++ src/southbridge/intel/i82371eb/bootblock.c | 9 ++++++++- 7 files changed, 21 insertions(+), 12 deletions(-) diff --git a/src/cpu/intel/car/p3/cache_as_ram.S b/src/cpu/intel/car/p3/cache_as_ram.S index 23df701e08..5262b1886d 100644 --- a/src/cpu/intel/car/p3/cache_as_ram.S +++ b/src/cpu/intel/car/p3/cache_as_ram.S @@ -18,14 +18,10 @@ #define CACHE_AS_RAM_SIZE CONFIG_DCACHE_RAM_SIZE #define CACHE_AS_RAM_BASE CONFIG_DCACHE_RAM_BASE -#if !CONFIG(ROMCC_BOOTBLOCK) #if ((CONFIG_C_ENV_BOOTBLOCK_SIZE & (CONFIG_C_ENV_BOOTBLOCK_SIZE - 1)) != 0) #error "CONFIG_C_ENV_BOOTBLOCK_SIZE must be a power of 2!" #endif #define XIP_ROM_SIZE CONFIG_C_ENV_BOOTBLOCK_SIZE -#else -#define XIP_ROM_SIZE CONFIG_XIP_ROM_SIZE -#endif .global bootblock_pre_c_entry diff --git a/src/cpu/intel/slot_1/Kconfig b/src/cpu/intel/slot_1/Kconfig index 00af79a440..791997499d 100644 --- a/src/cpu/intel/slot_1/Kconfig +++ b/src/cpu/intel/slot_1/Kconfig @@ -27,7 +27,6 @@ config SLOT_SPECIFIC_OPTIONS # dummy select UDELAY_TSC select TSC_MONOTONIC_TIMER select UNKNOWN_TSC_RATE - select ROMCC_BOOTBLOCK config DCACHE_RAM_BASE hex @@ -37,4 +36,12 @@ config DCACHE_RAM_SIZE hex default 0x02000 +config DCACHE_BSP_STACK_SIZE + hex + default 0x1000 + +config C_ENV_BOOTBLOCK_SIZE + hex + default 0x2000 + endif diff --git a/src/cpu/intel/slot_1/Makefile.inc b/src/cpu/intel/slot_1/Makefile.inc index 599a5d0f24..0e4e7e6fd4 100644 --- a/src/cpu/intel/slot_1/Makefile.inc +++ b/src/cpu/intel/slot_1/Makefile.inc @@ -26,6 +26,7 @@ subdirs-y += ../../x86/cache subdirs-y += ../../x86/smm subdirs-y += ../microcode -cpu_incs-y += $(src)/cpu/intel/car/p3/cache_as_ram.S +bootblock-y += ../car/p3/cache_as_ram.S +bootblock-y += ../car/bootblock.c postcar-y += ../car/p4-netburst/exit_car.S romstage-y += ../car/romstage.c diff --git a/src/northbridge/intel/i440bx/Kconfig b/src/northbridge/intel/i440bx/Kconfig index df1e3650a4..010a6e7cb4 100644 --- a/src/northbridge/intel/i440bx/Kconfig +++ b/src/northbridge/intel/i440bx/Kconfig @@ -17,6 +17,7 @@ config NORTHBRIDGE_INTEL_I440BX bool select NO_MMCONF_SUPPORT select HAVE_DEBUG_RAM_SETUP + select NO_BOOTBLOCK_CONSOLE config SDRAMPWR_4DIMM bool diff --git a/src/southbridge/intel/i82371eb/Kconfig b/src/southbridge/intel/i82371eb/Kconfig index f5b5f4ee1e..d0eec0e5f4 100644 --- a/src/southbridge/intel/i82371eb/Kconfig +++ b/src/southbridge/intel/i82371eb/Kconfig @@ -4,8 +4,3 @@ config SOUTHBRIDGE_INTEL_I82371EB select SOUTHBRIDGE_INTEL_COMMON_RTC select SOUTHBRIDGE_INTEL_COMMON_RESET bool - -config BOOTBLOCK_SOUTHBRIDGE_INIT - string - default "southbridge/intel/i82371eb/bootblock.c" - depends on SOUTHBRIDGE_INTEL_I82371EB diff --git a/src/southbridge/intel/i82371eb/Makefile.inc b/src/southbridge/intel/i82371eb/Makefile.inc index 131010fc3d..390fd9783e 100644 --- a/src/southbridge/intel/i82371eb/Makefile.inc +++ b/src/southbridge/intel/i82371eb/Makefile.inc @@ -16,6 +16,8 @@ ifeq ($(CONFIG_SOUTHBRIDGE_INTEL_I82371EB),y) +bootblock-y += bootblock.c + ramstage-y += i82371eb.c ramstage-y += isa.c ramstage-y += ide.c diff --git a/src/southbridge/intel/i82371eb/bootblock.c b/src/southbridge/intel/i82371eb/bootblock.c index 2b8cd1f4b7..a6d62e03e0 100644 --- a/src/southbridge/intel/i82371eb/bootblock.c +++ b/src/southbridge/intel/i82371eb/bootblock.c @@ -18,6 +18,7 @@ #include #include #include +#include #include "i82371eb.h" #define PCI_ID(VENDOR_ID, DEVICE_ID) \ @@ -34,7 +35,13 @@ static pci_devfn_t pci_locate_device(unsigned int pci_id, pci_devfn_t dev) return PCI_DEV_INVALID; } -static void bootblock_southbridge_init(void) +/* TODO: Does not need to happen before console init. */ +/* The whole rom is not accessible before this so limit + the bootblock size. */ +#if CONFIG_C_ENV_BOOTBLOCK_SIZE > 0x10000 +#error "CONFIG_C_ENV_BOOTBLOCK_SIZE needs to be below 64KiB" +#endif +void bootblock_early_southbridge_init(void) { u16 reg16; pci_devfn_t dev; From e719288a3c8d20d087aa27bfaf0bf2b03fab2c66 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Micha=C5=82=20=C5=BBygowski?= Date: Sat, 23 Nov 2019 19:02:19 +0100 Subject: [PATCH 0364/1242] binaryPI: Use Kconfig to define the number of IOAPICs MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Define the number of IOAPICs in a Kconfig to get rid of AmdGetValue calls being not conformant to AGESA API. Change-Id: I532597dd326093455358a23aef3b3ea0d0a14f75 Signed-off-by: Michał Żygowski Reviewed-on: https://review.coreboot.org/c/coreboot/+/37169 Tested-by: build bot (Jenkins) Reviewed-by: Marshall Dawson --- src/northbridge/amd/pi/00630F01/northbridge.c | 18 ++++-------------- src/northbridge/amd/pi/00660F01/northbridge.c | 14 ++++---------- src/northbridge/amd/pi/00730F01/northbridge.c | 18 ++++-------------- src/northbridge/amd/pi/Kconfig | 4 ++++ 4 files changed, 16 insertions(+), 38 deletions(-) diff --git a/src/northbridge/amd/pi/00630F01/northbridge.c b/src/northbridge/amd/pi/00630F01/northbridge.c index 40d3e0577c..6bb121707e 100644 --- a/src/northbridge/amd/pi/00630F01/northbridge.c +++ b/src/northbridge/amd/pi/00630F01/northbridge.c @@ -27,7 +27,6 @@ #include #include #include -#include #include #include #include @@ -798,21 +797,12 @@ static void cpu_bus_scan(struct device *dev) int siblings = 0; unsigned int family; u32 modules = 0; - VOID* modules_ptr = &modules; - BUILD_OPT_CFG* options = NULL; int ioapic_count = 0; - // TODO Remove the printk's. - printk(BIOS_SPEW, "KaveriPI Debug: Grabbing the AMD Topology Information.\n"); - AmdGetValue(AMD_GLOBAL_USER_OPTIONS, (VOID**)&options, sizeof(options)); - AmdGetValue(AMD_GLOBAL_NUM_MODULES, &modules_ptr, sizeof(modules)); - modules = *(u32*)modules_ptr; - ASSERT(modules > 0); - ASSERT(options); - ioapic_count = (int)options->CfgPlatNumIoApics; - ASSERT(ioapic_count > 0); - printk(BIOS_SPEW, "KaveriPI Debug: AMD Topology Number of Modules (@0x%p) is %d\n", modules_ptr, modules); - printk(BIOS_SPEW, "KaveriPI Debug: AMD Topology Number of IOAPICs (@0x%p) is %d\n", options, (int)(options->CfgPlatNumIoApics)); + /* For binaryPI there is no multiprocessor configuration, the number of + * modules will always be 1. */ + modules = 1; + ioapic_count = CONFIG_NUM_OF_IOAPICS; dev_mc = pcidev_on_root(DEV_CDB, 0); if (!dev_mc) { diff --git a/src/northbridge/amd/pi/00660F01/northbridge.c b/src/northbridge/amd/pi/00660F01/northbridge.c index 533b651427..723e6f474d 100644 --- a/src/northbridge/amd/pi/00660F01/northbridge.c +++ b/src/northbridge/amd/pi/00660F01/northbridge.c @@ -27,7 +27,6 @@ #include #include #include -#include #include #include #include @@ -796,17 +795,12 @@ static void cpu_bus_scan(struct device *dev) int siblings = 0; unsigned int family; u32 modules = 0; - VOID* modules_ptr = &modules; - BUILD_OPT_CFG* options = NULL; int ioapic_count = 0; - AmdGetValue(AMD_GLOBAL_USER_OPTIONS, (VOID**)&options, sizeof(options)); - AmdGetValue(AMD_GLOBAL_NUM_MODULES, &modules_ptr, sizeof(modules)); - modules = (*(u32 *)modules_ptr) & ((1ull << (sizeof(modules) * 8)) - 1); - ASSERT(modules > 0); - ASSERT(options); - ioapic_count = (int)options->CfgPlatNumIoApics; - ASSERT(ioapic_count > 0); + /* For binaryPI there is no multiprocessor configuration, the number of + * modules will always be 1. */ + modules = 1; + ioapic_count = CONFIG_NUM_OF_IOAPICS; dev_mc = pcidev_on_root(DEV_CDB, 0); if (!dev_mc) { diff --git a/src/northbridge/amd/pi/00730F01/northbridge.c b/src/northbridge/amd/pi/00730F01/northbridge.c index 27e14f5df5..3d7b883d17 100644 --- a/src/northbridge/amd/pi/00730F01/northbridge.c +++ b/src/northbridge/amd/pi/00730F01/northbridge.c @@ -29,7 +29,6 @@ #include #include #include -#include #include #include #include @@ -1031,21 +1030,12 @@ static void cpu_bus_scan(struct device *dev) int siblings = 0; unsigned int family; u32 modules = 0; - VOID* modules_ptr = &modules; - BUILD_OPT_CFG* options = NULL; int ioapic_count = 0; - // TODO Remove the printk's. - printk(BIOS_SPEW, "MullinsPI Debug: Grabbing the AMD Topology Information.\n"); - AmdGetValue(AMD_GLOBAL_USER_OPTIONS, (VOID**)&options, sizeof(options)); - AmdGetValue(AMD_GLOBAL_NUM_MODULES, &modules_ptr, sizeof(modules)); - modules = *(u32*)modules_ptr; - ASSERT(modules > 0); - ASSERT(options); - ioapic_count = (int)options->CfgPlatNumIoApics; - ASSERT(ioapic_count > 0); - printk(BIOS_SPEW, "MullinsPI Debug: AMD Topology Number of Modules (@0x%p) is %d\n", modules_ptr, modules); - printk(BIOS_SPEW, "MullinsPI Debug: AMD Topology Number of IOAPICs (@0x%p) is %d\n", options, (int)options->CfgPlatNumIoApics); + /* For binaryPI there is no multiprocessor configuration, the number of + * modules will always be 1. */ + modules = 1; + ioapic_count = CONFIG_NUM_OF_IOAPICS; dev_mc = pcidev_on_root(DEV_CDB, 0); if (!dev_mc) { diff --git a/src/northbridge/amd/pi/Kconfig b/src/northbridge/amd/pi/Kconfig index 4fbcd4aad4..167d957268 100644 --- a/src/northbridge/amd/pi/Kconfig +++ b/src/northbridge/amd/pi/Kconfig @@ -54,4 +54,8 @@ config HEAP_SIZE hex default 0xc0000 +config NUM_OF_IOAPICS + int + default 3 + endif # NORTHBRIDGE_AMD_PI From 9367d91e22996f42444afcd7dbe1c41d55d98836 Mon Sep 17 00:00:00 2001 From: Tim Wawrzynczak Date: Wed, 20 Nov 2019 10:29:56 -0700 Subject: [PATCH 0365/1242] hatch: Enable EC sync in romstage Now that the EC software sync in romstage ("early EC sync") patches have landed, it's time to enable this for Hatch. BUG=none BRANCH=hatch TEST=verify EC sync runs in romstage Change-Id: Ie567ab081b95b2302b051812fbf46e183c76bab6 Signed-off-by: Tim Wawrzynczak Reviewed-on: https://review.coreboot.org/c/coreboot/+/37025 Reviewed-by: Furquan Shaikh Tested-by: build bot (Jenkins) --- src/mainboard/google/hatch/Kconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/src/mainboard/google/hatch/Kconfig b/src/mainboard/google/hatch/Kconfig index 943ec612a4..d6e6e46f18 100644 --- a/src/mainboard/google/hatch/Kconfig +++ b/src/mainboard/google/hatch/Kconfig @@ -129,6 +129,7 @@ config VARIANT_DIR config VBOOT select HAS_RECOVERY_MRC_CACHE select MRC_CLEAR_NORMAL_CACHE_ON_RECOVERY_RETRAIN + select VBOOT_EARLY_EC_SYNC select VBOOT_LID_SWITCH endif # BOARD_GOOGLE_BASEBOARD_HATCH From 2c3d91c9c8f0cf648ef4c2d8cb7d719433a9d9fe Mon Sep 17 00:00:00 2001 From: Maulik V Vaghela Date: Thu, 21 Nov 2019 21:20:17 +0530 Subject: [PATCH 0366/1242] soc/intel/tigerlake: Add Jasperlake soc Kconfig Add Kconfig option for Jasperlake soc and make tigerlake as a base soc. This will allow us to differentiate between soc features. Change-Id: Id5001dc498a7d7d5c7903dc3a3762da740fc9c8e Signed-off-by: Maulik V Vaghela Reviewed-on: https://review.coreboot.org/c/coreboot/+/37112 Tested-by: build bot (Jenkins) Reviewed-by: Aamir Bohra Reviewed-by: Subrata Banik Reviewed-by: Ronak Kanabar --- src/soc/intel/tigerlake/Kconfig | 12 +++++++++++- 1 file changed, 11 insertions(+), 1 deletion(-) diff --git a/src/soc/intel/tigerlake/Kconfig b/src/soc/intel/tigerlake/Kconfig index 9c5fc984c9..01ce7d8ee8 100644 --- a/src/soc/intel/tigerlake/Kconfig +++ b/src/soc/intel/tigerlake/Kconfig @@ -1,9 +1,19 @@ +config SOC_INTEL_TIGERLAKE_BASE + bool + config SOC_INTEL_TIGERLAKE bool + select SOC_INTEL_TIGERLAKE_BASE help Intel Tigerlake support -if SOC_INTEL_TIGERLAKE +config SOC_INTEL_JASPERLAKE + bool + select SOC_INTEL_TIGERLAKE_BASE + help + Intel Jasperlake support + +if SOC_INTEL_TIGERLAKE_BASE config CPU_SPECIFIC_OPTIONS def_bool y From a9b1a72a8f3e2aa968180fb7cb76b0441d6bb0df Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ky=C3=B6sti=20M=C3=A4lkki?= Date: Tue, 18 Jul 2017 16:27:38 +0300 Subject: [PATCH 0367/1242] binaryPI: Remove FieldAccessors.[ch] MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit SAGE brought these in outside AGESA specifications and they had some ill semantics. They were already removed from StoneyRidge. Change-Id: I59d0c450583b2ff58031c127aae881d1f3799338 Signed-off-by: Kyösti Mälkki Reviewed-on: https://review.coreboot.org/c/coreboot/+/37174 Tested-by: build bot (Jenkins) Reviewed-by: Michał Żygowski Reviewed-by: Marshall Dawson --- src/vendorcode/amd/pi/00630F01/AMD.h | 4 +- .../amd/pi/00630F01/binaryPI/AGESA.c | 76 ----------- .../amd/pi/00630F01/binaryPI/FieldAccessors.h | 111 ---------------- src/vendorcode/amd/pi/00660F01/AMD.h | 4 +- .../amd/pi/00660F01/binaryPI/AGESA.c | 73 ----------- .../amd/pi/00660F01/binaryPI/FieldAccessors.h | 118 ------------------ src/vendorcode/amd/pi/00730F01/AMD.h | 4 +- .../amd/pi/00730F01/binaryPI/AGESA.c | 73 ----------- .../amd/pi/00730F01/binaryPI/FieldAccessors.h | 111 ---------------- 9 files changed, 6 insertions(+), 568 deletions(-) delete mode 100644 src/vendorcode/amd/pi/00630F01/binaryPI/FieldAccessors.h delete mode 100644 src/vendorcode/amd/pi/00660F01/binaryPI/FieldAccessors.h delete mode 100644 src/vendorcode/amd/pi/00730F01/binaryPI/FieldAccessors.h diff --git a/src/vendorcode/amd/pi/00630F01/AMD.h b/src/vendorcode/amd/pi/00630F01/AMD.h index f70b128508..2de546136d 100644 --- a/src/vendorcode/amd/pi/00630F01/AMD.h +++ b/src/vendorcode/amd/pi/00630F01/AMD.h @@ -159,8 +159,8 @@ typedef enum { FCH_INIT_LATE = 0x00043000, FCH_INIT_S3_EARLY_RESTORE = 0x00044000, FCH_INIT_S3_LATE_RESTORE = 0x00045000, - AMD_SET_VALUE = 0x00081000, - AMD_GET_VALUE = 0x00082000, + AMD_SET_VALUE_invalid = 0x00081000, + AMD_GET_VALUE_invalid = 0x00082000, } AGESA_STRUCT_NAME; /* ResetType constant values */ diff --git a/src/vendorcode/amd/pi/00630F01/binaryPI/AGESA.c b/src/vendorcode/amd/pi/00630F01/binaryPI/AGESA.c index 2bc939970f..fa6c276ce2 100644 --- a/src/vendorcode/amd/pi/00630F01/binaryPI/AGESA.c +++ b/src/vendorcode/amd/pi/00630F01/binaryPI/AGESA.c @@ -48,7 +48,6 @@ #include #include #include -#include CONST UINT32 ImageSignature = IMAGE_SIGNATURE; CONST UINT32 ModuleSignature = MODULE_SIGNATURE; @@ -511,78 +510,3 @@ ImcIdle ( { ((FCH_DATA_BLOCK*)FchDataPtr)->StdHeader->Func = 0; } - -/********************************************************************** - * Interface call: AmdSetValue - **********************************************************************/ -AGESA_STATUS -AmdSetValue ( - IN CONST AGESA_FIELD_NAME name, - IN OUT VOID* value, - IN UINT32 size - ) -{ - AGESA_STATUS status = AGESA_UNSUPPORTED; - - MODULE_ENTRY Dispatcher = NULL; - const AMD_MODULE_HEADER* module = agesawrapper_locate_module(ModuleIdentifier); - - AMD_ACCESSOR_PARAMS AccessorParams = {}; - - if (!module) return status; - Dispatcher = module->ModuleDispatcher; - - AccessorParams.StdHeader.AltImageBasePtr = 0; - AccessorParams.StdHeader.CalloutPtr = NULL; - AccessorParams.StdHeader.Func = AMD_SET_VALUE; - AccessorParams.StdHeader.ImageBasePtr = 0; - - AccessorParams.AllocationMethod = ByHost; - AccessorParams.FieldName = name; - AccessorParams.FieldValue = value; - AccessorParams.FieldSize = size; - - status = Dispatcher(&AccessorParams); - return status; -} - -/********************************************************************** - * Interface call: AmdGetValue - **********************************************************************/ -AGESA_STATUS -AmdGetValue ( - IN CONST AGESA_FIELD_NAME name, - IN OUT VOID** value, - IN UINT32 size - ) -{ - AGESA_STATUS status = AGESA_UNSUPPORTED; - - MODULE_ENTRY Dispatcher = NULL; - const AMD_MODULE_HEADER* module = agesawrapper_locate_module(ModuleIdentifier); - - AMD_ACCESSOR_PARAMS AccessorParams = {}; - - ASSERT(module); - if (!module) return status; - Dispatcher = module->ModuleDispatcher; - ASSERT(Dispatcher); - - AccessorParams.StdHeader.AltImageBasePtr = 0; - AccessorParams.StdHeader.CalloutPtr = NULL; - AccessorParams.StdHeader.Func = AMD_GET_VALUE; - AccessorParams.StdHeader.ImageBasePtr = 0; - - AccessorParams.AllocationMethod = ByHost; - AccessorParams.FieldName = name; - AccessorParams.FieldValue = *value; - AccessorParams.FieldSize = size; - - status = Dispatcher(&AccessorParams); - ASSERT(AGESA_SUCCESS == status); - - *value = AccessorParams.FieldValue; - size = AccessorParams.FieldSize; - - return status; -} diff --git a/src/vendorcode/amd/pi/00630F01/binaryPI/FieldAccessors.h b/src/vendorcode/amd/pi/00630F01/binaryPI/FieldAccessors.h deleted file mode 100644 index bfbccbe164..0000000000 --- a/src/vendorcode/amd/pi/00630F01/binaryPI/FieldAccessors.h +++ /dev/null @@ -1,111 +0,0 @@ -/***************************************************************************** - * - * Copyright (c) 2013 - 2014, Sage Electronic Engineering, LLC - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ***************************************************************************/ -#ifndef _FIELDACCESSORS_H_ -#define _FIELDACCESSORS_H_ - -#include "AGESA.h" - -/// AGESA value name -typedef enum { - AMD_GLOBAL_USER_OPTIONS = 0x00020000, - AMD_GLOBAL_NUM_SOCKETS = 0x00020001, - AMD_GLOBAL_NUM_MODULES = 0x00020002, -} AGESA_FIELD_NAME; - -typedef AGESA_STATUS (*SETTER_ENTRY) ( - IN OUT VOID* value, - IN UINT32 size - ); - -typedef AGESA_STATUS (*GETTER_ENTRY) ( - IN OUT VOID** value, - IN UINT32 size - ); - -/// Accessor Interface. -typedef struct { - IN AMD_CONFIG_PARAMS StdHeader; ///< Standard configuration header - IN AGESA_FIELD_NAME FieldName; ///< The service to init - IN ALLOCATION_METHOD AllocationMethod; ///< For pointers, how to allocate space for copied data - IN OUT VOID *Struct; ///< The struct for the service. - IN OUT UINT32 FieldSize; ///< The size of the data value. - IN OUT VOID *FieldValue; ///< The value retrieved or set into the target structure. -} AMD_ACCESSOR_PARAMS; - - -/********************************************************************** - * Interface call: AmdSetValue - **********************************************************************/ -AGESA_STATUS -AmdGetValue ( - IN CONST AGESA_FIELD_NAME name, - IN OUT VOID** value, - IN UINT32 size - ); - -/********************************************************************** - * Interface call: AmdSetValue - **********************************************************************/ -AGESA_STATUS -AmdSetValue ( - IN CONST AGESA_FIELD_NAME name, - IN OUT VOID* value, - IN UINT32 size - ); - -/** - * Dispatch Table. - * - * The push high dispatcher uses this table to find what entries are currently in the build image. - */ -typedef struct { - UINT32 FunctionId; - SETTER_ENTRY SetValueEntryPoint; - GETTER_ENTRY GetValueEntryPoint; -} ACCESSOR_DISPATCH_TABLE; - -AGESA_STATUS -GetUserOptions( - IN OUT VOID** value, - IN UINT32 size - ); - -AGESA_STATUS -GetNumSockets( - IN OUT VOID** value, - IN UINT32 size - ); - -AGESA_STATUS -GetNumModules( - IN OUT VOID** value, - IN UINT32 size - ); - -#endif /* _FIELDACCESSORS_H_ */ diff --git a/src/vendorcode/amd/pi/00660F01/AMD.h b/src/vendorcode/amd/pi/00660F01/AMD.h index 54abf80af0..990261b32b 100644 --- a/src/vendorcode/amd/pi/00660F01/AMD.h +++ b/src/vendorcode/amd/pi/00660F01/AMD.h @@ -168,8 +168,8 @@ typedef enum { FCH_INIT_LATE = 0x00043000, FCH_INIT_S3_EARLY_RESTORE = 0x00044000, FCH_INIT_S3_LATE_RESTORE = 0x00045000, - AMD_SET_VALUE = 0x00081000, - AMD_GET_VALUE = 0x00082000 + AMD_SET_VALUE_invalid = 0x00081000, + AMD_GET_VALUE_invalid = 0x00082000 } AGESA_STRUCT_NAME; /* ResetType constant values */ diff --git a/src/vendorcode/amd/pi/00660F01/binaryPI/AGESA.c b/src/vendorcode/amd/pi/00660F01/binaryPI/AGESA.c index cb2f7f69f5..a4eef5ad86 100644 --- a/src/vendorcode/amd/pi/00660F01/binaryPI/AGESA.c +++ b/src/vendorcode/amd/pi/00660F01/binaryPI/AGESA.c @@ -42,7 +42,6 @@ // TODO This list needs to be pruned of anything that is not API #include "AGESA.h" #include "agesawrapper.h" -#include "FieldAccessors.h" #include "AcpiLib.h" #include "FchCommonCfg.h" #include "Fch.h" @@ -401,75 +400,3 @@ FchInitS3LateRestore ( Dispatcher = module->ModuleDispatcher; Dispatcher(FchDataPtr); } - -/********************************************************************** - * Interface call: AmdSetValue - **********************************************************************/ -AGESA_STATUS -AmdSetValue ( - IN CONST AGESA_FIELD_NAME name, - IN OUT VOID* value, - IN UINT32 size - ) -{ - AGESA_STATUS status = AGESA_UNSUPPORTED; - - MODULE_ENTRY Dispatcher = NULL; - const AMD_MODULE_HEADER* module = agesawrapper_locate_module(ModuleIdentifier); - - AMD_ACCESSOR_PARAMS AccessorParams = {}; - - if (!module) return status; - Dispatcher = module->ModuleDispatcher; - - AccessorParams.StdHeader.AltImageBasePtr = 0; - AccessorParams.StdHeader.CalloutPtr = NULL; - AccessorParams.StdHeader.Func = AMD_SET_VALUE; - AccessorParams.StdHeader.ImageBasePtr = 0; - - AccessorParams.AllocationMethod = ByHost; - AccessorParams.FieldName = name; - AccessorParams.FieldValue = value; - AccessorParams.FieldSize = size; - - status = Dispatcher(&AccessorParams); - return status; -} - -/********************************************************************** - * Interface call: AmdGetValue - **********************************************************************/ -AGESA_STATUS -AmdGetValue ( - IN CONST AGESA_FIELD_NAME name, - IN OUT VOID** value, - IN UINT32 size - ) -{ - AGESA_STATUS status = AGESA_UNSUPPORTED; - - MODULE_ENTRY Dispatcher = NULL; - const AMD_MODULE_HEADER* module = agesawrapper_locate_module(ModuleIdentifier); - - AMD_ACCESSOR_PARAMS AccessorParams = {}; - - if (!module) return status; - Dispatcher = module->ModuleDispatcher; - - AccessorParams.StdHeader.AltImageBasePtr = 0; - AccessorParams.StdHeader.CalloutPtr = NULL; - AccessorParams.StdHeader.Func = AMD_GET_VALUE; - AccessorParams.StdHeader.ImageBasePtr = 0; - - AccessorParams.AllocationMethod = ByHost; - AccessorParams.FieldName = name; - AccessorParams.FieldValue = *value; - AccessorParams.FieldSize = size; - - status = Dispatcher(&AccessorParams); - - *value = AccessorParams.FieldValue; - size = AccessorParams.FieldSize; - - return status; -} diff --git a/src/vendorcode/amd/pi/00660F01/binaryPI/FieldAccessors.h b/src/vendorcode/amd/pi/00660F01/binaryPI/FieldAccessors.h deleted file mode 100644 index 2d860c5005..0000000000 --- a/src/vendorcode/amd/pi/00660F01/binaryPI/FieldAccessors.h +++ /dev/null @@ -1,118 +0,0 @@ -/***************************************************************************** - * - * Copyright (c) 2013 - 2014, Sage Electronic Engineering, LLC - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ***************************************************************************/ -#ifndef _FIELDACCESSORS_H_ -#define _FIELDACCESSORS_H_ - -/// AGESA value name -typedef enum { - AMD_GLOBAL_USER_OPTIONS = 0x00020000, - AMD_GLOBAL_NUM_SOCKETS = 0x00020001, - AMD_GLOBAL_NUM_MODULES = 0x00020002, -} AGESA_FIELD_NAME; - -typedef AGESA_STATUS (*SETTER_ENTRY) ( - IN OUT VOID* value, - IN UINT32 size - ); - -typedef AGESA_STATUS (*GETTER_ENTRY) ( - IN OUT VOID** value, - IN UINT32 size - ); - -/// Accessor Interface. -typedef struct { - IN AMD_CONFIG_PARAMS StdHeader; ///< Standard configuration header - IN AGESA_FIELD_NAME FieldName; ///< The service to init - IN ALLOCATION_METHOD AllocationMethod; ///< For pointers, how to allocate space for copied data - IN OUT VOID *Struct; ///< The struct for the service. - IN OUT UINT32 FieldSize; ///< The size of the data value. - IN OUT VOID *FieldValue; ///< The value retrieved or set into the target structure. -} AMD_ACCESSOR_PARAMS; - -/********************************************************************** - * Interface call: AmdSetValue - **********************************************************************/ -AGESA_STATUS -AmdSetValueDispatch ( - IN OUT AMD_ACCESSOR_PARAMS *AccessorParams - ); - -AGESA_STATUS -AmdSetValue ( - IN CONST AGESA_FIELD_NAME name, - IN OUT VOID* value, - IN UINT32 size - ); - -/********************************************************************** - * Interface call: AmdGetValue - **********************************************************************/ -AGESA_STATUS -AmdGetValueDispatch ( - IN OUT AMD_ACCESSOR_PARAMS *AccessorParams - ); - -AGESA_STATUS -AmdGetValue ( - IN CONST AGESA_FIELD_NAME name, - IN OUT VOID** value, - IN UINT32 size - ); - -/** - * Dispatch Table. - * - * The push high dispatcher uses this table to find what entries are currently in the build image. - */ -typedef struct { - UINT32 FunctionId; - SETTER_ENTRY SetValueEntryPoint; - GETTER_ENTRY GetValueEntryPoint; -} ACCESSOR_DISPATCH_TABLE; - -AGESA_STATUS -GetUserOptions( - IN OUT VOID** value, - IN UINT32 size - ); - -AGESA_STATUS -GetNumSockets( - IN OUT VOID** value, - IN UINT32 size - ); - -AGESA_STATUS -GetNumModules( - IN OUT VOID** value, - IN UINT32 size - ); - -#endif /* _FIELDACCESSORS_H_ */ diff --git a/src/vendorcode/amd/pi/00730F01/AMD.h b/src/vendorcode/amd/pi/00730F01/AMD.h index 13fc29afeb..81612b555f 100644 --- a/src/vendorcode/amd/pi/00730F01/AMD.h +++ b/src/vendorcode/amd/pi/00730F01/AMD.h @@ -159,8 +159,8 @@ typedef enum { FCH_INIT_LATE = 0x00043000, FCH_INIT_S3_EARLY_RESTORE = 0x00044000, FCH_INIT_S3_LATE_RESTORE = 0x00045000, - AMD_SET_VALUE = 0x00081000, - AMD_GET_VALUE = 0x00082000, + AMD_SET_VALUE_invalid = 0x00081000, + AMD_GET_VALUE_invalid = 0x00082000, } AGESA_STRUCT_NAME; /* ResetType constant values */ diff --git a/src/vendorcode/amd/pi/00730F01/binaryPI/AGESA.c b/src/vendorcode/amd/pi/00730F01/binaryPI/AGESA.c index f233542863..7b1a98a7af 100644 --- a/src/vendorcode/amd/pi/00730F01/binaryPI/AGESA.c +++ b/src/vendorcode/amd/pi/00730F01/binaryPI/AGESA.c @@ -42,7 +42,6 @@ // TODO This list needs to be pruned of anything that is not API #include "AGESA.h" #include -#include "FieldAccessors.h" #include "AcpiLib.h" #include "FchCommonCfg.h" #include "Fch.h" @@ -510,75 +509,3 @@ ImcIdle ( { ((FCH_DATA_BLOCK*)FchDataPtr)->StdHeader->Func = 0; } - -/********************************************************************** - * Interface call: AmdSetValue - **********************************************************************/ -AGESA_STATUS -AmdSetValue ( - IN CONST AGESA_FIELD_NAME name, - IN OUT VOID* value, - IN UINT32 size - ) -{ - AGESA_STATUS status = AGESA_UNSUPPORTED; - - MODULE_ENTRY Dispatcher = NULL; - const AMD_MODULE_HEADER* module = agesawrapper_locate_module(ModuleIdentifier); - - AMD_ACCESSOR_PARAMS AccessorParams = {}; - - if (!module) return status; - Dispatcher = module->ModuleDispatcher; - - AccessorParams.StdHeader.AltImageBasePtr = 0; - AccessorParams.StdHeader.CalloutPtr = NULL; - AccessorParams.StdHeader.Func = AMD_SET_VALUE; - AccessorParams.StdHeader.ImageBasePtr = 0; - - AccessorParams.AllocationMethod = ByHost; - AccessorParams.FieldName = name; - AccessorParams.FieldValue = value; - AccessorParams.FieldSize = size; - - status = Dispatcher(&AccessorParams); - return status; -} - -/********************************************************************** - * Interface call: AmdGetValue - **********************************************************************/ -AGESA_STATUS -AmdGetValue ( - IN CONST AGESA_FIELD_NAME name, - IN OUT VOID** value, - IN UINT32 size - ) -{ - AGESA_STATUS status = AGESA_UNSUPPORTED; - - MODULE_ENTRY Dispatcher = NULL; - const AMD_MODULE_HEADER* module = agesawrapper_locate_module(ModuleIdentifier); - - AMD_ACCESSOR_PARAMS AccessorParams = {}; - - if (!module) return status; - Dispatcher = module->ModuleDispatcher; - - AccessorParams.StdHeader.AltImageBasePtr = 0; - AccessorParams.StdHeader.CalloutPtr = NULL; - AccessorParams.StdHeader.Func = AMD_GET_VALUE; - AccessorParams.StdHeader.ImageBasePtr = 0; - - AccessorParams.AllocationMethod = ByHost; - AccessorParams.FieldName = name; - AccessorParams.FieldValue = *value; - AccessorParams.FieldSize = size; - - status = Dispatcher(&AccessorParams); - - *value = AccessorParams.FieldValue; - size = AccessorParams.FieldSize; - - return status; -} diff --git a/src/vendorcode/amd/pi/00730F01/binaryPI/FieldAccessors.h b/src/vendorcode/amd/pi/00730F01/binaryPI/FieldAccessors.h deleted file mode 100644 index d50e8fc9cd..0000000000 --- a/src/vendorcode/amd/pi/00730F01/binaryPI/FieldAccessors.h +++ /dev/null @@ -1,111 +0,0 @@ -/***************************************************************************** - * - * Copyright (c) 2014, Sage Electronic Engineering, LLC - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ***************************************************************************/ -#ifndef _FIELDACCESSORS_H_ -#define _FIELDACCESSORS_H_ - -#include "AGESA.h" - -/// AGESA value name -typedef enum { - AMD_GLOBAL_USER_OPTIONS = 0x00020000, - AMD_GLOBAL_NUM_SOCKETS = 0x00020001, - AMD_GLOBAL_NUM_MODULES = 0x00020002, -} AGESA_FIELD_NAME; - -typedef AGESA_STATUS (*SETTER_ENTRY) ( - IN OUT VOID* value, - IN UINT32 size - ); - -typedef AGESA_STATUS (*GETTER_ENTRY) ( - IN OUT VOID** value, - IN UINT32 size - ); - -/// Accessor Interface. -typedef struct { - IN AMD_CONFIG_PARAMS StdHeader; ///< Standard configuration header - IN AGESA_FIELD_NAME FieldName; ///< The service to init - IN ALLOCATION_METHOD AllocationMethod; ///< For pointers, how to allocate space for copied data - IN OUT VOID *Struct; ///< The struct for the service. - IN OUT UINT32 FieldSize; ///< The size of the data value. - IN OUT VOID *FieldValue; ///< The value retrieved or set into the target structure. -} AMD_ACCESSOR_PARAMS; - - -/********************************************************************** - * Interface call: AmdSetValue - **********************************************************************/ -AGESA_STATUS -AmdGetValue ( - IN CONST AGESA_FIELD_NAME name, - IN OUT VOID** value, - IN UINT32 size - ); - -/********************************************************************** - * Interface call: AmdSetValue - **********************************************************************/ -AGESA_STATUS -AmdSetValue ( - IN CONST AGESA_FIELD_NAME name, - IN OUT VOID* value, - IN UINT32 size - ); - -/** - * Dispatch Table. - * - * The push high dispatcher uses this table to find what entries are currently in the build image. - */ -typedef struct { - UINT32 FunctionId; - SETTER_ENTRY SetValueEntryPoint; - GETTER_ENTRY GetValueEntryPoint; -} ACCESSOR_DISPATCH_TABLE; - -AGESA_STATUS -GetUserOptions( - IN OUT VOID** value, - IN UINT32 size - ); - -AGESA_STATUS -GetNumSockets( - IN OUT VOID** value, - IN UINT32 size - ); - -AGESA_STATUS -GetNumModules( - IN OUT VOID** value, - IN UINT32 size - ); - -#endif /* _FIELDACCESSORS_H_ */ From 2b297d92a78373358c0a0e304a8e41098e2da795 Mon Sep 17 00:00:00 2001 From: Matt DeVillier Date: Sun, 24 Nov 2019 17:36:38 -0600 Subject: [PATCH 0368/1242] mb/samsung: remove header guards for SuperIO MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit SuperIO header needs to be included regardless of Kconfig option, otherwise compilation fails due to missing prototype for try_enabling_LPC47N207_uart() if DRIVERS_UART_8250IO is not set. Change-Id: I0eda4aee2cbb114bde33e862940a64675469693d Signed-off-by: Matt DeVillier Reviewed-on: https://review.coreboot.org/c/coreboot/+/37183 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki Reviewed-by: Nico Huber Reviewed-by: Angel Pons --- src/mainboard/samsung/lumpy/early_init.c | 4 +--- src/mainboard/samsung/stumpy/early_init.c | 2 -- 2 files changed, 1 insertion(+), 5 deletions(-) diff --git a/src/mainboard/samsung/lumpy/early_init.c b/src/mainboard/samsung/lumpy/early_init.c index af4e55dc22..28cd5c336e 100644 --- a/src/mainboard/samsung/lumpy/early_init.c +++ b/src/mainboard/samsung/lumpy/early_init.c @@ -29,10 +29,8 @@ #include #include #include -#include "option_table.h" -#if CONFIG(DRIVERS_UART_8250IO) #include -#endif +#include "option_table.h" void bootblock_mainboard_early_init(void) { diff --git a/src/mainboard/samsung/stumpy/early_init.c b/src/mainboard/samsung/stumpy/early_init.c index 7fca8adfcc..157fdf18e4 100644 --- a/src/mainboard/samsung/stumpy/early_init.c +++ b/src/mainboard/samsung/stumpy/early_init.c @@ -29,9 +29,7 @@ #include #include #include -#if CONFIG(DRIVERS_UART_8250IO) #include -#endif /* Stumpy USB Reset Disable defined in cmos.layout */ #if CONFIG(USE_OPTION_TABLE) From c61d415701a42c04bf5b24cfc4f07a5b4ee75d81 Mon Sep 17 00:00:00 2001 From: Bill XIE Date: Thu, 21 Nov 2019 18:16:12 +0800 Subject: [PATCH 0369/1242] util/sconfig: Fix illogical override rule for resource The old logic only uses the type to identify resources, which makes a resource in override tree overriding the first resource with the same type (but possibly different index) in base tree, and resources with same type (but again different index) in override tree overriding each other. Resources had better be identified with both their type and index. Change-Id: I7cd88905a8d6d1c7c6c03833835df2fba83047ea Signed-off-by: Bill XIE Reviewed-on: https://review.coreboot.org/c/coreboot/+/37109 Reviewed-by: Nico Huber Tested-by: build bot (Jenkins) --- util/sconfig/main.c | 19 ++++++++++++++----- 1 file changed, 14 insertions(+), 5 deletions(-) diff --git a/util/sconfig/main.c b/util/sconfig/main.c index 5c2333309b..3b60e2a87f 100644 --- a/util/sconfig/main.c +++ b/util/sconfig/main.c @@ -1072,6 +1072,16 @@ static int device_match(struct device *a, struct device *b) b->chip_instance->chip)); } +/* + * Match resource nodes from base and override tree to see if they are the same + * node. + */ +static int res_match(struct resource *a, struct resource *b) +{ + return ((a->type == b->type) && + (a->index == b->index)); +} + /* * Walk through the override subtree in breadth-first manner starting at node to * see if chip_instance pointer of the node is same as chip_instance pointer of @@ -1104,8 +1114,7 @@ static void update_resource(struct device *dev, struct resource *res) struct resource *base_res = dev->res; while (base_res) { - if (base_res->type == res->type) { - base_res->index = res->index; + if (res_match(base_res, res)) { base_res->base = res->base; return; } @@ -1195,9 +1204,9 @@ static void override_devicetree(struct bus *base_parent, * | | | * | res | Each resource that is present in override | * | | device is copied over to base device: | - * | | 1. If resource of same type is present in | - * | | base device, then index and base of the | - * | | resource is copied. | + * | | 1. If resource of same type and index is | + * | | present in base device, then base of | + * | | the resource is copied. | * | | 2. If not, then a new resource is allocated| * | | under the base device using type, index | * | | and base from override res. | From 8d82109c08163fa82263b35e9aa0a270a795a5f8 Mon Sep 17 00:00:00 2001 From: Arthur Heymans Date: Mon, 25 Nov 2019 06:56:04 +0100 Subject: [PATCH 0370/1242] nb/intel/sandybridge: Fix mrc.bin path MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The mrc.bin uses a lot of stack. The BSP stack size is kept the same for both romstage bootpaths, mrc.bin and native, in order for the CAR symbol/setups to be compatible. Change-Id: Ic422980ca1a0549b6937e30a433ce52e0d7a595c Signed-off-by: Arthur Heymans Reviewed-on: https://review.coreboot.org/c/coreboot/+/37185 Reviewed-by: Kyösti Mälkki Reviewed-by: Matt DeVillier Tested-by: build bot (Jenkins) --- src/northbridge/intel/sandybridge/Kconfig | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/src/northbridge/intel/sandybridge/Kconfig b/src/northbridge/intel/sandybridge/Kconfig index 0502b50014..7a27d098c5 100644 --- a/src/northbridge/intel/sandybridge/Kconfig +++ b/src/northbridge/intel/sandybridge/Kconfig @@ -74,7 +74,10 @@ config DCACHE_RAM_BASE config DCACHE_BSP_STACK_SIZE hex - default 0x2800 + default 0x10000 + help + The amount of BSP stack anticipated in bootblock and + other stages. if USE_NATIVE_RAMINIT From 2ed6848ea3530beb234a3b9d5c843a54688d1d3c Mon Sep 17 00:00:00 2001 From: Arthur Heymans Date: Sun, 24 Nov 2019 19:05:47 +0100 Subject: [PATCH 0371/1242] soc/amd/exit_car.S: Drop redundant enabling cache This is already done in arch/x86/exit_car.S Change-Id: Ie954aa11d5e76aaa3e2185ba552aafe8d075feb6 Signed-off-by: Arthur Heymans Reviewed-on: https://review.coreboot.org/c/coreboot/+/37179 Tested-by: build bot (Jenkins) Reviewed-by: Marshall Dawson --- src/soc/amd/common/block/cpu/car/exit_car.S | 5 ----- 1 file changed, 5 deletions(-) diff --git a/src/soc/amd/common/block/cpu/car/exit_car.S b/src/soc/amd/common/block/cpu/car/exit_car.S index f9d056e599..16880e71a5 100644 --- a/src/soc/amd/common/block/cpu/car/exit_car.S +++ b/src/soc/amd/common/block/cpu/car/exit_car.S @@ -29,9 +29,4 @@ chipset_teardown_car: AMD_DISABLE_STACK - /* enable cache */ - movl %cr0, %eax - andl $(~(CR0_CD | CR0_NW)), %eax - movl %eax, %cr0 - jmp *%esp From 515ef38db40cc44592770c00be8e4980bbaccc69 Mon Sep 17 00:00:00 2001 From: Andrey Petrov Date: Fri, 15 Nov 2019 13:19:08 -0800 Subject: [PATCH 0372/1242] arch/x86: SMBIOS: Improve core count reporting Current code uses CPUID leaf 0x1, EBX bits 16:23 to determine number for "core count". However, it turns out this number has little to do with real number of cores. According to SDM vol 2A, it stays for "maximum number of addressable IDs for logical processors in this physical package". This does not seem to take into account fusing of giving processor. The new code determines 'core count' by dividing thread-level cpus by reported logical cores. This seems to be the only way to arrive to number of cores as it is reported in official CPU datasheet. TEST=tested on OCP monolake Change-Id: Id4ba9e3079f92ffe38f9104ffcfafe62582dd259 Signed-off-by: Andrey Petrov Reviewed-on: https://review.coreboot.org/c/coreboot/+/36941 Tested-by: build bot (Jenkins) Reviewed-by: Werner Zeh --- src/arch/x86/smbios.c | 21 ++++++++++++++++++++- 1 file changed, 20 insertions(+), 1 deletion(-) diff --git a/src/arch/x86/smbios.c b/src/arch/x86/smbios.c index 7e05408242..a599addb61 100644 --- a/src/arch/x86/smbios.c +++ b/src/arch/x86/smbios.c @@ -647,7 +647,26 @@ static int smbios_write_type4(unsigned long *current, int handle) t->processor_version = smbios_processor_name(t->eos); t->processor_family = (res.eax > 0) ? 0x0c : 0x6; t->processor_type = 3; /* System Processor */ - t->core_count = (res.ebx >> 16) & 0xff; + /* + * If CPUID leaf 11 is available, calculate "core count" by dividing + * SMT_ID (logical processors in a core) by Core_ID (number of cores). + * This seems to be the way to arrive to a number of cores mentioned on + * ark.intel.com. + */ + if (cpu_have_cpuid() && cpuid_get_max_func() >= 0xb) { + uint32_t leaf_b_cores = 0, leaf_b_threads = 0; + res = cpuid_ext(0xb, 1); + leaf_b_cores = res.ebx; + res = cpuid_ext(0xb, 0); + leaf_b_threads = res.ebx; + /* if hyperthreading is not available, pretend this is 1 */ + if (leaf_b_threads == 0) { + leaf_b_threads = 1; + } + t->core_count = leaf_b_cores / leaf_b_threads; + } else { + t->core_count = (res.ebx >> 16) & 0xff; + } /* Assume we enable all the cores always, capped only by MAX_CPUS */ t->core_enabled = MIN(t->core_count, CONFIG_MAX_CPUS); t->l1_cache_handle = 0xffff; From 3397ef9627c29319290126892744ce1c9bcc3d79 Mon Sep 17 00:00:00 2001 From: Jacob Garber Date: Sun, 24 Nov 2019 13:09:22 -0700 Subject: [PATCH 0373/1242] soc/nvidia/tegra: Remove duplicate macros These macros are already defined in stdbool.h or commonlib/helpers.h Change-Id: I6e474fc233d3134c89c29840471797b1e0c9e3c3 Signed-off-by: Jacob Garber Reviewed-on: https://review.coreboot.org/c/coreboot/+/37182 Tested-by: build bot (Jenkins) Reviewed-by: HAOUAS Elyes Reviewed-by: Julius Werner --- src/soc/nvidia/tegra/types.h | 25 ------------------------- 1 file changed, 25 deletions(-) diff --git a/src/soc/nvidia/tegra/types.h b/src/soc/nvidia/tegra/types.h index 9af4b20e2f..0cbbd5d9d3 100644 --- a/src/soc/nvidia/tegra/types.h +++ b/src/soc/nvidia/tegra/types.h @@ -26,29 +26,4 @@ #define IS_ERR_PTR(ptr) \ (ptr == (void *)-EPTR) -#ifndef bool -#define bool int -#endif - -#ifndef false -#define false 0 -#endif - -#ifndef true -#define true 1 -#endif - -#ifndef container_of -/** - * container_of - cast a member of a structure out to the containing structure - * @ptr: the pointer to the member. - * @type: the type of the container struct this is embedded in. - * @member: the name of the member within the struct. - * - */ -#define container_of(ptr, type, member) ({ \ - const typeof( ((type *)0)->member ) *__mptr = (ptr); \ - (type *)( (char *)__mptr - offsetof(type,member) );}) -#endif - #endif /* __TEGRA_MISC_TYPES_H__ */ From a3eb1252383a51775f6c470b5a44d83bd6c913c5 Mon Sep 17 00:00:00 2001 From: Jacob Garber Date: Sun, 24 Nov 2019 13:11:39 -0700 Subject: [PATCH 0374/1242] security/vboot: Remove duplicate offsetof() definition This macro is already defined in commonlib/helpers.h Change-Id: I1fce2936757b13807e254f4a844f583b938bf349 Signed-off-by: Jacob Garber Reviewed-on: https://review.coreboot.org/c/coreboot/+/37181 Tested-by: build bot (Jenkins) Reviewed-by: HAOUAS Elyes Reviewed-by: Alex James Reviewed-by: Julius Werner --- src/security/vboot/secdata_tpm.c | 4 ---- 1 file changed, 4 deletions(-) diff --git a/src/security/vboot/secdata_tpm.c b/src/security/vboot/secdata_tpm.c index 38a1810d7f..2fbb30b008 100644 --- a/src/security/vboot/secdata_tpm.c +++ b/src/security/vboot/secdata_tpm.c @@ -40,10 +40,6 @@ #include #include -#ifndef offsetof -#define offsetof(A,B) __builtin_offsetof(A,B) -#endif - #ifdef FOR_TEST #include #define VBDEBUG(format, args...) printf(format, ## args) From 47a6603f34481e1226c106002c9fd7fb3d0c2c04 Mon Sep 17 00:00:00 2001 From: Arthur Heymans Date: Fri, 25 Oct 2019 23:43:14 +0200 Subject: [PATCH 0375/1242] sb/intel/common/spi: Add Baytrail/Braswell support The mechanism for getting the SPIBAR is little different. Tested on Intel Minnowboard Turbot. Change-Id: Ib14f185eab8bf708ad82b06c7a7ce586744318fd Signed-off-by: Arthur Heymans Reviewed-on: https://review.coreboot.org/c/coreboot/+/36342 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber --- src/soc/intel/broadwell/Kconfig | 2 +- src/southbridge/intel/bd82x6x/Kconfig | 2 +- src/southbridge/intel/common/Kconfig | 12 +++++++ src/southbridge/intel/common/spi.c | 48 ++++++++++++++++++------- src/southbridge/intel/i82801gx/Kconfig | 2 +- src/southbridge/intel/i82801ix/Kconfig | 2 +- src/southbridge/intel/i82801jx/Kconfig | 2 +- src/southbridge/intel/ibexpeak/Kconfig | 2 +- src/southbridge/intel/lynxpoint/Kconfig | 2 +- 9 files changed, 55 insertions(+), 19 deletions(-) diff --git a/src/soc/intel/broadwell/Kconfig b/src/soc/intel/broadwell/Kconfig index 07bcf22b1d..21c9b6f12a 100644 --- a/src/soc/intel/broadwell/Kconfig +++ b/src/soc/intel/broadwell/Kconfig @@ -20,7 +20,7 @@ config CPU_SPECIFIC_OPTIONS select HAVE_SMI_HANDLER select SOUTHBRIDGE_INTEL_COMMON_RESET select SOUTHBRIDGE_INTEL_COMMON_RTC - select SOUTHBRIDGE_INTEL_COMMON_SPI + select SOUTHBRIDGE_INTEL_COMMON_SPI_ICH9 select HAVE_USBDEBUG select IOAPIC select REG_SCRIPT diff --git a/src/southbridge/intel/bd82x6x/Kconfig b/src/southbridge/intel/bd82x6x/Kconfig index 1c7e9b7da6..8b8f6b361a 100644 --- a/src/southbridge/intel/bd82x6x/Kconfig +++ b/src/southbridge/intel/bd82x6x/Kconfig @@ -27,7 +27,7 @@ config SOUTH_BRIDGE_OPTIONS # dummy select SOUTHBRIDGE_INTEL_COMMON_FINALIZE select SOUTHBRIDGE_INTEL_COMMON_RCBA_PIRQ select SOUTHBRIDGE_INTEL_COMMON_SMBUS - select SOUTHBRIDGE_INTEL_COMMON_SPI + select SOUTHBRIDGE_INTEL_COMMON_SPI_ICH9 select SOUTHBRIDGE_INTEL_COMMON_PMCLIB select SOUTHBRIDGE_INTEL_COMMON_PMBASE select SOUTHBRIDGE_INTEL_COMMON_RTC diff --git a/src/southbridge/intel/common/Kconfig b/src/southbridge/intel/common/Kconfig index 18bcd2e4a6..d1b6bf6024 100644 --- a/src/southbridge/intel/common/Kconfig +++ b/src/southbridge/intel/common/Kconfig @@ -24,6 +24,18 @@ config SOUTHBRIDGE_INTEL_COMMON_SPI select SPI_FLASH select BOOT_DEVICE_SUPPORTS_WRITES +config SOUTHBRIDGE_INTEL_COMMON_SPI_ICH7 + def_bool n + select SOUTHBRIDGE_INTEL_COMMON_SPI + +config SOUTHBRIDGE_INTEL_COMMON_SPI_ICH9 + def_bool n + select SOUTHBRIDGE_INTEL_COMMON_SPI + +config SOUTHBRIDGE_INTEL_COMMON_SPI_SILVERMONT + def_bool n + select SOUTHBRIDGE_INTEL_COMMON_SPI + config SOUTHBRIDGE_INTEL_COMMON_PIRQ_ACPI_GEN def_bool n diff --git a/src/southbridge/intel/common/spi.c b/src/southbridge/intel/common/spi.c index a84a0dfb8f..4926df9d50 100644 --- a/src/southbridge/intel/common/spi.c +++ b/src/southbridge/intel/common/spi.c @@ -271,11 +271,36 @@ static void ich_set_bbar(uint32_t minaddr) #define MENU_BYTES member_size(struct ich9_spi_regs, opmenu) #endif +#define RCBA 0xf0 +#define SBASE 0x54 + +#ifdef __SIMPLE_DEVICE__ +static void *get_spi_bar(pci_devfn_t dev) +#else +static void *get_spi_bar(struct device *dev) +#endif +{ + uintptr_t rcba; /* Root Complex Register Block */ + uintptr_t sbase; + + if (CONFIG(SOUTHBRIDGE_INTEL_I82801GX)) { + rcba = pci_read_config32(dev, RCBA); + return (void *)((rcba & 0xffffc000) + 0x3020); + } + if (CONFIG(SOUTHBRIDGE_INTEL_COMMON_SPI_SILVERMONT)) { + sbase = pci_read_config32(dev, SBASE); + sbase &= ~0x1ff; + return (void *)sbase; + } + if (CONFIG(SOUTHBRIDGE_INTEL_COMMON_SPI_ICH9)) { + rcba = pci_read_config32(dev, RCBA); + return (void *)((rcba & 0xffffc000) + 0x3800); + } +} + void spi_init(void) { struct ich_spi_controller *cntlr = car_get_var_ptr(&g_cntlr); - uint8_t *rcrb; /* Root Complex Register Block */ - uint32_t rcba; /* Root Complex Base Address */ uint8_t bios_cntl; struct ich9_spi_regs *ich9_spi; struct ich7_spi_regs *ich7_spi; @@ -287,11 +312,8 @@ void spi_init(void) struct device *dev = pcidev_on_root(31, 0); #endif - rcba = pci_read_config32(dev, 0xf0); - /* Bits 31-14 are the base address, 13-1 are reserved, 0 is enable. */ - rcrb = (uint8_t *)(rcba & 0xffffc000); if (CONFIG(SOUTHBRIDGE_INTEL_I82801GX)) { - ich7_spi = (struct ich7_spi_regs *)(rcrb + 0x3020); + ich7_spi = get_spi_bar(dev); cntlr->ich7_spi = ich7_spi; cntlr->opmenu = ich7_spi->opmenu; cntlr->menubytes = sizeof(ich7_spi->opmenu); @@ -306,7 +328,7 @@ void spi_init(void) cntlr->fpr = &ich7_spi->pbr[0]; cntlr->fpr_max = 3; } else { - ich9_spi = (struct ich9_spi_regs *)(rcrb + 0x3800); + ich9_spi = get_spi_bar(dev); cntlr->ich9_spi = ich9_spi; hsfs = readw_(&ich9_spi->hsfs); cntlr->hsfs = hsfs; @@ -333,11 +355,13 @@ void spi_init(void) ich_set_bbar(0); - /* Disable the BIOS write protect so write commands are allowed. */ - bios_cntl = pci_read_config8(dev, 0xdc); - /* Deassert SMM BIOS Write Protect Disable. */ - bios_cntl &= ~(1 << 5); - pci_write_config8(dev, 0xdc, bios_cntl | 0x1); + if (CONFIG(SOUTHBRIDGE_INTEL_I82801GX) || CONFIG(SOUTHBRIDGE_INTEL_COMMON_SPI_ICH9)) { + /* Disable the BIOS write protect so write commands are allowed. */ + bios_cntl = pci_read_config8(dev, 0xdc); + /* Deassert SMM BIOS Write Protect Disable. */ + bios_cntl &= ~(1 << 5); + pci_write_config8(dev, 0xdc, bios_cntl | 0x1); + } } static int spi_locked(void) diff --git a/src/southbridge/intel/i82801gx/Kconfig b/src/southbridge/intel/i82801gx/Kconfig index 2d95fc2371..deb11299e9 100644 --- a/src/southbridge/intel/i82801gx/Kconfig +++ b/src/southbridge/intel/i82801gx/Kconfig @@ -22,7 +22,7 @@ config SOUTHBRIDGE_INTEL_I82801GX select COMMON_FADT select SOUTHBRIDGE_INTEL_COMMON_GPIO select SOUTHBRIDGE_INTEL_COMMON_SMBUS - select SOUTHBRIDGE_INTEL_COMMON_SPI if BOOT_DEVICE_SPI_FLASH + select SOUTHBRIDGE_INTEL_COMMON_SPI_ICH7 if BOOT_DEVICE_SPI_FLASH select SOUTHBRIDGE_INTEL_COMMON_PMCLIB select SOUTHBRIDGE_INTEL_COMMON_PMBASE select HAVE_INTEL_CHIPSET_LOCKDOWN diff --git a/src/southbridge/intel/i82801ix/Kconfig b/src/southbridge/intel/i82801ix/Kconfig index 836397822a..1e2ee475a6 100644 --- a/src/southbridge/intel/i82801ix/Kconfig +++ b/src/southbridge/intel/i82801ix/Kconfig @@ -17,7 +17,7 @@ config SOUTHBRIDGE_INTEL_I82801IX bool select SOUTHBRIDGE_INTEL_COMMON_SMBUS - select SOUTHBRIDGE_INTEL_COMMON_SPI if !BOARD_EMULATION_QEMU_X86_Q35 + select SOUTHBRIDGE_INTEL_COMMON_SPI_ICH9 if !BOARD_EMULATION_QEMU_X86_Q35 select SOUTHBRIDGE_INTEL_COMMON_RCBA_PIRQ select SOUTHBRIDGE_INTEL_COMMON_PMBASE select SOUTHBRIDGE_INTEL_COMMON_RTC diff --git a/src/southbridge/intel/i82801jx/Kconfig b/src/southbridge/intel/i82801jx/Kconfig index 161290f852..0e756a8da7 100644 --- a/src/southbridge/intel/i82801jx/Kconfig +++ b/src/southbridge/intel/i82801jx/Kconfig @@ -17,7 +17,7 @@ config SOUTHBRIDGE_INTEL_I82801JX bool select SOUTHBRIDGE_INTEL_COMMON_SMBUS - select SOUTHBRIDGE_INTEL_COMMON_SPI + select SOUTHBRIDGE_INTEL_COMMON_SPI_ICH9 select SOUTHBRIDGE_INTEL_COMMON_RCBA_PIRQ select SOUTHBRIDGE_INTEL_COMMON_PMCLIB select SOUTHBRIDGE_INTEL_COMMON_PMBASE diff --git a/src/southbridge/intel/ibexpeak/Kconfig b/src/southbridge/intel/ibexpeak/Kconfig index f9723fb2d8..f94e7a8e72 100644 --- a/src/southbridge/intel/ibexpeak/Kconfig +++ b/src/southbridge/intel/ibexpeak/Kconfig @@ -29,7 +29,7 @@ config SOUTH_BRIDGE_OPTIONS # dummy select SOUTHBRIDGE_INTEL_COMMON_FINALIZE select SOUTHBRIDGE_INTEL_COMMON_RCBA_PIRQ select SOUTHBRIDGE_INTEL_COMMON_SMBUS - select SOUTHBRIDGE_INTEL_COMMON_SPI + select SOUTHBRIDGE_INTEL_COMMON_SPI_ICH9 select SOUTHBRIDGE_INTEL_COMMON_SMM select SOUTHBRIDGE_INTEL_COMMON_PMCLIB select SOUTHBRIDGE_INTEL_COMMON_PMBASE diff --git a/src/southbridge/intel/lynxpoint/Kconfig b/src/southbridge/intel/lynxpoint/Kconfig index ef071f28ed..87f72984f4 100644 --- a/src/southbridge/intel/lynxpoint/Kconfig +++ b/src/southbridge/intel/lynxpoint/Kconfig @@ -22,7 +22,7 @@ config SOUTH_BRIDGE_OPTIONS # dummy def_bool y select ACPI_INTEL_HARDWARE_SLEEP_VALUES select SOUTHBRIDGE_INTEL_COMMON_SMBUS - select SOUTHBRIDGE_INTEL_COMMON_SPI + select SOUTHBRIDGE_INTEL_COMMON_SPI_ICH9 select SOUTHBRIDGE_INTEL_COMMON_ACPI_MADT select SOUTHBRIDGE_INTEL_COMMON_FINALIZE select SOUTHBRIDGE_INTEL_COMMON_PMCLIB From 026863b2ffa132e1f206a86b3fbf9360c86138d3 Mon Sep 17 00:00:00 2001 From: Arthur Heymans Date: Thu, 21 Nov 2019 08:24:02 +0100 Subject: [PATCH 0376/1242] southbridge/intel/common/spi.c: Define __SIMPLE_DEVICE__ This simplifies PCI config space accessors. Change-Id: Idf0f90ee2dc1dcb0003ef5d56eff44ca9a5634e7 Signed-off-by: Arthur Heymans Reviewed-on: https://review.coreboot.org/c/coreboot/+/37079 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber --- src/southbridge/intel/common/spi.c | 10 ++-------- 1 file changed, 2 insertions(+), 8 deletions(-) diff --git a/src/southbridge/intel/common/spi.c b/src/southbridge/intel/common/spi.c index 4926df9d50..3b7842de7d 100644 --- a/src/southbridge/intel/common/spi.c +++ b/src/southbridge/intel/common/spi.c @@ -15,6 +15,8 @@ * GNU General Public License for more details. */ +#define __SIMPLE_DEVICE__ + /* This file is derived from the flashrom project. */ #include #include @@ -274,11 +276,7 @@ static void ich_set_bbar(uint32_t minaddr) #define RCBA 0xf0 #define SBASE 0x54 -#ifdef __SIMPLE_DEVICE__ static void *get_spi_bar(pci_devfn_t dev) -#else -static void *get_spi_bar(struct device *dev) -#endif { uintptr_t rcba; /* Root Complex Register Block */ uintptr_t sbase; @@ -306,11 +304,7 @@ void spi_init(void) struct ich7_spi_regs *ich7_spi; uint16_t hsfs; -#ifdef __SIMPLE_DEVICE__ pci_devfn_t dev = PCI_DEV(0, 31, 0); -#else - struct device *dev = pcidev_on_root(31, 0); -#endif if (CONFIG(SOUTHBRIDGE_INTEL_I82801GX)) { ich7_spi = get_spi_bar(dev); From 433acc2d3d6cfb3d16030cbba7be9a5defccf057 Mon Sep 17 00:00:00 2001 From: Weiyi Lu Date: Fri, 22 Nov 2019 12:00:24 +0800 Subject: [PATCH 0377/1242] soc/mediatek/mt8183: disable BBLPM of DCXO core When we only enable XO_SOC and mask most BBLPM requests, the BBLPM HW arbiter will have DCXO core to enter Baseband Low-Power Mode(BBLPM). Under BBLPM mode, inaccurate(about 1.5KHz offset) 26MHz clocks from crystal is provided and crystal voltage will drop from 1.8V to 0.7V or lower. In order to ensure the stability by always outputting an accuarate system clock when system is running. We should disable BBLPM when only XO_SOC enabled. BRANCH=kukui TEST=accurate 26MHz provided and correct crystal voltage swing Change-Id: Iea72a964507a19735cf92e3774cd8a94c06545b2 Signed-off-by: Weiyi Lu Reviewed-on: https://review.coreboot.org/c/coreboot/+/37136 Reviewed-by: Hung-Te Lin Tested-by: build bot (Jenkins) --- src/soc/mediatek/mt8183/rtc.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/soc/mediatek/mt8183/rtc.c b/src/soc/mediatek/mt8183/rtc.c index 19b717cc82..6e17a309fe 100644 --- a/src/soc/mediatek/mt8183/rtc.c +++ b/src/soc/mediatek/mt8183/rtc.c @@ -435,8 +435,8 @@ void mt6358_dcxo_disable_unused(void) { /* Disable clock buffer XO_CEL */ rtc_write(PMIC_RG_DCXO_CW00_CLR, 0x0800); - /* Mask bblpm */ - rtc_write(PMIC_RG_DCXO_CW23, 0x0053); + /* Mask bblpm request and switch off bblpm mode */ + rtc_write(PMIC_RG_DCXO_CW23, 0x0052); } /* the rtc boot flow entry */ From e1470ea6a3b83473b5fca54b93d3c12834660980 Mon Sep 17 00:00:00 2001 From: Subrata Banik Date: Mon, 18 Nov 2019 14:08:08 +0530 Subject: [PATCH 0378/1242] soc/intel/cannonlake: Add chip config to override CPU flex ratio This patch provides options to override descriptor default CPU flex ratio from coreboot code. cpu_ratio_override to provide the required CPU ratio. Note: Don't override the flex ratio if cpu_ratio is 0. BUG=b:142264107 TEST=Without override flex_ratio is 0 and verified booting to OS after overriding with flex_ratio value 5. Change-Id: Ib01650f52f3d402f669e7e7f5b28a648b86f08ec Signed-off-by: Subrata Banik Reviewed-on: https://review.coreboot.org/c/coreboot/+/36864 Tested-by: build bot (Jenkins) Reviewed-by: Tim Wawrzynczak --- src/soc/intel/cannonlake/chip.h | 13 +++++++++++++ src/soc/intel/cannonlake/romstage/fsp_params.c | 12 ++++++++---- 2 files changed, 21 insertions(+), 4 deletions(-) diff --git a/src/soc/intel/cannonlake/chip.h b/src/soc/intel/cannonlake/chip.h index 17afdd10da..507290f504 100644 --- a/src/soc/intel/cannonlake/chip.h +++ b/src/soc/intel/cannonlake/chip.h @@ -424,6 +424,19 @@ struct soc_intel_cannonlake_config { * Bit 0: MISCCFG_GPDLCGEN */ uint8_t gpio_pm[TOTAL_GPIO_COMM]; + + /* + * Override CPU flex ratio value: + * CPU ratio value controls the maximum processor non-turbo ratio. + * Valid Range 0 to 63. + * + * In general descriptor provides option to set default cpu flex ratio. + * Default cpu flex ratio is 0 ensures booting with non-turbo max frequency. + * Thats the reason FSP skips cpu_ratio override if cpu_ratio is 0. + * + * Only override CPU flex ratio if don't want to boot with non-turbo max. + */ + uint8_t cpu_ratio_override; }; typedef struct soc_intel_cannonlake_config config_t; diff --git a/src/soc/intel/cannonlake/romstage/fsp_params.c b/src/soc/intel/cannonlake/romstage/fsp_params.c index 996c13577e..5c74d4a1e0 100644 --- a/src/soc/intel/cannonlake/romstage/fsp_params.c +++ b/src/soc/intel/cannonlake/romstage/fsp_params.c @@ -74,10 +74,14 @@ static void soc_memory_init_params(FSP_M_CONFIG *m_cfg, const config_t *config) m_cfg->SkipMpInit = !CONFIG_USE_INTEL_FSP_MP_INIT; #endif - /* Set CpuRatio to match existing MSR value */ - msr_t flex_ratio; - flex_ratio = rdmsr(MSR_FLEX_RATIO); - m_cfg->CpuRatio = (flex_ratio.lo >> 8) & 0xff; + if (config->cpu_ratio_override) { + m_cfg->CpuRatio = config->cpu_ratio_override; + } else { + /* Set CpuRatio to match existing MSR value */ + msr_t flex_ratio; + flex_ratio = rdmsr(MSR_FLEX_RATIO); + m_cfg->CpuRatio = (flex_ratio.lo >> 8) & 0xff; + } /* If ISH is enabled, enable ISH elements */ if (!dev) From 0d2dbcab5f08329567c2acbf54bcb7bd9ad5a8f6 Mon Sep 17 00:00:00 2001 From: Krystian Hebel Date: Tue, 23 Apr 2019 19:28:16 +0200 Subject: [PATCH 0379/1242] amd/pi/00730F01: Add support without BINARYPI_LEGACY_WRAPPER MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit A stripped down version (without S3) of ../agesa/family*/state_machine.c is used to provide platform-specific hooks. TEST=boot PC Engines apu2 with POSTCAR_STAGE patch Change-Id: I700a7d8d3c77ee0525b2c764c720ab5bf39925f8 Signed-off-by: Krystian Hebel Signed-off-by: Michał Żygowski Reviewed-on: https://review.coreboot.org/c/coreboot/+/32421 Reviewed-by: Kyösti Mälkki Reviewed-by: Marshall Dawson Tested-by: build bot (Jenkins) --- src/northbridge/amd/pi/00730F01/Makefile.inc | 5 ++ .../amd/pi/00730F01/state_machine.c | 86 +++++++++++++++++++ 2 files changed, 91 insertions(+) create mode 100644 src/northbridge/amd/pi/00730F01/state_machine.c diff --git a/src/northbridge/amd/pi/00730F01/Makefile.inc b/src/northbridge/amd/pi/00730F01/Makefile.inc index 39c3ee61ba..94cf72e5ad 100644 --- a/src/northbridge/amd/pi/00730F01/Makefile.inc +++ b/src/northbridge/amd/pi/00730F01/Makefile.inc @@ -17,3 +17,8 @@ romstage-y += dimmSpd.c ramstage-y += northbridge.c ramstage-y += iommu.c + +ifneq ($(CONFIG_BINARYPI_LEGACY_WRAPPER), y) +romstage-y += state_machine.c +ramstage-y += state_machine.c +endif diff --git a/src/northbridge/amd/pi/00730F01/state_machine.c b/src/northbridge/amd/pi/00730F01/state_machine.c new file mode 100644 index 0000000000..b567f38e2e --- /dev/null +++ b/src/northbridge/amd/pi/00730F01/state_machine.c @@ -0,0 +1,86 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016 Kyösti Mälkki + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include "Porting.h" +#include "AGESA.h" + +#include +#include +#include + +void platform_BeforeInitReset(struct sysinfo *cb, AMD_RESET_PARAMS *Reset) +{ +} + +void platform_BeforeInitEarly(struct sysinfo *cb, AMD_EARLY_PARAMS *Early) +{ +} + +void platform_BeforeInitPost(struct sysinfo *cb, AMD_POST_PARAMS *Post) +{ +} + +void platform_AfterInitPost(struct sysinfo *cb, AMD_POST_PARAMS *Post) +{ + /* If UMA is enabled we currently have it below TOP_MEM as well. + * UMA may or may not be cacheable, so Sub4GCacheTop could be + * higher than UmaBase. With UMA_NONE we see UmaBase==0. */ + if (Post->MemConfig.UmaBase) + backup_top_of_low_cacheable(Post->MemConfig.UmaBase << 16); + else + backup_top_of_low_cacheable(Post->MemConfig.Sub4GCacheTop); +} + + +void platform_BeforeInitEnv(struct sysinfo *cb, AMD_ENV_PARAMS *Env) +{ + EmptyHeap(); +} + +void platform_AfterInitEnv(struct sysinfo *cb, AMD_ENV_PARAMS *Env) +{ +} + +void platform_BeforeInitMid(struct sysinfo *cb, AMD_MID_PARAMS *Mid) +{ + amd_initcpuio(); +} + +void platform_AfterInitLate(struct sysinfo *cb, AMD_LATE_PARAMS *Late) +{ +} + + + +void platform_BeforeInitResume(struct sysinfo *cb, AMD_RESUME_PARAMS *Resume) +{ +} + +void platform_AfterInitResume(struct sysinfo *cb, AMD_RESUME_PARAMS *Resume) +{ +} + +void platform_BeforeS3LateRestore(struct sysinfo *cb, AMD_S3LATE_PARAMS *S3Late) +{ +} + +void platform_AfterS3LateRestore(struct sysinfo *cb, AMD_S3LATE_PARAMS *S3Late) +{ + amd_initcpuio(); +} + +void platform_AfterS3Save(struct sysinfo *cb, AMD_S3SAVE_PARAMS *S3Save) +{ +} From 24ab1c5db6a48f27d1541f8f356127a14111358e Mon Sep 17 00:00:00 2001 From: Subrata Banik Date: Mon, 25 Nov 2019 11:57:28 +0530 Subject: [PATCH 0380/1242] soc/intel/{apl,cnl,dnv,skl}: Skip ucode loading by FSP-T It is a requirement for Firmware to have Firmware Interface Table (FIT), which contains pointers to each microcode update. The microcode update is loaded for all logical processors before reset vector. FSPT_UPD.MicrocodeRegionBase and FSPT_UPD.MicrocodeRegionLength are input parameters to TempRamInit API. If these values are 0, FSP will not attempt to update microcode. Since Gen-4 all IA-SoC has FIT loading ucode even before cpu reset in place hence skipping FSP-T loading ucode after CPU reset options. Also removed unused kconfig CONFIG_CPU_MICROCODE_CBFS_LOC and CONFIG_CPU_MICROCODE_CBFS_LEN Change-Id: I3a406fa0e2e62e3363c2960e173dc5f5f5ca0455 Signed-off-by: Subrata Banik Reviewed-on: https://review.coreboot.org/c/coreboot/+/37187 Reviewed-by: Arthur Heymans Reviewed-by: David Guckian Tested-by: build bot (Jenkins) --- src/cpu/Makefile.inc | 5 ----- src/drivers/intel/fsp2_0/Kconfig | 15 --------------- src/soc/intel/apollolake/fspcar.c | 11 +++++++++++ src/soc/intel/cannonlake/bootblock/bootblock.c | 17 +++++++++++++---- src/soc/intel/denverton_ns/Kconfig | 8 -------- .../intel/denverton_ns/bootblock/bootblock.c | 17 +++++++++++++---- src/soc/intel/skylake/fspcar.c | 17 +++++++++++++---- 7 files changed, 50 insertions(+), 40 deletions(-) diff --git a/src/cpu/Makefile.inc b/src/cpu/Makefile.inc index b80c30d72b..4b5d67b908 100644 --- a/src/cpu/Makefile.inc +++ b/src/cpu/Makefile.inc @@ -59,9 +59,4 @@ $(obj)/cpu_microcode_blob.bin: $$(wildcard $$(cpu_microcode_bins)) cpu_microcode_blob.bin-file ?= $(obj)/cpu_microcode_blob.bin cpu_microcode_blob.bin-type := microcode - -ifneq ($(CONFIG_CPU_MICROCODE_CBFS_LOC),) -cpu_microcode_blob.bin-COREBOOT-position := $(CONFIG_CPU_MICROCODE_CBFS_LOC) -else cpu_microcode_blob.bin-align := 16 -endif diff --git a/src/drivers/intel/fsp2_0/Kconfig b/src/drivers/intel/fsp2_0/Kconfig index 1fd4b0cae1..77382d3674 100644 --- a/src/drivers/intel/fsp2_0/Kconfig +++ b/src/drivers/intel/fsp2_0/Kconfig @@ -37,21 +37,6 @@ config ADD_FSP_BINARIES Add the FSP-M and FSP-S binaries to CBFS. Currently coreboot does not use the FSP-T binary and it is not added. -config CPU_MICROCODE_CBFS_LEN - hex "Microcode update region length in bytes" - depends on FSP_CAR - default 0x0 - help - The length in bytes of the microcode update region. - -config CPU_MICROCODE_CBFS_LOC - hex "Microcode update base address in CBFS" - depends on FSP_CAR - default 0x0 - help - The location (base address) in CBFS that contains the - microcode update binary. - config FSP_T_CBFS string "Name of FSP-T in CBFS" depends on FSP_CAR diff --git a/src/soc/intel/apollolake/fspcar.c b/src/soc/intel/apollolake/fspcar.c index 8b1089f397..a284116bac 100644 --- a/src/soc/intel/apollolake/fspcar.c +++ b/src/soc/intel/apollolake/fspcar.c @@ -25,6 +25,17 @@ const FSPT_UPD temp_ram_init_params = { .FsptCommonUpd = { .Revision = 0, .Reserved = {0}, + /* + * It is a requirement for firmware to have Firmware Interface Table + * (FIT), which contains pointers to each microcode update. + * The microcode update is loaded for all logical processors before + * cpu reset vector. + * + * All SoC since Gen-4 has above mechanism in place to load microcode + * even before hitting CPU reset vector. Hence skipping FSP-T loading + * microcode after CPU reset by passing '0' value to + * FSPT_UPD.MicrocodeRegionBase and FSPT_UPD.MicrocodeRegionLength. + */ .MicrocodeRegionBase = 0, .MicrocodeRegionLength = 0, .CodeRegionBase = diff --git a/src/soc/intel/cannonlake/bootblock/bootblock.c b/src/soc/intel/cannonlake/bootblock/bootblock.c index 653ba30563..9f8539766c 100644 --- a/src/soc/intel/cannonlake/bootblock/bootblock.c +++ b/src/soc/intel/cannonlake/bootblock/bootblock.c @@ -30,10 +30,19 @@ const FSPT_UPD temp_ram_init_params = { .Reserved = {0}, }, .FsptCoreUpd = { - .MicrocodeRegionBase = - (uint32_t)CONFIG_CPU_MICROCODE_CBFS_LOC, - .MicrocodeRegionSize = - (uint32_t)CONFIG_CPU_MICROCODE_CBFS_LEN, + /* + * It is a requirement for firmware to have Firmware Interface Table + * (FIT), which contains pointers to each microcode update. + * The microcode update is loaded for all logical processors before + * cpu reset vector. + * + * All SoC since Gen-4 has above mechanism in place to load microcode + * even before hitting CPU reset vector. Hence skipping FSP-T loading + * microcode after CPU reset by passing '0' value to + * FSPT_UPD.MicrocodeRegionBase and FSPT_UPD.MicrocodeRegionLength. + */ + .MicrocodeRegionBase = 0, + .MicrocodeRegionLength = 0, .CodeRegionBase = (uint32_t)(0x100000000ULL - CONFIG_ROM_SIZE), .CodeRegionSize = (uint32_t)CONFIG_ROM_SIZE, diff --git a/src/soc/intel/denverton_ns/Kconfig b/src/soc/intel/denverton_ns/Kconfig index 0ce0d5bdd1..713aae60df 100644 --- a/src/soc/intel/denverton_ns/Kconfig +++ b/src/soc/intel/denverton_ns/Kconfig @@ -108,14 +108,6 @@ config DCACHE_BSP_STACK_SIZE hex default 0x10000 -config CPU_MICROCODE_CBFS_LOC - hex - default 0xfff20040 - -config CPU_MICROCODE_CBFS_LEN - hex - default 0x0ff80 - config CPU_BCLK_MHZ int default 100 diff --git a/src/soc/intel/denverton_ns/bootblock/bootblock.c b/src/soc/intel/denverton_ns/bootblock/bootblock.c index f75de1f2d0..47c76b5acd 100644 --- a/src/soc/intel/denverton_ns/bootblock/bootblock.c +++ b/src/soc/intel/denverton_ns/bootblock/bootblock.c @@ -31,10 +31,19 @@ const FSPT_UPD temp_ram_init_params = { .Reserved = {0}, }, .FsptCoreUpd = { - .MicrocodeRegionBase = - (UINT32)CONFIG_CPU_MICROCODE_CBFS_LOC, - .MicrocodeRegionLength = - (UINT32)CONFIG_CPU_MICROCODE_CBFS_LEN, + /* + * It is a requirement for firmware to have Firmware Interface Table + * (FIT), which contains pointers to each microcode update. + * The microcode update is loaded for all logical processors before + * cpu reset vector. + * + * All SoC since Gen-4 has above mechanism in place to load microcode + * even before hitting CPU reset vector. Hence skipping FSP-T loading + * microcode after CPU reset by passing '0' value to + * FSPT_UPD.MicrocodeRegionBase and FSPT_UPD.MicrocodeRegionLength. + */ + .MicrocodeRegionBase = 0, + .MicrocodeRegionLength = 0, .CodeRegionBase = (UINT32)(0x100000000ULL - CONFIG_ROM_SIZE), .CodeRegionLength = (UINT32)CONFIG_ROM_SIZE, diff --git a/src/soc/intel/skylake/fspcar.c b/src/soc/intel/skylake/fspcar.c index a4c3726492..0d27f57698 100644 --- a/src/soc/intel/skylake/fspcar.c +++ b/src/soc/intel/skylake/fspcar.c @@ -23,10 +23,19 @@ const FSPT_UPD temp_ram_init_params = { .Reserved = {0}, }, .FsptCoreUpd = { - .MicrocodeRegionBase = - (uint32_t)CONFIG_CPU_MICROCODE_CBFS_LOC, - .MicrocodeRegionSize = - (uint32_t)CONFIG_CPU_MICROCODE_CBFS_LEN, + /* + * It is a requirement for firmware to have Firmware Interface Table + * (FIT), which contains pointers to each microcode update. + * The microcode update is loaded for all logical processors before + * cpu reset vector. + * + * All SoC since Gen-4 has above mechanism in place to load microcode + * even before hitting CPU reset vector. Hence skipping FSP-T loading + * microcode after CPU reset by passing '0' value to + * FSPT_UPD.MicrocodeRegionBase and FSPT_UPD.MicrocodeRegionLength. + */ + .MicrocodeRegionBase = 0, + .MicrocodeRegionLength = 0, .CodeRegionBase = (uint32_t)(0x100000000ULL - CONFIG_ROM_SIZE), .CodeRegionSize = (uint32_t)CONFIG_ROM_SIZE, From a4f5954159531cfbe22a0b54acab331231440915 Mon Sep 17 00:00:00 2001 From: Patrick Georgi Date: Tue, 19 Nov 2019 17:12:42 +0100 Subject: [PATCH 0381/1242] util/release: Add amd_blobs to blob list Change-Id: I4417c733b3915ad74d81d2e1e0904da06eea300e Signed-off-by: Patrick Georgi Reviewed-on: https://review.coreboot.org/c/coreboot/+/36956 Reviewed-by: Stefan Reinauer Tested-by: build bot (Jenkins) --- util/release/build-release | 1 + 1 file changed, 1 insertion(+) diff --git a/util/release/build-release b/util/release/build-release index 0d90d162e3..e0f64ffa9e 100755 --- a/util/release/build-release +++ b/util/release/build-release @@ -70,6 +70,7 @@ cd .. exclude_paths="3rdparty/blobs " exclude_paths+="3rdparty/fsp " exclude_paths+="3rdparty/intel-microcode " +exclude_paths+="3rdparty/amd_blobs " for i in ${exclude_paths}; do blobs_paths+="coreboot-${VERSION_NAME}/${i} " exclude_opts+="--exclude=coreboot-${VERSION_NAME}/${i} " From 91709c91dfaf7d21581903c4c445ea85568506dc Mon Sep 17 00:00:00 2001 From: Arthur Heymans Date: Mon, 25 Nov 2019 23:23:14 +0100 Subject: [PATCH 0382/1242] .gitignore: Add pmh7tool binary Change-Id: Ide09ac2f61cffadb86f8a52b99a8ed9536a86a50 Signed-off-by: Arthur Heymans Reviewed-on: https://review.coreboot.org/c/coreboot/+/37216 Tested-by: build bot (Jenkins) Reviewed-by: Angel Pons --- .gitignore | 1 + 1 file changed, 1 insertion(+) diff --git a/.gitignore b/.gitignore index 84b3af10e2..0cc6ae2d3a 100644 --- a/.gitignore +++ b/.gitignore @@ -114,6 +114,7 @@ util/msrtool/msrtool util/nvramtool/.dependencies util/nvramtool/nvramtool util/optionlist/Options.wiki +util/pmh7tool/pmh7tool util/romcc/build util/runfw/googlesnow util/superiotool/superiotool From 6a23352515defc92fca208bdcf0d345d4542d6ce Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ky=C3=B6sti=20M=C3=A4lkki?= Date: Tue, 26 Nov 2019 11:11:00 +0200 Subject: [PATCH 0383/1242] amdfam10: Clean leftover prototypes MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Change-Id: Ic3278cb1148c34284aba59f6f588713b683ca90b Signed-off-by: Kyösti Mälkki Reviewed-on: https://review.coreboot.org/c/coreboot/+/37235 Tested-by: build bot (Jenkins) Reviewed-by: Arthur Heymans Reviewed-by: Michał Żygowski --- src/include/cpu/amd/car.h | 4 ---- 1 file changed, 4 deletions(-) diff --git a/src/include/cpu/amd/car.h b/src/include/cpu/amd/car.h index 359fa6bb8b..e4dd14289e 100644 --- a/src/include/cpu/amd/car.h +++ b/src/include/cpu/amd/car.h @@ -4,10 +4,6 @@ #include void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx); -asmlinkage void *post_cache_as_ram(void); -asmlinkage void cache_as_ram_new_stack(void); - -void disable_cache_as_ram(void); void asmlinkage early_all_cores(void); From f77f2c79c2bb898c123ffe89a0bd1acb5362afc5 Mon Sep 17 00:00:00 2001 From: Krystian Hebel Date: Fri, 19 Apr 2019 17:59:38 +0200 Subject: [PATCH 0384/1242] pcengines/apu2: Switch away from BINARYPI_LEGACY_WRAPPER MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Adopting the mainboard code to use hooks from state_machine.h. No post codes are changed, except for those which were explicitly sent in mainboard/romstage.c. Boot time is reduced by more than 7%, from 5.029s to 4.657s (coreboot timestamps, measured for loglevel 7). POSTCAR_STAGE is required since coreboot 4.11 release. TEST=boot PC Engines apu2 and launch Debian Linux with 4.14.50 kernel Change-Id: Iff3dbe68ac17eb2947ff40b9769c6650255656cf Signed-off-by: Krystian Hebel Signed-off-by: Michał Żygowski Reviewed-on: https://review.coreboot.org/c/coreboot/+/32363 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki Reviewed-by: Arthur Heymans --- src/mainboard/pcengines/apu2/BiosCallOuts.c | 111 +++++++++----------- src/mainboard/pcengines/apu2/Kconfig | 1 - src/mainboard/pcengines/apu2/OemCustomize.c | 22 +--- src/mainboard/pcengines/apu2/romstage.c | 89 ++++------------ 4 files changed, 74 insertions(+), 149 deletions(-) diff --git a/src/mainboard/pcengines/apu2/BiosCallOuts.c b/src/mainboard/pcengines/apu2/BiosCallOuts.c index dff346e16a..264dd77835 100644 --- a/src/mainboard/pcengines/apu2/BiosCallOuts.c +++ b/src/mainboard/pcengines/apu2/BiosCallOuts.c @@ -17,6 +17,7 @@ #include #include #include +#include #include #include @@ -24,7 +25,6 @@ #include "imc.h" #include "hudson.h" -static AGESA_STATUS Fch_Oem_config(UINT32 Func, UINTN FchData, VOID *ConfigPtr); static AGESA_STATUS board_ReadSpd_from_cbfs(UINT32 Func, UINTN Data, VOID *ConfigPtr); const BIOS_CALLOUT_STRUCT BiosCallouts[] = @@ -35,8 +35,7 @@ const BIOS_CALLOUT_STRUCT BiosCallouts[] = {AGESA_RUNFUNC_ONAP, agesa_RunFuncOnAp }, {AGESA_GET_IDS_INIT_DATA, agesa_EmptyIdsInitData }, {AGESA_HOOKBEFORE_DQS_TRAINING, agesa_NoopSuccess }, - {AGESA_HOOKBEFORE_EXIT_SELF_REF, agesa_NoopSuccess }, - {AGESA_FCH_OEM_CALLOUT, Fch_Oem_config } + {AGESA_HOOKBEFORE_EXIT_SELF_REF, agesa_NoopSuccess } }; const int BiosCalloutsLen = ARRAY_SIZE(BiosCallouts); @@ -57,75 +56,67 @@ static void oem_fan_control(FCH_DATA_BLOCK *FchParams) FchParams->Hwm.HwmFchtsiAutoPoll = FALSE; /* 1 enable, 0 disable TSI Auto Polling */ } -/** - * Fch Oem setting callback - * - * Configure platform specific Hudson device, - * such Azalia, SATA, IMC etc. - */ -static AGESA_STATUS Fch_Oem_config(UINT32 Func, UINTN FchData, VOID *ConfigPtr) +void board_FCH_InitReset(struct sysinfo *cb_NA, FCH_RESET_DATA_BLOCK *FchParams) { - AMD_CONFIG_PARAMS *StdHeader = (AMD_CONFIG_PARAMS *)ConfigPtr; - if (StdHeader->Func == AMD_INIT_RESET) { - FCH_RESET_DATA_BLOCK *FchParams = (FCH_RESET_DATA_BLOCK *) FchData; - printk(BIOS_DEBUG, "Fch OEM config in INIT RESET "); - //FchParams_reset->EcChannel0 = TRUE; /* logical devicd 3 */ - FchParams->LegacyFree = CONFIG(HUDSON_LEGACY_FREE); - FchParams->FchReset.SataEnable = hudson_sata_enable(); - FchParams->FchReset.IdeEnable = hudson_ide_enable(); - FchParams->FchReset.Xhci0Enable = CONFIG(HUDSON_XHCI_ENABLE); - FchParams->FchReset.Xhci1Enable = FALSE; - } else if (StdHeader->Func == AMD_INIT_ENV) { - FCH_DATA_BLOCK *FchParams = (FCH_DATA_BLOCK *)FchData; - printk(BIOS_DEBUG, "Fch OEM config in INIT ENV "); + printk(BIOS_DEBUG, "Fch OEM config in INIT RESET "); + //FchParams_reset->EcChannel0 = TRUE; /* logical devicd 3 */ + FchParams->LegacyFree = CONFIG(HUDSON_LEGACY_FREE); + FchParams->FchReset.SataEnable = hudson_sata_enable(); + FchParams->FchReset.IdeEnable = hudson_ide_enable(); + FchParams->FchReset.Xhci0Enable = CONFIG(HUDSON_XHCI_ENABLE); + FchParams->FchReset.Xhci1Enable = FALSE; + printk(BIOS_DEBUG, "Done\n"); +} + +void board_FCH_InitEnv(struct sysinfo *cb_NA, FCH_DATA_BLOCK *FchParams) +{ + printk(BIOS_DEBUG, "Fch OEM config in INIT ENV "); - FchParams->Azalia.AzaliaEnable = AzDisable; + FchParams->Azalia.AzaliaEnable = AzDisable; - /* Fan Control */ - oem_fan_control(FchParams); + /* Fan Control */ + oem_fan_control(FchParams); - /* XHCI configuration */ - FchParams->Usb.Xhci0Enable = CONFIG(HUDSON_XHCI_ENABLE); - FchParams->Usb.Xhci1Enable = FALSE; + /* XHCI configuration */ + FchParams->Usb.Xhci0Enable = CONFIG(HUDSON_XHCI_ENABLE); + FchParams->Usb.Xhci1Enable = FALSE; - /* EHCI configuration */ - FchParams->Usb.Ehci3Enable = !CONFIG(HUDSON_XHCI_ENABLE); + /* EHCI configuration */ + FchParams->Usb.Ehci3Enable = !CONFIG(HUDSON_XHCI_ENABLE); - if (CONFIG(BOARD_PCENGINES_APU2)) { - // Disable EHCI 0 (port 0 to 3) - FchParams->Usb.Ehci1Enable = FALSE; - } else { - // Enable EHCI 0 (port 0 to 3) - FchParams->Usb.Ehci1Enable = TRUE; - } + if (CONFIG(BOARD_PCENGINES_APU2)) { + // Disable EHCI 0 (port 0 to 3) + FchParams->Usb.Ehci1Enable = FALSE; + } else { + // Enable EHCI 0 (port 0 to 3) + FchParams->Usb.Ehci1Enable = TRUE; + } - // Enable EHCI 1 (port 4 to 7) - // port 4 and 5 to EHCI header port 6 and 7 to PCIe slot. - FchParams->Usb.Ehci2Enable = TRUE; + // Enable EHCI 1 (port 4 to 7) + // port 4 and 5 to EHCI header port 6 and 7 to PCIe slot. + FchParams->Usb.Ehci2Enable = TRUE; - /* sata configuration */ - FchParams->Sata.SataDevSlpPort0 = 0; // Disable DEVSLP0 and 1 to make sure GPIO55 and 59 are not used by DEVSLP - FchParams->Sata.SataDevSlpPort1 = 0; + /* sata configuration */ + // Disable DEVSLP0 and 1 to make sure GPIO55 and 59 are not used by DEVSLP + FchParams->Sata.SataDevSlpPort0 = 0; + FchParams->Sata.SataDevSlpPort1 = 0; - FchParams->Sata.SataClass = CONFIG_HUDSON_SATA_MODE; - switch ((SATA_CLASS)CONFIG_HUDSON_SATA_MODE) { - case SataRaid: - case SataAhci: - case SataAhci7804: - case SataLegacyIde: - FchParams->Sata.SataIdeMode = FALSE; - break; - case SataIde2Ahci: - case SataIde2Ahci7804: - default: /* SataNativeIde */ - FchParams->Sata.SataIdeMode = TRUE; - break; - } + FchParams->Sata.SataClass = CONFIG_HUDSON_SATA_MODE; + switch ((SATA_CLASS)CONFIG_HUDSON_SATA_MODE) { + case SataRaid: + case SataAhci: + case SataAhci7804: + case SataLegacyIde: + FchParams->Sata.SataIdeMode = FALSE; + break; + case SataIde2Ahci: + case SataIde2Ahci7804: + default: /* SataNativeIde */ + FchParams->Sata.SataIdeMode = TRUE; + break; } printk(BIOS_DEBUG, "Done\n"); - - return AGESA_SUCCESS; } static AGESA_STATUS board_ReadSpd_from_cbfs(UINT32 Func, UINTN Data, VOID *ConfigPtr) diff --git a/src/mainboard/pcengines/apu2/Kconfig b/src/mainboard/pcengines/apu2/Kconfig index 0437c84d28..372f67df6a 100644 --- a/src/mainboard/pcengines/apu2/Kconfig +++ b/src/mainboard/pcengines/apu2/Kconfig @@ -20,7 +20,6 @@ if BOARD_PCENGINES_APU2 || BOARD_PCENGINES_APU3 || BOARD_PCENGINES_APU4 || \ config BOARD_SPECIFIC_OPTIONS def_bool y - select BINARYPI_LEGACY_WRAPPER select CPU_AMD_PI_00730F01 select NORTHBRIDGE_AMD_PI_00730F01 select SOUTHBRIDGE_AMD_PI_AVALON diff --git a/src/mainboard/pcengines/apu2/OemCustomize.c b/src/mainboard/pcengines/apu2/OemCustomize.c index 700f4c7ca6..7ef7e00fc7 100644 --- a/src/mainboard/pcengines/apu2/OemCustomize.c +++ b/src/mainboard/pcengines/apu2/OemCustomize.c @@ -14,7 +14,7 @@ */ #include -#include +#include static const PCIe_PORT_DESCRIPTOR PortList[] = { @@ -76,25 +76,7 @@ static const PCIe_COMPLEX_DESCRIPTOR PcieComplex = { .DdiLinkList = NULL, }; -/*---------------------------------------------------------------------------------------*/ -/** - * OemCustomizeInitEarly - * - * Description: - * This stub function will call the host environment through the binary block - * interface (call-out port) to provide a user hook opportunity - * - * Parameters: - * @param[in] *InitEarly - * - * @retval VOID - * - **/ -/*---------------------------------------------------------------------------------------*/ -VOID -OemCustomizeInitEarly ( - IN OUT AMD_EARLY_PARAMS *InitEarly - ) +void board_BeforeInitEarly(struct sysinfo *cb, AMD_EARLY_PARAMS *InitEarly) { InitEarly->GnbConfig.PcieComplexList = &PcieComplex; InitEarly->PlatformConfig.CStateMode = CStateModeC6; diff --git a/src/mainboard/pcengines/apu2/romstage.c b/src/mainboard/pcengines/apu2/romstage.c index bd3c421a2f..4df1e47d99 100644 --- a/src/mainboard/pcengines/apu2/romstage.c +++ b/src/mainboard/pcengines/apu2/romstage.c @@ -21,11 +21,8 @@ #include #include #include -#include #include #include -#include -#include #include #include #include @@ -40,9 +37,11 @@ static void early_lpc_init(void); -void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) +void board_BeforeAgesa(struct sysinfo *cb) { u32 val; + pci_devfn_t dev; + u32 data; /* * In Hudson RRG, PMIOxD2[5:4] is "Drive strength control for @@ -52,85 +51,39 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) * the SoC BKDGs. Without this setting, there is no serial * output. */ - outb(0xD2, 0xcd6); + outb(0xd2, 0xcd6); outb(0x00, 0xcd7); hudson_lpc_port80(); - if (!cpu_init_detectedx && boot_cpu()) { - pci_devfn_t dev; - u32 data; + post_code(0x30); + early_lpc_init(); - timestamp_init(timestamp_get()); - timestamp_add_now(TS_START_ROMSTAGE); + hudson_clk_output_48Mhz(); + post_code(0x31); - post_code(0x30); - early_lpc_init(); + dev = PCI_DEV(0, 0x14, 3); + data = pci_read_config32(dev, LPC_IO_OR_MEM_DECODE_ENABLE); + /* enable 0x2e/0x4e IO decoding before configuring SuperIO */ + pci_write_config32(dev, LPC_IO_OR_MEM_DECODE_ENABLE, data | 3); - hudson_clk_output_48Mhz(); - post_code(0x31); + /* COM2 on apu5 is reserved so only COM1 should be supported */ + if ((CONFIG_UART_FOR_CONSOLE == 1) && + !CONFIG(BOARD_PCENGINES_APU5)) + nuvoton_enable_serial(SERIAL2_DEV, CONFIG_TTYS0_BASE); + else if (CONFIG_UART_FOR_CONSOLE == 0) + nuvoton_enable_serial(SERIAL1_DEV, CONFIG_TTYS0_BASE); - dev = PCI_DEV(0, 0x14, 3); - data = pci_read_config32(dev, LPC_IO_OR_MEM_DECODE_ENABLE); - /* enable 0x2e/0x4e IO decoding before configuring SuperIO */ - pci_write_config32(dev, LPC_IO_OR_MEM_DECODE_ENABLE, data | 3); - - /* COM2 on apu5 is reserved so only COM1 should be supported */ - if ((CONFIG_UART_FOR_CONSOLE == 1) && - !CONFIG(BOARD_PCENGINES_APU5)) - nuvoton_enable_serial(SERIAL2_DEV, CONFIG_TTYS0_BASE); - else if (CONFIG_UART_FOR_CONSOLE == 0) - nuvoton_enable_serial(SERIAL1_DEV, CONFIG_TTYS0_BASE); - - console_init(); - } - - /* Halt if there was a built in self test failure */ - post_code(0x34); - report_bist_failure(bist); - - /* Load MPB */ - val = cpuid_eax(1); - printk(BIOS_DEBUG, "BSP Family_Model: %08x\n", val); - printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx); - - post_code(0x37); - AGESAWRAPPER(amdinitreset); - - post_code(0x38); - printk(BIOS_DEBUG, "Got past avalon_early_setup\n"); - - post_code(0x39); - AGESAWRAPPER(amdinitearly); /* Disable SVI2 controller to wait for command completion */ val = pci_read_config32(PCI_DEV(0, 0x18, 5), 0x12C); - if (val & (1 << 30)) { - printk(BIOS_DEBUG, "SVI2 Wait completion disabled\n"); - } else { - printk(BIOS_DEBUG, "Disabling SVI2 Wait completion\n"); + if (!(val & (1 << 30))) { val |= (1 << 30); pci_write_config32(PCI_DEV(0, 0x18, 5), 0x12C, val); } - timestamp_add_now(TS_BEFORE_INITRAM); - - post_code(0x40); - AGESAWRAPPER(amdinitpost); - - /* FIXME: Detect if TSC frequency changed during raminit? */ - timestamp_rescale_table(1, 4); - - timestamp_add_now(TS_AFTER_INITRAM); -} - -void agesa_postcar(struct sysinfo *cb) -{ - //PspMboxBiosCmdDramInfo(); - post_code(0x41); - AGESAWRAPPER(amdinitenv); - - outb(0xEA, 0xCD6); + /* Disable PCI-PCI bridge and release GPIO32/33 for other uses. */ + outb(0xea, 0xcd6); outb(0x1, 0xcd7); } From a0a50775c2a08495c0e1d394504d9d2bfd84125c Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ky=C3=B6sti=20M=C3=A4lkki?= Date: Sat, 23 Nov 2019 20:22:09 +0200 Subject: [PATCH 0385/1242] binaryPI: Disable boards from build MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit As per the 4.11 release requirement, CAR_GLOBAL_MIGRATION=n is a mandatory feature, which most binaryPI boards lack as they use BINARYPI_LEGACY_WRAPPER. Disable all binaryPI platforms, except pcengines/apu2, from the build for the time being. If a platform does not reach POSTCAR_STAGE=y and C_ENVIRONMENT_BOOTBLOCK=y within a reasonable timeframe both the mainboard and the respective unused platform support code will get removed. Change-Id: Id81ab0f168034187ecf62203b5a33ac6ba49a35d Signed-off-by: Kyösti Mälkki Reviewed-on: https://review.coreboot.org/c/coreboot/+/37170 Tested-by: build bot (Jenkins) Reviewed-by: Richard Spiegel Reviewed-by: Arthur Heymans Reviewed-by: Michał Żygowski --- src/mainboard/amd/bettong/Kconfig | 3 +++ src/mainboard/amd/bettong/Kconfig.name | 5 +++-- src/mainboard/amd/db-ft3b-lc/Kconfig | 3 +++ src/mainboard/amd/db-ft3b-lc/Kconfig.name | 5 +++-- src/mainboard/amd/lamar/Kconfig | 3 +++ src/mainboard/amd/lamar/Kconfig.name | 5 +++-- src/mainboard/amd/olivehillplus/Kconfig | 3 +++ src/mainboard/amd/olivehillplus/Kconfig.name | 5 +++-- src/mainboard/bap/ode_e21XX/Kconfig | 3 +++ src/mainboard/bap/ode_e21XX/Kconfig.name | 5 +++-- 10 files changed, 30 insertions(+), 10 deletions(-) diff --git a/src/mainboard/amd/bettong/Kconfig b/src/mainboard/amd/bettong/Kconfig index 5f26e8777e..bcfceb19b3 100644 --- a/src/mainboard/amd/bettong/Kconfig +++ b/src/mainboard/amd/bettong/Kconfig @@ -13,6 +13,9 @@ # GNU General Public License for more details. # +config BOARD_AMD_BETTONG + def_bool n + if BOARD_AMD_BETTONG config BOARD_SPECIFIC_OPTIONS diff --git a/src/mainboard/amd/bettong/Kconfig.name b/src/mainboard/amd/bettong/Kconfig.name index 09201b5f80..4bd13291cd 100644 --- a/src/mainboard/amd/bettong/Kconfig.name +++ b/src/mainboard/amd/bettong/Kconfig.name @@ -1,2 +1,3 @@ -config BOARD_AMD_BETTONG - bool "Bettong" +# Disabled +#config BOARD_AMD_BETTONG +# bool "Bettong" diff --git a/src/mainboard/amd/db-ft3b-lc/Kconfig b/src/mainboard/amd/db-ft3b-lc/Kconfig index 256b5553bf..eaee3e7cd3 100644 --- a/src/mainboard/amd/db-ft3b-lc/Kconfig +++ b/src/mainboard/amd/db-ft3b-lc/Kconfig @@ -14,6 +14,9 @@ # GNU General Public License for more details. # +config BOARD_AMD_DB_FT3B_LC + def_bool n + if BOARD_AMD_DB_FT3B_LC config BOARD_SPECIFIC_OPTIONS diff --git a/src/mainboard/amd/db-ft3b-lc/Kconfig.name b/src/mainboard/amd/db-ft3b-lc/Kconfig.name index 7caf95ddfe..3197a70694 100644 --- a/src/mainboard/amd/db-ft3b-lc/Kconfig.name +++ b/src/mainboard/amd/db-ft3b-lc/Kconfig.name @@ -1,2 +1,3 @@ -config BOARD_AMD_DB_FT3B_LC - bool "DB-FT3b-LC" +# Disabled +#config BOARD_AMD_DB_FT3B_LC +# bool "DB-FT3b-LC" diff --git a/src/mainboard/amd/lamar/Kconfig b/src/mainboard/amd/lamar/Kconfig index 025e5ffa80..5527d59a1b 100644 --- a/src/mainboard/amd/lamar/Kconfig +++ b/src/mainboard/amd/lamar/Kconfig @@ -13,6 +13,9 @@ # GNU General Public License for more details. # +config BOARD_AMD_LAMAR + def_bool n + if BOARD_AMD_LAMAR config BOARD_SPECIFIC_OPTIONS diff --git a/src/mainboard/amd/lamar/Kconfig.name b/src/mainboard/amd/lamar/Kconfig.name index 1831b9a133..75eec04ae3 100644 --- a/src/mainboard/amd/lamar/Kconfig.name +++ b/src/mainboard/amd/lamar/Kconfig.name @@ -1,2 +1,3 @@ -config BOARD_AMD_LAMAR - bool "Lamar" +# Disabled +#config BOARD_AMD_LAMAR +# bool "Lamar" diff --git a/src/mainboard/amd/olivehillplus/Kconfig b/src/mainboard/amd/olivehillplus/Kconfig index 96d934702e..61ba33d3b9 100644 --- a/src/mainboard/amd/olivehillplus/Kconfig +++ b/src/mainboard/amd/olivehillplus/Kconfig @@ -13,6 +13,9 @@ # GNU General Public License for more details. # +config BOARD_AMD_OLIVEHILLPLUS + def_bool n + if BOARD_AMD_OLIVEHILLPLUS config BOARD_SPECIFIC_OPTIONS diff --git a/src/mainboard/amd/olivehillplus/Kconfig.name b/src/mainboard/amd/olivehillplus/Kconfig.name index 85a3e86ca2..1ce4a204b9 100644 --- a/src/mainboard/amd/olivehillplus/Kconfig.name +++ b/src/mainboard/amd/olivehillplus/Kconfig.name @@ -1,2 +1,3 @@ -config BOARD_AMD_OLIVEHILLPLUS - bool "Olive Hill Plus" +# Disabled +#config BOARD_AMD_OLIVEHILLPLUS +# bool "Olive Hill Plus" diff --git a/src/mainboard/bap/ode_e21XX/Kconfig b/src/mainboard/bap/ode_e21XX/Kconfig index bf812f26ea..5b0d2fb2f3 100644 --- a/src/mainboard/bap/ode_e21XX/Kconfig +++ b/src/mainboard/bap/ode_e21XX/Kconfig @@ -13,6 +13,9 @@ # GNU General Public License for more details. # +config BOARD_ODE_E21XX + def_bool n + if BOARD_ODE_E21XX config BOARD_SPECIFIC_OPTIONS diff --git a/src/mainboard/bap/ode_e21XX/Kconfig.name b/src/mainboard/bap/ode_e21XX/Kconfig.name index 5ef8804717..64665daea7 100644 --- a/src/mainboard/bap/ode_e21XX/Kconfig.name +++ b/src/mainboard/bap/ode_e21XX/Kconfig.name @@ -1,2 +1,3 @@ -config BOARD_ODE_E21XX - bool "ODE_e21xx" +# Disabled +#config BOARD_ODE_E21XX +# bool "ODE_e21xx" From b81731d9dbe067097388212c138e2bed88ce75d4 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ky=C3=B6sti=20M=C3=A4lkki?= Date: Mon, 25 Nov 2019 12:25:54 +0200 Subject: [PATCH 0386/1242] binaryPI: Drop S3_DATA_POS and S3_DATA_SIZE MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Direct SPI flash manipulation is forbidden, need to go through respective FMAP and rdev APIs. Change-Id: I765a6084fb26398008f38c0403f808bae19fdae1 Signed-off-by: Kyösti Mälkki Reviewed-on: https://review.coreboot.org/c/coreboot/+/37192 Reviewed-by: Arthur Heymans Reviewed-by: Michał Żygowski Tested-by: build bot (Jenkins) --- src/cpu/amd/pi/Kconfig | 8 -------- 1 file changed, 8 deletions(-) diff --git a/src/cpu/amd/pi/Kconfig b/src/cpu/amd/pi/Kconfig index ee6fa4bb5c..d2824f2503 100644 --- a/src/cpu/amd/pi/Kconfig +++ b/src/cpu/amd/pi/Kconfig @@ -51,14 +51,6 @@ config DCACHE_RAM_SIZE hex default 0x10000 -config S3_DATA_POS - hex - default 0xFFFF0000 - -config S3_DATA_SIZE - int - default 32768 - endif # CPU_AMD_PI source "src/cpu/amd/pi/00630F01/Kconfig" From 46f04cbb49fbab5854d395edefea5b5f81df572e Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ky=C3=B6sti=20M=C3=A4lkki?= Date: Wed, 6 Sep 2017 15:42:23 +0300 Subject: [PATCH 0387/1242] binaryPI: Drop BINARYPI_LEGACY_WRAPPER support MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Drop all the sources that were guarded with this. Change-Id: I6c6fd19875cb57f0caf42a1a94f59efed83bfe0d Signed-off-by: Kyösti Mälkki Reviewed-on: https://review.coreboot.org/c/coreboot/+/19275 Tested-by: build bot (Jenkins) Reviewed-by: Michał Żygowski --- src/cpu/amd/pi/Kconfig | 4 - src/cpu/amd/pi/Makefile.inc | 6 - src/cpu/amd/pi/amd_late_init.c | 36 -- src/cpu/amd/pi/romstage.c | 55 -- src/drivers/amd/agesa/Makefile.inc | 8 - src/drivers/amd/agesa/def_callouts.c | 18 +- src/drivers/amd/agesa/eventlog.c | 15 +- src/drivers/amd/agesa/romstage.c | 3 - src/include/cpu/amd/car.h | 1 - src/mainboard/amd/bettong/BiosCallOuts.c | 1 - src/mainboard/amd/bettong/Kconfig | 2 +- src/mainboard/amd/bettong/OemCustomize.c | 1 - src/mainboard/amd/bettong/romstage.c | 2 - src/mainboard/amd/db-ft3b-lc/Kconfig | 2 +- src/mainboard/amd/db-ft3b-lc/OemCustomize.c | 1 - src/mainboard/amd/db-ft3b-lc/romstage.c | 2 - src/mainboard/amd/lamar/Kconfig | 2 +- src/mainboard/amd/lamar/OemCustomize.c | 1 - src/mainboard/amd/lamar/romstage.c | 2 - src/mainboard/amd/olivehillplus/Kconfig | 2 +- .../amd/olivehillplus/OemCustomize.c | 1 - src/mainboard/amd/olivehillplus/romstage.c | 2 - src/mainboard/bap/ode_e21XX/Kconfig | 2 +- src/mainboard/bap/ode_e21XX/OemCustomize.c | 1 - src/mainboard/bap/ode_e21XX/romstage.c | 2 - src/northbridge/amd/agesa/state_machine.h | 2 - src/northbridge/amd/pi/00630F01/northbridge.c | 14 - src/northbridge/amd/pi/00660F01/northbridge.c | 11 - src/northbridge/amd/pi/00730F01/Makefile.inc | 2 - src/northbridge/amd/pi/00730F01/northbridge.c | 11 - src/northbridge/amd/pi/Makefile.inc | 5 - src/northbridge/amd/pi/agesawrapper.c | 317 ----------- src/northbridge/amd/pi/agesawrapper.h | 61 --- src/northbridge/amd/pi/agesawrapper_call.h | 58 -- src/vendorcode/amd/Kconfig | 1 - .../amd/pi/00630F01/binaryPI/AGESA.c | 512 ------------------ .../amd/pi/00660F01/binaryPI/AGESA.c | 402 -------------- .../amd/pi/00730F01/binaryPI/AGESA.c | 511 ----------------- src/vendorcode/amd/pi/Makefile.inc | 4 - 39 files changed, 9 insertions(+), 2074 deletions(-) delete mode 100644 src/cpu/amd/pi/amd_late_init.c delete mode 100644 src/cpu/amd/pi/romstage.c delete mode 100644 src/northbridge/amd/pi/agesawrapper.c delete mode 100644 src/northbridge/amd/pi/agesawrapper.h delete mode 100644 src/northbridge/amd/pi/agesawrapper_call.h delete mode 100644 src/vendorcode/amd/pi/00630F01/binaryPI/AGESA.c delete mode 100644 src/vendorcode/amd/pi/00660F01/binaryPI/AGESA.c delete mode 100644 src/vendorcode/amd/pi/00730F01/binaryPI/AGESA.c diff --git a/src/cpu/amd/pi/Kconfig b/src/cpu/amd/pi/Kconfig index d2824f2503..d18f873332 100644 --- a/src/cpu/amd/pi/Kconfig +++ b/src/cpu/amd/pi/Kconfig @@ -26,15 +26,11 @@ config CPU_AMD_PI select UDELAY_LAPIC select LAPIC_MONOTONIC_TIMER select SPI_FLASH if HAVE_ACPI_RESUME - select CAR_GLOBAL_MIGRATION if BINARYPI_LEGACY_WRAPPER select SMM_ASEG select NO_FIXED_XIP_ROM_SIZE if CPU_AMD_PI -config BINARYPI_LEGACY_WRAPPER - def_bool n - config UDELAY_LAPIC_FIXED_FSB int default 200 diff --git a/src/cpu/amd/pi/Makefile.inc b/src/cpu/amd/pi/Makefile.inc index 0a9b0649a9..6b6447c877 100644 --- a/src/cpu/amd/pi/Makefile.inc +++ b/src/cpu/amd/pi/Makefile.inc @@ -14,9 +14,3 @@ subdirs-$(CONFIG_CPU_AMD_PI_00630F01) += 00630F01 subdirs-$(CONFIG_CPU_AMD_PI_00730F01) += 00730F01 subdirs-$(CONFIG_CPU_AMD_PI_00660F01) += 00660F01 - -ifeq ($(CONFIG_BINARYPI_LEGACY_WRAPPER), y) -cpu_incs-y += $(src)/drivers/amd/agesa/cache_as_ram.S -romstage-y += romstage.c -ramstage-y += amd_late_init.c -endif diff --git a/src/cpu/amd/pi/amd_late_init.c b/src/cpu/amd/pi/amd_late_init.c deleted file mode 100644 index 46144c6fbb..0000000000 --- a/src/cpu/amd/pi/amd_late_init.c +++ /dev/null @@ -1,36 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include -#include - -#include -#include - -static void agesawrapper_post_device(void *unused) -{ - if (acpi_is_wakeup_s3()) - return; - - AGESAWRAPPER(amdinitlate); - - if (!acpi_s3_resume_allowed()) - return; - - AGESAWRAPPER(amdS3Save); -} - -BOOT_STATE_INIT_ENTRY(BS_POST_DEVICE, BS_ON_EXIT, - agesawrapper_post_device, NULL); diff --git a/src/cpu/amd/pi/romstage.c b/src/cpu/amd/pi/romstage.c deleted file mode 100644 index cac5664697..0000000000 --- a/src/cpu/amd/pi/romstage.c +++ /dev/null @@ -1,55 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include - -void asmlinkage early_all_cores(void) -{ - amd_initmmio(); -} - -void *asmlinkage romstage_main(unsigned long bist) -{ - int s3resume = 0; - u8 initial_apic_id = cpuid_ebx(1) >> 24; - - /* Only BSP returns from here. */ - cache_as_ram_main(bist, initial_apic_id); - - cbmem_recovery(s3resume); - - romstage_handoff_init(s3resume); - - char *stack_top = cbmem_add(CBMEM_ID_ROMSTAGE_RAM_STACK, HIGH_ROMSTAGE_STACK_SIZE); - stack_top += HIGH_ROMSTAGE_STACK_SIZE; - - printk(BIOS_DEBUG, "Move CAR stack.\n"); - return (void *)stack_top; -} - -void asmlinkage romstage_after_car(void) -{ - printk(BIOS_DEBUG, "CAR disabled.\n"); - - agesa_postcar(NULL); - - run_ramstage(); -} diff --git a/src/drivers/amd/agesa/Makefile.inc b/src/drivers/amd/agesa/Makefile.inc index 4d5bd3e368..fb46d91991 100644 --- a/src/drivers/amd/agesa/Makefile.inc +++ b/src/drivers/amd/agesa/Makefile.inc @@ -13,8 +13,6 @@ ifeq ($(CONFIG_DRIVERS_AMD_PI),y) -ifneq ($(CONFIG_BINARYPI_LEGACY_WRAPPER),y) - romstage-y += romstage.c romstage-y += mtrr_fixme.c romstage-y += state_machine.c @@ -24,12 +22,6 @@ ramstage-y += state_machine.c cpu_incs-y += $(src)/drivers/amd/agesa/cache_as_ram.S postcar-y += cache_as_ram.S -else - -romstage-y += heapmanager.c - -endif - romstage-y += def_callouts.c romstage-y += eventlog.c diff --git a/src/drivers/amd/agesa/def_callouts.c b/src/drivers/amd/agesa/def_callouts.c index 2e75220e4c..4b78d633c9 100644 --- a/src/drivers/amd/agesa/def_callouts.c +++ b/src/drivers/amd/agesa/def_callouts.c @@ -35,7 +35,7 @@ AGESA_STATUS GetBiosCallout (UINT32 Func, UINTN Data, VOID *ConfigPtr) AGESA_STATUS status; UINTN i; - if (HAS_LEGACY_WRAPPER || ENV_RAMSTAGE) { + if (ENV_RAMSTAGE) { /* One HeapManager serves them all. */ status = HeapManagerCallout(Func, Data, ConfigPtr); if (status != AGESA_UNSUPPORTED) @@ -43,7 +43,7 @@ AGESA_STATUS GetBiosCallout (UINT32 Func, UINTN Data, VOID *ConfigPtr) } #if HAS_AGESA_FCH_OEM_CALLOUT - if (!HAS_LEGACY_WRAPPER && Func == AGESA_FCH_OEM_CALLOUT) { + if (Func == AGESA_FCH_OEM_CALLOUT) { agesa_fch_oem_config(Data, ConfigPtr); return AGESA_SUCCESS; } @@ -120,24 +120,12 @@ AGESA_STATUS agesa_RunFuncOnAp (UINT32 Func, UINTN Data, VOID *ConfigPtr) AP_EXE_PARAMS ApExeParams; memset(&ApExeParams, 0, sizeof(AP_EXE_PARAMS)); - - if (HAS_LEGACY_WRAPPER) { - ApExeParams.StdHeader.AltImageBasePtr = 0; - ApExeParams.StdHeader.CalloutPtr = &GetBiosCallout; - ApExeParams.StdHeader.Func = 0; - ApExeParams.StdHeader.ImageBasePtr = 0; - } else { - memcpy(&ApExeParams.StdHeader, StdHeader, sizeof(*StdHeader)); - } + memcpy(&ApExeParams.StdHeader, StdHeader, sizeof(*StdHeader)); ApExeParams.FunctionNumber = Func; ApExeParams.RelatedDataBlock = ConfigPtr; -#if HAS_LEGACY_WRAPPER - status = AmdLateRunApTask(&ApExeParams); -#else status = module_dispatch(AMD_LATE_RUN_AP_TASK, &ApExeParams.StdHeader); -#endif ASSERT(status == AGESA_SUCCESS); return status; diff --git a/src/drivers/amd/agesa/eventlog.c b/src/drivers/amd/agesa/eventlog.c index df2c73c26d..aa0ea9b930 100644 --- a/src/drivers/amd/agesa/eventlog.c +++ b/src/drivers/amd/agesa/eventlog.c @@ -180,11 +180,7 @@ static void amd_flush_eventlog(EVENT_PARAMS *Event) do { AGESA_STATUS status; -#if HAS_LEGACY_WRAPPER - status = AmdReadEventLog(Event); -#else status = module_dispatch(AMD_READ_EVENT_LOG, &Event->StdHeader); -#endif if (status != AGESA_SUCCESS) return; if (Event->EventClass == 0) @@ -203,16 +199,7 @@ void agesawrapper_trace(AGESA_STATUS ret, AMD_CONFIG_PARAMS *StdHeader, return; memset(&AmdEventParams, 0, sizeof(EVENT_PARAMS)); - - if (HAS_LEGACY_WRAPPER) { - AmdEventParams.StdHeader.AltImageBasePtr = 0; - AmdEventParams.StdHeader.CalloutPtr = &GetBiosCallout; - AmdEventParams.StdHeader.Func = 0; - AmdEventParams.StdHeader.ImageBasePtr = 0; - AmdEventParams.StdHeader.HeapStatus = StdHeader->HeapStatus; - } else { - memcpy(&AmdEventParams.StdHeader, StdHeader, sizeof(*StdHeader)); - } + memcpy(&AmdEventParams.StdHeader, StdHeader, sizeof(*StdHeader)); amd_flush_eventlog(&AmdEventParams); } diff --git a/src/drivers/amd/agesa/romstage.c b/src/drivers/amd/agesa/romstage.c index 76a6ea4500..72aac3eedd 100644 --- a/src/drivers/amd/agesa/romstage.c +++ b/src/drivers/amd/agesa/romstage.c @@ -30,9 +30,6 @@ #if !CONFIG(POSTCAR_STAGE) #error "Only POSTCAR_STAGE is supported." #endif -#if HAS_LEGACY_WRAPPER -#error "LEGACY_WRAPPER code not supported" -#endif void asmlinkage early_all_cores(void) { diff --git a/src/include/cpu/amd/car.h b/src/include/cpu/amd/car.h index e4dd14289e..59f5bb91aa 100644 --- a/src/include/cpu/amd/car.h +++ b/src/include/cpu/amd/car.h @@ -8,6 +8,5 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx); void asmlinkage early_all_cores(void); void *asmlinkage romstage_main(unsigned long bist); -void asmlinkage romstage_after_car(void); #endif diff --git a/src/mainboard/amd/bettong/BiosCallOuts.c b/src/mainboard/amd/bettong/BiosCallOuts.c index e9836904d3..a6f424eff1 100644 --- a/src/mainboard/amd/bettong/BiosCallOuts.c +++ b/src/mainboard/amd/bettong/BiosCallOuts.c @@ -23,7 +23,6 @@ #include #include #include -#include #include #include "imc.h" diff --git a/src/mainboard/amd/bettong/Kconfig b/src/mainboard/amd/bettong/Kconfig index bcfceb19b3..0747bc1df5 100644 --- a/src/mainboard/amd/bettong/Kconfig +++ b/src/mainboard/amd/bettong/Kconfig @@ -20,7 +20,7 @@ if BOARD_AMD_BETTONG config BOARD_SPECIFIC_OPTIONS def_bool y - select BINARYPI_LEGACY_WRAPPER + #select BINARYPI_LEGACY_WRAPPER select CPU_AMD_PI_00660F01 select NORTHBRIDGE_AMD_PI_00660F01 select SOUTHBRIDGE_AMD_PI_KERN diff --git a/src/mainboard/amd/bettong/OemCustomize.c b/src/mainboard/amd/bettong/OemCustomize.c index 4843b2ade3..0e7882fb2e 100644 --- a/src/mainboard/amd/bettong/OemCustomize.c +++ b/src/mainboard/amd/bettong/OemCustomize.c @@ -14,7 +14,6 @@ */ #include -#include #include #include diff --git a/src/mainboard/amd/bettong/romstage.c b/src/mainboard/amd/bettong/romstage.c index 5201fa3a94..32f52de707 100644 --- a/src/mainboard/amd/bettong/romstage.c +++ b/src/mainboard/amd/bettong/romstage.c @@ -21,8 +21,6 @@ #include #include #include -#include -#include #include void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) diff --git a/src/mainboard/amd/db-ft3b-lc/Kconfig b/src/mainboard/amd/db-ft3b-lc/Kconfig index eaee3e7cd3..d7650327ff 100644 --- a/src/mainboard/amd/db-ft3b-lc/Kconfig +++ b/src/mainboard/amd/db-ft3b-lc/Kconfig @@ -21,7 +21,7 @@ if BOARD_AMD_DB_FT3B_LC config BOARD_SPECIFIC_OPTIONS def_bool y - select BINARYPI_LEGACY_WRAPPER + #select BINARYPI_LEGACY_WRAPPER select CPU_AMD_PI_00730F01 select NORTHBRIDGE_AMD_PI_00730F01 select SOUTHBRIDGE_AMD_PI_AVALON diff --git a/src/mainboard/amd/db-ft3b-lc/OemCustomize.c b/src/mainboard/amd/db-ft3b-lc/OemCustomize.c index a7f6fec1af..e90b92802a 100644 --- a/src/mainboard/amd/db-ft3b-lc/OemCustomize.c +++ b/src/mainboard/amd/db-ft3b-lc/OemCustomize.c @@ -14,7 +14,6 @@ */ #include -#include #include diff --git a/src/mainboard/amd/db-ft3b-lc/romstage.c b/src/mainboard/amd/db-ft3b-lc/romstage.c index 3e9b1c89ca..495ce59eff 100644 --- a/src/mainboard/amd/db-ft3b-lc/romstage.c +++ b/src/mainboard/amd/db-ft3b-lc/romstage.c @@ -21,8 +21,6 @@ #include #include #include -#include -#include #include #include diff --git a/src/mainboard/amd/lamar/Kconfig b/src/mainboard/amd/lamar/Kconfig index 5527d59a1b..e216e0260c 100644 --- a/src/mainboard/amd/lamar/Kconfig +++ b/src/mainboard/amd/lamar/Kconfig @@ -20,7 +20,7 @@ if BOARD_AMD_LAMAR config BOARD_SPECIFIC_OPTIONS def_bool y - select BINARYPI_LEGACY_WRAPPER + #select BINARYPI_LEGACY_WRAPPER select CPU_AMD_PI_00630F01 select NORTHBRIDGE_AMD_PI_00630F01 select SOUTHBRIDGE_AMD_PI_BOLTON diff --git a/src/mainboard/amd/lamar/OemCustomize.c b/src/mainboard/amd/lamar/OemCustomize.c index 2cd013b59a..4c1832b154 100644 --- a/src/mainboard/amd/lamar/OemCustomize.c +++ b/src/mainboard/amd/lamar/OemCustomize.c @@ -15,7 +15,6 @@ */ #include -#include static const PCIe_PORT_DESCRIPTOR PortList[] = { diff --git a/src/mainboard/amd/lamar/romstage.c b/src/mainboard/amd/lamar/romstage.c index 3f7d33f11b..77a0ea02f7 100644 --- a/src/mainboard/amd/lamar/romstage.c +++ b/src/mainboard/amd/lamar/romstage.c @@ -21,8 +21,6 @@ #include #include #include -#include -#include #include #include #include diff --git a/src/mainboard/amd/olivehillplus/Kconfig b/src/mainboard/amd/olivehillplus/Kconfig index 61ba33d3b9..3a72b2bb19 100644 --- a/src/mainboard/amd/olivehillplus/Kconfig +++ b/src/mainboard/amd/olivehillplus/Kconfig @@ -20,7 +20,7 @@ if BOARD_AMD_OLIVEHILLPLUS config BOARD_SPECIFIC_OPTIONS def_bool y - select BINARYPI_LEGACY_WRAPPER + #select BINARYPI_LEGACY_WRAPPER select CPU_AMD_PI_00730F01 select NORTHBRIDGE_AMD_PI_00730F01 select SOUTHBRIDGE_AMD_PI_AVALON diff --git a/src/mainboard/amd/olivehillplus/OemCustomize.c b/src/mainboard/amd/olivehillplus/OemCustomize.c index b66a88b7f9..76b7f25522 100644 --- a/src/mainboard/amd/olivehillplus/OemCustomize.c +++ b/src/mainboard/amd/olivehillplus/OemCustomize.c @@ -14,7 +14,6 @@ */ #include -#include static const PCIe_PORT_DESCRIPTOR PortList[] = { diff --git a/src/mainboard/amd/olivehillplus/romstage.c b/src/mainboard/amd/olivehillplus/romstage.c index 0181747c22..6df12e31cc 100644 --- a/src/mainboard/amd/olivehillplus/romstage.c +++ b/src/mainboard/amd/olivehillplus/romstage.c @@ -21,8 +21,6 @@ #include #include #include -#include -#include #include #include diff --git a/src/mainboard/bap/ode_e21XX/Kconfig b/src/mainboard/bap/ode_e21XX/Kconfig index 5b0d2fb2f3..a35107d77b 100644 --- a/src/mainboard/bap/ode_e21XX/Kconfig +++ b/src/mainboard/bap/ode_e21XX/Kconfig @@ -20,7 +20,7 @@ if BOARD_ODE_E21XX config BOARD_SPECIFIC_OPTIONS def_bool y - select BINARYPI_LEGACY_WRAPPER + #select BINARYPI_LEGACY_WRAPPER select CPU_AMD_PI_00730F01 select NORTHBRIDGE_AMD_PI_00730F01 select SOUTHBRIDGE_AMD_PI_AVALON diff --git a/src/mainboard/bap/ode_e21XX/OemCustomize.c b/src/mainboard/bap/ode_e21XX/OemCustomize.c index 008e5da4f4..97aaa4e6d0 100644 --- a/src/mainboard/bap/ode_e21XX/OemCustomize.c +++ b/src/mainboard/bap/ode_e21XX/OemCustomize.c @@ -14,7 +14,6 @@ */ #include -#include static const PCIe_PORT_DESCRIPTOR PortList[] = { diff --git a/src/mainboard/bap/ode_e21XX/romstage.c b/src/mainboard/bap/ode_e21XX/romstage.c index 10b7aabe83..774cd990b6 100644 --- a/src/mainboard/bap/ode_e21XX/romstage.c +++ b/src/mainboard/bap/ode_e21XX/romstage.c @@ -21,8 +21,6 @@ #include #include #include -#include -#include #include #include #include diff --git a/src/northbridge/amd/agesa/state_machine.h b/src/northbridge/amd/agesa/state_machine.h index 7d9fe9c5ef..02a7a41edc 100644 --- a/src/northbridge/amd/agesa/state_machine.h +++ b/src/northbridge/amd/agesa/state_machine.h @@ -20,8 +20,6 @@ #include #include -#define HAS_LEGACY_WRAPPER CONFIG(BINARYPI_LEGACY_WRAPPER) - /* eventlog */ void agesawrapper_trace(AGESA_STATUS ret, AMD_CONFIG_PARAMS *StdHeader, const char *func); AGESA_STATUS agesawrapper_amdreadeventlog(UINT8 HeapStatus); diff --git a/src/northbridge/amd/pi/00630F01/northbridge.c b/src/northbridge/amd/pi/00630F01/northbridge.c index 6bb121707e..6afea7c890 100644 --- a/src/northbridge/amd/pi/00630F01/northbridge.c +++ b/src/northbridge/amd/pi/00630F01/northbridge.c @@ -34,10 +34,6 @@ #include #include #include -#if CONFIG(BINARYPI_LEGACY_WRAPPER) -#include -#include -#endif #define MAX_NODE_NUMS MAX_NODES @@ -608,16 +604,6 @@ static void domain_read_resources(struct device *dev) static void domain_enable_resources(struct device *dev) { -#if CONFIG(BINARYPI_LEGACY_WRAPPER) - /* Must be called after PCI enumeration and resource allocation */ - if (!acpi_is_wakeup_s3()) { - /* Enable MMIO on AMD CPU Address Map Controller */ - amd_initcpuio(); - - agesawrapper_amdinitmid(); - } - printk(BIOS_DEBUG, " ader - leaving %s.\n", __func__); -#endif } #if CONFIG_HW_MEM_HOLE_SIZEK != 0 diff --git a/src/northbridge/amd/pi/00660F01/northbridge.c b/src/northbridge/amd/pi/00660F01/northbridge.c index 723e6f474d..c26f5aeed2 100644 --- a/src/northbridge/amd/pi/00660F01/northbridge.c +++ b/src/northbridge/amd/pi/00660F01/northbridge.c @@ -34,10 +34,6 @@ #include #include #include -#if CONFIG(BINARYPI_LEGACY_WRAPPER) -#include -#include -#endif #define MAX_NODE_NUMS MAX_NODES @@ -609,13 +605,6 @@ static void domain_read_resources(struct device *dev) static void domain_enable_resources(struct device *dev) { -#if CONFIG(BINARYPI_LEGACY_WRAPPER) - /* Must be called after PCI enumeration and resource allocation */ - if (!acpi_is_wakeup_s3()) - AGESAWRAPPER(amdinitmid); - - printk(BIOS_DEBUG, " ader - leaving domain_enable_resources.\n"); -#endif } #if CONFIG_HW_MEM_HOLE_SIZEK != 0 diff --git a/src/northbridge/amd/pi/00730F01/Makefile.inc b/src/northbridge/amd/pi/00730F01/Makefile.inc index 94cf72e5ad..33f2b79940 100644 --- a/src/northbridge/amd/pi/00730F01/Makefile.inc +++ b/src/northbridge/amd/pi/00730F01/Makefile.inc @@ -18,7 +18,5 @@ romstage-y += dimmSpd.c ramstage-y += northbridge.c ramstage-y += iommu.c -ifneq ($(CONFIG_BINARYPI_LEGACY_WRAPPER), y) romstage-y += state_machine.c ramstage-y += state_machine.c -endif diff --git a/src/northbridge/amd/pi/00730F01/northbridge.c b/src/northbridge/amd/pi/00730F01/northbridge.c index 3d7b883d17..acb20e6c63 100644 --- a/src/northbridge/amd/pi/00730F01/northbridge.c +++ b/src/northbridge/amd/pi/00730F01/northbridge.c @@ -36,10 +36,6 @@ #include #include #include -#if CONFIG(BINARYPI_LEGACY_WRAPPER) -#include -#include -#endif #define MAX_NODE_NUMS MAX_NODES @@ -835,13 +831,6 @@ static void domain_read_resources(struct device *dev) static void domain_enable_resources(struct device *dev) { -#if CONFIG(BINARYPI_LEGACY_WRAPPER) - /* Must be called after PCI enumeration and resource allocation */ - if (!acpi_is_wakeup_s3()) - AGESAWRAPPER(amdinitmid); - - printk(BIOS_DEBUG, " ader - leaving domain_enable_resources.\n"); -#endif } #if CONFIG_HW_MEM_HOLE_SIZEK != 0 diff --git a/src/northbridge/amd/pi/Makefile.inc b/src/northbridge/amd/pi/Makefile.inc index c2c8d8818d..ffafc6038f 100644 --- a/src/northbridge/amd/pi/Makefile.inc +++ b/src/northbridge/amd/pi/Makefile.inc @@ -19,11 +19,6 @@ subdirs-$(CONFIG_NORTHBRIDGE_AMD_PI_00630F01) += 00630F01 subdirs-$(CONFIG_NORTHBRIDGE_AMD_PI_00730F01) += 00730F01 subdirs-$(CONFIG_NORTHBRIDGE_AMD_PI_00660F01) += 00660F01 -ifeq ($(CONFIG_BINARYPI_LEGACY_WRAPPER), y) -romstage-y += agesawrapper.c -ramstage-y += agesawrapper.c -endif - romstage-y += ramtop.c postcar-y += ramtop.c ramstage-y += ramtop.c diff --git a/src/northbridge/amd/pi/agesawrapper.c b/src/northbridge/amd/pi/agesawrapper.c deleted file mode 100644 index e3bfd90fd8..0000000000 --- a/src/northbridge/amd/pi/agesawrapper.c +++ /dev/null @@ -1,317 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2012 - 2014 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -void __weak OemPostParams(AMD_POST_PARAMS *PostParams) {} - -#define FILECODE UNASSIGNED_FILE_FILECODE - -AGESA_STATUS agesawrapper_amdinitreset(void) -{ - AGESA_STATUS status; - AMD_INTERFACE_PARAMS AmdParamStruct; - AMD_RESET_PARAMS AmdResetParams; - - LibAmdMemFill (&AmdParamStruct, - 0, - sizeof(AMD_INTERFACE_PARAMS), - &(AmdParamStruct.StdHeader)); - - LibAmdMemFill (&AmdResetParams, - 0, - sizeof(AMD_RESET_PARAMS), - &(AmdResetParams.StdHeader)); - - AmdParamStruct.AgesaFunctionName = AMD_INIT_RESET; - AmdParamStruct.AllocationMethod = ByHost; - AmdParamStruct.NewStructSize = sizeof(AMD_RESET_PARAMS); - AmdParamStruct.NewStructPtr = &AmdResetParams; - AmdParamStruct.StdHeader.AltImageBasePtr = 0; - AmdParamStruct.StdHeader.CalloutPtr = &GetBiosCallout; - AmdParamStruct.StdHeader.Func = 0; - AmdParamStruct.StdHeader.ImageBasePtr = 0; - AmdCreateStruct (&AmdParamStruct); - - AmdResetParams.FchInterface.Xhci0Enable = CONFIG(HUDSON_XHCI_ENABLE); - if (CONFIG(SOUTHBRIDGE_AMD_PI_BOLTON)) - AmdResetParams.FchInterface.Xhci1Enable = TRUE; - - AmdResetParams.FchInterface.SataEnable = !((CONFIG_HUDSON_SATA_MODE == 0) || (CONFIG_HUDSON_SATA_MODE == 3)); - AmdResetParams.FchInterface.IdeEnable = (CONFIG_HUDSON_SATA_MODE == 0) || (CONFIG_HUDSON_SATA_MODE == 3); - - status = AmdInitReset(&AmdResetParams); - if (status != AGESA_SUCCESS) agesawrapper_amdreadeventlog(AmdParamStruct.StdHeader.HeapStatus); - AmdReleaseStruct (&AmdParamStruct); - return status; -} - -AGESA_STATUS agesawrapper_amdinitearly(void) -{ - AGESA_STATUS status; - AMD_INTERFACE_PARAMS AmdParamStruct; - AMD_EARLY_PARAMS *AmdEarlyParamsPtr; - - LibAmdMemFill (&AmdParamStruct, - 0, - sizeof(AMD_INTERFACE_PARAMS), - &(AmdParamStruct.StdHeader)); - - AmdParamStruct.AgesaFunctionName = AMD_INIT_EARLY; - AmdParamStruct.AllocationMethod = PreMemHeap; - AmdParamStruct.StdHeader.AltImageBasePtr = 0; - AmdParamStruct.StdHeader.CalloutPtr = &GetBiosCallout; - AmdParamStruct.StdHeader.Func = 0; - AmdParamStruct.StdHeader.ImageBasePtr = 0; - AmdCreateStruct (&AmdParamStruct); - - AmdEarlyParamsPtr = (AMD_EARLY_PARAMS *)AmdParamStruct.NewStructPtr; - OemCustomizeInitEarly (AmdEarlyParamsPtr); - - AmdEarlyParamsPtr->GnbConfig.PsppPolicy = PsppDisabled; - status = AmdInitEarly ((AMD_EARLY_PARAMS *)AmdParamStruct.NewStructPtr); - /* - * init_timer() needs to be called on CZ PI, because AGESA resets the LAPIC reload value - * on the AMD_INIT_EARLY call - */ - if (CONFIG(CPU_AMD_PI_00660F01)) - init_timer(); - if (status != AGESA_SUCCESS) agesawrapper_amdreadeventlog(AmdParamStruct.StdHeader.HeapStatus); - AmdReleaseStruct (&AmdParamStruct); - - return status; -} - -AGESA_STATUS agesawrapper_amdinitpost(void) -{ - AGESA_STATUS status; - AMD_INTERFACE_PARAMS AmdParamStruct; - AMD_POST_PARAMS *PostParams; - - LibAmdMemFill (&AmdParamStruct, - 0, - sizeof(AMD_INTERFACE_PARAMS), - &(AmdParamStruct.StdHeader)); - - AmdParamStruct.AgesaFunctionName = AMD_INIT_POST; - AmdParamStruct.AllocationMethod = PreMemHeap; - AmdParamStruct.StdHeader.AltImageBasePtr = NULL; - AmdParamStruct.StdHeader.CalloutPtr = &GetBiosCallout; - AmdParamStruct.StdHeader.Func = 0; - AmdParamStruct.StdHeader.ImageBasePtr = 0; - - AmdCreateStruct (&AmdParamStruct); - PostParams = (AMD_POST_PARAMS *)AmdParamStruct.NewStructPtr; - - PostParams->MemConfig.UmaMode = CONFIG(GFXUMA) ? UMA_AUTO : UMA_NONE; - PostParams->MemConfig.UmaSize = 0; - PostParams->MemConfig.BottomIo = (UINT16) - (CONFIG_BOTTOMIO_POSITION >> 24); - - OemPostParams(PostParams); - - status = AmdInitPost (PostParams); - - /* If UMA is enabled we currently have it below TOP_MEM as well. - * UMA may or may not be cacheable, so Sub4GCacheTop could be - * higher than UmaBase. With UMA_NONE we see UmaBase==0. */ - if (PostParams->MemConfig.UmaBase) - backup_top_of_low_cacheable(PostParams->MemConfig.UmaBase << 16); - else - backup_top_of_low_cacheable(PostParams->MemConfig.Sub4GCacheTop); - - printk( - BIOS_SPEW, - "setup_uma_memory: umamode %s\n", - (PostParams->MemConfig.UmaMode == UMA_AUTO) ? "UMA_AUTO" : - (PostParams->MemConfig.UmaMode == UMA_SPECIFIED) ? "UMA_SPECIFIED" : - (PostParams->MemConfig.UmaMode == UMA_NONE) ? "UMA_NONE" : - "unknown" - ); - printk( - BIOS_SPEW, - "setup_uma_memory: syslimit 0x%08llX, bottomio 0x%08lx\n", - (unsigned long long)(PostParams->MemConfig.SysLimit) << 16, - (unsigned long)(PostParams->MemConfig.BottomIo) << 16 - ); - printk( - BIOS_SPEW, - "setup_uma_memory: uma size %luMB, uma start 0x%08lx\n", - (unsigned long)(PostParams->MemConfig.UmaSize) >> (20 - 16), - (unsigned long)(PostParams->MemConfig.UmaBase) << 16 - ); - if (status != AGESA_SUCCESS) agesawrapper_amdreadeventlog(PostParams->StdHeader.HeapStatus); - AmdReleaseStruct (&AmdParamStruct); - - return status; -} - -AGESA_STATUS agesawrapper_amdinitenv(void) -{ - AGESA_STATUS status; - AMD_INTERFACE_PARAMS AmdParamStruct; - AMD_ENV_PARAMS *EnvParam; - - /* Initialize heap space */ - EmptyHeap(); - - LibAmdMemFill (&AmdParamStruct, - 0, - sizeof(AMD_INTERFACE_PARAMS), - &(AmdParamStruct.StdHeader)); - - AmdParamStruct.AgesaFunctionName = AMD_INIT_ENV; - AmdParamStruct.AllocationMethod = PostMemDram; - AmdParamStruct.StdHeader.AltImageBasePtr = 0; - AmdParamStruct.StdHeader.CalloutPtr = &GetBiosCallout; - AmdParamStruct.StdHeader.Func = 0; - AmdParamStruct.StdHeader.ImageBasePtr = 0; - status = AmdCreateStruct (&AmdParamStruct); - EnvParam = (AMD_ENV_PARAMS *)AmdParamStruct.NewStructPtr; - - EnvParam->FchInterface.AzaliaController = AzEnable; - EnvParam->FchInterface.SataClass = CONFIG_HUDSON_SATA_MODE; - EnvParam->FchInterface.SataEnable = !((CONFIG_HUDSON_SATA_MODE == 0) || (CONFIG_HUDSON_SATA_MODE == 3)); - EnvParam->FchInterface.IdeEnable = (CONFIG_HUDSON_SATA_MODE == 0) || (CONFIG_HUDSON_SATA_MODE == 3); - EnvParam->FchInterface.SataIdeMode = (CONFIG_HUDSON_SATA_MODE == 3); - - status = AmdInitEnv (EnvParam); - if (status != AGESA_SUCCESS) agesawrapper_amdreadeventlog(EnvParam->StdHeader.HeapStatus); - /* Initialize Subordinate Bus Number and Secondary Bus Number - * In platform BIOS this address is allocated by PCI enumeration code - Modify D1F0x18 - */ - - return status; -} - -AGESA_STATUS agesawrapper_amdinitmid(void) -{ - AGESA_STATUS status; - AMD_INTERFACE_PARAMS AmdParamStruct; - AMD_MID_PARAMS *MidParam; - - /* Enable MMIO on AMD CPU Address Map Controller */ - amd_initcpuio (); - - LibAmdMemFill (&AmdParamStruct, - 0, - sizeof(AMD_INTERFACE_PARAMS), - &(AmdParamStruct.StdHeader)); - - AmdParamStruct.AgesaFunctionName = AMD_INIT_MID; - AmdParamStruct.AllocationMethod = PostMemDram; - AmdParamStruct.StdHeader.AltImageBasePtr = 0; - AmdParamStruct.StdHeader.CalloutPtr = &GetBiosCallout; - AmdParamStruct.StdHeader.Func = 0; - AmdParamStruct.StdHeader.ImageBasePtr = 0; - - AmdCreateStruct (&AmdParamStruct); - MidParam = (AMD_MID_PARAMS *)AmdParamStruct.NewStructPtr; - - MidParam->GnbMidConfiguration.iGpuVgaMode = 0;/* 0 iGpuVgaAdapter, 1 iGpuVgaNonAdapter; */ - MidParam->GnbMidConfiguration.GnbIoapicAddress = 0xFEC20000; - - MidParam->FchInterface.AzaliaController = AzEnable; - MidParam->FchInterface.SataClass = CONFIG_HUDSON_SATA_MODE; - MidParam->FchInterface.SataEnable = !((CONFIG_HUDSON_SATA_MODE == 0) || (CONFIG_HUDSON_SATA_MODE == 3)); - MidParam->FchInterface.IdeEnable = (CONFIG_HUDSON_SATA_MODE == 0) || (CONFIG_HUDSON_SATA_MODE == 3); - MidParam->FchInterface.SataIdeMode = (CONFIG_HUDSON_SATA_MODE == 3); - - status = AmdInitMid ((AMD_MID_PARAMS *)AmdParamStruct.NewStructPtr); - if (status != AGESA_SUCCESS) agesawrapper_amdreadeventlog(AmdParamStruct.StdHeader.HeapStatus); - AmdReleaseStruct (&AmdParamStruct); - - return status; -} - -AGESA_STATUS agesawrapper_amdinitlate(void) -{ - AGESA_STATUS Status; - AMD_INTERFACE_PARAMS AmdParamStruct; - AMD_LATE_PARAMS *AmdLateParams; - - if (!ENV_RAMSTAGE) - return AGESA_UNSUPPORTED; - - LibAmdMemFill (&AmdParamStruct, - 0, - sizeof(AMD_INTERFACE_PARAMS), - &(AmdParamStruct.StdHeader)); - - AmdParamStruct.AgesaFunctionName = AMD_INIT_LATE; - AmdParamStruct.AllocationMethod = PostMemDram; - AmdParamStruct.StdHeader.AltImageBasePtr = 0; - AmdParamStruct.StdHeader.CalloutPtr = &GetBiosCallout; - AmdParamStruct.StdHeader.HeapStatus = HEAP_SYSTEM_MEM; - AmdParamStruct.StdHeader.Func = 0; - AmdParamStruct.StdHeader.ImageBasePtr = 0; - - /* NOTE: if not call amdcreatestruct, the initializer(AmdInitLateInitializer) would not be called */ - AmdCreateStruct(&AmdParamStruct); - AmdLateParams = (AMD_LATE_PARAMS *)AmdParamStruct.NewStructPtr; - AmdLateParams->GnbLateConfiguration.GnbIoapicId = CONFIG_MAX_CPUS + 1; - AmdLateParams->GnbLateConfiguration.FchIoapicId = CONFIG_MAX_CPUS; - /* Code for creating CDIT requires hop count table. If it is not - * present AGESA_ERROR is returned, which confuses users. CDIT is not - * written to the ACPI tables anyway. */ - AmdLateParams->PlatformConfig.UserOptionCdit = 0; - - Status = AmdInitLate(AmdLateParams); - if (Status != AGESA_SUCCESS) { - agesawrapper_amdreadeventlog(AmdLateParams->StdHeader.HeapStatus); - ASSERT(Status == AGESA_SUCCESS); - } - - agesawrapper_setlateinitptr(AmdLateParams); - - /* No AmdReleaseStruct(&AmdParamStruct), we need AmdLateParams later. */ - return Status; -} - -const void *agesawrapper_locate_module (const CHAR8 name[8]) -{ - const void *agesa; - const AMD_IMAGE_HEADER* image; - const AMD_MODULE_HEADER* module; - size_t file_size; - - if (CONFIG(VBOOT)) { - /* Use phys. location in flash and prevent vboot from searching cbmem */ - agesa = (void *)CONFIG_AGESA_BINARY_PI_LOCATION; - file_size = 0x100000; - } else { - agesa = cbfs_boot_map_with_leak((const char *)CONFIG_AGESA_CBFS_NAME, - CBFS_TYPE_RAW, &file_size); - } - - if (!agesa) - return NULL; - image = LibAmdLocateImage(agesa, agesa + file_size - 1, 4096, name); - module = (AMD_MODULE_HEADER*)image->ModuleInfoOffset; - - return module; -} diff --git a/src/northbridge/amd/pi/agesawrapper.h b/src/northbridge/amd/pi/agesawrapper.h deleted file mode 100644 index e1cec43c32..0000000000 --- a/src/northbridge/amd/pi/agesawrapper.h +++ /dev/null @@ -1,61 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef _AGESAWRAPPER_H_ -#define _AGESAWRAPPER_H_ - -#if CONFIG(BINARYPI_LEGACY_WRAPPER) - -#include -#include -#include - -AGESA_STATUS agesawrapper_amdinitreset(void); -AGESA_STATUS agesawrapper_amdinitearly(void); -AGESA_STATUS agesawrapper_amdinitenv(void); -AGESA_STATUS agesawrapper_amdinitlate(void); -AGESA_STATUS agesawrapper_amdinitpost(void); -AGESA_STATUS agesawrapper_amdinitmid(void); - -AGESA_STATUS agesawrapper_amdinitresume(void); -AGESA_STATUS agesawrapper_amdS3Save(void); -AGESA_STATUS agesawrapper_amds3laterestore(void); - -AGESA_STATUS agesawrapper_fchs3earlyrestore(void); -AGESA_STATUS agesawrapper_fchs3laterestore(void); - -#define AGESA_EVENTLOG(status, stdheader) \ - agesawrapper_trace(status, stdheader, __func__) - -#else - -/* Defined to make unused agesa_main() build. */ -static inline int agesawrapper_amdinitreset(void) { return -1; } -static inline int agesawrapper_amdinitearly(void) { return -1; } -static inline int agesawrapper_amdinitenv(void) { return -1; } -static inline int agesawrapper_amdinitpost(void) { return -1; } -static inline int agesawrapper_amdinitresume(void) { return -1; } -static inline int agesawrapper_amds3laterestore(void) { return -1; } - -#endif - -#if CONFIG(BINARYPI_LEGACY_WRAPPER) -const void *agesawrapper_locate_module (const CHAR8 name[8]); - -VOID OemCustomizeInitEarly (IN OUT AMD_EARLY_PARAMS *InitEarly); -void OemPostParams(AMD_POST_PARAMS *PostParams); -#endif - -#endif /* _AGESAWRAPPER_H_ */ diff --git a/src/northbridge/amd/pi/agesawrapper_call.h b/src/northbridge/amd/pi/agesawrapper_call.h deleted file mode 100644 index b235b49939..0000000000 --- a/src/northbridge/amd/pi/agesawrapper_call.h +++ /dev/null @@ -1,58 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef _AGESAWRAPPER_CALL_H_ -#define _AGESAWRAPPER_CALL_H_ - -#include -#include -#include - -/* - * Possible AGESA_STATUS values: - * - * 0x0 = AGESA_SUCCESS - * 0x1 = AGESA_UNSUPPORTED - * 0x2 = AGESA_BOUNDS_CHK - * 0x3 = AGESA_ALERT - * 0x4 = AGESA_WARNING - * 0x5 = AGESA_ERROR - * 0x6 = AGESA_CRITICAL - * 0x7 = AGESA_FATAL - */ -static const char *decodeAGESA_STATUS(AGESA_STATUS sret) -{ - const char *statusStrings[] = { "AGESA_SUCCESS", "AGESA_UNSUPPORTED", - "AGESA_BOUNDS_CHK", "AGESA_ALERT", - "AGESA_WARNING", "AGESA_ERROR", - "AGESA_CRITICAL", "AGESA_FATAL" - }; - if (sret > 7) return "unknown"; /* Non-AGESA error code */ - return statusStrings[sret]; -} - -static inline u32 do_agesawrapper(AGESA_STATUS (*func)(void), const char *name) -{ - AGESA_STATUS ret; - printk(BIOS_DEBUG, "agesawrapper_%s() entry\n", name); - ret = func(); - printk(BIOS_DEBUG, "agesawrapper_%s() returned %s\n", - name, decodeAGESA_STATUS(ret)); - return (u32)ret; -} - -#define AGESAWRAPPER(func) do_agesawrapper(agesawrapper_ ## func, #func) - -#define AGESAWRAPPER_PRE_CONSOLE(func) agesawrapper_ ## func() - -#endif diff --git a/src/vendorcode/amd/Kconfig b/src/vendorcode/amd/Kconfig index 10a49473a1..4e6624412d 100644 --- a/src/vendorcode/amd/Kconfig +++ b/src/vendorcode/amd/Kconfig @@ -50,7 +50,6 @@ endif config AGESA_EXTRA_TIMESTAMPS bool "Add instrumentation for AGESA calls" default n - depends on !BINARYPI_LEGACY_WRAPPER depends on DRIVERS_AMD_PI help Insert additional timestamps around each entrypoint into diff --git a/src/vendorcode/amd/pi/00630F01/binaryPI/AGESA.c b/src/vendorcode/amd/pi/00630F01/binaryPI/AGESA.c deleted file mode 100644 index fa6c276ce2..0000000000 --- a/src/vendorcode/amd/pi/00630F01/binaryPI/AGESA.c +++ /dev/null @@ -1,512 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * Agesa structures and definitions - * - * Contains AMD AGESA core interface - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: Include - * @e \$Revision: 85818 $ @e \$Date: 2013-01-11 17:04:21 -0600 (Fri, 11 Jan 2013) $ - */ -/***************************************************************************** - * - * Copyright (c) 2008 - 2014, Advanced Micro Devices, Inc. - * 2013 - 2014, Sage Electronic Engineering, LLC - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ***************************************************************************/ -#include -#include -#include -#include -#include -#include -#include -#include - -CONST UINT32 ImageSignature = IMAGE_SIGNATURE; -CONST UINT32 ModuleSignature = MODULE_SIGNATURE; -CONST CHAR8 ModuleIdentifier[] = AGESA_ID; - -/************************************************************************ - * - * AGESA Basic Level interface structure definition and function prototypes - * - ***********************************************************************/ - - -/********************************************************************** - * Interface call: AmdCreateStruct - **********************************************************************/ -AGESA_STATUS -AmdCreateStruct ( - IN OUT AMD_INTERFACE_PARAMS *InterfaceParams - ) -{ - MODULE_ENTRY Dispatcher = NULL; - const AMD_MODULE_HEADER* module = agesawrapper_locate_module(ModuleIdentifier); - InterfaceParams->StdHeader.Func = AMD_CREATE_STRUCT; - if (!module) return AGESA_UNSUPPORTED; - Dispatcher = module->ModuleDispatcher; - return Dispatcher(InterfaceParams); -} - -/********************************************************************** - * Interface call: AmdReleaseStruct - **********************************************************************/ -AGESA_STATUS -AmdReleaseStruct ( - IN OUT AMD_INTERFACE_PARAMS *InterfaceParams - ) -{ - MODULE_ENTRY Dispatcher = NULL; - const AMD_MODULE_HEADER* module = agesawrapper_locate_module(ModuleIdentifier); - InterfaceParams->StdHeader.Func = AMD_RELEASE_STRUCT; - if (!module) return AGESA_UNSUPPORTED; - Dispatcher = module->ModuleDispatcher; - return Dispatcher(InterfaceParams); -} - -/********************************************************************** - * Interface call: AmdInitReset - **********************************************************************/ -AGESA_STATUS -AmdInitReset ( - IN OUT AMD_RESET_PARAMS *ResetParams - ) -{ - MODULE_ENTRY Dispatcher = NULL; - const AMD_MODULE_HEADER* module = agesawrapper_locate_module(ModuleIdentifier); - ResetParams->StdHeader.Func = AMD_INIT_RESET; - if (!module) return AGESA_UNSUPPORTED; - Dispatcher = module->ModuleDispatcher; - return Dispatcher(ResetParams); -} - -/********************************************************************** - * Interface call: AmdInitEarly - **********************************************************************/ -AGESA_STATUS -AmdInitEarly ( - IN OUT AMD_EARLY_PARAMS *EarlyParams - ) -{ - MODULE_ENTRY Dispatcher = NULL; - const AMD_MODULE_HEADER* module = agesawrapper_locate_module(ModuleIdentifier); - EarlyParams->StdHeader.Func = AMD_INIT_EARLY; - if (!module) return AGESA_UNSUPPORTED; - Dispatcher = module->ModuleDispatcher; - return Dispatcher(EarlyParams); -} - -/********************************************************************** - * Interface call: AmdInitPost - **********************************************************************/ -AGESA_STATUS -AmdInitPost ( - IN OUT AMD_POST_PARAMS *PostParams ///< Amd Cpu init param - ) -{ - MODULE_ENTRY Dispatcher = NULL; - const AMD_MODULE_HEADER* module = agesawrapper_locate_module(ModuleIdentifier); - PostParams->StdHeader.Func = AMD_INIT_POST; - if (!module) return AGESA_UNSUPPORTED; - Dispatcher = module->ModuleDispatcher; - return Dispatcher(PostParams); -} - -/********************************************************************** - * Interface call: AmdInitEnv - **********************************************************************/ -AGESA_STATUS -AmdInitEnv ( - IN OUT AMD_ENV_PARAMS *EnvParams - ) -{ - MODULE_ENTRY Dispatcher = NULL; - const AMD_MODULE_HEADER* module = agesawrapper_locate_module(ModuleIdentifier); - EnvParams->StdHeader.Func = AMD_INIT_ENV; - if (!module) return AGESA_UNSUPPORTED; - Dispatcher = module->ModuleDispatcher; - return Dispatcher(EnvParams); -} - -/********************************************************************** - * Interface call: AmdInitMid - **********************************************************************/ -AGESA_STATUS -AmdInitMid ( - IN OUT AMD_MID_PARAMS *MidParams - ) -{ - MODULE_ENTRY Dispatcher = NULL; - const AMD_MODULE_HEADER* module = agesawrapper_locate_module(ModuleIdentifier); - MidParams->StdHeader.Func = AMD_INIT_MID; - if (!module) return AGESA_UNSUPPORTED; - Dispatcher = module->ModuleDispatcher; - return Dispatcher(MidParams); -} - -/********************************************************************** - * Interface call: AmdInitLate - **********************************************************************/ -AGESA_STATUS -AmdInitLate ( - IN OUT AMD_LATE_PARAMS *LateParams - ) -{ - MODULE_ENTRY Dispatcher = NULL; - const AMD_MODULE_HEADER* module = agesawrapper_locate_module(ModuleIdentifier); - LateParams->StdHeader.Func = AMD_INIT_LATE; - if (!module) return AGESA_UNSUPPORTED; - Dispatcher = module->ModuleDispatcher; - return Dispatcher(LateParams); -} - -/********************************************************************** - * Interface call: AmdInitRecovery - **********************************************************************/ -AGESA_STATUS -AmdInitRecovery ( - IN OUT AMD_RECOVERY_PARAMS *RecoveryParams - ) -{ - MODULE_ENTRY Dispatcher = NULL; - const AMD_MODULE_HEADER* module = agesawrapper_locate_module(ModuleIdentifier); - RecoveryParams->StdHeader.Func = AMD_INIT_RECOVERY; - if (!module) return AGESA_UNSUPPORTED; - Dispatcher = module->ModuleDispatcher; - return Dispatcher(RecoveryParams); -} - -/********************************************************************** - * Interface call: AmdInitResume - **********************************************************************/ -AGESA_STATUS -AmdInitResume ( - IN AMD_RESUME_PARAMS *ResumeParams - ) -{ - MODULE_ENTRY Dispatcher = NULL; - const AMD_MODULE_HEADER* module = agesawrapper_locate_module(ModuleIdentifier); - ResumeParams->StdHeader.Func = AMD_INIT_RESUME; - if (!module) return AGESA_UNSUPPORTED; - Dispatcher = module->ModuleDispatcher; - return Dispatcher(ResumeParams); -} - -/********************************************************************** - * Interface call: AmdS3LateRestore - **********************************************************************/ -AGESA_STATUS -AmdS3LateRestore ( - IN OUT AMD_S3LATE_PARAMS *S3LateParams - ) -{ - MODULE_ENTRY Dispatcher = NULL; - const AMD_MODULE_HEADER* module = agesawrapper_locate_module(ModuleIdentifier); - S3LateParams->StdHeader.Func = AMD_S3LATE_RESTORE; - if (!module) return AGESA_UNSUPPORTED; - Dispatcher = module->ModuleDispatcher; - return Dispatcher(S3LateParams); -} - -/********************************************************************** - * Interface call: AmdS3Save - **********************************************************************/ -AGESA_STATUS -AmdS3Save ( - IN OUT AMD_S3SAVE_PARAMS *AmdS3SaveParams - ) -{ - MODULE_ENTRY Dispatcher = NULL; - const AMD_MODULE_HEADER* module = agesawrapper_locate_module(ModuleIdentifier); - AmdS3SaveParams->StdHeader.Func = AMD_S3_SAVE; - if (!module) return AGESA_UNSUPPORTED; - Dispatcher = module->ModuleDispatcher; - return Dispatcher(AmdS3SaveParams); -} - -/********************************************************************** - * Interface call: AmdLateRunApTask - **********************************************************************/ -AGESA_STATUS -AmdLateRunApTask ( - IN AP_EXE_PARAMS *AmdApExeParams -) -{ - MODULE_ENTRY Dispatcher = NULL; - const AMD_MODULE_HEADER* module = agesawrapper_locate_module(ModuleIdentifier); - AmdApExeParams->StdHeader.Func = AMD_LATE_RUN_AP_TASK; - if (!module) return AGESA_UNSUPPORTED; - Dispatcher = module->ModuleDispatcher; - return Dispatcher(AmdApExeParams); -} - -/********************************************************************** - * Interface service call: AmdGetApicId - **********************************************************************/ -AGESA_STATUS -AmdGetApicId ( - IN OUT AMD_APIC_PARAMS *AmdParamApic -) -{ - MODULE_ENTRY Dispatcher = NULL; - const AMD_MODULE_HEADER* module = agesawrapper_locate_module(ModuleIdentifier); - AmdParamApic->StdHeader.Func = AMD_GET_APIC_ID; - if (!module) return AGESA_UNSUPPORTED; - Dispatcher = module->ModuleDispatcher; - return Dispatcher(AmdParamApic); -} - -/********************************************************************** - * Interface service call: AmdGetPciAddress - **********************************************************************/ -AGESA_STATUS -AmdGetPciAddress ( - IN OUT AMD_GET_PCI_PARAMS *AmdParamGetPci -) -{ - MODULE_ENTRY Dispatcher = NULL; - const AMD_MODULE_HEADER* module = agesawrapper_locate_module(ModuleIdentifier); - AmdParamGetPci->StdHeader.Func = AMD_GET_PCI_ADDRESS; - if (!module) return AGESA_UNSUPPORTED; - Dispatcher = module->ModuleDispatcher; - return Dispatcher(AmdParamGetPci); -} - -/********************************************************************** - * Interface service call: AmdIdentifyCore - **********************************************************************/ -AGESA_STATUS -AmdIdentifyCore ( - IN OUT AMD_IDENTIFY_PARAMS *AmdParamIdentify -) -{ - MODULE_ENTRY Dispatcher = NULL; - const AMD_MODULE_HEADER* module = agesawrapper_locate_module(ModuleIdentifier); - AmdParamIdentify->StdHeader.Func = AMD_IDENTIFY_CORE; - if (!module) return AGESA_UNSUPPORTED; - Dispatcher = module->ModuleDispatcher; - return Dispatcher(AmdParamIdentify); -} - -/********************************************************************** - * Interface service call: AmdReadEventLog - **********************************************************************/ -AGESA_STATUS -AmdReadEventLog ( - IN EVENT_PARAMS *Event -) -{ - MODULE_ENTRY Dispatcher = NULL; - const AMD_MODULE_HEADER* module = agesawrapper_locate_module(ModuleIdentifier); - Event->StdHeader.Func = AMD_READ_EVENT_LOG; - if (!module) return AGESA_UNSUPPORTED; - Dispatcher = module->ModuleDispatcher; - return Dispatcher(Event); -} - -/********************************************************************** - * Interface service call: AmdIdentifyDimm - **********************************************************************/ -AGESA_STATUS -AmdIdentifyDimm ( - IN OUT AMD_IDENTIFY_DIMM *AmdDimmIdentify -) -{ - MODULE_ENTRY Dispatcher = NULL; - const AMD_MODULE_HEADER* module = agesawrapper_locate_module(ModuleIdentifier); - AmdDimmIdentify->StdHeader.Func = AMD_IDENTIFY_DIMMS; - if (!module) return AGESA_UNSUPPORTED; - Dispatcher = module->ModuleDispatcher; - return Dispatcher(AmdDimmIdentify); -} - -AGESA_STATUS -AmdIdsRunApTaskLate ( - IN AP_EXE_PARAMS *AmdApExeParams - ) -{ - AmdApExeParams->StdHeader.Func = -1; - return AGESA_UNSUPPORTED; -} - -/********************************************************************** - * Interface service call: AmdGet2DDataEye - **********************************************************************/ -AGESA_STATUS -AmdGet2DDataEye ( - IN OUT AMD_GET_DATAEYE *AmdGetDataEye - ) -{ - MODULE_ENTRY Dispatcher = NULL; - const AMD_MODULE_HEADER* module = agesawrapper_locate_module(ModuleIdentifier); - AmdGetDataEye->StdHeader.Func = AMD_GET_2D_DATA_EYE; - if (!module) return AGESA_UNSUPPORTED; - Dispatcher = module->ModuleDispatcher; - return Dispatcher(AmdGetDataEye); -} - -/********************************************************************** - * FCH Functions - **********************************************************************/ - -VOID FchInitS3LateRestore (IN FCH_DATA_BLOCK *FchDataPtr); -VOID FchInitS3EarlyRestore (IN FCH_DATA_BLOCK *FchDataPtr); - -VOID -FchInitS3EarlyRestore ( - IN FCH_DATA_BLOCK *FchDataPtr - ) -{ - MODULE_ENTRY Dispatcher = NULL; - const AMD_MODULE_HEADER* module = agesawrapper_locate_module(ModuleIdentifier); - FchDataPtr->StdHeader->Func = FCH_INIT_S3_EARLY_RESTORE; - if (!module) return; - Dispatcher = module->ModuleDispatcher; - Dispatcher(FchDataPtr); -} - -VOID -FchInitS3LateRestore ( - IN FCH_DATA_BLOCK *FchDataPtr - ) -{ - MODULE_ENTRY Dispatcher = NULL; - const AMD_MODULE_HEADER* module = agesawrapper_locate_module(ModuleIdentifier); - FchDataPtr->StdHeader->Func = FCH_INIT_S3_LATE_RESTORE; - if (!module) return; - Dispatcher = module->ModuleDispatcher; - Dispatcher(FchDataPtr); -} - -/** - * WaitForEcLDN9MailboxCmdAck - * - * - * @param[in] StdHeader - * - */ -VOID -WaitForEcLDN9MailboxCmdAck ( - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - StdHeader->Func = 0; -} - -/** - * ImcSleep - IMC Sleep. - * - * - * @param[in] FchDataPtr Fch configuration structure pointer. - * - */ -VOID -ImcSleep ( - IN VOID *FchDataPtr - ) -{ - ((FCH_DATA_BLOCK*)FchDataPtr)->StdHeader->Func = 0; -} - -/** - * SoftwareDisableImc - Software disable IMC strap - * - * - * @param[in] FchDataPtr Fch configuration structure pointer. - * - */ -VOID -SoftwareDisableImc ( - IN VOID *FchDataPtr - ) -{ - ((FCH_DATA_BLOCK*)FchDataPtr)->StdHeader->Func = 0; -} - -/** - * ImcEnableSurebootTimer - IMC Enable Sureboot Timer. - * - * - * @param[in] FchDataPtr Fch configuration structure pointer. - * - */ -VOID -ImcEnableSurebootTimer ( - IN VOID *FchDataPtr - ) -{ - ((FCH_DATA_BLOCK*)FchDataPtr)->StdHeader->Func = 0; -} - -/** - * ImcDisableSurebootTimer - IMC Disable Sureboot Timer. - * - * - * @param[in] FchDataPtr Fch configuration structure pointer. - * - */ -VOID -ImcDisableSurebootTimer ( - IN VOID *FchDataPtr - ) -{ - ((FCH_DATA_BLOCK*)FchDataPtr)->StdHeader->Func = 0; -} - -/** - * ImcWakeup - IMC Wakeup. - * - * - * @param[in] FchDataPtr Fch configuration structure pointer. - * - */ -VOID -ImcWakeup ( - IN VOID *FchDataPtr - ) -{ - ((FCH_DATA_BLOCK*)FchDataPtr)->StdHeader->Func = 0; -} - -/** - * ImcIdle - IMC Idle. - * - * - * @param[in] FchDataPtr Fch configuration structure pointer. - * - */ -VOID -ImcIdle ( - IN VOID *FchDataPtr - ) -{ - ((FCH_DATA_BLOCK*)FchDataPtr)->StdHeader->Func = 0; -} diff --git a/src/vendorcode/amd/pi/00660F01/binaryPI/AGESA.c b/src/vendorcode/amd/pi/00660F01/binaryPI/AGESA.c deleted file mode 100644 index a4eef5ad86..0000000000 --- a/src/vendorcode/amd/pi/00660F01/binaryPI/AGESA.c +++ /dev/null @@ -1,402 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * Agesa structures and definitions - * - * Contains AMD AGESA core interface - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: Include - * @e \$Revision: 85818 $ @e \$Date: 2013-01-11 17:04:21 -0600 (Fri, 11 Jan 2013) $ - */ -/***************************************************************************** - * - * Copyright (c) 2008 - 2013, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ***************************************************************************/ -// TODO This list needs to be pruned of anything that is not API -#include "AGESA.h" -#include "agesawrapper.h" -#include "AcpiLib.h" -#include "FchCommonCfg.h" -#include "Fch.h" -#include "FchDef.h" -#include "amdlib.h" -#include "cbfs.h" -#include -#include - -CONST UINT32 ImageSignature = IMAGE_SIGNATURE; -CONST UINT32 ModuleSignature = MODULE_SIGNATURE; -CONST CHAR8 ModuleIdentifier[] = AGESA_ID; - -/********************************************************************** - * Interface call: AmdCreateStruct - **********************************************************************/ -AGESA_STATUS -AmdCreateStruct ( - IN OUT AMD_INTERFACE_PARAMS *InterfaceParams - ) -{ - MODULE_ENTRY Dispatcher = NULL; - const AMD_MODULE_HEADER* module = agesawrapper_locate_module(ModuleIdentifier); - InterfaceParams->StdHeader.Func = AMD_CREATE_STRUCT; - if (!module) return AGESA_UNSUPPORTED; - Dispatcher = module->ModuleDispatcher; - return Dispatcher(InterfaceParams); -} - -/********************************************************************** - * Interface call: AmdReleaseStruct - **********************************************************************/ -AGESA_STATUS -AmdReleaseStruct ( - IN OUT AMD_INTERFACE_PARAMS *InterfaceParams - ) -{ - MODULE_ENTRY Dispatcher = NULL; - const AMD_MODULE_HEADER* module = agesawrapper_locate_module(ModuleIdentifier); - InterfaceParams->StdHeader.Func = AMD_RELEASE_STRUCT; - if (!module) return AGESA_UNSUPPORTED; - Dispatcher = module->ModuleDispatcher; - return Dispatcher(InterfaceParams); -} - -/********************************************************************** - * Interface call: AmdInitReset - **********************************************************************/ -AGESA_STATUS -AmdInitReset ( - IN OUT AMD_RESET_PARAMS *ResetParams - ) -{ - MODULE_ENTRY Dispatcher = NULL; - const AMD_MODULE_HEADER* module = agesawrapper_locate_module(ModuleIdentifier); - ResetParams->StdHeader.Func = AMD_INIT_RESET; - if (!module) return AGESA_UNSUPPORTED; - Dispatcher = module->ModuleDispatcher; - return Dispatcher(ResetParams); -} - -/********************************************************************** - * Interface call: AmdInitEarly - **********************************************************************/ -AGESA_STATUS -AmdInitEarly ( - IN OUT AMD_EARLY_PARAMS *EarlyParams - ) -{ - MODULE_ENTRY Dispatcher = NULL; - const AMD_MODULE_HEADER* module = agesawrapper_locate_module(ModuleIdentifier); - EarlyParams->StdHeader.Func = AMD_INIT_EARLY; - if (!module) return AGESA_UNSUPPORTED; - Dispatcher = module->ModuleDispatcher; - return Dispatcher(EarlyParams); -} - -/********************************************************************** - * Interface call: AmdInitPost - **********************************************************************/ -AGESA_STATUS -AmdInitPost ( - IN OUT AMD_POST_PARAMS *PostParams ///< Amd Cpu init param - ) -{ - MODULE_ENTRY Dispatcher = NULL; - const AMD_MODULE_HEADER* module = agesawrapper_locate_module(ModuleIdentifier); - PostParams->StdHeader.Func = AMD_INIT_POST; - if (!module) return AGESA_UNSUPPORTED; - Dispatcher = module->ModuleDispatcher; - return Dispatcher(PostParams); -} - -/********************************************************************** - * Interface call: AmdInitEnv - **********************************************************************/ -AGESA_STATUS -AmdInitEnv ( - IN OUT AMD_ENV_PARAMS *EnvParams - ) -{ - MODULE_ENTRY Dispatcher = NULL; - const AMD_MODULE_HEADER* module = agesawrapper_locate_module(ModuleIdentifier); - EnvParams->StdHeader.Func = AMD_INIT_ENV; - if (!module) return AGESA_UNSUPPORTED; - Dispatcher = module->ModuleDispatcher; - return Dispatcher(EnvParams); -} - -/********************************************************************** - * Interface call: AmdInitMid - **********************************************************************/ -AGESA_STATUS -AmdInitMid ( - IN OUT AMD_MID_PARAMS *MidParams - ) -{ - MODULE_ENTRY Dispatcher = NULL; - const AMD_MODULE_HEADER* module = agesawrapper_locate_module(ModuleIdentifier); - MidParams->StdHeader.Func = AMD_INIT_MID; - if (!module) return AGESA_UNSUPPORTED; - Dispatcher = module->ModuleDispatcher; - return Dispatcher(MidParams); -} - -/********************************************************************** - * Interface call: AmdInitLate - **********************************************************************/ -AGESA_STATUS -AmdInitLate ( - IN OUT AMD_LATE_PARAMS *LateParams - ) -{ - MODULE_ENTRY Dispatcher = NULL; - const AMD_MODULE_HEADER* module = agesawrapper_locate_module(ModuleIdentifier); - LateParams->StdHeader.Func = AMD_INIT_LATE; - if (!module) return AGESA_UNSUPPORTED; - Dispatcher = module->ModuleDispatcher; - return Dispatcher(LateParams); -} - -/********************************************************************** - * Interface call: AmdInitRecovery - **********************************************************************/ -AGESA_STATUS -AmdInitRecovery ( - IN OUT AMD_RECOVERY_PARAMS *RecoveryParams - ) -{ - MODULE_ENTRY Dispatcher = NULL; - const AMD_MODULE_HEADER* module = agesawrapper_locate_module(ModuleIdentifier); - RecoveryParams->StdHeader.Func = AMD_INIT_RECOVERY; - if (!module) return AGESA_UNSUPPORTED; - Dispatcher = module->ModuleDispatcher; - return Dispatcher(RecoveryParams); -} - -/********************************************************************** - * Interface call: AmdInitResume - **********************************************************************/ -AGESA_STATUS -AmdInitResume ( - IN AMD_RESUME_PARAMS *ResumeParams - ) -{ - MODULE_ENTRY Dispatcher = NULL; - const AMD_MODULE_HEADER* module = agesawrapper_locate_module(ModuleIdentifier); - ResumeParams->StdHeader.Func = AMD_INIT_RESUME; - if (!module) return AGESA_UNSUPPORTED; - Dispatcher = module->ModuleDispatcher; - return Dispatcher(ResumeParams); -} - -/********************************************************************** - * Interface call: AmdS3LateRestore - **********************************************************************/ -AGESA_STATUS -AmdS3LateRestore ( - IN OUT AMD_S3LATE_PARAMS *S3LateParams - ) -{ - MODULE_ENTRY Dispatcher = NULL; - const AMD_MODULE_HEADER* module = agesawrapper_locate_module(ModuleIdentifier); - S3LateParams->StdHeader.Func = AMD_S3LATE_RESTORE; - if (!module) return AGESA_UNSUPPORTED; - Dispatcher = module->ModuleDispatcher; - return Dispatcher(S3LateParams); -} - -/********************************************************************** - * Interface call: AmdInitRtb - **********************************************************************/ -AGESA_STATUS -AmdInitRtb ( - IN OUT AMD_RTB_PARAMS *AmdInitRtbParams - ) -{ - MODULE_ENTRY Dispatcher = NULL; - const AMD_MODULE_HEADER* module = agesawrapper_locate_module(ModuleIdentifier); - AmdInitRtbParams->StdHeader.Func = AMD_INIT_RTB; - if (!module) return AGESA_UNSUPPORTED; - Dispatcher = module->ModuleDispatcher; - return Dispatcher(AmdInitRtbParams); -} - -/********************************************************************** - * Interface call: AmdLateRunApTask - **********************************************************************/ -AGESA_STATUS -AmdLateRunApTask ( - IN AP_EXE_PARAMS *AmdApExeParams -) -{ - MODULE_ENTRY Dispatcher = NULL; - const AMD_MODULE_HEADER* module = agesawrapper_locate_module(ModuleIdentifier); - AmdApExeParams->StdHeader.Func = AMD_LATE_RUN_AP_TASK; - if (!module) return AGESA_UNSUPPORTED; - Dispatcher = module->ModuleDispatcher; - return Dispatcher(AmdApExeParams); -} - -/********************************************************************** - * Interface service call: AmdGetApicId - **********************************************************************/ -AGESA_STATUS -AmdGetApicId ( - IN OUT AMD_APIC_PARAMS *AmdParamApic -) -{ - MODULE_ENTRY Dispatcher = NULL; - const AMD_MODULE_HEADER* module = agesawrapper_locate_module(ModuleIdentifier); - AmdParamApic->StdHeader.Func = AMD_GET_APIC_ID; - if (!module) return AGESA_UNSUPPORTED; - Dispatcher = module->ModuleDispatcher; - return Dispatcher(AmdParamApic); -} - -/********************************************************************** - * Interface service call: AmdGetPciAddress - **********************************************************************/ -AGESA_STATUS -AmdGetPciAddress ( - IN OUT AMD_GET_PCI_PARAMS *AmdParamGetPci -) -{ - MODULE_ENTRY Dispatcher = NULL; - const AMD_MODULE_HEADER* module = agesawrapper_locate_module(ModuleIdentifier); - AmdParamGetPci->StdHeader.Func = AMD_GET_PCI_ADDRESS; - if (!module) return AGESA_UNSUPPORTED; - Dispatcher = module->ModuleDispatcher; - return Dispatcher(AmdParamGetPci); -} - -/********************************************************************** - * Interface service call: AmdIdentifyCore - **********************************************************************/ -AGESA_STATUS -AmdIdentifyCore ( - IN OUT AMD_IDENTIFY_PARAMS *AmdParamIdentify -) -{ - MODULE_ENTRY Dispatcher = NULL; - const AMD_MODULE_HEADER* module = agesawrapper_locate_module(ModuleIdentifier); - AmdParamIdentify->StdHeader.Func = AMD_IDENTIFY_CORE; - if (!module) return AGESA_UNSUPPORTED; - Dispatcher = module->ModuleDispatcher; - return Dispatcher(AmdParamIdentify); -} - -/********************************************************************** - * Interface service call: AmdReadEventLog - **********************************************************************/ -AGESA_STATUS -AmdReadEventLog ( - IN EVENT_PARAMS *Event -) -{ - MODULE_ENTRY Dispatcher = NULL; - const AMD_MODULE_HEADER* module = agesawrapper_locate_module(ModuleIdentifier); - Event->StdHeader.Func = AMD_READ_EVENT_LOG; - if (!module) return AGESA_UNSUPPORTED; - Dispatcher = module->ModuleDispatcher; - return Dispatcher(Event); -} - -/********************************************************************** - * Interface service call: AmdIdentifyDimm - **********************************************************************/ -AGESA_STATUS -AmdIdentifyDimm ( - IN OUT AMD_IDENTIFY_DIMM *AmdDimmIdentify -) -{ - MODULE_ENTRY Dispatcher = NULL; - const AMD_MODULE_HEADER* module = agesawrapper_locate_module(ModuleIdentifier); - AmdDimmIdentify->StdHeader.Func = AMD_IDENTIFY_DIMMS; - if (!module) return AGESA_UNSUPPORTED; - Dispatcher = module->ModuleDispatcher; - return Dispatcher(AmdDimmIdentify); -} - -AGESA_STATUS -AmdIdsRunApTaskLate ( - IN AP_EXE_PARAMS *AmdApExeParams - ) -{ - AmdApExeParams->StdHeader.Func = -1; - return AGESA_UNSUPPORTED; -} - -/********************************************************************** - * Interface service call: AmdGet2DDataEye - **********************************************************************/ -AGESA_STATUS -AmdGet2DDataEye ( - IN OUT AMD_GET_DATAEYE *AmdGetDataEye - ) -{ - MODULE_ENTRY Dispatcher = NULL; - const AMD_MODULE_HEADER* module = agesawrapper_locate_module(ModuleIdentifier); - AmdGetDataEye->StdHeader.Func = AMD_GET_2D_DATA_EYE; - if (!module) return AGESA_UNSUPPORTED; - Dispatcher = module->ModuleDispatcher; - return Dispatcher(AmdGetDataEye); -} - -/********************************************************************** - * FCH Functions - **********************************************************************/ - -VOID FchInitS3LateRestore (IN FCH_DATA_BLOCK *FchDataPtr); -VOID FchInitS3EarlyRestore (IN FCH_DATA_BLOCK *FchDataPtr); - -VOID -FchInitS3EarlyRestore ( - IN FCH_DATA_BLOCK *FchDataPtr - ) -{ - MODULE_ENTRY Dispatcher = NULL; - const AMD_MODULE_HEADER* module = agesawrapper_locate_module(ModuleIdentifier); - FchDataPtr->StdHeader->Func = FCH_INIT_S3_EARLY_RESTORE; - if (!module) return; - Dispatcher = module->ModuleDispatcher; - Dispatcher(FchDataPtr); -} - -VOID -FchInitS3LateRestore ( - IN FCH_DATA_BLOCK *FchDataPtr - ) -{ - MODULE_ENTRY Dispatcher = NULL; - const AMD_MODULE_HEADER* module = agesawrapper_locate_module(ModuleIdentifier); - FchDataPtr->StdHeader->Func = FCH_INIT_S3_LATE_RESTORE; - if (!module) return; - Dispatcher = module->ModuleDispatcher; - Dispatcher(FchDataPtr); -} diff --git a/src/vendorcode/amd/pi/00730F01/binaryPI/AGESA.c b/src/vendorcode/amd/pi/00730F01/binaryPI/AGESA.c deleted file mode 100644 index 7b1a98a7af..0000000000 --- a/src/vendorcode/amd/pi/00730F01/binaryPI/AGESA.c +++ /dev/null @@ -1,511 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * Agesa structures and definitions - * - * Contains AMD AGESA core interface - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: Include - * @e \$Revision: 85818 $ @e \$Date: 2013-01-11 17:04:21 -0600 (Fri, 11 Jan 2013) $ - */ -/***************************************************************************** - * - * Copyright (c) 2008 - 2013, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ***************************************************************************/ -// TODO This list needs to be pruned of anything that is not API -#include "AGESA.h" -#include -#include "AcpiLib.h" -#include "FchCommonCfg.h" -#include "Fch.h" -#include "FchDef.h" -#include "amdlib.h" - -CONST UINT32 ImageSignature = IMAGE_SIGNATURE; -CONST UINT32 ModuleSignature = MODULE_SIGNATURE; -CONST CHAR8 ModuleIdentifier[] = AGESA_ID; - -/************************************************************************ - * - * AGESA Basic Level interface structure definition and function prototypes - * - ***********************************************************************/ - - -/********************************************************************** - * Interface call: AmdCreateStruct - **********************************************************************/ -AGESA_STATUS -AmdCreateStruct ( - IN OUT AMD_INTERFACE_PARAMS *InterfaceParams - ) -{ - MODULE_ENTRY Dispatcher = NULL; - const AMD_MODULE_HEADER* module = agesawrapper_locate_module(ModuleIdentifier); - InterfaceParams->StdHeader.Func = AMD_CREATE_STRUCT; - if (!module) return AGESA_UNSUPPORTED; - Dispatcher = module->ModuleDispatcher; - return Dispatcher(InterfaceParams); -} - -/********************************************************************** - * Interface call: AmdReleaseStruct - **********************************************************************/ -AGESA_STATUS -AmdReleaseStruct ( - IN OUT AMD_INTERFACE_PARAMS *InterfaceParams - ) -{ - MODULE_ENTRY Dispatcher = NULL; - const AMD_MODULE_HEADER* module = agesawrapper_locate_module(ModuleIdentifier); - InterfaceParams->StdHeader.Func = AMD_RELEASE_STRUCT; - if (!module) return AGESA_UNSUPPORTED; - Dispatcher = module->ModuleDispatcher; - return Dispatcher(InterfaceParams); -} - -/********************************************************************** - * Interface call: AmdInitReset - **********************************************************************/ -AGESA_STATUS -AmdInitReset ( - IN OUT AMD_RESET_PARAMS *ResetParams - ) -{ - MODULE_ENTRY Dispatcher = NULL; - const AMD_MODULE_HEADER* module = agesawrapper_locate_module(ModuleIdentifier); - ResetParams->StdHeader.Func = AMD_INIT_RESET; - if (!module) return AGESA_UNSUPPORTED; - Dispatcher = module->ModuleDispatcher; - return Dispatcher(ResetParams); -} - -/********************************************************************** - * Interface call: AmdInitEarly - **********************************************************************/ -AGESA_STATUS -AmdInitEarly ( - IN OUT AMD_EARLY_PARAMS *EarlyParams - ) -{ - MODULE_ENTRY Dispatcher = NULL; - const AMD_MODULE_HEADER* module = agesawrapper_locate_module(ModuleIdentifier); - EarlyParams->StdHeader.Func = AMD_INIT_EARLY; - if (!module) return AGESA_UNSUPPORTED; - Dispatcher = module->ModuleDispatcher; - return Dispatcher(EarlyParams); -} - -/********************************************************************** - * Interface call: AmdInitPost - **********************************************************************/ -AGESA_STATUS -AmdInitPost ( - IN OUT AMD_POST_PARAMS *PostParams ///< Amd Cpu init param - ) -{ - MODULE_ENTRY Dispatcher = NULL; - const AMD_MODULE_HEADER* module = agesawrapper_locate_module(ModuleIdentifier); - PostParams->StdHeader.Func = AMD_INIT_POST; - if (!module) return AGESA_UNSUPPORTED; - Dispatcher = module->ModuleDispatcher; - return Dispatcher(PostParams); -} - -/********************************************************************** - * Interface call: AmdInitEnv - **********************************************************************/ -AGESA_STATUS -AmdInitEnv ( - IN OUT AMD_ENV_PARAMS *EnvParams - ) -{ - MODULE_ENTRY Dispatcher = NULL; - const AMD_MODULE_HEADER* module = agesawrapper_locate_module(ModuleIdentifier); - EnvParams->StdHeader.Func = AMD_INIT_ENV; - if (!module) return AGESA_UNSUPPORTED; - Dispatcher = module->ModuleDispatcher; - return Dispatcher(EnvParams); -} - -/********************************************************************** - * Interface call: AmdInitMid - **********************************************************************/ -AGESA_STATUS -AmdInitMid ( - IN OUT AMD_MID_PARAMS *MidParams - ) -{ - MODULE_ENTRY Dispatcher = NULL; - const AMD_MODULE_HEADER* module = agesawrapper_locate_module(ModuleIdentifier); - MidParams->StdHeader.Func = AMD_INIT_MID; - if (!module) return AGESA_UNSUPPORTED; - Dispatcher = module->ModuleDispatcher; - return Dispatcher(MidParams); -} - -/********************************************************************** - * Interface call: AmdInitLate - **********************************************************************/ -AGESA_STATUS -AmdInitLate ( - IN OUT AMD_LATE_PARAMS *LateParams - ) -{ - MODULE_ENTRY Dispatcher = NULL; - const AMD_MODULE_HEADER* module = agesawrapper_locate_module(ModuleIdentifier); - LateParams->StdHeader.Func = AMD_INIT_LATE; - if (!module) return AGESA_UNSUPPORTED; - Dispatcher = module->ModuleDispatcher; - return Dispatcher(LateParams); -} - -/********************************************************************** - * Interface call: AmdInitRecovery - **********************************************************************/ -AGESA_STATUS -AmdInitRecovery ( - IN OUT AMD_RECOVERY_PARAMS *RecoveryParams - ) -{ - MODULE_ENTRY Dispatcher = NULL; - const AMD_MODULE_HEADER* module = agesawrapper_locate_module(ModuleIdentifier); - RecoveryParams->StdHeader.Func = AMD_INIT_RECOVERY; - if (!module) return AGESA_UNSUPPORTED; - Dispatcher = module->ModuleDispatcher; - return Dispatcher(RecoveryParams); -} - -/********************************************************************** - * Interface call: AmdInitResume - **********************************************************************/ -AGESA_STATUS -AmdInitResume ( - IN AMD_RESUME_PARAMS *ResumeParams - ) -{ - MODULE_ENTRY Dispatcher = NULL; - const AMD_MODULE_HEADER* module = agesawrapper_locate_module(ModuleIdentifier); - ResumeParams->StdHeader.Func = AMD_INIT_RESUME; - if (!module) return AGESA_UNSUPPORTED; - Dispatcher = module->ModuleDispatcher; - return Dispatcher(ResumeParams); -} - -/********************************************************************** - * Interface call: AmdS3LateRestore - **********************************************************************/ -AGESA_STATUS -AmdS3LateRestore ( - IN OUT AMD_S3LATE_PARAMS *S3LateParams - ) -{ - MODULE_ENTRY Dispatcher = NULL; - const AMD_MODULE_HEADER* module = agesawrapper_locate_module(ModuleIdentifier); - S3LateParams->StdHeader.Func = AMD_S3LATE_RESTORE; - if (!module) return AGESA_UNSUPPORTED; - Dispatcher = module->ModuleDispatcher; - return Dispatcher(S3LateParams); -} - -/********************************************************************** - * Interface call: AmdS3Save - **********************************************************************/ -AGESA_STATUS -AmdS3Save ( - IN OUT AMD_S3SAVE_PARAMS *AmdS3SaveParams - ) -{ - MODULE_ENTRY Dispatcher = NULL; - const AMD_MODULE_HEADER* module = agesawrapper_locate_module(ModuleIdentifier); - AmdS3SaveParams->StdHeader.Func = AMD_S3_SAVE; - if (!module) return AGESA_UNSUPPORTED; - Dispatcher = module->ModuleDispatcher; - return Dispatcher(AmdS3SaveParams); -} - -/********************************************************************** - * Interface call: AmdLateRunApTask - **********************************************************************/ -AGESA_STATUS -AmdLateRunApTask ( - IN AP_EXE_PARAMS *AmdApExeParams -) -{ - MODULE_ENTRY Dispatcher = NULL; - const AMD_MODULE_HEADER* module = agesawrapper_locate_module(ModuleIdentifier); - AmdApExeParams->StdHeader.Func = AMD_LATE_RUN_AP_TASK; - if (!module) return AGESA_UNSUPPORTED; - Dispatcher = module->ModuleDispatcher; - return Dispatcher(AmdApExeParams); -} - -/********************************************************************** - * Interface service call: AmdGetApicId - **********************************************************************/ -AGESA_STATUS -AmdGetApicId ( - IN OUT AMD_APIC_PARAMS *AmdParamApic -) -{ - MODULE_ENTRY Dispatcher = NULL; - const AMD_MODULE_HEADER* module = agesawrapper_locate_module(ModuleIdentifier); - AmdParamApic->StdHeader.Func = AMD_GET_APIC_ID; - if (!module) return AGESA_UNSUPPORTED; - Dispatcher = module->ModuleDispatcher; - return Dispatcher(AmdParamApic); -} - -/********************************************************************** - * Interface service call: AmdGetPciAddress - **********************************************************************/ -AGESA_STATUS -AmdGetPciAddress ( - IN OUT AMD_GET_PCI_PARAMS *AmdParamGetPci -) -{ - MODULE_ENTRY Dispatcher = NULL; - const AMD_MODULE_HEADER* module = agesawrapper_locate_module(ModuleIdentifier); - AmdParamGetPci->StdHeader.Func = AMD_GET_PCI_ADDRESS; - if (!module) return AGESA_UNSUPPORTED; - Dispatcher = module->ModuleDispatcher; - return Dispatcher(AmdParamGetPci); -} - -/********************************************************************** - * Interface service call: AmdIdentifyCore - **********************************************************************/ -AGESA_STATUS -AmdIdentifyCore ( - IN OUT AMD_IDENTIFY_PARAMS *AmdParamIdentify -) -{ - MODULE_ENTRY Dispatcher = NULL; - const AMD_MODULE_HEADER* module = agesawrapper_locate_module(ModuleIdentifier); - AmdParamIdentify->StdHeader.Func = AMD_IDENTIFY_CORE; - if (!module) return AGESA_UNSUPPORTED; - Dispatcher = module->ModuleDispatcher; - return Dispatcher(AmdParamIdentify); -} - -/********************************************************************** - * Interface service call: AmdReadEventLog - **********************************************************************/ -AGESA_STATUS -AmdReadEventLog ( - IN EVENT_PARAMS *Event -) -{ - MODULE_ENTRY Dispatcher = NULL; - const AMD_MODULE_HEADER* module = agesawrapper_locate_module(ModuleIdentifier); - Event->StdHeader.Func = AMD_READ_EVENT_LOG; - if (!module) return AGESA_UNSUPPORTED; - Dispatcher = module->ModuleDispatcher; - return Dispatcher(Event); -} - -/********************************************************************** - * Interface service call: AmdIdentifyDimm - **********************************************************************/ -AGESA_STATUS -AmdIdentifyDimm ( - IN OUT AMD_IDENTIFY_DIMM *AmdDimmIdentify -) -{ - MODULE_ENTRY Dispatcher = NULL; - const AMD_MODULE_HEADER* module = agesawrapper_locate_module(ModuleIdentifier); - AmdDimmIdentify->StdHeader.Func = AMD_IDENTIFY_DIMMS; - if (!module) return AGESA_UNSUPPORTED; - Dispatcher = module->ModuleDispatcher; - return Dispatcher(AmdDimmIdentify); -} - -AGESA_STATUS -AmdIdsRunApTaskLate ( - IN AP_EXE_PARAMS *AmdApExeParams - ) -{ - AmdApExeParams->StdHeader.Func = -1; - return AGESA_UNSUPPORTED; -} - -/********************************************************************** - * Interface service call: AmdGet2DDataEye - **********************************************************************/ -AGESA_STATUS -AmdGet2DDataEye ( - IN OUT AMD_GET_DATAEYE *AmdGetDataEye - ) -{ - MODULE_ENTRY Dispatcher = NULL; - const AMD_MODULE_HEADER* module = agesawrapper_locate_module(ModuleIdentifier); - AmdGetDataEye->StdHeader.Func = AMD_GET_2D_DATA_EYE; - if (!module) return AGESA_UNSUPPORTED; - Dispatcher = module->ModuleDispatcher; - return Dispatcher(AmdGetDataEye); -} - -/********************************************************************** - * FCH Functions - **********************************************************************/ - -VOID FchInitS3LateRestore (IN FCH_DATA_BLOCK *FchDataPtr); -VOID FchInitS3EarlyRestore (IN FCH_DATA_BLOCK *FchDataPtr); - -VOID -FchInitS3EarlyRestore ( - IN FCH_DATA_BLOCK *FchDataPtr - ) -{ - MODULE_ENTRY Dispatcher = NULL; - const AMD_MODULE_HEADER* module = agesawrapper_locate_module(ModuleIdentifier); - FchDataPtr->StdHeader->Func = FCH_INIT_S3_EARLY_RESTORE; - if (!module) return; - Dispatcher = module->ModuleDispatcher; - Dispatcher(FchDataPtr); -} - -VOID -FchInitS3LateRestore ( - IN FCH_DATA_BLOCK *FchDataPtr - ) -{ - MODULE_ENTRY Dispatcher = NULL; - const AMD_MODULE_HEADER* module = agesawrapper_locate_module(ModuleIdentifier); - FchDataPtr->StdHeader->Func = FCH_INIT_S3_LATE_RESTORE; - if (!module) return; - Dispatcher = module->ModuleDispatcher; - Dispatcher(FchDataPtr); -} - -/** - * WaitForEcLDN9MailboxCmdAck - * - * - * @param[in] StdHeader - * - */ -VOID -WaitForEcLDN9MailboxCmdAck ( - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - StdHeader->Func = 0; -} - -/** - * ImcSleep - IMC Sleep. - * - * - * @param[in] FchDataPtr Fch configuration structure pointer. - * - */ -VOID -ImcSleep ( - IN VOID *FchDataPtr - ) -{ - ((FCH_DATA_BLOCK*)FchDataPtr)->StdHeader->Func = 0; -} - -/** - * SoftwareDisableImc - Software disable IMC strap - * - * - * @param[in] FchDataPtr Fch configuration structure pointer. - * - */ -VOID -SoftwareDisableImc ( - IN VOID *FchDataPtr - ) -{ - ((FCH_DATA_BLOCK*)FchDataPtr)->StdHeader->Func = 0; -} - -/** - * ImcEnableSurebootTimer - IMC Enable Sureboot Timer. - * - * - * @param[in] FchDataPtr Fch configuration structure pointer. - * - */ -VOID -ImcEnableSurebootTimer ( - IN VOID *FchDataPtr - ) -{ - ((FCH_DATA_BLOCK*)FchDataPtr)->StdHeader->Func = 0; -} - -/** - * ImcDisableSurebootTimer - IMC Disable Sureboot Timer. - * - * - * @param[in] FchDataPtr Fch configuration structure pointer. - * - */ -VOID -ImcDisableSurebootTimer ( - IN VOID *FchDataPtr - ) -{ - ((FCH_DATA_BLOCK*)FchDataPtr)->StdHeader->Func = 0; -} - -/** - * ImcWakeup - IMC Wakeup. - * - * - * @param[in] FchDataPtr Fch configuration structure pointer. - * - */ -VOID -ImcWakeup ( - IN VOID *FchDataPtr - ) -{ - ((FCH_DATA_BLOCK*)FchDataPtr)->StdHeader->Func = 0; -} - -/** - * ImcIdle - IMC Idle. - * - * - * @param[in] FchDataPtr Fch configuration structure pointer. - * - */ -VOID -ImcIdle ( - IN VOID *FchDataPtr - ) -{ - ((FCH_DATA_BLOCK*)FchDataPtr)->StdHeader->Func = 0; -} diff --git a/src/vendorcode/amd/pi/Makefile.inc b/src/vendorcode/amd/pi/Makefile.inc index 90714aa286..9b3a0e6b12 100644 --- a/src/vendorcode/amd/pi/Makefile.inc +++ b/src/vendorcode/amd/pi/Makefile.inc @@ -110,10 +110,6 @@ endef agesa_raw_files += $(wildcard $(src)/vendorcode/amd/pi/Lib/*.[cS]) -ifeq ($(CONFIG_BINARYPI_LEGACY_WRAPPER),y) -agesa_raw_files += $(wildcard $(AGESA_ROOT)/binaryPI/*.[cS]) -endif - ifeq ($(CONFIG_CPU_AMD_PI_00660F01),y) agesa_raw_files += $(wildcard $(AGESA_ROOT)/Proc/Fch/Kern/KernImc/*.[cS]) agesa_raw_files += $(wildcard $(AGESA_ROOT)/Proc/Fch/Common/*.[cS]) From 56397364c9178cae527520a5fffb9eab2f6cc35b Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ky=C3=B6sti=20M=C3=A4lkki?= Date: Thu, 7 Sep 2017 22:13:10 +0300 Subject: [PATCH 0388/1242] binaryPI: Drop CAR teardown without POSTCAR_STAGE MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The remaining (active) binaryPI boards moved away from BINARYPI_LEGACY_WRAPPER and have POSTCAR_STAGE now. As the cache_as_ram.S is also used with AGESA, this slightly reduces the codesize there for romstage and postcar as well. This commit is actually a revert for the vendorcode parts, AMD originally shipped the codes using 'invd' for the CAR teardown, but these were changed for coreboot due the convoluted teardown that used to happen with non-empty stack. Change-Id: I693c104c3aab3be537c00695cbd764a48bd603b0 Signed-off-by: Kyösti Mälkki Reviewed-on: https://review.coreboot.org/c/coreboot/+/18526 Tested-by: build bot (Jenkins) --- src/drivers/amd/agesa/Makefile.inc | 2 +- src/drivers/amd/agesa/cache_as_ram.S | 58 +------------------ src/drivers/amd/agesa/exit_car.S | 37 ++++++++++++ .../amd/pi/00630F01/binaryPI/gcccar.inc | 29 +--------- .../amd/pi/00660F01/binaryPI/gcccar.inc | 29 +--------- .../amd/pi/00730F01/binaryPI/gcccar.inc | 29 +--------- 6 files changed, 45 insertions(+), 139 deletions(-) create mode 100644 src/drivers/amd/agesa/exit_car.S diff --git a/src/drivers/amd/agesa/Makefile.inc b/src/drivers/amd/agesa/Makefile.inc index fb46d91991..dfb385da80 100644 --- a/src/drivers/amd/agesa/Makefile.inc +++ b/src/drivers/amd/agesa/Makefile.inc @@ -20,7 +20,7 @@ romstage-y += state_machine.c ramstage-y += state_machine.c cpu_incs-y += $(src)/drivers/amd/agesa/cache_as_ram.S -postcar-y += cache_as_ram.S +postcar-y += exit_car.S romstage-y += def_callouts.c romstage-y += eventlog.c diff --git a/src/drivers/amd/agesa/cache_as_ram.S b/src/drivers/amd/agesa/cache_as_ram.S index dcb0c43d8e..3f1358a2f8 100644 --- a/src/drivers/amd/agesa/cache_as_ram.S +++ b/src/drivers/amd/agesa/cache_as_ram.S @@ -27,7 +27,6 @@ .code32 .globl _cache_as_ram_setup, _cache_as_ram_setup_end -.globl chipset_teardown_car _cache_as_ram_setup: @@ -105,66 +104,11 @@ _cache_as_ram_setup: pushl %eax call romstage_main -#if CONFIG(POSTCAR_STAGE) - -/* We do not return. Execution continues with run_postcar_phase() - * calling to chipset_teardown_car below. - */ - jmp postcar_entry_failure - -chipset_teardown_car: - -/* - * Retrieve return address from stack as it will get trashed below if - * execution is utilizing the cache-as-ram stack. - */ - pop %esp - -#else - - movl %eax, %esp - -/* Register %esp is new stacktop for remaining of romstage. */ - -#endif - - /* Disable cache */ - movl %cr0, %eax - orl $CR0_CacheDisable, %eax - movl %eax, %cr0 - -/* Register %esp is preserved in AMD_DISABLE_STACK. */ - AMD_DISABLE_STACK - -#if CONFIG(POSTCAR_STAGE) - - jmp *%esp - -#else - - /* enable cache */ - movl %cr0, %eax - andl $0x9fffffff, %eax - movl %eax, %cr0 - - call romstage_after_car - -#endif - /* Should never see this postcode */ - post_code(0xaf) + post_code(0xae) stop: hlt jmp stop -/* These are here for linking purposes. */ -.weak early_all_cores, romstage_main -early_all_cores: -romstage_main: -postcar_entry_failure: - /* Should never see this postcode */ - post_code(0xae) - jmp stop - _cache_as_ram_setup_end: diff --git a/src/drivers/amd/agesa/exit_car.S b/src/drivers/amd/agesa/exit_car.S new file mode 100644 index 0000000000..f9d056e599 --- /dev/null +++ b/src/drivers/amd/agesa/exit_car.S @@ -0,0 +1,37 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include + +.code32 +.globl chipset_teardown_car + +chipset_teardown_car: + pop %esp + + /* Disable cache */ + movl %cr0, %eax + orl $CR0_CacheDisable, %eax + movl %eax, %cr0 + + AMD_DISABLE_STACK + + /* enable cache */ + movl %cr0, %eax + andl $(~(CR0_CD | CR0_NW)), %eax + movl %eax, %cr0 + + jmp *%esp diff --git a/src/vendorcode/amd/pi/00630F01/binaryPI/gcccar.inc b/src/vendorcode/amd/pi/00630F01/binaryPI/gcccar.inc index 75ba9e7df5..4d903e686f 100644 --- a/src/vendorcode/amd/pi/00630F01/binaryPI/gcccar.inc +++ b/src/vendorcode/amd/pi/00630F01/binaryPI/gcccar.inc @@ -696,13 +696,6 @@ fam15_enable_stack_hook_exit: * Return any family specific controls to their 'standard' * settings for using cache with main memory. * -* Note: Customized for coreboot: -* A wbinvd is used to send cache to memory. The existing stack is preserved -* at its original location and additional information is preserved (e.g. -* coreboot CAR globals, heap structures, etc.). This implementation should -* NOT be used with S3 resume IF the stack/cache area is not reserved and -* over system memory. -* * Inputs: * ESI - [31:24] flags; [15,8]= Node#; [7,0]= core# * Outputs: @@ -911,16 +904,7 @@ fam15_disable_stack_remote_read_exit: btr $INVD_WBINVD, %eax # Disable INVD -> WBINVD conversion _WRMSR - #-------------------------------------------------------------------------- - # Send cache to memory. Preserve stack and coreboot CAR globals. - # This shouldn't be used with S3 resume IF the stack/cache area is - # not reserved and over system memory. - #-------------------------------------------------------------------------- -#if !CONFIG(POSTCAR_STAGE) - wbinvd -#else invd -#endif #.if (bh == 01h) || (bh == 03h) ; Is this TN or KV? cmp $01, %bh @@ -1563,17 +1547,8 @@ ClearTheStack: # Stack base is in SS, stack pointer is .endm /***************************************************************************** -* AMD_DISABLE_STACK: Implementation is modified for coreboot from -* the original AMD intent. A WBINVD is used in the HOOK -* to send dirty cache contents to DRAM backing before -* disabling cache-as-ram. This is not safe for S3 resume. -* -* todo: -* * rework PI/AGESA source to set DRAM to UC to send -* writes directly to memory -* * move DCACHE_BASE or use postcar stage for teardown -* to eliminate car_migrated problem that will occur -* after wbinvd is changed back to invd +* AMD_DISABLE_STACK: Destroy the stack inside the cache. This routine +* should only be executed on the BSP * * In: * none diff --git a/src/vendorcode/amd/pi/00660F01/binaryPI/gcccar.inc b/src/vendorcode/amd/pi/00660F01/binaryPI/gcccar.inc index 8f3ca83598..b208cc14ca 100644 --- a/src/vendorcode/amd/pi/00660F01/binaryPI/gcccar.inc +++ b/src/vendorcode/amd/pi/00660F01/binaryPI/gcccar.inc @@ -401,13 +401,6 @@ fam15_enable_stack_hook_exit: * Return any family specific controls to their 'standard' * settings for using cache with main memory. * -* Note: Customized for coreboot: -* A wbinvd is used to send cache to memory. The existing stack is preserved -* at its original location and additional information is preserved (e.g. -* coreboot CAR globals, heap structures, etc.). This implementation should -* NOT be used with S3 resume IF the stack/cache area is not reserved and -* over system memory. -* * Inputs: * ESI - [31:24] flags; [15,8]= Node#; [7,0]= core# * Outputs: @@ -646,16 +639,7 @@ fam15_disable_stack_remote_read_exit: btr $INVD_WBINVD, %eax # Disable INVD -> WBINVD conversion _WRMSR - #-------------------------------------------------------------------------- - # Send cache to memory. Preserve stack and coreboot CAR globals. - # This shouldn't be used with S3 resume IF the stack/cache area is - # not reserved and over system memory. - #-------------------------------------------------------------------------- -#if !CONFIG(POSTCAR_STAGE) - wbinvd -#else invd -#endif # #.if (bh == 01h) || (bh == 03h) ; Is this TN or KM? # cmp $01, %bh @@ -1302,17 +1286,8 @@ ClearTheStack: # Stack base is in SS, stack pointer is .endm /***************************************************************************** -* AMD_DISABLE_STACK: Implementation is modified for coreboot from -* the original AMD intent. A WBINVD is used in the HOOK -* to send dirty cache contents to DRAM backing before -* disabling cache-as-ram. This is not safe for S3 resume. -* -* todo: -* * rework PI/AGESA source to set DRAM to UC to send -* writes directly to memory -* * move DCACHE_BASE or use postcar stage for teardown -* to eliminate car_migrated problem that will occur -* after wbinvd is changed back to invd +* AMD_DISABLE_STACK: Destroy the stack inside the cache. This routine +* should only be executed on the BSP * * In: * none diff --git a/src/vendorcode/amd/pi/00730F01/binaryPI/gcccar.inc b/src/vendorcode/amd/pi/00730F01/binaryPI/gcccar.inc index 357b8be6d5..7d86a31c69 100644 --- a/src/vendorcode/amd/pi/00730F01/binaryPI/gcccar.inc +++ b/src/vendorcode/amd/pi/00730F01/binaryPI/gcccar.inc @@ -383,13 +383,6 @@ fam16_enable_stack_hook_exit: ; Return any family specific controls to their 'standard' ; settings for using cache with main memory. ; -; Note: Customized for coreboot: -; A wbinvd is used to send cache to memory. The existing stack is preserved -; at its original location and additional information is preserved (e.g. -; coreboot CAR globals, heap structures, etc.). This implementation should -; NOT be used with S3 resume IF the stack/cache area is not reserved and -; over system memory. -; ; Inputs: ; ESI - [31:24] flags; [15:8]= Node#; [7:0]= core# ; Outputs: @@ -610,16 +603,7 @@ fam16_disable_stack_remote_read_exit: btr $INVD_WBINVD, %eax # Disable INVD -> WBINVD conversion _WRMSR - #-------------------------------------------------------------------------- - # Send cache to memory. Preserve stack and coreboot CAR globals. - # This shouldn't be used with S3 resume IF the stack/cache area is - # not reserved and over system memory. - #-------------------------------------------------------------------------- -#if !CONFIG(POSTCAR_STAGE) - wbinvd -#else invd -#endif #Do Standard Family 16 work mov $HWCR, %ecx # MSR:C001_0015h @@ -1276,17 +1260,8 @@ ClearTheStack: # Stack base is in SS, stack pointer is .endm /***************************************************************************** -* AMD_DISABLE_STACK: Implementation is modified for coreboot from -* the original AMD intent. A WBINVD is used in the HOOK -* to send dirty cache contents to DRAM backing before -* disabling cache-as-ram. This is not safe for S3 resume. -* -* todo: -* * rework PI/AGESA source to set DRAM to UC to send -* writes directly to memory -* * move DCACHE_BASE or use postcar stage for teardown -* to eliminate car_migrated problem that will occur -* after wbinvd is changed back to invd +* AMD_DISABLE_STACK: Destroy the stack inside the cache. This routine +* should only be executed on the BSP * * In: * none From 9266ce90c6cf6962f612b59a173149eca4e1538f Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ky=C3=B6sti=20M=C3=A4lkki?= Date: Mon, 25 Nov 2019 18:21:05 +0200 Subject: [PATCH 0389/1242] AGESA,binaryPI: Remove early_all_cores() MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This was implemented to make sure it gets called before attempting any PCI MMIO access. Now that we have one central romstage_main() implementation this extra precaution is no longer useful. Change-Id: I09b24da827e00d7a9ba0a51d5eef36f174b893a6 Signed-off-by: Kyösti Mälkki Reviewed-on: https://review.coreboot.org/c/coreboot/+/37203 Tested-by: build bot (Jenkins) Reviewed-by: Arthur Heymans Reviewed-by: Michał Żygowski --- src/drivers/amd/agesa/cache_as_ram.S | 2 -- src/drivers/amd/agesa/romstage.c | 12 +++--------- src/include/cpu/amd/car.h | 2 -- 3 files changed, 3 insertions(+), 13 deletions(-) diff --git a/src/drivers/amd/agesa/cache_as_ram.S b/src/drivers/amd/agesa/cache_as_ram.S index 3f1358a2f8..e3e5735c3b 100644 --- a/src/drivers/amd/agesa/cache_as_ram.S +++ b/src/drivers/amd/agesa/cache_as_ram.S @@ -94,8 +94,6 @@ _cache_as_ram_setup: #endif - call early_all_cores - /* Must maintain 16-byte stack alignment here. */ pushl $0x0 pushl $0x0 diff --git a/src/drivers/amd/agesa/romstage.c b/src/drivers/amd/agesa/romstage.c index 72aac3eedd..0ecfeb2bb6 100644 --- a/src/drivers/amd/agesa/romstage.c +++ b/src/drivers/amd/agesa/romstage.c @@ -27,15 +27,6 @@ #include #include -#if !CONFIG(POSTCAR_STAGE) -#error "Only POSTCAR_STAGE is supported." -#endif - -void asmlinkage early_all_cores(void) -{ - amd_initmmio(); -} - void __weak platform_once(struct sysinfo *cb) { board_BeforeAgesa(cb); @@ -57,6 +48,9 @@ void *asmlinkage romstage_main(unsigned long bist) u8 initial_apic_id = (u8) (cpuid_ebx(1) >> 24); int cbmem_initted = 0; + /* Enable PCI MMIO configuration. */ + amd_initmmio(); + fill_sysinfo(cb); if ((initial_apic_id == 0) && boot_cpu()) { diff --git a/src/include/cpu/amd/car.h b/src/include/cpu/amd/car.h index 59f5bb91aa..46f7e1d5c9 100644 --- a/src/include/cpu/amd/car.h +++ b/src/include/cpu/amd/car.h @@ -5,8 +5,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx); -void asmlinkage early_all_cores(void); - void *asmlinkage romstage_main(unsigned long bist); #endif From 18ecdbfeb8992507ac170c6257be62cccbbe5899 Mon Sep 17 00:00:00 2001 From: Elyes HAOUAS Date: Mon, 14 Oct 2019 10:16:29 +0200 Subject: [PATCH 0390/1242] crossgcc: Update binutils to version 2.33.1 Change-Id: I3bb6055383aa72153fffc70adc9cc446e5a0612e Signed-off-by: Elyes HAOUAS Reviewed-on: https://review.coreboot.org/c/coreboot/+/36013 Reviewed-by: Patrick Georgi Tested-by: build bot (Jenkins) --- util/crossgcc/buildgcc | 2 +- ...inutils-2.32_as-ipxe.patch => binutils-2.33.1_as-ipxe.patch} | 0 ...ils-2.32_mips-gold.patch => binutils-2.33.1_mips-gold.patch} | 0 ...s-2.32_no-bfd-doc.patch => binutils-2.33.1_no-bfd-doc.patch} | 0 util/crossgcc/sum/binutils-2.32.tar.xz.cksum | 1 - util/crossgcc/sum/binutils-2.33.1.tar.xz.cksum | 1 + 6 files changed, 2 insertions(+), 2 deletions(-) rename util/crossgcc/patches/{binutils-2.32_as-ipxe.patch => binutils-2.33.1_as-ipxe.patch} (100%) rename util/crossgcc/patches/{binutils-2.32_mips-gold.patch => binutils-2.33.1_mips-gold.patch} (100%) rename util/crossgcc/patches/{binutils-2.32_no-bfd-doc.patch => binutils-2.33.1_no-bfd-doc.patch} (100%) delete mode 100644 util/crossgcc/sum/binutils-2.32.tar.xz.cksum create mode 100644 util/crossgcc/sum/binutils-2.33.1.tar.xz.cksum diff --git a/util/crossgcc/buildgcc b/util/crossgcc/buildgcc index 0ce8f20851..b5a0845995 100755 --- a/util/crossgcc/buildgcc +++ b/util/crossgcc/buildgcc @@ -52,7 +52,7 @@ MPFR_VERSION=4.0.2 MPC_VERSION=1.1.0 GCC_VERSION=8.3.0 GCC_AUTOCONF_VERSION=2.69 -BINUTILS_VERSION=2.32 +BINUTILS_VERSION=2.33.1 GDB_VERSION=8.3 IASL_VERSION=20190703 PYTHON_VERSION=3.7.4 diff --git a/util/crossgcc/patches/binutils-2.32_as-ipxe.patch b/util/crossgcc/patches/binutils-2.33.1_as-ipxe.patch similarity index 100% rename from util/crossgcc/patches/binutils-2.32_as-ipxe.patch rename to util/crossgcc/patches/binutils-2.33.1_as-ipxe.patch diff --git a/util/crossgcc/patches/binutils-2.32_mips-gold.patch b/util/crossgcc/patches/binutils-2.33.1_mips-gold.patch similarity index 100% rename from util/crossgcc/patches/binutils-2.32_mips-gold.patch rename to util/crossgcc/patches/binutils-2.33.1_mips-gold.patch diff --git a/util/crossgcc/patches/binutils-2.32_no-bfd-doc.patch b/util/crossgcc/patches/binutils-2.33.1_no-bfd-doc.patch similarity index 100% rename from util/crossgcc/patches/binutils-2.32_no-bfd-doc.patch rename to util/crossgcc/patches/binutils-2.33.1_no-bfd-doc.patch diff --git a/util/crossgcc/sum/binutils-2.32.tar.xz.cksum b/util/crossgcc/sum/binutils-2.32.tar.xz.cksum deleted file mode 100644 index bdb84aaa75..0000000000 --- a/util/crossgcc/sum/binutils-2.32.tar.xz.cksum +++ /dev/null @@ -1 +0,0 @@ -cd45a512af1c8a508976c1beb4f5825b3bb89f4d tarballs/binutils-2.32.tar.xz diff --git a/util/crossgcc/sum/binutils-2.33.1.tar.xz.cksum b/util/crossgcc/sum/binutils-2.33.1.tar.xz.cksum new file mode 100644 index 0000000000..3a2f076400 --- /dev/null +++ b/util/crossgcc/sum/binutils-2.33.1.tar.xz.cksum @@ -0,0 +1 @@ +06598868f5fa8efc98427dcb790d42c664f1a1a4 tarballs/binutils-2.33.1.tar.xz From 2368681c83e1c0de4df07c5ea9d881e5b284406d Mon Sep 17 00:00:00 2001 From: Elyes HAOUAS Date: Sat, 21 Sep 2019 12:23:16 +0200 Subject: [PATCH 0391/1242] crossgcc: Upgrade GDB to version 8.3.1 Change-Id: I380ba8678b22483b0d9c5fc558c0e08fd38778e7 Signed-off-by: Elyes HAOUAS Reviewed-on: https://review.coreboot.org/c/coreboot/+/35513 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi --- util/crossgcc/buildgcc | 2 +- .../patches/{gdb-8.3_amd64.patch => gdb-8.3.1_amd64.patch} | 0 .../patches/{gdb-8.3_no-doc.patch => gdb-8.3.1_no-doc.patch} | 0 .../{gdb-8.3_pythonhome.patch => gdb-8.3.1_pythonhome.patch} | 0 util/crossgcc/sum/gdb-8.3.1.tar.xz.cksum | 1 + util/crossgcc/sum/gdb-8.3.tar.xz.cksum | 1 - 6 files changed, 2 insertions(+), 2 deletions(-) rename util/crossgcc/patches/{gdb-8.3_amd64.patch => gdb-8.3.1_amd64.patch} (100%) rename util/crossgcc/patches/{gdb-8.3_no-doc.patch => gdb-8.3.1_no-doc.patch} (100%) rename util/crossgcc/patches/{gdb-8.3_pythonhome.patch => gdb-8.3.1_pythonhome.patch} (100%) create mode 100644 util/crossgcc/sum/gdb-8.3.1.tar.xz.cksum delete mode 100644 util/crossgcc/sum/gdb-8.3.tar.xz.cksum diff --git a/util/crossgcc/buildgcc b/util/crossgcc/buildgcc index b5a0845995..89f0a4c924 100755 --- a/util/crossgcc/buildgcc +++ b/util/crossgcc/buildgcc @@ -53,7 +53,7 @@ MPC_VERSION=1.1.0 GCC_VERSION=8.3.0 GCC_AUTOCONF_VERSION=2.69 BINUTILS_VERSION=2.33.1 -GDB_VERSION=8.3 +GDB_VERSION=8.3.1 IASL_VERSION=20190703 PYTHON_VERSION=3.7.4 EXPAT_VERSION=2.2.7 diff --git a/util/crossgcc/patches/gdb-8.3_amd64.patch b/util/crossgcc/patches/gdb-8.3.1_amd64.patch similarity index 100% rename from util/crossgcc/patches/gdb-8.3_amd64.patch rename to util/crossgcc/patches/gdb-8.3.1_amd64.patch diff --git a/util/crossgcc/patches/gdb-8.3_no-doc.patch b/util/crossgcc/patches/gdb-8.3.1_no-doc.patch similarity index 100% rename from util/crossgcc/patches/gdb-8.3_no-doc.patch rename to util/crossgcc/patches/gdb-8.3.1_no-doc.patch diff --git a/util/crossgcc/patches/gdb-8.3_pythonhome.patch b/util/crossgcc/patches/gdb-8.3.1_pythonhome.patch similarity index 100% rename from util/crossgcc/patches/gdb-8.3_pythonhome.patch rename to util/crossgcc/patches/gdb-8.3.1_pythonhome.patch diff --git a/util/crossgcc/sum/gdb-8.3.1.tar.xz.cksum b/util/crossgcc/sum/gdb-8.3.1.tar.xz.cksum new file mode 100644 index 0000000000..c36285846f --- /dev/null +++ b/util/crossgcc/sum/gdb-8.3.1.tar.xz.cksum @@ -0,0 +1 @@ +d403ba208945bbf04f8130ea4853730cdf0c8fc7 tarballs/gdb-8.3.1.tar.xz diff --git a/util/crossgcc/sum/gdb-8.3.tar.xz.cksum b/util/crossgcc/sum/gdb-8.3.tar.xz.cksum deleted file mode 100644 index bc82f51e37..0000000000 --- a/util/crossgcc/sum/gdb-8.3.tar.xz.cksum +++ /dev/null @@ -1 +0,0 @@ -f45de6af561f0fa0241f0d5085198556fcfd1e5e tarballs/gdb-8.3.tar.xz From 33847db3ce43d3af90bc778a14fc2bc38183f8b8 Mon Sep 17 00:00:00 2001 From: Elyes HAOUAS Date: Tue, 15 Oct 2019 16:17:26 +0200 Subject: [PATCH 0392/1242] crossgcc: Upgrade Python to version 3.8.0 Change-Id: I1265e7df4d6c04aa1ccf0c65dc87e62bec5a4a35 Signed-off-by: Elyes HAOUAS Reviewed-on: https://review.coreboot.org/c/coreboot/+/36066 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi --- util/crossgcc/buildgcc | 2 +- util/crossgcc/sum/Python-3.7.4.tar.xz.cksum | 1 - util/crossgcc/sum/Python-3.8.0.tar.xz.cksum | 1 + 3 files changed, 2 insertions(+), 2 deletions(-) delete mode 100644 util/crossgcc/sum/Python-3.7.4.tar.xz.cksum create mode 100644 util/crossgcc/sum/Python-3.8.0.tar.xz.cksum diff --git a/util/crossgcc/buildgcc b/util/crossgcc/buildgcc index 89f0a4c924..808a52fe5d 100755 --- a/util/crossgcc/buildgcc +++ b/util/crossgcc/buildgcc @@ -55,7 +55,7 @@ GCC_AUTOCONF_VERSION=2.69 BINUTILS_VERSION=2.33.1 GDB_VERSION=8.3.1 IASL_VERSION=20190703 -PYTHON_VERSION=3.7.4 +PYTHON_VERSION=3.8.0 EXPAT_VERSION=2.2.7 # CLANG version number CLANG_VERSION=8.0.0 diff --git a/util/crossgcc/sum/Python-3.7.4.tar.xz.cksum b/util/crossgcc/sum/Python-3.7.4.tar.xz.cksum deleted file mode 100644 index bc792af12b..0000000000 --- a/util/crossgcc/sum/Python-3.7.4.tar.xz.cksum +++ /dev/null @@ -1 +0,0 @@ -a862c5a58626fdad02d2047a57771ede2783fcef tarballs/Python-3.7.4.tar.xz diff --git a/util/crossgcc/sum/Python-3.8.0.tar.xz.cksum b/util/crossgcc/sum/Python-3.8.0.tar.xz.cksum new file mode 100644 index 0000000000..d4566f82c1 --- /dev/null +++ b/util/crossgcc/sum/Python-3.8.0.tar.xz.cksum @@ -0,0 +1 @@ +7720e0384558c598107cf046c48165fd7e1f5b2c tarballs/Python-3.8.0.tar.xz From a2fbddfabc447189e03793196b2ef80f4bde273a Mon Sep 17 00:00:00 2001 From: Elyes HAOUAS Date: Thu, 3 Oct 2019 10:38:39 +0200 Subject: [PATCH 0393/1242] crossgcc: Upgrade Expat to version 2.2.9 Changes: https://github.com/libexpat/libexpat/blob/R_2_2_9/expat/Changes Change-Id: I591e4ed186bc8d46ff64161eddc488b640cad5fc Signed-off-by: Elyes HAOUAS Reviewed-on: https://review.coreboot.org/c/coreboot/+/35432 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi --- util/crossgcc/buildgcc | 2 +- util/crossgcc/sum/expat-2.2.7.tar.bz2.cksum | 1 - util/crossgcc/sum/expat-2.2.9.tar.bz2.cksum | 1 + 3 files changed, 2 insertions(+), 2 deletions(-) delete mode 100644 util/crossgcc/sum/expat-2.2.7.tar.bz2.cksum create mode 100644 util/crossgcc/sum/expat-2.2.9.tar.bz2.cksum diff --git a/util/crossgcc/buildgcc b/util/crossgcc/buildgcc index 808a52fe5d..806b6c0d3d 100755 --- a/util/crossgcc/buildgcc +++ b/util/crossgcc/buildgcc @@ -56,7 +56,7 @@ BINUTILS_VERSION=2.33.1 GDB_VERSION=8.3.1 IASL_VERSION=20190703 PYTHON_VERSION=3.8.0 -EXPAT_VERSION=2.2.7 +EXPAT_VERSION=2.2.9 # CLANG version number CLANG_VERSION=8.0.0 MAKE_VERSION=4.2.1 diff --git a/util/crossgcc/sum/expat-2.2.7.tar.bz2.cksum b/util/crossgcc/sum/expat-2.2.7.tar.bz2.cksum deleted file mode 100644 index 77f627233b..0000000000 --- a/util/crossgcc/sum/expat-2.2.7.tar.bz2.cksum +++ /dev/null @@ -1 +0,0 @@ -9c8a268211e3f1ae31c4d550e5be7708973ec6a6 tarballs/expat-2.2.7.tar.bz2 diff --git a/util/crossgcc/sum/expat-2.2.9.tar.bz2.cksum b/util/crossgcc/sum/expat-2.2.9.tar.bz2.cksum new file mode 100644 index 0000000000..924b412ec1 --- /dev/null +++ b/util/crossgcc/sum/expat-2.2.9.tar.bz2.cksum @@ -0,0 +1 @@ +ef5c1c55913a6ab18496ee99166f86269c7cdc31 tarballs/expat-2.2.9.tar.bz2 From 18315db8e083183cbbd3a4b250d598afdac9a4b5 Mon Sep 17 00:00:00 2001 From: Elyes HAOUAS Date: Tue, 26 Nov 2019 19:12:21 +0100 Subject: [PATCH 0394/1242] crossgcc: Upgrade CMake to 3.16.0 Change-Id: Ib564217c4fdcb609fd6dfd4cb71288dd54ffe4bf Signed-off-by: Elyes HAOUAS Reviewed-on: https://review.coreboot.org/c/coreboot/+/35774 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi --- util/crossgcc/buildgcc | 4 ++-- util/crossgcc/sum/cmake-3.15.3.tar.gz.cksum | 1 - util/crossgcc/sum/cmake-3.16.0.tar.gz.cksum | 1 + 3 files changed, 3 insertions(+), 3 deletions(-) delete mode 100644 util/crossgcc/sum/cmake-3.15.3.tar.gz.cksum create mode 100644 util/crossgcc/sum/cmake-3.16.0.tar.gz.cksum diff --git a/util/crossgcc/buildgcc b/util/crossgcc/buildgcc index 806b6c0d3d..b78637ad28 100755 --- a/util/crossgcc/buildgcc +++ b/util/crossgcc/buildgcc @@ -60,7 +60,7 @@ EXPAT_VERSION=2.2.9 # CLANG version number CLANG_VERSION=8.0.0 MAKE_VERSION=4.2.1 -CMAKE_VERSION=3.15.3 +CMAKE_VERSION=3.16.0 NASM_VERSION=2.14.02 # GCC toolchain archive locations @@ -82,7 +82,7 @@ CFE_ARCHIVE="https://releases.llvm.org/${CLANG_VERSION}/cfe-${CLANG_VERSION}.src CRT_ARCHIVE="https://releases.llvm.org/${CLANG_VERSION}/compiler-rt-${CLANG_VERSION}.src.tar.xz" CTE_ARCHIVE="https://releases.llvm.org/${CLANG_VERSION}/clang-tools-extra-${CLANG_VERSION}.src.tar.xz" MAKE_ARCHIVE="https://ftpmirror.gnu.org/make/make-${MAKE_VERSION}.tar.bz2" -CMAKE_ARCHIVE="https://cmake.org/files/v3.15/cmake-${CMAKE_VERSION}.tar.gz" +CMAKE_ARCHIVE="https://cmake.org/files/v3.16/cmake-${CMAKE_VERSION}.tar.gz" NASM_ARCHIVE="https://www.nasm.us/pub/nasm/releasebuilds/${NASM_VERSION}/nasm-${NASM_VERSION}.tar.bz2" ALL_ARCHIVES="$GMP_ARCHIVE $MPFR_ARCHIVE $MPC_ARCHIVE \ diff --git a/util/crossgcc/sum/cmake-3.15.3.tar.gz.cksum b/util/crossgcc/sum/cmake-3.15.3.tar.gz.cksum deleted file mode 100644 index c4676767e6..0000000000 --- a/util/crossgcc/sum/cmake-3.15.3.tar.gz.cksum +++ /dev/null @@ -1 +0,0 @@ -f467388ba336ea3652f5800918a72cfcc4f7f403 tarballs/cmake-3.15.3.tar.gz diff --git a/util/crossgcc/sum/cmake-3.16.0.tar.gz.cksum b/util/crossgcc/sum/cmake-3.16.0.tar.gz.cksum new file mode 100644 index 0000000000..0adcc1af7e --- /dev/null +++ b/util/crossgcc/sum/cmake-3.16.0.tar.gz.cksum @@ -0,0 +1 @@ +9943ebbbf076bbe1b54c7dadcd6df28ad0d241ed tarballs/cmake-3.16.0.tar.gz From 3ba84c5950c84b2ab11bfa063e25db7960a7cbd1 Mon Sep 17 00:00:00 2001 From: Elyes HAOUAS Date: Fri, 20 Sep 2019 09:01:53 +0200 Subject: [PATCH 0395/1242] crossgcc: Upgrade LLVM to version 9.0.0 Change-Id: I35e6a5210340b8057db6d1cff597428fa8dd3cd1 Signed-off-by: Elyes HAOUAS Reviewed-on: https://review.coreboot.org/c/coreboot/+/34527 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi --- util/crossgcc/buildgcc | 2 +- util/crossgcc/sum/cfe-8.0.0.src.tar.xz.cksum | 1 - util/crossgcc/sum/cfe-9.0.0.src.tar.xz.cksum | 1 + util/crossgcc/sum/clang-tools-extra-8.0.0.src.tar.xz.cksum | 1 - util/crossgcc/sum/clang-tools-extra-9.0.0.src.tar.xz.cksum | 1 + util/crossgcc/sum/compiler-rt-8.0.0.src.tar.xz.cksum | 1 - util/crossgcc/sum/compiler-rt-9.0.0.src.tar.xz.cksum | 1 + util/crossgcc/sum/llvm-8.0.0.src.tar.xz.cksum | 1 - util/crossgcc/sum/llvm-9.0.0.src.tar.xz.cksum | 1 + 9 files changed, 5 insertions(+), 5 deletions(-) delete mode 100644 util/crossgcc/sum/cfe-8.0.0.src.tar.xz.cksum create mode 100644 util/crossgcc/sum/cfe-9.0.0.src.tar.xz.cksum delete mode 100644 util/crossgcc/sum/clang-tools-extra-8.0.0.src.tar.xz.cksum create mode 100644 util/crossgcc/sum/clang-tools-extra-9.0.0.src.tar.xz.cksum delete mode 100644 util/crossgcc/sum/compiler-rt-8.0.0.src.tar.xz.cksum create mode 100644 util/crossgcc/sum/compiler-rt-9.0.0.src.tar.xz.cksum delete mode 100644 util/crossgcc/sum/llvm-8.0.0.src.tar.xz.cksum create mode 100644 util/crossgcc/sum/llvm-9.0.0.src.tar.xz.cksum diff --git a/util/crossgcc/buildgcc b/util/crossgcc/buildgcc index b78637ad28..5dac074a06 100755 --- a/util/crossgcc/buildgcc +++ b/util/crossgcc/buildgcc @@ -58,7 +58,7 @@ IASL_VERSION=20190703 PYTHON_VERSION=3.8.0 EXPAT_VERSION=2.2.9 # CLANG version number -CLANG_VERSION=8.0.0 +CLANG_VERSION=9.0.0 MAKE_VERSION=4.2.1 CMAKE_VERSION=3.16.0 NASM_VERSION=2.14.02 diff --git a/util/crossgcc/sum/cfe-8.0.0.src.tar.xz.cksum b/util/crossgcc/sum/cfe-8.0.0.src.tar.xz.cksum deleted file mode 100644 index 45225c1ce8..0000000000 --- a/util/crossgcc/sum/cfe-8.0.0.src.tar.xz.cksum +++ /dev/null @@ -1 +0,0 @@ -3cb1e10af3955174a3ca5e560f674f24fac2a02f tarballs/cfe-8.0.0.src.tar.xz diff --git a/util/crossgcc/sum/cfe-9.0.0.src.tar.xz.cksum b/util/crossgcc/sum/cfe-9.0.0.src.tar.xz.cksum new file mode 100644 index 0000000000..e39bea12bb --- /dev/null +++ b/util/crossgcc/sum/cfe-9.0.0.src.tar.xz.cksum @@ -0,0 +1 @@ +6977cf7a802a053c57fa74138d3648b563e71e88 tarballs/cfe-9.0.0.src.tar.xz diff --git a/util/crossgcc/sum/clang-tools-extra-8.0.0.src.tar.xz.cksum b/util/crossgcc/sum/clang-tools-extra-8.0.0.src.tar.xz.cksum deleted file mode 100644 index 4a689aba75..0000000000 --- a/util/crossgcc/sum/clang-tools-extra-8.0.0.src.tar.xz.cksum +++ /dev/null @@ -1 +0,0 @@ -f341ba17494ba756fd404b2744e6f5991b50389f tarballs/clang-tools-extra-8.0.0.src.tar.xz diff --git a/util/crossgcc/sum/clang-tools-extra-9.0.0.src.tar.xz.cksum b/util/crossgcc/sum/clang-tools-extra-9.0.0.src.tar.xz.cksum new file mode 100644 index 0000000000..47eba2cca0 --- /dev/null +++ b/util/crossgcc/sum/clang-tools-extra-9.0.0.src.tar.xz.cksum @@ -0,0 +1 @@ +ac64403321d8486699d8bea5376b2438663dbb41 tarballs/clang-tools-extra-9.0.0.src.tar.xz diff --git a/util/crossgcc/sum/compiler-rt-8.0.0.src.tar.xz.cksum b/util/crossgcc/sum/compiler-rt-8.0.0.src.tar.xz.cksum deleted file mode 100644 index 2f6cc29250..0000000000 --- a/util/crossgcc/sum/compiler-rt-8.0.0.src.tar.xz.cksum +++ /dev/null @@ -1 +0,0 @@ -5af387779120bb2a9fad5d6fff1a3d6f4fa6c352 tarballs/compiler-rt-8.0.0.src.tar.xz diff --git a/util/crossgcc/sum/compiler-rt-9.0.0.src.tar.xz.cksum b/util/crossgcc/sum/compiler-rt-9.0.0.src.tar.xz.cksum new file mode 100644 index 0000000000..15f1a61e70 --- /dev/null +++ b/util/crossgcc/sum/compiler-rt-9.0.0.src.tar.xz.cksum @@ -0,0 +1 @@ +4e00cb231ff87fd4f970f35b2da86185a612e0e2 tarballs/compiler-rt-9.0.0.src.tar.xz diff --git a/util/crossgcc/sum/llvm-8.0.0.src.tar.xz.cksum b/util/crossgcc/sum/llvm-8.0.0.src.tar.xz.cksum deleted file mode 100644 index 078a3d0f31..0000000000 --- a/util/crossgcc/sum/llvm-8.0.0.src.tar.xz.cksum +++ /dev/null @@ -1 +0,0 @@ -0689345d73911e24a07b24cc82dab4fb46b8c323 tarballs/llvm-8.0.0.src.tar.xz diff --git a/util/crossgcc/sum/llvm-9.0.0.src.tar.xz.cksum b/util/crossgcc/sum/llvm-9.0.0.src.tar.xz.cksum new file mode 100644 index 0000000000..4fb1c2daad --- /dev/null +++ b/util/crossgcc/sum/llvm-9.0.0.src.tar.xz.cksum @@ -0,0 +1 @@ +7ef2527ba3da7603a41ce3592a8cd890f8d27ffa tarballs/llvm-9.0.0.src.tar.xz From a2ac3ad5e5802e017f71706899f77fd795878099 Mon Sep 17 00:00:00 2001 From: Matt DeVillier Date: Wed, 19 Dec 2018 02:15:07 -0600 Subject: [PATCH 0396/1242] google/glados: add libgfxinit support Both linear framebuffer and vga text mode verified on chell and caroline variants Change-Id: I106e7bb761055581634176a112816be8447e6745 Signed-off-by: Matt DeVillier Reviewed-on: https://review.coreboot.org/c/coreboot/+/37205 Tested-by: build bot (Jenkins) Reviewed-by: Angel Pons --- src/mainboard/google/glados/Kconfig | 1 + src/mainboard/google/glados/Makefile.inc | 2 ++ src/mainboard/google/glados/gma-mainboard.ads | 31 +++++++++++++++++++ 3 files changed, 34 insertions(+) create mode 100644 src/mainboard/google/glados/gma-mainboard.ads diff --git a/src/mainboard/google/glados/Kconfig b/src/mainboard/google/glados/Kconfig index fe7359f59f..52907cc683 100644 --- a/src/mainboard/google/glados/Kconfig +++ b/src/mainboard/google/glados/Kconfig @@ -19,6 +19,7 @@ config BOARD_GOOGLE_BASEBOARD_GLADOS select MAINBOARD_HAS_TPM1 select SOC_INTEL_SKYLAKE select SYSTEM_TYPE_LAPTOP + select MAINBOARD_HAS_LIBGFXINIT if BOARD_GOOGLE_BASEBOARD_GLADOS diff --git a/src/mainboard/google/glados/Makefile.inc b/src/mainboard/google/glados/Makefile.inc index 323e68baa2..af43f7c495 100644 --- a/src/mainboard/google/glados/Makefile.inc +++ b/src/mainboard/google/glados/Makefile.inc @@ -30,6 +30,8 @@ ramstage-y += mainboard.c smm-y += smihandler.c +ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads + subdirs-y += variants/$(VARIANT_DIR) CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/variants/baseboard/include CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/variants/$(VARIANT_DIR)/include diff --git a/src/mainboard/google/glados/gma-mainboard.ads b/src/mainboard/google/glados/gma-mainboard.ads new file mode 100644 index 0000000000..87cdb5e7c0 --- /dev/null +++ b/src/mainboard/google/glados/gma-mainboard.ads @@ -0,0 +1,31 @@ +-- +-- This file is part of the coreboot project. +-- +-- This program is free software; you can redistribute it and/or modify +-- it under the terms of the GNU General Public License as published by +-- the Free Software Foundation; either version 2 of the License, or +-- (at your option) any later version. +-- +-- This program is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more details. +-- + +with HW.GFX.GMA; +with HW.GFX.GMA.Display_Probing; + +use HW.GFX.GMA; +use HW.GFX.GMA.Display_Probing; + +private package GMA.Mainboard is + + ports : constant Port_List := + (Internal, + DP1, + DP2, + HDMI1, + HDMI2, + others => Disabled); + +end GMA.Mainboard; From 64dc5c1d53421d5f01245cca41a0f5e49791316a Mon Sep 17 00:00:00 2001 From: Matt DeVillier Date: Sat, 21 Sep 2019 13:54:58 -0500 Subject: [PATCH 0397/1242] google/fizz: add libgfxinit support Change-Id: Idd7bfa4a97770f525c3f25f04f90c4bf092e4ae1 Signed-off-by: Matt DeVillier Reviewed-on: https://review.coreboot.org/c/coreboot/+/37206 Tested-by: build bot (Jenkins) Reviewed-by: Angel Pons --- src/mainboard/google/fizz/Kconfig | 1 + src/mainboard/google/fizz/Makefile.inc | 2 ++ src/mainboard/google/fizz/gma-mainboard.ads | 30 +++++++++++++++++++++ 3 files changed, 33 insertions(+) create mode 100644 src/mainboard/google/fizz/gma-mainboard.ads diff --git a/src/mainboard/google/fizz/Kconfig b/src/mainboard/google/fizz/Kconfig index 44ac064bd1..cafb855fe4 100644 --- a/src/mainboard/google/fizz/Kconfig +++ b/src/mainboard/google/fizz/Kconfig @@ -17,6 +17,7 @@ config BOARD_GOOGLE_BASEBOARD_FIZZ select INTEL_GMA_HAVE_VBT select INTEL_LPSS_UART_FOR_CONSOLE select MAINBOARD_HAS_CHROMEOS + select MAINBOARD_HAS_LIBGFXINIT select NO_FADT_8042 select SOC_INTEL_KABYLAKE select MAINBOARD_HAS_SPI_TPM_CR50 diff --git a/src/mainboard/google/fizz/Makefile.inc b/src/mainboard/google/fizz/Makefile.inc index 3e030c3270..9721c45c7d 100644 --- a/src/mainboard/google/fizz/Makefile.inc +++ b/src/mainboard/google/fizz/Makefile.inc @@ -24,6 +24,8 @@ ramstage-$(CONFIG_CHROMEOS) += chromeos.c ramstage-$(CONFIG_EC_GOOGLE_CHROMEEC) += ec.c ramstage-y += mainboard.c +ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads + smm-y += smihandler.c subdirs-y += variants/baseboard diff --git a/src/mainboard/google/fizz/gma-mainboard.ads b/src/mainboard/google/fizz/gma-mainboard.ads new file mode 100644 index 0000000000..e47ea7eab3 --- /dev/null +++ b/src/mainboard/google/fizz/gma-mainboard.ads @@ -0,0 +1,30 @@ +-- +-- This file is part of the coreboot project. +-- +-- This program is free software; you can redistribute it and/or modify +-- it under the terms of the GNU General Public License as published by +-- the Free Software Foundation; either version 2 of the License, or +-- (at your option) any later version. +-- +-- This program is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more details. +-- + +with HW.GFX.GMA; +with HW.GFX.GMA.Display_Probing; + +use HW.GFX.GMA; +use HW.GFX.GMA.Display_Probing; + +private package GMA.Mainboard is + + ports : constant Port_List := + (DP1, + DP2, + HDMI1, + HDMI2, + others => Disabled); + +end GMA.Mainboard; From 8cfffb442785097050621bd289b60a194b59b2aa Mon Sep 17 00:00:00 2001 From: Matt DeVillier Date: Mon, 25 Nov 2019 01:20:18 -0600 Subject: [PATCH 0398/1242] google/eve: add libgfxinit support Change-Id: Id9d9d804dfc2301b8d2186aff7be331d5ddbf18a Signed-off-by: Matt DeVillier Reviewed-on: https://review.coreboot.org/c/coreboot/+/37207 Tested-by: build bot (Jenkins) Reviewed-by: Angel Pons --- src/mainboard/google/eve/Kconfig | 1 + src/mainboard/google/eve/Makefile.inc | 2 ++ src/mainboard/google/eve/gma-mainboard.ads | 31 ++++++++++++++++++++++ 3 files changed, 34 insertions(+) create mode 100644 src/mainboard/google/eve/gma-mainboard.ads diff --git a/src/mainboard/google/eve/Kconfig b/src/mainboard/google/eve/Kconfig index c768ecc3a4..31ff6e9335 100644 --- a/src/mainboard/google/eve/Kconfig +++ b/src/mainboard/google/eve/Kconfig @@ -18,6 +18,7 @@ config BOARD_SPECIFIC_OPTIONS select INTEL_LPSS_UART_FOR_CONSOLE select MAINBOARD_HAS_CHROMEOS select MAINBOARD_HAS_I2C_TPM_CR50 + select MAINBOARD_HAS_LIBGFXINIT select MAINBOARD_HAS_TPM2 select SOC_INTEL_KABYLAKE diff --git a/src/mainboard/google/eve/Makefile.inc b/src/mainboard/google/eve/Makefile.inc index d137f92b2d..ed1933ec55 100644 --- a/src/mainboard/google/eve/Makefile.inc +++ b/src/mainboard/google/eve/Makefile.inc @@ -25,4 +25,6 @@ ramstage-$(CONFIG_CHROMEOS) += chromeos.c ramstage-y += mainboard.c ramstage-$(CONFIG_EC_GOOGLE_CHROMEEC) += ec.c +ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads + smm-y += smihandler.c diff --git a/src/mainboard/google/eve/gma-mainboard.ads b/src/mainboard/google/eve/gma-mainboard.ads new file mode 100644 index 0000000000..87cdb5e7c0 --- /dev/null +++ b/src/mainboard/google/eve/gma-mainboard.ads @@ -0,0 +1,31 @@ +-- +-- This file is part of the coreboot project. +-- +-- This program is free software; you can redistribute it and/or modify +-- it under the terms of the GNU General Public License as published by +-- the Free Software Foundation; either version 2 of the License, or +-- (at your option) any later version. +-- +-- This program is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more details. +-- + +with HW.GFX.GMA; +with HW.GFX.GMA.Display_Probing; + +use HW.GFX.GMA; +use HW.GFX.GMA.Display_Probing; + +private package GMA.Mainboard is + + ports : constant Port_List := + (Internal, + DP1, + DP2, + HDMI1, + HDMI2, + others => Disabled); + +end GMA.Mainboard; From 7ad1a34ea7a975781b2d5a311948b36805b8af3a Mon Sep 17 00:00:00 2001 From: Matt DeVillier Date: Mon, 25 Nov 2019 01:53:52 -0600 Subject: [PATCH 0399/1242] google/beltino: add libgfxinit support Tested on Zako variant Change-Id: I433863b34731584797456eee6c2d270868a4f13f Signed-off-by: Matt DeVillier Reviewed-on: https://review.coreboot.org/c/coreboot/+/37208 Tested-by: build bot (Jenkins) Reviewed-by: Angel Pons --- src/mainboard/google/beltino/Kconfig | 1 + src/mainboard/google/beltino/Makefile.inc | 2 ++ .../google/beltino/gma-mainboard.ads | 30 +++++++++++++++++++ 3 files changed, 33 insertions(+) create mode 100644 src/mainboard/google/beltino/gma-mainboard.ads diff --git a/src/mainboard/google/beltino/Kconfig b/src/mainboard/google/beltino/Kconfig index 4b18c8cfea..01e0cbf35b 100644 --- a/src/mainboard/google/beltino/Kconfig +++ b/src/mainboard/google/beltino/Kconfig @@ -10,6 +10,7 @@ config BOARD_GOOGLE_BASEBOARD_BELTINO select HAVE_OPTION_TABLE select HAVE_ACPI_RESUME select MAINBOARD_HAS_CHROMEOS + select MAINBOARD_HAS_LIBGFXINIT select MAINBOARD_HAS_LPC_TPM select MAINBOARD_HAS_TPM1 diff --git a/src/mainboard/google/beltino/Makefile.inc b/src/mainboard/google/beltino/Makefile.inc index e1bebc1369..3b763a08c4 100644 --- a/src/mainboard/google/beltino/Makefile.inc +++ b/src/mainboard/google/beltino/Makefile.inc @@ -22,5 +22,7 @@ smm-y += smihandler.c variants/$(VARIANT_DIR)/led.c romstage-y += variants/$(VARIANT_DIR)/led.c +ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads + subdirs-y += variants/$(VARIANT_DIR) CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/variants/$(VARIANT_DIR)/include diff --git a/src/mainboard/google/beltino/gma-mainboard.ads b/src/mainboard/google/beltino/gma-mainboard.ads new file mode 100644 index 0000000000..3a92b599ff --- /dev/null +++ b/src/mainboard/google/beltino/gma-mainboard.ads @@ -0,0 +1,30 @@ +-- +-- This file is part of the coreboot project. +-- +-- This program is free software; you can redistribute it and/or modify +-- it under the terms of the GNU General Public License as published by +-- the Free Software Foundation; either version 2 of the License, or +-- (at your option) any later version. +-- +-- This program is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more details. +-- + +with HW.GFX.GMA; +with HW.GFX.GMA.Display_Probing; + +use HW.GFX.GMA; +use HW.GFX.GMA.Display_Probing; + +private package GMA.Mainboard is + + ports : constant Port_List := + (HDMI1, + HDMI2, + DP1, + DP2, + others => Disabled); + +end GMA.Mainboard; From 941796a50d1ed3cefd503aa28b97be14e22273bb Mon Sep 17 00:00:00 2001 From: Matt DeVillier Date: Mon, 25 Nov 2019 01:55:12 -0600 Subject: [PATCH 0400/1242] google/jecht: add libgfxinit support Tested on Guado variant Change-Id: Ie3a42d1d69d11eebda25e60572f5d9a7452144c2 Signed-off-by: Matt DeVillier Reviewed-on: https://review.coreboot.org/c/coreboot/+/37209 Tested-by: build bot (Jenkins) Reviewed-by: Angel Pons --- src/mainboard/google/jecht/Kconfig | 1 + src/mainboard/google/jecht/Makefile.inc | 2 ++ src/mainboard/google/jecht/gma-mainboard.ads | 30 ++++++++++++++++++++ 3 files changed, 33 insertions(+) create mode 100644 src/mainboard/google/jecht/gma-mainboard.ads diff --git a/src/mainboard/google/jecht/Kconfig b/src/mainboard/google/jecht/Kconfig index 41727c56a7..6d1fda93f8 100644 --- a/src/mainboard/google/jecht/Kconfig +++ b/src/mainboard/google/jecht/Kconfig @@ -7,6 +7,7 @@ config BOARD_GOOGLE_BASEBOARD_JECHT select HAVE_OPTION_TABLE select HAVE_ACPI_RESUME select MAINBOARD_HAS_CHROMEOS + select MAINBOARD_HAS_LIBGFXINIT select MAINBOARD_HAS_LPC_TPM select MAINBOARD_HAS_TPM1 diff --git a/src/mainboard/google/jecht/Makefile.inc b/src/mainboard/google/jecht/Makefile.inc index 9ea24f6aa0..ed7177617b 100644 --- a/src/mainboard/google/jecht/Makefile.inc +++ b/src/mainboard/google/jecht/Makefile.inc @@ -28,6 +28,8 @@ bootblock-y += led.c bootblock-y += bootblock.c +ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads + subdirs-y += variants/$(VARIANT_DIR) CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/variants/$(VARIANT_DIR)/include diff --git a/src/mainboard/google/jecht/gma-mainboard.ads b/src/mainboard/google/jecht/gma-mainboard.ads new file mode 100644 index 0000000000..3a92b599ff --- /dev/null +++ b/src/mainboard/google/jecht/gma-mainboard.ads @@ -0,0 +1,30 @@ +-- +-- This file is part of the coreboot project. +-- +-- This program is free software; you can redistribute it and/or modify +-- it under the terms of the GNU General Public License as published by +-- the Free Software Foundation; either version 2 of the License, or +-- (at your option) any later version. +-- +-- This program is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more details. +-- + +with HW.GFX.GMA; +with HW.GFX.GMA.Display_Probing; + +use HW.GFX.GMA; +use HW.GFX.GMA.Display_Probing; + +private package GMA.Mainboard is + + ports : constant Port_List := + (HDMI1, + HDMI2, + DP1, + DP2, + others => Disabled); + +end GMA.Mainboard; From 4ff63d3a11014fa1a54c82a3023182059c5812f1 Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Fri, 30 Aug 2019 20:05:33 +0200 Subject: [PATCH 0401/1242] soc/skylake: Write the P2SB IBDF and HBDF registers in coreboot MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Do it in coreboot code instead of letting FSP do it. Change-Id: Ic5e8a62141608463ade398432253bad460a9a79d Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/35170 Tested-by: build bot (Jenkins) Reviewed-by: Michael Niewöhner Reviewed-by: Nico Huber --- src/soc/intel/skylake/chip.c | 8 +++----- src/soc/intel/skylake/include/soc/systemagent.h | 2 ++ src/soc/intel/skylake/romstage/romstage.c | 9 +++------ src/soc/intel/skylake/romstage/systemagent.c | 5 +++++ 4 files changed, 13 insertions(+), 11 deletions(-) diff --git a/src/soc/intel/skylake/chip.c b/src/soc/intel/skylake/chip.c index 1e0803c67b..de11a9e1c7 100644 --- a/src/soc/intel/skylake/chip.c +++ b/src/soc/intel/skylake/chip.c @@ -391,17 +391,15 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd) /* Set TccActivationOffset */ tconfig->TccActivationOffset = config->tcc_offset; + /* Already handled in coreboot code, so tell FSP to ignore UPDs */ + params->PchIoApicBdfValid = 0; + /* Enable VT-d and X2APIC */ if (!config->ignore_vtd && soc_is_vtd_capable()) { params->VtdBaseAddress[0] = GFXVT_BASE_ADDRESS; params->VtdBaseAddress[1] = VTVC0_BASE_ADDRESS; params->X2ApicOptOut = 0; tconfig->VtdDisable = 0; - - params->PchIoApicBdfValid = 1; - params->PchIoApicBusNumber = V_P2SB_IBDF_BUS; - params->PchIoApicDeviceNumber = V_P2SB_IBDF_DEV; - params->PchIoApicFunctionNumber = V_P2SB_IBDF_FUN; } dev = pcidev_path_on_root(SA_DEVFN_IGD); diff --git a/src/soc/intel/skylake/include/soc/systemagent.h b/src/soc/intel/skylake/include/soc/systemagent.h index 565c885893..91209c8793 100644 --- a/src/soc/intel/skylake/include/soc/systemagent.h +++ b/src/soc/intel/skylake/include/soc/systemagent.h @@ -66,9 +66,11 @@ static const struct sa_mmio_descriptor soc_vtvc0_mmio_descriptor = { #define V_P2SB_IBDF_BUS 250 #define V_P2SB_IBDF_DEV 31 #define V_P2SB_IBDF_FUN 0 +#define V_DEFAULT_IBDF ((V_P2SB_IBDF_BUS << 8) | PCI_DEVFN(V_P2SB_IBDF_DEV, V_P2SB_IBDF_FUN)) #define V_P2SB_HBDF_BUS 250 #define V_P2SB_HBDF_DEV 15 #define V_P2SB_HBDF_FUN 0 +#define V_DEFAULT_HBDF ((V_P2SB_HBDF_BUS << 8) | PCI_DEVFN(V_P2SB_HBDF_DEV, V_P2SB_HBDF_FUN)) #endif diff --git a/src/soc/intel/skylake/romstage/romstage.c b/src/soc/intel/skylake/romstage/romstage.c index 2904f05f01..d381caa104 100644 --- a/src/soc/intel/skylake/romstage/romstage.c +++ b/src/soc/intel/skylake/romstage/romstage.c @@ -248,12 +248,9 @@ static void soc_memory_init_params(FSP_M_CONFIG *m_cfg, cpu_flex_override(m_cfg); - if (!config->ignore_vtd) { - m_cfg->PchHpetBdfValid = 1; - m_cfg->PchHpetBusNumber = V_P2SB_HBDF_BUS; - m_cfg->PchHpetDeviceNumber = V_P2SB_HBDF_DEV; - m_cfg->PchHpetFunctionNumber = V_P2SB_HBDF_FUN; - } + /* HPET BDF already handled in coreboot code, so tell FSP to ignore UPDs */ + m_cfg->PchHpetBdfValid = 0; + m_cfg->HyperThreading = CONFIG(FSP_HYPERTHREADING); } diff --git a/src/soc/intel/skylake/romstage/systemagent.c b/src/soc/intel/skylake/romstage/systemagent.c index bf0d5064e4..e1272a1cb1 100644 --- a/src/soc/intel/skylake/romstage/systemagent.c +++ b/src/soc/intel/skylake/romstage/systemagent.c @@ -19,6 +19,7 @@ #include #include #include +#include #include #include #include @@ -38,6 +39,10 @@ static void systemagent_vtd_init(void) if (!vtd_capable) return; + /* Configure P2SB VT-d originators (HPET and IOAPIC) */ + pci_write_config16(PCH_DEV_P2SB, PCH_P2SB_HBDF, V_DEFAULT_HBDF); + pci_write_config16(PCH_DEV_P2SB, PCH_P2SB_IBDF, V_DEFAULT_IBDF); + if (igd_dev && igd_dev->enabled) sa_set_mch_bar(&soc_gfxvt_mmio_descriptor, 1); From b48d63359bb4beb63cf2e14edb7b1d833e602ce1 Mon Sep 17 00:00:00 2001 From: Arthur Heymans Date: Tue, 4 Jun 2019 14:51:19 +0200 Subject: [PATCH 0402/1242] soc/intel/baytrail: Use sb/intel/common/spi.c This common implementation is compatible. Change-Id: I2023bb7522ec40f1d9911cb5c57d7d66e4cefa6d Signed-off-by: Arthur Heymans Reviewed-on: https://review.coreboot.org/c/coreboot/+/33206 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber --- src/soc/intel/baytrail/Kconfig | 1 + src/soc/intel/baytrail/Makefile.inc | 4 - src/soc/intel/baytrail/include/soc/spi.h | 7 - src/soc/intel/baytrail/spi.c | 600 ----------------------- 4 files changed, 1 insertion(+), 611 deletions(-) delete mode 100644 src/soc/intel/baytrail/spi.c diff --git a/src/soc/intel/baytrail/Kconfig b/src/soc/intel/baytrail/Kconfig index fac14cbd3b..e96b53d321 100644 --- a/src/soc/intel/baytrail/Kconfig +++ b/src/soc/intel/baytrail/Kconfig @@ -18,6 +18,7 @@ config CPU_SPECIFIC_OPTIONS select SUPPORT_CPU_UCODE_IN_CBFS select HAVE_SMI_HANDLER select SOUTHBRIDGE_INTEL_COMMON_RESET + select SOUTHBRIDGE_INTEL_COMMON_SPI_SILVERMONT select NO_FIXED_XIP_ROM_SIZE select PARALLEL_MP select PCIEXP_ASPM diff --git a/src/soc/intel/baytrail/Makefile.inc b/src/soc/intel/baytrail/Makefile.inc index d9663462c6..2c49c63454 100644 --- a/src/soc/intel/baytrail/Makefile.inc +++ b/src/soc/intel/baytrail/Makefile.inc @@ -12,12 +12,10 @@ subdirs-y += ../../../cpu/intel/common romstage-y += iosf.c romstage-y += memmap.c romstage-y += pmutil.c -romstage-y += spi.c romstage-y += tsc_freq.c postcar-y += iosf.c postcar-y += memmap.c -postcar-y += spi.c postcar-y += tsc_freq.c ramstage-y += acpi.c @@ -43,7 +41,6 @@ ramstage-y += scc.c ramstage-y += sd.c ramstage-y += smm.c ramstage-y += southcluster.c -ramstage-y += spi.c ramstage-y += tsc_freq.c ramstage-y += xhci.c ramstage-$(CONFIG_ELOG) += elog.c @@ -52,7 +49,6 @@ ramstage-$(CONFIG_HAVE_REFCODE_BLOB) += refcode.c smm-y += iosf.c smm-y += pmutil.c smm-y += smihandler.c -smm-y += spi.c smm-y += tsc_freq.c # Remove as ramstage gets fleshed out diff --git a/src/soc/intel/baytrail/include/soc/spi.h b/src/soc/intel/baytrail/include/soc/spi.h index 063dd7fd3a..1ac0b59e56 100644 --- a/src/soc/intel/baytrail/include/soc/spi.h +++ b/src/soc/intel/baytrail/include/soc/spi.h @@ -20,14 +20,7 @@ /* These registers live behind SPI_BASE_ADDRESS. */ #define HSFSTS 0x04 -#define FDATA0 0x10 # define FLOCKDN (0x1 << 15) -#define SSFS 0x90 -# define CYCLE_DONE_STATUS (0x1 << 2) -# define FLASH_CYCLE_ERROR (0x1 << 3) -#define SSFC 0x91 -# define SPI_CYCLE_GO (0x1 << 1) -# define DATA_CYCLE (0x1 << 14) #define PREOP 0x94 #define OPTYPE 0x96 #define OPMENU0 0x98 diff --git a/src/soc/intel/baytrail/spi.c b/src/soc/intel/baytrail/spi.c deleted file mode 100644 index e43900258e..0000000000 --- a/src/soc/intel/baytrail/spi.c +++ /dev/null @@ -1,600 +0,0 @@ -/* - * Copyright (c) 2013 Google Inc. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but without any warranty; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -/* This file is derived from the flashrom project. */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include - -typedef struct spi_slave ich_spi_slave; - -static int ichspi_lock = 0; - -typedef struct ich9_spi_regs { - uint32_t bfpr; - uint16_t hsfs; - uint16_t hsfc; - uint32_t faddr; - uint32_t _reserved0; - uint32_t fdata[16]; - uint32_t frap; - uint32_t freg[5]; - uint32_t _reserved1[3]; - uint32_t pr[5]; - uint32_t _reserved2[2]; - uint8_t ssfs; - uint8_t ssfc[3]; - uint16_t preop; - uint16_t optype; - uint8_t opmenu[8]; - uint32_t bbar; - uint8_t _reserved3[12]; - uint32_t fdoc; - uint32_t fdod; - uint8_t _reserved4[8]; - uint32_t afc; - uint32_t lvscc; - uint32_t uvscc; - uint8_t _reserved5[4]; - uint32_t fpb; - uint8_t _reserved6[28]; - uint32_t srdl; - uint32_t srdc; - uint32_t srd; -} __packed ich9_spi_regs; - -typedef struct ich_spi_controller { - int locked; - - uint8_t *opmenu; - int menubytes; - uint16_t *preop; - uint16_t *optype; - uint32_t *addr; - uint8_t *data; - unsigned int databytes; - uint8_t *status; - uint16_t *control; - uint32_t *bbar; -} ich_spi_controller; - -static ich_spi_controller cntlr; - -enum { - SPIS_SCIP = 0x0001, - SPIS_GRANT = 0x0002, - SPIS_CDS = 0x0004, - SPIS_FCERR = 0x0008, - SSFS_AEL = 0x0010, - SPIS_LOCK = 0x8000, - SPIS_RESERVED_MASK = 0x7ff0, - SSFS_RESERVED_MASK = 0x7fe2 -}; - -enum { - SPIC_SCGO = 0x000002, - SPIC_ACS = 0x000004, - SPIC_SPOP = 0x000008, - SPIC_DBC = 0x003f00, - SPIC_DS = 0x004000, - SPIC_SME = 0x008000, - SSFC_SCF_MASK = 0x070000, - SSFC_RESERVED = 0xf80000 -}; - -enum { - HSFS_FDONE = 0x0001, - HSFS_FCERR = 0x0002, - HSFS_AEL = 0x0004, - HSFS_BERASE_MASK = 0x0018, - HSFS_BERASE_SHIFT = 3, - HSFS_SCIP = 0x0020, - HSFS_FDOPSS = 0x2000, - HSFS_FDV = 0x4000, - HSFS_FLOCKDN = 0x8000 -}; - -enum { - HSFC_FGO = 0x0001, - HSFC_FCYCLE_MASK = 0x0006, - HSFC_FCYCLE_SHIFT = 1, - HSFC_FDBC_MASK = 0x3f00, - HSFC_FDBC_SHIFT = 8, - HSFC_FSMIE = 0x8000 -}; - -enum { - SPI_OPCODE_TYPE_READ_NO_ADDRESS = 0, - SPI_OPCODE_TYPE_WRITE_NO_ADDRESS = 1, - SPI_OPCODE_TYPE_READ_WITH_ADDRESS = 2, - SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS = 3 -}; - -#if CONFIG(DEBUG_SPI_FLASH) - -static u8 readb_(const void *addr) -{ - u8 v = read8((unsigned long)addr); - printk(BIOS_DEBUG, "read %2.2x from %4.4x\n", - v, ((unsigned int) addr & 0xffff) - 0xf020); - return v; -} - -static u16 readw_(const void *addr) -{ - u16 v = read16((unsigned long)addr); - printk(BIOS_DEBUG, "read %4.4x from %4.4x\n", - v, ((unsigned int) addr & 0xffff) - 0xf020); - return v; -} - -static u32 readl_(const void *addr) -{ - u32 v = read32((unsigned long)addr); - printk(BIOS_DEBUG, "read %8.8x from %4.4x\n", - v, ((unsigned int) addr & 0xffff) - 0xf020); - return v; -} - -static void writeb_(u8 b, void *addr) -{ - write8(addr, b); - printk(BIOS_DEBUG, "wrote %2.2x to %4.4x\n", - b, ((unsigned int) addr & 0xffff) - 0xf020); -} - -static void writew_(u16 b, void *addr) -{ - write16(addr, b); - printk(BIOS_DEBUG, "wrote %4.4x to %4.4x\n", - b, ((unsigned int) addr & 0xffff) - 0xf020); -} - -static void writel_(u32 b, void *addr) -{ - write32(addr, b); - printk(BIOS_DEBUG, "wrote %8.8x to %4.4x\n", - b, ((unsigned int) addr & 0xffff) - 0xf020); -} - -#else /* CONFIG_DEBUG_SPI_FLASH ^^^ enabled vvv NOT enabled */ - -#define readb_(a) read8(a) -#define readw_(a) read16(a) -#define readl_(a) read32(a) -#define writeb_(val, addr) write8(addr, val) -#define writew_(val, addr) write16(addr, val) -#define writel_(val, addr) write32(addr, val) - -#endif /* CONFIG_DEBUG_SPI_FLASH ^^^ NOT enabled */ - -static void write_reg(const void *value, void *dest, uint32_t size) -{ - const uint8_t *bvalue = value; - uint8_t *bdest = dest; - - while (size >= 4) { - writel_(*(const uint32_t *)bvalue, bdest); - bdest += 4; bvalue += 4; size -= 4; - } - while (size) { - writeb_(*bvalue, bdest); - bdest++; bvalue++; size--; - } -} - -static void read_reg(const void *src, void *value, uint32_t size) -{ - const uint8_t *bsrc = src; - uint8_t *bvalue = value; - - while (size >= 4) { - *(uint32_t *)bvalue = readl_(bsrc); - bsrc += 4; bvalue += 4; size -= 4; - } - while (size) { - *bvalue = readb_(bsrc); - bsrc++; bvalue++; size--; - } -} - -static void ich_set_bbar(uint32_t minaddr) -{ - const uint32_t bbar_mask = 0x00ffff00; - uint32_t ichspi_bbar; - - minaddr &= bbar_mask; - ichspi_bbar = readl_(cntlr.bbar) & ~bbar_mask; - ichspi_bbar |= minaddr; - writel_(ichspi_bbar, cntlr.bbar); -} - -static ich9_spi_regs *spi_regs(void) -{ - uint32_t sbase; - -#ifdef __SIMPLE_DEVICE__ - pci_devfn_t dev = PCI_DEV(0, LPC_DEV, LPC_FUNC); -#else - struct device *dev = pcidev_on_root(LPC_DEV, LPC_FUNC); -#endif - sbase = pci_read_config32(dev, SBASE); - sbase &= ~0x1ff; - - return (void *)sbase; -} - -#define MENU_BYTES member_size(struct ich9_spi_regs, opmenu) - -void spi_init(void) -{ - ich9_spi_regs *ich9_spi = spi_regs(); - - ichspi_lock = readw_(&ich9_spi->hsfs) & HSFS_FLOCKDN; - cntlr.opmenu = ich9_spi->opmenu; - cntlr.menubytes = sizeof(ich9_spi->opmenu); - cntlr.optype = &ich9_spi->optype; - cntlr.addr = &ich9_spi->faddr; - cntlr.data = (uint8_t *)ich9_spi->fdata; - cntlr.databytes = sizeof(ich9_spi->fdata); - cntlr.status = &ich9_spi->ssfs; - cntlr.control = (uint16_t *)ich9_spi->ssfc; - cntlr.bbar = &ich9_spi->bbar; - cntlr.preop = &ich9_spi->preop; - ich_set_bbar(0); -} - -static void spi_init_cb(void *unused) -{ - spi_init(); -} - -BOOT_STATE_INIT_ENTRY(BS_DEV_INIT, BS_ON_ENTRY, spi_init_cb, NULL); - -typedef struct spi_transaction { - const uint8_t *out; - uint32_t bytesout; - uint8_t *in; - uint32_t bytesin; - uint8_t type; - uint8_t opcode; - uint32_t offset; -} spi_transaction; - -static inline void spi_use_out(spi_transaction *trans, unsigned int bytes) -{ - trans->out += bytes; - trans->bytesout -= bytes; -} - -static inline void spi_use_in(spi_transaction *trans, unsigned int bytes) -{ - trans->in += bytes; - trans->bytesin -= bytes; -} - -static void spi_setup_type(spi_transaction *trans) -{ - trans->type = 0xFF; - - /* Try to guess spi type from read/write sizes. */ - if (trans->bytesin == 0) { - if (trans->bytesout > 4) - /* - * If bytesin = 0 and bytesout > 4, we presume this is - * a write data operation, which is accompanied by an - * address. - */ - trans->type = SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS; - else - trans->type = SPI_OPCODE_TYPE_WRITE_NO_ADDRESS; - return; - } - - if (trans->bytesout == 1) { /* and bytesin is > 0 */ - trans->type = SPI_OPCODE_TYPE_READ_NO_ADDRESS; - return; - } - - if (trans->bytesout == 4) { /* and bytesin is > 0 */ - trans->type = SPI_OPCODE_TYPE_READ_WITH_ADDRESS; - } - - /* Fast read command is called with 5 bytes instead of 4 */ - if (trans->out[0] == SPI_OPCODE_FAST_READ && trans->bytesout == 5) { - trans->type = SPI_OPCODE_TYPE_READ_WITH_ADDRESS; - --trans->bytesout; - } -} - -static int spi_setup_opcode(spi_transaction *trans) -{ - uint16_t optypes; - uint8_t opmenu[MENU_BYTES]; - - trans->opcode = trans->out[0]; - spi_use_out(trans, 1); - if (!ichspi_lock) { - /* The lock is off, so just use index 0. */ - writeb_(trans->opcode, cntlr.opmenu); - optypes = readw_(cntlr.optype); - optypes = (optypes & 0xfffc) | (trans->type & 0x3); - writew_(optypes, cntlr.optype); - return 0; - } else { - /* The lock is on. See if what we need is on the menu. */ - uint8_t optype; - uint16_t opcode_index; - - /* Write Enable is handled as atomic prefix */ - if (trans->opcode == SPI_OPCODE_WREN) - return 0; - - read_reg(cntlr.opmenu, opmenu, sizeof(opmenu)); - for (opcode_index = 0; opcode_index < ARRAY_SIZE(opmenu); opcode_index++) { - if (opmenu[opcode_index] == trans->opcode) - break; - } - - if (opcode_index == ARRAY_SIZE(opmenu)) { - printk(BIOS_DEBUG, "ICH SPI: Opcode %x not found\n", - trans->opcode); - return -1; - } - - optypes = readw_(cntlr.optype); - optype = (optypes >> (opcode_index * 2)) & 0x3; - if (trans->type == SPI_OPCODE_TYPE_WRITE_NO_ADDRESS && - optype == SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS && - trans->bytesout >= 3) { - /* We guessed wrong earlier. Fix it up. */ - trans->type = optype; - } - if (optype != trans->type) { - printk(BIOS_DEBUG, "ICH SPI: Transaction doesn't fit type %d\n", - optype); - return -1; - } - return opcode_index; - } -} - -static int spi_setup_offset(spi_transaction *trans) -{ - /* Separate the SPI address and data. */ - switch (trans->type) { - case SPI_OPCODE_TYPE_READ_NO_ADDRESS: - case SPI_OPCODE_TYPE_WRITE_NO_ADDRESS: - return 0; - case SPI_OPCODE_TYPE_READ_WITH_ADDRESS: - case SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS: - trans->offset = ((uint32_t)trans->out[0] << 16) | - ((uint32_t)trans->out[1] << 8) | - ((uint32_t)trans->out[2] << 0); - spi_use_out(trans, 3); - return 1; - default: - printk(BIOS_DEBUG, "Unrecognized SPI transaction type %#x\n", trans->type); - return -1; - } -} - -/* - * Wait for up to 60ms til status register bit(s) turn 1 (in case wait_til_set - * below is True) or 0. In case the wait was for the bit(s) to set - write - * those bits back, which would cause resetting them. - * - * Return the last read status value on success or -1 on failure. - */ -static int ich_status_poll(u16 bitmask, int wait_til_set) -{ - int timeout = 40000; /* This will result in 400 ms */ - u16 status = 0; - - while (timeout--) { - status = readw_(cntlr.status); - if (wait_til_set ^ ((status & bitmask) == 0)) { - if (wait_til_set) - writew_((status & bitmask), cntlr.status); - return status; - } - udelay(10); - } - - printk(BIOS_DEBUG, "ICH SPI: SCIP timeout, read %x, expected %x\n", - status, bitmask); - return -1; -} - -static int spi_ctrlr_xfer(const struct spi_slave *slave, const void *dout, - size_t bytesout, void *din, size_t bytesin) -{ - uint16_t control; - int16_t opcode_index; - int with_address; - int status; - - spi_transaction trans = { - dout, bytesout, - din, bytesin, - 0xff, 0xff, 0 - }; - - /* There has to always at least be an opcode. */ - if (!bytesout || !dout) { - printk(BIOS_DEBUG, "ICH SPI: No opcode for transfer\n"); - return -1; - } - /* Make sure if we read something we have a place to put it. */ - if (bytesin != 0 && !din) { - printk(BIOS_DEBUG, "ICH SPI: Read but no target buffer\n"); - return -1; - } - - if (ich_status_poll(SPIS_SCIP, 0) == -1) - return -1; - - writew_(SPIS_CDS | SPIS_FCERR, cntlr.status); - - spi_setup_type(&trans); - if ((opcode_index = spi_setup_opcode(&trans)) < 0) - return -1; - if ((with_address = spi_setup_offset(&trans)) < 0) - return -1; - - if (trans.opcode == SPI_OPCODE_WREN) { - /* - * Treat Write Enable as Atomic Pre-Op if possible - * in order to prevent the Management Engine from - * issuing a transaction between WREN and DATA. - */ - if (!ichspi_lock) - writew_(trans.opcode, cntlr.preop); - return 0; - } - - /* Preset control fields */ - control = SPIC_SCGO | ((opcode_index & 0x07) << 4); - - /* Issue atomic preop cycle if needed */ - if (readw_(cntlr.preop)) - control |= SPIC_ACS; - - if (!trans.bytesout && !trans.bytesin) { - /* SPI addresses are 24 bit only */ - if (with_address) - writel_(trans.offset & 0x00FFFFFF, cntlr.addr); - - /* - * This is a 'no data' command (like Write Enable), its - * bytesout size was 1, decremented to zero while executing - * spi_setup_opcode() above. Tell the chip to send the - * command. - */ - writew_(control, cntlr.control); - - /* wait for the result */ - status = ich_status_poll(SPIS_CDS | SPIS_FCERR, 1); - if (status == -1) - return -1; - - if (status & SPIS_FCERR) { - printk(BIOS_DEBUG, "ICH SPI: Command transaction error\n"); - return -1; - } - - return 0; - } - - /* - * Check if this is a write command attempting to transfer more bytes - * than the controller can handle. Iterations for writes are not - * supported here because each SPI write command needs to be preceded - * and followed by other SPI commands, and this sequence is controlled - * by the SPI chip driver. - */ - if (trans.bytesout > cntlr.databytes) { - printk(BIOS_DEBUG, "ICH SPI: Too much to write. Does your SPI chip driver use" - " spi_crop_chunk()?\n"); - return -1; - } - - /* - * Read or write up to databytes bytes at a time until everything has - * been sent. - */ - while (trans.bytesout || trans.bytesin) { - uint32_t data_length; - - /* SPI addresses are 24 bit only */ - writel_(trans.offset & 0x00FFFFFF, cntlr.addr); - - if (trans.bytesout) - data_length = min(trans.bytesout, cntlr.databytes); - else - data_length = min(trans.bytesin, cntlr.databytes); - - /* Program data into FDATA0 to N */ - if (trans.bytesout) { - write_reg(trans.out, cntlr.data, data_length); - spi_use_out(&trans, data_length); - if (with_address) - trans.offset += data_length; - } - - /* Add proper control fields' values */ - control &= ~((cntlr.databytes - 1) << 8); - control |= SPIC_DS; - control |= (data_length - 1) << 8; - - /* write it */ - writew_(control, cntlr.control); - - /* Wait for Cycle Done Status or Flash Cycle Error. */ - status = ich_status_poll(SPIS_CDS | SPIS_FCERR, 1); - if (status == -1) - return -1; - - if (status & SPIS_FCERR) { - printk(BIOS_DEBUG, "ICH SPI: Data transaction error\n"); - return -1; - } - - if (trans.bytesin) { - read_reg(cntlr.data, trans.in, data_length); - spi_use_in(&trans, data_length); - if (with_address) - trans.offset += data_length; - } - } - - /* Clear atomic preop now that xfer is done */ - writew_(0, cntlr.preop); - - return 0; -} - -static int xfer_vectors(const struct spi_slave *slave, - struct spi_op vectors[], size_t count) -{ - return spi_flash_vector_helper(slave, vectors, count, spi_ctrlr_xfer); -} - -static const struct spi_ctrlr spi_ctrlr = { - .xfer_vector = xfer_vectors, - .max_xfer_size = member_size(ich9_spi_regs, fdata), -}; - -const struct spi_ctrlr_buses spi_ctrlr_bus_map[] = { - { - .ctrlr = &spi_ctrlr, - .bus_start = 0, - .bus_end = 0, - }, -}; - -const size_t spi_ctrlr_bus_map_count = ARRAY_SIZE(spi_ctrlr_bus_map); From 7d802a48f3a0a72e99feb6e3fc90adab7d706511 Mon Sep 17 00:00:00 2001 From: Arthur Heymans Date: Sun, 13 Oct 2019 23:29:41 +0200 Subject: [PATCH 0403/1242] soc/intel/baytrail: Don't reinitialize SPI after lockdown With the common southbridge SPI code reinitialization after lockdown is not necessary, hence the SMM finalize call becomes a no-op. Change-Id: Ie73a0adc120731d541a772e09f3482902771b9eb Signed-off-by: Arthur Heymans Reviewed-on: https://review.coreboot.org/c/coreboot/+/36008 Reviewed-by: Nico Huber Tested-by: build bot (Jenkins) --- src/soc/intel/baytrail/smihandler.c | 20 -------------------- src/soc/intel/baytrail/southcluster.c | 3 --- 2 files changed, 23 deletions(-) diff --git a/src/soc/intel/baytrail/smihandler.c b/src/soc/intel/baytrail/smihandler.c index 16e2d950b5..2a92cb954c 100644 --- a/src/soc/intel/baytrail/smihandler.c +++ b/src/soc/intel/baytrail/smihandler.c @@ -229,22 +229,6 @@ static void southbridge_smi_gsmi(void) *ret = gsmi_exec(sub_command, param); } -static void finalize(void) -{ - static int finalize_done; - - if (finalize_done) { - printk(BIOS_DEBUG, "SMM already finalized.\n"); - return; - } - finalize_done = 1; - -#if CONFIG(SPI_FLASH_SMM) - /* Re-init SPI driver to handle locked BAR */ - spi_init(); -#endif -} - /* * soc_legacy: A payload (Depthcharge) has indicated that the * legacy payload (SeaBIOS) is being loaded. Switch devices that are @@ -348,10 +332,6 @@ static void southbridge_smi_apmc(void) if (CONFIG(ELOG_GSMI)) southbridge_smi_gsmi(); break; - case APM_CNT_FINALIZE: - finalize(); - break; - case APM_CNT_LEGACY: soc_legacy(); break; diff --git a/src/soc/intel/baytrail/southcluster.c b/src/soc/intel/baytrail/southcluster.c index fb6143efb0..55bef11909 100644 --- a/src/soc/intel/baytrail/southcluster.c +++ b/src/soc/intel/baytrail/southcluster.c @@ -577,9 +577,6 @@ static void finalize_chipset(void *unused) write32(spi + UVSCC, cfg.uvscc); write32(spi + LVSCC, cfg.lvscc | VCL); } - - printk(BIOS_DEBUG, "Finalizing SMM.\n"); - outb(APM_CNT_FINALIZE, APM_CNT); } BOOT_STATE_INIT_ENTRY(BS_OS_RESUME, BS_ON_ENTRY, finalize_chipset, NULL); From b0f15f0f86b13257fdbf3ce2c2c651c40116994c Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ky=C3=B6sti=20M=C3=A4lkki?= Date: Fri, 22 Nov 2019 23:15:29 +0200 Subject: [PATCH 0404/1242] soc/intel/tigerlake: Fix smm_relocation_params MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Platform is not yet build-tested, this should have gone in with commit f5c0d61 intel/smm: Provide common smm_relocation_params. Change-Id: Iba667972e361d3ed463258357ab6bbde26ef1e06 Signed-off-by: Kyösti Mälkki Reviewed-on: https://review.coreboot.org/c/coreboot/+/37165 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber --- src/soc/intel/tigerlake/Kconfig | 1 + src/soc/intel/tigerlake/smmrelocate.c | 11 ----------- 2 files changed, 1 insertion(+), 11 deletions(-) diff --git a/src/soc/intel/tigerlake/Kconfig b/src/soc/intel/tigerlake/Kconfig index 01ce7d8ee8..d76771025a 100644 --- a/src/soc/intel/tigerlake/Kconfig +++ b/src/soc/intel/tigerlake/Kconfig @@ -45,6 +45,7 @@ config CPU_SPECIFIC_OPTIONS select SMP select SOC_AHCI_PORT_IMPLEMENTED_INVERT select PMC_GLOBAL_RESET_ENABLE_LOCK + select CPU_INTEL_COMMON_SMM select SOC_INTEL_COMMON select SOC_INTEL_COMMON_ACPI_WAKE_SOURCE select SOC_INTEL_COMMON_BLOCK diff --git a/src/soc/intel/tigerlake/smmrelocate.c b/src/soc/intel/tigerlake/smmrelocate.c index 53f206d1c2..46f550bfb5 100644 --- a/src/soc/intel/tigerlake/smmrelocate.c +++ b/src/soc/intel/tigerlake/smmrelocate.c @@ -33,17 +33,6 @@ #include #include -/* This gets filled in and used during relocation. */ -static struct smm_relocation_params smm_reloc_params; - -static inline void write_smrr(struct smm_relocation_params *relo_params) -{ - printk(BIOS_DEBUG, "Writing SMRR. base = 0x%08x, mask=0x%08x\n", - relo_params->smrr_base.lo, relo_params->smrr_mask.lo); - wrmsr(IA32_SMRR_PHYS_BASE, relo_params->smrr_base); - wrmsr(IA32_SMRR_PHYS_MASK, relo_params->smrr_mask); -} - static void update_save_state(int cpu, uintptr_t curr_smbase, uintptr_t staggered_smbase, struct smm_relocation_params *relo_params) From d367503147125210fbc09fa43628d233840f2c65 Mon Sep 17 00:00:00 2001 From: Surendranath Gurivireddy Date: Thu, 31 Oct 2019 15:45:39 -0700 Subject: [PATCH 0405/1242] soc/intel/cannonlake: Disable USB2 PHY Power gating Workaround to disable USB2 PHY power gating to fix issue seen when Apple 87W USB-C charger is connected in S0ix state on WHL platforms (based on Intel's recommendation). Issue is seen on CML platforms also. So, disable power gating for Drallion too. Add devicetree entry to set the flag to disable USB2 PHY power gating for different CNL PCH based platforms BUG=b:133775942 TEST=Connect Apple 87W USB-C charger when the system is in sleep and check if the system wakes up after that Signed-off-by: Surendranath Gurivireddy Change-Id: I95909c73de758fccc7f616a330c1e1f0667e8c25 Reviewed-on: https://review.coreboot.org/c/coreboot/+/36519 Reviewed-by: Duncan Laurie Reviewed-by: EricR Lai Tested-by: build bot (Jenkins) --- src/mainboard/google/drallion/variants/drallion/devicetree.cb | 2 ++ src/mainboard/google/sarien/variants/arcada/devicetree.cb | 2 ++ src/mainboard/google/sarien/variants/sarien/devicetree.cb | 2 ++ src/soc/intel/cannonlake/chip.h | 2 ++ src/soc/intel/cannonlake/fsp_params.c | 3 +++ 5 files changed, 11 insertions(+) diff --git a/src/mainboard/google/drallion/variants/drallion/devicetree.cb b/src/mainboard/google/drallion/variants/drallion/devicetree.cb index ed44f4fec1..6ecb689790 100644 --- a/src/mainboard/google/drallion/variants/drallion/devicetree.cb +++ b/src/mainboard/google/drallion/variants/drallion/devicetree.cb @@ -38,6 +38,8 @@ chip soc/intel/cannonlake register "PchPmSlpSusMinAssert" = "4" # 4s register "PchPmSlpAMinAssert" = "4" # 2s register "PchUnlockGpioPads" = "1" + # USB2 PHY Power gating + register "PchUsb2PhySusPgDisable" = "1" register "speed_shift_enable" = "1" register "psys_pmax" = "140" diff --git a/src/mainboard/google/sarien/variants/arcada/devicetree.cb b/src/mainboard/google/sarien/variants/arcada/devicetree.cb index 4af8ca25ca..6bc3df11af 100644 --- a/src/mainboard/google/sarien/variants/arcada/devicetree.cb +++ b/src/mainboard/google/sarien/variants/arcada/devicetree.cb @@ -27,6 +27,8 @@ chip soc/intel/cannonlake register "PchPmSlpSusMinAssert" = "4" # 4s register "PchPmSlpAMinAssert" = "4" # 2s register "PchUnlockGpioPads" = "1" + # USB2 PHY Power gating + register "PchUsb2PhySusPgDisable" = "1" register "speed_shift_enable" = "1" register "psys_pmax" = "140" diff --git a/src/mainboard/google/sarien/variants/sarien/devicetree.cb b/src/mainboard/google/sarien/variants/sarien/devicetree.cb index cd216e593b..b2aa8d5e8d 100644 --- a/src/mainboard/google/sarien/variants/sarien/devicetree.cb +++ b/src/mainboard/google/sarien/variants/sarien/devicetree.cb @@ -30,6 +30,8 @@ chip soc/intel/cannonlake register "PchPmSlpS4MinAssert" = "4" # 4s register "PchPmSlpSusMinAssert" = "4" # 4s register "PchPmSlpAMinAssert" = "4" # 2s + # USB2 PHY Power gating + register "PchUsb2PhySusPgDisable" = "1" register "speed_shift_enable" = "1" register "s0ix_enable" = "1" diff --git a/src/soc/intel/cannonlake/chip.h b/src/soc/intel/cannonlake/chip.h index 507290f504..f08fd0a95e 100644 --- a/src/soc/intel/cannonlake/chip.h +++ b/src/soc/intel/cannonlake/chip.h @@ -130,6 +130,8 @@ struct soc_intel_cannonlake_config { uint16_t usb2_wake_enable_bitmap; /* Wake Enable Bitmap for USB3 ports */ uint16_t usb3_wake_enable_bitmap; + /* USB2 PHY power gating */ + uint8_t PchUsb2PhySusPgDisable; /* SATA related */ enum { diff --git a/src/soc/intel/cannonlake/fsp_params.c b/src/soc/intel/cannonlake/fsp_params.c index 0713ef4604..dfc7e22522 100644 --- a/src/soc/intel/cannonlake/fsp_params.c +++ b/src/soc/intel/cannonlake/fsp_params.c @@ -273,6 +273,9 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd) params->Usb2AfePehalfbit[i] = config->usb2_ports[i].pre_emp_bit; } + if (config->PchUsb2PhySusPgDisable) + params->PchUsb2PhySusPgEnable = 0; + for (i = 0; i < ARRAY_SIZE(config->usb3_ports); i++) { params->PortUsb30Enable[i] = config->usb3_ports[i].enable; params->Usb3OverCurrentPin[i] = config->usb3_ports[i].ocpin; From 65a8c2e076bc2e200e8a4d6fcaa91a0eab51740b Mon Sep 17 00:00:00 2001 From: Usha P Date: Thu, 14 Nov 2019 11:58:53 +0530 Subject: [PATCH 0406/1242] soc/intel/skylake: Clean up report_cpu_info() function This patch makes below clean-up for report_cpu_info() function. 1. Remove unused variables. 2. Make fill_processor_name function available in bootblock. 3. Reuse fill_processor_name. TEST= Succesfully able to boot soraka and verify the cpu_name "CPU: Intel(R) Pentium(R) CPU 4415Y @ 1.60GHz" Change-Id: Idf7b04edc3fce147f7856591ce7e5a0cd05f43fe Signed-off-by: Usha P Reviewed-on: https://review.coreboot.org/c/coreboot/+/36840 Reviewed-by: Arthur Heymans Tested-by: build bot (Jenkins) --- src/cpu/x86/name/Makefile.inc | 1 + .../intel/skylake/bootblock/report_platform.c | 24 ++++--------------- 2 files changed, 5 insertions(+), 20 deletions(-) diff --git a/src/cpu/x86/name/Makefile.inc b/src/cpu/x86/name/Makefile.inc index a2e37e56fc..944c18f87f 100644 --- a/src/cpu/x86/name/Makefile.inc +++ b/src/cpu/x86/name/Makefile.inc @@ -11,4 +11,5 @@ ## GNU General Public License for more details. ## +bootblock-y += name.c ramstage-y += name.c diff --git a/src/soc/intel/skylake/bootblock/report_platform.c b/src/soc/intel/skylake/bootblock/report_platform.c index 0bd65c3def..b0b416e1a0 100644 --- a/src/soc/intel/skylake/bootblock/report_platform.c +++ b/src/soc/intel/skylake/bootblock/report_platform.c @@ -18,6 +18,7 @@ #include #include #include +#include #include #include #include @@ -164,31 +165,14 @@ static uint16_t get_dev_id(pci_devfn_t dev) static void report_cpu_info(void) { - struct cpuid_result cpuidr; - u32 i, index, cpu_id, cpu_feature_flag; - char cpu_string[50], *cpu_name = cpu_string; /* 48 bytes are reported */ + u32 i, cpu_id, cpu_feature_flag; + char cpu_name[49]; int vt, txt, aes; msr_t microcode_ver; static const char *const mode[] = {"NOT ", ""}; const char *cpu_type = "Unknown"; - index = 0x80000000; - cpuidr = cpuid(index); - if (cpuidr.eax < 0x80000004) { - strcpy(cpu_string, "Platform info not available"); - } else { - u32 *p = (u32 *) cpu_string; - for (i = 2; i <= 4; i++) { - cpuidr = cpuid(index + i); - *p++ = cpuidr.eax; - *p++ = cpuidr.ebx; - *p++ = cpuidr.ecx; - *p++ = cpuidr.edx; - } - } - /* Skip leading spaces in CPU name string */ - while (cpu_name[0] == ' ') - cpu_name++; + fill_processor_name(cpu_name); microcode_ver.lo = 0; microcode_ver.hi = 0; From 3ac0ab524b70d9c3ff4f93684ae8f36f3586d155 Mon Sep 17 00:00:00 2001 From: Marshall Dawson Date: Sun, 24 Nov 2019 19:03:56 -0700 Subject: [PATCH 0407/1242] soc/amd/stoneyridge: Add selectable packages The StoneyPI package supports Family 15h Models 60h-6Fh and 70h-7Fh in FT4 and FP4 packages. Add options for the packages. The existing convention of SOC_AMD_PRODUCTNAME_PKG will be phased out. Change-Id: I60232ca099b813640742868db08aa66b32265f3b Signed-off-by: Marshall Dawson Reviewed-on: https://review.coreboot.org/c/coreboot/+/37218 Tested-by: build bot (Jenkins) Reviewed-by: Richard Spiegel --- src/soc/amd/stoneyridge/Kconfig | 18 ++++++++++++++++++ src/vendorcode/amd/pi/Kconfig | 8 ++++---- 2 files changed, 22 insertions(+), 4 deletions(-) diff --git a/src/soc/amd/stoneyridge/Kconfig b/src/soc/amd/stoneyridge/Kconfig index cbf88df902..c753ecee6a 100644 --- a/src/soc/amd/stoneyridge/Kconfig +++ b/src/soc/amd/stoneyridge/Kconfig @@ -15,16 +15,19 @@ config SOC_AMD_STONEYRIDGE_FP4 bool + select AMD_APU_PKG_FP4 help AMD Stoney Ridge FP4 support config SOC_AMD_STONEYRIDGE_FT4 bool + select AMD_APU_PKG_FT4 help AMD Stoney Ridge FT4 support config SOC_AMD_MERLINFALCON bool + select AMD_APU_PKG_FP4 help AMD Merlin Falcon FP4 support @@ -77,6 +80,21 @@ config CPU_SPECIFIC_OPTIONS select SSE2 select RTC +config AMD_APU_PKG_FP4 + bool + help + AMD FP4 package + +config AMD_APU_PKG_FT4 + bool + help + AMD FT4 package + +config AMD_SOC_PACKAGE + string + default "FP4" if AMD_APU_PKG_FP4 + default "FT4" if AMD_APU_PKG_FT4 + config VBOOT select VBOOT_SEPARATE_VERSTAGE select VBOOT_STARTS_IN_BOOTBLOCK diff --git a/src/vendorcode/amd/pi/Kconfig b/src/vendorcode/amd/pi/Kconfig index 08e7cc6697..06055639fb 100644 --- a/src/vendorcode/amd/pi/Kconfig +++ b/src/vendorcode/amd/pi/Kconfig @@ -44,10 +44,10 @@ config AGESA_BINARY_PI_FILE string "AGESA PI binary file name" default "3rdparty/blobs/pi/amd/00630F01/FP3/AGESA.bin" if CPU_AMD_PI_00630F01 default "3rdparty/blobs/pi/amd/00730F01/FT3b/AGESA.bin" if CPU_AMD_PI_00730F01 - default "3rdparty/blobs/pi/amd/merlinfalcon/FP4/AGESA_CZ_FP4.bin" if SOC_AMD_MERLINFALCON && HAVE_MERLINFALCON_BINARIES - default "3rdparty/blobs/pi/amd/00670F00/FP4/AGESA.bin" if SOC_AMD_MERLINFALCON && !HAVE_MERLINFALCON_BINARIES - default "3rdparty/blobs/pi/amd/00670F00/FP4/AGESA.bin" if SOC_AMD_STONEYRIDGE_FP4 - default "3rdparty/blobs/pi/amd/00670F00/FT4/AGESA.bin" if SOC_AMD_STONEYRIDGE_FT4 + default "3rdparty/blobs/pi/amd/merlinfalcon/$(CONFIG_AMD_SOC_PACKAGE)/AGESA_CZ_FP4.bin" if SOC_AMD_MERLINFALCON && HAVE_MERLINFALCON_BINARIES + default "3rdparty/blobs/pi/amd/00670F00/$(CONFIG_AMD_SOC_PACKAGE)/AGESA.bin" if SOC_AMD_MERLINFALCON && !HAVE_MERLINFALCON_BINARIES + default "3rdparty/blobs/pi/amd/00670F00/$(CONFIG_AMD_SOC_PACKAGE)/AGESA.bin" if SOC_AMD_STONEYRIDGE_FP4 + default "3rdparty/blobs/pi/amd/00670F00/$(CONFIG_AMD_SOC_PACKAGE)/AGESA.bin" if SOC_AMD_STONEYRIDGE_FT4 default "3rdparty/blobs/pi/amd/00660F01/FP4/AGESA.bin" if CPU_AMD_PI_00660F01 help Specify the binary file to use for AMD platform initialization. From 12294d0c48bd5a916e192ca663ffa49a346b420f Mon Sep 17 00:00:00 2001 From: Marshall Dawson Date: Mon, 25 Nov 2019 07:21:18 -0700 Subject: [PATCH 0408/1242] soc/amd/stoneyridge: Add selectable APU names Add APU names of STONEYRIDGE and MERLINFALCON to Kconfig. The existing convention of SOC_AMD_PRODUCTNAME_PKG will be phased out. Don't explicitely use the APU_STONEYRIDGE name yet when creating default paths. Prairie Falcon relies on the default setting, and this will be addressed in a later change. Change-Id: I2061b9b02f6e9def4e151fc38951ad8abb68df1d Signed-off-by: Marshall Dawson Reviewed-on: https://review.coreboot.org/c/coreboot/+/37219 Tested-by: build bot (Jenkins) Reviewed-by: Richard Spiegel --- src/soc/amd/stoneyridge/Kconfig | 24 ++++++++++++++++++------ src/soc/amd/stoneyridge/Makefile.inc | 14 +++++++++++++- 2 files changed, 31 insertions(+), 7 deletions(-) diff --git a/src/soc/amd/stoneyridge/Kconfig b/src/soc/amd/stoneyridge/Kconfig index c753ecee6a..bb297a9356 100644 --- a/src/soc/amd/stoneyridge/Kconfig +++ b/src/soc/amd/stoneyridge/Kconfig @@ -15,24 +15,27 @@ config SOC_AMD_STONEYRIDGE_FP4 bool + select AMD_APU_STONEYRIDGE select AMD_APU_PKG_FP4 help AMD Stoney Ridge FP4 support config SOC_AMD_STONEYRIDGE_FT4 bool + select AMD_APU_STONEYRIDGE select AMD_APU_PKG_FT4 help AMD Stoney Ridge FT4 support config SOC_AMD_MERLINFALCON bool + select AMD_APU_MERLINFALCON select AMD_APU_PKG_FP4 help AMD Merlin Falcon FP4 support config HAVE_MERLINFALCON_BINARIES - depends on SOC_AMD_MERLINFALCON + depends on AMD_APU_MERLINFALCON bool "Merlinfalcon binaries are present" default n help @@ -80,6 +83,16 @@ config CPU_SPECIFIC_OPTIONS select SSE2 select RTC +config AMD_APU_STONEYRIDGE + bool + help + AMD Stoney Ridge APU + +config AMD_APU_MERLINFALCON + bool + help + AMD Merlin Falcon APU + config AMD_APU_PKG_FP4 bool help @@ -153,7 +166,7 @@ config MMCONF_BUS_NUMBER config VGA_BIOS_ID string - default "1002,9874" if SOC_AMD_MERLINFALCON + default "1002,9874" if AMD_APU_MERLINFALCON default "1002,98e4" help The default VGA BIOS PCI vendor/device ID should be set to the @@ -161,7 +174,7 @@ config VGA_BIOS_ID config VGA_BIOS_FILE string - default "3rdparty/blobs/soc/amd/merlinfalcon/VBIOS.bin" if SOC_AMD_MERLINFALCON && HAVE_MERLINFALCON_BINARIES + default "3rdparty/blobs/soc/amd/merlinfalcon/VBIOS.bin" if AMD_APU_MERLINFALCON && HAVE_MERLINFALCON_BINARIES default "3rdparty/blobs/soc/amd/stoneyridge/VBIOS.bin" config S3_VGA_ROM_RUN @@ -210,7 +223,7 @@ config STONEYRIDGE_GEC_FWM_FILE config AMD_PUBKEY_FILE string "AMD public Key" - default "3rdparty/blobs/soc/amd/merlinfalcon/PSP/AmdPubKeyCZ.bin" if SOC_AMD_MERLINFALCON && HAVE_MERLINFALCON_BINARIES + default "3rdparty/blobs/soc/amd/merlinfalcon/PSP/AmdPubKeyCZ.bin" if AMD_APU_MERLINFALCON && HAVE_MERLINFALCON_BINARIES default "3rdparty/blobs/soc/amd/stoneyridge/PSP/AmdPubKeyST.bin" config STONEYRIDGE_SATA_MODE @@ -331,8 +344,7 @@ config USE_PSPSECUREOS config SOC_AMD_PSP_SELECTABLE_SMU_FW bool - default n if SOC_AMD_MERLINFALCON - default y + default y if AMD_APU_STONEYRIDGE help Some ST implementations allow storing SMU firmware into cbfs and calling the PSP to load the blobs at the proper time. diff --git a/src/soc/amd/stoneyridge/Makefile.inc b/src/soc/amd/stoneyridge/Makefile.inc index b74bc68cc3..f697fc2e65 100644 --- a/src/soc/amd/stoneyridge/Makefile.inc +++ b/src/soc/amd/stoneyridge/Makefile.inc @@ -137,11 +137,23 @@ STONEYRIDGE_FWM_POSITION=$(call int-add, \ ### 0 FIRMWARE_LOCATE=$(dir $(call strip_quotes, $(CONFIG_AMD_PUBKEY_FILE))) + +ifeq ($(CONFIG_AMD_APU_STONEYRIDGE),y) +FIRMWARE_TYPE=ST +else + +ifeq ($(CONFIG_AMD_APU_MERLINFALCON),y) +# If Merlin Falcon, but blobs aren't present, use Stoney Ridge instead ifeq ($(CONFIG_HAVE_MERLINFALCON_BINARIES),y) FIRMWARE_TYPE=CZ else FIRMWARE_TYPE=ST -endif +endif # CONFIG_HAVE_MERLINFALCON_BINARIES +else +$(error stoneyridge: Unknown FIRMWARE_TYPE) + +endif # CONFIG_AMD_APU_MERLINFALCON +endif # CONFIG_AMD_APU_STONEYRIDGE ###5 PUBSIGNEDKEY_FILE=$(top)/$(FIRMWARE_LOCATE)/RtmPubSigned$(FIRMWARE_TYPE).key From c7fc199f40339344903c51ff51bbf8610f218b86 Mon Sep 17 00:00:00 2001 From: Vadim Bendebury Date: Tue, 26 Nov 2019 14:08:59 -0800 Subject: [PATCH 0409/1242] cr50 i2c: add error message reporting TPM IRQ timeout Various recent x86 SOCs have trouble registering short pulses generated by the H1 to indicate that it is ready for the next transaction. This patch adds an error message to report this condition, which would greatly reduce the amount of guesswork when troubleshooting new platforms. BUG=b:144002424 TEST=tried this code on the Drallion device exhibiting the problem, observed error messages in the coreboot log; $ grep IRQ ap.log Cr50 i2c TPM IRQ timeout! Cr50 i2c TPM IRQ timeout! Cr50 i2c TPM IRQ timeout! Cr50 i2c TPM IRQ timeout! ... Change-Id: I5f6ee3986bed58e12fd0ec8cecbf35f46c9263c2 Signed-off-by: Vadim Bendebury Reviewed-on: https://review.coreboot.org/c/coreboot/+/37255 Tested-by: build bot (Jenkins) Reviewed-by: Mathew King --- src/drivers/i2c/tpm/cr50.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/src/drivers/i2c/tpm/cr50.c b/src/drivers/i2c/tpm/cr50.c index 6714bd4a03..f9a286241e 100644 --- a/src/drivers/i2c/tpm/cr50.c +++ b/src/drivers/i2c/tpm/cr50.c @@ -78,9 +78,10 @@ static int cr50_i2c_wait_tpm_ready(struct tpm_chip *chip) stopwatch_init_msecs_expire(&sw, CR50_TIMEOUT_IRQ_MS); while (!tis_plat_irq_status()) - if (stopwatch_expired(&sw)) + if (stopwatch_expired(&sw)) { + printk(BIOS_ERR, "Cr50 i2c TPM IRQ timeout!\n"); return -1; - + } return 0; } From d492f01bf16e28cc55e64462e98ba7c99b1bb336 Mon Sep 17 00:00:00 2001 From: David Wu Date: Tue, 26 Nov 2019 19:16:25 +0800 Subject: [PATCH 0410/1242] mb/google/hatch/var/kindred: Add ELAN touchscreen support Add ELAN EKTH6918 USI touchsreen support. BUG=b:131205495 b:127996093 TEST=FW_NAME=kindred emerge-hatch coreboot chromeos-bootimage and check touchscreen work. Change-Id: I8b003685cd7ee68738bcd4298b63a44d6e6118e4 Signed-off-by: David Wu Reviewed-on: https://review.coreboot.org/c/coreboot/+/37236 Reviewed-by: Tim Wawrzynczak Tested-by: build bot (Jenkins) --- .../hatch/variants/kindred/overridetree.cb | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/src/mainboard/google/hatch/variants/kindred/overridetree.cb b/src/mainboard/google/hatch/variants/kindred/overridetree.cb index 9d33fa96d0..1122609649 100644 --- a/src/mainboard/google/hatch/variants/kindred/overridetree.cb +++ b/src/mainboard/google/hatch/variants/kindred/overridetree.cb @@ -145,6 +145,22 @@ chip soc/intel/cannonlake register "has_power_resource" = "1" device i2c 39 on end end + chip drivers/i2c/hid + register "generic.hid" = ""ELAN9004"" + register "generic.desc" = ""ELAN Touchscreen"" + register "generic.irq" = "ACPI_IRQ_EDGE_LOW(GPP_D16_IRQ)" + register "generic.probed" = "1" + register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D15)" + register "generic.reset_delay_ms" = "20" + register "generic.reset_off_delay_ms" = "2" + register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D9)" + register "generic.enable_delay_ms" = "10" + register "generic.stop_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C4)" + register "generic.stop_delay_ms" = "300" + register "generic.has_power_resource" = "1" + register "hid_desc_reg_offset" = "0x01" + device i2c 10 on end + end chip drivers/generic/gpio_keys register "name" = ""PENH"" register "gpio" = "ACPI_GPIO_IRQ_EDGE_BOTH(GPP_A8)" From 3e8ef1028dc92d2f06f20e7f80db70002ba84841 Mon Sep 17 00:00:00 2001 From: Patrick Georgi Date: Fri, 22 Nov 2019 16:54:17 +0100 Subject: [PATCH 0411/1242] util/kconfig: Move coreboot specific changes into Makefile.inc This eases maintenance of our kconfig fork. Change-Id: Ia4bc0bf22e66457356b9f8fcbea9412792495bca Signed-off-by: Patrick Georgi Reviewed-on: https://review.coreboot.org/c/coreboot/+/37151 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer --- Makefile | 2 +- util/kconfig/Makefile | 15 --------------- util/kconfig/Makefile.inc | 27 +++++++++++++++++++++++++++ 3 files changed, 28 insertions(+), 16 deletions(-) create mode 100644 util/kconfig/Makefile.inc diff --git a/Makefile b/Makefile index f3f9592649..41a9b3afa4 100644 --- a/Makefile +++ b/Makefile @@ -119,7 +119,7 @@ help_coreboot help:: # This include must come _before_ the pattern rules below! # Order _does_ matter for pattern rules. -include $(srck)/Makefile +include $(srck)/Makefile.inc # Three cases where we don't need fully populated $(obj) lists: # 1. when no .config exists diff --git a/util/kconfig/Makefile b/util/kconfig/Makefile index 147b125b96..1713b8d0eb 100644 --- a/util/kconfig/Makefile +++ b/util/kconfig/Makefile @@ -10,14 +10,6 @@ DEFCONFIG?=defconfig PHONY += oldconfig xconfig gconfig menuconfig config silentoldconfig update-po-config \ localmodconfig localyesconfig -_OS=$(shell uname -s |cut -c-7) -regex-objs= -ifeq ($(_OS),MINGW32) - regex-objs=regex.o -endif - -Kconfig ?= src/Kconfig - xconfig: $(objk)/qconf $< $(Kconfig) @@ -345,8 +337,6 @@ $(objk)/nconf: $(patsubst %,$(objk)/%,$(nconf-objs)) $(HOSTCC) $(HOSTCFLAGS) -o $@ $^ $(HOSTLOADLIBES_nconf) $(objk)/conf: $(patsubst %,$(objk)/%,$(conf-objs)) $(HOSTCC) $(HOSTCFLAGS) $(HOST_EXTRACFLAGS) -o $@ $^ -$(objk)/toada: $(objk)/toada.o - $(HOSTCC) $(HOSTCFLAGS) $(HOST_EXTRACFLAGS) -o $@ $^ $(objk)/mconf.o: $(srck)/mconf.c $(HOSTCC) $(HOSTCFLAGS) $(HOST_EXTRACFLAGS) -c -o $@ $< @@ -356,8 +346,6 @@ $(objk)/nconf.gui.o: $(srck)/nconf.gui.c $(HOSTCC) $(HOSTCFLAGS) $(HOST_EXTRACFLAGS) -c -o $@ $< $(objk)/conf.o: $(srck)/conf.c $(HOSTCC) $(HOSTCFLAGS) $(HOST_EXTRACFLAGS) -c -o $@ $< -$(objk)/regex.o: $(srck)/regex.c - $(HOSTCC) $(HOSTCFLAGS) $(HOST_EXTRACFLAGS) -DHAVE_STRING_H -c -o $@ $< $(objk)/zconf.tab.o: $(objk)/zconf.tab.c $(objk)/zconf.lex.c \ $(objk)/zconf.hash.c @@ -385,8 +373,5 @@ $(objk)/lxdialog/lxdialog: $(objk)/dochecklxdialog \ $(objk)/lxdialog/%.o: $(srck)/lxdialog/%.c $(HOSTCC) $(HOSTCFLAGS) $(HOST_EXTRACFLAGS) $^ -c -o $@ -$(objk)/toada.o: $(srck)/toada.c - $(HOSTCC) $(HOSTCFLAGS) $(HOST_EXTRACFLAGS) -c -o $@ $< - $(objk)/%.o: HOSTCFLAGS+=-I$(srck) -I$(objk) $(objk)/%.o: HOSTCXXFLAGS+=-I$(srck) -I$(objk) diff --git a/util/kconfig/Makefile.inc b/util/kconfig/Makefile.inc new file mode 100644 index 0000000000..27681f75a1 --- /dev/null +++ b/util/kconfig/Makefile.inc @@ -0,0 +1,27 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# Early configuration of coreboot specific changes +Kconfig ?= src/Kconfig + +# Include verbatim Makefile +include $(dir $(lastword $(MAKEFILE_LIST)))Makefile + +# Extend Linux kconfig build rules + +# Support mingw by shipping our own regex implementation +_OS=$(shell uname -s |cut -c-7) +regex-objs= +ifeq ($(_OS),MINGW32) + regex-objs=regex.o +endif +$(objk)/regex.o: $(srck)/regex.c + $(HOSTCC) $(HOSTCFLAGS) $(HOST_EXTRACFLAGS) -DHAVE_STRING_H -c -o $@ $< + +conf-objs += $(regex-objs) +mconf-objs += $(regex-objs) + +# Provide tool to convert kconfig output into Ada format +$(objk)/toada: $(objk)/toada.o + $(HOSTCC) $(HOSTCFLAGS) $(HOST_EXTRACFLAGS) -o $@ $^ +$(objk)/toada.o: $(srck)/toada.c + $(HOSTCC) $(HOSTCFLAGS) $(HOST_EXTRACFLAGS) -c -o $@ $< From d618aaceae69fa83f630da84036da8ee23ef43e1 Mon Sep 17 00:00:00 2001 From: Julius Werner Date: Tue, 26 Nov 2019 17:58:11 -0800 Subject: [PATCH 0412/1242] security/vboot: Use persistent context to read GBB flags With the persistent vboot context coreboot no longer needs to read GBB flags from flash itself -- it can just ask vboot for the cached result. This patch removes the existing GBB code and provides gbb_is_flag_set() (with a slightly better namespaced name) as a static inline instead. Change-Id: Ibc3ed0f3fbeb53d630925d47df4dc474b0ed07ee Signed-off-by: Julius Werner Reviewed-on: https://review.coreboot.org/c/coreboot/+/37261 Tested-by: build bot (Jenkins) Reviewed-by: Joel Kitching --- src/security/vboot/Makefile.inc | 2 - src/security/vboot/gbb.c | 80 ------------------------------- src/security/vboot/gbb.h | 39 --------------- src/security/vboot/misc.h | 11 +++++ src/security/vboot/vboot_common.c | 4 +- 5 files changed, 13 insertions(+), 123 deletions(-) delete mode 100644 src/security/vboot/gbb.c delete mode 100644 src/security/vboot/gbb.h diff --git a/src/security/vboot/Makefile.inc b/src/security/vboot/Makefile.inc index 010a06cfa7..5292bd142d 100644 --- a/src/security/vboot/Makefile.inc +++ b/src/security/vboot/Makefile.inc @@ -24,8 +24,6 @@ postcar-y += bootmode.c verstage-generic-ccopts += -D__VERSTAGE__ -ramstage-y += gbb.c - bootblock-y += vbnv.c verstage-y += vbnv.c romstage-y += vbnv.c diff --git a/src/security/vboot/gbb.c b/src/security/vboot/gbb.c deleted file mode 100644 index 5293033666..0000000000 --- a/src/security/vboot/gbb.c +++ /dev/null @@ -1,80 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright 2018 Google LLC - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#define NEED_VB20_INTERNALS /* Peeking into vb2_gbb_header */ - -#include -#include -#include -#include -#include -#include - -#define GBB_FMAP_REGION_NAME "GBB" - -/* Copy of GBB header read from boot media. */ -static struct vb2_gbb_header gbb_header; - -/* - * Read "GBB" region from SPI flash to obtain GBB header and validate - * signature. - * - * Return value: - * Success = 0 - * Error = 1 - */ -static int gbb_init(void) -{ - static bool init_done = false; - struct region_device gbb_rdev; - - if (init_done != false) - return 0; - - if (fmap_locate_area_as_rdev(GBB_FMAP_REGION_NAME, &gbb_rdev)) - return 1; - - if (rdev_readat(&gbb_rdev, &gbb_header, 0, - sizeof(struct vb2_gbb_header)) != - sizeof(struct vb2_gbb_header)) { - printk(BIOS_ERR, "%s: Failure to read GBB header!\n", __func__); - return 1; - } - - if (memcmp(gbb_header.signature, VB2_GBB_SIGNATURE, - VB2_GBB_SIGNATURE_SIZE)) { - printk(BIOS_ERR, "%s: Signature check failed!\n", __func__); - return 1; - } - - init_done = true; - return 0; -} - -uint32_t gbb_get_flags(void) -{ - if (gbb_init()) { - printk(BIOS_ERR, - "%s: Failure to initialize GBB. Returning flags as 0!\n", - __func__); - return 0; - } - return gbb_header.flags; -} - -bool gbb_is_flag_set(uint32_t flag) -{ - return !!(gbb_get_flags() & flag); -} diff --git a/src/security/vboot/gbb.h b/src/security/vboot/gbb.h deleted file mode 100644 index 389242a3a2..0000000000 --- a/src/security/vboot/gbb.h +++ /dev/null @@ -1,39 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright 2018 Google LLC - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef __SECURITY_VBOOT_GBB_H__ -#define __SECURITY_VBOOT_GBB_H__ - -#include - -/* In order to use VB2_GBB_FLAG_* macros from vboot, include vb2_api.h. */ - -/* - * Read flags field from GBB header. - * Return value: - * Success: 32-bit unsigned integer representing flags field from GBB header. - * Error : 0 - */ -uint32_t gbb_get_flags(void); - -/* - * Check if given flag is set in the flags field in GBB header. - * Return value: - * true: Flag is set. - * false: Flag is not set or failure to read GBB flags. - */ -bool gbb_is_flag_set(uint32_t flag); - -#endif /* __SECURITY_VBOOT_GBB_H__ */ diff --git a/src/security/vboot/misc.h b/src/security/vboot/misc.h index 1b147992d8..471f838a9c 100644 --- a/src/security/vboot/misc.h +++ b/src/security/vboot/misc.h @@ -49,6 +49,17 @@ static inline int vboot_is_firmware_slot_a(const struct vb2_context *ctx) return !(ctx->flags & VB2_CONTEXT_FW_SLOT_B); } +/* + * Check if given flag is set in the flags field in GBB header. + * Return value: + * true: Flag is set. + * false: Flag is not set. + */ +static inline bool vboot_is_gbb_flag_set(enum vb2_gbb_flag flag) +{ + return !!(vb2api_gbb_get_flags(vboot_get_context()) & flag); +} + /* * Locates firmware as a region device. Returns 0 on success, -1 on failure. */ diff --git a/src/security/vboot/vboot_common.c b/src/security/vboot/vboot_common.c index a24b220a9c..458ed87982 100644 --- a/src/security/vboot/vboot_common.c +++ b/src/security/vboot/vboot_common.c @@ -19,7 +19,7 @@ #include #include #include -#include +#include #include #include #include @@ -31,7 +31,7 @@ int vboot_can_enable_udc(void) if (!vboot_developer_mode_enabled()) return 0; /* Enable if GBB flag is set */ - if (gbb_is_flag_set(VB2_GBB_FLAG_ENABLE_UDC)) + if (vboot_is_gbb_flag_set(VB2_GBB_FLAG_ENABLE_UDC)) return 1; /* Enable if VBNV flag is set */ if (vbnv_udc_enable_flag()) From 693e04f5c661bfe103e42cbf99afded6478a4a4c Mon Sep 17 00:00:00 2001 From: Jacob Garber Date: Sun, 24 Nov 2019 12:57:29 -0700 Subject: [PATCH 0413/1242] arch/arm/include: Remove unused armv7 types.h This header was originally copied from the Linux kernel. However, these days all fixed-width integers are defined in stdint.h, and all of the other typedefs in this file are kernel-specific and aren't used anywhere, so we can drop it. Change-Id: I6ee7acb5e12f4b4b7c4325cedcfee36b93ab6a3d Signed-off-by: Jacob Garber Reviewed-on: https://review.coreboot.org/c/coreboot/+/37257 Tested-by: build bot (Jenkins) Reviewed-by: Julius Werner --- src/arch/arm/include/armv7/arch/types.h | 59 ------------------------- 1 file changed, 59 deletions(-) delete mode 100644 src/arch/arm/include/armv7/arch/types.h diff --git a/src/arch/arm/include/armv7/arch/types.h b/src/arch/arm/include/armv7/arch/types.h deleted file mode 100644 index b9a3d703c1..0000000000 --- a/src/arch/arm/include/armv7/arch/types.h +++ /dev/null @@ -1,59 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef __ASM_ARM_TYPES_H -#define __ASM_ARM_TYPES_H - -typedef unsigned short umode_t; - -/* - * __xx is ok: it doesn't pollute the POSIX namespace. Use these in the - * header files exported to user space - */ - -typedef __signed__ char __s8; -typedef unsigned char __u8; - -typedef __signed__ short __s16; -typedef unsigned short __u16; - -typedef __signed__ int __s32; -typedef unsigned int __u32; - -#if defined(__GNUC__) -__extension__ typedef __signed__ long long __s64; -__extension__ typedef unsigned long long __u64; -#endif - -typedef signed char s8; -typedef unsigned char u8; - -typedef signed short s16; -typedef unsigned short u16; - -typedef signed int s32; -typedef unsigned int u32; - -typedef signed long long s64; -typedef unsigned long long u64; - -#define BITS_PER_LONG 32 - -/* Dma addresses are 32-bits wide. */ - -typedef u32 dma_addr_t; - -typedef unsigned long phys_addr_t; -typedef unsigned long phys_size_t; - -#endif From 7b3e8730ee0ab81988a8a600701d644c8a014e5f Mon Sep 17 00:00:00 2001 From: Nico Huber Date: Tue, 26 Nov 2019 18:30:40 +0100 Subject: [PATCH 0414/1242] soc/intel/skl: Drop FSP_CAR remnants FSP-T support was abandoned long ago for Skylake. With FSP1.1 support also dropped now, it's more visible that this code is unused. Change-Id: I83a9130ef403b498e2beea01749c178e547b0f08 Signed-off-by: Nico Huber Reviewed-on: https://review.coreboot.org/c/coreboot/+/37251 Reviewed-by: Arthur Heymans Tested-by: build bot (Jenkins) --- src/soc/intel/skylake/Kconfig | 1 - src/soc/intel/skylake/Makefile.inc | 1 - src/soc/intel/skylake/fspcar.c | 43 ------------------------------ 3 files changed, 45 deletions(-) delete mode 100644 src/soc/intel/skylake/fspcar.c diff --git a/src/soc/intel/skylake/Kconfig b/src/soc/intel/skylake/Kconfig index 032ded4025..528fd4a0bf 100644 --- a/src/soc/intel/skylake/Kconfig +++ b/src/soc/intel/skylake/Kconfig @@ -31,7 +31,6 @@ config CPU_SPECIFIC_OPTIONS select CPU_INTEL_FIRMWARE_INTERFACE_TABLE select CPU_INTEL_COMMON_HYPERTHREADING select FSP_M_XIP - select FSP_T_XIP if FSP_CAR select GENERIC_GPIO_LIB select HAVE_FSP_GOP select INTEL_DESCRIPTOR_MODE_CAPABLE diff --git a/src/soc/intel/skylake/Makefile.inc b/src/soc/intel/skylake/Makefile.inc index b049e84795..c0937385f0 100644 --- a/src/soc/intel/skylake/Makefile.inc +++ b/src/soc/intel/skylake/Makefile.inc @@ -11,7 +11,6 @@ subdirs-y += ../../../cpu/x86/smm subdirs-y += ../../../cpu/x86/tsc bootblock-y += bootblock/bootblock.c -bootblock-$(CONFIG_FSP_CAR) += fspcar.c bootblock-y += bootblock/cpu.c bootblock-y += i2c.c bootblock-y += bootblock/pch.c diff --git a/src/soc/intel/skylake/fspcar.c b/src/soc/intel/skylake/fspcar.c deleted file mode 100644 index 0d27f57698..0000000000 --- a/src/soc/intel/skylake/fspcar.c +++ /dev/null @@ -1,43 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2018 Intel Corp. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ -#include -#include - -const FSPT_UPD temp_ram_init_params = { - .FspUpdHeader = { - .Signature = 0x545F4450554C424B, /* 'KBLUPD_T' */ - .Revision = 1, - .Reserved = {0}, - }, - .FsptCoreUpd = { - /* - * It is a requirement for firmware to have Firmware Interface Table - * (FIT), which contains pointers to each microcode update. - * The microcode update is loaded for all logical processors before - * cpu reset vector. - * - * All SoC since Gen-4 has above mechanism in place to load microcode - * even before hitting CPU reset vector. Hence skipping FSP-T loading - * microcode after CPU reset by passing '0' value to - * FSPT_UPD.MicrocodeRegionBase and FSPT_UPD.MicrocodeRegionLength. - */ - .MicrocodeRegionBase = 0, - .MicrocodeRegionLength = 0, - .CodeRegionBase = - (uint32_t)(0x100000000ULL - CONFIG_ROM_SIZE), - .CodeRegionSize = (uint32_t)CONFIG_ROM_SIZE, - }, -}; From c4b7ad4db594d6e1616f5e8265a18cefec0a8c6c Mon Sep 17 00:00:00 2001 From: Patrick Georgi Date: Wed, 20 Nov 2019 14:45:09 +0100 Subject: [PATCH 0415/1242] util/release: Don't try to remove a file named like a long string Change-Id: I81fcb58720fb20ac4f57e31e9f991f5009aba568 Signed-off-by: Patrick Georgi Reviewed-on: https://review.coreboot.org/c/coreboot/+/37020 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer --- util/release/genrelnotes | 1 - 1 file changed, 1 deletion(-) diff --git a/util/release/genrelnotes b/util/release/genrelnotes index c19aaa7215..d0f1a7ac1c 100755 --- a/util/release/genrelnotes +++ b/util/release/genrelnotes @@ -192,7 +192,6 @@ version_ctrl_c() { -exec rename 's/gnumakefile/Makefile\.inc/' {} \; git checkout origin/master > /dev/null 2>&1 git submodule update --init --checkout > /dev/null 2>&1 - rm -f "$mainboard_list_old" "$mainboard_list_new" rm "$LOGFILE" exit 1; } From 6572fe538a1991911759c364d31f6054a3810860 Mon Sep 17 00:00:00 2001 From: David Hendricks Date: Tue, 26 Nov 2019 15:46:44 -0800 Subject: [PATCH 0416/1242] Documentation: Rework staging and commit information This patch does two things: - The CLI and Git Cola sections contained some duplicated information about pushing patches, which is now factored out into its own section. - The draft workflow is now disabled, so that part has been reworded to describe how to submit a private patch. Signed-off-by: David Hendricks Change-Id: I562c101ab2ee78d901be7e99165daba7473dc3c1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/37256 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer --- Documentation/tutorial/part2.md | 11 ++++------- 1 file changed, 4 insertions(+), 7 deletions(-) diff --git a/Documentation/tutorial/part2.md b/Documentation/tutorial/part2.md index e5322186f9..3009e28167 100644 --- a/Documentation/tutorial/part2.md +++ b/Documentation/tutorial/part2.md @@ -157,10 +157,10 @@ commit, you wish to make changes to it, running `git commit --amend` allows you to take back your commit and amend it. When you are done with your commit, run `git push` to push your commit to -coreboot.org. **Note:** To submit as a draft, use -`git push origin HEAD:refs/drafts/master`. Submitting as a draft means that -your commit will be on coreboot.org, but is only visible to those you add -as reviewers. +coreboot.org. **Note:** To submit as a private patch, use +`git push origin HEAD:refs/for/master%private`. Submitting as a private patch +means that your commit will be on review.coreboot.org, but is only visible to +yourself and those you add as reviewers. This has been a quick primer on how to submit a change to Gerrit for review using git. You may wish to review the [Gerrit code review workflow @@ -227,9 +227,6 @@ explained in the extended description. When ready, select 'Commit' again. Once all errors have been satisfied and the commit succeeds, move to the command line and run `git push`. -**Note:** To submit as a draft, use `git push origin HEAD:refs/drafts/master`. -Submitting as a draft means that your commit will be on coreboot.org, but is -only visible to those you add as reviewers. ## Part 5: Getting your commit reviewed From 282171c105f18e15c542fc04761c692abbd005ce Mon Sep 17 00:00:00 2001 From: Elyes HAOUAS Date: Sun, 30 Jun 2019 00:16:40 +0200 Subject: [PATCH 0417/1242] mainboard/google: Remove unused include Change-Id: I9e71474bea61befd61900aff554f32f1bc782a77 Signed-off-by: Elyes HAOUAS Reviewed-on: https://review.coreboot.org/c/coreboot/+/33699 Tested-by: build bot (Jenkins) Reviewed-by: Matt DeVillier --- src/mainboard/google/beltino/romstage.c | 1 - src/mainboard/google/beltino/variants/mccloud/hda_verb.c | 2 -- src/mainboard/google/beltino/variants/monroe/hda_verb.c | 2 -- src/mainboard/google/beltino/variants/panther/hda_verb.c | 2 -- src/mainboard/google/beltino/variants/tricky/hda_verb.c | 2 -- src/mainboard/google/beltino/variants/zako/hda_verb.c | 2 -- src/mainboard/google/cyan/variants/banon/gpio.c | 1 - src/mainboard/google/cyan/variants/celes/gpio.c | 1 - src/mainboard/google/cyan/variants/cyan/gpio.c | 1 - src/mainboard/google/cyan/variants/edgar/gpio.c | 1 - src/mainboard/google/cyan/variants/kefka/gpio.c | 2 -- src/mainboard/google/cyan/variants/reks/gpio.c | 1 - src/mainboard/google/cyan/variants/relm/gpio.c | 2 -- src/mainboard/google/cyan/variants/setzer/gpio.c | 2 -- src/mainboard/google/cyan/variants/terra/gpio.c | 1 - src/mainboard/google/cyan/variants/ultima/gpio.c | 1 - src/mainboard/google/cyan/variants/wizpig/gpio.c | 1 - src/mainboard/google/daisy/memory.c | 1 - src/mainboard/google/foster/pmic.c | 1 - src/mainboard/google/gale/boardid.c | 1 - src/mainboard/google/glados/mainboard.c | 1 - src/mainboard/google/gru/boardid.c | 1 - src/mainboard/google/nyan/pmic.c | 1 - src/mainboard/google/nyan_big/boardid.c | 1 - src/mainboard/google/nyan_big/pmic.c | 1 - src/mainboard/google/nyan_blaze/boardid.c | 1 - src/mainboard/google/nyan_blaze/pmic.c | 1 - src/mainboard/google/oak/boardid.c | 1 - src/mainboard/google/oak/sdram_configs.c | 1 - src/mainboard/google/peach_pit/mainboard.c | 1 - src/mainboard/google/peach_pit/memory.c | 1 - src/mainboard/google/peach_pit/romstage.c | 1 - src/mainboard/google/rambi/variants/banjo/gpio.c | 1 - src/mainboard/google/rambi/variants/candy/gpio.c | 1 - src/mainboard/google/rambi/variants/clapper/gpio.c | 1 - src/mainboard/google/rambi/variants/enguarde/gpio.c | 1 - src/mainboard/google/rambi/variants/glimmer/gpio.c | 1 - src/mainboard/google/rambi/variants/gnawty/gpio.c | 1 - src/mainboard/google/rambi/variants/heli/gpio.c | 1 - src/mainboard/google/rambi/variants/kip/gpio.c | 1 - src/mainboard/google/rambi/variants/ninja/gpio.c | 1 - src/mainboard/google/rambi/variants/orco/gpio.c | 1 - src/mainboard/google/rambi/variants/quawks/gpio.c | 1 - src/mainboard/google/rambi/variants/rambi/gpio.c | 1 - src/mainboard/google/rambi/variants/squawks/gpio.c | 1 - src/mainboard/google/rambi/variants/sumo/gpio.c | 1 - src/mainboard/google/rambi/variants/swanky/gpio.c | 1 - src/mainboard/google/rambi/variants/winky/gpio.c | 1 - src/mainboard/google/slippy/variants/falco/romstage.c | 2 +- src/mainboard/google/smaug/boardid.c | 1 - src/mainboard/google/smaug/pmic.c | 1 - src/mainboard/google/storm/boardid.c | 1 - src/mainboard/google/veyron/boardid.c | 1 - src/mainboard/google/veyron/romstage.c | 1 - src/mainboard/google/veyron_mickey/boardid.c | 1 - src/mainboard/google/veyron_mickey/romstage.c | 1 - src/mainboard/google/veyron_rialto/boardid.c | 1 - src/mainboard/google/veyron_rialto/romstage.c | 1 - 58 files changed, 1 insertion(+), 66 deletions(-) diff --git a/src/mainboard/google/beltino/romstage.c b/src/mainboard/google/beltino/romstage.c index f2066647d0..607c8a4d48 100644 --- a/src/mainboard/google/beltino/romstage.c +++ b/src/mainboard/google/beltino/romstage.c @@ -15,7 +15,6 @@ */ #include -#include #include #include #include diff --git a/src/mainboard/google/beltino/variants/mccloud/hda_verb.c b/src/mainboard/google/beltino/variants/mccloud/hda_verb.c index 4d65f36a45..233a8eecca 100644 --- a/src/mainboard/google/beltino/variants/mccloud/hda_verb.c +++ b/src/mainboard/google/beltino/variants/mccloud/hda_verb.c @@ -16,8 +16,6 @@ #ifndef HDA_VERB_H #define HDA_VERB_H -#include - #include const u32 cim_verb_data[] = { diff --git a/src/mainboard/google/beltino/variants/monroe/hda_verb.c b/src/mainboard/google/beltino/variants/monroe/hda_verb.c index 8482ec3d8f..8281fb86d0 100644 --- a/src/mainboard/google/beltino/variants/monroe/hda_verb.c +++ b/src/mainboard/google/beltino/variants/monroe/hda_verb.c @@ -16,8 +16,6 @@ #ifndef HDA_VERB_H #define HDA_VERB_H -#include - #include const u32 cim_verb_data[] = { diff --git a/src/mainboard/google/beltino/variants/panther/hda_verb.c b/src/mainboard/google/beltino/variants/panther/hda_verb.c index 4d65f36a45..233a8eecca 100644 --- a/src/mainboard/google/beltino/variants/panther/hda_verb.c +++ b/src/mainboard/google/beltino/variants/panther/hda_verb.c @@ -16,8 +16,6 @@ #ifndef HDA_VERB_H #define HDA_VERB_H -#include - #include const u32 cim_verb_data[] = { diff --git a/src/mainboard/google/beltino/variants/tricky/hda_verb.c b/src/mainboard/google/beltino/variants/tricky/hda_verb.c index 4d65f36a45..233a8eecca 100644 --- a/src/mainboard/google/beltino/variants/tricky/hda_verb.c +++ b/src/mainboard/google/beltino/variants/tricky/hda_verb.c @@ -16,8 +16,6 @@ #ifndef HDA_VERB_H #define HDA_VERB_H -#include - #include const u32 cim_verb_data[] = { diff --git a/src/mainboard/google/beltino/variants/zako/hda_verb.c b/src/mainboard/google/beltino/variants/zako/hda_verb.c index 4d65f36a45..233a8eecca 100644 --- a/src/mainboard/google/beltino/variants/zako/hda_verb.c +++ b/src/mainboard/google/beltino/variants/zako/hda_verb.c @@ -16,8 +16,6 @@ #ifndef HDA_VERB_H #define HDA_VERB_H -#include - #include const u32 cim_verb_data[] = { diff --git a/src/mainboard/google/cyan/variants/banon/gpio.c b/src/mainboard/google/cyan/variants/banon/gpio.c index 6983d91169..2a3e8fc8ec 100644 --- a/src/mainboard/google/cyan/variants/banon/gpio.c +++ b/src/mainboard/google/cyan/variants/banon/gpio.c @@ -16,7 +16,6 @@ #include #include -#include /* South East Community */ static const struct soc_gpio_map gpse_gpio_map[] = { diff --git a/src/mainboard/google/cyan/variants/celes/gpio.c b/src/mainboard/google/cyan/variants/celes/gpio.c index c416053dae..6f53f2ea37 100644 --- a/src/mainboard/google/cyan/variants/celes/gpio.c +++ b/src/mainboard/google/cyan/variants/celes/gpio.c @@ -16,7 +16,6 @@ #include #include -#include /* South East Community */ static const struct soc_gpio_map gpse_gpio_map[] = { diff --git a/src/mainboard/google/cyan/variants/cyan/gpio.c b/src/mainboard/google/cyan/variants/cyan/gpio.c index c26e7b69fb..05ba93e102 100644 --- a/src/mainboard/google/cyan/variants/cyan/gpio.c +++ b/src/mainboard/google/cyan/variants/cyan/gpio.c @@ -16,7 +16,6 @@ #include #include -#include /* South East Community */ static const struct soc_gpio_map gpse_gpio_map[] = { diff --git a/src/mainboard/google/cyan/variants/edgar/gpio.c b/src/mainboard/google/cyan/variants/edgar/gpio.c index 2010ac5172..59486af102 100644 --- a/src/mainboard/google/cyan/variants/edgar/gpio.c +++ b/src/mainboard/google/cyan/variants/edgar/gpio.c @@ -16,7 +16,6 @@ #include #include -#include /* South East Community */ static const struct soc_gpio_map gpse_gpio_map[] = { diff --git a/src/mainboard/google/cyan/variants/kefka/gpio.c b/src/mainboard/google/cyan/variants/kefka/gpio.c index 0ef284282e..1036cc6985 100644 --- a/src/mainboard/google/cyan/variants/kefka/gpio.c +++ b/src/mainboard/google/cyan/variants/kefka/gpio.c @@ -16,8 +16,6 @@ #include #include -#include - /* South East Community */ static const struct soc_gpio_map gpse_gpio_map[] = { diff --git a/src/mainboard/google/cyan/variants/reks/gpio.c b/src/mainboard/google/cyan/variants/reks/gpio.c index e0d82cf039..955dc51fb7 100644 --- a/src/mainboard/google/cyan/variants/reks/gpio.c +++ b/src/mainboard/google/cyan/variants/reks/gpio.c @@ -16,7 +16,6 @@ #include #include -#include /* South East Community */ static const struct soc_gpio_map gpse_gpio_map[] = { diff --git a/src/mainboard/google/cyan/variants/relm/gpio.c b/src/mainboard/google/cyan/variants/relm/gpio.c index 9cb80e6277..e9014ac6f0 100644 --- a/src/mainboard/google/cyan/variants/relm/gpio.c +++ b/src/mainboard/google/cyan/variants/relm/gpio.c @@ -16,8 +16,6 @@ #include #include -#include - /* South East Community */ static const struct soc_gpio_map gpse_gpio_map[] = { diff --git a/src/mainboard/google/cyan/variants/setzer/gpio.c b/src/mainboard/google/cyan/variants/setzer/gpio.c index 83f742e5d8..517d06971a 100644 --- a/src/mainboard/google/cyan/variants/setzer/gpio.c +++ b/src/mainboard/google/cyan/variants/setzer/gpio.c @@ -16,8 +16,6 @@ #include #include -#include - /* South East Community */ static const struct soc_gpio_map gpse_gpio_map[] = { diff --git a/src/mainboard/google/cyan/variants/terra/gpio.c b/src/mainboard/google/cyan/variants/terra/gpio.c index b4feebff16..dc10ceff85 100644 --- a/src/mainboard/google/cyan/variants/terra/gpio.c +++ b/src/mainboard/google/cyan/variants/terra/gpio.c @@ -16,7 +16,6 @@ #include #include -#include /* South East Community */ static const struct soc_gpio_map gpse_gpio_map[] = { diff --git a/src/mainboard/google/cyan/variants/ultima/gpio.c b/src/mainboard/google/cyan/variants/ultima/gpio.c index fe8c934b7d..3cae31384f 100644 --- a/src/mainboard/google/cyan/variants/ultima/gpio.c +++ b/src/mainboard/google/cyan/variants/ultima/gpio.c @@ -16,7 +16,6 @@ #include #include -#include /* South East Community */ static const struct soc_gpio_map gpse_gpio_map[] = { diff --git a/src/mainboard/google/cyan/variants/wizpig/gpio.c b/src/mainboard/google/cyan/variants/wizpig/gpio.c index affe8932d4..ecd74ef386 100644 --- a/src/mainboard/google/cyan/variants/wizpig/gpio.c +++ b/src/mainboard/google/cyan/variants/wizpig/gpio.c @@ -16,7 +16,6 @@ #include #include -#include /* South East Community */ static const struct soc_gpio_map gpse_gpio_map[] = { diff --git a/src/mainboard/google/daisy/memory.c b/src/mainboard/google/daisy/memory.c index 009604b295..c5b752c2bf 100644 --- a/src/mainboard/google/daisy/memory.c +++ b/src/mainboard/google/daisy/memory.c @@ -20,7 +20,6 @@ #include #include #include -#include const struct mem_timings mem_timings[] = { { diff --git a/src/mainboard/google/foster/pmic.c b/src/mainboard/google/foster/pmic.c index 6435317a22..af6a364903 100644 --- a/src/mainboard/google/foster/pmic.c +++ b/src/mainboard/google/foster/pmic.c @@ -20,7 +20,6 @@ #include #include #include -#include #include "pmic.h" diff --git a/src/mainboard/google/gale/boardid.c b/src/mainboard/google/gale/boardid.c index 96fc936bf3..082cc26876 100644 --- a/src/mainboard/google/gale/boardid.c +++ b/src/mainboard/google/gale/boardid.c @@ -16,7 +16,6 @@ #include #include #include -#include /* * Gale boards dedicate to the board ID three GPIOs in ternary mode: 64, 65 diff --git a/src/mainboard/google/glados/mainboard.c b/src/mainboard/google/glados/mainboard.c index ebc50f41e2..516d7bae2a 100644 --- a/src/mainboard/google/glados/mainboard.c +++ b/src/mainboard/google/glados/mainboard.c @@ -20,7 +20,6 @@ #include #include #include -#include #include #include #include diff --git a/src/mainboard/google/gru/boardid.c b/src/mainboard/google/gru/boardid.c index 4630a9170b..efba922e80 100644 --- a/src/mainboard/google/gru/boardid.c +++ b/src/mainboard/google/gru/boardid.c @@ -16,7 +16,6 @@ #include #include #include -#include #include static const int id_readings[] = { diff --git a/src/mainboard/google/nyan/pmic.c b/src/mainboard/google/nyan/pmic.c index 893d2eace5..75b888865b 100644 --- a/src/mainboard/google/nyan/pmic.c +++ b/src/mainboard/google/nyan/pmic.c @@ -19,7 +19,6 @@ #include #include #include -#include #include #include "pmic.h" diff --git a/src/mainboard/google/nyan_big/boardid.c b/src/mainboard/google/nyan_big/boardid.c index 2a2911c9c5..49a9938cbb 100644 --- a/src/mainboard/google/nyan_big/boardid.c +++ b/src/mainboard/google/nyan_big/boardid.c @@ -16,7 +16,6 @@ #include #include #include -#include uint32_t board_id(void) { diff --git a/src/mainboard/google/nyan_big/pmic.c b/src/mainboard/google/nyan_big/pmic.c index f70e6dd49f..0564f3d597 100644 --- a/src/mainboard/google/nyan_big/pmic.c +++ b/src/mainboard/google/nyan_big/pmic.c @@ -19,7 +19,6 @@ #include #include #include -#include #include #include "pmic.h" diff --git a/src/mainboard/google/nyan_blaze/boardid.c b/src/mainboard/google/nyan_blaze/boardid.c index 2a2911c9c5..49a9938cbb 100644 --- a/src/mainboard/google/nyan_blaze/boardid.c +++ b/src/mainboard/google/nyan_blaze/boardid.c @@ -16,7 +16,6 @@ #include #include #include -#include uint32_t board_id(void) { diff --git a/src/mainboard/google/nyan_blaze/pmic.c b/src/mainboard/google/nyan_blaze/pmic.c index f70e6dd49f..0564f3d597 100644 --- a/src/mainboard/google/nyan_blaze/pmic.c +++ b/src/mainboard/google/nyan_blaze/pmic.c @@ -19,7 +19,6 @@ #include #include #include -#include #include #include "pmic.h" diff --git a/src/mainboard/google/oak/boardid.c b/src/mainboard/google/oak/boardid.c index 91e2df3d88..ada2de5041 100644 --- a/src/mainboard/google/oak/boardid.c +++ b/src/mainboard/google/oak/boardid.c @@ -16,7 +16,6 @@ #include #include #include -#include #include "gpio.h" static int board_id_value = -1; diff --git a/src/mainboard/google/oak/sdram_configs.c b/src/mainboard/google/oak/sdram_configs.c index 65b12ceae5..34191082ca 100644 --- a/src/mainboard/google/oak/sdram_configs.c +++ b/src/mainboard/google/oak/sdram_configs.c @@ -16,7 +16,6 @@ #include #include #include -#include static const struct mt8173_sdram_params sdram_configs[] = { #include "sdram_inf/sdram-lpddr3-H9CCNNN8GTMLAR-2GB.inc" /* ram_code = 0000 */ diff --git a/src/mainboard/google/peach_pit/mainboard.c b/src/mainboard/google/peach_pit/mainboard.c index 234a433acb..553c2adbd5 100644 --- a/src/mainboard/google/peach_pit/mainboard.c +++ b/src/mainboard/google/peach_pit/mainboard.c @@ -33,7 +33,6 @@ #include #include #include -#include #include #include #include diff --git a/src/mainboard/google/peach_pit/memory.c b/src/mainboard/google/peach_pit/memory.c index a5e3d9eeb9..541e3b04c1 100644 --- a/src/mainboard/google/peach_pit/memory.c +++ b/src/mainboard/google/peach_pit/memory.c @@ -19,7 +19,6 @@ #include #include #include -#include const struct mem_timings mem_timings = { .mem_manuf = MEM_MANUF_SAMSUNG, diff --git a/src/mainboard/google/peach_pit/romstage.c b/src/mainboard/google/peach_pit/romstage.c index fdbe534b2c..0c2cb3e3e8 100644 --- a/src/mainboard/google/peach_pit/romstage.c +++ b/src/mainboard/google/peach_pit/romstage.c @@ -33,7 +33,6 @@ #include #include #include -#include #include #include diff --git a/src/mainboard/google/rambi/variants/banjo/gpio.c b/src/mainboard/google/rambi/variants/banjo/gpio.c index bfb2c9aa2f..e22c8db35d 100644 --- a/src/mainboard/google/rambi/variants/banjo/gpio.c +++ b/src/mainboard/google/rambi/variants/banjo/gpio.c @@ -13,7 +13,6 @@ * GNU General Public License for more details. */ -#include #include #include diff --git a/src/mainboard/google/rambi/variants/candy/gpio.c b/src/mainboard/google/rambi/variants/candy/gpio.c index 3cbfbaf459..61050e58b1 100644 --- a/src/mainboard/google/rambi/variants/candy/gpio.c +++ b/src/mainboard/google/rambi/variants/candy/gpio.c @@ -13,7 +13,6 @@ * GNU General Public License for more details. */ -#include #include #include diff --git a/src/mainboard/google/rambi/variants/clapper/gpio.c b/src/mainboard/google/rambi/variants/clapper/gpio.c index 1e02783d68..e1bcefa6e9 100644 --- a/src/mainboard/google/rambi/variants/clapper/gpio.c +++ b/src/mainboard/google/rambi/variants/clapper/gpio.c @@ -13,7 +13,6 @@ * GNU General Public License for more details. */ -#include #include #include diff --git a/src/mainboard/google/rambi/variants/enguarde/gpio.c b/src/mainboard/google/rambi/variants/enguarde/gpio.c index 2802aa6495..784ed23cc5 100644 --- a/src/mainboard/google/rambi/variants/enguarde/gpio.c +++ b/src/mainboard/google/rambi/variants/enguarde/gpio.c @@ -13,7 +13,6 @@ * GNU General Public License for more details. */ -#include #include #include diff --git a/src/mainboard/google/rambi/variants/glimmer/gpio.c b/src/mainboard/google/rambi/variants/glimmer/gpio.c index 8cfe90ea04..504d64adda 100644 --- a/src/mainboard/google/rambi/variants/glimmer/gpio.c +++ b/src/mainboard/google/rambi/variants/glimmer/gpio.c @@ -13,7 +13,6 @@ * GNU General Public License for more details. */ -#include #include #include diff --git a/src/mainboard/google/rambi/variants/gnawty/gpio.c b/src/mainboard/google/rambi/variants/gnawty/gpio.c index e79dc5a827..7e2361c086 100644 --- a/src/mainboard/google/rambi/variants/gnawty/gpio.c +++ b/src/mainboard/google/rambi/variants/gnawty/gpio.c @@ -13,7 +13,6 @@ * GNU General Public License for more details. */ -#include #include #include diff --git a/src/mainboard/google/rambi/variants/heli/gpio.c b/src/mainboard/google/rambi/variants/heli/gpio.c index 2a61c556cb..bcb1430c98 100644 --- a/src/mainboard/google/rambi/variants/heli/gpio.c +++ b/src/mainboard/google/rambi/variants/heli/gpio.c @@ -13,7 +13,6 @@ * GNU General Public License for more details. */ -#include #include #include diff --git a/src/mainboard/google/rambi/variants/kip/gpio.c b/src/mainboard/google/rambi/variants/kip/gpio.c index 3d79d37441..56942bd2be 100644 --- a/src/mainboard/google/rambi/variants/kip/gpio.c +++ b/src/mainboard/google/rambi/variants/kip/gpio.c @@ -13,7 +13,6 @@ * GNU General Public License for more details. */ -#include #include #include diff --git a/src/mainboard/google/rambi/variants/ninja/gpio.c b/src/mainboard/google/rambi/variants/ninja/gpio.c index 85d565e44a..2d8285c6d6 100644 --- a/src/mainboard/google/rambi/variants/ninja/gpio.c +++ b/src/mainboard/google/rambi/variants/ninja/gpio.c @@ -13,7 +13,6 @@ * GNU General Public License for more details. */ -#include #include #include diff --git a/src/mainboard/google/rambi/variants/orco/gpio.c b/src/mainboard/google/rambi/variants/orco/gpio.c index f2bbe8abdb..afa50cf1ce 100644 --- a/src/mainboard/google/rambi/variants/orco/gpio.c +++ b/src/mainboard/google/rambi/variants/orco/gpio.c @@ -13,7 +13,6 @@ * GNU General Public License for more details. */ -#include #include #include diff --git a/src/mainboard/google/rambi/variants/quawks/gpio.c b/src/mainboard/google/rambi/variants/quawks/gpio.c index 3d79d37441..56942bd2be 100644 --- a/src/mainboard/google/rambi/variants/quawks/gpio.c +++ b/src/mainboard/google/rambi/variants/quawks/gpio.c @@ -13,7 +13,6 @@ * GNU General Public License for more details. */ -#include #include #include diff --git a/src/mainboard/google/rambi/variants/rambi/gpio.c b/src/mainboard/google/rambi/variants/rambi/gpio.c index 3d79d37441..56942bd2be 100644 --- a/src/mainboard/google/rambi/variants/rambi/gpio.c +++ b/src/mainboard/google/rambi/variants/rambi/gpio.c @@ -13,7 +13,6 @@ * GNU General Public License for more details. */ -#include #include #include diff --git a/src/mainboard/google/rambi/variants/squawks/gpio.c b/src/mainboard/google/rambi/variants/squawks/gpio.c index 3d79d37441..56942bd2be 100644 --- a/src/mainboard/google/rambi/variants/squawks/gpio.c +++ b/src/mainboard/google/rambi/variants/squawks/gpio.c @@ -13,7 +13,6 @@ * GNU General Public License for more details. */ -#include #include #include diff --git a/src/mainboard/google/rambi/variants/sumo/gpio.c b/src/mainboard/google/rambi/variants/sumo/gpio.c index 0856c29d24..c4cc40aa98 100644 --- a/src/mainboard/google/rambi/variants/sumo/gpio.c +++ b/src/mainboard/google/rambi/variants/sumo/gpio.c @@ -13,7 +13,6 @@ * GNU General Public License for more details. */ -#include #include #include diff --git a/src/mainboard/google/rambi/variants/swanky/gpio.c b/src/mainboard/google/rambi/variants/swanky/gpio.c index a713549cd9..3b62880b0d 100644 --- a/src/mainboard/google/rambi/variants/swanky/gpio.c +++ b/src/mainboard/google/rambi/variants/swanky/gpio.c @@ -13,7 +13,6 @@ * GNU General Public License for more details. */ -#include #include #include diff --git a/src/mainboard/google/rambi/variants/winky/gpio.c b/src/mainboard/google/rambi/variants/winky/gpio.c index dcdf6f5d76..9c3a33875b 100644 --- a/src/mainboard/google/rambi/variants/winky/gpio.c +++ b/src/mainboard/google/rambi/variants/winky/gpio.c @@ -13,7 +13,6 @@ * GNU General Public License for more details. */ -#include #include #include diff --git a/src/mainboard/google/slippy/variants/falco/romstage.c b/src/mainboard/google/slippy/variants/falco/romstage.c index 1903588816..c193d20e41 100644 --- a/src/mainboard/google/slippy/variants/falco/romstage.c +++ b/src/mainboard/google/slippy/variants/falco/romstage.c @@ -14,8 +14,8 @@ * GNU General Public License for more details. */ +#include #include -#include #include #include #include diff --git a/src/mainboard/google/smaug/boardid.c b/src/mainboard/google/smaug/boardid.c index 2512f830cf..74f6f11e22 100644 --- a/src/mainboard/google/smaug/boardid.c +++ b/src/mainboard/google/smaug/boardid.c @@ -15,7 +15,6 @@ #include #include -#include #include "gpio.h" diff --git a/src/mainboard/google/smaug/pmic.c b/src/mainboard/google/smaug/pmic.c index 68e0f6ccd3..fdbabacc9c 100644 --- a/src/mainboard/google/smaug/pmic.c +++ b/src/mainboard/google/smaug/pmic.c @@ -20,7 +20,6 @@ #include #include #include -#include #include "pmic.h" diff --git a/src/mainboard/google/storm/boardid.c b/src/mainboard/google/storm/boardid.c index 87f6d2a796..d952155e8d 100644 --- a/src/mainboard/google/storm/boardid.c +++ b/src/mainboard/google/storm/boardid.c @@ -16,7 +16,6 @@ #include #include #include -#include /* * Storm boards dedicate to the board ID three GPIOs in tertiary mode: 29, 30 diff --git a/src/mainboard/google/veyron/boardid.c b/src/mainboard/google/veyron/boardid.c index c9c68ccd5b..bf311cf605 100644 --- a/src/mainboard/google/veyron/boardid.c +++ b/src/mainboard/google/veyron/boardid.c @@ -16,7 +16,6 @@ #include #include #include -#include uint32_t board_id(void) { diff --git a/src/mainboard/google/veyron/romstage.c b/src/mainboard/google/veyron/romstage.c index 3870b63a60..eba96c4650 100644 --- a/src/mainboard/google/veyron/romstage.c +++ b/src/mainboard/google/veyron/romstage.c @@ -27,7 +27,6 @@ #include #include #include -#include #include #include #include diff --git a/src/mainboard/google/veyron_mickey/boardid.c b/src/mainboard/google/veyron_mickey/boardid.c index 3833dbedfc..9c53e374d8 100644 --- a/src/mainboard/google/veyron_mickey/boardid.c +++ b/src/mainboard/google/veyron_mickey/boardid.c @@ -16,7 +16,6 @@ #include #include #include -#include uint32_t board_id(void) { diff --git a/src/mainboard/google/veyron_mickey/romstage.c b/src/mainboard/google/veyron_mickey/romstage.c index c8a98428e9..d20bdb4c6d 100644 --- a/src/mainboard/google/veyron_mickey/romstage.c +++ b/src/mainboard/google/veyron_mickey/romstage.c @@ -27,7 +27,6 @@ #include #include #include -#include #include #include #include diff --git a/src/mainboard/google/veyron_rialto/boardid.c b/src/mainboard/google/veyron_rialto/boardid.c index 3833dbedfc..9c53e374d8 100644 --- a/src/mainboard/google/veyron_rialto/boardid.c +++ b/src/mainboard/google/veyron_rialto/boardid.c @@ -16,7 +16,6 @@ #include #include #include -#include uint32_t board_id(void) { diff --git a/src/mainboard/google/veyron_rialto/romstage.c b/src/mainboard/google/veyron_rialto/romstage.c index d9fc42b7e6..ac651ef1d9 100644 --- a/src/mainboard/google/veyron_rialto/romstage.c +++ b/src/mainboard/google/veyron_rialto/romstage.c @@ -27,7 +27,6 @@ #include #include #include -#include #include #include #include From c9ece506e08ed1b215c9fd78bb25260db197b85f Mon Sep 17 00:00:00 2001 From: Jonathan Zhang Date: Mon, 25 Nov 2019 12:41:15 -0800 Subject: [PATCH 0418/1242] pci_ids: Update Intel Lewisburg SMBUS PCI ID Change PCI_DEVICE_ID_INTEL_KBP_H_LWB_SMBUS to PCI_DEVICE_ID_INTEL_LWB_SMBUS. Ideally the abbreviation for Lewisburg should be LBG instead of LWB. However, LWB is used for consistency. Signed-off-by: Jonathan Zhang Signed-off-by: Anjaneya (Reddy) Chagam Change-Id: Ibc0cb6f2f7eb337180c2ae89015953a9aeaed68b Reviewed-on: https://review.coreboot.org/c/coreboot/+/37215 Reviewed-by: Angel Pons Reviewed-by: Maxim Polyakov Reviewed-by: David Hendricks Tested-by: build bot (Jenkins) --- src/include/device/pci_ids.h | 2 +- src/soc/intel/common/block/smbus/smbus.c | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/src/include/device/pci_ids.h b/src/include/device/pci_ids.h index c05640fe9c..0f96737f3b 100644 --- a/src/include/device/pci_ids.h +++ b/src/include/device/pci_ids.h @@ -3323,7 +3323,7 @@ /* Intel SMBUS device Ids */ #define PCI_DEVICE_ID_INTEL_SPT_LP_SMBUS 0x9d23 #define PCI_DEVICE_ID_INTEL_SPT_H_SMBUS 0xa123 -#define PCI_DEVICE_ID_INTEL_KBP_H_LWB_SMBUS 0xa1a3 +#define PCI_DEVICE_ID_INTEL_LWB_SMBUS 0xa1a3 #define PCI_DEVICE_ID_INTEL_LWB_SMBUS_SUPER 0xa223 #define PCI_DEVICE_ID_INTEL_CNL_SMBUS 0x9da3 #define PCI_DEVICE_ID_INTEL_CNP_H_SMBUS 0xa323 diff --git a/src/soc/intel/common/block/smbus/smbus.c b/src/soc/intel/common/block/smbus/smbus.c index 56f54d7d17..d7114e4356 100644 --- a/src/soc/intel/common/block/smbus/smbus.c +++ b/src/soc/intel/common/block/smbus/smbus.c @@ -92,7 +92,7 @@ static const unsigned short pci_device_ids[] = { PCI_DEVICE_ID_INTEL_SPT_LP_SMBUS, PCI_DEVICE_ID_INTEL_SPT_H_SMBUS, PCI_DEVICE_ID_INTEL_LWB_SMBUS_SUPER, - PCI_DEVICE_ID_INTEL_KBP_H_LWB_SMBUS, + PCI_DEVICE_ID_INTEL_LWB_SMBUS, PCI_DEVICE_ID_INTEL_ICP_LP_SMBUS, PCI_DEVICE_ID_INTEL_CMP_SMBUS, PCI_DEVICE_ID_INTEL_TGP_LP_SMBUS, From 5c44c4ac7d560b8f2a04317363952e8b84322e30 Mon Sep 17 00:00:00 2001 From: satya priya Date: Mon, 25 Nov 2019 15:10:08 +0530 Subject: [PATCH 0419/1242] libpayload: Add BIT(x) macro definition Add BIT(x) macro definition in libpayload. Change-Id: I15ca2d3758d516cecf9edd60af47e7fdbd808c40 Signed-off-by: satya priya Reviewed-on: https://review.coreboot.org/c/coreboot/+/37254 Tested-by: build bot (Jenkins) Reviewed-by: Julius Werner --- payloads/libpayload/include/libpayload.h | 1 + 1 file changed, 1 insertion(+) diff --git a/payloads/libpayload/include/libpayload.h b/payloads/libpayload/include/libpayload.h index 0bd5db8257..934c368e5c 100644 --- a/payloads/libpayload/include/libpayload.h +++ b/payloads/libpayload/include/libpayload.h @@ -85,6 +85,7 @@ #define MAX(a, b) __CMP(a, b, >) #define ARRAY_SIZE(a) (sizeof(a) / sizeof((a)[0])) +#define BIT(x) (1ul << (x)) #define DIV_ROUND_UP(x, y) ({ \ typeof(x) _div_local_x = (x); \ From 9f5c895ec7761f376724332cb61b9222562835e1 Mon Sep 17 00:00:00 2001 From: Arthur Heymans Date: Wed, 27 Nov 2019 08:20:57 +0100 Subject: [PATCH 0420/1242] mb/*/*/Kconfig: Drop redundant redeclaration of MAINBOARD_VENDOR Change-Id: Ic92e08ae5b741889a8200d10ea8148e4b4384dc8 Signed-off-by: Arthur Heymans Reviewed-on: https://review.coreboot.org/c/coreboot/+/37270 Reviewed-by: HAOUAS Elyes Reviewed-by: David Guckian Reviewed-by: Angel Pons Tested-by: build bot (Jenkins) --- src/mainboard/cavium/cn8100_sff_evb/Kconfig | 4 ---- src/mainboard/google/cheza/Kconfig | 4 ---- src/mainboard/google/cyan/Kconfig | 4 ---- src/mainboard/google/dragonegg/Kconfig | 4 ---- src/mainboard/google/drallion/Kconfig | 4 ---- src/mainboard/google/gru/Kconfig | 4 ---- src/mainboard/google/hatch/Kconfig | 4 ---- src/mainboard/google/mistral/Kconfig | 4 ---- src/mainboard/google/oak/Kconfig | 4 ---- src/mainboard/google/sarien/Kconfig | 4 ---- src/mainboard/google/trogdor/Kconfig | 4 ---- src/mainboard/google/veyron/Kconfig | 4 ---- src/mainboard/google/veyron_mickey/Kconfig | 4 ---- src/mainboard/google/veyron_rialto/Kconfig | 4 ---- src/mainboard/intel/apollolake_rvp/Kconfig | 4 ---- src/mainboard/intel/cannonlake_rvp/Kconfig | 4 ---- src/mainboard/intel/coffeelake_rvp/Kconfig | 4 ---- src/mainboard/intel/galileo/Kconfig | 4 ---- src/mainboard/intel/harcuvar/Kconfig | 4 ---- src/mainboard/intel/icelake_rvp/Kconfig | 4 ---- src/mainboard/intel/leafhill/Kconfig | 4 ---- src/mainboard/intel/strago/Kconfig | 4 ---- src/mainboard/kontron/ktqm77/Kconfig | 4 ---- src/mainboard/packardbell/ms2290/Kconfig | 4 ---- src/mainboard/purism/librem_bdw/Kconfig | 4 ---- src/mainboard/purism/librem_skl/Kconfig | 4 ---- src/mainboard/roda/rv11/Kconfig | 4 ---- src/mainboard/scaleway/tagada/Kconfig | 4 ---- src/mainboard/ti/beaglebone/Kconfig | 4 ---- 29 files changed, 116 deletions(-) diff --git a/src/mainboard/cavium/cn8100_sff_evb/Kconfig b/src/mainboard/cavium/cn8100_sff_evb/Kconfig index 0cb6f5a0b5..03e65f5de9 100644 --- a/src/mainboard/cavium/cn8100_sff_evb/Kconfig +++ b/src/mainboard/cavium/cn8100_sff_evb/Kconfig @@ -29,10 +29,6 @@ config MAINBOARD_DIR string default "cavium/cn8100_sff_evb" -config MAINBOARD_VENDOR - string - default "Cavium" - config DRAM_SIZE_MB int default 8192 diff --git a/src/mainboard/google/cheza/Kconfig b/src/mainboard/google/cheza/Kconfig index 30218ccb44..3f3f75607b 100644 --- a/src/mainboard/google/cheza/Kconfig +++ b/src/mainboard/google/cheza/Kconfig @@ -27,10 +27,6 @@ config MAINBOARD_DIR string default "google/cheza" -config MAINBOARD_VENDOR - string - default "Google" - config DRIVER_TPM_SPI_BUS hex default 0x5 diff --git a/src/mainboard/google/cyan/Kconfig b/src/mainboard/google/cyan/Kconfig index bb5ffb692a..6331419cd3 100644 --- a/src/mainboard/google/cyan/Kconfig +++ b/src/mainboard/google/cyan/Kconfig @@ -69,10 +69,6 @@ config MAINBOARD_PART_NUMBER default "Ultima" if BOARD_GOOGLE_ULTIMA default "Wizpig" if BOARD_GOOGLE_WIZPIG -config MAINBOARD_VENDOR - string - default "Google" - config DEVICETREE string default "variants/$(CONFIG_VARIANT_DIR)/devicetree.cb" diff --git a/src/mainboard/google/dragonegg/Kconfig b/src/mainboard/google/dragonegg/Kconfig index 1891cbe0ac..550d83a7df 100644 --- a/src/mainboard/google/dragonegg/Kconfig +++ b/src/mainboard/google/dragonegg/Kconfig @@ -46,10 +46,6 @@ config MAINBOARD_PART_NUMBER string default "Dragonegg" -config MAINBOARD_VENDOR - string - default "Google" - config MAINBOARD_FAMILY string default "Google_Dragonegg" diff --git a/src/mainboard/google/drallion/Kconfig b/src/mainboard/google/drallion/Kconfig index 256f8cbdae..accb9c8483 100644 --- a/src/mainboard/google/drallion/Kconfig +++ b/src/mainboard/google/drallion/Kconfig @@ -74,10 +74,6 @@ config MAINBOARD_PART_NUMBER default "Sarien_cml" if BOARD_GOOGLE_SARIEN_CML default "Drallion" if BOARD_GOOGLE_DRALLION -config MAINBOARD_VENDOR - string - default "Google" - config MAX_CPUS int default 8 diff --git a/src/mainboard/google/gru/Kconfig b/src/mainboard/google/gru/Kconfig index 72003e0d06..6cf165c395 100644 --- a/src/mainboard/google/gru/Kconfig +++ b/src/mainboard/google/gru/Kconfig @@ -69,10 +69,6 @@ config MAINBOARD_DIR string default "google/gru" -config MAINBOARD_VENDOR - string - default "Google" - config EC_GOOGLE_CHROMEEC_SPI_BUS hex default 0x5 diff --git a/src/mainboard/google/hatch/Kconfig b/src/mainboard/google/hatch/Kconfig index d6e6e46f18..fce1b875fe 100644 --- a/src/mainboard/google/hatch/Kconfig +++ b/src/mainboard/google/hatch/Kconfig @@ -97,10 +97,6 @@ config MAINBOARD_PART_NUMBER default "Kohaku" if BOARD_GOOGLE_KOHAKU default "Puff" if BOARD_GOOGLE_PUFF -config MAINBOARD_VENDOR - string - default "Google" - config MAX_CPUS int default 8 diff --git a/src/mainboard/google/mistral/Kconfig b/src/mainboard/google/mistral/Kconfig index 88e67097ba..b7d0d312a2 100644 --- a/src/mainboard/google/mistral/Kconfig +++ b/src/mainboard/google/mistral/Kconfig @@ -24,10 +24,6 @@ config MAINBOARD_DIR string default "google/mistral" -config MAINBOARD_VENDOR - string - default "Google" - ########################################################## #### Update below when adding a new derivative board. #### ########################################################## diff --git a/src/mainboard/google/oak/Kconfig b/src/mainboard/google/oak/Kconfig index 264f3711e3..dc12816d6c 100644 --- a/src/mainboard/google/oak/Kconfig +++ b/src/mainboard/google/oak/Kconfig @@ -52,10 +52,6 @@ config MAINBOARD_DIR string default "google/oak" -config MAINBOARD_VENDOR - string - default "Google" - config EC_GOOGLE_CHROMEEC_SPI_BUS hex default 0x0 diff --git a/src/mainboard/google/sarien/Kconfig b/src/mainboard/google/sarien/Kconfig index 455fbc205f..3cd49650d9 100644 --- a/src/mainboard/google/sarien/Kconfig +++ b/src/mainboard/google/sarien/Kconfig @@ -76,10 +76,6 @@ config MAINBOARD_PART_NUMBER default "Arcada" if BOARD_GOOGLE_ARCADA default "Sarien" if BOARD_GOOGLE_SARIEN -config MAINBOARD_VENDOR - string - default "Google" - config MAX_CPUS int default 8 diff --git a/src/mainboard/google/trogdor/Kconfig b/src/mainboard/google/trogdor/Kconfig index fba6b17667..27bd023169 100644 --- a/src/mainboard/google/trogdor/Kconfig +++ b/src/mainboard/google/trogdor/Kconfig @@ -27,10 +27,6 @@ config MAINBOARD_DIR string default "google/trogdor" -config MAINBOARD_VENDOR - string - default "Google" - config DRIVER_TPM_SPI_BUS hex default 0x5 diff --git a/src/mainboard/google/veyron/Kconfig b/src/mainboard/google/veyron/Kconfig index 5d1e616911..38c5c3b552 100644 --- a/src/mainboard/google/veyron/Kconfig +++ b/src/mainboard/google/veyron/Kconfig @@ -58,10 +58,6 @@ config MAINBOARD_PART_NUMBER default "Veyron_Speedy" if BOARD_GOOGLE_VEYRON_SPEEDY default "Veyron" -config MAINBOARD_VENDOR - string - default "Google" - config EC_GOOGLE_CHROMEEC_SPI_BUS hex default 0x0 diff --git a/src/mainboard/google/veyron_mickey/Kconfig b/src/mainboard/google/veyron_mickey/Kconfig index 5d15f0ec77..1bedab71d8 100644 --- a/src/mainboard/google/veyron_mickey/Kconfig +++ b/src/mainboard/google/veyron_mickey/Kconfig @@ -38,10 +38,6 @@ config MAINBOARD_PART_NUMBER string default "Veyron_Mickey" -config MAINBOARD_VENDOR - string - default "Google" - config BOOT_DEVICE_SPI_FLASH_BUS int default 2 diff --git a/src/mainboard/google/veyron_rialto/Kconfig b/src/mainboard/google/veyron_rialto/Kconfig index ac6f382054..5d4fab3182 100644 --- a/src/mainboard/google/veyron_rialto/Kconfig +++ b/src/mainboard/google/veyron_rialto/Kconfig @@ -38,10 +38,6 @@ config MAINBOARD_PART_NUMBER string default "Veyron_Rialto" -config MAINBOARD_VENDOR - string - default "Google" - config BOOT_DEVICE_SPI_FLASH_BUS int default 2 diff --git a/src/mainboard/intel/apollolake_rvp/Kconfig b/src/mainboard/intel/apollolake_rvp/Kconfig index 391ce1f494..dfd86eb3ea 100644 --- a/src/mainboard/intel/apollolake_rvp/Kconfig +++ b/src/mainboard/intel/apollolake_rvp/Kconfig @@ -15,10 +15,6 @@ config MAINBOARD_PART_NUMBER string default "Apollolake RVP" -config MAINBOARD_VENDOR - string - default "Intel" - config UART_FOR_CONSOLE default 2 endif diff --git a/src/mainboard/intel/cannonlake_rvp/Kconfig b/src/mainboard/intel/cannonlake_rvp/Kconfig index d86e48564f..133fe477f9 100644 --- a/src/mainboard/intel/cannonlake_rvp/Kconfig +++ b/src/mainboard/intel/cannonlake_rvp/Kconfig @@ -27,10 +27,6 @@ config MAINBOARD_PART_NUMBER string default "Cannonlake RVP" -config MAINBOARD_VENDOR - string - default "Intel" - config MAINBOARD_FAMILY string default "Intel_cannonlake_rvp" diff --git a/src/mainboard/intel/coffeelake_rvp/Kconfig b/src/mainboard/intel/coffeelake_rvp/Kconfig index 13e55b3f93..5ae567d326 100644 --- a/src/mainboard/intel/coffeelake_rvp/Kconfig +++ b/src/mainboard/intel/coffeelake_rvp/Kconfig @@ -35,10 +35,6 @@ config MAINBOARD_PART_NUMBER default "cmlrvp" if BOARD_INTEL_COMETLAKE_RVP default "cflrvp" -config MAINBOARD_VENDOR - string - default "Intel" - config MAINBOARD_FAMILY string default "Intel_whlrvp" if BOARD_INTEL_WHISKEYLAKE_RVP diff --git a/src/mainboard/intel/galileo/Kconfig b/src/mainboard/intel/galileo/Kconfig index 2e855da87a..4ea7f474e3 100644 --- a/src/mainboard/intel/galileo/Kconfig +++ b/src/mainboard/intel/galileo/Kconfig @@ -34,10 +34,6 @@ config MAINBOARD_PART_NUMBER string default "Galileo" -config MAINBOARD_VENDOR - string - default "Intel" - config GALILEO_GEN2 bool "Board generation: GEN1 (n) or GEN2 (y)" default y diff --git a/src/mainboard/intel/harcuvar/Kconfig b/src/mainboard/intel/harcuvar/Kconfig index e3cd86e8f7..271ff81892 100644 --- a/src/mainboard/intel/harcuvar/Kconfig +++ b/src/mainboard/intel/harcuvar/Kconfig @@ -29,10 +29,6 @@ config MAINBOARD_PART_NUMBER string default "Harcuvar CRB" -config MAINBOARD_VENDOR - string - default "Intel" - config ENABLE_FSP_MEMORY_DOWN bool "Enable Memory Down" default n diff --git a/src/mainboard/intel/icelake_rvp/Kconfig b/src/mainboard/intel/icelake_rvp/Kconfig index 728a532054..8331f1bd91 100644 --- a/src/mainboard/intel/icelake_rvp/Kconfig +++ b/src/mainboard/intel/icelake_rvp/Kconfig @@ -30,10 +30,6 @@ config MAINBOARD_PART_NUMBER string default "Icelake RVP" -config MAINBOARD_VENDOR - string - default "Intel" - config MAINBOARD_FAMILY string default "Intel_icelake_rvp" diff --git a/src/mainboard/intel/leafhill/Kconfig b/src/mainboard/intel/leafhill/Kconfig index 5832570b54..97758e192f 100644 --- a/src/mainboard/intel/leafhill/Kconfig +++ b/src/mainboard/intel/leafhill/Kconfig @@ -15,10 +15,6 @@ config MAINBOARD_PART_NUMBER string default "Leafhill" -config MAINBOARD_VENDOR - string - default "Intel" - config FMDFILE string default "src/mainboard/$(CONFIG_MAINBOARD_DIR)/leafhill.$(CONFIG_COREBOOT_ROMSIZE_KB).fmd" diff --git a/src/mainboard/intel/strago/Kconfig b/src/mainboard/intel/strago/Kconfig index 246add1895..5e710a52bf 100644 --- a/src/mainboard/intel/strago/Kconfig +++ b/src/mainboard/intel/strago/Kconfig @@ -30,10 +30,6 @@ config MAINBOARD_PART_NUMBER string default "Strago" -config MAINBOARD_VENDOR - string - default "Intel" - config VGA_BIOS_FILE string depends on VGA_BIOS diff --git a/src/mainboard/kontron/ktqm77/Kconfig b/src/mainboard/kontron/ktqm77/Kconfig index 1cefa599b4..77775e6b8e 100644 --- a/src/mainboard/kontron/ktqm77/Kconfig +++ b/src/mainboard/kontron/ktqm77/Kconfig @@ -31,8 +31,4 @@ config VGA_BIOS_FILE string default "pci8086,0166.rom" -config MAINBOARD_VENDOR - string - default "Kontron" - endif # BOARD_KONTRON_KTQM77 diff --git a/src/mainboard/packardbell/ms2290/Kconfig b/src/mainboard/packardbell/ms2290/Kconfig index 6a613849ea..819400257b 100644 --- a/src/mainboard/packardbell/ms2290/Kconfig +++ b/src/mainboard/packardbell/ms2290/Kconfig @@ -26,10 +26,6 @@ config MAINBOARD_VERSION string default "V1.20" -config MAINBOARD_VENDOR - string - default "Packard Bell" - config USBDEBUG_HCD_INDEX int default 2 diff --git a/src/mainboard/purism/librem_bdw/Kconfig b/src/mainboard/purism/librem_bdw/Kconfig index 466e03ec7a..7a8bc22459 100644 --- a/src/mainboard/purism/librem_bdw/Kconfig +++ b/src/mainboard/purism/librem_bdw/Kconfig @@ -42,10 +42,6 @@ config MAINBOARD_DIR string default "purism/librem_bdw" -config MAINBOARD_VENDOR - string - default "Purism" - config MAINBOARD_PART_NUMBER string default "Librem 13 v1" if BOARD_PURISM_LIBREM13_V1 diff --git a/src/mainboard/purism/librem_skl/Kconfig b/src/mainboard/purism/librem_skl/Kconfig index 05fd43d2de..ca1582a50c 100644 --- a/src/mainboard/purism/librem_skl/Kconfig +++ b/src/mainboard/purism/librem_skl/Kconfig @@ -23,10 +23,6 @@ config VARIANT_DIR default "librem13v2" if BOARD_PURISM_LIBREM13_V2 || BOARD_PURISM_LIBREM13_V4 default "librem15v3" if BOARD_PURISM_LIBREM15_V3 || BOARD_PURISM_LIBREM15_V4 -config MAINBOARD_VENDOR - string - default "Purism" - config MAINBOARD_FAMILY string default "Librem 13" if BOARD_PURISM_LIBREM13_V2 || BOARD_PURISM_LIBREM13_V4 diff --git a/src/mainboard/roda/rv11/Kconfig b/src/mainboard/roda/rv11/Kconfig index 54f04c406e..70c383fc55 100644 --- a/src/mainboard/roda/rv11/Kconfig +++ b/src/mainboard/roda/rv11/Kconfig @@ -37,8 +37,4 @@ config MAX_CPUS int default 8 -config MAINBOARD_VENDOR - string - default "Roda" - endif # BOARD_RODA_RV11 || BOARD_RODA_RW11 diff --git a/src/mainboard/scaleway/tagada/Kconfig b/src/mainboard/scaleway/tagada/Kconfig index 25cb7e13d7..21088cbb00 100644 --- a/src/mainboard/scaleway/tagada/Kconfig +++ b/src/mainboard/scaleway/tagada/Kconfig @@ -32,10 +32,6 @@ config MAINBOARD_PART_NUMBER string default "TAGADA" -config MAINBOARD_VENDOR - string - default "Scaleway" - config BMC_INFO_LOC hex "BMC information location in flash" default 0xff802000 diff --git a/src/mainboard/ti/beaglebone/Kconfig b/src/mainboard/ti/beaglebone/Kconfig index 70096229b9..e4075d0d62 100644 --- a/src/mainboard/ti/beaglebone/Kconfig +++ b/src/mainboard/ti/beaglebone/Kconfig @@ -33,10 +33,6 @@ config MAX_CPUS int default 1 -config MAINBOARD_VENDOR - string - default "TI" - config DRAM_SIZE_MB int default 256 From c9eae795d1595e37fcb955b5d4c923d59ba5f210 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ky=C3=B6sti=20M=C3=A4lkki?= Date: Wed, 27 Nov 2019 07:45:27 +0200 Subject: [PATCH 0421/1242] soc/amd/common: Fix indirect includes MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Builds that would otherwise be reproducible are sometimes broken due to added #include combined with __LINE__ used in assert() statement. Change-Id: If4a02393799a34bbae4f6e506052774526c1a969 Signed-off-by: Kyösti Mälkki Reviewed-on: https://review.coreboot.org/c/coreboot/+/37266 Reviewed-by: Richard Spiegel Reviewed-by: Arthur Heymans Tested-by: build bot (Jenkins) --- .../kahlee/variants/baseboard/include/baseboard/acpi/audio.asl | 3 ++- src/soc/amd/common/block/gpio_banks/gpio.c | 1 + src/soc/amd/common/block/include/amdblocks/gpio_banks.h | 1 + src/soc/amd/picasso/acpi/sb_fch.asl | 1 + src/soc/amd/stoneyridge/acpi/sb_fch.asl | 1 + 5 files changed, 6 insertions(+), 1 deletion(-) diff --git a/src/mainboard/google/kahlee/variants/baseboard/include/baseboard/acpi/audio.asl b/src/mainboard/google/kahlee/variants/baseboard/include/baseboard/acpi/audio.asl index 87890daf36..01942dcbd3 100644 --- a/src/mainboard/google/kahlee/variants/baseboard/include/baseboard/acpi/audio.asl +++ b/src/mainboard/google/kahlee/variants/baseboard/include/baseboard/acpi/audio.asl @@ -12,7 +12,8 @@ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. */ -#include + +#include /* Grunt specific I2S machine driver */ Device (I2S) diff --git a/src/soc/amd/common/block/gpio_banks/gpio.c b/src/soc/amd/common/block/gpio_banks/gpio.c index 17e3de09e3..76c2021578 100644 --- a/src/soc/amd/common/block/gpio_banks/gpio.c +++ b/src/soc/amd/common/block/gpio_banks/gpio.c @@ -20,6 +20,7 @@ #include #include #include +#include #include #include #include diff --git a/src/soc/amd/common/block/include/amdblocks/gpio_banks.h b/src/soc/amd/common/block/include/amdblocks/gpio_banks.h index 6427cb696e..2206e35ff2 100644 --- a/src/soc/amd/common/block/include/amdblocks/gpio_banks.h +++ b/src/soc/amd/common/block/include/amdblocks/gpio_banks.h @@ -18,6 +18,7 @@ #include #include +#include struct soc_amd_gpio { uint8_t gpio; diff --git a/src/soc/amd/picasso/acpi/sb_fch.asl b/src/soc/amd/picasso/acpi/sb_fch.asl index 680f496611..ca8d175c61 100644 --- a/src/soc/amd/picasso/acpi/sb_fch.asl +++ b/src/soc/amd/picasso/acpi/sb_fch.asl @@ -15,6 +15,7 @@ #include #include +#include Device (AAHB) { diff --git a/src/soc/amd/stoneyridge/acpi/sb_fch.asl b/src/soc/amd/stoneyridge/acpi/sb_fch.asl index e7975f8d94..897c9ec905 100644 --- a/src/soc/amd/stoneyridge/acpi/sb_fch.asl +++ b/src/soc/amd/stoneyridge/acpi/sb_fch.asl @@ -15,6 +15,7 @@ #include #include +#include Device (AAHB) { From c2a05d143bb87db9177494d3752b4ee2b04cc144 Mon Sep 17 00:00:00 2001 From: Maulik V Vaghela Date: Wed, 27 Nov 2019 14:31:38 +0530 Subject: [PATCH 0422/1242] soc/intel/tigerlake: select correct chipset based on soc Kconfig Since we accomodate both Tigerlake and Jasperlake soc in single folder, we need to select IFD chipset correctly based on soc. Change-Id: I73cfe4f583da3a28c3b29d29a93ff62097130e27 Signed-off-by: Maulik V Vaghela Reviewed-on: https://review.coreboot.org/c/coreboot/+/37273 Tested-by: build bot (Jenkins) Reviewed-by: Subrata Banik Reviewed-by: Aamir Bohra --- src/soc/intel/tigerlake/Kconfig | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/src/soc/intel/tigerlake/Kconfig b/src/soc/intel/tigerlake/Kconfig index d76771025a..652c3a30c6 100644 --- a/src/soc/intel/tigerlake/Kconfig +++ b/src/soc/intel/tigerlake/Kconfig @@ -97,7 +97,8 @@ config FSP_TEMP_RAM_SIZE config IFD_CHIPSET string - default "tgl" + default "tgl" if SOC_INTEL_TIGERLAKE + default "jsl" if SOC_INTEL_JASPERLAKE config IED_REGION_SIZE hex From b6e36181380b711976d37a490fe2ada96fc4d440 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ky=C3=B6sti=20M=C3=A4lkki?= Date: Mon, 25 Nov 2019 19:41:58 +0200 Subject: [PATCH 0423/1242] soc/amd/common: Remove guards on ACPIMMIO utils MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit If one wishes to use the functions guarded here, he has to have datasheet open anyways. It should be clear from there which regions are supported and which are not. TEST=Reproducible build of google/aleena. Change-Id: I0c1f0c9c9a6711532c5078c08cdf9e6612f3bc9c Signed-off-by: Kyösti Mälkki Reviewed-on: https://review.coreboot.org/c/coreboot/+/37210 Tested-by: build bot (Jenkins) Reviewed-by: Michał Żygowski --- src/soc/amd/common/block/acpimmio/mmio_util.c | 84 ------------------- .../common/block/include/amdblocks/acpimmio.h | 65 -------------- src/soc/amd/picasso/include/soc/iomap.h | 20 ----- src/soc/amd/stoneyridge/include/soc/iomap.h | 20 ----- 4 files changed, 189 deletions(-) diff --git a/src/soc/amd/common/block/acpimmio/mmio_util.c b/src/soc/amd/common/block/acpimmio/mmio_util.c index 7fad456106..1fc5fd4ed4 100644 --- a/src/soc/amd/common/block/acpimmio/mmio_util.c +++ b/src/soc/amd/common/block/acpimmio/mmio_util.c @@ -65,9 +65,6 @@ void pm_io_write32(uint8_t reg, uint32_t value) pm_io_write16(reg + sizeof(uint16_t), value & 0xffff); } -#if SUPPORTS_ACPIMMIO_SM_PCI_BASE -/* smbus pci read/write - access registers at 0xfed80000 */ - u8 sm_pci_read8(u8 reg) { return read8((void *)(ACPIMMIO_SM_PCI_BASE + reg)); @@ -97,10 +94,6 @@ void sm_pci_write32(u8 reg, u32 value) { write32((void *)(ACPIMMIO_SM_PCI_BASE + reg), value); } -#endif - -#if SUPPORTS_ACPIMMIO_SMI_BASE -/* smi read/write - access registers at 0xfed80200 */ uint8_t smi_read8(uint8_t reg) { @@ -131,10 +124,6 @@ void smi_write32(uint8_t reg, uint32_t value) { write32((void *)(ACPIMMIO_SMI_BASE + reg), value); } -#endif /* SUPPORTS_ACPIMMIO_SMI_BASE */ - -#if SUPPORTS_ACPIMMIO_PMIO_BASE -/* pm read/write - access registers at 0xfed80300 */ u8 pm_read8(u8 reg) { @@ -165,14 +154,6 @@ void pm_write32(u8 reg, u32 value) { write32((void *)(ACPIMMIO_PMIO_BASE + reg), value); } -#endif /* SUPPORTS_ACPIMMIO_PMIO_BASE */ - -#if SUPPORTS_ACPIMMIO_PMIO2_BASE -/* pm2 read/write - access registers at 0xfed80400 - currently unused by any soc */ -#endif - -#if SUPPORTS_ACPIMMIO_BIOSRAM_BASE -/* biosram read/write - access registers at 0xfed80500 */ uint8_t biosram_read8(uint8_t reg) { @@ -208,18 +189,6 @@ void biosram_write32(uint8_t reg, uint32_t value) value >>= 16; biosram_write16(reg + sizeof(uint16_t), value & 0xffff); } -#endif /* SUPPORTS_ACPIMMIO_BIOSRAM_BASE */ - -#if SUPPORTS_ACPIMMIO_CMOSRAM_BASE -/* cmosram read/write - access registers at 0xfed80600 - currently unused by any soc */ -#endif - -#if SUPPORTS_ACPIMMIO_CMOS_BASE -/* cmos read/write - access registers at 0xfed80700 - currently unused by any soc */ -#endif - -#if SUPPORTS_ACPIMMIO_ACPI_BASE -/* acpi read/write - access registers at 0xfed80800 */ u8 acpi_read8(u8 reg) { @@ -250,10 +219,6 @@ void acpi_write32(u8 reg, u32 value) { write32((void *)(ACPIMMIO_ACPI_BASE + reg), value); } -#endif /* SUPPORTS_ACPIMMIO_ACPI_BASE */ - -#if SUPPORTS_ACPIMMIO_ASF_BASE -/* asf read/write - access registers at 0xfed80900 */ u8 asf_read8(u8 reg) { @@ -274,10 +239,6 @@ void asf_write16(u8 reg, u16 value) { write16((void *)(ACPIMMIO_ASF_BASE + reg), value); } -#endif /* SUPPORTS_ACPIMMIO_ASF_BASE */ - -#if SUPPORTS_ACPIMMIO_SMBUS_BASE -/* smbus read/write - access registers at 0xfed80a00 */ u8 smbus_read8(u8 reg) { @@ -298,18 +259,6 @@ void smbus_write16(u8 reg, u16 value) { write16((void *)(ACPIMMIO_SMBUS_BASE + reg), value); } -#endif /* SUPPORTS_ACPIMMIO_SMBUS_BASE */ - -#if SUPPORTS_ACPIMMIO_WDT_BASE -/* wdt read/write - access registers at 0xfed80b00 - not currently used by any soc */ -#endif - -#if SUPPORTS_ACPIMMIO_HPET_BASE -/* hpet read/write - access registers at 0xfed80c00 - not currently used by any soc */ -#endif - -#if SUPPORTS_ACPIMMIO_IOMUX_BASE -/* iomux read/write - access registers at 0xfed80d00 */ u8 iomux_read8(u8 reg) { @@ -340,10 +289,6 @@ void iomux_write32(u8 reg, u32 value) { write32((void *)(ACPIMMIO_IOMUX_BASE + reg), value); } -#endif /* SUPPORTS_ACPIMMIO_IOMUX_BASE */ - -#if SUPPORTS_ACPIMMIO_MISC_BASE -/* misc read/write - access registers at 0xfed80e00 */ u8 misc_read8(u8 reg) { @@ -374,26 +319,6 @@ void misc_write32(u8 reg, u32 value) { write32((void *)(ACPIMMIO_MISC_BASE + reg), value); } -#endif /* SUPPORTS_ACPIMMIO_MISC_BASE */ - -#if SUPPORTS_ACPIMMIO_DPVGA_BASE -/* dpvga read/write - access registers at 0xfed81400 - not currently used by any soc */ -#endif - -#if SUPPORTS_ACPIMMIO_GPIO0_BASE || SUPPORTS_ACPIMMIO_GPIO1_BASE \ - || SUPPORTS_ACPIMMIO_GPIO2_BASE -/* - * No helpers are currently in use however common/block//gpio.c accesses - * the registers directly. - */ - -/* gpio bk 0 read/write - access registers at 0xfed81500 */ -/* gpio bk 1 read/write - access registers at 0xfed81600 */ -/* gpio bk 2 read/write - access registers at 0xfed81700 */ -#endif - -#if SUPPORTS_ACPIMMIO_XHCIPM_BASE -/* xhci_pm read/write - access registers at 0xfed81c00 */ uint8_t xhci_pm_read8(uint8_t reg) { @@ -424,14 +349,6 @@ void xhci_pm_write32(uint8_t reg, uint32_t value) { write32((void *)(ACPIMMIO_XHCIPM_BASE + reg), value); } -#endif /* SUPPORTS_ACPIMMIO_XHCIPM_BASE */ - -#if SUPPORTS_ACPIMMIO_ACDCTMR_BASE -/* acdc_tmr read/write - access registers at 0xfed81d00 - not currently used by any soc */ -#endif - -#if SUPPORTS_ACPIMMIO_AOAC_BASE -/* aoac read/write - access registers at 0xfed81e00 */ u8 aoac_read8(u8 reg) { @@ -442,4 +359,3 @@ void aoac_write8(u8 reg, u8 value) { write8((void *)(ACPIMMIO_AOAC_BASE + reg), value); } -#endif /* SUPPORTS_ACPIMMIO_AOAC_BASE */ diff --git a/src/soc/amd/common/block/include/amdblocks/acpimmio.h b/src/soc/amd/common/block/include/amdblocks/acpimmio.h index ca57cf5dcc..b395cdba9c 100644 --- a/src/soc/amd/common/block/include/amdblocks/acpimmio.h +++ b/src/soc/amd/common/block/include/amdblocks/acpimmio.h @@ -19,71 +19,6 @@ #define __AMDBLOCKS_ACPIMMIO_H__ #include -/* iomap.h must indicate if the device uses a block, optional if unused. */ -#include -#ifndef SUPPORTS_ACPIMMIO_SM_PCI_BASE - #define SUPPORTS_ACPIMMIO_SM_PCI_BASE 0 -#endif -#ifndef SUPPORTS_ACPIMMIO_SMI_BASE - #define SUPPORTS_ACPIMMIO_SMI_BASE 0 -#endif -#ifndef SUPPORTS_ACPIMMIO_PMIO_BASE - #define SUPPORTS_ACPIMMIO_PMIO_BASE 0 -#endif -#ifndef SUPPORTS_ACPIMMIO_PMIO2_BASE - #define SUPPORTS_ACPIMMIO_PMIO2_BASE 0 -#endif -#ifndef SUPPORTS_ACPIMMIO_BIOSRAM_BASE - #define SUPPORTS_ACPIMMIO_BIOSRAM_BASE 0 -#endif -#ifndef SUPPORTS_ACPIMMIO_CMOSRAM_BASE - #define SUPPORTS_ACPIMMIO_CMOSRAM_BASE 0 -#endif -#ifndef SUPPORTS_ACPIMMIO_CMOS_BASE - #define SUPPORTS_ACPIMMIO_CMOS_BASE 0 -#endif -#ifndef SUPPORTS_ACPIMMIO_ACPI_BASE - #define SUPPORTS_ACPIMMIO_ACPI_BASE 0 -#endif -#ifndef SUPPORTS_ACPIMMIO_ASF_BASE - #define SUPPORTS_ACPIMMIO_ASF_BASE 0 -#endif -#ifndef SUPPORTS_ACPIMMIO_SMBUS_BASE - #define SUPPORTS_ACPIMMIO_SMBUS_BASE 0 -#endif -#ifndef SUPPORTS_ACPIMMIO_WDT_BASE - #define SUPPORTS_ACPIMMIO_WDT_BASE 0 -#endif -#ifndef SUPPORTS_ACPIMMIO_HPET_BASE - #define SUPPORTS_ACPIMMIO_HPET_BASE 0 -#endif -#ifndef SUPPORTS_ACPIMMIO_IOMUX_BASE - #define SUPPORTS_ACPIMMIO_IOMUX_BASE 0 -#endif -#ifndef SUPPORTS_ACPIMMIO_MISC_BASE - #define SUPPORTS_ACPIMMIO_MISC_BASE 0 -#endif -#ifndef SUPPORTS_ACPIMMIO_DPVGA_BASE - #define SUPPORTS_ACPIMMIO_DPVGA_BASE 0 -#endif -#ifndef SUPPORTS_ACPIMMIO_GPIO0_BASE - #define SUPPORTS_ACPIMMIO_GPIO0_BASE 0 -#endif -#ifndef SUPPORTS_ACPIMMIO_GPIO1_BASE - #define SUPPORTS_ACPIMMIO_GPIO1_BASE 0 -#endif -#ifndef SUPPORTS_ACPIMMIO_GPIO2_BASE - #define SUPPORTS_ACPIMMIO_GPIO2_BASE 0 -#endif -#ifndef SUPPORTS_ACPIMMIO_XHCIPM_BASE - #define SUPPORTS_ACPIMMIO_XHCIPM_BASE 0 -#endif -#ifndef SUPPORTS_ACPIMMIO_ACDCTMR_BASE - #define SUPPORTS_ACPIMMIO_ACDCTMR_BASE 0 -#endif -#ifndef SUPPORTS_ACPIMMIO_AOAC_BASE - #define SUPPORTS_ACPIMMIO_AOAC_BASE 0 -#endif /* * The following AcpiMmio register block mapping represents definitions diff --git a/src/soc/amd/picasso/include/soc/iomap.h b/src/soc/amd/picasso/include/soc/iomap.h index 5037a1c2c5..b1d4bff48c 100644 --- a/src/soc/amd/picasso/include/soc/iomap.h +++ b/src/soc/amd/picasso/include/soc/iomap.h @@ -27,26 +27,6 @@ #endif #define HPET_BASE_ADDRESS 0xfed00000 -/* - * AcpiMmio blocks are at fixed offsets from FED8_0000h and enabled in PMx04[1]. - * All ranges not specified as supported below may, or may not, be listed in - * any documentation but should be considered reserved through FED8_1FFFh. - */ -#include -#define SUPPORTS_ACPIMMIO_SM_PCI_BASE 1 /* 0xfed80000 */ -#define SUPPORTS_ACPIMMIO_SMI_BASE 1 /* 0xfed80100 */ -#define SUPPORTS_ACPIMMIO_PMIO_BASE 1 /* 0xfed80300 */ -#define SUPPORTS_ACPIMMIO_BIOSRAM_BASE 1 /* 0xfed80500 */ -#define SUPPORTS_ACPIMMIO_ACPI_BASE 1 /* 0xfed80800 */ -#define SUPPORTS_ACPIMMIO_ASF_BASE 1 /* 0xfed80900 */ -#define SUPPORTS_ACPIMMIO_SMBUS_BASE 1 /* 0xfed80a00 */ -#define SUPPORTS_ACPIMMIO_IOMUX_BASE 1 /* 0xfed80d00 */ -#define SUPPORTS_ACPIMMIO_MISC_BASE 1 /* 0xfed80e00 */ -#define SUPPORTS_ACPIMMIO_GPIO0_BASE 1 /* 0xfed81500 */ -#define SUPPORTS_ACPIMMIO_GPIO1_BASE 1 /* 0xfed81800 */ -#define SUPPORTS_ACPIMMIO_GPIO2_BASE 1 /* 0xfed81700 */ -#define SUPPORTS_ACPIMMIO_AOAC_BASE 1 /* 0xfed81e00 */ - #define ALINK_AHB_ADDRESS 0xfedc0000 /* Reserved 0xfecd1000-0xfedc3fff */ diff --git a/src/soc/amd/stoneyridge/include/soc/iomap.h b/src/soc/amd/stoneyridge/include/soc/iomap.h index 612b6e871b..02997cc777 100644 --- a/src/soc/amd/stoneyridge/include/soc/iomap.h +++ b/src/soc/amd/stoneyridge/include/soc/iomap.h @@ -22,26 +22,6 @@ #define SPI_BASE_ADDRESS 0xfec10000 #define IO_APIC2_ADDR 0xfec20000 -/* - * AcpiMmio blocks are at fixed offsets from FED8_0000h and enabled in PMx04[1]. - * All ranges not specified as supported below may, or may not, be listed in - * any documentation but should be considered reserved through FED8_1FFFh. - */ -#include -#define SUPPORTS_ACPIMMIO_SMI_BASE 1 /* 0xfed80100 */ -#define SUPPORTS_ACPIMMIO_PMIO_BASE 1 /* 0xfed80300 */ -#define SUPPORTS_ACPIMMIO_BIOSRAM_BASE 1 /* 0xfed80500 */ -#define SUPPORTS_ACPIMMIO_ACPI_BASE 1 /* 0xfed80800 */ -#define SUPPORTS_ACPIMMIO_ASF_BASE 1 /* 0xfed80900 */ -#define SUPPORTS_ACPIMMIO_SMBUS_BASE 1 /* 0xfed80a00 */ -#define SUPPORTS_ACPIMMIO_IOMUX_BASE 1 /* 0xfed80d00 */ -#define SUPPORTS_ACPIMMIO_MISC_BASE 1 /* 0xfed80e00 */ -#define SUPPORTS_ACPIMMIO_GPIO0_BASE 1 /* 0xfed81500 */ -#define SUPPORTS_ACPIMMIO_GPIO1_BASE 1 /* 0xfed81800 */ -#define SUPPORTS_ACPIMMIO_GPIO2_BASE 1 /* 0xfed81700 */ -#define SUPPORTS_ACPIMMIO_XHCIPM_BASE 1 /* 0xfed81c00 */ -#define SUPPORTS_ACPIMMIO_AOAC_BASE 1 /* 0xfed81e00 */ - #define ALINK_AHB_ADDRESS 0xfedc0000 /* I2C fixed address */ From 30da30c1db3375bfb582afca36e43c2e1669b8df Mon Sep 17 00:00:00 2001 From: Peter Lemenkov Date: Wed, 27 Nov 2019 15:58:21 +0100 Subject: [PATCH 0424/1242] mb/lenovo/t400/Kconfig: Remove default data.vbt path Change-Id: Ib720d9ca57cf1ce640f168cd6aab654b53e92b82 Signed-off-by: Peter Lemenkov Reviewed-on: https://review.coreboot.org/c/coreboot/+/37286 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber --- src/mainboard/lenovo/t400/Kconfig | 3 --- 1 file changed, 3 deletions(-) diff --git a/src/mainboard/lenovo/t400/Kconfig b/src/mainboard/lenovo/t400/Kconfig index 9355540713..deb6c8e4bd 100644 --- a/src/mainboard/lenovo/t400/Kconfig +++ b/src/mainboard/lenovo/t400/Kconfig @@ -79,7 +79,4 @@ config CBFS_SIZE hex default 0x200000 -config INTEL_GMA_VBT_FILE - default "src/mainboard/$(MAINBOARDDIR)/variants/$(VARIANT_DIR)/data.vbt" - endif # BOARD_LENOVO_T400 From bf5aacca2c8c74510613741ea7eaeef602ea0679 Mon Sep 17 00:00:00 2001 From: Peter Lemenkov Date: Wed, 27 Nov 2019 15:59:39 +0100 Subject: [PATCH 0425/1242] mb/lenovo/t400/Makefile: Build gpio w/o subdir makefiles Change-Id: Ia2e889fe72d746b71d92026e358c7471f56b381f Signed-off-by: Peter Lemenkov Reviewed-on: https://review.coreboot.org/c/coreboot/+/37287 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber --- src/mainboard/lenovo/t400/Makefile.inc | 2 +- src/mainboard/lenovo/t400/variants/r500/Makefile.inc | 1 - src/mainboard/lenovo/t400/variants/t400/Makefile.inc | 1 - 3 files changed, 1 insertion(+), 3 deletions(-) delete mode 100644 src/mainboard/lenovo/t400/variants/r500/Makefile.inc delete mode 100644 src/mainboard/lenovo/t400/variants/t400/Makefile.inc diff --git a/src/mainboard/lenovo/t400/Makefile.inc b/src/mainboard/lenovo/t400/Makefile.inc index b3ca78d2de..e4e6a1f012 100644 --- a/src/mainboard/lenovo/t400/Makefile.inc +++ b/src/mainboard/lenovo/t400/Makefile.inc @@ -16,7 +16,7 @@ bootblock-y += bootblock.c bootblock-y += dock.c -subdirs-y += variants/$(VARIANT_DIR)/ +romstage-y += variants/$(VARIANT_DIR)/gpio.c ramstage-y += dock.c ramstage-y += cstates.c diff --git a/src/mainboard/lenovo/t400/variants/r500/Makefile.inc b/src/mainboard/lenovo/t400/variants/r500/Makefile.inc deleted file mode 100644 index 3dae61e8a8..0000000000 --- a/src/mainboard/lenovo/t400/variants/r500/Makefile.inc +++ /dev/null @@ -1 +0,0 @@ -romstage-y += gpio.c diff --git a/src/mainboard/lenovo/t400/variants/t400/Makefile.inc b/src/mainboard/lenovo/t400/variants/t400/Makefile.inc deleted file mode 100644 index 3dae61e8a8..0000000000 --- a/src/mainboard/lenovo/t400/variants/t400/Makefile.inc +++ /dev/null @@ -1 +0,0 @@ -romstage-y += gpio.c From ed50d85576adf8e653efa3511ab62b6d28fd83f9 Mon Sep 17 00:00:00 2001 From: Arthur Heymans Date: Wed, 26 Dec 2018 11:20:59 +0100 Subject: [PATCH 0426/1242] drivers/smmstore: Fix some issues This fixes the following: - Fix smmstore_read_region to actually read stuff - Clean up the code a little - Change the loglevel for non error messages to BIOS_DEBUG - Use an incoherent rdev to potentially speed up reading access TESTED on google/wolf with out of tree patch to hook up smmstore to sb/intel/lynxpoint. Change-Id: I629be25d2a9b65796ae8f7a700b6bdab57b91b22 Signed-off-by: Arthur Heymans Reviewed-on: https://review.coreboot.org/c/coreboot/+/30432 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi --- src/drivers/smmstore/store.c | 168 ++++++++++++++++++++++------------- 1 file changed, 104 insertions(+), 64 deletions(-) diff --git a/src/drivers/smmstore/store.c b/src/drivers/smmstore/store.c index dc4a0cf75b..23d2af015f 100644 --- a/src/drivers/smmstore/store.c +++ b/src/drivers/smmstore/store.c @@ -43,6 +43,33 @@ * crash/reboot could clear out all variables. */ +static enum cb_err lookup_store_region(struct region *region) +{ + if (CONFIG(SMMSTORE_IN_CBFS)) { + struct cbfsf file; + if (cbfs_locate_file_in_region(&file, + CONFIG_SMMSTORE_REGION, + CONFIG_SMMSTORE_FILENAME, NULL) < 0) { + printk(BIOS_WARNING, + "smm store: Unable to find SMM store file in region '%s'\n", + CONFIG_SMMSTORE_REGION); + return CB_ERR; + } + struct region_device rdev; + cbfs_file_data(&rdev, &file); + *region = *region_device_region(&rdev); + } else { + if (fmap_locate_area(CONFIG_SMMSTORE_REGION, region)) { + printk(BIOS_WARNING, + "smm store: Unable to find SMM store FMAP region '%s'\n", + CONFIG_SMMSTORE_REGION); + return CB_ERR; + } + } + + return CB_SUCCESS; +} + /* * Return a region device that points into the store file. * @@ -57,28 +84,26 @@ */ static int lookup_store(struct region_device *rstore) { - struct cbfsf file; - if (CONFIG(SMMSTORE_IN_CBFS)) { - if (cbfs_locate_file_in_region(&file, - CONFIG_SMMSTORE_REGION, - CONFIG_SMMSTORE_FILENAME, NULL) < 0) { - printk(BIOS_WARNING, "smm store: " - "Unable to find SMM store file in region '%s'\n", - CONFIG_SMMSTORE_REGION); - return -1; - } + static struct region_device read_rdev, write_rdev; + static struct incoherent_rdev store_irdev; + struct region region; + const struct region_device *rdev; - cbfs_file_data(rstore, &file); - } else { - if (fmap_locate_area_as_rdev_rw(CONFIG_SMMSTORE_REGION, rstore)) { - printk(BIOS_WARNING, - "smm store: Unable to find SMM store FMAP region '%s'\n", - CONFIG_SMMSTORE_REGION); - return -1; - } - } + if (lookup_store_region(®ion) != CB_SUCCESS) + return -1; - return 0; + if (boot_device_ro_subregion(®ion, &read_rdev) < 0) + return -1; + + if (boot_device_rw_subregion(®ion, &write_rdev) < 0) + return -1; + + rdev = incoherent_rdev_init(&store_irdev, ®ion, &read_rdev, &write_rdev); + + if (rdev == NULL) + return -1; + + return rdev_chain(rstore, rdev, 0, region_device_sz(rdev)); } /* @@ -94,13 +119,12 @@ int smmstore_read_region(void *buf, ssize_t *bufsize) if (bufsize == NULL) return -1; - *bufsize = 0; if (lookup_store(&store) < 0) { printk(BIOS_WARNING, "reading region failed\n"); return -1; } - ssize_t tx = min(*bufsize, region_device_sz(&store)); + ssize_t tx = MIN(*bufsize, region_device_sz(&store)); *bufsize = rdev_readat(&store, buf, 0, tx); if (*bufsize < 0) @@ -109,33 +133,19 @@ int smmstore_read_region(void *buf, ssize_t *bufsize) return 0; } -/* - * Append data to region - * - * Returns 0 on success, -1 on failure - */ -int smmstore_append_data(void *key, uint32_t key_sz, - void *value, uint32_t value_sz) +static enum cb_err scan_end(struct region_device *store) { - struct region_device store; - - if (lookup_store(&store) < 0) { - printk(BIOS_WARNING, "reading region failed\n"); - return -1; - } - - ssize_t data_sz = region_device_sz(&store); - /* scan for end */ ssize_t end = 0; uint32_t k_sz, v_sz; + const ssize_t data_sz = region_device_sz(store); while (end < data_sz) { /* make odd corner cases identifiable, eg. invalid v_sz */ k_sz = 0; - if (rdev_readat(&store, &k_sz, end, sizeof(k_sz)) < 0) { + if (rdev_readat(store, &k_sz, end, sizeof(k_sz)) < 0) { printk(BIOS_WARNING, "failed reading key size\n"); - return -1; + return CB_ERR; } /* found the end */ @@ -148,65 +158,95 @@ int smmstore_append_data(void *key, uint32_t key_sz, */ if (k_sz > data_sz) { printk(BIOS_WARNING, "key size out of bounds\n"); - return -1; + return CB_ERR; } - if (rdev_readat(&store, &v_sz, end + 4, sizeof(v_sz)) < 0) { + if (rdev_readat(store, &v_sz, end + sizeof(k_sz), sizeof(v_sz)) < 0) { printk(BIOS_WARNING, "failed reading value size\n"); - return -1; + return CB_ERR; } if (v_sz > data_sz) { printk(BIOS_WARNING, "value size out of bounds\n"); - return -1; + return CB_ERR; } - end += 8 + k_sz + v_sz + 1; + end += sizeof(k_sz) + sizeof(v_sz) + k_sz + v_sz + 1; end = ALIGN_UP(end, sizeof(uint32_t)); } - printk(BIOS_WARNING, "used smm store size might be 0x%zx bytes\n", end); + printk(BIOS_DEBUG, "used smm store size might be 0x%zx bytes\n", end); if (k_sz != 0xffffffff) { printk(BIOS_WARNING, "eof of data marker looks invalid: 0x%x\n", k_sz); + return CB_ERR; + } + + if (rdev_chain(store, store, end, data_sz - end)) + return CB_ERR; + + return CB_SUCCESS; + +} +/* + * Append data to region + * + * Returns 0 on success, -1 on failure + */ +int smmstore_append_data(void *key, uint32_t key_sz, void *value, + uint32_t value_sz) +{ + struct region_device store; + + if (lookup_store(&store) < 0) { + printk(BIOS_WARNING, "reading region failed\n"); return -1; } - printk(BIOS_WARNING, "used size looks legit\n"); + ssize_t offset = 0; + ssize_t size; + uint8_t nul = 0; + if (scan_end(&store) != CB_SUCCESS) + return -1; - printk(BIOS_WARNING, "open (%zx, %zx) for writing\n", + printk(BIOS_DEBUG, "used size looks legit\n"); + + printk(BIOS_DEBUG, "open (%zx, %zx) for writing\n", region_device_offset(&store), region_device_sz(&store)); - if (boot_device_rw_subregion(&store.region, &store) < 0) { - printk(BIOS_WARNING, "couldn't open store for writing\n"); - return -1; - } - uint32_t record_sz = 8 + key_sz + value_sz + 1; - if (end + record_sz >= data_sz) { + size = sizeof(key_sz) + sizeof(value_sz) + key_sz + value_sz + + sizeof(nul); + if (rdev_chain(&store, &store, 0, size)) { printk(BIOS_WARNING, "not enough space for new data\n"); return -1; } - if (rdev_writeat(&store, &key_sz, end, 4) != 4) { + if (rdev_writeat(&store, &key_sz, offset, sizeof(key_sz)) + != sizeof(key_sz)) { printk(BIOS_WARNING, "failed writing key size\n"); + return -1; } - end += 4; - if (rdev_writeat(&store, &value_sz, end, 4) != 4) { + offset += sizeof(key_sz); + if (rdev_writeat(&store, &value_sz, offset, sizeof(value_sz)) + != sizeof(value_sz)) { printk(BIOS_WARNING, "failed writing value size\n"); + return -1; } - end += 4; - if (rdev_writeat(&store, key, end, key_sz) != key_sz) { + offset += sizeof(value_sz); + if (rdev_writeat(&store, key, offset, key_sz) != key_sz) { printk(BIOS_WARNING, "failed writing key data\n"); + return -1; } - end += key_sz; - if (rdev_writeat(&store, value, end, value_sz) != value_sz) { + offset += key_sz; + if (rdev_writeat(&store, value, offset, value_sz) != value_sz) { printk(BIOS_WARNING, "failed writing value data\n"); + return -1; } - end += value_sz; - uint8_t nul = 0; - if (rdev_writeat(&store, &nul, end, 1) != 1) { + offset += value_sz; + if (rdev_writeat(&store, &nul, offset, sizeof(nul)) != sizeof(nul)) { printk(BIOS_WARNING, "failed writing termination\n"); + return -1; } return 0; From b52cc0e094f228c69d0b6e183bd14a146edd7f2f Mon Sep 17 00:00:00 2001 From: Arthur Heymans Date: Tue, 26 Nov 2019 16:11:58 +0100 Subject: [PATCH 0427/1242] Documentation: Add SMMSTORE documentation This documents the smmstore API. Change-Id: I992c04c0cf9b3f03755cf3fede2c82c6471a5ef4 Signed-off-by: Arthur Heymans Reviewed-on: https://review.coreboot.org/c/coreboot/+/37243 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi --- Documentation/drivers/index.md | 1 + Documentation/drivers/smmstore.md | 123 ++++++++++++++++++++++++++++++ 2 files changed, 124 insertions(+) create mode 100644 Documentation/drivers/smmstore.md diff --git a/Documentation/drivers/index.md b/Documentation/drivers/index.md index 60e90c3bf6..807ed85ed6 100644 --- a/Documentation/drivers/index.md +++ b/Documentation/drivers/index.md @@ -5,3 +5,4 @@ and plugin devices, significantly reducing integration complexity and they allow to easily reuse existing code accross platforms. * [IPMI KCS](ipmi_kcs.md) +* [SMMSTORE](smmstore.md) diff --git a/Documentation/drivers/smmstore.md b/Documentation/drivers/smmstore.md new file mode 100644 index 0000000000..ecf937b1d0 --- /dev/null +++ b/Documentation/drivers/smmstore.md @@ -0,0 +1,123 @@ +# SMM based flash storage driver + +This documents the API exposed by the x86 system management based +storage driver. + +## SMMSTORE + +SMMSTORE is a SMM mediated driver to read from, write to and erase a +predefined region in flash. It can be enabled by setting +`CONFIG_SMMSTORE=y` in menuconfig. + +This can be used by the OS or the payload to implement persistent +storage to hold for instance configuration data, without needing +to implement a (platform specific) storage driver in the payload +itself. + +The API provides append-only semantics for key/value pairs. + +## API + +### Storage region + +By default SMMSTORE will operate on a separate FMAP region called +`SMMSTORE`. The default generated FMAP will include such a region. +On systems with a locked FMAP, e.g. in an existing VBOOT setup +with a locked RO region, the option exists to add a cbfsfile +called `smm_store` in the `RW_LEGACY` (if CHROMEOS) or in the +`COREBOOT` FMAP regions. It is recommended for new builds using +a handcrafted FMD that intend to make use of SMMSTORE to include a +sufficiently large `SMMSTORE` FMAP region. It is recommended to +align the `SMMSTORE` region to 64KiB for the largest flash erase +op compatibility. + +When a default generated FMAP is used the size of the FMAP region +is equal to `CONFIG_SMMSTORE_SIZE`. UEFI payloads expect at least +64KiB. Given that the current implementation lacks a way to rewrite +key-value pairs at least a multiple of this is recommended. + +### generating the SMI + +SMMSTORE is called via an SMI, which is generated via a write to the +IO port defined in the smi_cmd entry of the FADT ACPI table. `%al` +contains `APM_CNT_SMMSTORE=0xed` and is written to the smi_cmd IO +port. `%ah` contains the SMMSTORE command. `%ebx` contains the +parameter buffer to the SMMSTORE command. + +### Return values + +If a command succeeds, SMMSTORE will return with +`SMMSTORE_RET_SUCCESS=0` on `%eax`. On failure SMMSTORE will return +`SMMSTORE_RET_FAILURE=1`. For unsupported SMMSTORE commands +`SMMSTORE_REG_UNSUPPORTED=2` is returned. + +**NOTE1**: The caller **must** check the return value and should make +no assumption on the returned data if `%eax` does not contain +`SMMSTORE_RET_SUCCESS`. + +**NOTE2**: If the SMI returns without changing `%ax` assume that the +SMMSTORE feature is not installed. + +### Calling arguments + +SMMSTORE supports 3 subcommands that are passed via `%ah`, the additional +calling arguments are passed via `%ebx`. + +**NOTE**: The size of the struct entries are in the native word size of +smihandler. This means 32 bits in almost all cases. + + +#### - SMMSTORE_CMD_CLEAR = 1 + +This clears the `SMMSTORE` storage region. The argument in `%ebx` is +unused. + +#### - SMMSTORE_CMD_READ = 2 + +The additional parameter buffer `%ebx` contains a pointer to +the following struct: + +```C +struct smmstore_params_read { + void *buf; + ssize_t bufsize; +}; +``` + +INPUT: +- `buf`: is a pointer to where the data needs to be read +- `bufsize`: is the size of the buffer + +OUTPUT: +- `buf` +- `bufsize`: returns the amount of data that has actually been read. + +#### - SMMSTORE_CMD_APPEND = 3 + +SMMSTORE takes a key-value approach to appending data. key-value pairs +are never updated, they are always appended. It is up to the caller to +walk through the key-value pairs after reading SMMSTORE to find the +latest one. + +The additional parameter buffer `%ebx` contains a pointer to +the following struct: + +```C +struct smmstore_params_append { + void *key; + size_t keysize; + void *val; + size_t valsize; +}; +``` + +INPUT: +- `key`: pointer to the key data +- `keysize`: size of the key data +- `val`: pointer to the value data +- `valsize`: size of the value data + +## External links + +* [A Tour Beyond BIOS Implementing UEFI Authenticated Variables in SMM with EDKI](https://software.intel.com/sites/default/files/managed/cf/ea/a_tour_beyond_bios_implementing_uefi_authenticated_variables_in_smm_with_edkii.pdf) +Note, this differs significantly from coreboot's implementation. From c1abf137ffd959318b9fdd33b7276f12c32aa19f Mon Sep 17 00:00:00 2001 From: Arthur Heymans Date: Tue, 26 Nov 2019 16:12:21 +0100 Subject: [PATCH 0428/1242] Documentation/4.12-relnotes.md: Add SMMSTORE as production ready Change-Id: I9fa0473dd8ab9d0476400fc2f40c684db0188fc3 Signed-off-by: Arthur Heymans Reviewed-on: https://review.coreboot.org/c/coreboot/+/37244 Reviewed-by: Paul Menzel Reviewed-by: Patrick Georgi Tested-by: build bot (Jenkins) --- Documentation/releases/coreboot-4.12-relnotes.md | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/Documentation/releases/coreboot-4.12-relnotes.md b/Documentation/releases/coreboot-4.12-relnotes.md index f9c5f7ed74..7943aa7161 100644 --- a/Documentation/releases/coreboot-4.12-relnotes.md +++ b/Documentation/releases/coreboot-4.12-relnotes.md @@ -13,4 +13,8 @@ notes. Significant changes ------------------- +### SMMSTORE is now production ready + +See [smmstore](../drivers/smmstore.md) for the documentation on the API. + ### Add significant changes here From f3db2aea85623cbbacdeb29cd175005cfdb05189 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Micha=C5=82=20=C5=BBygowski?= Date: Sun, 24 Nov 2019 13:26:10 +0100 Subject: [PATCH 0429/1242] sb/amd/{agesa,pi}/hudson: enable support for AMD common ACPIMMIO blocks MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: Michał Żygowski Change-Id: Idd014f1ba85efff0c98a0c5ab60d775ac93cbc60 Reviewed-on: https://review.coreboot.org/c/coreboot/+/37177 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki --- src/mainboard/pcengines/apu2/mainboard.c | 1 + src/southbridge/amd/agesa/hudson/Kconfig | 3 +++ src/southbridge/amd/agesa/hudson/hudson.c | 26 +------------------ src/southbridge/amd/agesa/hudson/hudson.h | 5 ---- src/southbridge/amd/agesa/hudson/lpc.c | 1 + src/southbridge/amd/agesa/hudson/smi.c | 1 + src/southbridge/amd/agesa/hudson/smi.h | 20 -------------- src/southbridge/amd/agesa/hudson/smi_util.c | 5 ++-- src/southbridge/amd/agesa/hudson/smihandler.c | 1 + src/southbridge/amd/pi/hudson/Kconfig | 3 +++ src/southbridge/amd/pi/hudson/hudson.c | 21 +-------------- src/southbridge/amd/pi/hudson/hudson.h | 5 ---- src/southbridge/amd/pi/hudson/lpc.c | 1 + src/southbridge/amd/pi/hudson/smi.c | 1 + src/southbridge/amd/pi/hudson/smi.h | 20 -------------- src/southbridge/amd/pi/hudson/smi_util.c | 5 ++-- src/southbridge/amd/pi/hudson/smihandler.c | 1 + 17 files changed, 21 insertions(+), 99 deletions(-) diff --git a/src/mainboard/pcengines/apu2/mainboard.c b/src/mainboard/pcengines/apu2/mainboard.c index 682120bc65..d46361c93b 100644 --- a/src/mainboard/pcengines/apu2/mainboard.c +++ b/src/mainboard/pcengines/apu2/mainboard.c @@ -13,6 +13,7 @@ * GNU General Public License for more details. */ +#include #include #include #include diff --git a/src/southbridge/amd/agesa/hudson/Kconfig b/src/southbridge/amd/agesa/hudson/Kconfig index 394a19697a..93db1a920c 100644 --- a/src/southbridge/amd/agesa/hudson/Kconfig +++ b/src/southbridge/amd/agesa/hudson/Kconfig @@ -27,6 +27,9 @@ config SOUTHBRIDGE_SPECIFIC_OPTIONS # dummy select HAVE_USBDEBUG_OPTIONS select HAVE_CF9_RESET select HAVE_CF9_RESET_PREPARE + select SOC_AMD_COMMON + select SOC_AMD_COMMON_BLOCK + select SOC_AMD_COMMON_BLOCK_ACPIMMIO config BOOTBLOCK_SOUTHBRIDGE_INIT string diff --git a/src/southbridge/amd/agesa/hudson/hudson.c b/src/southbridge/amd/agesa/hudson/hudson.c index 4c06e87281..d586d33f73 100644 --- a/src/southbridge/amd/agesa/hudson/hudson.c +++ b/src/southbridge/amd/agesa/hudson/hudson.c @@ -13,6 +13,7 @@ * GNU General Public License for more details. */ +#include #include #include #include @@ -25,31 +26,6 @@ #include "smbus.h" #include "smi.h" -/* Offsets from ACPI_MMIO_BASE - * This is defined by AGESA, but we don't include AGESA headers to avoid - * polluting the namespace. - */ -#define PM_MMIO_BASE 0xfed80300 - -void pm_write8(u8 reg, u8 value) -{ - write8((void *)((uintptr_t)PM_MMIO_BASE + reg), value); -} - -u8 pm_read8(u8 reg) -{ - return read8((void *)((uintptr_t)PM_MMIO_BASE + reg)); -} - -void pm_write16(u8 reg, u16 value) -{ - write16((void *)((uintptr_t)PM_MMIO_BASE + reg), value); -} - -u16 pm_read16(u16 reg) -{ - return read16((void *)((uintptr_t)PM_MMIO_BASE + reg)); -} #define PM_REG_USB_ENABLE 0xef diff --git a/src/southbridge/amd/agesa/hudson/hudson.h b/src/southbridge/amd/agesa/hudson/hudson.h index 21a2129a5c..18303fc5cb 100644 --- a/src/southbridge/amd/agesa/hudson/hudson.h +++ b/src/southbridge/amd/agesa/hudson/hudson.h @@ -61,11 +61,6 @@ static inline int hudson_ide_enable(void) return (CONFIG_HUDSON_SATA_MODE == 0) || (CONFIG_HUDSON_SATA_MODE == 3); } -void pm_write8(u8 reg, u8 value); -u8 pm_read8(u8 reg); -void pm_write16(u8 reg, u16 value); -u16 pm_read16(u16 reg); - void hudson_lpc_port80(void); void hudson_pci_port80(void); void hudson_clk_output_48Mhz(void); diff --git a/src/southbridge/amd/agesa/hudson/lpc.c b/src/southbridge/amd/agesa/hudson/lpc.c index eed1aec2e3..9c65d04729 100644 --- a/src/southbridge/amd/agesa/hudson/lpc.c +++ b/src/southbridge/amd/agesa/hudson/lpc.c @@ -14,6 +14,7 @@ * GNU General Public License for more details. */ +#include #include #include #include diff --git a/src/southbridge/amd/agesa/hudson/smi.c b/src/southbridge/amd/agesa/hudson/smi.c index f8196b4e65..7f76cd59d0 100644 --- a/src/southbridge/amd/agesa/hudson/smi.c +++ b/src/southbridge/amd/agesa/hudson/smi.c @@ -18,6 +18,7 @@ * Utilities for SMM setup */ +#include #include #include diff --git a/src/southbridge/amd/agesa/hudson/smi.h b/src/southbridge/amd/agesa/hudson/smi.h index 5e0c09a8e0..b1156a8e1f 100644 --- a/src/southbridge/amd/agesa/hudson/smi.h +++ b/src/southbridge/amd/agesa/hudson/smi.h @@ -47,26 +47,6 @@ enum smi_lvl { SMI_LVL_HIGH = 1, }; -static inline uint32_t smi_read32(uint8_t offset) -{ - return read32((void *)((uintptr_t)SMI_BASE + offset)); -} - -static inline void smi_write32(uint8_t offset, uint32_t value) -{ - write32((void *)((uintptr_t)SMI_BASE + offset), value); -} - -static inline uint16_t smi_read16(uint8_t offset) -{ - return read16((void *)((uintptr_t)SMI_BASE + offset)); -} - -static inline void smi_write16(uint8_t offset, uint16_t value) -{ - write16((void *)((uintptr_t)SMI_BASE + offset), value); -} - void hudson_configure_gevent_smi(uint8_t gevent, uint8_t mode, uint8_t level); void hudson_disable_gevent_smi(uint8_t gevent); void hudson_enable_acpi_cmd_smi(void); diff --git a/src/southbridge/amd/agesa/hudson/smi_util.c b/src/southbridge/amd/agesa/hudson/smi_util.c index 63bce7b071..80329541a8 100644 --- a/src/southbridge/amd/agesa/hudson/smi_util.c +++ b/src/southbridge/amd/agesa/hudson/smi_util.c @@ -18,10 +18,11 @@ * SMM utilities used in both SMM and normal mode */ -#include "smi.h" - +#include #include +#include "smi.h" + #define HUDSON_SMI_ACPI_COMMAND 75 static void configure_smi(uint8_t smi_num, uint8_t mode) diff --git a/src/southbridge/amd/agesa/hudson/smihandler.c b/src/southbridge/amd/agesa/hudson/smihandler.c index 6ecb7462f0..1b60f18652 100644 --- a/src/southbridge/amd/agesa/hudson/smihandler.c +++ b/src/southbridge/amd/agesa/hudson/smihandler.c @@ -18,6 +18,7 @@ * SMI handler for Hudson southbridges */ +#include #include #include diff --git a/src/southbridge/amd/pi/hudson/Kconfig b/src/southbridge/amd/pi/hudson/Kconfig index c636df8c13..01f3937321 100644 --- a/src/southbridge/amd/pi/hudson/Kconfig +++ b/src/southbridge/amd/pi/hudson/Kconfig @@ -30,6 +30,9 @@ config SOUTHBRIDGE_SPECIFIC_OPTIONS # dummy select HAVE_USBDEBUG_OPTIONS select HAVE_CF9_RESET select HAVE_CF9_RESET_PREPARE + select SOC_AMD_COMMON + select SOC_AMD_COMMON_BLOCK + select SOC_AMD_COMMON_BLOCK_ACPIMMIO config BOOTBLOCK_SOUTHBRIDGE_INIT string diff --git a/src/southbridge/amd/pi/hudson/hudson.c b/src/southbridge/amd/pi/hudson/hudson.c index a331c57262..51c37a1ca0 100644 --- a/src/southbridge/amd/pi/hudson/hudson.c +++ b/src/southbridge/amd/pi/hudson/hudson.c @@ -13,6 +13,7 @@ * GNU General Public License for more details. */ +#include #include #include #include @@ -36,26 +37,6 @@ int acpi_get_sleep_type(void) return (int)tmp; } -void pm_write8(u8 reg, u8 value) -{ - write8((void *)(PM_MMIO_BASE + reg), value); -} - -u8 pm_read8(u8 reg) -{ - return read8((void *)(PM_MMIO_BASE + reg)); -} - -void pm_write16(u8 reg, u16 value) -{ - write16((void *)(PM_MMIO_BASE + reg), value); -} - -u16 pm_read16(u16 reg) -{ - return read16((void *)(PM_MMIO_BASE + reg)); -} - void hudson_enable(struct device *dev) { printk(BIOS_DEBUG, "hudson_enable()\n"); diff --git a/src/southbridge/amd/pi/hudson/hudson.h b/src/southbridge/amd/pi/hudson/hudson.h index 9511a6ad24..b24629f0a1 100644 --- a/src/southbridge/amd/pi/hudson/hudson.h +++ b/src/southbridge/amd/pi/hudson/hudson.h @@ -169,11 +169,6 @@ static inline int hudson_ide_enable(void) return (CONFIG_HUDSON_SATA_MODE == 0) || (CONFIG_HUDSON_SATA_MODE == 3); } -void pm_write8(u8 reg, u8 value); -u8 pm_read8(u8 reg); -void pm_write16(u8 reg, u16 value); -u16 pm_read16(u16 reg); - void hudson_lpc_port80(void); void hudson_lpc_decode(void); void hudson_pci_port80(void); diff --git a/src/southbridge/amd/pi/hudson/lpc.c b/src/southbridge/amd/pi/hudson/lpc.c index e65fd838b0..6c3561f0c3 100644 --- a/src/southbridge/amd/pi/hudson/lpc.c +++ b/src/southbridge/amd/pi/hudson/lpc.c @@ -14,6 +14,7 @@ * GNU General Public License for more details. */ +#include #include #include #include diff --git a/src/southbridge/amd/pi/hudson/smi.c b/src/southbridge/amd/pi/hudson/smi.c index f8196b4e65..7f76cd59d0 100644 --- a/src/southbridge/amd/pi/hudson/smi.c +++ b/src/southbridge/amd/pi/hudson/smi.c @@ -18,6 +18,7 @@ * Utilities for SMM setup */ +#include #include #include diff --git a/src/southbridge/amd/pi/hudson/smi.h b/src/southbridge/amd/pi/hudson/smi.h index 684dca51c2..4faee1512f 100644 --- a/src/southbridge/amd/pi/hudson/smi.h +++ b/src/southbridge/amd/pi/hudson/smi.h @@ -47,26 +47,6 @@ enum smi_lvl { SMI_LVL_HIGH = 1, }; -static inline uint32_t smi_read32(uint8_t offset) -{ - return read32((void *)(SMI_BASE + offset)); -} - -static inline void smi_write32(uint8_t offset, uint32_t value) -{ - write32((void *)(SMI_BASE + offset), value); -} - -static inline uint16_t smi_read16(uint8_t offset) -{ - return read16((void *)(SMI_BASE + offset)); -} - -static inline void smi_write16(uint8_t offset, uint16_t value) -{ - write16((void *)(SMI_BASE + offset), value); -} - void hudson_configure_gevent_smi(uint8_t gevent, uint8_t mode, uint8_t level); void hudson_disable_gevent_smi(uint8_t gevent); void hudson_enable_acpi_cmd_smi(void); diff --git a/src/southbridge/amd/pi/hudson/smi_util.c b/src/southbridge/amd/pi/hudson/smi_util.c index 63bce7b071..80329541a8 100644 --- a/src/southbridge/amd/pi/hudson/smi_util.c +++ b/src/southbridge/amd/pi/hudson/smi_util.c @@ -18,10 +18,11 @@ * SMM utilities used in both SMM and normal mode */ -#include "smi.h" - +#include #include +#include "smi.h" + #define HUDSON_SMI_ACPI_COMMAND 75 static void configure_smi(uint8_t smi_num, uint8_t mode) diff --git a/src/southbridge/amd/pi/hudson/smihandler.c b/src/southbridge/amd/pi/hudson/smihandler.c index 6ecb7462f0..1b60f18652 100644 --- a/src/southbridge/amd/pi/hudson/smihandler.c +++ b/src/southbridge/amd/pi/hudson/smihandler.c @@ -18,6 +18,7 @@ * SMI handler for Hudson southbridges */ +#include #include #include From a3ce27d3dd65fd937ed9a8c5b9230bcace5b356f Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Micha=C5=82=20=C5=BBygowski?= Date: Wed, 27 Nov 2019 22:29:44 +0100 Subject: [PATCH 0430/1242] cpu/amd/{agesa,pi}/Kconfig: select SSE2 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit SSE2 instructions are supported by family14 and newer. SSE will be automatically enabled in bootblock_crt0 for platforms that migrate to C bootblock. Because of that family specific CAR setup may avoid additional code. TEST=boot PC Engines apu1 and apu2 Signed-off-by: Michał Żygowski Change-Id: I19f1793112439f0c706ebb066f9807364ad8c5a7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/37292 Reviewed-by: Patrick Georgi Reviewed-by: Kyösti Mälkki Tested-by: build bot (Jenkins) --- src/cpu/amd/agesa/Kconfig | 1 + src/cpu/amd/pi/Kconfig | 1 + 2 files changed, 2 insertions(+) diff --git a/src/cpu/amd/agesa/Kconfig b/src/cpu/amd/agesa/Kconfig index ddfe707d79..9956579c69 100644 --- a/src/cpu/amd/agesa/Kconfig +++ b/src/cpu/amd/agesa/Kconfig @@ -29,6 +29,7 @@ config CPU_AMD_AGESA select CBMEM_STAGE_CACHE if HAVE_ACPI_RESUME select SMM_ASEG select NO_FIXED_XIP_ROM_SIZE + select SSE2 if CPU_AMD_AGESA diff --git a/src/cpu/amd/pi/Kconfig b/src/cpu/amd/pi/Kconfig index d18f873332..728c7b1ce7 100644 --- a/src/cpu/amd/pi/Kconfig +++ b/src/cpu/amd/pi/Kconfig @@ -28,6 +28,7 @@ config CPU_AMD_PI select SPI_FLASH if HAVE_ACPI_RESUME select SMM_ASEG select NO_FIXED_XIP_ROM_SIZE + select SSE2 if CPU_AMD_PI From fba9f33187842e08dd3bb2b21845d7097b116094 Mon Sep 17 00:00:00 2001 From: Kevin Chiu Date: Thu, 28 Nov 2019 16:29:01 +0800 Subject: [PATCH 0431/1242] mainboard/google/kahlee: add G2 TS support for careena Add G2 GTCH7503 HID TS support spec from G2: G7500 / Ver.1.2 (3, April, 2018) BUG=b:141577276 BRANCH=master TEST=emerge-grunt coreboot Change-Id: I91e4f2b934b64b14bca20108037b721288d40942 Signed-off-by: Kevin Chiu Reviewed-on: https://review.coreboot.org/c/coreboot/+/37318 Reviewed-by: Martin Roth Tested-by: build bot (Jenkins) --- .../google/kahlee/variants/careena/devicetree.cb | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/src/mainboard/google/kahlee/variants/careena/devicetree.cb b/src/mainboard/google/kahlee/variants/careena/devicetree.cb index 635b23735c..3387b6f40b 100644 --- a/src/mainboard/google/kahlee/variants/careena/devicetree.cb +++ b/src/mainboard/google/kahlee/variants/careena/devicetree.cb @@ -167,5 +167,19 @@ chip soc/amd/stoneyridge register "has_power_resource" = "1" device i2c 10 on end end + chip drivers/i2c/hid + register "generic.hid" = ""GTCH7503"" + register "generic.desc" = ""G2TOUCH Touchscreen"" + register "generic.probed" = "1" + register "generic.irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW(GPIO_11)" + register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_85)" + register "generic.reset_delay_ms" = "50" + register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_76)" + register "generic.enable_delay_ms" = "1" + register "generic.has_power_resource" = "1" + register "generic.disable_gpio_export_in_crs" = "1" + register "hid_desc_reg_offset" = "0x01" + device i2c 40 on end + end end end #chip soc/amd/stoneyridge From b6c9a5d797ac5768321292ed649f1626c3596750 Mon Sep 17 00:00:00 2001 From: Arthur Heymans Date: Wed, 20 Nov 2019 19:35:59 +0100 Subject: [PATCH 0432/1242] vendorcode/siemens/hwilib: Drop CAR_GLOBAL_MIGRATION TEST: BUILD_TIMELESS=1 results in identical binaries. TODO: Is this code correct? The strncpy/strncmp current_hwi seems wrong. Change-Id: Icf44fee8f7f538df6c34dfbd98b852954d146896 Signed-off-by: Arthur Heymans Reviewed-on: https://review.coreboot.org/c/coreboot/+/37026 Tested-by: build bot (Jenkins) Reviewed-by: Werner Zeh --- src/vendorcode/siemens/hwilib/hwilib.c | 47 +++++++++++--------------- 1 file changed, 20 insertions(+), 27 deletions(-) diff --git a/src/vendorcode/siemens/hwilib/hwilib.c b/src/vendorcode/siemens/hwilib/hwilib.c index a4d87addff..35fb4ce86f 100644 --- a/src/vendorcode/siemens/hwilib/hwilib.c +++ b/src/vendorcode/siemens/hwilib/hwilib.c @@ -17,7 +17,6 @@ #include #include #include -#include #include #include "hwilib.h" @@ -74,15 +73,15 @@ struct param_info { /* Storage for pointers to the different blocks. The contents will be filled * in hwilib_find_blocks(). */ -static uint8_t *all_blocks[MAX_BLOCK_NUM] CAR_GLOBAL; +static uint8_t *all_blocks[MAX_BLOCK_NUM]; /* As the length of extended block is variable, save all length to a global * variable so that they can be used later to check boundaries. */ -static uint16_t all_blk_size[MAX_BLOCK_NUM] CAR_GLOBAL; +static uint16_t all_blk_size[MAX_BLOCK_NUM]; /* Storage for the cbfs file name of the currently open hwi file. */ -static char current_hwi[HWI_MAX_NAME_LEN] CAR_GLOBAL; +static char current_hwi[HWI_MAX_NAME_LEN]; static uint32_t hwilib_read_bytes (const struct param_info *param, uint8_t *dst, @@ -405,16 +404,14 @@ static uint32_t hwilib_read_bytes (const struct param_info *param, uint8_t *dst, uint32_t maxlen) { uint8_t i = 0, *blk = NULL; - uint8_t **blk_ptr = car_get_var_ptr(&all_blocks[0]); - uint16_t *all_blk_size_ptr = car_get_var_ptr(&all_blk_size[0]); if (!param || !dst) return 0; /* Take the first valid block to get the parameter from */ do { if ((param->pos[i].len) && (param->pos[i].offset) && - (blk_ptr[param->pos[i].blk_type])) { - blk = blk_ptr[param->pos[i].blk_type]; + (all_blocks[param->pos[i].blk_type])) { + blk = all_blocks[param->pos[i].blk_type]; break; } i++; @@ -425,7 +422,7 @@ static uint32_t hwilib_read_bytes (const struct param_info *param, uint8_t *dst, */ if ((!blk) || (param->pos[i].len > maxlen) || (param->pos[i].len + param->pos[i].offset > - all_blk_size_ptr[param->pos[i].blk_type])) + all_blk_size[param->pos[i].blk_type])) return 0; /* We can now copy the wanted data. */ memcpy(dst, (blk + param->pos[i].offset), param->pos[i].len); @@ -472,9 +469,6 @@ enum cb_err hwilib_find_blocks (const char *hwi_filename) { uint8_t *ptr = NULL, *base = NULL; uint32_t next_offset = 1; - uint8_t **blk_ptr = car_get_var_ptr(&all_blocks[0]); - uint16_t *all_blk_size_ptr = car_get_var_ptr(&all_blk_size[0]); - char *curr_hwi_name_ptr = car_get_var_ptr(¤t_hwi); size_t filesize = 0; /* Check for a valid parameter */ @@ -482,8 +476,7 @@ enum cb_err hwilib_find_blocks (const char *hwi_filename) return CB_ERR_ARG; /* Check if this file is already open. If yes, just leave as there is nothing left to do here. */ - if (curr_hwi_name_ptr && - !strncmp(curr_hwi_name_ptr, hwi_filename, HWI_MAX_NAME_LEN)) { + if (!strncmp((char *)¤t_hwi, hwi_filename, HWI_MAX_NAME_LEN)) { printk(BIOS_SPEW, "HWILIB: File \"%s\" already open.\n", hwi_filename); return CB_SUCCESS; @@ -504,15 +497,15 @@ enum cb_err hwilib_find_blocks (const char *hwi_filename) * in prior calls to this function. * This way the caller do not need to "close" already opened blocks. */ - memset(blk_ptr, 0, (MAX_BLOCK_NUM * sizeof (uint8_t *))); + memset(all_blocks, 0, (MAX_BLOCK_NUM * sizeof (uint8_t *))); /* Check which blocks are available by examining the length field. */ base = ptr; /* Fill in sizes of all fixed length blocks. */ - all_blk_size_ptr[BLK_HIB] = LEN_HIB; - all_blk_size_ptr[BLK_SIB] = LEN_SIB; - all_blk_size_ptr[BLK_EIB] = LEN_EIB; + all_blk_size[BLK_HIB] = LEN_HIB; + all_blk_size[BLK_SIB] = LEN_SIB; + all_blk_size[BLK_EIB] = LEN_EIB; /* Length of BLK_XIB is variable and will be filled if block is found */ - all_blk_size_ptr[BLK_XIB] = 0; + all_blk_size[BLK_XIB] = 0; while(!(strncmp((char *)ptr, BLOCK_MAGIC, LEN_MAGIC_NUM)) && next_offset) { uint16_t len = read16(ptr + LEN_OFFSET); @@ -520,26 +513,26 @@ enum cb_err hwilib_find_blocks (const char *hwi_filename) if ((ptr - base + len) > filesize) break; if (len == LEN_HIB) { - blk_ptr[BLK_HIB] = ptr; + all_blocks[BLK_HIB] = ptr; next_offset = read32(ptr + NEXT_OFFSET_HIB); if (next_offset) ptr = base + next_offset; } else if (len == LEN_SIB) { - blk_ptr[BLK_SIB] = ptr; + all_blocks[BLK_SIB] = ptr; next_offset = read32(ptr + NEXT_OFFSET_SIB); if (next_offset) ptr = base + next_offset; } else if (len == LEN_EIB) { /* Skip preliminary blocks */ if (!(read16(ptr + EIB_FEATRUE_OFFSET) & 0x01)) - blk_ptr[BLK_EIB] = ptr; + all_blocks[BLK_EIB] = ptr; next_offset = read32(ptr + NEXT_OFFSET_EIB); if (next_offset) ptr = base + next_offset; } else if (len >= MIN_LEN_XIB) { - blk_ptr[BLK_XIB] = ptr; + all_blocks[BLK_XIB] = ptr; next_offset = read32(ptr + NEXT_OFFSET_XIB); - all_blk_size_ptr[BLK_XIB] = len; + all_blk_size[BLK_XIB] = len; if (next_offset) ptr = base + next_offset; } else { @@ -547,10 +540,10 @@ enum cb_err hwilib_find_blocks (const char *hwi_filename) } } /* We should have found at least one valid block */ - if (blk_ptr[BLK_HIB] || blk_ptr[BLK_SIB] || blk_ptr[BLK_EIB] || - blk_ptr[BLK_XIB]) { + if (all_blocks[BLK_HIB] || all_blocks[BLK_SIB] || all_blocks[BLK_EIB] || + all_blocks[BLK_XIB]) { /* Save currently opened hwi filename. */ - strncpy(curr_hwi_name_ptr, hwi_filename, HWI_MAX_NAME_LEN); + strncpy((char *)¤t_hwi, hwi_filename, HWI_MAX_NAME_LEN); return CB_SUCCESS; } else From 5b0db35e0d597a93972c57fa210b1b4935e693ce Mon Sep 17 00:00:00 2001 From: Arthur Heymans Date: Thu, 21 Nov 2019 08:00:27 +0100 Subject: [PATCH 0433/1242] vendorcode/siemens/hwilib: Fix current file string usage The CAR_GLOBAL accessors likely hid a bug where strncmp/cpy was passed a pointer to a char array instead of the char array. Change-Id: I68788e47ef27a959d6e048e9385afcfb663cdebc Signed-off-by: Arthur Heymans Reviewed-on: https://review.coreboot.org/c/coreboot/+/37077 Tested-by: build bot (Jenkins) Reviewed-by: Werner Zeh Reviewed-by: Angel Pons --- src/vendorcode/siemens/hwilib/hwilib.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/vendorcode/siemens/hwilib/hwilib.c b/src/vendorcode/siemens/hwilib/hwilib.c index 35fb4ce86f..a4b8e547ae 100644 --- a/src/vendorcode/siemens/hwilib/hwilib.c +++ b/src/vendorcode/siemens/hwilib/hwilib.c @@ -476,7 +476,7 @@ enum cb_err hwilib_find_blocks (const char *hwi_filename) return CB_ERR_ARG; /* Check if this file is already open. If yes, just leave as there is nothing left to do here. */ - if (!strncmp((char *)¤t_hwi, hwi_filename, HWI_MAX_NAME_LEN)) { + if (!strncmp(current_hwi, hwi_filename, HWI_MAX_NAME_LEN)) { printk(BIOS_SPEW, "HWILIB: File \"%s\" already open.\n", hwi_filename); return CB_SUCCESS; @@ -543,7 +543,7 @@ enum cb_err hwilib_find_blocks (const char *hwi_filename) if (all_blocks[BLK_HIB] || all_blocks[BLK_SIB] || all_blocks[BLK_EIB] || all_blocks[BLK_XIB]) { /* Save currently opened hwi filename. */ - strncpy((char *)¤t_hwi, hwi_filename, HWI_MAX_NAME_LEN); + strncpy(current_hwi, hwi_filename, HWI_MAX_NAME_LEN); return CB_SUCCESS; } else From 7255610d9fe0867de50add6890653f14da676c06 Mon Sep 17 00:00:00 2001 From: Arthur Heymans Date: Wed, 20 Nov 2019 19:39:43 +0100 Subject: [PATCH 0434/1242] sb/intel/spi: Drop CAR_GLOBAL_MIGRATION Change-Id: I693cf494522c3bc1e1697a09be3e98fcb6db634d Signed-off-by: Arthur Heymans Reviewed-on: https://review.coreboot.org/c/coreboot/+/37027 Tested-by: build bot (Jenkins) Reviewed-by: HAOUAS Elyes Reviewed-by: Patrick Georgi --- src/southbridge/intel/common/spi.c | 198 +++++++++++++---------------- 1 file changed, 90 insertions(+), 108 deletions(-) diff --git a/src/southbridge/intel/common/spi.c b/src/southbridge/intel/common/spi.c index 3b7842de7d..4974e08c65 100644 --- a/src/southbridge/intel/common/spi.c +++ b/src/southbridge/intel/common/spi.c @@ -18,7 +18,6 @@ #define __SIMPLE_DEVICE__ /* This file is derived from the flashrom project. */ -#include #include #include #include @@ -112,7 +111,7 @@ struct ich_spi_controller { uint8_t fpr_max; }; -static struct ich_spi_controller g_cntlr CAR_GLOBAL; +static struct ich_spi_controller g_cntlr; enum { SPIS_SCIP = 0x0001, @@ -257,14 +256,13 @@ static void read_reg(const void *src, void *value, uint32_t size) static void ich_set_bbar(uint32_t minaddr) { - struct ich_spi_controller *cntlr = car_get_var_ptr(&g_cntlr); const uint32_t bbar_mask = 0x00ffff00; uint32_t ichspi_bbar; minaddr &= bbar_mask; - ichspi_bbar = readl_(cntlr->bbar) & ~bbar_mask; + ichspi_bbar = readl_(g_cntlr.bbar) & ~bbar_mask; ichspi_bbar |= minaddr; - writel_(ichspi_bbar, cntlr->bbar); + writel_(ichspi_bbar, g_cntlr.bbar); } #if CONFIG(SOUTHBRIDGE_INTEL_I82801GX) @@ -298,7 +296,6 @@ static void *get_spi_bar(pci_devfn_t dev) void spi_init(void) { - struct ich_spi_controller *cntlr = car_get_var_ptr(&g_cntlr); uint8_t bios_cntl; struct ich9_spi_regs *ich9_spi; struct ich7_spi_regs *ich7_spi; @@ -308,42 +305,42 @@ void spi_init(void) if (CONFIG(SOUTHBRIDGE_INTEL_I82801GX)) { ich7_spi = get_spi_bar(dev); - cntlr->ich7_spi = ich7_spi; - cntlr->opmenu = ich7_spi->opmenu; - cntlr->menubytes = sizeof(ich7_spi->opmenu); - cntlr->optype = &ich7_spi->optype; - cntlr->addr = &ich7_spi->spia; - cntlr->data = (uint8_t *)ich7_spi->spid; - cntlr->databytes = sizeof(ich7_spi->spid); - cntlr->status = (uint8_t *)&ich7_spi->spis; - cntlr->control = &ich7_spi->spic; - cntlr->bbar = &ich7_spi->bbar; - cntlr->preop = &ich7_spi->preop; - cntlr->fpr = &ich7_spi->pbr[0]; - cntlr->fpr_max = 3; + g_cntlr.ich7_spi = ich7_spi; + g_cntlr.opmenu = ich7_spi->opmenu; + g_cntlr.menubytes = sizeof(ich7_spi->opmenu); + g_cntlr.optype = &ich7_spi->optype; + g_cntlr.addr = &ich7_spi->spia; + g_cntlr.data = (uint8_t *)ich7_spi->spid; + g_cntlr.databytes = sizeof(ich7_spi->spid); + g_cntlr.status = (uint8_t *)&ich7_spi->spis; + g_cntlr.control = &ich7_spi->spic; + g_cntlr.bbar = &ich7_spi->bbar; + g_cntlr.preop = &ich7_spi->preop; + g_cntlr.fpr = &ich7_spi->pbr[0]; + g_cntlr.fpr_max = 3; } else { ich9_spi = get_spi_bar(dev); - cntlr->ich9_spi = ich9_spi; + g_cntlr.ich9_spi = ich9_spi; hsfs = readw_(&ich9_spi->hsfs); - cntlr->hsfs = hsfs; - cntlr->opmenu = ich9_spi->opmenu; - cntlr->menubytes = sizeof(ich9_spi->opmenu); - cntlr->optype = &ich9_spi->optype; - cntlr->addr = &ich9_spi->faddr; - cntlr->data = (uint8_t *)ich9_spi->fdata; - cntlr->databytes = sizeof(ich9_spi->fdata); - cntlr->status = &ich9_spi->ssfs; - cntlr->control = (uint16_t *)ich9_spi->ssfc; - cntlr->bbar = &ich9_spi->bbar; - cntlr->preop = &ich9_spi->preop; - cntlr->fpr = &ich9_spi->pr[0]; - cntlr->fpr_max = 5; + g_cntlr.hsfs = hsfs; + g_cntlr.opmenu = ich9_spi->opmenu; + g_cntlr.menubytes = sizeof(ich9_spi->opmenu); + g_cntlr.optype = &ich9_spi->optype; + g_cntlr.addr = &ich9_spi->faddr; + g_cntlr.data = (uint8_t *)ich9_spi->fdata; + g_cntlr.databytes = sizeof(ich9_spi->fdata); + g_cntlr.status = &ich9_spi->ssfs; + g_cntlr.control = (uint16_t *)ich9_spi->ssfc; + g_cntlr.bbar = &ich9_spi->bbar; + g_cntlr.preop = &ich9_spi->preop; + g_cntlr.fpr = &ich9_spi->pr[0]; + g_cntlr.fpr_max = 5; - if (cntlr->hsfs & HSFS_FDV) { + if (g_cntlr.hsfs & HSFS_FDV) { writel_(4, &ich9_spi->fdoc); - cntlr->flmap0 = readl_(&ich9_spi->fdod); + g_cntlr.flmap0 = readl_(&ich9_spi->fdod); writel_(0x1000, &ich9_spi->fdoc); - cntlr->flcomp = readl_(&ich9_spi->fdod); + g_cntlr.flcomp = readl_(&ich9_spi->fdod); } } @@ -360,11 +357,10 @@ void spi_init(void) static int spi_locked(void) { - struct ich_spi_controller *cntlr = &g_cntlr; if (CONFIG(SOUTHBRIDGE_INTEL_I82801GX)) { - return !!(readw_(&cntlr->ich7_spi->spis) & HSFS_FLOCKDN); + return !!(readw_(&g_cntlr.ich7_spi->spis) & HSFS_FLOCKDN); } else { - return !!(readw_(&cntlr->ich9_spi->hsfs) & HSFS_FLOCKDN); + return !!(readw_(&g_cntlr.ich9_spi->hsfs) & HSFS_FLOCKDN); } } @@ -433,7 +429,6 @@ static void spi_setup_type(spi_transaction *trans) static int spi_setup_opcode(spi_transaction *trans) { - struct ich_spi_controller *cntlr = car_get_var_ptr(&g_cntlr); uint16_t optypes; uint8_t opmenu[MENU_BYTES]; @@ -441,10 +436,10 @@ static int spi_setup_opcode(spi_transaction *trans) spi_use_out(trans, 1); if (!spi_locked()) { /* The lock is off, so just use index 0. */ - writeb_(trans->opcode, cntlr->opmenu); - optypes = readw_(cntlr->optype); + writeb_(trans->opcode, g_cntlr.opmenu); + optypes = readw_(g_cntlr.optype); optypes = (optypes & 0xfffc) | (trans->type & 0x3); - writew_(optypes, cntlr->optype); + writew_(optypes, g_cntlr.optype); return 0; } @@ -456,7 +451,7 @@ static int spi_setup_opcode(spi_transaction *trans) if (trans->opcode == SPI_OPCODE_WREN) return 0; - read_reg(cntlr->opmenu, opmenu, sizeof(opmenu)); + read_reg(g_cntlr.opmenu, opmenu, sizeof(opmenu)); for (opcode_index = 0; opcode_index < ARRAY_SIZE(opmenu); opcode_index++) { if (opmenu[opcode_index] == trans->opcode) break; @@ -468,7 +463,7 @@ static int spi_setup_opcode(spi_transaction *trans) return -1; } - optypes = readw_(cntlr->optype); + optypes = readw_(g_cntlr.optype); optype = (optypes >> (opcode_index * 2)) & 0x3; if (trans->type == SPI_OPCODE_TYPE_WRITE_NO_ADDRESS && optype == SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS && @@ -513,15 +508,14 @@ static int spi_setup_offset(spi_transaction *trans) */ static int ich_status_poll(u16 bitmask, int wait_til_set) { - struct ich_spi_controller *cntlr = car_get_var_ptr(&g_cntlr); int timeout = 600000; /* This will result in 6 seconds */ u16 status = 0; while (timeout--) { - status = readw_(cntlr->status); + status = readw_(g_cntlr.status); if (wait_til_set ^ ((status & bitmask) == 0)) { if (wait_til_set) - writew_((status & bitmask), cntlr->status); + writew_((status & bitmask), g_cntlr.status); return status; } udelay(10); @@ -534,16 +528,14 @@ static int ich_status_poll(u16 bitmask, int wait_til_set) static int spi_is_multichip(void) { - struct ich_spi_controller *cntlr = car_get_var_ptr(&g_cntlr); - if (!(cntlr->hsfs & HSFS_FDV)) + if (!(g_cntlr.hsfs & HSFS_FDV)) return 0; - return !!((cntlr->flmap0 >> 8) & 3); + return !!((g_cntlr.flmap0 >> 8) & 3); } static int spi_ctrlr_xfer(const struct spi_slave *slave, const void *dout, size_t bytesout, void *din, size_t bytesin) { - struct ich_spi_controller *cntlr = car_get_var_ptr(&g_cntlr); uint16_t control; int16_t opcode_index; int with_address; @@ -569,7 +561,7 @@ static int spi_ctrlr_xfer(const struct spi_slave *slave, const void *dout, if (ich_status_poll(SPIS_SCIP, 0) == -1) return -1; - writew_(SPIS_CDS | SPIS_FCERR, cntlr->status); + writew_(SPIS_CDS | SPIS_FCERR, g_cntlr.status); spi_setup_type(&trans); if ((opcode_index = spi_setup_opcode(&trans)) < 0) @@ -584,7 +576,7 @@ static int spi_ctrlr_xfer(const struct spi_slave *slave, const void *dout, * issuing a transaction between WREN and DATA. */ if (!spi_locked()) - writew_(trans.opcode, cntlr->preop); + writew_(trans.opcode, g_cntlr.preop); return 0; } @@ -592,13 +584,13 @@ static int spi_ctrlr_xfer(const struct spi_slave *slave, const void *dout, control = SPIC_SCGO | ((opcode_index & 0x07) << 4); /* Issue atomic preop cycle if needed */ - if (readw_(cntlr->preop)) + if (readw_(g_cntlr.preop)) control |= SPIC_ACS; if (!trans.bytesout && !trans.bytesin) { /* SPI addresses are 24 bit only */ if (with_address) - writel_(trans.offset & 0x00FFFFFF, cntlr->addr); + writel_(trans.offset & 0x00FFFFFF, g_cntlr.addr); /* * This is a 'no data' command (like Write Enable), its @@ -606,7 +598,7 @@ static int spi_ctrlr_xfer(const struct spi_slave *slave, const void *dout, * spi_setup_opcode() above. Tell the chip to send the * command. */ - writew_(control, cntlr->control); + writew_(control, g_cntlr.control); /* wait for the result */ status = ich_status_poll(SPIS_CDS | SPIS_FCERR, 1); @@ -628,7 +620,7 @@ static int spi_ctrlr_xfer(const struct spi_slave *slave, const void *dout, * and followed by other SPI commands, and this sequence is controlled * by the SPI chip driver. */ - if (trans.bytesout > cntlr->databytes) { + if (trans.bytesout > g_cntlr.databytes) { printk(BIOS_DEBUG, "ICH SPI: Too much to write. Does your SPI chip driver use" " spi_crop_chunk()?\n"); return -1; @@ -642,28 +634,28 @@ static int spi_ctrlr_xfer(const struct spi_slave *slave, const void *dout, uint32_t data_length; /* SPI addresses are 24 bit only */ - writel_(trans.offset & 0x00FFFFFF, cntlr->addr); + writel_(trans.offset & 0x00FFFFFF, g_cntlr.addr); if (trans.bytesout) - data_length = min(trans.bytesout, cntlr->databytes); + data_length = min(trans.bytesout, g_cntlr.databytes); else - data_length = min(trans.bytesin, cntlr->databytes); + data_length = min(trans.bytesin, g_cntlr.databytes); /* Program data into FDATA0 to N */ if (trans.bytesout) { - write_reg(trans.out, cntlr->data, data_length); + write_reg(trans.out, g_cntlr.data, data_length); spi_use_out(&trans, data_length); if (with_address) trans.offset += data_length; } /* Add proper control fields' values */ - control &= ~((cntlr->databytes - 1) << 8); + control &= ~((g_cntlr.databytes - 1) << 8); control |= SPIC_DS; control |= (data_length - 1) << 8; /* write it */ - writew_(control, cntlr->control); + writew_(control, g_cntlr.control); /* Wait for Cycle Done Status or Flash Cycle Error. */ status = ich_status_poll(SPIS_CDS | SPIS_FCERR, 1); @@ -676,7 +668,7 @@ static int spi_ctrlr_xfer(const struct spi_slave *slave, const void *dout, } if (trans.bytesin) { - read_reg(cntlr->data, trans.in, data_length); + read_reg(g_cntlr.data, trans.in, data_length); spi_use_in(&trans, data_length); if (with_address) trans.offset += data_length; @@ -685,7 +677,7 @@ static int spi_ctrlr_xfer(const struct spi_slave *slave, const void *dout, spi_xfer_exit: /* Clear atomic preop now that xfer is done */ - writew_(0, cntlr->preop); + writew_(0, g_cntlr.preop); return 0; } @@ -693,10 +685,9 @@ spi_xfer_exit: /* Sets FLA in FADDR to (addr & 0x01FFFFFF) without touching other bits. */ static void ich_hwseq_set_addr(uint32_t addr) { - struct ich_spi_controller *cntlr = car_get_var_ptr(&g_cntlr); - uint32_t addr_old = readl_(&cntlr->ich9_spi->faddr) & ~0x01FFFFFF; + uint32_t addr_old = readl_(&g_cntlr.ich9_spi->faddr) & ~0x01FFFFFF; - writel_((addr & 0x01FFFFFF) | addr_old, &cntlr->ich9_spi->faddr); + writel_((addr & 0x01FFFFFF) | addr_old, &g_cntlr.ich9_spi->faddr); } /* Polls for Cycle Done Status, Flash Cycle Error or timeout in 8 us intervals. @@ -706,22 +697,21 @@ static void ich_hwseq_set_addr(uint32_t addr) static int ich_hwseq_wait_for_cycle_complete(unsigned int timeout, unsigned int len) { - struct ich_spi_controller *cntlr = car_get_var_ptr(&g_cntlr); uint16_t hsfs; uint32_t addr; timeout /= 8; /* scale timeout duration to counter */ - while ((((hsfs = readw_(&cntlr->ich9_spi->hsfs)) & + while ((((hsfs = readw_(&g_cntlr.ich9_spi->hsfs)) & (HSFS_FDONE | HSFS_FCERR)) == 0) && --timeout) { udelay(8); } - writew_(readw_(&cntlr->ich9_spi->hsfs), &cntlr->ich9_spi->hsfs); + writew_(readw_(&g_cntlr.ich9_spi->hsfs), &g_cntlr.ich9_spi->hsfs); if (!timeout) { uint16_t hsfc; - addr = readl_(&cntlr->ich9_spi->faddr) & 0x01FFFFFF; - hsfc = readw_(&cntlr->ich9_spi->hsfc); + addr = readl_(&g_cntlr.ich9_spi->faddr) & 0x01FFFFFF; + hsfc = readw_(&g_cntlr.ich9_spi->hsfc); printk(BIOS_ERR, "Transaction timeout between offset 0x%08x and " "0x%08x (= 0x%08x + %d) HSFC=%x HSFS=%x!\n", addr, addr + len - 1, addr, len - 1, @@ -731,8 +721,8 @@ static int ich_hwseq_wait_for_cycle_complete(unsigned int timeout, if (hsfs & HSFS_FCERR) { uint16_t hsfc; - addr = readl_(&cntlr->ich9_spi->faddr) & 0x01FFFFFF; - hsfc = readw_(&cntlr->ich9_spi->hsfc); + addr = readl_(&g_cntlr.ich9_spi->faddr) & 0x01FFFFFF; + hsfc = readw_(&g_cntlr.ich9_spi->hsfc); printk(BIOS_ERR, "Transaction error between offset 0x%08x and " "0x%08x (= 0x%08x + %d) HSFC=%x HSFS=%x!\n", addr, addr + len - 1, addr, len - 1, @@ -746,7 +736,6 @@ static int ich_hwseq_wait_for_cycle_complete(unsigned int timeout, static int ich_hwseq_erase(const struct spi_flash *flash, u32 offset, size_t len) { - struct ich_spi_controller *cntlr = car_get_var_ptr(&g_cntlr); u32 start, end, erase_size; int ret; uint16_t hsfc; @@ -769,17 +758,17 @@ static int ich_hwseq_erase(const struct spi_flash *flash, u32 offset, while (offset < end) { /* make sure FDONE, FCERR, AEL are cleared by writing 1 to them */ - writew_(readw_(&cntlr->ich9_spi->hsfs), &cntlr->ich9_spi->hsfs); + writew_(readw_(&g_cntlr.ich9_spi->hsfs), &g_cntlr.ich9_spi->hsfs); ich_hwseq_set_addr(offset); offset += erase_size; - hsfc = readw_(&cntlr->ich9_spi->hsfc); + hsfc = readw_(&g_cntlr.ich9_spi->hsfc); hsfc &= ~HSFC_FCYCLE; /* clear operation */ hsfc |= (0x3 << HSFC_FCYCLE_OFF); /* set erase operation */ hsfc |= HSFC_FGO; /* start */ - writew_(hsfc, &cntlr->ich9_spi->hsfc); + writew_(hsfc, &g_cntlr.ich9_spi->hsfc); if (ich_hwseq_wait_for_cycle_complete(timeout, len)) { printk(BIOS_ERR, "SF: Erase failed at %x\n", offset - erase_size); ret = -1; @@ -796,13 +785,12 @@ out: static void ich_read_data(uint8_t *data, int len) { - struct ich_spi_controller *cntlr = car_get_var_ptr(&g_cntlr); int i; uint32_t temp32 = 0; for (i = 0; i < len; i++) { if ((i % 4) == 0) - temp32 = readl_(cntlr->data + i); + temp32 = readl_(g_cntlr.data + i); data[i] = (temp32 >> ((i % 4) * 8)) & 0xff; } @@ -811,7 +799,6 @@ static void ich_read_data(uint8_t *data, int len) static int ich_hwseq_read(const struct spi_flash *flash, u32 addr, size_t len, void *buf) { - struct ich_spi_controller *cntlr = car_get_var_ptr(&g_cntlr); uint16_t hsfc; uint16_t timeout = 100 * 60; uint8_t block_len; @@ -825,20 +812,20 @@ static int ich_hwseq_read(const struct spi_flash *flash, u32 addr, size_t len, } /* clear FDONE, FCERR, AEL by writing 1 to them (if they are set) */ - writew_(readw_(&cntlr->ich9_spi->hsfs), &cntlr->ich9_spi->hsfs); + writew_(readw_(&g_cntlr.ich9_spi->hsfs), &g_cntlr.ich9_spi->hsfs); while (len > 0) { - block_len = min(len, cntlr->databytes); + block_len = min(len, g_cntlr.databytes); if (block_len > (~addr & 0xff)) block_len = (~addr & 0xff) + 1; ich_hwseq_set_addr(addr); - hsfc = readw_(&cntlr->ich9_spi->hsfc); + hsfc = readw_(&g_cntlr.ich9_spi->hsfc); hsfc &= ~HSFC_FCYCLE; /* set read operation */ hsfc &= ~HSFC_FDBC; /* clear byte count */ /* set byte count */ hsfc |= (((block_len - 1) << HSFC_FDBC_OFF) & HSFC_FDBC); hsfc |= HSFC_FGO; /* start */ - writew_(hsfc, &cntlr->ich9_spi->hsfc); + writew_(hsfc, &g_cntlr.ich9_spi->hsfc); if (ich_hwseq_wait_for_cycle_complete(timeout, block_len)) return 1; @@ -857,7 +844,6 @@ static int ich_hwseq_read(const struct spi_flash *flash, u32 addr, size_t len, */ static void ich_fill_data(const uint8_t *data, int len) { - struct ich_spi_controller *cntlr = car_get_var_ptr(&g_cntlr); uint32_t temp32 = 0; int i; @@ -871,17 +857,16 @@ static void ich_fill_data(const uint8_t *data, int len) temp32 |= ((uint32_t) data[i]) << ((i % 4) * 8); if ((i % 4) == 3) /* 32 bits are full, write them to regs. */ - writel_(temp32, cntlr->data + (i - (i % 4))); + writel_(temp32, g_cntlr.data + (i - (i % 4))); } i--; if ((i % 4) != 3) /* Write remaining data to regs. */ - writel_(temp32, cntlr->data + (i - (i % 4))); + writel_(temp32, g_cntlr.data + (i - (i % 4))); } static int ich_hwseq_write(const struct spi_flash *flash, u32 addr, size_t len, const void *buf) { - struct ich_spi_controller *cntlr = car_get_var_ptr(&g_cntlr); uint16_t hsfc; uint16_t timeout = 100 * 60; uint8_t block_len; @@ -895,24 +880,24 @@ static int ich_hwseq_write(const struct spi_flash *flash, u32 addr, size_t len, } /* clear FDONE, FCERR, AEL by writing 1 to them (if they are set) */ - writew_(readw_(&cntlr->ich9_spi->hsfs), &cntlr->ich9_spi->hsfs); + writew_(readw_(&g_cntlr.ich9_spi->hsfs), &g_cntlr.ich9_spi->hsfs); while (len > 0) { - block_len = min(len, cntlr->databytes); + block_len = min(len, g_cntlr.databytes); if (block_len > (~addr & 0xff)) block_len = (~addr & 0xff) + 1; ich_hwseq_set_addr(addr); ich_fill_data(buf, block_len); - hsfc = readw_(&cntlr->ich9_spi->hsfc); + hsfc = readw_(&g_cntlr.ich9_spi->hsfc); hsfc &= ~HSFC_FCYCLE; /* clear operation */ hsfc |= (0x2 << HSFC_FCYCLE_OFF); /* set write operation */ hsfc &= ~HSFC_FDBC; /* clear byte count */ /* set byte count */ hsfc |= (((block_len - 1) << HSFC_FDBC_OFF) & HSFC_FDBC); hsfc |= HSFC_FGO; /* start */ - writew_(hsfc, &cntlr->ich9_spi->hsfc); + writew_(hsfc, &g_cntlr.ich9_spi->hsfc); if (ich_hwseq_wait_for_cycle_complete(timeout, block_len)) { printk(BIOS_ERR, "SF: write failure at %x\n", @@ -937,7 +922,6 @@ static const struct spi_flash_ops spi_flash_ops = { static int spi_flash_programmer_probe(const struct spi_slave *spi, struct spi_flash *flash) { - struct ich_spi_controller *cntlr = car_get_var_ptr(&g_cntlr); if (CONFIG(SOUTHBRIDGE_INTEL_I82801GX)) return spi_flash_generic_probe(spi, flash); @@ -950,7 +934,7 @@ static int spi_flash_programmer_probe(const struct spi_slave *spi, flash->name = "Opaque HW-sequencing"; ich_hwseq_set_addr(0); - switch ((cntlr->hsfs >> 3) & 3) { + switch ((g_cntlr.hsfs >> 3) & 3) { case 0: flash->sector_size = 256; break; @@ -965,12 +949,12 @@ static int spi_flash_programmer_probe(const struct spi_slave *spi, break; } - flash->size = 1 << (19 + (cntlr->flcomp & 7)); + flash->size = 1 << (19 + (g_cntlr.flcomp & 7)); flash->ops = &spi_flash_ops; - if ((cntlr->hsfs & HSFS_FDV) && ((cntlr->flmap0 >> 8) & 3)) - flash->size += 1 << (19 + ((cntlr->flcomp >> 3) & 7)); + if ((g_cntlr.hsfs & HSFS_FDV) && ((g_cntlr.flmap0 >> 8) & 3)) + flash->size += 1 << (19 + ((g_cntlr.flcomp >> 3) & 7)); printk(BIOS_DEBUG, "flash size 0x%x bytes\n", flash->size); return 0; @@ -1017,7 +1001,6 @@ static int spi_flash_protect(const struct spi_flash *flash, const struct region *region, const enum ctrlr_prot_type type) { - struct ich_spi_controller *cntlr = car_get_var_ptr(&g_cntlr); u32 start = region_offset(region); u32 end = start + region_sz(region) - 1; u32 reg; @@ -1025,16 +1008,16 @@ static int spi_flash_protect(const struct spi_flash *flash, int fpr; uint32_t *fpr_base; - fpr_base = cntlr->fpr; + fpr_base = g_cntlr.fpr; /* Find first empty FPR */ - for (fpr = 0; fpr < cntlr->fpr_max; fpr++) { + for (fpr = 0; fpr < g_cntlr.fpr_max; fpr++) { reg = read32(&fpr_base[fpr]); if (reg == 0) break; } - if (fpr == cntlr->fpr_max) { + if (fpr == g_cntlr.fpr_max) { printk(BIOS_ERR, "ERROR: No SPI FPR free!\n"); return -1; } @@ -1075,7 +1058,6 @@ static int spi_flash_protect(const struct spi_flash *flash, void spi_finalize_ops(void) { - struct ich_spi_controller *cntlr = car_get_var_ptr(&g_cntlr); u16 spi_opprefix; u16 optype = 0; struct intel_swseq_spi_config spi_config_default = { @@ -1124,12 +1106,12 @@ void spi_finalize_ops(void) spi_opprefix = spi_config->opprefixes[0] | (spi_config->opprefixes[1] << 8); - writew_(spi_opprefix, cntlr->preop); + writew_(spi_opprefix, g_cntlr.preop); for (i = 0; i < ARRAY_SIZE(spi_config->ops); i++) { optype |= (spi_config->ops[i].type & 3) << (i * 2); - writeb_(spi_config->ops[i].op, &cntlr->opmenu[i]); + writeb_(spi_config->ops[i].op, &g_cntlr.opmenu[i]); } - writew_(optype, cntlr->optype); + writew_(optype, g_cntlr.optype); } __weak void intel_southbridge_override_spi(struct intel_swseq_spi_config *spi_config) From 344e86bb3baff8f89c1335c190dbee050176e058 Mon Sep 17 00:00:00 2001 From: Arthur Heymans Date: Wed, 20 Nov 2019 19:47:10 +0100 Subject: [PATCH 0435/1242] security/vboot: Drop CAR_GLOBAL_MIGRATION support Change-Id: I9dee03da028b9111b685e325368815a86e444a47 Signed-off-by: Arthur Heymans Reviewed-on: https://review.coreboot.org/c/coreboot/+/37028 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin --- src/security/vboot/common.c | 19 ++++++++--------- src/security/vboot/misc.h | 3 +-- src/security/vboot/vbnv.c | 35 +++++++------------------------ src/security/vboot/vbnv_flash.c | 11 +++++----- src/security/vboot/vboot_loader.c | 8 +++---- 5 files changed, 26 insertions(+), 50 deletions(-) diff --git a/src/security/vboot/common.c b/src/security/vboot/common.c index bad01ff57f..290fa5e231 100644 --- a/src/security/vboot/common.c +++ b/src/security/vboot/common.c @@ -25,7 +25,7 @@ #include #include -static struct vb2_context *vboot_ctx CAR_GLOBAL; +static struct vb2_context *vboot_ctx; struct vboot_working_data *vboot_get_working_data(void) { @@ -50,20 +50,19 @@ static inline void *vboot_get_workbuf(struct vboot_working_data *wd) struct vb2_context *vboot_get_context(void) { - struct vb2_context **vboot_ctx_ptr = car_get_var_ptr(&vboot_ctx); struct vboot_working_data *wd; /* Return if context has already been initialized/restored. */ - if (*vboot_ctx_ptr) - return *vboot_ctx_ptr; + if (vboot_ctx) + return vboot_ctx; wd = vboot_get_working_data(); /* Restore context from a previous stage. */ if (vboot_logic_executed()) { assert(vb2api_reinit(vboot_get_workbuf(wd), - vboot_ctx_ptr) == VB2_SUCCESS); - return *vboot_ctx_ptr; + &vboot_ctx) == VB2_SUCCESS); + return vboot_ctx; } assert(verification_should_run()); @@ -78,10 +77,10 @@ struct vb2_context *vboot_get_context(void) /* Initialize vb2_shared_data and friends. */ assert(vb2api_init(vboot_get_workbuf(wd), VB2_FIRMWARE_WORKBUF_RECOMMENDED_SIZE - - wd->buffer_offset, - vboot_ctx_ptr) == VB2_SUCCESS); + wd->buffer_offset, + &vboot_ctx) == VB2_SUCCESS); - return *vboot_ctx_ptr; + return vboot_ctx; } int vboot_locate_firmware(const struct vb2_context *ctx, @@ -116,7 +115,7 @@ static void vboot_migrate_cbmem(int unused) vb2api_relocate(vboot_get_workbuf(wd_cbmem), vboot_get_workbuf(wd_preram), cbmem_size - wd_cbmem->buffer_offset, - car_get_var_ptr(&vboot_ctx)); + &vboot_ctx); } ROMSTAGE_CBMEM_INIT_HOOK(vboot_migrate_cbmem) #else diff --git a/src/security/vboot/misc.h b/src/security/vboot/misc.h index 471f838a9c..9f681f6f7f 100644 --- a/src/security/vboot/misc.h +++ b/src/security/vboot/misc.h @@ -17,7 +17,6 @@ #define __VBOOT_MISC_H__ #include -#include #include struct vb2_context; @@ -112,7 +111,7 @@ static inline int vboot_logic_executed(void) need to check a global to see if verfication has run. */ if (verification_should_run() || (verstage_should_load() && CONFIG(VBOOT_RETURN_FROM_VERSTAGE))) - return car_get_var(vboot_executed); + return vboot_executed; if (CONFIG(VBOOT_STARTS_IN_BOOTBLOCK)) { /* All other stages are "after the bootblock" */ diff --git a/src/security/vboot/vbnv.c b/src/security/vboot/vbnv.c index eccd743012..be598acb18 100644 --- a/src/security/vboot/vbnv.c +++ b/src/security/vboot/vbnv.c @@ -13,32 +13,13 @@ * GNU General Public License for more details. */ -#include #include #include #include #include -static int vbnv_initialized CAR_GLOBAL; -static uint8_t vbnv[VBOOT_VBNV_BLOCK_SIZE] CAR_GLOBAL; - -/* Wrappers for accessing the variables marked as CAR_GLOBAL. */ -static inline int is_vbnv_initialized(void) -{ - return car_get_var(vbnv_initialized); -} - -static inline uint8_t *vbnv_data_addr(int index) -{ - uint8_t *vbnv_arr = car_get_var_ptr(vbnv); - - return &vbnv_arr[index]; -} - -static inline uint8_t vbnv_data(int index) -{ - return *vbnv_data_addr(index); -} +static int vbnv_initialized; +static uint8_t vbnv[VBOOT_VBNV_BLOCK_SIZE]; /* Return CRC-8 of the data, using x^8 + x^2 + x + 1 polynomial. */ static uint8_t crc8_vbnv(const uint8_t *data, int len) @@ -66,9 +47,9 @@ void vbnv_reset(uint8_t *vbnv_copy) /* Read VBNV data into cache. */ static void vbnv_setup(void) { - if (!is_vbnv_initialized()) { - read_vbnv(vbnv_data_addr(0)); - car_set_var(vbnv_initialized, 1); + if (!vbnv_initialized) { + read_vbnv(vbnv); + vbnv_initialized = 1; } } @@ -117,7 +98,7 @@ void save_vbnv(const uint8_t *vbnv_copy) save_vbnv_flash(vbnv_copy); /* Clear initialized flag to force cached data to be updated */ - car_set_var(vbnv_initialized, 0); + vbnv_initialized = 0; } /* Save a recovery reason into VBNV. */ @@ -137,14 +118,14 @@ void set_recovery_mode_into_vbnv(int recovery_reason) int get_recovery_mode_from_vbnv(void) { vbnv_setup(); - return vbnv_data(RECOVERY_OFFSET); + return vbnv[RECOVERY_OFFSET]; } /* Read the USB Device Controller(UDC) enable flag from VBNV. */ int vbnv_udc_enable_flag(void) { vbnv_setup(); - return (vbnv_data(DEV_FLAGS_OFFSET) & DEV_ENABLE_UDC) ? 1 : 0; + return (vbnv[DEV_FLAGS_OFFSET] & DEV_ENABLE_UDC) ? 1 : 0; } void vbnv_init(uint8_t *vbnv_copy) diff --git a/src/security/vboot/vbnv_flash.c b/src/security/vboot/vbnv_flash.c index 86c43cd302..58d3aba2a7 100644 --- a/src/security/vboot/vbnv_flash.c +++ b/src/security/vboot/vbnv_flash.c @@ -13,7 +13,6 @@ * GNU General Public License for more details. */ -#include #include #include #include @@ -41,7 +40,7 @@ struct vbnv_flash_ctx { /* Cache of the current nvdata */ uint8_t cache[BLOB_SIZE]; }; -static struct vbnv_flash_ctx vbnv_flash CAR_GLOBAL; +static struct vbnv_flash_ctx vbnv_flash; /* * This code assumes that flash is erased to 1-bits, and write operations can @@ -60,7 +59,7 @@ static inline int can_overwrite(uint8_t current, uint8_t new) static int init_vbnv(void) { - struct vbnv_flash_ctx *ctx = car_get_var_ptr(&vbnv_flash); + struct vbnv_flash_ctx *ctx = &vbnv_flash; struct region_device *rdev = &ctx->vbnv_dev; uint8_t buf[BLOB_SIZE]; uint8_t empty_blob[BLOB_SIZE]; @@ -116,7 +115,7 @@ static int init_vbnv(void) static int erase_nvram(void) { - struct vbnv_flash_ctx *ctx = car_get_var_ptr(&vbnv_flash); + struct vbnv_flash_ctx *ctx = &vbnv_flash; const struct region_device *rdev = &ctx->vbnv_dev; if (rdev_eraseat(rdev, 0, region_device_sz(rdev)) < 0) { @@ -130,7 +129,7 @@ static int erase_nvram(void) void read_vbnv_flash(uint8_t *vbnv_copy) { - struct vbnv_flash_ctx *ctx = car_get_var_ptr(&vbnv_flash); + struct vbnv_flash_ctx *ctx = &vbnv_flash; if (!ctx->initialized) if (init_vbnv()) @@ -141,7 +140,7 @@ void read_vbnv_flash(uint8_t *vbnv_copy) void save_vbnv_flash(const uint8_t *vbnv_copy) { - struct vbnv_flash_ctx *ctx = car_get_var_ptr(&vbnv_flash); + struct vbnv_flash_ctx *ctx = &vbnv_flash; int new_offset; int i; const struct region_device *rdev = &ctx->vbnv_dev; diff --git a/src/security/vboot/vboot_loader.c b/src/security/vboot/vboot_loader.c index 3e491a7200..9aaaff2f32 100644 --- a/src/security/vboot/vboot_loader.c +++ b/src/security/vboot/vboot_loader.c @@ -13,8 +13,6 @@ * GNU General Public License for more details. */ -#include -#include #include #include #include @@ -34,14 +32,14 @@ _Static_assert(!CONFIG(VBOOT_RETURN_FROM_VERSTAGE) || CONFIG(VBOOT_SEPARATE_VERSTAGE), "return from verstage only makes sense for separate verstages"); -int vboot_executed CAR_GLOBAL; +int vboot_executed; void vboot_run_logic(void) { if (verification_should_run()) { /* Note: this path is not used for VBOOT_RETURN_FROM_VERSTAGE */ verstage_main(); - car_set_var(vboot_executed, 1); + vboot_executed = 1; } else if (verstage_should_load()) { struct cbfsf file; struct prog verstage = @@ -68,7 +66,7 @@ void vboot_run_logic(void) if (!CONFIG(VBOOT_RETURN_FROM_VERSTAGE)) return; - car_set_var(vboot_executed, 1); + vboot_executed = 1; } } From 0ca944b16fd6c0d25bee666206ada43f95024ce3 Mon Sep 17 00:00:00 2001 From: Arthur Heymans Date: Wed, 20 Nov 2019 19:51:06 +0100 Subject: [PATCH 0436/1242] security/tpm: Drop CAR_GLOBAL_MIGRATION support Change-Id: I1c09eda6164efb390de4626f52aafba59962f9c4 Signed-off-by: Arthur Heymans Reviewed-on: https://review.coreboot.org/c/coreboot/+/37029 Reviewed-by: HAOUAS Elyes Reviewed-by: Patrick Georgi Tested-by: build bot (Jenkins) --- src/drivers/crb/tis.c | 9 +- src/drivers/crb/tpm.c | 1 - src/drivers/i2c/tpm/cr50.c | 32 +++---- src/drivers/i2c/tpm/tis.c | 41 ++++----- src/drivers/i2c/tpm/tis_atmel.c | 1 - src/drivers/i2c/tpm/tpm.c | 77 +++++++--------- src/drivers/pc80/tpm/tis.c | 7 +- src/drivers/spi/tpm/tis.c | 9 +- src/drivers/spi/tpm/tpm.c | 91 ++++++++----------- src/security/tpm/tspi/log.c | 1 - src/security/tpm/tss/tcg-1.2/tss.c | 8 +- src/security/tpm/tss/tcg-2.0/tss.c | 18 ++-- src/security/tpm/tss/tcg-2.0/tss_marshaling.c | 36 ++++---- src/security/tpm/tss/vendor/cr50/cr50.c | 1 - 14 files changed, 144 insertions(+), 188 deletions(-) diff --git a/src/drivers/crb/tis.c b/src/drivers/crb/tis.c index b7a5df4829..f2aba48297 100644 --- a/src/drivers/crb/tis.c +++ b/src/drivers/crb/tis.c @@ -11,7 +11,6 @@ * GNU General Public License for more details. */ -#include #include #include #include @@ -21,7 +20,7 @@ #include "tpm.h" #include "chip.h" -static unsigned tpm_is_open CAR_GLOBAL; +static unsigned int tpm_is_open; static const struct { uint16_t vid; @@ -45,7 +44,7 @@ static const char *tis_get_dev_name(struct tpm2_info *info) int tis_open(void) { - if (car_get_var(tpm_is_open)) { + if (tpm_is_open) { printk(BIOS_ERR, "%s called twice.\n", __func__); return -1; } @@ -63,13 +62,13 @@ int tis_open(void) int tis_close(void) { - if (car_get_var(tpm_is_open)) { + if (tpm_is_open) { /* * Do we need to do something here, like waiting for a * transaction to stop? */ - car_set_var(tpm_is_open, 0); + tpm_is_open = 0; } return 0; diff --git a/src/drivers/crb/tpm.c b/src/drivers/crb/tpm.c index 0393417e74..f2b7903e4c 100644 --- a/src/drivers/crb/tpm.c +++ b/src/drivers/crb/tpm.c @@ -15,7 +15,6 @@ */ #include -#include #include #include #include diff --git a/src/drivers/i2c/tpm/cr50.c b/src/drivers/i2c/tpm/cr50.c index f9a286241e..f386dacb0b 100644 --- a/src/drivers/i2c/tpm/cr50.c +++ b/src/drivers/i2c/tpm/cr50.c @@ -27,7 +27,6 @@ * instead of just reading header and determining the remainder */ -#include #include #include #include @@ -55,15 +54,15 @@ struct tpm_inf_dev { uint8_t buf[CR50_MAX_BUFSIZE + sizeof(uint8_t)]; }; -static struct tpm_inf_dev g_tpm_dev CAR_GLOBAL; +static struct tpm_inf_dev g_tpm_dev; __weak int tis_plat_irq_status(void) { - static int warning_displayed CAR_GLOBAL; + static int warning_displayed; - if (!car_get_var(warning_displayed)) { + if (!warning_displayed) { printk(BIOS_WARNING, "WARNING: tis_plat_irq_status() not implemented, wasting 20ms to wait on Cr50!\n"); - car_set_var(warning_displayed, 1); + warning_displayed = 1; } mdelay(CR50_TIMEOUT_NOIRQ_MS); @@ -102,16 +101,14 @@ static int cr50_i2c_wait_tpm_ready(struct tpm_chip *chip) static int cr50_i2c_read(struct tpm_chip *chip, uint8_t addr, uint8_t *buffer, size_t len) { - struct tpm_inf_dev *tpm_dev = car_get_var_ptr(&g_tpm_dev); - - if (tpm_dev->addr == 0) + if (g_tpm_dev.addr == 0) return -1; /* Clear interrupt before starting transaction */ tis_plat_irq_status(); /* Send the register address byte to the TPM */ - if (i2c_write_raw(tpm_dev->bus, tpm_dev->addr, &addr, 1)) { + if (i2c_write_raw(g_tpm_dev.bus, g_tpm_dev.addr, &addr, 1)) { printk(BIOS_ERR, "%s: Address write failed\n", __func__); return -1; } @@ -121,7 +118,7 @@ static int cr50_i2c_read(struct tpm_chip *chip, uint8_t addr, return -1; /* Read response data from the TPM */ - if (i2c_read_raw(tpm_dev->bus, tpm_dev->addr, buffer, len)) { + if (i2c_read_raw(g_tpm_dev.bus, g_tpm_dev.addr, buffer, len)) { printk(BIOS_ERR, "%s: Read response failed\n", __func__); return -1; } @@ -146,22 +143,20 @@ static int cr50_i2c_read(struct tpm_chip *chip, uint8_t addr, static int cr50_i2c_write(struct tpm_chip *chip, uint8_t addr, uint8_t *buffer, size_t len) { - struct tpm_inf_dev *tpm_dev = car_get_var_ptr(&g_tpm_dev); - - if (tpm_dev->addr == 0) + if (g_tpm_dev.addr == 0) return -1; if (len > CR50_MAX_BUFSIZE) return -1; /* Prepend the 'register address' to the buffer */ - tpm_dev->buf[0] = addr; - memcpy(tpm_dev->buf + 1, buffer, len); + g_tpm_dev.buf[0] = addr; + memcpy(g_tpm_dev.buf + 1, buffer, len); /* Clear interrupt before starting transaction */ tis_plat_irq_status(); /* Send write request buffer with address */ - if (i2c_write_raw(tpm_dev->bus, tpm_dev->addr, tpm_dev->buf, len + 1)) { + if (i2c_write_raw(g_tpm_dev.bus, g_tpm_dev.addr, g_tpm_dev.buf, len + 1)) { printk(BIOS_ERR, "%s: Error writing to TPM\n", __func__); return -1; } @@ -492,7 +487,6 @@ static int cr50_i2c_probe(struct tpm_chip *chip, uint32_t *did_vid) int tpm_vendor_init(struct tpm_chip *chip, unsigned int bus, uint32_t dev_addr) { - struct tpm_inf_dev *tpm_dev = car_get_var_ptr(&g_tpm_dev); uint32_t did_vid = 0; if (dev_addr == 0) { @@ -500,8 +494,8 @@ int tpm_vendor_init(struct tpm_chip *chip, unsigned int bus, uint32_t dev_addr) return -1; } - tpm_dev->bus = bus; - tpm_dev->addr = dev_addr; + g_tpm_dev.bus = bus; + g_tpm_dev.addr = dev_addr; cr50_vendor_init(chip); diff --git a/src/drivers/i2c/tpm/tis.c b/src/drivers/i2c/tpm/tis.c index e466c45c9f..d791a56af5 100644 --- a/src/drivers/i2c/tpm/tis.c +++ b/src/drivers/i2c/tpm/tis.c @@ -12,7 +12,6 @@ * GNU General Public License for more details. */ -#include #include #include #include @@ -27,25 +26,24 @@ #include "tpm.h" /* global structure for tpm chip data */ -static struct tpm_chip g_chip CAR_GLOBAL; +static struct tpm_chip g_chip; #define TPM_CMD_COUNT_BYTE 2 #define TPM_CMD_ORDINAL_BYTE 6 int tis_open(void) { - struct tpm_chip *chip = car_get_var_ptr(&g_chip); int rc; - if (chip->is_open) { + if (g_chip.is_open) { printk(BIOS_DEBUG, "tis_open() called twice.\n"); return -1; } - rc = tpm_vendor_init(chip, CONFIG_DRIVER_TPM_I2C_BUS, + rc = tpm_vendor_init(&g_chip, CONFIG_DRIVER_TPM_I2C_BUS, CONFIG_DRIVER_TPM_I2C_ADDR); if (rc < 0) - chip->is_open = 0; + g_chip.is_open = 0; if (rc) return -1; @@ -55,11 +53,9 @@ int tis_open(void) int tis_close(void) { - struct tpm_chip *chip = car_get_var_ptr(&g_chip); - - if (chip->is_open) { - tpm_vendor_cleanup(chip); - chip->is_open = 0; + if (g_chip.is_open) { + tpm_vendor_cleanup(&g_chip); + g_chip.is_open = 0; } return 0; @@ -76,12 +72,11 @@ static ssize_t tpm_transmit(const uint8_t *sbuf, size_t sbufsiz, void *rbuf, { int rc; uint32_t count; - struct tpm_chip *chip = car_get_var_ptr(&g_chip); memcpy(&count, sbuf + TPM_CMD_COUNT_BYTE, sizeof(count)); count = be32_to_cpu(count); - if (!chip->vendor.send || !chip->vendor.status || !chip->vendor.cancel) + if (!g_chip.vendor.send || !g_chip.vendor.status || !g_chip.vendor.cancel) return -1; if (count == 0) { @@ -94,8 +89,8 @@ static ssize_t tpm_transmit(const uint8_t *sbuf, size_t sbufsiz, void *rbuf, return -1; } - ASSERT(chip->vendor.send); - rc = chip->vendor.send(chip, (uint8_t *) sbuf, count); + ASSERT(g_chip.vendor.send); + rc = g_chip.vendor.send(&g_chip, (uint8_t *) sbuf, count); if (rc < 0) { printk(BIOS_DEBUG, "tpm_transmit: tpm_send error\n"); goto out; @@ -103,14 +98,14 @@ static ssize_t tpm_transmit(const uint8_t *sbuf, size_t sbufsiz, void *rbuf, int timeout = 2 * 60 * 1000; /* two minutes timeout */ while (timeout) { - ASSERT(chip->vendor.status); - uint8_t status = chip->vendor.status(chip); - if ((status & chip->vendor.req_complete_mask) == - chip->vendor.req_complete_val) { + ASSERT(g_chip.vendor.status); + uint8_t status = g_chip.vendor.status(&g_chip); + if ((status & g_chip.vendor.req_complete_mask) == + g_chip.vendor.req_complete_val) { goto out_recv; } - if (status == chip->vendor.req_canceled) { + if (status == g_chip.vendor.req_canceled) { printk(BIOS_DEBUG, "tpm_transmit: Operation Canceled\n"); rc = -1; @@ -120,15 +115,15 @@ static ssize_t tpm_transmit(const uint8_t *sbuf, size_t sbufsiz, void *rbuf, timeout--; } - ASSERT(chip->vendor.cancel); - chip->vendor.cancel(chip); + ASSERT(g_chip.vendor.cancel); + g_chip.vendor.cancel(&g_chip); printk(BIOS_DEBUG, "tpm_transmit: Operation Timed out\n"); rc = -1; //ETIME; goto out; out_recv: - rc = chip->vendor.recv(chip, (uint8_t *) rbuf, rbufsiz); + rc = g_chip.vendor.recv(&g_chip, (uint8_t *) rbuf, rbufsiz); if (rc < 0) printk(BIOS_DEBUG, "tpm_transmit: tpm_recv: error %d\n", rc); out: diff --git a/src/drivers/i2c/tpm/tis_atmel.c b/src/drivers/i2c/tpm/tis_atmel.c index 42df292615..793418a96a 100644 --- a/src/drivers/i2c/tpm/tis_atmel.c +++ b/src/drivers/i2c/tpm/tis_atmel.c @@ -12,7 +12,6 @@ * GNU General Public License for more details. */ -#include #include #include #include diff --git a/src/drivers/i2c/tpm/tpm.c b/src/drivers/i2c/tpm/tpm.c index e0950849fc..71641d0edc 100644 --- a/src/drivers/i2c/tpm/tpm.c +++ b/src/drivers/i2c/tpm/tpm.c @@ -28,7 +28,6 @@ */ -#include #include #include #include @@ -81,7 +80,7 @@ struct tpm_inf_dev { enum i2c_chip_type chip_type; }; -static struct tpm_inf_dev g_tpm_dev CAR_GLOBAL; +static struct tpm_inf_dev g_tpm_dev; /* * iic_tpm_read() - read from TPM register @@ -99,24 +98,23 @@ static struct tpm_inf_dev g_tpm_dev CAR_GLOBAL; */ static int iic_tpm_read(uint8_t addr, uint8_t *buffer, size_t len) { - struct tpm_inf_dev *tpm_dev = car_get_var_ptr(&g_tpm_dev); int rc; int count; - if (tpm_dev->addr == 0) + if (g_tpm_dev.addr == 0) return -1; - switch (tpm_dev->chip_type) { + switch (g_tpm_dev.chip_type) { case SLB9635: case UNKNOWN: /* slb9635 protocol should work in both cases */ for (count = 0; count < MAX_COUNT; count++) { - rc = i2c_write_raw(tpm_dev->bus, tpm_dev->addr, + rc = i2c_write_raw(g_tpm_dev.bus, g_tpm_dev.addr, &addr, 1); if (rc == 0) break; /* success, break to skip sleep */ - udelay(tpm_dev->sleep_short); + udelay(g_tpm_dev.sleep_short); } if (rc) @@ -127,8 +125,8 @@ static int iic_tpm_read(uint8_t addr, uint8_t *buffer, size_t len) * retrieving the data */ for (count = 0; count < MAX_COUNT; count++) { - udelay(tpm_dev->sleep_short); - rc = i2c_read_raw(tpm_dev->bus, tpm_dev->addr, + udelay(g_tpm_dev.sleep_short); + rc = i2c_read_raw(g_tpm_dev.bus, g_tpm_dev.addr, buffer, len); if (rc == 0) break; /* success, break to skip sleep */ @@ -144,23 +142,23 @@ static int iic_tpm_read(uint8_t addr, uint8_t *buffer, size_t len) * retries should usually not be needed, but are kept just to * be safe on the safe side. */ - struct i2c_msg aseg = { .flags = 0, .slave = tpm_dev->addr, + struct i2c_msg aseg = { .flags = 0, .slave = g_tpm_dev.addr, .buf = &addr, .len = 1 }; struct i2c_msg dseg = { .flags = I2C_M_RD, - .slave = tpm_dev->addr, + .slave = g_tpm_dev.addr, .buf = buffer, .len = len }; for (count = 0; count < MAX_COUNT; count++) { - rc = i2c_transfer(tpm_dev->bus, &aseg, 1) || - i2c_transfer(tpm_dev->bus, &dseg, 1); + rc = i2c_transfer(g_tpm_dev.bus, &aseg, 1) || + i2c_transfer(g_tpm_dev.bus, &dseg, 1); if (rc == 0) break; /* break here to skip sleep */ - udelay(tpm_dev->sleep_short); + udelay(g_tpm_dev.sleep_short); } } } /* take care of 'guard time' */ - udelay(tpm_dev->sleep_short); + udelay(g_tpm_dev.sleep_short); if (rc) return -1; @@ -171,7 +169,6 @@ static int iic_tpm_write_generic(uint8_t addr, uint8_t *buffer, size_t len, unsigned int sleep_time, uint8_t max_count) { - struct tpm_inf_dev *tpm_dev = car_get_var_ptr(&g_tpm_dev); int rc = 0; int count; @@ -182,14 +179,14 @@ static int iic_tpm_write_generic(uint8_t addr, uint8_t *buffer, size_t len, } /* prepare send buffer */ - tpm_dev->buf[0] = addr; - memcpy(&(tpm_dev->buf[1]), buffer, len); + g_tpm_dev.buf[0] = addr; + memcpy(&(g_tpm_dev.buf[1]), buffer, len); - if (tpm_dev->addr == 0) + if (g_tpm_dev.addr == 0) return -1; for (count = 0; count < max_count; count++) { - rc = i2c_write_raw(tpm_dev->bus, tpm_dev->addr, - tpm_dev->buf, len + 1); + rc = i2c_write_raw(g_tpm_dev.bus, g_tpm_dev.addr, + g_tpm_dev.buf, len + 1); if (rc == 0) break; /* success, break to skip sleep */ @@ -197,7 +194,7 @@ static int iic_tpm_write_generic(uint8_t addr, uint8_t *buffer, size_t len, } /* take care of 'guard time' */ - udelay(tpm_dev->sleep_short); + udelay(g_tpm_dev.sleep_short); if (rc) return -1; @@ -222,8 +219,7 @@ static int iic_tpm_write_generic(uint8_t addr, uint8_t *buffer, size_t len, */ static int iic_tpm_write(uint8_t addr, uint8_t *buffer, size_t len) { - struct tpm_inf_dev *tpm_dev = car_get_var_ptr(&g_tpm_dev); - return iic_tpm_write_generic(addr, buffer, len, tpm_dev->sleep_short, + return iic_tpm_write_generic(addr, buffer, len, g_tpm_dev.sleep_short, MAX_COUNT); } @@ -233,8 +229,7 @@ static int iic_tpm_write(uint8_t addr, uint8_t *buffer, size_t len) * */ static int iic_tpm_write_long(uint8_t addr, uint8_t *buffer, size_t len) { - struct tpm_inf_dev *tpm_dev = car_get_var_ptr(&g_tpm_dev); - return iic_tpm_write_generic(addr, buffer, len, tpm_dev->sleep_long, + return iic_tpm_write_generic(addr, buffer, len, g_tpm_dev.sleep_long, MAX_COUNT_LONG); } @@ -479,17 +474,16 @@ out_err: int tpm_vendor_probe(unsigned int bus, uint32_t addr) { - struct tpm_inf_dev *tpm_dev = car_get_var_ptr(&g_tpm_dev); struct stopwatch sw; uint8_t buf = 0; int ret; long sw_run_duration = SLEEP_DURATION_PROBE_MS; - tpm_dev->chip_type = UNKNOWN; - tpm_dev->bus = bus; - tpm_dev->addr = addr; - tpm_dev->sleep_short = SLEEP_DURATION; - tpm_dev->sleep_long = SLEEP_DURATION_LONG; + g_tpm_dev.chip_type = UNKNOWN; + g_tpm_dev.bus = bus; + g_tpm_dev.addr = addr; + g_tpm_dev.sleep_short = SLEEP_DURATION; + g_tpm_dev.sleep_long = SLEEP_DURATION_LONG; /* * Probe TPM. Check if the TPM_ACCESS register's ValidSts bit is set(1) @@ -521,7 +515,6 @@ int tpm_vendor_probe(unsigned int bus, uint32_t addr) int tpm_vendor_init(struct tpm_chip *chip, unsigned int bus, uint32_t dev_addr) { - struct tpm_inf_dev *tpm_dev = car_get_var_ptr(&g_tpm_dev); uint32_t vendor; if (dev_addr == 0) { @@ -529,11 +522,11 @@ int tpm_vendor_init(struct tpm_chip *chip, unsigned int bus, uint32_t dev_addr) return -1; } - tpm_dev->chip_type = UNKNOWN; - tpm_dev->bus = bus; - tpm_dev->addr = dev_addr; - tpm_dev->sleep_short = SLEEP_DURATION; - tpm_dev->sleep_long = SLEEP_DURATION_LONG; + g_tpm_dev.chip_type = UNKNOWN; + g_tpm_dev.bus = bus; + g_tpm_dev.addr = dev_addr; + g_tpm_dev.sleep_short = SLEEP_DURATION; + g_tpm_dev.sleep_long = SLEEP_DURATION_LONG; memset(&chip->vendor, 0, sizeof(struct tpm_vendor_specific)); chip->is_open = 1; @@ -554,9 +547,9 @@ int tpm_vendor_init(struct tpm_chip *chip, unsigned int bus, uint32_t dev_addr) goto out_err; if (vendor == TPM_TIS_I2C_DID_VID_9645) { - tpm_dev->chip_type = SLB9645; + g_tpm_dev.chip_type = SLB9645; } else if (be32_to_cpu(vendor) == TPM_TIS_I2C_DID_VID_9635) { - tpm_dev->chip_type = SLB9635; + g_tpm_dev.chip_type = SLB9635; } else { printk(BIOS_DEBUG, "Vendor ID 0x%08x not recognized.\n", vendor); @@ -564,8 +557,8 @@ int tpm_vendor_init(struct tpm_chip *chip, unsigned int bus, uint32_t dev_addr) } printk(BIOS_DEBUG, "I2C TPM %u:%02x (chip type %s device-id 0x%X)\n", - tpm_dev->bus, tpm_dev->addr, - chip_name[tpm_dev->chip_type], vendor >> 16); + g_tpm_dev.bus, g_tpm_dev.addr, + chip_name[g_tpm_dev.chip_type], vendor >> 16); /* * A timeout query to TPM can be placed here. diff --git a/src/drivers/pc80/tpm/tis.c b/src/drivers/pc80/tpm/tis.c index 1baab26b00..39fa70db3f 100644 --- a/src/drivers/pc80/tpm/tis.c +++ b/src/drivers/pc80/tpm/tis.c @@ -31,7 +31,6 @@ #include #include #include -#include #include #include "chip.h" @@ -162,7 +161,7 @@ static const struct vendor_name vendor_names[] = { * Cached vendor/device ID pair to indicate that the device has been already * discovered */ -static u32 vendor_dev_id CAR_GLOBAL; +static u32 vendor_dev_id; static inline u8 tpm_read_status(int locality) { @@ -402,7 +401,7 @@ static u32 tis_probe(void) u16 vid, did; int i; - if (car_get_var(vendor_dev_id)) + if (vendor_dev_id) return 0; /* Already probed. */ didvid = tpm_read_did_vid(0); @@ -411,7 +410,7 @@ static u32 tis_probe(void) return TPM_DRIVER_ERR; } - car_set_var(vendor_dev_id, didvid); + vendor_dev_id = didvid; vid = didvid & 0xffff; did = (didvid >> 16) & 0xffff; diff --git a/src/drivers/spi/tpm/tis.c b/src/drivers/spi/tpm/tis.c index b50ab0a88c..7d42b7c424 100644 --- a/src/drivers/spi/tpm/tis.c +++ b/src/drivers/spi/tpm/tis.c @@ -4,13 +4,12 @@ * found in the LICENSE file. */ -#include #include #include #include "tpm.h" -static unsigned tpm_is_open CAR_GLOBAL; +static unsigned tpm_is_open; static const struct { uint16_t vid; @@ -34,7 +33,7 @@ static const char *tis_get_dev_name(struct tpm2_info *info) int tis_open(void) { - if (car_get_var(tpm_is_open)) { + if (tpm_is_open) { printk(BIOS_ERR, "tis_open() called twice.\n"); return -1; } @@ -43,13 +42,13 @@ int tis_open(void) int tis_close(void) { - if (car_get_var(tpm_is_open)) { + if (tpm_is_open) { /* * Do we need to do something here, like waiting for a * transaction to stop? */ - car_set_var(tpm_is_open, 0); + tpm_is_open = 0; } return 0; diff --git a/src/drivers/spi/tpm/tpm.c b/src/drivers/spi/tpm/tpm.c index 270b15b471..d3d36c9160 100644 --- a/src/drivers/spi/tpm/tpm.c +++ b/src/drivers/spi/tpm/tpm.c @@ -15,7 +15,6 @@ * Specification Revision 00.43". */ -#include #include #include #include @@ -40,10 +39,10 @@ #define CR50_TIMEOUT_INIT_MS 30000 /* Very long timeout for TPM init */ /* SPI slave structure for TPM device. */ -static struct spi_slave g_spi_slave CAR_GLOBAL; +static struct spi_slave g_spi_slave; /* Cached TPM device identification. */ -static struct tpm2_info g_tpm_info CAR_GLOBAL; +static struct tpm2_info g_tpm_info; /* * TODO(vbendeb): make CONFIG_DEBUG_TPM an int to allow different level of @@ -61,16 +60,16 @@ typedef struct { void tpm2_get_info(struct tpm2_info *info) { - *info = car_get_var(g_tpm_info); + *info = g_tpm_info; } __weak int tis_plat_irq_status(void) { - static int warning_displayed CAR_GLOBAL; + static int warning_displayed; - if (!car_get_var(warning_displayed)) { + if (!warning_displayed) { printk(BIOS_WARNING, "WARNING: tis_plat_irq_status() not implemented, wasting 10ms to wait on Cr50!\n"); - car_set_var(warning_displayed, 1); + warning_displayed = 1; } mdelay(10); @@ -109,9 +108,8 @@ static int start_transaction(int read_write, size_t bytes, unsigned int addr) uint8_t byte; int i; struct stopwatch sw; - static int tpm_sync_needed CAR_GLOBAL; - static struct stopwatch wake_up_sw CAR_GLOBAL; - struct spi_slave *spi_slave = car_get_var_ptr(&g_spi_slave); + static int tpm_sync_needed; + static struct stopwatch wake_up_sw; /* * First Cr50 access in each coreboot stage where TPM is used will be * prepended by a wake up pulse on the CS line. @@ -119,7 +117,7 @@ static int start_transaction(int read_write, size_t bytes, unsigned int addr) int wakeup_needed = 1; /* Wait for TPM to finish previous transaction if needed */ - if (car_get_var(tpm_sync_needed)) { + if (tpm_sync_needed) { tpm_sync(); /* * During the first invocation of this function on each stage @@ -127,17 +125,17 @@ static int start_transaction(int read_write, size_t bytes, unsigned int addr) * value is zero), during all following invocations the * stopwatch below is guaranteed to be started. */ - if (!stopwatch_expired(car_get_var_ptr(&wake_up_sw))) + if (!stopwatch_expired(&wake_up_sw)) wakeup_needed = 0; } else { - car_set_var(tpm_sync_needed, 1); + tpm_sync_needed = 1; } if (wakeup_needed) { /* Just in case Cr50 is asleep. */ - spi_claim_bus(spi_slave); + spi_claim_bus(&g_spi_slave); udelay(1); - spi_release_bus(spi_slave); + spi_release_bus(&g_spi_slave); udelay(100); } @@ -146,7 +144,7 @@ static int start_transaction(int read_write, size_t bytes, unsigned int addr) * SPI slave activity, let's be conservative and limit the * window to 900 ms. */ - stopwatch_init_msecs_expire(car_get_var_ptr(&wake_up_sw), 900); + stopwatch_init_msecs_expire(&wake_up_sw, 900); /* * The first byte of the frame header encodes the transaction type @@ -160,7 +158,7 @@ static int start_transaction(int read_write, size_t bytes, unsigned int addr) header.body[i + 1] = (addr >> (8 * (2 - i))) & 0xff; /* CS assert wakes up the slave. */ - spi_claim_bus(spi_slave); + spi_claim_bus(&g_spi_slave); /* * The TCG TPM over SPI specification introduces the notion of SPI @@ -187,7 +185,7 @@ static int start_transaction(int read_write, size_t bytes, unsigned int addr) * to require to stall the master, this would present an issue. * crosbug.com/p/52132 has been opened to track this. */ - spi_xfer(spi_slave, header.body, sizeof(header.body), NULL, 0); + spi_xfer(&g_spi_slave, header.body, sizeof(header.body), NULL, 0); /* * Now poll the bus until TPM removes the stall bit. Give it up to 100 @@ -198,10 +196,10 @@ static int start_transaction(int read_write, size_t bytes, unsigned int addr) do { if (stopwatch_expired(&sw)) { printk(BIOS_ERR, "TPM flow control failure\n"); - spi_release_bus(spi_slave); + spi_release_bus(&g_spi_slave); return 0; } - spi_xfer(spi_slave, NULL, 0, &byte, 1); + spi_xfer(&g_spi_slave, NULL, 0, &byte, 1); } while (!(byte & 1)); return 1; } @@ -214,11 +212,10 @@ static void trace_dump(const char *prefix, uint32_t reg, size_t bytes, const uint8_t *buffer, int force) { - static char prev_prefix CAR_GLOBAL; - static unsigned prev_reg CAR_GLOBAL; - static int current_char CAR_GLOBAL; + static char prev_prefix; + static unsigned int prev_reg; + static int current_char; const int BYTES_PER_LINE = 32; - int *current_char_ptr = car_get_var_ptr(¤t_char); if (!force) { if (!debug_level_) @@ -232,12 +229,11 @@ static void trace_dump(const char *prefix, uint32_t reg, * Do not print register address again if the last dump print was for * that register. */ - if ((car_get_var(prev_prefix) != *prefix) || - (car_get_var(prev_reg) != reg)) { - car_set_var(prev_prefix, *prefix); - car_set_var(prev_reg, reg); + if (prev_prefix != *prefix || (prev_reg != reg)) { + prev_prefix = *prefix; + prev_reg = reg; printk(BIOS_DEBUG, "\n%s %2.2x:", prefix, reg); - *current_char_ptr = 0; + current_char = 0; } if ((reg != TPM_DATA_FIFO_REG) && (bytes == 4)) { @@ -254,12 +250,12 @@ static void trace_dump(const char *prefix, uint32_t reg, * quantiites is printed byte at a time. */ for (i = 0; i < bytes; i++) { - if (*current_char_ptr && - !(*current_char_ptr % BYTES_PER_LINE)) { + if (current_char && + !(current_char % BYTES_PER_LINE)) { printk(BIOS_DEBUG, "\n "); - *current_char_ptr = 0; + current_char = 0; } - (*current_char_ptr)++; + (current_char)++; printk(BIOS_DEBUG, " %2.2x", buffer[i]); } } @@ -271,8 +267,7 @@ static void trace_dump(const char *prefix, uint32_t reg, */ static void write_bytes(const void *buffer, size_t bytes) { - struct spi_slave *spi_slave = car_get_var_ptr(&g_spi_slave); - spi_xfer(spi_slave, buffer, bytes, NULL, 0); + spi_xfer(&g_spi_slave, buffer, bytes, NULL, 0); } /* @@ -281,8 +276,7 @@ static void write_bytes(const void *buffer, size_t bytes) */ static void read_bytes(void *buffer, size_t bytes) { - struct spi_slave *spi_slave = car_get_var_ptr(&g_spi_slave); - spi_xfer(spi_slave, NULL, 0, buffer, bytes); + spi_xfer(&g_spi_slave, NULL, 0, buffer, bytes); } /* @@ -293,12 +287,11 @@ static void read_bytes(void *buffer, size_t bytes) */ static int tpm2_write_reg(unsigned int reg_number, const void *buffer, size_t bytes) { - struct spi_slave *spi_slave = car_get_var_ptr(&g_spi_slave); trace_dump("W", reg_number, bytes, buffer, 0); if (!start_transaction(false, bytes, reg_number)) return 0; write_bytes(buffer, bytes); - spi_release_bus(spi_slave); + spi_release_bus(&g_spi_slave); return 1; } @@ -311,13 +304,12 @@ static int tpm2_write_reg(unsigned int reg_number, const void *buffer, size_t by */ static int tpm2_read_reg(unsigned int reg_number, void *buffer, size_t bytes) { - struct spi_slave *spi_slave = car_get_var_ptr(&g_spi_slave); if (!start_transaction(true, bytes, reg_number)) { memset(buffer, 0, bytes); return 0; } read_bytes(buffer, bytes); - spi_release_bus(spi_slave); + spi_release_bus(&g_spi_slave); trace_dump("R", reg_number, bytes, buffer, 0); return 1; } @@ -424,10 +416,8 @@ int tpm2_init(struct spi_slave *spi_if) uint32_t did_vid, status; uint8_t cmd; int retries; - struct tpm2_info *tpm_info = car_get_var_ptr(&g_tpm_info); - struct spi_slave *spi_slave = car_get_var_ptr(&g_spi_slave); - memcpy(spi_slave, spi_if, sizeof(*spi_if)); + memcpy(&g_spi_slave, spi_if, sizeof(*spi_if)); /* clear any pending IRQs */ tis_plat_irq_status(); @@ -484,15 +474,15 @@ int tpm2_init(struct spi_slave *spi_if) * structure. */ tpm2_read_reg(TPM_RID_REG, &cmd, sizeof(cmd)); - tpm_info->vendor_id = did_vid & 0xffff; - tpm_info->device_id = did_vid >> 16; - tpm_info->revision = cmd; + g_tpm_info.vendor_id = did_vid & 0xffff; + g_tpm_info.device_id = did_vid >> 16; + g_tpm_info.revision = cmd; printk(BIOS_INFO, "Connected to device vid:did:rid of %4.4x:%4.4x:%2.2x\n", - tpm_info->vendor_id, tpm_info->device_id, tpm_info->revision); + g_tpm_info.vendor_id, g_tpm_info.device_id, g_tpm_info.revision); /* Let's report device FW version if available. */ - if (tpm_info->vendor_id == 0x1ae0) { + if (g_tpm_info.vendor_id == 0x1ae0) { int chunk_count = 0; size_t chunk_size; /* @@ -619,10 +609,9 @@ size_t tpm2_process_command(const void *tpm2_command, size_t command_size, uint8_t *rsp_body = tpm2_response; union fifo_transfer_buffer fifo_buffer; const int HEADER_SIZE = 6; - struct tpm2_info *tpm_info = car_get_var_ptr(&g_tpm_info); /* Do not try using an uninitialized TPM. */ - if (!tpm_info->vendor_id) + if (!g_tpm_info.vendor_id) return 0; /* Skip the two byte tag, read the size field. */ diff --git a/src/security/tpm/tspi/log.c b/src/security/tpm/tspi/log.c index 9986d9a7c5..8a9cc88827 100644 --- a/src/security/tpm/tspi/log.c +++ b/src/security/tpm/tspi/log.c @@ -15,7 +15,6 @@ #include #include -#include #include #include #include diff --git a/src/security/tpm/tss/tcg-1.2/tss.c b/src/security/tpm/tss/tcg-1.2/tss.c index b11d6a3d16..9bc72d2733 100644 --- a/src/security/tpm/tss/tcg-1.2/tss.c +++ b/src/security/tpm/tss/tcg-1.2/tss.c @@ -14,7 +14,6 @@ * time. */ -#include #include #include #include @@ -148,12 +147,11 @@ static uint32_t send(const uint8_t *command) /* Exported functions. */ -static uint8_t tlcl_init_done CAR_GLOBAL; +static uint8_t tlcl_init_done; uint32_t tlcl_lib_init(void) { - uint8_t done = car_get_var(tlcl_init_done); - if (done) + if (tlcl_init_done) return VB2_SUCCESS; if (tis_init()) @@ -161,7 +159,7 @@ uint32_t tlcl_lib_init(void) if (tis_open()) return VB2_ERROR_UNKNOWN; - car_set_var(tlcl_init_done, 1); + tlcl_init_done = 1; return VB2_SUCCESS; } diff --git a/src/security/tpm/tss/tcg-2.0/tss.c b/src/security/tpm/tss/tcg-2.0/tss.c index 16e40fe569..6bc30966ff 100644 --- a/src/security/tpm/tss/tcg-2.0/tss.c +++ b/src/security/tpm/tss/tcg-2.0/tss.c @@ -5,7 +5,6 @@ * found in the LICENSE file. */ -#include #include #include #include @@ -30,11 +29,9 @@ void *tpm_process_command(TPM_CC command, void *command_body) size_t in_size; const uint8_t *sendb; /* Command/response buffer. */ - static uint8_t cr_buffer[TPM_BUFFER_SIZE] CAR_GLOBAL; + static uint8_t cr_buffer[TPM_BUFFER_SIZE]; - uint8_t *cr_buffer_ptr = car_get_var_ptr(cr_buffer); - - obuf_init(&ob, cr_buffer_ptr, sizeof(cr_buffer)); + obuf_init(&ob, cr_buffer, sizeof(cr_buffer)); if (tpm_marshal_command(command, command_body, &ob) < 0) { printk(BIOS_ERR, "command %#x\n", command); @@ -44,12 +41,12 @@ void *tpm_process_command(TPM_CC command, void *command_body) sendb = obuf_contents(&ob, &out_size); in_size = sizeof(cr_buffer); - if (tis_sendrecv(sendb, out_size, cr_buffer_ptr, &in_size)) { + if (tis_sendrecv(sendb, out_size, cr_buffer, &in_size)) { printk(BIOS_ERR, "tpm transaction failed\n"); return NULL; } - ibuf_init(&ib, cr_buffer_ptr, in_size); + ibuf_init(&ib, cr_buffer, in_size); return tpm_unmarshal_response(command, &ib); } @@ -173,13 +170,12 @@ uint32_t tlcl_force_clear(void) return TPM_SUCCESS; } -static uint8_t tlcl_init_done CAR_GLOBAL; +static uint8_t tlcl_init_done; /* This function is called directly by vboot, uses vboot return types. */ uint32_t tlcl_lib_init(void) { - uint8_t done = car_get_var(tlcl_init_done); - if (done) + if (tlcl_init_done) return VB2_SUCCESS; if (tis_init()) { @@ -192,7 +188,7 @@ uint32_t tlcl_lib_init(void) return VB2_ERROR_UNKNOWN; } - car_set_var(tlcl_init_done, 1); + tlcl_init_done = 1; return VB2_SUCCESS; } diff --git a/src/security/tpm/tss/tcg-2.0/tss_marshaling.c b/src/security/tpm/tss/tcg-2.0/tss_marshaling.c index 1bf211a898..720e7c4b68 100644 --- a/src/security/tpm/tss/tcg-2.0/tss_marshaling.c +++ b/src/security/tpm/tss/tcg-2.0/tss_marshaling.c @@ -5,7 +5,6 @@ * found in the LICENSE file. */ -#include #include #include #include @@ -15,7 +14,7 @@ #include #include -static uint16_t tpm_tag CAR_GLOBAL; /* Depends on the command type. */ +static uint16_t tpm_tag; /* Depends on the command type. */ #define unmarshal_TPM_CAP(a, b) ibuf_read_be32(a, b) #define unmarshal_TPM_CC(a, b) ibuf_read_be32(a, b) @@ -165,7 +164,7 @@ static int marshal_common_session_header(struct obuf *ob, struct tpm2_session_header session_header; int rc = 0; - car_set_var(tpm_tag, TPM_ST_SESSIONS); + tpm_tag = TPM_ST_SESSIONS; for (i = 0; i < handle_count; i++) rc |= marshal_TPM_HANDLE(ob, handles[i]); @@ -270,7 +269,7 @@ static int marshal_hierarchy_control(struct obuf *ob, int rc = 0; struct tpm2_session_header session_header; - car_set_var(tpm_tag, TPM_ST_SESSIONS); + tpm_tag = TPM_ST_SESSIONS; rc |= marshal_TPM_HANDLE(ob, TPM_RH_PLATFORM); memset(&session_header, 0, sizeof(session_header)); @@ -335,7 +334,7 @@ int tpm_marshal_command(TPM_CC command, void *tpm_command_body, struct obuf *ob) const size_t hdr_sz = sizeof(uint16_t) + 2 * sizeof(uint32_t); int rc = 0; - car_set_var(tpm_tag, TPM_ST_NO_SESSIONS); + tpm_tag = TPM_ST_NO_SESSIONS; if (obuf_splice_current(ob, &ob_hdr, hdr_sz) < 0) return -1; @@ -407,7 +406,7 @@ int tpm_marshal_command(TPM_CC command, void *tpm_command_body, struct obuf *ob) return rc; /* Fix up the command header with known values. */ - rc |= obuf_write_be16(&ob_hdr, car_get_var(tpm_tag)); + rc |= obuf_write_be16(&ob_hdr, tpm_tag); rc |= obuf_write_be32(&ob_hdr, obuf_nr_written(ob)); return rc; @@ -552,23 +551,22 @@ static int unmarshal_vendor_command(struct ibuf *ib, struct tpm2_response *tpm_unmarshal_response(TPM_CC command, struct ibuf *ib) { - static struct tpm2_response tpm2_static_resp CAR_GLOBAL; - struct tpm2_response *tpm2_resp = car_get_var_ptr(&tpm2_static_resp); + static struct tpm2_response tpm2_static_resp; int rc = 0; - rc |= ibuf_read_be16(ib, &tpm2_resp->hdr.tpm_tag); - rc |= ibuf_read_be32(ib, &tpm2_resp->hdr.tpm_size); - rc |= unmarshal_TPM_CC(ib, &tpm2_resp->hdr.tpm_code); + rc |= ibuf_read_be16(ib, &tpm2_static_resp.hdr.tpm_tag); + rc |= ibuf_read_be32(ib, &tpm2_static_resp.hdr.tpm_size); + rc |= unmarshal_TPM_CC(ib, &tpm2_static_resp.hdr.tpm_code); if (rc != 0) return NULL; if (ibuf_remaining(ib) == 0) { - if (tpm2_resp->hdr.tpm_size != ibuf_nr_read(ib)) + if (tpm2_static_resp.hdr.tpm_size != ibuf_nr_read(ib)) printk(BIOS_ERR, "%s: size mismatch in response to command %#x\n", __func__, command); - return tpm2_resp; + return &tpm2_static_resp; } switch (command) { @@ -577,11 +575,11 @@ struct tpm2_response *tpm_unmarshal_response(TPM_CC command, struct ibuf *ib) break; case TPM2_GetCapability: - rc |= unmarshal_get_capability(ib, &tpm2_resp->gc); + rc |= unmarshal_get_capability(ib, &tpm2_static_resp.gc); break; case TPM2_NV_Read: - rc |= unmarshal_nv_read(ib, &tpm2_resp->nvr); + rc |= unmarshal_nv_read(ib, &tpm2_static_resp.nvr); break; case TPM2_Hierarchy_Control: @@ -595,7 +593,7 @@ struct tpm2_response *tpm_unmarshal_response(TPM_CC command, struct ibuf *ib) break; case TPM2_CR50_VENDOR_COMMAND: - rc |= unmarshal_vendor_command(ib, &tpm2_resp->vcr); + rc |= unmarshal_vendor_command(ib, &tpm2_static_resp.vcr); break; default: @@ -608,7 +606,7 @@ struct tpm2_response *tpm_unmarshal_response(TPM_CC command, struct ibuf *ib) "Request to unmarshal unexpected command %#x," " code %#x", __func__, __LINE__, command, - tpm2_resp->hdr.tpm_code); + tpm2_static_resp.hdr.tpm_code); sz_left = ibuf_remaining(ib); data = ibuf_oob_drain(ib, sz_left); @@ -627,7 +625,7 @@ struct tpm2_response *tpm_unmarshal_response(TPM_CC command, struct ibuf *ib) printk(BIOS_INFO, "%s:%d got %d bytes back in response to %#x," " failed to parse (%zd)\n", - __func__, __LINE__, tpm2_resp->hdr.tpm_size, + __func__, __LINE__, tpm2_static_resp.hdr.tpm_size, command, ibuf_remaining(ib)); return NULL; } @@ -636,5 +634,5 @@ struct tpm2_response *tpm_unmarshal_response(TPM_CC command, struct ibuf *ib) __func__); /* The entire message have been parsed. */ - return tpm2_resp; + return &tpm2_static_resp; } diff --git a/src/security/tpm/tss/vendor/cr50/cr50.c b/src/security/tpm/tss/vendor/cr50/cr50.c index 4f128dcac1..ec69df4ac9 100644 --- a/src/security/tpm/tss/vendor/cr50/cr50.c +++ b/src/security/tpm/tss/vendor/cr50/cr50.c @@ -4,7 +4,6 @@ * found in the LICENSE file. */ -#include #include #include #include From 1a71163675b7f0f06dcb6a95b2f411ac5cac3381 Mon Sep 17 00:00:00 2001 From: Arthur Heymans Date: Wed, 20 Nov 2019 20:38:29 +0100 Subject: [PATCH 0437/1242] lib/timestamp.c: Drop CAR_GLOBAL_MIGRATION support MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Change-Id: I0ba97d7a2da02ba24de6932678c3bc936aa6554b Signed-off-by: Arthur Heymans Reviewed-on: https://review.coreboot.org/c/coreboot/+/37030 Reviewed-by: Kyösti Mälkki Tested-by: build bot (Jenkins) --- src/lib/timestamp.c | 17 ++++++----------- 1 file changed, 6 insertions(+), 11 deletions(-) diff --git a/src/lib/timestamp.c b/src/lib/timestamp.c index dcb3124567..7c7210cc5a 100644 --- a/src/lib/timestamp.c +++ b/src/lib/timestamp.c @@ -22,7 +22,6 @@ #include #include #include -#include #include #define MAX_TIMESTAMPS 192 @@ -31,7 +30,7 @@ DECLARE_OPTIONAL_REGION(timestamp); /* This points to the active timestamp_table and can change within a stage as CBMEM comes available. */ -static struct timestamp_table *glob_ts_table CAR_GLOBAL; +static struct timestamp_table *glob_ts_table; static void timestamp_cache_init(struct timestamp_table *ts_cache, uint64_t base) @@ -94,21 +93,17 @@ static int timestamp_should_run(void) static struct timestamp_table *timestamp_table_get(void) { - struct timestamp_table *ts_table; + if (glob_ts_table) + return glob_ts_table; - ts_table = car_get_ptr(glob_ts_table); - if (ts_table) - return ts_table; + glob_ts_table = timestamp_cache_get(); - ts_table = timestamp_cache_get(); - car_set_ptr(glob_ts_table, ts_table); - - return ts_table; + return glob_ts_table; } static void timestamp_table_set(struct timestamp_table *ts) { - car_set_ptr(glob_ts_table, ts); + glob_ts_table = ts; } static const char *timestamp_name(enum timestamp_id id) From f0664cfc7b305aed1726dc30d0940d5d7339e2c2 Mon Sep 17 00:00:00 2001 From: Arthur Heymans Date: Wed, 20 Nov 2019 19:55:27 +0100 Subject: [PATCH 0438/1242] lib/spd_bin.c: Drop CAR_GLOBAL_MIGRATION support MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Change-Id: I1c307e1d5532929de6d876ce9215515ab1cf4652 Signed-off-by: Arthur Heymans Reviewed-on: https://review.coreboot.org/c/coreboot/+/37031 Reviewed-by: HAOUAS Elyes Reviewed-by: Kyösti Mälkki Tested-by: build bot (Jenkins) --- src/include/spd_bin.h | 1 - src/lib/spd_bin.c | 8 +++----- 2 files changed, 3 insertions(+), 6 deletions(-) diff --git a/src/include/spd_bin.h b/src/include/spd_bin.h index 3de60a95ce..f144b1461c 100644 --- a/src/include/spd_bin.h +++ b/src/include/spd_bin.h @@ -16,7 +16,6 @@ #ifndef SPD_BIN_H #define SPD_BIN_H -#include #include #include diff --git a/src/lib/spd_bin.c b/src/lib/spd_bin.c index 62e600b2c8..71fe036ef7 100644 --- a/src/lib/spd_bin.c +++ b/src/lib/spd_bin.c @@ -20,7 +20,7 @@ #include #include -static u8 spd_data[CONFIG_DIMM_MAX * CONFIG_DIMM_SPD_SIZE] CAR_GLOBAL; +static u8 spd_data[CONFIG_DIMM_MAX * CONFIG_DIMM_SPD_SIZE]; void dump_spd_info(struct spd_block *blk) { @@ -258,12 +258,10 @@ static void get_spd(u8 *spd, u8 addr) void get_spd_smbus(struct spd_block *blk) { u8 i; - unsigned char *spd_data_ptr = car_get_var_ptr(&spd_data); - for (i = 0 ; i < CONFIG_DIMM_MAX; i++) { - get_spd(spd_data_ptr + i * CONFIG_DIMM_SPD_SIZE, + get_spd(&spd_data[i * CONFIG_DIMM_SPD_SIZE], blk->addr_map[i]); - blk->spd_array[i] = spd_data_ptr + i * CONFIG_DIMM_SPD_SIZE; + blk->spd_array[i] = &spd_data[i * CONFIG_DIMM_SPD_SIZE]; } update_spd_len(blk); From dba22d2f9d309df0857159a22110339b04cd43cb Mon Sep 17 00:00:00 2001 From: Arthur Heymans Date: Wed, 20 Nov 2019 19:57:49 +0100 Subject: [PATCH 0439/1242] lib/fmap.c: Drop CAR_GLOBAL_MIGRATION support Change-Id: Ibf80d3e37f702c75c30394a14ce0a91af84a6b93 Signed-off-by: Arthur Heymans Reviewed-on: https://review.coreboot.org/c/coreboot/+/37033 Reviewed-by: HAOUAS Elyes Reviewed-by: Patrick Georgi Tested-by: build bot (Jenkins) --- src/lib/fmap.c | 24 +++++++++--------------- 1 file changed, 9 insertions(+), 15 deletions(-) diff --git a/src/lib/fmap.c b/src/lib/fmap.c index 48aab8f3d5..af26152d13 100644 --- a/src/lib/fmap.c +++ b/src/lib/fmap.c @@ -13,7 +13,6 @@ * GNU General Public License for more details. */ -#include #include #include #include @@ -29,11 +28,11 @@ * See http://code.google.com/p/flashmap/ for more information on FMAP. */ -static int fmap_print_once CAR_GLOBAL; -static struct mem_region_device fmap_cache CAR_GLOBAL; +static int fmap_print_once; +static struct mem_region_device fmap_cache; #define print_once(...) do { \ - if (!car_get_var(fmap_print_once)) \ + if (!fmap_print_once) \ printk(__VA_ARGS__); \ } while (0) @@ -55,7 +54,7 @@ static void report(const struct fmap *fmap) fmap->name, fmap->ver_major, fmap->ver_minor, FMAP_OFFSET); print_once(BIOS_DEBUG, "FMAP: base = %#llx size = %#x #areas = %d\n", (long long)fmap->base, fmap->size, fmap->nareas); - car_set_var(fmap_print_once, 1); + fmap_print_once = 1; } static void setup_preram_cache(struct mem_region_device *cache_mrdev) @@ -114,15 +113,13 @@ static int find_fmap_directory(struct region_device *fmrd) { const struct region_device *boot; struct fmap *fmap; - struct mem_region_device *cache; size_t offset = FMAP_OFFSET; /* Try FMAP cache first */ - cache = car_get_var_ptr(&fmap_cache); - if (!region_device_sz(&cache->rdev)) - setup_preram_cache(cache); - if (region_device_sz(&cache->rdev)) - return rdev_chain_full(fmrd, &cache->rdev); + if (!region_device_sz(&fmap_cache.rdev)) + setup_preram_cache(&fmap_cache); + if (region_device_sz(&fmap_cache.rdev)) + return rdev_chain_full(fmrd, &fmap_cache.rdev); boot_device_init(); boot = boot_device_ro(); @@ -277,9 +274,6 @@ ssize_t fmap_overwrite_area(const char *name, const void *buffer, size_t size) static void fmap_register_cbmem_cache(int unused) { const struct cbmem_entry *e; - struct mem_region_device *mdev; - - mdev = car_get_var_ptr(&fmap_cache); /* Find the FMAP cache installed by previous stage */ e = cbmem_entry_find(CBMEM_ID_FMAP); @@ -287,7 +281,7 @@ static void fmap_register_cbmem_cache(int unused) if (!e) return; - mem_region_device_ro_init(mdev, cbmem_entry_start(e), cbmem_entry_size(e)); + mem_region_device_ro_init(&fmap_cache, cbmem_entry_start(e), cbmem_entry_size(e)); } /* From 95b3f286a83b5433ec08499cc4a4d83943c546c1 Mon Sep 17 00:00:00 2001 From: Arthur Heymans Date: Wed, 20 Nov 2019 21:23:16 +0100 Subject: [PATCH 0440/1242] ec/google/chromeec: Drop CAR_GLOBAL_MIGRATION support Change-Id: I09bca1897920871a6b29c25dc2bad94a8061da29 Signed-off-by: Arthur Heymans Reviewed-on: https://review.coreboot.org/c/coreboot/+/37038 Reviewed-by: HAOUAS Elyes Reviewed-by: Patrick Georgi Tested-by: build bot (Jenkins) --- src/ec/google/chromeec/ec.c | 3 +-- src/ec/google/chromeec/ec_spi.c | 2 -- 2 files changed, 1 insertion(+), 4 deletions(-) diff --git a/src/ec/google/chromeec/ec.c b/src/ec/google/chromeec/ec.c index a9921467f4..5dff16252b 100644 --- a/src/ec/google/chromeec/ec.c +++ b/src/ec/google/chromeec/ec.c @@ -17,7 +17,6 @@ #include #include #include -#include #include #include #include @@ -231,7 +230,7 @@ bool google_chromeec_is_uhepi_supported(void) #define UHEPI_SUPPORTED 1 #define UHEPI_NOT_SUPPORTED 2 - static int uhepi_support CAR_GLOBAL; + static int uhepi_support; if (!uhepi_support) { uhepi_support = google_chromeec_check_feature diff --git a/src/ec/google/chromeec/ec_spi.c b/src/ec/google/chromeec/ec_spi.c index c47d419647..84a605bf9c 100644 --- a/src/ec/google/chromeec/ec_spi.c +++ b/src/ec/google/chromeec/ec_spi.c @@ -20,8 +20,6 @@ #include #include -/* This is assuming that this driver is not used on x86. If that changes, this - might need to become a CAR_GLOBAL or maybe even more complicated. */ static struct stopwatch cs_cooldown_sw; static const long cs_cooldown_us = 200; From 7c2fd97c05a7d7af342af04a4aa5e190eaa9c121 Mon Sep 17 00:00:00 2001 From: Arthur Heymans Date: Wed, 20 Nov 2019 21:25:10 +0100 Subject: [PATCH 0441/1242] drivers/vpd/vpd.c: Drop CAR_GLOBAL_MIGRATION support Change-Id: Idf522a822ddd54ee8b48312bed762c29783a2e45 Signed-off-by: Arthur Heymans Reviewed-on: https://review.coreboot.org/c/coreboot/+/37039 Reviewed-by: HAOUAS Elyes Reviewed-by: Patrick Georgi Tested-by: build bot (Jenkins) --- src/drivers/vpd/vpd.c | 32 ++++++++++++-------------------- src/drivers/vpd/vpd.h | 2 +- 2 files changed, 13 insertions(+), 21 deletions(-) diff --git a/src/drivers/vpd/vpd.c b/src/drivers/vpd/vpd.c index 10f5703e6a..b81a719176 100644 --- a/src/drivers/vpd/vpd.c +++ b/src/drivers/vpd/vpd.c @@ -4,7 +4,6 @@ * found in the LICENSE file. */ -#include #include #include #include @@ -24,7 +23,7 @@ struct vpd_gets_arg { int matched; }; -struct vpd_blob g_vpd_blob CAR_GLOBAL = {0}; +struct vpd_blob g_vpd_blob; /* * returns the size of data in a VPD 2.0 formatted fmap region, or 0. @@ -86,13 +85,10 @@ static void vpd_get_blob(void) if (ro_vpd_size == 0 && rw_vpd_size == 0) return; - struct vpd_blob *blob = car_get_var_ptr(&g_vpd_blob); - if (!blob) - return; - blob->ro_base = NULL; - blob->ro_size = 0; - blob->rw_base = NULL; - blob->rw_size = 0; + g_vpd_blob.ro_base = NULL; + g_vpd_blob.ro_size = 0; + g_vpd_blob.rw_base = NULL; + g_vpd_blob.rw_size = 0; struct region_device vpd; @@ -105,9 +101,9 @@ static void vpd_get_blob(void) } rdev_chain(&vpd, &vpd, GOOGLE_VPD_2_0_OFFSET, region_device_sz(&vpd) - GOOGLE_VPD_2_0_OFFSET); - blob->ro_base = (uint8_t *)(rdev_mmap_full(&vpd) + + g_vpd_blob.ro_base = (uint8_t *)(rdev_mmap_full(&vpd) + sizeof(struct google_vpd_info)); - blob->ro_size = ro_vpd_size; + g_vpd_blob.ro_size = ro_vpd_size; } if (rw_vpd_size) { if (fmap_locate_area_as_rdev("RW_VPD", &vpd)) { @@ -118,23 +114,19 @@ static void vpd_get_blob(void) } rdev_chain(&vpd, &vpd, GOOGLE_VPD_2_0_OFFSET, region_device_sz(&vpd) - GOOGLE_VPD_2_0_OFFSET); - blob->rw_base = (uint8_t *)(rdev_mmap_full(&vpd) + + g_vpd_blob.rw_base = (uint8_t *)(rdev_mmap_full(&vpd) + sizeof(struct google_vpd_info)); - blob->rw_size = rw_vpd_size; + g_vpd_blob.rw_size = rw_vpd_size; } - blob->initialized = true; + g_vpd_blob.initialized = true; } const struct vpd_blob *vpd_load_blob(void) { - struct vpd_blob *blob = NULL; - - blob = car_get_var_ptr(&g_vpd_blob); - - if (blob && blob->initialized == false) + if (g_vpd_blob.initialized == false) vpd_get_blob(); - return blob; + return &g_vpd_blob; } static int vpd_gets_callback(const uint8_t *key, uint32_t key_len, diff --git a/src/drivers/vpd/vpd.h b/src/drivers/vpd/vpd.h index 1bae5132cd..05b7db8f6d 100644 --- a/src/drivers/vpd/vpd.h +++ b/src/drivers/vpd/vpd.h @@ -28,7 +28,7 @@ struct vpd_blob { extern struct vpd_blob g_vpd_blob; /* - * This function loads g_vpd_blob CAR_GLOBAL variable. + * This function loads g_vpd_blob global variable. * The variable is initialized if it was not. */ const struct vpd_blob *vpd_load_blob(void); From 2b77881564e2e9f9f9c6adb2200d55a3434fff47 Mon Sep 17 00:00:00 2001 From: Arthur Heymans Date: Wed, 20 Nov 2019 21:27:33 +0100 Subject: [PATCH 0442/1242] drivers/usb/ehci_debug.c: Drop CAR_GLOBAL_MIGRATION support MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Change-Id: Ib0cd32893ad9540ae55e61e85fb03d194ee55894 Signed-off-by: Arthur Heymans Reviewed-on: https://review.coreboot.org/c/coreboot/+/37040 Reviewed-by: HAOUAS Elyes Reviewed-by: Kyösti Mälkki Tested-by: build bot (Jenkins) --- src/drivers/usb/ehci_debug.c | 15 +++++++-------- 1 file changed, 7 insertions(+), 8 deletions(-) diff --git a/src/drivers/usb/ehci_debug.c b/src/drivers/usb/ehci_debug.c index 398f5db321..e77cd85f75 100644 --- a/src/drivers/usb/ehci_debug.c +++ b/src/drivers/usb/ehci_debug.c @@ -17,7 +17,6 @@ #include #include #include -#include #include #include @@ -59,12 +58,12 @@ struct ehci_debug_info { static int dbgp_enabled(void); static void dbgp_print_data(struct ehci_dbg_port *ehci_debug); -static struct ehci_debug_info glob_dbg_info CAR_GLOBAL; -static struct ehci_debug_info * glob_dbg_info_p CAR_GLOBAL; +static struct ehci_debug_info glob_dbg_info; +static struct ehci_debug_info * glob_dbg_info_p; static inline struct ehci_debug_info *dbgp_ehci_info(void) { - if (car_get_ptr(glob_dbg_info_p) == NULL) { + if (glob_dbg_info_p == NULL) { struct ehci_debug_info *info; if (ENV_BOOTBLOCK || ENV_VERSTAGE || ENV_ROMSTAGE) { /* The message likely does not show if we hit this. */ @@ -74,9 +73,9 @@ static inline struct ehci_debug_info *dbgp_ehci_info(void) } else { info = &glob_dbg_info; } - car_set_ptr(glob_dbg_info_p, info); + glob_dbg_info_p = info; } - return car_get_ptr(glob_dbg_info_p); + return glob_dbg_info_p; } static int dbgp_wait_until_complete(struct ehci_dbg_port *ehci_debug) @@ -713,7 +712,7 @@ static void migrate_ehci_debug(int is_recovery) if (dbg_info_cbmem == NULL) return; memcpy(dbg_info_cbmem, dbg_info, sizeof(*dbg_info)); - car_set_ptr(glob_dbg_info_p, dbg_info_cbmem); + glob_dbg_info_p = dbg_info_cbmem; return; } @@ -721,7 +720,7 @@ static void migrate_ehci_debug(int is_recovery) /* Use state in CBMEM. */ dbg_info_cbmem = cbmem_find(CBMEM_ID_EHCI_DEBUG); if (dbg_info_cbmem) - car_set_ptr(glob_dbg_info_p, dbg_info_cbmem); + glob_dbg_info_p = dbg_info_cbmem; } rv = usbdebug_hw_init(false); From 5fadb46b362bed70d386823dcf0041e0d6ebd372 Mon Sep 17 00:00:00 2001 From: Arthur Heymans Date: Wed, 20 Nov 2019 21:28:15 +0100 Subject: [PATCH 0443/1242] drivers/uart/oxpcie_early.c: Drop CAR_GLOBAL_MIGRATION support MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Change-Id: Ibea14a4cfb7285af42a7493742636c8dc8fe0a33 Signed-off-by: Arthur Heymans Reviewed-on: https://review.coreboot.org/c/coreboot/+/37041 Reviewed-by: HAOUAS Elyes Reviewed-by: Kyösti Mälkki Tested-by: build bot (Jenkins) --- src/drivers/uart/oxpcie_early.c | 7 +++---- 1 file changed, 3 insertions(+), 4 deletions(-) diff --git a/src/drivers/uart/oxpcie_early.c b/src/drivers/uart/oxpcie_early.c index f6b4040807..d12b42ace2 100644 --- a/src/drivers/uart/oxpcie_early.c +++ b/src/drivers/uart/oxpcie_early.c @@ -14,12 +14,11 @@ #include #include #include -#include #include #include #include -static unsigned int oxpcie_present CAR_GLOBAL; +static unsigned int oxpcie_present; static DEVTREE_CONST u32 uart0_base = CONFIG_EARLY_PCI_MMIO_BASE + 0x1000; int pci_early_device_probe(u8 bus, u8 dev, u32 mmio_base) @@ -58,13 +57,13 @@ int pci_early_device_probe(u8 bus, u8 dev, u32 mmio_base) reg16 |= PCI_COMMAND_MEMORY; pci_s_write_config16(device, PCI_COMMAND, reg16); - car_set_var(oxpcie_present, 1); + oxpcie_present = 1; return 0; } static int oxpcie_uart_active(void) { - return (car_get_var(oxpcie_present)); + return oxpcie_present; } uintptr_t uart_platform_base(int idx) From c2a9c426701a45cfcb624e8d3befb258c74abe06 Mon Sep 17 00:00:00 2001 From: Arthur Heymans Date: Wed, 20 Nov 2019 21:33:31 +0100 Subject: [PATCH 0444/1242] drivers/spi/spi_flash.c: Drop CAR_GLOBAL_MIGRATION support Change-Id: Ie1d01f589289239c453c2cc38cc1e25f903399ea Signed-off-by: Arthur Heymans Reviewed-on: https://review.coreboot.org/c/coreboot/+/37042 Reviewed-by: HAOUAS Elyes Reviewed-by: Patrick Georgi Tested-by: build bot (Jenkins) --- src/drivers/spi/spi_flash.c | 11 +++++------ 1 file changed, 5 insertions(+), 6 deletions(-) diff --git a/src/drivers/spi/spi_flash.c b/src/drivers/spi/spi_flash.c index 7b5266a280..f0d01593f3 100644 --- a/src/drivers/spi/spi_flash.c +++ b/src/drivers/spi/spi_flash.c @@ -12,7 +12,6 @@ * GNU General Public License for more details. */ -#include #include #include #include @@ -522,7 +521,7 @@ int spi_flash_set_write_protected(const struct spi_flash *flash, return ret; } -static uint32_t volatile_group_count CAR_GLOBAL; +static uint32_t volatile_group_count; int spi_flash_volatile_group_begin(const struct spi_flash *flash) { @@ -532,12 +531,12 @@ int spi_flash_volatile_group_begin(const struct spi_flash *flash) if (!CONFIG(SPI_FLASH_HAS_VOLATILE_GROUP)) return ret; - count = car_get_var(volatile_group_count); + count = volatile_group_count; if (count == 0) ret = chipset_volatile_group_begin(flash); count++; - car_set_var(volatile_group_count, count); + volatile_group_count = count; return ret; } @@ -549,10 +548,10 @@ int spi_flash_volatile_group_end(const struct spi_flash *flash) if (!CONFIG(SPI_FLASH_HAS_VOLATILE_GROUP)) return ret; - count = car_get_var(volatile_group_count); + count = volatile_group_count; assert(count == 0); count--; - car_set_var(volatile_group_count, count); + volatile_group_count = count; if (count == 0) ret = chipset_volatile_group_end(flash); From 22be29e23b278bc0dd344832a8e3cab1eeb07f7a Mon Sep 17 00:00:00 2001 From: Arthur Heymans Date: Wed, 20 Nov 2019 22:02:33 +0100 Subject: [PATCH 0445/1242] drivers/pc80/pc/i8254.c: Drop CAR_GLOBAL_MIGRATION support MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Change-Id: Ibe9b353ce050b4718e07bccb958dbe3d2312e741 Signed-off-by: Arthur Heymans Reviewed-on: https://review.coreboot.org/c/coreboot/+/37045 Reviewed-by: Kyösti Mälkki Reviewed-by: HAOUAS Elyes Tested-by: build bot (Jenkins) --- src/drivers/pc80/pc/i8254.c | 19 +++++++------------ 1 file changed, 7 insertions(+), 12 deletions(-) diff --git a/src/drivers/pc80/pc/i8254.c b/src/drivers/pc80/pc/i8254.c index 5090f0c85b..9d23d4697e 100644 --- a/src/drivers/pc80/pc/i8254.c +++ b/src/drivers/pc80/pc/i8254.c @@ -11,7 +11,6 @@ * GNU General Public License for more details. */ -#include #include #include #include @@ -107,23 +106,19 @@ bad_ctc: } #if CONFIG(UNKNOWN_TSC_RATE) -static u32 g_timer_tsc CAR_GLOBAL; +static u32 g_timer_tsc; unsigned long tsc_freq_mhz(void) { - u32 tsc; + if (g_timer_tsc > 0) + return g_timer_tsc; - tsc = car_get_var(g_timer_tsc); - if (tsc > 0) - return tsc; - - tsc = calibrate_tsc_with_pit(); + g_timer_tsc = calibrate_tsc_with_pit(); /* Set some semi-ridiculous rate if approximation fails. */ - if (tsc == 0) - tsc = 5000; + if (g_timer_tsc == 0) + g_timer_tsc = 5000; - car_set_var(g_timer_tsc, tsc); - return tsc; + return g_timer_tsc; } #endif From 48ae50c3d278f414154f4ef31f581294b4bc2c5e Mon Sep 17 00:00:00 2001 From: Arthur Heymans Date: Wed, 20 Nov 2019 22:07:40 +0100 Subject: [PATCH 0446/1242] console/init.c: Drop CAR_GLOBAL_MIGRATION support MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Change-Id: If1150a811a41add88b80fbecda4a66c2bd322825 Signed-off-by: Arthur Heymans Reviewed-on: https://review.coreboot.org/c/coreboot/+/37047 Reviewed-by: Kyösti Mälkki Tested-by: build bot (Jenkins) --- src/console/init.c | 9 ++++----- 1 file changed, 4 insertions(+), 5 deletions(-) diff --git a/src/console/init.c b/src/console/init.c index d4818580e4..911dbd0546 100644 --- a/src/console/init.c +++ b/src/console/init.c @@ -12,7 +12,6 @@ * GNU General Public License for more details. */ -#include #include #include #include @@ -24,12 +23,12 @@ /* Mutable console log level only allowed when RAM comes online. */ #define CONSOLE_LEVEL_CONST !ENV_STAGE_HAS_DATA_SECTION -static int console_inited CAR_GLOBAL; +static int console_inited; static int console_loglevel = CONFIG_DEFAULT_CONSOLE_LOGLEVEL; static inline int get_log_level(void) { - if (car_get_var(console_inited) == 0) + if (console_inited == 0) return -1; if (CONSOLE_LEVEL_CONST) return get_console_loglevel(); @@ -78,14 +77,14 @@ asmlinkage void console_init(void) init_log_level(); if (CONFIG(DEBUG_CONSOLE_INIT)) - car_set_var(console_inited, 1); + console_inited = 1; if (CONFIG(EARLY_PCI_BRIDGE) && !ENV_SMM && !ENV_RAMSTAGE) pci_early_bridge_init(); console_hw_init(); - car_set_var(console_inited, 1); + console_inited = 1; printk(BIOS_NOTICE, "\n\ncoreboot-%s%s %s " ENV_STRING " starting (log level: %i)...\n", coreboot_version, coreboot_extra_version, coreboot_build, From 9e1ea54b1859ab24a073eb981aa5163b5f2b0cfd Mon Sep 17 00:00:00 2001 From: Arthur Heymans Date: Wed, 20 Nov 2019 22:09:15 +0100 Subject: [PATCH 0447/1242] arch/x86/exception.c: Drop CAR_GLOBAL_MIGRATION support Change-Id: I9e0d62d45e5b11a0c2f0867633cde2378f305ec8 Signed-off-by: Arthur Heymans Reviewed-on: https://review.coreboot.org/c/coreboot/+/37048 Reviewed-by: HAOUAS Elyes Reviewed-by: Patrick Georgi Tested-by: build bot (Jenkins) --- src/arch/x86/exception.c | 17 +++++++---------- 1 file changed, 7 insertions(+), 10 deletions(-) diff --git a/src/arch/x86/exception.c b/src/arch/x86/exception.c index b88f4a7553..a599e798c1 100644 --- a/src/arch/x86/exception.c +++ b/src/arch/x86/exception.c @@ -12,7 +12,6 @@ */ #include -#include #include #include #include @@ -569,7 +568,7 @@ static const uintptr_t intr_entries[] = { (uintptr_t)vec16, (uintptr_t)vec17, (uintptr_t)vec18, (uintptr_t)vec19, }; -static struct intr_gate idt[ARRAY_SIZE(intr_entries)] __aligned(8) CAR_GLOBAL; +static struct intr_gate idt[ARRAY_SIZE(intr_entries)] __aligned(8); static inline uint16_t get_cs(void) { @@ -620,21 +619,19 @@ asmlinkage void exception_init(void) { int i; uint16_t segment; - struct intr_gate *gates; segment = get_cs(); - gates = car_get_var_ptr(idt); /* Initialize IDT. */ for (i = 0; i < ARRAY_SIZE(idt); i++) { - gates[i].offset_0 = intr_entries[i]; - gates[i].segsel = segment; - gates[i].flags = IGATE_FLAGS; - gates[i].offset_1 = intr_entries[i] >> 16; + idt[i].offset_0 = intr_entries[i]; + idt[i].segsel = segment; + idt[i].flags = IGATE_FLAGS; + idt[i].offset_1 = intr_entries[i] >> 16; #if ENV_X86_64 - gates[i].offset_2 = intr_entries[i] >> 32; + idt[i].offset_2 = intr_entries[i] >> 32; #endif } - load_idt(gates, sizeof(idt)); + load_idt(idt, sizeof(idt)); } From 4e223db66cb19febe15f4dbf2700704fdb2fb0db Mon Sep 17 00:00:00 2001 From: Arthur Heymans Date: Wed, 20 Nov 2019 22:10:05 +0100 Subject: [PATCH 0448/1242] cpu/x86/tsc/delay_tsc.c: Drop CAR_GLOBAL_MIGRATION support Change-Id: I0a1e9fcea54444a84cc0a6ac30fe7d053261bb1c Signed-off-by: Arthur Heymans Reviewed-on: https://review.coreboot.org/c/coreboot/+/37049 Reviewed-by: Patrick Georgi Reviewed-by: HAOUAS Elyes Tested-by: build bot (Jenkins) --- src/cpu/x86/tsc/delay_tsc.c | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/src/cpu/x86/tsc/delay_tsc.c b/src/cpu/x86/tsc/delay_tsc.c index 7aa887ae63..fe6ae5b78e 100644 --- a/src/cpu/x86/tsc/delay_tsc.c +++ b/src/cpu/x86/tsc/delay_tsc.c @@ -11,7 +11,6 @@ * GNU General Public License for more details. */ -#include #include #include #include @@ -49,11 +48,11 @@ static struct monotonic_counter { int initialized; struct mono_time time; uint64_t last_value; -} mono_counter_g CAR_GLOBAL; +} mono_counter_g; static inline struct monotonic_counter *get_monotonic_context(void) { - return car_get_var_ptr(&mono_counter_g); + return &mono_counter_g; } void timer_monotonic_get(struct mono_time *mt) From 5d709789202e305b058fc34b9a65fbd2f2aac1b6 Mon Sep 17 00:00:00 2001 From: Arthur Heymans Date: Wed, 20 Nov 2019 22:11:28 +0100 Subject: [PATCH 0449/1242] cpu/x86/lapic/apic_timer.c: Drop CAR_GLOBAL_MIGRATION support Change-Id: Ideac1a04d6bb1a5e9cc601be7bbfcebe56b4a5da Signed-off-by: Arthur Heymans Reviewed-on: https://review.coreboot.org/c/coreboot/+/37050 Reviewed-by: Patrick Georgi Reviewed-by: HAOUAS Elyes Tested-by: build bot (Jenkins) --- src/cpu/x86/lapic/apic_timer.c | 20 ++++++++------------ 1 file changed, 8 insertions(+), 12 deletions(-) diff --git a/src/cpu/x86/lapic/apic_timer.c b/src/cpu/x86/lapic/apic_timer.c index 58836b5e3f..8f0f7afcfb 100644 --- a/src/cpu/x86/lapic/apic_timer.c +++ b/src/cpu/x86/lapic/apic_timer.c @@ -16,7 +16,6 @@ #include #include #include -#include #include #include @@ -63,18 +62,15 @@ static struct monotonic_counter { int initialized; struct mono_time time; uint32_t last_value; -} mono_counter_g CAR_GLOBAL; +} mono_counter_g; void timer_monotonic_get(struct mono_time *mt) { uint32_t current_tick; uint32_t usecs_elapsed; uint32_t timer_fsb; - struct monotonic_counter *mono_counter; - mono_counter = car_get_var_ptr(&mono_counter_g); - - if (!mono_counter->initialized) { + if (!mono_counter_g.initialized) { init_timer(); timer_fsb = get_timer_fsb(); /* An FSB frequency of 200Mhz provides a 20 second polling @@ -84,22 +80,22 @@ void timer_monotonic_get(struct mono_time *mt) printk(BIOS_WARNING, "apic timer freq (%d) may be too fast.\n", timer_fsb); - mono_counter->last_value = lapic_read(LAPIC_TMCCT); - mono_counter->initialized = 1; + mono_counter_g.last_value = lapic_read(LAPIC_TMCCT); + mono_counter_g.initialized = 1; } timer_fsb = get_timer_fsb(); current_tick = lapic_read(LAPIC_TMCCT); /* Note that the APIC timer counts down. */ - usecs_elapsed = (mono_counter->last_value - current_tick) / timer_fsb; + usecs_elapsed = (mono_counter_g.last_value - current_tick) / timer_fsb; /* Update current time and tick values only if a full tick occurred. */ if (usecs_elapsed) { - mono_time_add_usecs(&mono_counter->time, usecs_elapsed); - mono_counter->last_value = current_tick; + mono_time_add_usecs(&mono_counter_g.time, usecs_elapsed); + mono_counter_g.last_value = current_tick; } /* Save result. */ - *mt = mono_counter->time; + *mt = mono_counter_g.time; } #endif From eb501f054390aa21c90d6e0cf7afcd9e31f827d1 Mon Sep 17 00:00:00 2001 From: Arthur Heymans Date: Wed, 20 Nov 2019 22:13:02 +0100 Subject: [PATCH 0450/1242] commonlib/storage/pci_sdhci.c: Drop CAR_GLOBAL_MIGRATION support Change-Id: Idfbc0cf24000c361c9272fe0f61797de999c9277 Signed-off-by: Arthur Heymans Reviewed-on: https://review.coreboot.org/c/coreboot/+/37052 Reviewed-by: HAOUAS Elyes Reviewed-by: Patrick Georgi Tested-by: build bot (Jenkins) --- src/commonlib/storage/pci_sdhci.c | 13 ++++++------- 1 file changed, 6 insertions(+), 7 deletions(-) diff --git a/src/commonlib/storage/pci_sdhci.c b/src/commonlib/storage/pci_sdhci.c index abc093f777..380f2db557 100644 --- a/src/commonlib/storage/pci_sdhci.c +++ b/src/commonlib/storage/pci_sdhci.c @@ -12,7 +12,6 @@ * GNU General Public License for more details. */ -#include #include #include #include @@ -32,22 +31,22 @@ int sdhci_controller_init(struct sdhci_ctrlr *sdhci_ctrlr, void *ioaddr) struct sd_mmc_ctrlr *new_mem_sdhci_controller(void *ioaddr) { - static bool sdhci_init_done CAR_GLOBAL; - static struct sdhci_ctrlr sdhci_ctrlr CAR_GLOBAL; + static bool sdhci_init_done; + static struct sdhci_ctrlr sdhci_ctrlr; - if (car_get_var(sdhci_init_done) == true) { + if (sdhci_init_done == true) { sdhc_error("Error: SDHCI is already initialized.\n"); return NULL; } - if (sdhci_controller_init(car_get_var_ptr(&sdhci_ctrlr), ioaddr)) { + if (sdhci_controller_init(&sdhci_ctrlr, ioaddr)) { sdhc_error("Error: SDHCI initialization failed.\n"); return NULL; } - car_set_var(sdhci_init_done, true); + sdhci_init_done = true; - return car_get_var_ptr(&sdhci_ctrlr.sd_mmc_ctrlr); + return &sdhci_ctrlr.sd_mmc_ctrlr; } struct sd_mmc_ctrlr *new_pci_sdhci_controller(pci_devfn_t dev) From ff168e9e63256888cc3cf39148c2a5c5712654f8 Mon Sep 17 00:00:00 2001 From: Arthur Heymans Date: Wed, 20 Nov 2019 22:13:53 +0100 Subject: [PATCH 0451/1242] drivers/amd/agesa/def_callouts.c: Drop CAR_GLOBAL_MIGRATION support MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Drop stale comment. Change-Id: Ie9f5271074ac4876f08fa8470dbc35daf5b694b2 Signed-off-by: Arthur Heymans Reviewed-on: https://review.coreboot.org/c/coreboot/+/37053 Reviewed-by: HAOUAS Elyes Reviewed-by: Kyösti Mälkki Tested-by: build bot (Jenkins) --- src/drivers/amd/agesa/def_callouts.c | 1 - 1 file changed, 1 deletion(-) diff --git a/src/drivers/amd/agesa/def_callouts.c b/src/drivers/amd/agesa/def_callouts.c index 4b78d633c9..bce90d90ec 100644 --- a/src/drivers/amd/agesa/def_callouts.c +++ b/src/drivers/amd/agesa/def_callouts.c @@ -175,7 +175,6 @@ AGESA_STATUS agesa_ReadSpd_from_cbfs(UINT32 Func, UINTN Data, VOID *ConfigPtr) #if HAS_AGESA_FCH_OEM_CALLOUT void agesa_fch_oem_config(uintptr_t Data, AMD_CONFIG_PARAMS *StdHeader) { - /* FIXME: CAR_GLOBAL needed here to pass sysinfo. */ struct sysinfo *cb_NA = NULL; if (StdHeader->Func == AMD_INIT_RESET) { From 7c2994bb73641826ab04ad622a0904c1c6096cc0 Mon Sep 17 00:00:00 2001 From: Arthur Heymans Date: Wed, 20 Nov 2019 20:01:11 +0100 Subject: [PATCH 0452/1242] lib/*_stage_cache.c: drop CAR_GLOBAL_MIGRATION support MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Change-Id: I23d5367150649a64ec6d95601f38940dbb5972f8 Signed-off-by: Arthur Heymans Reviewed-on: https://review.coreboot.org/c/coreboot/+/37034 Reviewed-by: HAOUAS Elyes Reviewed-by: Kyösti Mälkki Tested-by: build bot (Jenkins) --- src/lib/cbmem_stage_cache.c | 1 - src/lib/ext_stage_cache.c | 20 +++++++------------- 2 files changed, 7 insertions(+), 14 deletions(-) diff --git a/src/lib/cbmem_stage_cache.c b/src/lib/cbmem_stage_cache.c index 299cb00dcf..dd56f62392 100644 --- a/src/lib/cbmem_stage_cache.c +++ b/src/lib/cbmem_stage_cache.c @@ -13,7 +13,6 @@ * GNU General Public License for more details. */ -#include #include #include #include diff --git a/src/lib/ext_stage_cache.c b/src/lib/ext_stage_cache.c index 354342d41b..466a65f53a 100644 --- a/src/lib/ext_stage_cache.c +++ b/src/lib/ext_stage_cache.c @@ -13,7 +13,6 @@ * GNU General Public License for more details. */ -#include #include #include #include @@ -21,12 +20,7 @@ #include #include -static struct imd imd_stage_cache CAR_GLOBAL = { }; - -static inline struct imd *imd_get(void) -{ - return car_get_var_ptr(&imd_stage_cache); -} +static struct imd imd_stage_cache; static void stage_cache_create_empty(void) { @@ -34,7 +28,7 @@ static void stage_cache_create_empty(void) void *base; size_t size; - imd = imd_get(); + imd = &imd_stage_cache; stage_cache_external_region(&base, &size); imd_handle_init(imd, (void *)(size + (uintptr_t)base)); @@ -50,7 +44,7 @@ static void stage_cache_recover(void) void *base; size_t size; - imd = imd_get(); + imd = &imd_stage_cache; stage_cache_external_region(&base, &size); imd_handle_init(imd, (void *)(size + (uintptr_t)base)); if (imd_recover(imd)) @@ -64,7 +58,7 @@ void stage_cache_add(int stage_id, const struct prog *stage) struct stage_cache *meta; void *c; - imd = imd_get(); + imd = &imd_stage_cache; e = imd_entry_add(imd, CBMEM_ID_STAGEx_META + stage_id, sizeof(*meta)); if (e == NULL) { @@ -99,7 +93,7 @@ void stage_cache_add_raw(int stage_id, const void *base, const size_t size) const struct imd_entry *e; void *c; - imd = imd_get(); + imd = &imd_stage_cache; e = imd_entry_add(imd, CBMEM_ID_STAGEx_RAW + stage_id, size); if (e == NULL) { printk(BIOS_DEBUG, "Error: Can't add %x raw data to imd\n", @@ -122,7 +116,7 @@ void stage_cache_get_raw(int stage_id, void **base, size_t *size) struct imd *imd; const struct imd_entry *e; - imd = imd_get(); + imd = &imd_stage_cache; e = imd_entry_find(imd, CBMEM_ID_STAGEx_RAW + stage_id); if (e == NULL) { printk(BIOS_DEBUG, "Error: Can't find %x raw data to imd\n", @@ -142,7 +136,7 @@ void stage_cache_load_stage(int stage_id, struct prog *stage) void *c; size_t size; - imd = imd_get(); + imd = &imd_stage_cache; e = imd_entry_find(imd, CBMEM_ID_STAGEx_META + stage_id); if (e == NULL) { printk(BIOS_DEBUG, "Error: Can't find %x metadata in imd\n", From 2d33c3e6c3ab2427377b9b532b6590aa87340c4e Mon Sep 17 00:00:00 2001 From: Arthur Heymans Date: Wed, 20 Nov 2019 22:06:47 +0100 Subject: [PATCH 0453/1242] drivers/elog/elog.c: Drop CAR_GLOBAL_MIGRATION support MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Change-Id: I7dcc8d08b40560f105c22454bda1282afaa617da Signed-off-by: Arthur Heymans Reviewed-on: https://review.coreboot.org/c/coreboot/+/37046 Reviewed-by: HAOUAS Elyes Reviewed-by: Kyösti Mälkki Tested-by: build bot (Jenkins) --- src/drivers/elog/elog.c | 127 ++++++++++++++-------------------------- 1 file changed, 43 insertions(+), 84 deletions(-) diff --git a/src/drivers/elog/elog.c b/src/drivers/elog/elog.c index c979e0cef9..768ea28468 100644 --- a/src/drivers/elog/elog.c +++ b/src/drivers/elog/elog.c @@ -14,7 +14,6 @@ #if CONFIG(HAVE_ACPI_RESUME) #include #endif -#include #include #include #include @@ -66,21 +65,14 @@ struct elog_state { enum elog_init_state elog_initialized; }; -static struct elog_state g_elog_state CAR_GLOBAL; +static struct elog_state g_elog_state; #define ELOG_SIZE (4 * KiB) -static uint8_t elog_mirror_buf[ELOG_SIZE] CAR_GLOBAL; - -static void *get_elog_mirror_buffer(void) -{ - return car_get_var_ptr(elog_mirror_buf); -} +static uint8_t elog_mirror_buf[ELOG_SIZE]; static inline struct region_device *mirror_dev_get(void) { - struct elog_state *es = car_get_var_ptr(&g_elog_state); - - return &es->mirror_dev.rdev; + return &g_elog_state.mirror_dev.rdev; } static size_t elog_events_start(void) @@ -91,9 +83,7 @@ static size_t elog_events_start(void) static size_t elog_events_total_space(void) { - struct elog_state *es = car_get_var_ptr(&g_elog_state); - - return region_device_sz(&es->nv_dev) - elog_events_start(); + return region_device_sz(&g_elog_state.nv_dev) - elog_events_start(); } static struct event_header *elog_get_event_buffer(size_t offset, size_t size) @@ -103,10 +93,8 @@ static struct event_header *elog_get_event_buffer(size_t offset, size_t size) static struct event_header *elog_get_next_event_buffer(size_t size) { - struct elog_state *es = car_get_var_ptr(&g_elog_state); - - elog_debug("ELOG: new event at offset 0x%zx\n", es->mirror_last_write); - return elog_get_event_buffer(es->mirror_last_write, size); + elog_debug("ELOG: new event at offset 0x%zx\n", g_elog_state.mirror_last_write); + return elog_get_event_buffer(g_elog_state.mirror_last_write, size); } static void elog_put_event_buffer(struct event_header *event) @@ -116,71 +104,54 @@ static void elog_put_event_buffer(struct event_header *event) static size_t elog_mirror_reset_last_write(void) { - struct elog_state *es = car_get_var_ptr(&g_elog_state); /* Return previous write value. */ - size_t prev = es->mirror_last_write; + size_t prev = g_elog_state.mirror_last_write; - es->mirror_last_write = 0; + g_elog_state.mirror_last_write = 0; return prev; } static void elog_mirror_increment_last_write(size_t size) { - struct elog_state *es = car_get_var_ptr(&g_elog_state); - - es->mirror_last_write += size; + g_elog_state.mirror_last_write += size; } static void elog_nv_reset_last_write(void) { - struct elog_state *es = car_get_var_ptr(&g_elog_state); - - es->nv_last_write = 0; + g_elog_state.nv_last_write = 0; } static void elog_nv_increment_last_write(size_t size) { - struct elog_state *es = car_get_var_ptr(&g_elog_state); - - es->nv_last_write += size; + g_elog_state.nv_last_write += size; } static void elog_nv_needs_possible_erase(void) { - struct elog_state *es = car_get_var_ptr(&g_elog_state); - /* If last write is 0 it means it is already erased. */ - if (es->nv_last_write != 0) - es->nv_last_write = NV_NEEDS_ERASE; + if (g_elog_state.nv_last_write != 0) + g_elog_state.nv_last_write = NV_NEEDS_ERASE; } static bool elog_should_shrink(void) { - struct elog_state *es = car_get_var_ptr(&g_elog_state); - - return es->mirror_last_write >= es->full_threshold; + return g_elog_state.mirror_last_write >= g_elog_state.full_threshold; } static bool elog_nv_needs_erase(void) { - struct elog_state *es = car_get_var_ptr(&g_elog_state); - - return es->nv_last_write == NV_NEEDS_ERASE; + return g_elog_state.nv_last_write == NV_NEEDS_ERASE; } static bool elog_nv_needs_update(void) { - struct elog_state *es = car_get_var_ptr(&g_elog_state); - - return es->nv_last_write != es->mirror_last_write; + return g_elog_state.nv_last_write != g_elog_state.mirror_last_write; } static size_t elog_nv_region_to_update(size_t *offset) { - struct elog_state *es = car_get_var_ptr(&g_elog_state); - - *offset = es->nv_last_write; - return es->mirror_last_write - es->nv_last_write; + *offset = g_elog_state.nv_last_write; + return g_elog_state.mirror_last_write - g_elog_state.nv_last_write; } /* @@ -352,8 +323,6 @@ static void elog_nv_write(size_t offset, size_t size) { void *address; const struct region_device *rdev = mirror_dev_get(); - struct elog_state *es = car_get_var_ptr(&g_elog_state); - if (!size) return; @@ -366,7 +335,7 @@ static void elog_nv_write(size_t offset, size_t size) return; /* Write the data to flash */ - if (rdev_writeat(&es->nv_dev, address, offset, size) != size) + if (rdev_writeat(&g_elog_state.nv_dev, address, offset, size) != size) printk(BIOS_ERR, "ELOG: NV Write failed at 0x%zx, size 0x%zx\n", offset, size); @@ -379,12 +348,11 @@ static void elog_nv_write(size_t offset, size_t size) */ static void elog_nv_erase(void) { - struct elog_state *es = car_get_var_ptr(&g_elog_state); - size_t size = region_device_sz(&es->nv_dev); + size_t size = region_device_sz(&g_elog_state.nv_dev); elog_debug("%s()\n", __func__); /* Erase the sectors in this region */ - if (rdev_eraseat(&es->nv_dev, 0, size) != size) + if (rdev_eraseat(&g_elog_state.nv_dev, 0, size) != size) printk(BIOS_ERR, "ELOG: erase failure.\n"); } @@ -442,12 +410,12 @@ static int elog_scan_flash(void) elog_debug("elog_scan_flash()\n"); void *mirror_buffer; const struct region_device *rdev = mirror_dev_get(); - struct elog_state *es = car_get_var_ptr(&g_elog_state); - size_t size = region_device_sz(&es->nv_dev); + + size_t size = region_device_sz(&g_elog_state.nv_dev); /* Fill memory buffer by reading from SPI */ mirror_buffer = rdev_mmap_full(rdev); - if (rdev_readat(&es->nv_dev, mirror_buffer, 0, size) != size) { + if (rdev_readat(&g_elog_state.nv_dev, mirror_buffer, 0, size) != size) { rdev_munmap(rdev, mirror_buffer); printk(BIOS_ERR, "ELOG: NV read failure.\n"); return -1; @@ -611,10 +579,8 @@ static int elog_prepare_empty(void) static int elog_shrink(void) { - struct elog_state *es = car_get_var_ptr(&g_elog_state); - if (elog_should_shrink()) - return elog_shrink_by_size(es->shrink_size); + return elog_shrink_by_size(g_elog_state.shrink_size); return 0; } @@ -623,18 +589,16 @@ static int elog_shrink(void) */ static inline u8 *elog_flash_offset_to_address(void) { - struct elog_state *es = car_get_var_ptr(&g_elog_state); - /* Only support memory-mapped devices. */ if (!CONFIG(BOOT_DEVICE_MEMORY_MAPPED)) return NULL; - if (!region_device_sz(&es->nv_dev)) + if (!region_device_sz(&g_elog_state.nv_dev)) return NULL; /* Get a view into the read-only boot device. */ - return rdev_mmap(boot_device_ro(), region_device_offset(&es->nv_dev), - region_device_sz(&es->nv_dev)); + return rdev_mmap(boot_device_ro(), region_device_offset(&g_elog_state.nv_dev), + region_device_sz(&g_elog_state.nv_dev)); } /* @@ -646,8 +610,8 @@ int elog_smbios_write_type15(unsigned long *current, int handle) struct smbios_type15 *t = (struct smbios_type15 *)*current; int len = sizeof(struct smbios_type15); uintptr_t log_address; - struct elog_state *es = car_get_var_ptr(&g_elog_state); - size_t elog_size = region_device_sz(&es->nv_dev); + + size_t elog_size = region_device_sz(&g_elog_state.nv_dev); if (CONFIG(ELOG_CBMEM)) { /* Save event log buffer into CBMEM for the OS to read */ @@ -701,8 +665,7 @@ static int elog_find_flash(void) { size_t total_size; size_t reserved_space = ELOG_MIN_AVAILABLE_ENTRIES * MAX_EVENT_SIZE; - struct elog_state *es = car_get_var_ptr(&g_elog_state); - struct region_device *rdev = &es->nv_dev; + struct region_device *rdev = &g_elog_state.nv_dev; elog_debug("%s()\n", __func__); @@ -725,10 +688,10 @@ static int elog_find_flash(void) total_size = MIN(ELOG_SIZE, region_device_sz(rdev)); rdev_chain(rdev, rdev, 0, total_size); - es->full_threshold = total_size - reserved_space; - es->shrink_size = total_size * ELOG_SHRINK_PERCENTAGE / 100; + g_elog_state.full_threshold = total_size - reserved_space; + g_elog_state.shrink_size = total_size * ELOG_SHRINK_PERCENTAGE / 100; - if (reserved_space > es->shrink_size) { + if (reserved_space > g_elog_state.shrink_size) { printk(BIOS_ERR, "ELOG: SHRINK_PERCENTAGE too small\n"); return -1; } @@ -741,8 +704,6 @@ static int elog_sync_to_nv(void) size_t offset; size_t size; bool erase_needed; - struct elog_state *es = car_get_var_ptr(&g_elog_state); - /* Determine if any updates are required. */ if (!elog_nv_needs_update()) return 0; @@ -773,7 +734,7 @@ static int elog_sync_to_nv(void) if (elog_scan_flash() < 0) { printk(BIOS_ERR, "ELOG: Sync back from NV storage failed.\n"); elog_debug_dump_buffer("ELOG: Buffer from NV:\n"); - es->elog_initialized = ELOG_BROKEN; + g_elog_state.elog_initialized = ELOG_BROKEN; return -1; } @@ -815,9 +776,7 @@ int elog_init(void) { void *mirror_buffer; size_t elog_size; - struct elog_state *es = car_get_var_ptr(&g_elog_state); - - switch (es->elog_initialized) { + switch (g_elog_state.elog_initialized) { case ELOG_UNINITIALIZED: break; case ELOG_INITIALIZED: @@ -825,7 +784,7 @@ int elog_init(void) case ELOG_BROKEN: return -1; } - es->elog_initialized = ELOG_BROKEN; + g_elog_state.elog_initialized = ELOG_BROKEN; elog_debug("elog_init()\n"); @@ -833,19 +792,19 @@ int elog_init(void) if (elog_find_flash() < 0) return -1; - elog_size = region_device_sz(&es->nv_dev); - mirror_buffer = get_elog_mirror_buffer(); + elog_size = region_device_sz(&g_elog_state.nv_dev); + mirror_buffer = elog_mirror_buf; if (!mirror_buffer) { printk(BIOS_ERR, "ELOG: Unable to allocate backing store\n"); return -1; } - mem_region_device_rw_init(&es->mirror_dev, mirror_buffer, elog_size); + mem_region_device_rw_init(&g_elog_state.mirror_dev, mirror_buffer, elog_size); /* * Mark as initialized to allow elog_init() to be called and deemed * successful in the prepare/shrink path which adds events. */ - es->elog_initialized = ELOG_INITIALIZED; + g_elog_state.elog_initialized = ELOG_INITIALIZED; /* Load the log from flash and prepare the flash if necessary. */ if (elog_scan_flash() < 0 && elog_prepare_empty() < 0) { @@ -854,8 +813,8 @@ int elog_init(void) } printk(BIOS_INFO, "ELOG: area is %zu bytes, full threshold %d," - " shrink size %d\n", region_device_sz(&es->nv_dev), - es->full_threshold, es->shrink_size); + " shrink size %d\n", region_device_sz(&g_elog_state.nv_dev), + g_elog_state.full_threshold, g_elog_state.shrink_size); if (ENV_PAYLOAD_LOADER) elog_add_boot_count(); From 56d913eedb2f4f0df0b2210f139d857a829bdf96 Mon Sep 17 00:00:00 2001 From: Arthur Heymans Date: Tue, 4 Jun 2019 14:45:13 +0200 Subject: [PATCH 0454/1242] soc/intel/braswell: Use sb/intel/common/spi.c This common implementation is compatible. Change-Id: I540f73514f17d3b135c3222facfe23170d2bb0c8 Signed-off-by: Arthur Heymans Reviewed-on: https://review.coreboot.org/c/coreboot/+/33205 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi --- src/soc/intel/braswell/Kconfig | 1 + src/soc/intel/braswell/Makefile.inc | 4 - src/soc/intel/braswell/include/soc/spi.h | 7 - src/soc/intel/braswell/spi.c | 583 ----------------------- 4 files changed, 1 insertion(+), 594 deletions(-) delete mode 100644 src/soc/intel/braswell/spi.c diff --git a/src/soc/intel/braswell/Kconfig b/src/soc/intel/braswell/Kconfig index f08b58982a..ba2ac68bf8 100644 --- a/src/soc/intel/braswell/Kconfig +++ b/src/soc/intel/braswell/Kconfig @@ -46,6 +46,7 @@ config CPU_SPECIFIC_OPTIONS select INTEL_GMA_SWSMISCI select CPU_INTEL_COMMON select SOUTHBRIDGE_INTEL_COMMON_SMBUS + select SOUTHBRIDGE_INTEL_COMMON_SPI_SILVERMONT config DCACHE_BSP_STACK_SIZE hex diff --git a/src/soc/intel/braswell/Makefile.inc b/src/soc/intel/braswell/Makefile.inc index cc111da485..d2626e865e 100644 --- a/src/soc/intel/braswell/Makefile.inc +++ b/src/soc/intel/braswell/Makefile.inc @@ -20,12 +20,10 @@ romstage-y += iosf.c romstage-y += memmap.c romstage-y += pmutil.c romstage-y += smbus.c -romstage-y += spi.c romstage-y += tsc_freq.c postcar-y += memmap.c postcar-y += iosf.c -postcar-y += spi.c postcar-y += tsc_freq.c ramstage-y += acpi.c @@ -51,7 +49,6 @@ ramstage-y += scc.c ramstage-y += sd.c ramstage-y += smm.c ramstage-y += southcluster.c -ramstage-y += spi.c ramstage-y += tsc_freq.c ramstage-y += xhci.c @@ -60,7 +57,6 @@ ramstage-y += placeholders.c smm-y += lpc_init.c smm-y += pmutil.c smm-y += smihandler.c -smm-y += spi.c smm-y += tsc_freq.c verstage-y += pmutil.c diff --git a/src/soc/intel/braswell/include/soc/spi.h b/src/soc/intel/braswell/include/soc/spi.h index 2d275450fa..47de9da55b 100644 --- a/src/soc/intel/braswell/include/soc/spi.h +++ b/src/soc/intel/braswell/include/soc/spi.h @@ -22,14 +22,7 @@ /* These registers live behind SPI_BASE_ADDRESS. */ #define HSFSTS 0x04 -#define FDATA0 0x10 # define FLOCKDN (0x1 << 15) -#define SSFS 0x90 -# define CYCLE_DONE_STATUS (0x1 << 2) -# define FLASH_CYCLE_ERROR (0x1 << 3) -#define SSFC 0x91 -# define SPI_CYCLE_GO (0x1 << 1) -# define DATA_CYCLE (0x1 << 14) #define PREOP 0x94 #define OPTYPE 0x96 # define SPI_OPTYPE_RD_NOADDR 0x00 /* Read, no address */ diff --git a/src/soc/intel/braswell/spi.c b/src/soc/intel/braswell/spi.c deleted file mode 100644 index 00ec48f978..0000000000 --- a/src/soc/intel/braswell/spi.c +++ /dev/null @@ -1,583 +0,0 @@ -/* - * Copyright (c) 2013 Google Inc. - * Copyright (C) 2015 Intel Corp. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but without any warranty; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -/* This file is derived from the flashrom project. */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -typedef struct spi_slave ich_spi_slave; - -static int ichspi_lock = 0; - -typedef struct ich9_spi_regs { - uint32_t bfpr; - uint16_t hsfs; - uint16_t hsfc; - uint32_t faddr; - uint32_t _reserved0; - uint32_t fdata[16]; - uint32_t frap; - uint32_t freg[5]; - uint32_t _reserved1[3]; - uint32_t pr[5]; - uint32_t _reserved2[2]; - uint8_t ssfs; - uint8_t ssfc[3]; - uint16_t preop; - uint16_t optype; - uint8_t opmenu[8]; -} __packed ich9_spi_regs; - -typedef struct ich_spi_controller { - int locked; - - uint8_t *opmenu; - int menubytes; - uint16_t *preop; - uint16_t *optype; - uint32_t *addr; - uint8_t *data; - unsigned int databytes; - uint8_t *status; - uint16_t *control; -} ich_spi_controller; - -static ich_spi_controller cntlr; - -enum { - SPIS_SCIP = 0x0001, - SPIS_GRANT = 0x0002, - SPIS_CDS = 0x0004, - SPIS_FCERR = 0x0008, - SSFS_AEL = 0x0010, - SPIS_LOCK = 0x8000, - SPIS_RESERVED_MASK = 0x7ff0, - SSFS_RESERVED_MASK = 0x7fe2 -}; - -enum { - SPIC_SCGO = 0x000002, - SPIC_ACS = 0x000004, - SPIC_SPOP = 0x000008, - SPIC_DBC = 0x003f00, - SPIC_DS = 0x004000, - SPIC_SME = 0x008000, - SSFC_SCF_MASK = 0x070000, - SSFC_RESERVED = 0xf80000 -}; - -enum { - HSFS_FDONE = 0x0001, - HSFS_FCERR = 0x0002, - HSFS_AEL = 0x0004, - HSFS_BERASE_MASK = 0x0018, - HSFS_BERASE_SHIFT = 3, - HSFS_SCIP = 0x0020, - HSFS_FDOPSS = 0x2000, - HSFS_FDV = 0x4000, - HSFS_FLOCKDN = 0x8000 -}; - -enum { - HSFC_FGO = 0x0001, - HSFC_FCYCLE_MASK = 0x0006, - HSFC_FCYCLE_SHIFT = 1, - HSFC_FDBC_MASK = 0x3f00, - HSFC_FDBC_SHIFT = 8, - HSFC_FSMIE = 0x8000 -}; - -enum { - SPI_OPCODE_TYPE_READ_NO_ADDRESS = 0, - SPI_OPCODE_TYPE_WRITE_NO_ADDRESS = 1, - SPI_OPCODE_TYPE_READ_WITH_ADDRESS = 2, - SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS = 3 -}; - -#if CONFIG(DEBUG_SPI_FLASH) - -static u8 readb_(void *addr) -{ - u8 v = read8(addr); - printk(BIOS_DEBUG, "0x%p --> 0x%2.2x\n", addr, v); - return v; -} - -static u16 readw_(void *addr) -{ - u16 v = read16(addr); - printk(BIOS_DEBUG, "0x%p --> 0x%4.4x\n", addr, v); - return v; -} - -static u32 readl_(void *addr) -{ - u32 v = read32(addr); - printk(BIOS_DEBUG, "0x%p --> 0x%8.8x\n", addr, v); - return v; -} - -static void writeb_(u8 b, void *addr) -{ - printk(BIOS_DEBUG, "0x%p <-- 0x%2.2x\n", addr, b); - write8(addr, b); -} - -static void writew_(u16 b, void *addr) -{ - printk(BIOS_DEBUG, "0x%p <-- 0x%4.4x\n", addr, b); - write16(addr, b); -} - -static void writel_(u32 b, void *addr) -{ - printk(BIOS_DEBUG, "0x%p <-- 0x%8.8x\n", addr, b); - write32(addr, b); -} - -#else /* CONFIG_DEBUG_SPI_FLASH ^^^ enabled vvv NOT enabled */ - -#define readb_(a) read8(a) -#define readw_(a) read16(a) -#define readl_(a) read32(a) -#define writeb_(val, addr) write8(addr, val) -#define writew_(val, addr) write16(addr, val) -#define writel_(val, addr) write32(addr, val) - -#endif /* CONFIG_DEBUG_SPI_FLASH ^^^ NOT enabled */ - -static void write_reg(const void *value, void *dest, uint32_t size) -{ - const uint8_t *bvalue = value; - uint8_t *bdest = dest; - - while (size >= 4) { - writel_(*(const uint32_t *)bvalue, bdest); - bdest += 4; bvalue += 4; size -= 4; - } - while (size) { - writeb_(*bvalue, bdest); - bdest++; bvalue++; size--; - } -} - -static void read_reg(void *src, void *value, uint32_t size) -{ - uint8_t *bsrc = src; - uint8_t *bvalue = value; - - while (size >= 4) { - *(uint32_t *)bvalue = readl_(bsrc); - bsrc += 4; bvalue += 4; size -= 4; - } - while (size) { - *bvalue = readb_(bsrc); - bsrc++; bvalue++; size--; - } -} - -static ich9_spi_regs *spi_regs(void) -{ - uint32_t sbase; - -#ifdef __SIMPLE_DEVICE__ - pci_devfn_t dev = PCI_DEV(0, LPC_DEV, LPC_FUNC); -#else - struct device *dev = pcidev_on_root(LPC_DEV, LPC_FUNC); -#endif - if (!dev) { - printk(BIOS_ERR, "%s: PCI device not found", __func__); - return NULL; - } - - sbase = pci_read_config32(dev, SBASE); - sbase &= ~0x1ff; - - return (void *)sbase; -} - -#define MENU_BYTES member_size(struct ich9_spi_regs, opmenu) - -void spi_init(void) -{ - ich9_spi_regs *ich9_spi; - - ich9_spi = spi_regs(); - if (!ich9_spi) { - printk(BIOS_ERR, "Not initialising spi as %s returned NULL\n", - __func__); - return; - } - - ichspi_lock = readw_(&ich9_spi->hsfs) & HSFS_FLOCKDN; - cntlr.opmenu = ich9_spi->opmenu; - cntlr.menubytes = sizeof(ich9_spi->opmenu); - cntlr.optype = &ich9_spi->optype; - cntlr.addr = &ich9_spi->faddr; - cntlr.data = (uint8_t *)ich9_spi->fdata; - cntlr.databytes = sizeof(ich9_spi->fdata); - cntlr.status = &ich9_spi->ssfs; - cntlr.control = (uint16_t *)ich9_spi->ssfc; - cntlr.preop = &ich9_spi->preop; -} - -static void spi_init_cb(void *unused) -{ - spi_init(); -} - -BOOT_STATE_INIT_ENTRY(BS_DEV_INIT, BS_ON_ENTRY, spi_init_cb, NULL); - -typedef struct spi_transaction { - const uint8_t *out; - uint32_t bytesout; - uint8_t *in; - uint32_t bytesin; - uint8_t type; - uint8_t opcode; - uint32_t offset; -} spi_transaction; - -static inline void spi_use_out(spi_transaction *trans, unsigned int bytes) -{ - trans->out += bytes; - trans->bytesout -= bytes; -} - -static inline void spi_use_in(spi_transaction *trans, unsigned int bytes) -{ - trans->in += bytes; - trans->bytesin -= bytes; -} - -static void spi_setup_type(spi_transaction *trans) -{ - trans->type = 0xFF; - - /* Try to guess spi type from read/write sizes. */ - if (trans->bytesin == 0) { - if (trans->bytesout > 4) - /* - * If bytesin = 0 and bytesout > 4, we presume this is - * a write data operation, which is accompanied by an - * address. - */ - trans->type = SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS; - else - trans->type = SPI_OPCODE_TYPE_WRITE_NO_ADDRESS; - return; - } - - if (trans->bytesout == 1) { /* and bytesin is > 0 */ - trans->type = SPI_OPCODE_TYPE_READ_NO_ADDRESS; - return; - } - - if (trans->bytesout == 4) { /* and bytesin is > 0 */ - trans->type = SPI_OPCODE_TYPE_READ_WITH_ADDRESS; - } - - /* Fast read command is called with 5 bytes instead of 4 */ - if (trans->out[0] == SPI_OPCODE_FAST_READ && trans->bytesout == 5) { - trans->type = SPI_OPCODE_TYPE_READ_WITH_ADDRESS; - --trans->bytesout; - } -} - -static int spi_setup_opcode(spi_transaction *trans) -{ - uint16_t optypes; - uint8_t opmenu[MENU_BYTES]; - - trans->opcode = trans->out[0]; - spi_use_out(trans, 1); - if (!ichspi_lock) { - /* The lock is off, so just use index 0. */ - writeb_(trans->opcode, cntlr.opmenu); - optypes = readw_(cntlr.optype); - optypes = (optypes & 0xfffc) | (trans->type & 0x3); - writew_(optypes, cntlr.optype); - return 0; - } - - /* The lock is on. See if what we need is on the menu. */ - uint8_t optype; - uint16_t opcode_index; - - /* Write Enable is handled as atomic prefix */ - if (trans->opcode == SPI_OPCODE_WREN) - return 0; - - read_reg(cntlr.opmenu, opmenu, sizeof(opmenu)); - for (opcode_index = 0; opcode_index < ARRAY_SIZE(opmenu); opcode_index++) { - if (opmenu[opcode_index] == trans->opcode) - break; - } - - if (opcode_index == ARRAY_SIZE(opmenu)) { - printk(BIOS_DEBUG, "ICH SPI: Opcode %x not found\n", - trans->opcode); - return -1; - } - - optypes = readw_(cntlr.optype); - optype = (optypes >> (opcode_index * 2)) & 0x3; - if (trans->type == SPI_OPCODE_TYPE_WRITE_NO_ADDRESS && - optype == SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS && - trans->bytesout >= 3) { - /* We guessed wrong earlier. Fix it up. */ - trans->type = optype; - } - if (optype != trans->type) { - printk(BIOS_DEBUG, "ICH SPI: Transaction doesn't fit type %d\n", - optype); - return -1; - } - return opcode_index; -} - -static int spi_setup_offset(spi_transaction *trans) -{ - /* Separate the SPI address and data. */ - switch (trans->type) { - case SPI_OPCODE_TYPE_READ_NO_ADDRESS: - case SPI_OPCODE_TYPE_WRITE_NO_ADDRESS: - return 0; - case SPI_OPCODE_TYPE_READ_WITH_ADDRESS: - case SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS: - trans->offset = ((uint32_t)trans->out[0] << 16) | - ((uint32_t)trans->out[1] << 8) | - ((uint32_t)trans->out[2] << 0); - spi_use_out(trans, 3); - return 1; - default: - printk(BIOS_DEBUG, "Unrecognized SPI transaction type %#x\n", - trans->type); - return -1; - } -} - -/* - * Wait for up to 400ms til status register bit(s) turn 1 (in case wait_til_set - * below is True) or 0. In case the wait was for the bit(s) to set - write - * those bits back, which would cause resetting them. - * - * Return the last read status value on success or -1 on failure. - */ -static int ich_status_poll(u16 bitmask, int wait_til_set) -{ - int timeout = 40000; /* This will result in 400 ms */ - u16 status = 0; - - wait_til_set &= 1; - while (timeout--) { - status = readw_(cntlr.status); - if (wait_til_set ^ ((status & bitmask) == 0)) { - if (wait_til_set) - writew_((status & bitmask), cntlr.status); - return status; - } - udelay(10); - } - - printk(BIOS_ERR, "ICH SPI: SCIP timeout, read %x, expected %x\n", - status, bitmask); - return -1; -} - -static int spi_ctrlr_xfer(const struct spi_slave *slave, const void *dout, - size_t bytesout, void *din, size_t bytesin) -{ - uint16_t control; - int16_t opcode_index; - int with_address; - int status; - - spi_transaction trans = { - dout, bytesout, - din, bytesin, - 0xff, 0xff, 0 - }; - - /* There has to always at least be an opcode. */ - if (!bytesout || !dout) { - printk(BIOS_DEBUG, "ICH SPI: No opcode for transfer\n"); - return -1; - } - /* Make sure if we read something we have a place to put it. */ - if (bytesin != 0 && !din) { - printk(BIOS_DEBUG, "ICH SPI: Read but no target buffer\n"); - return -1; - } - - if (ich_status_poll(SPIS_SCIP, 0) == -1) - return -1; - - writew_(SPIS_CDS | SPIS_FCERR, cntlr.status); - - spi_setup_type(&trans); - opcode_index = spi_setup_opcode(&trans); - if (opcode_index < 0) - return -1; - with_address = spi_setup_offset(&trans); - if (with_address < 0) - return -1; - - if (trans.opcode == SPI_OPCODE_WREN) { - /* - * Treat Write Enable as Atomic Pre-Op if possible - * in order to prevent the Management Engine from - * issuing a transaction between WREN and DATA. - */ - if (!ichspi_lock) - writew_(trans.opcode, cntlr.preop); - return 0; - } - - /* Preset control fields */ - control = SPIC_SCGO | ((opcode_index & 0x07) << 4); - - /* Issue atomic preop cycle if needed */ - if (readw_(cntlr.preop)) - control |= SPIC_ACS; - - if (!trans.bytesout && !trans.bytesin) { - /* SPI addresses are 24 bit only */ - if (with_address) - writel_(trans.offset & 0x00FFFFFF, cntlr.addr); - - /* - * This is a 'no data' command (like Write Enable), its - * bytesout size was 1, decremented to zero while executing - * spi_setup_opcode() above. Tell the chip to send the - * command. - */ - writew_(control, cntlr.control); - - /* wait for the result */ - status = ich_status_poll(SPIS_CDS | SPIS_FCERR, 1); - if (status == -1) - return -1; - - if (status & SPIS_FCERR) { - printk(BIOS_ERR, "ICH SPI: Command transaction error\n"); - return -1; - } - - return 0; - } - - /* - * Check if this is a write command attempting to transfer more bytes - * than the controller can handle. Iterations for writes are not - * supported here because each SPI write command needs to be preceded - * and followed by other SPI commands, and this sequence is controlled - * by the SPI chip driver. - */ - if (trans.bytesout > cntlr.databytes) { - printk(BIOS_DEBUG, - "ICH SPI: Too much to write. Does your SPI chip driver use" - " CONTROLLER_PAGE_LIMIT?\n"); - return -1; - } - - /* - * Read or write up to databytes bytes at a time until everything has - * been sent. - */ - while (trans.bytesout || trans.bytesin) { - uint32_t data_length; - - /* SPI addresses are 24 bit only */ - writel_(trans.offset & 0x00FFFFFF, cntlr.addr); - - if (trans.bytesout) - data_length = min(trans.bytesout, cntlr.databytes); - else - data_length = min(trans.bytesin, cntlr.databytes); - - /* Program data into FDATA0 to N */ - if (trans.bytesout) { - write_reg(trans.out, cntlr.data, data_length); - spi_use_out(&trans, data_length); - if (with_address) - trans.offset += data_length; - } - - /* Add proper control fields' values */ - control &= ~((cntlr.databytes - 1) << 8); - control |= SPIC_DS; - control |= (data_length - 1) << 8; - - /* write it */ - writew_(control, cntlr.control); - - /* Wait for Cycle Done Status or Flash Cycle Error. */ - status = ich_status_poll(SPIS_CDS | SPIS_FCERR, 1); - if (status == -1) - return -1; - - if (status & SPIS_FCERR) { - printk(BIOS_ERR, "ICH SPI: Data transaction error\n"); - return -1; - } - - if (trans.bytesin) { - read_reg(cntlr.data, trans.in, data_length); - spi_use_in(&trans, data_length); - if (with_address) - trans.offset += data_length; - } - } - - /* Clear atomic preop now that xfer is done */ - writew_(0, cntlr.preop); - - return 0; -} - -static int xfer_vectors(const struct spi_slave *slave, - struct spi_op vectors[], size_t count) -{ - return spi_flash_vector_helper(slave, vectors, count, spi_ctrlr_xfer); -} - -static const struct spi_ctrlr spi_ctrlr = { - .xfer_vector = xfer_vectors, - .max_xfer_size = member_size(ich9_spi_regs, fdata), -}; - -const struct spi_ctrlr_buses spi_ctrlr_bus_map[] = { - { - .ctrlr = &spi_ctrlr, - .bus_start = 0, - .bus_end = 0, - }, -}; - -const size_t spi_ctrlr_bus_map_count = ARRAY_SIZE(spi_ctrlr_bus_map); From 91eb2816faa4b2689f30ca47ff2585cf79ac53f3 Mon Sep 17 00:00:00 2001 From: Arthur Heymans Date: Sun, 13 Oct 2019 23:14:08 +0200 Subject: [PATCH 0455/1242] soc/intel/braswell: Don't reinitialize SPI after lockdown With the common southbridge SPI code reinitialization after lockdown is not necessary, hence the SMM finalize call becomes a no-op. Change-Id: I9fae28185470f4d25ef1818627eb76ac38cf100b Signed-off-by: Arthur Heymans Reviewed-on: https://review.coreboot.org/c/coreboot/+/36006 Reviewed-by: Nico Huber Tested-by: build bot (Jenkins) --- src/soc/intel/braswell/smihandler.c | 19 ------------------- src/soc/intel/braswell/southcluster.c | 4 ---- 2 files changed, 23 deletions(-) diff --git a/src/soc/intel/braswell/smihandler.c b/src/soc/intel/braswell/smihandler.c index b94fe653ad..d0306caaa3 100644 --- a/src/soc/intel/braswell/smihandler.c +++ b/src/soc/intel/braswell/smihandler.c @@ -280,22 +280,6 @@ static void southbridge_smi_gsmi(void) *ret = gsmi_exec(sub_command, param); } -static void finalize(void) -{ - static int finalize_done; - - if (finalize_done) { - printk(BIOS_DEBUG, "SMM already finalized.\n"); - return; - } - finalize_done = 1; - -#if CONFIG(SPI_FLASH_SMM) - /* Re-init SPI driver to handle locked BAR */ - spi_init(); -#endif -} - static void southbridge_smi_apmc(void) { uint8_t reg8; @@ -347,9 +331,6 @@ static void southbridge_smi_apmc(void) if (CONFIG(ELOG_GSMI)) southbridge_smi_gsmi(); break; - case APM_CNT_FINALIZE: - finalize(); - break; } mainboard_smi_apmc(reg8); diff --git a/src/soc/intel/braswell/southcluster.c b/src/soc/intel/braswell/southcluster.c index 9118f00a66..c233dc8172 100644 --- a/src/soc/intel/braswell/southcluster.c +++ b/src/soc/intel/braswell/southcluster.c @@ -650,10 +650,6 @@ static void finalize_chipset(void *unused) write32(spi + UVSCC, cfg.uvscc); write32(spi + LVSCC, cfg.lvscc | VCL); } - spi_init(); - - printk(BIOS_DEBUG, "Finalizing SMM.\n"); - outb(APM_CNT_FINALIZE, APM_CNT); } BOOT_STATE_INIT_ENTRY(BS_POST_DEVICE, BS_ON_EXIT, finalize_chipset, NULL); From d20b0a842bec15e65549db75d2b19e456db0ac50 Mon Sep 17 00:00:00 2001 From: Arthur Heymans Date: Wed, 20 Nov 2019 22:00:57 +0100 Subject: [PATCH 0456/1242] drivers/spi/boot_device_rw_nommap.c: Drop CAR_GLOBAL_MIGRATION support MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Change-Id: I613c28a2d06f5f0216deb75960ab660941ef8057 Signed-off-by: Arthur Heymans Reviewed-on: https://review.coreboot.org/c/coreboot/+/37044 Reviewed-by: HAOUAS Elyes Reviewed-by: Kyösti Mälkki Tested-by: build bot (Jenkins) --- src/drivers/spi/boot_device_rw_nommap.c | 40 ++++++++----------------- 1 file changed, 12 insertions(+), 28 deletions(-) diff --git a/src/drivers/spi/boot_device_rw_nommap.c b/src/drivers/spi/boot_device_rw_nommap.c index 47683144a8..5de9a71ceb 100644 --- a/src/drivers/spi/boot_device_rw_nommap.c +++ b/src/drivers/spi/boot_device_rw_nommap.c @@ -11,24 +11,18 @@ * GNU General Public License for more details. */ -#include #include #include #include #include -static struct spi_flash sfg CAR_GLOBAL; -static bool sfg_init_done CAR_GLOBAL; +static struct spi_flash sfg; +static bool sfg_init_done; static ssize_t spi_readat(const struct region_device *rd, void *b, size_t offset, size_t size) { - struct spi_flash *sf = car_get_var_ptr(&sfg); - - if (sf == NULL) - return -1; - - if (spi_flash_read(sf, offset, size, b)) + if (spi_flash_read(&sfg, offset, size, b)) return -1; return size; @@ -37,12 +31,7 @@ static ssize_t spi_readat(const struct region_device *rd, void *b, static ssize_t spi_writeat(const struct region_device *rd, const void *b, size_t offset, size_t size) { - struct spi_flash *sf = car_get_var_ptr(&sfg); - - if (sf == NULL) - return -1; - - if (spi_flash_write(sf, offset, size, b)) + if (spi_flash_write(&sfg, offset, size, b)) return -1; return size; @@ -51,12 +40,7 @@ static ssize_t spi_writeat(const struct region_device *rd, const void *b, static ssize_t spi_eraseat(const struct region_device *rd, size_t offset, size_t size) { - struct spi_flash *sf = car_get_var_ptr(&sfg); - - if (sf == NULL) - return -1; - - if (spi_flash_erase(sf, offset, size)) + if (spi_flash_erase(&sfg, offset, size)) return -1; return size; @@ -76,14 +60,14 @@ static void boot_device_rw_init(void) const int bus = CONFIG_BOOT_DEVICE_SPI_FLASH_BUS; const int cs = 0; - if (car_get_var(sfg_init_done) == true) + if (sfg_init_done == true) return; /* Ensure any necessary setup is performed by the drivers. */ spi_init(); - if (!spi_flash_probe(bus, cs, car_get_var_ptr(&sfg))) - car_set_var(sfg_init_done, true); + if (!spi_flash_probe(bus, cs, &sfg)) + sfg_init_done = true; } const struct region_device *boot_device_rw(void) @@ -91,7 +75,7 @@ const struct region_device *boot_device_rw(void) /* Probe for the SPI flash device if not already done. */ boot_device_rw_init(); - if (car_get_var(sfg_init_done) != true) + if (sfg_init_done != true) return NULL; return &spi_rw; @@ -101,10 +85,10 @@ const struct spi_flash *boot_device_spi_flash(void) { boot_device_rw_init(); - if (car_get_var(sfg_init_done) != true) + if (sfg_init_done != true) return NULL; - return car_get_var_ptr(&sfg); + return &sfg; } int boot_device_wp_region(const struct region_device *rd, @@ -122,7 +106,7 @@ int boot_device_wp_region(const struct region_device *rd, if (type == MEDIA_WP) { if (spi_flash_is_write_protected(boot_dev, - region_device_region(rd)) != 1) { + region_device_region(rd)) != 1) { return spi_flash_set_write_protected(boot_dev, region_device_region(rd), true, SPI_WRITE_PROTECTION_REBOOT); From 462a7daeec809ce8fca2fbb58eeeb5c1a3f099d7 Mon Sep 17 00:00:00 2001 From: Arthur Heymans Date: Wed, 20 Nov 2019 19:56:00 +0100 Subject: [PATCH 0457/1242] lib/imd_cbmem.c: Drop CAR_GLOBAL_MIGRATION support MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Change-Id: Id409f9abf33c851b6d08903bc111a6b8ec6bf8cf Signed-off-by: Arthur Heymans Reviewed-on: https://review.coreboot.org/c/coreboot/+/37032 Reviewed-by: Kyösti Mälkki Tested-by: build bot (Jenkins) --- src/lib/imd_cbmem.c | 35 ++--------------------------------- 1 file changed, 2 insertions(+), 33 deletions(-) diff --git a/src/lib/imd_cbmem.c b/src/lib/imd_cbmem.c index 6eb3e6096c..6fd48d57dd 100644 --- a/src/lib/imd_cbmem.c +++ b/src/lib/imd_cbmem.c @@ -22,28 +22,6 @@ #include #include #include -#include - -/* - * We need special handling on x86 where CAR global migration is employed. One - * cannot use true globals in that circumstance because CAR is where the globals - * are backed -- creating a circular dependency. For non CAR platforms globals - * are free to be used as well as any stages that are purely executing out of - * RAM. For CAR platforms that don't migrate globals the as-linked globals can - * be used, but they need special decoration using CAR_GLOBAL. That ensures - * proper object placement in conjunction with the linker. - * - * For the CAR global migration platforms we have to always try to partially - * recover CBMEM from cbmem_top() whenever we try to access it. In other - * environments we're not so constrained and just keep the backing imd struct - * in a global. This also means that we can easily tell whether CBMEM has - * explicitly been initialized or recovered yet on those platforms, and don't - * need to put the burden on board or chipset code to tell us by returning - * NULL from cbmem_top() before that point. - */ -#define CAN_USE_GLOBALS \ - (!CONFIG(ARCH_X86) || ENV_RAMSTAGE || ENV_POSTCAR || \ - !CONFIG(CAR_GLOBAL_MIGRATION)) /* The program loader passes on cbmem_top and the program entry point has to fill in the _cbmem_top_ptr symbol based on the calling arguments. */ @@ -67,11 +45,8 @@ void *cbmem_top(void) static inline struct imd *cbmem_get_imd(void) { - if (CAN_USE_GLOBALS) { - static struct imd imd_cbmem CAR_GLOBAL; - return &imd_cbmem; - } - return NULL; + static struct imd imd_cbmem; + return &imd_cbmem; } static inline const struct cbmem_entry *imd_to_cbmem(const struct imd_entry *e) @@ -115,12 +90,6 @@ static struct imd *imd_init_backing_with_recover(struct imd *backing) struct imd *imd; imd = imd_init_backing(backing); - if (!CAN_USE_GLOBALS) { - /* Always partially recover if we can't keep track of whether - * we have already initialized CBMEM in this stage. */ - imd_handle_init(imd, cbmem_top()); - imd_handle_init_partial_recovery(imd); - } return imd; } From 6229cc93ff16a5a9a424a0323fd631c8b3e1c943 Mon Sep 17 00:00:00 2001 From: Arthur Heymans Date: Wed, 20 Nov 2019 22:12:08 +0100 Subject: [PATCH 0458/1242] cpu/intel/common/fsb.c: Drop CAR_GLOBAL_MIGRATION support Change-Id: I151090c8d7f670f121dc7e4cbebfd720034fde33 Signed-off-by: Arthur Heymans Reviewed-on: https://review.coreboot.org/c/coreboot/+/37051 Tested-by: build bot (Jenkins) --- src/cpu/intel/common/fsb.c | 31 ++++++++++++------------------- 1 file changed, 12 insertions(+), 19 deletions(-) diff --git a/src/cpu/intel/common/fsb.c b/src/cpu/intel/common/fsb.c index 0004eade89..0f6fd1d921 100644 --- a/src/cpu/intel/common/fsb.c +++ b/src/cpu/intel/common/fsb.c @@ -11,7 +11,6 @@ * GNU General Public License for more details. */ -#include #include #include #include @@ -20,8 +19,8 @@ #include #include -static u32 g_timer_fsb CAR_GLOBAL; -static u32 g_timer_tsc CAR_GLOBAL; +static u32 g_timer_fsb; +static u32 g_timer_tsc; /* This is not an architectural MSR. */ #define MSR_PLATFORM_INFO 0xce @@ -99,8 +98,8 @@ static void resolve_timebase(void) ret = get_fsb_tsc(&fsb, &ratio); if (ret == 0) { u32 tsc = 100 * DIV_ROUND_CLOSEST(ratio * fsb, 100); - car_set_var(g_timer_fsb, fsb); - car_set_var(g_timer_tsc, tsc); + g_timer_fsb = fsb; + g_timer_tsc = tsc; return; } @@ -110,33 +109,27 @@ static void resolve_timebase(void) printk(BIOS_ERR, "CPU not supported\n"); /* Set some semi-ridiculous defaults. */ - car_set_var(g_timer_fsb, 500); - car_set_var(g_timer_tsc, 5000); + g_timer_fsb = 500; + g_timer_tsc = 5000; return; } u32 get_timer_fsb(void) { - u32 fsb; - - fsb = car_get_var(g_timer_fsb); - if (fsb > 0) - return fsb; + if (g_timer_fsb > 0) + return g_timer_fsb; resolve_timebase(); - return car_get_var(g_timer_fsb); + return g_timer_fsb; } unsigned long tsc_freq_mhz(void) { - u32 tsc; - - tsc = car_get_var(g_timer_tsc); - if (tsc > 0) - return tsc; + if (g_timer_tsc > 0) + return g_timer_tsc; resolve_timebase(); - return car_get_var(g_timer_tsc); + return g_timer_tsc; } /** From 179da7fb5cff3c9034dc3203086c84342560c600 Mon Sep 17 00:00:00 2001 From: Arthur Heymans Date: Fri, 15 Nov 2019 12:51:51 +0100 Subject: [PATCH 0459/1242] soc/intel/baytrail: Move to C_ENVIRONMENT_BOOTBLOCK This moves programming BAR's and setting up console in the bootblock. Change-Id: I062461cb7bfba2c4df4c20707ecda32f9857b164 Signed-off-by: Arthur Heymans Reviewed-on: https://review.coreboot.org/c/coreboot/+/36873 Reviewed-by: Patrick Georgi Tested-by: build bot (Jenkins) --- src/soc/intel/baytrail/Kconfig | 20 ++- src/soc/intel/baytrail/Makefile.inc | 10 +- src/soc/intel/baytrail/bootblock/bootblock.c | 118 +++++++++++++----- src/soc/intel/baytrail/include/soc/romstage.h | 2 - src/soc/intel/baytrail/romstage/Makefile.inc | 4 - src/soc/intel/baytrail/romstage/pmc.c | 10 -- src/soc/intel/baytrail/romstage/romstage.c | 60 --------- src/soc/intel/baytrail/romstage/uart.c | 34 ----- 8 files changed, 98 insertions(+), 160 deletions(-) delete mode 100644 src/soc/intel/baytrail/romstage/uart.c diff --git a/src/soc/intel/baytrail/Kconfig b/src/soc/intel/baytrail/Kconfig index e96b53d321..94ed887d5c 100644 --- a/src/soc/intel/baytrail/Kconfig +++ b/src/soc/intel/baytrail/Kconfig @@ -38,16 +38,11 @@ config CPU_SPECIFIC_OPTIONS select INTEL_GMA_SWSMISCI select CPU_INTEL_COMMON select CPU_HAS_L2_ENABLE_MSR - select ROMCC_BOOTBLOCK config VBOOT select VBOOT_MUST_REQUEST_DISPLAY select VBOOT_STARTS_IN_ROMSTAGE -config BOOTBLOCK_CPU_INIT - string - default "soc/intel/baytrail/bootblock/bootblock.c" - config MMCONF_BASE_ADDRESS hex default 0xe0000000 @@ -97,14 +92,9 @@ config MRC_RMT # +-------------+ DCACHE_RAM_BASE + DCACHE_RAM_SIZE + DCACHE_RAM_MRC_VAR_SIZE # | MRC usage | # | | -# +-------------+ DCACHE_RAM_BASE + DCACHE_RAM_SIZE -# | Stack | -# | | | -# | v | -# +-------------+ -# | ^ | -# | | | -# | CAR Globals | +# -------------+ DCACHE_RAM_BASE + DCACHE_RAM_SIZE +# | coreboot | +# | usage | # +-------------+ DCACHE_RAM_BASE # # Note that the MRC binary is linked to assume the region marked as "MRC usage" @@ -130,6 +120,10 @@ config DCACHE_RAM_MRC_VAR_SIZE help The amount of cache-as-ram region required by the reference code. +config DCACHE_BSP_STACK_SIZE + hex + default 0x2000 + config RESET_ON_INVALID_RAMSTAGE_CACHE bool "Reset the system on S3 wake when ramstage cache invalid." default n diff --git a/src/soc/intel/baytrail/Makefile.inc b/src/soc/intel/baytrail/Makefile.inc index 2c49c63454..1769b53085 100644 --- a/src/soc/intel/baytrail/Makefile.inc +++ b/src/soc/intel/baytrail/Makefile.inc @@ -9,14 +9,19 @@ subdirs-y += ../../../cpu/intel/microcode subdirs-y += ../../../cpu/intel/turbo subdirs-y += ../../../cpu/intel/common +all-y += tsc_freq.c + +bootblock-y += ../../../cpu/intel/car/non-evict/cache_as_ram.S +bootblock-y += ../../../cpu/intel/car/bootblock.c +bootblock-y += ../../../cpu/x86/early_reset.S +bootblock-y += bootblock/bootblock.c + romstage-y += iosf.c romstage-y += memmap.c romstage-y += pmutil.c -romstage-y += tsc_freq.c postcar-y += iosf.c postcar-y += memmap.c -postcar-y += tsc_freq.c ramstage-y += acpi.c ramstage-y += chip.c @@ -41,7 +46,6 @@ ramstage-y += scc.c ramstage-y += sd.c ramstage-y += smm.c ramstage-y += southcluster.c -ramstage-y += tsc_freq.c ramstage-y += xhci.c ramstage-$(CONFIG_ELOG) += elog.c ramstage-$(CONFIG_HAVE_REFCODE_BLOB) += refcode.c diff --git a/src/soc/intel/baytrail/bootblock/bootblock.c b/src/soc/intel/baytrail/bootblock/bootblock.c index b2cdf9d766..1c5bfc54d6 100644 --- a/src/soc/intel/baytrail/bootblock/bootblock.c +++ b/src/soc/intel/baytrail/bootblock/bootblock.c @@ -13,38 +13,14 @@ * GNU General Public License for more details. */ +#include #include -#include -#include -#include #include -#include - -static void set_var_mtrr(int reg, uint32_t base, uint32_t size, int type) -{ - msr_t basem, maskm; - basem.lo = base | type; - basem.hi = 0; - wrmsr(MTRR_PHYS_BASE(reg), basem); - maskm.lo = ~(size - 1) | MTRR_PHYS_MASK_VALID; - maskm.hi = (1 << (CONFIG_CPU_ADDR_BITS - 32)) - 1; - wrmsr(MTRR_PHYS_MASK(reg), maskm); -} - -static void enable_rom_caching(void) -{ - msr_t msr; - - disable_cache(); - /* Why only top 4MiB ? */ - set_var_mtrr(1, 0xffc00000, 4*1024*1024, MTRR_TYPE_WRPROT); - enable_cache(); - - /* Enable Variable MTRRs */ - msr.hi = 0x00000000; - msr.lo = 0x00000800; - wrmsr(MTRR_DEF_TYPE_MSR, msr); -} +#include +#include +#include +#include +#include static void setup_mmconfig(void) { @@ -64,12 +40,86 @@ static void setup_mmconfig(void) pci_io_write_config32(IOSF_PCI_DEV, MCR_REG, reg); } -static void bootblock_cpu_init(void) +static void program_base_addresses(void) +{ + uint32_t reg; + const uint32_t lpc_dev = PCI_DEV(0, LPC_DEV, LPC_FUNC); + + /* Memory Mapped IO registers. */ + reg = PMC_BASE_ADDRESS | 2; + pci_write_config32(lpc_dev, PBASE, reg); + reg = IO_BASE_ADDRESS | 2; + pci_write_config32(lpc_dev, IOBASE, reg); + reg = ILB_BASE_ADDRESS | 2; + pci_write_config32(lpc_dev, IBASE, reg); + reg = SPI_BASE_ADDRESS | 2; + pci_write_config32(lpc_dev, SBASE, reg); + reg = MPHY_BASE_ADDRESS | 2; + pci_write_config32(lpc_dev, MPBASE, reg); + reg = PUNIT_BASE_ADDRESS | 2; + pci_write_config32(lpc_dev, PUBASE, reg); + reg = RCBA_BASE_ADDRESS | 1; + pci_write_config32(lpc_dev, RCBA, reg); + + /* IO Port Registers. */ + reg = ACPI_BASE_ADDRESS | 2; + pci_write_config32(lpc_dev, ABASE, reg); + reg = GPIO_BASE_ADDRESS | 2; + pci_write_config32(lpc_dev, GBASE, reg); +} + +static void spi_init(void) +{ + u32 *scs = (u32 *)(SPI_BASE_ADDRESS + SCS); + u32 *bcr = (u32 *)(SPI_BASE_ADDRESS + BCR); + uint32_t reg; + + /* Disable generating SMI when setting WPD bit. */ + write32(scs, read32(scs) & ~SMIWPEN); + /* + * Enable caching and prefetching in the SPI controller. Disable + * the SMM-only BIOS write and set WPD bit. + */ + reg = (read32(bcr) & ~SRC_MASK) | SRC_CACHE_PREFETCH | BCR_WPD; + reg &= ~EISS; + write32(bcr, reg); +} + +static void tco_disable(void) +{ + uint32_t reg; + + reg = inl(ACPI_BASE_ADDRESS + TCO1_CNT); + reg |= TCO_TMR_HALT; + outl(reg, ACPI_BASE_ADDRESS + TCO1_CNT); +} + +static void byt_config_com1_and_enable(void) +{ + uint32_t reg; + + /* Enable the UART hardware for COM1. */ + reg = 1; + pci_write_config32(PCI_DEV(0, LPC_DEV, 0), UART_CONT, reg); + + /* Set up the pads to select the UART function */ + score_select_func(UART_RXD_PAD, 1); + score_select_func(UART_TXD_PAD, 1); +} + +/* The distinction between nb/sb/cpu is not applicable here so + just pick the one that is called first. */ +void bootblock_early_northbridge_init(void) { /* Allow memory-mapped PCI config access. */ setup_mmconfig(); - /* Load microcode before any caching. */ - intel_update_microcode_from_cbfs(); - enable_rom_caching(); + program_base_addresses(); + + tco_disable(); + + if (CONFIG(ENABLE_BUILTIN_COM1)) + byt_config_com1_and_enable(); + + spi_init(); } diff --git a/src/soc/intel/baytrail/include/soc/romstage.h b/src/soc/intel/baytrail/include/soc/romstage.h index e86861c4bf..16f80b4a4f 100644 --- a/src/soc/intel/baytrail/include/soc/romstage.h +++ b/src/soc/intel/baytrail/include/soc/romstage.h @@ -24,8 +24,6 @@ void mainboard_fill_mrc_params(struct mrc_params *mp); void raminit(struct mrc_params *mp, int prev_sleep_state); void gfx_init(void); -void tco_disable(void); void punit_init(void); -void byt_config_com1_and_enable(void); #endif /* _BAYTRAIL_ROMSTAGE_H_ */ diff --git a/src/soc/intel/baytrail/romstage/Makefile.inc b/src/soc/intel/baytrail/romstage/Makefile.inc index 2effbb08f6..58d7889917 100644 --- a/src/soc/intel/baytrail/romstage/Makefile.inc +++ b/src/soc/intel/baytrail/romstage/Makefile.inc @@ -1,9 +1,5 @@ -cpu_incs-y += $(src)/cpu/intel/car/non-evict/cache_as_ram.S -cpu_incs-y += $(obj)/fmap_config.h - romstage-y += ../../../../cpu/intel/car/romstage.c romstage-y += romstage.c romstage-y += raminit.c -romstage-$(CONFIG_ENABLE_BUILTIN_COM1) += uart.c romstage-y += gfx.c romstage-y += pmc.c diff --git a/src/soc/intel/baytrail/romstage/pmc.c b/src/soc/intel/baytrail/romstage/pmc.c index 2eb3846c4f..11b3b0f8bc 100644 --- a/src/soc/intel/baytrail/romstage/pmc.c +++ b/src/soc/intel/baytrail/romstage/pmc.c @@ -14,7 +14,6 @@ */ #include -#include #include #include #include @@ -27,15 +26,6 @@ #include #include "../chip.h" -void tco_disable(void) -{ - uint32_t reg; - - reg = inl(ACPI_BASE_ADDRESS + TCO1_CNT); - reg |= TCO_TMR_HALT; - outl(reg, ACPI_BASE_ADDRESS + TCO1_CNT); -} - /* This sequence signals the PUNIT to start running. */ void punit_init(void) { diff --git a/src/soc/intel/baytrail/romstage/romstage.c b/src/soc/intel/baytrail/romstage/romstage.c index 7c129e258e..25cb6617f6 100644 --- a/src/soc/intel/baytrail/romstage/romstage.c +++ b/src/soc/intel/baytrail/romstage/romstage.c @@ -27,60 +27,11 @@ #include #include #include -#include -#include #include -#include #include #include #include #include -#include - -static void program_base_addresses(void) -{ - uint32_t reg; - const uint32_t lpc_dev = PCI_DEV(0, LPC_DEV, LPC_FUNC); - - /* Memory Mapped IO registers. */ - reg = PMC_BASE_ADDRESS | 2; - pci_write_config32(lpc_dev, PBASE, reg); - reg = IO_BASE_ADDRESS | 2; - pci_write_config32(lpc_dev, IOBASE, reg); - reg = ILB_BASE_ADDRESS | 2; - pci_write_config32(lpc_dev, IBASE, reg); - reg = SPI_BASE_ADDRESS | 2; - pci_write_config32(lpc_dev, SBASE, reg); - reg = MPHY_BASE_ADDRESS | 2; - pci_write_config32(lpc_dev, MPBASE, reg); - reg = PUNIT_BASE_ADDRESS | 2; - pci_write_config32(lpc_dev, PUBASE, reg); - reg = RCBA_BASE_ADDRESS | 1; - pci_write_config32(lpc_dev, RCBA, reg); - - /* IO Port Registers. */ - reg = ACPI_BASE_ADDRESS | 2; - pci_write_config32(lpc_dev, ABASE, reg); - reg = GPIO_BASE_ADDRESS | 2; - pci_write_config32(lpc_dev, GBASE, reg); -} - -static void spi_init(void) -{ - u32 *scs = (u32 *)(SPI_BASE_ADDRESS + SCS); - u32 *bcr = (u32 *)(SPI_BASE_ADDRESS + BCR); - uint32_t reg; - - /* Disable generating SMI when setting WPD bit. */ - write32(scs, read32(scs) & ~SMIWPEN); - /* - * Enable caching and prefetching in the SPI controller. Disable - * the SMM-only BIOS write and set WPD bit. - */ - reg = (read32(bcr) & ~SRC_MASK) | SRC_CACHE_PREFETCH | BCR_WPD; - reg &= ~EISS; - write32(bcr, reg); -} static struct chipset_power_state power_state; @@ -158,17 +109,6 @@ void mainboard_romstage_entry(void) int prev_sleep_state; struct mrc_params mp; - program_base_addresses(); - - tco_disable(); - - if (CONFIG(ENABLE_BUILTIN_COM1)) - byt_config_com1_and_enable(); - - console_init(); - - spi_init(); - set_max_freq(); punit_init(); diff --git a/src/soc/intel/baytrail/romstage/uart.c b/src/soc/intel/baytrail/romstage/uart.c deleted file mode 100644 index f9f2fe4238..0000000000 --- a/src/soc/intel/baytrail/romstage/uart.c +++ /dev/null @@ -1,34 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2013 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include -#include -#include -#include - -void byt_config_com1_and_enable(void) -{ - uint32_t reg; - - /* Enable the UART hardware for COM1. */ - reg = 1; - pci_write_config32(PCI_DEV(0, LPC_DEV, 0), UART_CONT, reg); - - /* Set up the pads to select the UART function */ - score_select_func(UART_RXD_PAD, 1); - score_select_func(UART_TXD_PAD, 1); -} From 01787608670adec26fcea48173e18395e51c790e Mon Sep 17 00:00:00 2001 From: Elyes HAOUAS Date: Fri, 25 Oct 2019 10:53:20 +0200 Subject: [PATCH 0460/1242] {northbridge,soc,southbridge}: Don't use both of _ADR and _HID ACPI Version 6.3 Section 6.1: "A device object must contain either an _HID object or an _ADR object, but should not contain both." Change-Id: Ifb777c09aeef09a6a4cbee254b081519f5b6c457 Signed-off-by: Elyes HAOUAS Reviewed-on: https://review.coreboot.org/c/coreboot/+/36318 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth --- src/northbridge/amd/agesa/family14/acpi/northbridge.asl | 3 +-- .../amd/agesa/family15tn/acpi/northbridge.asl | 2 +- .../amd/agesa/family16kb/acpi/northbridge.asl | 2 +- src/northbridge/amd/pi/00630F01/acpi/northbridge.asl | 2 +- src/northbridge/amd/pi/00660F01/acpi/northbridge.asl | 2 +- src/northbridge/amd/pi/00730F01/acpi/northbridge.asl | 3 +-- src/soc/amd/stoneyridge/acpi/northbridge.asl | 2 +- src/soc/intel/broadwell/acpi/serialio.asl | 9 +-------- src/southbridge/intel/lynxpoint/acpi/serialio.asl | 9 +-------- 9 files changed, 9 insertions(+), 25 deletions(-) diff --git a/src/northbridge/amd/agesa/family14/acpi/northbridge.asl b/src/northbridge/amd/agesa/family14/acpi/northbridge.asl index 06199a1b07..fad157da29 100644 --- a/src/northbridge/amd/agesa/family14/acpi/northbridge.asl +++ b/src/northbridge/amd/agesa/family14/acpi/northbridge.asl @@ -16,7 +16,7 @@ /* Note: Only need HID on Primary Bus */ External (TOM1) External (TOM2) -Name(_HID, EISAID("PNP0A08")) /* PCI Express Root Bridge */ +/* Name(_HID, EISAID("PNP0A08")) // PCI Express Root Bridge */ Name(_CID, EISAID("PNP0A03")) /* PCI Root Bridge */ Name(_ADR, 0x00180000) /* Dev# = BSP Dev#, Func# = 0 */ @@ -125,7 +125,6 @@ Device(PE23) { /* Northbridge function 3 */ Device(NBF3) { - Name(_ADR, 0x00180003) /* k10temp thermal zone */ #include "thermal_mixin.asl" diff --git a/src/northbridge/amd/agesa/family15tn/acpi/northbridge.asl b/src/northbridge/amd/agesa/family15tn/acpi/northbridge.asl index 9a1fa9ed88..96c2d8bfac 100644 --- a/src/northbridge/amd/agesa/family15tn/acpi/northbridge.asl +++ b/src/northbridge/amd/agesa/family15tn/acpi/northbridge.asl @@ -16,7 +16,7 @@ /* Note: Only need HID on Primary Bus */ External (TOM1) External (TOM2) -Name(_HID, EISAID("PNP0A03")) /* PCI Express Root Bridge */ +/* Name(_HID, EISAID("PNP0A03")) // PCI Express Root Bridge */ Name(_ADR, 0x00180000) /* Dev# = BSP Dev#, Func# = 0 */ /* Describe the Northbridge devices */ diff --git a/src/northbridge/amd/agesa/family16kb/acpi/northbridge.asl b/src/northbridge/amd/agesa/family16kb/acpi/northbridge.asl index f74b31a080..a7e8307349 100644 --- a/src/northbridge/amd/agesa/family16kb/acpi/northbridge.asl +++ b/src/northbridge/amd/agesa/family16kb/acpi/northbridge.asl @@ -16,7 +16,7 @@ /* Note: Only need HID on Primary Bus */ External (TOM1) External (TOM2) -Name(_HID, EISAID("PNP0A08")) /* PCI Express Root Bridge */ +/* Name(_HID, EISAID("PNP0A08")) // PCI Express Root Bridge */ Name(_CID, EISAID("PNP0A03")) /* PCI Root Bridge */ Name(_ADR, 0x00180000) /* Dev# = BSP Dev#, Func# = 0 */ diff --git a/src/northbridge/amd/pi/00630F01/acpi/northbridge.asl b/src/northbridge/amd/pi/00630F01/acpi/northbridge.asl index c2b3aac4c5..de47bc2151 100644 --- a/src/northbridge/amd/pi/00630F01/acpi/northbridge.asl +++ b/src/northbridge/amd/pi/00630F01/acpi/northbridge.asl @@ -16,7 +16,7 @@ /* Note: Only need HID on Primary Bus */ External (TOM1) External (TOM2) -Name(_HID, EISAID("PNP0A03")) /* PCI Express Root Bridge */ +/* Name(_HID, EISAID("PNP0A03")) // PCI Express Root Bridge */ Name(_ADR, 0x00180000) /* Dev# = BSP Dev#, Func# = 0 */ /* Describe the Northbridge devices */ diff --git a/src/northbridge/amd/pi/00660F01/acpi/northbridge.asl b/src/northbridge/amd/pi/00660F01/acpi/northbridge.asl index d54f985e90..4a48aaf401 100644 --- a/src/northbridge/amd/pi/00660F01/acpi/northbridge.asl +++ b/src/northbridge/amd/pi/00660F01/acpi/northbridge.asl @@ -16,7 +16,7 @@ /* Note: Only need HID on Primary Bus */ External (TOM1) External (TOM2) -Name(_HID, EISAID("PNP0A08")) /* PCI Express Root Bridge */ +/* Name(_HID, EISAID("PNP0A08")) // PCI Express Root Bridge */ Name(_CID, EISAID("PNP0A03")) /* PCI Root Bridge */ Name(_ADR, 0x00180000) /* Dev# = BSP Dev#, Func# = 0 */ diff --git a/src/northbridge/amd/pi/00730F01/acpi/northbridge.asl b/src/northbridge/amd/pi/00730F01/acpi/northbridge.asl index f74b31a080..b317ccf1ea 100644 --- a/src/northbridge/amd/pi/00730F01/acpi/northbridge.asl +++ b/src/northbridge/amd/pi/00730F01/acpi/northbridge.asl @@ -16,10 +16,9 @@ /* Note: Only need HID on Primary Bus */ External (TOM1) External (TOM2) -Name(_HID, EISAID("PNP0A08")) /* PCI Express Root Bridge */ +/* Name(_HID, EISAID("PNP0A08")) // PCI Express Root Bridge */ Name(_CID, EISAID("PNP0A03")) /* PCI Root Bridge */ Name(_ADR, 0x00180000) /* Dev# = BSP Dev#, Func# = 0 */ - /* Describe the Northbridge devices */ Method(_BBN, 0, NotSerialized) /* Bus number = 0 */ diff --git a/src/soc/amd/stoneyridge/acpi/northbridge.asl b/src/soc/amd/stoneyridge/acpi/northbridge.asl index fe78534403..09bf2e18c2 100644 --- a/src/soc/amd/stoneyridge/acpi/northbridge.asl +++ b/src/soc/amd/stoneyridge/acpi/northbridge.asl @@ -17,7 +17,7 @@ /* Note: Only need HID on Primary Bus */ External (TOM1) External (TOM2) -Name(_HID, EISAID("PNP0A08")) /* PCI Express Root Bridge */ +/* Name(_HID, EISAID("PNP0A08")) // PCI Express Root Bridge */ Name(_CID, EISAID("PNP0A03")) /* PCI Root Bridge */ Name(_ADR, 0x00180000) /* Dev# = BSP Dev#, Func# = 0 */ diff --git a/src/soc/intel/broadwell/acpi/serialio.asl b/src/soc/intel/broadwell/acpi/serialio.asl index 1b44e9566a..fd25b0d8a8 100644 --- a/src/soc/intel/broadwell/acpi/serialio.asl +++ b/src/soc/intel/broadwell/acpi/serialio.asl @@ -157,7 +157,7 @@ Device (SIOR) Device (SDMA) { // Serial IO DMA Controller - Name (_HID, "INTL9C60") + /* Name (_HID, "INTL9C60") */ Name (_UID, 1) Name (_ADR, 0x00150000) @@ -205,7 +205,6 @@ Device (I2C0) Return ("INT33C2") } Name (_UID, 1) - Name (_ADR, 0x00150001) Name (SSCN, Package () { 432, 507, 30 }) Name (FMCN, Package () { 72, 160, 30 }) @@ -276,7 +275,6 @@ Device (I2C1) Return ("INT33C3") } Name (_UID, 1) - Name (_ADR, 0x00150002) Name (SSCN, Package () { 432, 507, 30 }) Name (FMCN, Package () { 72, 160, 30 }) @@ -347,7 +345,6 @@ Device (SPI0) Return ("INT33C0") } Name (_UID, 1) - Name (_ADR, 0x00150003) // BAR0 is assigned during PCI enumeration and saved into NVS Name (RBUF, ResourceTemplate () @@ -403,7 +400,6 @@ Device (SPI1) Return ("INT33C1") } Name (_UID, 1) - Name (_ADR, 0x00150004) // BAR0 is assigned during PCI enumeration and saved into NVS Name (RBUF, ResourceTemplate () @@ -471,7 +467,6 @@ Device (UAR0) Return ("INT33C4") } Name (_UID, 1) - Name (_ADR, 0x00150005) // BAR0 is assigned during PCI enumeration and saved into NVS Name (RBUF, ResourceTemplate () @@ -539,7 +534,6 @@ Device (UAR1) Return ("INT33C5") } Name (_UID, 1) - Name (_ADR, 0x00150006) // BAR0 is assigned during PCI enumeration and saved into NVS Name (RBUF, ResourceTemplate () @@ -596,7 +590,6 @@ Device (SDIO) } Name (_CID, "PNP0D40") Name (_UID, 1) - Name (_ADR, 0x00170000) // BAR0 is assigned during PCI enumeration and saved into NVS Name (RBUF, ResourceTemplate () diff --git a/src/southbridge/intel/lynxpoint/acpi/serialio.asl b/src/southbridge/intel/lynxpoint/acpi/serialio.asl index 9323b91cac..0eebe32dd6 100644 --- a/src/southbridge/intel/lynxpoint/acpi/serialio.asl +++ b/src/southbridge/intel/lynxpoint/acpi/serialio.asl @@ -123,7 +123,7 @@ Device (SIOR) Device (SDMA) { // Serial IO DMA Controller - Name (_HID, "INTL9C60") + /* Name (_HID, "INTL9C60") */ Name (_UID, 1) Name (_ADR, 0x00150000) @@ -163,7 +163,6 @@ Device (I2C0) Name (_HID, "INT33C2") Name (_CID, "INT33C2") Name (_UID, 1) - Name (_ADR, 0x00150001) Name (SSCN, Package () { 432, 507, 30 }) Name (FMCN, Package () { 72, 160, 30 }) @@ -245,7 +244,6 @@ Device (I2C1) Name (_HID, "INT33C3") Name (_CID, "INT33C3") Name (_UID, 1) - Name (_ADR, 0x00150002) Name (SSCN, Package () { 432, 507, 30 }) Name (FMCN, Package () { 72, 160, 30 }) @@ -327,7 +325,6 @@ Device (SPI0) Name (_HID, "INT33C0") Name (_CID, "INT33C0") Name (_UID, 1) - Name (_ADR, 0x00150003) // BAR0 is assigned during PCI enumeration and saved into NVS Name (RBUF, ResourceTemplate () @@ -365,7 +362,6 @@ Device (SPI1) Name (_HID, "INT33C1") Name (_CID, "INT33C1") Name (_UID, 1) - Name (_ADR, 0x00150004) // BAR0 is assigned during PCI enumeration and saved into NVS Name (RBUF, ResourceTemplate () @@ -416,7 +412,6 @@ Device (UAR0) Name (_HID, "INT33C4") Name (_CID, "INT33C4") Name (_UID, 1) - Name (_ADR, 0x00150005) // BAR0 is assigned during PCI enumeration and saved into NVS Name (RBUF, ResourceTemplate () @@ -467,7 +462,6 @@ Device (UAR1) Name (_HID, "INT33C5") Name (_CID, "INT33C5") Name (_UID, 1) - Name (_ADR, 0x00150006) // BAR0 is assigned during PCI enumeration and saved into NVS Name (RBUF, ResourceTemplate () @@ -505,7 +499,6 @@ Device (SDIO) Name (_HID, "INT33C6") Name (_CID, "PNP0D40") Name (_UID, 1) - Name (_ADR, 0x00170000) // BAR0 is assigned during PCI enumeration and saved into NVS Name (RBUF, ResourceTemplate () From 547de69de73629c051e9b5312f6369744ec6ce8f Mon Sep 17 00:00:00 2001 From: Elyes HAOUAS Date: Fri, 18 Oct 2019 20:51:22 +0200 Subject: [PATCH 0461/1242] crossgcc: Upgrade acpica to version 20191018 Changes: https://acpica.org/node/174 Change-Id: I72e44429f96c2ec82092c87aea46c3ff80755d4c Signed-off-by: Elyes HAOUAS Reviewed-on: https://review.coreboot.org/c/coreboot/+/34907 Tested-by: build bot (Jenkins) Reviewed-by: Angel Pons Reviewed-by: Martin Roth --- util/crossgcc/buildgcc | 2 +- ...ix2-20190703_iasl.patch => acpica-unix2-20191018_iasl.patch} | 0 util/crossgcc/sum/acpica-unix2-20190703.tar.gz.cksum | 1 - util/crossgcc/sum/acpica-unix2-20191018.tar.gz.cksum | 1 + 4 files changed, 2 insertions(+), 2 deletions(-) rename util/crossgcc/patches/{acpica-unix2-20190703_iasl.patch => acpica-unix2-20191018_iasl.patch} (100%) delete mode 100644 util/crossgcc/sum/acpica-unix2-20190703.tar.gz.cksum create mode 100644 util/crossgcc/sum/acpica-unix2-20191018.tar.gz.cksum diff --git a/util/crossgcc/buildgcc b/util/crossgcc/buildgcc index 5dac074a06..f1cf6bb8cf 100755 --- a/util/crossgcc/buildgcc +++ b/util/crossgcc/buildgcc @@ -54,7 +54,7 @@ GCC_VERSION=8.3.0 GCC_AUTOCONF_VERSION=2.69 BINUTILS_VERSION=2.33.1 GDB_VERSION=8.3.1 -IASL_VERSION=20190703 +IASL_VERSION=20191018 PYTHON_VERSION=3.8.0 EXPAT_VERSION=2.2.9 # CLANG version number diff --git a/util/crossgcc/patches/acpica-unix2-20190703_iasl.patch b/util/crossgcc/patches/acpica-unix2-20191018_iasl.patch similarity index 100% rename from util/crossgcc/patches/acpica-unix2-20190703_iasl.patch rename to util/crossgcc/patches/acpica-unix2-20191018_iasl.patch diff --git a/util/crossgcc/sum/acpica-unix2-20190703.tar.gz.cksum b/util/crossgcc/sum/acpica-unix2-20190703.tar.gz.cksum deleted file mode 100644 index 9a89796d53..0000000000 --- a/util/crossgcc/sum/acpica-unix2-20190703.tar.gz.cksum +++ /dev/null @@ -1 +0,0 @@ -c5594944f933265a53695204a0672d0808e4a580 tarballs/acpica-unix2-20190703.tar.gz diff --git a/util/crossgcc/sum/acpica-unix2-20191018.tar.gz.cksum b/util/crossgcc/sum/acpica-unix2-20191018.tar.gz.cksum new file mode 100644 index 0000000000..3df9d27cb3 --- /dev/null +++ b/util/crossgcc/sum/acpica-unix2-20191018.tar.gz.cksum @@ -0,0 +1 @@ +792e2ec4dcd78646de8405578d28f7437aacf811 tarballs/acpica-unix2-20191018.tar.gz From 34ac1ab4a3172fc821e47824f107873da25d8991 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ky=C3=B6sti=20M=C3=A4lkki?= Date: Thu, 28 Nov 2019 17:51:50 +0200 Subject: [PATCH 0462/1242] AGESA,binaryPI: Flag boards with ROMCC_BOOTBLOCK MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Allows boards to be transformed to C env bootblock one at a time. Change-Id: I1cc1910a8bfb6b3495593979cbf7194b0d82c8e1 Signed-off-by: Kyösti Mälkki Reviewed-on: https://review.coreboot.org/c/coreboot/+/37345 Reviewed-by: Angel Pons Reviewed-by: Michał Żygowski Tested-by: build bot (Jenkins) --- src/mainboard/amd/bettong/Kconfig | 1 + src/mainboard/amd/db-ft3b-lc/Kconfig | 1 + src/mainboard/amd/inagua/Kconfig | 1 + src/mainboard/amd/lamar/Kconfig | 1 + src/mainboard/amd/olivehill/Kconfig | 1 + src/mainboard/amd/olivehillplus/Kconfig | 1 + src/mainboard/amd/parmer/Kconfig | 1 + src/mainboard/amd/persimmon/Kconfig | 1 + src/mainboard/amd/south_station/Kconfig | 1 + src/mainboard/amd/thatcher/Kconfig | 1 + src/mainboard/amd/union_station/Kconfig | 1 + src/mainboard/asrock/e350m1/Kconfig | 1 + src/mainboard/asrock/imb-a180/Kconfig | 1 + src/mainboard/asus/am1i-a/Kconfig | 1 + src/mainboard/asus/f2a85-m/Kconfig | 1 + src/mainboard/bap/ode_e20XX/Kconfig | 1 + src/mainboard/bap/ode_e21XX/Kconfig | 1 + src/mainboard/biostar/a68n_5200/Kconfig | 1 + src/mainboard/biostar/am1ml/Kconfig | 1 + src/mainboard/elmex/pcm205400/Kconfig | 1 + src/mainboard/gizmosphere/gizmo/Kconfig | 1 + src/mainboard/gizmosphere/gizmo2/Kconfig | 1 + src/mainboard/hp/abm/Kconfig | 1 + src/mainboard/hp/pavilion_m6_1035dx/Kconfig | 1 + src/mainboard/jetway/nf81-t56n-lf/Kconfig | 1 + src/mainboard/lenovo/g505s/Kconfig | 1 + src/mainboard/lippert/frontrunner-af/Kconfig | 1 + src/mainboard/lippert/toucan-af/Kconfig | 1 + src/mainboard/msi/ms7721/Kconfig | 1 + src/mainboard/pcengines/apu1/Kconfig | 1 + src/mainboard/pcengines/apu2/Kconfig | 1 + src/northbridge/amd/agesa/Kconfig | 1 - src/northbridge/amd/pi/Kconfig | 1 - 33 files changed, 31 insertions(+), 2 deletions(-) diff --git a/src/mainboard/amd/bettong/Kconfig b/src/mainboard/amd/bettong/Kconfig index 0747bc1df5..f5f37cef77 100644 --- a/src/mainboard/amd/bettong/Kconfig +++ b/src/mainboard/amd/bettong/Kconfig @@ -21,6 +21,7 @@ if BOARD_AMD_BETTONG config BOARD_SPECIFIC_OPTIONS def_bool y #select BINARYPI_LEGACY_WRAPPER + select ROMCC_BOOTBLOCK select CPU_AMD_PI_00660F01 select NORTHBRIDGE_AMD_PI_00660F01 select SOUTHBRIDGE_AMD_PI_KERN diff --git a/src/mainboard/amd/db-ft3b-lc/Kconfig b/src/mainboard/amd/db-ft3b-lc/Kconfig index d7650327ff..b83a5253d2 100644 --- a/src/mainboard/amd/db-ft3b-lc/Kconfig +++ b/src/mainboard/amd/db-ft3b-lc/Kconfig @@ -22,6 +22,7 @@ if BOARD_AMD_DB_FT3B_LC config BOARD_SPECIFIC_OPTIONS def_bool y #select BINARYPI_LEGACY_WRAPPER + select ROMCC_BOOTBLOCK select CPU_AMD_PI_00730F01 select NORTHBRIDGE_AMD_PI_00730F01 select SOUTHBRIDGE_AMD_PI_AVALON diff --git a/src/mainboard/amd/inagua/Kconfig b/src/mainboard/amd/inagua/Kconfig index e24af4044a..541868bd71 100644 --- a/src/mainboard/amd/inagua/Kconfig +++ b/src/mainboard/amd/inagua/Kconfig @@ -17,6 +17,7 @@ if BOARD_AMD_INAGUA config BOARD_SPECIFIC_OPTIONS def_bool y + select ROMCC_BOOTBLOCK select CPU_AMD_AGESA_FAMILY14 select NORTHBRIDGE_AMD_AGESA_FAMILY14 select SOUTHBRIDGE_AMD_CIMX_SB800 diff --git a/src/mainboard/amd/lamar/Kconfig b/src/mainboard/amd/lamar/Kconfig index e216e0260c..1d3e0f66a7 100644 --- a/src/mainboard/amd/lamar/Kconfig +++ b/src/mainboard/amd/lamar/Kconfig @@ -21,6 +21,7 @@ if BOARD_AMD_LAMAR config BOARD_SPECIFIC_OPTIONS def_bool y #select BINARYPI_LEGACY_WRAPPER + select ROMCC_BOOTBLOCK select CPU_AMD_PI_00630F01 select NORTHBRIDGE_AMD_PI_00630F01 select SOUTHBRIDGE_AMD_PI_BOLTON diff --git a/src/mainboard/amd/olivehill/Kconfig b/src/mainboard/amd/olivehill/Kconfig index bd9a2fee81..806fdbd1d8 100644 --- a/src/mainboard/amd/olivehill/Kconfig +++ b/src/mainboard/amd/olivehill/Kconfig @@ -17,6 +17,7 @@ if BOARD_AMD_OLIVEHILL config BOARD_SPECIFIC_OPTIONS def_bool y + select ROMCC_BOOTBLOCK select CPU_AMD_AGESA_FAMILY16_KB select NORTHBRIDGE_AMD_AGESA_FAMILY16_KB select SOUTHBRIDGE_AMD_AGESA_YANGTZE diff --git a/src/mainboard/amd/olivehillplus/Kconfig b/src/mainboard/amd/olivehillplus/Kconfig index 3a72b2bb19..230dc4b25d 100644 --- a/src/mainboard/amd/olivehillplus/Kconfig +++ b/src/mainboard/amd/olivehillplus/Kconfig @@ -21,6 +21,7 @@ if BOARD_AMD_OLIVEHILLPLUS config BOARD_SPECIFIC_OPTIONS def_bool y #select BINARYPI_LEGACY_WRAPPER + select ROMCC_BOOTBLOCK select CPU_AMD_PI_00730F01 select NORTHBRIDGE_AMD_PI_00730F01 select SOUTHBRIDGE_AMD_PI_AVALON diff --git a/src/mainboard/amd/parmer/Kconfig b/src/mainboard/amd/parmer/Kconfig index 6d989b63ff..dde58a6fd4 100644 --- a/src/mainboard/amd/parmer/Kconfig +++ b/src/mainboard/amd/parmer/Kconfig @@ -17,6 +17,7 @@ if BOARD_AMD_PARMER config BOARD_SPECIFIC_OPTIONS def_bool y + select ROMCC_BOOTBLOCK select CPU_AMD_AGESA_FAMILY15_TN select NORTHBRIDGE_AMD_AGESA_FAMILY15_TN select SOUTHBRIDGE_AMD_AGESA_HUDSON diff --git a/src/mainboard/amd/persimmon/Kconfig b/src/mainboard/amd/persimmon/Kconfig index 41bf3c9c2e..005741e8b4 100644 --- a/src/mainboard/amd/persimmon/Kconfig +++ b/src/mainboard/amd/persimmon/Kconfig @@ -17,6 +17,7 @@ if BOARD_AMD_PERSIMMON config BOARD_SPECIFIC_OPTIONS def_bool y + select ROMCC_BOOTBLOCK select CPU_AMD_AGESA_FAMILY14 select NORTHBRIDGE_AMD_AGESA_FAMILY14 select SOUTHBRIDGE_AMD_CIMX_SB800 diff --git a/src/mainboard/amd/south_station/Kconfig b/src/mainboard/amd/south_station/Kconfig index a059403c7b..f10ff7a940 100644 --- a/src/mainboard/amd/south_station/Kconfig +++ b/src/mainboard/amd/south_station/Kconfig @@ -17,6 +17,7 @@ if BOARD_AMD_SOUTHSTATION config BOARD_SPECIFIC_OPTIONS def_bool y + select ROMCC_BOOTBLOCK select CPU_AMD_AGESA_FAMILY14 select NORTHBRIDGE_AMD_AGESA_FAMILY14 select SOUTHBRIDGE_AMD_CIMX_SB800 diff --git a/src/mainboard/amd/thatcher/Kconfig b/src/mainboard/amd/thatcher/Kconfig index a957d4c965..e11d0ea1d9 100644 --- a/src/mainboard/amd/thatcher/Kconfig +++ b/src/mainboard/amd/thatcher/Kconfig @@ -17,6 +17,7 @@ if BOARD_AMD_THATCHER config BOARD_SPECIFIC_OPTIONS def_bool y + select ROMCC_BOOTBLOCK select CPU_AMD_AGESA_FAMILY15_TN select NORTHBRIDGE_AMD_AGESA_FAMILY15_TN select SOUTHBRIDGE_AMD_AGESA_HUDSON diff --git a/src/mainboard/amd/union_station/Kconfig b/src/mainboard/amd/union_station/Kconfig index 72881b8d4c..f03fb08f8b 100644 --- a/src/mainboard/amd/union_station/Kconfig +++ b/src/mainboard/amd/union_station/Kconfig @@ -17,6 +17,7 @@ if BOARD_AMD_UNIONSTATION config BOARD_SPECIFIC_OPTIONS def_bool y + select ROMCC_BOOTBLOCK select CPU_AMD_AGESA_FAMILY14 select NORTHBRIDGE_AMD_AGESA_FAMILY14 select SOUTHBRIDGE_AMD_CIMX_SB800 diff --git a/src/mainboard/asrock/e350m1/Kconfig b/src/mainboard/asrock/e350m1/Kconfig index 3bbc2a5150..86eaac8ba5 100644 --- a/src/mainboard/asrock/e350m1/Kconfig +++ b/src/mainboard/asrock/e350m1/Kconfig @@ -17,6 +17,7 @@ if BOARD_ASROCK_E350M1 config BOARD_SPECIFIC_OPTIONS def_bool y + select ROMCC_BOOTBLOCK select CPU_AMD_AGESA_FAMILY14 select NORTHBRIDGE_AMD_AGESA_FAMILY14 select SOUTHBRIDGE_AMD_CIMX_SB800 diff --git a/src/mainboard/asrock/imb-a180/Kconfig b/src/mainboard/asrock/imb-a180/Kconfig index 2391202cff..883b1c04e4 100644 --- a/src/mainboard/asrock/imb-a180/Kconfig +++ b/src/mainboard/asrock/imb-a180/Kconfig @@ -17,6 +17,7 @@ if BOARD_ASROCK_IMB_A180 config BOARD_SPECIFIC_OPTIONS def_bool y + select ROMCC_BOOTBLOCK select CPU_AMD_AGESA_FAMILY16_KB select NORTHBRIDGE_AMD_AGESA_FAMILY16_KB select SOUTHBRIDGE_AMD_AGESA_YANGTZE diff --git a/src/mainboard/asus/am1i-a/Kconfig b/src/mainboard/asus/am1i-a/Kconfig index 0aafd8ba64..c3f21e9531 100644 --- a/src/mainboard/asus/am1i-a/Kconfig +++ b/src/mainboard/asus/am1i-a/Kconfig @@ -3,6 +3,7 @@ if BOARD_ASUS_AM1I_A config BOARD_SPECIFIC_OPTIONS def_bool y select BOARD_ROMSIZE_KB_8192 + select ROMCC_BOOTBLOCK select CPU_AMD_AGESA_FAMILY16_KB select FORCE_AM1_SOCKET_SUPPORT select GFXUMA diff --git a/src/mainboard/asus/f2a85-m/Kconfig b/src/mainboard/asus/f2a85-m/Kconfig index c1dd063c77..cd10e536a4 100644 --- a/src/mainboard/asus/f2a85-m/Kconfig +++ b/src/mainboard/asus/f2a85-m/Kconfig @@ -18,6 +18,7 @@ if BOARD_ASUS_F2A85_M || BOARD_ASUS_F2A85_M_PRO || BOARD_ASUS_F2A85_M_LE config BOARD_SPECIFIC_OPTIONS def_bool y + select ROMCC_BOOTBLOCK select CPU_AMD_AGESA_FAMILY15_TN select NORTHBRIDGE_AMD_AGESA_FAMILY15_TN select SOUTHBRIDGE_AMD_AGESA_HUDSON diff --git a/src/mainboard/bap/ode_e20XX/Kconfig b/src/mainboard/bap/ode_e20XX/Kconfig index 1d526399f1..a62fba82da 100644 --- a/src/mainboard/bap/ode_e20XX/Kconfig +++ b/src/mainboard/bap/ode_e20XX/Kconfig @@ -18,6 +18,7 @@ if BOARD_ODE_E20XX config BOARD_SPECIFIC_OPTIONS def_bool y + select ROMCC_BOOTBLOCK select CPU_AMD_AGESA_FAMILY16_KB select NORTHBRIDGE_AMD_AGESA_FAMILY16_KB select SOUTHBRIDGE_AMD_AGESA_YANGTZE diff --git a/src/mainboard/bap/ode_e21XX/Kconfig b/src/mainboard/bap/ode_e21XX/Kconfig index a35107d77b..3705fb9615 100644 --- a/src/mainboard/bap/ode_e21XX/Kconfig +++ b/src/mainboard/bap/ode_e21XX/Kconfig @@ -21,6 +21,7 @@ if BOARD_ODE_E21XX config BOARD_SPECIFIC_OPTIONS def_bool y #select BINARYPI_LEGACY_WRAPPER + select ROMCC_BOOTBLOCK select CPU_AMD_PI_00730F01 select NORTHBRIDGE_AMD_PI_00730F01 select SOUTHBRIDGE_AMD_PI_AVALON diff --git a/src/mainboard/biostar/a68n_5200/Kconfig b/src/mainboard/biostar/a68n_5200/Kconfig index e4271d34fe..a452569a9b 100644 --- a/src/mainboard/biostar/a68n_5200/Kconfig +++ b/src/mainboard/biostar/a68n_5200/Kconfig @@ -19,6 +19,7 @@ if BOARD_BIOSTAR_A68N5200 config BOARD_SPECIFIC_OPTIONS def_bool y + select ROMCC_BOOTBLOCK select CPU_AMD_AGESA_FAMILY16_KB select NORTHBRIDGE_AMD_AGESA_FAMILY16_KB select SOUTHBRIDGE_AMD_AGESA_YANGTZE diff --git a/src/mainboard/biostar/am1ml/Kconfig b/src/mainboard/biostar/am1ml/Kconfig index 31aa5f061b..4ea5ddc3c7 100644 --- a/src/mainboard/biostar/am1ml/Kconfig +++ b/src/mainboard/biostar/am1ml/Kconfig @@ -19,6 +19,7 @@ if BOARD_BIOSTAR_AM1ML config BOARD_SPECIFIC_OPTIONS def_bool y select BOARD_ROMSIZE_KB_4096 + select ROMCC_BOOTBLOCK select CPU_AMD_AGESA_FAMILY16_KB select FORCE_AM1_SOCKET_SUPPORT select GFXUMA diff --git a/src/mainboard/elmex/pcm205400/Kconfig b/src/mainboard/elmex/pcm205400/Kconfig index 7dc67d17ea..14254ca02d 100644 --- a/src/mainboard/elmex/pcm205400/Kconfig +++ b/src/mainboard/elmex/pcm205400/Kconfig @@ -29,6 +29,7 @@ if BOARD_ELMEX_PCM205400 || BOARD_ELMEX_PCM205401 config BOARD_SPECIFIC_OPTIONS def_bool y + select ROMCC_BOOTBLOCK select CPU_AMD_AGESA_FAMILY14 select NORTHBRIDGE_AMD_AGESA_FAMILY14 select SOUTHBRIDGE_AMD_CIMX_SB800 diff --git a/src/mainboard/gizmosphere/gizmo/Kconfig b/src/mainboard/gizmosphere/gizmo/Kconfig index e195e8f0a2..e1c286be8e 100644 --- a/src/mainboard/gizmosphere/gizmo/Kconfig +++ b/src/mainboard/gizmosphere/gizmo/Kconfig @@ -18,6 +18,7 @@ if BOARD_GIZMOSPHERE_GIZMO config BOARD_SPECIFIC_OPTIONS def_bool y + select ROMCC_BOOTBLOCK select CPU_AMD_AGESA_FAMILY14 select NORTHBRIDGE_AMD_AGESA_FAMILY14 select SOUTHBRIDGE_AMD_CIMX_SB800 diff --git a/src/mainboard/gizmosphere/gizmo2/Kconfig b/src/mainboard/gizmosphere/gizmo2/Kconfig index 034b6eeaf3..27a3b35c80 100644 --- a/src/mainboard/gizmosphere/gizmo2/Kconfig +++ b/src/mainboard/gizmosphere/gizmo2/Kconfig @@ -18,6 +18,7 @@ if BOARD_GIZMOSPHERE_GIZMO2 config BOARD_SPECIFIC_OPTIONS def_bool y + select ROMCC_BOOTBLOCK select CPU_AMD_AGESA_FAMILY16_KB select NORTHBRIDGE_AMD_AGESA_FAMILY16_KB select SOUTHBRIDGE_AMD_AGESA_YANGTZE diff --git a/src/mainboard/hp/abm/Kconfig b/src/mainboard/hp/abm/Kconfig index 5ba1b5b857..a179dbe8ca 100644 --- a/src/mainboard/hp/abm/Kconfig +++ b/src/mainboard/hp/abm/Kconfig @@ -18,6 +18,7 @@ if BOARD_HP_ABM config BOARD_SPECIFIC_OPTIONS def_bool y + select ROMCC_BOOTBLOCK select CPU_AMD_AGESA_FAMILY16_KB select NORTHBRIDGE_AMD_AGESA_FAMILY16_KB select SOUTHBRIDGE_AMD_AGESA_YANGTZE diff --git a/src/mainboard/hp/pavilion_m6_1035dx/Kconfig b/src/mainboard/hp/pavilion_m6_1035dx/Kconfig index 3c67e2ad07..05ea52ff20 100644 --- a/src/mainboard/hp/pavilion_m6_1035dx/Kconfig +++ b/src/mainboard/hp/pavilion_m6_1035dx/Kconfig @@ -18,6 +18,7 @@ if BOARD_HP_PAVILION_M6_1035DX config BOARD_SPECIFIC_OPTIONS def_bool y select SYSTEM_TYPE_LAPTOP + select ROMCC_BOOTBLOCK select CPU_AMD_AGESA_FAMILY15_TN select NORTHBRIDGE_AMD_AGESA_FAMILY15_TN select SOUTHBRIDGE_AMD_AGESA_HUDSON diff --git a/src/mainboard/jetway/nf81-t56n-lf/Kconfig b/src/mainboard/jetway/nf81-t56n-lf/Kconfig index d2dda6725f..95d3b7ef11 100644 --- a/src/mainboard/jetway/nf81-t56n-lf/Kconfig +++ b/src/mainboard/jetway/nf81-t56n-lf/Kconfig @@ -18,6 +18,7 @@ if BOARD_JETWAY_NF81_T56N_LF config BOARD_SPECIFIC_OPTIONS def_bool y + select ROMCC_BOOTBLOCK select CPU_AMD_AGESA_FAMILY14 select NORTHBRIDGE_AMD_AGESA_FAMILY14 select SOUTHBRIDGE_AMD_CIMX_SB800 diff --git a/src/mainboard/lenovo/g505s/Kconfig b/src/mainboard/lenovo/g505s/Kconfig index a277145f2c..815c7d5734 100644 --- a/src/mainboard/lenovo/g505s/Kconfig +++ b/src/mainboard/lenovo/g505s/Kconfig @@ -18,6 +18,7 @@ if BOARD_LENOVO_G505S config BOARD_SPECIFIC_OPTIONS def_bool y select SYSTEM_TYPE_LAPTOP + select ROMCC_BOOTBLOCK select CPU_AMD_AGESA_FAMILY15_TN select NORTHBRIDGE_AMD_AGESA_FAMILY15_TN select SOUTHBRIDGE_AMD_AGESA_HUDSON diff --git a/src/mainboard/lippert/frontrunner-af/Kconfig b/src/mainboard/lippert/frontrunner-af/Kconfig index 92d77434f5..8b33810ada 100644 --- a/src/mainboard/lippert/frontrunner-af/Kconfig +++ b/src/mainboard/lippert/frontrunner-af/Kconfig @@ -17,6 +17,7 @@ if BOARD_LIPPERT_FRONTRUNNER_AF config BOARD_SPECIFIC_OPTIONS def_bool y + select ROMCC_BOOTBLOCK select CPU_AMD_AGESA_FAMILY14 select NORTHBRIDGE_AMD_AGESA_FAMILY14 select SOUTHBRIDGE_AMD_CIMX_SB800 diff --git a/src/mainboard/lippert/toucan-af/Kconfig b/src/mainboard/lippert/toucan-af/Kconfig index 74b335a9fa..146af07821 100644 --- a/src/mainboard/lippert/toucan-af/Kconfig +++ b/src/mainboard/lippert/toucan-af/Kconfig @@ -17,6 +17,7 @@ if BOARD_LIPPERT_TOUCAN_AF config BOARD_SPECIFIC_OPTIONS def_bool y + select ROMCC_BOOTBLOCK select CPU_AMD_AGESA_FAMILY14 select NORTHBRIDGE_AMD_AGESA_FAMILY14 select SOUTHBRIDGE_AMD_CIMX_SB800 diff --git a/src/mainboard/msi/ms7721/Kconfig b/src/mainboard/msi/ms7721/Kconfig index 1fee74790e..779d3b1baa 100644 --- a/src/mainboard/msi/ms7721/Kconfig +++ b/src/mainboard/msi/ms7721/Kconfig @@ -20,6 +20,7 @@ if BOARD_MSI_MS7721 config BOARD_SPECIFIC_OPTIONS def_bool y + select ROMCC_BOOTBLOCK select CPU_AMD_AGESA_FAMILY15_TN select NORTHBRIDGE_AMD_AGESA_FAMILY15_TN select SOUTHBRIDGE_AMD_AGESA_HUDSON diff --git a/src/mainboard/pcengines/apu1/Kconfig b/src/mainboard/pcengines/apu1/Kconfig index 3396845559..168423632b 100644 --- a/src/mainboard/pcengines/apu1/Kconfig +++ b/src/mainboard/pcengines/apu1/Kconfig @@ -18,6 +18,7 @@ if BOARD_PCENGINES_APU1 config BOARD_SPECIFIC_OPTIONS def_bool y + select ROMCC_BOOTBLOCK select CPU_AMD_AGESA_FAMILY14 select NORTHBRIDGE_AMD_AGESA_FAMILY14 select SOUTHBRIDGE_AMD_CIMX_SB800 diff --git a/src/mainboard/pcengines/apu2/Kconfig b/src/mainboard/pcengines/apu2/Kconfig index 372f67df6a..5ecdb88991 100644 --- a/src/mainboard/pcengines/apu2/Kconfig +++ b/src/mainboard/pcengines/apu2/Kconfig @@ -20,6 +20,7 @@ if BOARD_PCENGINES_APU2 || BOARD_PCENGINES_APU3 || BOARD_PCENGINES_APU4 || \ config BOARD_SPECIFIC_OPTIONS def_bool y + select ROMCC_BOOTBLOCK select CPU_AMD_PI_00730F01 select NORTHBRIDGE_AMD_PI_00730F01 select SOUTHBRIDGE_AMD_PI_AVALON diff --git a/src/northbridge/amd/agesa/Kconfig b/src/northbridge/amd/agesa/Kconfig index 50dba252fe..e1e129a97d 100644 --- a/src/northbridge/amd/agesa/Kconfig +++ b/src/northbridge/amd/agesa/Kconfig @@ -17,7 +17,6 @@ config NORTHBRIDGE_AMD_AGESA bool default CPU_AMD_AGESA select CBMEM_TOP_BACKUP - select ROMCC_BOOTBLOCK if NORTHBRIDGE_AMD_AGESA diff --git a/src/northbridge/amd/pi/Kconfig b/src/northbridge/amd/pi/Kconfig index 167d957268..38ee5b32ab 100644 --- a/src/northbridge/amd/pi/Kconfig +++ b/src/northbridge/amd/pi/Kconfig @@ -18,7 +18,6 @@ config NORTHBRIDGE_AMD_PI default y if CPU_AMD_PI default n select CBMEM_TOP_BACKUP - select ROMCC_BOOTBLOCK if NORTHBRIDGE_AMD_PI From aeb85d53e90728bf758b08895c7ed5dbf9cf3062 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ky=C3=B6sti=20M=C3=A4lkki?= Date: Fri, 29 Nov 2019 06:37:52 +0200 Subject: [PATCH 0463/1242] binaryPI: Clean leftover romstage prototype MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Change-Id: Ie9e7a88f1f8dce967772e7c5ecf4aea971bb1c3f Signed-off-by: Kyösti Mälkki Reviewed-on: https://review.coreboot.org/c/coreboot/+/37346 Reviewed-by: Angel Pons Reviewed-by: Michał Żygowski Tested-by: build bot (Jenkins) --- src/include/cpu/amd/car.h | 2 -- src/mainboard/amd/bettong/romstage.c | 3 +-- src/mainboard/amd/db-ft3b-lc/romstage.c | 6 +++--- src/mainboard/amd/lamar/romstage.c | 3 +-- src/mainboard/amd/olivehillplus/romstage.c | 3 +-- src/mainboard/bap/ode_e21XX/romstage.c | 3 +-- src/mainboard/pcengines/apu2/romstage.c | 1 - 7 files changed, 7 insertions(+), 14 deletions(-) diff --git a/src/include/cpu/amd/car.h b/src/include/cpu/amd/car.h index 46f7e1d5c9..be7b69a942 100644 --- a/src/include/cpu/amd/car.h +++ b/src/include/cpu/amd/car.h @@ -3,8 +3,6 @@ #include -void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx); - void *asmlinkage romstage_main(unsigned long bist); #endif diff --git a/src/mainboard/amd/bettong/romstage.c b/src/mainboard/amd/bettong/romstage.c index 32f52de707..03e6585b9a 100644 --- a/src/mainboard/amd/bettong/romstage.c +++ b/src/mainboard/amd/bettong/romstage.c @@ -19,11 +19,10 @@ #include #include #include -#include #include #include -void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) +static void romstage_main_template(void) { u32 val; diff --git a/src/mainboard/amd/db-ft3b-lc/romstage.c b/src/mainboard/amd/db-ft3b-lc/romstage.c index 495ce59eff..2979cf4ae4 100644 --- a/src/mainboard/amd/db-ft3b-lc/romstage.c +++ b/src/mainboard/amd/db-ft3b-lc/romstage.c @@ -19,13 +19,13 @@ #include #include #include -#include #include #include #include -void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) -{ u32 val; +static void romstage_main_template(void) +{ + u32 val; /* * In Hudson RRG, PMIOxD2[5:4] is "Drive strength control for diff --git a/src/mainboard/amd/lamar/romstage.c b/src/mainboard/amd/lamar/romstage.c index 77a0ea02f7..67485f4f11 100644 --- a/src/mainboard/amd/lamar/romstage.c +++ b/src/mainboard/amd/lamar/romstage.c @@ -19,7 +19,6 @@ #include #include #include -#include #include #include #include @@ -28,7 +27,7 @@ #define SERIAL_DEV PNP_DEV(0x4e, F81216H_SP1) -void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) +static void romstage_main_template(void) { u32 val; diff --git a/src/mainboard/amd/olivehillplus/romstage.c b/src/mainboard/amd/olivehillplus/romstage.c index 6df12e31cc..519825827a 100644 --- a/src/mainboard/amd/olivehillplus/romstage.c +++ b/src/mainboard/amd/olivehillplus/romstage.c @@ -19,12 +19,11 @@ #include #include #include -#include #include #include #include -void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) +static void romstage_main_template(void) { u32 val; diff --git a/src/mainboard/bap/ode_e21XX/romstage.c b/src/mainboard/bap/ode_e21XX/romstage.c index 774cd990b6..4c5a51b5a5 100644 --- a/src/mainboard/bap/ode_e21XX/romstage.c +++ b/src/mainboard/bap/ode_e21XX/romstage.c @@ -19,7 +19,6 @@ #include #include #include -#include #include #include #include @@ -28,7 +27,7 @@ #define SERIAL_DEV1 PNP_DEV(0x4e, F81866D_SP1) -void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) +static void romstage_main_template(void) { u32 val; diff --git a/src/mainboard/pcengines/apu2/romstage.c b/src/mainboard/pcengines/apu2/romstage.c index 4df1e47d99..8eb18181b5 100644 --- a/src/mainboard/pcengines/apu2/romstage.c +++ b/src/mainboard/pcengines/apu2/romstage.c @@ -21,7 +21,6 @@ #include #include #include -#include #include #include #include From ce51d6d9d1ba9d49d0176f821c639aa2384f5582 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ky=C3=B6sti=20M=C3=A4lkki?= Date: Fri, 29 Nov 2019 06:15:54 +0200 Subject: [PATCH 0464/1242] binaryPI boards: Remove BIST reporting MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Can be restored with C environment bootblock. Change-Id: I077d7bf088a0ffc65e9ec0d0b1c239194dc4f4ca Signed-off-by: Kyösti Mälkki Reviewed-on: https://review.coreboot.org/c/coreboot/+/37347 Reviewed-by: Arthur Heymans Reviewed-by: Angel Pons Reviewed-by: Michał Żygowski Tested-by: build bot (Jenkins) --- src/mainboard/amd/bettong/romstage.c | 8 ++++---- src/mainboard/amd/db-ft3b-lc/romstage.c | 5 ----- src/mainboard/amd/lamar/romstage.c | 5 ----- src/mainboard/amd/olivehillplus/romstage.c | 5 ----- src/mainboard/bap/ode_e21XX/romstage.c | 5 ----- src/mainboard/pcengines/apu2/romstage.c | 1 - 6 files changed, 4 insertions(+), 25 deletions(-) diff --git a/src/mainboard/amd/bettong/romstage.c b/src/mainboard/amd/bettong/romstage.c index 03e6585b9a..c9a257cec5 100644 --- a/src/mainboard/amd/bettong/romstage.c +++ b/src/mainboard/amd/bettong/romstage.c @@ -18,10 +18,13 @@ #include #include #include -#include #include #include +/* Mask BIST bit 31. One result of Silicon Observation + * report_bist_failure(bist & 0x7FFFFFFF); + */ + static void romstage_main_template(void) { u32 val; @@ -38,9 +41,6 @@ static void romstage_main_template(void) console_init(); } - /* Halt if there was a built in self test failure */ - post_code(0x34); - report_bist_failure(bist & 0x7FFFFFFF); /* Mask bit 31. One result of Silicon Observation */ /* Load MPB */ val = cpuid_eax(1); diff --git a/src/mainboard/amd/db-ft3b-lc/romstage.c b/src/mainboard/amd/db-ft3b-lc/romstage.c index 2979cf4ae4..475431e419 100644 --- a/src/mainboard/amd/db-ft3b-lc/romstage.c +++ b/src/mainboard/amd/db-ft3b-lc/romstage.c @@ -20,7 +20,6 @@ #include #include #include -#include #include static void romstage_main_template(void) @@ -47,10 +46,6 @@ static void romstage_main_template(void) console_init(); } - /* Halt if there was a built in self test failure */ - post_code(0x34); - report_bist_failure(bist); - /* Load MPB */ val = cpuid_eax(1); printk(BIOS_DEBUG, "BSP Family_Model: %08x\n", val); diff --git a/src/mainboard/amd/lamar/romstage.c b/src/mainboard/amd/lamar/romstage.c index 67485f4f11..4dde4e2e3f 100644 --- a/src/mainboard/amd/lamar/romstage.c +++ b/src/mainboard/amd/lamar/romstage.c @@ -20,7 +20,6 @@ #include #include #include -#include #include #include #include @@ -58,10 +57,6 @@ static void romstage_main_template(void) console_init(); } - /* Halt if there was a built in self test failure */ - post_code(0x34); - report_bist_failure(bist); - /* Load MPB */ val = cpuid_eax(1); printk(BIOS_DEBUG, "BSP Family_Model: %08x\n", val); diff --git a/src/mainboard/amd/olivehillplus/romstage.c b/src/mainboard/amd/olivehillplus/romstage.c index 519825827a..bb80687b60 100644 --- a/src/mainboard/amd/olivehillplus/romstage.c +++ b/src/mainboard/amd/olivehillplus/romstage.c @@ -20,7 +20,6 @@ #include #include #include -#include #include static void romstage_main_template(void) @@ -47,10 +46,6 @@ static void romstage_main_template(void) console_init(); } - /* Halt if there was a built in self test failure */ - post_code(0x34); - report_bist_failure(bist); - /* Load MPB */ val = cpuid_eax(1); printk(BIOS_DEBUG, "BSP Family_Model: %08x\n", val); diff --git a/src/mainboard/bap/ode_e21XX/romstage.c b/src/mainboard/bap/ode_e21XX/romstage.c index 4c5a51b5a5..e58f875f2f 100644 --- a/src/mainboard/bap/ode_e21XX/romstage.c +++ b/src/mainboard/bap/ode_e21XX/romstage.c @@ -20,7 +20,6 @@ #include #include #include -#include #include #include #include @@ -51,10 +50,6 @@ static void romstage_main_template(void) console_init(); } - /* Halt if there was a built in self test failure */ - post_code(0x34); - report_bist_failure(bist); - /* Load MPB */ val = cpuid_eax(1); printk(BIOS_DEBUG, "BSP Family_Model: %08x\n", val); diff --git a/src/mainboard/pcengines/apu2/romstage.c b/src/mainboard/pcengines/apu2/romstage.c index 8eb18181b5..6c97c576c1 100644 --- a/src/mainboard/pcengines/apu2/romstage.c +++ b/src/mainboard/pcengines/apu2/romstage.c @@ -22,7 +22,6 @@ #include #include #include -#include #include #include #include From dc34a9d6de6ab21a1f1ed1a6cba142585c092045 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ky=C3=B6sti=20M=C3=A4lkki?= Date: Thu, 28 Nov 2019 15:04:17 +0200 Subject: [PATCH 0465/1242] AGESA,binaryPI: Split romstage_main() to BSP and AP parts MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit BSP and AP have two distinct execution paths for romstage. Change-Id: Id013b165f1345509fe6b74cef2bf8c3b420f84a4 Signed-off-by: Kyösti Mälkki Reviewed-on: https://review.coreboot.org/c/coreboot/+/37326 Reviewed-by: Angel Pons Reviewed-by: Arthur Heymans Reviewed-by: Michał Żygowski Tested-by: build bot (Jenkins) --- src/drivers/amd/agesa/romstage.c | 34 +++++++++++++++++++++++++++++--- src/include/cpu/amd/car.h | 2 +- 2 files changed, 32 insertions(+), 4 deletions(-) diff --git a/src/drivers/amd/agesa/romstage.c b/src/drivers/amd/agesa/romstage.c index 0ecfeb2bb6..f9a8c9705a 100644 --- a/src/drivers/amd/agesa/romstage.c +++ b/src/drivers/amd/agesa/romstage.c @@ -40,7 +40,7 @@ static void fill_sysinfo(struct sysinfo *cb) agesa_set_interface(cb); } -void *asmlinkage romstage_main(unsigned long bist) +static void bsp_romstage_main(unsigned long bist) { struct postcar_frame pcf; struct sysinfo romstage_state; @@ -53,7 +53,7 @@ void *asmlinkage romstage_main(unsigned long bist) fill_sysinfo(cb); - if ((initial_apic_id == 0) && boot_cpu()) { + if (initial_apic_id == 0) { timestamp_init(timestamp_get()); timestamp_add_now(TS_START_ROMSTAGE); @@ -101,5 +101,33 @@ void *asmlinkage romstage_main(unsigned long bist) run_postcar_phase(&pcf); /* We do not return. */ - return NULL; +} + +static void __noreturn ap_romstage_main(unsigned long bist) +{ + struct sysinfo romstage_state; + struct sysinfo *cb = &romstage_state; + + /* Enable PCI MMIO configuration. */ + amd_initmmio(); + + fill_sysinfo(cb); + + /* Halt if there was a built in self test failure */ + report_bist_failure(bist); + + agesa_execute_state(cb, AMD_INIT_RESET); + + agesa_execute_state(cb, AMD_INIT_EARLY); + + /* Not reached. */ + halt(); +} + +asmlinkage void romstage_main(unsigned long bist) +{ + if (boot_cpu()) + bsp_romstage_main(bist); + else + ap_romstage_main(bist); } diff --git a/src/include/cpu/amd/car.h b/src/include/cpu/amd/car.h index be7b69a942..7e2fccd80f 100644 --- a/src/include/cpu/amd/car.h +++ b/src/include/cpu/amd/car.h @@ -3,6 +3,6 @@ #include -void *asmlinkage romstage_main(unsigned long bist); +asmlinkage void romstage_main(unsigned long bist); #endif From 9b71804e4fda9bcb067bb06f7d5d5c3f76922327 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ky=C3=B6sti=20M=C3=A4lkki?= Date: Fri, 29 Nov 2019 00:52:01 +0200 Subject: [PATCH 0466/1242] AGESA,binaryPI: Remove BIST reporting in romstage MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit For easier C environment bootblock transition by using already existing prototypes, BIST will not be passed to romstage. It is expected that bootblock will have equivalent code. Change-Id: I0f8e3657ac79277cd77c397d1b3e931e33a6f5db Signed-off-by: Kyösti Mälkki Reviewed-on: https://review.coreboot.org/c/coreboot/+/37348 Reviewed-by: Angel Pons Reviewed-by: Arthur Heymans Reviewed-by: Michał Żygowski Tested-by: build bot (Jenkins) --- src/drivers/amd/agesa/romstage.c | 15 ++++----------- 1 file changed, 4 insertions(+), 11 deletions(-) diff --git a/src/drivers/amd/agesa/romstage.c b/src/drivers/amd/agesa/romstage.c index f9a8c9705a..8460035de4 100644 --- a/src/drivers/amd/agesa/romstage.c +++ b/src/drivers/amd/agesa/romstage.c @@ -16,7 +16,6 @@ #include #include #include -#include #include #include #include @@ -40,7 +39,7 @@ static void fill_sysinfo(struct sysinfo *cb) agesa_set_interface(cb); } -static void bsp_romstage_main(unsigned long bist) +static void bsp_romstage_main(void) { struct postcar_frame pcf; struct sysinfo romstage_state; @@ -66,9 +65,6 @@ static void bsp_romstage_main(unsigned long bist) printk(BIOS_DEBUG, "APIC %02d: CPU Family_Model = %08x\n", initial_apic_id, cpuid_eax(1)); - /* Halt if there was a built in self test failure */ - report_bist_failure(bist); - agesa_execute_state(cb, AMD_INIT_RESET); agesa_execute_state(cb, AMD_INIT_EARLY); @@ -103,7 +99,7 @@ static void bsp_romstage_main(unsigned long bist) /* We do not return. */ } -static void __noreturn ap_romstage_main(unsigned long bist) +static void __noreturn ap_romstage_main(void) { struct sysinfo romstage_state; struct sysinfo *cb = &romstage_state; @@ -113,9 +109,6 @@ static void __noreturn ap_romstage_main(unsigned long bist) fill_sysinfo(cb); - /* Halt if there was a built in self test failure */ - report_bist_failure(bist); - agesa_execute_state(cb, AMD_INIT_RESET); agesa_execute_state(cb, AMD_INIT_EARLY); @@ -127,7 +120,7 @@ static void __noreturn ap_romstage_main(unsigned long bist) asmlinkage void romstage_main(unsigned long bist) { if (boot_cpu()) - bsp_romstage_main(bist); + bsp_romstage_main(); else - ap_romstage_main(bist); + ap_romstage_main(); } From c57494722319274710533b99692e29510b5cf5ba Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Micha=C5=82=20=C5=BBygowski?= Date: Sun, 24 Nov 2019 16:32:05 +0100 Subject: [PATCH 0467/1242] AGESA,binaryPI: Remove redundant SSE enable MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Change-Id: Ib3bf731b74cb20e886d3ecd483b37b1e3fc64ebf Signed-off-by: Michał Żygowski Signed-off-by: Kyösti Mälkki Reviewed-on: https://review.coreboot.org/c/coreboot/+/37349 Reviewed-by: Angel Pons Reviewed-by: Arthur Heymans Tested-by: build bot (Jenkins) --- src/drivers/amd/agesa/cache_as_ram.S | 10 ---------- 1 file changed, 10 deletions(-) diff --git a/src/drivers/amd/agesa/cache_as_ram.S b/src/drivers/amd/agesa/cache_as_ram.S index e3e5735c3b..e429bba966 100644 --- a/src/drivers/amd/agesa/cache_as_ram.S +++ b/src/drivers/amd/agesa/cache_as_ram.S @@ -22,7 +22,6 @@ */ #include "gcccar.inc" -#include #include .code32 @@ -35,15 +34,6 @@ _cache_as_ram_setup: post_code(0xa0) - /* enable SSE2 128bit instructions */ - /* Turn on OSFXSR [BIT9] and OSXMMEXCPT [BIT10] onto CR4 register */ - - movl %cr4, %eax - orl $(3 << 9), %eax - movl %eax, %cr4 - - post_code(0xa1) - AMD_ENABLE_STACK /* Align the stack. */ From 2fa1cb15de4b03155277ae96c389753690a5e517 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Micha=C5=82=20=C5=BBygowski?= Date: Sun, 24 Nov 2019 16:32:05 +0100 Subject: [PATCH 0468/1242] AGESA,binaryPI: Remove __x86_64__ long mode in CAR MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Change-Id: I83a8b2325b751feeb046ce74fabd37aeb27c28dc Signed-off-by: Michał Żygowski Signed-off-by: Kyösti Mälkki Reviewed-on: https://review.coreboot.org/c/coreboot/+/37350 Reviewed-by: Patrick Rudolph Reviewed-by: Angel Pons Tested-by: build bot (Jenkins) --- src/drivers/amd/agesa/cache_as_ram.S | 45 ---------------------------- 1 file changed, 45 deletions(-) diff --git a/src/drivers/amd/agesa/cache_as_ram.S b/src/drivers/amd/agesa/cache_as_ram.S index e429bba966..4f1cbea574 100644 --- a/src/drivers/amd/agesa/cache_as_ram.S +++ b/src/drivers/amd/agesa/cache_as_ram.S @@ -39,51 +39,6 @@ _cache_as_ram_setup: /* Align the stack. */ and $0xFFFFFFF0, %esp -#ifdef __x86_64__ - /* switch to 64 bit long mode */ - mov %esi, %ecx - add $0, %ecx # core number - xor %eax, %eax - lea (0x1000+0x23)(%ecx), %edi - mov %edi, (%ecx) - mov %eax, 4(%ecx) - - lea 0x1000(%ecx), %edi - movl $0x000000e3, 0x00(%edi) - movl %eax, 0x04(%edi) - movl $0x400000e3, 0x08(%edi) - movl %eax, 0x0c(%edi) - movl $0x800000e3, 0x10(%edi) - movl %eax, 0x14(%edi) - movl $0xc00000e3, 0x18(%edi) - movl %eax, 0x1c(%edi) - - # load ROM based identity mapped page tables - mov %ecx, %eax - mov %eax, %cr3 - - # enable PAE - mov %cr4, %eax - bts $5, %eax - mov %eax, %cr4 - - # enable long mode - mov $0xC0000080, %ecx - rdmsr - bts $8, %eax - wrmsr - - # enable paging - mov %cr0, %eax - bts $31, %eax - mov %eax, %cr0 - - # use call far to switch to 64-bit code segment - ljmp $0x18, $1f -1: - -#endif - /* Must maintain 16-byte stack alignment here. */ pushl $0x0 pushl $0x0 From 3aa17f76044f92dd772cd2833fa8f30031e17f35 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Micha=C5=82=20=C5=BBygowski?= Date: Sun, 24 Nov 2019 16:32:05 +0100 Subject: [PATCH 0469/1242] AGESA,binaryPI: Fix stack location on entry to romstage MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit For BSP CPU, set up stack location to match the symbol from car.ld. For AP CPUs the stack is located outside _car_region and is currently not accounted for in the linker scripts. Change-Id: I0ec84ae4e73ecca5034f799cdc2a5c1056ad8b74 Signed-off-by: Michał Żygowski Signed-off-by: Kyösti Mälkki Reviewed-on: https://review.coreboot.org/c/coreboot/+/37351 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi --- src/drivers/amd/agesa/cache_as_ram.S | 26 ++++++++++++++++++++++++-- src/drivers/amd/agesa/romstage.c | 12 ++---------- src/include/cpu/amd/car.h | 1 + 3 files changed, 27 insertions(+), 12 deletions(-) diff --git a/src/drivers/amd/agesa/cache_as_ram.S b/src/drivers/amd/agesa/cache_as_ram.S index 4f1cbea574..e86830f5f7 100644 --- a/src/drivers/amd/agesa/cache_as_ram.S +++ b/src/drivers/amd/agesa/cache_as_ram.S @@ -22,6 +22,7 @@ */ #include "gcccar.inc" +#include #include .code32 @@ -36,6 +37,19 @@ _cache_as_ram_setup: AMD_ENABLE_STACK + /* + * Set up bootblock stack on BSP. + * AMD_ENABLE_STACK macro sets up a stack for BSP at BSP_STACK_BASE_ADDR + * which is 0x30000 (_car_region_end), but for C bootblock the stack + * begins at _ecar_stack (see arch/x86/car.ld) + */ + mov $LAPIC_BASE_MSR, %ecx + rdmsr + test $LAPIC_BASE_MSR_BOOTSTRAP_PROCESSOR, %eax + jz ap_entry + + mov $_ecar_stack, %esp + /* Align the stack. */ and $0xFFFFFFF0, %esp @@ -47,11 +61,19 @@ _cache_as_ram_setup: pushl %eax call romstage_main - /* Should never see this postcode */ - post_code(0xae) + /* Never reached. */ stop: + post_code(POST_DEAD_CODE) hlt jmp stop +ap_entry: + /* Align the stack for call to ap_romstage_main() */ + and $0xfffffff0, %esp + call ap_romstage_main + + /* Never reached. */ + jmp stop + _cache_as_ram_setup_end: diff --git a/src/drivers/amd/agesa/romstage.c b/src/drivers/amd/agesa/romstage.c index 8460035de4..571397fdb3 100644 --- a/src/drivers/amd/agesa/romstage.c +++ b/src/drivers/amd/agesa/romstage.c @@ -39,7 +39,7 @@ static void fill_sysinfo(struct sysinfo *cb) agesa_set_interface(cb); } -static void bsp_romstage_main(void) +asmlinkage void romstage_main(unsigned long bist) { struct postcar_frame pcf; struct sysinfo romstage_state; @@ -99,7 +99,7 @@ static void bsp_romstage_main(void) /* We do not return. */ } -static void __noreturn ap_romstage_main(void) +asmlinkage void ap_romstage_main(void) { struct sysinfo romstage_state; struct sysinfo *cb = &romstage_state; @@ -116,11 +116,3 @@ static void __noreturn ap_romstage_main(void) /* Not reached. */ halt(); } - -asmlinkage void romstage_main(unsigned long bist) -{ - if (boot_cpu()) - bsp_romstage_main(); - else - ap_romstage_main(); -} diff --git a/src/include/cpu/amd/car.h b/src/include/cpu/amd/car.h index 7e2fccd80f..f57ea82ad0 100644 --- a/src/include/cpu/amd/car.h +++ b/src/include/cpu/amd/car.h @@ -4,5 +4,6 @@ #include asmlinkage void romstage_main(unsigned long bist); +asmlinkage void ap_romstage_main(void); #endif From 33d0fb8d346512e1b6819fa70cb17212ea014336 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ky=C3=B6sti=20M=C3=A4lkki?= Date: Fri, 29 Nov 2019 06:38:46 +0200 Subject: [PATCH 0470/1242] AGESA,binaryPI: Add compatibility wrapper for romstage entry MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This simplifies transition and reviews towards C environment bootblock by allowing single cache_as_ram.S file to be used. Change-Id: I231972982e5ca6d0c08437693edf926b0eaf9ee1 Signed-off-by: Kyösti Mälkki Reviewed-on: https://review.coreboot.org/c/coreboot/+/37352 Reviewed-by: Angel Pons Reviewed-by: Michał Żygowski Tested-by: build bot (Jenkins) --- src/drivers/amd/agesa/cache_as_ram.S | 25 +++++++++++-------------- src/drivers/amd/agesa/romstage.c | 19 ++++++++++++++++--- src/include/bootblock_common.h | 3 +++ src/include/cpu/amd/car.h | 9 --------- 4 files changed, 30 insertions(+), 26 deletions(-) delete mode 100644 src/include/cpu/amd/car.h diff --git a/src/drivers/amd/agesa/cache_as_ram.S b/src/drivers/amd/agesa/cache_as_ram.S index e86830f5f7..4417e64595 100644 --- a/src/drivers/amd/agesa/cache_as_ram.S +++ b/src/drivers/amd/agesa/cache_as_ram.S @@ -30,9 +30,6 @@ _cache_as_ram_setup: - /* Preserve BIST. */ - movd %eax, %mm0 - post_code(0xa0) AMD_ENABLE_STACK @@ -50,16 +47,16 @@ _cache_as_ram_setup: mov $_ecar_stack, %esp - /* Align the stack. */ - and $0xFFFFFFF0, %esp + /* Align the stack and keep aligned for call to bootblock_c_entry() */ + and $0xfffffff0, %esp + sub $8, %esp - /* Must maintain 16-byte stack alignment here. */ - pushl $0x0 - pushl $0x0 - pushl $0x0 - movd %mm0, %eax /* bist */ - pushl %eax - call romstage_main + pushl $0 /* tsc[63:32] */ + pushl $0 /* tsc[31:0] */ + + post_code(0xa2) + + call bootblock_c_entry /* Never reached. */ @@ -69,9 +66,9 @@ stop: jmp stop ap_entry: - /* Align the stack for call to ap_romstage_main() */ + /* Align the stack for call to ap_bootblock_c_entry() */ and $0xfffffff0, %esp - call ap_romstage_main + call ap_bootblock_c_entry /* Never reached. */ jmp stop diff --git a/src/drivers/amd/agesa/romstage.c b/src/drivers/amd/agesa/romstage.c index 571397fdb3..48a81c57df 100644 --- a/src/drivers/amd/agesa/romstage.c +++ b/src/drivers/amd/agesa/romstage.c @@ -14,8 +14,8 @@ #include #include #include +#include #include -#include #include #include #include @@ -39,7 +39,7 @@ static void fill_sysinfo(struct sysinfo *cb) agesa_set_interface(cb); } -asmlinkage void romstage_main(unsigned long bist) +static void romstage_main(void) { struct postcar_frame pcf; struct sysinfo romstage_state; @@ -99,7 +99,7 @@ asmlinkage void romstage_main(unsigned long bist) /* We do not return. */ } -asmlinkage void ap_romstage_main(void) +static void ap_romstage_main(void) { struct sysinfo romstage_state; struct sysinfo *cb = &romstage_state; @@ -116,3 +116,16 @@ asmlinkage void ap_romstage_main(void) /* Not reached. */ halt(); } + +/* This wrapper enables easy transition away from ROMCC_BOOTBLOCK + * keeping changes in cache_as_ram.S easy to manage. + */ +asmlinkage void bootblock_c_entry(uint64_t base_timestamp) +{ + romstage_main(); +} + +asmlinkage void ap_bootblock_c_entry(void) +{ + ap_romstage_main(); +} diff --git a/src/include/bootblock_common.h b/src/include/bootblock_common.h index 1081f27453..eb9c24c75d 100644 --- a/src/include/bootblock_common.h +++ b/src/include/bootblock_common.h @@ -38,6 +38,9 @@ void bootblock_soc_init(void); asmlinkage void bootblock_c_entry(uint64_t base_timestamp); asmlinkage void bootblock_c_entry_bist(uint64_t base_timestamp, uint32_t bist); +/* To be used when APs execute through bootblock too. */ +asmlinkage void ap_bootblock_c_entry(void); + void bootblock_main_with_basetime(uint64_t base_timestamp); /* This is the argument structure passed from decompressor to bootblock. */ diff --git a/src/include/cpu/amd/car.h b/src/include/cpu/amd/car.h deleted file mode 100644 index f57ea82ad0..0000000000 --- a/src/include/cpu/amd/car.h +++ /dev/null @@ -1,9 +0,0 @@ -#ifndef _CPU_AMD_CAR_H -#define _CPU_AMD_CAR_H - -#include - -asmlinkage void romstage_main(unsigned long bist); -asmlinkage void ap_romstage_main(void); - -#endif From 2c2df5b6ddd1eb568b2384ec34dac6f721ee427e Mon Sep 17 00:00:00 2001 From: Patrick Georgi Date: Fri, 29 Nov 2019 10:41:40 +0100 Subject: [PATCH 0471/1242] src/drivers: Fix two issues discovered by checkpatch Change-Id: I46e318333e68b999b2889f51fa2fbf140a27a54e Signed-off-by: Patrick Georgi Reviewed-on: https://review.coreboot.org/c/coreboot/+/37357 Tested-by: build bot (Jenkins) Reviewed-by: HAOUAS Elyes Reviewed-by: Paul Menzel Reviewed-by: Angel Pons --- src/drivers/spi/tpm/tis.c | 2 +- src/drivers/usb/ehci_debug.c | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/src/drivers/spi/tpm/tis.c b/src/drivers/spi/tpm/tis.c index 7d42b7c424..6230751fb1 100644 --- a/src/drivers/spi/tpm/tis.c +++ b/src/drivers/spi/tpm/tis.c @@ -9,7 +9,7 @@ #include "tpm.h" -static unsigned tpm_is_open; +static unsigned int tpm_is_open; static const struct { uint16_t vid; diff --git a/src/drivers/usb/ehci_debug.c b/src/drivers/usb/ehci_debug.c index e77cd85f75..d6b468c3a2 100644 --- a/src/drivers/usb/ehci_debug.c +++ b/src/drivers/usb/ehci_debug.c @@ -59,7 +59,7 @@ static int dbgp_enabled(void); static void dbgp_print_data(struct ehci_dbg_port *ehci_debug); static struct ehci_debug_info glob_dbg_info; -static struct ehci_debug_info * glob_dbg_info_p; +static struct ehci_debug_info *glob_dbg_info_p; static inline struct ehci_debug_info *dbgp_ehci_info(void) { From 3802563bdcaa850b9db9afe48469af80ce24e652 Mon Sep 17 00:00:00 2001 From: Patrick Georgi Date: Fri, 29 Nov 2019 12:07:41 +0100 Subject: [PATCH 0472/1242] cpu/x86/tsc: Remove indirection when accessing mono_timer_g MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Change-Id: Ice1426cec8f9c5d9644836b0cf025be50e932f48 Signed-off-by: Patrick Georgi Reviewed-on: https://review.coreboot.org/c/coreboot/+/37359 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki Reviewed-by: Angel Pons --- src/cpu/x86/tsc/delay_tsc.c | 21 +++++++-------------- 1 file changed, 7 insertions(+), 14 deletions(-) diff --git a/src/cpu/x86/tsc/delay_tsc.c b/src/cpu/x86/tsc/delay_tsc.c index fe6ae5b78e..fda8fe1b20 100644 --- a/src/cpu/x86/tsc/delay_tsc.c +++ b/src/cpu/x86/tsc/delay_tsc.c @@ -50,27 +50,20 @@ static struct monotonic_counter { uint64_t last_value; } mono_counter_g; -static inline struct monotonic_counter *get_monotonic_context(void) -{ - return &mono_counter_g; -} - void timer_monotonic_get(struct mono_time *mt) { uint64_t current_tick; uint64_t ticks_elapsed; unsigned long ticks_per_usec; - struct monotonic_counter *mono_counter; - mono_counter = get_monotonic_context(); - if (!mono_counter->initialized) { + if (!mono_counter_g.initialized) { init_timer(); - mono_counter->last_value = rdtscll(); - mono_counter->initialized = 1; + mono_counter_g.last_value = rdtscll(); + mono_counter_g.initialized = 1; } current_tick = rdtscll(); - ticks_elapsed = current_tick - mono_counter->last_value; + ticks_elapsed = current_tick - mono_counter_g.last_value; ticks_per_usec = tsc_freq_mhz(); /* Update current time and tick values only if a full tick occurred. */ @@ -78,11 +71,11 @@ void timer_monotonic_get(struct mono_time *mt) uint64_t usecs_elapsed; usecs_elapsed = ticks_elapsed / ticks_per_usec; - mono_time_add_usecs(&mono_counter->time, (long)usecs_elapsed); - mono_counter->last_value = current_tick; + mono_time_add_usecs(&mono_counter_g.time, (long)usecs_elapsed); + mono_counter_g.last_value = current_tick; } /* Save result. */ - *mt = mono_counter->time; + *mt = mono_counter_g.time; } #endif From c0a4e2088720d65cd073440f14305090c8b7d6fb Mon Sep 17 00:00:00 2001 From: Arthur Heymans Date: Wed, 20 Nov 2019 20:06:41 +0100 Subject: [PATCH 0473/1242] lib/cbmem_console.c: Drop CAR_GLOBAL_MIGRATION support MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Change-Id: I5c970a07c7114bff81f0048cac8eafaec35a2386 Signed-off-by: Arthur Heymans Reviewed-on: https://review.coreboot.org/c/coreboot/+/37035 Reviewed-by: Kyösti Mälkki Tested-by: build bot (Jenkins) --- src/lib/cbmem_console.c | 43 +++++++++++++++-------------------------- 1 file changed, 16 insertions(+), 27 deletions(-) diff --git a/src/lib/cbmem_console.c b/src/lib/cbmem_console.c index 7876ff510a..7bd247d55b 100644 --- a/src/lib/cbmem_console.c +++ b/src/lib/cbmem_console.c @@ -16,7 +16,6 @@ #include #include #include -#include #include /* @@ -49,7 +48,7 @@ struct cbmem_console { _Static_assert(CONFIG_CONSOLE_CBMEM_BUFFER_SIZE <= MAX_SIZE, "cbmem_console format cannot support buffers larger than 256MB!"); -static struct cbmem_console *cbmem_console_p CAR_GLOBAL; +static struct cbmem_console *cbmem_console_p; /* * While running from ROM, before DRAM is initialized, some area in cache as @@ -65,14 +64,9 @@ static struct cbmem_console *cbmem_console_p CAR_GLOBAL; #define STATIC_CONSOLE_SIZE 1024 static u8 static_console[STATIC_CONSOLE_SIZE]; -static struct cbmem_console *current_console(void) -{ - return car_get_ptr(cbmem_console_p); -} - static void current_console_set(struct cbmem_console *new_console_p) { - car_set_ptr(cbmem_console_p, new_console_p); + cbmem_console_p = new_console_p; } static int buffer_valid(struct cbmem_console *cbm_cons_p, u32 total_space) @@ -112,21 +106,19 @@ void cbmemc_init(void) void cbmemc_tx_byte(unsigned char data) { - struct cbmem_console *cbm_cons_p = current_console(); - - if (!cbm_cons_p || !cbm_cons_p->size) + if (!cbmem_console_p || !cbmem_console_p->size) return; - u32 flags = cbm_cons_p->cursor & ~CURSOR_MASK; - u32 cursor = cbm_cons_p->cursor & CURSOR_MASK; + u32 flags = cbmem_console_p->cursor & ~CURSOR_MASK; + u32 cursor = cbmem_console_p->cursor & CURSOR_MASK; - cbm_cons_p->body[cursor++] = data; - if (cursor >= cbm_cons_p->size) { + cbmem_console_p->body[cursor++] = data; + if (cursor >= cbmem_console_p->size) { cursor = 0; flags |= OVERFLOW; } - cbm_cons_p->cursor = flags | cursor; + cbmem_console_p->cursor = flags | cursor; } /* @@ -166,7 +158,7 @@ static void cbmemc_reinit(int is_recovery) const size_t size = CONFIG_CONSOLE_CBMEM_BUFFER_SIZE; /* If CBMEM entry already existed, old contents are not altered. */ struct cbmem_console *cbmem_cons_p = cbmem_add(CBMEM_ID_CONSOLE, size); - struct cbmem_console *previous_cons_p = current_console(); + struct cbmem_console *previous_cons_p = cbmem_console_p; init_console_ptr(cbmem_cons_p, size); copy_console_buffer(previous_cons_p); @@ -178,19 +170,16 @@ POSTCAR_CBMEM_INIT_HOOK(cbmemc_reinit) #if CONFIG(CONSOLE_CBMEM_DUMP_TO_UART) void cbmem_dump_console(void) { - struct cbmem_console *cbm_cons_p; u32 cursor; - - cbm_cons_p = current_console(); - if (!cbm_cons_p) + if (!cbmem_console_p) return; uart_init(0); - if (cbm_cons_p->cursor & OVERFLOW) - for (cursor = cbm_cons_p->cursor & CURSOR_MASK; - cursor < cbm_cons_p->size; cursor++) - uart_tx_byte(0, cbm_cons_p->body[cursor]); - for (cursor = 0; cursor < (cbm_cons_p->cursor & CURSOR_MASK); cursor++) - uart_tx_byte(0, cbm_cons_p->body[cursor]); + if (cbmem_console_p->cursor & OVERFLOW) + for (cursor = cbmem_console_p->cursor & CURSOR_MASK; + cursor < cbmem_console_p->size; cursor++) + uart_tx_byte(0, cbmem_console_p->body[cursor]); + for (cursor = 0; cursor < (cbmem_console_p->cursor & CURSOR_MASK); cursor++) + uart_tx_byte(0, cbmem_console_p->body[cursor]); } #endif From 6ea3a13a17c0c9021fe871feada360ab55ceb6bf Mon Sep 17 00:00:00 2001 From: Arthur Heymans Date: Wed, 20 Nov 2019 21:50:54 +0100 Subject: [PATCH 0474/1242] drivers/spi/flashconsole.c: Drop CAR_GLOBAL_MIGRATION support MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Change-Id: I81a610a6d119745f2fc637629b8ba7ade76503bc Signed-off-by: Arthur Heymans Reviewed-on: https://review.coreboot.org/c/coreboot/+/37043 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki Reviewed-by: Angel Pons --- src/drivers/spi/flashconsole.c | 74 ++++++++++++++-------------------- 1 file changed, 31 insertions(+), 43 deletions(-) diff --git a/src/drivers/spi/flashconsole.c b/src/drivers/spi/flashconsole.c index 8874812449..c56bf52d92 100644 --- a/src/drivers/spi/flashconsole.c +++ b/src/drivers/spi/flashconsole.c @@ -11,7 +11,6 @@ * GNU General Public License for more details. */ -#include #include #include #include @@ -23,26 +22,25 @@ #define LINE_BUFFER_SIZE 128 #define READ_BUFFER_SIZE 0x100 -static const struct region_device *g_rdev_ptr CAR_GLOBAL; -static struct region_device g_rdev CAR_GLOBAL; -static uint8_t g_line_buffer[LINE_BUFFER_SIZE] CAR_GLOBAL; -static size_t g_offset CAR_GLOBAL; -static size_t g_line_offset CAR_GLOBAL; +static const struct region_device *g_rdev_ptr; +static struct region_device g_rdev; +static uint8_t g_line_buffer[LINE_BUFFER_SIZE]; +static size_t g_offset; +static size_t g_line_offset; void flashconsole_init(void) { - struct region_device *rdev = car_get_var_ptr(&g_rdev); uint8_t buffer[READ_BUFFER_SIZE]; size_t size; size_t offset = 0; size_t len = READ_BUFFER_SIZE; size_t i; - if (fmap_locate_area_as_rdev_rw("CONSOLE", rdev)) { + if (fmap_locate_area_as_rdev_rw("CONSOLE", &g_rdev)) { printk(BIOS_INFO, "Can't find 'CONSOLE' area in FMAP\n"); return; } - size = region_device_sz(rdev); + size = region_device_sz(&g_rdev); /* * We need to check the region until we find a 0xff indicating @@ -58,7 +56,7 @@ void flashconsole_init(void) // Fill the buffer on first iteration if (i == 0) { len = min(READ_BUFFER_SIZE, size - offset); - if (rdev_readat(rdev, buffer, offset, len) != len) + if (rdev_readat(&g_rdev, buffer, offset, len) != len) return; } if (buffer[i] == 0xff) { @@ -77,65 +75,55 @@ void flashconsole_init(void) return; } - car_set_var(g_offset, offset); - /* Set g_rdev_ptr last so tx_byte doesn't get executed early */ - car_set_var(g_rdev_ptr, rdev); + g_offset = offset; + g_rdev_ptr = &g_rdev; } void flashconsole_tx_byte(unsigned char c) { - const struct region_device *rdev = car_get_var(g_rdev_ptr); - uint8_t *line_buffer; - size_t offset; - size_t len; - size_t region_size; - - if (!rdev) + if (!g_rdev_ptr) return; - line_buffer = car_get_var_ptr(g_line_buffer); - offset = car_get_var(g_offset); - len = car_get_var(g_line_offset); - region_size = region_device_sz(rdev); + size_t region_size = region_device_sz(g_rdev_ptr); - line_buffer[len++] = c; - car_set_var(g_line_offset, len); + g_line_buffer[g_line_offset++] = c; - if (len >= LINE_BUFFER_SIZE || - offset + len >= region_size || c == '\n') { + if (g_line_offset >= LINE_BUFFER_SIZE || + g_offset + g_line_offset >= region_size || c == '\n') { flashconsole_tx_flush(); } } void flashconsole_tx_flush(void) { - const struct region_device *rdev = car_get_var(g_rdev_ptr); - uint8_t *line_buffer = car_get_var_ptr(g_line_buffer); - size_t offset = car_get_var(g_offset); - size_t len = car_get_var(g_line_offset); + size_t offset = g_offset; + size_t len = g_line_offset; size_t region_size; - - if (!rdev) - return; + static int busy; /* Prevent any recursive loops in case the spi flash driver * calls printk (in case of transaction timeout or * any other error while writing) */ - car_set_var(g_rdev_ptr, NULL); + if (busy) + return; - region_size = region_device_sz(rdev); + if (!g_rdev_ptr) + return; + + busy = 1; + region_size = region_device_sz(g_rdev_ptr); if (offset + len >= region_size) len = region_size - offset; - if (rdev_writeat(rdev, line_buffer, offset, len) != len) - rdev = NULL; + if (rdev_writeat(&g_rdev, g_line_buffer, offset, len) != len) + return; // If the region is full, stop future write attempts if (offset + len >= region_size) - rdev = NULL; + return; - car_set_var(g_offset, offset + len); - car_set_var(g_line_offset, 0); + g_offset = offset + len; + g_line_offset = 0; - car_set_var(g_rdev_ptr, rdev); + busy = 0; } From 706251d91375241630a4e753512ebeefad56c2bc Mon Sep 17 00:00:00 2001 From: Arthur Heymans Date: Wed, 20 Nov 2019 22:50:33 +0100 Subject: [PATCH 0475/1242] arch/x86/cache.h: Use ENV_CACHE_AS_RAM macro Change-Id: Ic7b088a04165bb24b9ebcebc1580a96ce0fdfcc8 Signed-off-by: Arthur Heymans Reviewed-on: https://review.coreboot.org/c/coreboot/+/37063 Tested-by: build bot (Jenkins) Reviewed-by: Angel Pons --- src/arch/x86/include/arch/cache.h | 5 ++--- src/arch/x86/include/arch/early_variables.h | 8 -------- src/cpu/x86/car.c | 5 ----- 3 files changed, 2 insertions(+), 16 deletions(-) diff --git a/src/arch/x86/include/arch/cache.h b/src/arch/x86/include/arch/cache.h index c0d50e650d..36476fd0ab 100644 --- a/src/arch/x86/include/arch/cache.h +++ b/src/arch/x86/include/arch/cache.h @@ -31,13 +31,12 @@ #ifndef ARCH_CACHE_H #define ARCH_CACHE_H -#include #include /* Executing WBINVD when running out of CAR would not be good, prevent that. */ static inline void dcache_clean_invalidate_all(void) { - if (!car_active()) + if (!ENV_CACHE_AS_RAM) wbinvd(); } static inline void dcache_clean_all(void) @@ -47,7 +46,7 @@ static inline void dcache_clean_all(void) } static inline void dcache_invalidate_all(void) { - if (!car_active()) + if (!ENV_CACHE_AS_RAM) invd(); } diff --git a/src/arch/x86/include/arch/early_variables.h b/src/arch/x86/include/arch/early_variables.h index 7393cc94e0..0c4c37b7c9 100644 --- a/src/arch/x86/include/arch/early_variables.h +++ b/src/arch/x86/include/arch/early_variables.h @@ -40,9 +40,6 @@ asm(".previous"); /* Get the correct pointer for the CAR global variable. */ void *car_get_var_ptr(void *var); -/* Return 1 when currently running with globals in Cache-as-RAM, 0 otherwise. */ -int car_active(void); - /* Get and set a primitive type global variable. */ #define car_get_var(var) \ (*(typeof(var) *)car_get_var_ptr(&(var))) @@ -81,11 +78,6 @@ static inline void *car_get_var_ptr(void *var) return var; } -static inline int car_active(void) -{ - return ENV_CACHE_AS_RAM; -} - #endif #endif /* ARCH_EARLY_VARIABLES_H */ diff --git a/src/cpu/x86/car.c b/src/cpu/x86/car.c index b2dcdc85a3..ef645fc1db 100644 --- a/src/cpu/x86/car.c +++ b/src/cpu/x86/car.c @@ -65,11 +65,6 @@ void *car_get_var_ptr(void *var) return &migrated_base[offset]; } -int car_active(void) -{ - return !car_migrated; -} - static void do_car_migrate_variables(void) { void *migrated_base; From 1b8df77ac10769abfe5a028ee0b62a23a1ea5db2 Mon Sep 17 00:00:00 2001 From: Arthur Heymans Date: Wed, 20 Nov 2019 22:22:36 +0100 Subject: [PATCH 0476/1242] arch/*/*/early_variables.h: drop unused files MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Kill off NO_GLOBAL_MIGRATION finally! Change-Id: Ieb7d9f5590b3a7dd1fd5c0ce2e51337332434dbd Signed-off-by: Arthur Heymans Reviewed-on: https://review.coreboot.org/c/coreboot/+/37054 Reviewed-by: Kyösti Mälkki Reviewed-by: Patrick Georgi Tested-by: build bot (Jenkins) --- src/arch/arm/include/arch/early_variables.h | 26 ----- src/arch/arm64/include/arch/early_variables.h | 26 ----- src/arch/ppc64/include/arch/early_variables.h | 27 ------ src/arch/riscv/include/arch/early_variables.h | 29 ------ src/arch/x86/include/arch/early_variables.h | 83 ---------------- src/cpu/x86/Makefile.inc | 2 - src/cpu/x86/car.c | 94 ------------------- 7 files changed, 287 deletions(-) delete mode 100644 src/arch/arm/include/arch/early_variables.h delete mode 100644 src/arch/arm64/include/arch/early_variables.h delete mode 100644 src/arch/ppc64/include/arch/early_variables.h delete mode 100644 src/arch/riscv/include/arch/early_variables.h delete mode 100644 src/arch/x86/include/arch/early_variables.h delete mode 100644 src/cpu/x86/car.c diff --git a/src/arch/arm/include/arch/early_variables.h b/src/arch/arm/include/arch/early_variables.h deleted file mode 100644 index 7002a8805e..0000000000 --- a/src/arch/arm/include/arch/early_variables.h +++ /dev/null @@ -1,26 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef ARCH_EARLY_VARIABLES_H -#define ARCH_EARLY_VARIABLES_H - -#define CAR_GLOBAL - -static inline void *car_get_var_ptr(void *var) { return var; } -#define car_get_var(var) (var) -#define car_set_var(var, val) do { (var) = (val); } while (0) - -#define car_get_ptr car_get_var -#define car_set_ptr car_set_var - -#endif diff --git a/src/arch/arm64/include/arch/early_variables.h b/src/arch/arm64/include/arch/early_variables.h deleted file mode 100644 index 7002a8805e..0000000000 --- a/src/arch/arm64/include/arch/early_variables.h +++ /dev/null @@ -1,26 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef ARCH_EARLY_VARIABLES_H -#define ARCH_EARLY_VARIABLES_H - -#define CAR_GLOBAL - -static inline void *car_get_var_ptr(void *var) { return var; } -#define car_get_var(var) (var) -#define car_set_var(var, val) do { (var) = (val); } while (0) - -#define car_get_ptr car_get_var -#define car_set_ptr car_set_var - -#endif diff --git a/src/arch/ppc64/include/arch/early_variables.h b/src/arch/ppc64/include/arch/early_variables.h deleted file mode 100644 index 05b8bc7e48..0000000000 --- a/src/arch/ppc64/include/arch/early_variables.h +++ /dev/null @@ -1,27 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef ARCH_EARLY_VARIABLES_H -#define ARCH_EARLY_VARIABLES_H - -#define CAR_GLOBAL - -#define CAR_MIGRATE(migrate_fn_) -static inline void *car_get_var_ptr(void *var) { return var; } -#define car_get_var(var) (var) -#define car_set_var(var, val) do { (var) = (val); } while (0) - -#define car_get_ptr car_get_var -#define car_set_ptr car_set_var - -#endif diff --git a/src/arch/riscv/include/arch/early_variables.h b/src/arch/riscv/include/arch/early_variables.h deleted file mode 100644 index a2da5f86ee..0000000000 --- a/src/arch/riscv/include/arch/early_variables.h +++ /dev/null @@ -1,29 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 The ChromiumOS Authors. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef ARCH_EARLY_VARIABLES_H -#define ARCH_EARLY_VARIABLES_H - -#define CAR_GLOBAL - -#define CAR_MIGRATE(migrate_fn_) -static inline void *car_get_var_ptr(void *var) { return var; } -#define car_get_var(var) (var) -#define car_set_var(var, val) do { (var) = (val); } while (0) - -#define car_get_ptr car_get_var -#define car_set_ptr car_set_var - -#endif diff --git a/src/arch/x86/include/arch/early_variables.h b/src/arch/x86/include/arch/early_variables.h deleted file mode 100644 index 0c4c37b7c9..0000000000 --- a/src/arch/x86/include/arch/early_variables.h +++ /dev/null @@ -1,83 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef ARCH_EARLY_VARIABLES_H -#define ARCH_EARLY_VARIABLES_H - -#include -#include -#include - -#if ENV_ROMSTAGE && CONFIG(CAR_GLOBAL_MIGRATION) - -/* - * The _car_global_[start|end]symbols cover CAR data which is relocatable - * once memory comes online. Variables with CAR_GLOBAL decoration - * reside within this region. - */ -extern char _car_global_start[]; -extern char _car_global_end[]; -#define _car_global_size (_car_global_end - _car_global_start) - -asm(".section .car.global_data,\"w\",@nobits"); -asm(".previous"); -#ifdef __clang__ -#define CAR_GLOBAL __attribute__((used, section(".car.global_data"))) -#else -#define CAR_GLOBAL __attribute__((used, section(".car.global_data#"))) -#endif /* __clang__ */ - -/* Get the correct pointer for the CAR global variable. */ -void *car_get_var_ptr(void *var); - -/* Get and set a primitive type global variable. */ -#define car_get_var(var) \ - (*(typeof(var) *)car_get_var_ptr(&(var))) -#define car_set_var(var, val) car_get_var(var) = (val) - -/* Get and set a CAR_GLOBAL pointing elsewhere inside CAR. */ -#define car_get_ptr car_get_var -#define car_set_ptr car_set_var - -static inline size_t car_data_size(void) -{ - size_t car_size = _car_global_size; - return ALIGN(car_size, 64); -} - -static inline size_t car_object_offset(void *ptr) -{ - return (char *)ptr - &_car_global_start[0]; -} - -#else - -/* - * For all stages other than romstage, all CAR_GLOBAL variables are accessed - * unconditionally as there is no migration of symbols. - */ - -#define CAR_GLOBAL -#define car_get_var(var) (var) -#define car_set_var(var, val) (var) = (val) -#define car_get_ptr car_get_var -#define car_set_ptr car_set_var - -static inline void *car_get_var_ptr(void *var) -{ - return var; -} - -#endif - -#endif /* ARCH_EARLY_VARIABLES_H */ diff --git a/src/cpu/x86/Makefile.inc b/src/cpu/x86/Makefile.inc index 55d1fad7cb..1191069502 100644 --- a/src/cpu/x86/Makefile.inc +++ b/src/cpu/x86/Makefile.inc @@ -1,5 +1,3 @@ -romstage-$(CONFIG_CAR_GLOBAL_MIGRATION) += car.c - subdirs-y += pae subdirs-$(CONFIG_PARALLEL_MP) += name ramstage-$(CONFIG_PARALLEL_MP) += mp_init.c diff --git a/src/cpu/x86/car.c b/src/cpu/x86/car.c deleted file mode 100644 index ef645fc1db..0000000000 --- a/src/cpu/x86/car.c +++ /dev/null @@ -1,94 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include -#include -#include -#include - -typedef void (* const car_migration_func_t)(void); - -extern car_migration_func_t _car_migrate_start; - -/* - * The car_migrated global variable determines if the cache-as-ram space has - * been migrated to real RAM. It does this by assuming the following things: - * 1. cache-as-ram space is zero'd out once it is set up. - * 2. Either the cache-as-ram space is memory-backed after getting torn down - * or the space returns 0xff's for each byte read. - * Based on these 2 attributes there is the ability to tell when the - * cache-as-ram region has been migrated. - */ -static int car_migrated CAR_GLOBAL; - -/** @brief returns pointer to a CAR variable, before or after migration. - * - * @param var pointer to the CAR variable - */ -void *car_get_var_ptr(void *var) -{ - char *migrated_base = NULL; - int offset; - void *_car_start = _car_global_start; - void *_car_end = _car_global_end; - - /* If the cache-as-ram has not been migrated return the pointer - * passed in. */ - if (!car_migrated) - return var; - - if (var < _car_start || var >= _car_end) { - printk(BIOS_ERR, - "Requesting CAR variable outside of CAR region: %p\n", - var); - return var; - } - - migrated_base = cbmem_find(CBMEM_ID_CAR_GLOBALS); - offset = (char *)var - (char *)_car_start; - - if (migrated_base == NULL) - die("CAR: Could not find migration base!\n"); - - return &migrated_base[offset]; -} - -static void do_car_migrate_variables(void) -{ - void *migrated_base; - size_t car_size = car_data_size(); - - /* Check if already migrated. */ - if (car_migrated) - return; - - migrated_base = cbmem_add(CBMEM_ID_CAR_GLOBALS, car_size); - - if (migrated_base == NULL) { - printk(BIOS_ERR, "Could not migrate CAR data!\n"); - return; - } - - memcpy(migrated_base, _car_global_start, car_size); - - /* Mark that the data has been moved. */ - car_migrated = ~0; -} - -static void car_migrate_variables(int is_recovery) -{ - do_car_migrate_variables(); -} -ROMSTAGE_CBMEM_INIT_HOOK(car_migrate_variables) From fdb8b13e64d233296486ca9a4ca9eb34c0386934 Mon Sep 17 00:00:00 2001 From: Arthur Heymans Date: Thu, 28 Nov 2019 14:00:01 +0100 Subject: [PATCH 0477/1242] arch/x86/car.ld: Drop CAR_GLOBAL region MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Change-Id: Id66fd0528987fb3e464d400cf9ccac98752fb8f5 Signed-off-by: Arthur Heymans Reviewed-on: https://review.coreboot.org/c/coreboot/+/37327 Reviewed-by: Patrick Georgi Reviewed-by: HAOUAS Elyes Reviewed-by: Kyösti Mälkki Tested-by: build bot (Jenkins) --- src/arch/x86/car.ld | 15 +-------------- 1 file changed, 1 insertion(+), 14 deletions(-) diff --git a/src/arch/x86/car.ld b/src/arch/x86/car.ld index 483a908816..d8ff4b36b7 100644 --- a/src/arch/x86/car.ld +++ b/src/arch/x86/car.ld @@ -71,7 +71,7 @@ /* _bss and _ebss provide symbols to per-stage * variables that are not shared like the timestamp and the pre-ram * cbmem console. This is useful for clearing this area on a per-stage - * basis when more than one stage uses cache-as-ram for CAR_GLOBALs. */ + * basis when more than one stage uses cache-as-ram. */ . = ALIGN(ARCH_POINTER_ALIGN_SIZE); _bss = .; @@ -81,10 +81,6 @@ *(.bss.*) *(.sbss) *(.sbss.*) -#else - _car_global_start = .; - *(.car.global_data); - _car_global_end = .; #endif . = ALIGN(ARCH_POINTER_ALIGN_SIZE); _ebss = .; @@ -106,15 +102,6 @@ .illegal_globals . : { *(EXCLUDE_FILE ("*/libagesa.*.a:" "*/romstage*/buildOpts.o" "*/romstage*/agesawrapper.o" "*/vendorcode/amd/agesa/*" "*/vendorcode/amd/cimx/*") .data) *(EXCLUDE_FILE ("*/libagesa.*.a:" "*/romstage*/buildOpts.o" "*/romstage*/agesawrapper.o" "*/vendorcode/amd/agesa/*" "*/vendorcode/amd/cimx/*") .data.*) -#if CONFIG(CAR_GLOBAL_MIGRATION) - *(.bss) - *(.bss.*) - *(.sbss) - *(.sbss.*) -#else - /* In case something sneaks through when it shouldn't. */ - *(.car.global_data); -#endif } _bogus = ASSERT((CONFIG_DCACHE_RAM_SIZE == 0) || (SIZEOF(.car.data) <= CONFIG_DCACHE_RAM_SIZE), "Cache as RAM area is too full"); From 8601afb679f9e0af556a4bd19473d9dc5c140895 Mon Sep 17 00:00:00 2001 From: Arthur Heymans Date: Wed, 20 Nov 2019 22:25:30 +0100 Subject: [PATCH 0478/1242] kill CAR_GLOBAL_MIGRATION leftovers MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Change-Id: Ia3b2c10af63cd0cab42dc39f479cb69bc4df9124 Signed-off-by: Arthur Heymans Reviewed-on: https://review.coreboot.org/c/coreboot/+/37055 Reviewed-by: Angel Pons Reviewed-by: HAOUAS Elyes Reviewed-by: Kyösti Mälkki Tested-by: build bot (Jenkins) --- src/arch/x86/Kconfig | 1 - src/console/printk.c | 3 +-- src/cpu/Kconfig | 8 -------- src/include/rules.h | 2 +- 4 files changed, 2 insertions(+), 12 deletions(-) diff --git a/src/arch/x86/Kconfig b/src/arch/x86/Kconfig index a788bc0e23..0e6f486d03 100644 --- a/src/arch/x86/Kconfig +++ b/src/arch/x86/Kconfig @@ -219,7 +219,6 @@ config VERSTAGE_ADDR config POSTCAR_STAGE def_bool y depends on ARCH_X86 - depends on !CAR_GLOBAL_MIGRATION config VERSTAGE_DEBUG_SPINLOOP bool diff --git a/src/console/printk.c b/src/console/printk.c index fd590fa6f7..a08dd2f80f 100644 --- a/src/console/printk.c +++ b/src/console/printk.c @@ -25,8 +25,7 @@ DECLARE_SPIN_LOCK(console_lock) -#define TRACK_CONSOLE_TIME (CONFIG(HAVE_MONOTONIC_TIMER) && \ - (ENV_RAMSTAGE || !CONFIG(CAR_GLOBAL_MIGRATION))) +#define TRACK_CONSOLE_TIME (CONFIG(HAVE_MONOTONIC_TIMER)) static struct mono_time mt_start, mt_stop; static long console_usecs; diff --git a/src/cpu/Kconfig b/src/cpu/Kconfig index 3c0bf89afd..1ad7ef1b1b 100644 --- a/src/cpu/Kconfig +++ b/src/cpu/Kconfig @@ -6,14 +6,6 @@ source "src/cpu/*/Kconfig" if ARCH_X86 -config CAR_GLOBAL_MIGRATION - bool - default n - help - This option is selected if there is need to migrate CAR globals. - All stages which use CAR globals can directly access the variables - from their linked addresses. - config DCACHE_RAM_BASE hex diff --git a/src/include/rules.h b/src/include/rules.h index 9e13ee65a6..fa60ede181 100644 --- a/src/include/rules.h +++ b/src/include/rules.h @@ -258,7 +258,7 @@ /* No .data sections with execute-in-place from ROM. */ #define ENV_STAGE_HAS_DATA_SECTION !ENV_CACHE_AS_RAM /* No .bss sections for stage with CAR teardown. */ -#define ENV_STAGE_HAS_BSS_SECTION !(ENV_ROMSTAGE && CONFIG(CAR_GLOBAL_MIGRATION)) +#define ENV_STAGE_HAS_BSS_SECTION 1 #else /* Both .data and .bss, sometimes SRAM not DRAM. */ #define ENV_STAGE_HAS_DATA_SECTION 1 From bc2204edd24eab1162613fe610746a63ec1a66c0 Mon Sep 17 00:00:00 2001 From: Patrick Rudolph Date: Thu, 21 Nov 2019 17:33:58 +0100 Subject: [PATCH 0479/1242] util/pgtblgen: Fix typo Change-Id: I638eda3040c7225aa4a8b492c8dc78b0e2effba1 Signed-off-by: Patrick Rudolph Reviewed-on: https://review.coreboot.org/c/coreboot/+/37369 Reviewed-by: Patrick Georgi Reviewed-by: Angel Pons Tested-by: build bot (Jenkins) --- util/pgtblgen/pgtblgen.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/util/pgtblgen/pgtblgen.c b/util/pgtblgen/pgtblgen.c index efbad55204..e9ebd8b0cf 100644 --- a/util/pgtblgen/pgtblgen.c +++ b/util/pgtblgen/pgtblgen.c @@ -28,7 +28,7 @@ static void usage(char *argv[]) printf("usage: %s -b -a -o \n", argv[0]); printf(" -a\t architecure. Supported: x86_64\n"); printf(" -b\t base address\n"); - printf(" -b\t the file to write to\n"); + printf(" -o\t the file to write to\n"); printf(" -h\t show this help text\n"); } From cd666d992de9db8f207d997a6a65373904785a09 Mon Sep 17 00:00:00 2001 From: Patrick Georgi Date: Fri, 29 Nov 2019 12:14:30 +0100 Subject: [PATCH 0480/1242] lib/imd_cbmem: Remove indirection through cbmem_get_imd() MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit It always returns the same pointer so why not use the pointer directly? Change-Id: Ib5a13edc7f3ab05c3baf9956ab67031507bdddc1 Signed-off-by: Patrick Georgi Reviewed-on: https://review.coreboot.org/c/coreboot/+/37360 Reviewed-by: Kyösti Mälkki Reviewed-by: Angel Pons Tested-by: build bot (Jenkins) --- src/lib/imd_cbmem.c | 12 ++++-------- 1 file changed, 4 insertions(+), 8 deletions(-) diff --git a/src/lib/imd_cbmem.c b/src/lib/imd_cbmem.c index 6fd48d57dd..d7f7d20f25 100644 --- a/src/lib/imd_cbmem.c +++ b/src/lib/imd_cbmem.c @@ -43,11 +43,7 @@ void *cbmem_top(void) } -static inline struct imd *cbmem_get_imd(void) -{ - static struct imd imd_cbmem; - return &imd_cbmem; -} +static struct imd imd_cbmem; static inline const struct cbmem_entry *imd_to_cbmem(const struct imd_entry *e) { @@ -75,7 +71,7 @@ static struct imd *imd_init_backing(struct imd *backing) { struct imd *imd; - imd = cbmem_get_imd(); + imd = &imd_cbmem; if (imd != NULL) return imd; @@ -288,7 +284,7 @@ void cbmem_add_bootmem(void) void cbmem_get_region(void **baseptr, size_t *size) { - imd_region_used(cbmem_get_imd(), baseptr, size); + imd_region_used(&imd_cbmem, baseptr, size); } #if ENV_PAYLOAD_LOADER || (CONFIG(EARLY_CBMEM_LIST) \ @@ -314,7 +310,7 @@ void cbmem_add_records_to_cbtable(struct lb_header *header) struct imd_cursor cursor; struct imd *imd; - imd = cbmem_get_imd(); + imd = &imd_cbmem; if (imd_cursor_init(imd, &cursor)) return; From a854c9d7874a4592f2ea9b8d19703c81adef33e9 Mon Sep 17 00:00:00 2001 From: Arthur Heymans Date: Wed, 27 Nov 2019 21:53:01 +0100 Subject: [PATCH 0481/1242] nb/intel/x4x: Factor out hiding PCI devs in pure fn This increases readability. Also change the update expression. '--variable' does not make much sense there. Change-Id: I64db2460115f5fb35ca197b83440f8ee47470761 Signed-off-by: Arthur Heymans Reviewed-on: https://review.coreboot.org/c/coreboot/+/37291 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan Reviewed-by: Angel Pons --- src/northbridge/intel/x4x/northbridge.c | 53 +++++++++---------------- 1 file changed, 19 insertions(+), 34 deletions(-) diff --git a/src/northbridge/intel/x4x/northbridge.c b/src/northbridge/intel/x4x/northbridge.c index 39f24d302b..252e14fda6 100644 --- a/src/northbridge/intel/x4x/northbridge.c +++ b/src/northbridge/intel/x4x/northbridge.c @@ -206,45 +206,30 @@ static void enable_dev(struct device *dev) dev->ops = &cpu_bus_ops; } +static void hide_pci_fn(const int dev_bit_base, const struct device *dev) +{ + if (!dev || dev->enabled) + return; + const unsigned int fn = PCI_FUNC(dev->path.pci.devfn); + const struct device *const d0f0 = pcidev_on_root(0, 0); + pci_update_config32(d0f0, D0F0_DEVEN, ~(1 << (dev_bit_base + fn)), 0); +} + +static void hide_pci_dev(const int dev, int functions, const int dev_bit_base) +{ + for (; functions >= 0; functions--) + hide_pci_fn(dev_bit_base, pcidev_on_root(dev, functions)); +} + static void x4x_init(void *const chip_info) { - int dev, fn, bit_base; - struct device *const d0f0 = pcidev_on_root(0x0, 0); /* Hide internal functions based on devicetree info. */ - for (dev = 6; dev > 0; --dev) { - switch (dev) { - case 6: /* PEG1: only on P45 */ - fn = 0; - bit_base = 13; - break; - case 3: /* ME */ - fn = 3; - bit_base = 6; - break; - case 2: /* IGD */ - fn = 1; - bit_base = 3; - break; - case 1: /* PEG0 */ - fn = 0; - bit_base = 1; - break; - case 4: /* Nothing to do */ - case 5: - continue; - } - for (; fn >= 0; --fn) { - const struct device *const d = - pcidev_on_root(dev, fn); - if (!d || d->enabled) - continue; - const u32 deven = pci_read_config32(d0f0, D0F0_DEVEN); - pci_write_config32(d0f0, D0F0_DEVEN, - deven & ~(1 << (bit_base + fn))); - } - } + hide_pci_dev(6, 0, 13); /* PEG1: only on P45 */ + hide_pci_dev(3, 3, 6); /* ME */ + hide_pci_dev(2, 1, 3); /* IGD */ + hide_pci_dev(1, 0, 1); /* PEG0 */ const u32 deven = pci_read_config32(d0f0, D0F0_DEVEN); if (!(deven & (0xf << 6))) From eef7c69d491de1a9b2fbc68f333c54fd5eac86a3 Mon Sep 17 00:00:00 2001 From: Maxim Polyakov Date: Wed, 27 Nov 2019 13:01:24 +0300 Subject: [PATCH 0482/1242] superio/nct5539d: include the missing acpi.h and ssdt.h Change-Id: Idd80fae1c39f3c7c4bc66a42e9023fb7a727b024 Signed-off-by: Maxim Polyakov Reviewed-on: https://review.coreboot.org/c/coreboot/+/37274 Tested-by: build bot (Jenkins) Reviewed-by: Felix Held --- src/superio/nuvoton/nct5539d/superio.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/src/superio/nuvoton/nct5539d/superio.c b/src/superio/nuvoton/nct5539d/superio.c index 4f2a4a5c16..45187ac74b 100644 --- a/src/superio/nuvoton/nct5539d/superio.c +++ b/src/superio/nuvoton/nct5539d/superio.c @@ -24,9 +24,12 @@ #include #include #include - #include "nct5539d.h" +#if CONFIG(HAVE_ACPI_TABLES) +#include +#include +#endif static void nct5539d_init(struct device *dev) { From 92542469e2df519b91cd88e57fd934b9c1c4d760 Mon Sep 17 00:00:00 2001 From: Elyes HAOUAS Date: Sat, 30 Nov 2019 17:56:41 +0100 Subject: [PATCH 0483/1242] src/superio: Remove unused include Change-Id: I941c3d80d6b822b12a2d0c279415ab0c6b7f375b Signed-off-by: Elyes HAOUAS Reviewed-on: https://review.coreboot.org/c/coreboot/+/37379 Tested-by: build bot (Jenkins) Reviewed-by: Felix Held --- src/superio/fintek/f81803a/superio.c | 1 - src/superio/nuvoton/nct5539d/superio.c | 1 - 2 files changed, 2 deletions(-) diff --git a/src/superio/fintek/f81803a/superio.c b/src/superio/fintek/f81803a/superio.c index 1cb31bfa9b..5a54f54f52 100644 --- a/src/superio/fintek/f81803a/superio.c +++ b/src/superio/fintek/f81803a/superio.c @@ -17,7 +17,6 @@ #include #include #include -#include #include #include "f81803a.h" diff --git a/src/superio/nuvoton/nct5539d/superio.c b/src/superio/nuvoton/nct5539d/superio.c index 45187ac74b..04461b3abe 100644 --- a/src/superio/nuvoton/nct5539d/superio.c +++ b/src/superio/nuvoton/nct5539d/superio.c @@ -22,7 +22,6 @@ #include #include #include -#include #include #include "nct5539d.h" From a8582c4c0266bc54db7957173b496dcf1cb4a9e7 Mon Sep 17 00:00:00 2001 From: Patrick Georgi Date: Sat, 30 Nov 2019 10:49:17 +0100 Subject: [PATCH 0484/1242] lib/cbmem_console: Rename cbmem_console_p to current_console MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit That way, current_console_set() also isn't necessary anymore and symmetry is re-established. Change-Id: I392ed509f490d63b0c016a80fd7ab3ef98ba8019 Signed-off-by: Patrick Georgi Reviewed-on: https://review.coreboot.org/c/coreboot/+/37374 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki --- src/lib/cbmem_console.c | 39 +++++++++++++++++---------------------- 1 file changed, 17 insertions(+), 22 deletions(-) diff --git a/src/lib/cbmem_console.c b/src/lib/cbmem_console.c index 7bd247d55b..f6a055e079 100644 --- a/src/lib/cbmem_console.c +++ b/src/lib/cbmem_console.c @@ -48,7 +48,7 @@ struct cbmem_console { _Static_assert(CONFIG_CONSOLE_CBMEM_BUFFER_SIZE <= MAX_SIZE, "cbmem_console format cannot support buffers larger than 256MB!"); -static struct cbmem_console *cbmem_console_p; +static struct cbmem_console *current_console; /* * While running from ROM, before DRAM is initialized, some area in cache as @@ -64,11 +64,6 @@ static struct cbmem_console *cbmem_console_p; #define STATIC_CONSOLE_SIZE 1024 static u8 static_console[STATIC_CONSOLE_SIZE]; -static void current_console_set(struct cbmem_console *new_console_p) -{ - cbmem_console_p = new_console_p; -} - static int buffer_valid(struct cbmem_console *cbm_cons_p, u32 total_space) { return (cbm_cons_p->cursor & CURSOR_MASK) < cbm_cons_p->size && @@ -81,7 +76,7 @@ static void init_console_ptr(void *storage, u32 total_space) struct cbmem_console *cbm_cons_p = storage; if (!cbm_cons_p || total_space <= sizeof(struct cbmem_console)) { - current_console_set(NULL); + current_console = NULL; return; } @@ -90,7 +85,7 @@ static void init_console_ptr(void *storage, u32 total_space) cbm_cons_p->cursor = 0; } - current_console_set(cbm_cons_p); + current_console = cbm_cons_p; } void cbmemc_init(void) @@ -106,19 +101,19 @@ void cbmemc_init(void) void cbmemc_tx_byte(unsigned char data) { - if (!cbmem_console_p || !cbmem_console_p->size) + if (!current_console || !current_console->size) return; - u32 flags = cbmem_console_p->cursor & ~CURSOR_MASK; - u32 cursor = cbmem_console_p->cursor & CURSOR_MASK; + u32 flags = current_console->cursor & ~CURSOR_MASK; + u32 cursor = current_console->cursor & CURSOR_MASK; - cbmem_console_p->body[cursor++] = data; - if (cursor >= cbmem_console_p->size) { + current_console->body[cursor++] = data; + if (cursor >= current_console->size) { cursor = 0; flags |= OVERFLOW; } - cbmem_console_p->cursor = flags | cursor; + current_console->cursor = flags | cursor; } /* @@ -158,7 +153,7 @@ static void cbmemc_reinit(int is_recovery) const size_t size = CONFIG_CONSOLE_CBMEM_BUFFER_SIZE; /* If CBMEM entry already existed, old contents are not altered. */ struct cbmem_console *cbmem_cons_p = cbmem_add(CBMEM_ID_CONSOLE, size); - struct cbmem_console *previous_cons_p = cbmem_console_p; + struct cbmem_console *previous_cons_p = current_console; init_console_ptr(cbmem_cons_p, size); copy_console_buffer(previous_cons_p); @@ -171,15 +166,15 @@ POSTCAR_CBMEM_INIT_HOOK(cbmemc_reinit) void cbmem_dump_console(void) { u32 cursor; - if (!cbmem_console_p) + if (!current_console) return; uart_init(0); - if (cbmem_console_p->cursor & OVERFLOW) - for (cursor = cbmem_console_p->cursor & CURSOR_MASK; - cursor < cbmem_console_p->size; cursor++) - uart_tx_byte(0, cbmem_console_p->body[cursor]); - for (cursor = 0; cursor < (cbmem_console_p->cursor & CURSOR_MASK); cursor++) - uart_tx_byte(0, cbmem_console_p->body[cursor]); + if (current_console->cursor & OVERFLOW) + for (cursor = current_console->cursor & CURSOR_MASK; + cursor < current_console->size; cursor++) + uart_tx_byte(0, current_console->body[cursor]); + for (cursor = 0; cursor < (current_console->cursor & CURSOR_MASK); cursor++) + uart_tx_byte(0, current_console->body[cursor]); } #endif From ae64f22e8d5707ef715ad4bd01b6181653a3f9ca Mon Sep 17 00:00:00 2001 From: Patrick Rudolph Date: Sat, 30 Nov 2019 09:42:20 +0100 Subject: [PATCH 0485/1242] drivers/usb/ehci_debug: Add x86_64 support MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Use proper int to pointer conversions. Tested on Lenovo T410 with x86_64 enabled. Still works. Change-Id: I4ed62297fb47d7d83d4b28e80f3770de99ce70f7 Signed-off-by: Patrick Rudolph Reviewed-on: https://review.coreboot.org/c/coreboot/+/37393 Reviewed-by: Kyösti Mälkki Tested-by: build bot (Jenkins) --- src/drivers/usb/ehci_debug.c | 4 ++-- src/drivers/usb/ehci_debug.h | 2 +- src/drivers/usb/pci_ehci.c | 3 ++- 3 files changed, 5 insertions(+), 4 deletions(-) diff --git a/src/drivers/usb/ehci_debug.c b/src/drivers/usb/ehci_debug.c index d6b468c3a2..318dfe7f59 100644 --- a/src/drivers/usb/ehci_debug.c +++ b/src/drivers/usb/ehci_debug.c @@ -434,7 +434,7 @@ static int ehci_wait_for_port(struct ehci_regs *ehci_regs, int port) -static int usbdebug_init_(unsigned int ehci_bar, unsigned int offset, struct ehci_debug_info *info) +static int usbdebug_init_(uintptr_t ehci_bar, unsigned int offset, struct ehci_debug_info *info) { struct ehci_caps *ehci_caps; struct ehci_regs *ehci_regs; @@ -653,7 +653,7 @@ void dbgp_put(struct dbgp_pipe *pipe) } #if ENV_RAMSTAGE -void usbdebug_re_enable(unsigned int ehci_base) +void usbdebug_re_enable(uintptr_t ehci_base) { struct ehci_debug_info *dbg_info = dbgp_ehci_info(); u64 diff; diff --git a/src/drivers/usb/ehci_debug.h b/src/drivers/usb/ehci_debug.h index 0f20c2f5fb..a6a3e55826 100644 --- a/src/drivers/usb/ehci_debug.h +++ b/src/drivers/usb/ehci_debug.h @@ -16,7 +16,7 @@ #include -void usbdebug_re_enable(unsigned int ehci_base); +void usbdebug_re_enable(uintptr_t ehci_base); void usbdebug_disable(void); /* Returns 0 on success and sets MMIO base and dbg_offset if EHCI debug diff --git a/src/drivers/usb/pci_ehci.c b/src/drivers/usb/pci_ehci.c index a740d50dbf..dfc78cc666 100644 --- a/src/drivers/usb/pci_ehci.c +++ b/src/drivers/usb/pci_ehci.c @@ -116,6 +116,7 @@ void pci_ehci_read_resources(struct device *dev) u8 *pci_ehci_base_regs(pci_devfn_t sdev) { - u8 *base = (u8 *)(pci_s_read_config32(sdev, EHCI_BAR_INDEX) & ~0x0f); + u32 bar = pci_s_read_config32(sdev, EHCI_BAR_INDEX) & ~0x0f; + u8 *base = (u8 *)(uintptr_t)bar; return base + HC_LENGTH(read32(base)); } From c9b13594eb8d425e54a126b5c10e3f6fbc41528b Mon Sep 17 00:00:00 2001 From: Patrick Georgi Date: Fri, 29 Nov 2019 11:47:47 +0100 Subject: [PATCH 0486/1242] src/: Remove g_ prefixes and _g suffixes from variables MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit These were often used to distinguish CAR_GLOBAL variables that weren't directly usable. Since we're getting rid of this special case, also get rid of the marker. This change was created using coccinelle and the following script: @match@ type T; identifier old =~ "^(g_.*|.*_g)$"; @@ old @script:python global_marker@ old << match.old; new; @@ new = old if old[0:2] == "g_": new = new[2:] if new[-2:] == "_g": new = new[:-2] coccinelle.new = new @@ identifier match.old, global_marker.new; @@ - old + new @@ type T; identifier match.old, global_marker.new; @@ - T old; + T new; @@ type T; identifier match.old, global_marker.new; @@ - T old + T new = ...; There were some manual fixups: Some code still uses the global/local variable naming scheme, so keep g_* there, and some variable names weren't completely rewritten. Change-Id: I4936ff9780a0d3ed9b8b539772bc48887f8d5eed Signed-off-by: Patrick Georgi Reviewed-on: https://review.coreboot.org/c/coreboot/+/37358 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki Reviewed-by: HAOUAS Elyes --- src/cpu/intel/common/fsb.c | 24 ++-- src/cpu/x86/lapic/apic_timer.c | 16 +-- src/cpu/x86/tsc/delay_tsc.c | 16 +-- src/drivers/elog/elog.c | 81 ++++++------ src/drivers/i2c/tpm/cr50.c | 20 +-- src/drivers/i2c/tpm/tis.c | 36 +++--- src/drivers/i2c/tpm/tpm.c | 74 +++++------ src/drivers/pc80/pc/i8254.c | 14 +-- src/drivers/spi/flashconsole.c | 44 +++---- src/drivers/spi/tpm/tpm.c | 40 +++--- src/drivers/vpd/vpd.c | 24 ++-- src/soc/intel/common/block/cse/cse.c | 20 +-- src/soc/nvidia/tegra/i2c.c | 4 +- src/soc/nvidia/tegra/i2c.h | 2 +- src/soc/nvidia/tegra124/i2c.c | 2 +- src/soc/nvidia/tegra210/i2c.c | 2 +- src/southbridge/intel/common/spi.c | 180 +++++++++++++-------------- 17 files changed, 301 insertions(+), 298 deletions(-) diff --git a/src/cpu/intel/common/fsb.c b/src/cpu/intel/common/fsb.c index 0f6fd1d921..726ab1c240 100644 --- a/src/cpu/intel/common/fsb.c +++ b/src/cpu/intel/common/fsb.c @@ -19,8 +19,8 @@ #include #include -static u32 g_timer_fsb; -static u32 g_timer_tsc; +static u32 timer_fsb; +static u32 timer_tsc; /* This is not an architectural MSR. */ #define MSR_PLATFORM_INFO 0xce @@ -98,8 +98,8 @@ static void resolve_timebase(void) ret = get_fsb_tsc(&fsb, &ratio); if (ret == 0) { u32 tsc = 100 * DIV_ROUND_CLOSEST(ratio * fsb, 100); - g_timer_fsb = fsb; - g_timer_tsc = tsc; + timer_fsb = fsb; + timer_tsc = tsc; return; } @@ -109,27 +109,27 @@ static void resolve_timebase(void) printk(BIOS_ERR, "CPU not supported\n"); /* Set some semi-ridiculous defaults. */ - g_timer_fsb = 500; - g_timer_tsc = 5000; + timer_fsb = 500; + timer_tsc = 5000; return; } u32 get_timer_fsb(void) { - if (g_timer_fsb > 0) - return g_timer_fsb; + if (timer_fsb > 0) + return timer_fsb; resolve_timebase(); - return g_timer_fsb; + return timer_fsb; } unsigned long tsc_freq_mhz(void) { - if (g_timer_tsc > 0) - return g_timer_tsc; + if (timer_tsc > 0) + return timer_tsc; resolve_timebase(); - return g_timer_tsc; + return timer_tsc; } /** diff --git a/src/cpu/x86/lapic/apic_timer.c b/src/cpu/x86/lapic/apic_timer.c index 8f0f7afcfb..0b3f6910ae 100644 --- a/src/cpu/x86/lapic/apic_timer.c +++ b/src/cpu/x86/lapic/apic_timer.c @@ -62,7 +62,7 @@ static struct monotonic_counter { int initialized; struct mono_time time; uint32_t last_value; -} mono_counter_g; +} mono_counter; void timer_monotonic_get(struct mono_time *mt) { @@ -70,7 +70,7 @@ void timer_monotonic_get(struct mono_time *mt) uint32_t usecs_elapsed; uint32_t timer_fsb; - if (!mono_counter_g.initialized) { + if (!mono_counter.initialized) { init_timer(); timer_fsb = get_timer_fsb(); /* An FSB frequency of 200Mhz provides a 20 second polling @@ -80,22 +80,22 @@ void timer_monotonic_get(struct mono_time *mt) printk(BIOS_WARNING, "apic timer freq (%d) may be too fast.\n", timer_fsb); - mono_counter_g.last_value = lapic_read(LAPIC_TMCCT); - mono_counter_g.initialized = 1; + mono_counter.last_value = lapic_read(LAPIC_TMCCT); + mono_counter.initialized = 1; } timer_fsb = get_timer_fsb(); current_tick = lapic_read(LAPIC_TMCCT); /* Note that the APIC timer counts down. */ - usecs_elapsed = (mono_counter_g.last_value - current_tick) / timer_fsb; + usecs_elapsed = (mono_counter.last_value - current_tick) / timer_fsb; /* Update current time and tick values only if a full tick occurred. */ if (usecs_elapsed) { - mono_time_add_usecs(&mono_counter_g.time, usecs_elapsed); - mono_counter_g.last_value = current_tick; + mono_time_add_usecs(&mono_counter.time, usecs_elapsed); + mono_counter.last_value = current_tick; } /* Save result. */ - *mt = mono_counter_g.time; + *mt = mono_counter.time; } #endif diff --git a/src/cpu/x86/tsc/delay_tsc.c b/src/cpu/x86/tsc/delay_tsc.c index fda8fe1b20..4a1f5c98be 100644 --- a/src/cpu/x86/tsc/delay_tsc.c +++ b/src/cpu/x86/tsc/delay_tsc.c @@ -48,7 +48,7 @@ static struct monotonic_counter { int initialized; struct mono_time time; uint64_t last_value; -} mono_counter_g; +} mono_counter; void timer_monotonic_get(struct mono_time *mt) { @@ -56,14 +56,14 @@ void timer_monotonic_get(struct mono_time *mt) uint64_t ticks_elapsed; unsigned long ticks_per_usec; - if (!mono_counter_g.initialized) { + if (!mono_counter.initialized) { init_timer(); - mono_counter_g.last_value = rdtscll(); - mono_counter_g.initialized = 1; + mono_counter.last_value = rdtscll(); + mono_counter.initialized = 1; } current_tick = rdtscll(); - ticks_elapsed = current_tick - mono_counter_g.last_value; + ticks_elapsed = current_tick - mono_counter.last_value; ticks_per_usec = tsc_freq_mhz(); /* Update current time and tick values only if a full tick occurred. */ @@ -71,11 +71,11 @@ void timer_monotonic_get(struct mono_time *mt) uint64_t usecs_elapsed; usecs_elapsed = ticks_elapsed / ticks_per_usec; - mono_time_add_usecs(&mono_counter_g.time, (long)usecs_elapsed); - mono_counter_g.last_value = current_tick; + mono_time_add_usecs(&mono_counter.time, (long)usecs_elapsed); + mono_counter.last_value = current_tick; } /* Save result. */ - *mt = mono_counter_g.time; + *mt = mono_counter.time; } #endif diff --git a/src/drivers/elog/elog.c b/src/drivers/elog/elog.c index 768ea28468..97a9c7fa79 100644 --- a/src/drivers/elog/elog.c +++ b/src/drivers/elog/elog.c @@ -65,14 +65,14 @@ struct elog_state { enum elog_init_state elog_initialized; }; -static struct elog_state g_elog_state; +static struct elog_state elog_state; #define ELOG_SIZE (4 * KiB) static uint8_t elog_mirror_buf[ELOG_SIZE]; static inline struct region_device *mirror_dev_get(void) { - return &g_elog_state.mirror_dev.rdev; + return &elog_state.mirror_dev.rdev; } static size_t elog_events_start(void) @@ -83,7 +83,7 @@ static size_t elog_events_start(void) static size_t elog_events_total_space(void) { - return region_device_sz(&g_elog_state.nv_dev) - elog_events_start(); + return region_device_sz(&elog_state.nv_dev) - elog_events_start(); } static struct event_header *elog_get_event_buffer(size_t offset, size_t size) @@ -93,8 +93,9 @@ static struct event_header *elog_get_event_buffer(size_t offset, size_t size) static struct event_header *elog_get_next_event_buffer(size_t size) { - elog_debug("ELOG: new event at offset 0x%zx\n", g_elog_state.mirror_last_write); - return elog_get_event_buffer(g_elog_state.mirror_last_write, size); + elog_debug("ELOG: new event at offset 0x%zx\n", + elog_state.mirror_last_write); + return elog_get_event_buffer(elog_state.mirror_last_write, size); } static void elog_put_event_buffer(struct event_header *event) @@ -105,53 +106,53 @@ static void elog_put_event_buffer(struct event_header *event) static size_t elog_mirror_reset_last_write(void) { /* Return previous write value. */ - size_t prev = g_elog_state.mirror_last_write; + size_t prev = elog_state.mirror_last_write; - g_elog_state.mirror_last_write = 0; + elog_state.mirror_last_write = 0; return prev; } static void elog_mirror_increment_last_write(size_t size) { - g_elog_state.mirror_last_write += size; + elog_state.mirror_last_write += size; } static void elog_nv_reset_last_write(void) { - g_elog_state.nv_last_write = 0; + elog_state.nv_last_write = 0; } static void elog_nv_increment_last_write(size_t size) { - g_elog_state.nv_last_write += size; + elog_state.nv_last_write += size; } static void elog_nv_needs_possible_erase(void) { /* If last write is 0 it means it is already erased. */ - if (g_elog_state.nv_last_write != 0) - g_elog_state.nv_last_write = NV_NEEDS_ERASE; + if (elog_state.nv_last_write != 0) + elog_state.nv_last_write = NV_NEEDS_ERASE; } static bool elog_should_shrink(void) { - return g_elog_state.mirror_last_write >= g_elog_state.full_threshold; + return elog_state.mirror_last_write >= elog_state.full_threshold; } static bool elog_nv_needs_erase(void) { - return g_elog_state.nv_last_write == NV_NEEDS_ERASE; + return elog_state.nv_last_write == NV_NEEDS_ERASE; } static bool elog_nv_needs_update(void) { - return g_elog_state.nv_last_write != g_elog_state.mirror_last_write; + return elog_state.nv_last_write != elog_state.mirror_last_write; } static size_t elog_nv_region_to_update(size_t *offset) { - *offset = g_elog_state.nv_last_write; - return g_elog_state.mirror_last_write - g_elog_state.nv_last_write; + *offset = elog_state.nv_last_write; + return elog_state.mirror_last_write - elog_state.nv_last_write; } /* @@ -335,7 +336,7 @@ static void elog_nv_write(size_t offset, size_t size) return; /* Write the data to flash */ - if (rdev_writeat(&g_elog_state.nv_dev, address, offset, size) != size) + if (rdev_writeat(&elog_state.nv_dev, address, offset, size) != size) printk(BIOS_ERR, "ELOG: NV Write failed at 0x%zx, size 0x%zx\n", offset, size); @@ -348,11 +349,11 @@ static void elog_nv_write(size_t offset, size_t size) */ static void elog_nv_erase(void) { - size_t size = region_device_sz(&g_elog_state.nv_dev); + size_t size = region_device_sz(&elog_state.nv_dev); elog_debug("%s()\n", __func__); /* Erase the sectors in this region */ - if (rdev_eraseat(&g_elog_state.nv_dev, 0, size) != size) + if (rdev_eraseat(&elog_state.nv_dev, 0, size) != size) printk(BIOS_ERR, "ELOG: erase failure.\n"); } @@ -411,11 +412,11 @@ static int elog_scan_flash(void) void *mirror_buffer; const struct region_device *rdev = mirror_dev_get(); - size_t size = region_device_sz(&g_elog_state.nv_dev); + size_t size = region_device_sz(&elog_state.nv_dev); /* Fill memory buffer by reading from SPI */ mirror_buffer = rdev_mmap_full(rdev); - if (rdev_readat(&g_elog_state.nv_dev, mirror_buffer, 0, size) != size) { + if (rdev_readat(&elog_state.nv_dev, mirror_buffer, 0, size) != size) { rdev_munmap(rdev, mirror_buffer); printk(BIOS_ERR, "ELOG: NV read failure.\n"); return -1; @@ -580,7 +581,7 @@ static int elog_prepare_empty(void) static int elog_shrink(void) { if (elog_should_shrink()) - return elog_shrink_by_size(g_elog_state.shrink_size); + return elog_shrink_by_size(elog_state.shrink_size); return 0; } @@ -593,12 +594,13 @@ static inline u8 *elog_flash_offset_to_address(void) if (!CONFIG(BOOT_DEVICE_MEMORY_MAPPED)) return NULL; - if (!region_device_sz(&g_elog_state.nv_dev)) + if (!region_device_sz(&elog_state.nv_dev)) return NULL; /* Get a view into the read-only boot device. */ - return rdev_mmap(boot_device_ro(), region_device_offset(&g_elog_state.nv_dev), - region_device_sz(&g_elog_state.nv_dev)); + return rdev_mmap(boot_device_ro(), + region_device_offset(&elog_state.nv_dev), + region_device_sz(&elog_state.nv_dev)); } /* @@ -611,7 +613,7 @@ int elog_smbios_write_type15(unsigned long *current, int handle) int len = sizeof(struct smbios_type15); uintptr_t log_address; - size_t elog_size = region_device_sz(&g_elog_state.nv_dev); + size_t elog_size = region_device_sz(&elog_state.nv_dev); if (CONFIG(ELOG_CBMEM)) { /* Save event log buffer into CBMEM for the OS to read */ @@ -665,7 +667,7 @@ static int elog_find_flash(void) { size_t total_size; size_t reserved_space = ELOG_MIN_AVAILABLE_ENTRIES * MAX_EVENT_SIZE; - struct region_device *rdev = &g_elog_state.nv_dev; + struct region_device *rdev = &elog_state.nv_dev; elog_debug("%s()\n", __func__); @@ -688,10 +690,10 @@ static int elog_find_flash(void) total_size = MIN(ELOG_SIZE, region_device_sz(rdev)); rdev_chain(rdev, rdev, 0, total_size); - g_elog_state.full_threshold = total_size - reserved_space; - g_elog_state.shrink_size = total_size * ELOG_SHRINK_PERCENTAGE / 100; + elog_state.full_threshold = total_size - reserved_space; + elog_state.shrink_size = total_size * ELOG_SHRINK_PERCENTAGE / 100; - if (reserved_space > g_elog_state.shrink_size) { + if (reserved_space > elog_state.shrink_size) { printk(BIOS_ERR, "ELOG: SHRINK_PERCENTAGE too small\n"); return -1; } @@ -734,7 +736,7 @@ static int elog_sync_to_nv(void) if (elog_scan_flash() < 0) { printk(BIOS_ERR, "ELOG: Sync back from NV storage failed.\n"); elog_debug_dump_buffer("ELOG: Buffer from NV:\n"); - g_elog_state.elog_initialized = ELOG_BROKEN; + elog_state.elog_initialized = ELOG_BROKEN; return -1; } @@ -776,7 +778,7 @@ int elog_init(void) { void *mirror_buffer; size_t elog_size; - switch (g_elog_state.elog_initialized) { + switch (elog_state.elog_initialized) { case ELOG_UNINITIALIZED: break; case ELOG_INITIALIZED: @@ -784,7 +786,7 @@ int elog_init(void) case ELOG_BROKEN: return -1; } - g_elog_state.elog_initialized = ELOG_BROKEN; + elog_state.elog_initialized = ELOG_BROKEN; elog_debug("elog_init()\n"); @@ -792,19 +794,20 @@ int elog_init(void) if (elog_find_flash() < 0) return -1; - elog_size = region_device_sz(&g_elog_state.nv_dev); + elog_size = region_device_sz(&elog_state.nv_dev); mirror_buffer = elog_mirror_buf; if (!mirror_buffer) { printk(BIOS_ERR, "ELOG: Unable to allocate backing store\n"); return -1; } - mem_region_device_rw_init(&g_elog_state.mirror_dev, mirror_buffer, elog_size); + mem_region_device_rw_init(&elog_state.mirror_dev, mirror_buffer, + elog_size); /* * Mark as initialized to allow elog_init() to be called and deemed * successful in the prepare/shrink path which adds events. */ - g_elog_state.elog_initialized = ELOG_INITIALIZED; + elog_state.elog_initialized = ELOG_INITIALIZED; /* Load the log from flash and prepare the flash if necessary. */ if (elog_scan_flash() < 0 && elog_prepare_empty() < 0) { @@ -813,8 +816,8 @@ int elog_init(void) } printk(BIOS_INFO, "ELOG: area is %zu bytes, full threshold %d," - " shrink size %d\n", region_device_sz(&g_elog_state.nv_dev), - g_elog_state.full_threshold, g_elog_state.shrink_size); + " shrink size %d\n", region_device_sz(&elog_state.nv_dev), + elog_state.full_threshold, elog_state.shrink_size); if (ENV_PAYLOAD_LOADER) elog_add_boot_count(); diff --git a/src/drivers/i2c/tpm/cr50.c b/src/drivers/i2c/tpm/cr50.c index f386dacb0b..8ea544d0db 100644 --- a/src/drivers/i2c/tpm/cr50.c +++ b/src/drivers/i2c/tpm/cr50.c @@ -54,7 +54,7 @@ struct tpm_inf_dev { uint8_t buf[CR50_MAX_BUFSIZE + sizeof(uint8_t)]; }; -static struct tpm_inf_dev g_tpm_dev; +static struct tpm_inf_dev tpm_dev; __weak int tis_plat_irq_status(void) { @@ -101,14 +101,14 @@ static int cr50_i2c_wait_tpm_ready(struct tpm_chip *chip) static int cr50_i2c_read(struct tpm_chip *chip, uint8_t addr, uint8_t *buffer, size_t len) { - if (g_tpm_dev.addr == 0) + if (tpm_dev.addr == 0) return -1; /* Clear interrupt before starting transaction */ tis_plat_irq_status(); /* Send the register address byte to the TPM */ - if (i2c_write_raw(g_tpm_dev.bus, g_tpm_dev.addr, &addr, 1)) { + if (i2c_write_raw(tpm_dev.bus, tpm_dev.addr, &addr, 1)) { printk(BIOS_ERR, "%s: Address write failed\n", __func__); return -1; } @@ -118,7 +118,7 @@ static int cr50_i2c_read(struct tpm_chip *chip, uint8_t addr, return -1; /* Read response data from the TPM */ - if (i2c_read_raw(g_tpm_dev.bus, g_tpm_dev.addr, buffer, len)) { + if (i2c_read_raw(tpm_dev.bus, tpm_dev.addr, buffer, len)) { printk(BIOS_ERR, "%s: Read response failed\n", __func__); return -1; } @@ -143,20 +143,20 @@ static int cr50_i2c_read(struct tpm_chip *chip, uint8_t addr, static int cr50_i2c_write(struct tpm_chip *chip, uint8_t addr, uint8_t *buffer, size_t len) { - if (g_tpm_dev.addr == 0) + if (tpm_dev.addr == 0) return -1; if (len > CR50_MAX_BUFSIZE) return -1; /* Prepend the 'register address' to the buffer */ - g_tpm_dev.buf[0] = addr; - memcpy(g_tpm_dev.buf + 1, buffer, len); + tpm_dev.buf[0] = addr; + memcpy(tpm_dev.buf + 1, buffer, len); /* Clear interrupt before starting transaction */ tis_plat_irq_status(); /* Send write request buffer with address */ - if (i2c_write_raw(g_tpm_dev.bus, g_tpm_dev.addr, g_tpm_dev.buf, len + 1)) { + if (i2c_write_raw(tpm_dev.bus, tpm_dev.addr, tpm_dev.buf, len + 1)) { printk(BIOS_ERR, "%s: Error writing to TPM\n", __func__); return -1; } @@ -494,8 +494,8 @@ int tpm_vendor_init(struct tpm_chip *chip, unsigned int bus, uint32_t dev_addr) return -1; } - g_tpm_dev.bus = bus; - g_tpm_dev.addr = dev_addr; + tpm_dev.bus = bus; + tpm_dev.addr = dev_addr; cr50_vendor_init(chip); diff --git a/src/drivers/i2c/tpm/tis.c b/src/drivers/i2c/tpm/tis.c index d791a56af5..8b07bb78dd 100644 --- a/src/drivers/i2c/tpm/tis.c +++ b/src/drivers/i2c/tpm/tis.c @@ -26,7 +26,7 @@ #include "tpm.h" /* global structure for tpm chip data */ -static struct tpm_chip g_chip; +static struct tpm_chip chip; #define TPM_CMD_COUNT_BYTE 2 #define TPM_CMD_ORDINAL_BYTE 6 @@ -35,15 +35,15 @@ int tis_open(void) { int rc; - if (g_chip.is_open) { + if (chip.is_open) { printk(BIOS_DEBUG, "tis_open() called twice.\n"); return -1; } - rc = tpm_vendor_init(&g_chip, CONFIG_DRIVER_TPM_I2C_BUS, + rc = tpm_vendor_init(&chip, CONFIG_DRIVER_TPM_I2C_BUS, CONFIG_DRIVER_TPM_I2C_ADDR); if (rc < 0) - g_chip.is_open = 0; + chip.is_open = 0; if (rc) return -1; @@ -53,9 +53,9 @@ int tis_open(void) int tis_close(void) { - if (g_chip.is_open) { - tpm_vendor_cleanup(&g_chip); - g_chip.is_open = 0; + if (chip.is_open) { + tpm_vendor_cleanup(&chip); + chip.is_open = 0; } return 0; @@ -76,7 +76,7 @@ static ssize_t tpm_transmit(const uint8_t *sbuf, size_t sbufsiz, void *rbuf, memcpy(&count, sbuf + TPM_CMD_COUNT_BYTE, sizeof(count)); count = be32_to_cpu(count); - if (!g_chip.vendor.send || !g_chip.vendor.status || !g_chip.vendor.cancel) + if (!chip.vendor.send || !chip.vendor.status || !chip.vendor.cancel) return -1; if (count == 0) { @@ -89,8 +89,8 @@ static ssize_t tpm_transmit(const uint8_t *sbuf, size_t sbufsiz, void *rbuf, return -1; } - ASSERT(g_chip.vendor.send); - rc = g_chip.vendor.send(&g_chip, (uint8_t *) sbuf, count); + ASSERT(chip.vendor.send); + rc = chip.vendor.send(&chip, (uint8_t *) sbuf, count); if (rc < 0) { printk(BIOS_DEBUG, "tpm_transmit: tpm_send error\n"); goto out; @@ -98,14 +98,14 @@ static ssize_t tpm_transmit(const uint8_t *sbuf, size_t sbufsiz, void *rbuf, int timeout = 2 * 60 * 1000; /* two minutes timeout */ while (timeout) { - ASSERT(g_chip.vendor.status); - uint8_t status = g_chip.vendor.status(&g_chip); - if ((status & g_chip.vendor.req_complete_mask) == - g_chip.vendor.req_complete_val) { + ASSERT(chip.vendor.status); + uint8_t status = chip.vendor.status(&chip); + if ((status & chip.vendor.req_complete_mask) == + chip.vendor.req_complete_val) { goto out_recv; } - if (status == g_chip.vendor.req_canceled) { + if (status == chip.vendor.req_canceled) { printk(BIOS_DEBUG, "tpm_transmit: Operation Canceled\n"); rc = -1; @@ -115,15 +115,15 @@ static ssize_t tpm_transmit(const uint8_t *sbuf, size_t sbufsiz, void *rbuf, timeout--; } - ASSERT(g_chip.vendor.cancel); - g_chip.vendor.cancel(&g_chip); + ASSERT(chip.vendor.cancel); + chip.vendor.cancel(&chip); printk(BIOS_DEBUG, "tpm_transmit: Operation Timed out\n"); rc = -1; //ETIME; goto out; out_recv: - rc = g_chip.vendor.recv(&g_chip, (uint8_t *) rbuf, rbufsiz); + rc = chip.vendor.recv(&chip, (uint8_t *) rbuf, rbufsiz); if (rc < 0) printk(BIOS_DEBUG, "tpm_transmit: tpm_recv: error %d\n", rc); out: diff --git a/src/drivers/i2c/tpm/tpm.c b/src/drivers/i2c/tpm/tpm.c index 71641d0edc..009227eb36 100644 --- a/src/drivers/i2c/tpm/tpm.c +++ b/src/drivers/i2c/tpm/tpm.c @@ -80,7 +80,7 @@ struct tpm_inf_dev { enum i2c_chip_type chip_type; }; -static struct tpm_inf_dev g_tpm_dev; +static struct tpm_inf_dev tpm_dev; /* * iic_tpm_read() - read from TPM register @@ -101,20 +101,20 @@ static int iic_tpm_read(uint8_t addr, uint8_t *buffer, size_t len) int rc; int count; - if (g_tpm_dev.addr == 0) + if (tpm_dev.addr == 0) return -1; - switch (g_tpm_dev.chip_type) { + switch (tpm_dev.chip_type) { case SLB9635: case UNKNOWN: /* slb9635 protocol should work in both cases */ for (count = 0; count < MAX_COUNT; count++) { - rc = i2c_write_raw(g_tpm_dev.bus, g_tpm_dev.addr, + rc = i2c_write_raw(tpm_dev.bus, tpm_dev.addr, &addr, 1); if (rc == 0) break; /* success, break to skip sleep */ - udelay(g_tpm_dev.sleep_short); + udelay(tpm_dev.sleep_short); } if (rc) @@ -125,8 +125,8 @@ static int iic_tpm_read(uint8_t addr, uint8_t *buffer, size_t len) * retrieving the data */ for (count = 0; count < MAX_COUNT; count++) { - udelay(g_tpm_dev.sleep_short); - rc = i2c_read_raw(g_tpm_dev.bus, g_tpm_dev.addr, + udelay(tpm_dev.sleep_short); + rc = i2c_read_raw(tpm_dev.bus, tpm_dev.addr, buffer, len); if (rc == 0) break; /* success, break to skip sleep */ @@ -142,23 +142,23 @@ static int iic_tpm_read(uint8_t addr, uint8_t *buffer, size_t len) * retries should usually not be needed, but are kept just to * be safe on the safe side. */ - struct i2c_msg aseg = { .flags = 0, .slave = g_tpm_dev.addr, + struct i2c_msg aseg = { .flags = 0, .slave = tpm_dev.addr, .buf = &addr, .len = 1 }; struct i2c_msg dseg = { .flags = I2C_M_RD, - .slave = g_tpm_dev.addr, + .slave = tpm_dev.addr, .buf = buffer, .len = len }; for (count = 0; count < MAX_COUNT; count++) { - rc = i2c_transfer(g_tpm_dev.bus, &aseg, 1) || - i2c_transfer(g_tpm_dev.bus, &dseg, 1); + rc = i2c_transfer(tpm_dev.bus, &aseg, 1) || + i2c_transfer(tpm_dev.bus, &dseg, 1); if (rc == 0) break; /* break here to skip sleep */ - udelay(g_tpm_dev.sleep_short); + udelay(tpm_dev.sleep_short); } } } /* take care of 'guard time' */ - udelay(g_tpm_dev.sleep_short); + udelay(tpm_dev.sleep_short); if (rc) return -1; @@ -179,14 +179,14 @@ static int iic_tpm_write_generic(uint8_t addr, uint8_t *buffer, size_t len, } /* prepare send buffer */ - g_tpm_dev.buf[0] = addr; - memcpy(&(g_tpm_dev.buf[1]), buffer, len); + tpm_dev.buf[0] = addr; + memcpy(&(tpm_dev.buf[1]), buffer, len); - if (g_tpm_dev.addr == 0) + if (tpm_dev.addr == 0) return -1; for (count = 0; count < max_count; count++) { - rc = i2c_write_raw(g_tpm_dev.bus, g_tpm_dev.addr, - g_tpm_dev.buf, len + 1); + rc = i2c_write_raw(tpm_dev.bus, tpm_dev.addr, + tpm_dev.buf, len + 1); if (rc == 0) break; /* success, break to skip sleep */ @@ -194,7 +194,7 @@ static int iic_tpm_write_generic(uint8_t addr, uint8_t *buffer, size_t len, } /* take care of 'guard time' */ - udelay(g_tpm_dev.sleep_short); + udelay(tpm_dev.sleep_short); if (rc) return -1; @@ -219,8 +219,8 @@ static int iic_tpm_write_generic(uint8_t addr, uint8_t *buffer, size_t len, */ static int iic_tpm_write(uint8_t addr, uint8_t *buffer, size_t len) { - return iic_tpm_write_generic(addr, buffer, len, g_tpm_dev.sleep_short, - MAX_COUNT); + return iic_tpm_write_generic(addr, buffer, len, tpm_dev.sleep_short, + MAX_COUNT); } /* @@ -229,8 +229,8 @@ static int iic_tpm_write(uint8_t addr, uint8_t *buffer, size_t len) * */ static int iic_tpm_write_long(uint8_t addr, uint8_t *buffer, size_t len) { - return iic_tpm_write_generic(addr, buffer, len, g_tpm_dev.sleep_long, - MAX_COUNT_LONG); + return iic_tpm_write_generic(addr, buffer, len, tpm_dev.sleep_long, + MAX_COUNT_LONG); } static int check_locality(struct tpm_chip *chip, int loc) @@ -479,11 +479,11 @@ int tpm_vendor_probe(unsigned int bus, uint32_t addr) int ret; long sw_run_duration = SLEEP_DURATION_PROBE_MS; - g_tpm_dev.chip_type = UNKNOWN; - g_tpm_dev.bus = bus; - g_tpm_dev.addr = addr; - g_tpm_dev.sleep_short = SLEEP_DURATION; - g_tpm_dev.sleep_long = SLEEP_DURATION_LONG; + tpm_dev.chip_type = UNKNOWN; + tpm_dev.bus = bus; + tpm_dev.addr = addr; + tpm_dev.sleep_short = SLEEP_DURATION; + tpm_dev.sleep_long = SLEEP_DURATION_LONG; /* * Probe TPM. Check if the TPM_ACCESS register's ValidSts bit is set(1) @@ -522,11 +522,11 @@ int tpm_vendor_init(struct tpm_chip *chip, unsigned int bus, uint32_t dev_addr) return -1; } - g_tpm_dev.chip_type = UNKNOWN; - g_tpm_dev.bus = bus; - g_tpm_dev.addr = dev_addr; - g_tpm_dev.sleep_short = SLEEP_DURATION; - g_tpm_dev.sleep_long = SLEEP_DURATION_LONG; + tpm_dev.chip_type = UNKNOWN; + tpm_dev.bus = bus; + tpm_dev.addr = dev_addr; + tpm_dev.sleep_short = SLEEP_DURATION; + tpm_dev.sleep_long = SLEEP_DURATION_LONG; memset(&chip->vendor, 0, sizeof(struct tpm_vendor_specific)); chip->is_open = 1; @@ -547,9 +547,9 @@ int tpm_vendor_init(struct tpm_chip *chip, unsigned int bus, uint32_t dev_addr) goto out_err; if (vendor == TPM_TIS_I2C_DID_VID_9645) { - g_tpm_dev.chip_type = SLB9645; + tpm_dev.chip_type = SLB9645; } else if (be32_to_cpu(vendor) == TPM_TIS_I2C_DID_VID_9635) { - g_tpm_dev.chip_type = SLB9635; + tpm_dev.chip_type = SLB9635; } else { printk(BIOS_DEBUG, "Vendor ID 0x%08x not recognized.\n", vendor); @@ -557,8 +557,8 @@ int tpm_vendor_init(struct tpm_chip *chip, unsigned int bus, uint32_t dev_addr) } printk(BIOS_DEBUG, "I2C TPM %u:%02x (chip type %s device-id 0x%X)\n", - g_tpm_dev.bus, g_tpm_dev.addr, - chip_name[g_tpm_dev.chip_type], vendor >> 16); + tpm_dev.bus, tpm_dev.addr, + chip_name[tpm_dev.chip_type], vendor >> 16); /* * A timeout query to TPM can be placed here. diff --git a/src/drivers/pc80/pc/i8254.c b/src/drivers/pc80/pc/i8254.c index 9d23d4697e..0b04b393e4 100644 --- a/src/drivers/pc80/pc/i8254.c +++ b/src/drivers/pc80/pc/i8254.c @@ -106,19 +106,19 @@ bad_ctc: } #if CONFIG(UNKNOWN_TSC_RATE) -static u32 g_timer_tsc; +static u32 timer_tsc; unsigned long tsc_freq_mhz(void) { - if (g_timer_tsc > 0) - return g_timer_tsc; + if (timer_tsc > 0) + return timer_tsc; - g_timer_tsc = calibrate_tsc_with_pit(); + timer_tsc = calibrate_tsc_with_pit(); /* Set some semi-ridiculous rate if approximation fails. */ - if (g_timer_tsc == 0) - g_timer_tsc = 5000; + if (timer_tsc == 0) + timer_tsc = 5000; - return g_timer_tsc; + return timer_tsc; } #endif diff --git a/src/drivers/spi/flashconsole.c b/src/drivers/spi/flashconsole.c index c56bf52d92..98f3cb4796 100644 --- a/src/drivers/spi/flashconsole.c +++ b/src/drivers/spi/flashconsole.c @@ -22,11 +22,11 @@ #define LINE_BUFFER_SIZE 128 #define READ_BUFFER_SIZE 0x100 -static const struct region_device *g_rdev_ptr; -static struct region_device g_rdev; -static uint8_t g_line_buffer[LINE_BUFFER_SIZE]; -static size_t g_offset; -static size_t g_line_offset; +static const struct region_device *rdev_ptr; +static struct region_device rdev; +static uint8_t line_buffer[LINE_BUFFER_SIZE]; +static size_t offset; +static size_t line_offset; void flashconsole_init(void) { @@ -36,11 +36,11 @@ void flashconsole_init(void) size_t len = READ_BUFFER_SIZE; size_t i; - if (fmap_locate_area_as_rdev_rw("CONSOLE", &g_rdev)) { + if (fmap_locate_area_as_rdev_rw("CONSOLE", &rdev)) { printk(BIOS_INFO, "Can't find 'CONSOLE' area in FMAP\n"); return; } - size = region_device_sz(&g_rdev); + size = region_device_sz(&rdev); /* * We need to check the region until we find a 0xff indicating @@ -56,7 +56,7 @@ void flashconsole_init(void) // Fill the buffer on first iteration if (i == 0) { len = min(READ_BUFFER_SIZE, size - offset); - if (rdev_readat(&g_rdev, buffer, offset, len) != len) + if (rdev_readat(&rdev, buffer, offset, len) != len) return; } if (buffer[i] == 0xff) { @@ -75,29 +75,29 @@ void flashconsole_init(void) return; } - g_offset = offset; - g_rdev_ptr = &g_rdev; + offset = offset; + rdev_ptr = &rdev; } void flashconsole_tx_byte(unsigned char c) { - if (!g_rdev_ptr) + if (!rdev_ptr) return; - size_t region_size = region_device_sz(g_rdev_ptr); + size_t region_size = region_device_sz(rdev_ptr); - g_line_buffer[g_line_offset++] = c; + line_buffer[line_offset++] = c; - if (g_line_offset >= LINE_BUFFER_SIZE || - g_offset + g_line_offset >= region_size || c == '\n') { + if (line_offset >= LINE_BUFFER_SIZE || + offset + line_offset >= region_size || c == '\n') { flashconsole_tx_flush(); } } void flashconsole_tx_flush(void) { - size_t offset = g_offset; - size_t len = g_line_offset; + size_t offset = offset; + size_t len = line_offset; size_t region_size; static int busy; @@ -107,23 +107,23 @@ void flashconsole_tx_flush(void) if (busy) return; - if (!g_rdev_ptr) + if (!rdev_ptr) return; busy = 1; - region_size = region_device_sz(g_rdev_ptr); + region_size = region_device_sz(rdev_ptr); if (offset + len >= region_size) len = region_size - offset; - if (rdev_writeat(&g_rdev, g_line_buffer, offset, len) != len) + if (rdev_writeat(&rdev, line_buffer, offset, len) != len) return; // If the region is full, stop future write attempts if (offset + len >= region_size) return; - g_offset = offset + len; - g_line_offset = 0; + offset = offset + len; + line_offset = 0; busy = 0; } diff --git a/src/drivers/spi/tpm/tpm.c b/src/drivers/spi/tpm/tpm.c index d3d36c9160..62d1bbae55 100644 --- a/src/drivers/spi/tpm/tpm.c +++ b/src/drivers/spi/tpm/tpm.c @@ -39,10 +39,10 @@ #define CR50_TIMEOUT_INIT_MS 30000 /* Very long timeout for TPM init */ /* SPI slave structure for TPM device. */ -static struct spi_slave g_spi_slave; +static struct spi_slave spi_slave; /* Cached TPM device identification. */ -static struct tpm2_info g_tpm_info; +static struct tpm2_info tpm_info; /* * TODO(vbendeb): make CONFIG_DEBUG_TPM an int to allow different level of @@ -60,7 +60,7 @@ typedef struct { void tpm2_get_info(struct tpm2_info *info) { - *info = g_tpm_info; + *info = tpm_info; } __weak int tis_plat_irq_status(void) @@ -133,9 +133,9 @@ static int start_transaction(int read_write, size_t bytes, unsigned int addr) if (wakeup_needed) { /* Just in case Cr50 is asleep. */ - spi_claim_bus(&g_spi_slave); + spi_claim_bus(&spi_slave); udelay(1); - spi_release_bus(&g_spi_slave); + spi_release_bus(&spi_slave); udelay(100); } @@ -158,7 +158,7 @@ static int start_transaction(int read_write, size_t bytes, unsigned int addr) header.body[i + 1] = (addr >> (8 * (2 - i))) & 0xff; /* CS assert wakes up the slave. */ - spi_claim_bus(&g_spi_slave); + spi_claim_bus(&spi_slave); /* * The TCG TPM over SPI specification introduces the notion of SPI @@ -185,7 +185,7 @@ static int start_transaction(int read_write, size_t bytes, unsigned int addr) * to require to stall the master, this would present an issue. * crosbug.com/p/52132 has been opened to track this. */ - spi_xfer(&g_spi_slave, header.body, sizeof(header.body), NULL, 0); + spi_xfer(&spi_slave, header.body, sizeof(header.body), NULL, 0); /* * Now poll the bus until TPM removes the stall bit. Give it up to 100 @@ -196,10 +196,10 @@ static int start_transaction(int read_write, size_t bytes, unsigned int addr) do { if (stopwatch_expired(&sw)) { printk(BIOS_ERR, "TPM flow control failure\n"); - spi_release_bus(&g_spi_slave); + spi_release_bus(&spi_slave); return 0; } - spi_xfer(&g_spi_slave, NULL, 0, &byte, 1); + spi_xfer(&spi_slave, NULL, 0, &byte, 1); } while (!(byte & 1)); return 1; } @@ -267,7 +267,7 @@ static void trace_dump(const char *prefix, uint32_t reg, */ static void write_bytes(const void *buffer, size_t bytes) { - spi_xfer(&g_spi_slave, buffer, bytes, NULL, 0); + spi_xfer(&spi_slave, buffer, bytes, NULL, 0); } /* @@ -276,7 +276,7 @@ static void write_bytes(const void *buffer, size_t bytes) */ static void read_bytes(void *buffer, size_t bytes) { - spi_xfer(&g_spi_slave, NULL, 0, buffer, bytes); + spi_xfer(&spi_slave, NULL, 0, buffer, bytes); } /* @@ -291,7 +291,7 @@ static int tpm2_write_reg(unsigned int reg_number, const void *buffer, size_t by if (!start_transaction(false, bytes, reg_number)) return 0; write_bytes(buffer, bytes); - spi_release_bus(&g_spi_slave); + spi_release_bus(&spi_slave); return 1; } @@ -309,7 +309,7 @@ static int tpm2_read_reg(unsigned int reg_number, void *buffer, size_t bytes) return 0; } read_bytes(buffer, bytes); - spi_release_bus(&g_spi_slave); + spi_release_bus(&spi_slave); trace_dump("R", reg_number, bytes, buffer, 0); return 1; } @@ -417,7 +417,7 @@ int tpm2_init(struct spi_slave *spi_if) uint8_t cmd; int retries; - memcpy(&g_spi_slave, spi_if, sizeof(*spi_if)); + memcpy(&spi_slave, spi_if, sizeof(*spi_if)); /* clear any pending IRQs */ tis_plat_irq_status(); @@ -474,15 +474,15 @@ int tpm2_init(struct spi_slave *spi_if) * structure. */ tpm2_read_reg(TPM_RID_REG, &cmd, sizeof(cmd)); - g_tpm_info.vendor_id = did_vid & 0xffff; - g_tpm_info.device_id = did_vid >> 16; - g_tpm_info.revision = cmd; + tpm_info.vendor_id = did_vid & 0xffff; + tpm_info.device_id = did_vid >> 16; + tpm_info.revision = cmd; printk(BIOS_INFO, "Connected to device vid:did:rid of %4.4x:%4.4x:%2.2x\n", - g_tpm_info.vendor_id, g_tpm_info.device_id, g_tpm_info.revision); + tpm_info.vendor_id, tpm_info.device_id, tpm_info.revision); /* Let's report device FW version if available. */ - if (g_tpm_info.vendor_id == 0x1ae0) { + if (tpm_info.vendor_id == 0x1ae0) { int chunk_count = 0; size_t chunk_size; /* @@ -611,7 +611,7 @@ size_t tpm2_process_command(const void *tpm2_command, size_t command_size, const int HEADER_SIZE = 6; /* Do not try using an uninitialized TPM. */ - if (!g_tpm_info.vendor_id) + if (!tpm_info.vendor_id) return 0; /* Skip the two byte tag, read the size field. */ diff --git a/src/drivers/vpd/vpd.c b/src/drivers/vpd/vpd.c index b81a719176..ab77a01bff 100644 --- a/src/drivers/vpd/vpd.c +++ b/src/drivers/vpd/vpd.c @@ -23,7 +23,7 @@ struct vpd_gets_arg { int matched; }; -struct vpd_blob g_vpd_blob; +struct vpd_blob vpd_blob; /* * returns the size of data in a VPD 2.0 formatted fmap region, or 0. @@ -85,10 +85,10 @@ static void vpd_get_blob(void) if (ro_vpd_size == 0 && rw_vpd_size == 0) return; - g_vpd_blob.ro_base = NULL; - g_vpd_blob.ro_size = 0; - g_vpd_blob.rw_base = NULL; - g_vpd_blob.rw_size = 0; + vpd_blob.ro_base = NULL; + vpd_blob.ro_size = 0; + vpd_blob.rw_base = NULL; + vpd_blob.rw_size = 0; struct region_device vpd; @@ -101,9 +101,9 @@ static void vpd_get_blob(void) } rdev_chain(&vpd, &vpd, GOOGLE_VPD_2_0_OFFSET, region_device_sz(&vpd) - GOOGLE_VPD_2_0_OFFSET); - g_vpd_blob.ro_base = (uint8_t *)(rdev_mmap_full(&vpd) + + vpd_blob.ro_base = (uint8_t *)(rdev_mmap_full(&vpd) + sizeof(struct google_vpd_info)); - g_vpd_blob.ro_size = ro_vpd_size; + vpd_blob.ro_size = ro_vpd_size; } if (rw_vpd_size) { if (fmap_locate_area_as_rdev("RW_VPD", &vpd)) { @@ -114,19 +114,19 @@ static void vpd_get_blob(void) } rdev_chain(&vpd, &vpd, GOOGLE_VPD_2_0_OFFSET, region_device_sz(&vpd) - GOOGLE_VPD_2_0_OFFSET); - g_vpd_blob.rw_base = (uint8_t *)(rdev_mmap_full(&vpd) + + vpd_blob.rw_base = (uint8_t *)(rdev_mmap_full(&vpd) + sizeof(struct google_vpd_info)); - g_vpd_blob.rw_size = rw_vpd_size; + vpd_blob.rw_size = rw_vpd_size; } - g_vpd_blob.initialized = true; + vpd_blob.initialized = true; } const struct vpd_blob *vpd_load_blob(void) { - if (g_vpd_blob.initialized == false) + if (vpd_blob.initialized == false) vpd_get_blob(); - return &g_vpd_blob; + return &vpd_blob; } static int vpd_gets_callback(const uint8_t *key, uint32_t key_len, diff --git a/src/soc/intel/common/block/cse/cse.c b/src/soc/intel/common/block/cse/cse.c index 5eb37611f5..99218253ae 100644 --- a/src/soc/intel/common/block/cse/cse.c +++ b/src/soc/intel/common/block/cse/cse.c @@ -88,7 +88,7 @@ static struct cse_device { uintptr_t sec_bar; -} g_cse; +} cse; /* * Initialize the device with provided temporary BAR. If BAR is 0 use a @@ -105,7 +105,7 @@ void heci_init(uintptr_t tempbar) u8 pcireg; /* Assume it is already initialized, nothing else to do */ - if (g_cse.sec_bar) + if (cse.sec_bar) return; /* Use default pre-ram bar */ @@ -127,7 +127,7 @@ void heci_init(uintptr_t tempbar) pcireg |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY; pci_write_config8(dev, PCI_COMMAND, pcireg); - g_cse.sec_bar = tempbar; + cse.sec_bar = tempbar; } /* Get HECI BAR 0 from PCI configuration space */ @@ -147,17 +147,17 @@ static uint32_t get_cse_bar(void) static uint32_t read_bar(uint32_t offset) { /* Reach PCI config space to get BAR in case CAR global not available */ - if (!g_cse.sec_bar) - g_cse.sec_bar = get_cse_bar(); - return read32((void *)(g_cse.sec_bar + offset)); + if (!cse.sec_bar) + cse.sec_bar = get_cse_bar(); + return read32((void *)(cse.sec_bar + offset)); } static void write_bar(uint32_t offset, uint32_t val) { /* Reach PCI config space to get BAR in case CAR global not available */ - if (!g_cse.sec_bar) - g_cse.sec_bar = get_cse_bar(); - return write32((void *)(g_cse.sec_bar + offset), val); + if (!cse.sec_bar) + cse.sec_bar = get_cse_bar(); + return write32((void *)(cse.sec_bar + offset), val); } static uint32_t read_cse_csr(void) @@ -725,7 +725,7 @@ int send_hmrfpo_get_status_msg(void) static void update_sec_bar(struct device *dev) { - g_cse.sec_bar = find_resource(dev, PCI_BASE_ADDRESS_0)->base; + cse.sec_bar = find_resource(dev, PCI_BASE_ADDRESS_0)->base; } static void cse_set_resources(struct device *dev) diff --git a/src/soc/nvidia/tegra/i2c.c b/src/soc/nvidia/tegra/i2c.c index 0e9553c8ed..3ca0e13fa4 100644 --- a/src/soc/nvidia/tegra/i2c.c +++ b/src/soc/nvidia/tegra/i2c.c @@ -193,7 +193,7 @@ int platform_i2c_transfer(unsigned int bus, struct i2c_msg *segments, int count) struct i2c_msg *seg = segments; int i; - if (bus >= g_num_i2c_buses) { + if (bus >= num_i2c_buses) { printk(BIOS_ERR, "%s: ERROR: invalid I2C bus (%u)\n", __func__, bus); return -1; @@ -212,7 +212,7 @@ void i2c_init(unsigned int bus) { struct tegra_i2c_regs *regs; - if (bus >= g_num_i2c_buses) { + if (bus >= num_i2c_buses) { printk(BIOS_ERR, "%s: ERROR: invalid I2C bus (%u)\n", __func__, bus); return; diff --git a/src/soc/nvidia/tegra/i2c.h b/src/soc/nvidia/tegra/i2c.h index a2bf9508be..c32450b824 100644 --- a/src/soc/nvidia/tegra/i2c.h +++ b/src/soc/nvidia/tegra/i2c.h @@ -168,6 +168,6 @@ struct tegra_i2c_regs { }; check_member(tegra_i2c_regs, config_load, 0x8C); -extern unsigned int g_num_i2c_buses; +extern unsigned int num_i2c_buses; #endif /* __SOC_NVIDIA_TEGRA_I2C_H__ */ diff --git a/src/soc/nvidia/tegra124/i2c.c b/src/soc/nvidia/tegra124/i2c.c index ee339bbe48..0d65b9a018 100644 --- a/src/soc/nvidia/tegra124/i2c.c +++ b/src/soc/nvidia/tegra124/i2c.c @@ -50,4 +50,4 @@ struct tegra_i2c_bus_info tegra_i2c_info[] = { } }; -unsigned int g_num_i2c_buses = ARRAY_SIZE(tegra_i2c_info); +unsigned int num_i2c_buses = ARRAY_SIZE(tegra_i2c_info); diff --git a/src/soc/nvidia/tegra210/i2c.c b/src/soc/nvidia/tegra210/i2c.c index 34aae5a639..4764b78303 100644 --- a/src/soc/nvidia/tegra210/i2c.c +++ b/src/soc/nvidia/tegra210/i2c.c @@ -50,4 +50,4 @@ struct tegra_i2c_bus_info tegra_i2c_info[] = { } }; -unsigned int g_num_i2c_buses = ARRAY_SIZE(tegra_i2c_info); +unsigned int num_i2c_buses = ARRAY_SIZE(tegra_i2c_info); diff --git a/src/southbridge/intel/common/spi.c b/src/southbridge/intel/common/spi.c index 4974e08c65..cf678176ab 100644 --- a/src/southbridge/intel/common/spi.c +++ b/src/southbridge/intel/common/spi.c @@ -111,7 +111,7 @@ struct ich_spi_controller { uint8_t fpr_max; }; -static struct ich_spi_controller g_cntlr; +static struct ich_spi_controller cntlr; enum { SPIS_SCIP = 0x0001, @@ -260,9 +260,9 @@ static void ich_set_bbar(uint32_t minaddr) uint32_t ichspi_bbar; minaddr &= bbar_mask; - ichspi_bbar = readl_(g_cntlr.bbar) & ~bbar_mask; + ichspi_bbar = readl_(cntlr.bbar) & ~bbar_mask; ichspi_bbar |= minaddr; - writel_(ichspi_bbar, g_cntlr.bbar); + writel_(ichspi_bbar, cntlr.bbar); } #if CONFIG(SOUTHBRIDGE_INTEL_I82801GX) @@ -305,42 +305,42 @@ void spi_init(void) if (CONFIG(SOUTHBRIDGE_INTEL_I82801GX)) { ich7_spi = get_spi_bar(dev); - g_cntlr.ich7_spi = ich7_spi; - g_cntlr.opmenu = ich7_spi->opmenu; - g_cntlr.menubytes = sizeof(ich7_spi->opmenu); - g_cntlr.optype = &ich7_spi->optype; - g_cntlr.addr = &ich7_spi->spia; - g_cntlr.data = (uint8_t *)ich7_spi->spid; - g_cntlr.databytes = sizeof(ich7_spi->spid); - g_cntlr.status = (uint8_t *)&ich7_spi->spis; - g_cntlr.control = &ich7_spi->spic; - g_cntlr.bbar = &ich7_spi->bbar; - g_cntlr.preop = &ich7_spi->preop; - g_cntlr.fpr = &ich7_spi->pbr[0]; - g_cntlr.fpr_max = 3; + cntlr.ich7_spi = ich7_spi; + cntlr.opmenu = ich7_spi->opmenu; + cntlr.menubytes = sizeof(ich7_spi->opmenu); + cntlr.optype = &ich7_spi->optype; + cntlr.addr = &ich7_spi->spia; + cntlr.data = (uint8_t *)ich7_spi->spid; + cntlr.databytes = sizeof(ich7_spi->spid); + cntlr.status = (uint8_t *)&ich7_spi->spis; + cntlr.control = &ich7_spi->spic; + cntlr.bbar = &ich7_spi->bbar; + cntlr.preop = &ich7_spi->preop; + cntlr.fpr = &ich7_spi->pbr[0]; + cntlr.fpr_max = 3; } else { ich9_spi = get_spi_bar(dev); - g_cntlr.ich9_spi = ich9_spi; + cntlr.ich9_spi = ich9_spi; hsfs = readw_(&ich9_spi->hsfs); - g_cntlr.hsfs = hsfs; - g_cntlr.opmenu = ich9_spi->opmenu; - g_cntlr.menubytes = sizeof(ich9_spi->opmenu); - g_cntlr.optype = &ich9_spi->optype; - g_cntlr.addr = &ich9_spi->faddr; - g_cntlr.data = (uint8_t *)ich9_spi->fdata; - g_cntlr.databytes = sizeof(ich9_spi->fdata); - g_cntlr.status = &ich9_spi->ssfs; - g_cntlr.control = (uint16_t *)ich9_spi->ssfc; - g_cntlr.bbar = &ich9_spi->bbar; - g_cntlr.preop = &ich9_spi->preop; - g_cntlr.fpr = &ich9_spi->pr[0]; - g_cntlr.fpr_max = 5; + cntlr.hsfs = hsfs; + cntlr.opmenu = ich9_spi->opmenu; + cntlr.menubytes = sizeof(ich9_spi->opmenu); + cntlr.optype = &ich9_spi->optype; + cntlr.addr = &ich9_spi->faddr; + cntlr.data = (uint8_t *)ich9_spi->fdata; + cntlr.databytes = sizeof(ich9_spi->fdata); + cntlr.status = &ich9_spi->ssfs; + cntlr.control = (uint16_t *)ich9_spi->ssfc; + cntlr.bbar = &ich9_spi->bbar; + cntlr.preop = &ich9_spi->preop; + cntlr.fpr = &ich9_spi->pr[0]; + cntlr.fpr_max = 5; - if (g_cntlr.hsfs & HSFS_FDV) { + if (cntlr.hsfs & HSFS_FDV) { writel_(4, &ich9_spi->fdoc); - g_cntlr.flmap0 = readl_(&ich9_spi->fdod); + cntlr.flmap0 = readl_(&ich9_spi->fdod); writel_(0x1000, &ich9_spi->fdoc); - g_cntlr.flcomp = readl_(&ich9_spi->fdod); + cntlr.flcomp = readl_(&ich9_spi->fdod); } } @@ -358,9 +358,9 @@ void spi_init(void) static int spi_locked(void) { if (CONFIG(SOUTHBRIDGE_INTEL_I82801GX)) { - return !!(readw_(&g_cntlr.ich7_spi->spis) & HSFS_FLOCKDN); + return !!(readw_(&cntlr.ich7_spi->spis) & HSFS_FLOCKDN); } else { - return !!(readw_(&g_cntlr.ich9_spi->hsfs) & HSFS_FLOCKDN); + return !!(readw_(&cntlr.ich9_spi->hsfs) & HSFS_FLOCKDN); } } @@ -436,10 +436,10 @@ static int spi_setup_opcode(spi_transaction *trans) spi_use_out(trans, 1); if (!spi_locked()) { /* The lock is off, so just use index 0. */ - writeb_(trans->opcode, g_cntlr.opmenu); - optypes = readw_(g_cntlr.optype); + writeb_(trans->opcode, cntlr.opmenu); + optypes = readw_(cntlr.optype); optypes = (optypes & 0xfffc) | (trans->type & 0x3); - writew_(optypes, g_cntlr.optype); + writew_(optypes, cntlr.optype); return 0; } @@ -451,7 +451,7 @@ static int spi_setup_opcode(spi_transaction *trans) if (trans->opcode == SPI_OPCODE_WREN) return 0; - read_reg(g_cntlr.opmenu, opmenu, sizeof(opmenu)); + read_reg(cntlr.opmenu, opmenu, sizeof(opmenu)); for (opcode_index = 0; opcode_index < ARRAY_SIZE(opmenu); opcode_index++) { if (opmenu[opcode_index] == trans->opcode) break; @@ -463,7 +463,7 @@ static int spi_setup_opcode(spi_transaction *trans) return -1; } - optypes = readw_(g_cntlr.optype); + optypes = readw_(cntlr.optype); optype = (optypes >> (opcode_index * 2)) & 0x3; if (trans->type == SPI_OPCODE_TYPE_WRITE_NO_ADDRESS && optype == SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS && @@ -512,10 +512,10 @@ static int ich_status_poll(u16 bitmask, int wait_til_set) u16 status = 0; while (timeout--) { - status = readw_(g_cntlr.status); + status = readw_(cntlr.status); if (wait_til_set ^ ((status & bitmask) == 0)) { if (wait_til_set) - writew_((status & bitmask), g_cntlr.status); + writew_((status & bitmask), cntlr.status); return status; } udelay(10); @@ -528,9 +528,9 @@ static int ich_status_poll(u16 bitmask, int wait_til_set) static int spi_is_multichip(void) { - if (!(g_cntlr.hsfs & HSFS_FDV)) + if (!(cntlr.hsfs & HSFS_FDV)) return 0; - return !!((g_cntlr.flmap0 >> 8) & 3); + return !!((cntlr.flmap0 >> 8) & 3); } static int spi_ctrlr_xfer(const struct spi_slave *slave, const void *dout, @@ -561,7 +561,7 @@ static int spi_ctrlr_xfer(const struct spi_slave *slave, const void *dout, if (ich_status_poll(SPIS_SCIP, 0) == -1) return -1; - writew_(SPIS_CDS | SPIS_FCERR, g_cntlr.status); + writew_(SPIS_CDS | SPIS_FCERR, cntlr.status); spi_setup_type(&trans); if ((opcode_index = spi_setup_opcode(&trans)) < 0) @@ -576,7 +576,7 @@ static int spi_ctrlr_xfer(const struct spi_slave *slave, const void *dout, * issuing a transaction between WREN and DATA. */ if (!spi_locked()) - writew_(trans.opcode, g_cntlr.preop); + writew_(trans.opcode, cntlr.preop); return 0; } @@ -584,13 +584,13 @@ static int spi_ctrlr_xfer(const struct spi_slave *slave, const void *dout, control = SPIC_SCGO | ((opcode_index & 0x07) << 4); /* Issue atomic preop cycle if needed */ - if (readw_(g_cntlr.preop)) + if (readw_(cntlr.preop)) control |= SPIC_ACS; if (!trans.bytesout && !trans.bytesin) { /* SPI addresses are 24 bit only */ if (with_address) - writel_(trans.offset & 0x00FFFFFF, g_cntlr.addr); + writel_(trans.offset & 0x00FFFFFF, cntlr.addr); /* * This is a 'no data' command (like Write Enable), its @@ -598,7 +598,7 @@ static int spi_ctrlr_xfer(const struct spi_slave *slave, const void *dout, * spi_setup_opcode() above. Tell the chip to send the * command. */ - writew_(control, g_cntlr.control); + writew_(control, cntlr.control); /* wait for the result */ status = ich_status_poll(SPIS_CDS | SPIS_FCERR, 1); @@ -620,7 +620,7 @@ static int spi_ctrlr_xfer(const struct spi_slave *slave, const void *dout, * and followed by other SPI commands, and this sequence is controlled * by the SPI chip driver. */ - if (trans.bytesout > g_cntlr.databytes) { + if (trans.bytesout > cntlr.databytes) { printk(BIOS_DEBUG, "ICH SPI: Too much to write. Does your SPI chip driver use" " spi_crop_chunk()?\n"); return -1; @@ -634,28 +634,28 @@ static int spi_ctrlr_xfer(const struct spi_slave *slave, const void *dout, uint32_t data_length; /* SPI addresses are 24 bit only */ - writel_(trans.offset & 0x00FFFFFF, g_cntlr.addr); + writel_(trans.offset & 0x00FFFFFF, cntlr.addr); if (trans.bytesout) - data_length = min(trans.bytesout, g_cntlr.databytes); + data_length = min(trans.bytesout, cntlr.databytes); else - data_length = min(trans.bytesin, g_cntlr.databytes); + data_length = min(trans.bytesin, cntlr.databytes); /* Program data into FDATA0 to N */ if (trans.bytesout) { - write_reg(trans.out, g_cntlr.data, data_length); + write_reg(trans.out, cntlr.data, data_length); spi_use_out(&trans, data_length); if (with_address) trans.offset += data_length; } /* Add proper control fields' values */ - control &= ~((g_cntlr.databytes - 1) << 8); + control &= ~((cntlr.databytes - 1) << 8); control |= SPIC_DS; control |= (data_length - 1) << 8; /* write it */ - writew_(control, g_cntlr.control); + writew_(control, cntlr.control); /* Wait for Cycle Done Status or Flash Cycle Error. */ status = ich_status_poll(SPIS_CDS | SPIS_FCERR, 1); @@ -668,7 +668,7 @@ static int spi_ctrlr_xfer(const struct spi_slave *slave, const void *dout, } if (trans.bytesin) { - read_reg(g_cntlr.data, trans.in, data_length); + read_reg(cntlr.data, trans.in, data_length); spi_use_in(&trans, data_length); if (with_address) trans.offset += data_length; @@ -677,7 +677,7 @@ static int spi_ctrlr_xfer(const struct spi_slave *slave, const void *dout, spi_xfer_exit: /* Clear atomic preop now that xfer is done */ - writew_(0, g_cntlr.preop); + writew_(0, cntlr.preop); return 0; } @@ -685,9 +685,9 @@ spi_xfer_exit: /* Sets FLA in FADDR to (addr & 0x01FFFFFF) without touching other bits. */ static void ich_hwseq_set_addr(uint32_t addr) { - uint32_t addr_old = readl_(&g_cntlr.ich9_spi->faddr) & ~0x01FFFFFF; + uint32_t addr_old = readl_(&cntlr.ich9_spi->faddr) & ~0x01FFFFFF; - writel_((addr & 0x01FFFFFF) | addr_old, &g_cntlr.ich9_spi->faddr); + writel_((addr & 0x01FFFFFF) | addr_old, &cntlr.ich9_spi->faddr); } /* Polls for Cycle Done Status, Flash Cycle Error or timeout in 8 us intervals. @@ -701,17 +701,17 @@ static int ich_hwseq_wait_for_cycle_complete(unsigned int timeout, uint32_t addr; timeout /= 8; /* scale timeout duration to counter */ - while ((((hsfs = readw_(&g_cntlr.ich9_spi->hsfs)) & + while ((((hsfs = readw_(&cntlr.ich9_spi->hsfs)) & (HSFS_FDONE | HSFS_FCERR)) == 0) && --timeout) { udelay(8); } - writew_(readw_(&g_cntlr.ich9_spi->hsfs), &g_cntlr.ich9_spi->hsfs); + writew_(readw_(&cntlr.ich9_spi->hsfs), &cntlr.ich9_spi->hsfs); if (!timeout) { uint16_t hsfc; - addr = readl_(&g_cntlr.ich9_spi->faddr) & 0x01FFFFFF; - hsfc = readw_(&g_cntlr.ich9_spi->hsfc); + addr = readl_(&cntlr.ich9_spi->faddr) & 0x01FFFFFF; + hsfc = readw_(&cntlr.ich9_spi->hsfc); printk(BIOS_ERR, "Transaction timeout between offset 0x%08x and " "0x%08x (= 0x%08x + %d) HSFC=%x HSFS=%x!\n", addr, addr + len - 1, addr, len - 1, @@ -721,8 +721,8 @@ static int ich_hwseq_wait_for_cycle_complete(unsigned int timeout, if (hsfs & HSFS_FCERR) { uint16_t hsfc; - addr = readl_(&g_cntlr.ich9_spi->faddr) & 0x01FFFFFF; - hsfc = readw_(&g_cntlr.ich9_spi->hsfc); + addr = readl_(&cntlr.ich9_spi->faddr) & 0x01FFFFFF; + hsfc = readw_(&cntlr.ich9_spi->hsfc); printk(BIOS_ERR, "Transaction error between offset 0x%08x and " "0x%08x (= 0x%08x + %d) HSFC=%x HSFS=%x!\n", addr, addr + len - 1, addr, len - 1, @@ -758,17 +758,17 @@ static int ich_hwseq_erase(const struct spi_flash *flash, u32 offset, while (offset < end) { /* make sure FDONE, FCERR, AEL are cleared by writing 1 to them */ - writew_(readw_(&g_cntlr.ich9_spi->hsfs), &g_cntlr.ich9_spi->hsfs); + writew_(readw_(&cntlr.ich9_spi->hsfs), &cntlr.ich9_spi->hsfs); ich_hwseq_set_addr(offset); offset += erase_size; - hsfc = readw_(&g_cntlr.ich9_spi->hsfc); + hsfc = readw_(&cntlr.ich9_spi->hsfc); hsfc &= ~HSFC_FCYCLE; /* clear operation */ hsfc |= (0x3 << HSFC_FCYCLE_OFF); /* set erase operation */ hsfc |= HSFC_FGO; /* start */ - writew_(hsfc, &g_cntlr.ich9_spi->hsfc); + writew_(hsfc, &cntlr.ich9_spi->hsfc); if (ich_hwseq_wait_for_cycle_complete(timeout, len)) { printk(BIOS_ERR, "SF: Erase failed at %x\n", offset - erase_size); ret = -1; @@ -790,7 +790,7 @@ static void ich_read_data(uint8_t *data, int len) for (i = 0; i < len; i++) { if ((i % 4) == 0) - temp32 = readl_(g_cntlr.data + i); + temp32 = readl_(cntlr.data + i); data[i] = (temp32 >> ((i % 4) * 8)) & 0xff; } @@ -812,20 +812,20 @@ static int ich_hwseq_read(const struct spi_flash *flash, u32 addr, size_t len, } /* clear FDONE, FCERR, AEL by writing 1 to them (if they are set) */ - writew_(readw_(&g_cntlr.ich9_spi->hsfs), &g_cntlr.ich9_spi->hsfs); + writew_(readw_(&cntlr.ich9_spi->hsfs), &cntlr.ich9_spi->hsfs); while (len > 0) { - block_len = min(len, g_cntlr.databytes); + block_len = min(len, cntlr.databytes); if (block_len > (~addr & 0xff)) block_len = (~addr & 0xff) + 1; ich_hwseq_set_addr(addr); - hsfc = readw_(&g_cntlr.ich9_spi->hsfc); + hsfc = readw_(&cntlr.ich9_spi->hsfc); hsfc &= ~HSFC_FCYCLE; /* set read operation */ hsfc &= ~HSFC_FDBC; /* clear byte count */ /* set byte count */ hsfc |= (((block_len - 1) << HSFC_FDBC_OFF) & HSFC_FDBC); hsfc |= HSFC_FGO; /* start */ - writew_(hsfc, &g_cntlr.ich9_spi->hsfc); + writew_(hsfc, &cntlr.ich9_spi->hsfc); if (ich_hwseq_wait_for_cycle_complete(timeout, block_len)) return 1; @@ -857,11 +857,11 @@ static void ich_fill_data(const uint8_t *data, int len) temp32 |= ((uint32_t) data[i]) << ((i % 4) * 8); if ((i % 4) == 3) /* 32 bits are full, write them to regs. */ - writel_(temp32, g_cntlr.data + (i - (i % 4))); + writel_(temp32, cntlr.data + (i - (i % 4))); } i--; if ((i % 4) != 3) /* Write remaining data to regs. */ - writel_(temp32, g_cntlr.data + (i - (i % 4))); + writel_(temp32, cntlr.data + (i - (i % 4))); } static int ich_hwseq_write(const struct spi_flash *flash, u32 addr, size_t len, @@ -880,24 +880,24 @@ static int ich_hwseq_write(const struct spi_flash *flash, u32 addr, size_t len, } /* clear FDONE, FCERR, AEL by writing 1 to them (if they are set) */ - writew_(readw_(&g_cntlr.ich9_spi->hsfs), &g_cntlr.ich9_spi->hsfs); + writew_(readw_(&cntlr.ich9_spi->hsfs), &cntlr.ich9_spi->hsfs); while (len > 0) { - block_len = min(len, g_cntlr.databytes); + block_len = min(len, cntlr.databytes); if (block_len > (~addr & 0xff)) block_len = (~addr & 0xff) + 1; ich_hwseq_set_addr(addr); ich_fill_data(buf, block_len); - hsfc = readw_(&g_cntlr.ich9_spi->hsfc); + hsfc = readw_(&cntlr.ich9_spi->hsfc); hsfc &= ~HSFC_FCYCLE; /* clear operation */ hsfc |= (0x2 << HSFC_FCYCLE_OFF); /* set write operation */ hsfc &= ~HSFC_FDBC; /* clear byte count */ /* set byte count */ hsfc |= (((block_len - 1) << HSFC_FDBC_OFF) & HSFC_FDBC); hsfc |= HSFC_FGO; /* start */ - writew_(hsfc, &g_cntlr.ich9_spi->hsfc); + writew_(hsfc, &cntlr.ich9_spi->hsfc); if (ich_hwseq_wait_for_cycle_complete(timeout, block_len)) { printk(BIOS_ERR, "SF: write failure at %x\n", @@ -934,7 +934,7 @@ static int spi_flash_programmer_probe(const struct spi_slave *spi, flash->name = "Opaque HW-sequencing"; ich_hwseq_set_addr(0); - switch ((g_cntlr.hsfs >> 3) & 3) { + switch ((cntlr.hsfs >> 3) & 3) { case 0: flash->sector_size = 256; break; @@ -949,12 +949,12 @@ static int spi_flash_programmer_probe(const struct spi_slave *spi, break; } - flash->size = 1 << (19 + (g_cntlr.flcomp & 7)); + flash->size = 1 << (19 + (cntlr.flcomp & 7)); flash->ops = &spi_flash_ops; - if ((g_cntlr.hsfs & HSFS_FDV) && ((g_cntlr.flmap0 >> 8) & 3)) - flash->size += 1 << (19 + ((g_cntlr.flcomp >> 3) & 7)); + if ((cntlr.hsfs & HSFS_FDV) && ((cntlr.flmap0 >> 8) & 3)) + flash->size += 1 << (19 + ((cntlr.flcomp >> 3) & 7)); printk(BIOS_DEBUG, "flash size 0x%x bytes\n", flash->size); return 0; @@ -1008,16 +1008,16 @@ static int spi_flash_protect(const struct spi_flash *flash, int fpr; uint32_t *fpr_base; - fpr_base = g_cntlr.fpr; + fpr_base = cntlr.fpr; /* Find first empty FPR */ - for (fpr = 0; fpr < g_cntlr.fpr_max; fpr++) { + for (fpr = 0; fpr < cntlr.fpr_max; fpr++) { reg = read32(&fpr_base[fpr]); if (reg == 0) break; } - if (fpr == g_cntlr.fpr_max) { + if (fpr == cntlr.fpr_max) { printk(BIOS_ERR, "ERROR: No SPI FPR free!\n"); return -1; } @@ -1106,12 +1106,12 @@ void spi_finalize_ops(void) spi_opprefix = spi_config->opprefixes[0] | (spi_config->opprefixes[1] << 8); - writew_(spi_opprefix, g_cntlr.preop); + writew_(spi_opprefix, cntlr.preop); for (i = 0; i < ARRAY_SIZE(spi_config->ops); i++) { optype |= (spi_config->ops[i].type & 3) << (i * 2); - writeb_(spi_config->ops[i].op, &g_cntlr.opmenu[i]); + writeb_(spi_config->ops[i].op, &cntlr.opmenu[i]); } - writew_(optype, g_cntlr.optype); + writew_(optype, cntlr.optype); } __weak void intel_southbridge_override_spi(struct intel_swseq_spi_config *spi_config) From fdcc9ab317af2ae9cd69cb2490d3a4444180429a Mon Sep 17 00:00:00 2001 From: Gaggery Tsai Date: Mon, 4 Nov 2019 20:49:10 -0800 Subject: [PATCH 0487/1242] src/soc/intel: Add Cometlake-S and CMP-H skus This patch adds some sku support for CML-S CPU and CMP-H chips. According to doc #605546: CML-S (6+2) G0: A0650h CML-S (6+2) G1: A0653h CML-S (10+2, 8+2) P0: A0651h CML-S (6+2, 10+2) Q0/P1: A0654h CMP-H HM470: 068Dh CMP-H WM490: 068Eh CMP-H QM480: 068Ch CMP-H H470: 0684h CMP-H Z490: 0685h CMP-H Q470: 0687h TEST=Boot with CML-S (6+2) G1 + CMP-H WM490 and IDs are recognized Change-Id: I6bda09070ec330033eff95329448ace57e87144f Signed-off-by: Gaggery Tsai Reviewed-on: https://review.coreboot.org/c/coreboot/+/36684 Tested-by: build bot (Jenkins) Reviewed-by: Subrata Banik Reviewed-by: Angel Pons --- src/include/device/pci_ids.h | 20 ++++++++++++++++++- .../cannonlake/bootblock/report_platform.c | 20 +++++++++++++++++-- src/soc/intel/cannonlake/lpc.c | 3 ++- src/soc/intel/common/block/cpu/mp_init.c | 4 +++- .../block/include/intelblocks/mp_init.h | 4 +++- .../common/block/systemagent/systemagent.c | 4 +++- 6 files changed, 48 insertions(+), 7 deletions(-) diff --git a/src/include/device/pci_ids.h b/src/include/device/pci_ids.h index 0f96737f3b..b75e596d19 100644 --- a/src/include/device/pci_ids.h +++ b/src/include/device/pci_ids.h @@ -2769,6 +2769,14 @@ #define PCI_DEVICE_ID_INTEL_CMP_PREMIUM_U_LPC 0x0284 #define PCI_DEVICE_ID_INTEL_CMP_BASE_U_LPC 0x0285 #define PCI_DEVICE_ID_INTEL_CMP_SUPER_Y_LPC 0x0286 +#define PCI_DEVICE_ID_INTEL_CMP_H_LPC_HM470 0x068D +#define PCI_DEVICE_ID_INTEL_CMP_H_LPC_WM490 0x068E +#define PCI_DEVICE_ID_INTEL_CMP_H_LPC_QM480 0x068C +#define PCI_DEVICE_ID_INTEL_CMP_H_LPC_W480 0x0697 +#define PCI_DEVICE_ID_INTEL_CMP_H_LPC_H470 0x0684 +#define PCI_DEVICE_ID_INTEL_CMP_H_LPC_Z490 0x0685 +#define PCI_DEVICE_ID_INTEL_CMP_H_LPC_Q470 0x0687 +#define PCI_DEVICE_ID_INTEL_TGL_ESPI 0xA083 #define PCI_DEVICE_ID_INTEL_TGP_ESPI_0 0xA080 #define PCI_DEVICE_ID_INTEL_TGP_SUPER_U_ESPI 0xA081 #define PCI_DEVICE_ID_INTEL_TGP_PREMIUM_U_ESPI 0xA082 @@ -3262,6 +3270,14 @@ #define PCI_DEVICE_ID_INTEL_CML_GT1_H_2 0x9B22 #define PCI_DEVICE_ID_INTEL_CML_GT2_H_1 0x9B44 #define PCI_DEVICE_ID_INTEL_CML_GT2_H_2 0x9B42 +#define PCI_DEVICE_ID_INTEL_CML_GT2_S_G0 0x9BC8 +#define PCI_DEVICE_ID_INTEL_CML_GT2_S_P0 0x9BC5 +#define PCI_DEVICE_ID_INTEL_CML_GT2_H_R0 0x3E9B +#define PCI_DEVICE_ID_INTEL_CML_GT2_H_R1 0x9BC4 +#define PCI_DEVICE_ID_INTEL_TGL_GT1 0X9A60 +#define PCI_DEVICE_ID_INTEL_TGL_GT2_UY 0X9A49 +#define PCI_DEVICE_ID_INTEL_TGL_GT2 0XFF20 +#define PCI_DEVICE_ID_INTEL_TGL_GT2_Y 0X9A40 #define PCI_DEVICE_ID_INTEL_TGL_GT0 0x9A7F #define PCI_DEVICE_ID_INTEL_TGL_GT2_ULT 0x9A49 #define PCI_DEVICE_ID_INTEL_TGL_GT3_ULT 0x9A52 @@ -3313,7 +3329,9 @@ #define PCI_DEVICE_ID_INTEL_CML_ULT_6_2 0x9B51 #define PCI_DEVICE_ID_INTEL_CML_ULX 0x9B60 #define PCI_DEVICE_ID_INTEL_CML_S 0x9B55 -#define PCI_DEVICE_ID_INTEL_CML_S_10_2 0x9B35 +#define PCI_DEVICE_ID_INTEL_CML_S_G0G1_P0P1_6_2 0x9B53 +#define PCI_DEVICE_ID_INTEL_CML_S_P0P1_10_2 0x9B35 +#define PCI_DEVICE_ID_INTEL_CML_S_P0P1_8_2 0x9B43 #define PCI_DEVICE_ID_INTEL_CML_H 0x9B54 #define PCI_DEVICE_ID_INTEL_CML_H_8_2 0x9B44 #define PCI_DEVICE_ID_INTEL_TGL_ID_U 0x9A14 diff --git a/src/soc/intel/cannonlake/bootblock/report_platform.c b/src/soc/intel/cannonlake/bootblock/report_platform.c index 3d46916133..8d823850fd 100644 --- a/src/soc/intel/cannonlake/bootblock/report_platform.c +++ b/src/soc/intel/cannonlake/bootblock/report_platform.c @@ -45,8 +45,10 @@ static struct { { CPUID_COFFEELAKE_R0, "Coffeelake R0" }, { CPUID_COMETLAKE_U_A0, "Cometlake-U A0 (6+2)" }, { CPUID_COMETLAKE_U_K0_S0, "Cometlake-U K0/S0 (6+2)/(4+2)" }, - { CPUID_COMETLAKE_H_S_6_2_P0, "Cometlake-H/S P0 (6+2)" }, + { CPUID_COMETLAKE_H_S_6_2_G0, "Cometlake-H/S G0 (6+2)" }, + { CPUID_COMETLAKE_H_S_6_2_G1, "Cometlake-H/S G1 (6+2)" }, { CPUID_COMETLAKE_H_S_10_2_P0, "Cometlake-H/S P0 (10+2)" }, + { CPUID_COMETLAKE_H_S_10_2_Q0_P1, "Cometlake-H/S Q0/P1 (10+2)" }, }; static struct { @@ -77,7 +79,9 @@ static struct { { PCI_DEVICE_ID_INTEL_CML_ULT_6_2, "CometLake-U (6+2)" }, { PCI_DEVICE_ID_INTEL_CML_ULX, "CometLake-ULX (4+2)" }, { PCI_DEVICE_ID_INTEL_CML_S, "CometLake-S (6+2)" }, - { PCI_DEVICE_ID_INTEL_CML_S_10_2, "CometLake-S (10+2)" }, + { PCI_DEVICE_ID_INTEL_CML_S_G0G1_P0P1_6_2, "CometLake-S G0/G1/P0/P1 (6+2)" }, + { PCI_DEVICE_ID_INTEL_CML_S_P0P1_8_2, "CometLake-S P0/P1 (8+2)" }, + { PCI_DEVICE_ID_INTEL_CML_S_P0P1_10_2, "CometLake-S P0/P1 (10+2)" }, { PCI_DEVICE_ID_INTEL_CML_H, "CometLake-H (6+2)" }, { PCI_DEVICE_ID_INTEL_CML_H_8_2, "CometLake-H (8+2)" }, }; @@ -104,6 +108,13 @@ static struct { { PCI_DEVICE_ID_INTEL_CMP_PREMIUM_U_LPC, "Cometlake-U Premium" }, { PCI_DEVICE_ID_INTEL_CMP_BASE_U_LPC, "Cometlake-U Base" }, { PCI_DEVICE_ID_INTEL_CMP_SUPER_Y_LPC, "Cometlake-Y Super" }, + { PCI_DEVICE_ID_INTEL_CMP_H_LPC_HM470, "Cometlake-H HM470" }, + { PCI_DEVICE_ID_INTEL_CMP_H_LPC_WM490, "Cometlake-H WM490" }, + { PCI_DEVICE_ID_INTEL_CMP_H_LPC_QM480, "Cometlake-H QM480" }, + { PCI_DEVICE_ID_INTEL_CMP_H_LPC_W480, "Cometlake-H W480" }, + { PCI_DEVICE_ID_INTEL_CMP_H_LPC_H470, "Cometlake-H H470" }, + { PCI_DEVICE_ID_INTEL_CMP_H_LPC_Z490, "Cometlake-H Z490" }, + { PCI_DEVICE_ID_INTEL_CMP_H_LPC_Q470, "Cometlake-H Q470" }, }; static struct { @@ -143,10 +154,15 @@ static struct { { PCI_DEVICE_ID_INTEL_CML_GT1_S_2, "CometLake S GT1" }, { PCI_DEVICE_ID_INTEL_CML_GT2_S_1, "CometLake S GT2" }, { PCI_DEVICE_ID_INTEL_CML_GT2_S_2, "CometLake S GT2" }, + { PCI_DEVICE_ID_INTEL_CML_GT2_S_G0, "CometLake S GT2 G0" }, + { PCI_DEVICE_ID_INTEL_CML_GT2_S_P0, "CometLake S GT2 P0" }, { PCI_DEVICE_ID_INTEL_CML_GT1_H_1, "CometLake H GT1" }, { PCI_DEVICE_ID_INTEL_CML_GT1_H_2, "CometLake H GT1" }, { PCI_DEVICE_ID_INTEL_CML_GT2_H_1, "CometLake H GT2" }, { PCI_DEVICE_ID_INTEL_CML_GT2_H_2, "CometLake H GT2" }, + { PCI_DEVICE_ID_INTEL_CML_GT2_H_R0, "CometLake H GT2 R0" }, + { PCI_DEVICE_ID_INTEL_CML_GT2_H_R1, "CometLake H GT2 R1" }, + }; static uint8_t get_dev_revision(pci_devfn_t dev) diff --git a/src/soc/intel/cannonlake/lpc.c b/src/soc/intel/cannonlake/lpc.c index a7fcd94d67..c4eb884a75 100644 --- a/src/soc/intel/cannonlake/lpc.c +++ b/src/soc/intel/cannonlake/lpc.c @@ -83,7 +83,8 @@ uint8_t get_pch_series(void) case 0x02: /* CML-LP */ pch_series = PCH_LP; break; - case 0xA3: + case 0xA3: /* CFL-H */ + case 0x06: /* CML-H */ pch_series = PCH_H; break; default: diff --git a/src/soc/intel/common/block/cpu/mp_init.c b/src/soc/intel/common/block/cpu/mp_init.c index df571ba775..721e42c03c 100644 --- a/src/soc/intel/common/block/cpu/mp_init.c +++ b/src/soc/intel/common/block/cpu/mp_init.c @@ -82,8 +82,10 @@ static const struct cpu_device_id cpu_table[] = { { X86_VENDOR_INTEL, CPUID_ICELAKE_B0 }, { X86_VENDOR_INTEL, CPUID_COMETLAKE_U_A0 }, { X86_VENDOR_INTEL, CPUID_COMETLAKE_U_K0_S0 }, - { X86_VENDOR_INTEL, CPUID_COMETLAKE_H_S_6_2_P0 }, + { X86_VENDOR_INTEL, CPUID_COMETLAKE_H_S_6_2_G0 }, + { X86_VENDOR_INTEL, CPUID_COMETLAKE_H_S_6_2_G1 }, { X86_VENDOR_INTEL, CPUID_COMETLAKE_H_S_10_2_P0 }, + { X86_VENDOR_INTEL, CPUID_COMETLAKE_H_S_10_2_Q0_P1 }, { X86_VENDOR_INTEL, CPUID_TIGERLAKE_A0 }, { 0, 0 }, }; diff --git a/src/soc/intel/common/block/include/intelblocks/mp_init.h b/src/soc/intel/common/block/include/intelblocks/mp_init.h index e5475383f7..aaf1793a14 100644 --- a/src/soc/intel/common/block/include/intelblocks/mp_init.h +++ b/src/soc/intel/common/block/include/intelblocks/mp_init.h @@ -49,8 +49,10 @@ #define CPUID_ICELAKE_B0 0x706e1 #define CPUID_COMETLAKE_U_A0 0xa0660 #define CPUID_COMETLAKE_U_K0_S0 0xa0661 -#define CPUID_COMETLAKE_H_S_6_2_P0 0xa0650 +#define CPUID_COMETLAKE_H_S_6_2_G0 0xa0650 +#define CPUID_COMETLAKE_H_S_6_2_G1 0xa0653 #define CPUID_COMETLAKE_H_S_10_2_P0 0xa0651 +#define CPUID_COMETLAKE_H_S_10_2_Q0_P1 0xa0654 #define CPUID_TIGERLAKE_A0 0x806c0 /* diff --git a/src/soc/intel/common/block/systemagent/systemagent.c b/src/soc/intel/common/block/systemagent/systemagent.c index 5f7d5af82c..b3657069f1 100644 --- a/src/soc/intel/common/block/systemagent/systemagent.c +++ b/src/soc/intel/common/block/systemagent/systemagent.c @@ -359,7 +359,9 @@ static const unsigned short systemagent_ids[] = { PCI_DEVICE_ID_INTEL_CML_ULT_6_2, PCI_DEVICE_ID_INTEL_CML_ULX, PCI_DEVICE_ID_INTEL_CML_S, - PCI_DEVICE_ID_INTEL_CML_S_10_2, + PCI_DEVICE_ID_INTEL_CML_S_G0G1_P0P1_6_2, + PCI_DEVICE_ID_INTEL_CML_S_P0P1_8_2, + PCI_DEVICE_ID_INTEL_CML_S_P0P1_10_2, PCI_DEVICE_ID_INTEL_CML_H, PCI_DEVICE_ID_INTEL_CML_H_8_2, PCI_DEVICE_ID_INTEL_TGL_ID_U, From cc3e2a031aeb81809573bc9c69bf315868420b82 Mon Sep 17 00:00:00 2001 From: Gaggery Tsai Date: Sun, 10 Nov 2019 22:44:46 -0800 Subject: [PATCH 0488/1242] src/mb/intel/coffeelake_rvp: Rename COMETLAKE_RVP to COMETLAKE_RVPU This patch renames COMETLAKE_RVP to COMETLAKE_RVPU to avoid confusion. TEST=build an image with COMETLAKE_RVPU Change-Id: I93d7b5cc0be475926bb92503b66797dc67e607f5 Signed-off-by: Gaggery Tsai Reviewed-on: https://review.coreboot.org/c/coreboot/+/36793 Reviewed-by: Subrata Banik Reviewed-by: Angel Pons Tested-by: build bot (Jenkins) --- src/mainboard/intel/coffeelake_rvp/Kconfig | 10 +++++----- src/mainboard/intel/coffeelake_rvp/Kconfig.name | 2 +- .../intel/coffeelake_rvp/variants/baseboard/gpio.c | 2 +- 3 files changed, 7 insertions(+), 7 deletions(-) diff --git a/src/mainboard/intel/coffeelake_rvp/Kconfig b/src/mainboard/intel/coffeelake_rvp/Kconfig index 5ae567d326..72906d7d3e 100644 --- a/src/mainboard/intel/coffeelake_rvp/Kconfig +++ b/src/mainboard/intel/coffeelake_rvp/Kconfig @@ -1,4 +1,4 @@ -if BOARD_INTEL_COFFEELAKE_RVP11 || BOARD_INTEL_COFFEELAKE_RVPU || BOARD_INTEL_WHISKEYLAKE_RVP || BOARD_INTEL_COFFEELAKE_RVP8 || BOARD_INTEL_COMETLAKE_RVP +if BOARD_INTEL_COFFEELAKE_RVP11 || BOARD_INTEL_COFFEELAKE_RVPU || BOARD_INTEL_WHISKEYLAKE_RVP || BOARD_INTEL_COFFEELAKE_RVP8 || BOARD_INTEL_COMETLAKE_RVPU config BOARD_SPECIFIC_OPTIONS def_bool y @@ -13,7 +13,7 @@ config BOARD_SPECIFIC_OPTIONS select DRIVERS_I2C_GENERIC select SOC_INTEL_CANNONLAKE_PCH_H if BOARD_INTEL_COFFEELAKE_RVP11 || BOARD_INTEL_COFFEELAKE_RVP8 select SOC_INTEL_COMMON_BLOCK_HDA_VERB if !BOARD_INTEL_COFFEELAKE_RVPU - select SOC_INTEL_COMMON_BLOCK_HDA if BOARD_INTEL_WHISKEYLAKE_RVP || BOARD_INTEL_COMETLAKE_RVP + select SOC_INTEL_COMMON_BLOCK_HDA if BOARD_INTEL_WHISKEYLAKE_RVP || BOARD_INTEL_COMETLAKE_RVPU select MAINBOARD_USES_IFD_EC_REGION select MAINBOARD_USES_IFD_GBE_REGION if BOARD_INTEL_COFFEELAKE_RVP11 || BOARD_INTEL_COFFEELAKE_RVP8 @@ -27,18 +27,18 @@ config VARIANT_DIR default "cfl_h" if BOARD_INTEL_COFFEELAKE_RVP11 default "whl_u" if BOARD_INTEL_WHISKEYLAKE_RVP default "cfl_s" if BOARD_INTEL_COFFEELAKE_RVP8 - default "cml_u" if BOARD_INTEL_COMETLAKE_RVP + default "cml_u" if BOARD_INTEL_COMETLAKE_RVPU config MAINBOARD_PART_NUMBER string default "whlrvp" if BOARD_INTEL_WHISKEYLAKE_RVP - default "cmlrvp" if BOARD_INTEL_COMETLAKE_RVP + default "cmlrvp" if BOARD_INTEL_COMETLAKE_RVPU default "cflrvp" config MAINBOARD_FAMILY string default "Intel_whlrvp" if BOARD_INTEL_WHISKEYLAKE_RVP - default "Intel_cmlrvp" if BOARD_INTEL_COMETLAKE_RVP + default "Intel_cmlrvp" if BOARD_INTEL_COMETLAKE_RVPU default "Intel_cflrvp" config CHROMEOS diff --git a/src/mainboard/intel/coffeelake_rvp/Kconfig.name b/src/mainboard/intel/coffeelake_rvp/Kconfig.name index 35c0f0ff4a..519cd50dc1 100644 --- a/src/mainboard/intel/coffeelake_rvp/Kconfig.name +++ b/src/mainboard/intel/coffeelake_rvp/Kconfig.name @@ -12,6 +12,6 @@ config BOARD_INTEL_WHISKEYLAKE_RVP config BOARD_INTEL_COFFEELAKE_RVP8 bool "-> Coffeelake S U-DIMM DDR4 RVP8" select SOC_INTEL_COFFEELAKE -config BOARD_INTEL_COMETLAKE_RVP +config BOARD_INTEL_COMETLAKE_RVPU bool "-> Cometlake U DDR4 RVP" select SOC_INTEL_COMETLAKE diff --git a/src/mainboard/intel/coffeelake_rvp/variants/baseboard/gpio.c b/src/mainboard/intel/coffeelake_rvp/variants/baseboard/gpio.c index ec8f58ba16..709249e918 100644 --- a/src/mainboard/intel/coffeelake_rvp/variants/baseboard/gpio.c +++ b/src/mainboard/intel/coffeelake_rvp/variants/baseboard/gpio.c @@ -264,7 +264,7 @@ static const struct pad_config gpio_table[] = { /* H21 : GPPC_H_21 */ /* H22 : GPPC_H_22 */ PAD_CFG_GPI(GPP_H22, NONE, DEEP), -#if CONFIG(BOARD_INTEL_WHISKEYLAKE_RVP) || CONFIG(BOARD_INTEL_COMETLAKE_RVP) +#if CONFIG(BOARD_INTEL_WHISKEYLAKE_RVP) || CONFIG(BOARD_INTEL_COMETLAKE_RVPU) PAD_CFG_GPO(GPP_H22, 1, PLTRST), #else PAD_CFG_GPI(GPP_H22, NONE, DEEP), From 12507ce8954e074fd93c5366b0b5ecb10f28aa0a Mon Sep 17 00:00:00 2001 From: Matt DeVillier Date: Wed, 27 Nov 2019 22:49:43 -0600 Subject: [PATCH 0489/1242] mb/google/poppy: add VBTs for remaining variants Add VBT files for Atlas, Nocturne, Rammus, and Soraka variants. Extracted from ChromeOS recovery images for the respective boards. Select INTEL_GMA_HAVE_VBT for all variants except Poppy, since it doesn't have a VBT (or a recovery image from which to extract one). Change-Id: Icba2741e0b7309c22c027f956cd20cec78f34052 Signed-off-by: Matt DeVillier Reviewed-on: https://review.coreboot.org/c/coreboot/+/37311 Tested-by: build bot (Jenkins) Reviewed-by: Angel Pons --- src/mainboard/google/poppy/Kconfig | 2 +- .../google/poppy/variants/atlas/data.vbt | Bin 0 -> 4608 bytes .../google/poppy/variants/nocturne/data.vbt | Bin 0 -> 4608 bytes .../google/poppy/variants/rammus/data.vbt | Bin 0 -> 4608 bytes .../google/poppy/variants/soraka/data.vbt | Bin 0 -> 4608 bytes 5 files changed, 1 insertion(+), 1 deletion(-) create mode 100644 src/mainboard/google/poppy/variants/atlas/data.vbt create mode 100644 src/mainboard/google/poppy/variants/nocturne/data.vbt create mode 100644 src/mainboard/google/poppy/variants/rammus/data.vbt create mode 100644 src/mainboard/google/poppy/variants/soraka/data.vbt diff --git a/src/mainboard/google/poppy/Kconfig b/src/mainboard/google/poppy/Kconfig index 85dc9a5701..30e5263613 100644 --- a/src/mainboard/google/poppy/Kconfig +++ b/src/mainboard/google/poppy/Kconfig @@ -10,7 +10,7 @@ config BOARD_GOOGLE_BASEBOARD_POPPY select EC_GOOGLE_CHROMEEC_ESPI select HAVE_ACPI_RESUME select HAVE_ACPI_TABLES - select INTEL_GMA_HAVE_VBT if BOARD_GOOGLE_NAMI || BOARD_GOOGLE_NAUTILUS + select INTEL_GMA_HAVE_VBT if !BOARD_GOOGLE_POPPY select INTEL_LPSS_UART_FOR_CONSOLE select MAINBOARD_HAS_CHROMEOS select SOC_INTEL_KABYLAKE diff --git a/src/mainboard/google/poppy/variants/atlas/data.vbt b/src/mainboard/google/poppy/variants/atlas/data.vbt new file mode 100644 index 0000000000000000000000000000000000000000..850375e550f1eb49935d100d57b626e244c2cd96 GIT binary patch literal 4608 zcmeHKeQZ-z6hE)8pSSO|uWtmpiu3Rh=qB4<2MkrhkNQ}C~s3b=Hi^zW(qKO(zOa$t=?>#nTfmISf)YEtF zIrqH#e)oLb``+#PfsTI6_6#MXJ)LM#9yAyU{7&ss>PV!r!|`Z;bhsm#iuK@mSP5F- z>P3LOAk<0`O^YNBO%;mazIuX9;-0a6qs2mVyfFFX)Yv$tV+oAz-(M&eCPts9Nbr!XhQyON(qJRcnj1wrzbxX7SEgYEL?m zjP@r|y_o95cp@9kW;^$EB!@8Fm+DS*B>Fq!GFu2EHa32AV)TgvQy7lbV++mEXn-0n zV{B|uaq;MYNbD=h%->n=NhdFcRj5z$?; zn7Uz5z_vrMk!_`A25f2f6SVdE* zxLk0x@g}@+D*B%y_a`F zd<8u4qwSoF!8z9@;bhG}Q{!1vmid{PU0h&h-)!@czrOpw{vXc3>TdYPQ!3+y2Nid2 zt(l0r+p|3M7_CX0n_dh$AgK~`Ll}Y(hxM=ma*#I8Pj2Hq`!&-=MdkaEQPs zmkgLA0;qo##2CX-rar^ia}3{O>W7Sd%J3(qRv7bmvDvFey{yNJhrQ~vUiOj~-}kB? zd)b#>{LQPnBo>fxo1`WrmX+|Rq`n}r*ChNvQa_j2w-R2FRKLt>W!x#N8JRsQ;|W=P zMP_fw_>ruBEwk@rbokU&KDNe(yL{@9kL~x#4XUGLyC9STKI6dSo{;F>GiZ|xc}Y-6 zI{X{yE4Q>Lt;gwO&!d%49JDQuFzZK%46ep-X@!}iy4K_7XOC({uk+;*^0lBxVS^St z*=iyLTaSz8IgQ)|J4a}zgVW8U&>G-W1~gq8uUYVc9^|?-?FdzcFpZgzqAS-S2xZ6L zKzO%#`a&kOK_5J|=z~yp8VI`cOcg$K@6@$@XIgaq>>`5GJON1qj%qUb_?m&a4Af~| zWvdoElV#)ENv>3rhht6U*<7ej*U+j3RnuNJPN-7JRZSG(_R{S5nRSHFz+(p>1V`C8 zr%1DonJU)9oAtBjGBazn^c$-d5Jd2DUDBP^AZQKxd~PPM1vBP(kozFga^wiNxh4$+ z*+g()6;WIa!E72=X_6M>PZ@a-%d{WKhmvc%u^#v$zxk@RwUvU0w>Rp8jf=Gq!EYeY zpC0G(`=VZlTnTD&iW1;YnLf}7d9ySTD!w(`fX#$*Fp!-8L(|zra$6c43m;7(AGld zZr;3|H}~6_d9!clwhpxQW2$SYJJQvTHf2DEk&2TvuBNtlA~hU~^hbu zuefy;AR`FXa#+{H@$up$*+e~3!b}E~HA)9GX7zeokUZ(&cxFBGF05_X}6yP<$i{MqkX@C>K zse*xEsDLVX0h|B^00OAo2^Ads1PAH1d%<1BHH$>>qB%FXu}y>qm(rlB-aiS7lLx?M zPE-NO6>^4{ZfBc0edeNlW4cmsXf9 zYVWBODUus6(k*#JrVuy*_yrxteKn8}LvUPlz^me3sB>Nf)rYXtr$Ptu5b^ge2A7F{ zCjNu?ImAV6GAyoI=)cn@)exQqA@@i6fiv3mw?lpF=V6GR2UmKBx+)d_FbLg9?9 zKV$2Cztg4@F(Sx)uh8q2ZI6pohd^ngrEvyuoc!p8j@!Jve6K?uOqDuc5`0JU#}7-cxdw3irrh2bYm`<$__82-kz5@S9I8zn6wu`UUZ zO4`d3dqcucCGAUzeJ9~xlID?Fg^YV-EiSW^jK^f{HJQC5<7cw=jm&u%{F}sc3I0>;nbAP_!Qu_LG7xzqY~8Hu-VCUmNnXQNL2BxeAUeLZQNMHayP=}rAy@~jjN+hUZG`y%LU?c^h6?Mf9Mv?RuwHw#S9F}O zjgYAZBLds>s#DDtLRIq#(dyI4O>lCAR%)DXABA2Ar+Yy+^vTL4ALxgCF3-AxWg*OB zZ%{SVe;^1&vk5E{;p4{HE4{&O#^C8?AB3XW_{oO*Tp2!eK56KO&ovpwg=GY{)d9%^ zu5vQ@%%*{}y-=ff6z#p>nJk*`PI9H3JREN*&ZmPlhK}}L&~7@5W``;lJmo|YYAwu9 zp4&nQb<2BEH2V~J-ZfW7J-lB#ztB6kSx>&VVF^J5vpuFvmV=IZ?M z5UCt_J=|eUnh1)8;KDMZxEh4{ByP}UJ-Qr4k)B8Lq2SqT)&no{+gG)trBHQrZ@n>C zzq}VBokbksytLq1`?;t!AYFjUw5nF{UxAeemCxkvj^uE1WIUVe899=DFfV#0MyF@; zsY&vIid+2wCG}CV;g4p zj~Zt};-BOcqPg{zigLWAEsmky5cGS)6!ka&!zci4?~7?k$#zs$s1!En>TDkjJ34VSC4HXRd0{AwQt&@uw+-FuQ!uQ z#|Khe_wa1Gd0kaRM^}w5~E{>$48!cauTD7Mr@^bthYd| zkTEejKGux!QVILH&jj`tCyL`w7Yoe_;~=NN?-l?A57ZeTz~xpT1Go(^5K!fc8^Nve zuAy>^AHWS@03d+MgHXY>NpO*EwI94;ZkZ*57cJf3&JLj)&gDT>{TB#{lMlc{!Vju| z0ypqxh2eNza=h%<(i0TWMZ)qzbi9HAZUP|TwG>@I`_GQ!A^Xo8}rvD)xfk6l~Y$53&bvrU`Nm0x={Q;6ZS3^$U zGy{3+y6E%Iwd@ScZ8p=S7g=H@R-ciX!exHbdJ zyWw1*T*34AsQ&y)`&q-SS?+zD)}+f%2ZI4fstnx_g)k&x6)b{0WURW$Z=JK(1W}s_ z5$gB`y$MAl1U@m(;RF#t;~OA8$Z(ix6O292@O`Fz!r12we`MO9j0qC1k+dxmOGr2( zY0paRWeGo$w9h2=rG&pqnklh>j4iSjmsyXD2W9OgnY||C$FlZ?%)XKF4_WgmETrHA zik4DXPQk;9_KL#ZRPa+p`$}QoD|lJa>Vj-(5FZI@*&ur?s5EJwvg^E14h5}3$3HI9 z*)!ylEqPH;NqXwm&@DHAQreEtWzR<|qd4SR7-6OkAvUxeqvb_*jvCsI*w-G-6&>db zBNUc`5r@@!_-LDr5Ntu`K9@K2|>$1O1Te@{}i16T%c` zBdVcZg&d*vys)t(6MR^LdB~2WW#&1h8VgZG4wqrTMgq>6~Sv)K=Poc zmQ3zjF?b>i4f@uKGZ#FQ73=P#P-@A;bIp~Re5Aq9(U}XHO?SnrPUW(%mQh4I$}?jp z?<0gJo;?6U@KmfiMV|3Y*RUSmX`DHmonEPD-d-|?Ac9pIQzmOc(3_0Y`RRfl&f4`L zk3pp6NOY@f(n3&d1P|6QiVG2#$>0)Q))UoHRA@g^3}xSDYd!Eqe&bc`YA=TmZeDK; zt*_372z7Q0^p9rYebHz@z6|wwRSi{RphJ|$klvcvof$q*EbSQHU;H0*>;c}aUHc+< zx1XjO{e;v0Bv$pS?SDfzuOruWv~DrHx|M=VQRTjqF0TTt6W#&}q*)i>=p5Y{s-5iF UKOVPTZV1pt#Wy(ZqC15C0;em?9{>OV literal 0 HcmV?d00001 diff --git a/src/mainboard/google/poppy/variants/soraka/data.vbt b/src/mainboard/google/poppy/variants/soraka/data.vbt new file mode 100644 index 0000000000000000000000000000000000000000..4156bdeff437f84855543e72347cbcd96e31a454 GIT binary patch literal 4608 zcmeHKUu;ul6hHUg{{8N~-R&KLQg9v-p&PK>4wx{f+^!w0tYhsu=7=VA(4vcljcu6W zKWd!G691$RYS0i};tRnS662FG@?s<*Di4Z}@?xSy6B9AM0QKDOURGd%H5gG0r#;^} z-*-=c_nh0Ie^)oU8z`47dn&&19k;XYUfjDvM;+k5gUl@?o9Q?d+=LW43XfK z3jldRSgJ$~Bbq!gStv&O8woary`y_ZiiMU$Vd9y|(J@TNlNj5(w@@sM4^I~Im>t{} zLkm-7orgw>dE9Ym|DM8lI}(sV))?K;ynX{>w5654Msy>oMtiiaedA`8CA#8$z3F5s zHjwPwfqng$NM>W%Y*%k*Y8R&a`?`~z$$_qf%I3m|kB%K4A9?EONsPoBv6bGjj)QWS zF+Msz){L=Y5&JEh3G6RS6vm$|!}OC1V8}IazX=fqaf1QDj#@4*2q;Nc!}$#W$X~T;9L$g&3A#2Eb;=lxuOY3 zo{%rZXgXGx94q^^{4t7iR_Is-{MHZv2@h8c0qs{)kDMmb$a}|1<|gzWyw=Jdypyd& zkzRU^-pIqYgkTXsKrmpRzX7&M5tx)jcuCp>D_p0+=SNuM*WfYY4DlH^gYSrcApV*7 zcjC*$UJrvH@iO9vh+Bv^6UT{ri618(CiWbHOBJzXO#x9!aAeSypt<19MkpO~#*aDU z{@-Y_iI^j0NAkfMno7m%g)5b>Lr|&s9<@9$34y{E5)M+gBU4;TQrhVckhF3&E%3-odA^&R0*bl1)aS{lBz&AL?8qSSP6?D2Weh6`S>||ofEYU zAwr$CL2p5kFo93ZGdMv6(D)Wek1!l&`UGPyGW?L~pD^}0!ylRcCu4$)t7Uz&%;GYR z$olg#dsW7dWc@RleJSIwvR;vyU%?hdk14E2!Gntaio)Jd@MA^)LSf%1_=lo#vJs(+=j?^V34>U9COG=N(IdM3c02&hfEyCj|$O2GgxbbR9q zojpUM!sSIlBk8VNO}E_qNohMmm%SCOg3^$}{> zM#wJ(GX|@S&`g_+5NbOj+4UK@2`&qvgKDOmM`1L<(F_=-F;+k41O3p_l___)CWI-> zgf&yU20aRwG<1JI?GvQU{(9x<7LYdcmis?C7gAd(XOk>ZEmsC5lK#X?E=7 zgM`pjor^NBQ zRHL78+T+7j{o3)rp;vAo@djGE7+&8>P9~{x-$|EO9@Yx)z)uo18v@MC(cPii$-er> T Date: Thu, 28 Nov 2019 00:50:47 -0600 Subject: [PATCH 0490/1242] mb/google/rammus: add libgfxinit support Add libgfxinit support for rammus. Use panel init values from VBT. Test: build/boot rammus with libgfxinit and Tianocore payload Change-Id: I4775a36d83bd67a0064a162effaf96649e9c186d Signed-off-by: Matt DeVillier Reviewed-on: https://review.coreboot.org/c/coreboot/+/37312 Tested-by: build bot (Jenkins) Reviewed-by: Angel Pons --- src/mainboard/google/poppy/Kconfig | 1 + src/mainboard/google/poppy/Makefile.inc | 1 + src/mainboard/google/poppy/gma-mainboard.ads | 31 +++++++++++++++++++ .../poppy/variants/rammus/devicetree.cb | 7 +++++ 4 files changed, 40 insertions(+) create mode 100644 src/mainboard/google/poppy/gma-mainboard.ads diff --git a/src/mainboard/google/poppy/Kconfig b/src/mainboard/google/poppy/Kconfig index 30e5263613..674fef9c8f 100644 --- a/src/mainboard/google/poppy/Kconfig +++ b/src/mainboard/google/poppy/Kconfig @@ -191,6 +191,7 @@ config VARIANT_SPECIFIC_OPTIONS_RAMMUS select DRIVERS_I2C_DA7219 select DRIVERS_SPI_ACPI select DRIVERS_USB_ACPI + select MAINBOARD_HAS_LIBGFXINIT select MAINBOARD_HAS_SPI_TPM_CR50 config VARIANT_SPECIFIC_OPTIONS_SORAKA diff --git a/src/mainboard/google/poppy/Makefile.inc b/src/mainboard/google/poppy/Makefile.inc index 030cf1da2d..9d26430343 100644 --- a/src/mainboard/google/poppy/Makefile.inc +++ b/src/mainboard/google/poppy/Makefile.inc @@ -24,6 +24,7 @@ ramstage-$(CONFIG_CHROMEOS) += chromeos.c ramstage-$(CONFIG_EC_GOOGLE_CHROMEEC) += ec.c ramstage-y += mainboard.c ramstage-y += ramstage.c +ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads smm-y += smihandler.c smm-$(CONFIG_EC_GOOGLE_CHROMEEC) += ec.c diff --git a/src/mainboard/google/poppy/gma-mainboard.ads b/src/mainboard/google/poppy/gma-mainboard.ads new file mode 100644 index 0000000000..87cdb5e7c0 --- /dev/null +++ b/src/mainboard/google/poppy/gma-mainboard.ads @@ -0,0 +1,31 @@ +-- +-- This file is part of the coreboot project. +-- +-- This program is free software; you can redistribute it and/or modify +-- it under the terms of the GNU General Public License as published by +-- the Free Software Foundation; either version 2 of the License, or +-- (at your option) any later version. +-- +-- This program is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more details. +-- + +with HW.GFX.GMA; +with HW.GFX.GMA.Display_Probing; + +use HW.GFX.GMA; +use HW.GFX.GMA.Display_Probing; + +private package GMA.Mainboard is + + ports : constant Port_List := + (Internal, + DP1, + DP2, + HDMI1, + HDMI2, + others => Disabled); + +end GMA.Mainboard; diff --git a/src/mainboard/google/poppy/variants/rammus/devicetree.cb b/src/mainboard/google/poppy/variants/rammus/devicetree.cb index 70a4667e9e..f44f9ce3ef 100644 --- a/src/mainboard/google/poppy/variants/rammus/devicetree.cb +++ b/src/mainboard/google/poppy/variants/rammus/devicetree.cb @@ -1,5 +1,12 @@ chip soc/intel/skylake + register "gpu_pp_up_delay_ms" = "200" + register "gpu_pp_down_delay_ms" = "500" + register "gpu_pp_cycle_delay_ms" = "600" + register "gpu_pp_backlight_on_delay_ms" = " 1" + register "gpu_pp_backlight_off_delay_ms" = "200" + register "gpu_pch_backlight_pwm_hz" = "1000" + # Deep Sx states register "deep_s3_enable_ac" = "0" register "deep_s3_enable_dc" = "0" From 2d086e6971fc5bed9e5a6c028ca8601d2499fd82 Mon Sep 17 00:00:00 2001 From: Matt DeVillier Date: Fri, 29 Nov 2019 13:05:11 -0600 Subject: [PATCH 0491/1242] mb/google/glados: restore device-specific VBTs When migrating glados (and variants) to FSP 2.0, the older board- specific VBTs were dropped in favor of the default FSP 2.0 VBT due to compatibility issues. Now that libgfxinit is available and the default, restore the board-specific VBTs so that external displays function properly. Select MAINBOARD_NO_FSP_GOP for all variants except glados since FSP/GOP init will not function properly with the older VBTs. Test: build/boot chell and caroline variants w/libgfxinit, verify external displays now work again. Change-Id: If55a67e0d3d78e4acf80cee1733ad8e14b8847d4 Signed-off-by: Matt DeVillier Reviewed-on: https://review.coreboot.org/c/coreboot/+/37397 Tested-by: build bot (Jenkins) Reviewed-by: Angel Pons --- src/mainboard/google/glados/Kconfig | 5 ++--- .../google/glados/variants/asuka/data.vbt | Bin 0 -> 4608 bytes .../google/glados/variants/caroline/data.vbt | Bin 0 -> 4608 bytes .../google/glados/variants/cave/data.vbt | Bin 0 -> 4608 bytes .../google/glados/variants/chell/data.vbt | Bin 0 -> 4608 bytes .../google/glados/variants/lars/data.vbt | Bin 0 -> 4608 bytes .../google/glados/variants/sentry/data.vbt | Bin 0 -> 4608 bytes 7 files changed, 2 insertions(+), 3 deletions(-) create mode 100644 src/mainboard/google/glados/variants/asuka/data.vbt create mode 100644 src/mainboard/google/glados/variants/caroline/data.vbt create mode 100644 src/mainboard/google/glados/variants/cave/data.vbt create mode 100644 src/mainboard/google/glados/variants/chell/data.vbt create mode 100644 src/mainboard/google/glados/variants/lars/data.vbt create mode 100644 src/mainboard/google/glados/variants/sentry/data.vbt diff --git a/src/mainboard/google/glados/Kconfig b/src/mainboard/google/glados/Kconfig index 52907cc683..bc0c67ba46 100644 --- a/src/mainboard/google/glados/Kconfig +++ b/src/mainboard/google/glados/Kconfig @@ -20,6 +20,7 @@ config BOARD_GOOGLE_BASEBOARD_GLADOS select SOC_INTEL_SKYLAKE select SYSTEM_TYPE_LAPTOP select MAINBOARD_HAS_LIBGFXINIT + select MAINBOARD_NO_FSP_GOP if !BOARD_GOOGLE_GLADOS if BOARD_GOOGLE_BASEBOARD_GLADOS @@ -63,9 +64,6 @@ config DEVICETREE string default "variants/$(CONFIG_VARIANT_DIR)/devicetree.cb" -config INTEL_GMA_VBT_FILE - default "3rdparty/fsp/KabylakeFspBinPkg/SampleCode/Vbt/Vbt.bin" - config MAX_CPUS int default 8 @@ -94,4 +92,5 @@ config EC_GOOGLE_CHROMEEC_PD_BOARDNAME config UART_FOR_CONSOLE int default 2 + endif diff --git a/src/mainboard/google/glados/variants/asuka/data.vbt b/src/mainboard/google/glados/variants/asuka/data.vbt new file mode 100644 index 0000000000000000000000000000000000000000..8f2a7b0614404d5a1ba4a78e14a66d0f23b09012 GIT binary patch literal 4608 zcmeHKUu;ul6hF7Of4_TgcXx+U3eF?q=mu=J118KVw`&J0>sY&vIid+2wCG}CV;g4p zj~ZvP#9;d1A2dXl_+s#7iSfx8c`+_oRAM4N%8Lo2CMIHh0qXhgy{y%RtikvP<+SHJ z=lkyI@1AqMf2ZpPI|ne`vo8_p=|Y>bpu@cSJ+(`zGv1fpABzk`_ID=wqCL0(cf#xH zwMzh5L0Bb+bv+zEGMUSV`Wp#0fxV*#M)J9qSZ?Bp$5)RJ}di*1mPS!eU*~zTRX! z5gCa0?ZLi&jK$NDbh@jzGqDeo{e9i>&iFuAOks;*L`TPtkB>a|_#}p+jo3=>*kpp5 zE@O0be5@HG`8@V>n+fdCP2|R(%w?Mu#zD@4*C_x9E~trs09RW9yo+BIoCY`%oGKUy zh6S31{f=ST<&xzY$t#cl{K7|?oz#(wN@hPZ*Ju7M`=wuymT-afTYUM4Iv0X4A#L4$UxGp zo4jD&yp<`hZU_--mi)951|Sq9@QL4#QSS^9K;tVQKEQC8X%mb+%kUkheZbhq48LXC zuZ#&2u9vj!5{pVWB56-c>_rLRleCW{_NjzFN?J)`J{enNEh4iX8IQ`^3o<(?DnIVjz(n)DML6<#`Rz`8iu{^?T4MKQm4TcIU ztQ^(1op4ywA@k#Wd4%jLFe1>P2WHwVgh1N~(W=kLO>lCA4yu`M9EIKlr&6FB`dHnf z5A;K>%TumkRR~j<3aW-$fglvk>aR+KcUz_|q=F5`(5bQyLeZ@GWWzmIg%9034E?}d zt6`iiBe<;!NFH=mlgUH(44z3ry}q+(&jrt9(Y!m!m1^?vOmlHI6RbCMwC93m(^)jD zQ@P-&CW=r;VRmfpUP5Rp&qdL!Q{-9KbQSC2&Bobtsp++P@{N^?2qKuJF=etE1ii_a z&rE0aK+38Ifua!U=-}(&CfB5ipjZeltRjj_L6}YAN?q2YLv;4kjG$2!ex{RvUmVKZ@l>3m_ncSZoK9bAt89to* z4|J>mE87jvgM0Tp)#PXF_M%wUE64wYUit%7zMtzG?|_p#Nye#C-%FQO7B&j6!9}ro Y4q#@HZV7d>kM0G&pJ>tErkl&aZ;9f<9{>OV literal 0 HcmV?d00001 diff --git a/src/mainboard/google/glados/variants/caroline/data.vbt b/src/mainboard/google/glados/variants/caroline/data.vbt new file mode 100644 index 0000000000000000000000000000000000000000..02e1cd10f68fba12d9de799f7800043f63b4f2b8 GIT binary patch literal 4608 zcmeHKU2GIp6h5=FzjtP~(<#cbU_Bzjwm>^upq5%?w!4Kc-O}A|sU@1Qgy3zQ9>DfK^ zoO|}pH|J;WowMuu+xsxvwJ#Ox>OhC`pu>#%6pf3iJ=v4ppNRFv_P3{c;$3(i?uNJ2 z8&?4Gg0M=C>UuPJWV}#}^wtq<3cH673>6EFiNe^^7#$oh6^q!**NkCrVXQFvOd;Q(Fb;AK{B8k2@IX}z1i0P=;Gg}f;5NXG;8wvv zFjPR5|LO)X01!asPN?A8Cb-D9-Vfdox7;Lx7cJf3iycBYT+D&0`mYcYCm(>vQd9xS z6Y_-^4QJIgXO+vkE&oM8(w$YvHNpx8xH6vvv~Nu|a+*jb?{B+m{?-4CE>fh|o~3(P zVRIpH0tgB^917IJE-?b*q6=OWTVSnw2K)hpjR6%NA^#hFHq)dVS#+mrat-XJ4J`WGCf8Vj>;*92Q$&~mR_*LHvTO3qhtgWK;$85DEe(8a zwp={^o4Y514Z-*mHZFpgJwnat3$?)^x(f zK&gzE?os`@wRTQw|D5IC$LX1L`RQOV07;dh6Cx0T1gwJB+ZmqK*mN{i^;4@#-pruAF0-#?{8iR`3aeJ| zK}Aa{EUVygMSE3YZz%YQqJ62bZxy_*XjMVBDu_FRS|-RI3o7+4Psw#jC{+ioM#n!Y z)7dlNk}Y{vP)T~KHqcvcaZ#F2(951jE2B8zS{h-h3L!eM1|y{vc8+SBPq^%I$R%Hk zdufFHDllTOUJspYwh=rd$2chh>d@#Jz75LD(!_W^*HyOscIRvlW0m=Oy z5SPy6q5JyJW}sHzS$1l{Gg-FYo#aX-d3e5|Je3RA8ag_)plZ6yR(DF(tR#v^TWM-! z`hG&FpQ}aL>Qm$?&twHryi+%IAv3vFPrto#7C{8b$z&x6dc84|o6PH>jNK0cMIqAB zK_v4QW9dvTdL}Id#YXU81qfHdFqOuYx~#|fRbcs0ru|4hRJJc%t)md(b%=DAvk zP-P*|pB*oc;`aNZ&VXDAYI3St&9Ab3phJ{MPVG$ZPY)g`6!#1sF8mKBJg9}V@g?x? zo}r%ntTSE~=k)pZzo479&_WLYHr)lMc9Jnko%&vSS><7q@FrXq8>RtH&e9#BZV7-; SqW@nl&Yrq8)aCio8TcItGQ%GL literal 0 HcmV?d00001 diff --git a/src/mainboard/google/glados/variants/cave/data.vbt b/src/mainboard/google/glados/variants/cave/data.vbt new file mode 100644 index 0000000000000000000000000000000000000000..02e1cd10f68fba12d9de799f7800043f63b4f2b8 GIT binary patch literal 4608 zcmeHKU2GIp6h5=FzjtP~(<#cbU_Bzjwm>^upq5%?w!4Kc-O}A|sU@1Qgy3zQ9>DfK^ zoO|}pH|J;WowMuu+xsxvwJ#Ox>OhC`pu>#%6pf3iJ=v4ppNRFv_P3{c;$3(i?uNJ2 z8&?4Gg0M=C>UuPJWV}#}^wtq<3cH673>6EFiNe^^7#$oh6^q!**NkCrVXQFvOd;Q(Fb;AK{B8k2@IX}z1i0P=;Gg}f;5NXG;8wvv zFjPR5|LO)X01!asPN?A8Cb-D9-Vfdox7;Lx7cJf3iycBYT+D&0`mYcYCm(>vQd9xS z6Y_-^4QJIgXO+vkE&oM8(w$YvHNpx8xH6vvv~Nu|a+*jb?{B+m{?-4CE>fh|o~3(P zVRIpH0tgB^917IJE-?b*q6=OWTVSnw2K)hpjR6%NA^#hFHq)dVS#+mrat-XJ4J`WGCf8Vj>;*92Q$&~mR_*LHvTO3qhtgWK;$85DEe(8a zwp={^o4Y514Z-*mHZFpgJwnat3$?)^x(f zK&gzE?os`@wRTQw|D5IC$LX1L`RQOV07;dh6Cx0T1gwJB+ZmqK*mN{i^;4@#-pruAF0-#?{8iR`3aeJ| zK}Aa{EUVygMSE3YZz%YQqJ62bZxy_*XjMVBDu_FRS|-RI3o7+4Psw#jC{+ioM#n!Y z)7dlNk}Y{vP)T~KHqcvcaZ#F2(951jE2B8zS{h-h3L!eM1|y{vc8+SBPq^%I$R%Hk zdufFHDllTOUJspYwh=rd$2chh>d@#Jz75LD(!_W^*HyOscIRvlW0m=Oy z5SPy6q5JyJW}sHzS$1l{Gg-FYo#aX-d3e5|Je3RA8ag_)plZ6yR(DF(tR#v^TWM-! z`hG&FpQ}aL>Qm$?&twHryi+%IAv3vFPrto#7C{8b$z&x6dc84|o6PH>jNK0cMIqAB zK_v4QW9dvTdL}Id#YXU81qfHdFqOuYx~#|fRbcs0ru|4hRJJc%t)md(b%=DAvk zP-P*|pB*oc;`aNZ&VXDAYI3St&9Ab3phJ{MPVG$ZPY)g`6!#1sF8mKBJg9}V@g?x? zo}r%ntTSE~=k)pZzo479&_WLYHr)lMc9Jnko%&vSS><7q@FrXq8>RtH&e9#BZV7-; SqW@nl&Yrq8)aCio8TcItGQ%GL literal 0 HcmV?d00001 diff --git a/src/mainboard/google/glados/variants/chell/data.vbt b/src/mainboard/google/glados/variants/chell/data.vbt new file mode 100644 index 0000000000000000000000000000000000000000..a654a5efd5fb57401c093ce712fbf428ce3709ae GIT binary patch literal 4608 zcmeHKU2GIp6h1SvzjtP~(<#cbU_Bzjwm>^upq5%?w!4Kc-O}A|sYOlL!Y`tXksG97hpYiX6O%%bffVH!a$vx$_87HGsXft?*&mPgMfbNSdtzO94(^7x zwCk4va)Pi*i5NyCab!GS2=~?zY!bVN4-6IZjq&{0)8oSVkS6a9?HHd2k&NOSA9?JA3R#Cp0@ ziDa}d(X$78dNH2JL^GL=?)Kz9O!fA3CfXBy9dVV-g%KMbIX*h{j1~&m%g2miZ+WmVt*YZ08lJ1N`t`Szi&y|HFp#5sHk<&yPd4J1M3!naHbcrIp`YgT6 z3Y!ao6F@*P;E=x-c1d9vmqd6`YJs(`S@8K0Hu^Pqgg8xn&duN(;_rxmApV8;8nM^I zpqh9!@dLz-#M_Bu#NEV?5)Tr4j=|NkSmaYcR1_RpZA;Kx@LC-dPdoP0j@|z=O*Rp8 zr0ht`SV2=Rd%bYI{8bRjW#7Zx1CtOaY$5I-bviO>Nl8jM{XUXBR|8JJT=r+F+eFvj z*Rpdkx7f;MdXYu9tESYzZd$;SuWfRT706zI@_VWT6TqsSwMKSbx$#k2gI2r?o{*)1 zx6PJI+kf*;i0=uje-zJq8JzcC5vFSXn;OrWw#;Q`mOe0NTd@0g+B+FooPjl+aKT?J z;l+D2Uv{m1ulCPb?tOy3Nzq3eg9%8g0-X?sAjDxEtbi<}th&hu*2%lji^@!hP_^XI zg)ji&5P^>^wo&g45kTGRAU(uzkm+NLy}1`^9j+O4yEXAaV?LK zTLoqm)*Hd8W*Z^cd_uD8GjbCwgf^;~{x}Mw9!{mfFpZI#IUndjt}7GnP(=t6m=0;C zwg5pWS=C>K2p=>~Tug`7n**ojeGp0>%LmglQ-KeiJ51xiOp|Gzok#H46_C>J25I?B z9=fmpOd4v9oh4^3cqU8M*-5Tcl85ITO4Hd;t!bb$7c`r$l2x73Y*rFQxUD!nGIKv6 z)X&dF$*NP7Y4>CWQM^+(eLg+8)=0g*at=WP*~w%j2u8g*o1M%V!L(fu0!1Ow)0BpJoPVOXQf-3dBbXetJlkg^7k{V_Jrsn9jP`CI&DAND0 P7H3V}9O|9^@)`IYcV5CD literal 0 HcmV?d00001 diff --git a/src/mainboard/google/glados/variants/lars/data.vbt b/src/mainboard/google/glados/variants/lars/data.vbt new file mode 100644 index 0000000000000000000000000000000000000000..0aac82c3b18d3bb71258b1a04aaadf8dee2152e9 GIT binary patch literal 4608 zcmeHKUu;ul6hF7Of4_TgcXx+U3eF=UbOW~A0Tbqw+qHw0b*x>-9MOahT6D3nu?;i) zM~yQfF_=F12My6Bz8HL2Vtg`2UW`kK%8U3YFD6JdF%jbna6R9>m$kT%H5mV3IPLk) z`Of$C_nq_oJzX=@HHg{Xy{TAlH#(FD9p=>yR4%5jWPf&FA~qP?*Olsz_u@IY7v5H{ zUk1nv!U{R6>(S)lsX{R_&_u8)>>JxZS}e3C3X{)Fjg4bEp2XOJ1BGH?Vq~h2$L!F~ z7;;R7bsZfo=5hDYL;DL89Y{br^~UJtmQ9-xqpfZ9)uUTT)jOi?9b2|3EYThB?@K3B zvB6~jZtNexL^2!8X1n{kQhPBy(BG5nN)C1>6t)mXd~E#K#OPB`Phlk9gl#m&Mhnz( z8RKIU<1H8~7IA?0nZ$v@WMSgjLcT>|9ONwc-2#B%fw~w7aIFo%zwlMTZGaoWt%8AI zsDLVObpsdx2%vH&RB&w(Tx4782XBa5ZVe#I3~Jh~vb4#E%n?5POfpRnt}COF&c-99eHmP~Gr)6O>Ln_S23% z@Cz+A5p$&ENXuA5VVXW4TsOZCfob|5Kw%3B2dT%ADNBlC+Nlqc|&p&b46I@0NFG;N}@v z)dLp-r7~W;Pxa?k+ii`vXSx4L+LJCnT?_^wsWS9H1VWI2HLwhFkhbzBKUgnswHLLS z5TS0-Ppe@7B4GlbyxB&zGeiJQZ-Dp+!x5%UGWH_F5194|W1lnpfoZ=pCP=tW(zZz~ zF5#%8Juk6WCHzRzK9ks&68L6 z{t21xo?(}4$t!|N(o?sNUb)4K(teyCdmgQf;;?IJgxNZT=c;{;Hp=Z0H@1JWkjI$L4ublzO zL!Me@^56qQXEM;J?2uL!K&}K0IaRH%_&}E^_aU_-y)Qj-xKP|Za;We>sMrBkm+M~! z@2+{u$S+No<(|II%!?gt{p} P?*czhv}y0s?aja+nFGQf literal 0 HcmV?d00001 diff --git a/src/mainboard/google/glados/variants/sentry/data.vbt b/src/mainboard/google/glados/variants/sentry/data.vbt new file mode 100644 index 0000000000000000000000000000000000000000..0aac82c3b18d3bb71258b1a04aaadf8dee2152e9 GIT binary patch literal 4608 zcmeHKUu;ul6hF7Of4_TgcXx+U3eF=UbOW~A0Tbqw+qHw0b*x>-9MOahT6D3nu?;i) zM~yQfF_=F12My6Bz8HL2Vtg`2UW`kK%8U3YFD6JdF%jbna6R9>m$kT%H5mV3IPLk) z`Of$C_nq_oJzX=@HHg{Xy{TAlH#(FD9p=>yR4%5jWPf&FA~qP?*Olsz_u@IY7v5H{ zUk1nv!U{R6>(S)lsX{R_&_u8)>>JxZS}e3C3X{)Fjg4bEp2XOJ1BGH?Vq~h2$L!F~ z7;;R7bsZfo=5hDYL;DL89Y{br^~UJtmQ9-xqpfZ9)uUTT)jOi?9b2|3EYThB?@K3B zvB6~jZtNexL^2!8X1n{kQhPBy(BG5nN)C1>6t)mXd~E#K#OPB`Phlk9gl#m&Mhnz( z8RKIU<1H8~7IA?0nZ$v@WMSgjLcT>|9ONwc-2#B%fw~w7aIFo%zwlMTZGaoWt%8AI zsDLVObpsdx2%vH&RB&w(Tx4782XBa5ZVe#I3~Jh~vb4#E%n?5POfpRnt}COF&c-99eHmP~Gr)6O>Ln_S23% z@Cz+A5p$&ENXuA5VVXW4TsOZCfob|5Kw%3B2dT%ADNBlC+Nlqc|&p&b46I@0NFG;N}@v z)dLp-r7~W;Pxa?k+ii`vXSx4L+LJCnT?_^wsWS9H1VWI2HLwhFkhbzBKUgnswHLLS z5TS0-Ppe@7B4GlbyxB&zGeiJQZ-Dp+!x5%UGWH_F5194|W1lnpfoZ=pCP=tW(zZz~ zF5#%8Juk6WCHzRzK9ks&68L6 z{t21xo?(}4$t!|N(o?sNUb)4K(teyCdmgQf;;?IJgxNZT=c;{;Hp=Z0H@1JWkjI$L4ublzO zL!Me@^56qQXEM;J?2uL!K&}K0IaRH%_&}E^_aU_-y)Qj-xKP|Za;We>sMrBkm+M~! z@2+{u$S+No<(|II%!?gt{p} P?*czhv}y0s?aja+nFGQf literal 0 HcmV?d00001 From 57368465817341663d9d1e7f5565dbb3cd2020f8 Mon Sep 17 00:00:00 2001 From: Martin Roth Date: Sat, 30 Nov 2019 20:26:53 -0700 Subject: [PATCH 0492/1242] superio/aspeed: Remove unused aspeed include path Working on some other code, I noticed that superio/aspeed was added as an include path even though I wasn't using it. I investigated and found that NOTHING is using it. The files in the aspeed directory all reference files in their own directory. The supermicro x11-lga1151-series boards are the only ones using this SIO. TEST=util/abuild/abuild -t supermicro/x11-lga1151-series Signed-off-by: Martin Roth Change-Id: I377066451a50452c17c9bfaa0f815f69e039984e Reviewed-on: https://review.coreboot.org/c/coreboot/+/37390 Tested-by: build bot (Jenkins) Reviewed-by: HAOUAS Elyes Reviewed-by: Angel Pons --- src/superio/aspeed/Makefile.inc | 2 -- 1 file changed, 2 deletions(-) diff --git a/src/superio/aspeed/Makefile.inc b/src/superio/aspeed/Makefile.inc index 6d0cc263e9..b9494fae61 100644 --- a/src/superio/aspeed/Makefile.inc +++ b/src/superio/aspeed/Makefile.inc @@ -20,5 +20,3 @@ bootblock-$(CONFIG_SUPERIO_ASPEED_COMMON_PRE_RAM) += common/early_serial.c subdirs-y += ast2400 subdirs-y += common - -CPPFLAGS_common += -Isrc/superio/aspeed From bd36ea9866372e29ebf7c5bfd2c44dcef6c6e485 Mon Sep 17 00:00:00 2001 From: Maulik V Vaghela Date: Sat, 30 Nov 2019 18:39:27 +0530 Subject: [PATCH 0493/1242] soc/intel/tigerlake: Change compilation based on TIGERLAKE_BASE since we support JSL and TGL soc under tigerlake folder, we need to make sure all soc related files get compiled based on CONFIG_SOC_INTEL_TIGERLAKE_BASE and not only for Tigerlake. We can control soc specific file compilation through Kconfig of individual soc. Change-Id: I1a663555d0bdf7588c4e12363375e7c90629f7d9 Signed-off-by: Maulik V Vaghela Reviewed-on: https://review.coreboot.org/c/coreboot/+/37376 Tested-by: build bot (Jenkins) Reviewed-by: Angel Pons Reviewed-by: Aamir Bohra --- src/soc/intel/tigerlake/Makefile.inc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/soc/intel/tigerlake/Makefile.inc b/src/soc/intel/tigerlake/Makefile.inc index b402fa0d63..0d5aecb328 100644 --- a/src/soc/intel/tigerlake/Makefile.inc +++ b/src/soc/intel/tigerlake/Makefile.inc @@ -1,4 +1,4 @@ -ifeq ($(CONFIG_SOC_INTEL_TIGERLAKE),y) +ifeq ($(CONFIG_SOC_INTEL_TIGERLAKE_BASE),y) subdirs-y += romstage subdirs-y += ../../../cpu/intel/microcode From b7f30ad25f8803e8e88963550b7ff4eb0d86dcdb Mon Sep 17 00:00:00 2001 From: Kane Chen Date: Wed, 27 Nov 2019 16:47:55 +0800 Subject: [PATCH 0494/1242] mb/google/hatch/variants/helios: DPTF solution update Modify DPTF parameters. BUG=b:131272830 BRANCH=firmware-hatch-12672.B TEST=emerge-hatch coreboot chromeos-bootimage Signed-off-by: Kane Chen Change-Id: I93930525edf4c5efb6b73bdfc8f16950754f7c9a Reviewed-on: https://review.coreboot.org/c/coreboot/+/37272 Reviewed-by: Sumeet R Pawnikar Tested-by: build bot (Jenkins) --- .../helios/include/variant/acpi/dptf.asl | 22 +++++++------------ 1 file changed, 8 insertions(+), 14 deletions(-) diff --git a/src/mainboard/google/hatch/variants/helios/include/variant/acpi/dptf.asl b/src/mainboard/google/hatch/variants/helios/include/variant/acpi/dptf.asl index 20a61d7df4..a359284680 100644 --- a/src/mainboard/google/hatch/variants/helios/include/variant/acpi/dptf.asl +++ b/src/mainboard/google/hatch/variants/helios/include/variant/acpi/dptf.asl @@ -18,16 +18,16 @@ #define DPTF_TSR0_SENSOR_ID 0 #define DPTF_TSR0_SENSOR_NAME "Battery Charger" -#define DPTF_TSR0_PASSIVE 50 +#define DPTF_TSR0_PASSIVE 59 #define DPTF_TSR0_CRITICAL 80 #define DPTF_TSR1_SENSOR_ID 1 #define DPTF_TSR1_SENSOR_NAME "5V Regulator" #define DPTF_TSR1_PASSIVE 0 #define DPTF_TSR1_CRITICAL 70 -#define DPTF_TSR1_ACTIVE_AC0 43 -#define DPTF_TSR1_ACTIVE_AC1 40 -#define DPTF_TSR1_ACTIVE_AC2 38 +#define DPTF_TSR1_ACTIVE_AC0 42 +#define DPTF_TSR1_ACTIVE_AC1 41 +#define DPTF_TSR1_ACTIVE_AC2 39 #define DPTF_TSR2_SENSOR_ID 2 #define DPTF_TSR2_SENSOR_NAME "Ambient" @@ -36,14 +36,8 @@ #define DPTF_TSR3_SENSOR_ID 3 #define DPTF_TSR3_SENSOR_NAME "CPU" -#define DPTF_TSR3_PASSIVE 90 -#define DPTF_TSR3_CRITICAL 105 -#define DPTF_TSR3_ACTIVE_AC0 87 -#define DPTF_TSR3_ACTIVE_AC1 85 -#define DPTF_TSR3_ACTIVE_AC2 83 -#define DPTF_TSR3_ACTIVE_AC3 80 -#define DPTF_TSR3_ACTIVE_AC4 78 -#define DPTF_TSR3_ACTIVE_AC5 75 +#define DPTF_TSR3_PASSIVE 44 +#define DPTF_TSR3_CRITICAL 90 #define DPTF_ENABLE_CHARGER #define DPTF_ENABLE_FAN_CONTROL @@ -91,7 +85,7 @@ Name (DART, Package () { 0, 0, 0 }, Package () { - \_SB.DPTF.TFN1, \_SB.DPTF.TSR1, 100, 100, 80, 60, 0, 0, 0, 0, + \_SB.DPTF.TFN1, \_SB.DPTF.TSR1, 100, 90, 70, 50, 0, 0, 0, 0, 0, 0, 0 }, Package () { @@ -99,7 +93,7 @@ Name (DART, Package () { 0, 0, 0 }, Package () { - \_SB.DPTF.TFN1, \_SB.DPTF.TSR3, 100, 90, 69, 56, 46, 36, 30, 0, + \_SB.DPTF.TFN1, \_SB.DPTF.TSR3, 100, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }) From e58eafc45a67a25ffd19b43d9bd845290a87b71c Mon Sep 17 00:00:00 2001 From: Praveen Hodagatta Pranesh Date: Wed, 27 Nov 2019 13:47:09 +0800 Subject: [PATCH 0495/1242] soc/intel/cannonlake: Fix compilation Change MicrocodeRegionLength to MicrocodeRegionSize as per coffeelake FsptUpd.h. TEST= Build with CONFIG_USE_CANNONLAKE_FSP_CAR selected and boot test on coffeelake RVP. Change-Id: Iebbf5c34e289870a4d7abdd49fd81e4db236051a Signed-off-by: Praveen Hodagatta Pranesh Reviewed-on: https://review.coreboot.org/c/coreboot/+/37265 Reviewed-by: Subrata Banik Tested-by: build bot (Jenkins) --- src/soc/intel/cannonlake/bootblock/bootblock.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/soc/intel/cannonlake/bootblock/bootblock.c b/src/soc/intel/cannonlake/bootblock/bootblock.c index 9f8539766c..6a6dd8be25 100644 --- a/src/soc/intel/cannonlake/bootblock/bootblock.c +++ b/src/soc/intel/cannonlake/bootblock/bootblock.c @@ -39,10 +39,10 @@ const FSPT_UPD temp_ram_init_params = { * All SoC since Gen-4 has above mechanism in place to load microcode * even before hitting CPU reset vector. Hence skipping FSP-T loading * microcode after CPU reset by passing '0' value to - * FSPT_UPD.MicrocodeRegionBase and FSPT_UPD.MicrocodeRegionLength. + * FSPT_UPD.MicrocodeRegionBase and FSPT_UPD.MicrocodeRegionSize. */ .MicrocodeRegionBase = 0, - .MicrocodeRegionLength = 0, + .MicrocodeRegionSize = 0, .CodeRegionBase = (uint32_t)(0x100000000ULL - CONFIG_ROM_SIZE), .CodeRegionSize = (uint32_t)CONFIG_ROM_SIZE, From ab62d940fe15a04bda3d8c17ed2f1b5585616d64 Mon Sep 17 00:00:00 2001 From: Praveen Hodagatta Pranesh Date: Wed, 27 Nov 2019 18:12:09 +0800 Subject: [PATCH 0496/1242] configs: Jenkins buildtest for FSP_CAR Change-Id: I004fc02bd84b7b8d5c5fb96451e59f143f0fe6d3 Signed-off-by: Praveen Hodagatta Pranesh Reviewed-on: https://review.coreboot.org/c/coreboot/+/37275 Tested-by: build bot (Jenkins) Reviewed-by: Angel Pons --- configs/config.intel.cfl_rvp11_fsp_car | 9 +++++++++ 1 file changed, 9 insertions(+) create mode 100644 configs/config.intel.cfl_rvp11_fsp_car diff --git a/configs/config.intel.cfl_rvp11_fsp_car b/configs/config.intel.cfl_rvp11_fsp_car new file mode 100644 index 0000000000..33192c4e1f --- /dev/null +++ b/configs/config.intel.cfl_rvp11_fsp_car @@ -0,0 +1,9 @@ +CONFIG_USE_BLOBS=y +CONFIG_VENDOR_INTEL=y +CONFIG_INTEL_GMA_VBT_FILE="3rdparty/fsp/CoffeeLakeFspBinPkg/SampleCode/Vbt/Vbt.bin" +CONFIG_BOARD_INTEL_COFFEELAKE_RVP11=y +CONFIG_ADD_FSP_BINARIES=y +CONFIG_USE_CANNONLAKE_FSP_CAR=y +CONFIG_RUN_FSP_GOP=y +CONFIG_FSP_USE_REPO=y +CONFIG_PAYLOAD_NONE=y From 1804b158969ab849ea7c6e47b1bb6b297c1f8e45 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ky=C3=B6sti=20M=C3=A4lkki?= Date: Mon, 25 Nov 2019 20:03:27 +0200 Subject: [PATCH 0497/1242] soc/amd/common: Inline ACPI MMIO accessors MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The overhead of pushing variables to stack exceeded the number of instructions the actual MMIO operation took and the build of google/aleena with inlined accessors turned out to be just slightly (<2 KiB) smaller for the entire romstage or ramstage. Simple read-modify-write MMIO cycles should optimise better now. IO cycles with index/data register are borderline, at first sight assembly looked better by not inlining them. Change-Id: If2c37c9886a0151183aa6dd80eb068d6c67b3848 Signed-off-by: Kyösti Mälkki Reviewed-on: https://review.coreboot.org/c/coreboot/+/37211 Tested-by: build bot (Jenkins) Reviewed-by: Angel Pons --- src/soc/amd/common/block/acpimmio/mmio_util.c | 271 -------------- .../common/block/include/amdblocks/acpimmio.h | 353 +++++++++++++----- 2 files changed, 265 insertions(+), 359 deletions(-) diff --git a/src/soc/amd/common/block/acpimmio/mmio_util.c b/src/soc/amd/common/block/acpimmio/mmio_util.c index 1fc5fd4ed4..04d5e4af4d 100644 --- a/src/soc/amd/common/block/acpimmio/mmio_util.c +++ b/src/soc/amd/common/block/acpimmio/mmio_util.c @@ -15,7 +15,6 @@ #include #include -#include #include #include @@ -65,101 +64,6 @@ void pm_io_write32(uint8_t reg, uint32_t value) pm_io_write16(reg + sizeof(uint16_t), value & 0xffff); } -u8 sm_pci_read8(u8 reg) -{ - return read8((void *)(ACPIMMIO_SM_PCI_BASE + reg)); -} - -u16 sm_pci_read16(u8 reg) -{ - return read16((void *)(ACPIMMIO_SM_PCI_BASE + reg)); -} - -u32 sm_pci_read32(u8 reg) -{ - return read32((void *)(ACPIMMIO_SM_PCI_BASE + reg)); -} - -void sm_pci_write8(u8 reg, u8 value) -{ - write8((void *)(ACPIMMIO_SM_PCI_BASE + reg), value); -} - -void sm_pci_write16(u8 reg, u16 value) -{ - write16((void *)(ACPIMMIO_SM_PCI_BASE + reg), value); -} - -void sm_pci_write32(u8 reg, u32 value) -{ - write32((void *)(ACPIMMIO_SM_PCI_BASE + reg), value); -} - -uint8_t smi_read8(uint8_t reg) -{ - return read8((void *)(ACPIMMIO_SMI_BASE + reg)); -} - -uint16_t smi_read16(uint8_t reg) -{ - return read16((void *)(ACPIMMIO_SMI_BASE + reg)); -} - -uint32_t smi_read32(uint8_t reg) -{ - return read32((void *)(ACPIMMIO_SMI_BASE + reg)); -} - -void smi_write8(uint8_t reg, uint8_t value) -{ - write8((void *)(ACPIMMIO_SMI_BASE + reg), value); -} - -void smi_write16(uint8_t reg, uint16_t value) -{ - write16((void *)(ACPIMMIO_SMI_BASE + reg), value); -} - -void smi_write32(uint8_t reg, uint32_t value) -{ - write32((void *)(ACPIMMIO_SMI_BASE + reg), value); -} - -u8 pm_read8(u8 reg) -{ - return read8((void *)(ACPIMMIO_PMIO_BASE + reg)); -} - -u16 pm_read16(u8 reg) -{ - return read16((void *)(ACPIMMIO_PMIO_BASE + reg)); -} - -u32 pm_read32(u8 reg) -{ - return read32((void *)(ACPIMMIO_PMIO_BASE + reg)); -} - -void pm_write8(u8 reg, u8 value) -{ - write8((void *)(ACPIMMIO_PMIO_BASE + reg), value); -} - -void pm_write16(u8 reg, u16 value) -{ - write16((void *)(ACPIMMIO_PMIO_BASE + reg), value); -} - -void pm_write32(u8 reg, u32 value) -{ - write32((void *)(ACPIMMIO_PMIO_BASE + reg), value); -} - -uint8_t biosram_read8(uint8_t reg) -{ - return read8((void *)(ACPIMMIO_BIOSRAM_BASE + reg)); -} - uint16_t biosram_read16(uint8_t reg) /* Must be 1 byte at a time */ { return (biosram_read8(reg + sizeof(uint8_t)) << 8 | biosram_read8(reg)); @@ -171,11 +75,6 @@ uint32_t biosram_read32(uint8_t reg) return value | biosram_read16(reg); } -void biosram_write8(uint8_t reg, uint8_t value) -{ - write8((void *)(ACPIMMIO_BIOSRAM_BASE + reg), value); -} - void biosram_write16(uint8_t reg, uint16_t value) { biosram_write8(reg, value & 0xff); @@ -189,173 +88,3 @@ void biosram_write32(uint8_t reg, uint32_t value) value >>= 16; biosram_write16(reg + sizeof(uint16_t), value & 0xffff); } - -u8 acpi_read8(u8 reg) -{ - return read8((void *)(ACPIMMIO_ACPI_BASE + reg)); -} - -u16 acpi_read16(u8 reg) -{ - return read16((void *)(ACPIMMIO_ACPI_BASE + reg)); -} - -u32 acpi_read32(u8 reg) -{ - return read32((void *)(ACPIMMIO_ACPI_BASE + reg)); -} - -void acpi_write8(u8 reg, u8 value) -{ - write8((void *)(ACPIMMIO_ACPI_BASE + reg), value); -} - -void acpi_write16(u8 reg, u16 value) -{ - write16((void *)(ACPIMMIO_ACPI_BASE + reg), value); -} - -void acpi_write32(u8 reg, u32 value) -{ - write32((void *)(ACPIMMIO_ACPI_BASE + reg), value); -} - -u8 asf_read8(u8 reg) -{ - return read8((void *)(ACPIMMIO_ASF_BASE + reg)); -} - -u16 asf_read16(u8 reg) -{ - return read16((void *)(ACPIMMIO_ASF_BASE + reg)); -} - -void asf_write8(u8 reg, u8 value) -{ - write8((void *)(ACPIMMIO_ASF_BASE + reg), value); -} - -void asf_write16(u8 reg, u16 value) -{ - write16((void *)(ACPIMMIO_ASF_BASE + reg), value); -} - -u8 smbus_read8(u8 reg) -{ - return read8((void *)(ACPIMMIO_SMBUS_BASE + reg)); -} - -u16 smbus_read16(u8 reg) -{ - return read16((void *)(ACPIMMIO_SMBUS_BASE + reg)); -} - -void smbus_write8(u8 reg, u8 value) -{ - write8((void *)(ACPIMMIO_SMBUS_BASE + reg), value); -} - -void smbus_write16(u8 reg, u16 value) -{ - write16((void *)(ACPIMMIO_SMBUS_BASE + reg), value); -} - -u8 iomux_read8(u8 reg) -{ - return read8((void *)(ACPIMMIO_IOMUX_BASE + reg)); -} - -u16 iomux_read16(u8 reg) -{ - return read16((void *)(ACPIMMIO_IOMUX_BASE + reg)); -} - -u32 iomux_read32(u8 reg) -{ - return read32((void *)(ACPIMMIO_IOMUX_BASE + reg)); -} - -void iomux_write8(u8 reg, u8 value) -{ - write8((void *)(ACPIMMIO_IOMUX_BASE + reg), value); -} - -void iomux_write16(u8 reg, u16 value) -{ - write16((void *)(ACPIMMIO_IOMUX_BASE + reg), value); -} - -void iomux_write32(u8 reg, u32 value) -{ - write32((void *)(ACPIMMIO_IOMUX_BASE + reg), value); -} - -u8 misc_read8(u8 reg) -{ - return read8((void *)(ACPIMMIO_MISC_BASE + reg)); -} - -u16 misc_read16(u8 reg) -{ - return read16((void *)(ACPIMMIO_MISC_BASE + reg)); -} - -u32 misc_read32(u8 reg) -{ - return read32((void *)(ACPIMMIO_MISC_BASE + reg)); -} - -void misc_write8(u8 reg, u8 value) -{ - write8((void *)(ACPIMMIO_MISC_BASE + reg), value); -} - -void misc_write16(u8 reg, u16 value) -{ - write16((void *)(ACPIMMIO_MISC_BASE + reg), value); -} - -void misc_write32(u8 reg, u32 value) -{ - write32((void *)(ACPIMMIO_MISC_BASE + reg), value); -} - -uint8_t xhci_pm_read8(uint8_t reg) -{ - return read8((void *)(ACPIMMIO_XHCIPM_BASE + reg)); -} - -uint16_t xhci_pm_read16(uint8_t reg) -{ - return read16((void *)(ACPIMMIO_XHCIPM_BASE + reg)); -} - -uint32_t xhci_pm_read32(uint8_t reg) -{ - return read32((void *)(ACPIMMIO_XHCIPM_BASE + reg)); -} - -void xhci_pm_write8(uint8_t reg, uint8_t value) -{ - write8((void *)(ACPIMMIO_XHCIPM_BASE + reg), value); -} - -void xhci_pm_write16(uint8_t reg, uint16_t value) -{ - write16((void *)(ACPIMMIO_XHCIPM_BASE + reg), value); -} - -void xhci_pm_write32(uint8_t reg, uint32_t value) -{ - write32((void *)(ACPIMMIO_XHCIPM_BASE + reg), value); -} - -u8 aoac_read8(u8 reg) -{ - return read8((void *)(ACPIMMIO_AOAC_BASE + reg)); -} - -void aoac_write8(u8 reg, u8 value) -{ - write8((void *)(ACPIMMIO_AOAC_BASE + reg), value); -} diff --git a/src/soc/amd/common/block/include/amdblocks/acpimmio.h b/src/soc/amd/common/block/include/amdblocks/acpimmio.h index b395cdba9c..57d24db5b2 100644 --- a/src/soc/amd/common/block/include/amdblocks/acpimmio.h +++ b/src/soc/amd/common/block/include/amdblocks/acpimmio.h @@ -18,7 +18,10 @@ #ifndef __AMDBLOCKS_ACPIMMIO_H__ #define __AMDBLOCKS_ACPIMMIO_H__ +#include #include +#include +#include /* * The following AcpiMmio register block mapping represents definitions @@ -100,14 +103,6 @@ /* Enable the AcpiMmio range at 0xfed80000 */ void enable_acpimmio_decode(void); -/* Access SMBus PCI registers at 0xfed80000 */ -uint8_t sm_pci_read8(uint8_t reg); -uint16_t sm_pci_read16(uint8_t reg); -uint32_t sm_pci_read32(uint8_t reg); -void sm_pci_write8(uint8_t reg, uint8_t value); -void sm_pci_write16(uint8_t reg, uint16_t value); -void sm_pci_write32(uint8_t reg, uint32_t value); - /* Access PM registers using IO cycles */ uint8_t pm_io_read8(uint8_t reg); uint16_t pm_io_read16(uint8_t reg); @@ -116,100 +111,282 @@ void pm_io_write8(uint8_t reg, uint8_t value); void pm_io_write16(uint8_t reg, uint16_t value); void pm_io_write32(uint8_t reg, uint32_t value); -/* Access SMI registers at 0xfed80100 */ -uint8_t smi_read8(uint8_t reg); -uint16_t smi_read16(uint8_t reg); -uint32_t smi_read32(uint8_t reg); -void smi_write8(uint8_t reg, uint8_t value); -void smi_write16(uint8_t reg, uint16_t value); -void smi_write32(uint8_t reg, uint32_t value); - -/* Access Power Management registers at 0xfed80300 */ -uint8_t pm_read8(uint8_t reg); -uint16_t pm_read16(uint8_t reg); -uint32_t pm_read32(uint8_t reg); -void pm_write8(uint8_t reg, uint8_t value); -void pm_write16(uint8_t reg, uint16_t value); -void pm_write32(uint8_t reg, uint32_t value); - -/* Access Power Management 2 registers at 0xfed80400 */ -uint8_t pm2_read8(uint8_t reg); -uint16_t pm2_read16(uint8_t reg); -uint32_t pm2_read32(uint8_t reg); -void pm2_write8(uint8_t reg, uint8_t value); -void pm2_write16(uint8_t reg, uint16_t value); -void pm2_write32(uint8_t reg, uint32_t value); /* Access BIOS RAM storage at 0xfed80500 */ -uint8_t biosram_read8(uint8_t reg); uint16_t biosram_read16(uint8_t reg); uint32_t biosram_read32(uint8_t reg); -void biosram_write8(uint8_t reg, uint8_t value); void biosram_write16(uint8_t reg, uint16_t value); void biosram_write32(uint8_t reg, uint32_t value); -/* Access ACPI registers at 0xfed80800 */ -uint8_t acpi_read8(uint8_t reg); -uint16_t acpi_read16(uint8_t reg); -uint32_t acpi_read32(uint8_t reg); -void acpi_write8(uint8_t reg, uint8_t value); -void acpi_write16(uint8_t reg, uint16_t value); -void acpi_write32(uint8_t reg, uint32_t value); -/* Access ASF controller registers at 0xfed80900 */ -uint8_t asf_read8(uint8_t reg); -uint16_t asf_read16(uint8_t reg); -void asf_write8(uint8_t reg, uint8_t value); -void asf_write16(uint8_t reg, uint16_t value); +static inline uint8_t sm_pci_read8(uint8_t reg) +{ + return read8((void *)(ACPIMMIO_SM_PCI_BASE + reg)); +} -/* Access SMBus controller registers at 0xfed80a00 */ -uint8_t smbus_read8(uint8_t reg); -uint16_t smbus_read16(uint8_t reg); -void smbus_write8(uint8_t reg, uint8_t value); -void smbus_write16(uint8_t reg, uint16_t value); +static inline uint16_t sm_pci_read16(uint8_t reg) +{ + return read16((void *)(ACPIMMIO_SM_PCI_BASE + reg)); +} -/* Access WDT registers at 0xfed80b00 */ -uint8_t wdt_read8(uint8_t reg); -uint16_t wdt_read16(uint8_t reg); -uint32_t wdt_read32(uint8_t reg); -void wdt_write8(uint8_t reg, uint8_t value); -void wdt_write16(uint8_t reg, uint16_t value); -void wdt_write32(uint8_t reg, uint32_t value); +static inline uint32_t sm_pci_read32(uint8_t reg) +{ + return read32((void *)(ACPIMMIO_SM_PCI_BASE + reg)); +} -/* Access HPET registers at 0xfed80c00 */ -uint8_t hpet_read8(uint8_t reg); -uint16_t hpet_read16(uint8_t reg); -uint32_t hpet_read32(uint8_t reg); -void hpet_write8(uint8_t reg, uint8_t value); -void hpet_write16(uint8_t reg, uint16_t value); -void hpet_write32(uint8_t reg, uint32_t value); +static inline void sm_pci_write8(uint8_t reg, uint8_t value) +{ + write8((void *)(ACPIMMIO_SM_PCI_BASE + reg), value); +} -/* Access GPIO MUX registers at 0xfed80d00 */ -uint8_t iomux_read8(uint8_t reg); -uint16_t iomux_read16(uint8_t reg); -uint32_t iomux_read32(uint8_t reg); -void iomux_write8(uint8_t reg, uint8_t value); -void iomux_write16(uint8_t reg, uint16_t value); -void iomux_write32(uint8_t reg, uint32_t value); +static inline void sm_pci_write16(uint8_t reg, uint16_t value) +{ + write16((void *)(ACPIMMIO_SM_PCI_BASE + reg), value); +} -/* Access Miscellaneous registers at 0xfed80e00 */ -uint8_t misc_read8(uint8_t reg); -uint16_t misc_read16(uint8_t reg); -uint32_t misc_read32(uint8_t reg); -void misc_write8(uint8_t reg, uint8_t value); -void misc_write16(uint8_t reg, uint16_t value); -void misc_write32(uint8_t reg, uint32_t value); +static inline void sm_pci_write32(uint8_t reg, uint32_t value) +{ + write32((void *)(ACPIMMIO_SM_PCI_BASE + reg), value); +} -/* Access xHCI Power Management registers at 0xfed81c00 */ -uint8_t xhci_pm_read8(uint8_t reg); -uint16_t xhci_pm_read16(uint8_t reg); -uint32_t xhci_pm_read32(uint8_t reg); -void xhci_pm_write8(uint8_t reg, uint8_t value); -void xhci_pm_write16(uint8_t reg, uint16_t value); -void xhci_pm_write32(uint8_t reg, uint32_t value); +static inline uint8_t smi_read8(uint8_t reg) +{ + return read8((void *)(ACPIMMIO_SMI_BASE + reg)); +} -/* Access Always On Always Connect registers at 0xfed81e00 */ -uint8_t aoac_read8(uint8_t reg); -void aoac_write8(uint8_t reg, uint8_t value); +static inline uint16_t smi_read16(uint8_t reg) +{ + return read16((void *)(ACPIMMIO_SMI_BASE + reg)); +} + +static inline uint32_t smi_read32(uint8_t reg) +{ + return read32((void *)(ACPIMMIO_SMI_BASE + reg)); +} + +static inline void smi_write8(uint8_t reg, uint8_t value) +{ + write8((void *)(ACPIMMIO_SMI_BASE + reg), value); +} + +static inline void smi_write16(uint8_t reg, uint16_t value) +{ + write16((void *)(ACPIMMIO_SMI_BASE + reg), value); +} + +static inline void smi_write32(uint8_t reg, uint32_t value) +{ + write32((void *)(ACPIMMIO_SMI_BASE + reg), value); +} + +static inline uint8_t pm_read8(uint8_t reg) +{ + return read8((void *)(ACPIMMIO_PMIO_BASE + reg)); +} + +static inline uint16_t pm_read16(uint8_t reg) +{ + return read16((void *)(ACPIMMIO_PMIO_BASE + reg)); +} + +static inline uint32_t pm_read32(uint8_t reg) +{ + return read32((void *)(ACPIMMIO_PMIO_BASE + reg)); +} + +static inline void pm_write8(uint8_t reg, uint8_t value) +{ + write8((void *)(ACPIMMIO_PMIO_BASE + reg), value); +} + +static inline void pm_write16(uint8_t reg, uint16_t value) +{ + write16((void *)(ACPIMMIO_PMIO_BASE + reg), value); +} + +static inline void pm_write32(uint8_t reg, uint32_t value) +{ + write32((void *)(ACPIMMIO_PMIO_BASE + reg), value); +} + +static inline uint8_t biosram_read8(uint8_t reg) +{ + return read8((void *)(ACPIMMIO_BIOSRAM_BASE + reg)); +} + +static inline void biosram_write8(uint8_t reg, uint8_t value) +{ + write8((void *)(ACPIMMIO_BIOSRAM_BASE + reg), value); +} + +static inline uint8_t acpi_read8(uint8_t reg) +{ + return read8((void *)(ACPIMMIO_ACPI_BASE + reg)); +} + +static inline uint16_t acpi_read16(uint8_t reg) +{ + return read16((void *)(ACPIMMIO_ACPI_BASE + reg)); +} + +static inline uint32_t acpi_read32(uint8_t reg) +{ + return read32((void *)(ACPIMMIO_ACPI_BASE + reg)); +} + +static inline void acpi_write8(uint8_t reg, uint8_t value) +{ + write8((void *)(ACPIMMIO_ACPI_BASE + reg), value); +} + +static inline void acpi_write16(uint8_t reg, uint16_t value) +{ + write16((void *)(ACPIMMIO_ACPI_BASE + reg), value); +} + +static inline void acpi_write32(uint8_t reg, uint32_t value) +{ + write32((void *)(ACPIMMIO_ACPI_BASE + reg), value); +} + +static inline uint8_t asf_read8(uint8_t reg) +{ + return read8((void *)(ACPIMMIO_ASF_BASE + reg)); +} + +static inline uint16_t asf_read16(uint8_t reg) +{ + return read16((void *)(ACPIMMIO_ASF_BASE + reg)); +} + +static inline void asf_write8(uint8_t reg, uint8_t value) +{ + write8((void *)(ACPIMMIO_ASF_BASE + reg), value); +} + +static inline void asf_write16(uint8_t reg, uint16_t value) +{ + write16((void *)(ACPIMMIO_ASF_BASE + reg), value); +} + +static inline uint8_t smbus_read8(uint8_t reg) +{ + return read8((void *)(ACPIMMIO_SMBUS_BASE + reg)); +} + +static inline uint16_t smbus_read16(uint8_t reg) +{ + return read16((void *)(ACPIMMIO_SMBUS_BASE + reg)); +} + +static inline void smbus_write8(uint8_t reg, uint8_t value) +{ + write8((void *)(ACPIMMIO_SMBUS_BASE + reg), value); +} + +static inline void smbus_write16(uint8_t reg, uint16_t value) +{ + write16((void *)(ACPIMMIO_SMBUS_BASE + reg), value); +} + +static inline uint8_t iomux_read8(uint8_t reg) +{ + return read8((void *)(ACPIMMIO_IOMUX_BASE + reg)); +} + +static inline uint16_t iomux_read16(uint8_t reg) +{ + return read16((void *)(ACPIMMIO_IOMUX_BASE + reg)); +} + +static inline uint32_t iomux_read32(uint8_t reg) +{ + return read32((void *)(ACPIMMIO_IOMUX_BASE + reg)); +} + +static inline void iomux_write8(uint8_t reg, uint8_t value) +{ + write8((void *)(ACPIMMIO_IOMUX_BASE + reg), value); +} + +static inline void iomux_write16(uint8_t reg, uint16_t value) +{ + write16((void *)(ACPIMMIO_IOMUX_BASE + reg), value); +} + +static inline void iomux_write32(uint8_t reg, uint32_t value) +{ + write32((void *)(ACPIMMIO_IOMUX_BASE + reg), value); +} + +static inline uint8_t misc_read8(uint8_t reg) +{ + return read8((void *)(ACPIMMIO_MISC_BASE + reg)); +} + +static inline uint16_t misc_read16(uint8_t reg) +{ + return read16((void *)(ACPIMMIO_MISC_BASE + reg)); +} + +static inline uint32_t misc_read32(uint8_t reg) +{ + return read32((void *)(ACPIMMIO_MISC_BASE + reg)); +} + +static inline void misc_write8(uint8_t reg, uint8_t value) +{ + write8((void *)(ACPIMMIO_MISC_BASE + reg), value); +} + +static inline void misc_write16(uint8_t reg, uint16_t value) +{ + write16((void *)(ACPIMMIO_MISC_BASE + reg), value); +} + +static inline void misc_write32(uint8_t reg, uint32_t value) +{ + write32((void *)(ACPIMMIO_MISC_BASE + reg), value); +} + +static inline uint8_t xhci_pm_read8(uint8_t reg) +{ + return read8((void *)(ACPIMMIO_XHCIPM_BASE + reg)); +} + +static inline uint16_t xhci_pm_read16(uint8_t reg) +{ + return read16((void *)(ACPIMMIO_XHCIPM_BASE + reg)); +} + +static inline uint32_t xhci_pm_read32(uint8_t reg) +{ + return read32((void *)(ACPIMMIO_XHCIPM_BASE + reg)); +} + +static inline void xhci_pm_write8(uint8_t reg, uint8_t value) +{ + write8((void *)(ACPIMMIO_XHCIPM_BASE + reg), value); +} + +static inline void xhci_pm_write16(uint8_t reg, uint16_t value) +{ + write16((void *)(ACPIMMIO_XHCIPM_BASE + reg), value); +} + +static inline void xhci_pm_write32(uint8_t reg, uint32_t value) +{ + write32((void *)(ACPIMMIO_XHCIPM_BASE + reg), value); +} + +static inline uint8_t aoac_read8(uint8_t reg) +{ + return read8((void *)(ACPIMMIO_AOAC_BASE + reg)); +} + +static inline void aoac_write8(uint8_t reg, uint8_t value) +{ + write8((void *)(ACPIMMIO_AOAC_BASE + reg), value); +} #endif /* __AMDBLOCKS_ACPIMMIO_H__ */ From 2d54fc9581ef01fe03ef114cd6718f7b352c01fc Mon Sep 17 00:00:00 2001 From: Sakari Ailus Date: Fri, 1 Nov 2019 12:10:40 +0200 Subject: [PATCH 0498/1242] mb/google/poppy: Declare output GPIOs as pull-downs The pull direction is used to determine the initial state of the pin. If no pull direction is specified, the pin will remain as input. Fix this. BUG=chromium:959232 Signed-off-by: Sakari Ailus Tested-by: Jacopo Mondi Change-Id: I1158bc8aaa447b223e8ce25d808348e758de28c5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/36721 Reviewed-by: Patrick Georgi Reviewed-by: Furquan Shaikh Tested-by: build bot (Jenkins) --- .../baseboard/include/baseboard/acpi/camera_pmic.asl | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/src/mainboard/google/poppy/variants/baseboard/include/baseboard/acpi/camera_pmic.asl b/src/mainboard/google/poppy/variants/baseboard/include/baseboard/acpi/camera_pmic.asl index 5eaf5b758a..d3fafe9510 100644 --- a/src/mainboard/google/poppy/variants/baseboard/include/baseboard/acpi/camera_pmic.asl +++ b/src/mainboard/google/poppy/variants/baseboard/include/baseboard/acpi/camera_pmic.asl @@ -142,21 +142,21 @@ Scope (\_SB.PCI0.I2C2) 2 } /* GPIO.4 is AVDD pin for user facing camera */ - GpioIo (Exclusive, PullDefault, 0x0000, 0x0000, + GpioIo (Exclusive, PullDown, 0x0000, 0x0000, IoRestrictionOutputOnly, "\\_SB.PCI0.I2C2.PMIC", 0x00, ResourceConsumer,,) { 4 } /* GPIO.5 is XSHUTDOWN pin for user facing camera */ - GpioIo (Exclusive, PullDefault, 0x0000, 0x0000, + GpioIo (Exclusive, PullDown, 0x0000, 0x0000, IoRestrictionOutputOnly, "\\_SB.PCI0.I2C2.PMIC", 0x00, ResourceConsumer,,) { 5 } /* GPIO.9 is XSHUTDOWN pin for world facing camera */ - GpioIo (Exclusive, PullDefault, 0x0000, 0x0000, + GpioIo (Exclusive, PullDown, 0x0000, 0x0000, IoRestrictionOutputOnly, "\\_SB.PCI0.I2C2.PMIC", 0x00, ResourceConsumer,,) { @@ -188,7 +188,7 @@ Scope (\_SB.PCI0.I2C2) GPO2, 1, Connection ( - GpioIo (Exclusive, PullDefault, 0x0000, 0x0000, + GpioIo (Exclusive, PullDown, 0x0000, 0x0000, IoRestrictionOutputOnly, "\\_SB.PCI0.I2C2.PMIC", 0x00, ResourceConsumer,,) @@ -199,7 +199,7 @@ Scope (\_SB.PCI0.I2C2) GRST, 1, Connection ( - GpioIo (Exclusive, PullDefault, 0x0000, 0x0000, + GpioIo (Exclusive, PullDown, 0x0000, 0x0000, IoRestrictionOutputOnly, "\\_SB.PCI0.I2C2.PMIC", 0x00, ResourceConsumer,,) @@ -210,7 +210,7 @@ Scope (\_SB.PCI0.I2C2) GPO4, 1, Connection ( - GpioIo (Exclusive, PullDefault, 0x0000, 0x0000, + GpioIo (Exclusive, PullDown, 0x0000, 0x0000, IoRestrictionOutputOnly, "\\_SB.PCI0.I2C2.PMIC", 0x00, ResourceConsumer,,) From ecfb4b81aeb91b94a20b57d7229e1a9da9d4722f Mon Sep 17 00:00:00 2001 From: Sakari Ailus Date: Fri, 1 Nov 2019 12:12:41 +0200 Subject: [PATCH 0499/1242] mb/google/poppy: Power on PMIC before accessing its opregion MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The PMIC opregion is used to change the direction of two GPIOs for I²C daisy chain operation. Do this after the PMIC is powered on, not before. BUG=chromium:959232 Reported-by: Laurent Pinchart Signed-off-by: Sakari Ailus Tested-by: Jacopo Mondi Change-Id: I923987ef21a971df9e32ca03f2da4dccdac07843 Reviewed-on: https://review.coreboot.org/c/coreboot/+/36722 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi Reviewed-by: Furquan Shaikh --- .../baseboard/include/baseboard/acpi/camera_pmic.asl | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/src/mainboard/google/poppy/variants/baseboard/include/baseboard/acpi/camera_pmic.asl b/src/mainboard/google/poppy/variants/baseboard/include/baseboard/acpi/camera_pmic.asl index d3fafe9510..12c3c22e1b 100644 --- a/src/mainboard/google/poppy/variants/baseboard/include/baseboard/acpi/camera_pmic.asl +++ b/src/mainboard/google/poppy/variants/baseboard/include/baseboard/acpi/camera_pmic.asl @@ -458,16 +458,16 @@ Scope (\_SB.PCI0.I2C2) /* TODO: Read Voltage and Sleep values from Sensor Obj */ If (LEqual (AVBL, 1)) { If (LEqual (STA, 0)) { + /* Enable VSIO regulator + + daisy chain */ + DOVD(1) + If (LEqual (C0GP, 0)) { \_SB.PCI0.I2C2.PMIC.CGP1() \_SB.PCI0.I2C2.PMIC.CGP2() C0GP = 1 } - /* Enable VSIO regulator + - daisy chain */ - DOVD(1) - VACT = 1 if (LNotEqual (ACVA, 109)) { /* Set ANA at 2.8152V */ From c0b9c8cbc014662dccdab98841a47dca2570dc0d Mon Sep 17 00:00:00 2001 From: Sakari Ailus Date: Fri, 1 Nov 2019 12:16:03 +0200 Subject: [PATCH 0500/1242] mb/google/poppy: Rework OV5670 power on sequence MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit In particular: - Enable regulators *after* configuring the voltage - Allow 1 ms for the voltages to settle - Enable clock after powering on regulators - Remove extra delays between enabling things. The sensor requires 8192 clock cycles after the reset is lifted before I²C access, so 1 ms is enough. - Make the delay after lifting xshutdown 10 ms. This guarantees that streaming will only start once the sensor has had enough time to settle after lifting the reset. BUG=chromium:959232 Signed-off-by: Sakari Ailus Tested-by: Jacopo Mondi Change-Id: I4589a7d7ec324f4520572a406cc11ad3feec8b21 Reviewed-on: https://review.coreboot.org/c/coreboot/+/36723 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi Reviewed-by: Furquan Shaikh --- .../include/baseboard/acpi/camera_pmic.asl | 35 ++++++++++++------- 1 file changed, 22 insertions(+), 13 deletions(-) diff --git a/src/mainboard/google/poppy/variants/baseboard/include/baseboard/acpi/camera_pmic.asl b/src/mainboard/google/poppy/variants/baseboard/include/baseboard/acpi/camera_pmic.asl index 12c3c22e1b..355b25528e 100644 --- a/src/mainboard/google/poppy/variants/baseboard/include/baseboard/acpi/camera_pmic.asl +++ b/src/mainboard/google/poppy/variants/baseboard/include/baseboard/acpi/camera_pmic.asl @@ -526,30 +526,39 @@ Scope (\_SB.PCI0.I2C2) daisy chain */ DOVD(1) - VAX2 = 1 /* Enable VAUX2 */ - if (LNotEqual (AX2V, 52)) { /* Set VAUX2 as 1.8006 V */ AX2V = 52 } + VAX2 = 1 /* Enable VAUX2 */ + + \_SB.PCI0.I2C2.PMIC.CGP4(1) + + /* + * Wait for DOVDD and AVDD + * to settle. + */ + Sleep(1) + + if (LNotEqual (AX1V, 19)) { + /* Set VAUX1 as 1.2132V */ + AX1V = 19 + } + VAX1 = 1 /* Enable VAUX1 */ + + /* Wait for VDD to settle. */ Sleep(1) \_SB.PCI0.I2C2.PMIC.CLKE() CLE1 = 1 - VAX1 = 1 /* Enable VAUX1 */ - if (LNotEqual (AX1V, 19)) { - /* Set VAUX1 as 1.2132V */ - AX1V = 19 - } - Sleep(3) - - \_SB.PCI0.I2C2.PMIC.CGP4(1) - Sleep(3) - \_SB.PCI0.I2C2.PMIC.CGP5(1) - Sleep(3) + /* + * Ensure 10 ms between + * power-up and streamon. + */ + Sleep(10) STA = 1 } } From be0dfef30c00dab0e4cb37f340f8424d8695f884 Mon Sep 17 00:00:00 2001 From: Sakari Ailus Date: Fri, 1 Nov 2019 18:01:24 +0200 Subject: [PATCH 0501/1242] mb/google/poppy: Rework OV13858 power on sequence In particular: - Set voltage before enabling regulators - Enable regulators and the clock without any sleeping in between. There's no need to wait there. - Sleep 1 ms in order to wait for regulator voltages settling before lifting xshutdown. BUG=chromium:959232 Signed-off-by: Sakari Ailus Tested-by: Jacopo Mondi Change-Id: I0f8857ae369d5038f293a0e2c48c681df535ad86 Reviewed-on: https://review.coreboot.org/c/coreboot/+/36744 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi Reviewed-by: Furquan Shaikh --- .../include/baseboard/acpi/camera_pmic.asl | 24 +++++++++++++------ 1 file changed, 17 insertions(+), 7 deletions(-) diff --git a/src/mainboard/google/poppy/variants/baseboard/include/baseboard/acpi/camera_pmic.asl b/src/mainboard/google/poppy/variants/baseboard/include/baseboard/acpi/camera_pmic.asl index 355b25528e..fc23d065b7 100644 --- a/src/mainboard/google/poppy/variants/baseboard/include/baseboard/acpi/camera_pmic.asl +++ b/src/mainboard/google/poppy/variants/baseboard/include/baseboard/acpi/camera_pmic.asl @@ -468,23 +468,33 @@ Scope (\_SB.PCI0.I2C2) C0GP = 1 } - VACT = 1 if (LNotEqual (ACVA, 109)) { /* Set ANA at 2.8152V */ ACVA = 109 } - Sleep(3) + VACT = 1 - \_SB.PCI0.I2C2.PMIC.CLKE() - CLE0 = 1 - - VDCT = 1 if (LNotEqual (DCVA, 12)) { /* Set CORE at 1.2V */ DCVA = 12 } - Sleep(3) + VDCT = 1 + + \_SB.PCI0.I2C2.PMIC.CLKE() + CLE0 = 1 + + /* + * Wait for all regulator + * outputs to settle. + */ + Sleep(1) + \_SB.PCI0.I2C2.PMIC.CRST(1) + + /* + * 5 ms needed before + * streaming on. + */ Sleep(5) STA = 1 From 68f0eb52696397d664c343dacef5c8b390a614e1 Mon Sep 17 00:00:00 2001 From: Sakari Ailus Date: Fri, 1 Nov 2019 12:09:28 +0200 Subject: [PATCH 0502/1242] mb/google/poppy: Remove redundant mutex The mutex is only used in one method and that method is serialised. Remove the mutex. BUG=chromium:959232 Reported-by: Laurent Pinchart Signed-off-by: Sakari Ailus Tested-by: Jacopo Mondi Change-Id: Ic173d557f4b49cc9e860d13b782fc4940fd80869 Reviewed-on: https://review.coreboot.org/c/coreboot/+/36745 Reviewed-by: Patrick Georgi Reviewed-by: Furquan Shaikh Tested-by: build bot (Jenkins) --- .../include/baseboard/acpi/camera_pmic.asl | 69 ++++++++----------- 1 file changed, 30 insertions(+), 39 deletions(-) diff --git a/src/mainboard/google/poppy/variants/baseboard/include/baseboard/acpi/camera_pmic.asl b/src/mainboard/google/poppy/variants/baseboard/include/baseboard/acpi/camera_pmic.asl index fc23d065b7..d70726f49e 100644 --- a/src/mainboard/google/poppy/variants/baseboard/include/baseboard/acpi/camera_pmic.asl +++ b/src/mainboard/google/poppy/variants/baseboard/include/baseboard/acpi/camera_pmic.asl @@ -400,50 +400,41 @@ Scope (\_SB.PCI0.I2C2) } /* Reference count for VSIO */ - Mutex (MUTV, 0) Name (VSIC, 0) Method (DOVD, 1, Serialized) { - /* Save Acquire result so we can check for - Mutex acquired */ - Store (Acquire (MUTV, 1000), Local0) - /* Check for Mutex acquired */ - If (LEqual (Local0, Zero)) { - /* Turn off VSIO */ - If (LEqual (Arg0, Zero)) { - /* Decrement only if VSIC > 0 */ - if (LGreater (VSIC, 0)) { - Decrement (VSIC) - If (LEqual (VSIC, Zero)) { - VSIO = 0 - Sleep(1) - PMOF() - } - } - } ElseIf (LEqual (Arg0, 1)) { - /* Increment only if VSIC < 4 */ - If (LLess (VSIC, 4)) { - /* Turn on VSIO */ - If (LEqual (VSIC, Zero)) { - PMON() - VSIO = 3 - - if (LNotEqual (IOVA, 52)) { - /* Set VSIO value as - 1.8006 V */ - IOVA = 52 - } - if (LNotEqual (SIOV, 52)) { - /* Set VSIO value as - 1.8006 V */ - SIOV = 52 - } - Sleep(3) - } - Increment (VSIC) + /* Turn off VSIO */ + If (LEqual (Arg0, Zero)) { + /* Decrement only if VSIC > 0 */ + if (LGreater (VSIC, 0)) { + Decrement (VSIC) + If (LEqual (VSIC, Zero)) { + VSIO = 0 + Sleep(1) + PMOF() } } + } ElseIf (LEqual (Arg0, 1)) { + /* Increment only if VSIC < 4 */ + If (LLess (VSIC, 4)) { + /* Turn on VSIO */ + If (LEqual (VSIC, Zero)) { + PMON() + VSIO = 3 - Release (MUTV) + if (LNotEqual (IOVA, 52)) { + /* Set VSIO value as + 1.8006 V */ + IOVA = 52 + } + if (LNotEqual (SIOV, 52)) { + /* Set VSIO value as + 1.8006 V */ + SIOV = 52 + } + Sleep(3) + } + Increment (VSIC) + } } } From 00517b687a03d6c9a760669c8fe1e89af2fc3884 Mon Sep 17 00:00:00 2001 From: Sakari Ailus Date: Fri, 1 Nov 2019 19:13:01 +0200 Subject: [PATCH 0503/1242] mb/google/poppy: Remove useless ifs around voltage and GPIO direction configuration The methods generally tested OP region settings and only changed them if they were not in their desired values. Instead, assign them directly without checking them. BUG=chromium:959232 Signed-off-by: Sakari Ailus Tested-by: Jacopo Mondi Change-Id: I3ceca4bd51c4410c7020431f4fd682c4ca925110 Reviewed-on: https://review.coreboot.org/c/coreboot/+/36746 Reviewed-by: Patrick Georgi Reviewed-by: Furquan Shaikh Tested-by: build bot (Jenkins) --- .../include/baseboard/acpi/camera_pmic.asl | 41 +++++-------------- 1 file changed, 11 insertions(+), 30 deletions(-) diff --git a/src/mainboard/google/poppy/variants/baseboard/include/baseboard/acpi/camera_pmic.asl b/src/mainboard/google/poppy/variants/baseboard/include/baseboard/acpi/camera_pmic.asl index d70726f49e..d15f5c63d8 100644 --- a/src/mainboard/google/poppy/variants/baseboard/include/baseboard/acpi/camera_pmic.asl +++ b/src/mainboard/google/poppy/variants/baseboard/include/baseboard/acpi/camera_pmic.asl @@ -438,10 +438,6 @@ Scope (\_SB.PCI0.I2C2) } } - /* C0GP is used to indicate if CAM0 - * GPIOs are configured as input. - */ - Name (C0GP, 0) /* Power resource methods for CAM0 */ PowerResource (OVTH, 0, 0) { Name (STA, 0) @@ -453,22 +449,15 @@ Scope (\_SB.PCI0.I2C2) daisy chain */ DOVD(1) - If (LEqual (C0GP, 0)) { - \_SB.PCI0.I2C2.PMIC.CGP1() - \_SB.PCI0.I2C2.PMIC.CGP2() - C0GP = 1 - } + \_SB.PCI0.I2C2.PMIC.CGP1() + \_SB.PCI0.I2C2.PMIC.CGP2() - if (LNotEqual (ACVA, 109)) { - /* Set ANA at 2.8152V */ - ACVA = 109 - } + /* Set ANA at 2.8152V */ + ACVA = 109 VACT = 1 - if (LNotEqual (DCVA, 12)) { - /* Set CORE at 1.2V */ - DCVA = 12 - } + /* Set CORE at 1.2V */ + DCVA = 12 VDCT = 1 \_SB.PCI0.I2C2.PMIC.CLKE() @@ -527,11 +516,8 @@ Scope (\_SB.PCI0.I2C2) daisy chain */ DOVD(1) - if (LNotEqual (AX2V, 52)) { - /* Set VAUX2 as - 1.8006 V */ - AX2V = 52 - } + /* Set VAUX2 as 1.8006 V */ + AX2V = 52 VAX2 = 1 /* Enable VAUX2 */ \_SB.PCI0.I2C2.PMIC.CGP4(1) @@ -542,10 +528,8 @@ Scope (\_SB.PCI0.I2C2) */ Sleep(1) - if (LNotEqual (AX1V, 19)) { /* Set VAUX1 as 1.2132V */ - AX1V = 19 - } + AX1V = 19 VAX1 = 1 /* Enable VAUX1 */ /* Wait for VDD to settle. */ @@ -603,11 +587,8 @@ Scope (\_SB.PCI0.I2C2) /* Enable VCM regulator */ VCMC = 1 - if (LNotEqual (VCMV, 109)) { - /* Set VCM value at - 2.8152 V */ - VCMV = 109 - } + /* Set VCM value at 2.8152 V */ + VCMV = 109 Sleep(3) STA = 1 From 2317b4f1140821051d8688a95fcfd7e0eedaa773 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Micha=C5=82=20=C5=BBygowski?= Date: Thu, 28 Nov 2019 12:59:44 +0100 Subject: [PATCH 0504/1242] sb/amd/cimx: replace cimx_util with common ACPIMMIO AMD block MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Drop the redundant cimx_util, remove the includes when appropriate and replace the implementation with amdblocks/acpimmio where needed. TEST=boot PC Engines apu1 and launch Debian with Linux kernel 4.14.50 Signed-off-by: Michał Żygowski Change-Id: I66b1f82926372b6ebb570893b6eb73c7f2935b9d Reviewed-on: https://review.coreboot.org/c/coreboot/+/37328 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki Reviewed-by: Patrick Georgi --- src/mainboard/amd/inagua/mainboard.c | 6 +-- src/mainboard/amd/persimmon/mainboard.c | 6 +-- src/mainboard/amd/south_station/mainboard.c | 6 +-- src/mainboard/amd/union_station/mainboard.c | 6 +-- src/mainboard/asrock/e350m1/mainboard.c | 6 +-- src/mainboard/elmex/pcm205400/mainboard.c | 6 +-- src/mainboard/gizmosphere/gizmo/mainboard.c | 1 - src/mainboard/jetway/nf81-t56n-lf/mainboard.c | 7 ++- .../lippert/frontrunner-af/mainboard.c | 6 +-- src/mainboard/lippert/toucan-af/mainboard.c | 6 +-- src/mainboard/pcengines/apu1/gpio_ftns.c | 17 ++----- src/mainboard/pcengines/apu1/mainboard.c | 1 - src/mainboard/pcengines/apu1/romstage.c | 10 ++-- src/mainboard/pcengines/apu2/gpio_ftns.c | 1 - src/southbridge/amd/cimx/Makefile.inc | 4 -- src/southbridge/amd/cimx/cimx_util.c | 51 ------------------- src/southbridge/amd/cimx/cimx_util.h | 37 -------------- src/southbridge/amd/cimx/sb800/Kconfig | 3 ++ src/southbridge/amd/cimx/sb800/fan.c | 12 ++--- 19 files changed, 46 insertions(+), 146 deletions(-) delete mode 100644 src/southbridge/amd/cimx/cimx_util.c delete mode 100644 src/southbridge/amd/cimx/cimx_util.h diff --git a/src/mainboard/amd/inagua/mainboard.c b/src/mainboard/amd/inagua/mainboard.c index cf40e262aa..83fe394be7 100644 --- a/src/mainboard/amd/inagua/mainboard.c +++ b/src/mainboard/amd/inagua/mainboard.c @@ -13,9 +13,9 @@ * GNU General Public License for more details. */ +#include #include #include -#include #include /* Platform Specific Definitions */ static void init_gpios(void) @@ -63,8 +63,8 @@ static void mainboard_enable(struct device *dev) * SPD read code has been made generic and moved out of the board * directory, so the ASF init is being done here. */ - pm_iowrite(0x29, 0x80); - pm_iowrite(0x28, 0x61); + pm_write8(0x29, 0x80); + pm_write8(0x28, 0x61); } struct chip_operations mainboard_ops = { diff --git a/src/mainboard/amd/persimmon/mainboard.c b/src/mainboard/amd/persimmon/mainboard.c index 43be863f4d..0e89ffde05 100644 --- a/src/mainboard/amd/persimmon/mainboard.c +++ b/src/mainboard/amd/persimmon/mainboard.c @@ -14,11 +14,11 @@ * GNU General Public License for more details. */ +#include #include #include #include #include -#include #include #include #include @@ -139,8 +139,8 @@ static void mainboard_enable(struct device *dev) * SPD read code has been made generic and moved out of the board * directory, so the ASF init is being done here. */ - pm_iowrite(0x29, 0x80); - pm_iowrite(0x28, 0x61); + pm_write8(0x29, 0x80); + pm_write8(0x28, 0x61); /* Initialize the PIRQ data structures for consumption */ pirq_setup(); diff --git a/src/mainboard/amd/south_station/mainboard.c b/src/mainboard/amd/south_station/mainboard.c index c6f219662f..9b041e0111 100644 --- a/src/mainboard/amd/south_station/mainboard.c +++ b/src/mainboard/amd/south_station/mainboard.c @@ -13,10 +13,10 @@ * GNU General Public License for more details. */ +#include #include #include #include -#include #include /* Platform Specific Definitions */ /** @@ -59,8 +59,8 @@ static void mainboard_enable(struct device *dev) * SPD read code has been made generic and moved out of the board * directory, so the ASF init is being done here. */ - pm_iowrite(0x29, 0x80); - pm_iowrite(0x28, 0x61); + pm_write8(0x29, 0x80); + pm_write8(0x28, 0x61); } struct chip_operations mainboard_ops = { diff --git a/src/mainboard/amd/union_station/mainboard.c b/src/mainboard/amd/union_station/mainboard.c index e2c0ac7370..d680520d47 100644 --- a/src/mainboard/amd/union_station/mainboard.c +++ b/src/mainboard/amd/union_station/mainboard.c @@ -13,9 +13,9 @@ * GNU General Public License for more details. */ +#include #include #include -#include #include /* Platform Specific Definitions */ /********************************************** @@ -31,8 +31,8 @@ static void mainboard_enable(struct device *dev) * SPD read code has been made generic and moved out of the board * directory, so the ASF init is being done here. */ - pm_iowrite(0x29, 0x80); - pm_iowrite(0x28, 0x61); + pm_write8(0x29, 0x80); + pm_write8(0x28, 0x61); } struct chip_operations mainboard_ops = { diff --git a/src/mainboard/asrock/e350m1/mainboard.c b/src/mainboard/asrock/e350m1/mainboard.c index b83a57f78d..e2f4f2b259 100644 --- a/src/mainboard/asrock/e350m1/mainboard.c +++ b/src/mainboard/asrock/e350m1/mainboard.c @@ -13,10 +13,10 @@ * GNU General Public License for more details. */ +#include #include #include #include -#include #include /********************************************** @@ -46,8 +46,8 @@ static void mainboard_enable(struct device *dev) * SPD read code has been made generic and moved out of the board * directory, so the ASF init is being done here. */ - pm_iowrite(0x29, 0x80); - pm_iowrite(0x28, 0x61); + pm_write8(0x29, 0x80); + pm_write8(0x28, 0x61); } struct chip_operations mainboard_ops = { diff --git a/src/mainboard/elmex/pcm205400/mainboard.c b/src/mainboard/elmex/pcm205400/mainboard.c index 43be863f4d..0e89ffde05 100644 --- a/src/mainboard/elmex/pcm205400/mainboard.c +++ b/src/mainboard/elmex/pcm205400/mainboard.c @@ -14,11 +14,11 @@ * GNU General Public License for more details. */ +#include #include #include #include #include -#include #include #include #include @@ -139,8 +139,8 @@ static void mainboard_enable(struct device *dev) * SPD read code has been made generic and moved out of the board * directory, so the ASF init is being done here. */ - pm_iowrite(0x29, 0x80); - pm_iowrite(0x28, 0x61); + pm_write8(0x29, 0x80); + pm_write8(0x28, 0x61); /* Initialize the PIRQ data structures for consumption */ pirq_setup(); diff --git a/src/mainboard/gizmosphere/gizmo/mainboard.c b/src/mainboard/gizmosphere/gizmo/mainboard.c index 36fa5f9074..8196922571 100644 --- a/src/mainboard/gizmosphere/gizmo/mainboard.c +++ b/src/mainboard/gizmosphere/gizmo/mainboard.c @@ -20,7 +20,6 @@ #include #include #include -#include #include /********************************************** diff --git a/src/mainboard/jetway/nf81-t56n-lf/mainboard.c b/src/mainboard/jetway/nf81-t56n-lf/mainboard.c index 3439d2fa4e..0a12c3f66a 100644 --- a/src/mainboard/jetway/nf81-t56n-lf/mainboard.c +++ b/src/mainboard/jetway/nf81-t56n-lf/mainboard.c @@ -15,7 +15,7 @@ * GNU General Public License for more details. */ - +#include #include #include #include @@ -23,7 +23,6 @@ #include #include #include -#include #include /*********************************************************** @@ -142,8 +141,8 @@ static void mainboard_enable(struct device *dev) * SPD read code has been made generic and moved out of the board * directory, so the ASF init is being done here. */ - pm_iowrite(0x29, 0x80); - pm_iowrite(0x28, 0x61); + pm_write8(0x29, 0x80); + pm_write8(0x28, 0x61); /* Initialize the PIRQ data structures for consumption */ pirq_setup(); diff --git a/src/mainboard/lippert/frontrunner-af/mainboard.c b/src/mainboard/lippert/frontrunner-af/mainboard.c index 44d0104e00..ea473c035c 100644 --- a/src/mainboard/lippert/frontrunner-af/mainboard.c +++ b/src/mainboard/lippert/frontrunner-af/mainboard.c @@ -14,6 +14,7 @@ */ #include +#include #include #include #include @@ -21,7 +22,6 @@ #include #include #include -#include #include #include /* SMBUS0_BASE_ADDRESS */ #include @@ -136,8 +136,8 @@ static void mainboard_enable(struct device *dev) * SPD read code has been made generic and moved out of the board * directory, so the ASF init is being done here. */ - pm_iowrite(0x29, 0x80); - pm_iowrite(0x28, 0x61); + pm_write8(0x29, 0x80); + pm_write8(0x28, 0x61); } struct chip_operations mainboard_ops = { diff --git a/src/mainboard/lippert/toucan-af/mainboard.c b/src/mainboard/lippert/toucan-af/mainboard.c index 746b1953f8..b000688da6 100644 --- a/src/mainboard/lippert/toucan-af/mainboard.c +++ b/src/mainboard/lippert/toucan-af/mainboard.c @@ -14,13 +14,13 @@ */ #include +#include #include #include #include #include #include #include -#include #include #include /* SMBUS0_BASE_ADDRESS */ #include @@ -101,8 +101,8 @@ static void mainboard_enable(struct device *dev) * SPD read code has been made generic and moved out of the board * directory, so the ASF init is being done here. */ - pm_iowrite(0x29, 0x80); - pm_iowrite(0x28, 0x61); + pm_write8(0x29, 0x80); + pm_write8(0x28, 0x61); } struct chip_operations mainboard_ops = { diff --git a/src/mainboard/pcengines/apu1/gpio_ftns.c b/src/mainboard/pcengines/apu1/gpio_ftns.c index 7a988e7ec6..bedd15a514 100644 --- a/src/mainboard/pcengines/apu1/gpio_ftns.c +++ b/src/mainboard/pcengines/apu1/gpio_ftns.c @@ -14,25 +14,18 @@ */ #include +#include #include #include -#include #include "gpio_ftns.h" uintptr_t find_gpio_base(void) { - u8 pm_index, pm_data; - uintptr_t base_addr = 0; - - /* Find the ACPImmioAddr base address */ - for (pm_index = 0x27; pm_index > 0x23; pm_index--) { - outb(pm_index, PM_INDEX); - pm_data = inb(PM_DATA); - base_addr <<= 8; - base_addr |= (u32)pm_data; - } + uintptr_t base_addr; + /* Get the ACPIMMIO base address */ + base_addr = pm_read32(0x24); base_addr &= 0xFFFFF000; - return (base_addr); + return base_addr; } void configure_gpio(uintptr_t base_addr, u32 gpio, u8 iomux_ftn, u8 setting) diff --git a/src/mainboard/pcengines/apu1/mainboard.c b/src/mainboard/pcengines/apu1/mainboard.c index 088c839239..1c302912a9 100644 --- a/src/mainboard/pcengines/apu1/mainboard.c +++ b/src/mainboard/pcengines/apu1/mainboard.c @@ -21,7 +21,6 @@ #include #include #include -#include #include #include #include diff --git a/src/mainboard/pcengines/apu1/romstage.c b/src/mainboard/pcengines/apu1/romstage.c index ab48943c55..89bf3049d6 100644 --- a/src/mainboard/pcengines/apu1/romstage.c +++ b/src/mainboard/pcengines/apu1/romstage.c @@ -15,8 +15,8 @@ * GNU General Public License for more details. */ +#include #include -#include #include #include #include "gpio_ftns.h" @@ -33,16 +33,16 @@ static void early_lpc_init(void) * controlled in PM_REG 5Bh register. "Always Power On" works by writing a * value of 05h. */ - u8 bdata = pm_ioread(SB_PMIOA_REG5B); + u8 bdata = pm_read8(SB_PMIOA_REG5B); bdata &= 0xf8; //clear bits 0-2 bdata |= 0x05; //set bits 0,2 - pm_iowrite(SB_PMIOA_REG5B, bdata); + pm_write8(SB_PMIOA_REG5B, bdata); /* Multi-function pins switch to GPIO0-35, these pins are shared with PCI pins */ - bdata = pm_ioread(SB_PMIOA_REGEA); + bdata = pm_read8(SB_PMIOA_REGEA); bdata &= 0xfe; //clear bit 0 bdata |= 0x01; //set bit 0 - pm_iowrite(SB_PMIOA_REGEA, bdata); + pm_write8(SB_PMIOA_REGEA, bdata); //configure required GPIOs mmio_base = find_gpio_base(); diff --git a/src/mainboard/pcengines/apu2/gpio_ftns.c b/src/mainboard/pcengines/apu2/gpio_ftns.c index a1e2e51952..249ecc3494 100644 --- a/src/mainboard/pcengines/apu2/gpio_ftns.c +++ b/src/mainboard/pcengines/apu2/gpio_ftns.c @@ -15,7 +15,6 @@ #include #include -#include #include #include "gpio_ftns.h" diff --git a/src/southbridge/amd/cimx/Makefile.inc b/src/southbridge/amd/cimx/Makefile.inc index 5d1d3f683b..6161c1493a 100644 --- a/src/southbridge/amd/cimx/Makefile.inc +++ b/src/southbridge/amd/cimx/Makefile.inc @@ -14,7 +14,3 @@ # subdirs-$(CONFIG_SOUTHBRIDGE_AMD_CIMX_SB800) += sb800 - -romstage-$(CONFIG_SOUTHBRIDGE_AMD_CIMX_SB800) += cimx_util.c - -ramstage-$(CONFIG_SOUTHBRIDGE_AMD_CIMX_SB800) += cimx_util.c diff --git a/src/southbridge/amd/cimx/cimx_util.c b/src/southbridge/amd/cimx/cimx_util.c deleted file mode 100644 index 1db04d8311..0000000000 --- a/src/southbridge/amd/cimx/cimx_util.c +++ /dev/null @@ -1,51 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2010 Advanced Micro Devices, Inc. - * Copyright (C) 2014 Sage Electronic Engineering, LLC. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include "cimx_util.h" - -static void pmio_write_index(u16 port_base, u8 reg, u8 value) -{ - outb(reg, port_base); - outb(value, port_base + 1); -} - -static u8 pmio_read_index(u16 port_base, u8 reg) -{ - outb(reg, port_base); - return inb(port_base + 1); -} - -void pm_iowrite(u8 reg, u8 value) -{ - pmio_write_index(PM_INDEX, reg, value); -} - -u8 pm_ioread(u8 reg) -{ - return pmio_read_index(PM_INDEX, reg); -} - -void pm2_iowrite(u8 reg, u8 value) -{ - pmio_write_index(PM2_INDEX, reg, value); -} - -u8 pm2_ioread(u8 reg) -{ - return pmio_read_index(PM2_INDEX, reg); -} diff --git a/src/southbridge/amd/cimx/cimx_util.h b/src/southbridge/amd/cimx/cimx_util.h deleted file mode 100644 index bf41e8ab72..0000000000 --- a/src/southbridge/amd/cimx/cimx_util.h +++ /dev/null @@ -1,37 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2010 Advanced Micro Devices, Inc. - * Copyright (C) 2014 Sage Electronic Engineering, LLC. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef CIMX_UTIL_H -#define CIMX_UTIL_H - -#include - -/* FCH index/data registers */ -#define BIOSRAM_INDEX 0xcd4 -#define BIOSRAM_DATA 0xcd5 -#define PM_INDEX 0xcd6 -#define PM_DATA 0xcd7 -#define PM2_INDEX 0xcd0 -#define PM2_DATA 0xcd1 -#define PCI_INTR_INDEX 0xc00 -#define PCI_INTR_DATA 0xc01 - -void pm_iowrite(u8 reg, u8 value); -u8 pm_ioread(u8 reg); -void pm2_iowrite(u8 reg, u8 value); -u8 pm2_ioread(u8 reg); - -#endif /* CIMX_UTIL_H */ diff --git a/src/southbridge/amd/cimx/sb800/Kconfig b/src/southbridge/amd/cimx/sb800/Kconfig index aa5160b68f..0b790b06dc 100644 --- a/src/southbridge/amd/cimx/sb800/Kconfig +++ b/src/southbridge/amd/cimx/sb800/Kconfig @@ -21,6 +21,9 @@ config SOUTHBRIDGE_AMD_CIMX_SB800 select AMD_SB_CIMX select HAVE_CF9_RESET select HAVE_CF9_RESET_PREPARE + select SOC_AMD_COMMON + select SOC_AMD_COMMON_BLOCK + select SOC_AMD_COMMON_BLOCK_ACPIMMIO if SOUTHBRIDGE_AMD_CIMX_SB800 config BOOTBLOCK_SOUTHBRIDGE_INIT diff --git a/src/southbridge/amd/cimx/sb800/fan.c b/src/southbridge/amd/cimx/sb800/fan.c index a8dfa31d9a..42c13d74a7 100644 --- a/src/southbridge/amd/cimx/sb800/fan.c +++ b/src/southbridge/amd/cimx/sb800/fan.c @@ -13,7 +13,7 @@ * GNU General Public License for more details. */ -#include +#include #include #include /* device_operations */ #include @@ -31,27 +31,27 @@ void init_sb800_MANUAL_fans(struct device *dev) /* Init Fan 0 */ if (sb_chip->fan0_enabled) for (i = 0; i < FAN_REGISTER_COUNT; i++) - pm2_iowrite(FAN_0_OFFSET + i, sb_chip->fan0_config_vals[i]); + pm2_write8(FAN_0_OFFSET + i, sb_chip->fan0_config_vals[i]); /* Init Fan 1 */ if (sb_chip->fan1_enabled) for (i = 0; i < FAN_REGISTER_COUNT; i++) - pm2_iowrite(FAN_1_OFFSET + i, sb_chip->fan1_config_vals[i]); + pm2_write8(FAN_1_OFFSET + i, sb_chip->fan1_config_vals[i]); /* Init Fan 2 */ if (sb_chip->fan2_enabled) for (i = 0; i < FAN_REGISTER_COUNT; i++) - pm2_iowrite(FAN_2_OFFSET + i, sb_chip->fan2_config_vals[i]); + pm2_write8(FAN_2_OFFSET + i, sb_chip->fan2_config_vals[i]); /* Init Fan 3 */ if (sb_chip->fan3_enabled) for (i = 0; i < FAN_REGISTER_COUNT; i++) - pm2_iowrite(FAN_3_OFFSET + i, sb_chip->fan3_config_vals[i]); + pm2_write8(FAN_3_OFFSET + i, sb_chip->fan3_config_vals[i]); /* Init Fan 4 */ if (sb_chip->fan4_enabled) for (i = 0; i < FAN_REGISTER_COUNT; i++) - pm2_iowrite(FAN_4_OFFSET + i, sb_chip->fan4_config_vals[i]); + pm2_write8(FAN_4_OFFSET + i, sb_chip->fan4_config_vals[i]); } From a2962daf6fd1e184b7444feabe3f963a9ba614d7 Mon Sep 17 00:00:00 2001 From: Yu-Ping Wu Date: Tue, 26 Nov 2019 10:47:35 +0800 Subject: [PATCH 0505/1242] security/vboot: Remove struct vboot_working_data After CB:36808, CB:36844 and CB:36845, all fields except buffer_offset were removed from struct vboot_working_data. Since buffer_offset is used to record the offset of the workbuf relative to the whole structure, it is no longer needed. This patch removes the structure, and renames vboot_get_working_data() to vboot_get_workbuf(). BRANCH=none BUG=chromium:1021452 TEST=emerge-nami coreboot Change-Id: I304a5e4236f13b1aecd64b88ca5c8fbc1526e592 Signed-off-by: Yu-Ping Wu Reviewed-on: https://review.coreboot.org/c/coreboot/+/37231 Tested-by: build bot (Jenkins) Reviewed-by: Joel Kitching --- src/lib/coreboot_table.c | 10 ++--- src/security/vboot/common.c | 77 +++++++++++-------------------------- src/security/vboot/misc.h | 14 +------ 3 files changed, 28 insertions(+), 73 deletions(-) diff --git a/src/lib/coreboot_table.c b/src/lib/coreboot_table.c index 7245a63893..8b18dfb18e 100644 --- a/src/lib/coreboot_table.c +++ b/src/lib/coreboot_table.c @@ -221,20 +221,18 @@ static void lb_vbnv(struct lb_header *header) static void lb_vboot_workbuf(struct lb_header *header) { struct lb_range *vbwb; - struct vboot_working_data *wd = vboot_get_working_data(); + void *wb = vboot_get_workbuf(); vbwb = (struct lb_range *)lb_new_record(header); vbwb->tag = LB_TAG_VBOOT_WORKBUF; vbwb->size = sizeof(*vbwb); - vbwb->range_start = (uintptr_t)wd + wd->buffer_offset; + vbwb->range_start = (uintptr_t)wb; /* * TODO(chromium:1021452): Since cbmem size of vboot workbuf is now * always a known value, we hardcode the value of range_size here. - * Ultimately we'll want to move this to add_cbmem_pointers() below, - * but we'll have to get rid of the vboot_working_data struct first. + * Ultimately we'll want to move this to add_cbmem_pointers() below. */ - vbwb->range_size = VB2_KERNEL_WORKBUF_RECOMMENDED_SIZE - - wd->buffer_offset; + vbwb->range_size = VB2_KERNEL_WORKBUF_RECOMMENDED_SIZE; } __weak uint32_t board_id(void) { return UNDEFINED_STRAPPING_ID; } diff --git a/src/security/vboot/common.c b/src/security/vboot/common.c index 290fa5e231..517a1d4d34 100644 --- a/src/security/vboot/common.c +++ b/src/security/vboot/common.c @@ -27,57 +27,42 @@ static struct vb2_context *vboot_ctx; -struct vboot_working_data *vboot_get_working_data(void) +void *vboot_get_workbuf(void) { - struct vboot_working_data *wd = NULL; + void *wb = NULL; if (cbmem_possibly_online()) - wd = cbmem_find(CBMEM_ID_VBOOT_WORKBUF); + wb = cbmem_find(CBMEM_ID_VBOOT_WORKBUF); - if (wd == NULL && CONFIG(VBOOT_STARTS_IN_BOOTBLOCK) && + if (wb == NULL && CONFIG(VBOOT_STARTS_IN_BOOTBLOCK) && preram_symbols_available()) - wd = (struct vboot_working_data *)_vboot2_work; + wb = _vboot2_work; - assert(wd != NULL); + assert(wb != NULL); - return wd; -} - -static inline void *vboot_get_workbuf(struct vboot_working_data *wd) -{ - return (void *)((uintptr_t)wd + wd->buffer_offset); + return wb; } struct vb2_context *vboot_get_context(void) { - struct vboot_working_data *wd; + void *wb; /* Return if context has already been initialized/restored. */ if (vboot_ctx) return vboot_ctx; - wd = vboot_get_working_data(); + wb = vboot_get_workbuf(); /* Restore context from a previous stage. */ if (vboot_logic_executed()) { - assert(vb2api_reinit(vboot_get_workbuf(wd), - &vboot_ctx) == VB2_SUCCESS); + assert(vb2api_reinit(wb, &vboot_ctx) == VB2_SUCCESS); return vboot_ctx; } assert(verification_should_run()); - /* - * vboot prefers 16-byte alignment. This takes away 16 bytes - * from the VBOOT2_WORK region, but the vboot devs said that's okay. - */ - memset(wd, 0, sizeof(*wd)); - wd->buffer_offset = ALIGN_UP(sizeof(*wd), 16); - /* Initialize vb2_shared_data and friends. */ - assert(vb2api_init(vboot_get_workbuf(wd), - VB2_FIRMWARE_WORKBUF_RECOMMENDED_SIZE - - wd->buffer_offset, + assert(vb2api_init(wb, VB2_FIRMWARE_WORKBUF_RECOMMENDED_SIZE, &vboot_ctx) == VB2_SUCCESS); return vboot_ctx; @@ -96,35 +81,19 @@ int vboot_locate_firmware(const struct vb2_context *ctx, return fmap_locate_area_as_rdev(name, fw); } -#if CONFIG(VBOOT_STARTS_IN_BOOTBLOCK) -/* - * For platforms that do not employ VBOOT_STARTS_IN_ROMSTAGE, vboot - * verification occurs before CBMEM is brought online, using pre-RAM. - * In order to make vboot data structures available downstream, copy - * vboot_working_data from SRAM/CAR into CBMEM. - */ -static void vboot_migrate_cbmem(int unused) -{ - const size_t cbmem_size = VB2_KERNEL_WORKBUF_RECOMMENDED_SIZE; - struct vboot_working_data *wd_preram = - (struct vboot_working_data *)_vboot2_work; - struct vboot_working_data *wd_cbmem = - cbmem_add(CBMEM_ID_VBOOT_WORKBUF, cbmem_size); - assert(wd_cbmem != NULL); - memcpy(wd_cbmem, wd_preram, sizeof(struct vboot_working_data)); - vb2api_relocate(vboot_get_workbuf(wd_cbmem), - vboot_get_workbuf(wd_preram), - cbmem_size - wd_cbmem->buffer_offset, - &vboot_ctx); -} -ROMSTAGE_CBMEM_INIT_HOOK(vboot_migrate_cbmem) -#else static void vboot_setup_cbmem(int unused) { - struct vboot_working_data *wd_cbmem = - cbmem_add(CBMEM_ID_VBOOT_WORKBUF, - VB2_KERNEL_WORKBUF_RECOMMENDED_SIZE); - assert(wd_cbmem != NULL); + const size_t cbmem_size = VB2_KERNEL_WORKBUF_RECOMMENDED_SIZE; + void *wb_cbmem = cbmem_add(CBMEM_ID_VBOOT_WORKBUF, cbmem_size); + assert(wb_cbmem != NULL); + /* + * For platforms where VBOOT_STARTS_IN_BOOTBLOCK, vboot verification + * occurs before CBMEM is brought online, using pre-RAM. In order to + * make vboot data structures available downstream, copy vboot workbuf + * from SRAM/CAR into CBMEM. + */ + if (CONFIG(VBOOT_STARTS_IN_BOOTBLOCK)) + assert(vb2api_relocate(wb_cbmem, _vboot2_work, cbmem_size, + &vboot_ctx) == VB2_SUCCESS); } ROMSTAGE_CBMEM_INIT_HOOK(vboot_setup_cbmem) -#endif diff --git a/src/security/vboot/misc.h b/src/security/vboot/misc.h index 9f681f6f7f..9dd482e846 100644 --- a/src/security/vboot/misc.h +++ b/src/security/vboot/misc.h @@ -22,22 +22,10 @@ struct vb2_context; struct vb2_shared_data; -/* - * Stores vboot-related information. selected_region is used by verstage to - * store the location of the selected slot. buffer is used by vboot to store - * its work buffer. vb2_context is contained within this work buffer, and is - * accessible via vboot_get_context() declared below. - * Keep the struct CPU architecture agnostic as it crosses stage boundaries. - */ -struct vboot_working_data { - /* offset of the buffer from the start of this struct */ - uint16_t buffer_offset; -}; - /* * Source: security/vboot/common.c */ -struct vboot_working_data *vboot_get_working_data(void); +void *vboot_get_workbuf(void); struct vb2_context *vboot_get_context(void); /* From 63b9700b2ca0f2414ff242881bae9bfd77fdb138 Mon Sep 17 00:00:00 2001 From: Yu-Ping Wu Date: Tue, 26 Nov 2019 13:31:32 +0800 Subject: [PATCH 0506/1242] lib/coreboot_table: Add CBMEM_ID_VBOOT_WORKBUF pointer to coreboot table Since struct vb2_shared_data already contains workbuf_size and vboot_workbuf_size is never used in depthcharge, remove it from struct sysinfo_t. In addition, remove lb_vboot_workbuf() and add CBMEM_ID_VBOOT_WORKBUF pointer to coreboot table with add_cbmem_pointers(). Parsing of coreboot table in libpayload is modified accordingly. BRANCH=none BUG=chromium:1021452 TEST=emerge-nami coreboot libpayload depthcharge; Akali booted correctly Change-Id: I890df3ff93fa44ed6d3f9ad05f9c6e49780a8ecb Signed-off-by: Yu-Ping Wu Reviewed-on: https://review.coreboot.org/c/coreboot/+/37234 Tested-by: build bot (Jenkins) Reviewed-by: Joel Kitching Reviewed-by: Julius Werner --- payloads/libpayload/include/sysinfo.h | 1 - payloads/libpayload/libc/coreboot.c | 5 +---- src/lib/coreboot_table.c | 23 +---------------------- src/security/vboot/common.c | 2 +- src/security/vboot/misc.h | 1 - 5 files changed, 3 insertions(+), 29 deletions(-) diff --git a/payloads/libpayload/include/sysinfo.h b/payloads/libpayload/include/sysinfo.h index c05be7c159..4b929f1390 100644 --- a/payloads/libpayload/include/sysinfo.h +++ b/payloads/libpayload/include/sysinfo.h @@ -96,7 +96,6 @@ struct sysinfo_t { struct cb_mainboard *mainboard; void *vboot_workbuf; - uint32_t vboot_workbuf_size; #if CONFIG(LP_ARCH_X86) int x86_rom_var_mtrr_index; diff --git a/payloads/libpayload/libc/coreboot.c b/payloads/libpayload/libc/coreboot.c index 2ff2090c19..f6e937923e 100644 --- a/payloads/libpayload/libc/coreboot.c +++ b/payloads/libpayload/libc/coreboot.c @@ -86,10 +86,7 @@ static void cb_parse_serial(void *ptr, struct sysinfo_t *info) static void cb_parse_vboot_workbuf(unsigned char *ptr, struct sysinfo_t *info) { - struct lb_range *vbwb = (struct lb_range *)ptr; - - info->vboot_workbuf = (void *)(uintptr_t)vbwb->range_start; - info->vboot_workbuf_size = vbwb->range_size; + info->vboot_workbuf = get_cbmem_ptr(ptr); } static void cb_parse_vbnv(unsigned char *ptr, struct sysinfo_t *info) diff --git a/src/lib/coreboot_table.c b/src/lib/coreboot_table.c index 8b18dfb18e..af9f6599c5 100644 --- a/src/lib/coreboot_table.c +++ b/src/lib/coreboot_table.c @@ -218,23 +218,6 @@ static void lb_vbnv(struct lb_header *header) } #endif /* CONFIG_CHROMEOS */ -static void lb_vboot_workbuf(struct lb_header *header) -{ - struct lb_range *vbwb; - void *wb = vboot_get_workbuf(); - - vbwb = (struct lb_range *)lb_new_record(header); - vbwb->tag = LB_TAG_VBOOT_WORKBUF; - vbwb->size = sizeof(*vbwb); - vbwb->range_start = (uintptr_t)wb; - /* - * TODO(chromium:1021452): Since cbmem size of vboot workbuf is now - * always a known value, we hardcode the value of range_size here. - * Ultimately we'll want to move this to add_cbmem_pointers() below. - */ - vbwb->range_size = VB2_KERNEL_WORKBUF_RECOMMENDED_SIZE; -} - __weak uint32_t board_id(void) { return UNDEFINED_STRAPPING_ID; } __weak uint32_t ram_code(void) { return UNDEFINED_STRAPPING_ID; } __weak uint32_t sku_id(void) { return UNDEFINED_STRAPPING_ID; } @@ -349,6 +332,7 @@ static void add_cbmem_pointers(struct lb_header *header) {CBMEM_ID_WIFI_CALIBRATION, LB_TAG_WIFI_CALIBRATION}, {CBMEM_ID_TCPA_LOG, LB_TAG_TCPA_LOG}, {CBMEM_ID_FMAP, LB_TAG_FMAP}, + {CBMEM_ID_VBOOT_WORKBUF, LB_TAG_VBOOT_WORKBUF}, }; int i; @@ -558,11 +542,6 @@ static uintptr_t write_coreboot_table(uintptr_t rom_table_end) lb_vbnv(head); #endif - if (CONFIG(VBOOT)) { - /* pass along the vboot workbuf address. */ - lb_vboot_workbuf(head); - } - /* Add strapping IDs if available */ lb_board_id(head); lb_ram_code(head); diff --git a/src/security/vboot/common.c b/src/security/vboot/common.c index 517a1d4d34..c21fe155a5 100644 --- a/src/security/vboot/common.c +++ b/src/security/vboot/common.c @@ -27,7 +27,7 @@ static struct vb2_context *vboot_ctx; -void *vboot_get_workbuf(void) +static void *vboot_get_workbuf(void) { void *wb = NULL; diff --git a/src/security/vboot/misc.h b/src/security/vboot/misc.h index 9dd482e846..d03e76eea7 100644 --- a/src/security/vboot/misc.h +++ b/src/security/vboot/misc.h @@ -25,7 +25,6 @@ struct vb2_shared_data; /* * Source: security/vboot/common.c */ -void *vboot_get_workbuf(void); struct vb2_context *vboot_get_context(void); /* From b9aaa337221867f6a6af03b4f81bd46b95b605c3 Mon Sep 17 00:00:00 2001 From: Aamir Bohra Date: Fri, 29 Nov 2019 11:57:15 +0530 Subject: [PATCH 0507/1242] mb/intel/icelake_rvp: Remove unused mainboard ACPI write table Change-Id: I19040cca064c2ce063aab77391e0577271c6e9dc Signed-off-by: Aamir Bohra Reviewed-on: https://review.coreboot.org/c/coreboot/+/37354 Tested-by: build bot (Jenkins) Reviewed-by: Rizwan Qureshi Reviewed-by: Lean Sheng Tan Reviewed-by: Ronak Kanabar --- src/mainboard/intel/icelake_rvp/mainboard.c | 12 ------------ 1 file changed, 12 deletions(-) diff --git a/src/mainboard/intel/icelake_rvp/mainboard.c b/src/mainboard/intel/icelake_rvp/mainboard.c index 36d6a3e6e2..8e51e453d3 100644 --- a/src/mainboard/intel/icelake_rvp/mainboard.c +++ b/src/mainboard/intel/icelake_rvp/mainboard.c @@ -29,20 +29,8 @@ static void mainboard_init(void *chip_info) gpio_configure_pads(pads, num); } -static unsigned long mainboard_write_acpi_tables(struct device *device, - unsigned long current, - acpi_rsdp_t *rsdp) -{ - uintptr_t start_addr; - - start_addr = current; - - return start_addr; -} - static void mainboard_enable(struct device *dev) { - dev->ops->write_acpi_tables = mainboard_write_acpi_tables; dev->ops->acpi_inject_dsdt_generator = chromeos_dsdt_generator; } From 68ec3eb1f0447ab5bc300d1a510e499d3512d5f7 Mon Sep 17 00:00:00 2001 From: Elyes HAOUAS Date: Sat, 22 Jun 2019 09:21:18 +0200 Subject: [PATCH 0508/1242] src: Move 'static' to the beginning of declaration Change-Id: I9b2cc1bb58922d9e32202ea4c20b9aacfe308bad Signed-off-by: Elyes HAOUAS Reviewed-on: https://review.coreboot.org/c/coreboot/+/33673 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin --- src/mainboard/gizmosphere/gizmo/platform_cfg.h | 2 +- src/northbridge/intel/x4x/dq_dqs.c | 4 ++-- src/northbridge/intel/x4x/raminit_ddr23.c | 6 +++--- src/security/vboot/secdata_tpm.c | 6 +++--- src/security/vboot/vboot_crtm.c | 2 +- src/soc/amd/stoneyridge/southbridge.c | 4 ++-- 6 files changed, 12 insertions(+), 12 deletions(-) diff --git a/src/mainboard/gizmosphere/gizmo/platform_cfg.h b/src/mainboard/gizmosphere/gizmo/platform_cfg.h index 57b1aecef1..c56b537f9d 100644 --- a/src/mainboard/gizmosphere/gizmo/platform_cfg.h +++ b/src/mainboard/gizmosphere/gizmo/platform_cfg.h @@ -212,7 +212,7 @@ */ #define GEC_CONFIG 0 -const static CODECENTRY gizmo_codec_alc272[] = +static const CODECENTRY gizmo_codec_alc272[] = { /* NID, PinConfig */ {0x11, 0x411111F0}, /* S/PDIF-OUT2 unused */ diff --git a/src/northbridge/intel/x4x/dq_dqs.c b/src/northbridge/intel/x4x/dq_dqs.c index ed372b538f..d48601d300 100644 --- a/src/northbridge/intel/x4x/dq_dqs.c +++ b/src/northbridge/intel/x4x/dq_dqs.c @@ -88,7 +88,7 @@ static void set_db(const struct sysinfo *s, struct dll_setting *dq_dqs_setting) } } -const static u8 max_tap[3] = {12, 10, 13}; +static const u8 max_tap[3] = {12, 10, 13}; static int increment_dq_dqs(const struct sysinfo *s, struct dll_setting *dq_dqs_setting) @@ -540,7 +540,7 @@ static void set_rank_write_level(struct sysinfo *s, u8 channel, u8 config, u32 emrs1; /* Is shifted by bits 2 later so u8 can be used to reduce size */ - const static u8 emrs1_lut[8][4][4]={ /* [Config][Leveling Rank][Rank] */ + static const u8 emrs1_lut[8][4][4] = { /* [Config][Leveling Rank][Rank] */ { /* Config 0: 2R2R */ {0x11, 0x00, 0x91, 0x00}, {0x00, 0x11, 0x91, 0x00}, diff --git a/src/northbridge/intel/x4x/raminit_ddr23.c b/src/northbridge/intel/x4x/raminit_ddr23.c index efdcbb637a..dd48d8ab63 100644 --- a/src/northbridge/intel/x4x/raminit_ddr23.c +++ b/src/northbridge/intel/x4x/raminit_ddr23.c @@ -437,7 +437,7 @@ static void program_timings(struct sysinfo *s) 5200 }; - const static u8 ddr3_turnaround_tab[3][6][4] = { + static const u8 ddr3_turnaround_tab[3][6][4] = { { /* DDR3 800 */ {0x9, 0x7, 0x7, 0x9}, /* CL = 5 */ {0x9, 0x7, 0x8, 0x8}, /* CL = 6 */ @@ -459,7 +459,7 @@ static void program_timings(struct sysinfo *s) }; /* [DDR freq][0x26F & 1][pagemod] */ - const static u8 ddr2_x252_tab[2][2][2] = { + static const u8 ddr2_x252_tab[2][2][2] = { { /* DDR2 667 */ {12, 16}, {14, 18} @@ -470,7 +470,7 @@ static void program_timings(struct sysinfo *s) } }; - const static u8 ddr3_x252_tab[3][2][2] = { + static const u8 ddr3_x252_tab[3][2][2] = { { /* DDR3 800 */ {16, 20}, {18, 22} diff --git a/src/security/vboot/secdata_tpm.c b/src/security/vboot/secdata_tpm.c index 2fbb30b008..0afd00d6cc 100644 --- a/src/security/vboot/secdata_tpm.c +++ b/src/security/vboot/secdata_tpm.c @@ -133,7 +133,7 @@ static const uint8_t rec_hash_data[REC_HASH_NV_SIZE] = { }; * i.e. those which should not be possible to delete or modify once * the RO exits, and the rest of the NVRAM spaces. */ -const static TPMA_NV ro_space_attributes = { +static const TPMA_NV ro_space_attributes = { .TPMA_NV_PPWRITE = 1, .TPMA_NV_AUTHREAD = 1, .TPMA_NV_PPREAD = 1, @@ -142,7 +142,7 @@ const static TPMA_NV ro_space_attributes = { .TPMA_NV_POLICY_DELETE = 1, }; -const static TPMA_NV rw_space_attributes = { +static const TPMA_NV rw_space_attributes = { .TPMA_NV_PPWRITE = 1, .TPMA_NV_AUTHREAD = 1, .TPMA_NV_PPREAD = 1, @@ -153,7 +153,7 @@ const static TPMA_NV rw_space_attributes = { * This policy digest was obtained using TPM2_PolicyPCR * selecting only PCR_0 with a value of all zeros. */ -const static uint8_t pcr0_unchanged_policy[] = { +static const uint8_t pcr0_unchanged_policy[] = { 0x09, 0x93, 0x3C, 0xCE, 0xEB, 0xB4, 0x41, 0x11, 0x18, 0x81, 0x1D, 0xD4, 0x47, 0x78, 0x80, 0x08, 0x88, 0x86, 0x62, 0x2D, 0xD7, 0x79, 0x94, 0x46, 0x62, 0x26, 0x68, 0x8E, 0xEE, 0xE6, 0x6A, 0xA1}; diff --git a/src/security/vboot/vboot_crtm.c b/src/security/vboot/vboot_crtm.c index e4266b2ca9..f68ab0a4bc 100644 --- a/src/security/vboot/vboot_crtm.c +++ b/src/security/vboot/vboot_crtm.c @@ -29,7 +29,7 @@ static int create_tcpa_metadata(const struct region_device *rdev, { int i; struct region_device fmap; - const static char *fmap_cbfs_names[] = { + static const char *fmap_cbfs_names[] = { "COREBOOT", "FW_MAIN_A", "FW_MAIN_B", diff --git a/src/soc/amd/stoneyridge/southbridge.c b/src/soc/amd/stoneyridge/southbridge.c index d7a09aaf57..8556790772 100644 --- a/src/soc/amd/stoneyridge/southbridge.c +++ b/src/soc/amd/stoneyridge/southbridge.c @@ -43,7 +43,7 @@ * waiting for each device to become available, a single delay will be * executed. */ -const static struct stoneyridge_aoac aoac_devs[] = { +static const struct stoneyridge_aoac aoac_devs[] = { { (FCH_AOAC_D3_CONTROL_UART0 + CONFIG_UART_FOR_CONSOLE * 2), (FCH_AOAC_D3_STATE_UART0 + CONFIG_UART_FOR_CONSOLE * 2) }, { FCH_AOAC_D3_CONTROL_AMBA, FCH_AOAC_D3_STATE_AMBA }, @@ -115,7 +115,7 @@ void SetFchMidParams(FCH_INTERFACE *params) * amd_pci_int_defs.h, just add the pair at the end of this table. * Order is not important. */ -const static struct irq_idx_name irq_association[] = { +static const struct irq_idx_name irq_association[] = { { PIRQ_A, "INTA#" }, { PIRQ_B, "INTB#" }, { PIRQ_C, "INTC#" }, From c135b829e7cfd0cc12ccbef57af2509654374911 Mon Sep 17 00:00:00 2001 From: Mathew King Date: Mon, 14 Oct 2019 10:19:15 -0600 Subject: [PATCH 0509/1242] drivers/gfx: Add generic graphics with SSDT generator Adds a generic graphics driver that can be added to a devicetree which populates graphics-related ACPI table. It will write the _DOD method (Enumerate All Devices Attached to the Display Adapter) and a device object for each device defined. The device may optionally have a connected privacy screen which can be controlled with a _DSM. Example: chip drivers/generic/gfx register "device_count" = "1" register "device[0].name" = ""LCD"" register "device[0].addr" = "0x0400" register "device[0].privacy.enabled" = "1" register "device[0].privacy.detect_function" = ""\\_SB.PCI0.PVSC.GPVD"" register "device[0].privacy.status_function" = ""\\_SB.PCI0.PVSC.GPVX"" register "device[0].privacy.enable_function" = ""\\_SB.PCI0.PVSC.EPVX"" register "device[0].privacy.disable_function" = ""\\_SB.PCI0.PVSC.DPVX"" device generic 0 on end end ASL Scope (\_SB.PCI0.GFX0) { Method (_DOD, 0, NotSerialized) // _DOD: Display Output Devices { Return (Package (0x01) { 0x00000400 }) } Device (LCD) { Name (_ADR, 0x0400) // _ADR: Address Name (_STA, 0x0F) // _STA: Status Method (_DSM, 4, Serialized) // _DSM: Device-Specific Method { ToBuffer (Arg0, Local0) If ((Local0 == ToUUID ("c7033113-8720-4ceb-9090-9d52b3e52d73"))) { ToInteger (Arg2, Local1) If ((Local1 == Zero)) { Local2 = \_SB.PCI0.PVSC.GPVD () If ((Local2 == One)) { Return (Buffer (One) { 0x0F }) } } If ((Local1 == One)) { ToBuffer (\_SB.PCI0.PVSC.GPVX (), Local2) Return (Local2) } If ((Local1 == 0x02)) { \_SB.PCI0.PVSC.EPVX () } If ((Local1 == 0x03)) { \_SB.PCI0.PVSC.DPVX () } Return (Buffer (One) { 0x00 }) } Return (Buffer (One) { 0x00 }) } } } BUG=b:142237145 TEST=Added gfx to devicetree on sarien_cml and correct ASL in SSDT Change-Id: Ida520dd7aad81ee7c1e5f2d0d3f5cc1a766d78a0 Signed-off-by: Mathew King Reviewed-on: https://review.coreboot.org/c/coreboot/+/36041 Reviewed-by: Simon Glass Tested-by: build bot (Jenkins) --- src/drivers/generic/gfx/Kconfig | 6 ++ src/drivers/generic/gfx/Makefile.inc | 1 + src/drivers/generic/gfx/chip.h | 56 ++++++++++++ src/drivers/generic/gfx/gfx.c | 127 +++++++++++++++++++++++++++ 4 files changed, 190 insertions(+) create mode 100644 src/drivers/generic/gfx/Kconfig create mode 100644 src/drivers/generic/gfx/Makefile.inc create mode 100644 src/drivers/generic/gfx/chip.h create mode 100644 src/drivers/generic/gfx/gfx.c diff --git a/src/drivers/generic/gfx/Kconfig b/src/drivers/generic/gfx/Kconfig new file mode 100644 index 0000000000..1152f5bb7d --- /dev/null +++ b/src/drivers/generic/gfx/Kconfig @@ -0,0 +1,6 @@ +config DRIVERS_GENERIC_GFX + bool + default n + depends on HAVE_ACPI_TABLES + help + Include support for generic graphics device in devicetree diff --git a/src/drivers/generic/gfx/Makefile.inc b/src/drivers/generic/gfx/Makefile.inc new file mode 100644 index 0000000000..c31986be46 --- /dev/null +++ b/src/drivers/generic/gfx/Makefile.inc @@ -0,0 +1 @@ +ramstage-$(CONFIG_DRIVERS_GENERIC_GFX) += gfx.c diff --git a/src/drivers/generic/gfx/chip.h b/src/drivers/generic/gfx/chip.h new file mode 100644 index 0000000000..ee5bd1ff88 --- /dev/null +++ b/src/drivers/generic/gfx/chip.h @@ -0,0 +1,56 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2019 Google LLC + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __DRIVERS_GENERIC_GFX_CHIP_H__ +#define __DRIVERS_GENERIC_GFX_CHIP_H__ + +/* Config for electronic privacy screen */ +struct drivers_generic_gfx_privacy_screen_config { + /* Is privacy screen available on this graphics device */ + int enabled; + /* ACPI namespace path to privacy screen detection function */ + const char *detect_function; + /* ACPI namespace path to privacy screen status function */ + const char *status_function; + /* ACPI namespace path to privacy screen enable function */ + const char *enable_function; + /* ACPI namespace path to privacy screen disable function */ + const char *disable_function; +}; + +/* Config for an output device as defined in section A.5 of the ACPI spec */ +struct drivers_generic_gfx_device_config { + /* ACPI device name of the output device */ + const char *name; + /* The address of the output device. See section A.3.2 */ + unsigned int addr; + /* Electronic privacy screen specific config */ + struct drivers_generic_gfx_privacy_screen_config privacy; +}; + +/* Config for an ACPI video device defined in Appendix A of the ACPI spec */ +struct drivers_generic_gfx_config { + /* + * ACPI device name of the graphics card, "GFX0" will be used if name is + * not set + */ + const char *name; + /* The number of output devices defined */ + int device_count; + /* Config for output devices */ + struct drivers_generic_gfx_device_config device[5]; +}; + +#endif /* __DRIVERS_GENERIC_GFX_CHIP_H__ */ diff --git a/src/drivers/generic/gfx/gfx.c b/src/drivers/generic/gfx/gfx.c new file mode 100644 index 0000000000..76d311cc9c --- /dev/null +++ b/src/drivers/generic/gfx/gfx.c @@ -0,0 +1,127 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2019 Google LLC + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include +#include +#include +#include +#include + +#include "chip.h" + +#define ACPI_DSM_PRIVACY_SCREEN_UUID "C7033113-8720-4CEB-9090-9D52B3E52D73" + +static void privacy_screen_detect_cb(void *arg) +{ + struct drivers_generic_gfx_privacy_screen_config *config = arg; + + acpigen_write_store(); + acpigen_emit_namestring(config->detect_function); + acpigen_emit_byte(LOCAL2_OP); + acpigen_write_if_lequal_op_int(LOCAL2_OP, 1); + acpigen_write_return_singleton_buffer(0xF); + acpigen_pop_len(); +} +static void privacy_screen_get_status_cb(void *arg) +{ + struct drivers_generic_gfx_privacy_screen_config *config = arg; + + acpigen_emit_byte(RETURN_OP); + acpigen_emit_namestring(config->status_function); +} +static void privacy_screen_enable_cb(void *arg) +{ + struct drivers_generic_gfx_privacy_screen_config *config = arg; + + acpigen_emit_namestring(config->enable_function); +} +static void privacy_screen_disable_cb(void *arg) +{ + struct drivers_generic_gfx_privacy_screen_config *config = arg; + + acpigen_emit_namestring(config->disable_function); +} + +static void (*privacy_screen_callbacks[])(void *) = { + privacy_screen_detect_cb, + privacy_screen_get_status_cb, + privacy_screen_enable_cb, + privacy_screen_disable_cb, +}; + +static void gfx_fill_ssdt_generator(struct device *dev) +{ + size_t i; + struct drivers_generic_gfx_config *config = dev->chip_info; + + const char *scope = acpi_device_scope(dev); + + acpigen_write_scope(scope); + + /* Method (_DOD, 0) */ + acpigen_write_method("_DOD", 0); + acpigen_emit_byte(RETURN_OP); + acpigen_write_package(config->device_count); + for (i = 0; i < config->device_count; i++) + acpigen_write_dword(config->device[i].addr); + acpigen_pop_len(); /* End Package. */ + acpigen_pop_len(); /* End Method. */ + + for (i = 0; i < config->device_count; i++) { + acpigen_write_device(config->device[i].name); + + acpigen_write_name_integer("_ADR", config->device[i].addr); + acpigen_write_name_integer("_STA", 0xF); + + if (config->device[i].privacy.enabled) { + acpigen_write_dsm(ACPI_DSM_PRIVACY_SCREEN_UUID, + privacy_screen_callbacks, + ARRAY_SIZE(privacy_screen_callbacks), + &config->device[i].privacy); + } + + acpigen_pop_len(); /* Device */ + } + acpigen_pop_len(); /* Scope */ +} + +static const char *gfx_acpi_name(const struct device *dev) +{ + struct drivers_generic_gfx_config *config = dev->chip_info; + + return config->name ? : "GFX0"; +} + +static struct device_operations gfx_ops = { + .acpi_name = gfx_acpi_name, + .acpi_fill_ssdt_generator = gfx_fill_ssdt_generator, +}; + +static void gfx_enable(struct device *dev) +{ + struct drivers_generic_gfx_config *config = dev->chip_info; + + if (!config) + return; + + dev->ops = &gfx_ops; +} + +struct chip_operations drivers_generic_gfx_ops = { + CHIP_NAME("Graphics Device") + .enable_dev = gfx_enable +}; From f9fa985242b0e4abb089931b7643db4e493bd86f Mon Sep 17 00:00:00 2001 From: Mathew King Date: Mon, 14 Oct 2019 11:28:59 -0600 Subject: [PATCH 0510/1242] soc/intel: Intel graphics driver scans generic bus This change allows for Intel graphics devices to use drivers/generic/gfx driver to populate ACPI SSDT table for common graphics related devices and methods. BUG=b:142237145 TEST=On sarien_cml add generic/gfx to the devicetree and device is enumerated and correct SSDT ASL is observed. Change-Id: Ibc86a88687ac860ebef19a4b68af64fd50d12b8e Signed-off-by: Mathew King Reviewed-on: https://review.coreboot.org/c/coreboot/+/36042 Tested-by: build bot (Jenkins) Reviewed-by: Simon Glass Reviewed-by: Simon Glass Reviewed-by: Duncan Laurie --- src/soc/intel/common/block/graphics/graphics.c | 1 + 1 file changed, 1 insertion(+) diff --git a/src/soc/intel/common/block/graphics/graphics.c b/src/soc/intel/common/block/graphics/graphics.c index df838c0c88..e91e0af16f 100644 --- a/src/soc/intel/common/block/graphics/graphics.c +++ b/src/soc/intel/common/block/graphics/graphics.c @@ -118,6 +118,7 @@ static const struct device_operations graphics_ops = { .init = graphics_soc_init, .ops_pci = &pci_dev_ops_pci, .write_acpi_tables = graphics_soc_write_acpi_opregion, + .scan_bus = scan_generic_bus, }; static const unsigned short pci_device_ids[] = { From 6f8f34f1bf91bd225b1dd9fe4dc70fdcf6ce2805 Mon Sep 17 00:00:00 2001 From: Mathew King Date: Mon, 14 Oct 2019 11:37:12 -0600 Subject: [PATCH 0511/1242] soc/intel/cannonlake: Add gfx.asl file Add gfx.asl file for cannonlake SOCs to allow for graphics-related ACPI devices and methods on cannonlake devices. BUG=b:142237145 TEST=gfx.asl added to drallion dsdt.asl Change-Id: I38a26f3135d571e2f9b63840d38fd4d3476fc142 Signed-off-by: Mathew King Reviewed-on: https://review.coreboot.org/c/coreboot/+/36043 Tested-by: build bot (Jenkins) Reviewed-by: Simon Glass --- src/soc/intel/cannonlake/acpi/gfx.asl | 20 +++++++++++++++++++ src/soc/intel/cannonlake/acpi/southbridge.asl | 3 +++ 2 files changed, 23 insertions(+) create mode 100644 src/soc/intel/cannonlake/acpi/gfx.asl diff --git a/src/soc/intel/cannonlake/acpi/gfx.asl b/src/soc/intel/cannonlake/acpi/gfx.asl new file mode 100644 index 0000000000..d2678596c0 --- /dev/null +++ b/src/soc/intel/cannonlake/acpi/gfx.asl @@ -0,0 +1,20 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 Google LLC + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the + * GNU General Public License for more details. + */ + +Device (GFX0) +{ + Name (_ADR, 0x00020000) +} diff --git a/src/soc/intel/cannonlake/acpi/southbridge.asl b/src/soc/intel/cannonlake/acpi/southbridge.asl index b52de65e36..8dbd850df6 100644 --- a/src/soc/intel/cannonlake/acpi/southbridge.asl +++ b/src/soc/intel/cannonlake/acpi/southbridge.asl @@ -31,6 +31,9 @@ #include "gpio.asl" #endif +/* GFX 00:02.0 */ +#include "gfx.asl" + /* LPC 0:1f.0 */ #include From c650e130ced0ee1f62fe0d9bff7a89b8717f6f28 Mon Sep 17 00:00:00 2001 From: Mathew King Date: Mon, 14 Oct 2019 11:59:41 -0600 Subject: [PATCH 0512/1242] ec/google/wilco: Add EC ACPI methods for privacy screen Add ACPI methods to the Wilco EC for controlling a privacy screen on the device. BUG=b:142237145, b:142656363 TEST=none Change-Id: Ic3c136f9d2de90eeb3c9e468e4c7430ccf6dcc42 Signed-off-by: Mathew King Reviewed-on: https://review.coreboot.org/c/coreboot/+/36044 Reviewed-by: Simon Glass Tested-by: build bot (Jenkins) --- src/ec/google/wilco/acpi/ec.asl | 3 ++ src/ec/google/wilco/acpi/ec_ram.asl | 4 +++ src/ec/google/wilco/acpi/privacy.asl | 43 ++++++++++++++++++++++++++++ 3 files changed, 50 insertions(+) create mode 100644 src/ec/google/wilco/acpi/privacy.asl diff --git a/src/ec/google/wilco/acpi/ec.asl b/src/ec/google/wilco/acpi/ec.asl index 532f421780..8fcd0dd5c2 100644 --- a/src/ec/google/wilco/acpi/ec.asl +++ b/src/ec/google/wilco/acpi/ec.asl @@ -178,4 +178,7 @@ Device (EC0) #ifdef EC_ENABLE_DPTF #include "dptf.asl" #endif +#ifdef EC_ENABLE_PRIVACY + #include "privacy.asl" +#endif } diff --git a/src/ec/google/wilco/acpi/ec_ram.asl b/src/ec/google/wilco/acpi/ec_ram.asl index 47e9072dcb..af8fc0effc 100644 --- a/src/ec/google/wilco/acpi/ec_ram.asl +++ b/src/ec/google/wilco/acpi/ec_ram.asl @@ -125,6 +125,9 @@ Name (BCCY, Package () { 0x3e, 0xffff, RD }) /* BCACHE: Cycle Count */ Name (ESGN, Package () { 0x5c, 0xff, RD }) /* Indicate EC uses signed FW */ +Name (EPDT, Package () { 0x5d, 0xff, RD }) /* Privacy Screen Detection */ +Name (EPST, Package () { 0x5e, 0xff, RD }) /* Privacy Screen State */ + /* * EC RAM WRITE */ @@ -135,6 +138,7 @@ Name (SSEL, Package () { 0x04, 0xff, WR }) /* Battery String Select */ Name (ERDY, Package () { 0x05, 0xff, WR }) /* EC Ready */ Name (FWAK, Package () { 0x06, 0xff, WR }) /* EC _WAK */ Name (PS2M, Package () { 0x20, 0xff, WR }) /* EC PS/2 Mouse Emulation */ +Name (EPCT, Package () { 0x25, 0xff, WR }) /* Privacy Screen Control */ Name (DWST, Package () { 0x32, 0xff, WR }) /* DPTF: Write State */ Name (DWTI, Package () { 0x33, 0xff, WR }) /* DPTF: Write Thermal Index */ Name (DWTL, Package () { 0x35, 0xff, WR }) /* DPTF: Write Trip Low */ diff --git a/src/ec/google/wilco/acpi/privacy.asl b/src/ec/google/wilco/acpi/privacy.asl new file mode 100644 index 0000000000..5c620b0fca --- /dev/null +++ b/src/ec/google/wilco/acpi/privacy.asl @@ -0,0 +1,43 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2019 Google LLC + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* Read Privacy Screen Present */ +Method (GPVD, 0, Serialized) +{ + Return (R (EPDT)) +} + +/* Read Privacy Screen Status */ +Method (GPVX, 0, Serialized) +{ + If (R (EPST) == Zero) { + Return (Zero) + } + + Return (One) +} + +/* Enable Privacy Screen */ +Method (EPVX, 0, Serialized) +{ + W (EPCT, One) +} + +/* Disable Privacy Screen */ +Method (DPVX, 0, Serialized) +{ + W (EPCT, Zero) +} From c487ac1a9fea07023ca3a8e95b8f44eb67a9a01d Mon Sep 17 00:00:00 2001 From: Mathew King Date: Mon, 14 Oct 2019 12:07:23 -0600 Subject: [PATCH 0513/1242] mb/g/drallion: Enable privacy screen on Drallion variant Enable ACPI methods to control privacy screen on Drallion devices. Drallion devices may not have a privacy screen and it is up to the EC to determine if the privacy screen is present on the system. BUG=b:142656363 TEST=emerge-drallion coreboot chromeos-bootimage Change-Id: I79d02bb1b25f0deb49ae4bb852b7ed8c21fd31c7 Signed-off-by: Mathew King Reviewed-on: https://review.coreboot.org/c/coreboot/+/36045 Reviewed-by: Simon Glass Tested-by: build bot (Jenkins) --- src/mainboard/google/drallion/Kconfig | 1 + .../drallion/variants/drallion/devicetree.cb | 16 +++++++++++++++- .../variants/drallion/include/variant/ec.h | 3 +++ 3 files changed, 19 insertions(+), 1 deletion(-) diff --git a/src/mainboard/google/drallion/Kconfig b/src/mainboard/google/drallion/Kconfig index accb9c8483..27818c091d 100644 --- a/src/mainboard/google/drallion/Kconfig +++ b/src/mainboard/google/drallion/Kconfig @@ -2,6 +2,7 @@ config BOARD_GOOGLE_BASEBOARD_DRALLION def_bool n select BOARD_ROMSIZE_KB_32768 + select DRIVERS_GENERIC_GFX select DRIVERS_I2C_GENERIC select DRIVERS_I2C_HID select DRIVERS_INTEL_ISH diff --git a/src/mainboard/google/drallion/variants/drallion/devicetree.cb b/src/mainboard/google/drallion/variants/drallion/devicetree.cb index 6ecb689790..4c5cff25a0 100644 --- a/src/mainboard/google/drallion/variants/drallion/devicetree.cb +++ b/src/mainboard/google/drallion/variants/drallion/devicetree.cb @@ -224,7 +224,21 @@ chip soc/intel/cannonlake end device domain 0 on device pci 00.0 on end # Host Bridge - device pci 02.0 on end # Integrated Graphics Device + device pci 02.0 on + chip drivers/generic/gfx + register "device_count" = "1" + register "device[0].name" = ""LCD"" + # Address is set following the ACPI spec section A.3.2 + # for an internal panel on the first port of the graphics chip + register "device[0].addr" = "0x80010400" + register "device[0].privacy.enabled" = "1" + register "device[0].privacy.detect_function" = ""\\_SB.PCI0.LPCB.EC0.GPVD"" + register "device[0].privacy.status_function" = ""\\_SB.PCI0.LPCB.EC0.GPVX"" + register "device[0].privacy.enable_function" = ""\\_SB.PCI0.LPCB.EC0.EPVX"" + register "device[0].privacy.disable_function" = ""\\_SB.PCI0.LPCB.EC0.DPVX"" + device generic 0 on end + end + end # Integrated Graphics Device device pci 04.0 on end # SA Thermal device device pci 12.0 on end # Thermal Subsystem device pci 12.5 off end # UFS SCS diff --git a/src/mainboard/google/drallion/variants/drallion/include/variant/ec.h b/src/mainboard/google/drallion/variants/drallion/include/variant/ec.h index 01a17b5f99..11e3be8404 100644 --- a/src/mainboard/google/drallion/variants/drallion/include/variant/ec.h +++ b/src/mainboard/google/drallion/variants/drallion/include/variant/ec.h @@ -31,4 +31,7 @@ /* Enable DPTF */ #define EC_ENABLE_DPTF +/* Enable privacy screen functionality */ +#define EC_ENABLE_PRIVACY + #endif From f82437852634d21f1ba2ee7a31ec825220807224 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ky=C3=B6sti=20M=C3=A4lkki?= Date: Mon, 2 Dec 2019 04:55:46 +0200 Subject: [PATCH 0514/1242] AGESA,binaryPI: Remove unused s3_load/save_nvram MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This is access to BIOSRAM region in ACPIMMIO. While we use the region, we do not use these functions. Change-Id: I39d1ae811cfe23595587ae0fe51c6549ecbaba6c Signed-off-by: Kyösti Mälkki Reviewed-on: https://review.coreboot.org/c/coreboot/+/37408 Tested-by: build bot (Jenkins) Reviewed-by: Michał Żygowski --- .../amd/agesa/hudson/early_setup.c | 30 ------------------- src/southbridge/amd/agesa/hudson/hudson.h | 3 -- src/southbridge/amd/pi/hudson/early_setup.c | 30 ------------------- src/southbridge/amd/pi/hudson/hudson.h | 2 -- 4 files changed, 65 deletions(-) diff --git a/src/southbridge/amd/agesa/hudson/early_setup.c b/src/southbridge/amd/agesa/hudson/early_setup.c index c3a4d41c8e..c5e6c25b68 100644 --- a/src/southbridge/amd/agesa/hudson/early_setup.c +++ b/src/southbridge/amd/agesa/hudson/early_setup.c @@ -87,34 +87,4 @@ void hudson_lpc_port80(void) pci_write_config8(dev, 0x4a, byte); } -int s3_save_nvram_early(u32 dword, int size, int nvram_pos) -{ - int i; - printk(BIOS_DEBUG, "Writing %x of size %d to nvram pos: %d\n", dword, size, nvram_pos); - - for (i = 0; i < size; i++) { - outb(nvram_pos, BIOSRAM_INDEX); - outb((dword >> (8 * i)) & 0xff, BIOSRAM_DATA); - nvram_pos++; - } - - return nvram_pos; -} - -int s3_load_nvram_early(int size, u32 *old_dword, int nvram_pos) -{ - u32 data = *old_dword; - int i; - for (i = 0; i < size; i++) { - outb(nvram_pos, BIOSRAM_INDEX); - data &= ~(0xff << (i * 8)); - data |= inb(BIOSRAM_DATA) << (i *8); - nvram_pos++; - } - *old_dword = data; - printk(BIOS_DEBUG, "Loading %x of size %d to nvram pos:%d\n", *old_dword, size, - nvram_pos-size); - return nvram_pos; -} - #endif /* _HUDSON_EARLY_SETUP_C_ */ diff --git a/src/southbridge/amd/agesa/hudson/hudson.h b/src/southbridge/amd/agesa/hudson/hudson.h index 18303fc5cb..4927a3adfd 100644 --- a/src/southbridge/amd/agesa/hudson/hudson.h +++ b/src/southbridge/amd/agesa/hudson/hudson.h @@ -65,9 +65,6 @@ void hudson_lpc_port80(void); void hudson_pci_port80(void); void hudson_clk_output_48Mhz(void); -int s3_save_nvram_early(u32 dword, int size, int nvram_pos); -int s3_load_nvram_early(int size, u32 *old_dword, int nvram_pos); - void hudson_enable(struct device *dev); #endif /* HUDSON_H */ diff --git a/src/southbridge/amd/pi/hudson/early_setup.c b/src/southbridge/amd/pi/hudson/early_setup.c index 34a3513b63..3453021a5e 100644 --- a/src/southbridge/amd/pi/hudson/early_setup.c +++ b/src/southbridge/amd/pi/hudson/early_setup.c @@ -230,36 +230,6 @@ void lpc_wideio_16_window(uint16_t base) lpc_wideio_window(base, 16); } -int s3_save_nvram_early(u32 dword, int size, int nvram_pos) -{ - int i; - printk(BIOS_DEBUG, "Writing %x of size %d to nvram pos: %d\n", dword, size, nvram_pos); - - for (i = 0; i < size; i++) { - outb(nvram_pos, BIOSRAM_INDEX); - outb((dword >> (8 * i)) & 0xff, BIOSRAM_DATA); - nvram_pos++; - } - - return nvram_pos; -} - -int s3_load_nvram_early(int size, u32 *old_dword, int nvram_pos) -{ - u32 data = *old_dword; - int i; - for (i = 0; i < size; i++) { - outb(nvram_pos, BIOSRAM_INDEX); - data &= ~(0xff << (i * 8)); - data |= inb(BIOSRAM_DATA) << (i *8); - nvram_pos++; - } - *old_dword = data; - printk(BIOS_DEBUG, "Loading %x of size %d to nvram pos:%d\n", *old_dword, size, - nvram_pos-size); - return nvram_pos; -} - void hudson_clk_output_48Mhz(void) { u32 ctrl; diff --git a/src/southbridge/amd/pi/hudson/hudson.h b/src/southbridge/amd/pi/hudson/hudson.h index b24629f0a1..ac35536bc2 100644 --- a/src/southbridge/amd/pi/hudson/hudson.h +++ b/src/southbridge/amd/pi/hudson/hudson.h @@ -180,8 +180,6 @@ void hudson_set_readspeed(u16 norm, u16 fast); void lpc_wideio_512_window(uint16_t base); void lpc_wideio_16_window(uint16_t base); void hudson_tpm_decode_spi(void); -int s3_save_nvram_early(u32 dword, int size, int nvram_pos); -int s3_load_nvram_early(int size, u32 *old_dword, int nvram_pos); void configure_hudson_uart(void); void hudson_enable(struct device *dev); From 5cdbce80724d47edcfe0374245b4f304f99f6dd0 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ky=C3=B6sti=20M=C3=A4lkki?= Date: Mon, 2 Dec 2019 05:09:11 +0200 Subject: [PATCH 0515/1242] AGESA boards: Drop commented out code MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Change-Id: I9db1147c5e112e5e6832eeece2214fece8aa6b83 Signed-off-by: Kyösti Mälkki Reviewed-on: https://review.coreboot.org/c/coreboot/+/37409 Tested-by: build bot (Jenkins) Reviewed-by: Michał Żygowski --- src/mainboard/amd/olivehill/mptable.c | 38 ----------------------- src/mainboard/asrock/imb-a180/mptable.c | 38 ----------------------- src/mainboard/biostar/a68n_5200/mptable.c | 38 ----------------------- src/mainboard/hp/abm/mptable.c | 38 ----------------------- 4 files changed, 152 deletions(-) diff --git a/src/mainboard/amd/olivehill/mptable.c b/src/mainboard/amd/olivehill/mptable.c index 75d026e00a..3054effc19 100644 --- a/src/mainboard/amd/olivehill/mptable.c +++ b/src/mainboard/amd/olivehill/mptable.c @@ -99,45 +99,7 @@ static void *smp_write_config_table(void *v) outb(byte | 0x80, 0xC00); outb(intr_data[byte], 0xC01); } -#if 0 - outb(0x0B, 0xCD6); - outb(0x02, 0xCD7); - outb(0x50, 0xCD6); - outb(0x1F, 0xCD7); - - outb(0x48, 0xCD6); - outb(0xF2, 0xCD7); - - //outb(0xBE, 0xCD6); - //outb(0x52, 0xCD7); - - outb(0xED, 0xCD6); - outb(0x17, 0xCD7); - - *(volatile u8 *) (0xFED80D00 + 0x31) = 2; - *(volatile u8 *) (0xFED80D00 + 0x32) = 2; - *(volatile u8 *) (0xFED80D00 + 0x33) = 2; - *(volatile u8 *) (0xFED80D00 + 0x34) = 2; - - *(volatile u8 *) (0xFED80100 + 0x31) = 0xc8; - *(volatile u8 *) (0xFED80100 + 0x32) = 0xc8; - *(volatile u8 *) (0xFED80100 + 0x33) = 0xc8; - *(volatile u8 *) (0xFED80100 + 0x34) = 0xa0; - - *(volatile u8 *) (0xFED80D00 + 0x6c) = 1; - *(volatile u8 *) (0xFED80D00 + 0x6E) = 2; - *(volatile u8 *) (0xFED80D00 + 0x6f) = 2; - - *(volatile u8 *) (0xFED80100 + 0x6c) = 0xa0; - *(volatile u8 *) (0xFED80100 + 0x6E) = 0xa8; - *(volatile u8 *) (0xFED80100 + 0x6f) = 0xa0; - - *(volatile u8 *) (0xFED80D00 + 0xA6) = 2; - *(volatile u8 *) (0xFED80100 + 0xA6) = 0; - - *(volatile u8 *) (0xFED80100 + 0x40) = 0xC8; -#endif /* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ #define IO_LOCAL_INT(type, intr, apicid, pin) \ smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin)); diff --git a/src/mainboard/asrock/imb-a180/mptable.c b/src/mainboard/asrock/imb-a180/mptable.c index a3c8e517bb..fd4dff7f08 100644 --- a/src/mainboard/asrock/imb-a180/mptable.c +++ b/src/mainboard/asrock/imb-a180/mptable.c @@ -100,45 +100,7 @@ static void *smp_write_config_table(void *v) outb(byte | 0x80, 0xC00); outb(intr_data[byte], 0xC01); } -#if 0 - outb(0x0B, 0xCD6); - outb(0x02, 0xCD7); - outb(0x50, 0xCD6); - outb(0x1F, 0xCD7); - - outb(0x48, 0xCD6); - outb(0xF2, 0xCD7); - - //outb(0xBE, 0xCD6); - //outb(0x52, 0xCD7); - - outb(0xED, 0xCD6); - outb(0x17, 0xCD7); - - *(volatile u8 *) (0xFED80D00 + 0x31) = 2; - *(volatile u8 *) (0xFED80D00 + 0x32) = 2; - *(volatile u8 *) (0xFED80D00 + 0x33) = 2; - *(volatile u8 *) (0xFED80D00 + 0x34) = 2; - - *(volatile u8 *) (0xFED80100 + 0x31) = 0xc8; - *(volatile u8 *) (0xFED80100 + 0x32) = 0xc8; - *(volatile u8 *) (0xFED80100 + 0x33) = 0xc8; - *(volatile u8 *) (0xFED80100 + 0x34) = 0xa0; - - *(volatile u8 *) (0xFED80D00 + 0x6c) = 1; - *(volatile u8 *) (0xFED80D00 + 0x6E) = 2; - *(volatile u8 *) (0xFED80D00 + 0x6f) = 2; - - *(volatile u8 *) (0xFED80100 + 0x6c) = 0xa0; - *(volatile u8 *) (0xFED80100 + 0x6E) = 0xa8; - *(volatile u8 *) (0xFED80100 + 0x6f) = 0xa0; - - *(volatile u8 *) (0xFED80D00 + 0xA6) = 2; - *(volatile u8 *) (0xFED80100 + 0xA6) = 0; - - *(volatile u8 *) (0xFED80100 + 0x40) = 0xC8; -#endif /* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ #define IO_LOCAL_INT(type, intr, apicid, pin) \ smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin)); diff --git a/src/mainboard/biostar/a68n_5200/mptable.c b/src/mainboard/biostar/a68n_5200/mptable.c index 75d026e00a..3054effc19 100644 --- a/src/mainboard/biostar/a68n_5200/mptable.c +++ b/src/mainboard/biostar/a68n_5200/mptable.c @@ -99,45 +99,7 @@ static void *smp_write_config_table(void *v) outb(byte | 0x80, 0xC00); outb(intr_data[byte], 0xC01); } -#if 0 - outb(0x0B, 0xCD6); - outb(0x02, 0xCD7); - outb(0x50, 0xCD6); - outb(0x1F, 0xCD7); - - outb(0x48, 0xCD6); - outb(0xF2, 0xCD7); - - //outb(0xBE, 0xCD6); - //outb(0x52, 0xCD7); - - outb(0xED, 0xCD6); - outb(0x17, 0xCD7); - - *(volatile u8 *) (0xFED80D00 + 0x31) = 2; - *(volatile u8 *) (0xFED80D00 + 0x32) = 2; - *(volatile u8 *) (0xFED80D00 + 0x33) = 2; - *(volatile u8 *) (0xFED80D00 + 0x34) = 2; - - *(volatile u8 *) (0xFED80100 + 0x31) = 0xc8; - *(volatile u8 *) (0xFED80100 + 0x32) = 0xc8; - *(volatile u8 *) (0xFED80100 + 0x33) = 0xc8; - *(volatile u8 *) (0xFED80100 + 0x34) = 0xa0; - - *(volatile u8 *) (0xFED80D00 + 0x6c) = 1; - *(volatile u8 *) (0xFED80D00 + 0x6E) = 2; - *(volatile u8 *) (0xFED80D00 + 0x6f) = 2; - - *(volatile u8 *) (0xFED80100 + 0x6c) = 0xa0; - *(volatile u8 *) (0xFED80100 + 0x6E) = 0xa8; - *(volatile u8 *) (0xFED80100 + 0x6f) = 0xa0; - - *(volatile u8 *) (0xFED80D00 + 0xA6) = 2; - *(volatile u8 *) (0xFED80100 + 0xA6) = 0; - - *(volatile u8 *) (0xFED80100 + 0x40) = 0xC8; -#endif /* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ #define IO_LOCAL_INT(type, intr, apicid, pin) \ smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin)); diff --git a/src/mainboard/hp/abm/mptable.c b/src/mainboard/hp/abm/mptable.c index 75d026e00a..3054effc19 100644 --- a/src/mainboard/hp/abm/mptable.c +++ b/src/mainboard/hp/abm/mptable.c @@ -99,45 +99,7 @@ static void *smp_write_config_table(void *v) outb(byte | 0x80, 0xC00); outb(intr_data[byte], 0xC01); } -#if 0 - outb(0x0B, 0xCD6); - outb(0x02, 0xCD7); - outb(0x50, 0xCD6); - outb(0x1F, 0xCD7); - - outb(0x48, 0xCD6); - outb(0xF2, 0xCD7); - - //outb(0xBE, 0xCD6); - //outb(0x52, 0xCD7); - - outb(0xED, 0xCD6); - outb(0x17, 0xCD7); - - *(volatile u8 *) (0xFED80D00 + 0x31) = 2; - *(volatile u8 *) (0xFED80D00 + 0x32) = 2; - *(volatile u8 *) (0xFED80D00 + 0x33) = 2; - *(volatile u8 *) (0xFED80D00 + 0x34) = 2; - - *(volatile u8 *) (0xFED80100 + 0x31) = 0xc8; - *(volatile u8 *) (0xFED80100 + 0x32) = 0xc8; - *(volatile u8 *) (0xFED80100 + 0x33) = 0xc8; - *(volatile u8 *) (0xFED80100 + 0x34) = 0xa0; - - *(volatile u8 *) (0xFED80D00 + 0x6c) = 1; - *(volatile u8 *) (0xFED80D00 + 0x6E) = 2; - *(volatile u8 *) (0xFED80D00 + 0x6f) = 2; - - *(volatile u8 *) (0xFED80100 + 0x6c) = 0xa0; - *(volatile u8 *) (0xFED80100 + 0x6E) = 0xa8; - *(volatile u8 *) (0xFED80100 + 0x6f) = 0xa0; - - *(volatile u8 *) (0xFED80D00 + 0xA6) = 2; - *(volatile u8 *) (0xFED80100 + 0xA6) = 0; - - *(volatile u8 *) (0xFED80100 + 0x40) = 0xC8; -#endif /* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ #define IO_LOCAL_INT(type, intr, apicid, pin) \ smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin)); From 08c8cf9586ab9f75ab6d26fc8d80f14bd8087a1b Mon Sep 17 00:00:00 2001 From: Patrick Georgi Date: Mon, 2 Dec 2019 11:43:20 +0100 Subject: [PATCH 0516/1242] soc/intel/common/cse: Update comment for post-CAR global world MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Change-Id: I4ec9d7d3af1c4d7713ec5dfe516b24d110303ff1 Signed-off-by: Patrick Georgi Reviewed-on: https://review.coreboot.org/c/coreboot/+/37412 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki --- src/soc/intel/common/block/cse/cse.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/soc/intel/common/block/cse/cse.c b/src/soc/intel/common/block/cse/cse.c index 99218253ae..011916dd92 100644 --- a/src/soc/intel/common/block/cse/cse.c +++ b/src/soc/intel/common/block/cse/cse.c @@ -146,7 +146,7 @@ static uint32_t get_cse_bar(void) static uint32_t read_bar(uint32_t offset) { - /* Reach PCI config space to get BAR in case CAR global not available */ + /* Load and cache BAR */ if (!cse.sec_bar) cse.sec_bar = get_cse_bar(); return read32((void *)(cse.sec_bar + offset)); @@ -154,7 +154,7 @@ static uint32_t read_bar(uint32_t offset) static void write_bar(uint32_t offset, uint32_t val) { - /* Reach PCI config space to get BAR in case CAR global not available */ + /* Load and cache BAR */ if (!cse.sec_bar) cse.sec_bar = get_cse_bar(); return write32((void *)(cse.sec_bar + offset), val); From a37eef131a81f25647ee9896d2bca3b39f8fa2c2 Mon Sep 17 00:00:00 2001 From: Patrick Georgi Date: Mon, 2 Dec 2019 11:42:44 +0100 Subject: [PATCH 0517/1242] soc/nvidia/tegra: Constify variable MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Change-Id: Iab0a442e6dbde0f9abdf2d8689f9891b79a2d37a Signed-off-by: Patrick Georgi Reviewed-on: https://review.coreboot.org/c/coreboot/+/37413 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki --- src/soc/nvidia/tegra/i2c.h | 2 +- src/soc/nvidia/tegra124/i2c.c | 2 +- src/soc/nvidia/tegra210/i2c.c | 2 +- 3 files changed, 3 insertions(+), 3 deletions(-) diff --git a/src/soc/nvidia/tegra/i2c.h b/src/soc/nvidia/tegra/i2c.h index c32450b824..440af69387 100644 --- a/src/soc/nvidia/tegra/i2c.h +++ b/src/soc/nvidia/tegra/i2c.h @@ -168,6 +168,6 @@ struct tegra_i2c_regs { }; check_member(tegra_i2c_regs, config_load, 0x8C); -extern unsigned int num_i2c_buses; +extern const unsigned int num_i2c_buses; #endif /* __SOC_NVIDIA_TEGRA_I2C_H__ */ diff --git a/src/soc/nvidia/tegra124/i2c.c b/src/soc/nvidia/tegra124/i2c.c index 0d65b9a018..e2c5a44ebe 100644 --- a/src/soc/nvidia/tegra124/i2c.c +++ b/src/soc/nvidia/tegra124/i2c.c @@ -50,4 +50,4 @@ struct tegra_i2c_bus_info tegra_i2c_info[] = { } }; -unsigned int num_i2c_buses = ARRAY_SIZE(tegra_i2c_info); +const unsigned int num_i2c_buses = ARRAY_SIZE(tegra_i2c_info); diff --git a/src/soc/nvidia/tegra210/i2c.c b/src/soc/nvidia/tegra210/i2c.c index 4764b78303..2fa1123cec 100644 --- a/src/soc/nvidia/tegra210/i2c.c +++ b/src/soc/nvidia/tegra210/i2c.c @@ -50,4 +50,4 @@ struct tegra_i2c_bus_info tegra_i2c_info[] = { } }; -unsigned int num_i2c_buses = ARRAY_SIZE(tegra_i2c_info); +const unsigned int num_i2c_buses = ARRAY_SIZE(tegra_i2c_info); From 91e7fe7b547396857c7165a2c68aad5fda8730e4 Mon Sep 17 00:00:00 2001 From: Marshall Dawson Date: Sun, 24 Nov 2019 17:19:19 -0700 Subject: [PATCH 0518/1242] soc/amd/stoneyridge: Use USE_AMD_BLOBS to remove default paths Remove default path/to/file strings when USE_AMD_BLOBS is not enabled. This will result in a buildable, but not runable image, in the default configuration. Drop the check for HAVE_MERLINFALCON_BINARIES in the path default. A later patch will address the poor use of this symbol All PSP blobs are still assumed to be in the same directory as the AMD public key. Qualify building the amdfw.rom intermediate image and including it into coreboot.rom on whether the public key remains "". This change infers it's OK to skip xHCI and GEC firmware too, although the images normally reside in a separate directory. This change only determines whether default paths and names exist. Paths will be updated in a follow-on patch. Change-Id: Ic21fbd7a58b340a9bcaaea456e1f38b567215b81 Signed-off-by: Marshall Dawson Reviewed-on: https://review.coreboot.org/c/coreboot/+/37220 Reviewed-by: Richard Spiegel Tested-by: build bot (Jenkins) --- src/soc/amd/stoneyridge/Kconfig | 7 +++++-- src/soc/amd/stoneyridge/Makefile.inc | 22 +++++++++++++++------- 2 files changed, 20 insertions(+), 9 deletions(-) diff --git a/src/soc/amd/stoneyridge/Kconfig b/src/soc/amd/stoneyridge/Kconfig index bb297a9356..a5607b4c88 100644 --- a/src/soc/amd/stoneyridge/Kconfig +++ b/src/soc/amd/stoneyridge/Kconfig @@ -174,7 +174,8 @@ config VGA_BIOS_ID config VGA_BIOS_FILE string - default "3rdparty/blobs/soc/amd/merlinfalcon/VBIOS.bin" if AMD_APU_MERLINFALCON && HAVE_MERLINFALCON_BINARIES + default "" if !USE_AMD_BLOBS + default "3rdparty/blobs/soc/amd/merlinfalcon/VBIOS.bin" if AMD_APU_MERLINFALCON default "3rdparty/blobs/soc/amd/stoneyridge/VBIOS.bin" config S3_VGA_ROM_RUN @@ -214,6 +215,7 @@ config STONEYRIDGE_GEC_FWM config STONEYRIDGE_XHCI_FWM_FILE string "XHCI firmware path and filename" + default "" if !USE_AMD_BLOBS default "3rdparty/blobs/soc/amd/stoneyridge/xhci.bin" depends on STONEYRIDGE_XHCI_FWM @@ -223,7 +225,8 @@ config STONEYRIDGE_GEC_FWM_FILE config AMD_PUBKEY_FILE string "AMD public Key" - default "3rdparty/blobs/soc/amd/merlinfalcon/PSP/AmdPubKeyCZ.bin" if AMD_APU_MERLINFALCON && HAVE_MERLINFALCON_BINARIES + default "" if !USE_AMD_BLOBS + default "3rdparty/blobs/soc/amd/merlinfalcon/PSP/AmdPubKeyCZ.bin" if AMD_APU_MERLINFALCON default "3rdparty/blobs/soc/amd/stoneyridge/PSP/AmdPubKeyST.bin" config STONEYRIDGE_SATA_MODE diff --git a/src/soc/amd/stoneyridge/Makefile.inc b/src/soc/amd/stoneyridge/Makefile.inc index f697fc2e65..d2d64c805c 100644 --- a/src/soc/amd/stoneyridge/Makefile.inc +++ b/src/soc/amd/stoneyridge/Makefile.inc @@ -137,20 +137,15 @@ STONEYRIDGE_FWM_POSITION=$(call int-add, \ ### 0 FIRMWARE_LOCATE=$(dir $(call strip_quotes, $(CONFIG_AMD_PUBKEY_FILE))) +ifneq ($(FIRMWARE_LOCATE),) ifeq ($(CONFIG_AMD_APU_STONEYRIDGE),y) FIRMWARE_TYPE=ST else - ifeq ($(CONFIG_AMD_APU_MERLINFALCON),y) -# If Merlin Falcon, but blobs aren't present, use Stoney Ridge instead -ifeq ($(CONFIG_HAVE_MERLINFALCON_BINARIES),y) FIRMWARE_TYPE=CZ else -FIRMWARE_TYPE=ST -endif # CONFIG_HAVE_MERLINFALCON_BINARIES -else -$(error stoneyridge: Unknown FIRMWARE_TYPE) +$(error soc/amd/stoneyridge: Unusable FIRMWARE_TYPE) endif # CONFIG_AMD_APU_MERLINFALCON endif # CONFIG_AMD_APU_STONEYRIDGE @@ -332,4 +327,17 @@ endif endif # ifeq ($(CONFIG_SOC_AMD_PSP_SELECTABLE_SMU_FW),y) +else # ifneq ($(FIRMWARE_LOCATE),) + +warn_no_amdfw: + printf "\n\t** WARNING **\n" + printf "coreboot has been built with no PSP firmware and " + printf "a non-booting image has been generated.\n\n" + +PHONY+=warn_no_amdfw + +files_added:: warn_no_amdfw + +endif # ifneq ($(FIRMWARE_LOCATE),) + endif # ($(CONFIG_SOC_AMD_MERLINFALCON)$(CONFIG_SOC_AMD_STONEYRIDGE_FP4)$(CONFIG_SOC_AMD_STONEYRIDGE_FT4),y) From 73b1bd7992fb33f33c33747fd0919fc495c3d5c4 Mon Sep 17 00:00:00 2001 From: Subrata Banik Date: Thu, 28 Nov 2019 13:56:24 +0530 Subject: [PATCH 0519/1242] soc/intel/cannonlake: Configure GPIO PM configuration in bootblock This patch performs below operations: 1. Rename soc_fill_gpio_pm_configuration to soc_gpio_pm_configuration 2. Move soc_gpio_pm_configuration() to gpio_common.c 3. Calling from bootblock and after FSP-S to ensure GPIO PM configuration is updated with devicetree.cb value even with platform reset. BUG=b:144002424 TEST=coreboot configures all MISCCFG.bit 0-5 local clock gating based on devicetree.cb Change-Id: I54061d556d62462d9012bc47bb9f3604a3e5a250 Signed-off-by: Subrata Banik Reviewed-on: https://review.coreboot.org/c/coreboot/+/37319 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh --- src/soc/intel/cannonlake/Makefile.inc | 3 ++ src/soc/intel/cannonlake/bootblock/pch.c | 4 +++ src/soc/intel/cannonlake/chip.c | 19 ++--------- src/soc/intel/cannonlake/gpio_common.c | 38 +++++++++++++++++++++ src/soc/intel/cannonlake/include/soc/gpio.h | 6 ++++ 5 files changed, 53 insertions(+), 17 deletions(-) create mode 100644 src/soc/intel/cannonlake/gpio_common.c diff --git a/src/soc/intel/cannonlake/Makefile.inc b/src/soc/intel/cannonlake/Makefile.inc index 0fcbcd15e6..c744e9953d 100644 --- a/src/soc/intel/cannonlake/Makefile.inc +++ b/src/soc/intel/cannonlake/Makefile.inc @@ -89,6 +89,9 @@ smm-y += gpio.c verstage-y += gpio.c endif +bootblock-y += gpio_common.c +ramstage-y += gpio_common.c + ifeq ($(CONFIG_SOC_INTEL_CANNONLAKE),y) # Not yet in intel-microcode repo #cpu_microcode_bins += $(wildcard 3rdparty/intel-microcode/intel-ucode/06-66-*) diff --git a/src/soc/intel/cannonlake/bootblock/pch.c b/src/soc/intel/cannonlake/bootblock/pch.c index 39433a26d9..9ad7e86178 100644 --- a/src/soc/intel/cannonlake/bootblock/pch.c +++ b/src/soc/intel/cannonlake/bootblock/pch.c @@ -28,6 +28,7 @@ #include #include #include +#include #include #include #include @@ -198,4 +199,7 @@ void pch_early_init(void) pmc_gpe_init(); enable_rtc_upper_bank(); + + /* GPIO community PM configuration */ + soc_gpio_pm_configuration(); } diff --git a/src/soc/intel/cannonlake/chip.c b/src/soc/intel/cannonlake/chip.c index 0ce2f1aca7..2bb1c92612 100644 --- a/src/soc/intel/cannonlake/chip.c +++ b/src/soc/intel/cannonlake/chip.c @@ -23,6 +23,7 @@ #include #include #include +#include #include #include @@ -166,22 +167,6 @@ void cnl_configure_pads(const struct pad_config *cfg, size_t num_pads) gpio_configure_pads(cfg, num_pads); } -/* SoC rotine to fill GPIO PM mask and value for GPIO_MISCCFG register */ -static void soc_fill_gpio_pm_configuration(void) -{ - uint8_t value[TOTAL_GPIO_COMM]; - const config_t *config = config_of_soc(); - - if (config->gpio_override_pm) - memcpy(value, config->gpio_pm, sizeof(uint8_t) * - TOTAL_GPIO_COMM); - else - memset(value, MISCCFG_ENABLE_GPIO_PM_CONFIG, sizeof(uint8_t) * - TOTAL_GPIO_COMM); - - gpio_pm_configure(value, TOTAL_GPIO_COMM); -} - void soc_init_pre_device(void *chip_info) { /* Perform silicon specific init. */ @@ -193,7 +178,7 @@ void soc_init_pre_device(void *chip_info) /* TODO(furquan): Get rid of this workaround once FSP is fixed. */ cnl_configure_pads(NULL, 0); - soc_fill_gpio_pm_configuration(); + soc_gpio_pm_configuration(); } static void pci_domain_set_resources(struct device *dev) diff --git a/src/soc/intel/cannonlake/gpio_common.c b/src/soc/intel/cannonlake/gpio_common.c new file mode 100644 index 0000000000..360189a0fd --- /dev/null +++ b/src/soc/intel/cannonlake/gpio_common.c @@ -0,0 +1,38 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include + +/* + * Routine to perform below operations: + * 1. SoC rotine to fill GPIO PM mask and value for GPIO_MISCCFG register + * 2. Program GPIO PM configuration based on PM mask and value + */ +void soc_gpio_pm_configuration(void) +{ + uint8_t value[TOTAL_GPIO_COMM]; + const config_t *config = config_of_soc(); + + if (config->gpio_override_pm) + memcpy(value, config->gpio_pm, sizeof(uint8_t) * + TOTAL_GPIO_COMM); + else + memset(value, MISCCFG_ENABLE_GPIO_PM_CONFIG, sizeof(uint8_t) * + TOTAL_GPIO_COMM); + + gpio_pm_configure(value, TOTAL_GPIO_COMM); +} diff --git a/src/soc/intel/cannonlake/include/soc/gpio.h b/src/soc/intel/cannonlake/include/soc/gpio.h index e7056ebcec..efed88180c 100644 --- a/src/soc/intel/cannonlake/include/soc/gpio.h +++ b/src/soc/intel/cannonlake/include/soc/gpio.h @@ -28,6 +28,12 @@ #ifndef __ACPI__ struct pad_config; void cnl_configure_pads(const struct pad_config *cfg, size_t num_pads); +/* + * Routine to perform below operations: + * 1. SoC routine to fill GPIO PM mask and value for GPIO_MISCCFG register + * 2. Program GPIO PM configuration based on PM mask and value + */ +void soc_gpio_pm_configuration(void); #endif #endif From 54daaecacb69194b282484d2c2488c3f5eabc02d Mon Sep 17 00:00:00 2001 From: Subrata Banik Date: Thu, 28 Nov 2019 14:02:10 +0530 Subject: [PATCH 0520/1242] mb/google/drallion: Disable GPIO dynamic PM configuration BUG=b:144002424 TEST=Ensured no TPM time out issue and system can boot to OS Change-Id: I7282e6c2d9627846039638bdc0db3ee7ebba5f12 Signed-off-by: Subrata Banik Reviewed-on: https://review.coreboot.org/c/coreboot/+/37320 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh --- .../drallion/variants/arcada_cml/devicetree.cb | 12 +++++++----- .../drallion/variants/drallion/devicetree.cb | 16 +++++++--------- .../drallion/variants/sarien_cml/devicetree.cb | 12 +++++++----- 3 files changed, 21 insertions(+), 19 deletions(-) diff --git a/src/mainboard/google/drallion/variants/arcada_cml/devicetree.cb b/src/mainboard/google/drallion/variants/arcada_cml/devicetree.cb index 5f396fe353..11abc87daa 100644 --- a/src/mainboard/google/drallion/variants/arcada_cml/devicetree.cb +++ b/src/mainboard/google/drallion/variants/arcada_cml/devicetree.cb @@ -212,11 +212,13 @@ chip soc/intel/cannonlake register "gpio_override_pm" = "1" # GPIO community PM configuration - register "gpio_pm[COMM_0]" = "MISCCFG_ENABLE_GPIO_PM_CONFIG" - register "gpio_pm[COMM_1]" = "MISCCFG_GPSIDEDPCGEN | MISCCFG_GPRTCDLCGEN | MISCCFG_GSXSLCGEN | MISCCFG_GPDPCGEN | MISCCFG_GPDLCGEN" - register "gpio_pm[COMM_2]" = "MISCCFG_ENABLE_GPIO_PM_CONFIG" - register "gpio_pm[COMM_3]" = "MISCCFG_ENABLE_GPIO_PM_CONFIG" - register "gpio_pm[COMM_4]" = "MISCCFG_ENABLE_GPIO_PM_CONFIG" + # Disable dynamic clock gating; with bits 0-5 set in these registers, + # some short interrupt pulses were missed (esp. cr50 irq) + register "gpio_pm[COMM_0]" = "0" + register "gpio_pm[COMM_1]" = "0" + register "gpio_pm[COMM_2]" = "0" + register "gpio_pm[COMM_3]" = "0" + register "gpio_pm[COMM_4]" = "0" device cpu_cluster 0 on device lapic 0 on end diff --git a/src/mainboard/google/drallion/variants/drallion/devicetree.cb b/src/mainboard/google/drallion/variants/drallion/devicetree.cb index 4c5cff25a0..2fcf191eae 100644 --- a/src/mainboard/google/drallion/variants/drallion/devicetree.cb +++ b/src/mainboard/google/drallion/variants/drallion/devicetree.cb @@ -209,15 +209,13 @@ chip soc/intel/cannonlake register "gpio_override_pm" = "1" # GPIO community PM configuration - register "gpio_pm[COMM_0]" = "MISCCFG_ENABLE_GPIO_PM_CONFIG" - register "gpio_pm[COMM_1]" = "MISCCFG_GPSIDEDPCGEN | - MISCCFG_GPRTCDLCGEN | - MISCCFG_GSXSLCGEN | - MISCCFG_GPDPCGEN | - MISCCFG_GPDLCGEN" - register "gpio_pm[COMM_2]" = "MISCCFG_ENABLE_GPIO_PM_CONFIG" - register "gpio_pm[COMM_3]" = "MISCCFG_ENABLE_GPIO_PM_CONFIG" - register "gpio_pm[COMM_4]" = "MISCCFG_ENABLE_GPIO_PM_CONFIG" + # Disable dynamic clock gating; with bits 0-5 set in these registers, + # some short interrupt pulses were missed (esp. cr50 irq) + register "gpio_pm[COMM_0]" = "0" + register "gpio_pm[COMM_1]" = "0" + register "gpio_pm[COMM_2]" = "0" + register "gpio_pm[COMM_3]" = "0" + register "gpio_pm[COMM_4]" = "0" device cpu_cluster 0 on device lapic 0 on end diff --git a/src/mainboard/google/drallion/variants/sarien_cml/devicetree.cb b/src/mainboard/google/drallion/variants/sarien_cml/devicetree.cb index 8cb1aa3001..c466637918 100644 --- a/src/mainboard/google/drallion/variants/sarien_cml/devicetree.cb +++ b/src/mainboard/google/drallion/variants/sarien_cml/devicetree.cb @@ -215,11 +215,13 @@ chip soc/intel/cannonlake register "gpio_override_pm" = "1" # GPIO community PM configuration - register "gpio_pm[COMM_0]" = "MISCCFG_ENABLE_GPIO_PM_CONFIG" - register "gpio_pm[COMM_1]" = "MISCCFG_GPSIDEDPCGEN | MISCCFG_GPRTCDLCGEN | MISCCFG_GSXSLCGEN | MISCCFG_GPDPCGEN | MISCCFG_GPDLCGEN" - register "gpio_pm[COMM_2]" = "MISCCFG_ENABLE_GPIO_PM_CONFIG" - register "gpio_pm[COMM_3]" = "MISCCFG_ENABLE_GPIO_PM_CONFIG" - register "gpio_pm[COMM_4]" = "MISCCFG_ENABLE_GPIO_PM_CONFIG" + # Disable dynamic clock gating; with bits 0-5 set in these registers, + # some short interrupt pulses were missed (esp. cr50 irq) + register "gpio_pm[COMM_0]" = "0" + register "gpio_pm[COMM_1]" = "0" + register "gpio_pm[COMM_2]" = "0" + register "gpio_pm[COMM_3]" = "0" + register "gpio_pm[COMM_4]" = "0" device cpu_cluster 0 on device lapic 0 on end From 70a03dd9605c6a973bbb78e64e626e8af377ad74 Mon Sep 17 00:00:00 2001 From: Elyes HAOUAS Date: Mon, 2 Dec 2019 20:47:50 +0100 Subject: [PATCH 0521/1242] src: Add missing include Change-Id: I17dc2fed6c6518daf5af286788c98c049088911e Signed-off-by: Elyes HAOUAS Reviewed-on: https://review.coreboot.org/c/coreboot/+/37366 Tested-by: build bot (Jenkins) Reviewed-by: Werner Zeh --- src/arch/x86/acpi_device.c | 1 + src/commonlib/storage/sdhci_adma.c | 1 + src/mainboard/emulation/qemu-i440fx/fw_cfg.c | 1 + src/mainboard/sifive/hifive-unleashed/fixup_fdt.c | 1 + src/soc/intel/broadwell/me.c | 1 + 5 files changed, 5 insertions(+) diff --git a/src/arch/x86/acpi_device.c b/src/arch/x86/acpi_device.c index d367108457..5c77953bc2 100644 --- a/src/arch/x86/acpi_device.c +++ b/src/arch/x86/acpi_device.c @@ -17,6 +17,7 @@ #include #include #include +#include #if CONFIG(GENERIC_GPIO_LIB) #include #endif diff --git a/src/commonlib/storage/sdhci_adma.c b/src/commonlib/storage/sdhci_adma.c index 2806bdeaee..2ca4b5557c 100644 --- a/src/commonlib/storage/sdhci_adma.c +++ b/src/commonlib/storage/sdhci_adma.c @@ -19,6 +19,7 @@ #include #include #include +#include #include #include "sdhci.h" diff --git a/src/mainboard/emulation/qemu-i440fx/fw_cfg.c b/src/mainboard/emulation/qemu-i440fx/fw_cfg.c index 580e09ad45..50123f97b4 100644 --- a/src/mainboard/emulation/qemu-i440fx/fw_cfg.c +++ b/src/mainboard/emulation/qemu-i440fx/fw_cfg.c @@ -12,6 +12,7 @@ */ #include +#include #include #include #include diff --git a/src/mainboard/sifive/hifive-unleashed/fixup_fdt.c b/src/mainboard/sifive/hifive-unleashed/fixup_fdt.c index 8ac6ff1208..3d431812fa 100644 --- a/src/mainboard/sifive/hifive-unleashed/fixup_fdt.c +++ b/src/mainboard/sifive/hifive-unleashed/fixup_fdt.c @@ -14,6 +14,7 @@ */ #include +#include #include #include #include diff --git a/src/soc/intel/broadwell/me.c b/src/soc/intel/broadwell/me.c index 0021d2c48a..448c5dada9 100644 --- a/src/soc/intel/broadwell/me.c +++ b/src/soc/intel/broadwell/me.c @@ -29,6 +29,7 @@ #include #include #include +#include #include #include #include From d14673f0b11c72a6c1493caa25334cbb63a66682 Mon Sep 17 00:00:00 2001 From: Dtrain Hsu Date: Tue, 26 Nov 2019 10:34:27 +0800 Subject: [PATCH 0522/1242] hatch: Create stryke variant (Auto-Generated by create_coreboot_variant.sh version 1.0.0). BUG=b:145101696 TEST=util/abuild/abuild -p none -t google/hatch -x -a make sure the build includes GOOGLE_STRYKE Signed-off-by: Dtrain Hsu Change-Id: Iea6f8a1c6c24a1e3545c364551cb623debdc4a1a Reviewed-on: https://review.coreboot.org/c/coreboot/+/37229 Tested-by: build bot (Jenkins) Reviewed-by: Tim Wawrzynczak --- src/mainboard/google/hatch/Kconfig | 2 + src/mainboard/google/hatch/Kconfig.name | 5 + .../google/hatch/variants/stryke/Makefile.inc | 22 ++ .../google/hatch/variants/stryke/gpio.c | 110 +++++++++ .../stryke/include/variant/acpi/dptf.asl | 14 ++ .../variants/stryke/include/variant/ec.h | 19 ++ .../variants/stryke/include/variant/gpio.h | 25 ++ .../hatch/variants/stryke/overridetree.cb | 215 ++++++++++++++++++ 8 files changed, 412 insertions(+) create mode 100644 src/mainboard/google/hatch/variants/stryke/Makefile.inc create mode 100644 src/mainboard/google/hatch/variants/stryke/gpio.c create mode 100644 src/mainboard/google/hatch/variants/stryke/include/variant/acpi/dptf.asl create mode 100644 src/mainboard/google/hatch/variants/stryke/include/variant/ec.h create mode 100644 src/mainboard/google/hatch/variants/stryke/include/variant/gpio.h create mode 100644 src/mainboard/google/hatch/variants/stryke/overridetree.cb diff --git a/src/mainboard/google/hatch/Kconfig b/src/mainboard/google/hatch/Kconfig index fce1b875fe..98a0174dfe 100644 --- a/src/mainboard/google/hatch/Kconfig +++ b/src/mainboard/google/hatch/Kconfig @@ -96,6 +96,7 @@ config MAINBOARD_PART_NUMBER default "Kindred" if BOARD_GOOGLE_KINDRED default "Kohaku" if BOARD_GOOGLE_KOHAKU default "Puff" if BOARD_GOOGLE_PUFF + default "Stryke" if BOARD_GOOGLE_STRYKE config MAX_CPUS int @@ -121,6 +122,7 @@ config VARIANT_DIR default "kindred" if BOARD_GOOGLE_KINDRED default "kohaku" if BOARD_GOOGLE_KOHAKU default "puff" if BOARD_GOOGLE_PUFF + default "stryke" if BOARD_GOOGLE_STRYKE config VBOOT select HAS_RECOVERY_MRC_CACHE diff --git a/src/mainboard/google/hatch/Kconfig.name b/src/mainboard/google/hatch/Kconfig.name index 82da88324c..ed90de6c34 100644 --- a/src/mainboard/google/hatch/Kconfig.name +++ b/src/mainboard/google/hatch/Kconfig.name @@ -50,3 +50,8 @@ config BOARD_GOOGLE_HELIOS_DISKSWAP select BOARD_ROMSIZE_KB_16384 select CHROMEOS_DSM_CALIB select DRIVERS_I2C_RT1011 + +config BOARD_GOOGLE_STRYKE + bool "-> Stryke" + select BOARD_GOOGLE_BASEBOARD_HATCH + select BOARD_ROMSIZE_KB_16384 diff --git a/src/mainboard/google/hatch/variants/stryke/Makefile.inc b/src/mainboard/google/hatch/variants/stryke/Makefile.inc new file mode 100644 index 0000000000..ab779a9bce --- /dev/null +++ b/src/mainboard/google/hatch/variants/stryke/Makefile.inc @@ -0,0 +1,22 @@ +## This file is part of the coreboot project. +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +SPD_SOURCES = 4G_2400 # 0b000 +SPD_SOURCES += empty_ddr4 # 0b001 +SPD_SOURCES += 8G_2400 # 0b010 +SPD_SOURCES += 8G_2666 # 0b011 +SPD_SOURCES += 16G_2400 # 0b100 +SPD_SOURCES += 16G_2666 # 0b101 +SPD_SOURCES += 8G_3200 # 0b110 + +bootblock-y += gpio.c +ramstage-y += gpio.c diff --git a/src/mainboard/google/hatch/variants/stryke/gpio.c b/src/mainboard/google/hatch/variants/stryke/gpio.c new file mode 100644 index 0000000000..4d27554a6b --- /dev/null +++ b/src/mainboard/google/hatch/variants/stryke/gpio.c @@ -0,0 +1,110 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2019 Google LLC + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the + * GNU General Public License for more details. + */ + +#include +#include +#include +#include + +static const struct pad_config gpio_table[] = { + /* A0 : NC */ + PAD_NC(GPP_A0, NONE), + /* A6 : NC */ + PAD_NC(GPP_A6, NONE), + /* A8 : NC */ + PAD_NC(GPP_A8, NONE), + /* A10 : NC */ + PAD_NC(GPP_A10, NONE), + /* A11 : NC */ + PAD_NC(GPP_A11, NONE), + /* A12 : NC */ + PAD_NC(GPP_A12, NONE), + /* A22 : NC */ + PAD_NC(GPP_A22, NONE), + /* A23 : NC */ + PAD_NC(GPP_A23, NONE), + /* B20 : NC */ + PAD_NC(GPP_B20, NONE), + /* B21 : NC */ + PAD_NC(GPP_B21, NONE), + /* B22 : NC */ + PAD_NC(GPP_B22, NONE), + /* C11 : NC */ + PAD_NC(GPP_C11, NONE), + /* C12 : NC */ + PAD_NC(GPP_C12, NONE), + /* F1 : NC */ + PAD_NC(GPP_F1, NONE), + /* F3 : MEM_STRAP_3 */ + PAD_CFG_GPI(GPP_F3, NONE, PLTRST), + /* F10 : MEM_STRAP_2 */ + PAD_CFG_GPI(GPP_F10, NONE, PLTRST), + /* F11 : NC */ + PAD_NC(GPP_F11, NONE), + /* F20 : NC */ + PAD_NC(GPP_F20, NONE), + /* F21 : NC */ + PAD_NC(GPP_F21, NONE), + /* F22 : NC */ + PAD_NC(GPP_F22, NONE), + /* H19 : MEM_STRAP_0 */ + PAD_CFG_GPI(GPP_H19, NONE, PLTRST), + /* H22 : MEM_STRAP_1 */ + PAD_CFG_GPI(GPP_H22, NONE, PLTRST), +}; + +const struct pad_config *override_gpio_table(size_t *num) +{ + *num = ARRAY_SIZE(gpio_table); + return gpio_table; +} + +/* + * GPIOs configured before ramstage + * Note: the Hatch platform's romstage will configure + * the MEM_STRAP_* (a.k.a GPIO_MEM_CONFIG_*) pins + * as inputs before it reads them, so they are not + * needed in this table. + */ +static const struct pad_config early_gpio_table[] = { + /* B15 : H1_SLAVE_SPI_CS_L */ + PAD_CFG_NF(GPP_B15, NONE, DEEP, NF1), + /* B16 : H1_SLAVE_SPI_CLK */ + PAD_CFG_NF(GPP_B16, NONE, DEEP, NF1), + /* B17 : H1_SLAVE_SPI_MISO_R */ + PAD_CFG_NF(GPP_B17, NONE, DEEP, NF1), + /* B18 : H1_SLAVE_SPI_MOSI_R */ + PAD_CFG_NF(GPP_B18, NONE, DEEP, NF1), + /* C14 : BT_DISABLE_L */ + PAD_CFG_GPO(GPP_C14, 0, DEEP), + /* PCH_WP_OD */ + PAD_CFG_GPI(GPP_C20, NONE, DEEP), + /* C21 : H1_PCH_INT_ODL */ + PAD_CFG_GPI_APIC(GPP_C21, NONE, PLTRST, LEVEL, INVERT), + /* C23 : WLAN_PE_RST# */ + PAD_CFG_GPO(GPP_C23, 1, DEEP), + /* E1 : M2_SSD_PEDET */ + PAD_CFG_NF(GPP_E1, NONE, DEEP, NF1), + /* E5 : SATA_DEVSLP1 */ + PAD_CFG_NF(GPP_E5, NONE, PLTRST, NF1), + /* F2 : MEM_CH_SEL */ + PAD_CFG_GPI(GPP_F2, NONE, PLTRST), +}; + +const struct pad_config *variant_early_gpio_table(size_t *num) +{ + *num = ARRAY_SIZE(early_gpio_table); + return early_gpio_table; +} diff --git a/src/mainboard/google/hatch/variants/stryke/include/variant/acpi/dptf.asl b/src/mainboard/google/hatch/variants/stryke/include/variant/acpi/dptf.asl new file mode 100644 index 0000000000..496334daab --- /dev/null +++ b/src/mainboard/google/hatch/variants/stryke/include/variant/acpi/dptf.asl @@ -0,0 +1,14 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include diff --git a/src/mainboard/google/hatch/variants/stryke/include/variant/ec.h b/src/mainboard/google/hatch/variants/stryke/include/variant/ec.h new file mode 100644 index 0000000000..25269627bd --- /dev/null +++ b/src/mainboard/google/hatch/variants/stryke/include/variant/ec.h @@ -0,0 +1,19 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef VARIANT_EC_H +#define VARIANT_EC_H + +#include + +#endif diff --git a/src/mainboard/google/hatch/variants/stryke/include/variant/gpio.h b/src/mainboard/google/hatch/variants/stryke/include/variant/gpio.h new file mode 100644 index 0000000000..132457e5dc --- /dev/null +++ b/src/mainboard/google/hatch/variants/stryke/include/variant/gpio.h @@ -0,0 +1,25 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the + * GNU General Public License for more details. + */ + +#ifndef VARIANT_GPIO_H +#define VARIANT_GPIO_H + +#include + +/* Memory configuration board straps */ +#define GPIO_MEM_CONFIG_0 GPP_H19 +#define GPIO_MEM_CONFIG_1 GPP_H22 +#define GPIO_MEM_CONFIG_2 GPP_F10 +#define GPIO_MEM_CONFIG_3 GPP_F3 + +#endif diff --git a/src/mainboard/google/hatch/variants/stryke/overridetree.cb b/src/mainboard/google/hatch/variants/stryke/overridetree.cb new file mode 100644 index 0000000000..e04a2e7d11 --- /dev/null +++ b/src/mainboard/google/hatch/variants/stryke/overridetree.cb @@ -0,0 +1,215 @@ +chip soc/intel/cannonlake + + register "SerialIoDevMode" = "{ + [PchSerialIoIndexI2C0] = PchSerialIoPci, + [PchSerialIoIndexI2C1] = PchSerialIoPci, + [PchSerialIoIndexI2C2] = PchSerialIoDisabled, + [PchSerialIoIndexI2C3] = PchSerialIoDisabled, + [PchSerialIoIndexI2C4] = PchSerialIoPci, + [PchSerialIoIndexI2C5] = PchSerialIoDisabled, + [PchSerialIoIndexSPI0] = PchSerialIoPci, + [PchSerialIoIndexSPI1] = PchSerialIoDisabled, + [PchSerialIoIndexSPI2] = PchSerialIoDisabled, + [PchSerialIoIndexUART0] = PchSerialIoSkipInit, + [PchSerialIoIndexUART1] = PchSerialIoDisabled, + [PchSerialIoIndexUART2] = PchSerialIoDisabled, + }" + + register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC2)" # Type-C Port 0 + register "usb2_ports[1]" = "USB2_PORT_TYPE_C(OC2)" # Type-C Port 1 + register "usb2_ports[2]" = "USB2_PORT_SHORT(OC3)" # Type-A Port 0 + register "usb2_ports[3]" = "USB2_PORT_EMPTY" + register "usb2_ports[4]" = "USB2_PORT_EMPTY" + register "usb2_ports[5]" = "USB2_PORT_EMPTY" + register "usb2_ports[6]" = "USB2_PORT_LONG(OC_SKIP)" #Front Camera + register "usb2_ports[7]" = "USB2_PORT_EMPTY" + register "usb2_ports[8]" = "USB2_PORT_EMPTY" + register "usb2_ports[9]" = "USB2_PORT_MID(OC_SKIP)" # BT + + register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC2)" # Type-C Port 0 + register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC2)" # Type-C Port 1 + register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC3)" # Type-A Port 0 + register "usb3_ports[3]" = "USB3_PORT_EMPTY" + register "usb3_ports[4]" = "USB3_PORT_EMPTY" + register "usb3_ports[5]" = "USB3_PORT_EMPTY" + + # Intel Common SoC Config + #+-------------------+---------------------------+ + #| Field | Value | + #+-------------------+---------------------------+ + #| GSPI0 | cr50 TPM. Early init is | + #| | required to set up a BAR | + #| | for TPM communication | + #| | before memory is up | + #| GSPI1 | | + #| I2C0 | Touchpad | + #| I2C1 | Touch screen | + #| I2C4 | Audio | + #+-------------------+---------------------------+ + register "common_soc_config" = "{ + .gspi[0] = { + .speed_mhz = 1, + .early_init = 1, + }, + .i2c[0] = { + .speed = I2C_SPEED_FAST, + }, + .i2c[1] = { + .speed = I2C_SPEED_FAST, + }, + .i2c[4] = { + .speed = I2C_SPEED_FAST, + }, + }" + + # GPIO for SD card detect + register "sdcard_cd_gpio" = "vSD3_CD_B" + + device domain 0 on + device pci 14.0 on + chip drivers/usb/acpi + register "desc" = ""Root Hub"" + register "type" = "UPC_TYPE_HUB" + device usb 0.0 on + chip drivers/usb/acpi + register "desc" = ""Left Type-C Port"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "group" = "ACPI_PLD_GROUP(1, 1)" + device usb 2.0 on end + end + chip drivers/usb/acpi + register "desc" = ""Right Type-C Port 1"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "group" = "ACPI_PLD_GROUP(2, 1)" + device usb 2.1 on end + end + chip drivers/usb/acpi + register "desc" = ""Left Type-A Port"" + register "type" = "UPC_TYPE_A" + register "group" = "ACPI_PLD_GROUP(1, 2)" + device usb 2.2 on end + end + chip drivers/usb/acpi + # No Type-A Port 1 + device usb 2.3 off end + end + chip drivers/usb/acpi + # Unused + device usb 2.4 off end + end + chip drivers/usb/acpi + # No WWAN + device usb 2.5 off end + end + chip drivers/usb/acpi + register "desc" = ""Camera"" + register "type" = "UPC_TYPE_INTERNAL" + device usb 2.6 on end + end + chip drivers/usb/acpi + # Unused + device usb 2.7 off end + end + chip drivers/usb/acpi + # Unused + device usb 2.8 off end + end + chip drivers/usb/acpi + register "desc" = ""Bluetooth"" + register "type" = "UPC_TYPE_INTERNAL" + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C14)" + device usb 2.9 on end + end + chip drivers/usb/acpi + register "desc" = ""Left Type-C Port"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "group" = "ACPI_PLD_GROUP(1, 1)" + device usb 3.0 on end + end + chip drivers/usb/acpi + register "desc" = ""Right Type-C Port 1"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "group" = "ACPI_PLD_GROUP(2, 1)" + device usb 3.1 on end + end + chip drivers/usb/acpi + register "desc" = ""Left Type-A Port"" + register "type" = "UPC_TYPE_USB3_A" + register "group" = "ACPI_PLD_GROUP(1, 2)" + device usb 3.2 on end + end + chip drivers/usb/acpi + # No Type-A Port 1 + device usb 3.3 off end + end + chip drivers/usb/acpi + # No WWAN + device usb 3.4 off end + end + chip drivers/usb/acpi + # Unused + device usb 3.5 off end + end + end + end + end # USB xHCI + device pci 15.0 on + chip drivers/i2c/generic + register "hid" = ""ELAN0000"" + register "desc" = ""ELAN Touchpad"" + register "irq" = "ACPI_IRQ_WAKE_EDGE_LOW(GPP_A21_IRQ)" + register "wake" = "GPE0_DW0_21" + register "probed" = "1" + device i2c 15 on end + end + end # I2C #0 + device pci 15.1 on + chip drivers/i2c/generic + register "hid" = ""ELAN0001"" + register "desc" = ""ELAN Touchscreen"" + register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_D16_IRQ)" + register "probed" = "1" + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D15)" + register "reset_delay_ms" = "100" + register "reset_off_delay_ms" = "5" + register "has_power_resource" = "1" + register "stop_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C4)" + register "stop_off_delay_ms" = "5" + device i2c 49 on end + end + chip drivers/i2c/hid + register "generic.hid" = ""GDIX0000"" + register "generic.desc" = ""Goodix Touchscreen"" + register "generic.irq" = "ACPI_IRQ_EDGE_LOW(GPP_D16_IRQ)" + register "generic.probed" = "1" + register "generic.reset_gpio" = + "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D15)" + register "generic.reset_delay_ms" = "120" + register "generic.reset_off_delay_ms" = "3" + register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D9)" + register "generic.enable_delay_ms" = "12" + register "generic.has_power_resource" = "1" + register "hid_desc_reg_offset" = "0x01" + device i2c 5d on end + end + end # I2C #1 + device pci 15.2 off end # I2C #2 + device pci 15.3 off end # I2C #3 + device pci 19.0 on + chip drivers/i2c/generic + register "hid" = ""10EC5682"" + register "name" = ""RT58"" + register "desc" = ""Realtek RT5682"" + register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_BOTH(GPP_H0)" + register "property_count" = "1" + # Set the jd_src to RT5668_JD1 for jack detection + register "property_list[0].type" = "ACPI_DP_TYPE_INTEGER" + register "property_list[0].name" = ""realtek,jd-src"" + register "property_list[0].integer" = "1" + device i2c 1a on end + end + end #I2C #4 + device pci 1e.3 off end # GSPI #1 + end + +end From 5e4c663a5a0fd63164202f98ebcc525f5d8b1d1c Mon Sep 17 00:00:00 2001 From: Patrick Georgi Date: Fri, 29 Nov 2019 12:18:26 +0100 Subject: [PATCH 0523/1242] lib/imd_cbmem: Eliminate unnecessary NULL check MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit &imd_cbmem is never NULL, so remove that path Change-Id: Ib9a9c88d6cd4842df447f046bc0abaa7ef5032c7 Signed-off-by: Patrick Georgi Reviewed-on: https://review.coreboot.org/c/coreboot/+/37361 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki --- src/lib/imd_cbmem.c | 11 +---------- 1 file changed, 1 insertion(+), 10 deletions(-) diff --git a/src/lib/imd_cbmem.c b/src/lib/imd_cbmem.c index d7f7d20f25..4172fa4911 100644 --- a/src/lib/imd_cbmem.c +++ b/src/lib/imd_cbmem.c @@ -69,16 +69,7 @@ static inline const struct imd_entry *cbmem_to_imd(const struct cbmem_entry *e) */ static struct imd *imd_init_backing(struct imd *backing) { - struct imd *imd; - - imd = &imd_cbmem; - - if (imd != NULL) - return imd; - - imd = backing; - - return imd; + return &imd_cbmem; } static struct imd *imd_init_backing_with_recover(struct imd *backing) From 596947ccf78207ebe02fb636adf394b97e6f74ee Mon Sep 17 00:00:00 2001 From: Patrick Georgi Date: Fri, 29 Nov 2019 12:23:35 +0100 Subject: [PATCH 0524/1242] lib/imd_cbmem: Remove the indirections that hide imd_cbmem MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Change-Id: Ie68c6e2ebe56a5902a7665bf62119302146f5928 Signed-off-by: Patrick Georgi Reviewed-on: https://review.coreboot.org/c/coreboot/+/37362 Reviewed-by: Aaron Durbin Reviewed-by: Kyösti Mälkki Tested-by: build bot (Jenkins) --- src/lib/imd_cbmem.c | 73 +++++++-------------------------------------- 1 file changed, 10 insertions(+), 63 deletions(-) diff --git a/src/lib/imd_cbmem.c b/src/lib/imd_cbmem.c index 4172fa4911..c3204e2881 100644 --- a/src/lib/imd_cbmem.c +++ b/src/lib/imd_cbmem.c @@ -55,32 +55,6 @@ static inline const struct imd_entry *cbmem_to_imd(const struct cbmem_entry *e) return (const struct imd_entry *)e; } -/* These are the different situations to handle: - * - * In ramstage cbmem_initialize() attempts a recovery of the - * cbmem region set up by romstage. It uses cbmem_top() as the - * starting point of recovery. - * - * In romstage, similar to ramstage, cbmem_initialize() needs to - * attempt recovery of the cbmem area using cbmem_top() as the limit. - * cbmem_initialize_empty() initializes an empty cbmem area from - * cbmem_top(); - * - */ -static struct imd *imd_init_backing(struct imd *backing) -{ - return &imd_cbmem; -} - -static struct imd *imd_init_backing_with_recover(struct imd *backing) -{ - struct imd *imd; - - imd = imd_init_backing(backing); - - return imd; -} - void cbmem_initialize_empty(void) { cbmem_initialize_empty_id_size(0, 0); @@ -100,13 +74,11 @@ static void cbmem_top_init_once(void) void cbmem_initialize_empty_id_size(u32 id, u64 size) { - struct imd *imd; - struct imd imd_backing; + struct imd *imd = &imd_cbmem; const int no_recovery = 0; cbmem_top_init_once(); - imd = imd_init_backing(&imd_backing); imd_handle_init(imd, cbmem_top()); printk(BIOS_DEBUG, "CBMEM:\n"); @@ -132,13 +104,11 @@ int cbmem_initialize(void) int cbmem_initialize_id_size(u32 id, u64 size) { - struct imd *imd; - struct imd imd_backing; + struct imd *imd = &imd_cbmem; const int recovery = 1; cbmem_top_init_once(); - imd = imd_init_backing(&imd_backing); imd_handle_init(imd, cbmem_top()); if (imd_recover(imd)) @@ -175,12 +145,9 @@ int cbmem_recovery(int is_wakeup) const struct cbmem_entry *cbmem_entry_add(u32 id, u64 size64) { - struct imd *imd; - struct imd imd_backing; + struct imd *imd = &imd_cbmem; const struct imd_entry *e; - imd = imd_init_backing_with_recover(&imd_backing); - e = imd_entry_find_or_add(imd, id, size64); return imd_to_cbmem(e); @@ -188,12 +155,9 @@ const struct cbmem_entry *cbmem_entry_add(u32 id, u64 size64) void *cbmem_add(u32 id, u64 size) { - struct imd *imd; - struct imd imd_backing; + struct imd *imd = &imd_cbmem; const struct imd_entry *e; - imd = imd_init_backing_with_recover(&imd_backing); - e = imd_entry_find_or_add(imd, id, size); if (e == NULL) @@ -205,12 +169,9 @@ void *cbmem_add(u32 id, u64 size) /* Retrieve a region provided a given id. */ const struct cbmem_entry *cbmem_entry_find(u32 id) { - struct imd *imd; - struct imd imd_backing; + struct imd *imd = &imd_cbmem; const struct imd_entry *e; - imd = imd_init_backing_with_recover(&imd_backing); - e = imd_entry_find(imd, id); return imd_to_cbmem(e); @@ -218,12 +179,9 @@ const struct cbmem_entry *cbmem_entry_find(u32 id) void *cbmem_find(u32 id) { - struct imd *imd; - struct imd imd_backing; + struct imd *imd = &imd_cbmem; const struct imd_entry *e; - imd = imd_init_backing_with_recover(&imd_backing); - e = imd_entry_find(imd, id); if (e == NULL) @@ -236,30 +194,21 @@ void *cbmem_find(u32 id) * cannot be removed unless it was the last one added. */ int cbmem_entry_remove(const struct cbmem_entry *entry) { - struct imd *imd; - struct imd imd_backing; - - imd = imd_init_backing_with_recover(&imd_backing); + struct imd *imd = &imd_cbmem; return imd_entry_remove(imd, cbmem_to_imd(entry)); } u64 cbmem_entry_size(const struct cbmem_entry *entry) { - struct imd *imd; - struct imd imd_backing; - - imd = imd_init_backing_with_recover(&imd_backing); + struct imd *imd = &imd_cbmem; return imd_entry_size(imd, cbmem_to_imd(entry)); } void *cbmem_entry_start(const struct cbmem_entry *entry) { - struct imd *imd; - struct imd imd_backing; - - imd = imd_init_backing_with_recover(&imd_backing); + struct imd *imd = &imd_cbmem; return imd_entry_at(imd, cbmem_to_imd(entry)); } @@ -288,10 +237,8 @@ void cbmem_get_region(void **baseptr, size_t *size) void cbmem_list(void) { static const struct imd_lookup lookup[] = { CBMEM_ID_TO_NAME_TABLE }; - struct imd *imd; - struct imd imd_backing; + struct imd *imd = &imd_cbmem; - imd = imd_init_backing_with_recover(&imd_backing); imd_print_entries(imd, lookup, ARRAY_SIZE(lookup)); } #endif From b6161be9de85f4e05d755dfeb2d5b56c63c9f8d8 Mon Sep 17 00:00:00 2001 From: Patrick Georgi Date: Fri, 29 Nov 2019 12:27:01 +0100 Subject: [PATCH 0525/1242] lib/imd_cbmem: Rename imd_cbmem into imd, use directly MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Change-Id: I70e9d9f769831087becbf42dcfb774d8f2638770 Signed-off-by: Patrick Georgi Reviewed-on: https://review.coreboot.org/c/coreboot/+/37363 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki Reviewed-by: Aaron Durbin --- src/lib/imd_cbmem.c | 61 ++++++++++++++++----------------------------- 1 file changed, 22 insertions(+), 39 deletions(-) diff --git a/src/lib/imd_cbmem.c b/src/lib/imd_cbmem.c index c3204e2881..5be7dc46f5 100644 --- a/src/lib/imd_cbmem.c +++ b/src/lib/imd_cbmem.c @@ -27,6 +27,8 @@ has to fill in the _cbmem_top_ptr symbol based on the calling arguments. */ uintptr_t _cbmem_top_ptr; +static struct imd imd; + void *cbmem_top(void) { if (ENV_ROMSTAGE) { @@ -42,9 +44,6 @@ void *cbmem_top(void) dead_code(); } - -static struct imd imd_cbmem; - static inline const struct cbmem_entry *imd_to_cbmem(const struct imd_entry *e) { return (const struct cbmem_entry *)e; @@ -74,16 +73,15 @@ static void cbmem_top_init_once(void) void cbmem_initialize_empty_id_size(u32 id, u64 size) { - struct imd *imd = &imd_cbmem; const int no_recovery = 0; cbmem_top_init_once(); - imd_handle_init(imd, cbmem_top()); + imd_handle_init(&imd, cbmem_top()); printk(BIOS_DEBUG, "CBMEM:\n"); - if (imd_create_tiered_empty(imd, CBMEM_ROOT_MIN_SIZE, CBMEM_LG_ALIGN, + if (imd_create_tiered_empty(&imd, CBMEM_ROOT_MIN_SIZE, CBMEM_LG_ALIGN, CBMEM_SM_ROOT_SIZE, CBMEM_SM_ALIGN)) { printk(BIOS_DEBUG, "failed.\n"); return; @@ -104,14 +102,13 @@ int cbmem_initialize(void) int cbmem_initialize_id_size(u32 id, u64 size) { - struct imd *imd = &imd_cbmem; const int recovery = 1; cbmem_top_init_once(); - imd_handle_init(imd, cbmem_top()); + imd_handle_init(&imd, cbmem_top()); - if (imd_recover(imd)) + if (imd_recover(&imd)) return 1; /* @@ -120,7 +117,7 @@ int cbmem_initialize_id_size(u32 id, u64 size) * is being taken. */ if (ENV_ROMSTAGE) - imd_lockdown(imd); + imd_lockdown(&imd); /* Add the specified range first */ if (size) @@ -145,72 +142,62 @@ int cbmem_recovery(int is_wakeup) const struct cbmem_entry *cbmem_entry_add(u32 id, u64 size64) { - struct imd *imd = &imd_cbmem; const struct imd_entry *e; - e = imd_entry_find_or_add(imd, id, size64); + e = imd_entry_find_or_add(&imd, id, size64); return imd_to_cbmem(e); } void *cbmem_add(u32 id, u64 size) { - struct imd *imd = &imd_cbmem; const struct imd_entry *e; - e = imd_entry_find_or_add(imd, id, size); + e = imd_entry_find_or_add(&imd, id, size); if (e == NULL) return NULL; - return imd_entry_at(imd, e); + return imd_entry_at(&imd, e); } /* Retrieve a region provided a given id. */ const struct cbmem_entry *cbmem_entry_find(u32 id) { - struct imd *imd = &imd_cbmem; const struct imd_entry *e; - e = imd_entry_find(imd, id); + e = imd_entry_find(&imd, id); return imd_to_cbmem(e); } void *cbmem_find(u32 id) { - struct imd *imd = &imd_cbmem; const struct imd_entry *e; - e = imd_entry_find(imd, id); + e = imd_entry_find(&imd, id); if (e == NULL) return NULL; - return imd_entry_at(imd, e); + return imd_entry_at(&imd, e); } /* Remove a reserved region. Returns 0 on success, < 0 on error. Note: A region * cannot be removed unless it was the last one added. */ int cbmem_entry_remove(const struct cbmem_entry *entry) { - struct imd *imd = &imd_cbmem; - - return imd_entry_remove(imd, cbmem_to_imd(entry)); + return imd_entry_remove(&imd, cbmem_to_imd(entry)); } u64 cbmem_entry_size(const struct cbmem_entry *entry) { - struct imd *imd = &imd_cbmem; - - return imd_entry_size(imd, cbmem_to_imd(entry)); + return imd_entry_size(&imd, cbmem_to_imd(entry)); } void *cbmem_entry_start(const struct cbmem_entry *entry) { - struct imd *imd = &imd_cbmem; - - return imd_entry_at(imd, cbmem_to_imd(entry)); + return imd_entry_at(&imd, cbmem_to_imd(entry)); } void cbmem_add_bootmem(void) @@ -224,7 +211,7 @@ void cbmem_add_bootmem(void) void cbmem_get_region(void **baseptr, size_t *size) { - imd_region_used(&imd_cbmem, baseptr, size); + imd_region_used(&imd, baseptr, size); } #if ENV_PAYLOAD_LOADER || (CONFIG(EARLY_CBMEM_LIST) \ @@ -237,20 +224,16 @@ void cbmem_get_region(void **baseptr, size_t *size) void cbmem_list(void) { static const struct imd_lookup lookup[] = { CBMEM_ID_TO_NAME_TABLE }; - struct imd *imd = &imd_cbmem; - imd_print_entries(imd, lookup, ARRAY_SIZE(lookup)); + imd_print_entries(&imd, lookup, ARRAY_SIZE(lookup)); } #endif void cbmem_add_records_to_cbtable(struct lb_header *header) { struct imd_cursor cursor; - struct imd *imd; - imd = &imd_cbmem; - - if (imd_cursor_init(imd, &cursor)) + if (imd_cursor_init(&imd, &cursor)) return; while (1) { @@ -263,7 +246,7 @@ void cbmem_add_records_to_cbtable(struct lb_header *header) if (e == NULL) break; - id = imd_entry_id(imd, e); + id = imd_entry_id(&imd, e); /* Don't add these metadata entries. */ if (id == CBMEM_ID_IMD_ROOT || id == CBMEM_ID_IMD_SMALL) continue; @@ -271,8 +254,8 @@ void cbmem_add_records_to_cbtable(struct lb_header *header) lbe = (struct lb_cbmem_entry *)lb_new_record(header); lbe->tag = LB_TAG_CBMEM_ENTRY; lbe->size = sizeof(*lbe); - lbe->address = (uintptr_t)imd_entry_at(imd, e); - lbe->entry_size = imd_entry_size(imd, e); + lbe->address = (uintptr_t)imd_entry_at(&imd, e); + lbe->entry_size = imd_entry_size(&imd, e); lbe->id = id; } } From c08fdf3decc6a61a9020a7df484d92473f7223e9 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ky=C3=B6sti=20M=C3=A4lkki?= Date: Tue, 3 Dec 2019 08:04:31 +0200 Subject: [PATCH 0526/1242] binaryPI: Fix failing AP startup MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Fix regression with commit 5639736 binaryPI: Drop CAR teardown without POSTCAR_STAGE Occassionally (maybe 1 boot in 10) SMP lapic_cpu_init() fails with following errors in the logs of pcengines/apu2: CPU 0x03 would not start! CPU 0x03 did not initialize! The CPU number is sometimes 0x02, never seen 0x01. Work-around also suggests something to do with cache coherency and MTRRs that is really at fault. As a work-around return the BSP CAR teardown to use wbinvd instead of invd. These platforms do not support S3 resume so this is the easy work-around for the time being. Change-Id: I3dac8785aaf4af5c7c105ec9dd0b95156b7cca21 Signed-off-by: Kyösti Mälkki Reviewed-on: https://review.coreboot.org/c/coreboot/+/37438 Tested-by: build bot (Jenkins) Reviewed-by: Michał Żygowski Reviewed-by: Arthur Heymans Reviewed-by: Angel Pons --- src/vendorcode/amd/pi/00630F01/binaryPI/gcccar.inc | 3 ++- src/vendorcode/amd/pi/00660F01/binaryPI/gcccar.inc | 3 ++- src/vendorcode/amd/pi/00730F01/binaryPI/gcccar.inc | 3 ++- 3 files changed, 6 insertions(+), 3 deletions(-) diff --git a/src/vendorcode/amd/pi/00630F01/binaryPI/gcccar.inc b/src/vendorcode/amd/pi/00630F01/binaryPI/gcccar.inc index 4d903e686f..cecf5ca230 100644 --- a/src/vendorcode/amd/pi/00630F01/binaryPI/gcccar.inc +++ b/src/vendorcode/amd/pi/00630F01/binaryPI/gcccar.inc @@ -904,7 +904,8 @@ fam15_disable_stack_remote_read_exit: btr $INVD_WBINVD, %eax # Disable INVD -> WBINVD conversion _WRMSR - invd + # An invd here sometimes breaks AP CPU startup ? + wbinvd #.if (bh == 01h) || (bh == 03h) ; Is this TN or KV? cmp $01, %bh diff --git a/src/vendorcode/amd/pi/00660F01/binaryPI/gcccar.inc b/src/vendorcode/amd/pi/00660F01/binaryPI/gcccar.inc index b208cc14ca..88e1a7d1be 100644 --- a/src/vendorcode/amd/pi/00660F01/binaryPI/gcccar.inc +++ b/src/vendorcode/amd/pi/00660F01/binaryPI/gcccar.inc @@ -639,7 +639,8 @@ fam15_disable_stack_remote_read_exit: btr $INVD_WBINVD, %eax # Disable INVD -> WBINVD conversion _WRMSR - invd + # An invd here sometimes breaks AP CPU startup ? + wbinvd # #.if (bh == 01h) || (bh == 03h) ; Is this TN or KM? # cmp $01, %bh diff --git a/src/vendorcode/amd/pi/00730F01/binaryPI/gcccar.inc b/src/vendorcode/amd/pi/00730F01/binaryPI/gcccar.inc index 7d86a31c69..c246b99395 100644 --- a/src/vendorcode/amd/pi/00730F01/binaryPI/gcccar.inc +++ b/src/vendorcode/amd/pi/00730F01/binaryPI/gcccar.inc @@ -603,7 +603,8 @@ fam16_disable_stack_remote_read_exit: btr $INVD_WBINVD, %eax # Disable INVD -> WBINVD conversion _WRMSR - invd + # An invd here sometimes breaks AP CPU startup + wbinvd #Do Standard Family 16 work mov $HWCR, %ecx # MSR:C001_0015h From 73a544d4533fa8305f1c0a809137b5e2151ea17e Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Micha=C5=82=20=C5=BBygowski?= Date: Sun, 24 Nov 2019 14:16:34 +0100 Subject: [PATCH 0527/1242] soc/amd/common/block/acpimmio: fix ACPIMMIO decode enable function MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit According to BKDGs for families 15h 60-6fh or newer and families 16h the ACPI MMIO decode enable bit is the second LSB, not the first LSB. Additionally create another enable function for older families where the register and bit is different. It does not seem to impact any current board, but may be crucial for incoming C bootblock implementations when this bit will need to be set very early. Most likely this bit is set by AGESA right now. Signed-off-by: Michał Żygowski Change-Id: Iaa31abc3dbdf77d8513fa83c7415b9a1b7fd266f Reviewed-on: https://review.coreboot.org/c/coreboot/+/37178 Reviewed-by: Angel Pons Reviewed-by: Kyösti Mälkki Tested-by: build bot (Jenkins) --- src/soc/amd/common/block/acpimmio/mmio_util.c | 17 +++++++++++++---- .../common/block/include/amdblocks/acpimmio.h | 7 ++++++- .../block/include/amdblocks/acpimmio_map.h | 19 ++++++++++++------- src/soc/amd/picasso/southbridge.c | 2 +- src/soc/amd/stoneyridge/southbridge.c | 2 +- 5 files changed, 33 insertions(+), 14 deletions(-) diff --git a/src/soc/amd/common/block/acpimmio/mmio_util.c b/src/soc/amd/common/block/acpimmio/mmio_util.c index 04d5e4af4d..a589ef549a 100644 --- a/src/soc/amd/common/block/acpimmio/mmio_util.c +++ b/src/soc/amd/common/block/acpimmio/mmio_util.c @@ -18,13 +18,22 @@ #include #include -void enable_acpimmio_decode(void) +void enable_acpimmio_decode_pm24(void) { uint32_t dw; - dw = pm_io_read32(ACPIMMIO_DECODE_REGISTER); - dw |= ACPIMMIO_DECODE_EN; - pm_io_write32(ACPIMMIO_DECODE_REGISTER, dw); + dw = pm_io_read32(ACPIMMIO_DECODE_REGISTER_24); + dw |= PM_24_ACPIMMIO_DECODE_EN; + pm_io_write32(ACPIMMIO_DECODE_REGISTER_24, dw); +} + +void enable_acpimmio_decode_pm04(void) +{ + uint32_t dw; + + dw = pm_io_read32(ACPIMMIO_DECODE_REGISTER_04); + dw |= PM_04_ACPIMMIO_DECODE_EN; + pm_io_write32(ACPIMMIO_DECODE_REGISTER_04, dw); } /* PM registers are accessed a byte at a time via CD6/CD7 */ diff --git a/src/soc/amd/common/block/include/amdblocks/acpimmio.h b/src/soc/amd/common/block/include/amdblocks/acpimmio.h index 57d24db5b2..c441ab8f63 100644 --- a/src/soc/amd/common/block/include/amdblocks/acpimmio.h +++ b/src/soc/amd/common/block/include/amdblocks/acpimmio.h @@ -101,7 +101,12 @@ */ /* Enable the AcpiMmio range at 0xfed80000 */ -void enable_acpimmio_decode(void); + +/* For older discrete FCHs */ +void enable_acpimmio_decode_pm24(void); + +/* For newer integrated FCHs */ +void enable_acpimmio_decode_pm04(void); /* Access PM registers using IO cycles */ uint8_t pm_io_read8(uint8_t reg); diff --git a/src/soc/amd/common/block/include/amdblocks/acpimmio_map.h b/src/soc/amd/common/block/include/amdblocks/acpimmio_map.h index 755af52d4f..9a1584004b 100644 --- a/src/soc/amd/common/block/include/amdblocks/acpimmio_map.h +++ b/src/soc/amd/common/block/include/amdblocks/acpimmio_map.h @@ -22,16 +22,21 @@ #define PM_INDEX 0xcd6 #define PM_DATA 0xcd7 -/* TODO: In the event this is ported backward far enough, earlier devices - * enable the decode in PMx24 instead. All discrete FCHs and the Kabini - * SoC fall into this category. Kabini's successor, Mullins, uses this - * newer method. +/* Earlier devices enable the decode in PMx24 instead. All discrete FCHs and + * the Kabini SoC fall into this category. Kabini's successor, Mullins, uses + * this newer method. */ -#define ACPIMMIO_DECODE_REGISTER 0x4 -#define ACPIMMIO_DECODE_EN BIT(0) + +#define ACPIMMIO_DECODE_REGISTER_24 0x24 +#define PM_24_ACPIMMIO_DECODE_EN BIT(0) + +#define ACPIMMIO_DECODE_REGISTER_04 0x4 +#define PM_04_BIOSRAM_DECODE_EN BIT(0) +#define PM_04_ACPIMMIO_DECODE_EN BIT(1) + /* MMIO register blocks are at fixed offsets from 0xfed80000 and are enabled - * in PMx24[1] (older implementations) and PMx04[1] (newer implementations). + * in PMx24[0] (older implementations) and PMx04[1] (newer implementations). * PM registers are also accessible via IO CD6/CD7. * * All products do not support all blocks below, however AMD has avoided diff --git a/src/soc/amd/picasso/southbridge.c b/src/soc/amd/picasso/southbridge.c index fe801d4126..041d262af7 100644 --- a/src/soc/amd/picasso/southbridge.c +++ b/src/soc/amd/picasso/southbridge.c @@ -278,7 +278,7 @@ void fch_pre_init(void) sb_disable_4dw_burst(); sb_set_spi100(SPI_SPEED_33M, SPI_SPEED_33M, SPI_SPEED_16M, SPI_SPEED_16M); - enable_acpimmio_decode(); + enable_acpimmio_decode_pm04(); fch_smbus_init(); sb_enable_cf9_io(); sb_enable_legacy_io(); diff --git a/src/soc/amd/stoneyridge/southbridge.c b/src/soc/amd/stoneyridge/southbridge.c index 8556790772..85c7eafcf1 100644 --- a/src/soc/amd/stoneyridge/southbridge.c +++ b/src/soc/amd/stoneyridge/southbridge.c @@ -399,7 +399,7 @@ void bootblock_fch_early_init(void) lpc_enable_spi_prefetch(); sb_init_spi_base(); sb_disable_4dw_burst(); /* Must be disabled on CZ(ST) */ - enable_acpimmio_decode(); + enable_acpimmio_decode_pm04(); fch_smbus_init(); sb_enable_cf9_io(); setup_spread_spectrum(&reboot); From f65c1e40885377a07794fc59f38fce1c9230854f Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Micha=C5=82=20=C5=BBygowski?= Date: Sun, 1 Dec 2019 18:14:39 +0100 Subject: [PATCH 0528/1242] amdblocks/acpimmio: Unify BIOSRAM usage MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit All AMD CPU families supported in coreboot have BIOSRAM space. Looking at the source code, every family could have the same API to save and restore cbmem top or UMA base and size. Unify BIOSRAM layout and add implementation for cbmem top and UMA storing. Also replace the existing implementation of cbmem top and UMA with the BIOSRAM access. TEST=boot PC Engines apu1 and apu2 Signed-off-by: Michał Żygowski Change-Id: I69a03e4f01d7fb2ffc9f8b5af73d7e4e7ec027da Reviewed-on: https://review.coreboot.org/c/coreboot/+/37402 Reviewed-by: Richard Spiegel Reviewed-by: Angel Pons Reviewed-by: Kyösti Mälkki Tested-by: build bot (Jenkins) --- src/northbridge/amd/pi/Makefile.inc | 3 -- .../amd/common/block/acpimmio/Makefile.inc | 7 ++++ .../amd/common/block/acpimmio/biosram.c} | 39 +++++++++++++------ .../common/block/include/amdblocks/biosram.h | 33 ++++++++++++++++ src/soc/amd/common/block/pi/agesawrapper.c | 2 +- src/soc/amd/picasso/include/soc/southbridge.h | 32 --------------- src/soc/amd/picasso/memmap.c | 10 ----- src/soc/amd/picasso/northbridge.c | 2 +- src/soc/amd/picasso/southbridge.c | 24 ------------ .../amd/stoneyridge/include/soc/southbridge.h | 33 +--------------- src/soc/amd/stoneyridge/memmap.c | 10 ----- src/soc/amd/stoneyridge/northbridge.c | 2 +- src/soc/amd/stoneyridge/southbridge.c | 24 ------------ src/southbridge/amd/agesa/hudson/ramtop.c | 25 ------------ src/southbridge/amd/cimx/sb800/ramtop.c | 24 ------------ 15 files changed, 72 insertions(+), 198 deletions(-) rename src/{northbridge/amd/pi/ramtop.c => soc/amd/common/block/acpimmio/biosram.c} (50%) create mode 100644 src/soc/amd/common/block/include/amdblocks/biosram.h diff --git a/src/northbridge/amd/pi/Makefile.inc b/src/northbridge/amd/pi/Makefile.inc index ffafc6038f..61917c9d48 100644 --- a/src/northbridge/amd/pi/Makefile.inc +++ b/src/northbridge/amd/pi/Makefile.inc @@ -19,7 +19,4 @@ subdirs-$(CONFIG_NORTHBRIDGE_AMD_PI_00630F01) += 00630F01 subdirs-$(CONFIG_NORTHBRIDGE_AMD_PI_00730F01) += 00730F01 subdirs-$(CONFIG_NORTHBRIDGE_AMD_PI_00660F01) += 00660F01 -romstage-y += ramtop.c -postcar-y += ramtop.c -ramstage-y += ramtop.c endif diff --git a/src/soc/amd/common/block/acpimmio/Makefile.inc b/src/soc/amd/common/block/acpimmio/Makefile.inc index 9517b10b8a..69253b9203 100644 --- a/src/soc/amd/common/block/acpimmio/Makefile.inc +++ b/src/soc/amd/common/block/acpimmio/Makefile.inc @@ -4,3 +4,10 @@ romstage-$(CONFIG_SOC_AMD_COMMON_BLOCK_ACPIMMIO) += mmio_util.c postcar-$(CONFIG_SOC_AMD_COMMON_BLOCK_ACPIMMIO) += mmio_util.c ramstage-$(CONFIG_SOC_AMD_COMMON_BLOCK_ACPIMMIO) += mmio_util.c smm-$(CONFIG_SOC_AMD_COMMON_BLOCK_ACPIMMIO) += mmio_util.c + +bootblock-$(CONFIG_SOC_AMD_COMMON_BLOCK_ACPIMMIO) += biosram.c +verstage-$(CONFIG_SOC_AMD_COMMON_BLOCK_ACPIMMIO) += biosram.c +romstage-$(CONFIG_SOC_AMD_COMMON_BLOCK_ACPIMMIO) += biosram.c +postcar-$(CONFIG_SOC_AMD_COMMON_BLOCK_ACPIMMIO) += biosram.c +ramstage-$(CONFIG_SOC_AMD_COMMON_BLOCK_ACPIMMIO) += biosram.c +smm-$(CONFIG_SOC_AMD_COMMON_BLOCK_ACPIMMIO) += biosram.c diff --git a/src/northbridge/amd/pi/ramtop.c b/src/soc/amd/common/block/acpimmio/biosram.c similarity index 50% rename from src/northbridge/amd/pi/ramtop.c rename to src/soc/amd/common/block/acpimmio/biosram.c index 823a15c079..f0a1257fb9 100644 --- a/src/northbridge/amd/pi/ramtop.c +++ b/src/soc/amd/common/block/acpimmio/biosram.c @@ -11,23 +11,40 @@ * GNU General Public License for more details. */ -#define __SIMPLE_DEVICE__ - -#include -#include #include - -#define CBMEM_TOP_SCRATCHPAD 0x78 +#include +#include void backup_top_of_low_cacheable(uintptr_t ramtop) { - uint16_t top_cache = ramtop >> 16; - pci_write_config16(PCI_DEV(0,0,0), CBMEM_TOP_SCRATCHPAD, top_cache); + biosram_write32(BIOSRAM_CBMEM_TOP, ramtop); } uintptr_t restore_top_of_low_cacheable(void) { - uint16_t top_cache; - top_cache = pci_read_config16(PCI_DEV(0,0,0), CBMEM_TOP_SCRATCHPAD); - return (top_cache << 16); + return biosram_read32(BIOSRAM_CBMEM_TOP); +} + +void save_uma_size(uint32_t size) +{ + biosram_write32(BIOSRAM_UMA_SIZE, size); +} + +void save_uma_base(uint64_t base) +{ + biosram_write32(BIOSRAM_UMA_BASE, (uint32_t) base); + biosram_write32(BIOSRAM_UMA_BASE + 4, (uint32_t) (base >> 32)); +} + +uint32_t get_uma_size(void) +{ + return biosram_read32(BIOSRAM_UMA_SIZE); +} + +uint64_t get_uma_base(void) +{ + uint64_t base; + base = biosram_read32(BIOSRAM_UMA_BASE); + base |= ((uint64_t)(biosram_read32(BIOSRAM_UMA_BASE + 4)) << 32); + return base; } diff --git a/src/soc/amd/common/block/include/amdblocks/biosram.h b/src/soc/amd/common/block/include/amdblocks/biosram.h new file mode 100644 index 0000000000..e2c1eb33f7 --- /dev/null +++ b/src/soc/amd/common/block/include/amdblocks/biosram.h @@ -0,0 +1,33 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __AMDBLOCKS_BIOSRAM_H__ +#define __AMDBLOCKS_BIOSRAM_H__ + +#include + +/* BiosRam Ranges at 0xfed80500 or I/O 0xcd4/0xcd5 */ +#define BIOSRAM_CBMEM_TOP 0xf0 /* 4 bytes */ +#define BIOSRAM_UMA_SIZE 0xf4 /* 4 bytes */ +#define BIOSRAM_UMA_BASE 0xf8 /* 8 bytes */ + +/* Saves the UMA size returned by AGESA */ +void save_uma_size(uint32_t size); +/* Saves the UMA base address returned by AGESA */ +void save_uma_base(uint64_t base); +/* Returns the saved UMA size */ +uint32_t get_uma_size(void); +/* Returns the saved UMA base */ +uint64_t get_uma_base(void); + +#endif diff --git a/src/soc/amd/common/block/pi/agesawrapper.c b/src/soc/amd/common/block/pi/agesawrapper.c index c5464df834..45842168de 100644 --- a/src/soc/amd/common/block/pi/agesawrapper.c +++ b/src/soc/amd/common/block/pi/agesawrapper.c @@ -18,11 +18,11 @@ #include #include #include +#include #include #include #include #include -#include #include #include diff --git a/src/soc/amd/picasso/include/soc/southbridge.h b/src/soc/amd/picasso/include/soc/southbridge.h index 0fb187dc52..cbf95b9b16 100644 --- a/src/soc/amd/picasso/include/soc/southbridge.h +++ b/src/soc/amd/picasso/include/soc/southbridge.h @@ -335,38 +335,6 @@ void sb_set_spi100(u16 norm, u16 fast, u16 alt, u16 tpm); void fch_pre_init(void); void fch_early_init(void); void set_uart_config(int idx); -/** - * @brief Save the UMA bize - * - * @param size = in bytes - * - * @return none - */ -void save_uma_size(uint32_t size); -/** - * @brief Save the UMA base address - * - * @param base = 64bit base address - * - * @return none - */ -void save_uma_base(uint64_t base); -/** - * @brief Get the saved UMA size - * - * @param none - * - * @return size in bytes - */ -uint32_t get_uma_size(void); -/** - * @brief Get the saved UMA base - * - * @param none - * - * @return 64bit base address - */ -uint64_t get_uma_base(void); /* Initialize all the i2c buses that are marked with early init. */ void i2c_soc_early_init(void); diff --git a/src/soc/amd/picasso/memmap.c b/src/soc/amd/picasso/memmap.c index 82d6fb6e8e..ae5a331259 100644 --- a/src/soc/amd/picasso/memmap.c +++ b/src/soc/amd/picasso/memmap.c @@ -28,16 +28,6 @@ #include #include -void backup_top_of_low_cacheable(uintptr_t ramtop) -{ - biosram_write32(BIOSRAM_CBMEM_TOP, ramtop); -} - -uintptr_t restore_top_of_low_cacheable(void) -{ - return biosram_read32(BIOSRAM_CBMEM_TOP); -} - #if CONFIG(ACPI_BERT) #if CONFIG_SMM_TSEG_SIZE == 0x0 #define BERT_REGION_MAX_SIZE 0x100000 diff --git a/src/soc/amd/picasso/northbridge.c b/src/soc/amd/picasso/northbridge.c index 08807f3321..4a1493cba3 100644 --- a/src/soc/amd/picasso/northbridge.c +++ b/src/soc/amd/picasso/northbridge.c @@ -13,6 +13,7 @@ * GNU General Public License for more details. */ +#include #include #include #include @@ -29,7 +30,6 @@ #include #include #include -#include #include #include #include diff --git a/src/soc/amd/picasso/southbridge.c b/src/soc/amd/picasso/southbridge.c index 041d262af7..0dff4bcae3 100644 --- a/src/soc/amd/picasso/southbridge.c +++ b/src/soc/amd/picasso/southbridge.c @@ -501,27 +501,3 @@ static void set_pci_irqs(void *unused) * on entry into BS_DEV_ENABLE. */ BOOT_STATE_INIT_ENTRY(BS_DEV_ENABLE, BS_ON_ENTRY, set_pci_irqs, NULL); - -void save_uma_size(uint32_t size) -{ - biosram_write32(BIOSRAM_UMA_SIZE, size); -} - -void save_uma_base(uint64_t base) -{ - biosram_write32(BIOSRAM_UMA_BASE, (uint32_t) base); - biosram_write32(BIOSRAM_UMA_BASE + 4, (uint32_t) (base >> 32)); -} - -uint32_t get_uma_size(void) -{ - return biosram_read32(BIOSRAM_UMA_SIZE); -} - -uint64_t get_uma_base(void) -{ - uint64_t base; - base = biosram_read32(BIOSRAM_UMA_BASE); - base |= ((uint64_t)(biosram_read32(BIOSRAM_UMA_BASE + 4)) << 32); - return base; -} diff --git a/src/soc/amd/stoneyridge/include/soc/southbridge.h b/src/soc/amd/stoneyridge/include/soc/southbridge.h index dd514ab88f..0555afbba8 100644 --- a/src/soc/amd/stoneyridge/include/soc/southbridge.h +++ b/src/soc/amd/stoneyridge/include/soc/southbridge.h @@ -350,38 +350,7 @@ void sb_read_mode(u32 mode); void sb_set_spi100(u16 norm, u16 fast, u16 alt, u16 tpm); void bootblock_fch_early_init(void); void bootblock_fch_init(void); -/** - * @brief Save the UMA bize returned by AGESA - * - * @param size = in bytes - * - * @return none - */ -void save_uma_size(uint32_t size); -/** - * @brief Save the UMA base address returned by AGESA - * - * @param base = 64bit base address - * - * @return none - */ -void save_uma_base(uint64_t base); -/** - * @brief Get the saved UMA size - * - * @param none - * - * @return size in bytes - */ -uint32_t get_uma_size(void); -/** - * @brief Get the saved UMA base - * - * @param none - * - * @return 64bit base address - */ -uint64_t get_uma_base(void); + /* * Call the mainboard to get the USB Over Current Map. The mainboard * returns the map and 0 on Success or -1 on error or no map. There is diff --git a/src/soc/amd/stoneyridge/memmap.c b/src/soc/amd/stoneyridge/memmap.c index 82d6fb6e8e..ae5a331259 100644 --- a/src/soc/amd/stoneyridge/memmap.c +++ b/src/soc/amd/stoneyridge/memmap.c @@ -28,16 +28,6 @@ #include #include -void backup_top_of_low_cacheable(uintptr_t ramtop) -{ - biosram_write32(BIOSRAM_CBMEM_TOP, ramtop); -} - -uintptr_t restore_top_of_low_cacheable(void) -{ - return biosram_read32(BIOSRAM_CBMEM_TOP); -} - #if CONFIG(ACPI_BERT) #if CONFIG_SMM_TSEG_SIZE == 0x0 #define BERT_REGION_MAX_SIZE 0x100000 diff --git a/src/soc/amd/stoneyridge/northbridge.c b/src/soc/amd/stoneyridge/northbridge.c index 044a1b05ca..c98d0a9517 100644 --- a/src/soc/amd/stoneyridge/northbridge.c +++ b/src/soc/amd/stoneyridge/northbridge.c @@ -13,6 +13,7 @@ * GNU General Public License for more details. */ +#include #include #include #include @@ -32,7 +33,6 @@ #include #include #include -#include #include #include #include diff --git a/src/soc/amd/stoneyridge/southbridge.c b/src/soc/amd/stoneyridge/southbridge.c index 85c7eafcf1..1b2afec3f1 100644 --- a/src/soc/amd/stoneyridge/southbridge.c +++ b/src/soc/amd/stoneyridge/southbridge.c @@ -648,27 +648,3 @@ static void set_pci_irqs(void *unused) * on entry into BS_DEV_ENABLE. */ BOOT_STATE_INIT_ENTRY(BS_DEV_ENABLE, BS_ON_ENTRY, set_pci_irqs, NULL); - -void save_uma_size(uint32_t size) -{ - biosram_write32(BIOSRAM_UMA_SIZE, size); -} - -void save_uma_base(uint64_t base) -{ - biosram_write32(BIOSRAM_UMA_BASE, (uint32_t) base); - biosram_write32(BIOSRAM_UMA_BASE + 4, (uint32_t) (base >> 32)); -} - -uint32_t get_uma_size(void) -{ - return biosram_read32(BIOSRAM_UMA_SIZE); -} - -uint64_t get_uma_base(void) -{ - uint64_t base; - base = biosram_read32(BIOSRAM_UMA_BASE); - base |= ((uint64_t)(biosram_read32(BIOSRAM_UMA_BASE + 4)) << 32); - return base; -} diff --git a/src/southbridge/amd/agesa/hudson/ramtop.c b/src/southbridge/amd/agesa/hudson/ramtop.c index 22b291d1bb..2af95df034 100644 --- a/src/southbridge/amd/agesa/hudson/ramtop.c +++ b/src/southbridge/amd/agesa/hudson/ramtop.c @@ -16,7 +16,6 @@ #include #include #include -#include #include "hudson.h" int acpi_get_sleep_type(void) @@ -25,27 +24,3 @@ int acpi_get_sleep_type(void) tmp = ((tmp & (7 << 10)) >> 10); return (int)tmp; } - -void backup_top_of_low_cacheable(uintptr_t ramtop) -{ - u32 dword = ramtop; - int nvram_pos = 0xf8, i; /* temp */ - for (i = 0; i < 4; i++) { - outb(nvram_pos, BIOSRAM_INDEX); - outb((dword >> (8 * i)) & 0xff, BIOSRAM_DATA); - nvram_pos++; - } -} - -uintptr_t restore_top_of_low_cacheable(void) -{ - uint32_t xdata = 0; - int xnvram_pos = 0xf8, xi; - for (xi = 0; xi < 4; xi++) { - outb(xnvram_pos, BIOSRAM_INDEX); - xdata &= ~(0xff << (xi * 8)); - xdata |= inb(BIOSRAM_DATA) << (xi *8); - xnvram_pos++; - } - return xdata; -} diff --git a/src/southbridge/amd/cimx/sb800/ramtop.c b/src/southbridge/amd/cimx/sb800/ramtop.c index b9fc00df06..98d12c7101 100644 --- a/src/southbridge/amd/cimx/sb800/ramtop.c +++ b/src/southbridge/amd/cimx/sb800/ramtop.c @@ -25,27 +25,3 @@ int acpi_get_sleep_type(void) tmp = ((tmp & (7 << 10)) >> 10); return (int)tmp; } - -void backup_top_of_low_cacheable(uintptr_t ramtop) -{ - u32 dword = ramtop; - int nvram_pos = 0xf8, i; /* temp */ - for (i = 0; i < 4; i++) { - outb(nvram_pos, BIOSRAM_INDEX); - outb((dword >> (8 * i)) & 0xff, BIOSRAM_DATA); - nvram_pos++; - } -} - -uintptr_t restore_top_of_low_cacheable(void) -{ - u32 xdata = 0; - int xnvram_pos = 0xf8, xi; - for (xi = 0; xi < 4; xi++) { - outb(xnvram_pos, BIOSRAM_INDEX); - xdata &= ~(0xff << (xi * 8)); - xdata |= inb(BIOSRAM_DATA) << (xi * 8); - xnvram_pos++; - } - return xdata; -} From 5a6620277d6232a0d222047cbd7db414fb8585bc Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Micha=C5=82=20=C5=BBygowski?= Date: Mon, 2 Dec 2019 17:02:00 +0100 Subject: [PATCH 0529/1242] amdblocks/acpimmio: add common functions for AP entry MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Move the stoneyridge implementation of get/set AP entry to the common block. Signed-off-by: Michał Żygowski Change-Id: I9c73940ffe5f735dcd844911361355c384f617b1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/37416 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki Reviewed-by: Angel Pons Reviewed-by: Richard Spiegel --- src/soc/amd/common/block/acpimmio/biosram.c | 11 +++++ .../common/block/include/amdblocks/biosram.h | 5 +++ src/soc/amd/stoneyridge/Makefile.inc | 6 --- src/soc/amd/stoneyridge/bootblock/bootblock.c | 2 +- .../amd/stoneyridge/include/soc/northbridge.h | 6 --- src/soc/amd/stoneyridge/nb_util.c | 40 ------------------- src/soc/amd/stoneyridge/romstage.c | 1 + 7 files changed, 18 insertions(+), 53 deletions(-) delete mode 100644 src/soc/amd/stoneyridge/nb_util.c diff --git a/src/soc/amd/common/block/acpimmio/biosram.c b/src/soc/amd/common/block/acpimmio/biosram.c index f0a1257fb9..e33f02d02c 100644 --- a/src/soc/amd/common/block/acpimmio/biosram.c +++ b/src/soc/amd/common/block/acpimmio/biosram.c @@ -15,6 +15,17 @@ #include #include +void *get_ap_entry_ptr(void) +{ + return (void *)biosram_read32(BIOSRAM_AP_ENTRY); +} + +void set_ap_entry_ptr(void *entry) +{ + biosram_write32(BIOSRAM_AP_ENTRY, (uintptr_t)entry); +} + + void backup_top_of_low_cacheable(uintptr_t ramtop) { biosram_write32(BIOSRAM_CBMEM_TOP, ramtop); diff --git a/src/soc/amd/common/block/include/amdblocks/biosram.h b/src/soc/amd/common/block/include/amdblocks/biosram.h index e2c1eb33f7..db283100d5 100644 --- a/src/soc/amd/common/block/include/amdblocks/biosram.h +++ b/src/soc/amd/common/block/include/amdblocks/biosram.h @@ -17,10 +17,15 @@ #include /* BiosRam Ranges at 0xfed80500 or I/O 0xcd4/0xcd5 */ +#define BIOSRAM_AP_ENTRY 0xe8 /* 8 bytes */ #define BIOSRAM_CBMEM_TOP 0xf0 /* 4 bytes */ #define BIOSRAM_UMA_SIZE 0xf4 /* 4 bytes */ #define BIOSRAM_UMA_BASE 0xf8 /* 8 bytes */ +/* Returns the bootblock C entry point for APs */ +void *get_ap_entry_ptr(void); +/* Used by BSP to store the bootblock entry point for APs */ +void set_ap_entry_ptr(void *entry); /* Saves the UMA size returned by AGESA */ void save_uma_size(uint32_t size); /* Saves the UMA base address returned by AGESA */ diff --git a/src/soc/amd/stoneyridge/Makefile.inc b/src/soc/amd/stoneyridge/Makefile.inc index d2d64c805c..52c54d26eb 100644 --- a/src/soc/amd/stoneyridge/Makefile.inc +++ b/src/soc/amd/stoneyridge/Makefile.inc @@ -48,7 +48,6 @@ bootblock-y += pmutil.c bootblock-y += reset.c bootblock-y += tsc_freq.c bootblock-y += southbridge.c -bootblock-y += nb_util.c bootblock-$(CONFIG_HAVE_SMI_HANDLER) += smi_util.c romstage-y += BiosCallOuts.c @@ -65,7 +64,6 @@ romstage-y += memmap.c romstage-$(CONFIG_STONEYRIDGE_UART) += uart.c romstage-y += tsc_freq.c romstage-y += southbridge.c -romstage-y += nb_util.c romstage-$(CONFIG_HAVE_SMI_HANDLER) += smi_util.c verstage-y += gpio.c @@ -75,12 +73,10 @@ verstage-y += pmutil.c verstage-y += reset.c verstage-$(CONFIG_STONEYRIDGE_UART) += uart.c verstage-y += tsc_freq.c -verstage-y += nb_util.c postcar-y += monotonic_timer.c postcar-$(CONFIG_STONEYRIDGE_UART) += uart.c postcar-y += memmap.c -postcar-y += nb_util.c postcar-$(CONFIG_VBOOT_MEASURED_BOOT) += i2c.c postcar-y += tsc_freq.c @@ -107,14 +103,12 @@ ramstage-$(CONFIG_STONEYRIDGE_UART) += uart.c ramstage-y += usb.c ramstage-y += tsc_freq.c ramstage-y += finalize.c -ramstage-y += nb_util.c smm-y += monotonic_timer.c smm-y += smihandler.c smm-y += smi_util.c smm-y += tsc_freq.c smm-$(CONFIG_DEBUG_SMI) += uart.c -smm-y += nb_util.c smm-y += gpio.c CPPFLAGS_common += -I$(src)/soc/amd/stoneyridge diff --git a/src/soc/amd/stoneyridge/bootblock/bootblock.c b/src/soc/amd/stoneyridge/bootblock/bootblock.c index a079ec2561..d92535ac31 100644 --- a/src/soc/amd/stoneyridge/bootblock/bootblock.c +++ b/src/soc/amd/stoneyridge/bootblock/bootblock.c @@ -24,9 +24,9 @@ #include #include #include +#include #include #include -#include #include #include #include diff --git a/src/soc/amd/stoneyridge/include/soc/northbridge.h b/src/soc/amd/stoneyridge/include/soc/northbridge.h index a0d7ce88dd..5694779fb5 100644 --- a/src/soc/amd/stoneyridge/include/soc/northbridge.h +++ b/src/soc/amd/stoneyridge/include/soc/northbridge.h @@ -40,8 +40,6 @@ #define NB_IOAPIC_SCRATCH0 0x3e #define NB_IOAPIC_SCRATCH1 0x3f -#define AP_SCRATCH_REG NB_IOAPIC_SCRATCH0 - /* D1F1 - HDA Configuration Registers */ #define HDA_DEV_CTRL_STATUS 0x60 #define HDA_NO_SNOOP_EN BIT(11) @@ -102,10 +100,6 @@ void domain_enable_resources(struct device *dev); void domain_set_resources(struct device *dev); void fam15_finalize(void *chip_info); -uint32_t nb_ioapic_read(unsigned int index); -void nb_ioapic_write(unsigned int index, uint32_t value); -void *get_ap_entry_ptr(void); -void set_ap_entry_ptr(void *entry); void set_warm_reset_flag(void); int is_warm_reset(void); diff --git a/src/soc/amd/stoneyridge/nb_util.c b/src/soc/amd/stoneyridge/nb_util.c deleted file mode 100644 index d5de067814..0000000000 --- a/src/soc/amd/stoneyridge/nb_util.c +++ /dev/null @@ -1,40 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2018 Advanced Micro Devices - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include - -uint32_t nb_ioapic_read(unsigned int index) -{ - pci_write_config32(SOC_GNB_DEV, NB_IOAPIC_INDEX, index); - return pci_read_config32(SOC_GNB_DEV, NB_IOAPIC_DATA); -} - -void nb_ioapic_write(unsigned int index, uint32_t value) -{ - pci_write_config32(SOC_GNB_DEV, NB_IOAPIC_INDEX, index); - pci_write_config32(SOC_GNB_DEV, NB_IOAPIC_DATA, value); -} - -void *get_ap_entry_ptr(void) -{ - return (void *)nb_ioapic_read(AP_SCRATCH_REG); -} - -void set_ap_entry_ptr(void *entry) -{ - nb_ioapic_write(AP_SCRATCH_REG, (uintptr_t)entry); -} diff --git a/src/soc/amd/stoneyridge/romstage.c b/src/soc/amd/stoneyridge/romstage.c index 2228c1a23e..25eb4a1ce2 100644 --- a/src/soc/amd/stoneyridge/romstage.c +++ b/src/soc/amd/stoneyridge/romstage.c @@ -14,6 +14,7 @@ * GNU General Public License for more details. */ +#include #include #include #include From 6b9cff49b004f965c87ccf75680fb942863f871e Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ky=C3=B6sti=20M=C3=A4lkki?= Date: Tue, 3 Dec 2019 08:21:30 +0200 Subject: [PATCH 0530/1242] AGESA: Reduce S3_DATA_SIZE MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Make some room for C environment bootblock. The S3 resume feature needs less than 2 KiB. Change-Id: Ic49c313d492f1d18f59d61e84f81f106e3b41fb1 Signed-off-by: Kyösti Mälkki Reviewed-on: https://review.coreboot.org/c/coreboot/+/37439 Tested-by: build bot (Jenkins) Reviewed-by: Michał Żygowski --- src/cpu/amd/agesa/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/cpu/amd/agesa/Kconfig b/src/cpu/amd/agesa/Kconfig index 9956579c69..5e1ff1d6c9 100644 --- a/src/cpu/amd/agesa/Kconfig +++ b/src/cpu/amd/agesa/Kconfig @@ -63,7 +63,7 @@ config S3_DATA_POS config S3_DATA_SIZE int - default 32768 + default 8192 endif # CPU_AMD_AGESA From 2f35744e4068ebc3e3bc13cee6b67b48bf2765a4 Mon Sep 17 00:00:00 2001 From: Peichao Wang Date: Mon, 11 Nov 2019 09:26:33 +0800 Subject: [PATCH 0531/1242] mb/google/hatch/var/akemi: tune DPTF for Akemi Tune DPTF to ensure compliance with Akemi thermal design requirements BUG=b:144195069 TEST=FW_NAME="akemi" emerge-hatch coreboot chromeos-ec chromeos-bootimage Signed-off-by: Peichao.Wang Change-Id: Ie0e6d93e1fc0c684e067d1450eb119a53cfefaed Reviewed-on: https://review.coreboot.org/c/coreboot/+/36716 Tested-by: build bot (Jenkins) Reviewed-by: Tim Wawrzynczak --- .../akemi/include/variant/acpi/dptf.asl | 79 ++++++++++--------- 1 file changed, 42 insertions(+), 37 deletions(-) diff --git a/src/mainboard/google/hatch/variants/akemi/include/variant/acpi/dptf.asl b/src/mainboard/google/hatch/variants/akemi/include/variant/acpi/dptf.asl index bb46fe9b1c..5c53022026 100644 --- a/src/mainboard/google/hatch/variants/akemi/include/variant/acpi/dptf.asl +++ b/src/mainboard/google/hatch/variants/akemi/include/variant/acpi/dptf.asl @@ -25,33 +25,33 @@ #define DPTF_TSR0_SENSOR_NAME "Thermal Sensor 1" #define DPTF_TSR0_PASSIVE 65 #define DPTF_TSR0_CRITICAL 75 -#define DPTF_TSR0_ACTIVE_AC0 50 -#define DPTF_TSR0_ACTIVE_AC1 47 -#define DPTF_TSR0_ACTIVE_AC2 45 -#define DPTF_TSR0_ACTIVE_AC3 42 -#define DPTF_TSR0_ACTIVE_AC4 39 +#define DPTF_TSR0_ACTIVE_AC0 61 +#define DPTF_TSR0_ACTIVE_AC1 59 +#define DPTF_TSR0_ACTIVE_AC2 57 +#define DPTF_TSR0_ACTIVE_AC3 55 +#define DPTF_TSR0_ACTIVE_AC4 51 +#define DPTF_TSR0_ACTIVE_AC5 48 +#define DPTF_TSR0_ACTIVE_AC6 40 #define DPTF_TSR1_SENSOR_ID 1 #define DPTF_TSR1_SENSOR_NAME "Thermal Sensor 2" -#define DPTF_TSR1_PASSIVE 65 +#define DPTF_TSR1_PASSIVE 38 #define DPTF_TSR1_CRITICAL 75 -#define DPTF_TSR1_ACTIVE_AC0 50 -#define DPTF_TSR1_ACTIVE_AC1 47 -#define DPTF_TSR1_ACTIVE_AC2 45 -#define DPTF_TSR1_ACTIVE_AC3 42 -#define DPTF_TSR1_ACTIVE_AC4 39 +#define DPTF_TSR1_ACTIVE_AC0 42 +#define DPTF_TSR1_ACTIVE_AC1 40 +#define DPTF_TSR1_ACTIVE_AC2 38 #define DPTF_TSR2_SENSOR_ID 2 #define DPTF_TSR2_SENSOR_NAME "Thermal Sensor - CPU" -#define DPTF_TSR2_PASSIVE 60 -#define DPTF_TSR2_CRITICAL 75 -#define DPTF_TSR2_ACTIVE_AC0 51 -#define DPTF_TSR2_ACTIVE_AC1 48 -#define DPTF_TSR2_ACTIVE_AC2 45 -#define DPTF_TSR2_ACTIVE_AC3 42 -#define DPTF_TSR2_ACTIVE_AC4 39 -#define DPTF_TSR2_ACTIVE_AC5 36 -#define DPTF_TSR2_ACTIVE_AC6 33 +#define DPTF_TSR2_PASSIVE 62 +#define DPTF_TSR2_CRITICAL 105 +#define DPTF_TSR2_ACTIVE_AC0 62 +#define DPTF_TSR2_ACTIVE_AC1 61 +#define DPTF_TSR2_ACTIVE_AC2 60 +#define DPTF_TSR2_ACTIVE_AC3 54 +#define DPTF_TSR2_ACTIVE_AC4 51 +#define DPTF_TSR2_ACTIVE_AC5 48 +#define DPTF_TSR2_ACTIVE_AC6 45 #define DPTF_ENABLE_CHARGER #define DPTF_ENABLE_FAN_CONTROL @@ -72,16 +72,21 @@ Name (DFPS, Package () { * These are initial reference values. */ /* Control, Trip Point, Speed, NoiseLevel, Power */ - Package () {90, 0xFFFFFFFF, 6700, 220, 2200}, - Package () {80, 0xFFFFFFFF, 5800, 180, 1800}, - Package () {70, 0xFFFFFFFF, 5000, 145, 1450}, - Package () {60, 0xFFFFFFFF, 4900, 115, 1150}, - Package () {50, 0xFFFFFFFF, 3838, 90, 900}, - Package () {40, 0xFFFFFFFF, 2904, 55, 550}, - Package () {30, 0xFFFFFFFF, 2337, 30, 300}, - Package () {20, 0xFFFFFFFF, 1608, 15, 150}, - Package () {10, 0xFFFFFFFF, 800, 10, 100}, - Package () {0, 0xFFFFFFFF, 0, 0, 50} + Package () {85, 0xFFFFFFFF, 5500, 180, 1800}, + Package () {79, 0xFFFFFFFF, 5400, 170, 1700}, + Package () {73, 0xFFFFFFFF, 5200, 160, 1600}, + Package () {68, 0xFFFFFFFF, 5000, 150, 1500}, + Package () {62, 0xFFFFFFFF, 4800, 140, 1400}, + Package () {58, 0xFFFFFFFF, 4600, 130, 1300}, + Package () {53, 0xFFFFFFFF, 4400, 110, 1100}, + Package () {49, 0xFFFFFFFF, 4200, 95, 950}, + Package () {46, 0xFFFFFFFF, 4000, 70, 700}, + Package () {42, 0xFFFFFFFF, 3700, 50, 500}, + Package () {40, 0xFFFFFFFF, 3600, 35, 350}, + Package () {36, 0xFFFFFFFF, 3400, 25, 250}, + Package () {33, 0xFFFFFFFF, 3200, 15, 150}, + Package () {30, 0xFFFFFFFF, 3000, 5, 50}, + Package () {0, 0xFFFFFFFF, 0, 0, 0} }) Name (DART, Package () { @@ -96,15 +101,15 @@ Name (DART, Package () { 0, 0, 0 }, Package () { - \_SB.DPTF.TFN1, \_SB.DPTF.TSR0, 100, 90, 69, 56, 46, 36, 0, 0, + \_SB.DPTF.TFN1, \_SB.DPTF.TSR0, 100, 85, 73, 62, 49, 33, 25, 14, 0, 0, 0 }, Package () { - \_SB.DPTF.TFN1, \_SB.DPTF.TSR1, 100, 90, 69, 56, 46, 36, 0, 0, + \_SB.DPTF.TFN1, \_SB.DPTF.TSR1, 100, 85, 73, 62, 0, 0, 0, 0, 0, 0, 0 }, Package () { - \_SB.DPTF.TFN1, \_SB.DPTF.TSR2, 100, 90, 80, 70, 60, 50, 40, 30, + \_SB.DPTF.TFN1, \_SB.DPTF.TSR2, 100, 85, 73, 62, 56, 33, 25, 14, 0, 0, 0 }, }) @@ -114,13 +119,13 @@ Name (DTRT, Package () { Package () { \_SB.PCI0.TCPU, \_SB.PCI0.TCPU, 100, 50, 0, 0, 0, 0 }, /* CPU Throttle Effect on Ambient (TSR0) */ - Package () { \_SB.PCI0.TCPU, \_SB.DPTF.TSR0, 100, 60, 0, 0, 0, 0 }, + Package () { \_SB.DPTF.TCHG, \_SB.DPTF.TSR0, 100, 60, 0, 0, 0, 0 }, /* Charger Throttle Effect on Charger (TSR1) */ - Package () { \_SB.DPTF.TCHG, \_SB.DPTF.TSR1, 100, 60, 0, 0, 0, 0 }, + Package () { \_SB.PCI0.TCPU, \_SB.DPTF.TSR1, 100, 60, 0, 0, 0, 0 }, /* CPU Throttle Effect on CPU (TSR2) */ - Package () { \_SB.DPTF.TCHG, \_SB.DPTF.TSR2, 100, 60, 0, 0, 0, 0 }, + Package () { \_SB.PCI0.TCPU, \_SB.DPTF.TSR2, 100, 60, 0, 0, 0, 0 }, }) Name (MPPC, Package () @@ -128,7 +133,7 @@ Name (MPPC, Package () 0x2, /* Revision */ Package () { /* Power Limit 1 */ 0, /* PowerLimitIndex, 0 for Power Limit 1 */ - 3000, /* PowerLimitMinimum */ + 5000, /* PowerLimitMinimum */ 15000, /* PowerLimitMaximum */ 28000, /* TimeWindowMinimum */ 32000, /* TimeWindowMaximum */ From d9105d98b7cf98bec64f53ee1fb786599279b336 Mon Sep 17 00:00:00 2001 From: Seunghwan Kim Date: Thu, 28 Nov 2019 16:35:02 +0900 Subject: [PATCH 0532/1242] mb/google/kohaku: Adjust I2C clock frequency All serial I2C bus frequencies should not be over 400KHz in kohaku, but the measurement showed frequencies of I2C1 and I2C4 were over 400KHz. (b:144885961) This change adjusts I2C speed settings to limit that frequencies to 400KHz. The new setting values have been from other projects using same I2C components, and verified I2C1 and I2C4 frequencies < 400MHz internally. BUG=b:144885961 BRANCH=firmware-hatch-12672.B TEST=Verified I2C1 and I2C4 frequency not over 400KHz Change-Id: I9614fb39b6e55cb2ce1b0879a9f5204e55002f8d Signed-off-by: Seunghwan Kim Reviewed-on: https://review.coreboot.org/c/coreboot/+/37313 Tested-by: build bot (Jenkins) Reviewed-by: Tim Wawrzynczak --- src/mainboard/google/hatch/variants/kohaku/overridetree.cb | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/src/mainboard/google/hatch/variants/kohaku/overridetree.cb b/src/mainboard/google/hatch/variants/kohaku/overridetree.cb index 55ac071be5..d515ecc44d 100644 --- a/src/mainboard/google/hatch/variants/kohaku/overridetree.cb +++ b/src/mainboard/google/hatch/variants/kohaku/overridetree.cb @@ -60,6 +60,8 @@ chip soc/intel/cannonlake }, .i2c[1] = { .speed = I2C_SPEED_FAST, + .rise_time_ns = 60, + .fall_time_ns = 25, }, .i2c[2] = { .speed = I2C_SPEED_FAST, @@ -68,8 +70,8 @@ chip soc/intel/cannonlake }, .i2c[4] = { .speed = I2C_SPEED_FAST, - .rise_time_ns = 100, - .fall_time_ns = 20, + .rise_time_ns = 104, + .fall_time_ns = 52, }, .gspi[0] = { .speed_mhz = 1, From afd687f71f629bbdf6c5bb25ac43e32079853a0c Mon Sep 17 00:00:00 2001 From: John Su Date: Tue, 26 Nov 2019 10:39:45 +0800 Subject: [PATCH 0533/1242] mb/google/drallion/variants/drallion: Adjust all I2C CLK to meet spec After adjustment on Drallion Touch Pad CLK: 393 KHz Touch Screen CLK: 381 KHz H1 CLK: 391 KHz BUG=b:144245601 BRANCH=master TEST=emerge-drallion coreboot chromeos-bootimage measure by scope with drallion. Change-Id: Id669d7199bc6ed4b55d7542f095c6c8baf00f984 Signed-off-by: John Su Reviewed-on: https://review.coreboot.org/c/coreboot/+/37230 Reviewed-by: Mathew King Tested-by: build bot (Jenkins) --- .../google/drallion/variants/drallion/devicetree.cb | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/src/mainboard/google/drallion/variants/drallion/devicetree.cb b/src/mainboard/google/drallion/variants/drallion/devicetree.cb index 2fcf191eae..75fd3ee09b 100644 --- a/src/mainboard/google/drallion/variants/drallion/devicetree.cb +++ b/src/mainboard/google/drallion/variants/drallion/devicetree.cb @@ -176,20 +176,20 @@ chip soc/intel/cannonlake .chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT, .i2c[0] = { .speed = I2C_SPEED_FAST, - .rise_time_ns = 52, - .fall_time_ns = 110, + .rise_time_ns = 180, + .fall_time_ns = 200, }, .i2c[1] = { .speed = I2C_SPEED_FAST, - .rise_time_ns = 52, - .fall_time_ns = 110, + .rise_time_ns = 30, + .fall_time_ns = 80, .data_hold_time_ns = 330, }, .i2c[4] = { .early_init = 1, .speed = I2C_SPEED_FAST, - .rise_time_ns = 36, - .fall_time_ns = 99, + .rise_time_ns = 30, + .fall_time_ns = 60, }, }" From 41fe62b6dccd6be84e9d3685c73f1d8683af78de Mon Sep 17 00:00:00 2001 From: "Hash.Hung" Date: Tue, 26 Nov 2019 23:36:40 +0800 Subject: [PATCH 0534/1242] mb/google/octopus: Create Lick variant Create new variant for Lick that is copied from phaser variant. Remove unnecessary code, due to not support touchscreen and stylus. Set to default_override_table. Remove variant.c. BUG=b:145181137 BRANCH=octopus TEST=./util/abuild/abuild -p none -t google/octopus -x -a Change-Id: If732d94194defb9f5ee9c847ee93dd58aef01174 Signed-off-by: Hash.Hung Reviewed-on: https://review.coreboot.org/c/coreboot/+/37247 Reviewed-by: Patrick Georgi Reviewed-by: Henry Sun Reviewed-by: Marco Chen Tested-by: build bot (Jenkins) --- src/mainboard/google/octopus/Kconfig | 2 + src/mainboard/google/octopus/Kconfig.name | 6 + .../google/octopus/variants/lick/Makefile.inc | 3 + .../google/octopus/variants/lick/gpio.c | 52 ++++++++ .../lick/include/variant/acpi/dptf.asl | 16 +++ .../variants/lick/include/variant/ec.h | 21 ++++ .../variants/lick/include/variant/gpio.h | 21 ++++ .../octopus/variants/lick/overridetree.cb | 113 ++++++++++++++++++ 8 files changed, 234 insertions(+) create mode 100644 src/mainboard/google/octopus/variants/lick/Makefile.inc create mode 100644 src/mainboard/google/octopus/variants/lick/gpio.c create mode 100644 src/mainboard/google/octopus/variants/lick/include/variant/acpi/dptf.asl create mode 100644 src/mainboard/google/octopus/variants/lick/include/variant/ec.h create mode 100644 src/mainboard/google/octopus/variants/lick/include/variant/gpio.h create mode 100644 src/mainboard/google/octopus/variants/lick/overridetree.cb diff --git a/src/mainboard/google/octopus/Kconfig b/src/mainboard/google/octopus/Kconfig index 65a641b1e6..78b2eba03b 100644 --- a/src/mainboard/google/octopus/Kconfig +++ b/src/mainboard/google/octopus/Kconfig @@ -63,6 +63,7 @@ config VARIANT_DIR default "octopus" if BOARD_GOOGLE_OCTOPUS default "garg" if BOARD_GOOGLE_GARG default "dood" if BOARD_GOOGLE_DOOD + default "lick" if BOARD_GOOGLE_LICK config DEVICETREE string @@ -85,6 +86,7 @@ config MAINBOARD_PART_NUMBER default "Octopus" if BOARD_GOOGLE_OCTOPUS default "Garg" if BOARD_GOOGLE_GARG default "Dood" if BOARD_GOOGLE_DOOD + default "Lick" if BOARD_GOOGLE_LICK config MAINBOARD_FAMILY string diff --git a/src/mainboard/google/octopus/Kconfig.name b/src/mainboard/google/octopus/Kconfig.name index 8a8d33981c..c837365239 100644 --- a/src/mainboard/google/octopus/Kconfig.name +++ b/src/mainboard/google/octopus/Kconfig.name @@ -17,6 +17,12 @@ config BOARD_GOOGLE_PHASER select BOARD_GOOGLE_BASEBOARD_OCTOPUS select NHLT_DA7219 if INCLUDE_NHLT_BLOBS +config BOARD_GOOGLE_LICK + bool "-> Lick" + select BASEBOARD_OCTOPUS_LAPTOP + select BOARD_GOOGLE_BASEBOARD_OCTOPUS + select NHLT_DA7219 if INCLUDE_NHLT_BLOBS + config BOARD_GOOGLE_FLEEX bool "-> Fleex" select BASEBOARD_OCTOPUS_LAPTOP diff --git a/src/mainboard/google/octopus/variants/lick/Makefile.inc b/src/mainboard/google/octopus/variants/lick/Makefile.inc new file mode 100644 index 0000000000..9fb63f5f43 --- /dev/null +++ b/src/mainboard/google/octopus/variants/lick/Makefile.inc @@ -0,0 +1,3 @@ +bootblock-y += gpio.c + +ramstage-y += gpio.c diff --git a/src/mainboard/google/octopus/variants/lick/gpio.c b/src/mainboard/google/octopus/variants/lick/gpio.c new file mode 100644 index 0000000000..d0599826b4 --- /dev/null +++ b/src/mainboard/google/octopus/variants/lick/gpio.c @@ -0,0 +1,52 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2019 Google LLC + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the + * GNU General Public License for more details. + */ + +#include +#include +#include +#include +#include +#include + +#define SKU_UNKNOWN 0xFFFFFFFF + +static const struct pad_config default_override_table[] = { + /* disable I2C7 SCL and SDA */ + PAD_NC(GPIO_114, UP_20K), /* LPSS_I2C7_SDA */ + PAD_NC(GPIO_115, UP_20K), /* LPSS_I2C7_SCL */ + + PAD_NC(GPIO_52, UP_20K), + PAD_NC(GPIO_53, UP_20K), + PAD_NC(GPIO_67, UP_20K), + PAD_NC(GPIO_117, UP_20K), + PAD_NC(GPIO_143, UP_20K), + + /* EN_PP3300_TOUCHSCREEN */ + PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_146, 0, DEEP, NONE, Tx0RxDCRx0, DISPUPD), + + PAD_NC(GPIO_161, DN_20K), + + /* EN_PP3300_WLAN_L */ + PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_178, 0, DEEP, NONE, Tx0RxDCRx0, DISPUPD), + + PAD_NC(GPIO_213, DN_20K), + PAD_NC(GPIO_214, DN_20K), +}; + +const struct pad_config *variant_override_gpio_table(size_t *num) +{ + *num = ARRAY_SIZE(default_override_table); + return default_override_table; +} diff --git a/src/mainboard/google/octopus/variants/lick/include/variant/acpi/dptf.asl b/src/mainboard/google/octopus/variants/lick/include/variant/acpi/dptf.asl new file mode 100644 index 0000000000..4f6497ab2d --- /dev/null +++ b/src/mainboard/google/octopus/variants/lick/include/variant/acpi/dptf.asl @@ -0,0 +1,16 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2019 Google LLC + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include diff --git a/src/mainboard/google/octopus/variants/lick/include/variant/ec.h b/src/mainboard/google/octopus/variants/lick/include/variant/ec.h new file mode 100644 index 0000000000..260d7d43b2 --- /dev/null +++ b/src/mainboard/google/octopus/variants/lick/include/variant/ec.h @@ -0,0 +1,21 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2019 Google LLC + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef MAINBOARD_EC_H +#define MAINBOARD_EC_H + +#include + +#endif diff --git a/src/mainboard/google/octopus/variants/lick/include/variant/gpio.h b/src/mainboard/google/octopus/variants/lick/include/variant/gpio.h new file mode 100644 index 0000000000..750b0d4ccc --- /dev/null +++ b/src/mainboard/google/octopus/variants/lick/include/variant/gpio.h @@ -0,0 +1,21 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2019 Google LLC + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the + * GNU General Public License for more details. + */ + +#ifndef MAINBOARD_GPIO_H +#define MAINBOARD_GPIO_H + +#include + +#endif /* MAINBOARD_GPIO_H */ diff --git a/src/mainboard/google/octopus/variants/lick/overridetree.cb b/src/mainboard/google/octopus/variants/lick/overridetree.cb new file mode 100644 index 0000000000..41d078e882 --- /dev/null +++ b/src/mainboard/google/octopus/variants/lick/overridetree.cb @@ -0,0 +1,113 @@ +chip soc/intel/apollolake + + # EMMC Tx CMD Delay + # Refer to EDS-Vol2-16.32. + # [14:8] steps of delay for DDR mode, each 125ps. + # [6:0] steps of delay for SDR mode, each 125ps. + register "emmc_tx_cmd_cntl" = "0x505" + + # EMMC TX DATA Delay 1 + # Refer to EDS-Vol2-16.33. + # [14:8] steps of delay for HS400, each 125ps. + # [6:0] steps of delay for SDR104/HS200, each 125ps. + register "emmc_tx_data_cntl1" = "0x0b0c" + + # EMMC TX DATA Delay 2 + # Refer to EDS-Vol2-16.34. + # [30:24] steps of delay for SDR50, each 125ps. + # [22:16] steps of delay for DDR50, each 125ps. + # [14:8] steps of delay for SDR25/HS50, each 125ps. + # [6:0] steps of delay for SDR12, each 125ps. + register "emmc_tx_data_cntl2" = "0x1c282929" + + # EMMC RX CMD/DATA Delay 1 + # Refer to EDS-Vol2-16.35. + # [30:24] steps of delay for SDR50, each 125ps. + # [22:16] steps of delay for DDR50, each 125ps. + # [14:8] steps of delay for SDR25/HS50, each 125ps. + # [6:0] steps of delay for SDR12, each 125ps. + register "emmc_rx_cmd_data_cntl1" = "0x00181b1b" + + # EMMC RX CMD/DATA Delay 2 + # Refer to EDS-Vol2-16.37. + # [17:16] stands for Rx Clock before Output Buffer + # [14:8] steps of delay for Auto Tuning Mode, each 125ps. + # [6:0] steps of delay for HS200, each 125ps. + register "emmc_rx_cmd_data_cntl2" = "0x10028" + + # EMMC Rx Strobe Delay + # Refer to EDS-Vol2-16.36. + # [14:8] Rx Strobe Delay DLL 1(HS400 Mode), each 125ps. + # [6:0] Rx Strobe Delay DLL 2(HS400 Mode), each 125ps. + register "emmc_rx_strobe_cntl" = "0x0b0b" + + # Intel Common SoC Config + #+-------------------+---------------------------+ + #| Field | Value | + #+-------------------+---------------------------+ + #| GSPI0 | cr50 TPM. Early init is | + #| | required to set up a BAR | + #| | for TPM communication | + #| | before memory is up | + #| I2C5 | Audio | + #| I2C6 | Trackpad | + #+-------------------+---------------------------+ + register "common_soc_config" = "{ + .gspi[0] = { + .speed_mhz = 1, + .early_init = 1, + }, + .i2c[5] = { + .speed = I2C_SPEED_FAST, + .rise_time_ns = 104, + .fall_time_ns = 52, + }, + .i2c[6] = { + .speed = I2C_SPEED_FAST, + .rise_time_ns = 66, + .fall_time_ns = 90, + .data_hold_time_ns = 350, + }, + }" + + device domain 0 on + device pci 17.1 on + chip drivers/i2c/da7219 + register "irq" = "ACPI_IRQ_LEVEL_LOW(GPIO_137_IRQ)" + register "btn_cfg" = "50" + register "mic_det_thr" = "500" + register "jack_ins_deb" = "20" + register "jack_det_rate" = ""32ms_64ms"" + register "jack_rem_deb" = "1" + register "a_d_btn_thr" = "0xa" + register "d_b_btn_thr" = "0x16" + register "b_c_btn_thr" = "0x21" + register "c_mic_btn_thr" = "0x3e" + register "btn_avg" = "4" + register "adc_1bit_rpt" = "1" + register "micbias_lvl" = "2600" + register "mic_amp_in_sel" = ""diff"" + device i2c 1a on end + end + end # - I2C 5 + device pci 17.2 on + chip drivers/i2c/generic + register "hid" = ""ELAN0000"" + register "desc" = ""ELAN Touchpad"" + register "irq" = "ACPI_IRQ_WAKE_EDGE_LOW(GPIO_135_IRQ)" + register "wake" = "GPE0_DW3_27" + register "probed" = "1" + device i2c 15 on end + end + chip drivers/i2c/hid + register "generic.hid" = ""PNP0C50"" + register "generic.desc" = ""Synaptics Touchpad"" + register "generic.irq" = "ACPI_IRQ_WAKE_EDGE_LOW(GPIO_135_IRQ)" + register "generic.wake" = "GPE0_DW3_27" + register "generic.probed" = "1" + register "hid_desc_reg_offset" = "0x20" + device i2c 0x2c on end + end + end # - I2C 6 + end +end From 1c371572188a90ea16275460dd4ab6bf9966350b Mon Sep 17 00:00:00 2001 From: Julius Werner Date: Mon, 2 Dec 2019 18:02:51 -0800 Subject: [PATCH 0535/1242] mmio: Add clrsetbitsXX() API in place of updateX() This patch removes the recently added update8/16/32/64() API and replaces it with clrsetbits8/16/32/64(). This is more in line with the existing endian-specific clrsetbits_le16/32/64() functions that have been used for this task on some platforms already. Rename clrsetbits_8() to clrsetbits8() to be in line with the new naming. Keep this stuff in and get rid of again because having both is confusing and we seem to have been standardizing on as the standard arch-independent header that all platforms should include already. Also sync libpayload back up with what we have in coreboot. (I'm the original author of the clrsetbits_le32-definitions so I'm relicensing them to BSD here.) Change-Id: Ie4f7b9fdbdf9e8c0174427b4288f79006d56978b Signed-off-by: Julius Werner Reviewed-on: https://review.coreboot.org/c/coreboot/+/37432 Reviewed-by: Nico Huber Reviewed-by: Furquan Shaikh Reviewed-by: Hung-Te Lin Tested-by: build bot (Jenkins) --- payloads/libpayload/include/endian.h | 53 +++++++++++++++++++++------ src/drivers/maxim/max77686/max77686.c | 6 +-- src/include/device/mmio.h | 18 +++++++++ src/include/endian.h | 5 --- src/include/mmio.h | 45 ----------------------- 5 files changed, 62 insertions(+), 65 deletions(-) delete mode 100644 src/include/mmio.h diff --git a/payloads/libpayload/include/endian.h b/payloads/libpayload/include/endian.h index b387e66243..ec0825dc31 100644 --- a/payloads/libpayload/include/endian.h +++ b/payloads/libpayload/include/endian.h @@ -181,18 +181,47 @@ static inline void le32enc(void *pp, uint32_t u) /* Handy bit manipulation macros */ -#define clrsetbits_le32(addr, clear, set) writel(htole32((le32toh(readl(addr)) \ - & ~(clear)) | (set)), (addr)) -#define setbits_le32(addr, set) writel(htole32(le32toh(readl(addr)) \ - | (set)), (addr)) -#define clrbits_le32(addr, clear) writel(htole32(le32toh(readl(addr)) \ - & ~(clear)), (addr)) +#define __clrsetbits(endian, bits, addr, clear, set) \ + write##bits(addr, hto##endian##bits((endian##bits##toh( \ + read##bits(addr)) & ~((uint##bits##_t)(clear))) | (set))) -#define clrsetbits_be32(addr, clear, set) writel(htobe32((be32toh(readl(addr)) \ - & ~(clear)) | (set)), (addr)) -#define setbits_be32(addr, set) writel(htobe32(be32toh(readl(addr)) \ - | (set)), (addr)) -#define clrbits_be32(addr, clear) writel(htobe32(be32toh(readl(addr)) \ - & ~(clear)), (addr)) +#define clrbits_le64(addr, clear) __clrsetbits(le, 64, addr, clear, 0) +#define clrbits_be64(addr, clear) __clrsetbits(be, 64, addr, clear, 0) +#define clrbits_le32(addr, clear) __clrsetbits(le, 32, addr, clear, 0) +#define clrbits_be32(addr, clear) __clrsetbits(be, 32, addr, clear, 0) +#define clrbits_le16(addr, clear) __clrsetbits(le, 16, addr, clear, 0) +#define clrbits_be16(addr, clear) __clrsetbits(be, 16, addr, clear, 0) + +#define setbits_le64(addr, set) __clrsetbits(le, 64, addr, 0, set) +#define setbits_be64(addr, set) __clrsetbits(be, 64, addr, 0, set) +#define setbits_le32(addr, set) __clrsetbits(le, 32, addr, 0, set) +#define setbits_be32(addr, set) __clrsetbits(be, 32, addr, 0, set) +#define setbits_le16(addr, set) __clrsetbits(le, 16, addr, 0, set) +#define setbits_be16(addr, set) __clrsetbits(be, 16, addr, 0, set) + +#define clrsetbits_le64(addr, clear, set) __clrsetbits(le, 64, addr, clear, set) +#define clrsetbits_be64(addr, clear, set) __clrsetbits(be, 64, addr, clear, set) +#define clrsetbits_le32(addr, clear, set) __clrsetbits(le, 32, addr, clear, set) +#define clrsetbits_be32(addr, clear, set) __clrsetbits(be, 32, addr, clear, set) +#define clrsetbits_le16(addr, clear, set) __clrsetbits(le, 16, addr, clear, set) +#define clrsetbits_be16(addr, clear, set) __clrsetbits(be, 16, addr, clear, set) + +#define __clrsetbits_impl(bits, addr, clear, set) write##bits(addr, \ + (read##bits(addr) & ~((uint##bits##_t)(clear))) | (set)) + +#define clrsetbits8(addr, clear, set) __clrsetbits_impl(8, addr, clear, set) +#define clrsetbits16(addr, clear, set) __clrsetbits_impl(16, addr, clear, set) +#define clrsetbits32(addr, clear, set) __clrsetbits_impl(32, addr, clear, set) +#define clrsetbits64(addr, clear, set) __clrsetbits_impl(64, addr, clear, set) + +#define setbits8(addr, set) clrsetbits8(addr, 0, set) +#define setbits16(addr, set) clrsetbits16(addr, 0, set) +#define setbits32(addr, set) clrsetbits32(addr, 0, set) +#define setbits64(addr, set) clrsetbits64(addr, 0, set) + +#define clrbits8(addr, clear) clrsetbits8(addr, clear, 0) +#define clrbits16(addr, clear) clrsetbits16(addr, clear, 0) +#define clrbits32(addr, clear) clrsetbits32(addr, clear, 0) +#define clrbits64(addr, clear) clrsetbits64(addr, clear, 0) #endif /* _ENDIAN_H_ */ diff --git a/src/drivers/maxim/max77686/max77686.c b/src/drivers/maxim/max77686/max77686.c index 54e3a6c912..cfbf912937 100644 --- a/src/drivers/maxim/max77686/max77686.c +++ b/src/drivers/maxim/max77686/max77686.c @@ -127,10 +127,10 @@ static int max77686_enablereg(unsigned int bus, enum max77686_regnum reg, int en } if (enable == REG_DISABLE) { - clrbits_8(&read_data, + clrbits8(&read_data, pmic->reg_enbitmask << pmic->reg_enbitpos); } else { - clrsetbits_8(&read_data, + clrsetbits8(&read_data, pmic->reg_enbitmask << pmic->reg_enbitpos, pmic->reg_enbiton << pmic->reg_enbitpos); } @@ -177,7 +177,7 @@ int max77686_volsetting(unsigned int bus, enum max77686_regnum reg, } vol_level /= (u32)pmic->vol_div; - clrsetbits_8(&read_data, pmic->vol_bitmask << pmic->vol_bitpos, + clrsetbits8(&read_data, pmic->vol_bitmask << pmic->vol_bitpos, vol_level << pmic->vol_bitpos); ret = max77686_i2c_write(bus, MAX77686_I2C_ADDR, pmic->vol_addr, read_data); diff --git a/src/include/device/mmio.h b/src/include/device/mmio.h index 6596cf89ed..9c5e27cfd8 100644 --- a/src/include/device/mmio.h +++ b/src/include/device/mmio.h @@ -19,6 +19,24 @@ #include #include +#define __clrsetbits_impl(bits, addr, clear, set) write##bits(addr, \ + (read##bits(addr) & ~((uint##bits##_t)(clear))) | (set)) + +#define clrsetbits8(addr, clear, set) __clrsetbits_impl(8, addr, clear, set) +#define clrsetbits16(addr, clear, set) __clrsetbits_impl(16, addr, clear, set) +#define clrsetbits32(addr, clear, set) __clrsetbits_impl(32, addr, clear, set) +#define clrsetbits64(addr, clear, set) __clrsetbits_impl(64, addr, clear, set) + +#define setbits8(addr, set) clrsetbits8(addr, 0, set) +#define setbits16(addr, set) clrsetbits16(addr, 0, set) +#define setbits32(addr, set) clrsetbits32(addr, 0, set) +#define setbits64(addr, set) clrsetbits64(addr, 0, set) + +#define clrbits8(addr, clear) clrsetbits8(addr, clear, 0) +#define clrbits16(addr, clear) clrsetbits16(addr, clear, 0) +#define clrbits32(addr, clear) clrsetbits32(addr, clear, 0) +#define clrbits64(addr, clear) clrsetbits64(addr, clear, 0) + #ifndef __ROMCC__ /* * Reads a transfer buffer from 32-bit FIFO registers. fifo_stride is the diff --git a/src/include/endian.h b/src/include/endian.h index 8dc18542ae..f16f668a18 100644 --- a/src/include/endian.h +++ b/src/include/endian.h @@ -79,11 +79,6 @@ #define clrsetbits_le16(addr, clear, set) __clrsetbits(le, 16, addr, clear, set) #define clrsetbits_be16(addr, clear, set) __clrsetbits(be, 16, addr, clear, set) -#define clrsetbits_8(addr, clear, set) \ - write8(addr, (read8(addr) & ~(clear)) | (set)) -#define clrbits_8(addr, clear) clrsetbits_8(addr, clear, 0) -#define setbits_8(addr, set) setbits_8(addr, 0, set) - #ifndef __ROMCC__ /* be16dec/be32dec/be64dec/le16dec/le32dec/le64dec family of functions. */ #define DEFINE_ENDIAN_DEC(endian, width) \ diff --git a/src/include/mmio.h b/src/include/mmio.h deleted file mode 100644 index 4f2c806cac..0000000000 --- a/src/include/mmio.h +++ /dev/null @@ -1,45 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -/* - * mmio.h provides update*() as well as read/write*() from arch/mmio.h - */ - -#ifndef __MMIO_H__ -#define __MMIO_H__ - -#include -#include - -static __always_inline void update8(volatile void *addr, uint8_t mask, uint8_t or) -{ - uint8_t reg = read8(addr); - reg = (reg & mask) | or; - write8(addr, reg); -} - -static __always_inline void update16(volatile void *addr, uint16_t mask, uint16_t or) -{ - uint16_t reg = read16(addr); - reg = (reg & mask) | or; - write16(addr, reg); -} - -static __always_inline void update32(volatile void *addr, uint32_t mask, uint32_t or) -{ - uint32_t reg = read32(addr); - reg = (reg & mask) | or; - write32(addr, reg); -} - -#endif /* __MMIO_H__ */ From 55009af42c39f413c49503670ce9bc2858974962 Mon Sep 17 00:00:00 2001 From: Julius Werner Date: Mon, 2 Dec 2019 22:03:27 -0800 Subject: [PATCH 0536/1242] Change all clrsetbits_leXX() to clrsetbitsXX() This patch changes all existing instances of clrsetbits_leXX() to the new endian-independent clrsetbitsXX(), after double-checking that they're all in SoC-specific code operating on CPU registers and not actually trying to make an endian conversion. This patch was created by running sed -i -e 's/\([cs][le][rt]bits\)_le\([136][624]\)/\1\2/g' across the codebase and cleaning up formatting a bit. Change-Id: I7fc3e736e5fe927da8960fdcd2aae607b62b5ff4 Signed-off-by: Julius Werner Reviewed-on: https://review.coreboot.org/c/coreboot/+/37433 Tested-by: build bot (Jenkins) Reviewed-by: Hung-Te Lin --- payloads/libpayload/drivers/udc/chipidea.c | 16 +- src/arch/arm64/include/armv8/arch/mmio.h | 1 - src/cpu/ti/am335x/gpio.c | 4 +- src/drivers/crb/tpm.c | 3 +- src/include/device/mmio.h | 8 +- src/mainboard/google/kahlee/mainboard.c | 16 +- src/mainboard/google/nyan/mainboard.c | 6 +- src/mainboard/google/nyan_big/mainboard.c | 6 +- src/mainboard/google/nyan_blaze/mainboard.c | 6 +- src/mainboard/google/oak/bootblock.c | 6 +- src/mainboard/google/storm/cdp.c | 4 +- src/mainboard/google/trogdor/mainboard.c | 4 +- src/mainboard/google/veyron/bootblock.c | 4 +- .../google/veyron_mickey/bootblock.c | 4 +- .../google/veyron_rialto/bootblock.c | 4 +- src/mainboard/sifive/hifive-unleashed/media.c | 2 +- src/soc/amd/picasso/uart.c | 2 +- src/soc/cavium/cn81xx/timer.c | 12 +- src/soc/mediatek/common/ddp.c | 8 +- src/soc/mediatek/common/dsi.c | 8 +- src/soc/mediatek/common/gpio.c | 3 +- src/soc/mediatek/common/mtcmos.c | 12 +- src/soc/mediatek/common/spi.c | 36 +- src/soc/mediatek/common/timer.c | 4 +- src/soc/mediatek/common/usb.c | 46 +- src/soc/mediatek/common/wdt.c | 8 +- src/soc/mediatek/mt8173/ddp.c | 20 +- src/soc/mediatek/mt8173/dramc_pi_basic_api.c | 226 ++-- .../mt8173/dramc_pi_calibration_api.c | 196 ++-- src/soc/mediatek/mt8173/dsi.c | 40 +- src/soc/mediatek/mt8173/emi.c | 8 +- src/soc/mediatek/mt8173/gpio_init.c | 4 +- src/soc/mediatek/mt8173/pll.c | 54 +- src/soc/mediatek/mt8173/pmic_wrap.c | 4 +- src/soc/mediatek/mt8173/spi.c | 8 +- src/soc/mediatek/mt8183/auxadc.c | 8 +- src/soc/mediatek/mt8183/ddp.c | 8 +- src/soc/mediatek/mt8183/dramc_init_setting.c | 966 +++++++++--------- src/soc/mediatek/mt8183/dramc_pi_basic_api.c | 214 ++-- .../mt8183/dramc_pi_calibration_api.c | 238 ++--- src/soc/mediatek/mt8183/dsi.c | 22 +- src/soc/mediatek/mt8183/emi.c | 38 +- src/soc/mediatek/mt8183/gpio.c | 32 +- src/soc/mediatek/mt8183/md_ctrl.c | 4 +- src/soc/mediatek/mt8183/pll.c | 48 +- src/soc/mediatek/mt8183/spi.c | 8 +- src/soc/mediatek/mt8183/spm.c | 14 +- src/soc/mediatek/mt8183/sspm.c | 2 +- src/soc/nvidia/tegra/usb.c | 4 +- src/soc/nvidia/tegra124/clock.c | 36 +- src/soc/nvidia/tegra124/dma.c | 8 +- src/soc/nvidia/tegra124/include/soc/clock.h | 4 +- src/soc/nvidia/tegra124/power.c | 4 +- src/soc/nvidia/tegra124/sdram.c | 24 +- src/soc/nvidia/tegra124/spi.c | 42 +- src/soc/nvidia/tegra210/addressmap.c | 10 +- src/soc/nvidia/tegra210/clock.c | 38 +- src/soc/nvidia/tegra210/cpu.c | 2 +- src/soc/nvidia/tegra210/dma.c | 8 +- src/soc/nvidia/tegra210/include/soc/clock.h | 4 +- src/soc/nvidia/tegra210/sdram.c | 24 +- src/soc/nvidia/tegra210/spi.c | 52 +- src/soc/qualcomm/ipq40xx/blsp.c | 2 +- src/soc/qualcomm/ipq40xx/clock.c | 6 +- src/soc/qualcomm/ipq40xx/include/soc/iomap.h | 4 +- src/soc/qualcomm/ipq40xx/spi.c | 18 +- src/soc/qualcomm/ipq806x/clock.c | 10 +- src/soc/qualcomm/ipq806x/include/soc/iomap.h | 4 +- src/soc/qualcomm/ipq806x/spi.c | 46 +- src/soc/qualcomm/ipq806x/usb.c | 12 +- src/soc/qualcomm/qcs405/blsp.c | 2 +- src/soc/qualcomm/qcs405/clock.c | 14 +- src/soc/qualcomm/qcs405/gpio.c | 4 +- src/soc/qualcomm/qcs405/include/soc/iomap.h | 4 +- src/soc/qualcomm/qcs405/spi.c | 18 +- src/soc/qualcomm/qcs405/usb.c | 20 +- src/soc/qualcomm/sc7180/gpio.c | 6 +- src/soc/qualcomm/sdm845/clock.c | 14 +- src/soc/qualcomm/sdm845/usb.c | 16 +- src/soc/rockchip/common/edp.c | 26 +- src/soc/rockchip/common/gpio.c | 26 +- src/soc/rockchip/common/pwm.c | 2 +- src/soc/rockchip/common/spi.c | 14 +- src/soc/rockchip/common/vop.c | 38 +- src/soc/rockchip/rk3288/hdmi.c | 92 +- src/soc/rockchip/rk3288/sdram.c | 108 +- src/soc/rockchip/rk3288/software_i2c.c | 8 +- src/soc/rockchip/rk3288/tsadc.c | 8 +- src/soc/rockchip/rk3399/clock.c | 6 +- src/soc/rockchip/rk3399/saradc.c | 10 +- src/soc/rockchip/rk3399/sdram.c | 300 +++--- src/soc/rockchip/rk3399/tsadc.c | 6 +- src/soc/rockchip/rk3399/usb.c | 12 +- src/soc/samsung/exynos5250/clock.c | 8 +- src/soc/samsung/exynos5250/clock_init.c | 248 ++--- src/soc/samsung/exynos5250/dp-reg.c | 20 +- src/soc/samsung/exynos5250/fb.c | 24 +- src/soc/samsung/exynos5250/power.c | 12 +- src/soc/samsung/exynos5250/spi.c | 34 +- src/soc/samsung/exynos5250/usb.c | 40 +- src/soc/samsung/exynos5420/clock.c | 8 +- src/soc/samsung/exynos5420/clock_init.c | 10 +- src/soc/samsung/exynos5420/dmc_init_ddr3.c | 34 +- src/soc/samsung/exynos5420/power.c | 12 +- src/soc/samsung/exynos5420/spi.c | 20 +- src/soc/samsung/exynos5420/usb.c | 50 +- src/soc/sifive/fu540/clock.c | 14 +- src/soc/sifive/fu540/spi.c | 2 +- 108 files changed, 2022 insertions(+), 2025 deletions(-) diff --git a/payloads/libpayload/drivers/udc/chipidea.c b/payloads/libpayload/drivers/udc/chipidea.c index 20267ede62..702cd6e4d2 100644 --- a/payloads/libpayload/drivers/udc/chipidea.c +++ b/payloads/libpayload/drivers/udc/chipidea.c @@ -140,7 +140,7 @@ static void chipidea_halt_ep(struct usbdev_ctrl *this, int ep, int in_dir) writel(1 << ep_to_bits(ep, in_dir), &p->opreg->epflush); while (readl(&p->opreg->epflush)) ; - clrbits_le32(&p->opreg->epctrl[ep], 1 << (7 + (in_dir ? 16 : 0))); + clrbits32(&p->opreg->epctrl[ep], 1 << (7 + (in_dir ? 16 : 0))); while (!SIMPLEQ_EMPTY(&p->job_queue[ep][in_dir])) { struct job *job = SIMPLEQ_FIRST(&p->job_queue[ep][in_dir]); @@ -161,7 +161,7 @@ static void chipidea_start_ep(struct usbdev_ctrl *this, in_dir = in_dir ? 1 : 0; debug("enabling %d-%d (type %d)\n", ep, in_dir, ep_type); /* enable endpoint, reset data toggle */ - setbits_le32(&p->opreg->epctrl[ep], + setbits32(&p->opreg->epctrl[ep], ((1 << 7) | (1 << 6) | (ep_type << 2)) << (in_dir*16)); p->ep_busy[ep][in_dir] = 0; this->ep_mps[ep][in_dir] = mps; @@ -456,17 +456,17 @@ static void chipidea_stall(struct usbdev_ctrl *this, in_dir = in_dir ? 1 : 0; if (set) { if (in_dir) - setbits_le32(ctrl, 1 << 16); + setbits32(ctrl, 1 << 16); else - setbits_le32(ctrl, 1 << 0); + setbits32(ctrl, 1 << 0); } else { /* reset STALL bit, reset data toggle */ if (in_dir) { - setbits_le32(ctrl, 1 << 22); - clrbits_le32(ctrl, 1 << 16); + setbits32(ctrl, 1 << 22); + clrbits32(ctrl, 1 << 16); } else { - setbits_le32(ctrl, 1 << 6); - clrbits_le32(ctrl, 1 << 0); + setbits32(ctrl, 1 << 6); + clrbits32(ctrl, 1 << 0); } } this->ep_halted[ep][in_dir] = set; diff --git a/src/arch/arm64/include/armv8/arch/mmio.h b/src/arch/arm64/include/armv8/arch/mmio.h index 4342fc60e5..4a92ddb38d 100644 --- a/src/arch/arm64/include/armv8/arch/mmio.h +++ b/src/arch/arm64/include/armv8/arch/mmio.h @@ -17,7 +17,6 @@ #ifndef __ARCH_MMIO_H__ #define __ARCH_MMIO_H__ -#include #include #include #include diff --git a/src/cpu/ti/am335x/gpio.c b/src/cpu/ti/am335x/gpio.c index 0b3eae815c..5e3b62a34f 100644 --- a/src/cpu/ti/am335x/gpio.c +++ b/src/cpu/ti/am335x/gpio.c @@ -45,7 +45,7 @@ int gpio_direction_input(unsigned int gpio) if (!regs) return -1; - setbits_le32(®s->oe, bit); + setbits32(®s->oe, bit); return 0; } @@ -60,7 +60,7 @@ int gpio_direction_output(unsigned int gpio, int value) write32(®s->setdataout, bit); else write32(®s->cleardataout, bit); - clrbits_le32(®s->oe, bit); + clrbits32(®s->oe, bit); return 0; } diff --git a/src/drivers/crb/tpm.c b/src/drivers/crb/tpm.c index f2b7903e4c..964ccf9f95 100644 --- a/src/drivers/crb/tpm.c +++ b/src/drivers/crb/tpm.c @@ -16,10 +16,9 @@ #include #include -#include #include +#include #include -#include #include #include diff --git a/src/include/device/mmio.h b/src/include/device/mmio.h index 9c5e27cfd8..4007cff7c3 100644 --- a/src/include/device/mmio.h +++ b/src/include/device/mmio.h @@ -120,10 +120,10 @@ static inline void buffer_to_fifo32(void *buffer, size_t size, void *fifo, * * These will be translated to: * - * clrsetbits_le32(&disp_regs.ctrl, 0x6, 0x4); - * clrsetbits_le32(&disp_regs.ctrl, 0x1, 0x0); + * clrsetbits32(&disp_regs.ctrl, 0x6, 0x4); + * clrsetbits32(&disp_regs.ctrl, 0x1, 0x0); * - * clrsetbits_le32(&disp_regs.ctrl, 0x7, 0x3); + * clrsetbits32(&disp_regs.ctrl, 0x7, 0x3); * write32(&disp_regs.ctrl, 0x3); * * (read32(®) & 0x6) >> 1 @@ -187,7 +187,7 @@ static inline void buffer_to_fifo32(void *buffer, size_t size, void *fifo, _BF_IMPL(_WRITE32_BITFIELDS_IMPL, addr, __VA_ARGS__) #define SET32_BITFIELDS(addr, ...) \ - _BF_IMPL(clrsetbits_le32, addr, __VA_ARGS__) + _BF_IMPL(clrsetbits32, addr, __VA_ARGS__) #define EXTRACT_BITFIELD(value, name) \ (((value) & _BF_MASK(name, 0)) >> name##_BITFIELD_SHIFT) diff --git a/src/mainboard/google/kahlee/mainboard.c b/src/mainboard/google/kahlee/mainboard.c index f218f3f31b..0173064b10 100644 --- a/src/mainboard/google/kahlee/mainboard.c +++ b/src/mainboard/google/kahlee/mainboard.c @@ -147,16 +147,16 @@ static void mainboard_init(void *chip_info) pm_write8(PM_PCIB_CFG, pm_read8(PM_PCIB_CFG) | PM_GENINT_DISABLE); /* Set low-power mode for BayHub eMMC bridge's PCIe clock. */ - clrsetbits_le32((uint32_t *)(ACPIMMIO_MISC_BASE + GPP_CLK_CNTRL), - GPP_CLK2_REQ_MAP_MASK, - GPP_CLK2_REQ_MAP_CLK_REQ2 << - GPP_CLK2_REQ_MAP_SHIFT); + clrsetbits32((uint32_t *)(ACPIMMIO_MISC_BASE + GPP_CLK_CNTRL), + GPP_CLK2_REQ_MAP_MASK, + GPP_CLK2_REQ_MAP_CLK_REQ2 << + GPP_CLK2_REQ_MAP_SHIFT); /* Same for the WiFi */ - clrsetbits_le32((uint32_t *)(ACPIMMIO_MISC_BASE + GPP_CLK_CNTRL), - GPP_CLK0_REQ_MAP_MASK, - GPP_CLK0_REQ_MAP_CLK_REQ0 << - GPP_CLK0_REQ_MAP_SHIFT); + clrsetbits32((uint32_t *)(ACPIMMIO_MISC_BASE + GPP_CLK_CNTRL), + GPP_CLK0_REQ_MAP_MASK, + GPP_CLK0_REQ_MAP_CLK_REQ0 << + GPP_CLK0_REQ_MAP_SHIFT); } /************************************************* diff --git a/src/mainboard/google/nyan/mainboard.c b/src/mainboard/google/nyan/mainboard.c index 3e9f9fad7b..7fa47bbcb5 100644 --- a/src/mainboard/google/nyan/mainboard.c +++ b/src/mainboard/google/nyan/mainboard.c @@ -61,9 +61,9 @@ static void set_clock_sources(void) clock_configure_irregular_source(host1x, PLLP, 408000, 4); /* Use PLLD_OUT0 as clock source for disp1 */ - clrsetbits_le32(&clk_rst->clk_src_disp1, - CLK_SOURCE_MASK | CLK_DIVISOR_MASK, - 2 /*PLLD_OUT0 */ << CLK_SOURCE_SHIFT); + clrsetbits32(&clk_rst->clk_src_disp1, + CLK_SOURCE_MASK | CLK_DIVISOR_MASK, + 2 /*PLLD_OUT0 */ << CLK_SOURCE_SHIFT); } diff --git a/src/mainboard/google/nyan_big/mainboard.c b/src/mainboard/google/nyan_big/mainboard.c index 9c4e943ae5..115f73aa1e 100644 --- a/src/mainboard/google/nyan_big/mainboard.c +++ b/src/mainboard/google/nyan_big/mainboard.c @@ -61,9 +61,9 @@ static void set_clock_sources(void) clock_configure_irregular_source(host1x, PLLP, 408000, 4); /* Use PLLD_OUT0 as clock source for disp1 */ - clrsetbits_le32(&clk_rst->clk_src_disp1, - CLK_SOURCE_MASK | CLK_DIVISOR_MASK, - 2 /*PLLD_OUT0 */ << CLK_SOURCE_SHIFT); + clrsetbits32(&clk_rst->clk_src_disp1, + CLK_SOURCE_MASK | CLK_DIVISOR_MASK, + 2 /*PLLD_OUT0 */ << CLK_SOURCE_SHIFT); } diff --git a/src/mainboard/google/nyan_blaze/mainboard.c b/src/mainboard/google/nyan_blaze/mainboard.c index 7f8abab119..d57ac8bdd8 100644 --- a/src/mainboard/google/nyan_blaze/mainboard.c +++ b/src/mainboard/google/nyan_blaze/mainboard.c @@ -61,9 +61,9 @@ static void set_clock_sources(void) clock_configure_irregular_source(host1x, PLLP, 408000, 4); /* Use PLLD_OUT0 as clock source for disp1 */ - clrsetbits_le32(&clk_rst->clk_src_disp1, - CLK_SOURCE_MASK | CLK_DIVISOR_MASK, - 2 /*PLLD_OUT0 */ << CLK_SOURCE_SHIFT); + clrsetbits32(&clk_rst->clk_src_disp1, + CLK_SOURCE_MASK | CLK_DIVISOR_MASK, + 2 /*PLLD_OUT0 */ << CLK_SOURCE_SHIFT); } diff --git a/src/mainboard/google/oak/bootblock.c b/src/mainboard/google/oak/bootblock.c index 89169ef0bf..73e50fda63 100644 --- a/src/mainboard/google/oak/bootblock.c +++ b/src/mainboard/google/oak/bootblock.c @@ -42,9 +42,9 @@ static void nor_set_gpio_pinmux(void) * 3: 16mA */ /* EINT4: 0x10005B20[14:13] */ - clrsetbits_le16(&mtk_gpio->drv_mode[2].val, 0xf << 12, 2 << 13); + clrsetbits16(&mtk_gpio->drv_mode[2].val, 0xf << 12, 2 << 13); /* EINT5~EINT9: 0x10005B30[2:1] */ - clrsetbits_le16(&mtk_gpio->drv_mode[3].val, 0xf << 0, 2 << 1), + clrsetbits16(&mtk_gpio->drv_mode[3].val, 0xf << 0, 2 << 1), gpio_set_pull(GPIO(EINT4), GPIO_PULL_ENABLE, GPIO_PULL_UP); gpio_set_pull(GPIO(EINT5), GPIO_PULL_ENABLE, GPIO_PULL_UP); @@ -64,7 +64,7 @@ static void nor_set_gpio_pinmux(void) void bootblock_mainboard_early_init(void) { /* Clear UART0 power down signal */ - clrbits_le32(&mt8173_pericfg->pdn0_set, PERICFG_UART0_PDN); + clrbits32(&mt8173_pericfg->pdn0_set, PERICFG_UART0_PDN); } void bootblock_mainboard_init(void) diff --git a/src/mainboard/google/storm/cdp.c b/src/mainboard/google/storm/cdp.c index f143bf9171..18b22c13ce 100644 --- a/src/mainboard/google/storm/cdp.c +++ b/src/mainboard/google/storm/cdp.c @@ -68,6 +68,6 @@ void board_nand_init(void) configure_nand_gpio(); /* NAND Flash is connected to CS0 */ - clrsetbits_le32(&ebi2_regs->chip_select_cfg0, CS0_CFG_MASK, - CS0_CFG_SERIAL_FLASH_DEVICE); + clrsetbits32(&ebi2_regs->chip_select_cfg0, CS0_CFG_MASK, + CS0_CFG_SERIAL_FLASH_DEVICE); } diff --git a/src/mainboard/google/trogdor/mainboard.c b/src/mainboard/google/trogdor/mainboard.c index ce03ce1421..42af265cd9 100644 --- a/src/mainboard/google/trogdor/mainboard.c +++ b/src/mainboard/google/trogdor/mainboard.c @@ -13,9 +13,9 @@ * GNU General Public License for more details. */ -#include #include -#include +#include +#include #include #include diff --git a/src/mainboard/google/veyron/bootblock.c b/src/mainboard/google/veyron/bootblock.c index 80fe7e8266..ad5e70944c 100644 --- a/src/mainboard/google/veyron/bootblock.c +++ b/src/mainboard/google/veyron/bootblock.c @@ -42,8 +42,8 @@ void bootblock_mainboard_init(void) reboot_from_watchdog(); /* Up VDD_CPU (BUCK1) to 1.4V to support max CPU frequency (1.8GHz). */ - setbits_le32(&rk3288_pmu->iomux_i2c0scl, IOMUX_I2C0SCL); - setbits_le32(&rk3288_pmu->iomux_i2c0sda, IOMUX_I2C0SDA); + setbits32(&rk3288_pmu->iomux_i2c0scl, IOMUX_I2C0SCL); + setbits32(&rk3288_pmu->iomux_i2c0sda, IOMUX_I2C0SDA); assert(CONFIG_PMIC_BUS == 0); /* must correspond with IOMUX */ i2c_init(CONFIG_PMIC_BUS, 400*KHz); diff --git a/src/mainboard/google/veyron_mickey/bootblock.c b/src/mainboard/google/veyron_mickey/bootblock.c index 1107b1a6a4..ec55f7e452 100644 --- a/src/mainboard/google/veyron_mickey/bootblock.c +++ b/src/mainboard/google/veyron_mickey/bootblock.c @@ -44,8 +44,8 @@ void bootblock_mainboard_init(void) gpio_output(GPIO(7, A, 0), 1); /* Power LED */ /* Up VDD_CPU (BUCK1) to 1.4V to support max CPU frequency (1.8GHz). */ - setbits_le32(&rk3288_pmu->iomux_i2c0scl, IOMUX_I2C0SCL); - setbits_le32(&rk3288_pmu->iomux_i2c0sda, IOMUX_I2C0SDA); + setbits32(&rk3288_pmu->iomux_i2c0scl, IOMUX_I2C0SCL); + setbits32(&rk3288_pmu->iomux_i2c0sda, IOMUX_I2C0SDA); assert(CONFIG_PMIC_BUS == 0); /* must correspond with IOMUX */ i2c_init(CONFIG_PMIC_BUS, 400*KHz); diff --git a/src/mainboard/google/veyron_rialto/bootblock.c b/src/mainboard/google/veyron_rialto/bootblock.c index 91396b0074..2379ae2478 100644 --- a/src/mainboard/google/veyron_rialto/bootblock.c +++ b/src/mainboard/google/veyron_rialto/bootblock.c @@ -48,8 +48,8 @@ void bootblock_mainboard_init(void) gpio_output(GPIO(7, B, 7), 1); /* LED_ERROR */ /* Up VDD_CPU (BUCK1) to 1.4V to support max CPU frequency (1.8GHz). */ - setbits_le32(&rk3288_pmu->iomux_i2c0scl, IOMUX_I2C0SCL); - setbits_le32(&rk3288_pmu->iomux_i2c0sda, IOMUX_I2C0SDA); + setbits32(&rk3288_pmu->iomux_i2c0scl, IOMUX_I2C0SCL); + setbits32(&rk3288_pmu->iomux_i2c0sda, IOMUX_I2C0SDA); assert(CONFIG_PMIC_BUS == 0); /* must correspond with IOMUX */ i2c_init(CONFIG_PMIC_BUS, 400*KHz); diff --git a/src/mainboard/sifive/hifive-unleashed/media.c b/src/mainboard/sifive/hifive-unleashed/media.c index 45d1f1a613..9942912730 100644 --- a/src/mainboard/sifive/hifive-unleashed/media.c +++ b/src/mainboard/sifive/hifive-unleashed/media.c @@ -17,7 +17,7 @@ #include #include #include -#include +#include #include #include #include diff --git a/src/soc/amd/picasso/uart.c b/src/soc/amd/picasso/uart.c index 445862430a..c50de464c7 100644 --- a/src/soc/amd/picasso/uart.c +++ b/src/soc/amd/picasso/uart.c @@ -13,9 +13,9 @@ * GNU General Public License for more details. */ -#include #include #include +#include #include #include #include diff --git a/src/soc/cavium/cn81xx/timer.c b/src/soc/cavium/cn81xx/timer.c index bd67d8a888..be15b9be8e 100644 --- a/src/soc/cavium/cn81xx/timer.c +++ b/src/soc/cavium/cn81xx/timer.c @@ -123,7 +123,7 @@ void init_timer(void) write32(>i->cc_cntrate, ((1ULL << 32) * tickrate) / sclk); /* Enable the counter */ - setbits_le32(>i->cc_cntcr, GTI_CC_CNTCR_EN); + setbits32(>i->cc_cntcr, GTI_CC_CNTCR_EN); //u32 u = (CNTPS_CTL_EL1_IMASK | CNTPS_CTL_EL1_EN); //BDK_MSR(CNTPS_CTL_EL1, u); @@ -172,11 +172,11 @@ void watchdog_set(const size_t index, unsigned int timeout_ms) printk(BIOS_DEBUG, "Watchdog: Set to expire %llu SCLK cycles\n", timeout_wdog << 18); - clrsetbits_le64(&timer->cwd_wdog[index], - (GTI_CWD_WDOG_LEN_MASK << GTI_CWD_WDOG_LEN_SHIFT) | - (GTI_CWD_WDOG_MODE_MASK << GTI_CWD_WDOG_MODE_SHIFT), - (timeout_wdog << GTI_CWD_WDOG_LEN_SHIFT) | - (3 << GTI_CWD_WDOG_MODE_SHIFT)); + clrsetbits64(&timer->cwd_wdog[index], + (GTI_CWD_WDOG_LEN_MASK << GTI_CWD_WDOG_LEN_SHIFT) | + (GTI_CWD_WDOG_MODE_MASK << GTI_CWD_WDOG_MODE_SHIFT), + (timeout_wdog << GTI_CWD_WDOG_LEN_SHIFT) | + (3 << GTI_CWD_WDOG_MODE_SHIFT)); } /** diff --git a/src/soc/mediatek/common/ddp.c b/src/soc/mediatek/common/ddp.c index 173fa90cd7..8f1f0e64ac 100644 --- a/src/soc/mediatek/common/ddp.c +++ b/src/soc/mediatek/common/ddp.c @@ -31,7 +31,7 @@ void ovl_set_roi(u32 idx, u32 width, u32 height, u32 color) void rdma_start(void) { - setbits_le32(&disp_rdma0->global_con, RDMA_ENGINE_EN); + setbits32(&disp_rdma0->global_con, RDMA_ENGINE_EN); } void rdma_config(u32 width, u32 height, u32 pixel_clk, u32 fifo_size) @@ -39,8 +39,8 @@ void rdma_config(u32 width, u32 height, u32 pixel_clk, u32 fifo_size) u32 threshold; u32 reg; - clrsetbits_le32(&disp_rdma0->size_con_0, 0x1FFF, width); - clrsetbits_le32(&disp_rdma0->size_con_1, 0xFFFFF, height); + clrsetbits32(&disp_rdma0->size_con_0, 0x1FFF, width); + clrsetbits32(&disp_rdma0->size_con_1, 0xFFFFF, height); /* * Enable FIFO underflow since DSI and DPI can't be blocked. Set the @@ -78,5 +78,5 @@ void ovl_layer_config(u32 fmt, u32 bpp, u32 width, u32 height) write32(&ovl0->rdma[0].ctrl, BIT(0)); write32(&ovl0->rdma[0].mem_gmc_setting, RDMA_MEM_GMC); - setbits_le32(&ovl0->src_con, BIT(0)); + setbits32(&ovl0->src_con, BIT(0)); } diff --git a/src/soc/mediatek/common/dsi.c b/src/soc/mediatek/common/dsi.c index d60abdb964..238b1eb47f 100644 --- a/src/soc/mediatek/common/dsi.c +++ b/src/soc/mediatek/common/dsi.c @@ -120,12 +120,12 @@ static void mtk_dsi_phy_timing(int data_rate, struct mtk_phy_timing *phy_timing) static void mtk_dsi_clk_hs_mode_enable(void) { - setbits_le32(&dsi0->dsi_phy_lccon, LC_HS_TX_EN); + setbits32(&dsi0->dsi_phy_lccon, LC_HS_TX_EN); } static void mtk_dsi_clk_hs_mode_disable(void) { - clrbits_le32(&dsi0->dsi_phy_lccon, LC_HS_TX_EN); + clrbits32(&dsi0->dsi_phy_lccon, LC_HS_TX_EN); } static void mtk_dsi_set_mode(u32 mode_flags) @@ -394,8 +394,8 @@ static void mtk_dsi_send_init_commands(const u8 *buf) static void mtk_dsi_reset_dphy(void) { - setbits_le32(&dsi0->dsi_con_ctrl, DPHY_RESET); - clrbits_le32(&dsi0->dsi_con_ctrl, DPHY_RESET); + setbits32(&dsi0->dsi_con_ctrl, DPHY_RESET); + clrbits32(&dsi0->dsi_con_ctrl, DPHY_RESET); } int mtk_dsi_init(u32 mode_flags, u32 format, u32 lanes, const struct edid *edid, diff --git a/src/soc/mediatek/common/gpio.c b/src/soc/mediatek/common/gpio.c index 3a1a202d4d..84ba0e2e99 100644 --- a/src/soc/mediatek/common/gpio.c +++ b/src/soc/mediatek/common/gpio.c @@ -63,8 +63,7 @@ void gpio_set_mode(gpio_t gpio, int mode) pos_bit_calc_for_mode(gpio, &pos, &bit); - clrsetbits_le32(&mtk_gpio->mode[pos].val, - mask << bit, mode << bit); + clrsetbits32(&mtk_gpio->mode[pos].val, mask << bit, mode << bit); } int gpio_get(gpio_t gpio) diff --git a/src/soc/mediatek/common/mtcmos.c b/src/soc/mediatek/common/mtcmos.c index fa0b23a353..fbc2d7dfe7 100644 --- a/src/soc/mediatek/common/mtcmos.c +++ b/src/soc/mediatek/common/mtcmos.c @@ -46,17 +46,17 @@ static void mtcmos_power_on(const struct power_domain_data *pd) write32(&mtk_spm->poweron_config_set, (SPM_PROJECT_CODE << 16) | (1U << 0)); - setbits_le32(pd->pwr_con, PWR_ON); - setbits_le32(pd->pwr_con, PWR_ON_2ND); + setbits32(pd->pwr_con, PWR_ON); + setbits32(pd->pwr_con, PWR_ON_2ND); while (!(read32(&mtk_spm->pwr_status) & pd->pwr_sta_mask) || !(read32(&mtk_spm->pwr_status_2nd) & pd->pwr_sta_mask)) continue; - clrbits_le32(pd->pwr_con, PWR_CLK_DIS); - clrbits_le32(pd->pwr_con, PWR_ISO); - setbits_le32(pd->pwr_con, PWR_RST_B); - clrbits_le32(pd->pwr_con, pd->sram_pdn_mask); + clrbits32(pd->pwr_con, PWR_CLK_DIS); + clrbits32(pd->pwr_con, PWR_ISO); + setbits32(pd->pwr_con, PWR_RST_B); + clrbits32(pd->pwr_con, pd->sram_pdn_mask); while (read32(pd->pwr_con) & pd->sram_ack_mask) continue; diff --git a/src/soc/mediatek/common/spi.c b/src/soc/mediatek/common/spi.c index 2a668fe349..9271d6e6dc 100644 --- a/src/soc/mediatek/common/spi.c +++ b/src/soc/mediatek/common/spi.c @@ -50,8 +50,8 @@ static inline struct mtk_spi_bus *to_mtk_spi(const struct spi_slave *slave) static void spi_sw_reset(struct mtk_spi_regs *regs) { - setbits_le32(®s->spi_cmd_reg, SPI_CMD_RST_EN); - clrbits_le32(®s->spi_cmd_reg, SPI_CMD_RST_EN); + setbits32(®s->spi_cmd_reg, SPI_CMD_RST_EN); + clrbits32(®s->spi_cmd_reg, SPI_CMD_RST_EN); } void mtk_spi_init(unsigned int bus, enum spi_pad_mask pad_select, @@ -77,17 +77,17 @@ void mtk_spi_init(unsigned int bus, enum spi_pad_mask pad_select, mtk_spi_set_timing(regs, sck_ticks, cs_ticks, tick_dly); - clrsetbits_le32(®s->spi_cmd_reg, - (SPI_CMD_CPHA_EN | SPI_CMD_CPOL_EN | - SPI_CMD_TX_ENDIAN_EN | SPI_CMD_RX_ENDIAN_EN | - SPI_CMD_TX_DMA_EN | SPI_CMD_RX_DMA_EN | - SPI_CMD_PAUSE_EN | SPI_CMD_DEASSERT_EN), - (SPI_CMD_TXMSBF_EN | SPI_CMD_RXMSBF_EN | - SPI_CMD_FINISH_IE_EN | SPI_CMD_PAUSE_IE_EN)); + clrsetbits32(®s->spi_cmd_reg, + (SPI_CMD_CPHA_EN | SPI_CMD_CPOL_EN | + SPI_CMD_TX_ENDIAN_EN | SPI_CMD_RX_ENDIAN_EN | + SPI_CMD_TX_DMA_EN | SPI_CMD_RX_DMA_EN | + SPI_CMD_PAUSE_EN | SPI_CMD_DEASSERT_EN), + (SPI_CMD_TXMSBF_EN | SPI_CMD_RXMSBF_EN | + SPI_CMD_FINISH_IE_EN | SPI_CMD_PAUSE_IE_EN)); mtk_spi_set_gpio_pinmux(bus, pad_select); - clrsetbits_le32(®s->spi_pad_macro_sel_reg, SPI_PAD_SEL_MASK, + clrsetbits32(®s->spi_pad_macro_sel_reg, SPI_PAD_SEL_MASK, pad_select); gpio_output(slave->cs_gpio, 1); @@ -110,7 +110,7 @@ static int spi_ctrlr_claim_bus(const struct spi_slave *slave) struct mtk_spi_bus *mtk_slave = to_mtk_spi(slave); struct mtk_spi_regs *regs = mtk_slave->regs; - setbits_le32(®s->spi_cmd_reg, 1 << SPI_CMD_PAUSE_EN_SHIFT); + setbits32(®s->spi_cmd_reg, 1 << SPI_CMD_PAUSE_EN_SHIFT); mtk_slave->state = MTK_SPI_IDLE; gpio_output(mtk_slave->cs_gpio, 0); @@ -135,10 +135,10 @@ static int do_transfer(const struct spi_slave *slave, void *in, const void *out, else size = MIN(*bytes_in, *bytes_out); - clrsetbits_le32(®s->spi_cfg1_reg, - SPI_CFG1_PACKET_LENGTH_MASK | SPI_CFG1_PACKET_LOOP_MASK, - ((size - 1) << SPI_CFG1_PACKET_LENGTH_SHIFT) | - (0 << SPI_CFG1_PACKET_LOOP_SHIFT)); + clrsetbits32(®s->spi_cfg1_reg, + SPI_CFG1_PACKET_LENGTH_MASK | SPI_CFG1_PACKET_LOOP_MASK, + ((size - 1) << SPI_CFG1_PACKET_LENGTH_SHIFT) | + (0 << SPI_CFG1_PACKET_LOOP_SHIFT)); if (*bytes_out) { const uint8_t *outb = (const uint8_t *)out; @@ -166,10 +166,10 @@ static int do_transfer(const struct spi_slave *slave, void *in, const void *out, } if (mtk_slave->state == MTK_SPI_IDLE) { - setbits_le32(®s->spi_cmd_reg, SPI_CMD_ACT_EN); + setbits32(®s->spi_cmd_reg, SPI_CMD_ACT_EN); mtk_slave->state = MTK_SPI_PAUSE_IDLE; } else if (mtk_slave->state == MTK_SPI_PAUSE_IDLE) { - setbits_le32(®s->spi_cmd_reg, SPI_CMD_RESUME_EN); + setbits32(®s->spi_cmd_reg, SPI_CMD_RESUME_EN); } stopwatch_init_usecs_expire(&sw, MTK_TXRX_TIMEOUT_US); @@ -246,7 +246,7 @@ static void spi_ctrlr_release_bus(const struct spi_slave *slave) struct mtk_spi_bus *mtk_slave = to_mtk_spi(slave); struct mtk_spi_regs *regs = mtk_slave->regs; - clrbits_le32(®s->spi_cmd_reg, SPI_CMD_PAUSE_EN); + clrbits32(®s->spi_cmd_reg, SPI_CMD_PAUSE_EN); spi_sw_reset(regs); mtk_slave->state = MTK_SPI_IDLE; diff --git a/src/soc/mediatek/common/timer.c b/src/soc/mediatek/common/timer.c index c8af2be113..6fc2ab2fe9 100644 --- a/src/soc/mediatek/common/timer.c +++ b/src/soc/mediatek/common/timer.c @@ -48,8 +48,8 @@ void init_timer(void) timer_prepare(); /* Disable timer and clear the counter */ - clrbits_le32(&mtk_gpt->gpt6_con, GPT_CON_EN); - setbits_le32(&mtk_gpt->gpt6_con, GPT_CON_CLR); + clrbits32(&mtk_gpt->gpt6_con, GPT_CON_EN); + setbits32(&mtk_gpt->gpt6_con, GPT_CON_CLR); /* Set clock source to system clock and set clock divider to 1 */ write32(&mtk_gpt->gpt6_clk, GPT_SYS_CLK | GPT_CLK_DIV1); diff --git a/src/soc/mediatek/common/usb.c b/src/soc/mediatek/common/usb.c index 328bf66e0f..d80cfe98b3 100644 --- a/src/soc/mediatek/common/usb.c +++ b/src/soc/mediatek/common/usb.c @@ -32,53 +32,53 @@ static void phy_index_power_on(int index) if (!index) { /* Set RG_SSUSB_VUSB10_ON as 1 after VUSB10 ready */ - setbits_le32(&phy->u3phya.phya_reg0, P3A_RG_U3_VUSB10_ON); + setbits32(&phy->u3phya.phya_reg0, P3A_RG_U3_VUSB10_ON); /* Disable power domain ISO */ - clrbits_le32(&phy->u2phy.usbphyacr6, PA6_RG_U2_ISO_EN); + clrbits32(&phy->u2phy.usbphyacr6, PA6_RG_U2_ISO_EN); } /* Switch system IP to USB mode */ - clrbits_le32(&phy->u2phy.u2phydtm0, P2C_FORCE_UART_EN); - clrbits_le32(&phy->u2phy.u2phydtm1, P2C_RG_UART_EN); + clrbits32(&phy->u2phy.u2phydtm0, P2C_FORCE_UART_EN); + clrbits32(&phy->u2phy.u2phydtm1, P2C_RG_UART_EN); if (!index) - clrbits_le32(&phy->u2phy.u2phyacr4, P2C_U2_GPIO_CTR_MSK); + clrbits32(&phy->u2phy.u2phyacr4, P2C_U2_GPIO_CTR_MSK); /* Disable force settings */ - clrbits_le32(&phy->u2phy.u2phydtm0, P2C_FORCE_SUSPENDM | + clrbits32(&phy->u2phy.u2phydtm0, P2C_FORCE_SUSPENDM | P2C_RG_XCVRSEL | P2C_RG_DATAIN | P2C_DTM0_PART_MASK); - clrbits_le32(&phy->u2phy.usbphyacr6, PA6_RG_U2_BC11_SW_EN); + clrbits32(&phy->u2phy.usbphyacr6, PA6_RG_U2_BC11_SW_EN); /* Improve Rx sensitivity */ - clrsetbits_le32(&phy->u2phy.usbphyacr6, + clrsetbits32(&phy->u2phy.usbphyacr6, PA6_RG_U2_SQTH, PA6_RG_U2_SQTH_VAL(2)); - setbits_le32(&phy->u2phy.usbphyacr6, PA6_RG_U2_OTG_VBUSCMP_EN); + setbits32(&phy->u2phy.usbphyacr6, PA6_RG_U2_OTG_VBUSCMP_EN); - clrsetbits_le32(&phy->u3phya_da.reg0, + clrsetbits32(&phy->u3phya_da.reg0, P3A_RG_XTAL_EXT_EN_U3, P3A_RG_XTAL_EXT_EN_U3_VAL(2)); - clrsetbits_le32(&phy->u3phya.phya_reg9, + clrsetbits32(&phy->u3phya.phya_reg9, P3A_RG_RX_DAC_MUX, P3A_RG_RX_DAC_MUX_VAL(4)); if (!index) - clrbits_le32(&phy->u2phy.usbphyacr5, PA5_RG_U2_HS_100U_U3_EN); + clrbits32(&phy->u2phy.usbphyacr5, PA5_RG_U2_HS_100U_U3_EN); - clrsetbits_le32(&phy->u3phya.phya_reg6, + clrsetbits32(&phy->u3phya.phya_reg6, P3A_RG_TX_EIDLE_CM, P3A_RG_TX_EIDLE_CM_VAL(0xe)); - clrsetbits_le32(&phy->u3phyd.phyd_cdr1, + clrsetbits32(&phy->u3phyd.phyd_cdr1, P3D_RG_CDR_BIR_LTD0, P3D_RG_CDR_BIR_LTD0_VAL(0xc)); - clrsetbits_le32(&phy->u3phyd.phyd_cdr1, + clrsetbits32(&phy->u3phyd.phyd_cdr1, P3D_RG_CDR_BIR_LTD1, P3D_RG_CDR_BIR_LTD1_VAL(0x3)); - clrsetbits_le32(&phy->u2phy.u2phydtm1, + clrsetbits32(&phy->u2phy.u2phydtm1, P2C_RG_SESSEND, P2C_RG_VBUSVALID | P2C_RG_AVALID); /* Set USB 2.0 slew rate value */ - clrsetbits_le32(&phy->u2phy.usbphyacr5, + clrsetbits32(&phy->u2phy.usbphyacr5, PA5_RG_U2_HSTX_SRCTRL, PA5_RG_U2_HSTX_SRCTRL_VAL(4)); /* Set USB 2.0 disconnect threshold */ - clrsetbits_le32(&phy->u2phy.usbphyacr6, + clrsetbits32(&phy->u2phy.usbphyacr6, PA6_RG_U2_DISCTH, PA6_RG_U2_DISCTH_VAL(15)); } @@ -128,18 +128,18 @@ static int u3phy_ports_enable(void) u3p_msg("%s u2p:%d, u3p:%d\n", __func__, u2_port_num, u3_port_num); /* Power on host ip */ - clrbits_le32(&ippc_regs->ip_pw_ctr1, CTRL1_IP_HOST_PDN); + clrbits32(&ippc_regs->ip_pw_ctr1, CTRL1_IP_HOST_PDN); /* Power on and enable all u3 ports */ for (i = 0; i < u3_port_num; i++) { - clrsetbits_le32(&ippc_regs->u3_ctrl_p[i], + clrsetbits32(&ippc_regs->u3_ctrl_p[i], CTRL_U3_PORT_PDN | CTRL_U3_PORT_DIS, CTRL_U3_PORT_HOST_SEL); } /* Power on and enable all u2 ports */ for (i = 0; i < u2_port_num; i++) { - clrsetbits_le32(&ippc_regs->u2_ctrl_p[i], + clrsetbits32(&ippc_regs->u2_ctrl_p[i], CTRL_U2_PORT_PDN | CTRL_U2_PORT_DIS, CTRL_U2_PORT_HOST_SEL); } @@ -149,8 +149,8 @@ static int u3phy_ports_enable(void) static inline void ssusb_soft_reset(void) { /* Reset whole ip */ - setbits_le32(&ippc_regs->ip_pw_ctr0, CTRL0_IP_SW_RST); - clrbits_le32(&ippc_regs->ip_pw_ctr0, CTRL0_IP_SW_RST); + setbits32(&ippc_regs->ip_pw_ctr0, CTRL0_IP_SW_RST); + clrbits32(&ippc_regs->ip_pw_ctr0, CTRL0_IP_SW_RST); } __weak void mtk_usb_prepare(void) { /* do nothing */ } diff --git a/src/soc/mediatek/common/wdt.c b/src/soc/mediatek/common/wdt.c index 54ce8c0077..7d42493f84 100644 --- a/src/soc/mediatek/common/wdt.c +++ b/src/soc/mediatek/common/wdt.c @@ -45,10 +45,10 @@ int mtk_wdt_init(void) * ENABLE: disable watchdog on initialization. * Setting bit EXTEN to enable watchdog output. */ - clrsetbits_le32(&mtk_wdt->wdt_mode, - MTK_WDT_MODE_DUAL_MODE | MTK_WDT_MODE_IRQ | - MTK_WDT_MODE_EXT_POL | MTK_WDT_MODE_ENABLE, - MTK_WDT_MODE_EXTEN | MTK_WDT_MODE_KEY); + clrsetbits32(&mtk_wdt->wdt_mode, + MTK_WDT_MODE_DUAL_MODE | MTK_WDT_MODE_IRQ | + MTK_WDT_MODE_EXT_POL | MTK_WDT_MODE_ENABLE, + MTK_WDT_MODE_EXTEN | MTK_WDT_MODE_KEY); return wdt_sta; } diff --git a/src/soc/mediatek/mt8173/ddp.c b/src/soc/mediatek/mt8173/ddp.c index 9f201fd0d4..555bfe905f 100644 --- a/src/soc/mediatek/mt8173/ddp.c +++ b/src/soc/mediatek/mt8173/ddp.c @@ -60,17 +60,17 @@ static void main_disp_path_setup(u32 width, u32 height, u32 pixel_clk) static void disp_clock_on(void) { - clrbits_le32(&mmsys_cfg->mmsys_cg_con0, CG_CON0_SMI_COMMON | - CG_CON0_SMI_LARB0 | - CG_CON0_MUTEX_32K | - CG_CON0_DISP_OVL0 | - CG_CON0_DISP_RDMA0 | - CG_CON0_DISP_COLOR0 | - CG_CON0_DISP_UFOE | - CG_CON0_DISP_OD); + clrbits32(&mmsys_cfg->mmsys_cg_con0, CG_CON0_SMI_COMMON | + CG_CON0_SMI_LARB0 | + CG_CON0_MUTEX_32K | + CG_CON0_DISP_OVL0 | + CG_CON0_DISP_RDMA0 | + CG_CON0_DISP_COLOR0 | + CG_CON0_DISP_UFOE | + CG_CON0_DISP_OD); - clrbits_le32(&mmsys_cfg->mmsys_cg_con1, CG_CON1_DSI0_ENGINE | - CG_CON1_DSI0_DIGITAL); + clrbits32(&mmsys_cfg->mmsys_cg_con1, CG_CON1_DSI0_ENGINE | + CG_CON1_DSI0_DIGITAL); } void mtk_ddp_init(void) diff --git a/src/soc/mediatek/mt8173/dramc_pi_basic_api.c b/src/soc/mediatek/mt8173/dramc_pi_basic_api.c index f9bd5073ca..58dce72e94 100644 --- a/src/soc/mediatek/mt8173/dramc_pi_basic_api.c +++ b/src/soc/mediatek/mt8173/dramc_pi_basic_api.c @@ -74,17 +74,17 @@ static void mem_pll_pre_init(u32 channel) write32(&ch[channel].ddrphy_regs->mempll05_divider, 0x1 << 27); /* enable chip top memory clock */ - setbits_le32(&ch[channel].ddrphy_regs->mempll_divider, 0x1 << 4); + setbits32(&ch[channel].ddrphy_regs->mempll_divider, 0x1 << 4); /* disable C/A and DQ M_CK clock gating */ - clrbits_le32(&ch[channel].ddrphy_regs->ddrphy_cg_ctrl, 0x1 << 2 | - 0x1 << 1); + clrbits32(&ch[channel].ddrphy_regs->ddrphy_cg_ctrl, 0x1 << 2 | + 0x1 << 1); /* enable spm control clock */ - clrbits_le32(&ch[channel].ddrphy_regs->mempll_divider, 0x1 << 15 | - 0x1 << 0); + clrbits32(&ch[channel].ddrphy_regs->mempll_divider, 0x1 << 15 | + 0x1 << 0); /* enable dramc 2X mode */ - setbits_le32(&ch[channel].ao_regs->ddr2ctl, 1 << 0); + setbits32(&ch[channel].ao_regs->ddr2ctl, 1 << 0); /* select internal clock path */ write32(&ch[channel].ddrphy_regs->peri[0], 0x21 << 24 | 0x27 << 16 | @@ -94,12 +94,12 @@ static void mem_pll_pre_init(u32 channel) 0x6 << 8 | 0x1e << 0); /* trigger to make memory clock correct phase */ - setbits_le32(&ch[channel].ddrphy_regs->mempll_divider, 0x1 << 24 | - 0x1 << 7); + setbits32(&ch[channel].ddrphy_regs->mempll_divider, 0x1 << 24 | + 0x1 << 7); if (channel == CHANNEL_A) { /* select memory clock sync for channel A (internal source) */ - clrbits_le32(&ch[channel].ddrphy_regs->mempll_divider, 0x1 << 3); + clrbits32(&ch[channel].ddrphy_regs->mempll_divider, 0x1 << 3); } } @@ -156,11 +156,11 @@ static void mem_pll_init_phase_sync(u32 channel) BIT(7) | BIT(5) | BIT(4) | BIT(0)); /* spm control clock enable */ - clrsetbits_le32(&ch[channel].ddrphy_regs->mempll_divider, BIT(0), - BIT(1)); + clrsetbits32(&ch[channel].ddrphy_regs->mempll_divider, BIT(0), + BIT(1)); - clrsetbits_le32(&ch[channel].ddrphy_regs->mempll_divider, BIT(1), - BIT(0)); + clrsetbits32(&ch[channel].ddrphy_regs->mempll_divider, BIT(1), + BIT(0)); } static void pll_phase_adjust(u32 channel, struct mem_pll *mempll, int reg_offs) @@ -169,25 +169,25 @@ static void pll_phase_adjust(u32 channel, struct mem_pll *mempll, int reg_offs) case MEMPLL_INIT: /* initial phase: zero out RG_MEPLL(2,3,4)_(REF_DL,FB)_DL */ - clrbits_le32(&ch[channel].ddrphy_regs->mempll[reg_offs], - 0x1f << MEMPLL_REF_DL_SHIFT | - 0x1f << MEMPLL_FB_DL_SHIFT); + clrbits32(&ch[channel].ddrphy_regs->mempll[reg_offs], + 0x1f << MEMPLL_REF_DL_SHIFT | + 0x1f << MEMPLL_FB_DL_SHIFT); break; case MEMPLL_REF_LAG: /* REF lag FBK, delay FBK */ - clrsetbits_le32(&ch[channel].ddrphy_regs->mempll[reg_offs], - 0x1f << MEMPLL_REF_DL_SHIFT | - 0x1f << MEMPLL_FB_DL_SHIFT, - mempll->delay << MEMPLL_FB_DL_SHIFT); + clrsetbits32(&ch[channel].ddrphy_regs->mempll[reg_offs], + 0x1f << MEMPLL_REF_DL_SHIFT | + 0x1f << MEMPLL_FB_DL_SHIFT, + mempll->delay << MEMPLL_FB_DL_SHIFT); break; case MEMPLL_REF_LEAD: /* REF lead FBK, delay REF */ - clrsetbits_le32(&ch[channel].ddrphy_regs->mempll[reg_offs], - 0x1f << MEMPLL_REF_DL_SHIFT | - 0x1f << MEMPLL_FB_DL_SHIFT, - mempll->delay << MEMPLL_REF_DL_SHIFT); + clrsetbits32(&ch[channel].ddrphy_regs->mempll[reg_offs], + 0x1f << MEMPLL_REF_DL_SHIFT | + 0x1f << MEMPLL_FB_DL_SHIFT, + mempll->delay << MEMPLL_REF_DL_SHIFT); }; } @@ -250,9 +250,9 @@ static void mem_pll_phase_cali(u32 channel) /* 1. set jitter meter count number to 1024 for mempll 2 3 4 */ for (i = 0; i < 3; i++) - clrsetbits_le32(&ch[channel].ddrphy_regs->jmeter[i], - JMETER_COUNTER_MASK, - JMETER_COUNT << JMETER_COUNTER_SHIFT); + clrsetbits32(&ch[channel].ddrphy_regs->jmeter[i], + JMETER_COUNTER_MASK, + JMETER_COUNT << JMETER_COUNTER_SHIFT); while (1) { @@ -266,8 +266,8 @@ static void mem_pll_phase_cali(u32 channel) /* 2. enable mempll 2 3 4 jitter meter */ for (i = 0; i < 3; i++) - setbits_le32(&ch[channel].ddrphy_regs->jmeter[i], - JMETER_EN_BIT); + setbits32(&ch[channel].ddrphy_regs->jmeter[i], + JMETER_EN_BIT); /* 3. wait for jitter meter complete */ udelay(JMETER_WAIT_DONE_US); @@ -281,8 +281,8 @@ static void mem_pll_phase_cali(u32 channel) /* 5. disable mempll 2 3 4 jitter meter */ for (i = 0; i < 3; i++) - clrbits_le32(&ch[channel].ddrphy_regs->jmeter[i], - JMETER_EN_BIT); + clrbits32(&ch[channel].ddrphy_regs->jmeter[i], + JMETER_EN_BIT); /* 6. all done early break */ if (mempll[0].done && mempll[1].done && mempll[2].done) @@ -336,58 +336,58 @@ void mem_pll_init(const struct mt8173_sdram_params *sdram_params) udelay(2); /* mempll2_en -> mempll4_en -> mempll3_en */ - setbits_le32(&ch[channel].ddrphy_regs->mempll[5], 1 << 0); - setbits_le32(&ch[channel].ddrphy_regs->mempll[11], 1 << 0); - setbits_le32(&ch[channel].ddrphy_regs->mempll[8], 1 << 0); + setbits32(&ch[channel].ddrphy_regs->mempll[5], 1 << 0); + setbits32(&ch[channel].ddrphy_regs->mempll[11], 1 << 0); + setbits32(&ch[channel].ddrphy_regs->mempll[8], 1 << 0); udelay(100); /* mempll_bias_lpf_en */ - setbits_le32(&ch[channel].ddrphy_regs->mempll[3], 1 << 7); + setbits32(&ch[channel].ddrphy_regs->mempll[3], 1 << 7); udelay(30); /* select mempll4 band register */ - setbits_le32(&ch[channel].ddrphy_regs->mempll[4], 1 << 26); - clrbits_le32(&ch[channel].ddrphy_regs->mempll[4], 1 << 26); + setbits32(&ch[channel].ddrphy_regs->mempll[4], 1 << 26); + clrbits32(&ch[channel].ddrphy_regs->mempll[4], 1 << 26); /* PLL ready */ /* disable mempll2_en -> mempll4_en -> mempll3_en */ - clrbits_le32(&ch[channel].ddrphy_regs->mempll[5], 1 << 0); - clrbits_le32(&ch[channel].ddrphy_regs->mempll[11], 1 << 0); - clrbits_le32(&ch[channel].ddrphy_regs->mempll[8], 1 << 0); + clrbits32(&ch[channel].ddrphy_regs->mempll[5], 1 << 0); + clrbits32(&ch[channel].ddrphy_regs->mempll[11], 1 << 0); + clrbits32(&ch[channel].ddrphy_regs->mempll[8], 1 << 0); /* disable autok mempll2_en -> mempll4_en -> mempll3_en */ - clrbits_le32(&ch[channel].ddrphy_regs->mempll[5], 1 << 23); - clrbits_le32(&ch[channel].ddrphy_regs->mempll[11], 1 << 23); - clrbits_le32(&ch[channel].ddrphy_regs->mempll[8], 1 << 23); + clrbits32(&ch[channel].ddrphy_regs->mempll[5], 1 << 23); + clrbits32(&ch[channel].ddrphy_regs->mempll[11], 1 << 23); + clrbits32(&ch[channel].ddrphy_regs->mempll[8], 1 << 23); udelay(1); /* mempll[2->4->3]_fb_mck_sel=1 (switch to outer loop) */ - setbits_le32(&ch[channel].ddrphy_regs->mempll[6], 1 << 25); - setbits_le32(&ch[channel].ddrphy_regs->mempll[12], 1 << 25); - setbits_le32(&ch[channel].ddrphy_regs->mempll[9], 1 << 25); + setbits32(&ch[channel].ddrphy_regs->mempll[6], 1 << 25); + setbits32(&ch[channel].ddrphy_regs->mempll[12], 1 << 25); + setbits32(&ch[channel].ddrphy_regs->mempll[9], 1 << 25); udelay(1); /* enable mempll2_en -> mempll4_en -> mempll3_en */ - setbits_le32(&ch[channel].ddrphy_regs->mempll[5], 1 << 0); - setbits_le32(&ch[channel].ddrphy_regs->mempll[11], 1 << 0); - setbits_le32(&ch[channel].ddrphy_regs->mempll[8], 1 << 0); + setbits32(&ch[channel].ddrphy_regs->mempll[5], 1 << 0); + setbits32(&ch[channel].ddrphy_regs->mempll[11], 1 << 0); + setbits32(&ch[channel].ddrphy_regs->mempll[8], 1 << 0); } /* mempll new power-on */ write32(&mtk_spm->poweron_config_set, 0x1 << 0 | SPM_PROJECT_CODE << 16); /* request mempll reset/pdn mode */ - setbits_le32(&mtk_spm->power_on_val0, 0x1 << 27); + setbits32(&mtk_spm->power_on_val0, 0x1 << 27); udelay(2); /* unrequest mempll reset/pdn mode and wait settle */ - clrbits_le32(&mtk_spm->power_on_val0, 0x1 << 27); + clrbits32(&mtk_spm->power_on_val0, 0x1 << 27); udelay(31); /* PLL ready */ @@ -628,16 +628,16 @@ void dramc_init(u32 channel, const struct mt8173_sdram_params *sdram_params) write32(&ch[channel].ao_regs->padctl7, 0x0); /* CLKTDN, DS0TDN, DS1TDN, DS2TDN, DS3TDN */ - setbits_le32(&ch[channel].ddrphy_regs->tdsel[2], 0x1 << 31 | + setbits32(&ch[channel].ddrphy_regs->tdsel[2], 0x1 << 31 | 0x1 << 29 | 0x1 << 27 | 0x1 << 25 | 0x1 << 1); /* DISABLE_PERBANK_REFRESH */ - clrbits_le32(&ch[channel].ao_regs->rkcfg, 0x1 << 7); + clrbits32(&ch[channel].ao_regs->rkcfg, 0x1 << 7); /* clear R_DMREFTHD to reduce MR4 wait refresh queue time */ - clrbits_le32(&ch[channel].ao_regs->conf2, 0x7 << 24); + clrbits32(&ch[channel].ao_regs->conf2, 0x7 << 24); /* duty default value */ write32(&ch[channel].ddrphy_regs->phyclkduty, 0x1 << 28 | @@ -645,7 +645,7 @@ void dramc_init(u32 channel, const struct mt8173_sdram_params *sdram_params) if (!dual_rank_set) { /* single rank, CKE1 always off */ - setbits_le32(&ch[channel].ao_regs->gddr3ctl1, 0x1 << 21); + setbits32(&ch[channel].ao_regs->gddr3ctl1, 0x1 << 21); } /* default dqs rx perbit input delay */ @@ -662,72 +662,72 @@ void dramc_init(u32 channel, const struct mt8173_sdram_params *sdram_params) void div2_phase_sync(void) { - clrbits_le32(&ch[CHANNEL_B].ddrphy_regs->mempll_divider, + clrbits32(&ch[CHANNEL_B].ddrphy_regs->mempll_divider, 1 << MEMCLKENB_SHIFT); udelay(1); - setbits_le32(&ch[CHANNEL_B].ddrphy_regs->mempll_divider, + setbits32(&ch[CHANNEL_B].ddrphy_regs->mempll_divider, 1 << MEMCLKENB_SHIFT); } void dramc_phy_reset(u32 channel) { /* reset phy */ - setbits_le32(&ch[channel].ddrphy_regs->phyctl1, + setbits32(&ch[channel].ddrphy_regs->phyctl1, 1 << PHYCTL1_PHYRST_SHIFT); /* read data counter reset */ - setbits_le32(&ch[channel].ao_regs->gddr3ctl1, + setbits32(&ch[channel].ao_regs->gddr3ctl1, 1 << GDDR3CTL1_RDATRST_SHIFT); udelay(1); /* delay 1ns */ - clrbits_le32(&ch[channel].ao_regs->gddr3ctl1, + clrbits32(&ch[channel].ao_regs->gddr3ctl1, 1 << GDDR3CTL1_RDATRST_SHIFT); - clrbits_le32(&ch[channel].ddrphy_regs->phyctl1, + clrbits32(&ch[channel].ddrphy_regs->phyctl1, 1 << PHYCTL1_PHYRST_SHIFT); } void dramc_runtime_config(u32 channel, const struct mt8173_sdram_params *sdram_params) { - setbits_le32(&ch[channel].ddrphy_regs->dqsgctl, + setbits32(&ch[channel].ddrphy_regs->dqsgctl, BIT(17)|BIT(18)); /* enable hw gating */ - setbits_le32(&ch[channel].ao_regs->dqscal0, - 1 << DQSCAL0_STBCALEN_SHIFT); + setbits32(&ch[channel].ao_regs->dqscal0, + 1 << DQSCAL0_STBCALEN_SHIFT); /* if frequency >1600, tCKE should >7 clk */ - setbits_le32(&ch[channel].ao_regs->dummy, 0x1 << 4); + setbits32(&ch[channel].ao_regs->dummy, 0x1 << 4); if (sdram_params->dram_freq * 2 < 1600 * MHz) die("set tCKE error in runtime config"); /* DDRPHY C/A and DQ M_CK clock gating enable */ - setbits_le32(&ch[channel].ddrphy_regs->ddrphy_cg_ctrl, 0x1 << 2 | + setbits32(&ch[channel].ddrphy_regs->ddrphy_cg_ctrl, 0x1 << 2 | 0x1 << 1); - setbits_le32(&ch[channel].ao_regs->perfctl0, BIT(19) | BIT(14) | + setbits32(&ch[channel].ao_regs->perfctl0, BIT(19) | BIT(14) | BIT(11) | BIT(10) | BIT(9) | BIT(8) | BIT(4) | BIT(0)); /* ZQCS_ENABLE */ if (sdram_params->emi_set.cona & 0x1) { /* dual channel, clear ZQCSCNT */ - clrbits_le32(&ch[channel].ao_regs->spcmd, 0xff << 16); + clrbits32(&ch[channel].ao_regs->spcmd, 0xff << 16); /* set ZQCSMASK for different channels */ if (channel == CHANNEL_A) { - clrbits_le32(&ch[channel].ao_regs->perfctl0, 0x1 << 24); + clrbits32(&ch[channel].ao_regs->perfctl0, 0x1 << 24); } else { - setbits_le32(&ch[channel].ao_regs->perfctl0, 0x1 << 24); + setbits32(&ch[channel].ao_regs->perfctl0, 0x1 << 24); } /* enable ZQCSDUAL */ - setbits_le32(&ch[channel].ao_regs->perfctl0, 0x1 << 25); + setbits32(&ch[channel].ao_regs->perfctl0, 0x1 << 25); } else { /* single channel, set ZQCSCNT */ - setbits_le32(&ch[channel].ao_regs->spcmd, 0x8 << 16); + setbits32(&ch[channel].ao_regs->spcmd, 0x8 << 16); } } @@ -736,17 +736,17 @@ void transfer_to_spm_control(void) u32 msk; msk = BIT(7) | BIT(11) | BIT(15); - clrbits_le32(&mtk_apmixed->ap_pll_con3, msk); + clrbits32(&mtk_apmixed->ap_pll_con3, msk); msk = BIT(0) | BIT(4) | BIT(8); - clrbits_le32(&ch[CHANNEL_A].ddrphy_regs->peri[3], msk); + clrbits32(&ch[CHANNEL_A].ddrphy_regs->peri[3], msk); msk = BIT(0) | BIT(8); - clrbits_le32(&ch[CHANNEL_B].ddrphy_regs->peri[3], msk); + clrbits32(&ch[CHANNEL_B].ddrphy_regs->peri[3], msk); msk = BIT(0) | BIT(9) | BIT(10) | BIT(11) | BIT(16) | BIT(24); - clrbits_le32(&ch[CHANNEL_A].ddrphy_regs->peri[2], msk); - clrbits_le32(&ch[CHANNEL_B].ddrphy_regs->peri[2], msk); + clrbits32(&ch[CHANNEL_A].ddrphy_regs->peri[2], msk); + clrbits32(&ch[CHANNEL_B].ddrphy_regs->peri[2], msk); } void transfer_to_reg_control(void) @@ -754,17 +754,17 @@ void transfer_to_reg_control(void) u32 val; val = BIT(7) | BIT(11) | BIT(15); - setbits_le32(&mtk_apmixed->ap_pll_con3, val); + setbits32(&mtk_apmixed->ap_pll_con3, val); val = BIT(0) | BIT(4) | BIT(8); - setbits_le32(&ch[CHANNEL_A].ddrphy_regs->peri[3], val); + setbits32(&ch[CHANNEL_A].ddrphy_regs->peri[3], val); val = BIT(0) | BIT(8); write32(&ch[CHANNEL_B].ddrphy_regs->peri[3], val); val = BIT(0) | BIT(9) | BIT(10) | BIT(11) | BIT(16) | BIT(24); - setbits_le32(&ch[CHANNEL_A].ddrphy_regs->peri[2], val); - setbits_le32(&ch[CHANNEL_B].ddrphy_regs->peri[2], val); + setbits32(&ch[CHANNEL_A].ddrphy_regs->peri[2], val); + setbits32(&ch[CHANNEL_B].ddrphy_regs->peri[2], val); } u32 dramc_engine2(u32 channel, enum dram_tw_op wr, u32 test2_1, u32 test2_2, @@ -776,9 +776,9 @@ u32 dramc_engine2(u32 channel, enum dram_tw_op wr, u32 test2_1, u32 test2_2, die("Invalid loopcount of engine2!"); /* Disable Test Agent1, Test Agent2 write/read */ - clrbits_le32(&ch[channel].ao_regs->conf2, CONF2_TEST1_EN | - CONF2_TEST2R_EN | - CONF2_TEST2W_EN); + clrbits32(&ch[channel].ao_regs->conf2, CONF2_TEST1_EN | + CONF2_TEST2R_EN | + CONF2_TEST2W_EN); /* 1. set pattern, base address, offset address */ write32(&ch[channel].nao_regs->test2_1, test2_1); @@ -794,49 +794,49 @@ u32 dramc_engine2(u32 channel, enum dram_tw_op wr, u32 test2_1, u32 test2_2, switch (testaudpat) { case XTALK: /* TESTAUDPAT = 0 */ - clrbits_le32(&ch[channel].ao_regs->test2_3, - TEST2_3_TESTAUDPAT_EN); + clrbits32(&ch[channel].ao_regs->test2_3, + TEST2_3_TESTAUDPAT_EN); /* TESTXTALKPAT = 1, select xtalk pattern * TESTAUDMODE = 0, read only * TESTAUDBITINV = 0, no bit inversion */ - clrsetbits_le32(&ch[channel].ao_regs->test2_4, - TEST2_4_TESTAUDBITINV_EN | - TEST2_4_TESTAUDMODE_EN, - TEST2_4_TESTXTALKPAT_EN); + clrsetbits32(&ch[channel].ao_regs->test2_4, + TEST2_4_TESTAUDBITINV_EN | + TEST2_4_TESTAUDMODE_EN, + TEST2_4_TESTXTALKPAT_EN); break; case AUDIO: /* TESTAUDPAT = 1 */ - setbits_le32(&ch[channel].ao_regs->test2_3, - TEST2_3_TESTAUDPAT_EN); + setbits32(&ch[channel].ao_regs->test2_3, + TEST2_3_TESTAUDPAT_EN); /* TESTXTALKPAT = 0 * TESTAUDINIT = 0x11 * TESTAUDINC = 0x0d * TESTAUDBITINV = 1 * TESTAUDMODE = 1 */ - clrsetbits_le32(&ch[channel].ao_regs->test2_4, - TEST2_4_TESTXTALKPAT_EN | - TEST2_4_TESTAUDINIT_MASK | - TEST2_4_TESTAUDINC_MASK, - TEST2_4_TESTAUDMODE_EN | - TEST2_4_TESTAUDBITINV_EN | - 0x11 << TEST2_4_TESTAUDINIT_SHIFT | - 0xd << TEST2_4_TESTAUDINC_SHIFT); + clrsetbits32(&ch[channel].ao_regs->test2_4, + TEST2_4_TESTXTALKPAT_EN | + TEST2_4_TESTAUDINIT_MASK | + TEST2_4_TESTAUDINC_MASK, + TEST2_4_TESTAUDMODE_EN | + TEST2_4_TESTAUDBITINV_EN | + 0x11 << TEST2_4_TESTAUDINIT_SHIFT | + 0xd << TEST2_4_TESTAUDINC_SHIFT); break; case ISI: /* TESTAUDPAT = 0 */ - clrbits_le32(&ch[channel].ao_regs->test2_3, - TEST2_3_TESTAUDPAT_EN); + clrbits32(&ch[channel].ao_regs->test2_3, + TEST2_3_TESTAUDPAT_EN); /* TESTXTALKPAT = 0 */ - clrbits_le32(&ch[channel].ao_regs->test2_4, - TEST2_4_TESTXTALKPAT_EN); + clrbits32(&ch[channel].ao_regs->test2_4, + TEST2_4_TESTXTALKPAT_EN); } /* 3. set loop number */ - clrsetbits_le32(&ch[channel].ao_regs->test2_3, TEST2_3_TESTCNT_MASK, - log2loopcount << TEST2_3_TESTCNT_SHIFT); + clrsetbits32(&ch[channel].ao_regs->test2_3, TEST2_3_TESTCNT_MASK, + log2loopcount << TEST2_3_TESTCNT_SHIFT); /* 4. enable read/write test */ if (wr == TE_OP_READ_CHECK) { @@ -844,15 +844,15 @@ u32 dramc_engine2(u32 channel, enum dram_tw_op wr, u32 test2_1, u32 test2_2, /* if audio pattern, enable read only */ /* (disable write after read), */ /* AUDMODE=0x48[15]=0 */ - clrbits_le32(&ch[channel].ao_regs->test2_4, - TEST2_4_TESTAUDMODE_EN); + clrbits32(&ch[channel].ao_regs->test2_4, + TEST2_4_TESTAUDMODE_EN); } /* enable read, 0x008[30:30] */ - setbits_le32(&ch[channel].ao_regs->conf2, CONF2_TEST2R_EN); + setbits32(&ch[channel].ao_regs->conf2, CONF2_TEST2R_EN); } else if (wr == TE_OP_WRITE_READ_CHECK) { /* enable write, 0x008[31:31] */ - setbits_le32(&ch[channel].ao_regs->conf2, CONF2_TEST2W_EN); + setbits32(&ch[channel].ao_regs->conf2, CONF2_TEST2W_EN); /* check "read data compare ready" bit */ do { @@ -860,8 +860,8 @@ u32 dramc_engine2(u32 channel, enum dram_tw_op wr, u32 test2_1, u32 test2_2, } while ((value & (1 << TESTRPT_DM_CMP_CPT_SHIFT)) == 0); /* Disable Test Agent2 write and enable Test Agent2 read */ - clrbits_le32(&ch[channel].ao_regs->conf2, CONF2_TEST2W_EN); - setbits_le32(&ch[channel].ao_regs->conf2, CONF2_TEST2R_EN); + clrbits32(&ch[channel].ao_regs->conf2, CONF2_TEST2W_EN); + setbits32(&ch[channel].ao_regs->conf2, CONF2_TEST2R_EN); } /* 5 check "read data compare ready" bit */ @@ -876,7 +876,7 @@ u32 dramc_engine2(u32 channel, enum dram_tw_op wr, u32 test2_1, u32 test2_2, value = read32(&ch[channel].nao_regs->cmp_err); /* 6 disable read */ - clrbits_le32(&ch[channel].ao_regs->conf2, CONF2_TEST2R_EN); + clrbits32(&ch[channel].ao_regs->conf2, CONF2_TEST2R_EN); /* return CMP_ERR result, pass: 0, failure: otherwise */ return value; diff --git a/src/soc/mediatek/mt8173/dramc_pi_calibration_api.c b/src/soc/mediatek/mt8173/dramc_pi_calibration_api.c index 0a8e69be1e..a22d7e22d1 100644 --- a/src/soc/mediatek/mt8173/dramc_pi_calibration_api.c +++ b/src/soc/mediatek/mt8173/dramc_pi_calibration_api.c @@ -42,14 +42,14 @@ void sw_impedance_cal(u32 channel, params->impedance_drvp << 12 | params->impedance_drvn << 8; /* DQS and DQ */ - clrsetbits_le32(&ch[channel].ao_regs->iodrv6, mask, value); + clrsetbits32(&ch[channel].ao_regs->iodrv6, mask, value); /* CLK and CMD */ - clrsetbits_le32(&ch[channel].ao_regs->drvctl1, mask, value); - clrsetbits_le32(&ch[channel].ddrphy_regs->drvctl1, mask, value); + clrsetbits32(&ch[channel].ao_regs->drvctl1, mask, value); + clrsetbits32(&ch[channel].ddrphy_regs->drvctl1, mask, value); /* DQ_2 and CMD_2 */ - clrsetbits_le32(&ch[channel].ao_regs->iodrv4, mask, value); + clrsetbits32(&ch[channel].ao_regs->iodrv4, mask, value); /* disable impcal calibration */ - clrbits_le32(&ch[channel].ao_regs->impcal, 1 << IMP_CALI_ENP_SHIFT | + clrbits32(&ch[channel].ao_regs->impcal, 1 << IMP_CALI_ENP_SHIFT | 1 << IMP_CALI_ENN_SHIFT | 1 << IMP_CALI_EN_SHIFT | 0xf << IMP_CALI_DRVP_SHIFT | @@ -89,40 +89,40 @@ void ca_training(u32 channel, const struct mt8173_sdram_params *sdram_params) /* set CA pins output delay */ for (i = 0; i < (CATRAINING_NUM - 1); i++) { order = ca_order[channel][i]; - clrsetbits_le32(&ch[channel].ddrphy_regs->cmddly[cmd_order[i]], - 0xf << shift[i], ca_shift[order] << shift[i]); + clrsetbits32(&ch[channel].ddrphy_regs->cmddly[cmd_order[i]], + 0xf << shift[i], ca_shift[order] << shift[i]); } order = ca_order[channel][9]; - clrsetbits_le32(&ch[channel].ddrphy_regs->dqscal0, - 0xf << DQSCAL0_RA14_SHIFT, - ca_shift[order] << DQSCAL0_RA14_SHIFT); + clrsetbits32(&ch[channel].ddrphy_regs->dqscal0, + 0xf << DQSCAL0_RA14_SHIFT, + ca_shift[order] << DQSCAL0_RA14_SHIFT); /* CKE and CS delay */ ca_shift_avg32 = (u32)(ca_shift_avg8 + (CATRAINING_NUM >> 1)); ca_shift_avg32 /= (u32)CATRAINING_NUM; /* CKEDLY */ - clrsetbits_le32(&ch[channel].ddrphy_regs->cmddly[4], - 0x1f << CMDDLY4_CS_SHIFT | - 0x1f << CMDDLY4_CKE_SHIFT, - ca_shift_avg32 << CMDDLY4_CS_SHIFT | - ca_shift_avg32 << CMDDLY4_CKE_SHIFT); + clrsetbits32(&ch[channel].ddrphy_regs->cmddly[4], + 0x1f << CMDDLY4_CS_SHIFT | + 0x1f << CMDDLY4_CKE_SHIFT, + ca_shift_avg32 << CMDDLY4_CS_SHIFT | + ca_shift_avg32 << CMDDLY4_CKE_SHIFT); /* CKE1DLY */ - clrsetbits_le32(&ch[channel].ao_regs->dqscal1, - 0x1f << DQSCAL1_CKE1_SHIFT, - ca_shift_avg32 << DQSCAL1_CKE1_SHIFT); + clrsetbits32(&ch[channel].ao_regs->dqscal1, + 0x1f << DQSCAL1_CKE1_SHIFT, + ca_shift_avg32 << DQSCAL1_CKE1_SHIFT); /* CS1DLY */ - clrsetbits_le32(&ch[channel].ddrphy_regs->padctl1, - 0xf << PADCTL1_CS1_SHIFT, - ca_shift_avg32 << PADCTL1_CS1_SHIFT); + clrsetbits32(&ch[channel].ddrphy_regs->padctl1, + 0xf << PADCTL1_CS1_SHIFT, + ca_shift_avg32 << PADCTL1_CS1_SHIFT); /* set max center into clk output delay */ - clrsetbits_le32(&ch[channel].ddrphy_regs->padctl1, - 0xf << PADCTL1_CLK_SHIFT, - ca_max_center << PADCTL1_CLK_SHIFT); + clrsetbits32(&ch[channel].ddrphy_regs->padctl1, + 0xf << PADCTL1_CLK_SHIFT, + ca_max_center << PADCTL1_CLK_SHIFT); dramc_dbg_msg("=========================================\n"); dramc_dbg_msg(" [Channel %d] CA training\n", channel); @@ -155,8 +155,8 @@ void write_leveling(u32 channel, const struct mt8173_sdram_params *sdram_params) write32(&ch[channel].ddrphy_regs->padctl3, value); /* DQM */ - clrsetbits_le32(&ch[channel].ddrphy_regs->padctl2, MASK_PADCTL2_32BIT, - (value << PADCTL2_SHIFT) & MASK_PADCTL2_32BIT); + clrsetbits32(&ch[channel].ddrphy_regs->padctl2, MASK_PADCTL2_32BIT, + (value << PADCTL2_SHIFT) & MASK_PADCTL2_32BIT); /* DQ */ for (byte_i = 0; byte_i < DQS_NUMBER; byte_i++) { @@ -203,10 +203,10 @@ static void set_gw_coarse_factor(u32 channel, u8 curr_val) curr_val_p1 = curr_val + 2; /* diff is 0.5T */ /* Rank 0 P0/P1 coarse tune settings */ - clrsetbits_le32(&ch[channel].ao_regs->dqsctl1, - 0xf << DQSCTL1_DQSINCTL_SHIFT, - coarse_tune_start << DQSCTL1_DQSINCTL_SHIFT & - 0xf << DQSCTL1_DQSINCTL_SHIFT); + clrsetbits32(&ch[channel].ao_regs->dqsctl1, + 0xf << DQSCTL1_DQSINCTL_SHIFT, + coarse_tune_start << DQSCTL1_DQSINCTL_SHIFT & + 0xf << DQSCTL1_DQSINCTL_SHIFT); /* DQSINCTL does not have P1. */ /* Need to use TXDLY_DQSGATE/TXDLY_DQSGATE_P1 to set */ @@ -214,33 +214,33 @@ static void set_gw_coarse_factor(u32 channel, u8 curr_val) selph2_dqsgate = (curr_val >> 2) - coarse_tune_start; selph2_dqsgate_p1 = (curr_val_p1 >> 2) - coarse_tune_start; - clrsetbits_le32(&ch[channel].ao_regs->selph2, - 0x7 << SELPH2_TXDLY_DQSGATE_SHIFT | - 0x7 << SELPH2_TXDLY_DQSGATE_P1_SHIFT, - selph2_dqsgate << SELPH2_TXDLY_DQSGATE_SHIFT | - selph2_dqsgate_p1 << SELPH2_TXDLY_DQSGATE_P1_SHIFT); + clrsetbits32(&ch[channel].ao_regs->selph2, + 0x7 << SELPH2_TXDLY_DQSGATE_SHIFT | + 0x7 << SELPH2_TXDLY_DQSGATE_P1_SHIFT, + selph2_dqsgate << SELPH2_TXDLY_DQSGATE_SHIFT | + selph2_dqsgate_p1 << SELPH2_TXDLY_DQSGATE_P1_SHIFT); /* dly_DQSGATE and dly_DQSGATE_P1 */ - clrsetbits_le32(&ch[channel].ao_regs->selph5, - 0x3 << SELPH5_DLY_DQSGATE_SHIFT | - 0x3 << SELPH5_DLY_DQSGATE_P1_SHIFT, - (curr_val & 0x3) << SELPH5_DLY_DQSGATE_SHIFT | - (curr_val_p1 & 0x3) << SELPH5_DLY_DQSGATE_P1_SHIFT); + clrsetbits32(&ch[channel].ao_regs->selph5, + 0x3 << SELPH5_DLY_DQSGATE_SHIFT | + 0x3 << SELPH5_DLY_DQSGATE_P1_SHIFT, + (curr_val & 0x3) << SELPH5_DLY_DQSGATE_SHIFT | + (curr_val_p1 & 0x3) << SELPH5_DLY_DQSGATE_P1_SHIFT); } static void set_gw_fine_factor(u32 channel, u8 curr_val, u8 rank) { u32 set = curr_val & (0x7f << DQSIEN_DQS0IEN_SHIFT); - clrsetbits_le32(&ch[channel].ao_regs->dqsien[rank], - 0x7f << DQSIEN_DQS0IEN_SHIFT | - 0x7f << DQSIEN_DQS1IEN_SHIFT | - 0x7f << DQSIEN_DQS2IEN_SHIFT | - 0x7f << DQSIEN_DQS3IEN_SHIFT, - set << DQSIEN_DQS0IEN_SHIFT | - set << DQSIEN_DQS1IEN_SHIFT | - set << DQSIEN_DQS2IEN_SHIFT | - set << DQSIEN_DQS3IEN_SHIFT); + clrsetbits32(&ch[channel].ao_regs->dqsien[rank], + 0x7f << DQSIEN_DQS0IEN_SHIFT | + 0x7f << DQSIEN_DQS1IEN_SHIFT | + 0x7f << DQSIEN_DQS2IEN_SHIFT | + 0x7f << DQSIEN_DQS3IEN_SHIFT, + set << DQSIEN_DQS0IEN_SHIFT | + set << DQSIEN_DQS1IEN_SHIFT | + set << DQSIEN_DQS2IEN_SHIFT | + set << DQSIEN_DQS3IEN_SHIFT); } static void set_gw_coarse_factor_rank1(u32 channel, u8 curr_val, u8 dqsinctl) @@ -249,33 +249,33 @@ static void set_gw_coarse_factor_rank1(u32 channel, u8 curr_val, u8 dqsinctl) curr_val_p1 = curr_val + 2; /* diff is 0.5T */ - clrsetbits_le32(&ch[channel].ao_regs->dqsctl2, - 0xf << DQSCTL2_DQSINCTL_SHIFT, - dqsinctl << DQSCTL2_DQSINCTL_SHIFT); + clrsetbits32(&ch[channel].ao_regs->dqsctl2, + 0xf << DQSCTL2_DQSINCTL_SHIFT, + dqsinctl << DQSCTL2_DQSINCTL_SHIFT); /* TXDLY_R1DQSGATE and TXDLY_R1DQSGATE_P1 */ r1dqsgate = (curr_val >> 2) - dqsinctl; r1dqsgate_p1 = (curr_val_p1 >> 2) - dqsinctl; - clrsetbits_le32(&ch[channel].ao_regs->selph6_1, - 0x7 << SELPH6_1_TXDLY_R1DQSGATE_SHIFT | - 0x7 << SELPH6_1_TXDLY_R1DQSGATE_P1_SHIFT, - r1dqsgate << SELPH6_1_TXDLY_R1DQSGATE_SHIFT | - r1dqsgate_p1 << SELPH6_1_TXDLY_R1DQSGATE_P1_SHIFT); + clrsetbits32(&ch[channel].ao_regs->selph6_1, + 0x7 << SELPH6_1_TXDLY_R1DQSGATE_SHIFT | + 0x7 << SELPH6_1_TXDLY_R1DQSGATE_P1_SHIFT, + r1dqsgate << SELPH6_1_TXDLY_R1DQSGATE_SHIFT | + r1dqsgate_p1 << SELPH6_1_TXDLY_R1DQSGATE_P1_SHIFT); /* dly_R1DQSGATE and dly_R1DQSGATE_P1 */ - clrsetbits_le32(&ch[channel].ao_regs->selph6_1, - 0x3 << SELPH6_1_DLY_R1DQSGATE_SHIFT | - 0x3 << SELPH6_1_DLY_R1DQSGATE_P1_SHIFT, - (curr_val & 0x3) << SELPH6_1_DLY_R1DQSGATE_SHIFT | - (curr_val_p1 & 0x3) << SELPH6_1_DLY_R1DQSGATE_P1_SHIFT); + clrsetbits32(&ch[channel].ao_regs->selph6_1, + 0x3 << SELPH6_1_DLY_R1DQSGATE_SHIFT | + 0x3 << SELPH6_1_DLY_R1DQSGATE_P1_SHIFT, + (curr_val & 0x3) << SELPH6_1_DLY_R1DQSGATE_SHIFT | + (curr_val_p1 & 0x3) << SELPH6_1_DLY_R1DQSGATE_P1_SHIFT); } static void dqs_gw_counter_reset(u32 channel) { /* reset dqs counter (1 to 0) */ - setbits_le32(&ch[channel].ao_regs->spcmd, 1 << SPCMD_DQSGCNTRST_SHIFT); - clrbits_le32(&ch[channel].ao_regs->spcmd, 1 << SPCMD_DQSGCNTRST_SHIFT); + setbits32(&ch[channel].ao_regs->spcmd, 1 << SPCMD_DQSGCNTRST_SHIFT); + clrbits32(&ch[channel].ao_regs->spcmd, 1 << SPCMD_DQSGCNTRST_SHIFT); dramc_phy_reset(channel); } @@ -357,15 +357,15 @@ void rx_dqs_gating_cal(u32 channel, u8 rank, u8 gw_coarse_val, gw_fine_val; /* disable HW gating */ - clrbits_le32(&ch[channel].ao_regs->dqscal0, + clrbits32(&ch[channel].ao_regs->dqscal0, 1 << DQSCAL0_STBCALEN_SHIFT); /* enable DQS gating window counter */ - setbits_le32(&ch[channel].ao_regs->dqsctl1, + setbits32(&ch[channel].ao_regs->dqsctl1, 1 << DQSCTL1_DQSIENMODE_SHIFT); - setbits_le32(&ch[channel].ao_regs->spcmd, + setbits32(&ch[channel].ao_regs->spcmd, 1 << SPCMD_DQSGCNTEN_SHIFT); /* dual-phase DQS clock gating control enabling */ - setbits_le32(&ch[channel].ddrphy_regs->dqsgctl, + setbits32(&ch[channel].ddrphy_regs->dqsgctl, 1 << DQSGCTL_DQSGDUALP_SHIFT); /* gating calibration value */ @@ -418,7 +418,7 @@ void dual_rank_rx_dqs_gating_cal(u32 channel, dqsinctl = (dqsinctl >> DQSCTL1_DQSINCTL_SHIFT) & (0xf << 0); /* swap cs0 and cs1 */ - setbits_le32(&ch[channel].ao_regs->rkcfg, MASK_RKCFG_RKSWAP_EN); + setbits32(&ch[channel].ao_regs->rkcfg, MASK_RKCFG_RKSWAP_EN); /* rank 1 gw calibration */ rx_dqs_gating_cal(channel, 1, sdram_params); @@ -429,7 +429,7 @@ void dual_rank_rx_dqs_gating_cal(u32 channel, set_gw_fine_factor(channel, opt_gw_fine_value[channel][1], 1); /* swap cs back */ - clrbits_le32(&ch[channel].ao_regs->rkcfg, MASK_RKCFG_RKSWAP_EN); + clrbits32(&ch[channel].ao_regs->rkcfg, MASK_RKCFG_RKSWAP_EN); /* set rank 0 coarse tune and fine tune back */ set_gw_coarse_factor(channel, opt_gw_coarse_value[channel][0]); @@ -446,15 +446,15 @@ void dramc_rankinctl_config(u32 channel, value = min(opt_gw_coarse_value[channel][0], opt_gw_coarse_value[channel][1]) >> 2; - clrsetbits_le32(&ch[channel].ao_regs->dummy, 0xf, value); + clrsetbits32(&ch[channel].ao_regs->dummy, 0xf, value); /* RANKINCTL = RANKINCTL_ROOT1 */ - clrsetbits_le32(&ch[channel].ao_regs->dqscal1, - 0xf << 16, value << 16); + clrsetbits32(&ch[channel].ao_regs->dqscal1, + 0xf << 16, value << 16); } /* disable per-bank refresh when refresh rate >= 5 */ - setbits_le32(&ch[channel].ao_regs->rkcfg, - 1 << RKCFG_PBREF_DISBYRATE_SHIFT); + setbits32(&ch[channel].ao_regs->rkcfg, + 1 << RKCFG_PBREF_DISBYRATE_SHIFT); } u32 dram_k_perbit(u32 channel) @@ -624,11 +624,11 @@ void clk_duty_cal(u32 channel) max_duty_sel = max_duty = 1; - clrsetbits_le32(&ch[channel].ddrphy_regs->phyclkduty, - 0x3 << PHYCLKDUTY_CMDCLKP0DUTYN_SHIFT | - 1 << PHYCLKDUTY_CMDCLKP0DUTYP_SHIFT, - 1 << PHYCLKDUTY_CMDCLKP0DUTYSEL_SHIFT | - max_duty << PHYCLKDUTY_CMDCLKP0DUTYN_SHIFT); + clrsetbits32(&ch[channel].ddrphy_regs->phyclkduty, + 0x3 << PHYCLKDUTY_CMDCLKP0DUTYN_SHIFT | + 1 << PHYCLKDUTY_CMDCLKP0DUTYP_SHIFT, + 1 << PHYCLKDUTY_CMDCLKP0DUTYSEL_SHIFT | + max_duty << PHYCLKDUTY_CMDCLKP0DUTYN_SHIFT); max_win_size = read32(&ch[channel].ddrphy_regs->phyclkduty); @@ -639,26 +639,26 @@ void clk_duty_cal(u32 channel) static void set_dle_factor(u32 channel, u8 curr_val) { - clrsetbits_le32(&ch[channel].ao_regs->ddr2ctl, - 0x7 << DDR2CTL_DATLAT_SHIFT, - (curr_val & 0x7) << DDR2CTL_DATLAT_SHIFT); + clrsetbits32(&ch[channel].ao_regs->ddr2ctl, + 0x7 << DDR2CTL_DATLAT_SHIFT, + (curr_val & 0x7) << DDR2CTL_DATLAT_SHIFT); - clrsetbits_le32(&ch[channel].ao_regs->padctl4, - 0x1 << PADCTL4_DATLAT3_SHIFT, - ((curr_val >> 3) & 0x1) << PADCTL4_DATLAT3_SHIFT); + clrsetbits32(&ch[channel].ao_regs->padctl4, + 0x1 << PADCTL4_DATLAT3_SHIFT, + ((curr_val >> 3) & 0x1) << PADCTL4_DATLAT3_SHIFT); - clrsetbits_le32(&ch[channel].ao_regs->phyctl1, - 0x1 << PHYCTL1_DATLAT4_SHIFT, - ((curr_val >> 4) & 0x1) << PHYCTL1_DATLAT4_SHIFT); + clrsetbits32(&ch[channel].ao_regs->phyctl1, + 0x1 << PHYCTL1_DATLAT4_SHIFT, + ((curr_val >> 4) & 0x1) << PHYCTL1_DATLAT4_SHIFT); - clrsetbits_le32(&ch[channel].ao_regs->misc, - 0x1f << MISC_DATLAT_DSEL_SHIFT, - (curr_val - 8) << MISC_DATLAT_DSEL_SHIFT); + clrsetbits32(&ch[channel].ao_regs->misc, + 0x1f << MISC_DATLAT_DSEL_SHIFT, + (curr_val - 8) << MISC_DATLAT_DSEL_SHIFT); /* optimize bandwidth for HW run time test engine use */ - clrsetbits_le32(&ch[channel].ao_regs->misc, - 0x1f << MISC_LATNORMP_SHIFT, - (curr_val - 3) << MISC_LATNORMP_SHIFT); + clrsetbits32(&ch[channel].ao_regs->misc, + 0x1f << MISC_LATNORMP_SHIFT, + (curr_val - 3) << MISC_LATNORMP_SHIFT); } void dual_rank_rx_datlat_cal(u32 channel, @@ -670,7 +670,7 @@ void dual_rank_rx_datlat_cal(u32 channel, r0_dle_setting = rx_datlat_cal(channel, 0, sdram_params); /* swap cs0 and cs1 */ - setbits_le32(&ch[channel].ao_regs->rkcfg, MASK_RKCFG_RKSWAP_EN); + setbits32(&ch[channel].ao_regs->rkcfg, MASK_RKCFG_RKSWAP_EN); /* set rank 1 coarse tune and fine tune back */ set_gw_coarse_factor(channel, opt_gw_coarse_value[channel][1]); @@ -684,7 +684,7 @@ void dual_rank_rx_datlat_cal(u32 channel, set_gw_fine_factor(channel, opt_gw_fine_value[channel][0], 0); /* swap cs back */ - clrbits_le32(&ch[channel].ao_regs->rkcfg, MASK_RKCFG_RKSWAP_EN); + clrbits32(&ch[channel].ao_regs->rkcfg, MASK_RKCFG_RKSWAP_EN); /* output dle setting of rank 0 and 1 */ dramc_dbg_msg("[DLE] Rank 0 DLE calibrated setting = %xh.\n" @@ -715,7 +715,7 @@ u8 rx_datlat_cal(u32 channel, u8 rank, channel, rank); dramc_dbg_msg("=========================================\n"); - clrbits_le32(&ch[channel].ao_regs->mckdly, + clrbits32(&ch[channel].ao_regs->mckdly, 0x11 << MCKDLY_DQIENQKEND_SHIFT | 0x1 << MCKDLY_DQIENLAT_SHIFT); diff --git a/src/soc/mediatek/mt8173/dsi.c b/src/soc/mediatek/mt8173/dsi.c index b6ff0bc51f..dae23f5a0c 100644 --- a/src/soc/mediatek/mt8173/dsi.c +++ b/src/soc/mediatek/mt8173/dsi.c @@ -40,16 +40,16 @@ void mtk_dsi_configure_mipi_tx(int data_rate, u32 lanes) write32(&mipi_tx0->dsi_bg_con, reg); udelay(30); - clrsetbits_le32(&mipi_tx0->dsi_top_con, RG_DSI_LNT_IMP_CAL_CODE, - 8 << 4 | RG_DSI_LNT_HS_BIAS_EN); + clrsetbits32(&mipi_tx0->dsi_top_con, RG_DSI_LNT_IMP_CAL_CODE, + 8 << 4 | RG_DSI_LNT_HS_BIAS_EN); - setbits_le32(&mipi_tx0->dsi_con, - RG_DSI0_CKG_LDOOUT_EN | RG_DSI0_LDOCORE_EN); + setbits32(&mipi_tx0->dsi_con, + RG_DSI0_CKG_LDOOUT_EN | RG_DSI0_LDOCORE_EN); - clrsetbits_le32(&mipi_tx0->dsi_pll_pwr, RG_DSI_MPPLL_SDM_ISO_EN, - RG_DSI_MPPLL_SDM_PWR_ON); + clrsetbits32(&mipi_tx0->dsi_pll_pwr, RG_DSI_MPPLL_SDM_ISO_EN, + RG_DSI_MPPLL_SDM_PWR_ON); - clrbits_le32(&mipi_tx0->dsi_pll_con0, RG_DSI0_MPPLL_PLL_EN); + clrbits32(&mipi_tx0->dsi_pll_con0, RG_DSI0_MPPLL_PLL_EN); if (data_rate > 500) { txdiv0 = 0; @@ -70,9 +70,9 @@ void mtk_dsi_configure_mipi_tx(int data_rate, u32 lanes) txdiv1 = 2; } - clrsetbits_le32(&mipi_tx0->dsi_pll_con0, - RG_DSI0_MPPLL_TXDIV1 | RG_DSI0_MPPLL_TXDIV0 | - RG_DSI0_MPPLL_PREDIV, txdiv1 << 5 | txdiv0 << 3); + clrsetbits32(&mipi_tx0->dsi_pll_con0, + RG_DSI0_MPPLL_TXDIV1 | RG_DSI0_MPPLL_TXDIV0 | + RG_DSI0_MPPLL_PREDIV, txdiv1 << 5 | txdiv0 << 3); /** * PLL PCW config @@ -86,25 +86,25 @@ void mtk_dsi_configure_mipi_tx(int data_rate, u32 lanes) pcw /= 13; write32(&mipi_tx0->dsi_pll_con2, pcw); - setbits_le32(&mipi_tx0->dsi_pll_con1, RG_DSI0_MPPLL_SDM_FRA_EN); + setbits32(&mipi_tx0->dsi_pll_con1, RG_DSI0_MPPLL_SDM_FRA_EN); - setbits_le32(&mipi_tx0->dsi_clock_lane, LDOOUT_EN); + setbits32(&mipi_tx0->dsi_clock_lane, LDOOUT_EN); for (i = 0; i < lanes; i++) - setbits_le32(&mipi_tx0->dsi_data_lane[i], LDOOUT_EN); + setbits32(&mipi_tx0->dsi_data_lane[i], LDOOUT_EN); - setbits_le32(&mipi_tx0->dsi_pll_con0, RG_DSI0_MPPLL_PLL_EN); + setbits32(&mipi_tx0->dsi_pll_con0, RG_DSI0_MPPLL_PLL_EN); udelay(40); - clrbits_le32(&mipi_tx0->dsi_pll_con1, RG_DSI0_MPPLL_SDM_SSC_EN); - clrbits_le32(&mipi_tx0->dsi_top_con, RG_DSI_PAD_TIE_LOW_EN); + clrbits32(&mipi_tx0->dsi_pll_con1, RG_DSI0_MPPLL_SDM_SSC_EN); + clrbits32(&mipi_tx0->dsi_top_con, RG_DSI_PAD_TIE_LOW_EN); } void mtk_dsi_reset(void) { - setbits_le32(&dsi0->dsi_con_ctrl, 3); - clrbits_le32(&dsi0->dsi_con_ctrl, 1); + setbits32(&dsi0->dsi_con_ctrl, 3); + clrbits32(&dsi0->dsi_con_ctrl, 1); } void mtk_dsi_override_phy_timing(struct mtk_phy_timing *timing) @@ -131,7 +131,7 @@ void mtk_dsi_pin_drv_ctrl(void) struct stopwatch sw; uint32_t pwr_ack; - setbits_le32(&lvds_tx1->vopll_ctl3, RG_DA_LVDSTX_PWR_ON); + setbits32(&lvds_tx1->vopll_ctl3, RG_DA_LVDSTX_PWR_ON); stopwatch_init_usecs_expire(&sw, 1000); @@ -143,5 +143,5 @@ void mtk_dsi_pin_drv_ctrl(void) pwr_ack = read32(&lvds_tx1->vopll_ctl3) & RG_AD_LVDSTX_PWR_ACK; } while (pwr_ack == 0); - clrbits_le32(&lvds_tx1->vopll_ctl3, RG_DA_LVDS_ISO_EN); + clrbits32(&lvds_tx1->vopll_ctl3, RG_DA_LVDS_ISO_EN); } diff --git a/src/soc/mediatek/mt8173/emi.c b/src/soc/mediatek/mt8173/emi.c index be84668abe..f3ea7614e4 100644 --- a/src/soc/mediatek/mt8173/emi.c +++ b/src/soc/mediatek/mt8173/emi.c @@ -166,11 +166,11 @@ size_t sdram_size(void) static void init_4GB_mode(void) { if (sdram_size() == (size_t)4 * GiB) { - setbits_le32(&mt8173_pericfg->axi_bus_ctl3, PERISYS_4G_SUPPORT); - setbits_le32(&mt8173_infracfg->infra_misc, DDR_4GB_SUPPORT_EN); + setbits32(&mt8173_pericfg->axi_bus_ctl3, PERISYS_4G_SUPPORT); + setbits32(&mt8173_infracfg->infra_misc, DDR_4GB_SUPPORT_EN); } else { - clrbits_le32(&mt8173_pericfg->axi_bus_ctl3, PERISYS_4G_SUPPORT); - clrbits_le32(&mt8173_infracfg->infra_misc, DDR_4GB_SUPPORT_EN); + clrbits32(&mt8173_pericfg->axi_bus_ctl3, PERISYS_4G_SUPPORT); + clrbits32(&mt8173_infracfg->infra_misc, DDR_4GB_SUPPORT_EN); } } diff --git a/src/soc/mediatek/mt8173/gpio_init.c b/src/soc/mediatek/mt8173/gpio_init.c index e991a5f75d..c701034a52 100644 --- a/src/soc/mediatek/mt8173/gpio_init.c +++ b/src/soc/mediatek/mt8173/gpio_init.c @@ -25,14 +25,14 @@ */ static void set_gpi_from_mipi(void) { - setbits_le32(&mt8173_mipi->mipi_rx_ana4c, + setbits32(&mt8173_mipi->mipi_rx_ana4c, 1 << 0 | /* RG_MIPI_GPI0_IES GPI47 */ 1 << 6 | /* RG_MIPI_GPI1_IES GPI48 */ 1 << 12 | /* RG_MIPI_GPI2_IES GPI49 */ 1 << 18 | /* RG_MIPI_GPI3_IES GPI50 */ 1 << 24); /* RF_MIPI_GPI4_IES GPI51 */ - setbits_le32(&mt8173_mipi->mipi_rx_ana50, + setbits32(&mt8173_mipi->mipi_rx_ana50, 1 << 0 | /* RG_MIPI_GPI5_IES GPI52 */ 1 << 6 | /* RG_MIPI_GPI6_IES GPI53 */ 1 << 12 | /* RG_MIPI_GPI7_IES GPI54 */ diff --git a/src/soc/mediatek/mt8173/pll.c b/src/soc/mediatek/mt8173/pll.c index e1c1bff6d5..494fcadbac 100644 --- a/src/soc/mediatek/mt8173/pll.c +++ b/src/soc/mediatek/mt8173/pll.c @@ -296,7 +296,7 @@ static const struct rate rates[] = { void pll_set_pcw_change(const struct pll *pll) { - setbits_le32(pll->pcw_reg, PLL_PCW_CHG); + setbits32(pll->pcw_reg, PLL_PCW_CHG); } void mt_pll_init(void) @@ -313,7 +313,7 @@ void mt_pll_init(void) * xPLL PWR ON **************/ for (i = 0; i < APMIXED_NR_PLL; i++) - setbits_le32(plls[i].pwr_reg, PLL_PWR_ON); + setbits32(plls[i].pwr_reg, PLL_PWR_ON); /* wait for xPLL_PWR_ON ready (min delay is 1us) */ udelay(PLL_PWR_ON_DELAY); @@ -322,7 +322,7 @@ void mt_pll_init(void) * xPLL ISO Disable *******************/ for (i = 0; i < APMIXED_NR_PLL; i++) - clrbits_le32(plls[i].pwr_reg, PLL_ISO); + clrbits32(plls[i].pwr_reg, PLL_ISO); /******************** * xPLL Frequency Set @@ -334,7 +334,7 @@ void mt_pll_init(void) * xPLL Frequency Enable ************************/ for (i = 0; i < APMIXED_NR_PLL; i++) - setbits_le32(plls[i].reg, PLL_EN); + setbits32(plls[i].reg, PLL_EN); udelay(PLL_EN_DELAY); /* wait for PLL stable (min delay is 20us) */ @@ -343,7 +343,7 @@ void mt_pll_init(void) ****************/ for (i = 0; i < APMIXED_NR_PLL; i++) { if (plls[i].rstb_shift != NO_RSTB_SHIFT) - setbits_le32(plls[i].reg, 1 << plls[i].rstb_shift); + setbits32(plls[i].reg, 1 << plls[i].rstb_shift); } /************** @@ -351,7 +351,7 @@ void mt_pll_init(void) ***************/ /* enable infrasys DCM */ - setbits_le32(&mt8173_infracfg->top_dcmctl, 0x1); + setbits32(&mt8173_infracfg->top_dcmctl, 0x1); write32(&mtk_topckgen->clk_mode, 0x1); write32(&mtk_topckgen->clk_mode, 0x0); /* enable TOPCKGEN */ @@ -374,16 +374,16 @@ void mt_pll_init(void) void mt_pll_enable_ssusb_clk(void) { /* set RG_LTECLKSQ_EN */ - setbits_le32(&mtk_apmixed->ap_pll_con0, 0x1); + setbits32(&mtk_apmixed->ap_pll_con0, 0x1); udelay(100); /* wait for PLL stable */ /* set RG_LTECLKSQ_LPF_EN & DA_REF2USB_TX_EN */ - setbits_le32(&mtk_apmixed->ap_pll_con0, 0x1 << 1); - setbits_le32(&mtk_apmixed->ap_pll_con2, 0x1); + setbits32(&mtk_apmixed->ap_pll_con0, 0x1 << 1); + setbits32(&mtk_apmixed->ap_pll_con2, 0x1); udelay(100); /* wait for PLL stable */ /* set DA_REF2USB_TX_LPF_EN & DA_REF2USB_TX_OUT_EN */ - setbits_le32(&mtk_apmixed->ap_pll_con2, (0x1 << 2) | (0x1 << 1)); + setbits32(&mtk_apmixed->ap_pll_con2, (0x1 << 2) | (0x1 << 1)); } @@ -391,7 +391,7 @@ void mt_pll_enable_ssusb_clk(void) void mt_pll_post_init(void) { /* CPU clock divide by 1 */ - clrbits_le32(&mt8173_infracfg->top_ckdiv1, 0x3ff); + clrbits32(&mt8173_infracfg->top_ckdiv1, 0x3ff); /* select ARMPLL */ write32(&mt8173_infracfg->top_ckmuxsel, (1 << 2) | 1); @@ -414,20 +414,20 @@ void mt_pll_set_aud_div(u32 rate) if (apll1) { /* mclk */ - clrbits_le32(&mtk_topckgen->clk_auddiv_0, 1 << 5); - clrsetbits_le32(&mtk_topckgen->clk_auddiv_1, 0xff << 8, - mclk_div << 8); + clrbits32(&mtk_topckgen->clk_auddiv_0, 1 << 5); + clrsetbits32(&mtk_topckgen->clk_auddiv_1, 0xff << 8, + mclk_div << 8); /* bclk */ - clrsetbits_le32(&mtk_topckgen->clk_auddiv_0, 0xf << 24, - 7 << 24); + clrsetbits32(&mtk_topckgen->clk_auddiv_0, 0xf << 24, + 7 << 24); } else { /* mclk */ - setbits_le32(&mtk_topckgen->clk_auddiv_0, 1 << 5); - clrsetbits_le32(&mtk_topckgen->clk_auddiv_2, 0xff << 8, - mclk_div << 8); + setbits32(&mtk_topckgen->clk_auddiv_0, 1 << 5); + clrsetbits32(&mtk_topckgen->clk_auddiv_2, 0xff << 8, + mclk_div << 8); /* bclk */ - clrsetbits_le32(&mtk_topckgen->clk_auddiv_0, 0xf << 28, - 7 << 28); + clrsetbits32(&mtk_topckgen->clk_auddiv_0, 0xf << 28, + 7 << 28); } } @@ -441,19 +441,19 @@ void mt_mem_pll_config_pre(const struct mt8173_sdram_params *sdram_params) u32 mpll_sdm_pcw_20_0 = 0xF13B1; /* disable MPLL for adjusting memory clk frequency */ - clrbits_le32(&mtk_apmixed->mpll_con0, BIT(0)); + clrbits32(&mtk_apmixed->mpll_con0, BIT(0)); /* MPLL configuration: mode selection */ - setbits_le32(&mtk_apmixed->mpll_con0, BIT(16)); - clrbits_le32(&mtk_apmixed->mpll_con0, 0x7 << 4); - clrbits_le32(&mtk_apmixed->pll_test_con0, 1 << 31); + setbits32(&mtk_apmixed->mpll_con0, BIT(16)); + clrbits32(&mtk_apmixed->mpll_con0, 0x7 << 4); + clrbits32(&mtk_apmixed->pll_test_con0, 1 << 31); /* set RG_MPLL_SDM_PCW for feedback divide ratio */ - clrsetbits_le32(&mtk_apmixed->mpll_con1, 0x1fffff, mpll_sdm_pcw_20_0); + clrsetbits32(&mtk_apmixed->mpll_con1, 0x1fffff, mpll_sdm_pcw_20_0); } void mt_mem_pll_config_post(void) { /* power up sequence starts: enable MPLL */ - setbits_le32(&mtk_apmixed->mpll_con0, BIT(0)); + setbits32(&mtk_apmixed->mpll_con0, BIT(0)); } void mt_mem_pll_mux(void) diff --git a/src/soc/mediatek/mt8173/pmic_wrap.c b/src/soc/mediatek/mt8173/pmic_wrap.c index af88343c14..a15447c20f 100644 --- a/src/soc/mediatek/mt8173/pmic_wrap.c +++ b/src/soc/mediatek/mt8173/pmic_wrap.c @@ -170,11 +170,11 @@ s32 pwrap_init(void) s32 sub_return1 = 0; u16 rdata = 0x0; - setbits_le32(&mt8173_infracfg->infra_rst0, INFRA_PMIC_WRAP_RST); + setbits32(&mt8173_infracfg->infra_rst0, INFRA_PMIC_WRAP_RST); /* add 1us delay for toggling SW reset */ udelay(1); /* clear reset bit */ - clrbits_le32(&mt8173_infracfg->infra_rst0, INFRA_PMIC_WRAP_RST); + clrbits32(&mt8173_infracfg->infra_rst0, INFRA_PMIC_WRAP_RST); /* Enable DCM */ write32(&mtk_pwrap->dcm_en, 3); diff --git a/src/soc/mediatek/mt8173/spi.c b/src/soc/mediatek/mt8173/spi.c index cf2ffa264b..1b0de79e34 100644 --- a/src/soc/mediatek/mt8173/spi.c +++ b/src/soc/mediatek/mt8173/spi.c @@ -47,10 +47,10 @@ void mtk_spi_set_timing(struct mtk_spi_regs *regs, u32 sck_ticks, u32 cs_ticks, ((sck_ticks - 1) << SPI_CFG0_SCK_LOW_SHIFT) | ((cs_ticks - 1) << SPI_CFG0_CS_HOLD_SHIFT) | ((cs_ticks - 1) << SPI_CFG0_CS_SETUP_SHIFT)); - clrsetbits_le32(®s->spi_cfg1_reg, SPI_CFG1_CS_IDLE_MASK | - SPI_CFG1_TICK_DLY_MASK, - (tick_dly << SPI_CFG1_TICK_DLY_SHIFT) | - ((cs_ticks - 1) << SPI_CFG1_CS_IDLE_SHIFT)); + clrsetbits32(®s->spi_cfg1_reg, SPI_CFG1_CS_IDLE_MASK | + SPI_CFG1_TICK_DLY_MASK, + (tick_dly << SPI_CFG1_TICK_DLY_SHIFT) | + ((cs_ticks - 1) << SPI_CFG1_CS_IDLE_SHIFT)); } static const struct spi_ctrlr spi_flash_ctrlr = { diff --git a/src/soc/mediatek/mt8183/auxadc.c b/src/soc/mediatek/mt8183/auxadc.c index 5460486709..23ce5570bf 100644 --- a/src/soc/mediatek/mt8183/auxadc.c +++ b/src/soc/mediatek/mt8183/auxadc.c @@ -51,19 +51,19 @@ static void mt_auxadc_update_cali(void) } static uint32_t auxadc_get_rawdata(int channel) { - setbits_le32(&mt8183_infracfg->module_sw_cg_1_clr, 1 << 10); + setbits32(&mt8183_infracfg->module_sw_cg_1_clr, 1 << 10); assert(wait_ms(300, !(read32(&mtk_auxadc->con2) & 0x1))); - clrbits_le32(&mtk_auxadc->con1, 1 << channel); + clrbits32(&mtk_auxadc->con1, 1 << channel); assert(wait_ms(300, !(read32(&mtk_auxadc->data[channel]) & (1 << 12)))); - setbits_le32(&mtk_auxadc->con1, 1 << channel); + setbits32(&mtk_auxadc->con1, 1 << channel); udelay(25); assert(wait_ms(300, read32(&mtk_auxadc->data[channel]) & (1 << 12))); uint32_t value = read32(&mtk_auxadc->data[channel]) & 0x0FFF; - setbits_le32(&mt8183_infracfg->module_sw_cg_1_set, 1 << 10); + setbits32(&mt8183_infracfg->module_sw_cg_1_set, 1 << 10); return value; } diff --git a/src/soc/mediatek/mt8183/ddp.c b/src/soc/mediatek/mt8183/ddp.c index 3c2b0fd662..50d6caf776 100644 --- a/src/soc/mediatek/mt8183/ddp.c +++ b/src/soc/mediatek/mt8183/ddp.c @@ -42,7 +42,7 @@ static void disp_config_main_path_mutex(void) static void ovl_bgclr_in_sel(u32 idx) { - setbits_le32(&disp_ovl[idx]->datapath_con, BIT(2)); + setbits32(&disp_ovl[idx]->datapath_con, BIT(2)); } static void enable_pq(struct disp_pq_regs *const regs, u32 width, u32 height, @@ -74,10 +74,10 @@ static void main_disp_path_setup(u32 width, u32 height, u32 vrefresh) static void disp_clock_on(void) { - clrbits_le32(&mmsys_cfg->mmsys_cg_con0, CG_CON0_DISP_ALL); + clrbits32(&mmsys_cfg->mmsys_cg_con0, CG_CON0_DISP_ALL); - clrbits_le32(&mmsys_cfg->mmsys_cg_con1, CG_CON1_DISP_DSI0 | - CG_CON1_DISP_DSI0_INTERFACE); + clrbits32(&mmsys_cfg->mmsys_cg_con1, CG_CON1_DISP_DSI0 | + CG_CON1_DISP_DSI0_INTERFACE); } void mtk_ddp_init(void) diff --git a/src/soc/mediatek/mt8183/dramc_init_setting.c b/src/soc/mediatek/mt8183/dramc_init_setting.c index 2a36b48d5d..74fa0e2f1d 100644 --- a/src/soc/mediatek/mt8183/dramc_init_setting.c +++ b/src/soc/mediatek/mt8183/dramc_init_setting.c @@ -39,7 +39,7 @@ static void cke_fix_onoff(int option, u8 chn) off = (1 - option); } - clrsetbits_le32(&ch[chn].ao.ckectrl, + clrsetbits32(&ch[chn].ao.ckectrl, (0x1 << 6) | (0x1 << 7), (on << 6) | (off << 7)); } @@ -67,13 +67,13 @@ static void dvfs_settings(u8 freq_group) dll_idle = dll_idle << 1; for (u8 chn = 0; chn < CHANNEL_MAX; chn++) { - setbits_le32(&ch[chn].ao.dvfsdll, 0x1 << 5); - setbits_le32(&ch[chn].phy.dvfs_emi_clk, 0x1 << 29); - clrsetbits_le32(&ch[0].ao.shuctrl2, 0x7f, dll_idle); + setbits32(&ch[chn].ao.dvfsdll, 0x1 << 5); + setbits32(&ch[chn].phy.dvfs_emi_clk, 0x1 << 29); + clrsetbits32(&ch[0].ao.shuctrl2, 0x7f, dll_idle); - setbits_le32(&ch[0].phy.misc_ctrl0, 0x3 << 19); - setbits_le32(&ch[chn].phy.dvfs_emi_clk, 0x1 << 24); - setbits_le32(&ch[chn].ao.dvfsdll, 0x1 << 7); + setbits32(&ch[0].phy.misc_ctrl0, 0x3 << 19); + setbits32(&ch[chn].phy.dvfs_emi_clk, 0x1 << 24); + setbits32(&ch[chn].ao.dvfsdll, 0x1 << 7); } } @@ -120,11 +120,11 @@ static void ddr_phy_pll_setting(u8 chn, u8 freq_group) ca_dll_mode[CHANNEL_A] = DLL_MASTER; ca_dll_mode[CHANNEL_B] = DLL_SLAVE; - clrbits_le32(&ch[chn].phy.shu[0].pll[4], 0xffff); - clrbits_le32(&ch[chn].phy.shu[0].pll[6], 0xffff); - setbits_le32(&ch[chn].phy.misc_shu_opt, (chn + 1) << 18); - clrsetbits_le32(&ch[chn].phy.ckmux_sel, 0x3 << 18 | 0x3 << 16, 0x0); - clrsetbits_le32(&ch[chn].phy.shu[0].ca_cmd[0], 0x3 << 18, 0x1 << 18); + clrbits32(&ch[chn].phy.shu[0].pll[4], 0xffff); + clrbits32(&ch[chn].phy.shu[0].pll[6], 0xffff); + setbits32(&ch[chn].phy.misc_shu_opt, (chn + 1) << 18); + clrsetbits32(&ch[chn].phy.ckmux_sel, 0x3 << 18 | 0x3 << 16, 0x0); + clrsetbits32(&ch[chn].phy.shu[0].ca_cmd[0], 0x3 << 18, 0x1 << 18); SET32_BITFIELDS(&ch[chn].ao.dvfsdll, DVFSDLL_R_BYPASS_1ST_DLL_SHU1, ca_dll_mode[chn] == DLL_SLAVE); @@ -136,7 +136,7 @@ static void ddr_phy_pll_setting(u8 chn, u8 freq_group) u8 idle_cnt = is_master ? 0x9 : 0x7; u8 fast_psjp = is_master ? 0x1 : 0x0; - clrsetbits_le32(&ch[chn].phy.shu[0].ca_dll[0], + clrsetbits32(&ch[chn].phy.shu[0].ca_dll[0], (0x1 << 31) | (0x1 << 30) | (0xf << 20) | (0xf << 16) | (0xf << 12) | (0x1 << 10) | (0x1 << 9) | (0x1 << 4), (phdet_out << 31) | (phdet_in << 30) | @@ -147,11 +147,11 @@ static void ddr_phy_pll_setting(u8 chn, u8 freq_group) u8 pd_ck_sel = is_master ? 0x1 : 0x0; u8 fastpj_ck_sel = is_master ? 0x0 : 0x1; - clrsetbits_le32(&ch[chn].phy.shu[0].ca_dll[1], + clrsetbits32(&ch[chn].phy.shu[0].ca_dll[1], (0x1 << 2) | (0x1 << 0), (pd_ck_sel << 2) | (fastpj_ck_sel << 0)); - clrsetbits_le32(&ch[chn].phy.shu[0].ca_cmd[6], + clrsetbits32(&ch[chn].phy.shu[0].ca_cmd[6], 0x1 << 7, (is_master ? 0x1 : 0x0) << 7); struct reg_value regs_bak[] = { @@ -164,86 +164,86 @@ static void ddr_phy_pll_setting(u8 chn, u8 freq_group) regs_bak[i].value = read32(regs_bak[i].addr); for (size_t b = 0; b < 2; b++) - setbits_le32(&ch[chn].phy.b[b].dq[7], + setbits32(&ch[chn].phy.b[b].dq[7], 0x1 << 6 | 0x1 << 4 | 0x1 << 2 | 0x1 << 0); - setbits_le32(&ch[chn].phy.ca_cmd[7], 0x1 << 6 | 0x1 << 4 | 0x1 << 2 | 0x1 << 0); - setbits_le32(&ch[chn].phy.ca_cmd[2], 0x1 << 21); + setbits32(&ch[chn].phy.ca_cmd[7], 0x1 << 6 | 0x1 << 4 | 0x1 << 2 | 0x1 << 0); + setbits32(&ch[chn].phy.ca_cmd[2], 0x1 << 21); /* 26M */ SET32_BITFIELDS(&ch[chn].phy.misc_cg_ctrl0, MISC_CG_CTRL0_CLK_MEM_SEL, 0); /* MID FINE_TUNE */ - clrbits_le32(&ch[chn].phy.shu[0].b[0].dq[6], (0x1 << 26) | (0x1 << 27)); - clrbits_le32(&ch[chn].phy.shu[0].b[1].dq[6], (0x1 << 26) | (0x1 << 27)); - clrbits_le32(&ch[chn].phy.shu[0].ca_cmd[6], (0x1 << 26) | (0x1 << 27)); - clrbits_le32(&ch[chn].phy.pll4, (0x1 << 16) | (0x1 << 22)); + clrbits32(&ch[chn].phy.shu[0].b[0].dq[6], (0x1 << 26) | (0x1 << 27)); + clrbits32(&ch[chn].phy.shu[0].b[1].dq[6], (0x1 << 26) | (0x1 << 27)); + clrbits32(&ch[chn].phy.shu[0].ca_cmd[6], (0x1 << 26) | (0x1 << 27)); + clrbits32(&ch[chn].phy.pll4, (0x1 << 16) | (0x1 << 22)); /* PLL */ - clrbits_le32(&ch[chn].phy.pll1, 0x1 << 31); - clrbits_le32(&ch[chn].phy.pll2, 0x1 << 31); + clrbits32(&ch[chn].phy.pll1, 0x1 << 31); + clrbits32(&ch[chn].phy.pll2, 0x1 << 31); /* DLL */ - clrbits_le32(&ch[chn].phy.ca_dll_fine_tune[2], 0x1 << 0); - clrbits_le32(&ch[chn].phy.b[0].dll_fine_tune[2], 0x1 << 0); - clrbits_le32(&ch[chn].phy.b[1].dll_fine_tune[2], 0x1 << 0); - setbits_le32(&ch[chn].phy.b[0].dll_fine_tune[2], + clrbits32(&ch[chn].phy.ca_dll_fine_tune[2], 0x1 << 0); + clrbits32(&ch[chn].phy.b[0].dll_fine_tune[2], 0x1 << 0); + clrbits32(&ch[chn].phy.b[1].dll_fine_tune[2], 0x1 << 0); + setbits32(&ch[chn].phy.b[0].dll_fine_tune[2], (0x1 << 10) | (0x1 << 11) | (0x1 << 13) | (0x1 << 14) | (0x1 << 15) | (0x1 << 17) | (0x1 << 19) | (0x1 << 27) | (0x1 << 31)); - setbits_le32(&ch[chn].phy.b[1].dll_fine_tune[2], + setbits32(&ch[chn].phy.b[1].dll_fine_tune[2], (0x1 << 10) | (0x1 << 11) | (0x1 << 13) | (0x1 << 14) | (0x1 << 15) | (0x1 << 17) | (0x1 << 19) | (0x1 << 27) | (0x1 << 31)); - setbits_le32(&ch[chn].phy.ca_dll_fine_tune[2], + setbits32(&ch[chn].phy.ca_dll_fine_tune[2], (0x1 << 10) | (0x1 << 11) | (0x1 << 13) | (0x1 << 15) | (0x1 << 16) | (0x1 << 17) | (0x1 << 19) | (0x1 << 27) | (0x1 << 31)); /* RESETB */ - clrbits_le32(&ch[chn].phy.ca_dll_fine_tune[0], 0x1 << 3); - clrbits_le32(&ch[chn].phy.b[0].dll_fine_tune[0], 0x1 << 3); - clrbits_le32(&ch[chn].phy.b[1].dll_fine_tune[0], 0x1 << 3); + clrbits32(&ch[chn].phy.ca_dll_fine_tune[0], 0x1 << 3); + clrbits32(&ch[chn].phy.b[0].dll_fine_tune[0], 0x1 << 3); + clrbits32(&ch[chn].phy.b[1].dll_fine_tune[0], 0x1 << 3); udelay(1); /* MPLL 52M */ - clrsetbits_le32(&ch[chn].phy.shu[0].pll[8], + clrsetbits32(&ch[chn].phy.shu[0].pll[8], (0x7 << 0) | (0x3 << 18), (0x0 << 0) | (0x1 << 18)); - clrsetbits_le32(&ch[chn].phy.shu[0].pll[10], + clrsetbits32(&ch[chn].phy.shu[0].pll[10], (0x7 << 0) | (0x3 << 18), (0x0 << 0) | (0x1 << 18)); - clrsetbits_le32(&ch[chn].phy.shu[0].pll[5], + clrsetbits32(&ch[chn].phy.shu[0].pll[5], (0xffff << 16) | 0x1 << 0, sdm_pcw << 16); - clrsetbits_le32(&ch[chn].phy.shu[0].pll[7], + clrsetbits32(&ch[chn].phy.shu[0].pll[7], (0xffff << 16) | 0x1 << 0, sdm_pcw << 16); - setbits_le32(&ch[chn].phy.ca_dll_fine_tune[0], 0x1 << 1); - setbits_le32(&ch[chn].phy.b[0].dll_fine_tune[0], 0x1 << 1); - setbits_le32(&ch[chn].phy.b[1].dll_fine_tune[0], 0x1 << 1); + setbits32(&ch[chn].phy.ca_dll_fine_tune[0], 0x1 << 1); + setbits32(&ch[chn].phy.b[0].dll_fine_tune[0], 0x1 << 1); + setbits32(&ch[chn].phy.b[1].dll_fine_tune[0], 0x1 << 1); - clrbits_le32(&ch[chn].phy.ca_dll_fine_tune[1], 0x1 << 11); - clrbits_le32(&ch[chn].phy.b[0].dll_fine_tune[1], 0x1 << 19); - clrbits_le32(&ch[chn].phy.b[1].dll_fine_tune[1], 0x1 << 19); + clrbits32(&ch[chn].phy.ca_dll_fine_tune[1], 0x1 << 11); + clrbits32(&ch[chn].phy.b[0].dll_fine_tune[1], 0x1 << 19); + clrbits32(&ch[chn].phy.b[1].dll_fine_tune[1], 0x1 << 19); - clrsetbits_le32(&ch[chn].phy.shu[0].b[0].dq[6], + clrsetbits32(&ch[chn].phy.shu[0].b[0].dq[6], (0x3 << 22) | (0x3 << 24) | (0x3 << 28), (mid_cap_sel << 22) | (vth_sel << 24) | (cap_sel << 28)); - clrsetbits_le32(&ch[chn].phy.shu[0].b[1].dq[6], + clrsetbits32(&ch[chn].phy.shu[0].b[1].dq[6], (0x3 << 22) | (0x3 << 24) | (0x3 << 28), (mid_cap_sel << 22) | (vth_sel << 24) | (cap_sel << 28)); - clrsetbits_le32(&ch[chn].phy.shu[0].ca_cmd[6], + clrsetbits32(&ch[chn].phy.shu[0].ca_cmd[6], (0x3 << 22) | (0x3 << 24) | (0x3 << 28), (mid_cap_sel << 22) | (vth_sel << 24) | (cap_sel << 28)); /* RESETB */ - setbits_le32(&ch[chn].phy.ca_dll_fine_tune[0], 0x1 << 3); - setbits_le32(&ch[chn].phy.b[0].dll_fine_tune[0], 0x1 << 3); - setbits_le32(&ch[chn].phy.b[1].dll_fine_tune[0], 0x1 << 3); + setbits32(&ch[chn].phy.ca_dll_fine_tune[0], 0x1 << 3); + setbits32(&ch[chn].phy.b[0].dll_fine_tune[0], 0x1 << 3); + setbits32(&ch[chn].phy.b[1].dll_fine_tune[0], 0x1 << 3); udelay(1); /* PLL EN */ - setbits_le32(&ch[chn].phy.pll1, 0x1 << 31); - setbits_le32(&ch[chn].phy.pll2, 0x1 << 31); + setbits32(&ch[chn].phy.pll1, 0x1 << 31); + setbits32(&ch[chn].phy.pll2, 0x1 << 31); udelay(100); /* MIDPI Init 1 */ - setbits_le32(&ch[chn].phy.pll4, (0x1 << 16) | (0x1 << 22)); + setbits32(&ch[chn].phy.pll4, (0x1 << 16) | (0x1 << 22)); udelay(1); /* MIDPI Init 2 */ @@ -261,50 +261,50 @@ static void ddr_phy_pll_setting(u8 chn, u8 freq_group) u32 dq6_clear = (0x1 << 26) | (0x1 << 27); u32 dq6_set = (midpi_en << 26) | (midpi_ckdiv4_en << 27); - clrsetbits_le32(&ch[chn].phy.shu[0].b[0].dq[6], dq6_clear, dq6_set); - clrsetbits_le32(&ch[chn].phy.shu[0].b[1].dq[6], dq6_clear, dq6_set); - clrsetbits_le32(&ch[chn].phy.shu[0].ca_cmd[6], dq6_clear, dq6_set); + clrsetbits32(&ch[chn].phy.shu[0].b[0].dq[6], dq6_clear, dq6_set); + clrsetbits32(&ch[chn].phy.shu[0].b[1].dq[6], dq6_clear, dq6_set); + clrsetbits32(&ch[chn].phy.shu[0].ca_cmd[6], dq6_clear, dq6_set); udelay(1); - clrsetbits_le32(&ch[chn].phy.ca_dll_fine_tune[3], 0x1 << 19, + clrsetbits32(&ch[chn].phy.ca_dll_fine_tune[3], 0x1 << 19, (0x1 << 13) | (0x1 << 15) | (0x1 << 16) | (0x1 << 17) | ((chn ? 0 : 1) << 19)); - setbits_le32(&ch[chn].phy.b[0].dll_fine_tune[3], + setbits32(&ch[chn].phy.b[0].dll_fine_tune[3], (0x1 << 11) | (0x1 << 13) | (0x1 << 14) | (0x1 << 15) | (0x1 << 17)); - setbits_le32(&ch[chn].phy.b[1].dll_fine_tune[3], + setbits32(&ch[chn].phy.b[1].dll_fine_tune[3], (0x1 << 11) | (0x1 << 13) | (0x1 << 14) | (0x1 << 15) | (0x1 << 17)); - clrbits_le32(&ch[chn].phy.ca_dll_fine_tune[2], + clrbits32(&ch[chn].phy.ca_dll_fine_tune[2], (0x1 << 10) | (0x1 << 13) | (0x1 << 15) | (0x1 << 16) | (0x1 << 17) | (0x1 << 19) | (0x1 << 27) | (0x1 << 31)); - clrbits_le32(&ch[chn].phy.b[0].dll_fine_tune[2], + clrbits32(&ch[chn].phy.b[0].dll_fine_tune[2], (0x1 << 10) | (0x1 << 13) | (0x1 << 14) | (0x1 << 15) | (0x1 << 17) | (0x1 << 19) | (0x1 << 27) | (0x1 << 31)); - clrbits_le32(&ch[chn].phy.b[1].dll_fine_tune[2], + clrbits32(&ch[chn].phy.b[1].dll_fine_tune[2], (0x1 << 10) | (0x1 << 13) | (0x1 << 14) | (0x1 << 15) | (0x1 << 17) | (0x1 << 19) | (0x1 << 27) | (0x1 << 31)); - setbits_le32(&ch[chn].phy.ca_dll_fine_tune[2], 0x1 << 11); - clrbits_le32(&ch[chn].phy.b[0].dll_fine_tune[2], 0x1 << 11); - clrbits_le32(&ch[chn].phy.b[1].dll_fine_tune[2], 0x1 << 11); + setbits32(&ch[chn].phy.ca_dll_fine_tune[2], 0x1 << 11); + clrbits32(&ch[chn].phy.b[0].dll_fine_tune[2], 0x1 << 11); + clrbits32(&ch[chn].phy.b[1].dll_fine_tune[2], 0x1 << 11); udelay(2); - setbits_le32(&ch[chn].phy.misc_cg_ctrl0, 0x1 << 4); + setbits32(&ch[chn].phy.misc_cg_ctrl0, 0x1 << 4); udelay(1); /* DLL */ - setbits_le32(&ch[chn].phy.ca_dll_fine_tune[2], 0x1 << 0); + setbits32(&ch[chn].phy.ca_dll_fine_tune[2], 0x1 << 0); udelay(1); - setbits_le32(&ch[chn].phy.b[0].dll_fine_tune[2], 0x1 << 0); - setbits_le32(&ch[chn].phy.b[1].dll_fine_tune[2], 0x1 << 0); + setbits32(&ch[chn].phy.b[0].dll_fine_tune[2], 0x1 << 0); + setbits32(&ch[chn].phy.b[1].dll_fine_tune[2], 0x1 << 0); udelay(1); - clrbits_le32(&ch[chn].phy.ca_cmd[2], 0x1 << 21); + clrbits32(&ch[chn].phy.ca_cmd[2], 0x1 << 21); for (size_t i = 0; i < ARRAY_SIZE(regs_bak); i++) write32(regs_bak[i].addr, regs_bak[i].value); @@ -312,18 +312,18 @@ static void ddr_phy_pll_setting(u8 chn, u8 freq_group) cke_fix_onoff(CKE_DYNAMIC, CHANNEL_B); if (freq_group == LP4X_DDR3200 || freq_group == LP4X_DDR3600) { - setbits_le32(&ch[chn].phy.shu[0].pll[5], 0x1 << 0); - setbits_le32(&ch[chn].phy.shu[0].pll[7], 0x1 << 0); - setbits_le32(&ch[chn].phy.shu[0].pll[14], 0x1 << 1); - setbits_le32(&ch[chn].phy.shu[0].pll20, 0x1 << 1); - clrsetbits_le32(&ch[chn].phy.shu[0].pll[14], - 0xffff << 16, 0x0208 << 16); - clrsetbits_le32(&ch[chn].phy.shu[0].pll20, - 0xffff << 16, 0x0208 << 16); - clrsetbits_le32(&ch[chn].phy.shu[0].pll[15], - 0xffffffff << 0, delta << 16); - clrsetbits_le32(&ch[chn].phy.shu[0].pll21, - 0xffffffff << 0, delta << 16); + setbits32(&ch[chn].phy.shu[0].pll[5], 0x1 << 0); + setbits32(&ch[chn].phy.shu[0].pll[7], 0x1 << 0); + setbits32(&ch[chn].phy.shu[0].pll[14], 0x1 << 1); + setbits32(&ch[chn].phy.shu[0].pll20, 0x1 << 1); + clrsetbits32(&ch[chn].phy.shu[0].pll[14], + 0xffff << 16, 0x0208 << 16); + clrsetbits32(&ch[chn].phy.shu[0].pll20, + 0xffff << 16, 0x0208 << 16); + clrsetbits32(&ch[chn].phy.shu[0].pll[15], + 0xffffffff << 0, delta << 16); + clrsetbits32(&ch[chn].phy.shu[0].pll21, + 0xffffffff << 0, delta << 16); } } @@ -337,17 +337,17 @@ static void dramc_gating_mode(u8 mode) } for (u8 b = 0; b < 2; b++) { - clrsetbits_le32(&ch[0].phy.b[b].dq[6], 0x3 << 14, vref_sel << 14); - setbits_le32(&ch[0].phy.b[b].dq[9], 0x1 << 5); + clrsetbits32(&ch[0].phy.b[b].dq[6], 0x3 << 14, vref_sel << 14); + setbits32(&ch[0].phy.b[b].dq[9], 0x1 << 5); } - clrsetbits_le32(&ch[0].ao.stbcal1, 0x1 << 5, burst << 5); - setbits_le32(&ch[0].ao.stbcal, 0x1 << 30); + clrsetbits32(&ch[0].ao.stbcal1, 0x1 << 5, burst << 5); + setbits32(&ch[0].ao.stbcal, 0x1 << 30); for (u8 b = 0; b < 2; b++) { - clrbits_le32(&ch[0].phy.b[b].dq[9], (0x1 << 4) | (0x1 << 0)); + clrbits32(&ch[0].phy.b[b].dq[9], (0x1 << 4) | (0x1 << 0)); udelay(1); - setbits_le32(&ch[0].phy.b[b].dq[9], (0x1 << 4) | (0x1 << 0)); + setbits32(&ch[0].phy.b[b].dq[9], (0x1 << 4) | (0x1 << 0)); } } @@ -360,196 +360,196 @@ static void update_initial_settings(u8 freq_group) rx_vref = 0xb; if (operate_fsp == FSP_1) { - setbits_le32(&ch[0].ao.shu[0].odtctrl, 0x1 << 0); - setbits_le32(&ch[0].phy.shu[0].b[0].dq[7], 0x1 << 15); - setbits_le32(&ch[0].phy.shu[0].b[1].dq[7], 0x1 << 15); + setbits32(&ch[0].ao.shu[0].odtctrl, 0x1 << 0); + setbits32(&ch[0].phy.shu[0].b[0].dq[7], 0x1 << 15); + setbits32(&ch[0].phy.shu[0].b[1].dq[7], 0x1 << 15); } else { - clrbits_le32(&ch[0].ao.shu[0].odtctrl, 0x1 << 0); - clrbits_le32(&ch[0].phy.shu[0].b[0].dq[7], 0x1 << 15); - clrbits_le32(&ch[0].phy.shu[0].b[1].dq[7], 0x1 << 15); + clrbits32(&ch[0].ao.shu[0].odtctrl, 0x1 << 0); + clrbits32(&ch[0].phy.shu[0].b[0].dq[7], 0x1 << 15); + clrbits32(&ch[0].phy.shu[0].b[1].dq[7], 0x1 << 15); } for (size_t b = 0; b < 2; b++) for (size_t r = 0; r < 2; r++) - clrbits_le32(&ch[0].phy.r[r].b[b].rxdvs[2], + clrbits32(&ch[0].phy.r[r].b[b].rxdvs[2], (0x1 << 23) | (0x1 << 28) | (0x3 << 30)); - clrbits_le32(&ch[0].phy.shu[0].ca_cmd[7], 0xf << 0); + clrbits32(&ch[0].phy.shu[0].ca_cmd[7], 0xf << 0); - setbits_le32(&ch[0].phy.ca_cmd[3], 0x1 << 10); - setbits_le32(&ch[0].phy.ca_cmd[10], 0x1 << 5); - clrsetbits_le32(&ch[0].phy.ca_cmd[6], 0x3 << 14, 0x1 << 14); - setbits_le32(&ch[0].phy.b[0].dq[3], 0x7 << 5); - setbits_le32(&ch[0].phy.b[1].dq[3], 0x7 << 5); - setbits_le32(&ch[0].phy.ca_cmd[3], (0x1 << 5) | (0x1 << 7)); - clrbits_le32(&ch[0].phy.b[0].dq[3], 0x1 << 1); - clrbits_le32(&ch[0].phy.b[1].dq[3], 0x1 << 1); - setbits_le32(&ch[0].phy.b[0].dq[5], 0x1 << 31); - setbits_le32(&ch[0].phy.b[1].dq[5], 0x1 << 31); - setbits_le32(&ch[0].phy.ca_cmd[5], 0x1 << 31); + setbits32(&ch[0].phy.ca_cmd[3], 0x1 << 10); + setbits32(&ch[0].phy.ca_cmd[10], 0x1 << 5); + clrsetbits32(&ch[0].phy.ca_cmd[6], 0x3 << 14, 0x1 << 14); + setbits32(&ch[0].phy.b[0].dq[3], 0x7 << 5); + setbits32(&ch[0].phy.b[1].dq[3], 0x7 << 5); + setbits32(&ch[0].phy.ca_cmd[3], (0x1 << 5) | (0x1 << 7)); + clrbits32(&ch[0].phy.b[0].dq[3], 0x1 << 1); + clrbits32(&ch[0].phy.b[1].dq[3], 0x1 << 1); + setbits32(&ch[0].phy.b[0].dq[5], 0x1 << 31); + setbits32(&ch[0].phy.b[1].dq[5], 0x1 << 31); + setbits32(&ch[0].phy.ca_cmd[5], 0x1 << 31); - clrsetbits_le32(&ch[0].phy.ca_cmd[6], 0xf << 16, 0x3 << 16); - clrsetbits_le32(&ch[0].phy.misc_imp_ctrl0, (0x1 << 5) | (0x1 << 6), + clrsetbits32(&ch[0].phy.ca_cmd[6], 0xf << 16, 0x3 << 16); + clrsetbits32(&ch[0].phy.misc_imp_ctrl0, (0x1 << 5) | (0x1 << 6), (0x1 << 5) | (0x0 << 6)); - setbits_le32(&ch[0].phy.b[0].dq[6], 0x1 << 9); - setbits_le32(&ch[0].phy.b[1].dq[6], 0x1 << 9); - setbits_le32(&ch[0].phy.ca_cmd[6], 0x1 << 9); - clrsetbits_le32(&ch[0].phy.b[0].dq[6], 0x3 << 0, 0x1 << 0); - clrsetbits_le32(&ch[0].phy.b[1].dq[6], 0x1 << 0, 0x1 << 0); - clrsetbits_le32(&ch[0].phy.ca_cmd[6], 0x3 << 0, 0x1 << 0); + setbits32(&ch[0].phy.b[0].dq[6], 0x1 << 9); + setbits32(&ch[0].phy.b[1].dq[6], 0x1 << 9); + setbits32(&ch[0].phy.ca_cmd[6], 0x1 << 9); + clrsetbits32(&ch[0].phy.b[0].dq[6], 0x3 << 0, 0x1 << 0); + clrsetbits32(&ch[0].phy.b[1].dq[6], 0x1 << 0, 0x1 << 0); + clrsetbits32(&ch[0].phy.ca_cmd[6], 0x3 << 0, 0x1 << 0); - setbits_le32(&ch[0].phy.ca_cmd[6], 0x1 << 6); - setbits_le32(&ch[0].phy.b[0].dq[6], 0x1 << 3); - setbits_le32(&ch[0].phy.b[1].dq[6], 0x1 << 3); - setbits_le32(&ch[0].phy.ca_cmd[6], 0x1 << 3); - setbits_le32(&ch[0].phy.b[0].dq[6], 0x1 << 5); - setbits_le32(&ch[0].phy.b[1].dq[6], 0x1 << 5); - setbits_le32(&ch[0].phy.ca_cmd[6], 0x1 << 5); + setbits32(&ch[0].phy.ca_cmd[6], 0x1 << 6); + setbits32(&ch[0].phy.b[0].dq[6], 0x1 << 3); + setbits32(&ch[0].phy.b[1].dq[6], 0x1 << 3); + setbits32(&ch[0].phy.ca_cmd[6], 0x1 << 3); + setbits32(&ch[0].phy.b[0].dq[6], 0x1 << 5); + setbits32(&ch[0].phy.b[1].dq[6], 0x1 << 5); + setbits32(&ch[0].phy.ca_cmd[6], 0x1 << 5); for (u8 b = 0; b < 2; b++) { - clrsetbits_le32(&ch[0].phy.shu[0].b[b].dq[5], 0x3f << 0, rx_vref << 0); - clrsetbits_le32(&ch[0].phy.b[b].dq[5], 0x3f << 8, rx_vref << 8); + clrsetbits32(&ch[0].phy.shu[0].b[b].dq[5], 0x3f << 0, rx_vref << 0); + clrsetbits32(&ch[0].phy.b[b].dq[5], 0x3f << 8, rx_vref << 8); } - setbits_le32(&ch[0].phy.b[0].dq[8], (0x1 << 0) | (0x1 << 1) | (0x1 << 2)); - setbits_le32(&ch[0].phy.b[1].dq[8], (0x1 << 0) | (0x1 << 1) | (0x1 << 2)); - setbits_le32(&ch[0].phy.ca_cmd[9], (0x1 << 0) | (0x1 << 1) | (0x1 << 2)); + setbits32(&ch[0].phy.b[0].dq[8], (0x1 << 0) | (0x1 << 1) | (0x1 << 2)); + setbits32(&ch[0].phy.b[1].dq[8], (0x1 << 0) | (0x1 << 1) | (0x1 << 2)); + setbits32(&ch[0].phy.ca_cmd[9], (0x1 << 0) | (0x1 << 1) | (0x1 << 2)); dramc_gating_mode(1); - setbits_le32(&ch[0].phy.ca_cmd[8], 0x1 << 19); - clrbits_le32(&ch[0].phy.ca_cmd[8], 0x1 << 18); - clrsetbits_le32(&ch[0].ao.shu[0].misc, 0xf << 0, 0x2 << 0); - clrsetbits_le32(&ch[0].ao.shu[0].dqsg, (0x3f << 20) | (0x1 << 16), + setbits32(&ch[0].phy.ca_cmd[8], 0x1 << 19); + clrbits32(&ch[0].phy.ca_cmd[8], 0x1 << 18); + clrsetbits32(&ch[0].ao.shu[0].misc, 0xf << 0, 0x2 << 0); + clrsetbits32(&ch[0].ao.shu[0].dqsg, (0x3f << 20) | (0x1 << 16), (0x2a << 20) | (0x1 << 16)); - clrbits_le32(&ch[0].phy.shu[0].b[0].dq[5], 0x3f << 8); - clrbits_le32(&ch[0].phy.shu[0].b[1].dq[5], 0x3f << 8); - clrbits_le32(&ch[0].phy.shu[0].ca_cmd[5], 0x3f << 8); + clrbits32(&ch[0].phy.shu[0].b[0].dq[5], 0x3f << 8); + clrbits32(&ch[0].phy.shu[0].b[1].dq[5], 0x3f << 8); + clrbits32(&ch[0].phy.shu[0].ca_cmd[5], 0x3f << 8); dramc_set_broadcast(DRAMC_BROADCAST_OFF); for (u8 chn = 0; chn < CHANNEL_MAX; chn++) { - clrbits_le32(&ch[chn].phy.shu[0].b[0].dq[6], 0x3f << 0); - clrbits_le32(&ch[chn].phy.shu[0].b[1].dq[6], 0x3f << 0); - clrbits_le32(&ch[chn].phy.shu[0].ca_cmd[6], 0x3f << 0); + clrbits32(&ch[chn].phy.shu[0].b[0].dq[6], 0x3f << 0); + clrbits32(&ch[chn].phy.shu[0].b[1].dq[6], 0x3f << 0); + clrbits32(&ch[chn].phy.shu[0].ca_cmd[6], 0x3f << 0); } dramc_set_broadcast(DRAMC_BROADCAST_ON); /* IMP Tracking Init Settings */ - clrsetbits_le32(&ch[0].ao.shu[0].impcal1, + clrsetbits32(&ch[0].ao.shu[0].impcal1, (0x7 << 0) | (0x7 << 17) | (0xff << 20) | (0xf << 28), (0x4 << 0) | (0x4 << 17) | (0x10 << 20) | (0x8 << 28)); - setbits_le32(&ch[0].ao.srefctrl, 0xf << 12); - setbits_le32(&ch[0].ao.pre_tdqsck[0], 0x1 << 17); - setbits_le32(&ch[0].ao.shu[0].misc, 0xf << 12); - clrsetbits_le32(&ch[0].phy.shu[0].b[0].dq[8], + setbits32(&ch[0].ao.srefctrl, 0xf << 12); + setbits32(&ch[0].ao.pre_tdqsck[0], 0x1 << 17); + setbits32(&ch[0].ao.shu[0].misc, 0xf << 12); + clrsetbits32(&ch[0].phy.shu[0].b[0].dq[8], (0xffff << 0) | (0x1 << 15) | (0x3ff << 22), (0x7fff << 0) | (0x0 << 15) | (0x3ff << 22)); - clrsetbits_le32(&ch[0].phy.shu[0].b[1].dq[8], + clrsetbits32(&ch[0].phy.shu[0].b[1].dq[8], (0xffff << 0) | (0x1 << 15) | (0x3ff << 22), (0x7fff << 0) | (0x0 << 15) | (0x3ff << 22)); - clrsetbits_le32(&ch[0].phy.shu[0].ca_cmd[8], + clrsetbits32(&ch[0].phy.shu[0].ca_cmd[8], (0xffff << 0) | (0x1 << 15) | (0x3ff << 22), (0x7fff << 0) | (0x0 << 15) | (0x3ff << 22)); - setbits_le32(&ch[0].phy.misc_ctrl3, 0x1 << 26); - clrbits_le32(&ch[0].phy.shu[0].b[0].dq[7], (0xf << 8) | (0x1 << 12) | (0x1 << 13)); - clrbits_le32(&ch[0].phy.shu[0].b[1].dq[7], (0xf << 8) | (0x1 << 12) | (0x1 << 13)); - clrsetbits_le32(&ch[0].ao.clkar, (0xffff << 0) | (0x1 << 15), + setbits32(&ch[0].phy.misc_ctrl3, 0x1 << 26); + clrbits32(&ch[0].phy.shu[0].b[0].dq[7], (0xf << 8) | (0x1 << 12) | (0x1 << 13)); + clrbits32(&ch[0].phy.shu[0].b[1].dq[7], (0xf << 8) | (0x1 << 12) | (0x1 << 13)); + clrsetbits32(&ch[0].ao.clkar, (0xffff << 0) | (0x1 << 15), (0x7fff << 0) | (0x1 << 15)); - clrbits_le32(&ch[0].ao.shu[0].dqsg_retry, 0x1 << 29); - clrbits_le32(&ch[0].ao.write_lev, 0x1 << 2); - setbits_le32(&ch[0].ao.dummy_rd, 0x1 << 24); - clrbits_le32(&ch[0].ao.stbcal2, (0x1 << 0) | (0x1 << 1)); - setbits_le32(&ch[0].ao.eyescan, (0x1 << 8) | (0x1 << 9) | (0x1 << 10)); - setbits_le32(&ch[0].ao.shu[0].odtctrl, (0x1 << 2) | (0x1 << 3)); + clrbits32(&ch[0].ao.shu[0].dqsg_retry, 0x1 << 29); + clrbits32(&ch[0].ao.write_lev, 0x1 << 2); + setbits32(&ch[0].ao.dummy_rd, 0x1 << 24); + clrbits32(&ch[0].ao.stbcal2, (0x1 << 0) | (0x1 << 1)); + setbits32(&ch[0].ao.eyescan, (0x1 << 8) | (0x1 << 9) | (0x1 << 10)); + setbits32(&ch[0].ao.shu[0].odtctrl, (0x1 << 2) | (0x1 << 3)); - setbits_le32(&ch[0].phy.shu[0].b[0].dll[0], 0x1 << 0); - setbits_le32(&ch[0].phy.shu[0].b[1].dll[0], 0x1 << 0); - setbits_le32(&ch[0].phy.ca_dll_fine_tune[1], 0x1 << 21); + setbits32(&ch[0].phy.shu[0].b[0].dll[0], 0x1 << 0); + setbits32(&ch[0].phy.shu[0].b[1].dll[0], 0x1 << 0); + setbits32(&ch[0].phy.ca_dll_fine_tune[1], 0x1 << 21); - setbits_le32(&ch[0].ao.perfctl0, (0x1 << 15) | (0x1 << 19) | (0x1 << 26)); - setbits_le32(&ch[0].ao.srefctrl, 0x1 << 22); - clrsetbits_le32(&ch[0].ao.shuctrl1, 0xff << 0, 0x1a << 0); - setbits_le32(&ch[0].phy.b[0].dq[6], (0x1 << 7) | (0x1 << 12)); - setbits_le32(&ch[0].phy.b[1].dq[6], (0x1 << 7) | (0x1 << 12)); - setbits_le32(&ch[0].phy.ca_cmd[6], (0x1 << 7) | (0x1 << 12)); - setbits_le32(&ch[0].ao.stbcal2, 0x1 << 16); - clrsetbits_le32(&ch[0].phy.shu[0].b[0].dq[7], + setbits32(&ch[0].ao.perfctl0, (0x1 << 15) | (0x1 << 19) | (0x1 << 26)); + setbits32(&ch[0].ao.srefctrl, 0x1 << 22); + clrsetbits32(&ch[0].ao.shuctrl1, 0xff << 0, 0x1a << 0); + setbits32(&ch[0].phy.b[0].dq[6], (0x1 << 7) | (0x1 << 12)); + setbits32(&ch[0].phy.b[1].dq[6], (0x1 << 7) | (0x1 << 12)); + setbits32(&ch[0].phy.ca_cmd[6], (0x1 << 7) | (0x1 << 12)); + setbits32(&ch[0].ao.stbcal2, 0x1 << 16); + clrsetbits32(&ch[0].phy.shu[0].b[0].dq[7], (0x7 << 29) | (0x1 << 28) | (0x7 << 25) | (0x1 << 24), (0x0 << 29) | (0x1 << 28) | (0x1 << 25) | (0x1 << 24)); - clrsetbits_le32(&ch[0].phy.shu[0].b[1].dq[7], + clrsetbits32(&ch[0].phy.shu[0].b[1].dq[7], (0x7 << 29) | (0x1 << 28) | (0x7 << 25) | (0x1 << 24), (0x0 << 29) | (0x1 << 28) | (0x1 << 25) | (0x1 << 24)); /* Disable RODT tracking */ - clrbits_le32(&ch[0].ao.shu[0].rodtenstb, 0x1 << 0); + clrbits32(&ch[0].ao.shu[0].rodtenstb, 0x1 << 0); /* Rx Gating tracking settings */ - clrsetbits_le32(&ch[0].ao.shu[0].dqsg, + clrsetbits32(&ch[0].ao.shu[0].dqsg, (0x1 << 11) | (0xf << 12), (0x1 << 11) | (0x9 << 12)); - clrbits_le32(&ch[0].ao.shu[0].rk[0].dqscal, (0x1 << 7) | (0x1 << 15)); - clrbits_le32(&ch[0].ao.shu[0].rk[1].dqscal, (0x1 << 7) | (0x1 << 15)); - clrsetbits_le32(&ch[0].ao.shu[0].stbcal, + clrbits32(&ch[0].ao.shu[0].rk[0].dqscal, (0x1 << 7) | (0x1 << 15)); + clrbits32(&ch[0].ao.shu[0].rk[1].dqscal, (0x1 << 7) | (0x1 << 15)); + clrsetbits32(&ch[0].ao.shu[0].stbcal, (0x7 << 4) | (0x1 << 8), (0x1 << 4) | (0x1 << 8)); - clrsetbits_le32(&ch[0].phy.b[0].dq[9], 0xff << 8, 0x4 << 8); - clrsetbits_le32(&ch[0].phy.b[1].dq[9], 0xff << 8, 0x4 << 8); - clrbits_le32(&ch[0].phy.ca_cmd[10], 0xff << 8); + clrsetbits32(&ch[0].phy.b[0].dq[9], 0xff << 8, 0x4 << 8); + clrsetbits32(&ch[0].phy.b[1].dq[9], 0xff << 8, 0x4 << 8); + clrbits32(&ch[0].phy.ca_cmd[10], 0xff << 8); - setbits_le32(&ch[0].phy.shu[0].b[0].dq[8], 0x1 << 24); - setbits_le32(&ch[0].phy.shu[0].b[1].dq[8], 0x1 << 24); + setbits32(&ch[0].phy.shu[0].b[0].dq[8], 0x1 << 24); + setbits32(&ch[0].phy.shu[0].b[1].dq[8], 0x1 << 24); /* Enable WDQS */ - clrsetbits_le32(&ch[0].phy.shu[0].b[0].dll[1], + clrsetbits32(&ch[0].phy.shu[0].b[0].dll[1], (0x1 << 10) | (0x1 << 16) | (0x1 << 17), (0x1 << 10) | (!operate_fsp << 16) | (0x1 << 17)); - clrsetbits_le32(&ch[0].phy.shu[0].b[1].dll[1], + clrsetbits32(&ch[0].phy.shu[0].b[1].dll[1], (0x1 << 10) | (0x1 << 16) | (0x1 << 17), (0x1 << 10) | (!operate_fsp << 16) | (0x1 << 17)); - setbits_le32(&ch[0].ao.shu[0].odtctrl, (0x1 << 0) | (0x1 << 30) | (0x1 << 31)); - setbits_le32(&ch[0].phy.shu[0].b[0].dq[7], 0x1 << 15); - setbits_le32(&ch[0].phy.shu[0].b[1].dq[7], 0x1 << 15); - setbits_le32(&ch[0].ao.drsctrl, 0x1 << 19); - setbits_le32(&ch[0].ao.refctrl0, 0x1 << 28); - setbits_le32(&ch[0].ao.zqcs, 0x1 << 19); - setbits_le32(&ch[0].ao.dummy_rd, 0x3 << 26); - setbits_le32(&ch[0].ao.shuctrl2, 0x1 << 8); - clrsetbits_le32(&ch[0].ao.shuctrl3, 0xff << 24, 0xb << 24); - setbits_le32(&ch[0].phy.misc_ctrl3, 0x1 << 27); - setbits_le32(&ch[0].phy.b[0].dll_fine_tune[1], 0x3 << 20); - setbits_le32(&ch[0].phy.b[1].dll_fine_tune[1], 0x3 << 20); - setbits_le32(&ch[0].phy.ca_dll_fine_tune[1], 0x1 << 20); - clrbits_le32(&ch[0].phy.misc_ctrl0, 0x1 << 27); - setbits_le32(&ch[0].phy.misc_rxdvs[2], 0x1 << 8); - setbits_le32(&ch[0].ao.clkctrl, 0x1 << 7); - setbits_le32(&ch[0].ao.refctrl1, 0x1 << 7); - clrsetbits_le32(&ch[0].ao.shuctrl, (0x1 << 2) | (0x3 << 6) | (0x3 << 26), + setbits32(&ch[0].ao.shu[0].odtctrl, (0x1 << 0) | (0x1 << 30) | (0x1 << 31)); + setbits32(&ch[0].phy.shu[0].b[0].dq[7], 0x1 << 15); + setbits32(&ch[0].phy.shu[0].b[1].dq[7], 0x1 << 15); + setbits32(&ch[0].ao.drsctrl, 0x1 << 19); + setbits32(&ch[0].ao.refctrl0, 0x1 << 28); + setbits32(&ch[0].ao.zqcs, 0x1 << 19); + setbits32(&ch[0].ao.dummy_rd, 0x3 << 26); + setbits32(&ch[0].ao.shuctrl2, 0x1 << 8); + clrsetbits32(&ch[0].ao.shuctrl3, 0xff << 24, 0xb << 24); + setbits32(&ch[0].phy.misc_ctrl3, 0x1 << 27); + setbits32(&ch[0].phy.b[0].dll_fine_tune[1], 0x3 << 20); + setbits32(&ch[0].phy.b[1].dll_fine_tune[1], 0x3 << 20); + setbits32(&ch[0].phy.ca_dll_fine_tune[1], 0x1 << 20); + clrbits32(&ch[0].phy.misc_ctrl0, 0x1 << 27); + setbits32(&ch[0].phy.misc_rxdvs[2], 0x1 << 8); + setbits32(&ch[0].ao.clkctrl, 0x1 << 7); + setbits32(&ch[0].ao.refctrl1, 0x1 << 7); + clrsetbits32(&ch[0].ao.shuctrl, (0x1 << 2) | (0x3 << 6) | (0x3 << 26), (0x0 << 2) | (0x3 << 6) | (0x3 << 26)); - setbits_le32(&ch[0].ao.shuctrl2, (0x1 << 31) | (0x3 << 10)); - clrbits_le32(&ch[0].ao.stbcal2, 0xf << 4); - clrbits_le32(&ch[0].ao.pre_tdqsck[0], 0x3 << 19); + setbits32(&ch[0].ao.shuctrl2, (0x1 << 31) | (0x3 << 10)); + clrbits32(&ch[0].ao.stbcal2, 0xf << 4); + clrbits32(&ch[0].ao.pre_tdqsck[0], 0x3 << 19); - setbits_le32(&ch[0].ao.ckectrl, 0x1 << 22); - clrsetbits_le32(&ch[0].phy.ca_tx_mck, (0x1 << 31) | (0x1f << 21) | (0x1f << 26), + setbits32(&ch[0].ao.ckectrl, 0x1 << 22); + clrsetbits32(&ch[0].phy.ca_tx_mck, (0x1 << 31) | (0x1f << 21) | (0x1f << 26), (0x1 << 31) | (0xa << 21) | (0xa << 26)); - setbits_le32(&ch[0].ao.ckectrl, 0x1 << 23); - clrbits_le32(&ch[0].ao.shu[0].rodtenstb, 0x1 << 31); + setbits32(&ch[0].ao.ckectrl, 0x1 << 23); + clrbits32(&ch[0].ao.shu[0].rodtenstb, 0x1 << 31); } static void dramc_power_on_sequence(void) { for (size_t chn = 0; chn < CHANNEL_MAX; chn++) - clrbits_le32(&ch[chn].phy.misc_ctrl1, 0x1 << 13); + clrbits32(&ch[chn].phy.misc_ctrl1, 0x1 << 13); dramc_cke_fix_onoff(CHANNEL_A, false, true); dramc_cke_fix_onoff(CHANNEL_B, false, true); udelay(200); for (size_t chn = 0; chn < CHANNEL_MAX; chn++) - setbits_le32(&ch[chn].phy.misc_ctrl1, 0x1 << 13); + setbits32(&ch[chn].phy.misc_ctrl1, 0x1 << 13); for (size_t chn = 0; chn < CHANNEL_MAX; chn++) - setbits_le32(&ch[chn].ao.dramc_pd_ctrl, 0x1 << 26); + setbits32(&ch[chn].ao.dramc_pd_ctrl, 0x1 << 26); udelay(2000); dramc_cke_fix_onoff(CHANNEL_A, true, false); @@ -571,22 +571,22 @@ static void ddr_phy_reserved_rg_setting(u8 freq_group) /* fine tune */ for (u8 chn = 0; chn < CHANNEL_MAX; chn++) - clrsetbits_le32(&ch[chn].phy.shu[0].ca_cmd[6], 0xffff << 6, + clrsetbits32(&ch[chn].phy.shu[0].ca_cmd[6], 0xffff << 6, (0x1 << 6) | ((!chn) << 7) | (hyst_sel << 8) | (midpi_cap_sel << 9) | (0x1 << 10) | (0x3 << 17) | (lp3_sel << 20)); for (u8 chn = 0; chn < CHANNEL_MAX; chn++) { - clrsetbits_le32(&ch[chn].phy.shu[0].ca_dll[1], + clrsetbits32(&ch[chn].phy.shu[0].ca_dll[1], (0xf << 9) | (0x1f << 16) | (0x7ff << 21), (0x1 << 8) | (0x7 << 13) | (0x4 << 16)); for (u8 b = 0; b < 2; b++) { - clrsetbits_le32(&ch[chn].phy.shu[0].b[b].dq[6], + clrsetbits32(&ch[chn].phy.shu[0].b[b].dq[6], (0x1f << 6) | (0x3f << 11) | (0x7 << 19), (0x1 << 6) | (hyst_sel << 8) | (midpi_cap_sel << 9) | (0x1 << 10) | (0x3 << 17) | (lp3_sel << 20)); - clrsetbits_le32(&ch[chn].phy.shu[0].b[b].dll[1], + clrsetbits32(&ch[chn].phy.shu[0].b[b].dll[1], (0x3 << 8) | (0x3 << 11) | (0x7 << 14) | (0x3fff << 18), (0x1 << 10) | (0x1 << 13) | (0x1 << 17)); } @@ -603,12 +603,12 @@ static void dramc_duty_set_clk_delay(u8 chn, s8 clkDelay) revb1 = dlyb ? 1 : 0; for (u8 r = 0; r < RANK_MAX; r++) { - clrsetbits_le32(&ch[chn].phy.shu[0].rk[r].ca_cmd[1], + clrsetbits32(&ch[chn].phy.shu[0].rk[r].ca_cmd[1], (0xf << 24) | (0xf << 28), (dly << 24) | (dly << 28)); - clrsetbits_le32(&ch[chn].phy.shu[0].rk[r].ca_cmd[0], + clrsetbits32(&ch[chn].phy.shu[0].rk[r].ca_cmd[0], (0xf << 24) | (0xf << 28), (dlyb << 24) | (dlyb << 28)); } - clrsetbits_le32(&ch[chn].phy.shu[0].ca_cmd[3], + clrsetbits32(&ch[chn].phy.shu[0].ca_cmd[3], (0x3 << 8), (revb0 << 8) | (revb1 << 9)); } @@ -625,11 +625,11 @@ static void dramc_duty_set_dqs_delay(u8 chn, const s8 *s_dqsDelay) dlyb = (dqsDelay < 0) ? 0 : dqsDelay; revb0 = dly ? 1 : 0; revb1 = dlyb ? 1 : 0; - clrsetbits_le32(&ch[chn].phy.shu[0].rk[r].b[dqs].dq[1], + clrsetbits32(&ch[chn].phy.shu[0].rk[r].b[dqs].dq[1], (0xf << 24) | (0xf << 28) | (0xf << 16) | (0xf << 20), (dly << 24) | (dly << 28) | (dlyb << 16) | (dlyb << 20)); } - clrsetbits_le32(&ch[chn].phy.shu[0].b[0].dll[1], + clrsetbits32(&ch[chn].phy.shu[0].b[0].dll[1], 0x3 << 8, (revb0 << 8) | (revb1 << 9)); } @@ -709,7 +709,7 @@ static u8 dramc_zq_calibration(u8 chn, u8 rank) for (size_t i = 0; i < ARRAY_SIZE(regs_bak); i++) regs_bak[i].value = read32(regs_bak[i].addr); - setbits_le32(&ch[chn].ao.dramc_pd_ctrl, 0x1 << 26); + setbits32(&ch[chn].ao.dramc_pd_ctrl, 0x1 << 26); dramc_cke_fix_onoff(chn, true, false); SET32_BITFIELDS(&ch[chn].ao.mrs, MRS_MRSRK, rank); @@ -794,7 +794,7 @@ static void dramc_mode_reg_init(u8 freq_group, struct mr_value *mr) for (chn = 0; chn < CHANNEL_MAX; chn++) { for (rank = 0; rank < 2; rank++) { - clrsetbits_le32(&ch[chn].ao.mrs, 0x3 << 24, rank << 24); + clrsetbits32(&ch[chn].ao.mrs, 0x3 << 24, rank << 24); dramc_zq_calibration(chn, rank); @@ -827,21 +827,21 @@ static void dramc_mode_reg_init(u8 freq_group, struct mr_value *mr) dramc_mode_reg_write(chn, 0xd, MR13Value); } - clrsetbits_le32(&ch[chn].ao.shu[0].hwset_mr13, + clrsetbits32(&ch[chn].ao.shu[0].hwset_mr13, (0x1fff << 0) | (0xff << 16), (13 << 0) | ((MR13Value | (0x1 << 3)) << 16)); - clrsetbits_le32(&ch[chn].ao.shu[0].hwset_vrcg, + clrsetbits32(&ch[chn].ao.shu[0].hwset_vrcg, (0x1fff << 0) | (0xff << 16), (13 << 0) | ((MR13Value | (0x1 << 3)) << 16)); - clrsetbits_le32(&ch[chn].ao.shu[0].hwset_mr2, + clrsetbits32(&ch[chn].ao.shu[0].hwset_mr2, (0x1fff << 0) | (0xff << 16), (2 << 0) | (MR02Value[operate_fsp] << 16)); } mr->MR13Value = MR13Value; - clrsetbits_le32(&ch[0].ao.mrs, 0x3 << 24, RANK_0 << 24); - clrsetbits_le32(&ch[1].ao.mrs, 0x3 << 24, RANK_0 << 24); + clrsetbits32(&ch[0].ao.mrs, 0x3 << 24, RANK_0 << 24); + clrsetbits32(&ch[1].ao.mrs, 0x3 << 24, RANK_0 << 24); dramc_set_broadcast(broadcast_bak); } @@ -851,7 +851,7 @@ static void auto_refresh_cke_off(void) dramc_set_broadcast(DRAMC_BROADCAST_OFF); for (u8 chn = 0; chn < CHANNEL_MAX; chn++) - setbits_le32(&ch[chn].ao.refctrl0, 0x1 << 29); + setbits32(&ch[chn].ao.refctrl0, 0x1 << 29); udelay(3); cke_fix_onoff(CKE_FIXOFF, CHANNEL_A); @@ -862,57 +862,57 @@ static void auto_refresh_cke_off(void) static void dramc_setting_DDR1600(void) { - clrsetbits_le32(&ch[0].ao.shu[0].rankctl, + clrsetbits32(&ch[0].ao.shu[0].rankctl, (0xf << 20) | (0xf << 24) | (0xf << 28), (0x0 << 20) | (0x0 << 24) | (0x2 << 28)); - clrbits_le32(&ch[0].ao.shu[0].ckectrl, 0x3 << 24); - clrbits_le32(&ch[0].ao.shu[0].odtctrl, (0x1 << 0) | (0x3 << 30)); + clrbits32(&ch[0].ao.shu[0].ckectrl, 0x3 << 24); + clrbits32(&ch[0].ao.shu[0].odtctrl, (0x1 << 0) | (0x3 << 30)); - clrbits_le32(&ch[0].phy.shu[0].b[0].dq[7], 0x1 << 15); - clrbits_le32(&ch[0].phy.shu[0].b[1].dq[7], 0x1 << 15); + clrbits32(&ch[0].phy.shu[0].b[0].dq[7], 0x1 << 15); + clrbits32(&ch[0].phy.shu[0].b[1].dq[7], 0x1 << 15); - clrsetbits_le32(&ch[0].ao.shu[0].selph_dqs0, 0x77777777, SELPH_DQS0_1600); - clrsetbits_le32(&ch[0].ao.shu[0].selph_dqs1, 0x77777777, SELPH_DQS1_1600); - clrsetbits_le32(&ch[0].ao.shu[0].wodt, (0x1 << 29) | (0x1 << 31), + clrsetbits32(&ch[0].ao.shu[0].selph_dqs0, 0x77777777, SELPH_DQS0_1600); + clrsetbits32(&ch[0].ao.shu[0].selph_dqs1, 0x77777777, SELPH_DQS1_1600); + clrsetbits32(&ch[0].ao.shu[0].wodt, (0x1 << 29) | (0x1 << 31), (0x0 << 29) | (0x1 << 31)); - clrsetbits_le32(&ch[0].ao.shu[0].dqs2dq_tx, 0x1f << 0, 0x4 << 0); + clrsetbits32(&ch[0].ao.shu[0].dqs2dq_tx, 0x1f << 0, 0x4 << 0); for (size_t rank = 0; rank < 2; rank++) { int value = ((rank == 0) ? 0x1a : 0x1e); - clrbits_le32(&ch[0].ao.shu[0].rk[rank].dqsien, (0x7f << 0) | (0x7f << 8)); - clrsetbits_le32(&ch[0].ao.shu[0].rk[rank].fine_tune, + clrbits32(&ch[0].ao.shu[0].rk[rank].dqsien, (0x7f << 0) | (0x7f << 8)); + clrsetbits32(&ch[0].ao.shu[0].rk[rank].fine_tune, (0x3f << 0) | (0x3f << 8) | (0x3f << 16) | (0x3f << 24), (value << 0) | (value << 8) | (value << 16) | (value << 24)); - clrsetbits_le32(&ch[0].ao.shu[0].rk[rank].selph_dq[0], + clrsetbits32(&ch[0].ao.shu[0].rk[rank].selph_dq[0], (0x7 << 8) | (0x7 << 12) | (0x7 << 16) | (0x7 << 20) | (0x7 << 24) | (0x7 << 28), (0x2 << 8) | (0x2 << 12) | (0x1 << 16) | (0x1 << 20) | (0x1 << 24) | (0x1 << 28)); - clrsetbits_le32(&ch[0].ao.shu[0].rk[rank].selph_dq[1], + clrsetbits32(&ch[0].ao.shu[0].rk[rank].selph_dq[1], (0x7 << 8) | (0x7 << 12) | (0x7 << 16) | (0x7 << 20) | (0x7 << 24) | (0x7 << 28), (0x2 << 8) | (0x2 << 12) | (0x1 << 16) | (0x1 << 20) | (0x1 << 24) | (0x1 << 28)); - clrsetbits_le32(&ch[0].ao.shu[0].rk[rank].selph_dq[2], + clrsetbits32(&ch[0].ao.shu[0].rk[rank].selph_dq[2], 0x77777777, _SELPH_DQS_BITS(0x1, 0x7)); - clrsetbits_le32(&ch[0].ao.shu[0].rk[rank].selph_dq[3], + clrsetbits32(&ch[0].ao.shu[0].rk[rank].selph_dq[3], 0x77777777, _SELPH_DQS_BITS(0x1, 0x7)); } - clrsetbits_le32(&ch[0].ao.shu[0].dqsg_retry, (0x1 << 2) | (0xf << 8), + clrsetbits32(&ch[0].ao.shu[0].dqsg_retry, (0x1 << 2) | (0xf << 8), (0x0 << 2) | (0x3 << 8)); - clrsetbits_le32(&ch[0].phy.b[0].dq[5], 0x7 << 20, 0x4 << 20); + clrsetbits32(&ch[0].phy.b[0].dq[5], 0x7 << 20, 0x4 << 20); - clrsetbits_le32(&ch[0].phy.b[0].dq[7], (0x3 << 4) | (0x1 << 7) | (0x1 << 13), + clrsetbits32(&ch[0].phy.b[0].dq[7], (0x3 << 4) | (0x1 << 7) | (0x1 << 13), (0x2 << 4) | (0x0 << 7) | (0x0 << 13)); - clrsetbits_le32(&ch[0].phy.b[1].dq[5], 0x7 << 20, 0x4 << 20); - clrbits_le32(&ch[0].phy.b[1].dq[7], (0x1 << 7) | (0x1 << 13)); + clrsetbits32(&ch[0].phy.b[1].dq[5], 0x7 << 20, 0x4 << 20); + clrbits32(&ch[0].phy.b[1].dq[7], (0x1 << 7) | (0x1 << 13)); for (size_t r = 0; r < 2; r++) { int value = ((r == 0) ? 0x1a : 0x26); for (size_t b = 0; b < 2; b++) - clrsetbits_le32(&ch[0].phy.shu[0].rk[r].b[b].dq[7], + clrsetbits32(&ch[0].phy.shu[0].rk[r].b[b].dq[7], (0x3f << 8) | (0x3f << 16), (value << 8) | (value << 16)); } @@ -920,65 +920,65 @@ static void dramc_setting_DDR1600(void) static void dramc_setting_DDR2400(void) { - clrsetbits_le32(&ch[0].ao.shu[0].rankctl, + clrsetbits32(&ch[0].ao.shu[0].rankctl, (0xf << 20) | (0xf << 24) | (0xf << 28), (0x2 << 20) | (0x2 << 24) | (0x4 << 28)); - clrsetbits_le32(&ch[0].ao.shu[0].ckectrl, 0x3 << 24, 0x3 << 24); - setbits_le32(&ch[0].ao.shu[0].odtctrl, (0x1 << 0) | (0x1 << 30) | (0x1 << 31)); + clrsetbits32(&ch[0].ao.shu[0].ckectrl, 0x3 << 24, 0x3 << 24); + setbits32(&ch[0].ao.shu[0].odtctrl, (0x1 << 0) | (0x1 << 30) | (0x1 << 31)); - setbits_le32(&ch[0].phy.shu[0].b[0].dq[7], 0x1 << 15); - setbits_le32(&ch[0].phy.shu[0].b[1].dq[7], 0x1 << 15); + setbits32(&ch[0].phy.shu[0].b[0].dq[7], 0x1 << 15); + setbits32(&ch[0].phy.shu[0].b[1].dq[7], 0x1 << 15); - clrsetbits_le32(&ch[0].ao.shu[0].selph_dqs0, 0x77777777, SELPH_DQS0_2400); - clrsetbits_le32(&ch[0].ao.shu[0].selph_dqs1, 0x77777777, SELPH_DQS1_2400); - clrsetbits_le32(&ch[0].ao.shu[0].wodt, + clrsetbits32(&ch[0].ao.shu[0].selph_dqs0, 0x77777777, SELPH_DQS0_2400); + clrsetbits32(&ch[0].ao.shu[0].selph_dqs1, 0x77777777, SELPH_DQS1_2400); + clrsetbits32(&ch[0].ao.shu[0].wodt, (0x1 << 29) | (0x1 << 31), (0x1 << 29) | (0x0 << 31)); - clrsetbits_le32(&ch[0].ao.shu[0].dqs2dq_tx, 0x1f << 0, 0x7 << 0); + clrsetbits32(&ch[0].ao.shu[0].dqs2dq_tx, 0x1f << 0, 0x7 << 0); for (size_t rank = 0; rank < 2; rank++) { int value = ((rank == 0) ? 0x19 : 0x1f); - clrsetbits_le32(&ch[0].ao.shu[0].rk[rank].dqsien, + clrsetbits32(&ch[0].ao.shu[0].rk[rank].dqsien, (0x7f << 0) | (0x7f << 8), (value << 0) | (value << 8)); - clrsetbits_le32(&ch[0].ao.shu[0].rk[rank].fine_tune, + clrsetbits32(&ch[0].ao.shu[0].rk[rank].fine_tune, (0x3f << 0) | (0x3f << 8) | (0x3f << 16) | (0x3f << 24), (0x14 << 0) | (0x14 << 8) | (0x14 << 16) | (0x14 << 24)); - clrsetbits_le32(&ch[0].ao.shu[0].rk[rank].selph_dq[0], + clrsetbits32(&ch[0].ao.shu[0].rk[rank].selph_dq[0], (0x7 << 8) | (0x7 << 12) | (0x7 << 16) | (0x7 << 20) | (0x7 << 24) | (0x7 << 28), (0x3 << 8) | (0x3 << 12) | (0x3 << 16) | (0x3 << 20) | (0x3 << 24) | (0x3 << 28)); - clrsetbits_le32(&ch[0].ao.shu[0].rk[rank].selph_dq[1], + clrsetbits32(&ch[0].ao.shu[0].rk[rank].selph_dq[1], (0x7 << 8) | (0x7 << 12) | (0x7 << 16) | (0x7 << 20) | (0x7 << 24) | (0x7 << 28), (0x3 << 8) | (0x3 << 12) | (0x3 << 16) | (0x3 << 20) | (0x3 << 24) | (0x3 << 28)); - clrsetbits_le32(&ch[0].ao.shu[0].rk[rank].selph_dq[2], + clrsetbits32(&ch[0].ao.shu[0].rk[rank].selph_dq[2], 0x77777777, _SELPH_DQS_BITS(0x2, 0x0)); - clrsetbits_le32(&ch[0].ao.shu[0].rk[rank].selph_dq[3], + clrsetbits32(&ch[0].ao.shu[0].rk[rank].selph_dq[3], 0x77777777, _SELPH_DQS_BITS(0x2, 0x0)); } - clrsetbits_le32(&ch[0].ao.shu[0].dqsg_retry, + clrsetbits32(&ch[0].ao.shu[0].dqsg_retry, (0x1 << 2) | (0xf << 8), (0x1 << 2) | (0x4 << 8)); - clrsetbits_le32(&ch[0].phy.b[0].dq[5], 0x7 << 20, 0x3 << 20); - clrsetbits_le32(&ch[0].phy.b[0].dq[7], (0x3 << 4) | (0x1 << 7) | (0x1 << 13), + clrsetbits32(&ch[0].phy.b[0].dq[5], 0x7 << 20, 0x3 << 20); + clrsetbits32(&ch[0].phy.b[0].dq[7], (0x3 << 4) | (0x1 << 7) | (0x1 << 13), (0x1 << 4) | (0x1 << 7) | (0x1 << 13)); - clrsetbits_le32(&ch[0].phy.b[1].dq[5], 0x7 << 20, 0x3 << 20); - clrsetbits_le32(&ch[0].phy.b[1].dq[7], + clrsetbits32(&ch[0].phy.b[1].dq[5], 0x7 << 20, 0x3 << 20); + clrsetbits32(&ch[0].phy.b[1].dq[7], (0x1 << 7) | (0x1 << 13), (0x1 << 7) | (0x1 << 13)); for (size_t r = 0; r < 2; r++) { for (size_t b = 0; b < 2; b++) - clrsetbits_le32(&ch[0].phy.shu[0].rk[r].b[b].dq[7], + clrsetbits32(&ch[0].phy.shu[0].rk[r].b[b].dq[7], (0x3f << 8) | (0x3f << 16), (0x14 << 8) | (0x14 << 16)); } } static void dramc_setting_DDR3600(void) { - clrsetbits_le32(&ch[0].ao.shu[0].selph_dqs0, 0x77777777, SELPH_DQS0_3600); - clrsetbits_le32(&ch[0].ao.shu[0].selph_dqs1, 0x77777777, SELPH_DQS1_3600); + clrsetbits32(&ch[0].ao.shu[0].selph_dqs0, 0x77777777, SELPH_DQS0_3600); + clrsetbits32(&ch[0].ao.shu[0].selph_dqs1, 0x77777777, SELPH_DQS1_3600); } static void dramc_setting(const struct sdram_params *params, u8 freq_group, @@ -990,158 +990,158 @@ static void dramc_setting(const struct sdram_params *params, u8 freq_group, dramc_set_broadcast(DRAMC_BROADCAST_OFF); for (chn = 0; chn < CHANNEL_MAX; chn++) - setbits_le32(&ch[chn].phy.ckmux_sel, (0x1 << 0) | (0x1 << 1)); + setbits32(&ch[chn].phy.ckmux_sel, (0x1 << 0) | (0x1 << 1)); dramc_set_broadcast(DRAMC_BROADCAST_ON); - setbits_le32(&ch[0].phy.misc_cg_ctrl0, 0x1 << 0); + setbits32(&ch[0].phy.misc_cg_ctrl0, 0x1 << 0); /* 26M */ - clrbits_le32(&ch[0].phy.misc_cg_ctrl0, 0x3 << 4); - clrbits_le32(&ch[0].phy.misc_ctrl0, 0x1 << 17); + clrbits32(&ch[0].phy.misc_cg_ctrl0, 0x3 << 4); + clrbits32(&ch[0].phy.misc_ctrl0, 0x1 << 17); - clrbits_le32(&ch[0].phy.misc_spm_ctrl1, 0xf << 0); + clrbits32(&ch[0].phy.misc_spm_ctrl1, 0xf << 0); write32(&ch[0].phy.misc_spm_ctrl2, 0x0); write32(&ch[0].phy.misc_spm_ctrl0, 0x0); write32(&ch[0].phy.misc_cg_ctrl2, 0x6003bf); write32(&ch[0].phy.misc_cg_ctrl4, 0x333f3f00); - setbits_le32(&ch[0].phy.shu[0].pll[1], (0x1 << 4) | (0x7 << 1)); - clrsetbits_le32(&ch[0].phy.shu[0].b[0].dq[7], 0x3f << 0, 0x10 << 0); - clrbits_le32(&ch[0].phy.shu[0].b[1].dq[7], 0x0f << 0); + setbits32(&ch[0].phy.shu[0].pll[1], (0x1 << 4) | (0x7 << 1)); + clrsetbits32(&ch[0].phy.shu[0].b[0].dq[7], 0x3f << 0, 0x10 << 0); + clrbits32(&ch[0].phy.shu[0].b[1].dq[7], 0x0f << 0); for (size_t b = 0; b <= 2; b += 2) - clrsetbits_le32(&ch[0].phy.shu[0].pll[4 + b], + clrsetbits32(&ch[0].phy.shu[0].pll[4 + b], (0x3 << 18) | (0x3 << 24) | (0x3 << 26), (0x2 << 18) | (0x1 << 24) | (0x1 << 26)); - clrbits_le32(&ch[0].phy.shu[0].pll[14], 0x1 << 1); - clrbits_le32(&ch[0].phy.shu[0].pll20, 0x1 << 1); - clrbits_le32(&ch[0].phy.ca_cmd[2], (0x3 << 16) | (0x3 << 20)); + clrbits32(&ch[0].phy.shu[0].pll[14], 0x1 << 1); + clrbits32(&ch[0].phy.shu[0].pll20, 0x1 << 1); + clrbits32(&ch[0].phy.ca_cmd[2], (0x3 << 16) | (0x3 << 20)); for (size_t b = 0; b < 2; b++) - clrbits_le32(&ch[0].phy.b[b].dq[2], (0x3 << 16) | (0x3 << 20)); + clrbits32(&ch[0].phy.b[b].dq[2], (0x3 << 16) | (0x3 << 20)); for (size_t b = 0; b < 2; b++) - clrsetbits_le32(&ch[0].phy.b[b].dq[9], 0x7 << 28, 0x1 << 28); - clrbits_le32(&ch[0].phy.ca_cmd[10], 0x7 << 28); + clrsetbits32(&ch[0].phy.b[b].dq[9], 0x7 << 28, 0x1 << 28); + clrbits32(&ch[0].phy.ca_cmd[10], 0x7 << 28); - setbits_le32(&ch[0].phy.b0_rxdvs[0], 0x1 << 28); - setbits_le32(&ch[0].phy.b1_rxdvs[0], 0x1 << 28); - setbits_le32(&ch[0].phy.b0_rxdvs[0], 0x1 << 9); - setbits_le32(&ch[0].phy.b1_rxdvs[0], 0x1 << 9); + setbits32(&ch[0].phy.b0_rxdvs[0], 0x1 << 28); + setbits32(&ch[0].phy.b1_rxdvs[0], 0x1 << 28); + setbits32(&ch[0].phy.b0_rxdvs[0], 0x1 << 9); + setbits32(&ch[0].phy.b1_rxdvs[0], 0x1 << 9); for (size_t b = 0; b < 2; b++) { for (size_t r = 0; r < 2; r++) - setbits_le32(&ch[0].phy.r[r].b[b].rxdvs[2], 0x1 << 29); - clrsetbits_le32(&ch[0].phy.shu[0].b[b].dq[5], 0x7 << 20, 0x3 << 20); + setbits32(&ch[0].phy.r[r].b[b].rxdvs[2], 0x1 << 29); + clrsetbits32(&ch[0].phy.shu[0].b[b].dq[5], 0x7 << 20, 0x3 << 20); for (size_t r = 0; r < 2; r++) { - clrsetbits_le32(&ch[0].phy.r[r].b[b].rxdvs[1], + clrsetbits32(&ch[0].phy.r[r].b[b].rxdvs[1], (0xffff << 0) | (0xffff << 16), (0x2 << 0) | (0x2 << 16)); - clrsetbits_le32(&ch[0].phy.r[r].b[b].rxdvs[2], + clrsetbits32(&ch[0].phy.r[r].b[b].rxdvs[2], (0x1 << 23) | (0x1 << 28) | (0x3 << 30), (0x1 << 23) | (0x1 << 28) | (0x2 << 30)); } } - clrbits_le32(&ch[0].phy.b0_rxdvs[0], 0x1 << 28); - clrbits_le32(&ch[0].phy.b1_rxdvs[0], 0x1 << 28); + clrbits32(&ch[0].phy.b0_rxdvs[0], 0x1 << 28); + clrbits32(&ch[0].phy.b1_rxdvs[0], 0x1 << 28); for (size_t b = 0; b < 2; b++) { - setbits_le32(&ch[0].phy.b[b].dq[9], 0x1 << 0); + setbits32(&ch[0].phy.b[b].dq[9], 0x1 << 0); for (size_t r = 0; r < 2; r++) - clrsetbits_le32(&ch[0].phy.shu[0].rk[r].b[b].dq[7], + clrsetbits32(&ch[0].phy.shu[0].rk[r].b[b].dq[7], (0x3f << 8) | (0x3f << 16), (0x1f << 8) | (0x1f << 16)); - clrsetbits_le32(&ch[0].phy.b[b].dq[4], + clrsetbits32(&ch[0].phy.b[b].dq[4], (0x7f << 0) | (0x7f << 8), (0x10 << 0) | (0x10 << 8)); - clrsetbits_le32(&ch[0].phy.b[b].dq[5], + clrsetbits32(&ch[0].phy.b[b].dq[5], (0xff << 0) | (0x3f << 8) | (0x1 << 16) | (0xf << 20) | (0x1 << 24), (0x10 << 0) | (0xe << 8) | (0x1 << 16) | (0x1 << 20) | (0x0 << 24)); - clrsetbits_le32(&ch[0].phy.b[b].dq[6], + clrsetbits32(&ch[0].phy.b[b].dq[6], (0x1 << 4) | (0x1 << 7) | (0x1 << 12) | (0x3 << 14) | (0xf << 16) | (0x1 << 24), (0x0 << 4) | (0x1 << 7) | (0x1 << 12) | (0x0 << 14) | (0x3 << 16) | (0x1 << 24)); - clrsetbits_le32(&ch[0].phy.b[b].dq[5], + clrsetbits32(&ch[0].phy.b[b].dq[5], (0xff << 0) | (0x1 << 25), (0x0 << 0) | (0x1 << 25)); } - setbits_le32(&ch[0].phy.ca_cmd[3], (0x3 << 2) | (0x1 << 7)); - clrsetbits_le32(&ch[0].phy.ca_cmd[6], (0x1 << 6) | (0x3 << 14) | (0x1 << 16), + setbits32(&ch[0].phy.ca_cmd[3], (0x3 << 2) | (0x1 << 7)); + clrsetbits32(&ch[0].phy.ca_cmd[6], (0x1 << 6) | (0x3 << 14) | (0x1 << 16), (0x0 << 6) | (0x0 << 14) | (0x0 << 16)); - clrbits_le32(&ch[0].phy.pll3, 0x1 < 0); - setbits_le32(&ch[0].phy.b[0].dq[3], 0x1 << 3); - setbits_le32(&ch[0].phy.b[1].dq[3], 0x1 << 3); + clrbits32(&ch[0].phy.pll3, 0x1 < 0); + setbits32(&ch[0].phy.b[0].dq[3], 0x1 << 3); + setbits32(&ch[0].phy.b[1].dq[3], 0x1 << 3); udelay(1); - clrsetbits_le32(&ch[0].phy.shu[0].pll[8], + clrsetbits32(&ch[0].phy.shu[0].pll[8], (0x7 << 0) | (0x3 << 18), (0x0 << 0) | (0x1 << 18)); udelay(1); - clrbits_le32(&ch[0].phy.shu[0].pll[9], + clrbits32(&ch[0].phy.shu[0].pll[9], (0x3 << 8) | (0x1 << 12) | (0x3 << 14) | (0x1 << 16)); - clrbits_le32(&ch[0].phy.shu[0].pll[11], + clrbits32(&ch[0].phy.shu[0].pll[11], (0x3 << 8) | (0x1 << 12) | (0x3 << 14) | (0x1 << 16)); udelay(1); - clrsetbits_le32(&ch[0].phy.shu[0].pll[10], + clrsetbits32(&ch[0].phy.shu[0].pll[10], (0x7 << 0) | (0x3 << 18), (0x0 << 0) | (0x1 << 18)); udelay(1); /* PLL EN */ /* MID FINE_TUNE Init 1 */ - clrsetbits_le32(&ch[0].phy.pll4, (0x3 << 18) | (0x1 << 21), 0x3 << 18); + clrsetbits32(&ch[0].phy.pll4, (0x3 << 18) | (0x1 << 21), 0x3 << 18); udelay(1); - clrsetbits_le32(&ch[0].phy.shu[0].pll[0], 0xffff << 0, 0x3 << 0); + clrsetbits32(&ch[0].phy.shu[0].pll[0], 0xffff << 0, 0x3 << 0); udelay(1); - setbits_le32(&ch[0].phy.ca_dll_fine_tune[1], 0x1 << 21); + setbits32(&ch[0].phy.ca_dll_fine_tune[1], 0x1 << 21); for (size_t b = 0; b < 2; b++) - setbits_le32(&ch[0].phy.b[b].dq[3], (0x3 << 1) | (0x1 << 10)); - setbits_le32(&ch[0].phy.shu[0].ca_dll[0], 0x1 << 0); + setbits32(&ch[0].phy.b[b].dq[3], (0x3 << 1) | (0x1 << 10)); + setbits32(&ch[0].phy.shu[0].ca_dll[0], 0x1 << 0); for (size_t b = 0; b < 2; b++) - clrsetbits_le32(&ch[0].phy.shu[0].b[b].dll[0], + clrsetbits32(&ch[0].phy.shu[0].b[b].dll[0], (0x1 << 4) | (0x3 << 9) | (0xf << 12) | (0xf << 16) | (0xf << 20) | (0x1 << 30), (0x0 << 4) | (0x3 << 9) | (0x8 << 12) | (0x7 << 16) | (0x7 << 20) | (0x1 << 30)); - clrbits_le32(&ch[0].phy.shu[0].ca_cmd[5], 0x3f << 0); - clrsetbits_le32(&ch[0].phy.shu[0].ca_cmd[0], + clrbits32(&ch[0].phy.shu[0].ca_cmd[5], 0x3f << 0); + clrsetbits32(&ch[0].phy.shu[0].ca_cmd[0], (0x1 << 4) | (0x7 << 12) | (0x1 << 20), (0x1 << 4) | (0x4 << 12) | (0x1 << 20)); dramc_set_broadcast(DRAMC_BROADCAST_OFF); - clrsetbits_le32(&ch[0].phy.shu[0].ca_cmd[6], 0xffff << 6, 0x3 << 6); - clrsetbits_le32(&ch[1].phy.shu[0].ca_cmd[6], 0xffff << 6, 0x1 << 6); + clrsetbits32(&ch[0].phy.shu[0].ca_cmd[6], 0xffff << 6, 0x3 << 6); + clrsetbits32(&ch[1].phy.shu[0].ca_cmd[6], 0xffff << 6, 0x1 << 6); dramc_set_broadcast(DRAMC_BROADCAST_ON); for (size_t b = 0; b < 2; b++) - clrsetbits_le32(&ch[0].phy.shu[0].b[b].dq[6], 0xffff << 6, 0x1 << 6); + clrsetbits32(&ch[0].phy.shu[0].b[b].dq[6], 0xffff << 6, 0x1 << 6); dramc_set_broadcast(DRAMC_BROADCAST_OFF); for (chn = 0; chn < CHANNEL_MAX; chn++) - clrsetbits_le32(&ch[chn].phy.misc_shu_opt, + clrsetbits32(&ch[chn].phy.misc_shu_opt, (0x1 << 0) | (0x3 << 2) | (0x1 << 8) | (0x3 << 10) | (0x1 << 16) | (0x3 << 18), (0x1 << 0) | (0x2 << 2) | (0x1 << 8) | (0x2 << 10) | (0x1 << 16) | ((0x1 + chn) << 18)); udelay(9); - clrsetbits_le32(&ch[0].phy.shu[0].ca_dll[1], (0x1 << 0) | (0x1 << 2), 0x1 << 2); - clrsetbits_le32(&ch[1].phy.shu[0].ca_dll[1], (0x1 << 0) | (0x1 << 2), 0x1 << 0); + clrsetbits32(&ch[0].phy.shu[0].ca_dll[1], (0x1 << 0) | (0x1 << 2), 0x1 << 2); + clrsetbits32(&ch[1].phy.shu[0].ca_dll[1], (0x1 << 0) | (0x1 << 2), 0x1 << 0); dramc_set_broadcast(DRAMC_BROADCAST_ON); for (size_t b = 0; b < 2; b++) - clrsetbits_le32(&ch[0].phy.shu[0].b[b].dll[1], + clrsetbits32(&ch[0].phy.shu[0].b[b].dll[1], (0x1 << 0) | (0x1 << 2), (0x1 << 0) | (0x0 << 2)); udelay(1); - clrbits_le32(&ch[0].phy.pll2, 0x1 << 31); - clrsetbits_le32(&ch[0].phy.misc_cg_ctrl0, 0xffffffff, 0xf); + clrbits32(&ch[0].phy.pll2, 0x1 << 31); + clrsetbits32(&ch[0].phy.misc_cg_ctrl0, 0xffffffff, 0xf); udelay(1); dramc_set_broadcast(DRAMC_BROADCAST_OFF); @@ -1150,241 +1150,241 @@ static void dramc_setting(const struct sdram_params *params, u8 freq_group, ddr_phy_pll_setting(chn, freq_group); dramc_set_broadcast(DRAMC_BROADCAST_ON); - setbits_le32(&ch[0].ao.drsctrl, 0x1 << 29); + setbits32(&ch[0].ao.drsctrl, 0x1 << 29); /* Set Run time MRR CKE fix to 1 in tMRRI old mode * to avoid no ACK from precharge all */ - setbits_le32(&ch[0].ao.ckectrl, 0x1 << 27); - clrsetbits_le32(&ch[0].ao.dramctrl, + setbits32(&ch[0].ao.ckectrl, 0x1 << 27); + clrsetbits32(&ch[0].ao.dramctrl, (0x1 << 15) | (0x1 << 17) | (0x1 << 23), (0x0 << 15) | (0x1 << 17) | (0x1 << 23)); - setbits_le32(&ch[0].ao.spcmdctrl, (0x1 << 1) | (0x1 << 8) | (0x1 << 9) | (0x1 << 10)); - setbits_le32(&ch[0].phy.b[0].dq[9], 0x1 << 4); - setbits_le32(&ch[0].phy.b[1].dq[9], 0x1 << 4); + setbits32(&ch[0].ao.spcmdctrl, (0x1 << 1) | (0x1 << 8) | (0x1 << 9) | (0x1 << 10)); + setbits32(&ch[0].phy.b[0].dq[9], 0x1 << 4); + setbits32(&ch[0].phy.b[1].dq[9], 0x1 << 4); - clrsetbits_le32(&ch[0].ao.shu[0].rk[1].dqsien, + clrsetbits32(&ch[0].ao.shu[0].rk[1].dqsien, (0x7f << 0) | (0x7f << 8) | (0x7f << 16) | (0x7f << 24), (0xf << 0) | (0xf << 8) | (0xf << 16) | (0xf << 24)); - clrsetbits_le32(&ch[0].ao.stbcal1, + clrsetbits32(&ch[0].ao.stbcal1, (0x1 << 4) | (0x1 << 8) | (0x1 << 12), (0x1 << 4) | (0x1 << 8)); - clrsetbits_le32(&ch[0].ao.shu[0].dqsg_retry, + clrsetbits32(&ch[0].ao.shu[0].dqsg_retry, (0x1 << 3) | (0xf << 8) | (0x1 << 21) | (0x1 << 31), (0x1 << 3) | (0x6 << 8) | (0x1 << 21) | (0x1 << 31)); for (size_t i = 0; i < 4; i++) { - clrsetbits_le32(&ch[0].ao.shu[0].drving[i], + clrsetbits32(&ch[0].ao.shu[0].drving[i], (0x1f << 0) | (0x1f << 5) | (0x1f << 10) | (0x1f << 15) | (0x1f << 20) | (0x1f << 25), (0xa << 0) | (0xa << 5) | (0xa << 10) | (0xa << 15) | (0xa << 20) | (0xa << 25)); } - clrsetbits_le32(&ch[0].ao.shuctrl2, + clrsetbits32(&ch[0].ao.shuctrl2, (0x3f << 0) | (0x1 << 12) | (0x1 << 14) | (0x1 << 15) | (0xff << 16) | (0x1 << 24), (0xa << 0) | (0x1 << 12) | (0x1 << 14) | (0x1 << 15) | (0x1 << 16) | (0x0 << 24)); - setbits_le32(&ch[0].ao.dvfsdll, 0x1 << 0); - setbits_le32(&ch[0].ao.ddrconf0, + setbits32(&ch[0].ao.dvfsdll, 0x1 << 0); + setbits32(&ch[0].ao.ddrconf0, (0x1 << 12) | (0x1 << 15) | (0x1 << 20) | (0x1 << 26)); - setbits_le32(&ch[0].ao.stbcal2, (0x1 << 4) | (0x7 << 28)); - clrbits_le32(&ch[0].ao.stbcal2, 0x1 << 29); - setbits_le32(&ch[0].ao.clkar, 0x1 << 19); + setbits32(&ch[0].ao.stbcal2, (0x1 << 4) | (0x7 << 28)); + clrbits32(&ch[0].ao.stbcal2, 0x1 << 29); + setbits32(&ch[0].ao.clkar, 0x1 << 19); for (size_t b = 0; b < 2; b++) - clrsetbits_le32(&ch[0].phy.b[b].dq[9], 0x7 << 20, 0x1 << 20); - clrsetbits_le32(&ch[0].phy.ca_cmd[10], 0x7 << 20, 0x0 << 20); - setbits_le32(&ch[0].phy.misc_ctrl0, + clrsetbits32(&ch[0].phy.b[b].dq[9], 0x7 << 20, 0x1 << 20); + clrsetbits32(&ch[0].phy.ca_cmd[10], 0x7 << 20, 0x0 << 20); + setbits32(&ch[0].phy.misc_ctrl0, (0xf << 0) | (0x1 << 9) | (0x1 << 24) | (0x1 << 31)); - setbits_le32(&ch[0].phy.misc_ctrl1, + setbits32(&ch[0].phy.misc_ctrl1, (0x1 << 2) | (0x1 << 3) | (0x1 << 15) | (0x1 << 24)); - clrsetbits_le32(&ch[0].phy.b0_rxdvs[0], 0x1 << 24, 0x1 << 24); - clrsetbits_le32(&ch[0].phy.b1_rxdvs[0], 0x1 << 24, 0x1 << 24); - clrsetbits_le32(&ch[0].phy.ca_rxdvs0, 0x1 << 24, 0x0 << 24); - clrbits_le32(&ch[0].phy.ca_cmd[7], (0x1 << 4) | (0x1 << 6)); - clrbits_le32(&ch[0].phy.b[0].dq[7], 0x1 << 6); - clrbits_le32(&ch[0].phy.b[1].dq[7], 0x1 << 6); + clrsetbits32(&ch[0].phy.b0_rxdvs[0], 0x1 << 24, 0x1 << 24); + clrsetbits32(&ch[0].phy.b1_rxdvs[0], 0x1 << 24, 0x1 << 24); + clrsetbits32(&ch[0].phy.ca_rxdvs0, 0x1 << 24, 0x0 << 24); + clrbits32(&ch[0].phy.ca_cmd[7], (0x1 << 4) | (0x1 << 6)); + clrbits32(&ch[0].phy.b[0].dq[7], 0x1 << 6); + clrbits32(&ch[0].phy.b[1].dq[7], 0x1 << 6); - clrsetbits_le32(&ch[0].ao.shu[0].conf[0], + clrsetbits32(&ch[0].ao.shu[0].conf[0], (0x3f << 0) | (0x1 << 7) | (0xf << 12) | (0x1 << 24) | (0x1 << 29) | (0x3 << 30), (0x3f << 0) | (0x1 << 7) | (0x1 << 12) | (0x1 << 24) | (0x1 << 29) | (0x2 << 30)); - clrsetbits_le32(&ch[0].ao.shu[0].odtctrl, + clrsetbits32(&ch[0].ao.shu[0].odtctrl, (0x1 << 0) | (0x1 << 1) | (0x7f << 16) | (0x1 << 30) | (0x1 << 31), (0x1 << 0) | (0x1 << 1) | (0x1 << 16) | (0x1 << 30) | (0x1 << 31)); - setbits_le32(&ch[0].phy.shu[0].b[0].dq[7], 0x1 << 15); - setbits_le32(&ch[0].phy.shu[0].b[1].dq[7], 0x1 << 15); + setbits32(&ch[0].phy.shu[0].b[0].dq[7], 0x1 << 15); + setbits32(&ch[0].phy.shu[0].b[1].dq[7], 0x1 << 15); - clrsetbits_le32(&ch[0].ao.refctrl0, 0xf << 24, 0x5 << 24); - clrbits_le32(&ch[0].ao.shu[0].selph_ca1, + clrsetbits32(&ch[0].ao.refctrl0, 0xf << 24, 0x5 << 24); + clrbits32(&ch[0].ao.shu[0].selph_ca1, (0x7 << 0) | (0x7 << 4) | (0x7 << 8) | (0x7 << 12) | (0x7 << 16) | (0x7 << 20) | (0x7 << 24) | (0x7 << 28)); - clrsetbits_le32(&ch[0].ao.shu[0].selph_ca2, + clrsetbits32(&ch[0].ao.shu[0].selph_ca2, (0x7 << 0) | (0x7 << 4) | (0x7 << 8) | (0x7 << 16) | (0x7 << 24), (0x0 << 0) | (0x0 << 4) | (0x0 << 8) | (0x7 << 16) | (0x0 << 24)); - clrbits_le32(&ch[0].ao.shu[0].selph_ca3, + clrbits32(&ch[0].ao.shu[0].selph_ca3, (0x7 << 0) | (0x7 << 4) | (0x7 << 8) | (0x7 << 12) | (0x7 << 16) | (0x7 << 20) | (0x7 << 24) | (0x7 << 28)); - clrbits_le32(&ch[0].ao.shu[0].selph_ca4, + clrbits32(&ch[0].ao.shu[0].selph_ca4, (0x7 << 0) | (0x7 << 4) | (0x7 << 8) | (0x7 << 12) | (0x7 << 16) | (0x7 << 20) | (0x7 << 24) | (0x7 << 28)); - clrbits_le32(&ch[0].ao.shu[0].selph_ca5, 0x7 << 8); - clrsetbits_le32(&ch[0].ao.shu[0].selph_dqs0, 0x77777777, SELPH_DQS0); - clrsetbits_le32(&ch[0].ao.shu[0].selph_dqs1, 0x77777777, SELPH_DQS1); + clrbits32(&ch[0].ao.shu[0].selph_ca5, 0x7 << 8); + clrsetbits32(&ch[0].ao.shu[0].selph_dqs0, 0x77777777, SELPH_DQS0); + clrsetbits32(&ch[0].ao.shu[0].selph_dqs1, 0x77777777, SELPH_DQS1); for (size_t rank = 0; rank < 2; rank++) { - clrsetbits_le32(&ch[0].ao.shu[0].rk[rank].selph_dq[0], + clrsetbits32(&ch[0].ao.shu[0].rk[rank].selph_dq[0], 0x77777777, _SELPH_DQS_BITS(0x3, 0x3)); - clrsetbits_le32(&ch[0].ao.shu[0].rk[rank].selph_dq[1], + clrsetbits32(&ch[0].ao.shu[0].rk[rank].selph_dq[1], 0x77777777, _SELPH_DQS_BITS(0x3, 0x3)); - clrsetbits_le32(&ch[0].ao.shu[0].rk[rank].selph_dq[2], + clrsetbits32(&ch[0].ao.shu[0].rk[rank].selph_dq[2], 0x77777777, _SELPH_DQS_BITS(0x6, 0x2)); - clrsetbits_le32(&ch[0].ao.shu[0].rk[rank].selph_dq[3], + clrsetbits32(&ch[0].ao.shu[0].rk[rank].selph_dq[3], 0x77777777, _SELPH_DQS_BITS(0x6, 0x2)); } for (int b = 0; b < 2; b++) { - clrsetbits_le32(&ch[0].phy.shu[0].rk[0].b[b].dq[7], + clrsetbits32(&ch[0].phy.shu[0].rk[0].b[b].dq[7], (0x3f << 8) | (0x3f << 16), (0x1a << 8) | (0x1a << 16)); - clrsetbits_le32(&ch[0].phy.shu[0].rk[1].b[b].dq[7], + clrsetbits32(&ch[0].phy.shu[0].rk[1].b[b].dq[7], (0x3f << 8) | (0x3f << 16), (0x14 << 8) | (0x14 << 16)); } udelay(1); for (size_t b = 0; b < 2; b++) { - setbits_le32(&ch[0].phy.b[b].dq[9], 0x1 << 5); - clrsetbits_le32(&ch[0].phy.b[b].dq[6], 0x3 << 14, 0x1 << 14); + setbits32(&ch[0].phy.b[b].dq[9], 0x1 << 5); + clrsetbits32(&ch[0].phy.b[b].dq[6], 0x3 << 14, 0x1 << 14); } - setbits_le32(&ch[0].ao.stbcal, 0x1 << 31); - clrsetbits_le32(&ch[0].ao.srefctrl, (0xf << 24) | (0x1 << 30), 0x8 << 24); - clrsetbits_le32(&ch[0].ao.shu[0].ckectrl, + setbits32(&ch[0].ao.stbcal, 0x1 << 31); + clrsetbits32(&ch[0].ao.srefctrl, (0xf << 24) | (0x1 << 30), 0x8 << 24); + clrsetbits32(&ch[0].ao.shu[0].ckectrl, (0x3 << 24) | (0x3 << 28), (0x3 << 24) | (0x3 << 28)); - setbits_le32(&ch[0].ao.shu[0].pipe, (0x1 << 30) | (0x1 << 31)); - setbits_le32(&ch[0].ao.ckectrl, (0x1 << 13) | (0x1 << 31)); - setbits_le32(&ch[0].ao.rkcfg, 0x1 << 2); - clrsetbits_le32(&ch[0].ao.shu[0].conf[2], + setbits32(&ch[0].ao.shu[0].pipe, (0x1 << 30) | (0x1 << 31)); + setbits32(&ch[0].ao.ckectrl, (0x1 << 13) | (0x1 << 31)); + setbits32(&ch[0].ao.rkcfg, 0x1 << 2); + clrsetbits32(&ch[0].ao.shu[0].conf[2], (0x7 << 16) | (0x1 << 28), (0x7 << 16) | (0x1 << 28)); - clrsetbits_le32(&ch[0].ao.spcmdctrl, 0x1 << 26, 0x1 << 26); - clrsetbits_le32(&ch[0].ao.shuctrl1, 0xff << 0, 0x40 << 0); + clrsetbits32(&ch[0].ao.spcmdctrl, 0x1 << 26, 0x1 << 26); + clrsetbits32(&ch[0].ao.shuctrl1, 0xff << 0, 0x40 << 0); - setbits_le32(&ch[0].ao.shuctrl, 0x1 << 16); - clrbits_le32(&ch[0].ao.refctrl1, (0x1 << 1) | (0x1 << 2) | (0x1 << 3) | (0x1 << 6)); - clrsetbits_le32(&ch[0].ao.refratre_filter, (0x1 << 15) | (0x1 << 23), + setbits32(&ch[0].ao.shuctrl, 0x1 << 16); + clrbits32(&ch[0].ao.refctrl1, (0x1 << 1) | (0x1 << 2) | (0x1 << 3) | (0x1 << 6)); + clrsetbits32(&ch[0].ao.refratre_filter, (0x1 << 15) | (0x1 << 23), (0x1 << 15) | (0x0 << 23)); - clrbits_le32(&ch[0].ao.dramctrl, 0x1 << 9); - setbits_le32(&ch[0].ao.misctl0, (0x1 << 19) | (0x1 << 24) | (0x1 << 31)); - setbits_le32(&ch[0].ao.perfctl0, + clrbits32(&ch[0].ao.dramctrl, 0x1 << 9); + setbits32(&ch[0].ao.misctl0, (0x1 << 19) | (0x1 << 24) | (0x1 << 31)); + setbits32(&ch[0].ao.perfctl0, (0x1 << 0) | (0x1 << 1) | (0x1 << 4) | (0x1 << 8) | (0x1 << 9) | (0x1 << 10) | (0x1 << 11) | (0x1 << 14) | (0x1 << 17)); - clrsetbits_le32(&ch[0].ao.arbctl, 0xff << 0, 0x80 << 0); - clrsetbits_le32(&ch[0].ao.padctrl, (0x3 << 0) | (0x1 << 3), (0x1 << 0) | (0x1 << 3)); - setbits_le32(&ch[0].ao.dramc_pd_ctrl, 0x1 << 8); - setbits_le32(&ch[0].ao.clkctrl, 0x1 << 29); - clrsetbits_le32(&ch[0].ao.refctrl0, (0x1 << 0) | (0x7 << 12), (0x1 << 0) | (0x4 << 12)); - clrsetbits_le32(&ch[0].ao.shu[0].rankctl, (0xf << 20) | (0xf << 24) | (0xf << 28), + clrsetbits32(&ch[0].ao.arbctl, 0xff << 0, 0x80 << 0); + clrsetbits32(&ch[0].ao.padctrl, (0x3 << 0) | (0x1 << 3), (0x1 << 0) | (0x1 << 3)); + setbits32(&ch[0].ao.dramc_pd_ctrl, 0x1 << 8); + setbits32(&ch[0].ao.clkctrl, 0x1 << 29); + clrsetbits32(&ch[0].ao.refctrl0, (0x1 << 0) | (0x7 << 12), (0x1 << 0) | (0x4 << 12)); + clrsetbits32(&ch[0].ao.shu[0].rankctl, (0xf << 20) | (0xf << 24) | (0xf << 28), (0x4 << 20) | (0x4 << 24) | (0x6 << 28)); udelay(2); - clrsetbits_le32(&ch[0].ao.shu[0].rk[0].dqsien, + clrsetbits32(&ch[0].ao.shu[0].rk[0].dqsien, (0x7f << 0) | (0x7f << 8), (0x19 << 0) | (0x19 << 8)); - clrsetbits_le32(&ch[0].ao.shu[0].rk[1].dqsien, + clrsetbits32(&ch[0].ao.shu[0].rk[1].dqsien, (0x7f << 0) | (0x7f << 8) | (0x7f << 16) | (0x7f << 24), (0x1b << 0) | (0x1b << 8) | (0x0 << 16) | (0x0 << 24)); - setbits_le32(&ch[0].ao.dramctrl, 0x1 << 19); - clrsetbits_le32(&ch[0].ao.zqcs, 0xff << 0, 0x56 << 0); + setbits32(&ch[0].ao.dramctrl, 0x1 << 19); + clrsetbits32(&ch[0].ao.zqcs, 0xff << 0, 0x56 << 0); udelay(1); - clrsetbits_le32(&ch[0].ao.shu[0].conf[3], 0x1ff << 16, 0xff << 16); - setbits_le32(&ch[0].ao.refctrl0, 0x1 << 30); - setbits_le32(&ch[0].ao.srefctrl, 0x1 << 30); - setbits_le32(&ch[0].ao.mpc_option, 0x1 << 17); - setbits_le32(&ch[0].ao.dramc_pd_ctrl, 0x1 << 30); - setbits_le32(&ch[0].ao.dramc_pd_ctrl, 0x1 << 0); - clrsetbits_le32(&ch[0].ao.eyescan, (0x1 << 1) | (0xf << 16), (0x0 << 1) | (0x1 << 16)); - setbits_le32(&ch[0].ao.stbcal1, (0x1 << 10) | (0x1 << 11)); - clrsetbits_le32(&ch[0].ao.test2_1, 0xfffffff << 4, 0x10000 << 4); - clrsetbits_le32(&ch[0].ao.test2_2, 0xfffffff << 4, 0x400 << 4); - clrsetbits_le32(&ch[0].ao.test2_3, + clrsetbits32(&ch[0].ao.shu[0].conf[3], 0x1ff << 16, 0xff << 16); + setbits32(&ch[0].ao.refctrl0, 0x1 << 30); + setbits32(&ch[0].ao.srefctrl, 0x1 << 30); + setbits32(&ch[0].ao.mpc_option, 0x1 << 17); + setbits32(&ch[0].ao.dramc_pd_ctrl, 0x1 << 30); + setbits32(&ch[0].ao.dramc_pd_ctrl, 0x1 << 0); + clrsetbits32(&ch[0].ao.eyescan, (0x1 << 1) | (0xf << 16), (0x0 << 1) | (0x1 << 16)); + setbits32(&ch[0].ao.stbcal1, (0x1 << 10) | (0x1 << 11)); + clrsetbits32(&ch[0].ao.test2_1, 0xfffffff << 4, 0x10000 << 4); + clrsetbits32(&ch[0].ao.test2_2, 0xfffffff << 4, 0x400 << 4); + clrsetbits32(&ch[0].ao.test2_3, (0x1 << 7) | (0x7 << 8) | (0x1 << 28), (0x1 << 7) | (0x4 << 8) | (0x1 << 28)); - clrbits_le32(&ch[0].ao.rstmask, 0x1 << 29); - clrbits_le32(&ch[0].ao.rstmask, 0x1 << 30); + clrbits32(&ch[0].ao.rstmask, 0x1 << 29); + clrbits32(&ch[0].ao.rstmask, 0x1 << 30); udelay(1); - clrsetbits_le32(&ch[0].ao.hw_mrr_fun, (0xf << 0) | (0xf << 4), (0x8 << 0) | (0x6 << 4)); + clrsetbits32(&ch[0].ao.hw_mrr_fun, (0xf << 0) | (0xf << 4), (0x8 << 0) | (0x6 << 4)); - clrbits_le32(&ch[0].ao.dramctrl, 0x1 << 0); - clrsetbits_le32(&ch[0].ao.perfctl0, + clrbits32(&ch[0].ao.dramctrl, 0x1 << 0); + clrsetbits32(&ch[0].ao.perfctl0, (0x1 << 18) | (0x1 << 19), (0x0 << 18) | (0x1 << 19)); - setbits_le32(&ch[0].ao.spcmdctrl, 0x1 << 28); - clrbits_le32(&ch[0].ao.rstmask, 0x1 << 28); - setbits_le32(&ch[0].ao.rkcfg, 0x1 << 11); - setbits_le32(&ch[0].ao.mpc_option, 0x1 << 17); - setbits_le32(&ch[0].ao.eyescan, 0x1 << 2); - setbits_le32(&ch[0].ao.shu[0].wodt, 0x1 << 29); - setbits_le32(&ch[0].phy.shu[0].b[0].dq[7], 0x1 << 7); - setbits_le32(&ch[0].phy.shu[0].b[1].dq[7], 0x1 << 7); - clrsetbits_le32(&ch[0].ao.shu[0].rankctl, 0xf << 20, 0x4 << 20); + setbits32(&ch[0].ao.spcmdctrl, 0x1 << 28); + clrbits32(&ch[0].ao.rstmask, 0x1 << 28); + setbits32(&ch[0].ao.rkcfg, 0x1 << 11); + setbits32(&ch[0].ao.mpc_option, 0x1 << 17); + setbits32(&ch[0].ao.eyescan, 0x1 << 2); + setbits32(&ch[0].ao.shu[0].wodt, 0x1 << 29); + setbits32(&ch[0].phy.shu[0].b[0].dq[7], 0x1 << 7); + setbits32(&ch[0].phy.shu[0].b[1].dq[7], 0x1 << 7); + clrsetbits32(&ch[0].ao.shu[0].rankctl, 0xf << 20, 0x4 << 20); for (size_t r = 0; r < 2; r++) { - clrsetbits_le32(&ch[0].ao.shu[0].rk[r].selph_dq[0], + clrsetbits32(&ch[0].ao.shu[0].rk[r].selph_dq[0], (0x7 << 0) | (0x7 << 4), (0x2 << 0) | (0x2 << 4)); - clrsetbits_le32(&ch[0].ao.shu[0].rk[r].selph_dq[1], + clrsetbits32(&ch[0].ao.shu[0].rk[r].selph_dq[1], (0x7 << 0) | (0x7 << 4), (0x2 << 0) | (0x2 << 4)); } udelay(5); - clrsetbits_le32(&ch[0].ao.stbcal1, 0xffff << 16, 0x3 << 16); - clrsetbits_le32(&ch[0].ao.stbcal1, 0xffff << 16, 0x1 << 16); - clrsetbits_le32(&ch[0].ao.stbcal, + clrsetbits32(&ch[0].ao.stbcal1, 0xffff << 16, 0x3 << 16); + clrsetbits32(&ch[0].ao.stbcal1, 0xffff << 16, 0x1 << 16); + clrsetbits32(&ch[0].ao.stbcal, (0x1 << 0) | (0x1 << 22) | (0x1 << 24) | (0x1 << 26) | (0x1 << 27), (0x1 << 0) | (0x0 << 22) | (0x0 << 24) | (0x1 << 26) | (0x1 << 27)); - setbits_le32(&ch[0].ao.stbcal1, 0x1 << 6); - clrsetbits_le32(&ch[0].ao.shu[0].dqsg, + setbits32(&ch[0].ao.stbcal1, 0x1 << 6); + clrsetbits32(&ch[0].ao.shu[0].dqsg, (0x1 << 11) | (0xf << 12), (0x1 << 11) | (0x9 << 12)); - clrbits_le32(&ch[0].phy.misc_ctrl0, 0xf << 0); - setbits_le32(&ch[0].ao.shu[0].stbcal, 0x1 << 8); - setbits_le32(&ch[0].ao.stbcal, 0x1 << 17); - clrbits_le32(&ch[0].phy.shu[0].b[0].dq[7], 0x1 << 14); - clrbits_le32(&ch[0].phy.shu[0].b[1].dq[7], 0x1 << 14); - clrsetbits_le32(&ch[0].ao.shu[0].stbcal, 0x7 << 4, 0x1 << 4); + clrbits32(&ch[0].phy.misc_ctrl0, 0xf << 0); + setbits32(&ch[0].ao.shu[0].stbcal, 0x1 << 8); + setbits32(&ch[0].ao.stbcal, 0x1 << 17); + clrbits32(&ch[0].phy.shu[0].b[0].dq[7], 0x1 << 14); + clrbits32(&ch[0].phy.shu[0].b[1].dq[7], 0x1 << 14); + clrsetbits32(&ch[0].ao.shu[0].stbcal, 0x7 << 4, 0x1 << 4); if (freq_group == LP4X_DDR1600) - clrsetbits_le32(&ch[0].ao.shu[0].stbcal, 0x3 << 0, 0x0 << 0); + clrsetbits32(&ch[0].ao.shu[0].stbcal, 0x3 << 0, 0x0 << 0); else - clrsetbits_le32(&ch[0].ao.shu[0].stbcal, 0x3 << 0, 0x2 << 0); - setbits_le32(&ch[0].ao.refctrl1, (0x1 << 0) | (0x1 << 5)); - setbits_le32(&ch[0].ao.dqsoscr, (0x1 << 23) | (0x1 << 27)); - clrbits_le32(&ch[0].ao.rstmask, (0x1 << 24) | (0x1 << 25) | (0x1 << 26)); - clrsetbits_le32(&ch[0].ao.rkcfg, 0x7 << 4, 0x1 << 4); + clrsetbits32(&ch[0].ao.shu[0].stbcal, 0x3 << 0, 0x2 << 0); + setbits32(&ch[0].ao.refctrl1, (0x1 << 0) | (0x1 << 5)); + setbits32(&ch[0].ao.dqsoscr, (0x1 << 23) | (0x1 << 27)); + clrbits32(&ch[0].ao.rstmask, (0x1 << 24) | (0x1 << 25) | (0x1 << 26)); + clrsetbits32(&ch[0].ao.rkcfg, 0x7 << 4, 0x1 << 4); udelay(12); - clrsetbits_le32(&ch[0].ao.shu[0].rankctl, + clrsetbits32(&ch[0].ao.shu[0].rankctl, (0xf << 24) | (0xf << 28), (0x4 << 24) | 0x6 << 28); - clrbits_le32(&ch[0].ao.shu[0].wodt, 0x1 << 31); - clrsetbits_le32(&ch[0].ao.shu[0].rk[0].fine_tune, + clrbits32(&ch[0].ao.shu[0].wodt, 0x1 << 31); + clrsetbits32(&ch[0].ao.shu[0].rk[0].fine_tune, (0x3f << 0) | (0x3f << 8) | (0x3f << 16) | (0x3f << 24), (0x1a << 0) | (0x1a << 8) | (0x1a << 16) | (0x1a << 24)); - clrsetbits_le32(&ch[0].ao.shu[0].rk[1].fine_tune, + clrsetbits32(&ch[0].ao.shu[0].rk[1].fine_tune, (0x3f << 0) | (0x3f << 8) | (0x3f << 16) | (0x3f << 24), (0x14 << 0) | (0x14 << 8) | (0x14 << 16) | (0x14 << 24)); for (u8 rank = 0; rank < 2; rank++) { - clrsetbits_le32(&ch[0].ao.shu[0].rk[rank].selph_dq[2], + clrsetbits32(&ch[0].ao.shu[0].rk[rank].selph_dq[2], (0x7 << 16) | (0x7 << 20) | (0x7 << 24) | (0x7 << 28), (0x4 << 16) | (0x4 << 20) | (0x4 << 24) | (0x4 << 28)); - clrsetbits_le32(&ch[0].ao.shu[0].rk[rank].selph_dq[3], + clrsetbits32(&ch[0].ao.shu[0].rk[rank].selph_dq[3], (0x7 << 16) | (0x7 << 20) | (0x7 << 24) | (0x7 << 28), (0x4 << 16) | (0x4 << 20) | (0x4 << 24) | (0x4 << 28)); } - clrsetbits_le32(&ch[0].ao.shu[0].dqsg_retry, + clrsetbits32(&ch[0].ao.shu[0].dqsg_retry, (0x1 << 2) | (0xf << 8) | (0x1 << 14) | (0x3 << 24), (0x1 << 2) | (0x5 << 8) | (0x0 << 14) | (0x1 << 24)); - setbits_le32(&ch[0].phy.shu[0].b[0].dq[7], (0x1 << 12) | (0x1 << 13)); - setbits_le32(&ch[0].phy.shu[0].b[1].dq[7], (0x1 << 12) | (0x1 << 13)); - clrbits_le32(&ch[0].ao.shu[0].dqs2dq_tx, 0x1f << 0); + setbits32(&ch[0].phy.shu[0].b[0].dq[7], (0x1 << 12) | (0x1 << 13)); + setbits32(&ch[0].phy.shu[0].b[1].dq[7], (0x1 << 12) | (0x1 << 13)); + clrbits32(&ch[0].ao.shu[0].dqs2dq_tx, 0x1f << 0); switch (freq_group) { case LP4X_DDR1600: @@ -1407,28 +1407,28 @@ static void dramc_setting(const struct sdram_params *params, u8 freq_group, update_initial_settings(freq_group); dramc_sw_impedance_save_reg(freq_group, impedance); - clrbits_le32(&ch[0].ao.test2_4, 0x1 << 17); - clrsetbits_le32(&ch[0].ao.shu[0].conf[3], 0x1ff << 0, 0x5 << 0); + clrbits32(&ch[0].ao.test2_4, 0x1 << 17); + clrsetbits32(&ch[0].ao.shu[0].conf[3], 0x1ff << 0, 0x5 << 0); udelay(1); - setbits_le32(&ch[0].ao.refctrl0, (0x1 << 17) | (0x1 << 18)); - setbits_le32(&ch[0].ao.shuctrl2, (0x1 << 24) | (0x1 << 25)); - setbits_le32(&ch[0].ao.refctrl0, 0x1 << 29); - setbits_le32(&ch[0].ao.dramctrl, 0x1 << 26); - clrsetbits_le32(&ch[0].ao.dummy_rd, + setbits32(&ch[0].ao.refctrl0, (0x1 << 17) | (0x1 << 18)); + setbits32(&ch[0].ao.shuctrl2, (0x1 << 24) | (0x1 << 25)); + setbits32(&ch[0].ao.refctrl0, 0x1 << 29); + setbits32(&ch[0].ao.dramctrl, 0x1 << 26); + clrsetbits32(&ch[0].ao.dummy_rd, (0x1 << 4) | (0x1 << 11) | (0x1 << 13) | (0x1 << 14) | (0x3 << 16) | (0x1 << 22), (0x1 << 4) | (0x1 << 11) | (0x1 << 13) | (0x1 << 14) | (0x2 << 16) | (0x1 << 22)); - clrsetbits_le32(&ch[0].ao.test2_4, 0x7 << 28, 0x4 << 28); - clrbits_le32(&ch[0].ao.dramctrl, 0x1 << 0); + clrsetbits32(&ch[0].ao.test2_4, 0x7 << 28, 0x4 << 28); + clrbits32(&ch[0].ao.dramctrl, 0x1 << 0); udelay(1); dramc_set_broadcast(DRAMC_BROADCAST_OFF); - clrsetbits_le32(&ch[0].ao.shuctrl, (0x1 << 5) | (0x1 << 17), (0x0 << 5) | (0x1 << 17)); - setbits_le32(&ch[0].ao.shuctrl2, 0x1 << 12); - clrsetbits_le32(&ch[1].ao.shuctrl, (0x1 << 5) | (0x1 << 17), (0x1 << 5) | (0x0 << 17)); - clrbits_le32(&ch[1].ao.shuctrl2, 0x1 << 12); + clrsetbits32(&ch[0].ao.shuctrl, (0x1 << 5) | (0x1 << 17), (0x0 << 5) | (0x1 << 17)); + setbits32(&ch[0].ao.shuctrl2, 0x1 << 12); + clrsetbits32(&ch[1].ao.shuctrl, (0x1 << 5) | (0x1 << 17), (0x1 << 5) | (0x0 << 17)); + clrbits32(&ch[1].ao.shuctrl2, 0x1 << 12); } struct ac_time { @@ -1651,33 +1651,33 @@ static void ddr_update_ac_timing(u8 freq_group) } for (u8 chn = 0; chn < CHANNEL_MAX; chn++) { - clrsetbits_le32(&ch[chn].ao.shu[0].actim[0], + clrsetbits32(&ch[chn].ao.shu[0].actim[0], (0xf << 24) | (0x7 << 16) | (0x1f << 8) | (0xf << 0), (ac_t.trcd << 24) | (ac_t.trrd << 16) | (ac_t.twr << 8) | (ac_t.twtr << 0)); - clrsetbits_le32(&ch[chn].ao.shu[0].actim[1], + clrsetbits32(&ch[chn].ao.shu[0].actim[1], (0x1f << 24) | (0xf << 16) | (0xf << 8) | (0x7 << 0), (ac_t.trc << 24) | (ac_t.tras << 16) | (ac_t.trp << 8) | (ac_t.trpab << 0)); - clrsetbits_le32(&ch[chn].ao.shu[0].actim[2], + clrsetbits32(&ch[chn].ao.shu[0].actim[2], (0x1f << 24) | (0xf << 16) | (0x7 << 8) | (0x7 << 0), (ac_t.tfaw << 24) | (trtw << 16) | (ac_t.trtp << 8) | (ac_t.txp << 0)); - clrsetbits_le32(&ch[chn].ao.shu[0].actim[3], + clrsetbits32(&ch[chn].ao.shu[0].actim[3], (0xff << 16) | (0xff << 24) | (0xff << 0), (ac_t.trfc << 16) | (ac_t.refcnt << 24) | (ac_t.trfcpb << 0)); - clrsetbits_le32(&ch[chn].ao.shu[0].actim[4], + clrsetbits32(&ch[chn].ao.shu[0].actim[4], (0xff << 24) | (0xff << 16) | (0x3ff << 0), (ac_t.tzqcs << 24) | (ac_t.refcnt_fr_clk << 16) | (ac_t.txrefcnt << 0)); - clrsetbits_le32(&ch[chn].ao.shu[0].actim[5], + clrsetbits32(&ch[chn].ao.shu[0].actim[5], (0xf << 24) | (0x1f << 8) | (0x1f << 0), (tmrr2w << 24) | (ac_t.twtpd << 8) | (ac_t.trtpd << 0)); - clrsetbits_le32(&ch[chn].ao.shu[0].actim_xrt, + clrsetbits32(&ch[chn].ao.shu[0].actim_xrt, (0xf << 24) | (0x7 << 16) | (0xf << 8) | (0x1f << 0), (ac_t.xrtw2w << 24) | (ac_t.xrtw2r << 16) | (ac_t.xrtr2w << 8) | (ac_t.xrtr2r << 0)); - clrsetbits_le32(&ch[chn].ao.shu[0].ac_time_05t, + clrsetbits32(&ch[chn].ao.shu[0].ac_time_05t, (0x1 << 25) | (0x0 << 24) | (0x1 << 16) | (0x0 << 15) | (0x1 << 13) | (0x1 << 12) | (0x1 << 10) | (0x1 << 9) | (0x1 << 8) | (0x1 << 7) | (0x1 << 6) | (0x1 << 5) | @@ -1690,45 +1690,45 @@ static void ddr_update_ac_timing(u8 freq_group) (ac_t.trcd_05T << 6) | (ac_t.trtp_05T << 5) | (ac_t.txp_05T << 4) | (ac_t.trfc_05T << 2) | (ac_t.trfcpb_05T << 1) | (ac_t.trc_05T << 0)); - clrsetbits_le32(&ch[chn].ao.catraining1, (0xff << 24) | (0xf << 20), + clrsetbits32(&ch[chn].ao.catraining1, (0xff << 24) | (0xf << 20), (ac_t.r_dmcatrain_intv << 24) | (0x0 << 20)); /* DQSINCTL related */ - clrsetbits_le32(&ch[chn].ao.shu[0].rk[0].dqsctl, 0xf << 0, + clrsetbits32(&ch[chn].ao.shu[0].rk[0].dqsctl, 0xf << 0, ac_t.dqsinctl << 0); - clrsetbits_le32(&ch[chn].ao.shu[0].rk[1].dqsctl, 0xf << 0, + clrsetbits32(&ch[chn].ao.shu[0].rk[1].dqsctl, 0xf << 0, ac_t.dqsinctl << 0); - clrsetbits_le32(&ch[chn].ao.shu[0].odtctrl, 0xf << 4, + clrsetbits32(&ch[chn].ao.shu[0].odtctrl, 0xf << 4, ac_t.dqsinctl << 4); /* DATLAT related, tREFBW */ - clrsetbits_le32(&ch[chn].ao.shu[0].conf[1], + clrsetbits32(&ch[chn].ao.shu[0].conf[1], (0x1f << 0) | (0x1f << 8) | (0x1f << 26) | (0x3ff << 16), (ac_t.datlat << 0) | (new_datlat << 8) | (new_datlat << 26) | (0x0 << 16)); - clrsetbits_le32(&ch[chn].ao.shu[0].conf[2], + clrsetbits32(&ch[chn].ao.shu[0].conf[2], (0xff << 8), ac_t.r_dmfspchg_prdcnt << 8); - clrsetbits_le32(&ch[chn].ao.shu[0].scintv, (0x1f << 13) | (0x1f << 6), + clrsetbits32(&ch[chn].ao.shu[0].scintv, (0x1f << 13) | (0x1f << 6), (ac_t.r_dmmrw_intv << 13) | (ac_t.zqlat2 << 6)); /* CKEPRD - CKE pulse width */ - clrsetbits_le32(&ch[chn].ao.shu[0].ckectrl, 0x7 << 20, ac_t.ckeprd << 20); + clrsetbits32(&ch[chn].ao.shu[0].ckectrl, 0x7 << 20, ac_t.ckeprd << 20); /* CKELCKCNT: Valid clock requirement after CKE input low */ - clrsetbits_le32(&ch[chn].ao.ckectrl, 0x7 << 24, ac_t.ckelckcnt << 24); + clrsetbits32(&ch[chn].ao.ckectrl, 0x7 << 24, ac_t.ckelckcnt << 24); temp = ((read32(&ch[chn].ao.shu[0].rankctl) & 0x00f00000) >> 20) & 0xf; - clrsetbits_le32(&ch[chn].ao.shu[0].rankctl, 0xf << 0, temp << 0); + clrsetbits32(&ch[chn].ao.shu[0].rankctl, 0xf << 0, temp << 0); - clrsetbits_le32(&ch[chn].ao.shu[0].rankctl, + clrsetbits32(&ch[chn].ao.shu[0].rankctl, (0xf << 16) | (0xf << 12) | (0xf << 8), (root << 16) | (tx_rank_inctl << 12) | (tx_dly << 8)); } u8 dram_cbt_mode = 0; - clrsetbits_le32(&ch[0].ao.arbctl, 0x7 << 10, 0x3 << 10); - clrsetbits_le32(&ch[0].ao.rstmask, 0x3 << 13, dram_cbt_mode); - clrsetbits_le32(&ch[0].ao.arbctl, 0x1 << 13, dram_cbt_mode); + clrsetbits32(&ch[0].ao.arbctl, 0x7 << 10, 0x3 << 10); + clrsetbits32(&ch[0].ao.rstmask, 0x3 << 13, dram_cbt_mode); + clrsetbits32(&ch[0].ao.arbctl, 0x1 << 13, dram_cbt_mode); } void dramc_init(const struct sdram_params *params, u8 freq_group, diff --git a/src/soc/mediatek/mt8183/dramc_pi_basic_api.c b/src/soc/mediatek/mt8183/dramc_pi_basic_api.c index eb30381953..1eb86f406f 100644 --- a/src/soc/mediatek/mt8183/dramc_pi_basic_api.c +++ b/src/soc/mediatek/mt8183/dramc_pi_basic_api.c @@ -48,7 +48,7 @@ static void dramc_sw_imp_cal_vref_sel(u8 term_option, u8 impcal_stage) } } - clrsetbits_le32(&ch[0].phy.shu[0].ca_cmd[11], 0x3f << 8, vref_sel << 8); + clrsetbits32(&ch[0].phy.shu[0].ca_cmd[11], 0x3f << 8, vref_sel << 8); } void dramc_sw_impedance_cal(const struct sdram_params *params, u8 term, @@ -60,29 +60,29 @@ void dramc_sw_impedance_cal(const struct sdram_params *params, u8 term, broadcast_bak = dramc_get_broadcast(); dramc_set_broadcast(DRAMC_BROADCAST_OFF); - clrbits_le32(&ch[0].phy.misc_spm_ctrl1, 0xf << 0); + clrbits32(&ch[0].phy.misc_spm_ctrl1, 0xf << 0); write32(&ch[0].phy.misc_spm_ctrl2, 0x0); write32(&ch[0].phy.misc_spm_ctrl0, 0x0); - clrbits_le32(&ch[0].ao.impcal, 0x1 << 31); + clrbits32(&ch[0].ao.impcal, 0x1 << 31); impcal_bak = read32(&ch[0].ao.impcal); dramc_sw_imp_cal_vref_sel(term, IMPCAL_STAGE_DRVP); - clrbits_le32(&ch[0].phy.misc_imp_ctrl1, 0x1 << 6); - clrsetbits_le32(&ch[0].ao.impcal, 0x1 << 21, 0x3 << 24); - clrsetbits_le32(&ch[0].phy.misc_imp_ctrl0, 0x7 << 4, 0x3 << 4); + clrbits32(&ch[0].phy.misc_imp_ctrl1, 0x1 << 6); + clrsetbits32(&ch[0].ao.impcal, 0x1 << 21, 0x3 << 24); + clrsetbits32(&ch[0].phy.misc_imp_ctrl0, 0x7 << 4, 0x3 << 4); udelay(1); dramc_dbg("impedance: K DRVP\n"); - setbits_le32(&ch[0].ao.impcal, 0x1 << 23); - setbits_le32(&ch[0].ao.impcal, 0x1 << 22); - clrbits_le32(&ch[0].ao.impcal, 0x1 << 21); - clrbits_le32(&ch[0].ao.shu[0].impcal1, 0x1f << 4 | 0x1f << 11); - clrsetbits_le32(&ch[0].phy.shu[0].ca_cmd[11], 0xff << 0, 0x3); + setbits32(&ch[0].ao.impcal, 0x1 << 23); + setbits32(&ch[0].ao.impcal, 0x1 << 22); + clrbits32(&ch[0].ao.impcal, 0x1 << 21); + clrbits32(&ch[0].ao.shu[0].impcal1, 0x1f << 4 | 0x1f << 11); + clrsetbits32(&ch[0].phy.shu[0].ca_cmd[11], 0xff << 0, 0x3); for (u8 impx_drv = 0; impx_drv < 32; impx_drv++) { impx_drv = (impx_drv == 16) ? 29 : impx_drv; - clrsetbits_le32(&ch[0].ao.shu[0].impcal1, + clrsetbits32(&ch[0].ao.shu[0].impcal1, 0x1f << 4, impx_drv << 4); udelay(1); imp_cal_result = (read32(&ch[0].phy_nao.misc_phy_rgs_cmd) >> @@ -100,17 +100,17 @@ void dramc_sw_impedance_cal(const struct sdram_params *params, u8 term, dramc_dbg("impedance: K ODTN\n"); dramc_sw_imp_cal_vref_sel(term, IMPCAL_STAGE_DRVN); - clrbits_le32(&ch[0].ao.impcal, 0x1 << 22); + clrbits32(&ch[0].ao.impcal, 0x1 << 22); if (term == ODT_ON) - setbits_le32(&ch[0].ao.impcal, 0x1 << 21); - clrsetbits_le32(&ch[0].ao.shu[0].impcal1, 0x1f << 4 | 0x1f << 11, + setbits32(&ch[0].ao.impcal, 0x1 << 21); + clrsetbits32(&ch[0].ao.shu[0].impcal1, 0x1f << 4 | 0x1f << 11, DRVP_result << 4 | 0x1f << 11); - clrsetbits_le32(&ch[0].phy.shu[0].ca_cmd[11], 0xff << 0, 0x3); + clrsetbits32(&ch[0].phy.shu[0].ca_cmd[11], 0xff << 0, 0x3); for (u8 impx_drv = 0; impx_drv < 32; impx_drv++) { impx_drv = (impx_drv == 16) ? 29 : impx_drv; - clrsetbits_le32(&ch[0].ao.shu[0].impcal1, + clrsetbits32(&ch[0].ao.shu[0].impcal1, 0x1f << 11, impx_drv << 11); udelay(1); imp_cal_result = (read32(&ch[0].phy_nao.misc_phy_rgs_cmd) >> @@ -163,31 +163,31 @@ void dramc_sw_impedance_save_reg(u8 freq_group, sw_impedance[ODT_OFF][2] = sw_impedance[ODT_ON][2]; sw_impedance[ODT_OFF][3] = sw_impedance[ODT_ON][3]; - clrsetbits_le32(&ch[0].phy.shu[0].ca_cmd[11], 0xff, 0x3); + clrsetbits32(&ch[0].phy.shu[0].ca_cmd[11], 0xff, 0x3); dramc_sw_imp_cal_vref_sel(dq_term, IMPCAL_STAGE_DRVP); /* DQ */ - clrsetbits_le32(&ch[0].ao.shu[0].drving[0], (0x1f << 5) | (0x1f << 0), + clrsetbits32(&ch[0].ao.shu[0].drving[0], (0x1f << 5) | (0x1f << 0), (sw_impedance[dq_term][0] << 5) | (sw_impedance[dq_term][1] << 0)); - clrsetbits_le32(&ch[0].ao.shu[0].drving[1], + clrsetbits32(&ch[0].ao.shu[0].drving[1], (0x1f << 25) | (0x1f << 20) | (1 << 31), (sw_impedance[dq_term][0] << 25) | (sw_impedance[dq_term][1] << 20) | (!dq_term << 31)); - clrsetbits_le32(&ch[0].ao.shu[0].drving[2], (0x1f << 5) | (0x1f << 0), + clrsetbits32(&ch[0].ao.shu[0].drving[2], (0x1f << 5) | (0x1f << 0), (sw_impedance[dq_term][2] << 5) | (sw_impedance[dq_term][3] << 0)); - clrsetbits_le32(&ch[0].ao.shu[0].drving[3], (0x1f << 25) | (0x1f << 20), + clrsetbits32(&ch[0].ao.shu[0].drving[3], (0x1f << 25) | (0x1f << 20), (sw_impedance[dq_term][2] << 25) | (sw_impedance[dq_term][3] << 20)); /* DQS */ for (u8 i = 0; i <= 2; i += 2) { - clrsetbits_le32(&ch[0].ao.shu[0].drving[i], + clrsetbits32(&ch[0].ao.shu[0].drving[i], (0x1f << 25) | (0x1f << 20), (sw_impedance[dq_term][i] << 25) | (sw_impedance[dq_term][i + 1] << 20)); - clrsetbits_le32(&ch[0].ao.shu[0].drving[i], + clrsetbits32(&ch[0].ao.shu[0].drving[i], (0x1f << 15) | (0x1f << 10), (sw_impedance[dq_term][i] << 15) | (sw_impedance[dq_term][i + 1] << 10)); @@ -195,19 +195,19 @@ void dramc_sw_impedance_save_reg(u8 freq_group, /* CMD & CLK */ for (u8 i = 1; i <= 3; i += 2) { - clrsetbits_le32(&ch[0].ao.shu[0].drving[i], + clrsetbits32(&ch[0].ao.shu[0].drving[i], (0x1f << 15) | (0x1f << 10), (sw_impedance[ca_term][i - 1] << 15) | (sw_impedance[ca_term][i] << 10)); - clrsetbits_le32(&ch[0].ao.shu[0].drving[i], + clrsetbits32(&ch[0].ao.shu[0].drving[i], (0x1f << 5) | (0x1f << 0), (sw_impedance[ca_term][i - 1] << 5) | (sw_impedance[ca_term][i] << 0)); } - clrsetbits_le32(&ch[0].phy.shu[0].ca_cmd[11], 0x1f << 17, + clrsetbits32(&ch[0].phy.shu[0].ca_cmd[11], 0x1f << 17, sw_impedance[ca_term][0] << 17); - clrsetbits_le32(&ch[0].phy.shu[0].ca_cmd[11], 0x1f << 22, + clrsetbits32(&ch[0].phy.shu[0].ca_cmd[11], 0x1f << 22, sw_impedance[ca_term][1] << 22); SET32_BITFIELDS(&ch[0].phy.shu[0].ca_cmd[3], @@ -215,34 +215,34 @@ void dramc_sw_impedance_save_reg(u8 freq_group, SET32_BITFIELDS(&ch[0].phy.shu[0].ca_cmd[0], SHU1_CA_CMD0_RG_TX_ARCLK_DRVN_PRE, 0); - clrsetbits_le32(&ch[0].phy.shu[0].ca_dll[1], 0x1f << 16, 0x9 << 16); + clrsetbits32(&ch[0].phy.shu[0].ca_dll[1], 0x1f << 16, 0x9 << 16); } static void transfer_pll_to_spm_control(void) { u8 shu_lev = (read32(&ch[0].ao.shustatus) >> 1) & 0x3; - clrsetbits_le32(&mtk_spm->poweron_config_set, + clrsetbits32(&mtk_spm->poweron_config_set, (0xffff << 16) | (0x1 << 0), (0xb16 << 16) | (0x1 << 0)); /* Set SPM pinmux */ - clrbits_le32(&mtk_spm->pcm_pwr_io_en, (0xff << 0) | (0xff << 16)); - setbits_le32(&mtk_spm->dramc_dpy_clk_sw_con_sel, 0xffffffff); - setbits_le32(&mtk_spm->dramc_dpy_clk_sw_con_sel2, 0xffffffff); + clrbits32(&mtk_spm->pcm_pwr_io_en, (0xff << 0) | (0xff << 16)); + setbits32(&mtk_spm->dramc_dpy_clk_sw_con_sel, 0xffffffff); + setbits32(&mtk_spm->dramc_dpy_clk_sw_con_sel2, 0xffffffff); - setbits_le32(&mtk_spm->spm_power_on_val0, (0x1 << 8) | (0xf << 12)); - setbits_le32(&mtk_spm->spm_s1_mode_ch, 0x3 << 0); + setbits32(&mtk_spm->spm_power_on_val0, (0x1 << 8) | (0xf << 12)); + setbits32(&mtk_spm->spm_s1_mode_ch, 0x3 << 0); shu_lev = (shu_lev == 1) ? 2 : 1; - clrsetbits_le32(&mtk_spm->spm_power_on_val0, 0x3 << 28, shu_lev << 28); - clrsetbits_le32(&mtk_spm->dramc_dpy_clk_sw_con2, + clrsetbits32(&mtk_spm->spm_power_on_val0, 0x3 << 28, shu_lev << 28); + clrsetbits32(&mtk_spm->dramc_dpy_clk_sw_con2, 0x3 << 2, shu_lev << 2); udelay(1); for (size_t chn = CHANNEL_A; chn < CHANNEL_MAX; chn++) { - clrbits_le32(&ch[chn].phy.pll1, 0x1 << 31); - clrbits_le32(&ch[chn].phy.pll2, 0x1 << 31); + clrbits32(&ch[chn].phy.pll1, 0x1 << 31); + clrbits32(&ch[chn].phy.pll2, 0x1 << 31); } } @@ -254,50 +254,50 @@ static void dramc_rx_input_delay_tracking(u8 chn) /* DVS mode to RG mode */ for (size_t r = 0; r < 2; r++) for (size_t b = 0; b < 2; b++) - clrbits_le32(&ch[chn].phy.r[r].b[b].rxdvs[2], 3 << 30); + clrbits32(&ch[chn].phy.r[r].b[b].rxdvs[2], 3 << 30); - clrsetbits_le32(&ch[chn].phy.b0_rxdvs[0], 0x1 << 19, 0x1 << 9); - clrsetbits_le32(&ch[chn].phy.b1_rxdvs[0], 0x1 << 19, 0x1 << 9); + clrsetbits32(&ch[chn].phy.b0_rxdvs[0], 0x1 << 19, 0x1 << 9); + clrsetbits32(&ch[chn].phy.b1_rxdvs[0], 0x1 << 19, 0x1 << 9); for (size_t r = 0; r < 2; r++) for (size_t b = 0; b < 2; b++) { - clrbits_le32(&ch[chn].phy.r[r].b[b].rxdvs[2], 1 << 29); - clrsetbits_le32(&ch[chn].phy.r[r].b[b].rxdvs[7], + clrbits32(&ch[chn].phy.r[r].b[b].rxdvs[2], 1 << 29); + clrsetbits32(&ch[chn].phy.r[r].b[b].rxdvs[7], (0x3f << 0) | (0x3f << 8) | (0x7f << 16) | (0x7f << 24), (0x0 << 0) | (0x3f << 8) | (0x0 << 16) | (0x7f << 24)); - clrsetbits_le32(&ch[chn].phy.r[r].b[b].rxdvs[1], + clrsetbits32(&ch[chn].phy.r[r].b[b].rxdvs[1], (0xffff << 16) | (0xffff << 0), (0x2 << 16) | (0x2 << 0)); /* DQ/DQS Rx DLY adjustment for tracking mode */ - clrbits_le32(&ch[chn].phy.r[r].b[b].rxdvs[2], + clrbits32(&ch[chn].phy.r[r].b[b].rxdvs[2], (0x3 << 26) | (0x3 << 24) | (0x3 << 18) | (0x3 << 16)); } /* Rx DLY tracking setting (Static) */ - clrsetbits_le32(&ch[chn].phy.b0_rxdvs[0], + clrsetbits32(&ch[chn].phy.b0_rxdvs[0], (0x1 << 29) | (0xf << 4) | (0x1 << 0), (0x1 << 29) | (0x0 << 4) | (0x1 << 0)); - clrsetbits_le32(&ch[chn].phy.b1_rxdvs[0], + clrsetbits32(&ch[chn].phy.b1_rxdvs[0], (0x1 << 29) | (0xf << 4) | (0x1 << 0), (0x1 << 29) | (0x0 << 4) | (0x1 << 0)); for (u8 b = 0; b < 2; b++) { - clrsetbits_le32(&ch[chn].phy.b[b].dq[9], + clrsetbits32(&ch[chn].phy.b[b].dq[9], (0x7 << 28) | (0x7 << 24), (0x1 << 28) | (0x0 << 24)); - setbits_le32(&ch[chn].phy.b[b].dq[5], 0x1 << 31); + setbits32(&ch[chn].phy.b[b].dq[5], 0x1 << 31); } - clrbits_le32(&ch[chn].phy.ca_cmd[10], (0x7 << 28) | (0x7 << 24)); + clrbits32(&ch[chn].phy.ca_cmd[10], (0x7 << 28) | (0x7 << 24)); - setbits_le32(&ch[chn].phy.b0_rxdvs[0], (0x1 << 28) | (0x1 << 31)); - setbits_le32(&ch[chn].phy.b1_rxdvs[0], (0x1 << 28) | (0x1 << 31)); + setbits32(&ch[chn].phy.b0_rxdvs[0], (0x1 << 28) | (0x1 << 31)); + setbits32(&ch[chn].phy.b1_rxdvs[0], (0x1 << 28) | (0x1 << 31)); for (u8 rank = RANK_0; rank < RANK_MAX; rank++) for (u8 b = 0; b < 2; b++) - clrsetbits_le32(&ch[chn].phy.r[rank].b[b].rxdvs[2], + clrsetbits32(&ch[chn].phy.r[rank].b[b].rxdvs[2], (0x3 << 30) | (0x1 << 28) | (0x1 << 23), (0x2 << 30) | (0x1 << 28) | (0x1 << 23)); @@ -305,29 +305,29 @@ static void dramc_rx_input_delay_tracking(u8 chn) static void dramc_hw_dqs_gating_tracking(u8 chn) { - clrsetbits_le32(&ch[chn].ao.stbcal, + clrsetbits32(&ch[chn].ao.stbcal, (0x1 << 21) | (0x3 << 15) | (0x1f << 8) | (0x1 << 4), (0x3 << 26) | (0x1 << 0)); - clrsetbits_le32(&ch[chn].ao.stbcal1, + clrsetbits32(&ch[chn].ao.stbcal1, (0xffff << 16) | (0x1 << 8) | (0x1 << 6), (0x1 << 16) | (0x1 << 8) | (0x1 << 6)); - clrsetbits_le32(&ch[chn].phy.misc_ctrl0, + clrsetbits32(&ch[chn].phy.misc_ctrl0, (0x1 << 24) | (0x1f << 11) | (0xf << 0), (0x1 << 24) | (0x0 << 11) | (0x0 << 0)); - clrbits_le32(&ch[chn].phy.b[0].dq[6], 0x1 << 31); - clrbits_le32(&ch[chn].phy.b[1].dq[6], 0x1 << 31); - clrbits_le32(&ch[chn].phy.ca_cmd[6], 0x1 << 31); + clrbits32(&ch[chn].phy.b[0].dq[6], 0x1 << 31); + clrbits32(&ch[chn].phy.b[1].dq[6], 0x1 << 31); + clrbits32(&ch[chn].phy.ca_cmd[6], 0x1 << 31); } static void dramc_hw_gating_init(void) { for (size_t chn = 0; chn < CHANNEL_MAX; chn++) { - clrbits_le32(&ch[chn].ao.stbcal, + clrbits32(&ch[chn].ao.stbcal, (0x7 << 22) | (0x3 << 14) | (0x1 << 19) | (0x1 << 21)); - setbits_le32(&ch[chn].ao.stbcal, (0x1 << 20) | (0x3 << 28)); - setbits_le32(&ch[chn].phy.misc_ctrl1, 0x1 << 24); + setbits32(&ch[chn].ao.stbcal, (0x1 << 20) | (0x3 << 28)); + setbits32(&ch[chn].phy.misc_ctrl1, 0x1 << 24); dramc_hw_dqs_gating_tracking(chn); } @@ -335,28 +335,28 @@ static void dramc_hw_gating_init(void) static void dramc_impedance_tracking_enable(void) { - setbits_le32(&ch[0].phy.misc_ctrl0, 0x1 << 10); + setbits32(&ch[0].phy.misc_ctrl0, 0x1 << 10); for (size_t chn = 0; chn < CHANNEL_MAX; chn++) { - setbits_le32(&ch[chn].ao.impcal, (0x1 << 31) | (0x1 << 29) | + setbits32(&ch[chn].ao.impcal, (0x1 << 31) | (0x1 << 29) | (0x1 << 26) | (0x1 << 17) | (0x7 << 11)); - clrbits_le32(&ch[chn].ao.impcal, 0x1 << 30); - setbits_le32(&ch[chn].phy.misc_ctrl0, 0x1 << 18); - setbits_le32(&ch[chn].ao.impcal, 0x1 << 19); + clrbits32(&ch[chn].ao.impcal, 0x1 << 30); + setbits32(&ch[chn].phy.misc_ctrl0, 0x1 << 18); + setbits32(&ch[chn].ao.impcal, 0x1 << 19); } - setbits_le32(&ch[0].ao.impcal, 0x1 << 14); + setbits32(&ch[0].ao.impcal, 0x1 << 14); for (size_t chn = 0; chn < CHANNEL_MAX; chn++) - setbits_le32(&ch[chn].ao.refctrl0, (0x1 << 2) | (0x1 << 3)); + setbits32(&ch[chn].ao.refctrl0, (0x1 << 2) | (0x1 << 3)); } static void dramc_phy_low_power_enable(void) { for (size_t chn = 0; chn < CHANNEL_MAX; chn++) { for (size_t b = 0; b < 2; b++) { - clrbits_le32(&ch[chn].phy.b[b].dll_fine_tune[2], + clrbits32(&ch[chn].phy.b[b].dll_fine_tune[2], 0x3fffff << 10); write32(&ch[chn].phy.b[b].dll_fine_tune[3], 0x2e800); } - clrsetbits_le32(&ch[chn].phy.ca_dll_fine_tune[2], + clrsetbits32(&ch[chn].phy.ca_dll_fine_tune[2], 0x3fffff << 10, 0x2 << 10); } write32(&ch[0].phy.ca_dll_fine_tune[3], 0xba000); @@ -365,67 +365,67 @@ static void dramc_phy_low_power_enable(void) static void dramc_dummy_read_for_tracking_enable(u8 chn) { - setbits_le32(&ch[chn].ao.dummy_rd, 0x3 << 16); + setbits32(&ch[chn].ao.dummy_rd, 0x3 << 16); for (size_t r = 0; r < 2; r++) for (size_t i = 0; i < 4; i++) write32(&ch[chn].ao.rk[r].dummy_rd_wdata[i], 0xaaaa5555); - clrsetbits_le32(&ch[chn].ao.test2_4, 0x7 << 28, 0x4 << 28); + clrsetbits32(&ch[chn].ao.test2_4, 0x7 << 28, 0x4 << 28); for (size_t r = 0; r < 2; r++) { - clrsetbits_le32(&ch[chn].ao.rk[r].dummy_rd_adr, + clrsetbits32(&ch[chn].ao.rk[r].dummy_rd_adr, (0x1ffff << 0) | (0x7ff << 17) | (0xf << 28), (0xffff << 0) | (0x3f0 << 17)); - clrbits_le32(&ch[chn].ao.rk[r].dummy_rd_bk, 0x7 << 0); + clrbits32(&ch[chn].ao.rk[r].dummy_rd_bk, 0x7 << 0); } - clrbits_le32(&ch[chn].ao.dummy_rd, 0x1 << 25 | 0x1 << 20); + clrbits32(&ch[chn].ao.dummy_rd, 0x1 << 25 | 0x1 << 20); } static void dramc_set_CKE_2_rank_independent(u8 chn) { - clrsetbits_le32(&ch[chn].ao.rkcfg, (0x1 << 15) | (0x1 << 12), 0x1 << 2); - clrsetbits_le32(&ch[chn].ao.ckectrl, + clrsetbits32(&ch[chn].ao.rkcfg, (0x1 << 15) | (0x1 << 12), 0x1 << 2); + clrsetbits32(&ch[chn].ao.ckectrl, (0x1 << 1) | (0xf << 8) | (0x7 << 13), (0x4 << 8) | (0x2 << 13)); for (u8 shu = 0; shu < DRAM_DFS_SHUFFLE_MAX; shu++) - setbits_le32(&ch[chn].ao.shu[shu].conf[2], + setbits32(&ch[chn].ao.shu[shu].conf[2], (0x1 << 29) | (0x1 << 31)); - clrbits_le32(&ch[chn].ao.dramctrl, 0x1 << 9); + clrbits32(&ch[chn].ao.dramctrl, 0x1 << 9); } static void dramc_pa_improve(u8 chn) { - clrbits_le32(&ch[chn].ao.clkar, 0xffff); - clrbits_le32(&ch[chn].ao.srefctrl, 0xf << 12); - clrbits_le32(&ch[chn].ao.zqcs, 0x1 << 19); - clrbits_le32(&ch[chn].ao.pre_tdqsck[0], 0x1 << 17); - clrbits_le32(&ch[chn].ao.zqcs, 0x1 << 19); - clrbits_le32(&ch[chn].ao.pre_tdqsck[0], 0x1 << 17); + clrbits32(&ch[chn].ao.clkar, 0xffff); + clrbits32(&ch[chn].ao.srefctrl, 0xf << 12); + clrbits32(&ch[chn].ao.zqcs, 0x1 << 19); + clrbits32(&ch[chn].ao.pre_tdqsck[0], 0x1 << 17); + clrbits32(&ch[chn].ao.zqcs, 0x1 << 19); + clrbits32(&ch[chn].ao.pre_tdqsck[0], 0x1 << 17); for (u8 shu = 0; shu < DRAM_DFS_SHUFFLE_MAX; shu++) - clrbits_le32(&ch[chn].ao.shu[shu].odtctrl, 0x3 << 2); + clrbits32(&ch[chn].ao.shu[shu].odtctrl, 0x3 << 2); } static void dramc_enable_dramc_dcm(void) { for (size_t chn = 0; chn < CHANNEL_MAX; chn++) { - clrsetbits_le32(&ch[chn].ao.dramc_pd_ctrl, + clrsetbits32(&ch[chn].ao.dramc_pd_ctrl, (0x7 << 0) | (0x1 << 26) | (0x1 << 30) | (0x1 << 31), (0x7 << 0) | (0x1 << 30) | (0x1 << 31)); - setbits_le32(&ch[chn].ao.clkar, 0x1 << 31); + setbits32(&ch[chn].ao.clkar, 0x1 << 31); } } void dramc_runtime_config(void) { - clrbits_le32(&ch[0].ao.refctrl0, 0x1 << 29); - clrbits_le32(&ch[1].ao.refctrl0, 0x1 << 29); + clrbits32(&ch[0].ao.refctrl0, 0x1 << 29); + clrbits32(&ch[1].ao.refctrl0, 0x1 << 29); transfer_pll_to_spm_control(); - setbits_le32(&mtk_spm->spm_power_on_val0, 0x1 << 25); + setbits32(&mtk_spm->spm_power_on_val0, 0x1 << 25); /* RX_TRACKING: ON */ for (u8 chn = 0; chn < CHANNEL_MAX; chn++) @@ -438,7 +438,7 @@ void dramc_runtime_config(void) /* HW_GATING DBG: OFF */ for (size_t chn = 0; chn < CHANNEL_MAX; chn++) - clrbits_le32(&ch[chn].ao.stbcal2, + clrbits32(&ch[chn].ao.stbcal2, (0x3 << 4) | (0x3 << 8) | (0x1 << 28)); /* DUMMY_READ_FOR_TRACKING: ON */ @@ -446,8 +446,8 @@ void dramc_runtime_config(void) dramc_dummy_read_for_tracking_enable(chn); /* ZQCS_ENABLE_LP4: ON */ - clrbits_le32(&ch[0].ao.spcmdctrl, 0x1 << 30); - clrbits_le32(&ch[1].ao.spcmdctrl, 0x1 << 30); + clrbits32(&ch[0].ao.spcmdctrl, 0x1 << 30); + clrbits32(&ch[1].ao.spcmdctrl, 0x1 << 30); /* LOWPOWER_GOLDEN_SETTINGS(DCM): ON */ dramc_phy_low_power_enable(); @@ -456,7 +456,7 @@ void dramc_runtime_config(void) /* DUMMY_READ_FOR_DQS_GATING_RETRY: OFF */ for (size_t chn = 0; chn < CHANNEL_MAX; chn++) for (size_t shu = 0; shu < DRAM_DFS_SHUFFLE_MAX; shu++) - clrbits_le32(&ch[chn].ao.shu[shu].dqsg_retry, + clrbits32(&ch[chn].ao.shu[shu].dqsg_retry, (0x1 << 1) | (0x3 << 13)); /* SPM_CONTROL_AFTERK: ON */ @@ -470,33 +470,33 @@ void dramc_runtime_config(void) for (size_t chn = 0; chn < CHANNEL_MAX; chn++) { /* TEMP_SENSOR: ON */ - clrbits_le32(&ch[chn].ao.spcmdctrl, 0x3 << 28); - setbits_le32(&ch[chn].ao.hw_mrr_fun, (0x1 << 0) | (0x1 << 11)); + clrbits32(&ch[chn].ao.spcmdctrl, 0x3 << 28); + setbits32(&ch[chn].ao.hw_mrr_fun, (0x1 << 0) | (0x1 << 11)); /* PER_BANK_REFRESH: ON */ - clrbits_le32(&ch[chn].ao.refctrl0, 0x1 << 18); + clrbits32(&ch[chn].ao.refctrl0, 0x1 << 18); /* HW_SAVE_FOR_SR: ON */ - clrbits_le32(&ch[chn].ao.rstmask, (0x1 << 25) | (0x1 << 28)); - setbits_le32(&ch[chn].ao.refctrl1, 0x1 << 0); - clrsetbits_le32(&ch[chn].ao.srefctrl, 0x1 << 20, 0x1 << 22); + clrbits32(&ch[chn].ao.rstmask, (0x1 << 25) | (0x1 << 28)); + setbits32(&ch[chn].ao.refctrl1, 0x1 << 0); + clrsetbits32(&ch[chn].ao.srefctrl, 0x1 << 20, 0x1 << 22); /* SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON */ dramc_set_CKE_2_rank_independent(chn); /* CLK_FREE_FUN_FOR_DRAMC_PSEL: ON */ - clrbits_le32(&ch[chn].ao.refctrl1, (0x1 << 6) | (0x3 << 2)); - clrbits_le32(&ch[chn].ao.clkar, 0x1 << 19); + clrbits32(&ch[chn].ao.refctrl1, (0x1 << 6) | (0x3 << 2)); + clrbits32(&ch[chn].ao.clkar, 0x1 << 19); /* PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: ON */ dramc_pa_improve(chn); /* DRAM DRS DISABLE */ - clrsetbits_le32(&ch[chn].ao.drsctrl, + clrsetbits32(&ch[chn].ao.drsctrl, (0x1 << 21) | (0x3f << 12) | (0xf << 8) | (0x1 << 6), (0x1 << 19) | (0x3 << 12) | (0x8 << 8) | (0x3 << 4) | (0x1 << 2) | (0x1 << 0)); - setbits_le32(&ch[chn].ao.dummy_rd, 0x3 << 26); + setbits32(&ch[chn].ao.dummy_rd, 0x3 << 26); } enable_emi_dcm(); diff --git a/src/soc/mediatek/mt8183/dramc_pi_calibration_api.c b/src/soc/mediatek/mt8183/dramc_pi_calibration_api.c index 16f28785d3..cd9f328ae6 100644 --- a/src/soc/mediatek/mt8183/dramc_pi_calibration_api.c +++ b/src/soc/mediatek/mt8183/dramc_pi_calibration_api.c @@ -154,8 +154,8 @@ static void move_dramc_delay(u32 *reg_0, u32 *reg_1, u8 shift, s8 shift_coarse_t tmp_0p5t = sum - (tmp_2t << DQ_DIV_SHIFT); } - clrsetbits_le32(reg_0, DQ_DIV_MASK << shift, tmp_0p5t << shift); - clrsetbits_le32(reg_1, DQ_DIV_MASK << shift, tmp_2t << shift); + clrsetbits32(reg_0, DQ_DIV_MASK << shift, tmp_0p5t << shift); + clrsetbits32(reg_1, DQ_DIV_MASK << shift, tmp_2t << shift); } static void move_dramc_tx_dqs(u8 chn, u8 byte, s8 shift_coarse_tune) @@ -279,36 +279,36 @@ static void dramc_write_dbi_onoff(bool onoff) static void dramc_phy_dcm_2_channel(u8 chn, bool en) { - clrsetbits_le32(&ch[chn].phy.misc_cg_ctrl0, (0x3 << 19) | (0x3ff << 8), + clrsetbits32(&ch[chn].phy.misc_cg_ctrl0, (0x3 << 19) | (0x3ff << 8), ((en ? 0 : 0x1) << 19) | ((en ? 0 : 0x1ff) << 9) | (1 << 8)); for (size_t i = 0; i < DRAM_DFS_SHUFFLE_MAX; i++) { struct ddrphy_ao_shu *shu = &ch[chn].phy.shu[i]; for (size_t b = 0; b < 2; b++) - clrsetbits_le32(&shu->b[b].dq[8], 0x1fff << 19, + clrsetbits32(&shu->b[b].dq[8], 0x1fff << 19, ((en ? 0 : 0x7ff) << 22) | (0x1 << 21) | ((en ? 0 : 0x3) << 19)); - clrbits_le32(&shu->ca_cmd[8], 0x1fff << 19); + clrbits32(&shu->ca_cmd[8], 0x1fff << 19); } - clrsetbits_le32(&ch[chn].phy.misc_cg_ctrl5, (0x7 << 16) | (0x7 << 20), + clrsetbits32(&ch[chn].phy.misc_cg_ctrl5, (0x7 << 16) | (0x7 << 20), ((en ? 0x7 : 0) << 16) | ((en ? 0x7 : 0) << 20)); } void dramc_enable_phy_dcm(bool en) { for (size_t chn = 0; chn < CHANNEL_MAX ; chn++) { - clrbits_le32(&ch[chn].phy.b[0].dll_fine_tune[1], 0x1 << 20); - clrbits_le32(&ch[chn].phy.b[1].dll_fine_tune[1], 0x1 << 20); - clrbits_le32(&ch[chn].phy.ca_dll_fine_tune[1], 0x1 << 20); + clrbits32(&ch[chn].phy.b[0].dll_fine_tune[1], 0x1 << 20); + clrbits32(&ch[chn].phy.b[1].dll_fine_tune[1], 0x1 << 20); + clrbits32(&ch[chn].phy.ca_dll_fine_tune[1], 0x1 << 20); for (size_t i = 0; i < DRAM_DFS_SHUFFLE_MAX; i++) { struct ddrphy_ao_shu *shu = &ch[chn].phy.shu[i]; - setbits_le32(&shu->b[0].dll[0], 0x1); - setbits_le32(&shu->b[1].dll[0], 0x1); - setbits_le32(&shu->ca_dll[0], 0x1); + setbits32(&shu->b[0].dll[0], 0x1); + setbits32(&shu->b[1].dll[0], 0x1); + setbits32(&shu->ca_dll[0], 0x1); } - clrsetbits_le32(&ch[chn].ao.dramc_pd_ctrl, + clrsetbits32(&ch[chn].ao.dramc_pd_ctrl, (0x1 << 0) | (0x1 << 1) | (0x1 << 2) | (0x1 << 5) | (0x1 << 26) | (0x1 << 30) | (0x1 << 31), ((en ? 0x1 : 0) << 0) | ((en ? 0x1 : 0) << 1) | @@ -324,16 +324,16 @@ void dramc_enable_phy_dcm(bool en) write32(&ch[chn].phy.misc_cg_ctrl2, 0x8060033e | (0x40 << (en ? 0x1 : 0))); - clrsetbits_le32(&ch[chn].phy.misc_ctrl3, 0x3 << 26, + clrsetbits32(&ch[chn].phy.misc_ctrl3, 0x3 << 26, (en ? 0 : 0x3) << 26); for (size_t i = 0; i < DRAM_DFS_SHUFFLE_MAX; i++) { u32 mask = 0x7 << 17; u32 value = (en ? 0x7 : 0) << 17; struct ddrphy_ao_shu *shu = &ch[chn].phy.shu[i]; - clrsetbits_le32(&shu->b[0].dq[7], mask, value); - clrsetbits_le32(&shu->b[1].dq[7], mask, value); - clrsetbits_le32(&shu->ca_cmd[7], mask, value); + clrsetbits32(&shu->b[0].dq[7], mask, value); + clrsetbits32(&shu->b[1].dq[7], mask, value); + clrsetbits32(&shu->ca_cmd[7], mask, value); } dramc_phy_dcm_2_channel(chn, en); @@ -346,31 +346,31 @@ static void dramc_reset_delay_chain_before_calibration(void) for (size_t rank = 0; rank < RANK_MAX; rank++) { struct dramc_ddrphy_regs_shu_rk *rk; rk = &ch[chn].phy.shu[0].rk[rank]; - clrbits_le32(&rk->ca_cmd[0], 0xffffff << 0); - clrbits_le32(&rk->b[0].dq[0], 0xfffffff << 0); - clrbits_le32(&rk->b[1].dq[0], 0xfffffff << 0); - clrbits_le32(&rk->b[0].dq[1], 0xf << 0); - clrbits_le32(&rk->b[1].dq[1], 0xf << 0); + clrbits32(&rk->ca_cmd[0], 0xffffff << 0); + clrbits32(&rk->b[0].dq[0], 0xfffffff << 0); + clrbits32(&rk->b[1].dq[0], 0xfffffff << 0); + clrbits32(&rk->b[0].dq[1], 0xf << 0); + clrbits32(&rk->b[1].dq[1], 0xf << 0); } } void dramc_hw_gating_onoff(u8 chn, bool on) { - clrsetbits_le32(&ch[chn].ao.shuctrl2, 0x3 << 14, + clrsetbits32(&ch[chn].ao.shuctrl2, 0x3 << 14, (on ? 0x3 : 0) << 14); - clrsetbits_le32(&ch[chn].ao.stbcal2, 0x1 << 28, (on ? 0x1 : 0) << 28); - clrsetbits_le32(&ch[chn].ao.stbcal, 0x1 << 24, (on ? 0x1 : 0) << 24); - clrsetbits_le32(&ch[chn].ao.stbcal, 0x1 << 22, (on ? 0x1 : 0) << 22); + clrsetbits32(&ch[chn].ao.stbcal2, 0x1 << 28, (on ? 0x1 : 0) << 28); + clrsetbits32(&ch[chn].ao.stbcal, 0x1 << 24, (on ? 0x1 : 0) << 24); + clrsetbits32(&ch[chn].ao.stbcal, 0x1 << 22, (on ? 0x1 : 0) << 22); } static void dramc_rx_input_delay_tracking_init_by_freq(u8 chn) { struct ddrphy_ao_shu *shu = &ch[chn].phy.shu[0]; - clrsetbits_le32(&shu->b[0].dq[5], 0x7 << 20, 0x3 << 20); - clrsetbits_le32(&shu->b[1].dq[5], 0x7 << 20, 0x3 << 20); - clrbits_le32(&shu->b[0].dq[7], (0x1 << 12) | (0x1 << 13)); - clrbits_le32(&shu->b[1].dq[7], (0x1 << 12) | (0x1 << 13)); + clrsetbits32(&shu->b[0].dq[5], 0x7 << 20, 0x3 << 20); + clrsetbits32(&shu->b[1].dq[5], 0x7 << 20, 0x3 << 20); + clrbits32(&shu->b[0].dq[7], (0x1 << 12) | (0x1 << 13)); + clrbits32(&shu->b[1].dq[7], (0x1 << 12) | (0x1 << 13)); } void dramc_apply_config_before_calibration(u8 freq_group) @@ -378,55 +378,55 @@ void dramc_apply_config_before_calibration(u8 freq_group) dramc_enable_phy_dcm(false); dramc_reset_delay_chain_before_calibration(); - setbits_le32(&ch[0].ao.shu[0].conf[3], 0x1ff << 16); - setbits_le32(&ch[0].ao.spcmdctrl, 0x1 << 24); - clrsetbits_le32(&ch[0].ao.shu[0].scintv, 0x1f << 1, 0x1b << 1); + setbits32(&ch[0].ao.shu[0].conf[3], 0x1ff << 16); + setbits32(&ch[0].ao.spcmdctrl, 0x1 << 24); + clrsetbits32(&ch[0].ao.shu[0].scintv, 0x1f << 1, 0x1b << 1); for (size_t shu = DRAM_DFS_SHUFFLE_1; shu < DRAM_DFS_SHUFFLE_MAX; shu++) - setbits_le32(&ch[0].ao.shu[shu].conf[3], 0x1ff << 0); + setbits32(&ch[0].ao.shu[shu].conf[3], 0x1ff << 0); - clrbits_le32(&ch[0].ao.dramctrl, 0x1 << 18); - clrbits_le32(&ch[0].ao.spcmdctrl, 0x1 << 31); - clrbits_le32(&ch[0].ao.spcmdctrl, 0x1 << 30); - clrbits_le32(&ch[0].ao.dqsoscr, 0x1 << 26); - clrbits_le32(&ch[0].ao.dqsoscr, 0x1 << 25); + clrbits32(&ch[0].ao.dramctrl, 0x1 << 18); + clrbits32(&ch[0].ao.spcmdctrl, 0x1 << 31); + clrbits32(&ch[0].ao.spcmdctrl, 0x1 << 30); + clrbits32(&ch[0].ao.dqsoscr, 0x1 << 26); + clrbits32(&ch[0].ao.dqsoscr, 0x1 << 25); dramc_write_dbi_onoff(false); dramc_read_dbi_onoff(false); for (size_t chn = 0; chn < CHANNEL_MAX; chn++) { - setbits_le32(&ch[chn].ao.spcmdctrl, 0x1 << 29); - setbits_le32(&ch[chn].ao.dqsoscr, 0x1 << 24); + setbits32(&ch[chn].ao.spcmdctrl, 0x1 << 29); + setbits32(&ch[chn].ao.dqsoscr, 0x1 << 24); for (size_t shu = DRAM_DFS_SHUFFLE_1; shu < DRAM_DFS_SHUFFLE_MAX; shu++) - setbits_le32(&ch[chn].ao.shu[shu].scintv, 0x1 << 30); + setbits32(&ch[chn].ao.shu[shu].scintv, 0x1 << 30); - clrbits_le32(&ch[chn].ao.dummy_rd, (0x1 << 7) | (0x7 << 20)); + clrbits32(&ch[chn].ao.dummy_rd, (0x1 << 7) | (0x7 << 20)); dramc_hw_gating_onoff(chn, false); - clrbits_le32(&ch[chn].ao.stbcal2, 0x1 << 28); + clrbits32(&ch[chn].ao.stbcal2, 0x1 << 28); - setbits_le32(&ch[chn].phy.misc_ctrl1, (0x1 << 7) | (0x1 << 11)); - clrbits_le32(&ch[chn].ao.refctrl0, 0x1 << 18); - clrbits_le32(&ch[chn].ao.mrs, 0x3 << 24); - setbits_le32(&ch[chn].ao.mpc_option, 0x1 << 17); - clrsetbits_le32(&ch[chn].phy.b[0].dq[6], 0x3 << 0, 0x1 << 0); - clrsetbits_le32(&ch[chn].phy.b[1].dq[6], 0x3 << 0, 0x1 << 0); - clrsetbits_le32(&ch[chn].phy.ca_cmd[6], 0x3 << 0, 0x1 << 0); + setbits32(&ch[chn].phy.misc_ctrl1, (0x1 << 7) | (0x1 << 11)); + clrbits32(&ch[chn].ao.refctrl0, 0x1 << 18); + clrbits32(&ch[chn].ao.mrs, 0x3 << 24); + setbits32(&ch[chn].ao.mpc_option, 0x1 << 17); + clrsetbits32(&ch[chn].phy.b[0].dq[6], 0x3 << 0, 0x1 << 0); + clrsetbits32(&ch[chn].phy.b[1].dq[6], 0x3 << 0, 0x1 << 0); + clrsetbits32(&ch[chn].phy.ca_cmd[6], 0x3 << 0, 0x1 << 0); dramc_rx_input_delay_tracking_init_by_freq(chn); - setbits_le32(&ch[chn].ao.dummy_rd, 0x1 << 25); - setbits_le32(&ch[chn].ao.drsctrl, 0x1 << 0); + setbits32(&ch[chn].ao.dummy_rd, 0x1 << 25); + setbits32(&ch[chn].ao.drsctrl, 0x1 << 0); if (freq_group == LP4X_DDR3200 || freq_group == LP4X_DDR3600) - clrbits_le32(&ch[chn].ao.shu[1].drving[1], 0x1 << 31); + clrbits32(&ch[chn].ao.shu[1].drving[1], 0x1 << 31); else - setbits_le32(&ch[chn].ao.shu[1].drving[1], 0x1 << 31); + setbits32(&ch[chn].ao.shu[1].drving[1], 0x1 << 31); } for (size_t r = 0; r < 2; r++) { for (size_t b = 0; b < 2; b++) - clrbits_le32(&ch[0].phy.r[r].b[b].rxdvs[2], + clrbits32(&ch[0].phy.r[r].b[b].rxdvs[2], (0x1 << 28) | (0x1 << 23) | (0x3 << 30)); - clrbits_le32(&ch[0].phy.r0_ca_rxdvs[2], 0x3 << 30); + clrbits32(&ch[0].phy.r0_ca_rxdvs[2], 0x3 << 30); } } @@ -437,51 +437,51 @@ static void dramc_set_mr13_vrcg_to_Normal(u8 chn, const struct mr_value *mr) mr->MR13Value & ~(0x1 << 3)); for (u8 shu = 0; shu < DRAM_DFS_SHUFFLE_MAX; shu++) - clrbits_le32(&ch[chn].ao.shu[shu].hwset_vrcg, 0x1 << 19); + clrbits32(&ch[chn].ao.shu[shu].hwset_vrcg, 0x1 << 19); } void dramc_apply_config_after_calibration(const struct mr_value *mr) { for (size_t chn = 0; chn < CHANNEL_MAX; chn++) { write32(&ch[chn].phy.misc_cg_ctrl4, 0x11400000); - clrbits_le32(&ch[chn].ao.refctrl1, 0x1 << 7); - clrbits_le32(&ch[chn].ao.shuctrl, 0x1 << 2); - clrbits_le32(&ch[chn].phy.ca_cmd[6], 0x1 << 6); + clrbits32(&ch[chn].ao.refctrl1, 0x1 << 7); + clrbits32(&ch[chn].ao.shuctrl, 0x1 << 2); + clrbits32(&ch[chn].phy.ca_cmd[6], 0x1 << 6); dramc_set_mr13_vrcg_to_Normal(chn, mr); - clrbits_le32(&ch[chn].phy.b[0].dq[6], 0x3); - clrbits_le32(&ch[chn].phy.b[1].dq[6], 0x3); - clrbits_le32(&ch[chn].phy.ca_cmd[6], 0x3); - setbits_le32(&ch[chn].phy.b[0].dq[6], 0x1 << 5); - setbits_le32(&ch[chn].phy.b[1].dq[6], 0x1 << 5); - setbits_le32(&ch[chn].phy.ca_cmd[6], 0x1 << 5); + clrbits32(&ch[chn].phy.b[0].dq[6], 0x3); + clrbits32(&ch[chn].phy.b[1].dq[6], 0x3); + clrbits32(&ch[chn].phy.ca_cmd[6], 0x3); + setbits32(&ch[chn].phy.b[0].dq[6], 0x1 << 5); + setbits32(&ch[chn].phy.b[1].dq[6], 0x1 << 5); + setbits32(&ch[chn].phy.ca_cmd[6], 0x1 << 5); - clrbits_le32(&ch[chn].ao.impcal, 0x3 << 24); - clrbits_le32(&ch[chn].phy.misc_imp_ctrl0, 0x4); - clrbits_le32(&ch[chn].phy.misc_cg_ctrl0, 0xf); + clrbits32(&ch[chn].ao.impcal, 0x3 << 24); + clrbits32(&ch[chn].phy.misc_imp_ctrl0, 0x4); + clrbits32(&ch[chn].phy.misc_cg_ctrl0, 0xf); - clrbits_le32(&ch[chn].phy.misc_ctrl0, 0x1 << 31); - clrbits_le32(&ch[chn].phy.misc_ctrl1, 0x1 << 25); + clrbits32(&ch[chn].phy.misc_ctrl0, 0x1 << 31); + clrbits32(&ch[chn].phy.misc_ctrl1, 0x1 << 25); - setbits_le32(&ch[chn].ao.spcmdctrl, 1 << 29); - setbits_le32(&ch[chn].ao.dqsoscr, 1 << 24); + setbits32(&ch[chn].ao.spcmdctrl, 1 << 29); + setbits32(&ch[chn].ao.dqsoscr, 1 << 24); for (u8 shu = 0; shu < DRAM_DFS_SHUFFLE_MAX; shu++) - clrbits_le32(&ch[chn].ao.shu[shu].scintv, 0x1 << 30); + clrbits32(&ch[chn].ao.shu[shu].scintv, 0x1 << 30); - clrbits_le32(&ch[chn].ao.dummy_rd, (0x7 << 20) | (0x1 << 7)); + clrbits32(&ch[chn].ao.dummy_rd, (0x7 << 20) | (0x1 << 7)); dramc_cke_fix_onoff(chn, false, false); - clrbits_le32(&ch[chn].ao.dramc_pd_ctrl, 0x1 << 26); + clrbits32(&ch[chn].ao.dramc_pd_ctrl, 0x1 << 26); - clrbits_le32(&ch[chn].ao.eyescan, 0x7 << 8); - clrsetbits_le32(&ch[chn].ao.test2_4, 0x7 << 28, 0x4 << 28); + clrbits32(&ch[chn].ao.eyescan, 0x7 << 8); + clrsetbits32(&ch[chn].ao.test2_4, 0x7 << 28, 0x4 << 28); } } static void dramc_rx_dqs_isi_pulse_cg_switch(u8 chn, bool flag) { for (size_t b = 0; b < 2; b++) - clrsetbits_le32(&ch[chn].phy.b[b].dq[6], 1 << 5, + clrsetbits32(&ch[chn].phy.b[b].dq[6], 1 << 5, (flag ? 1 : 0) << 5); } @@ -600,7 +600,7 @@ static u32 dramc_engine2_run(u8 chn, enum dram_te_op wr) static void dramc_engine2_end(u8 chn, u32 dummy_rd) { - clrbits_le32(&ch[chn].ao.test2_4, 0x1 << 17); + clrbits32(&ch[chn].ao.test2_4, 0x1 << 17); write32(&ch[chn].ao.dummy_rd, dummy_rd); } @@ -717,12 +717,12 @@ static void dram_phy_reset(u8 chn) { SET32_BITFIELDS(&ch[chn].ao.ddrconf0, DDRCONF0_RDATRST, 1); SET32_BITFIELDS(&ch[chn].phy.misc_ctrl1, MISC_CTRL1_R_DMPHYRST, 1); - clrbits_le32(&ch[chn].phy.b[0].dq[9], (1 << 4) | (1 << 0)); - clrbits_le32(&ch[chn].phy.b[1].dq[9], (1 << 4) | (1 << 0)); + clrbits32(&ch[chn].phy.b[0].dq[9], (1 << 4) | (1 << 0)); + clrbits32(&ch[chn].phy.b[1].dq[9], (1 << 4) | (1 << 0)); udelay(1); - setbits_le32(&ch[chn].phy.b[1].dq[9], (1 << 4) | (1 << 0)); - setbits_le32(&ch[chn].phy.b[0].dq[9], (1 << 4) | (1 << 0)); + setbits32(&ch[chn].phy.b[1].dq[9], (1 << 4) | (1 << 0)); + setbits32(&ch[chn].phy.b[0].dq[9], (1 << 4) | (1 << 0)); SET32_BITFIELDS(&ch[chn].phy.misc_ctrl1, MISC_CTRL1_R_DMPHYRST, 0); SET32_BITFIELDS(&ch[chn].ao.ddrconf0, DDRCONF0_RDATRST, 0); } @@ -737,18 +737,18 @@ static void dramc_set_gating_mode(u8 chn, bool mode) } for (size_t b = 0; b < 2; b++) { - clrsetbits_le32(&ch[chn].phy.b[b].dq[6], 0x3 << 14, vref << 14); - setbits_le32(&ch[chn].phy.b[b].dq[9], 0x1 << 5); + clrsetbits32(&ch[chn].phy.b[b].dq[6], 0x3 << 14, vref << 14); + setbits32(&ch[chn].phy.b[b].dq[9], 0x1 << 5); } - clrsetbits_le32(&ch[chn].ao.stbcal1, 0x1 << 5, burst << 5); - setbits_le32(&ch[chn].ao.stbcal, 0x1 << 30); + clrsetbits32(&ch[chn].ao.stbcal1, 0x1 << 5, burst << 5); + setbits32(&ch[chn].ao.stbcal, 0x1 << 30); - clrbits_le32(&ch[chn].phy.b[0].dq[9], (0x1 << 4) | (0x1 << 0)); - clrbits_le32(&ch[chn].phy.b[1].dq[9], (0x1 << 4) | (0x1 << 0)); + clrbits32(&ch[chn].phy.b[0].dq[9], (0x1 << 4) | (0x1 << 0)); + clrbits32(&ch[chn].phy.b[1].dq[9], (0x1 << 4) | (0x1 << 0)); udelay(1); - setbits_le32(&ch[chn].phy.b[1].dq[9], (0x1 << 4) | (0x1 << 0)); - setbits_le32(&ch[chn].phy.b[0].dq[9], (0x1 << 4) | (0x1 << 0)); + setbits32(&ch[chn].phy.b[1].dq[9], (0x1 << 4) | (0x1 << 0)); + setbits32(&ch[chn].phy.b[0].dq[9], (0x1 << 4) | (0x1 << 0)); } static void dramc_rx_dqs_gating_cal_pre(u8 chn, u8 rank) @@ -773,7 +773,7 @@ static void dramc_rx_dqs_gating_cal_pre(u8 chn, u8 rank) static void set_selph_gating_value(uint32_t *addr, u8 dly, u8 dly_p1) { - clrsetbits_le32(addr, 0x77777777, + clrsetbits32(addr, 0x77777777, (dly << 0) | (dly << 8) | (dly << 16) | (dly << 24) | (dly_p1 << 4) | (dly_p1 << 12) | (dly_p1 << 20) | (dly_p1 << 28)); } @@ -788,11 +788,11 @@ static void dramc_write_dqs_gating_result(u8 chn, u8 rank, dramc_rx_dqs_isi_pulse_cg_switch(chn, true); - clrsetbits_le32(&ch[chn].ao.shu[0].rk[rank].selph_dqsg0, + clrsetbits32(&ch[chn].ao.shu[0].rk[rank].selph_dqsg0, 0x77777777, (best_coarse_tune2t[0] << 0) | (best_coarse_tune2t[1] << 8) | (best_coarse_tune2t_p1[0] << 4) | (best_coarse_tune2t_p1[1] << 12)); - clrsetbits_le32(&ch[chn].ao.shu[0].rk[rank].selph_dqsg1, + clrsetbits32(&ch[chn].ao.shu[0].rk[rank].selph_dqsg1, 0x77777777, (best_coarse_tune0p5t[0] << 0) | (best_coarse_tune0p5t[1] << 8) | (best_coarse_tune0p5t_p1[0] << 4) | (best_coarse_tune0p5t_p1[1] << 12)); @@ -827,11 +827,11 @@ static void dramc_write_dqs_gating_result(u8 chn, u8 rank, } } - clrsetbits_le32(&ch[chn].ao.shu[0].rk[rank].selph_odten0, + clrsetbits32(&ch[chn].ao.shu[0].rk[rank].selph_odten0, 0x77777777, (best_coarse_rodt[0] << 0) | (best_coarse_rodt[1] << 8) | (best_coarse_rodt_p1[0] << 4) | (best_coarse_rodt_p1[1] << 12)); - clrsetbits_le32(&ch[chn].ao.shu[0].rk[rank].selph_odten1, + clrsetbits32(&ch[chn].ao.shu[0].rk[rank].selph_odten1, 0x77777777, (best_coarse_0p5t_rodt[0] << 0) | (best_coarse_0p5t_rodt[1] << 8) | (best_coarse_0p5t_rodt_p1[0] << 4) | (best_coarse_0p5t_rodt_p1[1] << 12)); @@ -1063,7 +1063,7 @@ static void dramc_rx_rd_dqc_init(u8 chn, u8 rank) u16 temp_value = 0; for (size_t b = 0; b < 2; b++) - clrbits_le32(&ch[chn].phy.shu[0].b[b].dq[7], 0x1 << 7); + clrbits32(&ch[chn].phy.shu[0].b[b].dq[7], 0x1 << 7); SET32_BITFIELDS(&ch[chn].ao.mrs, MRS_MRSRK, rank); SET32_BITFIELDS(&ch[chn].ao.mpc_option, MPC_OPTION_MPCRKEN, 1); @@ -1213,17 +1213,17 @@ static void dramc_set_tx_dly_factor(u8 chn, u8 rk, if (*dq_small_reg != dly_tune.coarse_tune_small) { if (type == TX_WIN_DQ_DQM || type == TX_WIN_DQ_ONLY) { - clrsetbits_le32(&ch[chn].ao.shu[0].rk[rk].selph_dq[0], + clrsetbits32(&ch[chn].ao.shu[0].rk[rk].selph_dq[0], 0x77777777, dly_large | (dly_large_oen << 16)); - clrsetbits_le32(&ch[chn].ao.shu[0].rk[rk].selph_dq[2], + clrsetbits32(&ch[chn].ao.shu[0].rk[rk].selph_dq[2], 0x77777777, dly_small | (dly_small_oen << 16)); } if (type == TX_WIN_DQ_DQM) { /* Large coarse_tune setting */ - clrsetbits_le32(&ch[chn].ao.shu[0].rk[rk].selph_dq[1], + clrsetbits32(&ch[chn].ao.shu[0].rk[rk].selph_dq[1], 0x77777777, dly_large | (dly_large_oen << 16)); - clrsetbits_le32(&ch[chn].ao.shu[0].rk[rk].selph_dq[3], + clrsetbits32(&ch[chn].ao.shu[0].rk[rk].selph_dq[3], 0x77777777, dly_small | (dly_small_oen << 16)); } } @@ -1480,13 +1480,13 @@ static void dramc_set_tx_best_dly_factor(u8 chn, u8 rank_start, u8 type, } for (size_t rank = rank_start; rank < RANK_MAX; rank++) { - clrsetbits_le32(&ch[chn].ao.shu[0].rk[rank].selph_dq[0], + clrsetbits32(&ch[chn].ao.shu[0].rk[rank].selph_dq[0], 0x77777777, dq_large | (dq_large_oen << 16)); - clrsetbits_le32(&ch[chn].ao.shu[0].rk[rank].selph_dq[2], + clrsetbits32(&ch[chn].ao.shu[0].rk[rank].selph_dq[2], 0x77777777, dq_small | (dq_small_oen << 16)); - clrsetbits_le32(&ch[chn].ao.shu[0].rk[rank].selph_dq[1], + clrsetbits32(&ch[chn].ao.shu[0].rk[rank].selph_dq[1], 0x77777777, dqm_large | (dqm_large_oen << 16)); - clrsetbits_le32(&ch[chn].ao.shu[0].rk[rank].selph_dq[3], + clrsetbits32(&ch[chn].ao.shu[0].rk[rank].selph_dq[3], 0x77777777, dqm_small | (dqm_small_oen << 16)); for (size_t byte = 0; byte < 2; byte++) @@ -1503,15 +1503,15 @@ static void dramc_set_tx_best_dly_factor(u8 chn, u8 rank_start, u8 type, if (type != TX_WIN_DQ_ONLY) continue; - clrsetbits_le32(&ch[chn].ao.shu[0].rk[rank].fine_tune, 0x3f3f3f3f, + clrsetbits32(&ch[chn].ao.shu[0].rk[rank].fine_tune, 0x3f3f3f3f, (dqdly_tune[0].fine_tune << 8) | (dqdly_tune[1].fine_tune << 0) | (dqmdly_tune[0].fine_tune << 24) | (dqmdly_tune[1].fine_tune << 16)); - clrsetbits_le32(&ch[chn].ao.shu[0].rk[rank].dqs2dq_cal1, 0x7ff | (0x7ff << 16), + clrsetbits32(&ch[chn].ao.shu[0].rk[rank].dqs2dq_cal1, 0x7ff | (0x7ff << 16), (dqdly_tune[0].fine_tune << 0) | (dqdly_tune[1].fine_tune << 16)); - clrsetbits_le32(&ch[chn].ao.shu[0].rk[rank].dqs2dq_cal2, 0x7ff | (0x7ff << 16), + clrsetbits32(&ch[chn].ao.shu[0].rk[rank].dqs2dq_cal2, 0x7ff | (0x7ff << 16), (dqdly_tune[0].fine_tune << 0) | (dqdly_tune[1].fine_tune << 16)); - clrsetbits_le32(&ch[chn].ao.shu[0].rk[rank].dqs2dq_cal5, 0x7ff | (0x7ff << 16), + clrsetbits32(&ch[chn].ao.shu[0].rk[rank].dqs2dq_cal5, 0x7ff | (0x7ff << 16), (dqmdly_tune[0].fine_tune << 0) | (dqmdly_tune[1].fine_tune << 16)); } } @@ -1525,7 +1525,7 @@ static void dramc_set_rx_best_dly_factor(u8 chn, u8 rank, for (u8 byte = 0; byte < DQS_NUMBER; byte++) { value = (dqsdly_byte[byte] << 24) | (dqsdly_byte[byte] << 16) | (dqmdly_byte[byte] << 8) | (dqmdly_byte[byte] << 0); - clrsetbits_le32(&ch[chn].phy.shu[0].rk[rank].b[byte].dq[6], 0x7f7f3f3f, value); + clrsetbits32(&ch[chn].phy.shu[0].rk[rank].b[byte].dq[6], 0x7f7f3f3f, value); } dram_phy_reset(chn); @@ -1538,7 +1538,7 @@ static void dramc_set_rx_best_dly_factor(u8 chn, u8 rank, (dly[index + 1].best_dqdly << 16) | (dly[index].best_dqdly << 8) | (dly[index].best_dqdly << 0); - clrsetbits_le32(&ch[chn].phy.shu[0].rk[rank].b[byte].dq[dq_num], + clrsetbits32(&ch[chn].phy.shu[0].rk[rank].b[byte].dq[dq_num], 0x3f3f3f3f, value); } } @@ -1817,11 +1817,11 @@ static u8 dramc_window_perbit_cal(u8 chn, u8 rank, u8 freq_group, if (type == TX_WIN_DQ_ONLY || type == TX_WIN_DQ_DQM) { for (size_t byte = 0; byte < 2; byte++) { write32(&ch[chn].phy.shu[0].rk[rank].b[byte].dq[0], 0); - clrbits_le32(&ch[chn].phy.shu[0].rk[rank].b[byte].dq[1], + clrbits32(&ch[chn].phy.shu[0].rk[rank].b[byte].dq[1], 0xf); } - setbits_le32(&ch[chn].phy.misc_ctrl1, 0x1 << 7); - setbits_le32(&ch[chn].ao.dqsoscr, 0x1 << 7); + setbits32(&ch[chn].phy.misc_ctrl1, 0x1 << 7); + setbits32(&ch[chn].ao.dqsoscr, 0x1 << 7); if (fsp == FSP_1) vref_step = 2; } @@ -2070,7 +2070,7 @@ static void dramc_rx_dqs_gating_post_process(u8 chn, u8 freq_group) dqs, best_coarse_tune2t_p1[rank][dqs]); } - clrsetbits_le32(&ch[chn].ao.shu[0].rk[rank].selph_dqsg0, + clrsetbits32(&ch[chn].ao.shu[0].rk[rank].selph_dqsg0, 0x77777777, (best_coarse_tune2t[rank][0] << 0) | (best_coarse_tune2t[rank][1] << 8) | @@ -2085,13 +2085,13 @@ static void dramc_rx_dqs_gating_post_process(u8 chn, u8 freq_group) SET32_BITFIELDS(&ch[chn].ao.shu[0].rk[0].dqsctl, SHURK_DQSCTL_DQSINCTL, read_dqsinctl); SET32_BITFIELDS(&ch[chn].ao.shu[0].rk[1].dqsctl, SHURK_DQSCTL_DQSINCTL, read_dqsinctl); - clrsetbits_le32(&ch[chn].ao.shu[0].rankctl, + clrsetbits32(&ch[chn].ao.shu[0].rankctl, (0xf << 28) | (0xf << 20) | (0xf << 24) | 0xf, (read_dqsinctl << 28) | (rankinctl_root << 20) | (rankinctl_root << 24) | rankinctl_root); u8 ROEN = read32(&ch[chn].ao.shu[0].odtctrl) & 0x1; - clrsetbits_le32(&ch[chn].ao.shu[0].rodtenstb, (0xffff << 8) | (0x3f << 2) | (0x1), + clrsetbits32(&ch[chn].ao.shu[0].rodtenstb, (0xffff << 8) | (0x3f << 2) | (0x1), (0xff << 8) | (0x9 << 2) | ROEN); } diff --git a/src/soc/mediatek/mt8183/dsi.c b/src/soc/mediatek/mt8183/dsi.c index 604592f5cb..7f5ac0a747 100644 --- a/src/soc/mediatek/mt8183/dsi.c +++ b/src/soc/mediatek/mt8183/dsi.c @@ -49,19 +49,19 @@ void mtk_dsi_configure_mipi_tx(int data_rate, u32 lanes) txdiv1 = 0; } - clrbits_le32(&mipi_tx->pll_con4, BIT(11) | BIT(10)); - setbits_le32(&mipi_tx->pll_pwr, AD_DSI_PLL_SDM_PWR_ON); + clrbits32(&mipi_tx->pll_con4, BIT(11) | BIT(10)); + setbits32(&mipi_tx->pll_pwr, AD_DSI_PLL_SDM_PWR_ON); udelay(30); - clrbits_le32(&mipi_tx->pll_pwr, AD_DSI_PLL_SDM_ISO_EN); + clrbits32(&mipi_tx->pll_pwr, AD_DSI_PLL_SDM_ISO_EN); pcw = (u64)data_rate * (1 << txdiv0) * (1 << txdiv1); pcw <<= 24; pcw /= CLK26M_HZ / MHz; write32(&mipi_tx->pll_con0, pcw); - clrsetbits_le32(&mipi_tx->pll_con1, RG_DSI_PLL_POSDIV, txdiv0 << 8); + clrsetbits32(&mipi_tx->pll_con1, RG_DSI_PLL_POSDIV, txdiv0 << 8); udelay(30); - setbits_le32(&mipi_tx->pll_con1, RG_DSI_PLL_EN); + setbits32(&mipi_tx->pll_con1, RG_DSI_PLL_EN); /* BG_LPF_EN / BG_CORE_EN */ write32(&mipi_tx->lane_con, 0x3fff0180); @@ -69,13 +69,13 @@ void mtk_dsi_configure_mipi_tx(int data_rate, u32 lanes) write32(&mipi_tx->lane_con, 0x3fff00c0); /* Switch OFF each Lane */ - clrbits_le32(&mipi_tx->d0_sw_ctl_en, DSI_SW_CTL_EN); - clrbits_le32(&mipi_tx->d1_sw_ctl_en, DSI_SW_CTL_EN); - clrbits_le32(&mipi_tx->d2_sw_ctl_en, DSI_SW_CTL_EN); - clrbits_le32(&mipi_tx->d3_sw_ctl_en, DSI_SW_CTL_EN); - clrbits_le32(&mipi_tx->ck_sw_ctl_en, DSI_SW_CTL_EN); + clrbits32(&mipi_tx->d0_sw_ctl_en, DSI_SW_CTL_EN); + clrbits32(&mipi_tx->d1_sw_ctl_en, DSI_SW_CTL_EN); + clrbits32(&mipi_tx->d2_sw_ctl_en, DSI_SW_CTL_EN); + clrbits32(&mipi_tx->d3_sw_ctl_en, DSI_SW_CTL_EN); + clrbits32(&mipi_tx->ck_sw_ctl_en, DSI_SW_CTL_EN); - setbits_le32(&mipi_tx->ck_ckmode_en, DSI_CK_CKMODE_EN); + setbits32(&mipi_tx->ck_ckmode_en, DSI_CK_CKMODE_EN); } void mtk_dsi_reset(void) diff --git a/src/soc/mediatek/mt8183/emi.c b/src/soc/mediatek/mt8183/emi.c index 7cd631ca0b..cf104f8485 100644 --- a/src/soc/mediatek/mt8183/emi.c +++ b/src/soc/mediatek/mt8183/emi.c @@ -157,7 +157,7 @@ size_t sdram_size(void) static void set_rank_info_to_conf(const struct sdram_params *params) { bool is_dual_rank = (params->emi_cona_val & (0x1 << 17)) != 0; - clrsetbits_le32(&ch[0].ao.rstmask, 0x1 << 12, + clrsetbits32(&ch[0].ao.rstmask, 0x1 << 12, (is_dual_rank ? 0 : 1) << 12); } @@ -297,8 +297,8 @@ static void emi_init2(const struct sdram_params *params) { emi_esl_setting2(); - setbits_le32(&emi_mpu->mpu_ctrl_d[1], 0x1 << 4); - setbits_le32(&emi_mpu->mpu_ctrl_d[7], 0x1 << 4); + setbits32(&emi_mpu->mpu_ctrl_d[1], 0x1 << 4); + setbits32(&emi_mpu->mpu_ctrl_d[7], 0x1 << 4); write32(&emi_regs->bwct0, 0x0a000705); write32(&emi_regs->bwct0_3rd, 0x0); @@ -311,14 +311,14 @@ static void emi_init2(const struct sdram_params *params) static void dramc_init_pre_settings(void) { - clrsetbits_le32(&ch[0].phy.ca_cmd[8], + clrsetbits32(&ch[0].phy.ca_cmd[8], (0x1 << 21) | (0x1 << 20) | (0x1 << 19) | (0x1 << 18) | (0x1f << 8) | (0x1f << 0), (0x1 << 19) | (0xa << 8) | (0xa << 0)); - setbits_le32(&ch[0].phy.misc_ctrl1, 0x1 << 12); - clrbits_le32(&ch[0].phy.misc_ctrl1, 0x1 << 13); - setbits_le32(&ch[0].phy.misc_ctrl1, 0x1 << 31); + setbits32(&ch[0].phy.misc_ctrl1, 0x1 << 12); + clrbits32(&ch[0].phy.misc_ctrl1, 0x1 << 13); + setbits32(&ch[0].phy.misc_ctrl1, 0x1 << 31); } static void dramc_ac_timing_optimize(u8 freq_group) @@ -331,20 +331,20 @@ static void dramc_ac_timing_optimize(u8 freq_group) }; for (size_t chn = 0; chn < CHANNEL_MAX; chn++) { - clrsetbits_le32(&ch[chn].ao.shu[0].actim[3], + clrsetbits32(&ch[chn].ao.shu[0].actim[3], 0xff << 16, rf_cab_opt[freq_group].rfc << 16); - clrbits_le32(&ch[chn].ao.shu[0].ac_time_05t, + clrbits32(&ch[chn].ao.shu[0].ac_time_05t, rf_cab_opt[freq_group].rfc_05t << 2); - clrsetbits_le32(&ch[chn].ao.shu[0].actim[4], + clrsetbits32(&ch[chn].ao.shu[0].actim[4], 0x3ff << 0, rf_cab_opt[freq_group].tx_ref_cnt << 0); } } static void spm_pinmux_setting(void) { - clrsetbits_le32(&mtk_spm->poweron_config_set, + clrsetbits32(&mtk_spm->poweron_config_set, (0xffff << 16) | (0x1 << 0), (0xb16 << 16) | (0x1 << 0)); - clrbits_le32(&mtk_spm->pcm_pwr_io_en, (0xff << 0) | (0xff << 16)); + clrbits32(&mtk_spm->pcm_pwr_io_en, (0xff << 0) | (0xff << 16)); write32(&mtk_spm->dramc_dpy_clk_sw_con_sel, 0xffffffff); write32(&mtk_spm->dramc_dpy_clk_sw_con_sel2, 0xffffffff); } @@ -377,11 +377,11 @@ static void init_dram(const struct sdram_params *params, u8 freq_group, void enable_emi_dcm(void) { - clrbits_le32(&emi_regs->conm, 0xff << 24); - clrbits_le32(&emi_regs->conn, 0xff << 24); + clrbits32(&emi_regs->conm, 0xff << 24); + clrbits32(&emi_regs->conn, 0xff << 24); for (size_t chn = 0; chn < CHANNEL_MAX; chn++) - clrbits_le32(&ch[chn].emi.chn_conb, 0xff << 24); + clrbits32(&ch[chn].emi.chn_conb, 0xff << 24); } struct shuffle_reg_addr { @@ -456,18 +456,18 @@ static void dramc_save_result_to_shuffle(u32 src_shuffle, u32 dst_shuffle) value = read32(src_addr) & 0x7f; if (dst_shuffle == DRAM_DFS_SHUFFLE_2) - clrsetbits_le32(dst_addr, 0x7f << 0x8, value << 0x8); + clrsetbits32(dst_addr, 0x7f << 0x8, value << 0x8); else if (dst_shuffle == DRAM_DFS_SHUFFLE_3) - clrsetbits_le32(dst_addr, 0x7f << 0x16, value << 0x16); + clrsetbits32(dst_addr, 0x7f << 0x16, value << 0x16); /* DRAMC-exception-2 */ src_addr = (u8 *)&ch[chn].ao.dvfsdll; value = (read32(src_addr) >> 1) & 0x1; if (dst_shuffle == DRAM_DFS_SHUFFLE_2) - clrsetbits_le32(src_addr, 0x1 << 2, value << 2); + clrsetbits32(src_addr, 0x1 << 2, value << 2); else if (dst_shuffle == DRAM_DFS_SHUFFLE_3) - clrsetbits_le32(src_addr, 0x1 << 3, value << 3); + clrsetbits32(src_addr, 0x1 << 3, value << 3); /* PHY */ for (index = 0; index < ARRAY_SIZE(phy_regs); index++) { diff --git a/src/soc/mediatek/mt8183/gpio.c b/src/soc/mediatek/mt8183/gpio.c index 3eccfbd50d..0664678dd9 100644 --- a/src/soc/mediatek/mt8183/gpio.c +++ b/src/soc/mediatek/mt8183/gpio.c @@ -34,15 +34,15 @@ static void gpio_set_pull_pupd(gpio_t gpio, enum pull_enable enable, if (enable == GPIO_PULL_ENABLE) { if (select == GPIO_PULL_DOWN) - setbits_le32(reg, 1 << (bit + 2)); + setbits32(reg, 1 << (bit + 2)); else - clrbits_le32(reg, 1 << (bit + 2)); + clrbits32(reg, 1 << (bit + 2)); } if (enable == GPIO_PULL_ENABLE) - clrsetbits_le32(reg, 3 << bit, 1 << bit); + clrsetbits32(reg, 3 << bit, 1 << bit); else - clrbits_le32(reg, 3 << bit); + clrbits32(reg, 3 << bit); } static void gpio_set_pull_en_sel(gpio_t gpio, enum pull_enable enable, @@ -53,15 +53,15 @@ static void gpio_set_pull_en_sel(gpio_t gpio, enum pull_enable enable, if (enable == GPIO_PULL_ENABLE) { if (select == GPIO_PULL_DOWN) - clrbits_le32(reg + SEL_OFFSET, 1 << bit); + clrbits32(reg + SEL_OFFSET, 1 << bit); else - setbits_le32(reg + SEL_OFFSET, 1 << bit); + setbits32(reg + SEL_OFFSET, 1 << bit); } if (enable == GPIO_PULL_ENABLE) - setbits_le32(reg + EN_OFFSET, 1 << bit); + setbits32(reg + EN_OFFSET, 1 << bit); else - clrbits_le32(reg + EN_OFFSET, 1 << bit); + clrbits32(reg + EN_OFFSET, 1 << bit); } void gpio_set_pull(gpio_t gpio, enum pull_enable enable, @@ -112,23 +112,23 @@ enum { void gpio_set_i2c_eh_rsel(void) { - clrsetbits_le32((void *)IOCFG_RB_BASE + EH_RSEL_OFFSET, + clrsetbits32((void *)IOCFG_RB_BASE + EH_RSEL_OFFSET, I2C_EH_RSL_MASK(SCL0) | I2C_EH_RSL_MASK(SDA0) | I2C_EH_RSL_MASK(SCL1) | I2C_EH_RSL_MASK(SDA1), I2C_EH_RSL_VAL(SCL0) | I2C_EH_RSL_VAL(SDA0) | I2C_EH_RSL_VAL(SCL1) | I2C_EH_RSL_VAL(SDA1)); - clrsetbits_le32((void *)IOCFG_RM_BASE + EH_RSEL_OFFSET, + clrsetbits32((void *)IOCFG_RM_BASE + EH_RSEL_OFFSET, I2C_EH_RSL_MASK(SCL2) | I2C_EH_RSL_MASK(SDA2) | I2C_EH_RSL_MASK(SCL4) | I2C_EH_RSL_MASK(SDA4), I2C_EH_RSL_VAL(SCL2) | I2C_EH_RSL_VAL(SDA2) | I2C_EH_RSL_VAL(SCL4) | I2C_EH_RSL_VAL(SDA4)); - clrsetbits_le32((void *)IOCFG_BL_BASE + EH_RSEL_OFFSET, + clrsetbits32((void *)IOCFG_BL_BASE + EH_RSEL_OFFSET, I2C_EH_RSL_MASK(SCL3) | I2C_EH_RSL_MASK(SDA3), I2C_EH_RSL_VAL(SCL3) | I2C_EH_RSL_VAL(SDA3)); - clrsetbits_le32((void *)IOCFG_LB_BASE + EH_RSEL_OFFSET, + clrsetbits32((void *)IOCFG_LB_BASE + EH_RSEL_OFFSET, I2C_EH_RSL_MASK(SCL5) | I2C_EH_RSL_MASK(SDA5), I2C_EH_RSL_VAL(SCL5) | I2C_EH_RSL_VAL(SDA5)); } @@ -153,17 +153,17 @@ void gpio_set_spi_driving(unsigned int bus, enum spi_pad_mask pad_select, reg = (void *)(IOCFG_LM_BASE + GPIO_DRV0_OFFSET); offset = 0; } else if (pad_select == SPI_PAD1_MASK) { - clrsetbits_le32((void *)IOCFG_RM_BASE + + clrsetbits32((void *)IOCFG_RM_BASE + GPIO_DRV0_OFFSET, 0xf | 0xf << 20, reg_val | reg_val << 20); - clrsetbits_le32((void *)IOCFG_RM_BASE + + clrsetbits32((void *)IOCFG_RM_BASE + GPIO_DRV1_OFFSET, 0xf << 16, reg_val << 16); return; } break; case 2: - clrsetbits_le32((void *)IOCFG_RM_BASE + GPIO_DRV0_OFFSET, + clrsetbits32((void *)IOCFG_RM_BASE + GPIO_DRV0_OFFSET, 0xf << 8 | 0xf << 12, reg_val << 8 | reg_val << 12); return; @@ -181,5 +181,5 @@ void gpio_set_spi_driving(unsigned int bus, enum spi_pad_mask pad_select, break; } - clrsetbits_le32(reg, 0xf << offset, reg_val << offset); + clrsetbits32(reg, 0xf << offset, reg_val << offset); } diff --git a/src/soc/mediatek/mt8183/md_ctrl.c b/src/soc/mediatek/mt8183/md_ctrl.c index aa97756db2..a1405dd0e7 100644 --- a/src/soc/mediatek/mt8183/md_ctrl.c +++ b/src/soc/mediatek/mt8183/md_ctrl.c @@ -24,10 +24,10 @@ static void internal_md_power_down(void) { /* Gating MD clock */ - setbits_le32(&mtk_topckgen->clk_mode, + setbits32(&mtk_topckgen->clk_mode, TOPCKGEN_CLK_MODE_MD_32K | TOPCKGEN_CLK_MODE_MD_26M); /* Release SRCCLKENA */ - clrbits_le32(&mt8183_infracfg->infra_misc2, + clrbits32(&mt8183_infracfg->infra_misc2, INFRA_MISC2_SRCCLKENA_RELEASE); } diff --git a/src/soc/mediatek/mt8183/pll.c b/src/soc/mediatek/mt8183/pll.c index 5368077318..ff61303337 100644 --- a/src/soc/mediatek/mt8183/pll.c +++ b/src/soc/mediatek/mt8183/pll.c @@ -282,7 +282,7 @@ static const struct rate rates[] = { void pll_set_pcw_change(const struct pll *pll) { - setbits_le32(pll->div_reg, PLL_PCW_CHG); + setbits32(pll->div_reg, PLL_PCW_CHG); } void mt_pll_init(void) @@ -290,20 +290,20 @@ void mt_pll_init(void) int i; /* enable univpll & mainpll div */ - setbits_le32(&mtk_apmixed->ap_pll_con2, 0x1FFE << 16); + setbits32(&mtk_apmixed->ap_pll_con2, 0x1FFE << 16); /* enable clock square1 low-pass filter */ - setbits_le32(&mtk_apmixed->ap_pll_con0, 0x2); + setbits32(&mtk_apmixed->ap_pll_con0, 0x2); /* xPLL PWR ON */ for (i = 0; i < APMIXED_PLL_MAX; i++) - setbits_le32(plls[i].pwr_reg, PLL_PWR_ON); + setbits32(plls[i].pwr_reg, PLL_PWR_ON); udelay(PLL_PWR_ON_DELAY); /* xPLL ISO Disable */ for (i = 0; i < APMIXED_PLL_MAX; i++) - clrbits_le32(plls[i].pwr_reg, PLL_ISO); + clrbits32(plls[i].pwr_reg, PLL_ISO); udelay(PLL_ISO_DELAY); @@ -319,7 +319,7 @@ void mt_pll_init(void) /* xPLL Frequency Enable */ for (i = 0; i < APMIXED_PLL_MAX; i++) - setbits_le32(plls[i].reg, PLL_EN); + setbits32(plls[i].reg, PLL_EN); /* wait for PLL stable */ udelay(PLL_EN_DELAY); @@ -327,32 +327,32 @@ void mt_pll_init(void) /* xPLL DIV RSTB */ for (i = 0; i < APMIXED_PLL_MAX; i++) { if (plls[i].rstb_shift != NO_RSTB_SHIFT) - setbits_le32(plls[i].reg, 1 << plls[i].rstb_shift); + setbits32(plls[i].reg, 1 << plls[i].rstb_shift); } /* MCUCFG CLKMUX */ - clrsetbits_le32(&mt8183_mcucfg->mp0_pll_divider_cfg, DIV_MASK, DIV_1); - clrsetbits_le32(&mt8183_mcucfg->mp2_pll_divider_cfg, DIV_MASK, DIV_1); - clrsetbits_le32(&mt8183_mcucfg->bus_pll_divider_cfg, DIV_MASK, DIV_2); + clrsetbits32(&mt8183_mcucfg->mp0_pll_divider_cfg, DIV_MASK, DIV_1); + clrsetbits32(&mt8183_mcucfg->mp2_pll_divider_cfg, DIV_MASK, DIV_1); + clrsetbits32(&mt8183_mcucfg->bus_pll_divider_cfg, DIV_MASK, DIV_2); - clrsetbits_le32(&mt8183_mcucfg->mp0_pll_divider_cfg, MUX_MASK, + clrsetbits32(&mt8183_mcucfg->mp0_pll_divider_cfg, MUX_MASK, MUX_SRC_ARMPLL); - clrsetbits_le32(&mt8183_mcucfg->mp2_pll_divider_cfg, MUX_MASK, + clrsetbits32(&mt8183_mcucfg->mp2_pll_divider_cfg, MUX_MASK, MUX_SRC_ARMPLL); - clrsetbits_le32(&mt8183_mcucfg->bus_pll_divider_cfg, MUX_MASK, + clrsetbits32(&mt8183_mcucfg->bus_pll_divider_cfg, MUX_MASK, MUX_SRC_ARMPLL); /* enable infrasys DCM */ - setbits_le32(&mt8183_infracfg->infra_bus_dcm_ctrl, 0x3 << 21); - clrsetbits_le32(&mt8183_infracfg->infra_bus_dcm_ctrl, + setbits32(&mt8183_infracfg->infra_bus_dcm_ctrl, 0x3 << 21); + clrsetbits32(&mt8183_infracfg->infra_bus_dcm_ctrl, DCM_INFRA_BUS_MASK, DCM_INFRA_BUS_ON); - setbits_le32(&mt8183_infracfg->mem_dcm_ctrl, DCM_INFRA_MEM_ON); - clrbits_le32(&mt8183_infracfg->p2p_rx_clk_on, DCM_INFRA_P2PRX_MASK); - clrsetbits_le32(&mt8183_infracfg->peri_bus_dcm_ctrl, + setbits32(&mt8183_infracfg->mem_dcm_ctrl, DCM_INFRA_MEM_ON); + clrbits32(&mt8183_infracfg->p2p_rx_clk_on, DCM_INFRA_P2PRX_MASK); + clrsetbits32(&mt8183_infracfg->peri_bus_dcm_ctrl, DCM_INFRA_PERI_MASK, DCM_INFRA_PERI_ON); /* enable [11] for change i2c module source clock to TOPCKGEN */ - setbits_le32(&mt8183_infracfg->module_clk_sel, 0x1 << 11); + setbits32(&mt8183_infracfg->module_clk_sel, 0x1 << 11); /* * TOP CLKMUX -- DO NOT CHANGE WITHOUT ADJUSTING CONSTANTS! @@ -361,19 +361,19 @@ void mt_pll_init(void) mux_set_sel(&muxes[mux_sels[i].id], mux_sels[i].sel); /* enable [14] dramc_pll104m_ck */ - setbits_le32(&mtk_topckgen->clk_misc_cfg_0, 1 << 14); + setbits32(&mtk_topckgen->clk_misc_cfg_0, 1 << 14); /* enable audio clock */ - setbits_le32(&mtk_topckgen->clk_cfg_5_clr, 1 << 7); + setbits32(&mtk_topckgen->clk_cfg_5_clr, 1 << 7); /* enable intbus clock */ - setbits_le32(&mtk_topckgen->clk_cfg_5_clr, 1 << 15); + setbits32(&mtk_topckgen->clk_cfg_5_clr, 1 << 15); /* enable infra clock */ - setbits_le32(&mt8183_infracfg->module_sw_cg_1_clr, 1 << 25); + setbits32(&mt8183_infracfg->module_sw_cg_1_clr, 1 << 25); /* enable mtkaif 26m clock */ - setbits_le32(&mt8183_infracfg->module_sw_cg_2_clr, 1 << 4); + setbits32(&mt8183_infracfg->module_sw_cg_2_clr, 1 << 4); } void mt_pll_raise_ca53_freq(u32 freq) diff --git a/src/soc/mediatek/mt8183/spi.c b/src/soc/mediatek/mt8183/spi.c index 7672db7993..c77d7ef7d3 100644 --- a/src/soc/mediatek/mt8183/spi.c +++ b/src/soc/mediatek/mt8183/spi.c @@ -127,10 +127,10 @@ void mtk_spi_set_timing(struct mtk_spi_regs *regs, u32 sck_ticks, u32 cs_ticks, ((sck_ticks - 1) << SPI_CFG2_SCK_HIGH_SHIFT) | ((sck_ticks - 1) << SPI_CFG2_SCK_LOW_SHIFT)); - clrsetbits_le32(®s->spi_cfg1_reg, SPI_CFG1_TICK_DLY_MASK | - SPI_CFG1_CS_IDLE_MASK, - (tick_dly << SPI_CFG1_TICK_DLY_SHIFT) | - ((cs_ticks - 1) << SPI_CFG1_CS_IDLE_SHIFT)); + clrsetbits32(®s->spi_cfg1_reg, SPI_CFG1_TICK_DLY_MASK | + SPI_CFG1_CS_IDLE_MASK, + (tick_dly << SPI_CFG1_TICK_DLY_SHIFT) | + ((cs_ticks - 1) << SPI_CFG1_CS_IDLE_SHIFT)); } const struct spi_ctrlr_buses spi_ctrlr_bus_map[] = { diff --git a/src/soc/mediatek/mt8183/spm.c b/src/soc/mediatek/mt8183/spm.c index 9a08782953..024fe1c9fc 100644 --- a/src/soc/mediatek/mt8183/spm.c +++ b/src/soc/mediatek/mt8183/spm.c @@ -77,16 +77,16 @@ static int spm_register_init(void) MD_DDR_EN_1_DBC_LEN | CONN_DDR_EN_DBC_LEN); - clrsetbits_le32(&mtk_spm->spare_ack_mask, - SPARE_ACK_MASK_B_BIT1, - SPARE_ACK_MASK_B_BIT0); + clrsetbits32(&mtk_spm->spare_ack_mask, + SPARE_ACK_MASK_B_BIT1, + SPARE_ACK_MASK_B_BIT0); write32(&mtk_spm->sysrom_con, IFR_SRAMROM_ROM_PDN); write32(&mtk_spm->spm_pc_trace_con, SPM_PC_TRACE_OFFSET | SPM_PC_TRACE_HW_EN_LSB); - setbits_le32(&mtk_spm->spare_src_req_mask, SPARE1_DDREN_MASK_B_LSB); + setbits32(&mtk_spm->spare_src_req_mask, SPARE1_DDREN_MASK_B_LSB); return 0; } @@ -131,9 +131,9 @@ static int spm_reset_and_init_pcm(const struct pcm_desc *pcmdesc) write32(&mtk_spm->pcm_pwr_io_en, 0); - clrsetbits_le32(&mtk_spm->pcm_con1, - PCM_TIMER_EN_LSB, - SPM_REGWR_CFG_KEY); + clrsetbits32(&mtk_spm->pcm_con1, + PCM_TIMER_EN_LSB, + SPM_REGWR_CFG_KEY); write32(&mtk_spm->pcm_con0, SPM_REGWR_CFG_KEY | PCM_CK_EN_LSB | PCM_SW_RESET_LSB); diff --git a/src/soc/mediatek/mt8183/sspm.c b/src/soc/mediatek/mt8183/sspm.c index 559034eacb..857d3dc56d 100644 --- a/src/soc/mediatek/mt8183/sspm.c +++ b/src/soc/mediatek/mt8183/sspm.c @@ -16,7 +16,7 @@ #include #include #include -#include +#include #include #include diff --git a/src/soc/nvidia/tegra/usb.c b/src/soc/nvidia/tegra/usb.c index 55d80ed567..2b450c5672 100644 --- a/src/soc/nvidia/tegra/usb.c +++ b/src/soc/nvidia/tegra/usb.c @@ -149,7 +149,7 @@ void usb_setup_utmip(void *usb_base) int khz = clock_get_pll_input_khz(); /* Stop UTMI+ crystal clock while we mess with its settings */ - clrbits_le32(&usb->utmip.misc1, 1 << 30); /* PHY_XTAL_CLKEN */ + clrbits32(&usb->utmip.misc1, 1 << 30); /* PHY_XTAL_CLKEN */ udelay(1); /* Take stuff out of pwrdn and add some magic numbers from U-Boot */ @@ -203,7 +203,7 @@ void usb_setup_utmip(void *usb_base) 25 * khz / 10 << 0); /* TODO: what's this, really? */ udelay(1); - setbits_le32(&usb->utmip.misc1, 1 << 30); /* PHY_XTAL_CLKEN */ + setbits32(&usb->utmip.misc1, 1 << 30); /* PHY_XTAL_CLKEN */ write32(&usb->suspend_ctrl, 1 << 12 | /* UTMI+ enable */ diff --git a/src/soc/nvidia/tegra124/clock.c b/src/soc/nvidia/tegra124/clock.c index bb0343d432..46ac4aca5d 100644 --- a/src/soc/nvidia/tegra124/clock.c +++ b/src/soc/nvidia/tegra124/clock.c @@ -203,13 +203,13 @@ void sor_clock_stop(void) * FIXME: this has to be cleaned up a bit more. * Waiting on some new info from Nvidia. */ - clrbits_le32(&clk_rst->clk_src_sor, SOR0_CLK_SEL0 | SOR0_CLK_SEL1); + clrbits32(&clk_rst->clk_src_sor, SOR0_CLK_SEL0 | SOR0_CLK_SEL1); } void sor_clock_start(void) { /* uses PLLP, has a non-standard bit layout. */ - setbits_le32(&clk_rst->clk_src_sor, SOR0_CLK_SEL0); + setbits32(&clk_rst->clk_src_sor, SOR0_CLK_SEL0); } static void init_pll(u32 *base, u32 *misc, const union pll_fields pll, u32 lock) @@ -240,7 +240,7 @@ static void init_utmip_pll(void) int khz = clock_get_pll_input_khz(); /* Shut off PLL crystal clock while we mess with it */ - clrbits_le32(&clk_rst->utmip_pll_cfg2, 1 << 30); /* PHY_XTAL_CLKEN */ + clrbits32(&clk_rst->utmip_pll_cfg2, 1 << 30); /* PHY_XTAL_CLKEN */ udelay(1); write32(&clk_rst->utmip_pll_cfg0, /* 960MHz * 1 / 80 == 12 MHz */ @@ -263,7 +263,7 @@ static void init_utmip_pll(void) 0 << 2 | /* SAMP_B/XHOST pwrdn */ 0 << 0); /* SAMP_A/USBD pwrdn */ - setbits_le32(&clk_rst->utmip_pll_cfg2, 1 << 30); /* PHY_XTAL_CLKEN */ + setbits32(&clk_rst->utmip_pll_cfg2, 1 << 30); /* PHY_XTAL_CLKEN */ } /* Graphics just has to be different. There's a few more bits we @@ -401,9 +401,9 @@ void clock_early_uart(void) { write32(&clk_rst->clk_src_uarta, CLK_M << CLK_SOURCE_SHIFT | CLK_UART_DIV_OVERRIDE | CLK_DIVIDER(TEGRA_CLK_M_KHZ, 1900)); - setbits_le32(&clk_rst->clk_out_enb_l, CLK_L_UARTA); + setbits32(&clk_rst->clk_out_enb_l, CLK_L_UARTA); udelay(2); - clrbits_le32(&clk_rst->rst_dev_l, CLK_L_UARTA); + clrbits32(&clk_rst->rst_dev_l, CLK_L_UARTA); } /* Enable output clock (CLK1~3) for external peripherals. */ @@ -411,13 +411,13 @@ void clock_external_output(int clk_id) { switch (clk_id) { case 1: - setbits_le32(&pmc->clk_out_cntrl, 1 << 2); + setbits32(&pmc->clk_out_cntrl, 1 << 2); break; case 2: - setbits_le32(&pmc->clk_out_cntrl, 1 << 10); + setbits32(&pmc->clk_out_cntrl, 1 << 10); break; case 3: - setbits_le32(&pmc->clk_out_cntrl, 1 << 18); + setbits32(&pmc->clk_out_cntrl, 1 << 18); break; default: printk(BIOS_CRIT, "ERROR: Unknown output clock id %d\n", @@ -461,7 +461,7 @@ void clock_sdram(u32 m, u32 n, u32 p, u32 setup, u32 ph45, u32 ph90, (p << PLL_BASE_DIVP_SHIFT)); write32(&clk_rst->pllm_base, base); - setbits_le32(&clk_rst->pllm_base, PLL_BASE_ENABLE); + setbits32(&clk_rst->pllm_base, PLL_BASE_ENABLE); /* stable_time is required, before we can start to check lock. */ udelay(stable_time); @@ -475,7 +475,7 @@ void clock_sdram(u32 m, u32 n, u32 p, u32 setup, u32 ph45, u32 ph90, udelay(10); /* Put OUT1 out of reset state (start to output). */ - setbits_le32(&clk_rst->pllm_out, PLLM_OUT1_RSTN_RESET_DISABLE); + setbits32(&clk_rst->pllm_out, PLLM_OUT1_RSTN_RESET_DISABLE); /* Enable and start MEM(MC) and EMC. */ clock_enable_clear_reset(0, CLK_H_MEM | CLK_H_EMC, 0, 0, 0, 0); @@ -492,7 +492,7 @@ void clock_cpu0_config(void *entry) write32(evp_cpu_reset, (uintptr_t)&maincpu_setup); /* Set active CPU cluster to G */ - clrbits_le32(&flow->cluster_control, 1); + clrbits32(&flow->cluster_control, 1); // Set up cclk_brst and divider. write32(&clk_rst->cclk_brst_pol, @@ -511,9 +511,9 @@ void clock_cpu0_config(void *entry) write32(&clk_rst->clk_cpu_cmplx_clr, cpu_cmplx_clr); // Enable other CPU related clocks. - setbits_le32(&clk_rst->clk_out_enb_l, CLK_L_CPU); - setbits_le32(&clk_rst->clk_out_enb_v, CLK_V_CPUG); - setbits_le32(&clk_rst->clk_out_enb_v, CLK_V_CPULP); + setbits32(&clk_rst->clk_out_enb_l, CLK_L_CPU); + setbits32(&clk_rst->clk_out_enb_v, CLK_V_CPUG); + setbits32(&clk_rst->clk_out_enb_v, CLK_V_CPULP); } void clock_cpu0_remove_reset(void) @@ -573,7 +573,7 @@ void clock_init(void) SCLK_SOURCE_PLLC_OUT1 << SCLK_RUN_SHIFT); /* Change the oscillator drive strength (from U-Boot -- why?) */ - clrsetbits_le32(&clk_rst->osc_ctrl, OSC_XOFS_MASK, + clrsetbits32(&clk_rst->osc_ctrl, OSC_XOFS_MASK, OSC_DRIVE_STRENGTH << OSC_XOFS_SHIFT); /* @@ -581,11 +581,11 @@ void clock_init(void) * "should update same value in PMC_OSC_EDPD_OVER XOFS * field for warmboot " */ - clrsetbits_le32(&pmc->osc_edpd_over, PMC_OSC_EDPD_OVER_XOFS_MASK, + clrsetbits32(&pmc->osc_edpd_over, PMC_OSC_EDPD_OVER_XOFS_MASK, OSC_DRIVE_STRENGTH << PMC_OSC_EDPD_OVER_XOFS_SHIFT); /* Disable IDDQ for PLLX before we set it up (from U-Boot -- why?) */ - clrbits_le32(&clk_rst->pllx_misc3, PLLX_IDDQ_MASK); + clrbits32(&clk_rst->pllx_misc3, PLLX_IDDQ_MASK); /* Set up PLLP_OUT(1|2|3|4) divisor to generate (9.6|48|102|204)MHz */ write32(&clk_rst->pllp_outa, diff --git a/src/soc/nvidia/tegra124/dma.c b/src/soc/nvidia/tegra124/dma.c index 761bb6bce5..78a8d10e00 100644 --- a/src/soc/nvidia/tegra124/dma.c +++ b/src/soc/nvidia/tegra124/dma.c @@ -82,7 +82,7 @@ struct apb_dma_channel * const dma_claim(void) * Set global enable bit, otherwise register access to channel * DMA registers will not be possible. */ - setbits_le32(&apb_dma->command, APB_COMMAND_GEN); + setbits32(&apb_dma->command, APB_COMMAND_GEN); for (i = 0; i < ARRAY_SIZE(apb_dma_channels); i++) { regs = apb_dma_channels[i].regs; @@ -122,7 +122,7 @@ void dma_release(struct apb_dma_channel * const channel) return; } - clrbits_le32(&apb_dma->command, APB_COMMAND_GEN); + clrbits32(&apb_dma->command, APB_COMMAND_GEN); } int dma_start(struct apb_dma_channel * const channel) @@ -130,7 +130,7 @@ int dma_start(struct apb_dma_channel * const channel) struct apb_dma_channel_regs *regs = channel->regs; /* Set ENB bit for this channel */ - setbits_le32(®s->csr, APB_CSR_ENB); + setbits32(®s->csr, APB_CSR_ENB); return 0; } @@ -140,7 +140,7 @@ int dma_stop(struct apb_dma_channel * const channel) struct apb_dma_channel_regs *regs = channel->regs; /* Clear ENB bit for this channel */ - clrbits_le32(®s->csr, APB_CSR_ENB); + clrbits32(®s->csr, APB_CSR_ENB); return 0; } diff --git a/src/soc/nvidia/tegra124/include/soc/clock.h b/src/soc/nvidia/tegra124/include/soc/clock.h index 00744ce596..f99e786180 100644 --- a/src/soc/nvidia/tegra124/include/soc/clock.h +++ b/src/soc/nvidia/tegra124/include/soc/clock.h @@ -231,8 +231,8 @@ static inline void _clock_set_div(u32 *reg, const char *name, u32 div, printk(BIOS_ERR, "%s clock divisor overflow!", name); hlt(); } - clrsetbits_le32(reg, CLK_SOURCE_MASK | CLK_DIVISOR_MASK, - src << CLK_SOURCE_SHIFT | div); + clrsetbits32(reg, CLK_SOURCE_MASK | CLK_DIVISOR_MASK, + src << CLK_SOURCE_SHIFT | div); } #define clock_configure_irregular_source(device, src, freq, src_id) \ diff --git a/src/soc/nvidia/tegra124/power.c b/src/soc/nvidia/tegra124/power.c index 9f3e355ca4..3f1ee7ee95 100644 --- a/src/soc/nvidia/tegra124/power.c +++ b/src/soc/nvidia/tegra124/power.c @@ -93,12 +93,12 @@ int power_reset_status(void) void ram_repair(void) { // Request RAM repair for cluster 0 - setbits_le32(&flow->ram_repair, RAM_REPAIR_REQ); + setbits32(&flow->ram_repair, RAM_REPAIR_REQ); // Poll for completion while (!(read32(&flow->ram_repair) & RAM_REPAIR_STS)) ; // Request RAM repair for cluster 1 - setbits_le32(&flow->ram_repair_cluster1, RAM_REPAIR_REQ); + setbits32(&flow->ram_repair_cluster1, RAM_REPAIR_REQ); // Poll for completion while (!(read32(&flow->ram_repair_cluster1) & RAM_REPAIR_STS)) ; diff --git a/src/soc/nvidia/tegra124/sdram.c b/src/soc/nvidia/tegra124/sdram.c index 9af116c56b..cf529257a7 100644 --- a/src/soc/nvidia/tegra124/sdram.c +++ b/src/soc/nvidia/tegra124/sdram.c @@ -34,7 +34,7 @@ static void sdram_patch(uintptr_t addr, uint32_t value) static void writebits(uint32_t value, uint32_t *addr, uint32_t mask) { - clrsetbits_le32(addr, mask, (value & mask)); + clrsetbits32(addr, mask, (value & mask)); } /* PMC must be configured before clock-enable and de-reset of MC/EMC. */ @@ -77,17 +77,17 @@ static void sdram_start_clocks(const struct sdram_params *param) static void sdram_deassert_clock_enable_signal(const struct sdram_params *param, struct tegra_pmc_regs *regs) { - clrbits_le32(®s->por_dpd_ctrl, - PMC_POR_DPD_CTRL_MEM0_HOLD_CKE_LOW_OVR_MASK); + clrbits32(®s->por_dpd_ctrl, + PMC_POR_DPD_CTRL_MEM0_HOLD_CKE_LOW_OVR_MASK); udelay(param->PmcPorDpdCtrlWait); } static void sdram_deassert_sel_dpd(const struct sdram_params *param, struct tegra_pmc_regs *regs) { - clrbits_le32(®s->por_dpd_ctrl, - (PMC_POR_DPD_CTRL_MEM0_ADDR0_CLK_SEL_DPD_MASK | - PMC_POR_DPD_CTRL_MEM0_ADDR1_CLK_SEL_DPD_MASK)); + clrbits32(®s->por_dpd_ctrl, + (PMC_POR_DPD_CTRL_MEM0_ADDR0_CLK_SEL_DPD_MASK | + PMC_POR_DPD_CTRL_MEM0_ADDR1_CLK_SEL_DPD_MASK)); /* * Note NVIDIA recommended to always do 10us delay here and ignore * BCT.PmcPorDpdCtrlWait. @@ -439,8 +439,8 @@ static void sdram_set_clock_enable_signal(const struct sdram_params *param, struct tegra_emc_regs *regs) { volatile uint32_t dummy = 0; - clrbits_le32(®s->pin, (EMC_PIN_RESET_MASK | EMC_PIN_DQM_MASK | - EMC_PIN_CKE_MASK)); + clrbits32(®s->pin, (EMC_PIN_RESET_MASK | EMC_PIN_DQM_MASK | + EMC_PIN_CKE_MASK)); /* * Assert dummy read of PIN register to ensure above write to PIN * register went through. 200 is the recommended value by NVIDIA. @@ -449,7 +449,7 @@ static void sdram_set_clock_enable_signal(const struct sdram_params *param, udelay(200 + param->EmcPinExtraWait); /* Deassert reset */ - setbits_le32(®s->pin, EMC_PIN_RESET_INACTIVE); + setbits32(®s->pin, EMC_PIN_RESET_INACTIVE); /* * Assert dummy read of PIN register to ensure above write to PIN * register went through. 200 is the recommended value by NVIDIA. @@ -458,7 +458,7 @@ static void sdram_set_clock_enable_signal(const struct sdram_params *param, udelay(500 + param->EmcPinExtraWait); /* Enable clock enable signal */ - setbits_le32(®s->pin, EMC_PIN_CKE_NORMAL); + setbits32(®s->pin, EMC_PIN_CKE_NORMAL); /* * Assert dummy read of PIN register to ensure above write to PIN * register went through. 200 is the recommended value by NVIDIA. @@ -547,8 +547,8 @@ static void sdram_enable_arbiter(const struct sdram_params *param) { /* TODO(hungte) Move values here to standalone header file. */ uint32_t *AHB_ARBITRATION_XBAR_CTRL = (uint32_t*)(0x6000c000 + 0xe0); - setbits_le32(AHB_ARBITRATION_XBAR_CTRL, - param->AhbArbitrationXbarCtrlMemInitDone << 16); + setbits32(AHB_ARBITRATION_XBAR_CTRL, + param->AhbArbitrationXbarCtrlMemInitDone << 16); } static void sdram_lock_carveouts(const struct sdram_params *param, diff --git a/src/soc/nvidia/tegra124/spi.c b/src/soc/nvidia/tegra124/spi.c index 27ae1faf22..007d189bc9 100644 --- a/src/soc/nvidia/tegra124/spi.c +++ b/src/soc/nvidia/tegra124/spi.c @@ -184,13 +184,13 @@ struct tegra_spi_channel *tegra_spi_init(unsigned int bus) return NULL; /* software drives chip-select, set value to high */ - setbits_le32(&spi->regs->command1, + setbits32(&spi->regs->command1, SPI_CMD1_CS_SW_HW | SPI_CMD1_CS_SW_VAL); /* 8-bit transfers, unpacked mode, most significant bit first */ - clrbits_le32(&spi->regs->command1, + clrbits32(&spi->regs->command1, SPI_CMD1_BIT_LEN_MASK | SPI_CMD1_PACKED); - setbits_le32(&spi->regs->command1, 7 << SPI_CMD1_BIT_LEN_SHIFT); + setbits32(&spi->regs->command1, 7 << SPI_CMD1_BIT_LEN_SHIFT); return spi; } @@ -265,7 +265,7 @@ static void dump_fifo_status(struct tegra_spi_channel *spi) static void clear_fifo_status(struct tegra_spi_channel *spi) { - clrbits_le32(&spi->regs->fifo_status, + clrbits32(&spi->regs->fifo_status, SPI_FIFO_STATUS_ERR | SPI_FIFO_STATUS_TX_FIFO_OVF | SPI_FIFO_STATUS_TX_FIFO_UNR | @@ -372,11 +372,11 @@ static int tegra_spi_pio_prepare(struct tegra_spi_channel *spi, enable_mask = SPI_CMD1_RX_EN; } - setbits_le32(&spi->regs->fifo_status, flush_mask); + setbits32(&spi->regs->fifo_status, flush_mask); while (read32(&spi->regs->fifo_status) & flush_mask) ; - setbits_le32(&spi->regs->command1, enable_mask); + setbits32(&spi->regs->command1, enable_mask); /* BLOCK_SIZE in SPI_DMA_BLK register applies to both DMA and * PIO transfers */ @@ -396,8 +396,8 @@ static int tegra_spi_pio_prepare(struct tegra_spi_channel *spi, static void tegra_spi_pio_start(struct tegra_spi_channel *spi) { - setbits_le32(&spi->regs->trans_status, SPI_STATUS_RDY); - setbits_le32(&spi->regs->command1, SPI_CMD1_GO); + setbits32(&spi->regs->trans_status, SPI_STATUS_RDY); + setbits32(&spi->regs->command1, SPI_CMD1_GO); /* Make sure the write to command1 completes. */ read32(&spi->regs->command1); } @@ -414,7 +414,7 @@ static int tegra_spi_pio_finish(struct tegra_spi_channel *spi) u8 *p = spi->in_buf; struct stopwatch sw; - clrbits_le32(&spi->regs->command1, SPI_CMD1_RX_EN | SPI_CMD1_TX_EN); + clrbits32(&spi->regs->command1, SPI_CMD1_RX_EN | SPI_CMD1_TX_EN); /* * Allow some time in case the Rx FIFO does not yet have @@ -446,19 +446,19 @@ static void setup_dma_params(struct tegra_spi_channel *spi, struct apb_dma_channel *dma) { /* APB bus width = 8-bits, address wrap for each word */ - clrbits_le32(&dma->regs->apb_seq, + clrbits32(&dma->regs->apb_seq, APB_BUS_WIDTH_MASK << APB_BUS_WIDTH_SHIFT); /* AHB 1 word burst, bus width = 32 bits (fixed in hardware), * no address wrapping */ - clrsetbits_le32(&dma->regs->ahb_seq, + clrsetbits32(&dma->regs->ahb_seq, (AHB_BURST_MASK << AHB_BURST_SHIFT), 4 << AHB_BURST_SHIFT); /* Set ONCE mode to transfer one "block" at a time (64KB) and enable * flow control. */ - clrbits_le32(&dma->regs->csr, + clrbits32(&dma->regs->csr, APB_CSR_REQ_SEL_MASK << APB_CSR_REQ_SEL_SHIFT); - setbits_le32(&dma->regs->csr, APB_CSR_ONCE | APB_CSR_FLOW | + setbits32(&dma->regs->csr, APB_CSR_ONCE | APB_CSR_FLOW | (spi->req_sel << APB_CSR_REQ_SEL_SHIFT)); } @@ -493,7 +493,7 @@ static int tegra_spi_dma_prepare(struct tegra_spi_channel *spi, write32(&spi->dma_out->regs->apb_ptr, (u32)&spi->regs->tx_fifo); write32(&spi->dma_out->regs->ahb_ptr, (u32)spi->out_buf); - setbits_le32(&spi->dma_out->regs->csr, APB_CSR_DIR); + setbits32(&spi->dma_out->regs->csr, APB_CSR_DIR); setup_dma_params(spi, spi->dma_out); write32(&spi->dma_out->regs->wcount, wcount); } else { @@ -506,7 +506,7 @@ static int tegra_spi_dma_prepare(struct tegra_spi_channel *spi, write32(&spi->dma_in->regs->apb_ptr, (u32)&spi->regs->rx_fifo); write32(&spi->dma_in->regs->ahb_ptr, (u32)spi->in_buf); - clrbits_le32(&spi->dma_in->regs->csr, APB_CSR_DIR); + clrbits32(&spi->dma_in->regs->csr, APB_CSR_DIR); setup_dma_params(spi, spi->dma_in); write32(&spi->dma_in->regs->wcount, wcount); } @@ -523,12 +523,12 @@ static void tegra_spi_dma_start(struct tegra_spi_channel *spi) * (set bit to clear) between each transaction. Otherwise the next * transaction does not start. */ - setbits_le32(&spi->regs->trans_status, SPI_STATUS_RDY); + setbits32(&spi->regs->trans_status, SPI_STATUS_RDY); if (spi->dma_out) - setbits_le32(&spi->regs->command1, SPI_CMD1_TX_EN); + setbits32(&spi->regs->command1, SPI_CMD1_TX_EN); if (spi->dma_in) - setbits_le32(&spi->regs->command1, SPI_CMD1_RX_EN); + setbits32(&spi->regs->command1, SPI_CMD1_RX_EN); /* * To avoid underrun conditions, enable APB DMA before SPI DMA for @@ -536,7 +536,7 @@ static void tegra_spi_dma_start(struct tegra_spi_channel *spi) */ if (spi->dma_out) dma_start(spi->dma_out); - setbits_le32(&spi->regs->dma_ctl, SPI_DMA_CTL_DMA); + setbits32(&spi->regs->dma_ctl, SPI_DMA_CTL_DMA); if (spi->dma_in) dma_start(spi->dma_in); @@ -555,7 +555,7 @@ static int tegra_spi_dma_finish(struct tegra_spi_channel *spi) dma_busy(spi->dma_in)) ; /* this shouldn't take long, no udelay */ dma_stop(spi->dma_in); - clrbits_le32(&spi->regs->command1, SPI_CMD1_RX_EN); + clrbits32(&spi->regs->command1, SPI_CMD1_RX_EN); dma_release(spi->dma_in); } @@ -566,7 +566,7 @@ static int tegra_spi_dma_finish(struct tegra_spi_channel *spi) dma_busy(spi->dma_out)) { spi_delay(spi, todo - spi_byte_count(spi)); } - clrbits_le32(&spi->regs->command1, SPI_CMD1_TX_EN); + clrbits32(&spi->regs->command1, SPI_CMD1_TX_EN); dma_stop(spi->dma_out); dma_release(spi->dma_out); } diff --git a/src/soc/nvidia/tegra210/addressmap.c b/src/soc/nvidia/tegra210/addressmap.c index 716c900fec..60ca16ca4e 100644 --- a/src/soc/nvidia/tegra210/addressmap.c +++ b/src/soc/nvidia/tegra210/addressmap.c @@ -297,14 +297,14 @@ void gpu_region_init(void) write32(&mc->security_carveout2_bom_hi, 0); /* Set the locked bit. This will lock out any other writes! */ - setbits_le32(&mc->security_carveout2_cfg0, MC_SECURITY_CARVEOUT_LOCKED); + setbits32(&mc->security_carveout2_cfg0, MC_SECURITY_CARVEOUT_LOCKED); /* Set the carveout3 base to 0, unused */ write32(&mc->security_carveout3_bom, 0); write32(&mc->security_carveout3_bom_hi, 0); /* Set the locked bit. This will lock out any other writes! */ - setbits_le32(&mc->security_carveout3_cfg0, MC_SECURITY_CARVEOUT_LOCKED); + setbits32(&mc->security_carveout3_cfg0, MC_SECURITY_CARVEOUT_LOCKED); } void nvdec_region_init(void) @@ -322,7 +322,7 @@ void nvdec_region_init(void) write32(&mc->security_carveout1_bom_hi, 0); /* Set the locked bit. This will lock out any other writes! */ - setbits_le32(&mc->security_carveout1_cfg0, MC_SECURITY_CARVEOUT_LOCKED); + setbits32(&mc->security_carveout1_cfg0, MC_SECURITY_CARVEOUT_LOCKED); } void tsec_region_init(void) @@ -345,8 +345,8 @@ void tsec_region_init(void) write32(&mc->security_carveout5_bom_hi, 0); /* Set the locked bit. This will lock out any other writes! */ - setbits_le32(&mc->security_carveout4_cfg0, MC_SECURITY_CARVEOUT_LOCKED); - setbits_le32(&mc->security_carveout5_cfg0, MC_SECURITY_CARVEOUT_LOCKED); + setbits32(&mc->security_carveout4_cfg0, MC_SECURITY_CARVEOUT_LOCKED); + setbits32(&mc->security_carveout5_cfg0, MC_SECURITY_CARVEOUT_LOCKED); } void vpr_region_init(void) diff --git a/src/soc/nvidia/tegra210/clock.c b/src/soc/nvidia/tegra210/clock.c index 55ee50bcdb..9117654e2a 100644 --- a/src/soc/nvidia/tegra210/clock.c +++ b/src/soc/nvidia/tegra210/clock.c @@ -255,13 +255,13 @@ void sor_clock_stop(void) * FIXME: this has to be cleaned up a bit more. * Waiting on some new info from Nvidia. */ - clrbits_le32(CLK_RST_REG(clk_src_sor), SOR0_CLK_SEL0 | SOR0_CLK_SEL1); + clrbits32(CLK_RST_REG(clk_src_sor), SOR0_CLK_SEL0 | SOR0_CLK_SEL1); } void sor_clock_start(void) { /* uses PLLP, has a non-standard bit layout. */ - setbits_le32(CLK_RST_REG(clk_src_sor), SOR0_CLK_SEL0); + setbits32(CLK_RST_REG(clk_src_sor), SOR0_CLK_SEL0); } static void init_pll(u32 index, u32 osc) @@ -280,13 +280,13 @@ static void init_pll(u32 index, u32 osc) /* Set Lock bit if needed. */ if (pll_reg->lock_enb_val) - setbits_le32(pll_reg->lock_enb_reg, pll_reg->lock_enb_val); + setbits32(pll_reg->lock_enb_reg, pll_reg->lock_enb_val); /* Set KCP/KVCO if needed. */ if (pll_reg->kcp_kvco_reg) - setbits_le32(pll_reg->kcp_kvco_reg, - pll->kcp << pll_reg->kcp_shift | - pll->kvco << pll_reg->kvco_shift); + setbits32(pll_reg->kcp_kvco_reg, + pll->kcp << pll_reg->kcp_shift | + pll->kvco << pll_reg->kvco_shift); /* Enable PLL and take it back out of BYPASS */ write32(pll_reg->base_reg, dividers | PLL_BASE_ENABLE); @@ -300,10 +300,10 @@ static void init_pll(u32 index, u32 osc) static void init_pllc(u32 osc) { /* Clear PLLC reset */ - clrbits_le32(CLK_RST_REG(pllc_misc), PLLC_MISC_RESET); + clrbits32(CLK_RST_REG(pllc_misc), PLLC_MISC_RESET); /* Clear PLLC IDDQ */ - clrbits_le32(CLK_RST_REG(pllc_misc_1), PLLC_MISC_1_IDDQ); + clrbits32(CLK_RST_REG(pllc_misc_1), PLLC_MISC_1_IDDQ); /* Max out the AVP clock before everything else (need PLLC for that). */ init_pll(PLLC_INDEX, osc); @@ -316,7 +316,7 @@ static void init_pllc(u32 osc) static void init_pllu(u32 osc) { /* Clear PLLU IDDQ */ - clrbits_le32(CLK_RST_REG(pllu_misc), PLLU_MISC_IDDQ); + clrbits32(CLK_RST_REG(pllu_misc), PLLU_MISC_IDDQ); /* Wait 5 us */ udelay(5); @@ -508,13 +508,13 @@ void clock_external_output(int clk_id) { switch (clk_id) { case 1: - setbits_le32(&pmc->clk_out_cntrl, 1 << 2); + setbits32(&pmc->clk_out_cntrl, 1 << 2); break; case 2: - setbits_le32(&pmc->clk_out_cntrl, 1 << 10); + setbits32(&pmc->clk_out_cntrl, 1 << 10); break; case 3: - setbits_le32(&pmc->clk_out_cntrl, 1 << 18); + setbits32(&pmc->clk_out_cntrl, 1 << 18); break; default: printk(BIOS_CRIT, "ERROR: Unknown output clock id %d\n", @@ -555,7 +555,7 @@ void clock_sdram(u32 m, u32 n, u32 p, u32 setup, u32 kvco, u32 kcp, (p << PLL_BASE_DIVP_SHIFT)); write32(CLK_RST_REG(pllm_base), base); - setbits_le32(CLK_RST_REG(pllm_base), PLL_BASE_ENABLE); + setbits32(CLK_RST_REG(pllm_base), PLL_BASE_ENABLE); /* stable_time is required, before we can start to check lock. */ udelay(stable_time); @@ -587,8 +587,8 @@ void clock_init(void) { u32 osc = clock_get_osc_bits(); /* clk_m = osc/2 */ - clrsetbits_le32(CLK_RST_REG(spare_reg0), CLK_M_DIVISOR_MASK, - CLK_M_DIVISOR_BY_2); + clrsetbits32(CLK_RST_REG(spare_reg0), CLK_M_DIVISOR_MASK, + CLK_M_DIVISOR_BY_2); /* TIMERUS needs to be adjusted for new 19.2MHz CLK_M rate */ write32((void *)TEGRA_TMRUS_BASE + TIMERUS_USEC_CFG, @@ -608,7 +608,7 @@ void clock_init(void) SCLK_SOURCE_PLLC_OUT1 << SCLK_RUN_SHIFT); /* Change the oscillator drive strength (from U-Boot -- why?) */ - clrsetbits_le32(CLK_RST_REG(osc_ctrl), OSC_XOFS_MASK, + clrsetbits32(CLK_RST_REG(osc_ctrl), OSC_XOFS_MASK, OSC_DRIVE_STRENGTH << OSC_XOFS_SHIFT); /* @@ -616,11 +616,11 @@ void clock_init(void) * "should update same value in PMC_OSC_EDPD_OVER XOFS * field for warmboot " */ - clrsetbits_le32(&pmc->osc_edpd_over, PMC_OSC_EDPD_OVER_XOFS_MASK, - OSC_DRIVE_STRENGTH << PMC_OSC_EDPD_OVER_XOFS_SHIFT); + clrsetbits32(&pmc->osc_edpd_over, PMC_OSC_EDPD_OVER_XOFS_MASK, + OSC_DRIVE_STRENGTH << PMC_OSC_EDPD_OVER_XOFS_SHIFT); /* Disable IDDQ for PLLX before we set it up (from U-Boot -- why?) */ - clrbits_le32(CLK_RST_REG(pllx_misc3), PLLX_IDDQ_MASK); + clrbits32(CLK_RST_REG(pllx_misc3), PLLX_IDDQ_MASK); /* Set up PLLP_OUT(1|2|3|4) divisor to generate (9.6|48|102|204)MHz */ write32(CLK_RST_REG(pllp_outa), diff --git a/src/soc/nvidia/tegra210/cpu.c b/src/soc/nvidia/tegra210/cpu.c index 8d74bd3fb6..4f236c09e3 100644 --- a/src/soc/nvidia/tegra210/cpu.c +++ b/src/soc/nvidia/tegra210/cpu.c @@ -58,7 +58,7 @@ void cpu_prepare_startup(void *entry_64) */ write32(&sb->sb_aa64_reset_low, (uintptr_t)entry_64); - setbits_le32(&sb->sb_aa64_reset_low, 1); + setbits32(&sb->sb_aa64_reset_low, 1); write32(&sb->sb_aa64_reset_high, 0); } diff --git a/src/soc/nvidia/tegra210/dma.c b/src/soc/nvidia/tegra210/dma.c index 75376d98f0..2984abec97 100644 --- a/src/soc/nvidia/tegra210/dma.c +++ b/src/soc/nvidia/tegra210/dma.c @@ -94,7 +94,7 @@ struct apb_dma_channel * const dma_claim(void) * Set global enable bit, otherwise register access to channel * DMA registers will not be possible. */ - setbits_le32(&apb_dma->command, APB_COMMAND_GEN); + setbits32(&apb_dma->command, APB_COMMAND_GEN); for (i = 0; i < ARRAY_SIZE(apb_dma_channels); i++) { regs = apb_dma_channels[i].regs; @@ -134,7 +134,7 @@ void dma_release(struct apb_dma_channel * const channel) return; } - clrbits_le32(&apb_dma->command, APB_COMMAND_GEN); + clrbits32(&apb_dma->command, APB_COMMAND_GEN); } int dma_start(struct apb_dma_channel * const channel) @@ -142,7 +142,7 @@ int dma_start(struct apb_dma_channel * const channel) struct apb_dma_channel_regs *regs = channel->regs; /* Set ENB bit for this channel */ - setbits_le32(®s->csr, APB_CSR_ENB); + setbits32(®s->csr, APB_CSR_ENB); return 0; } @@ -152,7 +152,7 @@ int dma_stop(struct apb_dma_channel * const channel) struct apb_dma_channel_regs *regs = channel->regs; /* Clear ENB bit for this channel */ - clrbits_le32(®s->csr, APB_CSR_ENB); + clrbits32(®s->csr, APB_CSR_ENB); return 0; } diff --git a/src/soc/nvidia/tegra210/include/soc/clock.h b/src/soc/nvidia/tegra210/include/soc/clock.h index 6d8c3386a0..8c4530c027 100644 --- a/src/soc/nvidia/tegra210/include/soc/clock.h +++ b/src/soc/nvidia/tegra210/include/soc/clock.h @@ -320,8 +320,8 @@ static inline void _clock_set_div(u32 *reg, const char *name, u32 div, printk(BIOS_ERR, "%s clock divisor overflow!", name); hlt(); } - clrsetbits_le32(reg, CLK_SOURCE_MASK | CLK_DIVISOR_MASK, - src << CLK_SOURCE_SHIFT | div); + clrsetbits32(reg, CLK_SOURCE_MASK | CLK_DIVISOR_MASK, + src << CLK_SOURCE_SHIFT | div); } #define get_i2c_clk_div(src, freq) \ diff --git a/src/soc/nvidia/tegra210/sdram.c b/src/soc/nvidia/tegra210/sdram.c index e1d91fd0f2..ce615476e6 100644 --- a/src/soc/nvidia/tegra210/sdram.c +++ b/src/soc/nvidia/tegra210/sdram.c @@ -34,7 +34,7 @@ static void sdram_patch(uintptr_t addr, uint32_t value) static void writebits(uint32_t value, uint32_t *addr, uint32_t mask) { - clrsetbits_le32(addr, mask, (value & mask)); + clrsetbits32(addr, mask, (value & mask)); } static void sdram_trigger_emc_timing_update(struct tegra_emc_regs *regs) @@ -82,15 +82,15 @@ static void sdram_start_clocks(const struct sdram_params *param, u32 clk_source_emc = param->EmcClockSource; /* Enable the clocks for EMC and MC */ - setbits_le32(&clk_rst->clk_enb_h_set, (1 << 25)); // ENB_EMC - setbits_le32(&clk_rst->clk_enb_h_set, (1 << 0)); // ENB_MC + setbits32(&clk_rst->clk_enb_h_set, (1 << 25)); // ENB_EMC + setbits32(&clk_rst->clk_enb_h_set, (1 << 0)); // ENB_MC if ((clk_source_emc >> EMC_2X_CLK_SRC_SHIFT) != PLLM_UD) - setbits_le32(&clk_rst->clk_enb_x_set, CLK_ENB_EMC_DLL); + setbits32(&clk_rst->clk_enb_x_set, CLK_ENB_EMC_DLL); /* Remove the EMC and MC controllers from reset */ - clrbits_le32(&clk_rst->rst_dev_h, (1 << 25)); // SWR_EMC - clrbits_le32(&clk_rst->rst_dev_h, (1 << 0)); // SWR_MC + clrbits32(&clk_rst->rst_dev_h, (1 << 25)); // SWR_EMC + clrbits32(&clk_rst->rst_dev_h, (1 << 0)); // SWR_MC clk_source_emc |= (is_same_freq << 16); @@ -818,9 +818,9 @@ static void sdram_set_clock_enable_signal(const struct sdram_params *param, (param->EmcPinGpio << EMC_PIN_GPIO_SHIFT); write32(®s->pin, val); - clrbits_le32(®s->pin, - (EMC_PIN_RESET_MASK | EMC_PIN_DQM_MASK | - EMC_PIN_CKE_MASK)); + clrbits32(®s->pin, + (EMC_PIN_RESET_MASK | EMC_PIN_DQM_MASK | + EMC_PIN_CKE_MASK)); /* * Assert dummy read of PIN register to ensure above write goes * through. Wait an additional 200us here as per NVIDIA. @@ -829,7 +829,7 @@ static void sdram_set_clock_enable_signal(const struct sdram_params *param, udelay(param->EmcPinExtraWait + 200); /* Deassert reset */ - setbits_le32(®s->pin, EMC_PIN_RESET_INACTIVE); + setbits32(®s->pin, EMC_PIN_RESET_INACTIVE); /* * Assert dummy read of PIN register to ensure above write goes @@ -840,7 +840,7 @@ static void sdram_set_clock_enable_signal(const struct sdram_params *param, } /* Enable clock enable signal */ - setbits_le32(®s->pin, EMC_PIN_CKE_NORMAL); + setbits32(®s->pin, EMC_PIN_CKE_NORMAL); /* Dummy read of PIN register to ensure final write goes through */ dummy |= read32(®s->pin); @@ -1005,7 +1005,7 @@ static void sdram_enable_arbiter(const struct sdram_params *param) /* TODO(hungte) Move values here to standalone header file. */ uint32_t *ahb_arbitration_xbar_ctrl = (uint32_t *)(AHB_ARB_XBAR_CTRL); - setbits_le32(ahb_arbitration_xbar_ctrl, + setbits32(ahb_arbitration_xbar_ctrl, param->AhbArbitrationXbarCtrlMemInitDone << 16); } diff --git a/src/soc/nvidia/tegra210/spi.c b/src/soc/nvidia/tegra210/spi.c index 5a065ba199..b0142a4bea 100644 --- a/src/soc/nvidia/tegra210/spi.c +++ b/src/soc/nvidia/tegra210/spi.c @@ -188,13 +188,13 @@ struct tegra_spi_channel *tegra_spi_init(unsigned int bus) return NULL; /* software drives chip-select, set value to high */ - setbits_le32(&spi->regs->command1, + setbits32(&spi->regs->command1, SPI_CMD1_CS_SW_HW | SPI_CMD1_CS_SW_VAL); /* 8-bit transfers, unpacked mode, most significant bit first */ - clrbits_le32(&spi->regs->command1, + clrbits32(&spi->regs->command1, SPI_CMD1_BIT_LEN_MASK | SPI_CMD1_PACKED); - setbits_le32(&spi->regs->command1, 7 << SPI_CMD1_BIT_LEN_SHIFT); + setbits32(&spi->regs->command1, 7 << SPI_CMD1_BIT_LEN_SHIFT); return spi; } @@ -263,7 +263,7 @@ static void dump_fifo_status(struct tegra_spi_channel *spi) static void clear_fifo_status(struct tegra_spi_channel *spi) { - clrbits_le32(&spi->regs->fifo_status, + clrbits32(&spi->regs->fifo_status, SPI_FIFO_STATUS_ERR | SPI_FIFO_STATUS_TX_FIFO_OVF | SPI_FIFO_STATUS_TX_FIFO_UNR | @@ -374,7 +374,7 @@ static int tegra_spi_pio_prepare(struct tegra_spi_channel *spi, */ write32(&spi->regs->dma_blk, todo - 1); - setbits_le32(&spi->regs->command1, enable_mask); + setbits32(&spi->regs->command1, enable_mask); if (dir == SPI_SEND) { unsigned int to_fifo = bytes; @@ -390,7 +390,7 @@ static int tegra_spi_pio_prepare(struct tegra_spi_channel *spi, static void tegra_spi_pio_start(struct tegra_spi_channel *spi) { - setbits_le32(&spi->regs->trans_status, SPI_STATUS_RDY); + setbits32(&spi->regs->trans_status, SPI_STATUS_RDY); /* * Need to stabilize other reg bit before GO bit set. * @@ -403,7 +403,7 @@ static void tegra_spi_pio_start(struct tegra_spi_channel *spi) * enabling pio or dma. */ udelay(2); - setbits_le32(&spi->regs->command1, SPI_CMD1_GO); + setbits32(&spi->regs->command1, SPI_CMD1_GO); /* Need to wait a few cycles before command1 register is read */ udelay(1); /* Make sure the write to command1 completes. */ @@ -421,7 +421,7 @@ static int tegra_spi_pio_finish(struct tegra_spi_channel *spi) { u8 *p = spi->in_buf; - clrbits_le32(&spi->regs->command1, SPI_CMD1_RX_EN | SPI_CMD1_TX_EN); + clrbits32(&spi->regs->command1, SPI_CMD1_RX_EN | SPI_CMD1_TX_EN); ASSERT(rx_fifo_count(spi) == spi_byte_count(spi)); @@ -447,19 +447,19 @@ static void setup_dma_params(struct tegra_spi_channel *spi, struct apb_dma_channel *dma) { /* APB bus width = 8-bits, address wrap for each word */ - clrbits_le32(&dma->regs->apb_seq, + clrbits32(&dma->regs->apb_seq, APB_BUS_WIDTH_MASK << APB_BUS_WIDTH_SHIFT); /* AHB 1 word burst, bus width = 32 bits (fixed in hardware), * no address wrapping */ - clrsetbits_le32(&dma->regs->ahb_seq, + clrsetbits32(&dma->regs->ahb_seq, (AHB_BURST_MASK << AHB_BURST_SHIFT), 4 << AHB_BURST_SHIFT); /* Set ONCE mode to transfer one "block" at a time (64KB) and enable * flow control. */ - clrbits_le32(&dma->regs->csr, + clrbits32(&dma->regs->csr, APB_CSR_REQ_SEL_MASK << APB_CSR_REQ_SEL_SHIFT); - setbits_le32(&dma->regs->csr, APB_CSR_ONCE | APB_CSR_FLOW | + setbits32(&dma->regs->csr, APB_CSR_ONCE | APB_CSR_FLOW | (spi->req_sel << APB_CSR_REQ_SEL_SHIFT)); } @@ -496,7 +496,7 @@ static int tegra_spi_dma_prepare(struct tegra_spi_channel *spi, write32(&spi->dma_out->regs->apb_ptr, (uintptr_t) & spi->regs->tx_fifo); write32(&spi->dma_out->regs->ahb_ptr, (uintptr_t)spi->out_buf); - setbits_le32(&spi->dma_out->regs->csr, APB_CSR_DIR); + setbits32(&spi->dma_out->regs->csr, APB_CSR_DIR); setup_dma_params(spi, spi->dma_out); write32(&spi->dma_out->regs->wcount, wcount); } else { @@ -510,7 +510,7 @@ static int tegra_spi_dma_prepare(struct tegra_spi_channel *spi, write32(&spi->dma_in->regs->apb_ptr, (uintptr_t)&spi->regs->rx_fifo); write32(&spi->dma_in->regs->ahb_ptr, (uintptr_t)spi->in_buf); - clrbits_le32(&spi->dma_in->regs->csr, APB_CSR_DIR); + clrbits32(&spi->dma_in->regs->csr, APB_CSR_DIR); setup_dma_params(spi, spi->dma_in); write32(&spi->dma_in->regs->wcount, wcount); } @@ -527,7 +527,7 @@ static void tegra_spi_dma_start(struct tegra_spi_channel *spi) * (set bit to clear) between each transaction. Otherwise the next * transaction does not start. */ - setbits_le32(&spi->regs->trans_status, SPI_STATUS_RDY); + setbits32(&spi->regs->trans_status, SPI_STATUS_RDY); struct apb_dma * const apb_dma = (struct apb_dma *)TEGRA_APB_DMA_BASE; @@ -539,21 +539,21 @@ static void tegra_spi_dma_start(struct tegra_spi_channel *spi) */ if (spi->dma_out) { /* Enable secure access for the channel. */ - setbits_le32(&apb_dma->security_reg, + setbits32(&apb_dma->security_reg, SECURITY_EN_BIT(spi->dma_out->num)); - clrsetbits_le32(&spi->regs->dma_ctl, + clrsetbits32(&spi->regs->dma_ctl, SPI_DMA_CTL_TX_TRIG_MASK << SPI_DMA_CTL_TX_TRIG_SHIFT, 1 << SPI_DMA_CTL_TX_TRIG_SHIFT); - setbits_le32(&spi->regs->command1, SPI_CMD1_TX_EN); + setbits32(&spi->regs->command1, SPI_CMD1_TX_EN); } if (spi->dma_in) { /* Enable secure access for the channel. */ - setbits_le32(&apb_dma->security_reg, + setbits32(&apb_dma->security_reg, SECURITY_EN_BIT(spi->dma_in->num)); - clrsetbits_le32(&spi->regs->dma_ctl, + clrsetbits32(&spi->regs->dma_ctl, SPI_DMA_CTL_RX_TRIG_MASK << SPI_DMA_CTL_RX_TRIG_SHIFT, 1 << SPI_DMA_CTL_RX_TRIG_SHIFT); - setbits_le32(&spi->regs->command1, SPI_CMD1_RX_EN); + setbits32(&spi->regs->command1, SPI_CMD1_RX_EN); } /* @@ -562,7 +562,7 @@ static void tegra_spi_dma_start(struct tegra_spi_channel *spi) */ if (spi->dma_out) dma_start(spi->dma_out); - setbits_le32(&spi->regs->dma_ctl, SPI_DMA_CTL_DMA); + setbits32(&spi->regs->dma_ctl, SPI_DMA_CTL_DMA); if (spi->dma_in) dma_start(spi->dma_in); @@ -583,9 +583,9 @@ static int tegra_spi_dma_finish(struct tegra_spi_channel *spi) dma_busy(spi->dma_in)) ; dma_stop(spi->dma_in); - clrbits_le32(&spi->regs->command1, SPI_CMD1_RX_EN); + clrbits32(&spi->regs->command1, SPI_CMD1_RX_EN); /* Disable secure access for the channel. */ - clrbits_le32(&apb_dma->security_reg, + clrbits32(&apb_dma->security_reg, SECURITY_EN_BIT(spi->dma_in->num)); dma_release(spi->dma_in); } @@ -596,10 +596,10 @@ static int tegra_spi_dma_finish(struct tegra_spi_channel *spi) while ((read32(&spi->dma_out->regs->dma_byte_sta) < todo) || dma_busy(spi->dma_out)) ; - clrbits_le32(&spi->regs->command1, SPI_CMD1_TX_EN); + clrbits32(&spi->regs->command1, SPI_CMD1_TX_EN); dma_stop(spi->dma_out); /* Disable secure access for the channel. */ - clrbits_le32(&apb_dma->security_reg, + clrbits32(&apb_dma->security_reg, SECURITY_EN_BIT(spi->dma_out->num)); dma_release(spi->dma_out); } diff --git a/src/soc/qualcomm/ipq40xx/blsp.c b/src/soc/qualcomm/ipq40xx/blsp.c index 75618c2461..099dc6e2c1 100644 --- a/src/soc/qualcomm/ipq40xx/blsp.c +++ b/src/soc/qualcomm/ipq40xx/blsp.c @@ -47,7 +47,7 @@ blsp_return_t blsp_i2c_init(blsp_qup_id_t id) return BLSP_UNSUPPORTED; /* Configure Mini core to I2C core */ - clrsetbits_le32(base, BLSP_MINI_CORE_MASK, BLSP_MINI_CORE_I2C); + clrsetbits32(base, BLSP_MINI_CORE_MASK, BLSP_MINI_CORE_I2C); return BLSP_SUCCESS; } diff --git a/src/soc/qualcomm/ipq40xx/clock.c b/src/soc/qualcomm/ipq40xx/clock.c index e3d60e4749..bd1345e4ac 100644 --- a/src/soc/qualcomm/ipq40xx/clock.c +++ b/src/soc/qualcomm/ipq40xx/clock.c @@ -59,7 +59,7 @@ void uart_clock_config(unsigned int blsp_uart, unsigned int m, 2 << 12); /* 13:12 Mode = Dual Edge */ /* Trigger update */ - setbits_le32(GCC_BLSP1_UART_APPS_CMD_RCGR(blsp_uart), 1); + setbits32(GCC_BLSP1_UART_APPS_CMD_RCGR(blsp_uart), 1); /* Wait for update */ for (i = 0; i < CLOCK_UPDATE_DELAY; i++) { @@ -71,7 +71,7 @@ void uart_clock_config(unsigned int blsp_uart, unsigned int m, } /* Please refer to the comments in blsp_i2c_clock_config() */ - setbits_le32(GCC_CLK_BRANCH_ENA, BLSP1_AHB | BLSP1_SLEEP); + setbits32(GCC_CLK_BRANCH_ENA, BLSP1_AHB | BLSP1_SLEEP); } /** @@ -154,7 +154,7 @@ int blsp_i2c_clock_config(blsp_qup_id_t id) * the same bits is harmless. Hence repeating them here should be ok. * This will ensure root and branch clocks remain on. */ - setbits_le32(GCC_CLK_BRANCH_ENA, BLSP1_AHB | BLSP1_SLEEP); + setbits32(GCC_CLK_BRANCH_ENA, BLSP1_AHB | BLSP1_SLEEP); /* Src Sel 1 (fepll 200), Src Div 10.5 */ write32(clk[id].cfg, (1u << 8) | (20u << 0)); diff --git a/src/soc/qualcomm/ipq40xx/include/soc/iomap.h b/src/soc/qualcomm/ipq40xx/include/soc/iomap.h index 930c912ee6..e4b613f7dc 100644 --- a/src/soc/qualcomm/ipq40xx/include/soc/iomap.h +++ b/src/soc/qualcomm/ipq40xx/include/soc/iomap.h @@ -47,8 +47,8 @@ */ #define readl_i(a) read32((const void *)(a)) #define writel_i(v,a) write32((void *)a, v) -#define clrsetbits_le32_i(addr, clear, set) \ - clrsetbits_le32(((void *)(addr)), (clear), (set)) +#define clrsetbits32_i(addr, clear, set) \ + clrsetbits32(((void *)(addr)), (clear), (set)) #define GCC_CLK_CTL_REG ((void *)0x01800000u) #define MSM_CLK_CTL_BASE GCC_CLK_CTL_REG diff --git a/src/soc/qualcomm/ipq40xx/spi.c b/src/soc/qualcomm/ipq40xx/spi.c index b68e1cb864..3b0d63603d 100644 --- a/src/soc/qualcomm/ipq40xx/spi.c +++ b/src/soc/qualcomm/ipq40xx/spi.c @@ -240,7 +240,7 @@ static int spi_hw_init(struct ipq_spi_slave *ds) * Configure Mini core to SPI core with Input Output enabled, * SPI master, N = 8 bits */ - clrsetbits_le32(ds->regs->qup_config, QUP_CONFIG_MINI_CORE_MSK | + clrsetbits32(ds->regs->qup_config, QUP_CONFIG_MINI_CORE_MSK | QUP_CONF_INPUT_MSK | QUP_CONF_OUTPUT_MSK | QUP_CONF_N_MASK, @@ -253,7 +253,7 @@ static int spi_hw_init(struct ipq_spi_slave *ds) * Configure Input first SPI protocol, * SPI master mode and no loopback */ - clrsetbits_le32(ds->regs->spi_config, SPI_CONFIG_LOOP_BACK_MSK | + clrsetbits32(ds->regs->spi_config, SPI_CONFIG_LOOP_BACK_MSK | SPI_CONFIG_NO_SLAVE_OPER_MSK, SPI_CONFIG_NO_LOOP_BACK | SPI_CONFIG_NO_SLAVE_OPER); @@ -273,7 +273,7 @@ static int spi_hw_init(struct ipq_spi_slave *ds) * INPUT_MODE = Block Mode * OUTPUT MODE = Block Mode */ - clrsetbits_le32(ds->regs->qup_io_modes, + clrsetbits32(ds->regs->qup_io_modes, QUP_IO_MODES_OUTPUT_BIT_SHIFT_MSK | QUP_IO_MODES_INPUT_MODE_MSK | QUP_IO_MODES_OUTPUT_MODE_MSK, @@ -320,10 +320,10 @@ static void write_force_cs(const struct spi_slave *slave, int assert) struct ipq_spi_slave *ds = to_ipq_spi(slave); if (assert) - clrsetbits_le32(ds->regs->io_control, + clrsetbits32(ds->regs->io_control, SPI_IO_CTRL_FORCE_CS_MSK, SPI_IO_CTRL_FORCE_CS_EN); else - clrsetbits_le32(ds->regs->io_control, + clrsetbits32(ds->regs->io_control, SPI_IO_CTRL_FORCE_CS_MSK, SPI_IO_CTRL_FORCE_CS_DIS); return; @@ -385,18 +385,18 @@ static void enable_io_config(struct ipq_spi_slave *ds, { if (write_cnt) { - clrsetbits_le32(ds->regs->qup_config, + clrsetbits32(ds->regs->qup_config, QUP_CONF_OUTPUT_MSK, QUP_CONF_OUTPUT_ENA); } else { - clrsetbits_le32(ds->regs->qup_config, + clrsetbits32(ds->regs->qup_config, QUP_CONF_OUTPUT_MSK, QUP_CONF_NO_OUTPUT); } if (read_cnt) { - clrsetbits_le32(ds->regs->qup_config, + clrsetbits32(ds->regs->qup_config, QUP_CONF_INPUT_MSK, QUP_CONF_INPUT_ENA); } else { - clrsetbits_le32(ds->regs->qup_config, + clrsetbits32(ds->regs->qup_config, QUP_CONF_INPUT_MSK, QUP_CONF_NO_INPUT); } diff --git a/src/soc/qualcomm/ipq806x/clock.c b/src/soc/qualcomm/ipq806x/clock.c index 15ea852ae8..5b7469c3fb 100644 --- a/src/soc/qualcomm/ipq806x/clock.c +++ b/src/soc/qualcomm/ipq806x/clock.c @@ -23,7 +23,7 @@ */ void uart_pll_vote_clk_enable(unsigned int clk_dummy) { - setbits_le32(BB_PLL_ENA_SC0_REG, BIT(8)); + setbits32(BB_PLL_ENA_SC0_REG, BIT(8)); if (!clk_dummy) while ((read32(PLL_LOCK_DET_STATUS_REG) & BIT(8)) == 0); @@ -39,11 +39,11 @@ static void uart_set_rate_mnd(unsigned int gsbi_port, unsigned int m, unsigned int n) { /* Assert MND reset. */ - setbits_le32(GSBIn_UART_APPS_NS_REG(gsbi_port), BIT(7)); + setbits32(GSBIn_UART_APPS_NS_REG(gsbi_port), BIT(7)); /* Program M and D values. */ write32(GSBIn_UART_APPS_MD_REG(gsbi_port), MD16(m, n)); /* Deassert MND reset. */ - clrbits_le32(GSBIn_UART_APPS_NS_REG(gsbi_port), BIT(7)); + clrbits32(GSBIn_UART_APPS_NS_REG(gsbi_port), BIT(7)); } /** @@ -53,7 +53,7 @@ static void uart_set_rate_mnd(unsigned int gsbi_port, unsigned int m, */ static void uart_branch_clk_enable_reg(unsigned int gsbi_port) { - setbits_le32(GSBIn_UART_APPS_NS_REG(gsbi_port), BIT(9)); + setbits32(GSBIn_UART_APPS_NS_REG(gsbi_port), BIT(9)); } /** @@ -100,7 +100,7 @@ static void uart_local_clock_enable(unsigned int gsbi_port, unsigned int n, */ static void uart_set_gsbi_clk(unsigned int gsbi_port) { - setbits_le32(GSBIn_HCLK_CTL_REG(gsbi_port), BIT(4)); + setbits32(GSBIn_HCLK_CTL_REG(gsbi_port), BIT(4)); } /** diff --git a/src/soc/qualcomm/ipq806x/include/soc/iomap.h b/src/soc/qualcomm/ipq806x/include/soc/iomap.h index 76fd353bca..d501a81b39 100644 --- a/src/soc/qualcomm/ipq806x/include/soc/iomap.h +++ b/src/soc/qualcomm/ipq806x/include/soc/iomap.h @@ -46,8 +46,8 @@ */ #define readl_i(a) read32((const void *)(a)) #define writel_i(v,a) write32((void *)a, v) -#define clrsetbits_le32_i(addr, clear, set) \ - clrsetbits_le32(((void *)(addr)), (clear), (set)) +#define clrsetbits32_i(addr, clear, set) \ + clrsetbits32(((void *)(addr)), (clear), (set)) #define MSM_CLK_CTL_BASE ((void *)0x00900000) diff --git a/src/soc/qualcomm/ipq806x/spi.c b/src/soc/qualcomm/ipq806x/spi.c index 183b33c20a..e2467b9ffd 100644 --- a/src/soc/qualcomm/ipq806x/spi.c +++ b/src/soc/qualcomm/ipq806x/spi.c @@ -307,7 +307,7 @@ static void gsbi_pin_config(unsigned int port_num, int cs_num) unsigned int gpio; unsigned int i; /* Hold the GSBIn (core_num) core in reset */ - clrsetbits_le32_i(GSBIn_RESET_REG(GSBI_IDX_TO_GSBI(port_num)), + clrsetbits32_i(GSBIn_RESET_REG(GSBI_IDX_TO_GSBI(port_num)), GSBI1_RESET_MSK, GSBI1_RESET); /* @@ -348,11 +348,11 @@ static int gsbi_clock_init(struct ipq_spi_slave *ds) int ret; /* Hold the GSBIn (core_num) core in reset */ - clrsetbits_le32_i(GSBIn_RESET_REG(GSBI_IDX_TO_GSBI(ds->slave.bus)), + clrsetbits32_i(GSBIn_RESET_REG(GSBI_IDX_TO_GSBI(ds->slave.bus)), GSBI1_RESET_MSK, GSBI1_RESET); /* Disable GSBIn (core_num) QUP core clock branch */ - clrsetbits_le32_i(ds->regs->qup_ns_reg, QUP_CLK_BRANCH_ENA_MSK, + clrsetbits32_i(ds->regs->qup_ns_reg, QUP_CLK_BRANCH_ENA_MSK, QUP_CLK_BRANCH_DIS); ret = check_qup_clk_state(ds->slave.bus, 1); @@ -363,41 +363,41 @@ static int gsbi_clock_init(struct ipq_spi_slave *ds) } /* Disable M/N:D counter and hold M/N:D counter in reset */ - clrsetbits_le32_i(ds->regs->qup_ns_reg, (MNCNTR_MSK | MNCNTR_RST_MSK), + clrsetbits32_i(ds->regs->qup_ns_reg, (MNCNTR_MSK | MNCNTR_RST_MSK), (MNCNTR_RST_ENA | MNCNTR_DIS)); /* Disable GSBIn (core_num) QUP core clock root */ - clrsetbits_le32_i(ds->regs->qup_ns_reg, CLK_ROOT_ENA_MSK, CLK_ROOT_DIS); + clrsetbits32_i(ds->regs->qup_ns_reg, CLK_ROOT_ENA_MSK, CLK_ROOT_DIS); - clrsetbits_le32_i(ds->regs->qup_ns_reg, GSBIn_PLL_SRC_MSK, + clrsetbits32_i(ds->regs->qup_ns_reg, GSBIn_PLL_SRC_MSK, GSBIn_PLL_SRC_PLL8); - clrsetbits_le32_i(ds->regs->qup_ns_reg, GSBIn_PRE_DIV_SEL_MSK, + clrsetbits32_i(ds->regs->qup_ns_reg, GSBIn_PRE_DIV_SEL_MSK, (0 << GSBI_PRE_DIV_SEL_SHFT)); /* Program M/N:D values for GSBIn_QUP_APPS_CLK @50MHz */ - clrsetbits_le32_i(ds->regs->qup_md_reg, GSBIn_M_VAL_MSK, + clrsetbits32_i(ds->regs->qup_md_reg, GSBIn_M_VAL_MSK, (0x01 << GSBI_M_VAL_SHFT)); - clrsetbits_le32_i(ds->regs->qup_md_reg, GSBIn_D_VAL_MSK, + clrsetbits32_i(ds->regs->qup_md_reg, GSBIn_D_VAL_MSK, (0xF7 << GSBI_D_VAL_SHFT)); - clrsetbits_le32_i(ds->regs->qup_ns_reg, GSBIn_N_VAL_MSK, + clrsetbits32_i(ds->regs->qup_ns_reg, GSBIn_N_VAL_MSK, (0xF8 << GSBI_N_VAL_SHFT)); /* Set MNCNTR_MODE = 0: Bypass mode */ - clrsetbits_le32_i(ds->regs->qup_ns_reg, MNCNTR_MODE_MSK, + clrsetbits32_i(ds->regs->qup_ns_reg, MNCNTR_MODE_MSK, MNCNTR_MODE_DUAL_EDGE); /* De-assert the M/N:D counter reset */ - clrsetbits_le32_i(ds->regs->qup_ns_reg, MNCNTR_RST_MSK, MNCNTR_RST_DIS); - clrsetbits_le32_i(ds->regs->qup_ns_reg, MNCNTR_MSK, MNCNTR_EN); + clrsetbits32_i(ds->regs->qup_ns_reg, MNCNTR_RST_MSK, MNCNTR_RST_DIS); + clrsetbits32_i(ds->regs->qup_ns_reg, MNCNTR_MSK, MNCNTR_EN); /* * Enable the GSBIn (core_num) QUP core clock root. * Keep MND counter disabled */ - clrsetbits_le32_i(ds->regs->qup_ns_reg, CLK_ROOT_ENA_MSK, CLK_ROOT_ENA); + clrsetbits32_i(ds->regs->qup_ns_reg, CLK_ROOT_ENA_MSK, CLK_ROOT_ENA); /* Enable GSBIn (core_num) QUP core clock branch */ - clrsetbits_le32_i(ds->regs->qup_ns_reg, QUP_CLK_BRANCH_ENA_MSK, + clrsetbits32_i(ds->regs->qup_ns_reg, QUP_CLK_BRANCH_ENA_MSK, QUP_CLK_BRANCH_ENA); ret = check_qup_clk_state(ds->slave.bus, 0); @@ -409,7 +409,7 @@ static int gsbi_clock_init(struct ipq_spi_slave *ds) } /* Enable GSBIn (core_num) core clock branch */ - clrsetbits_le32_i(GSBIn_HCLK_CTL_REG(GSBI_IDX_TO_GSBI(ds->slave.bus)), + clrsetbits32_i(GSBIn_HCLK_CTL_REG(GSBI_IDX_TO_GSBI(ds->slave.bus)), GSBI_CLK_BRANCH_ENA_MSK, GSBI_CLK_BRANCH_ENA); ret = check_hclk_state(ds->slave.bus, 0); @@ -420,7 +420,7 @@ static int gsbi_clock_init(struct ipq_spi_slave *ds) } /* Release GSBIn (core_num) core from reset */ - clrsetbits_le32_i(GSBIn_RESET_REG(GSBI_IDX_TO_GSBI(ds->slave.bus)), + clrsetbits32_i(GSBIn_RESET_REG(GSBI_IDX_TO_GSBI(ds->slave.bus)), GSBI1_RESET_MSK, 0); udelay(50); @@ -541,14 +541,14 @@ static int spi_hw_init(struct ipq_spi_slave *ds) return ret; /* Configure GSBI_CTRL register to set protocol_mode to SPI:011 */ - clrsetbits_le32_i(ds->regs->gsbi_ctrl, PROTOCOL_CODE_MSK, + clrsetbits32_i(ds->regs->gsbi_ctrl, PROTOCOL_CODE_MSK, PROTOCOL_CODE_SPI); /* * Configure Mini core to SPI core with Input Output enabled, * SPI master, N = 8 bits */ - clrsetbits_le32_i(ds->regs->qup_config, (QUP_CONFIG_MINI_CORE_MSK | + clrsetbits32_i(ds->regs->qup_config, (QUP_CONFIG_MINI_CORE_MSK | SPI_QUP_CONF_INPUT_MSK | SPI_QUP_CONF_OUTPUT_MSK | SPI_BIT_WORD_MSK), @@ -561,7 +561,7 @@ static int spi_hw_init(struct ipq_spi_slave *ds) * Configure Input first SPI protocol, * SPI master mode and no loopback */ - clrsetbits_le32_i(ds->regs->spi_config, (LOOP_BACK_MSK | + clrsetbits32_i(ds->regs->spi_config, (LOOP_BACK_MSK | SLAVE_OPERATION_MSK), (NO_LOOP_BACK | SLAVE_OPERATION)); @@ -581,7 +581,7 @@ static int spi_hw_init(struct ipq_spi_slave *ds) * INPUT_MODE = Block Mode * OUTPUT MODE = Block Mode */ - clrsetbits_le32_i(ds->regs->qup_io_modes, (OUTPUT_BIT_SHIFT_MSK | + clrsetbits32_i(ds->regs->qup_io_modes, (OUTPUT_BIT_SHIFT_MSK | INPUT_BLOCK_MODE_MSK | OUTPUT_BLOCK_MODE_MSK), (OUTPUT_BIT_SHIFT_EN | @@ -707,7 +707,7 @@ static int spi_ctrlr_xfer(const struct spi_slave *slave, const void *dout, * Let's do the write side of the transaction first. Enable output * FIFO. */ - clrsetbits_le32_i(ds->regs->qup_config, SPI_QUP_CONF_OUTPUT_MSK, + clrsetbits32_i(ds->regs->qup_config, SPI_QUP_CONF_OUTPUT_MSK, SPI_QUP_CONF_OUTPUT_ENA); while (out_bytes) { @@ -729,7 +729,7 @@ spi_receive: goto out; /* Enable input FIFO */ - clrsetbits_le32_i(ds->regs->qup_config, SPI_QUP_CONF_INPUT_MSK, + clrsetbits32_i(ds->regs->qup_config, SPI_QUP_CONF_INPUT_MSK, SPI_QUP_CONF_INPUT_ENA); while (in_bytes) { diff --git a/src/soc/qualcomm/ipq806x/usb.c b/src/soc/qualcomm/ipq806x/usb.c index 35285cd0d5..003bc7bf0b 100644 --- a/src/soc/qualcomm/ipq806x/usb.c +++ b/src/soc/qualcomm/ipq806x/usb.c @@ -127,9 +127,9 @@ static void setup_dwc3(struct usb_dwc3 *dwc3) udelay(5); - clrbits_le32(&dwc3->ctl, 0x1 << 11); /* deassert core soft reset */ - clrbits_le32(&dwc3->usb2phycfg, 0x1 << 31); /* PHY soft reset */ - clrbits_le32(&dwc3->usb3pipectl, 0x1 << 31); /* PHY soft reset */ + clrbits32(&dwc3->ctl, 0x1 << 11); /* deassert core soft reset */ + clrbits32(&dwc3->usb2phycfg, 0x1 << 31); /* PHY soft reset */ + clrbits32(&dwc3->usb3pipectl, 0x1 << 31); /* PHY soft reset */ } static void setup_phy(struct usb_qc_phy *phy) @@ -164,7 +164,7 @@ static void setup_phy(struct usb_qc_phy *phy) write32(&phy->general_cfg, 0x1 << 2); /* set XHCI 1.00 compliance */ udelay(5); - clrbits_le32(&phy->ss_phy_ctrl, 0x1 << 7); /* deassert SS PHY reset */ + clrbits32(&phy->ss_phy_ctrl, 0x1 << 7); /* deassert SS PHY reset */ } static void crport_handshake(void *capture_reg, void *acknowledge_bit, u32 data) @@ -206,7 +206,7 @@ static void tune_phy(struct usb_qc_phy *phy) void setup_usb_host1(void) { printk(BIOS_INFO, "Setting up USB HOST1 controller...\n"); - setbits_le32(tcsr_usb_sel, 1 << 0); /* Select DWC3 controller */ + setbits32(tcsr_usb_sel, 1 << 0); /* Select DWC3 controller */ setup_phy(usb_host1_phy); setup_dwc3(usb_host1_dwc3); tune_phy(usb_host1_phy); @@ -215,7 +215,7 @@ void setup_usb_host1(void) void setup_usb_host2(void) { printk(BIOS_INFO, "Setting up USB HOST2 controller...\n"); - setbits_le32(tcsr_usb_sel, 1 << 1); /* Select DWC3 controller */ + setbits32(tcsr_usb_sel, 1 << 1); /* Select DWC3 controller */ setup_phy(usb_host2_phy); setup_dwc3(usb_host2_dwc3); tune_phy(usb_host2_phy); diff --git a/src/soc/qualcomm/qcs405/blsp.c b/src/soc/qualcomm/qcs405/blsp.c index f185ea388a..42dc28d16c 100644 --- a/src/soc/qualcomm/qcs405/blsp.c +++ b/src/soc/qualcomm/qcs405/blsp.c @@ -59,7 +59,7 @@ blsp_return_t blsp_i2c_init(blsp_qup_id_t id) return BLSP_ID_ERROR; /* Configure Mini core to I2C core */ - clrsetbits_le32(base, BLSP_MINI_CORE_MASK, BLSP_MINI_CORE_I2C); + clrsetbits32(base, BLSP_MINI_CORE_MASK, BLSP_MINI_CORE_I2C); return BLSP_SUCCESS; } diff --git a/src/soc/qualcomm/qcs405/clock.c b/src/soc/qualcomm/qcs405/clock.c index 37fd2c2098..da2e8a4603 100644 --- a/src/soc/qualcomm/qcs405/clock.c +++ b/src/soc/qualcomm/qcs405/clock.c @@ -96,7 +96,7 @@ struct clock_config spi_cfg[] = { static int clock_configure_gpll0(void) { /* Keep existing GPLL0 configuration, in RUN mode @800Mhz. */ - setbits_le32(&gcc->gpll0.user_ctl, + setbits32(&gcc->gpll0.user_ctl, 1 << CLK_CTL_GPLL_PLLOUT_LV_EARLY_SHFT | 1 << CLK_CTL_GPLL_PLLOUT_AUX2_SHFT | 1 << CLK_CTL_GPLL_PLLOUT_AUX_SHFT | @@ -144,7 +144,7 @@ static int clock_configure(struct qcs405_clock *clk, clk_cfg[idx].d_2); /* Commit config to RCG*/ - setbits_le32(&clk->rcg.cmd, BIT(CLK_CTL_CMD_UPDATE_SHFT)); + setbits32(&clk->rcg.cmd, BIT(CLK_CTL_CMD_UPDATE_SHFT)); return 0; } @@ -159,7 +159,7 @@ static int clock_enable_vote(void *cbcr_addr, void *vote_addr, { /* Set clock vote bit */ - setbits_le32(vote_addr, BIT(vote_bit)); + setbits32(vote_addr, BIT(vote_bit)); /* Ensure clock is enabled */ while (clock_is_off(cbcr_addr)); @@ -171,7 +171,7 @@ static int clock_enable(void *cbcr_addr) { /* Set clock enable bit */ - setbits_le32(cbcr_addr, BIT(CLK_CTL_CBC_CLK_EN_SHFT)); + setbits32(cbcr_addr, BIT(CLK_CTL_CBC_CLK_EN_SHFT)); /* Ensure clock is enabled */ while (clock_is_off(cbcr_addr)) @@ -184,7 +184,7 @@ static int clock_disable(void *cbcr_addr) { /* Set clock enable bit */ - clrbits_le32(cbcr_addr, BIT(CLK_CTL_CBC_CLK_EN_SHFT)); + clrbits32(cbcr_addr, BIT(CLK_CTL_CBC_CLK_EN_SHFT)); return 0; } @@ -193,9 +193,9 @@ int clock_reset_bcr(void *bcr_addr, bool reset) struct qcs405_bcr *bcr = bcr_addr; if (reset) - setbits_le32(&bcr->bcr, BIT(CLK_CTL_BCR_BLK_ARES_SHFT)); + setbits32(&bcr->bcr, BIT(CLK_CTL_BCR_BLK_ARES_SHFT)); else - clrbits_le32(&bcr->bcr, BIT(CLK_CTL_BCR_BLK_ARES_SHFT)); + clrbits32(&bcr->bcr, BIT(CLK_CTL_BCR_BLK_ARES_SHFT)); return 0; } diff --git a/src/soc/qualcomm/qcs405/gpio.c b/src/soc/qualcomm/qcs405/gpio.c index fc58fae7ff..19027c32bb 100644 --- a/src/soc/qualcomm/qcs405/gpio.c +++ b/src/soc/qualcomm/qcs405/gpio.c @@ -78,9 +78,9 @@ void gpio_input_irq(gpio_t gpio, enum gpio_irq_type type, uint32_t pull) gpio_configure(gpio, GPIO_FUNC_GPIO, pull, GPIO_2MA, GPIO_DISABLE); - clrsetbits_le32(®s->intr_cfg, GPIO_INTR_DECT_CTL_MASK << + clrsetbits32(®s->intr_cfg, GPIO_INTR_DECT_CTL_MASK << GPIO_INTR_DECT_CTL_SHIFT, type << GPIO_INTR_DECT_CTL_SHIFT); - clrsetbits_le32(®s->intr_cfg, GPIO_INTR_RAW_STATUS_ENABLE + clrsetbits32(®s->intr_cfg, GPIO_INTR_RAW_STATUS_ENABLE << GPIO_INTR_RAW_STATUS_EN_SHIFT, GPIO_INTR_RAW_STATUS_ENABLE << GPIO_INTR_RAW_STATUS_EN_SHIFT); } diff --git a/src/soc/qualcomm/qcs405/include/soc/iomap.h b/src/soc/qualcomm/qcs405/include/soc/iomap.h index 2ed3e10f76..7d948ec46e 100644 --- a/src/soc/qualcomm/qcs405/include/soc/iomap.h +++ b/src/soc/qualcomm/qcs405/include/soc/iomap.h @@ -48,8 +48,8 @@ */ #define readl_i(a) read32((const void *)(a)) #define writel_i(v, a) write32((void *)a, v) -#define clrsetbits_le32_i(addr, clear, set) \ - clrsetbits_le32(((void *)(addr)), (clear), (set)) +#define clrsetbits32_i(addr, clear, set) \ + clrsetbits32(((void *)(addr)), (clear), (set)) #define GCC_CLK_CTL_REG ((void *)0x01800000u) #define MSM_CLK_CTL_BASE GCC_CLK_CTL_REG diff --git a/src/soc/qualcomm/qcs405/spi.c b/src/soc/qualcomm/qcs405/spi.c index 827448ce91..f621778f65 100644 --- a/src/soc/qualcomm/qcs405/spi.c +++ b/src/soc/qualcomm/qcs405/spi.c @@ -247,10 +247,10 @@ static void write_force_cs(const struct spi_slave *slave, int assert) { struct qcs_spi_slave *ds = to_qcs_spi(slave); if (assert) - clrsetbits_le32(ds->regs->io_control, + clrsetbits32(ds->regs->io_control, SPI_IO_CTRL_FORCE_CS_MSK, SPI_IO_CTRL_FORCE_CS_EN); else - clrsetbits_le32(ds->regs->io_control, + clrsetbits32(ds->regs->io_control, SPI_IO_CTRL_FORCE_CS_MSK, SPI_IO_CTRL_FORCE_CS_DIS); } @@ -275,7 +275,7 @@ static int spi_hw_init(struct qcs_spi_slave *ds) * Configure Mini core to SPI core with Input Output enabled, * SPI master, N = 8 bits */ - clrsetbits_le32(ds->regs->qup_config, QUP_CONFIG_MINI_CORE_MSK | + clrsetbits32(ds->regs->qup_config, QUP_CONFIG_MINI_CORE_MSK | QUP_CONF_INPUT_MSK | QUP_CONF_OUTPUT_MSK | QUP_CONF_N_MASK, @@ -288,7 +288,7 @@ static int spi_hw_init(struct qcs_spi_slave *ds) * Configure Input first SPI protocol, * SPI master mode and no loopback */ - clrsetbits_le32(ds->regs->spi_config, SPI_CONFIG_LOOP_BACK_MSK | + clrsetbits32(ds->regs->spi_config, SPI_CONFIG_LOOP_BACK_MSK | SPI_CONFIG_NO_SLAVE_OPER_MSK, SPI_CONFIG_NO_LOOP_BACK | SPI_CONFIG_NO_SLAVE_OPER); @@ -308,7 +308,7 @@ static int spi_hw_init(struct qcs_spi_slave *ds) * INPUT_MODE = Block Mode * OUTPUT MODE = Block Mode */ - clrsetbits_le32(ds->regs->qup_io_modes, + clrsetbits32(ds->regs->qup_io_modes, QUP_IO_MODES_OUTPUT_BIT_SHIFT_MSK | QUP_IO_MODES_INPUT_MODE_MSK | QUP_IO_MODES_OUTPUT_MODE_MSK, @@ -433,18 +433,18 @@ static void enable_io_config(struct qcs_spi_slave *ds, { if (write_cnt) { - clrsetbits_le32(ds->regs->qup_config, + clrsetbits32(ds->regs->qup_config, QUP_CONF_OUTPUT_MSK, QUP_CONF_OUTPUT_ENA); } else { - clrsetbits_le32(ds->regs->qup_config, + clrsetbits32(ds->regs->qup_config, QUP_CONF_OUTPUT_MSK, QUP_CONF_NO_OUTPUT); } if (read_cnt) { - clrsetbits_le32(ds->regs->qup_config, + clrsetbits32(ds->regs->qup_config, QUP_CONF_INPUT_MSK, QUP_CONF_INPUT_ENA); } else { - clrsetbits_le32(ds->regs->qup_config, + clrsetbits32(ds->regs->qup_config, QUP_CONF_INPUT_MSK, QUP_CONF_NO_INPUT); } } diff --git a/src/soc/qualcomm/qcs405/usb.c b/src/soc/qualcomm/qcs405/usb.c index a94973ff2b..7ddfaa231e 100644 --- a/src/soc/qualcomm/qcs405/usb.c +++ b/src/soc/qualcomm/qcs405/usb.c @@ -183,16 +183,16 @@ static void hs_usb_phy_init(struct usb_dwc3_cfg *dwc3) static void setup_dwc3(struct usb_dwc3 *dwc3) { /* core exits U1/U2/U3 only in PHY power state P1/P2/P3 respectively */ - clrsetbits_le32(&dwc3->usb3pipectl, + clrsetbits32(&dwc3->usb3pipectl, DWC3_GUSB3PIPECTL_DELAYP1TRANS, DWC3_GUSB3PIPECTL_UX_EXIT_IN_PX); - clrsetbits_le32(&dwc3->ctl, (DWC3_GCTL_SCALEDOWN_MASK | + clrsetbits32(&dwc3->ctl, (DWC3_GCTL_SCALEDOWN_MASK | DWC3_GCTL_DISSCRAMBLE), DWC3_GCTL_U2EXIT_LFPS | DWC3_GCTL_DSBLCLKGTNG); /* configure controller in Host mode */ - clrsetbits_le32(&dwc3->ctl, (DWC3_GCTL_PRTCAPDIR(DWC3_GCTL_PRTCAP_OTG)), + clrsetbits32(&dwc3->ctl, (DWC3_GCTL_PRTCAPDIR(DWC3_GCTL_PRTCAP_OTG)), DWC3_GCTL_PRTCAPDIR(DWC3_GCTL_PRTCAP_HOST)); printk(BIOS_INFO, "Configure USB in Host mode\n"); } @@ -213,10 +213,10 @@ void setup_usb_host(enum usb_port port, struct usb_board_data *board_data) if (port == HSUSB_SS_PORT_0) { /* Set PHY reset. */ - setbits_le32(&dwc3->usb2_phy_bcr, BIT(1)); + setbits32(&dwc3->usb2_phy_bcr, BIT(1)); udelay(15); /* Clear PHY reset. */ - clrbits_le32(&dwc3->usb2_phy_bcr, BIT(1)); + clrbits32(&dwc3->usb2_phy_bcr, BIT(1)); } else { clock_reset_bcr(dwc3->usb2_phy_bcr, 1); udelay(15); @@ -229,13 +229,13 @@ void setup_usb_host(enum usb_port port, struct usb_board_data *board_data) if (port == HSUSB_SS_PORT_0) { /* Set PHY POR reset. */ - setbits_le32(&dwc3->usb2_phy_por_bcr, BIT(0)); + setbits32(&dwc3->usb2_phy_por_bcr, BIT(0)); val = read8(&dwc3->usb2_phy_dig->ctrl_common0); val &= ~(0x4); write8(&dwc3->usb2_phy_dig->ctrl_common0, val); udelay(20); /* Clear PHY POR reset. */ - clrbits_le32(&dwc3->usb2_phy_por_bcr, BIT(0)); + clrbits32(&dwc3->usb2_phy_por_bcr, BIT(0)); } else { clock_reset_bcr(dwc3->usb2_phy_por_bcr, 1); val = read8(&dwc3->usb2_phy_dig->ctrl_common0); @@ -254,13 +254,13 @@ void setup_usb_host(enum usb_port port, struct usb_board_data *board_data) */ /* Configure dwc3 to use UTMI clock as PIPE clock not present */ - setbits_le32(&dwc3->usb_qscratch_reg->qscratch_cfg_reg, + setbits32(&dwc3->usb_qscratch_reg->qscratch_cfg_reg, PIPE_UTMI_CLK_DIS); udelay(2); - setbits_le32(&dwc3->usb_qscratch_reg->qscratch_cfg_reg, + setbits32(&dwc3->usb_qscratch_reg->qscratch_cfg_reg, PIPE_UTMI_CLK_SEL | PIPE3_PHYSTATUS_SW); udelay(3); - clrbits_le32(&dwc3->usb_qscratch_reg->qscratch_cfg_reg, + clrbits32(&dwc3->usb_qscratch_reg->qscratch_cfg_reg, PIPE_UTMI_CLK_DIS); printk(BIOS_INFO, "DWC3 and PHY setup finished\n"); diff --git a/src/soc/qualcomm/sc7180/gpio.c b/src/soc/qualcomm/sc7180/gpio.c index 9f3b722e31..ad89f85011 100644 --- a/src/soc/qualcomm/sc7180/gpio.c +++ b/src/soc/qualcomm/sc7180/gpio.c @@ -13,9 +13,9 @@ * GNU General Public License for more details. */ -#include #include #include +#include #include #include #include @@ -86,9 +86,9 @@ void gpio_input_irq(gpio_t gpio, enum gpio_irq_type type, uint32_t pull) gpio_configure(gpio, GPIO_FUNC_GPIO, pull, GPIO_2MA, GPIO_OUTPUT_DISABLE); - clrsetbits_le32(®s->intr_cfg, GPIO_INTR_DECT_CTL_MASK << + clrsetbits32(®s->intr_cfg, GPIO_INTR_DECT_CTL_MASK << GPIO_INTR_DECT_CTL_SHIFT, type << GPIO_INTR_DECT_CTL_SHIFT); - clrsetbits_le32(®s->intr_cfg, GPIO_INTR_RAW_STATUS_ENABLE + clrsetbits32(®s->intr_cfg, GPIO_INTR_RAW_STATUS_ENABLE << GPIO_INTR_RAW_STATUS_EN_SHIFT, GPIO_INTR_RAW_STATUS_ENABLE << GPIO_INTR_RAW_STATUS_EN_SHIFT); } diff --git a/src/soc/qualcomm/sdm845/clock.c b/src/soc/qualcomm/sdm845/clock.c index e55495b86e..f3b34cf68a 100644 --- a/src/soc/qualcomm/sdm845/clock.c +++ b/src/soc/qualcomm/sdm845/clock.c @@ -66,7 +66,7 @@ struct clock_config qspi_core_cfg[] = { static int clock_configure_gpll0(void) { /* Keep existing GPLL0 configuration, in RUN mode @600Mhz. */ - setbits_le32(&gcc->gpll0.user_ctl, + setbits32(&gcc->gpll0.user_ctl, 1 << CLK_CTL_GPLL_PLLOUT_EVEN_SHFT | 1 << CLK_CTL_GPLL_PLLOUT_MAIN_SHFT | 1 << CLK_CTL_GPLL_PLLOUT_ODD_SHFT); @@ -76,7 +76,7 @@ static int clock_configure_gpll0(void) static int clock_configure_mnd(struct sdm845_clock *clk, uint32_t m, uint32_t n, uint32_t d_2) { - setbits_le32(&clk->rcg.cfg, + setbits32(&clk->rcg.cfg, RCG_MODE_DUAL_EDGE << CLK_CTL_CFG_MODE_SHFT); write32(&clk->m, m & CLK_CTL_RCG_MND_BMSK); @@ -110,7 +110,7 @@ static int clock_configure(struct sdm845_clock *clk, clk_cfg[idx].d_2); /* Commit config to RCG*/ - setbits_le32(&clk->rcg.cmd, BIT(CLK_CTL_CMD_UPDATE_SHFT)); + setbits32(&clk->rcg.cmd, BIT(CLK_CTL_CMD_UPDATE_SHFT)); return 0; } @@ -125,7 +125,7 @@ static int clock_enable_vote(void *cbcr_addr, void *vote_addr, { /* Set clock vote bit */ - setbits_le32(vote_addr, BIT(vote_bit)); + setbits32(vote_addr, BIT(vote_bit)); /* Ensure clock is enabled */ while (clock_is_off(cbcr_addr)) @@ -138,7 +138,7 @@ static int clock_enable(void *cbcr_addr) { /* Set clock enable bit */ - setbits_le32(cbcr_addr, BIT(CLK_CTL_CBC_CLK_EN_SHFT)); + setbits32(cbcr_addr, BIT(CLK_CTL_CBC_CLK_EN_SHFT)); /* Ensure clock is enabled */ while (clock_is_off(cbcr_addr)) @@ -169,9 +169,9 @@ int clock_reset_bcr(void *bcr_addr, bool reset) struct sdm845_bcr *bcr = bcr_addr; if (reset) - setbits_le32(bcr, BIT(CLK_CTL_BCR_BLK_ARES_SHFT)); + setbits32(bcr, BIT(CLK_CTL_BCR_BLK_ARES_SHFT)); else - clrbits_le32(bcr, BIT(CLK_CTL_BCR_BLK_ARES_SHFT)); + clrbits32(bcr, BIT(CLK_CTL_BCR_BLK_ARES_SHFT)); return 0; } diff --git a/src/soc/qualcomm/sdm845/usb.c b/src/soc/qualcomm/sdm845/usb.c index 8e2b9119ae..56da28e44d 100644 --- a/src/soc/qualcomm/sdm845/usb.c +++ b/src/soc/qualcomm/sdm845/usb.c @@ -13,10 +13,10 @@ * GNU General Public License for more details. */ -#include #include #include #include +#include #include #include #include @@ -725,7 +725,7 @@ static void qusb2_phy_set_tune_param(struct usb_dwc3_cfg *dwc3) * tune parameters. */ if (tune_val) - clrsetbits_le32(&dwc3->qusb_phy_dig->tune1, + clrsetbits32(&dwc3->qusb_phy_dig->tune1, PORT_TUNE1_MASK, tune_val << 4); } @@ -762,7 +762,7 @@ static void tune_phy(struct usb_dwc3_cfg *dwc3, struct usb_qusb_phy_dig *phy) static void hs_qusb_phy_init(struct usb_dwc3_cfg *dwc3) { /* PWR_CTRL: set the power down bit to disable the PHY */ - setbits_le32(&dwc3->qusb_phy_dig->pwr_ctrl1, POWER_DOWN); + setbits32(&dwc3->qusb_phy_dig->pwr_ctrl1, POWER_DOWN); write32(&dwc3->qusb_phy_pll->analog_controls_two, QUSB2PHY_PLL_ANALOG_CONTROLS_TWO); @@ -782,7 +782,7 @@ static void hs_qusb_phy_init(struct usb_dwc3_cfg *dwc3) tune_phy(dwc3, dwc3->qusb_phy_dig); /* PWR_CTRL1: Clear the power down bit to enable the PHY */ - clrbits_le32(&dwc3->qusb_phy_dig->pwr_ctrl1, POWER_DOWN); + clrbits32(&dwc3->qusb_phy_dig->pwr_ctrl1, POWER_DOWN); write32(&dwc3->qusb_phy_dig->debug_ctrl2, DEBUG_CTRL2_MUX_PLL_LOCK_STATUS); @@ -848,7 +848,7 @@ static void ss_qmp_phy_init(struct usb_dwc3_cfg *dwc3) static void setup_dwc3(struct usb_dwc3 *dwc3) { /* core exits U1/U2/U3 only in PHY power state P1/P2/P3 respectively */ - clrsetbits_le32(&dwc3->usb3pipectl, + clrsetbits32(&dwc3->usb3pipectl, DWC3_GUSB3PIPECTL_DELAYP1TRANS, DWC3_GUSB3PIPECTL_UX_EXIT_IN_PX); @@ -858,18 +858,18 @@ static void setup_dwc3(struct usb_dwc3 *dwc3) * 2. Set USBTRDTIM to the corresponding value * according to the UTMI+ PHY interface. */ - clrsetbits_le32(&dwc3->usb2phycfg, + clrsetbits32(&dwc3->usb2phycfg, (DWC3_GUSB2PHYCFG_USB2TRDTIM_MASK | DWC3_GUSB2PHYCFG_PHYIF_MASK), (DWC3_GUSB2PHYCFG_PHYIF(UTMI_PHYIF_8_BIT) | DWC3_GUSB2PHYCFG_USBTRDTIM(USBTRDTIM_UTMI_8_BIT))); - clrsetbits_le32(&dwc3->ctl, (DWC3_GCTL_SCALEDOWN_MASK | + clrsetbits32(&dwc3->ctl, (DWC3_GCTL_SCALEDOWN_MASK | DWC3_GCTL_DISSCRAMBLE), DWC3_GCTL_U2EXIT_LFPS | DWC3_GCTL_DSBLCLKGTNG); /* configure controller in Host mode */ - clrsetbits_le32(&dwc3->ctl, (DWC3_GCTL_PRTCAPDIR(DWC3_GCTL_PRTCAP_OTG)), + clrsetbits32(&dwc3->ctl, (DWC3_GCTL_PRTCAPDIR(DWC3_GCTL_PRTCAP_OTG)), DWC3_GCTL_PRTCAPDIR(DWC3_GCTL_PRTCAP_HOST)); printk(BIOS_SPEW, "Configure USB in Host mode\n"); } diff --git a/src/soc/rockchip/common/edp.c b/src/soc/rockchip/common/edp.c index ea0930a058..18afc3a50a 100644 --- a/src/soc/rockchip/common/edp.c +++ b/src/soc/rockchip/common/edp.c @@ -97,7 +97,7 @@ static void rk_edp_init_interrupt(struct rk_edp *edp) static void rk_edp_enable_sw_function(struct rk_edp *edp) { - clrbits_le32(&edp->regs->func_en_1, SW_FUNC_EN_N); + clrbits32(&edp->regs->func_en_1, SW_FUNC_EN_N); } static int rk_edp_get_pll_lock_status(struct rk_edp *edp) @@ -116,7 +116,7 @@ static void rk_edp_init_analog_func(struct rk_edp *edp) write32(&edp->regs->common_int_sta_1, PLL_LOCK_CHG); - clrbits_le32(&edp->regs->dp_debug_ctl, F_PLL_LOCK | PLL_LOCK_CTRL); + clrbits32(&edp->regs->dp_debug_ctl, F_PLL_LOCK | PLL_LOCK_CTRL); stopwatch_init_msecs_expire(&sw, PLL_LOCK_TIMEOUT); @@ -128,7 +128,7 @@ static void rk_edp_init_analog_func(struct rk_edp *edp) } /* Enable Serdes FIFO function and Link symbol clock domain module */ - clrbits_le32(&edp->regs->func_en_2, SERDES_FIFO_FUNC_EN_N | + clrbits32(&edp->regs->func_en_2, SERDES_FIFO_FUNC_EN_N | LS_CLK_DOMAIN_FUNC_EN_N | AUX_FUNC_EN_N | SSC_FUNC_EN_N); } @@ -139,20 +139,20 @@ static void rk_edp_init_aux(struct rk_edp *edp) write32(&edp->regs->dp_int_sta, AUX_FUNC_EN_N); /* Disable AUX channel module */ - setbits_le32(&edp->regs->func_en_2, AUX_FUNC_EN_N); + setbits32(&edp->regs->func_en_2, AUX_FUNC_EN_N); /* Receive AUX Channel DEFER commands equal to DEFFER_COUNT*64 */ write32(&edp->regs->aux_ch_defer_dtl, DEFER_CTRL_EN | DEFER_COUNT(1)); /* Enable AUX channel module */ - clrbits_le32(&edp->regs->func_en_2, AUX_FUNC_EN_N); + clrbits32(&edp->regs->func_en_2, AUX_FUNC_EN_N); } static int rk_edp_aux_enable(struct rk_edp *edp) { struct stopwatch sw; - setbits_le32(&edp->regs->aux_ch_ctl_2, AUX_EN); + setbits32(&edp->regs->aux_ch_ctl_2, AUX_EN); stopwatch_init_msecs_expire(&sw, 20); do { if (!(read32(&edp->regs->aux_ch_ctl_2) & AUX_EN)) @@ -698,7 +698,7 @@ static int rk_edp_read_bytes_from_i2c(struct rk_edp *edp, write32(&edp->regs->buf_data_ctl, val); /* Set normal AUX CH command */ - clrbits_le32(&edp->regs->aux_ch_ctl_2, ADDR_ONLY); + clrbits32(&edp->regs->aux_ch_ctl_2, ADDR_ONLY); /* * If Rx sends defer, Tx sends only reads @@ -816,7 +816,7 @@ static void rk_edp_init_video(struct rk_edp *edp) static void rk_edp_config_video_slave_mode(struct rk_edp *edp) { - clrbits_le32(&edp->regs->func_en_1, + clrbits32(&edp->regs->func_en_1, VID_FIFO_FUNC_EN_N | VID_CAP_FUNC_EN_N); } @@ -828,7 +828,7 @@ static void rk_edp_set_video_cr_mn(struct rk_edp *edp, u32 val; if (type == REGISTER_M) { - setbits_le32(&edp->regs->sys_ctl_4, FIX_M_VID); + setbits32(&edp->regs->sys_ctl_4, FIX_M_VID); val = m_value & 0xff; write32(&edp->regs->m_vid_0, val); val = (m_value >> 8) & 0xff; @@ -843,7 +843,7 @@ static void rk_edp_set_video_cr_mn(struct rk_edp *edp, val = (n_value >> 16) & 0xff; write32(&edp->regs->n_vid_2, val); } else { - clrbits_le32(&edp->regs->sys_ctl_4, FIX_M_VID); + clrbits32(&edp->regs->sys_ctl_4, FIX_M_VID); write32(&edp->regs->n_vid_0, 0x00); write32(&edp->regs->n_vid_1, 0x80); @@ -914,10 +914,10 @@ static int rk_edp_config_video(struct rk_edp *edp) rk_edp_set_video_cr_mn(edp, CALCULATED_M, 0, 0); /* For video bist, Video timing must be generated by register */ - clrbits_le32(&edp->regs->video_ctl_10, F_SEL); + clrbits32(&edp->regs->video_ctl_10, F_SEL); /* Disable video mute */ - clrbits_le32(&edp->regs->video_ctl_1, VIDEO_MUTE); + clrbits32(&edp->regs->video_ctl_1, VIDEO_MUTE); return 0; } @@ -1000,7 +1000,7 @@ int rk_edp_prepare(void) int rk_edp_enable(void) { /* Enable video at next frame */ - setbits_le32(&rk_edp.regs->video_ctl_1, VIDEO_EN); + setbits32(&rk_edp.regs->video_ctl_1, VIDEO_EN); return rk_edp_is_video_stream_on(&rk_edp); } diff --git a/src/soc/rockchip/common/gpio.c b/src/soc/rockchip/common/gpio.c index 3d7e1614e0..16ab385b03 100644 --- a/src/soc/rockchip/common/gpio.c +++ b/src/soc/rockchip/common/gpio.c @@ -24,16 +24,16 @@ static void gpio_set_dir(gpio_t gpio, enum gpio_dir dir) { - clrsetbits_le32(&gpio_port[gpio.port]->swporta_ddr, - 1 << gpio.num, dir << gpio.num); + clrsetbits32(&gpio_port[gpio.port]->swporta_ddr, + 1 << gpio.num, dir << gpio.num); } static void gpio_set_pull(gpio_t gpio, enum gpio_pull pull) { u32 pull_val = gpio_get_pull_val(gpio, pull); if (is_pmu_gpio(gpio) && CONFIG(SOC_ROCKCHIP_RK3288)) - clrsetbits_le32(gpio_grf_reg(gpio), 3 << (gpio.idx * 2), - pull_val << (gpio.idx * 2)); + clrsetbits32(gpio_grf_reg(gpio), 3 << (gpio.idx * 2), + pull_val << (gpio.idx * 2)); else write32(gpio_grf_reg(gpio), RK_CLRSETBITS(3 << (gpio.idx * 2), pull_val << (gpio.idx * 2))); @@ -83,13 +83,13 @@ void gpio_input_irq(gpio_t gpio, enum gpio_irq_type type, enum gpio_pull pull) case IRQ_TYPE_LEVEL_LOW: break; } - clrsetbits_le32(&gpio_port[gpio.port]->int_polarity, - mask, int_polarity); - clrsetbits_le32(&gpio_port[gpio.port]->inttype_level, - mask, inttype_level); + clrsetbits32(&gpio_port[gpio.port]->int_polarity, + mask, int_polarity); + clrsetbits32(&gpio_port[gpio.port]->inttype_level, + mask, inttype_level); - setbits_le32(&gpio_port[gpio.port]->inten, mask); - clrbits_le32(&gpio_port[gpio.port]->intmask, mask); + setbits32(&gpio_port[gpio.port]->inten, mask); + clrbits32(&gpio_port[gpio.port]->intmask, mask); } int gpio_irq_status(gpio_t gpio) @@ -100,7 +100,7 @@ int gpio_irq_status(gpio_t gpio) if (!(int_status & mask)) return 0; - setbits_le32(&gpio_port[gpio.port]->porta_eoi, mask); + setbits32(&gpio_port[gpio.port]->porta_eoi, mask); return 1; } @@ -111,8 +111,8 @@ int gpio_get(gpio_t gpio) void gpio_set(gpio_t gpio, int value) { - clrsetbits_le32(&gpio_port[gpio.port]->swporta_dr, 1 << gpio.num, - !!value << gpio.num); + clrsetbits32(&gpio_port[gpio.port]->swporta_dr, 1 << gpio.num, + !!value << gpio.num); } void gpio_output(gpio_t gpio, int value) diff --git a/src/soc/rockchip/common/pwm.c b/src/soc/rockchip/common/pwm.c index e5da05e672..82fc2596c0 100644 --- a/src/soc/rockchip/common/pwm.c +++ b/src/soc/rockchip/common/pwm.c @@ -79,5 +79,5 @@ void pwm_init(u32 id, u32 period_ns, u32 duty_ns) write32(&rk_pwm->pwm[id].pwm_period_hpr, period); write32(&rk_pwm->pwm[id].pwm_duty_lpr, duty); - setbits_le32(&rk_pwm->pwm[id].pwm_ctrl, RK_PWM_ENABLE); + setbits32(&rk_pwm->pwm[id].pwm_ctrl, RK_PWM_ENABLE); } diff --git a/src/soc/rockchip/common/spi.c b/src/soc/rockchip/common/spi.c index 0307e24d35..d91bae0eac 100644 --- a/src/soc/rockchip/common/spi.c +++ b/src/soc/rockchip/common/spi.c @@ -70,13 +70,13 @@ static struct rockchip_spi_slave *to_rockchip_spi(const struct spi_slave *slave) static void spi_cs_activate(const struct spi_slave *slave) { struct rockchip_spi *regs = to_rockchip_spi(slave)->regs; - setbits_le32(®s->ser, 1); + setbits32(®s->ser, 1); } static void spi_cs_deactivate(const struct spi_slave *slave) { struct rockchip_spi *regs = to_rockchip_spi(slave)->regs; - clrbits_le32(®s->ser, 1); + clrbits32(®s->ser, 1); } static void rockchip_spi_enable_chip(struct rockchip_spi *regs, int enable) @@ -141,8 +141,8 @@ void rockchip_spi_set_sample_delay(unsigned int bus, unsigned int delay_ns) /* Rxd Sample Delay */ rsd = DIV_ROUND_CLOSEST(delay_ns * (SPI_SRCCLK_HZ >> 8), 1*GHz >> 8); assert(rsd <= 3); - clrsetbits_le32(®s->ctrlr0, SPI_RXDSD_MASK << SPI_RXDSD_OFFSET, - rsd << SPI_RXDSD_OFFSET); + clrsetbits32(®s->ctrlr0, SPI_RXDSD_MASK << SPI_RXDSD_OFFSET, + rsd << SPI_RXDSD_OFFSET); } static int spi_ctrlr_claim_bus(const struct spi_slave *slave) @@ -172,7 +172,7 @@ static int rockchip_spi_wait_till_not_busy(struct rockchip_spi *regs) static void set_tmod(struct rockchip_spi *regs, unsigned int tmod) { - clrsetbits_le32(®s->ctrlr0, SPI_TMOD_MASK << SPI_TMOD_OFFSET, + clrsetbits32(®s->ctrlr0, SPI_TMOD_MASK << SPI_TMOD_OFFSET, tmod << SPI_TMOD_OFFSET); } @@ -275,9 +275,9 @@ static int spi_ctrlr_xfer(const struct spi_slave *slave, const void *dout, } mask = SPI_APB_8BIT << SPI_HALF_WORLD_TX_OFFSET; if (use_16bit) - clrbits_le32(®s->ctrlr0, mask); + clrbits32(®s->ctrlr0, mask); else - setbits_le32(®s->ctrlr0, mask); + setbits32(®s->ctrlr0, mask); /* Enable/disable transmitter and receiver as needed to * avoid sending or reading spurious bits. */ diff --git a/src/soc/rockchip/common/vop.c b/src/soc/rockchip/common/vop.c index 9c70b78171..6e0ce4086c 100644 --- a/src/soc/rockchip/common/vop.c +++ b/src/soc/rockchip/common/vop.c @@ -60,7 +60,7 @@ void rkvop_prepare(u32 vop_id, const struct edid *edid) write32(&preg->win0_dsp_info, V_DSP_WIDTH(hactive - 1) | V_DSP_HEIGHT(vactive - 1)); - clrsetbits_le32(&preg->win0_color_key, M_WIN0_KEY_EN | M_WIN0_KEY_COLOR, + clrsetbits32(&preg->win0_color_key, M_WIN0_KEY_EN | M_WIN0_KEY_COLOR, V_WIN0_KEY_EN(0) | V_WIN0_KEY_COLOR(0)); @@ -89,10 +89,10 @@ void rkvop_prepare(u32 vop_id, const struct edid *edid) else lb_mode = LB_RGB_1280X8; - clrsetbits_le32(&preg->win0_ctrl0, - M_WIN0_LB_MODE | M_WIN0_DATA_FMT | M_WIN0_EN, - V_WIN0_LB_MODE(lb_mode) | - V_WIN0_DATA_FMT(rgb_mode) | V_WIN0_EN(1)); + clrsetbits32(&preg->win0_ctrl0, + M_WIN0_LB_MODE | M_WIN0_DATA_FMT | M_WIN0_EN, + V_WIN0_LB_MODE(lb_mode) | + V_WIN0_DATA_FMT(rgb_mode) | V_WIN0_EN(1)); } void rkvop_mode_set(u32 vop_id, const struct edid *edid, u32 mode) @@ -111,34 +111,34 @@ void rkvop_mode_set(u32 vop_id, const struct edid *edid, u32 mode) switch (mode) { case VOP_MODE_HDMI: - clrsetbits_le32(&preg->sys_ctrl, - M_ALL_OUT_EN, V_HDMI_OUT_EN(1)); + clrsetbits32(&preg->sys_ctrl, + M_ALL_OUT_EN, V_HDMI_OUT_EN(1)); dsp_out_mode = 15; break; case VOP_MODE_MIPI: - clrsetbits_le32(&preg->sys_ctrl, M_ALL_OUT_EN, - V_MIPI_OUT_EN(1)); + clrsetbits32(&preg->sys_ctrl, M_ALL_OUT_EN, + V_MIPI_OUT_EN(1)); dsp_out_mode = 0; break; case VOP_MODE_DUAL_MIPI: - clrsetbits_le32(&preg->sys_ctrl, M_ALL_OUT_EN, - V_MIPI_OUT_EN(1) | V_DUAL_MIPI_EN(1)); + clrsetbits32(&preg->sys_ctrl, M_ALL_OUT_EN, + V_MIPI_OUT_EN(1) | V_DUAL_MIPI_EN(1)); dsp_out_mode = 0; break; case VOP_MODE_EDP: default: - clrsetbits_le32(&preg->sys_ctrl, - M_ALL_OUT_EN, V_EDP_OUT_EN(1)); + clrsetbits32(&preg->sys_ctrl, + M_ALL_OUT_EN, V_EDP_OUT_EN(1)); dsp_out_mode = 15; break; } - clrsetbits_le32(&preg->dsp_ctrl0, - M_DSP_OUT_MODE | M_DSP_VSYNC_POL | - M_DSP_HSYNC_POL, - V_DSP_OUT_MODE(dsp_out_mode) | - V_DSP_HSYNC_POL(edid->mode.phsync == '+') | - V_DSP_VSYNC_POL(edid->mode.pvsync == '+')); + clrsetbits32(&preg->dsp_ctrl0, + M_DSP_OUT_MODE | M_DSP_VSYNC_POL | + M_DSP_HSYNC_POL, + V_DSP_OUT_MODE(dsp_out_mode) | + V_DSP_HSYNC_POL(edid->mode.phsync == '+') | + V_DSP_VSYNC_POL(edid->mode.pvsync == '+')); write32(&preg->dsp_htotal_hs_end, V_HSYNC(hsync_len) | V_HORPRD(hsync_len + hback_porch + hactive + hfront_porch)); diff --git a/src/soc/rockchip/rk3288/hdmi.c b/src/soc/rockchip/rk3288/hdmi.c index b4de270fc5..6569d295ea 100644 --- a/src/soc/rockchip/rk3288/hdmi.c +++ b/src/soc/rockchip/rk3288/hdmi.c @@ -250,8 +250,8 @@ static void hdmi_update_csc_coeffs(void) } } - clrsetbits_le32(&hdmi_regs->csc_scale, HDMI_CSC_SCALE_CSCSCALE_MASK, - csc_scale); + clrsetbits32(&hdmi_regs->csc_scale, HDMI_CSC_SCALE_CSCSCALE_MASK, + csc_scale); } static void hdmi_video_csc(void) @@ -261,8 +261,8 @@ static void hdmi_video_csc(void) /* configure the csc registers */ write32(&hdmi_regs->csc_cfg, interpolation); - clrsetbits_le32(&hdmi_regs->csc_scale, - HDMI_CSC_SCALE_CSC_COLORDE_PTH_MASK, color_depth); + clrsetbits32(&hdmi_regs->csc_scale, + HDMI_CSC_SCALE_CSC_COLORDE_PTH_MASK, color_depth); hdmi_update_csc_coeffs(); } @@ -281,18 +281,18 @@ static void hdmi_video_packetize(void) HDMI_VP_PR_CD_DESIRED_PR_FACTOR_MASK); write32(&hdmi_regs->vp_pr_cd, val); - clrsetbits_le32(&hdmi_regs->vp_stuff, HDMI_VP_STUFF_PR_STUFFING_MASK, - HDMI_VP_STUFF_PR_STUFFING_STUFFING_MODE); + clrsetbits32(&hdmi_regs->vp_stuff, HDMI_VP_STUFF_PR_STUFFING_MASK, + HDMI_VP_STUFF_PR_STUFFING_STUFFING_MODE); /* data from pixel repeater block */ vp_conf = HDMI_VP_CONF_PR_EN_DISABLE | HDMI_VP_CONF_BYPASS_SELECT_VID_PACKETIZER; - clrsetbits_le32(&hdmi_regs->vp_conf, HDMI_VP_CONF_PR_EN_MASK | - HDMI_VP_CONF_BYPASS_SELECT_MASK, vp_conf); + clrsetbits32(&hdmi_regs->vp_conf, HDMI_VP_CONF_PR_EN_MASK | + HDMI_VP_CONF_BYPASS_SELECT_MASK, vp_conf); - clrsetbits_le32(&hdmi_regs->vp_stuff, HDMI_VP_STUFF_IDEFAULT_PHASE_MASK, - 1 << HDMI_VP_STUFF_IDEFAULT_PHASE_OFFSET); + clrsetbits32(&hdmi_regs->vp_stuff, HDMI_VP_STUFF_IDEFAULT_PHASE_MASK, + 1 << HDMI_VP_STUFF_IDEFAULT_PHASE_OFFSET); write32(&hdmi_regs->vp_remap, remap_size); @@ -300,23 +300,23 @@ static void hdmi_video_packetize(void) HDMI_VP_CONF_PP_EN_DISABLE | HDMI_VP_CONF_YCC422_EN_DISABLE; - clrsetbits_le32(&hdmi_regs->vp_conf, HDMI_VP_CONF_BYPASS_EN_MASK | - HDMI_VP_CONF_PP_EN_ENMASK | HDMI_VP_CONF_YCC422_EN_MASK, - vp_conf); + clrsetbits32(&hdmi_regs->vp_conf, HDMI_VP_CONF_BYPASS_EN_MASK | + HDMI_VP_CONF_PP_EN_ENMASK | HDMI_VP_CONF_YCC422_EN_MASK, + vp_conf); - clrsetbits_le32(&hdmi_regs->vp_stuff, HDMI_VP_STUFF_PP_STUFFING_MASK | - HDMI_VP_STUFF_YCC422_STUFFING_MASK, - HDMI_VP_STUFF_PP_STUFFING_STUFFING_MODE | - HDMI_VP_STUFF_YCC422_STUFFING_STUFFING_MODE); + clrsetbits32(&hdmi_regs->vp_stuff, HDMI_VP_STUFF_PP_STUFFING_MASK | + HDMI_VP_STUFF_YCC422_STUFFING_MASK, + HDMI_VP_STUFF_PP_STUFFING_STUFFING_MODE | + HDMI_VP_STUFF_YCC422_STUFFING_STUFFING_MODE); - clrsetbits_le32(&hdmi_regs->vp_conf, HDMI_VP_CONF_OUTPUT_SELECTOR_MASK, - output_select); + clrsetbits32(&hdmi_regs->vp_conf, HDMI_VP_CONF_OUTPUT_SELECTOR_MASK, + output_select); } static inline void hdmi_phy_test_clear(u8 bit) { - clrsetbits_le32(&hdmi_regs->phy_tst0, HDMI_PHY_TST0_TSTCLR_MASK, - bit << HDMI_PHY_TST0_TSTCLR_OFFSET); + clrsetbits32(&hdmi_regs->phy_tst0, HDMI_PHY_TST0_TSTCLR_MASK, + bit << HDMI_PHY_TST0_TSTCLR_OFFSET); } static int hdmi_phy_wait_i2c_done(u32 msec) @@ -352,46 +352,46 @@ static void hdmi_phy_i2c_write(u16 data, u8 addr) static void hdmi_phy_enable_power(u8 enable) { - clrsetbits_le32(&hdmi_regs->phy_conf0, HDMI_PHY_CONF0_PDZ_MASK, - enable << HDMI_PHY_CONF0_PDZ_OFFSET); + clrsetbits32(&hdmi_regs->phy_conf0, HDMI_PHY_CONF0_PDZ_MASK, + enable << HDMI_PHY_CONF0_PDZ_OFFSET); } static void hdmi_phy_enable_tmds(u8 enable) { - clrsetbits_le32(&hdmi_regs->phy_conf0, HDMI_PHY_CONF0_ENTMDS_MASK, - enable << HDMI_PHY_CONF0_ENTMDS_OFFSET); + clrsetbits32(&hdmi_regs->phy_conf0, HDMI_PHY_CONF0_ENTMDS_MASK, + enable << HDMI_PHY_CONF0_ENTMDS_OFFSET); } static void hdmi_phy_enable_spare(u8 enable) { - clrsetbits_le32(&hdmi_regs->phy_conf0, HDMI_PHY_CONF0_SPARECTRL_MASK, - enable << HDMI_PHY_CONF0_SPARECTRL_OFFSET); + clrsetbits32(&hdmi_regs->phy_conf0, HDMI_PHY_CONF0_SPARECTRL_MASK, + enable << HDMI_PHY_CONF0_SPARECTRL_OFFSET); } static void hdmi_phy_gen2_pddq(u8 enable) { - clrsetbits_le32(&hdmi_regs->phy_conf0, HDMI_PHY_CONF0_GEN2_PDDQ_MASK, - enable << HDMI_PHY_CONF0_GEN2_PDDQ_OFFSET); + clrsetbits32(&hdmi_regs->phy_conf0, HDMI_PHY_CONF0_GEN2_PDDQ_MASK, + enable << HDMI_PHY_CONF0_GEN2_PDDQ_OFFSET); } static void hdmi_phy_gen2_txpwron(u8 enable) { - clrsetbits_le32(&hdmi_regs->phy_conf0, - HDMI_PHY_CONF0_GEN2_TXPWRON_MASK, - enable << HDMI_PHY_CONF0_GEN2_TXPWRON_OFFSET); + clrsetbits32(&hdmi_regs->phy_conf0, + HDMI_PHY_CONF0_GEN2_TXPWRON_MASK, + enable << HDMI_PHY_CONF0_GEN2_TXPWRON_OFFSET); } static void hdmi_phy_sel_data_en_pol(u8 enable) { - clrsetbits_le32(&hdmi_regs->phy_conf0, - HDMI_PHY_CONF0_SELDATAENPOL_MASK, - enable << HDMI_PHY_CONF0_SELDATAENPOL_OFFSET); + clrsetbits32(&hdmi_regs->phy_conf0, + HDMI_PHY_CONF0_SELDATAENPOL_MASK, + enable << HDMI_PHY_CONF0_SELDATAENPOL_OFFSET); } static void hdmi_phy_sel_interface_control(u8 enable) { - clrsetbits_le32(&hdmi_regs->phy_conf0, HDMI_PHY_CONF0_SELDIPIF_MASK, - enable << HDMI_PHY_CONF0_SELDIPIF_OFFSET); + clrsetbits32(&hdmi_regs->phy_conf0, HDMI_PHY_CONF0_SELDIPIF_MASK, + enable << HDMI_PHY_CONF0_SELDIPIF_OFFSET); } static int hdmi_phy_configure(u32 mpixelclock) @@ -723,8 +723,8 @@ static int hdmi_ddc_wait_i2c_done(int msec) static void hdmi_ddc_reset(void) { - clrsetbits_le32(&hdmi_regs->i2cm_softrstz, HDMI_I2CM_SOFTRSTZ, - HDMI_I2CM_SOFTRSTZ); + clrsetbits32(&hdmi_regs->i2cm_softrstz, HDMI_I2CM_SOFTRSTZ, + HDMI_I2CM_SOFTRSTZ); } static int hdmi_read_edid(int block, u8 *buff) @@ -737,7 +737,7 @@ static int hdmi_read_edid(int block, u8 *buff) /* set ddc i2c clk which devided from ddc_clk to 100khz */ write32(&hdmi_regs->i2cm_ss_scl_hcnt_0_addr, 0x7a); write32(&hdmi_regs->i2cm_ss_scl_lcnt_0_addr, 0x8d); - clrsetbits_le32(&hdmi_regs->i2cm_div, HDMI_I2CM_DIV_FAST_STD_MODE, + clrsetbits32(&hdmi_regs->i2cm_div, HDMI_I2CM_DIV_FAST_STD_MODE, HDMI_I2CM_DIV_STD_MODE); write32(&hdmi_regs->i2cm_slave, HDMI_I2CM_SLAVE_DDC_ADDR); @@ -751,13 +751,13 @@ static int hdmi_read_edid(int block, u8 *buff) write32(&hdmi_regs->i2cmess, shift + 8 * n); if (block == 0) - clrsetbits_le32(&hdmi_regs->i2cm_operation, - HDMI_I2CM_OPT_RD8, - HDMI_I2CM_OPT_RD8); + clrsetbits32(&hdmi_regs->i2cm_operation, + HDMI_I2CM_OPT_RD8, + HDMI_I2CM_OPT_RD8); else - clrsetbits_le32(&hdmi_regs->i2cm_operation, - HDMI_I2CM_OPT_RD8_EXT, - HDMI_I2CM_OPT_RD8_EXT); + clrsetbits32(&hdmi_regs->i2cm_operation, + HDMI_I2CM_OPT_RD8_EXT, + HDMI_I2CM_OPT_RD8_EXT); if (hdmi_ddc_wait_i2c_done(10)) { hdmi_ddc_reset(); diff --git a/src/soc/rockchip/rk3288/sdram.c b/src/soc/rockchip/rk3288/sdram.c index 74038b078e..3305263458 100644 --- a/src/soc/rockchip/rk3288/sdram.c +++ b/src/soc/rockchip/rk3288/sdram.c @@ -522,14 +522,14 @@ static void phy_pctrl_reset(struct rk3288_ddr_publ_regs *ddr_publ_regs, int i; rkclk_ddr_reset(channel, 1, 1); udelay(1); - clrbits_le32(&ddr_publ_regs->acdllcr, ACDLLCR_DLLSRST); + clrbits32(&ddr_publ_regs->acdllcr, ACDLLCR_DLLSRST); for (i = 0; i < 4; i++) - clrbits_le32(&ddr_publ_regs->datx8[i].dxdllcr, DXDLLCR_DLLSRST); + clrbits32(&ddr_publ_regs->datx8[i].dxdllcr, DXDLLCR_DLLSRST); udelay(10); - setbits_le32(&ddr_publ_regs->acdllcr, ACDLLCR_DLLSRST); + setbits32(&ddr_publ_regs->acdllcr, ACDLLCR_DLLSRST); for (i = 0; i < 4; i++) - setbits_le32(&ddr_publ_regs->datx8[i].dxdllcr, DXDLLCR_DLLSRST); + setbits32(&ddr_publ_regs->datx8[i].dxdllcr, DXDLLCR_DLLSRST); udelay(10); rkclk_ddr_reset(channel, 1, 0); @@ -544,23 +544,23 @@ static void phy_dll_bypass_set(struct rk3288_ddr_publ_regs *ddr_publ_regs, int i; if (freq <= 250*MHz) { if (freq <= 150*MHz) - clrbits_le32(&ddr_publ_regs->dllgcr, SBIAS_BYPASS); + clrbits32(&ddr_publ_regs->dllgcr, SBIAS_BYPASS); else - setbits_le32(&ddr_publ_regs->dllgcr, SBIAS_BYPASS); - setbits_le32(&ddr_publ_regs->acdllcr, ACDLLCR_DLLDIS); + setbits32(&ddr_publ_regs->dllgcr, SBIAS_BYPASS); + setbits32(&ddr_publ_regs->acdllcr, ACDLLCR_DLLDIS); for (i = 0; i < 4; i++) - setbits_le32(&ddr_publ_regs->datx8[i].dxdllcr, + setbits32(&ddr_publ_regs->datx8[i].dxdllcr, DXDLLCR_DLLDIS); - setbits_le32(&ddr_publ_regs->pir, PIR_DLLBYP); + setbits32(&ddr_publ_regs->pir, PIR_DLLBYP); } else { - clrbits_le32(&ddr_publ_regs->dllgcr, SBIAS_BYPASS); - clrbits_le32(&ddr_publ_regs->acdllcr, ACDLLCR_DLLDIS); + clrbits32(&ddr_publ_regs->dllgcr, SBIAS_BYPASS); + clrbits32(&ddr_publ_regs->acdllcr, ACDLLCR_DLLDIS); for (i = 0; i < 4; i++) - clrbits_le32(&ddr_publ_regs->datx8[i].dxdllcr, + clrbits32(&ddr_publ_regs->datx8[i].dxdllcr, DXDLLCR_DLLDIS); - clrbits_le32(&ddr_publ_regs->pir, PIR_DLLBYP); + clrbits32(&ddr_publ_regs->pir, PIR_DLLBYP); } } @@ -637,7 +637,7 @@ static void pctl_cfg(u32 channel, break; } - setbits_le32(&ddr_pctl_regs->scfg, 1); + setbits32(&ddr_pctl_regs->scfg, 1); } static void phy_cfg(u32 channel, const struct rk3288_sdram_params *sdram_params) @@ -668,33 +668,33 @@ static void phy_cfg(u32 channel, const struct rk3288_sdram_params *sdram_params) switch (sdram_params->dramtype) { case LPDDR3: - clrsetbits_le32(&ddr_publ_regs->pgcr, 0x1F, PGCR_DFTLMT(0) + clrsetbits32(&ddr_publ_regs->pgcr, 0x1F, PGCR_DFTLMT(0) | PGCR_DFTCMP(0) | PGCR_DQSCFG(1) | PGCR_ITMDMD(0)); /* DDRMODE select LPDDR3 */ - clrsetbits_le32(&ddr_publ_regs->dcr, DDRMD_MSK, + clrsetbits32(&ddr_publ_regs->dcr, DDRMD_MSK, DDRMD_CFG(DDRMD_LPDDR2_LPDDR3)); - clrsetbits_le32(&ddr_publ_regs->dxccr, DQSNRES_MSK | DQSRES_MSK, + clrsetbits32(&ddr_publ_regs->dxccr, DQSNRES_MSK | DQSRES_MSK, DQSRES_CFG(4) | DQSNRES_CFG(0xc)); i = TDQSCKMAX_VAL(read32(&ddr_publ_regs->dtpr[1])) - TDQSCK_VAL(read32(&ddr_publ_regs->dtpr[1])); - clrsetbits_le32(&ddr_publ_regs->dsgcr, DQSGE_MSK | DQSGX_MSK, + clrsetbits32(&ddr_publ_regs->dsgcr, DQSGE_MSK | DQSGX_MSK, DQSGE_CFG(i) | DQSGX_CFG(i)); break; case DDR3: - clrbits_le32(&ddr_publ_regs->pgcr, 0x1f); - clrsetbits_le32(&ddr_publ_regs->dcr, DDRMD_MSK, + clrbits32(&ddr_publ_regs->pgcr, 0x1f); + clrsetbits32(&ddr_publ_regs->dcr, DDRMD_MSK, DDRMD_CFG(DDRMD_DDR3)); break; } if (sdram_params->odt) { /*dynamic RTT enable */ for (i = 0; i < 4; i++) - setbits_le32(&ddr_publ_regs->datx8[i].dxgcr, + setbits32(&ddr_publ_regs->datx8[i].dxgcr, DQSRTT | DQRTT); } else { /*dynamic RTT disable */ for (i = 0; i < 4; i++) - clrbits_le32(&ddr_publ_regs->datx8[i].dxgcr, + clrbits32(&ddr_publ_regs->datx8[i].dxgcr, DQSRTT | DQRTT); } @@ -702,7 +702,7 @@ static void phy_cfg(u32 channel, const struct rk3288_sdram_params *sdram_params) static void phy_init(struct rk3288_ddr_publ_regs *ddr_publ_regs) { - setbits_le32(&ddr_publ_regs->pir, PIR_INIT | PIR_DLLSRST + setbits32(&ddr_publ_regs->pir, PIR_INIT | PIR_DLLSRST | PIR_DLLLOCK | PIR_ZCAL | PIR_ITMSRST | PIR_CLRSR); udelay(1); while ((read32(&ddr_publ_regs->pgsr) & @@ -723,10 +723,10 @@ static void send_command(struct rk3288_ddr_pctl_regs *ddr_pctl_regs, u32 rank, static void memory_init(struct rk3288_ddr_publ_regs *ddr_publ_regs, u32 dramtype) { - setbits_le32(&ddr_publ_regs->pir, - (PIR_INIT | PIR_DRAMINIT | PIR_LOCKBYP - | PIR_ZCALBYP | PIR_CLRSR | PIR_ICPC - | (dramtype == DDR3 ? PIR_DRAMRST : 0))); + setbits32(&ddr_publ_regs->pir, + (PIR_INIT | PIR_DRAMINIT | PIR_LOCKBYP + | PIR_ZCALBYP | PIR_CLRSR | PIR_ICPC + | (dramtype == DDR3 ? PIR_DRAMRST : 0))); udelay(1); while ((read32(&ddr_publ_regs->pgsr) & (PGSR_IDONE | PGSR_DLDONE)) != (PGSR_IDONE | PGSR_DLDONE)) @@ -775,42 +775,42 @@ static void set_bandwidth_ratio(u32 channel, u32 n) struct rk3288_msch_regs *msch_regs = rk3288_msch[channel]; if (n == 1) { - setbits_le32(&ddr_pctl_regs->ppcfg, 1); + setbits32(&ddr_pctl_regs->ppcfg, 1); write32(&rk3288_grf->soc_con0, RK_SETBITS(1 << (8 + channel))); - setbits_le32(&msch_regs->ddrtiming, 1 << 31); + setbits32(&msch_regs->ddrtiming, 1 << 31); /* Data Byte disable*/ - clrbits_le32(&ddr_publ_regs->datx8[2].dxgcr, 1); - clrbits_le32(&ddr_publ_regs->datx8[3].dxgcr, 1); + clrbits32(&ddr_publ_regs->datx8[2].dxgcr, 1); + clrbits32(&ddr_publ_regs->datx8[3].dxgcr, 1); /*disable DLL */ - setbits_le32(&ddr_publ_regs->datx8[2].dxdllcr, + setbits32(&ddr_publ_regs->datx8[2].dxdllcr, DXDLLCR_DLLDIS); - setbits_le32(&ddr_publ_regs->datx8[3].dxdllcr, + setbits32(&ddr_publ_regs->datx8[3].dxdllcr, DXDLLCR_DLLDIS); } else { - clrbits_le32(&ddr_pctl_regs->ppcfg, 1); + clrbits32(&ddr_pctl_regs->ppcfg, 1); write32(&rk3288_grf->soc_con0, RK_CLRBITS(1 << (8 + channel))); - clrbits_le32(&msch_regs->ddrtiming, 1 << 31); + clrbits32(&msch_regs->ddrtiming, 1 << 31); /* Data Byte enable*/ - setbits_le32(&ddr_publ_regs->datx8[2].dxgcr, 1); - setbits_le32(&ddr_publ_regs->datx8[3].dxgcr, 1); + setbits32(&ddr_publ_regs->datx8[2].dxgcr, 1); + setbits32(&ddr_publ_regs->datx8[3].dxgcr, 1); /*enable DLL */ - clrbits_le32(&ddr_publ_regs->datx8[2].dxdllcr, + clrbits32(&ddr_publ_regs->datx8[2].dxdllcr, DXDLLCR_DLLDIS); - clrbits_le32(&ddr_publ_regs->datx8[3].dxdllcr, + clrbits32(&ddr_publ_regs->datx8[3].dxdllcr, DXDLLCR_DLLDIS); /* reset DLL */ - clrbits_le32(&ddr_publ_regs->datx8[2].dxdllcr, + clrbits32(&ddr_publ_regs->datx8[2].dxdllcr, DXDLLCR_DLLSRST); - clrbits_le32(&ddr_publ_regs->datx8[3].dxdllcr, + clrbits32(&ddr_publ_regs->datx8[3].dxdllcr, DXDLLCR_DLLSRST); udelay(10); - setbits_le32(&ddr_publ_regs->datx8[2].dxdllcr, + setbits32(&ddr_publ_regs->datx8[2].dxdllcr, DXDLLCR_DLLSRST); - setbits_le32(&ddr_publ_regs->datx8[3].dxdllcr, + setbits32(&ddr_publ_regs->datx8[3].dxdllcr, DXDLLCR_DLLSRST); } - setbits_le32(&ddr_pctl_regs->dfistcfg0, 1 << 2); + setbits32(&ddr_pctl_regs->dfistcfg0, 1 << 2); } @@ -829,19 +829,19 @@ static int data_training(u32 channel, write32(&ddr_pctl_regs->trefi, 0); if (sdram_params->dramtype != LPDDR3) - setbits_le32(&ddr_publ_regs->pgcr, PGCR_DQSCFG(1)); + setbits32(&ddr_publ_regs->pgcr, PGCR_DQSCFG(1)); rank = sdram_params->ch[channel].rank | 1; for (j = 0; j < ARRAY_SIZE(step); j++) { /* * trigger QSTRN and RVTRN * clear DTDONE status */ - setbits_le32(&ddr_publ_regs->pir, PIR_CLRSR); + setbits32(&ddr_publ_regs->pir, PIR_CLRSR); /* trigger DTT */ - setbits_le32(&ddr_publ_regs->pir, - PIR_INIT | step[j] | PIR_LOCKBYP | PIR_ZCALBYP | - PIR_CLRSR); + setbits32(&ddr_publ_regs->pir, + PIR_INIT | step[j] | PIR_LOCKBYP | PIR_ZCALBYP | + PIR_CLRSR); udelay(1); /* wait echo byte DTDONE */ while ((read32(&ddr_publ_regs->datx8[0].dxgsr[0]) & rank) @@ -869,7 +869,7 @@ static int data_training(u32 channel, send_command(ddr_pctl_regs, rank, REF_CMD, 0); if (sdram_params->dramtype != LPDDR3) - clrbits_le32(&ddr_publ_regs->pgcr, PGCR_DQSCFG(1)); + clrbits32(&ddr_publ_regs->pgcr, PGCR_DQSCFG(1)); /* resume auto refresh */ write32(&ddr_pctl_regs->trefi, sdram_params->pctl_timing.trefi); @@ -928,9 +928,9 @@ static void dram_cfg_rbc(u32 chnum, struct rk3288_msch_regs *msch_regs = rk3288_msch[chnum]; if (sdram_params->ch[chnum].bk == 3) - clrsetbits_le32(&ddr_publ_regs->dcr, PDQ_MSK, PDQ_CFG(1)); + clrsetbits32(&ddr_publ_regs->dcr, PDQ_MSK, PDQ_CFG(1)); else - clrbits_le32(&ddr_publ_regs->dcr, PDQ_MSK); + clrbits32(&ddr_publ_regs->dcr, PDQ_MSK); write32(&msch_regs->ddrconf, sdram_params->ddrconfig); } @@ -1029,8 +1029,8 @@ void sdram_init(const struct rk3288_sdram_params *sdram_params) * CS1, n=2 * CS0 & CS1, n = 3 */ - clrsetbits_le32(&ddr_publ_regs->pgcr, 0xF << 18, - (sdram_params->ch[channel].rank | 1) << 18); + clrsetbits32(&ddr_publ_regs->pgcr, 0xF << 18, + (sdram_params->ch[channel].rank | 1) << 18); /* DS=40ohm,ODT=155ohm */ zqcr = ZDEN(1) | PU_ONDIE(0x2) | PD_ONDIE(0x2) | PU_OUTPUT(0x19) | PD_OUTPUT(0x19); diff --git a/src/soc/rockchip/rk3288/software_i2c.c b/src/soc/rockchip/rk3288/software_i2c.c index 8c439842c1..67fca1f624 100644 --- a/src/soc/rockchip/rk3288/software_i2c.c +++ b/src/soc/rockchip/rk3288/software_i2c.c @@ -73,8 +73,8 @@ void software_i2c_attach(unsigned int bus) /* Mux pins to GPIO function for software I2C emulation. */ switch (bus) { case 0: - clrbits_le32(&rk3288_pmu->iomux_i2c0scl, IOMUX_I2C0SCL); - clrbits_le32(&rk3288_pmu->iomux_i2c0sda, IOMUX_I2C0SDA); + clrbits32(&rk3288_pmu->iomux_i2c0scl, IOMUX_I2C0SCL); + clrbits32(&rk3288_pmu->iomux_i2c0sda, IOMUX_I2C0SDA); break; case 1: write32(&rk3288_grf->iomux_i2c1, IOMUX_GPIO(IOMUX_I2C1)); @@ -108,8 +108,8 @@ void software_i2c_detach(unsigned int bus) /* Mux pins back to hardware I2C controller. */ switch (bus) { case 0: - setbits_le32(&rk3288_pmu->iomux_i2c0scl, IOMUX_I2C0SCL); - setbits_le32(&rk3288_pmu->iomux_i2c0sda, IOMUX_I2C0SDA); + setbits32(&rk3288_pmu->iomux_i2c0scl, IOMUX_I2C0SCL); + setbits32(&rk3288_pmu->iomux_i2c0sda, IOMUX_I2C0SDA); break; case 1: write32(&rk3288_grf->iomux_i2c1, IOMUX_I2C1); diff --git a/src/soc/rockchip/rk3288/tsadc.c b/src/soc/rockchip/rk3288/tsadc.c index 3223a4ddd4..e0649754b4 100644 --- a/src/soc/rockchip/rk3288/tsadc.c +++ b/src/soc/rockchip/rk3288/tsadc.c @@ -81,9 +81,9 @@ void tsadc_init(void) { rkclk_configure_tsadc(TSADC_CLOCK_HZ); - setbits_le32(&rk3288_tsadc->auto_con, LAST_TSHUT); + setbits32(&rk3288_tsadc->auto_con, LAST_TSHUT); - setbits_le32(&rk3288_tsadc->int_en, + setbits32(&rk3288_tsadc->int_en, TSHUT_CRU_EN_SRC2 | TSHUT_CRU_EN_SRC1 | TSHUT_GPIO_EN_SRC2 | TSHUT_GPIO_EN_SRC1); @@ -96,7 +96,7 @@ void tsadc_init(void) write32(&rk3288_tsadc->comp2_shut, TSADC_SHUT_VALUE); /* polarity set to high,channel1 for cpu,channel2 for gpu */ - setbits_le32(&rk3288_tsadc->auto_con, TSHUT_POL_HIGH | SRC2_EN | + setbits32(&rk3288_tsadc->auto_con, TSHUT_POL_HIGH | SRC2_EN | SRC1_EN | AUTO_EN); /* @@ -104,5 +104,5 @@ void tsadc_init(void) since the tshut polarity defalut low active, so if you enable tsadc iomux,it will output high */ - setbits_le32(&rk3288_pmu->iomux_tsadc_int, IOMUX_TSADC_INT); + setbits32(&rk3288_pmu->iomux_tsadc_int, IOMUX_TSADC_INT); } diff --git a/src/soc/rockchip/rk3399/clock.c b/src/soc/rockchip/rk3399/clock.c index 5252232f39..f9c49c33d7 100644 --- a/src/soc/rockchip/rk3399/clock.c +++ b/src/soc/rockchip/rk3399/clock.c @@ -374,9 +374,9 @@ static void rkclk_set_dpllssc(struct pll_div *dpll_cfg) write32(&cru_ptr->dpll_con[3], RK_CLRSETBITS(PLL_DSMPD_MASK << PLL_DSMPD_SHIFT, PLL_FRAC_MODE << PLL_DSMPD_SHIFT)); - clrsetbits_le32(&cru_ptr->dpll_con[2], - PLL_FRACDIV_MASK << PLL_FRACDIV_SHIFT, - 0 << PLL_FRACDIV_SHIFT); + clrsetbits32(&cru_ptr->dpll_con[2], + PLL_FRACDIV_MASK << PLL_FRACDIV_SHIFT, + 0 << PLL_FRACDIV_SHIFT); /* * Configure SSC divval. diff --git a/src/soc/rockchip/rk3399/saradc.c b/src/soc/rockchip/rk3399/saradc.c index 3c6cbe648f..358bb6a7e0 100644 --- a/src/soc/rockchip/rk3399/saradc.c +++ b/src/soc/rockchip/rk3399/saradc.c @@ -60,15 +60,15 @@ u32 get_saradc_value(u32 chn) rkclk_configure_saradc(SARADC_HZ); /* power down adc converter */ - clrbits_le32(&rk3399_saradc->ctrl, ADC_PWR_CTRL); + clrbits32(&rk3399_saradc->ctrl, ADC_PWR_CTRL); /* select channel */ - clrsetbits_le32(&rk3399_saradc->ctrl, - ADC_CHN_SEL_MASK << ADC_CHN_SEL_SHIFT, - chn << ADC_CHN_SEL_SHIFT); + clrsetbits32(&rk3399_saradc->ctrl, + ADC_CHN_SEL_MASK << ADC_CHN_SEL_SHIFT, + chn << ADC_CHN_SEL_SHIFT); /* power up */ - setbits_le32(&rk3399_saradc->ctrl, ADC_PWR_CTRL); + setbits32(&rk3399_saradc->ctrl, ADC_PWR_CTRL); udelay(SARADC_DELAY_PU); diff --git a/src/soc/rockchip/rk3399/sdram.c b/src/soc/rockchip/rk3399/sdram.c index 0e8cda60d7..3fe22f2502 100644 --- a/src/soc/rockchip/rk3399/sdram.c +++ b/src/soc/rockchip/rk3399/sdram.c @@ -120,26 +120,26 @@ static void phy_dll_bypass_set(u32 channel, if (freq <= 125*MHz) { /* phy_sw_master_mode_X PHY_86/214/342/470 4bits offset_8 */ - setbits_le32(&denali_phy[86], (0x3 << 2) << 8); - setbits_le32(&denali_phy[214], (0x3 << 2) << 8); - setbits_le32(&denali_phy[342], (0x3 << 2) << 8); - setbits_le32(&denali_phy[470], (0x3 << 2) << 8); + setbits32(&denali_phy[86], (0x3 << 2) << 8); + setbits32(&denali_phy[214], (0x3 << 2) << 8); + setbits32(&denali_phy[342], (0x3 << 2) << 8); + setbits32(&denali_phy[470], (0x3 << 2) << 8); /* phy_adrctl_sw_master_mode PHY_547/675/803 4bits offset_16 */ - setbits_le32(&denali_phy[547], (0x3 << 2) << 16); - setbits_le32(&denali_phy[675], (0x3 << 2) << 16); - setbits_le32(&denali_phy[803], (0x3 << 2) << 16); + setbits32(&denali_phy[547], (0x3 << 2) << 16); + setbits32(&denali_phy[675], (0x3 << 2) << 16); + setbits32(&denali_phy[803], (0x3 << 2) << 16); } else { /* phy_sw_master_mode_X PHY_86/214/342/470 4bits offset_8 */ - clrbits_le32(&denali_phy[86], (0x3 << 2) << 8); - clrbits_le32(&denali_phy[214], (0x3 << 2) << 8); - clrbits_le32(&denali_phy[342], (0x3 << 2) << 8); - clrbits_le32(&denali_phy[470], (0x3 << 2) << 8); + clrbits32(&denali_phy[86], (0x3 << 2) << 8); + clrbits32(&denali_phy[214], (0x3 << 2) << 8); + clrbits32(&denali_phy[342], (0x3 << 2) << 8); + clrbits32(&denali_phy[470], (0x3 << 2) << 8); /* phy_adrctl_sw_master_mode PHY_547/675/803 4bits offset_16 */ - clrbits_le32(&denali_phy[547], (0x3 << 2) << 16); - clrbits_le32(&denali_phy[675], (0x3 << 2) << 16); - clrbits_le32(&denali_phy[803], (0x3 << 2) << 16); + clrbits32(&denali_phy[547], (0x3 << 2) << 16); + clrbits32(&denali_phy[675], (0x3 << 2) << 16); + clrbits32(&denali_phy[803], (0x3 << 2) << 16); } } @@ -164,23 +164,23 @@ static void set_memory_map(u32 channel, cs_map = (sdram_ch->rank > 1) ? 3 : 1; reduc = (sdram_ch->bw == 2) ? 0 : 1; - clrsetbits_le32(&denali_ctl[191], 0xF, (12 - sdram_ch->col)); - clrsetbits_le32(&denali_ctl[190], (0x3 << 16) | (0x7 << 24), - ((3 - sdram_ch->bk) << 16) | - ((16 - row) << 24)); + clrsetbits32(&denali_ctl[191], 0xF, (12 - sdram_ch->col)); + clrsetbits32(&denali_ctl[190], (0x3 << 16) | (0x7 << 24), + ((3 - sdram_ch->bk) << 16) | + ((16 - row) << 24)); - clrsetbits_le32(&denali_ctl[196], 0x3 | (1 << 16), - cs_map | (reduc << 16)); + clrsetbits32(&denali_ctl[196], 0x3 | (1 << 16), + cs_map | (reduc << 16)); /* PI_199 PI_COL_DIFF:RW:0:4 */ - clrsetbits_le32(&denali_pi[199], 0xF, (12 - sdram_ch->col)); + clrsetbits32(&denali_pi[199], 0xF, (12 - sdram_ch->col)); /* PI_155 PI_ROW_DIFF:RW:24:3 PI_BANK_DIFF:RW:16:2 */ - clrsetbits_le32(&denali_pi[155], (0x3 << 16) | (0x7 << 24), - ((3 - sdram_ch->bk) << 16) | - ((16 - row) << 24)); + clrsetbits32(&denali_pi[155], (0x3 << 16) | (0x7 << 24), + ((3 - sdram_ch->bk) << 16) | + ((16 - row) << 24)); /* PI_41 PI_CS_MAP:RW:24:4 */ - clrsetbits_le32(&denali_pi[41], 0xf << 24, cs_map << 24); + clrsetbits32(&denali_pi[41], 0xf << 24, cs_map << 24); if ((sdram_ch->rank == 1) && (sdram_params->dramtype == DDR3)) write32(&denali_pi[34], 0x2EC7FFFF); } @@ -244,84 +244,84 @@ static void set_ds_odt(u32 channel, reg_value = tsel_rd_select_n | (tsel_rd_select_p << 0x4) | (tsel_wr_select_n << 8) | (tsel_wr_select_p << 12) | (tsel_idle_select_n << 16) | (tsel_idle_select_p << 20); - clrsetbits_le32(&denali_phy[6], 0xffffff, reg_value); - clrsetbits_le32(&denali_phy[134], 0xffffff, reg_value); - clrsetbits_le32(&denali_phy[262], 0xffffff, reg_value); - clrsetbits_le32(&denali_phy[390], 0xffffff, reg_value); + clrsetbits32(&denali_phy[6], 0xffffff, reg_value); + clrsetbits32(&denali_phy[134], 0xffffff, reg_value); + clrsetbits32(&denali_phy[262], 0xffffff, reg_value); + clrsetbits32(&denali_phy[390], 0xffffff, reg_value); /* * phy_dqs_tsel_select_X 24bits DENALI_PHY_7/135/263/391 offset_0 * sets termination values for read/idle cycles and drive strength * for write cycles for DQS */ - clrsetbits_le32(&denali_phy[7], 0xffffff, reg_value); - clrsetbits_le32(&denali_phy[135], 0xffffff, reg_value); - clrsetbits_le32(&denali_phy[263], 0xffffff, reg_value); - clrsetbits_le32(&denali_phy[391], 0xffffff, reg_value); + clrsetbits32(&denali_phy[7], 0xffffff, reg_value); + clrsetbits32(&denali_phy[135], 0xffffff, reg_value); + clrsetbits32(&denali_phy[263], 0xffffff, reg_value); + clrsetbits32(&denali_phy[391], 0xffffff, reg_value); /* phy_adr_tsel_select_ 8bits DENALI_PHY_544/672/800 offset_0 */ reg_value = ca_tsel_wr_select_n | (ca_tsel_wr_select_p << 0x4); - clrsetbits_le32(&denali_phy[544], 0xff, reg_value); - clrsetbits_le32(&denali_phy[672], 0xff, reg_value); - clrsetbits_le32(&denali_phy[800], 0xff, reg_value); + clrsetbits32(&denali_phy[544], 0xff, reg_value); + clrsetbits32(&denali_phy[672], 0xff, reg_value); + clrsetbits32(&denali_phy[800], 0xff, reg_value); /* phy_pad_addr_drive 8bits DENALI_PHY_928 offset_0 */ - clrsetbits_le32(&denali_phy[928], 0xff, reg_value); + clrsetbits32(&denali_phy[928], 0xff, reg_value); /* phy_pad_rst_drive 8bits DENALI_PHY_937 offset_0 */ - clrsetbits_le32(&denali_phy[937], 0xff, reg_value); + clrsetbits32(&denali_phy[937], 0xff, reg_value); /* phy_pad_cke_drive 8bits DENALI_PHY_935 offset_0 */ - clrsetbits_le32(&denali_phy[935], 0xff, reg_value); + clrsetbits32(&denali_phy[935], 0xff, reg_value); /* phy_pad_cs_drive 8bits DENALI_PHY_939 offset_0 */ - clrsetbits_le32(&denali_phy[939], 0xff, reg_value); + clrsetbits32(&denali_phy[939], 0xff, reg_value); /* phy_pad_clk_drive 8bits DENALI_PHY_929 offset_0 */ - clrsetbits_le32(&denali_phy[929], 0xff, reg_value); + clrsetbits32(&denali_phy[929], 0xff, reg_value); /* phy_pad_fdbk_drive 23bit DENALI_PHY_924/925 */ - clrsetbits_le32(&denali_phy[924], 0xff, - tsel_wr_select_n | (tsel_wr_select_p << 4)); - clrsetbits_le32(&denali_phy[925], 0xff, - tsel_rd_select_n | (tsel_rd_select_p << 4)); + clrsetbits32(&denali_phy[924], 0xff, + tsel_wr_select_n | (tsel_wr_select_p << 4)); + clrsetbits32(&denali_phy[925], 0xff, + tsel_rd_select_n | (tsel_rd_select_p << 4)); /* phy_dq_tsel_enable_X 3bits DENALI_PHY_5/133/261/389 offset_16 */ reg_value = (tsel_rd_en | (tsel_wr_en << 1) | (tsel_idle_en << 2)) << 16; - clrsetbits_le32(&denali_phy[5], 0x7 << 16, reg_value); - clrsetbits_le32(&denali_phy[133], 0x7 << 16, reg_value); - clrsetbits_le32(&denali_phy[261], 0x7 << 16, reg_value); - clrsetbits_le32(&denali_phy[389], 0x7 << 16, reg_value); + clrsetbits32(&denali_phy[5], 0x7 << 16, reg_value); + clrsetbits32(&denali_phy[133], 0x7 << 16, reg_value); + clrsetbits32(&denali_phy[261], 0x7 << 16, reg_value); + clrsetbits32(&denali_phy[389], 0x7 << 16, reg_value); /* phy_dqs_tsel_enable_X 3bits DENALI_PHY_6/134/262/390 offset_24 */ reg_value = (tsel_rd_en | (tsel_wr_en << 1) | (tsel_idle_en << 2)) << 24; - clrsetbits_le32(&denali_phy[6], 0x7 << 24, reg_value); - clrsetbits_le32(&denali_phy[134], 0x7 << 24, reg_value); - clrsetbits_le32(&denali_phy[262], 0x7 << 24, reg_value); - clrsetbits_le32(&denali_phy[390], 0x7 << 24, reg_value); + clrsetbits32(&denali_phy[6], 0x7 << 24, reg_value); + clrsetbits32(&denali_phy[134], 0x7 << 24, reg_value); + clrsetbits32(&denali_phy[262], 0x7 << 24, reg_value); + clrsetbits32(&denali_phy[390], 0x7 << 24, reg_value); /* phy_adr_tsel_enable_ 1bit DENALI_PHY_518/646/774 offset_8 */ reg_value = tsel_wr_en << 8; - clrsetbits_le32(&denali_phy[518], 0x1 << 8, reg_value); - clrsetbits_le32(&denali_phy[646], 0x1 << 8, reg_value); - clrsetbits_le32(&denali_phy[774], 0x1 << 8, reg_value); + clrsetbits32(&denali_phy[518], 0x1 << 8, reg_value); + clrsetbits32(&denali_phy[646], 0x1 << 8, reg_value); + clrsetbits32(&denali_phy[774], 0x1 << 8, reg_value); /* phy_pad_addr_term tsel 1bit DENALI_PHY_933 offset_17 */ reg_value = tsel_wr_en << 17; - clrsetbits_le32(&denali_phy[933], 0x1 << 17, reg_value); + clrsetbits32(&denali_phy[933], 0x1 << 17, reg_value); /* * pad_rst/cke/cs/clk_term tsel 1bits * DENALI_PHY_938/936/940/934 offset_17 */ - clrsetbits_le32(&denali_phy[938], 0x1 << 17, reg_value); - clrsetbits_le32(&denali_phy[936], 0x1 << 17, reg_value); - clrsetbits_le32(&denali_phy[940], 0x1 << 17, reg_value); - clrsetbits_le32(&denali_phy[934], 0x1 << 17, reg_value); + clrsetbits32(&denali_phy[938], 0x1 << 17, reg_value); + clrsetbits32(&denali_phy[936], 0x1 << 17, reg_value); + clrsetbits32(&denali_phy[940], 0x1 << 17, reg_value); + clrsetbits32(&denali_phy[934], 0x1 << 17, reg_value); /* phy_pad_fdbk_term 1bit DENALI_PHY_930 offset_17 */ - clrsetbits_le32(&denali_phy[930], 0x1 << 17, reg_value); + clrsetbits32(&denali_phy[930], 0x1 << 17, reg_value); } static void phy_io_config(u32 channel, @@ -410,18 +410,18 @@ static void phy_io_config(u32 channel, reg_value = (vref_mode_dq << 9) | (0x1 << 8) | vref_value_dq; /* PHY_913 PHY_PAD_VREF_CTRL_DQ_0 12bits offset_8 */ - clrsetbits_le32(&denali_phy[913], 0xfff << 8, reg_value << 8); + clrsetbits32(&denali_phy[913], 0xfff << 8, reg_value << 8); /* PHY_914 PHY_PAD_VREF_CTRL_DQ_1 12bits offset_0 */ - clrsetbits_le32(&denali_phy[914], 0xfff, reg_value); + clrsetbits32(&denali_phy[914], 0xfff, reg_value); /* PHY_914 PHY_PAD_VREF_CTRL_DQ_2 12bits offset_16 */ - clrsetbits_le32(&denali_phy[914], 0xfff << 16, reg_value << 16); + clrsetbits32(&denali_phy[914], 0xfff << 16, reg_value << 16); /* PHY_915 PHY_PAD_VREF_CTRL_DQ_3 12bits offset_0 */ - clrsetbits_le32(&denali_phy[915], 0xfff, reg_value); + clrsetbits32(&denali_phy[915], 0xfff, reg_value); reg_value = (vref_mode_ac << 9) | (0x1 << 8) | vref_value_ac; /* PHY_915 PHY_PAD_VREF_CTRL_AC 12bits offset_16 */ - clrsetbits_le32(&denali_phy[915], 0xfff << 16, reg_value << 16); + clrsetbits32(&denali_phy[915], 0xfff << 16, reg_value << 16); if (sdram_params->dramtype == LPDDR4) mode_sel = 0x6; @@ -431,21 +431,21 @@ static void phy_io_config(u32 channel, mode_sel = 0x1; /* PHY_924 PHY_PAD_FDBK_DRIVE */ - clrsetbits_le32(&denali_phy[924], 0x7 << 15, mode_sel << 15); + clrsetbits32(&denali_phy[924], 0x7 << 15, mode_sel << 15); /* PHY_926 PHY_PAD_DATA_DRIVE */ - clrsetbits_le32(&denali_phy[926], 0x7 << 6, mode_sel << 6); + clrsetbits32(&denali_phy[926], 0x7 << 6, mode_sel << 6); /* PHY_927 PHY_PAD_DQS_DRIVE */ - clrsetbits_le32(&denali_phy[927], 0x7 << 6, mode_sel << 6); + clrsetbits32(&denali_phy[927], 0x7 << 6, mode_sel << 6); /* PHY_928 PHY_PAD_ADDR_DRIVE */ - clrsetbits_le32(&denali_phy[928], 0x7 << 14, mode_sel << 14); + clrsetbits32(&denali_phy[928], 0x7 << 14, mode_sel << 14); /* PHY_929 PHY_PAD_CLK_DRIVE */ - clrsetbits_le32(&denali_phy[929], 0x7 << 14, mode_sel << 14); + clrsetbits32(&denali_phy[929], 0x7 << 14, mode_sel << 14); /* PHY_935 PHY_PAD_CKE_DRIVE */ - clrsetbits_le32(&denali_phy[935], 0x7 << 14, mode_sel << 14); + clrsetbits32(&denali_phy[935], 0x7 << 14, mode_sel << 14); /* PHY_937 PHY_PAD_RST_DRIVE */ - clrsetbits_le32(&denali_phy[937], 0x7 << 14, mode_sel << 14); + clrsetbits32(&denali_phy[937], 0x7 << 14, mode_sel << 14); /* PHY_939 PHY_PAD_CS_DRIVE */ - clrsetbits_le32(&denali_phy[939], 0x7 << 14, mode_sel << 14); + clrsetbits32(&denali_phy[939], 0x7 << 14, mode_sel << 14); /* speed setting */ @@ -459,21 +459,21 @@ static void phy_io_config(u32 channel, speed = 0x3; /* PHY_924 PHY_PAD_FDBK_DRIVE */ - clrsetbits_le32(&denali_phy[924], 0x3 << 21, speed << 21); + clrsetbits32(&denali_phy[924], 0x3 << 21, speed << 21); /* PHY_926 PHY_PAD_DATA_DRIVE */ - clrsetbits_le32(&denali_phy[926], 0x3 << 9, speed << 9); + clrsetbits32(&denali_phy[926], 0x3 << 9, speed << 9); /* PHY_927 PHY_PAD_DQS_DRIVE */ - clrsetbits_le32(&denali_phy[927], 0x3 << 9, speed << 9); + clrsetbits32(&denali_phy[927], 0x3 << 9, speed << 9); /* PHY_928 PHY_PAD_ADDR_DRIVE */ - clrsetbits_le32(&denali_phy[928], 0x3 << 17, speed << 17); + clrsetbits32(&denali_phy[928], 0x3 << 17, speed << 17); /* PHY_929 PHY_PAD_CLK_DRIVE */ - clrsetbits_le32(&denali_phy[929], 0x3 << 17, speed << 17); + clrsetbits32(&denali_phy[929], 0x3 << 17, speed << 17); /* PHY_935 PHY_PAD_CKE_DRIVE */ - clrsetbits_le32(&denali_phy[935], 0x3 << 17, speed << 17); + clrsetbits32(&denali_phy[935], 0x3 << 17, speed << 17); /* PHY_937 PHY_PAD_RST_DRIVE */ - clrsetbits_le32(&denali_phy[937], 0x3 << 17, speed << 17); + clrsetbits32(&denali_phy[937], 0x3 << 17, speed << 17); /* PHY_939 PHY_PAD_CS_DRIVE */ - clrsetbits_le32(&denali_phy[939], 0x3 << 17, speed << 17); + clrsetbits32(&denali_phy[939], 0x3 << 17, speed << 17); } static int pctl_cfg(u32 channel, @@ -505,13 +505,13 @@ static int pctl_cfg(u32 channel, write32(&denali_phy[912], sdram_params->phy_regs.denali_phy[912]); pwrup_srefresh_exit = read32(&denali_ctl[68]) & PWRUP_SREFRESH_EXIT; - clrbits_le32(&denali_ctl[68], PWRUP_SREFRESH_EXIT); + clrbits32(&denali_ctl[68], PWRUP_SREFRESH_EXIT); /* PHY_DLL_RST_EN */ - clrsetbits_le32(&denali_phy[957], 0x3 << 24, 1 << 24); + clrsetbits32(&denali_phy[957], 0x3 << 24, 1 << 24); - setbits_le32(&denali_pi[0], START); - setbits_le32(&denali_ctl[0], START); + setbits32(&denali_pi[0], START); + setbits32(&denali_ctl[0], START); while (1) { tmp = read32(&denali_phy[920]); @@ -539,31 +539,31 @@ static int pctl_cfg(u32 channel, * dqs_tsel_wr_end[7:4] add Half cycle */ tmp = (read32(&denali_phy[84]) >> 8) & 0xff; - clrsetbits_le32(&denali_phy[84], 0xff << 8, (tmp + 0x10) << 8); + clrsetbits32(&denali_phy[84], 0xff << 8, (tmp + 0x10) << 8); tmp = (read32(&denali_phy[212]) >> 8) & 0xff; - clrsetbits_le32(&denali_phy[212], 0xff << 8, (tmp + 0x10) << 8); + clrsetbits32(&denali_phy[212], 0xff << 8, (tmp + 0x10) << 8); tmp = (read32(&denali_phy[340]) >> 8) & 0xff; - clrsetbits_le32(&denali_phy[340], 0xff << 8, (tmp + 0x10) << 8); + clrsetbits32(&denali_phy[340], 0xff << 8, (tmp + 0x10) << 8); tmp = (read32(&denali_phy[468]) >> 8) & 0xff; - clrsetbits_le32(&denali_phy[468], 0xff << 8, (tmp + 0x10) << 8); + clrsetbits32(&denali_phy[468], 0xff << 8, (tmp + 0x10) << 8); /* * phy_dqs_tsel_wr_timing_X 8bits DENALI_PHY_83/211/339/467 offset_8 * dq_tsel_wr_end[7:4] add Half cycle */ tmp = (read32(&denali_phy[83]) >> 16) & 0xff; - clrsetbits_le32(&denali_phy[83], 0xff << 16, (tmp + 0x10) << 16); + clrsetbits32(&denali_phy[83], 0xff << 16, (tmp + 0x10) << 16); tmp = (read32(&denali_phy[211]) >> 16) & 0xff; - clrsetbits_le32(&denali_phy[211], 0xff << 16, (tmp + 0x10) << 16); + clrsetbits32(&denali_phy[211], 0xff << 16, (tmp + 0x10) << 16); tmp = (read32(&denali_phy[339]) >> 16) & 0xff; - clrsetbits_le32(&denali_phy[339], 0xff << 16, (tmp + 0x10) << 16); + clrsetbits32(&denali_phy[339], 0xff << 16, (tmp + 0x10) << 16); tmp = (read32(&denali_phy[467]) >> 16) & 0xff; - clrsetbits_le32(&denali_phy[467], 0xff << 16, (tmp + 0x10) << 16); + clrsetbits32(&denali_phy[467], 0xff << 16, (tmp + 0x10) << 16); phy_io_config(channel, sdram_params); /* PHY_DLL_RST_EN */ - clrsetbits_le32(&denali_phy[957], 0x3 << 24, 0x2 << 24); + clrsetbits32(&denali_phy[957], 0x3 << 24, 0x2 << 24); /* FIXME: need to care ERROR bit */ stopwatch_init_msecs_expire(&sw, 100); @@ -572,8 +572,8 @@ static int pctl_cfg(u32 channel, return -1; } - clrsetbits_le32(&denali_ctl[68], PWRUP_SREFRESH_EXIT, - pwrup_srefresh_exit); + clrsetbits32(&denali_ctl[68], PWRUP_SREFRESH_EXIT, + pwrup_srefresh_exit); return 0; } @@ -587,10 +587,10 @@ static void select_per_cs_training_index(u32 channel, u32 rank) * PHY_8/136/264/392 * phy_per_cs_training_index_X 1bit offset_24 */ - clrsetbits_le32(&denali_phy[8], 0x1 << 24, rank << 24); - clrsetbits_le32(&denali_phy[136], 0x1 << 24, rank << 24); - clrsetbits_le32(&denali_phy[264], 0x1 << 24, rank << 24); - clrsetbits_le32(&denali_phy[392], 0x1 << 24, rank << 24); + clrsetbits32(&denali_phy[8], 0x1 << 24, rank << 24); + clrsetbits32(&denali_phy[136], 0x1 << 24, rank << 24); + clrsetbits32(&denali_phy[264], 0x1 << 24, rank << 24); + clrsetbits32(&denali_phy[392], 0x1 << 24, rank << 24); } } @@ -601,26 +601,26 @@ static void override_write_leveling_value(u32 channel) u32 byte; /* PHY_896 PHY_FREQ_SEL_MULTICAST_EN 1bit offset_0 */ - setbits_le32(&denali_phy[896], 1); + setbits32(&denali_phy[896], 1); /* * PHY_8/136/264/392 * phy_per_cs_training_multicast_en_X 1bit offset_16 */ - clrsetbits_le32(&denali_phy[8], 0x1 << 16, 1 << 16); - clrsetbits_le32(&denali_phy[136], 0x1 << 16, 1 << 16); - clrsetbits_le32(&denali_phy[264], 0x1 << 16, 1 << 16); - clrsetbits_le32(&denali_phy[392], 0x1 << 16, 1 << 16); + clrsetbits32(&denali_phy[8], 0x1 << 16, 1 << 16); + clrsetbits32(&denali_phy[136], 0x1 << 16, 1 << 16); + clrsetbits32(&denali_phy[264], 0x1 << 16, 1 << 16); + clrsetbits32(&denali_phy[392], 0x1 << 16, 1 << 16); for (byte = 0; byte < 4; byte++) - clrsetbits_le32(&denali_phy[63 + (128 * byte)], 0xffff << 16, + clrsetbits32(&denali_phy[63 + (128 * byte)], 0xffff << 16, 0x200 << 16); /* PHY_896 PHY_FREQ_SEL_MULTICAST_EN 1bit offset_0 */ - clrbits_le32(&denali_phy[896], 1); + clrbits32(&denali_phy[896], 1); /* CTL_200 ctrlupd_req 1bit offset_8 */ - clrsetbits_le32(&denali_ctl[200], 0x1 << 8, 0x1 << 8); + clrsetbits32(&denali_ctl[200], 0x1 << 8, 0x1 << 8); } static int data_training(u32 channel, @@ -635,7 +635,7 @@ static int data_training(u32 channel, u32 reg_value = 0; /* PHY_927 PHY_PAD_DQS_DRIVE RPULL offset_22 */ - setbits_le32(&denali_phy[927], (1 << 22)); + setbits32(&denali_phy[927], (1 << 22)); if (training_flag == PI_FULL_TRAINING) { if (sdram_params->dramtype == LPDDR4) { @@ -657,11 +657,11 @@ static int data_training(u32 channel, for (i = 0; i < rank; i++) { select_per_cs_training_index(channel, i); /* PI_100 PI_CALVL_EN:RW:8:2 */ - clrsetbits_le32(&denali_pi[100], 0x3 << 8, 0x2 << 8); + clrsetbits32(&denali_pi[100], 0x3 << 8, 0x2 << 8); /* PI_92 PI_CALVL_REQ:WR:16:1,PI_CALVL_CS:RW:24:2 */ - clrsetbits_le32(&denali_pi[92], - (0x1 << 16) | (0x3 << 24), - (0x1 << 16) | (i << 24)); + clrsetbits32(&denali_pi[92], + (0x1 << 16) | (0x3 << 24), + (0x1 << 16) | (i << 24)); while (1) { /* PI_174 PI_INT_STATUS:RD:8:18 */ @@ -690,7 +690,7 @@ static int data_training(u32 channel, /* clear interrupt,PI_175 PI_INT_ACK:WR:0:17 */ write32((&denali_pi[175]), 0x00003f7c); } - clrbits_le32(&denali_pi[100], 0x3 << 8); + clrbits32(&denali_pi[100], 0x3 << 8); } /* write leveling(LPDDR4,LPDDR3,DDR3 support) */ @@ -698,11 +698,11 @@ static int data_training(u32 channel, for (i = 0; i < rank; i++) { select_per_cs_training_index(channel, i); /* PI_60 PI_WRLVL_EN:RW:8:2 */ - clrsetbits_le32(&denali_pi[60], 0x3 << 8, 0x2 << 8); + clrsetbits32(&denali_pi[60], 0x3 << 8, 0x2 << 8); /* PI_59 PI_WRLVL_REQ:WR:8:1,PI_WRLVL_CS:RW:16:2 */ - clrsetbits_le32(&denali_pi[59], - (0x1 << 8) | (0x3 << 16), - (0x1 << 8) | (i << 16)); + clrsetbits32(&denali_pi[59], + (0x1 << 8) | (0x3 << 16), + (0x1 << 8) | (i << 16)); while (1) { /* PI_174 PI_INT_STATUS:RD:8:18 */ @@ -736,7 +736,7 @@ static int data_training(u32 channel, } override_write_leveling_value(channel); - clrbits_le32(&denali_pi[60], 0x3 << 8); + clrbits32(&denali_pi[60], 0x3 << 8); } /* read gate training(LPDDR4,LPDDR3,DDR3 support) */ @@ -758,22 +758,22 @@ static int data_training(u32 channel, * phy_dqs_tsel_enable_X 3bits * DENALI_PHY_6/134/262/390 offset_24 */ - clrbits_le32(&denali_phy[6], 0x7 << 24); - clrbits_le32(&denali_phy[134], 0x7 << 24); - clrbits_le32(&denali_phy[262], 0x7 << 24); - clrbits_le32(&denali_phy[390], 0x7 << 24); + clrbits32(&denali_phy[6], 0x7 << 24); + clrbits32(&denali_phy[134], 0x7 << 24); + clrbits32(&denali_phy[262], 0x7 << 24); + clrbits32(&denali_phy[390], 0x7 << 24); } for (i = 0; i < rank; i++) { select_per_cs_training_index(channel, i); /* PI_80 PI_RDLVL_GATE_EN:RW:24:2 */ - clrsetbits_le32(&denali_pi[80], 0x3 << 24, 0x2 << 24); + clrsetbits32(&denali_pi[80], 0x3 << 24, 0x2 << 24); /* * PI_74 PI_RDLVL_GATE_REQ:WR:16:1 * PI_RDLVL_CS:RW:24:2 */ - clrsetbits_le32(&denali_pi[74], - (0x1 << 16) | (0x3 << 24), - (0x1 << 16) | (i << 24)); + clrsetbits32(&denali_pi[74], + (0x1 << 16) | (0x3 << 24), + (0x1 << 16) | (i << 24)); while (1) { /* PI_174 PI_INT_STATUS:RD:8:18 */ @@ -805,7 +805,7 @@ static int data_training(u32 channel, /* clear interrupt,PI_175 PI_INT_ACK:WR:0:17 */ write32((&denali_pi[175]), 0x00003f7c); } - clrbits_le32(&denali_pi[80], 0x3 << 24); + clrbits32(&denali_pi[80], 0x3 << 24); if (sdram_params->dramtype != LPDDR4) { /* @@ -813,10 +813,10 @@ static int data_training(u32 channel, * DENALI_PHY_6/134/262/390 offset_24 */ tmp = reg_value << 24; - clrsetbits_le32(&denali_phy[6], 0x7 << 24, tmp); - clrsetbits_le32(&denali_phy[134], 0x7 << 24, tmp); - clrsetbits_le32(&denali_phy[262], 0x7 << 24, tmp); - clrsetbits_le32(&denali_phy[390], 0x7 << 24, tmp); + clrsetbits32(&denali_phy[6], 0x7 << 24, tmp); + clrsetbits32(&denali_phy[134], 0x7 << 24, tmp); + clrsetbits32(&denali_phy[262], 0x7 << 24, tmp); + clrsetbits32(&denali_phy[390], 0x7 << 24, tmp); } } @@ -825,11 +825,11 @@ static int data_training(u32 channel, for (i = 0; i < rank; i++) { select_per_cs_training_index(channel, i); /* PI_80 PI_RDLVL_EN:RW:16:2 */ - clrsetbits_le32(&denali_pi[80], 0x3 << 16, 0x2 << 16); + clrsetbits32(&denali_pi[80], 0x3 << 16, 0x2 << 16); /* PI_74 PI_RDLVL_REQ:WR:8:1,PI_RDLVL_CS:RW:24:2 */ - clrsetbits_le32(&denali_pi[74], - (0x1 << 8) | (0x3 << 24), - (0x1 << 8) | (i << 24)); + clrsetbits32(&denali_pi[74], + (0x1 << 8) | (0x3 << 24), + (0x1 << 8) | (i << 24)); while (1) { /* PI_174 PI_INT_STATUS:RD:8:18 */ @@ -850,7 +850,7 @@ static int data_training(u32 channel, /* clear interrupt,PI_175 PI_INT_ACK:WR:0:17 */ write32((&denali_pi[175]), 0x00003f7c); } - clrbits_le32(&denali_pi[80], 0x3 << 16); + clrbits32(&denali_pi[80], 0x3 << 16); } /* wdq leveling(LPDDR4 support) */ @@ -861,13 +861,13 @@ static int data_training(u32 channel, * disable PI_WDQLVL_VREF_EN before wdq leveling? * PI_181 PI_WDQLVL_VREF_EN:RW:8:1 */ - clrbits_le32(&denali_pi[181], 0x1 << 8); + clrbits32(&denali_pi[181], 0x1 << 8); /* PI_124 PI_WDQLVL_EN:RW:16:2 */ - clrsetbits_le32(&denali_pi[124], 0x3 << 16, 0x2 << 16); + clrsetbits32(&denali_pi[124], 0x3 << 16, 0x2 << 16); /* PI_121 PI_WDQLVL_REQ:WR:8:1,PI_WDQLVL_CS:RW:16:2 */ - clrsetbits_le32(&denali_pi[121], - (0x1 << 8) | (0x3 << 16), - (0x1 << 8) | (i << 16)); + clrsetbits32(&denali_pi[121], + (0x1 << 8) | (0x3 << 16), + (0x1 << 8) | (i << 16)); while (1) { /* PI_174 PI_INT_STATUS:RD:8:18 */ @@ -882,11 +882,11 @@ static int data_training(u32 channel, /* clear interrupt,PI_175 PI_INT_ACK:WR:0:17 */ write32((&denali_pi[175]), 0x00003f7c); } - clrbits_le32(&denali_pi[124], 0x3 << 16); + clrbits32(&denali_pi[124], 0x3 << 16); } /* PHY_927 PHY_PAD_DQS_DRIVE RPULL offset_22 */ - clrbits_le32(&denali_phy[927], (1 << 22)); + clrbits32(&denali_phy[927], (1 << 22)); return 0; } @@ -960,8 +960,8 @@ static void dram_all_config(const struct rk3399_sdram_params *sdram_params) /* rank 1 memory clock disable (dfi_dram_clk_disable = 1) */ if (sdram_params->ch[channel].rank == 1) - setbits_le32(&rk3399_ddr_pctl[channel]->denali_ctl[276], - 1 << 17); + setbits32(&rk3399_ddr_pctl[channel]->denali_ctl[276], + 1 << 17); } write32(&rk3399_pmugrf->os_reg2, sys_reg); @@ -971,7 +971,7 @@ static void dram_all_config(const struct rk3399_sdram_params *sdram_params) write32(&pmucru_ptr->pmucru_rstnhold_con[1], PRESET_SGRF_HOLD(0) | PRESET_GPIO0_HOLD(1) | PRESET_GPIO1_HOLD(1)); - clrsetbits_le32(&cru_ptr->glb_rst_con, 0x3, 0x3); + clrsetbits32(&cru_ptr->glb_rst_con, 0x3, 0x3); } static void switch_to_phy_index1(const struct rk3399_sdram_params *sdram_params) @@ -1005,7 +1005,7 @@ static void switch_to_phy_index1(const struct rk3399_sdram_params *sdram_params) for (channel = 0; channel < ch_count; channel++) { denali_phy = rk3399_ddr_publ[channel]->denali_phy; - clrsetbits_le32(&denali_phy[896], (0x3 << 8) | 1, 1 << 8); + clrsetbits32(&denali_phy[896], (0x3 << 8) | 1, 1 << 8); if (data_training(channel, sdram_params, PI_FULL_TRAINING)) { printk(BIOS_ERR, "index1 training failed, reset\n"); board_reset(); diff --git a/src/soc/rockchip/rk3399/tsadc.c b/src/soc/rockchip/rk3399/tsadc.c index 7ec24648a2..78ce1e366e 100644 --- a/src/soc/rockchip/rk3399/tsadc.c +++ b/src/soc/rockchip/rk3399/tsadc.c @@ -100,7 +100,7 @@ void tsadc_init(uint32_t polarity) rkclk_configure_tsadc(TSADC_CLOCK_HZ); /* tsadc power sequence */ - clrbits_le32(&rk3399_tsadc->user_con, ADC_POWER_CTRL); + clrbits32(&rk3399_tsadc->user_con, ADC_POWER_CTRL); write32(&rk3399_grf->tsadc_testbit_l, GRF_TSADC_TSEN_PD0_ON); udelay(50); write32(&rk3399_grf->tsadc_testbit_l, GRF_TSADC_TSEN_PD0_OFF); @@ -125,9 +125,9 @@ void tsadc_init(uint32_t polarity) write32(&rk3399_tsadc->auto_period_ht, AUTO_PERIOD_HT); write32(&rk3399_tsadc->hight_tshut_debounce, AUTO_DEBOUNCE_HT); /* Enable the src0, negative temprature coefficient */ - setbits_le32(&rk3399_tsadc->auto_con, Q_SEL | SRC0_EN); + setbits32(&rk3399_tsadc->auto_con, Q_SEL | SRC0_EN); udelay(100); - setbits_le32(&rk3399_tsadc->auto_con, AUTO_EN); + setbits32(&rk3399_tsadc->auto_con, AUTO_EN); write32(&rk3399_tsadc->comp0_shut, TSADC_SHUT_VALUE); write32(&rk3399_tsadc->int_en, TSHUT_CRU_EN_SRC0 | TSHUT_GPIO_EN_SRC0); diff --git a/src/soc/rockchip/rk3399/usb.c b/src/soc/rockchip/rk3399/usb.c index e016fbf7c1..434a99ef11 100644 --- a/src/soc/rockchip/rk3399/usb.c +++ b/src/soc/rockchip/rk3399/usb.c @@ -54,8 +54,8 @@ static void tcphy_cfg_24m(struct rk3399_tcphy *tcphy) write32(&tcphy->lane[i].tx_rcvdet_st_tmr, 0x30); } - clrsetbits_le32(&tcphy->cmn_diag_hsclk_sel, - TCPHY_CMN_HSCLK_PLL_MASK, TCPHY_CMN_HSCLK_PLL_CONFIG); + clrsetbits32(&tcphy->cmn_diag_hsclk_sel, + TCPHY_CMN_HSCLK_PLL_MASK, TCPHY_CMN_HSCLK_PLL_CONFIG); } static void tcphy_phy_init(struct rk3399_tcphy *tcphy) @@ -78,11 +78,11 @@ static void tcphy_phy_init(struct rk3399_tcphy *tcphy) static void reset_dwc3(struct rockchip_usb_dwc3 *dwc3) { /* Before Resetting PHY, put Core in Reset */ - setbits_le32(&dwc3->ctl, DWC3_GCTL_CORESOFTRESET); + setbits32(&dwc3->ctl, DWC3_GCTL_CORESOFTRESET); /* Assert USB3 PHY reset */ - setbits_le32(&dwc3->usb3pipectl, DWC3_GUSB3PIPECTL_PHYSOFTRST); + setbits32(&dwc3->usb3pipectl, DWC3_GUSB3PIPECTL_PHYSOFTRST); /* Assert USB2 PHY reset */ - setbits_le32(&dwc3->usb2phycfg, DWC3_GUSB2PHYCFG_PHYSOFTRST); + setbits32(&dwc3->usb2phycfg, DWC3_GUSB2PHYCFG_PHYSOFTRST); } static void setup_dwc3(struct rockchip_usb_dwc3 *dwc3) @@ -94,7 +94,7 @@ static void setup_dwc3(struct rockchip_usb_dwc3 *dwc3) assert(ctl & DWC3_GCTL_CORESOFTRESET); /* Clear USB3 PHY reset (oddly enough, this is really necessary). */ - clrbits_le32(&dwc3->usb3pipectl, DWC3_GUSB3PIPECTL_PHYSOFTRST); + clrbits32(&dwc3->usb3pipectl, DWC3_GUSB3PIPECTL_PHYSOFTRST); /* Clear USB2 PHY and core reset. */ usb2phycfg &= ~DWC3_GUSB2PHYCFG_PHYSOFTRST; diff --git a/src/soc/samsung/exynos5250/clock.c b/src/soc/samsung/exynos5250/clock.c index efb0de31f3..e762af1908 100644 --- a/src/soc/samsung/exynos5250/clock.c +++ b/src/soc/samsung/exynos5250/clock.c @@ -425,7 +425,7 @@ void clock_ll_set_pre_ratio(enum periph_id periph_id, unsigned int divisor) periph_id); return; } - clrsetbits_le32(reg, mask << shift, (divisor & mask) << shift); + clrsetbits32(reg, mask << shift, (divisor & mask) << shift); } void clock_ll_set_ratio(enum periph_id periph_id, unsigned int divisor) @@ -460,7 +460,7 @@ void clock_ll_set_ratio(enum periph_id periph_id, unsigned int divisor) periph_id); return; } - clrsetbits_le32(reg, mask << shift, (divisor & mask) << shift); + clrsetbits32(reg, mask << shift, (divisor & mask) << shift); } /** @@ -644,7 +644,7 @@ int clock_epll_set_rate(unsigned long rate) void clock_select_i2s_clk_source(void) { - clrsetbits_le32(&exynos_clock->src_peric1, AUDIO1_SEL_MASK, + clrsetbits32(&exynos_clock->src_peric1, AUDIO1_SEL_MASK, (CLK_SRC_SCLK_EPLL)); } @@ -664,7 +664,7 @@ int clock_set_i2s_clk_prescaler(unsigned int src_frq, unsigned int dst_frq) printk(BIOS_DEBUG, "src frq = %d des frq = %d ", src_frq, dst_frq); return -1; } - clrsetbits_le32(&exynos_clock->div_peric4, AUDIO_1_RATIO_MASK, + clrsetbits32(&exynos_clock->div_peric4, AUDIO_1_RATIO_MASK, (div & AUDIO_1_RATIO_MASK)); return 0; } diff --git a/src/soc/samsung/exynos5250/clock_init.c b/src/soc/samsung/exynos5250/clock_init.c index fa19eb1763..ca3dbd9921 100644 --- a/src/soc/samsung/exynos5250/clock_init.c +++ b/src/soc/samsung/exynos5250/clock_init.c @@ -28,27 +28,27 @@ void system_clock_init(struct mem_timings *mem, /* Turn on the MCT as early as possible. */ exynos_mct->g_tcon |= (1 << 8); - clrbits_le32(&exynos_clock->src_cpu, MUX_APLL_SEL_MASK); + clrbits32(&exynos_clock->src_cpu, MUX_APLL_SEL_MASK); do { val = read32(&exynos_clock->mux_stat_cpu); } while ((val | MUX_APLL_SEL_MASK) != val); - clrbits_le32(&exynos_clock->src_core1, MUX_MPLL_SEL_MASK); + clrbits32(&exynos_clock->src_core1, MUX_MPLL_SEL_MASK); do { val = read32(&exynos_clock->mux_stat_core1); } while ((val | MUX_MPLL_SEL_MASK) != val); - clrbits_le32(&exynos_clock->src_top2, MUX_CPLL_SEL_MASK); - clrbits_le32(&exynos_clock->src_top2, MUX_EPLL_SEL_MASK); - clrbits_le32(&exynos_clock->src_top2, MUX_VPLL_SEL_MASK); - clrbits_le32(&exynos_clock->src_top2, MUX_GPLL_SEL_MASK); + clrbits32(&exynos_clock->src_top2, MUX_CPLL_SEL_MASK); + clrbits32(&exynos_clock->src_top2, MUX_EPLL_SEL_MASK); + clrbits32(&exynos_clock->src_top2, MUX_VPLL_SEL_MASK); + clrbits32(&exynos_clock->src_top2, MUX_GPLL_SEL_MASK); tmp = MUX_CPLL_SEL_MASK | MUX_EPLL_SEL_MASK | MUX_VPLL_SEL_MASK | MUX_GPLL_SEL_MASK; do { val = read32(&exynos_clock->mux_stat_top2); } while ((val | tmp) != val); - clrbits_le32(&exynos_clock->src_cdrex, MUX_BPLL_SEL_MASK); + clrbits32(&exynos_clock->src_cdrex, MUX_BPLL_SEL_MASK); do { val = read32(&exynos_clock->mux_stat_cdrex); } while ((val | MUX_BPLL_SEL_MASK) != val); @@ -94,7 +94,7 @@ void system_clock_init(struct mem_timings *mem, } while (0 != val); /* switch A15 clock source to OSC clock before changing APLL */ - clrbits_le32(&exynos_clock->src_cpu, APLL_FOUT); + clrbits32(&exynos_clock->src_cpu, APLL_FOUT); /* Set APLL */ write32(&exynos_clock->apll_con1, APLL_CON1_VAL); @@ -105,7 +105,7 @@ void system_clock_init(struct mem_timings *mem, ; /* now it is safe to switch to APLL */ - setbits_le32(&exynos_clock->src_cpu, APLL_FOUT); + setbits32(&exynos_clock->src_cpu, APLL_FOUT); /* Set MPLL */ write32(&exynos_clock->mpll_con1, MPLL_CON1_VAL); @@ -118,7 +118,7 @@ void system_clock_init(struct mem_timings *mem, * Configure MUX_MPLL_FOUT to choose the direct clock source * path and avoid the fixed DIV/2 block to save power */ - setbits_le32(&exynos_clock->pll_div2_sel, MUX_MPLL_FOUT_SEL); + setbits32(&exynos_clock->pll_div2_sel, MUX_MPLL_FOUT_SEL); /* Set BPLL */ if (mem->use_bpll) { @@ -128,7 +128,7 @@ void system_clock_init(struct mem_timings *mem, while ((read32(&exynos_clock->bpll_con0) & BPLL_CON0_LOCKED) == 0) ; - setbits_le32(&exynos_clock->pll_div2_sel, MUX_BPLL_FOUT_SEL); + setbits32(&exynos_clock->pll_div2_sel, MUX_BPLL_FOUT_SEL); } /* Set CPLL */ @@ -280,124 +280,124 @@ void system_clock_init(struct mem_timings *mem, void clock_gate(void) { /* CLK_GATE_IP_SYSRGT */ - clrbits_le32(&exynos_clock->gate_ip_sysrgt, CLK_C2C_MASK); + clrbits32(&exynos_clock->gate_ip_sysrgt, CLK_C2C_MASK); /* CLK_GATE_IP_ACP */ - clrbits_le32(&exynos_clock->gate_ip_acp, CLK_SMMUG2D_MASK | - CLK_SMMUSSS_MASK | - CLK_SMMUMDMA_MASK | - CLK_ID_REMAPPER_MASK | - CLK_G2D_MASK | - CLK_SSS_MASK | - CLK_MDMA_MASK | - CLK_SECJTAG_MASK); + clrbits32(&exynos_clock->gate_ip_acp, CLK_SMMUG2D_MASK | + CLK_SMMUSSS_MASK | + CLK_SMMUMDMA_MASK | + CLK_ID_REMAPPER_MASK | + CLK_G2D_MASK | + CLK_SSS_MASK | + CLK_MDMA_MASK | + CLK_SECJTAG_MASK); /* CLK_GATE_BUS_SYSLFT */ - clrbits_le32(&exynos_clock->gate_bus_syslft, CLK_EFCLK_MASK); + clrbits32(&exynos_clock->gate_bus_syslft, CLK_EFCLK_MASK); /* CLK_GATE_IP_ISP0 */ - clrbits_le32(&exynos_clock->gate_ip_isp0, CLK_UART_ISP_MASK | - CLK_WDT_ISP_MASK | - CLK_PWM_ISP_MASK | - CLK_MTCADC_ISP_MASK | - CLK_I2C1_ISP_MASK | - CLK_I2C0_ISP_MASK | - CLK_MPWM_ISP_MASK | - CLK_MCUCTL_ISP_MASK | - CLK_INT_COMB_ISP_MASK | - CLK_SMMU_MCUISP_MASK | - CLK_SMMU_SCALERP_MASK | - CLK_SMMU_SCALERC_MASK | - CLK_SMMU_FD_MASK | - CLK_SMMU_DRC_MASK | - CLK_SMMU_ISP_MASK | - CLK_GICISP_MASK | - CLK_ARM9S_MASK | - CLK_MCUISP_MASK | - CLK_SCALERP_MASK | - CLK_SCALERC_MASK | - CLK_FD_MASK | - CLK_DRC_MASK | - CLK_ISP_MASK); + clrbits32(&exynos_clock->gate_ip_isp0, CLK_UART_ISP_MASK | + CLK_WDT_ISP_MASK | + CLK_PWM_ISP_MASK | + CLK_MTCADC_ISP_MASK | + CLK_I2C1_ISP_MASK | + CLK_I2C0_ISP_MASK | + CLK_MPWM_ISP_MASK | + CLK_MCUCTL_ISP_MASK | + CLK_INT_COMB_ISP_MASK | + CLK_SMMU_MCUISP_MASK | + CLK_SMMU_SCALERP_MASK | + CLK_SMMU_SCALERC_MASK | + CLK_SMMU_FD_MASK | + CLK_SMMU_DRC_MASK | + CLK_SMMU_ISP_MASK | + CLK_GICISP_MASK | + CLK_ARM9S_MASK | + CLK_MCUISP_MASK | + CLK_SCALERP_MASK | + CLK_SCALERC_MASK | + CLK_FD_MASK | + CLK_DRC_MASK | + CLK_ISP_MASK); /* CLK_GATE_IP_ISP1 */ - clrbits_le32(&exynos_clock->gate_ip_isp1, CLK_SPI1_ISP_MASK | - CLK_SPI0_ISP_MASK | - CLK_SMMU3DNR_MASK | - CLK_SMMUDIS1_MASK | - CLK_SMMUDIS0_MASK | - CLK_SMMUODC_MASK | - CLK_3DNR_MASK | - CLK_DIS_MASK | - CLK_ODC_MASK); + clrbits32(&exynos_clock->gate_ip_isp1, CLK_SPI1_ISP_MASK | + CLK_SPI0_ISP_MASK | + CLK_SMMU3DNR_MASK | + CLK_SMMUDIS1_MASK | + CLK_SMMUDIS0_MASK | + CLK_SMMUODC_MASK | + CLK_3DNR_MASK | + CLK_DIS_MASK | + CLK_ODC_MASK); /* CLK_GATE_SCLK_ISP */ - clrbits_le32(&exynos_clock->gate_sclk_isp, SCLK_MPWM_ISP_MASK); + clrbits32(&exynos_clock->gate_sclk_isp, SCLK_MPWM_ISP_MASK); /* CLK_GATE_IP_GSCL */ - clrbits_le32(&exynos_clock->gate_ip_gscl, CLK_SMMUFIMC_LITE2_MASK | - CLK_SMMUFIMC_LITE1_MASK | - CLK_SMMUFIMC_LITE0_MASK | - CLK_SMMUGSCL3_MASK | - CLK_SMMUGSCL2_MASK | - CLK_SMMUGSCL1_MASK | - CLK_SMMUGSCL0_MASK | - CLK_GSCL_WRAP_B_MASK | - CLK_GSCL_WRAP_A_MASK | - CLK_CAMIF_TOP_MASK | - CLK_GSCL3_MASK | - CLK_GSCL2_MASK | - CLK_GSCL1_MASK | - CLK_GSCL0_MASK); + clrbits32(&exynos_clock->gate_ip_gscl, CLK_SMMUFIMC_LITE2_MASK | + CLK_SMMUFIMC_LITE1_MASK | + CLK_SMMUFIMC_LITE0_MASK | + CLK_SMMUGSCL3_MASK | + CLK_SMMUGSCL2_MASK | + CLK_SMMUGSCL1_MASK | + CLK_SMMUGSCL0_MASK | + CLK_GSCL_WRAP_B_MASK | + CLK_GSCL_WRAP_A_MASK | + CLK_CAMIF_TOP_MASK | + CLK_GSCL3_MASK | + CLK_GSCL2_MASK | + CLK_GSCL1_MASK | + CLK_GSCL0_MASK); /* CLK_GATE_IP_DISP1 */ - clrbits_le32(&exynos_clock->gate_ip_disp1, CLK_SMMUTVX_MASK | - CLK_ASYNCTVX_MASK | - CLK_HDMI_MASK | - CLK_MIXER_MASK | - CLK_DSIM1_MASK); + clrbits32(&exynos_clock->gate_ip_disp1, CLK_SMMUTVX_MASK | + CLK_ASYNCTVX_MASK | + CLK_HDMI_MASK | + CLK_MIXER_MASK | + CLK_DSIM1_MASK); /* CLK_GATE_IP_MFC */ - clrbits_le32(&exynos_clock->gate_ip_mfc, CLK_SMMUMFCR_MASK | - CLK_SMMUMFCL_MASK | - CLK_MFC_MASK); + clrbits32(&exynos_clock->gate_ip_mfc, CLK_SMMUMFCR_MASK | + CLK_SMMUMFCL_MASK | + CLK_MFC_MASK); /* CLK_GATE_IP_GEN */ - clrbits_le32(&exynos_clock->gate_ip_gen, CLK_SMMUMDMA1_MASK | - CLK_SMMUJPEG_MASK | - CLK_SMMUROTATOR_MASK | - CLK_MDMA1_MASK | - CLK_JPEG_MASK | - CLK_ROTATOR_MASK); + clrbits32(&exynos_clock->gate_ip_gen, CLK_SMMUMDMA1_MASK | + CLK_SMMUJPEG_MASK | + CLK_SMMUROTATOR_MASK | + CLK_MDMA1_MASK | + CLK_JPEG_MASK | + CLK_ROTATOR_MASK); /* CLK_GATE_IP_FSYS */ - clrbits_le32(&exynos_clock->gate_ip_fsys, CLK_WDT_IOP_MASK | - CLK_SMMUMCU_IOP_MASK | - CLK_SATA_PHY_I2C_MASK | - CLK_SATA_PHY_CTRL_MASK | - CLK_MCUCTL_MASK | - CLK_NFCON_MASK | - CLK_SMMURTIC_MASK | - CLK_RTIC_MASK | - CLK_MIPI_HSI_MASK | - CLK_USBOTG_MASK | - CLK_SATA_MASK | - CLK_PDMA1_MASK | - CLK_PDMA0_MASK | - CLK_MCU_IOP_MASK); + clrbits32(&exynos_clock->gate_ip_fsys, CLK_WDT_IOP_MASK | + CLK_SMMUMCU_IOP_MASK | + CLK_SATA_PHY_I2C_MASK | + CLK_SATA_PHY_CTRL_MASK | + CLK_MCUCTL_MASK | + CLK_NFCON_MASK | + CLK_SMMURTIC_MASK | + CLK_RTIC_MASK | + CLK_MIPI_HSI_MASK | + CLK_USBOTG_MASK | + CLK_SATA_MASK | + CLK_PDMA1_MASK | + CLK_PDMA0_MASK | + CLK_MCU_IOP_MASK); /* CLK_GATE_IP_PERIC */ - clrbits_le32(&exynos_clock->gate_ip_peric, CLK_HS_I2C3_MASK | - CLK_HS_I2C2_MASK | - CLK_HS_I2C1_MASK | - CLK_HS_I2C0_MASK | - CLK_AC97_MASK | - CLK_SPDIF_MASK | - CLK_PCM2_MASK | - CLK_PCM1_MASK | - CLK_I2S2_MASK | - CLK_SPI2_MASK | - CLK_SPI0_MASK); + clrbits32(&exynos_clock->gate_ip_peric, CLK_HS_I2C3_MASK | + CLK_HS_I2C2_MASK | + CLK_HS_I2C1_MASK | + CLK_HS_I2C0_MASK | + CLK_AC97_MASK | + CLK_SPDIF_MASK | + CLK_PCM2_MASK | + CLK_PCM1_MASK | + CLK_I2S2_MASK | + CLK_SPI2_MASK | + CLK_SPI0_MASK); /* * CLK_GATE_IP_PERIS @@ -405,33 +405,33 @@ void clock_gate(void) * register (PRO_ID) works correctly when the OS kernel determines * which chip it is running on. */ - clrbits_le32(&exynos_clock->gate_ip_peris, CLK_RTC_MASK | - CLK_TZPC9_MASK | - CLK_TZPC8_MASK | - CLK_TZPC7_MASK | - CLK_TZPC6_MASK | - CLK_TZPC5_MASK | - CLK_TZPC4_MASK | - CLK_TZPC3_MASK | - CLK_TZPC2_MASK | - CLK_TZPC1_MASK | - CLK_TZPC0_MASK); + clrbits32(&exynos_clock->gate_ip_peris, CLK_RTC_MASK | + CLK_TZPC9_MASK | + CLK_TZPC8_MASK | + CLK_TZPC7_MASK | + CLK_TZPC6_MASK | + CLK_TZPC5_MASK | + CLK_TZPC4_MASK | + CLK_TZPC3_MASK | + CLK_TZPC2_MASK | + CLK_TZPC1_MASK | + CLK_TZPC0_MASK); /* CLK_GATE_BLOCK */ - clrbits_le32(&exynos_clock->gate_block, CLK_ACP_MASK); + clrbits32(&exynos_clock->gate_block, CLK_ACP_MASK); /* CLK_GATE_IP_CDREX */ - clrbits_le32(&exynos_clock->gate_ip_cdrex, CLK_DPHY0_MASK | - CLK_DPHY1_MASK | - CLK_TZASC_DRBXR_MASK); + clrbits32(&exynos_clock->gate_ip_cdrex, CLK_DPHY0_MASK | + CLK_DPHY1_MASK | + CLK_TZASC_DRBXR_MASK); } void clock_init_dp_clock(void) { /* DP clock enable */ - setbits_le32(&exynos_clock->gate_ip_disp1, CLK_GATE_DP1_ALLOW); + setbits32(&exynos_clock->gate_ip_disp1, CLK_GATE_DP1_ALLOW); /* We run DP at 267 Mhz */ - setbits_le32(&exynos_clock->div_disp1_0, CLK_DIV_DISP1_0_FIMD1); + setbits32(&exynos_clock->div_disp1_0, CLK_DIV_DISP1_0_FIMD1); } diff --git a/src/soc/samsung/exynos5250/dp-reg.c b/src/soc/samsung/exynos5250/dp-reg.c index e57b0af2f9..fa5e11cf2a 100644 --- a/src/soc/samsung/exynos5250/dp-reg.c +++ b/src/soc/samsung/exynos5250/dp-reg.c @@ -34,8 +34,8 @@ void s5p_dp_reset(struct s5p_dp_device *dp) write32(&base->dp_tx_sw_reset, RESET_DP_TX); /* Stop Video */ - clrbits_le32(&base->video_ctl_1, VIDEO_EN); - clrbits_le32(&base->video_ctl_1, HDCP_VIDEO_MUTE); + clrbits32(&base->video_ctl_1, VIDEO_EN); + clrbits32(&base->video_ctl_1, HDCP_VIDEO_MUTE); reg = MASTER_VID_FUNC_EN_N | SLAVE_VID_FUNC_EN_N | AUD_FIFO_FUNC_EN_N | AUD_FUNC_EN_N | @@ -124,12 +124,12 @@ int s5p_dp_init_analog_func(struct s5p_dp_device *dp) reg = PLL_LOCK_CHG; write32(&base->common_int_sta_1, reg); - clrbits_le32(&base->dp_debug_ctl, (F_PLL_LOCK | PLL_LOCK_CTRL)); + clrbits32(&base->dp_debug_ctl, (F_PLL_LOCK | PLL_LOCK_CTRL)); /* Power up PLL */ if (s5p_dp_get_pll_lock_status(dp) == PLL_UNLOCKED) { - clrbits_le32(&base->dp_pll_ctl, DP_PLL_PD); + clrbits32(&base->dp_pll_ctl, DP_PLL_PD); stopwatch_init_msecs_expire(&sw, PLL_LOCK_TIMEOUT); @@ -143,7 +143,7 @@ int s5p_dp_init_analog_func(struct s5p_dp_device *dp) } /* Enable Serdes FIFO function and Link symbol clock domain module */ - clrbits_le32(&base->func_en_2, (SERDES_FIFO_FUNC_EN_N | + clrbits32(&base->func_en_2, (SERDES_FIFO_FUNC_EN_N | LS_CLK_DOMAIN_FUNC_EN_N | AUX_FUNC_EN_N)); return 0; } @@ -158,7 +158,7 @@ void s5p_dp_init_aux(struct s5p_dp_device *dp) write32(&base->dp_int_sta, reg); /* Disable AUX channel module */ - setbits_le32(&base->func_en_2, AUX_FUNC_EN_N); + setbits32(&base->func_en_2, AUX_FUNC_EN_N); /* Disable AUX transaction H/W retry */ reg = (3 & AUX_BIT_PERIOD_MASK) << AUX_BIT_PERIOD_SHIFT; @@ -172,7 +172,7 @@ void s5p_dp_init_aux(struct s5p_dp_device *dp) write32(&base->aux_ch_defer_dtl, reg); /* Enable AUX channel module */ - clrbits_le32(&base->func_en_2, AUX_FUNC_EN_N); + clrbits32(&base->func_en_2, AUX_FUNC_EN_N); } int s5p_dp_start_aux_transaction(struct s5p_dp_device *dp) @@ -181,7 +181,7 @@ int s5p_dp_start_aux_transaction(struct s5p_dp_device *dp) struct exynos5_dp *base = dp->base; /* Enable AUX CH operation */ - setbits_le32(&base->aux_ch_ctl_2, AUX_EN); + setbits32(&base->aux_ch_ctl_2, AUX_EN); /* Is AUX CH command reply received? */ reg = read32(&base->dp_int_sta); @@ -386,7 +386,7 @@ void s5p_dp_set_video_cr_mn(struct s5p_dp_device *dp, struct exynos5_dp *base = dp->base; if (type == REGISTER_M) { - setbits_le32(&base->sys_ctl_4, FIX_M_VID); + setbits32(&base->sys_ctl_4, FIX_M_VID); reg = m_value >> M_VID_0_VALUE_SHIFT; write32(&base->m_vid_0, reg); @@ -406,7 +406,7 @@ void s5p_dp_set_video_cr_mn(struct s5p_dp_device *dp, reg = (n_value >> N_VID_2_VALUE_SHIFT); write32(&base->n_vid_2, reg); } else { - clrbits_le32(&base->sys_ctl_4, FIX_M_VID); + clrbits32(&base->sys_ctl_4, FIX_M_VID); write32(&base->n_vid_0, 0x00); write32(&base->n_vid_1, 0x80); diff --git a/src/soc/samsung/exynos5250/fb.c b/src/soc/samsung/exynos5250/fb.c index 64980a1aec..2e8acf2688 100644 --- a/src/soc/samsung/exynos5250/fb.c +++ b/src/soc/samsung/exynos5250/fb.c @@ -100,7 +100,7 @@ short console_row; /* Bypass FIMD of DISP1_BLK */ static void fimd_bypass(void) { - setbits_le32(&exynos_sysreg->disp1blk_cfg, FIMDBYPASS_DISP1); + setbits32(&exynos_sysreg->disp1blk_cfg, FIMDBYPASS_DISP1); exynos_sysreg->disp1blk_cfg &= ~FIMDBYPASS_DISP1; } @@ -145,7 +145,7 @@ void fb_init(unsigned long int fb_size, void *lcdbase, write32(&exynos_fimd->vidosd0b, val); write32(&exynos_fimd->vidosd0c, pd->xres * pd->yres); - setbits_le32(&exynos_fimd->shadowcon, CHANNEL0_EN); + setbits32(&exynos_fimd->shadowcon, CHANNEL0_EN); val = BPPMODE_F_RGB_16BIT_565 << BPPMODE_F_OFFSET; val |= ENWIN_F_ENABLE | HALF_WORD_SWAP_EN; @@ -159,7 +159,7 @@ void fb_init(unsigned long int fb_size, void *lcdbase, void exynos_fimd_disable(void) { write32(&exynos_fimd->wincon0, 0); - clrbits_le32(&exynos_fimd->shadowcon, CHANNEL0_EN); + clrbits32(&exynos_fimd->shadowcon, CHANNEL0_EN); } #endif @@ -205,16 +205,16 @@ static int s5p_dp_config_video(struct s5p_dp_device *dp, /* Set to use the register calculated M/N video */ s5p_dp_set_video_cr_mn(dp, CALCULATED_M, 0, 0); - clrbits_le32(&base->video_ctl_10, FORMAT_SEL); + clrbits32(&base->video_ctl_10, FORMAT_SEL); /* Disable video mute */ - clrbits_le32(&base->video_ctl_1, HDCP_VIDEO_MUTE); + clrbits32(&base->video_ctl_1, HDCP_VIDEO_MUTE); /* Configure video slave mode */ s5p_dp_enable_video_master(dp); /* Enable video */ - setbits_le32(&base->video_ctl_1, VIDEO_EN); + setbits32(&base->video_ctl_1, VIDEO_EN); timeout = s5p_dp_is_video_stream_on(dp); if (timeout) { @@ -258,7 +258,7 @@ static int s5p_dp_enable_scramble(struct s5p_dp_device *dp) u8 data; struct exynos5_dp *base = dp->base; - clrbits_le32(&base->dp_training_ptn_set, SCRAMBLING_DISABLE); + clrbits32(&base->dp_training_ptn_set, SCRAMBLING_DISABLE); if (s5p_dp_read_byte_from_dpcd(dp, DPCD_ADDR_TRAINING_PATTERN_SET, &data)) { @@ -288,7 +288,7 @@ static int s5p_dp_init_dp(struct s5p_dp_device *dp) s5p_dp_reset(dp); /* SW defined function Normal operation */ - clrbits_le32(&base->func_en_1, SW_FUNC_EN_N); + clrbits32(&base->func_en_1, SW_FUNC_EN_N); ret = s5p_dp_init_analog_func(dp); if (!ret) @@ -397,7 +397,7 @@ static int s5p_dp_hw_link_training(struct s5p_dp_device *dp, struct exynos5_dp *base = dp->base; /* Stop Video */ - clrbits_le32(&base->video_ctl_1, VIDEO_EN); + clrbits32(&base->video_ctl_1, VIDEO_EN); stopwatch_init_msecs_expire(&sw, PLL_LOCK_TIMEOUT); @@ -411,12 +411,12 @@ static int s5p_dp_hw_link_training(struct s5p_dp_device *dp, printk(BIOS_SPEW, "PLL is %slocked\n", pll_is_locked == PLL_LOCKED ? "": "not "); /* Reset Macro */ - setbits_le32(&base->dp_phy_test, MACRO_RST); + setbits32(&base->dp_phy_test, MACRO_RST); /* 10 us is the minimum reset time. */ udelay(10); - clrbits_le32(&base->dp_phy_test, MACRO_RST); + clrbits32(&base->dp_phy_test, MACRO_RST); /* Set TX pre-emphasis to minimum */ for (lane = 0; lane < max_lane; lane++) @@ -534,7 +534,7 @@ int dp_controller_init(struct s5p_dp_device *dp_device) base = dp->base; /* Enable enhanced mode */ - setbits_le32(&base->sys_ctl_4, ENHANCED); + setbits32(&base->sys_ctl_4, ENHANCED); write32(&base->lane_count_set, dp->link_train.lane_count); write32(&base->link_bw_set, dp->link_train.link_rate); diff --git a/src/soc/samsung/exynos5250/power.c b/src/soc/samsung/exynos5250/power.c index e649e949c8..37369b3482 100644 --- a/src/soc/samsung/exynos5250/power.c +++ b/src/soc/samsung/exynos5250/power.c @@ -26,7 +26,7 @@ static void ps_hold_setup(void) { /* Set PS-Hold high */ - setbits_le32(&exynos_power->ps_hold_ctrl, + setbits32(&exynos_power->ps_hold_ctrl, POWER_PS_HOLD_CONTROL_DATA_HIGH); } @@ -35,7 +35,7 @@ void power_reset(void) /* Clear inform1 so there's no change we think we've got a wake reset */ exynos_power->inform1 = 0; - setbits_le32(&exynos_power->sw_reset, 1); + setbits32(&exynos_power->sw_reset, 1); } void do_board_reset(void) @@ -46,7 +46,7 @@ void do_board_reset(void) /* This function never returns */ void power_shutdown(void) { - clrbits_le32(&exynos_power->ps_hold_ctrl, + clrbits32(&exynos_power->ps_hold_ctrl, POWER_PS_HOLD_CONTROL_DATA_HIGH); halt(); @@ -54,13 +54,13 @@ void power_shutdown(void) void power_enable_dp_phy(void) { - setbits_le32(&exynos_power->dptx_phy_control, EXYNOS_DP_PHY_ENABLE); + setbits32(&exynos_power->dptx_phy_control, EXYNOS_DP_PHY_ENABLE); } void power_enable_hw_thermal_trip(void) { /* Enable HW thermal trip */ - setbits_le32(&exynos_power->ps_hold_ctrl, POWER_ENABLE_HW_TRIP); + setbits32(&exynos_power->ps_hold_ctrl, POWER_ENABLE_HW_TRIP); } uint32_t power_read_reset_status(void) @@ -84,7 +84,7 @@ int power_init(void) void power_enable_xclkout(void) { /* use xxti for xclk out */ - clrsetbits_le32(&exynos_power->pmu_debug, PMU_DEBUG_CLKOUT_SEL_MASK, + clrsetbits32(&exynos_power->pmu_debug, PMU_DEBUG_CLKOUT_SEL_MASK, PMU_DEBUG_XXTI); } diff --git a/src/soc/samsung/exynos5250/spi.c b/src/soc/samsung/exynos5250/spi.c index e35f888177..4d5e01f493 100644 --- a/src/soc/samsung/exynos5250/spi.c +++ b/src/soc/samsung/exynos5250/spi.c @@ -42,8 +42,8 @@ static void exynos_spi_rx_tx(struct exynos_spi *regs, int todo, ASSERT(todo % 4 == 0); out_bytes = in_bytes = todo; - setbits_le32(®s->ch_cfg, SPI_CH_RST); - clrbits_le32(®s->ch_cfg, SPI_CH_RST); + setbits32(®s->ch_cfg, SPI_CH_RST); + clrbits32(®s->ch_cfg, SPI_CH_RST); write32(®s->pkt_cnt, ((todo * 8) / 32) | SPI_PACKET_CNT_EN); while (in_bytes) { @@ -81,22 +81,22 @@ int exynos_spi_open(struct exynos_spi *regs) /* set FB_CLK_SEL */ write32(®s->fb_clk, SPI_FB_DELAY_180); /* set CH_WIDTH and BUS_WIDTH as word */ - setbits_le32(®s->mode_cfg, + setbits32(®s->mode_cfg, SPI_MODE_CH_WIDTH_WORD | SPI_MODE_BUS_WIDTH_WORD); - clrbits_le32(®s->ch_cfg, SPI_CH_CPOL_L); /* CPOL: active high */ + clrbits32(®s->ch_cfg, SPI_CH_CPOL_L); /* CPOL: active high */ /* clear rx and tx channel if set previously */ - clrbits_le32(®s->ch_cfg, SPI_RX_CH_ON | SPI_TX_CH_ON); + clrbits32(®s->ch_cfg, SPI_RX_CH_ON | SPI_TX_CH_ON); - setbits_le32(®s->swap_cfg, - SPI_RX_SWAP_EN | SPI_RX_BYTE_SWAP | SPI_RX_HWORD_SWAP); + setbits32(®s->swap_cfg, + SPI_RX_SWAP_EN | SPI_RX_BYTE_SWAP | SPI_RX_HWORD_SWAP); /* do a soft reset */ - setbits_le32(®s->ch_cfg, SPI_CH_RST); - clrbits_le32(®s->ch_cfg, SPI_CH_RST); + setbits32(®s->ch_cfg, SPI_CH_RST); + clrbits32(®s->ch_cfg, SPI_CH_RST); /* now set rx and tx channel ON */ - setbits_le32(®s->ch_cfg, SPI_RX_CH_ON | SPI_TX_CH_ON | SPI_CH_HS_EN); + setbits32(®s->ch_cfg, SPI_RX_CH_ON | SPI_TX_CH_ON | SPI_CH_HS_EN); return 0; } @@ -104,7 +104,7 @@ int exynos_spi_read(struct exynos_spi *regs, void *dest, u32 len, u32 off) { int upto, todo; int i; - clrbits_le32(®s->cs_reg, SPI_SLAVE_SIG_INACT); /* CS low */ + clrbits32(®s->cs_reg, SPI_SLAVE_SIG_INACT); /* CS low */ /* Send read instruction (0x3h) followed by a 24 bit addr */ write32(®s->tx_data, (SF_READ_DATA_CMD << 24) | off); @@ -117,7 +117,7 @@ int exynos_spi_read(struct exynos_spi *regs, void *dest, u32 len, u32 off) exynos_spi_rx_tx(regs, todo, dest, (void *)(off), i); } - setbits_le32(®s->cs_reg, SPI_SLAVE_SIG_INACT);/* make the CS high */ + setbits32(®s->cs_reg, SPI_SLAVE_SIG_INACT);/* make the CS high */ return len; } @@ -128,17 +128,17 @@ int exynos_spi_close(struct exynos_spi *regs) * Let put controller mode to BYTE as * SPI driver does not support WORD mode yet */ - clrbits_le32(®s->mode_cfg, - SPI_MODE_CH_WIDTH_WORD | SPI_MODE_BUS_WIDTH_WORD); + clrbits32(®s->mode_cfg, + SPI_MODE_CH_WIDTH_WORD | SPI_MODE_BUS_WIDTH_WORD); write32(®s->swap_cfg, 0); /* * Flush spi tx, rx fifos and reset the SPI controller * and clear rx/tx channel */ - clrsetbits_le32(®s->ch_cfg, SPI_CH_HS_EN, SPI_CH_RST); - clrbits_le32(®s->ch_cfg, SPI_CH_RST); - clrbits_le32(®s->ch_cfg, SPI_TX_CH_ON | SPI_RX_CH_ON); + clrsetbits32(®s->ch_cfg, SPI_CH_HS_EN, SPI_CH_RST); + clrbits32(®s->ch_cfg, SPI_CH_RST); + clrbits32(®s->ch_cfg, SPI_TX_CH_ON | SPI_RX_CH_ON); return 0; } diff --git a/src/soc/samsung/exynos5250/usb.c b/src/soc/samsung/exynos5250/usb.c index 076e42eee9..12b658aef3 100644 --- a/src/soc/samsung/exynos5250/usb.c +++ b/src/soc/samsung/exynos5250/usb.c @@ -25,9 +25,9 @@ static void reset_dwc3(struct exynos5_usb_drd_dwc3 *dwc3) { - setbits_le32(&dwc3->ctl, 0x1 << 11); /* core soft reset */ - setbits_le32(&dwc3->usb3pipectl, 0x1 << 31); /* PHY soft reset */ - setbits_le32(&dwc3->usb2phycfg, 0x1 << 31); /* PHY soft reset */ + setbits32(&dwc3->ctl, 0x1 << 11); /* core soft reset */ + setbits32(&dwc3->usb3pipectl, 0x1 << 31); /* PHY soft reset */ + setbits32(&dwc3->usb2phycfg, 0x1 << 31); /* PHY soft reset */ } void reset_usb_drd_dwc3() @@ -77,7 +77,7 @@ static void setup_drd_phy(struct exynos5_usb_drd_phy *phy) /* Set all PHY registers to default values */ /* XHCI Version 1.0, Frame Length adjustment 30 MHz */ - setbits_le32(&phy->linksystem, 0x1 << 27 | 0x20 << 1); + setbits32(&phy->linksystem, 0x1 << 27 | 0x20 << 1); /* Disable OTG, ID0 and DRVVBUS, do not force sleep/suspend */ write32(&phy->utmi, 1 << 6); @@ -120,13 +120,13 @@ static void setup_drd_phy(struct exynos5_usb_drd_phy *phy) write32(&phy->resume, 0x0); udelay(10); - clrbits_le32(&phy->clkrst, 0x1 << 1); /* deassert port reset */ + clrbits32(&phy->clkrst, 0x1 << 1); /* deassert port reset */ } void setup_usb_drd_phy() { printk(BIOS_DEBUG, "Powering up USB DRD PHY\n"); - setbits_le32(&exynos_power->usb_drd_phy_ctrl, POWER_USB_PHY_CTRL_EN); + setbits32(&exynos_power->usb_drd_phy_ctrl, POWER_USB_PHY_CTRL_EN); setup_drd_phy(exynos_usb_drd_phy); } @@ -134,8 +134,8 @@ void setup_usb_host_phy(int hsic_gpio) { unsigned int hostphy_ctrl0; - setbits_le32(&exynos_sysreg->usb20_phy_cfg, USB20_PHY_CFG_EN); - setbits_le32(&exynos_power->usb_host_phy_ctrl, POWER_USB_PHY_CTRL_EN); + setbits32(&exynos_sysreg->usb20_phy_cfg, USB20_PHY_CFG_EN); + setbits32(&exynos_power->usb_host_phy_ctrl, POWER_USB_PHY_CTRL_EN); printk(BIOS_DEBUG, "Powering up USB HOST PHY (%s HSIC)\n", hsic_gpio ? "with" : "without"); @@ -156,13 +156,13 @@ void setup_usb_host_phy(int hsic_gpio) HOST_CTRL0_UTMISWRST); write32(&exynos_usb_host_phy->usbphyctrl0, hostphy_ctrl0); udelay(10); - clrbits_le32(&exynos_usb_host_phy->usbphyctrl0, - HOST_CTRL0_LINKSWRST | - HOST_CTRL0_UTMISWRST); + clrbits32(&exynos_usb_host_phy->usbphyctrl0, + HOST_CTRL0_LINKSWRST | + HOST_CTRL0_UTMISWRST); udelay(20); /* EHCI Ctrl setting */ - setbits_le32(&exynos_usb_host_phy->ehcictrl, + setbits32(&exynos_usb_host_phy->ehcictrl, EHCICTRL_ENAINCRXALIGN | EHCICTRL_ENAINCR4 | EHCICTRL_ENAINCR8 | @@ -175,15 +175,15 @@ void setup_usb_host_phy(int hsic_gpio) gpio_direction_output(hsic_gpio, 1); udelay(5000); - clrbits_le32(&exynos_usb_host_phy->hsicphyctrl1, - HOST_CTRL0_SIDDQ | - HOST_CTRL0_FORCESLEEP | - HOST_CTRL0_FORCESUSPEND); - setbits_le32(&exynos_usb_host_phy->hsicphyctrl1, - HOST_CTRL0_PHYSWRST); + clrbits32(&exynos_usb_host_phy->hsicphyctrl1, + HOST_CTRL0_SIDDQ | + HOST_CTRL0_FORCESLEEP | + HOST_CTRL0_FORCESUSPEND); + setbits32(&exynos_usb_host_phy->hsicphyctrl1, + HOST_CTRL0_PHYSWRST); udelay(10); - clrbits_le32(&exynos_usb_host_phy->hsicphyctrl1, - HOST_CTRL0_PHYSWRST); + clrbits32(&exynos_usb_host_phy->hsicphyctrl1, + HOST_CTRL0_PHYSWRST); } /* At this point we need to wait for 50ms before talking to diff --git a/src/soc/samsung/exynos5420/clock.c b/src/soc/samsung/exynos5420/clock.c index b578133ea4..fe11cdecff 100644 --- a/src/soc/samsung/exynos5420/clock.c +++ b/src/soc/samsung/exynos5420/clock.c @@ -390,7 +390,7 @@ void clock_ll_set_pre_ratio(enum periph_id periph_id, unsigned int divisor) periph_id); return; } - clrsetbits_le32(reg, mask << shift, (divisor & mask) << shift); + clrsetbits32(reg, mask << shift, (divisor & mask) << shift); } void clock_ll_set_ratio(enum periph_id periph_id, unsigned int divisor) @@ -425,7 +425,7 @@ void clock_ll_set_ratio(enum periph_id periph_id, unsigned int divisor) periph_id); return; } - clrsetbits_le32(reg, mask << shift, (divisor & mask) << shift); + clrsetbits32(reg, mask << shift, (divisor & mask) << shift); } /** @@ -607,7 +607,7 @@ int clock_epll_set_rate(unsigned long rate) void clock_select_i2s_clk_source(void) { - clrsetbits_le32(&exynos_clock->clk_src_peric1, AUDIO1_SEL_MASK, + clrsetbits32(&exynos_clock->clk_src_peric1, AUDIO1_SEL_MASK, (CLK_SRC_SCLK_EPLL)); } @@ -627,7 +627,7 @@ int clock_set_i2s_clk_prescaler(unsigned int src_frq, unsigned int dst_frq) printk(BIOS_DEBUG, "src frq = %d des frq = %d ", src_frq, dst_frq); return -1; } - clrsetbits_le32(&exynos_clock->clk_div_peric4, AUDIO_1_RATIO_MASK, + clrsetbits32(&exynos_clock->clk_div_peric4, AUDIO_1_RATIO_MASK, (div & AUDIO_1_RATIO_MASK)); return 0; } diff --git a/src/soc/samsung/exynos5420/clock_init.c b/src/soc/samsung/exynos5420/clock_init.c index eae08a8dea..92abf32081 100644 --- a/src/soc/samsung/exynos5420/clock_init.c +++ b/src/soc/samsung/exynos5420/clock_init.c @@ -42,7 +42,7 @@ void system_clock_init(void) write32(&exynos_clock->kpll_lock, KPLL_LOCK_VAL); write32(&exynos_clock->rpll_lock, RPLL_LOCK_VAL); - setbits_le32(&exynos_clock->clk_src_cpu, MUX_HPM_SEL_MASK); + setbits32(&exynos_clock->clk_src_cpu, MUX_HPM_SEL_MASK); write32(&exynos_clock->clk_src_top6, 0); @@ -52,7 +52,7 @@ void system_clock_init(void) write32(&exynos_clock->clk_div_cpu0, CLK_DIV_CPU0_VAL); /* switch A15 clock source to OSC clock before changing APLL */ - clrbits_le32(&exynos_clock->clk_src_cpu, APLL_FOUT); + clrbits32(&exynos_clock->clk_src_cpu, APLL_FOUT); /* Set APLL */ write32(&exynos_clock->apll_con1, APLL_CON1_VAL); @@ -62,13 +62,13 @@ void system_clock_init(void) ; /* now it is safe to switch to APLL */ - setbits_le32(&exynos_clock->clk_src_cpu, APLL_FOUT); + setbits32(&exynos_clock->clk_src_cpu, APLL_FOUT); write32(&exynos_clock->clk_src_kfc, SRC_KFC_HPM_SEL); write32(&exynos_clock->clk_div_kfc0, CLK_DIV_KFC_VAL); /* switch A7 clock source to OSC clock before changing KPLL */ - clrbits_le32(&exynos_clock->clk_src_kfc, KPLL_FOUT); + clrbits32(&exynos_clock->clk_src_kfc, KPLL_FOUT); /* Set KPLL*/ write32(&exynos_clock->kpll_con1, KPLL_CON1_VAL); @@ -78,7 +78,7 @@ void system_clock_init(void) ; /* now it is safe to switch to KPLL */ - setbits_le32(&exynos_clock->clk_src_kfc, KPLL_FOUT); + setbits32(&exynos_clock->clk_src_kfc, KPLL_FOUT); /* Set MPLL */ write32(&exynos_clock->mpll_con1, MPLL_CON1_VAL); diff --git a/src/soc/samsung/exynos5420/dmc_init_ddr3.c b/src/soc/samsung/exynos5420/dmc_init_ddr3.c index 6ea92ee36f..88dc18d2f6 100644 --- a/src/soc/samsung/exynos5420/dmc_init_ddr3.c +++ b/src/soc/samsung/exynos5420/dmc_init_ddr3.c @@ -33,10 +33,10 @@ int ddr3_mem_ctrl_init(struct mem_timings *mem, int interleave_size, int reset) int i, chip; /* Enable PAUSE for DREX */ - setbits_le32(&exynos_clock->pause, ENABLE_BIT); + setbits32(&exynos_clock->pause, ENABLE_BIT); /* Enable BYPASS mode */ - setbits_le32(&exynos_clock->bpll_con1, BYPASS_EN); + setbits32(&exynos_clock->bpll_con1, BYPASS_EN); write32(&exynos_clock->clk_src_cdrex, MUX_BPLL_SEL_FOUTBPLL); do { @@ -44,7 +44,7 @@ int ddr3_mem_ctrl_init(struct mem_timings *mem, int interleave_size, int reset) val &= BPLL_SEL_MASK; } while (val != FOUTBPLL); - clrbits_le32(&exynos_clock->bpll_con1, BYPASS_EN); + clrbits32(&exynos_clock->bpll_con1, BYPASS_EN); /* Specify the DDR memory type as DDR3 */ val = read32(&exynos_phy0_control->phy_con0); @@ -87,8 +87,8 @@ int ddr3_mem_ctrl_init(struct mem_timings *mem, int interleave_size, int reset) if (dmc_config_zq(mem, exynos_phy0_control, exynos_phy1_control)) return SETUP_ERR_ZQ_CALIBRATION_FAILURE; - clrbits_le32(&exynos_phy0_control->phy_con16, ZQ_CLK_DIV_EN); - clrbits_le32(&exynos_phy1_control->phy_con16, ZQ_CLK_DIV_EN); + clrbits32(&exynos_phy0_control->phy_con16, ZQ_CLK_DIV_EN); + clrbits32(&exynos_phy1_control->phy_con16, ZQ_CLK_DIV_EN); /* DQ Signal */ val = read32(&exynos_phy0_control->phy_con14); @@ -116,8 +116,8 @@ int ddr3_mem_ctrl_init(struct mem_timings *mem, int interleave_size, int reset) val = read32(&exynos_drex1->phystatus); } while ((val & DFI_INIT_COMPLETE) != DFI_INIT_COMPLETE); - clrbits_le32(&exynos_drex0->concontrol, DFI_INIT_START); - clrbits_le32(&exynos_drex1->concontrol, DFI_INIT_START); + clrbits32(&exynos_drex0->concontrol, DFI_INIT_START); + clrbits32(&exynos_drex1->concontrol, DFI_INIT_START); update_reset_dll(exynos_drex0, mem->mem_type); update_reset_dll(exynos_drex1, mem->mem_type); @@ -205,8 +205,8 @@ int ddr3_mem_ctrl_init(struct mem_timings *mem, int interleave_size, int reset) write32(&exynos_phy0_control->phy_con0, PHY_CON0_RESET_VAL); write32(&exynos_phy1_control->phy_con0, PHY_CON0_RESET_VAL); - setbits_le32(&exynos_phy0_control->phy_con0, P0_CMD_EN); - setbits_le32(&exynos_phy1_control->phy_con0, P0_CMD_EN); + setbits32(&exynos_phy0_control->phy_con0, P0_CMD_EN); + setbits32(&exynos_phy1_control->phy_con0, P0_CMD_EN); val = PHY_CON2_RESET_VAL; val |= INIT_DESKEW_EN; @@ -243,11 +243,11 @@ int ddr3_mem_ctrl_init(struct mem_timings *mem, int interleave_size, int reset) val | (chip << DIRECT_CMD_CHIP_SHIFT)); } - setbits_le32(&exynos_phy0_control->phy_con2, RDLVL_GATE_EN); - setbits_le32(&exynos_phy1_control->phy_con2, RDLVL_GATE_EN); + setbits32(&exynos_phy0_control->phy_con2, RDLVL_GATE_EN); + setbits32(&exynos_phy1_control->phy_con2, RDLVL_GATE_EN); - setbits_le32(&exynos_phy0_control->phy_con0, CTRL_SHGATE); - setbits_le32(&exynos_phy1_control->phy_con0, CTRL_SHGATE); + setbits32(&exynos_phy0_control->phy_con0, CTRL_SHGATE); + setbits32(&exynos_phy1_control->phy_con0, CTRL_SHGATE); val = read32(&exynos_phy0_control->phy_con1); val &= ~(CTRL_GATEDURADJ_MASK); @@ -303,8 +303,8 @@ int ddr3_mem_ctrl_init(struct mem_timings *mem, int interleave_size, int reset) write32(&exynos_phy0_control->phy_con12, (val + nLockW_phy0)); write32(&exynos_phy1_control->phy_con12, (val + nLockW_phy1)); - setbits_le32(&exynos_phy0_control->phy_con2, DLL_DESKEW_EN); - setbits_le32(&exynos_phy1_control->phy_con2, DLL_DESKEW_EN); + setbits32(&exynos_phy0_control->phy_con2, DLL_DESKEW_EN); + setbits32(&exynos_phy1_control->phy_con2, DLL_DESKEW_EN); } /* Send PALL command */ @@ -332,8 +332,8 @@ int ddr3_mem_ctrl_init(struct mem_timings *mem, int interleave_size, int reset) * this saves around 25 mw dmc power as compared to the power * consumption without these bits enabled */ - setbits_le32(&exynos_drex0->cgcontrol, DMC_INTERNAL_CG); - setbits_le32(&exynos_drex1->cgcontrol, DMC_INTERNAL_CG); + setbits32(&exynos_drex0->cgcontrol, DMC_INTERNAL_CG); + setbits32(&exynos_drex1->cgcontrol, DMC_INTERNAL_CG); return 0; } diff --git a/src/soc/samsung/exynos5420/power.c b/src/soc/samsung/exynos5420/power.c index 9dfffd6ee6..b59162eccd 100644 --- a/src/soc/samsung/exynos5420/power.c +++ b/src/soc/samsung/exynos5420/power.c @@ -25,7 +25,7 @@ static void ps_hold_setup(void) { /* Set PS-Hold high */ - setbits_le32(&exynos_power->ps_hold_ctrl, + setbits32(&exynos_power->ps_hold_ctrl, POWER_PS_HOLD_CONTROL_DATA_HIGH); } @@ -34,13 +34,13 @@ void power_reset(void) /* Clear inform1 so there's no change we think we've got a wake reset */ exynos_power->inform1 = 0; - setbits_le32(&exynos_power->sw_reset, 1); + setbits32(&exynos_power->sw_reset, 1); } /* This function never returns */ void power_shutdown(void) { - clrbits_le32(&exynos_power->ps_hold_ctrl, + clrbits32(&exynos_power->ps_hold_ctrl, POWER_PS_HOLD_CONTROL_DATA_HIGH); halt(); @@ -48,13 +48,13 @@ void power_shutdown(void) void power_enable_dp_phy(void) { - setbits_le32(&exynos_power->dptx_phy_control, EXYNOS_DP_PHY_ENABLE); + setbits32(&exynos_power->dptx_phy_control, EXYNOS_DP_PHY_ENABLE); } void power_enable_hw_thermal_trip(void) { /* Enable HW thermal trip */ - setbits_le32(&exynos_power->ps_hold_ctrl, POWER_ENABLE_HW_TRIP); + setbits32(&exynos_power->ps_hold_ctrl, POWER_ENABLE_HW_TRIP); } uint32_t power_read_reset_status(void) @@ -78,7 +78,7 @@ int power_init(void) void power_enable_xclkout(void) { /* use xxti for xclk out */ - clrsetbits_le32(&exynos_power->pmu_debug, PMU_DEBUG_CLKOUT_SEL_MASK, + clrsetbits32(&exynos_power->pmu_debug, PMU_DEBUG_CLKOUT_SEL_MASK, PMU_DEBUG_XXTI); } diff --git a/src/soc/samsung/exynos5420/spi.c b/src/soc/samsung/exynos5420/spi.c index 1903f6b3b9..5637b0215d 100644 --- a/src/soc/samsung/exynos5420/spi.c +++ b/src/soc/samsung/exynos5420/spi.c @@ -89,10 +89,10 @@ static void spi_sw_reset(struct exynos_spi *regs, int word) if (swap_cfg != orig_swap_cfg) write32(®s->swap_cfg, swap_cfg); - clrbits_le32(®s->ch_cfg, SPI_RX_CH_ON | SPI_TX_CH_ON); - setbits_le32(®s->ch_cfg, SPI_CH_RST); - clrbits_le32(®s->ch_cfg, SPI_CH_RST); - setbits_le32(®s->ch_cfg, SPI_RX_CH_ON | SPI_TX_CH_ON); + clrbits32(®s->ch_cfg, SPI_RX_CH_ON | SPI_TX_CH_ON); + setbits32(®s->ch_cfg, SPI_CH_RST); + clrbits32(®s->ch_cfg, SPI_CH_RST); + setbits32(®s->ch_cfg, SPI_RX_CH_ON | SPI_TX_CH_ON); } static void exynos_spi_init(struct exynos_spi *regs) @@ -100,14 +100,14 @@ static void exynos_spi_init(struct exynos_spi *regs) // Set FB_CLK_SEL. write32(®s->fb_clk, SPI_FB_DELAY_180); // CPOL: Active high. - clrbits_le32(®s->ch_cfg, SPI_CH_CPOL_L); + clrbits32(®s->ch_cfg, SPI_CH_CPOL_L); // Clear rx and tx channel if set priveously. - clrbits_le32(®s->ch_cfg, SPI_RX_CH_ON | SPI_TX_CH_ON); + clrbits32(®s->ch_cfg, SPI_RX_CH_ON | SPI_TX_CH_ON); - setbits_le32(®s->swap_cfg, + setbits32(®s->swap_cfg, SPI_RX_SWAP_EN | SPI_RX_BYTE_SWAP | SPI_RX_HWORD_SWAP); - clrbits_le32(®s->ch_cfg, SPI_CH_HS_EN); + clrbits32(®s->ch_cfg, SPI_CH_HS_EN); // Do a soft reset, which will also enable both channels. spi_sw_reset(regs, 1); @@ -117,7 +117,7 @@ static int spi_ctrlr_claim_bus(const struct spi_slave *slave) { struct exynos_spi *regs = to_exynos_spi(slave)->regs; // TODO(hungte) Add some delay if too many transactions happen at once. - clrbits_le32(®s->cs_reg, SPI_SLAVE_SIG_INACT); + clrbits32(®s->cs_reg, SPI_SLAVE_SIG_INACT); return 0; } @@ -201,7 +201,7 @@ static int spi_ctrlr_xfer(const struct spi_slave *slave, const void *dout, size_ static void spi_ctrlr_release_bus(const struct spi_slave *slave) { struct exynos_spi *regs = to_exynos_spi(slave)->regs; - setbits_le32(®s->cs_reg, SPI_SLAVE_SIG_INACT); + setbits32(®s->cs_reg, SPI_SLAVE_SIG_INACT); } static int spi_ctrlr_setup(const struct spi_slave *slave) diff --git a/src/soc/samsung/exynos5420/usb.c b/src/soc/samsung/exynos5420/usb.c index 9dda4c100d..2f141c1b67 100644 --- a/src/soc/samsung/exynos5420/usb.c +++ b/src/soc/samsung/exynos5420/usb.c @@ -25,9 +25,9 @@ static void reset_dwc3(struct exynos5_usb_drd_dwc3 *dwc3) { - setbits_le32(&dwc3->ctl, 0x1 << 11); /* core soft reset */ - setbits_le32(&dwc3->usb3pipectl, 0x1 << 31); /* PHY soft reset */ - setbits_le32(&dwc3->usb2phycfg, 0x1 << 31); /* PHY soft reset */ + setbits32(&dwc3->ctl, 0x1 << 11); /* core soft reset */ + setbits32(&dwc3->usb3pipectl, 0x1 << 31); /* PHY soft reset */ + setbits32(&dwc3->usb2phycfg, 0x1 << 31); /* PHY soft reset */ } void reset_usb_drd0_dwc3() @@ -89,7 +89,7 @@ static void setup_drd_phy(struct exynos5_usb_drd_phy *phy) /* Set all PHY registers to default values */ /* XHCI Version 1.0, Frame Length adjustment 30 MHz */ - setbits_le32(&phy->linksystem, 0x1 << 27 | 0x20 << 1); + setbits32(&phy->linksystem, 0x1 << 27 | 0x20 << 1); /* Disable OTG, ID0 and DRVVBUS, do not force sleep/suspend */ write32(&phy->utmi, 1 << 6); @@ -132,20 +132,20 @@ static void setup_drd_phy(struct exynos5_usb_drd_phy *phy) write32(&phy->resume, 0x0); udelay(10); - clrbits_le32(&phy->clkrst, 0x1 << 1); /* deassert port reset */ + clrbits32(&phy->clkrst, 0x1 << 1); /* deassert port reset */ } void setup_usb_drd0_phy() { printk(BIOS_DEBUG, "Powering up USB DRD0 PHY\n"); - setbits_le32(&exynos_power->usb_drd0_phy_ctrl, POWER_USB_PHY_CTRL_EN); + setbits32(&exynos_power->usb_drd0_phy_ctrl, POWER_USB_PHY_CTRL_EN); setup_drd_phy(exynos_usb_drd0_phy); } void setup_usb_drd1_phy() { printk(BIOS_DEBUG, "Powering up USB DRD1 PHY\n"); - setbits_le32(&exynos_power->usb_drd1_phy_ctrl, POWER_USB_PHY_CTRL_EN); + setbits32(&exynos_power->usb_drd1_phy_ctrl, POWER_USB_PHY_CTRL_EN); setup_drd_phy(exynos_usb_drd1_phy); } @@ -153,8 +153,8 @@ void setup_usb_host_phy(int hsic_gpio) { unsigned int hostphy_ctrl0; - setbits_le32(&exynos_sysreg->usb20_phy_cfg, USB20_PHY_CFG_EN); - setbits_le32(&exynos_power->usb_host_phy_ctrl, POWER_USB_PHY_CTRL_EN); + setbits32(&exynos_sysreg->usb20_phy_cfg, USB20_PHY_CFG_EN); + setbits32(&exynos_power->usb_host_phy_ctrl, POWER_USB_PHY_CTRL_EN); printk(BIOS_DEBUG, "Powering up USB HOST PHY (%s HSIC)\n", hsic_gpio ? "with" : "without"); @@ -175,17 +175,17 @@ void setup_usb_host_phy(int hsic_gpio) HOST_CTRL0_UTMISWRST); write32(&exynos_usb_host_phy->usbphyctrl0, hostphy_ctrl0); udelay(10); - clrbits_le32(&exynos_usb_host_phy->usbphyctrl0, - HOST_CTRL0_LINKSWRST | - HOST_CTRL0_UTMISWRST); + clrbits32(&exynos_usb_host_phy->usbphyctrl0, + HOST_CTRL0_LINKSWRST | + HOST_CTRL0_UTMISWRST); udelay(20); /* EHCI Ctrl setting */ - setbits_le32(&exynos_usb_host_phy->ehcictrl, - EHCICTRL_ENAINCRXALIGN | - EHCICTRL_ENAINCR4 | - EHCICTRL_ENAINCR8 | - EHCICTRL_ENAINCR16); + setbits32(&exynos_usb_host_phy->ehcictrl, + EHCICTRL_ENAINCRXALIGN | + EHCICTRL_ENAINCR4 | + EHCICTRL_ENAINCR8 | + EHCICTRL_ENAINCR16); /* HSIC USB Hub initialization. */ if (hsic_gpio) { @@ -194,15 +194,15 @@ void setup_usb_host_phy(int hsic_gpio) gpio_direction_output(hsic_gpio, 1); udelay(5000); - clrbits_le32(&exynos_usb_host_phy->hsicphyctrl1, - HOST_CTRL0_SIDDQ | - HOST_CTRL0_FORCESLEEP | - HOST_CTRL0_FORCESUSPEND); - setbits_le32(&exynos_usb_host_phy->hsicphyctrl1, - HOST_CTRL0_PHYSWRST); + clrbits32(&exynos_usb_host_phy->hsicphyctrl1, + HOST_CTRL0_SIDDQ | + HOST_CTRL0_FORCESLEEP | + HOST_CTRL0_FORCESUSPEND); + setbits32(&exynos_usb_host_phy->hsicphyctrl1, + HOST_CTRL0_PHYSWRST); udelay(10); - clrbits_le32(&exynos_usb_host_phy->hsicphyctrl1, - HOST_CTRL0_PHYSWRST); + clrbits32(&exynos_usb_host_phy->hsicphyctrl1, + HOST_CTRL0_PHYSWRST); } /* At this point we need to wait for 50ms before talking to diff --git a/src/soc/sifive/fu540/clock.c b/src/soc/sifive/fu540/clock.c index 60a8a134c3..ef6221b262 100644 --- a/src/soc/sifive/fu540/clock.c +++ b/src/soc/sifive/fu540/clock.c @@ -84,7 +84,7 @@ static void configure_pll(u32 *reg, const struct pll_settings *s) { // Write the settings to the register u32 c = read32(reg); - clrsetbits_le32(&c, PRCI_PLLCFG_DIVR_MASK + clrsetbits32(&c, PRCI_PLLCFG_DIVR_MASK | PRCI_PLLCFG_DIVF_MASK | PRCI_PLLCFG_DIVQ_MASK | PRCI_PLLCFG_RANGE_MASK | PRCI_PLLCFG_BYPASS_MASK | PRCI_PLLCFG_FSE_MASK, @@ -155,13 +155,13 @@ static const struct pll_settings gemgxlpll_settings = { static void init_coreclk(void) { // switch coreclk to input reference frequency before modifying PLL - clrsetbits_le32(&prci->coreclksel, PRCI_CORECLK_MASK, + clrsetbits32(&prci->coreclksel, PRCI_CORECLK_MASK, PRCI_CORECLK_HFCLK); configure_pll(&prci->corepllcfg0, &corepll_settings); // switch coreclk to use corepll - clrsetbits_le32(&prci->coreclksel, PRCI_CORECLK_MASK, + clrsetbits32(&prci->coreclksel, PRCI_CORECLK_MASK, PRCI_CORECLK_CORE_PLL); } @@ -169,25 +169,25 @@ static void init_pll_ddr(void) { // disable ddr clock output before reconfiguring the PLL u32 cfg1 = read32(&prci->ddrpllcfg1); - clrbits_le32(&cfg1, PRCI_DDRPLLCFG1_MASK); + clrbits32(&cfg1, PRCI_DDRPLLCFG1_MASK); write32(&prci->ddrpllcfg1, cfg1); configure_pll(&prci->ddrpllcfg0, &ddrpll_settings); // enable ddr clock output - setbits_le32(&cfg1, PRCI_DDRPLLCFG1_MASK); + setbits32(&cfg1, PRCI_DDRPLLCFG1_MASK); write32(&prci->ddrpllcfg1, cfg1); } static void init_gemgxlclk(void) { u32 cfg1 = read32(&prci->gemgxlpllcfg1); - clrbits_le32(&cfg1, PRCI_GEMGXLPPLCFG1_MASK); + clrbits32(&cfg1, PRCI_GEMGXLPPLCFG1_MASK); write32(&prci->gemgxlpllcfg1, cfg1); configure_pll(&prci->gemgxlpllcfg0, &gemgxlpll_settings); - setbits_le32(&cfg1, PRCI_GEMGXLPPLCFG1_MASK); + setbits32(&cfg1, PRCI_GEMGXLPPLCFG1_MASK); write32(&prci->gemgxlpllcfg1, cfg1); } diff --git a/src/soc/sifive/fu540/spi.c b/src/soc/sifive/fu540/spi.c index 5e30e77939..ae57cf6ef0 100644 --- a/src/soc/sifive/fu540/spi.c +++ b/src/soc/sifive/fu540/spi.c @@ -14,7 +14,7 @@ * GNU General Public License for more details. */ -#include +#include #include #include #include From 8cee45c3f8f05d936ba181f56405b8c936666a36 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Micha=C5=82=20=C5=BBygowski?= Date: Sat, 23 Nov 2019 18:03:46 +0100 Subject: [PATCH 0537/1242] sb/amd/{agesa,pi}/hudson: add southbridge C bootblock initialization MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: Michał Żygowski Change-Id: Iaba5443d8770473c4abe73ec2a91f8d6a52574af Reviewed-on: https://review.coreboot.org/c/coreboot/+/37168 Reviewed-by: Kyösti Mälkki Tested-by: build bot (Jenkins) --- src/southbridge/amd/agesa/hudson/Makefile.inc | 7 ++- src/southbridge/amd/agesa/hudson/bootblock.c | 45 ++++++++++++++++++ .../amd/agesa/hudson/early_setup.c | 18 +++++++ src/southbridge/amd/agesa/hudson/hudson.h | 41 ++++++++++++++++ src/southbridge/amd/pi/hudson/Makefile.inc | 6 ++- src/southbridge/amd/pi/hudson/bootblock.c | 47 +++++++++++++++++++ src/southbridge/amd/pi/hudson/early_setup.c | 25 ++++------ src/southbridge/amd/pi/hudson/hudson.h | 4 ++ 8 files changed, 176 insertions(+), 17 deletions(-) diff --git a/src/southbridge/amd/agesa/hudson/Makefile.inc b/src/southbridge/amd/agesa/hudson/Makefile.inc index 5cb3755e8b..5c921280f7 100644 --- a/src/southbridge/amd/agesa/hudson/Makefile.inc +++ b/src/southbridge/amd/agesa/hudson/Makefile.inc @@ -17,7 +17,12 @@ ramstage-y += sd.c ramstage-$(CONFIG_HAVE_ACPI_TABLES) += fadt.c ramstage-y += reset.c -bootblock-y += enable_usbdebug.c +ifneq ($(CONFIG_ROMCC_BOOTBLOCK),y) +bootblock-y += bootblock.c +bootblock-y += early_setup.c +bootblock-$(CONFIG_USBDEBUG) += enable_usbdebug.c +endif + romstage-y += enable_usbdebug.c ramstage-y += enable_usbdebug.c romstage-y += early_setup.c diff --git a/src/southbridge/amd/agesa/hudson/bootblock.c b/src/southbridge/amd/agesa/hudson/bootblock.c index f12cec8602..97e8803f48 100644 --- a/src/southbridge/amd/agesa/hudson/bootblock.c +++ b/src/southbridge/amd/agesa/hudson/bootblock.c @@ -60,3 +60,48 @@ static void bootblock_southbridge_init(void) { hudson_enable_rom(); } + + +#if !CONFIG(ROMCC_BOOTBLOCK) + +#include +#include +#include + +void bootblock_soc_early_init(void) +{ + pci_devfn_t dev; + u32 data; + + bootblock_southbridge_init(); + hudson_lpc_decode(); + enable_acpimmio_decode_pm24(); + + dev = PCI_DEV(0, 0x14, 3); + data = pci_read_config32(dev, LPC_IO_OR_MEM_DECODE_ENABLE); + /* enable 0x2e/0x4e IO decoding for SuperIO */ + pci_write_config32(dev, LPC_IO_OR_MEM_DECODE_ENABLE, data | 3); + + /* + * Enable FCH to decode TPM associated Memory and IO regions for vboot + * + * Enable decoding of TPM cycles defined in TPM 1.2 spec + * Enable decoding of legacy TPM addresses: IO addresses 0x7f- + * 0x7e and 0xef-0xee. + */ + + data = pci_read_config32(dev, LPC_TRUSTED_PLATFORM_MODULE); + data |= TPM_12_EN | TPM_LEGACY_EN; + pci_write_config32(dev, LPC_TRUSTED_PLATFORM_MODULE, data); + + /* + * In Hudson RRG, PMIOxD2[5:4] is "Drive strength control for + * LpcClk[1:0]". This following register setting has been + * replicated in every reference design since Parmer, so it is + * believed to be required even though it is not documented in + * the SoC BKDGs. Without this setting, there is no serial + * output. + */ + pm_write8(0xd2, 0); +} +#endif diff --git a/src/southbridge/amd/agesa/hudson/early_setup.c b/src/southbridge/amd/agesa/hudson/early_setup.c index c5e6c25b68..d85cb2b6f1 100644 --- a/src/southbridge/amd/agesa/hudson/early_setup.c +++ b/src/southbridge/amd/agesa/hudson/early_setup.c @@ -87,4 +87,22 @@ void hudson_lpc_port80(void) pci_write_config8(dev, 0x4a, byte); } +void hudson_lpc_decode(void) +{ + pci_devfn_t dev; + u32 tmp; + + dev = PCI_DEV(0, 0x14, 3); + /* Serial port numeration on Hudson: + * PORT0 - 0x3f8 + * PORT1 - 0x2f8 + * PORT5 - 0x2e8 + * PORT7 - 0x3e8 + */ + tmp = DECODE_ENABLE_SERIAL_PORT0 | DECODE_ENABLE_SERIAL_PORT1 + | DECODE_ENABLE_SERIAL_PORT5 | DECODE_ENABLE_SERIAL_PORT7; + + pci_write_config32(dev, LPC_IO_PORT_DECODE_ENABLE, tmp); +} + #endif /* _HUDSON_EARLY_SETUP_C_ */ diff --git a/src/southbridge/amd/agesa/hudson/hudson.h b/src/southbridge/amd/agesa/hudson/hudson.h index 4927a3adfd..8a36ea2251 100644 --- a/src/southbridge/amd/agesa/hudson/hudson.h +++ b/src/southbridge/amd/agesa/hudson/hudson.h @@ -45,6 +45,46 @@ #define REV_HUDSON_A11 0x11 #define REV_HUDSON_A12 0x12 +#define LPC_IO_PORT_DECODE_ENABLE 0x44 +#define DECODE_ENABLE_PARALLEL_PORT0 BIT(0) +#define DECODE_ENABLE_PARALLEL_PORT1 BIT(1) +#define DECODE_ENABLE_PARALLEL_PORT2 BIT(2) +#define DECODE_ENABLE_PARALLEL_PORT3 BIT(3) +#define DECODE_ENABLE_PARALLEL_PORT4 BIT(4) +#define DECODE_ENABLE_PARALLEL_PORT5 BIT(5) +#define DECODE_ENABLE_SERIAL_PORT0 BIT(6) +#define DECODE_ENABLE_SERIAL_PORT1 BIT(7) +#define DECODE_ENABLE_SERIAL_PORT2 BIT(8) +#define DECODE_ENABLE_SERIAL_PORT3 BIT(9) +#define DECODE_ENABLE_SERIAL_PORT4 BIT(10) +#define DECODE_ENABLE_SERIAL_PORT5 BIT(11) +#define DECODE_ENABLE_SERIAL_PORT6 BIT(12) +#define DECODE_ENABLE_SERIAL_PORT7 BIT(13) +#define DECODE_ENABLE_AUDIO_PORT0 BIT(14) +#define DECODE_ENABLE_AUDIO_PORT1 BIT(15) +#define DECODE_ENABLE_AUDIO_PORT2 BIT(16) +#define DECODE_ENABLE_AUDIO_PORT3 BIT(17) +#define DECODE_ENABLE_MIDI_PORT0 BIT(18) +#define DECODE_ENABLE_MIDI_PORT1 BIT(19) +#define DECODE_ENABLE_MIDI_PORT2 BIT(20) +#define DECODE_ENABLE_MIDI_PORT3 BIT(21) +#define DECODE_ENABLE_MSS_PORT0 BIT(22) +#define DECODE_ENABLE_MSS_PORT1 BIT(23) +#define DECODE_ENABLE_MSS_PORT2 BIT(24) +#define DECODE_ENABLE_MSS_PORT3 BIT(25) +#define DECODE_ENABLE_FDC_PORT0 BIT(26) +#define DECODE_ENABLE_FDC_PORT1 BIT(27) +#define DECODE_ENABLE_GAME_PORT BIT(28) +#define DECODE_ENABLE_KBC_PORT BIT(29) +#define DECODE_ENABLE_ACPIUC_PORT BIT(30) +#define DECODE_ENABLE_ADLIB_PORT BIT(31) + +#define LPC_IO_OR_MEM_DECODE_ENABLE 0x48 + +#define LPC_TRUSTED_PLATFORM_MODULE 0x7c +#define TPM_12_EN BIT(0) +#define TPM_LEGACY_EN BIT(2) + #define SPIROM_BASE_ADDRESS_REGISTER 0xA0 #define SPI_ROM_ENABLE 0x02 #define SPI_BASE_ADDRESS 0xFEC10000 @@ -63,6 +103,7 @@ static inline int hudson_ide_enable(void) void hudson_lpc_port80(void); void hudson_pci_port80(void); +void hudson_lpc_decode(void); void hudson_clk_output_48Mhz(void); void hudson_enable(struct device *dev); diff --git a/src/southbridge/amd/pi/hudson/Makefile.inc b/src/southbridge/amd/pi/hudson/Makefile.inc index 0eccadb4f9..615fc048d6 100644 --- a/src/southbridge/amd/pi/hudson/Makefile.inc +++ b/src/southbridge/amd/pi/hudson/Makefile.inc @@ -28,7 +28,11 @@ # #***************************************************************************** -bootblock-y += enable_usbdebug.c +ifneq ($(CONFIG_ROMCC_BOOTBLOCK),y) +bootblock-y += bootblock.c +bootblock-y += early_setup.c +bootblock-$(CONFIG_USBDEBUG) += enable_usbdebug.c +endif romstage-y += early_setup.c romstage-y += enable_usbdebug.c diff --git a/src/southbridge/amd/pi/hudson/bootblock.c b/src/southbridge/amd/pi/hudson/bootblock.c index f12cec8602..e9a9d337c4 100644 --- a/src/southbridge/amd/pi/hudson/bootblock.c +++ b/src/southbridge/amd/pi/hudson/bootblock.c @@ -60,3 +60,50 @@ static void bootblock_southbridge_init(void) { hudson_enable_rom(); } + +#if !CONFIG(ROMCC_BOOTBLOCK) + +#include +#include +#include + +void bootblock_soc_early_init(void) +{ + pci_devfn_t dev; + u32 data; + + bootblock_southbridge_init(); + hudson_lpc_decode(); + if (CONFIG(SOUTHBRIDGE_AMD_PI_BOLTON)) + enable_acpimmio_decode_pm24(); + else + enable_acpimmio_decode_pm04(); + + dev = PCI_DEV(0, 0x14, 3); + data = pci_read_config32(dev, LPC_IO_OR_MEM_DECODE_ENABLE); + /* enable 0x2e/0x4e IO decoding for SuperIO */ + pci_write_config32(dev, LPC_IO_OR_MEM_DECODE_ENABLE, data | 3); + + /* + * Enable FCH to decode TPM associated Memory and IO regions for vboot + * + * Enable decoding of TPM cycles defined in TPM 1.2 spec + * Enable decoding of legacy TPM addresses: IO addresses 0x7f- + * 0x7e and 0xef-0xee. + */ + + data = pci_read_config32(dev, LPC_TRUSTED_PLATFORM_MODULE); + data |= TPM_12_EN | TPM_LEGACY_EN; + pci_write_config32(dev, LPC_TRUSTED_PLATFORM_MODULE, data); + + /* + * In Hudson RRG, PMIOxD2[5:4] is "Drive strength control for + * LpcClk[1:0]". This following register setting has been + * replicated in every reference design since Parmer, so it is + * believed to be required even though it is not documented in + * the SoC BKDGs. Without this setting, there is no serial + * output. + */ + pm_write8(0xd2, 0); +} +#endif diff --git a/src/southbridge/amd/pi/hudson/early_setup.c b/src/southbridge/amd/pi/hudson/early_setup.c index 3453021a5e..56b894c852 100644 --- a/src/southbridge/amd/pi/hudson/early_setup.c +++ b/src/southbridge/amd/pi/hudson/early_setup.c @@ -123,22 +123,17 @@ void hudson_lpc_port80(void) void hudson_lpc_decode(void) { pci_devfn_t dev; - u32 tmp = 0; + u32 tmp; - /* Enable I/O decode to LPC bus */ - dev = PCI_DEV(0, PCU_DEV, LPC_FUNC); - tmp = DECODE_ENABLE_PARALLEL_PORT0 | DECODE_ENABLE_PARALLEL_PORT2 - | DECODE_ENABLE_PARALLEL_PORT4 | DECODE_ENABLE_SERIAL_PORT0 - | DECODE_ENABLE_SERIAL_PORT1 | DECODE_ENABLE_SERIAL_PORT2 - | DECODE_ENABLE_SERIAL_PORT3 | DECODE_ENABLE_SERIAL_PORT4 - | DECODE_ENABLE_SERIAL_PORT5 | DECODE_ENABLE_SERIAL_PORT6 - | DECODE_ENABLE_SERIAL_PORT7 | DECODE_ENABLE_AUDIO_PORT0 - | DECODE_ENABLE_AUDIO_PORT1 | DECODE_ENABLE_AUDIO_PORT2 - | DECODE_ENABLE_AUDIO_PORT3 | DECODE_ENABLE_MSS_PORT2 - | DECODE_ENABLE_MSS_PORT3 | DECODE_ENABLE_FDC_PORT0 - | DECODE_ENABLE_FDC_PORT1 | DECODE_ENABLE_GAME_PORT - | DECODE_ENABLE_KBC_PORT | DECODE_ENABLE_ACPIUC_PORT - | DECODE_ENABLE_ADLIB_PORT; + dev = PCI_DEV(0, 0x14, 3); + /* Serial port numeration on Hudson: + * PORT0 - 0x3f8 + * PORT1 - 0x2f8 + * PORT5 - 0x2e8 + * PORT7 - 0x3e8 + */ + tmp = DECODE_ENABLE_SERIAL_PORT0 | DECODE_ENABLE_SERIAL_PORT1 + | DECODE_ENABLE_SERIAL_PORT5 | DECODE_ENABLE_SERIAL_PORT7; pci_write_config32(dev, LPC_IO_PORT_DECODE_ENABLE, tmp); } diff --git a/src/southbridge/amd/pi/hudson/hudson.h b/src/southbridge/amd/pi/hudson/hudson.h index ac35536bc2..6264319dd4 100644 --- a/src/southbridge/amd/pi/hudson/hudson.h +++ b/src/southbridge/amd/pi/hudson/hudson.h @@ -117,6 +117,10 @@ #define LPC_ALT_WIDEIO1_ENABLE BIT(2) #define LPC_ALT_WIDEIO0_ENABLE BIT(0) +#define LPC_TRUSTED_PLATFORM_MODULE 0x7c +#define TPM_12_EN BIT(0) +#define TPM_LEGACY_EN BIT(2) + #define LPC_WIDEIO2_GENERIC_PORT 0x90 #define SPI_CNTRL0 0x00 From 08cd65198e44a5c26ba8f1f5439fbf7475fb0ed0 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Micha=C5=82=20=C5=BBygowski?= Date: Thu, 28 Nov 2019 14:14:52 +0100 Subject: [PATCH 0538/1242] sb/amd/cimx/sb800: add C bootblock southbridge initialization MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit TEST=boot PC Engines apu1 with C bootblock patch and launch Debian with Linux kernel 4.14.50 Signed-off-by: Michał Żygowski Change-Id: Ie81198f5034a84d319ee7143aa032433f82be254 Reviewed-on: https://review.coreboot.org/c/coreboot/+/37329 Reviewed-by: Kyösti Mälkki Tested-by: build bot (Jenkins) --- src/southbridge/amd/cimx/sb800/Makefile.inc | 4 ++++ src/southbridge/amd/cimx/sb800/bootblock.c | 23 +++++++++++++++++---- 2 files changed, 23 insertions(+), 4 deletions(-) diff --git a/src/southbridge/amd/cimx/sb800/Makefile.inc b/src/southbridge/amd/cimx/sb800/Makefile.inc index 418110b5e0..ccb3a2a744 100644 --- a/src/southbridge/amd/cimx/sb800/Makefile.inc +++ b/src/southbridge/amd/cimx/sb800/Makefile.inc @@ -16,6 +16,10 @@ # SB800 Platform Files +ifneq ($(CONFIG_ROMCC_BOOTBLOCK),y) +bootblock-y += bootblock.c +endif + romstage-y += cfg.c romstage-y += early.c romstage-y += smbus.c smbus_spd.c diff --git a/src/southbridge/amd/cimx/sb800/bootblock.c b/src/southbridge/amd/cimx/sb800/bootblock.c index 28b37c30f4..b4f03dad7e 100644 --- a/src/southbridge/amd/cimx/sb800/bootblock.c +++ b/src/southbridge/amd/cimx/sb800/bootblock.c @@ -79,18 +79,21 @@ static void enable_spi_fast_mode(void) pci_io_write_config32(dev, 0xa0, save); } -static void enable_clocks(void) +static void enable_acpimmio_decode_pm24(void) { u8 reg8; - u32 reg32; - volatile u32 *acpi_mmio = (void *) (0xFED80000 + 0xE00 + 0x40); - // Program AcpiMmioEn to enable MMIO access to MiscCntrl register outb(0x24, 0xCD6); reg8 = inb(0xCD7); reg8 |= 1; reg8 &= ~(1 << 1); outb(reg8, 0xCD7); +} + +static void enable_clocks(void) +{ + u32 reg32; + volatile u32 *acpi_mmio = (void *) (0xFED80000 + 0xE00 + 0x40); // Program SB800 MiscClkCntrl register to configure clock output on the // 14M_25M_48M_OSC ball usually used for the Super-I/O. @@ -112,5 +115,17 @@ static void bootblock_southbridge_init(void) enable_rom(); enable_prefetch(); enable_spi_fast_mode(); + + // Program AcpiMmioEn to enable MMIO access to MiscCntrl register + enable_acpimmio_decode_pm24(); enable_clocks(); } + +#if !CONFIG(ROMCC_BOOTBLOCK) +#include + +void bootblock_soc_early_init(void) +{ + bootblock_southbridge_init(); +} +#endif From 0e03aa2c6f54210b99cd8149c7118b43c43381cd Mon Sep 17 00:00:00 2001 From: Taniya Das Date: Wed, 7 Aug 2019 11:28:28 +0530 Subject: [PATCH 0539/1242] sc7180: Add clock driver Add support for clock driver for SC7180 Developer/Reviewer, be aware of this patch from Napali: https://review.coreboot.org/c/coreboot/+/31083/6 Change-Id: I3f39252c887c36e8af43bc49289795000e4638d8 Signed-off-by: Taniya Das Reviewed-on: https://review.coreboot.org/c/coreboot/+/35496 Tested-by: build bot (Jenkins) Reviewed-by: Julius Werner --- src/soc/qualcomm/sc7180/Makefile.inc | 4 + src/soc/qualcomm/sc7180/bootblock.c | 2 + src/soc/qualcomm/sc7180/clock.c | 227 ++++++++++++++++++ .../qualcomm/sc7180/include/soc/addressmap.h | 2 +- src/soc/qualcomm/sc7180/include/soc/clock.h | 214 +++++++++++++++++ 5 files changed, 448 insertions(+), 1 deletion(-) create mode 100644 src/soc/qualcomm/sc7180/clock.c create mode 100644 src/soc/qualcomm/sc7180/include/soc/clock.h diff --git a/src/soc/qualcomm/sc7180/Makefile.inc b/src/soc/qualcomm/sc7180/Makefile.inc index 6d2a3e7c08..6b492d5784 100644 --- a/src/soc/qualcomm/sc7180/Makefile.inc +++ b/src/soc/qualcomm/sc7180/Makefile.inc @@ -8,12 +8,14 @@ bootblock-y += timer.c bootblock-y += spi.c bootblock-y += gpio.c bootblock-$(CONFIG_DRIVERS_UART) += uart_bitbang.c +bootblock-y += clock.c ################################################################################ verstage-y += timer.c verstage-y += spi.c verstage-y += gpio.c verstage-$(CONFIG_DRIVERS_UART) += uart_bitbang.c +verstage-y += clock.c ################################################################################ romstage-y += cbmem.c @@ -25,6 +27,7 @@ romstage-y += mmu.c romstage-y += spi.c romstage-y += gpio.c romstage-$(CONFIG_DRIVERS_UART) += uart_bitbang.c +romstage-y += clock.c ################################################################################ ramstage-y += soc.c @@ -32,6 +35,7 @@ ramstage-y += timer.c ramstage-y += spi.c ramstage-y += gpio.c ramstage-$(CONFIG_DRIVERS_UART) += uart_bitbang.c +ramstage-y += clock.c ################################################################################ diff --git a/src/soc/qualcomm/sc7180/bootblock.c b/src/soc/qualcomm/sc7180/bootblock.c index b9b86609ad..bf80bff706 100644 --- a/src/soc/qualcomm/sc7180/bootblock.c +++ b/src/soc/qualcomm/sc7180/bootblock.c @@ -14,9 +14,11 @@ */ #include +#include #include void bootblock_soc_init(void) { sc7180_mmu_init(); + clock_init(); } diff --git a/src/soc/qualcomm/sc7180/clock.c b/src/soc/qualcomm/sc7180/clock.c new file mode 100644 index 0000000000..97b7b280ca --- /dev/null +++ b/src/soc/qualcomm/sc7180/clock.c @@ -0,0 +1,227 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2019 Qualcomm Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include +#include +#include + +#define DIV(div) (2 * div - 1) + +struct clock_config qup_cfg[] = { + { + .hz = 7372800, + .src = SRC_GPLL0_EVEN_300MHZ, + .div = DIV(1), + .m = 384, + .n = 15625, + .d_2 = 15625, + }, + { + .hz = SRC_XO_HZ, /* 19.2KHz */ + .src = SRC_XO_19_2MHZ, + .div = DIV(1), + } +}; + +struct clock_config qspi_core_cfg[] = { + { + .hz = SRC_XO_HZ, /* 19.2KHz */ + .src = SRC_XO_19_2MHZ, + .div = DIV(1), + }, + { + .hz = 100 * MHz, + .src = SRC_GPLL0_EVEN_300MHZ, + .div = DIV(3), + }, + { + .hz = 150 * MHz, + .src = SRC_GPLL0_EVEN_300MHZ, + .div = DIV(2), + }, + { + .hz = GPLL0_EVEN_HZ, /* 300MHz */ + .src = SRC_GPLL0_EVEN_300MHZ, + .div = DIV(1), + } +}; + +static int clock_configure_gpll0(void) +{ + setbits_le32(&gcc->gpll0.user_ctl_u, 1 << SCALE_FREQ_SHFT); + + /* Keep existing GPLL0 configuration, in RUN mode @600Mhz. */ + setbits_le32(&gcc->gpll0.user_ctl, + 1 << CLK_CTL_GPLL_PLLOUT_EVEN_SHFT | + 1 << CLK_CTL_GPLL_PLLOUT_MAIN_SHFT | + 1 << CLK_CTL_GPLL_PLLOUT_ODD_SHFT); + + return 0; +} + +static int clock_configure_mnd(struct sc7180_clock *clk, uint32_t m, uint32_t n, + uint32_t d_2) +{ + struct sc7180_mnd_clock *mnd = (struct sc7180_mnd_clock *)clk; + setbits_le32(&clk->rcg_cfg, + RCG_MODE_DUAL_EDGE << CLK_CTL_CFG_MODE_SHFT); + + write32(&mnd->m, m & CLK_CTL_RCG_MND_BMSK); + write32(&mnd->n, ~(n-m) & CLK_CTL_RCG_MND_BMSK); + write32(&mnd->d_2, ~(d_2) & CLK_CTL_RCG_MND_BMSK); + + return 0; +} + +static int clock_configure(struct sc7180_clock *clk, + struct clock_config *clk_cfg, + uint32_t hz, uint32_t num_perfs) +{ + uint32_t reg_val; + uint32_t idx; + + for (idx = 0; idx < num_perfs; idx++) + if (hz <= clk_cfg[idx].hz) + break; + + assert(hz == clk_cfg[idx].hz); + + reg_val = (clk_cfg[idx].src << CLK_CTL_CFG_SRC_SEL_SHFT) | + (clk_cfg[idx].div << CLK_CTL_CFG_SRC_DIV_SHFT); + + /* Set clock config */ + write32(&clk->rcg_cfg, reg_val); + + if (clk_cfg[idx].m != 0) + clock_configure_mnd(clk, clk_cfg[idx].m, clk_cfg[idx].n, + clk_cfg[idx].d_2); + + /* Commit config to RCG*/ + setbits_le32(&clk->rcg_cmd, BIT(CLK_CTL_CMD_UPDATE_SHFT)); + + return 0; +} + +static bool clock_is_off(u32 *cbcr_addr) +{ + return (read32(cbcr_addr) & CLK_CTL_CBC_CLK_OFF_BMSK); +} + +static int clock_enable_vote(void *cbcr_addr, void *vote_addr, + uint32_t vote_bit) +{ + /* Set clock vote bit */ + setbits_le32(vote_addr, BIT(vote_bit)); + + /* Ensure clock is enabled */ + while (clock_is_off(cbcr_addr)) + ; + + return 0; +} + +static int clock_enable(void *cbcr_addr) +{ + /* Set clock enable bit */ + setbits_le32(cbcr_addr, BIT(CLK_CTL_CBC_CLK_EN_SHFT)); + + /* Ensure clock is enabled */ + while (clock_is_off(cbcr_addr)) + ; + + return 0; +} + +void clock_reset_aop(void) +{ + /* Bring AOP out of RESET */ + clrbits_le32(&aoss->aoss_cc_apcs_misc, BIT(AOP_RESET_SHFT)); +} + +void clock_configure_qspi(uint32_t hz) +{ + clock_configure(&gcc->qspi_core, + qspi_core_cfg, hz, + ARRAY_SIZE(qspi_core_cfg)); + clock_enable(&gcc->qspi_cnoc_ahb_cbcr); + clock_enable(&gcc->qspi_core.cbcr); +} + +int clock_reset_bcr(void *bcr_addr, bool reset) +{ + struct sc7180_bcr *bcr = bcr_addr; + + if (reset) + setbits_le32(bcr, BIT(CLK_CTL_BCR_BLK_ARES_SHFT)); + else + clrbits_le32(bcr, BIT(CLK_CTL_BCR_BLK_ARES_SHFT)); + + return 0; +} + +void clock_configure_qup(int qup, uint32_t hz) +{ + int s = qup % QUP_WRAP1_S0; + struct sc7180_qupv3_clock *qup_clk = qup < QUP_WRAP1_S0 ? + &gcc->qup_wrap0_s[s] : &gcc->qup_wrap1_s[s]; + + clock_configure(&qup_clk->mnd_clk.clock, qup_cfg, hz, + ARRAY_SIZE(qup_cfg)); +} + +void clock_enable_qup(int qup) +{ + int s = qup % QUP_WRAP1_S0; + int clk_en_off = qup < QUP_WRAP1_S0 ? + QUPV3_WRAP0_CLK_ENA_S(s) : QUPV3_WRAP1_CLK_ENA_S(s); + struct sc7180_qupv3_clock *qup_clk = qup < QUP_WRAP1_S0 ? + &gcc->qup_wrap0_s[s] : &gcc->qup_wrap1_s[s]; + + clock_enable_vote(&qup_clk->mnd_clk, &gcc->apcs_clk_br_en1, + clk_en_off); +} + +void clock_init(void) +{ + clock_configure_gpll0(); + + clock_enable_vote(&gcc->qup_wrap0_core_2x.cbcr, + &gcc->apcs_clk_br_en1, + QUPV3_WRAP0_CORE_2X_CLK_ENA); + clock_enable_vote(&gcc->qup_wrap0_core_cbcr, + &gcc->apcs_clk_br_en1, + QUPV3_WRAP0_CORE_CLK_ENA); + clock_enable_vote(&gcc->qup_wrap0_m_ahb_cbcr, + &gcc->apcs_clk_br_en1, + QUPV3_WRAP_0_M_AHB_CLK_ENA); + clock_enable_vote(&gcc->qup_wrap0_s_ahb_cbcr, + &gcc->apcs_clk_br_en1, + QUPV3_WRAP_0_S_AHB_CLK_ENA); + + clock_enable_vote(&gcc->qup_wrap1_core_2x_cbcr, + &gcc->apcs_clk_br_en1, + QUPV3_WRAP1_CORE_2X_CLK_ENA); + clock_enable_vote(&gcc->qup_wrap1_core_cbcr, + &gcc->apcs_clk_br_en1, + QUPV3_WRAP1_CORE_CLK_ENA); + clock_enable_vote(&gcc->qup_wrap1_m_ahb_cbcr, + &gcc->apcs_clk_br_en1, + QUPV3_WRAP_1_M_AHB_CLK_ENA); + clock_enable_vote(&gcc->qup_wrap1_s_ahb_cbcr, + &gcc->apcs_clk_br_en1, + QUPV3_WRAP_1_S_AHB_CLK_ENA); +} diff --git a/src/soc/qualcomm/sc7180/include/soc/addressmap.h b/src/soc/qualcomm/sc7180/include/soc/addressmap.h index ffacf55681..e3941899f6 100644 --- a/src/soc/qualcomm/sc7180/include/soc/addressmap.h +++ b/src/soc/qualcomm/sc7180/include/soc/addressmap.h @@ -1,7 +1,7 @@ /* * This file is part of the coreboot project. * - * Copyright (c) 2018-2019 Qualcomm Technologies + * Copyright (c) 2019 Qualcomm Technologies * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and diff --git a/src/soc/qualcomm/sc7180/include/soc/clock.h b/src/soc/qualcomm/sc7180/include/soc/clock.h new file mode 100644 index 0000000000..39cde8c1bc --- /dev/null +++ b/src/soc/qualcomm/sc7180/include/soc/clock.h @@ -0,0 +1,214 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2019 Qualcomm Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include + +#ifndef __SOC_QUALCOMM_SC7180_CLOCK_H__ +#define __SOC_QUALCOMM_SC7180_CLOCK_H__ + +#define QUPV3_WRAP_0_M_AHB_CLK_ENA 6 +#define QUPV3_WRAP_0_S_AHB_CLK_ENA 7 +#define QUPV3_WRAP0_CORE_2X_CLK_ENA 9 +#define QUPV3_WRAP0_CORE_CLK_ENA 8 +#define QUPV3_WRAP1_CORE_2X_CLK_ENA 18 +#define QUPV3_WRAP1_CORE_CLK_ENA 19 +#define QUPV3_WRAP_1_M_AHB_CLK_ENA 20 +#define QUPV3_WRAP_1_S_AHB_CLK_ENA 21 +#define QUPV3_WRAP0_CLK_ENA_S(idx) (10 + idx) +#define QUPV3_WRAP1_CLK_ENA_S(idx) (22 + idx) + +#define SRC_XO_HZ (19200 * KHz) +#define GPLL0_EVEN_HZ (300 * MHz) +#define GPLL0_MAIN_HZ (600 * MHz) + +#define SRC_XO_19_2MHZ 0 +#define SRC_GPLL0_MAIN_600MHZ 1 +#define SRC_GPLL0_EVEN_300MHZ 6 + +#define AOP_RESET_SHFT 0 +#define RCG_MODE_DUAL_EDGE 2 + +#define SCALE_FREQ_SHFT 11 + +struct sc7180_clock { + u32 cbcr; + u32 rcg_cmd; + u32 rcg_cfg; +}; + +struct sc7180_mnd_clock { + struct sc7180_clock clock; + u32 m; + u32 n; + u32 d_2; +}; + +struct sc7180_qupv3_clock { + struct sc7180_mnd_clock mnd_clk; + u8 _res[0x130 - 0x18]; +}; + +struct sc7180_gpll { + u32 mode; + u32 l_val; + u32 cal_l_val; + u32 user_ctl; + u32 user_ctl_u; + u32 config_ctl; + u32 config_ctl_u; + u32 test_ctl; + u32 test_ctl_u; + u8 _res[0x1000 - 0x24]; +}; + +struct sc7180_gcc { + struct sc7180_gpll gpll0; + u8 _res0[0xf000 - 0x1000]; + u32 usb30_prim_bcr; + u8 _res1[0x17000 - 0xf004]; + u32 qup_wrap0_bcr; + u32 qup_wrap0_m_ahb_cbcr; + u32 qup_wrap0_s_ahb_cbcr; + u32 qup_wrap0_core_cbcr; + u32 qup_wrap0_core_cdivr; + struct sc7180_clock qup_wrap0_core_2x; + u8 _res2[0x17030 - 0x17020]; + struct sc7180_qupv3_clock qup_wrap0_s[6]; + u8 _res3[0x18000 - 0x17750]; + u32 qup_wrap1_bcr; + u32 qup_wrap1_core_2x_cbcr; + u32 qup_wrap1_core_cbcr; + u32 qup_wrap1_m_ahb_cbcr; + u32 qup_wrap1_s_ahb_cbcr; + struct sc7180_qupv3_clock qup_wrap1_s[6]; + u8 _res4[0x18994 - 0x18734]; + u32 qup_wrap1_core_cdivr; + u8 _res5[0x26000 - 0x18998]; + u32 qusb2phy_prim_bcr; + u8 _res6[0x4b000 - 0x26004]; + u32 qspi_bcr; + u32 qspi_cnoc_ahb_cbcr; + struct sc7180_clock qspi_core; + u8 _res7[0x50000 - 0x4b014]; + u32 usb3_phy_prim_bcr; + u32 usb3phy_phy_prim_bcr; + u32 usb3_dp_phy_prim_bcr; + u32 usb3_phy_sec_bcr; + u32 usb3phy_phy_sec_bcr; + u32 usb3_dp_phy_sec_bcr; + u8 _res8[0x52008 - 0x50018]; + u32 apcs_clk_br_en1; + u8 _res9[0x1000000 - 0x5200c]; +}; +check_member(sc7180_gcc, usb30_prim_bcr, 0xf000); +check_member(sc7180_gcc, qup_wrap0_bcr, 0x17000); +check_member(sc7180_gcc, qup_wrap1_bcr, 0x18000); +check_member(sc7180_gcc, qup_wrap1_core_cdivr, 0x18994); +check_member(sc7180_gcc, qusb2phy_prim_bcr, 0x26000); +check_member(sc7180_gcc, usb3phy_phy_prim_bcr, 0x50004); +check_member(sc7180_gcc, usb3_phy_prim_bcr, 0x50000); +check_member(sc7180_gcc, apcs_clk_br_en1, 0x52008); + +struct sc7180_aoss { + u8 _res[0x5002c]; + u32 aoss_cc_apcs_misc; +}; + +enum clk_ctl_gpll_user_ctl { + CLK_CTL_GPLL_PLLOUT_EVEN_BMSK = 0x2, + CLK_CTL_GPLL_PLLOUT_MAIN_SHFT = 0, + CLK_CTL_GPLL_PLLOUT_EVEN_SHFT = 1, + CLK_CTL_GPLL_PLLOUT_ODD_SHFT = 2 +}; + +enum clk_ctl_cfg_rcgr { + CLK_CTL_CFG_HW_CTL_BMSK = 0x100000, + CLK_CTL_CFG_HW_CTL_SHFT = 20, + CLK_CTL_CFG_MODE_BMSK = 0x3000, + CLK_CTL_CFG_MODE_SHFT = 12, + CLK_CTL_CFG_SRC_SEL_BMSK = 0x700, + CLK_CTL_CFG_SRC_SEL_SHFT = 8, + CLK_CTL_CFG_SRC_DIV_BMSK = 0x1F, + CLK_CTL_CFG_SRC_DIV_SHFT = 0 +}; + +enum clk_ctl_cmd_rcgr { + CLK_CTL_CMD_ROOT_OFF_BMSK = 0x80000000, + CLK_CTL_CMD_ROOT_OFF_SHFT = 31, + CLK_CTL_CMD_ROOT_EN_BMSK = 0x2, + CLK_CTL_CMD_ROOT_EN_SHFT = 1, + CLK_CTL_CMD_UPDATE_BMSK = 0x1, + CLK_CTL_CMD_UPDATE_SHFT = 0 +}; + +enum clk_ctl_cbcr { + CLK_CTL_CBC_CLK_OFF_BMSK = 0x80000000, + CLK_CTL_CBC_CLK_OFF_SHFT = 31, + CLK_CTL_CBC_CLK_EN_BMSK = 0x1, + CLK_CTL_CBC_CLK_EN_SHFT = 0 +}; + +enum clk_ctl_rcg_mnd { + CLK_CTL_RCG_MND_BMSK = 0xFFFF, + CLK_CTL_RCG_MND_SHFT = 0, +}; + +enum clk_ctl_bcr { + CLK_CTL_BCR_BLK_ARES_BMSK = 0x1, + CLK_CTL_BCR_BLK_ARES_SHFT = 0, +}; + +enum clk_qup { + QUP_WRAP0_S0, + QUP_WRAP0_S1, + QUP_WRAP0_S2, + QUP_WRAP0_S3, + QUP_WRAP0_S4, + QUP_WRAP0_S5, + QUP_WRAP1_S0, + QUP_WRAP1_S1, + QUP_WRAP1_S2, + QUP_WRAP1_S3, + QUP_WRAP1_S4, + QUP_WRAP1_S5, +}; + +struct clock_config { + uint32_t hz; + uint8_t src; + uint8_t div; + uint16_t m; + uint16_t n; + uint16_t d_2; +}; + +struct mdss_clock_config { + const char *clk_name; + uintptr_t rcgr; + uintptr_t cbcr; +}; + +static struct sc7180_gcc *const gcc = (void *)GCC_BASE; +static struct sc7180_aoss *const aoss = (void *)AOSS_CC_BASE; + +void clock_init(void); +void clock_reset_aop(void); +void clock_configure_qspi(uint32_t hz); +int clock_reset_bcr(void *bcr_addr, bool reset); +void clock_configure_qup(int qup, uint32_t hz); +void clock_enable_qup(int qup); + +#endif // __SOC_QUALCOMM_SC7180_CLOCK_H__ From b1ea707bdaf064ae1d2427e5e3c20d2ab66bf93d Mon Sep 17 00:00:00 2001 From: Kane Chen Date: Mon, 2 Dec 2019 07:02:43 +0000 Subject: [PATCH 0540/1242] Revert "mb/google/hatch: Enable PchPmSlpS0Vm075VSupport for hatch" This reverts commit 0bc35af93326ec3232ec73c9b1334241b85f0252. Reason for revert: This change breaks runtime s0ix. BRANCH=hatch BUG=b:141831197 TEST=Check slp_s0 residency increased when system is idle. Change-Id: Ida80f55b56de7129ed629eb29bd14f2ef300126f Signed-off-by: Kane Chen Reviewed-on: https://review.coreboot.org/c/coreboot/+/37088 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh --- src/mainboard/google/hatch/variants/baseboard/devicetree.cb | 2 -- 1 file changed, 2 deletions(-) diff --git a/src/mainboard/google/hatch/variants/baseboard/devicetree.cb b/src/mainboard/google/hatch/variants/baseboard/devicetree.cb index a2831e1bba..7382209264 100644 --- a/src/mainboard/google/hatch/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/hatch/variants/baseboard/devicetree.cb @@ -58,8 +58,6 @@ chip soc/intel/cannonlake register "PmTimerDisabled" = "1" - register "PchPmSlpS0Vm075VSupport" = "1" - # VR Settings Configuration for 4 Domains #+----------------+-------+-------+-------+-------+ #| Domain/Setting | SA | IA | GTUS | GTS | From 2f50d7cd3bac409390b3e3131650a5c5b26a4e0b Mon Sep 17 00:00:00 2001 From: Maxim Polyakov Date: Wed, 4 Dec 2019 19:38:12 +0300 Subject: [PATCH 0541/1242] mb/asrock/h110m: disable CLKREQ to use onboard LAN The PCH uses the SRCCLKREQ# pin to detect PCIe device in the slot in order to send clock signal to it. However, this logic is not required for the Realtek LAN device, since this chip is soldered to the board and always uses clocking. The chipset can't receive the clock request signal (most likely this pin isn't connected) and doesn't enable the CLK. For this reason, the device is broken during the initialization phase. The patch disables clock request logic for the PCH PCIe port 6 to initialize the onboard LAN device correctly. Change-Id: I5cbce6177c89052eb50959f43903b6f8a607e77f Signed-off-by: Maxim Polyakov Reviewed-on: https://review.coreboot.org/c/coreboot/+/36377 Reviewed-by: Patrick Rudolph Tested-by: build bot (Jenkins) --- src/mainboard/asrock/h110m/devicetree.cb | 6 ++---- 1 file changed, 2 insertions(+), 4 deletions(-) diff --git a/src/mainboard/asrock/h110m/devicetree.cb b/src/mainboard/asrock/h110m/devicetree.cb index bd51e40bf3..bf4bec0e5e 100644 --- a/src/mainboard/asrock/h110m/devicetree.cb +++ b/src/mainboard/asrock/h110m/devicetree.cb @@ -219,10 +219,8 @@ chip soc/intel/skylake # Enable Root port 6(x1) for LAN. register "PcieRpEnable[5]" = "1" - # Enable CLKREQ# - register "PcieRpClkReqSupport[5]" = "1" - # Use SRCCLKREQ1# - register "PcieRpClkReqNumber[5]" = "1" + # Disable CLKREQ#, since onboard LAN is always present + register "PcieRpClkReqSupport[5]" = "0" # Enable Advanced Error Reporting register "PcieRpAdvancedErrorReporting[5]" = "1" # Enable Latency Tolerance Reporting Mechanism From 9a669b1c689cce4b473927855f9b4a416fd5453f Mon Sep 17 00:00:00 2001 From: Elyes HAOUAS Date: Thu, 5 Dec 2019 09:14:30 +0100 Subject: [PATCH 0542/1242] superio/{aspeed,nuvoton}: Fix typo Change-Id: I7772fadc756ceeef5988e4b1ecf8f93ad3605a84 Signed-off-by: Elyes HAOUAS Reviewed-on: https://review.coreboot.org/c/coreboot/+/37502 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel Reviewed-by: Felix Held --- src/superio/aspeed/ast2400/superio.c | 6 +++--- src/superio/nuvoton/nct6791d/superio.c | 2 +- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/src/superio/aspeed/ast2400/superio.c b/src/superio/aspeed/ast2400/superio.c index c5df8b5833..a41bba787e 100644 --- a/src/superio/aspeed/ast2400/superio.c +++ b/src/superio/aspeed/ast2400/superio.c @@ -48,9 +48,9 @@ static const char *ast2400_acpi_hid(const struct device *dev) return NULL; switch (dev->path.pnp.device & 0xff) { - case AST2400_SUART1: /* falltrough */ - case AST2400_SUART2: /* falltrough */ - case AST2400_SUART3: /* falltrough */ + case AST2400_SUART1: /* fallthrough */ + case AST2400_SUART2: /* fallthrough */ + case AST2400_SUART3: /* fallthrough */ case AST2400_SUART4: return ACPI_HID_COM; case AST2400_KBC: diff --git a/src/superio/nuvoton/nct6791d/superio.c b/src/superio/nuvoton/nct6791d/superio.c index 08f0bfa3a6..ed8f5c3659 100644 --- a/src/superio/nuvoton/nct6791d/superio.c +++ b/src/superio/nuvoton/nct6791d/superio.c @@ -48,7 +48,7 @@ static const char *nct6791d_acpi_hid(const struct device *dev) return NULL; switch (dev->path.pnp.device & 0xff) { - case NCT6791D_SP1: /* falltrough */ + case NCT6791D_SP1: /* fallthrough */ case NCT6791D_SP2: return ACPI_HID_COM; case NCT6791D_KBC: From b21999cbede5fc24ec28c47b0c89a4eb08f1ccad Mon Sep 17 00:00:00 2001 From: Elyes HAOUAS Date: Thu, 5 Dec 2019 10:02:10 +0100 Subject: [PATCH 0543/1242] superio/ite/it8528e: Fix typo Change-Id: I40035bf622fea2ff7aed74dce125cbf6265afa6e Signed-off-by: Elyes HAOUAS Reviewed-on: https://review.coreboot.org/c/coreboot/+/37505 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel Reviewed-by: Felix Held --- src/superio/ite/it8528e/it8528e.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/superio/ite/it8528e/it8528e.h b/src/superio/ite/it8528e/it8528e.h index d9d07d0188..a065b7d5de 100644 --- a/src/superio/ite/it8528e/it8528e.h +++ b/src/superio/ite/it8528e/it8528e.h @@ -27,7 +27,7 @@ #define IT8528E_RTCT 0x10 /* RTC-like Timer */ #define IT8528E_PMC1 0x11 /* Power Management Channel 1 */ #define IT8528E_PMC2 0x12 /* Power Management Channel 2 */ -#define IT8528E_SSPI 0x13 /* Serial Periphial Interface */ +#define IT8528E_SSPI 0x13 /* Serial Peripheral Interface */ #define IT8528E_PECI 0x14 /* Platform EC Interface */ #define IT8528E_PMC3 0x17 /* Power Management Channel 3 */ #define IT8528E_PMC4 0x18 /* Power Management Channel 4 */ From 36c6f956029178fd78d7b2f3ebfddc264078fec7 Mon Sep 17 00:00:00 2001 From: Elyes HAOUAS Date: Thu, 5 Dec 2019 11:05:19 +0100 Subject: [PATCH 0544/1242] superio/smsc/lpc47n2{17,27}: Fix typo Change-Id: I29a42908af5699200216b7a0082e1417c90c95a6 Signed-off-by: Elyes HAOUAS Reviewed-on: https://review.coreboot.org/c/coreboot/+/37510 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel Reviewed-by: Felix Held --- src/superio/smsc/lpc47n217/early_serial.c | 2 +- src/superio/smsc/lpc47n227/early_serial.c | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/src/superio/smsc/lpc47n217/early_serial.c b/src/superio/smsc/lpc47n217/early_serial.c index 5fb8d7fcdb..8037ee890d 100644 --- a/src/superio/smsc/lpc47n217/early_serial.c +++ b/src/superio/smsc/lpc47n217/early_serial.c @@ -69,7 +69,7 @@ static void lpc47n217_pnp_set_iobase(pnp_devfn_t dev, u16 iobase) * true base port is programmed (see lpc47n217_enable_serial() below). * * @param dev High 8 bits = Super I/O port, low 8 bits = logical device number. - * @param enable 0 to disable, anythig else to enable. + * @param enable 0 to disable, anything else to enable. */ static void lpc47n217_pnp_set_enable(pnp_devfn_t dev, int enable) { diff --git a/src/superio/smsc/lpc47n227/early_serial.c b/src/superio/smsc/lpc47n227/early_serial.c index 42213b74cc..9e6ecd7d13 100644 --- a/src/superio/smsc/lpc47n227/early_serial.c +++ b/src/superio/smsc/lpc47n227/early_serial.c @@ -73,7 +73,7 @@ static void lpc47n227_pnp_set_iobase(pnp_devfn_t dev, u16 iobase) * true base port is programmed (see lpc47n227_enable_serial() below). * * @param dev High 8 bits = Super I/O port, low 8 bits = logical device number. - * @param enable 0 to disable, anythig else to enable. + * @param enable 0 to disable, anything else to enable. */ static void lpc47n227_pnp_set_enable(pnp_devfn_t dev, int enable) { From e46a41542b8c2b0ecef154fe0083863697cdbcb1 Mon Sep 17 00:00:00 2001 From: Elyes HAOUAS Date: Thu, 5 Dec 2019 10:48:17 +0100 Subject: [PATCH 0545/1242] superio/serverengines/pilot: Fix typo Change-Id: Ic7cd93150252b2e5235c82c8c63540059b68d22b Signed-off-by: Elyes HAOUAS Reviewed-on: https://review.coreboot.org/c/coreboot/+/37508 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel Reviewed-by: Felix Held --- src/superio/serverengines/pilot/early_serial.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/superio/serverengines/pilot/early_serial.c b/src/superio/serverengines/pilot/early_serial.c index 555e4f5156..3c140fb8c9 100644 --- a/src/superio/serverengines/pilot/early_serial.c +++ b/src/superio/serverengines/pilot/early_serial.c @@ -22,7 +22,7 @@ #include #include "pilot.h" -/* Pilot uses 0x5A/0xA5 pattern to actiavte deactivate config access. */ +/* Pilot uses 0x5A/0xA5 pattern to activate deactivate config access. */ void pnp_enter_ext_func_mode(pnp_devfn_t dev) { u16 port = dev >> 8; From 7e51f15129b67407b2803f1b229b7d873a598d6b Mon Sep 17 00:00:00 2001 From: Elyes HAOUAS Date: Thu, 5 Dec 2019 09:51:57 +0100 Subject: [PATCH 0546/1242] superio/fintek/f81866d: capitalize 'TODO' Change-Id: I2879a8739012863837e23e60fed5eb6ee209dea0 Signed-off-by: Elyes HAOUAS Reviewed-on: https://review.coreboot.org/c/coreboot/+/37504 Tested-by: build bot (Jenkins) Reviewed-by: Felix Held --- src/superio/fintek/f81866d/f81866d_hwm.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/superio/fintek/f81866d/f81866d_hwm.c b/src/superio/fintek/f81866d/f81866d_hwm.c index 8b6435ca5d..1b499689b1 100644 --- a/src/superio/fintek/f81866d/f81866d_hwm.c +++ b/src/superio/fintek/f81866d/f81866d_hwm.c @@ -17,7 +17,7 @@ */ /* Setup only for Fan2 - * Todo: Add support for Fan1 and Fan3 + * TODO: Add support for Fan1 and Fan3 */ #include From 634c783d1fbee4a9dee7a04c8d2e21d8b6d18e3c Mon Sep 17 00:00:00 2001 From: Akash Asthana Date: Mon, 29 Jul 2019 18:11:15 +0530 Subject: [PATCH 0547/1242] sc7180: Add SPI-NOR support This implements the SPI-NOR driver for the Qualcomm QSPI core. Developer/Reviewer, be aware of this patch from Napali: https://review.coreboot.org/c/coreboot/+/27483/58 Change-Id: I2eb8cf90aa4559541ba293b3fd2870896bed20b7 Signed-off-by: Akash Asthana Reviewed-on: https://review.coreboot.org/c/coreboot/+/35501 Reviewed-by: Patrick Georgi Reviewed-by: Julius Werner Tested-by: build bot (Jenkins) --- src/soc/qualcomm/sc7180/Kconfig | 9 + src/soc/qualcomm/sc7180/Makefile.inc | 4 + src/soc/qualcomm/sc7180/bootblock.c | 2 + src/soc/qualcomm/sc7180/include/soc/qspi.h | 121 ++++++++ src/soc/qualcomm/sc7180/qspi.c | 306 +++++++++++++++++++++ src/soc/qualcomm/sc7180/spi.c | 13 +- 6 files changed, 452 insertions(+), 3 deletions(-) create mode 100644 src/soc/qualcomm/sc7180/include/soc/qspi.h create mode 100644 src/soc/qualcomm/sc7180/qspi.c diff --git a/src/soc/qualcomm/sc7180/Kconfig b/src/soc/qualcomm/sc7180/Kconfig index 70737e9379..4093c93213 100644 --- a/src/soc/qualcomm/sc7180/Kconfig +++ b/src/soc/qualcomm/sc7180/Kconfig @@ -22,4 +22,13 @@ config VBOOT select VBOOT_MUST_REQUEST_DISPLAY select VBOOT_STARTS_IN_BOOTBLOCK +config SC7180_QSPI + bool + default y if COMMON_CBFS_SPI_WRAPPER + prompt "Build Flash Using SPI-NOR" + +config BOOT_DEVICE_SPI_FLASH_BUS + int + default 16 + endif diff --git a/src/soc/qualcomm/sc7180/Makefile.inc b/src/soc/qualcomm/sc7180/Makefile.inc index 6b492d5784..e1d0492085 100644 --- a/src/soc/qualcomm/sc7180/Makefile.inc +++ b/src/soc/qualcomm/sc7180/Makefile.inc @@ -9,6 +9,7 @@ bootblock-y += spi.c bootblock-y += gpio.c bootblock-$(CONFIG_DRIVERS_UART) += uart_bitbang.c bootblock-y += clock.c +bootblock-$(CONFIG_SC7180_QSPI) += qspi.c ################################################################################ verstage-y += timer.c @@ -16,6 +17,7 @@ verstage-y += spi.c verstage-y += gpio.c verstage-$(CONFIG_DRIVERS_UART) += uart_bitbang.c verstage-y += clock.c +verstage-$(CONFIG_SC7180_QSPI) += qspi.c ################################################################################ romstage-y += cbmem.c @@ -28,6 +30,7 @@ romstage-y += spi.c romstage-y += gpio.c romstage-$(CONFIG_DRIVERS_UART) += uart_bitbang.c romstage-y += clock.c +romstage-$(CONFIG_SC7180_QSPI) += qspi.c ################################################################################ ramstage-y += soc.c @@ -36,6 +39,7 @@ ramstage-y += spi.c ramstage-y += gpio.c ramstage-$(CONFIG_DRIVERS_UART) += uart_bitbang.c ramstage-y += clock.c +ramstage-$(CONFIG_SC7180_QSPI) += qspi.c ################################################################################ diff --git a/src/soc/qualcomm/sc7180/bootblock.c b/src/soc/qualcomm/sc7180/bootblock.c index bf80bff706..4f97d76c9b 100644 --- a/src/soc/qualcomm/sc7180/bootblock.c +++ b/src/soc/qualcomm/sc7180/bootblock.c @@ -16,9 +16,11 @@ #include #include #include +#include void bootblock_soc_init(void) { sc7180_mmu_init(); clock_init(); + quadspi_init(25 * MHz); } diff --git a/src/soc/qualcomm/sc7180/include/soc/qspi.h b/src/soc/qualcomm/sc7180/include/soc/qspi.h new file mode 100644 index 0000000000..c3d1f78196 --- /dev/null +++ b/src/soc/qualcomm/sc7180/include/soc/qspi.h @@ -0,0 +1,121 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2019 Qualcomm Technologies. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ +#include +#include +#include + +#ifndef __SOC_QUALCOMM_SC7180_QSPI_H__ +#define __SOC_QUALCOMM_SC7180_QSPI_H__ + +struct sc7180_qspi_regs { + u32 mstr_cfg; + u32 ahb_mstr_cfg; + u32 reserve_0; + u32 mstr_int_en; + u32 mstr_int_sts; + u32 pio_xfer_ctrl; + u32 pio_xfer_cfg; + u32 pio_xfer_sts; + u32 pio_dataout_1byte; + u32 pio_dataout_4byte; + u32 rd_fifo_cfg; + u32 rd_fifo_sts; + u32 rd_fifo_rst; + u32 reserve_1[3]; + u32 next_dma_desc_addr; + u32 current_dma_desc_addr; + u32 current_mem_addr; + u32 hw_version; + u32 rd_fifo[16]; +}; + +check_member(sc7180_qspi_regs, rd_fifo, 0x50); +static struct sc7180_qspi_regs * const sc7180_qspi = (void *) QSPI_BASE; + +// MSTR_CONFIG register + +#define TX_DATA_OE_DELAY_SHIFT 24 +#define TX_DATA_OE_DELAY_MASK (0x3 << TX_DATA_OE_DELAY_SHIFT) +#define TX_CS_N_DELAY_SHIFT 22 +#define TX_CS_N_DELAY_MASK (0x3 << TX_CS_N_DELAY_SHIFT) +#define TX_CLK_DELAY_SHIFT 20 +#define TX_CLK_DELAY_MASK (0x3 << TX_CLK_DELAY_SHIFT) +#define TX_DATA_DELAY_SHIFT 18 +#define TX_DATA_DELAY_MASK (0x3 << TX_DATA_DELAY_SHIFT) +#define LPA_BASE_SHIFT 14 +#define LPA_BASE_MASK (0xF << LPA_BASE_SHIFT) +#define SBL_EN BIT(13) +#define CHIP_SELECT_NUM BIT(12) +#define SPI_MODE_SHIFT 10 +#define SPI_MODE_MASK (0x3 << SPI_MODE_SHIFT) +#define BIG_ENDIAN_MODE BIT(9) +#define DMA_ENABLE BIT(8) +#define PIN_WPN BIT(7) +#define PIN_HOLDN BIT(6) +#define FB_CLK_EN BIT(4) +#define FULL_CYCLE_MODE BIT(3) + +// MSTR_INT_ENABLE and MSTR_INT_STATUS register + +#define DMA_CHAIN_DONE BIT(31) +#define TRANSACTION_DONE BIT(16) +#define WRITE_FIFO_OVERRUN BIT(11) +#define WRITE_FIFO_FULL BIT(10) +#define HRESP_FROM_NOC_ERR BIT(3) +#define RESP_FIFO_RDY BIT(2) +#define RESP_FIFO_NOT_EMPTY BIT(1) +#define RESP_FIFO_UNDERRUN BIT(0) + +// PIO_TRANSFER_CONFIG register + +#define TRANSFER_FRAGMENT BIT(8) +#define MULTI_IO_MODE_SHIFT 1 +#define MULTI_IO_MODE_MASK (0x7 << MULTI_IO_MODE_SHIFT) +#define TRANSFER_DIRECTION BIT(0) + +// PIO_TRANSFER_STATUS register + +#define WR_FIFO_BYTES_SHIFT 16 +#define WR_FIFO_BYTES_MASK (0xFFFF << WR_FIFO_BYTES_SHIFT) + +// RD_FIFO_CONFIG register + +#define CONTINUOUS_MODE BIT(0) + +// RD_FIFO_STATUS register + +#define FIFO_EMPTY BIT(11) +#define WR_CNTS_SHIFT 4 +#define WR_CNTS_MASK (0x7F << WR_CNTS_SHIFT) +#define RDY_64BYTE BIT(3) +#define RDY_32BYTE BIT(2) +#define RDY_16BYTE BIT(1) +#define FIFO_RDY BIT(0) + +// RD_FIFO_RESET register + +#define RESET_FIFO BIT(0) + +#define QSPI_MAX_PACKET_COUNT 0xFFC0 + +void quadspi_init(uint32_t hz); +int sc7180_claim_bus(const struct spi_slave *slave); +int sc7180_setup_bus(const struct spi_slave *slave); +void sc7180_release_bus(const struct spi_slave *slave); +int sc7180_xfer(const struct spi_slave *slave, const void *dout, + size_t out_bytes, void *din, size_t in_bytes); +int sc7180_xfer_dual(const struct spi_slave *slave, const void *dout, + size_t out_bytes, void *din, size_t in_bytes); +#endif /* __SOC_QUALCOMM_SC7180_QSPI_H__ */ diff --git a/src/soc/qualcomm/sc7180/qspi.c b/src/soc/qualcomm/sc7180/qspi.c new file mode 100644 index 0000000000..30dc1c3387 --- /dev/null +++ b/src/soc/qualcomm/sc7180/qspi.c @@ -0,0 +1,306 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define CACHE_LINE_SIZE 64 + +static int curr_desc_idx = -1; + +struct cmd_desc { + uint32_t data_address; + uint32_t next_descriptor; + uint32_t direction:1; + uint32_t multi_io_mode:3; + uint32_t reserved1:4; + uint32_t fragment:1; + uint32_t reserved2:7; + uint32_t length:16; + //------------------------// + uint32_t bounce_src; + uint32_t bounce_dst; + uint32_t bounce_length; + uint64_t padding[5]; +}; + +enum qspi_mode { + SDR_1BIT = 1, + SDR_2BIT = 2, + SDR_4BIT = 3, + DDR_1BIT = 5, + DDR_2BIT = 6, + DDR_4BIT = 7, +}; + +enum cs_state { + CS_DEASSERT, + CS_ASSERT +}; + +struct xfer_cfg { + enum qspi_mode mode; +}; + +enum bus_xfer_direction { + MASTER_READ = 0, + MASTER_WRITE = 1, +}; + +struct { + struct cmd_desc descriptors[3]; + uint8_t buffers[3][CACHE_LINE_SIZE]; +} *dma = (void *)_dma_coherent; + +static void dma_transfer_chain(struct cmd_desc *chain) +{ + uint32_t mstr_int_status; + + write32(&sc7180_qspi->mstr_int_sts, 0xFFFFFFFF); + write32(&sc7180_qspi->next_dma_desc_addr, (uint32_t)(uintptr_t) chain); + + while (1) { + mstr_int_status = read32(&sc7180_qspi->mstr_int_sts); + if (mstr_int_status & DMA_CHAIN_DONE) + break; + } +} + +static void flush_chain(void) +{ + struct cmd_desc *desc = &dma->descriptors[0]; + uint8_t *src; + uint8_t *dst; + + dma_transfer_chain(desc); + + while (desc) { + if (desc->direction == MASTER_READ) { + if (desc->bounce_length == 0) + dcache_invalidate_by_mva( + (void *)(uintptr_t) desc->data_address, + desc->length); + else { + src = (void *)(uintptr_t) desc->bounce_src; + dst = (void *)(uintptr_t) desc->bounce_dst; + memcpy(dst, src, desc->bounce_length); + } + } + desc = (void *)(uintptr_t) desc->next_descriptor; + } + curr_desc_idx = -1; +} + +static struct cmd_desc *allocate_descriptor(void) +{ + struct cmd_desc *current; + struct cmd_desc *next; + uint8_t index; + + current = (curr_desc_idx == -1) ? + NULL : &dma->descriptors[curr_desc_idx]; + + index = ++curr_desc_idx; + next = &dma->descriptors[index]; + + next->data_address = (uint32_t) (uintptr_t) dma->buffers[index]; + + next->next_descriptor = 0; + next->direction = MASTER_READ; + next->multi_io_mode = 0; + next->reserved1 = 0; + next->fragment = 0; + next->reserved2 = 0; + next->length = 0; + next->bounce_src = 0; + next->bounce_dst = 0; + next->bounce_length = 0; + + if (current) { + current->next_descriptor = (uint32_t)(uintptr_t) next; + current->fragment = 1; + } + + return next; +} + +static void cs_change(enum cs_state state) +{ + gpio_set(GPIO(68), state == CS_DEASSERT); +} + +static void configure_gpios(void) +{ + gpio_output(GPIO(68), 1); + + gpio_configure(GPIO(64), GPIO64_FUNC_QSPI_DATA_0, + GPIO_NO_PULL, GPIO_2MA, GPIO_OUTPUT_ENABLE); + + gpio_configure(GPIO(65), GPIO65_FUNC_QSPI_DATA_1, + GPIO_NO_PULL, GPIO_2MA, GPIO_OUTPUT_ENABLE); + + gpio_configure(GPIO(63), GPIO63_FUNC_QSPI_CLK, + GPIO_NO_PULL, GPIO_2MA, GPIO_OUTPUT_ENABLE); +} + +static void queue_bounce_data(uint8_t *data, uint32_t data_bytes, + enum qspi_mode data_mode, bool write) +{ + struct cmd_desc *desc; + uint8_t *ptr; + + desc = allocate_descriptor(); + desc->direction = write; + desc->multi_io_mode = data_mode; + ptr = (void *)(uintptr_t) desc->data_address; + + if (write) { + memcpy(ptr, data, data_bytes); + } else { + desc->bounce_src = (uint32_t)(uintptr_t) ptr; + desc->bounce_dst = (uint32_t)(uintptr_t) data; + desc->bounce_length = data_bytes; + } + + desc->length = data_bytes; +} + +static void queue_direct_data(uint8_t *data, uint32_t data_bytes, + enum qspi_mode data_mode, bool write) +{ + struct cmd_desc *desc; + + desc = allocate_descriptor(); + desc->direction = write; + desc->multi_io_mode = data_mode; + desc->data_address = (uint32_t)(uintptr_t) data; + desc->length = data_bytes; + + if (write) + dcache_clean_by_mva(data, data_bytes); + else + dcache_invalidate_by_mva(data, data_bytes); +} + +static void queue_data(uint8_t *data, uint32_t data_bytes, + enum qspi_mode data_mode, bool write) +{ + uint8_t *aligned_ptr; + uint8_t *epilog_ptr; + uint32_t prolog_bytes, aligned_bytes, epilog_bytes; + + if (data_bytes == 0) + return; + + aligned_ptr = + (uint8_t *)ALIGN_UP((uintptr_t)data, CACHE_LINE_SIZE); + + prolog_bytes = MIN(data_bytes, aligned_ptr - data); + aligned_bytes = ALIGN_DOWN(data_bytes - prolog_bytes, CACHE_LINE_SIZE); + epilog_bytes = data_bytes - prolog_bytes - aligned_bytes; + + epilog_ptr = data + prolog_bytes + aligned_bytes; + + if (prolog_bytes) + queue_bounce_data(data, prolog_bytes, data_mode, write); + if (aligned_bytes) + queue_direct_data(aligned_ptr, aligned_bytes, data_mode, write); + if (epilog_bytes) + queue_bounce_data(epilog_ptr, epilog_bytes, data_mode, write); +} + +static void reg_init(void) +{ + uint32_t spi_mode; + uint32_t tx_data_oe_delay, tx_data_delay; + uint32_t mstr_config; + + spi_mode = 0; + + tx_data_oe_delay = 0; + tx_data_delay = 0; + + mstr_config = (tx_data_oe_delay << TX_DATA_OE_DELAY_SHIFT) | + (tx_data_delay << TX_DATA_DELAY_SHIFT) | (SBL_EN) | + (spi_mode << SPI_MODE_SHIFT) | + (PIN_HOLDN) | + (FB_CLK_EN) | + (DMA_ENABLE) | + (FULL_CYCLE_MODE); + + write32(&sc7180_qspi->mstr_cfg, mstr_config); + write32(&sc7180_qspi->ahb_mstr_cfg, 0xA42); + write32(&sc7180_qspi->mstr_int_en, 0x0); + write32(&sc7180_qspi->mstr_int_sts, 0xFFFFFFFF); + write32(&sc7180_qspi->rd_fifo_cfg, 0x0); + write32(&sc7180_qspi->rd_fifo_rst, RESET_FIFO); +} + +void quadspi_init(uint32_t hz) +{ + assert(dcache_line_bytes() == CACHE_LINE_SIZE); + clock_configure_qspi(hz * 4); + configure_gpios(); + reg_init(); +} + +int sc7180_claim_bus(const struct spi_slave *slave) +{ + cs_change(CS_ASSERT); + return 0; +} + +void sc7180_release_bus(const struct spi_slave *slave) +{ + cs_change(CS_DEASSERT); +} + +static int xfer(enum qspi_mode mode, const void *dout, size_t out_bytes, + void *din, size_t in_bytes) +{ + if ((out_bytes && !dout) || (in_bytes && !din) || + (in_bytes && out_bytes)) { + return -1; + } + + queue_data((uint8_t *) (out_bytes ? dout : din), + in_bytes | out_bytes, mode, !!out_bytes); + + flush_chain(); + + return 0; +} + +int sc7180_xfer(const struct spi_slave *slave, const void *dout, + size_t out_bytes, void *din, size_t in_bytes) +{ + return xfer(SDR_1BIT, dout, out_bytes, din, in_bytes); +} + +int sc7180_xfer_dual(const struct spi_slave *slave, const void *dout, + size_t out_bytes, void *din, size_t in_bytes) +{ + return xfer(SDR_2BIT, dout, out_bytes, din, in_bytes); +} diff --git a/src/soc/qualcomm/sc7180/spi.c b/src/soc/qualcomm/sc7180/spi.c index 5abb81ac0a..c6d4cb15cb 100644 --- a/src/soc/qualcomm/sc7180/spi.c +++ b/src/soc/qualcomm/sc7180/spi.c @@ -1,7 +1,7 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2018, The Linux Foundation. All rights reserved. + * Copyright (C) 2019, The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and @@ -15,12 +15,19 @@ #include #include +#include -static const struct spi_ctrlr spi_ctrlr; +static const struct spi_ctrlr qspi_ctrlr = { + .claim_bus = sc7180_claim_bus, + .release_bus = sc7180_release_bus, + .xfer = sc7180_xfer, + .xfer_dual = sc7180_xfer_dual, + .max_xfer_size = QSPI_MAX_PACKET_COUNT, +}; const struct spi_ctrlr_buses spi_ctrlr_bus_map[] = { { - .ctrlr = &spi_ctrlr, + .ctrlr = &qspi_ctrlr, .bus_start = CONFIG_BOOT_DEVICE_SPI_FLASH_BUS, .bus_end = CONFIG_BOOT_DEVICE_SPI_FLASH_BUS, }, From 6bbf8f238f27f35a77ba653a627d88a51e17660c Mon Sep 17 00:00:00 2001 From: Ravi Kumar Bokka Date: Mon, 12 Aug 2019 14:54:21 +0530 Subject: [PATCH 0548/1242] sc7180: Add AOP firmware support Developer/Reviewer, be aware of this patch from Napali: https://review.coreboot.org/c/coreboot/+/25210/85 Change-Id: I1cd552fbf03b5135e5911f1143f8778cad81e360 Signed-off-by: Ashwin Kumar Reviewed-on: https://review.coreboot.org/c/coreboot/+/35502 Tested-by: build bot (Jenkins) Reviewed-by: Julius Werner --- src/soc/qualcomm/sc7180/Makefile.inc | 1 + src/soc/qualcomm/sc7180/aop_load_reset.c | 43 +++++++++++++++++++ src/soc/qualcomm/sc7180/include/soc/aop.h | 21 +++++++++ .../qualcomm/sc7180/include/soc/memlayout.ld | 9 ++++ src/soc/qualcomm/sc7180/include/soc/symbols.h | 1 + src/soc/qualcomm/sc7180/mmu.c | 5 +++ src/soc/qualcomm/sc7180/soc.c | 7 ++- 7 files changed, 85 insertions(+), 2 deletions(-) create mode 100644 src/soc/qualcomm/sc7180/aop_load_reset.c create mode 100644 src/soc/qualcomm/sc7180/include/soc/aop.h diff --git a/src/soc/qualcomm/sc7180/Makefile.inc b/src/soc/qualcomm/sc7180/Makefile.inc index e1d0492085..8a76a03c9c 100644 --- a/src/soc/qualcomm/sc7180/Makefile.inc +++ b/src/soc/qualcomm/sc7180/Makefile.inc @@ -40,6 +40,7 @@ ramstage-y += gpio.c ramstage-$(CONFIG_DRIVERS_UART) += uart_bitbang.c ramstage-y += clock.c ramstage-$(CONFIG_SC7180_QSPI) += qspi.c +ramstage-y += aop_load_reset.c ################################################################################ diff --git a/src/soc/qualcomm/sc7180/aop_load_reset.c b/src/soc/qualcomm/sc7180/aop_load_reset.c new file mode 100644 index 0000000000..8d22d62056 --- /dev/null +++ b/src/soc/qualcomm/sc7180/aop_load_reset.c @@ -0,0 +1,43 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +void aop_fw_load_reset(void) +{ + bool aop_fw_entry; + + struct prog aop_fw_prog = + PROG_INIT(PROG_PAYLOAD, CONFIG_CBFS_PREFIX "/aop"); + + if (prog_locate(&aop_fw_prog)) + die("SOC image: AOP_FW not found"); + + aop_fw_entry = selfload(&aop_fw_prog); + if (!aop_fw_entry) + die("SOC image: AOP load failed"); + + clock_reset_aop(); + + printk(BIOS_DEBUG, "\nSOC:AOP brought out of reset.\n"); +} diff --git a/src/soc/qualcomm/sc7180/include/soc/aop.h b/src/soc/qualcomm/sc7180/include/soc/aop.h new file mode 100644 index 0000000000..5573163a5b --- /dev/null +++ b/src/soc/qualcomm/sc7180/include/soc/aop.h @@ -0,0 +1,21 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _SOC_QUALCOMM_SC7180_AOP_H__ +#define _SOC_QUALCOMM_SC7180_AOP_H__ + +void aop_fw_load_reset(void); + +#endif // _SOC_QUALCOMM_SC7180_AOP_H__ diff --git a/src/soc/qualcomm/sc7180/include/soc/memlayout.ld b/src/soc/qualcomm/sc7180/include/soc/memlayout.ld index 3f43419d14..732311953e 100644 --- a/src/soc/qualcomm/sc7180/include/soc/memlayout.ld +++ b/src/soc/qualcomm/sc7180/include/soc/memlayout.ld @@ -24,8 +24,16 @@ #define BSRAM_START(addr) SYMBOL(bsram, addr) #define BSRAM_END(addr) SYMBOL(ebsram, addr) +/* AOP : 0x0B000000 - 0x0B100000 */ +#define AOPSRAM_START(addr) SYMBOL(aopsram, addr) +#define AOPSRAM_END(addr) SYMBOL(eaopsram, addr) + SECTIONS { + AOPSRAM_START(0x0B000000) + REGION(aop, 0x0B000000, 0x100000, 4096) + AOPSRAM_END(0x0B100000) + SSRAM_START(0x14680000) OVERLAP_VERSTAGE_ROMSTAGE(0x14680000, 100K) REGION(qcsdi, 0x14699000, 52K, 4K) @@ -52,6 +60,7 @@ SECTIONS DRAM_START(0x80000000) /* Various hardware/software subsystems make use of this area */ + REGION(dram_aop, 0x80800000, 0x040000, 0x1000) REGION(dram_soc, 0x80900000, 0x300000, 0x1000) BL31(0x80C00000, 0x1A800000) POSTRAM_CBFS_CACHE(0x9F800000, 16M) diff --git a/src/soc/qualcomm/sc7180/include/soc/symbols.h b/src/soc/qualcomm/sc7180/include/soc/symbols.h index f379bb98e3..d2a53fbf92 100644 --- a/src/soc/qualcomm/sc7180/include/soc/symbols.h +++ b/src/soc/qualcomm/sc7180/include/soc/symbols.h @@ -25,5 +25,6 @@ DECLARE_REGION(dram_soc) DECLARE_REGION(dcb) DECLARE_REGION(pmic) DECLARE_REGION(limits_cfg) +DECLARE_REGION(aop) #endif /* _SOC_QUALCOMM_SC7180_SYMBOLS_H_ */ diff --git a/src/soc/qualcomm/sc7180/mmu.c b/src/soc/qualcomm/sc7180/mmu.c index 231b06f819..2eb8c86994 100644 --- a/src/soc/qualcomm/sc7180/mmu.c +++ b/src/soc/qualcomm/sc7180/mmu.c @@ -32,3 +32,8 @@ void sc7180_mmu_init(void) mmu_enable(); } + +void soc_mmu_dram_config_post_dram_init(void) +{ + mmu_config_range((void *)_aop, REGION_SIZE(aop), CACHED_RAM); +} diff --git a/src/soc/qualcomm/sc7180/soc.c b/src/soc/qualcomm/sc7180/soc.c index 7003b39a75..fbcfc6ed8d 100644 --- a/src/soc/qualcomm/sc7180/soc.c +++ b/src/soc/qualcomm/sc7180/soc.c @@ -18,18 +18,21 @@ #include #include #include +#include static void soc_read_resources(struct device *dev) { ram_resource(dev, 0, (uintptr_t)ddr_region->offset / KiB, ddr_region->size / KiB); - reserved_ram_resource(dev, 1, (uintptr_t)_dram_soc / KiB, + reserved_ram_resource(dev, 1, (uintptr_t)_dram_aop / KiB, + REGION_SIZE(dram_aop) / KiB); + reserved_ram_resource(dev, 2, (uintptr_t)_dram_soc / KiB, REGION_SIZE(dram_soc) / KiB); } static void soc_init(struct device *dev) { - + aop_fw_load_reset(); } static struct device_operations soc_ops = { From 050be72e77fb5beaf0882c9abaf1ce9a571231dc Mon Sep 17 00:00:00 2001 From: T Michael Turney Date: Tue, 22 Oct 2019 06:25:09 -0700 Subject: [PATCH 0549/1242] sc7180: Add USB support This includes USB QUSB2,QMP Phy and Controller support And libpayload support for USB Change-Id: I0651fc28dc227efbeb23eeefe9b96a3b940ae995 Signed-off-by: Sandeep Maheswaram Reviewed-on: https://review.coreboot.org/c/coreboot/+/35503 Tested-by: build bot (Jenkins) Reviewed-by: Julius Werner --- src/soc/qualcomm/sc7180/Makefile.inc | 2 + .../qualcomm/sc7180/include/soc/addressmap.h | 12 + src/soc/qualcomm/sc7180/include/soc/efuse.h | 28 + src/soc/qualcomm/sc7180/include/soc/usb.h | 96 +++ src/soc/qualcomm/sc7180/usb.c | 748 ++++++++++++++++++ 5 files changed, 886 insertions(+) create mode 100644 src/soc/qualcomm/sc7180/include/soc/efuse.h create mode 100644 src/soc/qualcomm/sc7180/include/soc/usb.h create mode 100644 src/soc/qualcomm/sc7180/usb.c diff --git a/src/soc/qualcomm/sc7180/Makefile.inc b/src/soc/qualcomm/sc7180/Makefile.inc index 8a76a03c9c..5f4dc1d756 100644 --- a/src/soc/qualcomm/sc7180/Makefile.inc +++ b/src/soc/qualcomm/sc7180/Makefile.inc @@ -26,6 +26,7 @@ romstage-y += ../common/qclib.c romstage-y += qclib.c romstage-y += ../common/mmu.c romstage-y += mmu.c +romstage-y += usb.c romstage-y += spi.c romstage-y += gpio.c romstage-$(CONFIG_DRIVERS_UART) += uart_bitbang.c @@ -41,6 +42,7 @@ ramstage-$(CONFIG_DRIVERS_UART) += uart_bitbang.c ramstage-y += clock.c ramstage-$(CONFIG_SC7180_QSPI) += qspi.c ramstage-y += aop_load_reset.c +ramstage-y += usb.c ################################################################################ diff --git a/src/soc/qualcomm/sc7180/include/soc/addressmap.h b/src/soc/qualcomm/sc7180/include/soc/addressmap.h index e3941899f6..60570f0dc0 100644 --- a/src/soc/qualcomm/sc7180/include/soc/addressmap.h +++ b/src/soc/qualcomm/sc7180/include/soc/addressmap.h @@ -25,4 +25,16 @@ #define TLMM_SOUTH_TILE_BASE 0x03D00000 #define TLMM_WEST_TILE_BASE 0x03500000 +/* + * USB BASE ADDRESSES + */ +#define QFPROM_BASE 0x00780000 +#define QUSB_PRIM_PHY_BASE 0x088e3000 +#define QUSB_PRIM_PHY_DIG_BASE 0x088e3200 +#define QMP_PHY_QSERDES_COM_REG_BASE 0x088e9000 +#define QMP_PHY_QSERDES_TX_REG_BASE 0x088e9200 +#define QMP_PHY_QSERDES_RX_REG_BASE 0x088e9400 +#define QMP_PHY_PCS_REG_BASE 0x088e9c00 +#define USB_HOST_DWC3_BASE 0x0a60c100 + #endif /* __SOC_QUALCOMM_SC7180_ADDRESS_MAP_H__ */ diff --git a/src/soc/qualcomm/sc7180/include/soc/efuse.h b/src/soc/qualcomm/sc7180/include/soc/efuse.h new file mode 100644 index 0000000000..baaa97179b --- /dev/null +++ b/src/soc/qualcomm/sc7180/include/soc/efuse.h @@ -0,0 +1,28 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (c) 2019 Qualcomm Technologies + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __SOC_QUALCOMM_SC7180_EFUSE_ADDRESS_MAP_H__ +#define __SOC_QUALCOMM_SC7180_EFUSE_ADDRESS_MAP_H__ + +/** + * USB EFUSE registers + */ +struct qfprom_corr { + u8 rsvd[0x4258 - 0x0]; + u32 qusb_hstx_trim_lsb; +}; +check_member(qfprom_corr, qusb_hstx_trim_lsb, 0x4258); + +#endif /* __SOC_QUALCOMM_SC7180_EFUSE_ADDRESS_MAP_H__ */ diff --git a/src/soc/qualcomm/sc7180/include/soc/usb.h b/src/soc/qualcomm/sc7180/include/soc/usb.h new file mode 100644 index 0000000000..3a8816a027 --- /dev/null +++ b/src/soc/qualcomm/sc7180/include/soc/usb.h @@ -0,0 +1,96 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (c) 2019 Qualcomm Technologies + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ +#include + +#ifndef _SC7180_USB_H_ +#define _SC7180_USB_H_ + +/* QSCRATCH_GENERAL_CFG register bit offset */ +#define PIPE_UTMI_CLK_SEL BIT(0) +#define PIPE3_PHYSTATUS_SW BIT(3) +#define PIPE_UTMI_CLK_DIS BIT(8) + +/* Global USB3 Control Registers */ +#define DWC3_GUSB3PIPECTL_DELAYP1TRANS BIT(18) +#define DWC3_GUSB3PIPECTL_UX_EXIT_IN_PX BIT(27) +#define DWC3_GCTL_PRTCAPDIR(n) ((n) << 12) +#define DWC3_GCTL_PRTCAP_OTG 3 +#define DWC3_GCTL_PRTCAP_HOST 1 + +/* Global USB2 PHY Configuration Register */ +#define DWC3_GUSB2PHYCFG_USBTRDTIM(n) ((n) << 10) +#define DWC3_GUSB2PHYCFG_USB2TRDTIM_MASK DWC3_GUSB2PHYCFG_USBTRDTIM(0xf) +#define DWC3_GUSB2PHYCFG_PHYIF(n) ((n) << 3) +#define DWC3_GUSB2PHYCFG_PHYIF_MASK DWC3_GUSB2PHYCFG_PHYIF(1) +#define USBTRDTIM_UTMI_8_BIT 9 +#define UTMI_PHYIF_8_BIT 0 + +#define DWC3_GCTL_SCALEDOWN(n) ((n) << 4) +#define DWC3_GCTL_SCALEDOWN_MASK DWC3_GCTL_SCALEDOWN(3) +#define DWC3_GCTL_DISSCRAMBLE (1 << 3) +#define DWC3_GCTL_U2EXIT_LFPS (1 << 2) +#define DWC3_GCTL_DSBLCLKGTNG (1 << 0) + +#define PORT_TUNE1_MASK 0xf0 + +/* QUSB2PHY_PWR_CTRL1 register related bits */ +#define POWER_DOWN BIT(0) + +/* DEBUG_CTRL2 register value to program VSTATUS MUX for PHY status */ +#define DEBUG_CTRL2_MUX_PLL_LOCK_STATUS 0x4 + +/* STAT5 register bits */ +#define VSTATUS_PLL_LOCK_STATUS_MASK BIT(0) + +/* QUSB PHY register values */ +#define QUSB2PHY_PLL_ANALOG_CONTROLS_TWO 0x03 +#define QUSB2PHY_PLL_CLOCK_INVERTERS 0x7c +#define QUSB2PHY_PLL_CMODE 0x80 +#define QUSB2PHY_PLL_LOCK_DELAY 0x0a +#define QUSB2PHY_PLL_DIGITAL_TIMERS_TWO 0x19 +#define QUSB2PHY_PLL_BIAS_CONTROL_1 0x40 +#define QUSB2PHY_PLL_BIAS_CONTROL_2 0x22 +#define QUSB2PHY_PWR_CTRL2 0x21 +#define QUSB2PHY_IMP_CTRL1 0x08 +#define QUSB2PHY_IMP_CTRL2 0x58 +#define QUSB2PHY_PORT_TUNE1 0xc5 +#define QUSB2PHY_PORT_TUNE2 0x29 +#define QUSB2PHY_PORT_TUNE3 0xca +#define QUSB2PHY_PORT_TUNE4 0x04 +#define QUSB2PHY_PORT_TUNE5 0x03 +#define QUSB2PHY_CHG_CTRL2 0x30 + +/* USB3PHY_PCIE_USB3_PCS_PCS_STATUS bit */ +#define USB3_PCS_PHYSTATUS BIT(6) + +struct usb_board_data { + /* Register values going to override from the boardfile */ + u32 pll_bias_control_2; + u32 imp_ctrl1; + u32 port_tune1; +}; + +struct qmp_phy_init_tbl { + u32 *address; + u32 val; +}; + +void setup_usb_host0(struct usb_board_data *data); + +/* Call reset_ before setup_ */ +void reset_usb0(void); + + +#endif /* _SC7180_USB_H_ */ diff --git a/src/soc/qualcomm/sc7180/usb.c b/src/soc/qualcomm/sc7180/usb.c new file mode 100644 index 0000000000..4183e9b97d --- /dev/null +++ b/src/soc/qualcomm/sc7180/usb.c @@ -0,0 +1,748 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (c) 2019 Qualcomm Technologies + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +struct usb_qusb_phy_dig { + u8 rsvd1[16]; + u32 pwr_ctrl1; + u32 pwr_ctrl2; + u8 rsvd2[8]; + u32 imp_ctrl1; + u32 imp_ctrl2; + u8 rsvd3[20]; + u32 chg_ctrl2; + u32 tune1; + u32 tune2; + u32 tune3; + u32 tune4; + u32 tune5; + u8 rsvd4[44]; + u32 debug_ctrl2; + u8 rsvd5[28]; + u32 debug_stat5; +}; +check_member(usb_qusb_phy_dig, tune5, 0x50); +check_member(usb_qusb_phy_dig, debug_ctrl2, 0x80); +check_member(usb_qusb_phy_dig, debug_stat5, 0xA0); + +struct usb_qusb_phy_pll { + u8 rsvd0[4]; + u32 analog_controls_two; + u8 rsvd1[36]; + u32 cmode; + u8 rsvd2[132]; + u32 dig_tim; + u8 rsvd3[204]; + u32 lock_delay; + u8 rsvd4[4]; + u32 clock_inverters; + u8 rsvd5[4]; + u32 bias_ctrl_1; + u32 bias_ctrl_2; +}; +check_member(usb_qusb_phy_pll, cmode, 0x2C); +check_member(usb_qusb_phy_pll, bias_ctrl_2, 0x198); +check_member(usb_qusb_phy_pll, dig_tim, 0xB4); + +/* Only for QMP V3 PHY - QSERDES COM registers */ +struct usb3_phy_qserdes_com_reg_layout { + u8 _reserved1[16]; + u32 com_ssc_en_center; + u32 com_ssc_adj_per1; + u32 com_ssc_adj_per2; + u32 com_ssc_per1; + u32 com_ssc_per2; + u32 com_ssc_step_size1; + u32 com_ssc_step_size2; + u8 _reserved2[8]; + u32 com_bias_en_clkbuflr_en; + u32 com_sys_clk_enable1; + u32 com_sys_clk_ctrl; + u32 com_sysclk_buf_enable; + u32 com_pll_en; + u32 com_pll_ivco; + u8 _reserved3[20]; + u32 com_cp_ctrl_mode0; + u8 _reserved4[4]; + u32 com_pll_rctrl_mode0; + u8 _reserved5[4]; + u32 com_pll_cctrl_mode0; + u8 _reserved6[12]; + u32 com_sysclk_en_sel; + u8 _reserved7[8]; + u32 com_resetsm_ctrl2; + u32 com_lock_cmp_en; + u32 com_lock_cmp_cfg; + u32 com_lock_cmp1_mode0; + u32 com_lock_cmp2_mode0; + u32 com_lock_cmp3_mode0; + u8 _reserved8[12]; + u32 com_dec_start_mode0; + u8 _reserved9[4]; + u32 com_div_frac_start1_mode0; + u32 com_div_frac_start2_mode0; + u32 com_div_frac_start3_mode0; + u8 _reserved10[20]; + u32 com_integloop_gain0_mode0; + u32 com_integloop_gain1_mode0; + u8 _reserved11[16]; + u32 com_vco_tune_map; + u32 com_vco_tune1_mode0; + u32 com_vco_tune2_mode0; + u8 _reserved12[60]; + u32 com_clk_select; + u32 com_hsclk_sel; + u8 _reserved13[8]; + u32 com_coreclk_div_mode0; + u8 _reserved14[8]; + u32 com_core_clk_en; + u32 com_c_ready_status; + u32 com_cmn_config; + u32 com_cmn_rate_override; + u32 com_svs_mode_clk_sel; +}; +check_member(usb3_phy_qserdes_com_reg_layout, com_ssc_en_center, 0x010); +check_member(usb3_phy_qserdes_com_reg_layout, com_ssc_adj_per1, 0x014); +check_member(usb3_phy_qserdes_com_reg_layout, com_ssc_adj_per2, 0x018); +check_member(usb3_phy_qserdes_com_reg_layout, com_ssc_per1, 0x01c); +check_member(usb3_phy_qserdes_com_reg_layout, com_ssc_per2, 0x020); +check_member(usb3_phy_qserdes_com_reg_layout, com_bias_en_clkbuflr_en, 0x034); +check_member(usb3_phy_qserdes_com_reg_layout, com_pll_ivco, 0x048); +check_member(usb3_phy_qserdes_com_reg_layout, com_cp_ctrl_mode0, 0x060); +check_member(usb3_phy_qserdes_com_reg_layout, com_sysclk_en_sel, 0x080); +check_member(usb3_phy_qserdes_com_reg_layout, com_resetsm_ctrl2, 0x08c); +check_member(usb3_phy_qserdes_com_reg_layout, com_dec_start_mode0, 0x0b0); +check_member(usb3_phy_qserdes_com_reg_layout, com_div_frac_start1_mode0, 0x0b8); +check_member(usb3_phy_qserdes_com_reg_layout, com_integloop_gain0_mode0, 0x0d8); +check_member(usb3_phy_qserdes_com_reg_layout, com_vco_tune_map, 0x0f0); +check_member(usb3_phy_qserdes_com_reg_layout, com_clk_select, 0x138); +check_member(usb3_phy_qserdes_com_reg_layout, com_coreclk_div_mode0, 0x148); +check_member(usb3_phy_qserdes_com_reg_layout, com_core_clk_en, 0x154); +check_member(usb3_phy_qserdes_com_reg_layout, com_svs_mode_clk_sel, 0x164); + +/* Only for QMP V3 PHY - TX registers */ +struct usb3_phy_qserdes_tx_reg_layout { + u8 _reserved1[68]; + u32 tx_res_code_lane_offset_tx; + u32 tx_res_code_lane_offset_rx; + u8 _reserved2[20]; + u32 tx_highz_drvr_en; + u8 _reserved3[40]; + u32 tx_lane_mode_1; + u8 _reserved4[20]; + u32 tx_rcv_detect_lvl_2; +}; +check_member(usb3_phy_qserdes_tx_reg_layout, tx_res_code_lane_offset_tx, 0x044); +check_member(usb3_phy_qserdes_tx_reg_layout, tx_res_code_lane_offset_rx, 0x048); +check_member(usb3_phy_qserdes_tx_reg_layout, tx_highz_drvr_en, 0x060); +check_member(usb3_phy_qserdes_tx_reg_layout, tx_lane_mode_1, 0x08c); +check_member(usb3_phy_qserdes_tx_reg_layout, tx_rcv_detect_lvl_2, 0x0a4); + +/* Only for QMP V3 PHY - RX registers */ +struct usb3_phy_qserdes_rx_reg_layout { + u8 _reserved1[8]; + u32 rx_ucdr_fo_gain; + u32 rx_ucdr_so_gain_half; + u8 _reserved2[32]; + u32 rx_ucdr_fastlock_fo_gain; + u32 rx_ucdr_so_saturtn_and_en; + u8 _reserved3[12]; + u32 rx_ucdr_pi_cntrls; + u8 _reserved4[120]; + u32 rx_vga_cal_ctrl2; + u8 _reserved5[16]; + u32 rx_rx_equ_adap_ctrl2; + u32 rx_rx_equ_adap_ctrl3; + u32 rx_rx_equ_adap_ctrl4; + u8 _reserved6[24]; + u32 rx_rx_eq_offset_adap_ctrl1; + u32 rx_rx_offset_adap_ctrl2; + u32 rx_sigdet_enables; + u32 rx_sigdet_ctrl; + u8 _reserved7[4]; + u32 rx_sigdet_deglitch_ctrl; + u32 rx_rx_band; + u8 _reserved8[80]; + u32 rx_rx_mode_00; +}; +check_member(usb3_phy_qserdes_rx_reg_layout, rx_ucdr_fo_gain, 0x008); +check_member(usb3_phy_qserdes_rx_reg_layout, rx_ucdr_so_gain_half, 0x00c); +check_member(usb3_phy_qserdes_rx_reg_layout, rx_ucdr_fastlock_fo_gain, 0x030); +check_member(usb3_phy_qserdes_rx_reg_layout, rx_ucdr_so_saturtn_and_en, 0x034); +check_member(usb3_phy_qserdes_rx_reg_layout, rx_ucdr_pi_cntrls, 0x044); +check_member(usb3_phy_qserdes_rx_reg_layout, rx_vga_cal_ctrl2, 0x0c0); +check_member(usb3_phy_qserdes_rx_reg_layout, rx_rx_equ_adap_ctrl2, 0x0d4); +check_member(usb3_phy_qserdes_rx_reg_layout, rx_rx_equ_adap_ctrl3, 0x0d8); +check_member(usb3_phy_qserdes_rx_reg_layout, rx_rx_equ_adap_ctrl4, 0x0dc); +check_member(usb3_phy_qserdes_rx_reg_layout, rx_rx_eq_offset_adap_ctrl1, 0x0f8); +check_member(usb3_phy_qserdes_rx_reg_layout, rx_rx_offset_adap_ctrl2, 0x0fc); +check_member(usb3_phy_qserdes_rx_reg_layout, rx_sigdet_enables, 0x100); +check_member(usb3_phy_qserdes_rx_reg_layout, rx_sigdet_ctrl, 0x104); +check_member(usb3_phy_qserdes_rx_reg_layout, rx_sigdet_deglitch_ctrl, 0x10c); +check_member(usb3_phy_qserdes_rx_reg_layout, rx_rx_band, 0x110); +check_member(usb3_phy_qserdes_rx_reg_layout, rx_rx_mode_00, 0x164); + +/* Only for QMP V3 PHY - PCS registers */ +struct usb3_phy_pcs_reg_layout { + u32 pcs_sw_reset; + u32 pcs_power_down_control; + u32 pcs_start_control; + u32 pcs_txmgn_v0; + u32 pcs_txmgn_v1; + u32 pcs_txmgn_v2; + u32 pcs_txmgn_v3; + u32 pcs_txmgn_v4; + u32 pcs_txmgn_ls; + u32 pcs_txdeemph_m6db_v0; + u32 pcs_txdeemph_m3p5db_v0; + u32 pcs_txdeemph_m6db_v1; + u32 pcs_txdeemph_m3p5db_v1; + u32 pcs_txdeemph_m6db_v2; + u32 pcs_txdeemph_m3p5db_v2; + u32 pcs_txdeemph_m6db_v3; + u32 pcs_txdeemph_m3p5db_v3; + u32 pcs_txdeemph_m6db_v4; + u32 pcs_txdeemph_m3p5db_v4; + u32 pcs_txdeemph_m6db_ls; + u32 pcs_txdeemph_m3p5db_ls; + u8 _reserved1[8]; + u32 pcs_rate_slew_cntrl; + u8 _reserved2[4]; + u32 pcs_power_state_config2; + u8 _reserved3[8]; + u32 pcs_rcvr_dtct_dly_p1u2_l; + u32 pcs_rcvr_dtct_dly_p1u2_h; + u32 pcs_rcvr_dtct_dly_u3_l; + u32 pcs_rcvr_dtct_dly_u3_h; + u32 pcs_lock_detect_config1; + u32 pcs_lock_detect_config2; + u32 pcs_lock_detect_config3; + u32 pcs_tsync_rsync_time; + u8 _reserved4[16]; + u32 pcs_pwrup_reset_dly_time_auxclk; + u8 _reserved5[12]; + u32 pcs_lfps_ecstart_eqtlock; + u8 _reserved6[4]; + u32 pcs_rxeqtraining_wait_time; + u32 pcs_rxeqtraining_run_time; + u8 _reserved7[4]; + u32 pcs_fll_ctrl1; + u32 pcs_fll_ctrl2; + u32 pcs_fll_cnt_val_l; + u32 pcs_fll_cnt_val_h_tol; + u32 pcs_fll_man_code; + u32 pcs_autonomous_mode_ctrl; + u8 _reserved8[152]; + u32 pcs_ready_status; + u8 _reserved9[96]; + u32 pcs_rx_sigdet_lvl; + u8 _reserved10[48]; + u32 pcs_refgen_req_config1; + u32 pcs_refgen_req_config2; +}; +check_member(usb3_phy_pcs_reg_layout, pcs_sw_reset, 0x000); +check_member(usb3_phy_pcs_reg_layout, pcs_txmgn_v0, 0x00c); +check_member(usb3_phy_pcs_reg_layout, pcs_txmgn_v1, 0x010); +check_member(usb3_phy_pcs_reg_layout, pcs_txmgn_v2, 0x014); +check_member(usb3_phy_pcs_reg_layout, pcs_txmgn_v3, 0x018); +check_member(usb3_phy_pcs_reg_layout, pcs_txmgn_v4, 0x01c); +check_member(usb3_phy_pcs_reg_layout, pcs_txmgn_ls, 0x020); +check_member(usb3_phy_pcs_reg_layout, pcs_txdeemph_m6db_v0, 0x024); +check_member(usb3_phy_pcs_reg_layout, pcs_txdeemph_m3p5db_v0, 0x028); +check_member(usb3_phy_pcs_reg_layout, pcs_txdeemph_m6db_v1, 0x02c); +check_member(usb3_phy_pcs_reg_layout, pcs_txdeemph_m3p5db_v1, 0x030); +check_member(usb3_phy_pcs_reg_layout, pcs_txdeemph_m6db_v2, 0x034); +check_member(usb3_phy_pcs_reg_layout, pcs_txdeemph_m3p5db_v2, 0x038); +check_member(usb3_phy_pcs_reg_layout, pcs_txdeemph_m6db_v3, 0x03c); +check_member(usb3_phy_pcs_reg_layout, pcs_txdeemph_m3p5db_v3, 0x040); +check_member(usb3_phy_pcs_reg_layout, pcs_txdeemph_m6db_v4, 0x044); +check_member(usb3_phy_pcs_reg_layout, pcs_txdeemph_m3p5db_v4, 0x048); +check_member(usb3_phy_pcs_reg_layout, pcs_txdeemph_m6db_ls, 0x04c); +check_member(usb3_phy_pcs_reg_layout, pcs_txdeemph_m3p5db_ls, 0x050); +check_member(usb3_phy_pcs_reg_layout, pcs_rate_slew_cntrl, 0x05c); +check_member(usb3_phy_pcs_reg_layout, pcs_power_state_config2, 0x064); +check_member(usb3_phy_pcs_reg_layout, pcs_rcvr_dtct_dly_p1u2_l, 0x070); +check_member(usb3_phy_pcs_reg_layout, pcs_rcvr_dtct_dly_p1u2_h, 0x074); +check_member(usb3_phy_pcs_reg_layout, pcs_rcvr_dtct_dly_u3_l, 0x078); +check_member(usb3_phy_pcs_reg_layout, pcs_rcvr_dtct_dly_u3_h, 0x07c); +check_member(usb3_phy_pcs_reg_layout, pcs_lock_detect_config1, 0x080); +check_member(usb3_phy_pcs_reg_layout, pcs_lock_detect_config2, 0x084); +check_member(usb3_phy_pcs_reg_layout, pcs_lock_detect_config3, 0x088); +check_member(usb3_phy_pcs_reg_layout, pcs_pwrup_reset_dly_time_auxclk, 0x0a0); +check_member(usb3_phy_pcs_reg_layout, pcs_rxeqtraining_wait_time, 0x0b8); +check_member(usb3_phy_pcs_reg_layout, pcs_fll_cnt_val_h_tol, 0x0d0); +check_member(usb3_phy_pcs_reg_layout, pcs_autonomous_mode_ctrl, 0x0d8); +check_member(usb3_phy_pcs_reg_layout, pcs_ready_status, 0x174); +check_member(usb3_phy_pcs_reg_layout, pcs_refgen_req_config2, 0x210); + +static struct usb3_phy_qserdes_com_reg_layout *const qserdes_com_reg_layout = + (void *)QMP_PHY_QSERDES_COM_REG_BASE; +static struct usb3_phy_qserdes_tx_reg_layout *const qserdes_tx_reg_layout = + (void *)QMP_PHY_QSERDES_TX_REG_BASE; +static struct usb3_phy_qserdes_rx_reg_layout *const qserdes_rx_reg_layout = + (void *)QMP_PHY_QSERDES_RX_REG_BASE; +static struct usb3_phy_pcs_reg_layout *const pcs_reg_layout = + (void *)QMP_PHY_PCS_REG_BASE; + + + +struct usb_dwc3 { + u32 sbuscfg0; + u32 sbuscfg1; + u32 txthrcfg; + u32 rxthrcfg; + u32 ctl; + u32 pmsts; + u32 sts; + u32 uctl1; + u32 snpsid; + u32 gpio; + u32 uid; + u32 uctl; + u64 buserraddr; + u64 prtbimap; + u8 reserved1[32]; + u32 dbgfifospace; + u32 dbgltssm; + u32 dbglnmcc; + u32 dbgbmu; + u32 dbglspmux; + u32 dbglsp; + u32 dbgepinfo0; + u32 dbgepinfo1; + u64 prtbimap_hs; + u64 prtbimap_fs; + u8 reserved2[112]; + u32 usb2phycfg; + u8 reserved3[124]; + u32 usb2phyacc; + u8 reserved4[60]; + u32 usb3pipectl; + u8 reserved5[60]; +}; +check_member(usb_dwc3, usb3pipectl, 0x1c0); + +static const struct qmp_phy_init_tbl qmp_v3_usb3_serdes_tbl[] = { + {&qserdes_com_reg_layout->com_pll_ivco, 0x07}, + {&qserdes_com_reg_layout->com_sysclk_en_sel, 0x14}, + {&qserdes_com_reg_layout->com_bias_en_clkbuflr_en, 0x08}, + {&qserdes_com_reg_layout->com_clk_select, 0x30}, + {&qserdes_com_reg_layout->com_sys_clk_ctrl, 0x02}, + {&qserdes_com_reg_layout->com_resetsm_ctrl2, 0x08}, + {&qserdes_com_reg_layout->com_cmn_config, 0x16}, + {&qserdes_com_reg_layout->com_svs_mode_clk_sel, 0x01}, + {&qserdes_com_reg_layout->com_hsclk_sel, 0x80}, + {&qserdes_com_reg_layout->com_dec_start_mode0, 0x82}, + {&qserdes_com_reg_layout->com_div_frac_start1_mode0, 0xab}, + {&qserdes_com_reg_layout->com_div_frac_start2_mode0, 0xea}, + {&qserdes_com_reg_layout->com_div_frac_start3_mode0, 0x02}, + {&qserdes_com_reg_layout->com_cp_ctrl_mode0, 0x06}, + {&qserdes_com_reg_layout->com_pll_rctrl_mode0, 0x16}, + {&qserdes_com_reg_layout->com_pll_cctrl_mode0, 0x36}, + {&qserdes_com_reg_layout->com_integloop_gain1_mode0, 0x00}, + {&qserdes_com_reg_layout->com_integloop_gain0_mode0, 0x3f}, + {&qserdes_com_reg_layout->com_vco_tune2_mode0, 0x01}, + {&qserdes_com_reg_layout->com_vco_tune1_mode0, 0xc9}, + {&qserdes_com_reg_layout->com_coreclk_div_mode0, 0x0a}, + {&qserdes_com_reg_layout->com_lock_cmp3_mode0, 0x00}, + {&qserdes_com_reg_layout->com_lock_cmp2_mode0, 0x34}, + {&qserdes_com_reg_layout->com_lock_cmp1_mode0, 0x15}, + {&qserdes_com_reg_layout->com_lock_cmp_en, 0x04}, + {&qserdes_com_reg_layout->com_core_clk_en, 0x00}, + {&qserdes_com_reg_layout->com_lock_cmp_cfg, 0x00}, + {&qserdes_com_reg_layout->com_vco_tune_map, 0x00}, + {&qserdes_com_reg_layout->com_sysclk_buf_enable, 0x0a}, + {&qserdes_com_reg_layout->com_ssc_en_center, 0x01}, + {&qserdes_com_reg_layout->com_ssc_per1, 0x31}, + {&qserdes_com_reg_layout->com_ssc_per2, 0x01}, + {&qserdes_com_reg_layout->com_ssc_adj_per1, 0x00}, + {&qserdes_com_reg_layout->com_ssc_adj_per2, 0x00}, + {&qserdes_com_reg_layout->com_ssc_step_size1, 0x85}, + {&qserdes_com_reg_layout->com_ssc_step_size2, 0x07}, +}; + +static const struct qmp_phy_init_tbl qmp_v3_usb3_tx_tbl[] = { + {&qserdes_tx_reg_layout->tx_highz_drvr_en, 0x10}, + {&qserdes_tx_reg_layout->tx_rcv_detect_lvl_2, 0x12}, + {&qserdes_tx_reg_layout->tx_lane_mode_1, 0x16}, + {&qserdes_tx_reg_layout->tx_res_code_lane_offset_rx, 0x09}, + {&qserdes_tx_reg_layout->tx_res_code_lane_offset_tx, 0x06}, +}; + +static const struct qmp_phy_init_tbl qmp_v3_usb3_rx_tbl[] = { + {&qserdes_rx_reg_layout->rx_ucdr_fastlock_fo_gain, 0x0b}, + {&qserdes_rx_reg_layout->rx_rx_equ_adap_ctrl2, 0x0f}, + {&qserdes_rx_reg_layout->rx_rx_equ_adap_ctrl3, 0x4e}, + {&qserdes_rx_reg_layout->rx_rx_equ_adap_ctrl4, 0x18}, + {&qserdes_rx_reg_layout->rx_rx_eq_offset_adap_ctrl1, 0x77}, + {&qserdes_rx_reg_layout->rx_rx_offset_adap_ctrl2, 0x80}, + {&qserdes_rx_reg_layout->rx_sigdet_ctrl, 0x03}, + {&qserdes_rx_reg_layout->rx_sigdet_deglitch_ctrl, 0x16}, + {&qserdes_rx_reg_layout->rx_ucdr_so_saturtn_and_en, 0x75}, + {&qserdes_rx_reg_layout->rx_ucdr_pi_cntrls, 0x80}, + {&qserdes_rx_reg_layout->rx_ucdr_fo_gain, 0x0a}, + {&qserdes_rx_reg_layout->rx_ucdr_so_gain_half, 0x06}, + {&qserdes_rx_reg_layout->rx_sigdet_enables, 0x00}, +}; + +static const struct qmp_phy_init_tbl qmp_v3_usb3_pcs_tbl[] = { + /* FLL settings */ + {&pcs_reg_layout->pcs_fll_ctrl2, 0x83}, + {&pcs_reg_layout->pcs_fll_cnt_val_l, 0x09}, + {&pcs_reg_layout->pcs_fll_cnt_val_h_tol, 0xa2}, + {&pcs_reg_layout->pcs_fll_man_code, 0x40}, + {&pcs_reg_layout->pcs_fll_ctrl1, 0x02}, + + /* Lock Det settings */ + {&pcs_reg_layout->pcs_lock_detect_config1, 0xd1}, + {&pcs_reg_layout->pcs_lock_detect_config2, 0x1f}, + {&pcs_reg_layout->pcs_lock_detect_config3, 0x47}, + {&pcs_reg_layout->pcs_power_state_config2, 0x1b}, + + {&pcs_reg_layout->pcs_rx_sigdet_lvl, 0xba}, + {&pcs_reg_layout->pcs_txmgn_v0, 0x9f}, + {&pcs_reg_layout->pcs_txmgn_v1, 0x9f}, + {&pcs_reg_layout->pcs_txmgn_v2, 0xb7}, + {&pcs_reg_layout->pcs_txmgn_v3, 0x4e}, + {&pcs_reg_layout->pcs_txmgn_v4, 0x65}, + {&pcs_reg_layout->pcs_txmgn_ls, 0x6b}, + {&pcs_reg_layout->pcs_txdeemph_m6db_v0, 0x15}, + {&pcs_reg_layout->pcs_txdeemph_m3p5db_v0, 0x0d}, + {&pcs_reg_layout->pcs_txdeemph_m6db_v1, 0x15}, + {&pcs_reg_layout->pcs_txdeemph_m3p5db_v1, 0x0d}, + {&pcs_reg_layout->pcs_txdeemph_m6db_v2, 0x15}, + {&pcs_reg_layout->pcs_txdeemph_m3p5db_v2, 0x0d}, + {&pcs_reg_layout->pcs_txdeemph_m6db_v3, 0x15}, + {&pcs_reg_layout->pcs_txdeemph_m3p5db_v3, 0x1d}, + {&pcs_reg_layout->pcs_txdeemph_m6db_v4, 0x15}, + {&pcs_reg_layout->pcs_txdeemph_m3p5db_v4, 0x0d}, + {&pcs_reg_layout->pcs_txdeemph_m6db_ls, 0x15}, + {&pcs_reg_layout->pcs_txdeemph_m3p5db_ls, 0x0d}, + {&pcs_reg_layout->pcs_rate_slew_cntrl, 0x02}, + {&pcs_reg_layout->pcs_pwrup_reset_dly_time_auxclk, 0x04}, + {&pcs_reg_layout->pcs_tsync_rsync_time, 0x44}, + {&pcs_reg_layout->pcs_rcvr_dtct_dly_p1u2_l, 0xe7}, + {&pcs_reg_layout->pcs_rcvr_dtct_dly_p1u2_h, 0x03}, + {&pcs_reg_layout->pcs_rcvr_dtct_dly_u3_l, 0x40}, + {&pcs_reg_layout->pcs_rcvr_dtct_dly_u3_h, 0x00}, + {&pcs_reg_layout->pcs_rxeqtraining_wait_time, 0x75}, + {&pcs_reg_layout->pcs_lfps_ecstart_eqtlock, 0x86}, + {&pcs_reg_layout->pcs_rxeqtraining_run_time, 0x13}, +}; + + + +struct usb_dwc3_cfg { + struct usb_dwc3 *usb_host_dwc3; + struct usb_qusb_phy_pll *qusb_phy_pll; + struct usb_qusb_phy_dig *qusb_phy_dig; + /* Init sequence for QMP PHY blocks - serdes, tx, rx, pcs */ + const struct qmp_phy_init_tbl *serdes_tbl; + int serdes_tbl_num; + const struct qmp_phy_init_tbl *tx_tbl; + int tx_tbl_num; + const struct qmp_phy_init_tbl *rx_tbl; + int rx_tbl_num; + const struct qmp_phy_init_tbl *pcs_tbl; + int pcs_tbl_num; + struct usb3_phy_pcs_reg_layout *qmp_pcs_reg; + + u32 *usb3_bcr; + u32 *qusb2phy_bcr; + u32 *gcc_usb3phy_bcr_reg; + u32 *gcc_qmpphy_bcr_reg; + struct usb_board_data *board_data; + u32 efuse_offset; +}; + +static struct usb_dwc3_cfg usb_port0 = { + .usb_host_dwc3 = (void *)USB_HOST_DWC3_BASE, + .qusb_phy_pll = (void *)QUSB_PRIM_PHY_BASE, + .qusb_phy_dig = (void *)QUSB_PRIM_PHY_DIG_BASE, + .serdes_tbl = qmp_v3_usb3_serdes_tbl, + .serdes_tbl_num = ARRAY_SIZE(qmp_v3_usb3_serdes_tbl), + .tx_tbl = qmp_v3_usb3_tx_tbl, + .tx_tbl_num = ARRAY_SIZE(qmp_v3_usb3_tx_tbl), + .rx_tbl = qmp_v3_usb3_rx_tbl, + .rx_tbl_num = ARRAY_SIZE(qmp_v3_usb3_rx_tbl), + .pcs_tbl = qmp_v3_usb3_pcs_tbl, + .pcs_tbl_num = ARRAY_SIZE(qmp_v3_usb3_pcs_tbl), + .qmp_pcs_reg = (void *)QMP_PHY_PCS_REG_BASE, + .usb3_bcr = &gcc->usb30_prim_bcr, + .qusb2phy_bcr = &gcc->qusb2phy_prim_bcr, + .gcc_usb3phy_bcr_reg = &gcc->usb3_dp_phy_prim_bcr, + .gcc_qmpphy_bcr_reg = &gcc->usb3_phy_prim_bcr, + .efuse_offset = 25, +}; + + +static struct qfprom_corr * const qfprom_corr_efuse = (void *)QFPROM_BASE; + +static void reset_usb(struct usb_dwc3_cfg *dwc3) +{ + /* Assert Core reset */ + clock_reset_bcr(dwc3->usb3_bcr, 1); + + /* Assert QUSB PHY reset */ + clock_reset_bcr(dwc3->qusb2phy_bcr, 1); + + /* Assert QMP PHY reset */ + clock_reset_bcr(dwc3->gcc_usb3phy_bcr_reg, 1); + clock_reset_bcr(dwc3->gcc_qmpphy_bcr_reg, 1); +} + +void reset_usb0(void) +{ + /* Before Resetting PHY, put Core in Reset */ + printk(BIOS_INFO, "Starting DWC3 and PHY resets for USB(0)\n"); + + reset_usb(&usb_port0); +} + + +/* + * Update board specific PHY tuning override values that specified from + * board file. + */ +static void qusb2_phy_override_phy_params(struct usb_dwc3_cfg *dwc3) +{ + /* Override preemphasis value */ + write32(&dwc3->qusb_phy_dig->tune1, + dwc3->board_data->port_tune1); + + /* Override BIAS_CTRL_2 to reduce the TX swing overshooting. */ + write32(&dwc3->qusb_phy_pll->bias_ctrl_2, + dwc3->board_data->pll_bias_control_2); + + /* Override IMP_RES_OFFSET value */ + write32(&dwc3->qusb_phy_dig->imp_ctrl1, + dwc3->board_data->imp_ctrl1); +} + +/* + * Fetches HS Tx tuning value from efuse register and sets the + * QUSB2PHY_PORT_TUNE1/2 register. + * For error case, skip setting the value and use the default value. + */ +static void qusb2_phy_set_tune_param(struct usb_dwc3_cfg *dwc3) +{ + /* + * Efuse registers 3 bit value specifies tuning for HSTX + * output current in TUNE1 Register. Hence Extract 3 bits from + * EFUSE at correct position. + */ + + const int efuse_bits = 3; + int bit_pos = dwc3->efuse_offset; + + u32 bit_mask = (1 << efuse_bits) - 1; + u32 tune_val = + (read32(&qfprom_corr_efuse->qusb_hstx_trim_lsb) >> bit_pos) + & bit_mask; + /* + * if efuse reg is updated (i.e non-zero) then use it to program + * tune parameters. + */ + if (tune_val) + clrsetbits_le32(&dwc3->qusb_phy_dig->tune1, + PORT_TUNE1_MASK, tune_val << 4); +} + +static void tune_phy(struct usb_dwc3_cfg *dwc3, struct usb_qusb_phy_dig *phy) +{ + write32(&phy->pwr_ctrl2, QUSB2PHY_PWR_CTRL2); + /* IMP_CTRL1: Control the impedance reduction */ + write32(&phy->imp_ctrl1, QUSB2PHY_IMP_CTRL1); + /* IMP_CTRL2: Impedance offset/mapping slope */ + write32(&phy->imp_ctrl2, QUSB2PHY_IMP_CTRL1); + write32(&phy->chg_ctrl2, QUSB2PHY_IMP_CTRL2); + /* + * TUNE1: Sets HS Impedance to approx 45 ohms + * then override with efuse value. + */ + write32(&phy->tune1, QUSB2PHY_PORT_TUNE1); + /* TUNE2: Tuning for HS Disconnect Level */ + write32(&phy->tune2, QUSB2PHY_PORT_TUNE2); + /* TUNE3: Tune squelch range */ + write32(&phy->tune3, QUSB2PHY_PORT_TUNE3); + /* TUNE4: Sets EOP_DLY(Squelch rising edge to linestate falling edge) */ + write32(&phy->tune4, QUSB2PHY_PORT_TUNE4); + write32(&phy->tune5, QUSB2PHY_PORT_TUNE5); + + if (dwc3->board_data) { + /* Override board specific PHY tuning values */ + qusb2_phy_override_phy_params(dwc3); + + /* Set efuse value for tuning the PHY */ + qusb2_phy_set_tune_param(dwc3); + } +} + +static void hs_qusb_phy_init(struct usb_dwc3_cfg *dwc3) +{ + /* PWR_CTRL: set the power down bit to disable the PHY */ + setbits_le32(&dwc3->qusb_phy_dig->pwr_ctrl1, POWER_DOWN); + + write32(&dwc3->qusb_phy_pll->analog_controls_two, + QUSB2PHY_PLL_ANALOG_CONTROLS_TWO); + write32(&dwc3->qusb_phy_pll->clock_inverters, + QUSB2PHY_PLL_CLOCK_INVERTERS); + write32(&dwc3->qusb_phy_pll->cmode, + QUSB2PHY_PLL_CMODE); + write32(&dwc3->qusb_phy_pll->lock_delay, + QUSB2PHY_PLL_LOCK_DELAY); + write32(&dwc3->qusb_phy_pll->dig_tim, + QUSB2PHY_PLL_DIGITAL_TIMERS_TWO); + write32(&dwc3->qusb_phy_pll->bias_ctrl_1, + QUSB2PHY_PLL_BIAS_CONTROL_1); + write32(&dwc3->qusb_phy_pll->bias_ctrl_2, + QUSB2PHY_PLL_BIAS_CONTROL_2); + + tune_phy(dwc3, dwc3->qusb_phy_dig); + + /* PWR_CTRL1: Clear the power down bit to enable the PHY */ + clrbits_le32(&dwc3->qusb_phy_dig->pwr_ctrl1, POWER_DOWN); + + write32(&dwc3->qusb_phy_dig->debug_ctrl2, + DEBUG_CTRL2_MUX_PLL_LOCK_STATUS); + + /* + * DEBUG_STAT5: wait for 160uS for PLL lock; + * vstatus[0] changes from 0 to 1. + */ + long lock_us = wait_us(160, read32(&dwc3->qusb_phy_dig->debug_stat5) & + VSTATUS_PLL_LOCK_STATUS_MASK); + if (!lock_us) + printk(BIOS_ERR, "ERROR: QUSB PHY PLL LOCK fails\n"); + else + printk(BIOS_DEBUG, "QUSB PHY initialized and locked in %ldus\n", + lock_us); +} + +static void qcom_qmp_phy_configure(const struct qmp_phy_init_tbl tbl[], + int num) +{ + int i; + const struct qmp_phy_init_tbl *t = tbl; + + if (!t) + return; + + for (i = 0; i < num; i++, t++) + write32(t->address, t->val); +} + +static void ss_qmp_phy_init(struct usb_dwc3_cfg *dwc3) +{ + /* power up USB3 PHY */ + write32(&dwc3->qmp_pcs_reg->pcs_power_down_control, 0x01); + + /* Serdes configuration */ + qcom_qmp_phy_configure(dwc3->serdes_tbl, dwc3->serdes_tbl_num); + /* Tx, Rx, and PCS configurations */ + qcom_qmp_phy_configure(dwc3->tx_tbl, dwc3->tx_tbl_num); + qcom_qmp_phy_configure(dwc3->rx_tbl, dwc3->rx_tbl_num); + qcom_qmp_phy_configure(dwc3->pcs_tbl, dwc3->pcs_tbl_num); + + /* perform software reset of PCS/Serdes */ + write32(&dwc3->qmp_pcs_reg->pcs_sw_reset, 0x00); + /* start PCS/Serdes to operation mode */ + write32(&dwc3->qmp_pcs_reg->pcs_start_control, 0x03); + + /* + * Wait for PHY initialization to be done + * PCS_STATUS: wait for 1ms for PHY STATUS; + * SW can continuously check for PHYSTATUS = 1.b0. + */ + long lock_us = wait_us(1000, + !(read32(&dwc3->qmp_pcs_reg->pcs_ready_status) & + USB3_PCS_PHYSTATUS)); + if (!lock_us) + printk(BIOS_ERR, "ERROR: QMP PHY PLL LOCK fails:\n"); + else + printk(BIOS_DEBUG, "QMP PHY initialized and locked in %ldus\n", + lock_us); +} + +static void setup_dwc3(struct usb_dwc3 *dwc3) +{ + /* core exits U1/U2/U3 only in PHY power state P1/P2/P3 respectively */ + clrsetbits_le32(&dwc3->usb3pipectl, + DWC3_GUSB3PIPECTL_DELAYP1TRANS, + DWC3_GUSB3PIPECTL_UX_EXIT_IN_PX); + + /* + * Configure USB phy interface of DWC3 core. + * 1. Select UTMI+ PHY with 16-bit interface. + * 2. Set USBTRDTIM to the corresponding value + * according to the UTMI+ PHY interface. + */ + clrsetbits_le32(&dwc3->usb2phycfg, + (DWC3_GUSB2PHYCFG_USB2TRDTIM_MASK | + DWC3_GUSB2PHYCFG_PHYIF_MASK), + (DWC3_GUSB2PHYCFG_PHYIF(UTMI_PHYIF_8_BIT) | + DWC3_GUSB2PHYCFG_USBTRDTIM(USBTRDTIM_UTMI_8_BIT))); + + clrsetbits_le32(&dwc3->ctl, (DWC3_GCTL_SCALEDOWN_MASK | + DWC3_GCTL_DISSCRAMBLE), + DWC3_GCTL_U2EXIT_LFPS | DWC3_GCTL_DSBLCLKGTNG); + + /* configure controller in Host mode */ + clrsetbits_le32(&dwc3->ctl, (DWC3_GCTL_PRTCAPDIR(DWC3_GCTL_PRTCAP_OTG)), + DWC3_GCTL_PRTCAPDIR(DWC3_GCTL_PRTCAP_HOST)); + printk(BIOS_SPEW, "Configure USB in Host mode\n"); +} + +/* Initialization of DWC3 Core and PHY */ +static void setup_usb_host(struct usb_dwc3_cfg *dwc3, + struct usb_board_data *board_data) +{ + dwc3->board_data = board_data; + + /* Clear core reset. */ + clock_reset_bcr(dwc3->usb3_bcr, 0); + + /* Clear QUSB PHY reset. */ + clock_reset_bcr(dwc3->qusb2phy_bcr, 0); + + /* Initialize QUSB PHY */ + hs_qusb_phy_init(dwc3); + + /* Clear QMP PHY resets. */ + clock_reset_bcr(dwc3->gcc_usb3phy_bcr_reg, 0); + clock_reset_bcr(dwc3->gcc_qmpphy_bcr_reg, 0); + + /* Initialize QMP PHY */ + ss_qmp_phy_init(dwc3); + + setup_dwc3(dwc3->usb_host_dwc3); + + printk(BIOS_INFO, "DWC3 and PHY setup finished\n"); +} + +void setup_usb_host0(struct usb_board_data *board_data) +{ + printk(BIOS_INFO, "Setting up USB HOST0 controller.\n"); + setup_usb_host(&usb_port0, board_data); +} From 655220ae69b553e600d6225b550f045e9b212638 Mon Sep 17 00:00:00 2001 From: T Michael Turney Date: Tue, 22 Oct 2019 06:26:21 -0700 Subject: [PATCH 0550/1242] trogdor: Add mainboard USB support Change-Id: I126d1d6b582ea95c97ac55784d44d3081aabdae7 Signed-off-by: Sandeep Maheswaram Reviewed-on: https://review.coreboot.org/c/coreboot/+/36232 Tested-by: build bot (Jenkins) Reviewed-by: Julius Werner --- src/mainboard/google/trogdor/mainboard.c | 14 +++++++++++++- src/mainboard/google/trogdor/romstage.c | 12 ++++++++++++ 2 files changed, 25 insertions(+), 1 deletion(-) diff --git a/src/mainboard/google/trogdor/mainboard.c b/src/mainboard/google/trogdor/mainboard.c index 42af265cd9..63fac19984 100644 --- a/src/mainboard/google/trogdor/mainboard.c +++ b/src/mainboard/google/trogdor/mainboard.c @@ -18,10 +18,22 @@ #include #include #include +#include + +static struct usb_board_data usb0_board_data = { + .pll_bias_control_2 = 0x22, + .imp_ctrl1 = 0x08, + .port_tune1 = 0xc5, +}; + +static void setup_usb(void) +{ + setup_usb_host0(&usb0_board_data); +} static void mainboard_init(struct device *dev) { - + setup_usb(); } static void mainboard_enable(struct device *dev) diff --git a/src/mainboard/google/trogdor/romstage.c b/src/mainboard/google/trogdor/romstage.c index 718538728c..872798a791 100644 --- a/src/mainboard/google/trogdor/romstage.c +++ b/src/mainboard/google/trogdor/romstage.c @@ -14,10 +14,22 @@ */ #include +#include #include +static void prepare_usb(void) +{ + /* + * Do DWC3 core and phy reset. Kick these resets + * off early so they get at least 1ms to settle. + */ + reset_usb0(); +} + void platform_romstage_main(void) { + prepare_usb(); + /* QCLib: DDR init & train */ qclib_load_and_run(); } From 31a5ff5e36ea499f87a8947875a067c843a45532 Mon Sep 17 00:00:00 2001 From: T Michael Turney Date: Tue, 22 Oct 2019 06:28:03 -0700 Subject: [PATCH 0551/1242] trogdor: libpayload USB support Change-Id: I26c28f9af8d819f4644e383e8d0293a3d5de9eef Signed-off-by: Sandeep Maheswaram Reviewed-on: https://review.coreboot.org/c/coreboot/+/36233 Tested-by: build bot (Jenkins) Reviewed-by: Julius Werner --- payloads/libpayload/configs/config.trogdor | 6 ++++++ 1 file changed, 6 insertions(+) create mode 100644 payloads/libpayload/configs/config.trogdor diff --git a/payloads/libpayload/configs/config.trogdor b/payloads/libpayload/configs/config.trogdor new file mode 100644 index 0000000000..413f66ffe8 --- /dev/null +++ b/payloads/libpayload/configs/config.trogdor @@ -0,0 +1,6 @@ +CONFIG_LP_CHROMEOS=y +CONFIG_LP_ARCH_ARM64=y +CONFIG_LP_TIMER_ARM64_ARCH=y +CONFIG_LP_USB=y +CONFIG_LP_USB_EHCI=y +CONFIG_LP_USB_XHCI=y From bb345abbfc999f70e3f0f9739f13e1f45d5a0fe9 Mon Sep 17 00:00:00 2001 From: Julius Werner Date: Tue, 3 Dec 2019 22:47:01 -0800 Subject: [PATCH 0552/1242] arm64: Correctly unmask asynchronous SError interrupts Arm CPUs have always had an odd feature that allows you to mask not only true interrupts, but also "external aborts" (memory bus errors from outside the CPU). CPUs usually have all of these masked after reset, which we quickly learned was a bad idea back when bringing up the first arm32 systems in coreboot. Masking external aborts means that if any of your firmware code does an illegal memory access, you will only see it once the kernel comes up and unmasks the abort (not when it happens). Therefore, we always unmask everything in early bootblock assembly code. When arm64 came around, it had very similar masking bits and we did the same there, thinking the issue resolved. Unfortunately Arm, in their ceaseless struggle for more complexity, decided that having a single bit to control this masking behavior is no longer enough: on AArch64, in addition to the PSTATE.DAIF bits that are analogous to arm32's CPSR, there are additional bits in SCR_EL3 that can override the PSTATE setting for some but not all cases (makes perfect sense, I know...). When aborts are unmasked in PSTATE, but SCR.EA is not set, then synchronous external aborts will cause an exception while asynchronous external aborts will not. It turns out we never intialize SCR in coreboot and on RK3399 it comes up with all zeroes (even the reserved-1 bits, which is super weird). If you get an asynchronous external abort in coreboot it will silently hide in the CPU until BL31 enables SCR.EA before it has its own console handlers registered and silently hangs. This patch resolves the issue by also initializing SCR to a known good state early in the bootblock. It also cleans up some bit defintions and slightly reworks the DAIF unmasking... it doesn't actually make that much sense to unmask anything before our console and exception handlers are up. The new code will mask everything until the exception handler is installed and then unmask it, so that if there was a super early external abort we could still see it. (Of course there are still dozens of other processor exceptions that could happen which we have no way to mask.) Change-Id: I5266481a7aaf0b72aca8988accb671d92739af6f Signed-off-by: Julius Werner Reviewed-on: https://review.coreboot.org/c/coreboot/+/37463 Tested-by: build bot (Jenkins) Reviewed-by: Hung-Te Lin --- src/arch/arm64/armv8/cpu.S | 30 +++--- src/arch/arm64/include/armv8/arch/cache.h | 22 +---- .../arm64/include/armv8/arch/lib_helpers.h | 99 +++++++------------ src/arch/arm64/transition.c | 32 ++---- src/arch/arm64/transition_asm.S | 5 +- 5 files changed, 59 insertions(+), 129 deletions(-) diff --git a/src/arch/arm64/armv8/cpu.S b/src/arch/arm64/armv8/cpu.S index 2bc4defde8..5f06c7e677 100644 --- a/src/arch/arm64/armv8/cpu.S +++ b/src/arch/arm64/armv8/cpu.S @@ -99,15 +99,14 @@ ENDPROC(mmu_disable) /* * Bring an ARMv8 processor we just gained control of (e.g. from IROM) into a - * known state regarding caches/SCTLR/PSTATE. Completely invalidates + * known state regarding caches/SCTLR/SCR/PSTATE. Completely invalidates * icache/dcache, disables MMU and dcache (if active), and enables unaligned - * accesses, icache and branch prediction (if inactive). Seeds the stack and - * initializes SP_EL0. Clobbers R22 and R23. + * accesses, icache. Seeds stack and initializes SP_EL0. Clobbers R22 and R23. */ ENTRY(arm64_init_cpu) - /* Initialize PSTATE (unmask all exceptions, select SP_EL0). */ + /* Initialize PSTATE (mask all exceptions, select SP_EL0). */ msr SPSel, #0 - msr DAIFClr, #0xf + msr DAIFSet, #0xf /* TODO: This is where we'd put non-boot CPUs into WFI if needed. */ @@ -116,24 +115,25 @@ ENTRY(arm64_init_cpu) /* TODO: Assert that we always start running at EL3 */ mrs x22, sctlr_el3 - /* Activate ICache (12) already for speed during cache flush below. */ - orr x22, x22, #(1 << 12) + /* Activate ICache already for speed during cache flush below. */ + orr x22, x22, #SCTLR_I msr sctlr_el3, x22 isb /* Invalidate dcache */ bl dcache_invalidate_all - /* Deactivate MMU (0), Alignment Check (1) and DCache (2) */ - and x22, x22, # ~(1 << 0) & ~(1 << 1) & ~(1 << 2) - /* Activate Stack Alignment (3) because why not */ - orr x22, x22, #(1 << 3) - /* Set to little-endian (25) */ - and x22, x22, # ~(1 << 25) - /* Deactivate write-xor-execute enforcement (19) */ - and x22, x22, # ~(1 << 19) + /* Reinitialize SCTLR from scratch to known-good state. + This may disable MMU or DCache. */ + ldr w22, =(SCTLR_RES1 | SCTLR_I | SCTLR_SA) msr sctlr_el3, x22 + /* Initialize SCR to unmask all interrupts (so that if we get a spurious + IRQ/SError we'll see it when it happens, not hang in BL31). This will + only have an effect after we DAIFClr in exception_init(). */ + mov x22, #SCR_RES1 | SCR_IRQ | SCR_FIQ | SCR_EA + msr scr_el3, x22 + /* Invalidate icache and TLB for good measure */ ic iallu tlbi alle3 diff --git a/src/arch/arm64/include/armv8/arch/cache.h b/src/arch/arm64/include/armv8/arch/cache.h index 3de2e80877..1168992cc4 100644 --- a/src/arch/arm64/include/armv8/arch/cache.h +++ b/src/arch/arm64/include/armv8/arch/cache.h @@ -32,33 +32,13 @@ #ifndef ARM_ARM64_CACHE_H #define ARM_ARM64_CACHE_H -/* SCTLR_ELx common bits */ -#define SCTLR_M (1 << 0) /* MMU enable */ -#define SCTLR_A (1 << 1) /* Alignment check enable */ -#define SCTLR_C (1 << 2) /* Data/unified cache enable */ -#define SCTLR_SA (1 << 3) /* Stack alignment check enable */ -#define SCTLR_I (1 << 12) /* Instruction cache enable */ -#define SCTLR_WXN (1 << 19) /* Write permission implies XN */ -#define SCTLR_EE (1 << 25) /* Exception endianness */ - -/* SCTLR_EL1 bits */ -#define SCTLR_EL1_CP15B (1 << 5) /* CP15 barrier enable */ -#define SCTLR_EL1_ITD (1 << 7) /* IT disable */ -#define SCTLR_EL1_SED (1 << 8) /* SETEND disable */ -#define SCTLR_EL1_UMA (1 << 9) /* User mask access */ -#define SCTLR_EL1_DZE (1 << 14) /* DC ZVA instruction at EL0 */ -#define SCTLR_EL1_UCT (1 << 15) /* CTR_EL0 register EL0 access */ -#define SCTLR_EL1_NTWI (1 << 16) /* Not trap WFI */ -#define SCTLR_EL1_NTWE (1 << 18) /* Not trap WFE */ -#define SCTLR_EL1_E0E (1 << 24) /* Exception endianness at EL0 */ -#define SCTLR_EL1_UCI (1 << 26) /* EL0 access to cache instructions */ +#include #ifndef __ASSEMBLER__ #include #include #include -#include /* dcache clean by virtual address to PoC */ void dcache_clean_by_mva(void const *addr, size_t len); diff --git a/src/arch/arm64/include/armv8/arch/lib_helpers.h b/src/arch/arm64/include/armv8/arch/lib_helpers.h index 0afbf82a23..9d5b508453 100644 --- a/src/arch/arm64/include/armv8/arch/lib_helpers.h +++ b/src/arch/arm64/include/armv8/arch/lib_helpers.h @@ -38,79 +38,46 @@ #define SPSR_DEBUG (1 << 9) #define SPSR_EXCEPTION_MASK (SPSR_FIQ | SPSR_IRQ | SPSR_SERROR | SPSR_DEBUG) -#define SCR_NS_SHIFT 0 -#define SCR_NS_MASK (1 << SCR_NS_SHIFT) -#define SCR_NS_ENABLE (1 << SCR_NS_SHIFT) -#define SCR_NS_DISABLE (0 << SCR_NS_SHIFT) -#define SCR_NS SCR_NS_ENABLE -#define SCR_RES1 (0x3 << 4) -#define SCR_IRQ_SHIFT 2 -#define SCR_IRQ_MASK (1 << SCR_IRQ_SHIFT) -#define SCR_IRQ_ENABLE (1 << SCR_IRQ_SHIFT) -#define SCR_IRQ_DISABLE (0 << SCR_IRQ_SHIFT) -#define SCR_FIQ_SHIFT 2 -#define SCR_FIQ_MASK (1 << SCR_FIQ_SHIFT) -#define SCR_FIQ_ENABLE (1 << SCR_FIQ_SHIFT) -#define SCR_FIQ_DISABLE (0 << SCR_FIQ_SHIFT) -#define SCR_EA_SHIFT 3 -#define SCR_EA_MASK (1 << SCR_EA_SHIFT) -#define SCR_EA_ENABLE (1 << SCR_EA_SHIFT) -#define SCR_EA_DISABLE (0 << SCR_EA_SHIFT) -#define SCR_SMD_SHIFT 7 -#define SCR_SMD_MASK (1 << SCR_SMD_SHIFT) -#define SCR_SMD_DISABLE (1 << SCR_SMD_SHIFT) -#define SCR_SMD_ENABLE (0 << SCR_SMD_SHIFT) -#define SCR_HVC_SHIFT 8 -#define SCR_HVC_MASK (1 << SCR_HVC_SHIFT) -#define SCR_HVC_DISABLE (0 << SCR_HVC_SHIFT) -#define SCR_HVC_ENABLE (1 << SCR_HVC_SHIFT) -#define SCR_SIF_SHIFT 9 -#define SCR_SIF_MASK (1 << SCR_SIF_SHIFT) -#define SCR_SIF_ENABLE (1 << SCR_SIF_SHIFT) -#define SCR_SIF_DISABLE (0 << SCR_SIF_SHIFT) -#define SCR_RW_SHIFT 10 -#define SCR_RW_MASK (1 << SCR_RW_SHIFT) -#define SCR_LOWER_AARCH64 (1 << SCR_RW_SHIFT) -#define SCR_LOWER_AARCH32 (0 << SCR_RW_SHIFT) -#define SCR_ST_SHIFT 11 -#define SCR_ST_MASK (1 << SCR_ST_SHIFT) -#define SCR_ST_ENABLE (1 << SCR_ST_SHIFT) -#define SCR_ST_DISABLE (0 << SCR_ST_SHIFT) -#define SCR_TWI_SHIFT 12 -#define SCR_TWI_MASK (1 << SCR_TWI_SHIFT) -#define SCR_TWI_ENABLE (1 << SCR_TWI_SHIFT) -#define SCR_TWI_DISABLE (0 << SCR_TWI_SHIFT) -#define SCR_TWE_SHIFT 13 -#define SCR_TWE_MASK (1 << SCR_TWE_SHIFT) -#define SCR_TWE_ENABLE (1 << SCR_TWE_SHIFT) -#define SCR_TWE_DISABLE (0 << SCR_TWE_SHIFT) +#define SCR_NS (1 << 0) /* EL0/1 are non-secure */ +#define SCR_IRQ (1 << 1) /* Take IRQs in EL3 */ +#define SCR_FIQ (1 << 2) /* Take FIQs in EL3 */ +#define SCR_EA (1 << 3) /* Take EA/SError in EL3 */ +#define SCR_SMD (1 << 7) /* Disable SMC instruction */ +#define SCR_HCE (1 << 8) /* Enable HVC instruction */ +#define SCR_SIF (1 << 9) /* Forbid insns from NS memory */ +#define SCR_RW (1 << 10) /* Lower ELs are AArch64 */ +#define SCR_ST (1 << 11) /* Don't trap secure CNTPS */ +#define SCR_TWI (1 << 12) /* Trap WFI to EL3 */ +#define SCR_TWE (1 << 13) /* Trap WFE to EL3 */ +#define SCR_TLOR (1 << 14) /* Trap LOR accesses to EL3 */ +#define SCR_TERR (1 << 15) /* Trap ERR accesses to EL3 */ +#define SCR_APK (1 << 16) /* Don't trap ptrauth keys */ +#define SCR_API (1 << 17) /* Don't trap ptrauth insn */ +#define SCR_EEL2 (1 << 18) /* Enable secure EL2 */ +#define SCR_EASE (1 << 19) /* Sync EAs use SError vector */ +#define SCR_NMEA (1 << 20) /* Disallow EL3 SError masking */ +#define SCR_FIEN (1 << 21) /* Don't trap EXRPFG */ +#define SCR_RES1 (3 << 4) #define HCR_RW_SHIFT 31 #define HCR_LOWER_AARCH64 (1 << HCR_RW_SHIFT) #define HCR_LOWER_AARCH32 (0 << HCR_RW_SHIFT) -#define SCTLR_MMU_ENABLE 1 -#define SCTLR_MMU_DISABLE 0 -#define SCTLR_ACE_SHIFT 1 -#define SCTLR_ACE_ENABLE (1 << SCTLR_ACE_SHIFT) -#define SCTLR_ACE_DISABLE (0 << SCTLR_ACE_SHIFT) -#define SCTLR_CACHE_SHIFT 2 -#define SCTLR_CACHE_ENABLE (1 << SCTLR_CACHE_SHIFT) -#define SCTLR_CACHE_DISABLE (0 << SCTLR_CACHE_SHIFT) -#define SCTLR_SAE_SHIFT 3 -#define SCTLR_SAE_ENABLE (1 << SCTLR_SAE_SHIFT) -#define SCTLR_SAE_DISABLE (0 << SCTLR_SAE_SHIFT) +#define SCTLR_M (1 << 0) /* MMU enable */ +#define SCTLR_A (1 << 1) /* Alignment check enable */ +#define SCTLR_C (1 << 2) /* Data/unified cache enable */ +#define SCTLR_SA (1 << 3) /* Stack alignment check enable */ +#define SCTLR_NAA (1 << 6) /* non-aligned access STA/LDR */ +#define SCTLR_I (1 << 12) /* Instruction cache enable */ +#define SCTLR_ENDB (1 << 13) /* Pointer auth (data B) */ +#define SCTLR_WXN (1 << 19) /* Write permission implies XN */ +#define SCTLR_IESB (1 << 21) /* Implicit error sync event */ +#define SCTLR_EE (1 << 25) /* Exception endianness (BE) */ +#define SCTLR_ENDA (1 << 27) /* Pointer auth (data A) */ +#define SCTLR_ENIB (1 << 30) /* Pointer auth (insn B) */ +#define SCTLR_ENIA (1 << 31) /* Pointer auth (insn A) */ #define SCTLR_RES1 ((0x3 << 4) | (0x1 << 11) | (0x1 << 16) | \ (0x1 << 18) | (0x3 << 22) | (0x3 << 28)) -#define SCTLR_ICE_SHIFT 12 -#define SCTLR_ICE_ENABLE (1 << SCTLR_ICE_SHIFT) -#define SCTLR_ICE_DISABLE (0 << SCTLR_ICE_SHIFT) -#define SCTLR_WXN_SHIFT 19 -#define SCTLR_WXN_ENABLE (1 << SCTLR_WXN_SHIFT) -#define SCTLR_WXN_DISABLE (0 << SCTLR_WXN_SHIFT) -#define SCTLR_ENDIAN_SHIFT 25 -#define SCTLR_LITTLE_END (0 << SCTLR_ENDIAN_SHIFT) -#define SCTLR_BIG_END (1 << SCTLR_ENDIAN_SHIFT) #define CPTR_EL3_TCPAC_SHIFT (31) #define CPTR_EL3_TTA_SHIFT (20) diff --git a/src/arch/arm64/transition.c b/src/arch/arm64/transition.c index 3e8d7f0762..ac59d19acf 100644 --- a/src/arch/arm64/transition.c +++ b/src/arch/arm64/transition.c @@ -17,14 +17,6 @@ #include #include -/* Litte-endian, No XN-forced, Instr cache disabled, - * Stack alignment disabled, Data and unified cache - * disabled, Alignment check disabled, MMU disabled - */ -#define SCTLR_MASK (SCTLR_MMU_DISABLE | SCTLR_ACE_DISABLE | \ - SCTLR_CACHE_DISABLE | SCTLR_SAE_DISABLE | SCTLR_RES1 | \ - SCTLR_ICE_DISABLE | SCTLR_WXN_DISABLE | SCTLR_LITTLE_END) - void __weak exc_dispatch(struct exc_state *exc_state, uint64_t id) { /* Default weak implementation does nothing. */ @@ -54,7 +46,6 @@ void transition_to_el2(void *entry, void *arg, uint64_t spsr) struct exc_state exc_state; struct elx_state *elx = &exc_state.elx; struct regs *regs = &exc_state.regs; - uint32_t sctlr; regs->x[X0_INDEX] = (uint64_t)arg; elx->elr = (uint64_t)entry; @@ -70,19 +61,10 @@ void transition_to_el2(void *entry, void *arg, uint64_t spsr) */ assert(get_el_from_spsr(spsr) == EL2 && !(spsr & SPSR_ERET_32)); - /* Initialize SCR with defaults for running without secure monitor. */ - raw_write_scr_el3(SCR_TWE_DISABLE | /* don't trap WFE */ - SCR_TWI_DISABLE | /* don't trap WFI */ - SCR_ST_ENABLE | /* allow secure timer access */ - SCR_LOWER_AARCH64 | /* lower level is AArch64 */ - SCR_SIF_DISABLE | /* disable secure ins. fetch */ - SCR_HVC_ENABLE | /* allow HVC instruction */ - SCR_SMD_ENABLE | /* disable SMC instruction */ - SCR_RES1 | /* reserved-1 bits */ - SCR_EA_DISABLE | /* disable ext. abort trap */ - SCR_FIQ_DISABLE | /* disable FIQ trap to EL3 */ - SCR_IRQ_DISABLE | /* disable IRQ trap to EL3 */ - SCR_NS_ENABLE); /* lower level is non-secure */ + /* Initialize SCR with defaults for running without secure monitor + (disable all traps, enable all instructions, run NS at AArch64). */ + raw_write_scr_el3(SCR_FIEN | SCR_API | SCR_APK | SCR_ST | SCR_RW | + SCR_HCE | SCR_SMD | SCR_RES1 | SCR_NS); /* Initialize CPTR to not trap anything to EL3. */ raw_write_cptr_el3(CPTR_EL3_TCPAC_DISABLE | CPTR_EL3_TTA_DISABLE | @@ -92,10 +74,8 @@ void transition_to_el2(void *entry, void *arg, uint64_t spsr) raw_write_elr_el3(elx->elr); raw_write_spsr_el3(elx->spsr); - /* SCTLR: Initialize EL with selected properties */ - sctlr = raw_read_sctlr_el2(); - sctlr &= SCTLR_MASK; - raw_write_sctlr_el2(sctlr); + /* SCTLR: Initialize EL with everything disabled */ + raw_write_sctlr_el2(SCTLR_RES1); /* SP_ELx: Initialize stack pointer */ raw_write_sp_el2(elx->sp_elx); diff --git a/src/arch/arm64/transition_asm.S b/src/arch/arm64/transition_asm.S index 718832b421..bdb412f36d 100644 --- a/src/arch/arm64/transition_asm.S +++ b/src/arch/arm64/transition_asm.S @@ -154,7 +154,7 @@ ENDPROC(exc_exit) /* * exception_init_asm: Initialize VBAR and point SP_EL3 to exception stack. - * x0 = end of exception stack + * Also unmask aborts now that we can report them. x0 = end of exception stack */ ENTRY(exception_init_asm) msr SPSel, #SPSR_USE_H @@ -163,6 +163,9 @@ ENTRY(exception_init_asm) adr x0, exc_vectors msr vbar_el3, x0 + + msr DAIFClr, #0xf + dsb sy isb ret From 2e0bca011af0518f7335a700ea04082611b3ddad Mon Sep 17 00:00:00 2001 From: Julius Werner Date: Tue, 3 Dec 2019 23:04:41 -0800 Subject: [PATCH 0553/1242] arm64: Bump exception stack size to 2KB To avoid trampling over interesting exception artifacts on the real stack, our arm64 systems switch to a separate exception stack when entering an exception handler. We don't want that to use up too much SRAM so we just set it to 512 bytes. I mean it just prints a bunch of registers, how much stack could it need, right? Quite a bit it turns out. The whole vtxprintf() call stack goes pretty deep, and aarch64 generally seems to be very generous with stack space. Just the varargs handling seems to require 128 bytes for some reason, and the other stuff adds up too. In the end the current implementation takes 1008 bytes, so bump the exception stack size to 2K to make sure it fits. Change-Id: I910be4c5f6b29fae35eb53929c733a1bd4585377 Signed-off-by: Julius Werner Reviewed-on: https://review.coreboot.org/c/coreboot/+/37464 Tested-by: build bot (Jenkins) Reviewed-by: Hung-Te Lin --- payloads/libpayload/arch/arm64/exception.c | 2 +- src/arch/arm64/armv8/exception.c | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/payloads/libpayload/arch/arm64/exception.c b/payloads/libpayload/arch/arm64/exception.c index a5e55163a8..d9bd3e6af5 100644 --- a/payloads/libpayload/arch/arm64/exception.c +++ b/payloads/libpayload/arch/arm64/exception.c @@ -31,7 +31,7 @@ #include #include -u64 exception_stack[0x200] __attribute__((aligned(16))); +u64 exception_stack[2*KiB] __attribute__((aligned(16))); u64 *exception_stack_end = exception_stack + ARRAY_SIZE(exception_stack); extern unsigned int test_exc; diff --git a/src/arch/arm64/armv8/exception.c b/src/arch/arm64/armv8/exception.c index 579e1040b4..13f456da26 100644 --- a/src/arch/arm64/armv8/exception.c +++ b/src/arch/arm64/armv8/exception.c @@ -36,7 +36,7 @@ #include #include -uint8_t exception_stack[0x200] __attribute__((aligned(16))); +uint8_t exception_stack[2*KiB] __attribute__((aligned(16))); static const char *exception_names[NUM_EXC_VIDS] = { [EXC_VID_CUR_SP_EL0_SYNC] = "_sync_sp_el0", From 51359d6c843b95fe09f1f7b63cb97f7cda06ac3c Mon Sep 17 00:00:00 2001 From: Julius Werner Date: Tue, 3 Dec 2019 23:29:26 -0800 Subject: [PATCH 0554/1242] arm64: Print a char to UART early in exception handler Over time our printk() seems to acquire more and more features... which is nice, but it also makes it a little less robust when something goes wrong. If the wrong global is trampled by some buffer overflow, it suddenly doesn't print anymore. It would be nice to have at least some way to tell that we triggered a real exception in that case. With this patch, arm64 exceptions will print a '!' straight to the UART before trying any of the more fancy printk() stuff. It's not much but it should tell the difference between an exception and a hang and hopefully help someone dig in the right direction sooner. This violates loglevels (which is part of the point), but presumably when you have a fatal exception you shouldn't care about that anymore. Change-Id: I3b08ab86beaee55263786011caa5588d93bbc720 Signed-off-by: Julius Werner Reviewed-on: https://review.coreboot.org/c/coreboot/+/37465 Reviewed-by: Hung-Te Lin Tested-by: build bot (Jenkins) --- src/arch/arm64/armv8/exception.c | 10 ++++++++-- 1 file changed, 8 insertions(+), 2 deletions(-) diff --git a/src/arch/arm64/armv8/exception.c b/src/arch/arm64/armv8/exception.c index 13f456da26..4d566aa415 100644 --- a/src/arch/arm64/armv8/exception.c +++ b/src/arch/arm64/armv8/exception.c @@ -34,6 +34,7 @@ #include #include #include +#include #include uint8_t exception_stack[2*KiB] __attribute__((aligned(16))); @@ -131,8 +132,13 @@ int exception_handler_unregister(uint64_t vid, struct exception_handler *h) static void print_exception_info(struct exc_state *state, uint64_t idx) { - if (idx < NUM_EXC_VIDS) - printk(BIOS_DEBUG, "exception %s\n", exception_names[idx]); + /* Poor man's sign of life in case printk() is shot. */ + __uart_tx_byte('\r'); + __uart_tx_byte('\n'); + __uart_tx_byte('!'); + + printk(BIOS_DEBUG, "\nexception %s\n", + idx < NUM_EXC_VIDS ? exception_names[idx] : "_unknown"); print_regs(state); /* Few words below SP in case we need state from a returned function. */ From 53486a0be0f4c8a9647158b91fb82cb951b07297 Mon Sep 17 00:00:00 2001 From: Aamir Bohra Date: Fri, 29 Nov 2019 14:42:33 +0530 Subject: [PATCH 0555/1242] mb/intel/icelake_rvp: Remove nested variant header references Change-Id: I11b2d75dc0d4ff180b03324e5ce3d5590c8169a5 Signed-off-by: Aamir Bohra Reviewed-on: https://review.coreboot.org/c/coreboot/+/37356 Tested-by: build bot (Jenkins) Reviewed-by: Rizwan Qureshi --- src/mainboard/intel/icelake_rvp/Makefile.inc | 1 - src/mainboard/intel/icelake_rvp/bootblock.c | 2 +- src/mainboard/intel/icelake_rvp/chromeos.c | 3 +- src/mainboard/intel/icelake_rvp/dsdt.asl | 4 +- src/mainboard/intel/icelake_rvp/hda_verb.c | 3 +- src/mainboard/intel/icelake_rvp/mainboard.c | 2 +- .../variants/baseboard/include/baseboard/ec.h | 4 +- .../include/baseboard}/hda_verb.h | 0 .../baseboard/include/baseboard/variants.h | 1 - .../variants/icl_u/include/variant/ec.h | 21 - .../variants/icl_u/include/variant/gpio.h | 21 - .../variants/icl_y/include/variant/ec.h | 21 - .../variants/icl_y/include/variant/gpio.h | 21 - .../variants/icl_y/include/variant/hda_verb.h | 700 ------------------ 14 files changed, 7 insertions(+), 797 deletions(-) rename src/mainboard/intel/icelake_rvp/variants/{icl_u/include/variant => baseboard/include/baseboard}/hda_verb.h (100%) delete mode 100644 src/mainboard/intel/icelake_rvp/variants/icl_u/include/variant/ec.h delete mode 100644 src/mainboard/intel/icelake_rvp/variants/icl_u/include/variant/gpio.h delete mode 100644 src/mainboard/intel/icelake_rvp/variants/icl_y/include/variant/ec.h delete mode 100644 src/mainboard/intel/icelake_rvp/variants/icl_y/include/variant/gpio.h delete mode 100644 src/mainboard/intel/icelake_rvp/variants/icl_y/include/variant/hda_verb.h diff --git a/src/mainboard/intel/icelake_rvp/Makefile.inc b/src/mainboard/intel/icelake_rvp/Makefile.inc index 7e74f09beb..74d02cb293 100644 --- a/src/mainboard/intel/icelake_rvp/Makefile.inc +++ b/src/mainboard/intel/icelake_rvp/Makefile.inc @@ -33,4 +33,3 @@ subdirs-y += variants/baseboard CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/variants/baseboard/include subdirs-y += variants/$(VARIANT_DIR) -CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/variants/$(VARIANT_DIR)/include diff --git a/src/mainboard/intel/icelake_rvp/bootblock.c b/src/mainboard/intel/icelake_rvp/bootblock.c index 86559474da..300488f9a0 100644 --- a/src/mainboard/intel/icelake_rvp/bootblock.c +++ b/src/mainboard/intel/icelake_rvp/bootblock.c @@ -13,10 +13,10 @@ * GNU General Public License for more details. */ +#include #include #include #include -#include void bootblock_mainboard_init(void) { diff --git a/src/mainboard/intel/icelake_rvp/chromeos.c b/src/mainboard/intel/icelake_rvp/chromeos.c index 785fe4a862..da3f1d442d 100644 --- a/src/mainboard/intel/icelake_rvp/chromeos.c +++ b/src/mainboard/intel/icelake_rvp/chromeos.c @@ -14,11 +14,10 @@ */ #include +#include #include #include #include -#include -#include #include void fill_lb_gpios(struct lb_gpios *gpios) diff --git a/src/mainboard/intel/icelake_rvp/dsdt.asl b/src/mainboard/intel/icelake_rvp/dsdt.asl index 152f038fc6..f8fcd4d88c 100644 --- a/src/mainboard/intel/icelake_rvp/dsdt.asl +++ b/src/mainboard/intel/icelake_rvp/dsdt.asl @@ -14,8 +14,8 @@ */ #include -#include "variant/ec.h" -#include "variant/gpio.h" +#include +#include DefinitionBlock( "dsdt.aml", diff --git a/src/mainboard/intel/icelake_rvp/hda_verb.c b/src/mainboard/intel/icelake_rvp/hda_verb.c index c87392d3c0..f6ae630c98 100644 --- a/src/mainboard/intel/icelake_rvp/hda_verb.c +++ b/src/mainboard/intel/icelake_rvp/hda_verb.c @@ -12,5 +12,4 @@ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. */ - -#include "variant/hda_verb.h" +#include diff --git a/src/mainboard/intel/icelake_rvp/mainboard.c b/src/mainboard/intel/icelake_rvp/mainboard.c index 8e51e453d3..67695fa827 100644 --- a/src/mainboard/intel/icelake_rvp/mainboard.c +++ b/src/mainboard/intel/icelake_rvp/mainboard.c @@ -14,11 +14,11 @@ */ #include +#include #include #include #include #include -#include static void mainboard_init(void *chip_info) { diff --git a/src/mainboard/intel/icelake_rvp/variants/baseboard/include/baseboard/ec.h b/src/mainboard/intel/icelake_rvp/variants/baseboard/include/baseboard/ec.h index 03096ac777..ed335472e7 100644 --- a/src/mainboard/intel/icelake_rvp/variants/baseboard/include/baseboard/ec.h +++ b/src/mainboard/intel/icelake_rvp/variants/baseboard/include/baseboard/ec.h @@ -18,9 +18,7 @@ #include #include - -#include - +#include #define MAINBOARD_EC_SCI_EVENTS \ (EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_CLOSED) |\ diff --git a/src/mainboard/intel/icelake_rvp/variants/icl_u/include/variant/hda_verb.h b/src/mainboard/intel/icelake_rvp/variants/baseboard/include/baseboard/hda_verb.h similarity index 100% rename from src/mainboard/intel/icelake_rvp/variants/icl_u/include/variant/hda_verb.h rename to src/mainboard/intel/icelake_rvp/variants/baseboard/include/baseboard/hda_verb.h diff --git a/src/mainboard/intel/icelake_rvp/variants/baseboard/include/baseboard/variants.h b/src/mainboard/intel/icelake_rvp/variants/baseboard/include/baseboard/variants.h index 12d16bc72c..a00b3441d2 100644 --- a/src/mainboard/intel/icelake_rvp/variants/baseboard/include/baseboard/variants.h +++ b/src/mainboard/intel/icelake_rvp/variants/baseboard/include/baseboard/variants.h @@ -25,7 +25,6 @@ const struct pad_config *variant_gpio_table(size_t *num); const struct pad_config *variant_early_gpio_table(size_t *num); - const struct cros_gpio *variant_cros_gpios(size_t *num); #endif /*__BASEBOARD_VARIANTS_H__ */ diff --git a/src/mainboard/intel/icelake_rvp/variants/icl_u/include/variant/ec.h b/src/mainboard/intel/icelake_rvp/variants/icl_u/include/variant/ec.h deleted file mode 100644 index af41bf4008..0000000000 --- a/src/mainboard/intel/icelake_rvp/variants/icl_u/include/variant/ec.h +++ /dev/null @@ -1,21 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2018 Intel Corporation. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef __MAINBOARD_EC_H__ -#define __MAINBOARD_EC_H__ - -#include - -#endif /* __MAINBOARD_EC_H__ */ diff --git a/src/mainboard/intel/icelake_rvp/variants/icl_u/include/variant/gpio.h b/src/mainboard/intel/icelake_rvp/variants/icl_u/include/variant/gpio.h deleted file mode 100644 index c34a9b3cd9..0000000000 --- a/src/mainboard/intel/icelake_rvp/variants/icl_u/include/variant/gpio.h +++ /dev/null @@ -1,21 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright 2018 Intel Corporation. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the - * GNU General Public License for more details. - */ - -#ifndef __MAINBOARD_GPIO_H__ -#define __MAINBOARD_GPIO_H__ - -#include - -#endif /* __MAINBOARD_GPIO_H__ */ diff --git a/src/mainboard/intel/icelake_rvp/variants/icl_y/include/variant/ec.h b/src/mainboard/intel/icelake_rvp/variants/icl_y/include/variant/ec.h deleted file mode 100644 index af41bf4008..0000000000 --- a/src/mainboard/intel/icelake_rvp/variants/icl_y/include/variant/ec.h +++ /dev/null @@ -1,21 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2018 Intel Corporation. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef __MAINBOARD_EC_H__ -#define __MAINBOARD_EC_H__ - -#include - -#endif /* __MAINBOARD_EC_H__ */ diff --git a/src/mainboard/intel/icelake_rvp/variants/icl_y/include/variant/gpio.h b/src/mainboard/intel/icelake_rvp/variants/icl_y/include/variant/gpio.h deleted file mode 100644 index c34a9b3cd9..0000000000 --- a/src/mainboard/intel/icelake_rvp/variants/icl_y/include/variant/gpio.h +++ /dev/null @@ -1,21 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright 2018 Intel Corporation. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the - * GNU General Public License for more details. - */ - -#ifndef __MAINBOARD_GPIO_H__ -#define __MAINBOARD_GPIO_H__ - -#include - -#endif /* __MAINBOARD_GPIO_H__ */ diff --git a/src/mainboard/intel/icelake_rvp/variants/icl_y/include/variant/hda_verb.h b/src/mainboard/intel/icelake_rvp/variants/icl_y/include/variant/hda_verb.h deleted file mode 100644 index d821a26531..0000000000 --- a/src/mainboard/intel/icelake_rvp/variants/icl_y/include/variant/hda_verb.h +++ /dev/null @@ -1,700 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2018 Intel Corporation - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef HDA_VERB_H -#define HDA_VERB_H - -#include - -const u32 cim_verb_data[] = { - /* ALC 700 */ - 0x10EC0700, - 0xFFFFFFFF, - 0x00000023, - - AZALIA_SUBVENDOR(0, 0x10EC10F2), - AZALIA_PIN_CFG(0, 0x01, 0x00000000), - AZALIA_PIN_CFG(0, 0x12, 0x40000000), - AZALIA_PIN_CFG(0, 0x13, 0x40000000), - AZALIA_PIN_CFG(0, 0x14, 0x411111F0), - AZALIA_PIN_CFG(0, 0x15, 0x411111F0), - AZALIA_PIN_CFG(0, 0x16, 0x411111F0), - AZALIA_PIN_CFG(0, 0x17, 0x90170110), - AZALIA_PIN_CFG(0, 0x18, 0x411111F0), - AZALIA_PIN_CFG(0, 0x19, 0x04A11030), - AZALIA_PIN_CFG(0, 0x1A, 0x411111F0), - AZALIA_PIN_CFG(0, 0x1B, 0x411111F0), - AZALIA_PIN_CFG(0, 0x1D, 0x40622005), - AZALIA_PIN_CFG(0, 0x1E, 0x411111F0), - AZALIA_PIN_CFG(0, 0x1F, 0x411111F0), - AZALIA_PIN_CFG(0, 0x21, 0x04211020), - AZALIA_PIN_CFG(0, 0x29, 0x411111F0), - - /* Widget node 0x20 */ - 0x02050045, - 0x02045289, - 0x0205004A, - 0x0204201B, - /* Widget node 0x20 - 1 */ - 0x05850000, - 0x05843888, - 0x0205006F, - 0x02042C0B, - - //Widget node 0X20 for ALC1305 20160603 update - 0x02050024, - 0x02040010, - 0x02050026, - 0x02040000, - 0x02050028, - 0x02040000, - 0x02050029, - 0x0204B024, - - 0x02050024, - 0x02040010, - 0x02050026, - 0x02040004, - 0x02050028, - 0x02040600, - 0x02050029, - 0x0204B024, - - 0x02050024, - 0x02040010, - 0x02050026, - 0x0204003C, - 0x02050028, - 0x0204FFD0, - 0x02050029, - 0x0204B024, - - 0x02050024, - 0x02040010, - 0x02050026, - 0x02040080, - 0x02050028, - 0x02040080, - 0x02050029, - 0x0204B024, - - 0x02050024, - 0x02040010, - 0x02050026, - 0x02040080, - 0x02050028, - 0x02040880, - 0x02050029, - 0x0204B024, - - 0x02050024, - 0x02040010, - 0x02050026, - 0x0204003A, - 0x02050028, - 0x02040DFE, - 0x02050029, - 0x0204B024, - - 0x02050024, - 0x02040010, - 0x02050026, - 0x0204006A, - 0x02050028, - 0x0204005D, - 0x02050029, - 0x0204B024, - - 0x02050024, - 0x02040010, - 0x02050026, - 0x0204006C, - 0x02050028, - 0x02040442, - 0x02050029, - 0x0204B024, - - 0x02050024, - 0x02040010, - 0x02050026, - 0x02040005, - 0x02050028, - 0x02040880, - 0x02050029, - 0x0204B024, - - 0x02050024, - 0x02040010, - 0x02050026, - 0x02040006, - 0x02050028, - 0x02040000, - 0x02050029, - 0x0204B024, - - 0x02050024, - 0x02040010, - 0x02050026, - 0x02040008, - 0x02050028, - 0x0204B000, - 0x02050029, - 0x0204B024, - - 0x02050024, - 0x02040010, - 0x02050026, - 0x0204002E, - 0x02050028, - 0x02040800, - 0x02050029, - 0x0204B024, - - 0x02050024, - 0x02040010, - 0x02050026, - 0x0204006A, - 0x02050028, - 0x020400C3, - 0x02050029, - 0x0204B024, - - 0x02050024, - 0x02040010, - 0x02050026, - 0x0204006C, - 0x02050028, - 0x0204D4A0, - 0x02050029, - 0x0204B024, - - 0x02050024, - 0x02040010, - 0x02050026, - 0x0204006A, - 0x02050028, - 0x020400CC, - 0x02050029, - 0x0204B024, - - 0x02050024, - 0x02040010, - 0x02050026, - 0x0204006C, - 0x02050028, - 0x0204400A, - 0x02050029, - 0x0204B024, - - 0x02050024, - 0x02040010, - 0x02050026, - 0x0204006A, - 0x02050028, - 0x020400C1, - 0x02050029, - 0x0204B024, - - 0x02050024, - 0x02040010, - 0x02050026, - 0x0204006C, - 0x02050028, - 0x02040320, - 0x02050029, - 0x0204B024, - - 0x02050024, - 0x02040010, - 0x02050026, - 0x02040039, - 0x02050028, - 0x02040000, - 0x02050029, - 0x0204B024, - - 0x02050024, - 0x02040010, - 0x02050026, - 0x0204003B, - 0x02050028, - 0x0204FFFF, - 0x02050029, - 0x0204B024, - - 0x02050024, - 0x02040010, - 0x02050026, - 0x0204003C, - 0x02050028, - 0x0204FC20, - 0x02050029, - 0x0204B024, - - 0x02050024, - 0x02040010, - 0x02050026, - 0x0204003A, - 0x02050028, - 0x02041DFE, - 0x02050029, - 0x0204B024, - - 0x02050024, - 0x02040010, - 0x02050026, - 0x020400C0, - 0x02050028, - 0x020401FA, - 0x02050029, - 0x0204B024, - - 0x02050024, - 0x02040010, - 0x02050026, - 0x020400C1, - 0x02050028, - 0x0204DE23, - 0x02050029, - 0x0204B024, - - 0x02050024, - 0x02040010, - 0x02050026, - 0x020400C2, - 0x02050028, - 0x02041C00, - 0x02050029, - 0x0204B024, - - 0x02050024, - 0x02040010, - 0x02050026, - 0x020400C3, - 0x02050028, - 0x02040000, - 0x02050029, - 0x0204B024, - - 0x02050024, - 0x02040010, - 0x02050026, - 0x020400C4, - 0x02050028, - 0x02040200, - 0x02050029, - 0x0204B024, - - 0x02050024, - 0x02040010, - 0x02050026, - 0x020400C5, - 0x02050028, - 0x02040000, - 0x02050029, - 0x0204B024, - - 0x02050024, - 0x02040010, - 0x02050026, - 0x020400C6, - 0x02050028, - 0x020403F5, - 0x02050029, - 0x0204B024, - - 0x02050024, - 0x02040010, - 0x02050026, - 0x020400C7, - 0x02050028, - 0x0204AF1B, - 0x02050029, - 0x0204B024, - - 0x02050024, - 0x02040010, - 0x02050026, - 0x020400C8, - 0x02050028, - 0x02041E0A, - 0x02050029, - 0x0204B024, - - 0x02050024, - 0x02040010, - 0x02050026, - 0x020400C9, - 0x02050028, - 0x0204368E, - 0x02050029, - 0x0204B024, - - 0x02050024, - 0x02040010, - 0x02050026, - 0x020400CA, - 0x02050028, - 0x020401FA, - 0x02050029, - 0x0204B024, - - 0x02050024, - 0x02040010, - 0x02050026, - 0x020400CB, - 0x02050028, - 0x0204DE23, - 0x02050029, - 0x0204B024, - - 0x02050024, - 0x02040010, - 0x02050026, - 0x020400CC, - 0x02050028, - 0x02041C00, - 0x02050029, - 0x0204B024, - - 0x02050024, - 0x02040010, - 0x02050026, - 0x020400CD, - 0x02050028, - 0x02040000, - 0x02050029, - 0x0204B024, - - 0x02050024, - 0x02040010, - 0x02050026, - 0x020400CE, - 0x02050028, - 0x02040200, - 0x02050029, - 0x0204B024, - - 0x02050024, - 0x02040010, - 0x02050026, - 0x020400CF, - 0x02050028, - 0x02040000, - 0x02050029, - 0x0204B024, - - 0x02050024, - 0x02040010, - 0x02050026, - 0x020400D0, - 0x02050028, - 0x020403F5, - 0x02050029, - 0x0204B024, - - 0x02050024, - 0x02040010, - 0x02050026, - 0x020400D1, - 0x02050028, - 0x0204AF1B, - 0x02050029, - 0x0204B024, - - 0x02050024, - 0x02040010, - 0x02050026, - 0x020400D2, - 0x02050028, - 0x02041E0A, - 0x02050029, - 0x0204B024, - - 0x02050024, - 0x02040010, - 0x02050026, - 0x020400D3, - 0x02050028, - 0x0204368E, - 0x02050029, - 0x0204B024, - - 0x02050024, - 0x02040010, - 0x02050026, - 0x02040040, - 0x02050028, - 0x0204800F, - 0x02050029, - 0x0204B024, - - 0x02050024, - 0x02040010, - 0x02050026, - 0x02040062, - 0x02050028, - 0x02048000, - 0x02050029, - 0x0204B024, - - 0x02050024, - 0x02040010, - 0x02050026, - 0x02040063, - 0x02050028, - 0x02044848, - 0x02050029, - 0x0204B024, - - 0x02050024, - 0x02040010, - 0x02050026, - 0x02040064, - 0x02050028, - 0x02040800, - 0x02050029, - 0x0204B024, - - 0x02050024, - 0x02040010, - 0x02050026, - 0x02040065, - 0x02050028, - 0x02040000, - 0x02050029, - 0x0204B024, - - 0x02050024, - 0x02040010, - 0x02050026, - 0x02040066, - 0x02050028, - 0x02044004, - 0x02050029, - 0x0204B024, - - 0x02050024, - 0x02040010, - 0x02050026, - 0x02040067, - 0x02050028, - 0x02040802, - 0x02050029, - 0x0204B024, - - 0x02050024, - 0x02040010, - 0x02050026, - 0x02040068, - 0x02050028, - 0x0204890F, - 0x02050029, - 0x0204B024, - - 0x02050024, - 0x02040010, - 0x02050026, - 0x02040069, - 0x02050028, - 0x0204E021, - 0x02050029, - 0x0204B024, - - 0x02050024, - 0x02040010, - 0x02050026, - 0x02040070, - 0x02050028, - 0x02040000, - 0x02050029, - 0x0204B024, - - 0x02050024, - 0x02040010, - 0x02050026, - 0x02040071, - 0x02050000, - 0x02043330, - 0x02050029, - 0x0204B024, - - 0x02050024, - 0x02040010, - 0x02050026, - 0x02040072, - 0x02050000, - 0x02043333, - 0x02050029, - 0x0204B024, - - 0x02050024, - 0x02040010, - 0x02050026, - 0x02040073, - 0x02050028, - 0x02040000, - 0x02050029, - 0x0204B024, - - 0x02050024, - 0x02040010, - 0x02050026, - 0x02040074, - 0x02050028, - 0x02040000, - 0x02050029, - 0x0204B024, - - 0x02050024, - 0x02040010, - 0x02050026, - 0x02040075, - 0x02050028, - 0x02040000, - 0x02050029, - 0x0204B024, - - 0x02050024, - 0x02040010, - 0x02050026, - 0x02040076, - 0x02050028, - 0x02040000, - 0x02050029, - 0x0204B024, - - 0x02050024, - 0x02040010, - 0x02050026, - 0x02040050, - 0x02050028, - 0x020402EC, - 0x02050029, - 0x0204B024, - - 0x02050024, - 0x02040010, - 0x02050026, - 0x02040051, - 0x02050028, - 0x02044909, - 0x02050029, - 0x0204B024, - - 0x02050024, - 0x02040010, - 0x02050026, - 0x02040052, - 0x02050028, - 0x020440B0, - 0x02050029, - 0x0204B024, - - 0x02050024, - 0x02040010, - 0x02050026, - 0x02040046, - 0x02050028, - 0x0204C22E, - 0x02050029, - 0x0204B024, - - 0x02050024, - 0x02040010, - 0x02050026, - 0x02040047, - 0x02050028, - 0x02040C00, - 0x02050029, - 0x0204B024, - - 0x02050024, - 0x02040010, - 0x02050026, - 0x02040048, - 0x02050028, - 0x02040000, - 0x02050029, - 0x0204B024, - - 0x02050024, - 0x02040010, - 0x02050026, - 0x02040049, - 0x02050028, - 0x02040000, - 0x02050029, - 0x0204B024, - - 0x02050024, - 0x02040010, - 0x02050026, - 0x0204004A, - 0x02050028, - 0x02040000, - 0x02050029, - 0x0204B024, - - 0x02050024, - 0x02040010, - 0x02050026, - 0x0204004B, - 0x02050028, - 0x02041C00, - 0x02050029, - 0x0204B024, - - 0x02050024, - 0x02040010, - 0x02050026, - 0x0204006A, - 0x02050028, - 0x02040090, - 0x02050029, - 0x0204B024, - - 0x02050024, - 0x02040010, - 0x02050026, - 0x0204006C, - 0x02050028, - 0x0204721F, - 0x02050029, - 0x0204B024, - - 0x02050024, - 0x02040010, - 0x02050026, - 0x0204009E, - 0x02050028, - 0x02040001, - 0x02050029, - 0x0204B024, - - 0x02050024, - 0x02040010, - 0x02050026, - 0x02040004, - 0x02050028, - 0x02040500, - 0x02050029, - 0x0204B024 -}; - -const u32 pc_beep_verbs[] = { -}; -AZALIA_ARRAY_SIZES; -#endif From 68b6eb78d2b86d43d3d285a88a686de20751cb81 Mon Sep 17 00:00:00 2001 From: Arthur Heymans Date: Sun, 13 Oct 2019 23:26:36 +0200 Subject: [PATCH 0556/1242] soc/intel/braswell: Use common sb code for SPI lockdown configuration This removes the weakly linked function to configure the SPI lockdown. Change-Id: I1e7be41a9470b37ad954d3120a67fc4d93633113 Signed-off-by: Arthur Heymans Reviewed-on: https://review.coreboot.org/c/coreboot/+/36007 Reviewed-by: Angel Pons Reviewed-by: Frans Hendriks Reviewed-by: Nico Huber Tested-by: build bot (Jenkins) --- src/mainboard/facebook/fbg1701/w25q64.c | 47 ++---------------------- src/mainboard/google/cyan/w25q64.c | 42 ++------------------- src/mainboard/intel/strago/w25q64.c | 41 ++------------------- src/mainboard/portwell/m107/w25q64.c | 47 ++---------------------- src/soc/intel/braswell/include/soc/spi.h | 17 ++------- src/soc/intel/braswell/southcluster.c | 22 ++++------- 6 files changed, 22 insertions(+), 194 deletions(-) diff --git a/src/mainboard/facebook/fbg1701/w25q64.c b/src/mainboard/facebook/fbg1701/w25q64.c index bc908f04b3..2f131f4ec6 100644 --- a/src/mainboard/facebook/fbg1701/w25q64.c +++ b/src/mainboard/facebook/fbg1701/w25q64.c @@ -20,57 +20,16 @@ #include /* - * SPI lockdown configuration + * SPI VSCC configuration */ -#define SPI_OPMENU_0 CMD_W25_WRSR /* Write Status Register */ -#define SPI_OPTYPE_0 SPI_OPTYPE_WR_NOADDR /* Write, no address */ - -#define SPI_OPMENU_1 CMD_W25_PP /* BYPR: Byte Program */ -#define SPI_OPTYPE_1 SPI_OPTYPE_WR_ADDR /* Write, address required */ - -#define SPI_OPMENU_2 CMD_W25_READ /* Read Data */ -#define SPI_OPTYPE_2 SPI_OPTYPE_RD_ADDR /* Read, address required */ - -#define SPI_OPMENU_3 CMD_W25_RDSR /* Read Status Register */ -#define SPI_OPTYPE_3 SPI_OPTYPE_RD_NOADDR /* Read, no address */ - -#define SPI_OPMENU_4 CMD_W25_SE /* Sector Erase */ -#define SPI_OPTYPE_4 SPI_OPTYPE_WR_ADDR /* Write, address required */ - -#define SPI_OPMENU_5 CMD_W25_RDID /* Read ID */ -#define SPI_OPTYPE_5 SPI_OPTYPE_RD_NOADDR /* Read, no address */ - -#define SPI_OPMENU_6 CMD_W25_BE /* BE: Block Erase */ -#define SPI_OPTYPE_6 SPI_OPTYPE_WR_ADDR /* Write, address required */ - -#define SPI_OPMENU_7 CMD_W25_FAST_READ /* FAST: Fast Read */ -#define SPI_OPTYPE_7 SPI_OPTYPE_RD_ADDR /* Read, address required */ - -#define SPI_OPPREFIX CMD_W25_WREN /* WREN only to be inline */ - /* with flashrom */ - -#define SPI_OPTYPE ((SPI_OPTYPE_7 << 14) | (SPI_OPTYPE_6 << 12) | \ - (SPI_OPTYPE_5 << 10) | (SPI_OPTYPE_4 << 8) | \ - (SPI_OPTYPE_3 << 6) | (SPI_OPTYPE_2 << 4) | \ - (SPI_OPTYPE_1 << 2) | (SPI_OPTYPE_0 << 0)) - -#define SPI_OPMENU_UPPER ((SPI_OPMENU_7 << 24) | (SPI_OPMENU_6 << 16) | \ - (SPI_OPMENU_5 << 8) | (SPI_OPMENU_4 << 0)) - -#define SPI_OPMENU_LOWER ((SPI_OPMENU_3 << 24) | (SPI_OPMENU_2 << 16) | \ - (SPI_OPMENU_1 << 8) | (SPI_OPMENU_0 << 0)) - #define SPI_VSCC (WG_64_BYTE | EO(0x20) | BES_4_KB) -static const struct spi_config spi_config = { - .preop = CMD_W25_WREN, - .optype = SPI_OPTYPE, - .opmenu = { SPI_OPMENU_LOWER, SPI_OPMENU_UPPER }, +static const struct vscc_config spi_config = { .lvscc = SPI_VSCC, .uvscc = SPI_VSCC, }; -int mainboard_get_spi_config(struct spi_config *cfg) +int mainboard_get_spi_vscc_config(struct vscc_config *cfg) { memcpy(cfg, &spi_config, sizeof(*cfg)); diff --git a/src/mainboard/google/cyan/w25q64.c b/src/mainboard/google/cyan/w25q64.c index 861a4645f8..5eea802942 100644 --- a/src/mainboard/google/cyan/w25q64.c +++ b/src/mainboard/google/cyan/w25q64.c @@ -18,52 +18,16 @@ #include /* - * SPI lockdown configuration W25Q64FW. + * SPI VSCC configuration W25Q64FW. */ -#define SPI_OPMENU_0 0x01 /* WRSR: Write Status Register */ -#define SPI_OPTYPE_0 0x01 /* Write, no address */ - -#define SPI_OPMENU_1 0x02 /* BYPR: Byte Program */ -#define SPI_OPTYPE_1 0x03 /* Write, address required */ - -#define SPI_OPMENU_2 0x03 /* READ: Read Data */ -#define SPI_OPTYPE_2 0x02 /* Read, address required */ - -#define SPI_OPMENU_3 0x05 /* RDSR: Read Status Register */ -#define SPI_OPTYPE_3 0x00 /* Read, no address */ - -#define SPI_OPMENU_4 0x20 /* SE20: Sector Erase 0x20 */ -#define SPI_OPTYPE_4 0x03 /* Write, address required */ - -#define SPI_OPMENU_5 0x9f /* RDID: Read ID */ -#define SPI_OPTYPE_5 0x00 /* Read, no address */ - -#define SPI_OPMENU_6 0xd8 /* BED8: Block Erase 0xd8 */ -#define SPI_OPTYPE_6 0x03 /* Write, address required */ - -#define SPI_OPMENU_7 0x0b /* FAST: Fast Read */ -#define SPI_OPTYPE_7 0x02 /* Read, address required */ - -#define SPI_OPPREFIX ((0x50 << 8) | 0x06) /* EWSR and WREN */ -#define SPI_OPTYPE ((SPI_OPTYPE_7 << 14) | (SPI_OPTYPE_6 << 12) | \ - (SPI_OPTYPE_5 << 10) | (SPI_OPTYPE_4 << 8) | \ - (SPI_OPTYPE_3 << 6) | (SPI_OPTYPE_2 << 4) | \ - (SPI_OPTYPE_1 << 2) | (SPI_OPTYPE_0 << 0)) -#define SPI_OPMENU_UPPER ((SPI_OPMENU_7 << 24) | (SPI_OPMENU_6 << 16) | \ - (SPI_OPMENU_5 << 8) | (SPI_OPMENU_4 << 0)) -#define SPI_OPMENU_LOWER ((SPI_OPMENU_3 << 24) | (SPI_OPMENU_2 << 16) | \ - (SPI_OPMENU_1 << 8) | (SPI_OPMENU_0 << 0)) #define SPI_VSCC (WG_64_BYTE | EO(0x20) | BES_4_KB) -static const struct spi_config spi_config = { - .preop = SPI_OPPREFIX, - .optype = SPI_OPTYPE, - .opmenu = { SPI_OPMENU_LOWER, SPI_OPMENU_UPPER }, +static const struct vscc_config spi_config = { .lvscc = SPI_VSCC, .uvscc = SPI_VSCC, }; -int mainboard_get_spi_config(struct spi_config *cfg) +int mainboard_get_spi_vscc_config(struct vscc_config *cfg) { memcpy(cfg, &spi_config, sizeof(*cfg)); diff --git a/src/mainboard/intel/strago/w25q64.c b/src/mainboard/intel/strago/w25q64.c index 861a4645f8..5598de48a1 100644 --- a/src/mainboard/intel/strago/w25q64.c +++ b/src/mainboard/intel/strago/w25q64.c @@ -18,52 +18,17 @@ #include /* - * SPI lockdown configuration W25Q64FW. + * SPI VSCC configuration W25Q64FW. */ -#define SPI_OPMENU_0 0x01 /* WRSR: Write Status Register */ -#define SPI_OPTYPE_0 0x01 /* Write, no address */ -#define SPI_OPMENU_1 0x02 /* BYPR: Byte Program */ -#define SPI_OPTYPE_1 0x03 /* Write, address required */ - -#define SPI_OPMENU_2 0x03 /* READ: Read Data */ -#define SPI_OPTYPE_2 0x02 /* Read, address required */ - -#define SPI_OPMENU_3 0x05 /* RDSR: Read Status Register */ -#define SPI_OPTYPE_3 0x00 /* Read, no address */ - -#define SPI_OPMENU_4 0x20 /* SE20: Sector Erase 0x20 */ -#define SPI_OPTYPE_4 0x03 /* Write, address required */ - -#define SPI_OPMENU_5 0x9f /* RDID: Read ID */ -#define SPI_OPTYPE_5 0x00 /* Read, no address */ - -#define SPI_OPMENU_6 0xd8 /* BED8: Block Erase 0xd8 */ -#define SPI_OPTYPE_6 0x03 /* Write, address required */ - -#define SPI_OPMENU_7 0x0b /* FAST: Fast Read */ -#define SPI_OPTYPE_7 0x02 /* Read, address required */ - -#define SPI_OPPREFIX ((0x50 << 8) | 0x06) /* EWSR and WREN */ -#define SPI_OPTYPE ((SPI_OPTYPE_7 << 14) | (SPI_OPTYPE_6 << 12) | \ - (SPI_OPTYPE_5 << 10) | (SPI_OPTYPE_4 << 8) | \ - (SPI_OPTYPE_3 << 6) | (SPI_OPTYPE_2 << 4) | \ - (SPI_OPTYPE_1 << 2) | (SPI_OPTYPE_0 << 0)) -#define SPI_OPMENU_UPPER ((SPI_OPMENU_7 << 24) | (SPI_OPMENU_6 << 16) | \ - (SPI_OPMENU_5 << 8) | (SPI_OPMENU_4 << 0)) -#define SPI_OPMENU_LOWER ((SPI_OPMENU_3 << 24) | (SPI_OPMENU_2 << 16) | \ - (SPI_OPMENU_1 << 8) | (SPI_OPMENU_0 << 0)) #define SPI_VSCC (WG_64_BYTE | EO(0x20) | BES_4_KB) -static const struct spi_config spi_config = { - .preop = SPI_OPPREFIX, - .optype = SPI_OPTYPE, - .opmenu = { SPI_OPMENU_LOWER, SPI_OPMENU_UPPER }, +static const struct vscc_config spi_config = { .lvscc = SPI_VSCC, .uvscc = SPI_VSCC, }; -int mainboard_get_spi_config(struct spi_config *cfg) +int mainboard_get_spi_vscc_config(struct vscc_config *cfg) { memcpy(cfg, &spi_config, sizeof(*cfg)); diff --git a/src/mainboard/portwell/m107/w25q64.c b/src/mainboard/portwell/m107/w25q64.c index bc908f04b3..2f131f4ec6 100644 --- a/src/mainboard/portwell/m107/w25q64.c +++ b/src/mainboard/portwell/m107/w25q64.c @@ -20,57 +20,16 @@ #include /* - * SPI lockdown configuration + * SPI VSCC configuration */ -#define SPI_OPMENU_0 CMD_W25_WRSR /* Write Status Register */ -#define SPI_OPTYPE_0 SPI_OPTYPE_WR_NOADDR /* Write, no address */ - -#define SPI_OPMENU_1 CMD_W25_PP /* BYPR: Byte Program */ -#define SPI_OPTYPE_1 SPI_OPTYPE_WR_ADDR /* Write, address required */ - -#define SPI_OPMENU_2 CMD_W25_READ /* Read Data */ -#define SPI_OPTYPE_2 SPI_OPTYPE_RD_ADDR /* Read, address required */ - -#define SPI_OPMENU_3 CMD_W25_RDSR /* Read Status Register */ -#define SPI_OPTYPE_3 SPI_OPTYPE_RD_NOADDR /* Read, no address */ - -#define SPI_OPMENU_4 CMD_W25_SE /* Sector Erase */ -#define SPI_OPTYPE_4 SPI_OPTYPE_WR_ADDR /* Write, address required */ - -#define SPI_OPMENU_5 CMD_W25_RDID /* Read ID */ -#define SPI_OPTYPE_5 SPI_OPTYPE_RD_NOADDR /* Read, no address */ - -#define SPI_OPMENU_6 CMD_W25_BE /* BE: Block Erase */ -#define SPI_OPTYPE_6 SPI_OPTYPE_WR_ADDR /* Write, address required */ - -#define SPI_OPMENU_7 CMD_W25_FAST_READ /* FAST: Fast Read */ -#define SPI_OPTYPE_7 SPI_OPTYPE_RD_ADDR /* Read, address required */ - -#define SPI_OPPREFIX CMD_W25_WREN /* WREN only to be inline */ - /* with flashrom */ - -#define SPI_OPTYPE ((SPI_OPTYPE_7 << 14) | (SPI_OPTYPE_6 << 12) | \ - (SPI_OPTYPE_5 << 10) | (SPI_OPTYPE_4 << 8) | \ - (SPI_OPTYPE_3 << 6) | (SPI_OPTYPE_2 << 4) | \ - (SPI_OPTYPE_1 << 2) | (SPI_OPTYPE_0 << 0)) - -#define SPI_OPMENU_UPPER ((SPI_OPMENU_7 << 24) | (SPI_OPMENU_6 << 16) | \ - (SPI_OPMENU_5 << 8) | (SPI_OPMENU_4 << 0)) - -#define SPI_OPMENU_LOWER ((SPI_OPMENU_3 << 24) | (SPI_OPMENU_2 << 16) | \ - (SPI_OPMENU_1 << 8) | (SPI_OPMENU_0 << 0)) - #define SPI_VSCC (WG_64_BYTE | EO(0x20) | BES_4_KB) -static const struct spi_config spi_config = { - .preop = CMD_W25_WREN, - .optype = SPI_OPTYPE, - .opmenu = { SPI_OPMENU_LOWER, SPI_OPMENU_UPPER }, +static const struct vscc_config spi_config = { .lvscc = SPI_VSCC, .uvscc = SPI_VSCC, }; -int mainboard_get_spi_config(struct spi_config *cfg) +int mainboard_get_spi_vscc_config(struct vscc_config *cfg) { memcpy(cfg, &spi_config, sizeof(*cfg)); diff --git a/src/soc/intel/braswell/include/soc/spi.h b/src/soc/intel/braswell/include/soc/spi.h index 47de9da55b..0234021e65 100644 --- a/src/soc/intel/braswell/include/soc/spi.h +++ b/src/soc/intel/braswell/include/soc/spi.h @@ -23,14 +23,6 @@ /* These registers live behind SPI_BASE_ADDRESS. */ #define HSFSTS 0x04 # define FLOCKDN (0x1 << 15) -#define PREOP 0x94 -#define OPTYPE 0x96 -# define SPI_OPTYPE_RD_NOADDR 0x00 /* Read, no address */ -# define SPI_OPTYPE_WR_NOADDR 0x01 /* Write, no address */ -# define SPI_OPTYPE_RD_ADDR 0x02 /* Read, address required */ -# define SPI_OPTYPE_WR_ADDR 0x03 /* Write, address required */ -#define OPMENU0 0x98 -#define OPMENU1 0x9c #define LVSCC 0xc4 # define VCL (0x1 << 23) # define EO(x) (((x) & 0xff) << 8) @@ -53,17 +45,14 @@ # define BCR_WPD (0x1 << 0) /* - * SPI lockdown configuration. + * SPI VSCC configuration. */ -struct spi_config { - uint16_t preop; - uint16_t optype; - uint32_t opmenu[2]; +struct vscc_config { uint32_t lvscc; uint32_t uvscc; }; /* Return 0 on success < 0 on failure. */ -int mainboard_get_spi_config(struct spi_config *cfg); +int mainboard_get_spi_vscc_config(struct vscc_config *cfg); #endif /* _SOC_SPI_H_ */ diff --git a/src/soc/intel/braswell/southcluster.c b/src/soc/intel/braswell/southcluster.c index c233dc8172..8b13fd0e82 100644 --- a/src/soc/intel/braswell/southcluster.c +++ b/src/soc/intel/braswell/southcluster.c @@ -42,6 +42,7 @@ #include #include #include +#include static void sc_set_serial_irqs_mode(struct device *dev, enum serirq_mode mode) { @@ -608,13 +609,6 @@ static const struct pci_driver southcluster __pci_driver = { .device = LPC_DEVID, }; -int __weak mainboard_get_spi_config(struct spi_config *cfg) -{ - printk(BIOS_SPEW, "%s/%s (0x%p)\n", - __FILE__, __func__, (void *)cfg); - return -1; -} - static void finalize_chipset(void *unused) { void *bcr = (void *)(SPI_BASE_ADDRESS + BCR); @@ -622,7 +616,7 @@ static void finalize_chipset(void *unused) void *gen_pmcon2 = (void *)(PMC_BASE_ADDRESS + GEN_PMCON2); void *etr = (void *)(PMC_BASE_ADDRESS + ETR); uint8_t *spi = (uint8_t *)SPI_BASE_ADDRESS; - struct spi_config cfg; + struct vscc_config cfg; printk(BIOS_SPEW, "%s/%s (0x%p)\n", __FILE__, __func__, unused); @@ -639,14 +633,12 @@ static void finalize_chipset(void *unused) /* Set the CF9 lock. */ write32(etr, read32(etr) | CF9LOCK); - if (mainboard_get_spi_config(&cfg) < 0) { - printk(BIOS_DEBUG, "No SPI lockdown configuration.\n"); + spi_finalize_ops(); + write16(spi + HSFSTS, read16(spi + HSFSTS) | FLOCKDN); + + if (mainboard_get_spi_vscc_config(&cfg) < 0) { + printk(BIOS_DEBUG, "No SPI VSCC configuration.\n"); } else { - write16(spi + PREOP, cfg.preop); - write16(spi + OPTYPE, cfg.optype); - write32(spi + OPMENU0, cfg.opmenu[0]); - write32(spi + OPMENU1, cfg.opmenu[1]); - write16(spi + HSFSTS, read16(spi + HSFSTS) | FLOCKDN); write32(spi + UVSCC, cfg.uvscc); write32(spi + LVSCC, cfg.lvscc | VCL); } From b9d5b264584affa666adaa0e364e99f86361fd16 Mon Sep 17 00:00:00 2001 From: Patrick Georgi Date: Thu, 5 Dec 2019 19:56:53 +0100 Subject: [PATCH 0557/1242] soc/qualcomm/sc7180: Adapt to recent API changes MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Definitions were moved so that now device/mmio.h needs to be included instead of arch/mmio.h. Also, don't use le32 conversion. This follows the activities of commit 55009af42 (Change all clrsetbits_leXX() to clrsetbitsXX()) and commit 1c371572188 (mmio: Add clrsetbitsXX() API in place of updateX()). Change-Id: Ie3af0d4f0b3331fe5572fc56915952547b512db7 Signed-off-by: Patrick Georgi Reviewed-on: https://review.coreboot.org/c/coreboot/+/37534 Reviewed-by: Julius Werner Reviewed-by: Kyösti Mälkki Reviewed-by: Stefan Reinauer Tested-by: build bot (Jenkins) --- src/soc/qualcomm/sc7180/clock.c | 18 +++++++++--------- src/soc/qualcomm/sc7180/usb.c | 16 ++++++++-------- 2 files changed, 17 insertions(+), 17 deletions(-) diff --git a/src/soc/qualcomm/sc7180/clock.c b/src/soc/qualcomm/sc7180/clock.c index 97b7b280ca..9092a4e185 100644 --- a/src/soc/qualcomm/sc7180/clock.c +++ b/src/soc/qualcomm/sc7180/clock.c @@ -62,10 +62,10 @@ struct clock_config qspi_core_cfg[] = { static int clock_configure_gpll0(void) { - setbits_le32(&gcc->gpll0.user_ctl_u, 1 << SCALE_FREQ_SHFT); + setbits32(&gcc->gpll0.user_ctl_u, 1 << SCALE_FREQ_SHFT); /* Keep existing GPLL0 configuration, in RUN mode @600Mhz. */ - setbits_le32(&gcc->gpll0.user_ctl, + setbits32(&gcc->gpll0.user_ctl, 1 << CLK_CTL_GPLL_PLLOUT_EVEN_SHFT | 1 << CLK_CTL_GPLL_PLLOUT_MAIN_SHFT | 1 << CLK_CTL_GPLL_PLLOUT_ODD_SHFT); @@ -77,7 +77,7 @@ static int clock_configure_mnd(struct sc7180_clock *clk, uint32_t m, uint32_t n, uint32_t d_2) { struct sc7180_mnd_clock *mnd = (struct sc7180_mnd_clock *)clk; - setbits_le32(&clk->rcg_cfg, + setbits32(&clk->rcg_cfg, RCG_MODE_DUAL_EDGE << CLK_CTL_CFG_MODE_SHFT); write32(&mnd->m, m & CLK_CTL_RCG_MND_BMSK); @@ -111,7 +111,7 @@ static int clock_configure(struct sc7180_clock *clk, clk_cfg[idx].d_2); /* Commit config to RCG*/ - setbits_le32(&clk->rcg_cmd, BIT(CLK_CTL_CMD_UPDATE_SHFT)); + setbits32(&clk->rcg_cmd, BIT(CLK_CTL_CMD_UPDATE_SHFT)); return 0; } @@ -125,7 +125,7 @@ static int clock_enable_vote(void *cbcr_addr, void *vote_addr, uint32_t vote_bit) { /* Set clock vote bit */ - setbits_le32(vote_addr, BIT(vote_bit)); + setbits32(vote_addr, BIT(vote_bit)); /* Ensure clock is enabled */ while (clock_is_off(cbcr_addr)) @@ -137,7 +137,7 @@ static int clock_enable_vote(void *cbcr_addr, void *vote_addr, static int clock_enable(void *cbcr_addr) { /* Set clock enable bit */ - setbits_le32(cbcr_addr, BIT(CLK_CTL_CBC_CLK_EN_SHFT)); + setbits32(cbcr_addr, BIT(CLK_CTL_CBC_CLK_EN_SHFT)); /* Ensure clock is enabled */ while (clock_is_off(cbcr_addr)) @@ -149,7 +149,7 @@ static int clock_enable(void *cbcr_addr) void clock_reset_aop(void) { /* Bring AOP out of RESET */ - clrbits_le32(&aoss->aoss_cc_apcs_misc, BIT(AOP_RESET_SHFT)); + clrbits32(&aoss->aoss_cc_apcs_misc, BIT(AOP_RESET_SHFT)); } void clock_configure_qspi(uint32_t hz) @@ -166,9 +166,9 @@ int clock_reset_bcr(void *bcr_addr, bool reset) struct sc7180_bcr *bcr = bcr_addr; if (reset) - setbits_le32(bcr, BIT(CLK_CTL_BCR_BLK_ARES_SHFT)); + setbits32(bcr, BIT(CLK_CTL_BCR_BLK_ARES_SHFT)); else - clrbits_le32(bcr, BIT(CLK_CTL_BCR_BLK_ARES_SHFT)); + clrbits32(bcr, BIT(CLK_CTL_BCR_BLK_ARES_SHFT)); return 0; } diff --git a/src/soc/qualcomm/sc7180/usb.c b/src/soc/qualcomm/sc7180/usb.c index 4183e9b97d..639f40136e 100644 --- a/src/soc/qualcomm/sc7180/usb.c +++ b/src/soc/qualcomm/sc7180/usb.c @@ -13,10 +13,10 @@ * GNU General Public License for more details. */ -#include #include #include #include +#include #include #include #include @@ -565,7 +565,7 @@ static void qusb2_phy_set_tune_param(struct usb_dwc3_cfg *dwc3) * tune parameters. */ if (tune_val) - clrsetbits_le32(&dwc3->qusb_phy_dig->tune1, + clrsetbits32(&dwc3->qusb_phy_dig->tune1, PORT_TUNE1_MASK, tune_val << 4); } @@ -602,7 +602,7 @@ static void tune_phy(struct usb_dwc3_cfg *dwc3, struct usb_qusb_phy_dig *phy) static void hs_qusb_phy_init(struct usb_dwc3_cfg *dwc3) { /* PWR_CTRL: set the power down bit to disable the PHY */ - setbits_le32(&dwc3->qusb_phy_dig->pwr_ctrl1, POWER_DOWN); + setbits32(&dwc3->qusb_phy_dig->pwr_ctrl1, POWER_DOWN); write32(&dwc3->qusb_phy_pll->analog_controls_two, QUSB2PHY_PLL_ANALOG_CONTROLS_TWO); @@ -622,7 +622,7 @@ static void hs_qusb_phy_init(struct usb_dwc3_cfg *dwc3) tune_phy(dwc3, dwc3->qusb_phy_dig); /* PWR_CTRL1: Clear the power down bit to enable the PHY */ - clrbits_le32(&dwc3->qusb_phy_dig->pwr_ctrl1, POWER_DOWN); + clrbits32(&dwc3->qusb_phy_dig->pwr_ctrl1, POWER_DOWN); write32(&dwc3->qusb_phy_dig->debug_ctrl2, DEBUG_CTRL2_MUX_PLL_LOCK_STATUS); @@ -688,7 +688,7 @@ static void ss_qmp_phy_init(struct usb_dwc3_cfg *dwc3) static void setup_dwc3(struct usb_dwc3 *dwc3) { /* core exits U1/U2/U3 only in PHY power state P1/P2/P3 respectively */ - clrsetbits_le32(&dwc3->usb3pipectl, + clrsetbits32(&dwc3->usb3pipectl, DWC3_GUSB3PIPECTL_DELAYP1TRANS, DWC3_GUSB3PIPECTL_UX_EXIT_IN_PX); @@ -698,18 +698,18 @@ static void setup_dwc3(struct usb_dwc3 *dwc3) * 2. Set USBTRDTIM to the corresponding value * according to the UTMI+ PHY interface. */ - clrsetbits_le32(&dwc3->usb2phycfg, + clrsetbits32(&dwc3->usb2phycfg, (DWC3_GUSB2PHYCFG_USB2TRDTIM_MASK | DWC3_GUSB2PHYCFG_PHYIF_MASK), (DWC3_GUSB2PHYCFG_PHYIF(UTMI_PHYIF_8_BIT) | DWC3_GUSB2PHYCFG_USBTRDTIM(USBTRDTIM_UTMI_8_BIT))); - clrsetbits_le32(&dwc3->ctl, (DWC3_GCTL_SCALEDOWN_MASK | + clrsetbits32(&dwc3->ctl, (DWC3_GCTL_SCALEDOWN_MASK | DWC3_GCTL_DISSCRAMBLE), DWC3_GCTL_U2EXIT_LFPS | DWC3_GCTL_DSBLCLKGTNG); /* configure controller in Host mode */ - clrsetbits_le32(&dwc3->ctl, (DWC3_GCTL_PRTCAPDIR(DWC3_GCTL_PRTCAP_OTG)), + clrsetbits32(&dwc3->ctl, (DWC3_GCTL_PRTCAPDIR(DWC3_GCTL_PRTCAP_OTG)), DWC3_GCTL_PRTCAPDIR(DWC3_GCTL_PRTCAP_HOST)); printk(BIOS_SPEW, "Configure USB in Host mode\n"); } From 344b331783a3c315ed6d34cbe980cd08c12e3574 Mon Sep 17 00:00:00 2001 From: Gaggery Tsai Date: Mon, 11 Nov 2019 08:36:10 -0800 Subject: [PATCH 0558/1242] mb/intel/coffeelake_rvp: Switch to overridetree setup This patch moves the common devicetree settings into baseboard and creates overridetree.cb for each variant. For PCIe root port settings, SATA, eMMC, I2Cs and GBe, they are in overridetree. TEST=build an image for each variant Change-Id: I067bdb3fcf1218b93e52801f6db093e24d7d2b62 Signed-off-by: Gaggery Tsai Reviewed-on: https://review.coreboot.org/c/coreboot/+/36794 Reviewed-by: Angel Pons Tested-by: build bot (Jenkins) --- src/mainboard/intel/coffeelake_rvp/Kconfig | 6 +- .../{whl_u => baseboard}/devicetree.cb | 74 +------------- .../cfl_h/{devicetree.cb => overridetree.cb} | 78 +++++---------- .../cfl_s/{devicetree.cb => overridetree.cb} | 66 ++++--------- .../cfl_u/{devicetree.cb => overridetree.cb} | 73 +++----------- .../cml_u/{devicetree.cb => overridetree.cb} | 78 +++------------ .../variants/whl_u/overridetree.cb | 97 +++++++++++++++++++ 7 files changed, 171 insertions(+), 301 deletions(-) rename src/mainboard/intel/coffeelake_rvp/variants/{whl_u => baseboard}/devicetree.cb (52%) rename src/mainboard/intel/coffeelake_rvp/variants/cfl_h/{devicetree.cb => overridetree.cb} (64%) rename src/mainboard/intel/coffeelake_rvp/variants/cfl_s/{devicetree.cb => overridetree.cb} (69%) rename src/mainboard/intel/coffeelake_rvp/variants/cfl_u/{devicetree.cb => overridetree.cb} (54%) rename src/mainboard/intel/coffeelake_rvp/variants/cml_u/{devicetree.cb => overridetree.cb} (55%) create mode 100644 src/mainboard/intel/coffeelake_rvp/variants/whl_u/overridetree.cb diff --git a/src/mainboard/intel/coffeelake_rvp/Kconfig b/src/mainboard/intel/coffeelake_rvp/Kconfig index 72906d7d3e..da2cd2eb3d 100644 --- a/src/mainboard/intel/coffeelake_rvp/Kconfig +++ b/src/mainboard/intel/coffeelake_rvp/Kconfig @@ -59,7 +59,11 @@ config UART_FOR_CONSOLE config DEVICETREE string - default "variants/$(CONFIG_VARIANT_DIR)/devicetree.cb" + default "variants/baseboard/devicetree.cb" + +config OVERRIDE_DEVICETREE + string + default "variants/$(CONFIG_VARIANT_DIR)/overridetree.cb" config FMDFILE string diff --git a/src/mainboard/intel/coffeelake_rvp/variants/whl_u/devicetree.cb b/src/mainboard/intel/coffeelake_rvp/variants/baseboard/devicetree.cb similarity index 52% rename from src/mainboard/intel/coffeelake_rvp/variants/whl_u/devicetree.cb rename to src/mainboard/intel/coffeelake_rvp/variants/baseboard/devicetree.cb index 429d5daca8..01d970ca56 100644 --- a/src/mainboard/intel/coffeelake_rvp/variants/whl_u/devicetree.cb +++ b/src/mainboard/intel/coffeelake_rvp/variants/baseboard/devicetree.cb @@ -7,20 +7,9 @@ chip soc/intel/cannonlake # FSP configuration register "SaGv" = "SaGv_Enabled" register "ScsEmmcHs400Enabled" = "1" - register "HeciEnabled" = "1" - # Enable eDP device - register "DdiPortEdp" = "1" - # Enable HPD for DDI ports B/C/D/F - register "DdiPortBHpd" = "1" - register "DdiPortCHpd" = "1" - register "DdiPortDHpd" = "1" - register "DdiPortFHpd" = "1" - # Enable DDC for DDI ports B/C/D/F - register "DdiPortBDdc" = "1" - register "DdiPortCDdc" = "1" - register "DdiPortDDdc" = "1" - register "DdiPortFDdc" = "1" + # HECI + register "HeciEnabled" = "1" register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC0)" register "usb2_ports[1]" = "USB2_PORT_MID(OC0)" @@ -40,36 +29,9 @@ chip soc/intel/cannonlake register "usb3_ports[4]" = "USB3_PORT_DEFAULT(OC0)" register "usb3_ports[5]" = "USB3_PORT_DEFAULT(OC0)" - register "SataSalpSupport" = "1" - register "SataPortsEnable[0]" = "1" - register "SataPortsEnable[1]" = "1" - register "SataPortsEnable[2]" = "1" - register "SataPortsEnable[3]" = "1" - register "SataPortsEnable[4]" = "1" - register "SataPortsEnable[5]" = "1" - register "SataPortsEnable[6]" = "1" - register "SataPortsEnable[7]" = "1" - register "PchHdaDspEnable" = "1" register "PchHdaAudioLinkHda" = "1" - register "PcieRpEnable[0]" = "1" - register "PcieRpEnable[1]" = "1" - register "PcieRpEnable[2]" = "1" - register "PcieRpEnable[3]" = "1" - register "PcieRpEnable[4]" = "1" - register "PcieRpEnable[5]" = "1" - register "PcieRpEnable[6]" = "1" - register "PcieRpEnable[7]" = "1" - register "PcieRpEnable[8]" = "1" - register "PcieRpEnable[9]" = "1" - register "PcieRpEnable[10]" = "1" - register "PcieRpEnable[11]" = "1" - register "PcieRpEnable[12]" = "1" - register "PcieRpEnable[13]" = "1" - register "PcieRpEnable[14]" = "1" - register "PcieRpEnable[15]" = "1" - register "PcieClkSrcUsage[0]" = "1" register "PcieClkSrcUsage[1]" = "8" register "PcieClkSrcUsage[2]" = "PCIE_CLK_LAN" @@ -87,8 +49,8 @@ chip soc/intel/cannonlake # Enable "Intel Speed Shift Technology" register "speed_shift_enable" = "1" - # GPIO for SD card detect - register "sdcard_cd_gpio" = "GPP_G5" + # Disable S0ix + register "s0ix_enable" = "0" device domain 0 on device pci 00.0 on end # Host Bridge @@ -99,41 +61,14 @@ chip soc/intel/cannonlake device pci 12.6 off end # GSPI #2 device pci 14.0 on end # USB xHCI device pci 14.1 off end # USB xDCI (OTG) - chip drivers/intel/wifi - register "wake" = "PME_B0_EN_BIT" - device pci 14.3 on end # CNVi wifi - end device pci 14.5 on end # SDCard - device pci 15.0 on end # I2C #0 - device pci 15.1 on end # I2C #1 - device pci 15.2 off end # I2C #2 - device pci 15.3 off end # I2C #3 device pci 16.0 on end # Management Engine Interface 1 device pci 16.1 off end # Management Engine Interface 2 device pci 16.2 off end # Management Engine IDE-R device pci 16.3 off end # Management Engine KT Redirection device pci 16.4 off end # Management Engine Interface 3 device pci 16.5 off end # Management Engine Interface 4 - device pci 17.0 on end # SATA - device pci 19.0 on end # I2C #4 - device pci 19.1 off end # I2C #5 - device pci 19.2 on end # UART #2 - device pci 1a.0 on end # eMMC - device pci 1c.0 on end # PCI Express Port 1 x4 SLOT1 - device pci 1c.4 on end # PCI Express Port 5 x1 SLOT2/LAN - device pci 1c.5 off end # PCI Express Port 6 - device pci 1c.6 off end # PCI Express Port 7 - device pci 1c.7 off end # PCI Express Port 8 - device pci 1d.0 on end # PCI Express Port 9 - device pci 1d.1 off end # PCI Express Port 10 - device pci 1d.2 off end # PCI Express Port 11 - device pci 1d.3 off end # PCI Express Port 12 - device pci 1d.4 off end # PCI Express Port 13 - device pci 1d.5 off end # PCI Express Port 14 - device pci 1d.6 off end # PCI Express Port 15 - device pci 1d.7 off end # PCI Express Port 16 device pci 1e.0 on end # UART #0 - device pci 1e.1 off end # UART #1 device pci 1e.2 off end # GSPI #0 device pci 1e.3 off end # GSPI #1 device pci 1f.0 on @@ -146,6 +81,5 @@ chip soc/intel/cannonlake device pci 1f.3 on end # Intel HDA device pci 1f.4 on end # SMBus device pci 1f.5 on end # PCH SPI - device pci 1f.6 on end # GbE end end diff --git a/src/mainboard/intel/coffeelake_rvp/variants/cfl_h/devicetree.cb b/src/mainboard/intel/coffeelake_rvp/variants/cfl_h/overridetree.cb similarity index 64% rename from src/mainboard/intel/coffeelake_rvp/variants/cfl_h/devicetree.cb rename to src/mainboard/intel/coffeelake_rvp/variants/cfl_h/overridetree.cb index 9648ac345b..989b5cd4ea 100644 --- a/src/mainboard/intel/coffeelake_rvp/variants/cfl_h/devicetree.cb +++ b/src/mainboard/intel/coffeelake_rvp/variants/cfl_h/overridetree.cb @@ -5,9 +5,7 @@ chip soc/intel/cannonlake end # FSP configuration - register "SaGv" = "SaGv_Enabled" register "RMT" = "1" - register "ScsEmmcHs400Enabled" = "1" register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC5)" register "usb2_ports[1]" = "USB2_PORT_MID(OC6)" @@ -53,25 +51,25 @@ chip soc/intel/cannonlake register "PcieRpEnable[2]" = "1" register "PcieRpEnable[3]" = "1" register "PcieRpEnable[4]" = "1" - register "PcieRpEnable[5]" = "1" - register "PcieRpEnable[6]" = "1" - register "PcieRpEnable[7]" = "1" + register "PcieRpEnable[5]" = "0" + register "PcieRpEnable[6]" = "0" + register "PcieRpEnable[7]" = "0" register "PcieRpEnable[8]" = "1" register "PcieRpEnable[9]" = "1" register "PcieRpEnable[10]" = "1" register "PcieRpEnable[11]" = "1" - register "PcieRpEnable[12]" = "1" - register "PcieRpEnable[13]" = "1" - register "PcieRpEnable[14]" = "1" - register "PcieRpEnable[15]" = "1" - register "PcieRpEnable[16]" = "1" - register "PcieRpEnable[17]" = "1" - register "PcieRpEnable[18]" = "1" - register "PcieRpEnable[19]" = "1" - register "PcieRpEnable[20]" = "1" - register "PcieRpEnable[21]" = "1" - register "PcieRpEnable[22]" = "1" - register "PcieRpEnable[23]" = "1" + register "PcieRpEnable[12]" = "0" + register "PcieRpEnable[13]" = "0" + register "PcieRpEnable[14]" = "0" + register "PcieRpEnable[15]" = "0" + register "PcieRpEnable[16]" = "0" + register "PcieRpEnable[17]" = "0" + register "PcieRpEnable[18]" = "0" + register "PcieRpEnable[19]" = "0" + register "PcieRpEnable[20]" = "0" + register "PcieRpEnable[21]" = "0" + register "PcieRpEnable[22]" = "0" + register "PcieRpEnable[23]" = "0" register "PcieClkSrcUsage[0]" = "1" register "PcieClkSrcUsage[1]" = "8" @@ -91,34 +89,14 @@ chip soc/intel/cannonlake register "PcieClkSrcClkReq[8]" = "8" register "PcieClkSrcClkReq[9]" = "9" - # Enable "Intel Speed Shift Technology" - register "speed_shift_enable" = "1" - - # HECI - register "HeciEnabled" = "1" - device domain 0 on - device pci 00.0 on end # Host Bridge - device pci 02.0 on end # Integrated Graphics Device - device pci 04.0 on end # SA Thermal device - device pci 12.0 on end # Thermal Subsystem - device pci 12.5 off end # UFS SCS - device pci 12.6 off end # GSPI #2 - device pci 14.0 on end # USB xHCI - device pci 14.1 off end # USB xDCI (OTG) - device pci 14.5 on end # SDCard device pci 15.0 on end # I2C #0 device pci 15.1 on end # I2C #1 device pci 15.2 off end # I2C #2 device pci 15.3 off end # I2C #3 - device pci 16.0 on end # Management Engine Interface 1 - device pci 16.1 off end # Management Engine Interface 2 - device pci 16.2 off end # Management Engine IDE-R - device pci 16.3 off end # Management Engine KT Redirection - device pci 16.4 off end # Management Engine Interface 3 - device pci 16.5 off end # Management Engine Interface 4 device pci 17.0 on end # SATA - device pci 19.0 off end # I2C #4 + device pci 19.0 off end # I2C #4 (Not available on PCH-H) + device pci 19.1 off end # I2C #5 (Not available on PCH-H) device pci 19.2 on end # UART #2 device pci 1a.0 on end # eMMC device pci 1c.0 on end # PCI Express Port 1 x4 SLOT1 @@ -127,27 +105,21 @@ chip soc/intel/cannonlake device pci 1c.6 off end # PCI Express Port 7 device pci 1c.7 off end # PCI Express Port 8 device pci 1d.0 on end # PCI Express Port 9 - device pci 1d.1 off end # PCI Express Port 10 - device pci 1d.2 off end # PCI Express Port 11 - device pci 1d.3 off end # PCI Express Port 12 device pci 1d.4 off end # PCI Express Port 13 device pci 1d.5 off end # PCI Express Port 14 device pci 1d.6 off end # PCI Express Port 15 device pci 1d.7 off end # PCI Express Port 16 - device pci 1e.0 on end # UART #0 + device pci 1b.0 off end # PCI Express Port 17 + device pci 1b.1 off end # PCI Express Port 18 + device pci 1b.2 off end # PCI Express Port 19 + device pci 1b.3 off end # PCI Express Port 20 + device pci 1b.4 off end # PCI Express Port 21 + device pci 1b.5 off end # PCI Express Port 22 + device pci 1b.6 off end # PCI Express Port 23 + device pci 1b.7 off end # PCI Express Port 24 device pci 1e.1 off end # UART #1 device pci 1e.2 off end # GSPI #0 device pci 1e.3 off end # GSPI #1 - device pci 1f.0 on - chip drivers/pc80/tpm - device pnp 0c31.0 on end - end - end # LPC Interface - device pci 1f.1 on end # P2SB - device pci 1f.2 on end # Power Management Controller - device pci 1f.3 on end # Intel HDA - device pci 1f.4 on end # SMBus - device pci 1f.5 on end # PCH SPI device pci 1f.6 on end # GbE end end diff --git a/src/mainboard/intel/coffeelake_rvp/variants/cfl_s/devicetree.cb b/src/mainboard/intel/coffeelake_rvp/variants/cfl_s/overridetree.cb similarity index 69% rename from src/mainboard/intel/coffeelake_rvp/variants/cfl_s/devicetree.cb rename to src/mainboard/intel/coffeelake_rvp/variants/cfl_s/overridetree.cb index 126cab01f0..a63d4c0364 100644 --- a/src/mainboard/intel/coffeelake_rvp/variants/cfl_s/devicetree.cb +++ b/src/mainboard/intel/coffeelake_rvp/variants/cfl_s/overridetree.cb @@ -5,9 +5,7 @@ chip soc/intel/cannonlake end # FSP configuration - register "SaGv" = "SaGv_Enabled" register "RMT" = "1" - register "ScsEmmcHs400Enabled" = "1" register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC4)" register "usb2_ports[1]" = "USB2_PORT_TYPE_C(OC0)" @@ -53,17 +51,17 @@ chip soc/intel/cannonlake register "PcieRpEnable[2]" = "1" register "PcieRpEnable[3]" = "1" register "PcieRpEnable[4]" = "1" - register "PcieRpEnable[5]" = "1" - register "PcieRpEnable[6]" = "1" - register "PcieRpEnable[7]" = "1" + register "PcieRpEnable[5]" = "0" + register "PcieRpEnable[6]" = "0" + register "PcieRpEnable[7]" = "0" register "PcieRpEnable[8]" = "1" - register "PcieRpEnable[9]" = "1" - register "PcieRpEnable[10]" = "1" - register "PcieRpEnable[11]" = "1" - register "PcieRpEnable[12]" = "1" - register "PcieRpEnable[13]" = "1" - register "PcieRpEnable[14]" = "1" - register "PcieRpEnable[15]" = "1" + register "PcieRpEnable[9]" = "0" + register "PcieRpEnable[10]" = "0" + register "PcieRpEnable[11]" = "0" + register "PcieRpEnable[12]" = "0" + register "PcieRpEnable[13]" = "0" + register "PcieRpEnable[14]" = "0" + register "PcieRpEnable[15]" = "0" register "PcieRpEnable[16]" = "1" register "PcieRpEnable[17]" = "1" register "PcieRpEnable[18]" = "1" @@ -95,38 +93,18 @@ chip soc/intel/cannonlake register "PcieClkSrcClkReq[9]" = "9" register "PcieClkSrcClkReq[10]" = "10" - # Enable "Intel Speed Shift Technology" - register "speed_shift_enable" = "1" - - # HECI - register "HeciEnabled" = "1" - device domain 0 on - device pci 00.0 on end # Host Bridge - device pci 02.0 on end # Integrated Graphics Device - device pci 04.0 on end # SA Thermal device - device pci 12.0 on end # Thermal Subsystem - device pci 12.5 off end # UFS SCS - device pci 12.6 off end # GSPI #2 - device pci 14.0 on end # USB xHCI - device pci 14.1 off end # USB xDCI (OTG) chip drivers/intel/wifi register "wake" = "PME_B0_EN_BIT" device pci 14.3 on end # CNVi wifi end - device pci 14.5 on end # SDCard - device pci 15.0 on end # I2C 0 + device pci 15.0 on end # I2C #0 device pci 15.1 on end # I2C #1 device pci 15.2 on end # I2C #2 device pci 15.3 on end # I2C #3 - device pci 16.0 on end # Management Engine Interface 1 - device pci 16.1 off end # Management Engine Interface 2 - device pci 16.2 off end # Management Engine IDE-R - device pci 16.3 off end # Management Engine KT Redirection - device pci 16.4 off end # Management Engine Interface 3 - device pci 16.5 off end # Management Engine Interface 4 device pci 17.0 on end # SATA - device pci 19.0 off end # I2C #4 + device pci 19.0 off end # I2C #4 (Not available on PCH-H) + device pci 19.1 off end # I2C #5 (Not available on PCH-H) device pci 19.2 on end # UART #2 device pci 1a.0 on end # eMMC device pci 1c.0 on end # PCI Express Port 1 @@ -134,7 +112,7 @@ chip soc/intel/cannonlake device pci 1c.5 off end # PCI Express Port 6 device pci 1c.6 off end # PCI Express Port 7 device pci 1c.7 off end # PCI Express Port 8 - device pci 1d.0 on end # PCI Express Port 9 X4 SLOT 1 + device pci 1d.0 on end # PCI Express Port 9 x4 SLOT 1 device pci 1d.1 off end # PCI Express Port 10 device pci 1d.2 off end # PCI Express Port 11 device pci 1d.3 off end # PCI Express Port 12 @@ -143,21 +121,11 @@ chip soc/intel/cannonlake device pci 1d.6 off end # PCI Express Port 15 device pci 1d.7 off end # PCI Express Port 16 device pci 1b.0 on end # PCI Express Port 17 + device pci 1b.1 on end # PCI Express Port 18 + device pci 1b.2 on end # PCI Express Port 19 + device pci 1b.3 on end # PCI Express Port 20 device pci 1b.4 on end # PCI Express Port 21 X4 SLOT 2 - device pci 1e.0 on end # UART #0 device pci 1e.1 off end # UART #1 - device pci 1e.2 off end # GSPI #0 - device pci 1e.3 off end # GSPI #1 - device pci 1f.0 on - chip drivers/pc80/tpm - device pnp 0c31.0 on end - end - end # LPC Interface - device pci 1f.1 on end # P2SB - device pci 1f.2 on end # Power Management Controller - device pci 1f.3 on end # Intel HDA - device pci 1f.4 on end # SMBus - device pci 1f.5 on end # PCH SPI device pci 1f.6 on end # GbE end end diff --git a/src/mainboard/intel/coffeelake_rvp/variants/cfl_u/devicetree.cb b/src/mainboard/intel/coffeelake_rvp/variants/cfl_u/overridetree.cb similarity index 54% rename from src/mainboard/intel/coffeelake_rvp/variants/cfl_u/devicetree.cb rename to src/mainboard/intel/coffeelake_rvp/variants/cfl_u/overridetree.cb index e5f867cbdc..c5c291df9f 100644 --- a/src/mainboard/intel/coffeelake_rvp/variants/cfl_u/devicetree.cb +++ b/src/mainboard/intel/coffeelake_rvp/variants/cfl_u/overridetree.cb @@ -4,28 +4,6 @@ chip soc/intel/cannonlake device lapic 0 on end end - # FSP configuration - register "SaGv" = "SaGv_Enabled" - register "ScsEmmcHs400Enabled" = "1" - - register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC0)" - register "usb2_ports[1]" = "USB2_PORT_MID(OC0)" - register "usb2_ports[2]" = "USB2_PORT_MID(OC0)" - register "usb2_ports[3]" = "USB2_PORT_MID(OC0)" - register "usb2_ports[4]" = "USB2_PORT_MID(OC0)" - register "usb2_ports[5]" = "USB2_PORT_MID(OC0)" - register "usb2_ports[6]" = "USB2_PORT_MID(OC0)" - register "usb2_ports[7]" = "USB2_PORT_MID(OC0)" - register "usb2_ports[8]" = "USB2_PORT_MID(OC0)" - register "usb2_ports[9]" = "USB2_PORT_MID(OC0)" - - register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC0)" - register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC0)" - register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC0)" - register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC0)" - register "usb3_ports[4]" = "USB3_PORT_DEFAULT(OC0)" - register "usb3_ports[5]" = "USB3_PORT_DEFAULT(OC0)" - register "PchHdaDspEnable" = "1" register "PchHdaAudioLinkHda" = "1" @@ -34,17 +12,17 @@ chip soc/intel/cannonlake register "PcieRpEnable[2]" = "1" register "PcieRpEnable[3]" = "1" register "PcieRpEnable[4]" = "1" - register "PcieRpEnable[5]" = "1" - register "PcieRpEnable[6]" = "1" - register "PcieRpEnable[7]" = "1" + register "PcieRpEnable[5]" = "0" + register "PcieRpEnable[6]" = "0" + register "PcieRpEnable[7]" = "0" register "PcieRpEnable[8]" = "1" - register "PcieRpEnable[9]" = "1" - register "PcieRpEnable[10]" = "1" - register "PcieRpEnable[11]" = "1" - register "PcieRpEnable[12]" = "1" - register "PcieRpEnable[13]" = "1" - register "PcieRpEnable[14]" = "1" - register "PcieRpEnable[15]" = "1" + register "PcieRpEnable[9]" = "0" + register "PcieRpEnable[10]" = "0" + register "PcieRpEnable[11]" = "0" + register "PcieRpEnable[12]" = "0" + register "PcieRpEnable[13]" = "0" + register "PcieRpEnable[14]" = "0" + register "PcieRpEnable[15]" = "0" register "PcieClkSrcUsage[0]" = "1" register "PcieClkSrcUsage[1]" = "8" @@ -60,9 +38,6 @@ chip soc/intel/cannonlake register "PcieClkSrcClkReq[4]" = "4" register "PcieClkSrcClkReq[5]" = "5" - # Enable "Intel Speed Shift Technology" - register "speed_shift_enable" = "1" - # GPIO for SD card detect register "sdcard_cd_gpio" = "GPP_G5" @@ -86,19 +61,10 @@ chip soc/intel/cannonlake }" device domain 0 on - device pci 00.0 on end # Host Bridge - device pci 02.0 on end # Integrated Graphics Device - device pci 04.0 on end # SA Thermal device - device pci 12.0 on end # Thermal Subsystem - device pci 12.5 off end # UFS SCS - device pci 12.6 off end # GSPI #2 - device pci 14.0 on end # USB xHCI - device pci 14.1 off end # USB xDCI (OTG) chip drivers/intel/wifi register "wake" = "PME_B0_EN_BIT" device pci 14.3 on end # CNVi wifi end - device pci 14.5 on end # SDCard device pci 15.0 on end # I2C #0 device pci 15.1 on end # I2C #1 device pci 15.2 off end # I2C #2 @@ -113,13 +79,7 @@ chip soc/intel/cannonlake device i2c 32 on end end end # I2C #3 - device pci 16.0 on end # Management Engine Interface 1 - device pci 16.1 off end # Management Engine Interface 2 - device pci 16.2 off end # Management Engine IDE-R - device pci 16.3 off end # Management Engine KT Redirection - device pci 16.4 off end # Management Engine Interface 3 - device pci 16.5 off end # Management Engine Interface 4 - device pci 17.0 off end # SATA + device pci 17.0 off end # SATA device pci 19.0 on end # I2C #4 device pci 19.1 off end # I2C #5 device pci 19.2 on end # UART #2 @@ -137,20 +97,9 @@ chip soc/intel/cannonlake device pci 1d.5 off end # PCI Express Port 14 device pci 1d.6 off end # PCI Express Port 15 device pci 1d.7 off end # PCI Express Port 16 - device pci 1e.0 on end # UART #0 device pci 1e.1 off end # UART #1 device pci 1e.2 off end # GSPI #0 device pci 1e.3 off end # GSPI #1 - device pci 1f.0 on - chip drivers/pc80/tpm - device pnp 0c31.0 on end - end - end # LPC Interface - device pci 1f.1 on end # P2SB - device pci 1f.2 on end # Power Management Controller - device pci 1f.3 on end # Intel HDA - device pci 1f.4 on end # SMBus - device pci 1f.5 on end # PCH SPI device pci 1f.6 off end # GbE end end diff --git a/src/mainboard/intel/coffeelake_rvp/variants/cml_u/devicetree.cb b/src/mainboard/intel/coffeelake_rvp/variants/cml_u/overridetree.cb similarity index 55% rename from src/mainboard/intel/coffeelake_rvp/variants/cml_u/devicetree.cb rename to src/mainboard/intel/coffeelake_rvp/variants/cml_u/overridetree.cb index 241ac33345..93b5af9394 100644 --- a/src/mainboard/intel/coffeelake_rvp/variants/cml_u/devicetree.cb +++ b/src/mainboard/intel/coffeelake_rvp/variants/cml_u/overridetree.cb @@ -4,12 +4,6 @@ chip soc/intel/cannonlake device lapic 0 on end end - # FSP configuration - register "SaGv" = "SaGv_Enabled" - register "ScsEmmcHs400Enabled" = "1" - register "HeciEnabled" = "1" - register "s0ix_enable" = "1" - # Enable eDP device register "DdiPortEdp" = "1" # Enable HPD for DDI ports B/C @@ -38,24 +32,6 @@ chip soc/intel/cannonlake [PchSerialIoIndexUART2] = PchSerialIoSkipInit, }" - register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC0)" - register "usb2_ports[1]" = "USB2_PORT_MID(OC0)" - register "usb2_ports[2]" = "USB2_PORT_MID(OC0)" - register "usb2_ports[3]" = "USB2_PORT_MID(OC0)" - register "usb2_ports[4]" = "USB2_PORT_MID(OC0)" - register "usb2_ports[5]" = "USB2_PORT_MID(OC0)" - register "usb2_ports[6]" = "USB2_PORT_MID(OC0)" - register "usb2_ports[7]" = "USB2_PORT_MID(OC0)" - register "usb2_ports[8]" = "USB2_PORT_MID(OC0)" - register "usb2_ports[9]" = "USB2_PORT_MID(OC0)" - - register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC0)" - register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC0)" - register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC0)" - register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC0)" - register "usb3_ports[4]" = "USB3_PORT_DEFAULT(OC0)" - register "usb3_ports[5]" = "USB3_PORT_DEFAULT(OC0)" - register "SataSalpSupport" = "1" register "SataPortsEnable[0]" = "1" register "SataPortsEnable[1]" = "1" @@ -74,17 +50,17 @@ chip soc/intel/cannonlake register "PcieRpEnable[2]" = "1" register "PcieRpEnable[3]" = "1" register "PcieRpEnable[4]" = "1" - register "PcieRpEnable[5]" = "1" - register "PcieRpEnable[6]" = "1" - register "PcieRpEnable[7]" = "1" + register "PcieRpEnable[5]" = "0" + register "PcieRpEnable[6]" = "0" + register "PcieRpEnable[7]" = "0" register "PcieRpEnable[8]" = "1" - register "PcieRpEnable[9]" = "1" - register "PcieRpEnable[10]" = "1" - register "PcieRpEnable[11]" = "1" - register "PcieRpEnable[12]" = "1" - register "PcieRpEnable[13]" = "1" - register "PcieRpEnable[14]" = "1" - register "PcieRpEnable[15]" = "1" + register "PcieRpEnable[9]" = "0" + register "PcieRpEnable[10]" = "0" + register "PcieRpEnable[11]" = "0" + register "PcieRpEnable[12]" = "0" + register "PcieRpEnable[13]" = "0" + register "PcieRpEnable[14]" = "0" + register "PcieRpEnable[15]" = "0" register "PcieClkSrcUsage[0]" = "1" register "PcieClkSrcUsage[1]" = "8" @@ -100,43 +76,26 @@ chip soc/intel/cannonlake register "PcieClkSrcClkReq[4]" = "4" register "PcieClkSrcClkReq[5]" = "5" - # Enable "Intel Speed Shift Technology" - register "speed_shift_enable" = "1" - # GPIO for SD card detect register "sdcard_cd_gpio" = "GPP_G5" device domain 0 on - device pci 00.0 on end # Host Bridge - device pci 02.0 on end # Integrated Graphics Device - device pci 04.0 on end # SA Thermal device - device pci 12.0 on end # Thermal Subsystem - device pci 12.5 off end # UFS SCS - device pci 12.6 off end # GSPI #2 - device pci 14.0 on end # USB xHCI - device pci 14.1 off end # USB xDCI (OTG) chip drivers/intel/wifi register "wake" = "PME_B0_EN_BIT" device pci 14.3 on end # CNVi wifi end device pci 14.5 on end # SDCard device pci 15.0 on end # I2C #0 - device pci 15.1 on end # I2C #1 + device pci 15.1 on end # I2C #1 device pci 15.2 off end # I2C #2 device pci 15.3 off end # I2C #3 - device pci 16.0 on end # Management Engine Interface 1 - device pci 16.1 off end # Management Engine Interface 2 - device pci 16.2 off end # Management Engine IDE-R - device pci 16.3 off end # Management Engine KT Redirection - device pci 16.4 off end # Management Engine Interface 3 - device pci 16.5 off end # Management Engine Interface 4 device pci 17.0 on end # SATA device pci 19.0 on end # I2C #4 device pci 19.1 off end # I2C #5 device pci 19.2 on end # UART #2 device pci 1a.0 on end # eMMC device pci 1c.0 on end # PCI Express Port 1 x4 SLOT1 - device pci 1c.4 on end # PCI Express Port 5 x1 SLOT2/LAN + device pci 1c.4 on end # PCI Express Port 5 x1 SLOT2/LAN device pci 1c.5 off end # PCI Express Port 6 device pci 1c.6 off end # PCI Express Port 7 device pci 1c.7 off end # PCI Express Port 8 @@ -148,20 +107,7 @@ chip soc/intel/cannonlake device pci 1d.5 off end # PCI Express Port 14 device pci 1d.6 off end # PCI Express Port 15 device pci 1d.7 off end # PCI Express Port 16 - device pci 1e.0 on end # UART #0 device pci 1e.1 off end # UART #1 - device pci 1e.2 off end # GSPI #0 - device pci 1e.3 off end # GSPI #1 - device pci 1f.0 on - chip drivers/pc80/tpm - device pnp 0c31.0 on end - end - end # LPC Interface - device pci 1f.1 on end # P2SB - device pci 1f.2 on end # Power Management Controller - device pci 1f.3 on end # Intel HDA - device pci 1f.4 on end # SMBus - device pci 1f.5 on end # PCH SPI device pci 1f.6 on end # GbE end end diff --git a/src/mainboard/intel/coffeelake_rvp/variants/whl_u/overridetree.cb b/src/mainboard/intel/coffeelake_rvp/variants/whl_u/overridetree.cb new file mode 100644 index 0000000000..1e388240a6 --- /dev/null +++ b/src/mainboard/intel/coffeelake_rvp/variants/whl_u/overridetree.cb @@ -0,0 +1,97 @@ +chip soc/intel/cannonlake + + device cpu_cluster 0 on + device lapic 0 on end + end + + # Enable eDP device + register "DdiPortEdp" = "1" + # Enable HPD for DDI ports B/C/D/F + register "DdiPortBHpd" = "1" + register "DdiPortCHpd" = "1" + register "DdiPortDHpd" = "1" + register "DdiPortFHpd" = "1" + # Enable DDC for DDI ports B/C/D/F + register "DdiPortBDdc" = "1" + register "DdiPortCDdc" = "1" + register "DdiPortDDdc" = "1" + register "DdiPortFDdc" = "1" + + register "SataSalpSupport" = "1" + register "SataPortsEnable[0]" = "1" + register "SataPortsEnable[1]" = "1" + register "SataPortsEnable[2]" = "1" + register "SataPortsEnable[3]" = "1" + register "SataPortsEnable[4]" = "1" + register "SataPortsEnable[5]" = "1" + register "SataPortsEnable[6]" = "1" + register "SataPortsEnable[7]" = "1" + + register "PchHdaDspEnable" = "1" + register "PchHdaAudioLinkHda" = "1" + + register "PcieRpEnable[0]" = "1" + register "PcieRpEnable[1]" = "1" + register "PcieRpEnable[2]" = "1" + register "PcieRpEnable[3]" = "1" + register "PcieRpEnable[4]" = "1" + register "PcieRpEnable[5]" = "0" + register "PcieRpEnable[6]" = "0" + register "PcieRpEnable[7]" = "0" + register "PcieRpEnable[8]" = "1" + register "PcieRpEnable[9]" = "0" + register "PcieRpEnable[10]" = "0" + register "PcieRpEnable[11]" = "0" + register "PcieRpEnable[12]" = "0" + register "PcieRpEnable[13]" = "0" + register "PcieRpEnable[14]" = "0" + register "PcieRpEnable[15]" = "0" + + register "PcieClkSrcUsage[0]" = "1" + register "PcieClkSrcUsage[1]" = "8" + register "PcieClkSrcUsage[2]" = "PCIE_CLK_LAN" + register "PcieClkSrcUsage[3]" = "13" + register "PcieClkSrcUsage[4]" = "4" + register "PcieClkSrcUsage[5]" = "14" + + register "PcieClkSrcClkReq[0]" = "0" + register "PcieClkSrcClkReq[1]" = "1" + register "PcieClkSrcClkReq[2]" = "2" + register "PcieClkSrcClkReq[3]" = "3" + register "PcieClkSrcClkReq[4]" = "4" + register "PcieClkSrcClkReq[5]" = "5" + + # GPIO for SD card detect + register "sdcard_cd_gpio" = "GPP_G5" + + device domain 0 on + chip drivers/intel/wifi + register "wake" = "PME_B0_EN_BIT" + device pci 14.3 on end # CNVi wifi + end + device pci 15.0 on end # I2C #0 + device pci 15.1 on end # I2C #1 + device pci 15.2 off end # I2C #2 + device pci 15.3 off end # I2C #3 + device pci 17.0 on end # SATA + device pci 19.0 on end # I2C #4 + device pci 19.1 off end # I2C #5 + device pci 19.2 on end # UART #2 + device pci 1a.0 on end # eMMC + device pci 1c.0 on end # PCI Express Port 1 x4 SLOT1 + device pci 1c.4 on end # PCI Express Port 5 x1 SLOT2/LAN + device pci 1c.5 off end # PCI Express Port 6 + device pci 1c.6 off end # PCI Express Port 7 + device pci 1c.7 off end # PCI Express Port 8 + device pci 1d.0 on end # PCI Express Port 9 + device pci 1d.1 off end # PCI Express Port 10 + device pci 1d.2 off end # PCI Express Port 11 + device pci 1d.3 off end # PCI Express Port 12 + device pci 1d.4 off end # PCI Express Port 13 + device pci 1d.5 off end # PCI Express Port 14 + device pci 1d.6 off end # PCI Express Port 15 + device pci 1d.7 off end # PCI Express Port 16 + device pci 1e.1 off end # UART #1 + device pci 1f.6 on end # GbE + end +end From fcd8c9e99e7f70e2b9494f2fa28a08ba13126daa Mon Sep 17 00:00:00 2001 From: Craig Hesling Date: Wed, 27 Nov 2019 11:50:47 -0800 Subject: [PATCH 0559/1242] hatch: Fix FPMCU pwr/rst gpio handling 1. No gpio control in bootblock 2. Disable power and assert reset in ramstage gpio 3. Power on and then deassert reset at the end of ramstage gpio 4. Disable power and assert reset when entering S5 On "reboot", the amount of time the power is disabled for is equivalent to the amount of time between triggering #4 and wrapping around to #3, which is about 400ms on Kohaku. Since #2 forces power off for FPMCU, S3 resume will still not work properly. Additionally, we must ensure that GPP_A12 is reconfigured as an output before going to any sleep state, since user space could have configured it to use its native3 function. See https://review.coreboot.org/c/coreboot/+/32111 for more detail. The control signals have been validated on a Kohaku in the following scenarios: 1. Cold startup 2. Issuing a "reboot" command 3. Issuing a "halt -p" and powering back on within 10 seconds 4. Issuing a "halt -p" and powering back on after 10 seconds 5. Entering and leaving S3 (does not work properly) 6. Entering and leaving S0iX BRANCH=hatch BUG=b/142751685 TEST=Verify all signals as mentioned above TEST=reboot flash_fp_mcu /opt/google/biod/fw/dartmonkey_v2.0.2417-af88cc91a.bin TEST=halt -p # power back on within 10 seconds flash_fp_mcu /opt/google/biod/fw/dartmonkey_v2.0.2417-af88cc91a.bin TEST=halt -p # power back on after 10 seconds flash_fp_mcu /opt/google/biod/fw/dartmonkey_v2.0.2417-af88cc91a.bin Change-Id: I2e3ff42715611d519677a4256bdd172ec98687f9 Signed-off-by: Craig Hesling Reviewed-on: https://review.coreboot.org/c/coreboot/+/37459 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh --- src/mainboard/google/hatch/ramstage.c | 7 ++++ .../google/hatch/variants/baseboard/gpio.c | 15 +++++---- .../baseboard/include/baseboard/variants.h | 3 ++ .../google/hatch/variants/helios/Makefile.inc | 2 ++ .../google/hatch/variants/helios/gpio.c | 28 +++++++++++----- .../google/hatch/variants/helios/ramstage.c | 32 +++++++++++++++++++ .../google/hatch/variants/kindred/gpio.c | 2 -- .../google/hatch/variants/kohaku/Makefile.inc | 2 ++ .../google/hatch/variants/kohaku/gpio.c | 26 +++++++++++---- .../google/hatch/variants/kohaku/ramstage.c | 32 +++++++++++++++++++ 10 files changed, 127 insertions(+), 22 deletions(-) create mode 100644 src/mainboard/google/hatch/variants/helios/ramstage.c create mode 100644 src/mainboard/google/hatch/variants/kohaku/ramstage.c diff --git a/src/mainboard/google/hatch/ramstage.c b/src/mainboard/google/hatch/ramstage.c index e9f50625cd..e84aa1861b 100644 --- a/src/mainboard/google/hatch/ramstage.c +++ b/src/mainboard/google/hatch/ramstage.c @@ -31,6 +31,11 @@ void __weak variant_devtree_update(void) /* Override dev tree settings per board */ } +void __weak variant_ramstage_init(void) +{ + /* Default weak implementation */ +} + static void mainboard_init(struct device *dev) { mainboard_ec_init(); @@ -56,6 +61,8 @@ static void mainboard_chip_init(void *chip_info) base_gpios, override_table, override_gpios); + + variant_ramstage_init(); } struct chip_operations mainboard_ops = { diff --git a/src/mainboard/google/hatch/variants/baseboard/gpio.c b/src/mainboard/google/hatch/variants/baseboard/gpio.c index 598600bda3..94cb2e53a2 100644 --- a/src/mainboard/google/hatch/variants/baseboard/gpio.c +++ b/src/mainboard/google/hatch/variants/baseboard/gpio.c @@ -38,7 +38,7 @@ static const struct pad_config gpio_table[] = { /* A11 : PCH_SPI_FPMCU_CS_L */ PAD_CFG_NF(GPP_A11, NONE, DEEP, NF2), /* A12 : FPMCU_RST_ODL */ - PAD_CFG_GPO(GPP_A12, 1, DEEP), + PAD_CFG_GPO(GPP_A12, 0, DEEP), /* A13 : SUSWARN_L */ PAD_CFG_NF(GPP_A13, NONE, DEEP, NF1), /* A14 : ESPI_RST_L */ @@ -133,7 +133,7 @@ static const struct pad_config gpio_table[] = { /* C10 : GPP_10 ==> GPP_C10_TP */ PAD_NC(GPP_C10, NONE), /* C11 : GPP_11 ==> EN_FP_RAILS */ - PAD_CFG_GPO(GPP_C11, 1, DEEP), + PAD_CFG_GPO(GPP_C11, 0, DEEP), /* C12 : GPP_C12 ==> NC */ PAD_NC(GPP_C12, NONE), /* C13 : EC_PCH_INT_L */ @@ -398,8 +398,10 @@ const struct pad_config *base_gpio_table(size_t *num) } /* - * Default GPIO settings before entering sleep. Configure A12: FPMCU_RST_ODL - * as GPO before entering sleep. + * Default GPIO settings before entering non-S5 sleep states. + * Configure A12: FPMCU_RST_ODL as GPO before entering sleep. + * This guarantees that A12's native3 function is disabled. + * See https://review.coreboot.org/c/coreboot/+/32111 . */ static const struct pad_config default_sleep_gpio_table[] = { PAD_CFG_GPO(GPP_A12, 1, DEEP), /* FPMCU_RST_ODL */ @@ -408,10 +410,11 @@ static const struct pad_config default_sleep_gpio_table[] = { /* * GPIO settings before entering S5, which are same as * default_sleep_gpio_table but also, - * turn off EN_PP3300_WWAN. + * turn off EN_PP3300_WWAN and FPMCU. */ static const struct pad_config s5_sleep_gpio_table[] = { - PAD_CFG_GPO(GPP_A12, 1, DEEP), /* FPMCU_RST_ODL */ + PAD_CFG_GPO(GPP_A12, 0, DEEP), /* FPMCU_RST_ODL */ + PAD_CFG_GPO(GPP_C11, 0, DEEP), /* PCH_FP_PWR_EN */ PAD_CFG_GPO(GPP_A18, 0, DEEP), /* EN_PP3300_WWAN */ }; diff --git a/src/mainboard/google/hatch/variants/baseboard/include/baseboard/variants.h b/src/mainboard/google/hatch/variants/baseboard/include/baseboard/variants.h index 920e428484..1542d9bc54 100644 --- a/src/mainboard/google/hatch/variants/baseboard/include/baseboard/variants.h +++ b/src/mainboard/google/hatch/variants/baseboard/include/baseboard/variants.h @@ -50,4 +50,7 @@ uint32_t get_board_sku(void); /* Modify devictree settings during ramstage. */ void variant_devtree_update(void); +/* Perform variant specific initialization early on in ramstage. */ +void variant_ramstage_init(void); + #endif /* BASEBOARD_VARIANTS_H */ diff --git a/src/mainboard/google/hatch/variants/helios/Makefile.inc b/src/mainboard/google/hatch/variants/helios/Makefile.inc index fbd69c40a9..be074b770d 100644 --- a/src/mainboard/google/hatch/variants/helios/Makefile.inc +++ b/src/mainboard/google/hatch/variants/helios/Makefile.inc @@ -17,4 +17,6 @@ SPD_SOURCES += LP_16G_2133 # 0b0001 romstage-y += memory.c bootblock-y += gpio.c + ramstage-y += gpio.c +ramstage-y += ramstage.c diff --git a/src/mainboard/google/hatch/variants/helios/gpio.c b/src/mainboard/google/hatch/variants/helios/gpio.c index 85eb3fc156..456877c8ee 100644 --- a/src/mainboard/google/hatch/variants/helios/gpio.c +++ b/src/mainboard/google/hatch/variants/helios/gpio.c @@ -117,8 +117,6 @@ const struct pad_config *override_gpio_table(size_t *num) * needed in this table. */ static const struct pad_config early_gpio_table[] = { - /* A12 : FPMCU_RST_ODL */ - PAD_CFG_GPO(GPP_A12, 0, DEEP), /* B15 : H1_SLAVE_SPI_CS_L */ PAD_CFG_NF(GPP_B15, NONE, DEEP, NF1), /* B16 : H1_SLAVE_SPI_CLK */ @@ -127,8 +125,6 @@ static const struct pad_config early_gpio_table[] = { PAD_CFG_NF(GPP_B17, NONE, DEEP, NF1), /* B18 : H1_SLAVE_SPI_MOSI_R */ PAD_CFG_NF(GPP_B18, NONE, DEEP, NF1), - /* C11 : GPP_C11 ==> EN_FP_RAILS */ - PAD_CFG_GPO(GPP_C11, 1, DEEP), /* C14 : BT_DISABLE_L */ PAD_CFG_GPO(GPP_C14, 0, DEEP), /* PCH_WP_OD */ @@ -150,14 +146,30 @@ const struct pad_config *variant_early_gpio_table(size_t *num) } /* - * GPIO settings before entering all sleep states + * Default GPIO settings before entering non-S5 sleep states. + * Configure A12: FPMCU_RST_ODL as GPO before entering sleep. + * This guarantees that A12's native3 function is disabled. + * See https://review.coreboot.org/c/coreboot/+/32111 . */ -static const struct pad_config sleep_gpio_table[] = { +static const struct pad_config default_sleep_gpio_table[] = { PAD_CFG_GPO(GPP_A12, 1, DEEP), /* FPMCU_RST_ODL */ }; +/* + * GPIO settings before entering S5, which are same as + * default_sleep_gpio_table but also, turn off FPMCU. + */ +static const struct pad_config s5_sleep_gpio_table[] = { + PAD_CFG_GPO(GPP_A12, 0, DEEP), /* FPMCU_RST_ODL */ + PAD_CFG_GPO(GPP_C11, 0, DEEP), /* PCH_FP_PWR_EN */ +}; + const struct pad_config *variant_sleep_gpio_table(u8 slp_typ, size_t *num) { - *num = ARRAY_SIZE(sleep_gpio_table); - return sleep_gpio_table; + if (slp_typ == ACPI_S5) { + *num = ARRAY_SIZE(s5_sleep_gpio_table); + return s5_sleep_gpio_table; + } + *num = ARRAY_SIZE(default_sleep_gpio_table); + return default_sleep_gpio_table; } diff --git a/src/mainboard/google/hatch/variants/helios/ramstage.c b/src/mainboard/google/hatch/variants/helios/ramstage.c new file mode 100644 index 0000000000..9b919fccd8 --- /dev/null +++ b/src/mainboard/google/hatch/variants/helios/ramstage.c @@ -0,0 +1,32 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2019 Google LLC + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include +#include + +void variant_ramstage_init(void) +{ + /* + * Enable power to FPMCU, wait for power rail to stabilize, + * and then deassert FPMCU reset. + * Waiting for the power rail to stabilize can take a while, + * a minimum of 400us on Kohaku. + */ + gpio_output(GPP_C11, 1); + mdelay(1); + gpio_output(GPP_A12, 1); +} diff --git a/src/mainboard/google/hatch/variants/kindred/gpio.c b/src/mainboard/google/hatch/variants/kindred/gpio.c index 827ee0b504..9e2d818f9b 100644 --- a/src/mainboard/google/hatch/variants/kindred/gpio.c +++ b/src/mainboard/google/hatch/variants/kindred/gpio.c @@ -154,8 +154,6 @@ const struct pad_config *override_gpio_table(size_t *num) * needed in this table. */ static const struct pad_config early_gpio_table[] = { - /* A12 : FPMCU_RST_ODL */ - PAD_CFG_GPO(GPP_A12, 0, DEEP), /* B15 : H1_SLAVE_SPI_CS_L */ PAD_CFG_NF(GPP_B15, NONE, DEEP, NF1), /* B16 : H1_SLAVE_SPI_CLK */ diff --git a/src/mainboard/google/hatch/variants/kohaku/Makefile.inc b/src/mainboard/google/hatch/variants/kohaku/Makefile.inc index 9cdff32074..6bd29737aa 100644 --- a/src/mainboard/google/hatch/variants/kohaku/Makefile.inc +++ b/src/mainboard/google/hatch/variants/kohaku/Makefile.inc @@ -17,4 +17,6 @@ SPD_SOURCES = LP_8G_2133 # 0b000 romstage-y += memory.c bootblock-y += gpio.c + ramstage-y += gpio.c +ramstage-y += ramstage.c diff --git a/src/mainboard/google/hatch/variants/kohaku/gpio.c b/src/mainboard/google/hatch/variants/kohaku/gpio.c index 61d3375d6d..f52cc27724 100644 --- a/src/mainboard/google/hatch/variants/kohaku/gpio.c +++ b/src/mainboard/google/hatch/variants/kohaku/gpio.c @@ -97,8 +97,6 @@ const struct pad_config *override_gpio_table(size_t *num) * needed in this table. */ static const struct pad_config early_gpio_table[] = { - /* A12 : FPMCU_RST_ODL */ - PAD_CFG_GPO(GPP_A12, 0, DEEP), /* B15 : H1_SLAVE_SPI_CS_L */ PAD_CFG_NF(GPP_B15, NONE, DEEP, NF1), /* B16 : H1_SLAVE_SPI_CLK */ @@ -136,14 +134,30 @@ const struct pad_config *variant_early_gpio_table(size_t *num) } /* - * GPIO settings before entering all sleep states + * Default GPIO settings before entering non-S5 sleep states. + * Configure A12: FPMCU_RST_ODL as GPO before entering sleep. + * This guarantees that A12's native3 function is disabled. + * See https://review.coreboot.org/c/coreboot/+/32111 . */ -static const struct pad_config sleep_gpio_table[] = { +static const struct pad_config default_sleep_gpio_table[] = { PAD_CFG_GPO(GPP_A12, 1, DEEP), /* FPMCU_RST_ODL */ }; +/* + * GPIO settings before entering S5, which are same as + * default_sleep_gpio_table but also, turn off FPMCU. + */ +static const struct pad_config s5_sleep_gpio_table[] = { + PAD_CFG_GPO(GPP_A12, 0, DEEP), /* FPMCU_RST_ODL */ + PAD_CFG_GPO(GPP_C11, 0, DEEP), /* PCH_FP_PWR_EN */ +}; + const struct pad_config *variant_sleep_gpio_table(u8 slp_typ, size_t *num) { - *num = ARRAY_SIZE(sleep_gpio_table); - return sleep_gpio_table; + if (slp_typ == ACPI_S5) { + *num = ARRAY_SIZE(s5_sleep_gpio_table); + return s5_sleep_gpio_table; + } + *num = ARRAY_SIZE(default_sleep_gpio_table); + return default_sleep_gpio_table; } diff --git a/src/mainboard/google/hatch/variants/kohaku/ramstage.c b/src/mainboard/google/hatch/variants/kohaku/ramstage.c new file mode 100644 index 0000000000..9b919fccd8 --- /dev/null +++ b/src/mainboard/google/hatch/variants/kohaku/ramstage.c @@ -0,0 +1,32 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2019 Google LLC + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include +#include + +void variant_ramstage_init(void) +{ + /* + * Enable power to FPMCU, wait for power rail to stabilize, + * and then deassert FPMCU reset. + * Waiting for the power rail to stabilize can take a while, + * a minimum of 400us on Kohaku. + */ + gpio_output(GPP_C11, 1); + mdelay(1); + gpio_output(GPP_A12, 1); +} From 1debc0c1019159396ca2f72874938a991bb3246e Mon Sep 17 00:00:00 2001 From: Joel Kitching Date: Wed, 27 Nov 2019 14:25:16 +0800 Subject: [PATCH 0560/1242] vboot: update VbExNvStorageWrite function Going forwards, vb2ex_commit_data will be used to flush both nvdata and secdata. The patch that is circularly dependent on this lies between a patch that makes vboot no longer build and the patch that fixes that, so we have to pull the whole thing in at once to sort out the mess. Updating from commit id 1c4dbaa0: 2019-11-18 Julius Werner Makefile: Fix typo for MOCK_TPM to commit id 695c56dc: 2019-12-04 Julius Werner Makefile: Make loop unrolling fully controllable by the caller BUG=b:124141368, chromium:1006689 TEST=make clean && make test-abuild BRANCH=none Change-Id: Ia2612da0df101cd3c46151dbce728633a39fada1 Signed-off-by: Joel Kitching Signed-off-by: Julius Werner Reviewed-on: https://review.coreboot.org/c/coreboot/+/37315 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin --- 3rdparty/vboot | 2 +- src/security/vboot/ec_sync.c | 4 ++-- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/3rdparty/vboot b/3rdparty/vboot index 1c4dbaa084..695c56dc50 160000 --- a/3rdparty/vboot +++ b/3rdparty/vboot @@ -1 +1 @@ -Subproject commit 1c4dbaa08419e13366db32ed20244f63c34388a0 +Subproject commit 695c56dc50a59e5c9098c94f41b3d86b8f99baf1 diff --git a/src/security/vboot/ec_sync.c b/src/security/vboot/ec_sync.c index c2a6b25f90..8a3ba71d75 100644 --- a/src/security/vboot/ec_sync.c +++ b/src/security/vboot/ec_sync.c @@ -399,9 +399,9 @@ vb2_error_t VbExDisplayScreen(uint32_t screen_type, uint32_t locale, /* * Write opaque data into NV storage region. */ -vb2_error_t VbExNvStorageWrite(const uint8_t *buf) +vb2_error_t vb2ex_commit_data(struct vb2_context *ctx) { - save_vbnv(buf); + save_vbnv(ctx->nvdata); return VB2_SUCCESS; } From 683657e93ac52a194807d824d417e7fc3226ee9d Mon Sep 17 00:00:00 2001 From: Julius Werner Date: Wed, 4 Dec 2019 12:50:43 -0800 Subject: [PATCH 0561/1242] vboot: Clear secdata change flags after factory init factory_initialize_tpm() calls secdata_xxx_create() (for both firmware and kernel space) and then immediately writes those spaces out to the TPM. The create() functions make vboot think it just changed the secdata (because it reinitialized the byte arrays in the context), so we also need to clear the VB2_CONTEXT_SECDATA_xxx_CHANGED flags again, otherwise vboot thinks it still needs to flush the spaces out to the TPM even though we already did that. Also clean up some minor related stuff (VB2_CONTEXT_SECDATA_CHANGED notation is deprecated, and secdata space intialization should use the same write-and-readback function we use for updates). Change-Id: I231fadcf7b35a1aec3b39254e7e41c3d456d4911 Signed-off-by: Julius Werner Reviewed-on: https://review.coreboot.org/c/coreboot/+/37471 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin --- src/security/vboot/secdata_tpm.c | 12 +++++++----- src/security/vboot/vboot_logic.c | 4 ++-- 2 files changed, 9 insertions(+), 7 deletions(-) diff --git a/src/security/vboot/secdata_tpm.c b/src/security/vboot/secdata_tpm.c index 0afd00d6cc..ef245552d5 100644 --- a/src/security/vboot/secdata_tpm.c +++ b/src/security/vboot/secdata_tpm.c @@ -188,7 +188,7 @@ static uint32_t set_space(const char *name, uint32_t index, const void *data, if (rv != TPM_SUCCESS) return rv; - return safe_write(index, data, length); + return write_secdata(index, data, length); } static uint32_t set_firmware_space(const void *firmware_blob) @@ -398,6 +398,11 @@ static uint32_t factory_initialize_tpm(struct vb2_context *ctx) if (result != TPM_SUCCESS) return result; + /* _factory_initialize_tpm() writes initial secdata values to TPM + immediately, so let vboot know that it's up to date now. */ + ctx->flags &= ~(VB2_CONTEXT_SECDATA_FIRMWARE_CHANGED | + VB2_CONTEXT_SECDATA_KERNEL_CHANGED); + VBDEBUG("TPM: factory initialization successful\n"); return TPM_SUCCESS; @@ -410,14 +415,11 @@ uint32_t antirollback_read_space_firmware(struct vb2_context *ctx) /* Read the firmware space. */ rv = read_space_firmware(ctx); if (rv == TPM_E_BADINDEX) { - /* - * This seems the first time we've run. Initialize the TPM. - */ + /* This seems the first time we've run. Initialize the TPM. */ VBDEBUG("TPM: Not initialized yet.\n"); RETURN_ON_FAILURE(factory_initialize_tpm(ctx)); } else if (rv != TPM_SUCCESS) { VBDEBUG("TPM: Firmware space in a bad state; giving up.\n"); - //RETURN_ON_FAILURE(factory_initialize_tpm(ctx)); return TPM_E_CORRUPTED_STATE; } diff --git a/src/security/vboot/vboot_logic.c b/src/security/vboot/vboot_logic.c index ccce148882..6c4f8fd2a8 100644 --- a/src/security/vboot/vboot_logic.c +++ b/src/security/vboot/vboot_logic.c @@ -265,10 +265,10 @@ void vboot_save_nvdata_only(struct vb2_context *ctx) void vboot_save_data(struct vb2_context *ctx) { - if (ctx->flags & VB2_CONTEXT_SECDATA_CHANGED) { + if (ctx->flags & VB2_CONTEXT_SECDATA_FIRMWARE_CHANGED) { printk(BIOS_INFO, "Saving secdata\n"); antirollback_write_space_firmware(ctx); - ctx->flags &= ~VB2_CONTEXT_SECDATA_CHANGED; + ctx->flags &= ~VB2_CONTEXT_SECDATA_FIRMWARE_CHANGED; } vboot_save_nvdata_only(ctx); From d3f2a1e4a977d26bf7a0c4e281fada356b75425c Mon Sep 17 00:00:00 2001 From: Elyes HAOUAS Date: Thu, 5 Dec 2019 09:38:26 +0100 Subject: [PATCH 0562/1242] superio/fintek: Fix typo Change-Id: If5c0921e20b26ce558f542f405cf62ae8d4a8101 Signed-off-by: Elyes HAOUAS Reviewed-on: https://review.coreboot.org/c/coreboot/+/37503 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel Reviewed-by: Felix Held Reviewed-by: Angel Pons --- src/superio/fintek/common/fan_control.h | 2 +- src/superio/fintek/f81803a/fan_control.c | 8 ++++---- 2 files changed, 5 insertions(+), 5 deletions(-) diff --git a/src/superio/fintek/common/fan_control.h b/src/superio/fintek/common/fan_control.h index c3167782be..80f17dd0c2 100644 --- a/src/superio/fintek/common/fan_control.h +++ b/src/superio/fintek/common/fan_control.h @@ -115,7 +115,7 @@ struct fintek_fan { #define HWM_STATUS_INVALID_SECTION_VALUE -9 #define HWM_STATUS_BOUNDARY_WRONG_ORDER -10 #define HWM_STATUS_SECTIONS_WRONG_ORDER -11 -#define HWM_STATUS_WARNING_SENSOR_DISCONECTED 1 +#define HWM_STATUS_WARNING_SENSOR_DISCONNECTED 1 #define HWM_STATUS_WARNING_FAN_NOT_PWM 2 #define CPU_DAMAGE_TEMP 110 diff --git a/src/superio/fintek/f81803a/fan_control.c b/src/superio/fintek/f81803a/fan_control.c index 41fd0d3d50..a08180a7f9 100644 --- a/src/superio/fintek/f81803a/fan_control.c +++ b/src/superio/fintek/f81803a/fan_control.c @@ -159,16 +159,16 @@ int set_sensor_type(u16 base_address, external_sensor sensor, switch (sensor) { case EXTERNAL_SENSOR1: if (sensor_status & TP_EXTERNAL_SENSOR1_OPEN) { - printk(BIOS_WARNING, "Sensor 1 disconected!\n"); - return HWM_STATUS_WARNING_SENSOR_DISCONECTED; + printk(BIOS_WARNING, "Sensor 1 disconnected!\n"); + return HWM_STATUS_WARNING_SENSOR_DISCONNECTED; } hwm_reg_modify(base_address, TP_SENSOR_TYPE, TP_SENSOR1_TYPE_SHIFT, TP_SENSOR_TYPE_MASK, type); break; case EXTERNAL_SENSOR2: if (sensor_status & TP_EXTERNAL_SENSOR2_OPEN) { - printk(BIOS_WARNING, "Sensor 2 disconected!\n"); - return HWM_STATUS_WARNING_SENSOR_DISCONECTED; + printk(BIOS_WARNING, "Sensor 2 disconnected!\n"); + return HWM_STATUS_WARNING_SENSOR_DISCONNECTED; } hwm_reg_modify(base_address, TP_SENSOR_TYPE, TP_SENSOR2_TYPE_SHIFT, TP_SENSOR_TYPE_MASK, type); From 5cf4d0c14896bb80a4b70f97ae036f2255d2de85 Mon Sep 17 00:00:00 2001 From: Elyes HAOUAS Date: Thu, 5 Dec 2019 11:18:52 +0100 Subject: [PATCH 0563/1242] src/superio/via: Remove unused superio chips Change-Id: I248608361fcdc51ff435222d37c5bbc736b1947e Signed-off-by: Elyes HAOUAS Reviewed-on: https://review.coreboot.org/c/coreboot/+/37511 Tested-by: build bot (Jenkins) Reviewed-by: Felix Held Reviewed-by: Angel Pons --- src/superio/via/Makefile.inc | 16 ---------------- 1 file changed, 16 deletions(-) delete mode 100644 src/superio/via/Makefile.inc diff --git a/src/superio/via/Makefile.inc b/src/superio/via/Makefile.inc deleted file mode 100644 index 890ed00fc0..0000000000 --- a/src/superio/via/Makefile.inc +++ /dev/null @@ -1,16 +0,0 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2009 Ronald G. Minnich -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; version 2 of the License. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## - -subdirs-y += vt1211 From 462738299b04fcb1900109485e6d2abe4c41d761 Mon Sep 17 00:00:00 2001 From: Elyes HAOUAS Date: Thu, 5 Dec 2019 10:13:41 +0100 Subject: [PATCH 0564/1242] superio/nsc/pc87417: Remove unused Change-Id: Icacf2806702a868a807080e1e2d14b1ee4ed4f90 Signed-off-by: Elyes HAOUAS Reviewed-on: https://review.coreboot.org/c/coreboot/+/37507 Reviewed-by: Felix Held Tested-by: build bot (Jenkins) --- src/superio/nsc/pc87417/pc87417.h | 1 - 1 file changed, 1 deletion(-) diff --git a/src/superio/nsc/pc87417/pc87417.h b/src/superio/nsc/pc87417/pc87417.h index 25401e4617..c3fc5ef699 100644 --- a/src/superio/nsc/pc87417/pc87417.h +++ b/src/superio/nsc/pc87417/pc87417.h @@ -111,7 +111,6 @@ #define PC87417_XWBCNF 0x16 #include -#include void pc87417_disable_dev(pnp_devfn_t dev); void pc87417_enable_dev(pnp_devfn_t dev); From 6fdf122fc391a894ae8ea340c58ef351be3dd5f1 Mon Sep 17 00:00:00 2001 From: Elyes HAOUAS Date: Thu, 5 Dec 2019 11:01:47 +0100 Subject: [PATCH 0565/1242] superio/smsc/lpc47n207: Remove unused Change-Id: I9e6b2548ff7eb7224b15ffa2541922790816c947 Signed-off-by: Elyes HAOUAS Reviewed-on: https://review.coreboot.org/c/coreboot/+/37509 Tested-by: build bot (Jenkins) Reviewed-by: Felix Held --- src/superio/smsc/lpc47n207/lpc47n207.h | 2 -- 1 file changed, 2 deletions(-) diff --git a/src/superio/smsc/lpc47n207/lpc47n207.h b/src/superio/smsc/lpc47n207/lpc47n207.h index e13d10a81c..f8e06c89c6 100644 --- a/src/superio/smsc/lpc47n207/lpc47n207.h +++ b/src/superio/smsc/lpc47n207/lpc47n207.h @@ -16,8 +16,6 @@ #ifndef SUPERIO_SMSC_LPC47N207_H #define SUPERIO_SMSC_LPC47N207_H -#include - void try_enabling_LPC47N207_uart(void); #endif /* SUPERIO_SMSC_LPC47N207_H */ From 879ea7fce8a21359ad80e4008c41587b3e1769ae Mon Sep 17 00:00:00 2001 From: Julius Werner Date: Thu, 28 Nov 2019 12:53:43 -0800 Subject: [PATCH 0566/1242] endian: Replace explicit byte swapping with compiler builtin gcc seems to have some stupid problem with deciding when to inline byte swapping functions (https://gcc.gnu.org/bugzilla/show_bug.cgi?id=92716). Using the compiler builtin instead seems to solve the problem. (This doesn't yet solve the issue for the read_be32()-family of functions, which we should maybe just get rid of at some point?) Change-Id: Ia2a6d8ea98987266ccc32ffaa0a7f78965fca1cd Signed-off-by: Julius Werner Reviewed-on: https://review.coreboot.org/c/coreboot/+/37343 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin --- payloads/libpayload/include/endian.h | 29 ++++-------------- payloads/libpayload/include/swab.h | 44 ---------------------------- src/include/swab.h | 6 ++++ 3 files changed, 12 insertions(+), 67 deletions(-) delete mode 100644 payloads/libpayload/include/swab.h diff --git a/payloads/libpayload/include/endian.h b/payloads/libpayload/include/endian.h index ec0825dc31..dee45f227b 100644 --- a/payloads/libpayload/include/endian.h +++ b/payloads/libpayload/include/endian.h @@ -34,23 +34,6 @@ #include #include -static inline uint16_t swap_bytes16(uint16_t in) -{ - return ((in & 0xFF) << 8) | ((in & 0xFF00) >> 8); -} - -static inline uint32_t swap_bytes32(uint32_t in) -{ - return ((in & 0xFF) << 24) | ((in & 0xFF00) << 8) | - ((in & 0xFF0000) >> 8) | ((in & 0xFF000000) >> 24); -} - -static inline uint64_t swap_bytes64(uint64_t in) -{ - return ((uint64_t)swap_bytes32((uint32_t)in) << 32) | - ((uint64_t)swap_bytes32((uint32_t)(in >> 32))); -} - /* Endian functions from glibc 2.9 / BSD "endian.h" */ #if CONFIG(LP_BIG_ENDIAN) @@ -59,15 +42,15 @@ static inline uint64_t swap_bytes64(uint64_t in) #define htobe32(in) (in) #define htobe64(in) (in) -#define htole16(in) swap_bytes16(in) -#define htole32(in) swap_bytes32(in) -#define htole64(in) swap_bytes64(in) +#define htole16(in) ((uint16_t)__builtin_bswap16(in)) +#define htole32(in) ((uint32_t)__builtin_bswap32(in)) +#define htole64(in) ((uint64_t)__builtin_bswap64(in)) #elif CONFIG(LP_LITTLE_ENDIAN) -#define htobe16(in) swap_bytes16(in) -#define htobe32(in) swap_bytes32(in) -#define htobe64(in) swap_bytes64(in) +#define htobe16(in) ((uint16_t)__builtin_bswap16(in)) +#define htobe32(in) ((uint32_t)__builtin_bswap32(in)) +#define htobe64(in) ((uint64_t)__builtin_bswap64(in)) #define htole16(in) (in) #define htole32(in) (in) diff --git a/payloads/libpayload/include/swab.h b/payloads/libpayload/include/swab.h deleted file mode 100644 index 2198077ad2..0000000000 --- a/payloads/libpayload/include/swab.h +++ /dev/null @@ -1,44 +0,0 @@ -#ifndef _SWAB_H -#define _SWAB_H - -/* - * linux/byteorder/swab.h - * Byte-swapping, independently from CPU endianness - * swabXX[ps]?(foo) - * - * Francois-Rene Rideau 19971205 - * separated swab functions from cpu_to_XX, - * to clean up support for bizarre-endian architectures. - * - * See asm-i386/byteorder.h and suches for examples of how to provide - * architecture-dependent optimized versions - * - */ - -/* casts are necessary for constants, because we never know for sure - * how U/UL/ULL map to __u16, __u32, __u64. At least not in a portable way. - */ -#define swab16(x) \ - ((unsigned short)( \ - (((unsigned short)(x) & (unsigned short)0x00ffU) << 8) | \ - (((unsigned short)(x) & (unsigned short)0xff00U) >> 8))) - -#define swab32(x) \ - ((unsigned int)( \ - (((unsigned int)(x) & (unsigned int)0x000000ffUL) << 24) | \ - (((unsigned int)(x) & (unsigned int)0x0000ff00UL) << 8) | \ - (((unsigned int)(x) & (unsigned int)0x00ff0000UL) >> 8) | \ - (((unsigned int)(x) & (unsigned int)0xff000000UL) >> 24))) - -#define swab64(x) \ - ((uint64_t)( \ - (((uint64_t)(x) & (uint64_t)0x00000000000000ffULL) << 56) | \ - (((uint64_t)(x) & (uint64_t)0x000000000000ff00ULL) << 40) | \ - (((uint64_t)(x) & (uint64_t)0x0000000000ff0000ULL) << 24) | \ - (((uint64_t)(x) & (uint64_t)0x00000000ff000000ULL) << 8) | \ - (((uint64_t)(x) & (uint64_t)0x000000ff00000000ULL) >> 8) | \ - (((uint64_t)(x) & (uint64_t)0x0000ff0000000000ULL) >> 24) | \ - (((uint64_t)(x) & (uint64_t)0x00ff000000000000ULL) >> 40) | \ - (((uint64_t)(x) & (uint64_t)0xff00000000000000ULL) >> 56))) - -#endif /* _SWAB_H */ diff --git a/src/include/swab.h b/src/include/swab.h index 956cfa5532..57fe5a2e53 100644 --- a/src/include/swab.h +++ b/src/include/swab.h @@ -21,6 +21,7 @@ #include +#if defined(__ROMCC__) || ENV_ARMV4 #define swab16(x) \ ((unsigned short)( \ (((unsigned short)(x) & (unsigned short)0x00ffU) << 8) | \ @@ -43,5 +44,10 @@ (((uint64_t)(x) & (uint64_t)0x0000ff0000000000ULL) >> 24) | \ (((uint64_t)(x) & (uint64_t)0x00ff000000000000ULL) >> 40) | \ (((uint64_t)(x) & (uint64_t)0xff00000000000000ULL) >> 56))) +#else /* __ROMCC__ || ENV_ARMV4 */ +#define swab16(x) ((uint16_t)__builtin_bswap16(x)) +#define swab32(x) ((uint32_t)__builtin_bswap32(x)) +#define swab64(x) ((uint64_t)__builtin_bswap64(x)) +#endif /* !(__ROMCC__ || ENV_ARMV4) */ #endif /* _SWAB_H */ From 8cb5ea7879cf82b79ab9a2c4342c542a167943bf Mon Sep 17 00:00:00 2001 From: Elyes HAOUAS Date: Thu, 5 Dec 2019 14:33:07 +0100 Subject: [PATCH 0567/1242] nb/i945: Fix typo Change-Id: I082ac2c1c13cbe6835a02d703f8651e837a43f37 Signed-off-by: Elyes HAOUAS Reviewed-on: https://review.coreboot.org/c/coreboot/+/37518 Tested-by: build bot (Jenkins) Reviewed-by: Angel Pons --- src/northbridge/intel/i945/memmap.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/northbridge/intel/i945/memmap.c b/src/northbridge/intel/i945/memmap.c index 000ac7e682..54141205ec 100644 --- a/src/northbridge/intel/i945/memmap.c +++ b/src/northbridge/intel/i945/memmap.c @@ -55,7 +55,7 @@ static uintptr_t northbridge_get_tseg_base(void) else tom = (pci_read_config8(PCI_DEV(0, 0, 0), TOLUD) & 0xf7) << 24; - /* subsctract TSEG size */ + /* subtract TSEG size */ tom -= decode_tseg_size(pci_read_config8(PCI_DEV(0, 0, 0), ESMRAMC)); return tom; } From 934ae21b52492c9c730dc5accd2900b32c5c1492 Mon Sep 17 00:00:00 2001 From: Philipp Hug Date: Wed, 4 Sep 2019 09:24:45 -0700 Subject: [PATCH 0568/1242] mb/emulation/qemu-riscv: Implement ipi using clint to enable smp in qemu/spike. TEST=Set MAX_CPUS=2 and run qemu with -smp 2 Signed-off-by: Philipp Hug Change-Id: I94fb25fad103e3cb5db676eb4caead11d54ae0ae Reviewed-on: https://review.coreboot.org/c/coreboot/+/35246 Tested-by: build bot (Jenkins) Reviewed-by: Xiang Wang --- .../emulation/qemu-riscv/Makefile.inc | 1 + src/mainboard/emulation/qemu-riscv/clint.c | 6 ++++++ .../emulation/spike-riscv/Makefile.inc | 1 + src/mainboard/emulation/spike-riscv/clint.c | 6 ++++++ src/soc/ucb/riscv/Makefile.inc | 4 ---- src/soc/ucb/riscv/ipi.c | 21 ------------------- 6 files changed, 14 insertions(+), 25 deletions(-) delete mode 100644 src/soc/ucb/riscv/ipi.c diff --git a/src/mainboard/emulation/qemu-riscv/Makefile.inc b/src/mainboard/emulation/qemu-riscv/Makefile.inc index eb99544c35..2ca75fdae1 100644 --- a/src/mainboard/emulation/qemu-riscv/Makefile.inc +++ b/src/mainboard/emulation/qemu-riscv/Makefile.inc @@ -19,6 +19,7 @@ bootblock-y += clint.c romstage-y += romstage.c romstage-y += uart.c romstage-y += rom_media.c +romstage-y += clint.c ramstage-y += uart.c ramstage-y += rom_media.c diff --git a/src/mainboard/emulation/qemu-riscv/clint.c b/src/mainboard/emulation/qemu-riscv/clint.c index 367d48d4ae..4a00bc2142 100644 --- a/src/mainboard/emulation/qemu-riscv/clint.c +++ b/src/mainboard/emulation/qemu-riscv/clint.c @@ -14,6 +14,7 @@ */ #include +#include #include /* This function is used to initialize HLS()->time/HLS()->timecmp */ @@ -23,3 +24,8 @@ void mtime_init(void) HLS()->time = (uint64_t *)(QEMU_VIRT_CLINT + 0xbff8); HLS()->timecmp = (uint64_t *)(QEMU_VIRT_CLINT + 0x4000 + 8 * hart_id); } + +void set_msip(int hartid, int val) +{ + write32((void *)(QEMU_VIRT_CLINT + 4 * (uintptr_t)hartid), !!val); +} diff --git a/src/mainboard/emulation/spike-riscv/Makefile.inc b/src/mainboard/emulation/spike-riscv/Makefile.inc index 38977b6345..bfeaf58867 100644 --- a/src/mainboard/emulation/spike-riscv/Makefile.inc +++ b/src/mainboard/emulation/spike-riscv/Makefile.inc @@ -18,6 +18,7 @@ bootblock-y += clint.c romstage-y += romstage.c romstage-y += uart.c romstage-y += rom_media.c +romstage-y += clint.c ramstage-y += uart.c ramstage-y += rom_media.c ramstage-y += clint.c diff --git a/src/mainboard/emulation/spike-riscv/clint.c b/src/mainboard/emulation/spike-riscv/clint.c index 7ad3f5a7af..c39e05831c 100644 --- a/src/mainboard/emulation/spike-riscv/clint.c +++ b/src/mainboard/emulation/spike-riscv/clint.c @@ -14,6 +14,7 @@ */ #include +#include #define SPIKE_CLINT_BASE 0x02000000 @@ -24,3 +25,8 @@ void mtime_init(void) HLS()->time = (uint64_t *)(SPIKE_CLINT_BASE + 0xbff8); HLS()->timecmp = (uint64_t *)(SPIKE_CLINT_BASE + 0x4000 + 8 * hart_id); } + +void set_msip(int hartid, int val) +{ + write32((void *)(SPIKE_CLINT_BASE + 4 * (uintptr_t)hartid), !!val); +} diff --git a/src/soc/ucb/riscv/Makefile.inc b/src/soc/ucb/riscv/Makefile.inc index ef03642d89..80899d570f 100644 --- a/src/soc/ucb/riscv/Makefile.inc +++ b/src/soc/ucb/riscv/Makefile.inc @@ -1,11 +1,7 @@ ifeq ($(CONFIG_SOC_UCB_RISCV),y) -bootblock-y += ipi.c - romstage-y += cbmem.c -romstage-y += ipi.c ramstage-y += cbmem.c -ramstage-y += ipi.c endif diff --git a/src/soc/ucb/riscv/ipi.c b/src/soc/ucb/riscv/ipi.c deleted file mode 100644 index 80307a8d2a..0000000000 --- a/src/soc/ucb/riscv/ipi.c +++ /dev/null @@ -1,21 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2018 HardenedLinux - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include - -/* TODO: Please implement this function */ -void set_msip(int hartid, int val) -{ -} From 05fe16c4f344d3fe23725d35104d38dab590a746 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ky=C3=B6sti=20M=C3=A4lkki?= Date: Sun, 1 Dec 2019 08:38:11 +0200 Subject: [PATCH 0569/1242] console,monotonic_timer: Avoid calls from APs MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The code in cpu/x86/lapic/apic_timer.c for timer_monotonic_get() is not SMP safe as LAPIC timers do not run as synchronised as TSCs. The times reported for console for boot_states does not accumulate from APs now. Also remove console time tracking from ENV_SMM. Change-Id: I1ea2c1e7172f8ab3692b42dee3f669c5942d864a Signed-off-by: Kyösti Mälkki Reviewed-on: https://review.coreboot.org/c/coreboot/+/37398 Reviewed-by: Arthur Heymans Tested-by: build bot (Jenkins) --- src/console/printk.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/src/console/printk.c b/src/console/printk.c index a08dd2f80f..b32fadb8b1 100644 --- a/src/console/printk.c +++ b/src/console/printk.c @@ -25,20 +25,20 @@ DECLARE_SPIN_LOCK(console_lock) -#define TRACK_CONSOLE_TIME (CONFIG(HAVE_MONOTONIC_TIMER)) +#define TRACK_CONSOLE_TIME (!ENV_SMM && CONFIG(HAVE_MONOTONIC_TIMER)) static struct mono_time mt_start, mt_stop; static long console_usecs; static void console_time_run(void) { - if (TRACK_CONSOLE_TIME) + if (TRACK_CONSOLE_TIME && boot_cpu()) timer_monotonic_get(&mt_start); } static void console_time_stop(void) { - if (TRACK_CONSOLE_TIME) { + if (TRACK_CONSOLE_TIME && boot_cpu()) { timer_monotonic_get(&mt_stop); console_usecs += mono_time_diff_microseconds(&mt_start, &mt_stop); } From 2ab4f4b2c5adddc0d98654b1d268227d4c7457ba Mon Sep 17 00:00:00 2001 From: Wim Vervoorn Date: Wed, 23 Oct 2019 10:22:06 +0200 Subject: [PATCH 0570/1242] soc/intel/skylake: Add option to control microcode update inclusion On embedded boards the cpu mounted on the board is known. So it is not required to include microcode for all possible Sky Lake and Kaby Lake cpus. This patch provides the possibility to only support the versions required. By default all microcode updates will be included and the versions not required can be removed using Kconfig. BUG=N/A TEST=build Change-Id: Iaa36c2846b2279a2eb2b61e6c97d6c89d0736f55 Signed-off-by: Wim Vervoorn Reviewed-on: https://review.coreboot.org/c/coreboot/+/37514 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Rudolph Reviewed-by: Paul Menzel Reviewed-by: Angel Pons Reviewed-by: Frans Hendriks --- src/soc/intel/skylake/Kconfig | 24 ++++++++++++++++++++++++ src/soc/intel/skylake/Makefile.inc | 10 ++++++++++ 2 files changed, 34 insertions(+) diff --git a/src/soc/intel/skylake/Kconfig b/src/soc/intel/skylake/Kconfig index 528fd4a0bf..31f809a475 100644 --- a/src/soc/intel/skylake/Kconfig +++ b/src/soc/intel/skylake/Kconfig @@ -288,4 +288,28 @@ config INTEL_TXT_BIOSACM_ALIGNMENT hex default 0x40000 # 256KB +config MAINBOARD_SUPPORTS_SKYLAKE_CPU + bool "Board can contain Skylake CPU" + default y + +if SKYLAKE_SOC_PCH_H + +config MAINBOARD_SUPPORTS_KABYLAKE_CPU + bool "Board can contain Kaby Lake CPU" + default y if SOC_INTEL_KABYLAKE + +endif + +if !SKYLAKE_SOC_PCH_H + +config MAINBOARD_SUPPORTS_KABYLAKE_DUAL + bool "Board can contain Kaby Lake DUAL core" + default y + +config MAINBOARD_SUPPORTS_KABYLAKE_QUAD + bool "Board can contain Kaby Lake QUAD core" + default y + +endif + endif diff --git a/src/soc/intel/skylake/Makefile.inc b/src/soc/intel/skylake/Makefile.inc index c0937385f0..75121abe0d 100644 --- a/src/soc/intel/skylake/Makefile.inc +++ b/src/soc/intel/skylake/Makefile.inc @@ -79,18 +79,28 @@ postcar-y += i2c.c postcar-y += uart.c ifeq ($(CONFIG_SKYLAKE_SOC_PCH_H),y) +ifeq ($(CONFIG_MAINBOARD_SUPPORTS_SKYLAKE_CPU),y) # Skylake H Q0 cpu_microcode_bins += 3rdparty/intel-microcode/intel-ucode/06-5e-03 +endif +ifeq ($(CONFIG_MAINBOARD_SUPPORTS_KABYLAKE_CPU),y) # Kabylake H B0 S0 cpu_microcode_bins += 3rdparty/intel-microcode/intel-ucode/06-9e-09 +endif else +ifeq ($(CONFIG_MAINBOARD_SUPPORTS_SKYLAKE_CPU),y) # Skylake D0 cpu_microcode_bins += 3rdparty/intel-microcode/intel-ucode/06-4e-03 +endif +ifeq ($(CONFIG_MAINBOARD_SUPPORTS_KABYLAKE_DUAL),y) # Kabylake H0, J0, J1 cpu_microcode_bins += 3rdparty/intel-microcode/intel-ucode/06-8e-09 +endif +ifeq ($(CONFIG_MAINBOARD_SUPPORTS_KABYLAKE_QUAD),y) # Kabylake Y0 cpu_microcode_bins += 3rdparty/intel-microcode/intel-ucode/06-8e-0a endif +endif # Missing for Skylake C0 (0x406e2), Kabylake G0 (0x406e8), Kabylake HA0 (0x506e8) # since those are probably pre-release samples. From cbc878d2a20549030deaecdecc37ff5b9dcb3272 Mon Sep 17 00:00:00 2001 From: Wim Vervoorn Date: Thu, 28 Nov 2019 14:45:12 +0100 Subject: [PATCH 0571/1242] drivers/intel/fsp2_0: Add logo support Add support for the FSP feature to display the logo. BUG=N/A TEST=tested on facebook monolith Change-Id: Iaaffd2be567861371bbe908c1ef9d7dde483a945 Signed-off-by: Wim Vervoorn Reviewed-on: https://review.coreboot.org/c/coreboot/+/37515 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Rudolph Reviewed-by: Frans Hendriks Reviewed-by: Angel Pons --- src/drivers/intel/fsp2_0/Kconfig | 14 +++++++++++ src/drivers/intel/fsp2_0/Makefile.inc | 7 ++++++ src/drivers/intel/fsp2_0/include/fsp/api.h | 3 +++ src/drivers/intel/fsp2_0/logo.c | 27 ++++++++++++++++++++++ src/drivers/intel/fsp2_0/silicon_init.c | 13 +++++++++++ 5 files changed, 64 insertions(+) create mode 100644 src/drivers/intel/fsp2_0/logo.c diff --git a/src/drivers/intel/fsp2_0/Kconfig b/src/drivers/intel/fsp2_0/Kconfig index 77382d3674..d9d7fb2060 100644 --- a/src/drivers/intel/fsp2_0/Kconfig +++ b/src/drivers/intel/fsp2_0/Kconfig @@ -156,6 +156,20 @@ config FSP_PEIM_TO_PEIM_INTERFACE is limited till EFI_PEI_MP_SERVICE_PPI and this option might be useful to add further PPI if required. +config FSP2_0_DISPLAY_LOGO + bool "Enable logo" + default n + depends on HAVE_FSP_GOP + help + Uses the FSP to display the boot logo. This method supports a + BMP file only. The uncompressed size can be up to 1 MB. The logo can be compressed + using LZMA. + +config FSP2_0_LOGO_FILE_NAME + string "Logo file" + depends on FSP2_0_DISPLAY_LOGO + default "3rdparty/blobs/mainboard/$(MAINBOARDDIR)/logo.bmp" + if FSP_PEIM_TO_PEIM_INTERFACE source "src/drivers/intel/fsp2_0/ppi/Kconfig" endif diff --git a/src/drivers/intel/fsp2_0/Makefile.inc b/src/drivers/intel/fsp2_0/Makefile.inc index bc00cd42c8..8658062348 100644 --- a/src/drivers/intel/fsp2_0/Makefile.inc +++ b/src/drivers/intel/fsp2_0/Makefile.inc @@ -30,6 +30,7 @@ ramstage-y += hand_off_block.c ramstage-$(CONFIG_DISPLAY_FSP_HEADER) += header_display.c ramstage-$(CONFIG_DISPLAY_HOBS) += hob_display.c ramstage-$(CONFIG_VERIFY_HOBS) += hob_verify.c +ramstage-$(CONFIG_FSP2_0_DISPLAY_LOGO) += logo.c ramstage-y += notify.c ramstage-y += silicon_init.c ramstage-$(CONFIG_DISPLAY_UPD_DATA) += upd_display.c @@ -78,6 +79,12 @@ $(obj)/Fsp_T.fd: $(call strip_quotes,$(CONFIG_FSP_FD_PATH)) $(obj)/Fsp_M.fd true endif +# Add logo to the cbfs image +cbfs-files-$(CONFIG_FSP2_0_DISPLAY_LOGO) += logo.bmp +logo.bmp-file := $(call strip_quotes,$(CONFIG_FSP2_0_LOGO_FILE_NAME)) +logo.bmp-type := raw +logo.bmp-compression := LZMA + ifneq ($(call strip_quotes,$(CONFIG_FSP_HEADER_PATH)),) CPPFLAGS_common+=-I$(CONFIG_FSP_HEADER_PATH) endif diff --git a/src/drivers/intel/fsp2_0/include/fsp/api.h b/src/drivers/intel/fsp2_0/include/fsp/api.h index b63cd046de..fb42c7647b 100644 --- a/src/drivers/intel/fsp2_0/include/fsp/api.h +++ b/src/drivers/intel/fsp2_0/include/fsp/api.h @@ -69,6 +69,9 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd); uint8_t fsp_memory_mainboard_version(void); uint8_t fsp_memory_soc_version(void); +/* Load logo to be displayed by FSP */ +void load_logo(FSPS_UPD *supd); + /* Callback after processing FSP notify */ void platform_fsp_notify_status(enum fsp_notify_phase phase); diff --git a/src/drivers/intel/fsp2_0/logo.c b/src/drivers/intel/fsp2_0/logo.c new file mode 100644 index 0000000000..feeec3b995 --- /dev/null +++ b/src/drivers/intel/fsp2_0/logo.c @@ -0,0 +1,27 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include +#include + +void load_logo(FSPS_UPD *supd) +{ + FSP_S_CONFIG *params = &supd->FspsConfig; + + params->LogoSize = cbfs_boot_load_file("logo.bmp", (void *)params->LogoPtr, + params->LogoSize, CBFS_TYPE_RAW); + if (!params->LogoSize) + params->LogoPtr = 0; +} diff --git a/src/drivers/intel/fsp2_0/silicon_init.c b/src/drivers/intel/fsp2_0/silicon_init.c index f58851d8c0..ebdbdbf2e6 100644 --- a/src/drivers/intel/fsp2_0/silicon_init.c +++ b/src/drivers/intel/fsp2_0/silicon_init.c @@ -34,6 +34,7 @@ static void do_silicon_init(struct fsp_header *hdr) fsp_silicon_init_fn silicon_init; uint32_t status; uint8_t postcode; + const struct cbmem_entry *logo_entry; supd = (FSPS_UPD *) (hdr->cfg_region_offset + hdr->image_base); @@ -56,6 +57,15 @@ static void do_silicon_init(struct fsp_header *hdr) /* Give SoC/mainboard a chance to populate entries */ platform_fsp_silicon_init_params_cb(upd); +#if (CONFIG(HAVE_FSP_GOP)) + if (CONFIG(FSP2_0_DISPLAY_LOGO)) { + upd->FspsConfig.LogoSize = 1 * MiB; + logo_entry = cbmem_entry_add(CBMEM_ID_FSP_LOGO, upd->FspsConfig.LogoSize); + upd->FspsConfig.LogoPtr = (UINT32)cbmem_entry_start(logo_entry); + load_logo(upd); + } +#endif + /* Call SiliconInit */ silicon_init = (void *) (hdr->image_base + hdr->silicon_init_entry_offset); @@ -67,6 +77,9 @@ static void do_silicon_init(struct fsp_header *hdr) timestamp_add_now(TS_FSP_SILICON_INIT_END); post_code(POST_FSP_SILICON_EXIT); + if (CONFIG(FSP2_0_DISPLAY_LOGO)) + cbmem_entry_remove(logo_entry); + fsp_debug_after_silicon_init(status); /* Handle any errors returned by FspSiliconInit */ From 7c04acff8a58b7350fc669e2a0a71f3a308f8c09 Mon Sep 17 00:00:00 2001 From: Wim Vervoorn Date: Thu, 5 Dec 2019 13:45:41 +0100 Subject: [PATCH 0572/1242] mb/facebook/monolith: Add Facebook Monolith The board is booting Linux and has been briefly tested. SeaBIOS, TianoCore payload and Linux as payload all seem to work fine. BUG=N/A TEST=tested on Facebook Monolith Change-Id: I65a2e03334af65cfb3f825d43fa0daa6e6c75913 Signed-off-by: Wim Vervoorn Reviewed-on: https://review.coreboot.org/c/coreboot/+/37516 Tested-by: build bot (Jenkins) Reviewed-by: Frans Hendriks --- Documentation/mainboard/facebook/monolith.md | 78 ++++++ Documentation/mainboard/index.md | 1 + src/mainboard/facebook/monolith/Kconfig | 90 +++++++ src/mainboard/facebook/monolith/Kconfig.name | 2 + src/mainboard/facebook/monolith/Makefile.inc | 23 ++ src/mainboard/facebook/monolith/acpi/dptf.asl | 53 ++++ src/mainboard/facebook/monolith/acpi/ec.asl | 0 .../facebook/monolith/acpi/mainboard.asl | 42 +++ .../facebook/monolith/acpi/superio.asl | 45 ++++ src/mainboard/facebook/monolith/acpi_tables.c | 0 .../facebook/monolith/board_info.txt | 6 + src/mainboard/facebook/monolith/cmos.layout | 121 +++++++++ src/mainboard/facebook/monolith/com_init.c | 29 ++ src/mainboard/facebook/monolith/data.vbt | Bin 0 -> 4608 bytes src/mainboard/facebook/monolith/devicetree.cb | 247 ++++++++++++++++++ src/mainboard/facebook/monolith/dsdt.asl | 54 ++++ src/mainboard/facebook/monolith/gpio.h | 207 +++++++++++++++ src/mainboard/facebook/monolith/mainboard.c | 50 ++++ src/mainboard/facebook/monolith/onboard.h | 24 ++ src/mainboard/facebook/monolith/ramstage.c | 26 ++ src/mainboard/facebook/monolith/romstage.c | 41 +++ .../facebook/monolith/spd/Makefile.inc | 18 ++ src/mainboard/facebook/monolith/spd/spd.h | 26 ++ .../facebook/monolith/spd/spd_util.c | 56 ++++ src/mainboard/facebook/monolith/vboot-rw.fmd | 28 ++ 25 files changed, 1267 insertions(+) create mode 100644 Documentation/mainboard/facebook/monolith.md create mode 100644 src/mainboard/facebook/monolith/Kconfig create mode 100644 src/mainboard/facebook/monolith/Kconfig.name create mode 100644 src/mainboard/facebook/monolith/Makefile.inc create mode 100644 src/mainboard/facebook/monolith/acpi/dptf.asl create mode 100644 src/mainboard/facebook/monolith/acpi/ec.asl create mode 100644 src/mainboard/facebook/monolith/acpi/mainboard.asl create mode 100644 src/mainboard/facebook/monolith/acpi/superio.asl create mode 100644 src/mainboard/facebook/monolith/acpi_tables.c create mode 100644 src/mainboard/facebook/monolith/board_info.txt create mode 100644 src/mainboard/facebook/monolith/cmos.layout create mode 100644 src/mainboard/facebook/monolith/com_init.c create mode 100644 src/mainboard/facebook/monolith/data.vbt create mode 100644 src/mainboard/facebook/monolith/devicetree.cb create mode 100644 src/mainboard/facebook/monolith/dsdt.asl create mode 100644 src/mainboard/facebook/monolith/gpio.h create mode 100644 src/mainboard/facebook/monolith/mainboard.c create mode 100644 src/mainboard/facebook/monolith/onboard.h create mode 100644 src/mainboard/facebook/monolith/ramstage.c create mode 100644 src/mainboard/facebook/monolith/romstage.c create mode 100644 src/mainboard/facebook/monolith/spd/Makefile.inc create mode 100644 src/mainboard/facebook/monolith/spd/spd.h create mode 100644 src/mainboard/facebook/monolith/spd/spd_util.c create mode 100644 src/mainboard/facebook/monolith/vboot-rw.fmd diff --git a/Documentation/mainboard/facebook/monolith.md b/Documentation/mainboard/facebook/monolith.md new file mode 100644 index 0000000000..9b9f33b29f --- /dev/null +++ b/Documentation/mainboard/facebook/monolith.md @@ -0,0 +1,78 @@ +# Facebook Monolith + +This page describes how to run coreboot on the Facebook Monolith. + +Please note: the coreboot implementation for this boards is in it's Alpha state and isn't fully +tested yet. + +## Required blobs + +This board currently requires: +fsp blobs 3rdparty/fsp/KabylakeFspBinPkg/Fsp_M.fd + 3rdparty/fsp/KabylakeFspBinPkg/Fsp_S.fd + +Microcode 3rdparty/intel-microcode/intel-ucode + +## Flashing coreboot + +### Internal programming + +The SPI flash can be accessed using [flashrom]. + +### External programming + +The system has an internal flash chip which is a 16 MiB soldered SOIC-8 chip. +Specifically, it's a Winbond W25Q128JVSIQ (3.3V). + +The system has an external flash chip which is a 16 MiB soldered SOIC-8 chip. +Specifically, it's a Winbond W25Q128JVSIM (3.3V). + +Flashing of these devices is very difficult, disassembling the system destroys the cooling +solution. Wires need to be connected to be able to flash using an external programmer. + +## Known issues + +- None + +## Untested + +- Hardware monitor +- SDIO +- Full Embedded Controller support +- eMMC +- SATA + +## Working + +- USB +- Gigabit Ethernet +- Graphics (Using FSP GOP) +- flashrom +- PCIe +- EC serial port +- SMBus +- Initialization with FSP +- SeaBIOS payload (commit a5cab58e9a3fb6e168aba919c5669bea406573b4) +- TianoCore payload (commit a5cab58e9a3fb6e168aba919c5669bea406573b4) + +All of the above has been briefly tested by booting Linux from the TianoCore payload. +SeaBios has been checked to the extend that it runs to the boot selection and provides display +output. + +## Technology + +```eval_rst ++------------------+--------------------------------------------------+ +| SoC | Intel Kaby Lake U | ++------------------+--------------------------------------------------+ +| CPU | Intel i3-7100U | ++------------------+--------------------------------------------------+ +| Super I/O, EC | ITE8256 | ++------------------+--------------------------------------------------+ +| Coprocessor | Intel Management Engine | ++------------------+--------------------------------------------------+ +``` + +[W25Q128JVSIQ]: https://www.winbond.com/resource-files/w25q128jv%20revf%2003272018%20plus.pdf +[W25Q128JVSIM]: https://www.winbond.com/resource-files/w25q128jv%20dtr%20revb%2011042016.pdf +[flashrom]: https://flashrom.org/Flashrom diff --git a/Documentation/mainboard/index.md b/Documentation/mainboard/index.md index 60302cbe0f..038689d192 100644 --- a/Documentation/mainboard/index.md +++ b/Documentation/mainboard/index.md @@ -32,6 +32,7 @@ The boards in this section are not real mainboards, but emulators. ## Facebook - [FBG-1701](facebook/fbg1701.md) +- [Monolith](facebook/monolith.md) ## Foxconn diff --git a/src/mainboard/facebook/monolith/Kconfig b/src/mainboard/facebook/monolith/Kconfig new file mode 100644 index 0000000000..32616618ce --- /dev/null +++ b/src/mainboard/facebook/monolith/Kconfig @@ -0,0 +1,90 @@ +if BOARD_FACEBOOK_MONOLITH + +config BOARD_SPECIFIC_OPTIONS + def_bool y + select BOARD_ROMSIZE_KB_16384 + select HAVE_ACPI_RESUME + select HAVE_ACPI_TABLES + select HAVE_OPTION_TABLE + select SOC_INTEL_KABYLAKE + select MAINBOARD_HAS_LPC_TPM + select MAINBOARD_HAS_TPM2 + select MAINBOARD_USES_IFD_GBE_REGION + select INTEL_GMA_HAVE_VBT + +config CBFS_SIZE + hex "CBFS_SIZE" + default 0x00900000 + +config IRQ_SLOT_COUNT + int + default 18 + +config MAINBOARD_DIR + string + default "facebook/monolith" + +config MAINBOARD_PART_NUMBER + string + default "Monolith" + +config MAINBOARD_FAMILY + string + default "Facebook Monolith" + +config MAX_CPUS + int + default 4 + +config IFD_BIN_PATH + string + depends on HAVE_IFD_BIN + default "3rdparty/blobs/mainboard/$(MAINBOARDDIR)/descriptor.bin" + +config ME_BIN_PATH + string + depends on HAVE_ME_BIN + default "3rdparty/blobs/mainboard/$(MAINBOARDDIR)/me.bin" + +config GBE_BIN_PATH + string + depends on HAVE_GBE_BIN + default "3rdparty/blobs/mainboard/$(MAINBOARDDIR)/gbe.bin" + +config PRERAM_CBMEM_CONSOLE_SIZE + hex + default 0xd00 + +config DIMM_SPD_SIZE + int + default 512 #DDR4 + +config UART_FOR_CONSOLE + int + default 0 + +config DIMM_MAX + int + default 2 + +config TPM_INIT + bool + default n + +config MAINBOARD_SUPPORTS_SKYLAKE_CPU + bool + default n + +config MAINBOARD_SUPPORTS_KABYLAKE_QUAD + bool + default n + +config RW_REGION_ONLY + string "Files in RW only" + +config VBOOT_ENABLE_CBFS_FALLBACK + bool + default y + depends on VBOOT + +endif diff --git a/src/mainboard/facebook/monolith/Kconfig.name b/src/mainboard/facebook/monolith/Kconfig.name new file mode 100644 index 0000000000..865aa2f0f7 --- /dev/null +++ b/src/mainboard/facebook/monolith/Kconfig.name @@ -0,0 +1,2 @@ +config BOARD_FACEBOOK_MONOLITH + bool "Facebook Monolith" diff --git a/src/mainboard/facebook/monolith/Makefile.inc b/src/mainboard/facebook/monolith/Makefile.inc new file mode 100644 index 0000000000..0cccd26f71 --- /dev/null +++ b/src/mainboard/facebook/monolith/Makefile.inc @@ -0,0 +1,23 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2013 Google Inc. +## Copyright (C) 2016 Intel Corporation. +## Copyright (C) 2019 Eltan B.V. +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +subdirs-y += spd + +bootblock-y += com_init.c + +ramstage-y += mainboard.c +ramstage-y += ramstage.c diff --git a/src/mainboard/facebook/monolith/acpi/dptf.asl b/src/mainboard/facebook/monolith/acpi/dptf.asl new file mode 100644 index 0000000000..5ea95b41d0 --- /dev/null +++ b/src/mainboard/facebook/monolith/acpi/dptf.asl @@ -0,0 +1,53 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2014 Google Inc. + * Copyright (C) 2015 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#define DPTF_CPU_PASSIVE 80 +#define DPTF_CPU_CRITICAL 90 +#define DPTF_CPU_ACTIVE_AC0 90 +#define DPTF_CPU_ACTIVE_AC1 80 +#define DPTF_CPU_ACTIVE_AC2 70 +#define DPTF_CPU_ACTIVE_AC3 60 +#define DPTF_CPU_ACTIVE_AC4 50 + +Name (DTRT, Package () { + /* CPU Throttle Effect on CPU */ + Package () { \_SB.PCI0.B0D4, \_SB.PCI0.B0D4, 100, 50, 0, 0, 0, 0 }, + +}) + +Name (MPPC, Package () +{ + 0x2, /* Revision */ + Package () { /* Power Limit 1 */ + 0, /* PowerLimitIndex, 0 for Power Limit 1 */ + 1600, /* PowerLimitMinimum */ + 15000, /* PowerLimitMaximum */ + 1000, /* TimeWindowMinimum */ + 1000, /* TimeWindowMaximum */ + 200 /* StepSize */ + }, + Package () { /* Power Limit 2 */ + 1, /* PowerLimitIndex, 1 for Power Limit 2 */ + 8000, /* PowerLimitMinimum */ + 8000, /* PowerLimitMaximum */ + 1000, /* TimeWindowMinimum */ + 1000, /* TimeWindowMaximum */ + 1000 /* StepSize */ + } +}) + +/* Include DPTF */ +#include diff --git a/src/mainboard/facebook/monolith/acpi/ec.asl b/src/mainboard/facebook/monolith/acpi/ec.asl new file mode 100644 index 0000000000..e69de29bb2 diff --git a/src/mainboard/facebook/monolith/acpi/mainboard.asl b/src/mainboard/facebook/monolith/acpi/mainboard.asl new file mode 100644 index 0000000000..2a3ad59b9f --- /dev/null +++ b/src/mainboard/facebook/monolith/acpi/mainboard.asl @@ -0,0 +1,42 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2014 Google Inc. + * Copyright (C) 2016 Intel Corporation. + * Copyright (C) 2018-2019 Eltan B.V. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +Scope (\_SB) +{ + Device (PWRB) + { + Name (_HID, EisaId ("PNP0C0C")) + Name (_UID, 1) + } +} + +/* + * Onboard CPLD + */ +Scope (\_SB.PCI0.LPCB) +{ + Device (CPLD) /* Onboard CPLD */ + { + Name(_HID, EISAID("PNP0C01")) + Name(_CRS, ResourceTemplate() + { + /* Reserve 0x280 to 0x2BF for the CPLD */ + FixedIO (0x0280, 0x40) + IRQNoFlags () {7} + }) + } +} diff --git a/src/mainboard/facebook/monolith/acpi/superio.asl b/src/mainboard/facebook/monolith/acpi/superio.asl new file mode 100644 index 0000000000..0f5790da8d --- /dev/null +++ b/src/mainboard/facebook/monolith/acpi/superio.asl @@ -0,0 +1,45 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Google Inc. + * Copyright (C) 2015 Intel Corp. + * Copyright (C) 2018-2019 Eltan B.V. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* mainboard configuration */ + +Device (COM1) { + Name (_HID, EISAID ("PNP0501")) + Name (_UID, 1) + + Method (_STA, 0, NotSerialized) + { + Return (0x0F) + } + + Name (_CRS, ResourceTemplate () + { + FixedIO (0x03F8, 0x08) + FixedIO (0x6E, 0x02) + IRQNoFlags () {4} + }) + + Name (_PRS, ResourceTemplate () + { + StartDependentFn (0, 0) { + FixedIO (0x03F8, 0x08) + FixedIO (0x6E, 0x02) + IRQNoFlags () {4} + } + EndDependentFn () + }) +} diff --git a/src/mainboard/facebook/monolith/acpi_tables.c b/src/mainboard/facebook/monolith/acpi_tables.c new file mode 100644 index 0000000000..e69de29bb2 diff --git a/src/mainboard/facebook/monolith/board_info.txt b/src/mainboard/facebook/monolith/board_info.txt new file mode 100644 index 0000000000..c58669ca68 --- /dev/null +++ b/src/mainboard/facebook/monolith/board_info.txt @@ -0,0 +1,6 @@ +Vendor name: Facebook +Board name: Monolith System +Category: misc +ROM protocol: SPI +ROM socketed: n +Flashrom support: y diff --git a/src/mainboard/facebook/monolith/cmos.layout b/src/mainboard/facebook/monolith/cmos.layout new file mode 100644 index 0000000000..04b2e15a3d --- /dev/null +++ b/src/mainboard/facebook/monolith/cmos.layout @@ -0,0 +1,121 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2007-2008 coresystems GmbH +## Copyright (C) 2016 Intel Corporation. +## Copyright (C) 2019 Eltan B.V. +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +# ----------------------------------------------------------------- +entries + +#start-bit length config config-ID name +#0 8 r 0 seconds +#8 8 r 0 alarm_seconds +#16 8 r 0 minutes +#24 8 r 0 alarm_minutes +#32 8 r 0 hours +#40 8 r 0 alarm_hours +#48 8 r 0 day_of_week +#56 8 r 0 day_of_month +#64 8 r 0 month +#72 8 r 0 year +# ----------------------------------------------------------------- +# Status Register A +#80 4 r 0 rate_select +#84 3 r 0 REF_Clock +#87 1 r 0 UIP +# ----------------------------------------------------------------- +# Status Register B +#88 1 r 0 auto_switch_DST +#89 1 r 0 24_hour_mode +#90 1 r 0 binary_values_enable +#91 1 r 0 square-wave_out_enable +#92 1 r 0 update_finished_enable +#93 1 r 0 alarm_interrupt_enable +#94 1 r 0 periodic_interrupt_enable +#95 1 r 0 disable_clock_updates +# ----------------------------------------------------------------- +# Status Register C +#96 4 r 0 status_c_rsvd +#100 1 r 0 uf_flag +#101 1 r 0 af_flag +#102 1 r 0 pf_flag +#103 1 r 0 irqf_flag +# ----------------------------------------------------------------- +# Status Register D +#104 7 r 0 status_d_rsvd +#111 1 r 0 valid_cmos_ram +# ----------------------------------------------------------------- +# Diagnostic Status Register +#112 8 r 0 diag_rsvd1 + +# ----------------------------------------------------------------- +0 120 r 0 reserved_memory +#120 264 r 0 unused + +# ----------------------------------------------------------------- +# RTC_BOOT_BYTE (coreboot hardcoded) +384 1 e 4 boot_option +# reboot_counter reserved for core, not used by platform. +388 4 h 0 reboot_counter +#390 2 r 0 unused + +# ----------------------------------------------------------------- +# coreboot config options: console +#392 3 r 0 unused +395 4 e 6 debug_level +#399 1 r 0 unused + +# coreboot config options: cpu +#400 1 e 2 unused +#401 7 r 0 unused + +# coreboot config options: southbridge +408 1 e 1 nmi +409 2 e 7 power_on_after_fail +#411 5 r 0 unused + +# coreboot config options: bootloader +#416 568 r 0 unused + +# coreboot config options: check sums +984 16 h 0 check_sum +#1000 24 r 0 amd_reserved + +# ----------------------------------------------------------------- + +enumerations + +#ID value text +1 0 Disable +1 1 Enable +2 0 Enable +2 1 Disable +4 0 Fallback +4 1 Normal +6 0 Emergency +6 1 Alert +6 2 Critical +6 3 Error +6 4 Warning +6 5 Notice +6 6 Info +6 7 Debug +6 8 Spew +7 0 Disable +7 1 Enable +7 2 Keep +# ----------------------------------------------------------------- +checksums + +checksum 392 415 984 diff --git a/src/mainboard/facebook/monolith/com_init.c b/src/mainboard/facebook/monolith/com_init.c new file mode 100644 index 0000000000..f19aba311c --- /dev/null +++ b/src/mainboard/facebook/monolith/com_init.c @@ -0,0 +1,29 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Google Inc. + * Copyright (C) 2015 Intel Corp. + * Copyright (C) 2018-2019 Eltan B.V. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include "onboard.h" + +#define SERIAL_DEV PNP_DEV(ITE8528_CMD_PORT, 1) /* ITE8528 UART1 */ + +void bootblock_mainboard_early_init(void) +{ + /* Enable the serial port inside the EC */ + pnp_set_logical_device(SERIAL_DEV); + pnp_set_enable(SERIAL_DEV, 1); +} diff --git a/src/mainboard/facebook/monolith/data.vbt b/src/mainboard/facebook/monolith/data.vbt new file mode 100644 index 0000000000000000000000000000000000000000..d2c3e6c84e8b116a9bc8a8594c8a991ac99f458d GIT binary patch literal 4608 zcmeHKZ){Ul6hE)8fA4#*eSIU)Rh)-ELO0p=I$+>3!t2_Nl@;2qW7(p~I%w6!!p1ht zP!dXF-A6OOkoeJ_7riNgJbES~hP%jJCGXpBmjtU9}_H-m&#bi6y$@={=cb zDmIWz@5OXKCX%^WF4w)MD>aOn{&a7$D>=}ekl3Od@$reHlVi_5H;s{aBeu~R%_gX6 zGRDUzCt5I8Dq+8&Gll)dsp8}d#X^h343M+nb#efl3j!K&aIFo%se$HPga<%y%Ag@= zGN24zQUK75X^;&q85}z}2hDBtf;(i)ED*u-W?wUuZ6Y+dkOx`z{z*^r8yN9K?- zJJir}wwlvt%{k14jXsCew+KnmLR)F8k#L*OR1U4xX@s_^GDK`O!3F@lL2Y67o=Tp) zzWO39Nzxz=ID-KEoC=404Upy|aEy1rtNeCoa-IX(hp^cvLl5yV@%JtU7m0r+{)6~$ zVwamifViG`9dR@9HsTm@AMrlo5#ljo_Yt_NJIcmR5S2Mw1}zD)6W(lu@@aeiv_0?p z-O3VXOTm^VNDYmydpvMm|271=?%iQnpb-MO%_VH4UR$P2$@3X|JV4Tj)sQ{bbzh!_ z4*K1_mVFJ2hfddNA(I}|o>&LF=_K;r&RJ_0_W|f1Nj%H|3)%;h98|=Gq%^%<@gcaw zmgAmIOD=8y%O_zY10MO+ao)q=yypscvhM!u8Bvp$`B{;zCYUvT*glNFjS*Pg3m1Il z3SN3t_U6}G&l>J*=CP+KCmmjTF=$}inIiN;1VWI2^{@i+kTL5gulb(6!HC+X5Fub3 z(A!WXOyE;X6y}Kl8s7#!&Txz=FEREC!%vvF4%F6f3SQAmJC1@`J>FlF;Q>R{7Z)Kko7?!+v(aFEuHyvf~n04*Jc4$2%#~yJyHD zn(_)KlXL|((k-`iQ`(QyWp8*ZB0uC<9$_wk5FJ{Lk@5;FMh)%9t!t0=ieBf-BNXaE zi@^ppbh6z-2(=&QtvZd&1gC+}Nrls`y-=IrR2EcCov2&1f&S6xi!-ipO$alX4a=JR zF9fb)7J)S)eB3&7DI4CP4V|jmz*Wq`Pt@FJYOtYqr>5>d)23->s|aqZ0ul#ZwM6on zHG}h6Xi$49_Ffo~teAHvnNmv}jRwdLIz^mw&DM|)?>Ek!&(5w@Gw-chMBu?Jk13M1AgE2+x%_NF4P~uL0>}%V($UC= zJIqNFL9!5BSc4ar!!Vb@RjR1Qt6o&-JdzD%&vr8(j3mExRy#V%p~KsowV~$fUhojG zY@jcj<A~n)!Cv_AxaV@S{o#DOJ-<($ F{R2-b$sYg! literal 0 HcmV?d00001 diff --git a/src/mainboard/facebook/monolith/devicetree.cb b/src/mainboard/facebook/monolith/devicetree.cb new file mode 100644 index 0000000000..b5e3191fcb --- /dev/null +++ b/src/mainboard/facebook/monolith/devicetree.cb @@ -0,0 +1,247 @@ +chip soc/intel/skylake + + # Enable deep Sx states + register "deep_s5_enable_ac" = "0" + register "deep_s5_enable_dc" = "0" + register "deep_sx_config" = "DSX_EN_LAN_WAKE_PIN" + + # GPE configuration + # Note that GPE events called out in ASL code rely on this + # route. i.e. If this route changes then the affected GPE + # offset bits also need to be changed. + register "gpe0_dw0" = "GPP_C" + register "gpe0_dw1" = "GPP_D" + register "gpe0_dw2" = "GPP_E" + + # CPLD host command ranges are in 0x280-0x2BF + # EC PNP registers are at 0x6e and 0x6f + register "gen1_dec" = "0x003c0281" + register "gen3_dec" = "0x0004006d" + + # LPC serial IRQ + register "serirq_mode" = "SERIRQ_CONTINUOUS" + + # Enable "Intel Speed Shift Technology" + register "speed_shift_enable" = "1" + + # Enable DPTF + register "dptf_enable" = "0" + + # FSP Configuration + register "EnableAzalia" = "0" + register "SmbusEnable" = "1" + register "ScsEmmcEnabled" = "1" + register "ScsEmmcHs400Enabled" = "1" + register "SkipExtGfxScan" = "1" + register "Device4Enable" = "1" + register "SaGv" = "SaGv_Enabled" + register "SaImguEnable" = "0" + register "Cio2Enable" = "0" + register "PmTimerDisabled" = "1" + register "HeciEnabled" = "0" + register "EnableLan" = "1" + + register "EnableSata" = "1" + register "SataSalpSupport" = "1" + register "SataPortsEnable" = "{ \ + [0] = 1, \ + [1] = 0, \ + [2] = 0, \ + [3] = 0, \ + [4] = 0, \ + [5] = 0, \ + [6] = 0, \ + [7] = 0, \ + }" + + register "pirqa_routing" = "PCH_IRQ11" + register "pirqb_routing" = "PCH_IRQ10" + register "pirqc_routing" = "PCH_IRQ11" + register "pirqd_routing" = "PCH_IRQ11" + register "pirqe_routing" = "PCH_IRQ11" + register "pirqf_routing" = "PCH_IRQ11" + register "pirqg_routing" = "PCH_IRQ11" + register "pirqh_routing" = "PCH_IRQ11" + + # Enabling SLP_S3#, SLP_S4#, SLP_SUS and SLP_A Stretch + # SLP_S3 Minimum Assertion Width. Values 0: 60us, 1: 1ms, 2: 50ms, 3: 2s + register "PmConfigSlpS3MinAssert" = "2" + + # SLP_S4 Minimum Assertion Width. Values 0: default, 1: 1s, 2: 2s, 3: 3s, 4: 4s + register "PmConfigSlpS4MinAssert" = "4" + + # SLP_SUS Minimum Assertion Width. Values 0: 0ms, 1: 500ms, 2: 1s, 3: 4s + register "PmConfigSlpSusMinAssert" = "3" + + # SLP_A Minimum Assertion Width. Values 0: 0ms, 1: 4s, 2: 98ms, 3: 2s + register "PmConfigSlpAMinAssert" = "3" + + # VR Settings Configuration for 4 Domains + #+----------------+-------+-------+-------+-------+ + #| Domain/Setting | SA | IA | GTUS | GTS | + #+----------------+-------+-------+-------+-------+ + #| Psi1Threshold | 20A | 20A | 20A | 20A | + #| Psi2Threshold | 5A | 5A | 5A | 5A | + #| Psi3Threshold | 1A | 1A | 1A | 1A | + #| Psi3Enable | 1 | 1 | 1 | 1 | + #| Psi4Enable | 1 | 1 | 1 | 1 | + #| ImonSlope | 0 | 0 | 0 | 0 | + #| ImonOffset | 0 | 0 | 0 | 0 | + #| IccMax | 7A | 34A | 35A | 35A | + #| VrVoltageLimit | 1.52V | 1.52V | 1.52V | 1.52V | + #+----------------+-------+-------+-------+-------+ + register "domain_vr_config[VR_SYSTEM_AGENT]" = "{ + .vr_config_enable = 1, \ + .psi1threshold = VR_CFG_AMP(20), \ + .psi2threshold = VR_CFG_AMP(5), \ + .psi3threshold = VR_CFG_AMP(1), \ + .psi3enable = 1, \ + .psi4enable = 1, \ + .imon_slope = 0, \ + .imon_offset = 0, \ + .icc_max = VR_CFG_AMP(7), \ + .voltage_limit = 1520 \ + }" + + register "domain_vr_config[VR_IA_CORE]" = "{ + .vr_config_enable = 1, \ + .psi1threshold = VR_CFG_AMP(20), \ + .psi2threshold = VR_CFG_AMP(5), \ + .psi3threshold = VR_CFG_AMP(1), \ + .psi3enable = 1, \ + .psi4enable = 1, \ + .imon_slope = 0, \ + .imon_offset = 0, \ + .icc_max = VR_CFG_AMP(34), \ + .voltage_limit = 1520 \ + }" + + register "domain_vr_config[VR_GT_UNSLICED]" = "{ + .vr_config_enable = 1, \ + .psi1threshold = VR_CFG_AMP(20), \ + .psi2threshold = VR_CFG_AMP(5), \ + .psi3threshold = VR_CFG_AMP(1), \ + .psi3enable = 1, \ + .psi4enable = 1, \ + .imon_slope = 0, \ + .imon_offset = 0, \ + .icc_max = VR_CFG_AMP(35),\ + .voltage_limit = 1520 \ + }" + + register "domain_vr_config[VR_GT_SLICED]" = "{ + .vr_config_enable = 1, \ + .psi1threshold = VR_CFG_AMP(20), \ + .psi2threshold = VR_CFG_AMP(5), \ + .psi3threshold = VR_CFG_AMP(1), \ + .psi3enable = 1, \ + .psi4enable = 1, \ + .imon_slope = 0, \ + .imon_offset = 0, \ + .icc_max = VR_CFG_AMP(35), \ + .voltage_limit = 1520 \ + }" + + # Send an extra VR mailbox command for the PS4 exit issue + register "SendVrMbxCmd" = "2" + + # Enable Root ports. + # PCIE Port 1 disabled + # PCIE Port 2 disabled + + # PCIE Port 3 x1 -> Module x1 : Mapped to PCIe 2 on the baseboard + register "PcieRpEnable[2]" = "1" + # Disable CLKREQ# + register "PcieRpClkReqSupport[2]" = "0" + + # PCIE Port 4 disabled + # PCIE Port 5 x1 -> MODULE i219 + + # PCIE Port 6 x1 -> BASEBOARD x1 i210 : Mapped to PCIe 4 on the baseboard + register "PcieRpEnable[5]" = "1" + register "PcieRpClkReqSupport[5]" = "0" + + # PCIE Port 7 Disabled + # PCIE Port 8 Disabled + + # PCIE Port 9 x4 -> BASEBOARD PEG0-3 FPGA + register "PcieRpEnable[8]" = "1" + # Disable CLKREQ# + register "PcieRpClkReqSupport[8]" = "0" + # Use Hot Plug subsystem + register "PcieRpHotPlug[8]" = "1" + + # USB 2.0 Enable all ports + register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC_SKIP)" # USB-C Port 2 + register "usb2_ports[1]" = "USB2_PORT_MID(OC1)" # USB3_TYPE-A Port 1 + register "usb2_ports[2]" = "USB2_PORT_MID(OC1)" # USB3_TYPE-A Port 2 + register "usb2_ports[3]" = "USB2_PORT_TYPE_C(OC_SKIP)" # USB-C Port 1 + register "usb2_ports[4]" = "USB2_PORT_SHORT(OC_SKIP)" # M2 Port + register "usb2_ports[5]" = "USB2_PORT_EMPTY" # Disabled + register "usb2_ports[6]" = "USB2_PORT_SHORT(OC_SKIP)" # Audio board + register "usb2_ports[7]" = "USB2_PORT_EMPTY" # Disabled + register "usb2_ports[8]" = "USB2_PORT_EMPTY" # Disabled + register "usb2_ports[9]" = "USB2_PORT_EMPTY" # Disabled + register "usb2_ports[10]" = "USB2_PORT_EMPTY" # Disabled + register "usb2_ports[11]" = "USB2_PORT_EMPTY" # Disabled + + # USB 3.0 Enable Port 1-4. Port 5 & 6 Disabled + register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB-C Port 2 + register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB3_TYPE-A Port 1 + register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB3_TYPE-A Port 2 + register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB-C Port 1 + register "usb3_ports[4]" = "USB3_PORT_EMPTY" # Disabled + register "usb3_ports[5]" = "USB3_PORT_EMPTY" # Disabled + + register "SsicPortEnable" = "0" + + # Must leave UART0 enabled or SD/eMMC will not work as PCI + register "SerialIoDevMode" = "{ \ + [PchSerialIoIndexI2C0] = PchSerialIoDisabled, \ + [PchSerialIoIndexI2C1] = PchSerialIoDisabled, \ + [PchSerialIoIndexI2C2] = PchSerialIoDisabled, \ + [PchSerialIoIndexI2C3] = PchSerialIoDisabled, \ + [PchSerialIoIndexI2C4] = PchSerialIoDisabled, \ + [PchSerialIoIndexI2C5] = PchSerialIoDisabled, \ + [PchSerialIoIndexSpi0] = PchSerialIoDisabled, \ + [PchSerialIoIndexSpi1] = PchSerialIoDisabled, \ + [PchSerialIoIndexUart0] = PchSerialIoPci, \ + [PchSerialIoIndexUart1] = PchSerialIoDisabled, \ + [PchSerialIoIndexUart2] = PchSerialIoDisabled, \ + }" + + # Lock Down + register "common_soc_config" = "{ + .chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT, + }" + + device cpu_cluster 0 on + device lapic 0 on end + end + device domain 0 on + device pci 00.0 on end # Host Bridge + device pci 02.0 on end # Integrated Graphics Device + device pci 04.0 on end # + device pci 08.0 on end # Gaussian Mixture Model + device pci 14.0 on end # USB xHCI + device pci 14.1 on end # USB xDCI (OTG) + device pci 14.2 on end # Thermal Subsystem + device pci 17.0 on end # SATA + device pci 1c.2 on end # PCI Express Port 3 x1 baseboard WWAN + device pci 1c.5 on end # PCI Express Port 6 x1 baseboard i210 + device pci 1d.0 on end # PCI Express Port 9 x4 FPGA + device pci 1e.0 on end # UART #0 + device pci 1e.4 on end # eMMC + device pci 1e.5 off end # SDIO + device pci 1f.0 on # LPC Interface + chip drivers/pc80/tpm + device pnp 0c31.0 on end + end + end # LPC Bridge + device pci 1f.1 on end # P2SB + device pci 1f.2 on end # Power Management Controller + device pci 1f.4 on end # SMBus + device pci 1f.5 on end # PCH SPI + device pci 1f.6 on end # GbE + end +end diff --git a/src/mainboard/facebook/monolith/dsdt.asl b/src/mainboard/facebook/monolith/dsdt.asl new file mode 100644 index 0000000000..2f00110e8a --- /dev/null +++ b/src/mainboard/facebook/monolith/dsdt.asl @@ -0,0 +1,54 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * Copyright (C) 2015 Google Inc. + * Copyright (C) 2016 Intel Corporation + * Copyright (C) 2019 Eltan B.V. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +DefinitionBlock( + "dsdt.aml", + "DSDT", + 0x02, // DSDT revision: ACPI v2.0 and up + OEM_ID, + ACPI_TABLE_CREATOR, + 0x20110725 // OEM revision +) +{ + // Some generic macros + #include + + // global NVS and variables + #include + + // CPU + #include + + Scope (\_SB) { + Device (PCI0) + { + #include + #include + } + + // Dynamic Platform Thermal Framework + #include "acpi/dptf.asl" + } + + // Chipset specific sleep states + #include + + // Mainboard specific + #include "acpi/mainboard.asl" +} diff --git a/src/mainboard/facebook/monolith/gpio.h b/src/mainboard/facebook/monolith/gpio.h new file mode 100644 index 0000000000..65300fff6c --- /dev/null +++ b/src/mainboard/facebook/monolith/gpio.h @@ -0,0 +1,207 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Google Inc. + * Copyright (C) 2016 Intel Corporation + * Copyright (C) 2019 Eltan B.V. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the + * GNU General Public License for more details. + */ + +#ifndef MAINBOARD_GPIO_H +#define MAINBOARD_GPIO_H + +#include +#include + +/* EC wake is LAN_WAKE# which is a special DeepSX wake pin */ +#define GPE_EC_WAKE GPE0_LAN_WAK + +/* GPP_E16 is EC_SCI_L. GPP_E group is routed to DW2 in the GPE0 block */ +#define EC_SCI_GPI GPE0_DW2_16 +#define EC_SMI_GPI GPP_E15 + +#ifndef __ACPI__ +/* Pad configuration in ramstage. */ +static const struct pad_config gpio_table[] = { +/* PCH_RCIN */ PAD_CFG_NF(GPP_A0, NONE, DEEP, NF1), +/* LPC_LAD_0 */ PAD_CFG_NF(GPP_A1, 20K_PD, DEEP, NF1), +/* LPC_LAD_1 */ PAD_CFG_NF(GPP_A2, 20K_PD, DEEP, NF1), +/* LPC_LAD_2 */ PAD_CFG_NF(GPP_A3, 20K_PD, DEEP, NF1), +/* LPC_LAD_3 */ PAD_CFG_NF(GPP_A4, 20K_PD, DEEP, NF1), +/* LPC_FRAME */ PAD_CFG_NF(GPP_A5, NONE, DEEP, NF1), +/* LPC_SERIRQ */ PAD_CFG_NF(GPP_A6, NONE, DEEP, NF1), +/* PM_SLP_S0ix_N */ PAD_CFG_GPI_GPIO_DRIVER(GPP_A7, 20K_PU, DEEP), +///* PIRQA# */ PAD_CFG_NF(GPP_A7, NONE, DEEP, NF1), +/* LPC_CLKRUN */ PAD_CFG_NF(GPP_A8, NONE, DEEP, NF1), +/* LPC_CLK */ PAD_CFG_NF(GPP_A9, 20K_PD, DEEP, NF1), +/* PCH_LPC_CLK */ PAD_CFG_NF(GPP_A10, 20K_PD, DEEP, NF1), +/* SLEEP */ PAD_CFG_NC(GPP_A11), /* available on the module not used here */ +/* ISH_KB_PROX_INT */ PAD_CFG_NC(GPP_A12), +/* PCH_SUSPWRACB */ PAD_CFG_NF(GPP_A13, NONE, DEEP, NF1), +/* PM_SUS_STAT */ PAD_CFG_NF(GPP_A14, NONE, DEEP, NF1), +/* SUSACK_R_N */ PAD_CFG_NF(GPP_A15, 20K_PD, DEEP, NF1), +/* SD_1P8_SEL */ PAD_CFG_NF(GPP_A16, NONE, DEEP, NF1), +/* SD_PWR_EN */ PAD_CFG_NF(GPP_A17, NONE, DEEP, NF1), +/* ISH_GP0 */ PAD_CFG_NC(GPP_A18), +/* ISH_GP1 */ PAD_CFG_NC(GPP_A19), +/* ISH_GP2 */ PAD_CFG_NC(GPP_A20), +/* ISH_GP3 */ PAD_CFG_NC(GPP_A21), +/* ISH_GP4 */ PAD_CFG_NC(GPP_A22), +/* ISH_GP5 */ PAD_CFG_NC(GPP_A23), +/* V0.85A_VID0 */ PAD_CFG_NF(GPP_B0, NONE, DEEP, NF1), +/* V0.85A_VID1 */ PAD_CFG_NF(GPP_B1, NONE, DEEP, NF1), +/* GP_VRALERTB */ PAD_CFG_NF(GPP_B2, NONE, DEEP, NF1), +/* CPU_GP2 */ PAD_CFG_NC(GPP_B3), +/* CPU_GP2 */ PAD_CFG_NC(GPP_B4), +/* CLK_REQ_SLOT0 */ PAD_CFG_NC(GPP_B5), +/* CLK_REQ_SLOT1 */ PAD_CFG_NC(GPP_B6), +/* CLK_REQ_SLOT2 */ PAD_CFG_NC(GPP_B7), +/* CLK_REQ_SLOT3 */ PAD_CFG_NC(GPP_B8), +/* CLK_REQ_SLOT4 */ PAD_CFG_NC(GPP_B9), +/* CLK_REQ_SLOT5 */ PAD_CFG_NC(GPP_B10), +/* MPHY_EXT_PWR_GATE */ PAD_CFG_NF(GPP_B11, NONE, DEEP, NF1), +/* PM_SLP_S0 */ PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1), +/* PCH_PLT_RST */ PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1), +/* PCH_SPKR */ PAD_CFG_NF(GPP_B14, NONE, DEEP, NF1), +/* GSPI0_CS# */ /* GPP_B15 */ +/* GSPI0_CLK */ PAD_CFG_NC(GPP_B16), +/* GSPI0_MISO */ PAD_CFG_NC(GPP_B17), +/* GSPI0_MOSI */ PAD_CFG_NC(GPP_B18), +/* GSPI1_CS */ PAD_CFG_NF(GPP_B19, NONE, DEEP, NF1), +/* GSPI1_CLK */ PAD_CFG_NF(GPP_B20, 20K_PD, DEEP, NF1), +/* GSPI1_MISO */ PAD_CFG_NF(GPP_B21, 20K_PD, DEEP, NF1), +/* GSPI1_MOSI */ PAD_CFG_NF(GPP_B22, 20K_PD, DEEP, NF1), +///* CB_OVT# */ PAD_CFG_NF(GPP_B23, NONE, DEEP, NF1), +/* SML1ALERT# */ PAD_CFG_GPI_APIC(GPP_B23, 20K_PD, PLTRST), +/* SMB_CLK */ PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1), +/* SMB_DATA */ PAD_CFG_NF(GPP_C1, 20K_PD, DEEP, NF1), +/* SMBALERT# */ PAD_CFG_GPO(GPP_C2, 1, DEEP), +/* SML0_CLK */ PAD_CFG_NF(GPP_C3, NONE, DEEP, NF1), +/* SML0DATA */ PAD_CFG_NF(GPP_C4, NONE, DEEP, NF1), +///* SML0ALERT# */ PAD_CFG_GPI_APIC(GPP_C5, 20K_PD, PLTRST), +/* SML0ALERT# */ PAD_CFG_NC(GPP_C5), +/* SML1_CLK */ PAD_CFG_NF(GPP_C6, NONE, DEEP, NF1), +/* SML1_DATA */ PAD_CFG_NF(GPP_C7, 20K_PD, DEEP, NF1), +/* UART0_RXD */ PAD_CFG_NF(GPP_C8, NONE, DEEP, NF1), +/* UART0_TXD */ PAD_CFG_NF(GPP_C9, NONE, DEEP, NF1), +/* UART0_RTS */ PAD_CFG_NF(GPP_C10, NONE, DEEP, NF1), +/* UART0_CTS */ PAD_CFG_NF(GPP_C11, NONE, DEEP, NF1), +/* UART1_RXD */ PAD_CFG_NC(GPP_C12), +/* UART1_TXD */ PAD_CFG_NC(GPP_C13), +/* UART1_RTS */ PAD_CFG_NC(GPP_C14), +/* UART1_CTS */ PAD_CFG_NC(GPP_C15), +/* I2C0_SDA */ PAD_CFG_NF(GPP_C16, 5K_PU, DEEP, NF1), +/* I2C0_SCL */ PAD_CFG_NF(GPP_C17, 5K_PU, DEEP, NF1), +/* I2C1_SDA */ PAD_CFG_NC(GPP_C18), +/* I2C1_SCL */ PAD_CFG_NC(GPP_C19), +/* UART2_RXD */ PAD_CFG_NC(GPP_C20), +/* UART2_TXD */ PAD_CFG_NC(GPP_C21), +///* EC_SMI */ PAD_CFG_GPI_ACPI_SMI(GPP_E15, NONE, DEEP, YES), +///* EC_SCI */ PAD_CFG_GPI_ACPI_SCI(GPP_E16, NONE, DEEP, YES), +/* EC_SCI# not used */ PAD_CFG_NC(GPP_C22), +/* EC_SMI# not used */ PAD_CFG_NC(GPP_C23), +/* SPI1_CS */ PAD_CFG_NF(GPP_D0, NONE, DEEP, NF1), +/* SPI1_CLK */ PAD_CFG_NF(GPP_D1, NONE, DEEP, NF1), +/* SPI1_MISO */ PAD_CFG_NF(GPP_D2, NONE, DEEP, NF1), +/* SPI1_MOSI */ PAD_CFG_NF(GPP_D3, NONE, DEEP, NF1), +/* CAM_FLASH_STROBE */ PAD_CFG_NF(GPP_D4, NONE, DEEP, NF1), +/* ISH_I2C0_SDA */ PAD_CFG_NF(GPP_D5, NONE, DEEP, NF1), +/* ISH_I2C0_SCL */ PAD_CFG_NF(GPP_D6, NONE, DEEP, NF1), +/* ISH_I2C1_SDA */ PAD_CFG_NF(GPP_D7, NONE, DEEP, NF1), +/* ISH_I2C1_SCL */ PAD_CFG_NF(GPP_D8, NONE, DEEP, NF1), +/* GPP_D9 */ PAD_CFG_NC(GPP_D9), +/* GPP_D10 */ PAD_CFG_NC(GPP_D10), +/* GPP_D11 */ PAD_CFG_NC(GPP_D11), +/* GPP_D12 */ PAD_CFG_NC(GPP_D12), +/* ISH_UART0_RXD */ PAD_CFG_NC(GPP_D13), +/* ISH_UART0_TXD */ PAD_CFG_NC(GPP_D14), +/* ISH_UART0_RTS */ PAD_CFG_NC(GPP_D15), +/* ISH_UART0_CTS */ PAD_CFG_NC(GPP_D16), +/* DMIC_CLK_1 */ PAD_CFG_NC(GPP_D17), +/* DMIC_DATA_1 */ PAD_CFG_NC(GPP_D18), +/* DMIC_CLK_0 */ PAD_CFG_NC(GPP_D19), +/* DMIC_DATA_0 */ PAD_CFG_NC(GPP_D20), +/* SPI1_D2 */ PAD_CFG_NF(GPP_D21, NONE, DEEP, NF1), +/* SPI1_D3 */ PAD_CFG_NF(GPP_D22, NONE, DEEP, NF1), +/* I2S_MCLK */ PAD_CFG_NC(GPP_D23), +///* SPI_TPM_IRQ */ PAD_CFG_GPI_APIC(GPP_E0, NONE, PLTRST), +/* GPP_E0 */ PAD_CFG_NC(GPP_E0), +/* GPP_E1 */ PAD_CFG_NC(GPP_E1), +/* GPP_E2 */ PAD_CFG_NC(GPP_E2), +/* GPP_E3 */ PAD_CFG_NC(GPP_E3), +/* SATA_DEVSLP0 */ PAD_CFG_NF(GPP_E4, NONE, DEEP, NF1), +/* SATA_DEVSLP1 */ PAD_CFG_NF(GPP_E5, NONE, DEEP, NF1), +/* SATA_DEVSLP2 */ PAD_CFG_NF(GPP_E6, NONE, DEEP, NF1), +/* GPP_E7 */ PAD_CFG_NC(GPP_E7), +/* SATALED# */ PAD_CFG_NF(GPP_E8, NONE, DEEP, NF1), +/* USB2_OC_0 */ PAD_CFG_NF(GPP_E9, NONE, DEEP, NF1), +/* USB2_OC_1 */ PAD_CFG_NF(GPP_E10, NONE, DEEP, NF1), +/* USB2_OC_2 */ PAD_CFG_NF(GPP_E11, NONE, DEEP, NF1), +/* USB2_OC_3 */ PAD_CFG_GPI_APIC(GPP_E12, NONE, PLTRST), +/* DDI1_HPD */ PAD_CFG_NF(GPP_E13, NONE, DEEP, NF1), +/* DDI2_HPD */ PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1), +/* DDI3_HPD */ PAD_CFG_NF(GPP_E15, NONE, DEEP, NF1), +/* DDI4_HPD */ PAD_CFG_NF(GPP_E16, NONE, DEEP, NF1), +/* EDP_HPD */ PAD_CFG_NF(GPP_E17, NONE, DEEP, NF1), +/* DDPB_CTRLCLK */ PAD_CFG_NF(GPP_E18, NONE, DEEP, NF1), +/* DDPB_CTRLDATA */ PAD_CFG_NF(GPP_E19, 20K_PD, DEEP, NF1), +/* DDPC_CTRLCLK */ PAD_CFG_NF(GPP_E20, NONE, DEEP, NF1), +/* DDPC_CTRLDATA */ PAD_CFG_NF(GPP_E21, 20K_PD, DEEP, NF1), +/* DDPD_CTRLCLK */ PAD_CFG_NF(GPP_E22, NONE, DEEP, NF1), +/* DDPD_CTRLDATA */ PAD_CFG_NF(GPP_E23, 20K_PD, DEEP, NF1), +/* I2S2_SCLK */ PAD_CFG_NC(GPP_F0), +/* I2S2_SFRM */ PAD_CFG_NC(GPP_F1), +/* I2S2_TXD */ PAD_CFG_NC(GPP_F2), +/* I2S2_RXD */ PAD_CFG_NC(GPP_F3), +/* I2C2_SDA */ PAD_CFG_NC(GPP_F4), +/* I2C2_SCL */ PAD_CFG_NC(GPP_F5), +/* I2C3_SDA */ PAD_CFG_NC(GPP_F6), +/* I2C3_SCL */ PAD_CFG_NC(GPP_F7), +/* I2C4_SDA */ PAD_CFG_NC(GPP_F8), +/* I2C4_SDA */ PAD_CFG_NC(GPP_F9), +/* ISH_I2C2_SDA */ PAD_CFG_NC(GPP_F10), +/* ISH_I2C2_SCL */ PAD_CFG_NC(GPP_F11), +/* EMMC_CMD */ PAD_CFG_NF(GPP_F12, NONE, DEEP, NF1), +/* EMMC_DATA0 */ PAD_CFG_NF(GPP_F13, NONE, DEEP, NF1), +/* EMMC_DATA1 */ PAD_CFG_NF(GPP_F14, NONE, DEEP, NF1), +/* EMMC_DATA2 */ PAD_CFG_NF(GPP_F15, NONE, DEEP, NF1), +/* EMMC_DATA3 */ PAD_CFG_NF(GPP_F16, NONE, DEEP, NF1), +/* EMMC_DATA4 */ PAD_CFG_NF(GPP_F17, NONE, DEEP, NF1), +/* EMMC_DATA5 */ PAD_CFG_NF(GPP_F18, NONE, DEEP, NF1), +/* EMMC_DATA6 */ PAD_CFG_NF(GPP_F19, NONE, DEEP, NF1), +/* EMMC_DATA7 */ PAD_CFG_NF(GPP_F20, NONE, DEEP, NF1), +/* EMMC_RCLK */ PAD_CFG_NF(GPP_F21, NONE, DEEP, NF1), +/* EMMC_CLK */ PAD_CFG_NF(GPP_F22, NONE, DEEP, NF1), +/* GPP_F23 */ PAD_CFG_NC(GPP_F23), +/* SD_CMD */ PAD_CFG_NF(GPP_G0, NONE, DEEP, NF1), +/* SD_DATA0 */ PAD_CFG_NF(GPP_G1, NONE, DEEP, NF1), +/* SD_DATA1 */ PAD_CFG_NF(GPP_G2, NONE, DEEP, NF1), +/* SD_DATA2 */ PAD_CFG_NF(GPP_G3, NONE, DEEP, NF1), +/* SD_DATA3 */ PAD_CFG_NF(GPP_G4, NONE, DEEP, NF1), +/* SD_CD# */ PAD_CFG_NF(GPP_G5, NONE, DEEP, NF1), +/* SD_CLK */ PAD_CFG_NF(GPP_G6, NONE, DEEP, NF1), +/* SD_WP */ PAD_CFG_NF(GPP_G7, NONE, DEEP, NF1), +/* PCH_BATLOW */ PAD_CFG_NF(GPD0, NONE, DEEP, NF1), +/* AC_PRESENT */ PAD_CFG_NF(GPD1, NONE, DEEP, NF1), +/* PCH_WAKE */ PAD_CFG_NF(GPD2, NONE, DEEP, NF1), +/* PCH_PWRBTN */ PAD_CFG_NF(GPD3, NONE, DEEP, NF1), +/* PM_SLP_S3# */ PAD_CFG_NF(GPD4, NONE, DEEP, NF1), +/* PM_SLP_S4# */ PAD_CFG_NF(GPD5, NONE, DEEP, NF1), +/* PM_SLP_SA# */ PAD_CFG_NF(GPD6, NONE, DEEP, NF1), +/* GPD7 */ PAD_CFG_NC(GPD7), +/* PM_SUSCLK */ PAD_CFG_NF(GPD8, NONE, DEEP, NF1), +/* PCH_SLP_WLAN# */ PAD_CFG_NF(GPD9, NONE, DEEP, NF1), +/* PM_SLP_S5# */ PAD_CFG_NF(GPD10, NONE, DEEP, NF1), +/* LANPHYC */ PAD_CFG_NF(GPD11, NONE, DEEP, NF1), +}; + +#endif +#endif diff --git a/src/mainboard/facebook/monolith/mainboard.c b/src/mainboard/facebook/monolith/mainboard.c new file mode 100644 index 0000000000..3d6532e2d8 --- /dev/null +++ b/src/mainboard/facebook/monolith/mainboard.c @@ -0,0 +1,50 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * Copyright (C) 2013 Google Inc. + * Copyright (C) 2016 Intel Corporation. + * Copyright (C) 2018-2019 Eltan B.V. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include + +/* + * Declare the resources we are using + */ +static void mainboard_reserve_resources(struct device *dev) +{ + unsigned int idx = 0; + struct resource *res; + + /* + * CPLD: Reserve the IRQ here all others are within the default LPC + * range 0 to 1000h + */ + res = new_resource(dev, idx++); + res->base = 0x7; + res->size = 0x1; + res->flags = IORESOURCE_IRQ | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; +} + +/* + * mainboard_enable is executed as first thing after + * enumerate_buses(). + */ +static void mainboard_enable(struct device *dev) +{ + mainboard_reserve_resources(dev); +} + +struct chip_operations mainboard_ops = { + .enable_dev = mainboard_enable, +}; diff --git a/src/mainboard/facebook/monolith/onboard.h b/src/mainboard/facebook/monolith/onboard.h new file mode 100644 index 0000000000..68b5feaec5 --- /dev/null +++ b/src/mainboard/facebook/monolith/onboard.h @@ -0,0 +1,24 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Google Inc. + * Copyright (C) 2015 Intel Corp. + * Copyright (C) 2018-2019 Eltan B.V. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef ONBOARD_H +#define ONBOARD_H + +#define ITE8528_CMD_PORT 0x6E +#define ITE8528_DATA_PORT 0x6F + +#endif diff --git a/src/mainboard/facebook/monolith/ramstage.c b/src/mainboard/facebook/monolith/ramstage.c new file mode 100644 index 0000000000..bed104956f --- /dev/null +++ b/src/mainboard/facebook/monolith/ramstage.c @@ -0,0 +1,26 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016-2018 Intel Corporation + * Copyright (C) 2019 Eltan B.V. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include "gpio.h" + +void mainboard_silicon_init_params(FSP_SIL_UPD *params) +{ + /* Configure pads prior to SiliconInit() in case there's any + * dependencies during hardware initialization. */ + gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table)); + params->CdClock = 3; +} diff --git a/src/mainboard/facebook/monolith/romstage.c b/src/mainboard/facebook/monolith/romstage.c new file mode 100644 index 0000000000..7c54708f2c --- /dev/null +++ b/src/mainboard/facebook/monolith/romstage.c @@ -0,0 +1,41 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016-2018 Intel Corporation. + * Copyright (C) 2019 Eltan B.V. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include +#include "spd/spd.h" + +void mainboard_memory_init_params(FSPM_UPD *mupd) +{ + FSP_M_CONFIG *mem_cfg; + mem_cfg = &mupd->FspmConfig; + struct spd_block blk = { + .addr_map = { 0x50, 0x52, }, + }; + + mainboard_fill_dq_map_data(&mem_cfg->DqByteMapCh0); + mainboard_fill_dqs_map_data(&mem_cfg->DqsMapCpu2DramCh0); + mainboard_fill_rcomp_res_data(&mem_cfg->RcompResistor); + mainboard_fill_rcomp_strength_data(&mem_cfg->RcompTarget); + + mem_cfg->DqPinsInterleaved = 1; + get_spd_smbus(&blk); + mem_cfg->MemorySpdDataLen = blk.len; + mem_cfg->MemorySpdPtr00 = (uintptr_t)blk.spd_array[0]; + mem_cfg->MemorySpdPtr10 = (uintptr_t)blk.spd_array[1]; + mupd->FspmTestConfig.DmiVc1 = 1; +} diff --git a/src/mainboard/facebook/monolith/spd/Makefile.inc b/src/mainboard/facebook/monolith/spd/Makefile.inc new file mode 100644 index 0000000000..b4b42f7856 --- /dev/null +++ b/src/mainboard/facebook/monolith/spd/Makefile.inc @@ -0,0 +1,18 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2014 Google Inc. +## Copyright (C) 2015 Intel Corporation. +## Copyright (C) 2019 Eltan B.V. +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +romstage-y += spd_util.c diff --git a/src/mainboard/facebook/monolith/spd/spd.h b/src/mainboard/facebook/monolith/spd/spd.h new file mode 100644 index 0000000000..f2b6f2af70 --- /dev/null +++ b/src/mainboard/facebook/monolith/spd/spd.h @@ -0,0 +1,26 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2014 Google Inc. + * Copyright (C) 2015 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef MAINBOARD_SPD_H +#define MAINBOARD_SPD_H + +#define RCOMP_TARGET_PARAMS 0x5 + +void mainboard_fill_dq_map_data(void *dq_map_ptr); +void mainboard_fill_dqs_map_data(void *dqs_map_ptr); +void mainboard_fill_rcomp_res_data(void *rcomp_ptr); +void mainboard_fill_rcomp_strength_data(void *rcomp_strength_ptr); +#endif diff --git a/src/mainboard/facebook/monolith/spd/spd_util.c b/src/mainboard/facebook/monolith/spd/spd_util.c new file mode 100644 index 0000000000..5ccc8107fb --- /dev/null +++ b/src/mainboard/facebook/monolith/spd/spd_util.c @@ -0,0 +1,56 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include + +#include "spd.h" + +void mainboard_fill_dq_map_data(void *dq_map_ptr) +{ + /* DQ byte map */ + const u8 dq_map[2][12] = { + { 0x0F, 0xF0, 0x00, 0xF0, 0x0F, 0xF0, + 0x0F, 0x00, 0xFF, 0x00, 0xFF, 0x00 }, + { 0x33, 0xCC, 0x00, 0xCC, 0x33, 0xCC, + 0x33, 0x00, 0xFF, 0x00, 0xFF, 0x00 } }; + memcpy(dq_map_ptr, dq_map, sizeof(dq_map)); +} + +void mainboard_fill_dqs_map_data(void *dqs_map_ptr) +{ + /* DQS CPU<>DRAM map */ + const u8 dqs_map[2][8] = { + { 0, 1, 3, 2, 4, 5, 6, 7 }, + { 1, 0, 4, 5, 2, 3, 6, 7 } }; + memcpy(dqs_map_ptr, dqs_map, sizeof(dqs_map)); +} + +void mainboard_fill_rcomp_res_data(void *rcomp_ptr) +{ + /* Rcomp resistor */ + const u16 RcompResistor[3] = { 200, 81, 162 }; + memcpy(rcomp_ptr, RcompResistor, + sizeof(RcompResistor)); +} + +void mainboard_fill_rcomp_strength_data(void *rcomp_strength_ptr) +{ + /* Rcomp target */ + static const u16 RcompTarget[RCOMP_TARGET_PARAMS] = { + 100, 40, 40, 23, 40 }; + + memcpy(rcomp_strength_ptr, RcompTarget, sizeof(RcompTarget)); +} diff --git a/src/mainboard/facebook/monolith/vboot-rw.fmd b/src/mainboard/facebook/monolith/vboot-rw.fmd new file mode 100644 index 0000000000..fad0f97767 --- /dev/null +++ b/src/mainboard/facebook/monolith/vboot-rw.fmd @@ -0,0 +1,28 @@ +FLASH 16M { + SI_ALL@0x0 0x700000 { + SI_DESC@0x0 0x1000 + UNUSED_1@0x1000 0x2000 + SI_ME@0x3000 0x6fd000 + } + SI_BIOS@0x700000 0x900000 { + MISC_RW@0x0 0x20000 { + RW_MRC_CACHE@0x0 0x10000 + RW_VPD(PRESERVE)@0x010000 0x2000 + RW_NVRAM(PRESERVE)@0x012000 0x6000 + } + RW_SECTION_A@0x20000 0x860000 { + VBLOCK_A@0x0 0x10000 + RW_FWID_A@0x10000% 0x40 + FW_MAIN_A(CBFS)@0x10040% 0x84FFC0 + } + WP_RO@0x880000 0x080000 { + RO_SECTION@0x0000 0x80000 { + FMAP@0x0% 0x800 + RO_FRID@0x800% 0x40 + RO_FRID_PAD@0x840% 0x7c0 + GBB@0x1000 0x4000 + COREBOOT(CBFS)@0x5000 0x07B000 + } + } + } +} From 4ba70a75758711b1665545f754cbe11235df5097 Mon Sep 17 00:00:00 2001 From: Wim Vervoorn Date: Thu, 5 Dec 2019 13:48:11 +0100 Subject: [PATCH 0573/1242] src: Add Facebook Monolith to maintainers Add Facebook Monolith maintainers. BUG=N/A TEST=build Change-Id: I4e7f44710deada0331ac9b4e77d6144848faf6cb Signed-off-by: Wim Vervoorn Reviewed-on: https://review.coreboot.org/c/coreboot/+/37517 Tested-by: build bot (Jenkins) Reviewed-by: Frans Hendriks --- MAINTAINERS | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index d4b19350b0..6c565f7db7 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -334,6 +334,12 @@ M: Wim Vervoorn S: Maintained F: src/mainboard/facebook/fbg1701/ +FACEBOOK MONOLITH MAINBOARD +M: Frans Hendriks +M: Wim Vervoorn +S: Maintained +F: src/mainboard/facebook/monolith/ + PORTWELL PQ-M107 MAINBOARD M: Frans Hendriks M: Wim Vervoorn From 67910db907fb3d5feacdbfaa40952a88f673795a Mon Sep 17 00:00:00 2001 From: Marshall Dawson Date: Fri, 1 Nov 2019 17:30:05 -0600 Subject: [PATCH 0574/1242] arch|cpu/x86: Add Kconfig option for x86 reset vector Prepare for an implementation supporting the reset vector in RAM and not the traditional 0xfffffff0. Add a Kconfig symbol that can be used in place of hardcoded values. Change-Id: I6a814f7179ee4251aeeccb2555221616e944e03d Signed-off-by: Marshall Dawson Reviewed-on: https://review.coreboot.org/c/coreboot/+/37485 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi --- src/arch/x86/Kconfig | 10 ++++++++++ src/arch/x86/failover.ld | 2 +- src/arch/x86/id.ld | 2 +- src/arch/x86/memlayout.ld | 2 +- src/cpu/intel/fit/fit.ld | 2 +- src/cpu/x86/16bit/reset16.ld | 12 +++++------- 6 files changed, 19 insertions(+), 11 deletions(-) diff --git a/src/arch/x86/Kconfig b/src/arch/x86/Kconfig index 0e6f486d03..e27aec2463 100644 --- a/src/arch/x86/Kconfig +++ b/src/arch/x86/Kconfig @@ -87,6 +87,16 @@ config AP_IN_SIPI_WAIT default n depends on ARCH_X86 && SMP +config X86_RESET_VECTOR + hex + depends on ARCH_X86 + default 0xfffffff0 + help + Specify the location of the x86 reset vector. In traditional devices + this must match the architectural reset vector to produce a bootable + image. Nontraditional designs may use this to position the reset + vector into its desired location. + config RESET_VECTOR_IN_RAM bool depends on ARCH_X86 diff --git a/src/arch/x86/failover.ld b/src/arch/x86/failover.ld index 334145a742..139136540c 100644 --- a/src/arch/x86/failover.ld +++ b/src/arch/x86/failover.ld @@ -14,7 +14,7 @@ ENTRY(_start) MEMORY { - rom : ORIGIN = 0xffff0000, LENGTH = 64K + rom : ORIGIN = CONFIG_X86_RESET_VECTOR - 0xfff0, LENGTH = 64K } TARGET(binary) diff --git a/src/arch/x86/id.ld b/src/arch/x86/id.ld index 2a50f9ca4f..3d9ef37ab9 100644 --- a/src/arch/x86/id.ld +++ b/src/arch/x86/id.ld @@ -12,7 +12,7 @@ */ SECTIONS { - . = (0xffffffff - CONFIG_ID_SECTION_OFFSET) - (__id_end - __id_start) + 1; + . = (CONFIG_X86_RESET_VECTOR - CONFIG_ID_SECTION_OFFSET) - (__id_end - __id_start) + 0x10; .id (.): { KEEP(*(.id)) } diff --git a/src/arch/x86/memlayout.ld b/src/arch/x86/memlayout.ld index f8ae9f3918..b14fd624a7 100644 --- a/src/arch/x86/memlayout.ld +++ b/src/arch/x86/memlayout.ld @@ -50,7 +50,7 @@ SECTIONS #include EARLY_MEMLAYOUT #elif ENV_BOOTBLOCK /* arch/x86/bootblock.ld contains the logic for the ROMCC_BOOTBLOCK linking. */ - BOOTBLOCK(0xffffffff - CONFIG_C_ENV_BOOTBLOCK_SIZE + 1, + BOOTBLOCK(CONFIG_X86_RESET_VECTOR - CONFIG_C_ENV_BOOTBLOCK_SIZE + 0x10, CONFIG_C_ENV_BOOTBLOCK_SIZE) #include EARLY_MEMLAYOUT diff --git a/src/cpu/intel/fit/fit.ld b/src/cpu/intel/fit/fit.ld index 6e30ea168a..2e65186e40 100644 --- a/src/cpu/intel/fit/fit.ld +++ b/src/cpu/intel/fit/fit.ld @@ -12,7 +12,7 @@ */ SECTIONS { - . = 0xffffffc0; + . = CONFIG_X86_RESET_VECTOR - 0x30; /* 0xffffffc0 */ .fit_pointer (.): { KEEP(*(.fit_pointer)) } diff --git a/src/cpu/x86/16bit/reset16.ld b/src/cpu/x86/16bit/reset16.ld index c57cc96cdd..ec01810e73 100644 --- a/src/cpu/x86/16bit/reset16.ld +++ b/src/cpu/x86/16bit/reset16.ld @@ -11,16 +11,14 @@ * GNU General Public License for more details. */ -/* - * _ROMTOP : The top of the ROM used where we - * need to put the reset vector. - */ +/* _RESET_VECTOR: typically the top of the ROM */ SECTIONS { /* Trigger an error if I have an unuseable start address */ - _bogus = ASSERT(_start16bit >= 0xffff0000, "_start16bit too low. Please report."); - _ROMTOP = 0xfffffff0; - . = _ROMTOP; + _TOO_LOW = CONFIG_X86_RESET_VECTOR - 0xfff0; + _bogus = ASSERT(_start16bit >= _TOO_LOW, "_start16bit too low. Please report."); + + . = CONFIG_X86_RESET_VECTOR; .reset . : { *(.reset); . = 15; From 2ee6fbf0d7593f0c78677c9c2bb307e47cea6c23 Mon Sep 17 00:00:00 2001 From: Peter Lemenkov Date: Wed, 27 Nov 2019 15:07:31 +0100 Subject: [PATCH 0575/1242] mb/lenovo/t520/devicetree: Use subsystemid inheritance Change-Id: Iffeb634c73f58aa1cddac5210d75fda75a3d5e92 Signed-off-by: Peter Lemenkov Reviewed-on: https://review.coreboot.org/c/coreboot/+/37293 Reviewed-by: Patrick Georgi Reviewed-by: HAOUAS Elyes Tested-by: build bot (Jenkins) --- .../lenovo/t520/variants/t520/devicetree.cb | 13 +++++++++---- 1 file changed, 9 insertions(+), 4 deletions(-) diff --git a/src/mainboard/lenovo/t520/variants/t520/devicetree.cb b/src/mainboard/lenovo/t520/variants/t520/devicetree.cb index 7893daf9ec..0bfa18f4a6 100644 --- a/src/mainboard/lenovo/t520/variants/t520/devicetree.cb +++ b/src/mainboard/lenovo/t520/variants/t520/devicetree.cb @@ -37,9 +37,13 @@ chip northbridge/intel/sandybridge register "pci_mmio_size" = "2048" device domain 0 on + subsystemid 0x17aa 0x21cf inherit + device pci 00.0 on end # host bridge device pci 01.0 on end # NVIDIA Corporation GF119M [NVS 4200M] - device pci 02.0 on end # vga controller + device pci 02.0 on + subsystemid 0x17aa 0x21d1 + end # vga controller chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH # GPI routing @@ -73,7 +77,9 @@ chip northbridge/intel/sandybridge device pci 16.1 off end device pci 16.2 off end device pci 16.3 off end - device pci 19.0 on end # Intel Gigabit Ethernet + device pci 19.0 on # Intel Gigabit Ethernet + subsystemid 0x17aa 0x21ce + end device pci 1a.0 on end # USB2 EHCI #2 device pci 1b.0 on end # High Definition Audio device pci 1c.0 off end # PCIe Port #1 @@ -91,8 +97,7 @@ chip northbridge/intel/sandybridge device pci 1f.0 on #LPC bridge chip ec/lenovo/pmh7 - device pnp ff.1 on # dummy - end + device pnp ff.1 on end # dummy register "backlight_enable" = "0x01" register "dock_event_enable" = "0x01" end From a0c97590b910da51dcd95547f720e9d3b964f140 Mon Sep 17 00:00:00 2001 From: Peter Lemenkov Date: Wed, 27 Nov 2019 15:15:27 +0100 Subject: [PATCH 0576/1242] mb/lenovo/w520/devicetree: Use subsystemid inheritance Change-Id: If7816992e717b4da585b16e5bbe67610c9af867d Signed-off-by: Peter Lemenkov Reviewed-on: https://review.coreboot.org/c/coreboot/+/37294 Tested-by: build bot (Jenkins) Reviewed-by: HAOUAS Elyes Reviewed-by: Patrick Rudolph --- .../lenovo/t520/variants/w520/devicetree.cb | 14 ++++++++++---- 1 file changed, 10 insertions(+), 4 deletions(-) diff --git a/src/mainboard/lenovo/t520/variants/w520/devicetree.cb b/src/mainboard/lenovo/t520/variants/w520/devicetree.cb index 8716046410..8b2cbe78e4 100644 --- a/src/mainboard/lenovo/t520/variants/w520/devicetree.cb +++ b/src/mainboard/lenovo/t520/variants/w520/devicetree.cb @@ -37,9 +37,13 @@ chip northbridge/intel/sandybridge register "pci_mmio_size" = "2048" device domain 0 on + subsystemid 0x17aa 0x21cf inherit + device pci 00.0 on end # host bridge device pci 01.0 on end # NVIDIA Corporation GF119M [NVS 4200M] - device pci 02.0 on end # vga controller + device pci 02.0 on + subsystemid 0x17aa 0x21d1 + end # vga controller chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH # GPI routing @@ -73,7 +77,9 @@ chip northbridge/intel/sandybridge device pci 16.1 off end device pci 16.2 off end device pci 16.3 off end - device pci 19.0 on end # Intel Gigabit Ethernet + device pci 19.0 on # Intel Gigabit Ethernet + subsystemid 0x17aa 0x21ce + end device pci 1a.0 on end # USB2 EHCI #2 device pci 1b.0 on end # High Definition Audio device pci 1c.0 off end # PCIe Port #1 @@ -87,10 +93,10 @@ chip northbridge/intel/sandybridge device pci 1c.6 on end # PCIe Port #7 USB 3.0 only W520 device pci 1c.7 off end # PCIe Port #8 device pci 1d.0 on end # USB2 EHCI #1 + device pci 1f.0 on #LPC bridge chip ec/lenovo/pmh7 - device pnp ff.1 on # dummy - end + device pnp ff.1 on end # dummy register "backlight_enable" = "0x01" register "dock_event_enable" = "0x01" end From 9f56eeda41a227028feb29d5f3406b024f9aa8a2 Mon Sep 17 00:00:00 2001 From: Elyes HAOUAS Date: Thu, 5 Dec 2019 10:06:26 +0100 Subject: [PATCH 0577/1242] src/superio: Remove unused intel's superio chips Change-Id: Ie693ff700a804778682daf0cb3990a56ab747a93 Signed-off-by: Elyes HAOUAS Reviewed-on: https://review.coreboot.org/c/coreboot/+/37506 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel Reviewed-by: Felix Held --- src/superio/intel/Makefile.inc | 17 ----------------- 1 file changed, 17 deletions(-) delete mode 100644 src/superio/intel/Makefile.inc diff --git a/src/superio/intel/Makefile.inc b/src/superio/intel/Makefile.inc deleted file mode 100644 index f46408a759..0000000000 --- a/src/superio/intel/Makefile.inc +++ /dev/null @@ -1,17 +0,0 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2009 Ronald G. Minnich -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; version 2 of the License. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## - -subdirs-y += i3100 -subdirs-y += i8900 From dafc78bb8d6bda8bddb029168491365b333ce529 Mon Sep 17 00:00:00 2001 From: Elyes HAOUAS Date: Sat, 7 Dec 2019 10:23:05 +0100 Subject: [PATCH 0578/1242] mb/asus/am1i-a: Remove defined and not used ITE_CONFIG_REG_CC Change-Id: I934830c09f7996e8f5aae5d5abe9fb6014fb478d Signed-off-by: Elyes HAOUAS Reviewed-on: https://review.coreboot.org/c/coreboot/+/37569 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel Reviewed-by: Mike Banon --- src/mainboard/asus/am1i-a/romstage.c | 2 -- 1 file changed, 2 deletions(-) diff --git a/src/mainboard/asus/am1i-a/romstage.c b/src/mainboard/asus/am1i-a/romstage.c index 5e1218abd3..c0f5c04bc8 100644 --- a/src/mainboard/asus/am1i-a/romstage.c +++ b/src/mainboard/asus/am1i-a/romstage.c @@ -24,8 +24,6 @@ #include #include -#define ITE_CONFIG_REG_CC 0x02 - #if CONFIG_UART_FOR_CONSOLE == 0 #define SERIAL_DEV PNP_DEV(0x2e, IT8623E_SP1) #elif CONFIG_UART_FOR_CONSOLE == 1 From 657d68bddc030e38bc19eb4eef07f59b5e5258e4 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ky=C3=B6sti=20M=C3=A4lkki?= Date: Tue, 3 Dec 2019 12:36:09 +0200 Subject: [PATCH 0579/1242] AGESA,binaryPI: Move PORT80 selection to C bootblock MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Because the function is implemented in C, post_code() calls from cache_as_ram.S and other early assembly entry files may not currently work for cold boots. Assembly implementation needs to follow one day. This effectively removes PORT80 routing from boards with ROMCC_BOOTBLOCK. Change-Id: I71aa94b33bd6f65e243724810472a440e98e0750 Signed-off-by: Kyösti Mälkki Reviewed-on: https://review.coreboot.org/c/coreboot/+/37451 Tested-by: build bot (Jenkins) Reviewed-by: Michał Żygowski --- src/console/Kconfig | 5 +++++ src/mainboard/amd/bettong/Kconfig | 1 + src/mainboard/amd/bettong/romstage.c | 2 -- src/mainboard/amd/db-ft3b-lc/Kconfig | 1 + src/mainboard/amd/db-ft3b-lc/romstage.c | 2 -- src/mainboard/amd/lamar/Kconfig | 1 + src/mainboard/amd/lamar/romstage.c | 2 -- src/mainboard/amd/olivehill/Kconfig | 1 + src/mainboard/amd/olivehill/romstage.c | 2 -- src/mainboard/amd/olivehillplus/Kconfig | 1 + src/mainboard/amd/olivehillplus/romstage.c | 2 -- src/mainboard/amd/parmer/Kconfig | 1 + src/mainboard/amd/parmer/romstage.c | 2 -- src/mainboard/amd/thatcher/Kconfig | 1 + src/mainboard/amd/thatcher/romstage.c | 1 - src/mainboard/asrock/imb-a180/Kconfig | 1 + src/mainboard/asrock/imb-a180/romstage.c | 2 -- src/mainboard/asus/am1i-a/Kconfig | 1 + src/mainboard/asus/am1i-a/romstage.c | 2 -- src/mainboard/asus/f2a85-m/romstage.c | 5 ----- src/mainboard/bap/ode_e20XX/Kconfig | 1 + src/mainboard/bap/ode_e20XX/romstage.c | 2 -- src/mainboard/bap/ode_e21XX/Kconfig | 1 + src/mainboard/bap/ode_e21XX/romstage.c | 2 -- src/mainboard/biostar/a68n_5200/romstage.c | 6 ------ src/mainboard/biostar/am1ml/Kconfig | 1 + src/mainboard/biostar/am1ml/romstage.c | 2 -- src/mainboard/gizmosphere/gizmo2/Kconfig | 1 + src/mainboard/gizmosphere/gizmo2/romstage.c | 2 -- src/mainboard/hp/abm/Kconfig | 1 + src/mainboard/hp/abm/romstage.c | 2 -- src/mainboard/hp/pavilion_m6_1035dx/Kconfig | 1 + src/mainboard/hp/pavilion_m6_1035dx/romstage.c | 1 - src/mainboard/lenovo/g505s/Kconfig | 1 + src/mainboard/lenovo/g505s/romstage.c | 1 - src/mainboard/msi/ms7721/romstage.c | 5 ----- src/mainboard/pcengines/apu2/Kconfig | 1 + src/mainboard/pcengines/apu2/romstage.c | 2 -- src/southbridge/amd/agesa/hudson/bootblock.c | 5 +++++ src/southbridge/amd/pi/hudson/bootblock.c | 5 +++++ 40 files changed, 32 insertions(+), 47 deletions(-) diff --git a/src/console/Kconfig b/src/console/Kconfig index 9151a32a11..5225d11f50 100644 --- a/src/console/Kconfig +++ b/src/console/Kconfig @@ -417,6 +417,7 @@ config POST_DEVICE choice prompt "Device to send POST codes to" depends on POST_DEVICE + default POST_DEVICE_LPC if DEFAULT_POST_ON_LPC default POST_DEVICE_NONE config POST_DEVICE_NONE @@ -429,6 +430,10 @@ config POST_DEVICE_PCI_PCIE depends on PCI endchoice +config DEFAULT_POST_ON_LPC + bool + default n + config POST_IO bool "Send POST codes to an IO port" depends on PC80_SYSTEM && !NO_POST diff --git a/src/mainboard/amd/bettong/Kconfig b/src/mainboard/amd/bettong/Kconfig index f5f37cef77..08410d3a72 100644 --- a/src/mainboard/amd/bettong/Kconfig +++ b/src/mainboard/amd/bettong/Kconfig @@ -25,6 +25,7 @@ config BOARD_SPECIFIC_OPTIONS select CPU_AMD_PI_00660F01 select NORTHBRIDGE_AMD_PI_00660F01 select SOUTHBRIDGE_AMD_PI_KERN + select DEFAULT_POST_ON_LPC select HAVE_OPTION_TABLE select HAVE_PIRQ_TABLE select HAVE_MP_TABLE diff --git a/src/mainboard/amd/bettong/romstage.c b/src/mainboard/amd/bettong/romstage.c index c9a257cec5..58430dcf17 100644 --- a/src/mainboard/amd/bettong/romstage.c +++ b/src/mainboard/amd/bettong/romstage.c @@ -29,8 +29,6 @@ static void romstage_main_template(void) { u32 val; - hudson_lpc_port80(); - if (!cpu_init_detectedx && boot_cpu()) { post_code(0x30); diff --git a/src/mainboard/amd/db-ft3b-lc/Kconfig b/src/mainboard/amd/db-ft3b-lc/Kconfig index b83a5253d2..eb5fe8786f 100644 --- a/src/mainboard/amd/db-ft3b-lc/Kconfig +++ b/src/mainboard/amd/db-ft3b-lc/Kconfig @@ -26,6 +26,7 @@ config BOARD_SPECIFIC_OPTIONS select CPU_AMD_PI_00730F01 select NORTHBRIDGE_AMD_PI_00730F01 select SOUTHBRIDGE_AMD_PI_AVALON + select DEFAULT_POST_ON_LPC select HAVE_OPTION_TABLE select HAVE_PIRQ_TABLE select HAVE_MP_TABLE diff --git a/src/mainboard/amd/db-ft3b-lc/romstage.c b/src/mainboard/amd/db-ft3b-lc/romstage.c index 475431e419..a0c6b8d9f3 100644 --- a/src/mainboard/amd/db-ft3b-lc/romstage.c +++ b/src/mainboard/amd/db-ft3b-lc/romstage.c @@ -37,8 +37,6 @@ static void romstage_main_template(void) outb(0xD2, 0xcd6); outb(0x00, 0xcd7); - hudson_lpc_port80(); - if (!cpu_init_detectedx && boot_cpu()) { post_code(0x30); diff --git a/src/mainboard/amd/lamar/Kconfig b/src/mainboard/amd/lamar/Kconfig index 1d3e0f66a7..d509afcfa9 100644 --- a/src/mainboard/amd/lamar/Kconfig +++ b/src/mainboard/amd/lamar/Kconfig @@ -25,6 +25,7 @@ config BOARD_SPECIFIC_OPTIONS select CPU_AMD_PI_00630F01 select NORTHBRIDGE_AMD_PI_00630F01 select SOUTHBRIDGE_AMD_PI_BOLTON + select DEFAULT_POST_ON_LPC select SUPERIO_FINTEK_F81216H select HAVE_OPTION_TABLE select HAVE_PIRQ_TABLE diff --git a/src/mainboard/amd/lamar/romstage.c b/src/mainboard/amd/lamar/romstage.c index 4dde4e2e3f..7f37990efc 100644 --- a/src/mainboard/amd/lamar/romstage.c +++ b/src/mainboard/amd/lamar/romstage.c @@ -48,8 +48,6 @@ static void romstage_main_template(void) *(volatile u32 *) (AMD_SB_ACPI_MMIO_ADDR + 0xE00 + 0x28) |= 1 << 18; /* 24Mhz */ *(volatile u32 *) (AMD_SB_ACPI_MMIO_ADDR + 0xE00 + 0x40) &= ~(1 << 2); /* 24Mhz */ - hudson_lpc_port80(); - if (!cpu_init_detectedx) { post_code(0x30); f81216h_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE, MODE_7777); diff --git a/src/mainboard/amd/olivehill/Kconfig b/src/mainboard/amd/olivehill/Kconfig index 806fdbd1d8..e1b5215348 100644 --- a/src/mainboard/amd/olivehill/Kconfig +++ b/src/mainboard/amd/olivehill/Kconfig @@ -21,6 +21,7 @@ config BOARD_SPECIFIC_OPTIONS select CPU_AMD_AGESA_FAMILY16_KB select NORTHBRIDGE_AMD_AGESA_FAMILY16_KB select SOUTHBRIDGE_AMD_AGESA_YANGTZE + select DEFAULT_POST_ON_LPC select HAVE_OPTION_TABLE select HAVE_PIRQ_TABLE select HAVE_MP_TABLE diff --git a/src/mainboard/amd/olivehill/romstage.c b/src/mainboard/amd/olivehill/romstage.c index 9a28f98b33..122bb19e3d 100644 --- a/src/mainboard/amd/olivehill/romstage.c +++ b/src/mainboard/amd/olivehill/romstage.c @@ -41,8 +41,6 @@ void board_BeforeAgesa(struct sysinfo *cb) pci_devfn_t dev = PCI_DEV(0, 0x14, 3); pci_write_config32(dev, 0x44, 0xff03ffd5); - hudson_lpc_port80(); - /* On Larne, after LpcClkDrvSth is set, it needs some time to be stable, because of the buffer ICS551M */ for (i = 0; i < 200000; i++) val = inb(0xcd6); diff --git a/src/mainboard/amd/olivehillplus/Kconfig b/src/mainboard/amd/olivehillplus/Kconfig index 230dc4b25d..229e3f97e0 100644 --- a/src/mainboard/amd/olivehillplus/Kconfig +++ b/src/mainboard/amd/olivehillplus/Kconfig @@ -25,6 +25,7 @@ config BOARD_SPECIFIC_OPTIONS select CPU_AMD_PI_00730F01 select NORTHBRIDGE_AMD_PI_00730F01 select SOUTHBRIDGE_AMD_PI_AVALON + select DEFAULT_POST_ON_LPC select HAVE_OPTION_TABLE select HAVE_PIRQ_TABLE select HAVE_MP_TABLE diff --git a/src/mainboard/amd/olivehillplus/romstage.c b/src/mainboard/amd/olivehillplus/romstage.c index bb80687b60..c04aafeff6 100644 --- a/src/mainboard/amd/olivehillplus/romstage.c +++ b/src/mainboard/amd/olivehillplus/romstage.c @@ -37,8 +37,6 @@ static void romstage_main_template(void) outb(0xD2, 0xcd6); outb(0x00, 0xcd7); - hudson_lpc_port80(); - if (!cpu_init_detectedx && boot_cpu()) { post_code(0x30); diff --git a/src/mainboard/amd/parmer/Kconfig b/src/mainboard/amd/parmer/Kconfig index dde58a6fd4..3b6cb5ce89 100644 --- a/src/mainboard/amd/parmer/Kconfig +++ b/src/mainboard/amd/parmer/Kconfig @@ -21,6 +21,7 @@ config BOARD_SPECIFIC_OPTIONS select CPU_AMD_AGESA_FAMILY15_TN select NORTHBRIDGE_AMD_AGESA_FAMILY15_TN select SOUTHBRIDGE_AMD_AGESA_HUDSON + select DEFAULT_POST_ON_LPC select HAVE_OPTION_TABLE select HAVE_PIRQ_TABLE select HAVE_MP_TABLE diff --git a/src/mainboard/amd/parmer/romstage.c b/src/mainboard/amd/parmer/romstage.c index 48aee89a9b..6366c4e348 100644 --- a/src/mainboard/amd/parmer/romstage.c +++ b/src/mainboard/amd/parmer/romstage.c @@ -19,8 +19,6 @@ void board_BeforeAgesa(struct sysinfo *cb) { - hudson_lpc_port80(); - pci_devfn_t dev = PCI_DEV(0, 0x14, 3); /* For serial port option, plug-in card on LPC. */ diff --git a/src/mainboard/amd/thatcher/Kconfig b/src/mainboard/amd/thatcher/Kconfig index e11d0ea1d9..2c0939c84e 100644 --- a/src/mainboard/amd/thatcher/Kconfig +++ b/src/mainboard/amd/thatcher/Kconfig @@ -21,6 +21,7 @@ config BOARD_SPECIFIC_OPTIONS select CPU_AMD_AGESA_FAMILY15_TN select NORTHBRIDGE_AMD_AGESA_FAMILY15_TN select SOUTHBRIDGE_AMD_AGESA_HUDSON + select DEFAULT_POST_ON_LPC select HAVE_OPTION_TABLE select HAVE_PIRQ_TABLE select HAVE_MP_TABLE diff --git a/src/mainboard/amd/thatcher/romstage.c b/src/mainboard/amd/thatcher/romstage.c index 1d89e4d6d1..5678021f8b 100644 --- a/src/mainboard/amd/thatcher/romstage.c +++ b/src/mainboard/amd/thatcher/romstage.c @@ -31,7 +31,6 @@ void board_BeforeAgesa(struct sysinfo *cb) /* Set LPC decode enables. */ dev = PCI_DEV(0, 0x14, 3); - hudson_lpc_port80(); byte = pci_read_config8(dev, 0x48); byte |= 3; /* 2e, 2f */ diff --git a/src/mainboard/asrock/imb-a180/Kconfig b/src/mainboard/asrock/imb-a180/Kconfig index 883b1c04e4..b753424c84 100644 --- a/src/mainboard/asrock/imb-a180/Kconfig +++ b/src/mainboard/asrock/imb-a180/Kconfig @@ -21,6 +21,7 @@ config BOARD_SPECIFIC_OPTIONS select CPU_AMD_AGESA_FAMILY16_KB select NORTHBRIDGE_AMD_AGESA_FAMILY16_KB select SOUTHBRIDGE_AMD_AGESA_YANGTZE + select DEFAULT_POST_ON_LPC select SUPERIO_WINBOND_W83627UHG select HAVE_OPTION_TABLE select HAVE_PIRQ_TABLE diff --git a/src/mainboard/asrock/imb-a180/romstage.c b/src/mainboard/asrock/imb-a180/romstage.c index ce5e0643a5..5b9a2263e5 100644 --- a/src/mainboard/asrock/imb-a180/romstage.c +++ b/src/mainboard/asrock/imb-a180/romstage.c @@ -35,8 +35,6 @@ void board_BeforeAgesa(struct sysinfo *cb) pci_devfn_t dev = PCI_DEV(0, 0x14, 3); pci_write_config32(dev, 0x44, 0xff03ffd5); - hudson_lpc_port80(); - /* Enable the AcpiMmio space */ outb(0x24, 0xcd6); outb(0x1, 0xcd7); diff --git a/src/mainboard/asus/am1i-a/Kconfig b/src/mainboard/asus/am1i-a/Kconfig index c3f21e9531..f194519393 100644 --- a/src/mainboard/asus/am1i-a/Kconfig +++ b/src/mainboard/asus/am1i-a/Kconfig @@ -16,6 +16,7 @@ config BOARD_SPECIFIC_OPTIONS select HAVE_ACPI_TABLES select NORTHBRIDGE_AMD_AGESA_FAMILY16_KB select SOUTHBRIDGE_AMD_AGESA_YANGTZE + select DEFAULT_POST_ON_LPC select SUPERIO_ITE_IT8623E select MAINBOARD_HAS_LPC_TPM diff --git a/src/mainboard/asus/am1i-a/romstage.c b/src/mainboard/asus/am1i-a/romstage.c index c0f5c04bc8..de8532504d 100644 --- a/src/mainboard/asus/am1i-a/romstage.c +++ b/src/mainboard/asus/am1i-a/romstage.c @@ -142,8 +142,6 @@ void board_BeforeAgesa(struct sysinfo *cb) pci_devfn_t dev2 = PCI_DEV(0, 0x14, 3); pci_write_config32(dev2, 0x44, 0xff03ffd5); - hudson_lpc_port80(); - /* Enable the AcpiMmio space */ outb(0x24, 0xcd6); outb(0x1, 0xcd7); diff --git a/src/mainboard/asus/f2a85-m/romstage.c b/src/mainboard/asus/f2a85-m/romstage.c index d5acdb55e3..8a48e0080c 100644 --- a/src/mainboard/asus/f2a85-m/romstage.c +++ b/src/mainboard/asus/f2a85-m/romstage.c @@ -68,11 +68,6 @@ void board_BeforeAgesa(struct sysinfo *cb) u8 byte; pci_devfn_t dev; - if (CONFIG(POST_DEVICE_PCI_PCIE)) - hudson_pci_port80(); - else if (CONFIG(POST_DEVICE_LPC)) - hudson_lpc_port80(); - /* enable SIO LPC decode */ dev = PCI_DEV(0, 0x14, 3); byte = pci_read_config8(dev, 0x48); diff --git a/src/mainboard/bap/ode_e20XX/Kconfig b/src/mainboard/bap/ode_e20XX/Kconfig index a62fba82da..97593d5d78 100644 --- a/src/mainboard/bap/ode_e20XX/Kconfig +++ b/src/mainboard/bap/ode_e20XX/Kconfig @@ -22,6 +22,7 @@ config BOARD_SPECIFIC_OPTIONS select CPU_AMD_AGESA_FAMILY16_KB select NORTHBRIDGE_AMD_AGESA_FAMILY16_KB select SOUTHBRIDGE_AMD_AGESA_YANGTZE + select DEFAULT_POST_ON_LPC select HAVE_OPTION_TABLE select HAVE_PIRQ_TABLE select HAVE_MP_TABLE diff --git a/src/mainboard/bap/ode_e20XX/romstage.c b/src/mainboard/bap/ode_e20XX/romstage.c index ef7a7fb65b..505de38d9e 100644 --- a/src/mainboard/bap/ode_e20XX/romstage.c +++ b/src/mainboard/bap/ode_e20XX/romstage.c @@ -36,7 +36,5 @@ void board_BeforeAgesa(struct sysinfo *cb) pci_devfn_t dev = PCI_DEV(0, 0x14, 3); pci_write_config32(dev, 0x44, 0xff03ffd5); - hudson_lpc_port80(); - fintek_enable_serial(SERIAL_DEV1, CONFIG_TTYS0_BASE); } diff --git a/src/mainboard/bap/ode_e21XX/Kconfig b/src/mainboard/bap/ode_e21XX/Kconfig index 3705fb9615..bc5c131f79 100644 --- a/src/mainboard/bap/ode_e21XX/Kconfig +++ b/src/mainboard/bap/ode_e21XX/Kconfig @@ -25,6 +25,7 @@ config BOARD_SPECIFIC_OPTIONS select CPU_AMD_PI_00730F01 select NORTHBRIDGE_AMD_PI_00730F01 select SOUTHBRIDGE_AMD_PI_AVALON + select DEFAULT_POST_ON_LPC select HAVE_OPTION_TABLE select HAVE_PIRQ_TABLE select HAVE_MP_TABLE diff --git a/src/mainboard/bap/ode_e21XX/romstage.c b/src/mainboard/bap/ode_e21XX/romstage.c index e58f875f2f..de39f18a75 100644 --- a/src/mainboard/bap/ode_e21XX/romstage.c +++ b/src/mainboard/bap/ode_e21XX/romstage.c @@ -41,8 +41,6 @@ static void romstage_main_template(void) outb(0xD2, 0xcd6); outb(0x00, 0xcd7); - hudson_lpc_port80(); - if (!cpu_init_detectedx && boot_cpu()) { post_code(0x30); fintek_enable_serial(SERIAL_DEV1, CONFIG_TTYS0_BASE); diff --git a/src/mainboard/biostar/a68n_5200/romstage.c b/src/mainboard/biostar/a68n_5200/romstage.c index ddcf4d0f78..5d210fa4be 100644 --- a/src/mainboard/biostar/a68n_5200/romstage.c +++ b/src/mainboard/biostar/a68n_5200/romstage.c @@ -58,12 +58,6 @@ void board_BeforeAgesa(struct sysinfo *cb) pci_devfn_t dev = PCI_DEV(0, 0x14, 3); pci_write_config32(dev, 0x44, 0xff03ffd5); - if (CONFIG(POST_DEVICE_PCI_PCIE)) - hudson_pci_port80(); - - if (CONFIG(POST_DEVICE_LPC)) - hudson_lpc_port80(); - /* enable SIO LPC decode */ byte = pci_read_config8(dev, 0x48); byte |= 3; /* 2e, 2f */ diff --git a/src/mainboard/biostar/am1ml/Kconfig b/src/mainboard/biostar/am1ml/Kconfig index 4ea5ddc3c7..3c87965998 100644 --- a/src/mainboard/biostar/am1ml/Kconfig +++ b/src/mainboard/biostar/am1ml/Kconfig @@ -30,6 +30,7 @@ config BOARD_SPECIFIC_OPTIONS select HAVE_ACPI_TABLES select NORTHBRIDGE_AMD_AGESA_FAMILY16_KB select SOUTHBRIDGE_AMD_AGESA_YANGTZE + select DEFAULT_POST_ON_LPC select SUPERIO_ITE_IT8728F config MAINBOARD_DIR diff --git a/src/mainboard/biostar/am1ml/romstage.c b/src/mainboard/biostar/am1ml/romstage.c index c83a86585d..6c1581bbcb 100644 --- a/src/mainboard/biostar/am1ml/romstage.c +++ b/src/mainboard/biostar/am1ml/romstage.c @@ -89,8 +89,6 @@ void board_BeforeAgesa(struct sysinfo *cb) pci_devfn_t dev2 = PCI_DEV(0, 0x14, 3); pci_write_config32(dev2, 0x44, 0xff03ffd5); - hudson_lpc_port80(); - /* Enable the AcpiMmio space */ outb(0x24, 0xcd6); outb(0x1, 0xcd7); diff --git a/src/mainboard/gizmosphere/gizmo2/Kconfig b/src/mainboard/gizmosphere/gizmo2/Kconfig index 27a3b35c80..b066cdb8cf 100644 --- a/src/mainboard/gizmosphere/gizmo2/Kconfig +++ b/src/mainboard/gizmosphere/gizmo2/Kconfig @@ -22,6 +22,7 @@ config BOARD_SPECIFIC_OPTIONS select CPU_AMD_AGESA_FAMILY16_KB select NORTHBRIDGE_AMD_AGESA_FAMILY16_KB select SOUTHBRIDGE_AMD_AGESA_YANGTZE + select DEFAULT_POST_ON_LPC select HAVE_OPTION_TABLE select HAVE_PIRQ_TABLE select HAVE_MP_TABLE diff --git a/src/mainboard/gizmosphere/gizmo2/romstage.c b/src/mainboard/gizmosphere/gizmo2/romstage.c index c6563470ad..4676199b47 100644 --- a/src/mainboard/gizmosphere/gizmo2/romstage.c +++ b/src/mainboard/gizmosphere/gizmo2/romstage.c @@ -24,8 +24,6 @@ void board_BeforeAgesa(struct sysinfo *cb) pci_devfn_t dev = PCI_DEV(0, 0x14, 3); pci_write_config32(dev, 0x44, 0xff03ffd5); - hudson_lpc_port80(); - /* In Hudson RRG, PMIOxD2[5:4] is "Drive strength control for * LpcClk[1:0]". To be consistent with Parmer, setting to 4mA * even though the register is not documented in the Kabini BKDG. diff --git a/src/mainboard/hp/abm/Kconfig b/src/mainboard/hp/abm/Kconfig index a179dbe8ca..9e35163180 100644 --- a/src/mainboard/hp/abm/Kconfig +++ b/src/mainboard/hp/abm/Kconfig @@ -22,6 +22,7 @@ config BOARD_SPECIFIC_OPTIONS select CPU_AMD_AGESA_FAMILY16_KB select NORTHBRIDGE_AMD_AGESA_FAMILY16_KB select SOUTHBRIDGE_AMD_AGESA_YANGTZE + select DEFAULT_POST_ON_LPC select SUPERIO_NUVOTON_NCT5104D select HAVE_OPTION_TABLE select HAVE_PIRQ_TABLE diff --git a/src/mainboard/hp/abm/romstage.c b/src/mainboard/hp/abm/romstage.c index 2cc8d1bead..d7322c9eee 100644 --- a/src/mainboard/hp/abm/romstage.c +++ b/src/mainboard/hp/abm/romstage.c @@ -32,8 +32,6 @@ void board_BeforeAgesa(struct sysinfo *cb) pci_devfn_t dev = PCI_DEV(0, 0x14, 3); pci_write_config32(dev, 0x44, 0xff03ffd5); - hudson_lpc_port80(); - /* In Hudson RRG, PMIOxD2[5:4] is "Drive strength control for * LpcClk[1:0]". To be consistent with Parmer, setting to 4mA * even though the register is not documented in the Kabini BKDG. diff --git a/src/mainboard/hp/pavilion_m6_1035dx/Kconfig b/src/mainboard/hp/pavilion_m6_1035dx/Kconfig index 05ea52ff20..144b1138f6 100644 --- a/src/mainboard/hp/pavilion_m6_1035dx/Kconfig +++ b/src/mainboard/hp/pavilion_m6_1035dx/Kconfig @@ -22,6 +22,7 @@ config BOARD_SPECIFIC_OPTIONS select CPU_AMD_AGESA_FAMILY15_TN select NORTHBRIDGE_AMD_AGESA_FAMILY15_TN select SOUTHBRIDGE_AMD_AGESA_HUDSON + select DEFAULT_POST_ON_LPC select EC_COMPAL_ENE932 select HAVE_OPTION_TABLE select HAVE_PIRQ_TABLE diff --git a/src/mainboard/hp/pavilion_m6_1035dx/romstage.c b/src/mainboard/hp/pavilion_m6_1035dx/romstage.c index c05b87a0ec..0395566b74 100644 --- a/src/mainboard/hp/pavilion_m6_1035dx/romstage.c +++ b/src/mainboard/hp/pavilion_m6_1035dx/romstage.c @@ -18,5 +18,4 @@ void board_BeforeAgesa(struct sysinfo *cb) { - hudson_lpc_port80(); } diff --git a/src/mainboard/lenovo/g505s/Kconfig b/src/mainboard/lenovo/g505s/Kconfig index 815c7d5734..b220b97b06 100644 --- a/src/mainboard/lenovo/g505s/Kconfig +++ b/src/mainboard/lenovo/g505s/Kconfig @@ -22,6 +22,7 @@ config BOARD_SPECIFIC_OPTIONS select CPU_AMD_AGESA_FAMILY15_TN select NORTHBRIDGE_AMD_AGESA_FAMILY15_TN select SOUTHBRIDGE_AMD_AGESA_HUDSON + select DEFAULT_POST_ON_LPC select EC_COMPAL_ENE932 select HAVE_OPTION_TABLE select HAVE_MP_TABLE diff --git a/src/mainboard/lenovo/g505s/romstage.c b/src/mainboard/lenovo/g505s/romstage.c index c05b87a0ec..0395566b74 100644 --- a/src/mainboard/lenovo/g505s/romstage.c +++ b/src/mainboard/lenovo/g505s/romstage.c @@ -18,5 +18,4 @@ void board_BeforeAgesa(struct sysinfo *cb) { - hudson_lpc_port80(); } diff --git a/src/mainboard/msi/ms7721/romstage.c b/src/mainboard/msi/ms7721/romstage.c index 0266eff5c4..ebb875de63 100644 --- a/src/mainboard/msi/ms7721/romstage.c +++ b/src/mainboard/msi/ms7721/romstage.c @@ -117,11 +117,6 @@ void board_BeforeAgesa(struct sysinfo *cb) u8 byte; pci_devfn_t dev; - if (CONFIG(POST_DEVICE_PCI_PCIE)) - hudson_pci_port80(); - else if (CONFIG(POST_DEVICE_LPC)) - hudson_lpc_port80(); - /* enable SIO LPC decode */ dev = PCI_DEV(0, 0x14, 3); byte = pci_read_config8(dev, 0x48); diff --git a/src/mainboard/pcengines/apu2/Kconfig b/src/mainboard/pcengines/apu2/Kconfig index 5ecdb88991..b0360cd298 100644 --- a/src/mainboard/pcengines/apu2/Kconfig +++ b/src/mainboard/pcengines/apu2/Kconfig @@ -24,6 +24,7 @@ config BOARD_SPECIFIC_OPTIONS select CPU_AMD_PI_00730F01 select NORTHBRIDGE_AMD_PI_00730F01 select SOUTHBRIDGE_AMD_PI_AVALON + select DEFAULT_POST_ON_LPC select SUPERIO_NUVOTON_NCT5104D select HAVE_PIRQ_TABLE select HAVE_MP_TABLE diff --git a/src/mainboard/pcengines/apu2/romstage.c b/src/mainboard/pcengines/apu2/romstage.c index 6c97c576c1..3e2672ad70 100644 --- a/src/mainboard/pcengines/apu2/romstage.c +++ b/src/mainboard/pcengines/apu2/romstage.c @@ -52,8 +52,6 @@ void board_BeforeAgesa(struct sysinfo *cb) outb(0xd2, 0xcd6); outb(0x00, 0xcd7); - hudson_lpc_port80(); - post_code(0x30); early_lpc_init(); diff --git a/src/southbridge/amd/agesa/hudson/bootblock.c b/src/southbridge/amd/agesa/hudson/bootblock.c index 97e8803f48..6925393b06 100644 --- a/src/southbridge/amd/agesa/hudson/bootblock.c +++ b/src/southbridge/amd/agesa/hudson/bootblock.c @@ -77,6 +77,11 @@ void bootblock_soc_early_init(void) hudson_lpc_decode(); enable_acpimmio_decode_pm24(); + if (CONFIG(POST_DEVICE_PCI_PCIE)) + hudson_pci_port80(); + else if (CONFIG(POST_DEVICE_LPC)) + hudson_lpc_port80(); + dev = PCI_DEV(0, 0x14, 3); data = pci_read_config32(dev, LPC_IO_OR_MEM_DECODE_ENABLE); /* enable 0x2e/0x4e IO decoding for SuperIO */ diff --git a/src/southbridge/amd/pi/hudson/bootblock.c b/src/southbridge/amd/pi/hudson/bootblock.c index e9a9d337c4..ec8663dad1 100644 --- a/src/southbridge/amd/pi/hudson/bootblock.c +++ b/src/southbridge/amd/pi/hudson/bootblock.c @@ -79,6 +79,11 @@ void bootblock_soc_early_init(void) else enable_acpimmio_decode_pm04(); + if (CONFIG(POST_DEVICE_PCI_PCIE)) + hudson_pci_port80(); + else if (CONFIG(POST_DEVICE_LPC)) + hudson_lpc_port80(); + dev = PCI_DEV(0, 0x14, 3); data = pci_read_config32(dev, LPC_IO_OR_MEM_DECODE_ENABLE); /* enable 0x2e/0x4e IO decoding for SuperIO */ From 0bb644754d13868adfa0eb09c4c10d9f5a7f37b9 Mon Sep 17 00:00:00 2001 From: Matt DeVillier Date: Thu, 5 Dec 2019 17:08:58 -0600 Subject: [PATCH 0580/1242] mb/google/poppy: set detachable system type for nocturne/soraka Set the SMBIOS system type to detachable for nocturne and soraka variants, to allow the OS to correctly process events. Change-Id: Ie0ee5ea6666542c0bca2c264b2ed2e6135b78658 Signed-off-by: Matt DeVillier Reviewed-on: https://review.coreboot.org/c/coreboot/+/37540 Tested-by: build bot (Jenkins) Reviewed-by: Angel Pons --- src/mainboard/google/poppy/Kconfig | 2 ++ 1 file changed, 2 insertions(+) diff --git a/src/mainboard/google/poppy/Kconfig b/src/mainboard/google/poppy/Kconfig index 674fef9c8f..5a621bb940 100644 --- a/src/mainboard/google/poppy/Kconfig +++ b/src/mainboard/google/poppy/Kconfig @@ -181,6 +181,7 @@ config VARIANT_SPECIFIC_OPTIONS_NOCTURNE select EXCLUDE_NATIVE_SD_INTERFACE select MAINBOARD_HAS_SPI_TPM_CR50 select NO_FADT_8042 + select SYSTEM_TYPE_DETACHABLE select VARIANT_HAS_CAMERA_ACPI select GEO_SAR_ENABLE if CHROMEOS_WIFI_SAR @@ -198,6 +199,7 @@ config VARIANT_SPECIFIC_OPTIONS_SORAKA def_bool n select DRIVERS_I2C_MAX98927 select NO_FADT_8042 + select SYSTEM_TYPE_DETACHABLE select VARIANT_HAS_CAMERA_ACPI select MAINBOARD_HAS_I2C_TPM_CR50 From 57aa8e37dc90e7ce53947d1743a0ed47b200982b Mon Sep 17 00:00:00 2001 From: Wim Vervoorn Date: Fri, 6 Dec 2019 11:30:33 +0100 Subject: [PATCH 0581/1242] mb/intel/kblrvp: Remove hex values from VR settings Change the hex values in the VR configuration tables of the Intel Kaby Lake RVP boards to the same style that is used in the other mainboards. Also, correct some numbers in the comment tables that did not match the register values. The values in the tables haven't changed. BUG=N/A TEST=build Change-Id: I77af544d7d88143e19abedb12a13627779c705c6 Signed-off-by: Wim Vervoorn Reviewed-on: https://review.coreboot.org/c/coreboot/+/37550 Reviewed-by: Angel Pons Reviewed-by: Frans Hendriks Tested-by: build bot (Jenkins) --- .../kblrvp/variants/baseboard/devicetree.cb | 66 +++++++++---------- .../kblrvp/variants/rvp3/overridetree.cb | 14 ++-- .../kblrvp/variants/rvp7/overridetree.cb | 64 +++++++++--------- .../kblrvp/variants/rvp8/overridetree.cb | 62 ++++++++--------- 4 files changed, 105 insertions(+), 101 deletions(-) diff --git a/src/mainboard/intel/kblrvp/variants/baseboard/devicetree.cb b/src/mainboard/intel/kblrvp/variants/baseboard/devicetree.cb index 212721a90f..b14fe31db6 100644 --- a/src/mainboard/intel/kblrvp/variants/baseboard/devicetree.cb +++ b/src/mainboard/intel/kblrvp/variants/baseboard/devicetree.cb @@ -43,16 +43,16 @@ chip soc/intel/skylake # Enabling SLP_S3#, SLP_S4#, SLP_SUS and SLP_A Stretch # SLP_S3 Minimum Assertion Width. Values 0: 60us, 1: 1ms, 2: 50ms, 3: 2s - register "PmConfigSlpS3MinAssert" = "0x02" + register "PmConfigSlpS3MinAssert" = "2" # SLP_S4 Minimum Assertion Width. Values 0: default, 1: 1s, 2: 2s, 3: 3s, 4: 4s - register "PmConfigSlpS4MinAssert" = "0x04" + register "PmConfigSlpS4MinAssert" = "4" # SLP_SUS Minimum Assertion Width. Values 0: 0ms, 1: 500ms, 2: 1s, 3: 4s - register "PmConfigSlpSusMinAssert" = "0x03" + register "PmConfigSlpSusMinAssert" = "3" # SLP_A Minimum Assertion Width. Values 0: 0ms, 1: 4s, 2: 98ms, 3: 2s - register "PmConfigSlpAMinAssert" = "0x03" + register "PmConfigSlpAMinAssert" = "3" # VR Settings Configuration for 4 Domains @@ -60,7 +60,7 @@ chip soc/intel/skylake #| Domain/Setting | SA | IA | GTUS | GTS | #+----------------+-------+-------+-------+-------+ #| Psi1Threshold | 20A | 20A | 20A | 20A | - #| Psi2Threshold | 5A | 5A | 5A | 5A | + #| Psi2Threshold | 4A | 5A | 5A | 5A | #| Psi3Threshold | 1A | 1A | 1A | 1A | #| Psi3Enable | 1 | 1 | 1 | 1 | #| Psi4Enable | 1 | 1 | 1 | 1 | @@ -71,54 +71,54 @@ chip soc/intel/skylake #+----------------+-------+-------+-------+-------+ register "domain_vr_config[VR_SYSTEM_AGENT]" = "{ .vr_config_enable = 1, \ - .psi1threshold = 0x50, \ - .psi2threshold = 0x10, \ - .psi3threshold = 0x4, \ + .psi1threshold = VR_CFG_AMP(20), \ + .psi2threshold = VR_CFG_AMP(4), \ + .psi3threshold = VR_CFG_AMP(1), \ .psi3enable = 1, \ .psi4enable = 1, \ - .imon_slope = 0x0, \ - .imon_offset = 0x0, \ - .icc_max = 0x1C, \ - .voltage_limit = 0x5F0 \ + .imon_slope = 0, \ + .imon_offset = 0, \ + .icc_max = VR_CFG_AMP(7), \ + .voltage_limit = 1520 \ }" register "domain_vr_config[VR_IA_CORE]" = "{ .vr_config_enable = 1, \ - .psi1threshold = 0x50, \ - .psi2threshold = 0x14, \ - .psi3threshold = 0x4, \ + .psi1threshold = VR_CFG_AMP(20), \ + .psi2threshold = VR_CFG_AMP(5), \ + .psi3threshold = VR_CFG_AMP(1), \ .psi3enable = 1, \ .psi4enable = 1, \ - .imon_slope = 0x0, \ - .imon_offset = 0x0, \ - .icc_max = 0x88, \ - .voltage_limit = 0x5F0 \ + .imon_slope = 0, \ + .imon_offset = 0, \ + .icc_max = VR_CFG_AMP(34), \ + .voltage_limit = 1520 \ }" register "domain_vr_config[VR_GT_UNSLICED]" = "{ .vr_config_enable = 1, \ - .psi1threshold = 0x50, \ - .psi2threshold = 0x14, \ - .psi3threshold = 0x4, \ + .psi1threshold = VR_CFG_AMP(20), \ + .psi2threshold = VR_CFG_AMP(5), \ + .psi3threshold = VR_CFG_AMP(1), \ .psi3enable = 1, \ .psi4enable = 1, \ - .imon_slope = 0x0, \ - .imon_offset = 0x0, \ - .icc_max = 0x8C ,\ - .voltage_limit = 0x5F0 \ + .imon_slope = 0, \ + .imon_offset = 0, \ + .icc_max = VR_CFG_AMP(35),\ + .voltage_limit = 1520 \ }" register "domain_vr_config[VR_GT_SLICED]" = "{ .vr_config_enable = 1, \ - .psi1threshold = 0x50, \ - .psi2threshold = 0x14, \ - .psi3threshold = 0x4, \ + .psi1threshold = VR_CFG_AMP(20), \ + .psi2threshold = VR_CFG_AMP(5), \ + .psi3threshold = VR_CFG_AMP(1), \ .psi3enable = 1, \ .psi4enable = 1, \ - .imon_slope = 0x0, \ - .imon_offset = 0x0, \ - .icc_max = 0x8C, \ - .voltage_limit = 0x5F0 \ + .imon_slope = 0, \ + .imon_offset = 0, \ + .icc_max = VR_CFG_AMP(35), \ + .voltage_limit = 1520 \ }" # Send an extra VR mailbox command for the PS4 exit issue diff --git a/src/mainboard/intel/kblrvp/variants/rvp3/overridetree.cb b/src/mainboard/intel/kblrvp/variants/rvp3/overridetree.cb index c413cc6982..a269d01458 100644 --- a/src/mainboard/intel/kblrvp/variants/rvp3/overridetree.cb +++ b/src/mainboard/intel/kblrvp/variants/rvp3/overridetree.cb @@ -31,15 +31,15 @@ chip soc/intel/skylake #+----------------+-------+-------+-------+-------+ register "domain_vr_config[VR_SYSTEM_AGENT]" = "{ .vr_config_enable = 1, \ - .psi1threshold = 0x50, \ - .psi2threshold = 0x14, \ - .psi3threshold = 0x4, \ + .psi1threshold = VR_CFG_AMP(20), \ + .psi2threshold = VR_CFG_AMP(5), \ + .psi3threshold = VR_CFG_AMP(1), \ .psi3enable = 1, \ .psi4enable = 1, \ - .imon_slope = 0x0, \ - .imon_offset = 0x0, \ - .icc_max = 0x1C, \ - .voltage_limit = 0x5F0 \ + .imon_slope = 0, \ + .imon_offset = 0, \ + .icc_max = VR_CFG_AMP(7), \ + .voltage_limit = 1520 \ }" # Enable Root ports. diff --git a/src/mainboard/intel/kblrvp/variants/rvp7/overridetree.cb b/src/mainboard/intel/kblrvp/variants/rvp7/overridetree.cb index abd9886d17..07d7385943 100644 --- a/src/mainboard/intel/kblrvp/variants/rvp7/overridetree.cb +++ b/src/mainboard/intel/kblrvp/variants/rvp7/overridetree.cb @@ -22,65 +22,67 @@ chip soc/intel/skylake #| Domain/Setting | SA | IA | GTUS | GTS | #+----------------+-------+-------+-------+-------+ #| Psi1Threshold | 20A | 20A | 20A | 20A | - #| Psi2Threshold | 4A | 5A | 5A | 5A | + #| Psi2Threshold | 5A | 5A | 5A | 5A | #| Psi3Threshold | 1A | 1A | 1A | 1A | #| Psi3Enable | 1 | 1 | 1 | 1 | #| Psi4Enable | 1 | 1 | 1 | 1 | #| ImonSlope | 0 | 0 | 0 | 0 | #| ImonOffset | 0 | 0 | 0 | 0 | - #| IccMax | 7A | 34A | 35A | 35A | - #| VrVoltageLimit | 1.52V | 1.52V | 1.52V | 1.52V | + #| IccMax | Auto | Auto | Auto | Auto | + #| VrVoltageLimit*| 0 | 0 | 0 | 0 | #+----------------+-------+-------+-------+-------+ + #* VrVoltageLimit command not sent. + register "domain_vr_config[VR_SYSTEM_AGENT]" = "{ .vr_config_enable = 1, \ - .psi1threshold = 0x50, \ - .psi2threshold = 0x14, \ - .psi3threshold = 0x4, \ + .psi1threshold = VR_CFG_AMP(20), \ + .psi2threshold = VR_CFG_AMP(5), \ + .psi3threshold = VR_CFG_AMP(1), \ .psi3enable = 1, \ .psi4enable = 1, \ - .imon_slope = 0x0, \ - .imon_offset = 0x0, \ - .icc_max = 0x0, \ - .voltage_limit = 0x0 \ + .imon_slope = 0, \ + .imon_offset = 0, \ + .icc_max = 0, \ + .voltage_limit = 0 \ }" register "domain_vr_config[VR_IA_CORE]" = "{ .vr_config_enable = 1, \ - .psi1threshold = 0x50, \ - .psi2threshold = 0x14, \ - .psi3threshold = 0x4, \ + .psi1threshold = VR_CFG_AMP(20), \ + .psi2threshold = VR_CFG_AMP(5), \ + .psi3threshold = VR_CFG_AMP(1), \ .psi3enable = 1, \ .psi4enable = 1, \ - .imon_slope = 0x0, \ - .imon_offset = 0x0, \ - .icc_max = 0x0, \ - .voltage_limit = 0x0 \ + .imon_slope = 0, \ + .imon_offset = 0, \ + .icc_max = 0, \ + .voltage_limit = 0 \ }" register "domain_vr_config[VR_GT_UNSLICED]" = "{ .vr_config_enable = 1, \ - .psi1threshold = 0x50, \ - .psi2threshold = 0x14, \ - .psi3threshold = 0x4, \ + .psi1threshold = VR_CFG_AMP(20), \ + .psi2threshold = VR_CFG_AMP(5), \ + .psi3threshold = VR_CFG_AMP(1), \ .psi3enable = 1, \ .psi4enable = 1, \ - .imon_slope = 0x0, \ - .imon_offset = 0x0, \ - .icc_max = 0x0 ,\ - .voltage_limit = 0x0 \ + .imon_slope = 0, \ + .imon_offset = 0, \ + .icc_max = 0 ,\ + .voltage_limit = 0 \ }" register "domain_vr_config[VR_GT_SLICED]" = "{ .vr_config_enable = 1, \ - .psi1threshold = 0x50, \ - .psi2threshold = 0x14, \ - .psi3threshold = 0x4, \ + .psi1threshold = VR_CFG_AMP(20), \ + .psi2threshold = VR_CFG_AMP(5), \ + .psi3threshold = VR_CFG_AMP(1), \ .psi3enable = 1, \ .psi4enable = 1, \ - .imon_slope = 0x0, \ - .imon_offset = 0x0, \ - .icc_max = 0x0, \ - .voltage_limit = 0x0 \ + .imon_slope = 0, \ + .imon_offset = 0, \ + .icc_max = 0, \ + .voltage_limit = 0 \ }" # Enable Root ports. diff --git a/src/mainboard/intel/kblrvp/variants/rvp8/overridetree.cb b/src/mainboard/intel/kblrvp/variants/rvp8/overridetree.cb index 8dbaf685a8..46d7929d21 100644 --- a/src/mainboard/intel/kblrvp/variants/rvp8/overridetree.cb +++ b/src/mainboard/intel/kblrvp/variants/rvp8/overridetree.cb @@ -24,59 +24,61 @@ chip soc/intel/skylake #| Psi4Enable | 1 | 1 | 1 | 1 | 1 | #| ImonSlope | 0 | 0 | 0 | 0 | 0 | #| ImonOffset | 0 | 0 | 0 | 0 | 0 | - #| IccMax | 7A | 34A | 34A | 35A | 35A | - #| VrVoltageLimit | 1.52V | 1.52V | 1.52V | 1.52V | 1.52V | + #| IccMax | Auto | Auto | Auto | Auto | Auto | + #| VrVoltageLimit*| 0 | 0 | 0 | 0 | 0 | #+----------------+-------+-------+-------------+-------------+-------+ + #* VrVoltageLimit command not sent. + register "domain_vr_config[VR_SYSTEM_AGENT]" = "{ .vr_config_enable = 1, \ - .psi1threshold = 0x50, \ - .psi2threshold = 0x10, \ - .psi3threshold = 0x4, \ + .psi1threshold = VR_CFG_AMP(20), \ + .psi2threshold = VR_CFG_AMP(4), \ + .psi3threshold = VR_CFG_AMP(1), \ .psi3enable = 1, \ .psi4enable = 1, \ - .imon_slope = 0x0, \ - .imon_offset = 0x0, \ - .icc_max = 0x0, \ - .voltage_limit = 0x0 \ + .imon_slope = 0, \ + .imon_offset = 0, \ + .icc_max = 0, \ + .voltage_limit = 0 \ }" register "domain_vr_config[VR_IA_CORE]" = "{ .vr_config_enable = 1, \ - .psi1threshold = 0x50, \ - .psi2threshold = 0x14, \ - .psi3threshold = 0x4, \ + .psi1threshold = VR_CFG_AMP(20), \ + .psi2threshold = VR_CFG_AMP(5), \ + .psi3threshold = VR_CFG_AMP(1), \ .psi3enable = 1, \ .psi4enable = 1, \ - .imon_slope = 0x0, \ - .imon_offset = 0x0, \ - .icc_max = 0x0, \ - .voltage_limit = 0x0 \ + .imon_slope = 0, \ + .imon_offset = 0, \ + .icc_max = 0, \ + .voltage_limit = 0 \ }" register "domain_vr_config[VR_GT_UNSLICED]" = "{ .vr_config_enable = 1, \ - .psi1threshold = 0x50, \ - .psi2threshold = 0x14, \ - .psi3threshold = 0x4, \ + .psi1threshold = VR_CFG_AMP(20), \ + .psi2threshold = VR_CFG_AMP(5), \ + .psi3threshold = VR_CFG_AMP(1), \ .psi3enable = 1, \ .psi4enable = 1, \ - .imon_slope = 0x0, \ - .imon_offset = 0x0, \ - .icc_max = 0x0 ,\ - .voltage_limit = 0x0 \ + .imon_slope = 0, \ + .imon_offset = 0, \ + .icc_max = 0 ,\ + .voltage_limit = 0 \ }" register "domain_vr_config[VR_GT_SLICED]" = "{ .vr_config_enable = 1, \ - .psi1threshold = 0x50, \ - .psi2threshold = 0x14, \ - .psi3threshold = 0x4, \ + .psi1threshold = VR_CFG_AMP(20), \ + .psi2threshold = VR_CFG_AMP(5), \ + .psi3threshold = VR_CFG_AMP(1), \ .psi3enable = 1, \ .psi4enable = 1, \ - .imon_slope = 0x0, \ - .imon_offset = 0x0, \ - .icc_max = 0x0, \ - .voltage_limit = 0x0 \ + .imon_slope = 0, \ + .imon_offset = 0, \ + .icc_max = 0, \ + .voltage_limit = 0 \ }" # Enable Root port. From 14dd073e80bc076a6416b613758a592d77521ba2 Mon Sep 17 00:00:00 2001 From: Tim Wawrzynczak Date: Fri, 6 Dec 2019 09:28:29 -0700 Subject: [PATCH 0582/1242] EC sync: Properly handle VBERROR return codes from vb2api_ec_sync Some return codes were missed when implementing this initially; the vboot logic can require the system to command the EC to reboot to its RO, switch RW slots or it can require a poweroff of the SoC. This patch appropriately handles these return codes. BUG=b:145768046 BRANCH=firmware-hatch-12672.B TEST=ODM verified this patch fixes the issues seen. Change-Id: I2748cf626d49c255cb0274cb336b072dcdf8cded Signed-off-by: Tim Wawrzynczak Reviewed-on: https://review.coreboot.org/c/coreboot/+/37562 Tested-by: build bot (Jenkins) Reviewed-by: Julius Werner --- src/security/vboot/ec_sync.c | 34 ++++++++++++++++++++++++++++++++-- 1 file changed, 32 insertions(+), 2 deletions(-) diff --git a/src/security/vboot/ec_sync.c b/src/security/vboot/ec_sync.c index 8a3ba71d75..ecceff50f9 100644 --- a/src/security/vboot/ec_sync.c +++ b/src/security/vboot/ec_sync.c @@ -16,6 +16,7 @@ #include #include #include +#include #include #include #include @@ -60,9 +61,38 @@ void vboot_sync_ec(void) retval = vb2api_ec_sync(ctx); vboot_save_nvdata_only(ctx); - if (retval != VB2_SUCCESS) { - printk(BIOS_ERR, "EC software sync failed (%#x), rebooting\n", retval); + switch (retval) { + case VB2_SUCCESS: + break; + + case VBERROR_EC_REBOOT_TO_RO_REQUIRED: + printk(BIOS_INFO, "EC Reboot requested. Doing cold reboot\n"); + if (google_chromeec_reboot(0, EC_REBOOT_COLD, 0)) + printk(BIOS_EMERG, "Failed to get EC to cold reboot\n"); + + halt(); + break; + + /* Only for EC-EFS */ + case VBERROR_EC_REBOOT_TO_SWITCH_RW: + printk(BIOS_INFO, "Switch EC slot requested. Doing cold reboot\n"); + if (google_chromeec_reboot(0, EC_REBOOT_COLD, + EC_REBOOT_FLAG_SWITCH_RW_SLOT)) + printk(BIOS_EMERG, "Failed to get EC to cold reboot\n"); + + halt(); + break; + + case VBERROR_REBOOT_REQUIRED: + printk(BIOS_INFO, "Reboot requested. Doing warm reboot\n"); vboot_reboot(); + break; + + default: + printk(BIOS_ERR, "EC software sync failed (%#x)," + " rebooting\n", retval); + vboot_reboot(); + break; } timestamp_add_now(TS_END_EC_SYNC); From 1bb330348dbf3dd709bf66f73358d6b97bf02838 Mon Sep 17 00:00:00 2001 From: Arthur Heymans Date: Tue, 26 Nov 2019 14:13:02 +0100 Subject: [PATCH 0583/1242] Documentation: Remove redundant 'documentation' We are already in documentation so it should be obvious that other links point to other documentation. Change-Id: I7a021a09bdb88418ec85dbf433465f26445057d0 Signed-off-by: Arthur Heymans Reviewed-on: https://review.coreboot.org/c/coreboot/+/37241 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber --- Documentation/index.md | 20 ++++++++++---------- 1 file changed, 10 insertions(+), 10 deletions(-) diff --git a/Documentation/index.md b/Documentation/index.md index 8a996b917d..3ed6bd37ee 100644 --- a/Documentation/index.md +++ b/Documentation/index.md @@ -174,17 +174,17 @@ Contents: * [GPIO toggling in ACPI AML](acpi/gpio.md) * [Adding devices to a device tree](acpi/devicetree.md) * [Native Graphics Initialization with libgfxinit](gfx/libgfxinit.md) -* [Display panel-specific documentation](gfx/display-panel.md) -* [Architecture-specific documentation](arch/index.md) -* [Platform independend drivers documentation](drivers/index.md) -* [Northbridge-specific documentation](northbridge/index.md) -* [System on Chip-specific documentation](soc/index.md) -* [Mainboard-specific documentation](mainboard/index.md) -* [Payload-specific documentation](lib/payloads/index.md) -* [Library-specific documentation](lib/index.md) +* [Display panel](gfx/display-panel.md) +* [CPU Architecture](arch/index.md) +* [Platform independend drivers](drivers/index.md) +* [Northbridge](northbridge/index.md) +* [System on Chip](soc/index.md) +* [Mainboard](mainboard/index.md) +* [Payloads](lib/payloads/index.md) +* [Libraries](lib/index.md) * [Security](security/index.md) -* [SuperIO-specific documentation](superio/index.md) -* [Vendorcode-specific documentation](vendorcode/index.md) +* [SuperIO](superio/index.md) +* [Vendorcode](vendorcode/index.md) * [Utilities](util.md) * [Release notes for past releases](releases/index.md) * [Flashing firmware tutorial](flash_tutorial/index.md) From edcce0753163b60f44e27df084ff28f41fbcd8be Mon Sep 17 00:00:00 2001 From: Arthur Heymans Date: Tue, 26 Nov 2019 14:18:11 +0100 Subject: [PATCH 0584/1242] Documentation: Move ACPI documentation in a subindex Change-Id: I17c5263674b805a73d98aaa3e7090083905e37ef Signed-off-by: Arthur Heymans Reviewed-on: https://review.coreboot.org/c/coreboot/+/37242 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber --- Documentation/acpi/index.md | 11 +++++++++++ Documentation/index.md | 3 +-- 2 files changed, 12 insertions(+), 2 deletions(-) create mode 100644 Documentation/acpi/index.md diff --git a/Documentation/acpi/index.md b/Documentation/acpi/index.md new file mode 100644 index 0000000000..8add8db387 --- /dev/null +++ b/Documentation/acpi/index.md @@ -0,0 +1,11 @@ +# ACPI-specific documentation + +This section contains documentation about coreboot on ACPI. + +## GPIO + +- [GPIO toggling in ACPI AML](gpio.md) + +## devicetree + +- [Adding devices to a device tree](devicetree.md) diff --git a/Documentation/index.md b/Documentation/index.md index 3ed6bd37ee..bfc9cea992 100644 --- a/Documentation/index.md +++ b/Documentation/index.md @@ -171,8 +171,7 @@ Contents: * [Payloads](payloads.md) * [Distributions](distributions.md) * [Technotes](technotes/index.md) -* [GPIO toggling in ACPI AML](acpi/gpio.md) -* [Adding devices to a device tree](acpi/devicetree.md) +* [ACPI](acpi/index.md) * [Native Graphics Initialization with libgfxinit](gfx/libgfxinit.md) * [Display panel](gfx/display-panel.md) * [CPU Architecture](arch/index.md) From 3b34db6c0f1a2758e06faff8a72c4afd073aa056 Mon Sep 17 00:00:00 2001 From: Peichao Wang Date: Wed, 4 Dec 2019 07:51:27 +0800 Subject: [PATCH 0585/1242] mb/google/octopus: Create Foob variant This commit creates a foob variant for Octopus. The initial settings override the baseboard was copied from variant phaser. BUG=b:144890301 BRANCH=octopus TEST=emerge-octopus coreboot Signed-off-by: Peichao Wang Change-Id: Ibcdda4dd0846612f5e98ab454db7144c1caf0507 Reviewed-on: https://review.coreboot.org/c/coreboot/+/37456 Reviewed-by: Henry Sun Reviewed-by: Marco Chen Tested-by: build bot (Jenkins) --- src/mainboard/google/octopus/Kconfig | 2 + src/mainboard/google/octopus/Kconfig.name | 6 + .../google/octopus/variants/foob/Makefile.inc | 3 + .../google/octopus/variants/foob/gpio.c | 44 +++++ .../foob/include/variant/acpi/dptf.asl | 16 ++ .../variants/foob/include/variant/ec.h | 21 +++ .../variants/foob/include/variant/gpio.h | 21 +++ .../octopus/variants/foob/overridetree.cb | 164 ++++++++++++++++++ 8 files changed, 277 insertions(+) create mode 100644 src/mainboard/google/octopus/variants/foob/Makefile.inc create mode 100644 src/mainboard/google/octopus/variants/foob/gpio.c create mode 100644 src/mainboard/google/octopus/variants/foob/include/variant/acpi/dptf.asl create mode 100644 src/mainboard/google/octopus/variants/foob/include/variant/ec.h create mode 100644 src/mainboard/google/octopus/variants/foob/include/variant/gpio.h create mode 100644 src/mainboard/google/octopus/variants/foob/overridetree.cb diff --git a/src/mainboard/google/octopus/Kconfig b/src/mainboard/google/octopus/Kconfig index 78b2eba03b..3139716808 100644 --- a/src/mainboard/google/octopus/Kconfig +++ b/src/mainboard/google/octopus/Kconfig @@ -64,6 +64,7 @@ config VARIANT_DIR default "garg" if BOARD_GOOGLE_GARG default "dood" if BOARD_GOOGLE_DOOD default "lick" if BOARD_GOOGLE_LICK + default "foob" if BOARD_GOOGLE_FOOB config DEVICETREE string @@ -87,6 +88,7 @@ config MAINBOARD_PART_NUMBER default "Garg" if BOARD_GOOGLE_GARG default "Dood" if BOARD_GOOGLE_DOOD default "Lick" if BOARD_GOOGLE_LICK + default "Foob" if BOARD_GOOGLE_FOOB config MAINBOARD_FAMILY string diff --git a/src/mainboard/google/octopus/Kconfig.name b/src/mainboard/google/octopus/Kconfig.name index c837365239..6e3dbf493c 100644 --- a/src/mainboard/google/octopus/Kconfig.name +++ b/src/mainboard/google/octopus/Kconfig.name @@ -70,3 +70,9 @@ config BOARD_GOOGLE_DOOD select BASEBOARD_OCTOPUS_LAPTOP select BOARD_GOOGLE_BASEBOARD_OCTOPUS select NHLT_DA7219 if INCLUDE_NHLT_BLOBS + +config BOARD_GOOGLE_FOOB + bool "-> Foob" + select BASEBOARD_OCTOPUS_LAPTOP + select BOARD_GOOGLE_BASEBOARD_OCTOPUS + select NHLT_DA7219 if INCLUDE_NHLT_BLOBS diff --git a/src/mainboard/google/octopus/variants/foob/Makefile.inc b/src/mainboard/google/octopus/variants/foob/Makefile.inc new file mode 100644 index 0000000000..9fb63f5f43 --- /dev/null +++ b/src/mainboard/google/octopus/variants/foob/Makefile.inc @@ -0,0 +1,3 @@ +bootblock-y += gpio.c + +ramstage-y += gpio.c diff --git a/src/mainboard/google/octopus/variants/foob/gpio.c b/src/mainboard/google/octopus/variants/foob/gpio.c new file mode 100644 index 0000000000..27ce0eea61 --- /dev/null +++ b/src/mainboard/google/octopus/variants/foob/gpio.c @@ -0,0 +1,44 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2019 Google LLC + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the + * GNU General Public License for more details. + */ + +#include +#include +#include +#include +#include +#include + +static const struct pad_config default_override_table[] = { + PAD_NC(GPIO_52, UP_20K), + PAD_NC(GPIO_53, UP_20K), + PAD_NC(GPIO_67, UP_20K), + PAD_NC(GPIO_117, UP_20K), + PAD_NC(GPIO_143, UP_20K), + + /* EN_PP3300_TOUCHSCREEN */ + PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_146, 0, DEEP, NONE, Tx0RxDCRx0, + DISPUPD), + + PAD_NC(GPIO_161, DN_20K), + + PAD_NC(GPIO_213, DN_20K), + PAD_NC(GPIO_214, DN_20K), +}; + +const struct pad_config *variant_override_gpio_table(size_t *num) +{ + *num = ARRAY_SIZE(default_override_table); + return default_override_table; +} diff --git a/src/mainboard/google/octopus/variants/foob/include/variant/acpi/dptf.asl b/src/mainboard/google/octopus/variants/foob/include/variant/acpi/dptf.asl new file mode 100644 index 0000000000..4f6497ab2d --- /dev/null +++ b/src/mainboard/google/octopus/variants/foob/include/variant/acpi/dptf.asl @@ -0,0 +1,16 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2019 Google LLC + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include diff --git a/src/mainboard/google/octopus/variants/foob/include/variant/ec.h b/src/mainboard/google/octopus/variants/foob/include/variant/ec.h new file mode 100644 index 0000000000..260d7d43b2 --- /dev/null +++ b/src/mainboard/google/octopus/variants/foob/include/variant/ec.h @@ -0,0 +1,21 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2019 Google LLC + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef MAINBOARD_EC_H +#define MAINBOARD_EC_H + +#include + +#endif diff --git a/src/mainboard/google/octopus/variants/foob/include/variant/gpio.h b/src/mainboard/google/octopus/variants/foob/include/variant/gpio.h new file mode 100644 index 0000000000..750b0d4ccc --- /dev/null +++ b/src/mainboard/google/octopus/variants/foob/include/variant/gpio.h @@ -0,0 +1,21 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2019 Google LLC + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the + * GNU General Public License for more details. + */ + +#ifndef MAINBOARD_GPIO_H +#define MAINBOARD_GPIO_H + +#include + +#endif /* MAINBOARD_GPIO_H */ diff --git a/src/mainboard/google/octopus/variants/foob/overridetree.cb b/src/mainboard/google/octopus/variants/foob/overridetree.cb new file mode 100644 index 0000000000..b1311737dc --- /dev/null +++ b/src/mainboard/google/octopus/variants/foob/overridetree.cb @@ -0,0 +1,164 @@ +chip soc/intel/apollolake + + # EMMC Tx CMD Delay + # Refer to EDS-Vol2-16.32. + # [14:8] steps of delay for DDR mode, each 125ps. + # [6:0] steps of delay for SDR mode, each 125ps. + register "emmc_tx_cmd_cntl" = "0x505" + + # EMMC TX DATA Delay 1 + # Refer to EDS-Vol2-16.33. + # [14:8] steps of delay for HS400, each 125ps. + # [6:0] steps of delay for SDR104/HS200, each 125ps. + register "emmc_tx_data_cntl1" = "0x0b0c" + + # EMMC TX DATA Delay 2 + # Refer to EDS-Vol2-16.34. + # [30:24] steps of delay for SDR50, each 125ps. + # [22:16] steps of delay for DDR50, each 125ps. + # [14:8] steps of delay for SDR25/HS50, each 125ps. + # [6:0] steps of delay for SDR12, each 125ps. + register "emmc_tx_data_cntl2" = "0x1c282929" + + # EMMC RX CMD/DATA Delay 1 + # Refer to EDS-Vol2-16.35. + # [30:24] steps of delay for SDR50, each 125ps. + # [22:16] steps of delay for DDR50, each 125ps. + # [14:8] steps of delay for SDR25/HS50, each 125ps. + # [6:0] steps of delay for SDR12, each 125ps. + register "emmc_rx_cmd_data_cntl1" = "0x00181b1b" + + # EMMC RX CMD/DATA Delay 2 + # Refer to EDS-Vol2-16.37. + # [17:16] stands for Rx Clock before Output Buffer + # [14:8] steps of delay for Auto Tuning Mode, each 125ps. + # [6:0] steps of delay for HS200, each 125ps. + register "emmc_rx_cmd_data_cntl2" = "0x10028" + + # EMMC Rx Strobe Delay + # Refer to EDS-Vol2-16.36. + # [14:8] Rx Strobe Delay DLL 1(HS400 Mode), each 125ps. + # [6:0] Rx Strobe Delay DLL 2(HS400 Mode), each 125ps. + register "emmc_rx_strobe_cntl" = "0x0b0b" + + # Intel Common SoC Config + #+-------------------+---------------------------+ + #| Field | Value | + #+-------------------+---------------------------+ + #| GSPI0 | cr50 TPM. Early init is | + #| | required to set up a BAR | + #| | for TPM communication | + #| | before memory is up | + #| I2C0 | Digitizer | + #| I2C5 | Audio | + #| I2C6 | Trackpad | + #| I2C7 | Touchscreen | + #+-------------------+---------------------------+ + register "common_soc_config" = "{ + .gspi[0] = { + .speed_mhz = 1, + .early_init = 1, + }, + .i2c[0] = { + .speed = I2C_SPEED_FAST, + .rise_time_ns = 66, + .fall_time_ns = 90, + }, + .i2c[5] = { + .speed = I2C_SPEED_FAST, + .rise_time_ns = 104, + .fall_time_ns = 52, + }, + .i2c[6] = { + .speed = I2C_SPEED_FAST, + .rise_time_ns = 66, + .fall_time_ns = 90, + .data_hold_time_ns = 350, + }, + .i2c[7] = { + .speed = I2C_SPEED_FAST, + .rise_time_ns = 76, + .fall_time_ns = 164, + }, + }" + + device domain 0 on + device pci 16.0 on + chip drivers/i2c/hid + register "generic.hid" = ""WCOM50C1"" + register "generic.desc" = ""WCOM Digitizer"" + register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPIO_139_IRQ)" + register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_140)" + register "generic.reset_delay_ms" = "20" + register "generic.has_power_resource" = "1" + register "hid_desc_reg_offset" = "0x1" + device i2c 0x9 on end + end + end # - I2C 0 + device pci 17.1 on + chip drivers/i2c/da7219 + register "irq" = "ACPI_IRQ_LEVEL_LOW(GPIO_137_IRQ)" + register "btn_cfg" = "50" + register "mic_det_thr" = "500" + register "jack_ins_deb" = "20" + register "jack_det_rate" = ""32ms_64ms"" + register "jack_rem_deb" = "1" + register "a_d_btn_thr" = "0xa" + register "d_b_btn_thr" = "0x16" + register "b_c_btn_thr" = "0x21" + register "c_mic_btn_thr" = "0x3e" + register "btn_avg" = "4" + register "adc_1bit_rpt" = "1" + register "micbias_lvl" = "2600" + register "mic_amp_in_sel" = ""diff"" + device i2c 1a on end + end + end # - I2C 5 + device pci 17.2 on + chip drivers/i2c/generic + register "hid" = ""ELAN0000"" + register "desc" = ""ELAN Touchpad"" + register "irq" = "ACPI_IRQ_WAKE_EDGE_LOW(GPIO_135_IRQ)" + register "wake" = "GPE0_DW3_27" + register "probed" = "1" + device i2c 15 on end + end + chip drivers/i2c/hid + register "generic.hid" = ""PNP0C50"" + register "generic.desc" = ""Synaptics Touchpad"" + register "generic.irq" = "ACPI_IRQ_WAKE_EDGE_LOW(GPIO_135_IRQ)" + register "generic.wake" = "GPE0_DW3_27" + register "generic.probed" = "1" + register "hid_desc_reg_offset" = "0x20" + device i2c 0x2c on end + end + end # - I2C 6 + device pci 17.3 on + chip drivers/i2c/generic + register "hid" = ""ELAN0001"" + register "desc" = ""ELAN Touchscreen"" + register "irq" = "ACPI_IRQ_EDGE_LOW(GPIO_212_IRQ)" + register "probed" = "1" + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_105)" + register "reset_delay_ms" = "20" + register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_146)" + register "enable_delay_ms" = "1" + register "has_power_resource" = "1" + device i2c 10 on end + end + chip drivers/i2c/hid + register "generic.hid" = ""SYTS7817"" + register "generic.desc" = ""Synaptics Touchscreen"" + register "generic.irq" = "ACPI_IRQ_EDGE_LOW(GPIO_212_IRQ)" + register "generic.probed" = "1" + register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_105)" + register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_146)" + register "generic.reset_delay_ms" = "45" + register "generic.has_power_resource" = "1" + register "generic.disable_gpio_export_in_crs" = "1" + register "hid_desc_reg_offset" = "0x20" + device i2c 20 on end + end + end # - I2C 7 + end +end From 96e2a5da34eda9a9c9c78c475696915f2b23d2ef Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Sun, 1 Dec 2019 21:37:58 +0100 Subject: [PATCH 0586/1242] soc/intel/bsw/gpio: Factor out GPI macros This patch simplifies some GPIO macros by removing redundant code. Also, for the sake of completeness, add two missing macros. Change-Id: I838efe8b26f60d3e059f4ce18c116aefbc0b0400 Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/37404 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber --- src/soc/intel/braswell/include/soc/gpio.h | 31 +++++++---------------- 1 file changed, 9 insertions(+), 22 deletions(-) diff --git a/src/soc/intel/braswell/include/soc/gpio.h b/src/soc/intel/braswell/include/soc/gpio.h index 2240ae1e4b..24318c5e5e 100644 --- a/src/soc/intel/braswell/include/soc/gpio.h +++ b/src/soc/intel/braswell/include/soc/gpio.h @@ -228,30 +228,17 @@ #define PAD_CONFIG1_CSEN 0x0DC00000 #define PAD_CONFIG1_DEFAULT1 0x05C00020 -#define GPIO_INPUT_NO_PULL \ - { .pad_conf0 = PAD_PULL_DISABLE | PAD_GPIO_ENABLE \ - | PAD_CONFIG0_GPI_DEFAULT, \ +#define GPIO_INPUT_PULL(pull) \ + { .pad_conf0 = pull | PAD_GPIO_ENABLE | PAD_CONFIG0_GPI_DEFAULT, \ .pad_conf1 = PAD_CONFIG1_DEFAULT0 } -#define GPIO_INPUT_PU_20K \ - { .pad_conf0 = PAD_PULL_UP_20K | PAD_GPIO_ENABLE \ - | PAD_CONFIG0_GPI_DEFAULT, \ - .pad_conf1 = PAD_CONFIG1_DEFAULT0 } - -#define GPIO_INPUT_PD_5K \ - { .pad_conf0 = PAD_PULL_DOWN_5K | PAD_GPIO_ENABLE \ - | PAD_CONFIG0_GPI_DEFAULT, \ - .pad_conf1 = PAD_CONFIG1_DEFAULT0 } - -#define GPIO_INPUT_PD_20K \ - { .pad_conf0 = PAD_PULL_DOWN_20K | PAD_GPIO_ENABLE \ - | PAD_CONFIG0_GPI_DEFAULT, \ - .pad_conf1 = PAD_CONFIG1_DEFAULT0 } - -#define GPIO_INPUT_PU_5K \ - { .pad_conf0 = PAD_PULL_UP_5K | PAD_GPIO_ENABLE \ - | PAD_CONFIG0_GPI_DEFAULT, \ - .pad_conf1 = PAD_CONFIG1_DEFAULT0 } +#define GPIO_INPUT_NO_PULL GPIO_INPUT_PULL(PAD_PULL_DISABLE) +#define GPIO_INPUT_PU_20K GPIO_INPUT_PULL(PAD_PULL_UP_20K) +#define GPIO_INPUT_PU_5K GPIO_INPUT_PULL(PAD_PULL_UP_5K) +#define GPIO_INPUT_PU_1K GPIO_INPUT_PULL(PAD_PULL_UP_1K) +#define GPIO_INPUT_PD_20K GPIO_INPUT_PULL(PAD_PULL_DOWN_20K) +#define GPIO_INPUT_PD_5K GPIO_INPUT_PULL(PAD_PULL_DOWN_5K) +#define GPIO_INPUT_PD_1K GPIO_INPUT_PULL(PAD_PULL_DOWN_1K) #define GPI(int_type, int_sel, term, int_msk, glitch_cfg, wake_msk, gpe_val) { \ .pad_conf0 = PAD_INT_SEL(int_sel) | PAD_GFCFG(glitch_cfg) \ From 0b82b3d6fdc413db5b65b08adc0d2a5ddc6687ad Mon Sep 17 00:00:00 2001 From: Johanna Schander Date: Fri, 6 Dec 2019 18:32:58 +0100 Subject: [PATCH 0587/1242] 3rdparts/fsp: Update fsp submodule The name for the CoffeeLake FSP.fd was changed to Fsp.fd. Therefore the CoffeLake / WhiskeyLake default path was changed. Change-Id: I0f51e378fcaacb25392d8940a342fc968c730157 Signed-off-by: Johanna Schander Reviewed-on: https://review.coreboot.org/c/coreboot/+/37564 Reviewed-by: Felix Singer Reviewed-by: Nico Huber Tested-by: build bot (Jenkins) --- 3rdparty/fsp | 2 +- src/soc/intel/cannonlake/Kconfig | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/3rdparty/fsp b/3rdparty/fsp index 59964173e1..0bc2b07eab 160000 --- a/3rdparty/fsp +++ b/3rdparty/fsp @@ -1 +1 @@ -Subproject commit 59964173e18950debcc6b8856c5c928935ce0b4f +Subproject commit 0bc2b07eab29a8a75cd084963c285ee5434e6666 diff --git a/src/soc/intel/cannonlake/Kconfig b/src/soc/intel/cannonlake/Kconfig index 5c91ac142f..c82660e6dc 100644 --- a/src/soc/intel/cannonlake/Kconfig +++ b/src/soc/intel/cannonlake/Kconfig @@ -310,7 +310,7 @@ config FSP_HEADER_PATH config FSP_FD_PATH string depends on FSP_USE_REPO - default "3rdparty/fsp/CoffeeLakeFspBinPkg/FSP.fd" if SOC_INTEL_COFFEELAKE || SOC_INTEL_WHISKEYLAKE + default "3rdparty/fsp/CoffeeLakeFspBinPkg/Fsp.fd" if SOC_INTEL_COFFEELAKE || SOC_INTEL_WHISKEYLAKE config SOC_INTEL_CANNONLAKE_DEBUG_CONSENT int "Debug Consent for CNL" From 808f5c384974b7c9679165aff15057cfb9a0d5f2 Mon Sep 17 00:00:00 2001 From: Johanna Schander Date: Fri, 6 Dec 2019 10:57:25 +0100 Subject: [PATCH 0588/1242] drivers/intel/fsp2_0: Allow to add FSP binaries from repo for IceLake This commit is adding a dependency check for the FSP_USE_REPO config option which so far was not able to deal with IceLake systems. Change-Id: I29faa8d3acff5680b611951fc193d33f514dc0d3 Signed-off-by: Johanna Schander Reviewed-on: https://review.coreboot.org/c/coreboot/+/37561 Reviewed-by: Nico Huber Tested-by: build bot (Jenkins) --- src/drivers/intel/fsp2_0/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/drivers/intel/fsp2_0/Kconfig b/src/drivers/intel/fsp2_0/Kconfig index d9d7fb2060..824fd0b896 100644 --- a/src/drivers/intel/fsp2_0/Kconfig +++ b/src/drivers/intel/fsp2_0/Kconfig @@ -55,7 +55,7 @@ config FSP_USE_REPO depends on ADD_FSP_BINARIES depends on SOC_INTEL_APOLLOLAKE || SOC_INTEL_SKYLAKE || \ SOC_INTEL_KABYLAKE || SOC_INTEL_COFFEELAKE || \ - SOC_INTEL_WHISKEYLAKE + SOC_INTEL_ICELAKE || SOC_INTEL_WHISKEYLAKE help When selecting this option, the SoC must set FSP_HEADER_PATH and FSP_FD_PATH correctly so FSP splitting works. From c79efa822d8738d02bc989ef2b99a4dc0f6fb128 Mon Sep 17 00:00:00 2001 From: Elyes HAOUAS Date: Sat, 7 Dec 2019 17:10:16 +0100 Subject: [PATCH 0589/1242] util/lint: Update spelling.txt to latest linux version Change-Id: Ife90b61d04e32f307a688d81922bdcf6fa57cfc9 Signed-off-by: Elyes HAOUAS Reviewed-on: https://review.coreboot.org/c/coreboot/+/37572 Reviewed-by: Martin Roth Tested-by: build bot (Jenkins) --- util/lint/spelling.txt | 219 +++++++++++++++++++++++++++++++++++++++++ 1 file changed, 219 insertions(+) diff --git a/util/lint/spelling.txt b/util/lint/spelling.txt index 118a435702..1f2752b2ee 100644 --- a/util/lint/spelling.txt +++ b/util/lint/spelling.txt @@ -11,6 +11,10 @@ abandonning||abandoning abigious||ambiguous abitrate||arbitrate +abnornally||abnormally +abnrormal||abnormal +abord||abort +aboslute||absolute abov||above abreviated||abbreviated absense||absence @@ -26,6 +30,7 @@ accessable||accessible accesss||access accidentaly||accidentally accidentually||accidentally +acclerated||accelerated accoding||according accomodate||accommodate accomodates||accommodates @@ -37,6 +42,7 @@ accquired||acquired accross||across acessable||accessible acess||access +acessing||accessing achitecture||architecture acient||ancient acitions||actions @@ -50,6 +56,7 @@ activete||activate actived||activated actualy||actually acumulating||accumulating +acumulative||accumulative acumulator||accumulator adapater||adapter addional||additional @@ -59,12 +66,15 @@ addres||address adddress||address addreses||addresses addresss||address +addrress||address aditional||additional aditionally||additionally aditionaly||additionally adminstrative||administrative adress||address adresses||addresses +adrresses||addresses +advertisment||advertisement adviced||advised afecting||affecting againt||against @@ -78,6 +88,7 @@ algorith||algorithm algorithmical||algorithmically algoritm||algorithm algoritms||algorithms +algorithmn||algorithm algorrithm||algorithm algorritm||algorithm aligment||alignment @@ -96,11 +107,15 @@ alogrithm||algorithm alot||a lot alow||allow alows||allows +alredy||already altough||although alue||value ambigious||ambiguous +ambigous||ambiguous amoung||among amout||amount +amplifer||amplifier +amplifyer||amplifier an union||a union an user||a user an userspace||a userspace @@ -139,6 +154,7 @@ artillary||artillery asign||assign asser||assert assertation||assertion +assertting||asserting assiged||assigned assigment||assignment assigments||assignments @@ -146,11 +162,15 @@ assistent||assistant assocation||association associcated||associated assotiated||associated +asssert||assert assum||assume assumtpion||assumption asuming||assuming asycronous||asynchronous asynchnous||asynchronous +asynchromous||asynchronous +asymetric||asymmetric +asymmeric||asymmetric atomatically||automatically atomicly||atomically atempt||attempt @@ -158,8 +178,11 @@ attachement||attachment attched||attached attemps||attempts attemping||attempting +attepmpt||attempt +attnetion||attention attruibutes||attributes authentification||authentication +authenicated||authenticated automaticaly||automatically automaticly||automatically automatize||automate @@ -173,6 +196,7 @@ avaible||available availabe||available availabled||available availablity||availability +availaible||available availale||available availavility||availability availble||available @@ -206,9 +230,14 @@ boardcast||broadcast borad||board boundry||boundary brievely||briefly +brigde||bridge +broadcase||broadcast broadcat||broadcast +bufufer||buffer cacluated||calculated +caculate||calculate caculation||calculation +cadidate||candidate calender||calendar calescing||coalescing calle||called @@ -218,16 +247,20 @@ calulate||calculate cancelation||cancellation cancle||cancel capabilites||capabilities +capabilties||capabilities capabilty||capability capabitilies||capabilities +capablity||capability capatibilities||capabilities capapbilities||capabilities +caputure||capture carefuly||carefully cariage||carriage catagory||category cehck||check challange||challenge challanges||challenges +chache||cache chanell||channel changable||changeable chanined||chained @@ -241,6 +274,7 @@ charaters||characters charcter||character chcek||check chck||check +checksumed||checksummed checksuming||checksumming childern||children childs||children @@ -256,7 +290,9 @@ claread||cleared clared||cleared closeing||closing clustred||clustered +cnfiguration||configuration coexistance||coexistence +colescing||coalescing collapsable||collapsible colorfull||colorful comand||command @@ -273,6 +309,7 @@ comsumer||consumer comsuming||consuming compability||compatibility compaibility||compatibility +comparsion||comparison compatability||compatibility compatable||compatible compatibiliy||compatibility @@ -286,15 +323,21 @@ completly||completely complient||compliant componnents||components compoment||component +comppatible||compatible compres||compress compresion||compression comression||compression comunication||communication conbination||combination conditionaly||conditionally +conditon||condition conected||connected +conector||connector connecetd||connected +configration||configuration configuartion||configuration +configuation||configuration +configued||configured configuratoin||configuration configuraton||configuration configuretion||configuration @@ -311,11 +354,13 @@ containts||contains contaisn||contains contant||contact contence||contents +contiguos||contiguous continious||continuous continous||continuous continously||continuously continueing||continuing contraints||constraints +contruct||construct contol||control contoller||controller controled||controlled @@ -343,10 +388,14 @@ cylic||cyclic dafault||default deafult||default deamon||daemon +debouce||debounce decompres||decompress +decsribed||described decription||description dectected||detected defailt||default +deferal||deferral +deffered||deferred defferred||deferred definate||definite definately||definitely @@ -373,13 +422,16 @@ depreacte||deprecate desactivate||deactivate desciptor||descriptor desciptors||descriptors +descripto||descriptor descripton||description descrition||description descritptor||descriptor desctiptor||descriptor desriptor||descriptor desriptors||descriptors +desination||destination destionation||destination +destoried||destroyed destory||destroy destoryed||destroyed destorys||destroys @@ -396,43 +448,64 @@ deveolpment||development devided||divided deviece||device diable||disable +dicline||decline dictionnary||dictionary didnt||didn't diferent||different differrence||difference diffrent||different +differenciate||differentiate diffrentiate||differentiate difinition||definition +digial||digital +dimention||dimension dimesions||dimensions +dispalying||displaying diplay||display +directon||direction direectly||directly +diregard||disregard disassocation||disassociation disapear||disappear disapeared||disappeared disappared||disappeared +disbale||disable +disbaled||disabled disble||disable disbled||disabled disconnet||disconnect discontinous||discontinuous +disharge||discharge +disnabled||disabled dispertion||dispersion dissapears||disappears +dissconect||disconnect distiction||distinction +divisable||divisible +divsiors||divisors docuentation||documentation documantation||documentation documentaion||documentation documment||document doesnt||doesn't +donwload||download +donwloading||downloading dorp||drop dosen||doesn downlad||download downlads||downloads +droped||dropped +droput||dropout druing||during dynmaic||dynamic +eanable||enable +eanble||enable easilly||easily ecspecially||especially edditable||editable editting||editing efective||effective +effectivness||effectiveness efficently||efficiently ehther||ether eigth||eight @@ -440,6 +513,8 @@ elementry||elementary eletronic||electronic embeded||embedded enabledi||enabled +enbale||enable +enble||enable enchanced||enhanced encorporating||incorporating encrupted||encrypted @@ -448,6 +523,9 @@ encryptio||encryption endianess||endianness enhaced||enhanced enlightnment||enlightenment +enqueing||enqueuing +entires||entries +entites||entities entrys||entries enocded||encoded enterily||entirely @@ -467,7 +545,10 @@ etsbalishment||establishment excecutable||executable exceded||exceeded excellant||excellent +execeeded||exceeded +execeeds||exceeds exeed||exceed +exeuction||execution existance||existence existant||existent exixt||exist @@ -475,6 +556,7 @@ exlcude||exclude exlcusive||exclusive exmaple||example expecially||especially +experies||expires explicite||explicit explicitely||explicitly explict||explicit @@ -485,9 +567,14 @@ exprimental||experimental extened||extended extensability||extensibility extention||extension +extenstion||extension extracter||extractor +faied||failed +faield||failed falied||failed faild||failed +failded||failed +failer||failure faill||fail failied||failed faillure||failure @@ -506,6 +593,8 @@ fetaure||feature fetaures||features fileystem||filesystem fimware||firmware +firmare||firmware +firmaware||firmware firware||firmware finanize||finalize findn||find @@ -521,13 +610,17 @@ forseeable||foreseeable forse||force fortan||fortran forwardig||forwarding +frambuffer||framebuffer framming||framing framwork||framework frequncy||frequency +frequancy||frequency frome||from fucntion||function fuction||function fuctions||functions +fullill||fulfill +funcation||function funcion||function functionallity||functionality functionaly||functionally @@ -538,9 +631,13 @@ funtions||functions furthur||further futhermore||furthermore futrue||future +gatable||gateable +gateing||gating +gauage||gauge gaurenteed||guaranteed generiously||generously genereate||generate +genereted||generated genric||generic globel||global grabing||grabbing @@ -554,14 +651,17 @@ guarentee||guarantee halfs||halves hander||handler handfull||handful +hanlde||handle hanled||handled happend||happened harware||hardware heirarchically||hierarchically helpfull||helpful +hexdecimal||hexadecimal hybernate||hibernate hierachy||hierarchy hierarchie||hierarchy +homogenous||homogeneous howver||however hsould||should hypervior||hypervisor @@ -569,12 +669,16 @@ hypter||hyper identidier||identifier iligal||illegal illigal||illegal +illgal||illegal +iomaped||iomapped imblance||imbalance immeadiately||immediately immedaite||immediate +immedate||immediate immediatelly||immediately immediatly||immediately immidiate||immediate +immutible||immutable impelentation||implementation impementated||implemented implemantation||implementation @@ -592,10 +696,12 @@ incative||inactive incomming||incoming incompatabilities||incompatibilities incompatable||incompatible +incompatble||incompatible inconsistant||inconsistent increas||increase incremeted||incremented incrment||increment +inculde||include indendation||indentation indended||intended independant||independent @@ -604,6 +710,7 @@ independed||independent indiate||indicate indicat||indicate inexpect||inexpected +inferface||interface infomation||information informatiom||information informations||information @@ -618,14 +725,22 @@ initalize||initialize initation||initiation initators||initiators initialiazation||initialization +initializationg||initialization initializiation||initialization +initialze||initialize initialzed||initialized +initialzing||initializing initilization||initialization initilize||initialize +initliaze||initialize inofficial||unofficial +inrerface||interface insititute||institute +instace||instance instal||install +instanciate||instantiate instanciated||instantiated +insufficent||insufficient inteface||interface integreated||integrated integrety||integrity @@ -640,6 +755,8 @@ intermittant||intermittent internel||internal interoprability||interoperability interuupt||interrupt +interupt||interrupt +interupts||interrupts interrface||interface interrrupt||interrupt interrup||interrupt @@ -655,10 +772,14 @@ intialization||initialization intialized||initialized intialize||initialize intregral||integral +intrerrupt||interrupt intrrupt||interrupt intterrupt||interrupt intuative||intuitive +inavlid||invalid invaid||invalid +invaild||invalid +invailid||invalid invald||invalid invalde||invalid invalide||invalid @@ -667,6 +788,7 @@ invalud||invalid invididual||individual invokation||invocation invokations||invocations +ireelevant||irrelevant irrelevent||irrelevant isnt||isn't isssue||issue @@ -675,6 +797,7 @@ itertation||iteration itslef||itself jave||java jeffies||jiffies +jumpimng||jumping juse||just jus||just kown||known @@ -684,6 +807,7 @@ langauge||language langugage||language lauch||launch layed||laid +legnth||length leightweight||lightweight lengh||length lenght||length @@ -694,29 +818,39 @@ libary||library librairies||libraries libraris||libraries licenceing||licencing +logaritmic||logarithmic loggging||logging loggin||login logile||logfile +loobpack||loopback loosing||losing losted||lost machinary||machinery +maibox||mailbox maintainance||maintenance maintainence||maintenance maintan||maintain makeing||making +mailformed||malformed malplaced||misplaced malplace||misplace managable||manageable managment||management mangement||management manoeuvering||maneuvering +manufaucturing||manufacturing mappping||mapping +matchs||matches mathimatical||mathematical mathimatic||mathematic mathimatics||mathematics +maximium||maximum maxium||maximum mechamism||mechanism meetign||meeting +memeory||memory +memmber||member +memoery||memory ment||meant mergable||mergeable mesage||message @@ -724,11 +858,14 @@ messags||messages messgaes||messages messsage||message messsages||messages +metdata||metadata micropone||microphone microprocesspr||microprocessor +migrateable||migratable milliseonds||milliseconds minium||minimum minimam||minimum +miniumum||minimum minumum||minimum misalinged||misaligned miscelleneous||miscellaneous @@ -737,11 +874,14 @@ mispelled||misspelled mispelt||misspelt mising||missing mismactch||mismatch +missign||missing missmanaged||mismanaged missmatch||mismatch +misssing||missing miximum||maximum mmnemonic||mnemonic mnay||many +modfiy||modify modulues||modules momery||memory memomry||memory @@ -752,6 +892,7 @@ mopdule||module mroe||more mulitplied||multiplied multidimensionnal||multidimensional +multipe||multiple multple||multiple mumber||number muticast||multicast @@ -774,10 +915,13 @@ nescessary||necessary nessessary||necessary noticable||noticeable notications||notifications +notifcations||notifications notifed||notified +notity||notify numebr||number numner||number obtaion||obtain +obusing||abusing occassionally||occasionally occationally||occasionally occurance||occurrence @@ -787,7 +931,11 @@ occurence||occurrence occure||occurred occured||occurred occuring||occurring +offser||offset offet||offset +offlaod||offload +offloded||offloaded +offseting||offsetting omited||omitted omiting||omitting omitt||omit @@ -802,6 +950,7 @@ optmizations||optimizations orientatied||orientated orientied||oriented orignal||original +originial||original otherise||otherwise ouput||output oustanding||outstanding @@ -821,6 +970,7 @@ packege||package packge||package packtes||packets pakage||package +paket||packet pallette||palette paln||plan paramameters||parameters @@ -830,23 +980,30 @@ parametes||parameters parametised||parametrised paramter||parameter paramters||parameters +parmaters||parameters particuarly||particularly particularily||particularly +partion||partition +partions||partitions partiton||partition pased||passed passin||passing pathes||paths pecularities||peculiarities peformance||performance +peforming||performing peice||piece pendantic||pedantic peprocessor||preprocessor perfoming||performing +peripherial||peripheral permissons||permissions peroid||period persistance||persistence persistant||persistent +phoneticly||phonetically plalform||platform +platfoem||platform platfrom||platform plattform||platform pleaes||please @@ -858,7 +1015,10 @@ poiter||pointer posible||possible positon||position possibilites||possibilities +potocol||protocol powerfull||powerful +pramater||parameter +preamle||preamble preample||preamble preapre||prepare preceeded||preceded @@ -871,6 +1031,7 @@ prefered||preferred prefferably||preferably premption||preemption prepaired||prepared +preperation||preparation pressre||pressure primative||primitive princliple||principle @@ -898,6 +1059,8 @@ programers||programmers programm||program programms||programs progresss||progress +prohibitted||prohibited +prohibitting||prohibiting promiscous||promiscuous promps||prompts pronnounced||pronounced @@ -912,19 +1075,24 @@ prosess||process protable||portable protcol||protocol protecion||protection +protedcted||protected protocoll||protocol promixity||proximity psudo||pseudo psuedo||pseudo psychadelic||psychedelic pwoer||power +queing||queuing quering||querying +queus||queues randomally||randomly raoming||roaming reasearcher||researcher reasearchers||researchers reasearch||research +receieve||receive recepient||recipient +recevied||received receving||receiving recieved||received recieve||receive @@ -936,6 +1104,7 @@ recommanded||recommended recyle||recycle redircet||redirect redirectrion||redirection +redundacy||redundancy reename||rename refcounf||refcount refence||reference @@ -974,19 +1143,27 @@ requirment||requirement requred||required requried||required requst||request +reregisteration||reregistration reseting||resetting +reseved||reserved +reseverd||reserved resizeable||resizable resouce||resource resouces||resources resoures||resources responce||response +resrouce||resource ressizes||resizes ressource||resource ressources||resources +restesting||retesting +resumbmitting||resubmitting retransmited||retransmitted retreived||retrieved retreive||retrieve +retreiving||retrieving retrive||retrieve +retrived||retrieved retuned||returned reudce||reduce reuest||request @@ -1007,14 +1184,18 @@ sacrifying||sacrificing safly||safely safty||safety savable||saveable +scaleing||scaling scaned||scanned scaning||scanning scarch||search +schdule||schedule seach||search searchs||searches secquence||sequence secund||second segement||segment +semaphone||semaphore +senario||scenario senarios||scenarios sentivite||sensitive separatly||separately @@ -1026,9 +1207,13 @@ seperate||separate seperatly||separately seperator||separator sepperate||separate +seqeunce||sequence +seqeuncer||sequencer +seqeuencer||sequencer sequece||sequence sequencial||sequential serveral||several +servive||service setts||sets settting||setting shotdown||shutdown @@ -1047,9 +1232,11 @@ singaled||signaled singal||signal singed||signed sleeped||slept +sliped||slipped softwares||software speach||speech specfic||specific +specfield||specified speciefied||specified specifc||specific specifed||specified @@ -1072,8 +1259,12 @@ staion||station standardss||standards standartization||standardization standart||standard +standy||standby +stardard||standard staticly||statically +statuss||status stoped||stopped +stoping||stopping stoppped||stopped straming||streaming struc||struct @@ -1086,6 +1277,7 @@ subdirectoires||subdirectories suble||subtle substract||subtract submition||submission +suceed||succeed succesfully||successfully succesful||successful successed||succeeded @@ -1109,6 +1301,7 @@ surpressed||suppressed surpresses||suppresses susbsystem||subsystem suspeneded||suspended +suspsend||suspend suspicously||suspiciously swaping||swapping switchs||switches @@ -1123,6 +1316,7 @@ swtich||switch symetric||symmetric synax||syntax synchonized||synchronized +synchronuously||synchronously syncronize||synchronize syncronized||synchronized syncronizing||synchronizing @@ -1131,28 +1325,38 @@ syste||system sytem||system sythesis||synthesis taht||that +tansmit||transmit targetted||targeted targetting||targeting +taskelt||tasklet teh||the temorary||temporary temproarily||temporarily +temperture||temperature +thead||thread therfore||therefore thier||their threds||threads threshhold||threshold thresold||threshold throught||through +trackling||tracking troughput||throughput thses||these +tiggers||triggers tiggered||triggered tipically||typically +timeing||timing timout||timeout tmis||this +toogle||toggle torerable||tolerable +traking||tracking tramsmitted||transmitted tramsmit||transmit tranasction||transaction tranfer||transfer +transcevier||transceiver transciever||transceiver transferd||transferred transfered||transferred @@ -1163,6 +1367,7 @@ transormed||transformed trasfer||transfer trasmission||transmission treshold||threshold +trigerred||triggered trigerring||triggering trun||turn tunning||tuning @@ -1170,8 +1375,11 @@ ture||true tyep||type udpate||update uesd||used +uknown||unknown +usupported||unsupported uncommited||uncommitted unconditionaly||unconditionally +undeflow||underflow underun||underrun unecessary||unnecessary unexecpted||unexpected @@ -1182,11 +1390,15 @@ unexpeted||unexpected unexpexted||unexpected unfortunatelly||unfortunately unifiy||unify +uniterrupted||uninterrupted unintialized||uninitialized +unitialized||uninitialized unkmown||unknown unknonw||unknown unknow||unknown unkown||unknown +unamed||unnamed +uneeded||unneeded unneded||unneeded unneccecary||unnecessary unneccesary||unnecessary @@ -1205,12 +1417,15 @@ unsuccessfull||unsuccessful unsuported||unsupported untill||until unuseful||useless +unvalid||invalid upate||update +upsupported||unsupported usefule||useful usefull||useful usege||usage usera||users usualy||usually +usupported||unsupported utilites||utilities utillities||utilities utilties||utilities @@ -1225,6 +1440,7 @@ varible||variable varient||variant vaule||value verbse||verbose +veify||verify verisons||versions verison||version verson||version @@ -1234,7 +1450,9 @@ virtaul||virtual virtiual||virtual visiters||visitors vitual||virtual +vunerable||vulnerable wakeus||wakeups +wathdog||watchdog wating||waiting wiat||wait wether||whether @@ -1251,5 +1469,6 @@ wnat||want workarould||workaround writeing||writing writting||writing +wtih||with zombe||zombie zomebie||zombie From aeff512a507e01c8b9d0ba9b6099de4a53c85420 Mon Sep 17 00:00:00 2001 From: Elyes HAOUAS Date: Sat, 7 Dec 2019 11:57:35 +0100 Subject: [PATCH 0590/1242] src/device: Fix typo Change-Id: Ibe99264a82fdea0e185907d2d2d4c57078ef3ae4 Signed-off-by: Elyes HAOUAS Reviewed-on: https://review.coreboot.org/c/coreboot/+/37571 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi Reviewed-by: Paul Menzel --- src/device/pciexp_device.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/device/pciexp_device.c b/src/device/pciexp_device.c index 72aac4c7c5..c73c548bb4 100644 --- a/src/device/pciexp_device.c +++ b/src/device/pciexp_device.c @@ -165,7 +165,7 @@ static void pciexp_configure_ltr(struct device *dev) cap = pci_find_capability(dev, PCI_CAP_ID_PCIE); /* - * Check if capibility pointer is valid and + * Check if capability pointer is valid and * device supports LTR mechanism. */ if (!cap || !pciexp_is_ltr_supported(dev, cap)) { From 322635a955ed6133508dd56b85f65ad448fcb1c5 Mon Sep 17 00:00:00 2001 From: Bill XIE Date: Tue, 19 Nov 2019 00:29:27 +0800 Subject: [PATCH 0591/1242] mb/gigabyte/ga-b75m-d3h: Add ga-b75-d3v as a variant It is an ATX board similar to existing ga-b75* boards. The major difference is the configuration of pci-e ports on PCH, and on-board pci-e NIC. (see below) Tested: - CPU i5 3570T - Slotted DIMM 8GiB*4 from Kingston - usb2 and usb3 - pci and pci-e ports - sata - Sound - S3 - AR8161 NIC connected to 1c.2 with mac address burnt in efuse - libgfxinit-based graphic init - NVRAM options for North and South bridges - tpm 1.2 on lpc (similar to ga-b75m-d3h) - Linux 4.19.67-2 within Debian GNU/Linux stable, loaded from SeaBIOS. Change-Id: I1a969880e4da02abf8ba73aac60ee1296fe0abf2 Signed-off-by: Bill XIE Reviewed-on: https://review.coreboot.org/c/coreboot/+/36992 Tested-by: build bot (Jenkins) Reviewed-by: Arthur Heymans --- src/mainboard/gigabyte/ga-b75m-d3h/Kconfig | 10 +- .../gigabyte/ga-b75m-d3h/Kconfig.name | 3 + .../variants/ga-b75-d3v/board_info.txt | 7 + .../variants/ga-b75-d3v/gma-mainboard.ads | 28 +++ .../ga-b75m-d3h/variants/ga-b75-d3v/gpio.c | 201 ++++++++++++++++++ .../ga-b75-d3v/include/variant/hda_verb.h | 43 ++++ .../variants/ga-b75-d3v/overridetree.cb | 23 ++ 7 files changed, 313 insertions(+), 2 deletions(-) create mode 100644 src/mainboard/gigabyte/ga-b75m-d3h/variants/ga-b75-d3v/board_info.txt create mode 100644 src/mainboard/gigabyte/ga-b75m-d3h/variants/ga-b75-d3v/gma-mainboard.ads create mode 100644 src/mainboard/gigabyte/ga-b75m-d3h/variants/ga-b75-d3v/gpio.c create mode 100644 src/mainboard/gigabyte/ga-b75m-d3h/variants/ga-b75-d3v/include/variant/hda_verb.h create mode 100644 src/mainboard/gigabyte/ga-b75m-d3h/variants/ga-b75-d3v/overridetree.cb diff --git a/src/mainboard/gigabyte/ga-b75m-d3h/Kconfig b/src/mainboard/gigabyte/ga-b75m-d3h/Kconfig index 64d9cc526e..1ad68f4a96 100644 --- a/src/mainboard/gigabyte/ga-b75m-d3h/Kconfig +++ b/src/mainboard/gigabyte/ga-b75m-d3h/Kconfig @@ -1,4 +1,4 @@ -if BOARD_GIGABYTE_GA_B75M_D3H || BOARD_GIGABYTE_GA_B75M_D3V +if BOARD_GIGABYTE_GA_B75M_D3H || BOARD_GIGABYTE_GA_B75M_D3V || BOARD_GIGABYTE_GA_B75_D3V config BOARD_SPECIFIC_OPTIONS def_bool y @@ -34,11 +34,17 @@ config VARIANT_DIR string default "ga-b75m-d3h" if BOARD_GIGABYTE_GA_B75M_D3H default "ga-b75m-d3v" if BOARD_GIGABYTE_GA_B75M_D3V + default "ga-b75-d3v" if BOARD_GIGABYTE_GA_B75_D3V config MAINBOARD_PART_NUMBER string default "GA-B75M-D3H" if BOARD_GIGABYTE_GA_B75M_D3H default "GA-B75M-D3V" if BOARD_GIGABYTE_GA_B75M_D3V + default "GA-B75-D3V" if BOARD_GIGABYTE_GA_B75_D3V + +config OVERRIDE_DEVICETREE + string + default "variants/$(CONFIG_VARIANT_DIR)/overridetree.cb" if BOARD_GIGABYTE_GA_B75_D3V config MAX_CPUS int @@ -49,4 +55,4 @@ config INTEL_GMA_VBT_FILE string default "src/mainboard/$(MAINBOARDDIR)/data.vbt" -endif # BOARD_GIGABYTE_GA_B75M* +endif # BOARD_GIGABYTE_GA_B75* diff --git a/src/mainboard/gigabyte/ga-b75m-d3h/Kconfig.name b/src/mainboard/gigabyte/ga-b75m-d3h/Kconfig.name index f8fbe54215..93f73a5afc 100644 --- a/src/mainboard/gigabyte/ga-b75m-d3h/Kconfig.name +++ b/src/mainboard/gigabyte/ga-b75m-d3h/Kconfig.name @@ -3,3 +3,6 @@ config BOARD_GIGABYTE_GA_B75M_D3H config BOARD_GIGABYTE_GA_B75M_D3V bool "GA-B75M-D3V" + +config BOARD_GIGABYTE_GA_B75_D3V + bool "GA-B75-D3V" diff --git a/src/mainboard/gigabyte/ga-b75m-d3h/variants/ga-b75-d3v/board_info.txt b/src/mainboard/gigabyte/ga-b75m-d3h/variants/ga-b75-d3v/board_info.txt new file mode 100644 index 0000000000..f90483fb71 --- /dev/null +++ b/src/mainboard/gigabyte/ga-b75m-d3h/variants/ga-b75-d3v/board_info.txt @@ -0,0 +1,7 @@ +Category: desktop +Board URL: https://www.gigabyte.com/Motherboard/GA-B75-D3V-rev-11 +ROM package: SOIC-8 +ROM protocol: SPI +ROM socketed: n +Flashrom support: y +Release year: 2012 diff --git a/src/mainboard/gigabyte/ga-b75m-d3h/variants/ga-b75-d3v/gma-mainboard.ads b/src/mainboard/gigabyte/ga-b75m-d3h/variants/ga-b75-d3v/gma-mainboard.ads new file mode 100644 index 0000000000..416732dc2b --- /dev/null +++ b/src/mainboard/gigabyte/ga-b75m-d3h/variants/ga-b75-d3v/gma-mainboard.ads @@ -0,0 +1,28 @@ +-- +-- Copyright (C) 2017 Bill XIE persmule@gmail.com +-- +-- This program is free software; you can redistribute it and/or modify +-- it under the terms of the GNU General Public License as published by +-- the Free Software Foundation; either version 2 of the License, or +-- (at your option) any later version. +-- +-- This program is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more details. +-- + +with HW.GFX.GMA; +with HW.GFX.GMA.Display_Probing; + +use HW.GFX.GMA; +use HW.GFX.GMA.Display_Probing; + +private package GMA.Mainboard is + + ports : constant Port_List := + (HDMI1, + Analog, + others => Disabled); + +end GMA.Mainboard; diff --git a/src/mainboard/gigabyte/ga-b75m-d3h/variants/ga-b75-d3v/gpio.c b/src/mainboard/gigabyte/ga-b75m-d3h/variants/ga-b75-d3v/gpio.c new file mode 100644 index 0000000000..763dfadefd --- /dev/null +++ b/src/mainboard/gigabyte/ga-b75m-d3h/variants/ga-b75-d3v/gpio.c @@ -0,0 +1,201 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008-2009 coresystems GmbH + * Copyright (C) 2014 Vladimir Serbinenko + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include + +static const struct pch_gpio_set1 pch_gpio_set1_mode = { + .gpio0 = GPIO_MODE_GPIO, + .gpio1 = GPIO_MODE_GPIO, + .gpio2 = GPIO_MODE_NATIVE, + .gpio3 = GPIO_MODE_NATIVE, + .gpio4 = GPIO_MODE_NATIVE, + .gpio5 = GPIO_MODE_NATIVE, + .gpio6 = GPIO_MODE_GPIO, + .gpio7 = GPIO_MODE_GPIO, + .gpio8 = GPIO_MODE_GPIO, + .gpio9 = GPIO_MODE_NATIVE, + .gpio10 = GPIO_MODE_NATIVE, + .gpio11 = GPIO_MODE_NATIVE, + .gpio12 = GPIO_MODE_GPIO, + .gpio13 = GPIO_MODE_GPIO, + .gpio14 = GPIO_MODE_NATIVE, + .gpio15 = GPIO_MODE_GPIO, + .gpio16 = GPIO_MODE_GPIO, + .gpio17 = GPIO_MODE_GPIO, + .gpio18 = GPIO_MODE_NATIVE, + .gpio19 = GPIO_MODE_GPIO, + .gpio20 = GPIO_MODE_NATIVE, + .gpio21 = GPIO_MODE_GPIO, + .gpio22 = GPIO_MODE_GPIO, + .gpio23 = GPIO_MODE_NATIVE, + .gpio24 = GPIO_MODE_GPIO, + .gpio25 = GPIO_MODE_NATIVE, + .gpio26 = GPIO_MODE_NATIVE, + .gpio27 = GPIO_MODE_GPIO, + .gpio28 = GPIO_MODE_GPIO, + .gpio29 = GPIO_MODE_GPIO, + .gpio30 = GPIO_MODE_NATIVE, + .gpio31 = GPIO_MODE_GPIO, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_direction = { + .gpio0 = GPIO_DIR_INPUT, + .gpio1 = GPIO_DIR_INPUT, + .gpio6 = GPIO_DIR_INPUT, + .gpio7 = GPIO_DIR_INPUT, + .gpio8 = GPIO_DIR_OUTPUT, + .gpio12 = GPIO_DIR_OUTPUT, + .gpio13 = GPIO_DIR_INPUT, + .gpio15 = GPIO_DIR_OUTPUT, + .gpio16 = GPIO_DIR_INPUT, + .gpio17 = GPIO_DIR_INPUT, + .gpio19 = GPIO_DIR_INPUT, + .gpio21 = GPIO_DIR_INPUT, + .gpio22 = GPIO_DIR_INPUT, + .gpio24 = GPIO_DIR_OUTPUT, + .gpio27 = GPIO_DIR_INPUT, + .gpio28 = GPIO_DIR_OUTPUT, + .gpio29 = GPIO_DIR_INPUT, + .gpio31 = GPIO_DIR_INPUT, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_level = { + .gpio8 = GPIO_LEVEL_HIGH, + .gpio12 = GPIO_LEVEL_HIGH, + .gpio15 = GPIO_LEVEL_LOW, + .gpio24 = GPIO_LEVEL_LOW, + .gpio28 = GPIO_LEVEL_LOW, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_reset = { + .gpio24 = GPIO_RESET_RSMRST, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_invert = { + .gpio13 = GPIO_INVERT, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_blink = { +}; + +static const struct pch_gpio_set2 pch_gpio_set2_mode = { + .gpio32 = GPIO_MODE_GPIO, + .gpio33 = GPIO_MODE_GPIO, + .gpio34 = GPIO_MODE_GPIO, + .gpio35 = GPIO_MODE_GPIO, + .gpio36 = GPIO_MODE_GPIO, + .gpio37 = GPIO_MODE_GPIO, + .gpio38 = GPIO_MODE_GPIO, + .gpio39 = GPIO_MODE_GPIO, + .gpio40 = GPIO_MODE_NATIVE, + .gpio41 = GPIO_MODE_NATIVE, + .gpio42 = GPIO_MODE_NATIVE, + .gpio43 = GPIO_MODE_NATIVE, + .gpio44 = GPIO_MODE_NATIVE, + .gpio45 = GPIO_MODE_NATIVE, + .gpio46 = GPIO_MODE_NATIVE, + .gpio47 = GPIO_MODE_NATIVE, + .gpio48 = GPIO_MODE_GPIO, + .gpio49 = GPIO_MODE_GPIO, + .gpio50 = GPIO_MODE_NATIVE, + .gpio51 = GPIO_MODE_NATIVE, + .gpio52 = GPIO_MODE_NATIVE, + .gpio53 = GPIO_MODE_NATIVE, + .gpio54 = GPIO_MODE_NATIVE, + .gpio55 = GPIO_MODE_NATIVE, + .gpio56 = GPIO_MODE_NATIVE, + .gpio57 = GPIO_MODE_GPIO, + .gpio58 = GPIO_MODE_NATIVE, + .gpio59 = GPIO_MODE_NATIVE, + .gpio60 = GPIO_MODE_NATIVE, + .gpio61 = GPIO_MODE_NATIVE, + .gpio62 = GPIO_MODE_NATIVE, + .gpio63 = GPIO_MODE_NATIVE, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_direction = { + .gpio32 = GPIO_DIR_OUTPUT, + .gpio33 = GPIO_DIR_OUTPUT, + .gpio34 = GPIO_DIR_INPUT, + .gpio35 = GPIO_DIR_OUTPUT, + .gpio36 = GPIO_DIR_INPUT, + .gpio37 = GPIO_DIR_INPUT, + .gpio38 = GPIO_DIR_INPUT, + .gpio39 = GPIO_DIR_INPUT, + .gpio48 = GPIO_DIR_INPUT, + .gpio49 = GPIO_DIR_INPUT, + .gpio57 = GPIO_DIR_INPUT, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_level = { + .gpio32 = GPIO_LEVEL_HIGH, + .gpio33 = GPIO_LEVEL_HIGH, + .gpio35 = GPIO_LEVEL_LOW, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_reset = { +}; + +static const struct pch_gpio_set3 pch_gpio_set3_mode = { + .gpio64 = GPIO_MODE_NATIVE, + .gpio65 = GPIO_MODE_NATIVE, + .gpio66 = GPIO_MODE_NATIVE, + .gpio67 = GPIO_MODE_NATIVE, + .gpio68 = GPIO_MODE_GPIO, + .gpio69 = GPIO_MODE_GPIO, + .gpio70 = GPIO_MODE_NATIVE, + .gpio71 = GPIO_MODE_NATIVE, + .gpio72 = GPIO_MODE_GPIO, + .gpio73 = GPIO_MODE_NATIVE, + .gpio74 = GPIO_MODE_NATIVE, + .gpio75 = GPIO_MODE_NATIVE, +}; + +static const struct pch_gpio_set3 pch_gpio_set3_direction = { + .gpio68 = GPIO_DIR_INPUT, + .gpio69 = GPIO_DIR_INPUT, + .gpio72 = GPIO_DIR_INPUT, +}; + +static const struct pch_gpio_set3 pch_gpio_set3_level = { +}; + +static const struct pch_gpio_set3 pch_gpio_set3_reset = { +}; + +const struct pch_gpio_map mainboard_gpio_map = { + .set1 = { + .mode = &pch_gpio_set1_mode, + .direction = &pch_gpio_set1_direction, + .level = &pch_gpio_set1_level, + .blink = &pch_gpio_set1_blink, + .invert = &pch_gpio_set1_invert, + .reset = &pch_gpio_set1_reset, + }, + .set2 = { + .mode = &pch_gpio_set2_mode, + .direction = &pch_gpio_set2_direction, + .level = &pch_gpio_set2_level, + .reset = &pch_gpio_set2_reset, + }, + .set3 = { + .mode = &pch_gpio_set3_mode, + .direction = &pch_gpio_set3_direction, + .level = &pch_gpio_set3_level, + .reset = &pch_gpio_set3_reset, + }, +}; diff --git a/src/mainboard/gigabyte/ga-b75m-d3h/variants/ga-b75-d3v/include/variant/hda_verb.h b/src/mainboard/gigabyte/ga-b75m-d3h/variants/ga-b75-d3v/include/variant/hda_verb.h new file mode 100644 index 0000000000..76c4ed3195 --- /dev/null +++ b/src/mainboard/gigabyte/ga-b75m-d3h/variants/ga-b75-d3v/include/variant/hda_verb.h @@ -0,0 +1,43 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef GA_B75_D3V_HDA_VERB_H +#define GA_B75_D3V_HDA_VERB_H + +const u32 cim_verb_data[] = { + /* coreboot specific header */ + 0x10ec0887, // Realtek 887 + 0x1458a002, // Subsystem ID + 0x0000000e, // Number of entries + + /* NID 0x01: Subsystem ID. */ + AZALIA_SUBVENDOR(0x2, 0x1458a002), + + /* Pin Widget Verb Table */ + AZALIA_PIN_CFG(0x2, 0x11, 0x99430130), + AZALIA_PIN_CFG(0x2, 0x12, 0x411111f0), + AZALIA_PIN_CFG(0x2, 0x14, 0x01014410), + AZALIA_PIN_CFG(0x2, 0x15, 0x411111f0), + AZALIA_PIN_CFG(0x2, 0x16, 0x411111f0), + AZALIA_PIN_CFG(0x2, 0x17, 0x411111f0), + AZALIA_PIN_CFG(0x2, 0x18, 0x01a19c50), + AZALIA_PIN_CFG(0x2, 0x19, 0x02a19c60), + AZALIA_PIN_CFG(0x2, 0x1a, 0x0181345f), + AZALIA_PIN_CFG(0x2, 0x1b, 0x02214c20), + AZALIA_PIN_CFG(0x2, 0x1c, 0x411111f0), + AZALIA_PIN_CFG(0x2, 0x1d, 0x4004c601), + AZALIA_PIN_CFG(0x2, 0x1e, 0x411111f0), + AZALIA_PIN_CFG(0x2, 0x1f, 0x411111f0), +}; + +#endif diff --git a/src/mainboard/gigabyte/ga-b75m-d3h/variants/ga-b75-d3v/overridetree.cb b/src/mainboard/gigabyte/ga-b75m-d3h/variants/ga-b75-d3v/overridetree.cb new file mode 100644 index 0000000000..2fd3cd545b --- /dev/null +++ b/src/mainboard/gigabyte/ga-b75m-d3h/variants/ga-b75-d3v/overridetree.cb @@ -0,0 +1,23 @@ +chip northbridge/intel/sandybridge + device domain 0 on + chip southbridge/intel/bd82x6x # Intel Series 7 Panther Point PCH + device pci 16.0 off end # Management Engine Interface 1 + register "xhci_overcurrent_mapping" = "0x00000c03" + device pci 1c.1 on end # PCIe Port #2 + device pci 1c.2 on + device pci 00.0 on # PCI 1969:1091 + subsystemid 0x1458 0xe000 + end + end # PCIe Port #3 + device pci 1c.3 on end # PCIe Port #4 + device pci 1c.4 on end # PCIe Port #5 + device pci 1f.0 on # ISA/LPC bridge + subsystemid 0x1458 0x5001 + chip superio/ite/it8728f + device pnp 2e.2 off end # COM2 + device pnp 2e.3 off end # LPT + end + end + end + end +end From f15f310ea4af0d9db5f2b0dd5daac0fb8967e25f Mon Sep 17 00:00:00 2001 From: Peter Lemenkov Date: Wed, 27 Nov 2019 12:04:42 +0100 Subject: [PATCH 0592/1242] mb/lenovo/t420/devicetree: Use subsystemid inheritance Change-Id: Ia321f2b974539ac1684173d767dd9eb64060364a Signed-off-by: Peter Lemenkov Reviewed-on: https://review.coreboot.org/c/coreboot/+/37284 Tested-by: build bot (Jenkins) Reviewed-by: HAOUAS Elyes Reviewed-by: Patrick Rudolph --- src/mainboard/lenovo/t420/devicetree.cb | 50 +++++++------------------ 1 file changed, 14 insertions(+), 36 deletions(-) diff --git a/src/mainboard/lenovo/t420/devicetree.cb b/src/mainboard/lenovo/t420/devicetree.cb index 6deff6039c..53bd16f68a 100644 --- a/src/mainboard/lenovo/t420/devicetree.cb +++ b/src/mainboard/lenovo/t420/devicetree.cb @@ -37,13 +37,11 @@ chip northbridge/intel/sandybridge register "pci_mmio_size" = "2048" device domain 0 on - device pci 00.0 on - subsystemid 0x17aa 0x21ce - end # host bridge + subsystemid 0x17aa 0x21ce inherit + + device pci 00.0 on end # host bridge device pci 01.0 on end # PCIe Bridge for discrete graphics - device pci 02.0 on - subsystemid 0x17aa 0x21ce - end # Integrated Graphics Controller + device pci 02.0 on end # Integrated Graphics Controller chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH # GPI routing @@ -67,6 +65,7 @@ chip northbridge/intel/sandybridge # Enable zero-based linear PCIe root port functions register "pcie_port_coalesce" = "1" + register "c2_latency" = "101" # c2 not supported # device specific SPI configuration @@ -77,46 +76,30 @@ chip northbridge/intel/sandybridge device pci 16.1 off end # Management Engine Interface 2 device pci 16.2 off end # Management Engine IDE-R device pci 16.3 off end # Management Engine KT - device pci 19.0 on - subsystemid 0x17aa 0x21ce - end # Intel Gigabit Ethernet - device pci 1a.0 on - subsystemid 0x17aa 0x21ce - end # USB Enhanced Host Controller #2 - device pci 1b.0 on - subsystemid 0x17aa 0x21ce - end # High Definition Audio Controller + device pci 19.0 on end # Intel Gigabit Ethernet + device pci 1a.0 on end # USB Enhanced Host Controller #2 + device pci 1b.0 on end # High Definition Audio Controller device pci 1c.0 off end # PCIe Port #1 - device pci 1c.1 on - subsystemid 0x17aa 0x21ce - end # PCIe Port #2 Integrated Wireless LAN + device pci 1c.1 on end # PCIe Port #2 Integrated Wireless LAN device pci 1c.2 off end # PCIe Port #3 device pci 1c.3 on - subsystemid 0x17aa 0x21ce smbios_slot_desc "7" "3" "ExpressCard Slot" "8" end # PCIe Port #4 ExpressCard device pci 1c.4 on - subsystemid 0x17aa 0x21ce chip drivers/ricoh/rce822 register "sdwppol" = "1" register "disable_mask" = "0x87" - device pci 00.0 on - subsystemid 0x17aa 0x21ce - end + device pci 00.0 on end end end # PCIe Port #5 (Ricoh SD & FW) device pci 1c.5 off end # PCIe Port #6 Intel Gigabit Ethernet PHY (not PCIe) device pci 1c.6 off end # PCIe Port #7 device pci 1c.7 off end # PCIe Port #8 - device pci 1d.0 on - subsystemid 0x17aa 0x21ce - end # USB Enhanced Host Controller #1 + device pci 1d.0 on end # USB Enhanced Host Controller #1 device pci 1e.0 off end # PCI bridge device pci 1f.0 on - subsystemid 0x17aa 0x21ce chip ec/lenovo/pmh7 - device pnp ff.1 on # dummy - end + device pnp ff.1 on end # dummy register "backlight_enable" = "0x01" register "dock_event_enable" = "0x01" end @@ -176,11 +159,8 @@ chip northbridge/intel/sandybridge register "has_thinker1" = "1" end end # LPC Controller - device pci 1f.2 on - subsystemid 0x17aa 0x21ce - end # 6 port SATA AHCI Controller + device pci 1f.2 on end # 6 port SATA AHCI Controller device pci 1f.3 on - subsystemid 0x17aa 0x21ce # eeprom, 8 virtual devices, same chip chip drivers/i2c/at24rf08c device i2c 54 on end @@ -194,9 +174,7 @@ chip northbridge/intel/sandybridge end end # SMBus Controller device pci 1f.5 off end # SATA Controller 2 - device pci 1f.6 on - subsystemid 0x17aa 0x21ce - end # Thermal + device pci 1f.6 on end # Thermal end end end From 5ee7e472d1fb836b04f6fde3368ab8fb8aa9a08a Mon Sep 17 00:00:00 2001 From: Peter Lemenkov Date: Wed, 27 Nov 2019 12:17:26 +0100 Subject: [PATCH 0593/1242] mb/lenovo/t420s/devicetree: Use subsystemid inheritance Change-Id: Ia77f0ce89b2234b9c164bb326d76bef98949832a Signed-off-by: Peter Lemenkov Reviewed-on: https://review.coreboot.org/c/coreboot/+/37285 Reviewed-by: HAOUAS Elyes Tested-by: build bot (Jenkins) --- src/mainboard/lenovo/t420s/devicetree.cb | 40 +++++++----------------- 1 file changed, 11 insertions(+), 29 deletions(-) diff --git a/src/mainboard/lenovo/t420s/devicetree.cb b/src/mainboard/lenovo/t420s/devicetree.cb index aa6cc68154..c91b04e919 100644 --- a/src/mainboard/lenovo/t420s/devicetree.cb +++ b/src/mainboard/lenovo/t420s/devicetree.cb @@ -36,9 +36,9 @@ chip northbridge/intel/sandybridge register "pci_mmio_size" = "2048" device domain 0 on - device pci 00.0 on - subsystemid 0x17aa 0x21d2 - end # host bridge + subsystemid 0x17aa 0x21d2 inherit + + device pci 00.0 on end # host bridge device pci 01.0 on end # NVIDIA Corporation GF119M [NVS 4200M] device pci 02.0 on subsystemid 0x17aa 0x21d3 @@ -79,36 +79,23 @@ chip northbridge/intel/sandybridge device pci 19.0 on subsystemid 0x17aa 0x21ce end # Intel Gigabit Ethernet - device pci 1a.0 on - subsystemid 0x17aa 0x21d2 - end # USB Enhanced Host Controller #2 - device pci 1b.0 on - subsystemid 0x17aa 0x21d2 - end # High Definition Audio Controller + device pci 1a.0 on end # USB Enhanced Host Controller #2 + device pci 1b.0 on end # High Definition Audio Controller device pci 1c.0 off end # PCIe Port #1 - device pci 1c.1 on - subsystemid 0x17aa 0x21d2 - end # PCIe Port #2 Integrated Wireless LAN + device pci 1c.1 on end # PCIe Port #2 Integrated Wireless LAN device pci 1c.2 off end # PCIe Port #3 device pci 1c.3 on - subsystemid 0x17aa 0x21d2 smbios_slot_desc "7" "3" "ExpressCard Slot" "8" end # PCIe Port #4 ExpressCard device pci 1c.4 off end # PCIe Port #5 device pci 1c.5 off end # PCIe Port #6 Intel Gigabit Ethernet PHY (not PCIe) - device pci 1c.6 on - subsystemid 0x17aa 0x21d2 - end # PCIe Port #7 NEC Corporation uPD720200A USB 3.0 Host Controller + device pci 1c.6 on end # PCIe Port #7 NEC Corporation uPD720200A USB 3.0 Host Controller device pci 1c.7 off end # PCIe Port #8 - device pci 1d.0 on - subsystemid 0x17aa 0x21d2 - end # USB Enhanced Host Controller #1 + device pci 1d.0 on end # USB Enhanced Host Controller #1 device pci 1e.0 off end # PCI bridge device pci 1f.0 on - subsystemid 0x17aa 0x21d2 chip ec/lenovo/pmh7 - device pnp ff.1 on # dummy - end + device pnp ff.1 on end # dummy register "backlight_enable" = "0x01" register "dock_event_enable" = "0x01" end @@ -168,11 +155,8 @@ chip northbridge/intel/sandybridge register "has_thinker1" = "1" end end # LPC Controller - device pci 1f.2 on - subsystemid 0x17aa 0x21d2 - end # 6 port SATA AHCI Controller + device pci 1f.2 on end # 6 port SATA AHCI Controller device pci 1f.3 on - subsystemid 0x17aa 0x21d2 # eeprom, 8 virtual devices, same chip chip drivers/i2c/at24rf08c device i2c 54 on end @@ -186,9 +170,7 @@ chip northbridge/intel/sandybridge end end # SMBus Controller device pci 1f.5 off end # SATA Controller 2 - device pci 1f.6 on - subsystemid 0x17aa 0x21d2 - end # Thermal + device pci 1f.6 on end # Thermal end end end From 7e128576c2abe440a1b39a723f55b9e139c3cf1c Mon Sep 17 00:00:00 2001 From: Peter Lemenkov Date: Wed, 27 Nov 2019 22:39:52 +0100 Subject: [PATCH 0594/1242] mb/lenovo/l520/devicetree: Use subsystemid inheritance Change-Id: I90774e22fb7765f44b6cd4fa05b535236b782023 Signed-off-by: Peter Lemenkov Reviewed-on: https://review.coreboot.org/c/coreboot/+/37296 Tested-by: build bot (Jenkins) Reviewed-by: HAOUAS Elyes --- src/mainboard/lenovo/l520/devicetree.cb | 122 ++++++++---------------- 1 file changed, 39 insertions(+), 83 deletions(-) diff --git a/src/mainboard/lenovo/l520/devicetree.cb b/src/mainboard/lenovo/l520/devicetree.cb index 024b8f8dd1..29b75984fb 100644 --- a/src/mainboard/lenovo/l520/devicetree.cb +++ b/src/mainboard/lenovo/l520/devicetree.cb @@ -15,7 +15,7 @@ chip northbridge/intel/sandybridge register "gpu_panel_power_up_delay" = "0" register "gpu_pch_backlight" = "0x00000000" - device cpu_cluster 0x0 on + device cpu_cluster 0 on chip cpu/intel/model_206ax register "c1_acpower" = "1" register "c1_battery" = "1" @@ -28,15 +28,13 @@ chip northbridge/intel/sandybridge end end - device domain 0x0 on - device pci 00.0 on # Host bridge Host bridge - subsystemid 0x17aa 0x21dd - end - device pci 01.0 on # PCIe Bridge for discrete graphics - end - device pci 02.0 on # Internal graphics VGA controller - subsystemid 0x17aa 0x21dd - end + device domain 0 on + subsystemid 0x17aa 0x21dd inherit + + device pci 00.0 on end # Host bridge + device pci 01.0 on end # PCIe Bridge for discrete graphics + device pci 02.0 on end # Internal graphics VGA controller + chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH register "c2_latency" = "0x0065" register "docking_supported" = "1" @@ -54,57 +52,28 @@ chip northbridge/intel/sandybridge register "spi_uvscc" = "0" register "spi_lvscc" = "0x2005" - device pci 16.0 on # Management Engine Interface 1 - subsystemid 0x17aa 0x21dd - end - device pci 16.1 off # Management Engine Interface 2 - end - device pci 16.2 off # Management Engine IDE-R - end - device pci 16.3 off # Management Engine KT - end - device pci 19.0 off # Intel Gigabit Ethernet - end - device pci 1a.0 on # USB2 EHCI #2 - subsystemid 0x17aa 0x21dd - end - device pci 1b.0 on # High Definition Audio Audio controller - subsystemid 0x17aa 0x21dd - end - device pci 1c.0 on # PCIe Port #1 - subsystemid 0x17aa 0x21dd - end - device pci 1c.1 on # PCIe Port #2 - subsystemid 0x17aa 0x21dd - end - device pci 1c.2 on # PCIe Port #3 - subsystemid 0x17aa 0x21dd - end - device pci 1c.3 on # PCIe Port #4 - subsystemid 0x17aa 0x21dd - end - device pci 1c.4 on # PCIe Port #5 - subsystemid 0x17aa 0x21dd - end - device pci 1c.5 on # PCIe Port #6 - subsystemid 0x17aa 0x21dd - end - device pci 1c.6 off # PCIe Port #7 - end - device pci 1c.7 off # PCIe Port #8 - end - device pci 1d.0 on # USB2 EHCI #1 - subsystemid 0x17aa 0x21dd - end - device pci 1e.0 off # PCI bridge - end + device pci 16.0 on end # Management Engine Interface 1 + device pci 16.1 off end # Management Engine Interface 2 + device pci 16.2 off end # Management Engine IDE-R + device pci 16.3 off end # Management Engine KT + device pci 19.0 off end # Intel Gigabit Ethernet + device pci 1a.0 on end # USB2 EHCI #2 + device pci 1b.0 on end # High Definition Audio Audio controller + device pci 1c.0 on end # PCIe Port #1 + device pci 1c.1 on end # PCIe Port #2 + device pci 1c.2 on end # PCIe Port #3 + device pci 1c.3 on end # PCIe Port #4 + device pci 1c.4 on end # PCIe Port #5 + device pci 1c.5 on end # PCIe Port #6 + device pci 1c.6 off end # PCIe Port #7 + device pci 1c.7 off end # PCIe Port #8 + device pci 1d.0 on end # USB2 EHCI #1 + device pci 1e.0 off end # PCI bridge device pci 1f.0 on # LPC bridge PCI-LPC bridge - subsystemid 0x17aa 0x21dd chip ec/lenovo/pmh7 register "backlight_enable" = "0x01" register "dock_event_enable" = "0x01" - device pnp ff.1 on # dummy - end + device pnp ff.1 on end # dummy end chip ec/lenovo/h8 register "config0" = "0xa7" @@ -136,35 +105,22 @@ chip northbridge/intel/sandybridge io 0x66 = 0x1604 end end - end - device pci 1f.2 on # SATA Controller 1 - subsystemid 0x17aa 0x21dd - end + end # LPC bridge + device pci 1f.2 on end # SATA Controller 1 device pci 1f.3 on # SMBus - subsystemid 0x17aa 0x21dd chip drivers/i2c/at24rf08c # eeprom, 8 virtual devices, same chip - device i2c 54 on - end - device i2c 55 on - end - device i2c 56 on - end - device i2c 57 on - end - device i2c 5c on - end - device i2c 5d on - end - device i2c 5e on - end - device i2c 5f on - end + device i2c 54 on end + device i2c 55 on end + device i2c 56 on end + device i2c 57 on end + device i2c 5c on end + device i2c 5d on end + device i2c 5e on end + device i2c 5f on end end - end - device pci 1f.5 off # SATA Controller 2 - end - device pci 1f.6 off # Thermal - end + end # SMBus + device pci 1f.5 off end # SATA Controller 2 + device pci 1f.6 off end # Thermal end end end From 289b7d65fcd031b13056cf77471efd35f2dc9efe Mon Sep 17 00:00:00 2001 From: Peter Lemenkov Date: Wed, 27 Nov 2019 22:45:36 +0100 Subject: [PATCH 0595/1242] mb/lenovo/x220/devicetree: Use subsystemid inheritance Change-Id: Ia9367d03b6f97f1eb8c35045fd7bb79e5f45b535 Signed-off-by: Peter Lemenkov Reviewed-on: https://review.coreboot.org/c/coreboot/+/37297 Tested-by: build bot (Jenkins) Reviewed-by: HAOUAS Elyes --- src/mainboard/lenovo/x220/devicetree.cb | 57 +++++++------------------ 1 file changed, 15 insertions(+), 42 deletions(-) diff --git a/src/mainboard/lenovo/x220/devicetree.cb b/src/mainboard/lenovo/x220/devicetree.cb index 26fa1a4d1f..5ae14278b4 100644 --- a/src/mainboard/lenovo/x220/devicetree.cb +++ b/src/mainboard/lenovo/x220/devicetree.cb @@ -37,13 +37,11 @@ chip northbridge/intel/sandybridge register "pci_mmio_size" = "1024" device domain 0 on - device pci 00.0 on - subsystemid 0x17aa 0x21db - end # host bridge + subsystemid 0x17aa 0x21db inherit + + device pci 00.0 on end # host bridge device pci 01.0 off end # PCIe Bridge for discrete graphics - device pci 02.0 on - subsystemid 0x17aa 0x21db - end # vga controller + device pci 02.0 on end # vga controller chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH # GPI routing @@ -80,49 +78,29 @@ chip northbridge/intel/sandybridge device pci 19.0 on subsystemid 0x17aa 0x21ce end # Intel Gigabit Ethernet - device pci 1a.0 on - subsystemid 0x17aa 0x21db - end # USB2 EHCI #2 - device pci 1b.0 on - subsystemid 0x17aa 0x21db - end # High Definition Audio - device pci 1c.0 on - subsystemid 0x17aa 0x21db - end # PCIe Port #1 - device pci 1c.1 on - subsystemid 0x17aa 0x21db - end # PCIe Port #2 (wlan) - device pci 1c.2 on - subsystemid 0x17aa 0x21db - end # PCIe Port #3 + device pci 1a.0 on end # USB2 EHCI #2 + device pci 1b.0 on end # High Definition Audio + device pci 1c.0 on end # PCIe Port #1 + device pci 1c.1 on end # PCIe Port #2 (wlan) + device pci 1c.2 on end # PCIe Port #3 device pci 1c.3 on - subsystemid 0x17aa 0x21db smbios_slot_desc "7" "3" "ExpressCard Slot" "8" end # PCIe Port #4 device pci 1c.4 on - subsystemid 0x17aa 0x21db chip drivers/ricoh/rce822 register "sdwppol" = "1" register "disable_mask" = "0x87" - device pci 00.0 on - subsystemid 0x17aa 0x21fa - end + device pci 00.0 on end end end # PCIe Port #5 (SD) device pci 1c.5 off end # PCIe Port #6 - device pci 1c.6 on - subsystemid 0x17aa 0x21db - end # PCIe Port #7 + device pci 1c.6 on end # PCIe Port #7 device pci 1c.7 off end # PCIe Port #8 - device pci 1d.0 on - subsystemid 0x17aa 0x21db - end # USB2 EHCI #1 + device pci 1d.0 on end # USB2 EHCI #1 device pci 1e.0 off end # PCI bridge device pci 1f.0 on #LPC bridge - subsystemid 0x17aa 0x21db chip ec/lenovo/pmh7 - device pnp ff.1 on # dummy - end + device pnp ff.1 on end # dummy register "backlight_enable" = "0x01" register "dock_event_enable" = "0x01" end @@ -172,11 +150,8 @@ chip northbridge/intel/sandybridge register "wwan_gpio_lvl" = "0" end end # LPC bridge - device pci 1f.2 on - subsystemid 0x17aa 0x21db - end # SATA Controller 1 + device pci 1f.2 on end # SATA Controller 1 device pci 1f.3 on - subsystemid 0x17aa 0x21db # eeprom, 8 virtual devices, same chip chip drivers/i2c/at24rf08c device i2c 54 on end @@ -190,9 +165,7 @@ chip northbridge/intel/sandybridge end end # SMBus device pci 1f.5 off end # SATA Controller 2 - device pci 1f.6 on - subsystemid 0x17aa 0x21db - end # Thermal + device pci 1f.6 on end # Thermal end end end From bbb00d74044af88afa79e406f03dd8b231c80df6 Mon Sep 17 00:00:00 2001 From: Peter Lemenkov Date: Wed, 27 Nov 2019 22:50:30 +0100 Subject: [PATCH 0596/1242] mb/lenovo/x230/devicetree: Use subsystemid inheritance Change-Id: I95dbf55b74deca1e035ee1d042f1549d2583e346 Signed-off-by: Peter Lemenkov Reviewed-on: https://review.coreboot.org/c/coreboot/+/37298 Tested-by: build bot (Jenkins) Reviewed-by: HAOUAS Elyes --- src/mainboard/lenovo/x230/devicetree.cb | 53 +++++++------------------ 1 file changed, 14 insertions(+), 39 deletions(-) diff --git a/src/mainboard/lenovo/x230/devicetree.cb b/src/mainboard/lenovo/x230/devicetree.cb index 61a5468a78..e492dda710 100644 --- a/src/mainboard/lenovo/x230/devicetree.cb +++ b/src/mainboard/lenovo/x230/devicetree.cb @@ -37,13 +37,11 @@ chip northbridge/intel/sandybridge register "pci_mmio_size" = "1024" device domain 0 on - device pci 00.0 on - subsystemid 0x17aa 0x21fa - end # host bridge + subsystemid 0x17aa 0x21fa inherit + + device pci 00.0 on end # host bridge device pci 01.0 off end # PCIe Bridge for discrete graphics - device pci 02.0 on - subsystemid 0x17aa 0x21fa - end # vga controller + device pci 02.0 on end # vga controller chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH # GPI routing @@ -76,39 +74,25 @@ chip northbridge/intel/sandybridge register "spi_uvscc" = "0x2005" register "spi_lvscc" = "0x2005" - device pci 14.0 on - subsystemid 0x17aa 0x21fa - end # USB 3.0 Controller - device pci 16.0 on - subsystemid 0x17aa 0x21fa - end # Management Engine Interface 1 + device pci 14.0 on end # USB 3.0 Controller + device pci 16.0 on end # Management Engine Interface 1 device pci 16.1 off end # Management Engine Interface 2 device pci 16.2 off end # Management Engine IDE-R device pci 16.3 off end # Management Engine KT device pci 19.0 on subsystemid 0x17aa 0x21f3 end # Intel Gigabit Ethernet - device pci 1a.0 on - subsystemid 0x17aa 0x21fa - end # USB2 EHCI #2 - device pci 1b.0 on - subsystemid 0x17aa 0x21fa - end # High Definition Audio + device pci 1a.0 on end # USB2 EHCI #2 + device pci 1b.0 on end # High Definition Audio device pci 1c.0 on - subsystemid 0x17aa 0x21fa chip drivers/ricoh/rce822 register "sdwppol" = "1" register "disable_mask" = "0x87" - device pci 00.0 on - subsystemid 0x17aa 0x21fa - end + device pci 00.0 on end end end # PCIe Port #1 - device pci 1c.1 on - subsystemid 0x17aa 0x21fa - end # PCIe Port #2 + device pci 1c.1 on end # PCIe Port #2 device pci 1c.2 on - subsystemid 0x17aa 0x21fa smbios_slot_desc "7" "3" "ExpressCard Slot" "8" end # PCIe Port #3 (expresscard) device pci 1c.3 off end # PCIe Port #4 @@ -116,15 +100,11 @@ chip northbridge/intel/sandybridge device pci 1c.5 off end # PCIe Port #6 device pci 1c.6 off end # PCIe Port #7 device pci 1c.7 off end # PCIe Port #8 - device pci 1d.0 on - subsystemid 0x17aa 0x21fa - end # USB2 EHCI #1 + device pci 1d.0 on end # USB2 EHCI #1 device pci 1e.0 off end # PCI bridge device pci 1f.0 on #LPC bridge - subsystemid 0x17aa 0x21fa chip ec/lenovo/pmh7 - device pnp ff.1 on # dummy - end + device pnp ff.1 on end # dummy register "backlight_enable" = "0x01" register "dock_event_enable" = "0x01" end @@ -176,11 +156,8 @@ chip northbridge/intel/sandybridge register "wwan_gpio_lvl" = "0" end end # LPC bridge - device pci 1f.2 on - subsystemid 0x17aa 0x21fa - end # SATA Controller 1 + device pci 1f.2 on end # SATA Controller 1 device pci 1f.3 on - subsystemid 0x17aa 0x21fa # eeprom, 8 virtual devices, same chip chip drivers/i2c/at24rf08c device i2c 54 on end @@ -194,9 +171,7 @@ chip northbridge/intel/sandybridge end end # SMBus device pci 1f.5 off end # SATA Controller 2 - device pci 1f.6 on - subsystemid 0x17aa 0x21fa - end # Thermal + device pci 1f.6 on end # Thermal end end end From 07b2fdb59413242030033d96495e903ce20e7ed2 Mon Sep 17 00:00:00 2001 From: Peter Lemenkov Date: Wed, 27 Nov 2019 22:56:57 +0100 Subject: [PATCH 0597/1242] mb/lenovo/t430/devicetree: Use subsystemid inheritance Change-Id: I53e9e1a8381ca51200dc5306eef32442668607a3 Signed-off-by: Peter Lemenkov Reviewed-on: https://review.coreboot.org/c/coreboot/+/37299 Tested-by: build bot (Jenkins) Reviewed-by: HAOUAS Elyes --- src/mainboard/lenovo/t430/devicetree.cb | 116 +++++++----------------- 1 file changed, 35 insertions(+), 81 deletions(-) diff --git a/src/mainboard/lenovo/t430/devicetree.cb b/src/mainboard/lenovo/t430/devicetree.cb index f7e04367c6..cfdc3a4189 100644 --- a/src/mainboard/lenovo/t430/devicetree.cb +++ b/src/mainboard/lenovo/t430/devicetree.cb @@ -31,6 +31,8 @@ chip northbridge/intel/sandybridge end device domain 0x0 on + subsystemid 0x17aa 0x21f3 inherit + chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH register "c2_latency" = "0x0065" register "docking_supported" = "1" @@ -51,66 +53,37 @@ chip northbridge/intel/sandybridge register "spi_uvscc" = "0x2005" register "spi_lvscc" = "0x2005" - device pci 14.0 on # USB 3.0 Controller - subsystemid 0x17aa 0x21f3 - end - device pci 16.0 on # Management Engine Interface 1 - subsystemid 0x17aa 0x21f3 - end - device pci 16.1 off # Management Engine Interface 2 - end - device pci 16.2 off # Management Engine IDE-R - end - device pci 16.3 off # Management Engine KT - end - device pci 19.0 on # Intel Gigabit Ethernet - subsystemid 0x17aa 0x21f3 - end - device pci 1a.0 on # USB2 EHCI #2 - subsystemid 0x17aa 0x21f3 - end - device pci 1b.0 on # High Definition Audio Audio controller - subsystemid 0x17aa 0x21f3 - end + device pci 14.0 on end # USB 3.0 Controller + device pci 16.0 on end # Management Engine Interface 1 + device pci 16.1 off end # Management Engine Interface 2 + device pci 16.2 off end # Management Engine IDE-R + device pci 16.3 off end # Management Engine KT + device pci 19.0 on end # Intel Gigabit Ethernet + device pci 1a.0 on end # USB2 EHCI #2 + device pci 1b.0 on end # High Definition Audio Audio controller device pci 1c.0 on # PCIe Port #1 - subsystemid 0x17aa 0x21f3 chip drivers/ricoh/rce822 # Ricoh cardreader register "disable_mask" = "0x87" register "sdwppol" = "1" - device pci 00.0 on # Ricoh SD card reader - subsystemid 0x17aa 0x21f3 - end + device pci 00.0 on end # Ricoh SD card reader end end - device pci 1c.1 on # PCIe Port #2 - subsystemid 0x17aa 0x21f3 - end + device pci 1c.1 on end # PCIe Port #2 device pci 1c.2 on # PCIe Port #3 - subsystemid 0x17aa 0x21f3 smbios_slot_desc "7" "3" "ExpressCard Slot" "8" end - device pci 1c.3 off # PCIe Port #4 - end - device pci 1c.4 off # PCIe Port #5 - end - device pci 1c.5 off # PCIe Port #6 - end - device pci 1c.6 off # PCIe Port #7 - end - device pci 1c.7 off # PCIe Port #8 - end - device pci 1d.0 on # USB2 EHCI #1 - subsystemid 0x17aa 0x21f3 - end - device pci 1e.0 off # PCI bridge - end + device pci 1c.3 off end # PCIe Port #4 + device pci 1c.4 off end # PCIe Port #5 + device pci 1c.5 off end # PCIe Port #6 + device pci 1c.6 off end # PCIe Port #7 + device pci 1c.7 off end # PCIe Port #8 + device pci 1d.0 on end # USB2 EHCI #1 + device pci 1e.0 off end # PCI bridge device pci 1f.0 on # LPC bridge PCI-LPC bridge - subsystemid 0x17aa 0x21f3 chip ec/lenovo/pmh7 register "backlight_enable" = "0x01" register "dock_event_enable" = "0x01" - device pnp ff.1 on # dummy - end + device pnp ff.1 on end # dummy end chip ec/lenovo/h8 device pnp ff.2 on # dummy @@ -169,44 +142,25 @@ chip northbridge/intel/sandybridge device pnp 0c31.0 on end end end - device pci 1f.2 on # SATA Controller 1 - subsystemid 0x17aa 0x21f3 - end + device pci 1f.2 on end # SATA Controller 1 device pci 1f.3 on # SMBus - subsystemid 0x17aa 0x21f3 chip drivers/i2c/at24rf08c # eeprom, 8 virtual devices, same chip - device i2c 54 on - end - device i2c 55 on - end - device i2c 56 on - end - device i2c 57 on - end - device i2c 5c on - end - device i2c 5d on - end - device i2c 5e on - end - device i2c 5f on - end + device i2c 54 on end + device i2c 55 on end + device i2c 56 on end + device i2c 57 on end + device i2c 5c on end + device i2c 5d on end + device i2c 5e on end + device i2c 5f on end end end - device pci 1f.5 off # SATA Controller 2 - end - device pci 1f.6 off # Thermal - end - end - device pci 00.0 on # Host bridge Host bridge - subsystemid 0x17aa 0x21f3 - end - device pci 01.0 on # PCIe Bridge for discrete graphics - end - device pci 02.0 on # Internal graphics VGA controller - subsystemid 0x17aa 0x21f3 - end - device pci 04.0 off # Signal processing controller + device pci 1f.5 off end # SATA Controller 2 + device pci 1f.6 off end # Thermal end + device pci 00.0 on end # Host bridge Host bridge + device pci 01.0 on end # PCIe Bridge for discrete graphics + device pci 02.0 on end # Internal graphics VGA controller + device pci 04.0 off end # Signal processing controller end end From b8b9786ad4bc055c539c8aae88267b3f6c543c97 Mon Sep 17 00:00:00 2001 From: Peter Lemenkov Date: Wed, 27 Nov 2019 23:04:49 +0100 Subject: [PATCH 0598/1242] mb/lenovo/t430s/devicetree: Use subsystemid inheritance Change-Id: Ifde5d382eb223bd996b9bb909c751e9d5f0a11e5 Signed-off-by: Peter Lemenkov Reviewed-on: https://review.coreboot.org/c/coreboot/+/37300 Reviewed-by: HAOUAS Elyes Tested-by: build bot (Jenkins) --- src/mainboard/lenovo/t430s/devicetree.cb | 44 +++++-------------- .../t430s/variants/t430s/overridetree.cb | 4 +- 2 files changed, 13 insertions(+), 35 deletions(-) diff --git a/src/mainboard/lenovo/t430s/devicetree.cb b/src/mainboard/lenovo/t430s/devicetree.cb index 0c2f668897..ee612cd95c 100644 --- a/src/mainboard/lenovo/t430s/devicetree.cb +++ b/src/mainboard/lenovo/t430s/devicetree.cb @@ -36,13 +36,11 @@ chip northbridge/intel/sandybridge register "pci_mmio_size" = "2048" device domain 0 on - device pci 00.0 on - subsystemid 0x17aa 0x21fb - end # host bridge + subsystemid 0x17aa 0x21fb inherit + + device pci 00.0 on end # host bridge device pci 01.0 on end # PCIe Bridge for discrete graphics - device pci 02.0 on - subsystemid 0x17aa 0x21fb - end # Integrated Graphics Controller + device pci 02.0 on end # Integrated Graphics Controller chip southbridge/intel/bd82x6x # Intel Series 7 Panther Point PCH # GPI routing @@ -76,9 +74,7 @@ chip northbridge/intel/sandybridge register "spi_uvscc" = "0x2005" register "spi_lvscc" = "0x2005" - device pci 14.0 on - subsystemid 0x17aa 0x21fb - end # USB 3.0 Controller + device pci 14.0 on end # USB 3.0 Controller device pci 16.0 off end # Management Engine Interface 1 device pci 16.1 off end # Management Engine Interface 2 device pci 16.2 off end # Management Engine IDE-R @@ -86,18 +82,11 @@ chip northbridge/intel/sandybridge device pci 19.0 on subsystemid 0x17aa 0x21f3 end # Intel Gigabit Ethernet - device pci 1a.0 on - subsystemid 0x17aa 0x21fb - end # USB Enhanced Host Controller #2 - device pci 1b.0 on - subsystemid 0x17aa 0x21fb - end # High Definition Audio Controller + device pci 1a.0 on end # USB Enhanced Host Controller #2 + device pci 1b.0 on end # High Definition Audio Controller device pci 1c.0 off end # PCIe Port #1 - device pci 1c.1 on - subsystemid 0x17aa 0x21fb - end # PCIe Port #2 Integrated Wireless LAN + device pci 1c.1 on end # PCIe Port #2 Integrated Wireless LAN device pci 1c.2 on - subsystemid 0x17aa 0x21fb smbios_slot_desc "7" "3" "ExpressCard Slot" "8" end # PCIe Port #3 ExpressCard device pci 1c.3 off end # PCIe Port #4 @@ -105,15 +94,11 @@ chip northbridge/intel/sandybridge device pci 1c.5 off end # PCIe Port #6 Intel Gigabit Ethernet PHY (not PCIe) device pci 1c.6 off end # PCIe Port #7 device pci 1c.7 off end # PCIe Port #8 - device pci 1d.0 on - subsystemid 0x17aa 0x21fb - end # USB Enhanced Host Controller #1 + device pci 1d.0 on end # USB Enhanced Host Controller #1 device pci 1e.0 off end # PCI bridge device pci 1f.0 on - subsystemid 0x17aa 0x21fb chip ec/lenovo/pmh7 - device pnp ff.1 on # dummy - end + device pnp ff.1 on end # dummy register "backlight_enable" = "0x01" register "dock_event_enable" = "0x01" end @@ -155,11 +140,8 @@ chip northbridge/intel/sandybridge register "evente_enable" = "0x0d" end end # LPC Controller - device pci 1f.2 on - subsystemid 0x17aa 0x21fb - end # 6 port SATA AHCI Controller + device pci 1f.2 on end # 6 port SATA AHCI Controller device pci 1f.3 on - subsystemid 0x17aa 0x21fb # eeprom, 8 virtual devices, same chip chip drivers/i2c/at24rf08c device i2c 54 on end @@ -173,9 +155,7 @@ chip northbridge/intel/sandybridge end end # SMBus Controller device pci 1f.5 off end # SATA Controller 2 - device pci 1f.6 on - subsystemid 0x17aa 0x21fb - end # Thermal + device pci 1f.6 on end # Thermal end end end diff --git a/src/mainboard/lenovo/t430s/variants/t430s/overridetree.cb b/src/mainboard/lenovo/t430s/variants/t430s/overridetree.cb index ee949792a7..abbe4a8ce1 100644 --- a/src/mainboard/lenovo/t430s/variants/t430s/overridetree.cb +++ b/src/mainboard/lenovo/t430s/variants/t430s/overridetree.cb @@ -3,9 +3,7 @@ chip northbridge/intel/sandybridge chip southbridge/intel/bd82x6x # Intel Series 7 Panther Point PCH # Enable hotplug on Port 5 for Thunderbolt controller register "pcie_hotplug_map" = "{ 0, 0, 1, 0, 1, 0, 0, 0 }" - device pci 1c.4 on - subsystemid 0x17aa 0x21fb - end # PCIe Port #5 Thunderbolt controller + device pci 1c.4 on end # PCIe Port #5 Thunderbolt controller device pci 1f.0 on chip ec/lenovo/h8 register "has_bdc_detection" = "1" From abb0ebbb51fbaeb858736de7450e67b3b4ae5a3b Mon Sep 17 00:00:00 2001 From: Peter Lemenkov Date: Wed, 27 Nov 2019 23:16:14 +0100 Subject: [PATCH 0599/1242] mb/lenovo/s230u/devicetree: Use subsystemid inheritance Change-Id: I70eabc0b03709409d997ccbe8b8e257d68aec338 Signed-off-by: Peter Lemenkov Reviewed-on: https://review.coreboot.org/c/coreboot/+/37302 Tested-by: build bot (Jenkins) Reviewed-by: HAOUAS Elyes --- src/mainboard/lenovo/s230u/devicetree.cb | 111 +++++++---------------- 1 file changed, 35 insertions(+), 76 deletions(-) diff --git a/src/mainboard/lenovo/s230u/devicetree.cb b/src/mainboard/lenovo/s230u/devicetree.cb index 15d323d8b9..b03e2f9459 100644 --- a/src/mainboard/lenovo/s230u/devicetree.cb +++ b/src/mainboard/lenovo/s230u/devicetree.cb @@ -27,14 +27,12 @@ chip northbridge/intel/sandybridge end end device domain 0x0 on - device pci 00.0 on # Host bridge Host bridge - subsystemid 0x17aa 0x2205 - end - device pci 01.0 off # PCIe Bridge for discrete graphics - end - device pci 02.0 on # Internal graphics VGA controller - subsystemid 0x17aa 0x2205 - end + subsystemid 0x17aa 0x2205 inherit + + device pci 00.0 on end # Host bridge Host bridge + device pci 01.0 off end # PCIe Bridge for discrete graphics + device pci 02.0 on end # Internal graphics VGA controller + chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH register "c2_latency" = "0x0065" register "docking_supported" = "1" @@ -55,83 +53,44 @@ chip northbridge/intel/sandybridge register "spi_uvscc" = "0x2005" register "spi_lvscc" = "0x2005" - device pci 14.0 on # USB 3.0 Controller - subsystemid 0x17aa 0x2205 - end - device pci 16.0 off # Management Engine Interface 1 - end - device pci 16.1 off # Management Engine Interface 2 - end - device pci 16.2 off # Management Engine IDE-R - end - device pci 16.3 off # Management Engine KT - end - device pci 19.0 off # Intel Gigabit Ethernet - end - device pci 1a.0 on # USB2 EHCI #2 - subsystemid 0x17aa 0x2205 - end - device pci 1b.0 on # High Definition Audio Audio controller - subsystemid 0x17aa 0x2205 - end - device pci 1c.0 on # PCIe Port #1 - subsystemid 0x17aa 0x2205 - end - device pci 1c.1 on # PCIe Port #2 - subsystemid 0x17aa 0x2205 - end - device pci 1c.2 off # PCIe Port #3 - end - device pci 1c.3 on # PCIe Port #4 - subsystemid 0x17aa 0x2205 - end - device pci 1c.4 off # PCIe Port #5 - end - device pci 1c.5 off # PCIe Port #6 - end - device pci 1c.6 off # PCIe Port #7 - end - device pci 1c.7 off # PCIe Port #8 - end - device pci 1d.0 on # USB2 EHCI #1 - subsystemid 0x17aa 0x2205 - end - device pci 1e.0 off # PCI bridge - end + device pci 14.0 on end # USB 3.0 Controller + device pci 16.0 off end # Management Engine Interface 1 + device pci 16.1 off end # Management Engine Interface 2 + device pci 16.2 off end # Management Engine IDE-R + device pci 16.3 off end # Management Engine KT + device pci 19.0 off end # Intel Gigabit Ethernet + device pci 1a.0 on end # USB2 EHCI #2 + device pci 1b.0 on end # High Definition Audio Audio controller + device pci 1c.0 on end # PCIe Port #1 + device pci 1c.1 on end # PCIe Port #2 + device pci 1c.2 off end # PCIe Port #3 + device pci 1c.3 on end # PCIe Port #4 + device pci 1c.4 off end # PCIe Port #5 + device pci 1c.5 off end # PCIe Port #6 + device pci 1c.6 off end # PCIe Port #7 + device pci 1c.7 off end # PCIe Port #8 + device pci 1d.0 on end # USB2 EHCI #1 + device pci 1e.0 off end # PCI bridge device pci 1f.0 on # LPC bridge PCI-LPC bridge - subsystemid 0x17aa 0x2205 chip drivers/pc80/tpm device pnp 0c31.0 on end end end - device pci 1f.2 on # SATA Controller 1 - subsystemid 0x17aa 0x2205 - end + device pci 1f.2 on end # SATA Controller 1 device pci 1f.3 on # SMBus - subsystemid 0x17aa 0x2205 chip drivers/i2c/at24rf08c # eeprom, 8 virtual devices, same chip - device i2c 54 on - end - device i2c 55 on - end - device i2c 56 on - end - device i2c 57 on - end - device i2c 5c on - end - device i2c 5d on - end - device i2c 5e on - end - device i2c 5f on - end + device i2c 54 on end + device i2c 55 on end + device i2c 56 on end + device i2c 57 on end + device i2c 5c on end + device i2c 5d on end + device i2c 5e on end + device i2c 5f on end end end - device pci 1f.5 off # SATA Controller 2 - end - device pci 1f.6 off # Thermal - end + device pci 1f.5 off end # SATA Controller 2 + device pci 1f.6 off end # Thermal end end end From d01b67506735f685cdadab7a175529df23b50c8f Mon Sep 17 00:00:00 2001 From: Peter Lemenkov Date: Sat, 30 Nov 2019 21:31:22 +0100 Subject: [PATCH 0600/1242] mb/lenovo/w530/devicetree: Use subsystemid inheritance Change-Id: I0646b18e823c52109e0fb62c85726622156172b9 Signed-off-by: Peter Lemenkov Reviewed-on: https://review.coreboot.org/c/coreboot/+/37385 Reviewed-by: HAOUAS Elyes Tested-by: build bot (Jenkins) --- .../lenovo/t530/variants/w530/devicetree.cb | 107 ++++++------------ 1 file changed, 32 insertions(+), 75 deletions(-) diff --git a/src/mainboard/lenovo/t530/variants/w530/devicetree.cb b/src/mainboard/lenovo/t530/variants/w530/devicetree.cb index 0844124f0e..135627f702 100644 --- a/src/mainboard/lenovo/t530/variants/w530/devicetree.cb +++ b/src/mainboard/lenovo/t530/variants/w530/devicetree.cb @@ -37,6 +37,8 @@ chip northbridge/intel/sandybridge register "pci_mmio_size" = "2048" device domain 0x0 on + subsystemid 0x17aa 0x21f6 inherit + chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH # GPI routing # 0 No effect (default) @@ -60,67 +62,39 @@ chip northbridge/intel/sandybridge register "superspeed_capable_ports" = "0x0000000f" register "xhci_overcurrent_mapping" = "0x04000201" register "xhci_switchable_ports" = "0x0000000f" - device pci 14.0 on # USB 3.0 Controller - subsystemid 0x17aa 0x21f6 - end - device pci 16.0 on # Management Engine Interface 1 - subsystemid 0x17aa 0x21f6 - end - device pci 16.1 off # Management Engine Interface 2 - end - device pci 16.2 off # Management Engine IDE-R - end - device pci 16.3 on # Management Engine KT - subsystemid 0x17aa 0x21f6 - end + device pci 14.0 on end # USB 3.0 Controller + device pci 16.0 on end # Management Engine Interface 1 + device pci 16.1 off end # Management Engine Interface 2 + device pci 16.2 off end # Management Engine IDE-R + device pci 16.3 on end # Management Engine KT device pci 19.0 on # Intel Gigabit Ethernet subsystemid 0x17aa 0x21f3 end - device pci 1a.0 on # USB2 EHCI #2 - subsystemid 0x17aa 0x21f6 - end - device pci 1b.0 on # High Definition Audio Audio controller - subsystemid 0x17aa 0x21f6 - end + device pci 1a.0 on end # USB2 EHCI #2 + device pci 1b.0 on end # High Definition Audio Audio controller device pci 1c.0 on # PCIe Port #1 - subsystemid 0x17aa 0x21f6 chip drivers/ricoh/rce822 # Ricoh cardreader register "disable_mask" = "0x83" register "sdwppol" = "1" - device pci 00.0 on # Ricoh SD card reader - subsystemid 0x17aa 0x21f6 - end + device pci 00.0 on end # Ricoh SD card reader end end - device pci 1c.1 on # PCIe Port #2 - subsystemid 0x17aa 0x21f6 - end + device pci 1c.1 on end # PCIe Port #2 device pci 1c.2 on # PCIe Port #3 - subsystemid 0x17aa 0x21f6 smbios_slot_desc "7" "3" "ExpressCard Slot" "8" end - device pci 1c.3 off # PCIe Port #4 - end - device pci 1c.4 off # PCIe Port #5 - end - device pci 1c.5 off # PCIe Port #6 - end - device pci 1c.6 off # PCIe Port #7 - end - device pci 1c.7 off # PCIe Port #8 - end - device pci 1d.0 on # USB2 EHCI #1 - subsystemid 0x17aa 0x21f6 - end - device pci 1e.0 off # PCI bridge - end + device pci 1c.3 off end # PCIe Port #4 + device pci 1c.4 off end # PCIe Port #5 + device pci 1c.5 off end # PCIe Port #6 + device pci 1c.6 off end # PCIe Port #7 + device pci 1c.7 off end # PCIe Port #8 + device pci 1d.0 on end # USB2 EHCI #1 + device pci 1e.0 off end # PCI bridge device pci 1f.0 on # LPC bridge PCI-LPC bridge - subsystemid 0x17aa 0x21f6 chip ec/lenovo/pmh7 register "backlight_enable" = "0x01" register "dock_event_enable" = "0x01" - device pnp ff.1 on # dummy - end + device pnp ff.1 on end # dummy end chip drivers/pc80/tpm @@ -178,41 +152,24 @@ chip northbridge/intel/sandybridge register "has_thinker1" = "1" end end - device pci 1f.2 on # SATA Controller 1 - subsystemid 0x17aa 0x21f6 - end + device pci 1f.2 on end # SATA Controller 1 device pci 1f.3 on # SMBus - subsystemid 0x17aa 0x21f6 chip drivers/i2c/at24rf08c # eeprom, 8 virtual devices, same chip - device i2c 54 on - end - device i2c 55 on - end - device i2c 56 on - end - device i2c 57 on - end - device i2c 5c on - end - device i2c 5d on - end - device i2c 5e on - end - device i2c 5f on - end + device i2c 54 on end + device i2c 55 on end + device i2c 56 on end + device i2c 57 on end + device i2c 5c on end + device i2c 5d on end + device i2c 5e on end + device i2c 5f on end end end - device pci 1f.5 off # SATA Controller 2 - end - device pci 1f.6 off # Thermal - end - end - device pci 00.0 on # Host bridge Host bridge - subsystemid 0x17aa 0x21f6 - end - device pci 01.0 on # PCIe Bridge for discrete graphics - subsystemid 0x17aa 0x21f6 + device pci 1f.5 off end # SATA Controller 2 + device pci 1f.6 off end # Thermal end + device pci 00.0 on end # Host bridge Host bridge + device pci 01.0 on end # PCIe Bridge for discrete graphics device pci 02.0 on # Internal graphics VGA controller subsystemid 0x17aa 0x21f5 end From 3979def529ac6efeb37248e1bfc965112e6c86db Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Thu, 25 Jul 2019 12:19:44 +0200 Subject: [PATCH 0601/1242] payloads/bayou: remove unhooked payload The bayou payload is not attached to the build system in any way, and has not been for quite a while. Since selecting it in Kconfig does nothing, remove this payload now that coreboot 4.10 has been released. Change-Id: Icfb18b88e460a4e4b538b7efe907d4eef6c40638 Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/34565 Tested-by: build bot (Jenkins) Reviewed-by: ron minnich Reviewed-by: Nico Huber --- payloads/Kconfig | 9 - payloads/bayou/Doxyfile | 1635 ------------------------------ payloads/bayou/Makefile | 67 -- payloads/bayou/bayou.h | 83 -- payloads/bayou/bayou.ldscript | 87 -- payloads/bayou/bayou.xml.example | 37 - payloads/bayou/config.c | 161 --- payloads/bayou/lzma.c | 43 - payloads/bayou/lzmadecode.c | 398 -------- payloads/bayou/lzmadecode.h | 67 -- payloads/bayou/main.c | 66 -- payloads/bayou/menu.c | 152 --- payloads/bayou/nrv2b.c | 86 -- payloads/bayou/payload.c | 107 -- payloads/bayou/self.c | 143 --- payloads/bayou/self.h | 40 - 16 files changed, 3181 deletions(-) delete mode 100644 payloads/bayou/Doxyfile delete mode 100644 payloads/bayou/Makefile delete mode 100644 payloads/bayou/bayou.h delete mode 100644 payloads/bayou/bayou.ldscript delete mode 100644 payloads/bayou/bayou.xml.example delete mode 100644 payloads/bayou/config.c delete mode 100644 payloads/bayou/lzma.c delete mode 100644 payloads/bayou/lzmadecode.c delete mode 100644 payloads/bayou/lzmadecode.h delete mode 100644 payloads/bayou/main.c delete mode 100644 payloads/bayou/menu.c delete mode 100644 payloads/bayou/nrv2b.c delete mode 100644 payloads/bayou/payload.c delete mode 100644 payloads/bayou/self.c delete mode 100644 payloads/bayou/self.h diff --git a/payloads/Kconfig b/payloads/Kconfig index 46cfaf5ad0..4e86c21ec7 100644 --- a/payloads/Kconfig +++ b/payloads/Kconfig @@ -40,21 +40,12 @@ config PAYLOAD_FIT You will be able to specify the location and file name of the payload image later. -config PAYLOAD_BAYOU - bool "Bayou" - depends on ARCH_X86 - help - Select this option if you want to set bayou as your primary - payload. - source "payloads/external/*/Kconfig.name" endchoice source "payloads/external/*/Kconfig" -source "payloads/bayou/Kconfig" - config PAYLOAD_FILE string "Payload path and filename" depends on PAYLOAD_ELF || PAYLOAD_FIT diff --git a/payloads/bayou/Doxyfile b/payloads/bayou/Doxyfile deleted file mode 100644 index acab01c1c4..0000000000 --- a/payloads/bayou/Doxyfile +++ /dev/null @@ -1,1635 +0,0 @@ -# Doxyfile 1.7.1 - -# This file describes the settings to be used by the documentation system -# doxygen (www.doxygen.org) for a project -# -# All text after a hash (#) is considered a comment and will be ignored -# The format is: -# TAG = value [value, ...] -# For lists items can also be appended using: -# TAG += value [value, ...] -# Values that contain spaces should be placed between quotes (" ") - -#--------------------------------------------------------------------------- -# Project related configuration options -#--------------------------------------------------------------------------- - -# This tag specifies the encoding used for all characters in the config file -# that follow. The default is UTF-8 which is also the encoding used for all -# text before the first occurrence of this tag. Doxygen uses libiconv (or the -# iconv built into libc) for the transcoding. See -# http://www.gnu.org/software/libiconv for the list of possible encodings. - -DOXYFILE_ENCODING = UTF-8 - -# The PROJECT_NAME tag is a single word (or a sequence of words surrounded -# by quotes) that should identify the project. - -PROJECT_NAME = bayou - -# The PROJECT_NUMBER tag can be used to enter a project or revision number. -# This could be handy for archiving the generated documentation or -# if some version control system is used. - -PROJECT_NUMBER = - -# The OUTPUT_DIRECTORY tag is used to specify the (relative or absolute) -# base path where the generated documentation will be put. -# If a relative path is entered, it will be relative to the location -# where doxygen was started. If left blank the current directory will be used. - -OUTPUT_DIRECTORY = doxygen - -# If the CREATE_SUBDIRS tag is set to YES, then doxygen will create -# 4096 sub-directories (in 2 levels) under the output directory of each output -# format and will distribute the generated files over these directories. -# Enabling this option can be useful when feeding doxygen a huge amount of -# source files, where putting all generated files in the same directory would -# otherwise cause performance problems for the file system. - -CREATE_SUBDIRS = NO - -# The OUTPUT_LANGUAGE tag is used to specify the language in which all -# documentation generated by doxygen is written. Doxygen will use this -# information to generate all constant output in the proper language. -# The default language is English, other supported languages are: -# Afrikaans, Arabic, Brazilian, Catalan, Chinese, Chinese-Traditional, -# Croatian, Czech, Danish, Dutch, Esperanto, Farsi, Finnish, French, German, -# Greek, Hungarian, Italian, Japanese, Japanese-en (Japanese with English -# messages), Korean, Korean-en, Lithuanian, Norwegian, Macedonian, Persian, -# Polish, Portuguese, Romanian, Russian, Serbian, Serbian-Cyrilic, Slovak, -# Slovene, Spanish, Swedish, Ukrainian, and Vietnamese. - -OUTPUT_LANGUAGE = English - -# If the BRIEF_MEMBER_DESC tag is set to YES (the default) Doxygen will -# include brief member descriptions after the members that are listed in -# the file and class documentation (similar to JavaDoc). -# Set to NO to disable this. - -BRIEF_MEMBER_DESC = YES - -# If the REPEAT_BRIEF tag is set to YES (the default) Doxygen will prepend -# the brief description of a member or function before the detailed description. -# Note: if both HIDE_UNDOC_MEMBERS and BRIEF_MEMBER_DESC are set to NO, the -# brief descriptions will be completely suppressed. - -REPEAT_BRIEF = YES - -# This tag implements a quasi-intelligent brief description abbreviator -# that is used to form the text in various listings. Each string -# in this list, if found as the leading text of the brief description, will be -# stripped from the text and the result after processing the whole list, is -# used as the annotated text. Otherwise, the brief description is used as-is. -# If left blank, the following values are used ("$name" is automatically -# replaced with the name of the entity): "The $name class" "The $name widget" -# "The $name file" "is" "provides" "specifies" "contains" -# "represents" "a" "an" "the" - -ABBREVIATE_BRIEF = - -# If the ALWAYS_DETAILED_SEC and REPEAT_BRIEF tags are both set to YES then -# Doxygen will generate a detailed section even if there is only a brief -# description. - -ALWAYS_DETAILED_SEC = YES - -# If the INLINE_INHERITED_MEMB tag is set to YES, doxygen will show all -# inherited members of a class in the documentation of that class as if those -# members were ordinary class members. Constructors, destructors and assignment -# operators of the base classes will not be shown. - -INLINE_INHERITED_MEMB = NO - -# If the FULL_PATH_NAMES tag is set to YES then Doxygen will prepend the full -# path before files name in the file list and in the header files. If set -# to NO the shortest path that makes the file name unique will be used. - -FULL_PATH_NAMES = YES - -# If the FULL_PATH_NAMES tag is set to YES then the STRIP_FROM_PATH tag -# can be used to strip a user-defined part of the path. Stripping is -# only done if one of the specified strings matches the left-hand part of -# the path. The tag can be used to show relative paths in the file list. -# If left blank the directory from which doxygen is run is used as the -# path to strip. - -STRIP_FROM_PATH = - -# The STRIP_FROM_INC_PATH tag can be used to strip a user-defined part of -# the path mentioned in the documentation of a class, which tells -# the reader which header file to include in order to use a class. -# If left blank only the name of the header file containing the class -# definition is used. Otherwise one should specify the include paths that -# are normally passed to the compiler using the -I flag. - -STRIP_FROM_INC_PATH = - -# If the SHORT_NAMES tag is set to YES, doxygen will generate much shorter -# (but less readable) file names. This can be useful is your file systems -# doesn't support long names like on DOS, Mac, or CD-ROM. - -SHORT_NAMES = NO - -# If the JAVADOC_AUTOBRIEF tag is set to YES then Doxygen -# will interpret the first line (until the first dot) of a JavaDoc-style -# comment as the brief description. If set to NO, the JavaDoc -# comments will behave just like regular Qt-style comments -# (thus requiring an explicit @brief command for a brief description.) - -JAVADOC_AUTOBRIEF = YES - -# If the QT_AUTOBRIEF tag is set to YES then Doxygen will -# interpret the first line (until the first dot) of a Qt-style -# comment as the brief description. If set to NO, the comments -# will behave just like regular Qt-style comments (thus requiring -# an explicit \brief command for a brief description.) - -QT_AUTOBRIEF = NO - -# The MULTILINE_CPP_IS_BRIEF tag can be set to YES to make Doxygen -# treat a multi-line C++ special comment block (i.e. a block of //! or /// -# comments) as a brief description. This used to be the default behaviour. -# The new default is to treat a multi-line C++ comment block as a detailed -# description. Set this tag to YES if you prefer the old behaviour instead. - -MULTILINE_CPP_IS_BRIEF = NO - -# If the INHERIT_DOCS tag is set to YES (the default) then an undocumented -# member inherits the documentation from any documented member that it -# re-implements. - -INHERIT_DOCS = YES - -# If the SEPARATE_MEMBER_PAGES tag is set to YES, then doxygen will produce -# a new page for each member. If set to NO, the documentation of a member will -# be part of the file/class/namespace that contains it. - -SEPARATE_MEMBER_PAGES = NO - -# The TAB_SIZE tag can be used to set the number of spaces in a tab. -# Doxygen uses this value to replace tabs by spaces in code fragments. - -TAB_SIZE = 8 - -# This tag can be used to specify a number of aliases that acts -# as commands in the documentation. An alias has the form "name=value". -# For example adding "sideeffect=\par Side Effects:\n" will allow you to -# put the command \sideeffect (or @sideeffect) in the documentation, which -# will result in a user-defined paragraph with heading "Side Effects:". -# You can put \n's in the value part of an alias to insert newlines. - -ALIASES = - -# Set the OPTIMIZE_OUTPUT_FOR_C tag to YES if your project consists of C -# sources only. Doxygen will then generate output that is more tailored for C. -# For instance, some of the names that are used will be different. The list -# of all members will be omitted, etc. - -OPTIMIZE_OUTPUT_FOR_C = YES - -# Set the OPTIMIZE_OUTPUT_JAVA tag to YES if your project consists of Java -# sources only. Doxygen will then generate output that is more tailored for -# Java. For instance, namespaces will be presented as packages, qualified -# scopes will look different, etc. - -OPTIMIZE_OUTPUT_JAVA = NO - -# Set the OPTIMIZE_FOR_FORTRAN tag to YES if your project consists of Fortran -# sources only. Doxygen will then generate output that is more tailored for -# Fortran. - -OPTIMIZE_FOR_FORTRAN = NO - -# Set the OPTIMIZE_OUTPUT_VHDL tag to YES if your project consists of VHDL -# sources. Doxygen will then generate output that is tailored for -# VHDL. - -OPTIMIZE_OUTPUT_VHDL = NO - -# Doxygen selects the parser to use depending on the extension of the files it -# parses. With this tag you can assign which parser to use for a given extension. -# Doxygen has a built-in mapping, but you can override or extend it using this -# tag. The format is ext=language, where ext is a file extension, and language -# is one of the parsers supported by doxygen: IDL, Java, Javascript, CSharp, C, -# C++, D, PHP, Objective-C, Python, Fortran, VHDL, C, C++. For instance to make -# doxygen treat .inc files as Fortran files (default is PHP), and .f files as C -# (default is Fortran), use: inc=Fortran f=C. Note that for custom extensions -# you also need to set FILE_PATTERNS otherwise the files are not read by doxygen. - -EXTENSION_MAPPING = - -# If you use STL classes (i.e. std::string, std::vector, etc.) but do not want -# to include (a tag file for) the STL sources as input, then you should -# set this tag to YES in order to let doxygen match functions declarations and -# definitions whose arguments contain STL classes (e.g. func(std::string); v.s. -# func(std::string) {}). This also make the inheritance and collaboration -# diagrams that involve STL classes more complete and accurate. - -BUILTIN_STL_SUPPORT = NO - -# If you use Microsoft's C++/CLI language, you should set this option to YES to -# enable parsing support. - -CPP_CLI_SUPPORT = NO - -# Set the SIP_SUPPORT tag to YES if your project consists of sip sources only. -# Doxygen will parse them like normal C++ but will assume all classes use public -# instead of private inheritance when no explicit protection keyword is present. - -SIP_SUPPORT = NO - -# For Microsoft's IDL there are propget and propput attributes to indicate getter -# and setter methods for a property. Setting this option to YES (the default) -# will make doxygen to replace the get and set methods by a property in the -# documentation. This will only work if the methods are indeed getting or -# setting a simple type. If this is not the case, or you want to show the -# methods anyway, you should set this option to NO. - -IDL_PROPERTY_SUPPORT = YES - -# If member grouping is used in the documentation and the DISTRIBUTE_GROUP_DOC -# tag is set to YES, then doxygen will reuse the documentation of the first -# member in the group (if any) for the other members of the group. By default -# all members of a group must be documented explicitly. - -DISTRIBUTE_GROUP_DOC = NO - -# Set the SUBGROUPING tag to YES (the default) to allow class member groups of -# the same type (for instance a group of public functions) to be put as a -# subgroup of that type (e.g. under the Public Functions section). Set it to -# NO to prevent subgrouping. Alternatively, this can be done per class using -# the \nosubgrouping command. - -SUBGROUPING = YES - -# When TYPEDEF_HIDES_STRUCT is enabled, a typedef of a struct, union, or enum -# is documented as struct, union, or enum with the name of the typedef. So -# typedef struct TypeS {} TypeT, will appear in the documentation as a struct -# with name TypeT. When disabled the typedef will appear as a member of a file, -# namespace, or class. And the struct will be named TypeS. This can typically -# be useful for C code in case the coding convention dictates that all compound -# types are typedef'ed and only the typedef is referenced, never the tag name. - -TYPEDEF_HIDES_STRUCT = NO - -# The SYMBOL_CACHE_SIZE determines the size of the internal cache use to -# determine which symbols to keep in memory and which to flush to disk. -# When the cache is full, less often used symbols will be written to disk. -# For small to medium size projects (<1000 input files) the default value is -# probably good enough. For larger projects a too small cache size can cause -# doxygen to be busy swapping symbols to and from disk most of the time -# causing a significant performance penality. -# If the system has enough physical memory increasing the cache will improve the -# performance by keeping more symbols in memory. Note that the value works on -# a logarithmic scale so increasing the size by one will rougly double the -# memory usage. The cache size is given by this formula: -# 2^(16+SYMBOL_CACHE_SIZE). The valid range is 0..9, the default is 0, -# corresponding to a cache size of 2^16 = 65536 symbols - -SYMBOL_CACHE_SIZE = 0 - -#--------------------------------------------------------------------------- -# Build related configuration options -#--------------------------------------------------------------------------- - -# If the EXTRACT_ALL tag is set to YES doxygen will assume all entities in -# documentation are documented, even if no documentation was available. -# Private class members and static file members will be hidden unless -# the EXTRACT_PRIVATE and EXTRACT_STATIC tags are set to YES - -EXTRACT_ALL = YES - -# If the EXTRACT_PRIVATE tag is set to YES all private members of a class -# will be included in the documentation. - -EXTRACT_PRIVATE = NO - -# If the EXTRACT_STATIC tag is set to YES all static members of a file -# will be included in the documentation. - -EXTRACT_STATIC = YES - -# If the EXTRACT_LOCAL_CLASSES tag is set to YES classes (and structs) -# defined locally in source files will be included in the documentation. -# If set to NO only classes defined in header files are included. - -EXTRACT_LOCAL_CLASSES = YES - -# This flag is only useful for Objective-C code. When set to YES local -# methods, which are defined in the implementation section but not in -# the interface are included in the documentation. -# If set to NO (the default) only methods in the interface are included. - -EXTRACT_LOCAL_METHODS = NO - -# If this flag is set to YES, the members of anonymous namespaces will be -# extracted and appear in the documentation as a namespace called -# 'anonymous_namespace{file}', where file will be replaced with the base -# name of the file that contains the anonymous namespace. By default -# anonymous namespace are hidden. - -EXTRACT_ANON_NSPACES = NO - -# If the HIDE_UNDOC_MEMBERS tag is set to YES, Doxygen will hide all -# undocumented members of documented classes, files or namespaces. -# If set to NO (the default) these members will be included in the -# various overviews, but no documentation section is generated. -# This option has no effect if EXTRACT_ALL is enabled. - -HIDE_UNDOC_MEMBERS = NO - -# If the HIDE_UNDOC_CLASSES tag is set to YES, Doxygen will hide all -# undocumented classes that are normally visible in the class hierarchy. -# If set to NO (the default) these classes will be included in the various -# overviews. This option has no effect if EXTRACT_ALL is enabled. - -HIDE_UNDOC_CLASSES = NO - -# If the HIDE_FRIEND_COMPOUNDS tag is set to YES, Doxygen will hide all -# friend (class|struct|union) declarations. -# If set to NO (the default) these declarations will be included in the -# documentation. - -HIDE_FRIEND_COMPOUNDS = NO - -# If the HIDE_IN_BODY_DOCS tag is set to YES, Doxygen will hide any -# documentation blocks found inside the body of a function. -# If set to NO (the default) these blocks will be appended to the -# function's detailed documentation block. - -HIDE_IN_BODY_DOCS = NO - -# The INTERNAL_DOCS tag determines if documentation -# that is typed after a \internal command is included. If the tag is set -# to NO (the default) then the documentation will be excluded. -# Set it to YES to include the internal documentation. - -INTERNAL_DOCS = NO - -# If the CASE_SENSE_NAMES tag is set to NO then Doxygen will only generate -# file names in lower-case letters. If set to YES upper-case letters are also -# allowed. This is useful if you have classes or files whose names only differ -# in case and if your file system supports case sensitive file names. Windows -# and Mac users are advised to set this option to NO. - -CASE_SENSE_NAMES = YES - -# If the HIDE_SCOPE_NAMES tag is set to NO (the default) then Doxygen -# will show members with their full class and namespace scopes in the -# documentation. If set to YES the scope will be hidden. - -HIDE_SCOPE_NAMES = NO - -# If the SHOW_INCLUDE_FILES tag is set to YES (the default) then Doxygen -# will put a list of the files that are included by a file in the documentation -# of that file. - -SHOW_INCLUDE_FILES = YES - -# If the FORCE_LOCAL_INCLUDES tag is set to YES then Doxygen -# will list include files with double quotes in the documentation -# rather than with sharp brackets. - -FORCE_LOCAL_INCLUDES = NO - -# If the INLINE_INFO tag is set to YES (the default) then a tag [inline] -# is inserted in the documentation for inline members. - -INLINE_INFO = YES - -# If the SORT_MEMBER_DOCS tag is set to YES (the default) then doxygen -# will sort the (detailed) documentation of file and class members -# alphabetically by member name. If set to NO the members will appear in -# declaration order. - -SORT_MEMBER_DOCS = YES - -# If the SORT_BRIEF_DOCS tag is set to YES then doxygen will sort the -# brief documentation of file, namespace and class members alphabetically -# by member name. If set to NO (the default) the members will appear in -# declaration order. - -SORT_BRIEF_DOCS = NO - -# If the SORT_MEMBERS_CTORS_1ST tag is set to YES then doxygen -# will sort the (brief and detailed) documentation of class members so that -# constructors and destructors are listed first. If set to NO (the default) -# the constructors will appear in the respective orders defined by -# SORT_MEMBER_DOCS and SORT_BRIEF_DOCS. -# This tag will be ignored for brief docs if SORT_BRIEF_DOCS is set to NO -# and ignored for detailed docs if SORT_MEMBER_DOCS is set to NO. - -SORT_MEMBERS_CTORS_1ST = NO - -# If the SORT_GROUP_NAMES tag is set to YES then doxygen will sort the -# hierarchy of group names into alphabetical order. If set to NO (the default) -# the group names will appear in their defined order. - -SORT_GROUP_NAMES = NO - -# If the SORT_BY_SCOPE_NAME tag is set to YES, the class list will be -# sorted by fully-qualified names, including namespaces. If set to -# NO (the default), the class list will be sorted only by class name, -# not including the namespace part. -# Note: This option is not very useful if HIDE_SCOPE_NAMES is set to YES. -# Note: This option applies only to the class list, not to the -# alphabetical list. - -SORT_BY_SCOPE_NAME = NO - -# The GENERATE_TODOLIST tag can be used to enable (YES) or -# disable (NO) the todo list. This list is created by putting \todo -# commands in the documentation. - -GENERATE_TODOLIST = YES - -# The GENERATE_TESTLIST tag can be used to enable (YES) or -# disable (NO) the test list. This list is created by putting \test -# commands in the documentation. - -GENERATE_TESTLIST = YES - -# The GENERATE_BUGLIST tag can be used to enable (YES) or -# disable (NO) the bug list. This list is created by putting \bug -# commands in the documentation. - -GENERATE_BUGLIST = YES - -# The GENERATE_DEPRECATEDLIST tag can be used to enable (YES) or -# disable (NO) the deprecated list. This list is created by putting -# \deprecated commands in the documentation. - -GENERATE_DEPRECATEDLIST= YES - -# The ENABLED_SECTIONS tag can be used to enable conditional -# documentation sections, marked by \if sectionname ... \endif. - -ENABLED_SECTIONS = - -# The MAX_INITIALIZER_LINES tag determines the maximum number of lines -# the initial value of a variable or define consists of for it to appear in -# the documentation. If the initializer consists of more lines than specified -# here it will be hidden. Use a value of 0 to hide initializers completely. -# The appearance of the initializer of individual variables and defines in the -# documentation can be controlled using \showinitializer or \hideinitializer -# command in the documentation regardless of this setting. - -MAX_INITIALIZER_LINES = 30 - -# Set the SHOW_USED_FILES tag to NO to disable the list of files generated -# at the bottom of the documentation of classes and structs. If set to YES the -# list will mention the files that were used to generate the documentation. - -SHOW_USED_FILES = YES - -# If the sources in your project are distributed over multiple directories -# then setting the SHOW_DIRECTORIES tag to YES will show the directory hierarchy -# in the documentation. The default is NO. - -SHOW_DIRECTORIES = YES - -# Set the SHOW_FILES tag to NO to disable the generation of the Files page. -# This will remove the Files entry from the Quick Index and from the -# Folder Tree View (if specified). The default is YES. - -SHOW_FILES = YES - -# Set the SHOW_NAMESPACES tag to NO to disable the generation of the -# Namespaces page. -# This will remove the Namespaces entry from the Quick Index -# and from the Folder Tree View (if specified). The default is YES. - -SHOW_NAMESPACES = YES - -# The FILE_VERSION_FILTER tag can be used to specify a program or script that -# doxygen should invoke to get the current version for each file (typically from -# the version control system). Doxygen will invoke the program by executing (via -# popen()) the command , where is the value of -# the FILE_VERSION_FILTER tag, and is the name of an input file -# provided by doxygen. Whatever the program writes to standard output -# is used as the file version. See the manual for examples. - -FILE_VERSION_FILTER = - -# The LAYOUT_FILE tag can be used to specify a layout file which will be parsed -# by doxygen. The layout file controls the global structure of the generated -# output files in an output format independent way. The create the layout file -# that represents doxygen's defaults, run doxygen with the -l option. -# You can optionally specify a file name after the option, if omitted -# DoxygenLayout.xml will be used as the name of the layout file. - -LAYOUT_FILE = - -#--------------------------------------------------------------------------- -# configuration options related to warning and progress messages -#--------------------------------------------------------------------------- - -# The QUIET tag can be used to turn on/off the messages that are generated -# by doxygen. Possible values are YES and NO. If left blank NO is used. - -QUIET = NO - -# The WARNINGS tag can be used to turn on/off the warning messages that are -# generated by doxygen. Possible values are YES and NO. If left blank -# NO is used. - -WARNINGS = YES - -# If WARN_IF_UNDOCUMENTED is set to YES, then doxygen will generate warnings -# for undocumented members. If EXTRACT_ALL is set to YES then this flag will -# automatically be disabled. - -WARN_IF_UNDOCUMENTED = YES - -# If WARN_IF_DOC_ERROR is set to YES, doxygen will generate warnings for -# potential errors in the documentation, such as not documenting some -# parameters in a documented function, or documenting parameters that -# don't exist or using markup commands wrongly. - -WARN_IF_DOC_ERROR = YES - -# This WARN_NO_PARAMDOC option can be abled to get warnings for -# functions that are documented, but have no documentation for their parameters -# or return value. If set to NO (the default) doxygen will only warn about -# wrong or incomplete parameter documentation, but not about the absence of -# documentation. - -WARN_NO_PARAMDOC = YES - -# The WARN_FORMAT tag determines the format of the warning messages that -# doxygen can produce. The string should contain the $file, $line, and $text -# tags, which will be replaced by the file and line number from which the -# warning originated and the warning text. Optionally the format may contain -# $version, which will be replaced by the version of the file (if it could -# be obtained via FILE_VERSION_FILTER) - -WARN_FORMAT = "$file:$line: $text" - -# The WARN_LOGFILE tag can be used to specify a file to which warning -# and error messages should be written. If left blank the output is written -# to stderr. - -WARN_LOGFILE = - -#--------------------------------------------------------------------------- -# configuration options related to the input files -#--------------------------------------------------------------------------- - -# The INPUT tag can be used to specify the files and/or directories that contain -# documented source files. You may enter file names like "myfile.cpp" or -# directories like "/usr/src/myproject". Separate the files or directories -# with spaces. - -INPUT = . - -# This tag can be used to specify the character encoding of the source files -# that doxygen parses. Internally doxygen uses the UTF-8 encoding, which is -# also the default input encoding. Doxygen uses libiconv (or the iconv built -# into libc) for the transcoding. See http://www.gnu.org/software/libiconv for -# the list of possible encodings. - -INPUT_ENCODING = UTF-8 - -# If the value of the INPUT tag contains directories, you can use the -# FILE_PATTERNS tag to specify one or more wildcard pattern (like *.cpp -# and *.h) to filter out the source-files in the directories. If left -# blank the following patterns are tested: -# *.c *.cc *.cxx *.cpp *.c++ *.java *.ii *.ixx *.ipp *.i++ *.inl *.h *.hh *.hxx -# *.hpp *.h++ *.idl *.odl *.cs *.php *.php3 *.inc *.m *.mm *.py *.f90 - -FILE_PATTERNS = - -# The RECURSIVE tag can be used to turn specify whether or not subdirectories -# should be searched for input files as well. Possible values are YES and NO. -# If left blank NO is used. - -RECURSIVE = YES - -# The EXCLUDE tag can be used to specify files and/or directories that should -# excluded from the INPUT source files. This way you can easily exclude a -# subdirectory from a directory tree whose root is specified with the INPUT tag. - -EXCLUDE = util/kconfig - -# The EXCLUDE_SYMLINKS tag can be used select whether or not files or -# directories that are symbolic links (a Unix filesystem feature) are excluded -# from the input. - -EXCLUDE_SYMLINKS = NO - -# If the value of the INPUT tag contains directories, you can use the -# EXCLUDE_PATTERNS tag to specify one or more wildcard patterns to exclude -# certain files from those directories. Note that the wildcards are matched -# against the file with absolute path, so to exclude all test directories -# for example use the pattern */test/* - -EXCLUDE_PATTERNS = - -# The EXCLUDE_SYMBOLS tag can be used to specify one or more symbol names -# (namespaces, classes, functions, etc.) that should be excluded from the -# output. The symbol name can be a fully qualified name, a word, or if the -# wildcard * is used, a substring. Examples: ANamespace, AClass, -# AClass::ANamespace, ANamespace::*Test - -EXCLUDE_SYMBOLS = - -# The EXAMPLE_PATH tag can be used to specify one or more files or -# directories that contain example code fragments that are included (see -# the \include command). - -EXAMPLE_PATH = - -# If the value of the EXAMPLE_PATH tag contains directories, you can use the -# EXAMPLE_PATTERNS tag to specify one or more wildcard pattern (like *.cpp -# and *.h) to filter out the source-files in the directories. If left -# blank all files are included. - -EXAMPLE_PATTERNS = - -# If the EXAMPLE_RECURSIVE tag is set to YES then subdirectories will be -# searched for input files to be used with the \include or \dontinclude -# commands irrespective of the value of the RECURSIVE tag. -# Possible values are YES and NO. If left blank NO is used. - -EXAMPLE_RECURSIVE = NO - -# The IMAGE_PATH tag can be used to specify one or more files or -# directories that contain image that are included in the documentation (see -# the \image command). - -IMAGE_PATH = - -# The INPUT_FILTER tag can be used to specify a program that doxygen should -# invoke to filter for each input file. Doxygen will invoke the filter program -# by executing (via popen()) the command , where -# is the value of the INPUT_FILTER tag, and is the name of an -# input file. Doxygen will then use the output that the filter program writes -# to standard output. -# If FILTER_PATTERNS is specified, this tag will be -# ignored. - -INPUT_FILTER = - -# The FILTER_PATTERNS tag can be used to specify filters on a per file pattern -# basis. -# Doxygen will compare the file name with each pattern and apply the -# filter if there is a match. -# The filters are a list of the form: -# pattern=filter (like *.cpp=my_cpp_filter). See INPUT_FILTER for further -# info on how filters are used. If FILTER_PATTERNS is empty, INPUT_FILTER -# is applied to all files. - -FILTER_PATTERNS = - -# If the FILTER_SOURCE_FILES tag is set to YES, the input filter (if set using -# INPUT_FILTER) will be used to filter the input files when producing source -# files to browse (i.e. when SOURCE_BROWSER is set to YES). - -FILTER_SOURCE_FILES = NO - -#--------------------------------------------------------------------------- -# configuration options related to source browsing -#--------------------------------------------------------------------------- - -# If the SOURCE_BROWSER tag is set to YES then a list of source files will -# be generated. Documented entities will be cross-referenced with these sources. -# Note: To get rid of all source code in the generated output, make sure also -# VERBATIM_HEADERS is set to NO. - -SOURCE_BROWSER = YES - -# Setting the INLINE_SOURCES tag to YES will include the body -# of functions and classes directly in the documentation. - -INLINE_SOURCES = NO - -# Setting the STRIP_CODE_COMMENTS tag to YES (the default) will instruct -# doxygen to hide any special comment blocks from generated source code -# fragments. Normal C and C++ comments will always remain visible. - -STRIP_CODE_COMMENTS = NO - -# If the REFERENCED_BY_RELATION tag is set to YES -# then for each documented function all documented -# functions referencing it will be listed. - -REFERENCED_BY_RELATION = YES - -# If the REFERENCES_RELATION tag is set to YES -# then for each documented function all documented entities -# called/used by that function will be listed. - -REFERENCES_RELATION = YES - -# If the REFERENCES_LINK_SOURCE tag is set to YES (the default) -# and SOURCE_BROWSER tag is set to YES, then the hyperlinks from -# functions in REFERENCES_RELATION and REFERENCED_BY_RELATION lists will -# link to the source code. -# Otherwise they will link to the documentation. - -REFERENCES_LINK_SOURCE = YES - -# If the USE_HTAGS tag is set to YES then the references to source code -# will point to the HTML generated by the htags(1) tool instead of doxygen -# built-in source browser. The htags tool is part of GNU's global source -# tagging system (see http://www.gnu.org/software/global/global.html). You -# will need version 4.8.6 or higher. - -USE_HTAGS = NO - -# If the VERBATIM_HEADERS tag is set to YES (the default) then Doxygen -# will generate a verbatim copy of the header file for each class for -# which an include is specified. Set to NO to disable this. - -VERBATIM_HEADERS = YES - -#--------------------------------------------------------------------------- -# configuration options related to the alphabetical class index -#--------------------------------------------------------------------------- - -# If the ALPHABETICAL_INDEX tag is set to YES, an alphabetical index -# of all compounds will be generated. Enable this if the project -# contains a lot of classes, structs, unions or interfaces. - -ALPHABETICAL_INDEX = YES - -# If the alphabetical index is enabled (see ALPHABETICAL_INDEX) then -# the COLS_IN_ALPHA_INDEX tag can be used to specify the number of columns -# in which this list will be split (can be a number in the range [1..20]) - -COLS_IN_ALPHA_INDEX = 5 - -# In case all classes in a project start with a common prefix, all -# classes will be put under the same header in the alphabetical index. -# The IGNORE_PREFIX tag can be used to specify one or more prefixes that -# should be ignored while generating the index headers. - -IGNORE_PREFIX = - -#--------------------------------------------------------------------------- -# configuration options related to the HTML output -#--------------------------------------------------------------------------- - -# If the GENERATE_HTML tag is set to YES (the default) Doxygen will -# generate HTML output. - -GENERATE_HTML = YES - -# The HTML_OUTPUT tag is used to specify where the HTML docs will be put. -# If a relative path is entered the value of OUTPUT_DIRECTORY will be -# put in front of it. If left blank `html' will be used as the default path. - -HTML_OUTPUT = html - -# The HTML_FILE_EXTENSION tag can be used to specify the file extension for -# each generated HTML page (for example: .htm,.php,.asp). If it is left blank -# doxygen will generate files with .html extension. - -HTML_FILE_EXTENSION = .html - -# The HTML_HEADER tag can be used to specify a personal HTML header for -# each generated HTML page. If it is left blank doxygen will generate a -# standard header. - -HTML_HEADER = - -# The HTML_FOOTER tag can be used to specify a personal HTML footer for -# each generated HTML page. If it is left blank doxygen will generate a -# standard footer. - -HTML_FOOTER = - -# If the HTML_FOOTER_DESCRIPTION tag is set to YES, Doxygen will -# add generated date, project name and doxygen version to HTML footer. - -HTML_FOOTER_DESCRIPTION= YES - -# The HTML_STYLESHEET tag can be used to specify a user-defined cascading -# style sheet that is used by each HTML page. It can be used to -# fine-tune the look of the HTML output. If the tag is left blank doxygen -# will generate a default style sheet. Note that doxygen will try to copy -# the style sheet file to the HTML output directory, so don't put your own -# stylesheet in the HTML output directory as well, or it will be erased! - -HTML_STYLESHEET = - -# The HTML_COLORSTYLE_HUE tag controls the color of the HTML output. -# Doxygen will adjust the colors in the stylesheet and background images -# according to this color. Hue is specified as an angle on a colorwheel, -# see http://en.wikipedia.org/wiki/Hue for more information. -# For instance the value 0 represents red, 60 is yellow, 120 is green, -# 180 is cyan, 240 is blue, 300 purple, and 360 is red again. -# The allowed range is 0 to 359. - -HTML_COLORSTYLE_HUE = 220 - -# The HTML_COLORSTYLE_SAT tag controls the purity (or saturation) of -# the colors in the HTML output. For a value of 0 the output will use -# grayscales only. A value of 255 will produce the most vivid colors. - -HTML_COLORSTYLE_SAT = 100 - -# The HTML_COLORSTYLE_GAMMA tag controls the gamma correction applied to -# the luminance component of the colors in the HTML output. Values below -# 100 gradually make the output lighter, whereas values above 100 make -# the output darker. The value divided by 100 is the actual gamma applied, -# so 80 represents a gamma of 0.8, The value 220 represents a gamma of 2.2, -# and 100 does not change the gamma. - -HTML_COLORSTYLE_GAMMA = 80 - -# If the HTML_TIMESTAMP tag is set to YES then the footer of each generated HTML -# page will contain the date and time when the page was generated. Setting -# this to NO can help when comparing the output of multiple runs. - -HTML_TIMESTAMP = NO - -# If the HTML_ALIGN_MEMBERS tag is set to YES, the members of classes, -# files or namespaces will be aligned in HTML using tables. If set to -# NO a bullet list will be used. - -HTML_ALIGN_MEMBERS = YES - -# If the HTML_DYNAMIC_SECTIONS tag is set to YES then the generated HTML -# documentation will contain sections that can be hidden and shown after the -# page has loaded. For this to work a browser that supports -# JavaScript and DHTML is required (for instance Mozilla 1.0+, Firefox -# Netscape 6.0+, Internet explorer 5.0+, Konqueror, or Safari). - -HTML_DYNAMIC_SECTIONS = YES - -# If the GENERATE_DOCSET tag is set to YES, additional index files -# will be generated that can be used as input for Apple's Xcode 3 -# integrated development environment, introduced with OSX 10.5 (Leopard). -# To create a documentation set, doxygen will generate a Makefile in the -# HTML output directory. Running make will produce the docset in that -# directory and running "make install" will install the docset in -# ~/Library/Developer/Shared/Documentation/DocSets so that Xcode will find -# it at startup. -# See http://developer.apple.com/tools/creatingdocsetswithdoxygen.html -# for more information. - -GENERATE_DOCSET = NO - -# When GENERATE_DOCSET tag is set to YES, this tag determines the name of the -# feed. A documentation feed provides an umbrella under which multiple -# documentation sets from a single provider (such as a company or product suite) -# can be grouped. - -DOCSET_FEEDNAME = "Doxygen generated docs" - -# When GENERATE_DOCSET tag is set to YES, this tag specifies a string that -# should uniquely identify the documentation set bundle. This should be a -# reverse domain-name style string, e.g. com.mycompany.MyDocSet. Doxygen -# will append .docset to the name. - -DOCSET_BUNDLE_ID = org.doxygen.Project - -# When GENERATE_PUBLISHER_ID tag specifies a string that should uniquely identify -# the documentation publisher. This should be a reverse domain-name style -# string, e.g. com.mycompany.MyDocSet.documentation. - -DOCSET_PUBLISHER_ID = org.doxygen.Publisher - -# The GENERATE_PUBLISHER_NAME tag identifies the documentation publisher. - -DOCSET_PUBLISHER_NAME = Publisher - -# If the GENERATE_HTMLHELP tag is set to YES, additional index files -# will be generated that can be used as input for tools like the -# Microsoft HTML help workshop to generate a compiled HTML help file (.chm) -# of the generated HTML documentation. - -GENERATE_HTMLHELP = NO - -# If the GENERATE_HTMLHELP tag is set to YES, the CHM_FILE tag can -# be used to specify the file name of the resulting .chm file. You -# can add a path in front of the file if the result should not be -# written to the html output directory. - -CHM_FILE = - -# If the GENERATE_HTMLHELP tag is set to YES, the HHC_LOCATION tag can -# be used to specify the location (absolute path including file name) of -# the HTML help compiler (hhc.exe). If non-empty doxygen will try to run -# the HTML help compiler on the generated index.hhp. - -HHC_LOCATION = - -# If the GENERATE_HTMLHELP tag is set to YES, the GENERATE_CHI flag -# controls if a separate .chi index file is generated (YES) or that -# it should be included in the master .chm file (NO). - -GENERATE_CHI = NO - -# If the GENERATE_HTMLHELP tag is set to YES, the CHM_INDEX_ENCODING -# is used to encode HtmlHelp index (hhk), content (hhc) and project file -# content. - -CHM_INDEX_ENCODING = - -# If the GENERATE_HTMLHELP tag is set to YES, the BINARY_TOC flag -# controls whether a binary table of contents is generated (YES) or a -# normal table of contents (NO) in the .chm file. - -BINARY_TOC = NO - -# The TOC_EXPAND flag can be set to YES to add extra items for group members -# to the contents of the HTML help documentation and to the tree view. - -TOC_EXPAND = NO - -# If the GENERATE_QHP tag is set to YES and both QHP_NAMESPACE and -# QHP_VIRTUAL_FOLDER are set, an additional index file will be generated -# that can be used as input for Qt's qhelpgenerator to generate a -# Qt Compressed Help (.qch) of the generated HTML documentation. - -GENERATE_QHP = NO - -# If the QHG_LOCATION tag is specified, the QCH_FILE tag can -# be used to specify the file name of the resulting .qch file. -# The path specified is relative to the HTML output folder. - -QCH_FILE = - -# The QHP_NAMESPACE tag specifies the namespace to use when generating -# Qt Help Project output. For more information please see -# http://doc.trolltech.com/qthelpproject.html#namespace - -QHP_NAMESPACE = org.doxygen.Project - -# The QHP_VIRTUAL_FOLDER tag specifies the namespace to use when generating -# Qt Help Project output. For more information please see -# http://doc.trolltech.com/qthelpproject.html#virtual-folders - -QHP_VIRTUAL_FOLDER = doc - -# If QHP_CUST_FILTER_NAME is set, it specifies the name of a custom filter to -# add. For more information please see -# http://doc.trolltech.com/qthelpproject.html#custom-filters - -QHP_CUST_FILTER_NAME = - -# The QHP_CUST_FILT_ATTRS tag specifies the list of the attributes of the -# custom filter to add. For more information please see -# -# Qt Help Project / Custom Filters. - -QHP_CUST_FILTER_ATTRS = - -# The QHP_SECT_FILTER_ATTRS tag specifies the list of the attributes this -# project's -# filter section matches. -# -# Qt Help Project / Filter Attributes. - -QHP_SECT_FILTER_ATTRS = - -# If the GENERATE_QHP tag is set to YES, the QHG_LOCATION tag can -# be used to specify the location of Qt's qhelpgenerator. -# If non-empty doxygen will try to run qhelpgenerator on the generated -# .qhp file. - -QHG_LOCATION = - -# If the GENERATE_ECLIPSEHELP tag is set to YES, additional index files -# will be generated, which together with the HTML files, form an Eclipse help -# plugin. To install this plugin and make it available under the help contents -# menu in Eclipse, the contents of the directory containing the HTML and XML -# files needs to be copied into the plugins directory of eclipse. The name of -# the directory within the plugins directory should be the same as -# the ECLIPSE_DOC_ID value. After copying Eclipse needs to be restarted before -# the help appears. - -GENERATE_ECLIPSEHELP = NO - -# A unique identifier for the eclipse help plugin. When installing the plugin -# the directory name containing the HTML and XML files should also have -# this name. - -ECLIPSE_DOC_ID = org.doxygen.Project - -# The DISABLE_INDEX tag can be used to turn on/off the condensed index at -# top of each HTML page. The value NO (the default) enables the index and -# the value YES disables it. - -DISABLE_INDEX = NO - -# This tag can be used to set the number of enum values (range [1..20]) -# that doxygen will group on one line in the generated HTML documentation. - -ENUM_VALUES_PER_LINE = 4 - -# The GENERATE_TREEVIEW tag is used to specify whether a tree-like index -# structure should be generated to display hierarchical information. -# If the tag value is set to YES, a side panel will be generated -# containing a tree-like index structure (just like the one that -# is generated for HTML Help). For this to work a browser that supports -# JavaScript, DHTML, CSS and frames is required (i.e. any modern browser). -# Windows users are probably better off using the HTML help feature. - -GENERATE_TREEVIEW = YES - -# By enabling USE_INLINE_TREES, doxygen will generate the Groups, Directories, -# and Class Hierarchy pages using a tree view instead of an ordered list. - -USE_INLINE_TREES = NO - -# If the treeview is enabled (see GENERATE_TREEVIEW) then this tag can be -# used to set the initial width (in pixels) of the frame in which the tree -# is shown. - -TREEVIEW_WIDTH = 250 - -# When the EXT_LINKS_IN_WINDOW option is set to YES doxygen will open -# links to external symbols imported via tag files in a separate window. - -EXT_LINKS_IN_WINDOW = NO - -# Use this tag to change the font size of Latex formulas included -# as images in the HTML documentation. The default is 10. Note that -# when you change the font size after a successful doxygen run you need -# to manually remove any form_*.png images from the HTML output directory -# to force them to be regenerated. - -FORMULA_FONTSIZE = 10 - -# Use the FORMULA_TRANPARENT tag to determine whether or not the images -# generated for formulas are transparent PNGs. Transparent PNGs are -# not supported properly for IE 6.0, but are supported on all modern browsers. -# Note that when changing this option you need to delete any form_*.png files -# in the HTML output before the changes have effect. - -FORMULA_TRANSPARENT = YES - -# When the SEARCHENGINE tag is enabled doxygen will generate a search box -# for the HTML output. The underlying search engine uses javascript -# and DHTML and should work on any modern browser. Note that when using -# HTML help (GENERATE_HTMLHELP), Qt help (GENERATE_QHP), or docsets -# (GENERATE_DOCSET) there is already a search function so this one should -# typically be disabled. For large projects the javascript based search engine -# can be slow, then enabling SERVER_BASED_SEARCH may provide a better solution. - -SEARCHENGINE = YES - -# When the SERVER_BASED_SEARCH tag is enabled the search engine will be -# implemented using a PHP enabled web server instead of at the web client -# using Javascript. Doxygen will generate the search PHP script and index -# file to put on the web server. The advantage of the server -# based approach is that it scales better to large projects and allows -# full text search. The disadvances is that it is more difficult to setup -# and does not have live searching capabilities. - -SERVER_BASED_SEARCH = NO - -#--------------------------------------------------------------------------- -# configuration options related to the LaTeX output -#--------------------------------------------------------------------------- - -# If the GENERATE_LATEX tag is set to YES (the default) Doxygen will -# generate Latex output. - -GENERATE_LATEX = NO - -# The LATEX_OUTPUT tag is used to specify where the LaTeX docs will be put. -# If a relative path is entered the value of OUTPUT_DIRECTORY will be -# put in front of it. If left blank `latex' will be used as the default path. - -LATEX_OUTPUT = latex - -# The LATEX_CMD_NAME tag can be used to specify the LaTeX command name to be -# invoked. If left blank `latex' will be used as the default command name. -# Note that when enabling USE_PDFLATEX this option is only used for -# generating bitmaps for formulas in the HTML output, but not in the -# Makefile that is written to the output directory. - -LATEX_CMD_NAME = latex - -# The MAKEINDEX_CMD_NAME tag can be used to specify the command name to -# generate index for LaTeX. If left blank `makeindex' will be used as the -# default command name. - -MAKEINDEX_CMD_NAME = makeindex - -# If the COMPACT_LATEX tag is set to YES Doxygen generates more compact -# LaTeX documents. This may be useful for small projects and may help to -# save some trees in general. - -COMPACT_LATEX = NO - -# The PAPER_TYPE tag can be used to set the paper type that is used -# by the printer. Possible values are: a4, a4wide, letter, legal and -# executive. If left blank a4wide will be used. - -PAPER_TYPE = a4wide - -# The EXTRA_PACKAGES tag can be to specify one or more names of LaTeX -# packages that should be included in the LaTeX output. - -EXTRA_PACKAGES = - -# The LATEX_HEADER tag can be used to specify a personal LaTeX header for -# the generated latex document. The header should contain everything until -# the first chapter. If it is left blank doxygen will generate a -# standard header. Notice: only use this tag if you know what you are doing! - -LATEX_HEADER = - -# If the PDF_HYPERLINKS tag is set to YES, the LaTeX that is generated -# is prepared for conversion to pdf (using ps2pdf). The pdf file will -# contain links (just like the HTML output) instead of page references -# This makes the output suitable for online browsing using a pdf viewer. - -PDF_HYPERLINKS = NO - -# If the USE_PDFLATEX tag is set to YES, pdflatex will be used instead of -# plain latex in the generated Makefile. Set this option to YES to get a -# higher quality PDF documentation. - -USE_PDFLATEX = NO - -# If the LATEX_BATCHMODE tag is set to YES, doxygen will add the \\batchmode. -# command to the generated LaTeX files. This will instruct LaTeX to keep -# running if errors occur, instead of asking the user for help. -# This option is also used when generating formulas in HTML. - -LATEX_BATCHMODE = NO - -# If LATEX_HIDE_INDICES is set to YES then doxygen will not -# include the index chapters (such as File Index, Compound Index, etc.) -# in the output. - -LATEX_HIDE_INDICES = NO - -# If LATEX_SOURCE_CODE is set to YES then doxygen will include -# source code with syntax highlighting in the LaTeX output. -# Note that which sources are shown also depends on other settings -# such as SOURCE_BROWSER. - -LATEX_SOURCE_CODE = NO - -#--------------------------------------------------------------------------- -# configuration options related to the RTF output -#--------------------------------------------------------------------------- - -# If the GENERATE_RTF tag is set to YES Doxygen will generate RTF output -# The RTF output is optimized for Word 97 and may not look very pretty with -# other RTF readers or editors. - -GENERATE_RTF = NO - -# The RTF_OUTPUT tag is used to specify where the RTF docs will be put. -# If a relative path is entered the value of OUTPUT_DIRECTORY will be -# put in front of it. If left blank `rtf' will be used as the default path. - -RTF_OUTPUT = rtf - -# If the COMPACT_RTF tag is set to YES Doxygen generates more compact -# RTF documents. This may be useful for small projects and may help to -# save some trees in general. - -COMPACT_RTF = NO - -# If the RTF_HYPERLINKS tag is set to YES, the RTF that is generated -# will contain hyperlink fields. The RTF file will -# contain links (just like the HTML output) instead of page references. -# This makes the output suitable for online browsing using WORD or other -# programs which support those fields. -# Note: wordpad (write) and others do not support links. - -RTF_HYPERLINKS = NO - -# Load stylesheet definitions from file. Syntax is similar to doxygen's -# config file, i.e. a series of assignments. You only have to provide -# replacements, missing definitions are set to their default value. - -RTF_STYLESHEET_FILE = - -# Set optional variables used in the generation of an rtf document. -# Syntax is similar to doxygen's config file. - -RTF_EXTENSIONS_FILE = - -#--------------------------------------------------------------------------- -# configuration options related to the man page output -#--------------------------------------------------------------------------- - -# If the GENERATE_MAN tag is set to YES (the default) Doxygen will -# generate man pages - -GENERATE_MAN = NO - -# The MAN_OUTPUT tag is used to specify where the man pages will be put. -# If a relative path is entered the value of OUTPUT_DIRECTORY will be -# put in front of it. If left blank `man' will be used as the default path. - -MAN_OUTPUT = man - -# The MAN_EXTENSION tag determines the extension that is added to -# the generated man pages (default is the subroutine's section .3) - -MAN_EXTENSION = .3 - -# If the MAN_LINKS tag is set to YES and Doxygen generates man output, -# then it will generate one additional man file for each entity -# documented in the real man page(s). These additional files -# only source the real man page, but without them the man command -# would be unable to find the correct page. The default is NO. - -MAN_LINKS = NO - -#--------------------------------------------------------------------------- -# configuration options related to the XML output -#--------------------------------------------------------------------------- - -# If the GENERATE_XML tag is set to YES Doxygen will -# generate an XML file that captures the structure of -# the code including all documentation. - -GENERATE_XML = NO - -# The XML_OUTPUT tag is used to specify where the XML pages will be put. -# If a relative path is entered the value of OUTPUT_DIRECTORY will be -# put in front of it. If left blank `xml' will be used as the default path. - -XML_OUTPUT = xml - -# The XML_SCHEMA tag can be used to specify an XML schema, -# which can be used by a validating XML parser to check the -# syntax of the XML files. - -XML_SCHEMA = - -# The XML_DTD tag can be used to specify an XML DTD, -# which can be used by a validating XML parser to check the -# syntax of the XML files. - -XML_DTD = - -# If the XML_PROGRAMLISTING tag is set to YES Doxygen will -# dump the program listings (including syntax highlighting -# and cross-referencing information) to the XML output. Note that -# enabling this will significantly increase the size of the XML output. - -XML_PROGRAMLISTING = YES - -#--------------------------------------------------------------------------- -# configuration options for the AutoGen Definitions output -#--------------------------------------------------------------------------- - -# If the GENERATE_AUTOGEN_DEF tag is set to YES Doxygen will -# generate an AutoGen Definitions (see autogen.sf.net) file -# that captures the structure of the code including all -# documentation. Note that this feature is still experimental -# and incomplete at the moment. - -GENERATE_AUTOGEN_DEF = NO - -#--------------------------------------------------------------------------- -# configuration options related to the Perl module output -#--------------------------------------------------------------------------- - -# If the GENERATE_PERLMOD tag is set to YES Doxygen will -# generate a Perl module file that captures the structure of -# the code including all documentation. Note that this -# feature is still experimental and incomplete at the -# moment. - -GENERATE_PERLMOD = NO - -# If the PERLMOD_LATEX tag is set to YES Doxygen will generate -# the necessary Makefile rules, Perl scripts and LaTeX code to be able -# to generate PDF and DVI output from the Perl module output. - -PERLMOD_LATEX = NO - -# If the PERLMOD_PRETTY tag is set to YES the Perl module output will be -# nicely formatted so it can be parsed by a human reader. -# This is useful -# if you want to understand what is going on. -# On the other hand, if this -# tag is set to NO the size of the Perl module output will be much smaller -# and Perl will parse it just the same. - -PERLMOD_PRETTY = YES - -# The names of the make variables in the generated doxyrules.make file -# are prefixed with the string contained in PERLMOD_MAKEVAR_PREFIX. -# This is useful so different doxyrules.make files included by the same -# Makefile don't overwrite each other's variables. - -PERLMOD_MAKEVAR_PREFIX = - -#--------------------------------------------------------------------------- -# Configuration options related to the preprocessor -#--------------------------------------------------------------------------- - -# If the ENABLE_PREPROCESSING tag is set to YES (the default) Doxygen will -# evaluate all C-preprocessor directives found in the sources and include -# files. - -ENABLE_PREPROCESSING = YES - -# If the MACRO_EXPANSION tag is set to YES Doxygen will expand all macro -# names in the source code. If set to NO (the default) only conditional -# compilation will be performed. Macro expansion can be done in a controlled -# way by setting EXPAND_ONLY_PREDEF to YES. - -MACRO_EXPANSION = NO - -# If the EXPAND_ONLY_PREDEF and MACRO_EXPANSION tags are both set to YES -# then the macro expansion is limited to the macros specified with the -# PREDEFINED and EXPAND_AS_DEFINED tags. - -EXPAND_ONLY_PREDEF = NO - -# If the SEARCH_INCLUDES tag is set to YES (the default) the includes files -# in the INCLUDE_PATH (see below) will be search if a #include is found. - -SEARCH_INCLUDES = YES - -# The INCLUDE_PATH tag can be used to specify one or more directories that -# contain include files that are not input files but should be processed by -# the preprocessor. - -INCLUDE_PATH = - -# You can use the INCLUDE_FILE_PATTERNS tag to specify one or more wildcard -# patterns (like *.h and *.hpp) to filter out the header-files in the -# directories. If left blank, the patterns specified with FILE_PATTERNS will -# be used. - -INCLUDE_FILE_PATTERNS = - -# The PREDEFINED tag can be used to specify one or more macro names that -# are defined before the preprocessor is started (similar to the -D option of -# gcc). The argument of the tag is a list of macros of the form: name -# or name=definition (no spaces). If the definition and the = are -# omitted =1 is assumed. To prevent a macro definition from being -# undefined via #undef or recursively expanded use the := operator -# instead of the = operator. - -PREDEFINED = - -# If the MACRO_EXPANSION and EXPAND_ONLY_PREDEF tags are set to YES then -# this tag can be used to specify a list of macro names that should be expanded. -# The macro definition that is found in the sources will be used. -# Use the PREDEFINED tag if you want to use a different macro definition. - -EXPAND_AS_DEFINED = - -# If the SKIP_FUNCTION_MACROS tag is set to YES (the default) then -# doxygen's preprocessor will remove all function-like macros that are alone -# on a line, have an all uppercase name, and do not end with a semicolon. Such -# function macros are typically used for boiler-plate code, and will confuse -# the parser if not removed. - -SKIP_FUNCTION_MACROS = YES - -#--------------------------------------------------------------------------- -# Configuration::additions related to external references -#--------------------------------------------------------------------------- - -# The TAGFILES option can be used to specify one or more tagfiles. -# Optionally an initial location of the external documentation -# can be added for each tagfile. The format of a tag file without -# this location is as follows: -# -# TAGFILES = file1 file2 ... -# Adding location for the tag files is done as follows: -# -# TAGFILES = file1=loc1 "file2 = loc2" ... -# where "loc1" and "loc2" can be relative or absolute paths or -# URLs. If a location is present for each tag, the installdox tool -# does not have to be run to correct the links. -# Note that each tag file must have a unique name -# (where the name does NOT include the path) -# If a tag file is not located in the directory in which doxygen -# is run, you must also specify the path to the tagfile here. - -TAGFILES = - -# When a file name is specified after GENERATE_TAGFILE, doxygen will create -# a tag file that is based on the input files it reads. - -GENERATE_TAGFILE = - -# If the ALLEXTERNALS tag is set to YES all external classes will be listed -# in the class index. If set to NO only the inherited external classes -# will be listed. - -ALLEXTERNALS = NO - -# If the EXTERNAL_GROUPS tag is set to YES all external groups will be listed -# in the modules index. If set to NO, only the current project's groups will -# be listed. - -EXTERNAL_GROUPS = YES - -# The PERL_PATH should be the absolute path and name of the perl script -# interpreter (i.e. the result of `which perl'). - -PERL_PATH = /usr/bin/perl - -#--------------------------------------------------------------------------- -# Configuration options related to the dot tool -#--------------------------------------------------------------------------- - -# If the CLASS_DIAGRAMS tag is set to YES (the default) Doxygen will -# generate a inheritance diagram (in HTML, RTF and LaTeX) for classes with base -# or super classes. Setting the tag to NO turns the diagrams off. Note that -# this option is superseded by the HAVE_DOT option below. This is only a -# fallback. It is recommended to install and use dot, since it yields more -# powerful graphs. - -CLASS_DIAGRAMS = YES - -# You can define message sequence charts within doxygen comments using the \msc -# command. Doxygen will then run the mscgen tool (see -# http://www.mcternan.me.uk/mscgen/) to produce the chart and insert it in the -# documentation. The MSCGEN_PATH tag allows you to specify the directory where -# the mscgen tool resides. If left empty the tool is assumed to be found in the -# default search path. - -MSCGEN_PATH = - -# If set to YES, the inheritance and collaboration graphs will hide -# inheritance and usage relations if the target is undocumented -# or is not a class. - -HIDE_UNDOC_RELATIONS = NO - -# If you set the HAVE_DOT tag to YES then doxygen will assume the dot tool is -# available from the path. This tool is part of Graphviz, a graph visualization -# toolkit from AT&T and Lucent Bell Labs. The other options in this section -# have no effect if this option is set to NO (the default) - -HAVE_DOT = YES - -# The DOT_NUM_THREADS specifies the number of dot invocations doxygen is -# allowed to run in parallel. When set to 0 (the default) doxygen will -# base this on the number of processors available in the system. You can set it -# explicitly to a value larger than 0 to get control over the balance -# between CPU load and processing speed. - -DOT_NUM_THREADS = 0 - -# By default doxygen will write a font called FreeSans.ttf to the output -# directory and reference it in all dot files that doxygen generates. This -# font does not include all possible unicode characters however, so when you need -# these (or just want a differently looking font) you can specify the font name -# using DOT_FONTNAME. You need need to make sure dot is able to find the font, -# which can be done by putting it in a standard location or by setting the -# DOTFONTPATH environment variable or by setting DOT_FONTPATH to the directory -# containing the font. - -DOT_FONTNAME = FreeSans - -# The DOT_FONTSIZE tag can be used to set the size of the font of dot graphs. -# The default size is 10pt. - -DOT_FONTSIZE = 10 - -# By default doxygen will tell dot to use the output directory to look for the -# FreeSans.ttf font (which doxygen will put there itself). If you specify a -# different font using DOT_FONTNAME you can set the path where dot -# can find it using this tag. - -DOT_FONTPATH = - -# If the CLASS_GRAPH and HAVE_DOT tags are set to YES then doxygen -# will generate a graph for each documented class showing the direct and -# indirect inheritance relations. Setting this tag to YES will force the -# the CLASS_DIAGRAMS tag to NO. - -CLASS_GRAPH = YES - -# If the COLLABORATION_GRAPH and HAVE_DOT tags are set to YES then doxygen -# will generate a graph for each documented class showing the direct and -# indirect implementation dependencies (inheritance, containment, and -# class references variables) of the class with other documented classes. - -COLLABORATION_GRAPH = YES - -# If the GROUP_GRAPHS and HAVE_DOT tags are set to YES then doxygen -# will generate a graph for groups, showing the direct groups dependencies - -GROUP_GRAPHS = YES - -# If the UML_LOOK tag is set to YES doxygen will generate inheritance and -# collaboration diagrams in a style similar to the OMG's Unified Modeling -# Language. - -UML_LOOK = YES - -# If set to YES, the inheritance and collaboration graphs will show the -# relations between templates and their instances. - -TEMPLATE_RELATIONS = NO - -# If the ENABLE_PREPROCESSING, SEARCH_INCLUDES, INCLUDE_GRAPH, and HAVE_DOT -# tags are set to YES then doxygen will generate a graph for each documented -# file showing the direct and indirect include dependencies of the file with -# other documented files. - -INCLUDE_GRAPH = YES - -# If the ENABLE_PREPROCESSING, SEARCH_INCLUDES, INCLUDED_BY_GRAPH, and -# HAVE_DOT tags are set to YES then doxygen will generate a graph for each -# documented header file showing the documented files that directly or -# indirectly include this file. - -INCLUDED_BY_GRAPH = YES - -# If the CALL_GRAPH and HAVE_DOT options are set to YES then -# doxygen will generate a call dependency graph for every global function -# or class method. Note that enabling this option will significantly increase -# the time of a run. So in most cases it will be better to enable call graphs -# for selected functions only using the \callgraph command. - -CALL_GRAPH = YES - -# If the CALLER_GRAPH and HAVE_DOT tags are set to YES then -# doxygen will generate a caller dependency graph for every global function -# or class method. Note that enabling this option will significantly increase -# the time of a run. So in most cases it will be better to enable caller -# graphs for selected functions only using the \callergraph command. - -CALLER_GRAPH = YES - -# If the GRAPHICAL_HIERARCHY and HAVE_DOT tags are set to YES then doxygen -# will graphical hierarchy of all classes instead of a textual one. - -GRAPHICAL_HIERARCHY = YES - -# If the DIRECTORY_GRAPH, SHOW_DIRECTORIES and HAVE_DOT tags are set to YES -# then doxygen will show the dependencies a directory has on other directories -# in a graphical way. The dependency relations are determined by the #include -# relations between the files in the directories. - -DIRECTORY_GRAPH = YES - -# The DOT_IMAGE_FORMAT tag can be used to set the image format of the images -# generated by dot. Possible values are png, jpg, or gif -# If left blank png will be used. - -DOT_IMAGE_FORMAT = png - -# The tag DOT_PATH can be used to specify the path where the dot tool can be -# found. If left blank, it is assumed the dot tool can be found in the path. - -DOT_PATH = - -# The DOTFILE_DIRS tag can be used to specify one or more directories that -# contain dot files that are included in the documentation (see the -# \dotfile command). - -DOTFILE_DIRS = - -# The DOT_GRAPH_MAX_NODES tag can be used to set the maximum number of -# nodes that will be shown in the graph. If the number of nodes in a graph -# becomes larger than this value, doxygen will truncate the graph, which is -# visualized by representing a node as a red box. Note that doxygen if the -# number of direct children of the root node in a graph is already larger than -# DOT_GRAPH_MAX_NODES then the graph will not be shown at all. Also note -# that the size of a graph can be further restricted by MAX_DOT_GRAPH_DEPTH. - -DOT_GRAPH_MAX_NODES = 50 - -# The MAX_DOT_GRAPH_DEPTH tag can be used to set the maximum depth of the -# graphs generated by dot. A depth value of 3 means that only nodes reachable -# from the root by following a path via at most 3 edges will be shown. Nodes -# that lay further from the root node will be omitted. Note that setting this -# option to 1 or 2 may greatly reduce the computation time needed for large -# code bases. Also note that the size of a graph can be further restricted by -# DOT_GRAPH_MAX_NODES. Using a depth of 0 means no depth restriction. - -MAX_DOT_GRAPH_DEPTH = 0 - -# Set the DOT_TRANSPARENT tag to YES to generate images with a transparent -# background. This is disabled by default, because dot on Windows does not -# seem to support this out of the box. Warning: Depending on the platform used, -# enabling this option may lead to badly anti-aliased labels on the edges of -# a graph (i.e. they become hard to read). - -DOT_TRANSPARENT = NO - -# Set the DOT_MULTI_TARGETS tag to YES allow dot to generate multiple output -# files in one run (i.e. multiple -o and -T options on the command line). This -# makes dot run faster, but since only newer versions of dot (>1.8.10) -# support this, this feature is disabled by default. - -DOT_MULTI_TARGETS = YES - -# If the GENERATE_LEGEND tag is set to YES (the default) Doxygen will -# generate a legend page explaining the meaning of the various boxes and -# arrows in the dot generated graphs. - -GENERATE_LEGEND = YES - -# If the DOT_CLEANUP tag is set to YES (the default) Doxygen will -# remove the intermediate dot files that are used to generate -# the various graphs. - -DOT_CLEANUP = YES diff --git a/payloads/bayou/Makefile b/payloads/bayou/Makefile deleted file mode 100644 index 7a4b08b484..0000000000 --- a/payloads/bayou/Makefile +++ /dev/null @@ -1,67 +0,0 @@ -## -## This file is part of the bayou project. -## -## Copyright (C) 2008 Advanced Micro Devices, Inc. -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License version 2 as -## published by the Free Software Foundation. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## - -CONFIG_LZMA=y -CONFIG_NRV2B=y -CONFIG_BUILTIN_LAR=y - -PBUILDER_CONFIG=bayou.xml -BUILTIN_LAR=builtin.lar - -export src := $(CURDIR) -export obj := $(src)/build - -LIBPAYLOAD_DIR := $(obj)/libpayload - -CC?=gcc -STRIP?=strip -OBJCOPY?=objcopy - -FFLAGS-y= -FFLAGS-$(CONFIG_BUILTIN_LAR) += -DCONFIG_BUILTIN_LAR -FFLAGS-$(CONFIG_LZMA) += -DCONFIG_LZMA -FFLAGS-$(CONFIG_NRV2B) += -DCONFIG_NRV2B - -OBJECTS-y=main.o payload.o config.o menu.o self.o -OBJECTS-$(CONFIG_LZMA) += lzma.o -OBJECTS-$(CONFIG_NRV2B) += nrv2b.o -OBJECTS-$(CONFIG_BUILTIN_LAR) += builtin-lar.o - -CFLAGS= -Wall -Werror -Os $(FFLAGS-y) -LDFLAGS=-Wl,-T,bayou.ldscript -static -LIBGCC=$(shell $(CC) -m32 -print-libgcc-file-name) - -LPCC=$(LIBPAYLOAD_DIR)/bin/lpgcc - -bayou.elf: $(OBJECTS-y) - $(LPCC) $(LDFLAGS) -m32 -o $@ $(OBJECTS-y) - @$(STRIP) $@ - -builtin-lar.o: $(BUILTIN_LAR) - @$(OBJCOPY) -I binary -B i386 -O elf32-i386 $(BUILTIN_LAR) $@ - -builtin.lar: util/pbuilder/pbuilder - @rm -f $@ - util/pbuilder/pbuilder -c $(PBUILDER_CONFIG) create $@ - -util/pbuilder/pbuilder: - $(MAKE) -C util/pbuilder - -%.o: %.c - $(LPCC) $(CFLAGS) -c -o $@ $< - -clean: - rm -f *.o bayou.elf builtin.lar - $(MAKE) -C util/pbuilder clean diff --git a/payloads/bayou/bayou.h b/payloads/bayou/bayou.h deleted file mode 100644 index 6bf10a5a70..0000000000 --- a/payloads/bayou/bayou.h +++ /dev/null @@ -1,83 +0,0 @@ -/* - * This file is part of the bayou project. - * - * Copyright (C) 2008 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef BAYOU_H_ -#define BAYOU_H_ - -#include - -#define BAYOU_MAX_ENTRIES 10 - -struct bpt_config { - u32 id; - u8 timeout; - u8 entries; - u8 padding[10]; -}; - -struct bpt_pentry { - u8 index; - u8 parent; - u8 type; - u8 flags; - u8 title[64]; - u8 nlen; -}; - -#define BPT_ID 0x30545042 -#define BPT_TYPE_CHOOSER 0x01 -#define BPT_TYPE_CHAIN 0x02 -#define BPT_TYPE_SUBCHAIN 0x03 - -#define BPT_FLAG_DEFAULT 0x01 -#define BPT_FLAG_NOSHOW 0x02 - -enum bayou_params { - BAYOU_PARAM_NAME = 0, - BAYOU_PARAM_LIST, - BAYOU_PARAM_DESC, - BAYOU_PARAMS_COUNT -}; - -struct payload { - struct bpt_pentry pentry; - struct larstat stat; - u8 *fptr; - char *params[BAYOU_PARAMS_COUNT]; -}; - -struct bayoucfg { - u8 timeout; - int n_entries; - struct payload entries[BAYOU_MAX_ENTRIES]; -}; - -extern struct bayoucfg bayoucfg; - -int verify_self(u8 *ptr); -int self_get_params(u8 *fptr, u8 **params); -int self_load_and_run(struct payload *p, int *ret); - -void menu(void); - -void run_payload(struct payload *p); -char *payload_get_name(struct payload *p); -struct payload *payload_get_default(void); -void run_payload_timeout(struct payload *p, int timeout); -void payload_parse_params(struct payload *pload, u8 *params, int len); - -int get_configuration(struct LAR *lar); - -#endif diff --git a/payloads/bayou/bayou.ldscript b/payloads/bayou/bayou.ldscript deleted file mode 100644 index 86baaecb2e..0000000000 --- a/payloads/bayou/bayou.ldscript +++ /dev/null @@ -1,87 +0,0 @@ -/* - * This file is part of the bayou project. - * - * Copyright (C) 2008 Advanced Micro Devices, Inc. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. - */ - -BASE_ADDRESS = 0x19000; - -OUTPUT_FORMAT(elf32-i386) -OUTPUT_ARCH(i386) - -ENTRY(_entry) - -HEAP_SIZE = 16384; -STACK_SIZE = 16384; - -SECTIONS -{ - . = BASE_ADDRESS; - - . = ALIGN(16); - _start = .; - - .text : { - *(.text._entry) - *(.text) - *(.text.*) - } - - .rodata : { - *(.rodata) - *(.rodata.*) - } - - .data : { - *(.data) - *(.data.*) - } - - _edata = .; - - .bss : { - *(.bss) - *(.bss.*) - *(COMMON) - - /* Stack and heap */ - - . = ALIGN(16); - _heap = .; - . += HEAP_SIZE; - . = ALIGN(16); - _eheap = .; - - _estack = .; - . += STACK_SIZE; - . = ALIGN(16); - _stack = .; - } - - _end = .; - - /DISCARD/ : { *(.comment) *(.note) *(.note.*) } -} diff --git a/payloads/bayou/bayou.xml.example b/payloads/bayou/bayou.xml.example deleted file mode 100644 index c52eaf22e1..0000000000 --- a/payloads/bayou/bayou.xml.example +++ /dev/null @@ -1,37 +0,0 @@ - - - - - - - 10 - - - - Default Chain - - payloads/passwd.elf - passwd - - - payloads/coreinfo.elf - - - - payloads/coreinfo.elf - - - diff --git a/payloads/bayou/config.c b/payloads/bayou/config.c deleted file mode 100644 index ad315c8fda..0000000000 --- a/payloads/bayou/config.c +++ /dev/null @@ -1,161 +0,0 @@ -/* - * This file is part of the bayou project. - * - * Copyright (C) 2008 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include "bayou.h" - -struct bayoucfg bayoucfg; - -static int add_payload(struct LAR *lar, struct larent *larent) -{ - struct payload *payload; - int plen; - u8 *params = NULL; - u8 *fptr; - - if (bayoucfg.n_entries == BAYOU_MAX_ENTRIES) - return -1; - - payload = &bayoucfg.entries[bayoucfg.n_entries]; - - if (strncmp((char *)larent->name, "payload/", 8)) - return -1; - - if (larstat(lar, (const char *)larent->name, &payload->stat)) - return -1; - - /* Make sure the LAR entry is valid. */ - if (!lfverify(lar, (const char *)larent->name)) - return -1; - - /* Get a pointer to the start of the file. */ - fptr = larfptr(lar, (const char *)larent->name); - - if (fptr == NULL) - return -1; - - if (!verify_self(fptr)) - return -1; - - payload->pentry.index = bayoucfg.n_entries; - payload->pentry.parent = 0; - payload->pentry.type = BPT_TYPE_CHOOSER; - payload->pentry.flags = 0; - - plen = self_get_params(fptr, ¶ms); - payload_parse_params(payload, params, plen); - - payload->fptr = fptr; - - bayoucfg.n_entries++; - - return 0; -} - -static int lar_walk_files(struct LAR *lar, - int (*cb) (struct LAR *, struct larent *)) -{ - struct larent *larent; - int ret = 0; - - rewindlar(lar); - - while ((larent = readlar(lar)) != NULL) { - if ((ret = cb(lar, larent))) - break; - } - - return ret; -} - -/** - * If reading the bayou_payload_table fails for some reason, then construct - * a dummy table. All valid payloads in the lar are added as chooser items. - */ -static void build_dummy_table(struct LAR *lar) -{ - bayoucfg.timeout = 0xFF; - bayoucfg.n_entries = 0; - - lar_walk_files(lar, add_payload); -} - -int get_configuration(struct LAR *lar) -{ - struct larstat stat; - struct bpt_config *bptcfg; - u8 *fptr, *ptr; - int i; - - /* - * If bayou_payload_table doesn't exist, then dummy up - * a table from the LAR contents. - */ - if (larstat(lar, "bayou_payload_table", &stat) || - !lfverify(lar, "bayou_payload_table")) - build_dummy_table(lar); - - /* Open up the BPT and get the creamy goodness within. */ - - fptr = larfptr(lar, "bayou_payload_table"); - - if (fptr == NULL) - build_dummy_table(lar); - - bptcfg = (struct bpt_config *)fptr; - bayoucfg.timeout = bptcfg->timeout; - - bayoucfg.n_entries = bptcfg->entries; - - if (bayoucfg.n_entries > BAYOU_MAX_ENTRIES) { - printf("W: Limiting the number of entries to %d\n", - BAYOU_MAX_ENTRIES); - bayoucfg.n_entries = BAYOU_MAX_ENTRIES; - } - - ptr = fptr + sizeof(struct bpt_config); - - for (i = 0; i < bayoucfg.n_entries; i++) { - struct bpt_pentry *entry = (struct bpt_pentry *)ptr; - struct payload *p = &(bayoucfg.entries[i]); - int plen; - u8 *params = NULL; - - memcpy(&p->pentry, entry, sizeof(struct bpt_pentry)); - - if (entry->type != BPT_TYPE_CHAIN) { - char *lname = (char *)ptr + sizeof(struct bpt_pentry); - - if (larstat(lar, (const char *)lname, &p->stat)) - build_dummy_table(lar); - - if (!lfverify(lar, (const char *)lname)) - build_dummy_table(lar); - - fptr = larfptr(lar, (const char *)lname); - - if (verify_self(fptr)) - p->fptr = fptr; - else - build_dummy_table(lar); - - plen = self_get_params(fptr, ¶ms); - payload_parse_params(p, params, plen); - } - - ptr += sizeof(struct bpt_pentry) + entry->nlen; - } - - return 0; -} diff --git a/payloads/bayou/lzma.c b/payloads/bayou/lzma.c deleted file mode 100644 index 14bd921527..0000000000 --- a/payloads/bayou/lzma.c +++ /dev/null @@ -1,43 +0,0 @@ -/* - -coreboot interface to memory-saving variant of LZMA decoder - -(C)opyright 2006 Carl-Daniel Hailfinger -Released under the GNU GPL v2 or later - -Parts of this file are based on C/7zip/Compress/LZMA_C/LzmaTest.c from the LZMA -SDK 4.42, which is written and distributed to public domain by Igor Pavlov. - -*/ - -#include -#include "lzmadecode.c" - -unsigned long ulzma(u8 *src, u8 *dst) -{ - unsigned char properties[LZMA_PROPERTIES_SIZE]; - UInt32 outSize; - SizeT inProcessed; - SizeT outProcessed; - int res; - CLzmaDecoderState state; - SizeT mallocneeds; - unsigned char scratchpad[15980]; - - memcpy(properties, src, LZMA_PROPERTIES_SIZE); - outSize = *(UInt32 *)(src + LZMA_PROPERTIES_SIZE); - if (LzmaDecodeProperties(&state.Properties, properties, LZMA_PROPERTIES_SIZE) != LZMA_RESULT_OK) { - printf("Incorrect stream properties\n"); - } - mallocneeds = (LzmaGetNumProbs(&state.Properties) * sizeof(CProb)); - if (mallocneeds > 15980) { - printf("Decoder scratchpad too small!\n"); - } - state.Probs = (CProb *)scratchpad; - res = LzmaDecode(&state, src + LZMA_PROPERTIES_SIZE + 8, (SizeT)0xffffffff, &inProcessed, - dst, outSize, &outProcessed); - if (res != 0) { - printf("Decoding error = %d\n", res); - } - return outSize; -} diff --git a/payloads/bayou/lzmadecode.c b/payloads/bayou/lzmadecode.c deleted file mode 100644 index b03415f35e..0000000000 --- a/payloads/bayou/lzmadecode.c +++ /dev/null @@ -1,398 +0,0 @@ -/* - LzmaDecode.c - LZMA Decoder (optimized for Speed version) - - LZMA SDK 4.40 Copyright (c) 1999-2006 Igor Pavlov (2006-05-01) - http://www.7-zip.org/ - - LZMA SDK is licensed under two licenses: - 1) GNU Lesser General Public License (GNU LGPL) - 2) Common Public License (CPL) - It means that you can select one of these two licenses and - follow rules of that license. - - SPECIAL EXCEPTION: - Igor Pavlov, as the author of this Code, expressly permits you to - statically or dynamically link your Code (or bind by name) to the - interfaces of this file without subjecting your linked Code to the - terms of the CPL or GNU LGPL. Any modifications or additions - to this file, however, are subject to the LGPL or CPL terms. -*/ - -#include "lzmadecode.h" - -#define kNumTopBits 24 -#define kTopValue ((UInt32)1 << kNumTopBits) - -#define kNumBitModelTotalBits 11 -#define kBitModelTotal (1 << kNumBitModelTotalBits) -#define kNumMoveBits 5 - -#define RC_READ_BYTE (*Buffer++) - -#define RC_INIT2 Code = 0; Range = 0xFFFFFFFF; \ - { int i; for(i = 0; i < 5; i++) { RC_TEST; Code = (Code << 8) | RC_READ_BYTE; }} - - -#define RC_TEST { if (Buffer == BufferLim) return LZMA_RESULT_DATA_ERROR; } - -#define RC_INIT(buffer, bufferSize) Buffer = buffer; BufferLim = buffer + bufferSize; RC_INIT2 - - -#define RC_NORMALIZE if (Range < kTopValue) { RC_TEST; Range <<= 8; Code = (Code << 8) | RC_READ_BYTE; } - -#define IfBit0(p) RC_NORMALIZE; bound = (Range >> kNumBitModelTotalBits) * *(p); if (Code < bound) -#define UpdateBit0(p) Range = bound; *(p) += (kBitModelTotal - *(p)) >> kNumMoveBits; -#define UpdateBit1(p) Range -= bound; Code -= bound; *(p) -= (*(p)) >> kNumMoveBits; - -#define RC_GET_BIT2(p, mi, A0, A1) IfBit0(p) \ - { UpdateBit0(p); mi <<= 1; A0; } else \ - { UpdateBit1(p); mi = (mi + mi) + 1; A1; } - -#define RC_GET_BIT(p, mi) RC_GET_BIT2(p, mi, ; , ;) - -#define RangeDecoderBitTreeDecode(probs, numLevels, res) \ - { int i = numLevels; res = 1; \ - do { CProb *p = probs + res; RC_GET_BIT(p, res) } while(--i != 0); \ - res -= (1 << numLevels); } - - -#define kNumPosBitsMax 4 -#define kNumPosStatesMax (1 << kNumPosBitsMax) - -#define kLenNumLowBits 3 -#define kLenNumLowSymbols (1 << kLenNumLowBits) -#define kLenNumMidBits 3 -#define kLenNumMidSymbols (1 << kLenNumMidBits) -#define kLenNumHighBits 8 -#define kLenNumHighSymbols (1 << kLenNumHighBits) - -#define LenChoice 0 -#define LenChoice2 (LenChoice + 1) -#define LenLow (LenChoice2 + 1) -#define LenMid (LenLow + (kNumPosStatesMax << kLenNumLowBits)) -#define LenHigh (LenMid + (kNumPosStatesMax << kLenNumMidBits)) -#define kNumLenProbs (LenHigh + kLenNumHighSymbols) - - -#define kNumStates 12 -#define kNumLitStates 7 - -#define kStartPosModelIndex 4 -#define kEndPosModelIndex 14 -#define kNumFullDistances (1 << (kEndPosModelIndex >> 1)) - -#define kNumPosSlotBits 6 -#define kNumLenToPosStates 4 - -#define kNumAlignBits 4 -#define kAlignTableSize (1 << kNumAlignBits) - -#define kMatchMinLen 2 - -#define IsMatch 0 -#define IsRep (IsMatch + (kNumStates << kNumPosBitsMax)) -#define IsRepG0 (IsRep + kNumStates) -#define IsRepG1 (IsRepG0 + kNumStates) -#define IsRepG2 (IsRepG1 + kNumStates) -#define IsRep0Long (IsRepG2 + kNumStates) -#define PosSlot (IsRep0Long + (kNumStates << kNumPosBitsMax)) -#define SpecPos (PosSlot + (kNumLenToPosStates << kNumPosSlotBits)) -#define Align (SpecPos + kNumFullDistances - kEndPosModelIndex) -#define LenCoder (Align + kAlignTableSize) -#define RepLenCoder (LenCoder + kNumLenProbs) -#define Literal (RepLenCoder + kNumLenProbs) - -#if Literal != LZMA_BASE_SIZE -StopCompilingDueBUG -#endif - -int LzmaDecodeProperties(CLzmaProperties *propsRes, const unsigned char *propsData, int size) -{ - unsigned char prop0; - if (size < LZMA_PROPERTIES_SIZE) - return LZMA_RESULT_DATA_ERROR; - prop0 = propsData[0]; - if (prop0 >= (9 * 5 * 5)) - return LZMA_RESULT_DATA_ERROR; - { - for (propsRes->pb = 0; prop0 >= (9 * 5); propsRes->pb++, prop0 -= (9 * 5)); - for (propsRes->lp = 0; prop0 >= 9; propsRes->lp++, prop0 -= 9); - propsRes->lc = prop0; - /* - unsigned char remainder = (unsigned char)(prop0 / 9); - propsRes->lc = prop0 % 9; - propsRes->pb = remainder / 5; - propsRes->lp = remainder % 5; - */ - } - - return LZMA_RESULT_OK; -} - -#define kLzmaStreamWasFinishedId (-1) - -int LzmaDecode(CLzmaDecoderState *vs, - const unsigned char *inStream, SizeT inSize, SizeT *inSizeProcessed, - unsigned char *outStream, SizeT outSize, SizeT *outSizeProcessed) -{ - CProb *p = vs->Probs; - SizeT nowPos = 0; - Byte previousByte = 0; - UInt32 posStateMask = (1 << (vs->Properties.pb)) - 1; - UInt32 literalPosMask = (1 << (vs->Properties.lp)) - 1; - int lc = vs->Properties.lc; - - - int state = 0; - UInt32 rep0 = 1, rep1 = 1, rep2 = 1, rep3 = 1; - int len = 0; - const Byte *Buffer; - const Byte *BufferLim; - UInt32 Range; - UInt32 Code; - - *inSizeProcessed = 0; - *outSizeProcessed = 0; - - { - UInt32 i; - UInt32 numProbs = Literal + ((UInt32)LZMA_LIT_SIZE << (lc + vs->Properties.lp)); - for (i = 0; i < numProbs; i++) - p[i] = kBitModelTotal >> 1; - } - - RC_INIT(inStream, inSize); - - - while(nowPos < outSize) - { - CProb *prob; - UInt32 bound; - int posState = (int)( - (nowPos - ) - & posStateMask); - - prob = p + IsMatch + (state << kNumPosBitsMax) + posState; - IfBit0(prob) - { - int symbol = 1; - UpdateBit0(prob) - prob = p + Literal + (LZMA_LIT_SIZE * - ((( - (nowPos - ) - & literalPosMask) << lc) + (previousByte >> (8 - lc)))); - - if (state >= kNumLitStates) - { - int matchByte; - matchByte = outStream[nowPos - rep0]; - do - { - int bit; - CProb *probLit; - matchByte <<= 1; - bit = (matchByte & 0x100); - probLit = prob + 0x100 + bit + symbol; - RC_GET_BIT2(probLit, symbol, if (bit != 0) break, if (bit == 0) break) - } - while (symbol < 0x100); - } - while (symbol < 0x100) - { - CProb *probLit = prob + symbol; - RC_GET_BIT(probLit, symbol) - } - previousByte = (Byte)symbol; - - outStream[nowPos++] = previousByte; - if (state < 4) state = 0; - else if (state < 10) state -= 3; - else state -= 6; - } - else - { - UpdateBit1(prob); - prob = p + IsRep + state; - IfBit0(prob) - { - UpdateBit0(prob); - rep3 = rep2; - rep2 = rep1; - rep1 = rep0; - state = state < kNumLitStates ? 0 : 3; - prob = p + LenCoder; - } - else - { - UpdateBit1(prob); - prob = p + IsRepG0 + state; - IfBit0(prob) - { - UpdateBit0(prob); - prob = p + IsRep0Long + (state << kNumPosBitsMax) + posState; - IfBit0(prob) - { - UpdateBit0(prob); - - if (nowPos == 0) - return LZMA_RESULT_DATA_ERROR; - - state = state < kNumLitStates ? 9 : 11; - previousByte = outStream[nowPos - rep0]; - outStream[nowPos++] = previousByte; - - continue; - } - else - { - UpdateBit1(prob); - } - } - else - { - UInt32 distance; - UpdateBit1(prob); - prob = p + IsRepG1 + state; - IfBit0(prob) - { - UpdateBit0(prob); - distance = rep1; - } - else - { - UpdateBit1(prob); - prob = p + IsRepG2 + state; - IfBit0(prob) - { - UpdateBit0(prob); - distance = rep2; - } - else - { - UpdateBit1(prob); - distance = rep3; - rep3 = rep2; - } - rep2 = rep1; - } - rep1 = rep0; - rep0 = distance; - } - state = state < kNumLitStates ? 8 : 11; - prob = p + RepLenCoder; - } - { - int numBits, offset; - CProb *probLen = prob + LenChoice; - IfBit0(probLen) - { - UpdateBit0(probLen); - probLen = prob + LenLow + (posState << kLenNumLowBits); - offset = 0; - numBits = kLenNumLowBits; - } - else - { - UpdateBit1(probLen); - probLen = prob + LenChoice2; - IfBit0(probLen) - { - UpdateBit0(probLen); - probLen = prob + LenMid + (posState << kLenNumMidBits); - offset = kLenNumLowSymbols; - numBits = kLenNumMidBits; - } - else - { - UpdateBit1(probLen); - probLen = prob + LenHigh; - offset = kLenNumLowSymbols + kLenNumMidSymbols; - numBits = kLenNumHighBits; - } - } - RangeDecoderBitTreeDecode(probLen, numBits, len); - len += offset; - } - - if (state < 4) - { - int posSlot; - state += kNumLitStates; - prob = p + PosSlot + - ((len < kNumLenToPosStates ? len : kNumLenToPosStates - 1) << - kNumPosSlotBits); - RangeDecoderBitTreeDecode(prob, kNumPosSlotBits, posSlot); - if (posSlot >= kStartPosModelIndex) - { - int numDirectBits = ((posSlot >> 1) - 1); - rep0 = (2 | ((UInt32)posSlot & 1)); - if (posSlot < kEndPosModelIndex) - { - rep0 <<= numDirectBits; - prob = p + SpecPos + rep0 - posSlot - 1; - } - else - { - numDirectBits -= kNumAlignBits; - do - { - RC_NORMALIZE - Range >>= 1; - rep0 <<= 1; - if (Code >= Range) - { - Code -= Range; - rep0 |= 1; - } - } - while (--numDirectBits != 0); - prob = p + Align; - rep0 <<= kNumAlignBits; - numDirectBits = kNumAlignBits; - } - { - int i = 1; - int mi = 1; - do - { - CProb *prob3 = prob + mi; - RC_GET_BIT2(prob3, mi, ; , rep0 |= i); - i <<= 1; - } - while(--numDirectBits != 0); - } - } - else - rep0 = posSlot; - if (++rep0 == (UInt32)(0)) - { - /* it's for stream version */ - len = kLzmaStreamWasFinishedId; - break; - } - } - - len += kMatchMinLen; - if (rep0 > nowPos) - return LZMA_RESULT_DATA_ERROR; - - - do - { - previousByte = outStream[nowPos - rep0]; - len--; - outStream[nowPos++] = previousByte; - } - while(len != 0 && nowPos < outSize); - } - } - RC_NORMALIZE; - - - *inSizeProcessed = (SizeT)(Buffer - inStream); - *outSizeProcessed = nowPos; - return LZMA_RESULT_OK; -} diff --git a/payloads/bayou/lzmadecode.h b/payloads/bayou/lzmadecode.h deleted file mode 100644 index 37712455e9..0000000000 --- a/payloads/bayou/lzmadecode.h +++ /dev/null @@ -1,67 +0,0 @@ -/* - LzmaDecode.h - LZMA Decoder interface - - LZMA SDK 4.40 Copyright (c) 1999-2006 Igor Pavlov (2006-05-01) - http://www.7-zip.org/ - - LZMA SDK is licensed under two licenses: - 1) GNU Lesser General Public License (GNU LGPL) - 2) Common Public License (CPL) - It means that you can select one of these two licenses and - follow rules of that license. - - SPECIAL EXCEPTION: - Igor Pavlov, as the author of this code, expressly permits you to - statically or dynamically link your code (or bind by name) to the - interfaces of this file without subjecting your linked code to the - terms of the CPL or GNU LGPL. Any modifications or additions - to this file, however, are subject to the LGPL or CPL terms. -*/ - -#ifndef LZMADECODE_H -#define LZMADECODE_H - -typedef unsigned char Byte; -typedef unsigned short UInt16; -typedef unsigned int UInt32; -typedef UInt32 SizeT; - -#define CProb UInt16 - -#define LZMA_RESULT_OK 0 -#define LZMA_RESULT_DATA_ERROR 1 - - -#define LZMA_BASE_SIZE 1846 -#define LZMA_LIT_SIZE 768 - -#define LZMA_PROPERTIES_SIZE 5 - -typedef struct _CLzmaProperties -{ - int lc; - int lp; - int pb; -}CLzmaProperties; - -int LzmaDecodeProperties(CLzmaProperties *propsRes, const unsigned char *propsData, int size); - -#define LzmaGetNumProbs(Properties) (LZMA_BASE_SIZE + (LZMA_LIT_SIZE << ((Properties)->lc + (Properties)->lp))) - -#define kLzmaNeedInitId (-2) - -typedef struct _CLzmaDecoderState -{ - CLzmaProperties Properties; - CProb *Probs; - - -} CLzmaDecoderState; - - -int LzmaDecode(CLzmaDecoderState *vs, - const unsigned char *inStream, SizeT inSize, SizeT *inSizeProcessed, - unsigned char *outStream, SizeT outSize, SizeT *outSizeProcessed); - -#endif /* LZMADECODE_H */ diff --git a/payloads/bayou/main.c b/payloads/bayou/main.c deleted file mode 100644 index cdccea1072..0000000000 --- a/payloads/bayou/main.c +++ /dev/null @@ -1,66 +0,0 @@ -/* - * This file is part of the bayou project. - * - * Copyright (C) 2008 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include "bayou.h" - -static void print_banner(void) -{ - printf("\e[H\e[JBayou Payload Chooser v0.3\n"); -} - -int main(void) -{ - extern unsigned long _binary_builtin_lar_start; - struct LAR *lar; - - print_banner(); - - lar = openlar((void *)&_binary_builtin_lar_start); - - if (lar == NULL) { - printf("[CHOOSER]: Unable to scan the attached LAR file\n"); - return -1; - } - - get_configuration(lar); - - if (bayoucfg.n_entries == 0) { - printf("[CHOOSER]: No payloads were found in the LAR\n"); - return -1; - } - - /* - * If timeout == 0xFF, then show the menu immediately. - * If timeout is zero, then find and run the default item immediately. - * If there is no default item, then show the menu. - * If timeout is anything else, then show a message and wait for a - * keystroke. If there is no keystroke in time then run the default. - * If there is no default then show the menu. - */ - if (bayoucfg.timeout != 0xFF) { - struct payload *d = payload_get_default(); - - if (d != NULL) { - if (bayoucfg.timeout == 0) - run_payload(d); - else - run_payload_timeout(d, bayoucfg.timeout); - } - } - - menu(); - - return 0; -} diff --git a/payloads/bayou/menu.c b/payloads/bayou/menu.c deleted file mode 100644 index 0d312ca322..0000000000 --- a/payloads/bayou/menu.c +++ /dev/null @@ -1,152 +0,0 @@ -/* - * This file is part of the bayou project. - * - * Copyright (C) 2008 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include "bayou.h" - -#define SCREEN_X 80 -#define SCREEN_Y 25 - -static int menu_width = 0; -static struct payload *mpayloads[BAYOU_MAX_ENTRIES]; -static int m_entries = 0; -static unsigned int selected = 0; -static WINDOW *menuwin, *status; - -void create_menu(void) -{ - int i; - - for (i = 0; i < bayoucfg.n_entries; i++) { - struct payload *p = &(bayoucfg.entries[i]); - char *name; - - if ((p->pentry.parent != 0) || - (p->pentry.flags & BPT_FLAG_NOSHOW)) - continue; - - mpayloads[m_entries++] = p; - - name = payload_get_name(p); - - if (strlen(name) > menu_width) - menu_width = strlen(name); - } - - menu_width += 4; - - if (menu_width < 30) - menu_width = 30; - - menuwin = newwin(m_entries + 3, menu_width, - (SCREEN_Y - (m_entries + 3)) / 2, - (SCREEN_X - menu_width) / 2); -} - -void draw_menu(void) -{ - struct payload *s; - int i; - - wattrset(menuwin, COLOR_PAIR(3)); - wclear(menuwin); - wborder(menuwin, ACS_VLINE, ACS_VLINE, ACS_HLINE, ACS_HLINE, - ACS_ULCORNER, ACS_URCORNER, ACS_LLCORNER, ACS_LRCORNER); - - wattrset(menuwin, COLOR_PAIR(4) | A_BOLD); - mvwprintw(menuwin, 0, (menu_width - 17) / 2, " Payload Chooser "); - - wattrset(menuwin, COLOR_PAIR(3)); - - for (i = 0; i < m_entries; i++) { - char *name = payload_get_name(mpayloads[i]); - int col = (menu_width - (2 + strlen(name))) / 2; - - if (i == selected) - wattrset(menuwin, COLOR_PAIR(5) | A_BOLD); - else - wattrset(menuwin, COLOR_PAIR(3)); - - mvwprintw(menuwin, 2 + i, col, name); - } - - s = mpayloads[selected]; - - wclear(status); - - if (s->params[BAYOU_PARAM_DESC] != NULL) { - char buf[66]; - int len = strnlen(s->params[BAYOU_PARAM_DESC], 65); - - snprintf(buf, 65, s->params[BAYOU_PARAM_DESC]); - buf[65] = 0; - - mvwprintw(status, 0, (80 - len) / 2, buf); - } - - wrefresh(menuwin); - wrefresh(status); -} - -void loop(void) -{ - int key; - - while (1) { - key = getch(); - - if (key == ERR) - continue; - - if (key == KEY_DOWN) - selected = (selected + 1) % m_entries; - else if (key == KEY_UP) - selected = (selected - 1) % m_entries; - else if (key == KEY_ENTER) { - run_payload(mpayloads[selected]); - clear(); - refresh(); - } else - continue; - - draw_menu(); - } -} - -void menu(void) -{ - initscr(); - - init_pair(1, COLOR_WHITE, COLOR_RED); - init_pair(2, COLOR_BLACK, COLOR_WHITE); - init_pair(3, COLOR_BLACK, COLOR_WHITE); - init_pair(4, COLOR_CYAN, COLOR_WHITE); - init_pair(5, COLOR_WHITE, COLOR_RED); - - wattrset(stdscr, COLOR_PAIR(1)); - wclear(stdscr); - - status = newwin(1, 80, 24, 0); - wattrset(status, COLOR_PAIR(2)); - wclear(status); - - refresh(); - - create_menu(); - draw_menu(); - - loop(); -} diff --git a/payloads/bayou/nrv2b.c b/payloads/bayou/nrv2b.c deleted file mode 100644 index 53f79882f5..0000000000 --- a/payloads/bayou/nrv2b.c +++ /dev/null @@ -1,86 +0,0 @@ -#include - -// This GETBIT is supposed to work on little endian -// 32bit systems. The algorithm will definitely need -// some fixing on other systems, but it might not be -// a problem since the nrv2b binary behaves the same.. - -#ifndef ENDIAN -#define ENDIAN 0 -#endif -#ifndef BITSIZE -#define BITSIZE 32 -#endif - -#define GETBIT_8(bb, src, ilen) \ - (((bb = bb & 0x7f ? bb*2 : ((unsigned)src[ilen++]*2+1)) >> 8) & 1) - -#define GETBIT_LE16(bb, src, ilen) \ - (bb*=2,bb&0xffff ? (bb>>16)&1 : (ilen+=2,((bb=(src[ilen-2]+src[ilen-1]*256u)*2+1)>>16)&1)) -#define GETBIT_LE32(bb, src, ilen) \ - (bc > 0 ? ((bb>>--bc)&1) : (bc=31,\ - bb=*(const u32 *)((src)+ilen),ilen+=4,(bb>>31)&1)) - -#if ENDIAN == 0 && BITSIZE == 8 -#define GETBIT(bb, src, ilen) GETBIT_8(bb, src, ilen) -#endif -#if ENDIAN == 0 && BITSIZE == 16 -#define GETBIT(bb, src, ilen) GETBIT_LE16(bb, src, ilen) -#endif -#if ENDIAN == 0 && BITSIZE == 32 -#define GETBIT(bb, src, ilen) GETBIT_LE32(bb, src, ilen) -#endif - -unsigned long unrv2b(u8 *src, u8 *dst, unsigned long *ilen_p) -{ - unsigned long ilen = 0, olen = 0, last_m_off = 1; - u32 bb = 0; - unsigned bc = 0; - const u8 *m_pos; - - // skip length - src += 4; - /* FIXME: check olen with the length stored in first 4 bytes */ - - for (;;) { - unsigned int m_off, m_len; - while (GETBIT(bb, src, ilen)) { - dst[olen++] = src[ilen++]; - } - - m_off = 1; - do { - m_off = m_off * 2 + GETBIT(bb, src, ilen); - } while (!GETBIT(bb, src, ilen)); - if (m_off == 2) { - m_off = last_m_off; - } else { - m_off = (m_off - 3) * 256 + src[ilen++]; - if (m_off == 0xffffffffU) - break; - last_m_off = ++m_off; - } - - m_len = GETBIT(bb, src, ilen); - m_len = m_len * 2 + GETBIT(bb, src, ilen); - if (m_len == 0) { - m_len++; - do { - m_len = m_len * 2 + GETBIT(bb, src, ilen); - } while (!GETBIT(bb, src, ilen)); - m_len += 2; - } - m_len += (m_off > 0xd00); - - m_pos = dst + olen - m_off; - dst[olen++] = *m_pos++; - do { - dst[olen++] = *m_pos++; - } while (--m_len > 0); - } - - *ilen_p = ilen; - - return olen; - -} diff --git a/payloads/bayou/payload.c b/payloads/bayou/payload.c deleted file mode 100644 index a76e49ff6c..0000000000 --- a/payloads/bayou/payload.c +++ /dev/null @@ -1,107 +0,0 @@ -/* - * This file is part of the bayou project. - * - * Copyright (C) 2008 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include "bayou.h" - -#define TIMEOUT_MESSAGE "Press ESC for the menu (%2d)...\r" -#define TIMEOUT_KEY '\033' - -void run_payload(struct payload *p) -{ - int ret, i; - - /* For chooser entries, just run the payload. */ - if (p->pentry.type == BPT_TYPE_CHOOSER) { - self_load_and_run(p, &ret); - return; - } - - /* For chained entries, run all the sub-chain items. */ - for (i = 0; i < bayoucfg.n_entries; i++) { - struct payload *s = &(bayoucfg.entries[i]); - - if (s->pentry.parent == p->pentry.index) - self_load_and_run(s, &ret); - } -} - -char *payload_get_name(struct payload *p) -{ - if (p->pentry.type == BPT_TYPE_CHAIN) - return (char *)p->pentry.title; - else if (p->pentry.type == BPT_TYPE_CHOOSER) { - if (p->pentry.title[0] != 0) - return (char *)p->pentry.title; - return p->params[BAYOU_PARAM_DESC]; - } - - return NULL; -} - -struct payload *payload_get_default(void) -{ - int i; - - for (i = 0; i < bayoucfg.n_entries; i++) { - struct payload *s = &(bayoucfg.entries[i]); - - if (s->pentry.parent == 0 && s->pentry.flags & BPT_FLAG_DEFAULT) - return s; - } - - return NULL; -} - -void run_payload_timeout(struct payload *p, int timeout) -{ - int t, ch, tval; - - for (t = timeout; t >= 0; t--) { - printf(TIMEOUT_MESSAGE, t); - - tval = 1000; - ch = getchar_timeout(&tval); - - if (ch == TIMEOUT_KEY) - return; - } - - run_payload(p); -} - -void payload_parse_params(struct payload *pload, u8 *params, int len) -{ - char *ptr = (char *)params; - int i = 0; - - if (ptr == NULL) - return; - - while (ptr < ((char *)params + len)) { - - if (!strncmp(ptr, "name=", 5)) { - pload->params[BAYOU_PARAM_NAME] = ptr + 5; - } else if (!strncmp(ptr, "desc=", 5)) { - pload->params[BAYOU_PARAM_DESC] = ptr + 5; - } else if (!strncmp(ptr, "listname=", 9)) { - pload->params[BAYOU_PARAM_LIST] = ptr + 9; - } - - ptr += strnlen(ptr, len - i); - - if (ptr < ((char *)params + len) && *ptr == 0) - ptr++; - } -} diff --git a/payloads/bayou/self.c b/payloads/bayou/self.c deleted file mode 100644 index 88e495b17a..0000000000 --- a/payloads/bayou/self.c +++ /dev/null @@ -1,143 +0,0 @@ -/* - * This file is part of the bayou project. - * - * Copyright (C) 2008 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include "bayou.h" -#include "self.h" - -static int nop_decompress(void *dst, void *src, int len) -{ - memcpy(dst, src, len); - return len; -} - -#ifdef CONFIG_LZMA -extern int ulzma(u8 *, u8 *); - -static int lzma_decompress(void *dst, void *src, int len) -{ - return ulzma((u8 *) src, (u8 *) dst); -} -#endif - -#ifdef CONFIG_NRV2B -extern int unrv2b(u8 *, u8 *, unsigned long *); - -static int nrv2b_decompress(void *dst, void *src, int len) -{ - unsigned long l = (u32) len; - return unrv2b(src, dst, &l); -} -#endif - -static int zeros_decompress(void *dst, void *src, int len) -{ - memset(dst, 0, len); - return len; -} - -int self_get_params(u8 *fptr, u8 **params) -{ - struct self_segment *seg = (struct self_segment *)fptr; - - while (seg->type != SELF_TYPE_ENTRY) { - if (seg->type == 0) - return -1; - - if (seg->type == SELF_TYPE_PARAMS) { - *params = (u8 *) (fptr + seg->offset); - return seg->len; - } - - seg++; - } - - *params = NULL; - - return 0; -} - -int verify_self(u8 *ptr) -{ - struct self_segment *seg = (struct self_segment *)ptr; - - switch (seg->type) { - case SELF_TYPE_CODE: - case SELF_TYPE_DATA: - case SELF_TYPE_BSS: - case SELF_TYPE_PARAMS: - case SELF_TYPE_ENTRY: - return 1; - } - - return 0; -} - -int self_load_and_run(struct payload *p, int *ret) -{ - struct self_segment *seg = (struct self_segment *)p->fptr; - int (*dcmp) (void *, void *, int); - int dlen; - - switch (p->stat.compression) { -#ifdef CONFIG_LZMA - case ALGO_LZMA: - dcmp = lzma_decompress; - break; -#endif -#ifdef CONFIG_NRV2B - case ALGO_NRV2B: - dcmp = nrv2b_decompress; - break; -#endif - case ALGO_ZEROES: - dcmp = zeros_decompress; - break; - case ALGO_NONE: - dcmp = nop_decompress; - default: - printf("E: Unsupported decompression type\n"); - return -1; - } - - while (1) { - u32 laddr = (u32) (seg->load_addr & 0xFFFFFFFF); - - switch (seg->type) { - case SELF_TYPE_CODE: - case SELF_TYPE_DATA: - dlen = dcmp((void *)laddr, - (void *)p->fptr + seg->offset, seg->len); - - if (dlen < seg->mem_len) { - memset((void *)(laddr + dlen), 0, - seg->mem_len - dlen); - } - break; - - case SELF_TYPE_BSS: - memset((void *)laddr, 0, seg->len); - break; - case SELF_TYPE_ENTRY: - *ret = exec(laddr, 0, NULL); - return 0; - default: - break; - } - - seg++; - } - - return -1; -} diff --git a/payloads/bayou/self.h b/payloads/bayou/self.h deleted file mode 100644 index a341899673..0000000000 --- a/payloads/bayou/self.h +++ /dev/null @@ -1,40 +0,0 @@ -/* - * This file is part of the bayou project. - * - * Copyright (C) 2008 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef SELF_H_ -#define SELF_H_ - -#include - -struct self_segment { - u32 type; - u32 offset; - u64 load_addr; - u32 len; - u32 mem_len; -}; - -struct self { - struct larstat stat; - void *fptr; -}; - -#define SELF_TYPE_CODE 0x45444F43 -#define SELF_TYPE_DATA 0x41544144 -#define SELF_TYPE_BSS 0x20535342 -#define SELF_TYPE_PARAMS 0x41524150 -#define SELF_TYPE_ENTRY 0x52544E45 - -#endif From 4841203c3ae7457564f8ef55682c5fa0239447a8 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ky=C3=B6sti=20M=C3=A4lkki?= Date: Sat, 30 Nov 2019 08:18:55 +0200 Subject: [PATCH 0602/1242] binaryPI boards: Bulk remove BINARYPI_LEGACY_WRAPPER remains MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit These boards currently have no build-testing, so they degrade fast. Apply some of the build-tested changes we know to be good from pcengines/apu2 to get them a bit closer to using POSTCAR_STAGE=y. Change-Id: Ibc9a15ed5e91c6dd857f2dd02e37d0979dd6ae90 Signed-off-by: Kyösti Mälkki Reviewed-on: https://review.coreboot.org/c/coreboot/+/37373 Tested-by: build bot (Jenkins) Reviewed-by: Michał Żygowski --- src/mainboard/amd/bettong/romstage.c | 21 +-------------------- src/mainboard/amd/db-ft3b-lc/romstage.c | 21 +-------------------- src/mainboard/amd/lamar/romstage.c | 22 ---------------------- src/mainboard/amd/olivehillplus/romstage.c | 17 +---------------- src/mainboard/bap/ode_e21XX/romstage.c | 22 +--------------------- src/northbridge/amd/agesa/state_machine.h | 3 --- 6 files changed, 4 insertions(+), 102 deletions(-) diff --git a/src/mainboard/amd/bettong/romstage.c b/src/mainboard/amd/bettong/romstage.c index 58430dcf17..0f41f714e3 100644 --- a/src/mainboard/amd/bettong/romstage.c +++ b/src/mainboard/amd/bettong/romstage.c @@ -38,30 +38,11 @@ static void romstage_main_template(void) post_code(0x31); console_init(); } - - - /* Load MPB */ - val = cpuid_eax(1); - printk(BIOS_DEBUG, "BSP Family_Model: %08x\n", val); - printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx); - - post_code(0x37); - AGESAWRAPPER(amdinitreset); - post_code(0x38); - printk(BIOS_DEBUG, "Got past agesawrapper_amdinitreset\n"); - - post_code(0x39); - AGESAWRAPPER(amdinitearly); - - post_code(0x40); - AGESAWRAPPER(amdinitpost); } void agesa_postcar(struct sysinfo *cb) { - post_code(0x41); - AGESAWRAPPER(amdinitenv); - + /* After AMD_INIT_ENV -> move to ramstage ? */ if (acpi_is_wakeup_s4()) { outb(0xEE, PM_INDEX); outb(0x8, PM_DATA); diff --git a/src/mainboard/amd/db-ft3b-lc/romstage.c b/src/mainboard/amd/db-ft3b-lc/romstage.c index a0c6b8d9f3..a3ad3a16e9 100644 --- a/src/mainboard/amd/db-ft3b-lc/romstage.c +++ b/src/mainboard/amd/db-ft3b-lc/romstage.c @@ -43,30 +43,11 @@ static void romstage_main_template(void) post_code(0x31); console_init(); } - - /* Load MPB */ - val = cpuid_eax(1); - printk(BIOS_DEBUG, "BSP Family_Model: %08x\n", val); - printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx); - - post_code(0x37); - AGESAWRAPPER(amdinitreset); - - post_code(0x38); - printk(BIOS_DEBUG, "Got past avalon_early_setup\n"); - - post_code(0x39); - AGESAWRAPPER(amdinitearly); - - post_code(0x40); - AGESAWRAPPER(amdinitpost); } void agesa_postcar(struct sysinfo *cb) { - post_code(0x41); - AGESAWRAPPER(amdinitenv); - + /* After AMD_INIT_ENV -> move to ramstage ? */ outb(0xEA, 0xCD6); outb(0x1, 0xcd7); } diff --git a/src/mainboard/amd/lamar/romstage.c b/src/mainboard/amd/lamar/romstage.c index 7f37990efc..a22b247f27 100644 --- a/src/mainboard/amd/lamar/romstage.c +++ b/src/mainboard/amd/lamar/romstage.c @@ -54,26 +54,4 @@ static void romstage_main_template(void) post_code(0x31); console_init(); } - - /* Load MPB */ - val = cpuid_eax(1); - printk(BIOS_DEBUG, "BSP Family_Model: %08x\n", val); - printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx); - - post_code(0x37); - AGESAWRAPPER(amdinitreset); - post_code(0x38); - printk(BIOS_DEBUG, "Got past hudson_early_setup\n"); - - post_code(0x39); - AGESAWRAPPER(amdinitearly); - - post_code(0x40); - AGESAWRAPPER(amdinitpost); -} - -void agesa_postcar(struct sysinfo *cb) -{ - post_code(0x41); - AGESAWRAPPER(amdinitenv); } diff --git a/src/mainboard/amd/olivehillplus/romstage.c b/src/mainboard/amd/olivehillplus/romstage.c index c04aafeff6..3dd7d531eb 100644 --- a/src/mainboard/amd/olivehillplus/romstage.c +++ b/src/mainboard/amd/olivehillplus/romstage.c @@ -59,26 +59,11 @@ static void romstage_main_template(void) for (i = 0; i < 200000; i++) inb(0xCD6); } - - post_code(0x37); - AGESAWRAPPER(amdinitreset); - - post_code(0x38); - printk(BIOS_DEBUG, "Got past avalon_early_setup\n"); - - post_code(0x39); - AGESAWRAPPER(amdinitearly); - - post_code(0x40); - AGESAWRAPPER(amdinitpost); } void agesa_postcar(struct sysinfo *cb) { - //PspMboxBiosCmdDramInfo(); - post_code(0x41); - AGESAWRAPPER(amdinitenv); - + /* After AMD_INIT_ENV -> move to ramstage ? */ outb(0xEA, 0xCD6); outb(0x1, 0xcd7); } diff --git a/src/mainboard/bap/ode_e21XX/romstage.c b/src/mainboard/bap/ode_e21XX/romstage.c index de39f18a75..9729ffb400 100644 --- a/src/mainboard/bap/ode_e21XX/romstage.c +++ b/src/mainboard/bap/ode_e21XX/romstage.c @@ -47,31 +47,11 @@ static void romstage_main_template(void) post_code(0x31); console_init(); } - - /* Load MPB */ - val = cpuid_eax(1); - printk(BIOS_DEBUG, "BSP Family_Model: %08x\n", val); - printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx); - - post_code(0x37); - AGESAWRAPPER(amdinitreset); - - post_code(0x38); - printk(BIOS_DEBUG, "Got past avalon_early_setup\n"); - - post_code(0x39); - AGESAWRAPPER(amdinitearly); - - post_code(0x40); - AGESAWRAPPER(amdinitpost); } void agesa_postcar(struct sysinfo *cb) { - //PspMboxBiosCmdDramInfo(); - post_code(0x41); - AGESAWRAPPER(amdinitenv); - + /* After AMD_INIT_ENV -> move to ramstage ? */ outb(0xEA, 0xCD6); outb(0x1, 0xcd7); } diff --git a/src/northbridge/amd/agesa/state_machine.h b/src/northbridge/amd/agesa/state_machine.h index 02a7a41edc..9de011a062 100644 --- a/src/northbridge/amd/agesa/state_machine.h +++ b/src/northbridge/amd/agesa/state_machine.h @@ -44,9 +44,6 @@ struct sysinfo int s3resume; }; -void agesa_main(struct sysinfo *cb); -void agesa_postcar(struct sysinfo *cb); - void board_BeforeAgesa(struct sysinfo *cb); void platform_once(struct sysinfo *cb); From d83bd535be3035d19aaf37c17182e8ad2e3dde87 Mon Sep 17 00:00:00 2001 From: Nico Huber Date: Sun, 8 Dec 2019 12:05:21 +0100 Subject: [PATCH 0603/1242] Kconfig: Drop NO_RELOCATABLE_RAMSTAGE MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit It's not selected anywhere anymore. Drop it and set the default for RELOCATABLE_RAMSTAGE directly. Change-Id: I580e89525ece39418afeefd6a9d0b89b370ca95f Signed-off-by: Nico Huber Reviewed-on: https://review.coreboot.org/c/coreboot/+/37577 Reviewed-by: Arthur Heymans Reviewed-by: Kyösti Mälkki Reviewed-by: ron minnich Tested-by: build bot (Jenkins) --- src/Kconfig | 7 +------ 1 file changed, 1 insertion(+), 6 deletions(-) diff --git a/src/Kconfig b/src/Kconfig index 2e06299af3..25bb450174 100644 --- a/src/Kconfig +++ b/src/Kconfig @@ -263,14 +263,9 @@ config UBSAN say N because it adds a small performance penalty and may abort on code that happens to work in spite of the UB. -config NO_RELOCATABLE_RAMSTAGE - bool - default n if ARCH_X86 - default y - config RELOCATABLE_RAMSTAGE bool - default !NO_RELOCATABLE_RAMSTAGE + default y if ARCH_X86 select RELOCATABLE_MODULES help The reloctable ramstage support allows for the ramstage to be built From 19b963ce86058a65d34d9951d9b9f3420316343e Mon Sep 17 00:00:00 2001 From: Christian Walter Date: Mon, 9 Dec 2019 15:07:13 +0100 Subject: [PATCH 0604/1242] include/device/pci_ids: Add Coffeelake U IGD P630 Change-Id: Ifdb9943e6362b7f29c2079759ea09d7b3a940993 Signed-off-by: Christian Walter Reviewed-on: https://review.coreboot.org/c/coreboot/+/37608 Reviewed-by: Patrick Rudolph Reviewed-by: Paul Menzel Tested-by: build bot (Jenkins) --- src/include/device/pci_ids.h | 1 + src/soc/intel/cannonlake/bootblock/report_platform.c | 1 + src/soc/intel/common/block/graphics/graphics.c | 1 + 3 files changed, 3 insertions(+) diff --git a/src/include/device/pci_ids.h b/src/include/device/pci_ids.h index b75e596d19..932414185e 100644 --- a/src/include/device/pci_ids.h +++ b/src/include/device/pci_ids.h @@ -3234,6 +3234,7 @@ #define PCI_DEVICE_ID_INTEL_CFL_S_GT2_2 0x3e98 #define PCI_DEVICE_ID_INTEL_CFL_S_GT2_3 0x3e9a #define PCI_DEVICE_ID_INTEL_CFL_S_GT2_4 0x3e91 +#define PCI_DEVICE_ID_INTEL_CFL_U_GT2 0x3e96 #define PCI_DEVICE_ID_INTEL_ICL_GT0_ULT 0x8A70 #define PCI_DEVICE_ID_INTEL_ICL_GT0_5_ULT 0x8A71 #define PCI_DEVICE_ID_INTEL_ICL_GT1_ULT 0x8A40 diff --git a/src/soc/intel/cannonlake/bootblock/report_platform.c b/src/soc/intel/cannonlake/bootblock/report_platform.c index 8d823850fd..8cdf38e64b 100644 --- a/src/soc/intel/cannonlake/bootblock/report_platform.c +++ b/src/soc/intel/cannonlake/bootblock/report_platform.c @@ -138,6 +138,7 @@ static struct { { PCI_DEVICE_ID_INTEL_CFL_S_GT2_2, "Coffeelake-S GT2" }, { PCI_DEVICE_ID_INTEL_CFL_S_GT2_3, "Coffeelake-S GT2" }, { PCI_DEVICE_ID_INTEL_CFL_S_GT2_4, "Coffeelake-S GT2" }, + { PCI_DEVICE_ID_INTEL_CFL_U_GT2, "Coffeelake-U GT2" }, { PCI_DEVICE_ID_INTEL_CML_GT1_ULT_1, "CometLake ULT GT1" }, { PCI_DEVICE_ID_INTEL_CML_GT1_ULT_2, "CometLake ULT GT1" }, { PCI_DEVICE_ID_INTEL_CML_GT2_ULT_1, "CometLake ULT GT2" }, diff --git a/src/soc/intel/common/block/graphics/graphics.c b/src/soc/intel/common/block/graphics/graphics.c index e91e0af16f..4b418cc4b4 100644 --- a/src/soc/intel/common/block/graphics/graphics.c +++ b/src/soc/intel/common/block/graphics/graphics.c @@ -172,6 +172,7 @@ static const unsigned short pci_device_ids[] = { PCI_DEVICE_ID_INTEL_CFL_S_GT2_2, PCI_DEVICE_ID_INTEL_CFL_S_GT2_3, PCI_DEVICE_ID_INTEL_CFL_S_GT2_4, + PCI_DEVICE_ID_INTEL_CFL_U_GT2, PCI_DEVICE_ID_INTEL_ICL_GT0_ULT, PCI_DEVICE_ID_INTEL_ICL_GT0_5_ULT, PCI_DEVICE_ID_INTEL_ICL_GT1_ULT, From e86ded841fdb3846b070a9cbe1793f72efe540aa Mon Sep 17 00:00:00 2001 From: Patrick Georgi Date: Mon, 9 Dec 2019 10:57:34 +0100 Subject: [PATCH 0605/1242] Documentation: Describe how to deal with snooping https proxies Disabling SSL verification is far from optimal, but depending on the circumstances may be the most practical way, so describe how to do that instead of leaving users confused. It's also not _that_ bad because git's hashing scheme should uncover most attempts to tamper with code, either when checking signed tags or when people push (and see lots of modified commits). State the command in a way that isn't conductive to careless copy & paste. Change-Id: Idbd52ba5d6e8b0f0e891fca16e4159ccef10771a Signed-off-by: Patrick Georgi Reviewed-on: https://review.coreboot.org/c/coreboot/+/37599 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel Reviewed-by: Angel Pons --- Documentation/tutorial/part2.md | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/Documentation/tutorial/part2.md b/Documentation/tutorial/part2.md index 3009e28167..43e9253fde 100644 --- a/Documentation/tutorial/part2.md +++ b/Documentation/tutorial/part2.md @@ -58,6 +58,20 @@ the password, and add the following to your `$HOME/.netrc` file: where YourUserNameHere is your username, and YourPasswordHere is the password you just generated. +If your system is behind a snooping HTTPS proxy, you might also have to +make its SSL certificate known to curl, a system specific operation. +If that's not possible for some reason, you can also disable SSL +certificate verification in git: + + git config [--global] http.sslVerify [true|false] + +The `--global` argument sets it for all git transfers of your local +user, `false` means not to validate the certificate. + +If that still doesn't allow you to pull or push changes to the server, the +proxy is likely tampering with the data stream, in which case there's nothing +we can do. + ## Part 3: Clone coreboot and configure it for submitting patches On Gerrit, click on the **Browse** tab in the upper left corner and select From 13746076e95a611b56dfe37519685ae125172bb4 Mon Sep 17 00:00:00 2001 From: Elyes HAOUAS Date: Sun, 8 Dec 2019 11:34:24 +0100 Subject: [PATCH 0606/1242] mainboard/(i945,ich7): Remove commented RCBA32(0x341c) code PCIe root port clock gate is already enabled at i945/early_init.c Also fix comments when only PCIe root port is enabled. Change-Id: Ica38529dbdd5cc51b19b426999a1d9f0b678b4f5 Signed-off-by: Elyes HAOUAS Reviewed-on: https://review.coreboot.org/c/coreboot/+/37576 Reviewed-by: Nico Huber Tested-by: build bot (Jenkins) --- src/mainboard/asus/p5gc-mx/early_init.c | 2 +- src/mainboard/getac/p470/early_init.c | 3 --- src/mainboard/gigabyte/ga-945gcm-s2l/early_init.c | 2 +- src/mainboard/ibase/mb899/early_init.c | 3 --- src/mainboard/intel/d945gclf/early_init.c | 3 --- src/northbridge/intel/i945/early_init.c | 1 + 6 files changed, 3 insertions(+), 11 deletions(-) diff --git a/src/mainboard/asus/p5gc-mx/early_init.c b/src/mainboard/asus/p5gc-mx/early_init.c index 6d37fed2ef..988d2328f6 100644 --- a/src/mainboard/asus/p5gc-mx/early_init.c +++ b/src/mainboard/asus/p5gc-mx/early_init.c @@ -94,7 +94,7 @@ static u8 msr_get_fsb(void) void mainboard_late_rcba_config(void) { - /* Enable PCIe Root Port Clock Gate */ + /* Enable only PCIe Root Port Clock Gate */ RCBA32(CG) = 0x00000001; } diff --git a/src/mainboard/getac/p470/early_init.c b/src/mainboard/getac/p470/early_init.c index c75caada6e..1ce44ae9d7 100644 --- a/src/mainboard/getac/p470/early_init.c +++ b/src/mainboard/getac/p470/early_init.c @@ -138,9 +138,6 @@ void mainboard_late_rcba_config(void) /* Disable unused devices */ RCBA32(FD) |= FD_INTLAN; - /* Enable PCIe Root Port Clock Gate */ - // RCBA32(0x341c) = 0x00000001; - /* This should probably go into the ACPI enable trap */ /* Set up I/O Trap #0 for 0xfe00 (SMIC) */ RCBA32(0x1e84) = 0x00020001; diff --git a/src/mainboard/gigabyte/ga-945gcm-s2l/early_init.c b/src/mainboard/gigabyte/ga-945gcm-s2l/early_init.c index 7b82059580..f0f598b7af 100644 --- a/src/mainboard/gigabyte/ga-945gcm-s2l/early_init.c +++ b/src/mainboard/gigabyte/ga-945gcm-s2l/early_init.c @@ -56,6 +56,6 @@ void bootblock_mainboard_early_init(void) void mainboard_late_rcba_config(void) { - /* Enable PCIe Root Port Clock Gate */ + /* Enable only PCIe Root Port Clock Gate */ RCBA32(CG) = 0x00000001; } diff --git a/src/mainboard/ibase/mb899/early_init.c b/src/mainboard/ibase/mb899/early_init.c index 0b005022d8..fd96f66ea8 100644 --- a/src/mainboard/ibase/mb899/early_init.c +++ b/src/mainboard/ibase/mb899/early_init.c @@ -110,7 +110,4 @@ void mainboard_late_rcba_config(void) RCBA16(D29IR) = 0x0237; RCBA16(D28IR) = 0x3201; RCBA16(D27IR) = 0x0146; - - /* Enable PCIe Root Port Clock Gate */ - // RCBA32(0x341c) = 0x00000001; } diff --git a/src/mainboard/intel/d945gclf/early_init.c b/src/mainboard/intel/d945gclf/early_init.c index b4818e49ca..d31fcc5907 100644 --- a/src/mainboard/intel/d945gclf/early_init.c +++ b/src/mainboard/intel/d945gclf/early_init.c @@ -32,9 +32,6 @@ void mainboard_late_rcba_config(void) /* Disable unused devices */ RCBA32(FD) |= FD_INTLAN; - - /* Enable PCIe Root Port Clock Gate */ - // RCBA32(0x341c) = 0x00000001; } void bootblock_mainboard_early_init(void) diff --git a/src/northbridge/intel/i945/early_init.c b/src/northbridge/intel/i945/early_init.c index 13dce61325..6629a0e0f8 100644 --- a/src/northbridge/intel/i945/early_init.c +++ b/src/northbridge/intel/i945/early_init.c @@ -837,6 +837,7 @@ static void ich7_setup_root_complex_topology(void) static void ich7_setup_pci_express(void) { + /* Enable PCIe Root Port Clock Gate */ RCBA32(CG) |= (1 << 0); /* Initialize slot power limit for root ports */ From 0a2de7b538e3d6490a8d748bc8b8b9b7511c81bc Mon Sep 17 00:00:00 2001 From: Seunghwan Kim Date: Mon, 9 Dec 2019 11:12:08 +0900 Subject: [PATCH 0607/1242] mb/google/kohaku: Update TCC offset setting This change sets TCC offset to 10 for kohaku. BUG=b:144532818 BRANCH=firmware-hatch-12672.B TEST=Checked thermal and performance efficiency internally (b:144532818) Change-Id: Ia4b53de3a53bc39c1cd0f7626ae23d4c11a7a3db Signed-off-by: Seunghwan Kim Reviewed-on: https://review.coreboot.org/c/coreboot/+/37587 Reviewed-by: Kane Chen Reviewed-by: Grace Kao Reviewed-by: Tim Wawrzynczak Tested-by: build bot (Jenkins) --- src/mainboard/google/hatch/variants/kohaku/overridetree.cb | 2 -- 1 file changed, 2 deletions(-) diff --git a/src/mainboard/google/hatch/variants/kohaku/overridetree.cb b/src/mainboard/google/hatch/variants/kohaku/overridetree.cb index d515ecc44d..cd5ce0e816 100644 --- a/src/mainboard/google/hatch/variants/kohaku/overridetree.cb +++ b/src/mainboard/google/hatch/variants/kohaku/overridetree.cb @@ -2,8 +2,6 @@ chip soc/intel/cannonlake register "tdp_pl1_override" = "8" register "tdp_pl2_override" = "51" - register "tcc_offset" = "35" # TCC of 65C - register "SerialIoDevMode" = "{ [PchSerialIoIndexI2C0] = PchSerialIoPci, [PchSerialIoIndexI2C1] = PchSerialIoPci, From a244d5edd4f45fd9e21db3d97ed0a32eaf089e7b Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ky=C3=B6sti=20M=C3=A4lkki?= Date: Mon, 9 Dec 2019 08:08:58 +0200 Subject: [PATCH 0608/1242] sb/amd/{agesa,pi}/hudson: Explicitly enable LPC controller MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Location in hudson_lpc_port80() was called conditionally. Also move hudson_lpc_decode() call after enable_acpimmio_decode_pmXX() due the change from IO to MMIO using pm_read/write. Change-Id: I38e94e4b04f0a493052cfd3ffdd0a9c2ac0d07fc Signed-off-by: Kyösti Mälkki Reviewed-on: https://review.coreboot.org/c/coreboot/+/37595 Tested-by: build bot (Jenkins) Reviewed-by: Michał Żygowski --- src/southbridge/amd/agesa/hudson/bootblock.c | 2 +- src/southbridge/amd/agesa/hudson/early_setup.c | 11 ++++------- src/southbridge/amd/pi/hudson/bootblock.c | 2 +- src/southbridge/amd/pi/hudson/early_setup.c | 11 ++++------- 4 files changed, 10 insertions(+), 16 deletions(-) diff --git a/src/southbridge/amd/agesa/hudson/bootblock.c b/src/southbridge/amd/agesa/hudson/bootblock.c index 6925393b06..4da030b89a 100644 --- a/src/southbridge/amd/agesa/hudson/bootblock.c +++ b/src/southbridge/amd/agesa/hudson/bootblock.c @@ -74,8 +74,8 @@ void bootblock_soc_early_init(void) u32 data; bootblock_southbridge_init(); - hudson_lpc_decode(); enable_acpimmio_decode_pm24(); + hudson_lpc_decode(); if (CONFIG(POST_DEVICE_PCI_PCIE)) hudson_pci_port80(); diff --git a/src/southbridge/amd/agesa/hudson/early_setup.c b/src/southbridge/amd/agesa/hudson/early_setup.c index d85cb2b6f1..84c429955a 100644 --- a/src/southbridge/amd/agesa/hudson/early_setup.c +++ b/src/southbridge/amd/agesa/hudson/early_setup.c @@ -20,6 +20,7 @@ #include #include #include +#include #include "hudson.h" @@ -73,13 +74,6 @@ void hudson_lpc_port80(void) u8 byte; pci_devfn_t dev; - /* Enable LPC controller */ - outb(0xEC, 0xCD6); - byte = inb(0xCD7); - byte |= 1; - outb(0xEC, 0xCD6); - outb(byte, 0xCD7); - /* Enable port 80 LPC decode in pci function 3 configuration space. */ dev = PCI_DEV(0, 0x14, 3); byte = pci_read_config8(dev, 0x4a); @@ -92,6 +86,9 @@ void hudson_lpc_decode(void) pci_devfn_t dev; u32 tmp; + /* Enable LPC controller */ + pm_write8(0xec, pm_read8(0xec) | 0x01); + dev = PCI_DEV(0, 0x14, 3); /* Serial port numeration on Hudson: * PORT0 - 0x3f8 diff --git a/src/southbridge/amd/pi/hudson/bootblock.c b/src/southbridge/amd/pi/hudson/bootblock.c index ec8663dad1..d16aecc2a8 100644 --- a/src/southbridge/amd/pi/hudson/bootblock.c +++ b/src/southbridge/amd/pi/hudson/bootblock.c @@ -73,11 +73,11 @@ void bootblock_soc_early_init(void) u32 data; bootblock_southbridge_init(); - hudson_lpc_decode(); if (CONFIG(SOUTHBRIDGE_AMD_PI_BOLTON)) enable_acpimmio_decode_pm24(); else enable_acpimmio_decode_pm04(); + hudson_lpc_decode(); if (CONFIG(POST_DEVICE_PCI_PCIE)) hudson_pci_port80(); diff --git a/src/southbridge/amd/pi/hudson/early_setup.c b/src/southbridge/amd/pi/hudson/early_setup.c index 56b894c852..0e3646bb5c 100644 --- a/src/southbridge/amd/pi/hudson/early_setup.c +++ b/src/southbridge/amd/pi/hudson/early_setup.c @@ -22,6 +22,7 @@ #include #include #include +#include #include "hudson.h" #include "pci_devs.h" @@ -106,13 +107,6 @@ void hudson_lpc_port80(void) u8 byte; pci_devfn_t dev; - /* Enable LPC controller */ - outb(0xEC, 0xCD6); - byte = inb(0xCD7); - byte |= 1; - outb(0xEC, 0xCD6); - outb(byte, 0xCD7); - /* Enable port 80 LPC decode in pci function 3 configuration space. */ dev = PCI_DEV(0, 0x14, 3); byte = pci_read_config8(dev, 0x4a); @@ -125,6 +119,9 @@ void hudson_lpc_decode(void) pci_devfn_t dev; u32 tmp; + /* Enable LPC controller */ + pm_write8(0xec, pm_read8(0xec) | 0x01); + dev = PCI_DEV(0, 0x14, 3); /* Serial port numeration on Hudson: * PORT0 - 0x3f8 From 200d213d1bae614fcd35913c1d46fec7e495717f Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Micha=C5=82=20=C5=BBygowski?= Date: Fri, 6 Dec 2019 12:07:52 +0100 Subject: [PATCH 0609/1242] amdblocks/pci: add common implementation of MMCONF enabling MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add common function to enable PCI MMCONF base address. Use the common function in stoneyridge bootblock. Signed-off-by: Michał Żygowski Change-Id: I1bb8b22b282584c421a9fffa3322b2a8e406d037 Reviewed-on: https://review.coreboot.org/c/coreboot/+/37552 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki --- .../block/include/amdblocks/amd_pci_mmconf.h | 19 +++++++++++++ src/soc/amd/common/block/pci/Makefile.inc | 5 ++-- src/soc/amd/common/block/pci/amd_pci_mmconf.c | 27 +++++++++++++++++++ src/soc/amd/stoneyridge/bootblock/bootblock.c | 8 ++---- 4 files changed, 50 insertions(+), 9 deletions(-) create mode 100644 src/soc/amd/common/block/include/amdblocks/amd_pci_mmconf.h create mode 100644 src/soc/amd/common/block/pci/amd_pci_mmconf.c diff --git a/src/soc/amd/common/block/include/amdblocks/amd_pci_mmconf.h b/src/soc/amd/common/block/include/amdblocks/amd_pci_mmconf.h new file mode 100644 index 0000000000..4b65ad0948 --- /dev/null +++ b/src/soc/amd/common/block/include/amdblocks/amd_pci_mmconf.h @@ -0,0 +1,19 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __AMDBLOCKS_PCI_MMCONF_H__ +#define __AMDBLOCKS_PCI_MMCONF_H__ + +void enable_pci_mmconf(void); + +#endif diff --git a/src/soc/amd/common/block/pci/Makefile.inc b/src/soc/amd/common/block/pci/Makefile.inc index fc40c9d478..558a7ac736 100644 --- a/src/soc/amd/common/block/pci/Makefile.inc +++ b/src/soc/amd/common/block/pci/Makefile.inc @@ -1,5 +1,4 @@ -ifeq ($(CONFIG_SOC_AMD_COMMON_BLOCK_PCI),y) -ramstage-y += amd_pci_util.c +ramstage-$(CONFIG_SOC_AMD_COMMON_BLOCK_PCI) += amd_pci_util.c -endif +all-y += amd_pci_mmconf.c diff --git a/src/soc/amd/common/block/pci/amd_pci_mmconf.c b/src/soc/amd/common/block/pci/amd_pci_mmconf.c new file mode 100644 index 0000000000..1aed51bf1b --- /dev/null +++ b/src/soc/amd/common/block/pci/amd_pci_mmconf.c @@ -0,0 +1,27 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include +#include + +void enable_pci_mmconf(void) +{ + msr_t mmconf; + + mmconf.hi = 0; + mmconf.lo = CONFIG_MMCONF_BASE_ADDRESS | MMIO_RANGE_EN + | fms(CONFIG_MMCONF_BUS_NUMBER) << MMIO_BUS_RANGE_SHIFT; + wrmsr(MMIO_CONF_BASE, mmconf); +} diff --git a/src/soc/amd/stoneyridge/bootblock/bootblock.c b/src/soc/amd/stoneyridge/bootblock/bootblock.c index d92535ac31..9920aff082 100644 --- a/src/soc/amd/stoneyridge/bootblock/bootblock.c +++ b/src/soc/amd/stoneyridge/bootblock/bootblock.c @@ -24,6 +24,7 @@ #include #include #include +#include #include #include #include @@ -42,15 +43,9 @@ /* Set the MMIO Configuration Base Address, Bus Range, and misc MTRRs. */ static void amd_initmmio(void) { - msr_t mmconf; msr_t mtrr_cap = rdmsr(MTRR_CAP_MSR); int mtrr; - mmconf.hi = 0; - mmconf.lo = CONFIG_MMCONF_BASE_ADDRESS | MMIO_RANGE_EN - | fms(CONFIG_MMCONF_BUS_NUMBER) << MMIO_BUS_RANGE_SHIFT; - wrmsr(MMIO_CONF_BASE, mmconf); - /* * todo: AGESA currently writes variable MTRRs. Once that is * corrected, un-hardcode this MTRR. @@ -75,6 +70,7 @@ static void amd_initmmio(void) asmlinkage void bootblock_c_entry(uint64_t base_timestamp) { + enable_pci_mmconf(); amd_initmmio(); /* * Call lib/bootblock.c main with BSP, shortcut for APs From 263f129a8e1d012c53733170acaf9d0a01886b10 Mon Sep 17 00:00:00 2001 From: rkanabar Date: Thu, 28 Nov 2019 10:41:45 +0530 Subject: [PATCH 0610/1242] soc/intel/common: Add Jasperlake Device IDs Add Jasperlake SA and PCH IDs Change-Id: I2c9ec1ee4236184b986d99250f263172c80f7117 Signed-off-by: Ronak Kanabar Reviewed-on: https://review.coreboot.org/c/coreboot/+/37434 Tested-by: build bot (Jenkins) Reviewed-by: Lean Sheng Tan Reviewed-by: Aamir Bohra Reviewed-by: V Sowmya --- src/include/device/pci_ids.h | 39 ++++++++++++++++++- src/soc/intel/common/block/cse/cse.c | 1 + src/soc/intel/common/block/dsp/dsp.c | 1 + .../intel/common/block/graphics/graphics.c | 1 + src/soc/intel/common/block/i2c/i2c.c | 6 +++ src/soc/intel/common/block/lpc/lpc.c | 2 + src/soc/intel/common/block/p2sb/p2sb.c | 1 + src/soc/intel/common/block/pcie/pcie.c | 8 ++++ src/soc/intel/common/block/pmc/pmc.c | 1 + src/soc/intel/common/block/sata/sata.c | 1 + src/soc/intel/common/block/scs/sd.c | 1 + src/soc/intel/common/block/smbus/smbus.c | 1 + src/soc/intel/common/block/spi/spi.c | 4 ++ src/soc/intel/common/block/sram/sram.c | 1 + .../common/block/systemagent/systemagent.c | 1 + src/soc/intel/common/block/uart/uart.c | 3 ++ src/soc/intel/common/block/xhci/xhci.c | 1 + .../tigerlake/bootblock/report_platform.c | 4 ++ 18 files changed, 76 insertions(+), 1 deletion(-) diff --git a/src/include/device/pci_ids.h b/src/include/device/pci_ids.h index 932414185e..43752f8368 100644 --- a/src/include/device/pci_ids.h +++ b/src/include/device/pci_ids.h @@ -2809,6 +2809,8 @@ #define PCI_DEVICE_ID_INTEL_TGP_ESPI_24 0xA09D #define PCI_DEVICE_ID_INTEL_TGP_ESPI_25 0xA09E #define PCI_DEVICE_ID_INTEL_TGP_ESPI_26 0xA09F +#define PCI_DEVICE_ID_INTEL_JSP_PRE_PROD_ESPI_1 0x3887 +#define PCI_DEVICE_ID_INTEL_JSP_PRE_PROD_ESPI_2 0x4d80 /* Intel PCIE device ids */ #define PCI_DEVICE_ID_INTEL_SPT_LP_PCIE_RP1 0x9d10 @@ -3004,6 +3006,15 @@ #define PCI_DEVICE_ID_INTEL_CMP_LP_PCIE_RP15 0x02b6 #define PCI_DEVICE_ID_INTEL_CMP_LP_PCIE_RP16 0x02b7 +#define PCI_DEVICE_ID_INTEL_JSP_PRE_PROD_PCIE_RP1 0x38b8 +#define PCI_DEVICE_ID_INTEL_JSP_PRE_PROD_PCIE_RP2 0x38b9 +#define PCI_DEVICE_ID_INTEL_JSP_PRE_PROD_PCIE_RP3 0x38ba +#define PCI_DEVICE_ID_INTEL_JSP_PRE_PROD_PCIE_RP4 0x38bb +#define PCI_DEVICE_ID_INTEL_JSP_PRE_PROD_PCIE_RP5 0x38bc +#define PCI_DEVICE_ID_INTEL_JSP_PRE_PROD_PCIE_RP6 0x38bd +#define PCI_DEVICE_ID_INTEL_JSP_PRE_PROD_PCIE_RP7 0x38be +#define PCI_DEVICE_ID_INTEL_JSP_PRE_PROD_PCIE_RP8 0x38bf + /* Intel SATA device Ids */ #define PCI_DEVICE_ID_INTEL_SPT_U_SATA 0x9d03 #define PCI_DEVICE_ID_INTEL_SPT_U_Y_PREMIUM_SATA 0x9d07 @@ -3035,6 +3046,7 @@ #define PCI_DEVICE_ID_INTEL_TGP_SATA 0xa0d5 #define PCI_DEVICE_ID_INTEL_TGP_PREMIUM_SATA 0xa0d7 #define PCI_DEVICE_ID_INTEL_TGP_COMPAT_SATA 0x282a +#define PCI_DEVICE_ID_INTEL_JSP_PRE_PROD_SATA 0x38d3 /* Intel PMC device Ids */ #define PCI_DEVICE_ID_INTEL_SPT_LP_PMC 0x9d21 @@ -3049,6 +3061,7 @@ #define PCI_DEVICE_ID_INTEL_ICP_PMC 0x34a1 #define PCI_DEVICE_ID_INTEL_CMP_PMC 0x02a1 #define PCI_DEVICE_ID_INTEL_TGP_PMC 0xa0a1 +#define PCI_DEVICE_ID_INTEL_JSP_PRE_PROD_PMC 0x38a1 /* Intel I2C device Ids */ #define PCI_DEVICE_ID_INTEL_SPT_I2C0 0x9d60 @@ -3108,6 +3121,13 @@ #define PCI_DEVICE_ID_INTEL_TGP_I2C6 0xa0d8 #define PCI_DEVICE_ID_INTEL_TGP_I2C7 0xa0d9 +#define PCI_DEVICE_ID_INTEL_JSP_PRE_PROD_I2C0 0x38e8 +#define PCI_DEVICE_ID_INTEL_JSP_PRE_PROD_I2C1 0x38e9 +#define PCI_DEVICE_ID_INTEL_JSP_PRE_PROD_I2C2 0x38ea +#define PCI_DEVICE_ID_INTEL_JSP_PRE_PROD_I2C3 0x38eb +#define PCI_DEVICE_ID_INTEL_JSP_PRE_PROD_I2C4 0x38c5 +#define PCI_DEVICE_ID_INTEL_JSP_PRE_PROD_I2C5 0x38c6 + /* Intel UART device Ids */ #define PCI_DEVICE_ID_INTEL_SPT_UART0 0x9d27 #define PCI_DEVICE_ID_INTEL_SPT_UART1 0x9d28 @@ -3142,6 +3162,10 @@ #define PCI_DEVICE_ID_INTEL_TGP_UART1 0xa0a9 #define PCI_DEVICE_ID_INTEL_TGP_UART2 0xa0c7 +#define PCI_DEVICE_ID_INTEL_JSP_PRE_PROD_UART0 0x38a8 +#define PCI_DEVICE_ID_INTEL_JSP_PRE_PROD_UART1 0x38a9 +#define PCI_DEVICE_ID_INTEL_JSP_PRE_PROD_UART2 0x38c7 + /* Intel SPI device Ids */ #define PCI_DEVICE_ID_INTEL_SPT_SPI1 0x9d24 #define PCI_DEVICE_ID_INTEL_SPT_SPI2 0x9d29 @@ -3180,6 +3204,11 @@ #define PCI_DEVICE_ID_INTEL_TGP_GSPI5 0xa0de #define PCI_DEVICE_ID_INTEL_TGP_GSPI6 0xa0df +#define PCI_DEVICE_ID_INTEL_JSP_PRE_PROD_SPI0 0x38aa +#define PCI_DEVICE_ID_INTEL_JSP_PRE_PROD_SPI1 0x38ab +#define PCI_DEVICE_ID_INTEL_JSP_PRE_PROD_SPI2 0x38fb +#define PCI_DEVICE_ID_INTEL_JSP_PRE_PROD_HWSEQ_SPI 0x38a4 + /* Intel IGD device Ids */ #define PCI_DEVICE_ID_INTEL_SKL_GT1F_DT2 0x1902 #define PCI_DEVICE_ID_INTEL_SKL_GT1_SULTM 0x1906 @@ -3283,6 +3312,7 @@ #define PCI_DEVICE_ID_INTEL_TGL_GT2_ULT 0x9A49 #define PCI_DEVICE_ID_INTEL_TGL_GT3_ULT 0x9A52 #define PCI_DEVICE_ID_INTEL_TGL_GT2_ULX 0x9A40 +#define PCI_DEVICE_ID_INTEL_JSL_PRE_PROD_GT0 0x4569 /* Intel Northbridge Ids */ #define PCI_DEVICE_ID_INTEL_APL_NB 0x5af0 @@ -3338,6 +3368,7 @@ #define PCI_DEVICE_ID_INTEL_TGL_ID_U 0x9A14 #define PCI_DEVICE_ID_INTEL_TGL_ID_U_1 0x9A12 #define PCI_DEVICE_ID_INTEL_TGL_ID_Y 0x9A10 +#define PCI_DEVICE_ID_INTEL_JSL_PRE_PROD 0x4e2a /* Intel SMBUS device Ids */ #define PCI_DEVICE_ID_INTEL_SPT_LP_SMBUS 0x9d23 @@ -3349,6 +3380,7 @@ #define PCI_DEVICE_ID_INTEL_ICP_LP_SMBUS 0x34a3 #define PCI_DEVICE_ID_INTEL_CMP_SMBUS 0x02a3 #define PCI_DEVICE_ID_INTEL_TGP_LP_SMBUS 0xa0a3 +#define PCI_DEVICE_ID_INTEL_JSP_PRE_PROD_SMBUS 0x38a3 /* Intel XHCI device Ids */ #define PCI_DEVICE_ID_INTEL_APL_XHCI 0x5aa8 @@ -3363,6 +3395,7 @@ #define PCI_DEVICE_ID_INTEL_ICP_LP_XHCI 0x34ed #define PCI_DEVICE_ID_INTEL_CMP_LP_XHCI 0x02ed #define PCI_DEVICE_ID_INTEL_TGP_LP_XHCI 0xa0ed +#define PCI_DEVICE_ID_INTEL_JSP_PRE_PROD_XHCI 0x38ed /* Intel P2SB device Ids */ #define PCI_DEVICE_ID_INTEL_APL_P2SB 0x5a92 @@ -3377,6 +3410,7 @@ #define PCI_DEVICE_ID_INTEL_ICL_P2SB 0x34a0 #define PCI_DEVICE_ID_INTEL_CMP_P2SB 0x02a0 #define PCI_DEVICE_ID_INTEL_TGL_P2SB 0xa0a0 +#define PCI_DEVICE_ID_INTEL_JSP_PRE_PROD_P2SB 0x38a0 /* Intel SRAM device Ids */ #define PCI_DEVICE_ID_INTEL_APL_SRAM 0x5aec @@ -3386,6 +3420,7 @@ #define PCI_DEVICE_ID_INTEL_ICL_SRAM 0x34ef #define PCI_DEVICE_ID_INTEL_CMP_SRAM 0x02ef #define PCI_DEVICE_ID_INTEL_TGL_SRAM 0xa0ef +#define PCI_DEVICE_ID_INTEL_JSP_PRE_PROD_SRAM 0x38ef /* Intel AUDIO device Ids */ #define PCI_DEVICE_ID_INTEL_APL_AUDIO 0x5a98 @@ -3401,6 +3436,7 @@ #define PCI_DEVICE_ID_INTEL_CMP_AUDIO 0x02c8 #define PCI_DEVICE_ID_INTEL_BSW_AUDIO 0x2284 #define PCI_DEVICE_ID_INTEL_TGL_AUDIO 0xa0c8 +#define PCI_DEVICE_ID_INTEL_JSP_PRE_PROD_AUDIO 0x38c8 /* Intel HECI/ME device Ids */ #define PCI_DEVICE_ID_INTEL_APL_CSE0 0x5a9a @@ -3417,6 +3453,7 @@ #define PCI_DEVICE_ID_INTEL_ICL_CSE0 0x34e0 #define PCI_DEVICE_ID_INTEL_CMP_CSE0 0x02e0 #define PCI_DEVICE_ID_INTEL_TGL_CSE0 0xa0e0 +#define PCI_DEVICE_ID_INTEL_JSP_PRE_PROD_CSE0 0x38e0 /* Intel XDCI device Ids */ #define PCI_DEVICE_ID_INTEL_APL_XDCI 0x5aaa @@ -3436,6 +3473,7 @@ #define PCI_DEVICE_ID_INTEL_CNP_H_SD 0xa375 #define PCI_DEVICE_ID_INTEL_ICL_SD 0x34f8 #define PCI_DEVICE_ID_INTEL_CMP_SD 0x02f5 +#define PCI_DEVICE_ID_INTEL_JSP_PRE_PROD_SD 0x38f8 /* Intel EMMC device Ids */ #define PCI_DEVICE_ID_INTEL_SKL_EMMC 0x9d2b @@ -3514,7 +3552,6 @@ #define PCI_DEVICE_ID_ADAPTEC_7887 0x8778 #define PCI_DEVICE_ID_ADAPTEC_7888 0x8878 #define PCI_DEVICE_ID_ADAPTEC_1030 0x8b78 - #define PCI_VENDOR_ID_ADAPTEC2 0x9005 #define PCI_DEVICE_ID_ADAPTEC2_2940U2 0x0010 #define PCI_DEVICE_ID_ADAPTEC2_2930U2 0x0011 diff --git a/src/soc/intel/common/block/cse/cse.c b/src/soc/intel/common/block/cse/cse.c index 011916dd92..6aaba40559 100644 --- a/src/soc/intel/common/block/cse/cse.c +++ b/src/soc/intel/common/block/cse/cse.c @@ -755,6 +755,7 @@ static const unsigned short pci_device_ids[] = { PCI_DEVICE_ID_INTEL_ICL_CSE0, PCI_DEVICE_ID_INTEL_CMP_CSE0, PCI_DEVICE_ID_INTEL_TGL_CSE0, + PCI_DEVICE_ID_INTEL_JSP_PRE_PROD_CSE0, 0, }; diff --git a/src/soc/intel/common/block/dsp/dsp.c b/src/soc/intel/common/block/dsp/dsp.c index 947c002250..6c00ed1c77 100644 --- a/src/soc/intel/common/block/dsp/dsp.c +++ b/src/soc/intel/common/block/dsp/dsp.c @@ -35,6 +35,7 @@ static const unsigned short pci_device_ids[] = { PCI_DEVICE_ID_INTEL_CMP_AUDIO, PCI_DEVICE_ID_INTEL_ICL_AUDIO, PCI_DEVICE_ID_INTEL_TGL_AUDIO, + PCI_DEVICE_ID_INTEL_JSP_PRE_PROD_AUDIO, 0, }; diff --git a/src/soc/intel/common/block/graphics/graphics.c b/src/soc/intel/common/block/graphics/graphics.c index 4b418cc4b4..cbe189c9d1 100644 --- a/src/soc/intel/common/block/graphics/graphics.c +++ b/src/soc/intel/common/block/graphics/graphics.c @@ -213,6 +213,7 @@ static const unsigned short pci_device_ids[] = { PCI_DEVICE_ID_INTEL_TGL_GT2_ULT, PCI_DEVICE_ID_INTEL_TGL_GT2_ULX, PCI_DEVICE_ID_INTEL_TGL_GT3_ULT, + PCI_DEVICE_ID_INTEL_JSL_PRE_PROD_GT0, 0, }; diff --git a/src/soc/intel/common/block/i2c/i2c.c b/src/soc/intel/common/block/i2c/i2c.c index 1749bf547a..bc692d3a87 100644 --- a/src/soc/intel/common/block/i2c/i2c.c +++ b/src/soc/intel/common/block/i2c/i2c.c @@ -243,6 +243,12 @@ static const unsigned short pci_device_ids[] = { PCI_DEVICE_ID_INTEL_TGP_I2C5, PCI_DEVICE_ID_INTEL_TGP_I2C6, PCI_DEVICE_ID_INTEL_TGP_I2C7, + PCI_DEVICE_ID_INTEL_JSP_PRE_PROD_I2C0, + PCI_DEVICE_ID_INTEL_JSP_PRE_PROD_I2C1, + PCI_DEVICE_ID_INTEL_JSP_PRE_PROD_I2C2, + PCI_DEVICE_ID_INTEL_JSP_PRE_PROD_I2C3, + PCI_DEVICE_ID_INTEL_JSP_PRE_PROD_I2C4, + PCI_DEVICE_ID_INTEL_JSP_PRE_PROD_I2C5, 0, }; diff --git a/src/soc/intel/common/block/lpc/lpc.c b/src/soc/intel/common/block/lpc/lpc.c index 249e6d6256..258975ce76 100644 --- a/src/soc/intel/common/block/lpc/lpc.c +++ b/src/soc/intel/common/block/lpc/lpc.c @@ -222,6 +222,8 @@ static const unsigned short pci_device_ids[] = { PCI_DEVICE_ID_INTEL_TGP_ESPI_24, PCI_DEVICE_ID_INTEL_TGP_ESPI_25, PCI_DEVICE_ID_INTEL_TGP_ESPI_26, + PCI_DEVICE_ID_INTEL_JSP_PRE_PROD_ESPI_1, + PCI_DEVICE_ID_INTEL_JSP_PRE_PROD_ESPI_2, 0 }; diff --git a/src/soc/intel/common/block/p2sb/p2sb.c b/src/soc/intel/common/block/p2sb/p2sb.c index 981ad07872..75c74f298a 100644 --- a/src/soc/intel/common/block/p2sb/p2sb.c +++ b/src/soc/intel/common/block/p2sb/p2sb.c @@ -180,6 +180,7 @@ static const unsigned short pci_device_ids[] = { PCI_DEVICE_ID_INTEL_ICL_P2SB, PCI_DEVICE_ID_INTEL_CMP_P2SB, PCI_DEVICE_ID_INTEL_TGL_P2SB, + PCI_DEVICE_ID_INTEL_JSP_PRE_PROD_P2SB, 0, }; diff --git a/src/soc/intel/common/block/pcie/pcie.c b/src/soc/intel/common/block/pcie/pcie.c index 406a227387..ecc1fcbc71 100644 --- a/src/soc/intel/common/block/pcie/pcie.c +++ b/src/soc/intel/common/block/pcie/pcie.c @@ -266,6 +266,14 @@ static const unsigned short pcie_device_ids[] = { PCI_DEVICE_ID_INTEL_TGP_LP_PCIE_RP14, PCI_DEVICE_ID_INTEL_TGP_LP_PCIE_RP15, PCI_DEVICE_ID_INTEL_TGP_LP_PCIE_RP16, + PCI_DEVICE_ID_INTEL_JSP_PRE_PROD_PCIE_RP1, + PCI_DEVICE_ID_INTEL_JSP_PRE_PROD_PCIE_RP2, + PCI_DEVICE_ID_INTEL_JSP_PRE_PROD_PCIE_RP3, + PCI_DEVICE_ID_INTEL_JSP_PRE_PROD_PCIE_RP4, + PCI_DEVICE_ID_INTEL_JSP_PRE_PROD_PCIE_RP5, + PCI_DEVICE_ID_INTEL_JSP_PRE_PROD_PCIE_RP6, + PCI_DEVICE_ID_INTEL_JSP_PRE_PROD_PCIE_RP7, + PCI_DEVICE_ID_INTEL_JSP_PRE_PROD_PCIE_RP8, 0 }; diff --git a/src/soc/intel/common/block/pmc/pmc.c b/src/soc/intel/common/block/pmc/pmc.c index 1d2aa61807..1645070fa7 100644 --- a/src/soc/intel/common/block/pmc/pmc.c +++ b/src/soc/intel/common/block/pmc/pmc.c @@ -134,6 +134,7 @@ static const unsigned short pci_device_ids[] = { PCI_DEVICE_ID_INTEL_ICP_PMC, PCI_DEVICE_ID_INTEL_CMP_PMC, PCI_DEVICE_ID_INTEL_TGP_PMC, + PCI_DEVICE_ID_INTEL_JSP_PRE_PROD_PMC, 0 }; diff --git a/src/soc/intel/common/block/sata/sata.c b/src/soc/intel/common/block/sata/sata.c index 13ac32e766..0f26262db2 100644 --- a/src/soc/intel/common/block/sata/sata.c +++ b/src/soc/intel/common/block/sata/sata.c @@ -100,6 +100,7 @@ static const unsigned short pci_device_ids[] = { PCI_DEVICE_ID_INTEL_TGP_SATA, PCI_DEVICE_ID_INTEL_TGP_PREMIUM_SATA, PCI_DEVICE_ID_INTEL_TGP_COMPAT_SATA, + PCI_DEVICE_ID_INTEL_JSP_PRE_PROD_SATA, 0 }; diff --git a/src/soc/intel/common/block/scs/sd.c b/src/soc/intel/common/block/scs/sd.c index 2794a3b82e..e94e4e97c4 100644 --- a/src/soc/intel/common/block/scs/sd.c +++ b/src/soc/intel/common/block/scs/sd.c @@ -73,6 +73,7 @@ static const unsigned short pci_device_ids[] = { PCI_DEVICE_ID_INTEL_CNP_H_SD, PCI_DEVICE_ID_INTEL_ICL_SD, PCI_DEVICE_ID_INTEL_CMP_SD, + PCI_DEVICE_ID_INTEL_JSP_PRE_PROD_SD, 0 }; diff --git a/src/soc/intel/common/block/smbus/smbus.c b/src/soc/intel/common/block/smbus/smbus.c index d7114e4356..c9a6b170bd 100644 --- a/src/soc/intel/common/block/smbus/smbus.c +++ b/src/soc/intel/common/block/smbus/smbus.c @@ -96,6 +96,7 @@ static const unsigned short pci_device_ids[] = { PCI_DEVICE_ID_INTEL_ICP_LP_SMBUS, PCI_DEVICE_ID_INTEL_CMP_SMBUS, PCI_DEVICE_ID_INTEL_TGP_LP_SMBUS, + PCI_DEVICE_ID_INTEL_JSP_PRE_PROD_SMBUS, 0 }; diff --git a/src/soc/intel/common/block/spi/spi.c b/src/soc/intel/common/block/spi/spi.c index 3c77cc4c81..eedde756f0 100644 --- a/src/soc/intel/common/block/spi/spi.c +++ b/src/soc/intel/common/block/spi/spi.c @@ -89,6 +89,10 @@ static const unsigned short pci_device_ids[] = { PCI_DEVICE_ID_INTEL_TGP_GSPI4, PCI_DEVICE_ID_INTEL_TGP_GSPI5, PCI_DEVICE_ID_INTEL_TGP_GSPI6, + PCI_DEVICE_ID_INTEL_JSP_PRE_PROD_SPI0, + PCI_DEVICE_ID_INTEL_JSP_PRE_PROD_SPI1, + PCI_DEVICE_ID_INTEL_JSP_PRE_PROD_SPI2, + PCI_DEVICE_ID_INTEL_JSP_PRE_PROD_HWSEQ_SPI, 0 }; diff --git a/src/soc/intel/common/block/sram/sram.c b/src/soc/intel/common/block/sram/sram.c index 47ba28f755..9e44fa3178 100644 --- a/src/soc/intel/common/block/sram/sram.c +++ b/src/soc/intel/common/block/sram/sram.c @@ -52,6 +52,7 @@ static const unsigned short pci_device_ids[] = { PCI_DEVICE_ID_INTEL_ICL_SRAM, PCI_DEVICE_ID_INTEL_CMP_SRAM, PCI_DEVICE_ID_INTEL_TGL_SRAM, + PCI_DEVICE_ID_INTEL_JSP_PRE_PROD_SRAM, 0, }; diff --git a/src/soc/intel/common/block/systemagent/systemagent.c b/src/soc/intel/common/block/systemagent/systemagent.c index b3657069f1..2019ef6d5b 100644 --- a/src/soc/intel/common/block/systemagent/systemagent.c +++ b/src/soc/intel/common/block/systemagent/systemagent.c @@ -367,6 +367,7 @@ static const unsigned short systemagent_ids[] = { PCI_DEVICE_ID_INTEL_TGL_ID_U, PCI_DEVICE_ID_INTEL_TGL_ID_U_1, PCI_DEVICE_ID_INTEL_TGL_ID_Y, + PCI_DEVICE_ID_INTEL_JSL_PRE_PROD, 0 }; diff --git a/src/soc/intel/common/block/uart/uart.c b/src/soc/intel/common/block/uart/uart.c index 718eaca96b..405351691d 100644 --- a/src/soc/intel/common/block/uart/uart.c +++ b/src/soc/intel/common/block/uart/uart.c @@ -278,6 +278,9 @@ static const unsigned short pci_device_ids[] = { PCI_DEVICE_ID_INTEL_TGP_UART0, PCI_DEVICE_ID_INTEL_TGP_UART1, PCI_DEVICE_ID_INTEL_TGP_UART2, + PCI_DEVICE_ID_INTEL_JSP_PRE_PROD_UART0, + PCI_DEVICE_ID_INTEL_JSP_PRE_PROD_UART1, + PCI_DEVICE_ID_INTEL_JSP_PRE_PROD_UART2, 0, }; diff --git a/src/soc/intel/common/block/xhci/xhci.c b/src/soc/intel/common/block/xhci/xhci.c index 5930e23081..af4d132194 100644 --- a/src/soc/intel/common/block/xhci/xhci.c +++ b/src/soc/intel/common/block/xhci/xhci.c @@ -132,6 +132,7 @@ static const unsigned short pci_device_ids[] = { PCI_DEVICE_ID_INTEL_ICP_LP_XHCI, PCI_DEVICE_ID_INTEL_CMP_LP_XHCI, PCI_DEVICE_ID_INTEL_TGP_LP_XHCI, + PCI_DEVICE_ID_INTEL_JSP_PRE_PROD_XHCI, 0 }; diff --git a/src/soc/intel/tigerlake/bootblock/report_platform.c b/src/soc/intel/tigerlake/bootblock/report_platform.c index 41061ee03b..3d856a5039 100644 --- a/src/soc/intel/tigerlake/bootblock/report_platform.c +++ b/src/soc/intel/tigerlake/bootblock/report_platform.c @@ -47,6 +47,7 @@ static struct { { PCI_DEVICE_ID_INTEL_TGL_ID_U, "Tigerlake-U-4-2" }, { PCI_DEVICE_ID_INTEL_TGL_ID_U_1, "Tigerlake-U-4-3e" }, { PCI_DEVICE_ID_INTEL_TGL_ID_Y, "Tigerlake-Y-4-2" }, + { PCI_DEVICE_ID_INTEL_JSL_PRE_PROD, "Jasperlake Pre Prod" }, }; static struct { @@ -85,6 +86,8 @@ static struct { { PCI_DEVICE_ID_INTEL_TGP_ESPI_24, "Tigerlake-Base SKU" }, { PCI_DEVICE_ID_INTEL_TGP_ESPI_25, "Tigerlake-Base SKU" }, { PCI_DEVICE_ID_INTEL_TGP_ESPI_26, "Tigerlake-Base SKU" }, + { PCI_DEVICE_ID_INTEL_JSP_PRE_PROD_ESPI_1, "Jasperlake Pre Prod" }, + { PCI_DEVICE_ID_INTEL_JSP_PRE_PROD_ESPI_2, "Jasperlake Pre Prod" }, }; static struct { @@ -95,6 +98,7 @@ static struct { { PCI_DEVICE_ID_INTEL_TGL_GT2_ULT, "Tigerlake U GT2" }, { PCI_DEVICE_ID_INTEL_TGL_GT2_ULX, "Tigerlake Y GT2" }, { PCI_DEVICE_ID_INTEL_TGL_GT3_ULT, "Tigerlake U GT3" }, + { PCI_DEVICE_ID_INTEL_JSL_PRE_PROD_GT0, "Jasperlake Pre Prod GT0" }, }; static inline uint8_t get_dev_revision(pci_devfn_t dev) From 18aa6fe26123c5fa4bc5439e4eb237b1cc5d86e4 Mon Sep 17 00:00:00 2001 From: Frans Hendriks Date: Fri, 6 Dec 2019 16:00:20 +0100 Subject: [PATCH 0611/1242] mb/{facebook/portwell}: Remove ITE8258_CMD_PORT ITE8258_CMD_PORT is used in com_init.c only. Replace ITE8258_CMD_PORT by fixed value in the c file. ITE8258_DATA_PORT is removed as this isn't used. BUG=N/A TEST=build Change-Id: I401da3f127db9e65763fd8d115eb274fbadbefbe Signed-off-by: Wim Vervoorn Reviewed-on: https://review.coreboot.org/c/coreboot/+/37609 Tested-by: build bot (Jenkins) Reviewed-by: Frans Hendriks --- src/mainboard/facebook/fbg1701/com_init.c | 3 +-- src/mainboard/facebook/fbg1701/onboard.h | 3 --- src/mainboard/portwell/m107/com_init.c | 3 +-- src/mainboard/portwell/m107/onboard.h | 2 -- 4 files changed, 2 insertions(+), 9 deletions(-) diff --git a/src/mainboard/facebook/fbg1701/com_init.c b/src/mainboard/facebook/fbg1701/com_init.c index f19aba311c..fc640dd236 100644 --- a/src/mainboard/facebook/fbg1701/com_init.c +++ b/src/mainboard/facebook/fbg1701/com_init.c @@ -17,9 +17,8 @@ #include #include -#include "onboard.h" -#define SERIAL_DEV PNP_DEV(ITE8528_CMD_PORT, 1) /* ITE8528 UART1 */ +#define SERIAL_DEV PNP_DEV(0x6E, 1) /* ITE8528 UART1 */ void bootblock_mainboard_early_init(void) { diff --git a/src/mainboard/facebook/fbg1701/onboard.h b/src/mainboard/facebook/fbg1701/onboard.h index c22a63a04a..6e094ab6e9 100644 --- a/src/mainboard/facebook/fbg1701/onboard.h +++ b/src/mainboard/facebook/fbg1701/onboard.h @@ -21,9 +21,6 @@ /* SD CARD gpio */ #define SDCARD_CD 81 /* Not used */ -#define ITE8528_CMD_PORT 0x6E -#define ITE8528_DATA_PORT 0x6F - /* Define the items to be measured or verified */ #define FSP (const char *)"fsp.bin" #define CMOS_LAYOUT (const char *)"cmos_layout.bin" diff --git a/src/mainboard/portwell/m107/com_init.c b/src/mainboard/portwell/m107/com_init.c index f19aba311c..fc640dd236 100644 --- a/src/mainboard/portwell/m107/com_init.c +++ b/src/mainboard/portwell/m107/com_init.c @@ -17,9 +17,8 @@ #include #include -#include "onboard.h" -#define SERIAL_DEV PNP_DEV(ITE8528_CMD_PORT, 1) /* ITE8528 UART1 */ +#define SERIAL_DEV PNP_DEV(0x6E, 1) /* ITE8528 UART1 */ void bootblock_mainboard_early_init(void) { diff --git a/src/mainboard/portwell/m107/onboard.h b/src/mainboard/portwell/m107/onboard.h index fd4e4d6516..3a5dee2f12 100644 --- a/src/mainboard/portwell/m107/onboard.h +++ b/src/mainboard/portwell/m107/onboard.h @@ -21,6 +21,4 @@ /* SD CARD gpio */ #define SDCARD_CD 81 /* Not used */ -#define ITE8528_CMD_PORT 0x6E -#define ITE8528_DATA_PORT 0x6F #endif From 9e052c2b6c4a30771ff282286bec5d78d4422c72 Mon Sep 17 00:00:00 2001 From: Joel Kitching Date: Mon, 9 Dec 2019 12:09:54 +0800 Subject: [PATCH 0612/1242] vboot: remove old vboot_fill_handoff function header This function was removed in CB:33535. BUG=b:124141368 TEST=make clean && make runtests BRANCH=none Change-Id: Ifded75319c92dcbb4befbb3fbecc1cd2df8a9ad0 Signed-off-by: Joel Kitching Reviewed-on: https://review.coreboot.org/c/coreboot/+/37588 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh Reviewed-by: Julius Werner --- src/security/vboot/misc.h | 5 ----- 1 file changed, 5 deletions(-) diff --git a/src/security/vboot/misc.h b/src/security/vboot/misc.h index d03e76eea7..1fda8b42b2 100644 --- a/src/security/vboot/misc.h +++ b/src/security/vboot/misc.h @@ -52,11 +52,6 @@ static inline bool vboot_is_gbb_flag_set(enum vb2_gbb_flag flag) int vboot_locate_firmware(const struct vb2_context *ctx, struct region_device *fw); -/* - * Source: security/vboot/vboot_handoff.c - */ -void vboot_fill_handoff(void); - /* * Source: security/vboot/bootmode.c */ From 12520134f17b55ac7f695d1d9384e33a99b18def Mon Sep 17 00:00:00 2001 From: Elyes HAOUAS Date: Sun, 8 Dec 2019 14:05:32 +0100 Subject: [PATCH 0613/1242] mb/google/daisy: Move 'PMIC_BUS' to Kconfig Change-Id: If40fa38e5b249452a6dacf4a4045b6bd00c27cfa Signed-off-by: Elyes HAOUAS Reviewed-on: https://review.coreboot.org/c/coreboot/+/37580 Tested-by: build bot (Jenkins) Reviewed-by: Julius Werner --- src/mainboard/google/daisy/Kconfig | 4 ++++ src/mainboard/google/daisy/romstage.c | 22 ++++++++++------------ 2 files changed, 14 insertions(+), 12 deletions(-) diff --git a/src/mainboard/google/daisy/Kconfig b/src/mainboard/google/daisy/Kconfig index f15bd9b864..61bb80b3a8 100644 --- a/src/mainboard/google/daisy/Kconfig +++ b/src/mainboard/google/daisy/Kconfig @@ -58,4 +58,8 @@ config UART_FOR_CONSOLE int default 3 +config PMIC_BUS + int + default 0 + endif # BOARD_GOOGLE_DAISY diff --git a/src/mainboard/google/daisy/romstage.c b/src/mainboard/google/daisy/romstage.c index 838a6c70d7..08570249e8 100644 --- a/src/mainboard/google/daisy/romstage.c +++ b/src/mainboard/google/daisy/romstage.c @@ -36,8 +36,6 @@ #include "exynos5250.h" -#define PMIC_BUS 0 - static void setup_power(int is_resume) { int error = 0; @@ -63,26 +61,26 @@ static void setup_power(int is_resume) * * Disable Coin BATT Charging */ - error = max77686_disable_backup_batt(PMIC_BUS); + error = max77686_disable_backup_batt(CONFIG_PMIC_BUS); - error |= max77686_volsetting(PMIC_BUS, PMIC_BUCK2, VDD_ARM_MV, + error |= max77686_volsetting(CONFIG_PMIC_BUS, PMIC_BUCK2, VDD_ARM_MV, REG_ENABLE, MAX77686_MV); - error |= max77686_volsetting(PMIC_BUS, PMIC_BUCK3, VDD_INT_UV, + error |= max77686_volsetting(CONFIG_PMIC_BUS, PMIC_BUCK3, VDD_INT_UV, REG_ENABLE, MAX77686_UV); - error |= max77686_volsetting(PMIC_BUS, PMIC_BUCK1, VDD_MIF_MV, + error |= max77686_volsetting(CONFIG_PMIC_BUS, PMIC_BUCK1, VDD_MIF_MV, REG_ENABLE, MAX77686_MV); - error |= max77686_volsetting(PMIC_BUS, PMIC_BUCK4, VDD_G3D_MV, + error |= max77686_volsetting(CONFIG_PMIC_BUS, PMIC_BUCK4, VDD_G3D_MV, REG_ENABLE, MAX77686_MV); - error |= max77686_volsetting(PMIC_BUS, PMIC_LDO2, VDD_LDO2_MV, + error |= max77686_volsetting(CONFIG_PMIC_BUS, PMIC_LDO2, VDD_LDO2_MV, REG_ENABLE, MAX77686_MV); - error |= max77686_volsetting(PMIC_BUS, PMIC_LDO3, VDD_LDO3_MV, + error |= max77686_volsetting(CONFIG_PMIC_BUS, PMIC_LDO3, VDD_LDO3_MV, REG_ENABLE, MAX77686_MV); - error |= max77686_volsetting(PMIC_BUS, PMIC_LDO5, VDD_LDO5_MV, + error |= max77686_volsetting(CONFIG_PMIC_BUS, PMIC_LDO5, VDD_LDO5_MV, REG_ENABLE, MAX77686_MV); - error |= max77686_volsetting(PMIC_BUS, PMIC_LDO10, VDD_LDO10_MV, + error |= max77686_volsetting(CONFIG_PMIC_BUS, PMIC_LDO10, VDD_LDO10_MV, REG_ENABLE, MAX77686_MV); - error |= max77686_enable_32khz_cp(PMIC_BUS); + error |= max77686_enable_32khz_cp(CONFIG_PMIC_BUS); if (error) { printk(BIOS_CRIT, "%s: PMIC error: %#x\n", __func__, error); From 9484792ad1470117aeb9bd234adc86f7e9087b0b Mon Sep 17 00:00:00 2001 From: John Su Date: Fri, 15 Nov 2019 14:42:07 +0800 Subject: [PATCH 0614/1242] mb/google/drallion/variants/drallion: Update thermal configuration for DPTF Follow thermal table for first tuning. BUG=b:144464314 TEST=Built and tested on drallion Change-Id: I4546622cdc6efb2bf2eb973cfc5c6f22c40cc6ef Signed-off-by: John Su Reviewed-on: https://review.coreboot.org/c/coreboot/+/36860 Reviewed-by: Sumeet R Pawnikar Reviewed-by: EricR Lai Tested-by: build bot (Jenkins) --- .../drallion/include/variant/acpi/dptf.asl | 36 +++++++++---------- 1 file changed, 18 insertions(+), 18 deletions(-) diff --git a/src/mainboard/google/drallion/variants/drallion/include/variant/acpi/dptf.asl b/src/mainboard/google/drallion/variants/drallion/include/variant/acpi/dptf.asl index 73e1decc1b..4ecdf1a67e 100644 --- a/src/mainboard/google/drallion/variants/drallion/include/variant/acpi/dptf.asl +++ b/src/mainboard/google/drallion/variants/drallion/include/variant/acpi/dptf.asl @@ -13,42 +13,42 @@ * GNU General Public License for more details. */ -#define DPTF_CPU_PASSIVE 98 -#define DPTF_CPU_CRITICAL 108 +#define DPTF_CPU_PASSIVE 99 +#define DPTF_CPU_CRITICAL 127 /* Skin Sensor for CPU VR temperature monitor */ #define DPTF_TSR0_SENSOR_ID 1 #define DPTF_TSR0_SENSOR_NAME "Skin" -#define DPTF_TSR0_PASSIVE 55 -#define DPTF_TSR0_CRITICAL 100 +#define DPTF_TSR0_PASSIVE 64 +#define DPTF_TSR0_CRITICAL 127 /* Memory Sensor for DDR temperature monitor */ #define DPTF_TSR1_SENSOR_ID 2 #define DPTF_TSR1_SENSOR_NAME "DDR" -#define DPTF_TSR1_PASSIVE 53 -#define DPTF_TSR1_CRITICAL 100 +#define DPTF_TSR1_PASSIVE 54 +#define DPTF_TSR1_CRITICAL 127 /* M.2 Sensor for Ambient temperature monitor */ #define DPTF_TSR2_SENSOR_ID 3 #define DPTF_TSR2_SENSOR_NAME "Ambient" -#define DPTF_TSR2_PASSIVE 38 -#define DPTF_TSR2_CRITICAL 93 +#define DPTF_TSR2_PASSIVE 40 +#define DPTF_TSR2_CRITICAL 127 #undef DPTF_ENABLE_FAN_CONTROL #undef DPTF_ENABLE_CHARGER Name (DTRT, Package () { /* CPU Throttle Effect on CPU */ - Package () { \_SB.PCI0.TCPU, \_SB.PCI0.TCPU, 500, 100, 0, 0, 0, 0 }, + Package () { \_SB.PCI0.TCPU, \_SB.PCI0.TCPU, 250, 10, 0, 0, 0, 0 }, /* CPU Throttle Effect on Skin (TSR0) */ - Package () { \_SB.PCI0.TCPU, \_SB.DPTF.TSR0, 400, 40, 0, 0, 0, 0 }, + Package () { \_SB.PCI0.TCPU, \_SB.DPTF.TSR0, 250, 10, 0, 0, 0, 0 }, /* CPU Throttle Effect on DDR (TSR1) */ - Package () { \_SB.PCI0.TCPU, \_SB.DPTF.TSR1, 300, 50, 2, 0, 0, 0 }, + Package () { \_SB.PCI0.TCPU, \_SB.DPTF.TSR1, 250, 10, 2, 0, 0, 0 }, /* CPU Throttle Effect on Ambient (TSR2) */ - Package () { \_SB.PCI0.TCPU, \_SB.DPTF.TSR2, 1000, 100, 1, 0, 0, 0 }, + Package () { \_SB.PCI0.TCPU, \_SB.DPTF.TSR2, 250, 10, 1, 0, 0, 0 }, }) Name (MPPC, Package () @@ -56,18 +56,18 @@ Name (MPPC, Package () 0x2, /* Revision */ Package () { /* Power Limit 1 */ 0, /* PowerLimitIndex, 0 for Power Limit 1 */ - 3000, /* PowerLimitMinimum */ - 21000, /* PowerLimitMaximum */ - 28000, /* TimeWindowMinimum */ - 28000, /* TimeWindowMaximum */ + 4000, /* PowerLimitMinimum */ + 15000, /* PowerLimitMaximum */ + 100000, /* TimeWindowMinimum */ + 100000, /* TimeWindowMaximum */ 100 /* StepSize */ }, Package () { /* Power Limit 2 */ 1, /* PowerLimitIndex, 1 for Power Limit 2 */ 15000, /* PowerLimitMinimum */ 51000, /* PowerLimitMaximum */ - 28000, /* TimeWindowMinimum */ - 28000, /* TimeWindowMaximum */ + 280000, /* TimeWindowMinimum */ + 280000, /* TimeWindowMaximum */ 100 /* StepSize */ } }) From 8d98d80e5330f465c315a7aade4b754b8c6c79b3 Mon Sep 17 00:00:00 2001 From: Frans Hendriks Date: Mon, 9 Dec 2019 10:02:26 +0100 Subject: [PATCH 0615/1242] mb/portwell/m107/devicetree.cb: Use IGD_MEMSIZE_32MB Make code more readable. Replace 1 by IGD_MEMSIZE_32MB for PcdIgdDvmtS0PreAlloc. BUG=N/A TEST=build Change-Id: I5d84e575935e9e60610e1805e1402f290672b114 Signed-off-by: Wim Vervoorn Reviewed-on: https://review.coreboot.org/c/coreboot/+/37616 Tested-by: build bot (Jenkins) Reviewed-by: Frans Hendriks --- src/mainboard/portwell/m107/devicetree.cb | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/mainboard/portwell/m107/devicetree.cb b/src/mainboard/portwell/m107/devicetree.cb index 9a27fed8cf..f68b071a12 100644 --- a/src/mainboard/portwell/m107/devicetree.cb +++ b/src/mainboard/portwell/m107/devicetree.cb @@ -9,7 +9,7 @@ chip soc/intel/braswell register "PcdMrcInitMmioSize" = "0x0800" register "PcdMrcInitSpdAddr1" = "0xa0" register "PcdMrcInitSpdAddr2" = "0xa2" - register "PcdIgdDvmt50PreAlloc" = "1" + register "PcdIgdDvmt50PreAlloc" = "IGD_MEMSIZE_32MB" register "PcdApertureSize" = "2" register "PcdGttSize" = "1" register "PcdDvfsEnable" = "0" From c8e1c0d3952cb678203f6c62047ac4bee9809748 Mon Sep 17 00:00:00 2001 From: Frans Hendriks Date: Mon, 9 Dec 2019 08:43:42 +0100 Subject: [PATCH 0616/1242] mb/facebook/fbg1701/acpi/ec.asl: Remove header File contains header only. Remove header leaving an empty file. BUG=N/A TEST=build Change-Id: I8b1c6b38bd7936cc7af11c13744325bed23a6e83 Signed-off-by: Wim Vervoorn Reviewed-on: https://review.coreboot.org/c/coreboot/+/37613 Tested-by: build bot (Jenkins) Reviewed-by: Frans Hendriks --- src/mainboard/facebook/fbg1701/acpi/ec.asl | 14 -------------- 1 file changed, 14 deletions(-) diff --git a/src/mainboard/facebook/fbg1701/acpi/ec.asl b/src/mainboard/facebook/fbg1701/acpi/ec.asl index 3c9d818bae..e69de29bb2 100644 --- a/src/mainboard/facebook/fbg1701/acpi/ec.asl +++ b/src/mainboard/facebook/fbg1701/acpi/ec.asl @@ -1,14 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2018 Eltan B.V. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ From c1c5354e45a0a369ffa7371468bef05ba552909f Mon Sep 17 00:00:00 2001 From: Frans Hendriks Date: Fri, 6 Dec 2019 16:04:50 +0100 Subject: [PATCH 0617/1242] mb/{facebook/portwell}: Define SDCARD_CD in dsdt.asl SDCARD_CD is defined in onboard.h but required in ASL only, move this define to dsdt.asl. Removed the onboard.h file from the ASL files that don use it. BUG=N/A TEST=build Change-Id: I35b75e0ae2e2bc4ce143aaec6df6016774676095 Signed-off-by: Wim Vervoorn Reviewed-on: https://review.coreboot.org/c/coreboot/+/37610 Tested-by: build bot (Jenkins) Reviewed-by: Frans Hendriks --- src/mainboard/facebook/fbg1701/acpi/mainboard.asl | 2 -- src/mainboard/facebook/fbg1701/acpi/superio.asl | 3 --- src/mainboard/facebook/fbg1701/dsdt.asl | 2 ++ src/mainboard/facebook/fbg1701/onboard.h | 3 --- src/mainboard/portwell/m107/acpi/superio.asl | 2 -- src/mainboard/portwell/m107/dsdt.asl | 2 ++ 6 files changed, 4 insertions(+), 10 deletions(-) diff --git a/src/mainboard/facebook/fbg1701/acpi/mainboard.asl b/src/mainboard/facebook/fbg1701/acpi/mainboard.asl index 9575748446..af79bd76af 100644 --- a/src/mainboard/facebook/fbg1701/acpi/mainboard.asl +++ b/src/mainboard/facebook/fbg1701/acpi/mainboard.asl @@ -16,8 +16,6 @@ * GNU General Public License for more details. */ -#include "onboard.h" - Scope (\_SB) { Device (PWRB) diff --git a/src/mainboard/facebook/fbg1701/acpi/superio.asl b/src/mainboard/facebook/fbg1701/acpi/superio.asl index bdaa912fd7..4fa6772128 100644 --- a/src/mainboard/facebook/fbg1701/acpi/superio.asl +++ b/src/mainboard/facebook/fbg1701/acpi/superio.asl @@ -15,9 +15,6 @@ * GNU General Public License for more details. */ -/* mainboard configuration */ -#include "onboard.h" - Device (COM1) { Name (_HID, EISAID ("PNP0501")) Name (_UID, 1) diff --git a/src/mainboard/facebook/fbg1701/dsdt.asl b/src/mainboard/facebook/fbg1701/dsdt.asl index 4eea7b93f4..518e249197 100644 --- a/src/mainboard/facebook/fbg1701/dsdt.asl +++ b/src/mainboard/facebook/fbg1701/dsdt.asl @@ -18,6 +18,8 @@ #include +#define SDCARD_CD 81 /* Not used */ + DefinitionBlock( "dsdt.aml", "DSDT", diff --git a/src/mainboard/facebook/fbg1701/onboard.h b/src/mainboard/facebook/fbg1701/onboard.h index 6e094ab6e9..715f76a39d 100644 --- a/src/mainboard/facebook/fbg1701/onboard.h +++ b/src/mainboard/facebook/fbg1701/onboard.h @@ -18,9 +18,6 @@ #ifndef ONBOARD_H #define ONBOARD_H -/* SD CARD gpio */ -#define SDCARD_CD 81 /* Not used */ - /* Define the items to be measured or verified */ #define FSP (const char *)"fsp.bin" #define CMOS_LAYOUT (const char *)"cmos_layout.bin" diff --git a/src/mainboard/portwell/m107/acpi/superio.asl b/src/mainboard/portwell/m107/acpi/superio.asl index e411f721dc..309a26bb13 100644 --- a/src/mainboard/portwell/m107/acpi/superio.asl +++ b/src/mainboard/portwell/m107/acpi/superio.asl @@ -15,8 +15,6 @@ * GNU General Public License for more details. */ -/* mainboard configuration */ -#include "onboard.h" Device (COM1) { Name (_HID, EISAID ("PNP0501")) diff --git a/src/mainboard/portwell/m107/dsdt.asl b/src/mainboard/portwell/m107/dsdt.asl index 4eea7b93f4..518e249197 100644 --- a/src/mainboard/portwell/m107/dsdt.asl +++ b/src/mainboard/portwell/m107/dsdt.asl @@ -18,6 +18,8 @@ #include +#define SDCARD_CD 81 /* Not used */ + DefinitionBlock( "dsdt.aml", "DSDT", From 106abb82fe122aceb7656641b29a7d676f260c48 Mon Sep 17 00:00:00 2001 From: Frans Hendriks Date: Fri, 6 Dec 2019 16:06:39 +0100 Subject: [PATCH 0618/1242] mb/portwell/m107/acpi/superio.asl: Correct indent Remove the additional tabs on all lines. BUG=N/A TEST=build Change-Id: I02b1314fe2ae89da3659b198c12df9c30c8a039d Signed-off-by: Wim Vervoorn Reviewed-on: https://review.coreboot.org/c/coreboot/+/37611 Tested-by: build bot (Jenkins) Reviewed-by: Frans Hendriks --- src/mainboard/portwell/m107/acpi/superio.asl | 41 ++++++++++---------- 1 file changed, 20 insertions(+), 21 deletions(-) diff --git a/src/mainboard/portwell/m107/acpi/superio.asl b/src/mainboard/portwell/m107/acpi/superio.asl index 309a26bb13..aecd174fc8 100644 --- a/src/mainboard/portwell/m107/acpi/superio.asl +++ b/src/mainboard/portwell/m107/acpi/superio.asl @@ -15,30 +15,29 @@ * GNU General Public License for more details. */ +Device (COM1) { + Name (_HID, EISAID ("PNP0501")) + Name (_UID, 1) - Device (COM1) { - Name (_HID, EISAID ("PNP0501")) - Name (_UID, 1) + Method (_STA, 0, NotSerialized) + { + Return (0x0F) + } - Method (_STA, 0, NotSerialized) - { - Return (0x0F) - } + Name (_CRS, ResourceTemplate () + { + FixedIO (0x03F8, 0x08) + FixedIO (0x6E, 0x02) + IRQNoFlags () {4} + }) - Name (_CRS, ResourceTemplate () - { + Name (_PRS, ResourceTemplate () + { + StartDependentFn (0, 0) { FixedIO (0x03F8, 0x08) FixedIO (0x6E, 0x02) IRQNoFlags () {4} - }) - - Name (_PRS, ResourceTemplate () - { - StartDependentFn (0, 0) { - FixedIO (0x03F8, 0x08) - FixedIO (0x6E, 0x02) - IRQNoFlags () {4} - } - EndDependentFn () - }) - } + } + EndDependentFn () + }) +} From 42174235ba6a7cfac8243a4c2aedb1271a4659fe Mon Sep 17 00:00:00 2001 From: Wisley Chen Date: Mon, 9 Dec 2019 19:14:13 +0800 Subject: [PATCH 0619/1242] mb/goog/hatch/var/dratini: Tune i2c frequency to 400 KHz Tuning i2c frequency for dratini: I2C0: 396 KHz I2C1: 398 KHz I2C3: unused I2C4: 394 KHz BUG=b:145891557 BRANCH=hatch TEST=emerge-hatch coreboot chromeos-bootimage Change-Id: I1431554fbce5f3ce113ef1a934e39448e7ba321c Signed-off-by: Wisley Chen Reviewed-on: https://review.coreboot.org/c/coreboot/+/37605 Reviewed-by: Paul Fagerburg Reviewed-by: Tim Wawrzynczak Tested-by: build bot (Jenkins) --- .../google/hatch/variants/dratini/overridetree.cb | 9 ++++++--- 1 file changed, 6 insertions(+), 3 deletions(-) diff --git a/src/mainboard/google/hatch/variants/dratini/overridetree.cb b/src/mainboard/google/hatch/variants/dratini/overridetree.cb index 28b18b8b7f..564a14d93c 100644 --- a/src/mainboard/google/hatch/variants/dratini/overridetree.cb +++ b/src/mainboard/google/hatch/variants/dratini/overridetree.cb @@ -35,15 +35,18 @@ chip soc/intel/cannonlake }, .i2c[0] = { .speed = I2C_SPEED_FAST, + .rise_time_ns = 50, + .fall_time_ns = 15, }, .i2c[1] = { .speed = I2C_SPEED_FAST, - }, - .i2c[3] = { - .speed = I2C_SPEED_FAST, + .rise_time_ns = 60, + .fall_time_ns = 25, }, .i2c[4] = { .speed = I2C_SPEED_FAST, + .rise_time_ns = 60, + .fall_time_ns = 60, }, }" From a7ddf4cdb050ba8576a8cfb6e0b3bccec9ab61aa Mon Sep 17 00:00:00 2001 From: Frans Hendriks Date: Fri, 6 Dec 2019 16:08:54 +0100 Subject: [PATCH 0620/1242] mb/portwell/m107/fadt.c Use get_apic_table_revision Fixed value of ACPI_FADT_REV_ACPI_2_0 is replaced by get_acpi_table_revision(). BUG=N/A TEST=build Change-Id: I95b0d886b73f94bc880c0e3e7d512211d2d33e21 Signed-off-by: Wim Vervoorn Reviewed-on: https://review.coreboot.org/c/coreboot/+/37612 Tested-by: build bot (Jenkins) Reviewed-by: Frans Hendriks --- src/mainboard/portwell/m107/fadt.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/mainboard/portwell/m107/fadt.c b/src/mainboard/portwell/m107/fadt.c index 82986f63b1..544d24ba55 100644 --- a/src/mainboard/portwell/m107/fadt.c +++ b/src/mainboard/portwell/m107/fadt.c @@ -25,7 +25,7 @@ void acpi_create_fadt(acpi_fadt_t *fadt, acpi_facs_t *facs, void *dsdt) memset((void *) fadt, 0, sizeof(acpi_fadt_t)); memcpy(header->signature, "FACP", 4); header->length = sizeof(acpi_fadt_t); - header->revision = ACPI_FADT_REV_ACPI_2_0; + header->revision = get_acpi_table_revision(FADT); memcpy(header->oem_id, OEM_ID, 6); memcpy(header->oem_table_id, ACPI_TABLE_CREATOR, 8); memcpy(header->asl_compiler_id, ASLC, 4); From ddb4b0d576ce8a7a8f36ce8a8ebcfb871c11b18b Mon Sep 17 00:00:00 2001 From: Aamir Bohra Date: Fri, 6 Dec 2019 19:51:39 +0530 Subject: [PATCH 0621/1242] soc/intel/Kconfig: Load Tiger Lake SOC Kconfig Change-Id: I25463f1b7b5d8242da3decf3e7a7ca54c699d467 Signed-off-by: Aamir Bohra Reviewed-on: https://review.coreboot.org/c/coreboot/+/37554 Reviewed-by: Nico Huber Reviewed-by: Wonkyu Kim Reviewed-by: Furquan Shaikh Reviewed-by: Maulik V Vaghela Tested-by: build bot (Jenkins) --- src/soc/intel/Kconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/src/soc/intel/Kconfig b/src/soc/intel/Kconfig index 1eebeb61fb..e8935b9fd5 100644 --- a/src/soc/intel/Kconfig +++ b/src/soc/intel/Kconfig @@ -8,6 +8,7 @@ source "src/soc/intel/denverton_ns/Kconfig" source "src/soc/intel/quark/Kconfig" source "src/soc/intel/skylake/Kconfig" source "src/soc/intel/icelake/Kconfig" +source "src/soc/intel/tigerlake/Kconfig" # Load common config source "src/soc/intel/common/Kconfig" From e0cdaf0b19b68644b6c398be825f94327572e056 Mon Sep 17 00:00:00 2001 From: Aamir Bohra Date: Fri, 6 Dec 2019 19:37:37 +0530 Subject: [PATCH 0622/1242] soc/intel/tigerlake: add soc implementation for ETR address API Add soc_pmc_etr_addr function definition in tigerlake SOC code. The function is declared in common soc intel pmc driver. Change-Id: Icc471b16304c72a9341abdd9797ba3f8d0d3d1bc Signed-off-by: Aamir Bohra Reviewed-on: https://review.coreboot.org/c/coreboot/+/37555 Reviewed-by: Maulik V Vaghela Reviewed-by: Wonkyu Kim Reviewed-by: Ravishankar Sarawadi Reviewed-by: Karthik Ramasubramanian Tested-by: build bot (Jenkins) --- src/soc/intel/tigerlake/pmutil.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/src/soc/intel/tigerlake/pmutil.c b/src/soc/intel/tigerlake/pmutil.c index 53f86097ee..c163dc2f12 100644 --- a/src/soc/intel/tigerlake/pmutil.c +++ b/src/soc/intel/tigerlake/pmutil.c @@ -177,6 +177,12 @@ uintptr_t soc_read_pmc_base(void) return (uintptr_t)pmc_mmio_regs(); } + +uint32_t *soc_pmc_etr_addr(void) +{ + return (uint32_t *)(soc_read_pmc_base() + ETR); +} + void soc_get_gpi_gpe_configs(uint8_t *dw0, uint8_t *dw1, uint8_t *dw2) { DEVTREE_CONST struct soc_intel_tigerlake_config *config; From 86da00db899c4c58df90b4270082007c871169c7 Mon Sep 17 00:00:00 2001 From: Aamir Bohra Date: Fri, 6 Dec 2019 19:57:36 +0530 Subject: [PATCH 0623/1242] soc/intel/tigerlake: Include soc common lpss header file Include soc common lpss header file to resolve build error due to missing soc_lpss_controllers_list declaration. Also remove console header since it is unused. Change-Id: I2b2c82fc7592120993bc483d3061803cf75c7335 Signed-off-by: Aamir Bohra Reviewed-on: https://review.coreboot.org/c/coreboot/+/37556 Reviewed-by: Frans Hendriks Reviewed-by: Maulik V Vaghela Reviewed-by: Karthik Ramasubramanian Tested-by: build bot (Jenkins) --- src/soc/intel/tigerlake/fsp_params.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/soc/intel/tigerlake/fsp_params.c b/src/soc/intel/tigerlake/fsp_params.c index 18985a6495..6fb2f9f597 100644 --- a/src/soc/intel/tigerlake/fsp_params.c +++ b/src/soc/intel/tigerlake/fsp_params.c @@ -13,8 +13,8 @@ * GNU General Public License for more details. */ -#include #include +#include #include static const pci_devfn_t serial_io_dev[] = { From 540a98001d05a7b780e415c34d14a97b14e44ac6 Mon Sep 17 00:00:00 2001 From: Julius Werner Date: Mon, 9 Dec 2019 13:03:29 -0800 Subject: [PATCH 0624/1242] printf: Automatically prefix %p with 0x According to the POSIX standard, %p is supposed to print a pointer "as if by %#x", meaning the "0x" prefix should automatically be prepended. All other implementations out there (glibc, Linux, even libpayload) do this, so we should make coreboot match. This patch changes vtxprintf() accordingly and removes any explicit instances of "0x%p" from existing format strings. How to handle zero padding is less clear: the official POSIX definition above technically says there should be no automatic zero padding, but in practice most other implementations seem to do it and I assume most programmers would prefer it. The way chosen here is to always zero-pad to 32 bits, even on a 64-bit system. The rationale for this is that even on 64-bit systems, coreboot always avoids using any memory above 4GB for itself, so in practice all pointers should fit in that range and padding everything to 64 bits would just hurt readability. Padding it this way also helps pointers that do exceed 4GB (e.g. prints from MMU config on some arm64 systems) stand out better from the others. Change-Id: I0171b52f7288abb40e3fc3c8b874aee14b9bdcd6 Signed-off-by: Julius Werner Reviewed-on: https://review.coreboot.org/c/coreboot/+/37626 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel Reviewed-by: Patrick Georgi Reviewed-by: David Guckian --- payloads/libpayload/arch/arm/virtual.c | 2 +- payloads/libpayload/arch/arm64/mmu.c | 2 +- payloads/libpayload/libcbfs/cbfs.c | 4 ++-- src/arch/x86/ioapic.c | 2 +- src/commonlib/storage/sdhci.c | 2 +- src/console/vtxprintf.c | 9 +++++---- src/device/dram/ddr3.c | 2 +- src/device/dram/ddr4.c | 2 +- src/drivers/elog/elog.c | 2 +- src/drivers/generic/ioapic/ioapic.c | 2 +- src/drivers/i2c/designware/dw_i2c.c | 2 +- src/drivers/intel/fsp1_1/fsp_util.c | 16 ++++++++-------- src/drivers/intel/fsp1_1/hob.c | 2 +- src/drivers/intel/fsp1_1/raminit.c | 16 ++++++++-------- src/drivers/intel/fsp1_1/ramstage.c | 6 +++--- src/drivers/intel/fsp1_1/romstage.c | 2 +- src/drivers/intel/fsp2_0/debug.c | 14 +++++++------- src/drivers/intel/fsp2_0/hob_display.c | 4 ++-- src/drivers/intel/fsp2_0/hob_verify.c | 2 +- src/drivers/intel/fsp2_0/temp_ram_exit.c | 2 +- src/drivers/intel/fsp2_0/upd_display.c | 2 +- src/drivers/spi/adesto.c | 2 +- src/drivers/spi/amic.c | 2 +- src/drivers/spi/atmel.c | 2 +- src/drivers/spi/eon.c | 2 +- src/drivers/spi/gigadevice.c | 2 +- src/drivers/spi/macronix.c | 2 +- src/drivers/spi/spansion.c | 2 +- src/drivers/spi/sst.c | 6 +++--- src/drivers/spi/stmicro.c | 2 +- src/drivers/spi/winbond.c | 2 +- src/drivers/xgi/common/xgi_coreboot.c | 4 ++-- src/lib/coreboot_table.c | 2 +- src/lib/imd.c | 2 +- src/lib/rmodule.c | 2 +- src/lib/selfboot.c | 14 +++++++------- src/lib/trace.c | 2 +- src/mainboard/google/cyan/spd/spd.c | 2 +- src/soc/amd/common/block/pi/def_callouts.c | 2 +- src/soc/amd/common/block/s3/s3_resume.c | 4 ++-- src/soc/amd/common/block/spi/fch_spi_flash.c | 2 +- src/soc/amd/common/block/spi/fch_spi_special.c | 2 +- src/soc/intel/braswell/southcluster.c | 2 +- src/soc/intel/common/mma.c | 2 +- src/soc/intel/denverton_ns/hob_mem.c | 2 +- src/soc/intel/quark/bootblock/bootblock.c | 2 +- src/soc/intel/quark/i2c.c | 2 +- src/soc/intel/quark/romstage/debug.c | 2 +- src/soc/intel/quark/romstage/fsp_params.c | 6 +++--- src/soc/qualcomm/ipq40xx/qup.c | 2 +- src/soc/qualcomm/qcs405/qup.c | 2 +- src/vendorcode/google/chromeos/ramoops.c | 2 +- 52 files changed, 92 insertions(+), 91 deletions(-) diff --git a/payloads/libpayload/arch/arm/virtual.c b/payloads/libpayload/arch/arm/virtual.c index acca057a8b..4337e28487 100644 --- a/payloads/libpayload/arch/arm/virtual.c +++ b/payloads/libpayload/arch/arm/virtual.c @@ -92,7 +92,7 @@ static void lpae_map_init(void) /* get work block address */ work_block = ALIGN_UP((uintptr_t)_end, 2*MiB); assert(work_block); - printf("Work block for LPAE mapping is @ 0x%p\n", (void *)work_block); + printf("Work block for LPAE mapping is @ %p\n", (void *)work_block); /* get the address of the 1st pmd from pgd[0] */ pgd = (pgd_t *)((uintptr_t)read_ttbr0() & PGD_MASK); diff --git a/payloads/libpayload/arch/arm64/mmu.c b/payloads/libpayload/arch/arm64/mmu.c index 556f52b610..d1dd5b0147 100644 --- a/payloads/libpayload/arch/arm64/mmu.c +++ b/payloads/libpayload/arch/arm64/mmu.c @@ -273,7 +273,7 @@ uint64_t mmu_init(struct mmu_ranges *mmu_ranges) max_tables = (TTB_DEFAULT_SIZE >> GRANULE_SIZE_SHIFT); free_idx = 1; - printf("Libpayload ARM64: TTB_BUFFER: 0x%p Max Tables: %d\n", + printf("Libpayload ARM64: TTB_BUFFER: %p Max Tables: %d\n", (void*)xlat_addr, max_tables); /* diff --git a/payloads/libpayload/libcbfs/cbfs.c b/payloads/libpayload/libcbfs/cbfs.c index d2d13eac8e..fda98b92bb 100644 --- a/payloads/libpayload/libcbfs/cbfs.c +++ b/payloads/libpayload/libcbfs/cbfs.c @@ -106,7 +106,7 @@ void * cbfs_load_stage(struct cbfs_media *media, const char *name) if (stage == NULL) return (void *) -1; - LOG("loading stage %s @ 0x%p (%d bytes), entry @ 0x%llx\n", + LOG("loading stage %s @ %p (%d bytes), entry @ 0x%llx\n", name, (void*)(uintptr_t) stage->load, stage->memlen, stage->entry); @@ -215,7 +215,7 @@ void *cbfs_simple_buffer_unmap(struct cbfs_simple_buffer *buffer, const void *address) { // TODO Add simple buffer management so we can free more than last // allocated one. - DEBUG("simple_buffer_unmap(address=0x%p): " + DEBUG("simple_buffer_unmap(address=%p): " "allocated=%zu, size=%zu, last_allocate=%zu\n", address, buffer->allocated, buffer->size, buffer->last_allocate); diff --git a/src/arch/x86/ioapic.c b/src/arch/x86/ioapic.c index bf2ba6b255..757f7ee0fd 100644 --- a/src/arch/x86/ioapic.c +++ b/src/arch/x86/ioapic.c @@ -73,7 +73,7 @@ void set_ioapic_id(void *ioapic_base, u8 ioapic_id) u32 bsp_lapicid = lapicid(); int i; - printk(BIOS_DEBUG, "IOAPIC: Initializing IOAPIC at 0x%p\n", + printk(BIOS_DEBUG, "IOAPIC: Initializing IOAPIC at %p\n", ioapic_base); printk(BIOS_DEBUG, "IOAPIC: Bootstrap Processor Local APIC = 0x%02x\n", bsp_lapicid); diff --git a/src/commonlib/storage/sdhci.c b/src/commonlib/storage/sdhci.c index 25c0d6f1eb..6d99508ced 100644 --- a/src/commonlib/storage/sdhci.c +++ b/src/commonlib/storage/sdhci.c @@ -722,7 +722,7 @@ static int sdhci_init(struct sdhci_ctrlr *sdhci_ctrlr) if (ctrlr->initialized) return 0; - sdhc_debug("SDHCI Controller Base Address: 0x%p\n", + sdhc_debug("SDHCI Controller Base Address: %p\n", sdhci_ctrlr->ioaddr); rv = sdhci_pre_init(sdhci_ctrlr); diff --git a/src/console/vtxprintf.c b/src/console/vtxprintf.c index 104f4eaeb3..4045543839 100644 --- a/src/console/vtxprintf.c +++ b/src/console/vtxprintf.c @@ -220,10 +220,11 @@ repeat: continue; case 'p': - if (field_width == -1) { - field_width = 2*sizeof(void *); - flags |= ZEROPAD; - } + /* even on 64-bit systems, coreboot only resides in the + low 4GB so pad pointers to 32-bit for readability. */ + if (field_width == -1 && precision == -1) + precision = 2*sizeof(uint32_t); + flags |= SPECIAL; count += number(tx_byte, (unsigned long) va_arg(args, void *), 16, field_width, precision, flags, data); diff --git a/src/device/dram/ddr3.c b/src/device/dram/ddr3.c index 3f0c0a703e..bef3c78497 100644 --- a/src/device/dram/ddr3.c +++ b/src/device/dram/ddr3.c @@ -531,7 +531,7 @@ enum cb_err spd_add_smbios17(const u8 channel, const u8 slot, if (!mem_info) { mem_info = cbmem_add(CBMEM_ID_MEMINFO, sizeof(*mem_info)); - printk(BIOS_DEBUG, "CBMEM entry for DIMM info: 0x%p\n", + printk(BIOS_DEBUG, "CBMEM entry for DIMM info: %p\n", mem_info); if (!mem_info) return CB_ERR; diff --git a/src/device/dram/ddr4.c b/src/device/dram/ddr4.c index 07f9decb74..4f7e10928c 100644 --- a/src/device/dram/ddr4.c +++ b/src/device/dram/ddr4.c @@ -207,7 +207,7 @@ enum cb_err spd_add_smbios17_ddr4(const u8 channel, const u8 slot, const u16 sel if (!mem_info) { mem_info = cbmem_add(CBMEM_ID_MEMINFO, sizeof(*mem_info)); - printk(BIOS_DEBUG, "CBMEM entry for DIMM info: 0x%p\n", mem_info); + printk(BIOS_DEBUG, "CBMEM entry for DIMM info: %p\n", mem_info); if (!mem_info) return CB_ERR; diff --git a/src/drivers/elog/elog.c b/src/drivers/elog/elog.c index 97a9c7fa79..5f11c0c63e 100644 --- a/src/drivers/elog/elog.c +++ b/src/drivers/elog/elog.c @@ -329,7 +329,7 @@ static void elog_nv_write(size_t offset, size_t size) address = rdev_mmap(rdev, offset, size); - elog_debug("%s(address=0x%p offset=0x%08zx size=%zu)\n", __func__, + elog_debug("%s(address=%p offset=0x%08zx size=%zu)\n", __func__, address, offset, size); if (address == NULL) diff --git a/src/drivers/generic/ioapic/ioapic.c b/src/drivers/generic/ioapic/ioapic.c index 74dd941cd7..b16f8c6c26 100644 --- a/src/drivers/generic/ioapic/ioapic.c +++ b/src/drivers/generic/ioapic/ioapic.c @@ -32,7 +32,7 @@ static void ioapic_init(struct device *dev) ioapic_base = config->base; ioapic_id = config->apicid; - printk(BIOS_DEBUG, "IOAPIC: Initializing IOAPIC at 0x%p\n", + printk(BIOS_DEBUG, "IOAPIC: Initializing IOAPIC at %p\n", ioapic_base); printk(BIOS_DEBUG, "IOAPIC: Bootstrap Processor Local APIC = 0x%02x\n", bsp_lapicid); diff --git a/src/drivers/i2c/designware/dw_i2c.c b/src/drivers/i2c/designware/dw_i2c.c index eb90387955..9eda827f30 100644 --- a/src/drivers/i2c/designware/dw_i2c.c +++ b/src/drivers/i2c/designware/dw_i2c.c @@ -743,7 +743,7 @@ int dw_i2c_init(unsigned int bus, const struct dw_i2c_bus_config *bcfg) /* Enable stop detection interrupt */ write32(®s->intr_mask, INTR_STAT_STOP_DET); - printk(BIOS_INFO, "DW I2C bus %u at 0x%p (%u KHz)\n", + printk(BIOS_INFO, "DW I2C bus %u at %p (%u KHz)\n", bus, regs, speed / KHz); return 0; diff --git a/src/drivers/intel/fsp1_1/fsp_util.c b/src/drivers/intel/fsp1_1/fsp_util.c index 2889f3f6fc..b1075ff2b5 100644 --- a/src/drivers/intel/fsp1_1/fsp_util.c +++ b/src/drivers/intel/fsp1_1/fsp_util.c @@ -102,22 +102,22 @@ void print_fsp_info(FSP_INFO_HEADER *fsp_header) (u8)(fsp_header->ImageRevision & 0xff)); #if CONFIG(DISPLAY_FSP_ENTRY_POINTS) printk(BIOS_SPEW, "FSP Entry Points:\n"); - printk(BIOS_SPEW, " 0x%p: Image Base\n", fsp_base); - printk(BIOS_SPEW, " 0x%p: TempRamInit\n", + printk(BIOS_SPEW, " %p: Image Base\n", fsp_base); + printk(BIOS_SPEW, " %p: TempRamInit\n", &fsp_base[fsp_header->TempRamInitEntryOffset]); - printk(BIOS_SPEW, " 0x%p: FspInit\n", + printk(BIOS_SPEW, " %p: FspInit\n", &fsp_base[fsp_header->FspInitEntryOffset]); if (fsp_header->HeaderRevision >= FSP_HEADER_REVISION_2) { - printk(BIOS_SPEW, " 0x%p: MemoryInit\n", + printk(BIOS_SPEW, " %p: MemoryInit\n", &fsp_base[fsp_header->FspMemoryInitEntryOffset]); - printk(BIOS_SPEW, " 0x%p: TempRamExit\n", + printk(BIOS_SPEW, " %p: TempRamExit\n", &fsp_base[fsp_header->TempRamExitEntryOffset]); - printk(BIOS_SPEW, " 0x%p: SiliconInit\n", + printk(BIOS_SPEW, " %p: SiliconInit\n", &fsp_base[fsp_header->FspSiliconInitEntryOffset]); } - printk(BIOS_SPEW, " 0x%p: NotifyPhase\n", + printk(BIOS_SPEW, " %p: NotifyPhase\n", &fsp_base[fsp_header->NotifyPhaseEntryOffset]); - printk(BIOS_SPEW, " 0x%p: Image End\n", + printk(BIOS_SPEW, " %p: Image End\n", &fsp_base[fsp_header->ImageSize]); #endif } diff --git a/src/drivers/intel/fsp1_1/hob.c b/src/drivers/intel/fsp1_1/hob.c index d6878e3780..679cdf8032 100644 --- a/src/drivers/intel/fsp1_1/hob.c +++ b/src/drivers/intel/fsp1_1/hob.c @@ -282,7 +282,7 @@ void print_hob_type_structure(u16 hob_type, void *hob_list_ptr) * the end of the HOB list */ printk(BIOS_DEBUG, "\n=== FSP HOB Data Structure ===\n"); - printk(BIOS_DEBUG, "0x%p: hob_list_ptr\n", hob_list_ptr); + printk(BIOS_DEBUG, "%p: hob_list_ptr\n", hob_list_ptr); do { EFI_HOB_GENERIC_HEADER *current_header_ptr = (EFI_HOB_GENERIC_HEADER *)current_hob; diff --git a/src/drivers/intel/fsp1_1/raminit.c b/src/drivers/intel/fsp1_1/raminit.c index 59a60cfb83..208ebb5a58 100644 --- a/src/drivers/intel/fsp1_1/raminit.c +++ b/src/drivers/intel/fsp1_1/raminit.c @@ -66,10 +66,10 @@ void raminit(struct romstage_params *params) fsp_header = params->chipset_context; vpd_ptr = (VPD_DATA_REGION *)(fsp_header->CfgRegionOffset + fsp_header->ImageBase); - printk(BIOS_DEBUG, "VPD Data: 0x%p\n", vpd_ptr); + printk(BIOS_DEBUG, "VPD Data: %p\n", vpd_ptr); upd_ptr = (UPD_DATA_REGION *)(vpd_ptr->PcdUpdRegionOffset + fsp_header->ImageBase); - printk(BIOS_DEBUG, "UPD Data: 0x%p\n", upd_ptr); + printk(BIOS_DEBUG, "UPD Data: %p\n", upd_ptr); original_params = (void *)((u8 *)upd_ptr + upd_ptr->MemoryInitUpdOffset); memcpy(&memory_init_params, original_params, @@ -110,12 +110,12 @@ void raminit(struct romstage_params *params) /* Call FspMemoryInit to initialize RAM */ fsp_memory_init = (FSP_MEMORY_INIT)(fsp_header->ImageBase + fsp_header->FspMemoryInitEntryOffset); - printk(BIOS_DEBUG, "Calling FspMemoryInit: 0x%p\n", fsp_memory_init); - printk(BIOS_SPEW, " 0x%p: NvsBufferPtr\n", + printk(BIOS_DEBUG, "Calling FspMemoryInit: %p\n", fsp_memory_init); + printk(BIOS_SPEW, " %p: NvsBufferPtr\n", fsp_memory_init_params.NvsBufferPtr); - printk(BIOS_SPEW, " 0x%p: RtBufferPtr\n", + printk(BIOS_SPEW, " %p: RtBufferPtr\n", fsp_memory_init_params.RtBufferPtr); - printk(BIOS_SPEW, " 0x%p: HobListPtr\n", + printk(BIOS_SPEW, " %p: HobListPtr\n", fsp_memory_init_params.HobListPtr); timestamp_add_now(TS_FSP_MEMORY_INIT_START); @@ -151,7 +151,7 @@ void raminit(struct romstage_params *params) } /* Migrate CAR data */ - printk(BIOS_DEBUG, "0x%p: cbmem_top\n", cbmem_top()); + printk(BIOS_DEBUG, "%p: cbmem_top\n", cbmem_top()); if (!s3wake) { cbmem_initialize_empty_id_size(CBMEM_ID_FSP_RESERVED_MEMORY, fsp_reserved_bytes); @@ -216,7 +216,7 @@ void raminit(struct romstage_params *params) /* Get the address of the CBMEM region for the FSP reserved memory */ fsp_reserved_memory_area = cbmem_find(CBMEM_ID_FSP_RESERVED_MEMORY); - printk(BIOS_DEBUG, "0x%p: fsp_reserved_memory_area\n", + printk(BIOS_DEBUG, "%p: fsp_reserved_memory_area\n", fsp_reserved_memory_area); /* Verify the order of CBMEM root and FSP memory */ diff --git a/src/drivers/intel/fsp1_1/ramstage.c b/src/drivers/intel/fsp1_1/ramstage.c index 70bedc50af..9ecdfd658a 100644 --- a/src/drivers/intel/fsp1_1/ramstage.c +++ b/src/drivers/intel/fsp1_1/ramstage.c @@ -81,10 +81,10 @@ void fsp_run_silicon_init(FSP_INFO_HEADER *fsp_info_header, int is_s3_wakeup) /* Initialize the UPD values */ vpd_ptr = (VPD_DATA_REGION *)(fsp_info_header->CfgRegionOffset + fsp_info_header->ImageBase); - printk(BIOS_DEBUG, "0x%p: VPD Data\n", vpd_ptr); + printk(BIOS_DEBUG, "%p: VPD Data\n", vpd_ptr); upd_ptr = (UPD_DATA_REGION *)(vpd_ptr->PcdUpdRegionOffset + fsp_info_header->ImageBase); - printk(BIOS_DEBUG, "0x%p: UPD Data\n", upd_ptr); + printk(BIOS_DEBUG, "%p: UPD Data\n", upd_ptr); original_params = (void *)((u8 *)upd_ptr + upd_ptr->SiliconInitUpdOffset); memcpy(&silicon_init_params, original_params, @@ -114,7 +114,7 @@ void fsp_run_silicon_init(FSP_INFO_HEADER *fsp_info_header, int is_s3_wakeup) fsp_silicon_init = (FSP_SILICON_INIT)(fsp_info_header->ImageBase + fsp_info_header->FspSiliconInitEntryOffset); timestamp_add_now(TS_FSP_SILICON_INIT_START); - printk(BIOS_DEBUG, "Calling FspSiliconInit(0x%p) at 0x%p\n", + printk(BIOS_DEBUG, "Calling FspSiliconInit(%p) at %p\n", &silicon_init_params, fsp_silicon_init); post_code(POST_FSP_SILICON_INIT); status = fsp_silicon_init(&silicon_init_params); diff --git a/src/drivers/intel/fsp1_1/romstage.c b/src/drivers/intel/fsp1_1/romstage.c index d441ca7008..95148f744b 100644 --- a/src/drivers/intel/fsp1_1/romstage.c +++ b/src/drivers/intel/fsp1_1/romstage.c @@ -220,7 +220,7 @@ __weak void mainboard_save_dimm_info( * table 17 */ mem_info = cbmem_add(CBMEM_ID_MEMINFO, sizeof(*mem_info)); - printk(BIOS_DEBUG, "CBMEM entry for DIMM info: 0x%p\n", mem_info); + printk(BIOS_DEBUG, "CBMEM entry for DIMM info: %p\n", mem_info); if (mem_info == NULL) return; memset(mem_info, 0, sizeof(*mem_info)); diff --git a/src/drivers/intel/fsp2_0/debug.c b/src/drivers/intel/fsp2_0/debug.c index 44ad735be2..5fc3b6fc16 100644 --- a/src/drivers/intel/fsp2_0/debug.c +++ b/src/drivers/intel/fsp2_0/debug.c @@ -40,9 +40,9 @@ void fsp_debug_before_memory_init(fsp_memory_init_fn memory_init, /* Display the call entry point and parameters */ if (!CONFIG(DISPLAY_FSP_CALLS_AND_STATUS)) return; - printk(BIOS_SPEW, "Calling FspMemoryInit: 0x%p\n", memory_init); - printk(BIOS_SPEW, "\t0x%p: raminit_upd\n", fspm_new_upd); - printk(BIOS_SPEW, "\t0x%p: &hob_list_ptr\n", fsp_get_hob_list_ptr()); + printk(BIOS_SPEW, "Calling FspMemoryInit: %p\n", memory_init); + printk(BIOS_SPEW, "\t%p: raminit_upd\n", fspm_new_upd); + printk(BIOS_SPEW, "\t%p: &hob_list_ptr\n", fsp_get_hob_list_ptr()); } void fsp_debug_after_memory_init(uint32_t status) @@ -83,8 +83,8 @@ void fsp_debug_before_silicon_init(fsp_silicon_init_fn silicon_init, /* Display the call to FSP SiliconInit */ if (!CONFIG(DISPLAY_FSP_CALLS_AND_STATUS)) return; - printk(BIOS_SPEW, "Calling FspSiliconInit: 0x%p\n", silicon_init); - printk(BIOS_SPEW, "\t0x%p: upd\n", fsps_new_upd); + printk(BIOS_SPEW, "Calling FspSiliconInit: %p\n", silicon_init); + printk(BIOS_SPEW, "\t%p: upd\n", fsps_new_upd); } void fsp_debug_after_silicon_init(uint32_t status) @@ -111,8 +111,8 @@ void fsp_before_debug_notify(fsp_notify_fn notify, return; printk(BIOS_SPEW, "0x%08x: notify_params->phase\n", notify_params->phase); - printk(BIOS_SPEW, "Calling FspNotify: 0x%p\n", notify); - printk(BIOS_SPEW, "\t0x%p: notify_params\n", notify_params); + printk(BIOS_SPEW, "Calling FspNotify: %p\n", notify); + printk(BIOS_SPEW, "\t%p: notify_params\n", notify_params); } void fsp_debug_after_notify(uint32_t status) diff --git a/src/drivers/intel/fsp2_0/hob_display.c b/src/drivers/intel/fsp2_0/hob_display.c index c4f04aed42..ce6937d123 100644 --- a/src/drivers/intel/fsp2_0/hob_display.c +++ b/src/drivers/intel/fsp2_0/hob_display.c @@ -186,12 +186,12 @@ void fsp_display_hobs(void) /* Display the HOB list pointer */ printk(BIOS_SPEW, "\n=== FSP HOBs ===\n"); - printk(BIOS_SPEW, "0x%p: hob_list_ptr\n", hob); + printk(BIOS_SPEW, "%p: hob_list_ptr\n", hob); /* Walk the list of HOBs */ while (1) { /* Display the HOB header */ - printk(BIOS_SPEW, "0x%p, 0x%08x bytes: %s\n", hob, hob->length, + printk(BIOS_SPEW, "%p, 0x%08x bytes: %s\n", hob, hob->length, fsp_get_hob_type_name(hob)); switch (hob->type) { default: diff --git a/src/drivers/intel/fsp2_0/hob_verify.c b/src/drivers/intel/fsp2_0/hob_verify.c index 0c28a9a82d..bdfb64d81a 100644 --- a/src/drivers/intel/fsp2_0/hob_verify.c +++ b/src/drivers/intel/fsp2_0/hob_verify.c @@ -56,7 +56,7 @@ void fsp_verify_memory_init_hobs(void) } if (range_entry_end(&tolum) != (uintptr_t)cbmem_top()) { - printk(BIOS_CRIT, "TOLUM end: 0x%08llx != 0x%p: cbmem_top\n", + printk(BIOS_CRIT, "TOLUM end: 0x%08llx != %p: cbmem_top\n", range_entry_end(&tolum), cbmem_top()); die("Space between cbmem_top and BIOS TOLUM!\n"); } diff --git a/src/drivers/intel/fsp2_0/temp_ram_exit.c b/src/drivers/intel/fsp2_0/temp_ram_exit.c index 1dfe1ba7b7..a2171b07ca 100644 --- a/src/drivers/intel/fsp2_0/temp_ram_exit.c +++ b/src/drivers/intel/fsp2_0/temp_ram_exit.c @@ -40,7 +40,7 @@ void fsp_temp_ram_exit(void) die("Invalid FSPM header!\n"); temp_ram_exit = (void *)(hdr.image_base + hdr.temp_ram_exit_entry); - printk(BIOS_DEBUG, "Calling TempRamExit: 0x%p\n", temp_ram_exit); + printk(BIOS_DEBUG, "Calling TempRamExit: %p\n", temp_ram_exit); status = temp_ram_exit(NULL); if (status != FSP_SUCCESS) { diff --git a/src/drivers/intel/fsp2_0/upd_display.c b/src/drivers/intel/fsp2_0/upd_display.c index defedab376..6ac52dd8b8 100644 --- a/src/drivers/intel/fsp2_0/upd_display.c +++ b/src/drivers/intel/fsp2_0/upd_display.c @@ -32,7 +32,7 @@ static void fspm_display_arch_params(const FSPM_ARCH_UPD *old, const FSPM_ARCH_UPD *new) { /* Display the architectural parameters for MemoryInit */ - printk(BIOS_SPEW, "Architectural UPD values for MemoryInit at: 0x%p\n", + printk(BIOS_SPEW, "Architectural UPD values for MemoryInit at: %p\n", new); fsp_display_upd_value("Revision", sizeof(old->Revision), old->Revision, new->Revision); diff --git a/src/drivers/spi/adesto.c b/src/drivers/spi/adesto.c index 695bdab2ea..f671247fba 100644 --- a/src/drivers/spi/adesto.c +++ b/src/drivers/spi/adesto.c @@ -170,7 +170,7 @@ static int adesto_write(const struct spi_flash *flash, u32 offset, size_t len, cmd[2] = (offset >> 8) & 0xff; cmd[3] = offset & 0xff; #if CONFIG(DEBUG_SPI_FLASH) - printk(BIOS_SPEW, "PP: 0x%p => cmd = { 0x%02x 0x%02x%02x%02x }" + printk(BIOS_SPEW, "PP: %p => cmd = { 0x%02x 0x%02x%02x%02x }" " chunk_len = %zu\n", buf + actual, cmd[0], cmd[1], cmd[2], cmd[3], chunk_len); #endif diff --git a/src/drivers/spi/amic.c b/src/drivers/spi/amic.c index 4943779a1a..9a23d9b527 100644 --- a/src/drivers/spi/amic.c +++ b/src/drivers/spi/amic.c @@ -141,7 +141,7 @@ static int amic_write(const struct spi_flash *flash, u32 offset, size_t len, cmd[2] = (offset >> 8) & 0xff; cmd[3] = offset & 0xff; #if CONFIG(DEBUG_SPI_FLASH) - printk(BIOS_SPEW, "PP: 0x%p => cmd = { 0x%02x 0x%02x%02x%02x }" + printk(BIOS_SPEW, "PP: %p => cmd = { 0x%02x 0x%02x%02x%02x }" " chunk_len = %zu\n", buf + actual, cmd[0], cmd[1], cmd[2], cmd[3], chunk_len); #endif diff --git a/src/drivers/spi/atmel.c b/src/drivers/spi/atmel.c index 8f88880ad6..88321f03a2 100644 --- a/src/drivers/spi/atmel.c +++ b/src/drivers/spi/atmel.c @@ -125,7 +125,7 @@ static int atmel_write(const struct spi_flash *flash, u32 offset, size_t len, cmd[2] = (offset >> 8) & 0xff; cmd[3] = offset & 0xff; #if CONFIG(DEBUG_SPI_FLASH) - printk(BIOS_SPEW, "PP: 0x%p => cmd = { 0x%02x 0x%02x%02x%02x }" + printk(BIOS_SPEW, "PP: %p => cmd = { 0x%02x 0x%02x%02x%02x }" " chunk_len = %zu\n", buf + actual, cmd[0], cmd[1], cmd[2], cmd[3], chunk_len); #endif diff --git a/src/drivers/spi/eon.c b/src/drivers/spi/eon.c index 5b527d1211..a469fe228a 100644 --- a/src/drivers/spi/eon.c +++ b/src/drivers/spi/eon.c @@ -265,7 +265,7 @@ static int eon_write(const struct spi_flash *flash, #if CONFIG(DEBUG_SPI_FLASH) printk(BIOS_SPEW, - "PP: 0x%p => cmd = { 0x%02x 0x%02x%02x%02x } chunk_len = %zu\n", + "PP: %p => cmd = { 0x%02x 0x%02x%02x%02x } chunk_len = %zu\n", buf + actual, cmd[0], cmd[1], cmd[2], cmd[3], chunk_len); #endif diff --git a/src/drivers/spi/gigadevice.c b/src/drivers/spi/gigadevice.c index 05a73df77c..9afc355336 100644 --- a/src/drivers/spi/gigadevice.c +++ b/src/drivers/spi/gigadevice.c @@ -194,7 +194,7 @@ static int gigadevice_write(const struct spi_flash *flash, u32 offset, cmd[3] = offset & 0xff; #if CONFIG(DEBUG_SPI_FLASH) printk(BIOS_SPEW, - "PP gigadevice.c: 0x%p => cmd = { 0x%02x 0x%02x%02x%02x }" + "PP gigadevice.c: %p => cmd = { 0x%02x 0x%02x%02x%02x }" " chunk_len = %zu\n", buf + actual, cmd[0], cmd[1], cmd[2], cmd[3], chunk_len); #endif diff --git a/src/drivers/spi/macronix.c b/src/drivers/spi/macronix.c index 25784b4dc3..29489ee235 100644 --- a/src/drivers/spi/macronix.c +++ b/src/drivers/spi/macronix.c @@ -222,7 +222,7 @@ static int macronix_write(const struct spi_flash *flash, u32 offset, size_t len, cmd[2] = (offset >> 8) & 0xff; cmd[3] = offset & 0xff; #if CONFIG(DEBUG_SPI_FLASH) - printk(BIOS_SPEW, "PP: 0x%p => cmd = { 0x%02x 0x%02x%02x%02x }" + printk(BIOS_SPEW, "PP: %p => cmd = { 0x%02x 0x%02x%02x%02x }" " chunk_len = %zu\n", buf + actual, cmd[0], cmd[1], cmd[2], cmd[3], chunk_len); #endif diff --git a/src/drivers/spi/spansion.c b/src/drivers/spi/spansion.c index cee93b2ac6..cb665d0a59 100644 --- a/src/drivers/spi/spansion.c +++ b/src/drivers/spi/spansion.c @@ -241,7 +241,7 @@ static int spansion_write(const struct spi_flash *flash, u32 offset, size_t len, cmd[3] = offset & 0xff; #if CONFIG(DEBUG_SPI_FLASH) - printk(BIOS_SPEW, "PP: 0x%p => cmd = { 0x%02x 0x%02x%02x%02x }" + printk(BIOS_SPEW, "PP: %p => cmd = { 0x%02x 0x%02x%02x%02x }" " chunk_len = %zu\n", buf + actual, cmd[0], cmd[1], cmd[2], cmd[3], chunk_len); #endif diff --git a/src/drivers/spi/sst.c b/src/drivers/spi/sst.c index 348d06c3e8..5367b70d21 100644 --- a/src/drivers/spi/sst.c +++ b/src/drivers/spi/sst.c @@ -171,7 +171,7 @@ sst_byte_write(const struct spi_flash *flash, u32 offset, const void *buf) }; #if CONFIG(DEBUG_SPI_FLASH) - printk(BIOS_SPEW, "BP[%02x]: 0x%p => cmd = { 0x%02x 0x%06x }\n", + printk(BIOS_SPEW, "BP[%02x]: %p => cmd = { 0x%02x 0x%06x }\n", spi_w8r8(&flash->spi, CMD_SST_RDSR), buf, cmd[0], offset); #endif @@ -225,7 +225,7 @@ static int sst_write_256(const struct spi_flash *flash, u32 offset, size_t len, cmd[2] = (offset >> 8) & 0xff; cmd[3] = offset & 0xff; #if CONFIG(DEBUG_SPI_FLASH) - printk(BIOS_SPEW, "PP: 0x%p => cmd = { 0x%02x 0x%02x%02x%02x }" + printk(BIOS_SPEW, "PP: %p => cmd = { 0x%02x 0x%02x%02x%02x }" " chunk_len = %zu\n", buf + actual, cmd[0], cmd[1], cmd[2], cmd[3], chunk_len); #endif @@ -287,7 +287,7 @@ static int sst_write_ai(const struct spi_flash *flash, u32 offset, size_t len, for (; actual < len - 1; actual += 2) { #if CONFIG(DEBUG_SPI_FLASH) - printk(BIOS_SPEW, "WP[%02x]: 0x%p => cmd = { 0x%02x 0x%06x }\n", + printk(BIOS_SPEW, "WP[%02x]: %p => cmd = { 0x%02x 0x%06x }\n", spi_w8r8(&flash->spi, CMD_SST_RDSR), buf + actual, cmd[0], offset); #endif diff --git a/src/drivers/spi/stmicro.c b/src/drivers/spi/stmicro.c index ddff859d38..d397e6e669 100644 --- a/src/drivers/spi/stmicro.c +++ b/src/drivers/spi/stmicro.c @@ -306,7 +306,7 @@ static int stmicro_write(const struct spi_flash *flash, cmd[2] = (offset >> 8) & 0xff; cmd[3] = offset & 0xff; #if CONFIG(DEBUG_SPI_FLASH) - printk(BIOS_SPEW, "PP: 0x%p => cmd = { 0x%02x 0x%02x%02x%02x }" + printk(BIOS_SPEW, "PP: %p => cmd = { 0x%02x 0x%02x%02x%02x }" " chunk_len = %zu\n", buf + actual, cmd[0], cmd[1], cmd[2], cmd[3], chunk_len); #endif diff --git a/src/drivers/spi/winbond.c b/src/drivers/spi/winbond.c index 9e451171e5..432ad6a47e 100644 --- a/src/drivers/spi/winbond.c +++ b/src/drivers/spi/winbond.c @@ -318,7 +318,7 @@ static int winbond_write(const struct spi_flash *flash, u32 offset, size_t len, cmd[2] = (offset >> 8) & 0xff; cmd[3] = offset & 0xff; #if CONFIG(DEBUG_SPI_FLASH) - printk(BIOS_SPEW, "PP: 0x%p => cmd = { 0x%02x 0x%02x%02x%02x }" + printk(BIOS_SPEW, "PP: %p => cmd = { 0x%02x 0x%02x%02x%02x }" " chunk_len = %zu\n", buf + actual, cmd[0], cmd[1], cmd[2], cmd[3], chunk_len); #endif diff --git a/src/drivers/xgi/common/xgi_coreboot.c b/src/drivers/xgi/common/xgi_coreboot.c index caeb59d749..d65e007a2a 100644 --- a/src/drivers/xgi/common/xgi_coreboot.c +++ b/src/drivers/xgi/common/xgi_coreboot.c @@ -126,13 +126,13 @@ int xgifb_probe(struct pci_dev *pdev, struct xgifb_video_info *xgifb_info) xgifb_info->mmio_vbase = (void *)(intptr_t)xgifb_info->mmio_base; dev_info(&pdev->dev, - "Framebuffer at 0x%Lx, mapped to 0x%p, size %dk\n", + "Framebuffer at 0x%Lx, mapped to %p, size %dk\n", (u64) xgifb_info->video_base, xgifb_info->video_vbase, xgifb_info->video_size / 1024); dev_info(&pdev->dev, - "MMIO at 0x%Lx, mapped to 0x%p, size %ldk\n", + "MMIO at 0x%Lx, mapped to %p, size %ldk\n", (u64) xgifb_info->mmio_base, xgifb_info->mmio_vbase, xgifb_info->mmio_size / 1024); diff --git a/src/lib/coreboot_table.c b/src/lib/coreboot_table.c index af9f6599c5..e42cb3bdd2 100644 --- a/src/lib/coreboot_table.c +++ b/src/lib/coreboot_table.c @@ -476,7 +476,7 @@ size_t write_coreboot_forwarding_table(uintptr_t entry, uintptr_t target) { struct lb_header *head; - printk(BIOS_DEBUG, "Writing table forward entry at 0x%p\n", + printk(BIOS_DEBUG, "Writing table forward entry at %p\n", (void *)entry); head = lb_table_init(entry); diff --git a/src/lib/imd.c b/src/lib/imd.c index b5fc34a9a0..4fa8f7023b 100644 --- a/src/lib/imd.c +++ b/src/lib/imd.c @@ -687,7 +687,7 @@ static void imdr_print_entries(const struct imdr *imdr, const char *indent, printk(BIOS_DEBUG, "%s", name); printk(BIOS_DEBUG, "%2zu. ", i); printk(BIOS_DEBUG, "%p ", imdr_entry_at(imdr, e)); - printk(BIOS_DEBUG, "%08zx\n", imdr_entry_size(imdr, e)); + printk(BIOS_DEBUG, "0x%08zx\n", imdr_entry_size(imdr, e)); } } diff --git a/src/lib/rmodule.c b/src/lib/rmodule.c index 56529d2fb2..96cee8aad3 100644 --- a/src/lib/rmodule.c +++ b/src/lib/rmodule.c @@ -278,7 +278,7 @@ int rmodule_stage_load(struct rmod_stage_load *rsl) rmod_loc = &stage_region[rmodule_offset]; - printk(BIOS_INFO, "Decompressing stage %s @ 0x%p (%d bytes)\n", + printk(BIOS_INFO, "Decompressing stage %s @ %p (%d bytes)\n", prog_name(rsl->prog), rmod_loc, stage.memlen); if (!cbfs_load_and_decompress(fh, sizeof(stage), stage.len, rmod_loc, diff --git a/src/lib/selfboot.c b/src/lib/selfboot.c index a0bb711f8a..8cf7a6ff57 100644 --- a/src/lib/selfboot.c +++ b/src/lib/selfboot.c @@ -56,7 +56,7 @@ static int segment_targets_type(void *dest, unsigned long memsz, if (payload_arch_usable_ram_quirk(d, memsz)) return 1; - printk(BIOS_ERR, "SELF segment doesn't target RAM: 0x%p, %lu bytes\n", dest, memsz); + printk(BIOS_ERR, "SELF segment doesn't target RAM: %p, %lu bytes\n", dest, memsz); bootmem_dump_ranges(); return 0; } @@ -69,7 +69,7 @@ static int load_one_segment(uint8_t *dest, int flags) { unsigned char *middle, *end; - printk(BIOS_DEBUG, "Loading Segment: addr: 0x%p memsz: 0x%016zx filesz: 0x%016zx\n", + printk(BIOS_DEBUG, "Loading Segment: addr: %p memsz: 0x%016zx filesz: 0x%016zx\n", dest, memsz, len); /* Compute the boundaries of the segment */ @@ -150,7 +150,7 @@ static int check_payload_segments(struct cbfs_payload_segment *cbfssegs, enum bootmem_type dest_type = *(enum bootmem_type *)args; for (seg = cbfssegs;; ++seg) { - printk(BIOS_DEBUG, "Checking segment from ROM address 0x%p\n", seg); + printk(BIOS_DEBUG, "Checking segment from ROM address %p\n", seg); cbfs_decode_payload_segment(&segment, seg); dest = (uint8_t *)(uintptr_t)segment.load_addr; memsz = segment.mem_len; @@ -171,7 +171,7 @@ static int load_payload_segments(struct cbfs_payload_segment *cbfssegs, uintptr_ int flags = 0; for (first_segment = seg = cbfssegs;; ++seg) { - printk(BIOS_DEBUG, "Loading segment from ROM address 0x%p\n", seg); + printk(BIOS_DEBUG, "Loading segment from ROM address %p\n", seg); cbfs_decode_payload_segment(&segment, seg); dest = (uint8_t *)(uintptr_t)segment.load_addr; @@ -187,7 +187,7 @@ static int load_payload_segments(struct cbfs_payload_segment *cbfssegs, uintptr_ ? "code" : "data", segment.compression); src = ((uint8_t *)first_segment) + segment.offset; printk(BIOS_DEBUG, - " New segment dstaddr 0x%p memsize 0x%zx srcaddr 0x%p filesize 0x%zx\n", + " New segment dstaddr %p memsize 0x%zx srcaddr %p filesize 0x%zx\n", dest, memsz, src, filesz); /* Clean up the values */ @@ -198,7 +198,7 @@ static int load_payload_segments(struct cbfs_payload_segment *cbfssegs, uintptr_ break; case PAYLOAD_SEGMENT_BSS: - printk(BIOS_DEBUG, " BSS 0x%p (%d byte)\n", (void *) + printk(BIOS_DEBUG, " BSS %p (%d byte)\n", (void *) (intptr_t)segment.load_addr, segment.mem_len); filesz = 0; src = ((uint8_t *)first_segment) + segment.offset; @@ -206,7 +206,7 @@ static int load_payload_segments(struct cbfs_payload_segment *cbfssegs, uintptr_ break; case PAYLOAD_SEGMENT_ENTRY: - printk(BIOS_DEBUG, " Entry Point 0x%p\n", (void *) + printk(BIOS_DEBUG, " Entry Point %p\n", (void *) (intptr_t)segment.load_addr); *entry = segment.load_addr; diff --git a/src/lib/trace.c b/src/lib/trace.c index b11881760d..826fa3b671 100644 --- a/src/lib/trace.c +++ b/src/lib/trace.c @@ -26,7 +26,7 @@ void __cyg_profile_func_enter(void *func, void *callsite) return; DISABLE_TRACE - printk(BIOS_INFO, "~0x%p(0x%p)\n", func, callsite); + printk(BIOS_INFO, "~%p(%p)\n", func, callsite); ENABLE_TRACE } diff --git a/src/mainboard/google/cyan/spd/spd.c b/src/mainboard/google/cyan/spd/spd.c index f73b9e6539..8dd4366ad0 100644 --- a/src/mainboard/google/cyan/spd/spd.c +++ b/src/mainboard/google/cyan/spd/spd.c @@ -191,7 +191,7 @@ void mainboard_save_dimm_info(struct romstage_params *params) * table 17 */ mem_info = cbmem_add(CBMEM_ID_MEMINFO, sizeof(*mem_info)); - printk(BIOS_DEBUG, "CBMEM entry for DIMM info: 0x%p\n", mem_info); + printk(BIOS_DEBUG, "CBMEM entry for DIMM info: %p\n", mem_info); if (mem_info == NULL) return; memset(mem_info, 0, sizeof(*mem_info)); diff --git a/src/soc/amd/common/block/pi/def_callouts.c b/src/soc/amd/common/block/pi/def_callouts.c index 299a98abe9..facd5f8c0f 100644 --- a/src/soc/amd/common/block/pi/def_callouts.c +++ b/src/soc/amd/common/block/pi/def_callouts.c @@ -198,7 +198,7 @@ static void callout_ap_entry(void *unused) { AGESA_STATUS Status = AGESA_UNSUPPORTED; - printk(BIOS_DEBUG, "%s Func: 0x%x, Data: 0x%lx, Ptr: 0x%p\n", + printk(BIOS_DEBUG, "%s Func: 0x%x, Data: 0x%lx, Ptr: %p\n", __func__, agesadata.Func, agesadata.Data, agesadata.ConfigPtr); /* Check if this AP should run the function */ diff --git a/src/soc/amd/common/block/s3/s3_resume.c b/src/soc/amd/common/block/s3/s3_resume.c index 598036acf2..a0de406d38 100644 --- a/src/soc/amd/common/block/s3/s3_resume.c +++ b/src/soc/amd/common/block/s3/s3_resume.c @@ -58,7 +58,7 @@ AGESA_STATUS OemInitResume(S3_DATA_BLOCK *dataBlock) dataBlock->NvStorage = base; dataBlock->NvStorageSize = size; - printk(BIOS_SPEW, "S3 NV data @0x%p, 0x%0zx bytes\n", + printk(BIOS_SPEW, "S3 NV data @%p, 0x%0zx bytes\n", dataBlock->NvStorage, (size_t)dataBlock->NvStorageSize); return AGESA_SUCCESS; @@ -77,7 +77,7 @@ AGESA_STATUS OemS3LateRestore(S3_DATA_BLOCK *dataBlock) dataBlock->VolatileStorage = base; dataBlock->VolatileStorageSize = size; - printk(BIOS_SPEW, "S3 volatile data @0x%p, 0x%0zx bytes\n", + printk(BIOS_SPEW, "S3 volatile data @%p, 0x%0zx bytes\n", dataBlock->VolatileStorage, (size_t)dataBlock->VolatileStorageSize); return AGESA_SUCCESS; diff --git a/src/soc/amd/common/block/spi/fch_spi_flash.c b/src/soc/amd/common/block/spi/fch_spi_flash.c index 40dd0e2996..72bc5d6ea5 100644 --- a/src/soc/amd/common/block/spi/fch_spi_flash.c +++ b/src/soc/amd/common/block/spi/fch_spi_flash.c @@ -200,7 +200,7 @@ static int fch_spi_flash_write(const struct spi_flash *flash, uint32_t offset, s cmd[2] = (offset >> 8) & 0xff; cmd[3] = offset & 0xff; #if CONFIG(SOC_AMD_COMMON_BLOCK_SPI_DEBUG) - printk(BIOS_DEBUG, "PP: 0x%p => cmd = { 0x%02x 0x%02x%02x%02x } chunk_len = %zu" + printk(BIOS_DEBUG, "PP: %p => cmd = { 0x%02x 0x%02x%02x%02x } chunk_len = %zu" "\n", buf + actual, cmd[0], cmd[1], cmd[2], cmd[3], chunk_len); #endif diff --git a/src/soc/amd/common/block/spi/fch_spi_special.c b/src/soc/amd/common/block/spi/fch_spi_special.c index fa3c00ac84..27bea05143 100644 --- a/src/soc/amd/common/block/spi/fch_spi_special.c +++ b/src/soc/amd/common/block/spi/fch_spi_special.c @@ -56,7 +56,7 @@ int non_standard_sst_write_aai(u32 offset, size_t len, const void *buf, size_t s for (actual = start; actual < len - 1; actual += 2) { #if CONFIG(SOC_AMD_COMMON_BLOCK_SPI_DEBUG) - printk(BIOS_DEBUG, "PP: 0x%p => cmd = { 0x%02x 0x%06lx }" + printk(BIOS_DEBUG, "PP: %p => cmd = { 0x%02x 0x%06lx }" " chunk_len = 2\n", buf + actual, cmd[0], (offset + actual)); #endif diff --git a/src/soc/intel/braswell/southcluster.c b/src/soc/intel/braswell/southcluster.c index 8b13fd0e82..b2d13d5642 100644 --- a/src/soc/intel/braswell/southcluster.c +++ b/src/soc/intel/braswell/southcluster.c @@ -618,7 +618,7 @@ static void finalize_chipset(void *unused) uint8_t *spi = (uint8_t *)SPI_BASE_ADDRESS; struct vscc_config cfg; - printk(BIOS_SPEW, "%s/%s (0x%p)\n", + printk(BIOS_SPEW, "%s/%s (%p)\n", __FILE__, __func__, unused); /* Set the lock enable on the BIOS control register. */ diff --git a/src/soc/intel/common/mma.c b/src/soc/intel/common/mma.c index 1b3a82a088..2cd35ea6cd 100644 --- a/src/soc/intel/common/mma.c +++ b/src/soc/intel/common/mma.c @@ -219,7 +219,7 @@ static void save_mma_results_data(void *unused) memset(mma_data, 0, mma_data_size); printk(BIOS_DEBUG, - "MMA: copy MMA data to CBMEM(src 0x%p, dest 0x%p, %u bytes)\n", + "MMA: copy MMA data to CBMEM(src %p, dest %p, %u bytes)\n", mma_hob, mma_data, mma_hob_size); mma_data->mma_signature = MMA_DATA_SIGNATURE; diff --git a/src/soc/intel/denverton_ns/hob_mem.c b/src/soc/intel/denverton_ns/hob_mem.c index e4aa78f291..a00a4f498c 100644 --- a/src/soc/intel/denverton_ns/hob_mem.c +++ b/src/soc/intel/denverton_ns/hob_mem.c @@ -52,7 +52,7 @@ void soc_save_dimm_info(void) * table 17 */ mem_info = cbmem_add(CBMEM_ID_MEMINFO, sizeof(*mem_info)); - printk(BIOS_DEBUG, "CBMEM entry for DIMM info: 0x%p\n", mem_info); + printk(BIOS_DEBUG, "CBMEM entry for DIMM info: %p\n", mem_info); if (mem_info == NULL) return; memset(mem_info, 0, sizeof(*mem_info)); diff --git a/src/soc/intel/quark/bootblock/bootblock.c b/src/soc/intel/quark/bootblock/bootblock.c index 2b2fc29f59..957b4a0c37 100644 --- a/src/soc/intel/quark/bootblock/bootblock.c +++ b/src/soc/intel/quark/bootblock/bootblock.c @@ -118,6 +118,6 @@ void bootblock_soc_init(void) void platform_prog_run(struct prog *prog) { /* Display the program entry point */ - printk(BIOS_SPEW, "Calling %s, 0x%p(0x%p)\n", prog->name, + printk(BIOS_SPEW, "Calling %s, %p(%p)\n", prog->name, prog->entry, prog->arg); } diff --git a/src/soc/intel/quark/i2c.c b/src/soc/intel/quark/i2c.c index b09852bc3f..7ff2ddf93f 100644 --- a/src/soc/intel/quark/i2c.c +++ b/src/soc/intel/quark/i2c.c @@ -209,7 +209,7 @@ int platform_i2c_transfer(unsigned int bus, struct i2c_msg *segment, if (index == 0) printk(BIOS_ERR, "I2C Start\n"); printk(BIOS_ERR, - "I2C segment[%d]: %s 0x%02x %s 0x%p, 0x%08x bytes\n", + "I2C segment[%d]: %s 0x%02x %s %p, 0x%08x bytes\n", index, (segment[index].flags & I2C_M_RD) ? "Read from" : "Write to", segment[index].slave, diff --git a/src/soc/intel/quark/romstage/debug.c b/src/soc/intel/quark/romstage/debug.c index 1029eadb93..e0cf6c8262 100644 --- a/src/soc/intel/quark/romstage/debug.c +++ b/src/soc/intel/quark/romstage/debug.c @@ -26,7 +26,7 @@ void soc_display_fspm_upd_params(const FSPM_UPD *fspm_old_upd, new = &fspm_new_upd->FspmConfig; /* Display the parameters for MemoryInit */ - printk(BIOS_SPEW, "UPD values for MemoryInit at: 0x%p\n", new); + printk(BIOS_SPEW, "UPD values for MemoryInit at: %p\n", new); fsp_display_upd_value("AddrMode", sizeof(old->AddrMode), old->AddrMode, new->AddrMode); fsp_display_upd_value("ChanMask", sizeof(old->ChanMask), diff --git a/src/soc/intel/quark/romstage/fsp_params.c b/src/soc/intel/quark/romstage/fsp_params.c index 681e126a13..c31cafb14f 100644 --- a/src/soc/intel/quark/romstage/fsp_params.c +++ b/src/soc/intel/quark/romstage/fsp_params.c @@ -111,13 +111,13 @@ void platform_fsp_memory_init_params_cb(FSPM_UPD *fspm_upd, uint32_t version) "+-------------------+ 0x%08x (CONFIG_FSP_ESRAM_LOC)\n", CONFIG_FSP_ESRAM_LOC); printk(BIOS_SPEW, "| FSP stack |\n"); - printk(BIOS_SPEW, "+-------------------+ 0x%p\n", + printk(BIOS_SPEW, "+-------------------+ %p\n", aupd->StackBase); printk(BIOS_SPEW, "| |\n"); - printk(BIOS_SPEW, "+-------------------+ 0x%p\n", + printk(BIOS_SPEW, "+-------------------+ %p\n", _car_unallocated_start); printk(BIOS_SPEW, "| coreboot data |\n"); - printk(BIOS_SPEW, "+-------------------+ 0x%p\n", + printk(BIOS_SPEW, "+-------------------+ %p\n", _ecar_stack); printk(BIOS_SPEW, "| coreboot stack |\n"); printk(BIOS_SPEW, diff --git a/src/soc/qualcomm/ipq40xx/qup.c b/src/soc/qualcomm/ipq40xx/qup.c index 9a206fc6a9..1775c84628 100644 --- a/src/soc/qualcomm/ipq40xx/qup.c +++ b/src/soc/qualcomm/ipq40xx/qup.c @@ -47,7 +47,7 @@ #if QUP_DEBUG #define qup_write32(a, v) do { \ write32(a, v); \ - printk(QUPDBG "%s(%d): write32(0x%p, 0x%x)\n", \ + printk(QUPDBG "%s(%d): write32(%p, 0x%x)\n", \ __func__, __LINE__, a, v); \ } while (0) #else diff --git a/src/soc/qualcomm/qcs405/qup.c b/src/soc/qualcomm/qcs405/qup.c index cff5241480..6e84bcb2ff 100644 --- a/src/soc/qualcomm/qcs405/qup.c +++ b/src/soc/qualcomm/qcs405/qup.c @@ -48,7 +48,7 @@ #if QUP_DEBUG #define qup_write32(a, v) do { \ write32(a, v); \ - printk(QUPDBG "%s(%d): write32(0x%p, 0x%x)\n", \ + printk(QUPDBG "%s(%d): write32(%p, 0x%x)\n", \ __func__, __LINE__, a, v); \ } while (0) #else diff --git a/src/vendorcode/google/chromeos/ramoops.c b/src/vendorcode/google/chromeos/ramoops.c index 7eef2d1338..9ea112a5c4 100644 --- a/src/vendorcode/google/chromeos/ramoops.c +++ b/src/vendorcode/google/chromeos/ramoops.c @@ -32,7 +32,7 @@ static void set_ramoops(chromeos_acpi_t *chromeos, void *ram_oops, size_t size) return; } - printk(BIOS_DEBUG, "Ramoops buffer: 0x%zx@0x%p.\n", size, ram_oops); + printk(BIOS_DEBUG, "Ramoops buffer: 0x%zx@%p.\n", size, ram_oops); chromeos->ramoops_base = (uintptr_t)ram_oops; chromeos->ramoops_len = size; } From ba8d8f2583e5b9830322fb4a96b04306d427f29a Mon Sep 17 00:00:00 2001 From: Matt DeVillier Date: Thu, 5 Dec 2019 17:16:07 -0600 Subject: [PATCH 0625/1242] drivers/i2c/rt5663/: fix missing header include 'struct acpi_gpio' and 'struct acpi_irq' require the inclusion of acpi_device.h. The only reason this wasn't caught previously is due to the header being included with another driver compiled first on the one board using it (google/eve). Change-Id: I987f0ec6f769e550f3421629e0ef0c579a3d12f9 Signed-off-by: Matt DeVillier Reviewed-on: https://review.coreboot.org/c/coreboot/+/37539 Reviewed-by: Nico Huber Tested-by: build bot (Jenkins) --- src/drivers/i2c/rt5663/chip.h | 1 + 1 file changed, 1 insertion(+) diff --git a/src/drivers/i2c/rt5663/chip.h b/src/drivers/i2c/rt5663/chip.h index b1ed4b6589..235c253d07 100644 --- a/src/drivers/i2c/rt5663/chip.h +++ b/src/drivers/i2c/rt5663/chip.h @@ -15,6 +15,7 @@ * Realtek RT5663 audio codec devicetree bindings */ +#include #include struct drivers_i2c_rt5663_config { From e4951055dd96be64d46c3d73a6dc4fa3a8260a5b Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Thu, 5 Dec 2019 23:12:18 +0100 Subject: [PATCH 0626/1242] mb/**/hda_verb.c: use denary numerals for lengths Denary, also known as "decimal" or "base 10," is the standard number system used around the world. Therefore, make use of it. Change-Id: Ia22705d7629a322292cfd557add9cfadc649c16c Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/37537 Reviewed-by: HAOUAS Elyes Tested-by: build bot (Jenkins) --- src/mainboard/apple/macbook21/hda_verb.c | 4 ++-- src/mainboard/apple/macbookair4_2/hda_verb.c | 4 ++-- src/mainboard/asrock/b75pro3-m/hda_verb.c | 4 ++-- src/mainboard/asrock/h110m/hda_verb.c | 2 +- src/mainboard/asus/p8h61-m_pro/hda_verb.c | 4 ++-- src/mainboard/asus/p8z77-m_pro/hda_verb.c | 4 ++-- src/mainboard/compulab/intense_pc/hda_verb.c | 4 ++-- .../gigabyte/ga-h61m-s2pv/variants/ga-h61m-s2pv/hda_verb.c | 2 +- .../gigabyte/ga-h61m-s2pv/variants/ga-h61ma-d3v/hda_verb.c | 2 +- src/mainboard/google/butterfly/hda_verb.c | 4 ++-- src/mainboard/hp/2570p/hda_verb.c | 6 +++--- src/mainboard/hp/2760p/hda_verb.c | 6 +++--- src/mainboard/hp/8460p/hda_verb.c | 4 ++-- src/mainboard/hp/8470p/hda_verb.c | 4 ++-- src/mainboard/hp/8770w/hda_verb.c | 2 +- src/mainboard/hp/compaq_8200_elite_sff/hda_verb.c | 4 ++-- src/mainboard/hp/folio_9470m/hda_verb.c | 4 ++-- src/mainboard/hp/revolve_810_g1/hda_verb.c | 6 +++--- src/mainboard/hp/z220_sff_workstation/hda_verb.c | 4 ++-- src/mainboard/intel/dcp847ske/hda_verb.c | 2 +- src/mainboard/lenovo/l520/hda_verb.c | 4 ++-- src/mainboard/lenovo/s230u/hda_verb.c | 4 ++-- src/mainboard/lenovo/t410/hda_verb.c | 4 ++-- src/mainboard/lenovo/t420/hda_verb.c | 2 +- src/mainboard/lenovo/t420s/hda_verb.c | 2 +- src/mainboard/lenovo/t430/hda_verb.c | 2 +- src/mainboard/lenovo/t430s/variants/t430s/hda_verb.c | 4 ++-- src/mainboard/lenovo/t430s/variants/t431s/hda_verb.c | 4 ++-- src/mainboard/lenovo/t520/hda_verb.c | 2 +- src/mainboard/lenovo/t530/hda_verb.c | 4 ++-- src/mainboard/lenovo/t60/hda_verb.c | 2 +- src/mainboard/lenovo/x1_carbon_gen1/hda_verb.c | 4 ++-- src/mainboard/lenovo/x201/hda_verb.c | 4 ++-- src/mainboard/lenovo/x220/hda_verb.c | 4 ++-- src/mainboard/lenovo/x230/hda_verb.c | 4 ++-- src/mainboard/lenovo/x60/hda_verb.c | 2 +- src/mainboard/msi/ms7707/hda_verb.c | 2 +- src/mainboard/packardbell/ms2290/hda_verb.c | 4 ++-- src/mainboard/sapphire/pureplatinumh61/hda_verb.c | 4 ++-- 39 files changed, 69 insertions(+), 69 deletions(-) diff --git a/src/mainboard/apple/macbook21/hda_verb.c b/src/mainboard/apple/macbook21/hda_verb.c index 09d5f1ab98..3d87d3d882 100644 --- a/src/mainboard/apple/macbook21/hda_verb.c +++ b/src/mainboard/apple/macbook21/hda_verb.c @@ -22,7 +22,7 @@ const u32 cim_verb_data[] = { #if CONFIG(BOARD_APPLE_MACBOOK11) || \ CONFIG(BOARD_APPLE_MACBOOK21) 0x106b2200, /* Subsystem ID */ - 0x0000000B, /* Number of 4 dword sets */ + 11, /* Number of 4 dword sets */ /* NID 0x01: Subsystem ID. */ AZALIA_SUBVENDOR(0x0, 0x106B2200), @@ -58,7 +58,7 @@ const u32 cim_verb_data[] = { AZALIA_PIN_CFG(0x0, 0x1B, 0x400000FB), #else /* CONFIG_BOARD_APPLE_IMAC52 */ 0x106b0f00, /* Subsystem ID */ - 0x0000000b, /* Number of 4 dword sets */ + 11, /* Number of 4 dword sets */ /* NID 0x01: Subsystem ID. */ AZALIA_SUBVENDOR(0x0, 0x106b0f00), diff --git a/src/mainboard/apple/macbookair4_2/hda_verb.c b/src/mainboard/apple/macbookair4_2/hda_verb.c index 6ca5f512df..69a165ca19 100644 --- a/src/mainboard/apple/macbookair4_2/hda_verb.c +++ b/src/mainboard/apple/macbookair4_2/hda_verb.c @@ -17,7 +17,7 @@ const u32 cim_verb_data[] = { 0x10134206, /* Codec Vendor / Device ID: Cirrus */ 0x106b5b00, /* Subsystem ID */ - 0x0000000b, /* Number of 4 dword sets */ + 11, /* Number of 4 dword sets */ /* NID 0x01: Subsystem ID. */ AZALIA_SUBVENDOR(0x0, 0x106b5b00), @@ -53,7 +53,7 @@ const u32 cim_verb_data[] = { 0x80862805, /* Codec Vendor / Device ID: Intel */ 0x80860101, /* Subsystem ID */ - 0x00000004, /* Number of 4 dword sets */ + 4, /* Number of 4 dword sets */ /* NID 0x01: Subsystem ID. */ AZALIA_SUBVENDOR(0x3, 0x80860101), diff --git a/src/mainboard/asrock/b75pro3-m/hda_verb.c b/src/mainboard/asrock/b75pro3-m/hda_verb.c index cae9137088..d7e41b773a 100644 --- a/src/mainboard/asrock/b75pro3-m/hda_verb.c +++ b/src/mainboard/asrock/b75pro3-m/hda_verb.c @@ -21,7 +21,7 @@ const u32 cim_verb_data[] = { 0x10ec0892, /* Codec Vendor / Device ID: Realtek */ 0x18498892, /* Subsystem ID */ - 0x0000000f, /* Number of 4 dword sets */ + 15, /* Number of 4 dword sets */ /* NID 0x01: Subsystem ID. */ AZALIA_SUBVENDOR(0x0, 0x18498892), @@ -69,7 +69,7 @@ const u32 cim_verb_data[] = { 0x80862806, /* Codec Vendor / Device ID: Intel */ 0x80860101, /* Subsystem ID */ - 0x00000004, /* Number of 4 dword sets */ + 4, /* Number of 4 dword sets */ /* NID 0x01: Subsystem ID. */ AZALIA_SUBVENDOR(0x3, 0x80860101), diff --git a/src/mainboard/asrock/h110m/hda_verb.c b/src/mainboard/asrock/h110m/hda_verb.c index 2fb0fe7e7d..6e13784c27 100644 --- a/src/mainboard/asrock/h110m/hda_verb.c +++ b/src/mainboard/asrock/h110m/hda_verb.c @@ -41,7 +41,7 @@ const u32 cim_verb_data[] = { /* coreboot specific header */ 0x80862809, /* Codec Vendor / Device ID: Intel Skylake HDMI */ 0x80860101, - 0x00000004, + 4, /* NID 0x01, HDA Codec Subsystem ID Verb Table: 0x80860101 */ AZALIA_SUBVENDOR(0x2, 0x80860101), diff --git a/src/mainboard/asus/p8h61-m_pro/hda_verb.c b/src/mainboard/asus/p8h61-m_pro/hda_verb.c index 13b25ed438..05a2b39bca 100644 --- a/src/mainboard/asus/p8h61-m_pro/hda_verb.c +++ b/src/mainboard/asus/p8h61-m_pro/hda_verb.c @@ -19,7 +19,7 @@ const u32 cim_verb_data[] = { 0x10ec0887, /* Codec Vendor / Device ID: Realtek */ 0x10438444, /* Subsystem ID */ - 0x0000000f, /* Number of 4 dword sets */ + 15, /* Number of 4 dword sets */ /* NID 0x01: Subsystem ID. */ AZALIA_SUBVENDOR(0x0, 0x10438444), @@ -67,7 +67,7 @@ const u32 cim_verb_data[] = { 0x80862805, /* Codec Vendor / Device ID: Intel */ 0x80860101, /* Subsystem ID */ - 0x00000004, /* Number of 4 dword sets */ + 4, /* Number of 4 dword sets */ /* NID 0x01: Subsystem ID. */ AZALIA_SUBVENDOR(0x3, 0x80860101), diff --git a/src/mainboard/asus/p8z77-m_pro/hda_verb.c b/src/mainboard/asus/p8z77-m_pro/hda_verb.c index 4fd3fcc5e3..1f22a7c68f 100644 --- a/src/mainboard/asus/p8z77-m_pro/hda_verb.c +++ b/src/mainboard/asus/p8z77-m_pro/hda_verb.c @@ -22,7 +22,7 @@ const u32 cim_verb_data[] = { 0x10ec0892, /* Codec Vendor / Device ID: Realtek */ 0x10438436, /* Subsystem ID */ - 0x0000000f, /* Number of 4 dword sets */ + 15, /* Number of 4 dword sets */ /* Subsystem ID */ AZALIA_SUBVENDOR(0x0, 0x10438436), @@ -43,7 +43,7 @@ const u32 cim_verb_data[] = { 0x80862806, /* Codec Vendor / Device ID: Intel */ 0x80860101, /* Subsystem ID */ - 0x00000004, /* Number of 4 dword sets */ + 4, /* Number of 4 dword sets */ /* Subsystem ID */ AZALIA_SUBVENDOR(0x3, 0x80860101), diff --git a/src/mainboard/compulab/intense_pc/hda_verb.c b/src/mainboard/compulab/intense_pc/hda_verb.c index 5cade62e6f..c71d83b12e 100644 --- a/src/mainboard/compulab/intense_pc/hda_verb.c +++ b/src/mainboard/compulab/intense_pc/hda_verb.c @@ -21,7 +21,7 @@ const u32 cim_verb_data[] = { 0x10ec0888, /* Codec Vendor / Device ID: Realtek */ 0x10ec0888, /* Subsystem ID */ - 0x0000000f, /* Number of 4 dword sets */ + 15, /* Number of 4 dword sets */ /* NID 0x01: Subsystem ID. */ AZALIA_SUBVENDOR(0x0, 0x10ec0888), @@ -69,7 +69,7 @@ const u32 cim_verb_data[] = { 0x80862806, /* Codec Vendor / Device ID: Intel */ 0x80860101, /* Subsystem ID */ - 0x00000004, /* Number of 4 dword sets */ + 4, /* Number of 4 dword sets */ /* NID 0x01: Subsystem ID. */ AZALIA_SUBVENDOR(0x3, 0x80860101), diff --git a/src/mainboard/gigabyte/ga-h61m-s2pv/variants/ga-h61m-s2pv/hda_verb.c b/src/mainboard/gigabyte/ga-h61m-s2pv/variants/ga-h61m-s2pv/hda_verb.c index 93c7e11618..a0e0614637 100644 --- a/src/mainboard/gigabyte/ga-h61m-s2pv/variants/ga-h61m-s2pv/hda_verb.c +++ b/src/mainboard/gigabyte/ga-h61m-s2pv/variants/ga-h61m-s2pv/hda_verb.c @@ -19,7 +19,7 @@ const u32 cim_verb_data[] = { 0x10ec0887, /* Realtek ALC887 */ 0x1458a002, /* Subsystem ID */ - 0x0000000f, /* Number of 4 dword sets */ + 15, /* Number of 4 dword sets */ AZALIA_SUBVENDOR(0x2, 0x1458a002), AZALIA_PIN_CFG(0x2, 0x11, 0x411111f0), AZALIA_PIN_CFG(0x2, 0x12, 0x411111f0), diff --git a/src/mainboard/gigabyte/ga-h61m-s2pv/variants/ga-h61ma-d3v/hda_verb.c b/src/mainboard/gigabyte/ga-h61m-s2pv/variants/ga-h61ma-d3v/hda_verb.c index e160538d9f..8860993e27 100644 --- a/src/mainboard/gigabyte/ga-h61m-s2pv/variants/ga-h61ma-d3v/hda_verb.c +++ b/src/mainboard/gigabyte/ga-h61m-s2pv/variants/ga-h61ma-d3v/hda_verb.c @@ -19,7 +19,7 @@ const u32 cim_verb_data[] = { 0x10ec0887, /* Realtek ALC887 */ 0x1458a002, /* Subsystem ID */ - 0x0000000f, /* Number of 4 dword sets */ + 15, /* Number of 4 dword sets */ AZALIA_SUBVENDOR(0x2, 0x1458a002), AZALIA_PIN_CFG(0x2, 0x11, 0x411110f0), AZALIA_PIN_CFG(0x2, 0x12, 0x411111f0), diff --git a/src/mainboard/google/butterfly/hda_verb.c b/src/mainboard/google/butterfly/hda_verb.c index caf8b4afe8..fc34e5672d 100644 --- a/src/mainboard/google/butterfly/hda_verb.c +++ b/src/mainboard/google/butterfly/hda_verb.c @@ -26,7 +26,7 @@ const u32 cim_verb_data[] = { /* coreboot specific header */ 0x111D76E5, // Codec Vendor / Device ID: IDT 92HD99 0x103C18F9, // Subsystem ID - 0x00000073, // Number of 4 dword sets + 115, // Number of 4 dword sets /* Bits 31:28 - Codec Address */ /* Bits 27:20 - NID */ @@ -206,7 +206,7 @@ const u32 cim_verb_data[] = { /* coreboot specific header */ 0x80862806, // Codec Vendor / Device ID: Intel PantherPoint HDMI 0x80860101, // Subsystem ID - 0x00000004, // Number of IDs + 4, // Number of IDs /* NID 0x01, HDA Codec Subsystem ID Verb Table: 0x80860101 */ AZALIA_SUBVENDOR(0x3, 0x80860101), diff --git a/src/mainboard/hp/2570p/hda_verb.c b/src/mainboard/hp/2570p/hda_verb.c index 3c4c734c4c..a8e0729ca8 100644 --- a/src/mainboard/hp/2570p/hda_verb.c +++ b/src/mainboard/hp/2570p/hda_verb.c @@ -21,7 +21,7 @@ const u32 cim_verb_data[] = { 0x111d7605, /* Codec Vendor / Device ID: IDT */ 0x103c17df, /* Subsystem ID */ - 0x0000000b, /* Number of 4 dword sets */ + 11, /* Number of 4 dword sets */ /* NID 0x01: Subsystem ID. */ AZALIA_SUBVENDOR(0x0, 0x103c17df), @@ -57,13 +57,13 @@ const u32 cim_verb_data[] = { 0x11c11040, /* Codec Vendor / Device ID: LSI */ 0x103c3066, /* Subsystem ID */ - 0x00000001, /* Number of 4 dword sets */ + 1, /* Number of 4 dword sets */ /* NID 0x01: Subsystem ID. */ AZALIA_SUBVENDOR(0x1, 0x103c3066), 0x80862806, /* Codec Vendor / Device ID: Intel */ 0x80860101, /* Subsystem ID */ - 0x00000004, /* Number of 4 dword sets */ + 4, /* Number of 4 dword sets */ /* NID 0x01: Subsystem ID. */ AZALIA_SUBVENDOR(0x3, 0x80860101), diff --git a/src/mainboard/hp/2760p/hda_verb.c b/src/mainboard/hp/2760p/hda_verb.c index 6a62cf1b8b..48b730a441 100644 --- a/src/mainboard/hp/2760p/hda_verb.c +++ b/src/mainboard/hp/2760p/hda_verb.c @@ -21,7 +21,7 @@ const u32 cim_verb_data[] = { 0x111d7605, /* Codec Vendor / Device ID: IDT */ 0x103c162a, /* Subsystem ID */ - 0x0000000b, /* Number of 4 dword sets */ + 11, /* Number of 4 dword sets */ /* NID 0x01: Subsystem ID. */ AZALIA_SUBVENDOR(0x0, 0x103c162a), @@ -57,13 +57,13 @@ const u32 cim_verb_data[] = { 0x11c11040, /* Codec Vendor / Device ID: LSI */ 0x103c3066, /* Subsystem ID */ - 0x00000001, /* Number of 4 dword sets */ + 1, /* Number of 4 dword sets */ /* NID 0x01: Subsystem ID. */ AZALIA_SUBVENDOR(0x1, 0x103c3066), 0x80862805, /* Codec Vendor / Device ID: Intel */ 0x80860101, /* Subsystem ID */ - 0x00000004, /* Number of 4 dword sets */ + 4, /* Number of 4 dword sets */ /* NID 0x01: Subsystem ID. */ AZALIA_SUBVENDOR(0x3, 0x80860101), diff --git a/src/mainboard/hp/8460p/hda_verb.c b/src/mainboard/hp/8460p/hda_verb.c index 8436707410..964301334a 100644 --- a/src/mainboard/hp/8460p/hda_verb.c +++ b/src/mainboard/hp/8460p/hda_verb.c @@ -21,7 +21,7 @@ const u32 cim_verb_data[] = { 0x111d7605, /* Codec Vendor / Device ID: IDT */ 0x103c3588, /* Subsystem ID */ - 0x0000000b, /* Number of 4 dword sets */ + 11, /* Number of 4 dword sets */ /* NID 0x01: Subsystem ID. */ AZALIA_SUBVENDOR(0x0, 0x103c3588), @@ -57,7 +57,7 @@ const u32 cim_verb_data[] = { 0x11c11040, /* Codec Vendor / Device ID: LSI */ 0x103c3066, /* Subsystem ID */ - 0x00000001, /* Number of 4 dword sets */ + 1, /* Number of 4 dword sets */ /* NID 0x01: Subsystem ID. */ AZALIA_SUBVENDOR(0x1, 0x103c3066), }; diff --git a/src/mainboard/hp/8470p/hda_verb.c b/src/mainboard/hp/8470p/hda_verb.c index 0d7389a39e..a24aeb2dc8 100644 --- a/src/mainboard/hp/8470p/hda_verb.c +++ b/src/mainboard/hp/8470p/hda_verb.c @@ -21,7 +21,7 @@ const u32 cim_verb_data[] = { 0x111d7605, /* Codec Vendor / Device ID: IDT */ 0x103c17c2, /* Subsystem ID */ - 0x0000000b, /* Number of 4 dword sets */ + 11, /* Number of 4 dword sets */ /* NID 0x01: Subsystem ID. */ AZALIA_SUBVENDOR(0x0, 0x103c17c2), @@ -57,7 +57,7 @@ const u32 cim_verb_data[] = { 0x80862806, /* Codec Vendor / Device ID: Intel */ 0x80860101, /* Subsystem ID */ - 0x00000004, /* Number of 4 dword sets */ + 4, /* Number of 4 dword sets */ /* NID 0x01: Subsystem ID. */ AZALIA_SUBVENDOR(0x3, 0x80860101), diff --git a/src/mainboard/hp/8770w/hda_verb.c b/src/mainboard/hp/8770w/hda_verb.c index 51869cb54d..cc66a316ce 100644 --- a/src/mainboard/hp/8770w/hda_verb.c +++ b/src/mainboard/hp/8770w/hda_verb.c @@ -22,7 +22,7 @@ const u32 cim_verb_data[] = { 0x111d7605, /* Codec Vendor / Device ID: IDT */ 0x103c176c, /* Subsystem ID */ - 0x0000000b, /* Number of 4 dword sets */ + 11, /* Number of 4 dword sets */ /* NID 0x01: Subsystem ID. */ AZALIA_SUBVENDOR(0x0, 0x103c176c), diff --git a/src/mainboard/hp/compaq_8200_elite_sff/hda_verb.c b/src/mainboard/hp/compaq_8200_elite_sff/hda_verb.c index 4b90aab935..907ad2f61c 100644 --- a/src/mainboard/hp/compaq_8200_elite_sff/hda_verb.c +++ b/src/mainboard/hp/compaq_8200_elite_sff/hda_verb.c @@ -21,7 +21,7 @@ const u32 cim_verb_data[] = { 0x10ec0662, /* Codec Vendor / Device ID: Realtek */ 0x103c1495, /* Subsystem ID */ - 0x0000000b, /* Number of 4 dword sets */ + 11, /* Number of 4 dword sets */ /* NID 0x01: Subsystem ID. */ AZALIA_SUBVENDOR(0x0, 0x103c1495), @@ -57,7 +57,7 @@ const u32 cim_verb_data[] = { 0x80862805, /* Codec Vendor / Device ID: Intel */ 0x80861495, /* Subsystem ID */ - 0x00000004, /* Number of 4 dword sets */ + 4, /* Number of 4 dword sets */ /* NID 0x01: Subsystem ID. */ AZALIA_SUBVENDOR(0x3, 0x80861495), diff --git a/src/mainboard/hp/folio_9470m/hda_verb.c b/src/mainboard/hp/folio_9470m/hda_verb.c index 3abd5bed3e..14d181ff89 100644 --- a/src/mainboard/hp/folio_9470m/hda_verb.c +++ b/src/mainboard/hp/folio_9470m/hda_verb.c @@ -21,7 +21,7 @@ const u32 cim_verb_data[] = { 0x111d76e0, /* Codec Vendor / Device ID: IDT */ 0x103c18df, /* Subsystem ID */ - 0x0000000b, /* Number of 4 dword sets */ + 11, /* Number of 4 dword sets */ /* NID 0x01: Subsystem ID. */ AZALIA_SUBVENDOR(0x0, 0x103c18df), @@ -57,7 +57,7 @@ const u32 cim_verb_data[] = { 0x80862806, /* Codec Vendor / Device ID: Intel */ 0x80860101, /* Subsystem ID */ - 0x00000004, /* Number of 4 dword sets */ + 4, /* Number of 4 dword sets */ /* NID 0x01: Subsystem ID. */ AZALIA_SUBVENDOR(0x3, 0x80860101), diff --git a/src/mainboard/hp/revolve_810_g1/hda_verb.c b/src/mainboard/hp/revolve_810_g1/hda_verb.c index c7d5662b5a..693ee40a46 100644 --- a/src/mainboard/hp/revolve_810_g1/hda_verb.c +++ b/src/mainboard/hp/revolve_810_g1/hda_verb.c @@ -21,7 +21,7 @@ const u32 cim_verb_data[] = { 0x111d76e0, /* Codec Vendor / Device ID: IDT */ 0x103c18f8, /* Subsystem ID */ - 0x0000000b, /* Number of 4 dword sets */ + 11, /* Number of 4 dword sets */ /* NID 0x01: Subsystem ID. */ AZALIA_SUBVENDOR(0x0, 0x103c18f8), @@ -57,13 +57,13 @@ const u32 cim_verb_data[] = { 0x11c11040, /* Codec Vendor / Device ID: LSI */ 0x103c3066, /* Subsystem ID */ - 0x00000001, /* Number of 4 dword sets */ + 1, /* Number of 4 dword sets */ /* NID 0x01: Subsystem ID. */ AZALIA_SUBVENDOR(0x1, 0x103c3066), 0x80862806, /* Codec Vendor / Device ID: Intel */ 0x80860101, /* Subsystem ID */ - 0x00000004, /* Number of 4 dword sets */ + 4, /* Number of 4 dword sets */ /* NID 0x01: Subsystem ID. */ AZALIA_SUBVENDOR(0x3, 0x80860101), diff --git a/src/mainboard/hp/z220_sff_workstation/hda_verb.c b/src/mainboard/hp/z220_sff_workstation/hda_verb.c index 91804c187b..9ded3ec136 100644 --- a/src/mainboard/hp/z220_sff_workstation/hda_verb.c +++ b/src/mainboard/hp/z220_sff_workstation/hda_verb.c @@ -21,7 +21,7 @@ const u32 cim_verb_data[] = { 0x10ec0221, /* Codec Vendor / Device ID: Realtek */ 0x103c1791, /* Subsystem ID */ - 0x0000000b, /* Number of 4 dword sets */ + 11, /* Number of 4 dword sets */ /* NID 0x01: Subsystem ID. */ AZALIA_SUBVENDOR(0x0, 0x103c1791), @@ -57,7 +57,7 @@ const u32 cim_verb_data[] = { 0x80862806, /* Codec Vendor / Device ID: Intel */ 0x103c1791, /* Subsystem ID */ - 0x00000004, /* Number of 4 dword sets */ + 4, /* Number of 4 dword sets */ /* NID 0x01: Subsystem ID. */ AZALIA_SUBVENDOR(0x3, 0x103c1791), diff --git a/src/mainboard/intel/dcp847ske/hda_verb.c b/src/mainboard/intel/dcp847ske/hda_verb.c index b00034750c..3b7190d9e3 100644 --- a/src/mainboard/intel/dcp847ske/hda_verb.c +++ b/src/mainboard/intel/dcp847ske/hda_verb.c @@ -21,7 +21,7 @@ const u32 cim_verb_data[] = { 0x80862806, /* Codec Vendor / Device ID: Intel */ 0x80860101, /* Subsystem ID */ - 0x00000004, /* Number of 4 dword sets */ + 4, /* Number of 4 dword sets */ /* NID 0x01: Subsystem ID. */ AZALIA_SUBVENDOR(0x3, 0x80860101), diff --git a/src/mainboard/lenovo/l520/hda_verb.c b/src/mainboard/lenovo/l520/hda_verb.c index 30a4a61be2..bca06f5e56 100644 --- a/src/mainboard/lenovo/l520/hda_verb.c +++ b/src/mainboard/lenovo/l520/hda_verb.c @@ -21,7 +21,7 @@ const u32 cim_verb_data[] = { 0x10ec0269, /* Codec Vendor / Device ID: Realtek */ 0x17aa21de, /* Subsystem ID */ - 0x0000000b, /* Number of 4 dword sets */ + 11, /* Number of 4 dword sets */ /* NID 0x01: Subsystem ID. */ AZALIA_SUBVENDOR(0x0, 0x17aa21de), @@ -57,7 +57,7 @@ const u32 cim_verb_data[] = { 0x80862805, /* Codec Vendor / Device ID: Intel */ 0x80860101, /* Subsystem ID */ - 0x00000004, /* Number of 4 dword sets */ + 4, /* Number of 4 dword sets */ /* NID 0x01: Subsystem ID. */ AZALIA_SUBVENDOR(0x3, 0x80860101), diff --git a/src/mainboard/lenovo/s230u/hda_verb.c b/src/mainboard/lenovo/s230u/hda_verb.c index f2da2c4756..85150e51a5 100644 --- a/src/mainboard/lenovo/s230u/hda_verb.c +++ b/src/mainboard/lenovo/s230u/hda_verb.c @@ -22,7 +22,7 @@ const u32 cim_verb_data[] = { /* coreboot specific header */ 0x10ec0269, // Codec Vendor / Device ID: Realtek ALC269VC 0x17aa21fa, // Subsystem ID - 0x0000000c, // Number of 4 dword sets + 12, // Number of 4 dword sets /* Bits 31:28 - Codec Address */ /* Bits 27:20 - NID */ @@ -106,7 +106,7 @@ const u32 cim_verb_data[] = { /* coreboot specific header */ 0x80862806, // Codec Vendor / Device ID: Intel PantherPoint HDMI 0x80860101, // Subsystem ID - 0x00000004, // Number of IDs + 4, // Number of IDs /* NID 0x01, HDA Codec Subsystem ID Verb Table: 0x80860101 */ AZALIA_SUBVENDOR(0x3, 0x80860101), diff --git a/src/mainboard/lenovo/t410/hda_verb.c b/src/mainboard/lenovo/t410/hda_verb.c index 752e5da67b..2b871f6280 100644 --- a/src/mainboard/lenovo/t410/hda_verb.c +++ b/src/mainboard/lenovo/t410/hda_verb.c @@ -20,7 +20,7 @@ const u32 cim_verb_data[] = { /* coreboot specific header */ 0x14F15069, /* Codec Vendor / Device ID: Conexant CX20585 */ 0x17AA214C, /* Subsystem ID */ - 0x0000000B, /* Number of 4 dword sets */ + 11, /* Number of 4 dword sets */ AZALIA_SUBVENDOR(0x0, 0x17AA214C), AZALIA_PIN_CFG(0x0, 0x19, 0x042110F0), @@ -36,7 +36,7 @@ const u32 cim_verb_data[] = { 0x80862804, /* Codec Vendor / Device ID: Intel Ibexpeak HDMI. */ 0x17AA21B5, /* Subsystem ID */ - 0x00000004, /* Number of 4 dword sets */ + 4, /* Number of 4 dword sets */ AZALIA_SUBVENDOR(0x3, 0x17AA21B5), AZALIA_PIN_CFG(0x3, 0x04, 0x18560010), diff --git a/src/mainboard/lenovo/t420/hda_verb.c b/src/mainboard/lenovo/t420/hda_verb.c index 18a61a2436..9287d4adbe 100644 --- a/src/mainboard/lenovo/t420/hda_verb.c +++ b/src/mainboard/lenovo/t420/hda_verb.c @@ -27,7 +27,7 @@ const u32 cim_verb_data[] = { /* coreboot specific header */ 0x14f1506e, // Codec Vendor / Device ID: Conexant CX20590 - Schematic show CX20672 0x17aa21ce, // Subsystem ID - 0x0000000d, // Number of 4 dword sets + 13, // Number of 4 dword sets /* Bits 31:28 - Codec Address */ /* Bits 27:20 - NID */ diff --git a/src/mainboard/lenovo/t420s/hda_verb.c b/src/mainboard/lenovo/t420s/hda_verb.c index cad2050755..8a9c3e5b77 100644 --- a/src/mainboard/lenovo/t420s/hda_verb.c +++ b/src/mainboard/lenovo/t420s/hda_verb.c @@ -27,7 +27,7 @@ const u32 cim_verb_data[] = { /* coreboot specific header */ 0x14f1506e, // Codec Vendor / Device ID: Conexant CX20590 - Schematic show CX20672 0x17aa21d2, // Subsystem ID - 0x0000000d, // Number of 4 dword sets + 13, // Number of 4 dword sets /* Bits 31:28 - Codec Address */ /* Bits 27:20 - NID */ diff --git a/src/mainboard/lenovo/t430/hda_verb.c b/src/mainboard/lenovo/t430/hda_verb.c index 02f433f3c1..255198f044 100644 --- a/src/mainboard/lenovo/t430/hda_verb.c +++ b/src/mainboard/lenovo/t430/hda_verb.c @@ -55,7 +55,7 @@ const u32 cim_verb_data[] = { 0x80862806, /* Codec Vendor / Device ID: Intel */ 0x80860101, /* Subsystem ID */ - 0x00000004, /* Number of 4 dword sets */ + 4, /* Number of 4 dword sets */ /* NID 0x01: Subsystem ID. */ AZALIA_SUBVENDOR(0x3, 0x80860101), diff --git a/src/mainboard/lenovo/t430s/variants/t430s/hda_verb.c b/src/mainboard/lenovo/t430s/variants/t430s/hda_verb.c index f73434d53e..c5c17b8061 100644 --- a/src/mainboard/lenovo/t430s/variants/t430s/hda_verb.c +++ b/src/mainboard/lenovo/t430s/variants/t430s/hda_verb.c @@ -27,7 +27,7 @@ const u32 cim_verb_data[] = { /* coreboot specific header */ 0x10ec0269, // Codec Vendor / Device ID: Realtek ALC269VC 0x17aa21fb, // Subsystem ID - 0x00000013, // Number of 4 dword sets + 19, // Number of 4 dword sets /* Bits 31:28 - Codec Address */ /* Bits 27:20 - NID */ @@ -105,7 +105,7 @@ const u32 cim_verb_data[] = { /* coreboot specific header */ 0x80862806, // Codec Vendor / Device ID: Intel PantherPoint HDMI 0x80860101, // Subsystem ID - 0x00000004, // Number of IDs + 4, // Number of IDs /* NID 0x01, HDA Codec Subsystem ID Verb Table: 0x80860101 */ AZALIA_SUBVENDOR(0x3, 0x80860101), diff --git a/src/mainboard/lenovo/t430s/variants/t431s/hda_verb.c b/src/mainboard/lenovo/t430s/variants/t431s/hda_verb.c index 179fba0500..1c5d376247 100644 --- a/src/mainboard/lenovo/t430s/variants/t431s/hda_verb.c +++ b/src/mainboard/lenovo/t430s/variants/t431s/hda_verb.c @@ -21,7 +21,7 @@ const u32 cim_verb_data[] = { 0x10ec0269, /* Codec Vendor / Device ID: Realtek */ 0x17aa2208, /* Subsystem ID */ - 0x0000000b, /* Number of 4 dword sets */ + 11, /* Number of 4 dword sets */ /* NID 0x01: Subsystem ID. */ AZALIA_SUBVENDOR(0x0, 0x17aa2208), @@ -57,7 +57,7 @@ const u32 cim_verb_data[] = { 0x80862806, /* Codec Vendor / Device ID: Intel */ 0x80860101, /* Subsystem ID */ - 0x00000004, /* Number of 4 dword sets */ + 4, /* Number of 4 dword sets */ /* NID 0x01: Subsystem ID. */ AZALIA_SUBVENDOR(0x3, 0x80860101), diff --git a/src/mainboard/lenovo/t520/hda_verb.c b/src/mainboard/lenovo/t520/hda_verb.c index dae692d4ab..2d10e35b19 100644 --- a/src/mainboard/lenovo/t520/hda_verb.c +++ b/src/mainboard/lenovo/t520/hda_verb.c @@ -27,7 +27,7 @@ const u32 cim_verb_data[] = { /* coreboot specific header */ 0x14f1506e, // Codec Vendor / Device ID: Conexant CX20590 - Schematic shows CX20672 0x17aa21cf, // Subsystem ID - 0x0000000d, // Number of 4 dword sets + 13, // Number of 4 dword sets /* Bits 31:28 - Codec Address */ /* Bits 27:20 - NID */ diff --git a/src/mainboard/lenovo/t530/hda_verb.c b/src/mainboard/lenovo/t530/hda_verb.c index 154b3146a0..f8876aa1c8 100644 --- a/src/mainboard/lenovo/t530/hda_verb.c +++ b/src/mainboard/lenovo/t530/hda_verb.c @@ -27,7 +27,7 @@ const u32 cim_verb_data[] = { /* coreboot specific header */ 0x10ec0269, // Codec Vendor / Device ID: Realtek ALC269VC 0x17aa21fa, // Subsystem ID - 0x00000012, // Number of 4 dword sets + 18, // Number of 4 dword sets /* Bits 31:28 - Codec Address */ /* Bits 27:20 - NID */ @@ -104,7 +104,7 @@ const u32 cim_verb_data[] = { /* coreboot specific header */ 0x80862806, // Codec Vendor / Device ID: Intel PantherPoint HDMI 0x80860101, // Subsystem ID - 0x00000004, // Number of IDs + 4, // Number of IDs /* NID 0x01, HDA Codec Subsystem ID Verb Table: 0x80860101 */ AZALIA_SUBVENDOR(0x3, 0x80860101), diff --git a/src/mainboard/lenovo/t60/hda_verb.c b/src/mainboard/lenovo/t60/hda_verb.c index 35077766f8..216696b22b 100644 --- a/src/mainboard/lenovo/t60/hda_verb.c +++ b/src/mainboard/lenovo/t60/hda_verb.c @@ -16,7 +16,7 @@ const u32 cim_verb_data[] = { 0x11d41981, /* Codec Vendor / Device ID: Analog Devices AD1981 */ 0x17aa2025, /* Subsystem ID */ - 0x0000000b, /* Number of 4 dword sets */ + 11, /* Number of 4 dword sets */ AZALIA_SUBVENDOR(0x0, 0x17aa2025), diff --git a/src/mainboard/lenovo/x1_carbon_gen1/hda_verb.c b/src/mainboard/lenovo/x1_carbon_gen1/hda_verb.c index 2a216d3981..1946286cff 100644 --- a/src/mainboard/lenovo/x1_carbon_gen1/hda_verb.c +++ b/src/mainboard/lenovo/x1_carbon_gen1/hda_verb.c @@ -20,7 +20,7 @@ const u32 cim_verb_data[] = { 0x10ec0269, /* Codec Vendor / Device ID: Realtek */ 0x17aa21f9, /* Subsystem ID */ - 0x0000000b, /* Number of 4 dword sets */ + 11, /* Number of 4 dword sets */ /* NID 0x01: Subsystem ID. */ AZALIA_SUBVENDOR(0x0, 0x17aa21f9), @@ -56,7 +56,7 @@ const u32 cim_verb_data[] = { 0x80862806, /* Codec Vendor / Device ID: Intel */ 0x80860101, /* Subsystem ID */ - 0x00000004, /* Number of 4 dword sets */ + 4, /* Number of 4 dword sets */ /* NID 0x01: Subsystem ID. */ AZALIA_SUBVENDOR(0x3, 0x80860101), diff --git a/src/mainboard/lenovo/x201/hda_verb.c b/src/mainboard/lenovo/x201/hda_verb.c index 820e2c5f96..25a87f57f2 100644 --- a/src/mainboard/lenovo/x201/hda_verb.c +++ b/src/mainboard/lenovo/x201/hda_verb.c @@ -20,7 +20,7 @@ const u32 cim_verb_data[] = { /* coreboot specific header */ 0x14F15069, /* Codec Vendor / Device ID: Conexant CX20585 */ 0x17AA2155, /* Subsystem ID */ - 0x0000000B, /* Number of 4 dword sets */ + 11, /* Number of 4 dword sets */ /* NID 0x01: Subsystem ID. */ AZALIA_SUBVENDOR(0x0, 0x17AA2155), @@ -57,7 +57,7 @@ const u32 cim_verb_data[] = { 0x80862804, /* Codec Vendor / Device ID: Intel Ibexpeak HDMI. */ 0x17aa21b5, /* Subsystem ID */ - 0x00000004, /* Number of 4 dword sets */ + 4, /* Number of 4 dword sets */ /* NID 0x01, HDA Codec Subsystem ID Verb Table: 0x17aa21b5 */ AZALIA_SUBVENDOR(0x3, 0x17AA21B5), diff --git a/src/mainboard/lenovo/x220/hda_verb.c b/src/mainboard/lenovo/x220/hda_verb.c index d94c320b9c..b7b670d77a 100644 --- a/src/mainboard/lenovo/x220/hda_verb.c +++ b/src/mainboard/lenovo/x220/hda_verb.c @@ -27,7 +27,7 @@ const u32 cim_verb_data[] = { /* coreboot specific header */ 0x14f1506e, // Codec Vendor / Device ID: Conexant CX20590 0x17aa21db, // Subsystem ID - 0x0000000d, // Number of 4 dword sets + 13, // Number of 4 dword sets /* Bits 31:28 - Codec Address */ /* Bits 27:20 - NID */ @@ -71,7 +71,7 @@ const u32 cim_verb_data[] = { /* coreboot specific header */ 0x80862805, // Codec Vendor / Device ID: Intel PantherPoint HDMI 0x80860101, // Subsystem ID - 0x00000004, // Number of IDs + 4, // Number of IDs /* NID 0x01, HDA Codec Subsystem ID Verb Table: 0x80860101 */ AZALIA_SUBVENDOR(0x3, 0x80860101), diff --git a/src/mainboard/lenovo/x230/hda_verb.c b/src/mainboard/lenovo/x230/hda_verb.c index 792579aa32..0393ff50a6 100644 --- a/src/mainboard/lenovo/x230/hda_verb.c +++ b/src/mainboard/lenovo/x230/hda_verb.c @@ -27,7 +27,7 @@ const u32 cim_verb_data[] = { /* coreboot specific header */ 0x10ec0269, // Codec Vendor / Device ID: Realtek ALC269VC 0x17aa21fa, // Subsystem ID - 0x00000013, // Number of 4 dword sets + 19, // Number of 4 dword sets /* Bits 31:28 - Codec Address */ /* Bits 27:20 - NID */ @@ -112,7 +112,7 @@ const u32 cim_verb_data[] = { /* coreboot specific header */ 0x80862806, // Codec Vendor / Device ID: Intel PantherPoint HDMI 0x80860101, // Subsystem ID - 0x00000004, // Number of IDs + 4, // Number of IDs /* NID 0x01, HDA Codec Subsystem ID Verb Table: 0x80860101 */ AZALIA_SUBVENDOR(0x3, 0x80860101), diff --git a/src/mainboard/lenovo/x60/hda_verb.c b/src/mainboard/lenovo/x60/hda_verb.c index 35077766f8..216696b22b 100644 --- a/src/mainboard/lenovo/x60/hda_verb.c +++ b/src/mainboard/lenovo/x60/hda_verb.c @@ -16,7 +16,7 @@ const u32 cim_verb_data[] = { 0x11d41981, /* Codec Vendor / Device ID: Analog Devices AD1981 */ 0x17aa2025, /* Subsystem ID */ - 0x0000000b, /* Number of 4 dword sets */ + 11, /* Number of 4 dword sets */ AZALIA_SUBVENDOR(0x0, 0x17aa2025), diff --git a/src/mainboard/msi/ms7707/hda_verb.c b/src/mainboard/msi/ms7707/hda_verb.c index 6a6cf41553..7ff2bee168 100644 --- a/src/mainboard/msi/ms7707/hda_verb.c +++ b/src/mainboard/msi/ms7707/hda_verb.c @@ -21,7 +21,7 @@ const u32 cim_verb_data[] = { 0x10ec0887, /* Codec Vendor / Device ID: Realtek */ 0x14627707, /* Subsystem ID */ - 0x0000000f, /* Number of 4 dword sets */ + 15, /* Number of 4 dword sets */ /* NID 0x01: Subsystem ID. */ AZALIA_SUBVENDOR(0x0, 0x14627707), diff --git a/src/mainboard/packardbell/ms2290/hda_verb.c b/src/mainboard/packardbell/ms2290/hda_verb.c index 1932ff9963..d458cd6eed 100644 --- a/src/mainboard/packardbell/ms2290/hda_verb.c +++ b/src/mainboard/packardbell/ms2290/hda_verb.c @@ -20,7 +20,7 @@ const u32 cim_verb_data[] = { /* coreboot specific header */ 0x10ec0272, /* Codec Vendor / Device ID: Realtek ALC272X */ 0x10250379, /* Subsystem ID */ - 0x00000006, /* Number of 4 dword sets */ + 6, /* Number of 4 dword sets */ /* NID 0x01: Subsystem ID. */ AZALIA_SUBVENDOR(0x0, 0x10250379), @@ -42,7 +42,7 @@ const u32 cim_verb_data[] = { 0x80862804, /* Codec Vendor / Device ID: Intel Ibexpeak HDMI. */ 0x80860101, /* Subsystem ID */ - 0x00000004, /* Number of 4 dword sets */ + 4, /* Number of 4 dword sets */ /* NID 0x01, HDA Codec Subsystem ID Verb Table: 0x17aa21b5 */ AZALIA_SUBVENDOR(0x3, 0x80860101), diff --git a/src/mainboard/sapphire/pureplatinumh61/hda_verb.c b/src/mainboard/sapphire/pureplatinumh61/hda_verb.c index cf723d0867..9be242e501 100644 --- a/src/mainboard/sapphire/pureplatinumh61/hda_verb.c +++ b/src/mainboard/sapphire/pureplatinumh61/hda_verb.c @@ -20,7 +20,7 @@ const u32 cim_verb_data[] = { 0x10ec0892, /* Codec Vendor / Device ID: Realtek */ 0x10ec0000, /* Subsystem ID */ - 0x0000000f, /* Number of 4 dword sets */ + 15, /* Number of 4 dword sets */ /* NID 0x01: Subsystem ID. */ AZALIA_SUBVENDOR(0x2, 0x10ec0000), @@ -68,7 +68,7 @@ const u32 cim_verb_data[] = { 0x80862805, /* Codec Vendor / Device ID: Intel */ 0x80860101, /* Subsystem ID */ - 0x00000004, /* Number of 4 dword sets */ + 4, /* Number of 4 dword sets */ /* NID 0x01: Subsystem ID. */ AZALIA_SUBVENDOR(0x3, 0x80860101), From fd6fb289ce294b3468c7770b697e78932e281b09 Mon Sep 17 00:00:00 2001 From: Marshall Dawson Date: Mon, 25 Nov 2019 17:53:29 -0700 Subject: [PATCH 0627/1242] vc/amd/pi: Allow 00670F00 to build with no binaryPI Make the default binaryPI image strings for all stoneyridge-based APUs depend on USE_AMD_BLOBS. Ensure the build completes without names, and without images. Change-Id: I74a38efa2a4ad2f9f12a1f8e7fb8694d0ab9dd1e Signed-off-by: Marshall Dawson Reviewed-on: https://review.coreboot.org/c/coreboot/+/37228 Tested-by: build bot (Jenkins) Reviewed-by: Richard Spiegel --- src/vendorcode/amd/pi/00670F00/Makefile.inc | 23 ++++++++++++++++++++- src/vendorcode/amd/pi/Kconfig | 12 +++++------ 2 files changed, 28 insertions(+), 7 deletions(-) diff --git a/src/vendorcode/amd/pi/00670F00/Makefile.inc b/src/vendorcode/amd/pi/00670F00/Makefile.inc index fef7dff342..947134f1d9 100644 --- a/src/vendorcode/amd/pi/00670F00/Makefile.inc +++ b/src/vendorcode/amd/pi/00670F00/Makefile.inc @@ -116,10 +116,22 @@ ramstage-libs += $(agesa_output_path)/libagesa.a ####################################################################### +warn_no_agesa: + printf "\n\t** WARNING **\n" + printf "coreboot has been built with no AGESA support. Successfully " + printf "booting this image will be impossible.\n\n" + +PHONY+=warn_no_amdfw + ifeq ($(CONFIG_AGESA_SPLIT_MEMORY_FILES), y) # convert input elf to rmodule AGESA_POST_MEM_INPUT_ELF = $(call strip_quotes,$(CONFIG_AGESA_POST_MEMORY_BINARY_PI_FILE)) + +# If no post-mem file then also skip pre-mem file +ifeq ($(AGESA_POST_MEM_INPUT_ELF,)) +files_added:: warn_no_agesa +else AGESA_POST_MEM_ELF = $(objcbfs)/$(patsubst %.elf,%.debug,$(notdir $(AGESA_POST_MEM_INPUT_ELF))) AGESA_POST_MEM_ELF_RMOD = $(AGESA_POST_MEM_ELF).rmod @@ -140,10 +152,18 @@ cbfs-files-$(CONFIG_CPU_AMD_AGESA_BINARY_PI) += $(CONFIG_AGESA_POST_MEMORY_CBFS_ $(CONFIG_AGESA_POST_MEMORY_CBFS_NAME)-file := $(AGESA_POST_MEM_ELF_RMOD) $(CONFIG_AGESA_POST_MEMORY_CBFS_NAME)-type := stage $(CONFIG_AGESA_POST_MEMORY_CBFS_NAME)-compression := $(CBFS_COMPRESS_FLAG) + +endif # AGESA_POST_MEM_INPUT_ELF == "" + +else # CONFIG_AGESA_SPLIT_MEMORY_FILES + +AGESA_BINARYPI_INPUT_FILE = $(call strip_quotes,$(CONFIG_AGESA_BINARY_PI_FILE)) +ifeq ($(AGESA_BINARYPI_INPUT_FILE),) +files_added:: warn_no_agesa else cbfs-files-$(CONFIG_CPU_AMD_AGESA_BINARY_PI) += $(CONFIG_AGESA_CBFS_NAME) -$(CONFIG_AGESA_CBFS_NAME)-file := $(CONFIG_AGESA_BINARY_PI_FILE) +$(CONFIG_AGESA_CBFS_NAME)-file := $(AGESA_BINARYPI_INPUT_FILE) ifeq ($(CONFIG_AGESA_BINARY_PI_AS_STAGE),y) $(CONFIG_AGESA_CBFS_NAME)-type := stage @@ -156,6 +176,7 @@ $(CONFIG_AGESA_CBFS_NAME)-type := raw $(CONFIG_AGESA_CBFS_NAME)-position := $(CONFIG_AGESA_BINARY_PI_LOCATION) endif # CONFIG_AGESA_BINARY_PI_AS_STAGE +endif # AGESA_BINARYPI_INPUT_FILE == "" endif # CONFIG_AGESA_SPLIT_MEMORY_FILES endif diff --git a/src/vendorcode/amd/pi/Kconfig b/src/vendorcode/amd/pi/Kconfig index 06055639fb..73fe4f2f10 100644 --- a/src/vendorcode/amd/pi/Kconfig +++ b/src/vendorcode/amd/pi/Kconfig @@ -44,10 +44,10 @@ config AGESA_BINARY_PI_FILE string "AGESA PI binary file name" default "3rdparty/blobs/pi/amd/00630F01/FP3/AGESA.bin" if CPU_AMD_PI_00630F01 default "3rdparty/blobs/pi/amd/00730F01/FT3b/AGESA.bin" if CPU_AMD_PI_00730F01 - default "3rdparty/blobs/pi/amd/merlinfalcon/$(CONFIG_AMD_SOC_PACKAGE)/AGESA_CZ_FP4.bin" if SOC_AMD_MERLINFALCON && HAVE_MERLINFALCON_BINARIES - default "3rdparty/blobs/pi/amd/00670F00/$(CONFIG_AMD_SOC_PACKAGE)/AGESA.bin" if SOC_AMD_MERLINFALCON && !HAVE_MERLINFALCON_BINARIES - default "3rdparty/blobs/pi/amd/00670F00/$(CONFIG_AMD_SOC_PACKAGE)/AGESA.bin" if SOC_AMD_STONEYRIDGE_FP4 - default "3rdparty/blobs/pi/amd/00670F00/$(CONFIG_AMD_SOC_PACKAGE)/AGESA.bin" if SOC_AMD_STONEYRIDGE_FT4 + default "3rdparty/blobs/pi/amd/merlinfalcon/$(CONFIG_AMD_SOC_PACKAGE)/AGESA_CZ_FP4.bin" if SOC_AMD_MERLINFALCON && HAVE_MERLINFALCON_BINARIES && USE_AMD_BLOBS + default "3rdparty/blobs/pi/amd/00670F00/$(CONFIG_AMD_SOC_PACKAGE)/AGESA.bin" if SOC_AMD_MERLINFALCON && !HAVE_MERLINFALCON_BINARIES && USE_AMD_BLOBS + default "3rdparty/blobs/pi/amd/00670F00/$(CONFIG_AMD_SOC_PACKAGE)/AGESA.bin" if SOC_AMD_STONEYRIDGE_FP4 && USE_AMD_BLOBS + default "3rdparty/blobs/pi/amd/00670F00/$(CONFIG_AMD_SOC_PACKAGE)/AGESA.bin" if SOC_AMD_STONEYRIDGE_FT4 && USE_AMD_BLOBS default "3rdparty/blobs/pi/amd/00660F01/FP4/AGESA.bin" if CPU_AMD_PI_00660F01 help Specify the binary file to use for AMD platform initialization. @@ -72,7 +72,7 @@ config AGESA_SPLIT_MEMORY_FILES config AGESA_PRE_MEMORY_BINARY_PI_FILE string depends on AGESA_SPLIT_MEMORY_FILES - default "3rdparty/blobs/pi/amd/00670F00/FT4/AGESA_premem.elf" if SOC_AMD_STONEYRIDGE_FT4 + default "3rdparty/blobs/pi/amd/00670F00/FT4/AGESA_premem.elf" if SOC_AMD_STONEYRIDGE_FT4 && USE_AMD_BLOBS help Specify the binary file to use for pre-memory AMD platform initialization. @@ -80,7 +80,7 @@ config AGESA_PRE_MEMORY_BINARY_PI_FILE config AGESA_POST_MEMORY_BINARY_PI_FILE string depends on AGESA_SPLIT_MEMORY_FILES - default "3rdparty/blobs/pi/amd/00670F00/FT4/AGESA_postmem.elf" if SOC_AMD_STONEYRIDGE_FT4 + default "3rdparty/blobs/pi/amd/00670F00/FT4/AGESA_postmem.elf" if SOC_AMD_STONEYRIDGE_FT4 && USE_AMD_BLOBS help Specify the binary file to use for post-memory AMD platform initialization. From 7987c1cb6f2140d44eb0aa1a3642ac2a114c20ad Mon Sep 17 00:00:00 2001 From: Marshall Dawson Date: Mon, 25 Nov 2019 08:29:28 -0700 Subject: [PATCH 0628/1242] soc/amd/stoneyridge|vc: Change default locations for blobs Set the default location strings to point to the 3rdparty/amd_blobs files. Change-Id: I5426b8de2501ba55843efc1cda4b03bc3768f8cb Signed-off-by: Marshall Dawson Reviewed-on: https://review.coreboot.org/c/coreboot/+/37222 Tested-by: build bot (Jenkins) Reviewed-by: Richard Spiegel --- src/soc/amd/stoneyridge/Kconfig | 10 +++++----- src/vendorcode/amd/pi/Kconfig | 8 ++++---- 2 files changed, 9 insertions(+), 9 deletions(-) diff --git a/src/soc/amd/stoneyridge/Kconfig b/src/soc/amd/stoneyridge/Kconfig index a5607b4c88..0a3e77d4e0 100644 --- a/src/soc/amd/stoneyridge/Kconfig +++ b/src/soc/amd/stoneyridge/Kconfig @@ -175,8 +175,8 @@ config VGA_BIOS_ID config VGA_BIOS_FILE string default "" if !USE_AMD_BLOBS - default "3rdparty/blobs/soc/amd/merlinfalcon/VBIOS.bin" if AMD_APU_MERLINFALCON - default "3rdparty/blobs/soc/amd/stoneyridge/VBIOS.bin" + default "3rdparty/amd_blobs/stoneyridge/CarrizoGenericVbios.bin" if AMD_APU_MERLINFALCON + default "3rdparty/amd_blobs/stoneyridge/StoneyGenericVbios.bin" config S3_VGA_ROM_RUN bool @@ -216,7 +216,7 @@ config STONEYRIDGE_GEC_FWM config STONEYRIDGE_XHCI_FWM_FILE string "XHCI firmware path and filename" default "" if !USE_AMD_BLOBS - default "3rdparty/blobs/soc/amd/stoneyridge/xhci.bin" + default "3rdparty/amd_blobs/stoneyridge/xhci.bin" depends on STONEYRIDGE_XHCI_FWM config STONEYRIDGE_GEC_FWM_FILE @@ -226,8 +226,8 @@ config STONEYRIDGE_GEC_FWM_FILE config AMD_PUBKEY_FILE string "AMD public Key" default "" if !USE_AMD_BLOBS - default "3rdparty/blobs/soc/amd/merlinfalcon/PSP/AmdPubKeyCZ.bin" if AMD_APU_MERLINFALCON - default "3rdparty/blobs/soc/amd/stoneyridge/PSP/AmdPubKeyST.bin" + default "3rdparty/amd_blobs/stoneyridge/PSP/CZ/AmdPubKeyCZ.bin" if AMD_APU_MERLINFALCON + default "3rdparty/amd_blobs/stoneyridge/PSP/ST/AmdPubKeyST.bin" config STONEYRIDGE_SATA_MODE int "SATA Mode" diff --git a/src/vendorcode/amd/pi/Kconfig b/src/vendorcode/amd/pi/Kconfig index 73fe4f2f10..acf84974af 100644 --- a/src/vendorcode/amd/pi/Kconfig +++ b/src/vendorcode/amd/pi/Kconfig @@ -44,10 +44,10 @@ config AGESA_BINARY_PI_FILE string "AGESA PI binary file name" default "3rdparty/blobs/pi/amd/00630F01/FP3/AGESA.bin" if CPU_AMD_PI_00630F01 default "3rdparty/blobs/pi/amd/00730F01/FT3b/AGESA.bin" if CPU_AMD_PI_00730F01 - default "3rdparty/blobs/pi/amd/merlinfalcon/$(CONFIG_AMD_SOC_PACKAGE)/AGESA_CZ_FP4.bin" if SOC_AMD_MERLINFALCON && HAVE_MERLINFALCON_BINARIES && USE_AMD_BLOBS - default "3rdparty/blobs/pi/amd/00670F00/$(CONFIG_AMD_SOC_PACKAGE)/AGESA.bin" if SOC_AMD_MERLINFALCON && !HAVE_MERLINFALCON_BINARIES && USE_AMD_BLOBS - default "3rdparty/blobs/pi/amd/00670F00/$(CONFIG_AMD_SOC_PACKAGE)/AGESA.bin" if SOC_AMD_STONEYRIDGE_FP4 && USE_AMD_BLOBS - default "3rdparty/blobs/pi/amd/00670F00/$(CONFIG_AMD_SOC_PACKAGE)/AGESA.bin" if SOC_AMD_STONEYRIDGE_FT4 && USE_AMD_BLOBS + default "3rdparty/amd_blobs/stoneyridge/pi/ST/$(CONFIG_AMD_SOC_PACKAGE)/AGESA.bin" if SOC_AMD_MERLINFALCON && HAVE_MERLINFALCON_BINARIES && USE_AMD_BLOBS + default "3rdparty/amd_blobs/stoneyridge/pi/CZ/$(CONFIG_AMD_SOC_PACKAGE)/AGESA.bin" if SOC_AMD_MERLINFALCON && USE_AMD_BLOBS + default "3rdparty/amd_blobs/stoneyridge/pi/ST/$(CONFIG_AMD_SOC_PACKAGE)/AGESA.bin" if SOC_AMD_STONEYRIDGE_FP4 && USE_AMD_BLOBS + default "3rdparty/amd_blobs/stoneyridge/pi/ST/$(CONFIG_AMD_SOC_PACKAGE)/AGESA.bin" if SOC_AMD_STONEYRIDGE_FT4 && USE_AMD_BLOBS default "3rdparty/blobs/pi/amd/00660F01/FP4/AGESA.bin" if CPU_AMD_PI_00660F01 help Specify the binary file to use for AMD platform initialization. From e1988f5e0a3c9f6767cb5c37ea2910bf4b2c99f6 Mon Sep 17 00:00:00 2001 From: Marshall Dawson Date: Mon, 25 Nov 2019 11:15:35 -0700 Subject: [PATCH 0629/1242] soc/amd/stoneyridge|mb: Add Kconfig symbol for Prairie Falcon The stoneyridge code inferred that if Merlin Falcon was built but no Merlin Falcon binaries were present, the intent must be Prairie Falcon. The two falcons are Embedded variants, and Prairie Falcon falls within Family 15h Models 70h-7Fh. Add a Prairie Falcon symbol that can be used explicitely. Drop HAVE_MERLINFALCON_BINARIES. Change-Id: I0d3a1bc302760c18c8fe3d57c955e2bb3bd8153a Signed-off-by: Marshall Dawson Reviewed-on: https://review.coreboot.org/c/coreboot/+/37223 Tested-by: build bot (Jenkins) Reviewed-by: Richard Spiegel --- src/mainboard/amd/padmelon/devicetree.cb | 2 +- src/soc/amd/stoneyridge/Kconfig | 28 ++++++++++++++---------- src/soc/amd/stoneyridge/Makefile.inc | 4 ++++ src/soc/amd/stoneyridge/chip.h | 5 ++--- src/vendorcode/amd/pi/Kconfig | 2 +- 5 files changed, 25 insertions(+), 16 deletions(-) diff --git a/src/mainboard/amd/padmelon/devicetree.cb b/src/mainboard/amd/padmelon/devicetree.cb index 9baee2f2cf..fa83d106ca 100644 --- a/src/mainboard/amd/padmelon/devicetree.cb +++ b/src/mainboard/amd/padmelon/devicetree.cb @@ -16,7 +16,7 @@ chip soc/amd/stoneyridge register "spd_addr_lookup" = " { -#if CONFIG(HAVE_MERLINFALCON_BINARIES) +#if CONFIG(AMD_APU_MERLINFALCON) { {0xA0, 0x00}, {0xA4, 0x00} }, // socket 0 - Channel 0 & 1, slot 0 #else { {0xA0, 0x00} }, // socket 0 - Channel 0, slot 0 diff --git a/src/soc/amd/stoneyridge/Kconfig b/src/soc/amd/stoneyridge/Kconfig index 0a3e77d4e0..d1dd4334de 100644 --- a/src/soc/amd/stoneyridge/Kconfig +++ b/src/soc/amd/stoneyridge/Kconfig @@ -34,15 +34,14 @@ config SOC_AMD_MERLINFALCON help AMD Merlin Falcon FP4 support -config HAVE_MERLINFALCON_BINARIES - depends on AMD_APU_MERLINFALCON - bool "Merlinfalcon binaries are present" - default n +config SOC_AMD_PRAIRIEFALCON + bool + select AMD_APU_PRAIRIEFALCON + select AMD_APU_PKG_FP4 help - This config option will be removed once the binaries are merged - to the blobs repo. See 33615. + AMD Prairie Falcon FP4 support -if SOC_AMD_STONEYRIDGE_FP4 || SOC_AMD_STONEYRIDGE_FT4 || SOC_AMD_MERLINFALCON +if SOC_AMD_STONEYRIDGE_FP4 || SOC_AMD_STONEYRIDGE_FT4 || SOC_AMD_MERLINFALCON || SOC_AMD_PRAIRIEFALCON config CPU_SPECIFIC_OPTIONS def_bool y @@ -88,10 +87,15 @@ config AMD_APU_STONEYRIDGE help AMD Stoney Ridge APU +config AMD_APU_PRAIRIEFALCON + bool + help + AMD Embedded Prairie Falcon APU + config AMD_APU_MERLINFALCON bool help - AMD Merlin Falcon APU + AMD Embedded Merlin Falcon APU config AMD_APU_PKG_FP4 bool @@ -176,7 +180,8 @@ config VGA_BIOS_FILE string default "" if !USE_AMD_BLOBS default "3rdparty/amd_blobs/stoneyridge/CarrizoGenericVbios.bin" if AMD_APU_MERLINFALCON - default "3rdparty/amd_blobs/stoneyridge/StoneyGenericVbios.bin" + default "3rdparty/amd_blobs/stoneyridge/StoneyGenericVbios.bin" if AMD_APU_PRAIRIEFALCON + default "3rdparty/amd_blobs/stoneyridge/StoneyGenericVbios.bin" if AMD_APU_STONEYRIDGE config S3_VGA_ROM_RUN bool @@ -227,7 +232,8 @@ config AMD_PUBKEY_FILE string "AMD public Key" default "" if !USE_AMD_BLOBS default "3rdparty/amd_blobs/stoneyridge/PSP/CZ/AmdPubKeyCZ.bin" if AMD_APU_MERLINFALCON - default "3rdparty/amd_blobs/stoneyridge/PSP/ST/AmdPubKeyST.bin" + default "3rdparty/amd_blobs/stoneyridge/PSP/ST/AmdPubKeyST.bin" if AMD_APU_PRAIRIEFALCON + default "3rdparty/amd_blobs/stoneyridge/PSP/ST/AmdPubKeyST.bin" if AMD_APU_STONEYRIDGE config STONEYRIDGE_SATA_MODE int "SATA Mode" @@ -433,4 +439,4 @@ config MAINBOARD_POWER_RESTORE return to S0. Otherwise the system will remain in S5 once power is restored. -endif # SOC_AMD_STONEYRIDGE_FP4 || SOC_AMD_STONEYRIDGE_FT4 || SOC_AMD_MERLINFALCON +endif # SOC_AMD_STONEYRIDGE_FP4 || SOC_AMD_STONEYRIDGE_FT4 || SOC_AMD_MERLINFALCON || SOC_AMD_PRAIRIEFALCON diff --git a/src/soc/amd/stoneyridge/Makefile.inc b/src/soc/amd/stoneyridge/Makefile.inc index 52c54d26eb..ee4560d085 100644 --- a/src/soc/amd/stoneyridge/Makefile.inc +++ b/src/soc/amd/stoneyridge/Makefile.inc @@ -139,8 +139,12 @@ else ifeq ($(CONFIG_AMD_APU_MERLINFALCON),y) FIRMWARE_TYPE=CZ else +ifeq ($(CONFIG_AMD_APU_PRAIRIEFALCON),y) +FIRMWARE_TYPE=ST +else $(error soc/amd/stoneyridge: Unusable FIRMWARE_TYPE) +endif # CONFIG_AMD_APU_PRAIRIEFALCON endif # CONFIG_AMD_APU_MERLINFALCON endif # CONFIG_AMD_APU_STONEYRIDGE diff --git a/src/soc/amd/stoneyridge/chip.h b/src/soc/amd/stoneyridge/chip.h index 00b675cbb0..fedb3e9cd0 100644 --- a/src/soc/amd/stoneyridge/chip.h +++ b/src/soc/amd/stoneyridge/chip.h @@ -23,12 +23,11 @@ #include #include -/* Merlin Falcon supports 2 channels, Prairie Falcon only 1 (channel B) */ #define MAX_NODES 1 -#if CONFIG(SOC_AMD_MERLINFALCON) && CONFIG(HAVE_MERLINFALCON_BINARIES) +#if CONFIG(AMD_APU_MERLINFALCON) #define MAX_DRAM_CH 2 #define MAX_DIMMS_PER_CH 2 -#else +#else /* AMD_APU_STONEYRIDGE || AMD_APU_PRAIRIEFALCON */ #define MAX_DRAM_CH 1 #define MAX_DIMMS_PER_CH 2 #endif diff --git a/src/vendorcode/amd/pi/Kconfig b/src/vendorcode/amd/pi/Kconfig index acf84974af..9ac391386f 100644 --- a/src/vendorcode/amd/pi/Kconfig +++ b/src/vendorcode/amd/pi/Kconfig @@ -44,8 +44,8 @@ config AGESA_BINARY_PI_FILE string "AGESA PI binary file name" default "3rdparty/blobs/pi/amd/00630F01/FP3/AGESA.bin" if CPU_AMD_PI_00630F01 default "3rdparty/blobs/pi/amd/00730F01/FT3b/AGESA.bin" if CPU_AMD_PI_00730F01 - default "3rdparty/amd_blobs/stoneyridge/pi/ST/$(CONFIG_AMD_SOC_PACKAGE)/AGESA.bin" if SOC_AMD_MERLINFALCON && HAVE_MERLINFALCON_BINARIES && USE_AMD_BLOBS default "3rdparty/amd_blobs/stoneyridge/pi/CZ/$(CONFIG_AMD_SOC_PACKAGE)/AGESA.bin" if SOC_AMD_MERLINFALCON && USE_AMD_BLOBS + default "3rdparty/amd_blobs/stoneyridge/pi/ST/$(CONFIG_AMD_SOC_PACKAGE)/AGESA.bin" if SOC_AMD_PRAIRIEFALCON && USE_AMD_BLOBS default "3rdparty/amd_blobs/stoneyridge/pi/ST/$(CONFIG_AMD_SOC_PACKAGE)/AGESA.bin" if SOC_AMD_STONEYRIDGE_FP4 && USE_AMD_BLOBS default "3rdparty/amd_blobs/stoneyridge/pi/ST/$(CONFIG_AMD_SOC_PACKAGE)/AGESA.bin" if SOC_AMD_STONEYRIDGE_FT4 && USE_AMD_BLOBS default "3rdparty/blobs/pi/amd/00660F01/FP4/AGESA.bin" if CPU_AMD_PI_00660F01 From 6851922f08935af70180a68ac8d81a802c1e9207 Mon Sep 17 00:00:00 2001 From: Marshall Dawson Date: Mon, 25 Nov 2019 11:36:15 -0700 Subject: [PATCH 0630/1242] soc/amd/stoneyridge|mbs: Define SOC_AMD_STONEYRIDGE symbol Make a new Kconfig symbol for using soc//stoneyridge. This code also supports Prairie Falcon is backward-compatible with Carrizo and Merlin Falcon. Although Bettong uses Carrizo, it does not currently rely on stoneyridge source, so it is unaffected by this change. Change-Id: I786ca54b0444cbcf36dc428a193006797b01fc09 Signed-off-by: Marshall Dawson Reviewed-on: https://review.coreboot.org/c/coreboot/+/37224 Tested-by: build bot (Jenkins) Reviewed-by: Richard Spiegel --- src/mainboard/amd/gardenia/Kconfig | 1 + src/mainboard/amd/padmelon/Kconfig | 1 + src/mainboard/google/kahlee/Kconfig | 1 + src/soc/amd/stoneyridge/Kconfig | 11 ++++++++--- src/vendorcode/amd/pi/Kconfig | 14 ++++++-------- 5 files changed, 17 insertions(+), 11 deletions(-) diff --git a/src/mainboard/amd/gardenia/Kconfig b/src/mainboard/amd/gardenia/Kconfig index 02e3e95953..2d3f2646c1 100644 --- a/src/mainboard/amd/gardenia/Kconfig +++ b/src/mainboard/amd/gardenia/Kconfig @@ -17,6 +17,7 @@ if BOARD_AMD_GARDENIA config BOARD_SPECIFIC_OPTIONS def_bool y + select SOC_AMD_STONEYRIDGE select SOC_AMD_STONEYRIDGE_FP4 select HAVE_PIRQ_TABLE select HAVE_MP_TABLE diff --git a/src/mainboard/amd/padmelon/Kconfig b/src/mainboard/amd/padmelon/Kconfig index e4dd90c8b3..f5d4b6d20e 100644 --- a/src/mainboard/amd/padmelon/Kconfig +++ b/src/mainboard/amd/padmelon/Kconfig @@ -17,6 +17,7 @@ if BOARD_AMD_PADMELON config BOARD_SPECIFIC_OPTIONS # dummy def_bool y + select SOC_AMD_STONEYRIDGE select SOC_AMD_MERLINFALCON select BOARD_ROMSIZE_KB_8192 select DRIVERS_I2C_GENERIC diff --git a/src/mainboard/google/kahlee/Kconfig b/src/mainboard/google/kahlee/Kconfig index 8632553256..20b5273efb 100644 --- a/src/mainboard/google/kahlee/Kconfig +++ b/src/mainboard/google/kahlee/Kconfig @@ -15,6 +15,7 @@ config BOARD_GOOGLE_BASEBOARD_KAHLEE bool + select SOC_AMD_STONEYRIDGE select SOC_AMD_STONEYRIDGE_FT4 select ALWAYS_LOAD_OPROM select ALWAYS_RUN_OPROM diff --git a/src/soc/amd/stoneyridge/Kconfig b/src/soc/amd/stoneyridge/Kconfig index d1dd4334de..4b39ec756b 100644 --- a/src/soc/amd/stoneyridge/Kconfig +++ b/src/soc/amd/stoneyridge/Kconfig @@ -13,6 +13,13 @@ ## GNU General Public License for more details. ## +config SOC_AMD_STONEYRIDGE + bool + help + AMD support for SOCs in Family 15h Models 60h-6Fh and Models 70h-7Fh. + +if SOC_AMD_STONEYRIDGE + config SOC_AMD_STONEYRIDGE_FP4 bool select AMD_APU_STONEYRIDGE @@ -41,8 +48,6 @@ config SOC_AMD_PRAIRIEFALCON help AMD Prairie Falcon FP4 support -if SOC_AMD_STONEYRIDGE_FP4 || SOC_AMD_STONEYRIDGE_FT4 || SOC_AMD_MERLINFALCON || SOC_AMD_PRAIRIEFALCON - config CPU_SPECIFIC_OPTIONS def_bool y select ARCH_BOOTBLOCK_X86_32 @@ -439,4 +444,4 @@ config MAINBOARD_POWER_RESTORE return to S0. Otherwise the system will remain in S5 once power is restored. -endif # SOC_AMD_STONEYRIDGE_FP4 || SOC_AMD_STONEYRIDGE_FT4 || SOC_AMD_MERLINFALCON || SOC_AMD_PRAIRIEFALCON +endif # SOC_AMD_STONEYRIDGE diff --git a/src/vendorcode/amd/pi/Kconfig b/src/vendorcode/amd/pi/Kconfig index 9ac391386f..c72180a57e 100644 --- a/src/vendorcode/amd/pi/Kconfig +++ b/src/vendorcode/amd/pi/Kconfig @@ -26,15 +26,14 @@ # SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. # -if CPU_AMD_PI_00630F01 || CPU_AMD_PI_00730F01 || CPU_AMD_PI_00660F01 || SOC_AMD_STONEYRIDGE_FP4 || SOC_AMD_STONEYRIDGE_FT4 || SOC_AMD_MERLINFALCON +if CPU_AMD_PI_00630F01 || CPU_AMD_PI_00730F01 || CPU_AMD_PI_00660F01 || SOC_AMD_STONEYRIDGE || SOC_AMD_MERLINFALCON config AGESA_BINARY_PI_VENDORCODE_PATH string "AGESA PI directory path" default "src/vendorcode/amd/pi/00630F01" if CPU_AMD_PI_00630F01 default "src/vendorcode/amd/pi/00730F01" if CPU_AMD_PI_00730F01 default "src/vendorcode/amd/pi/00670F00" if SOC_AMD_MERLINFALCON - default "src/vendorcode/amd/pi/00670F00" if SOC_AMD_STONEYRIDGE_FP4 - default "src/vendorcode/amd/pi/00670F00" if SOC_AMD_STONEYRIDGE_FT4 + default "src/vendorcode/amd/pi/00670F00" if SOC_AMD_STONEYRIDGE default "src/vendorcode/amd/pi/00660F01" if CPU_AMD_PI_00660F01 help Specify where to find the AGESA header files @@ -46,15 +45,14 @@ config AGESA_BINARY_PI_FILE default "3rdparty/blobs/pi/amd/00730F01/FT3b/AGESA.bin" if CPU_AMD_PI_00730F01 default "3rdparty/amd_blobs/stoneyridge/pi/CZ/$(CONFIG_AMD_SOC_PACKAGE)/AGESA.bin" if SOC_AMD_MERLINFALCON && USE_AMD_BLOBS default "3rdparty/amd_blobs/stoneyridge/pi/ST/$(CONFIG_AMD_SOC_PACKAGE)/AGESA.bin" if SOC_AMD_PRAIRIEFALCON && USE_AMD_BLOBS - default "3rdparty/amd_blobs/stoneyridge/pi/ST/$(CONFIG_AMD_SOC_PACKAGE)/AGESA.bin" if SOC_AMD_STONEYRIDGE_FP4 && USE_AMD_BLOBS - default "3rdparty/amd_blobs/stoneyridge/pi/ST/$(CONFIG_AMD_SOC_PACKAGE)/AGESA.bin" if SOC_AMD_STONEYRIDGE_FT4 && USE_AMD_BLOBS + default "3rdparty/amd_blobs/stoneyridge/pi/ST/$(CONFIG_AMD_SOC_PACKAGE)/AGESA.bin" if AMD_APU_STONEYRIDGE && USE_AMD_BLOBS default "3rdparty/blobs/pi/amd/00660F01/FP4/AGESA.bin" if CPU_AMD_PI_00660F01 help Specify the binary file to use for AMD platform initialization. config AGESA_BINARY_PI_AS_STAGE bool "AGESA Binary PI is added as stage to CBFS." - depends on SOC_AMD_STONEYRIDGE_FT4 || SOC_AMD_STONEYRIDGE_FP4 + depends on SOC_AMD_STONEYRIDGE help AGESA will be added as a stage utilizing --xip cbfstool options as needed relocating the image to the proper location in memory-mapped @@ -72,7 +70,7 @@ config AGESA_SPLIT_MEMORY_FILES config AGESA_PRE_MEMORY_BINARY_PI_FILE string depends on AGESA_SPLIT_MEMORY_FILES - default "3rdparty/blobs/pi/amd/00670F00/FT4/AGESA_premem.elf" if SOC_AMD_STONEYRIDGE_FT4 && USE_AMD_BLOBS + default "3rdparty/blobs/pi/amd/00670F00/FT4/AGESA_premem.elf" if SOC_AMD_STONEYRIDGE && USE_AMD_BLOBS help Specify the binary file to use for pre-memory AMD platform initialization. @@ -80,7 +78,7 @@ config AGESA_PRE_MEMORY_BINARY_PI_FILE config AGESA_POST_MEMORY_BINARY_PI_FILE string depends on AGESA_SPLIT_MEMORY_FILES - default "3rdparty/blobs/pi/amd/00670F00/FT4/AGESA_postmem.elf" if SOC_AMD_STONEYRIDGE_FT4 && USE_AMD_BLOBS + default "3rdparty/blobs/pi/amd/00670F00/FT4/AGESA_postmem.elf" if SOC_AMD_STONEYRIDGE && USE_AMD_BLOBS help Specify the binary file to use for post-memory AMD platform initialization. From d786843ca6c0078fd268cc9516acc10109e98919 Mon Sep 17 00:00:00 2001 From: Marshall Dawson Date: Mon, 25 Nov 2019 11:47:32 -0700 Subject: [PATCH 0631/1242] soc/amd/stoneyridge|mbs: Deprecate SOC_AMD_NAME_PKG and others Add package and APU selections to mainboards and remove symbols no longer used in soc//stoneyridge. Change-Id: I60214b6557bef50358f9ec8f9fcdb7265e04663b Signed-off-by: Marshall Dawson Reviewed-on: https://review.coreboot.org/c/coreboot/+/37225 Tested-by: build bot (Jenkins) Reviewed-by: Richard Spiegel --- src/mainboard/amd/gardenia/Kconfig | 3 ++- src/mainboard/amd/padmelon/Kconfig | 3 ++- src/mainboard/google/kahlee/Kconfig | 3 ++- src/soc/amd/stoneyridge/Kconfig | 28 --------------------- src/soc/amd/stoneyridge/Makefile.inc | 4 +-- src/vendorcode/amd/pi/00670F00/Makefile.inc | 2 +- src/vendorcode/amd/pi/Kconfig | 10 ++++---- 7 files changed, 14 insertions(+), 39 deletions(-) diff --git a/src/mainboard/amd/gardenia/Kconfig b/src/mainboard/amd/gardenia/Kconfig index 2d3f2646c1..e97a3bad78 100644 --- a/src/mainboard/amd/gardenia/Kconfig +++ b/src/mainboard/amd/gardenia/Kconfig @@ -18,7 +18,8 @@ if BOARD_AMD_GARDENIA config BOARD_SPECIFIC_OPTIONS def_bool y select SOC_AMD_STONEYRIDGE - select SOC_AMD_STONEYRIDGE_FP4 + select AMD_APU_STONEYRIDGE + select AMD_APU_PKG_FP4 select HAVE_PIRQ_TABLE select HAVE_MP_TABLE select HAVE_ACPI_TABLES diff --git a/src/mainboard/amd/padmelon/Kconfig b/src/mainboard/amd/padmelon/Kconfig index f5d4b6d20e..1be3a62cee 100644 --- a/src/mainboard/amd/padmelon/Kconfig +++ b/src/mainboard/amd/padmelon/Kconfig @@ -18,7 +18,8 @@ if BOARD_AMD_PADMELON config BOARD_SPECIFIC_OPTIONS # dummy def_bool y select SOC_AMD_STONEYRIDGE - select SOC_AMD_MERLINFALCON + select AMD_APU_MERLINFALCON + select AMD_APU_PKG_FP4 select BOARD_ROMSIZE_KB_8192 select DRIVERS_I2C_GENERIC select DRIVERS_PS2_KEYBOARD diff --git a/src/mainboard/google/kahlee/Kconfig b/src/mainboard/google/kahlee/Kconfig index 20b5273efb..7d98d89f13 100644 --- a/src/mainboard/google/kahlee/Kconfig +++ b/src/mainboard/google/kahlee/Kconfig @@ -16,7 +16,8 @@ config BOARD_GOOGLE_BASEBOARD_KAHLEE bool select SOC_AMD_STONEYRIDGE - select SOC_AMD_STONEYRIDGE_FT4 + select AMD_APU_STONEYRIDGE + select AMD_APU_PKG_FT4 select ALWAYS_LOAD_OPROM select ALWAYS_RUN_OPROM select BOARD_ROMSIZE_KB_16384 diff --git a/src/soc/amd/stoneyridge/Kconfig b/src/soc/amd/stoneyridge/Kconfig index 4b39ec756b..a03b8f3e84 100644 --- a/src/soc/amd/stoneyridge/Kconfig +++ b/src/soc/amd/stoneyridge/Kconfig @@ -20,34 +20,6 @@ config SOC_AMD_STONEYRIDGE if SOC_AMD_STONEYRIDGE -config SOC_AMD_STONEYRIDGE_FP4 - bool - select AMD_APU_STONEYRIDGE - select AMD_APU_PKG_FP4 - help - AMD Stoney Ridge FP4 support - -config SOC_AMD_STONEYRIDGE_FT4 - bool - select AMD_APU_STONEYRIDGE - select AMD_APU_PKG_FT4 - help - AMD Stoney Ridge FT4 support - -config SOC_AMD_MERLINFALCON - bool - select AMD_APU_MERLINFALCON - select AMD_APU_PKG_FP4 - help - AMD Merlin Falcon FP4 support - -config SOC_AMD_PRAIRIEFALCON - bool - select AMD_APU_PRAIRIEFALCON - select AMD_APU_PKG_FP4 - help - AMD Prairie Falcon FP4 support - config CPU_SPECIFIC_OPTIONS def_bool y select ARCH_BOOTBLOCK_X86_32 diff --git a/src/soc/amd/stoneyridge/Makefile.inc b/src/soc/amd/stoneyridge/Makefile.inc index ee4560d085..15216b7934 100644 --- a/src/soc/amd/stoneyridge/Makefile.inc +++ b/src/soc/amd/stoneyridge/Makefile.inc @@ -27,7 +27,7 @@ # SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. # #***************************************************************************** -ifeq ($(CONFIG_SOC_AMD_MERLINFALCON)$(CONFIG_SOC_AMD_STONEYRIDGE_FP4)$(CONFIG_SOC_AMD_STONEYRIDGE_FT4),y) +ifeq ($(CONFIG_SOC_AMD_STONEYRIDGE),y) subdirs-y += ../../../cpu/amd/mtrr/ subdirs-y += ../../../cpu/x86/tsc @@ -338,4 +338,4 @@ files_added:: warn_no_amdfw endif # ifneq ($(FIRMWARE_LOCATE),) -endif # ($(CONFIG_SOC_AMD_MERLINFALCON)$(CONFIG_SOC_AMD_STONEYRIDGE_FP4)$(CONFIG_SOC_AMD_STONEYRIDGE_FT4),y) +endif # ($(CONFIG_SOC_AMD_STONEYRIDGE),y) diff --git a/src/vendorcode/amd/pi/00670F00/Makefile.inc b/src/vendorcode/amd/pi/00670F00/Makefile.inc index 947134f1d9..a019f0540e 100644 --- a/src/vendorcode/amd/pi/00670F00/Makefile.inc +++ b/src/vendorcode/amd/pi/00670F00/Makefile.inc @@ -28,7 +28,7 @@ # #***************************************************************************** -ifeq ($(CONFIG_SOC_AMD_MERLINFALCON)$(CONFIG_SOC_AMD_STONEYRIDGE_FP4)$(CONFIG_SOC_AMD_STONEYRIDGE_FT4),y) +ifeq ($(CONFIG_SOC_AMD_STONEYRIDGE),y) # AGESA V5 Files AGESA_ROOT = $(call strip_quotes,$(CONFIG_AGESA_BINARY_PI_VENDORCODE_PATH)) diff --git a/src/vendorcode/amd/pi/Kconfig b/src/vendorcode/amd/pi/Kconfig index c72180a57e..265a381eb6 100644 --- a/src/vendorcode/amd/pi/Kconfig +++ b/src/vendorcode/amd/pi/Kconfig @@ -26,14 +26,14 @@ # SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. # -if CPU_AMD_PI_00630F01 || CPU_AMD_PI_00730F01 || CPU_AMD_PI_00660F01 || SOC_AMD_STONEYRIDGE || SOC_AMD_MERLINFALCON +if CPU_AMD_PI_00630F01 || CPU_AMD_PI_00730F01 || CPU_AMD_PI_00660F01 || SOC_AMD_STONEYRIDGE config AGESA_BINARY_PI_VENDORCODE_PATH string "AGESA PI directory path" default "src/vendorcode/amd/pi/00630F01" if CPU_AMD_PI_00630F01 default "src/vendorcode/amd/pi/00730F01" if CPU_AMD_PI_00730F01 - default "src/vendorcode/amd/pi/00670F00" if SOC_AMD_MERLINFALCON - default "src/vendorcode/amd/pi/00670F00" if SOC_AMD_STONEYRIDGE + default "src/vendorcode/amd/pi/00670F00" if AMD_APU_MERLINFALCON + default "src/vendorcode/amd/pi/00670F00" if AMD_APU_STONEYRIDGE || AMD_APU_PRAIRIEFALCON default "src/vendorcode/amd/pi/00660F01" if CPU_AMD_PI_00660F01 help Specify where to find the AGESA header files @@ -43,8 +43,8 @@ config AGESA_BINARY_PI_FILE string "AGESA PI binary file name" default "3rdparty/blobs/pi/amd/00630F01/FP3/AGESA.bin" if CPU_AMD_PI_00630F01 default "3rdparty/blobs/pi/amd/00730F01/FT3b/AGESA.bin" if CPU_AMD_PI_00730F01 - default "3rdparty/amd_blobs/stoneyridge/pi/CZ/$(CONFIG_AMD_SOC_PACKAGE)/AGESA.bin" if SOC_AMD_MERLINFALCON && USE_AMD_BLOBS - default "3rdparty/amd_blobs/stoneyridge/pi/ST/$(CONFIG_AMD_SOC_PACKAGE)/AGESA.bin" if SOC_AMD_PRAIRIEFALCON && USE_AMD_BLOBS + default "3rdparty/amd_blobs/stoneyridge/pi/CZ/$(CONFIG_AMD_SOC_PACKAGE)/AGESA.bin" if AMD_APU_MERLINFALCON && USE_AMD_BLOBS + default "3rdparty/amd_blobs/stoneyridge/pi/ST/$(CONFIG_AMD_SOC_PACKAGE)/AGESA.bin" if AMD_APU_PRAIRIEFALCON && USE_AMD_BLOBS default "3rdparty/amd_blobs/stoneyridge/pi/ST/$(CONFIG_AMD_SOC_PACKAGE)/AGESA.bin" if AMD_APU_STONEYRIDGE && USE_AMD_BLOBS default "3rdparty/blobs/pi/amd/00660F01/FP4/AGESA.bin" if CPU_AMD_PI_00660F01 help From ad27283a3c777f288254974cac233e47d1c0005d Mon Sep 17 00:00:00 2001 From: Richard Spiegel Date: Wed, 13 Nov 2019 12:11:13 -0700 Subject: [PATCH 0632/1242] mb/amd/padmelon: Use Prairie Falcon configuration While Merlin Falcon binaries are not available, make it explicit that it's compiling for Prairie Falcon (it was being surreptitious about it). Board Padmelon accepts 3 different SOC, just changing some resistors (soldered or not): Brown Falcon, Prairie Falcon and Merlin Falcon. Code for Brown Falcon is not currently available. BUG=None TEST=Build with prairie falcon. Change-Id: I1663e4403a32a7d626dd2fa06763f18f4230457e Signed-off-by: Richard Spiegel Reviewed-on: https://review.coreboot.org/c/coreboot/+/36824 Tested-by: build bot (Jenkins) Reviewed-by: Marshall Dawson --- src/mainboard/amd/padmelon/Kconfig | 18 +++++++++++++++++- 1 file changed, 17 insertions(+), 1 deletion(-) diff --git a/src/mainboard/amd/padmelon/Kconfig b/src/mainboard/amd/padmelon/Kconfig index 1be3a62cee..e9d2acb1c2 100644 --- a/src/mainboard/amd/padmelon/Kconfig +++ b/src/mainboard/amd/padmelon/Kconfig @@ -18,7 +18,6 @@ if BOARD_AMD_PADMELON config BOARD_SPECIFIC_OPTIONS # dummy def_bool y select SOC_AMD_STONEYRIDGE - select AMD_APU_MERLINFALCON select AMD_APU_PKG_FP4 select BOARD_ROMSIZE_KB_8192 select DRIVERS_I2C_GENERIC @@ -43,6 +42,23 @@ config MAINBOARD_PART_NUMBER string default "Padmelon" +choice PADMELON_SOC + prompt "SOC used in padmelon board" + default PADMELON_MERLIN_FALCON + +config PADMELON_MERLIN_FALCON + bool "Merlin Falcon" + +config PADMELON_PRAIRIE_FALCON + bool "Prairie Falcon" + +endchoice + +config PADMELON_SOC_IN_USE + def_bool y + select AMD_APU_MERLINFALCON if PADMELON_MERLIN_FALCON + select AMD_APU_PRAIRIEFALCON if PADMELON_PRAIRIE_FALCON + config HAVE_S3_SUPPORT bool default n From 8245bd25a35466248c00bc7a4d0cf96f8391924a Mon Sep 17 00:00:00 2001 From: Julius Werner Date: Wed, 4 Dec 2019 20:32:15 -0800 Subject: [PATCH 0633/1242] fmap: Make FMAP_CACHE mandatory if it is configured in Now that we have a CONFIG_NO_FMAP_CACHE to completely configure out the pre-RAM FMAP cache code, there's no point in allowing the region to be optional anymore. This patch makes the section required by the linker. If a board doesn't want to provide it, it has to select NO_FMAP_CACHE. Adding FMAP_CACHE regions to a couple more targets that I think can use them but I don't know anything about... please yell if one of these is a bad idea and I should mark them NO_FMAP_CACHE instead. Change-Id: Ic7d47772ab3abfa7e3a66815c3739d0af071abc2 Signed-off-by: Julius Werner Reviewed-on: https://review.coreboot.org/c/coreboot/+/37497 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin Reviewed-by: Furquan Shaikh --- src/cpu/ti/am335x/memlayout.ld | 3 ++- src/include/memlayout.h | 2 +- src/lib/fmap.c | 10 ---------- src/mainboard/emulation/qemu-aarch64/memlayout.ld | 3 ++- src/mainboard/emulation/qemu-armv7/memlayout.ld | 1 + src/mainboard/emulation/qemu-power8/memlayout.ld | 1 + src/mainboard/emulation/qemu-riscv/memlayout.ld | 1 + src/mainboard/emulation/spike-riscv/memlayout.ld | 3 ++- src/soc/cavium/cn81xx/include/soc/memlayout.ld | 3 ++- src/soc/qualcomm/sdm845/include/soc/memlayout.ld | 3 ++- src/soc/sifive/fu540/include/soc/memlayout.ld | 1 + 11 files changed, 15 insertions(+), 16 deletions(-) diff --git a/src/cpu/ti/am335x/memlayout.ld b/src/cpu/ti/am335x/memlayout.ld index 0de86f1f44..f69a31595a 100644 --- a/src/cpu/ti/am335x/memlayout.ld +++ b/src/cpu/ti/am335x/memlayout.ld @@ -19,7 +19,8 @@ SECTIONS { DRAM_START(0x40000000) BOOTBLOCK(0x402f0400, 20K) - ROMSTAGE(0x402f5400, 90K) + ROMSTAGE(0x402f5400, 88K) + FMAP_CACHE(0x4030b400, 2K) STACK(0x4030be00, 4K) RAMSTAGE(0x80200000, 192K) diff --git a/src/include/memlayout.h b/src/include/memlayout.h index 56dfb6a785..e3aeec68b1 100644 --- a/src/include/memlayout.h +++ b/src/include/memlayout.h @@ -78,7 +78,7 @@ #define FMAP_CACHE(addr, sz) \ REGION(fmap_cache, addr, sz, 4) \ - _ = ASSERT(sz == 0 || sz >= FMAP_SIZE, \ + _ = ASSERT(sz >= FMAP_SIZE, \ STR(FMAP does not fit in FMAP_CACHE! (sz < FMAP_SIZE))); #if ENV_ROMSTAGE_OR_BEFORE diff --git a/src/lib/fmap.c b/src/lib/fmap.c index af26152d13..9d2b4e781f 100644 --- a/src/lib/fmap.c +++ b/src/lib/fmap.c @@ -36,8 +36,6 @@ static struct mem_region_device fmap_cache; printk(__VA_ARGS__); \ } while (0) -DECLARE_OPTIONAL_REGION(fmap_cache); - uint64_t get_fmap_flash_offset(void) { return FMAP_OFFSET; @@ -71,14 +69,6 @@ static void setup_preram_cache(struct mem_region_device *cache_mrdev) return; } - if (REGION_SIZE(fmap_cache) == 0) { - /* If you see this you should add FMAP_CACHE() to your memlayout - (or select NO_FMAP_CACHE if you can't afford the 2K). */ - print_once(BIOS_ERR, - "ERROR: FMAP_CACHE enabled but no region provided!\n"); - return; - } - struct fmap *fmap = (struct fmap *)_fmap_cache; if (!ENV_BOOTBLOCK) { /* NOTE: This assumes that for all platforms running this code, diff --git a/src/mainboard/emulation/qemu-aarch64/memlayout.ld b/src/mainboard/emulation/qemu-aarch64/memlayout.ld index 0b52d31052..aba4205750 100644 --- a/src/mainboard/emulation/qemu-aarch64/memlayout.ld +++ b/src/mainboard/emulation/qemu-aarch64/memlayout.ld @@ -24,7 +24,8 @@ SECTIONS DRAM_START(0x40000000) BOOTBLOCK(0x60010000, 64K) - STACK(0x60020000, 64K) + STACK(0x60020000, 62K) + FMAP_CACHE(0x6002F800, 2K) ROMSTAGE(0x60030000, 128K) RAMSTAGE(0x60070000, 16M) diff --git a/src/mainboard/emulation/qemu-armv7/memlayout.ld b/src/mainboard/emulation/qemu-armv7/memlayout.ld index 776e05166b..2b33cb39f3 100644 --- a/src/mainboard/emulation/qemu-armv7/memlayout.ld +++ b/src/mainboard/emulation/qemu-armv7/memlayout.ld @@ -42,6 +42,7 @@ SECTIONS /* TODO: does this thing emulate SRAM? */ BOOTBLOCK(0x00000, 64K) + FMAP_CACHE(0x10000, 2K) DRAM_START(0x60000000) STACK(0x60000000, 64K) diff --git a/src/mainboard/emulation/qemu-power8/memlayout.ld b/src/mainboard/emulation/qemu-power8/memlayout.ld index da0f4a5fe8..c22d3e4f25 100644 --- a/src/mainboard/emulation/qemu-power8/memlayout.ld +++ b/src/mainboard/emulation/qemu-power8/memlayout.ld @@ -26,5 +26,6 @@ SECTIONS ROMSTAGE(0x20000, 128K) STACK(0x40000, 0x3ff00) PRERAM_CBMEM_CONSOLE(0x80000, 8K) + FMAP_CACHE(0x82000, 2K) RAMSTAGE(0x100000, 16M) } diff --git a/src/mainboard/emulation/qemu-riscv/memlayout.ld b/src/mainboard/emulation/qemu-riscv/memlayout.ld index b29bc14fa9..e53df3845e 100644 --- a/src/mainboard/emulation/qemu-riscv/memlayout.ld +++ b/src/mainboard/emulation/qemu-riscv/memlayout.ld @@ -37,6 +37,7 @@ SECTIONS REGION(opensbi, STAGES_START, 128K, 4K) #endif PRERAM_CBMEM_CONSOLE(STAGES_START + 128K, 8K) + FMAP_CACHE(STAGES_START + 136K, 2K) RAMSTAGE(STAGES_START + 200K, 16M) STACK(STAGES_START + 200K + 16M, 4K) } diff --git a/src/mainboard/emulation/spike-riscv/memlayout.ld b/src/mainboard/emulation/spike-riscv/memlayout.ld index bae414ffd5..b6e4d9d5e8 100644 --- a/src/mainboard/emulation/spike-riscv/memlayout.ld +++ b/src/mainboard/emulation/spike-riscv/memlayout.ld @@ -24,7 +24,8 @@ SECTIONS DRAM_START(START) BOOTBLOCK(START, 64K) STACK(START + 8M, 4K) - /* hole at (START + 8M + 4K, 60K) */ + FMAP_CACHE(START + 8M + 4K, 2K) + /* hole at (START + 8M + 6K, 58K) */ ROMSTAGE(START + 8M + 64K, 128K) PRERAM_CBMEM_CONSOLE(START + 8M + 192k, 8K) RAMSTAGE(START + 8M + 200K, 256K) diff --git a/src/soc/cavium/cn81xx/include/soc/memlayout.ld b/src/soc/cavium/cn81xx/include/soc/memlayout.ld index e4e3490395..1a0eb155b7 100644 --- a/src/soc/cavium/cn81xx/include/soc/memlayout.ld +++ b/src/soc/cavium/cn81xx/include/soc/memlayout.ld @@ -31,7 +31,8 @@ SECTIONS STACK(BOOTROM_OFFSET, 16K) TIMESTAMP(BOOTROM_OFFSET + 0x4000, 4K) - PRERAM_CBFS_CACHE(BOOTROM_OFFSET + 0x6000, 8K) + PRERAM_CBFS_CACHE(BOOTROM_OFFSET + 0x6000, 6K) + FMAP_CACHE(BOOTROM_OFFSET + 0x7800, 2K) PRERAM_CBMEM_CONSOLE(BOOTROM_OFFSET + 0x8000, 8K) BOOTBLOCK(BOOTROM_OFFSET + 0x20000, 64K) VBOOT2_WORK(BOOTROM_OFFSET + 0x30000, 12K) diff --git a/src/soc/qualcomm/sdm845/include/soc/memlayout.ld b/src/soc/qualcomm/sdm845/include/soc/memlayout.ld index b0d2d43f4b..c3a3b4c84a 100644 --- a/src/soc/qualcomm/sdm845/include/soc/memlayout.ld +++ b/src/soc/qualcomm/sdm845/include/soc/memlayout.ld @@ -57,7 +57,8 @@ SECTIONS TIMESTAMP(0x14836000, 1K) PRERAM_CBMEM_CONSOLE(0x14836400, 32K) PRERAM_CBFS_CACHE(0x1483E400, 70K) - REGION(bsram_unused, 0x1484FC00, 0x9E300, 0x100) + FMAP_CACHE(0x1484FC00, 2K) + REGION(bsram_unused, 0x14850400, 0x9DB00, 0x100) REGION(ddr_information, 0x148EDF00, 256, 256) REGION(limits_cfg, 0x148EE000, 4K, 4K) REGION(qclib_serial_log, 0x148EF000, 4K, 4K) diff --git a/src/soc/sifive/fu540/include/soc/memlayout.ld b/src/soc/sifive/fu540/include/soc/memlayout.ld index df30ede510..46c559cba1 100644 --- a/src/soc/sifive/fu540/include/soc/memlayout.ld +++ b/src/soc/sifive/fu540/include/soc/memlayout.ld @@ -27,6 +27,7 @@ SECTIONS BOOTBLOCK(FU540_L2LIM, 64K) CAR_STACK(FU540_L2LIM + 64K, 20K) PRERAM_CBMEM_CONSOLE(FU540_L2LIM + 84K, 8K) + FMAP_CACHE(FU540_L2LIM + 92K, 2K) ROMSTAGE(FU540_L2LIM + 128K, 128K) PRERAM_CBFS_CACHE(FU540_L2LIM + 256K, 128K) L2LIM_END(FU540_L2LIM + 2M) From 07e6098d487fc9135fc47e316a6d7e0332d814a0 Mon Sep 17 00:00:00 2001 From: Frans Hendriks Date: Mon, 9 Dec 2019 09:56:44 +0100 Subject: [PATCH 0634/1242] mb/facebook/fbg1701: Move verified items to board_verified_boot.h Items in onboard.h are related to verified or measured boot. Move the items to board_verified_boot.h and remove onboard.h. BUG=N/A TEST=build Change-Id: Icfc8d6d8351f0654c277e81c7f3cc2b0a947866a Signed-off-by: Wim Vervoorn Reviewed-on: https://review.coreboot.org/c/coreboot/+/37614 Reviewed-by: Frans Hendriks Tested-by: build bot (Jenkins) --- src/mainboard/facebook/fbg1701/board_mboot.h | 1 + .../facebook/fbg1701/board_verified_boot.h | 11 ++++++- src/mainboard/facebook/fbg1701/onboard.h | 31 ------------------- 3 files changed, 11 insertions(+), 32 deletions(-) diff --git a/src/mainboard/facebook/fbg1701/board_mboot.h b/src/mainboard/facebook/fbg1701/board_mboot.h index 5cfb091451..69272de78b 100644 --- a/src/mainboard/facebook/fbg1701/board_mboot.h +++ b/src/mainboard/facebook/fbg1701/board_mboot.h @@ -14,6 +14,7 @@ */ #include +#include "board_verified_boot.h" const mboot_measure_item_t mb_log_list[] = { { "config", CBFS_TYPE_RAW, MBOOT_PCR_INDEX_0, EV_NO_ACTION, NULL }, diff --git a/src/mainboard/facebook/fbg1701/board_verified_boot.h b/src/mainboard/facebook/fbg1701/board_verified_boot.h index 0f79579050..20f53285ab 100644 --- a/src/mainboard/facebook/fbg1701/board_verified_boot.h +++ b/src/mainboard/facebook/fbg1701/board_verified_boot.h @@ -17,6 +17,15 @@ #define BOARD_VERIFIED_BOOT_H #include -#include "onboard.h" + +/* Define the items to be measured or verified */ +#define FSP (const char *)"fsp.bin" +#define CMOS_LAYOUT (const char *)"cmos_layout.bin" +#define RAMSTAGE (const char *)CONFIG_CBFS_PREFIX"/ramstage" +#define ROMSTAGE (const char *)CONFIG_CBFS_PREFIX"/romstage" +#define PAYLOAD (const char *)CONFIG_CBFS_PREFIX"/payload" +#define POSTCAR (const char *)CONFIG_CBFS_PREFIX"/postcar" +#define OP_ROM_VBT (const char *)"vbt.bin" +#define MICROCODE (const char *)"cpu_microcode_blob.bin" #endif diff --git a/src/mainboard/facebook/fbg1701/onboard.h b/src/mainboard/facebook/fbg1701/onboard.h index 715f76a39d..e69de29bb2 100644 --- a/src/mainboard/facebook/fbg1701/onboard.h +++ b/src/mainboard/facebook/fbg1701/onboard.h @@ -1,31 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2013 Google Inc. - * Copyright (C) 2015 Intel Corp. - * Copyright (C) 2018-2019 Eltan B.V. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef ONBOARD_H -#define ONBOARD_H - -/* Define the items to be measured or verified */ -#define FSP (const char *)"fsp.bin" -#define CMOS_LAYOUT (const char *)"cmos_layout.bin" -#define RAMSTAGE (const char *)CONFIG_CBFS_PREFIX"/ramstage" -#define ROMSTAGE (const char *)CONFIG_CBFS_PREFIX"/romstage" -#define PAYLOAD (const char *)CONFIG_CBFS_PREFIX"/payload" -#define POSTCAR (const char *)CONFIG_CBFS_PREFIX"/postcar" -#define OP_ROM_VBT (const char *)"vbt.bin" -#define MICROCODE (const char *)"cpu_microcode_blob.bin" - -#endif From e2291f5ad4049e8df864318760b5a88370c8344d Mon Sep 17 00:00:00 2001 From: Frans Hendriks Date: Mon, 9 Dec 2019 10:00:41 +0100 Subject: [PATCH 0635/1242] mb/{facebook/portwell}: Remove empty onboard.h Defines in onboard.h are moved to other files. Remove this empty and unused file. BUG=N/A TEST=build Change-Id: Ide10b352eadcffad2d4221865124f64466af5a1c Signed-off-by: Wim Vervoorn Reviewed-on: https://review.coreboot.org/c/coreboot/+/37615 Reviewed-by: Patrick Georgi Tested-by: build bot (Jenkins) --- src/mainboard/facebook/fbg1701/onboard.h | 0 src/mainboard/portwell/m107/onboard.h | 24 ------------------------ 2 files changed, 24 deletions(-) delete mode 100644 src/mainboard/facebook/fbg1701/onboard.h delete mode 100644 src/mainboard/portwell/m107/onboard.h diff --git a/src/mainboard/facebook/fbg1701/onboard.h b/src/mainboard/facebook/fbg1701/onboard.h deleted file mode 100644 index e69de29bb2..0000000000 diff --git a/src/mainboard/portwell/m107/onboard.h b/src/mainboard/portwell/m107/onboard.h deleted file mode 100644 index 3a5dee2f12..0000000000 --- a/src/mainboard/portwell/m107/onboard.h +++ /dev/null @@ -1,24 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2013 Google Inc. - * Copyright (C) 2015 Intel Corp. - * Copyright (C) 2018 Eltan B.V. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef ONBOARD_H -#define ONBOARD_H - -/* SD CARD gpio */ -#define SDCARD_CD 81 /* Not used */ - -#endif From e18dba8e9ad34061781a6dfd4f73209a991e933e Mon Sep 17 00:00:00 2001 From: Patrick Rudolph Date: Mon, 9 Dec 2019 20:10:20 +0100 Subject: [PATCH 0636/1242] mb/lenovo/t410: Select ricoh driver Fix for CB:35086. Build the Ricoh SDcard driver that is defined in devicetree. Change-Id: Ib0ac3da088d798c35e2c5ea045ea721c89d9e12f Signed-off-by: Patrick Rudolph Reviewed-on: https://review.coreboot.org/c/coreboot/+/37625 Reviewed-by: Philipp Deppenwiese Reviewed-by: Paul Menzel Tested-by: build bot (Jenkins) --- src/mainboard/lenovo/t410/Kconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/src/mainboard/lenovo/t410/Kconfig b/src/mainboard/lenovo/t410/Kconfig index 943bf43e0a..f97a0938b1 100644 --- a/src/mainboard/lenovo/t410/Kconfig +++ b/src/mainboard/lenovo/t410/Kconfig @@ -22,6 +22,7 @@ config BOARD_SPECIFIC_OPTIONS select MAINBOARD_USES_IFD_GBE_REGION select H8_HAS_BAT_TRESHOLDS_IMPL select MAINBOARD_HAS_LIBGFXINIT + select DRIVERS_RICOH_RCE822 config VBOOT select VBOOT_VBNV_CMOS From 6cfda93c6c3c3024741286b23c93dd80b9077525 Mon Sep 17 00:00:00 2001 From: Patrick Georgi Date: Tue, 10 Dec 2019 15:57:59 +0100 Subject: [PATCH 0637/1242] Documentation: Fix table and layout The table wasn't pretty enough so sphinx complained, while the second paragraph had trailing whitespace, could be wrapped differently and also came with a typo. Change-Id: I6c16a3a1fcc306d0b12043ebec7d4e69e9339d7d Signed-off-by: Patrick Georgi Reviewed-on: https://review.coreboot.org/c/coreboot/+/37642 Tested-by: build bot (Jenkins) Reviewed-by: Wim Vervoorn Reviewed-by: Frans Hendriks Reviewed-by: Paul Menzel Reviewed-by: Angel Pons --- Documentation/mainboard/facebook/monolith.md | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/Documentation/mainboard/facebook/monolith.md b/Documentation/mainboard/facebook/monolith.md index 9b9f33b29f..a469a8438a 100644 --- a/Documentation/mainboard/facebook/monolith.md +++ b/Documentation/mainboard/facebook/monolith.md @@ -2,8 +2,8 @@ This page describes how to run coreboot on the Facebook Monolith. -Please note: the coreboot implementation for this boards is in it's Alpha state and isn't fully -tested yet. +Please note: the coreboot implementation for this boards is in its +Alpha state and isn't fully tested yet. ## Required blobs @@ -63,7 +63,7 @@ output. ```eval_rst +------------------+--------------------------------------------------+ -| SoC | Intel Kaby Lake U | +| SoC | Intel Kaby Lake U | +------------------+--------------------------------------------------+ | CPU | Intel i3-7100U | +------------------+--------------------------------------------------+ From b643d3df8adbc933e02d8c8c7dcc61cc60b65afb Mon Sep 17 00:00:00 2001 From: Eric Lai Date: Mon, 9 Dec 2019 15:05:12 +0800 Subject: [PATCH 0638/1242] libpayload/drivers/i8042: Add AT translated Keyboard support Wilco device uses the AT translated keyboard and doesn't need to set scancode set. Remove the ignore flag and put into translation mode instead. BUG=b:145130110 TEST=Draillion keyboard is usable on every boot. Signed-off-by: Eric Lai Change-Id: Ie1053e24e44c5bad28b56cc92d091e24f3d9b6fd Reviewed-on: https://review.coreboot.org/c/coreboot/+/37594 Tested-by: build bot (Jenkins) Reviewed-by: Mathew King --- payloads/libpayload/Kconfig | 4 + payloads/libpayload/drivers/i8042/i8042.h | 1 + payloads/libpayload/drivers/i8042/keyboard.c | 86 +++++++++++++------- 3 files changed, 62 insertions(+), 29 deletions(-) diff --git a/payloads/libpayload/Kconfig b/payloads/libpayload/Kconfig index d216f61dc8..347ccac6b0 100644 --- a/payloads/libpayload/Kconfig +++ b/payloads/libpayload/Kconfig @@ -347,6 +347,10 @@ config PC_KEYBOARD_IGNORE_INIT_FAILURE bool "Ignore keyboard failures during init and always add input device" default n +config PC_KEYBOARD_AT_TRANSLATED + bool "AT Translation keyboard device" + default n + config PC_KEYBOARD_LAYOUT_US bool "English (US) keyboard layout" depends on PC_KEYBOARD diff --git a/payloads/libpayload/drivers/i8042/i8042.h b/payloads/libpayload/drivers/i8042/i8042.h index 643167ef40..f03956928f 100644 --- a/payloads/libpayload/drivers/i8042/i8042.h +++ b/payloads/libpayload/drivers/i8042/i8042.h @@ -33,6 +33,7 @@ /* Port 0x64 commands */ #define I8042_CMD_RD_CMD_BYTE 0x20 #define I8042_CMD_WR_CMD_BYTE 0x60 +#define I8042_CMD_BYTE_XLATE (1 << 6) #define I8042_CMD_DIS_AUX 0xa7 #define I8042_CMD_EN_AUX 0xa8 #define I8042_CMD_AUX_TEST 0xa9 diff --git a/payloads/libpayload/drivers/i8042/keyboard.c b/payloads/libpayload/drivers/i8042/keyboard.c index f9932ed4ed..4b4a56987a 100644 --- a/payloads/libpayload/drivers/i8042/keyboard.c +++ b/payloads/libpayload/drivers/i8042/keyboard.c @@ -312,9 +312,59 @@ static struct console_input_driver cons = { .input_type = CONSOLE_INPUT_TYPE_EC, }; -void keyboard_init(void) +/* Enable keyboard translated */ +static int enable_translated(void) +{ + if (!i8042_cmd(I8042_CMD_RD_CMD_BYTE)) { + int cmd = i8042_read_data_ps2(); + cmd |= I8042_CMD_BYTE_XLATE; + if (!i8042_cmd(I8042_CMD_WR_CMD_BYTE)) + i8042_write_data(cmd); + } else { + printf("ERROR: Keyboard i8042_cmd failed!\n"); + return 0; + } + return 1; +} + +/* Set scancode set 1 */ +static int set_scancode_set(void) { unsigned int ret; + ret = keyboard_cmd(I8042_KBCMD_SET_SCANCODE); + if (!ret) { + printf("ERROR: Keyboard set scancode failed!\n"); + return ret; + } + + ret = keyboard_cmd(I8042_SCANCODE_SET_1); + if (!ret) { + printf("ERROR: Keyboard scancode set#1 failed!\n"); + return ret; + } + + /* + * Set default parameters. + * Fix for broken QEMU ps/2 make scancodes. + */ + ret = keyboard_cmd(I8042_KBCMD_SET_DEFAULT); + if (!ret) { + printf("ERROR: Keyboard set default params failed!\n"); + return ret; + } + + /* Enable scanning */ + ret = keyboard_cmd(I8042_KBCMD_EN); + if (!ret) { + printf("ERROR: Keyboard enable scanning failed!\n"); + return ret; + } + + return ret; +} + +void keyboard_init(void) +{ map = &keyboard_layouts[0]; /* Initialized keyboard controller. */ @@ -328,34 +378,12 @@ void keyboard_init(void) /* Enable first PS/2 port */ i8042_cmd(I8042_CMD_EN_KB); - /* Set scancode set 1 */ - ret = keyboard_cmd(I8042_KBCMD_SET_SCANCODE); - if (!ret && !CONFIG(LP_PC_KEYBOARD_IGNORE_INIT_FAILURE)) { - printf("ERROR: Keyboard set scancode failed!\n"); - return; - } - - ret = keyboard_cmd(I8042_SCANCODE_SET_1); - if (!ret && !CONFIG(LP_PC_KEYBOARD_IGNORE_INIT_FAILURE)) { - printf("ERROR: Keyboard scancode set#1 failed!\n"); - return; - } - - /* - * Set default parameters. - * Fix for broken QEMU ps/2 make scancodes. - */ - ret = keyboard_cmd(0xf6); - if (!ret) { - printf("ERROR: Keyboard set default params failed!\n"); - return; - } - - /* Enable scanning */ - ret = keyboard_cmd(I8042_KBCMD_EN); - if (!ret && !CONFIG(LP_PC_KEYBOARD_IGNORE_INIT_FAILURE)) { - printf("ERROR: Keyboard enable scanning failed!\n"); - return; + if (CONFIG(LP_PC_KEYBOARD_AT_TRANSLATED)) { + if (!enable_translated()) + return; + } else { + if (!set_scancode_set()) + return; } console_add_input_driver(&cons); From 1b12b64dab57151d1f04d13d09c1afbf16a7485f Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Micha=C5=82=20=C5=BBygowski?= Date: Sun, 24 Nov 2019 16:32:05 +0100 Subject: [PATCH 0639/1242] AGESA, binaryPI: implement C bootblock MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Modify CAR setup to work in bootblock. Provide bootblock C file with necessary C bootblock functions. Additionally chache the ROM and set the MMCONF base before jumping to bootblock main. Change-Id: I29916a96f490ff717c69dc7cd565d74a83dbfb0d Signed-off-by: Michał Żygowski Signed-off-by: Kyösti Mälkki Reviewed-on: https://review.coreboot.org/c/coreboot/+/36914 Reviewed-by: Marshall Dawson Tested-by: build bot (Jenkins) --- src/cpu/amd/agesa/Kconfig | 8 +++++ src/cpu/amd/pi/Kconfig | 8 +++++ src/cpu/x86/lapic/Makefile.inc | 1 + src/drivers/amd/agesa/Makefile.inc | 6 ++++ src/drivers/amd/agesa/bootblock.c | 47 ++++++++++++++++++++++++++++ src/drivers/amd/agesa/cache_as_ram.S | 14 +++++++-- src/drivers/amd/agesa/romstage.c | 27 ++++++++++++++-- 7 files changed, 106 insertions(+), 5 deletions(-) create mode 100644 src/drivers/amd/agesa/bootblock.c diff --git a/src/cpu/amd/agesa/Kconfig b/src/cpu/amd/agesa/Kconfig index 5e1ff1d6c9..2c8f9c5e37 100644 --- a/src/cpu/amd/agesa/Kconfig +++ b/src/cpu/amd/agesa/Kconfig @@ -49,6 +49,14 @@ config DCACHE_RAM_SIZE hex default 0x10000 +config DCACHE_BSP_STACK_SIZE + hex + default 0x4000 + +config C_ENV_BOOTBLOCK_SIZE + hex + default 0x8000 + config ENABLE_MRC_CACHE bool "Use cached memory configuration" default n diff --git a/src/cpu/amd/pi/Kconfig b/src/cpu/amd/pi/Kconfig index 728c7b1ce7..c534b4d6e8 100644 --- a/src/cpu/amd/pi/Kconfig +++ b/src/cpu/amd/pi/Kconfig @@ -48,6 +48,14 @@ config DCACHE_RAM_SIZE hex default 0x10000 +config DCACHE_BSP_STACK_SIZE + hex + default 0x4000 + +config C_ENV_BOOTBLOCK_SIZE + hex + default 0x8000 + endif # CPU_AMD_PI source "src/cpu/amd/pi/00630F01/Kconfig" diff --git a/src/cpu/x86/lapic/Makefile.inc b/src/cpu/x86/lapic/Makefile.inc index 9454f8f00a..0d114782e1 100644 --- a/src/cpu/x86/lapic/Makefile.inc +++ b/src/cpu/x86/lapic/Makefile.inc @@ -1,6 +1,7 @@ ramstage-y += lapic.c ramstage-y += lapic_cpu_init.c ramstage-$(CONFIG_SMP) += secondary.S +bootblock-$(CONFIG_UDELAY_LAPIC) += apic_timer.c romstage-$(CONFIG_UDELAY_LAPIC) += apic_timer.c ramstage-$(CONFIG_UDELAY_LAPIC) += apic_timer.c postcar-$(CONFIG_UDELAY_LAPIC) += apic_timer.c diff --git a/src/drivers/amd/agesa/Makefile.inc b/src/drivers/amd/agesa/Makefile.inc index dfb385da80..3c3c4fc621 100644 --- a/src/drivers/amd/agesa/Makefile.inc +++ b/src/drivers/amd/agesa/Makefile.inc @@ -19,7 +19,13 @@ romstage-y += state_machine.c ramstage-y += state_machine.c +ifneq ($(CONFIG_ROMCC_BOOTBLOCK),y) +bootblock-y += bootblock.c +bootblock-y += cache_as_ram.S +else cpu_incs-y += $(src)/drivers/amd/agesa/cache_as_ram.S +endif + postcar-y += exit_car.S romstage-y += def_callouts.c diff --git a/src/drivers/amd/agesa/bootblock.c b/src/drivers/amd/agesa/bootblock.c new file mode 100644 index 0000000000..3763b98a3a --- /dev/null +++ b/src/drivers/amd/agesa/bootblock.c @@ -0,0 +1,47 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include +#include +#include +#include +#include + +#define EARLY_VMTRR_FLASH 6 + +static void set_early_mtrrs(void) +{ + /* Cache the ROM to speed up booting */ + set_var_mtrr(EARLY_VMTRR_FLASH, OPTIMAL_CACHE_ROM_BASE, + OPTIMAL_CACHE_ROM_SIZE, MTRR_TYPE_WRPROT); +} + +asmlinkage void bootblock_c_entry(uint64_t base_timestamp) +{ + enable_pci_mmconf(); + set_early_mtrrs(); + + bootblock_main_with_basetime(base_timestamp); +} + +asmlinkage void ap_bootblock_c_entry(void) +{ + enable_pci_mmconf(); + set_early_mtrrs(); + + void (*ap_romstage_entry)(void) = get_ap_entry_ptr(); + ap_romstage_entry(); /* execution does not return */ + halt(); +} diff --git a/src/drivers/amd/agesa/cache_as_ram.S b/src/drivers/amd/agesa/cache_as_ram.S index 4417e64595..1034992e17 100644 --- a/src/drivers/amd/agesa/cache_as_ram.S +++ b/src/drivers/amd/agesa/cache_as_ram.S @@ -27,9 +27,17 @@ .code32 .globl _cache_as_ram_setup, _cache_as_ram_setup_end +.global bootblock_pre_c_entry _cache_as_ram_setup: +/* + * on entry: + * mm0: BIST (ignored) + * mm2_mm1: timestamp at bootblock_protected_mode_entry + */ +bootblock_pre_c_entry: + post_code(0xa0) AMD_ENABLE_STACK @@ -51,8 +59,10 @@ _cache_as_ram_setup: and $0xfffffff0, %esp sub $8, %esp - pushl $0 /* tsc[63:32] */ - pushl $0 /* tsc[31:0] */ + movd %mm2, %eax + pushl %eax /* tsc[63:32] */ + movd %mm1, %eax + pushl %eax /* tsc[31:0] */ post_code(0xa2) diff --git a/src/drivers/amd/agesa/romstage.c b/src/drivers/amd/agesa/romstage.c index 48a81c57df..dbf8bd6070 100644 --- a/src/drivers/amd/agesa/romstage.c +++ b/src/drivers/amd/agesa/romstage.c @@ -11,6 +11,7 @@ * GNU General Public License for more details. */ +#include #include #include #include @@ -26,6 +27,8 @@ #include #include +void __weak board_BeforeAgesa(struct sysinfo *cb) { } + void __weak platform_once(struct sysinfo *cb) { board_BeforeAgesa(cb); @@ -39,6 +42,11 @@ static void fill_sysinfo(struct sysinfo *cb) agesa_set_interface(cb); } +/* APs will enter directly here from bootblock, bypassing verstage + * and potential fallback / normal bootflow detection. + */ +static void ap_romstage_main(void); + static void romstage_main(void) { struct postcar_frame pcf; @@ -48,13 +56,15 @@ static void romstage_main(void) int cbmem_initted = 0; /* Enable PCI MMIO configuration. */ - amd_initmmio(); + if (CONFIG(ROMCC_BOOTBLOCK)) + amd_initmmio(); fill_sysinfo(cb); if (initial_apic_id == 0) { - timestamp_init(timestamp_get()); + if (CONFIG(ROMCC_BOOTBLOCK)) + timestamp_init(timestamp_get()); timestamp_add_now(TS_START_ROMSTAGE); platform_once(cb); @@ -65,6 +75,9 @@ static void romstage_main(void) printk(BIOS_DEBUG, "APIC %02d: CPU Family_Model = %08x\n", initial_apic_id, cpuid_eax(1)); + if (!CONFIG(ROMCC_BOOTBLOCK)) + set_ap_entry_ptr(ap_romstage_main); + agesa_execute_state(cb, AMD_INIT_RESET); agesa_execute_state(cb, AMD_INIT_EARLY); @@ -105,7 +118,8 @@ static void ap_romstage_main(void) struct sysinfo *cb = &romstage_state; /* Enable PCI MMIO configuration. */ - amd_initmmio(); + if (CONFIG(ROMCC_BOOTBLOCK)) + amd_initmmio(); fill_sysinfo(cb); @@ -117,6 +131,7 @@ static void ap_romstage_main(void) halt(); } +#if CONFIG(ROMCC_BOOTBLOCK) /* This wrapper enables easy transition away from ROMCC_BOOTBLOCK * keeping changes in cache_as_ram.S easy to manage. */ @@ -129,3 +144,9 @@ asmlinkage void ap_bootblock_c_entry(void) { ap_romstage_main(); } +#else +asmlinkage void car_stage_entry(void) +{ + romstage_main(); +} +#endif From 5ee82832503ab46affbc5f12ce1088046e8ae28c Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ky=C3=B6sti=20M=C3=A4lkki?= Date: Tue, 3 Dec 2019 06:26:27 +0200 Subject: [PATCH 0640/1242] pcengines/apu2: Switch away from ROMCC_BOOTBLOCK MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add early SuperIO initialization in bootblock to enable early console. Also, remove some southbridge-specific initialization that has been moved to southbridge bootblock initialization in previous patch. The board obtains few additional timestamps: start of bootblock, end of bootblock, starting to load romstage and finished loading romstage. TEST=boot apu2 and launch Debian with Linux kernel 4.14.50 Signed-off-by: Michał Żygowski Change-Id: If770eff467b9a71d21eeb0963b6c3ebe72a88ef3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/36915 Reviewed-by: Kyösti Mälkki Tested-by: build bot (Jenkins) --- src/mainboard/pcengines/apu2/Kconfig | 1 - src/mainboard/pcengines/apu2/Makefile.inc | 2 + src/mainboard/pcengines/apu2/bootblock.c | 35 +++++++++++++++++ src/mainboard/pcengines/apu2/romstage.c | 48 ++--------------------- 4 files changed, 40 insertions(+), 46 deletions(-) create mode 100644 src/mainboard/pcengines/apu2/bootblock.c diff --git a/src/mainboard/pcengines/apu2/Kconfig b/src/mainboard/pcengines/apu2/Kconfig index b0360cd298..8c713e5f67 100644 --- a/src/mainboard/pcengines/apu2/Kconfig +++ b/src/mainboard/pcengines/apu2/Kconfig @@ -20,7 +20,6 @@ if BOARD_PCENGINES_APU2 || BOARD_PCENGINES_APU3 || BOARD_PCENGINES_APU4 || \ config BOARD_SPECIFIC_OPTIONS def_bool y - select ROMCC_BOOTBLOCK select CPU_AMD_PI_00730F01 select NORTHBRIDGE_AMD_PI_00730F01 select SOUTHBRIDGE_AMD_PI_AVALON diff --git a/src/mainboard/pcengines/apu2/Makefile.inc b/src/mainboard/pcengines/apu2/Makefile.inc index 4e6364e047..84ea41485c 100644 --- a/src/mainboard/pcengines/apu2/Makefile.inc +++ b/src/mainboard/pcengines/apu2/Makefile.inc @@ -14,6 +14,8 @@ # GNU General Public License for more details. # +bootblock-y += bootblock.c + romstage-y += BiosCallOuts.c romstage-y += OemCustomize.c romstage-y += gpio_ftns.c diff --git a/src/mainboard/pcengines/apu2/bootblock.c b/src/mainboard/pcengines/apu2/bootblock.c new file mode 100644 index 0000000000..8318f39287 --- /dev/null +++ b/src/mainboard/pcengines/apu2/bootblock.c @@ -0,0 +1,35 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include +#include +#include + +#define SIO_PORT 0x2e +#define SERIAL1_DEV PNP_DEV(SIO_PORT, NCT5104D_SP1) +#define SERIAL2_DEV PNP_DEV(SIO_PORT, NCT5104D_SP2) + +void bootblock_mainboard_early_init(void) +{ + hudson_lpc_port80(); + hudson_clk_output_48Mhz(); + + /* COM2 on apu5 is reserved so only COM1 should be supported */ + if ((CONFIG_UART_FOR_CONSOLE == 1) && + !CONFIG(BOARD_PCENGINES_APU5)) + nuvoton_enable_serial(SERIAL2_DEV, CONFIG_TTYS0_BASE); + else if (CONFIG_UART_FOR_CONSOLE == 0) + nuvoton_enable_serial(SERIAL1_DEV, CONFIG_TTYS0_BASE); +} diff --git a/src/mainboard/pcengines/apu2/romstage.c b/src/mainboard/pcengines/apu2/romstage.c index 3e2672ad70..27f0183787 100644 --- a/src/mainboard/pcengines/apu2/romstage.c +++ b/src/mainboard/pcengines/apu2/romstage.c @@ -14,63 +14,22 @@ */ #include +#include #include -#include #include -#include -#include -#include #include #include -#include -#include -#include -#include #include "gpio_ftns.h" -#define SIO_PORT 0x2e -#define SERIAL1_DEV PNP_DEV(SIO_PORT, NCT5104D_SP1) -#define SERIAL2_DEV PNP_DEV(SIO_PORT, NCT5104D_SP2) - static void early_lpc_init(void); void board_BeforeAgesa(struct sysinfo *cb) { u32 val; - pci_devfn_t dev; - u32 data; - /* - * In Hudson RRG, PMIOxD2[5:4] is "Drive strength control for - * LpcClk[1:0]". This following register setting has been - * replicated in every reference design since Parmer, so it is - * believed to be required even though it is not documented in - * the SoC BKDGs. Without this setting, there is no serial - * output. - */ - outb(0xd2, 0xcd6); - outb(0x00, 0xcd7); - - post_code(0x30); early_lpc_init(); - hudson_clk_output_48Mhz(); - post_code(0x31); - - dev = PCI_DEV(0, 0x14, 3); - data = pci_read_config32(dev, LPC_IO_OR_MEM_DECODE_ENABLE); - /* enable 0x2e/0x4e IO decoding before configuring SuperIO */ - pci_write_config32(dev, LPC_IO_OR_MEM_DECODE_ENABLE, data | 3); - - /* COM2 on apu5 is reserved so only COM1 should be supported */ - if ((CONFIG_UART_FOR_CONSOLE == 1) && - !CONFIG(BOARD_PCENGINES_APU5)) - nuvoton_enable_serial(SERIAL2_DEV, CONFIG_TTYS0_BASE); - else if (CONFIG_UART_FOR_CONSOLE == 0) - nuvoton_enable_serial(SERIAL1_DEV, CONFIG_TTYS0_BASE); - - /* Disable SVI2 controller to wait for command completion */ val = pci_read_config32(PCI_DEV(0, 0x18, 5), 0x12C); if (!(val & (1 << 30))) { @@ -78,9 +37,8 @@ void board_BeforeAgesa(struct sysinfo *cb) pci_write_config32(PCI_DEV(0, 0x18, 5), 0x12C, val); } - /* Disable PCI-PCI bridge and release GPIO32/33 for other uses. */ - outb(0xea, 0xcd6); - outb(0x1, 0xcd7); + /* Release GPIO32/33 for other uses. */ + pm_write8(0xea, 1); } static void early_lpc_init(void) From a73317e5cff3d104d567c341b114d242e0c0e5c0 Mon Sep 17 00:00:00 2001 From: Patrick Georgi Date: Tue, 10 Dec 2019 20:27:38 +0100 Subject: [PATCH 0641/1242] Documentation: enable ditaa integration For prettier diagrams: http://ditaa.sourceforge.net/ Change-Id: Ic28dc5ea9d82ff6bf8654e2e33e675a536348654 Signed-off-by: Patrick Georgi Reviewed-on: https://review.coreboot.org/c/coreboot/+/37646 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel Reviewed-by: Angel Pons --- Documentation/conf.py | 2 ++ util/docker/doc.coreboot.org/Dockerfile | 9 ++++++++- util/docker/doc.coreboot.org/ditaa.sh | 2 ++ 3 files changed, 12 insertions(+), 1 deletion(-) create mode 100755 util/docker/doc.coreboot.org/ditaa.sh diff --git a/Documentation/conf.py b/Documentation/conf.py index 85df9ea51e..8848ee6512 100644 --- a/Documentation/conf.py +++ b/Documentation/conf.py @@ -25,6 +25,8 @@ release = subprocess.check_output(('git', 'describe')).decode("utf-8") # The short X.Y version. version = release.split("-")[0] +extensions = ['sphinxcontrib.ditaa'] + # The language for content autogenerated by Sphinx. Refer to documentation # for a list of supported languages. # diff --git a/util/docker/doc.coreboot.org/Dockerfile b/util/docker/doc.coreboot.org/Dockerfile index d05e8b5835..23f5f50403 100644 --- a/util/docker/doc.coreboot.org/Dockerfile +++ b/util/docker/doc.coreboot.org/Dockerfile @@ -2,14 +2,21 @@ FROM alpine:3.8 COPY makeSphinx.sh /makeSphinx.sh -RUN apk add --no-cache python3 make bash git \ +ADD https://sourceforge.net/projects/ditaa/files/ditaa/0.9/ditaa0_9.zip/download /tmp/ditaa.zip + +RUN apk add --no-cache python3 make bash git openjdk8-jre ttf-dejavu fontconfig \ && pip3 install --upgrade --no-cache-dir pip \ && pip3 install --no-cache-dir \ sphinx===1.8.3 \ sphinx_rtd_theme===0.4.2 \ recommonmark===0.5.0 \ sphinx_autobuild===0.7.1 \ + sphinxcontrib-ditaa===0.6 \ && chmod 755 /makeSphinx.sh +RUN cd /tmp \ + && unzip ditaa.zip \ + && mv ditaa0_9.jar /usr/lib +ADD ditaa.sh /usr/bin/ditaa VOLUME /data-in /data-out diff --git a/util/docker/doc.coreboot.org/ditaa.sh b/util/docker/doc.coreboot.org/ditaa.sh new file mode 100755 index 0000000000..5f27f53497 --- /dev/null +++ b/util/docker/doc.coreboot.org/ditaa.sh @@ -0,0 +1,2 @@ +#!/bin/sh +exec java -jar /usr/lib/ditaa0_9.jar $* From b9edd8be67c0f6c503451af75e6c1609fc6ec7ad Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ky=C3=B6sti=20M=C3=A4lkki?= Date: Tue, 3 Dec 2019 13:32:11 +0200 Subject: [PATCH 0642/1242] asrock/imb-a180: Switch away from ROMCC_BOOTBLOCK MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Change-Id: I603e6c83d72cf6c1d8f8c6eef652fdf954a3a284 Signed-off-by: Kyösti Mälkki Reviewed-on: https://review.coreboot.org/c/coreboot/+/37453 Reviewed-by: HAOUAS Elyes Reviewed-by: Angel Pons Reviewed-by: Michał Żygowski Tested-by: build bot (Jenkins) --- src/mainboard/asrock/imb-a180/Kconfig | 1 - src/mainboard/asrock/imb-a180/Makefile.inc | 2 ++ .../imb-a180/{romstage.c => bootblock.c} | 26 ++++--------------- 3 files changed, 7 insertions(+), 22 deletions(-) rename src/mainboard/asrock/imb-a180/{romstage.c => bootblock.c} (69%) diff --git a/src/mainboard/asrock/imb-a180/Kconfig b/src/mainboard/asrock/imb-a180/Kconfig index b753424c84..8fca61c899 100644 --- a/src/mainboard/asrock/imb-a180/Kconfig +++ b/src/mainboard/asrock/imb-a180/Kconfig @@ -17,7 +17,6 @@ if BOARD_ASROCK_IMB_A180 config BOARD_SPECIFIC_OPTIONS def_bool y - select ROMCC_BOOTBLOCK select CPU_AMD_AGESA_FAMILY16_KB select NORTHBRIDGE_AMD_AGESA_FAMILY16_KB select SOUTHBRIDGE_AMD_AGESA_YANGTZE diff --git a/src/mainboard/asrock/imb-a180/Makefile.inc b/src/mainboard/asrock/imb-a180/Makefile.inc index f8895faa92..4dde2cfd1e 100644 --- a/src/mainboard/asrock/imb-a180/Makefile.inc +++ b/src/mainboard/asrock/imb-a180/Makefile.inc @@ -13,6 +13,8 @@ # GNU General Public License for more details. # +bootblock-y += bootblock.c + romstage-y += buildOpts.c romstage-y += BiosCallOuts.c romstage-y += OemCustomize.c diff --git a/src/mainboard/asrock/imb-a180/romstage.c b/src/mainboard/asrock/imb-a180/bootblock.c similarity index 69% rename from src/mainboard/asrock/imb-a180/romstage.c rename to src/mainboard/asrock/imb-a180/bootblock.c index 5b9a2263e5..f6bd5c40de 100644 --- a/src/mainboard/asrock/imb-a180/romstage.c +++ b/src/mainboard/asrock/imb-a180/bootblock.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; version 2 of the License. @@ -13,35 +11,21 @@ * GNU General Public License for more details. */ -#include -#include -#include -#include - -#include -#include - +#include +#include +#include #include #include #define SERIAL_DEV PNP_DEV(0x2e, W83627UHG_SP1) -void board_BeforeAgesa(struct sysinfo *cb) +void bootblock_mainboard_early_init(void) { volatile u32 *addr32; u32 t32; - /* Set LPC decode enables. */ - pci_devfn_t dev = PCI_DEV(0, 0x14, 3); - pci_write_config32(dev, 0x44, 0xff03ffd5); - - /* Enable the AcpiMmio space */ - outb(0x24, 0xcd6); - outb(0x1, 0xcd7); - /* Disable PCI-PCI bridge and release GPIO32/33 for other uses. */ - outb(0xea, 0xcd6); - outb(0x1, 0xcd7); + pm_write8(0xea, 0x1); /* Set auxiliary output clock frequency on OSCOUT1 pin to be 48MHz */ addr32 = (u32 *)0xfed80e28; From cc6100f2d986fcce8f880ee490bd8fe47696ef30 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ky=C3=B6sti=20M=C3=A4lkki?= Date: Tue, 3 Dec 2019 12:58:48 +0200 Subject: [PATCH 0643/1242] lenovo/g505s: Switch away from ROMCC_BOOTBLOCK MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit No special treatment required for bootblock. Change-Id: Icb673bba1ba210a077e9569de70b6c4f3cbd1e6b Signed-off-by: Kyösti Mälkki Reviewed-on: https://review.coreboot.org/c/coreboot/+/37499 Reviewed-by: HAOUAS Elyes Reviewed-by: Angel Pons Reviewed-by: Michał Żygowski Tested-by: build bot (Jenkins) --- src/mainboard/lenovo/g505s/Kconfig | 1 - src/mainboard/lenovo/g505s/romstage.c | 21 --------------------- 2 files changed, 22 deletions(-) delete mode 100644 src/mainboard/lenovo/g505s/romstage.c diff --git a/src/mainboard/lenovo/g505s/Kconfig b/src/mainboard/lenovo/g505s/Kconfig index b220b97b06..6ffe508ff9 100644 --- a/src/mainboard/lenovo/g505s/Kconfig +++ b/src/mainboard/lenovo/g505s/Kconfig @@ -18,7 +18,6 @@ if BOARD_LENOVO_G505S config BOARD_SPECIFIC_OPTIONS def_bool y select SYSTEM_TYPE_LAPTOP - select ROMCC_BOOTBLOCK select CPU_AMD_AGESA_FAMILY15_TN select NORTHBRIDGE_AMD_AGESA_FAMILY15_TN select SOUTHBRIDGE_AMD_AGESA_HUDSON diff --git a/src/mainboard/lenovo/g505s/romstage.c b/src/mainboard/lenovo/g505s/romstage.c deleted file mode 100644 index 0395566b74..0000000000 --- a/src/mainboard/lenovo/g505s/romstage.c +++ /dev/null @@ -1,21 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include - -void board_BeforeAgesa(struct sysinfo *cb) -{ -} From 3c73dadd6fa4226e616a4d93b241ccda7a98cbe9 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ky=C3=B6sti=20M=C3=A4lkki?= Date: Tue, 3 Dec 2019 12:58:48 +0200 Subject: [PATCH 0644/1242] hp/pavilion_m6_1035dx: Switch away from ROMCC_BOOTBLOCK MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit No special treatment required for bootblock. Change-Id: I0036614579045b62829577bb2ae94266b2d62310 Signed-off-by: Kyösti Mälkki Reviewed-on: https://review.coreboot.org/c/coreboot/+/37500 Reviewed-by: HAOUAS Elyes Reviewed-by: Angel Pons Reviewed-by: Michał Żygowski Tested-by: build bot (Jenkins) --- src/mainboard/hp/pavilion_m6_1035dx/Kconfig | 1 - .../hp/pavilion_m6_1035dx/romstage.c | 21 ------------------- 2 files changed, 22 deletions(-) delete mode 100644 src/mainboard/hp/pavilion_m6_1035dx/romstage.c diff --git a/src/mainboard/hp/pavilion_m6_1035dx/Kconfig b/src/mainboard/hp/pavilion_m6_1035dx/Kconfig index 144b1138f6..c6c35df390 100644 --- a/src/mainboard/hp/pavilion_m6_1035dx/Kconfig +++ b/src/mainboard/hp/pavilion_m6_1035dx/Kconfig @@ -18,7 +18,6 @@ if BOARD_HP_PAVILION_M6_1035DX config BOARD_SPECIFIC_OPTIONS def_bool y select SYSTEM_TYPE_LAPTOP - select ROMCC_BOOTBLOCK select CPU_AMD_AGESA_FAMILY15_TN select NORTHBRIDGE_AMD_AGESA_FAMILY15_TN select SOUTHBRIDGE_AMD_AGESA_HUDSON diff --git a/src/mainboard/hp/pavilion_m6_1035dx/romstage.c b/src/mainboard/hp/pavilion_m6_1035dx/romstage.c deleted file mode 100644 index 0395566b74..0000000000 --- a/src/mainboard/hp/pavilion_m6_1035dx/romstage.c +++ /dev/null @@ -1,21 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include - -void board_BeforeAgesa(struct sysinfo *cb) -{ -} From 199f98bc433f36fd0f91edd2495ecc3fd23afdbf Mon Sep 17 00:00:00 2001 From: Christian Walter Date: Mon, 9 Dec 2019 13:27:10 +0100 Subject: [PATCH 0645/1242] superio/common/generic: Assign resources behind device If multiple devices are behind a dev, we would only recognise port 0. We need to scan the complete 'bus'. Tested on ASpeed AST2500 Change-Id: Id80a2ae6e82c151b8d8adc9c5f35f38362d538fa Signed-off-by: Christian Walter Reviewed-on: https://review.coreboot.org/c/coreboot/+/37607 Reviewed-by: Patrick Rudolph Reviewed-by: Nico Huber Tested-by: build bot (Jenkins) --- src/superio/common/generic.c | 9 ++++----- 1 file changed, 4 insertions(+), 5 deletions(-) diff --git a/src/superio/common/generic.c b/src/superio/common/generic.c index 429ee51319..7ac1f8374e 100644 --- a/src/superio/common/generic.c +++ b/src/superio/common/generic.c @@ -21,6 +21,9 @@ static void generic_set_resources(struct device *dev) { struct resource *res; + if (dev->link_list) + assign_resources(dev->link_list); + for (res = dev->resource_list; res; res = res->next) { if (!(res->flags & IORESOURCE_ASSIGNED)) continue; @@ -167,6 +170,7 @@ static struct device_operations ops = { .read_resources = generic_read_resources, .set_resources = generic_set_resources, .enable_resources = DEVICE_NOOP, + .scan_bus = scan_static_bus, #if CONFIG(HAVE_ACPI_TABLES) .acpi_fill_ssdt_generator = generic_ssdt, .acpi_name = generic_acpi_name, @@ -182,11 +186,6 @@ static void enable_dev(struct device *dev) else dev->ops = &ops; - /* - * Need to call enable_dev() on the devices "behind" the Generic Super I/O. - * coreboot's generic allocator doesn't expect them behind PnP devices. - */ - enable_static_devices(dev); } struct chip_operations superio_common_ops = { From f1a4ae0a48e90de2a8a029c38c4583506b02a676 Mon Sep 17 00:00:00 2001 From: Patrick Rudolph Date: Mon, 30 Sep 2019 11:02:04 +0200 Subject: [PATCH 0646/1242] drivers/aspeed/common: Add support for high resolution framebuffer * Implement reading EDID over software I2C. * Fall back to VGA if no monitor connected for BMC KVM * Copy the linux kernel code and add a bunch of wrapper structs to make it compile. * Convert the EDID to a drm_display_mode, which is understood by the driver. * Properly select HAVE_LINEAR_FRAMEBUFFER and HAVE_VGA_TEXT_FRAMEBUFFER Tested on Supermicro X11SSH-TF using FullHD VGA monitor. Initializes the graphics in about 1 second, which is twice as fast as the VGA Option ROM. The framebuffer is advertised and working in tianocore. Change-Id: I7803566b64158405efc04a39f80a0ec98b44e646 Signed-off-by: Patrick Rudolph Reviewed-on: https://review.coreboot.org/c/coreboot/+/35726 Reviewed-by: Philipp Deppenwiese Tested-by: build bot (Jenkins) --- src/drivers/aspeed/ast2050/Kconfig | 1 - src/drivers/aspeed/ast2050/ast2050.c | 18 +- src/drivers/aspeed/common/Kconfig | 5 +- src/drivers/aspeed/common/Makefile.inc | 5 +- src/drivers/aspeed/common/ast_drv.h | 115 ++++ src/drivers/aspeed/common/ast_i2c.c | 140 ++++ src/drivers/aspeed/common/ast_mode.c | 601 ++++++++++++++++++ .../aspeed/common/ast_mode_corebootfb.c | 256 ++++++++ src/drivers/aspeed/common/ast_tables.h | 191 +++--- 9 files changed, 1247 insertions(+), 85 deletions(-) create mode 100644 src/drivers/aspeed/common/ast_i2c.c create mode 100644 src/drivers/aspeed/common/ast_mode.c create mode 100644 src/drivers/aspeed/common/ast_mode_corebootfb.c diff --git a/src/drivers/aspeed/ast2050/Kconfig b/src/drivers/aspeed/ast2050/Kconfig index 337b1817f3..7d2c728204 100644 --- a/src/drivers/aspeed/ast2050/Kconfig +++ b/src/drivers/aspeed/ast2050/Kconfig @@ -1,5 +1,4 @@ config DRIVERS_ASPEED_AST2050 bool select DRIVERS_ASPEED_AST_COMMON - select HAVE_VGA_TEXT_FRAMEBUFFER select MAINBOARD_HAS_NATIVE_VGA_INIT diff --git a/src/drivers/aspeed/ast2050/ast2050.c b/src/drivers/aspeed/ast2050/ast2050.c index b1bd276c74..67a1a803fe 100644 --- a/src/drivers/aspeed/ast2050/ast2050.c +++ b/src/drivers/aspeed/ast2050/ast2050.c @@ -48,13 +48,19 @@ static void aspeed_ast2050_init(struct device *dev) outb(0xa6, 0x3d4); outb(0x2f, 0x3d5); outb(0xa7, 0x3d4); outb(0x3f, 0x3d5); - /* Initialize standard VGA text mode */ - vga_io_init(); - vga_textmode_init(); - printk(BIOS_INFO, "ASpeed VGA text mode initialized\n"); + if (CONFIG(VGA_TEXT_FRAMEBUFFER)) { + /* Initialize standard VGA text mode */ + vga_io_init(); - /* if we don't have console, at least print something... */ - vga_line_write(0, "ASpeed VGA text mode initialized"); + vga_textmode_init(); + printk(BIOS_INFO, "ASpeed VGA text mode initialized\n"); + + /* if we don't have console, at least print something... */ + vga_line_write(0, "ASpeed VGA text mode initialized"); + } else if (CONFIG(GENERIC_LINEAR_FRAMEBUFFER)) { + ast_driver_framebuffer_init(&drm_dev, 0); + printk(BIOS_INFO, "ASpeed high resolution framebuffer initialized\n"); + } } static struct device_operations aspeed_ast2050_ops = { diff --git a/src/drivers/aspeed/common/Kconfig b/src/drivers/aspeed/common/Kconfig index 653782f8f4..79c4c75396 100644 --- a/src/drivers/aspeed/common/Kconfig +++ b/src/drivers/aspeed/common/Kconfig @@ -1,3 +1,6 @@ config DRIVERS_ASPEED_AST_COMMON bool - select VGA + select HAVE_LINEAR_FRAMEBUFFER if MAINBOARD_DO_NATIVE_VGA_INIT + select HAVE_VGA_TEXT_FRAMEBUFFER if MAINBOARD_DO_NATIVE_VGA_INIT + select VGA if VGA_TEXT_FRAMEBUFFER + select SOFTWARE_I2C if GENERIC_LINEAR_FRAMEBUFFER diff --git a/src/drivers/aspeed/common/Makefile.inc b/src/drivers/aspeed/common/Makefile.inc index 75f8b4899b..1f4b858a5a 100644 --- a/src/drivers/aspeed/common/Makefile.inc +++ b/src/drivers/aspeed/common/Makefile.inc @@ -1 +1,4 @@ -ramstage-$(CONFIG_DRIVERS_ASPEED_AST_COMMON) += ast_dp501.c ast_main.c ast_post.c +ifeq ($(CONFIG_DRIVERS_ASPEED_AST_COMMON),y) +ramstage-y += ast_dp501.c ast_main.c ast_post.c +ramstage-$(CONFIG_GENERIC_LINEAR_FRAMEBUFFER) += ast_mode.c ast_i2c.c ast_mode_corebootfb.c +endif diff --git a/src/drivers/aspeed/common/ast_drv.h b/src/drivers/aspeed/common/ast_drv.h index c1794694e0..39f49433da 100644 --- a/src/drivers/aspeed/common/ast_drv.h +++ b/src/drivers/aspeed/common/ast_drv.h @@ -46,6 +46,7 @@ enum ast_chip { AST2150, AST2300, AST2400, + AST2500, AST1180, }; @@ -192,6 +193,8 @@ static inline void ast_open_key(struct ast_private *ast) #define AST_HWC_SIZE (AST_MAX_HWC_WIDTH*AST_MAX_HWC_HEIGHT*2) #define AST_HWC_SIGNATURE_SIZE 32 +#define EINVAL 22 /* Invalid argument */ + #define AST_DEFAULT_HWC_NUM 2 /* define for signature structure */ #define AST_HWC_SIGNATURE_CHECKSUM 0x00 @@ -202,6 +205,99 @@ static inline void ast_open_key(struct ast_private *ast) #define AST_HWC_SIGNATURE_HOTSPOTX 0x14 #define AST_HWC_SIGNATURE_HOTSPOTY 0x18 +/* ast_mode.c stuff */ +struct ast_vbios_stdtable { + u8 misc; + u8 seq[4]; + u8 crtc[25]; + u8 ar[20]; + u8 gr[9]; +}; + +struct ast_vbios_enhtable { + u32 ht; + u32 hde; + u32 hfp; + u32 hsync; + u32 vt; + u32 vde; + u32 vfp; + u32 vsync; + u32 dclk_index; + u32 flags; + u32 refresh_rate; + u32 refresh_rate_index; + u32 mode_id; +}; + +struct ast_vbios_dclk_info { + u8 param1; + u8 param2; + u8 param3; +}; + +struct ast_vbios_mode_info { + const struct ast_vbios_stdtable *std_table; + const struct ast_vbios_enhtable *enh_table; +}; + +#define DRM_MODE_FLAG_NVSYNC 1 +#define DRM_MODE_FLAG_PVSYNC 2 +#define DRM_MODE_FLAG_NHSYNC 4 +#define DRM_MODE_FLAG_PHSYNC 8 + +struct drm_display_mode { + /* Proposed mode values */ + u16 vrefresh; /* in Hz */ + u32 clock; + u16 hdisplay; + u16 vdisplay; + u32 flags; + + /* Actual mode we give to hw */ + u16 crtc_hdisplay; + u16 crtc_htotal; + u16 crtc_hblank_start; + u16 crtc_hblank_end; + u16 crtc_hsync_start; + u16 crtc_hsync_end; + u16 crtc_vtotal; + u16 crtc_vsync_start; + u16 crtc_vsync_end; + u16 crtc_vdisplay; + u16 crtc_vblank_start; + u16 crtc_vblank_end; +}; + +struct drm_format { + u32 cpp[1]; /* Colors per pixel */ +}; + +struct drm_framebuffer { + u32 pitches[1]; + struct drm_format *format; + u32 mmio_addr; +}; + +struct drm_primary { + struct drm_framebuffer *fb; +}; + +struct drm_crtc { + struct drm_device *dev; + struct drm_primary *primary; + struct drm_display_mode mode; +}; + +struct drm_connector { + struct drm_device *dev; +}; + +enum drm_mode_status { + MODE_NOMODE, + MODE_OK +}; + #define AST_MM_ALIGN_SHIFT 4 #define AST_MM_ALIGN_MASK ((1 << AST_MM_ALIGN_SHIFT) - 1) @@ -222,4 +318,23 @@ bool ast_backup_fw(struct drm_device *dev, u8 *addr, u32 size); bool ast_dp501_read_edid(struct drm_device *dev, u8 *ediddata); u8 ast_get_dp501_max_clk(struct drm_device *dev); void ast_init_3rdtx(struct drm_device *dev); + +/* ast mode */ +int ast_crtc_mode_set(struct drm_crtc *crtc, + struct drm_display_mode *mode, + struct drm_display_mode *adjusted_mode); +enum drm_mode_status ast_mode_valid(struct drm_connector *connector, + const unsigned int hdisplay, + const unsigned int vdisplay); +void ast_hide_cursor(struct drm_crtc *crtc); +void ast_set_offset_reg(struct drm_crtc *crtc); +void ast_set_start_address_crt1(struct ast_private *ast, u32 offset); + +/* ast_mode_corebootfb */ +int ast_driver_framebuffer_init(struct drm_device *dev, int flags); +int ast_crtc_do_set_base(struct drm_crtc *crtc); + +/* ast i2c */ +int ast_software_i2c_read(struct ast_private *ast_priv, uint8_t edid[128]); + #endif diff --git a/src/drivers/aspeed/common/ast_i2c.c b/src/drivers/aspeed/common/ast_i2c.c new file mode 100644 index 0000000000..0838d10fcb --- /dev/null +++ b/src/drivers/aspeed/common/ast_i2c.c @@ -0,0 +1,140 @@ +/* + * Copied from Linux drivers/gpu/drm/ast/ast_mode.c + * + * Copyright 2012 Red Hat Inc. + * Parts based on xf86-video-ast + * Copyright (c) 2005 ASPEED Technology Inc. + * Copyright Dave Airlie + * Copyright 2019 9Elements Agency GmbH + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the + * "Software"), to deal in the Software without restriction, including + * without limitation the rights to use, copy, modify, merge, publish, + * distribute, sub license, and/or sell copies of the Software, and to + * permit persons to whom the Software is furnished to do so, subject to + * the following conditions: + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, + * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR + * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE + * USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * The above copyright notice and this permission notice (including the + * next paragraph) shall be included in all copies or substantial portions + * of the Software. + * + */ + +#include +#include + +#include "ast_drv.h" + +static struct ast_private *ast; + +#define _GET_INDEX_REG(x) ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xb7, (x)) +#define ASPEED_BUS 0 + +static int get_clock(unsigned int bus) +{ + uint32_t val, val2, count, pass; + + count = 0; + pass = 0; + val = (_GET_INDEX_REG(0x10) >> 4) & 0x01; + do { + val2 = (_GET_INDEX_REG(0x10) >> 4) & 0x01; + if (val == val2) { + pass++; + } else { + pass = 0; + val = (_GET_INDEX_REG(0x10) >> 4) & 0x01; + } + } while ((pass < 5) && (count++ < 0x10000)); + + return val & 1 ? 1 : 0; +} + +static int get_data(unsigned int bus) +{ + uint32_t val, val2, count, pass; + + count = 0; + pass = 0; + val = (_GET_INDEX_REG(0x20) >> 5) & 0x01; + do { + val2 = (_GET_INDEX_REG(0x20) >> 5) & 0x01; + if (val == val2) { + pass++; + } else { + pass = 0; + val = (_GET_INDEX_REG(0x20) >> 5) & 0x01; + } + } while ((pass < 5) && (count++ < 0x10000)); + + return val & 1 ? 1 : 0; +} + +static void set_clock(unsigned int bus, int clock) +{ + int i; + u8 ujcrb7, jtemp; + + for (i = 0; i < 0x10000; i++) { + ujcrb7 = ((clock & 0x01) ? 0 : 1); + ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xb7, 0xf4, ujcrb7); + jtemp = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xb7, 0x01); + if (ujcrb7 == jtemp) + break; + } +} + +static void set_data(unsigned int bus, int data) +{ + int i; + u8 ujcrb7, jtemp; + + for (i = 0; i < 0x10000; i++) { + ujcrb7 = ((data & 0x01) ? 0 : 1) << 2; + ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xb7, 0xf1, ujcrb7); + jtemp = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xb7, 0x04); + if (ujcrb7 == jtemp) + break; + } +} + +static struct software_i2c_ops ast_ops = { + .set_sda = set_data, + .set_scl = set_clock, + .get_sda = get_data, + .get_scl = get_clock, +}; + +int ast_software_i2c_read(struct ast_private *ast_priv, uint8_t edid[128]) +{ + struct software_i2c_ops *backup; + int ret; + + backup = software_i2c[ASPEED_BUS]; + + software_i2c[ASPEED_BUS] = &ast_ops; + + ast = ast_priv; + + /* Ast POST pulled SDA and SCL low, recover the bus to a known state */ + set_clock(ASPEED_BUS, 1); + set_data(ASPEED_BUS, 1); + + udelay(100); + + /* Need to reset internal EEPROM counter to 0 */ + ret = i2c_read_bytes(ASPEED_BUS, 0x50, 0, edid, 128); + + software_i2c[ASPEED_BUS] = backup; + + return ret; +} diff --git a/src/drivers/aspeed/common/ast_mode.c b/src/drivers/aspeed/common/ast_mode.c new file mode 100644 index 0000000000..2b6cedae3c --- /dev/null +++ b/src/drivers/aspeed/common/ast_mode.c @@ -0,0 +1,601 @@ +/* + * Copied from Linux drivers/gpu/drm/ast/ast_mode.c + * + * Copyright 2012 Red Hat Inc. + * Parts based on xf86-video-ast + * Copyright (c) 2005 ASPEED Technology Inc. + * Copyright Dave Airlie + * Copyright 2019 9Elements Agency GmbH + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the + * "Software"), to deal in the Software without restriction, including + * without limitation the rights to use, copy, modify, merge, publish, + * distribute, sub license, and/or sell copies of the Software, and to + * permit persons to whom the Software is furnished to do so, subject to + * the following conditions: + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, + * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR + * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE + * USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * The above copyright notice and this permission notice (including the + * next paragraph) shall be included in all copies or substantial portions + * of the Software. + * + * Please try to keep as close as possible to the upstream source. + */ + +#include "ast_drv.h" +#include "ast_tables.h" + + +static inline void ast_load_palette_index(struct ast_private *ast, + u8 index, u8 red, u8 green, + u8 blue) +{ + ast_io_write8(ast, AST_IO_DAC_INDEX_WRITE, index); + ast_io_read8(ast, AST_IO_SEQ_PORT); + ast_io_write8(ast, AST_IO_DAC_DATA, red); + ast_io_read8(ast, AST_IO_SEQ_PORT); + ast_io_write8(ast, AST_IO_DAC_DATA, green); + ast_io_read8(ast, AST_IO_SEQ_PORT); + ast_io_write8(ast, AST_IO_DAC_DATA, blue); + ast_io_read8(ast, AST_IO_SEQ_PORT); +} + +static void ast_crtc_load_lut(struct drm_crtc *crtc) +{ + struct ast_private *ast = crtc->dev->dev_private; + /* FIXME: Gamma cor 2.6 ? */ + for (int i = 0; i < 256; i++) + ast_load_palette_index(ast, i, i, i, i); + +} + +static bool ast_get_vbios_mode_info(struct drm_crtc *crtc, struct drm_display_mode *mode, + struct drm_display_mode *adjusted_mode, + struct ast_vbios_mode_info *vbios_mode) +{ + struct ast_private *ast = crtc->dev->dev_private; + const struct drm_framebuffer *fb = crtc->primary->fb; + u32 refresh_rate_index = 0, mode_id, color_index, refresh_rate; + const struct ast_vbios_enhtable *best = NULL; + u32 hborder, vborder; + bool check_sync; + + switch (fb->format->cpp[0] * 8) { + case 8: + vbios_mode->std_table = &vbios_stdtable[VGAModeIndex]; + color_index = VGAModeIndex - 1; + break; + case 16: + vbios_mode->std_table = &vbios_stdtable[HiCModeIndex]; + color_index = HiCModeIndex; + break; + case 24: + case 32: + vbios_mode->std_table = &vbios_stdtable[TrueCModeIndex]; + color_index = TrueCModeIndex; + break; + default: + return false; + } + + switch (crtc->mode.crtc_hdisplay) { + case 640: + vbios_mode->enh_table = &res_640x480[refresh_rate_index]; + break; + case 800: + vbios_mode->enh_table = &res_800x600[refresh_rate_index]; + break; + case 1024: + vbios_mode->enh_table = &res_1024x768[refresh_rate_index]; + break; + case 1280: + if (crtc->mode.crtc_vdisplay == 800) + vbios_mode->enh_table = &res_1280x800[refresh_rate_index]; + else + vbios_mode->enh_table = &res_1280x1024[refresh_rate_index]; + break; + case 1360: + vbios_mode->enh_table = &res_1360x768[refresh_rate_index]; + break; + case 1440: + vbios_mode->enh_table = &res_1440x900[refresh_rate_index]; + break; + case 1600: + if (crtc->mode.crtc_vdisplay == 900) + vbios_mode->enh_table = &res_1600x900[refresh_rate_index]; + else + vbios_mode->enh_table = &res_1600x1200[refresh_rate_index]; + break; + case 1680: + vbios_mode->enh_table = &res_1680x1050[refresh_rate_index]; + break; + case 1920: + if (crtc->mode.crtc_vdisplay == 1080) + vbios_mode->enh_table = &res_1920x1080[refresh_rate_index]; + else + vbios_mode->enh_table = &res_1920x1200[refresh_rate_index]; + break; + default: + return false; + } + + refresh_rate = mode->vrefresh; + check_sync = vbios_mode->enh_table->flags & WideScreenMode; + do { + const struct ast_vbios_enhtable *loop = vbios_mode->enh_table; + + while (loop->refresh_rate != 0xff) { + if ((check_sync) && + (((mode->flags & DRM_MODE_FLAG_NVSYNC) && + (loop->flags & PVSync)) || + ((mode->flags & DRM_MODE_FLAG_PVSYNC) && + (loop->flags & NVSync)) || + ((mode->flags & DRM_MODE_FLAG_NHSYNC) && + (loop->flags & PHSync)) || + ((mode->flags & DRM_MODE_FLAG_PHSYNC) && + (loop->flags & NHSync)))) { + loop++; + continue; + } + if (loop->refresh_rate <= refresh_rate + && (!best || loop->refresh_rate > best->refresh_rate)) + best = loop; + loop++; + } + if (best || !check_sync) + break; + check_sync = 0; + } while (1); + if (best) + vbios_mode->enh_table = best; + + hborder = (vbios_mode->enh_table->flags & HBorder) ? 8 : 0; + vborder = (vbios_mode->enh_table->flags & VBorder) ? 8 : 0; + + adjusted_mode->crtc_htotal = vbios_mode->enh_table->ht; + adjusted_mode->crtc_hblank_start = vbios_mode->enh_table->hde + hborder; + adjusted_mode->crtc_hblank_end = vbios_mode->enh_table->ht - hborder; + adjusted_mode->crtc_hsync_start = vbios_mode->enh_table->hde + hborder + + vbios_mode->enh_table->hfp; + adjusted_mode->crtc_hsync_end = (vbios_mode->enh_table->hde + hborder + + vbios_mode->enh_table->hfp + + vbios_mode->enh_table->hsync); + + adjusted_mode->crtc_vtotal = vbios_mode->enh_table->vt; + adjusted_mode->crtc_vblank_start = vbios_mode->enh_table->vde + vborder; + adjusted_mode->crtc_vblank_end = vbios_mode->enh_table->vt - vborder; + adjusted_mode->crtc_vsync_start = vbios_mode->enh_table->vde + vborder + + vbios_mode->enh_table->vfp; + adjusted_mode->crtc_vsync_end = (vbios_mode->enh_table->vde + vborder + + vbios_mode->enh_table->vfp + + vbios_mode->enh_table->vsync); + + refresh_rate_index = vbios_mode->enh_table->refresh_rate_index; + mode_id = vbios_mode->enh_table->mode_id; + + if (ast->chip == AST1180) { + /* TODO 1180 */ + } else { + ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0x8c, (u8)((color_index & 0xf) << 4)); + ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0x8d, refresh_rate_index & 0xff); + ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0x8e, mode_id & 0xff); + + ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0x91, 0x00); + if (vbios_mode->enh_table->flags & NewModeInfo) { + ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0x91, 0xa8); + ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0x92, + fb->format->cpp[0] * 8); + ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0x93, + adjusted_mode->clock / 1000); + ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0x94, + adjusted_mode->crtc_hdisplay); + ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0x95, + adjusted_mode->crtc_hdisplay >> 8); + + ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0x96, + adjusted_mode->crtc_vdisplay); + ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0x97, + adjusted_mode->crtc_vdisplay >> 8); + } + } + + return true; +} + +static void ast_set_std_reg(struct drm_crtc *crtc, struct drm_display_mode *mode, + struct ast_vbios_mode_info *vbios_mode) +{ + struct ast_private *ast = crtc->dev->dev_private; + const struct drm_framebuffer *fb = crtc->primary->fb; + const struct ast_vbios_stdtable *stdtable; + u32 i; + u8 jreg; + + switch (fb->format->cpp[0] * 8) { + case 8: + stdtable = &vbios_stdtable[VGAModeIndex]; + break; + case 16: + stdtable = &vbios_stdtable[HiCModeIndex]; + break; + case 24: + case 32: + stdtable = &vbios_stdtable[TrueCModeIndex]; + break; + default: + return; + } + + jreg = stdtable->misc; + ast_io_write8(ast, AST_IO_MISC_PORT_WRITE, jreg); + + /* Set SEQ */ + ast_set_index_reg(ast, AST_IO_SEQ_PORT, 0x00, 0x03); + for (i = 0; i < 4; i++) { + jreg = stdtable->seq[i]; + if (!i) + jreg |= 0x20; + ast_set_index_reg(ast, AST_IO_SEQ_PORT, (i + 1), jreg); + } + + /* Set CRTC */ + ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x11, 0x7f, 0x00); + for (i = 0; i < 25; i++) + ast_set_index_reg(ast, AST_IO_CRTC_PORT, i, stdtable->crtc[i]); + + /* set AR */ + jreg = ast_io_read8(ast, AST_IO_INPUT_STATUS1_READ); + for (i = 0; i < 20; i++) { + jreg = stdtable->ar[i]; + ast_io_write8(ast, AST_IO_AR_PORT_WRITE, (u8)i); + ast_io_write8(ast, AST_IO_AR_PORT_WRITE, jreg); + } + ast_io_write8(ast, AST_IO_AR_PORT_WRITE, 0x14); + ast_io_write8(ast, AST_IO_AR_PORT_WRITE, 0x00); + + jreg = ast_io_read8(ast, AST_IO_INPUT_STATUS1_READ); + ast_io_write8(ast, AST_IO_AR_PORT_WRITE, 0x20); + + /* Set GR */ + for (i = 0; i < 9; i++) + ast_set_index_reg(ast, AST_IO_GR_PORT, i, stdtable->gr[i]); +} + +static void ast_set_crtc_reg(struct drm_crtc *crtc, struct drm_display_mode *mode, + struct ast_vbios_mode_info *vbios_mode) +{ + struct ast_private *ast = crtc->dev->dev_private; + u8 jreg05 = 0, jreg07 = 0, jreg09 = 0, jregAC = 0, jregAD = 0, jregAE = 0; + u16 temp, precache = 0; + + if ((ast->chip == AST2500) && + (vbios_mode->enh_table->flags & AST2500PreCatchCRT)) + precache = 40; + + ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x11, 0x7f, 0x00); + + temp = (mode->crtc_htotal >> 3) - 5; + if (temp & 0x100) + jregAC |= 0x01; /* HT D[8] */ + ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x00, 0x00, temp); + + temp = (mode->crtc_hdisplay >> 3) - 1; + if (temp & 0x100) + jregAC |= 0x04; /* HDE D[8] */ + ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x01, 0x00, temp); + + temp = (mode->crtc_hblank_start >> 3) - 1; + if (temp & 0x100) + jregAC |= 0x10; /* HBS D[8] */ + ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x02, 0x00, temp); + + temp = ((mode->crtc_hblank_end >> 3) - 1) & 0x7f; + if (temp & 0x20) + jreg05 |= 0x80; /* HBE D[5] */ + if (temp & 0x40) + jregAD |= 0x01; /* HBE D[5] */ + ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x03, 0xE0, (temp & 0x1f)); + + temp = ((mode->crtc_hsync_start-precache) >> 3) - 1; + if (temp & 0x100) + jregAC |= 0x40; /* HRS D[5] */ + ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x04, 0x00, temp); + + temp = (((mode->crtc_hsync_end-precache) >> 3) - 1) & 0x3f; + if (temp & 0x20) + jregAD |= 0x04; /* HRE D[5] */ + ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x05, 0x60, (u8)((temp & 0x1f) | jreg05)); + + ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xAC, 0x00, jregAC); + ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xAD, 0x00, jregAD); + + /* vert timings */ + temp = (mode->crtc_vtotal) - 2; + if (temp & 0x100) + jreg07 |= 0x01; + if (temp & 0x200) + jreg07 |= 0x20; + if (temp & 0x400) + jregAE |= 0x01; + ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x06, 0x00, temp); + + temp = (mode->crtc_vsync_start) - 1; + if (temp & 0x100) + jreg07 |= 0x04; + if (temp & 0x200) + jreg07 |= 0x80; + if (temp & 0x400) + jregAE |= 0x08; + ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x10, 0x00, temp); + + temp = (mode->crtc_vsync_end - 1) & 0x3f; + if (temp & 0x10) + jregAE |= 0x20; + if (temp & 0x20) + jregAE |= 0x40; + ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x11, 0x70, temp & 0xf); + + temp = mode->crtc_vdisplay - 1; + if (temp & 0x100) + jreg07 |= 0x02; + if (temp & 0x200) + jreg07 |= 0x40; + if (temp & 0x400) + jregAE |= 0x02; + ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x12, 0x00, temp); + + temp = mode->crtc_vblank_start - 1; + if (temp & 0x100) + jreg07 |= 0x08; + if (temp & 0x200) + jreg09 |= 0x20; + if (temp & 0x400) + jregAE |= 0x04; + ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x15, 0x00, temp); + + temp = mode->crtc_vblank_end - 1; + if (temp & 0x100) + jregAE |= 0x10; + ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x16, 0x00, temp); + + ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x07, 0x00, jreg07); + ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x09, 0xdf, jreg09); + ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xAE, 0x00, (jregAE | 0x80)); + + if (precache) + ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xb6, 0x3f, 0x80); + else + ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xb6, 0x3f, 0x00); + + ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x11, 0x7f, 0x80); +} + +void ast_set_offset_reg(struct drm_crtc *crtc) +{ + struct ast_private *ast = crtc->dev->dev_private; + const struct drm_framebuffer *fb = crtc->primary->fb; + + u16 offset; + + offset = fb->pitches[0] >> 3; + ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0x13, (offset & 0xff)); + ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xb0, (offset >> 8) & 0x3f); +} + +static void ast_set_dclk_reg(struct drm_device *dev, struct drm_display_mode *mode, + struct ast_vbios_mode_info *vbios_mode) +{ + struct ast_private *ast = dev->dev_private; + const struct ast_vbios_dclk_info *clk_info; + + if (ast->chip == AST2500) + clk_info = &dclk_table_ast2500[vbios_mode->enh_table->dclk_index]; + else + clk_info = &dclk_table[vbios_mode->enh_table->dclk_index]; + + ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xc0, 0x00, clk_info->param1); + ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xc1, 0x00, clk_info->param2); + ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xbb, 0x0f, + (clk_info->param3 & 0xc0) | + ((clk_info->param3 & 0x3) << 4)); +} + +static void ast_set_ext_reg(struct drm_crtc *crtc, struct drm_display_mode *mode, + struct ast_vbios_mode_info *vbios_mode) +{ + struct ast_private *ast = crtc->dev->dev_private; + const struct drm_framebuffer *fb = crtc->primary->fb; + u8 jregA0 = 0, jregA3 = 0, jregA8 = 0; + + switch (fb->format->cpp[0] * 8) { + case 8: + jregA0 = 0x70; + jregA3 = 0x01; + jregA8 = 0x00; + break; + case 15: + case 16: + jregA0 = 0x70; + jregA3 = 0x04; + jregA8 = 0x02; + break; + case 24: + case 32: + jregA0 = 0x70; + jregA3 = 0x08; + jregA8 = 0x02; + break; + } + + ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xa0, 0x8f, jregA0); + ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xa3, 0xf0, jregA3); + ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xa8, 0xfd, jregA8); + + /* Set Threshold */ + if (ast->chip == AST2300 || ast->chip == AST2400 || + ast->chip == AST2500) { + ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xa7, 0x78); + ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xa6, 0x60); + } else if (ast->chip == AST2100 || + ast->chip == AST1100 || + ast->chip == AST2200 || + ast->chip == AST2150) { + ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xa7, 0x3f); + ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xa6, 0x2f); + } else { + ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xa7, 0x2f); + ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xa6, 0x1f); + } +} + +static void ast_set_sync_reg(struct drm_device *dev, struct drm_display_mode *mode, + struct ast_vbios_mode_info *vbios_mode) +{ + struct ast_private *ast = dev->dev_private; + u8 jreg; + + jreg = ast_io_read8(ast, AST_IO_MISC_PORT_READ); + jreg &= ~0xC0; + if (vbios_mode->enh_table->flags & NVSync) + jreg |= 0x80; + if (vbios_mode->enh_table->flags & NHSync) + jreg |= 0x40; + ast_io_write8(ast, AST_IO_MISC_PORT_WRITE, jreg); +} + +void ast_set_start_address_crt1(struct ast_private *ast, u32 offset) +{ + u32 addr; + + addr = offset >> 2; + ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0x0d, (u8)(addr & 0xff)); + ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0x0c, (u8)((addr >> 8) & 0xff)); + ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xaf, (u8)((addr >> 16) & 0xff)); +} + +void ast_hide_cursor(struct drm_crtc *crtc) +{ + struct ast_private *ast = crtc->dev->dev_private; + ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xcb, 0xfc, 0x00); +} + +int ast_crtc_mode_set(struct drm_crtc *crtc, + struct drm_display_mode *mode, + struct drm_display_mode *adjusted_mode) +{ + struct drm_device *dev = crtc->dev; + struct ast_private *ast = crtc->dev->dev_private; + struct ast_vbios_mode_info vbios_mode; + bool ret; + int err; + + if (ast->chip == AST1180) { + dev_err(dev->pdev, "AST 1180 modesetting not supported\n"); + return -EINVAL; + } + + /* DPMS, set on */ + ast_set_index_reg_mask(ast, AST_IO_SEQ_PORT, 0x1, 0xdf, 0); + if (ast->tx_chip_type == AST_TX_DP501) + ast_set_dp501_video_output(crtc->dev, 1); + ast_crtc_load_lut(crtc); + + /* Get mode */ + ret = ast_get_vbios_mode_info(crtc, mode, adjusted_mode, &vbios_mode); + if (ret == false) { + dev_err(dev->pdev, "Failed to find compatible vbios mode\n"); + return -EINVAL; + } + ast_open_key(ast); + + ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xa1, 0xff, 0x04); + + ast_set_std_reg(crtc, adjusted_mode, &vbios_mode); + ast_set_crtc_reg(crtc, adjusted_mode, &vbios_mode); + ast_set_offset_reg(crtc); + ast_set_dclk_reg(dev, adjusted_mode, &vbios_mode); + ast_set_ext_reg(crtc, adjusted_mode, &vbios_mode); + ast_set_sync_reg(dev, adjusted_mode, &vbios_mode); + + err = ast_crtc_do_set_base(crtc); + if (err) + return err; + + /* Commit changes */ + + ast_set_index_reg_mask(ast, AST_IO_SEQ_PORT, 0x1, 0xdf, 0); + ast_crtc_load_lut(crtc); + + return 0; +} + +enum drm_mode_status ast_mode_valid(struct drm_connector *connector, + const unsigned int hdisplay, const unsigned int vdisplay) +{ + struct ast_private *ast = connector->dev->dev_private; + int flags = MODE_NOMODE; + uint32_t jtemp; + + if (ast->support_wide_screen) { + if ((hdisplay == 1680) && (vdisplay == 1050)) + return MODE_OK; + if ((hdisplay == 1280) && (vdisplay == 800)) + return MODE_OK; + if ((hdisplay == 1440) && (vdisplay == 900)) + return MODE_OK; + if ((hdisplay == 1360) && (vdisplay == 768)) + return MODE_OK; + if ((hdisplay == 1600) && (vdisplay == 900)) + return MODE_OK; + + if ((ast->chip == AST2100) || (ast->chip == AST2200) || + (ast->chip == AST2300) || (ast->chip == AST2400) || + (ast->chip == AST2500) || (ast->chip == AST1180)) { + if ((hdisplay == 1920) && (vdisplay == 1080)) + return MODE_OK; + + if ((hdisplay == 1920) && (vdisplay == 1200)) { + jtemp = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xd1, + 0xff); + if (jtemp & 0x01) + return MODE_NOMODE; + else + return MODE_OK; + } + } + } + switch (hdisplay) { + case 640: + if (vdisplay == 480) + flags = MODE_OK; + break; + case 800: + if (vdisplay == 600) + flags = MODE_OK; + break; + case 1024: + if (vdisplay == 768) + flags = MODE_OK; + break; + case 1280: + if (vdisplay == 1024) + flags = MODE_OK; + break; + case 1600: + if (vdisplay == 1200) + flags = MODE_OK; + break; + default: + return flags; + } + + return flags; +} diff --git a/src/drivers/aspeed/common/ast_mode_corebootfb.c b/src/drivers/aspeed/common/ast_mode_corebootfb.c new file mode 100644 index 0000000000..2ec85ac31f --- /dev/null +++ b/src/drivers/aspeed/common/ast_mode_corebootfb.c @@ -0,0 +1,256 @@ +/* + * Copied from Linux drivers/gpu/drm/ast/ast_mode.c + * + * Copyright 2012 Red Hat Inc. + * Parts based on xf86-video-ast + * Copyright (c) 2005 ASPEED Technology Inc. + * Copyright Dave Airlie + * Copyright 2019 9Elements Agency GmbH + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the + * "Software"), to deal in the Software without restriction, including + * without limitation the rights to use, copy, modify, merge, publish, + * distribute, sub license, and/or sell copies of the Software, and to + * permit persons to whom the Software is furnished to do so, subject to + * the following conditions: + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, + * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR + * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE + * USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * The above copyright notice and this permission notice (including the + * next paragraph) shall be included in all copies or substantial portions + * of the Software. + * + */ + +#include + +#include "ast_drv.h" + +/* + * Set framebuffer MMIO address, which must fall into BAR0 MMIO window. + * + * Complete reimplementation as the original expects multiple kernel internal + * subsystems to be present. + */ +int ast_crtc_do_set_base(struct drm_crtc *crtc) +{ + struct ast_private *ast = crtc->dev->dev_private; + struct drm_framebuffer *fb = crtc->primary->fb; + + /* PCI BAR 0 */ + struct resource *res = find_resource(crtc->dev->pdev, 0x10); + if (!res) { + printk(BIOS_ERR, "BAR0 resource not found.\n"); + return -EIO; + } + + if (res->size < fb->pitches[0] * crtc->mode.vdisplay) { + dev_err(dev->pdev, "Framebuffer doesn't fit into BAR0 MMIO window\n"); + return -ENOMEM; + } + + fb->mmio_addr = (u32)res2mmio(res, 4095, 4095); + + ast_set_offset_reg(crtc); + ast_set_start_address_crt1(ast, fb->mmio_addr); + + return 0; +} + +static void ast_edid_to_drmmode(struct edid *edid, struct drm_display_mode *mode) +{ + memset(mode, 0, sizeof(*mode)); + + mode->hdisplay = edid->mode.ha; + mode->vdisplay = edid->mode.va; + mode->crtc_hdisplay = edid->mode.ha; + mode->crtc_vdisplay = edid->mode.va; + + /* EDID clock is in 10kHz, but drm clock is in KHz */ + mode->clock = edid->mode.pixel_clock * 10; + mode->vrefresh = edid->mode.refresh; + + mode->crtc_hblank_start = edid->mode.ha; + mode->crtc_hblank_end = edid->mode.ha + edid->mode.hbl; + mode->crtc_hsync_start = edid->mode.ha + edid->mode.hso; + mode->crtc_hsync_end = edid->mode.ha + edid->mode.hso + edid->mode.hspw; + mode->crtc_htotal = mode->crtc_hblank_end; + + mode->crtc_vblank_start = edid->mode.va; + mode->crtc_vblank_end = edid->mode.va + edid->mode.vbl; + mode->crtc_vsync_start = edid->mode.va + edid->mode.vso; + mode->crtc_vsync_end = edid->mode.va + edid->mode.vso + edid->mode.vspw; + mode->crtc_vtotal = mode->crtc_vblank_end; + + mode->flags = 0; + if (edid->mode.phsync == '+') + mode->flags |= DRM_MODE_FLAG_PHSYNC; + else + mode->flags |= DRM_MODE_FLAG_NHSYNC; + + if (edid->mode.pvsync == '+') + mode->flags |= DRM_MODE_FLAG_PVSYNC; + else + mode->flags |= DRM_MODE_FLAG_NVSYNC; +} + +static int ast_select_mode(struct drm_connector *connector, + struct edid *edid) +{ + struct ast_private *ast = connector->dev->dev_private; + bool widescreen; + u8 raw[128]; + bool flags = false; + + if (ast->tx_chip_type == AST_TX_DP501) { + ast->dp501_maxclk = 0xff; + flags = ast_dp501_read_edid(connector->dev, (u8 *)raw); + if (flags) + ast->dp501_maxclk = ast_get_dp501_max_clk(connector->dev); + else + dev_err(dev->pdev, "I2C transmission error\n"); + } + + if (!flags) + ast_software_i2c_read(ast, raw); + + if (decode_edid(raw, sizeof(raw), edid) != EDID_CONFORMANT) { + dev_err(dev->pdev, "Failed to decode EDID\n"); + printk(BIOS_DEBUG, "Assuming VGA for KVM\n"); + + memset(edid, 0, sizeof(*edid)); + + edid->mode.pixel_clock = 6411; + edid->mode.refresh = 60; + edid->mode.ha = 1024; + edid->mode.hspw = 4; + edid->mode.hso = 56; + edid->mode.hbl = 264; + edid->mode.phsync = '-'; + + edid->mode.va = 768; + edid->mode.vspw = 3; + edid->mode.vso = 1; + edid->mode.vbl = 26; + edid->mode.pvsync = '+'; + } + + printk(BIOS_DEBUG, "AST: Display has %dpx x %dpx\n", edid->mode.ha, edid->mode.va); + + widescreen = !!(((edid->mode.ha * 4) % (edid->mode.va * 3))); + + while (ast_mode_valid(connector, edid->mode.ha, edid->mode.va) != MODE_OK) { + /* Select a compatible smaller mode */ + if (edid->mode.ha > 1920 && widescreen) { + edid->mode.ha = 1920; + edid->mode.va = 1080; + } else if (edid->mode.ha >= 1920 && widescreen) { + edid->mode.ha = 1680; + edid->mode.va = 1050; + } else if (edid->mode.ha >= 1680 && widescreen) { + edid->mode.ha = 1600; + edid->mode.va = 900; + } else if (edid->mode.ha >= 1680 && !widescreen) { + edid->mode.ha = 1600; + edid->mode.va = 1200; + } else if (edid->mode.ha >= 1600 && widescreen) { + edid->mode.ha = 1440; + edid->mode.va = 900; + } else if (edid->mode.ha >= 1440 && widescreen) { + edid->mode.ha = 1360; + edid->mode.va = 768; + } else if (edid->mode.ha >= 1360 && widescreen) { + edid->mode.ha = 1280; + edid->mode.va = 800; + } else if (edid->mode.ha >= 1360 && !widescreen) { + edid->mode.ha = 1280; + edid->mode.va = 1024; + } else if (edid->mode.ha >= 1280) { + edid->mode.ha = 1024; + edid->mode.va = 768; + } else if (edid->mode.ha >= 1024) { + edid->mode.ha = 800; + edid->mode.va = 600; + } else if (edid->mode.ha >= 800) { + edid->mode.ha = 640; + edid->mode.va = 480; + } else { + dev_err(dev->pdev, "No compatible mode found.\n"); + + return -EIO; + } + }; + + return 0; +} + +int ast_driver_framebuffer_init(struct drm_device *dev, int flags) +{ + struct drm_display_mode adjusted_mode; + struct drm_crtc crtc; + struct drm_format format; + struct drm_primary primary; + struct drm_framebuffer fb; + struct drm_connector connector; + struct edid edid; + int ret; + + /* Init wrapper structs */ + connector.dev = dev; + + format.cpp[0] = 4; /* 32 BPP */ + fb.format = &format; + + primary.fb = &fb; + + crtc.dev = dev; + crtc.primary = &primary; + + /* Read EDID and find mode */ + ret = ast_select_mode(&connector, &edid); + if (ret) { + dev_err(dev->pdev, "Failed to select mode.\n"); + return ret; + } + + /* Updated edid for set_vbe_mode_info_valid */ + edid.x_resolution = edid.mode.ha; + edid.y_resolution = edid.mode.va; + edid.framebuffer_bits_per_pixel = format.cpp[0] * 8; + edid.bytes_per_line = ALIGN_UP(edid.x_resolution * format.cpp[0], 8); + + /* Updated framebuffer info for ast_crtc_mode_set */ + fb.pitches[0] = edid.bytes_per_line; + + printk(BIOS_DEBUG, "Using framebuffer %dpx x %dpx pitch %d @ %d BPP\n", + edid.x_resolution, edid.y_resolution, edid.bytes_per_line, + edid.framebuffer_bits_per_pixel); + + /* Convert EDID to AST DRM mode */ + ast_edid_to_drmmode(&edid, &crtc.mode); + + memcpy(&adjusted_mode, &crtc.mode, sizeof(crtc.mode)); + + ret = ast_crtc_mode_set(&crtc, &crtc.mode, &adjusted_mode); + if (ret) { + dev_err(dev->pdev, "Failed to set mode.\n"); + return ret; + } + + ast_hide_cursor(&crtc); + + /* Advertise new mode */ + set_vbe_mode_info_valid(&edid, fb.mmio_addr); + + /* Clear display */ + memset((void *)fb.mmio_addr, 0, edid.bytes_per_line * edid.y_resolution); + + return 0; +} diff --git a/src/drivers/aspeed/common/ast_tables.h b/src/drivers/aspeed/common/ast_tables.h index ae3c6d078a..27b01725b5 100644 --- a/src/drivers/aspeed/common/ast_tables.h +++ b/src/drivers/aspeed/common/ast_tables.h @@ -49,6 +49,7 @@ #define SyncPN (PVSync | NHSync) #define SyncNP (NVSync | PHSync) #define SyncNN (NVSync | NHSync) +#define AST2500PreCatchCRT 0x00004000 /* DCLK Index */ #define VCLK25_175 0x00 @@ -110,80 +111,110 @@ static struct ast_vbios_dclk_info dclk_table[] = { {0x3b, 0x2c, 0x81}, /* 1A: VCLK118_25 */ }; +static const struct ast_vbios_dclk_info dclk_table_ast2500[] = { + {0x2C, 0xE7, 0x03}, /* 00: VCLK25_175 */ + {0x95, 0x62, 0x03}, /* 01: VCLK28_322 */ + {0x67, 0x63, 0x01}, /* 02: VCLK31_5 */ + {0x76, 0x63, 0x01}, /* 03: VCLK36 */ + {0xEE, 0x67, 0x01}, /* 04: VCLK40 */ + {0x82, 0x62, 0x01}, /* 05: VCLK49_5 */ + {0xC6, 0x64, 0x01}, /* 06: VCLK50 */ + {0x94, 0x62, 0x01}, /* 07: VCLK56_25 */ + {0x80, 0x64, 0x00}, /* 08: VCLK65 */ + {0x7B, 0x63, 0x00}, /* 09: VCLK75 */ + {0x67, 0x62, 0x00}, /* 0A: VCLK78_75 */ + {0x7C, 0x62, 0x00}, /* 0B: VCLK94_5 */ + {0x8E, 0x62, 0x00}, /* 0C: VCLK108 */ + {0x85, 0x24, 0x00}, /* 0D: VCLK135 */ + {0x67, 0x22, 0x00}, /* 0E: VCLK157_5 */ + {0x6A, 0x22, 0x00}, /* 0F: VCLK162 */ + {0x4d, 0x4c, 0x80}, /* 10: VCLK154 */ + {0x68, 0x6f, 0x80}, /* 11: VCLK83.5 */ + {0x28, 0x49, 0x80}, /* 12: VCLK106.5 */ + {0x37, 0x49, 0x80}, /* 13: VCLK146.25 */ + {0x1f, 0x45, 0x80}, /* 14: VCLK148.5 */ + {0x47, 0x6c, 0x80}, /* 15: VCLK71 */ + {0x25, 0x65, 0x80}, /* 16: VCLK88.75 */ + {0x58, 0x01, 0x42}, /* 17: VCLK119 */ + {0x32, 0x67, 0x80}, /* 18: VCLK85_5 */ + {0x6a, 0x6d, 0x80}, /* 19: VCLK97_75 */ + {0x44, 0x20, 0x43}, /* 1A: VCLK118_25 */ +}; + static struct ast_vbios_stdtable vbios_stdtable[] = { /* MD_2_3_400 */ { 0x67, - {0x00,0x03,0x00,0x02}, - {0x5f,0x4f,0x50,0x82,0x55,0x81,0xbf,0x1f, - 0x00,0x4f,0x0d,0x0e,0x00,0x00,0x00,0x00, - 0x9c,0x8e,0x8f,0x28,0x1f,0x96,0xb9,0xa3, - 0xff}, - {0x00,0x01,0x02,0x03,0x04,0x05,0x14,0x07, - 0x38,0x39,0x3a,0x3b,0x3c,0x3d,0x3e,0x3f, - 0x0c,0x00,0x0f,0x08}, - {0x00,0x00,0x00,0x00,0x00,0x10,0x0e,0x00, - 0xff} + {0x00, 0x03, 0x00, 0x02}, + {0x5f, 0x4f, 0x50, 0x82, 0x55, 0x81, 0xbf, 0x1f, + 0x00, 0x4f, 0x0d, 0x0e, 0x00, 0x00, 0x00, 0x00, + 0x9c, 0x8e, 0x8f, 0x28, 0x1f, 0x96, 0xb9, 0xa3, + 0xff}, + {0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x14, 0x07, + 0x38, 0x39, 0x3a, 0x3b, 0x3c, 0x3d, 0x3e, 0x3f, + 0x0c, 0x00, 0x0f, 0x08}, + {0x00, 0x00, 0x00, 0x00, 0x00, 0x10, 0x0e, 0x00, + 0xff} }, /* Mode12/ExtEGATable */ { 0xe3, - {0x01,0x0f,0x00,0x06}, - {0x5f,0x4f,0x50,0x82,0x55,0x81,0x0b,0x3e, - 0x00,0x40,0x00,0x00,0x00,0x00,0x00,0x00, - 0xe9,0x8b,0xdf,0x28,0x00,0xe7,0x04,0xe3, - 0xff}, - {0x00,0x01,0x02,0x03,0x04,0x05,0x14,0x07, - 0x38,0x39,0x3a,0x3b,0x3c,0x3d,0x3e,0x3f, - 0x01,0x00,0x0f,0x00}, - {0x00,0x00,0x00,0x00,0x00,0x00,0x05,0x0f, - 0xff} + {0x01, 0x0f, 0x00, 0x06}, + {0x5f, 0x4f, 0x50, 0x82, 0x55, 0x81, 0x0b, 0x3e, + 0x00, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0xe9, 0x8b, 0xdf, 0x28, 0x00, 0xe7, 0x04, 0xe3, + 0xff}, + {0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x14, 0x07, + 0x38, 0x39, 0x3a, 0x3b, 0x3c, 0x3d, 0x3e, 0x3f, + 0x01, 0x00, 0x0f, 0x00}, + {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x05, 0x0f, + 0xff} }, /* ExtVGATable */ { 0x2f, - {0x01,0x0f,0x00,0x0e}, - {0x5f,0x4f,0x50,0x82,0x54,0x80,0x0b,0x3e, - 0x00,0x40,0x00,0x00,0x00,0x00,0x00,0x00, - 0xea,0x8c,0xdf,0x28,0x40,0xe7,0x04,0xa3, - 0xff}, - {0x00,0x01,0x02,0x03,0x04,0x05,0x06,0x07, - 0x08,0x09,0x0a,0x0b,0x0c,0x0d,0x0e,0x0f, - 0x01,0x00,0x00,0x00}, - {0x00,0x00,0x00,0x00,0x00,0x40,0x05,0x0f, - 0xff} + {0x01, 0x0f, 0x00, 0x0e}, + {0x5f, 0x4f, 0x50, 0x82, 0x54, 0x80, 0x0b, 0x3e, + 0x00, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0xea, 0x8c, 0xdf, 0x28, 0x40, 0xe7, 0x04, 0xa3, + 0xff}, + {0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, + 0x08, 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f, + 0x01, 0x00, 0x00, 0x00}, + {0x00, 0x00, 0x00, 0x00, 0x00, 0x40, 0x05, 0x0f, + 0xff} }, /* ExtHiCTable */ { 0x2f, - {0x01,0x0f,0x00,0x0e}, - {0x5f,0x4f,0x50,0x82,0x54,0x80,0x0b,0x3e, - 0x00,0x40,0x00,0x00,0x00,0x00,0x00,0x00, - 0xea,0x8c,0xdf,0x28,0x40,0xe7,0x04,0xa3, - 0xff}, - {0x00,0x01,0x02,0x03,0x04,0x05,0x06,0x07, - 0x08,0x09,0x0a,0x0b,0x0c,0x0d,0x0e,0x0f, - 0x01,0x00,0x00,0x00}, - {0x00,0x00,0x00,0x00,0x00,0x00,0x05,0x0f, - 0xff} + {0x01, 0x0f, 0x00, 0x0e}, + {0x5f, 0x4f, 0x50, 0x82, 0x54, 0x80, 0x0b, 0x3e, + 0x00, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0xea, 0x8c, 0xdf, 0x28, 0x40, 0xe7, 0x04, 0xa3, + 0xff}, + {0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, + 0x08, 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f, + 0x01, 0x00, 0x00, 0x00}, + {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x05, 0x0f, + 0xff} }, /* ExtTrueCTable */ { 0x2f, - {0x01,0x0f,0x00,0x0e}, - {0x5f,0x4f,0x50,0x82,0x54,0x80,0x0b,0x3e, - 0x00,0x40,0x00,0x00,0x00,0x00,0x00,0x00, - 0xea,0x8c,0xdf,0x28,0x40,0xe7,0x04,0xa3, + {0x01, 0x0f, 0x00, 0x0e}, + {0x5f, 0x4f, 0x50, 0x82, 0x54, 0x80, 0x0b, 0x3e, + 0x00, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0xea, 0x8c, 0xdf, 0x28, 0x40, 0xe7, 0x04, 0xa3, 0xff}, - {0x00,0x01,0x02,0x03,0x04,0x05,0x06,0x07, - 0x08,0x09,0x0a,0x0b,0x0c,0x0d,0x0e,0x0f, - 0x01,0x00,0x00,0x00}, - {0x00,0x00,0x00,0x00,0x00,0x00,0x05,0x0f, + {0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, + 0x08, 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f, + 0x01, 0x00, 0x00, 0x00}, + {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x05, 0x0f, 0xff} }, }; -static struct ast_vbios_enhtable res_640x480[] = { +static const struct ast_vbios_enhtable res_640x480[] = { { 800, 640, 8, 96, 525, 480, 2, 2, VCLK25_175, /* 60Hz */ (SyncNN | HBorder | VBorder | Charx8Dot), 60, 1, 0x2E }, { 832, 640, 16, 40, 520, 480, 1, 3, VCLK31_5, /* 72Hz */ @@ -196,7 +227,7 @@ static struct ast_vbios_enhtable res_640x480[] = { (SyncNN | Charx8Dot) , 0xFF, 4, 0x2E }, }; -static struct ast_vbios_enhtable res_800x600[] = { +static const struct ast_vbios_enhtable res_800x600[] = { {1024, 800, 24, 72, 625, 600, 1, 2, VCLK36, /* 56Hz */ (SyncPP | Charx8Dot), 56, 1, 0x30 }, {1056, 800, 40, 128, 628, 600, 1, 4, VCLK40, /* 60Hz */ @@ -212,7 +243,7 @@ static struct ast_vbios_enhtable res_800x600[] = { }; -static struct ast_vbios_enhtable res_1024x768[] = { +static const struct ast_vbios_enhtable res_1024x768[] = { {1344, 1024, 24, 136, 806, 768, 3, 6, VCLK65, /* 60Hz */ (SyncNN | Charx8Dot), 60, 1, 0x31 }, {1328, 1024, 24, 136, 806, 768, 3, 6, VCLK75, /* 70Hz */ @@ -225,7 +256,7 @@ static struct ast_vbios_enhtable res_1024x768[] = { (SyncPP | Charx8Dot), 0xFF, 4, 0x31 }, }; -static struct ast_vbios_enhtable res_1280x1024[] = { +static const struct ast_vbios_enhtable res_1280x1024[] = { {1688, 1280, 48, 112, 1066, 1024, 1, 3, VCLK108, /* 60Hz */ (SyncPP | Charx8Dot), 60, 1, 0x32 }, {1688, 1280, 16, 144, 1066, 1024, 1, 3, VCLK135, /* 75Hz */ @@ -236,7 +267,7 @@ static struct ast_vbios_enhtable res_1280x1024[] = { (SyncPP | Charx8Dot), 0xFF, 3, 0x32 }, }; -static struct ast_vbios_enhtable res_1600x1200[] = { +static const struct ast_vbios_enhtable res_1600x1200[] = { {2160, 1600, 64, 192, 1250, 1200, 1, 3, VCLK162, /* 60Hz */ (SyncPP | Charx8Dot), 60, 1, 0x33 }, {2160, 1600, 64, 192, 1250, 1200, 1, 3, VCLK162, /* end */ @@ -244,34 +275,39 @@ static struct ast_vbios_enhtable res_1600x1200[] = { }; /* 16:9 */ -static struct ast_vbios_enhtable res_1360x768[] = { - {1792, 1360, 64,112, 795, 768, 3, 6, VCLK85_5, /* 60Hz */ +static const struct ast_vbios_enhtable res_1360x768[] = { + {1792, 1360, 64, 112, 795, 768, 3, 6, VCLK85_5, /* 60Hz */ (SyncPP | Charx8Dot | LineCompareOff | WideScreenMode | NewModeInfo), 60, 1, 0x39 }, - {1792, 1360, 64,112, 795, 768, 3, 6, VCLK85_5, /* end */ - (SyncPP | Charx8Dot | LineCompareOff | WideScreenMode | NewModeInfo), 0xFF, 1, 0x39 }, + {1792, 1360, 64, 112, 795, 768, 3, 6, VCLK85_5, /* end */ + (SyncPP | Charx8Dot | LineCompareOff | WideScreenMode | NewModeInfo | + AST2500PreCatchCRT), 0xFF, 1, 0x39 }, }; -static struct ast_vbios_enhtable res_1600x900[] = { - {1760, 1600, 48, 32, 926, 900, 3, 5, VCLK97_75, /* 60Hz CVT RB */ - (SyncNP | Charx8Dot | LineCompareOff | WideScreenMode | NewModeInfo), 60, 1, 0x3A }, - {2112, 1600, 88,168, 934, 900, 3, 5, VCLK118_25, /* 60Hz CVT */ +static const struct ast_vbios_enhtable res_1600x900[] = { + {1760, 1600, 48, 32, 926, 900, 3, 5, VCLK97_75, /* 60Hz CVT RB */ + (SyncNP | Charx8Dot | LineCompareOff | WideScreenMode | NewModeInfo | + AST2500PreCatchCRT), 60, 1, 0x3A }, + {2112, 1600, 88, 168, 934, 900, 3, 5, VCLK118_25, /* 60Hz CVT */ (SyncPN | Charx8Dot | LineCompareOff | WideScreenMode | NewModeInfo), 60, 2, 0x3A }, - {2112, 1600, 88,168, 934, 900, 3, 5, VCLK118_25, /* 60Hz CVT */ + {2112, 1600, 88, 168, 934, 900, 3, 5, VCLK118_25, /* 60Hz CVT */ (SyncPN | Charx8Dot | LineCompareOff | WideScreenMode | NewModeInfo), 0xFF, 2, 0x3A }, }; -static struct ast_vbios_enhtable res_1920x1080[] = { +static const struct ast_vbios_enhtable res_1920x1080[] = { {2200, 1920, 88, 44, 1125, 1080, 4, 5, VCLK148_5, /* 60Hz */ - (SyncNP | Charx8Dot | LineCompareOff | WideScreenMode | NewModeInfo), 60, 1, 0x38 }, + (SyncNP | Charx8Dot | LineCompareOff | WideScreenMode | NewModeInfo | + AST2500PreCatchCRT), 60, 1, 0x38 }, {2200, 1920, 88, 44, 1125, 1080, 4, 5, VCLK148_5, /* 60Hz */ - (SyncNP | Charx8Dot | LineCompareOff | WideScreenMode | NewModeInfo), 0xFF, 1, 0x38 }, + (SyncNP | Charx8Dot | LineCompareOff | WideScreenMode | NewModeInfo | + AST2500PreCatchCRT), 0xFF, 1, 0x38 }, }; /* 16:10 */ -static struct ast_vbios_enhtable res_1280x800[] = { +static const struct ast_vbios_enhtable res_1280x800[] = { {1440, 1280, 48, 32, 823, 800, 3, 6, VCLK71, /* 60Hz RB */ - (SyncNP | Charx8Dot | LineCompareOff | WideScreenMode | NewModeInfo), 60, 1, 0x35 }, + (SyncNP | Charx8Dot | LineCompareOff | WideScreenMode | NewModeInfo | + AST2500PreCatchCRT), 60, 1, 0x35 }, {1680, 1280, 72,128, 831, 800, 3, 6, VCLK83_5, /* 60Hz */ (SyncPN | Charx8Dot | LineCompareOff | WideScreenMode | NewModeInfo), 60, 2, 0x35 }, {1680, 1280, 72,128, 831, 800, 3, 6, VCLK83_5, /* 60Hz */ @@ -279,29 +315,32 @@ static struct ast_vbios_enhtable res_1280x800[] = { }; -static struct ast_vbios_enhtable res_1440x900[] = { +static const struct ast_vbios_enhtable res_1440x900[] = { {1600, 1440, 48, 32, 926, 900, 3, 6, VCLK88_75, /* 60Hz RB */ - (SyncNP | Charx8Dot | LineCompareOff | WideScreenMode | NewModeInfo), 60, 1, 0x36 }, + (SyncNP | Charx8Dot | LineCompareOff | WideScreenMode | NewModeInfo | + AST2500PreCatchCRT), 60, 1, 0x36 }, {1904, 1440, 80,152, 934, 900, 3, 6, VCLK106_5, /* 60Hz */ (SyncPN | Charx8Dot | LineCompareOff | WideScreenMode | NewModeInfo), 60, 2, 0x36 }, {1904, 1440, 80,152, 934, 900, 3, 6, VCLK106_5, /* 60Hz */ (SyncPN | Charx8Dot | LineCompareOff | WideScreenMode | NewModeInfo), 0xFF, 2, 0x36 }, }; -static struct ast_vbios_enhtable res_1680x1050[] = { +static const struct ast_vbios_enhtable res_1680x1050[] = { {1840, 1680, 48, 32, 1080, 1050, 3, 6, VCLK119, /* 60Hz RB */ - (SyncNP | Charx8Dot | LineCompareOff | WideScreenMode | NewModeInfo), 60, 1, 0x37 }, + (SyncNP | Charx8Dot | LineCompareOff | WideScreenMode | NewModeInfo | + AST2500PreCatchCRT), 60, 1, 0x37 }, {2240, 1680,104,176, 1089, 1050, 3, 6, VCLK146_25, /* 60Hz */ (SyncPN | Charx8Dot | LineCompareOff | WideScreenMode | NewModeInfo), 60, 2, 0x37 }, {2240, 1680,104,176, 1089, 1050, 3, 6, VCLK146_25, /* 60Hz */ (SyncPN | Charx8Dot | LineCompareOff | WideScreenMode | NewModeInfo), 0xFF, 2, 0x37 }, }; -static struct ast_vbios_enhtable res_1920x1200[] = { +static const struct ast_vbios_enhtable res_1920x1200[] = { {2080, 1920, 48, 32, 1235, 1200, 3, 6, VCLK154, /* 60Hz RB*/ - (SyncNP | Charx8Dot | LineCompareOff | WideScreenMode | NewModeInfo), 60, 1, 0x34 }, - {2080, 1920, 48, 32, 1235, 1200, 3, 6, VCLK154, /* 60Hz RB */ - (SyncNP | Charx8Dot | LineCompareOff | WideScreenMode | NewModeInfo), 0xFF, 1, 0x34 }, + (SyncNP | Charx8Dot | LineCompareOff | WideScreenMode | NewModeInfo | + AST2500PreCatchCRT), 60, 1, 0x34 }, + {2080, 1920, 48, 32, 1235, 1200, 3, 6, VCLK154, /* 60Hz RB */ + (SyncNP | Charx8Dot | LineCompareOff | WideScreenMode | NewModeInfo | + AST2500PreCatchCRT), 0xFF, 1, 0x34 }, }; - #endif From 9fe3d692c741a873317d0b1738b12145ff9c800e Mon Sep 17 00:00:00 2001 From: Patrick Rudolph Date: Mon, 5 Aug 2019 10:43:09 +0200 Subject: [PATCH 0647/1242] drivers/aspeed: Add AST2500 support Tested on AST2500. Code for AST2400 still works. Copy code from GNU/Linux kernel to coreboot to add AST2500 support. Change-Id: I25bd34dd52a0acd3e04fc5818e011215ef907fad Signed-off-by: Patrick Rudolph Reviewed-on: https://review.coreboot.org/c/coreboot/+/34793 Tested-by: build bot (Jenkins) Reviewed-by: Philipp Deppenwiese --- src/drivers/aspeed/common/ast_dp501.c | 13 +- src/drivers/aspeed/common/ast_dram_tables.h | 62 +++ src/drivers/aspeed/common/ast_drv.h | 4 +- src/drivers/aspeed/common/ast_main.c | 26 +- src/drivers/aspeed/common/ast_post.c | 532 +++++++++++++++++--- 5 files changed, 553 insertions(+), 84 deletions(-) diff --git a/src/drivers/aspeed/common/ast_dp501.c b/src/drivers/aspeed/common/ast_dp501.c index 99b087550f..2954744557 100644 --- a/src/drivers/aspeed/common/ast_dp501.c +++ b/src/drivers/aspeed/common/ast_dp501.c @@ -147,7 +147,7 @@ bool ast_backup_fw(struct drm_device *dev, u8 *addr, u32 size) return false; } -bool ast_launch_m68k(struct drm_device *dev) +static bool ast_launch_m68k(struct drm_device *dev) { struct ast_private *ast = dev->dev_private; u32 i, data, len = 0; @@ -161,7 +161,10 @@ bool ast_launch_m68k(struct drm_device *dev) if (ast->dp501_fw_addr) { fw_addr = ast->dp501_fw_addr; len = 32*1024; - } else if (ast->dp501_fw) { + } else { + if (!ast->dp501_fw) + return false; + fw_addr = (u8 *)ast->dp501_fw->data; len = ast->dp501_fw->size; } @@ -226,11 +229,7 @@ u8 ast_get_dp501_max_clk(struct drm_device *dev) /* Read Link Capability */ offset = 0xf014; - data = ast_mindwm(ast, boot_address + offset); - linkcap[0] = (data & 0xff000000) >> 24; - linkcap[1] = (data & 0x00ff0000) >> 16; - linkcap[2] = (data & 0x0000ff00) >> 8; - linkcap[3] = (data & 0x000000ff); + *(u32 *)linkcap = ast_mindwm(ast, boot_address + offset); if (linkcap[2] == 0) { linkrate = linkcap[0]; linklanes = linkcap[1]; diff --git a/src/drivers/aspeed/common/ast_dram_tables.h b/src/drivers/aspeed/common/ast_dram_tables.h index 39495d3d18..69894fcb17 100644 --- a/src/drivers/aspeed/common/ast_dram_tables.h +++ b/src/drivers/aspeed/common/ast_dram_tables.h @@ -159,4 +159,66 @@ static const struct ast_dramstruct ast2100_dram_table_data[] = { { 0xffff, 0xffffffff }, }; +/* + * AST2500 DRAM settings modules + */ +#define REGTBL_NUM 17 +#define REGIDX_010 0 +#define REGIDX_014 1 +#define REGIDX_018 2 +#define REGIDX_020 3 +#define REGIDX_024 4 +#define REGIDX_02C 5 +#define REGIDX_030 6 +#define REGIDX_214 7 +#define REGIDX_2E0 8 +#define REGIDX_2E4 9 +#define REGIDX_2E8 10 +#define REGIDX_2EC 11 +#define REGIDX_2F0 12 +#define REGIDX_2F4 13 +#define REGIDX_2F8 14 +#define REGIDX_RFC 15 +#define REGIDX_PLL 16 + +static const u32 ast2500_ddr3_1600_timing_table[REGTBL_NUM] = { + 0x64604D38, /* 0x010 */ + 0x29690599, /* 0x014 */ + 0x00000300, /* 0x018 */ + 0x00000000, /* 0x020 */ + 0x00000000, /* 0x024 */ + 0x02181E70, /* 0x02C */ + 0x00000040, /* 0x030 */ + 0x00000024, /* 0x214 */ + 0x02001300, /* 0x2E0 */ + 0x0E0000A0, /* 0x2E4 */ + 0x000E001B, /* 0x2E8 */ + 0x35B8C105, /* 0x2EC */ + 0x08090408, /* 0x2F0 */ + 0x9B000800, /* 0x2F4 */ + 0x0E400A00, /* 0x2F8 */ + 0x9971452F, /* tRFC */ + 0x000071C1 /* PLL */ + }; + + static const u32 ast2500_ddr4_1600_timing_table[REGTBL_NUM] = { + 0x63604E37, /* 0x010 */ + 0xE97AFA99, /* 0x014 */ + 0x00019000, /* 0x018 */ + 0x08000000, /* 0x020 */ + 0x00000400, /* 0x024 */ + 0x00000410, /* 0x02C */ + 0x00000101, /* 0x030 */ + 0x00000024, /* 0x214 */ + 0x03002900, /* 0x2E0 */ + 0x0E0000A0, /* 0x2E4 */ + 0x000E001C, /* 0x2E8 */ + 0x35B8C106, /* 0x2EC */ + 0x08080607, /* 0x2F0 */ + 0x9B000900, /* 0x2F4 */ + 0x0E400A00, /* 0x2F8 */ + 0x99714545, /* tRFC */ + 0x000071C1 /* PLL */ + }; + #endif diff --git a/src/drivers/aspeed/common/ast_drv.h b/src/drivers/aspeed/common/ast_drv.h index 39f49433da..1c44026a43 100644 --- a/src/drivers/aspeed/common/ast_drv.h +++ b/src/drivers/aspeed/common/ast_drv.h @@ -63,6 +63,7 @@ enum ast_tx_chip { #define AST_DRAM_1Gx32 3 #define AST_DRAM_2Gx16 6 #define AST_DRAM_4Gx16 7 +#define AST_DRAM_8Gx16 8 struct ast_fbdev; @@ -311,13 +312,12 @@ void ast_post_gpu(struct drm_device *dev); u32 ast_mindwm(struct ast_private *ast, u32 r); void ast_moutdwm(struct ast_private *ast, u32 r, u32 v); /* ast dp501 */ -int ast_load_dp501_microcode(struct drm_device *dev); void ast_set_dp501_video_output(struct drm_device *dev, u8 mode); -bool ast_launch_m68k(struct drm_device *dev); bool ast_backup_fw(struct drm_device *dev, u8 *addr, u32 size); bool ast_dp501_read_edid(struct drm_device *dev, u8 *ediddata); u8 ast_get_dp501_max_clk(struct drm_device *dev); void ast_init_3rdtx(struct drm_device *dev); +void ast_release_firmware(struct drm_device *dev); /* ast mode */ int ast_crtc_mode_set(struct drm_crtc *crtc, diff --git a/src/drivers/aspeed/common/ast_main.c b/src/drivers/aspeed/common/ast_main.c index f9fb5e2361..0a26a9c922 100644 --- a/src/drivers/aspeed/common/ast_main.c +++ b/src/drivers/aspeed/common/ast_main.c @@ -75,8 +75,10 @@ static int ast_detect_chip(struct drm_device *dev, bool *need_post) } else { pci_read_config_dword(ast->dev->pdev, 0x08, &data); uint8_t revision = data & 0xff; - - if (revision >= 0x30) { + if (revision >= 0x40) { + ast->chip = AST2500; + DRM_INFO("AST 2500 detected\n"); + } else if (revision >= 0x30) { ast->chip = AST2400; DRM_INFO("AST 2400 detected\n"); } else if (revision >= 0x20) { @@ -151,6 +153,8 @@ static int ast_detect_chip(struct drm_device *dev, bool *need_post) ast->support_wide_screen = true; if (ast->chip == AST2400 && data == 0x100) /* ast1400 */ ast->support_wide_screen = true; + if (ast->chip == AST2500 && data == 0x100) /* ast2510 */ + ast->support_wide_screen = true; } break; } @@ -241,7 +245,23 @@ static int ast_get_dram_info(struct drm_device *dev) else ast->dram_bus_width = 32; - if (ast->chip == AST2300 || ast->chip == AST2400) { + if (ast->chip == AST2500) { + switch (data & 0x03) { + case 0: + ast->dram_type = AST_DRAM_1Gx16; + break; + default: + case 1: + ast->dram_type = AST_DRAM_2Gx16; + break; + case 2: + ast->dram_type = AST_DRAM_4Gx16; + break; + case 3: + ast->dram_type = AST_DRAM_8Gx16; + break; + } + } else if (ast->chip == AST2300 || ast->chip == AST2400) { switch (data & 0x03) { case 0: ast->dram_type = AST_DRAM_512Mx16; diff --git a/src/drivers/aspeed/common/ast_post.c b/src/drivers/aspeed/common/ast_post.c index d14082e0ca..d4ee8b45dd 100644 --- a/src/drivers/aspeed/common/ast_post.c +++ b/src/drivers/aspeed/common/ast_post.c @@ -33,7 +33,8 @@ #include "ast_drv.h" #include "ast_dram_tables.h" -static void ast_init_dram_2300(struct drm_device *dev); +static void ast_post_chip_2300(struct drm_device *dev); +static void ast_post_chip_2500(struct drm_device *dev); void ast_enable_vga(struct drm_device *dev) { @@ -60,13 +61,9 @@ bool ast_is_vga_enabled(struct drm_device *dev) /* TODO 1180 */ } else { ch = ast_io_read8(ast, AST_IO_VGA_ENABLE_PORT); - if (ch) { - ast_open_key(ast); - ch = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xb6, 0xff); - return ch & 0x04; - } + return !!(ch & 0x01); } - return 0; + return false; } static const u8 extreginfo[] = { 0x0f, 0x04, 0x1c, 0xff }; @@ -85,10 +82,11 @@ ast_set_def_ext_reg(struct drm_device *dev) uint8_t revision = data & 0xff; /* reset scratch */ - for (i = 0x81; i <= 0x8f; i++) + for (i = 0x81; i <= 0x9f; i++) ast_set_index_reg(ast, AST_IO_CRTC_PORT, i, 0x00); - if (ast->chip == AST2300 || ast->chip == AST2400) { + if (ast->chip == AST2300 || ast->chip == AST2400 || + ast->chip == AST2500) { if (revision >= 0x20) ext_reg_info = extreginfo_ast2300; else @@ -112,7 +110,8 @@ ast_set_def_ext_reg(struct drm_device *dev) /* Enable RAMDAC for A1 */ reg = 0x04; - if (ast->chip == AST2300 || ast->chip == AST2400) + if (ast->chip == AST2300 || ast->chip == AST2400 || + ast->chip == AST2500) reg |= 0x20; ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xb6, 0xff, reg); } @@ -393,12 +392,14 @@ void ast_post_gpu(struct drm_device *dev) pci_write_config_dword(ast->dev->pdev, 0x04, reg); ast_enable_vga(dev); - ast_enable_mmio(dev); ast_open_key(ast); + ast_enable_mmio(dev); ast_set_def_ext_reg(dev); - if (ast->chip == AST2300 || ast->chip == AST2400) - ast_init_dram_2300(dev); + if (ast->chip == AST2500) + ast_post_chip_2500(dev); + else if (ast->chip == AST2300 || ast->chip == AST2400) + ast_post_chip_2300(dev); else ast_init_dram_reg(dev); @@ -458,87 +459,72 @@ static const u32 pattern[8] = { 0x7C61D253 }; -static int mmc_test_burst(struct ast_private *ast, u32 datagen) +static bool mmc_test(struct ast_private *ast, u32 datagen, u8 test_ctl) { u32 data, timeout; ast_moutdwm(ast, 0x1e6e0070, 0x00000000); - ast_moutdwm(ast, 0x1e6e0070, 0x000000c1 | (datagen << 3)); - timeout = 0; - do { - data = ast_mindwm(ast, 0x1e6e0070) & 0x3000; - if (data & 0x2000) { - return 0; - } - if (++timeout > TIMEOUT) { - ast_moutdwm(ast, 0x1e6e0070, 0x00000000); - return 0; - } - } while (!data); - ast_moutdwm(ast, 0x1e6e0070, 0x00000000); - return 1; -} - -static int mmc_test_burst2(struct ast_private *ast, u32 datagen) -{ - u32 data, timeout; - - ast_moutdwm(ast, 0x1e6e0070, 0x00000000); - ast_moutdwm(ast, 0x1e6e0070, 0x00000041 | (datagen << 3)); - timeout = 0; - do { - data = ast_mindwm(ast, 0x1e6e0070) & 0x1000; - if (++timeout > TIMEOUT) { - ast_moutdwm(ast, 0x1e6e0070, 0x0); - return -1; - } - } while (!data); - data = ast_mindwm(ast, 0x1e6e0078); - data = (data | (data >> 16)) & 0xffff; - ast_moutdwm(ast, 0x1e6e0070, 0x0); - return data; -} - -static int mmc_test_single(struct ast_private *ast, u32 datagen) -{ - u32 data, timeout; - - ast_moutdwm(ast, 0x1e6e0070, 0x00000000); - ast_moutdwm(ast, 0x1e6e0070, 0x000000c5 | (datagen << 3)); + ast_moutdwm(ast, 0x1e6e0070, (datagen << 3) | test_ctl); timeout = 0; do { data = ast_mindwm(ast, 0x1e6e0070) & 0x3000; if (data & 0x2000) - return 0; + return false; if (++timeout > TIMEOUT) { - ast_moutdwm(ast, 0x1e6e0070, 0x0); - return 0; + ast_moutdwm(ast, 0x1e6e0070, 0x00000000); + return false; } } while (!data); ast_moutdwm(ast, 0x1e6e0070, 0x0); - return 1; + return true; } -static int mmc_test_single2(struct ast_private *ast, u32 datagen) +static u32 mmc_test2(struct ast_private *ast, u32 datagen, u8 test_ctl) { u32 data, timeout; ast_moutdwm(ast, 0x1e6e0070, 0x00000000); - ast_moutdwm(ast, 0x1e6e0070, 0x00000005 | (datagen << 3)); + ast_moutdwm(ast, 0x1e6e0070, (datagen << 3) | test_ctl); timeout = 0; do { data = ast_mindwm(ast, 0x1e6e0070) & 0x1000; if (++timeout > TIMEOUT) { ast_moutdwm(ast, 0x1e6e0070, 0x0); - return -1; + return 0xffffffff; } } while (!data); data = ast_mindwm(ast, 0x1e6e0078); data = (data | (data >> 16)) & 0xffff; - ast_moutdwm(ast, 0x1e6e0070, 0x0); + ast_moutdwm(ast, 0x1e6e0070, 0x00000000); return data; } + +static bool mmc_test_burst(struct ast_private *ast, u32 datagen) +{ + return mmc_test(ast, datagen, 0xc1); +} + +static u32 mmc_test_burst2(struct ast_private *ast, u32 datagen) +{ + return mmc_test2(ast, datagen, 0x41); +} + +static bool mmc_test_single(struct ast_private *ast, u32 datagen) +{ + return mmc_test(ast, datagen, 0xc5); +} + +static u32 mmc_test_single2(struct ast_private *ast, u32 datagen) +{ + return mmc_test2(ast, datagen, 0x05); +} + +static bool mmc_test_single_2500(struct ast_private *ast, u32 datagen) +{ + return mmc_test(ast, datagen, 0x85); +} + static int cbr_test(struct ast_private *ast) { u32 data; @@ -614,16 +600,16 @@ static u32 cbr_scan2(struct ast_private *ast) return data2; } -static u32 cbr_test3(struct ast_private *ast) +static bool cbr_test3(struct ast_private *ast) { if (!mmc_test_burst(ast, 0)) - return 0; + return false; if (!mmc_test_single(ast, 0)) - return 0; - return 1; + return false; + return true; } -static u32 cbr_scan3(struct ast_private *ast) +static bool cbr_scan3(struct ast_private *ast) { u32 patcnt, loop; @@ -634,9 +620,9 @@ static u32 cbr_scan3(struct ast_private *ast) break; } if (loop == 2) - return 0; + return false; } - return 1; + return true; } static bool finetuneDQI_L(struct ast_private *ast, struct ast2300_dram_param *param) @@ -1660,7 +1646,7 @@ ddr2_init_start: } -static void ast_init_dram_2300(struct drm_device *dev) +static void ast_post_chip_2300(struct drm_device *dev) { struct ast_private *ast = dev->dev_private; struct ast2300_dram_param param; @@ -1753,3 +1739,405 @@ static void ast_init_dram_2300(struct drm_device *dev) if (timeout >= COREBOOT_AST_FAILOVER_TIMEOUT) dev_err(dev->pdev, "Timeout while waiting for register\n"); } + +static bool cbr_test_2500(struct ast_private *ast) +{ + ast_moutdwm(ast, 0x1E6E0074, 0x0000FFFF); + ast_moutdwm(ast, 0x1E6E007C, 0xFF00FF00); + if (!mmc_test_burst(ast, 0)) + return false; + if (!mmc_test_single_2500(ast, 0)) + return false; + return true; +} + +static bool ddr_test_2500(struct ast_private *ast) +{ + ast_moutdwm(ast, 0x1E6E0074, 0x0000FFFF); + ast_moutdwm(ast, 0x1E6E007C, 0xFF00FF00); + if (!mmc_test_burst(ast, 0)) + return false; + if (!mmc_test_burst(ast, 1)) + return false; + if (!mmc_test_burst(ast, 2)) + return false; + if (!mmc_test_burst(ast, 3)) + return false; + if (!mmc_test_single_2500(ast, 0)) + return false; + return true; +} + +static void ddr_init_common_2500(struct ast_private *ast) +{ + ast_moutdwm(ast, 0x1E6E0034, 0x00020080); + ast_moutdwm(ast, 0x1E6E0008, 0x2003000F); + ast_moutdwm(ast, 0x1E6E0038, 0x00000FFF); + ast_moutdwm(ast, 0x1E6E0040, 0x88448844); + ast_moutdwm(ast, 0x1E6E0044, 0x24422288); + ast_moutdwm(ast, 0x1E6E0048, 0x22222222); + ast_moutdwm(ast, 0x1E6E004C, 0x22222222); + ast_moutdwm(ast, 0x1E6E0050, 0x80000000); + ast_moutdwm(ast, 0x1E6E0208, 0x00000000); + ast_moutdwm(ast, 0x1E6E0218, 0x00000000); + ast_moutdwm(ast, 0x1E6E0220, 0x00000000); + ast_moutdwm(ast, 0x1E6E0228, 0x00000000); + ast_moutdwm(ast, 0x1E6E0230, 0x00000000); + ast_moutdwm(ast, 0x1E6E02A8, 0x00000000); + ast_moutdwm(ast, 0x1E6E02B0, 0x00000000); + ast_moutdwm(ast, 0x1E6E0240, 0x86000000); + ast_moutdwm(ast, 0x1E6E0244, 0x00008600); + ast_moutdwm(ast, 0x1E6E0248, 0x80000000); + ast_moutdwm(ast, 0x1E6E024C, 0x80808080); +} + +static void ddr_phy_init_2500(struct ast_private *ast) +{ + u32 data, pass, timecnt; + + pass = 0; + ast_moutdwm(ast, 0x1E6E0060, 0x00000005); + while (!pass) { + for (timecnt = 0; timecnt < TIMEOUT; timecnt++) { + data = ast_mindwm(ast, 0x1E6E0060) & 0x1; + if (!data) + break; + } + if (timecnt != TIMEOUT) { + data = ast_mindwm(ast, 0x1E6E0300) & 0x000A0000; + if (!data) + pass = 1; + } + if (!pass) { + ast_moutdwm(ast, 0x1E6E0060, 0x00000000); + udelay(10); /* delay 10 us */ + ast_moutdwm(ast, 0x1E6E0060, 0x00000005); + } + } + + ast_moutdwm(ast, 0x1E6E0060, 0x00000006); +} + +/* + * Check DRAM Size + * 1Gb : 0x80000000 ~ 0x87FFFFFF + * 2Gb : 0x80000000 ~ 0x8FFFFFFF + * 4Gb : 0x80000000 ~ 0x9FFFFFFF + * 8Gb : 0x80000000 ~ 0xBFFFFFFF + */ +static void check_dram_size_2500(struct ast_private *ast, u32 tRFC) +{ + u32 reg_04, reg_14; + + reg_04 = ast_mindwm(ast, 0x1E6E0004) & 0xfffffffc; + reg_14 = ast_mindwm(ast, 0x1E6E0014) & 0xffffff00; + + ast_moutdwm(ast, 0xA0100000, 0x41424344); + ast_moutdwm(ast, 0x90100000, 0x35363738); + ast_moutdwm(ast, 0x88100000, 0x292A2B2C); + ast_moutdwm(ast, 0x80100000, 0x1D1E1F10); + + /* Check 8Gbit */ + if (ast_mindwm(ast, 0xA0100000) == 0x41424344) { + reg_04 |= 0x03; + reg_14 |= (tRFC >> 24) & 0xFF; + /* Check 4Gbit */ + } else if (ast_mindwm(ast, 0x90100000) == 0x35363738) { + reg_04 |= 0x02; + reg_14 |= (tRFC >> 16) & 0xFF; + /* Check 2Gbit */ + } else if (ast_mindwm(ast, 0x88100000) == 0x292A2B2C) { + reg_04 |= 0x01; + reg_14 |= (tRFC >> 8) & 0xFF; + } else { + reg_14 |= tRFC & 0xFF; + } + ast_moutdwm(ast, 0x1E6E0004, reg_04); + ast_moutdwm(ast, 0x1E6E0014, reg_14); +} + +static void enable_cache_2500(struct ast_private *ast) +{ + u32 reg_04, data; + + reg_04 = ast_mindwm(ast, 0x1E6E0004); + ast_moutdwm(ast, 0x1E6E0004, reg_04 | 0x1000); + + do + data = ast_mindwm(ast, 0x1E6E0004); + while (!(data & 0x80000)); + ast_moutdwm(ast, 0x1E6E0004, reg_04 | 0x400); +} + +static void set_mpll_2500(struct ast_private *ast) +{ + u32 addr, data, param; + + /* Reset MMC */ + ast_moutdwm(ast, 0x1E6E0000, 0xFC600309); + ast_moutdwm(ast, 0x1E6E0034, 0x00020080); + for (addr = 0x1e6e0004; addr < 0x1e6e0090;) { + ast_moutdwm(ast, addr, 0x0); + addr += 4; + } + ast_moutdwm(ast, 0x1E6E0034, 0x00020000); + + ast_moutdwm(ast, 0x1E6E2000, 0x1688A8A8); + data = ast_mindwm(ast, 0x1E6E2070) & 0x00800000; + if (data) { + /* CLKIN = 25MHz */ + param = 0x930023E0; + ast_moutdwm(ast, 0x1E6E2160, 0x00011320); + } else { + /* CLKIN = 24MHz */ + param = 0x93002400; + } + ast_moutdwm(ast, 0x1E6E2020, param); + udelay(100); +} + +static void reset_mmc_2500(struct ast_private *ast) +{ + ast_moutdwm(ast, 0x1E78505C, 0x00000004); + ast_moutdwm(ast, 0x1E785044, 0x00000001); + ast_moutdwm(ast, 0x1E785048, 0x00004755); + ast_moutdwm(ast, 0x1E78504C, 0x00000013); + mdelay(100); + ast_moutdwm(ast, 0x1E785054, 0x00000077); + ast_moutdwm(ast, 0x1E6E0000, 0xFC600309); +} + +static void ddr3_init_2500(struct ast_private *ast, const u32 *ddr_table) +{ + + ast_moutdwm(ast, 0x1E6E0004, 0x00000303); + ast_moutdwm(ast, 0x1E6E0010, ddr_table[REGIDX_010]); + ast_moutdwm(ast, 0x1E6E0014, ddr_table[REGIDX_014]); + ast_moutdwm(ast, 0x1E6E0018, ddr_table[REGIDX_018]); + ast_moutdwm(ast, 0x1E6E0020, ddr_table[REGIDX_020]); /* MODEREG4/6 */ + ast_moutdwm(ast, 0x1E6E0024, ddr_table[REGIDX_024]); /* MODEREG5 */ + ast_moutdwm(ast, 0x1E6E002C, ddr_table[REGIDX_02C] | 0x100); /* MODEREG0/2 */ + ast_moutdwm(ast, 0x1E6E0030, ddr_table[REGIDX_030]); /* MODEREG1/3 */ + + /* DDR PHY Setting */ + ast_moutdwm(ast, 0x1E6E0200, 0x02492AAE); + ast_moutdwm(ast, 0x1E6E0204, 0x00001001); + ast_moutdwm(ast, 0x1E6E020C, 0x55E00B0B); + ast_moutdwm(ast, 0x1E6E0210, 0x20000000); + ast_moutdwm(ast, 0x1E6E0214, ddr_table[REGIDX_214]); + ast_moutdwm(ast, 0x1E6E02E0, ddr_table[REGIDX_2E0]); + ast_moutdwm(ast, 0x1E6E02E4, ddr_table[REGIDX_2E4]); + ast_moutdwm(ast, 0x1E6E02E8, ddr_table[REGIDX_2E8]); + ast_moutdwm(ast, 0x1E6E02EC, ddr_table[REGIDX_2EC]); + ast_moutdwm(ast, 0x1E6E02F0, ddr_table[REGIDX_2F0]); + ast_moutdwm(ast, 0x1E6E02F4, ddr_table[REGIDX_2F4]); + ast_moutdwm(ast, 0x1E6E02F8, ddr_table[REGIDX_2F8]); + ast_moutdwm(ast, 0x1E6E0290, 0x00100008); + ast_moutdwm(ast, 0x1E6E02C0, 0x00000006); + + /* Controller Setting */ + ast_moutdwm(ast, 0x1E6E0034, 0x00020091); + + /* Wait DDR PHY init done */ + ddr_phy_init_2500(ast); + + ast_moutdwm(ast, 0x1E6E0120, ddr_table[REGIDX_PLL]); + ast_moutdwm(ast, 0x1E6E000C, 0x42AA5C81); + ast_moutdwm(ast, 0x1E6E0034, 0x0001AF93); + + check_dram_size_2500(ast, ddr_table[REGIDX_RFC]); + enable_cache_2500(ast); + ast_moutdwm(ast, 0x1E6E001C, 0x00000008); + ast_moutdwm(ast, 0x1E6E0038, 0xFFFFFF00); +} + +static void ddr4_init_2500(struct ast_private *ast, const u32 *ddr_table) +{ + u32 data, data2, pass, retrycnt; + u32 ddr_vref, phy_vref; + u32 min_ddr_vref = 0, min_phy_vref = 0; + u32 max_ddr_vref = 0, max_phy_vref = 0; + + ast_moutdwm(ast, 0x1E6E0004, 0x00000313); + ast_moutdwm(ast, 0x1E6E0010, ddr_table[REGIDX_010]); + ast_moutdwm(ast, 0x1E6E0014, ddr_table[REGIDX_014]); + ast_moutdwm(ast, 0x1E6E0018, ddr_table[REGIDX_018]); + ast_moutdwm(ast, 0x1E6E0020, ddr_table[REGIDX_020]); /* MODEREG4/6 */ + ast_moutdwm(ast, 0x1E6E0024, ddr_table[REGIDX_024]); /* MODEREG5 */ + ast_moutdwm(ast, 0x1E6E002C, ddr_table[REGIDX_02C] | 0x100); /* MODEREG0/2 */ + ast_moutdwm(ast, 0x1E6E0030, ddr_table[REGIDX_030]); /* MODEREG1/3 */ + + /* DDR PHY Setting */ + ast_moutdwm(ast, 0x1E6E0200, 0x42492AAE); + ast_moutdwm(ast, 0x1E6E0204, 0x09002000); + ast_moutdwm(ast, 0x1E6E020C, 0x55E00B0B); + ast_moutdwm(ast, 0x1E6E0210, 0x20000000); + ast_moutdwm(ast, 0x1E6E0214, ddr_table[REGIDX_214]); + ast_moutdwm(ast, 0x1E6E02E0, ddr_table[REGIDX_2E0]); + ast_moutdwm(ast, 0x1E6E02E4, ddr_table[REGIDX_2E4]); + ast_moutdwm(ast, 0x1E6E02E8, ddr_table[REGIDX_2E8]); + ast_moutdwm(ast, 0x1E6E02EC, ddr_table[REGIDX_2EC]); + ast_moutdwm(ast, 0x1E6E02F0, ddr_table[REGIDX_2F0]); + ast_moutdwm(ast, 0x1E6E02F4, ddr_table[REGIDX_2F4]); + ast_moutdwm(ast, 0x1E6E02F8, ddr_table[REGIDX_2F8]); + ast_moutdwm(ast, 0x1E6E0290, 0x00100008); + ast_moutdwm(ast, 0x1E6E02C4, 0x3C183C3C); + ast_moutdwm(ast, 0x1E6E02C8, 0x00631E0E); + + /* Controller Setting */ + ast_moutdwm(ast, 0x1E6E0034, 0x0001A991); + + /* Train PHY Vref first */ + pass = 0; + + for (retrycnt = 0; retrycnt < 4 && pass == 0; retrycnt++) { + max_phy_vref = 0x0; + pass = 0; + ast_moutdwm(ast, 0x1E6E02C0, 0x00001C06); + for (phy_vref = 0x40; phy_vref < 0x80; phy_vref++) { + ast_moutdwm(ast, 0x1E6E000C, 0x00000000); + ast_moutdwm(ast, 0x1E6E0060, 0x00000000); + ast_moutdwm(ast, 0x1E6E02CC, phy_vref | (phy_vref << 8)); + /* Fire DFI Init */ + ddr_phy_init_2500(ast); + ast_moutdwm(ast, 0x1E6E000C, 0x00005C01); + if (cbr_test_2500(ast)) { + pass++; + data = ast_mindwm(ast, 0x1E6E03D0); + data2 = data >> 8; + data = data & 0xff; + if (data > data2) + data = data2; + if (max_phy_vref < data) { + max_phy_vref = data; + min_phy_vref = phy_vref; + } + } else if (pass > 0) + break; + } + } + ast_moutdwm(ast, 0x1E6E02CC, min_phy_vref | (min_phy_vref << 8)); + + /* Train DDR Vref next */ + pass = 0; + + for (retrycnt = 0; retrycnt < 4 && pass == 0; retrycnt++) { + min_ddr_vref = 0xFF; + max_ddr_vref = 0x0; + pass = 0; + for (ddr_vref = 0x00; ddr_vref < 0x40; ddr_vref++) { + ast_moutdwm(ast, 0x1E6E000C, 0x00000000); + ast_moutdwm(ast, 0x1E6E0060, 0x00000000); + ast_moutdwm(ast, 0x1E6E02C0, 0x00000006 | (ddr_vref << 8)); + /* Fire DFI Init */ + ddr_phy_init_2500(ast); + ast_moutdwm(ast, 0x1E6E000C, 0x00005C01); + if (cbr_test_2500(ast)) { + pass++; + if (min_ddr_vref > ddr_vref) + min_ddr_vref = ddr_vref; + if (max_ddr_vref < ddr_vref) + max_ddr_vref = ddr_vref; + } else if (pass != 0) + break; + } + } + + ast_moutdwm(ast, 0x1E6E000C, 0x00000000); + ast_moutdwm(ast, 0x1E6E0060, 0x00000000); + ddr_vref = (min_ddr_vref + max_ddr_vref + 1) >> 1; + ast_moutdwm(ast, 0x1E6E02C0, 0x00000006 | (ddr_vref << 8)); + + /* Wait DDR PHY init done */ + ddr_phy_init_2500(ast); + + ast_moutdwm(ast, 0x1E6E0120, ddr_table[REGIDX_PLL]); + ast_moutdwm(ast, 0x1E6E000C, 0x42AA5C81); + ast_moutdwm(ast, 0x1E6E0034, 0x0001AF93); + + check_dram_size_2500(ast, ddr_table[REGIDX_RFC]); + enable_cache_2500(ast); + ast_moutdwm(ast, 0x1E6E001C, 0x00000008); + ast_moutdwm(ast, 0x1E6E0038, 0xFFFFFF00); +} + +static bool ast_dram_init_2500(struct ast_private *ast) +{ + u32 data; + u32 max_tries = 5; + + do { + if (max_tries-- == 0) + return false; + set_mpll_2500(ast); + reset_mmc_2500(ast); + ddr_init_common_2500(ast); + + data = ast_mindwm(ast, 0x1E6E2070); + if (data & 0x01000000) + ddr4_init_2500(ast, ast2500_ddr4_1600_timing_table); + else + ddr3_init_2500(ast, ast2500_ddr3_1600_timing_table); + } while (!ddr_test_2500(ast)); + + ast_moutdwm(ast, 0x1E6E2040, ast_mindwm(ast, 0x1E6E2040) | 0x41); + + /* Patch code */ + data = ast_mindwm(ast, 0x1E6E200C) & 0xF9FFFFFF; + ast_moutdwm(ast, 0x1E6E200C, data | 0x10000000); + + return true; +} + +void ast_post_chip_2500(struct drm_device *dev) +{ + struct ast_private *ast = dev->dev_private; + u32 temp; + u8 reg; + + reg = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xd0, 0xff); + if ((reg & 0x80) == 0) {/* vga only */ + /* Clear bus lock condition */ + ast_moutdwm(ast, 0x1e600000, 0xAEED1A03); + ast_moutdwm(ast, 0x1e600084, 0x00010000); + ast_moutdwm(ast, 0x1e600088, 0x00000000); + ast_moutdwm(ast, 0x1e6e2000, 0x1688A8A8); + ast_write32(ast, 0xf004, 0x1e6e0000); + ast_write32(ast, 0xf000, 0x1); + ast_write32(ast, 0x12000, 0x1688a8a8); + while (ast_read32(ast, 0x12000) != 0x1) + ; + + ast_write32(ast, 0x10000, 0xfc600309); + while (ast_read32(ast, 0x10000) != 0x1) + ; + + /* Slow down CPU/AHB CLK in VGA only mode */ + temp = ast_read32(ast, 0x12008); + temp |= 0x73; + ast_write32(ast, 0x12008, temp); + + /* Reset USB port to patch USB unknown device issue */ + ast_moutdwm(ast, 0x1e6e2090, 0x20000000); + temp = ast_mindwm(ast, 0x1e6e2094); + temp |= 0x00004000; + ast_moutdwm(ast, 0x1e6e2094, temp); + temp = ast_mindwm(ast, 0x1e6e2070); + if (temp & 0x00800000) { + ast_moutdwm(ast, 0x1e6e207c, 0x00800000); + mdelay(100); + ast_moutdwm(ast, 0x1e6e2070, 0x00800000); + } + + if (!ast_dram_init_2500(ast)) + printk(BIOS_ERR, "AST: DRAM init failed !\n"); + + temp = ast_mindwm(ast, 0x1e6e2040); + ast_moutdwm(ast, 0x1e6e2040, temp | 0x40); + } + + /* wait ready */ + do { + reg = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xd0, 0xff); + } while ((reg & 0x40) == 0); +} From 32bae49435bc6eb2f590ad685ff63076c5c16436 Mon Sep 17 00:00:00 2001 From: Patrick Rudolph Date: Thu, 8 Aug 2019 12:47:30 +0200 Subject: [PATCH 0648/1242] acpigen: Add methods for mutex operations Tested on Linux 5.2: Dumped and decoded the ACPI tables using iasl. Change-Id: I79310b0f9e2297cf8428d11598935164caf95968 Signed-off-by: Patrick Rudolph Reviewed-on: https://review.coreboot.org/c/coreboot/+/37637 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel Reviewed-by: Felix Held --- src/arch/x86/acpigen.c | 31 +++++++++++++++++++++++++++++ src/arch/x86/include/arch/acpigen.h | 15 ++++++++++++++ 2 files changed, 46 insertions(+) diff --git a/src/arch/x86/acpigen.c b/src/arch/x86/acpigen.c index 1d75889018..cc724a0cc1 100644 --- a/src/arch/x86/acpigen.c +++ b/src/arch/x86/acpigen.c @@ -403,6 +403,37 @@ void acpigen_write_opregion(struct opregion *opreg) acpigen_write_integer(opreg->regionlen); } +/* + * Generate ACPI AML code for Mutex + * Arg0: Pointer to name of mutex + * Arg1: Initial value of mutex + */ +void acpigen_write_mutex(const char *name, const uint8_t flags) +{ + /* MutexOp */ + acpigen_emit_ext_op(MUTEX_OP); + /* NameString 4 chars only */ + acpigen_emit_simple_namestring(name); + acpigen_emit_byte(flags); +} + +void acpigen_write_acquire(const char *name, const uint16_t val) +{ + /* AcquireOp */ + acpigen_emit_ext_op(ACQUIRE_OP); + /* NameString 4 chars only */ + acpigen_emit_simple_namestring(name); + acpigen_emit_word(val); +} + +void acpigen_write_release(const char *name) +{ + /* ReleaseOp */ + acpigen_emit_ext_op(RELEASE_OP); + /* NameString 4 chars only */ + acpigen_emit_simple_namestring(name); +} + static void acpigen_write_field_length(uint32_t len) { uint8_t i, j; diff --git a/src/arch/x86/include/arch/acpigen.h b/src/arch/x86/include/arch/acpigen.h index 6fd9f73e05..8b8c873fb5 100644 --- a/src/arch/x86/include/arch/acpigen.h +++ b/src/arch/x86/include/arch/acpigen.h @@ -410,6 +410,21 @@ void acpigen_write_rom(void *bios, const size_t length); * length. */ void acpigen_write_opregion(struct opregion *opreg); +/* + * Generate ACPI AML code for Mutex + * This function takes mutex name and initial value. + */ +void acpigen_write_mutex(const char *name, const uint8_t flags); +/* + * Generate ACPI AML code for Acquire + * This function takes mutex name and privilege value. + */ +void acpigen_write_acquire(const char *name, const uint16_t val); +/* + * Generate ACPI AML code for Release + * This function takes mutex name. + */ +void acpigen_write_release(const char *name); /* * Generate ACPI AML code for Field * This function takes input region name, fieldlist, count & flags. From 149d523c9a52446bbcf38fa0b5afc9b0c722efb9 Mon Sep 17 00:00:00 2001 From: Paul Fagerburg Date: Tue, 10 Dec 2019 13:57:06 -0700 Subject: [PATCH 0649/1242] util/hatch: remove GBB_HWID, clean up user-visible output * GBB_HWID is no longer used in Hatch Kconfig, so remove the code that creates the GBB_HWID and adds it to the Kconfig section * Add more information in the usage message when the cmdline params are incorrect. * Remove messages that tell the user what to do, because the top-level program that invokes this script will handle those commands, and so this script telling the user what to do is noise (and possibly harmful) * Add more information to the commit message that the script prepares for the user. * Bump script version number. BRANCH=None BUG=b:140261109 TEST=Create the "sushi" variant of the "hatch" baseboard: `util/mainboard/google/hatch/create_coreboot_variant.sh sushi` Inspect the files in src/mainboard/google/hatch/variants/sushi Change-Id: I04e949aedce61ed7fc7df681b72c3cfef31b5513 Signed-off-by: Paul Fagerburg Reviewed-on: https://review.coreboot.org/c/coreboot/+/37647 Tested-by: build bot (Jenkins) Reviewed-by: Justin TerAvest --- .../google/hatch/create_coreboot_variant.sh | 14 ++--- util/mainboard/google/hatch/kconfig.py | 52 ++----------------- 2 files changed, 12 insertions(+), 54 deletions(-) diff --git a/util/mainboard/google/hatch/create_coreboot_variant.sh b/util/mainboard/google/hatch/create_coreboot_variant.sh index 184e54c810..beaf302580 100755 --- a/util/mainboard/google/hatch/create_coreboot_variant.sh +++ b/util/mainboard/google/hatch/create_coreboot_variant.sh @@ -13,7 +13,7 @@ # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the # GNU General Public License for more details. -VERSION="1.0.0" +VERSION="1.0.1" SCRIPT=$(basename -- "${0}") export LC_ALL=C @@ -21,9 +21,8 @@ export LC_ALL=C if [[ "$#" -lt 1 ]]; then echo "Usage: ${SCRIPT} variant_name [b:bug_number]" echo "e.g. ${SCRIPT} kohaku b:140261109" - echo "Adds a new variant of Hatch to Kconfig and Kconfig.name, creates the" - echo "skeleton files for acpi, ec, and gpio, copies the makefile for" - echo "SPD sources, and sets up a basic overridetree" + echo "* Adds a new variant of the baseboard to Kconfig and Kconfig.name" + echo "* Copies the template files for the baseboard to the new variant" exit 1 fi @@ -78,11 +77,12 @@ git add Kconfig Kconfig.name # Now commit the files. git commit -sm "${BASE}: Create ${VARIANT} variant +Create the ${VARIANT} variant of the ${BASE} baseboard by +copying the baseboard template files to a new directory +named for the variant. + (Auto-Generated by ${SCRIPT} version ${VERSION}). BUG=${BUG} TEST=util/abuild/abuild -p none -t google/${BASE} -x -a make sure the build includes GOOGLE_${VARIANT_UPPER}" - -echo "Please check all the files (git show), make any changes you want," -echo "and then push to coreboot HEAD:refs/for/master" diff --git a/util/mainboard/google/hatch/kconfig.py b/util/mainboard/google/hatch/kconfig.py index 891714b53e..f55ceb21e7 100755 --- a/util/mainboard/google/hatch/kconfig.py +++ b/util/mainboard/google/hatch/kconfig.py @@ -3,22 +3,11 @@ To start a new variant of an existing baseboard, we need to add the variant into the Kconfig and Kconfig.name files for the -baseboard. In Kconfig, we have three sections that need additional -entries, GBB_HWID, MAINBOARD_PART_NUMBER, and VARIANT_DIR. +baseboard. In Kconfig, we have two sections that need additional +entries, MAINBOARD_PART_NUMBER and VARIANT_DIR. -In GBB_HWID, we need to add a HWID that includes a numeric suffix. -The numeric suffix is the CRC-32 of the all-caps ASCII name, -modulo 10000. -For example, if the board name is "Fizz", we calculate the CRC of -"FIZZ TEST", which is 0x598C492D. In decimal, the value is 1502365997, -modulo 10000 is 5997. So the HWID string is "FIZZ TEST 5997" -In the past, we have used an online CRC-32 calculator such as -https://www.lammertbies.nl/comm/info/crc-calculation.html, and then -used the calculator app to convert to decimal and take the last -4 digits. - -The MAINBOARD_PART_NUMBER and VARIANT_DIR are simpler, just using -various capitalizations of the variant name to create the strings. +The MAINBOARD_PART_NUMBER and VARIANT_DIR just use various +capitalizations of the variant name to create the strings. Kconfig.name adds an entire section for the new variant, and all of these use various capitalizations of the variant name. The strings @@ -38,7 +27,6 @@ GNU General Public License for more details. """ import argparse -import zlib def main(): @@ -52,26 +40,6 @@ def main(): add_to_Kconfig_name(args.name) -def get_gbb_hwid(variant_name): - """Create the GBB_HWID for a variant - - variant_name The name of the board variant, e.g. 'kohaku' - - Returns: - GBB_HWID string for the board variant, e.g. 'KOHAKU TEST 1953' - - Note that the case of the variant name does not matter; it gets - converted to all uppercase as part of this function.""" - hwid = variant_name + ' test' - upperhwid = hwid.upper() - # Force conversion to unsigned by bitwise AND with (2^32)-1. - # See the docs for crc32 at https://docs.python.org/3/library/zlib.html - # for why '& 0xffffffff' is necessary. - crc = zlib.crc32(upperhwid.encode('UTF-8')) & 0xffffffff - gbb_hwid = upperhwid + ' ' + str(crc % 10000).zfill(4) - return gbb_hwid - - def add_to_Kconfig(variant_name): """Add options for the variant to the Kconfig @@ -84,12 +52,10 @@ def add_to_Kconfig(variant_name): variant_name The name of the board variant, e.g. 'kohaku'""" # These are the part of the strings that we'll add to the sections BOARD = 'BOARD_GOOGLE_' + variant_name.upper() - gbb_hwid = get_gbb_hwid(variant_name) lowercase = variant_name.lower() capitalized = lowercase.capitalize() # These flags track whether we're in a section where we need to add an option - in_gbb_hwid = False in_mainboard_part_number = False in_variant_dir = False @@ -101,8 +67,6 @@ def add_to_Kconfig(variant_name): line = rawline.rstrip('\r\n') # Are we in one of the sections of interest? - if line == 'config GBB_HWID': - in_gbb_hwid = True if line == 'config MAINBOARD_PART_NUMBER': in_mainboard_part_number = True if line == 'config VARIANT_DIR': @@ -111,9 +75,6 @@ def add_to_Kconfig(variant_name): # Are we at the end of a section, and if so, is it one of the # sections of interest? if line == '': - if in_gbb_hwid: - print('\tdefault "' + gbb_hwid + '" if ' + BOARD, file=outfile) - in_gbb_hwid = False if in_mainboard_part_number: print('\tdefault "' + capitalized + '" if ' + BOARD, file=outfile) in_mainboard_part_number = False @@ -130,12 +91,9 @@ def add_to_Kconfig_name(variant_name): Kconfig.name is easier to modify than Kconfig; it only has a block at the end with the new variant's details. - config BOARD_GOOGLE_${VARIANT} - variant_name The name of the board variant, e.g. 'kohaku'""" # Board name for the config section uppercase = variant_name.upper() - BOARD = 'BOARD_GOOGLE_' + uppercase capitalized = variant_name.lower().capitalize() inputname = 'Kconfig.name' @@ -148,7 +106,7 @@ def add_to_Kconfig_name(variant_name): print(line, file=outfile) # Now add the new section - print('\nconfig ' + BOARD, file=outfile) + print('\nconfig ' + 'BOARD_GOOGLE_' + uppercase, file=outfile) print('\tbool "-> ' + capitalized + '"', file=outfile) print('\tselect BOARD_GOOGLE_BASEBOARD_HATCH', file=outfile) print('\tselect BOARD_ROMSIZE_KB_16384', file=outfile) From a6eab80dc9128e8ab82e997159c72906f989ee6c Mon Sep 17 00:00:00 2001 From: Furquan Shaikh Date: Wed, 11 Dec 2019 10:15:59 -0800 Subject: [PATCH 0650/1242] soc/intel/{cnl,icl,skl,tgl}: Remove unused gpe0_en_* from chip.h gpe0_en_* seem to have been copied over from previous generations but recent SoCs don't use it. This change gets rid of these unused members. Change-Id: I165e66aeefde4efea4484f588c774795987ca461 Signed-off-by: Furquan Shaikh Reviewed-on: https://review.coreboot.org/c/coreboot/+/37659 Tested-by: build bot (Jenkins) Reviewed-by: HAOUAS Elyes Reviewed-by: Angel Pons --- src/soc/intel/cannonlake/chip.h | 6 ------ src/soc/intel/icelake/chip.h | 6 ------ src/soc/intel/skylake/chip.h | 5 ----- src/soc/intel/tigerlake/chip.h | 6 ------ 4 files changed, 23 deletions(-) diff --git a/src/soc/intel/cannonlake/chip.h b/src/soc/intel/cannonlake/chip.h index f08fd0a95e..85c33db07b 100644 --- a/src/soc/intel/cannonlake/chip.h +++ b/src/soc/intel/cannonlake/chip.h @@ -45,12 +45,6 @@ struct soc_intel_cannonlake_config { /* Common struct containing soc config data required by common code */ struct soc_intel_common_config common_soc_config; - /* GPE configuration */ - uint32_t gpe0_en_1; /* GPE0_EN_31_0 */ - uint32_t gpe0_en_2; /* GPE0_EN_63_32 */ - uint32_t gpe0_en_3; /* GPE0_EN_95_64 */ - uint32_t gpe0_en_4; /* GPE0_EN_127_96 / GPE_STD */ - /* Gpio group routed to each dword of the GPE0 block. Values are * of the form GPP_[A:G] or GPD. */ uint8_t gpe0_dw0; /* GPE0_31_0 STS/EN */ diff --git a/src/soc/intel/icelake/chip.h b/src/soc/intel/icelake/chip.h index ec625a0049..068751324f 100644 --- a/src/soc/intel/icelake/chip.h +++ b/src/soc/intel/icelake/chip.h @@ -35,12 +35,6 @@ struct soc_intel_icelake_config { /* Common struct containing soc config data required by common code */ struct soc_intel_common_config common_soc_config; - /* GPE configuration */ - uint32_t gpe0_en_1; /* GPE0_EN_31_0 */ - uint32_t gpe0_en_2; /* GPE0_EN_63_32 */ - uint32_t gpe0_en_3; /* GPE0_EN_95_64 */ - uint32_t gpe0_en_4; /* GPE0_EN_127_96 / GPE_STD */ - /* Gpio group routed to each dword of the GPE0 block. Values are * of the form GPP_[A:G] or GPD. */ uint8_t gpe0_dw0; /* GPE0_31_0 STS/EN */ diff --git a/src/soc/intel/skylake/chip.h b/src/soc/intel/skylake/chip.h index 636266632e..b189a16a05 100644 --- a/src/soc/intel/skylake/chip.h +++ b/src/soc/intel/skylake/chip.h @@ -73,11 +73,6 @@ struct soc_intel_skylake_config { uint8_t pirqg_routing; uint8_t pirqh_routing; - /* GPE configuration */ - uint32_t gpe0_en_1; /* GPE0_EN_31_0 */ - uint32_t gpe0_en_2; /* GPE0_EN_63_32 */ - uint32_t gpe0_en_3; /* GPE0_EN_95_64 */ - uint32_t gpe0_en_4; /* GPE0_EN_127_96 / GPE_STD */ /* Gpio group routed to each dword of the GPE0 block. Values are * of the form GPP_[A:G] or GPD. */ uint8_t gpe0_dw0; /* GPE0_31_0 STS/EN */ diff --git a/src/soc/intel/tigerlake/chip.h b/src/soc/intel/tigerlake/chip.h index 32dc02c666..5e0fcd11c5 100644 --- a/src/soc/intel/tigerlake/chip.h +++ b/src/soc/intel/tigerlake/chip.h @@ -35,12 +35,6 @@ struct soc_intel_tigerlake_config { /* Common struct containing soc config data required by common code */ struct soc_intel_common_config common_soc_config; - /* GPE configuration */ - uint32_t gpe0_en_1; /* GPE0_EN_31_0 */ - uint32_t gpe0_en_2; /* GPE0_EN_63_32 */ - uint32_t gpe0_en_3; /* GPE0_EN_95_64 */ - uint32_t gpe0_en_4; /* GPE0_EN_127_96 / GPE_STD */ - /* Gpio group routed to each dword of the GPE0 block. Values are * of the form GPP_[A:G] or GPD. */ uint8_t gpe0_dw0; /* GPE0_31_0 STS/EN */ From 9a0f09334356ed11a02202d3e024a72c62c9755d Mon Sep 17 00:00:00 2001 From: Wim Vervoorn Date: Wed, 11 Dec 2019 14:50:11 +0100 Subject: [PATCH 0651/1242] Documentation: Fix EC type for facebook and portwell boards Board description contained incorrect EC type. Change EC type to ITE8528 BUG=N/A TEST=build Change-Id: Ib5af79fb00bfdfc5dbe001b60010a74bddc696e2 Signed-off-by: Wim Vervoorn Reviewed-on: https://review.coreboot.org/c/coreboot/+/37657 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel Reviewed-by: Angel Pons --- Documentation/mainboard/facebook/fbg1701.md | 2 +- Documentation/mainboard/facebook/monolith.md | 2 +- Documentation/mainboard/portwell/pq7-m107.md | 2 +- 3 files changed, 3 insertions(+), 3 deletions(-) diff --git a/Documentation/mainboard/facebook/fbg1701.md b/Documentation/mainboard/facebook/fbg1701.md index 06bf42fc98..e711ef3126 100644 --- a/Documentation/mainboard/facebook/fbg1701.md +++ b/Documentation/mainboard/facebook/fbg1701.md @@ -72,7 +72,7 @@ Specifically, it's a Winbond W25Q64FV (3.3V), whose datasheet can be found +------------------+--------------------------------------------------+ | CPU | Intel Braswell (N3710) | +------------------+--------------------------------------------------+ -| Super I/O, EC | ITE8256 | +| Super I/O, EC | ITE8528 | +------------------+--------------------------------------------------+ | Coprocessor | Intel Management Engine | +------------------+--------------------------------------------------+ diff --git a/Documentation/mainboard/facebook/monolith.md b/Documentation/mainboard/facebook/monolith.md index a469a8438a..0bc1448c45 100644 --- a/Documentation/mainboard/facebook/monolith.md +++ b/Documentation/mainboard/facebook/monolith.md @@ -67,7 +67,7 @@ output. +------------------+--------------------------------------------------+ | CPU | Intel i3-7100U | +------------------+--------------------------------------------------+ -| Super I/O, EC | ITE8256 | +| Super I/O, EC | ITE8528 | +------------------+--------------------------------------------------+ | Coprocessor | Intel Management Engine | +------------------+--------------------------------------------------+ diff --git a/Documentation/mainboard/portwell/pq7-m107.md b/Documentation/mainboard/portwell/pq7-m107.md index f7e5142bb4..0350ac3652 100644 --- a/Documentation/mainboard/portwell/pq7-m107.md +++ b/Documentation/mainboard/portwell/pq7-m107.md @@ -67,7 +67,7 @@ serial/video/pcie ports might be available. +------------------+--------------------------------------------------+ | CPU | Intel Braswell (N3710) | +------------------+--------------------------------------------------+ -| Super I/O, EC | ITE8256 | +| Super I/O, EC | ITE8528 | +------------------+--------------------------------------------------+ | Coprocessor | Intel Management Engine | +------------------+--------------------------------------------------+ From 3012948b395ddc3b3659701c1b0c7506988cb770 Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Fri, 6 Dec 2019 00:31:22 +0100 Subject: [PATCH 0652/1242] mb/**/hda_verb.c: Clean up formatting Change-Id: Ibe2d92990d0074266aa05ada749e9dad55e609a2 Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/37541 Tested-by: build bot (Jenkins) Reviewed-by: HAOUAS Elyes --- src/mainboard/apple/macbook21/hda_verb.c | 70 +--- src/mainboard/apple/macbookair4_2/hda_verb.c | 41 +-- src/mainboard/asrock/b75pro3-m/hda_verb.c | 49 +-- src/mainboard/asrock/h110m/hda_verb.c | 21 +- src/mainboard/asus/h61m-cs/hda_verb.c | 6 +- src/mainboard/asus/p8h61-m_pro/hda_verb.c | 49 +-- src/mainboard/asus/p8z77-m_pro/hda_verb.c | 17 +- src/mainboard/compulab/intense_pc/hda_verb.c | 49 +-- .../variants/ga-h61m-s2pv/hda_verb.c | 6 +- .../variants/ga-h61ma-d3v/hda_verb.c | 6 +- src/mainboard/google/butterfly/hda_verb.c | 304 ++++++++---------- src/mainboard/hp/2570p/hda_verb.c | 48 +-- src/mainboard/hp/2760p/hda_verb.c | 48 +-- src/mainboard/hp/8460p/hda_verb.c | 35 +- src/mainboard/hp/8770w/hda_verb.c | 28 +- .../hp/compaq_8200_elite_sff/hda_verb.c | 41 +-- src/mainboard/hp/folio_9470m/hda_verb.c | 41 +-- src/mainboard/hp/revolve_810_g1/hda_verb.c | 48 +-- .../hp/z220_sff_workstation/hda_verb.c | 41 +-- src/mainboard/intel/dcp847ske/hda_verb.c | 14 +- src/mainboard/lenovo/l520/hda_verb.c | 41 +-- src/mainboard/lenovo/s230u/hda_verb.c | 89 +++-- src/mainboard/lenovo/t410/hda_verb.c | 33 +- src/mainboard/lenovo/t420/hda_verb.c | 33 +- src/mainboard/lenovo/t420s/hda_verb.c | 51 ++- src/mainboard/lenovo/t430/hda_verb.c | 41 +-- .../lenovo/t430s/variants/t430s/hda_verb.c | 108 ++----- .../lenovo/t430s/variants/t431s/hda_verb.c | 41 +-- src/mainboard/lenovo/t440p/hda_verb.c | 6 +- src/mainboard/lenovo/t520/hda_verb.c | 51 ++- src/mainboard/lenovo/t530/hda_verb.c | 105 ++---- src/mainboard/lenovo/t60/hda_verb.c | 8 +- .../lenovo/x1_carbon_gen1/hda_verb.c | 41 +-- src/mainboard/lenovo/x201/hda_verb.c | 59 +--- src/mainboard/lenovo/x220/hda_verb.c | 78 ++--- src/mainboard/lenovo/x230/hda_verb.c | 106 ++---- src/mainboard/lenovo/x60/hda_verb.c | 6 +- src/mainboard/msi/ms7707/hda_verb.c | 36 +-- src/mainboard/packardbell/ms2290/hda_verb.c | 31 +- .../sapphire/pureplatinumh61/hda_verb.c | 49 +-- 40 files changed, 540 insertions(+), 1435 deletions(-) diff --git a/src/mainboard/apple/macbook21/hda_verb.c b/src/mainboard/apple/macbook21/hda_verb.c index 3d87d3d882..0d4149cf06 100644 --- a/src/mainboard/apple/macbook21/hda_verb.c +++ b/src/mainboard/apple/macbook21/hda_verb.c @@ -17,80 +17,34 @@ #include const u32 cim_verb_data[] = { - /* coreboot specific header */ 0x83847680, /* Codec Vendor / Device ID: SigmaTel STAC9221 A1 */ -#if CONFIG(BOARD_APPLE_MACBOOK11) || \ - CONFIG(BOARD_APPLE_MACBOOK21) +#if CONFIG(BOARD_APPLE_MACBOOK11) || CONFIG(BOARD_APPLE_MACBOOK21) 0x106b2200, /* Subsystem ID */ 11, /* Number of 4 dword sets */ - - /* NID 0x01: Subsystem ID. */ - AZALIA_SUBVENDOR(0x0, 0x106B2200), - - /* NID 0x0A. */ - AZALIA_PIN_CFG(0x0, 0x0A, 0x0321E21F), - - /* NID 0x0B. */ - AZALIA_PIN_CFG(0x0, 0x0B, 0x03A1E02E), - - /* NID 0x0C. */ - AZALIA_PIN_CFG(0x0, 0x0C, 0x9017E110), - - /* NID 0x0D. */ - AZALIA_PIN_CFG(0x0, 0x0D, 0x9017E11F), - - /* NID 0x0E. */ - AZALIA_PIN_CFG(0x0, 0x0E, 0x400000FE), - - /* NID 0x0F */ - AZALIA_PIN_CFG(0x0, 0x0F, 0x0381E020), - - /* NID 0x10 */ - AZALIA_PIN_CFG(0x0, 0x10, 0x1345E230), - - /* NID 0x11 */ - AZALIA_PIN_CFG(0x0, 0x11, 0x13C5E240), - - /* NID 0x15 */ - AZALIA_PIN_CFG(0x0, 0x15, 0x400000FC), - - /* NID 0x1B. */ - AZALIA_PIN_CFG(0x0, 0x1B, 0x400000FB), + AZALIA_SUBVENDOR(0x0, 0x106b2200), + AZALIA_PIN_CFG(0x0, 0x0a, 0x0321e21f), + AZALIA_PIN_CFG(0x0, 0x0b, 0x03a1e02e), + AZALIA_PIN_CFG(0x0, 0x0c, 0x9017e110), + AZALIA_PIN_CFG(0x0, 0x0d, 0x9017e11f), + AZALIA_PIN_CFG(0x0, 0x0e, 0x400000fe), + AZALIA_PIN_CFG(0x0, 0x0f, 0x0381e020), + AZALIA_PIN_CFG(0x0, 0x10, 0x1345e230), + AZALIA_PIN_CFG(0x0, 0x11, 0x13c5e240), + AZALIA_PIN_CFG(0x0, 0x15, 0x400000fc), + AZALIA_PIN_CFG(0x0, 0x1b, 0x400000fb), #else /* CONFIG_BOARD_APPLE_IMAC52 */ 0x106b0f00, /* Subsystem ID */ 11, /* Number of 4 dword sets */ - - /* NID 0x01: Subsystem ID. */ AZALIA_SUBVENDOR(0x0, 0x106b0f00), - - /* NID 0x0A. */ AZALIA_PIN_CFG(0x0, 0x0a, 0x012be032), - - /* NID 0x0B. */ AZALIA_PIN_CFG(0x0, 0x0b, 0x90afe111), - - /* NID 0x0C. */ AZALIA_PIN_CFG(0x0, 0x0c, 0x9017e131), - - /* NID 0x0D. */ AZALIA_PIN_CFG(0x0, 0x0d, 0x4080e10f), - - /* NID 0x0E. */ AZALIA_PIN_CFG(0x0, 0x0e, 0x40f0e00f), - - /* NID 0x0F */ AZALIA_PIN_CFG(0x0, 0x0f, 0x018be021), - - /* NID 0x10 */ AZALIA_PIN_CFG(0x0, 0x10, 0x114bf033), - - /* NID 0x11 */ AZALIA_PIN_CFG(0x0, 0x11, 0x11cbc022), - - /* NID 0x15 */ AZALIA_PIN_CFG(0x0, 0x15, 0x4080e10f), - - /* NID 0x1B. */ AZALIA_PIN_CFG(0x0, 0x1b, 0x4080e10f), #endif diff --git a/src/mainboard/apple/macbookair4_2/hda_verb.c b/src/mainboard/apple/macbookair4_2/hda_verb.c index 69a165ca19..d5b2dcfdca 100644 --- a/src/mainboard/apple/macbookair4_2/hda_verb.c +++ b/src/mainboard/apple/macbookair4_2/hda_verb.c @@ -14,56 +14,27 @@ #include const u32 cim_verb_data[] = { - 0x10134206, /* Codec Vendor / Device ID: Cirrus */ - 0x106b5b00, /* Subsystem ID */ - - 11, /* Number of 4 dword sets */ - /* NID 0x01: Subsystem ID. */ + 0x10134206, /* Codec Vendor / Device ID: Cirrus */ + 0x106b5b00, /* Subsystem ID */ + 11, /* Number of 4 dword sets */ AZALIA_SUBVENDOR(0x0, 0x106b5b00), - - /* NID 0x09. */ AZALIA_PIN_CFG(0x0, 0x09, 0x012b4030), - - /* NID 0x0a. */ AZALIA_PIN_CFG(0x0, 0x0a, 0x400000f0), - - /* NID 0x0b. */ AZALIA_PIN_CFG(0x0, 0x0b, 0x90100120), - - /* NID 0x0c. */ AZALIA_PIN_CFG(0x0, 0x0c, 0x400000f0), - - /* NID 0x0d. */ AZALIA_PIN_CFG(0x0, 0x0d, 0x90a00110), - - /* NID 0x0e. */ AZALIA_PIN_CFG(0x0, 0x0e, 0x400000f0), - - /* NID 0x0f. */ AZALIA_PIN_CFG(0x0, 0x0f, 0x400000f0), - - /* NID 0x10. */ AZALIA_PIN_CFG(0x0, 0x10, 0x400000f0), - - /* NID 0x12. */ AZALIA_PIN_CFG(0x0, 0x12, 0x400000f0), - - /* NID 0x15. */ AZALIA_PIN_CFG(0x0, 0x15, 0x400000f0), - 0x80862805, /* Codec Vendor / Device ID: Intel */ - 0x80860101, /* Subsystem ID */ - 4, /* Number of 4 dword sets */ - /* NID 0x01: Subsystem ID. */ + 0x80862805, /* Codec Vendor / Device ID: Intel */ + 0x80860101, /* Subsystem ID */ + 4, /* Number of 4 dword sets */ AZALIA_SUBVENDOR(0x3, 0x80860101), - - /* NID 0x05. */ AZALIA_PIN_CFG(0x3, 0x05, 0x18560010), - - /* NID 0x06. */ AZALIA_PIN_CFG(0x3, 0x06, 0x18560010), - - /* NID 0x07. */ AZALIA_PIN_CFG(0x3, 0x07, 0x18560010), }; diff --git a/src/mainboard/asrock/b75pro3-m/hda_verb.c b/src/mainboard/asrock/b75pro3-m/hda_verb.c index d7e41b773a..56c36ea96f 100644 --- a/src/mainboard/asrock/b75pro3-m/hda_verb.c +++ b/src/mainboard/asrock/b75pro3-m/hda_verb.c @@ -18,68 +18,31 @@ #include const u32 cim_verb_data[] = { - 0x10ec0892, /* Codec Vendor / Device ID: Realtek */ - 0x18498892, /* Subsystem ID */ - - 15, /* Number of 4 dword sets */ - /* NID 0x01: Subsystem ID. */ + 0x10ec0892, /* Codec Vendor / Device ID: Realtek */ + 0x18498892, /* Subsystem ID */ + 15, /* Number of 4 dword sets */ AZALIA_SUBVENDOR(0x0, 0x18498892), - - /* NID 0x11. */ AZALIA_PIN_CFG(0x0, 0x11, 0x411111f0), - - /* NID 0x12. */ AZALIA_PIN_CFG(0x0, 0x12, 0x411111f0), - - /* NID 0x14. */ AZALIA_PIN_CFG(0x0, 0x14, 0x01014010), - - /* NID 0x15. */ AZALIA_PIN_CFG(0x0, 0x15, 0x01011012), - - /* NID 0x16. */ AZALIA_PIN_CFG(0x0, 0x16, 0x01016011), - - /* NID 0x17. */ AZALIA_PIN_CFG(0x0, 0x17, 0x411111f0), - - /* NID 0x18. */ AZALIA_PIN_CFG(0x0, 0x18, 0x01a19840), - - /* NID 0x19. */ AZALIA_PIN_CFG(0x0, 0x19, 0x02a19950), - - /* NID 0x1a. */ AZALIA_PIN_CFG(0x0, 0x1a, 0x0181304f), - - /* NID 0x1b. */ AZALIA_PIN_CFG(0x0, 0x1b, 0x02214120), - - /* NID 0x1c. */ AZALIA_PIN_CFG(0x0, 0x1c, 0x411111f0), - - /* NID 0x1d. */ AZALIA_PIN_CFG(0x0, 0x1d, 0x4005e601), - - /* NID 0x1e. */ AZALIA_PIN_CFG(0x0, 0x1e, 0x01452130), - - /* NID 0x1f. */ AZALIA_PIN_CFG(0x0, 0x1f, 0x411111f0), - 0x80862806, /* Codec Vendor / Device ID: Intel */ - 0x80860101, /* Subsystem ID */ - 4, /* Number of 4 dword sets */ - /* NID 0x01: Subsystem ID. */ + 0x80862806, /* Codec Vendor / Device ID: Intel */ + 0x80860101, /* Subsystem ID */ + 4, /* Number of 4 dword sets */ AZALIA_SUBVENDOR(0x3, 0x80860101), - - /* NID 0x05. */ AZALIA_PIN_CFG(0x3, 0x05, 0x18560010), - - /* NID 0x06. */ AZALIA_PIN_CFG(0x3, 0x06, 0x18560020), - - /* NID 0x07. */ AZALIA_PIN_CFG(0x3, 0x07, 0x18560030), }; diff --git a/src/mainboard/asrock/h110m/hda_verb.c b/src/mainboard/asrock/h110m/hda_verb.c index 6e13784c27..dd182a9235 100644 --- a/src/mainboard/asrock/h110m/hda_verb.c +++ b/src/mainboard/asrock/h110m/hda_verb.c @@ -18,10 +18,9 @@ #include const u32 cim_verb_data[] = { - /* coreboot specific header ALC887 */ - 0x10ec0887, /* Codec Vendor / Device ID: Realtek */ - 0x10438445, /* Subsystem ID */ - 15, /* Number of 4 dword sets */ + 0x10ec0887, /* Codec Vendor / Device ID: Realtek ALC887 */ + 0x10438445, /* Subsystem ID */ + 15, /* Number of 4 dword sets */ AZALIA_SUBVENDOR(0x0, 0x10438445), AZALIA_PIN_CFG(0x0, 0x11, 0x40000000), AZALIA_PIN_CFG(0x0, 0x12, 0x411111f0), @@ -38,20 +37,12 @@ const u32 cim_verb_data[] = { AZALIA_PIN_CFG(0x0, 0x1e, 0x411111f0), AZALIA_PIN_CFG(0x0, 0x1f, 0x411111f0), - /* coreboot specific header */ - 0x80862809, /* Codec Vendor / Device ID: Intel Skylake HDMI */ - 0x80860101, - 4, - /* NID 0x01, HDA Codec Subsystem ID Verb Table: 0x80860101 */ + 0x80862809, /* Codec Vendor / Device ID: Intel Skylake HDMI */ + 0x80860101, /* Subsystem ID */ + 4, /* Number of 4 dword sets */ AZALIA_SUBVENDOR(0x2, 0x80860101), - - /* Pin Complex (NID 0x05) Digital Out at Int HDMI */ AZALIA_PIN_CFG(0x2, 0x05, 0x18560010), - - /* Pin Complex (NID 0x06) Digital Out at Int HDMI */ AZALIA_PIN_CFG(0x2, 0x06, 0x18560020), - - /* Pin Complex (NID 0x07) Digital Out at Int HDMI */ AZALIA_PIN_CFG(0x2, 0x07, 0x18560030) }; diff --git a/src/mainboard/asus/h61m-cs/hda_verb.c b/src/mainboard/asus/h61m-cs/hda_verb.c index 53b4ea485b..4ee07a7237 100644 --- a/src/mainboard/asus/h61m-cs/hda_verb.c +++ b/src/mainboard/asus/h61m-cs/hda_verb.c @@ -19,9 +19,9 @@ #include const u32 cim_verb_data[] = { - 0x10ec0887, /* Codec Vendor / Device ID: Realtek */ - 0x10438445, /* Subsystem ID */ - 15, /* Number of 4 dword sets */ + 0x10ec0887, /* Codec Vendor / Device ID: Realtek */ + 0x10438445, /* Subsystem ID */ + 15, /* Number of 4 dword sets */ AZALIA_SUBVENDOR(0x0, 0x10438445), AZALIA_PIN_CFG(0x0, 0x11, 0x40330000), AZALIA_PIN_CFG(0x0, 0x12, 0x411111f0), diff --git a/src/mainboard/asus/p8h61-m_pro/hda_verb.c b/src/mainboard/asus/p8h61-m_pro/hda_verb.c index 05a2b39bca..403ecb2730 100644 --- a/src/mainboard/asus/p8h61-m_pro/hda_verb.c +++ b/src/mainboard/asus/p8h61-m_pro/hda_verb.c @@ -16,68 +16,31 @@ #include const u32 cim_verb_data[] = { - 0x10ec0887, /* Codec Vendor / Device ID: Realtek */ - 0x10438444, /* Subsystem ID */ - - 15, /* Number of 4 dword sets */ - /* NID 0x01: Subsystem ID. */ + 0x10ec0887, /* Codec Vendor / Device ID: Realtek */ + 0x10438444, /* Subsystem ID */ + 15, /* Number of 4 dword sets */ AZALIA_SUBVENDOR(0x0, 0x10438444), - - /* NID 0x11. */ AZALIA_PIN_CFG(0x0, 0x11, 0x99430140), - - /* NID 0x12. */ AZALIA_PIN_CFG(0x0, 0x12, 0x411111f0), - - /* NID 0x14. */ AZALIA_PIN_CFG(0x0, 0x14, 0x01014010), - - /* NID 0x15. */ AZALIA_PIN_CFG(0x0, 0x15, 0x01011012), - - /* NID 0x16. */ AZALIA_PIN_CFG(0x0, 0x16, 0x01016011), - - /* NID 0x17. */ AZALIA_PIN_CFG(0x0, 0x17, 0x01012014), - - /* NID 0x18. */ AZALIA_PIN_CFG(0x0, 0x18, 0x01a19850), - - /* NID 0x19. */ AZALIA_PIN_CFG(0x0, 0x19, 0x02a19c60), - - /* NID 0x1a. */ AZALIA_PIN_CFG(0x0, 0x1a, 0x0181305f), - - /* NID 0x1b. */ AZALIA_PIN_CFG(0x0, 0x1b, 0x02214c20), - - /* NID 0x1c. */ AZALIA_PIN_CFG(0x0, 0x1c, 0x411111f0), - - /* NID 0x1d. */ AZALIA_PIN_CFG(0x0, 0x1d, 0x4005e601), - - /* NID 0x1e. */ AZALIA_PIN_CFG(0x0, 0x1e, 0x01456130), - - /* NID 0x1f. */ AZALIA_PIN_CFG(0x0, 0x1f, 0x411111f0), - 0x80862805, /* Codec Vendor / Device ID: Intel */ - 0x80860101, /* Subsystem ID */ - 4, /* Number of 4 dword sets */ - /* NID 0x01: Subsystem ID. */ + 0x80862805, /* Codec Vendor / Device ID: Intel */ + 0x80860101, /* Subsystem ID */ + 4, /* Number of 4 dword sets */ AZALIA_SUBVENDOR(0x3, 0x80860101), - - /* NID 0x05. */ AZALIA_PIN_CFG(0x3, 0x05, 0x58560010), - - /* NID 0x06. */ AZALIA_PIN_CFG(0x3, 0x06, 0x58560020), - - /* NID 0x07. */ AZALIA_PIN_CFG(0x3, 0x07, 0x18560030), }; diff --git a/src/mainboard/asus/p8z77-m_pro/hda_verb.c b/src/mainboard/asus/p8z77-m_pro/hda_verb.c index 1f22a7c68f..4ab54f9238 100644 --- a/src/mainboard/asus/p8z77-m_pro/hda_verb.c +++ b/src/mainboard/asus/p8z77-m_pro/hda_verb.c @@ -19,13 +19,10 @@ #include const u32 cim_verb_data[] = { - 0x10ec0892, /* Codec Vendor / Device ID: Realtek */ - 0x10438436, /* Subsystem ID */ - - 15, /* Number of 4 dword sets */ - /* Subsystem ID */ + 0x10ec0892, /* Codec Vendor / Device ID: Realtek */ + 0x10438436, /* Subsystem ID */ + 15, /* Number of 4 dword sets */ AZALIA_SUBVENDOR(0x0, 0x10438436), - AZALIA_PIN_CFG(0x0, 0x11, 0x99430140), AZALIA_PIN_CFG(0x0, 0x12, 0x411111f0), AZALIA_PIN_CFG(0x0, 0x14, 0x01014010), @@ -40,13 +37,11 @@ const u32 cim_verb_data[] = { AZALIA_PIN_CFG(0x0, 0x1d, 0x4005e601), AZALIA_PIN_CFG(0x0, 0x1e, 0x01456130), AZALIA_PIN_CFG(0x0, 0x1f, 0x411111f0), - 0x80862806, /* Codec Vendor / Device ID: Intel */ - 0x80860101, /* Subsystem ID */ - 4, /* Number of 4 dword sets */ - /* Subsystem ID */ + 0x80862806, /* Codec Vendor / Device ID: Intel */ + 0x80860101, /* Subsystem ID */ + 4, /* Number of 4 dword sets */ AZALIA_SUBVENDOR(0x3, 0x80860101), - AZALIA_PIN_CFG(0x3, 0x05, 0x58560010), AZALIA_PIN_CFG(0x3, 0x06, 0x58560020), AZALIA_PIN_CFG(0x3, 0x07, 0x18560030), diff --git a/src/mainboard/compulab/intense_pc/hda_verb.c b/src/mainboard/compulab/intense_pc/hda_verb.c index c71d83b12e..82017b5c03 100644 --- a/src/mainboard/compulab/intense_pc/hda_verb.c +++ b/src/mainboard/compulab/intense_pc/hda_verb.c @@ -18,68 +18,31 @@ #include const u32 cim_verb_data[] = { - 0x10ec0888, /* Codec Vendor / Device ID: Realtek */ - 0x10ec0888, /* Subsystem ID */ - - 15, /* Number of 4 dword sets */ - /* NID 0x01: Subsystem ID. */ + 0x10ec0888, /* Codec Vendor / Device ID: Realtek */ + 0x10ec0888, /* Subsystem ID */ + 15, /* Number of 4 dword sets */ AZALIA_SUBVENDOR(0x0, 0x10ec0888), - - /* NID 0x11. */ AZALIA_PIN_CFG(0x0, 0x11, 0x411110f0), - - /* NID 0x12. */ AZALIA_PIN_CFG(0x0, 0x12, 0x411111f0), - - /* NID 0x14. */ AZALIA_PIN_CFG(0x0, 0x14, 0x01214120), - - /* NID 0x15. */ AZALIA_PIN_CFG(0x0, 0x15, 0x411111f0), - - /* NID 0x16. */ AZALIA_PIN_CFG(0x0, 0x16, 0x411111f0), - - /* NID 0x17. */ AZALIA_PIN_CFG(0x0, 0x17, 0x411111f0), - - /* NID 0x18. */ AZALIA_PIN_CFG(0x0, 0x18, 0x01a19131), - - /* NID 0x19. */ AZALIA_PIN_CFG(0x0, 0x19, 0x411111f0), - - /* NID 0x1a. */ AZALIA_PIN_CFG(0x0, 0x1a, 0x411111f0), - - /* NID 0x1b. */ AZALIA_PIN_CFG(0x0, 0x1b, 0x411111f0), - - /* NID 0x1c. */ AZALIA_PIN_CFG(0x0, 0x1c, 0x411111f0), - - /* NID 0x1d. */ AZALIA_PIN_CFG(0x0, 0x1d, 0x411111f0), - - /* NID 0x1e. */ AZALIA_PIN_CFG(0x0, 0x1e, 0x014421f0), - - /* NID 0x1f. */ AZALIA_PIN_CFG(0x0, 0x1f, 0x01c421f0), - 0x80862806, /* Codec Vendor / Device ID: Intel */ - 0x80860101, /* Subsystem ID */ - 4, /* Number of 4 dword sets */ - /* NID 0x01: Subsystem ID. */ + 0x80862806, /* Codec Vendor / Device ID: Intel */ + 0x80860101, /* Subsystem ID */ + 4, /* Number of 4 dword sets */ AZALIA_SUBVENDOR(0x3, 0x80860101), - - /* NID 0x05. */ AZALIA_PIN_CFG(0x3, 0x05, 0x58560010), - - /* NID 0x06. */ AZALIA_PIN_CFG(0x3, 0x06, 0x18560020), - - /* NID 0x07. */ AZALIA_PIN_CFG(0x3, 0x07, 0x18560030), }; diff --git a/src/mainboard/gigabyte/ga-h61m-s2pv/variants/ga-h61m-s2pv/hda_verb.c b/src/mainboard/gigabyte/ga-h61m-s2pv/variants/ga-h61m-s2pv/hda_verb.c index a0e0614637..a205ed3cdd 100644 --- a/src/mainboard/gigabyte/ga-h61m-s2pv/variants/ga-h61m-s2pv/hda_verb.c +++ b/src/mainboard/gigabyte/ga-h61m-s2pv/variants/ga-h61m-s2pv/hda_verb.c @@ -17,9 +17,9 @@ #include const u32 cim_verb_data[] = { - 0x10ec0887, /* Realtek ALC887 */ - 0x1458a002, /* Subsystem ID */ - 15, /* Number of 4 dword sets */ + 0x10ec0887, /* Realtek ALC887 */ + 0x1458a002, /* Subsystem ID */ + 15, /* Number of 4 dword sets */ AZALIA_SUBVENDOR(0x2, 0x1458a002), AZALIA_PIN_CFG(0x2, 0x11, 0x411111f0), AZALIA_PIN_CFG(0x2, 0x12, 0x411111f0), diff --git a/src/mainboard/gigabyte/ga-h61m-s2pv/variants/ga-h61ma-d3v/hda_verb.c b/src/mainboard/gigabyte/ga-h61m-s2pv/variants/ga-h61ma-d3v/hda_verb.c index 8860993e27..a28151d6cc 100644 --- a/src/mainboard/gigabyte/ga-h61m-s2pv/variants/ga-h61ma-d3v/hda_verb.c +++ b/src/mainboard/gigabyte/ga-h61m-s2pv/variants/ga-h61ma-d3v/hda_verb.c @@ -17,9 +17,9 @@ #include const u32 cim_verb_data[] = { - 0x10ec0887, /* Realtek ALC887 */ - 0x1458a002, /* Subsystem ID */ - 15, /* Number of 4 dword sets */ + 0x10ec0887, /* Realtek ALC887 */ + 0x1458a002, /* Subsystem ID */ + 15, /* Number of 4 dword sets */ AZALIA_SUBVENDOR(0x2, 0x1458a002), AZALIA_PIN_CFG(0x2, 0x11, 0x411110f0), AZALIA_PIN_CFG(0x2, 0x12, 0x411111f0), diff --git a/src/mainboard/google/butterfly/hda_verb.c b/src/mainboard/google/butterfly/hda_verb.c index fc34e5672d..231c188d17 100644 --- a/src/mainboard/google/butterfly/hda_verb.c +++ b/src/mainboard/google/butterfly/hda_verb.c @@ -13,212 +13,172 @@ * GNU General Public License for more details. */ -/* Vendor Name : IDT - * Vendor ID : 0x111d76e5 - * Subsystem ID : 0x103c18f9 - * Revision ID : 0x100303 - */ - - #include const u32 cim_verb_data[] = { - /* coreboot specific header */ - 0x111D76E5, // Codec Vendor / Device ID: IDT 92HD99 - 0x103C18F9, // Subsystem ID + /* --- Codec #0 --- */ + 0x111d76e5, // Codec Vendor / Device ID: IDT 92HD99 + 0x103c18f9, // Subsystem ID 115, // Number of 4 dword sets + AZALIA_SUBVENDOR(0x0, 0x103c18F9), -/* Bits 31:28 - Codec Address */ -/* Bits 27:20 - NID */ -/* Bits 19:8 - Verb ID */ -/* Bits 7:0 - Payload */ + /* Ext. Microphone Connector: External,Right; MicIn,3.5mm; Black,JD; DA,Seq */ + AZALIA_PIN_CFG(0x0, 0x0a, 0x04a11020), -/* NID 0x01 - NodeInfo */ - AZALIA_SUBVENDOR(0x0, 0x103C18F9), + /* Headphones Connector: External,Right; HP,3.5mm; Black,JD; DA,Seq */ + AZALIA_PIN_CFG(0x0, 0x0b, 0x0421101f), -/* NID 0x0A - External Microphone Connector - * Config=0x04A11020 (External,Right; MicIn,3.5mm; Black,JD; DA,Seq) - */ - AZALIA_PIN_CFG(0x0, 0x0A, 0x04A11020), + /* Not connected: N/A,N/A; Other,Unknown; Unknown,JD; DA,Seq */ + AZALIA_PIN_CFG(0x0, 0x0c, 0x40f000f0), -/* NID 0x0B - Headphone Connector - * Config=0x0421101F (External,Right; HP,3.5mm; Black,JD; DA,Seq) - */ - AZALIA_PIN_CFG(0x0, 0x0B, 0x0421101F), + /* Internal Speakers: Fixed,Int; Speaker,Other Analog; Unknown,nJD; DA,Seq */ + AZALIA_PIN_CFG(0x0, 0x0d, 0x90170110), -/* NID 0x0C - Not connected - * Config=0x40F000F0 (N/A,N/A; Other,Unknown; Unknown,JD; DA,Seq) - */ - AZALIA_PIN_CFG(0x0, 0x0C, 0x40F000F0), + /* Not connected */ + AZALIA_PIN_CFG(0x0, 0x0f, 0x40f000f0), -/* NID 0x0D - Internal Speakers - * Config=0x90170110 (Fixed,Int; Speaker,Other Analog; Unknown,nJD; DA,Seq) - */ - AZALIA_PIN_CFG(0x0, 0x0D, 0x90170110), - -/* NID 0x0F - Not connected - * Config=0x40F000F0 - */ - AZALIA_PIN_CFG(0x0, 0x0F, 0x40F000F0), - -/* NID 0x11 - Internal Microphone - * Config=0xD5A30140 (Fixed internal,Top; Mic In,ATIPI; Unknown,nJD; DA,Seq) - */ - AZALIA_PIN_CFG(0x0, 0x11, 0xD5A30140), + /* Internal Microphone: Fixed,Int,Top; Mic In,ATIPI; Unknown,nJD; DA,Seq */ + AZALIA_PIN_CFG(0x0, 0x11, 0xd5a30140), /* * Hardware EQ Parameters * Sample Rate 88200 */ - 0x0227A63F, 0x0227A73E, 0x0227A8EB, 0x0227A93F, - 0x0227AA3E, 0x0227ABEB, 0x0227AC00, 0x0227AD80, - 0x0227A681, 0x0227A782, 0x0227A829, 0x0227A981, - 0x0227AA82, 0x0227AB29, 0x0227AC01, 0x0227AD80, - 0x0227A63F, 0x0227A73E, 0x0227A8EB, 0x0227A93F, - 0x0227AA3E, 0x0227ABEB, 0x0227AC02, 0x0227AD80, - 0x0227A67E, 0x0227A77B, 0x0227A846, 0x0227A97E, - 0x0227AA7B, 0x0227AB46, 0x0227AC03, 0x0227AD80, - 0x0227A6C1, 0x0227A77F, 0x0227A898, 0x0227A9C1, - 0x0227AA7F, 0x0227AB98, 0x0227AC04, 0x0227AD80, - 0x0227A63E, 0x0227A7D1, 0x0227A84F, 0x0227A93E, - 0x0227AAD1, 0x0227AB4F, 0x0227AC05, 0x0227AD80, - 0x0227A683, 0x0227A7BE, 0x0227A855, 0x0227A983, - 0x0227AABE, 0x0227AB55, 0x0227AC06, 0x0227AD80, - 0x0227A63D, 0x0227A7B9, 0x0227A856, 0x0227A93D, - 0x0227AAB9, 0x0227AB56, 0x0227AC07, 0x0227AD80, - 0x0227A67C, 0x0227A741, 0x0227A8AB, 0x0227A97C, - 0x0227AA41, 0x0227ABAB, 0x0227AC08, 0x0227AD80, - 0x0227A6C3, 0x0227A775, 0x0227A85A, 0x0227A9C3, - 0x0227AA75, 0x0227AB5A, 0x0227AC09, 0x0227AD80, - 0x0227A63F, 0x0227A79E, 0x0227A829, 0x0227A93F, - 0x0227AA9E, 0x0227AB29, 0x0227AC0A, 0x0227AD80, - 0x0227A682, 0x0227A7E3, 0x0227A867, 0x0227A982, - 0x0227AAE3, 0x0227AB67, 0x0227AC0B, 0x0227AD80, - 0x0227A63E, 0x0227A74F, 0x0227A89D, 0x0227A93E, - 0x0227AA4F, 0x0227AB9D, 0x0227AC0C, 0x0227AD80, - 0x0227A67D, 0x0227A71C, 0x0227A899, 0x0227A97D, - 0x0227AA1C, 0x0227AB99, 0x0227AC0D, 0x0227AD80, - 0x0227A6C2, 0x0227A712, 0x0227A839, 0x0227A9C2, - 0x0227AA12, 0x0227AB39, 0x0227AC0E, 0x0227AD80, - 0x0227A63F, 0x0227A708, 0x0227A856, 0x0227A93F, - 0x0227AA08, 0x0227AB56, 0x0227AC0F, 0x0227AD80, - 0x0227A68E, 0x0227A7ED, 0x0227A89D, 0x0227A98E, - 0x0227AAED, 0x0227AB9D, 0x0227AC10, 0x0227AD80, - 0x0227A637, 0x0227A78F, 0x0227A853, 0x0227A937, - 0x0227AA8F, 0x0227AB53, 0x0227AC11, 0x0227AD80, - 0x0227A671, 0x0227A712, 0x0227A863, 0x0227A971, - 0x0227AA12, 0x0227AB63, 0x0227AC12, 0x0227AD80, - 0x0227A6C9, 0x0227A768, 0x0227A856, 0x0227A9C9, - 0x0227AA68, 0x0227AB56, 0x0227AC13, 0x0227AD80, - 0x0227A642, 0x0227A709, 0x0227A838, 0x0227A942, - 0x0227AA09, 0x0227AB38, 0x0227AC14, 0x0227AD80, - 0x0227A69C, 0x0227A78A, 0x0227A867, 0x0227A99C, - 0x0227AA8A, 0x0227AB67, 0x0227AC15, 0x0227AD80, - 0x0227A634, 0x0227A717, 0x0227A8E3, 0x0227A934, - 0x0227AA17, 0x0227ABE3, 0x0227AC16, 0x0227AD80, - 0x0227A663, 0x0227A775, 0x0227A899, 0x0227A963, - 0x0227AA75, 0x0227AB99, 0x0227AC17, 0x0227AD80, - 0x0227A6C9, 0x0227A7DE, 0x0227A8E5, 0x0227A9C9, - 0x0227AADE, 0x0227ABE5, 0x0227AC18, 0x0227AD80, - 0x0227A640, 0x0227A700, 0x0227A800, 0x0227A940, - 0x0227AA00, 0x0227AB00, 0x0227AC19, 0x0227AD80, + 0x0227a63f, 0x0227a73e, 0x0227a8eb, 0x0227a93f, + 0x0227aa3e, 0x0227abeb, 0x0227ac00, 0x0227ad80, + 0x0227a681, 0x0227a782, 0x0227a829, 0x0227a981, + 0x0227aa82, 0x0227ab29, 0x0227ac01, 0x0227ad80, + 0x0227a63f, 0x0227a73e, 0x0227a8eb, 0x0227a93f, + 0x0227aa3e, 0x0227abeb, 0x0227ac02, 0x0227ad80, + 0x0227a67e, 0x0227a77b, 0x0227a846, 0x0227a97e, + 0x0227aa7b, 0x0227ab46, 0x0227ac03, 0x0227ad80, + 0x0227a6c1, 0x0227a77f, 0x0227a898, 0x0227a9c1, + 0x0227aa7f, 0x0227ab98, 0x0227ac04, 0x0227ad80, + 0x0227a63e, 0x0227a7d1, 0x0227a84f, 0x0227a93e, + 0x0227aad1, 0x0227ab4f, 0x0227ac05, 0x0227ad80, + 0x0227a683, 0x0227a7be, 0x0227a855, 0x0227a983, + 0x0227aabe, 0x0227ab55, 0x0227ac06, 0x0227ad80, + 0x0227a63d, 0x0227a7b9, 0x0227a856, 0x0227a93d, + 0x0227aab9, 0x0227ab56, 0x0227ac07, 0x0227ad80, + 0x0227a67c, 0x0227a741, 0x0227a8ab, 0x0227a97c, + 0x0227aa41, 0x0227abab, 0x0227ac08, 0x0227ad80, + 0x0227a6c3, 0x0227a775, 0x0227a85a, 0x0227a9c3, + 0x0227aa75, 0x0227ab5a, 0x0227ac09, 0x0227ad80, + 0x0227a63f, 0x0227a79e, 0x0227a829, 0x0227a93f, + 0x0227aa9e, 0x0227ab29, 0x0227ac0a, 0x0227ad80, + 0x0227a682, 0x0227a7e3, 0x0227a867, 0x0227a982, + 0x0227aae3, 0x0227ab67, 0x0227ac0b, 0x0227ad80, + 0x0227a63e, 0x0227a74f, 0x0227a89d, 0x0227a93e, + 0x0227aa4f, 0x0227ab9d, 0x0227ac0c, 0x0227ad80, + 0x0227a67d, 0x0227a71c, 0x0227a899, 0x0227a97d, + 0x0227aa1c, 0x0227ab99, 0x0227ac0d, 0x0227ad80, + 0x0227a6c2, 0x0227a712, 0x0227a839, 0x0227a9c2, + 0x0227aa12, 0x0227ab39, 0x0227ac0e, 0x0227ad80, + 0x0227a63f, 0x0227a708, 0x0227a856, 0x0227a93f, + 0x0227aa08, 0x0227ab56, 0x0227ac0f, 0x0227ad80, + 0x0227a68e, 0x0227a7ed, 0x0227a89d, 0x0227a98e, + 0x0227aaed, 0x0227ab9d, 0x0227ac10, 0x0227ad80, + 0x0227a637, 0x0227a78f, 0x0227a853, 0x0227a937, + 0x0227aa8f, 0x0227ab53, 0x0227ac11, 0x0227ad80, + 0x0227a671, 0x0227a712, 0x0227a863, 0x0227a971, + 0x0227aa12, 0x0227ab63, 0x0227ac12, 0x0227ad80, + 0x0227a6c9, 0x0227a768, 0x0227a856, 0x0227a9c9, + 0x0227aa68, 0x0227ab56, 0x0227ac13, 0x0227ad80, + 0x0227a642, 0x0227a709, 0x0227a838, 0x0227a942, + 0x0227aa09, 0x0227ab38, 0x0227ac14, 0x0227ad80, + 0x0227a69c, 0x0227a78a, 0x0227a867, 0x0227a99c, + 0x0227aa8a, 0x0227ab67, 0x0227ac15, 0x0227ad80, + 0x0227a634, 0x0227a717, 0x0227a8e3, 0x0227a934, + 0x0227aa17, 0x0227abe3, 0x0227ac16, 0x0227ad80, + 0x0227a663, 0x0227a775, 0x0227a899, 0x0227a963, + 0x0227aa75, 0x0227ab99, 0x0227ac17, 0x0227ad80, + 0x0227a6c9, 0x0227a7de, 0x0227a8e5, 0x0227a9c9, + 0x0227aade, 0x0227abe5, 0x0227ac18, 0x0227ad80, + 0x0227a640, 0x0227a700, 0x0227a800, 0x0227a940, + 0x0227aa00, 0x0227ab00, 0x0227ac19, 0x0227ad80, /* * Hardware EQ Parameters * Sample Rate 96000 */ - 0x0227A63F, 0x0227A74E, 0x0227A888, 0x0227A93F, - 0x0227AA4E, 0x0227AB88, 0x0227AC1A, 0x0227AD80, - 0x0227A681, 0x0227A762, 0x0227A8EE, 0x0227A981, - 0x0227AA62, 0x0227ABEE, 0x0227AC1B, 0x0227AD80, - 0x0227A63F, 0x0227A74E, 0x0227A888, 0x0227A93F, - 0x0227AA4E, 0x0227AB88, 0x0227AC1C, 0x0227AD80, - 0x0227A67E, 0x0227A79A, 0x0227A8E7, 0x0227A97E, - 0x0227AA9A, 0x0227ABE7, 0x0227AC1D, 0x0227AD80, - 0x0227A6C1, 0x0227A760, 0x0227A8C3, 0x0227A9C1, - 0x0227AA60, 0x0227ABC3, 0x0227AC1E, 0x0227AD80, - 0x0227A63E, 0x0227A7E9, 0x0227A84B, 0x0227A93E, - 0x0227AAE9, 0x0227AB4B, 0x0227AC1F, 0x0227AD80, - 0x0227A683, 0x0227A76C, 0x0227A8F2, 0x0227A983, - 0x0227AA6C, 0x0227ABF2, 0x0227AC20, 0x0227AD80, - 0x0227A63D, 0x0227A7E7, 0x0227A880, 0x0227A93D, - 0x0227AAE7, 0x0227AB80, 0x0227AC21, 0x0227AD80, - 0x0227A67C, 0x0227A793, 0x0227A80E, 0x0227A97C, - 0x0227AA93, 0x0227AB0E, 0x0227AC22, 0x0227AD80, - 0x0227A6C3, 0x0227A72F, 0x0227A835, 0x0227A9C3, - 0x0227AA2F, 0x0227AB35, 0x0227AC23, 0x0227AD80, - 0x0227A63F, 0x0227A7A5, 0x0227A8FE, 0x0227A93F, - 0x0227AAA5, 0x0227ABFE, 0x0227AC24, 0x0227AD80, - 0x0227A682, 0x0227A798, 0x0227A89D, 0x0227A982, - 0x0227AA98, 0x0227AB9D, 0x0227AC25, 0x0227AD80, - 0x0227A63E, 0x0227A772, 0x0227A839, 0x0227A93E, - 0x0227AA72, 0x0227AB39, 0x0227AC26, 0x0227AD80, - 0x0227A67D, 0x0227A767, 0x0227A863, 0x0227A97D, - 0x0227AA67, 0x0227AB63, 0x0227AC27, 0x0227AD80, - 0x0227A6C1, 0x0227A7E7, 0x0227A8C8, 0x0227A9C1, - 0x0227AAE7, 0x0227ABC8, 0x0227AC28, 0x0227AD80, - 0x0227A63F, 0x0227A71B, 0x0227A81A, 0x0227A93F, - 0x0227AA1B, 0x0227AB1A, 0x0227AC29, 0x0227AD80, - 0x0227A68D, 0x0227A763, 0x0227A872, 0x0227A98D, - 0x0227AA63, 0x0227AB72, 0x0227AC2A, 0x0227AD80, - 0x0227A638, 0x0227A733, 0x0227A809, 0x0227A938, - 0x0227AA33, 0x0227AB09, 0x0227AC2B, 0x0227AD80, - 0x0227A672, 0x0227A79C, 0x0227A88E, 0x0227A972, - 0x0227AA9C, 0x0227AB8E, 0x0227AC2C, 0x0227AD80, - 0x0227A6C8, 0x0227A7B1, 0x0227A8DD, 0x0227A9C8, - 0x0227AAB1, 0x0227ABDD, 0x0227AC2D, 0x0227AD80, - 0x0227A641, 0x0227A7E1, 0x0227A8D8, 0x0227A941, - 0x0227AAE1, 0x0227ABD8, 0x0227AC2E, 0x0227AD80, - 0x0227A699, 0x0227A70D, 0x0227A820, 0x0227A999, - 0x0227AA0D, 0x0227AB20, 0x0227AC2F, 0x0227AD80, - 0x0227A634, 0x0227A7FE, 0x0227A823, 0x0227A934, - 0x0227AAFE, 0x0227AB23, 0x0227AC30, 0x0227AD80, - 0x0227A666, 0x0227A7F2, 0x0227A8E0, 0x0227A966, - 0x0227AAF2, 0x0227ABE0, 0x0227AC31, 0x0227AD80, - 0x0227A6C9, 0x0227A720, 0x0227A804, 0x0227A9C9, - 0x0227AA20, 0x0227AB04, 0x0227AC32, 0x0227AD80, - 0x0227A640, 0x0227A700, 0x0227A800, 0x0227A940, - 0x0227AA00, 0x0227AB00, 0x0227AC33, 0x0227AD80, + 0x0227a63f, 0x0227a74e, 0x0227a888, 0x0227a93f, + 0x0227aa4e, 0x0227ab88, 0x0227ac1a, 0x0227ad80, + 0x0227a681, 0x0227a762, 0x0227a8ee, 0x0227a981, + 0x0227aa62, 0x0227abee, 0x0227ac1b, 0x0227ad80, + 0x0227a63f, 0x0227a74e, 0x0227a888, 0x0227a93f, + 0x0227aa4e, 0x0227ab88, 0x0227ac1c, 0x0227ad80, + 0x0227a67e, 0x0227a79a, 0x0227a8e7, 0x0227a97e, + 0x0227aa9a, 0x0227abe7, 0x0227ac1d, 0x0227ad80, + 0x0227a6c1, 0x0227a760, 0x0227a8c3, 0x0227a9c1, + 0x0227aa60, 0x0227abc3, 0x0227ac1e, 0x0227ad80, + 0x0227a63e, 0x0227a7e9, 0x0227a84b, 0x0227a93e, + 0x0227aae9, 0x0227ab4b, 0x0227ac1f, 0x0227ad80, + 0x0227a683, 0x0227a76c, 0x0227a8f2, 0x0227a983, + 0x0227aa6c, 0x0227abf2, 0x0227ac20, 0x0227ad80, + 0x0227a63d, 0x0227a7e7, 0x0227a880, 0x0227a93d, + 0x0227aae7, 0x0227ab80, 0x0227ac21, 0x0227ad80, + 0x0227a67c, 0x0227a793, 0x0227a80e, 0x0227a97c, + 0x0227aa93, 0x0227ab0e, 0x0227ac22, 0x0227ad80, + 0x0227a6c3, 0x0227a72f, 0x0227a835, 0x0227a9c3, + 0x0227aa2f, 0x0227ab35, 0x0227ac23, 0x0227ad80, + 0x0227a63f, 0x0227a7a5, 0x0227a8fe, 0x0227a93f, + 0x0227aaa5, 0x0227abfe, 0x0227ac24, 0x0227ad80, + 0x0227a682, 0x0227a798, 0x0227a89d, 0x0227a982, + 0x0227aa98, 0x0227ab9d, 0x0227ac25, 0x0227ad80, + 0x0227a63e, 0x0227a772, 0x0227a839, 0x0227a93e, + 0x0227aa72, 0x0227ab39, 0x0227ac26, 0x0227ad80, + 0x0227a67d, 0x0227a767, 0x0227a863, 0x0227a97d, + 0x0227aa67, 0x0227ab63, 0x0227ac27, 0x0227ad80, + 0x0227a6c1, 0x0227a7e7, 0x0227a8c8, 0x0227a9c1, + 0x0227aae7, 0x0227abc8, 0x0227ac28, 0x0227ad80, + 0x0227a63f, 0x0227a71b, 0x0227a81a, 0x0227a93f, + 0x0227aa1b, 0x0227ab1a, 0x0227ac29, 0x0227ad80, + 0x0227a68d, 0x0227a763, 0x0227a872, 0x0227a98d, + 0x0227aa63, 0x0227ab72, 0x0227ac2a, 0x0227ad80, + 0x0227a638, 0x0227a733, 0x0227a809, 0x0227a938, + 0x0227aa33, 0x0227ab09, 0x0227ac2b, 0x0227ad80, + 0x0227a672, 0x0227a79c, 0x0227a88e, 0x0227a972, + 0x0227aa9c, 0x0227ab8e, 0x0227ac2c, 0x0227ad80, + 0x0227a6c8, 0x0227a7b1, 0x0227a8dd, 0x0227a9c8, + 0x0227aab1, 0x0227abdd, 0x0227ac2d, 0x0227ad80, + 0x0227a641, 0x0227a7e1, 0x0227a8d8, 0x0227a941, + 0x0227aae1, 0x0227abd8, 0x0227ac2e, 0x0227ad80, + 0x0227a699, 0x0227a70d, 0x0227a820, 0x0227a999, + 0x0227aa0d, 0x0227ab20, 0x0227ac2f, 0x0227ad80, + 0x0227a634, 0x0227a7fe, 0x0227a823, 0x0227a934, + 0x0227aafe, 0x0227ab23, 0x0227ac30, 0x0227ad80, + 0x0227a666, 0x0227a7f2, 0x0227a8e0, 0x0227a966, + 0x0227aaf2, 0x0227abe0, 0x0227ac31, 0x0227ad80, + 0x0227a6c9, 0x0227a720, 0x0227a804, 0x0227a9c9, + 0x0227aa20, 0x0227ab04, 0x0227ac32, 0x0227ad80, + 0x0227a640, 0x0227a700, 0x0227a800, 0x0227a940, + 0x0227aa00, 0x0227ab00, 0x0227ac33, 0x0227ad80, /* SAFEDSP Parameters */ - 0x022782C1, 0x02277127, 0x02277227, 0x02278801, - 0x02278C58, 0x02278E90, 0x0227890A, 0x02278A14, - 0x02278B0F, 0x0017B008, + 0x022782c1, 0x02277127, 0x02277227, 0x02278801, + 0x02278c58, 0x02278e90, 0x0227890a, 0x02278a14, + 0x02278b0f, 0x0017b008, /* Misc entries */ - 0x00B707C0, /* Enable PortB as Output with HP amp */ - 0x00D70740, /* Enable PortD as Output */ - 0x0017A200, /* Disable ClkEn of PortSenseTst */ - 0x0017C621, /* Slave Port - Port A used as microphone input for + 0x00b707c0, /* Enable PortB as Output with HP amp */ + 0x00d70740, /* Enable PortD as Output */ + 0x0017a200, /* Disable ClkEn of PortSenseTst */ + 0x0017c621, /* Slave Port - Port A used as microphone input for combo Jack Master Port - Port B used for Jack Presence Detect Enable Combo Jack Detection */ - 0x0017A208, /* Enable ClkEn of PortSenseTst */ + 0x0017a208, /* Enable ClkEn of PortSenseTst */ 0x00170500, /* Set power state to D0 */ - /* --- Next Codec --- */ - -/* Vendor Name : Intel - * Vendor ID : 0x80862806 - * Subsystem ID : 0x80860101 - * Revision ID : 0x100000 - */ - /* coreboot specific header */ + /* --- Codec #3 --- */ 0x80862806, // Codec Vendor / Device ID: Intel PantherPoint HDMI 0x80860101, // Subsystem ID - 4, // Number of IDs - - /* NID 0x01, HDA Codec Subsystem ID Verb Table: 0x80860101 */ + // Revision ID: 0x100000 + 4, // Number of 4 dword sets AZALIA_SUBVENDOR(0x3, 0x80860101), - - /* Pin Complex (NID 0x05) Digital Out at Int HDMI */ AZALIA_PIN_CFG(0x3, 0x05, 0x18560010), - - /* Pin Complex (NID 0x06) Digital Out at Int HDMI */ AZALIA_PIN_CFG(0x3, 0x06, 0x18560020), - - /* Pin Complex (NID 0x07) Digital Out at Int HDMI */ - AZALIA_PIN_CFG(0x3, 0x07, 0x18560030) + AZALIA_PIN_CFG(0x3, 0x07, 0x18560030), }; const u32 pc_beep_verbs[] = { diff --git a/src/mainboard/hp/2570p/hda_verb.c b/src/mainboard/hp/2570p/hda_verb.c index a8e0729ca8..585d94aa9d 100644 --- a/src/mainboard/hp/2570p/hda_verb.c +++ b/src/mainboard/hp/2570p/hda_verb.c @@ -18,62 +18,32 @@ #include const u32 cim_verb_data[] = { - 0x111d7605, /* Codec Vendor / Device ID: IDT */ - 0x103c17df, /* Subsystem ID */ - - 11, /* Number of 4 dword sets */ - /* NID 0x01: Subsystem ID. */ + 0x111d7605, /* Codec Vendor / Device ID: IDT */ + 0x103c17df, /* Subsystem ID */ + 11, /* Number of 4 dword sets */ AZALIA_SUBVENDOR(0x0, 0x103c17df), - - /* NID 0x0a. */ AZALIA_PIN_CFG(0x0, 0x0a, 0x21011030), - - /* NID 0x0b. */ AZALIA_PIN_CFG(0x0, 0x0b, 0x0421101f), - - /* NID 0x0c. */ AZALIA_PIN_CFG(0x0, 0x0c, 0x04a11020), - - /* NID 0x0d. */ AZALIA_PIN_CFG(0x0, 0x0d, 0x90170110), - - /* NID 0x0e. */ AZALIA_PIN_CFG(0x0, 0x0e, 0x40f000f0), - - /* NID 0x0f. */ AZALIA_PIN_CFG(0x0, 0x0f, 0x2181102e), - - /* NID 0x10. */ AZALIA_PIN_CFG(0x0, 0x10, 0x40f000f0), - - /* NID 0x11. */ AZALIA_PIN_CFG(0x0, 0x11, 0xd5a30140), - - /* NID 0x1f. */ AZALIA_PIN_CFG(0x0, 0x1f, 0x40f000f0), - - /* NID 0x20. */ AZALIA_PIN_CFG(0x0, 0x20, 0x40f000f0), - 0x11c11040, /* Codec Vendor / Device ID: LSI */ - 0x103c3066, /* Subsystem ID */ - 1, /* Number of 4 dword sets */ - /* NID 0x01: Subsystem ID. */ + 0x11c11040, /* Codec Vendor / Device ID: LSI */ + 0x103c3066, /* Subsystem ID */ + 1, /* Number of 4 dword sets */ AZALIA_SUBVENDOR(0x1, 0x103c3066), - 0x80862806, /* Codec Vendor / Device ID: Intel */ - 0x80860101, /* Subsystem ID */ - 4, /* Number of 4 dword sets */ - /* NID 0x01: Subsystem ID. */ + 0x80862806, /* Codec Vendor / Device ID: Intel */ + 0x80860101, /* Subsystem ID */ + 4, /* Number of 4 dword sets */ AZALIA_SUBVENDOR(0x3, 0x80860101), - - /* NID 0x05. */ AZALIA_PIN_CFG(0x3, 0x05, 0x18560010), - - /* NID 0x06. */ AZALIA_PIN_CFG(0x3, 0x06, 0x58560020), - - /* NID 0x07. */ AZALIA_PIN_CFG(0x3, 0x07, 0x18560030), }; diff --git a/src/mainboard/hp/2760p/hda_verb.c b/src/mainboard/hp/2760p/hda_verb.c index 48b730a441..35890f34d8 100644 --- a/src/mainboard/hp/2760p/hda_verb.c +++ b/src/mainboard/hp/2760p/hda_verb.c @@ -18,62 +18,32 @@ #include const u32 cim_verb_data[] = { - 0x111d7605, /* Codec Vendor / Device ID: IDT */ - 0x103c162a, /* Subsystem ID */ - - 11, /* Number of 4 dword sets */ - /* NID 0x01: Subsystem ID. */ + 0x111d7605, /* Codec Vendor / Device ID: IDT */ + 0x103c162a, /* Subsystem ID */ + 11, /* Number of 4 dword sets */ AZALIA_SUBVENDOR(0x0, 0x103c162a), - - /* NID 0x0a. */ AZALIA_PIN_CFG(0x0, 0x0a, 0x40f000f0), - - /* NID 0x0b. */ AZALIA_PIN_CFG(0x0, 0x0b, 0x0421401f), - - /* NID 0x0c. */ AZALIA_PIN_CFG(0x0, 0x0c, 0x04a11020), - - /* NID 0x0d. */ AZALIA_PIN_CFG(0x0, 0x0d, 0x90170110), - - /* NID 0x0e. */ AZALIA_PIN_CFG(0x0, 0x0e, 0x90a70130), - - /* NID 0x0f. */ AZALIA_PIN_CFG(0x0, 0x0f, 0x40f000f0), - - /* NID 0x10. */ AZALIA_PIN_CFG(0x0, 0x10, 0x40f000f0), - - /* NID 0x11. */ AZALIA_PIN_CFG(0x0, 0x11, 0x40f000f0), - - /* NID 0x1f. */ AZALIA_PIN_CFG(0x0, 0x1f, 0x40f000f0), - - /* NID 0x20. */ AZALIA_PIN_CFG(0x0, 0x20, 0x40f000f0), - 0x11c11040, /* Codec Vendor / Device ID: LSI */ - 0x103c3066, /* Subsystem ID */ - 1, /* Number of 4 dword sets */ - /* NID 0x01: Subsystem ID. */ + 0x11c11040, /* Codec Vendor / Device ID: LSI */ + 0x103c3066, /* Subsystem ID */ + 1, /* Number of 4 dword sets */ AZALIA_SUBVENDOR(0x1, 0x103c3066), - 0x80862805, /* Codec Vendor / Device ID: Intel */ - 0x80860101, /* Subsystem ID */ - 4, /* Number of 4 dword sets */ - /* NID 0x01: Subsystem ID. */ + 0x80862805, /* Codec Vendor / Device ID: Intel */ + 0x80860101, /* Subsystem ID */ + 4, /* Number of 4 dword sets */ AZALIA_SUBVENDOR(0x3, 0x80860101), - - /* NID 0x05. */ AZALIA_PIN_CFG(0x3, 0x05, 0x18560010), - - /* NID 0x06. */ AZALIA_PIN_CFG(0x3, 0x06, 0x58560020), - - /* NID 0x07. */ AZALIA_PIN_CFG(0x3, 0x07, 0x58560030), }; diff --git a/src/mainboard/hp/8460p/hda_verb.c b/src/mainboard/hp/8460p/hda_verb.c index 964301334a..db9570629b 100644 --- a/src/mainboard/hp/8460p/hda_verb.c +++ b/src/mainboard/hp/8460p/hda_verb.c @@ -18,47 +18,24 @@ #include const u32 cim_verb_data[] = { - 0x111d7605, /* Codec Vendor / Device ID: IDT */ - 0x103c3588, /* Subsystem ID */ - - 11, /* Number of 4 dword sets */ - /* NID 0x01: Subsystem ID. */ + 0x111d7605, /* Codec Vendor / Device ID: IDT */ + 0x103c3588, /* Subsystem ID */ + 11, /* Number of 4 dword sets */ AZALIA_SUBVENDOR(0x0, 0x103c3588), - - /* NID 0x0a. */ AZALIA_PIN_CFG(0x0, 0x0a, 0x40f000f0), - - /* NID 0x0b. */ AZALIA_PIN_CFG(0x0, 0x0b, 0x0421401f), - - /* NID 0x0c. */ AZALIA_PIN_CFG(0x0, 0x0c, 0x04a11020), - - /* NID 0x0d. */ AZALIA_PIN_CFG(0x0, 0x0d, 0x90170110), - - /* NID 0x0e. */ AZALIA_PIN_CFG(0x0, 0x0e, 0x40f000f0), - - /* NID 0x0f. */ AZALIA_PIN_CFG(0x0, 0x0f, 0x40f000f0), - - /* NID 0x10. */ AZALIA_PIN_CFG(0x0, 0x10, 0x40f000f0), - - /* NID 0x11. */ AZALIA_PIN_CFG(0x0, 0x11, 0x90a60130), - - /* NID 0x1f. */ AZALIA_PIN_CFG(0x0, 0x1f, 0x40f000f0), - - /* NID 0x20. */ AZALIA_PIN_CFG(0x0, 0x20, 0x40f000f0), - 0x11c11040, /* Codec Vendor / Device ID: LSI */ - 0x103c3066, /* Subsystem ID */ - 1, /* Number of 4 dword sets */ - /* NID 0x01: Subsystem ID. */ + 0x11c11040, /* Codec Vendor / Device ID: LSI */ + 0x103c3066, /* Subsystem ID */ + 1, /* Number of 4 dword sets */ AZALIA_SUBVENDOR(0x1, 0x103c3066), }; diff --git a/src/mainboard/hp/8770w/hda_verb.c b/src/mainboard/hp/8770w/hda_verb.c index cc66a316ce..958b5bdd5e 100644 --- a/src/mainboard/hp/8770w/hda_verb.c +++ b/src/mainboard/hp/8770w/hda_verb.c @@ -19,41 +19,19 @@ #include const u32 cim_verb_data[] = { - 0x111d7605, /* Codec Vendor / Device ID: IDT */ - 0x103c176c, /* Subsystem ID */ - - 11, /* Number of 4 dword sets */ - /* NID 0x01: Subsystem ID. */ + 0x111d7605, /* Codec Vendor / Device ID: IDT */ + 0x103c176c, /* Subsystem ID */ + 11, /* Number of 4 dword sets */ AZALIA_SUBVENDOR(0x0, 0x103c176c), - - /* NID 0x0a. */ AZALIA_PIN_CFG(0x0, 0x0a, 0x21011030), - - /* NID 0x0b. */ AZALIA_PIN_CFG(0x0, 0x0b, 0x0421101f), - - /* NID 0x0c. */ AZALIA_PIN_CFG(0x0, 0x0c, 0x04a11020), - - /* NID 0x0d. */ AZALIA_PIN_CFG(0x0, 0x0d, 0x90170110), - - /* NID 0x0e. */ AZALIA_PIN_CFG(0x0, 0x0e, 0x40f000f0), - - /* NID 0x0f. */ AZALIA_PIN_CFG(0x0, 0x0f, 0x2181102e), - - /* NID 0x10. */ AZALIA_PIN_CFG(0x0, 0x10, 0x40f000f0), - - /* NID 0x11. */ AZALIA_PIN_CFG(0x0, 0x11, 0xd5a30140), - - /* NID 0x1f. */ AZALIA_PIN_CFG(0x0, 0x1f, 0x40f000f0), - - /* NID 0x20. */ AZALIA_PIN_CFG(0x0, 0x20, 0x40f000f0), }; diff --git a/src/mainboard/hp/compaq_8200_elite_sff/hda_verb.c b/src/mainboard/hp/compaq_8200_elite_sff/hda_verb.c index 907ad2f61c..b6daf8b1f6 100644 --- a/src/mainboard/hp/compaq_8200_elite_sff/hda_verb.c +++ b/src/mainboard/hp/compaq_8200_elite_sff/hda_verb.c @@ -18,56 +18,27 @@ #include const u32 cim_verb_data[] = { - 0x10ec0662, /* Codec Vendor / Device ID: Realtek */ - 0x103c1495, /* Subsystem ID */ - - 11, /* Number of 4 dword sets */ - /* NID 0x01: Subsystem ID. */ + 0x10ec0662, /* Codec Vendor / Device ID: Realtek */ + 0x103c1495, /* Subsystem ID */ + 11, /* Number of 4 dword sets */ AZALIA_SUBVENDOR(0x0, 0x103c1495), - - /* NID 0x14. */ AZALIA_PIN_CFG(0x0, 0x14, 0x01014010), - - /* NID 0x15. */ AZALIA_PIN_CFG(0x0, 0x15, 0x99130120), - - /* NID 0x16. */ AZALIA_PIN_CFG(0x0, 0x16, 0x411111f0), - - /* NID 0x18. */ AZALIA_PIN_CFG(0x0, 0x18, 0x01813c30), - - /* NID 0x19. */ AZALIA_PIN_CFG(0x0, 0x19, 0x02a11c3f), - - /* NID 0x1a. */ AZALIA_PIN_CFG(0x0, 0x1a, 0x411111f0), - - /* NID 0x1b. */ AZALIA_PIN_CFG(0x0, 0x1b, 0x0221101f), - - /* NID 0x1c. */ AZALIA_PIN_CFG(0x0, 0x1c, 0x411111f0), - - /* NID 0x1d. */ AZALIA_PIN_CFG(0x0, 0x1d, 0x40028101), - - /* NID 0x1e. */ AZALIA_PIN_CFG(0x0, 0x1e, 0x411111f0), - 0x80862805, /* Codec Vendor / Device ID: Intel */ - 0x80861495, /* Subsystem ID */ - 4, /* Number of 4 dword sets */ - /* NID 0x01: Subsystem ID. */ + 0x80862805, /* Codec Vendor / Device ID: Intel */ + 0x80861495, /* Subsystem ID */ + 4, /* Number of 4 dword sets */ AZALIA_SUBVENDOR(0x3, 0x80861495), - - /* NID 0x05. */ AZALIA_PIN_CFG(0x3, 0x05, 0x58560010), - - /* NID 0x06. */ AZALIA_PIN_CFG(0x3, 0x06, 0x18560020), - - /* NID 0x07. */ AZALIA_PIN_CFG(0x3, 0x07, 0x58560030), }; diff --git a/src/mainboard/hp/folio_9470m/hda_verb.c b/src/mainboard/hp/folio_9470m/hda_verb.c index 14d181ff89..7852b30eb3 100644 --- a/src/mainboard/hp/folio_9470m/hda_verb.c +++ b/src/mainboard/hp/folio_9470m/hda_verb.c @@ -18,56 +18,27 @@ #include const u32 cim_verb_data[] = { - 0x111d76e0, /* Codec Vendor / Device ID: IDT */ - 0x103c18df, /* Subsystem ID */ - - 11, /* Number of 4 dword sets */ - /* NID 0x01: Subsystem ID. */ + 0x111d76e0, /* Codec Vendor / Device ID: IDT */ + 0x103c18df, /* Subsystem ID */ + 11, /* Number of 4 dword sets */ AZALIA_SUBVENDOR(0x0, 0x103c18df), - - /* NID 0x0a. */ AZALIA_PIN_CFG(0x0, 0x0a, 0x21011030), - - /* NID 0x0b. */ AZALIA_PIN_CFG(0x0, 0x0b, 0x0321101f), - - /* NID 0x0c. */ AZALIA_PIN_CFG(0x0, 0x0c, 0x03a11020), - - /* NID 0x0d. */ AZALIA_PIN_CFG(0x0, 0x0d, 0x90170110), - - /* NID 0x0e. */ AZALIA_PIN_CFG(0x0, 0x0e, 0x40f000f0), - - /* NID 0x0f. */ AZALIA_PIN_CFG(0x0, 0x0f, 0x2181102e), - - /* NID 0x10. */ AZALIA_PIN_CFG(0x0, 0x10, 0x40f000f0), - - /* NID 0x11. */ AZALIA_PIN_CFG(0x0, 0x11, 0xd5a30140), - - /* NID 0x1f. */ AZALIA_PIN_CFG(0x0, 0x1f, 0x40f000f0), - - /* NID 0x20. */ AZALIA_PIN_CFG(0x0, 0x20, 0x40f000f0), - 0x80862806, /* Codec Vendor / Device ID: Intel */ - 0x80860101, /* Subsystem ID */ - 4, /* Number of 4 dword sets */ - /* NID 0x01: Subsystem ID. */ + 0x80862806, /* Codec Vendor / Device ID: Intel */ + 0x80860101, /* Subsystem ID */ + 4, /* Number of 4 dword sets */ AZALIA_SUBVENDOR(0x3, 0x80860101), - - /* NID 0x05. */ AZALIA_PIN_CFG(0x3, 0x05, 0x18560010), - - /* NID 0x06. */ AZALIA_PIN_CFG(0x3, 0x06, 0x58560020), - - /* NID 0x07. */ AZALIA_PIN_CFG(0x3, 0x07, 0x18560030), }; diff --git a/src/mainboard/hp/revolve_810_g1/hda_verb.c b/src/mainboard/hp/revolve_810_g1/hda_verb.c index 693ee40a46..86551a1d3e 100644 --- a/src/mainboard/hp/revolve_810_g1/hda_verb.c +++ b/src/mainboard/hp/revolve_810_g1/hda_verb.c @@ -18,62 +18,32 @@ #include const u32 cim_verb_data[] = { - 0x111d76e0, /* Codec Vendor / Device ID: IDT */ - 0x103c18f8, /* Subsystem ID */ - - 11, /* Number of 4 dword sets */ - /* NID 0x01: Subsystem ID. */ + 0x111d76e0, /* Codec Vendor / Device ID: IDT */ + 0x103c18f8, /* Subsystem ID */ + 11, /* Number of 4 dword sets */ AZALIA_SUBVENDOR(0x0, 0x103c18f8), - - /* NID 0x0a. */ AZALIA_PIN_CFG(0x0, 0x0a, 0x21011030), - - /* NID 0x0b. */ AZALIA_PIN_CFG(0x0, 0x0b, 0x0421101f), - - /* NID 0x0c. */ AZALIA_PIN_CFG(0x0, 0x0c, 0x04a11020), - - /* NID 0x0d. */ AZALIA_PIN_CFG(0x0, 0x0d, 0x90170110), - - /* NID 0x0e. */ AZALIA_PIN_CFG(0x0, 0x0e, 0x40f000f0), - - /* NID 0x0f. */ AZALIA_PIN_CFG(0x0, 0x0f, 0x2181102e), - - /* NID 0x10. */ AZALIA_PIN_CFG(0x0, 0x10, 0x40f000f0), - - /* NID 0x11. */ AZALIA_PIN_CFG(0x0, 0x11, 0xd5a30140), - - /* NID 0x1f. */ AZALIA_PIN_CFG(0x0, 0x1f, 0x40f000f0), - - /* NID 0x20. */ AZALIA_PIN_CFG(0x0, 0x20, 0x40f000f0), - 0x11c11040, /* Codec Vendor / Device ID: LSI */ - 0x103c3066, /* Subsystem ID */ - 1, /* Number of 4 dword sets */ - /* NID 0x01: Subsystem ID. */ + 0x11c11040, /* Codec Vendor / Device ID: LSI */ + 0x103c3066, /* Subsystem ID */ + 1, /* Number of 4 dword sets */ AZALIA_SUBVENDOR(0x1, 0x103c3066), - 0x80862806, /* Codec Vendor / Device ID: Intel */ - 0x80860101, /* Subsystem ID */ - 4, /* Number of 4 dword sets */ - /* NID 0x01: Subsystem ID. */ + 0x80862806, /* Codec Vendor / Device ID: Intel */ + 0x80860101, /* Subsystem ID */ + 4, /* Number of 4 dword sets */ AZALIA_SUBVENDOR(0x3, 0x80860101), - - /* NID 0x05. */ AZALIA_PIN_CFG(0x3, 0x05, 0x18560010), - - /* NID 0x06. */ AZALIA_PIN_CFG(0x3, 0x06, 0x58560020), - - /* NID 0x07. */ AZALIA_PIN_CFG(0x3, 0x07, 0x18560030), }; diff --git a/src/mainboard/hp/z220_sff_workstation/hda_verb.c b/src/mainboard/hp/z220_sff_workstation/hda_verb.c index 9ded3ec136..9ceb2a16a0 100644 --- a/src/mainboard/hp/z220_sff_workstation/hda_verb.c +++ b/src/mainboard/hp/z220_sff_workstation/hda_verb.c @@ -18,56 +18,27 @@ #include const u32 cim_verb_data[] = { - 0x10ec0221, /* Codec Vendor / Device ID: Realtek */ - 0x103c1791, /* Subsystem ID */ - - 11, /* Number of 4 dword sets */ - /* NID 0x01: Subsystem ID. */ + 0x10ec0221, /* Codec Vendor / Device ID: Realtek */ + 0x103c1791, /* Subsystem ID */ + 11, /* Number of 4 dword sets */ AZALIA_SUBVENDOR(0x0, 0x103c1791), - - /* NID 0x12. */ AZALIA_PIN_CFG(0x0, 0x12, 0x403c0000), - - /* NID 0x14. */ AZALIA_PIN_CFG(0x0, 0x14, 0x01014020), - - /* NID 0x17. */ AZALIA_PIN_CFG(0x0, 0x17, 0x90170110), - - /* NID 0x18. */ AZALIA_PIN_CFG(0x0, 0x18, 0x411111f0), - - /* NID 0x19. */ AZALIA_PIN_CFG(0x0, 0x19, 0x411111f0), - - /* NID 0x1a. */ AZALIA_PIN_CFG(0x0, 0x1a, 0x02a11030), - - /* NID 0x1b. */ AZALIA_PIN_CFG(0x0, 0x1b, 0x0181303f), - - /* NID 0x1d. */ AZALIA_PIN_CFG(0x0, 0x1d, 0x40400001), - - /* NID 0x1e. */ AZALIA_PIN_CFG(0x0, 0x1e, 0x411111f0), - - /* NID 0x21. */ AZALIA_PIN_CFG(0x0, 0x21, 0x0221102f), - 0x80862806, /* Codec Vendor / Device ID: Intel */ - 0x103c1791, /* Subsystem ID */ - 4, /* Number of 4 dword sets */ - /* NID 0x01: Subsystem ID. */ + 0x80862806, /* Codec Vendor / Device ID: Intel */ + 0x103c1791, /* Subsystem ID */ + 4, /* Number of 4 dword sets */ AZALIA_SUBVENDOR(0x3, 0x103c1791), - - /* NID 0x05. */ AZALIA_PIN_CFG(0x3, 0x05, 0x58560010), - - /* NID 0x06. */ AZALIA_PIN_CFG(0x3, 0x06, 0x18560020), - - /* NID 0x07. */ AZALIA_PIN_CFG(0x3, 0x07, 0x58560030), }; diff --git a/src/mainboard/intel/dcp847ske/hda_verb.c b/src/mainboard/intel/dcp847ske/hda_verb.c index 3b7190d9e3..dfcaa3a70e 100644 --- a/src/mainboard/intel/dcp847ske/hda_verb.c +++ b/src/mainboard/intel/dcp847ske/hda_verb.c @@ -18,20 +18,12 @@ #include const u32 cim_verb_data[] = { - 0x80862806, /* Codec Vendor / Device ID: Intel */ - 0x80860101, /* Subsystem ID */ - - 4, /* Number of 4 dword sets */ - /* NID 0x01: Subsystem ID. */ + 0x80862806, /* Codec Vendor / Device ID: Intel */ + 0x80860101, /* Subsystem ID */ + 4, /* Number of 4 dword sets */ AZALIA_SUBVENDOR(0x3, 0x80860101), - - /* NID 0x05. */ AZALIA_PIN_CFG(0x3, 0x05, 0x18560010), - - /* NID 0x06. */ AZALIA_PIN_CFG(0x3, 0x06, 0x58560020), - - /* NID 0x07. */ AZALIA_PIN_CFG(0x3, 0x07, 0x18560030), }; diff --git a/src/mainboard/lenovo/l520/hda_verb.c b/src/mainboard/lenovo/l520/hda_verb.c index bca06f5e56..6ab0938466 100644 --- a/src/mainboard/lenovo/l520/hda_verb.c +++ b/src/mainboard/lenovo/l520/hda_verb.c @@ -18,56 +18,27 @@ #include const u32 cim_verb_data[] = { - 0x10ec0269, /* Codec Vendor / Device ID: Realtek */ - 0x17aa21de, /* Subsystem ID */ - - 11, /* Number of 4 dword sets */ - /* NID 0x01: Subsystem ID. */ + 0x10ec0269, /* Codec Vendor / Device ID: Realtek */ + 0x17aa21de, /* Subsystem ID */ + 11, /* Number of 4 dword sets */ AZALIA_SUBVENDOR(0x0, 0x17aa21de), - - /* NID 0x12. */ AZALIA_PIN_CFG(0x0, 0x12, 0x99a30920), - - /* NID 0x14. */ AZALIA_PIN_CFG(0x0, 0x14, 0x99130110), - - /* NID 0x17. */ AZALIA_PIN_CFG(0x0, 0x17, 0x411111f0), - - /* NID 0x18. */ AZALIA_PIN_CFG(0x0, 0x18, 0x03a11830), - - /* NID 0x19. */ AZALIA_PIN_CFG(0x0, 0x19, 0x411111f0), - - /* NID 0x1a. */ AZALIA_PIN_CFG(0x0, 0x1a, 0x411111f0), - - /* NID 0x1b. */ AZALIA_PIN_CFG(0x0, 0x1b, 0x411111f0), - - /* NID 0x1d. */ AZALIA_PIN_CFG(0x0, 0x1d, 0x40079a2d), - - /* NID 0x1e. */ AZALIA_PIN_CFG(0x0, 0x1e, 0x411111f0), - - /* NID 0x21. */ AZALIA_PIN_CFG(0x0, 0x21, 0x0321101f), - 0x80862805, /* Codec Vendor / Device ID: Intel */ - 0x80860101, /* Subsystem ID */ - 4, /* Number of 4 dword sets */ - /* NID 0x01: Subsystem ID. */ + 0x80862805, /* Codec Vendor / Device ID: Intel */ + 0x80860101, /* Subsystem ID */ + 4, /* Number of 4 dword sets */ AZALIA_SUBVENDOR(0x3, 0x80860101), - - /* NID 0x05. */ AZALIA_PIN_CFG(0x3, 0x05, 0x18560010), - - /* NID 0x06. */ AZALIA_PIN_CFG(0x3, 0x06, 0x18560020), - - /* NID 0x07. */ AZALIA_PIN_CFG(0x3, 0x07, 0x18560030), }; diff --git a/src/mainboard/lenovo/s230u/hda_verb.c b/src/mainboard/lenovo/s230u/hda_verb.c index 85150e51a5..b096487d48 100644 --- a/src/mainboard/lenovo/s230u/hda_verb.c +++ b/src/mainboard/lenovo/s230u/hda_verb.c @@ -15,22 +15,19 @@ * GNU General Public License for more details. */ +/* Bits 31:28 - Codec Address */ +/* Bits 27:20 - NID */ +/* Bits 19:8 - Verb ID */ +/* Bits 7:0 - Payload */ #include const u32 cim_verb_data[] = { - /* coreboot specific header */ - 0x10ec0269, // Codec Vendor / Device ID: Realtek ALC269VC - 0x17aa21fa, // Subsystem ID - 12, // Number of 4 dword sets - - /* Bits 31:28 - Codec Address */ - /* Bits 27:20 - NID */ - /* Bits 19:8 - Verb ID */ - /* Bits 7:0 - Payload */ - - /* NID 0x01 - NodeInfo */ - AZALIA_SUBVENDOR(0x0, 0x17AA21FA), + /* --- Codec #0 --- */ + 0x10ec0269, /* Codec Vendor / Device ID: Realtek ALC269VC */ + 0x17aa21fa, /* Subsystem ID */ + 12, /* Number of 4 dword sets */ + AZALIA_SUBVENDOR(0x0, 0x17aa21fa), /* * PIN_CFG: @@ -64,61 +61,49 @@ const u32 cim_verb_data[] = { * 3:0 Sequence * For stream channel to in/out mapping */ - - /* - * NID 0x12 - Digital MIC - * Fixed function, mic in, digital - */ + /* Digital MIC: Fixed function, mic in, digital */ AZALIA_PIN_CFG(0x0, 0x12, 0x90a60940), - /* - * NID 0x14 - SPK out - * Fixed function, speaker, analog - */ + + /* SPK out: Fixed function, speaker, analog */ AZALIA_PIN_CFG(0x0, 0x14, 0x90170110), - /* - * NID 0x15 - HP out - * Location left, headphone out, 1/8" jack, black - */ + + /* HP out: Location left, headphone out, 1/8" jack, black */ AZALIA_PIN_CFG(0x0, 0x15, 0x03211020), - /* NID 0x17 - ? (Unconnected) */ + + /* Unknown: (Unconnected) */ AZALIA_PIN_CFG(0x0, 0x17, 0x411111f0), - /* - * NID 0x18 - MIC1 in - * Location left, mic in, 1/8" jack, black - */ + + /* MIC1 in: Location left, mic in, 1/8" jack, black */ AZALIA_PIN_CFG(0x0, 0x18, 0x03a11830), - /* NID 0x19 - MIC2 in (Unconnected) */ + + /* MIC2 in: (Unconnected) */ AZALIA_PIN_CFG(0x0, 0x19, 0x411111f0), - /* NID 0x1a - Line1 in (Unconnected) */ + + /* Line1 in: (Unconnected) */ AZALIA_PIN_CFG(0x0, 0x1a, 0x411111f0), - /* NID 0x1b - Line2 in (Unconnected) */ + + /* Line2 in: (Unconnected) */ AZALIA_PIN_CFG(0x0, 0x1b, 0x411111f0), - /* NID 0x1d - PCBEEP */ + + /* PCBEEP */ AZALIA_PIN_CFG(0x0, 0x1d, 0x40148605), - /* NID 0x1e - S/PDIF out (Unconnected) */ + + /* S/PDIF out: (Unconnected) */ AZALIA_PIN_CFG(0x0, 0x1e, 0x411111f0), - 0x01470740, // Enable output for NID 0x14 (Speaker out) - 0x015707C0, // Enable output & HP amp for NID 0x15 (HP out) - 0x01870724, // Enable Vrefout NID 0x18 (MIC1 in) - 0x00170500, // Set power state to D0 + 0x01470740, /* Enable output for NID 0x14 (Speaker out) */ + 0x015707C0, /* Enable output & HP amp for NID 0x15 (HP out) */ + 0x01870724, /* Enable Vrefout NID 0x18 (MIC1 in) */ + 0x00170500, /* Set power state to D0 */ - /* coreboot specific header */ - 0x80862806, // Codec Vendor / Device ID: Intel PantherPoint HDMI - 0x80860101, // Subsystem ID - 4, // Number of IDs - - /* NID 0x01, HDA Codec Subsystem ID Verb Table: 0x80860101 */ + /* --- Codec #3 --- */ + 0x80862806, /* Codec Vendor / Device ID: Intel PantherPoint HDMI */ + 0x80860101, /* Subsystem ID */ + 4, /* Number of 4 dword sets */ AZALIA_SUBVENDOR(0x3, 0x80860101), - - /* Pin Complex (NID 0x05) Digital Out at Int HDMI */ AZALIA_PIN_CFG(0x3, 0x05, 0x18560010), - - /* Pin Complex (NID 0x06) Digital Out at Int HDMI */ AZALIA_PIN_CFG(0x3, 0x06, 0x18560020), - - /* Pin Complex (NID 0x07) Digital Out at Int HDMI */ - AZALIA_PIN_CFG(0x3, 0x07, 0x58560030) + AZALIA_PIN_CFG(0x3, 0x07, 0x58560030), }; const u32 pc_beep_verbs[] = { diff --git a/src/mainboard/lenovo/t410/hda_verb.c b/src/mainboard/lenovo/t410/hda_verb.c index 2b871f6280..7569b6b606 100644 --- a/src/mainboard/lenovo/t410/hda_verb.c +++ b/src/mainboard/lenovo/t410/hda_verb.c @@ -17,28 +17,25 @@ #include const u32 cim_verb_data[] = { - /* coreboot specific header */ - 0x14F15069, /* Codec Vendor / Device ID: Conexant CX20585 */ - 0x17AA214C, /* Subsystem ID */ + 0x14f15069, /* Codec Vendor / Device ID: Conexant CX20585 */ + 0x17aa214c, /* Subsystem ID */ 11, /* Number of 4 dword sets */ - - AZALIA_SUBVENDOR(0x0, 0x17AA214C), - AZALIA_PIN_CFG(0x0, 0x19, 0x042110F0), - AZALIA_PIN_CFG(0x0, 0x1A, 0x61A190F0), - AZALIA_PIN_CFG(0x0, 0x1B, 0x04A110F0), - AZALIA_PIN_CFG(0x0, 0x1C, 0x612140F0), - AZALIA_PIN_CFG(0x0, 0x1D, 0x40F001F0), - AZALIA_PIN_CFG(0x0, 0x1E, 0x40F001F0), - AZALIA_PIN_CFG(0x0, 0x1F, 0x901701F0), - AZALIA_PIN_CFG(0x0, 0x20, 0x40F001F0), - AZALIA_PIN_CFG(0x0, 0x22, 0x40F001F0), - AZALIA_PIN_CFG(0x0, 0x23, 0x90A601F0), + AZALIA_SUBVENDOR(0x0, 0x17aa214c), + AZALIA_PIN_CFG(0x0, 0x19, 0x042110f0), + AZALIA_PIN_CFG(0x0, 0x1a, 0x61a190f0), + AZALIA_PIN_CFG(0x0, 0x1b, 0x04a110f0), + AZALIA_PIN_CFG(0x0, 0x1c, 0x612140f0), + AZALIA_PIN_CFG(0x0, 0x1d, 0x40f001f0), + AZALIA_PIN_CFG(0x0, 0x1e, 0x40f001f0), + AZALIA_PIN_CFG(0x0, 0x1f, 0x901701f0), + AZALIA_PIN_CFG(0x0, 0x20, 0x40f001f0), + AZALIA_PIN_CFG(0x0, 0x22, 0x40f001f0), + AZALIA_PIN_CFG(0x0, 0x23, 0x90a601f0), 0x80862804, /* Codec Vendor / Device ID: Intel Ibexpeak HDMI. */ - 0x17AA21B5, /* Subsystem ID */ + 0x17aa21b5, /* Subsystem ID */ 4, /* Number of 4 dword sets */ - - AZALIA_SUBVENDOR(0x3, 0x17AA21B5), + AZALIA_SUBVENDOR(0x3, 0x17aa21b5), AZALIA_PIN_CFG(0x3, 0x04, 0x18560010), AZALIA_PIN_CFG(0x3, 0x05, 0x18560020), AZALIA_PIN_CFG(0x3, 0x06, 0x18560030), diff --git a/src/mainboard/lenovo/t420/hda_verb.c b/src/mainboard/lenovo/t420/hda_verb.c index 9287d4adbe..4c68c73080 100644 --- a/src/mainboard/lenovo/t420/hda_verb.c +++ b/src/mainboard/lenovo/t420/hda_verb.c @@ -14,29 +14,18 @@ * GNU General Public License for more details. */ -/* Vendor Name : Conexant - * Vendor ID : 0x14f1506e - * Subsystem ID : 0x17aa21d2 - * Revision ID : 0x100002 - */ - - -#include - -const u32 cim_verb_data[] = { - /* coreboot specific header */ - 0x14f1506e, // Codec Vendor / Device ID: Conexant CX20590 - Schematic show CX20672 - 0x17aa21ce, // Subsystem ID - 13, // Number of 4 dword sets - /* Bits 31:28 - Codec Address */ /* Bits 27:20 - NID */ /* Bits 19:8 - Verb ID */ /* Bits 7:0 - Payload */ -/* NID 0x01 - NodeInfo */ - AZALIA_SUBVENDOR(0x0, 0x17AA21D2), +#include +const u32 cim_verb_data[] = { + 0x14f1506e, /* Codec VID / DID: Conexant CX20590 - schematic shows CX20672 */ + 0x17aa21ce, /* Subsystem ID */ + 13, /* Number of 4 dword sets */ + AZALIA_SUBVENDOR(0x0, 0x17aa21d2), AZALIA_PIN_CFG(0x0, 0x12, 0x90a60140), AZALIA_PIN_CFG(0x0, 0x14, 0x90170110), AZALIA_PIN_CFG(0x0, 0x15, 0x03211020), @@ -49,14 +38,14 @@ const u32 cim_verb_data[] = { AZALIA_PIN_CFG(0x0, 0x1e, 0x411111f0), /* Misc entries */ - 0x00B707C0, /* Enable PortB as Output with HP amp */ - 0x00D70740, /* Enable PortD as Output */ - 0x0017A200, /* Disable ClkEn of PortSenseTst */ - 0x0017C621, /* Slave Port - Port A used as microphone input for + 0x00b707C0, /* Enable PortB as Output with HP amp */ + 0x00d70740, /* Enable PortD as Output */ + 0x0017a200, /* Disable ClkEn of PortSenseTst */ + 0x0017c621, /* Slave Port - Port A used as microphone input for combo Jack Master Port - Port B used for Jack Presence Detect Enable Combo Jack Detection */ - 0x0017A208, /* Enable ClkEn of PortSenseTst */ + 0x0017a208, /* Enable ClkEn of PortSenseTst */ 0x00170500, /* Set power state to D0 */ 0x00170500, /* Padding */ 0x00170500, /* Padding */ diff --git a/src/mainboard/lenovo/t420s/hda_verb.c b/src/mainboard/lenovo/t420s/hda_verb.c index 8a9c3e5b77..9d315d7911 100644 --- a/src/mainboard/lenovo/t420s/hda_verb.c +++ b/src/mainboard/lenovo/t420s/hda_verb.c @@ -14,49 +14,38 @@ * GNU General Public License for more details. */ -/* Vendor Name : Conexant - * Vendor ID : 0x14f1506e - * Subsystem ID : 0x17aa21d2 - * Revision ID : 0x100002 - */ - - -#include - -const u32 cim_verb_data[] = { - /* coreboot specific header */ - 0x14f1506e, // Codec Vendor / Device ID: Conexant CX20590 - Schematic show CX20672 - 0x17aa21d2, // Subsystem ID - 13, // Number of 4 dword sets - /* Bits 31:28 - Codec Address */ /* Bits 27:20 - NID */ /* Bits 19:8 - Verb ID */ /* Bits 7:0 - Payload */ -/* NID 0x01 - NodeInfo */ - AZALIA_SUBVENDOR(0x0, 0x17AA21D2), +#include +const u32 cim_verb_data[] = { + 0x14f1506e, /* Codec VID / DID: Conexant CX20590 - schematic shows CX20672 */ + 0x17aa21d2, /* Subsystem ID */ + 13, /* Number of 4 dword sets */ + AZALIA_SUBVENDOR(0x0, 0x17aa21d2), AZALIA_PIN_CFG(0x0, 0x19, 0x04211040), - AZALIA_PIN_CFG(0x0, 0x1A, 0x61A19050), - AZALIA_PIN_CFG(0x0, 0x1B, 0x04A11060), - AZALIA_PIN_CFG(0x0, 0x1C, 0x6121401F), - AZALIA_PIN_CFG(0x0, 0x1D, 0x40F001F0), - AZALIA_PIN_CFG(0x0, 0x1E, 0x40F001F0), - AZALIA_PIN_CFG(0x0, 0x1F, 0x90170110), - AZALIA_PIN_CFG(0x0, 0x20, 0x40F001F0), - AZALIA_PIN_CFG(0x0, 0x22, 0x40F001F0), - AZALIA_PIN_CFG(0x0, 0x23, 0x90A60170), + AZALIA_PIN_CFG(0x0, 0x1a, 0x61a19050), + AZALIA_PIN_CFG(0x0, 0x1b, 0x04a11060), + AZALIA_PIN_CFG(0x0, 0x1c, 0x6121401f), + AZALIA_PIN_CFG(0x0, 0x1d, 0x40f001f0), + AZALIA_PIN_CFG(0x0, 0x1e, 0x40f001f0), + AZALIA_PIN_CFG(0x0, 0x1f, 0x90170110), + AZALIA_PIN_CFG(0x0, 0x20, 0x40f001f0), + AZALIA_PIN_CFG(0x0, 0x22, 0x40f001f0), + AZALIA_PIN_CFG(0x0, 0x23, 0x90a60170), /* Misc entries */ - 0x00B707C0, /* Enable PortB as Output with HP amp */ - 0x00D70740, /* Enable PortD as Output */ - 0x0017A200, /* Disable ClkEn of PortSenseTst */ - 0x0017C621, /* Slave Port - Port A used as microphone input for + 0x00b707C0, /* Enable PortB as Output with HP amp */ + 0x00d70740, /* Enable PortD as Output */ + 0x0017a200, /* Disable ClkEn of PortSenseTst */ + 0x0017c621, /* Slave Port - Port A used as microphone input for combo Jack Master Port - Port B used for Jack Presence Detect Enable Combo Jack Detection */ - 0x0017A208, /* Enable ClkEn of PortSenseTst */ + 0x0017a208, /* Enable ClkEn of PortSenseTst */ 0x00170500, /* Set power state to D0 */ 0x00170500, /* Padding */ 0x00170500, /* Padding */ diff --git a/src/mainboard/lenovo/t430/hda_verb.c b/src/mainboard/lenovo/t430/hda_verb.c index 255198f044..a8f67277f8 100644 --- a/src/mainboard/lenovo/t430/hda_verb.c +++ b/src/mainboard/lenovo/t430/hda_verb.c @@ -16,56 +16,27 @@ #include const u32 cim_verb_data[] = { - 0x10ec0269, /* Codec Vendor / Device ID: Realtek */ - 0x17aa21f3, /* Subsystem ID */ - - 11, /* Number of 4 dword sets */ - /* NID 0x01: Subsystem ID. */ + 0x10ec0269, /* Codec Vendor / Device ID: Realtek */ + 0x17aa21f3, /* Subsystem ID */ + 11, /* Number of 4 dword sets */ AZALIA_SUBVENDOR(0x0, 0x17aa21f3), - - /* NID 0x12. */ AZALIA_PIN_CFG(0x0, 0x12, 0x90a60140), - - /* NID 0x14. */ AZALIA_PIN_CFG(0x0, 0x14, 0x90170110), - - /* NID 0x15. */ AZALIA_PIN_CFG(0x0, 0x15, 0x03211020), - - /* NID 0x17. */ AZALIA_PIN_CFG(0x0, 0x17, 0x411111f0), - - /* NID 0x18. */ AZALIA_PIN_CFG(0x0, 0x18, 0x03a11830), - - /* NID 0x19. */ AZALIA_PIN_CFG(0x0, 0x19, 0x411111f0), - - /* NID 0x1a. */ AZALIA_PIN_CFG(0x0, 0x1a, 0x411111f0), - - /* NID 0x1b. */ AZALIA_PIN_CFG(0x0, 0x1b, 0x411111f0), - - /* NID 0x1d. */ AZALIA_PIN_CFG(0x0, 0x1d, 0x40138205), - - /* NID 0x1e. */ AZALIA_PIN_CFG(0x0, 0x1e, 0x411111f0), - 0x80862806, /* Codec Vendor / Device ID: Intel */ - 0x80860101, /* Subsystem ID */ - 4, /* Number of 4 dword sets */ - /* NID 0x01: Subsystem ID. */ + 0x80862806, /* Codec Vendor / Device ID: Intel */ + 0x80860101, /* Subsystem ID */ + 4, /* Number of 4 dword sets */ AZALIA_SUBVENDOR(0x3, 0x80860101), - - /* NID 0x05. */ AZALIA_PIN_CFG(0x3, 0x05, 0x18560010), - - /* NID 0x06. */ AZALIA_PIN_CFG(0x3, 0x06, 0x18560020), - - /* NID 0x07. */ AZALIA_PIN_CFG(0x3, 0x07, 0x18560030), }; diff --git a/src/mainboard/lenovo/t430s/variants/t430s/hda_verb.c b/src/mainboard/lenovo/t430s/variants/t430s/hda_verb.c index c5c17b8061..b8f6bfed16 100644 --- a/src/mainboard/lenovo/t430s/variants/t430s/hda_verb.c +++ b/src/mainboard/lenovo/t430s/variants/t430s/hda_verb.c @@ -14,110 +14,72 @@ * GNU General Public License for more details. */ -/* Vendor Name : Realtek - * Vendor ID : 0x10ec0269 - * Subsystem ID : 0x17aa21fb - * Revision ID : 0x100203 - */ - - -#include - -const u32 cim_verb_data[] = { - /* coreboot specific header */ - 0x10ec0269, // Codec Vendor / Device ID: Realtek ALC269VC - 0x17aa21fb, // Subsystem ID - 19, // Number of 4 dword sets - /* Bits 31:28 - Codec Address */ /* Bits 27:20 - NID */ /* Bits 19:8 - Verb ID */ /* Bits 7:0 - Payload */ -/* NID 0x01 - NodeInfo */ - AZALIA_SUBVENDOR(0x0, 0x17AA21FB), +#include -/* NID 0x0A - External Microphone Connector - * Config=0x04A11020 (External,Right; MicIn,3.5mm; Black,JD; DA,Seq) - */ - AZALIA_PIN_CFG(0x0, 0x0A, 0x04A11020), +const u32 cim_verb_data[] = { + /* --- Codec #0 --- */ + 0x10ec0269, /* Codec Vendor / Device ID: Realtek ALC269VC */ + 0x17aa21fb, /* Subsystem ID */ + 19, /* Number of 4 dword sets */ + AZALIA_SUBVENDOR(0x0, 0x17aa21fb), -/* NID 0x0B - Headphone Connector - * Config=0x0421101F (External,Right; HP,3.5mm; Black,JD; DA,Seq) - */ - AZALIA_PIN_CFG(0x0, 0x0B, 0x0421101F), + /* Ext. Microphone Connector: External,Right; MicIn,3.5mm; Black,JD; DA,Seq */ + AZALIA_PIN_CFG(0x0, 0x0a, 0x04a11020), -/* NID 0x0C - Not connected - * Config=0x40F000F0 (N/A,N/A; Other,Unknown; Unknown,JD; DA,Seq) - */ - AZALIA_PIN_CFG(0x0, 0x0C, 0x40F000F0), + /* Headphones Connector: External,Right; HP,3.5mm; Black,JD; DA,Seq */ + AZALIA_PIN_CFG(0x0, 0x0b, 0x0421101f), -/* NID 0x0D - Internal Speakers - * Config=0x90170110 (Fixed,Int; Speaker,Other Analog; Unknown,nJD; DA,Seq) - */ - AZALIA_PIN_CFG(0x0, 0x0D, 0x90170110), + /* Not connected: N/A,N/A; Other,Unknown; Unknown,JD; DA,Seq */ + AZALIA_PIN_CFG(0x0, 0x0c, 0x40f000f0), -/* NID 0x0F - Not connected - * Config=0x40F000F0 - */ - AZALIA_PIN_CFG(0x0, 0x0F, 0x40F000F0), + /* Internal Speakers Fixed,Int; Speaker,Other Analog; Unknown,nJD; DA,Seq */ + AZALIA_PIN_CFG(0x0, 0x0d, 0x90170110), -/* NID 0x11 - Internal Microphone - * Config=0xD5A30140 (Fixed internal,Top; Mic In,ATIPI; Unknown,nJD; DA,Seq) - */ - AZALIA_PIN_CFG(0x0, 0x12, 0x90A60140), + /* Not connected */ + AZALIA_PIN_CFG(0x0, 0x0f, 0x40f000f0), + AZALIA_PIN_CFG(0x0, 0x12, 0x90a60140), AZALIA_PIN_CFG(0x0, 0x14, 0x90170110), AZALIA_PIN_CFG(0x0, 0x15, 0x03211020), - AZALIA_PIN_CFG(0x0, 0x17, 0x411111F0), - AZALIA_PIN_CFG(0x0, 0x18, 0x03A11830), - AZALIA_PIN_CFG(0x0, 0x19, 0x411111F0), + AZALIA_PIN_CFG(0x0, 0x17, 0x411111f0), + AZALIA_PIN_CFG(0x0, 0x18, 0x03a11830), + AZALIA_PIN_CFG(0x0, 0x19, 0x411111f0), 0x01970804, 0x01870803, 0x01470740, 0x00970600, - AZALIA_PIN_CFG(0x0, 0x1A, 0x411111F0), - AZALIA_PIN_CFG(0x0, 0x1B, 0x411111F0), - AZALIA_PIN_CFG(0x0, 0x1D, 0x40138205), - AZALIA_PIN_CFG(0x0, 0x1E, 0x411111F0), + AZALIA_PIN_CFG(0x0, 0x1a, 0x411111f0), + AZALIA_PIN_CFG(0x0, 0x1b, 0x411111f0), + AZALIA_PIN_CFG(0x0, 0x1d, 0x40138205), + AZALIA_PIN_CFG(0x0, 0x1e, 0x411111f0), /* Misc entries */ 0x00370600, 0x00270600, - 0x00B707C0, /* Enable PortB as Output with HP amp */ - 0x00D70740, /* Enable PortD as Output */ - 0x0017A200, /* Disable ClkEn of PortSenseTst */ - 0x0017C621, /* Slave Port - Port A used as microphone input for + 0x00b707C0, /* Enable PortB as Output with HP amp */ + 0x00d70740, /* Enable PortD as Output */ + 0x0017a200, /* Disable ClkEn of PortSenseTst */ + 0x0017c621, /* Slave Port - Port A used as microphone input for combo Jack Master Port - Port B used for Jack Presence Detect Enable Combo Jack Detection */ - 0x0017A208, /* Enable ClkEn of PortSenseTst */ + 0x0017a208, /* Enable ClkEn of PortSenseTst */ 0x00170500, /* Set power state to D0 */ - /* --- Next Codec --- */ - -/* Vendor Name : Intel - * Vendor ID : 0x80862806 - * Subsystem ID : 0x80860101 - * Revision ID : 0x100000 - */ - /* coreboot specific header */ - 0x80862806, // Codec Vendor / Device ID: Intel PantherPoint HDMI - 0x80860101, // Subsystem ID - 4, // Number of IDs - - /* NID 0x01, HDA Codec Subsystem ID Verb Table: 0x80860101 */ + /* --- Codec #3 --- */ + 0x80862806, /* Codec Vendor / Device ID: Intel PantherPoint HDMI */ + 0x80860101, /* Subsystem ID */ + 4, /* Number of 4 dword sets */ AZALIA_SUBVENDOR(0x3, 0x80860101), - - /* Pin Complex (NID 0x05) Digital Out at Int HDMI */ AZALIA_PIN_CFG(0x3, 0x05, 0x18560010), - - /* Pin Complex (NID 0x06) Digital Out at Int HDMI */ AZALIA_PIN_CFG(0x3, 0x06, 0x18560020), - - /* Pin Complex (NID 0x07) Digital Out at Int HDMI */ - AZALIA_PIN_CFG(0x3, 0x07, 0x18560030) + AZALIA_PIN_CFG(0x3, 0x07, 0x18560030), }; const u32 pc_beep_verbs[] = { diff --git a/src/mainboard/lenovo/t430s/variants/t431s/hda_verb.c b/src/mainboard/lenovo/t430s/variants/t431s/hda_verb.c index 1c5d376247..5d47099db5 100644 --- a/src/mainboard/lenovo/t430s/variants/t431s/hda_verb.c +++ b/src/mainboard/lenovo/t430s/variants/t431s/hda_verb.c @@ -18,56 +18,27 @@ #include const u32 cim_verb_data[] = { - 0x10ec0269, /* Codec Vendor / Device ID: Realtek */ - 0x17aa2208, /* Subsystem ID */ - - 11, /* Number of 4 dword sets */ - /* NID 0x01: Subsystem ID. */ + 0x10ec0269, /* Codec Vendor / Device ID: Realtek */ + 0x17aa2208, /* Subsystem ID */ + 11, /* Number of 4 dword sets */ AZALIA_SUBVENDOR(0x0, 0x17aa2208), - - /* NID 0x12. */ AZALIA_PIN_CFG(0x0, 0x12, 0x90a60140), - - /* NID 0x14. */ AZALIA_PIN_CFG(0x0, 0x14, 0x90170110), - - /* NID 0x15. */ AZALIA_PIN_CFG(0x0, 0x15, 0x03211020), - - /* NID 0x17. */ AZALIA_PIN_CFG(0x0, 0x17, 0x40008000), - - /* NID 0x18. */ AZALIA_PIN_CFG(0x0, 0x18, 0x03a11030), - - /* NID 0x19. */ AZALIA_PIN_CFG(0x0, 0x19, 0x411111f0), - - /* NID 0x1a. */ AZALIA_PIN_CFG(0x0, 0x1a, 0x411111f0), - - /* NID 0x1b. */ AZALIA_PIN_CFG(0x0, 0x1b, 0x411111f0), - - /* NID 0x1d. */ AZALIA_PIN_CFG(0x0, 0x1d, 0x40f38205), - - /* NID 0x1e. */ AZALIA_PIN_CFG(0x0, 0x1e, 0x411111f0), - 0x80862806, /* Codec Vendor / Device ID: Intel */ - 0x80860101, /* Subsystem ID */ - 4, /* Number of 4 dword sets */ - /* NID 0x01: Subsystem ID. */ + 0x80862806, /* Codec Vendor / Device ID: Intel */ + 0x80860101, /* Subsystem ID */ + 4, /* Number of 4 dword sets */ AZALIA_SUBVENDOR(0x3, 0x80860101), - - /* NID 0x05. */ AZALIA_PIN_CFG(0x3, 0x05, 0x18560010), - - /* NID 0x06. */ AZALIA_PIN_CFG(0x3, 0x06, 0x18560020), - - /* NID 0x07. */ AZALIA_PIN_CFG(0x3, 0x07, 0x18560030), }; diff --git a/src/mainboard/lenovo/t440p/hda_verb.c b/src/mainboard/lenovo/t440p/hda_verb.c index 9527312340..791638d760 100644 --- a/src/mainboard/lenovo/t440p/hda_verb.c +++ b/src/mainboard/lenovo/t440p/hda_verb.c @@ -18,9 +18,9 @@ #include const u32 cim_verb_data[] = { - 0x10ec0292, /* Codec Vendor / Device ID: Realtek */ - 0x17aa220e, /* Subsystem ID */ - 12, /* Number of 4 dword sets */ + 0x10ec0292, /* Codec Vendor / Device ID: Realtek */ + 0x17aa220e, /* Subsystem ID */ + 12, /* Number of 4 dword sets */ AZALIA_SUBVENDOR(0x0, 0x17aa220e), AZALIA_PIN_CFG(0x0, 0x12, 0x90a60130), AZALIA_PIN_CFG(0x0, 0x13, 0x40000000), diff --git a/src/mainboard/lenovo/t520/hda_verb.c b/src/mainboard/lenovo/t520/hda_verb.c index 2d10e35b19..46d7d9484d 100644 --- a/src/mainboard/lenovo/t520/hda_verb.c +++ b/src/mainboard/lenovo/t520/hda_verb.c @@ -14,49 +14,38 @@ * GNU General Public License for more details. */ -/* Vendor Name : Conexant - * Vendor ID : 0x14f1506e - * Subsystem ID : 0x17aa21cf - * Revision ID : 0x100000 - */ - - -#include - -const u32 cim_verb_data[] = { - /* coreboot specific header */ - 0x14f1506e, // Codec Vendor / Device ID: Conexant CX20590 - Schematic shows CX20672 - 0x17aa21cf, // Subsystem ID - 13, // Number of 4 dword sets - /* Bits 31:28 - Codec Address */ /* Bits 27:20 - NID */ /* Bits 19:8 - Verb ID */ /* Bits 7:0 - Payload */ -/* NID 0x01 - NodeInfo */ - AZALIA_SUBVENDOR(0x0, 0x17AA21CF), +#include +const u32 cim_verb_data[] = { + 0x14f1506e, /* Codec VID / DID: Conexant CX20590 - Schematic shows CX20672 */ + 0x17aa21cf, /* Subsystem ID */ + 13, /* Number of 4 dword sets */ + AZALIA_SUBVENDOR(0x0, 0x17aa21cf), AZALIA_PIN_CFG(0x0, 0x19, 0x04211040), - AZALIA_PIN_CFG(0x0, 0x1A, 0x61A19050), - AZALIA_PIN_CFG(0x0, 0x1B, 0x04A11060), - AZALIA_PIN_CFG(0x0, 0x1C, 0x6121401F), - AZALIA_PIN_CFG(0x0, 0x1D, 0x40F001F0), - AZALIA_PIN_CFG(0x0, 0x1E, 0x40F001F0), - AZALIA_PIN_CFG(0x0, 0x1F, 0x90170110), - AZALIA_PIN_CFG(0x0, 0x20, 0x40F001F0), - AZALIA_PIN_CFG(0x0, 0x22, 0x40F001F0), - AZALIA_PIN_CFG(0x0, 0x23, 0x90A60170), + AZALIA_PIN_CFG(0x0, 0x1a, 0x61a19050), + AZALIA_PIN_CFG(0x0, 0x1b, 0x04a11060), + AZALIA_PIN_CFG(0x0, 0x1c, 0x6121401f), + AZALIA_PIN_CFG(0x0, 0x1d, 0x40f001f0), + AZALIA_PIN_CFG(0x0, 0x1e, 0x40f001f0), + AZALIA_PIN_CFG(0x0, 0x1f, 0x90170110), + AZALIA_PIN_CFG(0x0, 0x20, 0x40f001f0), + AZALIA_PIN_CFG(0x0, 0x22, 0x40f001f0), + AZALIA_PIN_CFG(0x0, 0x23, 0x90a60170), /* Misc entries */ - 0x00B707C0, /* Enable PortB as Output with HP amp */ - 0x00D70740, /* Enable PortD as Output */ - 0x0017A200, /* Disable ClkEn of PortSenseTst */ - 0x0017C621, /* Slave Port - Port A used as microphone input for + 0x00b707c0, /* Enable PortB as Output with HP amp */ + 0x00d70740, /* Enable PortD as Output */ + 0x0017a200, /* Disable ClkEn of PortSenseTst */ + 0x0017c621, /* Slave Port - Port A used as microphone input for combo Jack Master Port - Port B used for Jack Presence Detect Enable Combo Jack Detection */ - 0x0017A208, /* Enable ClkEn of PortSenseTst */ + 0x0017a208, /* Enable ClkEn of PortSenseTst */ 0x00170500, /* Set power state to D0 */ 0x00170500, /* Padding */ 0x00170500, /* Padding */ diff --git a/src/mainboard/lenovo/t530/hda_verb.c b/src/mainboard/lenovo/t530/hda_verb.c index f8876aa1c8..5ed12b4882 100644 --- a/src/mainboard/lenovo/t530/hda_verb.c +++ b/src/mainboard/lenovo/t530/hda_verb.c @@ -14,108 +14,71 @@ * GNU General Public License for more details. */ -/* Vendor Name : IDT - * Vendor ID : 0x10ec0269 - * Subsystem ID : 0x17aa21fa - * Revision ID : 0x100303 - */ - - -#include - -const u32 cim_verb_data[] = { - /* coreboot specific header */ - 0x10ec0269, // Codec Vendor / Device ID: Realtek ALC269VC - 0x17aa21fa, // Subsystem ID - 18, // Number of 4 dword sets - /* Bits 31:28 - Codec Address */ /* Bits 27:20 - NID */ /* Bits 19:8 - Verb ID */ /* Bits 7:0 - Payload */ -/* NID 0x01 - NodeInfo */ - AZALIA_SUBVENDOR(0x0, 0x17AA21FA), +#include -/* NID 0x0A - External Microphone Connector - * Config=0x04A11020 (External,Right; MicIn,3.5mm; Black,JD; DA,Seq) - */ - AZALIA_PIN_CFG(0x0, 0x0A, 0x04A11020), +const u32 cim_verb_data[] = { + 0x10ec0269, /* Codec Vendor / Device ID: Realtek ALC269VC */ + 0x17aa21fa, /* Subsystem ID */ + 18, /* Number of 4 dword sets */ + AZALIA_SUBVENDOR(0x0, 0x17aa21fa), -/* NID 0x0B - Headphone Connector - * Config=0x0421101F (External,Right; HP,3.5mm; Black,JD; DA,Seq) - */ - AZALIA_PIN_CFG(0x0, 0x0B, 0x0421101F), + /* Ext. Microphone Connector: External,Right; MicIn,3.5mm; Black,JD; DA,Seq */ + AZALIA_PIN_CFG(0x0, 0x0a, 0x04a11020), -/* NID 0x0C - Not connected - * Config=0x40F000F0 (N/A,N/A; Other,Unknown; Unknown,JD; DA,Seq) - */ - AZALIA_PIN_CFG(0x0, 0x0C, 0x40F000F0), + /* Headphones Connector: External,Right; HP,3.5mm; Black,JD; DA,Seq */ + AZALIA_PIN_CFG(0x0, 0x0b, 0x0421101f), -/* NID 0x0D - Internal Speakers - * Config=0x90170110 (Fixed,Int; Speaker,Other Analog; Unknown,nJD; DA,Seq) - */ - AZALIA_PIN_CFG(0x0, 0x0D, 0x90170110), + /* Not connected: N/A,N/A; Other,Unknown; Unknown,JD; DA,Seq */ + AZALIA_PIN_CFG(0x0, 0x0c, 0x40f000f0), -/* NID 0x0F - Not connected - * Config=0x40F000F0 - */ - AZALIA_PIN_CFG(0x0, 0x0F, 0x40F000F0), + /* Internal Speakers Fixed,Int; Speaker,Other Analog; Unknown,nJD; DA,Seq */ + AZALIA_PIN_CFG(0x0, 0x0d, 0x90170110), -/* NID 0x11 - Internal Microphone - * Config=0xD5A30140 (Fixed internal,Top; Mic In,ATIPI; Unknown,nJD; DA,Seq) - */ - AZALIA_PIN_CFG(0x0, 0x11, 0xD5A30140), - AZALIA_PIN_CFG(0x0, 0x12, 0x90A60140), + /* Not connected */ + AZALIA_PIN_CFG(0x0, 0x0f, 0x40f000f0), + + /* Internal Microphone: Fixed,Int,Top; Mic In,ATIPI; Unknown,nJD; DA,Seq */ + AZALIA_PIN_CFG(0x0, 0x11, 0xd5a30140), + AZALIA_PIN_CFG(0x0, 0x12, 0x90a60140), AZALIA_PIN_CFG(0x0, 0x14, 0x90170110), AZALIA_PIN_CFG(0x0, 0x15, 0x03211020), - AZALIA_PIN_CFG(0x0, 0x18, 0x03A11830), - AZALIA_PIN_CFG(0x0, 0x19, 0x411111F0), + AZALIA_PIN_CFG(0x0, 0x18, 0x03a11830), + AZALIA_PIN_CFG(0x0, 0x19, 0x411111f0), 0x01970804, 0x01870803, 0x01470740, 0x00970600, - AZALIA_PIN_CFG(0x0, 0x1A, 0x411111F0), - AZALIA_PIN_CFG(0x0, 0x1D, 0x40138205), - AZALIA_PIN_CFG(0x0, 0x1E, 0x411111F0), + AZALIA_PIN_CFG(0x0, 0x1a, 0x411111f0), + AZALIA_PIN_CFG(0x0, 0x1d, 0x40138205), + AZALIA_PIN_CFG(0x0, 0x1e, 0x411111f0), /* Misc entries */ 0x00370600, 0x00270600, - 0x00B707C0, /* Enable PortB as Output with HP amp */ - 0x00D70740, /* Enable PortD as Output */ - 0x0017A200, /* Disable ClkEn of PortSenseTst */ - 0x0017C621, /* Slave Port - Port A used as microphone input for + 0x00b707C0, /* Enable PortB as Output with HP amp */ + 0x00d70740, /* Enable PortD as Output */ + 0x0017a200, /* Disable ClkEn of PortSenseTst */ + 0x0017c621, /* Slave Port - Port A used as microphone input for combo Jack Master Port - Port B used for Jack Presence Detect Enable Combo Jack Detection */ - 0x0017A208, /* Enable ClkEn of PortSenseTst */ + 0x0017a208, /* Enable ClkEn of PortSenseTst */ 0x00170500, /* Set power state to D0 */ - /* --- Next Codec --- */ - -/* Vendor Name : Intel - * Vendor ID : 0x80862806 - * Subsystem ID : 0x80860101 - * Revision ID : 0x100000 - */ - /* coreboot specific header */ - 0x80862806, // Codec Vendor / Device ID: Intel PantherPoint HDMI - 0x80860101, // Subsystem ID - 4, // Number of IDs - - /* NID 0x01, HDA Codec Subsystem ID Verb Table: 0x80860101 */ + /* --- Codec #3 --- */ + 0x80862806, /* Codec Vendor / Device ID: Intel PantherPoint HDMI */ + 0x80860101, /* Subsystem ID */ + 4, /* Number of 4 dword sets */ AZALIA_SUBVENDOR(0x3, 0x80860101), - - /* Pin Complex (NID 0x05) Digital Out at Int HDMI */ AZALIA_PIN_CFG(0x3, 0x05, 0x18560010), - - /* Pin Complex (NID 0x06) Digital Out at Int HDMI */ AZALIA_PIN_CFG(0x3, 0x06, 0x18560020), - - /* Pin Complex (NID 0x07) Digital Out at Int HDMI */ AZALIA_PIN_CFG(0x3, 0x07, 0x18560030) }; diff --git a/src/mainboard/lenovo/t60/hda_verb.c b/src/mainboard/lenovo/t60/hda_verb.c index 216696b22b..22eec0a798 100644 --- a/src/mainboard/lenovo/t60/hda_verb.c +++ b/src/mainboard/lenovo/t60/hda_verb.c @@ -14,12 +14,10 @@ #include const u32 cim_verb_data[] = { - 0x11d41981, /* Codec Vendor / Device ID: Analog Devices AD1981 */ - 0x17aa2025, /* Subsystem ID */ - 11, /* Number of 4 dword sets */ - + 0x11d41981, /* Codec Vendor / Device ID: Analog Devices AD1981 */ + 0x17aa2025, /* Subsystem ID */ + 11, /* Number of 4 dword sets */ AZALIA_SUBVENDOR(0x0, 0x17aa2025), - AZALIA_PIN_CFG(0, 0x05, 0xc3014110), AZALIA_PIN_CFG(0, 0x06, 0x4221401f), AZALIA_PIN_CFG(0, 0x07, 0x591311f0), diff --git a/src/mainboard/lenovo/x1_carbon_gen1/hda_verb.c b/src/mainboard/lenovo/x1_carbon_gen1/hda_verb.c index 1946286cff..8ea325805c 100644 --- a/src/mainboard/lenovo/x1_carbon_gen1/hda_verb.c +++ b/src/mainboard/lenovo/x1_carbon_gen1/hda_verb.c @@ -17,56 +17,27 @@ #include const u32 cim_verb_data[] = { - 0x10ec0269, /* Codec Vendor / Device ID: Realtek */ - 0x17aa21f9, /* Subsystem ID */ - - 11, /* Number of 4 dword sets */ - /* NID 0x01: Subsystem ID. */ + 0x10ec0269, /* Codec Vendor / Device ID: Realtek */ + 0x17aa21f9, /* Subsystem ID */ + 11, /* Number of 4 dword sets */ AZALIA_SUBVENDOR(0x0, 0x17aa21f9), - - /* NID 0x12. */ AZALIA_PIN_CFG(0x0, 0x12, 0x90a60140), - - /* NID 0x14. */ AZALIA_PIN_CFG(0x0, 0x14, 0x90170110), - - /* NID 0x15. */ AZALIA_PIN_CFG(0x0, 0x15, 0x03211020), - - /* NID 0x17. */ AZALIA_PIN_CFG(0x0, 0x17, 0x411111f0), - - /* NID 0x18. */ AZALIA_PIN_CFG(0x0, 0x18, 0x03a11830), - - /* NID 0x19. */ AZALIA_PIN_CFG(0x0, 0x19, 0x411111f0), - - /* NID 0x1a. */ AZALIA_PIN_CFG(0x0, 0x1a, 0x411111f0), - - /* NID 0x1b. */ AZALIA_PIN_CFG(0x0, 0x1b, 0x411111f0), - - /* NID 0x1d. */ AZALIA_PIN_CFG(0x0, 0x1d, 0x40138205), - - /* NID 0x1e. */ AZALIA_PIN_CFG(0x0, 0x1e, 0x411111f0), - 0x80862806, /* Codec Vendor / Device ID: Intel */ - 0x80860101, /* Subsystem ID */ - 4, /* Number of 4 dword sets */ - /* NID 0x01: Subsystem ID. */ + 0x80862806, /* Codec Vendor / Device ID: Intel */ + 0x80860101, /* Subsystem ID */ + 4, /* Number of 4 dword sets */ AZALIA_SUBVENDOR(0x3, 0x80860101), - - /* Pin Complex (NID 0x05) Digital Out at Int HDMI */ AZALIA_PIN_CFG(0x3, 0x05, 0x18560010), - - /* Pin Complex (NID 0x06) Digital Out at Int HDMI */ AZALIA_PIN_CFG(0x3, 0x06, 0x58560020), - - /* Pin Complex (NID 0x07) Digital Out at Int HDMI */ AZALIA_PIN_CFG(0x3, 0x07, 0x58560030), }; diff --git a/src/mainboard/lenovo/x201/hda_verb.c b/src/mainboard/lenovo/x201/hda_verb.c index 25a87f57f2..ee12d3adcd 100644 --- a/src/mainboard/lenovo/x201/hda_verb.c +++ b/src/mainboard/lenovo/x201/hda_verb.c @@ -17,58 +17,27 @@ #include const u32 cim_verb_data[] = { - /* coreboot specific header */ - 0x14F15069, /* Codec Vendor / Device ID: Conexant CX20585 */ - 0x17AA2155, /* Subsystem ID */ + 0x14f15069, /* Codec Vendor / Device ID: Conexant CX20585 */ + 0x17aa2155, /* Subsystem ID */ 11, /* Number of 4 dword sets */ - - /* NID 0x01: Subsystem ID. */ - AZALIA_SUBVENDOR(0x0, 0x17AA2155), - - /* NID 0x19: Headphone jack. */ - AZALIA_PIN_CFG(0x0, 0x19, 0x042140F0), - - /* NID 0x1A: Dock mic jack. */ - AZALIA_PIN_CFG(0x0, 0x1A, 0x61A190F0), - - /* NID 0x1B: Mic jack. */ - AZALIA_PIN_CFG(0x0, 0x1B, 0x04A190F0), - - /* NID 0x1C: Dock headphone jack. */ - AZALIA_PIN_CFG(0x0, 0x1C, 0x612140F0), - - /* NID 0x1D: EAPD detect. */ - AZALIA_PIN_CFG(0x0, 0x1D, 0x601700F0), - - /* NID 0x1E */ - AZALIA_PIN_CFG(0x0, 0x1E, 0x40F001F0), - - /* NID 0x1F */ - AZALIA_PIN_CFG(0x0, 0x1F, 0x901701F0), - - /* NID 0x20 */ - AZALIA_PIN_CFG(0x0, 0x20, 0x40F001F0), - - /* NID 0x22 */ - AZALIA_PIN_CFG(0x0, 0x22, 0x40F001F0), - - /* NID 0x23: Internal mic boost volume. */ - AZALIA_PIN_CFG(0x0, 0x23, 0x90A601F0), + AZALIA_SUBVENDOR(0x0, 0x17aa2155), + AZALIA_PIN_CFG(0x0, 0x19, 0x042140f0), /* Headphone jack */ + AZALIA_PIN_CFG(0x0, 0x1a, 0x61a190f0), /* Dock mic jack */ + AZALIA_PIN_CFG(0x0, 0x1b, 0x04a190f0), /* Mic jack */ + AZALIA_PIN_CFG(0x0, 0x1c, 0x612140f0), /* Dock headphone jack */ + AZALIA_PIN_CFG(0x0, 0x1d, 0x601700f0), /* EAPD detect */ + AZALIA_PIN_CFG(0x0, 0x1e, 0x40f001f0), + AZALIA_PIN_CFG(0x0, 0x1f, 0x901701f0), + AZALIA_PIN_CFG(0x0, 0x20, 0x40f001f0), + AZALIA_PIN_CFG(0x0, 0x22, 0x40f001f0), + AZALIA_PIN_CFG(0x0, 0x23, 0x90a601f0), /* Internal mic boost volume */ 0x80862804, /* Codec Vendor / Device ID: Intel Ibexpeak HDMI. */ 0x17aa21b5, /* Subsystem ID */ 4, /* Number of 4 dword sets */ - - /* NID 0x01, HDA Codec Subsystem ID Verb Table: 0x17aa21b5 */ - AZALIA_SUBVENDOR(0x3, 0x17AA21B5), - - /* NID 0x04. */ + AZALIA_SUBVENDOR(0x3, 0x17aa21b5), AZALIA_PIN_CFG(0x3, 0x04, 0x58560010), - - /* NID 0x05. */ AZALIA_PIN_CFG(0x3, 0x05, 0x18560020), - - /* NID 0x06. */ AZALIA_PIN_CFG(0x3, 0x06, 0x58560030), }; diff --git a/src/mainboard/lenovo/x220/hda_verb.c b/src/mainboard/lenovo/x220/hda_verb.c index b7b670d77a..00751c4d6f 100644 --- a/src/mainboard/lenovo/x220/hda_verb.c +++ b/src/mainboard/lenovo/x220/hda_verb.c @@ -14,76 +14,52 @@ * GNU General Public License for more details. */ -/* Vendor Name : Conexant - * Vendor ID : 0x14f1506e - * Subsystem ID : 0x17aa21db - * Revision ID : 0x100002 - */ - - -#include - -const u32 cim_verb_data[] = { - /* coreboot specific header */ - 0x14f1506e, // Codec Vendor / Device ID: Conexant CX20590 - 0x17aa21db, // Subsystem ID - 13, // Number of 4 dword sets - /* Bits 31:28 - Codec Address */ /* Bits 27:20 - NID */ /* Bits 19:8 - Verb ID */ /* Bits 7:0 - Payload */ -/* NID 0x01 - NodeInfo */ - AZALIA_SUBVENDOR(0x0, 0x17AA21DB), +#include + +const u32 cim_verb_data[] = { + /* --- Codec #0 --- */ + 0x14f1506e, /* Codec Vendor / Device ID: Conexant CX20590 */ + 0x17aa21db, /* Subsystem ID */ + 13, /* Number of 4 dword sets */ + AZALIA_SUBVENDOR(0x0, 0x17aa21db), AZALIA_PIN_CFG(0x0, 0x19, 0x04211040), - AZALIA_PIN_CFG(0x0, 0x1A, 0x61A19050), - AZALIA_PIN_CFG(0x0, 0x1B, 0x04A11060), - AZALIA_PIN_CFG(0x0, 0x1C, 0x6121401F), - AZALIA_PIN_CFG(0x0, 0x1D, 0x40F001F0), - AZALIA_PIN_CFG(0x0, 0x1E, 0x40F001F0), - AZALIA_PIN_CFG(0x0, 0x1F, 0x90170110), - AZALIA_PIN_CFG(0x0, 0x20, 0x40F001F0), - AZALIA_PIN_CFG(0x0, 0x22, 0x40F001F0), - AZALIA_PIN_CFG(0x0, 0x23, 0x90A60170), + AZALIA_PIN_CFG(0x0, 0x1a, 0x61a19050), + AZALIA_PIN_CFG(0x0, 0x1b, 0x04a11060), + AZALIA_PIN_CFG(0x0, 0x1c, 0x6121401f), + AZALIA_PIN_CFG(0x0, 0x1d, 0x40f001f0), + AZALIA_PIN_CFG(0x0, 0x1e, 0x40f001f0), + AZALIA_PIN_CFG(0x0, 0x1f, 0x90170110), + AZALIA_PIN_CFG(0x0, 0x20, 0x40f001f0), + AZALIA_PIN_CFG(0x0, 0x22, 0x40f001f0), + AZALIA_PIN_CFG(0x0, 0x23, 0x90a60170), /* Misc entries */ - 0x00B707C0, /* Enable PortB as Output with HP amp */ - 0x00D70740, /* Enable PortD as Output */ - 0x0017A200, /* Disable ClkEn of PortSenseTst */ - 0x0017C621, /* Slave Port - Port A used as microphone input for + 0x00b707C0, /* Enable PortB as Output with HP amp */ + 0x00d70740, /* Enable PortD as Output */ + 0x0017a200, /* Disable ClkEn of PortSenseTst */ + 0x0017c621, /* Slave Port - Port A used as microphone input for combo Jack Master Port - Port B used for Jack Presence Detect Enable Combo Jack Detection */ - 0x0017A208, /* Enable ClkEn of PortSenseTst */ + 0x0017a208, /* Enable ClkEn of PortSenseTst */ 0x00170500, /* Set power state to D0 */ 0x00170500, /* Padding */ 0x00170500, /* Padding */ - /* --- Next Codec --- */ - -/* Vendor Name : Intel - * Vendor ID : 0x80862806 - * Subsystem ID : 0x80860101 - * Revision ID : 0x100000 - */ - /* coreboot specific header */ - 0x80862805, // Codec Vendor / Device ID: Intel PantherPoint HDMI - 0x80860101, // Subsystem ID - 4, // Number of IDs - - /* NID 0x01, HDA Codec Subsystem ID Verb Table: 0x80860101 */ + /* --- Codec #3 --- */ + 0x80862806, /* Codec Vendor / Device ID: Intel PantherPoint HDMI */ + 0x80860101, /* Subsystem ID */ + 4, /* Number of 4 dword sets */ AZALIA_SUBVENDOR(0x3, 0x80860101), - - /* Pin Complex (NID 0x05) Digital Out at Int HDMI */ AZALIA_PIN_CFG(0x3, 0x05, 0x18560010), - - /* Pin Complex (NID 0x06) Digital Out at Int HDMI */ AZALIA_PIN_CFG(0x3, 0x06, 0x18560020), - - /* Pin Complex (NID 0x07) Digital Out at Int HDMI */ - AZALIA_PIN_CFG(0x3, 0x07, 0x18560030) + AZALIA_PIN_CFG(0x3, 0x07, 0x18560030), }; const u32 pc_beep_verbs[] = { diff --git a/src/mainboard/lenovo/x230/hda_verb.c b/src/mainboard/lenovo/x230/hda_verb.c index 0393ff50a6..ff1a2dd153 100644 --- a/src/mainboard/lenovo/x230/hda_verb.c +++ b/src/mainboard/lenovo/x230/hda_verb.c @@ -14,67 +14,45 @@ * GNU General Public License for more details. */ -/* Vendor Name : IDT - * Vendor ID : 0x10ec0269 - * Subsystem ID : 0x17aa21fa - * Revision ID : 0x100303 - */ - - -#include - -const u32 cim_verb_data[] = { - /* coreboot specific header */ - 0x10ec0269, // Codec Vendor / Device ID: Realtek ALC269VC - 0x17aa21fa, // Subsystem ID - 19, // Number of 4 dword sets - /* Bits 31:28 - Codec Address */ /* Bits 27:20 - NID */ /* Bits 19:8 - Verb ID */ /* Bits 7:0 - Payload */ -/* NID 0x01 - NodeInfo */ - AZALIA_SUBVENDOR(0x0, 0x17AA21FA), +#include -/* NID 0x0A - External Microphone Connector - * Config=0x04A11020 (External,Right; MicIn,3.5mm; Black,JD; DA,Seq) - */ - AZALIA_PIN_CFG(0x0, 0x0A, 0x04A11020), +const u32 cim_verb_data[] = { + /* --- Codec #0 --- */ + 0x10ec0269, /* Codec Vendor / Device ID: Realtek ALC269VC */ + 0x17aa21fa, /* Subsystem ID */ + 19, /* Number of 4 dword sets */ + AZALIA_SUBVENDOR(0x0, 0x17aa21fa), -/* NID 0x0B - Headphone Connector - * Config=0x0421101F (External,Right; HP,3.5mm; Black,JD; DA,Seq) - */ - AZALIA_PIN_CFG(0x0, 0x0B, 0x0421101F), + /* Ext. Microphone Connector: External,Right; MicIn,3.5mm; Black,JD; DA,Seq */ + AZALIA_PIN_CFG(0x0, 0x0a, 0x04a11020), -/* NID 0x0C - Not connected - * Config=0x40F000F0 (N/A,N/A; Other,Unknown; Unknown,JD; DA,Seq) - */ - AZALIA_PIN_CFG(0x0, 0x0C, 0x40F000F0), + /* Headphones Connector: External,Right; HP,3.5mm; Black,JD; DA,Seq */ + AZALIA_PIN_CFG(0x0, 0x0b, 0x0421101f), -/* NID 0x0D - Internal Speakers - * Config=0x90170110 (Fixed,Int; Speaker,Other Analog; Unknown,nJD; DA,Seq) - */ - AZALIA_PIN_CFG(0x0, 0x0D, 0x90170110), + /* Not connected: N/A,N/A; Other,Unknown; Unknown,JD; DA,Seq */ + AZALIA_PIN_CFG(0x0, 0x0c, 0x40f000f0), -/* NID 0x0F - Not connected - * Config=0x40F000F0 - */ - AZALIA_PIN_CFG(0x0, 0x0F, 0x40F000F0), + /* Internal Speakers Fixed,Int; Speaker,Other Analog; Unknown,nJD; DA,Seq */ + AZALIA_PIN_CFG(0x0, 0x0d, 0x90170110), -/* NID 0x11 - Internal Microphone - * Config=0xD5A30140 (Fixed internal,Top; Mic In,ATIPI; Unknown,nJD; DA,Seq) - */ - AZALIA_PIN_CFG(0x0, 0x11, 0xD5A30140), - AZALIA_PIN_CFG(0x0, 0x12, 0x90A60140), + /* Not connected */ + AZALIA_PIN_CFG(0x0, 0x0f, 0x40f000f0), + + /* Internal Microphone: Fixed,Int,Top; Mic In,ATIPI; Unknown,nJD; DA,Seq */ + AZALIA_PIN_CFG(0x0, 0x11, 0xd5a30140), + AZALIA_PIN_CFG(0x0, 0x12, 0x90a60140), AZALIA_PIN_CFG(0x0, 0x14, 0x90170110), AZALIA_PIN_CFG(0x0, 0x15, 0x03211020), - AZALIA_PIN_CFG(0x0, 0x18, 0x03A11830), - AZALIA_PIN_CFG(0x0, 0x19, 0x411111F0), - - AZALIA_PIN_CFG(0x0, 0x1A, 0x411111F0), - AZALIA_PIN_CFG(0x0, 0x1D, 0x40138205), - AZALIA_PIN_CFG(0x0, 0x1E, 0x411111F0), + AZALIA_PIN_CFG(0x0, 0x18, 0x03a11830), + AZALIA_PIN_CFG(0x0, 0x19, 0x411111f0), + AZALIA_PIN_CFG(0x0, 0x1a, 0x411111f0), + AZALIA_PIN_CFG(0x0, 0x1d, 0x40138205), + AZALIA_PIN_CFG(0x0, 0x1e, 0x411111f0), /* Misc entries */ 0x01970804, @@ -84,11 +62,10 @@ const u32 cim_verb_data[] = { 0x00370680, 0x00270680, - 0x01470C02, - 0x01570C02, - - /* ALC coefficients. */ + 0x01470c02, + 0x01570c02, + /* ALC coefficients. */ /* 08 */ 0x02050008, 0x02040700, @@ -102,29 +79,14 @@ const u32 cim_verb_data[] = { 0x01870724, /* Enable Vrefout for mic */ 0x00170500, /* Set power state to D0 */ - /* --- Next Codec --- */ - -/* Vendor Name : Intel - * Vendor ID : 0x80862806 - * Subsystem ID : 0x80860101 - * Revision ID : 0x100000 - */ - /* coreboot specific header */ - 0x80862806, // Codec Vendor / Device ID: Intel PantherPoint HDMI - 0x80860101, // Subsystem ID - 4, // Number of IDs - - /* NID 0x01, HDA Codec Subsystem ID Verb Table: 0x80860101 */ + /* --- Codec #3 --- */ + 0x80862806, /* Codec Vendor / Device ID: Intel PantherPoint HDMI */ + 0x80860101, /* Subsystem ID */ + 4, /* Number of 4 dword sets */ AZALIA_SUBVENDOR(0x3, 0x80860101), - - /* Pin Complex (NID 0x05) Digital Out at Int HDMI */ AZALIA_PIN_CFG(0x3, 0x05, 0x18560010), - - /* Pin Complex (NID 0x06) Digital Out at Int HDMI */ AZALIA_PIN_CFG(0x3, 0x06, 0x18560020), - - /* Pin Complex (NID 0x07) Digital Out at Int HDMI */ - AZALIA_PIN_CFG(0x3, 0x07, 0x18560030) + AZALIA_PIN_CFG(0x3, 0x07, 0x18560030), }; const u32 pc_beep_verbs[] = { diff --git a/src/mainboard/lenovo/x60/hda_verb.c b/src/mainboard/lenovo/x60/hda_verb.c index 216696b22b..071249897c 100644 --- a/src/mainboard/lenovo/x60/hda_verb.c +++ b/src/mainboard/lenovo/x60/hda_verb.c @@ -14,9 +14,9 @@ #include const u32 cim_verb_data[] = { - 0x11d41981, /* Codec Vendor / Device ID: Analog Devices AD1981 */ - 0x17aa2025, /* Subsystem ID */ - 11, /* Number of 4 dword sets */ + 0x11d41981, /* Codec Vendor / Device ID: Analog Devices AD1981 */ + 0x17aa2025, /* Subsystem ID */ + 11, /* Number of 4 dword sets */ AZALIA_SUBVENDOR(0x0, 0x17aa2025), diff --git a/src/mainboard/msi/ms7707/hda_verb.c b/src/mainboard/msi/ms7707/hda_verb.c index 7ff2bee168..0895e29055 100644 --- a/src/mainboard/msi/ms7707/hda_verb.c +++ b/src/mainboard/msi/ms7707/hda_verb.c @@ -18,53 +18,23 @@ #include const u32 cim_verb_data[] = { - 0x10ec0887, /* Codec Vendor / Device ID: Realtek */ - 0x14627707, /* Subsystem ID */ - - 15, /* Number of 4 dword sets */ - /* NID 0x01: Subsystem ID. */ + 0x10ec0887, /* Codec Vendor / Device ID: Realtek */ + 0x14627707, /* Subsystem ID */ + 15, /* Number of 4 dword sets */ AZALIA_SUBVENDOR(0x0, 0x14627707), - - /* NID 0x11. */ AZALIA_PIN_CFG(0x0, 0x11, 0x411111f0), - - /* NID 0x12. */ AZALIA_PIN_CFG(0x0, 0x12, 0x411111f0), - - /* NID 0x14. */ AZALIA_PIN_CFG(0x0, 0x14, 0x01014410), - - /* NID 0x15. */ AZALIA_PIN_CFG(0x0, 0x15, 0x01011412), - - /* NID 0x16. */ AZALIA_PIN_CFG(0x0, 0x16, 0x01016411), - - /* NID 0x17. */ AZALIA_PIN_CFG(0x0, 0x17, 0x01012414), - - /* NID 0x18. */ AZALIA_PIN_CFG(0x0, 0x18, 0x01813c40), - - /* NID 0x19. */ AZALIA_PIN_CFG(0x0, 0x19, 0x02a19c50), - - /* NID 0x1a. */ AZALIA_PIN_CFG(0x0, 0x1a, 0x411111f0), - - /* NID 0x1b. */ AZALIA_PIN_CFG(0x0, 0x1b, 0x02214c20), - - /* NID 0x1c. */ AZALIA_PIN_CFG(0x0, 0x1c, 0x411111f0), - - /* NID 0x1d. */ AZALIA_PIN_CFG(0x0, 0x1d, 0x411111f0), - - /* NID 0x1e. */ AZALIA_PIN_CFG(0x0, 0x1e, 0x01454130), - - /* NID 0x1f. */ AZALIA_PIN_CFG(0x0, 0x1f, 0x411111f0), }; diff --git a/src/mainboard/packardbell/ms2290/hda_verb.c b/src/mainboard/packardbell/ms2290/hda_verb.c index d458cd6eed..4f78b89917 100644 --- a/src/mainboard/packardbell/ms2290/hda_verb.c +++ b/src/mainboard/packardbell/ms2290/hda_verb.c @@ -17,43 +17,22 @@ #include const u32 cim_verb_data[] = { - /* coreboot specific header */ 0x10ec0272, /* Codec Vendor / Device ID: Realtek ALC272X */ 0x10250379, /* Subsystem ID */ 6, /* Number of 4 dword sets */ - - /* NID 0x01: Subsystem ID. */ AZALIA_SUBVENDOR(0x0, 0x10250379), - - /* NID 0x14. */ AZALIA_PIN_CFG(0x0, 0x14, 0x99130110), + AZALIA_PIN_CFG(0x0, 0x18, 0x03a11830), + AZALIA_PIN_CFG(0x0, 0x19, 0x99a30920), + AZALIA_PIN_CFG(0x0, 0x1d, 0x4017992d), + AZALIA_PIN_CFG(0x0, 0x21, 0x0321101f), - /* NID 0x18. */ - AZALIA_PIN_CFG(0x0, 0x18, 0x03A11830), - - /* NID 0x19. */ - AZALIA_PIN_CFG(0x0, 0x19, 0x99A30920), - - /* NID 0x1D. */ - AZALIA_PIN_CFG(0x0, 0x1D, 0x4017992D), - - /* NID 0x21. */ - AZALIA_PIN_CFG(0x0, 0x21, 0x0321101F), - - 0x80862804, /* Codec Vendor / Device ID: Intel Ibexpeak HDMI. */ + 0x80862804, /* Codec Vendor / Device ID: Intel Ibexpeak HDMI */ 0x80860101, /* Subsystem ID */ 4, /* Number of 4 dword sets */ - - /* NID 0x01, HDA Codec Subsystem ID Verb Table: 0x17aa21b5 */ AZALIA_SUBVENDOR(0x3, 0x80860101), - - /* NID 0x04. */ AZALIA_PIN_CFG(0x3, 0x04, 0x18560010), - - /* NID 0x05. */ AZALIA_PIN_CFG(0x3, 0x05, 0x58560020), - - /* NID 0x06. */ AZALIA_PIN_CFG(0x3, 0x06, 0x58560030), }; diff --git a/src/mainboard/sapphire/pureplatinumh61/hda_verb.c b/src/mainboard/sapphire/pureplatinumh61/hda_verb.c index 9be242e501..23710040a0 100644 --- a/src/mainboard/sapphire/pureplatinumh61/hda_verb.c +++ b/src/mainboard/sapphire/pureplatinumh61/hda_verb.c @@ -17,68 +17,31 @@ #include const u32 cim_verb_data[] = { - 0x10ec0892, /* Codec Vendor / Device ID: Realtek */ - 0x10ec0000, /* Subsystem ID */ - - 15, /* Number of 4 dword sets */ - /* NID 0x01: Subsystem ID. */ + 0x10ec0892, /* Codec Vendor / Device ID: Realtek */ + 0x10ec0000, /* Subsystem ID */ + 15, /* Number of 4 dword sets */ AZALIA_SUBVENDOR(0x2, 0x10ec0000), - - /* NID 0x11. */ AZALIA_PIN_CFG(0x2, 0x11, 0x411111f0), - - /* NID 0x12. */ AZALIA_PIN_CFG(0x2, 0x12, 0x411111f0), - - /* NID 0x14. */ AZALIA_PIN_CFG(0x2, 0x14, 0x01014c10), - - /* NID 0x15. */ AZALIA_PIN_CFG(0x2, 0x15, 0x01011c12), - - /* NID 0x16. */ AZALIA_PIN_CFG(0x2, 0x16, 0x01016c11), - - /* NID 0x17. */ AZALIA_PIN_CFG(0x2, 0x17, 0x01012c14), - - /* NID 0x18. */ AZALIA_PIN_CFG(0x2, 0x18, 0x01a19c40), - - /* NID 0x19. */ AZALIA_PIN_CFG(0x2, 0x19, 0x02a19c50), - - /* NID 0x1a. */ AZALIA_PIN_CFG(0x2, 0x1a, 0x01813c4f), - - /* NID 0x1b. */ AZALIA_PIN_CFG(0x2, 0x1b, 0x0321403f), - - /* NID 0x1c. */ AZALIA_PIN_CFG(0x2, 0x1c, 0x411111f0), - - /* NID 0x1d. */ AZALIA_PIN_CFG(0x2, 0x1d, 0x4005e601), - - /* NID 0x1e. */ AZALIA_PIN_CFG(0x2, 0x1e, 0x0145e130), - - /* NID 0x1f. */ AZALIA_PIN_CFG(0x2, 0x1f, 0x411111f0), - 0x80862805, /* Codec Vendor / Device ID: Intel */ - 0x80860101, /* Subsystem ID */ - 4, /* Number of 4 dword sets */ - /* NID 0x01: Subsystem ID. */ + 0x80862805, /* Codec Vendor / Device ID: Intel */ + 0x80860101, /* Subsystem ID */ + 4, /* Number of 4 dword sets */ AZALIA_SUBVENDOR(0x3, 0x80860101), - - /* NID 0x05. */ AZALIA_PIN_CFG(0x3, 0x05, 0x58560010), - - /* NID 0x06. */ AZALIA_PIN_CFG(0x3, 0x06, 0x18560020), - - /* NID 0x07. */ AZALIA_PIN_CFG(0x3, 0x07, 0x18560030), }; From 4240e3298001f978e37477be86875d3bb6e19712 Mon Sep 17 00:00:00 2001 From: Peichao Wang Date: Thu, 5 Dec 2019 13:56:17 +0800 Subject: [PATCH 0653/1242] mb/google/hatch: Add new SKU ID 3 and 4 1. SKU ID 1 and 3 for eMMC 2. SKU ID 2 and 4 for SSD BUG=b:144815890 BRANCH=firmware-hatch-12672.B TEST=FW_NAME="akemi" emerge-hatch coreboot chromeos-bootimage Signed-off-by: Peichao Wang Change-Id: I25f0c4142be024ba55f671491601d1f6ec26d68a Reviewed-on: https://review.coreboot.org/c/coreboot/+/37498 Reviewed-by: Paul Fagerburg Reviewed-by: Philip Chen Tested-by: build bot (Jenkins) --- src/mainboard/google/hatch/variants/akemi/gpio.c | 2 +- src/mainboard/google/hatch/variants/akemi/variant.c | 8 ++++---- 2 files changed, 5 insertions(+), 5 deletions(-) diff --git a/src/mainboard/google/hatch/variants/akemi/gpio.c b/src/mainboard/google/hatch/variants/akemi/gpio.c index 4be3c34722..0780ddb97a 100644 --- a/src/mainboard/google/hatch/variants/akemi/gpio.c +++ b/src/mainboard/google/hatch/variants/akemi/gpio.c @@ -164,7 +164,7 @@ const struct pad_config *override_gpio_table(size_t *num) { uint32_t sku_id = get_board_sku(); /* For SSD SKU */ - if (sku_id == 2) { + if ((sku_id == 2) || (sku_id == 4)) { *num = ARRAY_SIZE(ssd_sku_gpio_table); return ssd_sku_gpio_table; } diff --git a/src/mainboard/google/hatch/variants/akemi/variant.c b/src/mainboard/google/hatch/variants/akemi/variant.c index c648a527f5..8440b5c2d3 100644 --- a/src/mainboard/google/hatch/variants/akemi/variant.c +++ b/src/mainboard/google/hatch/variants/akemi/variant.c @@ -27,17 +27,17 @@ void variant_devtree_update(void) emmc_host = pcidev_path_on_root(PCH_DEVFN_EMMC); ssd_host = pcidev_path_on_root(PCH_DEVFN_SATA); - /* SKU ID 2 doesn't have a eMMC device, hence disable it. */ + /* SKU ID 2 and 4 do not have eMMC, hence disable it. */ sku_id = get_board_sku(); - if (sku_id == 2) { + if ((sku_id == 2) || (sku_id == 4)) { if (emmc_host == NULL) return; emmc_host->enabled = 0; cfg->ScsEmmcHs400Enabled = 0; } - /* SKU ID 1 doesn't have a SSD device, hence disable it. */ - if (sku_id == 1) { + /* SKU ID 1 and 3 do not have SSD, hence disable it. */ + if ((sku_id == 1) || (sku_id == 3)) { if (ssd_host == NULL) return; ssd_host->enabled = 0; From 83b2740ba7d9503100798a0771818f0e58c46c53 Mon Sep 17 00:00:00 2001 From: Huayang Duan Date: Mon, 18 Nov 2019 09:45:22 +0800 Subject: [PATCH 0654/1242] soc/mediatek/mt8183: skip fast calibration for high frequency of TX RX window For low frequency (e.g., 1600 or 2400 Mbps) we can do fast calibration for TX and RX window. However, for high frequency (e.g., 3200 or 3600 Mbps) a full calibration is needed. BUG=b:80501386,b:142358843 BRANCH=kukui TEST=Boots correctly on Kukui Signed-off-by: Huayang Duan Change-Id: I00d563ece4cf91ef5e8e12b6cf7f777849375a24 Reviewed-on: https://review.coreboot.org/c/coreboot/+/36921 Reviewed-by: Hung-Te Lin Reviewed-by: Yu-Ping Wu Tested-by: build bot (Jenkins) --- src/soc/mediatek/mt8183/dramc_pi_calibration_api.c | 9 +++++---- 1 file changed, 5 insertions(+), 4 deletions(-) diff --git a/src/soc/mediatek/mt8183/dramc_pi_calibration_api.c b/src/soc/mediatek/mt8183/dramc_pi_calibration_api.c index cd9f328ae6..8c17d84df0 100644 --- a/src/soc/mediatek/mt8183/dramc_pi_calibration_api.c +++ b/src/soc/mediatek/mt8183/dramc_pi_calibration_api.c @@ -1788,8 +1788,9 @@ static u8 dramc_window_perbit_cal(u8 chn, u8 rank, u8 freq_group, u8 fsp = get_freq_fsq(freq_group); u8 vref_range = !fsp; - bool bypass_tx = !fsp; + bool bypass_tx_rx = !fsp; + dramc_dbg("bypass TX RX window: %s\n", bypass_tx_rx ? "Yes" : "No"); dramc_get_vref_prop(rank, type, fsp, &vref_scan_enable, &vref_begin, &vref_end); dramc_get_dly_range(chn, rank, type, freq_group, dq_precal_result, @@ -1826,9 +1827,9 @@ static u8 dramc_window_perbit_cal(u8 chn, u8 rank, u8 freq_group, vref_step = 2; } - if (fast_calib && bypass_tx && + if (fast_calib && bypass_tx_rx && (type == TX_WIN_DQ_ONLY || type == TX_WIN_DQ_DQM)) { - dramc_set_tx_best_dly(chn, rank, true, vref_dly.perbit_dly, + dramc_set_tx_best_dly(chn, rank, bypass_tx_rx, vref_dly.perbit_dly, type, freq_group, dq_precal_result, dly_cell_unit, params, fast_calib); @@ -1872,7 +1873,7 @@ static u8 dramc_window_perbit_cal(u8 chn, u8 rank, u8 freq_group, RX_DQ, FIRST_DQ_DELAY); } - if (fast_calib && + if (fast_calib && bypass_tx_rx && (type == RX_WIN_RD_DQC || type == RX_WIN_TEST_ENG)) { dramc_dbg("bypass RX params\n"); for (size_t bit = 0; bit < DQ_DATA_WIDTH; bit++) { From 2cd02610ee35eedc63a27c3fd1460258c273329a Mon Sep 17 00:00:00 2001 From: Peichao Wang Date: Fri, 6 Dec 2019 10:33:57 +0800 Subject: [PATCH 0655/1242] mb/google/hatch/variant/akemi: Increase Goodix touch screen reset delay time Confirmed with Goodix team, so increase reset delay time from 120ms to 150ms. BUG=b:144267684 TEST=FW_NAME="akemi" emerge-hatch coreboot chromeos-ec chromeos-bootimage Signed-off-by: Peichao.Wang Change-Id: I4ff95ac89314fc031620ca28e4f6e6e26cdef3f9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/37544 Reviewed-by: Tim Wawrzynczak Tested-by: build bot (Jenkins) --- src/mainboard/google/hatch/variants/akemi/overridetree.cb | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/mainboard/google/hatch/variants/akemi/overridetree.cb b/src/mainboard/google/hatch/variants/akemi/overridetree.cb index da669e4536..de4a903993 100644 --- a/src/mainboard/google/hatch/variants/akemi/overridetree.cb +++ b/src/mainboard/google/hatch/variants/akemi/overridetree.cb @@ -205,7 +205,7 @@ chip soc/intel/cannonlake register "generic.probed" = "1" register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D15)" - register "generic.reset_delay_ms" = "120" + register "generic.reset_delay_ms" = "150" register "generic.reset_off_delay_ms" = "3" register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D9)" From 442fb05acf149a178848931dfe123263e1748c90 Mon Sep 17 00:00:00 2001 From: Elyes HAOUAS Date: Wed, 11 Dec 2019 08:07:55 +0100 Subject: [PATCH 0656/1242] nb/{haswell,i945,sandybridge}: Drop outdated comment 'e7525/northbridge.c' does not exist anymore. Change-Id: I5520760f59a3c6f89afb1360b12bd9763fba562a Signed-off-by: Elyes HAOUAS Reviewed-on: https://review.coreboot.org/c/coreboot/+/37653 Reviewed-by: Frans Hendriks Reviewed-by: Patrick Rudolph Reviewed-by: Mimoja Reviewed-by: Angel Pons Tested-by: build bot (Jenkins) --- src/northbridge/intel/haswell/northbridge.c | 1 - src/northbridge/intel/i945/northbridge.c | 1 - src/northbridge/intel/sandybridge/northbridge.c | 1 - 3 files changed, 3 deletions(-) diff --git a/src/northbridge/intel/haswell/northbridge.c b/src/northbridge/intel/haswell/northbridge.c index c047c39ea7..1efa6603d2 100644 --- a/src/northbridge/intel/haswell/northbridge.c +++ b/src/northbridge/intel/haswell/northbridge.c @@ -92,7 +92,6 @@ static const char *northbridge_acpi_name(const struct device *dev) /* TODO We could determine how many PCIe busses we need in * the bar. For now that number is hardcoded to a max of 64. - * See e7525/northbridge.c for an example. */ static struct device_operations pci_domain_ops = { .read_resources = pci_domain_read_resources, diff --git a/src/northbridge/intel/i945/northbridge.c b/src/northbridge/intel/i945/northbridge.c index dde1b110f4..bcecd8854b 100644 --- a/src/northbridge/intel/i945/northbridge.c +++ b/src/northbridge/intel/i945/northbridge.c @@ -165,7 +165,6 @@ void northbridge_write_smram(u8 smram) /* TODO We could determine how many PCIe busses we need in * the bar. For now that number is hardcoded to a max of 64. - * See e7525/northbridge.c for an example. */ static struct device_operations pci_domain_ops = { .read_resources = mch_domain_read_resources, diff --git a/src/northbridge/intel/sandybridge/northbridge.c b/src/northbridge/intel/sandybridge/northbridge.c index 6337d69020..b34f07d696 100644 --- a/src/northbridge/intel/sandybridge/northbridge.c +++ b/src/northbridge/intel/sandybridge/northbridge.c @@ -258,7 +258,6 @@ static const char *northbridge_acpi_name(const struct device *dev) /* TODO We could determine how many PCIe busses we need in * the bar. For now that number is hardcoded to a max of 64. - * See e7525/northbridge.c for an example. */ static struct device_operations pci_domain_ops = { .read_resources = pci_domain_read_resources, From e077cdbc62c51182408f2164ea6ac8b663cec3dd Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ky=C3=B6sti=20M=C3=A4lkki?= Date: Mon, 26 Aug 2019 14:54:50 +0300 Subject: [PATCH 0657/1242] AGESA, binaryPI: Remove generic device for SPD eeproms MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit These entries have no functional purpose, followup work will disallow chip entries that do not link in the respective driver. Change-Id: Ieab695022d0dd2f2671f9058db97bdd6fb29a10d Signed-off-by: Kyösti Mälkki Reviewed-on: https://review.coreboot.org/c/coreboot/+/35102 Tested-by: build bot (Jenkins) Reviewed-by: Richard Spiegel Reviewed-by: Angel Pons --- src/mainboard/amd/bettong/devicetree.cb | 9 +-------- src/mainboard/amd/gardenia/devicetree.cb | 6 +----- src/mainboard/amd/inagua/devicetree.cb | 9 +-------- src/mainboard/amd/lamar/devicetree.cb | 15 +-------------- src/mainboard/amd/olivehill/devicetree.cb | 9 +-------- src/mainboard/amd/olivehillplus/devicetree.cb | 9 +-------- src/mainboard/amd/padmelon/devicetree.cb | 9 +-------- src/mainboard/amd/parmer/devicetree.cb | 9 +-------- src/mainboard/amd/persimmon/devicetree.cb | 9 +-------- src/mainboard/amd/thatcher/devicetree.cb | 9 +-------- src/mainboard/asrock/e350m1/devicetree.cb | 9 +-------- src/mainboard/asrock/imb-a180/devicetree.cb | 9 +-------- src/mainboard/asus/am1i-a/devicetree.cb | 9 +-------- src/mainboard/asus/f2a85-m/devicetree_f2a85-m.cb | 9 +-------- .../asus/f2a85-m/devicetree_f2a85-m_le.cb | 9 +-------- .../asus/f2a85-m/devicetree_f2a85-m_pro.cb | 15 +-------------- src/mainboard/biostar/am1ml/devicetree.cb | 9 +-------- src/mainboard/elmex/pcm205400/devicetree.cb | 9 +-------- src/mainboard/hp/abm/devicetree.cb | 6 +----- src/mainboard/hp/pavilion_m6_1035dx/devicetree.cb | 9 +-------- src/mainboard/jetway/nf81-t56n-lf/devicetree.cb | 9 +-------- src/mainboard/lenovo/g505s/devicetree.cb | 9 +-------- .../lippert/frontrunner-af/devicetree.cb | 9 +-------- src/mainboard/lippert/toucan-af/devicetree.cb | 9 +-------- src/mainboard/msi/ms7721/devicetree.cb | 9 +-------- 25 files changed, 25 insertions(+), 206 deletions(-) diff --git a/src/mainboard/amd/bettong/devicetree.cb b/src/mainboard/amd/bettong/devicetree.cb index 84aaf41a3c..c447bcad95 100644 --- a/src/mainboard/amd/bettong/devicetree.cb +++ b/src/mainboard/amd/bettong/devicetree.cb @@ -42,14 +42,7 @@ chip northbridge/amd/pi/00660F01/root_complex device pci 10.0 on end # USB device pci 11.0 on end # SATA device pci 12.0 on end # USB - device pci 14.0 on # SM - chip drivers/generic/generic #dimm 0-0-0 - device i2c 50 on end - end - chip drivers/generic/generic #dimm 0-0-1 - device i2c 51 on end - end - end # SM + device pci 14.0 on end # SM #device pci 14.2 on end # HDA 0x4383 device pci 14.3 on end # LPC 0x439d device pci 14.7 on end # SD diff --git a/src/mainboard/amd/gardenia/devicetree.cb b/src/mainboard/amd/gardenia/devicetree.cb index e9946adc55..027a820466 100644 --- a/src/mainboard/amd/gardenia/devicetree.cb +++ b/src/mainboard/amd/gardenia/devicetree.cb @@ -40,11 +40,7 @@ chip soc/amd/stoneyridge device pci 10.0 on end # xHCI device pci 11.0 on end # SATA device pci 12.0 on end # EHCI - device pci 14.0 on # SM - chip drivers/generic/generic # dimm 0-0-0 - device i2c 51 on end - end - end # SM + device pci 14.0 on end # SM device pci 14.3 on end # LPC 0x790e device pci 14.7 on end # SD device pci 18.0 on end diff --git a/src/mainboard/amd/inagua/devicetree.cb b/src/mainboard/amd/inagua/devicetree.cb index 578c654afd..946bd59078 100644 --- a/src/mainboard/amd/inagua/devicetree.cb +++ b/src/mainboard/amd/inagua/devicetree.cb @@ -37,14 +37,7 @@ chip northbridge/amd/agesa/family14/root_complex device pci 12.2 on end # EHCI USB 0-4 device pci 13.0 on end # OHCI USB 5-9 device pci 13.2 on end # EHCI USB 5-9 - device pci 14.0 on # SM - chip drivers/generic/generic #dimm 0-0-0 - device i2c 50 on end - end - chip drivers/generic/generic #dimm 0-0-1 - device i2c 51 on end - end - end # SM + device pci 14.0 on end # SM device pci 14.1 on end # IDE 0x439c device pci 14.2 on end # HDA 0x4383 device pci 14.3 on # LPC 0x439d diff --git a/src/mainboard/amd/lamar/devicetree.cb b/src/mainboard/amd/lamar/devicetree.cb index d7f3f05023..5c88a3c557 100644 --- a/src/mainboard/amd/lamar/devicetree.cb +++ b/src/mainboard/amd/lamar/devicetree.cb @@ -53,20 +53,7 @@ chip northbridge/amd/pi/00630F01/root_complex device pci 12.2 on end # 0x7808 USB EHCI device pci 13.0 on end # 0x7807 USB OHCI device pci 13.2 on end # 0x7808 USB EHCI - device pci 14.0 on # 0x780B SMBus - chip drivers/generic/generic #dimm 0-0-0 - device i2c 50 on end - end - chip drivers/generic/generic #dimm 0-0-1 - device i2c 51 on end - end - chip drivers/generic/generic #dimm 0-1-0 - device i2c 52 on end - end - chip drivers/generic/generic #dimm 0-1-1 - device i2c 53 on end - end - end # SM + device pci 14.0 on end # SM device pci 14.1 on end # 0x780C IDE device pci 14.2 on end # 0x780D HDA device pci 14.3 on # 0x780E LPC diff --git a/src/mainboard/amd/olivehill/devicetree.cb b/src/mainboard/amd/olivehill/devicetree.cb index bf8d476512..b29d32796d 100644 --- a/src/mainboard/amd/olivehill/devicetree.cb +++ b/src/mainboard/amd/olivehill/devicetree.cb @@ -40,14 +40,7 @@ chip northbridge/amd/agesa/family16kb/root_complex device pci 12.2 on end # USB device pci 13.0 on end # USB device pci 13.2 on end # USB - device pci 14.0 on # SM - chip drivers/generic/generic #dimm 0-0-0 - device i2c 50 on end - end - chip drivers/generic/generic #dimm 0-0-1 - device i2c 51 on end - end - end # SM + device pci 14.0 on end # SM device pci 14.2 on end # HDA 0x4383 device pci 14.3 on end # LPC 0x439d device pci 14.7 on end # SD diff --git a/src/mainboard/amd/olivehillplus/devicetree.cb b/src/mainboard/amd/olivehillplus/devicetree.cb index 430b17b0ec..9b59d99af5 100644 --- a/src/mainboard/amd/olivehillplus/devicetree.cb +++ b/src/mainboard/amd/olivehillplus/devicetree.cb @@ -41,14 +41,7 @@ chip northbridge/amd/pi/00730F01/root_complex device pci 11.0 on end # SATA device pci 12.0 on end # EHCI #0 device pci 13.0 on end # EHCI #1 - device pci 14.0 on # SMBus - chip drivers/generic/generic #dimm 0-0-0 - device i2c 50 on end - end - chip drivers/generic/generic #dimm 0-0-1 - device i2c 51 on end - end - end # SMbus + device pci 14.0 on end # SMBus device pci 14.2 on end # HDA 0x4383 device pci 14.3 on end # LPC 0x439d device pci 14.7 on end # SD diff --git a/src/mainboard/amd/padmelon/devicetree.cb b/src/mainboard/amd/padmelon/devicetree.cb index fa83d106ca..be0fdfc2a0 100644 --- a/src/mainboard/amd/padmelon/devicetree.cb +++ b/src/mainboard/amd/padmelon/devicetree.cb @@ -45,14 +45,7 @@ chip soc/amd/stoneyridge device pci 10.0 on end # USB xHCI device pci 11.0 on end # SATA device pci 12.0 on end # USB EHCI - device pci 14.0 on # SM - chip drivers/generic/generic #dimm 0-0-0 - device i2c 50 on end - end - chip drivers/generic/generic #dimm 0-1-0 - device i2c 52 on end - end - end # SM + device pci 14.0 on end # SM device pci 14.3 on # LPC 0x439d chip superio/fintek/f81803a device pnp 4e.1 on # COM1 diff --git a/src/mainboard/amd/parmer/devicetree.cb b/src/mainboard/amd/parmer/devicetree.cb index e619def270..aad3413279 100644 --- a/src/mainboard/amd/parmer/devicetree.cb +++ b/src/mainboard/amd/parmer/devicetree.cb @@ -43,14 +43,7 @@ chip northbridge/amd/agesa/family15tn/root_complex device pci 12.2 on end # USB device pci 13.0 on end # USB device pci 13.2 on end # USB - device pci 14.0 on # SMBUS - chip drivers/generic/generic #dimm 0 - device i2c 50 on end # 7-bit SPD address - end - chip drivers/generic/generic #dimm 1 - device i2c 51 on end # 7-bit SPD address - end - end # SM + device pci 14.0 on end # SMBUS device pci 14.1 on end # IDE 0x439c device pci 14.2 on end # HDA 0x4383 device pci 14.3 on end # LPC 0x439d diff --git a/src/mainboard/amd/persimmon/devicetree.cb b/src/mainboard/amd/persimmon/devicetree.cb index 323e7f2679..73cf19d4d8 100644 --- a/src/mainboard/amd/persimmon/devicetree.cb +++ b/src/mainboard/amd/persimmon/devicetree.cb @@ -36,14 +36,7 @@ chip northbridge/amd/agesa/family14/root_complex device pci 12.2 on end # EHCI USB 0-4 device pci 13.0 on end # OHCI USB 5-9 device pci 13.2 on end # EHCI USB 5-9 - device pci 14.0 on # SM - chip drivers/generic/generic #dimm 0-0-0 - device i2c 50 on end - end - chip drivers/generic/generic #dimm 0-0-1 - device i2c 51 on end - end - end # SM + device pci 14.0 on end # SM device pci 14.1 on end # IDE 0x439c device pci 14.2 on end # HDA 0x4383 device pci 14.3 on # LPC 0x439d diff --git a/src/mainboard/amd/thatcher/devicetree.cb b/src/mainboard/amd/thatcher/devicetree.cb index 4ae1ba93e9..fd4cbef85f 100644 --- a/src/mainboard/amd/thatcher/devicetree.cb +++ b/src/mainboard/amd/thatcher/devicetree.cb @@ -43,14 +43,7 @@ chip northbridge/amd/agesa/family15tn/root_complex device pci 12.2 on end # USB device pci 13.0 on end # USB device pci 13.2 on end # USB - device pci 14.0 on # SMBUS - chip drivers/generic/generic #dimm 0 - device i2c 50 on end # 7-bit SPD address - end - chip drivers/generic/generic #dimm 1 - device i2c 51 on end # 7-bit SPD address - end - end # SM + device pci 14.0 on end # SMBUS device pci 14.1 on end # IDE 0x439c device pci 14.2 on end # HDA 0x4383 device pci 14.3 on # LPC 0x439d diff --git a/src/mainboard/asrock/e350m1/devicetree.cb b/src/mainboard/asrock/e350m1/devicetree.cb index e374c417ba..b6ec209eb0 100644 --- a/src/mainboard/asrock/e350m1/devicetree.cb +++ b/src/mainboard/asrock/e350m1/devicetree.cb @@ -38,14 +38,7 @@ chip northbridge/amd/agesa/family14/root_complex device pci 12.2 on end # USB device pci 13.0 on end # USB device pci 13.2 on end # USB - device pci 14.0 on # SM - chip drivers/generic/generic #dimm 0-0-0 - device i2c 50 on end - end - chip drivers/generic/generic #dimm 0-0-1 - device i2c 51 on end - end - end # SM + device pci 14.0 on end # SM device pci 14.1 on end # IDE 0x439c device pci 14.2 on end # HDA 0x4383 device pci 14.3 on # LPC diff --git a/src/mainboard/asrock/imb-a180/devicetree.cb b/src/mainboard/asrock/imb-a180/devicetree.cb index 2c4a4aac12..536236ed4b 100644 --- a/src/mainboard/asrock/imb-a180/devicetree.cb +++ b/src/mainboard/asrock/imb-a180/devicetree.cb @@ -41,14 +41,7 @@ chip northbridge/amd/agesa/family16kb/root_complex device pci 12.2 on end # USB device pci 13.0 on end # USB device pci 13.2 on end # USB - device pci 14.0 on # SM - chip drivers/generic/generic #dimm 0-0-0 - device i2c 50 on end - end - chip drivers/generic/generic #dimm 0-0-1 - device i2c 51 on end - end - end # SM + device pci 14.0 on end # SM device pci 14.2 on end # HDA 0x4383 device pci 14.3 on chip superio/winbond/w83627uhg diff --git a/src/mainboard/asus/am1i-a/devicetree.cb b/src/mainboard/asus/am1i-a/devicetree.cb index 53114c17ea..8e44874edd 100644 --- a/src/mainboard/asus/am1i-a/devicetree.cb +++ b/src/mainboard/asus/am1i-a/devicetree.cb @@ -42,14 +42,7 @@ chip northbridge/amd/agesa/family16kb/root_complex device pci 12.2 on end # USB device pci 13.0 on end # USB device pci 13.2 on end # USB - device pci 14.0 on # SM - chip drivers/generic/generic #dimm 0-0-0 - device i2c 50 on end - end - chip drivers/generic/generic #dimm 0-0-1 - device i2c 51 on end - end - end # SM + device pci 14.0 on end # SM device pci 14.2 on end # HDA 0x4383 device pci 14.3 on # LPC 0x439d chip superio/ite/it8623e diff --git a/src/mainboard/asus/f2a85-m/devicetree_f2a85-m.cb b/src/mainboard/asus/f2a85-m/devicetree_f2a85-m.cb index 349a84533d..7a22d78871 100644 --- a/src/mainboard/asus/f2a85-m/devicetree_f2a85-m.cb +++ b/src/mainboard/asus/f2a85-m/devicetree_f2a85-m.cb @@ -46,14 +46,7 @@ chip northbridge/amd/agesa/family15tn/root_complex device pci 12.2 on end # USB device pci 13.0 on end # USB device pci 13.2 on end # USB - device pci 14.0 on # SMBUS - chip drivers/generic/generic #dimm 0 - device i2c 50 on end # 7-bit SPD address - end - chip drivers/generic/generic #dimm 1 - device i2c 51 on end # 7-bit SPD address - end - end # SM + device pci 14.0 on end # SMBUS device pci 14.1 off end # IDE 0x439c device pci 14.2 on end # HDA 0x4383 device pci 14.3 on # LPC 0x439d diff --git a/src/mainboard/asus/f2a85-m/devicetree_f2a85-m_le.cb b/src/mainboard/asus/f2a85-m/devicetree_f2a85-m_le.cb index af0e4cc9db..7d0e820007 100644 --- a/src/mainboard/asus/f2a85-m/devicetree_f2a85-m_le.cb +++ b/src/mainboard/asus/f2a85-m/devicetree_f2a85-m_le.cb @@ -46,14 +46,7 @@ chip northbridge/amd/agesa/family15tn/root_complex device pci 12.2 on end # USB device pci 13.0 on end # USB device pci 13.2 on end # USB - device pci 14.0 on # SMBUS - chip drivers/generic/generic #dimm 0 - device i2c 50 on end # 7-bit SPD address - end - chip drivers/generic/generic #dimm 1 - device i2c 51 on end # 7-bit SPD address - end - end # SM + device pci 14.0 on end # SMBUS device pci 14.1 off end # IDE 0x439c device pci 14.2 on end # HDA 0x4383 device pci 14.3 on # LPC 0x439d diff --git a/src/mainboard/asus/f2a85-m/devicetree_f2a85-m_pro.cb b/src/mainboard/asus/f2a85-m/devicetree_f2a85-m_pro.cb index f13e3e8ba7..97405aa313 100644 --- a/src/mainboard/asus/f2a85-m/devicetree_f2a85-m_pro.cb +++ b/src/mainboard/asus/f2a85-m/devicetree_f2a85-m_pro.cb @@ -37,20 +37,7 @@ chip northbridge/amd/agesa/family15tn/root_complex device pci 12.2 on end # USB device pci 13.0 on end # USB device pci 13.2 on end # USB - device pci 14.0 on # SMBUS - chip drivers/generic/generic #dimm 0 - device i2c 50 on end # 7-bit SPD address - end - chip drivers/generic/generic #dimm 1 - device i2c 52 on end # 7-bit SPD address - end - chip drivers/generic/generic #dimm 2 - device i2c 51 on end # 7-bit SPD address - end - chip drivers/generic/generic #dimm 3 - device i2c 53 on end # 7-bit SPD address - end - end # SM + device pci 14.0 on end # SMBUS device pci 14.1 off end # unused device pci 14.2 on end # HDA 0x4383 device pci 14.3 on # LPC 0x780e diff --git a/src/mainboard/biostar/am1ml/devicetree.cb b/src/mainboard/biostar/am1ml/devicetree.cb index 400653d67b..dfe537cda3 100644 --- a/src/mainboard/biostar/am1ml/devicetree.cb +++ b/src/mainboard/biostar/am1ml/devicetree.cb @@ -41,14 +41,7 @@ chip northbridge/amd/agesa/family16kb/root_complex device pci 12.2 on end # USB device pci 13.0 on end # USB device pci 13.2 on end # USB - device pci 14.0 on # SM - chip drivers/generic/generic #dimm 0-0-0 - device i2c 50 on end - end - chip drivers/generic/generic #dimm 0-0-1 - device i2c 51 on end - end - end # SM + device pci 14.0 on end # SM device pci 14.1 on end # there is no legacy ide device pci 14.2 on end # HDA 0x4383 device pci 14.3 on # LPC 0x439d diff --git a/src/mainboard/elmex/pcm205400/devicetree.cb b/src/mainboard/elmex/pcm205400/devicetree.cb index 405f3e0f7c..902b892adb 100644 --- a/src/mainboard/elmex/pcm205400/devicetree.cb +++ b/src/mainboard/elmex/pcm205400/devicetree.cb @@ -36,14 +36,7 @@ chip northbridge/amd/agesa/family14/root_complex device pci 12.2 on end # EHCI USB 0-4 device pci 13.0 on end # OHCI USB 5-9 device pci 13.2 on end # EHCI USB 5-9 - device pci 14.0 on # SM - chip drivers/generic/generic #dimm 0-0-0 - device i2c 50 on end - end - chip drivers/generic/generic #dimm 0-0-1 - device i2c 51 on end - end - end # SM + device pci 14.0 on end # SM device pci 14.1 on end # IDE 0x439c device pci 14.2 off end # HDA 0x4383 device pci 14.3 on # LPC 0x439d diff --git a/src/mainboard/hp/abm/devicetree.cb b/src/mainboard/hp/abm/devicetree.cb index c7a7510157..cd0b354598 100644 --- a/src/mainboard/hp/abm/devicetree.cb +++ b/src/mainboard/hp/abm/devicetree.cb @@ -40,11 +40,7 @@ chip northbridge/amd/agesa/family16kb/root_complex device pci 12.2 on end # USB device pci 13.0 on end # USB device pci 13.2 on end # USB - device pci 14.0 on # SM - chip drivers/generic/generic #dimm 0-0-0 - device i2c 50 on end - end - end # SM + device pci 14.0 on end # SM device pci 14.2 off end # HDA 0x4383 device pci 14.3 on # LPC 0x439d chip superio/nuvoton/nct5104d diff --git a/src/mainboard/hp/pavilion_m6_1035dx/devicetree.cb b/src/mainboard/hp/pavilion_m6_1035dx/devicetree.cb index ad59974f26..8d705ede3a 100644 --- a/src/mainboard/hp/pavilion_m6_1035dx/devicetree.cb +++ b/src/mainboard/hp/pavilion_m6_1035dx/devicetree.cb @@ -40,14 +40,7 @@ chip northbridge/amd/agesa/family15tn/root_complex device pci 12.2 on end # USB device pci 13.0 on end # USB device pci 13.2 on end # USB - device pci 14.0 on # SMBUS - chip drivers/generic/generic #dimm 0 - device i2c 50 on end # 7-bit SPD address - end - chip drivers/generic/generic #dimm 1 - device i2c 51 on end # 7-bit SPD address - end - end # SM + device pci 14.0 on end # SM device pci 14.2 on end # HDA 0x4383 device pci 14.3 on # LPC 0x439d chip ec/compal/ene932 diff --git a/src/mainboard/jetway/nf81-t56n-lf/devicetree.cb b/src/mainboard/jetway/nf81-t56n-lf/devicetree.cb index 6289438e8f..b5d51ef501 100644 --- a/src/mainboard/jetway/nf81-t56n-lf/devicetree.cb +++ b/src/mainboard/jetway/nf81-t56n-lf/devicetree.cb @@ -37,14 +37,7 @@ chip northbridge/amd/agesa/family14/root_complex device pci 12.2 on end # EHCI USB 0-4 device pci 13.0 on end # OHCI USB 5-9 device pci 13.2 on end # EHCI USB 5-9 - device pci 14.0 on # SM - chip drivers/generic/generic #dimm 0-0-0 - device i2c 50 on end - end - chip drivers/generic/generic #dimm 0-0-1 - device i2c 51 on end - end - end # SM + device pci 14.0 on end # SM device pci 14.1 off end # IDE 0x439c device pci 14.2 on end # HDA 0x4383 device pci 14.3 on # LPC 0x439d diff --git a/src/mainboard/lenovo/g505s/devicetree.cb b/src/mainboard/lenovo/g505s/devicetree.cb index 99f42d6d58..623a78b108 100644 --- a/src/mainboard/lenovo/g505s/devicetree.cb +++ b/src/mainboard/lenovo/g505s/devicetree.cb @@ -44,14 +44,7 @@ chip northbridge/amd/agesa/family15tn/root_complex device pci 12.2 on end # FCH USB EHCI Controller device pci 13.0 on end # FCH USB OHCI Controller device pci 13.2 on end # FCH USB EHCI Controller - device pci 14.0 on # SMBUS - chip drivers/generic/generic #dimm 0 - device i2c 50 on end # 7-bit SPD address - end - chip drivers/generic/generic #dimm 1 - device i2c 51 on end # 7-bit SPD address - end - end # SM + device pci 14.0 on end # SMBUS device pci 14.2 on end # FCH Azalia Controller device pci 14.3 on # FCH LPC Bridge [1022:780e] chip ec/compal/ene932 diff --git a/src/mainboard/lippert/frontrunner-af/devicetree.cb b/src/mainboard/lippert/frontrunner-af/devicetree.cb index b72059a411..0f89d255b0 100644 --- a/src/mainboard/lippert/frontrunner-af/devicetree.cb +++ b/src/mainboard/lippert/frontrunner-af/devicetree.cb @@ -36,14 +36,7 @@ chip northbridge/amd/agesa/family14/root_complex device pci 12.2 on end # EHCI USB 0-4 device pci 13.0 on end # OHCI USB 5-9 device pci 13.2 on end # EHCI USB 5-9 - device pci 14.0 on # SM - chip drivers/generic/generic #dimm 0-0-0 - device i2c 50 on end - end - chip drivers/generic/generic #dimm 0-0-1 - device i2c 51 off end - end - end # SM + device pci 14.0 on end # SM device pci 14.1 off end # IDE 0x439c device pci 14.2 on end # HDA 0x4383 device pci 14.3 on # LPC 0x439d diff --git a/src/mainboard/lippert/toucan-af/devicetree.cb b/src/mainboard/lippert/toucan-af/devicetree.cb index cb9aa8e668..ce05afc9ce 100644 --- a/src/mainboard/lippert/toucan-af/devicetree.cb +++ b/src/mainboard/lippert/toucan-af/devicetree.cb @@ -37,14 +37,7 @@ chip northbridge/amd/agesa/family14/root_complex device pci 12.2 on end # EHCI USB 0-4 device pci 13.0 on end # OHCI USB 5-9 device pci 13.2 on end # EHCI USB 5-9 - device pci 14.0 on # SM - chip drivers/generic/generic #dimm 0-0-0 - device i2c 50 on end - end - chip drivers/generic/generic #dimm 0-0-1 - device i2c 51 off end - end - end # SM + device pci 14.0 on end # SM device pci 14.1 off end # IDE 0x439c device pci 14.2 on end # HDA 0x4383 device pci 14.3 on # LPC 0x439d diff --git a/src/mainboard/msi/ms7721/devicetree.cb b/src/mainboard/msi/ms7721/devicetree.cb index d3991f1bb1..cb860742ed 100644 --- a/src/mainboard/msi/ms7721/devicetree.cb +++ b/src/mainboard/msi/ms7721/devicetree.cb @@ -45,14 +45,7 @@ chip northbridge/amd/agesa/family15tn/root_complex device pci 12.2 on end # USB EHCI device pci 13.0 on end # USB OHCI device pci 13.2 on end # USB EHCI - device pci 14.0 on # SMBUS - chip drivers/generic/generic #dimm 0 - device i2c 50 on end # 7-bit SPD address - end - chip drivers/generic/generic #dimm 1 - device i2c 51 on end # 7-bit SPD address - end - end # SM + device pci 14.0 on end # SMBUS device pci 14.1 off end # IDE 0x439c device pci 14.2 on end # Azalia (Audio) device pci 14.3 on # LPC 0x439d From 86867dd707a45a953814c3aa76bb8d1368b799fa Mon Sep 17 00:00:00 2001 From: Matt DeVillier Date: Fri, 6 Dec 2019 19:50:13 -0600 Subject: [PATCH 0658/1242] mb/google/nocturne: adjust VBT boot resolution On nocturne, the VBT specifies that the native panel resolution (3000x2000) is to be used by FSP/GOP init, which makes payload and grub menus extremely difficult to read. Change the default POST resolution specified by the VBT to 1500x1000 instead (200% scaling) which is much more legible. Test: build/boot nocturne with GOP init and Tianocore payload, observe menu text is actually readable. Signed-off-by: Matt DeVillier Change-Id: I767a2b8319c7673e3460acfad534140409bf1d57 Reviewed-on: https://review.coreboot.org/c/coreboot/+/37621 Reviewed-by: Angel Pons Tested-by: build bot (Jenkins) --- .../google/poppy/variants/nocturne/data.vbt | Bin 4608 -> 4608 bytes 1 file changed, 0 insertions(+), 0 deletions(-) diff --git a/src/mainboard/google/poppy/variants/nocturne/data.vbt b/src/mainboard/google/poppy/variants/nocturne/data.vbt index 4d9293ef08764378262dd29ba09d48e27c4add8a..4d894309086d04129e01b8145611ab73043fecb4 100644 GIT binary patch delta 29 lcmZorX;7IU#q7^uFxinwc%y-)Aln^Q28I{RlP|I@1ORiR2vz_9 delta 29 lcmZorX;7IU#oWkXFxinwc%y-)AlnXZ28IjllP|I@1ORqH2vz_9 From a1d668efe9204a3c737a3b025942c32ea61f0c10 Mon Sep 17 00:00:00 2001 From: Patrick Georgi Date: Thu, 12 Dec 2019 16:25:28 +0100 Subject: [PATCH 0659/1242] vc/amd/pi: Fix typo MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Change-Id: Ic3d1b9f90c6ed3d85ff209f433de9ab939d760a6 Signed-off-by: Patrick Georgi Reviewed-on: https://review.coreboot.org/c/coreboot/+/37676 Reviewed-by: Kyösti Mälkki Reviewed-by: Marshall Dawson Tested-by: build bot (Jenkins) --- src/vendorcode/amd/pi/00670F00/Makefile.inc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/vendorcode/amd/pi/00670F00/Makefile.inc b/src/vendorcode/amd/pi/00670F00/Makefile.inc index a019f0540e..c78e15a288 100644 --- a/src/vendorcode/amd/pi/00670F00/Makefile.inc +++ b/src/vendorcode/amd/pi/00670F00/Makefile.inc @@ -129,7 +129,7 @@ ifeq ($(CONFIG_AGESA_SPLIT_MEMORY_FILES), y) AGESA_POST_MEM_INPUT_ELF = $(call strip_quotes,$(CONFIG_AGESA_POST_MEMORY_BINARY_PI_FILE)) # If no post-mem file then also skip pre-mem file -ifeq ($(AGESA_POST_MEM_INPUT_ELF,)) +ifeq ($(AGESA_POST_MEM_INPUT_ELF),) files_added:: warn_no_agesa else AGESA_POST_MEM_ELF = $(objcbfs)/$(patsubst %.elf,%.debug,$(notdir $(AGESA_POST_MEM_INPUT_ELF))) From 928511add124e05bb7393264eb4802bb6ac39200 Mon Sep 17 00:00:00 2001 From: Joel Kitching Date: Wed, 11 Dec 2019 17:25:02 +0800 Subject: [PATCH 0660/1242] vboot: update secdata naming scheme secdata -> secdata_firmware secdatak -> secdata_kernel BUG=b:124141368, chromium:972956 TEST=make clean && make test-abuild BRANCH=none Change-Id: Ie2051de51c8f483a8921831385557fad816eb9fb Signed-off-by: Joel Kitching Reviewed-on: https://review.coreboot.org/c/coreboot/+/37655 Tested-by: build bot (Jenkins) Reviewed-by: Julius Werner --- src/security/vboot/secdata_tpm.c | 44 +++++++++++++++++--------------- 1 file changed, 23 insertions(+), 21 deletions(-) diff --git a/src/security/vboot/secdata_tpm.c b/src/security/vboot/secdata_tpm.c index ef245552d5..0ce213662e 100644 --- a/src/security/vboot/secdata_tpm.c +++ b/src/security/vboot/secdata_tpm.c @@ -67,10 +67,11 @@ static uint32_t read_space_firmware(struct vb2_context *ctx) int attempts = 3; while (attempts--) { - RETURN_ON_FAILURE(tlcl_read(FIRMWARE_NV_INDEX, ctx->secdata, - VB2_SECDATA_SIZE)); + RETURN_ON_FAILURE(tlcl_read(FIRMWARE_NV_INDEX, + ctx->secdata_firmware, + VB2_SECDATA_FIRMWARE_SIZE)); - if (vb2api_secdata_check(ctx) == VB2_SUCCESS) + if (vb2api_secdata_firmware_check(ctx) == VB2_SUCCESS) return TPM_SUCCESS; VBDEBUG("TPM: %s() - bad CRC\n", __func__); @@ -194,14 +195,14 @@ static uint32_t set_space(const char *name, uint32_t index, const void *data, static uint32_t set_firmware_space(const void *firmware_blob) { return set_space("firmware", FIRMWARE_NV_INDEX, firmware_blob, - VB2_SECDATA_SIZE, ro_space_attributes, + VB2_SECDATA_FIRMWARE_SIZE, ro_space_attributes, pcr0_unchanged_policy, sizeof(pcr0_unchanged_policy)); } static uint32_t set_kernel_space(const void *kernel_blob) { return set_space("kernel", KERNEL_NV_INDEX, kernel_blob, - VB2_SECDATAK_SIZE, rw_space_attributes, NULL, 0); + VB2_SECDATA_KERNEL_SIZE, rw_space_attributes, NULL, 0); } static uint32_t set_rec_hash_space(const uint8_t *data) @@ -222,12 +223,12 @@ static uint32_t _factory_initialize_tpm(struct vb2_context *ctx) * indication that TPM factory initialization was successfully * completed. */ - RETURN_ON_FAILURE(set_kernel_space(ctx->secdatak)); + RETURN_ON_FAILURE(set_kernel_space(ctx->secdata_kernel)); if (CONFIG(VBOOT_HAS_REC_HASH_SPACE)) RETURN_ON_FAILURE(set_rec_hash_space(rec_hash_data)); - RETURN_ON_FAILURE(set_firmware_space(ctx->secdata)); + RETURN_ON_FAILURE(set_firmware_space(ctx->secdata_firmware)); return TPM_SUCCESS; } @@ -326,22 +327,22 @@ static uint32_t _factory_initialize_tpm(struct vb2_context *ctx) VBDEBUG("TPM: Clearing owner\n"); RETURN_ON_FAILURE(tpm_clear_and_reenable()); - /* Define and write secdatak kernel space. */ + /* Define and write secdata_kernel space. */ RETURN_ON_FAILURE(safe_define_space(KERNEL_NV_INDEX, TPM_NV_PER_PPWRITE, - VB2_SECDATAK_SIZE)); + VB2_SECDATA_KERNEL_SIZE)); RETURN_ON_FAILURE(write_secdata(KERNEL_NV_INDEX, - ctx->secdatak, - VB2_SECDATAK_SIZE)); + ctx->secdata_kernel, + VB2_SECDATA_KERNEL_SIZE)); - /* Define and write secdata firmware space. */ + /* Define and write secdata_firmware space. */ RETURN_ON_FAILURE(safe_define_space(FIRMWARE_NV_INDEX, - TPM_NV_PER_GLOBALLOCK | - TPM_NV_PER_PPWRITE, - VB2_SECDATA_SIZE)); + TPM_NV_PER_GLOBALLOCK | + TPM_NV_PER_PPWRITE, + VB2_SECDATA_FIRMWARE_SIZE)); RETURN_ON_FAILURE(write_secdata(FIRMWARE_NV_INDEX, - ctx->secdata, - VB2_SECDATA_SIZE)); + ctx->secdata_firmware, + VB2_SECDATA_FIRMWARE_SIZE)); /* Define and set rec hash space, if available. */ if (CONFIG(VBOOT_HAS_REC_HASH_SPACE)) @@ -376,9 +377,9 @@ static uint32_t factory_initialize_tpm(struct vb2_context *ctx) { uint32_t result; - /* Set initial values of secdata and secdatak spaces. */ - vb2api_secdata_create(ctx); - vb2api_secdatak_create(ctx); + /* Set initial values of secdata_firmware and secdata_kernel spaces. */ + vb2api_secdata_firmware_create(ctx); + vb2api_secdata_kernel_create(ctx); VBDEBUG("TPM: factory initialization\n"); @@ -430,7 +431,8 @@ uint32_t antirollback_write_space_firmware(struct vb2_context *ctx) { if (CONFIG(CR50_IMMEDIATELY_COMMIT_FW_SECDATA)) tlcl_cr50_enable_nvcommits(); - return write_secdata(FIRMWARE_NV_INDEX, ctx->secdata, VB2_SECDATA_SIZE); + return write_secdata(FIRMWARE_NV_INDEX, ctx->secdata_firmware, + VB2_SECDATA_FIRMWARE_SIZE); } uint32_t antirollback_read_space_rec_hash(uint8_t *data, uint32_t size) From 3833f0ffdb0c5ef6142f0688a5a7593efe3b02ef Mon Sep 17 00:00:00 2001 From: Julius Werner Date: Wed, 11 Dec 2019 22:01:32 -0800 Subject: [PATCH 0661/1242] cbfstool: Bump C version to C11 cbfstool depends on vboot headers, and vboot expects to be able to use modern C features like _Static_assert(). It just so happens that it doesn't do that in any headers included from cbfstool right now, but that may change. Let's switch cbfstool to a newer version to prevent that from becoming a problem. Change-Id: I884e1bdf4ec21487ddb1bca57ef5dc2104cf8e0e Signed-off-by: Julius Werner Reviewed-on: https://review.coreboot.org/c/coreboot/+/37666 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi Reviewed-by: Paul Menzel --- util/cbfstool/Makefile.inc | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/util/cbfstool/Makefile.inc b/util/cbfstool/Makefile.inc index 95372c2988..5c048486e6 100644 --- a/util/cbfstool/Makefile.inc +++ b/util/cbfstool/Makefile.inc @@ -129,10 +129,10 @@ ifeq ($(shell uname -s | cut -c-7 2>/dev/null), MINGW32) TOOLCFLAGS += -mno-ms-bitfields endif ifeq ($(shell uname -o 2>/dev/null), Cygwin) -TOOLCFLAGS+=-std=gnu99 +TOOLCFLAGS+=-std=gnu11 TOOLCPPFLAGS+=-D_GNU_SOURCE else -TOOLCFLAGS+=-std=c99 +TOOLCFLAGS+=-std=c11 endif $(objutil)/cbfstool/%.o: $(objutil)/cbfstool/%.c From 24f0455016720e4222057ecda3415c05c7cb095c Mon Sep 17 00:00:00 2001 From: Eric Lai Date: Thu, 12 Dec 2019 13:06:09 +0800 Subject: [PATCH 0662/1242] libpayload/drivers/i8042: Remove obsolete flag CB:37594 change the flag makes PC_KEYBOARD_IGNORE_INIT_FAILURE obsolete. Remove it. BUG=b:145130110 TEST=N/A Signed-off-by: Eric Lai Change-Id: Idcf816155b32dd691b48a7479297b556d32dd6f9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/37663 Tested-by: build bot (Jenkins) Reviewed-by: Mathew King --- payloads/libpayload/Kconfig | 4 ---- 1 file changed, 4 deletions(-) diff --git a/payloads/libpayload/Kconfig b/payloads/libpayload/Kconfig index 347ccac6b0..f7501e36b0 100644 --- a/payloads/libpayload/Kconfig +++ b/payloads/libpayload/Kconfig @@ -343,10 +343,6 @@ config PC_KEYBOARD default y if ARCH_X86 # uses IO default n -config PC_KEYBOARD_IGNORE_INIT_FAILURE - bool "Ignore keyboard failures during init and always add input device" - default n - config PC_KEYBOARD_AT_TRANSLATED bool "AT Translation keyboard device" default n From 3d5e1e5d52b83306bcc8a32fc26f89d7f25bbb09 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ky=C3=B6sti=20M=C3=A4lkki?= Date: Tue, 3 Dec 2019 14:06:02 +0200 Subject: [PATCH 0663/1242] sb/amd/cimx/sb800: Postpone Sb_Poweron_Init() call MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit With LPC decode enables explicitly set in C env bootblock, this call can be delayed to happen before AMD_INIT_RESET. Change-Id: I3a28eaa2cf70b770b022760a2380ded0f43e9a6f Signed-off-by: Kyösti Mälkki Reviewed-on: https://review.coreboot.org/c/coreboot/+/37449 Tested-by: build bot (Jenkins) Reviewed-by: Michał Żygowski --- src/cpu/amd/agesa/family14/Makefile.inc | 1 - src/cpu/amd/agesa/family14/romstage.c | 24 ------------------- src/drivers/amd/agesa/romstage.c | 7 +----- src/mainboard/amd/inagua/romstage.c | 2 ++ src/mainboard/amd/persimmon/romstage.c | 2 ++ src/mainboard/amd/south_station/romstage.c | 2 ++ src/mainboard/amd/union_station/romstage.c | 2 ++ src/mainboard/asrock/e350m1/romstage.c | 2 ++ src/mainboard/elmex/pcm205400/romstage.c | 2 ++ src/mainboard/gizmosphere/gizmo/romstage.c | 2 ++ src/mainboard/jetway/nf81-t56n-lf/romstage.c | 2 ++ .../lippert/frontrunner-af/romstage.c | 2 ++ src/mainboard/lippert/toucan-af/romstage.c | 2 ++ src/mainboard/pcengines/apu1/romstage.c | 2 ++ .../amd/agesa/family14/state_machine.c | 18 +++++++++----- src/northbridge/amd/agesa/state_machine.h | 1 - 16 files changed, 35 insertions(+), 38 deletions(-) delete mode 100644 src/cpu/amd/agesa/family14/romstage.c diff --git a/src/cpu/amd/agesa/family14/Makefile.inc b/src/cpu/amd/agesa/family14/Makefile.inc index 7db1fe4ac9..1d681133c8 100644 --- a/src/cpu/amd/agesa/family14/Makefile.inc +++ b/src/cpu/amd/agesa/family14/Makefile.inc @@ -12,7 +12,6 @@ # romstage-y += fixme.c -romstage-y += romstage.c ramstage-y += fixme.c ramstage-y += chip_name.c diff --git a/src/cpu/amd/agesa/family14/romstage.c b/src/cpu/amd/agesa/family14/romstage.c deleted file mode 100644 index 54069cc30d..0000000000 --- a/src/cpu/amd/agesa/family14/romstage.c +++ /dev/null @@ -1,24 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - - -#include - -#include - -void platform_once(struct sysinfo *cb) -{ - sb_Poweron_Init(); - - board_BeforeAgesa(cb); -} diff --git a/src/drivers/amd/agesa/romstage.c b/src/drivers/amd/agesa/romstage.c index dbf8bd6070..ee4d45e95b 100644 --- a/src/drivers/amd/agesa/romstage.c +++ b/src/drivers/amd/agesa/romstage.c @@ -29,11 +29,6 @@ void __weak board_BeforeAgesa(struct sysinfo *cb) { } -void __weak platform_once(struct sysinfo *cb) -{ - board_BeforeAgesa(cb); -} - static void fill_sysinfo(struct sysinfo *cb) { memset(cb, 0, sizeof(*cb)); @@ -67,7 +62,7 @@ static void romstage_main(void) timestamp_init(timestamp_get()); timestamp_add_now(TS_START_ROMSTAGE); - platform_once(cb); + board_BeforeAgesa(cb); console_init(); } diff --git a/src/mainboard/amd/inagua/romstage.c b/src/mainboard/amd/inagua/romstage.c index 3454ef8744..43d9da9b5d 100644 --- a/src/mainboard/amd/inagua/romstage.c +++ b/src/mainboard/amd/inagua/romstage.c @@ -15,11 +15,13 @@ #include #include +#include #define SERIAL_DEV PNP_DEV(0x2e, SMSCSUPERIO_SP1) void board_BeforeAgesa(struct sysinfo *cb) { + sb_Poweron_Init(); kbc1100_early_init(0x2e); kbc1100_early_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); } diff --git a/src/mainboard/amd/persimmon/romstage.c b/src/mainboard/amd/persimmon/romstage.c index 1fbdd4b268..7ccf1674d7 100644 --- a/src/mainboard/amd/persimmon/romstage.c +++ b/src/mainboard/amd/persimmon/romstage.c @@ -16,10 +16,12 @@ #include #include #include +#include #define SERIAL_DEV PNP_DEV(0x4e, F81865F_SP1) void board_BeforeAgesa(struct sysinfo *cb) { + sb_Poweron_Init(); fintek_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); } diff --git a/src/mainboard/amd/south_station/romstage.c b/src/mainboard/amd/south_station/romstage.c index 1fbdd4b268..7ccf1674d7 100644 --- a/src/mainboard/amd/south_station/romstage.c +++ b/src/mainboard/amd/south_station/romstage.c @@ -16,10 +16,12 @@ #include #include #include +#include #define SERIAL_DEV PNP_DEV(0x4e, F81865F_SP1) void board_BeforeAgesa(struct sysinfo *cb) { + sb_Poweron_Init(); fintek_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); } diff --git a/src/mainboard/amd/union_station/romstage.c b/src/mainboard/amd/union_station/romstage.c index f2b00bc24d..af64ad8b50 100644 --- a/src/mainboard/amd/union_station/romstage.c +++ b/src/mainboard/amd/union_station/romstage.c @@ -14,7 +14,9 @@ */ #include +#include void board_BeforeAgesa(struct sysinfo *cb) { + sb_Poweron_Init(); } diff --git a/src/mainboard/asrock/e350m1/romstage.c b/src/mainboard/asrock/e350m1/romstage.c index 292ecf2b35..27a1fac815 100644 --- a/src/mainboard/asrock/e350m1/romstage.c +++ b/src/mainboard/asrock/e350m1/romstage.c @@ -16,11 +16,13 @@ #include #include #include +#include #define SERIAL_DEV PNP_DEV(0x2e, NCT5572D_SP1) void board_BeforeAgesa(struct sysinfo *cb) { + sb_Poweron_Init(); nuvoton_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); } diff --git a/src/mainboard/elmex/pcm205400/romstage.c b/src/mainboard/elmex/pcm205400/romstage.c index 1fbdd4b268..7ccf1674d7 100644 --- a/src/mainboard/elmex/pcm205400/romstage.c +++ b/src/mainboard/elmex/pcm205400/romstage.c @@ -16,10 +16,12 @@ #include #include #include +#include #define SERIAL_DEV PNP_DEV(0x4e, F81865F_SP1) void board_BeforeAgesa(struct sysinfo *cb) { + sb_Poweron_Init(); fintek_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); } diff --git a/src/mainboard/gizmosphere/gizmo/romstage.c b/src/mainboard/gizmosphere/gizmo/romstage.c index 8dec7feb8a..7c3f534527 100644 --- a/src/mainboard/gizmosphere/gizmo/romstage.c +++ b/src/mainboard/gizmosphere/gizmo/romstage.c @@ -15,7 +15,9 @@ */ #include +#include void board_BeforeAgesa(struct sysinfo *cb) { + sb_Poweron_Init(); } diff --git a/src/mainboard/jetway/nf81-t56n-lf/romstage.c b/src/mainboard/jetway/nf81-t56n-lf/romstage.c index a971c15d52..5e61bddfcc 100644 --- a/src/mainboard/jetway/nf81-t56n-lf/romstage.c +++ b/src/mainboard/jetway/nf81-t56n-lf/romstage.c @@ -17,11 +17,13 @@ #include #include #include +#include /* Ensure Super I/O config address (i.e., 0x2e or 0x4e) matches that of devicetree.cb */ #define SERIAL_DEV PNP_DEV(0x2e, F71869AD_SP1) void board_BeforeAgesa(struct sysinfo *cb) { + sb_Poweron_Init(); fintek_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); } diff --git a/src/mainboard/lippert/frontrunner-af/romstage.c b/src/mainboard/lippert/frontrunner-af/romstage.c index 83d5a6dc98..f8e6091af0 100644 --- a/src/mainboard/lippert/frontrunner-af/romstage.c +++ b/src/mainboard/lippert/frontrunner-af/romstage.c @@ -15,10 +15,12 @@ #include #include +#include #define SERIAL_DEV PNP_DEV(0x4e, SMSCSUPERIO_SP1) void board_BeforeAgesa(struct sysinfo *cb) { + sb_Poweron_Init(); smscsuperio_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); } diff --git a/src/mainboard/lippert/toucan-af/romstage.c b/src/mainboard/lippert/toucan-af/romstage.c index 7ca9dcb9f2..ebbe4fc0df 100644 --- a/src/mainboard/lippert/toucan-af/romstage.c +++ b/src/mainboard/lippert/toucan-af/romstage.c @@ -16,10 +16,12 @@ #include #include #include +#include #define SERIAL_DEV PNP_DEV(0x4e, W83627DHG_SP1) void board_BeforeAgesa(struct sysinfo *cb) { + sb_Poweron_Init(); winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); } diff --git a/src/mainboard/pcengines/apu1/romstage.c b/src/mainboard/pcengines/apu1/romstage.c index 89bf3049d6..da0e0d3d5e 100644 --- a/src/mainboard/pcengines/apu1/romstage.c +++ b/src/mainboard/pcengines/apu1/romstage.c @@ -21,6 +21,7 @@ #include #include "gpio_ftns.h" #include +#include #define SIO_PORT 0x2e #define SERIAL_DEV PNP_DEV(SIO_PORT, NCT5104D_SP1) @@ -60,6 +61,7 @@ static void early_lpc_init(void) void board_BeforeAgesa(struct sysinfo *cb) { + sb_Poweron_Init(); early_lpc_init(); nuvoton_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); } diff --git a/src/northbridge/amd/agesa/family14/state_machine.c b/src/northbridge/amd/agesa/family14/state_machine.c index df55efa749..91a8f70259 100644 --- a/src/northbridge/amd/agesa/family14/state_machine.c +++ b/src/northbridge/amd/agesa/family14/state_machine.c @@ -29,24 +29,30 @@ void platform_BeforeInitReset(struct sysinfo *cb, AMD_RESET_PARAMS *Reset) { + if (!boot_cpu()) + return; + + if (!CONFIG(ROMCC_BOOTBLOCK)) + sb_Poweron_Init(); + /* Reboots with outb(3,0x92), outb(4,0xcf9) or triple-fault all * would fail later in AmdInitPost(), when DRAM is already configured * and C6DramLock bit has been set. * * As a workaround, do a hard reset to clear C6DramLock bit. */ + #ifdef __SIMPLE_DEVICE__ pci_devfn_t dev = PCI_DEV(0, 0x18, 2); #else struct device *dev = pcidev_on_root(0x18, 2); #endif - if (boot_cpu()) { - u32 mct_cfg_lo = pci_read_config32(dev, 0x118); - if (mct_cfg_lo & (1<<19)) { - printk(BIOS_CRIT, "C6DramLock is set, resetting\n"); - system_reset(); - } + u32 mct_cfg_lo = pci_read_config32(dev, 0x118); + if (mct_cfg_lo & (1<<19)) { + printk(BIOS_CRIT, "C6DramLock is set, resetting\n"); + system_reset(); } + } void platform_BeforeInitEarly(struct sysinfo *cb, AMD_EARLY_PARAMS *Early) diff --git a/src/northbridge/amd/agesa/state_machine.h b/src/northbridge/amd/agesa/state_machine.h index 9de011a062..c4a30540b5 100644 --- a/src/northbridge/amd/agesa/state_machine.h +++ b/src/northbridge/amd/agesa/state_machine.h @@ -45,7 +45,6 @@ struct sysinfo }; void board_BeforeAgesa(struct sysinfo *cb); -void platform_once(struct sysinfo *cb); void agesa_set_interface(struct sysinfo *cb); From bc979cc904db24dcc78779a11940e0ac2be303c0 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Micha=C5=82=20=C5=BBygowski?= Date: Thu, 28 Nov 2019 14:18:12 +0100 Subject: [PATCH 0664/1242] pcengines/apu1: Switch away from ROMCC_BOOTBLOCK MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit TEST=boot PC Engines apu1 with C bootblock patch and launch Debian with Linux kernel 4.14.50 Signed-off-by: Michał Żygowski Change-Id: I36af6d3871a57f462a7508745663d9759de1c47d Reviewed-on: https://review.coreboot.org/c/coreboot/+/37332 Reviewed-by: Angel Pons Reviewed-by: HAOUAS Elyes Reviewed-by: Kyösti Mälkki Tested-by: build bot (Jenkins) --- src/mainboard/pcengines/apu1/Kconfig | 1 - src/mainboard/pcengines/apu1/Makefile.inc | 2 ++ src/mainboard/pcengines/apu1/bootblock.c | 25 +++++++++++++++++++++++ src/mainboard/pcengines/apu1/romstage.c | 2 -- 4 files changed, 27 insertions(+), 3 deletions(-) create mode 100644 src/mainboard/pcengines/apu1/bootblock.c diff --git a/src/mainboard/pcengines/apu1/Kconfig b/src/mainboard/pcengines/apu1/Kconfig index 168423632b..3396845559 100644 --- a/src/mainboard/pcengines/apu1/Kconfig +++ b/src/mainboard/pcengines/apu1/Kconfig @@ -18,7 +18,6 @@ if BOARD_PCENGINES_APU1 config BOARD_SPECIFIC_OPTIONS def_bool y - select ROMCC_BOOTBLOCK select CPU_AMD_AGESA_FAMILY14 select NORTHBRIDGE_AMD_AGESA_FAMILY14 select SOUTHBRIDGE_AMD_CIMX_SB800 diff --git a/src/mainboard/pcengines/apu1/Makefile.inc b/src/mainboard/pcengines/apu1/Makefile.inc index 543ac97723..3aa3bbe67c 100644 --- a/src/mainboard/pcengines/apu1/Makefile.inc +++ b/src/mainboard/pcengines/apu1/Makefile.inc @@ -21,6 +21,8 @@ pci$(stripped_ahcibios_id).rom-file := $(call strip_quotes,$(CONFIG_AHCI_BIOS_FI pci$(stripped_ahcibios_id).rom-type := optionrom endif +bootblock-y += bootblock.c + romstage-y += buildOpts.c romstage-y += BiosCallOuts.c romstage-y += OemCustomize.c diff --git a/src/mainboard/pcengines/apu1/bootblock.c b/src/mainboard/pcengines/apu1/bootblock.c new file mode 100644 index 0000000000..2d34cba3bf --- /dev/null +++ b/src/mainboard/pcengines/apu1/bootblock.c @@ -0,0 +1,25 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include +#include + +#define SIO_PORT 0x2e +#define SERIAL_DEV PNP_DEV(SIO_PORT, NCT5104D_SP1) + +void bootblock_mainboard_early_init(void) +{ + nuvoton_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); +} diff --git a/src/mainboard/pcengines/apu1/romstage.c b/src/mainboard/pcengines/apu1/romstage.c index da0e0d3d5e..20a6318a46 100644 --- a/src/mainboard/pcengines/apu1/romstage.c +++ b/src/mainboard/pcengines/apu1/romstage.c @@ -61,7 +61,5 @@ static void early_lpc_init(void) void board_BeforeAgesa(struct sysinfo *cb) { - sb_Poweron_Init(); early_lpc_init(); - nuvoton_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); } From 6a5c61583b48e665e3a5c6ae6f23138a7ca21207 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ky=C3=B6sti=20M=C3=A4lkki?= Date: Tue, 3 Dec 2019 12:58:48 +0200 Subject: [PATCH 0665/1242] gizmosphere/gizmo: Switch away from ROMCC_BOOTBLOCK MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit No special treatment required for bootblock. Change-Id: I1a08d4da94ab34bf62fbfdd2cb66f2b44a847916 Signed-off-by: Kyösti Mälkki Reviewed-on: https://review.coreboot.org/c/coreboot/+/37452 Reviewed-by: Patrick Georgi Reviewed-by: HAOUAS Elyes Tested-by: build bot (Jenkins) --- src/mainboard/gizmosphere/gizmo/Kconfig | 1 - src/mainboard/gizmosphere/gizmo/romstage.c | 23 ---------------------- 2 files changed, 24 deletions(-) delete mode 100644 src/mainboard/gizmosphere/gizmo/romstage.c diff --git a/src/mainboard/gizmosphere/gizmo/Kconfig b/src/mainboard/gizmosphere/gizmo/Kconfig index e1c286be8e..e195e8f0a2 100644 --- a/src/mainboard/gizmosphere/gizmo/Kconfig +++ b/src/mainboard/gizmosphere/gizmo/Kconfig @@ -18,7 +18,6 @@ if BOARD_GIZMOSPHERE_GIZMO config BOARD_SPECIFIC_OPTIONS def_bool y - select ROMCC_BOOTBLOCK select CPU_AMD_AGESA_FAMILY14 select NORTHBRIDGE_AMD_AGESA_FAMILY14 select SOUTHBRIDGE_AMD_CIMX_SB800 diff --git a/src/mainboard/gizmosphere/gizmo/romstage.c b/src/mainboard/gizmosphere/gizmo/romstage.c deleted file mode 100644 index 7c3f534527..0000000000 --- a/src/mainboard/gizmosphere/gizmo/romstage.c +++ /dev/null @@ -1,23 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 Advanced Micro Devices, Inc. - * Copyright (C) 2013 Sage Electronic Engineering, LLC - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include - -void board_BeforeAgesa(struct sysinfo *cb) -{ - sb_Poweron_Init(); -} From 8a2204896a4bd784a34d3c4a0bba1b5415aecf52 Mon Sep 17 00:00:00 2001 From: Christian Walter Date: Thu, 12 Dec 2019 10:06:27 +0100 Subject: [PATCH 0666/1242] 3rdparty/fsp: Set back commit to working version of the FSP With CB:37564 (3rdparts/fsp: Update fsp submodule) a regression has been introduced to CFL platforms, such that the FSP-M fails/is broken. This commit sets the commit to checkout in the submodule FSP back to a working version. Change-Id: I8eac551211559962fc60e7edd46ff118d7bde830 Signed-off-by: Christian Walter Reviewed-on: https://review.coreboot.org/c/coreboot/+/37669 Reviewed-by: Mimoja Reviewed-by: Patrick Rudolph Reviewed-by: Nico Huber Reviewed-by: Angel Pons Reviewed-by: Paul Menzel Tested-by: build bot (Jenkins) --- 3rdparty/fsp | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/3rdparty/fsp b/3rdparty/fsp index 0bc2b07eab..9e53d779eb 160000 --- a/3rdparty/fsp +++ b/3rdparty/fsp @@ -1 +1 @@ -Subproject commit 0bc2b07eab29a8a75cd084963c285ee5434e6666 +Subproject commit 9e53d779eb34e944f9b3386ad6a9df80f710bddd From 98b72dadf07bf8694f78384d21a4add7ac76c1f2 Mon Sep 17 00:00:00 2001 From: Patrick Rudolph Date: Tue, 10 Dec 2019 12:08:37 +0100 Subject: [PATCH 0667/1242] superio/*: Don't use conf_mode directly Use the functions defined in device/pnp.h instead of using the conf_mode directly. This will make future refactoring easier. Change-Id: Ibb94d86b3ee861f44cded469ff58b545dd7311fd Signed-off-by: Patrick Rudolph Reviewed-on: https://review.coreboot.org/c/coreboot/+/37638 Tested-by: build bot (Jenkins) Reviewed-by: Felix Held --- src/superio/nuvoton/nct5572d/superio.c | 12 ++++++------ src/superio/smsc/lpc47n227/superio.c | 13 +++++++------ src/superio/winbond/w83667hg-a/superio.c | 12 ++++++------ 3 files changed, 19 insertions(+), 18 deletions(-) diff --git a/src/superio/nuvoton/nct5572d/superio.c b/src/superio/nuvoton/nct5572d/superio.c index 30846872a0..76c983a0c7 100644 --- a/src/superio/nuvoton/nct5572d/superio.c +++ b/src/superio/nuvoton/nct5572d/superio.c @@ -43,29 +43,29 @@ static void nct5572d_init(struct device *dev) /* TODO: Might potentially need code for HWM or FDC etc. */ case NCT5572D_KBC: /* Enable mouse controller */ - pnp_enter_conf_mode_8787(dev); + pnp_enter_conf_mode(dev); byte = pnp_read_config(dev, 0x2a); byte &= ~(0x1 << 1); pnp_write_config(dev, 0x2a, byte); - pnp_exit_conf_mode_aa(dev); + pnp_exit_conf_mode(dev); mouse_detected = pc_keyboard_init(PROBE_AUX_DEVICE); if (!mouse_detected) { printk(BIOS_INFO, "%s: Disable mouse controller.", __func__); - pnp_enter_conf_mode_8787(dev); + pnp_enter_conf_mode(dev); byte = pnp_read_config(dev, 0x2a); byte |= 0x1 << 1; pnp_write_config(dev, 0x2a, byte); - pnp_exit_conf_mode_aa(dev); + pnp_exit_conf_mode(dev); } break; case NCT5572D_ACPI: /* Set power state after power fail */ power_status = CONFIG_MAINBOARD_POWER_FAILURE_STATE; get_option(&power_status, "power_on_after_fail"); - pnp_enter_conf_mode_8787(dev); + pnp_enter_conf_mode(dev); pnp_set_logical_device(dev); byte = pnp_read_config(dev, 0xe4); byte &= ~0x60; @@ -74,7 +74,7 @@ static void nct5572d_init(struct device *dev) else if (power_status == MAINBOARD_POWER_KEEP) byte |= (0x2 << 5); pnp_write_config(dev, 0xe4, byte); - pnp_exit_conf_mode_aa(dev); + pnp_exit_conf_mode(dev); printk(BIOS_INFO, "set power %s after power fail\n", power_status ? "on" : "off"); break; } diff --git a/src/superio/smsc/lpc47n227/superio.c b/src/superio/smsc/lpc47n227/superio.c index 57297aba5b..911343d890 100644 --- a/src/superio/smsc/lpc47n227/superio.c +++ b/src/superio/smsc/lpc47n227/superio.c @@ -48,6 +48,7 @@ static struct device_operations ops = { .enable_resources = lpc47n227_pnp_enable_resources, .enable = lpc47n227_pnp_enable, .init = lpc47n227_init, + .ops_pnp_mode = &pnp_conf_mode_55_aa, }; static struct pnp_info pnp_dev_info[] = { @@ -81,10 +82,10 @@ void lpc47n227_pnp_set_resources(struct device *dev) { struct resource *res; - pnp_enter_conf_mode_55(dev); + pnp_enter_conf_mode(dev); for (res = dev->resource_list; res; res = res->next) lpc47n227_pnp_set_resource(dev, res); - pnp_exit_conf_mode_aa(dev); + pnp_exit_conf_mode(dev); } /* @@ -93,9 +94,9 @@ void lpc47n227_pnp_set_resources(struct device *dev) */ void lpc47n227_pnp_enable_resources(struct device *dev) { - pnp_enter_conf_mode_55(dev); + pnp_enter_conf_mode(dev); lpc47n227_pnp_set_enable(dev, 1); - pnp_exit_conf_mode_aa(dev); + pnp_exit_conf_mode(dev); } /* @@ -104,9 +105,9 @@ void lpc47n227_pnp_enable_resources(struct device *dev) */ void lpc47n227_pnp_enable(struct device *dev) { - pnp_enter_conf_mode_55(dev); + pnp_enter_conf_mode(dev); lpc47n227_pnp_set_enable(dev, !!dev->enabled); - pnp_exit_conf_mode_aa(dev); + pnp_exit_conf_mode(dev); } /** diff --git a/src/superio/winbond/w83667hg-a/superio.c b/src/superio/winbond/w83667hg-a/superio.c index 4a995d6b5d..69ab91bf98 100644 --- a/src/superio/winbond/w83667hg-a/superio.c +++ b/src/superio/winbond/w83667hg-a/superio.c @@ -43,29 +43,29 @@ static void w83667hg_a_init(struct device *dev) /* TODO: Might potentially need code for HWM or FDC etc. */ case W83667HG_A_KBC: /* Enable mouse controller */ - pnp_enter_conf_mode_8787(dev); + pnp_enter_conf_mode(dev); byte = pnp_read_config(dev, 0x2a); byte &= ~(0x1 << 1); pnp_write_config(dev, 0x2a, byte); - pnp_exit_conf_mode_aa(dev); + pnp_exit_conf_mode(dev); mouse_detected = pc_keyboard_init(PROBE_AUX_DEVICE); if (!mouse_detected && !acpi_is_wakeup_s3()) { printk(BIOS_INFO, "%s: Disable mouse controller.", __func__); - pnp_enter_conf_mode_8787(dev); + pnp_enter_conf_mode(dev); byte = pnp_read_config(dev, 0x2a); byte |= 0x1 << 1; pnp_write_config(dev, 0x2a, byte); - pnp_exit_conf_mode_aa(dev); + pnp_exit_conf_mode(dev); } break; case W83667HG_A_ACPI: /* Set power state after power fail */ power_status = CONFIG_MAINBOARD_POWER_FAILURE_STATE; get_option(&power_status, "power_on_after_fail"); - pnp_enter_conf_mode_8787(dev); + pnp_enter_conf_mode(dev); pnp_set_logical_device(dev); byte = pnp_read_config(dev, 0xe4); byte &= ~0x60; @@ -74,7 +74,7 @@ static void w83667hg_a_init(struct device *dev) else if (power_status == MAINBOARD_POWER_KEEP) byte |= (0x2 << 5); pnp_write_config(dev, 0xe4, byte); - pnp_exit_conf_mode_aa(dev); + pnp_exit_conf_mode(dev); printk(BIOS_INFO, "set power %s after power fail\n", power_status ? "on" : "off"); break; } From d1613f5681f17c02e5219342a0edc39e4aed685d Mon Sep 17 00:00:00 2001 From: Eric Lai Date: Thu, 12 Dec 2019 13:15:30 +0800 Subject: [PATCH 0668/1242] libpayload/drivers/i8042: Add error handling Add error handling on I8042_CMD_WR_CMD_BYTE failure. BUG=b:145130110 TEST=Draillion keyboard is usable on every boot. Signed-off-by: Eric Lai Change-Id: I56c472ae7e399d4862c6e41b70f53a21d718157d Reviewed-on: https://review.coreboot.org/c/coreboot/+/37664 Tested-by: build bot (Jenkins) Reviewed-by: Duncan Laurie --- payloads/libpayload/drivers/i8042/keyboard.c | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a/payloads/libpayload/drivers/i8042/keyboard.c b/payloads/libpayload/drivers/i8042/keyboard.c index 4b4a56987a..79455cfe7b 100644 --- a/payloads/libpayload/drivers/i8042/keyboard.c +++ b/payloads/libpayload/drivers/i8042/keyboard.c @@ -318,10 +318,14 @@ static int enable_translated(void) if (!i8042_cmd(I8042_CMD_RD_CMD_BYTE)) { int cmd = i8042_read_data_ps2(); cmd |= I8042_CMD_BYTE_XLATE; - if (!i8042_cmd(I8042_CMD_WR_CMD_BYTE)) + if (!i8042_cmd(I8042_CMD_WR_CMD_BYTE)) { i8042_write_data(cmd); + } else { + printf("ERROR: i8042_cmd WR_CMD failed!\n"); + return 0; + } } else { - printf("ERROR: Keyboard i8042_cmd failed!\n"); + printf("ERROR: i8042_cmd RD_CMD failed!\n"); return 0; } return 1; From 12a651c060963ed89b46db6b00195874419417ca Mon Sep 17 00:00:00 2001 From: Gaggery Tsai Date: Thu, 5 Dec 2019 11:23:20 -0800 Subject: [PATCH 0669/1242] soc/intel/common: Add PCI device IDs for CMP-H This patch adds PCI device IDs for CMP-H. TEST=build coreboot.rom and boot to the OS Change-Id: Ia7413f75757c64b389a39d6e171f88eb61036c58 Signed-off-by: Gaggery Tsai Reviewed-on: https://review.coreboot.org/c/coreboot/+/37536 Tested-by: build bot (Jenkins) Reviewed-by: Duncan Laurie --- src/include/device/pci_ids.h | 49 ++++++++++++++++++- src/soc/intel/common/block/cse/cse.c | 1 + src/soc/intel/common/block/dsp/dsp.c | 1 + .../intel/common/block/graphics/graphics.c | 4 ++ src/soc/intel/common/block/hda/hda.c | 1 + src/soc/intel/common/block/i2c/i2c.c | 4 ++ src/soc/intel/common/block/p2sb/p2sb.c | 1 + src/soc/intel/common/block/pcie/pcie.c | 24 +++++++++ src/soc/intel/common/block/pmc/pmc.c | 1 + src/soc/intel/common/block/sata/sata.c | 3 ++ src/soc/intel/common/block/scs/sd.c | 1 + src/soc/intel/common/block/smbus/smbus.c | 1 + src/soc/intel/common/block/spi/spi.c | 4 ++ src/soc/intel/common/block/sram/sram.c | 1 + src/soc/intel/common/block/uart/uart.c | 3 ++ src/soc/intel/common/block/xdci/xdci.c | 1 + src/soc/intel/common/block/xhci/xhci.c | 1 + 17 files changed, 100 insertions(+), 1 deletion(-) diff --git a/src/include/device/pci_ids.h b/src/include/device/pci_ids.h index 43752f8368..bd5b3a5148 100644 --- a/src/include/device/pci_ids.h +++ b/src/include/device/pci_ids.h @@ -2930,6 +2930,7 @@ #define PCI_DEVICE_ID_INTEL_CNL_LP_PCIE_RP14 0x9db5 #define PCI_DEVICE_ID_INTEL_CNL_LP_PCIE_RP15 0x9db6 #define PCI_DEVICE_ID_INTEL_CNL_LP_PCIE_RP16 0x9db7 + #define PCI_DEVICE_ID_INTEL_ICP_LP_PCIE_RP1 0x34b8 #define PCI_DEVICE_ID_INTEL_ICP_LP_PCIE_RP2 0x34b9 #define PCI_DEVICE_ID_INTEL_ICP_LP_PCIE_RP3 0x34ba @@ -3005,7 +3006,30 @@ #define PCI_DEVICE_ID_INTEL_CMP_LP_PCIE_RP14 0x02b5 #define PCI_DEVICE_ID_INTEL_CMP_LP_PCIE_RP15 0x02b6 #define PCI_DEVICE_ID_INTEL_CMP_LP_PCIE_RP16 0x02b7 - +#define PCI_DEVICE_ID_INTEL_CMP_H_PCIE_RP1 0x06b8 +#define PCI_DEVICE_ID_INTEL_CMP_H_PCIE_RP2 0x06b9 +#define PCI_DEVICE_ID_INTEL_CMP_H_PCIE_RP3 0x06ba +#define PCI_DEVICE_ID_INTEL_CMP_H_PCIE_RP4 0x06bb +#define PCI_DEVICE_ID_INTEL_CMP_H_PCIE_RP5 0x06bc +#define PCI_DEVICE_ID_INTEL_CMP_H_PCIE_RP6 0x06bd +#define PCI_DEVICE_ID_INTEL_CMP_H_PCIE_RP7 0x06be +#define PCI_DEVICE_ID_INTEL_CMP_H_PCIE_RP8 0x06bf +#define PCI_DEVICE_ID_INTEL_CMP_H_PCIE_RP9 0x06b0 +#define PCI_DEVICE_ID_INTEL_CMP_H_PCIE_RP10 0x06b1 +#define PCI_DEVICE_ID_INTEL_CMP_H_PCIE_RP11 0x06b2 +#define PCI_DEVICE_ID_INTEL_CMP_H_PCIE_RP12 0x06b3 +#define PCI_DEVICE_ID_INTEL_CMP_H_PCIE_RP13 0x06b4 +#define PCI_DEVICE_ID_INTEL_CMP_H_PCIE_RP14 0x06b5 +#define PCI_DEVICE_ID_INTEL_CMP_H_PCIE_RP15 0x06b6 +#define PCI_DEVICE_ID_INTEL_CMP_H_PCIE_RP16 0x06b7 +#define PCI_DEVICE_ID_INTEL_CMP_H_PCIE_RP17 0x06c0 +#define PCI_DEVICE_ID_INTEL_CMP_H_PCIE_RP18 0x06c1 +#define PCI_DEVICE_ID_INTEL_CMP_H_PCIE_RP19 0x06c2 +#define PCI_DEVICE_ID_INTEL_CMP_H_PCIE_RP20 0x06c3 +#define PCI_DEVICE_ID_INTEL_CMP_H_PCIE_RP21 0x06ac +#define PCI_DEVICE_ID_INTEL_CMP_H_PCIE_RP22 0x06ad +#define PCI_DEVICE_ID_INTEL_CMP_H_PCIE_RP23 0x06ae +#define PCI_DEVICE_ID_INTEL_CMP_H_PCIE_RP24 0x06af #define PCI_DEVICE_ID_INTEL_JSP_PRE_PROD_PCIE_RP1 0x38b8 #define PCI_DEVICE_ID_INTEL_JSP_PRE_PROD_PCIE_RP2 0x38b9 #define PCI_DEVICE_ID_INTEL_JSP_PRE_PROD_PCIE_RP3 0x38ba @@ -3042,6 +3066,9 @@ #define PCI_DEVICE_ID_INTEL_CMP_SATA 0x02d5 #define PCI_DEVICE_ID_INTEL_CMP_PREMIUM_SATA 0x02d7 #define PCI_DEVICE_ID_INTEL_CMP_LP_SATA 0x02d3 +#define PCI_DEVICE_ID_INTEL_CMP_H_SATA 0x06d2 +#define PCI_DEVICE_ID_INTEL_CMP_H_HALO_SATA 0x06d3 +#define PCI_DEVICE_ID_INTEL_CMP_H_PREMIUM_SATA 0x06d7 #define PCI_DEVICE_ID_INTEL_TGP_LP_SATA 0xa0d3 #define PCI_DEVICE_ID_INTEL_TGP_SATA 0xa0d5 #define PCI_DEVICE_ID_INTEL_TGP_PREMIUM_SATA 0xa0d7 @@ -3060,6 +3087,7 @@ #define PCI_DEVICE_ID_INTEL_CNP_H_PMC 0xa321 #define PCI_DEVICE_ID_INTEL_ICP_PMC 0x34a1 #define PCI_DEVICE_ID_INTEL_CMP_PMC 0x02a1 +#define PCI_DEVICE_ID_INTEL_CMP_H_PMC 0x06a1 #define PCI_DEVICE_ID_INTEL_TGP_PMC 0xa0a1 #define PCI_DEVICE_ID_INTEL_JSP_PRE_PROD_PMC 0x38a1 @@ -3112,6 +3140,10 @@ #define PCI_DEVICE_ID_INTEL_CMP_I2C3 0x02eb #define PCI_DEVICE_ID_INTEL_CMP_I2C4 0x02c5 #define PCI_DEVICE_ID_INTEL_CMP_I2C5 0x02c6 +#define PCI_DEVICE_ID_INTEL_CMP_H_I2C0 0x06e8 +#define PCI_DEVICE_ID_INTEL_CMP_H_I2C1 0x06e9 +#define PCI_DEVICE_ID_INTEL_CMP_H_I2C2 0x06ea +#define PCI_DEVICE_ID_INTEL_CMP_H_I2C3 0x06eb #define PCI_DEVICE_ID_INTEL_TGP_I2C0 0xa0e8 #define PCI_DEVICE_ID_INTEL_TGP_I2C1 0xa0e9 #define PCI_DEVICE_ID_INTEL_TGP_I2C2 0xa0ea @@ -3158,6 +3190,9 @@ #define PCI_DEVICE_ID_INTEL_CMP_UART0 0x02a8 #define PCI_DEVICE_ID_INTEL_CMP_UART1 0x02a9 #define PCI_DEVICE_ID_INTEL_CMP_UART2 0x02c7 +#define PCI_DEVICE_ID_INTEL_CMP_H_UART0 0x06a8 +#define PCI_DEVICE_ID_INTEL_CMP_H_UART1 0x06a9 +#define PCI_DEVICE_ID_INTEL_CMP_H_UART2 0x06c7 #define PCI_DEVICE_ID_INTEL_TGP_UART0 0xa0a8 #define PCI_DEVICE_ID_INTEL_TGP_UART1 0xa0a9 #define PCI_DEVICE_ID_INTEL_TGP_UART2 0xa0c7 @@ -3195,6 +3230,10 @@ #define PCI_DEVICE_ID_INTEL_CMP_SPI1 0x02ab #define PCI_DEVICE_ID_INTEL_CMP_SPI2 0x02fb #define PCI_DEVICE_ID_INTEL_CMP_HWSEQ_SPI 0x02a4 +#define PCI_DEVICE_ID_INTEL_CMP_H_SPI0 0x06aa +#define PCI_DEVICE_ID_INTEL_CMP_H_SPI1 0x06ab +#define PCI_DEVICE_ID_INTEL_CMP_H_SPI2 0x06fb +#define PCI_DEVICE_ID_INTEL_CMP_H_HWSEQ_SPI 0x06a4 #define PCI_DEVICE_ID_INTEL_TGP_SPI0 0xa0a4 #define PCI_DEVICE_ID_INTEL_TGP_GSPI0 0xa0aa #define PCI_DEVICE_ID_INTEL_TGP_GSPI1 0xa0ab @@ -3379,6 +3418,7 @@ #define PCI_DEVICE_ID_INTEL_CNP_H_SMBUS 0xa323 #define PCI_DEVICE_ID_INTEL_ICP_LP_SMBUS 0x34a3 #define PCI_DEVICE_ID_INTEL_CMP_SMBUS 0x02a3 +#define PCI_DEVICE_ID_INTEL_CMP_H_SMBUS 0x06a3 #define PCI_DEVICE_ID_INTEL_TGP_LP_SMBUS 0xa0a3 #define PCI_DEVICE_ID_INTEL_JSP_PRE_PROD_SMBUS 0x38a3 @@ -3394,6 +3434,7 @@ #define PCI_DEVICE_ID_INTEL_CNP_H_XHCI 0xa36d #define PCI_DEVICE_ID_INTEL_ICP_LP_XHCI 0x34ed #define PCI_DEVICE_ID_INTEL_CMP_LP_XHCI 0x02ed +#define PCI_DEVICE_ID_INTEL_CMP_H_XHCI 0x06ed #define PCI_DEVICE_ID_INTEL_TGP_LP_XHCI 0xa0ed #define PCI_DEVICE_ID_INTEL_JSP_PRE_PROD_XHCI 0x38ed @@ -3409,6 +3450,7 @@ #define PCI_DEVICE_ID_INTEL_CNP_H_P2SB 0xa320 #define PCI_DEVICE_ID_INTEL_ICL_P2SB 0x34a0 #define PCI_DEVICE_ID_INTEL_CMP_P2SB 0x02a0 +#define PCI_DEVICE_ID_INTEL_CMP_H_P2SB 0x06a0 #define PCI_DEVICE_ID_INTEL_TGL_P2SB 0xa0a0 #define PCI_DEVICE_ID_INTEL_JSP_PRE_PROD_P2SB 0x38a0 @@ -3419,6 +3461,7 @@ #define PCI_DEVICE_ID_INTEL_CNP_H_SRAM 0xa36f #define PCI_DEVICE_ID_INTEL_ICL_SRAM 0x34ef #define PCI_DEVICE_ID_INTEL_CMP_SRAM 0x02ef +#define PCI_DEVICE_ID_INTEL_CMP_H_SRAM 0x06ef #define PCI_DEVICE_ID_INTEL_TGL_SRAM 0xa0ef #define PCI_DEVICE_ID_INTEL_JSP_PRE_PROD_SRAM 0x38ef @@ -3434,6 +3477,7 @@ #define PCI_DEVICE_ID_INTEL_CNP_H_AUDIO 0xa348 #define PCI_DEVICE_ID_INTEL_ICL_AUDIO 0x34c8 #define PCI_DEVICE_ID_INTEL_CMP_AUDIO 0x02c8 +#define PCI_DEVICE_ID_INTEL_CMP_H_AUDIO 0x06c8 #define PCI_DEVICE_ID_INTEL_BSW_AUDIO 0x2284 #define PCI_DEVICE_ID_INTEL_TGL_AUDIO 0xa0c8 #define PCI_DEVICE_ID_INTEL_JSP_PRE_PROD_AUDIO 0x38c8 @@ -3452,6 +3496,7 @@ #define PCI_DEVICE_ID_INTEL_CNP_H_CSE0 0xa360 #define PCI_DEVICE_ID_INTEL_ICL_CSE0 0x34e0 #define PCI_DEVICE_ID_INTEL_CMP_CSE0 0x02e0 +#define PCI_DEVICE_ID_INTEL_CMP_H_CSE0 0x06e0 #define PCI_DEVICE_ID_INTEL_TGL_CSE0 0xa0e0 #define PCI_DEVICE_ID_INTEL_JSP_PRE_PROD_CSE0 0x38e0 @@ -3463,6 +3508,7 @@ #define PCI_DEVICE_ID_INTEL_CNP_H_XDCI 0xa36e #define PCI_DEVICE_ID_INTEL_ICP_LP_XDCI 0x34ee #define PCI_DEVICE_ID_INTEL_CMP_LP_XDCI 0x02ee +#define PCI_DEVICE_ID_INTEL_CMP_H_XDCI 0x06ee #define PCI_DEVICE_ID_INTEL_TGP_LP_XDCI 0xa0ee /* Intel SD device Ids */ @@ -3473,6 +3519,7 @@ #define PCI_DEVICE_ID_INTEL_CNP_H_SD 0xa375 #define PCI_DEVICE_ID_INTEL_ICL_SD 0x34f8 #define PCI_DEVICE_ID_INTEL_CMP_SD 0x02f5 +#define PCI_DEVICE_ID_INTEL_CMP_H_SD 0x06f5 #define PCI_DEVICE_ID_INTEL_JSP_PRE_PROD_SD 0x38f8 /* Intel EMMC device Ids */ diff --git a/src/soc/intel/common/block/cse/cse.c b/src/soc/intel/common/block/cse/cse.c index 6aaba40559..74a0020ee3 100644 --- a/src/soc/intel/common/block/cse/cse.c +++ b/src/soc/intel/common/block/cse/cse.c @@ -754,6 +754,7 @@ static const unsigned short pci_device_ids[] = { PCI_DEVICE_ID_INTEL_CNP_H_CSE0, PCI_DEVICE_ID_INTEL_ICL_CSE0, PCI_DEVICE_ID_INTEL_CMP_CSE0, + PCI_DEVICE_ID_INTEL_CMP_H_CSE0, PCI_DEVICE_ID_INTEL_TGL_CSE0, PCI_DEVICE_ID_INTEL_JSP_PRE_PROD_CSE0, 0, diff --git a/src/soc/intel/common/block/dsp/dsp.c b/src/soc/intel/common/block/dsp/dsp.c index 6c00ed1c77..306003b3c9 100644 --- a/src/soc/intel/common/block/dsp/dsp.c +++ b/src/soc/intel/common/block/dsp/dsp.c @@ -33,6 +33,7 @@ static const unsigned short pci_device_ids[] = { PCI_DEVICE_ID_INTEL_SKL_AUDIO, PCI_DEVICE_ID_INTEL_CNP_H_AUDIO, PCI_DEVICE_ID_INTEL_CMP_AUDIO, + PCI_DEVICE_ID_INTEL_CMP_H_AUDIO, PCI_DEVICE_ID_INTEL_ICL_AUDIO, PCI_DEVICE_ID_INTEL_TGL_AUDIO, PCI_DEVICE_ID_INTEL_JSP_PRE_PROD_AUDIO, diff --git a/src/soc/intel/common/block/graphics/graphics.c b/src/soc/intel/common/block/graphics/graphics.c index cbe189c9d1..90931ebd4c 100644 --- a/src/soc/intel/common/block/graphics/graphics.c +++ b/src/soc/intel/common/block/graphics/graphics.c @@ -209,6 +209,10 @@ static const unsigned short pci_device_ids[] = { PCI_DEVICE_ID_INTEL_CML_GT1_H_2, PCI_DEVICE_ID_INTEL_CML_GT2_H_1, PCI_DEVICE_ID_INTEL_CML_GT2_H_2, + PCI_DEVICE_ID_INTEL_CML_GT2_S_G0, + PCI_DEVICE_ID_INTEL_CML_GT2_S_P0, + PCI_DEVICE_ID_INTEL_CML_GT2_H_R0, + PCI_DEVICE_ID_INTEL_CML_GT2_H_R1, PCI_DEVICE_ID_INTEL_TGL_GT0, PCI_DEVICE_ID_INTEL_TGL_GT2_ULT, PCI_DEVICE_ID_INTEL_TGL_GT2_ULX, diff --git a/src/soc/intel/common/block/hda/hda.c b/src/soc/intel/common/block/hda/hda.c index 4a87e1a2ef..12aa1051e6 100644 --- a/src/soc/intel/common/block/hda/hda.c +++ b/src/soc/intel/common/block/hda/hda.c @@ -81,6 +81,7 @@ static const unsigned short pci_device_ids[] = { PCI_DEVICE_ID_INTEL_CNP_H_AUDIO, PCI_DEVICE_ID_INTEL_ICL_AUDIO, PCI_DEVICE_ID_INTEL_CMP_AUDIO, + PCI_DEVICE_ID_INTEL_CMP_H_AUDIO, PCI_DEVICE_ID_INTEL_BSW_AUDIO, PCI_DEVICE_ID_INTEL_TGL_AUDIO, 0 diff --git a/src/soc/intel/common/block/i2c/i2c.c b/src/soc/intel/common/block/i2c/i2c.c index bc692d3a87..70f2c21f74 100644 --- a/src/soc/intel/common/block/i2c/i2c.c +++ b/src/soc/intel/common/block/i2c/i2c.c @@ -235,6 +235,10 @@ static const unsigned short pci_device_ids[] = { PCI_DEVICE_ID_INTEL_CMP_I2C3, PCI_DEVICE_ID_INTEL_CMP_I2C4, PCI_DEVICE_ID_INTEL_CMP_I2C5, + PCI_DEVICE_ID_INTEL_CMP_H_I2C0, + PCI_DEVICE_ID_INTEL_CMP_H_I2C1, + PCI_DEVICE_ID_INTEL_CMP_H_I2C2, + PCI_DEVICE_ID_INTEL_CMP_H_I2C3, PCI_DEVICE_ID_INTEL_TGP_I2C0, PCI_DEVICE_ID_INTEL_TGP_I2C1, PCI_DEVICE_ID_INTEL_TGP_I2C2, diff --git a/src/soc/intel/common/block/p2sb/p2sb.c b/src/soc/intel/common/block/p2sb/p2sb.c index 75c74f298a..4bfb955143 100644 --- a/src/soc/intel/common/block/p2sb/p2sb.c +++ b/src/soc/intel/common/block/p2sb/p2sb.c @@ -179,6 +179,7 @@ static const unsigned short pci_device_ids[] = { PCI_DEVICE_ID_INTEL_CNP_H_P2SB, PCI_DEVICE_ID_INTEL_ICL_P2SB, PCI_DEVICE_ID_INTEL_CMP_P2SB, + PCI_DEVICE_ID_INTEL_CMP_H_P2SB, PCI_DEVICE_ID_INTEL_TGL_P2SB, PCI_DEVICE_ID_INTEL_JSP_PRE_PROD_P2SB, 0, diff --git a/src/soc/intel/common/block/pcie/pcie.c b/src/soc/intel/common/block/pcie/pcie.c index ecc1fcbc71..ce43d3400e 100644 --- a/src/soc/intel/common/block/pcie/pcie.c +++ b/src/soc/intel/common/block/pcie/pcie.c @@ -250,6 +250,30 @@ static const unsigned short pcie_device_ids[] = { PCI_DEVICE_ID_INTEL_CMP_LP_PCIE_RP14, PCI_DEVICE_ID_INTEL_CMP_LP_PCIE_RP15, PCI_DEVICE_ID_INTEL_CMP_LP_PCIE_RP16, + PCI_DEVICE_ID_INTEL_CMP_H_PCIE_RP1, + PCI_DEVICE_ID_INTEL_CMP_H_PCIE_RP2, + PCI_DEVICE_ID_INTEL_CMP_H_PCIE_RP3, + PCI_DEVICE_ID_INTEL_CMP_H_PCIE_RP4, + PCI_DEVICE_ID_INTEL_CMP_H_PCIE_RP5, + PCI_DEVICE_ID_INTEL_CMP_H_PCIE_RP6, + PCI_DEVICE_ID_INTEL_CMP_H_PCIE_RP7, + PCI_DEVICE_ID_INTEL_CMP_H_PCIE_RP8, + PCI_DEVICE_ID_INTEL_CMP_H_PCIE_RP9, + PCI_DEVICE_ID_INTEL_CMP_H_PCIE_RP10, + PCI_DEVICE_ID_INTEL_CMP_H_PCIE_RP11, + PCI_DEVICE_ID_INTEL_CMP_H_PCIE_RP12, + PCI_DEVICE_ID_INTEL_CMP_H_PCIE_RP13, + PCI_DEVICE_ID_INTEL_CMP_H_PCIE_RP14, + PCI_DEVICE_ID_INTEL_CMP_H_PCIE_RP15, + PCI_DEVICE_ID_INTEL_CMP_H_PCIE_RP16, + PCI_DEVICE_ID_INTEL_CMP_H_PCIE_RP17, + PCI_DEVICE_ID_INTEL_CMP_H_PCIE_RP18, + PCI_DEVICE_ID_INTEL_CMP_H_PCIE_RP19, + PCI_DEVICE_ID_INTEL_CMP_H_PCIE_RP20, + PCI_DEVICE_ID_INTEL_CMP_H_PCIE_RP21, + PCI_DEVICE_ID_INTEL_CMP_H_PCIE_RP22, + PCI_DEVICE_ID_INTEL_CMP_H_PCIE_RP23, + PCI_DEVICE_ID_INTEL_CMP_H_PCIE_RP24, PCI_DEVICE_ID_INTEL_TGP_LP_PCIE_RP1, PCI_DEVICE_ID_INTEL_TGP_LP_PCIE_RP2, PCI_DEVICE_ID_INTEL_TGP_LP_PCIE_RP3, diff --git a/src/soc/intel/common/block/pmc/pmc.c b/src/soc/intel/common/block/pmc/pmc.c index 1645070fa7..f3a755bb95 100644 --- a/src/soc/intel/common/block/pmc/pmc.c +++ b/src/soc/intel/common/block/pmc/pmc.c @@ -133,6 +133,7 @@ static const unsigned short pci_device_ids[] = { PCI_DEVICE_ID_INTEL_CNP_H_PMC, PCI_DEVICE_ID_INTEL_ICP_PMC, PCI_DEVICE_ID_INTEL_CMP_PMC, + PCI_DEVICE_ID_INTEL_CMP_H_PMC, PCI_DEVICE_ID_INTEL_TGP_PMC, PCI_DEVICE_ID_INTEL_JSP_PRE_PROD_PMC, 0 diff --git a/src/soc/intel/common/block/sata/sata.c b/src/soc/intel/common/block/sata/sata.c index 0f26262db2..40ffb210a2 100644 --- a/src/soc/intel/common/block/sata/sata.c +++ b/src/soc/intel/common/block/sata/sata.c @@ -96,6 +96,9 @@ static const unsigned short pci_device_ids[] = { PCI_DEVICE_ID_INTEL_CMP_SATA, PCI_DEVICE_ID_INTEL_CMP_PREMIUM_SATA, PCI_DEVICE_ID_INTEL_CMP_LP_SATA, + PCI_DEVICE_ID_INTEL_CMP_H_SATA, + PCI_DEVICE_ID_INTEL_CMP_H_HALO_SATA, + PCI_DEVICE_ID_INTEL_CMP_H_PREMIUM_SATA, PCI_DEVICE_ID_INTEL_TGP_LP_SATA, PCI_DEVICE_ID_INTEL_TGP_SATA, PCI_DEVICE_ID_INTEL_TGP_PREMIUM_SATA, diff --git a/src/soc/intel/common/block/scs/sd.c b/src/soc/intel/common/block/scs/sd.c index e94e4e97c4..e815287dd6 100644 --- a/src/soc/intel/common/block/scs/sd.c +++ b/src/soc/intel/common/block/scs/sd.c @@ -73,6 +73,7 @@ static const unsigned short pci_device_ids[] = { PCI_DEVICE_ID_INTEL_CNP_H_SD, PCI_DEVICE_ID_INTEL_ICL_SD, PCI_DEVICE_ID_INTEL_CMP_SD, + PCI_DEVICE_ID_INTEL_CMP_H_SD, PCI_DEVICE_ID_INTEL_JSP_PRE_PROD_SD, 0 }; diff --git a/src/soc/intel/common/block/smbus/smbus.c b/src/soc/intel/common/block/smbus/smbus.c index c9a6b170bd..6be2a5e054 100644 --- a/src/soc/intel/common/block/smbus/smbus.c +++ b/src/soc/intel/common/block/smbus/smbus.c @@ -95,6 +95,7 @@ static const unsigned short pci_device_ids[] = { PCI_DEVICE_ID_INTEL_LWB_SMBUS, PCI_DEVICE_ID_INTEL_ICP_LP_SMBUS, PCI_DEVICE_ID_INTEL_CMP_SMBUS, + PCI_DEVICE_ID_INTEL_CMP_H_SMBUS, PCI_DEVICE_ID_INTEL_TGP_LP_SMBUS, PCI_DEVICE_ID_INTEL_JSP_PRE_PROD_SMBUS, 0 diff --git a/src/soc/intel/common/block/spi/spi.c b/src/soc/intel/common/block/spi/spi.c index eedde756f0..5ce400870d 100644 --- a/src/soc/intel/common/block/spi/spi.c +++ b/src/soc/intel/common/block/spi/spi.c @@ -81,6 +81,10 @@ static const unsigned short pci_device_ids[] = { PCI_DEVICE_ID_INTEL_CMP_SPI1, PCI_DEVICE_ID_INTEL_CMP_SPI2, PCI_DEVICE_ID_INTEL_CMP_HWSEQ_SPI, + PCI_DEVICE_ID_INTEL_CMP_H_SPI0, + PCI_DEVICE_ID_INTEL_CMP_H_SPI1, + PCI_DEVICE_ID_INTEL_CMP_H_SPI2, + PCI_DEVICE_ID_INTEL_CMP_H_HWSEQ_SPI, PCI_DEVICE_ID_INTEL_TGP_SPI0, PCI_DEVICE_ID_INTEL_TGP_GSPI0, PCI_DEVICE_ID_INTEL_TGP_GSPI1, diff --git a/src/soc/intel/common/block/sram/sram.c b/src/soc/intel/common/block/sram/sram.c index 9e44fa3178..a994235588 100644 --- a/src/soc/intel/common/block/sram/sram.c +++ b/src/soc/intel/common/block/sram/sram.c @@ -51,6 +51,7 @@ static const unsigned short pci_device_ids[] = { PCI_DEVICE_ID_INTEL_GLK_SRAM, PCI_DEVICE_ID_INTEL_ICL_SRAM, PCI_DEVICE_ID_INTEL_CMP_SRAM, + PCI_DEVICE_ID_INTEL_CMP_H_SRAM, PCI_DEVICE_ID_INTEL_TGL_SRAM, PCI_DEVICE_ID_INTEL_JSP_PRE_PROD_SRAM, 0, diff --git a/src/soc/intel/common/block/uart/uart.c b/src/soc/intel/common/block/uart/uart.c index 405351691d..bcb04ac85a 100644 --- a/src/soc/intel/common/block/uart/uart.c +++ b/src/soc/intel/common/block/uart/uart.c @@ -275,6 +275,9 @@ static const unsigned short pci_device_ids[] = { PCI_DEVICE_ID_INTEL_CMP_UART0, PCI_DEVICE_ID_INTEL_CMP_UART1, PCI_DEVICE_ID_INTEL_CMP_UART2, + PCI_DEVICE_ID_INTEL_CMP_H_UART0, + PCI_DEVICE_ID_INTEL_CMP_H_UART1, + PCI_DEVICE_ID_INTEL_CMP_H_UART2, PCI_DEVICE_ID_INTEL_TGP_UART0, PCI_DEVICE_ID_INTEL_TGP_UART1, PCI_DEVICE_ID_INTEL_TGP_UART2, diff --git a/src/soc/intel/common/block/xdci/xdci.c b/src/soc/intel/common/block/xdci/xdci.c index 92f3b15da3..2296f9f770 100644 --- a/src/soc/intel/common/block/xdci/xdci.c +++ b/src/soc/intel/common/block/xdci/xdci.c @@ -43,6 +43,7 @@ static const unsigned short pci_device_ids[] = { PCI_DEVICE_ID_INTEL_CNP_H_XDCI, PCI_DEVICE_ID_INTEL_ICP_LP_XDCI, PCI_DEVICE_ID_INTEL_CMP_LP_XDCI, + PCI_DEVICE_ID_INTEL_CMP_H_XDCI, PCI_DEVICE_ID_INTEL_TGP_LP_XDCI, 0 }; diff --git a/src/soc/intel/common/block/xhci/xhci.c b/src/soc/intel/common/block/xhci/xhci.c index af4d132194..e6a7e0db85 100644 --- a/src/soc/intel/common/block/xhci/xhci.c +++ b/src/soc/intel/common/block/xhci/xhci.c @@ -131,6 +131,7 @@ static const unsigned short pci_device_ids[] = { PCI_DEVICE_ID_INTEL_CNP_H_XHCI, PCI_DEVICE_ID_INTEL_ICP_LP_XHCI, PCI_DEVICE_ID_INTEL_CMP_LP_XHCI, + PCI_DEVICE_ID_INTEL_CMP_H_XHCI, PCI_DEVICE_ID_INTEL_TGP_LP_XHCI, PCI_DEVICE_ID_INTEL_JSP_PRE_PROD_XHCI, 0 From 8b4528aae5ebe021d2cfbc3f1ee71360f01dd30c Mon Sep 17 00:00:00 2001 From: Martin Kepplinger Date: Tue, 10 Dec 2019 12:25:00 +0100 Subject: [PATCH 0670/1242] payloads/seabios: Update stable from 1.12.1 to 1.13.0 SeaBIOS 1.13.0 has been tagged on 20191209. Major changes in this release: * Support for reading logical CHS drive information from QEMU * Workaround added for misbehaving optionroms that grab "int19" * The TPM 2 "PCR bank" option can now be set from the TPM menu * SeaVGABIOS support for QEMU "atiext" display * Several bug fixes and code cleanups see http://seabios.org/Releases Change-Id: I37c8a72b0819bc4d19da9f7ab8e90f907e3e4dec Signed-off-by: Martin Kepplinger Reviewed-on: https://review.coreboot.org/c/coreboot/+/37631 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber Reviewed-by: HAOUAS Elyes --- payloads/external/SeaBIOS/Kconfig | 2 +- payloads/external/SeaBIOS/Makefile | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/payloads/external/SeaBIOS/Kconfig b/payloads/external/SeaBIOS/Kconfig index 131c0d2898..8ec7361813 100644 --- a/payloads/external/SeaBIOS/Kconfig +++ b/payloads/external/SeaBIOS/Kconfig @@ -5,7 +5,7 @@ choice default SEABIOS_STABLE config SEABIOS_STABLE - bool "1.12.1" + bool "1.13.0" help Stable SeaBIOS version config SEABIOS_MASTER diff --git a/payloads/external/SeaBIOS/Makefile b/payloads/external/SeaBIOS/Makefile index fd05c0c12a..0086775b8d 100644 --- a/payloads/external/SeaBIOS/Makefile +++ b/payloads/external/SeaBIOS/Makefile @@ -1,5 +1,5 @@ TAG-$(CONFIG_SEABIOS_MASTER)=origin/master -TAG-$(CONFIG_SEABIOS_STABLE)=a5cab58e9a3fb6e168aba919c5669bea406573b4 +TAG-$(CONFIG_SEABIOS_STABLE)=f21b5a4aeb020f2a5e2c6503f906a9349dd2f069 TAG-$(CONFIG_SEABIOS_REVISION)=$(CONFIG_SEABIOS_REVISION_ID) project_git_repo=https://review.coreboot.org/seabios.git From 5232eb1a108c945435b63723c3b53349faabc940 Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Thu, 24 Oct 2019 19:37:50 +0200 Subject: [PATCH 0671/1242] Doc/mb/gigabyte/ga-h61m-s2pv: Correct IFD section Change-Id: Ic94dd7381e9a107081011d083286d27005148557 Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/36301 Tested-by: build bot (Jenkins) Reviewed-by: HAOUAS Elyes Reviewed-by: Nico Huber --- .../mainboard/gigabyte/ga-h61m-s2pv.md | 20 ++++++++----------- 1 file changed, 8 insertions(+), 12 deletions(-) diff --git a/Documentation/mainboard/gigabyte/ga-h61m-s2pv.md b/Documentation/mainboard/gigabyte/ga-h61m-s2pv.md index 06c0ff7e89..84b72ce24b 100644 --- a/Documentation/mainboard/gigabyte/ga-h61m-s2pv.md +++ b/Documentation/mainboard/gigabyte/ga-h61m-s2pv.md @@ -39,27 +39,23 @@ leave the backup chip untouched. The original IFD defines the BIOS region as the whole flash chip. While this is not an issue if flashing a complete image, it confuses flashrom and trashes the -flash chip's contents when using the --ifd option. However, this can be easily -fixed by reading the IFD with flashrom, editing the correct values into it with -ifdtool and then reflashing it. - -Create a layout.txt with the following contents: +flash chip's contents when using the `--ifd` option. A possible workaround is +to create a `layout.txt` file with a non-overlapping BIOS region: 00000000:00000fff fd 00180000:003fffff bios 00001000:0017ffff me -After that, simply run: +After that, use flashrom with the new layout file. For example, to create a +backup of the BIOS region and then flash a `coreboot.rom`, do: ```bash -sudo flashrom -p internal --ifd -i fd -r ifd.rom -ifdtool -n layout.txt ifd.rom -sudo flashrom -p internal --ifd -i fd -w ifd.rom.new +sudo flashrom -p internal -l layout.txt -i bios -r backup.rom +sudo flashrom -p internal -l layout.txt -i bios -w coreboot.rom ``` -After flashing, power cycle the computer to ensure the new IFD is being used. -If only a reboot is done, the old IFD layout is still seen by flashrom, even if -the IFD on the flash chip is correctly defining the new region layout. +Modifying the IFD so that the BIOS region does not overlap would work as well. +However, this makes DualBIOS unable to recover from a bad flash for some reason. ## Technology From 9b7c23292454ad8c04ec82fa03d276bc425fe315 Mon Sep 17 00:00:00 2001 From: Julius Werner Date: Fri, 13 Dec 2019 10:56:10 -0800 Subject: [PATCH 0672/1242] Update vboot submodule to upstream master Updating from commit id 695c56dc: 2019-12-04 Julius Werner Makefile: Make loop unrolling fully controllable by the caller to commit id b10e5e32: 2019-12-09 Yu-Ping Wu vboot: Make 2nvstorage.h private to vboot_reference This brings in 19 new commits. Change-Id: I9cdccd25422aee26620d48d31f83bcf32a7b4809 Signed-off-by: Julius Werner Reviewed-on: https://review.coreboot.org/c/coreboot/+/37717 Reviewed-by: Mathew King Tested-by: build bot (Jenkins) --- 3rdparty/vboot | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/3rdparty/vboot b/3rdparty/vboot index 695c56dc50..b10e5e32cc 160000 --- a/3rdparty/vboot +++ b/3rdparty/vboot @@ -1 +1 @@ -Subproject commit 695c56dc50a59e5c9098c94f41b3d86b8f99baf1 +Subproject commit b10e5e32cc34dba7660b070616d3481742a28e70 From f8e1764bb9696782ad3e525be8be34c3a9e14588 Mon Sep 17 00:00:00 2001 From: Julius Werner Date: Thu, 12 Dec 2019 13:23:06 -0800 Subject: [PATCH 0673/1242] security/vboot: Ensure firmware body size is respected again CB:36845 simplified how coreboot finds the RW CBFS after vboot has and eliminated a layer of caching. Unfortunately, we missed the fact that the former cached value didn't exactly match the FMAP section... it was in fact truncated to the data actually used by vboot. That patch unintentionally broke this truncation which leads to performance regressions on certain CBFS accesses. This patch makes use of a new API function added to vboot (CL:1965920) which we can use to retrieve the real firmware body length as before. (Also stop making all the vb2_context pointers const. vboot generally never marks context pointers as const in its API functions, even when the function doesn't modify the context. Therefore constifying it inside coreboot just makes things weird because it prevents you from calling random API functions for no reason. If we really want const context pointers, that's a refactoring that would have to start inside vboot first.) This patch brings in upstream vboot commit 4b0408d2: 2019-12-12 Julius Werner 2lib: Move firmware body size reporting to separate function Change-Id: I167cd40cb435dbae7f09d6069c9f1ffc1d99fe13 Signed-off-by: Julius Werner Reviewed-on: https://review.coreboot.org/c/coreboot/+/37680 Tested-by: build bot (Jenkins) Reviewed-by: Mathew King --- 3rdparty/vboot | 2 +- src/security/vboot/common.c | 10 ++++++--- src/security/vboot/misc.h | 5 ++--- src/security/vboot/vboot_loader.c | 2 +- src/security/vboot/vboot_logic.c | 35 +++++++++++-------------------- 5 files changed, 23 insertions(+), 31 deletions(-) diff --git a/3rdparty/vboot b/3rdparty/vboot index b10e5e32cc..2843aa62ba 160000 --- a/3rdparty/vboot +++ b/3rdparty/vboot @@ -1 +1 @@ -Subproject commit b10e5e32cc34dba7660b070616d3481742a28e70 +Subproject commit 2843aa62ba7bcaab2abccf16e3f1b8bd7e058fdb diff --git a/src/security/vboot/common.c b/src/security/vboot/common.c index c21fe155a5..214f6fa208 100644 --- a/src/security/vboot/common.c +++ b/src/security/vboot/common.c @@ -68,8 +68,7 @@ struct vb2_context *vboot_get_context(void) return vboot_ctx; } -int vboot_locate_firmware(const struct vb2_context *ctx, - struct region_device *fw) +int vboot_locate_firmware(struct vb2_context *ctx, struct region_device *fw) { const char *name; @@ -78,7 +77,12 @@ int vboot_locate_firmware(const struct vb2_context *ctx, else name = "FW_MAIN_B"; - return fmap_locate_area_as_rdev(name, fw); + int ret = fmap_locate_area_as_rdev(name, fw); + if (ret) + return ret; + + /* Truncate area to the size that was actually signed by vboot. */ + return rdev_chain(fw, fw, 0, vb2api_get_firmware_size(ctx)); } static void vboot_setup_cbmem(int unused) diff --git a/src/security/vboot/misc.h b/src/security/vboot/misc.h index 1fda8b42b2..0b2c8e54a9 100644 --- a/src/security/vboot/misc.h +++ b/src/security/vboot/misc.h @@ -30,7 +30,7 @@ struct vb2_context *vboot_get_context(void); /* * Returns 1 if firmware slot A is used, 0 if slot B is used. */ -static inline int vboot_is_firmware_slot_a(const struct vb2_context *ctx) +static inline int vboot_is_firmware_slot_a(struct vb2_context *ctx) { return !(ctx->flags & VB2_CONTEXT_FW_SLOT_B); } @@ -49,8 +49,7 @@ static inline bool vboot_is_gbb_flag_set(enum vb2_gbb_flag flag) /* * Locates firmware as a region device. Returns 0 on success, -1 on failure. */ -int vboot_locate_firmware(const struct vb2_context *ctx, - struct region_device *fw); +int vboot_locate_firmware(struct vb2_context *ctx, struct region_device *fw); /* * Source: security/vboot/bootmode.c diff --git a/src/security/vboot/vboot_loader.c b/src/security/vboot/vboot_loader.c index 9aaaff2f32..b72c82ba4a 100644 --- a/src/security/vboot/vboot_loader.c +++ b/src/security/vboot/vboot_loader.c @@ -72,7 +72,7 @@ void vboot_run_logic(void) static int vboot_locate(struct region_device *rdev) { - const struct vb2_context *ctx; + struct vb2_context *ctx; /* Don't honor vboot results until the vboot logic has run. */ if (!vboot_logic_executed()) diff --git a/src/security/vboot/vboot_logic.c b/src/security/vboot/vboot_logic.c index 6c4f8fd2a8..1d17a17657 100644 --- a/src/security/vboot/vboot_logic.c +++ b/src/security/vboot/vboot_logic.c @@ -173,10 +173,10 @@ static int handle_digest_result(void *slot_hash, size_t slot_hash_sz) } static vb2_error_t hash_body(struct vb2_context *ctx, - struct region_device *fw_main) + struct region_device *fw_body) { uint64_t load_ts; - uint32_t expected_size; + uint32_t remaining; uint8_t block[TODO_BLOCK_SIZE]; uint8_t hash_digest[VBOOT_MAX_HASH_SIZE]; const size_t hash_digest_sz = sizeof(hash_digest); @@ -197,33 +197,22 @@ static vb2_error_t hash_body(struct vb2_context *ctx, load_ts = timestamp_get(); timestamp_add(TS_START_HASH_BODY, load_ts); - expected_size = region_device_sz(fw_main); + remaining = region_device_sz(fw_body); offset = 0; /* Start the body hash */ - rv = vb2api_init_hash(ctx, VB2_HASH_TAG_FW_BODY, &expected_size); + rv = vb2api_init_hash(ctx, VB2_HASH_TAG_FW_BODY); if (rv) return rv; - /* - * Honor vboot's RW slot size. The expected size is pulled out of - * the preamble and obtained through vb2api_init_hash() above. By - * creating sub region the RW slot portion of the boot media is - * limited. - */ - if (rdev_chain(fw_main, fw_main, 0, expected_size)) { - printk(BIOS_ERR, "Unable to restrict CBFS size.\n"); - return VB2_ERROR_UNKNOWN; - } - /* Extend over the body */ - while (expected_size) { + while (remaining) { uint64_t temp_ts; - if (block_size > expected_size) - block_size = expected_size; + if (block_size > remaining) + block_size = remaining; temp_ts = timestamp_get(); - if (rdev_readat(fw_main, block, offset, block_size) < 0) + if (rdev_readat(fw_body, block, offset, block_size) < 0) return VB2_ERROR_UNKNOWN; load_ts += timestamp_get() - temp_ts; @@ -231,7 +220,7 @@ static vb2_error_t hash_body(struct vb2_context *ctx, if (rv) return rv; - expected_size -= block_size; + remaining -= block_size; offset += block_size; } @@ -309,7 +298,7 @@ ROMSTAGE_CBMEM_INIT_HOOK(vboot_log_and_clear_recovery_mode_switch) void verstage_main(void) { struct vb2_context *ctx; - struct region_device fw_main; + struct region_device fw_body; vb2_error_t rv; timestamp_add_now(TS_START_VBOOT); @@ -405,12 +394,12 @@ void verstage_main(void) } printk(BIOS_INFO, "Phase 4\n"); - rv = vboot_locate_firmware(ctx, &fw_main); + rv = vboot_locate_firmware(ctx, &fw_body); if (rv) die_with_post_code(POST_INVALID_ROM, "Failed to read FMAP to locate firmware"); - rv = hash_body(ctx, &fw_main); + rv = hash_body(ctx, &fw_body); vboot_save_data(ctx); if (rv) { printk(BIOS_INFO, "Reboot requested (%x)\n", rv); From 91c47c0deac054d5b949d1bf1be7c0e7cbf7d545 Mon Sep 17 00:00:00 2001 From: Denis 'GNUtoo' Carikli Date: Mon, 9 Dec 2019 00:40:31 +0100 Subject: [PATCH 0674/1242] asrock/e350m1: Switch away from ROMCC_BOOTBLOCK MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Change-Id: Ie14db10b6a72e19ac67254ca8f95bcf6ac8af8d3 Signed-off-by: Denis 'GNUtoo' Carikli Reviewed-on: https://review.coreboot.org/c/coreboot/+/37703 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki Reviewed-by: Arthur Heymans --- src/mainboard/asrock/e350m1/Kconfig | 1 - src/mainboard/asrock/e350m1/Makefile.inc | 2 ++ src/mainboard/asrock/e350m1/{romstage.c => bootblock.c} | 7 ++----- 3 files changed, 4 insertions(+), 6 deletions(-) rename src/mainboard/asrock/e350m1/{romstage.c => bootblock.c} (85%) diff --git a/src/mainboard/asrock/e350m1/Kconfig b/src/mainboard/asrock/e350m1/Kconfig index 86eaac8ba5..3bbc2a5150 100644 --- a/src/mainboard/asrock/e350m1/Kconfig +++ b/src/mainboard/asrock/e350m1/Kconfig @@ -17,7 +17,6 @@ if BOARD_ASROCK_E350M1 config BOARD_SPECIFIC_OPTIONS def_bool y - select ROMCC_BOOTBLOCK select CPU_AMD_AGESA_FAMILY14 select NORTHBRIDGE_AMD_AGESA_FAMILY14 select SOUTHBRIDGE_AMD_CIMX_SB800 diff --git a/src/mainboard/asrock/e350m1/Makefile.inc b/src/mainboard/asrock/e350m1/Makefile.inc index 440744c479..ffea060d80 100644 --- a/src/mainboard/asrock/e350m1/Makefile.inc +++ b/src/mainboard/asrock/e350m1/Makefile.inc @@ -13,6 +13,8 @@ # GNU General Public License for more details. # +bootblock-y += bootblock.c + romstage-y += buildOpts.c romstage-y += BiosCallOuts.c romstage-y += OemCustomize.c diff --git a/src/mainboard/asrock/e350m1/romstage.c b/src/mainboard/asrock/e350m1/bootblock.c similarity index 85% rename from src/mainboard/asrock/e350m1/romstage.c rename to src/mainboard/asrock/e350m1/bootblock.c index 27a1fac815..ea6aac093a 100644 --- a/src/mainboard/asrock/e350m1/romstage.c +++ b/src/mainboard/asrock/e350m1/bootblock.c @@ -13,16 +13,13 @@ * GNU General Public License for more details. */ -#include +#include #include #include -#include #define SERIAL_DEV PNP_DEV(0x2e, NCT5572D_SP1) - -void board_BeforeAgesa(struct sysinfo *cb) +void bootblock_mainboard_early_init(void) { - sb_Poweron_Init(); nuvoton_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); } From de640781020b10e72dd6a5cda26cab10932e94fe Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ky=C3=B6sti=20M=C3=A4lkki?= Date: Tue, 3 Dec 2019 07:30:26 +0200 Subject: [PATCH 0675/1242] bootblock: Provide some common prototypes MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The split of bootblock initialisation to cpu, northbridge and southbridge is not specific to intel at all, create new header as AMD will want some of these too. Change-Id: I702cc6bad4afee4f61acf58b9155608b28eb417e Signed-off-by: Kyösti Mälkki Reviewed-on: https://review.coreboot.org/c/coreboot/+/37429 Tested-by: build bot (Jenkins) Reviewed-by: Angel Pons --- src/{cpu/intel/car => arch/x86/include/arch}/bootblock.h | 4 ++-- src/cpu/intel/car/bootblock.c | 2 +- src/cpu/intel/haswell/bootblock.c | 2 +- src/cpu/intel/model_206ax/bootblock.c | 2 +- src/northbridge/intel/gm45/bootblock.c | 2 +- src/northbridge/intel/haswell/bootblock.c | 2 +- src/northbridge/intel/i945/bootblock.c | 2 +- src/northbridge/intel/nehalem/bootblock.c | 2 +- src/northbridge/intel/pineview/bootblock.c | 2 +- src/northbridge/intel/sandybridge/bootblock.c | 2 +- src/northbridge/intel/x4x/bootblock.c | 2 +- src/soc/intel/baytrail/bootblock/bootblock.c | 2 +- src/soc/intel/broadwell/bootblock/cpu.c | 4 ++-- src/soc/intel/broadwell/bootblock/pch.c | 2 +- src/soc/intel/broadwell/bootblock/systemagent.c | 2 +- src/southbridge/intel/bd82x6x/bootblock.c | 2 +- src/southbridge/intel/i82371eb/bootblock.c | 2 +- src/southbridge/intel/i82801dx/bootblock.c | 2 +- src/southbridge/intel/i82801gx/bootblock.c | 2 +- src/southbridge/intel/i82801ix/bootblock.c | 2 +- src/southbridge/intel/i82801jx/bootblock.c | 2 +- src/southbridge/intel/ibexpeak/bootblock.c | 2 +- src/southbridge/intel/lynxpoint/bootblock.c | 2 +- 23 files changed, 25 insertions(+), 25 deletions(-) rename src/{cpu/intel/car => arch/x86/include/arch}/bootblock.h (90%) diff --git a/src/cpu/intel/car/bootblock.h b/src/arch/x86/include/arch/bootblock.h similarity index 90% rename from src/cpu/intel/car/bootblock.h rename to src/arch/x86/include/arch/bootblock.h index 5adfd8711d..1ca4a762de 100644 --- a/src/cpu/intel/car/bootblock.h +++ b/src/arch/x86/include/arch/bootblock.h @@ -11,8 +11,8 @@ * GNU General Public License for more details. */ -#ifndef _CPU_INTEL_CAR_BOOTBLOCK_H -#define _CPU_INTEL_CAR_BOOTBLOCK_H +#ifndef __ARCH_BOOTBLOCK_H__ +#define __ARCH_BOOTBLOCK_H__ void bootblock_early_cpu_init(void); void bootblock_early_northbridge_init(void); diff --git a/src/cpu/intel/car/bootblock.c b/src/cpu/intel/car/bootblock.c index 664c2b5074..e60a65a7b2 100644 --- a/src/cpu/intel/car/bootblock.c +++ b/src/cpu/intel/car/bootblock.c @@ -12,7 +12,7 @@ */ #include -#include +#include #include static uint32_t saved_bist; diff --git a/src/cpu/intel/haswell/bootblock.c b/src/cpu/intel/haswell/bootblock.c index 94e5d36e18..70a4682175 100644 --- a/src/cpu/intel/haswell/bootblock.c +++ b/src/cpu/intel/haswell/bootblock.c @@ -13,6 +13,7 @@ #include #include +#include #include #include #include @@ -21,7 +22,6 @@ #include "haswell.h" #include -#include static void set_flex_ratio_to_tdp_nominal(void) { diff --git a/src/cpu/intel/model_206ax/bootblock.c b/src/cpu/intel/model_206ax/bootblock.c index da0333f4bc..a504480bca 100644 --- a/src/cpu/intel/model_206ax/bootblock.c +++ b/src/cpu/intel/model_206ax/bootblock.c @@ -12,11 +12,11 @@ */ #include +#include #include #include #include #include -#include #include "model_206ax.h" diff --git a/src/northbridge/intel/gm45/bootblock.c b/src/northbridge/intel/gm45/bootblock.c index d3aeb030f1..dda2b585f1 100644 --- a/src/northbridge/intel/gm45/bootblock.c +++ b/src/northbridge/intel/gm45/bootblock.c @@ -11,7 +11,7 @@ * GNU General Public License for more details. */ -#include +#include #include /* Just re-define these instead of including gm45.h. It blows up romcc. */ diff --git a/src/northbridge/intel/haswell/bootblock.c b/src/northbridge/intel/haswell/bootblock.c index 2c1bd58dde..04fec6fe65 100644 --- a/src/northbridge/intel/haswell/bootblock.c +++ b/src/northbridge/intel/haswell/bootblock.c @@ -11,8 +11,8 @@ * GNU General Public License for more details. */ +#include #include -#include #include "haswell.h" void bootblock_early_northbridge_init(void) diff --git a/src/northbridge/intel/i945/bootblock.c b/src/northbridge/intel/i945/bootblock.c index e86abe5ab1..38564bded1 100644 --- a/src/northbridge/intel/i945/bootblock.c +++ b/src/northbridge/intel/i945/bootblock.c @@ -11,7 +11,7 @@ * GNU General Public License for more details. */ -#include +#include #include #include "i945.h" diff --git a/src/northbridge/intel/nehalem/bootblock.c b/src/northbridge/intel/nehalem/bootblock.c index 46cdef0c47..2f9f7da916 100644 --- a/src/northbridge/intel/nehalem/bootblock.c +++ b/src/northbridge/intel/nehalem/bootblock.c @@ -11,8 +11,8 @@ * GNU General Public License for more details. */ +#include #include -#include void bootblock_early_northbridge_init(void) { diff --git a/src/northbridge/intel/pineview/bootblock.c b/src/northbridge/intel/pineview/bootblock.c index bd510b00ee..98085a7406 100644 --- a/src/northbridge/intel/pineview/bootblock.c +++ b/src/northbridge/intel/pineview/bootblock.c @@ -11,8 +11,8 @@ * GNU General Public License for more details. */ +#include #include -#include #include "pineview.h" #define MMCONF_256_BUSSES 16 diff --git a/src/northbridge/intel/sandybridge/bootblock.c b/src/northbridge/intel/sandybridge/bootblock.c index 40819bf7eb..74114963c3 100644 --- a/src/northbridge/intel/sandybridge/bootblock.c +++ b/src/northbridge/intel/sandybridge/bootblock.c @@ -11,8 +11,8 @@ * GNU General Public License for more details. */ +#include #include -#include #include "sandybridge.h" void bootblock_early_northbridge_init(void) diff --git a/src/northbridge/intel/x4x/bootblock.c b/src/northbridge/intel/x4x/bootblock.c index 64643dd79c..0120132c78 100644 --- a/src/northbridge/intel/x4x/bootblock.c +++ b/src/northbridge/intel/x4x/bootblock.c @@ -14,8 +14,8 @@ * GNU General Public License for more details. */ +#include #include -#include #include "x4x.h" #include "iomap.h" diff --git a/src/soc/intel/baytrail/bootblock/bootblock.c b/src/soc/intel/baytrail/bootblock/bootblock.c index 1c5bfc54d6..b5a786bdf5 100644 --- a/src/soc/intel/baytrail/bootblock/bootblock.c +++ b/src/soc/intel/baytrail/bootblock/bootblock.c @@ -13,7 +13,7 @@ * GNU General Public License for more details. */ -#include +#include #include #include #include diff --git a/src/soc/intel/broadwell/bootblock/cpu.c b/src/soc/intel/broadwell/bootblock/cpu.c index f3c35f3441..4c6ab75ef9 100644 --- a/src/soc/intel/broadwell/bootblock/cpu.c +++ b/src/soc/intel/broadwell/bootblock/cpu.c @@ -14,15 +14,15 @@ */ #include +#include +#include #include #include #include -#include #include #include #include #include -#include static void set_flex_ratio_to_tdp_nominal(void) { diff --git a/src/soc/intel/broadwell/bootblock/pch.c b/src/soc/intel/broadwell/bootblock/pch.c index 590961b361..7ea4a58e1f 100644 --- a/src/soc/intel/broadwell/bootblock/pch.c +++ b/src/soc/intel/broadwell/bootblock/pch.c @@ -13,6 +13,7 @@ * GNU General Public License for more details. */ +#include #include #include #include @@ -22,7 +23,6 @@ #include #include #include -#include /* * Enable Prefetching and Caching. diff --git a/src/soc/intel/broadwell/bootblock/systemagent.c b/src/soc/intel/broadwell/bootblock/systemagent.c index 7aaed789ac..c9c7d95ca6 100644 --- a/src/soc/intel/broadwell/bootblock/systemagent.c +++ b/src/soc/intel/broadwell/bootblock/systemagent.c @@ -13,10 +13,10 @@ * GNU General Public License for more details. */ +#include #include #include #include -#include void bootblock_early_northbridge_init(void) { diff --git a/src/southbridge/intel/bd82x6x/bootblock.c b/src/southbridge/intel/bd82x6x/bootblock.c index 1a8242f8d4..f2e32da130 100644 --- a/src/southbridge/intel/bd82x6x/bootblock.c +++ b/src/southbridge/intel/bd82x6x/bootblock.c @@ -13,7 +13,7 @@ * GNU General Public License for more details. */ -#include +#include #include #include "pch.h" diff --git a/src/southbridge/intel/i82371eb/bootblock.c b/src/southbridge/intel/i82371eb/bootblock.c index a6d62e03e0..711b317e16 100644 --- a/src/southbridge/intel/i82371eb/bootblock.c +++ b/src/southbridge/intel/i82371eb/bootblock.c @@ -15,10 +15,10 @@ */ #include +#include #include #include #include -#include #include "i82371eb.h" #define PCI_ID(VENDOR_ID, DEVICE_ID) \ diff --git a/src/southbridge/intel/i82801dx/bootblock.c b/src/southbridge/intel/i82801dx/bootblock.c index ef348553cc..31452a58cf 100644 --- a/src/southbridge/intel/i82801dx/bootblock.c +++ b/src/southbridge/intel/i82801dx/bootblock.c @@ -11,7 +11,7 @@ * GNU General Public License for more details. */ -#include +#include #include void bootblock_early_southbridge_init(void) diff --git a/src/southbridge/intel/i82801gx/bootblock.c b/src/southbridge/intel/i82801gx/bootblock.c index 4c464ff920..f470526589 100644 --- a/src/southbridge/intel/i82801gx/bootblock.c +++ b/src/southbridge/intel/i82801gx/bootblock.c @@ -13,8 +13,8 @@ * GNU General Public License for more details. */ +#include #include -#include #include "i82801gx.h" static void enable_spi_prefetch(void) diff --git a/src/southbridge/intel/i82801ix/bootblock.c b/src/southbridge/intel/i82801ix/bootblock.c index 0b50d61fba..b2701514a9 100644 --- a/src/southbridge/intel/i82801ix/bootblock.c +++ b/src/southbridge/intel/i82801ix/bootblock.c @@ -13,8 +13,8 @@ * GNU General Public License for more details. */ +#include #include -#include #include "i82801ix.h" diff --git a/src/southbridge/intel/i82801jx/bootblock.c b/src/southbridge/intel/i82801jx/bootblock.c index b6016793c2..567679ebcc 100644 --- a/src/southbridge/intel/i82801jx/bootblock.c +++ b/src/southbridge/intel/i82801jx/bootblock.c @@ -13,8 +13,8 @@ * GNU General Public License for more details. */ +#include #include -#include #include "i82801jx.h" static void enable_spi_prefetch(void) diff --git a/src/southbridge/intel/ibexpeak/bootblock.c b/src/southbridge/intel/ibexpeak/bootblock.c index c8b1d6ef31..0076864db9 100644 --- a/src/southbridge/intel/ibexpeak/bootblock.c +++ b/src/southbridge/intel/ibexpeak/bootblock.c @@ -13,8 +13,8 @@ * GNU General Public License for more details. */ +#include #include -#include #include "pch.h" #include "chip.h" diff --git a/src/southbridge/intel/lynxpoint/bootblock.c b/src/southbridge/intel/lynxpoint/bootblock.c index 39e69257eb..21475745c1 100644 --- a/src/southbridge/intel/lynxpoint/bootblock.c +++ b/src/southbridge/intel/lynxpoint/bootblock.c @@ -13,8 +13,8 @@ * GNU General Public License for more details. */ +#include #include -#include #include "pch.h" /* From b17a0f592c4d725958539a089df0f9b22ac2d7e2 Mon Sep 17 00:00:00 2001 From: Arthur Heymans Date: Mon, 25 Nov 2019 23:26:36 +0100 Subject: [PATCH 0676/1242] sb/intel/*: Remove romcc guards These platforms now use a GCC compiled bootblock. Change-Id: I9a0139f497fe84860664195ed6584f90daecec16 Signed-off-by: Arthur Heymans Reviewed-on: https://review.coreboot.org/c/coreboot/+/37217 Tested-by: build bot (Jenkins) Reviewed-by: HAOUAS Elyes Reviewed-by: Angel Pons --- src/southbridge/intel/bd82x6x/pch.h | 2 -- src/southbridge/intel/i82371eb/i82371eb.h | 2 -- src/southbridge/intel/i82801gx/i82801gx.h | 2 -- src/southbridge/intel/ibexpeak/pch.h | 2 -- 4 files changed, 8 deletions(-) diff --git a/src/southbridge/intel/bd82x6x/pch.h b/src/southbridge/intel/bd82x6x/pch.h index 127fb61cce..089d4586bf 100644 --- a/src/southbridge/intel/bd82x6x/pch.h +++ b/src/southbridge/intel/bd82x6x/pch.h @@ -90,10 +90,8 @@ struct southbridge_usb_port int oc_pin; }; -#ifndef __ROMCC__ void pch_enable(struct device *dev); extern const struct southbridge_usb_port mainboard_usb_ports[14]; -#endif void early_usb_init(const struct southbridge_usb_port *portmap); diff --git a/src/southbridge/intel/i82371eb/i82371eb.h b/src/southbridge/intel/i82371eb/i82371eb.h index 77931cb20c..d35b215ab1 100644 --- a/src/southbridge/intel/i82371eb/i82371eb.h +++ b/src/southbridge/intel/i82371eb/i82371eb.h @@ -19,10 +19,8 @@ #if !defined(__ACPI__) -#ifndef __ROMCC__ #include void i82371eb_enable(struct device *dev); -#endif void i82371eb_hard_reset(void); diff --git a/src/southbridge/intel/i82801gx/i82801gx.h b/src/southbridge/intel/i82801gx/i82801gx.h index 3d27faafad..0516a7a171 100644 --- a/src/southbridge/intel/i82801gx/i82801gx.h +++ b/src/southbridge/intel/i82801gx/i82801gx.h @@ -34,10 +34,8 @@ #ifndef __ACPI__ #define DEBUG_PERIODIC_SMIS 0 -#ifndef __ROMCC__ #include void i82801gx_enable(struct device *dev); -#endif void enable_smbus(void); void i82801gx_lpc_setup(void); diff --git a/src/southbridge/intel/ibexpeak/pch.h b/src/southbridge/intel/ibexpeak/pch.h index 9ee76f22f4..5785ef1a67 100644 --- a/src/southbridge/intel/ibexpeak/pch.h +++ b/src/southbridge/intel/ibexpeak/pch.h @@ -89,11 +89,9 @@ struct southbridge_usb_port { void early_usb_init(const struct southbridge_usb_port *portmap); -#ifndef __ROMCC__ extern const struct southbridge_usb_port mainboard_usb_ports[14]; #include void pch_enable(struct device *dev); -#endif #define MAINBOARD_POWER_OFF 0 #define MAINBOARD_POWER_ON 1 From 9efc7fc540d3b235274448d986747eab226b999d Mon Sep 17 00:00:00 2001 From: Nico Huber Date: Fri, 13 Dec 2019 19:33:32 +0100 Subject: [PATCH 0677/1242] Revert "crossgcc: Upgrade acpica to version 20191018" MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This reverts commit 547de69de73629c051e9b5312f6369744ec6ce8f. Merged out of order before CB:36317. The conflicting use of _ADR and _HID needs to be properly addressed before we can bump the IASL version. Change-Id: Iacbc9877a8ff2324eba4789d65df8545b8a25413 Signed-off-by: Nico Huber Reviewed-on: https://review.coreboot.org/c/coreboot/+/37713 Reviewed-by: HAOUAS Elyes Reviewed-by: Kyösti Mälkki Reviewed-by: Angel Pons Tested-by: build bot (Jenkins) --- util/crossgcc/buildgcc | 2 +- ...ix2-20191018_iasl.patch => acpica-unix2-20190703_iasl.patch} | 0 util/crossgcc/sum/acpica-unix2-20190703.tar.gz.cksum | 1 + util/crossgcc/sum/acpica-unix2-20191018.tar.gz.cksum | 1 - 4 files changed, 2 insertions(+), 2 deletions(-) rename util/crossgcc/patches/{acpica-unix2-20191018_iasl.patch => acpica-unix2-20190703_iasl.patch} (100%) create mode 100644 util/crossgcc/sum/acpica-unix2-20190703.tar.gz.cksum delete mode 100644 util/crossgcc/sum/acpica-unix2-20191018.tar.gz.cksum diff --git a/util/crossgcc/buildgcc b/util/crossgcc/buildgcc index f1cf6bb8cf..5dac074a06 100755 --- a/util/crossgcc/buildgcc +++ b/util/crossgcc/buildgcc @@ -54,7 +54,7 @@ GCC_VERSION=8.3.0 GCC_AUTOCONF_VERSION=2.69 BINUTILS_VERSION=2.33.1 GDB_VERSION=8.3.1 -IASL_VERSION=20191018 +IASL_VERSION=20190703 PYTHON_VERSION=3.8.0 EXPAT_VERSION=2.2.9 # CLANG version number diff --git a/util/crossgcc/patches/acpica-unix2-20191018_iasl.patch b/util/crossgcc/patches/acpica-unix2-20190703_iasl.patch similarity index 100% rename from util/crossgcc/patches/acpica-unix2-20191018_iasl.patch rename to util/crossgcc/patches/acpica-unix2-20190703_iasl.patch diff --git a/util/crossgcc/sum/acpica-unix2-20190703.tar.gz.cksum b/util/crossgcc/sum/acpica-unix2-20190703.tar.gz.cksum new file mode 100644 index 0000000000..9a89796d53 --- /dev/null +++ b/util/crossgcc/sum/acpica-unix2-20190703.tar.gz.cksum @@ -0,0 +1 @@ +c5594944f933265a53695204a0672d0808e4a580 tarballs/acpica-unix2-20190703.tar.gz diff --git a/util/crossgcc/sum/acpica-unix2-20191018.tar.gz.cksum b/util/crossgcc/sum/acpica-unix2-20191018.tar.gz.cksum deleted file mode 100644 index 3df9d27cb3..0000000000 --- a/util/crossgcc/sum/acpica-unix2-20191018.tar.gz.cksum +++ /dev/null @@ -1 +0,0 @@ -792e2ec4dcd78646de8405578d28f7437aacf811 tarballs/acpica-unix2-20191018.tar.gz From 7176a54c2b4c1a95219c5ab9e7b7b12a8ab6b0e2 Mon Sep 17 00:00:00 2001 From: Nico Huber Date: Fri, 13 Dec 2019 17:08:49 +0100 Subject: [PATCH 0678/1242] Revert "{northbridge,soc,southbridge}: Don't use both of _ADR and _HID" MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This reverts commit 01787608670adec26fcea48173e18395e51c790e. AMD: Dropping the _HID of PCI root bus doesn't work well and people started to notice the breakage. Intel: These platforms have a devicetree switch to choose between PCI and ACPI modes. In the former case we need _ADR, but in the latter _HID as the PCI devices are hidden. The conflicting use of _ADR and _HID still needs to be fixed before we can bump our IASL version. Change-Id: If7b52b9e8f2f53574849aa3fddfccfa016288179 Signed-off-by: Nico Huber Reviewed-on: https://review.coreboot.org/c/coreboot/+/37710 Reviewed-by: HAOUAS Elyes Reviewed-by: Kyösti Mälkki Reviewed-by: Angel Pons Tested-by: build bot (Jenkins) --- src/northbridge/amd/agesa/family14/acpi/northbridge.asl | 3 ++- .../amd/agesa/family15tn/acpi/northbridge.asl | 2 +- .../amd/agesa/family16kb/acpi/northbridge.asl | 2 +- src/northbridge/amd/pi/00630F01/acpi/northbridge.asl | 2 +- src/northbridge/amd/pi/00660F01/acpi/northbridge.asl | 2 +- src/northbridge/amd/pi/00730F01/acpi/northbridge.asl | 3 ++- src/soc/amd/stoneyridge/acpi/northbridge.asl | 2 +- src/soc/intel/broadwell/acpi/serialio.asl | 9 ++++++++- src/southbridge/intel/lynxpoint/acpi/serialio.asl | 9 ++++++++- 9 files changed, 25 insertions(+), 9 deletions(-) diff --git a/src/northbridge/amd/agesa/family14/acpi/northbridge.asl b/src/northbridge/amd/agesa/family14/acpi/northbridge.asl index fad157da29..06199a1b07 100644 --- a/src/northbridge/amd/agesa/family14/acpi/northbridge.asl +++ b/src/northbridge/amd/agesa/family14/acpi/northbridge.asl @@ -16,7 +16,7 @@ /* Note: Only need HID on Primary Bus */ External (TOM1) External (TOM2) -/* Name(_HID, EISAID("PNP0A08")) // PCI Express Root Bridge */ +Name(_HID, EISAID("PNP0A08")) /* PCI Express Root Bridge */ Name(_CID, EISAID("PNP0A03")) /* PCI Root Bridge */ Name(_ADR, 0x00180000) /* Dev# = BSP Dev#, Func# = 0 */ @@ -125,6 +125,7 @@ Device(PE23) { /* Northbridge function 3 */ Device(NBF3) { + Name(_ADR, 0x00180003) /* k10temp thermal zone */ #include "thermal_mixin.asl" diff --git a/src/northbridge/amd/agesa/family15tn/acpi/northbridge.asl b/src/northbridge/amd/agesa/family15tn/acpi/northbridge.asl index 96c2d8bfac..9a1fa9ed88 100644 --- a/src/northbridge/amd/agesa/family15tn/acpi/northbridge.asl +++ b/src/northbridge/amd/agesa/family15tn/acpi/northbridge.asl @@ -16,7 +16,7 @@ /* Note: Only need HID on Primary Bus */ External (TOM1) External (TOM2) -/* Name(_HID, EISAID("PNP0A03")) // PCI Express Root Bridge */ +Name(_HID, EISAID("PNP0A03")) /* PCI Express Root Bridge */ Name(_ADR, 0x00180000) /* Dev# = BSP Dev#, Func# = 0 */ /* Describe the Northbridge devices */ diff --git a/src/northbridge/amd/agesa/family16kb/acpi/northbridge.asl b/src/northbridge/amd/agesa/family16kb/acpi/northbridge.asl index a7e8307349..f74b31a080 100644 --- a/src/northbridge/amd/agesa/family16kb/acpi/northbridge.asl +++ b/src/northbridge/amd/agesa/family16kb/acpi/northbridge.asl @@ -16,7 +16,7 @@ /* Note: Only need HID on Primary Bus */ External (TOM1) External (TOM2) -/* Name(_HID, EISAID("PNP0A08")) // PCI Express Root Bridge */ +Name(_HID, EISAID("PNP0A08")) /* PCI Express Root Bridge */ Name(_CID, EISAID("PNP0A03")) /* PCI Root Bridge */ Name(_ADR, 0x00180000) /* Dev# = BSP Dev#, Func# = 0 */ diff --git a/src/northbridge/amd/pi/00630F01/acpi/northbridge.asl b/src/northbridge/amd/pi/00630F01/acpi/northbridge.asl index de47bc2151..c2b3aac4c5 100644 --- a/src/northbridge/amd/pi/00630F01/acpi/northbridge.asl +++ b/src/northbridge/amd/pi/00630F01/acpi/northbridge.asl @@ -16,7 +16,7 @@ /* Note: Only need HID on Primary Bus */ External (TOM1) External (TOM2) -/* Name(_HID, EISAID("PNP0A03")) // PCI Express Root Bridge */ +Name(_HID, EISAID("PNP0A03")) /* PCI Express Root Bridge */ Name(_ADR, 0x00180000) /* Dev# = BSP Dev#, Func# = 0 */ /* Describe the Northbridge devices */ diff --git a/src/northbridge/amd/pi/00660F01/acpi/northbridge.asl b/src/northbridge/amd/pi/00660F01/acpi/northbridge.asl index 4a48aaf401..d54f985e90 100644 --- a/src/northbridge/amd/pi/00660F01/acpi/northbridge.asl +++ b/src/northbridge/amd/pi/00660F01/acpi/northbridge.asl @@ -16,7 +16,7 @@ /* Note: Only need HID on Primary Bus */ External (TOM1) External (TOM2) -/* Name(_HID, EISAID("PNP0A08")) // PCI Express Root Bridge */ +Name(_HID, EISAID("PNP0A08")) /* PCI Express Root Bridge */ Name(_CID, EISAID("PNP0A03")) /* PCI Root Bridge */ Name(_ADR, 0x00180000) /* Dev# = BSP Dev#, Func# = 0 */ diff --git a/src/northbridge/amd/pi/00730F01/acpi/northbridge.asl b/src/northbridge/amd/pi/00730F01/acpi/northbridge.asl index b317ccf1ea..f74b31a080 100644 --- a/src/northbridge/amd/pi/00730F01/acpi/northbridge.asl +++ b/src/northbridge/amd/pi/00730F01/acpi/northbridge.asl @@ -16,9 +16,10 @@ /* Note: Only need HID on Primary Bus */ External (TOM1) External (TOM2) -/* Name(_HID, EISAID("PNP0A08")) // PCI Express Root Bridge */ +Name(_HID, EISAID("PNP0A08")) /* PCI Express Root Bridge */ Name(_CID, EISAID("PNP0A03")) /* PCI Root Bridge */ Name(_ADR, 0x00180000) /* Dev# = BSP Dev#, Func# = 0 */ + /* Describe the Northbridge devices */ Method(_BBN, 0, NotSerialized) /* Bus number = 0 */ diff --git a/src/soc/amd/stoneyridge/acpi/northbridge.asl b/src/soc/amd/stoneyridge/acpi/northbridge.asl index 09bf2e18c2..fe78534403 100644 --- a/src/soc/amd/stoneyridge/acpi/northbridge.asl +++ b/src/soc/amd/stoneyridge/acpi/northbridge.asl @@ -17,7 +17,7 @@ /* Note: Only need HID on Primary Bus */ External (TOM1) External (TOM2) -/* Name(_HID, EISAID("PNP0A08")) // PCI Express Root Bridge */ +Name(_HID, EISAID("PNP0A08")) /* PCI Express Root Bridge */ Name(_CID, EISAID("PNP0A03")) /* PCI Root Bridge */ Name(_ADR, 0x00180000) /* Dev# = BSP Dev#, Func# = 0 */ diff --git a/src/soc/intel/broadwell/acpi/serialio.asl b/src/soc/intel/broadwell/acpi/serialio.asl index fd25b0d8a8..1b44e9566a 100644 --- a/src/soc/intel/broadwell/acpi/serialio.asl +++ b/src/soc/intel/broadwell/acpi/serialio.asl @@ -157,7 +157,7 @@ Device (SIOR) Device (SDMA) { // Serial IO DMA Controller - /* Name (_HID, "INTL9C60") */ + Name (_HID, "INTL9C60") Name (_UID, 1) Name (_ADR, 0x00150000) @@ -205,6 +205,7 @@ Device (I2C0) Return ("INT33C2") } Name (_UID, 1) + Name (_ADR, 0x00150001) Name (SSCN, Package () { 432, 507, 30 }) Name (FMCN, Package () { 72, 160, 30 }) @@ -275,6 +276,7 @@ Device (I2C1) Return ("INT33C3") } Name (_UID, 1) + Name (_ADR, 0x00150002) Name (SSCN, Package () { 432, 507, 30 }) Name (FMCN, Package () { 72, 160, 30 }) @@ -345,6 +347,7 @@ Device (SPI0) Return ("INT33C0") } Name (_UID, 1) + Name (_ADR, 0x00150003) // BAR0 is assigned during PCI enumeration and saved into NVS Name (RBUF, ResourceTemplate () @@ -400,6 +403,7 @@ Device (SPI1) Return ("INT33C1") } Name (_UID, 1) + Name (_ADR, 0x00150004) // BAR0 is assigned during PCI enumeration and saved into NVS Name (RBUF, ResourceTemplate () @@ -467,6 +471,7 @@ Device (UAR0) Return ("INT33C4") } Name (_UID, 1) + Name (_ADR, 0x00150005) // BAR0 is assigned during PCI enumeration and saved into NVS Name (RBUF, ResourceTemplate () @@ -534,6 +539,7 @@ Device (UAR1) Return ("INT33C5") } Name (_UID, 1) + Name (_ADR, 0x00150006) // BAR0 is assigned during PCI enumeration and saved into NVS Name (RBUF, ResourceTemplate () @@ -590,6 +596,7 @@ Device (SDIO) } Name (_CID, "PNP0D40") Name (_UID, 1) + Name (_ADR, 0x00170000) // BAR0 is assigned during PCI enumeration and saved into NVS Name (RBUF, ResourceTemplate () diff --git a/src/southbridge/intel/lynxpoint/acpi/serialio.asl b/src/southbridge/intel/lynxpoint/acpi/serialio.asl index 0eebe32dd6..9323b91cac 100644 --- a/src/southbridge/intel/lynxpoint/acpi/serialio.asl +++ b/src/southbridge/intel/lynxpoint/acpi/serialio.asl @@ -123,7 +123,7 @@ Device (SIOR) Device (SDMA) { // Serial IO DMA Controller - /* Name (_HID, "INTL9C60") */ + Name (_HID, "INTL9C60") Name (_UID, 1) Name (_ADR, 0x00150000) @@ -163,6 +163,7 @@ Device (I2C0) Name (_HID, "INT33C2") Name (_CID, "INT33C2") Name (_UID, 1) + Name (_ADR, 0x00150001) Name (SSCN, Package () { 432, 507, 30 }) Name (FMCN, Package () { 72, 160, 30 }) @@ -244,6 +245,7 @@ Device (I2C1) Name (_HID, "INT33C3") Name (_CID, "INT33C3") Name (_UID, 1) + Name (_ADR, 0x00150002) Name (SSCN, Package () { 432, 507, 30 }) Name (FMCN, Package () { 72, 160, 30 }) @@ -325,6 +327,7 @@ Device (SPI0) Name (_HID, "INT33C0") Name (_CID, "INT33C0") Name (_UID, 1) + Name (_ADR, 0x00150003) // BAR0 is assigned during PCI enumeration and saved into NVS Name (RBUF, ResourceTemplate () @@ -362,6 +365,7 @@ Device (SPI1) Name (_HID, "INT33C1") Name (_CID, "INT33C1") Name (_UID, 1) + Name (_ADR, 0x00150004) // BAR0 is assigned during PCI enumeration and saved into NVS Name (RBUF, ResourceTemplate () @@ -412,6 +416,7 @@ Device (UAR0) Name (_HID, "INT33C4") Name (_CID, "INT33C4") Name (_UID, 1) + Name (_ADR, 0x00150005) // BAR0 is assigned during PCI enumeration and saved into NVS Name (RBUF, ResourceTemplate () @@ -462,6 +467,7 @@ Device (UAR1) Name (_HID, "INT33C5") Name (_CID, "INT33C5") Name (_UID, 1) + Name (_ADR, 0x00150006) // BAR0 is assigned during PCI enumeration and saved into NVS Name (RBUF, ResourceTemplate () @@ -499,6 +505,7 @@ Device (SDIO) Name (_HID, "INT33C6") Name (_CID, "PNP0D40") Name (_UID, 1) + Name (_ADR, 0x00170000) // BAR0 is assigned during PCI enumeration and saved into NVS Name (RBUF, ResourceTemplate () From 1a5c3bb7fa56378664ce221cd749f118ef6a09f6 Mon Sep 17 00:00:00 2001 From: Edward O'Callaghan Date: Fri, 13 Dec 2019 23:37:22 +1100 Subject: [PATCH 0679/1242] mainboard/google/puff: Toggle on DqPinsInterleaved BRANCH=none BUG=b:146172098 TEST=./util/abuild/abuild -p none -t google/hatch -x -a Change-Id: Ib2da3baace9255ef25c0f03390a064fd77ef9ae5 Signed-off-by: Edward O'Callaghan Reviewed-on: https://review.coreboot.org/c/coreboot/+/37696 Tested-by: build bot (Jenkins) Reviewed-by: Angel Pons Reviewed-by: Furquan Shaikh Reviewed-by: Kangheui Won --- src/mainboard/google/hatch/romstage_spd_smbus.c | 1 + 1 file changed, 1 insertion(+) diff --git a/src/mainboard/google/hatch/romstage_spd_smbus.c b/src/mainboard/google/hatch/romstage_spd_smbus.c index 74d59a59f5..9073744850 100644 --- a/src/mainboard/google/hatch/romstage_spd_smbus.c +++ b/src/mainboard/google/hatch/romstage_spd_smbus.c @@ -45,6 +45,7 @@ void mainboard_memory_init_params(FSPM_UPD *memupd) /* set to 2 VREF_CA goes to CH_A and VREF_DQ_B goes to CH_B. */ memcfg.vref_ca_config = 2; + memcfg.dq_pins_interleaved = 1; cannonlake_memcfg_init(&memupd->FspmConfig, &memcfg); } From ebcd0a8d8d6f28a3c4962a632e0e374a8fa47908 Mon Sep 17 00:00:00 2001 From: Elyes HAOUAS Date: Fri, 13 Dec 2019 07:57:37 +0100 Subject: [PATCH 0680/1242] mb/roda/rk886ex: Don't rewrite pnp_{enter,exit}_conf_state function Change-Id: Ie9918e5114bb880e37680a85eab2bd224b0b082c Signed-off-by: Elyes HAOUAS Reviewed-on: https://review.coreboot.org/c/coreboot/+/37686 Tested-by: build bot (Jenkins) Reviewed-by: Felix Held --- src/mainboard/roda/rk886ex/early_init.c | 17 ++++------------- 1 file changed, 4 insertions(+), 13 deletions(-) diff --git a/src/mainboard/roda/rk886ex/early_init.c b/src/mainboard/roda/rk886ex/early_init.c index f3e24e0f3b..6f0a12c335 100644 --- a/src/mainboard/roda/rk886ex/early_init.c +++ b/src/mainboard/roda/rk886ex/early_init.c @@ -24,6 +24,8 @@ #include #include #include +#include + #include "option_table.h" /* Override the default lpc decode ranges */ @@ -43,17 +45,6 @@ void mainboard_lpc_decode(void) * the two. Also set up the GPIOs from the beginning. This is the "no schematic * but safe anyways" method. */ -static inline void pnp_enter_ext_func_mode(pnp_devfn_t dev) -{ - unsigned int port = dev >> 8; - outb(0x55, port); -} - -static void pnp_exit_ext_func_mode(pnp_devfn_t dev) -{ - unsigned int port = dev >> 8; - outb(0xaa, port); -} void bootblock_mainboard_early_init(void) { @@ -61,7 +52,7 @@ void bootblock_mainboard_early_init(void) dev = PNP_DEV(0x2e, 0x00); - pnp_enter_ext_func_mode(dev); + pnp_enter_conf_state(dev); pnp_write_config(dev, 0x01, 0x94); /* Extended Parport modes */ pnp_write_config(dev, 0x02, 0x88); /* UART power on */ pnp_write_config(dev, 0x03, 0x72); /* Floppy */ @@ -87,7 +78,7 @@ void bootblock_mainboard_early_init(void) pnp_write_config(dev, 0x38, 0x00); /* GPIO4 POL */ pnp_write_config(dev, 0x39, 0x80); /* GPIO4 POL */ - pnp_exit_ext_func_mode(dev); + pnp_exit_conf_state(dev); } void mainboard_late_rcba_config(void) From 50b82ef2bb44602a62d676f2b9c6900da0ad4162 Mon Sep 17 00:00:00 2001 From: Elyes HAOUAS Date: Sat, 7 Dec 2019 10:37:40 +0100 Subject: [PATCH 0681/1242] mb/msi/ms7721: Don't rewrite pnp_{enter,exit}_conf_state function Change-Id: Ib27c518fb5ce99e17be25b974ff5adc8c6b3f3a6 Signed-off-by: Elyes HAOUAS Reviewed-on: https://review.coreboot.org/c/coreboot/+/37570 Reviewed-by: Felix Held Tested-by: build bot (Jenkins) --- src/mainboard/msi/ms7721/romstage.c | 15 --------------- src/superio/fintek/common/early_serial.c | 4 ++-- src/superio/fintek/common/fintek.h | 3 +++ 3 files changed, 5 insertions(+), 17 deletions(-) diff --git a/src/mainboard/msi/ms7721/romstage.c b/src/mainboard/msi/ms7721/romstage.c index ebb875de63..bec2f40bbb 100644 --- a/src/mainboard/msi/ms7721/romstage.c +++ b/src/mainboard/msi/ms7721/romstage.c @@ -41,21 +41,6 @@ /* GPIO configuration */ -#define FINTEK_ENTRY_KEY 0x87 -static void pnp_enter_conf_state(pnp_devfn_t dev) -{ - u16 port = dev >> 8; - outb(FINTEK_ENTRY_KEY, port); - outb(FINTEK_ENTRY_KEY, port); -} - -#define FINTEK_EXIT_KEY 0xAA -static void pnp_exit_conf_state(pnp_devfn_t dev) -{ - u16 port = dev >> 8; - outb(FINTEK_EXIT_KEY, port); -} - static void gpio_init(pnp_devfn_t dev) { pnp_enter_conf_state(dev); diff --git a/src/superio/fintek/common/early_serial.c b/src/superio/fintek/common/early_serial.c index c625b5327b..d0e0ab072f 100644 --- a/src/superio/fintek/common/early_serial.c +++ b/src/superio/fintek/common/early_serial.c @@ -43,7 +43,7 @@ #define FINTEK_EXIT_KEY 0xAA /* Enable configuration: pass entry key '0x87' into index port dev. */ -static void pnp_enter_conf_state(pnp_devfn_t dev) +void pnp_enter_conf_state(pnp_devfn_t dev) { u16 port = dev >> 8; outb(FINTEK_ENTRY_KEY, port); @@ -51,7 +51,7 @@ static void pnp_enter_conf_state(pnp_devfn_t dev) } /* Disable configuration: pass exit key '0xAA' into index port dev. */ -static void pnp_exit_conf_state(pnp_devfn_t dev) +void pnp_exit_conf_state(pnp_devfn_t dev) { u16 port = dev >> 8; outb(FINTEK_EXIT_KEY, port); diff --git a/src/superio/fintek/common/fintek.h b/src/superio/fintek/common/fintek.h index cbd175f7ac..306edeea7e 100644 --- a/src/superio/fintek/common/fintek.h +++ b/src/superio/fintek/common/fintek.h @@ -22,4 +22,7 @@ void fintek_enable_serial(pnp_devfn_t dev, u16 iobase); +void pnp_enter_conf_state(pnp_devfn_t dev); +void pnp_exit_conf_state(pnp_devfn_t dev); + #endif /* SUPERIO_FINTEK_COMMON_PRE_RAM_H */ From 9f4c4856f385e0951d0ce8238e77f6eaf71d6dd3 Mon Sep 17 00:00:00 2001 From: Idwer Vollering Date: Sat, 14 Dec 2019 18:03:44 +0100 Subject: [PATCH 0682/1242] asus/f2a85-m: switch away from ROMCC_BOOTBLOCK MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Change-Id: I1d7127e2f9bd5bd9677feb2b0e686a854c4e3885 Signed-off-by: Idwer Vollering Reviewed-on: https://review.coreboot.org/c/coreboot/+/37727 Reviewed-by: HAOUAS Elyes Reviewed-by: Kyösti Mälkki Tested-by: build bot (Jenkins) --- src/mainboard/asus/f2a85-m/Kconfig | 1 - src/mainboard/asus/f2a85-m/Makefile.inc | 2 + src/mainboard/asus/f2a85-m/bootblock.c | 68 +++++++++++++++++++++++++ src/mainboard/asus/f2a85-m/romstage.c | 68 ------------------------- 4 files changed, 70 insertions(+), 69 deletions(-) create mode 100644 src/mainboard/asus/f2a85-m/bootblock.c diff --git a/src/mainboard/asus/f2a85-m/Kconfig b/src/mainboard/asus/f2a85-m/Kconfig index cd10e536a4..c1dd063c77 100644 --- a/src/mainboard/asus/f2a85-m/Kconfig +++ b/src/mainboard/asus/f2a85-m/Kconfig @@ -18,7 +18,6 @@ if BOARD_ASUS_F2A85_M || BOARD_ASUS_F2A85_M_PRO || BOARD_ASUS_F2A85_M_LE config BOARD_SPECIFIC_OPTIONS def_bool y - select ROMCC_BOOTBLOCK select CPU_AMD_AGESA_FAMILY15_TN select NORTHBRIDGE_AMD_AGESA_FAMILY15_TN select SOUTHBRIDGE_AMD_AGESA_HUDSON diff --git a/src/mainboard/asus/f2a85-m/Makefile.inc b/src/mainboard/asus/f2a85-m/Makefile.inc index f8895faa92..4dde2cfd1e 100644 --- a/src/mainboard/asus/f2a85-m/Makefile.inc +++ b/src/mainboard/asus/f2a85-m/Makefile.inc @@ -13,6 +13,8 @@ # GNU General Public License for more details. # +bootblock-y += bootblock.c + romstage-y += buildOpts.c romstage-y += BiosCallOuts.c romstage-y += OemCustomize.c diff --git a/src/mainboard/asus/f2a85-m/bootblock.c b/src/mainboard/asus/f2a85-m/bootblock.c new file mode 100644 index 0000000000..648f55a559 --- /dev/null +++ b/src/mainboard/asus/f2a85-m/bootblock.c @@ -0,0 +1,68 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * Copyright (C) 2012 Rudolf Marek + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +#define SB_MMIO_MISC32(x) *(volatile u32 *)(AMD_SB_ACPI_MMIO_ADDR + 0xE00 + (x)) + +static void sbxxx_enable_48mhzout(void) +{ + /* most likely programming to 48MHz out signal */ + u32 reg32; + reg32 = SB_MMIO_MISC32(0x28); + reg32 &= 0xffc7ffff; + reg32 |= 0x00100000; + SB_MMIO_MISC32(0x28) = reg32; + + reg32 = SB_MMIO_MISC32(0x40); + reg32 &= ~0x80u; + SB_MMIO_MISC32(0x40) = reg32; +} + +static void superio_init_m(void) +{ + pnp_devfn_t uart = PNP_DEV(0x2e, IT8728F_SP1); + pnp_devfn_t gpio = PNP_DEV(0x2e, IT8728F_GPIO); + + ite_kill_watchdog(gpio); + ite_enable_serial(uart, CONFIG_TTYS0_BASE); + ite_enable_3vsbsw(gpio); +} + +static void superio_init_m_pro(void) +{ + pnp_devfn_t uart = PNP_DEV(0x2e, NCT6779D_SP1); + + nuvoton_enable_serial(uart, CONFIG_TTYS0_BASE); +} + +void bootblock_mainboard_early_init(void) +{ + /* enable SIO clock */ + sbxxx_enable_48mhzout(); + + if (CONFIG(BOARD_ASUS_F2A85_M_PRO)) + superio_init_m_pro(); + else + superio_init_m(); +} diff --git a/src/mainboard/asus/f2a85-m/romstage.c b/src/mainboard/asus/f2a85-m/romstage.c index 8a48e0080c..3aa29c8ce3 100644 --- a/src/mainboard/asus/f2a85-m/romstage.c +++ b/src/mainboard/asus/f2a85-m/romstage.c @@ -15,84 +15,16 @@ */ #include -#include -#include -#include #include -#include -#include #include #include -#include -#include -#include -#include - -#define MMIO_NON_POSTED_START 0xfed00000 -#define MMIO_NON_POSTED_END 0xfedfffff -#define SB_MMIO_MISC32(x) *(volatile u32 *)(AMD_SB_ACPI_MMIO_ADDR + 0xE00 + (x)) - -static void sbxxx_enable_48mhzout(void) -{ - /* most likely programming to 48MHz out signal */ - u32 reg32; - reg32 = SB_MMIO_MISC32(0x28); - reg32 &= 0xffc7ffff; - reg32 |= 0x00100000; - SB_MMIO_MISC32(0x28) = reg32; - - reg32 = SB_MMIO_MISC32(0x40); - reg32 &= ~0x80u; - SB_MMIO_MISC32(0x40) = reg32; -} - -static void superio_init_m(void) -{ - pnp_devfn_t uart = PNP_DEV(0x2e, IT8728F_SP1); - pnp_devfn_t gpio = PNP_DEV(0x2e, IT8728F_GPIO); - - ite_kill_watchdog(gpio); - ite_enable_serial(uart, CONFIG_TTYS0_BASE); - ite_enable_3vsbsw(gpio); -} - -static void superio_init_m_pro(void) -{ - pnp_devfn_t uart = PNP_DEV(0x2e, NCT6779D_SP1); - - nuvoton_enable_serial(uart, CONFIG_TTYS0_BASE); -} void board_BeforeAgesa(struct sysinfo *cb) { u8 byte; - pci_devfn_t dev; - - /* enable SIO LPC decode */ - dev = PCI_DEV(0, 0x14, 3); - byte = pci_read_config8(dev, 0x48); - byte |= 3; /* 2e, 2f */ - pci_write_config8(dev, 0x48, byte); - - /* enable serial decode */ - byte = pci_read_config8(dev, 0x44); - byte |= (1 << 6); /* 0x3f8 */ - pci_write_config8(dev, 0x44, byte); post_code(0x30); - /* enable SB MMIO space */ - outb(0x24, 0xcd6); - outb(0x1, 0xcd7); - - /* enable SIO clock */ - sbxxx_enable_48mhzout(); - - if (CONFIG(BOARD_ASUS_F2A85_M_PRO)) - superio_init_m_pro(); - else - superio_init_m(); - /* turn on secondary smbus at b20 */ outb(0x28, 0xcd6); byte = inb(0xcd7); From d912df22a8fde68dc513824d757b71eb16703479 Mon Sep 17 00:00:00 2001 From: Marshall Dawson Date: Fri, 13 Dec 2019 18:13:42 -0700 Subject: [PATCH 0683/1242] drivers/mrc_cache: Redo indenting Indent continuation lines of an if test farther than its "true" expression to be executed. Change-Id: I3dfa4049761095dcbb6797f1533d6a513e3b503c Signed-off-by: Marshall Dawson Reviewed-on: https://review.coreboot.org/c/coreboot/+/37720 Tested-by: build bot (Jenkins) Reviewed-by: Arthur Heymans Reviewed-by: Angel Pons --- src/drivers/mrc_cache/mrc_cache.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/drivers/mrc_cache/mrc_cache.c b/src/drivers/mrc_cache/mrc_cache.c index ca0f447523..d4a4aab308 100644 --- a/src/drivers/mrc_cache/mrc_cache.c +++ b/src/drivers/mrc_cache/mrc_cache.c @@ -415,8 +415,8 @@ static void update_mrc_cache_by_type(int type) printk(BIOS_DEBUG, "MRC: cache data '%s' needs update.\n", cr->name); if (region_file_update_data(&cache_file, - cbmem_entry_start(to_be_updated), - cbmem_entry_size(to_be_updated)) < 0) + cbmem_entry_start(to_be_updated), + cbmem_entry_size(to_be_updated)) < 0) log_event_cache_update(cr->elog_slot, UPDATE_FAILURE); else log_event_cache_update(cr->elog_slot, UPDATE_SUCCESS); From b320bc5e0e6863126b57166923f3e0fac96bbb0c Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ky=C3=B6sti=20M=C3=A4lkki?= Date: Sat, 23 Nov 2019 20:22:09 +0200 Subject: [PATCH 0684/1242] AGESA: Disable boards from build MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit As per the 4.11 release requirement, C_ENVIRONMENT_BOOTBLOCK=y is a mandatory feature, which most AGESA and binaryPI boards lack. Disable such platforms from the build for the time being. The Kconfig symbol has been flipped, ROMCC_BOOTBLOCK=n is the same mandated feature as C_ENVIRONMENT_BOOTBLOCK=y. If a platform does not reach ROMCC_BOOTBLOCK=n within a reasonable timeframe both the mainboard and the respective unused platform support code will get removed. Change-Id: I7fceb0370f7f4f5f52080277c5d21615d3ab3454 Signed-off-by: Kyösti Mälkki Reviewed-on: https://review.coreboot.org/c/coreboot/+/37355 Tested-by: build bot (Jenkins) Reviewed-by: Arthur Heymans --- src/mainboard/amd/bettong/Kconfig | 2 +- src/mainboard/amd/db-ft3b-lc/Kconfig | 2 +- src/mainboard/amd/inagua/Kconfig | 5 ++++- src/mainboard/amd/inagua/Kconfig.name | 4 ++-- src/mainboard/amd/lamar/Kconfig | 2 +- src/mainboard/amd/olivehill/Kconfig | 5 ++++- src/mainboard/amd/olivehill/Kconfig.name | 4 ++-- src/mainboard/amd/olivehillplus/Kconfig | 2 +- src/mainboard/amd/parmer/Kconfig | 5 ++++- src/mainboard/amd/parmer/Kconfig.name | 4 ++-- src/mainboard/amd/persimmon/Kconfig | 5 ++++- src/mainboard/amd/persimmon/Kconfig.name | 4 ++-- src/mainboard/amd/south_station/Kconfig | 5 ++++- src/mainboard/amd/south_station/Kconfig.name | 4 ++-- src/mainboard/amd/thatcher/Kconfig | 5 ++++- src/mainboard/amd/thatcher/Kconfig.name | 4 ++-- src/mainboard/amd/union_station/Kconfig | 5 ++++- src/mainboard/amd/union_station/Kconfig.name | 4 ++-- src/mainboard/asus/am1i-a/Kconfig | 5 ++++- src/mainboard/asus/am1i-a/Kconfig.name | 4 ++-- src/mainboard/bap/Kconfig | 4 ++++ src/mainboard/bap/ode_e20XX/Kconfig | 5 ++++- src/mainboard/bap/ode_e20XX/Kconfig.name | 4 ++-- src/mainboard/bap/ode_e21XX/Kconfig | 2 +- src/mainboard/biostar/Kconfig | 3 +++ src/mainboard/biostar/a68n_5200/Kconfig | 5 ++++- src/mainboard/biostar/a68n_5200/Kconfig.name | 4 ++-- src/mainboard/biostar/am1ml/Kconfig | 5 ++++- src/mainboard/biostar/am1ml/Kconfig.name | 4 ++-- src/mainboard/elmex/Kconfig | 3 +++ src/mainboard/elmex/pcm205400/Kconfig | 5 ++++- src/mainboard/elmex/pcm205400/Kconfig.name | 4 ++-- src/mainboard/elmex/pcm205401/Kconfig | 3 +++ src/mainboard/elmex/pcm205401/Kconfig.name | 4 ++-- src/mainboard/gizmosphere/gizmo2/Kconfig | 5 ++++- src/mainboard/gizmosphere/gizmo2/Kconfig.name | 4 ++-- src/mainboard/hp/abm/Kconfig | 5 ++++- src/mainboard/hp/abm/Kconfig.name | 4 ++-- src/mainboard/jetway/Kconfig | 3 +++ src/mainboard/jetway/nf81-t56n-lf/Kconfig | 5 ++++- src/mainboard/jetway/nf81-t56n-lf/Kconfig.name | 4 ++-- src/mainboard/lippert/Kconfig | 3 +++ src/mainboard/lippert/frontrunner-af/Kconfig | 5 ++++- src/mainboard/lippert/frontrunner-af/Kconfig.name | 4 ++-- src/mainboard/lippert/toucan-af/Kconfig | 5 ++++- src/mainboard/lippert/toucan-af/Kconfig.name | 4 ++-- src/mainboard/msi/ms7721/Kconfig | 5 ++++- src/mainboard/msi/ms7721/Kconfig.name | 4 ++-- 48 files changed, 134 insertions(+), 61 deletions(-) diff --git a/src/mainboard/amd/bettong/Kconfig b/src/mainboard/amd/bettong/Kconfig index 08410d3a72..4617360ea1 100644 --- a/src/mainboard/amd/bettong/Kconfig +++ b/src/mainboard/amd/bettong/Kconfig @@ -21,7 +21,7 @@ if BOARD_AMD_BETTONG config BOARD_SPECIFIC_OPTIONS def_bool y #select BINARYPI_LEGACY_WRAPPER - select ROMCC_BOOTBLOCK + #select ROMCC_BOOTBLOCK select CPU_AMD_PI_00660F01 select NORTHBRIDGE_AMD_PI_00660F01 select SOUTHBRIDGE_AMD_PI_KERN diff --git a/src/mainboard/amd/db-ft3b-lc/Kconfig b/src/mainboard/amd/db-ft3b-lc/Kconfig index eb5fe8786f..f17d2d34e9 100644 --- a/src/mainboard/amd/db-ft3b-lc/Kconfig +++ b/src/mainboard/amd/db-ft3b-lc/Kconfig @@ -22,7 +22,7 @@ if BOARD_AMD_DB_FT3B_LC config BOARD_SPECIFIC_OPTIONS def_bool y #select BINARYPI_LEGACY_WRAPPER - select ROMCC_BOOTBLOCK + #select ROMCC_BOOTBLOCK select CPU_AMD_PI_00730F01 select NORTHBRIDGE_AMD_PI_00730F01 select SOUTHBRIDGE_AMD_PI_AVALON diff --git a/src/mainboard/amd/inagua/Kconfig b/src/mainboard/amd/inagua/Kconfig index 541868bd71..a5ba07e637 100644 --- a/src/mainboard/amd/inagua/Kconfig +++ b/src/mainboard/amd/inagua/Kconfig @@ -13,11 +13,14 @@ # GNU General Public License for more details. # +config BOARD_AMD_INAGUA + def_bool n + if BOARD_AMD_INAGUA config BOARD_SPECIFIC_OPTIONS def_bool y - select ROMCC_BOOTBLOCK + #select ROMCC_BOOTBLOCK select CPU_AMD_AGESA_FAMILY14 select NORTHBRIDGE_AMD_AGESA_FAMILY14 select SOUTHBRIDGE_AMD_CIMX_SB800 diff --git a/src/mainboard/amd/inagua/Kconfig.name b/src/mainboard/amd/inagua/Kconfig.name index 668b22a7d7..1784fe6fd8 100644 --- a/src/mainboard/amd/inagua/Kconfig.name +++ b/src/mainboard/amd/inagua/Kconfig.name @@ -1,2 +1,2 @@ -config BOARD_AMD_INAGUA - bool "Inagua" +#config BOARD_AMD_INAGUA +# bool"Inagua" diff --git a/src/mainboard/amd/lamar/Kconfig b/src/mainboard/amd/lamar/Kconfig index d509afcfa9..c8565341d7 100644 --- a/src/mainboard/amd/lamar/Kconfig +++ b/src/mainboard/amd/lamar/Kconfig @@ -21,7 +21,7 @@ if BOARD_AMD_LAMAR config BOARD_SPECIFIC_OPTIONS def_bool y #select BINARYPI_LEGACY_WRAPPER - select ROMCC_BOOTBLOCK + #select ROMCC_BOOTBLOCK select CPU_AMD_PI_00630F01 select NORTHBRIDGE_AMD_PI_00630F01 select SOUTHBRIDGE_AMD_PI_BOLTON diff --git a/src/mainboard/amd/olivehill/Kconfig b/src/mainboard/amd/olivehill/Kconfig index e1b5215348..78f768f132 100644 --- a/src/mainboard/amd/olivehill/Kconfig +++ b/src/mainboard/amd/olivehill/Kconfig @@ -13,11 +13,14 @@ # GNU General Public License for more details. # +config BOARD_AMD_OLIVEHILL + def_bool n + if BOARD_AMD_OLIVEHILL config BOARD_SPECIFIC_OPTIONS def_bool y - select ROMCC_BOOTBLOCK + #select ROMCC_BOOTBLOCK select CPU_AMD_AGESA_FAMILY16_KB select NORTHBRIDGE_AMD_AGESA_FAMILY16_KB select SOUTHBRIDGE_AMD_AGESA_YANGTZE diff --git a/src/mainboard/amd/olivehill/Kconfig.name b/src/mainboard/amd/olivehill/Kconfig.name index fd1a713aac..d065472731 100644 --- a/src/mainboard/amd/olivehill/Kconfig.name +++ b/src/mainboard/amd/olivehill/Kconfig.name @@ -1,2 +1,2 @@ -config BOARD_AMD_OLIVEHILL - bool "Olive Hill" +#config BOARD_AMD_OLIVEHILL +# bool"Olive Hill" diff --git a/src/mainboard/amd/olivehillplus/Kconfig b/src/mainboard/amd/olivehillplus/Kconfig index 229e3f97e0..907de3be03 100644 --- a/src/mainboard/amd/olivehillplus/Kconfig +++ b/src/mainboard/amd/olivehillplus/Kconfig @@ -21,7 +21,7 @@ if BOARD_AMD_OLIVEHILLPLUS config BOARD_SPECIFIC_OPTIONS def_bool y #select BINARYPI_LEGACY_WRAPPER - select ROMCC_BOOTBLOCK + #select ROMCC_BOOTBLOCK select CPU_AMD_PI_00730F01 select NORTHBRIDGE_AMD_PI_00730F01 select SOUTHBRIDGE_AMD_PI_AVALON diff --git a/src/mainboard/amd/parmer/Kconfig b/src/mainboard/amd/parmer/Kconfig index 3b6cb5ce89..ae024dd91f 100644 --- a/src/mainboard/amd/parmer/Kconfig +++ b/src/mainboard/amd/parmer/Kconfig @@ -13,11 +13,14 @@ # GNU General Public License for more details. # +config BOARD_AMD_PARMER + def_bool n + if BOARD_AMD_PARMER config BOARD_SPECIFIC_OPTIONS def_bool y - select ROMCC_BOOTBLOCK + #select ROMCC_BOOTBLOCK select CPU_AMD_AGESA_FAMILY15_TN select NORTHBRIDGE_AMD_AGESA_FAMILY15_TN select SOUTHBRIDGE_AMD_AGESA_HUDSON diff --git a/src/mainboard/amd/parmer/Kconfig.name b/src/mainboard/amd/parmer/Kconfig.name index 3aedc956ae..07714686dd 100644 --- a/src/mainboard/amd/parmer/Kconfig.name +++ b/src/mainboard/amd/parmer/Kconfig.name @@ -1,2 +1,2 @@ -config BOARD_AMD_PARMER - bool "Parmer" +#config BOARD_AMD_PARMER +# bool"Parmer" diff --git a/src/mainboard/amd/persimmon/Kconfig b/src/mainboard/amd/persimmon/Kconfig index 005741e8b4..f243f0f9c7 100644 --- a/src/mainboard/amd/persimmon/Kconfig +++ b/src/mainboard/amd/persimmon/Kconfig @@ -13,11 +13,14 @@ # GNU General Public License for more details. # +config BOARD_AMD_PERSIMMON + def_bool n + if BOARD_AMD_PERSIMMON config BOARD_SPECIFIC_OPTIONS def_bool y - select ROMCC_BOOTBLOCK + #select ROMCC_BOOTBLOCK select CPU_AMD_AGESA_FAMILY14 select NORTHBRIDGE_AMD_AGESA_FAMILY14 select SOUTHBRIDGE_AMD_CIMX_SB800 diff --git a/src/mainboard/amd/persimmon/Kconfig.name b/src/mainboard/amd/persimmon/Kconfig.name index ba24b13aa4..d50ebbe8cd 100644 --- a/src/mainboard/amd/persimmon/Kconfig.name +++ b/src/mainboard/amd/persimmon/Kconfig.name @@ -1,2 +1,2 @@ -config BOARD_AMD_PERSIMMON - bool "Persimmon" +#config BOARD_AMD_PERSIMMON +# bool"Persimmon" diff --git a/src/mainboard/amd/south_station/Kconfig b/src/mainboard/amd/south_station/Kconfig index f10ff7a940..42841cbb93 100644 --- a/src/mainboard/amd/south_station/Kconfig +++ b/src/mainboard/amd/south_station/Kconfig @@ -13,11 +13,14 @@ # GNU General Public License for more details. # +config BOARD_AMD_SOUTHSTATION + def_bool n + if BOARD_AMD_SOUTHSTATION config BOARD_SPECIFIC_OPTIONS def_bool y - select ROMCC_BOOTBLOCK + #select ROMCC_BOOTBLOCK select CPU_AMD_AGESA_FAMILY14 select NORTHBRIDGE_AMD_AGESA_FAMILY14 select SOUTHBRIDGE_AMD_CIMX_SB800 diff --git a/src/mainboard/amd/south_station/Kconfig.name b/src/mainboard/amd/south_station/Kconfig.name index 0cc745e3bc..f8f1404af2 100644 --- a/src/mainboard/amd/south_station/Kconfig.name +++ b/src/mainboard/amd/south_station/Kconfig.name @@ -1,2 +1,2 @@ -config BOARD_AMD_SOUTHSTATION - bool "Southstation" +#config BOARD_AMD_SOUTHSTATION +# bool"Southstation" diff --git a/src/mainboard/amd/thatcher/Kconfig b/src/mainboard/amd/thatcher/Kconfig index 2c0939c84e..e55659225f 100644 --- a/src/mainboard/amd/thatcher/Kconfig +++ b/src/mainboard/amd/thatcher/Kconfig @@ -13,11 +13,14 @@ # GNU General Public License for more details. # +config BOARD_AMD_THATCHER + def_bool n + if BOARD_AMD_THATCHER config BOARD_SPECIFIC_OPTIONS def_bool y - select ROMCC_BOOTBLOCK + #select ROMCC_BOOTBLOCK select CPU_AMD_AGESA_FAMILY15_TN select NORTHBRIDGE_AMD_AGESA_FAMILY15_TN select SOUTHBRIDGE_AMD_AGESA_HUDSON diff --git a/src/mainboard/amd/thatcher/Kconfig.name b/src/mainboard/amd/thatcher/Kconfig.name index aff5246cc7..b57bdb9a7f 100644 --- a/src/mainboard/amd/thatcher/Kconfig.name +++ b/src/mainboard/amd/thatcher/Kconfig.name @@ -1,2 +1,2 @@ -config BOARD_AMD_THATCHER - bool "Thatcher" +#config BOARD_AMD_THATCHER +# bool"Thatcher" diff --git a/src/mainboard/amd/union_station/Kconfig b/src/mainboard/amd/union_station/Kconfig index f03fb08f8b..1532d34062 100644 --- a/src/mainboard/amd/union_station/Kconfig +++ b/src/mainboard/amd/union_station/Kconfig @@ -13,11 +13,14 @@ # GNU General Public License for more details. # +config BOARD_AMD_UNIONSTATION + def_bool n + if BOARD_AMD_UNIONSTATION config BOARD_SPECIFIC_OPTIONS def_bool y - select ROMCC_BOOTBLOCK + #select ROMCC_BOOTBLOCK select CPU_AMD_AGESA_FAMILY14 select NORTHBRIDGE_AMD_AGESA_FAMILY14 select SOUTHBRIDGE_AMD_CIMX_SB800 diff --git a/src/mainboard/amd/union_station/Kconfig.name b/src/mainboard/amd/union_station/Kconfig.name index 9af3c8270b..b4dc53656d 100644 --- a/src/mainboard/amd/union_station/Kconfig.name +++ b/src/mainboard/amd/union_station/Kconfig.name @@ -1,2 +1,2 @@ -config BOARD_AMD_UNIONSTATION - bool "Unionstation" +#config BOARD_AMD_UNIONSTATION +# bool"Unionstation" diff --git a/src/mainboard/asus/am1i-a/Kconfig b/src/mainboard/asus/am1i-a/Kconfig index f194519393..8ccb1742af 100644 --- a/src/mainboard/asus/am1i-a/Kconfig +++ b/src/mainboard/asus/am1i-a/Kconfig @@ -1,9 +1,12 @@ +config BOARD_ASUS_AM1I_A + def_bool n + if BOARD_ASUS_AM1I_A config BOARD_SPECIFIC_OPTIONS def_bool y select BOARD_ROMSIZE_KB_8192 - select ROMCC_BOOTBLOCK + #select ROMCC_BOOTBLOCK select CPU_AMD_AGESA_FAMILY16_KB select FORCE_AM1_SOCKET_SUPPORT select GFXUMA diff --git a/src/mainboard/asus/am1i-a/Kconfig.name b/src/mainboard/asus/am1i-a/Kconfig.name index 840e821f65..57c62278ca 100644 --- a/src/mainboard/asus/am1i-a/Kconfig.name +++ b/src/mainboard/asus/am1i-a/Kconfig.name @@ -1,2 +1,2 @@ -config BOARD_ASUS_AM1I_A - bool "AM1I-A" +#config BOARD_ASUS_AM1I_A +# bool"AM1I-A" diff --git a/src/mainboard/bap/Kconfig b/src/mainboard/bap/Kconfig index 9af496dca6..a638509026 100644 --- a/src/mainboard/bap/Kconfig +++ b/src/mainboard/bap/Kconfig @@ -13,6 +13,7 @@ ## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ## GNU General Public License for more details. ## + if VENDOR_BAP choice @@ -20,6 +21,9 @@ choice source "src/mainboard/bap/*/Kconfig.name" +config BAP_BOARDS_DISABLED + bool "Boards from vendor are disabled" + endchoice source "src/mainboard/bap/*/Kconfig" diff --git a/src/mainboard/bap/ode_e20XX/Kconfig b/src/mainboard/bap/ode_e20XX/Kconfig index 97593d5d78..2a72debf58 100644 --- a/src/mainboard/bap/ode_e20XX/Kconfig +++ b/src/mainboard/bap/ode_e20XX/Kconfig @@ -14,11 +14,14 @@ # GNU General Public License for more details. # +config BOARD_ODE_E20XX + def_bool n + if BOARD_ODE_E20XX config BOARD_SPECIFIC_OPTIONS def_bool y - select ROMCC_BOOTBLOCK + #select ROMCC_BOOTBLOCK select CPU_AMD_AGESA_FAMILY16_KB select NORTHBRIDGE_AMD_AGESA_FAMILY16_KB select SOUTHBRIDGE_AMD_AGESA_YANGTZE diff --git a/src/mainboard/bap/ode_e20XX/Kconfig.name b/src/mainboard/bap/ode_e20XX/Kconfig.name index a482846808..54ddcac682 100644 --- a/src/mainboard/bap/ode_e20XX/Kconfig.name +++ b/src/mainboard/bap/ode_e20XX/Kconfig.name @@ -1,2 +1,2 @@ -config BOARD_ODE_E20XX - bool "ODE_e20xx" +#config BOARD_ODE_E20XX +# bool"ODE_e20xx" diff --git a/src/mainboard/bap/ode_e21XX/Kconfig b/src/mainboard/bap/ode_e21XX/Kconfig index bc5c131f79..ff71d5bdc3 100644 --- a/src/mainboard/bap/ode_e21XX/Kconfig +++ b/src/mainboard/bap/ode_e21XX/Kconfig @@ -21,7 +21,7 @@ if BOARD_ODE_E21XX config BOARD_SPECIFIC_OPTIONS def_bool y #select BINARYPI_LEGACY_WRAPPER - select ROMCC_BOOTBLOCK + #select ROMCC_BOOTBLOCK select CPU_AMD_PI_00730F01 select NORTHBRIDGE_AMD_PI_00730F01 select SOUTHBRIDGE_AMD_PI_AVALON diff --git a/src/mainboard/biostar/Kconfig b/src/mainboard/biostar/Kconfig index 43896a3f1f..6469d4e6b5 100644 --- a/src/mainboard/biostar/Kconfig +++ b/src/mainboard/biostar/Kconfig @@ -20,6 +20,9 @@ choice source "src/mainboard/biostar/*/Kconfig.name" +config BIOSTAR_BOARDS_DISABLED + bool "Boards from vendor are disabled" + endchoice source "src/mainboard/biostar/*/Kconfig" diff --git a/src/mainboard/biostar/a68n_5200/Kconfig b/src/mainboard/biostar/a68n_5200/Kconfig index a452569a9b..f608513d0e 100644 --- a/src/mainboard/biostar/a68n_5200/Kconfig +++ b/src/mainboard/biostar/a68n_5200/Kconfig @@ -15,11 +15,14 @@ # GNU General Public License for more details. # +config BOARD_BIOSTAR_A68N5200 + def_bool n + if BOARD_BIOSTAR_A68N5200 config BOARD_SPECIFIC_OPTIONS def_bool y - select ROMCC_BOOTBLOCK + #select ROMCC_BOOTBLOCK select CPU_AMD_AGESA_FAMILY16_KB select NORTHBRIDGE_AMD_AGESA_FAMILY16_KB select SOUTHBRIDGE_AMD_AGESA_YANGTZE diff --git a/src/mainboard/biostar/a68n_5200/Kconfig.name b/src/mainboard/biostar/a68n_5200/Kconfig.name index 52a7f1511a..6d765d2712 100644 --- a/src/mainboard/biostar/a68n_5200/Kconfig.name +++ b/src/mainboard/biostar/a68n_5200/Kconfig.name @@ -1,2 +1,2 @@ -config BOARD_BIOSTAR_A68N5200 - bool "A68N-5200" +#config BOARD_BIOSTAR_A68N5200 +# bool"A68N-5200" diff --git a/src/mainboard/biostar/am1ml/Kconfig b/src/mainboard/biostar/am1ml/Kconfig index 3c87965998..866fc66e5d 100644 --- a/src/mainboard/biostar/am1ml/Kconfig +++ b/src/mainboard/biostar/am1ml/Kconfig @@ -14,12 +14,15 @@ # GNU General Public License for more details. # +config BOARD_BIOSTAR_AM1ML + def_bool n + if BOARD_BIOSTAR_AM1ML config BOARD_SPECIFIC_OPTIONS def_bool y select BOARD_ROMSIZE_KB_4096 - select ROMCC_BOOTBLOCK + #select ROMCC_BOOTBLOCK select CPU_AMD_AGESA_FAMILY16_KB select FORCE_AM1_SOCKET_SUPPORT select GFXUMA diff --git a/src/mainboard/biostar/am1ml/Kconfig.name b/src/mainboard/biostar/am1ml/Kconfig.name index ccfa6fea85..0980c2e85d 100644 --- a/src/mainboard/biostar/am1ml/Kconfig.name +++ b/src/mainboard/biostar/am1ml/Kconfig.name @@ -1,2 +1,2 @@ -config BOARD_BIOSTAR_AM1ML - bool "AM1ML" +#config BOARD_BIOSTAR_AM1ML +# bool"AM1ML" diff --git a/src/mainboard/elmex/Kconfig b/src/mainboard/elmex/Kconfig index d1fc9adda7..54217ea217 100644 --- a/src/mainboard/elmex/Kconfig +++ b/src/mainboard/elmex/Kconfig @@ -5,6 +5,9 @@ choice source "src/mainboard/elmex/*/Kconfig.name" +config ELMEX_BOARDS_DISABLED + bool "Boards from vendor are disabled" + endchoice source "src/mainboard/elmex/*/Kconfig" diff --git a/src/mainboard/elmex/pcm205400/Kconfig b/src/mainboard/elmex/pcm205400/Kconfig index 14254ca02d..e94a6d89bb 100644 --- a/src/mainboard/elmex/pcm205400/Kconfig +++ b/src/mainboard/elmex/pcm205400/Kconfig @@ -13,6 +13,9 @@ # GNU General Public License for more details. # +config BOARD_ELMEX_PCM205400 + def_bool n + if BOARD_ELMEX_PCM205400 config MAINBOARD_PART_NUMBER @@ -29,7 +32,7 @@ if BOARD_ELMEX_PCM205400 || BOARD_ELMEX_PCM205401 config BOARD_SPECIFIC_OPTIONS def_bool y - select ROMCC_BOOTBLOCK + #select ROMCC_BOOTBLOCK select CPU_AMD_AGESA_FAMILY14 select NORTHBRIDGE_AMD_AGESA_FAMILY14 select SOUTHBRIDGE_AMD_CIMX_SB800 diff --git a/src/mainboard/elmex/pcm205400/Kconfig.name b/src/mainboard/elmex/pcm205400/Kconfig.name index 445b58868a..6488992de2 100644 --- a/src/mainboard/elmex/pcm205400/Kconfig.name +++ b/src/mainboard/elmex/pcm205400/Kconfig.name @@ -1,2 +1,2 @@ -config BOARD_ELMEX_PCM205400 - bool "pcm205400" +#config BOARD_ELMEX_PCM205400 +# bool"pcm205400" diff --git a/src/mainboard/elmex/pcm205401/Kconfig b/src/mainboard/elmex/pcm205401/Kconfig index a9bbe6e471..15c741abf2 100644 --- a/src/mainboard/elmex/pcm205401/Kconfig +++ b/src/mainboard/elmex/pcm205401/Kconfig @@ -13,6 +13,9 @@ # GNU General Public License for more details. # +config BOARD_ELMEX_PCM205401 + def_bool n + if BOARD_ELMEX_PCM205401 config MAINBOARD_PART_NUMBER diff --git a/src/mainboard/elmex/pcm205401/Kconfig.name b/src/mainboard/elmex/pcm205401/Kconfig.name index f70b215abc..050b94c4b4 100644 --- a/src/mainboard/elmex/pcm205401/Kconfig.name +++ b/src/mainboard/elmex/pcm205401/Kconfig.name @@ -1,2 +1,2 @@ -config BOARD_ELMEX_PCM205401 - bool "pcm205401" +#config BOARD_ELMEX_PCM205401 +# bool "pcm205401" diff --git a/src/mainboard/gizmosphere/gizmo2/Kconfig b/src/mainboard/gizmosphere/gizmo2/Kconfig index b066cdb8cf..685e27190a 100644 --- a/src/mainboard/gizmosphere/gizmo2/Kconfig +++ b/src/mainboard/gizmosphere/gizmo2/Kconfig @@ -14,11 +14,14 @@ # GNU General Public License for more details. # +config BOARD_GIZMOSPHERE_GIZMO2 + def_bool n + if BOARD_GIZMOSPHERE_GIZMO2 config BOARD_SPECIFIC_OPTIONS def_bool y - select ROMCC_BOOTBLOCK + #select ROMCC_BOOTBLOCK select CPU_AMD_AGESA_FAMILY16_KB select NORTHBRIDGE_AMD_AGESA_FAMILY16_KB select SOUTHBRIDGE_AMD_AGESA_YANGTZE diff --git a/src/mainboard/gizmosphere/gizmo2/Kconfig.name b/src/mainboard/gizmosphere/gizmo2/Kconfig.name index a3bae57b28..29688e2a34 100644 --- a/src/mainboard/gizmosphere/gizmo2/Kconfig.name +++ b/src/mainboard/gizmosphere/gizmo2/Kconfig.name @@ -1,2 +1,2 @@ -config BOARD_GIZMOSPHERE_GIZMO2 - bool "Gizmo2" +#config BOARD_GIZMOSPHERE_GIZMO2 +# bool"Gizmo2" diff --git a/src/mainboard/hp/abm/Kconfig b/src/mainboard/hp/abm/Kconfig index 9e35163180..907c02546c 100644 --- a/src/mainboard/hp/abm/Kconfig +++ b/src/mainboard/hp/abm/Kconfig @@ -14,11 +14,14 @@ # GNU General Public License for more details. # +config BOARD_HP_ABM + def_bool n + if BOARD_HP_ABM config BOARD_SPECIFIC_OPTIONS def_bool y - select ROMCC_BOOTBLOCK + #select ROMCC_BOOTBLOCK select CPU_AMD_AGESA_FAMILY16_KB select NORTHBRIDGE_AMD_AGESA_FAMILY16_KB select SOUTHBRIDGE_AMD_AGESA_YANGTZE diff --git a/src/mainboard/hp/abm/Kconfig.name b/src/mainboard/hp/abm/Kconfig.name index 4ace57323d..27eda0c7d9 100644 --- a/src/mainboard/hp/abm/Kconfig.name +++ b/src/mainboard/hp/abm/Kconfig.name @@ -1,2 +1,2 @@ -config BOARD_HP_ABM - bool "ABM" +#config BOARD_HP_ABM +# bool"ABM" diff --git a/src/mainboard/jetway/Kconfig b/src/mainboard/jetway/Kconfig index 63b3accd8d..530700d816 100644 --- a/src/mainboard/jetway/Kconfig +++ b/src/mainboard/jetway/Kconfig @@ -5,6 +5,9 @@ choice source "src/mainboard/jetway/*/Kconfig.name" +config JETWAY_BOARDS_DISABLED + bool "Boards from vendor are disabled" + endchoice source "src/mainboard/jetway/*/Kconfig" diff --git a/src/mainboard/jetway/nf81-t56n-lf/Kconfig b/src/mainboard/jetway/nf81-t56n-lf/Kconfig index 95d3b7ef11..dfa01b93a6 100644 --- a/src/mainboard/jetway/nf81-t56n-lf/Kconfig +++ b/src/mainboard/jetway/nf81-t56n-lf/Kconfig @@ -14,11 +14,14 @@ # GNU General Public License for more details. # +config BOARD_JETWAY_NF81_T56N_LF + def_bool n + if BOARD_JETWAY_NF81_T56N_LF config BOARD_SPECIFIC_OPTIONS def_bool y - select ROMCC_BOOTBLOCK + #select ROMCC_BOOTBLOCK select CPU_AMD_AGESA_FAMILY14 select NORTHBRIDGE_AMD_AGESA_FAMILY14 select SOUTHBRIDGE_AMD_CIMX_SB800 diff --git a/src/mainboard/jetway/nf81-t56n-lf/Kconfig.name b/src/mainboard/jetway/nf81-t56n-lf/Kconfig.name index 2e660f937c..0b676274ae 100644 --- a/src/mainboard/jetway/nf81-t56n-lf/Kconfig.name +++ b/src/mainboard/jetway/nf81-t56n-lf/Kconfig.name @@ -1,2 +1,2 @@ -config BOARD_JETWAY_NF81_T56N_LF - bool "NF81_T56N_LF" +#config BOARD_JETWAY_NF81_T56N_LF +# bool"NF81_T56N_LF" diff --git a/src/mainboard/lippert/Kconfig b/src/mainboard/lippert/Kconfig index 76cf305f82..e45fc3e6a2 100644 --- a/src/mainboard/lippert/Kconfig +++ b/src/mainboard/lippert/Kconfig @@ -5,6 +5,9 @@ comment "was acquired by ADLINK" choice prompt "Mainboard model" +config LIPPERT_BOARDS_DISABLED + bool "Boards from vendor are disabled" + source "src/mainboard/lippert/*/Kconfig.name" endchoice diff --git a/src/mainboard/lippert/frontrunner-af/Kconfig b/src/mainboard/lippert/frontrunner-af/Kconfig index 8b33810ada..4a007bf394 100644 --- a/src/mainboard/lippert/frontrunner-af/Kconfig +++ b/src/mainboard/lippert/frontrunner-af/Kconfig @@ -13,11 +13,14 @@ # GNU General Public License for more details. # +config BOARD_LIPPERT_FRONTRUNNER_AF + def_bool n + if BOARD_LIPPERT_FRONTRUNNER_AF config BOARD_SPECIFIC_OPTIONS def_bool y - select ROMCC_BOOTBLOCK + #select ROMCC_BOOTBLOCK select CPU_AMD_AGESA_FAMILY14 select NORTHBRIDGE_AMD_AGESA_FAMILY14 select SOUTHBRIDGE_AMD_CIMX_SB800 diff --git a/src/mainboard/lippert/frontrunner-af/Kconfig.name b/src/mainboard/lippert/frontrunner-af/Kconfig.name index 2a8cba52ab..1939264bc4 100644 --- a/src/mainboard/lippert/frontrunner-af/Kconfig.name +++ b/src/mainboard/lippert/frontrunner-af/Kconfig.name @@ -1,2 +1,2 @@ -config BOARD_LIPPERT_FRONTRUNNER_AF - bool "FrontRunner-AF aka ADLINK CoreModule2-GF" +#config BOARD_LIPPERT_FRONTRUNNER_AF +# bool"FrontRunner-AF aka ADLINK CoreModule2-GF" diff --git a/src/mainboard/lippert/toucan-af/Kconfig b/src/mainboard/lippert/toucan-af/Kconfig index 146af07821..b62da2e333 100644 --- a/src/mainboard/lippert/toucan-af/Kconfig +++ b/src/mainboard/lippert/toucan-af/Kconfig @@ -13,11 +13,14 @@ # GNU General Public License for more details. # +config BOARD_LIPPERT_TOUCAN_AF + def_bool n + if BOARD_LIPPERT_TOUCAN_AF config BOARD_SPECIFIC_OPTIONS def_bool y - select ROMCC_BOOTBLOCK + #select ROMCC_BOOTBLOCK select CPU_AMD_AGESA_FAMILY14 select NORTHBRIDGE_AMD_AGESA_FAMILY14 select SOUTHBRIDGE_AMD_CIMX_SB800 diff --git a/src/mainboard/lippert/toucan-af/Kconfig.name b/src/mainboard/lippert/toucan-af/Kconfig.name index 3481f92fba..6eceb51f0c 100644 --- a/src/mainboard/lippert/toucan-af/Kconfig.name +++ b/src/mainboard/lippert/toucan-af/Kconfig.name @@ -1,2 +1,2 @@ -config BOARD_LIPPERT_TOUCAN_AF - bool "Toucan-AF aka cExpress-GFR (+W83627DHG SIO)" +#config BOARD_LIPPERT_TOUCAN_AF +# bool"Toucan-AF aka cExpress-GFR (+W83627DHG SIO)" diff --git a/src/mainboard/msi/ms7721/Kconfig b/src/mainboard/msi/ms7721/Kconfig index 779d3b1baa..5f68e750d5 100644 --- a/src/mainboard/msi/ms7721/Kconfig +++ b/src/mainboard/msi/ms7721/Kconfig @@ -16,11 +16,14 @@ # GNU General Public License for more details. # +config BOARD_MSI_MS7721 + def_bool n + if BOARD_MSI_MS7721 config BOARD_SPECIFIC_OPTIONS def_bool y - select ROMCC_BOOTBLOCK + #select ROMCC_BOOTBLOCK select CPU_AMD_AGESA_FAMILY15_TN select NORTHBRIDGE_AMD_AGESA_FAMILY15_TN select SOUTHBRIDGE_AMD_AGESA_HUDSON diff --git a/src/mainboard/msi/ms7721/Kconfig.name b/src/mainboard/msi/ms7721/Kconfig.name index bce5b99d43..9ed5473acf 100644 --- a/src/mainboard/msi/ms7721/Kconfig.name +++ b/src/mainboard/msi/ms7721/Kconfig.name @@ -1,2 +1,2 @@ -config BOARD_MSI_MS7721 - bool "MS-7721 (FM2-A75MA-E35)" +#config BOARD_MSI_MS7721 +# bool"MS-7721 (FM2-A75MA-E35)" From b7eb1097e5d38cbf7fd6ee6001cde264f1e74984 Mon Sep 17 00:00:00 2001 From: Mike Wiitala Date: Thu, 12 Dec 2019 13:44:44 -0700 Subject: [PATCH 0685/1242] mb/g/drallion: Remove Wilco 1.0 CML variants from drallion code Remove the sarien_cml and arcada_cml subdirectories from the drallion/variants directory. BUG=b:140068267 TEST=./build_packages --board=drallion Confirm that drallion still builds successfully. BRANCH=none Change-Id: I9648965ca222d4d68bf73738716ad1c93739b03f Signed-off-by: Mike Wiitala Reviewed-on: https://review.coreboot.org/c/coreboot/+/37678 Tested-by: build bot (Jenkins) Reviewed-by: Duncan Laurie Reviewed-by: Mathew King --- src/mainboard/google/drallion/Kconfig | 8 - src/mainboard/google/drallion/Kconfig.name | 8 - .../drallion/variants/arcada_cml/Makefile.inc | 24 - .../variants/arcada_cml/devicetree.cb | 397 ---------------- .../drallion/variants/arcada_cml/gpio.c | 279 ------------ .../arcada_cml/include/variant/acpi/dptf.asl | 73 --- .../include/variant/acpi/mainboard.asl | 44 -- .../variants/arcada_cml/include/variant/ec.h | 34 -- .../arcada_cml/include/variant/gpio.h | 34 -- .../arcada_cml/include/variant/hda_verb.h | 209 --------- .../arcada_cml/include/variant/variant.h | 25 -- .../google/drallion/variants/arcada_cml/sku.c | 35 -- .../drallion/variants/sarien_cml/Makefile.inc | 24 - .../variants/sarien_cml/devicetree.cb | 424 ------------------ .../drallion/variants/sarien_cml/gpio.c | 267 ----------- .../sarien_cml/include/variant/acpi/dptf.asl | 73 --- .../include/variant/acpi/mainboard.asl | 44 -- .../variants/sarien_cml/include/variant/ec.h | 34 -- .../sarien_cml/include/variant/gpio.h | 34 -- .../sarien_cml/include/variant/hda_verb.h | 152 ------- .../sarien_cml/include/variant/variant.h | 25 -- .../google/drallion/variants/sarien_cml/sku.c | 35 -- 22 files changed, 2282 deletions(-) delete mode 100644 src/mainboard/google/drallion/variants/arcada_cml/Makefile.inc delete mode 100644 src/mainboard/google/drallion/variants/arcada_cml/devicetree.cb delete mode 100644 src/mainboard/google/drallion/variants/arcada_cml/gpio.c delete mode 100644 src/mainboard/google/drallion/variants/arcada_cml/include/variant/acpi/dptf.asl delete mode 100644 src/mainboard/google/drallion/variants/arcada_cml/include/variant/acpi/mainboard.asl delete mode 100644 src/mainboard/google/drallion/variants/arcada_cml/include/variant/ec.h delete mode 100644 src/mainboard/google/drallion/variants/arcada_cml/include/variant/gpio.h delete mode 100644 src/mainboard/google/drallion/variants/arcada_cml/include/variant/hda_verb.h delete mode 100644 src/mainboard/google/drallion/variants/arcada_cml/include/variant/variant.h delete mode 100644 src/mainboard/google/drallion/variants/arcada_cml/sku.c delete mode 100644 src/mainboard/google/drallion/variants/sarien_cml/Makefile.inc delete mode 100644 src/mainboard/google/drallion/variants/sarien_cml/devicetree.cb delete mode 100644 src/mainboard/google/drallion/variants/sarien_cml/gpio.c delete mode 100644 src/mainboard/google/drallion/variants/sarien_cml/include/variant/acpi/dptf.asl delete mode 100644 src/mainboard/google/drallion/variants/sarien_cml/include/variant/acpi/mainboard.asl delete mode 100644 src/mainboard/google/drallion/variants/sarien_cml/include/variant/ec.h delete mode 100644 src/mainboard/google/drallion/variants/sarien_cml/include/variant/gpio.h delete mode 100644 src/mainboard/google/drallion/variants/sarien_cml/include/variant/hda_verb.h delete mode 100644 src/mainboard/google/drallion/variants/sarien_cml/include/variant/variant.h delete mode 100644 src/mainboard/google/drallion/variants/sarien_cml/sku.c diff --git a/src/mainboard/google/drallion/Kconfig b/src/mainboard/google/drallion/Kconfig index 27818c091d..fd7b6b19d4 100644 --- a/src/mainboard/google/drallion/Kconfig +++ b/src/mainboard/google/drallion/Kconfig @@ -65,14 +65,10 @@ config MAINBOARD_DIR config MAINBOARD_FAMILY string - default "Google_Arcada_cml" if BOARD_GOOGLE_ARCADA_CML - default "Google_Sarien_cml" if BOARD_GOOGLE_SARIEN_CML default "Google_Drallion" if BOARD_GOOGLE_DRALLION config MAINBOARD_PART_NUMBER string - default "Arcada_cml" if BOARD_GOOGLE_ARCADA_CML - default "Sarien_cml" if BOARD_GOOGLE_SARIEN_CML default "Drallion" if BOARD_GOOGLE_DRALLION config MAX_CPUS @@ -81,14 +77,10 @@ config MAX_CPUS config UART_FOR_CONSOLE int - default 2 if BOARD_GOOGLE_ARCADA_CML - default 2 if BOARD_GOOGLE_SARIEN_CML default 0 if BOARD_GOOGLE_DRALLION config VARIANT_DIR string - default "arcada_cml" if BOARD_GOOGLE_ARCADA_CML - default "sarien_cml" if BOARD_GOOGLE_SARIEN_CML default "drallion" if BOARD_GOOGLE_DRALLION config DEVICETREE diff --git a/src/mainboard/google/drallion/Kconfig.name b/src/mainboard/google/drallion/Kconfig.name index e67b9156b8..bd5d9032d2 100644 --- a/src/mainboard/google/drallion/Kconfig.name +++ b/src/mainboard/google/drallion/Kconfig.name @@ -1,13 +1,5 @@ comment "Drallion" -config BOARD_GOOGLE_ARCADA_CML - bool "-> Arcada_cml" - select BOARD_GOOGLE_BASEBOARD_DRALLION - -config BOARD_GOOGLE_SARIEN_CML - bool "-> Sarien_cml" - select BOARD_GOOGLE_BASEBOARD_DRALLION - config BOARD_GOOGLE_DRALLION bool "-> Drallion" select BOARD_GOOGLE_BASEBOARD_DRALLION diff --git a/src/mainboard/google/drallion/variants/arcada_cml/Makefile.inc b/src/mainboard/google/drallion/variants/arcada_cml/Makefile.inc deleted file mode 100644 index b979be187e..0000000000 --- a/src/mainboard/google/drallion/variants/arcada_cml/Makefile.inc +++ /dev/null @@ -1,24 +0,0 @@ -## -## This file is part of the coreboot project. -## -## Copyright 2018 Google LLC -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; version 2 of the License. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## - -## GPP_F12-F16 indicates mem_id to match specific spd file -SPD_SOURCES = empty_ddr4 # 0b00000 - -bootblock-y += gpio.c -ramstage-y += gpio.c -romstage-y += gpio.c -verstage-y += gpio.c - -ramstage-y += sku.c diff --git a/src/mainboard/google/drallion/variants/arcada_cml/devicetree.cb b/src/mainboard/google/drallion/variants/arcada_cml/devicetree.cb deleted file mode 100644 index 11abc87daa..0000000000 --- a/src/mainboard/google/drallion/variants/arcada_cml/devicetree.cb +++ /dev/null @@ -1,397 +0,0 @@ -chip soc/intel/cannonlake - - # GPE configuration - # Note that GPE events called out in ASL code rely on this - # route. i.e. If this route changes then the affected GPE - # offset bits also need to be changed. - register "gpe0_dw0" = "PMC_GPP_A" - register "gpe0_dw1" = "PMC_GPP_C" - register "gpe0_dw2" = "PMC_GPP_D" - - # EC host command ranges - register "gen1_dec" = "0x00040931" # 0x930-0x937 - register "gen2_dec" = "0x00040941" # 0x940-0x947 - register "gen3_dec" = "0x000c0951" # 0x950-0x95f - - # FSP configuration - register "SaGv" = "SaGv_Enabled" - register "HeciEnabled" = "0" - register "SataSalpSupport" = "1" - register "SataMode" = "Sata_AHCI" - register "SataPortsEnable[2]" = "1" - register "SataPortsDevSlp[2]" = "1" - register "InternalGfx" = "1" - register "SkipExtGfxScan" = "1" - register "PchPmSlpS3MinAssert" = "3" # 50ms - register "PchPmSlpS4MinAssert" = "4" # 4s - register "PchPmSlpSusMinAssert" = "4" # 4s - register "PchPmSlpAMinAssert" = "4" # 2s - register "PchUnlockGpioPads" = "1" - - register "speed_shift_enable" = "1" - register "psys_pmax" = "140" - register "s0ix_enable" = "1" - register "dptf_enable" = "1" - register "satapwroptimize" = "1" - register "tdp_pl1_override" = "25" - register "tdp_pl2_override" = "51" - register "Device4Enable" = "1" - register "AcousticNoiseMitigation" = "1" - register "SlowSlewRateForIa" = "2" - register "SlowSlewRateForGt" = "2" - register "SlowSlewRateForSa" = "0" - register "SlowSlewRateForFivr" = "2" - # Enable eDP device - register "DdiPortEdp" = "1" - # Enable HPD for DDI ports B/C - register "DdiPortBHpd" = "1" - register "DdiPortCHpd" = "1" - # Enable DDC for DDI port B - register "DdiPortBDdc" = "1" - - # Disable iDisplay codec enumeration - register "PchHdaIDispCodecDisconnect" = "1" - register "PchHdaAudioLinkHda" = "1" - - # VR Settings Configuration for 4 Domains - #+----------------+-------+-------+-------+-------+ - #| Domain/Setting | SA | IA | GTUS | GTS | - #+----------------+-------+-------+-------+-------+ - #| Psi1Threshold | 20A | 20A | 20A | 20A | - #| Psi2Threshold | 5A | 5A | 5A | 5A | - #| Psi3Threshold | 1A | 1A | 1A | 1A | - #| Psi3Enable | 1 | 1 | 1 | 1 | - #| Psi4Enable | 1 | 1 | 1 | 1 | - #| ImonSlope | 0 | 0 | 0 | 0 | - #| ImonOffset | 0 | 0 | 0 | 0 | - #| IccMax | 6A | 70A | 31A | 31A | - #| VrVoltageLimit | 1.52V | 1.52V | 1.52V | 1.52V | - #| AcLoadline | 10.3 | 1.8 | 3.1 | 3.1 | - #| DcLoadline | 10.3 | 1.8 | 3.1 | 3.1 | - #+----------------+-------+-------+-------+-------+ - register "domain_vr_config[VR_SYSTEM_AGENT]" = "{ - .vr_config_enable = 1, - .psi1threshold = VR_CFG_AMP(20), - .psi2threshold = VR_CFG_AMP(5), - .psi3threshold = VR_CFG_AMP(1), - .psi3enable = 1, - .psi4enable = 1, - .imon_slope = 0x0, - .imon_offset = 0x0, - .icc_max = VR_CFG_AMP(6), - .voltage_limit = 1520, - .ac_loadline = 1030, - .dc_loadline = 1030, - }" - - register "domain_vr_config[VR_IA_CORE]" = "{ - .vr_config_enable = 1, - .psi1threshold = VR_CFG_AMP(20), - .psi2threshold = VR_CFG_AMP(5), - .psi3threshold = VR_CFG_AMP(1), - .psi3enable = 1, - .psi4enable = 1, - .imon_slope = 0x0, - .imon_offset = 0x0, - .icc_max = VR_CFG_AMP(70), - .voltage_limit = 1520, - .ac_loadline = 180, - .dc_loadline = 180, - }" - - register "domain_vr_config[VR_GT_UNSLICED]" = "{ - .vr_config_enable = 1, - .psi1threshold = VR_CFG_AMP(20), - .psi2threshold = VR_CFG_AMP(5), - .psi3threshold = VR_CFG_AMP(1), - .psi3enable = 1, - .psi4enable = 1, - .imon_slope = 0x0, - .imon_offset = 0x0, - .icc_max = VR_CFG_AMP(31), - .voltage_limit = 1520, - .ac_loadline = 310, - .dc_loadline = 310, - }" - - register "domain_vr_config[VR_GT_SLICED]" = "{ - .vr_config_enable = 1, - .psi1threshold = VR_CFG_AMP(20), - .psi2threshold = VR_CFG_AMP(5), - .psi3threshold = VR_CFG_AMP(1), - .psi3enable = 1, - .psi4enable = 1, - .imon_slope = 0x0, - .imon_offset = 0x0, - .icc_max = VR_CFG_AMP(31), - .voltage_limit = 1520, - .ac_loadline = 310, - .dc_loadline = 310, - }" - - # Intel Common SoC Config - register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC_SKIP)" # Left Type-C Port - register "usb2_ports[1]" = "USB2_PORT_LONG(OC0)" # Left Type-A Port - register "usb2_ports[2]" = "USB2_PORT_LONG(OC1)" # Right Type-A Port - register "usb2_ports[3]" = "USB2_PORT_EMPTY" - register "usb2_ports[4]" = "USB2_PORT_EMPTY" - register "usb2_ports[5]" = "USB2_PORT_LONG(OC_SKIP)" # Camera - register "usb2_ports[6]" = "{ - .enable = 1, \ - .ocpin = OC_SKIP, \ - .tx_bias = USB2_BIAS_0MV, \ - .tx_emp_enable = USB2_DE_EMP_ON_PRE_EMP_ON, \ - .pre_emp_bias = USB2_BIAS_28P15MV, \ - .pre_emp_bit = USB2_HALF_BIT_PRE_EMP, \ - }" # WWAN - register "usb2_ports[7]" = "USB2_PORT_MID(OC_SKIP)" # USH - register "usb2_ports[8]" = "USB2_PORT_MID(OC_SKIP)" # Fingerprint - register "usb2_ports[9]" = "USB2_PORT_MID(OC_SKIP)" # Bluetooth - - register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Left Type-C Port - register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC0)" # Left Type-A Port - register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC1)" # Right Type-A Port - register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC_SKIP)" # WWAN - register "usb3_ports[4]" = "USB3_PORT_EMPTY" - register "usb3_ports[5]" = "USB3_PORT_EMPTY" - - # Intel Common SoC Config - #+-------------------+---------------------------+ - #| Field | Value | - #+-------------------+---------------------------+ - #| chipset_lockdown | CHIPSET_LOCKDOWN_COREBOOT | - #| I2C0 | Touchscreen | - #| I2C1 | Touchpad | - #| I2C4 | H1 TPM | - #+-------------------+---------------------------+ - - register "tcc_offset" = "1" - - # PCH Thermal Trip Temperature in deg C - register "common_soc_config.pch_thermal_trip" = "77" - - register "common_soc_config" = "{ - .chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT, - .i2c[0] = { - .speed = I2C_SPEED_FAST, - .rise_time_ns = 52, - .fall_time_ns = 110, - }, - .i2c[1] = { - .speed = I2C_SPEED_FAST, - .rise_time_ns = 52, - .fall_time_ns = 110, - .data_hold_time_ns = 330, - }, - .i2c[4] = { - .early_init = 1, - .speed = I2C_SPEED_FAST, - .rise_time_ns = 36, - .fall_time_ns = 99, - }, - }" - - # PCIe port 10 for M.2 2230 WLAN - register "PcieRpEnable[9]" = "1" - register "PcieClkSrcUsage[2]" = "9" - register "PcieClkSrcClkReq[2]" = "2" - - # PCIe port 11 for card reader - register "PcieRpEnable[10]" = "1" - register "PcieRpLtrEnable[10]" = "1" - register "PcieClkSrcUsage[1]" = "10" - register "PcieClkSrcClkReq[1]" = "1" - - # PCIe port 13 for M.2 2280 SSD - register "PcieRpEnable[12]" = "1" - register "PcieRpLtrEnable[12]" = "1" - register "PcieClkSrcUsage[4]" = "12" - register "PcieClkSrcClkReq[4]" = "4" - - # GPIO PM programming - register "gpio_override_pm" = "1" - - # GPIO community PM configuration - # Disable dynamic clock gating; with bits 0-5 set in these registers, - # some short interrupt pulses were missed (esp. cr50 irq) - register "gpio_pm[COMM_0]" = "0" - register "gpio_pm[COMM_1]" = "0" - register "gpio_pm[COMM_2]" = "0" - register "gpio_pm[COMM_3]" = "0" - register "gpio_pm[COMM_4]" = "0" - - device cpu_cluster 0 on - device lapic 0 on end - end - device domain 0 on - device pci 00.0 on end # Host Bridge - device pci 02.0 on end # Integrated Graphics Device - device pci 04.0 on end # SA Thermal device - device pci 12.0 on end # Thermal Subsystem - device pci 12.5 off end # UFS SCS - device pci 12.6 off end # GSPI #2 - device pci 13.0 on # Integrated Sensor Hub - chip drivers/intel/ish - register "firmware_name" = ""arcada_ish.bin"" - device generic 0 on end - end - end - device pci 14.0 on - chip drivers/usb/acpi - register "desc" = ""Root Hub"" - register "type" = "UPC_TYPE_HUB" - device usb 0.0 on - chip drivers/usb/acpi - register "desc" = ""Left Type-C Port"" - register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" - register "group" = "ACPI_PLD_GROUP(1, 1)" - device usb 2.0 on end - end - chip drivers/usb/acpi - register "desc" = ""Left Type-A Port"" - register "type" = "UPC_TYPE_A" - register "group" = "ACPI_PLD_GROUP(1, 2)" - device usb 2.1 on end - end - chip drivers/usb/acpi - register "desc" = ""Right Type-A Port"" - register "type" = "UPC_TYPE_A" - register "group" = "ACPI_PLD_GROUP(2, 1)" - device usb 2.2 on end - end - chip drivers/usb/acpi - register "desc" = ""Camera"" - register "type" = "UPC_TYPE_INTERNAL" - device usb 2.5 on end - end - chip drivers/usb/acpi - register "desc" = ""WWAN"" - register "type" = "UPC_TYPE_INTERNAL" - device usb 2.6 on end - end - chip drivers/usb/acpi - register "desc" = ""USH"" - register "type" = "UPC_TYPE_INTERNAL" - device usb 2.7 on end - end - chip drivers/usb/acpi - register "desc" = ""Fingerprint"" - register "type" = "UPC_TYPE_INTERNAL" - device usb 2.8 on end - end - chip drivers/usb/acpi - register "desc" = ""Bluetooth"" - register "type" = "UPC_TYPE_INTERNAL" - register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_H15)" - device usb 2.9 on end - end - chip drivers/usb/acpi - register "desc" = ""Left Type-C Port"" - register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" - register "group" = "ACPI_PLD_GROUP(1, 1)" - device usb 3.0 on end - end - chip drivers/usb/acpi - register "desc" = ""Left Type-A Port"" - register "type" = "UPC_TYPE_USB3_A" - register "group" = "ACPI_PLD_GROUP(1, 2)" - device usb 3.1 on end - end - chip drivers/usb/acpi - register "desc" = ""Right Type-A Port"" - register "type" = "UPC_TYPE_USB3_A" - register "group" = "ACPI_PLD_GROUP(2, 1)" - device usb 3.2 on end - end - chip drivers/usb/acpi - register "desc" = ""WWAN"" - register "type" = "UPC_TYPE_INTERNAL" - device usb 3.3 on end - end - end - end - end # USB xHCI - device pci 14.1 off end # USB xDCI (OTG) - chip drivers/intel/wifi - register "wake" = "PME_B0_EN_BIT" - device pci 14.3 on end # CNVi wifi - end - device pci 14.5 off end # SDCard - device pci 15.0 on - chip drivers/i2c/hid - register "generic.hid" = ""WCOM48E2"" - register "generic.desc" = ""Wacom Touchscreen"" - register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_C23_IRQ)" - register "generic.probed" = "1" - register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_E7)" - register "generic.reset_delay_ms" = "120" - register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_B21)" - register "generic.enable_delay_ms" = "55" - register "generic.has_power_resource" = "1" - register "generic.disable_gpio_export_in_crs" = "1" - register "hid_desc_reg_offset" = "0x1" - device i2c 0A on end - end - end # I2C #0 - device pci 15.1 on - chip drivers/i2c/generic - register "hid" = ""ELAN0000"" - register "desc" = ""ELAN Touchpad"" - register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_B3_IRQ)" - register "probed" = "1" - device i2c 2c on end - end - end # I2C #1 - device pci 15.2 off end # I2C #2 - device pci 15.3 off end # I2C #3 - device pci 16.0 on end # Management Engine Interface 1 - device pci 16.1 off end # Management Engine Interface 2 - device pci 16.2 off end # Management Engine IDE-R - device pci 16.3 off end # Management Engine KT Redirection - device pci 16.4 off end # Management Engine Interface 3 - device pci 16.5 off end # Management Engine Interface 4 - device pci 17.0 on end # SATA - device pci 19.0 on - chip drivers/i2c/tpm - register "hid" = ""GOOG0005"" - register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_D18_IRQ)" - device i2c 50 on end - end - end # I2C #4 - device pci 19.1 off end # I2C #5 - device pci 19.2 on end # UART #2 - device pci 1a.0 off end # eMMC - device pci 1c.0 off end # PCI Express Port 1 (USB) - device pci 1c.1 off end # PCI Express Port 2 (USB) - device pci 1c.2 off end # PCI Express Port 3 (USB) - device pci 1c.3 off end # PCI Express Port 4 (USB) - device pci 1c.4 off end # PCI Express Port 5 (USB) - device pci 1c.5 off end # PCI Express Port 6 - device pci 1c.6 off end # PCI Express Port 7 - device pci 1c.7 off end # PCI Express Port 8 - device pci 1d.0 on - smbios_slot_desc "SlotTypeM2Socket1_SD" "SlotLengthOther" "2230" "SlotDataBusWidth1X" - end # PCI Express Port 9 - device pci 1d.1 on end # PCI Express Port 10 - device pci 1d.2 on end # PCI Express Port 11 - device pci 1d.3 off end # PCI Express Port 12 - device pci 1d.4 on - smbios_slot_desc "SlotTypeM2Socket3" "SlotLengthOther" "2280" "SlotDataBusWidth4X" - end # PCI Express Port 13 (x4) - device pci 1e.0 off end # UART #0 - device pci 1e.1 off end # UART #1 - device pci 1e.2 off end # GSPI #0 - device pci 1e.3 off end # GSPI #1 - device pci 1f.0 on - chip ec/google/wilco - device pnp 0c09.0 on end - end - end # LPC/eSPI - device pci 1f.1 on end # P2SB - device pci 1f.2 on end # Power Management Controller - device pci 1f.3 on end # Intel HDA - device pci 1f.4 on end # SMBus - device pci 1f.5 on end # PCH SPI - device pci 1f.6 off end # GbE - end -end diff --git a/src/mainboard/google/drallion/variants/arcada_cml/gpio.c b/src/mainboard/google/drallion/variants/arcada_cml/gpio.c deleted file mode 100644 index ff0240c991..0000000000 --- a/src/mainboard/google/drallion/variants/arcada_cml/gpio.c +++ /dev/null @@ -1,279 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright 2018 Google LLC - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the - * GNU General Public License for more details. - */ - -#include -#include - -/* Pad configuration in ramstage */ -static const struct pad_config gpio_table[] = { -/* RCIN# */ PAD_NC(GPP_A0, NONE), -/* ESPI_IO0 */ -/* ESPI_IO1 */ -/* ESPI_IO2 */ -/* ESPI_IO3 */ -/* ESPI_CS# */ -/* SERIRQ */ -/* PIRQA# */ PAD_NC(GPP_A7, NONE), -/* CLKRUN# */ PAD_NC(GPP_A8, NONE), -/* ESPI_CLK */ -/* CLKOUT_LPC1 */ PAD_NC(GPP_A10, NONE), -/* PME# */ PAD_NC(GPP_A11, NONE), - /* ISH_LID_CL#_TAB */ -/* ISH_GP6 */ PAD_CFG_NF(GPP_A12, NONE, DEEP, NF2), -/* SUSWARN# */ PAD_NC(GPP_A13, NONE), -/* ESPI_RESET# */ -/* SUSACK# */ PAD_NC(GPP_A15, NONE), -/* SD_1P8_SEL */ PAD_NC(GPP_A16, NONE), -/* SD_PWR_EN# */ PAD_NC(GPP_A17, NONE), - /* ISH_ACC1_INT# */ -/* ISH_GP0 */ PAD_CFG_NF(GPP_A18, NONE, DEEP, NF1), - /* ISH_ACC2_INT# */ -/* ISH_GP1 */ PAD_CFG_NF(GPP_A19, NONE, DEEP, NF1), -/* ISH_GP2 */ PAD_NC(GPP_A20, NONE), -/* ISH_GP3 */ PAD_NC(GPP_A21, NONE), - /* ISH_NB_MODE */ -/* ISH_GP4 */ PAD_CFG_NF(GPP_A22, NONE, DEEP, NF1), - /* ISH_LID_CL#_NB */ -/* ISH_GP5 */ PAD_CFG_NF(GPP_A23, NONE, DEEP, NF1), - -/* CORE_VID0 */ -/* CORE_VID1 */ -/* VRALERT# */ PAD_NC(GPP_B2, NONE), -/* CPU_GP2 */ PAD_CFG_GPI_APIC(GPP_B3, NONE, PLTRST, - EDGE_SINGLE, INVERT), /* TOUCHPAD_INTR# */ -/* CPU_GP3 */ PAD_CFG_GPI(GPP_B4, NONE, DEEP), /* TOUCH_SCREEN_DET# */ - /* LAN_CLKREQ_CPU_N */ -/* SRCCLKREQ0# */ PAD_CFG_NF(GPP_B5, NONE, DEEP, NF1), - /* CARD_CLKREQ_CPU_N */ -/* SRCCLKREQ1# */ PAD_CFG_NF(GPP_B6, NONE, DEEP, NF1), - /* WLAN_CLKREQ_CPU_N */ -/* SRCCLKREQ2# */ PAD_CFG_NF(GPP_B7, NONE, DEEP, NF1), - /* WWAN_CLKREQ_CPU_N */ -/* SRCCLKREQ3# */ PAD_CFG_NF(GPP_B8, NONE, DEEP, NF1), - /* SSD_CKLREQ_CPU_N */ -/* SRCCLKREQ4# */ PAD_CFG_NF(GPP_B9, NONE, DEEP, NF1), -/* SRCCLKREQ5# */ PAD_NC(GPP_B10, NONE), /* TBT_CLKREQ_CPU_N (nostuff) */ -/* EXT_PWR_GATE# */ PAD_CFG_GPO(GPP_B11, 0, DEEP), /* 3.3V_CAM_EN# */ -/* SLP_S0# */ PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1), -/* PLTRST# */ PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1), -/* SPKR */ PAD_CFG_NF(GPP_B14, NONE, DEEP, NF1), -/* GSPI0_CS# */ PAD_NC(GPP_B15, NONE), /* PRIM_CORE_OPT_DIS (nostuff) */ -/* GSPI0_CLK */ PAD_CFG_GPI(GPP_B16, NONE, DEEP), /* ONE_DIMM# */ -/* GSPI0_MISO */ PAD_NC(GPP_B17, NONE), /* RTC_DET# */ -/* GSPI0_MOSI */ PAD_NC(GPP_B18, NONE), -/* GSPI1_CS# */ PAD_NC(GPP_B19, NONE), /* HDD_FALL_INT (nostuff) */ -/* GSPI1_CLK */ PAD_NC(GPP_B20, NONE), /* TPM_PIRQ# (nostuff) */ -/* GSPI1_MISO */ PAD_CFG_GPO(GPP_B21, 1, DEEP), /* PCH_3.3V_TS_EN */ -/* GSPI1_MOSI */ PAD_NC(GPP_B22, NONE), -/* SML1ALERT# */ PAD_NC(GPP_B23, DN_20K), - -/* SMBCLK */ PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1), /* MEM_SMBCLK */ -/* SMBDATA */ PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1), /* MEM_SMBDATA */ -/* SMBALERT# */ PAD_NC(GPP_C2, DN_20K), -/* SML0CLK */ PAD_CFG_NF(GPP_C3, NONE, DEEP, NF1), /* SML0_SMBCLK */ -/* SML0DATA */ PAD_CFG_NF(GPP_C4, NONE, DEEP, NF1), /* SML0_SMBDATA */ -/* SML0ALERT# */ PAD_NC(GPP_C5, DN_20K), -/* SM1CLK */ PAD_CFG_NF(GPP_C6, NONE, DEEP, NF1), /* SML1_SMBCLK */ -/* SM1DATA */ PAD_CFG_NF(GPP_C7, NONE, DEEP, NF1), /* SML1_SMBDATA */ -/* UART0_RXD */ PAD_NC(GPP_C8, NONE), /* PCH_TBT_PERST# (nostuff) */ -/* UART0_TXD */ PAD_NC(GPP_C9, NONE), -/* UART0_RTS# */ PAD_CFG_GPI(GPP_C10, NONE, DEEP), /* TYPEC_CON_SEL1 */ -/* UART0_CTS# */ PAD_CFG_GPI(GPP_C11, NONE, DEEP), /* TYPEC_CON_SEL2 */ -/* UART1_RXD */ PAD_CFG_GPI_SCI_LOW(GPP_C12, NONE, DEEP, - EDGE_SINGLE), /* SIO_EXT_WAKE# */ -/* UART1_TXD */ PAD_NC(GPP_C13, NONE), -/* UART1_RTS# */ PAD_CFG_GPI(GPP_C14, NONE, DEEP), /* LCD_CBL_DET# */ -/* UART1_CTS# */ PAD_NC(GPP_C15, NONE), -/* I2C0_SDA */ PAD_CFG_NF(GPP_C16, NONE, DEEP, NF1), /* TS_I2C_SDA */ -/* I2C0_SCL */ PAD_CFG_NF(GPP_C17, NONE, DEEP, NF1), /* TS_I2C_SCL */ -/* I2C1_SDA */ PAD_CFG_NF(GPP_C18, NONE, DEEP, NF1), /* I2C1_SDA_TP */ -/* I2C1_SCL */ PAD_CFG_NF(GPP_C19, NONE, DEEP, NF1), /* I2C1_SCK_TP */ -/* UART2_RXD */ PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1), /* SERVOTX_UART */ -/* UART2_TXD */ PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1), /* SERVORX_UART */ -/* UART2_RTS# */ PAD_NC(GPP_C22, NONE), -/* UART2_CTS# */ PAD_CFG_GPI_APIC(GPP_C23, NONE, PLTRST, - LEVEL, NONE), /* TS_INT# */ - -/* SPI1_CS# */ PAD_CFG_GPI_APIC(GPP_D0, NONE, PLTRST, - EDGE_SINGLE, INVERT), /* MEDIACARD_IRQ# */ -/* SPI1_CLK */ PAD_NC(GPP_D1, NONE), -/* SPI1_MISO */ PAD_CFG_GPI(GPP_D2, NONE, DEEP), /* ISH_LAN# */ -/* SPI1_MOSI */ PAD_NC(GPP_D3, NONE), -/* FASHTRIG */ PAD_NC(GPP_D4, NONE), /* TBT_FORCE_PWR (nostuff) */ - /* ISH_I2C0_ACC_SDA */ -/* ISH_I2C0_SDA */ PAD_CFG_NF(GPP_D5, NONE, DEEP, NF1), - /* ISH_I2C0_ACC_SCL */ -/* ISH_I2C0_SCL */ PAD_CFG_NF(GPP_D6, NONE, DEEP, NF1), -/* ISH_I2C1_SDA */ PAD_NC(GPP_D7, NONE), -/* ISH_I2C1_SCL */ PAD_NC(GPP_D8, NONE), -/* ISH_SPI_CS# */ PAD_CFG_GPI(GPP_D9, NONE, DEEP), /* IR_CAM_DET# */ -/* ISH_SPI_CLK */ PAD_NC(GPP_D10, NONE), -/* ISH_SPI_MISO */ PAD_CFG_GPI(GPP_D11, NONE, DEEP), /* TBT_DET# */ -/* ISH_SPI_MOSI */ PAD_NC(GPP_D12, NONE), - /* ISH_CPU_UART0_RX */ -/* ISH_UART0_RXD */ PAD_CFG_NF(GPP_D13, UP_20K, DEEP, NF1), - /* ISH_CPU_UART0_TX */ -/* ISH_UART0_TXD */ PAD_CFG_NF(GPP_D14, NONE, DEEP, NF1), -/* ISH_UART0_RTS# */ PAD_CFG_GPO(GPP_D15, 1, DEEP), /* WWAN_FULL_PWR_EN */ -/* ISH_UART0_CTS# */ PAD_NC(GPP_D16, NONE), -/* DMIC_CLK1 */ PAD_CFG_GPI(GPP_D17, NONE, DEEP), /* KB_DET# */ -/* DMIC_DATA1 */ PAD_CFG_GPI_APIC(GPP_D18, NONE, PLTRST, - EDGE_SINGLE, INVERT), /* H1_PCH_INT_ODL */ -/* DMIC_CLK0 */ PAD_NC(GPP_D19, NONE), -/* DMIC_DATA0 */ PAD_NC(GPP_D20, NONE), -/* SPI1_IO2 */ PAD_CFG_GPO(GPP_D21, 1, DEEP), /* WWAN_BB_RST# */ -/* SPI1_IO3 */ PAD_CFG_GPO(GPP_D22, 0, DEEP), /* WWAN_GPIO_PERST# */ -/* I2S_MCLK */ PAD_CFG_GPI_SCI_LOW(GPP_D23, NONE, DEEP, - EDGE_SINGLE), /* WWAN_GPIO_WAKE# */ - -/* SATAXPCIE0 */ PAD_NC(GPP_E0, NONE), - /* M3042_PCIE#_SATA */ -/* SATAXPCIE1 */ PAD_CFG_NF(GPP_E1, NONE, DEEP, NF1), - /* M2880_PCIE_SATA# */ -/* SATAXPCIE2 */ PAD_CFG_NF(GPP_E2, NONE, DEEP, NF1), -/* CPU_GP0 */ PAD_CFG_GPI(GPP_E3, NONE, DEEP), /* MEM_INTERLEAVED */ -/* SATA_DEVSLP0 */ PAD_NC(GPP_E4, NONE), -/* SATA_DEVSLP1 */ PAD_CFG_NF(GPP_E5, NONE, DEEP, NF1), /* M3042_DEVSLP */ -/* SATA_DEVSLP2 */ PAD_CFG_NF(GPP_E6, NONE, DEEP, NF1), /* M2280_DEVSLP */ -/* CPU_GP1 */ PAD_CFG_GPO(GPP_E7, 1, DEEP), /* TOUCH_SCREEN_PD# */ -/* SATALED# */ PAD_CFG_GPI(GPP_E8, NONE, DEEP), /* RECOVERY# */ -/* USB2_OCO# */ PAD_CFG_NF(GPP_E9, NONE, DEEP, NF1), /* USB_OC0# */ -/* USB2_OC1# */ PAD_CFG_NF(GPP_E10, NONE, DEEP, NF1), /* USB_OC1# */ -/* USB2_OC2# */ PAD_NC(GPP_E11, NONE), -/* USB2_OC3# */ PAD_NC(GPP_E12, NONE), -/* DDPB_HPD0 */ PAD_CFG_NF(GPP_E13, NONE, DEEP, NF1), /* DP_HPD_CPU */ -/* DDPC_HPD1 */ PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1), /* DP2_HPD_CPU */ -/* DDPD_HPD2 */ PAD_CFG_GPI(GPP_E15, NONE, DEEP), /* PCH_WP */ -/* DDPE_HPD3 */ PAD_NC(GPP_E16, NONE), /* FFS_INT2 (nostuff) */ -/* EDP_HPD */ PAD_CFG_NF(GPP_E17, NONE, DEEP, NF1), -/* DDPB_CTRLCLK */ PAD_CFG_NF(GPP_E18, NONE, DEEP, NF1), /* HDMI_SCL_CPU */ -/* DDPB_CTRLDATA */ PAD_CFG_NF(GPP_E19, NONE, DEEP, NF1), /* HDMI_SDA_CPU */ -/* DDPC_CTRLCLK */ PAD_NC(GPP_E20, NONE), -/* DDPC_CTRLDATA */ PAD_NC(GPP_E21, NONE), -/* DDPD_CTRLCLK */ PAD_NC(GPP_E22, NONE), -/* DDPD_CTRLDATA */ PAD_NC(GPP_E23, NONE), - -/* CNV_PA_BLANKING */ PAD_CFG_NF(GPP_F0, NONE, DEEP, NF1), /* CNV_COEX3 */ -/* GPP_F1 */ PAD_NC(GPP_F1, NONE), -/* GPP_F2 */ PAD_NC(GPP_F2, NONE), -/* GPP_F3 */ PAD_NC(GPP_F3, NONE), -/* CNV_BRI_DT */ PAD_CFG_NF(GPP_F4, NONE, DEEP, NF1), -/* CNV_BRI_RSP */ PAD_CFG_NF(GPP_F5, NONE, DEEP, NF1), -/* CNV_RGI_DT */ PAD_CFG_NF(GPP_F6, NONE, DEEP, NF1), -/* CNV_RGI_RSP */ PAD_CFG_NF(GPP_F7, NONE, DEEP, NF1), -/* CNV_MFUART2_RXD */ PAD_CFG_NF(GPP_F8, NONE, DEEP, NF1), /* CNV_COEX2 */ -/* CNV_MFUART2_TXD */ PAD_CFG_NF(GPP_F9, NONE, DEEP, NF1), /* CNV_COEX1 */ -/* GPP_F10 */ PAD_NC(GPP_F10, NONE), -/* EMMC_CMD */ PAD_NC(GPP_F11, NONE), -/* EMMC_DATA0 */ PAD_NC(GPP_F12, NONE), -/* EMMC_DATA1 */ PAD_NC(GPP_F13, NONE), -/* EMMC_DATA2 */ PAD_NC(GPP_F14, NONE), -/* EMMC_DATA3 */ PAD_NC(GPP_F15, NONE), -/* EMMC_DATA4 */ PAD_NC(GPP_F16, NONE), -/* EMMC_DATA5 */ PAD_NC(GPP_F17, NONE), -/* EMMC_DATA6 */ PAD_NC(GPP_F18, NONE), -/* EMMC_DATA7 */ PAD_NC(GPP_F19, NONE), -/* EMMC_RCLK */ PAD_NC(GPP_F20, NONE), -/* EMMC_CLK */ PAD_NC(GPP_F21, NONE), -/* EMMC_RESET# */ PAD_NC(GPP_F22, NONE), -/* A4WP_PRESENT */ PAD_NC(GPP_F23, NONE), - -/* SD_CMD */ PAD_CFG_GPI(GPP_G0, NONE, DEEP), /* CAM_MIC_CBL_DET# */ -/* SD_DATA0 */ PAD_NC(GPP_G1, NONE), /* ANT_CONFIG (nostuff) */ -/* SD_DATA1 */ PAD_NC(GPP_G2, NONE), /* TBT_CIO_PLUG_EVT# (nostuff) */ -/* SD_DATA2 */ PAD_NC(GPP_G3, NONE), -/* SD_DATA3 */ PAD_CFG_GPI(GPP_G4, NONE, DEEP), /* CTLESS_DET# */ -/* SD_CD# */ PAD_CFG_GPO(GPP_G5, 1, DEEP), /* HOST_SD_WP# */ -/* SD_CLK */ PAD_CFG_GPO(GPP_G6, 1, DEEP), /* AUD_PWR_EN */ -/* SD_WP */ PAD_CFG_GPI(GPP_G7, NONE, DEEP), /* SPK_DET# */ - -/* I2S2_SCLK */ PAD_NC(GPP_H0, NONE), -/* I2S2_SFRM */ PAD_CFG_NF(GPP_H1, NONE, DEEP, NF3), /* CNV_RF_RESET# */ -/* I2S2_TXD */ PAD_CFG_NF(GPP_H2, NONE, DEEP, NF3), /* CLKREQ_CNV# */ -/* I2S2_RXD */ PAD_NC(GPP_H3, NONE), -/* I2C2_SDA */ PAD_NC(GPP_H4, NONE), -/* I2C2_SCL */ PAD_NC(GPP_H5, NONE), -/* I2C3_SDA */ PAD_NC(GPP_H6, NONE), -/* I2C3_SCL */ PAD_NC(GPP_H7, NONE), -/* I2C4_SDA */ PAD_CFG_NF(GPP_H8, NONE, DEEP, NF1), /* I2C_SDA_H1 */ -/* I2C4_SCL */ PAD_CFG_NF(GPP_H9, NONE, DEEP, NF1), /* I2C_SCL_H1 */ -/* I2C5_SDA */ PAD_NC(GPP_H10, NONE), /* ISH_I2C2_SDA */ -/* I2C5_SCL */ PAD_NC(GPP_H11, NONE), /* ISH_I2C2_SCL */ -/* M2_SKT2_CFG2 */ PAD_NC(GPP_H14, NONE), -/* M2_SKT2_CFG3 */ PAD_CFG_GPO(GPP_H15, 1, DEEP), /* BT_RADIO_DIS# */ -/* DDPF_CTRLCLK */ PAD_NC(GPP_H16, NONE), -/* DPPF_CTRLDATA */ PAD_NC(GPP_H17, NONE), -/* CPU_C10_GATE# */ PAD_CFG_NF(GPP_H18, NONE, DEEP, NF1), /* C10_GATE# */ -/* TIMESYNC0 */ PAD_NC(GPP_H19, NONE), -/* IMGCLKOUT1 */ PAD_NC(GPP_H20, NONE), -/* GPP_H21 */ PAD_NC(GPP_H21, NONE), -/* GPP_H22 */ PAD_NC(GPP_H22, NONE), /* RTD3_CIO_PWR_EN (nostuff) */ -/* GPP_H23 */ PAD_NC(GPP_H23, NONE), - -/* BATLOW# */ PAD_CFG_NF(GPD0, NONE, DEEP, NF1), /* BATLOW# */ -/* ACPRESENT */ PAD_CFG_NF(GPD1, NONE, DEEP, NF1), /* AC_PRESENT */ -/* LAN_WAKE# */ PAD_CFG_NF(GPD2, NONE, DEEP, NF1), /* LAN_WAKE# */ -/* PWRBTN# */ PAD_CFG_NF(GPD3, NONE, DEEP, NF1), /* SIO_PWRBTN# */ -/* SLP_S3# */ PAD_CFG_NF(GPD4, NONE, DEEP, NF1), /* SIO_SLP_S3# */ -/* SLP_S4# */ PAD_CFG_NF(GPD5, NONE, DEEP, NF1), /* SIO_SLP_S4# */ -/* SLP_A# */ PAD_CFG_NF(GPD6, NONE, DEEP, NF1), /* SIO_SLP_A# */ -/* GPD7 */ PAD_NC(GPD7, NONE), /* TBT_RTD3_WAKE# (nostuff) */ -/* SUSCLK */ PAD_CFG_NF(GPD8, NONE, DEEP, NF1), /* SUSCLK */ -/* SLP_WLAN# */ PAD_CFG_NF(GPD9, NONE, DEEP, NF1), /* SIO_SLP_WLAN# */ -/* SLP_S5# */ PAD_CFG_NF(GPD10, NONE, DEEP, NF1), /* SIO_SLP_S5# */ -/* LANPHYC */ PAD_CFG_NF(GPD11, NONE, DEEP, NF1), /* PM_LANPHY_EN */ -}; - -/* Early pad configuration in bootblock */ -static const struct pad_config early_gpio_table[] = { -/* M2_SKT2_CFG1 */ PAD_CFG_GPO(GPP_H13, 1, DEEP), /* M.2 SSD D3 cold */ -/* SSD RESET pin will stay low first */ -/* M2_SKT2_CFG0 */ PAD_CFG_GPO(GPP_H12, 0, DEEP), /* D3 cold RST */ -/* UART2_RXD */ PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1), /* SERVOTX_UART */ -/* UART2_TXD */ PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1), /* SERVORX_UART */ -/* I2C4_SDA */ PAD_CFG_NF(GPP_H8, NONE, DEEP, NF1), /* I2C_SDA_H1 */ -/* I2C4_SCL */ PAD_CFG_NF(GPP_H9, NONE, DEEP, NF1), /* I2C_SCL_H1 */ -/* DMIC_DATA1 */ PAD_CFG_GPI_APIC(GPP_D18, NONE, PLTRST, - EDGE_SINGLE, INVERT), /* H1_PCH_INT_ODL */ -/* RESET# need to stay low before FULL_CARD_POWER_OFF assert */ -/* SPI1_IO2 */ PAD_CFG_GPO(GPP_D21, 0, DEEP), /* WWAN_BB_RST# */ -/* CPU_GP0 */ PAD_CFG_GPI(GPP_E3, NONE, DEEP), /* MEM_INTERLEAVED */ -/* SATALED# */ PAD_CFG_GPI(GPP_E8, NONE, DEEP), /* RECOVERY# */ -/* DDPD_HPD2 */ PAD_CFG_GPI(GPP_E15, NONE, DEEP), /* PCH_WP */ -/* M2_SKT2_CFG0 */ PAD_CFG_GPO(GPP_H12, 1, DEEP), /* D3 cold RST */ -}; - -const struct pad_config *variant_gpio_table(size_t *num) -{ - *num = ARRAY_SIZE(gpio_table); - return gpio_table; -} - -const struct pad_config *variant_early_gpio_table(size_t *num) -{ - *num = ARRAY_SIZE(early_gpio_table); - return early_gpio_table; -} - -static const struct cros_gpio cros_gpios[] = { - CROS_GPIO_REC_AL(GPP_E8, CROS_GPIO_DEVICE_NAME), - CROS_GPIO_WP_AH(GPP_E15, CROS_GPIO_DEVICE_NAME), -}; - -const struct cros_gpio *variant_cros_gpios(size_t *num) -{ - *num = ARRAY_SIZE(cros_gpios); - return cros_gpios; -} diff --git a/src/mainboard/google/drallion/variants/arcada_cml/include/variant/acpi/dptf.asl b/src/mainboard/google/drallion/variants/arcada_cml/include/variant/acpi/dptf.asl deleted file mode 100644 index 73e1decc1b..0000000000 --- a/src/mainboard/google/drallion/variants/arcada_cml/include/variant/acpi/dptf.asl +++ /dev/null @@ -1,73 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright 2018 Google LLC - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#define DPTF_CPU_PASSIVE 98 -#define DPTF_CPU_CRITICAL 108 - -/* Skin Sensor for CPU VR temperature monitor */ -#define DPTF_TSR0_SENSOR_ID 1 -#define DPTF_TSR0_SENSOR_NAME "Skin" -#define DPTF_TSR0_PASSIVE 55 -#define DPTF_TSR0_CRITICAL 100 - -/* Memory Sensor for DDR temperature monitor */ -#define DPTF_TSR1_SENSOR_ID 2 -#define DPTF_TSR1_SENSOR_NAME "DDR" -#define DPTF_TSR1_PASSIVE 53 -#define DPTF_TSR1_CRITICAL 100 - -/* M.2 Sensor for Ambient temperature monitor */ -#define DPTF_TSR2_SENSOR_ID 3 -#define DPTF_TSR2_SENSOR_NAME "Ambient" -#define DPTF_TSR2_PASSIVE 38 -#define DPTF_TSR2_CRITICAL 93 - -#undef DPTF_ENABLE_FAN_CONTROL -#undef DPTF_ENABLE_CHARGER - -Name (DTRT, Package () { - /* CPU Throttle Effect on CPU */ - Package () { \_SB.PCI0.TCPU, \_SB.PCI0.TCPU, 500, 100, 0, 0, 0, 0 }, - - /* CPU Throttle Effect on Skin (TSR0) */ - Package () { \_SB.PCI0.TCPU, \_SB.DPTF.TSR0, 400, 40, 0, 0, 0, 0 }, - - /* CPU Throttle Effect on DDR (TSR1) */ - Package () { \_SB.PCI0.TCPU, \_SB.DPTF.TSR1, 300, 50, 2, 0, 0, 0 }, - - /* CPU Throttle Effect on Ambient (TSR2) */ - Package () { \_SB.PCI0.TCPU, \_SB.DPTF.TSR2, 1000, 100, 1, 0, 0, 0 }, -}) - -Name (MPPC, Package () -{ - 0x2, /* Revision */ - Package () { /* Power Limit 1 */ - 0, /* PowerLimitIndex, 0 for Power Limit 1 */ - 3000, /* PowerLimitMinimum */ - 21000, /* PowerLimitMaximum */ - 28000, /* TimeWindowMinimum */ - 28000, /* TimeWindowMaximum */ - 100 /* StepSize */ - }, - Package () { /* Power Limit 2 */ - 1, /* PowerLimitIndex, 1 for Power Limit 2 */ - 15000, /* PowerLimitMinimum */ - 51000, /* PowerLimitMaximum */ - 28000, /* TimeWindowMinimum */ - 28000, /* TimeWindowMaximum */ - 100 /* StepSize */ - } -}) diff --git a/src/mainboard/google/drallion/variants/arcada_cml/include/variant/acpi/mainboard.asl b/src/mainboard/google/drallion/variants/arcada_cml/include/variant/acpi/mainboard.asl deleted file mode 100644 index 41121d28fe..0000000000 --- a/src/mainboard/google/drallion/variants/arcada_cml/include/variant/acpi/mainboard.asl +++ /dev/null @@ -1,44 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright 2019 Intel Corp. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#define CAM_EN GPP_B11 /* Active low */ -#define TS_PD GPP_E7 - -/* Method called from LPIT prior to enter s0ix state */ -Method (MS0X, 1) -{ - If (Arg0) { - /* Turn off camera power */ - \_SB.PCI0.STXS (CAM_EN) - } Else { - /* Turn on camera power */ - \_SB.PCI0.CTXS (CAM_EN) - } -} - -/* Method called from _PTS prior to enter sleep state */ -Method (MPTS, 1) -{ - \_SB.PCI0.LPCB.EC0.PTS (Arg0) - - /* Clear touch screen pd pin to avoid leakage */ - \_SB.PCI0.CTXS (TS_PD) -} - -/* Method called from _WAK prior to wakeup */ -Method (MWAK, 1) -{ - \_SB.PCI0.LPCB.EC0.WAK (Arg0) -} diff --git a/src/mainboard/google/drallion/variants/arcada_cml/include/variant/ec.h b/src/mainboard/google/drallion/variants/arcada_cml/include/variant/ec.h deleted file mode 100644 index 01a17b5f99..0000000000 --- a/src/mainboard/google/drallion/variants/arcada_cml/include/variant/ec.h +++ /dev/null @@ -1,34 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright 2018 Google LLC - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef VARIANT_EC_H -#define VARIANT_EC_H - -#include -#include - -/* EC wake pin */ -#define EC_WAKE_PIN GPE0_DW1_12 - -/* eSPI virtual wire reporting */ -#define EC_SCI_GPI GPE0_ESPI - -/* Enable PS/2 keyboard */ -#define SIO_EC_ENABLE_PS2K - -/* Enable DPTF */ -#define EC_ENABLE_DPTF - -#endif diff --git a/src/mainboard/google/drallion/variants/arcada_cml/include/variant/gpio.h b/src/mainboard/google/drallion/variants/arcada_cml/include/variant/gpio.h deleted file mode 100644 index f7e0403e59..0000000000 --- a/src/mainboard/google/drallion/variants/arcada_cml/include/variant/gpio.h +++ /dev/null @@ -1,34 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright 2018 Google LLC - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the - * GNU General Public License for more details. - */ - -#ifndef VARIANT_GPIO_H -#define VARIANT_GPIO_H - -#include -#include - -/* Flash Write Protect */ -#define GPIO_PCH_WP GPP_E15 - -/* Recovery mode */ -#define GPIO_REC_MODE GPP_E8 - -const struct pad_config *variant_gpio_table(size_t *num); -const struct pad_config *variant_early_gpio_table(size_t *num); - -struct cros_gpio; -const struct cros_gpio *variant_cros_gpios(size_t *num); - -#endif diff --git a/src/mainboard/google/drallion/variants/arcada_cml/include/variant/hda_verb.h b/src/mainboard/google/drallion/variants/arcada_cml/include/variant/hda_verb.h deleted file mode 100644 index 10fbaf13f5..0000000000 --- a/src/mainboard/google/drallion/variants/arcada_cml/include/variant/hda_verb.h +++ /dev/null @@ -1,209 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright 2018 Google LLC - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef MAINBOARD_HDA_VERB_H -#define MAINBOARD_HDA_VERB_H - -#include - -const u32 cim_verb_data[] = { - /* coreboot specific header */ - 0x10ec0295, // Codec Vendor / Device ID: Realtek ALC3204 - 0xffffffff, // Subsystem ID - 0x0000002b, // Number of jacks (NID entries) - - /* Rest Codec First */ - AZALIA_RESET(0x1), - /* NID 0x01, HDA Codec Subsystem ID Verb Table */ - AZALIA_SUBVENDOR(0x0, 0x102808b6), - - /* Pin Widget Verb Table */ - AZALIA_PIN_CFG(0x0, 0x12, 0xb7a60130), - AZALIA_PIN_CFG(0x0, 0x13, 0x411111f0), - AZALIA_PIN_CFG(0x0, 0x14, 0x90170110), - AZALIA_PIN_CFG(0x0, 0x16, 0x40000000), - AZALIA_PIN_CFG(0x0, 0x17, 0x411111f0), - AZALIA_PIN_CFG(0x0, 0x18, 0x411111f0), - AZALIA_PIN_CFG(0x0, 0x19, 0x04a11030), - AZALIA_PIN_CFG(0x0, 0x1a, 0x411111f0), - AZALIA_PIN_CFG(0x0, 0x1b, 0x411111f0), - AZALIA_PIN_CFG(0x0, 0x1d, 0x40c00001), - AZALIA_PIN_CFG(0x0, 0x1e, 0x421212f2), - AZALIA_PIN_CFG(0x0, 0x21, 0x04211020), - - /* D reset */ - 0x0205003C, - 0x0204F254, - 0x0205003C, - 0x0204F214, - /* JD1 - 2port JD mode */ - 0x02050009, - 0x0204E003, - 0x0205000A, - 0x02047770, - /* Set TRS type-1 */ - 0x02050045, - 0x02045289, - 0x02050049, - 0x02040049, - /* Set TRS type-2 + Set UAJ Line2 vref(ALC3254) */ - 0x0205004A, - 0x0204A830, - 0x02050063, - 0x0204CF00, - /* NID 0x20 set class-D to 2W@4ohm (+12dB gain) - * + Set sine tone gain(0x34) */ - 0x02050038, - 0x02043909, - 0x05C50000, - 0x05C43482, - /* AGC-1 Disable + (Front Gain=0dB ) */ - 0x05D50006, - 0x05D44C50, - 0x05D50002, - 0x05D44004, - /* AGC-2 (Backt Boost Gain= -0.375dB ,Limiter = -3dB) */ - 0x05D50003, - 0x05D45E5E, - 0x05D50001, - 0x05D4D788, - /* AGC-3 + AGC Enable */ - 0x05D50009, - 0x05D451FF, - 0x05D50006, - 0x05D44E50, - /* HP-JD Enable +Nokia type */ - 0x0205004A, - 0x02042010, - 0x02050008, - 0x02046A0C, - /* EAPD set to verb-control + I2C Un-use+ DVDD3.3V */ - 0x02050010, - 0x02040020, - 0x02050034, - 0x0204A23D, - /* Class D silent detection Enable -84dB threshold */ - 0x02050030, - 0x02049000, - 0x02050037, - 0x0204FE15, - /* Disable EQ + set 250Hz 3rd High Pass filter */ - 0x05350000, - 0x0534203A, - 0x05350000, - 0x0534203A, - /* Left Channel-1 */ - 0x0535001d, - 0x05340800, - 0x0535001e, - 0x05340800, - /* Left Channel-2 */ - 0x05350003, - 0x05341EF8, - 0x05350004, - 0x05340000, - /* Left Channel-3 */ - 0x05350005, - 0x053403EE, - 0x05350006, - 0x0534FA60, - /* Left Channel-4 */ - 0x05350007, - 0x05341E10, - 0x05350008, - 0x05347B86, - /* Left Channel-5 */ - 0x05350009, - 0x053401F7, - 0x0535000A, - 0x05349FB6, - /* Left Channel-6 */ - 0x0535000B, - 0x05341C00, - 0x0535000C, - 0x05340000, - /* Left Channel-7 */ - 0x0535000D, - 0x05340200, - 0x0535000E, - 0x05340000, - /* Right Channel-1 */ - 0x05450000, - 0x05442000, - 0x0545001d, - 0x05440800, - /* Right Channel-2 */ - 0x0545001e, - 0x05440800, - 0x05450003, - 0x05441EF8, - /* Right Channel-3 */ - 0x05450004, - 0x05440000, - 0x05450005, - 0x054403EE, - /* Right Channel-4 */ - 0x05450006, - 0x0544FA60, - 0x05450007, - 0x05441E10, - /* Right Channel-5 */ - 0x05450008, - 0x05447B86, - 0x05450009, - 0x054401F7, - /* Right Channel-6 */ - 0x0545000A, - 0x05449FB6, - 0x0545000B, - 0x05441C00, - /* Right Channel-7 */ - 0x0545000C, - 0x05440000, - 0x0545000D, - 0x05440200, - /* Right Channel-8 + EQ Update & Enable */ - 0x0545000E, - 0x05440000, - 0x05350000, - 0x0534E03A, - /* Enable all Microphone */ - 0x0205000D, - 0x0204A023, - 0x0205000D, - 0x0204A023, - /* Enable Internal Speaker (NID14) */ - 0x0205000F, - 0x02040000, - 0x0205000F, - 0x02040000, -}; - -const u32 pc_beep_verbs[] = { - /* PCBeep pass through to NID14 for ePSA test-1 */ - 0x02050036, - 0x020477D7, - 0x0143B000, - 0x01470740, - /* PCBeep pass through to NID14 for ePSA test-2 */ - 0x01470C02, - 0x01470C02, - 0x01470C02, - 0x01470C02, -}; - -AZALIA_ARRAY_SIZES; - -#endif diff --git a/src/mainboard/google/drallion/variants/arcada_cml/include/variant/variant.h b/src/mainboard/google/drallion/variants/arcada_cml/include/variant/variant.h deleted file mode 100644 index da1189e14c..0000000000 --- a/src/mainboard/google/drallion/variants/arcada_cml/include/variant/variant.h +++ /dev/null @@ -1,25 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright 2018 Google LLC - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef VARIANT_H -#define VARIANT_H - -/* Arcada is SKU ID 2 and 4 */ -#define VARIANT_SKU_ID 2 -#define VARIANT_SKU_NAME "sku2" -#define VARIANT_SKU_ID_SIGNED_EC 4 -#define VARIANT_SKU_NAME_SIGNED_EC "sku4" - -#endif diff --git a/src/mainboard/google/drallion/variants/arcada_cml/sku.c b/src/mainboard/google/drallion/variants/arcada_cml/sku.c deleted file mode 100644 index d0b48f0572..0000000000 --- a/src/mainboard/google/drallion/variants/arcada_cml/sku.c +++ /dev/null @@ -1,35 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright 2018 Google LLC - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include -#include - -uint32_t sku_id(void) -{ - if (wilco_ec_signed_fw()) - return VARIANT_SKU_ID_SIGNED_EC; - else - return VARIANT_SKU_ID; -} - -const char *smbios_system_sku(void) -{ - if (wilco_ec_signed_fw()) - return VARIANT_SKU_NAME_SIGNED_EC; - else - return VARIANT_SKU_NAME; -} diff --git a/src/mainboard/google/drallion/variants/sarien_cml/Makefile.inc b/src/mainboard/google/drallion/variants/sarien_cml/Makefile.inc deleted file mode 100644 index b979be187e..0000000000 --- a/src/mainboard/google/drallion/variants/sarien_cml/Makefile.inc +++ /dev/null @@ -1,24 +0,0 @@ -## -## This file is part of the coreboot project. -## -## Copyright 2018 Google LLC -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; version 2 of the License. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## - -## GPP_F12-F16 indicates mem_id to match specific spd file -SPD_SOURCES = empty_ddr4 # 0b00000 - -bootblock-y += gpio.c -ramstage-y += gpio.c -romstage-y += gpio.c -verstage-y += gpio.c - -ramstage-y += sku.c diff --git a/src/mainboard/google/drallion/variants/sarien_cml/devicetree.cb b/src/mainboard/google/drallion/variants/sarien_cml/devicetree.cb deleted file mode 100644 index c466637918..0000000000 --- a/src/mainboard/google/drallion/variants/sarien_cml/devicetree.cb +++ /dev/null @@ -1,424 +0,0 @@ -chip soc/intel/cannonlake - - # GPE configuration - # Note that GPE events called out in ASL code rely on this - # route. i.e. If this route changes then the affected GPE - # offset bits also need to be changed. - register "gpe0_dw0" = "PMC_GPP_A" - register "gpe0_dw1" = "PMC_GPP_C" - register "gpe0_dw2" = "PMC_GPP_D" - - # EC host command ranges - register "gen1_dec" = "0x00040931" # 0x930-0x937 - register "gen2_dec" = "0x00040941" # 0x940-0x947 - register "gen3_dec" = "0x000c0951" # 0x950-0x95f - - # FSP configuration - register "SaGv" = "SaGv_Enabled" - register "HeciEnabled" = "0" - register "SataSalpSupport" = "1" - register "SataMode" = "Sata_AHCI" - register "SataPortsEnable[0]" = "1" - register "SataPortsEnable[1]" = "1" - register "SataPortsEnable[2]" = "1" - register "SataPortsDevSlp[0]" = "1" - register "SataPortsDevSlp[1]" = "1" - register "SataPortsDevSlp[2]" = "1" - register "InternalGfx" = "1" - register "SkipExtGfxScan" = "1" - register "PchPmSlpS3MinAssert" = "3" # 50ms - register "PchPmSlpS4MinAssert" = "4" # 4s - register "PchPmSlpSusMinAssert" = "4" # 4s - register "PchPmSlpAMinAssert" = "4" # 2s - - register "speed_shift_enable" = "1" - register "s0ix_enable" = "1" - register "dptf_enable" = "1" - register "satapwroptimize" = "1" - register "AcousticNoiseMitigation" = "1" - register "SlowSlewRateForIa" = "2" - register "SlowSlewRateForGt" = "2" - register "SlowSlewRateForSa" = "2" - register "SlowSlewRateForFivr" = "2" - register "tdp_pl1_override" = "15" - register "tdp_pl2_override" = "51" - register "psys_pmax" = "136" - register "Device4Enable" = "1" - # Enable eDP device - register "DdiPortEdp" = "1" - # Enable HPD for DDI ports B/C - register "DdiPortBHpd" = "1" - register "DdiPortCHpd" = "1" - # Enable DDC for DDI port B - register "DdiPortBDdc" = "1" - - register "LanWakeFromDeepSx" = "0" - register "WolEnableOverride" = "0" - - # Disable iDisplay codec enumeration - register "PchHdaIDispCodecDisconnect" = "1" - register "PchHdaAudioLinkHda" = "1" - - # VR Settings Configuration for 4 Domains - #+----------------+-------+-------+-------+-------+ - #| Domain/Setting | SA | IA | GTUS | GTS | - #+----------------+-------+-------+-------+-------+ - #| Psi1Threshold | 20A | 20A | 20A | 20A | - #| Psi2Threshold | 5A | 5A | 5A | 5A | - #| Psi3Threshold | 1A | 1A | 1A | 1A | - #| Psi3Enable | 1 | 1 | 1 | 1 | - #| Psi4Enable | 1 | 1 | 1 | 1 | - #| ImonSlope | 0 | 0 | 0 | 0 | - #| ImonOffset | 0 | 0 | 0 | 0 | - #| IccMax | 6A | 70A | 31A | 31A | - #| VrVoltageLimit | 1.52V | 1.52V | 1.52V | 1.52V | - #| AcLoadline | 10.3 | 1.8 | 3.1 | 3.1 | - #| DcLoadline | 10.3 | 1.8 | 3.1 | 3.1 | - #+----------------+-------+-------+-------+-------+ - register "domain_vr_config[VR_SYSTEM_AGENT]" = "{ - .vr_config_enable = 1, - .psi1threshold = VR_CFG_AMP(20), - .psi2threshold = VR_CFG_AMP(5), - .psi3threshold = VR_CFG_AMP(1), - .psi3enable = 1, - .psi4enable = 1, - .imon_slope = 0x0, - .imon_offset = 0x0, - .icc_max = VR_CFG_AMP(6), - .voltage_limit = 1520, - .ac_loadline = 1030, - .dc_loadline = 1030, - }" - - register "domain_vr_config[VR_IA_CORE]" = "{ - .vr_config_enable = 1, - .psi1threshold = VR_CFG_AMP(20), - .psi2threshold = VR_CFG_AMP(5), - .psi3threshold = VR_CFG_AMP(1), - .psi3enable = 1, - .psi4enable = 1, - .imon_slope = 0x0, - .imon_offset = 0x0, - .icc_max = VR_CFG_AMP(70), - .voltage_limit = 1520, - .ac_loadline = 180, - .dc_loadline = 180, - }" - - register "domain_vr_config[VR_GT_UNSLICED]" = "{ - .vr_config_enable = 1, - .psi1threshold = VR_CFG_AMP(20), - .psi2threshold = VR_CFG_AMP(5), - .psi3threshold = VR_CFG_AMP(1), - .psi3enable = 1, - .psi4enable = 1, - .imon_slope = 0x0, - .imon_offset = 0x0, - .icc_max = VR_CFG_AMP(31), - .voltage_limit = 1520, - .ac_loadline = 310, - .dc_loadline = 310, - }" - - register "domain_vr_config[VR_GT_SLICED]" = "{ - .vr_config_enable = 1, - .psi1threshold = VR_CFG_AMP(20), - .psi2threshold = VR_CFG_AMP(5), - .psi3threshold = VR_CFG_AMP(1), - .psi3enable = 1, - .psi4enable = 1, - .imon_slope = 0x0, - .imon_offset = 0x0, - .icc_max = VR_CFG_AMP(31), - .voltage_limit = 1520, - .ac_loadline = 310, - .dc_loadline = 310, - }" - - # Intel Common SoC Config - register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC_SKIP)" # Left Type-C Port - register "usb2_ports[1]" = "USB2_PORT_LONG(OC0)" # Right Type-A Port 1 - register "usb2_ports[2]" = "USB2_PORT_LONG(OC1)" # Left Type-A Port - register "usb2_ports[3]" = "USB2_PORT_LONG(OC2)" # Right Type-A Port 2 - register "usb2_ports[4]" = "USB2_PORT_EMPTY" - register "usb2_ports[5]" = "USB2_PORT_LONG(OC_SKIP)" # Camera - register "usb2_ports[6]" = "USB2_PORT_MID(OC_SKIP)" # WWAN - register "usb2_ports[7]" = "USB2_PORT_MID(OC_SKIP)" # USH - register "usb2_ports[8]" = "USB2_PORT_MID(OC_SKIP)" # Fingerprint - register "usb2_ports[9]" = "USB2_PORT_MID(OC_SKIP)" # Bluetooth - - register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Left Type-C Port - register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC0)" # Right Type-A Port 1 - register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC1)" # Left Type-A Port - register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC2)" # Right Type-A Port 2 - register "usb3_ports[4]" = "USB3_PORT_DEFAULT(OC_SKIP)" # WWAN - register "usb3_ports[5]" = "USB3_PORT_EMPTY" - - # Intel Common SoC Config - #+-------------------+---------------------------+ - #| Field | Value | - #+-------------------+---------------------------+ - #| chipset_lockdown | CHIPSET_LOCKDOWN_COREBOOT | - #| I2C0 | Touchscreen | - #| I2C1 | Touchpad | - #| I2C4 | H1 TPM | - #+-------------------+---------------------------+ - - register "tcc_offset" = "10" - - # PCH Thermal Trip Temperature in deg C - register "common_soc_config.pch_thermal_trip" = "77" - - register "common_soc_config" = "{ - .chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT, - .i2c[0] = { - .speed = I2C_SPEED_FAST, - .rise_time_ns = 100, - .fall_time_ns = 80, - }, - .i2c[1] = { - .speed = I2C_SPEED_FAST, - .rise_time_ns = 80, - .fall_time_ns = 110, - }, - .i2c[4] = { - .early_init = 1, - .speed = I2C_SPEED_FAST, - .rise_time_ns = 36, - .fall_time_ns = 99, - }, - }" - - # PCIe port 8 for Card Reader - register "PcieRpEnable[7]" = "1" - register "PcieRpLtrEnable[7]" = "1" - register "PcieClkSrcUsage[4]" = "7" - register "PcieClkSrcClkReq[4]" = "4" - - # PCIe port 9 for LAN - register "PcieRpEnable[8]" = "1" - register "PcieClkSrcUsage[3]" = "PCIE_CLK_LAN" - register "PcieClkSrcClkReq[3]" = "3" - - # PCIe port 10 for M.2 2230 WLAN - register "PcieRpEnable[9]" = "1" - register "PcieClkSrcUsage[1]" = "9" - register "PcieClkSrcClkReq[1]" = "1" - - # PCIe port 13 for M.2 2280 SSD - register "PcieRpEnable[12]" = "1" - register "PcieRpLtrEnable[12]" = "1" - register "PcieClkSrcUsage[2]" = "12" - register "PcieClkSrcClkReq[2]" = "2" - - # GPIO PM programming - register "gpio_override_pm" = "1" - - # GPIO community PM configuration - # Disable dynamic clock gating; with bits 0-5 set in these registers, - # some short interrupt pulses were missed (esp. cr50 irq) - register "gpio_pm[COMM_0]" = "0" - register "gpio_pm[COMM_1]" = "0" - register "gpio_pm[COMM_2]" = "0" - register "gpio_pm[COMM_3]" = "0" - register "gpio_pm[COMM_4]" = "0" - - device cpu_cluster 0 on - device lapic 0 on end - end - device domain 0 on - device pci 00.0 on end # Host Bridge - device pci 02.0 on end # Integrated Graphics Device - device pci 04.0 on end # SA Thermal device - device pci 12.0 on end # Thermal Subsystem - device pci 12.5 off end # UFS SCS - device pci 12.6 off end # GSPI #2 - device pci 13.0 off end # Integrated Sensor Hub - device pci 14.0 on - chip drivers/usb/acpi - register "desc" = ""Root Hub"" - register "type" = "UPC_TYPE_HUB" - device usb 0.0 on - chip drivers/usb/acpi - register "desc" = ""Left Type-C Port"" - register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" - register "group" = "ACPI_PLD_GROUP(1, 1)" - device usb 2.0 on end - end - chip drivers/usb/acpi - register "desc" = ""Right Type-A Port 1"" - register "type" = "UPC_TYPE_A" - register "group" = "ACPI_PLD_GROUP(2, 1)" - device usb 2.1 on end - end - chip drivers/usb/acpi - register "desc" = ""Left Type-A Port"" - register "type" = "UPC_TYPE_A" - register "group" = "ACPI_PLD_GROUP(1, 2)" - device usb 2.2 on end - end - chip drivers/usb/acpi - register "desc" = ""Right Type-A Port 2"" - register "type" = "UPC_TYPE_A" - register "group" = "ACPI_PLD_GROUP(2, 2)" - device usb 2.4 on end - end - chip drivers/usb/acpi - register "desc" = ""Camera"" - register "type" = "UPC_TYPE_INTERNAL" - device usb 2.5 on end - end - chip drivers/usb/acpi - register "desc" = ""WWAN"" - register "type" = "UPC_TYPE_INTERNAL" - device usb 2.6 on end - end - chip drivers/usb/acpi - register "desc" = ""USH"" - register "type" = "UPC_TYPE_INTERNAL" - device usb 2.7 on end - end - chip drivers/usb/acpi - register "desc" = ""Fingerprint"" - register "type" = "UPC_TYPE_INTERNAL" - device usb 2.8 on end - end - chip drivers/usb/acpi - register "desc" = ""Bluetooth"" - register "type" = "UPC_TYPE_INTERNAL" - register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_H15)" - device usb 2.9 on end - end - chip drivers/usb/acpi - register "desc" = ""Left Type-C Port"" - register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" - register "group" = "ACPI_PLD_GROUP(1, 1)" - device usb 3.0 on end - end - chip drivers/usb/acpi - register "desc" = ""Right Type-A Port 1"" - register "type" = "UPC_TYPE_USB3_A" - register "group" = "ACPI_PLD_GROUP(2, 1)" - device usb 3.1 on end - end - chip drivers/usb/acpi - register "desc" = ""Left Type-A Port"" - register "type" = "UPC_TYPE_USB3_A" - register "group" = "ACPI_PLD_GROUP(1, 2)" - device usb 3.2 on end - end - chip drivers/usb/acpi - register "desc" = ""Right Type-A Port 2"" - register "type" = "UPC_TYPE_USB3_A" - register "group" = "ACPI_PLD_GROUP(2, 2)" - device usb 3.3 on end - end - chip drivers/usb/acpi - register "desc" = ""WWAN"" - register "type" = "UPC_TYPE_INTERNAL" - device usb 3.4 on end - end - end - end - end # USB xHCI - device pci 14.1 off end # USB xDCI (OTG) - chip drivers/intel/wifi - register "wake" = "PME_B0_EN_BIT" - device pci 14.3 on end # CNVi wifi - end - device pci 14.5 off end # SDCard - device pci 15.0 on - chip drivers/i2c/hid - register "generic.hid" = ""ELAN900C"" - register "generic.desc" = ""ELAN Touchscreen"" - register "generic.irq" = "ACPI_IRQ_EDGE_LOW(GPP_C23_IRQ)" - register "generic.probed" = "1" - register "generic.reset_gpio" = - "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_E7)" - register "generic.reset_delay_ms" = "10" - register "generic.enable_gpio" = - "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_B21)" - register "generic.enable_delay_ms" = "55" - register "generic.has_power_resource" = "1" - register "hid_desc_reg_offset" = "0x01" - register "generic.device_present_gpio" = "GPP_B4" - register "generic.device_present_gpio_invert" = "1" - device i2c 10 on end - end - chip drivers/i2c/generic - register "hid" = ""MLFS0000"" - register "desc" = ""Melfas Touchscreen"" - register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_C23_IRQ)" - register "probed" = "1" - register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_E7)" - register "reset_delay_ms" = "10" - register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_B21)" - register "enable_delay_ms" = "55" - register "has_power_resource" = "1" - register "device_present_gpio" = "GPP_B4" - register "device_present_gpio_invert" = "1" - device i2c 34 on end - end - end # I2C #0 - device pci 15.1 on - chip drivers/i2c/generic - register "hid" = ""ELAN0000"" - register "desc" = ""ELAN Touchpad"" - register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_B3_IRQ)" - register "probed" = "1" - device i2c 2c on end - end - end # I2C #1 - device pci 15.2 off end # I2C #2 - device pci 15.3 off end # I2C #3 - device pci 16.0 on end # Management Engine Interface 1 - device pci 16.1 off end # Management Engine Interface 2 - device pci 16.2 off end # Management Engine IDE-R - device pci 16.3 off end # Management Engine KT Redirection - device pci 16.4 off end # Management Engine Interface 3 - device pci 16.5 off end # Management Engine Interface 4 - device pci 17.0 on end # SATA - device pci 19.0 on - chip drivers/i2c/tpm - register "hid" = ""GOOG0005"" - register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_D18_IRQ)" - device i2c 50 on end - end - end # I2C #4 - device pci 19.1 off end # I2C #5 - device pci 19.2 on end # UART #2 - device pci 1a.0 off end # eMMC - device pci 1c.0 on end # PCI Express Port 1 (USB) - device pci 1c.1 off end # PCI Express Port 2 (USB) - device pci 1c.2 off end # PCI Express Port 3 (USB) - device pci 1c.3 off end # PCI Express Port 4 (USB) - device pci 1c.4 off end # PCI Express Port 5 (USB) - device pci 1c.5 off end # PCI Express Port 6 - device pci 1c.6 off end # PCI Express Port 7 - device pci 1c.7 on end # PCI Express Port 8 - device pci 1d.0 on - smbios_slot_desc "SlotTypeM2Socket1_SD" "SlotLengthOther" "2230" "SlotDataBusWidth1X" - end # PCI Express Port 9 - device pci 1d.1 on end # PCI Express Port 10 - device pci 1d.2 off end # PCI Express Port 11 - device pci 1d.3 off end # PCI Express Port 12 - device pci 1d.4 on - smbios_slot_desc "SlotTypeM2Socket3" "SlotLengthOther" "2280" "SlotDataBusWidth4X" - end # PCI Express Port 13 (x4) - device pci 1e.0 off end # UART #0 - device pci 1e.1 off end # UART #1 - device pci 1e.2 off end # GSPI #0 - device pci 1e.3 off end # GSPI #1 - device pci 1f.0 on - chip ec/google/wilco - device pnp 0c09.0 on end - end - end # LPC/eSPI - device pci 1f.1 on end # P2SB - device pci 1f.2 on end # Power Management Controller - device pci 1f.3 on end # Intel HDA - device pci 1f.4 on end # SMBus - device pci 1f.5 on end # PCH SPI - device pci 1f.6 off end # GbE - end -end diff --git a/src/mainboard/google/drallion/variants/sarien_cml/gpio.c b/src/mainboard/google/drallion/variants/sarien_cml/gpio.c deleted file mode 100644 index 78db12e8a1..0000000000 --- a/src/mainboard/google/drallion/variants/sarien_cml/gpio.c +++ /dev/null @@ -1,267 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright 2018 Google LLC - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the - * GNU General Public License for more details. - */ - -#include -#include - -/* Pad configuration in ramstage */ -static const struct pad_config gpio_table[] = { -/* RCIN# */ PAD_NC(GPP_A0, NONE), -/* ESPI_IO0 */ -/* ESPI_IO1 */ -/* ESPI_IO2 */ -/* ESPI_IO3 */ -/* ESPI_CS# */ -/* SERIRQ */ -/* PIRQA# */ PAD_NC(GPP_A7, NONE), -/* CLKRUN# */ PAD_NC(GPP_A8, NONE), -/* ESPI_CLK */ -/* CLKOUT_LPC1 */ PAD_NC(GPP_A10, NONE), -/* PME# */ PAD_NC(GPP_A11, NONE), -/* BM_BUSY# */ PAD_NC(GPP_A12, NONE), - -/* ESPI_RESET# */ - -/* SD_1P8_SEL */ PAD_NC(GPP_A16, NONE), -/* SD_PWR_EN# */ PAD_NC(GPP_A17, NONE), -/* ISH_GP0 */ PAD_NC(GPP_A18, NONE), -/* ISH_GP1 */ PAD_NC(GPP_A19, NONE), -/* ISH_GP2 */ PAD_NC(GPP_A20, NONE), -/* ISH_GP3 */ PAD_NC(GPP_A21, NONE), -/* ISH_GP4 */ PAD_NC(GPP_A22, NONE), -/* ISH_GP5 */ PAD_NC(GPP_A23, NONE), - -/* CORE_VID0 */ -/* CORE_VID1 */ -/* VRALERT# */ PAD_NC(GPP_B2, NONE), -/* CPU_GP2 */ PAD_CFG_GPI_APIC(GPP_B3, NONE, PLTRST, - EDGE_SINGLE, INVERT), /* TOUCHPAD_INTR# */ -/* CPU_GP3 */ PAD_CFG_GPI(GPP_B4, NONE, DEEP), /* TOUCH_SCREEN_DET# */ -/* SRCCLKREQ0# */ PAD_CFG_NF(GPP_B5, NONE, DEEP, NF1), /* CLKREQ_PCIE#0 */ -/* SRCCLKREQ1# */ PAD_CFG_NF(GPP_B6, NONE, DEEP, NF1), /* CLKREQ_PCIE#1 */ -/* SRCCLKREQ2# */ PAD_CFG_NF(GPP_B7, NONE, DEEP, NF1), /* CLKREQ_PCIE#2 */ -/* SRCCLKREQ3# */ PAD_CFG_NF(GPP_B8, NONE, DEEP, NF1), /* CLKREQ_PCIE#3 */ -/* SRCCLKREQ4# */ PAD_CFG_NF(GPP_B9, NONE, DEEP, NF1), /* CLKREQ_PCIE#4 */ -/* SRCCLKREQ5# */ PAD_NC(GPP_B10, NONE), -/* EXT_PWR_GATE# */ PAD_CFG_GPO(GPP_B11, 0, DEEP), /* 3.3V_CAM_EN# */ -/* SLP_S0# */ PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1), -/* PLTRST# */ PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1), -/* SPKR */ PAD_CFG_NF(GPP_B14, NONE, DEEP, NF1), -/* GSPI0_CS# */ PAD_NC(GPP_B15, NONE), -/* GSPI0_CLK */ PAD_NC(GPP_B16, NONE), -/* GSPI0_MISO */ PAD_NC(GPP_B17, NONE), -/* GSPI0_MOSI */ PAD_NC(GPP_B18, NONE), -/* GSPI1_CS# */ PAD_NC(GPP_B19, NONE), /* HDD_FALL_INT (nostuff) */ -/* GSPI1_CLK */ PAD_NC(GPP_B20, NONE), /* TPM_PIRQ# (nostuff) */ -/* GSPI1_MISO */ PAD_CFG_GPO(GPP_B21, 1, DEEP), /* PCH_3.3V_TS_EN */ -/* GSPI1_MOSI */ PAD_NC(GPP_B22, NONE), -/* SML1ALERT# */ PAD_NC(GPP_B23, DN_20K), - -/* SMBCLK */ PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1), /* MEM_SMBCLK */ -/* SMBDATA */ PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1), /* MEM_SMBDATA */ -/* SMBALERT# */ PAD_NC(GPP_C2, DN_20K), -/* SML0CLK */ PAD_CFG_NF(GPP_C3, NONE, DEEP, NF1), /* SML0_SMBCLK */ -/* SML0DATA */ PAD_CFG_NF(GPP_C4, NONE, DEEP, NF1), /* SML0_SMBDATA */ -/* SML0ALERT# */ PAD_NC(GPP_C5, DN_20K), -/* SM1CLK */ PAD_CFG_NF(GPP_C6, NONE, DEEP, NF1), /* SML1_SMBCLK */ -/* SM1DATA */ PAD_CFG_NF(GPP_C7, NONE, DEEP, NF1), /* SML1_SMBDATA */ -/* UART0_RXD */ PAD_NC(GPP_C8, NONE), -/* UART0_TXD */ PAD_NC(GPP_C9, NONE), -/* UART0_RTS# */ PAD_CFG_GPI(GPP_C10, NONE, DEEP), /* TYPEC_CON_SEL1 */ -/* UART0_CTS# */ PAD_CFG_GPI(GPP_C11, NONE, DEEP), /* TYPEC_CON_SEL2 */ -/* UART1_RXD */ PAD_CFG_GPI_SCI_LOW(GPP_C12, NONE, DEEP, - EDGE_SINGLE), /* SIO_EXT_WAKE# */ -/* UART1_TXD */ PAD_NC(GPP_C13, NONE), -/* UART1_RTS# */ PAD_CFG_GPI(GPP_C14, NONE, DEEP), /* LCD_CBL_DET# */ -/* UART1_CTS# */ PAD_NC(GPP_C15, NONE), -/* I2C0_SDA */ PAD_CFG_NF(GPP_C16, NONE, DEEP, NF1), /* TS_I2C_SDA */ -/* I2C0_SCL */ PAD_CFG_NF(GPP_C17, NONE, DEEP, NF1), /* TS_I2C_SCL */ -/* I2C1_SDA */ PAD_CFG_NF(GPP_C18, NONE, DEEP, NF1), /* I2C1_SDA_TP */ -/* I2C1_SCL */ PAD_CFG_NF(GPP_C19, NONE, DEEP, NF1), /* I2C1_SCK_TP */ -/* UART2_RXD */ PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1), /* SERVOTX_UART */ -/* UART2_TXD */ PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1), /* SERVORX_UART */ -/* UART2_RTS# */ PAD_NC(GPP_C22, NONE), -/* UART2_CTS# */ PAD_CFG_GPI_APIC(GPP_C23, NONE, PLTRST, - EDGE_SINGLE, INVERT), /* TS_INT# */ - -/* SPI1_CS# */ PAD_CFG_GPI_APIC(GPP_D0, NONE, PLTRST, - EDGE_SINGLE, INVERT), /* MEDIACARD_IRQ# */ -/* SPI1_CLK */ PAD_NC(GPP_D1, NONE), -/* SPI1_MISO */ PAD_NC(GPP_D2, NONE), -/* SPI1_MOSI */ PAD_CFG_GPI(GPP_D3, NONE, DEEP), /* RTC_DET# */ -/* FASHTRIG */ PAD_NC(GPP_D4, NONE), -/* ISH_I2C0_SDA */ PAD_NC(GPP_D5, NONE), -/* ISH_I2C0_SCL */ PAD_NC(GPP_D6, NONE), -/* ISH_I2C1_SDA */ PAD_NC(GPP_D7, NONE), -/* ISH_I2C1_SCL */ PAD_NC(GPP_D8, NONE), -/* ISH_SPI_CS# */ PAD_CFG_GPI(GPP_D9, NONE, DEEP), /* IR_CAM_DET# */ -/* ISH_SPI_CLK */ PAD_NC(GPP_D10, NONE), -/* ISH_SPI_MISO */ PAD_CFG_GPI(GPP_D11, NONE, DEEP), /* TBT_DET# */ -/* ISH_SPI_MOSI */ PAD_NC(GPP_D12, NONE), -/* ISH_UART0_RXD */ PAD_NC(GPP_D13, NONE), -/* ISH_UART0_TXD */ PAD_NC(GPP_D14, NONE), -/* ISH_UART0_RTS# */ PAD_CFG_GPO(GPP_D15, 1, DEEP), /* WWAN_FULL_PWR_EN */ -/* ISH_UART0_CTS# */ PAD_NC(GPP_D16, NONE), -/* DMIC_CLK1 */ PAD_CFG_GPI(GPP_D17, NONE, DEEP), /* KB_DET# */ -/* DMIC_DATA1 */ PAD_CFG_GPI_APIC(GPP_D18, NONE, PLTRST, - EDGE_SINGLE, INVERT), /* H1_PCH_INT_ODL */ -/* DMIC_CLK0 */ PAD_NC(GPP_D19, NONE), -/* DMIC_DATA0 */ PAD_NC(GPP_D20, NONE), -/* SPI1_IO2 */ PAD_CFG_GPO(GPP_D21, 1, DEEP), /* WWAN_BB_RST# */ -/* SPI1_IO3 */ PAD_CFG_GPO(GPP_D22, 0, DEEP), /* WWAN_GPIO_PERST# */ -/* I2S_MCLK */ PAD_CFG_GPI_SCI_LOW(GPP_D23, NONE, DEEP, - EDGE_SINGLE), /* WWAN_GPIO_WAKE# */ - -/* SATAXPCIE0 */ PAD_CFG_NF(GPP_E0, NONE, DEEP, NF1), /* HDD_DET# */ - /* M3042_PCIE#_SATA */ -/* SATAXPCIE1 */ PAD_CFG_NF(GPP_E1, NONE, DEEP, NF1), - /* M2880_PCIE_SATA# */ -/* SATAXPCIE2 */ PAD_CFG_NF(GPP_E2, NONE, DEEP, NF1), -/* CPU_GP0 */ PAD_CFG_GPI(GPP_E3, NONE, DEEP), /* MEM_INTERLEAVED */ -/* SATA_DEVSLP0 */ PAD_CFG_NF(GPP_E4, NONE, DEEP, NF1), /* HDD_DEVSLP */ -/* SATA_DEVSLP1 */ PAD_CFG_NF(GPP_E5, NONE, DEEP, NF1), /* M3042_DEVSLP */ -/* SATA_DEVSLP2 */ PAD_CFG_NF(GPP_E6, NONE, DEEP, NF1), /* M2280_DEVSLP */ -/* CPU_GP1 */ PAD_CFG_GPO(GPP_E7, 1, DEEP), /* TOUCH_SCREEN_PD# */ -/* SATALED# */ PAD_CFG_GPI(GPP_E8, NONE, DEEP), /* RECOVERY# */ -/* USB2_OCO# */ PAD_CFG_NF(GPP_E9, NONE, DEEP, NF1), /* USB_OC0# */ -/* USB2_OC1# */ PAD_CFG_NF(GPP_E10, NONE, DEEP, NF1), /* USB_OC1# */ -/* USB2_OC2# */ PAD_CFG_NF(GPP_E11, NONE, DEEP, NF1), /* USB_OC2# */ -/* USB2_OC3# */ PAD_NC(GPP_E12, NONE), -/* DDPB_HPD0 */ PAD_CFG_NF(GPP_E13, NONE, DEEP, NF1), /* HDMI_DP1_HPD */ -/* DDPC_HPD1 */ PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1), /* CPU_DP2_HPD */ -/* DDPD_HPD2 */ PAD_CFG_GPI(GPP_E15, NONE, DEEP), /* H1_FLASH_WP */ -/* DDPE_HPD3 */ PAD_NC(GPP_E16, NONE), /* FFS_INT2 (nostuff) */ -/* EDP_HPD */ PAD_CFG_NF(GPP_E17, NONE, DEEP, NF1), -/* DDPB_CTRLCLK */ PAD_CFG_NF(GPP_E18, NONE, DEEP, NF1), -/* DDPB_CTRLDATA */ PAD_CFG_NF(GPP_E19, NONE, DEEP, NF1), -/* DDPC_CTRLCLK */ PAD_NC(GPP_E20, NONE), -/* DDPC_CTRLDATA */ PAD_NC(GPP_E21, NONE), -/* DDPD_CTRLCLK */ PAD_NC(GPP_E22, NONE), -/* DDPD_CTRLDATA */ PAD_NC(GPP_E23, NONE), - -/* CNV_PA_BLANKING */ PAD_CFG_NF(GPP_F0, NONE, DEEP, NF1), /* CNV_COEX3 */ -/* GPP_F1 */ PAD_NC(GPP_F1, NONE), /* T406 */ -/* GPP_F2 */ PAD_NC(GPP_F2, NONE), /* T407 */ -/* GPP_F3 */ PAD_NC(GPP_F3, NONE), -/* CNV_BRI_DT */ PAD_CFG_NF(GPP_F4, NONE, DEEP, NF1), -/* CNV_BRI_RSP */ PAD_CFG_NF(GPP_F5, NONE, DEEP, NF1), -/* CNV_RGI_DT */ PAD_CFG_NF(GPP_F6, NONE, DEEP, NF1), -/* CNV_RGI_RSP */ PAD_CFG_NF(GPP_F7, NONE, DEEP, NF1), -/* CNV_MFUART2_RXD */ PAD_CFG_NF(GPP_F8, NONE, DEEP, NF1), /* CNV_COEX2 */ -/* CNV_MFUART2_TXD */ PAD_CFG_NF(GPP_F9, NONE, DEEP, NF1), /* CNV_COEX1 */ -/* GPP_F10 */ PAD_NC(GPP_F10, NONE), -/* EMMC_CMD */ PAD_NC(GPP_F11, NONE), -/* EMMC_DATA0 */ PAD_NC(GPP_F12, NONE), -/* EMMC_DATA1 */ PAD_NC(GPP_F13, NONE), -/* EMMC_DATA2 */ PAD_NC(GPP_F14, NONE), -/* EMMC_DATA3 */ PAD_NC(GPP_F15, NONE), -/* EMMC_DATA4 */ PAD_NC(GPP_F16, NONE), -/* EMMC_DATA5 */ PAD_NC(GPP_F17, NONE), -/* EMMC_DATA6 */ PAD_NC(GPP_F18, NONE), -/* EMMC_DATA7 */ PAD_NC(GPP_F19, NONE), -/* EMMC_RCLK */ PAD_NC(GPP_F20, NONE), -/* EMMC_CLK */ PAD_NC(GPP_F21, NONE), -/* EMMC_RESET# */ PAD_NC(GPP_F22, NONE), -/* A4WP_PRESENT */ PAD_NC(GPP_F23, NONE), - -/* SD_CMD */ PAD_CFG_GPI(GPP_G0, NONE, DEEP), /* CAM_MIC_CBL_DET# */ -/* SD_DATA0 */ PAD_NC(GPP_G1, NONE), -/* SD_DATA1 */ PAD_NC(GPP_G2, NONE), -/* SD_DATA2 */ PAD_NC(GPP_G3, NONE), /* T383 */ -/* SD_DATA3 */ PAD_CFG_GPI(GPP_G4, NONE, DEEP), /* CTLESS_DET# */ -/* SD_CD# */ PAD_CFG_GPO(GPP_G5, 1, DEEP), /* HOST_SD_WP# */ -/* SD_CLK */ PAD_CFG_GPO(GPP_G6, 1, DEEP), /* AUD_PWR_EN */ -/* SD_WP */ PAD_NC(GPP_G7, NONE), /* T384 */ - -/* I2S2_SCLK */ PAD_NC(GPP_H0, NONE), -/* I2S2_SFRM */ PAD_CFG_NF(GPP_H1, NONE, DEEP, NF3), /* CNV_RF_RESET# */ -/* I2S2_TXD */ PAD_CFG_NF(GPP_H2, NONE, DEEP, NF3), /* CLKREQ_CNV# */ -/* I2S2_RXD */ PAD_CFG_GPO(GPP_H3, 0, DEEP), /* CNVI_EN# */ -/* I2C2_SDA */ PAD_NC(GPP_H4, NONE), /* T388 */ -/* I2C2_SCL */ PAD_NC(GPP_H5, NONE), /* T389 */ -/* I2C3_SDA */ PAD_NC(GPP_H6, NONE), /* T378 */ -/* I2C3_SCL */ PAD_NC(GPP_H7, NONE), /* T379 */ -/* I2C4_SDA */ PAD_CFG_NF(GPP_H8, NONE, DEEP, NF1), /* I2C_SDA_H1 */ -/* I2C4_SCL */ PAD_CFG_NF(GPP_H9, NONE, DEEP, NF1), /* I2C_SCL_H1 */ -/* I2C5_SDA */ PAD_NC(GPP_H10, NONE), -/* I2C5_SCL */ PAD_NC(GPP_H11, NONE), -/* M2_SKT2_CFG2 */ PAD_NC(GPP_H14, NONE), -/* M2_SKT2_CFG3 */ PAD_CFG_GPO(GPP_H15, 1, DEEP), /* BT_RADIO_DIS# */ -/* DDPF_CTRLCLK */ PAD_NC(GPP_H16, NONE), -/* DPPF_CTRLDATA */ PAD_NC(GPP_H17, NONE), -/* CPU_C10_GATE# */ PAD_CFG_NF(GPP_H18, NONE, DEEP, NF1), /* C10_GATE# */ -/* TIMESYNC0 */ PAD_NC(GPP_H19, NONE), -/* IMGCLKOUT1 */ PAD_NC(GPP_H20, NONE), -/* GPP_H21 */ PAD_NC(GPP_H21, NONE), -/* GPP_H22 */ PAD_NC(GPP_H22, NONE), -/* GPP_H23 */ PAD_NC(GPP_H23, NONE), - -/* BATLOW# */ PAD_CFG_NF(GPD0, NONE, DEEP, NF1), /* BATLOW# */ -/* ACPRESENT */ PAD_CFG_NF(GPD1, NONE, DEEP, NF1), /* AC_PRESENT */ -/* LAN_WAKE# */ PAD_CFG_NF(GPD2, NONE, DEEP, NF1), /* LAN_WAKE# */ -/* SLP_S3# */ PAD_CFG_NF(GPD4, NONE, DEEP, NF1), /* SIO_SLP_S3# */ -/* SLP_S4# */ PAD_CFG_NF(GPD5, NONE, DEEP, NF1), /* SIO_SLP_S4# */ -/* SLP_A# */ PAD_CFG_NF(GPD6, NONE, DEEP, NF1), /* SIO_SLP_A# */ -/* GPD7 */ PAD_NC(GPD7, NONE), -/* SUSCLK */ PAD_CFG_NF(GPD8, NONE, DEEP, NF1), /* SUSCLK */ -/* SLP_WLAN# */ PAD_CFG_NF(GPD9, NONE, DEEP, NF1), /* SIO_SLP_WLAN# */ -/* SLP_S5# */ PAD_CFG_NF(GPD10, NONE, DEEP, NF1), /* SIO_SLP_S5# */ -/* LANPHYC */ PAD_CFG_NF(GPD11, NONE, DEEP, NF1), /* PM_LANPHY_EN */ -}; - -/* Early pad configuration in bootblock */ -static const struct pad_config early_gpio_table[] = { -/* M2_SKT2_CFG1 */ PAD_CFG_GPO(GPP_H13, 1, DEEP), /* M.2 SSD D3 cold */ -/* SUSWARN# */ PAD_CFG_GPO(GPP_A13, 0, DEEP), /* Card reader D3 cold */ -/* SUSACK# */ PAD_CFG_GPO(GPP_A15, 0, DEEP), /* Card reader D3 cold */ -/* UART2_RXD */ PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1), /* SERVOTX_UART */ -/* UART2_TXD */ PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1), /* SERVORX_UART */ -/* SSD RESET pin will stay low first */ -/* M2_SKT2_CFG0 */ PAD_CFG_GPO(GPP_H12, 0, DEEP), /* D3 cold RST */ -/* I2C4_SDA */ PAD_CFG_NF(GPP_H8, NONE, DEEP, NF1), /* I2C_SDA_H1 */ -/* I2C4_SCL */ PAD_CFG_NF(GPP_H9, NONE, DEEP, NF1), /* I2C_SCL_H1 */ -/* DMIC_DATA1 */ PAD_CFG_GPI_APIC(GPP_D18, NONE, PLTRST, - EDGE_SINGLE, INVERT), /* H1_PCH_INT_ODL */ -/* RESET# need to stay low before FULL_CARD_POWER_OFF assert */ -/* SPI1_IO2 */ PAD_CFG_GPO(GPP_D21, 0, DEEP), /* WWAN_BB_RST# */ -/* CPU_GP0 */ PAD_CFG_GPI(GPP_E3, NONE, DEEP), /* MEM_INTERLEAVED */ -/* SATALED# */ PAD_CFG_GPI(GPP_E8, NONE, DEEP), /* RECOVERY# */ -/* DDPD_HPD2 */ PAD_CFG_GPI(GPP_E15, NONE, DEEP), /* H1_FLASH_WP */ -/* PWRBTN# */ PAD_CFG_NF(GPD3, UP_20K, DEEP, NF1), /* SIO_PWRBTN# */ -/* M2_SKT2_CFG0 */ PAD_CFG_GPO(GPP_H12, 1, DEEP), /* D3 cold RST */ -}; - -const struct pad_config *variant_gpio_table(size_t *num) -{ - *num = ARRAY_SIZE(gpio_table); - return gpio_table; -} - -const struct pad_config *variant_early_gpio_table(size_t *num) -{ - *num = ARRAY_SIZE(early_gpio_table); - return early_gpio_table; -} - -static const struct cros_gpio cros_gpios[] = { - CROS_GPIO_REC_AL(GPP_E8, CROS_GPIO_DEVICE_NAME), - CROS_GPIO_WP_AH(GPP_E15, CROS_GPIO_DEVICE_NAME), -}; - -const struct cros_gpio *variant_cros_gpios(size_t *num) -{ - *num = ARRAY_SIZE(cros_gpios); - return cros_gpios; -} diff --git a/src/mainboard/google/drallion/variants/sarien_cml/include/variant/acpi/dptf.asl b/src/mainboard/google/drallion/variants/sarien_cml/include/variant/acpi/dptf.asl deleted file mode 100644 index 0cdbcd1400..0000000000 --- a/src/mainboard/google/drallion/variants/sarien_cml/include/variant/acpi/dptf.asl +++ /dev/null @@ -1,73 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright 2018 Google LLC - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#define DPTF_CPU_PASSIVE 99 -#define DPTF_CPU_CRITICAL 105 - -/* Skin Sensor for CPU VR temperature monitor */ -#define DPTF_TSR0_SENSOR_ID 1 -#define DPTF_TSR0_SENSOR_NAME "Skin" -#define DPTF_TSR0_PASSIVE 71 -#define DPTF_TSR0_CRITICAL 100 - -/* Memory Sensor for DDR temperature monitor */ -#define DPTF_TSR1_SENSOR_ID 2 -#define DPTF_TSR1_SENSOR_NAME "DDR" -#define DPTF_TSR1_PASSIVE 55 -#define DPTF_TSR1_CRITICAL 100 - -/* M.2 Sensor for Ambient temperature monitor */ -#define DPTF_TSR2_SENSOR_ID 3 -#define DPTF_TSR2_SENSOR_NAME "Ambient" -#define DPTF_TSR2_PASSIVE 90 -#define DPTF_TSR2_CRITICAL 100 - -#undef DPTF_ENABLE_FAN_CONTROL -#undef DPTF_ENABLE_CHARGER - -Name (DTRT, Package () { - /* CPU Throttle Effect on CPU */ - Package () { \_SB.PCI0.TCPU, \_SB.PCI0.TCPU, 250, 10, 0, 0, 0, 0 }, - - /* CPU Throttle Effect on Skin (TSR0) */ - Package () { \_SB.PCI0.TCPU, \_SB.DPTF.TSR0, 250, 10, 0, 0, 0, 0 }, - - /* CPU Throttle Effect on DDR (TSR1) */ - Package () { \_SB.PCI0.TCPU, \_SB.DPTF.TSR1, 250, 10, 0, 0, 0, 0 }, - - /* CPU Throttle Effect on Ambient (TSR2) */ - Package () { \_SB.PCI0.TCPU, \_SB.DPTF.TSR2, 250, 10, 0, 0, 0, 0 }, -}) - -Name (MPPC, Package () -{ - 0x2, /* Revision */ - Package () { /* Power Limit 1 */ - 0, /* PowerLimitIndex, 0 for Power Limit 1 */ - 5000, /* PowerLimitMinimum */ - 15000, /* PowerLimitMaximum */ - 10000, /* TimeWindowMinimum */ - 10000, /* TimeWindowMaximum */ - 100 /* StepSize */ - }, - Package () { /* Power Limit 2 */ - 1, /* PowerLimitIndex, 1 for Power Limit 2 */ - 5000, /* PowerLimitMinimum */ - 51000, /* PowerLimitMaximum */ - 28000, /* TimeWindowMinimum */ - 28000, /* TimeWindowMaximum */ - 100 /* StepSize */ - } -}) diff --git a/src/mainboard/google/drallion/variants/sarien_cml/include/variant/acpi/mainboard.asl b/src/mainboard/google/drallion/variants/sarien_cml/include/variant/acpi/mainboard.asl deleted file mode 100644 index 41121d28fe..0000000000 --- a/src/mainboard/google/drallion/variants/sarien_cml/include/variant/acpi/mainboard.asl +++ /dev/null @@ -1,44 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright 2019 Intel Corp. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#define CAM_EN GPP_B11 /* Active low */ -#define TS_PD GPP_E7 - -/* Method called from LPIT prior to enter s0ix state */ -Method (MS0X, 1) -{ - If (Arg0) { - /* Turn off camera power */ - \_SB.PCI0.STXS (CAM_EN) - } Else { - /* Turn on camera power */ - \_SB.PCI0.CTXS (CAM_EN) - } -} - -/* Method called from _PTS prior to enter sleep state */ -Method (MPTS, 1) -{ - \_SB.PCI0.LPCB.EC0.PTS (Arg0) - - /* Clear touch screen pd pin to avoid leakage */ - \_SB.PCI0.CTXS (TS_PD) -} - -/* Method called from _WAK prior to wakeup */ -Method (MWAK, 1) -{ - \_SB.PCI0.LPCB.EC0.WAK (Arg0) -} diff --git a/src/mainboard/google/drallion/variants/sarien_cml/include/variant/ec.h b/src/mainboard/google/drallion/variants/sarien_cml/include/variant/ec.h deleted file mode 100644 index 01a17b5f99..0000000000 --- a/src/mainboard/google/drallion/variants/sarien_cml/include/variant/ec.h +++ /dev/null @@ -1,34 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright 2018 Google LLC - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef VARIANT_EC_H -#define VARIANT_EC_H - -#include -#include - -/* EC wake pin */ -#define EC_WAKE_PIN GPE0_DW1_12 - -/* eSPI virtual wire reporting */ -#define EC_SCI_GPI GPE0_ESPI - -/* Enable PS/2 keyboard */ -#define SIO_EC_ENABLE_PS2K - -/* Enable DPTF */ -#define EC_ENABLE_DPTF - -#endif diff --git a/src/mainboard/google/drallion/variants/sarien_cml/include/variant/gpio.h b/src/mainboard/google/drallion/variants/sarien_cml/include/variant/gpio.h deleted file mode 100644 index f7e0403e59..0000000000 --- a/src/mainboard/google/drallion/variants/sarien_cml/include/variant/gpio.h +++ /dev/null @@ -1,34 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright 2018 Google LLC - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the - * GNU General Public License for more details. - */ - -#ifndef VARIANT_GPIO_H -#define VARIANT_GPIO_H - -#include -#include - -/* Flash Write Protect */ -#define GPIO_PCH_WP GPP_E15 - -/* Recovery mode */ -#define GPIO_REC_MODE GPP_E8 - -const struct pad_config *variant_gpio_table(size_t *num); -const struct pad_config *variant_early_gpio_table(size_t *num); - -struct cros_gpio; -const struct cros_gpio *variant_cros_gpios(size_t *num); - -#endif diff --git a/src/mainboard/google/drallion/variants/sarien_cml/include/variant/hda_verb.h b/src/mainboard/google/drallion/variants/sarien_cml/include/variant/hda_verb.h deleted file mode 100644 index 6eb6d14f6b..0000000000 --- a/src/mainboard/google/drallion/variants/sarien_cml/include/variant/hda_verb.h +++ /dev/null @@ -1,152 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright 2018 Google LLC - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef MAINBOARD_HDA_VERB_H -#define MAINBOARD_HDA_VERB_H - -#include - -const u32 cim_verb_data[] = { - /* coreboot specific header */ - 0x10ec0236, // Codec Vendor / Device ID: Realtek ALC3204 - 0xffffffff, // Subsystem ID - 0x0000001e, // Number of jacks (NID entries) - - /* Rest Codec First */ - AZALIA_RESET(0x1), - /* NID 0x01, HDA Codec Subsystem ID Verb Table */ - AZALIA_SUBVENDOR(0x0, 0x102808b8), - - /* Pin Widget Verb Table */ - AZALIA_PIN_CFG(0x0, 0x12, 0x90a60140), - AZALIA_PIN_CFG(0x0, 0x13, 0x40000000), - AZALIA_PIN_CFG(0x0, 0x14, 0x90170110), - AZALIA_PIN_CFG(0x0, 0x18, 0x411111f0), - AZALIA_PIN_CFG(0x0, 0x19, 0x04a11030), - AZALIA_PIN_CFG(0x0, 0x1a, 0x411111f0), - AZALIA_PIN_CFG(0x0, 0x1b, 0x411111f0), - AZALIA_PIN_CFG(0x0, 0x1d, 0x40700001), - AZALIA_PIN_CFG(0x0, 0x1e, 0x421212f2), - AZALIA_PIN_CFG(0x0, 0x21, 0x04211020), - - /* ALC3204 default-1 */ - 0x02050040, - 0x02049800, - 0x02050034, - 0x0204023C, - /* ALC3204 default-2 */ - 0x0205003C, - 0x02040354, - 0x0205003C, - 0x02040314, - /* ALC3204 Speaker output power - 4 ohm 2W (+12dB gain) - * + Combo Jack TRS setting */ - 0x02050038, - 0x02043901, - 0x02050045, - 0x02045089, - /* H/W AGC setting-1 */ - 0x02050016, - 0x02040C50, - 0x02050012, - 0x0204EBC2, - /* H/W AGC setting-2 */ - 0x02050013, - 0x0204401D, - 0x02050016, - 0x02044E50, - /* Zero data + EAPD to verb-control */ - 0x02050037, - 0x0204FE15, - 0x02050010, - 0x02040020, - /* Zero data */ - 0x02050030, - 0x02048000, - 0x02050030, - 0x02048000, - /* ALC3204 default-3 */ - 0x05750003, - 0x05740DA3, - 0x02050046, - 0x02040004, - /* ALC3204 default-4 */ - 0x0205001B, - 0x02040A4B, - 0x02050008, - 0x02046A6C, - /* JD1 */ - 0x02050009, - 0x0204E003, - 0x0205000A, - 0x02047770, - /* Microphone + Array MIC security Disable +ADC clock Enable */ - 0x0205000D, - 0x0204A020, - 0x02050005, - 0x02040700, - /* Speaker Enable */ - 0x0205000C, - 0x020401EF, - 0x0205000C, - 0x020401EF, - /* EQ Bypass + EQ HPF cutoff 250Hz */ - 0x05350000, - 0x0534201A, - 0x0535001d, - 0x05340800, - /* EQ-2 */ - 0x0535001e, - 0x05340800, - 0x05350003, - 0x05341EF8, - /* EQ-3 */ - 0x05350004, - 0x05340000, - 0x05450000, - 0x05442000, - /* EQ-4 */ - 0x0545001d, - 0x05440800, - 0x0545001e, - 0x05440800, - /* EQ-5 */ - 0x05450003, - 0x05441EF8, - 0x05450004, - 0x05440000, - /* EQ Update */ - 0x05350000, - 0x0534E01A, - 0x05350000, - 0x0534E01A, -}; - -const u32 pc_beep_verbs[] = { -/* PCBeep pass through to NID14 for ePSA test-1 */ - 0x02050036, - 0x02047717, - 0x02050036, - 0x02047717, -/* PCBeep pass through to NID14 for ePSA test-2 */ - 0x01470740, - 0x0143B000, - 0x01470C02, - 0x01470C02, -}; - -AZALIA_ARRAY_SIZES; - -#endif diff --git a/src/mainboard/google/drallion/variants/sarien_cml/include/variant/variant.h b/src/mainboard/google/drallion/variants/sarien_cml/include/variant/variant.h deleted file mode 100644 index bbb3e9e68d..0000000000 --- a/src/mainboard/google/drallion/variants/sarien_cml/include/variant/variant.h +++ /dev/null @@ -1,25 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright 2018 Google LLC - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef VARIANT_H -#define VARIANT_H - -/* Sarien is SKU ID 1 and 3 */ -#define VARIANT_SKU_ID 1 -#define VARIANT_SKU_NAME "sku1" -#define VARIANT_SKU_ID_SIGNED_EC 3 -#define VARIANT_SKU_NAME_SIGNED_EC "sku3" - -#endif diff --git a/src/mainboard/google/drallion/variants/sarien_cml/sku.c b/src/mainboard/google/drallion/variants/sarien_cml/sku.c deleted file mode 100644 index d0b48f0572..0000000000 --- a/src/mainboard/google/drallion/variants/sarien_cml/sku.c +++ /dev/null @@ -1,35 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright 2018 Google LLC - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include -#include - -uint32_t sku_id(void) -{ - if (wilco_ec_signed_fw()) - return VARIANT_SKU_ID_SIGNED_EC; - else - return VARIANT_SKU_ID; -} - -const char *smbios_system_sku(void) -{ - if (wilco_ec_signed_fw()) - return VARIANT_SKU_NAME_SIGNED_EC; - else - return VARIANT_SKU_NAME; -} From 8d9262a7e7c0b9ec8a48aee9792cef2bd15667d2 Mon Sep 17 00:00:00 2001 From: Maulik V Vaghela Date: Tue, 3 Dec 2019 16:12:13 +0530 Subject: [PATCH 0686/1242] soc/intel/tigerlake: Pick correct pmc base reg from pch type Update PMC shadow register base address for Jasperlake Correct PCH detection logic based on PCH ids and return correct base address based on PCH detected since our code supports both tgl and jsl. Change-Id: Iea3311b3dc8dc3ee5ea54db1148f386c2a5dd563 Signed-off-by: Maulik V Vaghela Reviewed-on: https://review.coreboot.org/c/coreboot/+/37670 Tested-by: build bot (Jenkins) Reviewed-by: Aamir Bohra --- src/soc/intel/tigerlake/bootblock/pch.c | 34 +++++++++++++++++------ src/soc/intel/tigerlake/espi.c | 8 +++--- src/soc/intel/tigerlake/include/soc/pch.h | 4 +-- 3 files changed, 31 insertions(+), 15 deletions(-) diff --git a/src/soc/intel/tigerlake/bootblock/pch.c b/src/soc/intel/tigerlake/bootblock/pch.c index 1ef4928fa6..8599423f91 100644 --- a/src/soc/intel/tigerlake/bootblock/pch.c +++ b/src/soc/intel/tigerlake/bootblock/pch.c @@ -37,7 +37,8 @@ #include #include -#define PCR_PSF3_TO_SHDW_PMC_REG_BASE 0x0600 +#define PCR_PSF3_TO_SHDW_PMC_REG_BASE_TGP 0x0600 +#define PCR_PSF3_TO_SHDW_PMC_REG_BASE_JSP 0x0980 #define PCR_PSFX_TO_SHDW_BAR0 0 #define PCR_PSFX_TO_SHDW_BAR1 0x4 #define PCR_PSFX_TO_SHDW_BAR2 0x8 @@ -57,6 +58,20 @@ #define PCR_DMI_LPCIOD 0x2770 #define PCR_DMI_LPCIOE 0x2774 +static uint32_t get_pmc_reg_base(void) +{ + uint8_t pch_series; + + pch_series = get_pch_series(); + + if (pch_series == PCH_TGP) + return PCR_PSF3_TO_SHDW_PMC_REG_BASE_TGP; + else if (pch_series == PCH_JSP) + return PCR_PSF3_TO_SHDW_PMC_REG_BASE_JSP; + else + return 0; +} + static void soc_config_pwrmbase(void) { uint32_t reg32; @@ -99,22 +114,23 @@ void bootblock_pch_early_init(void) static void soc_config_acpibase(void) { uint32_t pmc_reg_value; + uint32_t pmc_base_reg; - pmc_reg_value = pcr_read32(PID_PSF3, PCR_PSF3_TO_SHDW_PMC_REG_BASE + - PCR_PSFX_TO_SHDW_BAR4); + pmc_base_reg = get_pmc_reg_base(); + if (!pmc_base_reg) + die_with_post_code(POST_HW_INIT_FAILURE, "Invalid PMC base address\n"); + + pmc_reg_value = pcr_read32(PID_PSF3, pmc_base_reg + PCR_PSFX_TO_SHDW_BAR4); if (pmc_reg_value != 0xffffffff) { /* Disable Io Space before changing the address */ - pcr_rmw32(PID_PSF3, PCR_PSF3_TO_SHDW_PMC_REG_BASE + - PCR_PSFX_T0_SHDW_PCIEN, + pcr_rmw32(PID_PSF3, pmc_base_reg + PCR_PSFX_T0_SHDW_PCIEN, ~PCR_PSFX_TO_SHDW_PCIEN_IOEN, 0); /* Program ABASE in PSF3 PMC space BAR4*/ - pcr_write32(PID_PSF3, PCR_PSF3_TO_SHDW_PMC_REG_BASE + - PCR_PSFX_TO_SHDW_BAR4, + pcr_write32(PID_PSF3, pmc_base_reg + PCR_PSFX_TO_SHDW_BAR4, ACPI_BASE_ADDRESS); /* Enable IO Space */ - pcr_rmw32(PID_PSF3, PCR_PSF3_TO_SHDW_PMC_REG_BASE + - PCR_PSFX_T0_SHDW_PCIEN, + pcr_rmw32(PID_PSF3, pmc_base_reg + PCR_PSFX_T0_SHDW_PCIEN, ~0, PCR_PSFX_TO_SHDW_PCIEN_IOEN); } } diff --git a/src/soc/intel/tigerlake/espi.c b/src/soc/intel/tigerlake/espi.c index 932f76089d..d07a582a32 100644 --- a/src/soc/intel/tigerlake/espi.c +++ b/src/soc/intel/tigerlake/espi.c @@ -81,10 +81,10 @@ uint8_t get_pch_series(void) */ lpc_did_hi_byte = pci_read_config8(PCH_DEV_ESPI, PCI_DEVICE_ID + 1); - if (lpc_did_hi_byte == 0x9D) - return PCH_LP; - else if (lpc_did_hi_byte == 0xA3) - return PCH_H; + if (lpc_did_hi_byte == 0xA0) + return PCH_TGP; + else if (lpc_did_hi_byte == 0x38) + return PCH_JSP; else return PCH_UNKNOWN_SERIES; } diff --git a/src/soc/intel/tigerlake/include/soc/pch.h b/src/soc/intel/tigerlake/include/soc/pch.h index 57ddeaf97f..ae8e310afb 100644 --- a/src/soc/intel/tigerlake/include/soc/pch.h +++ b/src/soc/intel/tigerlake/include/soc/pch.h @@ -18,8 +18,8 @@ #include -#define PCH_H 1 -#define PCH_LP 2 +#define PCH_TGP 1 +#define PCH_JSP 2 #define PCH_UNKNOWN_SERIES 0xFF #define PCIE_CLK_NOTUSED 0xFF From 40bb6c340f4d1d2440f624d8bb68157d10304b3f Mon Sep 17 00:00:00 2001 From: Wim Vervoorn Date: Mon, 9 Dec 2019 14:05:21 +0100 Subject: [PATCH 0687/1242] mb/facebook/monolith/gpio.h: Update GPIO configuration Update signal names and GPIO configuration. Remove unused GPE_EC_WAKE and EC_XXX_GPI defines. BUG=N/A TEST=tested on facebook monolith Change-Id: Iae5edb8418894a669ed49c2d78672d8957010f3c Signed-off-by: Wim Vervoorn Reviewed-on: https://review.coreboot.org/c/coreboot/+/37671 Tested-by: build bot (Jenkins) Reviewed-by: Frans Hendriks --- src/mainboard/facebook/monolith/gpio.h | 297 ++++++++++++------------- 1 file changed, 142 insertions(+), 155 deletions(-) diff --git a/src/mainboard/facebook/monolith/gpio.h b/src/mainboard/facebook/monolith/gpio.h index 65300fff6c..4dae94bca5 100644 --- a/src/mainboard/facebook/monolith/gpio.h +++ b/src/mainboard/facebook/monolith/gpio.h @@ -21,154 +21,141 @@ #include #include -/* EC wake is LAN_WAKE# which is a special DeepSX wake pin */ -#define GPE_EC_WAKE GPE0_LAN_WAK - -/* GPP_E16 is EC_SCI_L. GPP_E group is routed to DW2 in the GPE0 block */ -#define EC_SCI_GPI GPE0_DW2_16 -#define EC_SMI_GPI GPP_E15 - #ifndef __ACPI__ /* Pad configuration in ramstage. */ static const struct pad_config gpio_table[] = { -/* PCH_RCIN */ PAD_CFG_NF(GPP_A0, NONE, DEEP, NF1), -/* LPC_LAD_0 */ PAD_CFG_NF(GPP_A1, 20K_PD, DEEP, NF1), -/* LPC_LAD_1 */ PAD_CFG_NF(GPP_A2, 20K_PD, DEEP, NF1), -/* LPC_LAD_2 */ PAD_CFG_NF(GPP_A3, 20K_PD, DEEP, NF1), -/* LPC_LAD_3 */ PAD_CFG_NF(GPP_A4, 20K_PD, DEEP, NF1), -/* LPC_FRAME */ PAD_CFG_NF(GPP_A5, NONE, DEEP, NF1), -/* LPC_SERIRQ */ PAD_CFG_NF(GPP_A6, NONE, DEEP, NF1), -/* PM_SLP_S0ix_N */ PAD_CFG_GPI_GPIO_DRIVER(GPP_A7, 20K_PU, DEEP), -///* PIRQA# */ PAD_CFG_NF(GPP_A7, NONE, DEEP, NF1), -/* LPC_CLKRUN */ PAD_CFG_NF(GPP_A8, NONE, DEEP, NF1), -/* LPC_CLK */ PAD_CFG_NF(GPP_A9, 20K_PD, DEEP, NF1), -/* PCH_LPC_CLK */ PAD_CFG_NF(GPP_A10, 20K_PD, DEEP, NF1), +/* PCH_RCIN# */ PAD_CFG_NF(GPP_A0, NONE, DEEP, NF1), +/* LAD_0 */ PAD_CFG_NF(GPP_A1, 20K_PD, DEEP, NF1), +/* LAD_1 */ PAD_CFG_NF(GPP_A2, 20K_PD, DEEP, NF1), +/* LAD_2 */ PAD_CFG_NF(GPP_A3, 20K_PD, DEEP, NF1), +/* LAD_3 */ PAD_CFG_NF(GPP_A4, 20K_PD, DEEP, NF1), +/* LFRAME# */ PAD_CFG_NF(GPP_A5, NONE, DEEP, NF1), +/* PCH_SERIRQ */ PAD_CFG_NF(GPP_A6, NONE, DEEP, NF1), +/* PIRQA# */ PAD_CFG_GPO(GPP_A7, 1, DEEP), +/* PM_CLKRUN_N */ PAD_CFG_NF(GPP_A8, NONE, DEEP, NF1), +/* CLK_LPC_EC */ PAD_CFG_NF(GPP_A9, 20K_PD, DEEP, NF1), +/* CLKOUT_LPC_CN */ PAD_CFG_NF(GPP_A10, 20K_PD, DEEP, NF1), /* SLEEP */ PAD_CFG_NC(GPP_A11), /* available on the module not used here */ -/* ISH_KB_PROX_INT */ PAD_CFG_NC(GPP_A12), -/* PCH_SUSPWRACB */ PAD_CFG_NF(GPP_A13, NONE, DEEP, NF1), +/* NC */ PAD_CFG_NC(GPP_A12), +/* PCH_SYSWARN */ PAD_CFG_NF(GPP_A13, NONE, DEEP, NF1), /* PM_SUS_STAT */ PAD_CFG_NF(GPP_A14, NONE, DEEP, NF1), -/* SUSACK_R_N */ PAD_CFG_NF(GPP_A15, 20K_PD, DEEP, NF1), +/* KBC_SUSACK */ PAD_CFG_NF(GPP_A15, 20K_PD, DEEP, NF1), /* SD_1P8_SEL */ PAD_CFG_NF(GPP_A16, NONE, DEEP, NF1), /* SD_PWR_EN */ PAD_CFG_NF(GPP_A17, NONE, DEEP, NF1), -/* ISH_GP0 */ PAD_CFG_NC(GPP_A18), -/* ISH_GP1 */ PAD_CFG_NC(GPP_A19), -/* ISH_GP2 */ PAD_CFG_NC(GPP_A20), -/* ISH_GP3 */ PAD_CFG_NC(GPP_A21), -/* ISH_GP4 */ PAD_CFG_NC(GPP_A22), -/* ISH_GP5 */ PAD_CFG_NC(GPP_A23), -/* V0.85A_VID0 */ PAD_CFG_NF(GPP_B0, NONE, DEEP, NF1), -/* V0.85A_VID1 */ PAD_CFG_NF(GPP_B1, NONE, DEEP, NF1), -/* GP_VRALERTB */ PAD_CFG_NF(GPP_B2, NONE, DEEP, NF1), -/* CPU_GP2 */ PAD_CFG_NC(GPP_B3), -/* CPU_GP2 */ PAD_CFG_NC(GPP_B4), -/* CLK_REQ_SLOT0 */ PAD_CFG_NC(GPP_B5), -/* CLK_REQ_SLOT1 */ PAD_CFG_NC(GPP_B6), -/* CLK_REQ_SLOT2 */ PAD_CFG_NC(GPP_B7), -/* CLK_REQ_SLOT3 */ PAD_CFG_NC(GPP_B8), -/* CLK_REQ_SLOT4 */ PAD_CFG_NC(GPP_B9), -/* CLK_REQ_SLOT5 */ PAD_CFG_NC(GPP_B10), -/* MPHY_EXT_PWR_GATE */ PAD_CFG_NF(GPP_B11, NONE, DEEP, NF1), -/* PM_SLP_S0 */ PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1), -/* PCH_PLT_RST */ PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1), -/* PCH_SPKR */ PAD_CFG_NF(GPP_B14, NONE, DEEP, NF1), -/* GSPI0_CS# */ /* GPP_B15 */ -/* GSPI0_CLK */ PAD_CFG_NC(GPP_B16), -/* GSPI0_MISO */ PAD_CFG_NC(GPP_B17), +/* NC */ PAD_CFG_NC(GPP_A18), +/* NC */ PAD_CFG_NC(GPP_A19), +/* NC */ PAD_CFG_NC(GPP_A20), +/* NC */ PAD_CFG_NC(GPP_A21), +/* NC */ PAD_CFG_NC(GPP_A22), +/* NC */ PAD_CFG_NC(GPP_A23), +/* CORE_VID0 */ PAD_CFG_NC(GPP_B0), +/* CORE_VID1 */ PAD_CFG_NC(GPP_B1), +/* VRALERT# */ PAD_CFG_NF(GPP_B2, NONE, DEEP, NF1), +/* NC */ PAD_CFG_NC(GPP_B3), +/* NC */ PAD_CFG_NC(GPP_B4), +/* SRCCLKREQ0 */ PAD_CFG_NC(GPP_B5), +/* SRCCLKREQ1 */ PAD_CFG_NC(GPP_B6), +/* SRCCLKREQ2 */ PAD_CFG_NC(GPP_B7), +/* SRCCLKREQ3 */ PAD_CFG_NC(GPP_B8), +/* SRCCLKREQ4 */ PAD_CFG_NC(GPP_B9), +/* SRCCLKREQ5 */ PAD_CFG_NC(GPP_B10), +/* EXT_PWR_GATE */ PAD_CFG_NF(GPP_B11, NONE, DEEP, NF1), +/* SLP_S0 */ PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1), +/* PCH_PLTRST */ PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1), +/* PCH_SPKR */ PAD_CFG_NF(GPP_B14, NONE, DEEP, NF1), +/* NC */ PAD_CFG_NC(GPP_B15), +/* NC */ PAD_CFG_NC(GPP_B16), +/* NC */ PAD_CFG_NC(GPP_B17), /* GSPI0_MOSI */ PAD_CFG_NC(GPP_B18), -/* GSPI1_CS */ PAD_CFG_NF(GPP_B19, NONE, DEEP, NF1), -/* GSPI1_CLK */ PAD_CFG_NF(GPP_B20, 20K_PD, DEEP, NF1), -/* GSPI1_MISO */ PAD_CFG_NF(GPP_B21, 20K_PD, DEEP, NF1), -/* GSPI1_MOSI */ PAD_CFG_NF(GPP_B22, 20K_PD, DEEP, NF1), -///* CB_OVT# */ PAD_CFG_NF(GPP_B23, NONE, DEEP, NF1), -/* SML1ALERT# */ PAD_CFG_GPI_APIC(GPP_B23, 20K_PD, PLTRST), -/* SMB_CLK */ PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1), -/* SMB_DATA */ PAD_CFG_NF(GPP_C1, 20K_PD, DEEP, NF1), +/* NC */ PAD_CFG_NC(GPP_B19), +/* NC */ PAD_CFG_NC(GPP_B20), +/* NC */ PAD_CFG_NC(GPP_B21), +/* BIOS_SEL */ PAD_CFG_NC(GPP_B22), +/* CB_OVT# */ PAD_CFG_GPO(GPP_B23, 1, DEEP), + +/* SMB_SCL */ PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1), +/* SMB_SDA */ PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1), /* SMBALERT# */ PAD_CFG_GPO(GPP_C2, 1, DEEP), /* SML0_CLK */ PAD_CFG_NF(GPP_C3, NONE, DEEP, NF1), -/* SML0DATA */ PAD_CFG_NF(GPP_C4, NONE, DEEP, NF1), -///* SML0ALERT# */ PAD_CFG_GPI_APIC(GPP_C5, 20K_PD, PLTRST), -/* SML0ALERT# */ PAD_CFG_NC(GPP_C5), -/* SML1_CLK */ PAD_CFG_NF(GPP_C6, NONE, DEEP, NF1), -/* SML1_DATA */ PAD_CFG_NF(GPP_C7, 20K_PD, DEEP, NF1), -/* UART0_RXD */ PAD_CFG_NF(GPP_C8, NONE, DEEP, NF1), -/* UART0_TXD */ PAD_CFG_NF(GPP_C9, NONE, DEEP, NF1), -/* UART0_RTS */ PAD_CFG_NF(GPP_C10, NONE, DEEP, NF1), -/* UART0_CTS */ PAD_CFG_NF(GPP_C11, NONE, DEEP, NF1), -/* UART1_RXD */ PAD_CFG_NC(GPP_C12), -/* UART1_TXD */ PAD_CFG_NC(GPP_C13), -/* UART1_RTS */ PAD_CFG_NC(GPP_C14), -/* UART1_CTS */ PAD_CFG_NC(GPP_C15), -/* I2C0_SDA */ PAD_CFG_NF(GPP_C16, 5K_PU, DEEP, NF1), -/* I2C0_SCL */ PAD_CFG_NF(GPP_C17, 5K_PU, DEEP, NF1), -/* I2C1_SDA */ PAD_CFG_NC(GPP_C18), -/* I2C1_SCL */ PAD_CFG_NC(GPP_C19), -/* UART2_RXD */ PAD_CFG_NC(GPP_C20), -/* UART2_TXD */ PAD_CFG_NC(GPP_C21), -///* EC_SMI */ PAD_CFG_GPI_ACPI_SMI(GPP_E15, NONE, DEEP, YES), -///* EC_SCI */ PAD_CFG_GPI_ACPI_SCI(GPP_E16, NONE, DEEP, YES), -/* EC_SCI# not used */ PAD_CFG_NC(GPP_C22), -/* EC_SMI# not used */ PAD_CFG_NC(GPP_C23), -/* SPI1_CS */ PAD_CFG_NF(GPP_D0, NONE, DEEP, NF1), -/* SPI1_CLK */ PAD_CFG_NF(GPP_D1, NONE, DEEP, NF1), -/* SPI1_MISO */ PAD_CFG_NF(GPP_D2, NONE, DEEP, NF1), -/* SPI1_MOSI */ PAD_CFG_NF(GPP_D3, NONE, DEEP, NF1), -/* CAM_FLASH_STROBE */ PAD_CFG_NF(GPP_D4, NONE, DEEP, NF1), -/* ISH_I2C0_SDA */ PAD_CFG_NF(GPP_D5, NONE, DEEP, NF1), -/* ISH_I2C0_SCL */ PAD_CFG_NF(GPP_D6, NONE, DEEP, NF1), -/* ISH_I2C1_SDA */ PAD_CFG_NF(GPP_D7, NONE, DEEP, NF1), -/* ISH_I2C1_SCL */ PAD_CFG_NF(GPP_D8, NONE, DEEP, NF1), -/* GPP_D9 */ PAD_CFG_NC(GPP_D9), -/* GPP_D10 */ PAD_CFG_NC(GPP_D10), -/* GPP_D11 */ PAD_CFG_NC(GPP_D11), -/* GPP_D12 */ PAD_CFG_NC(GPP_D12), -/* ISH_UART0_RXD */ PAD_CFG_NC(GPP_D13), -/* ISH_UART0_TXD */ PAD_CFG_NC(GPP_D14), -/* ISH_UART0_RTS */ PAD_CFG_NC(GPP_D15), -/* ISH_UART0_CTS */ PAD_CFG_NC(GPP_D16), -/* DMIC_CLK_1 */ PAD_CFG_NC(GPP_D17), -/* DMIC_DATA_1 */ PAD_CFG_NC(GPP_D18), -/* DMIC_CLK_0 */ PAD_CFG_NC(GPP_D19), -/* DMIC_DATA_0 */ PAD_CFG_NC(GPP_D20), -/* SPI1_D2 */ PAD_CFG_NF(GPP_D21, NONE, DEEP, NF1), -/* SPI1_D3 */ PAD_CFG_NF(GPP_D22, NONE, DEEP, NF1), -/* I2S_MCLK */ PAD_CFG_NC(GPP_D23), -///* SPI_TPM_IRQ */ PAD_CFG_GPI_APIC(GPP_E0, NONE, PLTRST), -/* GPP_E0 */ PAD_CFG_NC(GPP_E0), -/* GPP_E1 */ PAD_CFG_NC(GPP_E1), -/* GPP_E2 */ PAD_CFG_NC(GPP_E2), -/* GPP_E3 */ PAD_CFG_NC(GPP_E3), -/* SATA_DEVSLP0 */ PAD_CFG_NF(GPP_E4, NONE, DEEP, NF1), -/* SATA_DEVSLP1 */ PAD_CFG_NF(GPP_E5, NONE, DEEP, NF1), -/* SATA_DEVSLP2 */ PAD_CFG_NF(GPP_E6, NONE, DEEP, NF1), -/* GPP_E7 */ PAD_CFG_NC(GPP_E7), -/* SATALED# */ PAD_CFG_NF(GPP_E8, NONE, DEEP, NF1), -/* USB2_OC_0 */ PAD_CFG_NF(GPP_E9, NONE, DEEP, NF1), -/* USB2_OC_1 */ PAD_CFG_NF(GPP_E10, NONE, DEEP, NF1), -/* USB2_OC_2 */ PAD_CFG_NF(GPP_E11, NONE, DEEP, NF1), -/* USB2_OC_3 */ PAD_CFG_GPI_APIC(GPP_E12, NONE, PLTRST), -/* DDI1_HPD */ PAD_CFG_NF(GPP_E13, NONE, DEEP, NF1), -/* DDI2_HPD */ PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1), -/* DDI3_HPD */ PAD_CFG_NF(GPP_E15, NONE, DEEP, NF1), -/* DDI4_HPD */ PAD_CFG_NF(GPP_E16, NONE, DEEP, NF1), -/* EDP_HPD */ PAD_CFG_NF(GPP_E17, NONE, DEEP, NF1), +/* SML0_SDA */ PAD_CFG_NF(GPP_C4, NONE, DEEP, NF1), +/* SML0_ALERT */ PAD_CFG_NC(GPP_C5), +/* GPP_C6 - RESERVED */ +/* GPP_C7 - RESERVED */ +/* CPU_UART0_RXD */ PAD_CFG_NF(GPP_C8, NONE, DEEP, NF1), +/* CPU_UART0_TXD */ PAD_CFG_NF(GPP_C9, NONE, DEEP, NF1), +/* CPU_UART0_RTS */ PAD_CFG_NF(GPP_C10, NONE, DEEP, NF1), +/* CPU_UART0_CTS */ PAD_CFG_NF(GPP_C11, NONE, DEEP, NF1), +/* NC */ PAD_CFG_NC(GPP_C12), +/* NC */ PAD_CFG_NC(GPP_C13), +/* NC */ PAD_CFG_NC(GPP_C14), +/* NC */ PAD_CFG_NC(GPP_C15), +/* I2C0_SDA */ PAD_CFG_NF(GPP_C16, NONE, DEEP, NF1), +/* I2C0_SCL */ PAD_CFG_NF(GPP_C17, NONE, DEEP, NF1), +/* NC */ PAD_CFG_NC(GPP_C18), +/* NC */ PAD_CFG_NC(GPP_C19), +/* NC */ PAD_CFG_NC(GPP_C20), +/* NC */ PAD_CFG_NC(GPP_C21), +/* EC_SCI# NOT USED */ PAD_CFG_NC(GPP_C22), +/* EC_SMI# NOT USED */ PAD_CFG_NC(GPP_C23), +/* TOUCH_SPI1_CS */ PAD_CFG_NC(GPP_D0), +/* TPM_PIRQ_N NOT USED */ PAD_CFG_NC(GPP_D1), +/* NC */ PAD_CFG_NC(GPP_D2), +/* NC */ PAD_CFG_NC(GPP_D3), +/* NC */ PAD_CFG_NC(GPP_D4), +/* NC */ PAD_CFG_NC(GPP_D5), +/* NC */ PAD_CFG_NC(GPP_D6), +/* NC */ PAD_CFG_NC(GPP_D7), +/* NC */ PAD_CFG_NC(GPP_D8), +/* NC */ PAD_CFG_NC(GPP_D9), +/* NC */ PAD_CFG_NC(GPP_D11), +/* NC */ PAD_CFG_NC(GPP_D12), +/* NC */ PAD_CFG_NC(GPP_D13), +/* NC */ PAD_CFG_NC(GPP_D14), +/* NC */ PAD_CFG_NC(GPP_D15), +/* NC */ PAD_CFG_NC(GPP_D16), +/* NC */ PAD_CFG_NC(GPP_D17), +/* NC */ PAD_CFG_NC(GPP_D18), +/* NC */ PAD_CFG_NC(GPP_D19), +/* NC */ PAD_CFG_NC(GPP_D20), +/* LID# NOT USED */ PAD_CFG_NC(GPP_D21), +/* NC */ PAD_CFG_NC(GPP_D22), +/* NC */ PAD_CFG_NC(GPP_D23), +/* NC */ PAD_CFG_NC(GPP_E0), +/* NC */ PAD_CFG_NC(GPP_E1), +/* NC */ PAD_CFG_NC(GPP_E2), +/* NC */ PAD_CFG_NC(GPP_E3), +/* DEVSLP0 TP */ PAD_CFG_NC(GPP_E4), +/* DEVSLP0 TP */ PAD_CFG_NC(GPP_E5), +/* DEVSLP1 TP */ PAD_CFG_NC(GPP_E6), +/* NC */ PAD_CFG_NC(GPP_E7), +/* SATA_LED_N */ PAD_CFG_NF(GPP_E8, NONE, DEEP, NF1), +/* USB2_OC0_1 */ PAD_CFG_NF(GPP_E9, NONE, DEEP, NF1), +/* USB2_OC2_3 */ PAD_CFG_NF(GPP_E10, NONE, DEEP, NF1), +/* USB2_OC4_5 */ PAD_CFG_NF(GPP_E11, NONE, DEEP, NF1), +/* USB2_OC6_7 */ PAD_CFG_NF(GPP_E11, NONE, DEEP, NF1), +/* DDPB_HPD0_C */ PAD_CFG_NF(GPP_E13, NONE, DEEP, NF1), +/* DDPC_HPD1_C */ PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1), +/* DDPD_HPD2_C NC */ PAD_CFG_NC(GPP_E15), +/* DDPE_HPD3_C NC */ PAD_CFG_NC(GPP_E16), +/* EDP_HPD_C */ PAD_CFG_NF(GPP_E17, NONE, DEEP, NF1), /* DDPB_CTRLCLK */ PAD_CFG_NF(GPP_E18, NONE, DEEP, NF1), -/* DDPB_CTRLDATA */ PAD_CFG_NF(GPP_E19, 20K_PD, DEEP, NF1), -/* DDPC_CTRLCLK */ PAD_CFG_NF(GPP_E20, NONE, DEEP, NF1), -/* DDPC_CTRLDATA */ PAD_CFG_NF(GPP_E21, 20K_PD, DEEP, NF1), -/* DDPD_CTRLCLK */ PAD_CFG_NF(GPP_E22, NONE, DEEP, NF1), -/* DDPD_CTRLDATA */ PAD_CFG_NF(GPP_E23, 20K_PD, DEEP, NF1), -/* I2S2_SCLK */ PAD_CFG_NC(GPP_F0), -/* I2S2_SFRM */ PAD_CFG_NC(GPP_F1), -/* I2S2_TXD */ PAD_CFG_NC(GPP_F2), -/* I2S2_RXD */ PAD_CFG_NC(GPP_F3), -/* I2C2_SDA */ PAD_CFG_NC(GPP_F4), -/* I2C2_SCL */ PAD_CFG_NC(GPP_F5), -/* I2C3_SDA */ PAD_CFG_NC(GPP_F6), -/* I2C3_SCL */ PAD_CFG_NC(GPP_F7), -/* I2C4_SDA */ PAD_CFG_NC(GPP_F8), -/* I2C4_SDA */ PAD_CFG_NC(GPP_F9), -/* ISH_I2C2_SDA */ PAD_CFG_NC(GPP_F10), -/* ISH_I2C2_SCL */ PAD_CFG_NC(GPP_F11), +/* DDPB_CTRLDAT */ PAD_CFG_NF(GPP_E19, 20K_PD, DEEP, NF1), +/* DDI2_DDC_SCL_L */ PAD_CFG_NF(GPP_E20, NONE, DEEP, NF1), +/* DDI2_DDC_SDA_L */ PAD_CFG_NF(GPP_E21, 20K_PD, DEEP, NF1), +/* DDPD_CTRLCLK NC */ PAD_CFG_NC(GPP_E22), +/* DDPD_CTRLDAT NC */ PAD_CFG_NC(GPP_E23), +/* NC */ PAD_CFG_NC(GPP_F0), +/* NC */ PAD_CFG_NC(GPP_F1), +/* NC */ PAD_CFG_NC(GPP_F2), +/* NC */ PAD_CFG_NC(GPP_F3), +/* NC */ PAD_CFG_NC(GPP_F4), +/* NC */ PAD_CFG_NC(GPP_F5), +/* NC */ PAD_CFG_NC(GPP_F6), +/* NC */ PAD_CFG_NC(GPP_F7), +/* NC */ PAD_CFG_NC(GPP_F8), +/* NC */ PAD_CFG_NC(GPP_F9), +/* NC */ PAD_CFG_NC(GPP_F10), +/* NC */ PAD_CFG_NC(GPP_F11), /* EMMC_CMD */ PAD_CFG_NF(GPP_F12, NONE, DEEP, NF1), /* EMMC_DATA0 */ PAD_CFG_NF(GPP_F13, NONE, DEEP, NF1), /* EMMC_DATA1 */ PAD_CFG_NF(GPP_F14, NONE, DEEP, NF1), @@ -178,29 +165,29 @@ static const struct pad_config gpio_table[] = { /* EMMC_DATA5 */ PAD_CFG_NF(GPP_F18, NONE, DEEP, NF1), /* EMMC_DATA6 */ PAD_CFG_NF(GPP_F19, NONE, DEEP, NF1), /* EMMC_DATA7 */ PAD_CFG_NF(GPP_F20, NONE, DEEP, NF1), -/* EMMC_RCLK */ PAD_CFG_NF(GPP_F21, NONE, DEEP, NF1), +/* EMMC_STROBE */ PAD_CFG_NF(GPP_F21, NONE, DEEP, NF1), /* EMMC_CLK */ PAD_CFG_NF(GPP_F22, NONE, DEEP, NF1), -/* GPP_F23 */ PAD_CFG_NC(GPP_F23), +/* GPP_F23 */ PAD_CFG_NC(GPP_F23), /* SD_CMD */ PAD_CFG_NF(GPP_G0, NONE, DEEP, NF1), -/* SD_DATA0 */ PAD_CFG_NF(GPP_G1, NONE, DEEP, NF1), -/* SD_DATA1 */ PAD_CFG_NF(GPP_G2, NONE, DEEP, NF1), -/* SD_DATA2 */ PAD_CFG_NF(GPP_G3, NONE, DEEP, NF1), -/* SD_DATA3 */ PAD_CFG_NF(GPP_G4, NONE, DEEP, NF1), +/* SD_D0 */ PAD_CFG_NF(GPP_G1, NONE, DEEP, NF1), +/* SD_D1 */ PAD_CFG_NF(GPP_G2, NONE, DEEP, NF1), +/* SD_D2 */ PAD_CFG_NF(GPP_G3, NONE, DEEP, NF1), +/* SD_D3 */ PAD_CFG_NF(GPP_G4, NONE, DEEP, NF1), /* SD_CD# */ PAD_CFG_NF(GPP_G5, NONE, DEEP, NF1), /* SD_CLK */ PAD_CFG_NF(GPP_G6, NONE, DEEP, NF1), -/* SD_WP */ PAD_CFG_NF(GPP_G7, NONE, DEEP, NF1), +/* SD_WP */ PAD_CFG_NF(GPP_G7, NONE, DEEP, NF1), /* PCH_BATLOW */ PAD_CFG_NF(GPD0, NONE, DEEP, NF1), -/* AC_PRESENT */ PAD_CFG_NF(GPD1, NONE, DEEP, NF1), -/* PCH_WAKE */ PAD_CFG_NF(GPD2, NONE, DEEP, NF1), -/* PCH_PWRBTN */ PAD_CFG_NF(GPD3, NONE, DEEP, NF1), -/* PM_SLP_S3# */ PAD_CFG_NF(GPD4, NONE, DEEP, NF1), -/* PM_SLP_S4# */ PAD_CFG_NF(GPD5, NONE, DEEP, NF1), -/* PM_SLP_SA# */ PAD_CFG_NF(GPD6, NONE, DEEP, NF1), -/* GPD7 */ PAD_CFG_NC(GPD7), -/* PM_SUSCLK */ PAD_CFG_NF(GPD8, NONE, DEEP, NF1), -/* PCH_SLP_WLAN# */ PAD_CFG_NF(GPD9, NONE, DEEP, NF1), -/* PM_SLP_S5# */ PAD_CFG_NF(GPD10, NONE, DEEP, NF1), -/* LANPHYC */ PAD_CFG_NF(GPD11, NONE, DEEP, NF1), +/* KBC_ACPRESENT */ PAD_CFG_NF(GPD1, NONE, DEEP, NF1), +/* PCH_LAN_WAKE */ PAD_CFG_NF(GPD2, NONE, DEEP, NF1), +/* KBC_PWRBTN */ PAD_CFG_NF(GPD3, NONE, DEEP, NF1), +/* SLP_S3# */ PAD_CFG_NF(GPD4, NONE, DEEP, NF1), +/* SLP_S4# */ PAD_CFG_NF(GPD5, NONE, DEEP, NF1), +/* PM_SLP_M_N */ PAD_CFG_NF(GPD6, NONE, DEEP, NF1), +/* BIOS_RECOVERY NOT USED */ PAD_CFG_NC(GPD7), +/* CPU_SUSCLK */ PAD_CFG_NF(GPD8, NONE, DEEP, NF1), +/* SLP_WLAN# */ PAD_CFG_NF(GPD9, NONE, DEEP, NF1), +/* SLP_S5# */ PAD_CFG_NF(GPD10, NONE, DEEP, NF1), +/* PCH_LANPHYC */ PAD_CFG_NF(GPD11, NONE, DEEP, NF1), }; #endif From f17396591f32517416a804dee2ad5a9c33a28227 Mon Sep 17 00:00:00 2001 From: Wim Vervoorn Date: Fri, 6 Dec 2019 17:14:35 +0100 Subject: [PATCH 0688/1242] mb/facebook/monolith: Remove % tag from fmd file cbfstool doesn't support % tag yet while this was in the fmd. Revert the fmd changes that use the % tag. BUG=N/A TEST=build Change-Id: I2dc8b8f56ee0890e01be3bed939ed922feb15e89 Signed-off-by: Wim Vervoorn Reviewed-on: https://review.coreboot.org/c/coreboot/+/37672 Tested-by: build bot (Jenkins) Reviewed-by: Frans Hendriks --- src/mainboard/facebook/monolith/vboot-rw.fmd | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/src/mainboard/facebook/monolith/vboot-rw.fmd b/src/mainboard/facebook/monolith/vboot-rw.fmd index fad0f97767..fd7811b11f 100644 --- a/src/mainboard/facebook/monolith/vboot-rw.fmd +++ b/src/mainboard/facebook/monolith/vboot-rw.fmd @@ -12,14 +12,14 @@ FLASH 16M { } RW_SECTION_A@0x20000 0x860000 { VBLOCK_A@0x0 0x10000 - RW_FWID_A@0x10000% 0x40 - FW_MAIN_A(CBFS)@0x10040% 0x84FFC0 + RW_FWID_A@0x10000 0x40 + FW_MAIN_A(CBFS)@0x10040 0x84FFC0 } WP_RO@0x880000 0x080000 { RO_SECTION@0x0000 0x80000 { - FMAP@0x0% 0x800 - RO_FRID@0x800% 0x40 - RO_FRID_PAD@0x840% 0x7c0 + FMAP@0x0 0x800 + RO_FRID@0x800 0x40 + RO_FRID_PAD@0x840 0x7c0 GBB@0x1000 0x4000 COREBOOT(CBFS)@0x5000 0x07B000 } From 2f99897d006e49c64e337a1290298dd745f31434 Mon Sep 17 00:00:00 2001 From: Wim Vervoorn Date: Mon, 9 Dec 2019 14:25:58 +0100 Subject: [PATCH 0689/1242] mb/facebook/monolith: Add vboot-ro.fmd to support measured boot Add an fmd file with a layout that allows configuring the system for measured boot without enabling verified boot. BUG=N/A TEST=tested on facebook monolith Change-Id: I85fc6bee3f28fa4454d43df0e8bd1e511e1d0caf Signed-off-by: Wim Vervoorn Reviewed-on: https://review.coreboot.org/c/coreboot/+/37673 Reviewed-by: Frans Hendriks Tested-by: build bot (Jenkins) --- src/mainboard/facebook/monolith/vboot-ro.fmd | 23 ++++++++++++++++++++ 1 file changed, 23 insertions(+) create mode 100644 src/mainboard/facebook/monolith/vboot-ro.fmd diff --git a/src/mainboard/facebook/monolith/vboot-ro.fmd b/src/mainboard/facebook/monolith/vboot-ro.fmd new file mode 100644 index 0000000000..989afcbfcf --- /dev/null +++ b/src/mainboard/facebook/monolith/vboot-ro.fmd @@ -0,0 +1,23 @@ +FLASH 16M { + SI_ALL@0x0 0x700000 { + SI_DESC@0x0 0x1000 + UNUSED_1@0x1000 0x2000 + SI_ME@0x3000 0x6fd000 + } + SI_BIOS@0x700000 0x900000 { + MISC_RW@0x0 0x20000 { + RW_MRC_CACHE@0x0 0x10000 + RW_VPD(PRESERVE)@0x010000 0x2000 + RW_NVRAM(PRESERVE)@0x012000 0x6000 + } + WP_RO@0x20000 0x8E0000 { + RO_SECTION@0x0000 0x8E0000 { + FMAP@0x0 0x800 + RO_FRID@0x800 0x40 + RO_FRID_PAD@0x840 0x7c0 + GBB@0x1000 0x4000 + COREBOOT(CBFS)@0x5000 0x8DB000 + } + } + } +} From ed06e119007e65d5578963d871a1c15fb89b4d87 Mon Sep 17 00:00:00 2001 From: Patrick Georgi Date: Fri, 13 Dec 2019 14:09:28 +0100 Subject: [PATCH 0690/1242] Documentation: Extend release checklist (list to-be deprecated boards) MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Make it part of the release process to note not only what config flags / code properties etc will be deprecated, but to also spell out which boards would be affected at the time of the release. Change-Id: I0ef1404e75182ea4bacae31edb0a843e7a359545 Signed-off-by: Patrick Georgi Reviewed-on: https://review.coreboot.org/c/coreboot/+/37702 Reviewed-by: Kyösti Mälkki Reviewed-by: Nico Huber Reviewed-by: Angel Pons Tested-by: build bot (Jenkins) --- Documentation/releases/checklist.md | 3 +++ 1 file changed, 3 insertions(+) diff --git a/Documentation/releases/checklist.md b/Documentation/releases/checklist.md index ff931412f7..49045573d3 100644 --- a/Documentation/releases/checklist.md +++ b/Documentation/releases/checklist.md @@ -56,6 +56,9 @@ be more frequent than was needed, so we scaled it back to twice a year. and to update the release notes - [ ] Update the topic in the irc channel with the date of the upcoming release +- [ ] If there are any deprecations announced for the following release, + make sure that a list of currently affected board and chipsets is + part of the release notes. - [ ] Finalize release notes (as much as possible), without specifying release commit ids From 98579a9e86b341bc6827bdbb56583584981b8204 Mon Sep 17 00:00:00 2001 From: Himanshu Sahdev aka CunningLearner Date: Sat, 7 Sep 2019 16:59:43 +0530 Subject: [PATCH 0691/1242] soc/intel/common/block/chip/Kconfig: Fix minor whitespace Change-Id: I662420e6e05a6489950c583dfd37df5826153214 Signed-off-by: Himanshu Sahdev aka CunningLearner Reviewed-on: https://review.coreboot.org/c/coreboot/+/35291 Tested-by: build bot (Jenkins) Reviewed-by: RONAK KANABAR Reviewed-by: Frans Hendriks Reviewed-by: HAOUAS Elyes --- src/soc/intel/common/block/chip/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/soc/intel/common/block/chip/Kconfig b/src/soc/intel/common/block/chip/Kconfig index 273d0885e8..8021c248df 100644 --- a/src/soc/intel/common/block/chip/Kconfig +++ b/src/soc/intel/common/block/chip/Kconfig @@ -1,4 +1,4 @@ config SOC_INTEL_COMMON_BLOCK_CHIP_CONFIG bool help - Intel Processor common soc/ chip configuration support + Intel Processor common soc/chip configuration support From ece88ab765859b728c2ba17d1224455807a5fda6 Mon Sep 17 00:00:00 2001 From: Taniya Das Date: Tue, 5 Nov 2019 21:37:32 +0530 Subject: [PATCH 0692/1242] sc7180: clock: Add support for QUP DFSR configuration Support configuring the qup dfsr registers. Tested: validated DFSR clock configuration and M/N/D values. Change-Id: I146ac7c2197606965265f2a770769312af76041e Signed-off-by: Taniya Das Reviewed-on: https://review.coreboot.org/c/coreboot/+/37305 Tested-by: build bot (Jenkins) Reviewed-by: Julius Werner --- src/soc/qualcomm/sc7180/clock.c | 89 +++++++++++++++++++++ src/soc/qualcomm/sc7180/include/soc/clock.h | 21 ++++- 2 files changed, 109 insertions(+), 1 deletion(-) diff --git a/src/soc/qualcomm/sc7180/clock.c b/src/soc/qualcomm/sc7180/clock.c index 9092a4e185..b447a54487 100644 --- a/src/soc/qualcomm/sc7180/clock.c +++ b/src/soc/qualcomm/sc7180/clock.c @@ -60,6 +60,61 @@ struct clock_config qspi_core_cfg[] = { } }; +struct clock_config qup_wrap_cfg[] = { + { + .hz = SRC_XO_HZ, /* 19.2KHz */ + .src = SRC_XO_19_2MHZ, + .div = DIV(1), + }, + { + .hz = 32 * MHz, + .src = SRC_GPLL0_EVEN_300MHZ, + .div = DIV(1), + .m = 8, + .n = 75, + .d_2 = 150, + }, + { + .hz = 48 * MHz, + .src = SRC_GPLL0_EVEN_300MHZ, + .div = DIV(1), + .m = 4, + .n = 25, + .d_2 = 50, + }, + { + .hz = 64 * MHz, + .src = SRC_GPLL0_EVEN_300MHZ, + .div = DIV(1), + .m = 16, + .n = 75, + .d_2 = 150, + }, + { + .hz = 96 * MHz, + .src = SRC_GPLL0_EVEN_300MHZ, + .div = DIV(1), + .m = 8, + .n = 25, + .d_2 = 50, + }, + { + .hz = 100 * MHz, + .src = SRC_GPLL0_EVEN_300MHZ, + .div = DIV(3), + }, + { + .hz = SRC_XO_HZ, /* 19.2KHz */ + .src = SRC_XO_19_2MHZ, + .div = DIV(1), + }, + { + .hz = SRC_XO_HZ, /* 19.2KHz */ + .src = SRC_XO_19_2MHZ, + .div = DIV(1), + }, +}; + static int clock_configure_gpll0(void) { setbits32(&gcc->gpll0.user_ctl_u, 1 << SCALE_FREQ_SHFT); @@ -173,6 +228,40 @@ int clock_reset_bcr(void *bcr_addr, bool reset) return 0; } +void clock_configure_dfsr(int qup) +{ + int idx; + int s = qup % QUP_WRAP1_S0; + uint32_t reg_val; + struct sc7180_qupv3_clock *qup_clk = qup < QUP_WRAP1_S0 ? + &gcc->qup_wrap0_s[s] : &gcc->qup_wrap1_s[s]; + + setbits32(&qup_clk->dfsr_clk.cmd_dfsr, BIT(CLK_CTL_CMD_DFSR_SHFT)); + + for (idx = 0; idx < ARRAY_SIZE(qup_wrap_cfg); idx++) { + reg_val = (qup_wrap_cfg[idx].src << CLK_CTL_CFG_SRC_SEL_SHFT) | + (qup_wrap_cfg[idx].div << CLK_CTL_CFG_SRC_DIV_SHFT); + + write32(&qup_clk->dfsr_clk.perf_dfsr[idx], reg_val); + + if (qup_wrap_cfg[idx].m == 0) + continue; + + setbits32(&qup_clk->dfsr_clk.cmd_dfsr, + RCG_MODE_DUAL_EDGE << CLK_CTL_CFG_MODE_SHFT); + + reg_val = qup_wrap_cfg[idx].m & CLK_CTL_RCG_MND_BMSK; + write32(&qup_clk->dfsr_clk.perf_m_dfsr[idx], reg_val); + + reg_val = ~(qup_wrap_cfg[idx].n - qup_wrap_cfg[idx].m) + & CLK_CTL_RCG_MND_BMSK; + write32(&qup_clk->dfsr_clk.perf_n_dfsr[idx], reg_val); + + reg_val = ~(qup_wrap_cfg[idx].d_2) & CLK_CTL_RCG_MND_BMSK; + write32(&qup_clk->dfsr_clk.perf_d_dfsr[idx], reg_val); + } +} + void clock_configure_qup(int qup, uint32_t hz) { int s = qup % QUP_WRAP1_S0; diff --git a/src/soc/qualcomm/sc7180/include/soc/clock.h b/src/soc/qualcomm/sc7180/include/soc/clock.h index 39cde8c1bc..2e44b60623 100644 --- a/src/soc/qualcomm/sc7180/include/soc/clock.h +++ b/src/soc/qualcomm/sc7180/include/soc/clock.h @@ -56,9 +56,22 @@ struct sc7180_mnd_clock { u32 d_2; }; +struct sc7180_dfsr_clock { + u32 cmd_dfsr; + u8 _res0[0x20 - 0x1c]; + u32 perf_dfsr[8]; + u8 _res1[0x60 - 0x40]; + u32 perf_m_dfsr[8]; + u8 _res2[0xa0 - 0x80]; + u32 perf_n_dfsr[8]; + u8 _res3[0xe0 - 0xc0]; + u32 perf_d_dfsr[8]; + u8 _res4[0x130 - 0x100]; +}; + struct sc7180_qupv3_clock { struct sc7180_mnd_clock mnd_clk; - u8 _res[0x130 - 0x18]; + struct sc7180_dfsr_clock dfsr_clk; }; struct sc7180_gpll { @@ -171,6 +184,11 @@ enum clk_ctl_bcr { CLK_CTL_BCR_BLK_ARES_SHFT = 0, }; +enum clk_ctl_dfsr { + CLK_CTL_CMD_DFSR_BMSK = 0x1, + CLK_CTL_CMD_DFSR_SHFT = 0, +}; + enum clk_qup { QUP_WRAP0_S0, QUP_WRAP0_S1, @@ -210,5 +228,6 @@ void clock_configure_qspi(uint32_t hz); int clock_reset_bcr(void *bcr_addr, bool reset); void clock_configure_qup(int qup, uint32_t hz); void clock_enable_qup(int qup); +void clock_configure_dfsr(int qup); #endif // __SOC_QUALCOMM_SC7180_CLOCK_H__ From 80759b0dbdf119fb97f0b7655a063916958bd7ce Mon Sep 17 00:00:00 2001 From: Arthur Heymans Date: Sun, 27 Oct 2019 08:56:29 +0100 Subject: [PATCH 0693/1242] drivers/intel/fsp1_1: Drop unused function Change-Id: Ide336fb900360c446bffcc5ca31bf51e7746cae1 Signed-off-by: Arthur Heymans Reviewed-on: https://review.coreboot.org/c/coreboot/+/36370 Tested-by: build bot (Jenkins) Reviewed-by: HAOUAS Elyes Reviewed-by: Angel Pons --- src/drivers/intel/fsp1_1/fsp_util.c | 7 ------- src/drivers/intel/fsp1_1/include/fsp/util.h | 9 --------- 2 files changed, 16 deletions(-) diff --git a/src/drivers/intel/fsp1_1/fsp_util.c b/src/drivers/intel/fsp1_1/fsp_util.c index b1075ff2b5..891dc0379d 100644 --- a/src/drivers/intel/fsp1_1/fsp_util.c +++ b/src/drivers/intel/fsp1_1/fsp_util.c @@ -280,10 +280,3 @@ void fsp_display_upd_value(const char *name, uint32_t size, uint64_t old, } } } - -__attribute__((cdecl)) size_t fsp_write_line(uint8_t *buffer, - size_t number_of_bytes) -{ - console_write_line(buffer, number_of_bytes); - return number_of_bytes; -} diff --git a/src/drivers/intel/fsp1_1/include/fsp/util.h b/src/drivers/intel/fsp1_1/include/fsp/util.h index dca6d560a4..73b156fb94 100644 --- a/src/drivers/intel/fsp1_1/include/fsp/util.h +++ b/src/drivers/intel/fsp1_1/include/fsp/util.h @@ -96,15 +96,6 @@ void *get_first_hob(uint16_t type); void *get_next_guid_hob(const EFI_GUID *guid, const void *hob_start); void *get_first_guid_hob(const EFI_GUID *guid); -/* - * Writes number_of_bytes data bytes from buffer to the console. - * The number of bytes actually written to the console is returned. - * - * If number_of_bytes is zero, don't output any data but instead wait until - * the console has output all data, then return 0. - */ -__attribute__((cdecl)) size_t fsp_write_line(uint8_t *buffer, - size_t number_of_bytes); asmlinkage void chipset_teardown_car_main(void); From b86e96ab8cb190d0244fe442069fcef5e88ef68b Mon Sep 17 00:00:00 2001 From: Arthur Heymans Date: Sun, 10 Feb 2019 17:00:56 +0100 Subject: [PATCH 0694/1242] arch/x86: Make X86 stages select ARCH_X86 Also, don't define the default as this results in spurious lines in the .config. TEST: Build all boards with where config.h differed with BUILD_TIMELESS=1 and remained the same Change-Id: Ic77b696f493d7648f317f0ba0a27fdee5212961e Signed-off-by: Arthur Heymans Reviewed-on: https://review.coreboot.org/c/coreboot/+/31316 Reviewed-by: Angel Pons Reviewed-by: Nico Huber Reviewed-by: HAOUAS Elyes Tested-by: build bot (Jenkins) --- src/arch/x86/Kconfig | 19 ++++++++++--------- src/mainboard/apple/macbook21/Kconfig | 1 - src/mainboard/asrock/g41c-gs/Kconfig | 1 - src/mainboard/asus/p5gc-mx/Kconfig | 1 - src/mainboard/asus/p5qc/Kconfig | 1 - src/mainboard/asus/p5qpl-am/Kconfig | 1 - src/mainboard/asus/p8h61-m_pro/Kconfig | 1 - src/mainboard/foxconn/g41s-k/Kconfig | 1 - src/mainboard/gigabyte/ga-945gcm-s2l/Kconfig | 1 - src/mainboard/gigabyte/ga-b75m-d3h/Kconfig | 1 - src/mainboard/gigabyte/ga-g41m-es2l/Kconfig | 1 - src/mainboard/gigabyte/ga-h61m-s2pv/Kconfig | 1 - src/mainboard/intel/dg41wv/Kconfig | 1 - src/mainboard/intel/dg43gt/Kconfig | 1 - src/mainboard/lenovo/thinkcentre_a58/Kconfig | 1 - src/mainboard/msi/ms7707/Kconfig | 1 - .../sapphire/pureplatinumh61/Kconfig | 1 - 17 files changed, 10 insertions(+), 25 deletions(-) diff --git a/src/arch/x86/Kconfig b/src/arch/x86/Kconfig index e27aec2463..5713a21d65 100644 --- a/src/arch/x86/Kconfig +++ b/src/arch/x86/Kconfig @@ -13,7 +13,6 @@ config ARCH_X86 bool - default n select PCI select RELOCATABLE_MODULES @@ -21,17 +20,16 @@ config ARCH_X86 config ARCH_BOOTBLOCK_X86_32 bool - default n select ARCH_X86 select BOOTBLOCK_CUSTOM if ROMCC_BOOTBLOCK config ARCH_VERSTAGE_X86_32 bool - default n + select ARCH_X86 config ARCH_ROMSTAGE_X86_32 bool - default n + select ARCH_X86 config ARCH_POSTCAR_X86_32 bool @@ -39,23 +37,22 @@ config ARCH_POSTCAR_X86_32 config ARCH_RAMSTAGE_X86_32 bool - default n + select ARCH_X86 # stage selectors for x64 config ARCH_BOOTBLOCK_X86_64 bool - default n select ARCH_X86 select BOOTBLOCK_CUSTOM if ROMCC_BOOTBLOCK config ARCH_VERSTAGE_X86_64 bool - default n + select ARCH_X86 config ARCH_ROMSTAGE_X86_64 bool - default n + select ARCH_X86 config ARCH_POSTCAR_X86_64 bool @@ -63,7 +60,9 @@ config ARCH_POSTCAR_X86_64 config ARCH_RAMSTAGE_X86_64 bool - default n + select ARCH_X86 + +if ARCH_X86 config ARCH_X86_64_PGTBL_LOC hex "x86_64 page table location in CBFS" @@ -350,3 +349,5 @@ config MAX_PIRQ_LINKS also have a separate link for ATA or IOAPIC interrupts. When the PIRQ table specifies links greater than 4, pirq_route_irqs will not function properly, unless this variable is correctly set. + +endif diff --git a/src/mainboard/apple/macbook21/Kconfig b/src/mainboard/apple/macbook21/Kconfig index 93e2d8d9b4..9eb06ff36e 100644 --- a/src/mainboard/apple/macbook21/Kconfig +++ b/src/mainboard/apple/macbook21/Kconfig @@ -3,7 +3,6 @@ if BOARD_APPLE_MACBOOK11 || BOARD_APPLE_MACBOOK21 || BOARD_APPLE_IMAC52 config BOARD_SPECIFIC_OPTIONS def_bool y select SYSTEM_TYPE_LAPTOP - select ARCH_X86 select CPU_INTEL_SOCKET_M select NORTHBRIDGE_INTEL_I945 select NORTHBRIDGE_INTEL_SUBTYPE_I945GM diff --git a/src/mainboard/asrock/g41c-gs/Kconfig b/src/mainboard/asrock/g41c-gs/Kconfig index 81b0995988..5f66969100 100644 --- a/src/mainboard/asrock/g41c-gs/Kconfig +++ b/src/mainboard/asrock/g41c-gs/Kconfig @@ -20,7 +20,6 @@ if BOARD_ASROCK_G41C_GS || BOARD_ASROCK_G41C_GS_R2_0 || \ config BOARD_SPECIFIC_OPTIONS def_bool y - select ARCH_X86 select CPU_INTEL_SOCKET_LGA775 select NORTHBRIDGE_INTEL_X4X select SOUTHBRIDGE_INTEL_I82801GX diff --git a/src/mainboard/asus/p5gc-mx/Kconfig b/src/mainboard/asus/p5gc-mx/Kconfig index a0e60146a0..7b5cd19ac4 100644 --- a/src/mainboard/asus/p5gc-mx/Kconfig +++ b/src/mainboard/asus/p5gc-mx/Kconfig @@ -17,7 +17,6 @@ if BOARD_ASUS_P5GC_MX config BOARD_SPECIFIC_OPTIONS def_bool y - select ARCH_X86 select CPU_INTEL_SOCKET_LGA775 select NORTHBRIDGE_INTEL_I945 select NORTHBRIDGE_INTEL_SUBTYPE_I945GC diff --git a/src/mainboard/asus/p5qc/Kconfig b/src/mainboard/asus/p5qc/Kconfig index 9c147875f1..b59cd3cd44 100644 --- a/src/mainboard/asus/p5qc/Kconfig +++ b/src/mainboard/asus/p5qc/Kconfig @@ -18,7 +18,6 @@ if BOARD_ASUS_P5QC || BOARD_ASUS_P5Q_PRO || BOARD_ASUS_P5QL_PRO config BOARD_SPECIFIC_OPTIONS def_bool y - select ARCH_X86 select CPU_INTEL_SOCKET_LGA775 select NORTHBRIDGE_INTEL_X4X select SOUTHBRIDGE_INTEL_I82801JX diff --git a/src/mainboard/asus/p5qpl-am/Kconfig b/src/mainboard/asus/p5qpl-am/Kconfig index 7cdfea9048..0932241655 100644 --- a/src/mainboard/asus/p5qpl-am/Kconfig +++ b/src/mainboard/asus/p5qpl-am/Kconfig @@ -18,7 +18,6 @@ if BOARD_ASUS_P5QPL_AM || BOARD_ASUS_P5G41T_M_LX config BOARD_SPECIFIC_OPTIONS def_bool y - select ARCH_X86 select CPU_INTEL_SOCKET_LGA775 select NORTHBRIDGE_INTEL_X4X select SOUTHBRIDGE_INTEL_I82801GX diff --git a/src/mainboard/asus/p8h61-m_pro/Kconfig b/src/mainboard/asus/p8h61-m_pro/Kconfig index 0c8988e0c8..e9b8ab0f07 100644 --- a/src/mainboard/asus/p8h61-m_pro/Kconfig +++ b/src/mainboard/asus/p8h61-m_pro/Kconfig @@ -17,7 +17,6 @@ if BOARD_ASUS_P8H61_M_PRO config BOARD_SPECIFIC_OPTIONS def_bool y - select ARCH_X86 select BOARD_ROMSIZE_KB_4096 select HAVE_ACPI_RESUME select HAVE_ACPI_TABLES diff --git a/src/mainboard/foxconn/g41s-k/Kconfig b/src/mainboard/foxconn/g41s-k/Kconfig index 3597e4c82f..c35575835d 100644 --- a/src/mainboard/foxconn/g41s-k/Kconfig +++ b/src/mainboard/foxconn/g41s-k/Kconfig @@ -18,7 +18,6 @@ if BOARD_FOXCONN_G41S_K || BOARD_FOXCONN_G41M config BOARD_SPECIFIC_OPTIONS def_bool y - select ARCH_X86 select CPU_INTEL_SOCKET_LGA775 select NORTHBRIDGE_INTEL_X4X select SOUTHBRIDGE_INTEL_I82801GX diff --git a/src/mainboard/gigabyte/ga-945gcm-s2l/Kconfig b/src/mainboard/gigabyte/ga-945gcm-s2l/Kconfig index 3c373a767b..ea1a2fc689 100644 --- a/src/mainboard/gigabyte/ga-945gcm-s2l/Kconfig +++ b/src/mainboard/gigabyte/ga-945gcm-s2l/Kconfig @@ -17,7 +17,6 @@ if BOARD_GIGABYTE_GA_945GCM_S2L || BOARD_GIGABYTE_GA_945GCM_S2C config BOARD_SPECIFIC_OPTIONS def_bool y - select ARCH_X86 select CPU_INTEL_SOCKET_LGA775 select NORTHBRIDGE_INTEL_I945 select NORTHBRIDGE_INTEL_SUBTYPE_I945GC diff --git a/src/mainboard/gigabyte/ga-b75m-d3h/Kconfig b/src/mainboard/gigabyte/ga-b75m-d3h/Kconfig index 1ad68f4a96..719a649678 100644 --- a/src/mainboard/gigabyte/ga-b75m-d3h/Kconfig +++ b/src/mainboard/gigabyte/ga-b75m-d3h/Kconfig @@ -2,7 +2,6 @@ if BOARD_GIGABYTE_GA_B75M_D3H || BOARD_GIGABYTE_GA_B75M_D3V || BOARD_GIGABYTE_GA config BOARD_SPECIFIC_OPTIONS def_bool y - select ARCH_X86 select NORTHBRIDGE_INTEL_SANDYBRIDGE select USE_NATIVE_RAMINIT select SOUTHBRIDGE_INTEL_C216 diff --git a/src/mainboard/gigabyte/ga-g41m-es2l/Kconfig b/src/mainboard/gigabyte/ga-g41m-es2l/Kconfig index 6280facbc0..e928cbecaf 100644 --- a/src/mainboard/gigabyte/ga-g41m-es2l/Kconfig +++ b/src/mainboard/gigabyte/ga-g41m-es2l/Kconfig @@ -17,7 +17,6 @@ if BOARD_GIGABYTE_GA_G41M_ES2L config BOARD_SPECIFIC_OPTIONS def_bool y - select ARCH_X86 select CPU_INTEL_SOCKET_LGA775 select NORTHBRIDGE_INTEL_X4X select SOUTHBRIDGE_INTEL_I82801GX diff --git a/src/mainboard/gigabyte/ga-h61m-s2pv/Kconfig b/src/mainboard/gigabyte/ga-h61m-s2pv/Kconfig index 62d7f40117..62c422aa53 100644 --- a/src/mainboard/gigabyte/ga-h61m-s2pv/Kconfig +++ b/src/mainboard/gigabyte/ga-h61m-s2pv/Kconfig @@ -17,7 +17,6 @@ if BOARD_GIGABYTE_GA_H61M_S2PV || BOARD_GIGABYTE_GA_H61MA_D3V config BOARD_SPECIFIC_OPTIONS def_bool y - select ARCH_X86 select BOARD_ROMSIZE_KB_4096 select HAVE_ACPI_RESUME select HAVE_ACPI_TABLES diff --git a/src/mainboard/intel/dg41wv/Kconfig b/src/mainboard/intel/dg41wv/Kconfig index 74c7d5270c..648634ee51 100644 --- a/src/mainboard/intel/dg41wv/Kconfig +++ b/src/mainboard/intel/dg41wv/Kconfig @@ -18,7 +18,6 @@ if BOARD_INTEL_DG41WV config BOARD_SPECIFIC_OPTIONS def_bool y - select ARCH_X86 select CPU_INTEL_SOCKET_LGA775 select NORTHBRIDGE_INTEL_X4X select SOUTHBRIDGE_INTEL_I82801GX diff --git a/src/mainboard/intel/dg43gt/Kconfig b/src/mainboard/intel/dg43gt/Kconfig index 341baaa302..3c457ba1e2 100644 --- a/src/mainboard/intel/dg43gt/Kconfig +++ b/src/mainboard/intel/dg43gt/Kconfig @@ -18,7 +18,6 @@ if BOARD_INTEL_DG43GT config BOARD_SPECIFIC_OPTIONS def_bool y - select ARCH_X86 select CPU_INTEL_SOCKET_LGA775 select NORTHBRIDGE_INTEL_X4X select SOUTHBRIDGE_INTEL_I82801JX diff --git a/src/mainboard/lenovo/thinkcentre_a58/Kconfig b/src/mainboard/lenovo/thinkcentre_a58/Kconfig index 6d8b3dcd39..b42866cee7 100644 --- a/src/mainboard/lenovo/thinkcentre_a58/Kconfig +++ b/src/mainboard/lenovo/thinkcentre_a58/Kconfig @@ -18,7 +18,6 @@ if BOARD_LENOVO_THINKCENTRE_A58 config BOARD_SPECIFIC_OPTIONS def_bool y - select ARCH_X86 select CPU_INTEL_SOCKET_LGA775 select NORTHBRIDGE_INTEL_X4X select SOUTHBRIDGE_INTEL_I82801GX diff --git a/src/mainboard/msi/ms7707/Kconfig b/src/mainboard/msi/ms7707/Kconfig index c1a1b4c748..96ca719ea3 100644 --- a/src/mainboard/msi/ms7707/Kconfig +++ b/src/mainboard/msi/ms7707/Kconfig @@ -2,7 +2,6 @@ if BOARD_MSI_MS7707 config BOARD_SPECIFIC_OPTIONS def_bool y - select ARCH_X86 select NORTHBRIDGE_INTEL_SANDYBRIDGE select USE_NATIVE_RAMINIT select SOUTHBRIDGE_INTEL_BD82X6X diff --git a/src/mainboard/sapphire/pureplatinumh61/Kconfig b/src/mainboard/sapphire/pureplatinumh61/Kconfig index 0e289c18d4..707d2c9d8d 100644 --- a/src/mainboard/sapphire/pureplatinumh61/Kconfig +++ b/src/mainboard/sapphire/pureplatinumh61/Kconfig @@ -2,7 +2,6 @@ if BOARD_SAPPHIRE_PUREPLATINUMH61 config BOARD_SPECIFIC_OPTIONS def_bool y - select ARCH_X86 select NORTHBRIDGE_INTEL_SANDYBRIDGE select USE_NATIVE_RAMINIT select SOUTHBRIDGE_INTEL_BD82X6X From bf15b2f7c3474c9811516d16f40a3533da5108c7 Mon Sep 17 00:00:00 2001 From: Nico Huber Date: Fri, 13 Dec 2019 13:44:04 +0100 Subject: [PATCH 0695/1242] 3rdparty/fsp: Update to current master again We had to role the `fsp` submodule back for a minute due to a regression with the Coffee Lake binary. Intel silently mixed FSP 2.1 features into the Coffee Lake FSP which is supposed to be FSP 2.0. With the stack and heap usage partitioned for FSP using coreboot's stack (config FSP_USES_ CB_STACK), it works again. To make this even messier: We already selected this Kconfig option for Whiskey Lake, which is supposed to use the very same FSP binary. So with either submodule pointer, something was always broken :-/ Change-Id: Id2aa17aaa2c843dcc7e0fb28779d1e5948da83c9 Signed-off-by: Nico Huber Reviewed-on: https://review.coreboot.org/c/coreboot/+/37700 Tested-by: build bot (Jenkins) Reviewed-by: Jeremy Soller Reviewed-by: Angel Pons Reviewed-by: Mimoja --- 3rdparty/fsp | 2 +- src/soc/intel/cannonlake/Kconfig | 1 + 2 files changed, 2 insertions(+), 1 deletion(-) diff --git a/3rdparty/fsp b/3rdparty/fsp index 9e53d779eb..0bc2b07eab 160000 --- a/3rdparty/fsp +++ b/3rdparty/fsp @@ -1 +1 @@ -Subproject commit 9e53d779eb34e944f9b3386ad6a9df80f710bddd +Subproject commit 0bc2b07eab29a8a75cd084963c285ee5434e6666 diff --git a/src/soc/intel/cannonlake/Kconfig b/src/soc/intel/cannonlake/Kconfig index c82660e6dc..6d635ade3d 100644 --- a/src/soc/intel/cannonlake/Kconfig +++ b/src/soc/intel/cannonlake/Kconfig @@ -23,6 +23,7 @@ config SOC_INTEL_CANNONLAKE config SOC_INTEL_COFFEELAKE bool select SOC_INTEL_CANNONLAKE_BASE + select FSP_USES_CB_STACK help Intel Coffeelake support From 45d05d08237e5c262312453a2f272ef32d9366fb Mon Sep 17 00:00:00 2001 From: Matt DeVillier Date: Thu, 5 Dec 2019 17:35:00 -0600 Subject: [PATCH 0696/1242] ec/google/chromeec/acpi: move PS2K under PCI0 Commit 77ad581ce [chromeec: PS2K node can't be under SIO node] moved the PS2K ACPI device from under the SIO device to under the LPCB, and while this fixed the keyboard under Windows for Skylake devices, it was insufficient for Baytrail and Braswell devices (and likely Apollo Lake/Gemini Lake too). Moving the PS2K device under PCI0 allows the PS2K to be functional under Windows for all Chrome-EC platforms. Test: build/boot various Chrome-EC devices from IVB, HSW, BDW, BYT, SKL, BSW, and KBL platforms, verify keyboard functional under both Linux (4.x and 5.x) and Windows 10. Change-Id: If773eea69dc46030b6db9d64c3855be49951d4c0 Signed-off-by: Matt DeVillier Reviewed-on: https://review.coreboot.org/c/coreboot/+/37542 Reviewed-by: Angel Pons Reviewed-by: Furquan Shaikh Reviewed-by: Paul Menzel Tested-by: build bot (Jenkins) --- src/ec/google/chromeec/acpi/superio.asl | 51 +++++++++++++------------ 1 file changed, 27 insertions(+), 24 deletions(-) diff --git a/src/ec/google/chromeec/acpi/superio.asl b/src/ec/google/chromeec/acpi/superio.asl index 9c0fa68141..fc5fc8c266 100644 --- a/src/ec/google/chromeec/acpi/superio.asl +++ b/src/ec/google/chromeec/acpi/superio.asl @@ -131,30 +131,20 @@ Device (SIO) { } #ifdef SIO_EC_ENABLE_PS2K -Device (PS2K) // Keyboard +Scope (\_SB.PCI0) { - Name (_UID, 0) - Name (_HID, "GOOG000A") - Name (_CID, Package() { EISAID("PNP0303"), EISAID("PNP030B") } ) - - Method (_STA, 0, NotSerialized) { - Return (0x0F) - } - - Name (_CRS, ResourceTemplate() + Device (PS2K) // Keyboard { - IO (Decode16, 0x60, 0x60, 0x01, 0x01) - IO (Decode16, 0x64, 0x64, 0x01, 0x01) -#ifdef SIO_EC_PS2K_IRQ - SIO_EC_PS2K_IRQ -#else - IRQ (Edge, ActiveHigh, Exclusive) {1} -#endif - }) + Name (_UID, 0) + Name (_HID, "GOOG000A") + Name (_CID, Package() { EISAID("PNP0303"), EISAID("PNP030B") } ) - Name (_PRS, ResourceTemplate() - { - StartDependentFn (0, 0) { + Method (_STA, 0, NotSerialized) { + Return (0x0F) + } + + Name (_CRS, ResourceTemplate() + { IO (Decode16, 0x60, 0x60, 0x01, 0x01) IO (Decode16, 0x64, 0x64, 0x01, 0x01) #ifdef SIO_EC_PS2K_IRQ @@ -162,8 +152,21 @@ Device (PS2K) // Keyboard #else IRQ (Edge, ActiveHigh, Exclusive) {1} #endif - } - EndDependentFn () - }) + }) + + Name (_PRS, ResourceTemplate() + { + StartDependentFn (0, 0) { + IO (Decode16, 0x60, 0x60, 0x01, 0x01) + IO (Decode16, 0x64, 0x64, 0x01, 0x01) +#ifdef SIO_EC_PS2K_IRQ + SIO_EC_PS2K_IRQ +#else + IRQ (Edge, ActiveHigh, Exclusive) {1} +#endif + } + EndDependentFn () + }) + } } #endif From 591dbfe295bc46965db79762ce17cd7e664e25a6 Mon Sep 17 00:00:00 2001 From: Nico Huber Date: Sat, 14 Dec 2019 20:44:47 +0100 Subject: [PATCH 0697/1242] util/cbfstool: Further reduce warnings for lz4 code If the compiler fails to inline all the FORCE_INLINE functions, it will complain. Change-Id: I7b8349c9a3d53c47ac189f02b296600abac8a0cf Signed-off-by: Nico Huber Reviewed-on: https://review.coreboot.org/c/coreboot/+/37734 Reviewed-by: Idwer Vollering Tested-by: build bot (Jenkins) --- util/cbfstool/Makefile.inc | 1 + 1 file changed, 1 insertion(+) diff --git a/util/cbfstool/Makefile.inc b/util/cbfstool/Makefile.inc index 5c048486e6..066ef3495c 100644 --- a/util/cbfstool/Makefile.inc +++ b/util/cbfstool/Makefile.inc @@ -212,6 +212,7 @@ $(objutil)/cbfstool/cbfs.o: TOOLCFLAGS += -Wno-sign-compare -Wno-cast-qual $(objutil)/cbfstool/mem_pool.o: TOOLCFLAGS += -Wno-sign-compare -Wno-cast-qual # Tolerate lz4 warnings $(objutil)/cbfstool/lz4.o: TOOLCFLAGS += -Wno-missing-prototypes +$(objutil)/cbfstool/lz4_wrapper.o: TOOLCFLAGS += -Wno-attributes $(objutil)/cbfstool/fmd.o: $(objutil)/cbfstool/fmd_parser.h $(objutil)/cbfstool/fmd.o: $(objutil)/cbfstool/fmd_scanner.h From 658ae3eb29b048121a3365946ba7f9f7b357970f Mon Sep 17 00:00:00 2001 From: Matt DeVillier Date: Fri, 13 Dec 2019 01:22:30 -0600 Subject: [PATCH 0698/1242] mb/google/auron: add VBTs for variants Add VBTs for all auron variants, extracted from VGA BIOS from stock firmware images using intelvbttool, zero-padded to 0x11ff bytes to make the Intel BMP editor happy. Test: boot several auron variants with libgfxinit and Tianocore payload, ensure both internal and external displays as well as HDMI audio function properly under Linux (4.x/5.x). Change-Id: Ibc4eabfa5d02b4c08755cf52835b5df8c1291fea Signed-off-by: Matt DeVillier Reviewed-on: https://review.coreboot.org/c/coreboot/+/37714 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber Reviewed-by: Angel Pons --- src/mainboard/google/auron/Kconfig | 1 + .../google/auron/variants/auron_paine/data.vbt | Bin 0 -> 4608 bytes .../google/auron/variants/auron_yuna/data.vbt | Bin 0 -> 4608 bytes .../google/auron/variants/buddy/data.vbt | Bin 0 -> 4608 bytes .../google/auron/variants/gandof/data.vbt | Bin 0 -> 4608 bytes .../google/auron/variants/lulu/data.vbt | Bin 0 -> 4608 bytes .../google/auron/variants/samus/data.vbt | Bin 0 -> 4608 bytes 7 files changed, 1 insertion(+) create mode 100644 src/mainboard/google/auron/variants/auron_paine/data.vbt create mode 100644 src/mainboard/google/auron/variants/auron_yuna/data.vbt create mode 100644 src/mainboard/google/auron/variants/buddy/data.vbt create mode 100644 src/mainboard/google/auron/variants/gandof/data.vbt create mode 100644 src/mainboard/google/auron/variants/lulu/data.vbt create mode 100644 src/mainboard/google/auron/variants/samus/data.vbt diff --git a/src/mainboard/google/auron/Kconfig b/src/mainboard/google/auron/Kconfig index b64b47eb70..644104a37e 100644 --- a/src/mainboard/google/auron/Kconfig +++ b/src/mainboard/google/auron/Kconfig @@ -8,6 +8,7 @@ config BOARD_GOOGLE_BASEBOARD_AURON select HAVE_ACPI_TABLES select HAVE_OPTION_TABLE select HAVE_ACPI_RESUME + select INTEL_GMA_HAVE_VBT select MAINBOARD_HAS_CHROMEOS select MAINBOARD_HAS_LIBGFXINIT select MAINBOARD_HAS_LPC_TPM diff --git a/src/mainboard/google/auron/variants/auron_paine/data.vbt b/src/mainboard/google/auron/variants/auron_paine/data.vbt new file mode 100644 index 0000000000000000000000000000000000000000..a73fb49d98b7ebb64284955a250d47b855238f19 GIT binary patch literal 4608 zcmdT{ZEO>D7=QkE*Yl;vGhVlDwzIJAg)s?AfmT5$jPa5g zO{h8(jBouw2p9rONQ{zb_QmKI6Z`@sCWe?u^otTd5loCRd@uy9&;RaL21RHHXMcztg=jjrUtgm-J&sjZam)WGnjM0_N^sXIN;^Avsw3*niX zzb*mf7+a{en~$zc?bwqaj}A3qa(F$i*|}x=cz#79zx%~KJ0~#HlfwAct@-i%C*Krn*xjy$Ma38%NL1iI*q0Kfi4cMthnt zW}0Rzakit~W$f8GInjpk@o^mDIlFNvzdJv(Pr1E9u8Cf>eG6=# zlD^GCDCE0b>jdb<9y1~uCdLM8SWalmbG8DLtyrG1!o4{R17&`Bo^WEHQ zZl#5lq3a`em>|+vq{U#yIyzUa?y|ZQeaZfGW@uz|Y{SOFYp=gC9f7N#(wpod&wHcJ zOh_s9FeygixG2EK;wo4porPcg2)Yu220{m6lTU^dJ_9}@oFV)`_|>Pt9|S>GKqb@> z9wxLB9wVd(!-QuD&l7eLULm|mc%N{DaDwm&;d8=Qgs%zT5q=_g_rleZPynCZ-vV=W zjiVtX!Fx?mIO@iax^e$+v@b{$R|i~e2dijGC7%!eDt!}%Qb~TC_rM|snm3kknUbzf z+gcPeu0KMW&+nM)mrDLDxiPx#U8{V}_q-#e(*14)&Ok$f2H~D7?T>xA-?bH<*wj1b z1uVb+Uo-q}v8$4>rd<8NP_HW%wa364aaep^|HSrx-dXq*Z57e34RX24nbSHzx-YXS zvw25;eC_6!@>M#El8~zdD-O%d@PSTeykWB$4iAE9nG*|~Nc~4ErY;OdmRVzm=OW1` zEOX0j%(70+MZ!_&+%Gzlsdn!7fc;e=ixur%OqQ2_%K+56DAd6fy6T|F5S;5QeWIMJ zgm{sNa8VHuRo%`5B z8;MF_;0GB5`q?3YN-LRwB*e?a!0$0=piq)bC&dmWDKiU=5T$)!Iav}Zi(EeiJ%9*7 zVII*<%xIWiyu0GYNs^|6ATADIcfc44D9;9PI$#_MC^G>(9WcHRC_e{KR*i_NG^*II z8XHyRIThbgjbp0vk&54_#syWmq+&=jmTF3ihC`Z>)07<=9@LBvHDy-A^O|u{Q-0Sl ztQ*a`(xKx9-5A%EeL5c1jZbyu3mt#djo)=LV;jnwcYu$_yd|xUE{= zY8cFB>uh#9XNCuzU$MLoB5g;`aEE)+X3!i44^}aXOA(mK;388sd-zlKJcva)kJN{P zZ$SBIA!svD3G?3mTr^pbEx>|oC{)9ra{55kltiua6Mo;M z@j+cLkL&_(e`q<3o$NnL|4;B%n`h6D-?3e~L0TSwxB93XDf)k69b_N}E$k3n6x(J2 P4wU8oFt4A@|HAtl;!_Es literal 0 HcmV?d00001 diff --git a/src/mainboard/google/auron/variants/auron_yuna/data.vbt b/src/mainboard/google/auron/variants/auron_yuna/data.vbt new file mode 100644 index 0000000000000000000000000000000000000000..a73fb49d98b7ebb64284955a250d47b855238f19 GIT binary patch literal 4608 zcmdT{ZEO>D7=QkE*Yl;vGhVlDwzIJAg)s?AfmT5$jPa5g zO{h8(jBouw2p9rONQ{zb_QmKI6Z`@sCWe?u^otTd5loCRd@uy9&;RaL21RHHXMcztg=jjrUtgm-J&sjZam)WGnjM0_N^sXIN;^Avsw3*niX zzb*mf7+a{en~$zc?bwqaj}A3qa(F$i*|}x=cz#79zx%~KJ0~#HlfwAct@-i%C*Krn*xjy$Ma38%NL1iI*q0Kfi4cMthnt zW}0Rzakit~W$f8GInjpk@o^mDIlFNvzdJv(Pr1E9u8Cf>eG6=# zlD^GCDCE0b>jdb<9y1~uCdLM8SWalmbG8DLtyrG1!o4{R17&`Bo^WEHQ zZl#5lq3a`em>|+vq{U#yIyzUa?y|ZQeaZfGW@uz|Y{SOFYp=gC9f7N#(wpod&wHcJ zOh_s9FeygixG2EK;wo4porPcg2)Yu220{m6lTU^dJ_9}@oFV)`_|>Pt9|S>GKqb@> z9wxLB9wVd(!-QuD&l7eLULm|mc%N{DaDwm&;d8=Qgs%zT5q=_g_rleZPynCZ-vV=W zjiVtX!Fx?mIO@iax^e$+v@b{$R|i~e2dijGC7%!eDt!}%Qb~TC_rM|snm3kknUbzf z+gcPeu0KMW&+nM)mrDLDxiPx#U8{V}_q-#e(*14)&Ok$f2H~D7?T>xA-?bH<*wj1b z1uVb+Uo-q}v8$4>rd<8NP_HW%wa364aaep^|HSrx-dXq*Z57e34RX24nbSHzx-YXS zvw25;eC_6!@>M#El8~zdD-O%d@PSTeykWB$4iAE9nG*|~Nc~4ErY;OdmRVzm=OW1` zEOX0j%(70+MZ!_&+%Gzlsdn!7fc;e=ixur%OqQ2_%K+56DAd6fy6T|F5S;5QeWIMJ zgm{sNa8VHuRo%`5B z8;MF_;0GB5`q?3YN-LRwB*e?a!0$0=piq)bC&dmWDKiU=5T$)!Iav}Zi(EeiJ%9*7 zVII*<%xIWiyu0GYNs^|6ATADIcfc44D9;9PI$#_MC^G>(9WcHRC_e{KR*i_NG^*II z8XHyRIThbgjbp0vk&54_#syWmq+&=jmTF3ihC`Z>)07<=9@LBvHDy-A^O|u{Q-0Sl ztQ*a`(xKx9-5A%EeL5c1jZbyu3mt#djo)=LV;jnwcYu$_yd|xUE{= zY8cFB>uh#9XNCuzU$MLoB5g;`aEE)+X3!i44^}aXOA(mK;388sd-zlKJcva)kJN{P zZ$SBIA!svD3G?3mTr^pbEx>|oC{)9ra{55kltiua6Mo;M z@j+cLkL&_(e`q<3o$NnL|4;B%n`h6D-?3e~L0TSwxB93XDf)k69b_N}E$k3n6x(J2 P4wU8oFt4A@|HAtl;!_Es literal 0 HcmV?d00001 diff --git a/src/mainboard/google/auron/variants/buddy/data.vbt b/src/mainboard/google/auron/variants/buddy/data.vbt new file mode 100644 index 0000000000000000000000000000000000000000..400ea48b112733b8145250082c3096722ae484aa GIT binary patch literal 4608 zcmdT{U2GIp6h3!mc6WAmW_CLi*sf4dq0wz^%XBG~kQ!&(ZQZR4-TqK20a;*|A1zSI zPiiz_)tX@Z+Xq6x5Nu*%ltj`Oqc0}d8$bJK>k2}{BSuSz&zk%z~HYK_+_Tb zQc|{}GJ2R4XI34Sj_-vQo@yV3?MydI_5(41u6AkO1mrI5**Dg}f(v(Y7tH zZ3_A}3!#wjTD9Y#7klggU`RTE1?P5AfaqQ51jx=^0Awg|9eG0mVK;!AjxcoIHDkN6 zH_Z7O&UelA++~1BW097C8Eb1_y{5zJO!Ops)0u&x;gOA-3NOF%>SP4|JWFq~hdk?z zIx``q)WWzJh4(}OJ`z{MTIoFe;z!Vx5Y!Rc2wQwIyzevM6T(-79|*tt6!@JW$O@>0 z8p3iyGvRSUiZDpnOxQ`-Pk52=8sQznNy7Vtj|ra=z9f82_>S-s!Fve)EC~hh+4&Zj z+gCX~gd}*o0Sc#F|0&n+ze@XpL~;9o+uP0xno`NF%1_QHH#5xm%l*9vs0*N%ijOFFOonaR^#G;!G!Z61(fz=5??!me+YG@s zz+Ya#^84?b;&+Q(g@je*>Ia58r&v^<25-b+@pb$Y+y8lI(bKe5M7uV~Hz7U z%$Cg7z4_5~TleHEG!`czR|8fY9x=m5+nw=-%|F4g5h@4HOxIbDgJ8 zlyfz)8(M_3JQQXZr~qH^U1LWV%+`8t;k#Ab{r2%J=H^0KhC*=ri(*Jhr7Bk(``+3m z?QqdwDB`81AvwFu;i|2~v$Tz}Wy~)N9!V|dAd?F%DPFD0TooiaT%F*mB(u8utSZ-5 zL9o2-+{Yf?L{tI;Kgb}^&khMxTFC??Azmg1evd&Nxss$hA+{??ky)sRDD4BwiIS+Z z$n=xb1Beh5W)a;&jfO#o1NIHcx^e#uNy9M^mjtjgUsNmZ_>7}AVon$o14W?a^k-!u&CMx(B@>9|ohMs?+|j;D0vtgd{f~)}#r%@OD}+-GCOnaf7$&ek60$<&qQonUUG~+= z80Hr-&fvA@!SYU5ki-0<$7`Bhi`8LIB{R9BZum?;)S5j-cP+v+lSTV$M5$CV4==S8 zr?Qb+%S5+a(`rgZzdeeAuaZ$jI|@@{)60pWkv|1M44$I>aaN~1lNIcTcN?ZI^iM7` zGbb098AJ$hUA4TGFqnRL2RxpYy5tz#0VpBD{ z_*3>gh($V<aO{+TIVhKbyjuLU{k`W^1JR##)FFv>B*`dGCBK8Z5{bU_mw%s^U*M zIZ!nvQ7im}KQLi@P;=$6{ow5lJqjadde77U6TH=C>9hTJt(R_+riJi&52cZ!|0mW% Z26E8Ej>BcKWg6gUSsn~^?ri=S*5BX?3ZVc1 literal 0 HcmV?d00001 diff --git a/src/mainboard/google/auron/variants/gandof/data.vbt b/src/mainboard/google/auron/variants/gandof/data.vbt new file mode 100644 index 0000000000000000000000000000000000000000..f95f4dd5dda8b8af7a2501712934149a3098f545 GIT binary patch literal 4608 zcmdT{ZEO>D7=QkE*Y z>z4p>j4f6>%!gK|_8iEMM~9j*Is7>O2K*2otH{`0#MwhMx2jm>C*Krg~B%eF;sOA4l)ri5Dh!KlSthjP^ET z%rwn5;_N`X%h*n3k+230ox$fuJ#v02*aDJ>~Waxh8ti_ARh| zO8Pnrp^)!NofDuJd+Y>YNH%~4r=O+-(Ywe=ke#~#$WY)m@`e(^ZUT25Vd%VT-gk3v zxRn-GhHj4BWr9d!k(PoP>+D*yw%h7StV{N%GeaYzW1F`WUVi1(=?Gl=l-^_ydBGcX zW7T3TAX%2q&Bj`#98VQ|*Z9W-}`waMuaE9<5;TN9*zYzpk0hLfs zc!1DGc$knP3=_5zo+9icyhwPB@DAa9!g0bUgwF|I5zZ36A^bq_9)xQpp#VO+zXj&% z8b?D&g14KYaMX<-b>sfav@b{$R|i~e2dijGC7%zjm(GQuRFWUzJ+O#@=8Yv>rlhOW zwid;V>yMD;^E>AHrIJ5OZj7#fuT{?SJ?}`Vbgx^1GtgL|LAd7%`FNOTVj0(EDUh`= zLGVo8KB4^Nym2eTe7vmxeu7#H{ZxEJxqCWn({2JN9n(aZ0!8-&)4iMF8E+c|-vEDk z0n6|I#|*z)?5ZTJDOW!*)SHS$-G|_fI4r*Izhe78?<`(VTSc^MgIun1=ClrwUYFUH z*}f+~zH$3=`6`_yNyycM6^9jO_;8mq-muvM?+t=!nG>~6q~XM>sf&Y=71r2$^O5AE zmbqg#W?84^BjG4?9TJ_%RJ#s&!2YU`#ftVWCdQ zWjCw{XSpxT&Qk$C@4Lbd*DkcKQ2f@|pXL4gF+Q%)9WI_jr=wKkisS#ic4-$}@E3}B zaal;tE_b*Zs);P?q~0>-mj#ccmir)62rVgIr^?(EBspA{;HD(A#-^+)H`G9|yzSh_ z?%zUG0s}wDAkfba2~=9i1SBC|CI)_wK_i8dWI8E!C`p-FXo4v11Ix*hNLl3iDd+)2 z2nq{`{=|%i>BajiZk!}(J_6#>0QLlok%01K0H*`Sy8&e;fTsh-w*lqH0LrQnQI#eY z`&DC$s_atnP1X2NRZggQPBkv7$|V&;nz39{S~VQfjGU(I(eQ|7e55I}8eY(hpETuH z4a2(8qAQ&`Zq|))U3p%|qq^~_u6&{6_quUeSFY-aK_eDax`SGa;3)_fS)qmwE*%ef zQl;%ZCaAW)!a}4y!IiXGD%X-ulzYlh924%$FcU=R7+Z?bLY*^14PA!>nlBQSm+m_= zRF(*S(w$Sy*PAnR-*yz0C52ZAry5LoB2_U=;b0_Wg~~;VR~EbMtJN`77BSA?wdcX| z&Q{Tf%A&_>nq7<4QBO59xvO#Xx%ALglQ&=_ScBIQq4TP)Lxv)Mj9*=-EvK< zDHZ+pC6;uVeDl89Q{ARTWx{8Fn-r|=@w~S1h227Zlvh{iA|7!9JI1`;U}?u R7T|DM?hW(i+59iOKL7z53ZVc1 literal 0 HcmV?d00001 diff --git a/src/mainboard/google/auron/variants/lulu/data.vbt b/src/mainboard/google/auron/variants/lulu/data.vbt new file mode 100644 index 0000000000000000000000000000000000000000..00bc088f52e6248b2fdee3d13473442a8cac5370 GIT binary patch literal 4608 zcmdT{U2GIp6h3!mc6WAmW_EX|uw9{^VguXSmg!O|AvMmn+qzp8y8W?Mf_A}O6|GPT zm>Nx3wI&$<_JJ5RM4FHoB+>N6=!*%y00{{pCK`Rw#wUY`F@^_2(DmGz=~7sP4gQ5Q z{q8yU%$e{0pSx`u>lwvVV&tK|Oa@)ag9&eh8>y_8p7h|zL^3g&nCQt2_HM?{VL3b! z{^J5bp0VX>hq-=3diVaqWNf$@QzH-ImOVRnO%~QA3;Uklzh?@wy=hE5_E=%EFuh}c zA&( z$-dsfE!lJ?F`6FSii5+LOphc+M*6n&WFE%s@L($4lOF9$YRcj`diP8{H@)kLC--Bl zw;AK6X|@q(2ijf6-aXS(?UlZ*@BfAN1&QM7fU9k14Mn-^^T8kGa}g+)<@<>hx7fLb4edbmVSJ(L)N^PHh8 z%6VGZ6)VbF?u@YWlz`9sF0w<*mRkMS@m(+O-}muxh4>S;OUJ&Z%x{eu(P{aGGUYsClJ`Cc@0QLlo(SY)30A~Zn+W}=RfTse+Hv#2` z0LrQnRh1?c2UKIbsywdZ>#Fg-svKAGoN6qn$^{ienz33_S~VQjjJ&4o*6^@qe4r`w z8h))AKWfUa8b)-ZMOQj?+@>3oy7H`!M|9(3UHMGM?{woAUAd$q290=7=?-cwf~P1f zuws}FE*%efTBWT#E~vJ?$U>w&!L_tms@IZElzYlh92aiRFc(DV7+;C8Vx2QX4P6HX znlBQSr|z3GRHq1j(w$Sy*PAnR-*6PwDTQYUCmYOoqBSwh;7~MVg(^vjXBIo{tFZHeWnw^W)F;6Ws`FP{li6Lk(`%CUxL}(^U_H9I6sbwBsXfMs> zq79abZn~z`luCYk6h&Vxqlk4E=ceZGCWaRN6#y}KO7`Wf&Ut2Q*bnbD&z&EdU2SIH zT~T2WA;4|b^47v&wpeF!vw1Tzf?N@nc3^Xe2ui;0k8H`H`4U~#DkE9 ZJhZa6;YYE39^g<#ZV&V7+59hRe*#hV384T0 literal 0 HcmV?d00001 diff --git a/src/mainboard/google/auron/variants/samus/data.vbt b/src/mainboard/google/auron/variants/samus/data.vbt new file mode 100644 index 0000000000000000000000000000000000000000..4b079bca8c6f5e746fc2bcd54bf7ec61685b57ef GIT binary patch literal 4608 zcmdT{U2GIp6h3!;c4uer%t=(JNHnZpxt7Dz}4i1m7w*6zH zwX9`ig!OTsan?6HK0J1KI902unhJ0c6o~*38N37t{8*#cO4+Mka?PAB^ zwZGykNEi+Rz;Ycts~iVq-hmM&aGmiNGK5_RUUh^pr?2_C>$_0R*I2%3spTOZM4XFM z3TAynW7EcFtF^r&-qqdHH!zskwmtpMyYEd#;O+(N$)56}9(7_ur&Dh z!AsH%{OV(%t3ik&8W2NX1(Li&_zKjqqe zw=gbHRJZiI<)TS1t7fxaFWk#s3qv-myue3bAp@=(X?L08ZrN>@qS)is2e9Ppn{eyd ztS^bxdVC(=TfNF--jQtfN!R>WAezQWxaW%T`4D+@EiZGDMs2Z!AdfBYkZU=w+|Mv? z&z1k)ffhj*CLd90o($WxTLH3XG!Z61)qOy8&o+3&Qv-ny!I#^>T>p-ssSmI)%6S?|OUuUsi9%P!a9ipyaZgIjIA5 zck~SP?A$jz^778T!v$8>#35AzRtu~*!$;k#IBZtIiC!=*bF|2rXW6-DC+2!1>#f9z zc}x67%Y1FR-m)&vTf#ADJR&-aNgI#IVBadJk&GS1sCoEZ20%+K2Q*6KF~{OYTIHt9Ex`_(BwyX-f9@T>SRVyg#qQ-Wr?xO4?YMiF(Im)h4V~(mfDGO>wxu#ZYtWPsinz~P8$28+}O`X=* zbtYtH*V?b9i6d&Q6Es716q|Jr-eC^ z4&lMY}a)PYYwn zPhy-wS1CN5McP})EMm>+snO|m$WX;w0U(2%u`g#jB~KO*51&;|&Gt@~n>{Dj zi3HHr~o! z2Qh=^5yz1BHres8{Mi&Xro#uCYOF-f!d{3Fuo*Cgc~*|PUv17=ec zTHqDlzjN=Qab{oq5BD3Oz<&O<8=urtdFB9kx`G=ZalUH?|4%HuwMF`3`$Op2`=ojm ke9(cz=*0gMTcHP1P)&}*4Y76_;Al>s40Y*h{ui~s0CBSCivR!s literal 0 HcmV?d00001 From ac247b64e83ce7ba8fc0acf8de116871e3b0e583 Mon Sep 17 00:00:00 2001 From: Matt DeVillier Date: Sat, 14 Dec 2019 11:54:58 -0600 Subject: [PATCH 0699/1242] mb/google/slippy: Update VBT file Update VBT using file extracted from VGA BIOS from stock firmware image using intelvbttool, zero-padded to 0x11ff bytes to make the Intel BMP editor happy. Change-Id: I9f53e80305ec8de78a3d5c930224b394b5c8618a Signed-off-by: Matt DeVillier Reviewed-on: https://review.coreboot.org/c/coreboot/+/37732 Reviewed-by: Angel Pons Tested-by: build bot (Jenkins) --- src/mainboard/google/slippy/data.vbt | Bin 4399 -> 4608 bytes 1 file changed, 0 insertions(+), 0 deletions(-) diff --git a/src/mainboard/google/slippy/data.vbt b/src/mainboard/google/slippy/data.vbt index 3b0e45a13ce79f150c963b248ed6e10efae084e0..e765e99e9474ef48efc302c80df3458fb2362dbc 100644 GIT binary patch delta 25 fcmZ3l)S$9JfYD Date: Sat, 14 Dec 2019 12:17:24 -0600 Subject: [PATCH 0700/1242] mb/google/beltino: Add VBTs for all variants Add VBTs for beltino variants, extracted from VGA BIOS from stock firmware images using intelvbttool, zero-padded to 0x11ff bytes to make the Intel BMP editor happy. Use a common VBT for all except monroe, since it differs as it has a built-in display (being a Chromebase vs Chromebox). Change-Id: I82afb20a5648695c2cd568384a26839ab28be3da Signed-off-by: Matt DeVillier Reviewed-on: https://review.coreboot.org/c/coreboot/+/37733 Tested-by: build bot (Jenkins) Reviewed-by: Angel Pons --- src/mainboard/google/beltino/Kconfig | 6 ++++++ src/mainboard/google/beltino/data.vbt | Bin 0 -> 4608 bytes .../google/beltino/variants/monroe/data.vbt | Bin 0 -> 4608 bytes 3 files changed, 6 insertions(+) create mode 100644 src/mainboard/google/beltino/data.vbt create mode 100644 src/mainboard/google/beltino/variants/monroe/data.vbt diff --git a/src/mainboard/google/beltino/Kconfig b/src/mainboard/google/beltino/Kconfig index 01e0cbf35b..f50d49c550 100644 --- a/src/mainboard/google/beltino/Kconfig +++ b/src/mainboard/google/beltino/Kconfig @@ -9,6 +9,7 @@ config BOARD_GOOGLE_BASEBOARD_BELTINO select HAVE_ACPI_TABLES select HAVE_OPTION_TABLE select HAVE_ACPI_RESUME + select INTEL_GMA_HAVE_VBT select MAINBOARD_HAS_CHROMEOS select MAINBOARD_HAS_LIBGFXINIT select MAINBOARD_HAS_LPC_TPM @@ -51,6 +52,11 @@ config VGA_BIOS_FILE string default "pci8086,0406.rom" +# Override the default variant behavior, since the data.vbt is the same +# for all variants except monroe +config INTEL_GMA_VBT_FILE + default "src/mainboard/$(MAINBOARDDIR)/data.vbt" if !BOARD_GOOGLE_MONROE + config MAINBOARD_SMBIOS_MANUFACTURER string default "GOOGLE" diff --git a/src/mainboard/google/beltino/data.vbt b/src/mainboard/google/beltino/data.vbt new file mode 100644 index 0000000000000000000000000000000000000000..3195b151e40df228e4d6a797ee1523660cec132f GIT binary patch literal 4608 zcmds3U2GIp6h3!nc6WAmW`Cv?whPo-XkfSWXWC*ZwZ_?YTX)O0-F8c57eX7@s6_Eh zzB%WfIrGi^IrrSD9Bdn)kx*iDM=VB7Nr4KgcO35vr7hZ<*cJ{AgtoQCdfPYBw_yo@ z_sRu;6d_BbhWhmzqWdP&!-4)FjU+bH?vWk4htqZ8^!T2Mkx?3NkJ8Z2o$2B9*!GEZ ziY5l{3sJ@?i){yX52t9)fxSD@V=a^sVKl8@SKGLb(t5Q{U0>Ir);BV{MQv2Rg#CI6sc|k7x3p?);m$}`EZ#pbIJ9MJ=7}c{Px;~UsYSZvCMsNUl*2d| zfE;ImX|5T1_*uv~D17Mfz&XTuMA9z6NxK5?AZ8KYA%3=t@Ed{?M351FL?xmY(TwOq z3?Lpt>_Uto4kDgHWD&;^ClRL*?;<`xoI#vJ%pq(C;BwxQ0lVJs3^BFW(BR?W*&t+2 znEn%{-*M4cKGD=pQ!g_3MP2#4-40jspZg%67w%y_(2xPAmxN8Gh^b?`=D4`o9ze}f zYRGKo^Nu7o8}Pbyckxq}^M>T}x4Y&11S&E(2y@h&-2{+-U*=#EM3)1I+qMPv*lNIi6dZ*GEPVeTGaP2I zE0WNQ)z1_~(vx|*iY{XRI^x7b>U8svXn{|_Oeg4(j(6M<>sOi$|1kRg}mBeKd4M|Eu5+9W4VM%#G5?_<( zN0Rc5B>o^#yR4MS;wqU&W#s``Ow07Bth^$NZ^-mBS@~WT&&$;9QYu{HS{LneDLY-_ zUKf4NrM&JE-*VBfUCNIx@fVj|b&=0l=19hin+;Q17?Ut1hb)q=FA)!Ft9uQerwi8- zcY(PxC^uxeIYZ7(p?+vN4P;7<87gl&WWo7DkyyFCIm5zj&331;6WMw*hSnR7VqqCz zyITM2kS4AEq8KJ=pWmZ-3WbDK1HDui$*{2SFb11G51MVJh(0VVRICo^^-~(O7BiC% zR}4<~LAlzQHP^z2Gnv&-5bR1Z^Kh^>n@jr3HIk$@;)y zIx>d8n3Fn#Y%o}95u>=^hg_U4RVB5Zy`|3sm&N^veaP6G^?bPT-n6u2eEXYgw4s`- zYr%nAXTTC>yZOEdYLLu8Nz&u-vbT&rU^PXNiad62o3OR}!Pezj14GkYv-rnJw8n~zg z@oj!PZ{EK7-OQVrH**ccT|+Dp-}uzJWRiK31p`)9pTc*!boFi6IMNdzijQ<9H*~LO z)369E?Z#z*EFp_%TkD#RXU6imZDV7*ql2;X_V?G)JvRPI{`u|C?Pk&L7;7^Oqq)s! zZDoBscIQS}_gH?sg~dll*`V#Siw)*>1lA-l4LF5x0zkb8-%fb3V0MZ0yi+&9 zse=F)GoWeyXsv4q0QejSjWFy4fC=9@4r@IJ4zP_QgrN@D%w2^ejw+dI~Fnq57;iT-42aA-Kac}wAqy>Cv2;o8Xsx}*{Vt_LHK z=c90p=ipPm1D+6O;8>8s*Fg;~ATA+B0wNp_=4B|(`uK@{uM{uG96j6s*j%Y@# zLG&RuBA!NUN9;trhIk9{0pc*?IN~$JDa2QZvxp0bpAr6-;F`r10H+M4K)kZrEkP6D z{TLLEc=jWnJ$S{PKFKR(uUug83z{q|5P%!j`4Cu^_?X=T6B#hPq{m}QcxBQlc|PUU zhp@DlRNAXsRxpFrHhk{gTRLm6c~>m!LD%FnP+!17c>9Xk;~~EBrFL180&2H9aK8MV z9ZD_dmD?HS?WOXcJJ1^F$3((wos$uVb`ya0rNYAmNNNy>>fa16_?w~XT?m#Yu=M-? zni6!AU8Q{0V#!md&SIXg*B%9b*sTOQ=Z&|Q_w&o5^|(}cCpU=pE_B40Q~{E`sgcyy z9l6mbx4xLGu(CJ-**Y-eu)+xKYj?>)Mk5>=0K+uKYg|j@lT{OQ1K|~B`p~>3@wjPh zn{G4B)AN>46x#RjZZK*49v?WT3TmY2tYXys?vX?5qEH8a;8O=h!oYoI@Q8AsCUR2? z+bj>CgIP?#vw^E*U(J70a|2b$+p?Cl!^L2s$mW)6VrH4!CQ^xI>1xn`kf6x<1X}tn z5lze#;7p#@GV74_epwol*{ibto-7@d*%z{YUY354*$r9Os1&Bmr1~J0wota0>IbNFl(KKA zevwLZl=&4sq)5vYmQeJ~ij-B@JBofpkv>+~IYs|TkuE7rRduFHjVep2`ZiS>RoQ-3 z|45Zis_c7J|3#Iqs7m7%p}@_NLN#tST+(8m;*v~r)G4nL4NG6uN<2@?=Mr~;w=)=@ z=I+igRmGq+y@W*zwQhtW?Rz+k7YfBt^LJ+`-`4i-ba$dX-!?<%9Y;}~2JBt!+&bul zFI*AB1RDrzrdCQMb~bQQb%hM&iN|Je?xoc9Pgl@~@1mBiuomf}<<95D^%rC6Lzp@ Date: Sun, 15 Dec 2019 13:38:01 +0100 Subject: [PATCH 0701/1242] superio/ite: remove unused stdint.h include from header files Change-Id: Ica1c9f0c92886a081ab69612174a8d1d467b0713 Signed-off-by: Felix Held Reviewed-on: https://review.coreboot.org/c/coreboot/+/37739 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Rudolph --- src/superio/ite/it8783ef/it8783ef.h | 2 -- src/superio/ite/it8786e/it8786e.h | 2 -- 2 files changed, 4 deletions(-) diff --git a/src/superio/ite/it8783ef/it8783ef.h b/src/superio/ite/it8783ef/it8783ef.h index bdaea5a3de..b2b7edced5 100644 --- a/src/superio/ite/it8783ef/it8783ef.h +++ b/src/superio/ite/it8783ef/it8783ef.h @@ -31,6 +31,4 @@ #define IT8783EF_SP6 0x0b /* COM6 */ #define IT8783EF_CIR 0x0c /* Consumer IR */ -#include - #endif /* SUPERIO_ITE_IT8783EF_H */ diff --git a/src/superio/ite/it8786e/it8786e.h b/src/superio/ite/it8786e/it8786e.h index 5f11b63690..b73b71d5b3 100644 --- a/src/superio/ite/it8786e/it8786e.h +++ b/src/superio/ite/it8786e/it8786e.h @@ -31,6 +31,4 @@ #define IT8786E_SP5 0x0b /* COM5 */ #define IT8786E_SP6 0x0c /* COM6 */ -#include - #endif /* SUPERIO_ITE_IT8786E_H */ From 41956b574212224127ba393f6e65be88de6f3f21 Mon Sep 17 00:00:00 2001 From: Yu-Ping Wu Date: Mon, 2 Dec 2019 11:11:53 +0800 Subject: [PATCH 0702/1242] libpayload: Implement reading from CBMEM console To support showing CBMEM logs on recovery screen, add a function cbmem_console_snapshot() to copy the CBMEM console to an allocated buffer. Non-printable characters are automatically replaced with '?' to ensure the returned string is printable. BRANCH=none BUG=b:146105976 TEST=emerge-nami libpayload Change-Id: Ie324055f5fd8276f1d833fc9d04f60a792dbb9f6 Signed-off-by: Yu-Ping Wu Reviewed-on: https://review.coreboot.org/c/coreboot/+/37667 Tested-by: build bot (Jenkins) Reviewed-by: Hung-Te Lin --- payloads/libpayload/drivers/cbmem_console.c | 46 +++++++++++++++++++++ payloads/libpayload/include/libpayload.h | 7 ++++ 2 files changed, 53 insertions(+) diff --git a/payloads/libpayload/drivers/cbmem_console.c b/payloads/libpayload/drivers/cbmem_console.c index 9435e1ca9f..62aabfb9ca 100644 --- a/payloads/libpayload/drivers/cbmem_console.c +++ b/payloads/libpayload/drivers/cbmem_console.c @@ -75,3 +75,49 @@ void cbmem_console_write(const void *buffer, size_t count) do_write(buffer, count); } + +char *cbmem_console_snapshot(void) +{ + const struct cbmem_console *console_p = cbmem_console_p; + char *console_c; + uint32_t size, cursor, overflow; + + if (!console_p) { + printf("ERROR: No cbmem console found in coreboot table\n"); + return NULL; + } + + cursor = console_p->cursor & CURSOR_MASK; + overflow = console_p->cursor & OVERFLOW; + if (!overflow && cursor < console_p->size) + size = cursor; + else + size = console_p->size; + + console_c = malloc(size + 1); + if (!console_c) { + printf("ERROR: Not enough memory for console (size = %u)\n", + size); + return NULL; + } + console_c[size] = '\0'; + + if (overflow) { + if (cursor >= size) { + printf("ERROR: CBMEM console struct is corrupted\n"); + return NULL; + } + memcpy(console_c, console_p->body + cursor, size - cursor); + memcpy(console_c + size - cursor, console_p->body, cursor); + } else { + memcpy(console_c, console_p->body, size); + } + + /* Slight memory corruption may occur between reboots and give us a few + unprintable characters like '\0'. Replace them with '?' on output. */ + for (cursor = 0; cursor < size; cursor++) + if (!isprint(console_c[cursor]) && !isspace(console_c[cursor])) + console_c[cursor] = '?'; + + return console_c; +} diff --git a/payloads/libpayload/include/libpayload.h b/payloads/libpayload/include/libpayload.h index 934c368e5c..4b6a250f28 100644 --- a/payloads/libpayload/include/libpayload.h +++ b/payloads/libpayload/include/libpayload.h @@ -313,6 +313,13 @@ void video_printf(int foreground, int background, enum video_printf_align align, */ void cbmem_console_init(void); void cbmem_console_write(const void *buffer, size_t count); +/** + * Take a snapshot of the CBMEM memory console. This function will allocate a + * range of memory. Callers must free the returned buffer by themselves. + * + * @return The allocated buffer on success, NULL on failure. + */ +char *cbmem_console_snapshot(void); /** @} */ /* drivers/option.c */ From 9db39879a8b45558db267614dc42eb6bf3d8fd58 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ky=C3=B6sti=20M=C3=A4lkki?= Date: Fri, 13 Dec 2019 18:11:05 +0200 Subject: [PATCH 0703/1242] soc/amd,{agesa,pi}/hudson: Have do_board_reset in all stages MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Change-Id: I38a721c359ab7761c5a3ea79da0c159fd7f58970 Signed-off-by: Kyösti Mälkki Reviewed-on: https://review.coreboot.org/c/coreboot/+/37711 Reviewed-by: Mike Banon Reviewed-by: Marshall Dawson Tested-by: build bot (Jenkins) --- src/soc/amd/picasso/Makefile.inc | 5 ++--- src/soc/amd/stoneyridge/Makefile.inc | 6 ++---- src/southbridge/amd/agesa/hudson/Makefile.inc | 3 ++- src/southbridge/amd/cimx/sb800/Makefile.inc | 4 ++-- src/southbridge/amd/pi/hudson/Makefile.inc | 4 ++-- 5 files changed, 10 insertions(+), 12 deletions(-) diff --git a/src/soc/amd/picasso/Makefile.inc b/src/soc/amd/picasso/Makefile.inc index 76a4d70a8a..4492653713 100644 --- a/src/soc/amd/picasso/Makefile.inc +++ b/src/soc/amd/picasso/Makefile.inc @@ -41,7 +41,6 @@ romstage-y += i2c.c romstage-y += romstage.c romstage-y += gpio.c romstage-y += pmutil.c -romstage-y += reset.c romstage-y += smbus.c romstage-y += memmap.c romstage-$(CONFIG_PICASSO_UART) += uart.c @@ -52,7 +51,6 @@ romstage-$(CONFIG_HAVE_SMI_HANDLER) += smi_util.c verstage-y += gpio.c verstage-y += i2c.c verstage-y += pmutil.c -verstage-y += reset.c verstage-$(CONFIG_PICASSO_UART) += uart.c verstage-y += tsc_freq.c @@ -71,7 +69,6 @@ ramstage-y += gpio.c ramstage-y += southbridge.c ramstage-y += northbridge.c ramstage-y += pmutil.c -ramstage-y += reset.c ramstage-y += acp.c ramstage-y += sata.c ramstage-y += sm.c @@ -84,6 +81,8 @@ ramstage-y += usb.c ramstage-y += tsc_freq.c ramstage-y += finalize.c +all-y += reset.c + smm-y += smihandler.c smm-y += smi_util.c smm-y += tsc_freq.c diff --git a/src/soc/amd/stoneyridge/Makefile.inc b/src/soc/amd/stoneyridge/Makefile.inc index 15216b7934..e6cfa12ac4 100644 --- a/src/soc/amd/stoneyridge/Makefile.inc +++ b/src/soc/amd/stoneyridge/Makefile.inc @@ -45,7 +45,6 @@ bootblock-y += i2c.c bootblock-y += enable_usbdebug.c bootblock-y += monotonic_timer.c bootblock-y += pmutil.c -bootblock-y += reset.c bootblock-y += tsc_freq.c bootblock-y += southbridge.c bootblock-$(CONFIG_HAVE_SMI_HANDLER) += smi_util.c @@ -57,7 +56,6 @@ romstage-y += enable_usbdebug.c romstage-y += gpio.c romstage-y += monotonic_timer.c romstage-y += pmutil.c -romstage-y += reset.c romstage-y += smbus.c romstage-y += smbus_spd.c romstage-y += memmap.c @@ -70,7 +68,6 @@ verstage-y += gpio.c verstage-y += i2c.c verstage-y += monotonic_timer.c verstage-y += pmutil.c -verstage-y += reset.c verstage-$(CONFIG_STONEYRIDGE_UART) += uart.c verstage-y += tsc_freq.c @@ -92,7 +89,6 @@ ramstage-y += monotonic_timer.c ramstage-y += southbridge.c ramstage-y += northbridge.c ramstage-y += pmutil.c -ramstage-y += reset.c ramstage-y += sata.c ramstage-y += sm.c ramstage-y += smbus.c @@ -104,6 +100,8 @@ ramstage-y += usb.c ramstage-y += tsc_freq.c ramstage-y += finalize.c +all-y += reset.c + smm-y += monotonic_timer.c smm-y += smihandler.c smm-y += smi_util.c diff --git a/src/southbridge/amd/agesa/hudson/Makefile.inc b/src/southbridge/amd/agesa/hudson/Makefile.inc index 5c921280f7..be4ea26bee 100644 --- a/src/southbridge/amd/agesa/hudson/Makefile.inc +++ b/src/southbridge/amd/agesa/hudson/Makefile.inc @@ -15,7 +15,6 @@ ramstage-y += pcie.c ramstage-y += sd.c ramstage-$(CONFIG_HAVE_ACPI_TABLES) += fadt.c -ramstage-y += reset.c ifneq ($(CONFIG_ROMCC_BOOTBLOCK),y) bootblock-y += bootblock.c @@ -36,6 +35,8 @@ postcar-y += ramtop.c romstage-y += imc.c ramstage-y += imc.c +all-y += reset.c + smm-y += smihandler.c smi_util.c ramstage-$(CONFIG_HAVE_SMI_HANDLER) += smi.c smi_util.c diff --git a/src/southbridge/amd/cimx/sb800/Makefile.inc b/src/southbridge/amd/cimx/sb800/Makefile.inc index ccb3a2a744..5a68d0732e 100644 --- a/src/southbridge/amd/cimx/sb800/Makefile.inc +++ b/src/southbridge/amd/cimx/sb800/Makefile.inc @@ -23,11 +23,11 @@ endif romstage-y += cfg.c romstage-y += early.c romstage-y += smbus.c smbus_spd.c -romstage-y += reset.c ramstage-y += cfg.c ramstage-y += late.c -ramstage-y += reset.c + +all-y += reset.c ramstage-$(CONFIG_SB800_MANUAL_FAN_CONTROL) += fan.c ramstage-$(CONFIG_SB800_IMC_FAN_CONTROL) += fan.c diff --git a/src/southbridge/amd/pi/hudson/Makefile.inc b/src/southbridge/amd/pi/hudson/Makefile.inc index 615fc048d6..4aa9babafe 100644 --- a/src/southbridge/amd/pi/hudson/Makefile.inc +++ b/src/southbridge/amd/pi/hudson/Makefile.inc @@ -42,7 +42,6 @@ romstage-y += smbus_spd.c romstage-$(CONFIG_HUDSON_UART) += uart.c verstage-y += early_setup.c -verstage-y += reset.c verstage-$(CONFIG_HUDSON_UART) += uart.c ramstage-y += enable_usbdebug.c @@ -55,7 +54,6 @@ ramstage-$(CONFIG_HUDSON_IMC_FWM) += imc.c ramstage-y += lpc.c ramstage-y += pci.c ramstage-y += pcie.c -ramstage-y += reset.c ramstage-y += sata.c ramstage-y += sd.c ramstage-y += sm.c @@ -64,6 +62,8 @@ ramstage-$(CONFIG_HAVE_SMI_HANDLER) += smi_util.c ramstage-$(CONFIG_HUDSON_UART) += uart.c ramstage-y += usb.c +all-y += reset.c + smm-y += smihandler.c smm-y += smi_util.c From bbe66e4555daabff290e800afe193b842c0b2c30 Mon Sep 17 00:00:00 2001 From: Felix Held Date: Sun, 15 Dec 2019 14:03:24 +0100 Subject: [PATCH 0704/1242] superio/ite/it8728f: remove unused LDN selection register define Change-Id: Ie7a8af46a59c36b0dd62f227a6b53918c8fde7b8 Signed-off-by: Felix Held Reviewed-on: https://review.coreboot.org/c/coreboot/+/37742 Reviewed-by: Patrick Rudolph Tested-by: build bot (Jenkins) --- src/superio/ite/it8728f/it8728f.h | 1 - 1 file changed, 1 deletion(-) diff --git a/src/superio/ite/it8728f/it8728f.h b/src/superio/ite/it8728f/it8728f.h index 19a04de90a..3ce1cfb9df 100644 --- a/src/superio/ite/it8728f/it8728f.h +++ b/src/superio/ite/it8728f/it8728f.h @@ -30,7 +30,6 @@ /* Global configuration registers. */ #define IT8728F_CONFIG_REG_CC 0x02 /* Configure Control (write-only). */ -#define IT8728F_CONFIG_REG_LDN 0x07 /* Logical Device Number. */ #define IT8728F_CONFIG_REG_CHIPVERS 0x22 /* Chip version */ #define IT8728F_CONFIG_REG_CLOCKSEL 0x23 /* Clock Selection. */ #define IT8728F_CONFIG_REG_SWSUSP 0x24 /* Software Suspend, Flash I/F. 'Special register' */ From bf14c0050c694df862b766096e49cf1a6ab42f3a Mon Sep 17 00:00:00 2001 From: Aamir Bohra Date: Fri, 6 Dec 2019 19:39:36 +0530 Subject: [PATCH 0705/1242] soc/intel/tigerlake: Add FSP header and Fsp.fd file path for Jasper Lake Change-Id: I66d48206a4c1c31802e85c08ab935f81f10aadbc Signed-off-by: Aamir Bohra Reviewed-on: https://review.coreboot.org/c/coreboot/+/37558 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh Reviewed-by: Maulik V Vaghela Reviewed-by: Frans Hendriks --- src/soc/intel/tigerlake/Kconfig | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/src/soc/intel/tigerlake/Kconfig b/src/soc/intel/tigerlake/Kconfig index 652c3a30c6..7bb533ab71 100644 --- a/src/soc/intel/tigerlake/Kconfig +++ b/src/soc/intel/tigerlake/Kconfig @@ -189,11 +189,13 @@ config CBFS_SIZE config FSP_HEADER_PATH string "Location of FSP headers" - default "src/vendorcode/intel/fsp/fsp2_0/tigerlake/" + default "src/vendorcode/intel/fsp/fsp2_0/tigerlake/" if SOC_INTEL_TIGERLAKE + default "src/vendorcode/intel/fsp/fsp2_0/jasperlake/" if SOC_INTEL_JASPERLAKE config FSP_FD_PATH string depends on FSP_USE_REPO - default "3rdparty/fsp/TigerLakeFspBinPkg/Fsp.fd" + default "3rdparty/fsp/TigerLakeFspBinPkg/Fsp.fd" if SOC_INTEL_TIGERLAKE + default "3rdparty/fsp/JasperLakeFspBinPkg/Fsp.fd" if SOC_INTEL_JASPERLAKE endif From 03f78b069d4f4fe0aa2a3ec67117e0c478da3b72 Mon Sep 17 00:00:00 2001 From: Aamir Bohra Date: Fri, 6 Dec 2019 19:40:47 +0530 Subject: [PATCH 0706/1242] vendorcode/intel/fsp: Add Jasper Lake FSP headers for FSP v1433 The FSP-M/S/T headers added are generated as per FSP v1433. Change-Id: Iacb44204c3f7220a20ab3edc2163c97188014bbf Signed-off-by: Aamir Bohra Reviewed-on: https://review.coreboot.org/c/coreboot/+/37559 Reviewed-by: Maulik V Vaghela Reviewed-by: Ronak Kanabar Tested-by: build bot (Jenkins) --- .../jasperlake/FirmwareVersionInfoHob.h | 68 ++ .../intel/fsp/fsp2_0/jasperlake/FspUpd.h | 48 ++ .../intel/fsp/fsp2_0/jasperlake/FspmUpd.h | 637 +++++++++++++++++ .../intel/fsp/fsp2_0/jasperlake/FspsUpd.h | 656 ++++++++++++++++++ .../intel/fsp/fsp2_0/jasperlake/FsptUpd.h | 186 +++++ .../intel/fsp/fsp2_0/jasperlake/MemInfoHob.h | 274 ++++++++ 6 files changed, 1869 insertions(+) create mode 100644 src/vendorcode/intel/fsp/fsp2_0/jasperlake/FirmwareVersionInfoHob.h create mode 100644 src/vendorcode/intel/fsp/fsp2_0/jasperlake/FspUpd.h create mode 100644 src/vendorcode/intel/fsp/fsp2_0/jasperlake/FspmUpd.h create mode 100644 src/vendorcode/intel/fsp/fsp2_0/jasperlake/FspsUpd.h create mode 100644 src/vendorcode/intel/fsp/fsp2_0/jasperlake/FsptUpd.h create mode 100644 src/vendorcode/intel/fsp/fsp2_0/jasperlake/MemInfoHob.h diff --git a/src/vendorcode/intel/fsp/fsp2_0/jasperlake/FirmwareVersionInfoHob.h b/src/vendorcode/intel/fsp/fsp2_0/jasperlake/FirmwareVersionInfoHob.h new file mode 100644 index 0000000000..373c167186 --- /dev/null +++ b/src/vendorcode/intel/fsp/fsp2_0/jasperlake/FirmwareVersionInfoHob.h @@ -0,0 +1,68 @@ +/** @file + Header file for Firmware Version Information + + @copyright + Copyright (c) 2019, Intel Corporation. All rights reserved.
+ + This program and the accompanying materials are licensed and made available under + the terms and conditions of the BSD License which accompanies this distribution. + The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#ifndef _FIRMWARE_VERSION_INFO_HOB_H_ +#define _FIRMWARE_VERSION_INFO_HOB_H_ + +#include +#include +#include + +#pragma pack(1) +/// +/// Firmware Version Structure +/// +typedef struct { + UINT8 MajorVersion; + UINT8 MinorVersion; + UINT8 Revision; + UINT16 BuildNumber; +} FIRMWARE_VERSION; + +/// +/// Firmware Version Information Structure +/// +typedef struct { + UINT8 ComponentNameIndex; ///< Offset 0 Index of Component Name + UINT8 VersionStringIndex; ///< Offset 1 Index of Version String + FIRMWARE_VERSION Version; ///< Offset 2-6 Firmware version +} FIRMWARE_VERSION_INFO; + +#ifndef __SMBIOS_STANDARD_H__ +/// +/// The Smbios structure header. +/// +typedef struct { + UINT8 Type; + UINT8 Length; + UINT16 Handle; +} SMBIOS_STRUCTURE; +#endif + +/// +/// Firmware Version Information HOB Structure +/// +typedef struct { + EFI_HOB_GUID_TYPE Header; ///< Offset 0-23 The header of FVI HOB + SMBIOS_STRUCTURE SmbiosData; ///< Offset 24-27 The SMBIOS header of FVI HOB + UINT8 Count; ///< Offset 28 Number of FVI elements included. +/// +/// FIRMWARE_VERSION_INFO structures followed by the null terminated string buffer +/// +} FIRMWARE_VERSION_INFO_HOB; +#pragma pack() + +#endif // _FIRMWARE_VERSION_INFO_HOB_H_ diff --git a/src/vendorcode/intel/fsp/fsp2_0/jasperlake/FspUpd.h b/src/vendorcode/intel/fsp/fsp2_0/jasperlake/FspUpd.h new file mode 100644 index 0000000000..b28ba78ea0 --- /dev/null +++ b/src/vendorcode/intel/fsp/fsp2_0/jasperlake/FspUpd.h @@ -0,0 +1,48 @@ +/** @file + +Copyright (c) 2019, Intel Corporation. All rights reserved.
+ +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + +* Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. +* Redistributions in binary form must reproduce the above copyright notice, this + list of conditions and the following disclaimer in the documentation and/or + other materials provided with the distribution. +* Neither the name of Intel Corporation nor the names of its contributors may + be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF + THE POSSIBILITY OF SUCH DAMAGE. + + This file is automatically generated. Please do NOT modify !!! + +**/ + +#ifndef __FSPUPD_H__ +#define __FSPUPD_H__ + +#include + +#pragma pack(1) + +#define FSPT_UPD_SIGNATURE 0x545F4450554C534A /* 'JSLUPD_T' */ + +#define FSPM_UPD_SIGNATURE 0x4D5F4450554C534A /* 'JSLUPD_M' */ + +#define FSPS_UPD_SIGNATURE 0x535F4450554C534A /* 'JSLUPD_S' */ + +#pragma pack() + +#endif diff --git a/src/vendorcode/intel/fsp/fsp2_0/jasperlake/FspmUpd.h b/src/vendorcode/intel/fsp/fsp2_0/jasperlake/FspmUpd.h new file mode 100644 index 0000000000..cce959cb15 --- /dev/null +++ b/src/vendorcode/intel/fsp/fsp2_0/jasperlake/FspmUpd.h @@ -0,0 +1,637 @@ +/** @file + +Copyright (c) 2019, Intel Corporation. All rights reserved.
+ +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + +* Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. +* Redistributions in binary form must reproduce the above copyright notice, this + list of conditions and the following disclaimer in the documentation and/or + other materials provided with the distribution. +* Neither the name of Intel Corporation nor the names of its contributors may + be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF + THE POSSIBILITY OF SUCH DAMAGE. + + This file is automatically generated. Please do NOT modify !!! + +**/ + +#ifndef __FSPMUPD_H__ +#define __FSPMUPD_H__ + +#include + +#pragma pack(1) + + +#include + +/// +/// The ChipsetInit Info structure provides the information of ME ChipsetInit CRC and BIOS ChipsetInit CRC. +/// +typedef struct { + UINT8 Revision; ///< Chipset Init Info Revision + UINT8 Rsvd[3]; ///< Reserved + UINT16 MeChipInitCrc; ///< 16 bit CRC value of MeChipInit Table + UINT16 BiosChipInitCrc; ///< 16 bit CRC value of PchChipInit Table +} CHIPSET_INIT_INFO; + + +/** Fsp M Configuration +**/ +typedef struct { + +/** Offset 0x0040 - Reserved +**/ + UINT8 Reserved0[8]; + +/** Offset 0x0048 - SPD Data Length + Length of SPD Data + 0x100:256 Bytes, 0x200:512 Bytes +**/ + UINT16 MemorySpdDataLen; + +/** Offset 0x004A - Reserved +**/ + UINT8 Reserved1[2]; + +/** Offset 0x004C - Memory SPD Pointer Channel 0 Dimm 0 + Pointer to SPD data, will be used only when SpdAddressTable SPD Address are marked as 00 +**/ + UINT32 MemorySpdPtr00; + +/** Offset 0x0050 - Reserved +**/ + UINT8 Reserved2[4]; + +/** Offset 0x0054 - Memory SPD Pointer Channel 1 Dimm 0 + Pointer to SPD data, will be used only when SpdAddressTable SPD Address are marked as 00 +**/ + UINT32 MemorySpdPtr10; + +/** Offset 0x0058 - Reserved +**/ + UINT8 Reserved3[4]; + +/** Offset 0x005C - Dq Byte Map CH0 + Dq byte mapping between CPU and DRAM, Channel 0: board-dependent +**/ + UINT8 DqByteMapCh0[12]; + +/** Offset 0x0068 - Dq Byte Map CH1 + Dq byte mapping between CPU and DRAM, Channel 1: board-dependent +**/ + UINT8 DqByteMapCh1[12]; + +/** Offset 0x0074 - Dqs Map CPU to DRAM CH 0 + Set Dqs mapping relationship between CPU and DRAM, Channel 0: board-dependent +**/ + UINT8 DqsMapCpu2DramCh0[8]; + +/** Offset 0x007C - Dqs Map CPU to DRAM CH 1 + Set Dqs mapping relationship between CPU and DRAM, Channel 1: board-dependent +**/ + UINT8 DqsMapCpu2DramCh1[8]; + +/** Offset 0x0084 - RcompResister settings + Indicates RcompReister settings: Board-dependent +**/ + UINT16 RcompResistor[3]; + +/** Offset 0x008A - RcompTarget settings + RcompTarget settings: board-dependent +**/ + UINT16 RcompTarget[5]; + +/** Offset 0x0094 - Dqs Pins Interleaved Setting + Indicates DqPinsInterleaved setting: board-dependent + $EN_DIS +**/ + UINT8 DqPinsInterleaved; + +/** Offset 0x0095 - VREF_CA + CA Vref routing: board-dependent + 0:VREF_CA goes to both CH_A and CH_B, 1: VREF_CA to CH_A and VREF_DQ_A to CH_B, + 2:VREF_CA to CH_A and VREF_DQ_B to CH_B +**/ + UINT8 CaVrefConfig; + +/** Offset 0x0096 - Reserved +**/ + UINT8 Reserved4[6]; + +/** Offset 0x009C - Intel Enhanced Debug + Intel Enhanced Debug (IED): 0=Disabled, 0x400000=Enabled and 4MB SMRAM occupied + 0 : Disable, 0x400000 : Enable +**/ + UINT32 IedSize; + +/** Offset 0x00A0 - Tseg Size + Size of SMRAM memory reserved. 0x400000 for Release build and 0x1000000 for Debug build + 0x0400000:4MB, 0x01000000:16MB +**/ + UINT32 TsegSize; + +/** Offset 0x00A4 - Reserved +**/ + UINT8 Reserved5[6]; + +/** Offset 0x00AA - Enable SMBus + Enable/disable SMBus controller. + $EN_DIS +**/ + UINT8 SmbusEnable; + +/** Offset 0x00AB - Spd Address Tabl + Specify SPD Address table for CH0D0/CH0D1/CH1D0&CH1D1. MemorySpdPtr will be used + if SPD Address is 00 +**/ + UINT8 SpdAddressTable[4]; + +/** Offset 0x00AF - Platform Debug Consent + To 'opt-in' for debug, please select 'Enabled' with the desired debug probe type. + Enabling this BIOS option may alter the default value of other debug-related BIOS + options.\Manual: Do not use Platform Debug Consent to override other debug-relevant + policies, but the user must set each debug option manually, aimed at advanced users.\n + Note: DCI OOB (aka BSSB) uses CCA probe. + 0:Disabled, 2:Enabled (DCI OOB), 3:Enabled (USB3 DbC), 4:Enabled (XDP/MIPI60), 5:Enabled + (USB2 DbC), 6:Enable (2-wire DCI OOB), 7:Manual +**/ + UINT8 PlatformDebugConsent; + +/** Offset 0x00B0 - Reserved +**/ + UINT8 Reserved6[2]; + +/** Offset 0x00B2 - Enable DCI ModPHY Pwoer Gate + Enable ModPHY Pwoer Gate when DCI is enabled + $EN_DIS +**/ + UINT8 DciModphyPg; + +/** Offset 0x00B3 - Reserved +**/ + UINT8 Reserved7; + +/** Offset 0x00B4 - PCH Trace Hub Mode + Select 'Host Debugger' if Trace Hub is used with host debugger tool or 'Target Debugger' + if Trace Hub is used by target debugger software or 'Disable' trace hub functionality. + 0: Disable, 1: Target Debugger Mode, 2: Host Debugger Mode +**/ + UINT8 PchTraceHubMode; + +/** Offset 0x00B5 - Reserved +**/ + UINT8 Reserved8[47]; + +/** Offset 0x00E4 - Disable VT-d + 0=Enable/FALSE(VT-d enabled), 1=Disable/TRUE (VT-d disabled) + $EN_DIS +**/ + UINT8 VtdDisable; + +/** Offset 0x00E5 - Reserved +**/ + UINT8 Reserved9[3]; + +/** Offset 0x00E8 - Internal Graphics Pre-allocated Memory + Size of memory preallocated for internal graphics. + 0x00:0MB, 0x01:32MB, 0x02:64MB, 0x03:96MB, 0x04:128MB, 0x05:160MB, 0xF0:4MB, 0xF1:8MB, + 0xF2:12MB, 0xF3:16MB, 0xF4:20MB, 0xF5:24MB, 0xF6:28MB, 0xF7:32MB, 0xF8:36MB, 0xF9:40MB, + 0xFA:44MB, 0xFB:48MB, 0xFC:52MB, 0xFD:56MB, 0xFE:60MB +**/ + UINT8 IgdDvmt50PreAlloc; + +/** Offset 0x00E9 - Internal Graphics + Enable/disable internal graphics. + $EN_DIS +**/ + UINT8 InternalGfx; + +/** Offset 0x00EA - Reserved +**/ + UINT8 Reserved10; + +/** Offset 0x00EB - Board Type + MrcBoardType, Options are 0=Mobile/Mobile Halo, 1=Desktop/DT Halo, 5=ULT/ULX/Mobile + Halo, 7=UP Server + 0:Mobile/Mobile Halo, 1:Desktop/DT Halo, 5:ULT/ULX/Mobile Halo, 7:UP Server +**/ + UINT8 UserBd; + +/** Offset 0x00EC - Reserved +**/ + UINT8 Reserved11[2]; + +/** Offset 0x00EE - SA GV + System Agent dynamic frequency support and when enabled memory will be training + at three different frequencies. + 0:Disabled, 1:FixedLow, 2:FixedMid, 3:FixedHigh, 4:Enabled +**/ + UINT8 SaGv; + +/** Offset 0x00EF - Reserved +**/ + UINT8 Reserved12[5]; + +/** Offset 0x00F4 - Rank Margin Tool + Enable/disable Rank Margin Tool. + $EN_DIS +**/ + UINT8 RMT; + +/** Offset 0x00F5 - Reserved +**/ + UINT8 Reserved13[24]; + +/** Offset 0x010D - Memory Reference Clock + 100MHz, 133MHz. + 0:133MHz, 1:100MHz +**/ + UINT8 RefClk; + +/** Offset 0x010E - Reserved +**/ + UINT8 Reserved14[26]; + +/** Offset 0x0128 - Enable Intel HD Audio (Azalia) + 0: Disable, 1: Enable (Default) Azalia controller + $EN_DIS +**/ + UINT8 PchHdaEnable; + +/** Offset 0x0129 - CPU Trace Hub Mode + Select 'Host Debugger' if Trace Hub is used with host debugger tool or 'Target Debugger' + if Trace Hub is used by target debugger software or 'Disable' trace hub functionality. + 0: Disable, 1:Target Debugger Mode, 2:Host Debugger Mode +**/ + UINT8 CpuTraceHubMode; + +/** Offset 0x012A - Reserved +**/ + UINT8 Reserved15[98]; + +/** Offset 0x018C - Program GPIOs for LFP on DDI port-A device + 0=Disabled,1(Default)=eDP, 2=MIPI DSI + 0:Disabled, 1:eDP, 2:MIPI DSI +**/ + UINT8 DdiPortAConfig; + +/** Offset 0x018D - Reserved +**/ + UINT8 Reserved16[2]; + +/** Offset 0x018F - Enable or disable HPD of DDI port B + 0=Disable, 1(Default)=Enable + $EN_DIS +**/ + UINT8 DdiPortBHpd; + +/** Offset 0x0190 - Enable or disable HPD of DDI port C + 0(Default)=Disable, 1=Enable + $EN_DIS +**/ + UINT8 DdiPortCHpd; + +/** Offset 0x0191 - Reserved +**/ + UINT8 Reserved17[5]; + +/** Offset 0x0196 - Enable or disable DDC of DDI port B + 0=Disable, 1(Default)=Enable + $EN_DIS +**/ + UINT8 DdiPortBDdc; + +/** Offset 0x0197 - Enable or disable DDC of DDI port C + 0(Default)=Disable, 1=Enable + $EN_DIS +**/ + UINT8 DdiPortCDdc; + +/** Offset 0x0198 - Reserved +**/ + UINT8 Reserved18[165]; + +/** Offset 0x023D - C6DRAM power gating feature + This policy indicates whether or not BIOS should allocate PRMRR memory for C6DRAM + power gating feature.- 0: Don't allocate any PRMRR memory for C6DRAM power gating + feature.- 1: Allocate PRMRR memory for C6DRAM power gating feature. + $EN_DIS +**/ + UINT8 EnableC6Dram; + +/** Offset 0x023E - Reserved +**/ + UINT8 Reserved19[7]; + +/** Offset 0x0245 - CPU ratio value + CPU ratio value. Valid Range 0 to 63 +**/ + UINT8 CpuRatio; + +/** Offset 0x0246 - Reserved +**/ + UINT8 Reserved20[4]; + +/** Offset 0x024A - Enable or Disable VMX + Enable or Disable VMX; 0: Disable; 1: Enable. + $EN_DIS +**/ + UINT8 VmxEnable; + +/** Offset 0x024B - Reserved +**/ + UINT8 Reserved21[31]; + +/** Offset 0x026A - BiosGuard + Enable/Disable. 0: Disable, Enable/Disable BIOS Guard feature, 1: enable + $EN_DIS +**/ + UINT8 BiosGuard; + +/** Offset 0x026B - Reserved +**/ + UINT8 Reserved22[5]; + +/** Offset 0x0270 - PrmrrSize + Enable/Disable. 0: Disable, define default value of PrmrrSize , 1: enable +**/ + UINT32 PrmrrSize; + +/** Offset 0x0274 - SinitMemorySize + Enable/Disable. 0: Disable, define default value of SinitMemorySize , 1: enable +**/ + UINT32 SinitMemorySize; + +/** Offset 0x0278 - Reserved +**/ + UINT8 Reserved23[543]; + +/** Offset 0x0497 - Usage type for ClkSrc + 0-23: PCH rootport, 0x40-0x43: PEG port, 0x70:LAN, 0x80: unspecified but in use + (free running), 0xFF: not used +**/ + UINT8 PcieClkSrcUsage[16]; + +/** Offset 0x04A7 - ClkReq-to-ClkSrc mapping + Number of ClkReq signal assigned to ClkSrc +**/ + UINT8 PcieClkSrcClkReq[16]; + +/** Offset 0x04B7 - Reserved +**/ + UINT8 Reserved24[5]; + +/** Offset 0x04BC - Enable PCIE RP Mask + Enable/disable PCIE Root Ports. 0: disable, 1: enable. One bit for each port, bit0 + for port1, bit1 for port2, and so on. +**/ + UINT32 PcieRpEnableMask; + +/** Offset 0x04C0 - Debug Interfaces + Debug Interfaces. BIT0-RAM, BIT1-UART, BIT3-USB3, BIT4-Serial IO, BIT5-TraceHub, + BIT2 - Not used. +**/ + UINT8 PcdDebugInterfaceFlags; + +/** Offset 0x04C1 - Serial Io Uart Debug Controller Number + Select SerialIo Uart Controller for debug. Note: If UART0 is selected as CNVi BT + Core interface, it cannot be used for debug purpose. + 0:SerialIoUart0, 1:SerialIoUart1, 2:SerialIoUart2 +**/ + UINT8 SerialIoUartDebugControllerNumber; + +/** Offset 0x04C2 - Reserved +**/ + UINT8 Reserved25[22]; + +/** Offset 0x04D8 - Early Command Training + Enables/Disable Early Command Training + $EN_DIS +**/ + UINT8 ECT; + +/** Offset 0x04D9 - Reserved +**/ + UINT8 Reserved26[2]; + +/** Offset 0x04DB - Read MPR Training + Enables/Disable Read MPR Training + $EN_DIS +**/ + UINT8 RDMPRT; + +/** Offset 0x04DC - Reserved +**/ + UINT8 Reserved27[7]; + +/** Offset 0x04E3 - Dimm ODT Training + Enables/Disable Dimm ODT Training + $EN_DIS +**/ + UINT8 DIMMODTT; + +/** Offset 0x04E4 - DIMM RON Training + Enables/Disable DIMM RON Training + $EN_DIS +**/ + UINT8 DIMMRONT; + +/** Offset 0x04E5 - Reserved +**/ + UINT8 Reserved28; + +/** Offset 0x04E6 - Write Slew Rate Training + Enables/Disable Write Slew Rate Training + $EN_DIS +**/ + UINT8 WRSRT; + +/** Offset 0x04E7 - Read ODT Training + Enables/Disable Read ODT Training + $EN_DIS +**/ + UINT8 RDODTT; + +/** Offset 0x04E8 - Read Equalization Training + Enables/Disable Read Equalization Training + $EN_DIS +**/ + UINT8 RDEQT; + +/** Offset 0x04E9 - Read Amplifier Training + Enables/Disable Read Amplifier Training + $EN_DIS +**/ + UINT8 RDAPT; + +/** Offset 0x04EA - Reserved +**/ + UINT8 Reserved29[3]; + +/** Offset 0x04ED - Read Voltage Centering 2D + Enables/Disable Read Voltage Centering 2D + $EN_DIS +**/ + UINT8 RDVC2D; + +/** Offset 0x04EE - Reserved +**/ + UINT8 Reserved30[3]; + +/** Offset 0x04F1 - Turn Around Timing Training + Enables/Disable Turn Around Timing Training + $EN_DIS +**/ + UINT8 TAT; + +/** Offset 0x04F2 - Reserved +**/ + UINT8 Reserved31[6]; + +/** Offset 0x04F8 - Receive Enable Centering 1D + Enables/Disable Receive Enable Centering 1D + $EN_DIS +**/ + UINT8 RCVENC1D; + +/** Offset 0x04F9 - Retrain Margin Check + Enables/Disable Retrain Margin Check + $EN_DIS +**/ + UINT8 RMC; + +/** Offset 0x04FA - Reserved +**/ + UINT8 Reserved32[60]; + +/** Offset 0x0536 - RAPL PL 1 WindowX + Power PL 1 time window X value, (1/1024)*(1+(x/4))*(2^y) (0=Def) +**/ + UINT8 RaplLim1WindX; + +/** Offset 0x0537 - RAPL PL 1 WindowY + Power PL 1 time window Y value, (1/1024)*(1+(x/4))*(2^y) (0=Def) +**/ + UINT8 RaplLim1WindY; + +/** Offset 0x0538 - Reserved +**/ + UINT8 Reserved33[2]; + +/** Offset 0x053A - RAPL PL 1 Power + range[0;2^14-1]= [2047.875;0]in W, (224= Def) +**/ + UINT16 RaplLim1Pwr; + +/** Offset 0x053C - Reserved +**/ + UINT8 Reserved34[68]; + +/** Offset 0x0580 - LpDdrDqDqsReTraining + Enables/Disable LpDdrDqDqsReTraining + $EN_DIS +**/ + UINT8 LpDdrDqDqsReTraining; + +/** Offset 0x0581 - Reserved +**/ + UINT8 Reserved35[172]; + +/** Offset 0x062D - Enable HD Audio Link + Enable/disable HD Audio Link. Muxed with SSP0/SSP1/SNDW1. + $EN_DIS +**/ + UINT8 PchHdaAudioLinkHdaEnable; + +/** Offset 0x062E - Reserved +**/ + UINT8 Reserved36[3]; + +/** Offset 0x0631 - Enable HD Audio DMIC_N Link + Enable/disable HD Audio DMIC1 link. Muxed with SNDW3. +**/ + UINT8 PchHdaAudioLinkDmicEnable[2]; + +/** Offset 0x0633 - Reserved +**/ + UINT8 Reserved37[17]; + +/** Offset 0x0644 - Enable HD Audio DSP + Enable/disable HD Audio DSP feature. + $EN_DIS +**/ + UINT8 PchHdaDspEnable; + +/** Offset 0x0645 - Reserved +**/ + UINT8 Reserved38[11]; + +/** Offset 0x0650 - Enable HD Audio SSP0 Link + Enable/disable HD Audio SSP_N/I2S link. Muxed with HDA. N-number 0-5 +**/ + UINT8 PchHdaAudioLinkSspEnable[6]; + +/** Offset 0x0656 - Enable HD Audio SoundWire#N Link + Enable/disable HD Audio SNDW#N link. Muxed with HDA. +**/ + UINT8 PchHdaAudioLinkSndwEnable[4]; + +/** Offset 0x065A - Reserved +**/ + UINT8 Reserved39[7]; + +/** Offset 0x0661 - Skip MBP HOB + Test, 0: disable, 1: enable, Enable/Disable MOB HOB. + $EN_DIS +**/ + UINT8 SkipMbpHob; + +/** Offset 0x0662 - Reserved +**/ + UINT8 Reserved40[22]; +} FSP_M_CONFIG; + +/** Fsp M UPD Configuration +**/ +typedef struct { + +/** Offset 0x0000 +**/ + FSP_UPD_HEADER FspUpdHeader; + +/** Offset 0x0020 +**/ + FSPM_ARCH_UPD FspmArchUpd; + +/** Offset 0x0040 +**/ + FSP_M_CONFIG FspmConfig; + +/** Offset 0x0678 +**/ + UINT8 UnusedUpdSpace19[6]; + +/** Offset 0x067E +**/ + UINT16 UpdTerminator; +} FSPM_UPD; + +#pragma pack() + +#endif diff --git a/src/vendorcode/intel/fsp/fsp2_0/jasperlake/FspsUpd.h b/src/vendorcode/intel/fsp/fsp2_0/jasperlake/FspsUpd.h new file mode 100644 index 0000000000..d01ae6ab46 --- /dev/null +++ b/src/vendorcode/intel/fsp/fsp2_0/jasperlake/FspsUpd.h @@ -0,0 +1,656 @@ +/** @file + +Copyright (c) 2019, Intel Corporation. All rights reserved.
+ +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + +* Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. +* Redistributions in binary form must reproduce the above copyright notice, this + list of conditions and the following disclaimer in the documentation and/or + other materials provided with the distribution. +* Neither the name of Intel Corporation nor the names of its contributors may + be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF + THE POSSIBILITY OF SUCH DAMAGE. + + This file is automatically generated. Please do NOT modify !!! + +**/ + +#ifndef __FSPSUPD_H__ +#define __FSPSUPD_H__ + +#include + +#pragma pack(1) + + +/// +/// Azalia Header structure +/// +typedef struct { + UINT16 VendorId; ///< Codec Vendor ID + UINT16 DeviceId; ///< Codec Device ID + UINT8 RevisionId; ///< Revision ID of the codec. 0xFF matches any revision. + UINT8 SdiNum; ///< SDI number, 0xFF matches any SDI. + UINT16 DataDwords; ///< Number of data DWORDs pointed by the codec data buffer. + UINT32 Reserved; ///< Reserved for future use. Must be set to 0. +} AZALIA_HEADER; + +/// +/// Audio Azalia Verb Table structure +/// +typedef struct { + AZALIA_HEADER Header; ///< AZALIA PCH header + UINT32 *Data; ///< Pointer to the data buffer. Its length is specified in the header +} AUDIO_AZALIA_VERB_TABLE; + +/// +/// Refer to the definition of PCH_INT_PIN +/// +typedef enum { + SiPchNoInt, ///< No Interrupt Pin + SiPchIntA, + SiPchIntB, + SiPchIntC, + SiPchIntD +} SI_PCH_INT_PIN; +/// +/// The PCH_DEVICE_INTERRUPT_CONFIG block describes interrupt pin, IRQ and interrupt mode for PCH device. +/// +typedef struct { + UINT8 Device; ///< Device number + UINT8 Function; ///< Device function + UINT8 IntX; ///< Interrupt pin: INTA-INTD (see SI_PCH_INT_PIN) + UINT8 Irq; ///< IRQ to be set for device. +} SI_PCH_DEVICE_INTERRUPT_CONFIG; + +#define SI_PCH_MAX_DEVICE_INTERRUPT_CONFIG 64 ///< Number of all PCH devices + + +/** Fsp S Configuration +**/ +typedef struct { + +/** Offset 0x0020 - Reserved +**/ + UINT8 Reserved0[16]; + +/** Offset 0x0030 - Graphics Configuration Ptr + Points to VBT +**/ + UINT32 GraphicsConfigPtr; + +/** Offset 0x0034 - Enable Device 4 + Enable/disable Device 4 + $EN_DIS +**/ + UINT8 Device4Enable; + +/** Offset 0x0035 - Enable eMMC Controller + Enable/disable eMMC Controller. + $EN_DIS +**/ + UINT8 ScsEmmcEnabled; + +/** Offset 0x0036 - Enable eMMC HS400 Mode + Enable eMMC HS400 Mode. + $EN_DIS +**/ + UINT8 ScsEmmcHs400Enabled; + +/** Offset 0x0037 - Use DLL values from policy + Set if FSP should use HS400 DLL values from policy + $EN_DIS +**/ + UINT8 EmmcUseCustomDlls; + +/** Offset 0x0038 - Emmc Tx CMD Delay control register value + Please see Tx CMD Delay Control register definition for help +**/ + UINT32 EmmcTxCmdDelayRegValue; + +/** Offset 0x003C - Emmc Tx DATA Delay control 1 register value + Please see Tx DATA Delay control 1 register definition for help +**/ + UINT32 EmmcTxDataDelay1RegValue; + +/** Offset 0x0040 - Emmc Tx DATA Delay control 2 register value + Please see Tx DATA Delay control 2 register definition for help +**/ + UINT32 EmmcTxDataDelay2RegValue; + +/** Offset 0x0044 - Emmc Rx CMD + DATA Delay control 1 register value + Please see Rx CMD + DATA Delay control 1 register definition for help +**/ + UINT32 EmmcRxCmdDataDelay1RegValue; + +/** Offset 0x0048 - Emmc Rx CMD + DATA Delay control 2 register value + Please see Rx CMD + DATA Delay control 2 register definition for help +**/ + UINT32 EmmcRxCmdDataDelay2RegValue; + +/** Offset 0x004C - Emmc Rx Strobe Delay control register value + Please see Rx Strobe Delay control register definition for help +**/ + UINT32 EmmcRxStrobeDelayRegValue; + +/** Offset 0x0050 - Enable SdCard Controller + Enable/disable SD Card Controller. + $EN_DIS +**/ + UINT8 ScsSdCardEnabled; + +/** Offset 0x0051 - SdCard power enable polarity + Choose SD_PWREN# polarity + 0: Active low, 1: Active high +**/ + UINT8 SdCardPowerEnableActiveHigh; + +/** Offset 0x0052 - Reserved +**/ + UINT8 Reserved1[34]; + +/** Offset 0x0074 - SdCard Command Pad Termination + 0x0: Hardware default, 0x1: None, 0x13: 1kOhm weak pull-up, 0x15: 5kOhm weak pull-up, + 0x19: 20kOhm weak pull-up +**/ + UINT8 SdCardGpioCmdPadTermination; + +/** Offset 0x0075 - Reserved +**/ + UINT8 Reserved2[136]; + +/** Offset 0x00FD - Enable SATA SALP Support + Enable/disable SATA Aggressive Link Power Management. + $EN_DIS +**/ + UINT8 SataSalpSupport; + +/** Offset 0x00FE - Enable SATA ports + Enable/disable SATA ports. One byte for each port, byte0 for port0, byte1 for port1, + and so on. +**/ + UINT8 SataPortsEnable[8]; + +/** Offset 0x0106 - Enable SATA DEVSLP Feature + Enable/disable SATA DEVSLP per port. 0 is disable, 1 is enable. One byte for each + port, byte0 for port0, byte1 for port1, and so on. +**/ + UINT8 SataPortsDevSlp[8]; + +/** Offset 0x010E - Enable USB2 ports + Enable/disable per USB2 ports. One byte for each port, byte0 for port0, byte1 for + port1, and so on. +**/ + UINT8 PortUsb20Enable[16]; + +/** Offset 0x011E - Enable USB3 ports + Enable/disable per USB3 ports. One byte for each port, byte0 for port0, byte1 for + port1, and so on. +**/ + UINT8 PortUsb30Enable[10]; + +/** Offset 0x0128 - Enable xDCI controller + Enable/disable to xDCI controller. + $EN_DIS +**/ + UINT8 XdciEnable; + +/** Offset 0x0129 - Reserved +**/ + UINT8 Reserved3[28]; + +/** Offset 0x0145 - Enable SATA + Enable/disable SATA controller. + $EN_DIS +**/ + UINT8 SataEnable; + +/** Offset 0x0146 - SATA Mode + Select SATA controller working mode. + 0:AHCI, 1:RAID +**/ + UINT8 SataMode; + +/** Offset 0x0147 - SPIn Device Mode + Selects SPI operation mode. N represents controller index: SPI0, SPI1, ... Available + modes: 0:SerialIoSpiDisabled, 1:SerialIoSpiPci, 2:SerialIoSpiHidden +**/ + UINT8 SerialIoSpiMode[7]; + +/** Offset 0x014E - SPI Chip Select Polarity + Sets polarity for each chip Select. Available options: 0:SerialIoSpiCsActiveLow, + 1:SerialIoSpiCsActiveHigh +**/ + UINT8 SerialIoSpiCsPolarity[14]; + +/** Offset 0x015C - Reserved +**/ + UINT8 Reserved4[21]; + +/** Offset 0x0171 - SPIn Default Chip Select Mode HW/SW + Sets Default CS Mode Hardware or Software. N represents controller index: SPI0, + SPI1, ... Available options: 0:HW, 1:SW +**/ + UINT8 SerialIoSpiCsMode[7]; + +/** Offset 0x0178 - SPIn Default Chip Select State Low/High + Sets Default CS State Low or High. N represents controller index: SPI0, SPI1, ... + Available options: 0:Low, 1:High +**/ + UINT8 SerialIoSpiCsState[7]; + +/** Offset 0x017F - UARTn Device Mode + Selects Uart operation mode. N represents controller index: Uart0, Uart1, ... Available + modes: 0:SerialIoUartDisabled, 1:SerialIoUartPci, 2:SerialIoUartHidden, 3:SerialIoUartCom, + 4:SerialIoUartSkipInit +**/ + UINT8 SerialIoUartMode[7]; + +/** Offset 0x0186 - Reserved +**/ + UINT8 Reserved5[186]; + +/** Offset 0x0240 - UART Number For Debug Purpose + UART number for debug purpose. 0:UART0, 1:UART1, 2:UART2, 3:UART3, 4:UART4, 5:UART5, + 6:UART6. Note: If UART0 is selected as CNVi BT Core interface, it cannot be used + for debug purpose. + 0:UART0, 1:UART1, 2:UART2, 3:UART3, 4:UART4, 5:UART5, 6:UART6 +**/ + UINT8 SerialIoDebugUartNumber; + +/** Offset 0x0241 - Reserved +**/ + UINT8 Reserved6[7]; + +/** Offset 0x0248 - I2Cn Device Mode + Selects I2c operation mode. N represents controller index: I2c0, I2c1, ... Available + modes: 0:SerialIoI2cDisabled, 1:SerialIoI2cPci, 2:SerialIoI2cHidden +**/ + UINT8 SerialIoI2cMode[8]; + +/** Offset 0x0250 - Reserved +**/ + UINT8 Reserved7[72]; + +/** Offset 0x0298 - USB Per Port HS Preemphasis Bias + USB Per Port HS Preemphasis Bias. 000b-0mV, 001b-11.25mV, 010b-16.9mV, 011b-28.15mV, + 100b-28.15mV, 101b-39.35mV, 110b-45mV, 111b-56.3mV. One byte for each port. +**/ + UINT8 Usb2PhyPetxiset[16]; + +/** Offset 0x02A8 - USB Per Port HS Transmitter Bias + USB Per Port HS Transmitter Bias. 000b-0mV, 001b-11.25mV, 010b-16.9mV, 011b-28.15mV, + 100b-28.15mV, 101b-39.35mV, 110b-45mV, 111b-56.3mV, One byte for each port. +**/ + UINT8 Usb2PhyTxiset[16]; + +/** Offset 0x02B8 - USB Per Port HS Transmitter Emphasis + USB Per Port HS Transmitter Emphasis. 00b - Emphasis OFF, 01b - De-emphasis ON, + 10b - Pre-emphasis ON, 11b - Pre-emphasis & De-emphasis ON. One byte for each port. +**/ + UINT8 Usb2PhyPredeemp[16]; + +/** Offset 0x02C8 - USB Per Port Half Bit Pre-emphasis + USB Per Port Half Bit Pre-emphasis. 1b - half-bit pre-emphasis, 0b - full-bit pre-emphasis. + One byte for each port. +**/ + UINT8 Usb2PhyPehalfbit[16]; + +/** Offset 0x02D8 - Enable the write to USB 3.0 TX Output -3.5dB De-Emphasis Adjustment + Enable the write to USB 3.0 TX Output -3.5dB De-Emphasis Adjustment. Each value + in arrary can be between 0-1. One byte for each port. +**/ + UINT8 Usb3HsioTxDeEmphEnable[10]; + +/** Offset 0x02E2 - USB 3.0 TX Output -3.5dB De-Emphasis Adjustment Setting + USB 3.0 TX Output -3.5dB De-Emphasis Adjustment Setting, HSIO_TX_DWORD5[21:16], + Default = 29h (approximately -3.5dB De-Emphasis). One byte for each port. +**/ + UINT8 Usb3HsioTxDeEmph[10]; + +/** Offset 0x02EC - Enable the write to USB 3.0 TX Output Downscale Amplitude Adjustment + Enable the write to USB 3.0 TX Output Downscale Amplitude Adjustment, Each value + in arrary can be between 0-1. One byte for each port. +**/ + UINT8 Usb3HsioTxDownscaleAmpEnable[10]; + +/** Offset 0x02F6 - USB 3.0 TX Output Downscale Amplitude Adjustment + USB 3.0 TX Output Downscale Amplitude Adjustment, HSIO_TX_DWORD8[21:16], Default + = 00h. One byte for each port. +**/ + UINT8 Usb3HsioTxDownscaleAmp[10]; + +/** Offset 0x0300 - Enable LAN + Enable/disable LAN controller. + $EN_DIS +**/ + UINT8 PchLanEnable; + +/** Offset 0x0301 - Reserved +**/ + UINT8 Reserved8[83]; + +/** Offset 0x0354 - External V1P05 Voltage Value that will be used in S0i2/S0i3 states + Value is given in 2.5mV increments (0=0mV, 1=2.5mV, 2=5mV...) +**/ + UINT16 PchFivrExtV1p05RailVoltage; + +/** Offset 0x0356 - External V1P05 Icc Max Value + Granularity of this setting is 1mA and maximal possible value is 200mA +**/ + UINT8 PchFivrExtV1p05RailIccMax; + +/** Offset 0x0357 - Reserved +**/ + UINT8 Reserved9; + +/** Offset 0x0358 - External Vnn Voltage Value that will be used in S0ix/Sx states + Value is given in 2.5mV increments (0=0mV, 1=2.5mV, 2=5mV...) +**/ + UINT16 PchFivrExtVnnRailVoltage; + +/** Offset 0x035A - External Vnn Icc Max Value that will be used in S0ix/Sx states + Granularity of this setting is 1mA and maximal possible value is 200mA +**/ + UINT8 PchFivrExtVnnRailIccMax; + +/** Offset 0x035B - Reserved +**/ + UINT8 Reserved10; + +/** Offset 0x035C - External Vnn Voltage Value that will be used in Sx states + Use only if Ext Vnn Rail config is different in Sx. Value is given in 2.5mV increments + (0=0mV, 1=2.5mV, 2=5mV...) +**/ + UINT16 PchFivrExtVnnRailSxVoltage; + +/** Offset 0x035E - External Vnn Icc Max Value that will be used in Sx states + Use only if Ext Vnn Rail config is different in Sx. Granularity of this setting + is 1mA and maximal possible value is 200mA +**/ + UINT8 PchFivrExtVnnRailSxIccMax; + +/** Offset 0x035F - Reserved +**/ + UINT8 Reserved11[3]; + +/** Offset 0x0362 - Transition time in microseconds from Off (0V) to High Current Mode Voltage + This field has 1us resolution. When value is 0 Transition to 0V is disabled. +**/ + UINT16 PchFivrVccinAuxOffToHighCurModeVolTranTime; + +/** Offset 0x0364 - Reserved +**/ + UINT8 Reserved12[22]; + +/** Offset 0x037A - CNVi BT Audio Offload + Enable/Disable BT Audio Offload, Default is DISABLE. 0: DISABLE, 1: ENABLE + $EN_DIS +**/ + UINT8 CnviBtAudioOffload; + +/** Offset 0x037B - Reserved +**/ + UINT8 Reserved13; + +/** Offset 0x037C - CNVi RF_RESET pin muxing + Select CNVi RF_RESET# pin depending on board routing. ICP-N: GPP_H12 = 0x2746E40C(default) + or GPP_H1 = 0x3746E401. Refer to GPIO_*_MUXING_CNVI_RF_RESET_* in GpioPins*.h. +**/ + UINT32 CnviRfResetPinMux; + +/** Offset 0x0380 - CNVi CLKREQ pin muxing + Select CNVi CLKREQ pin depending on board routing. ICP-N: GPP_H13 = 0x2746E60D(default) + or GPP_H2 = 0x3746E602. Refer to GPIO_*_MUXING_CNVI_MODEM_CLKREQ_* in GpioPins*.h. +**/ + UINT32 CnviClkreqPinMux; + +/** Offset 0x0384 - Reserved +**/ + UINT8 Reserved14[6]; + +/** Offset 0x038A - HECI3 state + The HECI3 state from Mbp for reference in S3 path or when MbpHob is not installed. + 0: disable, 1: enable + $EN_DIS +**/ + UINT8 Heci3Enabled; + +/** Offset 0x038B - Reserved +**/ + UINT8 Reserved15[141]; + +/** Offset 0x0418 - CdClock Frequency selection + 0: (Default) Auto (Max based on reference clock frequency), 1: 172.8 Mhz, 2: 180 + Mhz, 3: 190 Mhz, 4: 307.2 Mhz, 5: 312 Mhz, 6: 552 Mhz, 7: 556.8 Mhz, 8: 648 Mhz, + 9: 652.8 Mhz + 0: Auto (Max based on reference clock frequency), 1: 172.8 Mhz, 2: 180 Mhz, 3: 190 + Mhz, 4: 307.2 Mhz, 5: 312 Mhz, 6: 552 Mhz, 7: 556.8 Mhz, 8: 648 Mhz, 9: 652.8 Mhz +**/ + UINT8 CdClock; + +/** Offset 0x0419 - Enable/Disable PeiGraphicsPeimInit + Enable: Enable PeiGraphicsPeimInit, Disable(Default): Disable PeiGraphicsPeimInit + $EN_DIS +**/ + UINT8 PeiGraphicsPeimInit; + +/** Offset 0x041A - Reserved +**/ + UINT8 Reserved16[160]; + +/** Offset 0x04BA - Skip Multi-Processor Initialization + When this is skipped, boot loader must initialize processors before SilicionInit + API. 0: Initialize; 1: Skip + $EN_DIS +**/ + UINT8 SkipMpInit; + +/** Offset 0x04BB - Reserved +**/ + UINT8 Reserved17[9]; + +/** Offset 0x04C4 - CpuMpPpi + Pointer for CpuMpPpi +**/ + UINT32 CpuMpPpi; + +/** Offset 0x04C8 - Reserved +**/ + UINT8 Reserved18[86]; + +/** Offset 0x051E - RTC Cmos Memory Lock + Enable RTC lower and upper 128 byte Lock bits to lock Bytes 38h-3Fh in the upper + and and lower 128-byte bank of RTC RAM. + $EN_DIS +**/ + UINT8 RtcMemoryLock; + +/** Offset 0x051F - Reserved +**/ + UINT8 Reserved19[24]; + +/** Offset 0x0537 - Enable PCIE RP Pm Sci + Indicate whether the root port power manager SCI is enabled. +**/ + UINT8 PcieRpPmSci[24]; + +/** Offset 0x054F - Reserved +**/ + UINT8 Reserved20[24]; + +/** Offset 0x0567 - Enable PCIE RP Clk Req Detect + Probe CLKREQ# signal before enabling CLKREQ# based power management. +**/ + UINT8 PcieRpClkReqDetect[24]; + +/** Offset 0x057F - Reserved +**/ + UINT8 Reserved21[455]; + +/** Offset 0x0746 - PCH Pm Slp S3 Min Assert + SLP_S3 Minimum Assertion Width Policy. Default is PchSlpS350ms. +**/ + UINT8 PchPmSlpS3MinAssert; + +/** Offset 0x0747 - Reserved +**/ + UINT8 Reserved22; + +/** Offset 0x0748 - PCH Pm Slp Sus Min Assert + SLP_SUS Minimum Assertion Width Policy. Default is PchSlpSus4s. +**/ + UINT8 PchPmSlpSusMinAssert; + +/** Offset 0x0749 - PCH Pm Slp A Min Assert + SLP_A Minimum Assertion Width Policy. Default is PchSlpA2s. +**/ + UINT8 PchPmSlpAMinAssert; + +/** Offset 0x074A - Reserved +**/ + UINT8 Reserved23[11]; + +/** Offset 0x0755 - PCH Sata Pwr Opt Enable + SATA Power Optimizer on PCH side. + $EN_DIS +**/ + UINT8 SataPwrOptEnable; + +/** Offset 0x0756 - Reserved +**/ + UINT8 Reserved24[146]; + +/** Offset 0x07E8 - USB2 Port Over Current Pin + Describe the specific over current pin number of USB 2.0 Port N. +**/ + UINT8 Usb2OverCurrentPin[16]; + +/** Offset 0x07F8 - USB3 Port Over Current Pin + Describe the specific over current pin number of USB 3.0 Port N. +**/ + UINT8 Usb3OverCurrentPin[10]; + +/** Offset 0x0802 - Enable 8254 Static Clock Gating + Set 8254CGE=1 is required for SLP_S0 support. However, set 8254CGE=1 in POST time + might fail to boot legacy OS using 8254 timer. Make sure it is disabled to support + legacy OS using 8254 timer. Also enable this while S0ix is enabled. + $EN_DIS +**/ + UINT8 Enable8254ClockGating; + +/** Offset 0x0803 - Enable 8254 Static Clock Gating On S3 + This is only applicable when Enable8254ClockGating is disabled. FSP will do the + 8254 CGE programming on S3 resume when Enable8254ClockGatingOnS3 is enabled. This + avoids the SMI requirement for the programming. + $EN_DIS +**/ + UINT8 Enable8254ClockGatingOnS3; + +/** Offset 0x0804 - Reserved +**/ + UINT8 Reserved25[531]; + +/** Offset 0x0A17 - Enable/Disable IGFX PmSupport + Enable(Default): Enable IGFX PmSupport, Disable: Disable IGFX PmSupport + $EN_DIS +**/ + UINT8 PmSupport; + +/** Offset 0x0A18 - Reserved +**/ + UINT8 Reserved26[32]; + +/** Offset 0x0A38 - TCC Activation Offset + TCC Activation Offset. Offset from factory set TCC activation temperature at which + the Thermal Control Circuit must be activated. TCC will be activated at TCC Activation + Temperature, in volts.For SKL Y SKU, the recommended default for this policy is + 10, For all other SKUs the recommended default are 0 +**/ + UINT8 TccActivationOffset; + +/** Offset 0x0A39 - Reserved +**/ + UINT8 Reserved27[34]; + +/** Offset 0x0A5B - Enable or Disable CPU power states (C-states) + Enable or Disable CPU power states (C-states). 0: Disable; 1: Enable + $EN_DIS +**/ + UINT8 Cx; + +/** Offset 0x0A5C - Reserved +**/ + UINT8 Reserved28[74]; + +/** Offset 0x0AA6 - Platform Power Pmax + PCODE MMIO Mailbox: Platform Power Pmax. 0 - Auto Specified in 1/8 Watt increments. + Range 0-1024 Watts. Value of 800 = 100W +**/ + UINT16 PsysPmax; + +/** Offset 0x0AA8 - Reserved +**/ + UINT8 Reserved29[116]; + +/** Offset 0x0B1C - End of Post message + Test, Send End of Post message. Disable(0x0): Disable EOP message, Send in PEI(0x1): + EOP send in PEI, Send in DXE(0x2)(Default): EOP send in DXE + 0:Disable, 1:Send in PEI, 2:Send in DXE, 3:Reserved +**/ + UINT8 EndOfPostMessage; + +/** Offset 0x0B1D - Reserved +**/ + UINT8 Reserved30[3]; + +/** Offset 0x0B20 - Unlock all GPIO pads + Force all GPIO pads to be unlocked for debug purpose. + $EN_DIS +**/ + UINT8 PchUnlockGpioPads; + +/** Offset 0x0B21 - Reserved +**/ + UINT8 Reserved31[447]; +} FSP_S_CONFIG; + +/** Fsp S UPD Configuration +**/ +typedef struct { + +/** Offset 0x0000 +**/ + FSP_UPD_HEADER FspUpdHeader; + +/** Offset 0x0020 +**/ + FSP_S_CONFIG FspsConfig; + +/** Offset 0x0CE0 +**/ + UINT8 UnusedUpdSpace37[6]; + +/** Offset 0x0CE6 +**/ + UINT16 UpdTerminator; +} FSPS_UPD; + +#pragma pack() + +#endif diff --git a/src/vendorcode/intel/fsp/fsp2_0/jasperlake/FsptUpd.h b/src/vendorcode/intel/fsp/fsp2_0/jasperlake/FsptUpd.h new file mode 100644 index 0000000000..508705c13f --- /dev/null +++ b/src/vendorcode/intel/fsp/fsp2_0/jasperlake/FsptUpd.h @@ -0,0 +1,186 @@ +/** @file + +Copyright (c) 2019, Intel Corporation. All rights reserved.
+ +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + +* Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. +* Redistributions in binary form must reproduce the above copyright notice, this + list of conditions and the following disclaimer in the documentation and/or + other materials provided with the distribution. +* Neither the name of Intel Corporation nor the names of its contributors may + be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF + THE POSSIBILITY OF SUCH DAMAGE. + + This file is automatically generated. Please do NOT modify !!! + +**/ + +#ifndef __FSPTUPD_H__ +#define __FSPTUPD_H__ + +#include + +#pragma pack(1) + + +/** Fsp T Core UPD +**/ +typedef struct { + +/** Offset 0x0020 +**/ + UINT32 MicrocodeRegionBase; + +/** Offset 0x0024 +**/ + UINT32 MicrocodeRegionSize; + +/** Offset 0x0028 +**/ + UINT32 CodeRegionBase; + +/** Offset 0x002C +**/ + UINT32 CodeRegionSize; + +/** Offset 0x0030 +**/ + UINT8 Reserved[16]; +} FSPT_CORE_UPD; + +/** Fsp T Configuration +**/ +typedef struct { + +/** Offset 0x0040 - PcdSerialIoUartDebugEnable + Enable SerialIo Uart debug library with/without initializing SerialIo Uart device in FSP. + 0:Disable, 1:Enable and Initialize, 2:Enable without Initializing +**/ + UINT8 PcdSerialIoUartDebugEnable; + +/** Offset 0x0041 - PcdSerialIoUartNumber - FSPT + Select SerialIo Uart Controller for debug. Note: If UART0 is selected as CNVi BT + Core interface, it cannot be used for debug purpose. + 0:SerialIoUart0, 1:SerialIoUart1, 2:SerialIoUart2 +**/ + UINT8 PcdSerialIoUartNumber; + +/** Offset 0x0042 - PcdSerialIoUartMode - FSPT + Select SerialIo Uart Controller mode + 0:SerialIoUartDisabled, 1:SerialIoUartPci, 2:SerialIoUartHidden, 3:SerialIoUartCom, + 4:SerialIoUartSkipInit +**/ + UINT8 PcdSerialIoUartMode; + +/** Offset 0x0043 +**/ + UINT8 UnusedUpdSpace0; + +/** Offset 0x0044 - PcdSerialIoUartBaudRate - FSPT + Set default BaudRate Supported from 0 - default to 6000000 +**/ + UINT32 PcdSerialIoUartBaudRate; + +/** Offset 0x0048 - Pci Express Base Address + Base address to be programmed for Pci Express +**/ + UINT64 PcdPciExpressBaseAddress; + +/** Offset 0x0050 - Pci Express Region Length + Region Length to be programmed for Pci Express +**/ + UINT32 PcdPciExpressRegionLength; + +/** Offset 0x0054 - PcdSerialIoUartParity - FSPT + Set default Parity. + 0: DefaultParity, 1: NoParity, 2: EvenParity, 3: OddParity +**/ + UINT8 PcdSerialIoUartParity; + +/** Offset 0x0055 - PcdSerialIoUartDataBits - FSPT + Set default word length. 0: Default, 5,6,7,8 +**/ + UINT8 PcdSerialIoUartDataBits; + +/** Offset 0x0056 - PcdSerialIoUartStopBits - FSPT + Set default stop bits. + 0: DefaultStopBits, 1: OneStopBit, 2: OneFiveStopBits, 3: TwoStopBits +**/ + UINT8 PcdSerialIoUartStopBits; + +/** Offset 0x0057 - PcdSerialIoUartAutoFlow - FSPT + Enables UART hardware flow control, CTS and RTS lines. + 0: Disable, 1:Enable +**/ + UINT8 PcdSerialIoUartAutoFlow; + +/** Offset 0x0058 - PcdSerialIoUartRxPinMux - FSPT + Select RX pin muxing for SerialIo UART used for debug +**/ + UINT32 PcdSerialIoUartRxPinMux; + +/** Offset 0x005C - PcdSerialIoUartTxPinMux - FSPT + Select TX pin muxing for SerialIo UART used for debug +**/ + UINT32 PcdSerialIoUartTxPinMux; + +/** Offset 0x0060 - PcdSerialIoUartRtsPinMux - FSPT + Select SerialIo Uart used for debug Rts pin muxing. Refer to GPIO_*_MUXING_SERIALIO_UARTx_RTS* + for possible values. +**/ + UINT32 PcdSerialIoUartRtsPinMux; + +/** Offset 0x0064 - PcdSerialIoUartCtsPinMux - FSPT + Select SerialIo Uart used for debug Cts pin muxing. Refer to GPIO_*_MUXING_SERIALIO_UARTx_CTS* + for possible values. +**/ + UINT32 PcdSerialIoUartCtsPinMux; + +/** Offset 0x0068 +**/ + UINT8 ReservedFsptUpd1[24]; +} FSP_T_CONFIG; + +/** Fsp T UPD Configuration +**/ +typedef struct { + +/** Offset 0x0000 +**/ + FSP_UPD_HEADER FspUpdHeader; + +/** Offset 0x0020 +**/ + FSPT_CORE_UPD FsptCoreUpd; + +/** Offset 0x0040 +**/ + FSP_T_CONFIG FsptConfig; + +/** Offset 0x0080 +**/ + UINT8 UnusedUpdSpace1[6]; + +/** Offset 0x0086 +**/ + UINT16 UpdTerminator; +} FSPT_UPD; + +#pragma pack() + +#endif diff --git a/src/vendorcode/intel/fsp/fsp2_0/jasperlake/MemInfoHob.h b/src/vendorcode/intel/fsp/fsp2_0/jasperlake/MemInfoHob.h new file mode 100644 index 0000000000..c590409f02 --- /dev/null +++ b/src/vendorcode/intel/fsp/fsp2_0/jasperlake/MemInfoHob.h @@ -0,0 +1,274 @@ +/** @file + This file contains definitions required for creation of + Memory S3 Save data, Memory Info data and Memory Platform + data hobs. + + @copyright + Copyright (c) 2019, Intel Corporation. All rights reserved.
+ This program and the accompanying materials are licensed and made available under + the terms and conditions of the BSD License that accompanies this distribution. + The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php. + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +@par Specification Reference: +**/ +#ifndef _MEM_INFO_HOB_H_ +#define _MEM_INFO_HOB_H_ + +#include +#include +#include + +#pragma pack (push, 1) + +extern EFI_GUID gSiMemoryS3DataGuid; +extern EFI_GUID gSiMemoryInfoDataGuid; +extern EFI_GUID gSiMemoryPlatformDataGuid; + +#define MAX_NODE 1 +#define MAX_CH 2 +#define MAX_DIMM 2 + +/// +/// Host reset states from MRC. +/// +#define WARM_BOOT 2 + +#define R_MC_CHNL_RANK_PRESENT 0x7C +#define B_RANK0_PRS BIT0 +#define B_RANK1_PRS BIT1 +#define B_RANK2_PRS BIT4 +#define B_RANK3_PRS BIT5 + +/// +/// Defines taken from MRC so avoid having to include MrcInterface.h +/// + +// +// Matches MAX_SPD_SAVE define in MRC +// +#ifndef MAX_SPD_SAVE +#define MAX_SPD_SAVE 29 +#endif + +// +// MRC version description. +// +typedef struct { + UINT8 Major; ///< Major version number + UINT8 Minor; ///< Minor version number + UINT8 Rev; ///< Revision number + UINT8 Build; ///< Build number +} SiMrcVersion; + +// +// Matches MrcChannelSts enum in MRC +// +#ifndef CHANNEL_NOT_PRESENT +#define CHANNEL_NOT_PRESENT 0 // There is no channel present on the controller. +#endif +#ifndef CHANNEL_DISABLED +#define CHANNEL_DISABLED 1 // There is a channel present but it is disabled. +#endif +#ifndef CHANNEL_PRESENT +#define CHANNEL_PRESENT 2 // There is a channel present and it is enabled. +#endif + +// +// Matches MrcDimmSts enum in MRC +// +#ifndef DIMM_ENABLED +#define DIMM_ENABLED 0 // DIMM/rank Pair is enabled, presence will be detected. +#endif +#ifndef DIMM_DISABLED +#define DIMM_DISABLED 1 // DIMM/rank Pair is disabled, regardless of presence. +#endif +#ifndef DIMM_PRESENT +#define DIMM_PRESENT 2 // There is a DIMM present in the slot/rank pair and it will be used. +#endif +#ifndef DIMM_NOT_PRESENT +#define DIMM_NOT_PRESENT 3 // There is no DIMM present in the slot/rank pair. +#endif + +// +// Matches MrcBootMode enum in MRC +// +#ifndef bmCold +#define bmCold 0 // Cold boot +#endif +#ifndef bmWarm +#define bmWarm 1 // Warm boot +#endif +#ifndef bmS3 +#define bmS3 2 // S3 resume +#endif +#ifndef bmFast +#define bmFast 3 // Fast boot +#endif + +// +// Matches MrcDdrType enum in MRC +// +#ifndef MRC_DDR_TYPE_DDR4 +#define MRC_DDR_TYPE_DDR4 0 +#endif +#ifndef MRC_DDR_TYPE_DDR3 +#define MRC_DDR_TYPE_DDR3 1 +#endif +#ifndef MRC_DDR_TYPE_LPDDR3 +#define MRC_DDR_TYPE_LPDDR3 2 +#endif +#ifndef CPU_CFL//CNL +#ifndef MRC_DDR_TYPE_LPDDR4 +#define MRC_DDR_TYPE_LPDDR4 3 +#endif +#else//CFL +#ifndef MRC_DDR_TYPE_UNKNOWN +#define MRC_DDR_TYPE_UNKNOWN 3 +#endif +#endif//CPU_CFL-endif + +#define MAX_PROFILE_NUM 4 // number of memory profiles supported +#define MAX_XMP_PROFILE_NUM 2 // number of XMP profiles supported + +// +// DIMM timings +// +typedef struct { + UINT32 tCK; ///< Memory cycle time, in femtoseconds. + UINT16 NMode; ///< Number of tCK cycles for the channel DIMM's command rate mode. + UINT16 tCL; ///< Number of tCK cycles for the channel DIMM's CAS latency. + UINT16 tCWL; ///< Number of tCK cycles for the channel DIMM's minimum CAS write latency time. + UINT16 tFAW; ///< Number of tCK cycles for the channel DIMM's minimum four activate window delay time. + UINT16 tRAS; ///< Number of tCK cycles for the channel DIMM's minimum active to precharge delay time. + UINT16 tRCDtRP; ///< Number of tCK cycles for the channel DIMM's minimum RAS# to CAS# delay time and Row Precharge delay time. + UINT16 tREFI; ///< Number of tCK cycles for the channel DIMM's minimum Average Periodic Refresh Interval. + UINT16 tRFC; ///< Number of tCK cycles for the channel DIMM's minimum refresh recovery delay time. + UINT16 tRFCpb; ///< Number of tCK cycles for the channel DIMM's minimum per bank refresh recovery delay time. + UINT16 tRFC2; ///< Number of tCK cycles for the channel DIMM's minimum refresh recovery delay time. + UINT16 tRFC4; ///< Number of tCK cycles for the channel DIMM's minimum refresh recovery delay time. + UINT16 tRPab; ///< Number of tCK cycles for the channel DIMM's minimum row precharge delay time for all banks. + UINT16 tRRD; ///< Number of tCK cycles for the channel DIMM's minimum row active to row active delay time. + UINT16 tRRD_L; ///< Number of tCK cycles for the channel DIMM's minimum row active to row active delay time for same bank groups. + UINT16 tRRD_S; ///< Number of tCK cycles for the channel DIMM's minimum row active to row active delay time for different bank groups. + UINT16 tRTP; ///< Number of tCK cycles for the channel DIMM's minimum internal read to precharge command delay time. + UINT16 tWR; ///< Number of tCK cycles for the channel DIMM's minimum write recovery time. + UINT16 tWTR; ///< Number of tCK cycles for the channel DIMM's minimum internal write to read command delay time. + UINT16 tWTR_L; ///< Number of tCK cycles for the channel DIMM's minimum internal write to read command delay time for same bank groups. + UINT16 tWTR_S; ///< Number of tCK cycles for the channel DIMM's minimum internal write to read command delay time for different bank groups. + UINT16 tCCD_L; ///< Number of tCK cycles for the channel DIMM's minimum CAS-to-CAS delay for same bank group. +} MRC_CH_TIMING; + +typedef struct { + UINT8 SG; ///< Number of tCK cycles between transactions in the same bank group. + UINT8 DG; ///< Number of tCK cycles between transactions when switching bank groups. + UINT8 DR; ///< Number of tCK cycles between transactions when switching between Ranks (in the same DIMM). + UINT8 DD; ///< Number of tCK cycles between transactions when switching between DIMMs. +} MRC_TA_TIMING; + +/// +/// Memory SMBIOS & OC Memory Data Hob +/// +typedef struct { + UINT8 Status; ///< See MrcDimmStatus for the definition of this field. + UINT8 DimmId; + UINT32 DimmCapacity; ///< DIMM size in MBytes. + UINT16 MfgId; + UINT8 ModulePartNum[20]; ///< Module part number for DDR3 is 18 bytes however for DRR4 20 bytes as per JEDEC Spec, so reserving 20 bytes + UINT8 RankInDimm; ///< The number of ranks in this DIMM. + UINT8 SpdDramDeviceType; ///< Save SPD DramDeviceType information needed for SMBIOS structure creation. + UINT8 SpdModuleType; ///< Save SPD ModuleType information needed for SMBIOS structure creation. + UINT8 SpdModuleMemoryBusWidth; ///< Save SPD ModuleMemoryBusWidth information needed for SMBIOS structure creation. + UINT8 SpdSave[MAX_SPD_SAVE]; ///< Save SPD Manufacturing information needed for SMBIOS structure creation. + UINT16 Speed; ///< The maximum capable speed of the device, in MHz. +} DIMM_INFO; + +typedef struct { + UINT8 Status; ///< Indicates whether this channel should be used. + UINT8 ChannelId; + UINT8 DimmCount; ///< Number of valid DIMMs that exist in the channel. + MRC_CH_TIMING Timing[MAX_PROFILE_NUM]; ///< The channel timing values. + DIMM_INFO DimmInfo[MAX_DIMM]; ///< Save the DIMM output characteristics. + MRC_TA_TIMING tRd2Rd; ///< Read-to-Read Turn Around Timings + MRC_TA_TIMING tRd2Wr; ///< Read-to-Write Turn Around Timings + MRC_TA_TIMING tWr2Rd; ///< Write-to-Read Turn Around Timings + MRC_TA_TIMING tWr2Wr; ///< Write-to-Write Turn Around Timings +} CHANNEL_INFO; + +typedef struct { + UINT8 Status; ///< Indicates whether this controller should be used. + UINT16 DeviceId; ///< The PCI device id of this memory controller. + UINT8 RevisionId; ///< The PCI revision id of this memory controller. + UINT8 ChannelCount; ///< Number of valid channels that exist on the controller. + CHANNEL_INFO ChannelInfo[MAX_CH]; ///< The following are channel level definitions. + MRC_TA_TIMING tRd2Rd; ///< Deprecated and moved to CHANNEL_INFO. Read-to-Read Turn Around Timings + MRC_TA_TIMING tRd2Wr; ///< Deprecated and moved to CHANNEL_INFO. Read-to-Write Turn Around Timings + MRC_TA_TIMING tWr2Rd; ///< Deprecated and moved to CHANNEL_INFO. Write-to-Read Turn Around Timings + MRC_TA_TIMING tWr2Wr; ///< Deprecated and moved to CHANNEL_INFO. Write-to-Write Turn Around Timings +} CONTROLLER_INFO; + +typedef struct { + UINT8 Revision; + UINT16 DataWidth; ///< Data width, in bits, of this memory device + /** As defined in SMBIOS 3.0 spec + Section 7.18.2 and Table 75 + **/ + UINT8 MemoryType; ///< DDR type: DDR3, DDR4, or LPDDR3 + UINT16 MaximumMemoryClockSpeed;///< The maximum capable speed of the device, in megahertz (MHz) + UINT16 ConfiguredMemoryClockSpeed; ///< The configured clock speed to the memory device, in megahertz (MHz) + /** As defined in SMBIOS 3.0 spec + Section 7.17.3 and Table 72 + **/ + UINT8 ErrorCorrectionType; + + SiMrcVersion Version; + BOOLEAN EccSupport; + UINT8 MemoryProfile; + UINT32 TotalPhysicalMemorySize; + UINT32 DefaultXmptCK[MAX_XMP_PROFILE_NUM];///< Stores the tCK value read from SPD XMP profiles if they exist. + UINT8 XmpProfileEnable; ///< If XMP capable DIMMs are detected, this will indicate which XMP Profiles are common among all DIMMs. + UINT8 Ratio; + UINT8 RefClk; + UINT32 VddVoltage[MAX_PROFILE_NUM]; + CONTROLLER_INFO Controller[MAX_NODE]; +} MEMORY_INFO_DATA_HOB; + +/** + Memory Platform Data Hob + + Revision 1: + - Initial version. + Revision 2: + - Added TsegBase, PrmrrSize, PrmrrBase, Gttbase, MmioSize, PciEBaseAddress fields +**/ +typedef struct { + UINT8 Revision; + UINT8 Reserved[3]; + UINT32 BootMode; + UINT32 TsegSize; + UINT32 TsegBase; + UINT32 PrmrrSize; + UINT32 PrmrrBase; + UINT32 GttBase; + UINT32 MmioSize; + UINT32 PciEBaseAddress; +#ifdef CPU_CFL + UINT32 GdxcIotBase; + UINT32 GdxcIotSize; + UINT32 GdxcMotBase; + UINT32 GdxcMotSize; +#endif //CPU_CFL +} MEMORY_PLATFORM_DATA; + +typedef struct { + EFI_HOB_GUID_TYPE EfiHobGuidType; + MEMORY_PLATFORM_DATA Data; + UINT8 *Buffer; +} MEMORY_PLATFORM_DATA_HOB; + +#pragma pack (pop) + +#endif // _MEM_INFO_HOB_H_ From 116a837818897d5f1f0c76021d48532133e8f5f6 Mon Sep 17 00:00:00 2001 From: Wim Vervoorn Date: Wed, 11 Dec 2019 11:54:33 +0100 Subject: [PATCH 0707/1242] mb: Use fixed value in RcompTarget structure Now RCOMP_TARGET_PARAMS is defined and used once in the definition of the RcompTarget structure. All other structures in these functions use a fixed value. Replace RCOMP_TARGET_PARAMS with fixed value. BUG=N/A TEST=build Change-Id: Ibe7c72c65975354433e9a0c613bda715eb782412 Signed-off-by: Wim Vervoorn Reviewed-on: https://review.coreboot.org/c/coreboot/+/37658 Reviewed-by: Frans Hendriks Tested-by: build bot (Jenkins) --- src/mainboard/asrock/h110m/romstage.c | 4 +--- src/mainboard/facebook/monolith/spd/spd.h | 2 -- src/mainboard/facebook/monolith/spd/spd_util.c | 3 +-- src/mainboard/intel/cannonlake_rvp/spd/spd.h | 2 -- src/mainboard/intel/cannonlake_rvp/spd/spd_util.c | 3 +-- src/mainboard/intel/icelake_rvp/spd/spd.h | 2 -- src/mainboard/intel/icelake_rvp/spd/spd_util.c | 6 +++--- src/mainboard/intel/kblrvp/spd/spd.h | 2 -- src/mainboard/intel/kblrvp/spd/spd_util.c | 3 +-- src/mainboard/intel/kunimitsu/spd/spd.h | 1 - src/mainboard/intel/kunimitsu/spd/spd_util.c | 4 ++-- src/mainboard/intel/saddlebrook/spd/spd.h | 2 -- src/mainboard/intel/saddlebrook/spd/spd_util.c | 3 +-- src/mainboard/razer/blade_stealth_kbl/spd/spd.h | 2 -- src/mainboard/razer/blade_stealth_kbl/spd/spd_util.c | 2 +- 15 files changed, 11 insertions(+), 30 deletions(-) diff --git a/src/mainboard/asrock/h110m/romstage.c b/src/mainboard/asrock/h110m/romstage.c index efbc650bf3..a068713fc2 100644 --- a/src/mainboard/asrock/h110m/romstage.c +++ b/src/mainboard/asrock/h110m/romstage.c @@ -18,8 +18,6 @@ #include #include -#define RCOMP_TARGET_PARAMS 0x5 - static void mainboard_fill_dq_map_data(void *dq_map_ch0, void *dq_map_ch1) { /* DQ byte map */ @@ -53,7 +51,7 @@ static void mainboard_fill_rcomp_res_data(void *rcomp_ptr) static void mainboard_fill_rcomp_strength_data(void *rcomp_strength_ptr) { /* Rcomp target */ - static const u16 RcompTarget[RCOMP_TARGET_PARAMS] = { + static const u16 RcompTarget[5] = { 100, 40, 40, 23, 40 }; memcpy(rcomp_strength_ptr, RcompTarget, sizeof(RcompTarget)); } diff --git a/src/mainboard/facebook/monolith/spd/spd.h b/src/mainboard/facebook/monolith/spd/spd.h index f2b6f2af70..e24be2fc22 100644 --- a/src/mainboard/facebook/monolith/spd/spd.h +++ b/src/mainboard/facebook/monolith/spd/spd.h @@ -17,8 +17,6 @@ #ifndef MAINBOARD_SPD_H #define MAINBOARD_SPD_H -#define RCOMP_TARGET_PARAMS 0x5 - void mainboard_fill_dq_map_data(void *dq_map_ptr); void mainboard_fill_dqs_map_data(void *dqs_map_ptr); void mainboard_fill_rcomp_res_data(void *rcomp_ptr); diff --git a/src/mainboard/facebook/monolith/spd/spd_util.c b/src/mainboard/facebook/monolith/spd/spd_util.c index 5ccc8107fb..b85454a788 100644 --- a/src/mainboard/facebook/monolith/spd/spd_util.c +++ b/src/mainboard/facebook/monolith/spd/spd_util.c @@ -49,8 +49,7 @@ void mainboard_fill_rcomp_res_data(void *rcomp_ptr) void mainboard_fill_rcomp_strength_data(void *rcomp_strength_ptr) { /* Rcomp target */ - static const u16 RcompTarget[RCOMP_TARGET_PARAMS] = { - 100, 40, 40, 23, 40 }; + static const u16 RcompTarget[5] = { 100, 40, 40, 23, 40 }; memcpy(rcomp_strength_ptr, RcompTarget, sizeof(RcompTarget)); } diff --git a/src/mainboard/intel/cannonlake_rvp/spd/spd.h b/src/mainboard/intel/cannonlake_rvp/spd/spd.h index 128eb64a3c..4193e9cb2f 100644 --- a/src/mainboard/intel/cannonlake_rvp/spd/spd.h +++ b/src/mainboard/intel/cannonlake_rvp/spd/spd.h @@ -17,8 +17,6 @@ #ifndef MAINBOARD_SPD_H #define MAINBOARD_SPD_H -#define RCOMP_TARGET_PARAMS 0x5 - void mainboard_fill_dq_map_ch0(void *dq_map_ptr); void mainboard_fill_dq_map_ch1(void *dq_map_ptr); void mainboard_fill_dqs_map_ch0(void *dqs_map_ptr); diff --git a/src/mainboard/intel/cannonlake_rvp/spd/spd_util.c b/src/mainboard/intel/cannonlake_rvp/spd/spd_util.c index 0c2f74781b..2499b32e2d 100644 --- a/src/mainboard/intel/cannonlake_rvp/spd/spd_util.c +++ b/src/mainboard/intel/cannonlake_rvp/spd/spd_util.c @@ -73,8 +73,7 @@ void mainboard_fill_rcomp_res_data(void *rcomp_ptr) void mainboard_fill_rcomp_strength_data(void *rcomp_strength_ptr) { /* Rcomp target */ - static const u16 RcompTarget[RCOMP_TARGET_PARAMS] = { - 80, 40, 40, 40, 30 }; + static const u16 RcompTarget[5] = { 80, 40, 40, 40, 30 }; memcpy(rcomp_strength_ptr, RcompTarget, sizeof(RcompTarget)); } diff --git a/src/mainboard/intel/icelake_rvp/spd/spd.h b/src/mainboard/intel/icelake_rvp/spd/spd.h index 9b55563209..fbc4919372 100644 --- a/src/mainboard/intel/icelake_rvp/spd/spd.h +++ b/src/mainboard/intel/icelake_rvp/spd/spd.h @@ -16,8 +16,6 @@ #ifndef MAINBOARD_SPD_H #define MAINBOARD_SPD_H -#define RCOMP_TARGET_PARAMS 0x5 - void mainboard_fill_dq_map_ch0(void *dq_map_ptr); void mainboard_fill_dq_map_ch1(void *dq_map_ptr); void mainboard_fill_dqs_map_ch0(void *dqs_map_ptr); diff --git a/src/mainboard/intel/icelake_rvp/spd/spd_util.c b/src/mainboard/intel/icelake_rvp/spd/spd_util.c index d7babbd082..cb4a7928e7 100644 --- a/src/mainboard/intel/icelake_rvp/spd/spd_util.c +++ b/src/mainboard/intel/icelake_rvp/spd/spd_util.c @@ -114,11 +114,11 @@ void mainboard_fill_rcomp_res_data(void *rcomp_ptr) void mainboard_fill_rcomp_strength_data(void *rcomp_strength_ptr) { /* Rcomp target */ - static const u16 RcompTarget_DDR4[RCOMP_TARGET_PARAMS] = { + static const u16 RcompTarget_DDR4[5] = { 100, 33, 32, 33, 28 }; - static const u16 RcompTarget_LPDDR4_Ax[RCOMP_TARGET_PARAMS] = { + static const u16 RcompTarget_LPDDR4_Ax[5] = { 80, 40, 40, 40, 30 }; - static const u16 RcompTarget_LPDDR4_Bx[RCOMP_TARGET_PARAMS] = { + static const u16 RcompTarget_LPDDR4_Bx[5] = { 60, 20, 20, 20, 20 }; switch (get_spd_index()) { diff --git a/src/mainboard/intel/kblrvp/spd/spd.h b/src/mainboard/intel/kblrvp/spd/spd.h index 316ff5eb40..e745a25f7b 100644 --- a/src/mainboard/intel/kblrvp/spd/spd.h +++ b/src/mainboard/intel/kblrvp/spd/spd.h @@ -20,8 +20,6 @@ #include #include -#define RCOMP_TARGET_PARAMS 0x5 - void mainboard_fill_dq_map_data(void *dq_map_ch0, void *dq_map_ch1); void mainboard_fill_dqs_map_data(void *dqs_map_ch0, void *dqs_map_ch1); void mainboard_fill_rcomp_res_data(void *rcomp_ptr); diff --git a/src/mainboard/intel/kblrvp/spd/spd_util.c b/src/mainboard/intel/kblrvp/spd/spd_util.c index 4795435a9c..a0a81ba06e 100644 --- a/src/mainboard/intel/kblrvp/spd/spd_util.c +++ b/src/mainboard/intel/kblrvp/spd/spd_util.c @@ -52,8 +52,7 @@ void mainboard_fill_rcomp_res_data(void *rcomp_ptr) void mainboard_fill_rcomp_strength_data(void *rcomp_strength_ptr) { /* Rcomp target */ - static const u16 RcompTarget[RCOMP_TARGET_PARAMS] = { - 100, 40, 40, 23, 40 }; + static const u16 RcompTarget[5] = { 100, 40, 40, 23, 40 }; memcpy(rcomp_strength_ptr, RcompTarget, sizeof(RcompTarget)); } diff --git a/src/mainboard/intel/kunimitsu/spd/spd.h b/src/mainboard/intel/kunimitsu/spd/spd.h index c6e47f084f..ad6453e7b8 100644 --- a/src/mainboard/intel/kunimitsu/spd/spd.h +++ b/src/mainboard/intel/kunimitsu/spd/spd.h @@ -41,7 +41,6 @@ /* PCH_MEM_CFG[3:0] */ #define MAX_MEMORY_CONFIG 0x10 -#define RCOMP_TARGET_PARAMS 0x5 #define K4E6E304EE_MEM_ID 0x3 static inline int get_spd_index(void) { diff --git a/src/mainboard/intel/kunimitsu/spd/spd_util.c b/src/mainboard/intel/kunimitsu/spd/spd_util.c index 05a0a86734..2fe4596e56 100644 --- a/src/mainboard/intel/kunimitsu/spd/spd_util.c +++ b/src/mainboard/intel/kunimitsu/spd/spd_util.c @@ -55,11 +55,11 @@ void mainboard_fill_rcomp_strength_data(void *rcomp_strength_ptr) mem_cfg_id = get_spd_index(); /* Rcomp target */ - static const u16 RcompTarget[RCOMP_TARGET_PARAMS] = { + static const u16 RcompTarget[5] = { 100, 40, 40, 23, 40 }; /* Strengthen the Rcomp Target Ctrl for 8GB K4E6E304EE -EGCF */ - static const u16 StrengthendRcompTarget[RCOMP_TARGET_PARAMS] = { + static const u16 StrengthendRcompTarget[5] = { 100, 40, 40, 21, 40 }; diff --git a/src/mainboard/intel/saddlebrook/spd/spd.h b/src/mainboard/intel/saddlebrook/spd/spd.h index 70a1f68ce8..d7936636df 100644 --- a/src/mainboard/intel/saddlebrook/spd/spd.h +++ b/src/mainboard/intel/saddlebrook/spd/spd.h @@ -17,8 +17,6 @@ #ifndef MAINBOARD_SPD_H #define MAINBOARD_SPD_H -#define RCOMP_TARGET_PARAMS 0x5 - void mainboard_fill_dq_map_data(void *dq_map_ch0, void *dq_map_ch1); void mainboard_fill_dqs_map_data(void *dqs_map_ch0, void *dqs_map_ch1); void mainboard_fill_rcomp_res_data(void *rcomp_ptr); diff --git a/src/mainboard/intel/saddlebrook/spd/spd_util.c b/src/mainboard/intel/saddlebrook/spd/spd_util.c index a09cebcf4e..b6cf08547a 100644 --- a/src/mainboard/intel/saddlebrook/spd/spd_util.c +++ b/src/mainboard/intel/saddlebrook/spd/spd_util.c @@ -49,7 +49,6 @@ void mainboard_fill_rcomp_res_data(void *rcomp_ptr) void mainboard_fill_rcomp_strength_data(void *rcomp_strength_ptr) { /* Rcomp target */ - static const u16 RcompTarget[RCOMP_TARGET_PARAMS] = { - 100, 40, 20, 20, 26 }; + static const u16 RcompTarget[5] = { 100, 40, 20, 20, 26 }; memcpy(rcomp_strength_ptr, RcompTarget, sizeof(RcompTarget)); } diff --git a/src/mainboard/razer/blade_stealth_kbl/spd/spd.h b/src/mainboard/razer/blade_stealth_kbl/spd/spd.h index 233d368567..36363cc702 100644 --- a/src/mainboard/razer/blade_stealth_kbl/spd/spd.h +++ b/src/mainboard/razer/blade_stealth_kbl/spd/spd.h @@ -21,8 +21,6 @@ #include #include "../gpio.h" -#define RCOMP_TARGET_PARAMS 0x5 - void mainboard_fill_dq_map_data(void *dq_map_ptr); void mainboard_fill_dqs_map_data(void *dqs_map_ptr); void mainboard_fill_rcomp_res_data(void *rcomp_ptr); diff --git a/src/mainboard/razer/blade_stealth_kbl/spd/spd_util.c b/src/mainboard/razer/blade_stealth_kbl/spd/spd_util.c index a6f31f0930..a81653f7fd 100644 --- a/src/mainboard/razer/blade_stealth_kbl/spd/spd_util.c +++ b/src/mainboard/razer/blade_stealth_kbl/spd/spd_util.c @@ -44,7 +44,7 @@ void mainboard_fill_rcomp_res_data(void *rcomp_ptr) void mainboard_fill_rcomp_strength_data(void *rcomp_strength_ptr) { /* Rcomp target */ - static const u16 RcompTarget[RCOMP_TARGET_PARAMS] = {100, 40, 40, 23, 40}; + static const u16 RcompTarget[5] = {100, 40, 40, 23, 40}; memcpy(rcomp_strength_ptr, RcompTarget, sizeof(RcompTarget)); } From 7b7bc59f2016264d02fa245341e3507539dcac8f Mon Sep 17 00:00:00 2001 From: Felix Held Date: Sun, 15 Dec 2019 13:53:48 +0100 Subject: [PATCH 0708/1242] device/pnp: introduce and use PNP_SKIP_FUNCTION -1 shouldn't be assigned to an unsigned variable, so use an otherwise unused constant here. Since 7 is the highest virtual LDN number, using 0xffff as PNP_SKIP_FUNCTION marker has no unwanted side effects. Change-Id: I5e31e7ef9dad5fedfd5552963c298336c533a5e9 Signed-off-by: Felix Held Reviewed-on: https://review.coreboot.org/c/coreboot/+/37741 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Rudolph --- src/device/pnp_device.c | 2 +- src/include/device/pnp.h | 1 + src/superio/smsc/smscsuperio/superio.c | 5 ++++- 3 files changed, 6 insertions(+), 2 deletions(-) diff --git a/src/device/pnp_device.c b/src/device/pnp_device.c index 28a45d0692..1852fc1b16 100644 --- a/src/device/pnp_device.c +++ b/src/device/pnp_device.c @@ -370,7 +370,7 @@ void pnp_enable_devices(struct device *base_dev, struct device_operations *ops, /* Setup the ops and resources on the newly allocated devices. */ for (i = 0; i < functions; i++) { /* Skip logical devices this Super I/O doesn't have. */ - if (info[i].function == -1) + if (info[i].function == PNP_SKIP_FUNCTION) continue; path.pnp.device = info[i].function; diff --git a/src/include/device/pnp.h b/src/include/device/pnp.h index 69a0667445..fde4c9d1dd 100644 --- a/src/include/device/pnp.h +++ b/src/include/device/pnp.h @@ -34,6 +34,7 @@ extern struct device_operations pnp_ops; struct pnp_info { struct device_operations *ops; /* LDN-specific ops override */ +#define PNP_SKIP_FUNCTION 0xffff unsigned int function; /* Must be at least 16 bits (virtual LDNs)! */ unsigned int flags; #define PNP_IO0 0x000001 diff --git a/src/superio/smsc/smscsuperio/superio.c b/src/superio/smsc/smscsuperio/superio.c index aa5af38250..0e86683da3 100644 --- a/src/superio/smsc/smscsuperio/superio.c +++ b/src/superio/smsc/smscsuperio/superio.c @@ -280,7 +280,10 @@ static void enable_dev(struct device *dev) */ for (j = 0; j < ARRAY_SIZE(pnp_dev_info); j++) { fn = pnp_dev_info[j].function; - pnp_dev_info[j].function = logical_device_table[i].devs[fn]; + if (logical_device_table[i].devs[fn] != -1) + pnp_dev_info[j].function = logical_device_table[i].devs[fn]; + else + pnp_dev_info[j].function = PNP_SKIP_FUNCTION; } /* Enable the specified devices (if present on the chip). */ From 9c6e9c684f0b3770c9c08586985993750b5cb3b9 Mon Sep 17 00:00:00 2001 From: Felix Held Date: Sun, 15 Dec 2019 13:51:19 +0100 Subject: [PATCH 0709/1242] device/pnp: use correct width type for pnp_info.function Change-Id: Idbc1b37a8c98fe7fa24d8632e6a55c046e2d2869 Signed-off-by: Felix Held Reviewed-on: https://review.coreboot.org/c/coreboot/+/37740 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Rudolph --- src/include/device/pnp.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/include/device/pnp.h b/src/include/device/pnp.h index fde4c9d1dd..d459fd2fd0 100644 --- a/src/include/device/pnp.h +++ b/src/include/device/pnp.h @@ -35,7 +35,7 @@ extern struct device_operations pnp_ops; struct pnp_info { struct device_operations *ops; /* LDN-specific ops override */ #define PNP_SKIP_FUNCTION 0xffff - unsigned int function; /* Must be at least 16 bits (virtual LDNs)! */ + u16 function; /* Must be at least 16 bits (virtual LDNs)! */ unsigned int flags; #define PNP_IO0 0x000001 #define PNP_IO1 0x000002 From fc749b23ef41f6bb63370d1377bcdaac250848f6 Mon Sep 17 00:00:00 2001 From: Sergej Ivanov Date: Fri, 13 Dec 2019 23:04:47 +0000 Subject: [PATCH 0710/1242] biostar/am1ml: Switch away from ROMCC_BOOTBLOCK MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Switching was done by moving a SIO configuration and a clocks setup from 'romstage.c' to 'bootblock.c' TEST=Boots into Ubuntu Linux 16.04.6 without a problem. Change-Id: I7a972b531183b08af7b325bd686cf3eb7558082f Signed-off-by: Sergej Ivanov Reviewed-on: https://review.coreboot.org/c/coreboot/+/37719 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki --- src/mainboard/biostar/Kconfig | 3 - src/mainboard/biostar/am1ml/Kconfig | 4 -- src/mainboard/biostar/am1ml/Kconfig.name | 4 +- src/mainboard/biostar/am1ml/Makefile.inc | 2 + .../biostar/am1ml/{romstage.c => bootblock.c} | 70 +++---------------- 5 files changed, 14 insertions(+), 69 deletions(-) rename src/mainboard/biostar/am1ml/{romstage.c => bootblock.c} (54%) diff --git a/src/mainboard/biostar/Kconfig b/src/mainboard/biostar/Kconfig index 6469d4e6b5..43896a3f1f 100644 --- a/src/mainboard/biostar/Kconfig +++ b/src/mainboard/biostar/Kconfig @@ -20,9 +20,6 @@ choice source "src/mainboard/biostar/*/Kconfig.name" -config BIOSTAR_BOARDS_DISABLED - bool "Boards from vendor are disabled" - endchoice source "src/mainboard/biostar/*/Kconfig" diff --git a/src/mainboard/biostar/am1ml/Kconfig b/src/mainboard/biostar/am1ml/Kconfig index 866fc66e5d..9eaa6fb98c 100644 --- a/src/mainboard/biostar/am1ml/Kconfig +++ b/src/mainboard/biostar/am1ml/Kconfig @@ -14,15 +14,11 @@ # GNU General Public License for more details. # -config BOARD_BIOSTAR_AM1ML - def_bool n - if BOARD_BIOSTAR_AM1ML config BOARD_SPECIFIC_OPTIONS def_bool y select BOARD_ROMSIZE_KB_4096 - #select ROMCC_BOOTBLOCK select CPU_AMD_AGESA_FAMILY16_KB select FORCE_AM1_SOCKET_SUPPORT select GFXUMA diff --git a/src/mainboard/biostar/am1ml/Kconfig.name b/src/mainboard/biostar/am1ml/Kconfig.name index 0980c2e85d..da7a677c9e 100644 --- a/src/mainboard/biostar/am1ml/Kconfig.name +++ b/src/mainboard/biostar/am1ml/Kconfig.name @@ -1,2 +1,2 @@ -#config BOARD_BIOSTAR_AM1ML -# bool"AM1ML" +config BOARD_BIOSTAR_AM1ML + bool"AM1ML" diff --git a/src/mainboard/biostar/am1ml/Makefile.inc b/src/mainboard/biostar/am1ml/Makefile.inc index f8895faa92..4dde2cfd1e 100644 --- a/src/mainboard/biostar/am1ml/Makefile.inc +++ b/src/mainboard/biostar/am1ml/Makefile.inc @@ -13,6 +13,8 @@ # GNU General Public License for more details. # +bootblock-y += bootblock.c + romstage-y += buildOpts.c romstage-y += BiosCallOuts.c romstage-y += OemCustomize.c diff --git a/src/mainboard/biostar/am1ml/romstage.c b/src/mainboard/biostar/am1ml/bootblock.c similarity index 54% rename from src/mainboard/biostar/am1ml/romstage.c rename to src/mainboard/biostar/am1ml/bootblock.c index 6c1581bbcb..f198fe6809 100644 --- a/src/mainboard/biostar/am1ml/romstage.c +++ b/src/mainboard/biostar/am1ml/bootblock.c @@ -1,26 +1,19 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * Copyright (C) 2015 Sergej Ivanov - * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; version 2 of the License. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. */ -#include +#include +#include #include -#include -#include -#include -#include -#include #include #include @@ -28,10 +21,6 @@ #define GPIO_DEV PNP_DEV(0x2e, IT8728F_GPIO) #define ENVC_DEV PNP_DEV(0x2e, IT8728F_EC) -#define MMIO_NON_POSTED_START 0xfed00000 -#define MMIO_NON_POSTED_END 0xfedfffff -#define SB_MMIO_MISC32(x) *(volatile u32 *)(AMD_SB_ACPI_MMIO_ADDR + 0xE00 + (x)) - static void ite_evc_conf(pnp_devfn_t dev) { pnp_enter_conf_state(dev); @@ -70,28 +59,13 @@ static void ite_gpio_conf(pnp_devfn_t dev) pnp_exit_conf_state(dev); } -void board_BeforeAgesa(struct sysinfo *cb) +void bootblock_mainboard_early_init(void) { - u32 val, t32; - u8 byte; - pci_devfn_t dev; - u32 *addr32; + volatile u32 *addr32; + u32 t32; - /* In Hudson RRG, PMIOxD2[5:4] is "Drive strength control for - * LpcClk[1:0]". To be consistent with Parmer, setting to 4mA - * even though the register is not documented in the Kabini BKDG. - * Otherwise the serial output is bad code. - */ - outb(0xD2, 0xcd6); - outb(0x00, 0xcd7); - - /* Set LPC decode enables. */ - pci_devfn_t dev2 = PCI_DEV(0, 0x14, 3); - pci_write_config32(dev2, 0x44, 0xff03ffd5); - - /* Enable the AcpiMmio space */ - outb(0x24, 0xcd6); - outb(0x1, 0xcd7); + /* Disable PCI-PCI bridge and release GPIO32/33 for other uses. */ + pm_write8(0xea, 0x1); /* Set auxiliary output clock frequency on OSCOUT1 pin to be 48MHz */ addr32 = (u32 *)0xfed80e28; @@ -105,35 +79,11 @@ void board_BeforeAgesa(struct sysinfo *cb) t32 &= 0xffffbffb; *addr32 = t32; - /* enable SIO LPC decode */ - dev = PCI_DEV(0, 0x14, 3); - byte = pci_read_config8(dev, 0x48); - byte |= 3; /* 2e, 2f */ - pci_write_config8(dev, 0x48, byte); - - /* enable serial decode */ - byte = pci_read_config8(dev, 0x44); - byte |= (1 << 6); /* 0x3f8 */ - pci_write_config8(dev, 0x44, byte); - - /* This functions configure SIO as it been done under vendor bios */ - printk(BIOS_DEBUG, "ITE CONFIG ENVC\n"); + /* Configure SIO as made under vendor BIOS */ ite_evc_conf(ENVC_DEV); - printk(BIOS_DEBUG, "ITE CONFIG GPIO\n"); ite_gpio_conf(GPIO_DEV); - printk(BIOS_DEBUG, "ITE CONFIG DONE\n"); - + /* Enable serial output on it8728f */ ite_kill_watchdog(GPIO_DEV); ite_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); - - /* On Larne, after LpcClkDrvSth is set, it needs some time to be stable, because of the buffer ICS551M */ - int i; - for (i = 0; i < 200000; i++) - val = inb(0xcd6); - - outb(0xEA, 0xCD6); - outb(0x1, 0xcd7); - - post_code(0x50); } From b4a68a5a28684b99657ae94b9bcb745ae2023863 Mon Sep 17 00:00:00 2001 From: Edward O'Callaghan Date: Sun, 15 Dec 2019 13:30:38 +1100 Subject: [PATCH 0711/1242] src/soc/intel/cannonlake: Bump MAX_CPU from 8->12 This impacts boards: hatch (&variants) and drallion. Some variants like Puff can have up to 12 cores. coreboot should take the min() where MAX_CPU is the upper bound. Further to that, boards themseleves shouldn't be setting the MAX_CPUS, the chipset should be and so do that. BRANCH=none BUG=b:146255011 TEST=./util/abuild/abuild -p none -t google/hatch -x -a Change-Id: I284d027886f662ebb8414ea92540916ed19bc797 Signed-off-by: Edward O'Callaghan Reviewed-on: https://review.coreboot.org/c/coreboot/+/37725 Tested-by: build bot (Jenkins) Reviewed-by: EricR Lai Reviewed-by: Shelley Chen Reviewed-by: Mathew King --- src/mainboard/google/drallion/Kconfig | 4 ---- src/mainboard/google/hatch/Kconfig | 4 ---- src/soc/intel/cannonlake/Kconfig | 4 ++++ 3 files changed, 4 insertions(+), 8 deletions(-) diff --git a/src/mainboard/google/drallion/Kconfig b/src/mainboard/google/drallion/Kconfig index fd7b6b19d4..e9e26a3832 100644 --- a/src/mainboard/google/drallion/Kconfig +++ b/src/mainboard/google/drallion/Kconfig @@ -71,10 +71,6 @@ config MAINBOARD_PART_NUMBER string default "Drallion" if BOARD_GOOGLE_DRALLION -config MAX_CPUS - int - default 8 - config UART_FOR_CONSOLE int default 0 if BOARD_GOOGLE_DRALLION diff --git a/src/mainboard/google/hatch/Kconfig b/src/mainboard/google/hatch/Kconfig index 98a0174dfe..dff5273714 100644 --- a/src/mainboard/google/hatch/Kconfig +++ b/src/mainboard/google/hatch/Kconfig @@ -98,10 +98,6 @@ config MAINBOARD_PART_NUMBER default "Puff" if BOARD_GOOGLE_PUFF default "Stryke" if BOARD_GOOGLE_STRYKE -config MAX_CPUS - int - default 8 - config OVERRIDE_DEVICETREE string default "variants/helios_diskswap/overridetree.cb" if BOARD_GOOGLE_HELIOS_DISKSWAP diff --git a/src/soc/intel/cannonlake/Kconfig b/src/soc/intel/cannonlake/Kconfig index 6d635ade3d..8820508259 100644 --- a/src/soc/intel/cannonlake/Kconfig +++ b/src/soc/intel/cannonlake/Kconfig @@ -108,6 +108,10 @@ config CPU_SPECIFIC_OPTIONS select FSP_T_XIP if FSP_CAR select HECI_DISABLE_USING_SMM if !SOC_INTEL_COFFEELAKE && !SOC_INTEL_WHISKEYLAKE && !SOC_INTEL_COMETLAKE +config MAX_CPUS + int + default 12 + config DCACHE_RAM_BASE default 0xfef00000 From c7305f7b372336fd0c07232f0bfdd2b785bd1f0f Mon Sep 17 00:00:00 2001 From: Matt DeVillier Date: Sun, 15 Dec 2019 01:06:48 -0600 Subject: [PATCH 0712/1242] mb/google/jecht: Add VBTs for all variants Add VBTs for jecht variants, extracted from VGA BIOS from stock firmware images using intelvbttool, zero-padded to 0x11ff bytes to make the Intel BMP editor happy. Use a common VBT for all except tidus, since it differs from the others. Change-Id: I570bdb749ef7d49f41539074220bb16c9c100342 Signed-off-by: Matt DeVillier Reviewed-on: https://review.coreboot.org/c/coreboot/+/37735 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber --- src/mainboard/google/jecht/Kconfig | 6 ++++++ src/mainboard/google/jecht/data.vbt | Bin 0 -> 4608 bytes .../google/jecht/variants/tidus/data.vbt | Bin 0 -> 4608 bytes 3 files changed, 6 insertions(+) create mode 100644 src/mainboard/google/jecht/data.vbt create mode 100644 src/mainboard/google/jecht/variants/tidus/data.vbt diff --git a/src/mainboard/google/jecht/Kconfig b/src/mainboard/google/jecht/Kconfig index 6d1fda93f8..71143c9401 100644 --- a/src/mainboard/google/jecht/Kconfig +++ b/src/mainboard/google/jecht/Kconfig @@ -6,6 +6,7 @@ config BOARD_GOOGLE_BASEBOARD_JECHT select HAVE_ACPI_TABLES select HAVE_OPTION_TABLE select HAVE_ACPI_RESUME + select INTEL_GMA_HAVE_VBT select MAINBOARD_HAS_CHROMEOS select MAINBOARD_HAS_LIBGFXINIT select MAINBOARD_HAS_LPC_TPM @@ -46,6 +47,11 @@ config VGA_BIOS_FILE string default "pci8086,0406.rom" +# Override the default variant behavior, since the data.vbt is the same +# for all variants except tidus +config INTEL_GMA_VBT_FILE + default "src/mainboard/$(MAINBOARDDIR)/data.vbt" if !BOARD_GOOGLE_TIDUS + config MAINBOARD_SMBIOS_MANUFACTURER string default "GOOGLE" diff --git a/src/mainboard/google/jecht/data.vbt b/src/mainboard/google/jecht/data.vbt new file mode 100644 index 0000000000000000000000000000000000000000..300035cfbd881084c7707b53b5685d2820323d42 GIT binary patch literal 4608 zcmdT{U2GIp6h3!mc6WAmW_CLi*sf4dp@D5}%XC{SHZ{(+TimS+-TqK2L0NDYL@Sg6 zrbZK1tqI1zeJ}vW?n~`Gm>-J{HehmS3vS%EbI(|QT_S(rse}8*G1HU6_~Vb~$MO?9 z4(4+>H1bd!Ij5#{AKEjP!%c^t-kG21L{3D}*xKIG){bblu8ZBjE@rmgix_L`G&?%m z+B7B6+ta@>lS;>jQ~jH;e-IO?q4>~H@5b)*BbXWNPo}z4!@UVjneRu>zVT-#_UwM* zAVzx{FlL%&GjX<}oig_9n;37w_}CZ@@|XiSm_Lx8cqX4~(G<>c3S@}^Fc0{c#o+fC z_+_TbQc|{}GJ2R4XI34Sa<+vQo@yV3?MydI_5(41u6AkO1mrI6diRgsVJ3oh6J-la}}44jw*849-MH)0680leu5L+4xb zZF=Xbxwv(^0z~SIv;xdnd&m0DE~`7SA=#JC3=WTsZrxUR;l-DxBJkVEMN-n42`Qx( zCd4SbCkpV9xE?l2v+$!IL03XhM`$N(_sQ_S&wx(|X9(XCe)1{sD?yMIPzg1J)r4lk zeS{QYi0~+3H(@{FIl{|?HwniG?-M>Id`kF|aF*~j;d_Gj5d2mW3gENzE-+VDIT}I| zywL!K>-YccOrPTFfU6hj{GzT>$>)PVO6S5*D#;J<3@l=x;bjSzDe3C8twk~8 zwuebm9E`f{QpumCW{j@ecUR8xHSb8Nbf;T^Gf-EcPPqFDd4HH^d?nXqDUkKo0KqeH zAdh z%<#L#u0p~ps(!8*s=b)!o7L}vH{vvWUGvWC^?&(f*~7F{M7uV~d>7hcPU!&Y4Vmqk z9eeX*n|3^%uduN^3Aq}u;;_aHAL($&!e%2J9RSlZ$Co&s+7H)F&J9G?SffYhJ;?_x zbLULVvQEu=!cpirEINa!b{zJAeX5YfiuNid%j+CDYE2Ys;0j$eP-FVP%7~cex9|9<=MnqNWRqRuZZK|?M#n)8h zT~+x|#dE4Lrz)3J3~9zHO=;3_P&0CxvRA{mG~)wJnbGiqW?a;iUo;HsMx(B@>$p`n z#&qQw9gpkANnQC&$M1CGXI;6XBL=cxMhn%>2-S8R7HGUkR9?Do&akjV@SX1LYChkb zq3eddSXfecg|L6YsFR*ZMGTWT5D8hKa#7-y#V-35GAt}&oWX04gXNv6AcuuTkJmK2 z7ONwkN=9;5-N=ans5Lhf-MI+UNEYqWh*GI!9G-6}PG=*vmWgh;rrDH=e!CY1UnRYW zb`_?_XI2wKBYz8k7(7M$a8{>1Qx&X-cN(V84@|8xGsl*f8AJ$hTeZBEFqnRL2R?v$}5tz>4a#J;X_*?ckh(+3ultaO{-d+zk-kU;a zA-sQmvo+d$buL5*+6+{}yf@z$4Hjezup}D_Rq?l+9H^R-s1+XJcT5=X)U|TYe(?5% z*23tCzFGP|aa-=C>!fKZyt0APNYVd^&5(f{G_kkgqS!J6aHK4EhI#F1{u`}70d`mk ArT_o{ literal 0 HcmV?d00001 diff --git a/src/mainboard/google/jecht/variants/tidus/data.vbt b/src/mainboard/google/jecht/variants/tidus/data.vbt new file mode 100644 index 0000000000000000000000000000000000000000..dce9168d22c8c81408f72e348d76da5959919970 GIT binary patch literal 4608 zcmdT`Z){Ul6hF7`wS9ekuWR2Xbal)-SfHERcpFQZ%Z#sEH`~#%?hm69bOl-vE!)@z znbCx*Gr?%I9|!?MU| z*LW&P`vzVPQpPEZt%vrflXUB$1G`hB&6E*gG_7x}+tf&@8rayN;;)|Bo0{tb&6}EJ zG1T7H-4%;OgZ+{2t+czBh9Z5zzP|RZ*61rV*4rJ9v_|^dL$WwOkGA2Fw?_Bxdwrbx z+p1`Ts;affSx@yL)3)K!kvbYor)e*X8Kb?avDE0{RI*MM8OLQ1cmhDIU?)J}j|OlE zL=yP0p!o%AC47)*6@-R(O(uLh;gh@;AzBroQC_R$X$?=^V37&%02KmUnJ`C1nMQg} zZ)>2pG3fgQxZUVZ)S_#4!+=>cfHe&v)Ogl> z8~Z#mpKLv?01oHEmx0>Q7-(v4(ON?t;m&BRw|^kMV`t{w_uilM!Gnu9Bz?*YhUOwF z*u`=f<@|7lv%q<-3A*?hIPakFox=?`5qA-Tb^*@X75EBq74Z||H@gVGBP@al5~38b z4pEEPjEErm5U(QkAr2zmMtp$y6mb%97V!n*Ys5E*Ylt5ZHxaf&@E~W&fL$MNhM3x8 zXmIoJNfl&Hnf_Cz-*LxSKGD=pQ!kkGl4dSvx5LBSbuZ*{!i#JK8ZuzsNXTRgn>wm% zj*FS?e$*_#akHJvITF}x!0YMV#cOQO8M=k-4ikcy!b3kfH*OnPtrm(t0!MxU z^Uwd+42N0l3MBMk^)p40{!%PTPJ_*7{AF*Mk9l1Gm;bEVf?I{tYlD!la_XcDAleZd zjO`jqrMK=nkSegTIt8^Oyoq7JyktCQIkmxP`=89 zS%f$Qig2@PfA_#7tfw6_p7|DEB~7e$$xUp4*9376K0JZo!WR z9wc0c5QHI^CuYKJf8ixixS;uOoAwAHEfJH^+WbkeCDcZyR^dc~>y=oEi-QbAIDl2|FxPD$A* ziF+mbv80@q#B&n8E-7=8cw3@wSy?NKH8Sm$m82{V$@G}4d@hUAGM$x`Te5gpre2p) z?GhVZbcahxyTrpTddj6-bcvT-^cRsx}X>B0vQ&UAjV+R^Pt(L3mC)VlEo^L zUP+|^YayB3TQP8<2g=osthp9m%w$%7m*7we$-_H!*{OuDTvMr8Y;iUDtV5qg#$L!Q z{4JTOk?D2FP|bP)AcHllzgnd!>tq4@;j^l#8$FY2)!50^c?J%g%$77;Aq;A@Hj|i4 zs@@*s84_p?{BaR_sZ_@X}(r44s zobeuPs@3APkJf^NBAo$Cm~HuUQKdm51H}oq+rxSpW58;PA{F=oUNK?M9|T*cdjrHT vbk5+n|5Lf=9+R49;KL3~W(2?ew?Pb&P(zNxEv{}F;Amb}hRHU?%9lR@A-E0P literal 0 HcmV?d00001 From 021462bb263040470c619c1360a44cd747bf86e8 Mon Sep 17 00:00:00 2001 From: Matt DeVillier Date: Mon, 16 Dec 2019 02:01:19 -0600 Subject: [PATCH 0713/1242] mb/google/rambi: add VBTs for variants Add VBTs for all rambi variants, extracted from VGA BIOS from stock firmware images using intelvbttool. Test: boot several rambi variants using MrChromebox edk2/master branch with Baytrail GOP driver and extracted VBTs. Change-Id: I401ae5accd852fc5211092a5944fc85871b642ae Signed-off-by: Matt DeVillier Reviewed-on: https://review.coreboot.org/c/coreboot/+/37761 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber --- src/mainboard/google/rambi/Kconfig | 1 + .../google/rambi/variants/banjo/data.vbt | Bin 0 -> 3603 bytes .../google/rambi/variants/candy/data.vbt | Bin 0 -> 3607 bytes .../google/rambi/variants/clapper/data.vbt | Bin 0 -> 3603 bytes .../google/rambi/variants/enguarde/data.vbt | Bin 0 -> 3603 bytes .../google/rambi/variants/glimmer/data.vbt | Bin 0 -> 3603 bytes .../google/rambi/variants/gnawty/data.vbt | Bin 0 -> 3603 bytes .../google/rambi/variants/heli/data.vbt | Bin 0 -> 3607 bytes src/mainboard/google/rambi/variants/kip/data.vbt | Bin 0 -> 3603 bytes .../google/rambi/variants/ninja/data.vbt | Bin 0 -> 3607 bytes .../google/rambi/variants/orco/data.vbt | Bin 0 -> 3603 bytes .../google/rambi/variants/quawks/data.vbt | Bin 0 -> 3603 bytes .../google/rambi/variants/squawks/data.vbt | Bin 0 -> 3603 bytes .../google/rambi/variants/sumo/data.vbt | Bin 0 -> 3607 bytes .../google/rambi/variants/swanky/data.vbt | Bin 0 -> 4608 bytes .../google/rambi/variants/winky/data.vbt | Bin 0 -> 3607 bytes 16 files changed, 1 insertion(+) create mode 100644 src/mainboard/google/rambi/variants/banjo/data.vbt create mode 100644 src/mainboard/google/rambi/variants/candy/data.vbt create mode 100644 src/mainboard/google/rambi/variants/clapper/data.vbt create mode 100644 src/mainboard/google/rambi/variants/enguarde/data.vbt create mode 100644 src/mainboard/google/rambi/variants/glimmer/data.vbt create mode 100644 src/mainboard/google/rambi/variants/gnawty/data.vbt create mode 100644 src/mainboard/google/rambi/variants/heli/data.vbt create mode 100644 src/mainboard/google/rambi/variants/kip/data.vbt create mode 100644 src/mainboard/google/rambi/variants/ninja/data.vbt create mode 100644 src/mainboard/google/rambi/variants/orco/data.vbt create mode 100644 src/mainboard/google/rambi/variants/quawks/data.vbt create mode 100644 src/mainboard/google/rambi/variants/squawks/data.vbt create mode 100644 src/mainboard/google/rambi/variants/sumo/data.vbt create mode 100644 src/mainboard/google/rambi/variants/swanky/data.vbt create mode 100644 src/mainboard/google/rambi/variants/winky/data.vbt diff --git a/src/mainboard/google/rambi/Kconfig b/src/mainboard/google/rambi/Kconfig index fc6e28e519..7a23a7d09a 100644 --- a/src/mainboard/google/rambi/Kconfig +++ b/src/mainboard/google/rambi/Kconfig @@ -9,6 +9,7 @@ config BOARD_GOOGLE_BASEBOARD_RAMBI select HAVE_ACPI_TABLES select HAVE_OPTION_TABLE select HAVE_ACPI_RESUME + select INTEL_GMA_HAVE_VBT if !BOARD_GOOGLE_RAMBI select MAINBOARD_HAS_CHROMEOS select MAINBOARD_HAS_LPC_TPM select MAINBOARD_HAS_TPM1 diff --git a/src/mainboard/google/rambi/variants/banjo/data.vbt b/src/mainboard/google/rambi/variants/banjo/data.vbt new file mode 100644 index 0000000000000000000000000000000000000000..01249f19c07261fed47f2f1c250f959d30c00495 GIT binary patch literal 3603 zcmds3Z)jUp6hH6fC3){A>C%_Z#aQcE9V4w>`;v8~mWnq`TAP}#Y1+kZh|9V}H_g_r z?M8)SqZa8vB(S1WMEXHw43VNB`y~A$6vQ!9_Dv~>W9-X@_(8_p^W2xLoz~4D44uE^ z+&|}@`@83!d+vL0Te@o)(~(4?dv7}4{R|3Z!2n;?B$XS{6(1PdABzk}_ID))qEF*z z@BsYixp@U3D@p#^kP+GyKRT7m2U880PNcDaZ1iwG*AmN3zBDy9j>%{oBL@%W^0|ov zQ@Jb-rJstR;PkMrehzj8A{=5Iy7}6|<%SpJlOQVqTUBuQ%SsON_?Iexvak<8MnGCa@ZS#O zTL*P(_F6i$N(H{jh{pHTU@_1H`$E~kn#{#0;cD4Hv}=C63NtXdSu_Tg;!sDeJ%hurpfM)u2e||JYuhdb8--Vl4ZCmx5Fvh3d|}7e5&~2 zYm&<(m+TC#kz6NH91N;R{3P`xO(bn3oTQIrnB+N!#6jWfLv)gV zxllD}%h27{dEe^#5H?xY>Xu?-UGo7r0vpx;9Zf)N;Gyr}f|HT_BF+2OTl2miOE
s&N%VBQ(twmD^B#P zdcDe;R7|OQR%J(3Tu}9oRJNqzMODA7vY%D-YkH%`S~c9K>3NNv(C~dt|3qWwH2gu+ zuW9VMhRF0VW1S2~nLfqXD-1tm`sa)-GrYv~Um25K7n)-yNoDG{WgYFt{=9E18lH<%#ZTd!QnQ zX&elAx%V~(sc08$6*8P@nO+?XZ094V*L{$R;-w94?pUh8hu$Z-F}f7ye0iP0QF{Bi z)7B@4AiFb6^ZBjmvx87)^c2fyAtG6{9$4f`C2^Q(E-q#Qb=<)6Sx_XEq9zt~7o3&s zBG_429AA2r7#d5iinAzM? z14rKqct+0NyVCpgI{ zDGI1kj*^EIA!LaP3J=JSRm4M7@c@X22o3H=)T9z%GDlf0--hSig#>_Q>t}$YVppP))l8(yeHPx z6ORW-rZ+t_n9t^tW7(k{bZCTTvZKk-(cZySZWqmu4E1MI*|FYCfUKmEo}7BNdg!Tx zGc=lRr7=y@wjyR1V%kj8k@9r8`b@dh5g;bWGRTquAhdrCjlgYjWT#bwvvI1ekh|lvl~zZihDR9 z2`&~*vo9NgBcPW%vx_@g2#m`BKiLN6@|_2pT-#Zh?1PQTWE?f*)Po@QQdI<|GZyN+I|J`7-jiZUR@4 ze?gW!1R9V-$eWPckrT)ac>s9~c@OeI{T!5%la}*aPy$~{AF~5Mh}Eu;yOozVR*f8!}v4=h9N&}Mi4|KtbovL?Fb=zj__F& zslDEevstOAy*3P`h|3s$?%YT|f|c$z4BUv*-75K;U;uB2C~wyzJdvFM#%lo)W`P9f zA;>${yeWV!?}%h{kwKDy;V1yZFFJF=N3wu78e|571OfwztvN+t^{cvnOLAT@!)Ub0 z^ob(}B^%RJ2dFe&3`n8w*;HAy7xUk$4A?J>LWhV@1sY2s_r8%`sk8R{lG^)_66Fm zO1kTk`Ga&@GK{t9C*}mJv;9;Y|C^S^3u@HYQRo_v(5T*Q?bVW)b78%Z{N{DOZ2UHb;-n78J8Jb}xP@udJ`1d*R8x2sy4Oh-(d~MDYUx2l zXtM$}&!WcPQ~tVp-a$XS(OSPSJikfHzrJAwK?EOEB4+d)6Ldi2oI?yYQm>*`sEu#O|( z`-!)fxwsV>Mk|A&4o$^iu+cK&Sp-elpXuI$)%xcom@JaiO11Lq+yzIf+G p<4@GS9!~aQF|+tTY$xQQ1nt7Ba9QkF0$5m~yF%Q?@3_?^zX4MUZFT?v literal 0 HcmV?d00001 diff --git a/src/mainboard/google/rambi/variants/clapper/data.vbt b/src/mainboard/google/rambi/variants/clapper/data.vbt new file mode 100644 index 0000000000000000000000000000000000000000..01249f19c07261fed47f2f1c250f959d30c00495 GIT binary patch literal 3603 zcmds3Z)jUp6hH6fC3){A>C%_Z#aQcE9V4w>`;v8~mWnq`TAP}#Y1+kZh|9V}H_g_r z?M8)SqZa8vB(S1WMEXHw43VNB`y~A$6vQ!9_Dv~>W9-X@_(8_p^W2xLoz~4D44uE^ z+&|}@`@83!d+vL0Te@o)(~(4?dv7}4{R|3Z!2n;?B$XS{6(1PdABzk}_ID))qEF*z z@BsYixp@U3D@p#^kP+GyKRT7m2U880PNcDaZ1iwG*AmN3zBDy9j>%{oBL@%W^0|ov zQ@Jb-rJstR;PkMrehzj8A{=5Iy7}6|<%SpJlOQVqTUBuQ%SsON_?Iexvak<8MnGCa@ZS#O zTL*P(_F6i$N(H{jh{pHTU@_1H`$E~kn#{#0;cD4Hv}=C63NtXdSu_Tg;!sDeJ%hurpfM)u2e||JYuhdb8--Vl4ZCmx5Fvh3d|}7e5&~2 zYm&<(m+TC#kz6NH91N;R{3P`xO(bn3oTQIrnB+N!#6jWfLv)gV zxllD}%h27{dEe^#5H?xY>Xu?-UGo7r0vpx;9Zf)N;Gyr}f|HT_BF+2OTl2miOE
s&N%VBQ(twmD^B#P zdcDe;R7|OQR%J(3Tu}9oRJNqzMODA7vY%D-YkH%`S~c9K>3NNv(C~dt|3qWwH2gu+ zuW9VMhRF0VW1S2~nLfqXD-1tm`sa)-GrYv~Um25K7n)-yNoDG{WgYFt{=9E18lH<%#ZTd!QnQ zX&elAx%V~(sc08$6*8P@nO+?XZ094V*L{$R;-w94?pUh8hu$Z-F}f7ye0iP0QF{Bi z)7B@4AiFb6^ZBjmvx87)^c2fyAtG6{9$4f`C2^Q(E-q#Qb=<)6Sx_XEq9zt~7o3&s zBG_429AA2r7#d5iinAzM? z14rKqct+0NyVCpC%_Z#aQcE9V4w>`;v8~mWnq`TAP}#Y1+kZh|9V}H_g_r z?M8)SqZa8vB(S1WMEXHw43VNB`y~A$6vQ!9_Dv~>W9-X@_(8_p^W2xLoz~4D44uE^ z+&|}@`@83!d+vL0Te@o)(~(4?dv7}4{R|3Z!2n;?B$XS{6(1PdABzk}_ID))qEF*z z@BsYixp@U3D@p#^kP+GyKRT7m2U880PNcDaZ1iwG*AmN3zBDy9j>%{oBL@%W^0|ov zQ@Jb-rJstR;PkMrehzj8A{=5Iy7}6|<%SpJlOQVqTUBuQ%SsON_?Iexvak<8MnGCa@ZS#O zTL*P(_F6i$N(H{jh{pHTU@_1H`$E~kn#{#0;cD4Hv}=C63NtXdSu_Tg;!sDeJ%hurpfM)u2e||JYuhdb8--Vl4ZCmx5Fvh3d|}7e5&~2 zYm&<(m+TC#kz6NH91N;R{3P`xO(bn3oTQIrnB+N!#6jWfLv)gV zxllD}%h27{dEe^#5H?xY>Xu?-UGo7r0vpx;9Zf)N;Gyr}f|HT_BF+2OTl2miOE
s&N%VBQ(twmD^B#P zdcDe;R7|OQR%J(3Tu}9oRJNqzMODA7vY%D-YkH%`S~c9K>3NNv(C~dt|3qWwH2gu+ zuW9VMhRF0VW1S2~nLfqXD-1tm`sa)-GrYv~Um25K7n)-yNoDG{WgYFt{=9E18lH<%#ZTd!QnQ zX&elAx%V~(sc08$6*8P@nO+?XZ094V*L{$R;-w94?pUh8hu$Z-F}f7ye0iP0QF{Bi z)7B@4AiFb6^ZBjmvx87)^c2fyAtG6{9$4f`C2^Q(E-q#Qb=<)6Sx_XEq9zt~7o3&s zBG_429AA2r7#d5iinAzM? z14rKqct+0NyVCpC%_Z#aQcE9V4w>`;v8~mWnq`TAP}#Y1+kZh|9V}H_g_r z?M8)SqZa8vB(S1WMEXHw43VNB`y~A$6vQ!9_Dv~>W9-X@_(8_p^W2xLoz~4D44uE^ z+&|}@`@83!d+vL0Te@o)(~(4?dv7}4{R|3Z!2n;?B$XS{6(1PdABzk}_ID))qEF*z z@BsYixp@U3D@p#^kP+GyKRT7m2U880PNcDaZ1iwG*AmN3zBDy9j>%{oBL@%W^0|ov zQ@Jb-rJstR;PkMrehzj8A{=5Iy7}6|<%SpJlOQVqTUBuQ%SsON_?Iexvak<8MnGCa@ZS#O zTL*P(_F6i$N(H{jh{pHTU@_1H`$E~kn#{#0;cD4Hv}=C63NtXdSu_Tg;!sDeJ%hurpfM)u2e||JYuhdb8--Vl4ZCmx5Fvh3d|}7e5&~2 zYm&<(m+TC#kz6NH91N;R{3P`xO(bn3oTQIrnB+N!#6jWfLv)gV zxllD}%h27{dEe^#5H?xY>Xu?-UGo7r0vpx;9Zf)N;Gyr}f|HT_BF+2OTl2miOE
s&N%VBQ(twmD^B#P zdcDe;R7|OQR%J(3Tu}9oRJNqzMODA7vY%D-YkH%`S~c9K>3NNv(C~dt|3qWwH2gu+ zuW9VMhRF0VW1S2~nLfqXD-1tm`sa)-GrYv~Um25K7n)-yNoDG{WgYFt{=9E18lH<%#ZTd!QnQ zX&elAx%V~(sc08$6*8P@nO+?XZ094V*L{$R;-w94?pUh8hu$Z-F}f7ye0iP0QF{Bi z)7B@4AiFb6^ZBjmvx87)^c2fyAtG6{9$4f`C2^Q(E-q#Qb=<)6Sx_XEq9zt~7o3&s zBG_429AA2r7#d5iinAzM? z14rKqct+0NyVCpC%_Z#aQcE9V4w>`;v8~mWnq`TAP}#Y1+kZh|9V}H_g_r z?M8)SqZa8vB(S1WMEXHw43VNB`y~A$6vQ!9_Dv~>W9-X@_(8_p^W2xLoz~4D44uE^ z+&|}@`@83!d+vL0Te@o)(~(4?dv7}4{R|3Z!2n;?B$XS{6(1PdABzk}_ID))qEF*z z@BsYixp@U3D@p#^kP+GyKRT7m2U880PNcDaZ1iwG*AmN3zBDy9j>%{oBL@%W^0|ov zQ@Jb-rJstR;PkMrehzj8A{=5Iy7}6|<%SpJlOQVqTUBuQ%SsON_?Iexvak<8MnGCa@ZS#O zTL*P(_F6i$N(H{jh{pHTU@_1H`$E~kn#{#0;cD4Hv}=C63NtXdSu_Tg;!sDeJ%hurpfM)u2e||JYuhdb8--Vl4ZCmx5Fvh3d|}7e5&~2 zYm&<(m+TC#kz6NH91N;R{3P`xO(bn3oTQIrnB+N!#6jWfLv)gV zxllD}%h27{dEe^#5H?xY>Xu?-UGo7r0vpx;9Zf)N;Gyr}f|HT_BF+2OTl2miOE
s&N%VBQ(twmD^B#P zdcDe;R7|OQR%J(3Tu}9oRJNqzMODA7vY%D-YkH%`S~c9K>3NNv(C~dt|3qWwH2gu+ zuW9VMhRF0VW1S2~nLfqXD-1tm`sa)-GrYv~Um25K7n)-yNoDG{WgYFt{=9E18lH<%#ZTd!QnQ zX&elAx%V~(sc08$6*8P@nO+?XZ094V*L{$R;-w94?pUh8hu$Z-F}f7ye0iP0QF{Bi z)7B@4AiFb6^ZBjmvx87)^c2fyAtG6{9$4f`C2^Q(E-q#Qb=<)6Sx_XEq9zt~7o3&s zBG_429AA2r7#d5iinAzM? z14rKqct+0NyVCpgI{ zDGI1kj*^EIA!LaP3J=JSRm4M7@c@X22o3H=)T9z%GDlf0--hSig#>_Q>t}$YVppP))l8(yeHPx z6ORW-rZ+t_n9t^tW7(k{bZCTTvZKk-(cZySZWqmu4E1MI*|FYCfUKmEo}7BNdg!Tx zGc=lRr7=y@wjyR1V%kj8k@9r8`b@dh5g;bWGRTquAhdrCjlgYjWT#bwvvI1ekh|lvl~zZihDR9 z2`&~*vo9NgBcPW%vx_@g2#m`BKiLN6@|_2pT-#Zh?1PQTWE?f*)Po@QQdI<|GZyN+I|J`7-jiZUR@4 ze?gW!1R9V-$eWPckrT)ac>s9~c@OeI{T!5%la}*aPy$~{AF~5Mh}Eu;yOozVR*f8!}v4=h9N&}Mi4|KtbovL?Fb=zj__F& zslDEevstOAy*3P`h|3s$?%YT|f|c$z4BUv*-75K;U;uB2C~wyzJdvFM#%lo)W`P9f zA;>${yeWV!?}%h{kwKDy;V1yZFFJF=N3wu78e|571OfwztvN+t^{cvnOLAT@!)Ub0 z^ob(}B^%RJ2dFe&3`n8w*;HAy7xUk$4A?J>LWhV@1sY2s_r8%`sk8R{lG^)_66Fm zO1kTk`Ga&@GK{t9C*}mJv;9;Y|C^S^3u@HYQRo_v(5T*Q?bVW)b78%Z{N{DOZ2UHb;-n78J8Jb}xP@udJ`1d*R8x2sy4Oh-(d~MDYUx2l zXtM$}&!WcPQ~tVp-a$XS(OSPSJikfHzrJAwK?EOEB4+d)6Ldi2oI?yYQm>*`sEu#O|( z`-!)fxwsV>Mk|A&4o$^iu+cK&Sp-elpXuI$)%xcom@JaiO11Lq+yzIf+G p<4@GS9!~aQF|+tTY$xQQ1nt7Ba9QkF0$5m~yF%Q?@3_?^zX4MUZFT?v literal 0 HcmV?d00001 diff --git a/src/mainboard/google/rambi/variants/kip/data.vbt b/src/mainboard/google/rambi/variants/kip/data.vbt new file mode 100644 index 0000000000000000000000000000000000000000..01249f19c07261fed47f2f1c250f959d30c00495 GIT binary patch literal 3603 zcmds3Z)jUp6hH6fC3){A>C%_Z#aQcE9V4w>`;v8~mWnq`TAP}#Y1+kZh|9V}H_g_r z?M8)SqZa8vB(S1WMEXHw43VNB`y~A$6vQ!9_Dv~>W9-X@_(8_p^W2xLoz~4D44uE^ z+&|}@`@83!d+vL0Te@o)(~(4?dv7}4{R|3Z!2n;?B$XS{6(1PdABzk}_ID))qEF*z z@BsYixp@U3D@p#^kP+GyKRT7m2U880PNcDaZ1iwG*AmN3zBDy9j>%{oBL@%W^0|ov zQ@Jb-rJstR;PkMrehzj8A{=5Iy7}6|<%SpJlOQVqTUBuQ%SsON_?Iexvak<8MnGCa@ZS#O zTL*P(_F6i$N(H{jh{pHTU@_1H`$E~kn#{#0;cD4Hv}=C63NtXdSu_Tg;!sDeJ%hurpfM)u2e||JYuhdb8--Vl4ZCmx5Fvh3d|}7e5&~2 zYm&<(m+TC#kz6NH91N;R{3P`xO(bn3oTQIrnB+N!#6jWfLv)gV zxllD}%h27{dEe^#5H?xY>Xu?-UGo7r0vpx;9Zf)N;Gyr}f|HT_BF+2OTl2miOE
s&N%VBQ(twmD^B#P zdcDe;R7|OQR%J(3Tu}9oRJNqzMODA7vY%D-YkH%`S~c9K>3NNv(C~dt|3qWwH2gu+ zuW9VMhRF0VW1S2~nLfqXD-1tm`sa)-GrYv~Um25K7n)-yNoDG{WgYFt{=9E18lH<%#ZTd!QnQ zX&elAx%V~(sc08$6*8P@nO+?XZ094V*L{$R;-w94?pUh8hu$Z-F}f7ye0iP0QF{Bi z)7B@4AiFb6^ZBjmvx87)^c2fyAtG6{9$4f`C2^Q(E-q#Qb=<)6Sx_XEq9zt~7o3&s zBG_429AA2r7#d5iinAzM? z14rKqct+0NyVCp znTBLn+`}-&G?6I!VERZF9~R<+8Xp#ehQvQ1JQ(8>8vhVtltki#L9XY!x2);}Z%l~d zY0vlfoZtELo$ubeIhPotxp*eiyE~WeeVlSCfCd{Hc3``f66vAQeX00Zd|x6nlzfc7 z1NXppz8hBn3W5*_b!ibTePp&+3XinXTqZ{crzQ@Sik+$A%u};d(=?k*)A)e{#Zs}n zf3{elqq#@plw z1pN$r5~LYq7z{FSN)Ts|V$jQ04c7*KaGV5?05;0?Ed~zy0nVk=9>5_`v|)oJxR~c+ zUp9h?fLhMfZd1`hVDRB2pZ-)6aG;5ETmVhr7(hf7DFj+18td-a&JwA<{(($(WGpwn z=L!9}6VERM;rblP{n4KWL4yaJE%3G@4Bt2$@S~#}UKY>8yrjWdDFB}!Uq=4cN#H8- zFUXRMKm&3Bc@uIwatxUv4H8cNKJ@);F5H0L^BvgT#A^ zwdw|aMPGplQ{2z@UqUr#bV1-nbIn#`7;ZP*Fg^`{VaPkU2Yy7t3<%AZMF`aTklBkO zt<5)M&odRS%?(4z<1~W5JJ*trV70mp0}YvUw~o9`Fo3s1l(*|4Gmu>X#;ZON=79JY zz;9M8zbSwvZ;ND9kwKDyVJiT`KPsDqTe5&R8e|571Ofwz)wl2@|I$z+uGUEPn&*9U z+C*WUd97|PtnHiM09SDB@_%O~$OE|VbGYCp$k&9$rut~Hsn1+HzP`TpZ;k9{%rF{j z#C1Y3_)O6&^wRx)Ilsw5X|b~s4uAt@)|g#FYCQ$wn{Im1t$yt$Ke%bLtZtEsCexg( zPRgV#)6=rLB$Kyf`h~21FO#2T8dB5_g>)-)ucA&X-VQ6h|dKfgOO*dJh=tE7>JLe4ALYSk&K|k~V z4ne3mIhsv`Go5pnhJ#z!`02V2Ld9hwFxRpTANn6*+Qf2%v6VW4%X$NPbLMA<72K^_ z!#KDxw=@hbT3@Ah7Ce&`^Pz>V*vZ53j!HEjY+)L$odsr6swid@y4y|^;q7{Ldig;_ zXtNyUXHhZVQ{Jj`!A3p2-depdys$~jzP4c%K?INK19RCy(AwDf{6aws4A;_*K8RS3 zNdL4ZO$48X;G{O9xDteFmTu6zT9Ru4aD++&A9;0mw~cym^yq=3-CNoC*7{k9u+Bul z_mf##d~z!?j8+DD9h&lff1@R2M&ajUZ>BH1FT4Lpv9xpl;o|>b^3YLm4V(wx_|lzg pjXzQQdN|pK$xP#S*e=LI0osLE;Ii1U46wLLcg1jC%_Z#aQcE9V4w>`;v8~mWnq`TAP}#Y1+kZh|9V}H_g_r z?M8)SqZa8vB(S1WMEXHw43VNB`y~A$6vQ!9_Dv~>W9-X@_(8_p^W2xLoz~4D44uE^ z+&|}@`@83!d+vL0Te@o)(~(4?dv7}4{R|3Z!2n;?B$XS{6(1PdABzk}_ID))qEF*z z@BsYixp@U3D@p#^kP+GyKRT7m2U880PNcDaZ1iwG*AmN3zBDy9j>%{oBL@%W^0|ov zQ@Jb-rJstR;PkMrehzj8A{=5Iy7}6|<%SpJlOQVqTUBuQ%SsON_?Iexvak<8MnGCa@ZS#O zTL*P(_F6i$N(H{jh{pHTU@_1H`$E~kn#{#0;cD4Hv}=C63NtXdSu_Tg;!sDeJ%hurpfM)u2e||JYuhdb8--Vl4ZCmx5Fvh3d|}7e5&~2 zYm&<(m+TC#kz6NH91N;R{3P`xO(bn3oTQIrnB+N!#6jWfLv)gV zxllD}%h27{dEe^#5H?xY>Xu?-UGo7r0vpx;9Zf)N;Gyr}f|HT_BF+2OTl2miOE
s&N%VBQ(twmD^B#P zdcDe;R7|OQR%J(3Tu}9oRJNqzMODA7vY%D-YkH%`S~c9K>3NNv(C~dt|3qWwH2gu+ zuW9VMhRF0VW1S2~nLfqXD-1tm`sa)-GrYv~Um25K7n)-yNoDG{WgYFt{=9E18lH<%#ZTd!QnQ zX&elAx%V~(sc08$6*8P@nO+?XZ094V*L{$R;-w94?pUh8hu$Z-F}f7ye0iP0QF{Bi z)7B@4AiFb6^ZBjmvx87)^c2fyAtG6{9$4f`C2^Q(E-q#Qb=<)6Sx_XEq9zt~7o3&s zBG_429AA2r7#d5iinAzM? z14rKqct+0NyVCpC%_Z#aQcE9V4w>`;v8~mWnq`TAP}#Y1+kZh|9V}H_g_r z?M8)SqZa8vB(S1WMEXHw43VNB`y~A$6vQ!9_Dv~>W9-X@_(8_p^W2xLoz~4D44uE^ z+&|}@`@83!d+vL0Te@o)(~(4?dv7}4{R|3Z!2n;?B$XS{6(1PdABzk}_ID))qEF*z z@BsYixp@U3D@p#^kP+GyKRT7m2U880PNcDaZ1iwG*AmN3zBDy9j>%{oBL@%W^0|ov zQ@Jb-rJstR;PkMrehzj8A{=5Iy7}6|<%SpJlOQVqTUBuQ%SsON_?Iexvak<8MnGCa@ZS#O zTL*P(_F6i$N(H{jh{pHTU@_1H`$E~kn#{#0;cD4Hv}=C63NtXdSu_Tg;!sDeJ%hurpfM)u2e||JYuhdb8--Vl4ZCmx5Fvh3d|}7e5&~2 zYm&<(m+TC#kz6NH91N;R{3P`xO(bn3oTQIrnB+N!#6jWfLv)gV zxllD}%h27{dEe^#5H?xY>Xu?-UGo7r0vpx;9Zf)N;Gyr}f|HT_BF+2OTl2miOE
s&N%VBQ(twmD^B#P zdcDe;R7|OQR%J(3Tu}9oRJNqzMODA7vY%D-YkH%`S~c9K>3NNv(C~dt|3qWwH2gu+ zuW9VMhRF0VW1S2~nLfqXD-1tm`sa)-GrYv~Um25K7n)-yNoDG{WgYFt{=9E18lH<%#ZTd!QnQ zX&elAx%V~(sc08$6*8P@nO+?XZ094V*L{$R;-w94?pUh8hu$Z-F}f7ye0iP0QF{Bi z)7B@4AiFb6^ZBjmvx87)^c2fyAtG6{9$4f`C2^Q(E-q#Qb=<)6Sx_XEq9zt~7o3&s zBG_429AA2r7#d5iinAzM? z14rKqct+0NyVCpC%_Z#aQcE9V4w>`;v8~mWnq`TAP}#Y1+kZh|9V}H_g_r z?M8)SqZa8vB(S1WMEXHw43VNB`y~A$6vQ!9_Dv~>W9-X@_(8_p^W2xLoz~4D44uE^ z+&|}@`@83!d+vL0Te@o)(~(4?dv7}4{R|3Z!2n;?B$XS{6(1PdABzk}_ID))qEF*z z@BsYixp@U3D@p#^kP+GyKRT7m2U880PNcDaZ1iwG*AmN3zBDy9j>%{oBL@%W^0|ov zQ@Jb-rJstR;PkMrehzj8A{=5Iy7}6|<%SpJlOQVqTUBuQ%SsON_?Iexvak<8MnGCa@ZS#O zTL*P(_F6i$N(H{jh{pHTU@_1H`$E~kn#{#0;cD4Hv}=C63NtXdSu_Tg;!sDeJ%hurpfM)u2e||JYuhdb8--Vl4ZCmx5Fvh3d|}7e5&~2 zYm&<(m+TC#kz6NH91N;R{3P`xO(bn3oTQIrnB+N!#6jWfLv)gV zxllD}%h27{dEe^#5H?xY>Xu?-UGo7r0vpx;9Zf)N;Gyr}f|HT_BF+2OTl2miOE
s&N%VBQ(twmD^B#P zdcDe;R7|OQR%J(3Tu}9oRJNqzMODA7vY%D-YkH%`S~c9K>3NNv(C~dt|3qWwH2gu+ zuW9VMhRF0VW1S2~nLfqXD-1tm`sa)-GrYv~Um25K7n)-yNoDG{WgYFt{=9E18lH<%#ZTd!QnQ zX&elAx%V~(sc08$6*8P@nO+?XZ094V*L{$R;-w94?pUh8hu$Z-F}f7ye0iP0QF{Bi z)7B@4AiFb6^ZBjmvx87)^c2fyAtG6{9$4f`C2^Q(E-q#Qb=<)6Sx_XEq9zt~7o3&s zBG_429AA2r7#d5iinAzM? z14rKqct+0NyVCpZ;170dVJ&rJwonX>w$W@lONXW=4;2et$->Mtvs2SFlSt9n{{4kw zp|o$dkf&qW$79sQ^pNkXjgtsp;oRhn_w- zOGAk^8rC#zD`Iw2?lMhGm8LsstXQO@rp^oH)y8&zzDDKe! zNpLA=s(slE49(7?l|8wO8&(k*9|QbkDVWo9mV(Wkh-e}OK?_HsJ-ypmJlQ`mn9huj zXD4<)rN40E#f1Rem_xlk`qLz6@PNG)-nE6`8=DP&wDrI#@dC_C8l08<@Cou2EJY71zoWEX5I_X!h0Pg zv!__APS98M6`17eUUU5wG=pXb_+RF-h8n|gI^m}AsUHkOe#G>^i%6IOp{2Sb_^m$3 zdr_p;d^7fDrb5=-Fq9ll!}z;%E%^v))omEK5vRL#JtE8j z@h*UuSFCwc0873hlF>v4Nd|_k01W?V%n6rd0dF+O3LLR! zdc>vbF7lF#F1yqZUF2hzr~R6w+b)|Aq&3MfR)-&*7pj%*rsBlklr&yYqq2@d_e79} z^p@>yIz@Ieh?AbtB#syQReR{cg4QYKs~(KR=GH`uu03jv7v?_f{XjW z9E~7o?d(EsA+PyIthA#KB9zT--;15rCx<9iwv+qcu zxMSbp!vA3M@KJCKUI5R;(w%FKKT*eeIN6WsPvLjiPRKwWI)vBYirBdfuvnwJVz`ap I@oFjk2E!t4b^rhX literal 0 HcmV?d00001 diff --git a/src/mainboard/google/rambi/variants/swanky/data.vbt b/src/mainboard/google/rambi/variants/swanky/data.vbt new file mode 100644 index 0000000000000000000000000000000000000000..d299aa487014dc38c7f6d462048d6bf2fc885fc3 GIT binary patch literal 4608 zcmeHJZ)jUp6hH6fC3){A>C%_Z#aQcE9V4y%^OAL?mWnrRTAP}#Y1+kZh|9V}H_g_r z?M8)SqZa8vBw*1gBK;sThDcG6eUg3=3gQ?l`=%7cG4^Fc{2*iQdG1TrPU~h6hEDfO z&i!-lxxahvx#zz3wxv3UF%^l&yZ5AG-A|!F1`P03Oj5ZKow0$TebLBpWM5}|pzBHe z6z+o`Jl8J)WF*O79Wp{YV@Ia4xnQymQ}Gn`kBuJ6Wt*ef$rq-^#xc0B-4jZ8sGL6g9( zKraW60x=G84*eYL3Pd2g-Z=D$R|Kn0Jf^&@RyVvfQ*2&hTy*$ z#y1Y?R_(ELXq5_lofeJnD#2o)3HF7Ofi;B< z?~L~J_Qey);nc|9r}Hnr^6Fdwu1%BO?_H^o40y<1183wQ{3y$CS#ES>V*7qei=qBbFUbGgQh{H1N^UBy0Qw>bUNX>dDai6sXit=@DdY6 zK&mRP2>w!CZPhj#mipVM7Lf{;`lhL+sT-!>oh#Xwu$JAXNefxHTU%})^nn64wIg3` zZDcoq`L@Rf)4;rQ;I%SV+!UacFAFM7Q9)6GQz-$bKTWnkL#jkK8dMIF0ul#>uMg2l z{^>%Mq%A>rTjzbF>qFRNU8@_4jdj)g;0SC~|9dn6v4ID^g>z0u^0PGWTW`(#dMw?{ z=5^ga)ha(?rde4+bt|0L@&#Od(5t3viwrg8Xo7x_VRFNgrwMfnU_0f+vrc{0$u2q3 ztLn8XYfv$%>KT9A)|xV=poMfa#wxw#@JX(|=)1c45$^x4T%>h0nY685euag&(=} z&s}WA<*C1-iEglqyMB9^rcnz#nDgaz21oJj z=T2Fl9D?lDFwJMTrcMt+jnPvmorQ>G!FphkE9Jytrm3))4%Bc1OJ_lmR0^6{)SY*h zvx{IyesO&1VPdE+x+>11V7;Tz~eJzq)B zWeopdDeUBfjna|ucXQHW@Dv&BSjH|c1z<6OTMW0+C1wE#hC+pCQ6$^S$OpMS??2ks z$VVF2&%y?qECzZvS*ayDw}NTbaY*OEm-c!qi$>NiyrS)n_aycu_8-aScI`i${SR~= zISP)x74VFlzH_Dd2Q+Mk6Fn5n7=457h6H4wL3#@=+M1RC=GSmnGT_Z;CZ}jVou$cr`^uGa zb?;2ML`MscCn?7akkrwGl@i^4^w31P+Cw=IYSXTG$JRKdT6d=w?~G|(ajM08VqHD) zcz|Sj(?f&#Y%V#L9okNZMrbBGnj9VN9ZcnR()`F!e>RmJ>&*nnN*L+MspqN(pFS`{ zqv=)}(==@hVs=r}WtyI>PIb^^r9wxz&NLkYmvVb=lWCnr+0t1PyF5yZ3uVssbG9Smc}GA+pJ z0hv@~x*)5IGI>{~U&-oanfxNth@y5Vq+6l86?IA>&nvX9sHYY3p+dh=)T;`)uFy?H zO%TEe-A~k6LXH!9il`qDa)!`LM7>6c$4A?J>Z3l=@1uu(s_r8%`RI~Q{m4f?^#$6l zNV@9+e<0nK3}bEhi8;ZlY(Evp|E8qzf*SR86uQPEG^#gSd$lCyT$nE;KflhmbpRI) zqjVpzBy83~ClZ!&C^08mhJJAK`+j>e46O|ohCyT6RFkEOKG=r-S$EhG!YmyQ2U+kY z1fk~UXburhb(nE;Q zW;x2wqGrCQ{B`%dgL-(YwSI1RexsIubNvc}2tLyX=5d0cwXw6s`H~hIw$qM2h**wD z|FkAegn)(MrVgUG6oz`9uGjopnp**Igjxe1`E_r%gL-iF=%FLsTiE!P)w2*`or!?& zC$qHpt#;A9^rGmGD0J0K4wXcu0Gi( Date: Tue, 10 Dec 2019 14:53:00 +0100 Subject: [PATCH 0714/1242] superio/aspeed/ast2400: Add AST2500 support The AST2500 is similar to the AST2400, but it also supports ESPI mode. In ESPI mode the IRQ level must be 0 and UART3/UART4 aren't usable. Change-Id: Iea45740427ad56656040e6342f5316ec9d38122f Signed-off-by: Patrick Rudolph Reviewed-on: https://review.coreboot.org/c/coreboot/+/37641 Tested-by: build bot (Jenkins) Reviewed-by: Frans Hendriks Reviewed-by: Felix Held --- src/superio/aspeed/ast2400/chip.h | 22 ++++++++++++++++++++++ src/superio/aspeed/ast2400/superio.c | 24 +++++++++++++++++++++++- 2 files changed, 45 insertions(+), 1 deletion(-) create mode 100644 src/superio/aspeed/ast2400/chip.h diff --git a/src/superio/aspeed/ast2400/chip.h b/src/superio/aspeed/ast2400/chip.h new file mode 100644 index 0000000000..4f1c5f022d --- /dev/null +++ b/src/superio/aspeed/ast2400/chip.h @@ -0,0 +1,22 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __SUPERIO_ASPEED__AST2400_CHIP_H__ +#define __SUPERIO_ASPEED__AST2400_CHIP_H__ + +struct superio_aspeed_ast2400_config { + /* On AST2500 only 1: ESPI, 0: LPC */ + bool use_espi; +}; + +#endif /* __SUPERIO_ASPEED__AST2400_CHIP_H__ */ diff --git a/src/superio/aspeed/ast2400/superio.c b/src/superio/aspeed/ast2400/superio.c index a41bba787e..37a7c9d30c 100644 --- a/src/superio/aspeed/ast2400/superio.c +++ b/src/superio/aspeed/ast2400/superio.c @@ -22,12 +22,23 @@ #include #include #include "ast2400.h" +#include "chip.h" static void ast2400_init(struct device *dev) { + struct superio_aspeed_ast2400_config *conf = dev->chip_info; + if (!dev->enabled) return; + if (conf && conf->use_espi) { + pnp_enter_conf_mode(dev); + pnp_set_logical_device(dev); + /* In ESPI mode must write 0 to IRQ level on every LDN */ + pnp_write_config(dev, 0x70, 0); + pnp_exit_conf_mode(dev); + } + switch (dev->path.pnp.device) { case AST2400_KBC: pc_keyboard_init(NO_AUX_DEVICE); @@ -94,11 +105,22 @@ static struct pnp_info pnp_dev_info[] = { static void enable_dev(struct device *dev) { + struct superio_aspeed_ast2400_config *conf = dev->chip_info; + + if (conf && conf->use_espi) { + /* UART3 and UART4 are not usable in ESPI mode */ + for (size_t i = 0; i < ARRAY_SIZE(pnp_dev_info); i++) { + if ((pnp_dev_info[i].function == AST2400_SUART3) || + (pnp_dev_info[i].function == AST2400_SUART4)) + pnp_dev_info[i].function = PNP_SKIP_FUNCTION; + } + } + pnp_enable_devices(dev, &ops, ARRAY_SIZE(pnp_dev_info), pnp_dev_info); } struct chip_operations superio_aspeed_ast2400_ops = { - CHIP_NAME("ASpeed AST2400 Super I/O") + CHIP_NAME("ASpeed AST2400/AST2500 Super I/O") .enable_dev = enable_dev, }; From 50a445489225b94339adc15fe8d1b6c3fa57b095 Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Sat, 14 Dec 2019 16:16:31 +0100 Subject: [PATCH 0715/1242] src/mb/Kconfig: add BOARD_ROMSIZE_KB_5120 Mainboards exist with a 4+1 MiB flash chip combination. Change-Id: I214553a2c70e1a4a0e4d972fee5e524b609bb1e0 Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/37729 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel Reviewed-by: Nico Huber --- src/mainboard/Kconfig | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/src/mainboard/Kconfig b/src/mainboard/Kconfig index 97086b7cd6..a3895e9dc9 100644 --- a/src/mainboard/Kconfig +++ b/src/mainboard/Kconfig @@ -28,6 +28,8 @@ config BOARD_ROMSIZE_KB_2048 bool config BOARD_ROMSIZE_KB_4096 bool +config BOARD_ROMSIZE_KB_5120 + bool config BOARD_ROMSIZE_KB_6144 bool config BOARD_ROMSIZE_KB_8192 @@ -53,6 +55,7 @@ choice default COREBOOT_ROMSIZE_KB_1024 if BOARD_ROMSIZE_KB_1024 default COREBOOT_ROMSIZE_KB_2048 if BOARD_ROMSIZE_KB_2048 default COREBOOT_ROMSIZE_KB_4096 if BOARD_ROMSIZE_KB_4096 + default COREBOOT_ROMSIZE_KB_5120 if BOARD_ROMSIZE_KB_5120 default COREBOOT_ROMSIZE_KB_6144 if BOARD_ROMSIZE_KB_6144 default COREBOOT_ROMSIZE_KB_8192 if BOARD_ROMSIZE_KB_8192 default COREBOOT_ROMSIZE_KB_10240 if BOARD_ROMSIZE_KB_10240 @@ -101,6 +104,11 @@ config COREBOOT_ROMSIZE_KB_4096 help Choose this option if you have a 4096 KB (4 MB) ROM chip. +config COREBOOT_ROMSIZE_KB_5120 + bool "5120 KB (5 MB)" + help + Choose this option if you have a 5120 KB (5 MB) ROM chip. + config COREBOOT_ROMSIZE_KB_6144 bool "6144 KB (6 MB)" help @@ -148,6 +156,7 @@ config COREBOOT_ROMSIZE_KB default 1024 if COREBOOT_ROMSIZE_KB_1024 default 2048 if COREBOOT_ROMSIZE_KB_2048 default 4096 if COREBOOT_ROMSIZE_KB_4096 + default 5120 if COREBOOT_ROMSIZE_KB_5120 default 6144 if COREBOOT_ROMSIZE_KB_6144 default 8192 if COREBOOT_ROMSIZE_KB_8192 default 10240 if COREBOOT_ROMSIZE_KB_10240 @@ -166,6 +175,7 @@ config ROM_SIZE default 0x100000 if COREBOOT_ROMSIZE_KB_1024 default 0x200000 if COREBOOT_ROMSIZE_KB_2048 default 0x400000 if COREBOOT_ROMSIZE_KB_4096 + default 0x500000 if COREBOOT_ROMSIZE_KB_5120 default 0x600000 if COREBOOT_ROMSIZE_KB_6144 default 0x800000 if COREBOOT_ROMSIZE_KB_8192 default 0xa00000 if COREBOOT_ROMSIZE_KB_10240 From 9cb88a70f7a636806752542216e177ba625e77d2 Mon Sep 17 00:00:00 2001 From: Frans Hendriks Date: Fri, 6 Dec 2019 11:54:01 +0100 Subject: [PATCH 0716/1242] src: Conditionally include TEVT MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit ACPI method TEVT is reported as unused by iASL (20190509) when ChromeEC support is not enabled. The message is “Method Argument is never used (Arg0)” on Method (TEVT, 1, NotSerialized), which indicates the TEVT method is empty. The solution is to only enable the TEVT code in mainboard or SoC when an EC is used that uses this event. The TEVT code in the EC is only enabled if the mainboard or SoC code implements TEVT. The TEVT method will be removed from the ASL code when the EC does not support TEVT. BUG=N/A TEST=Tested on facebook monolith. Change-Id: I8d2e14407ae2338e58797cdc7eb7d0cadf3cc26e Signed-off-by: Wim Vervoorn Reviewed-on: https://review.coreboot.org/c/coreboot/+/37560 Tested-by: build bot (Jenkins) Reviewed-by: Frans Hendriks --- src/ec/acpi/Kconfig | 6 ++++++ src/ec/google/chromeec/Kconfig | 1 + src/ec/google/wilco/Kconfig | 1 + src/ec/google/wilco/acpi/dptf.asl | 2 ++ src/mainboard/google/cyan/acpi/dptf.asl | 2 -- .../cyan/variants/terra/include/variant/acpi/thermal.asl | 3 +++ src/soc/intel/baytrail/acpi/dptf/thermal.asl | 3 +++ src/soc/intel/braswell/acpi/dptf/thermal.asl | 4 +++- src/soc/intel/common/acpi/dptf/thermal.asl | 3 +++ src/soc/intel/skylake/acpi/dptf/thermal.asl | 3 +++ 10 files changed, 25 insertions(+), 3 deletions(-) diff --git a/src/ec/acpi/Kconfig b/src/ec/acpi/Kconfig index 3081a86609..1fa707abdc 100644 --- a/src/ec/acpi/Kconfig +++ b/src/ec/acpi/Kconfig @@ -2,3 +2,9 @@ config EC_ACPI bool help ACPI Embedded Controller interface. Mostly found in laptops. + +config EC_SUPPORTS_DPTF_TEVT + bool + help + The EC ASL code supports calling of TEVT method when provided by + SoC or mainboard. diff --git a/src/ec/google/chromeec/Kconfig b/src/ec/google/chromeec/Kconfig index 2eb3b95c7d..b33864f09e 100644 --- a/src/ec/google/chromeec/Kconfig +++ b/src/ec/google/chromeec/Kconfig @@ -1,5 +1,6 @@ config EC_GOOGLE_CHROMEEC bool + select EC_SUPPORTS_DPTF_TEVT help Google's Chrome EC diff --git a/src/ec/google/wilco/Kconfig b/src/ec/google/wilco/Kconfig index 25d7cfafc2..ee7b556551 100644 --- a/src/ec/google/wilco/Kconfig +++ b/src/ec/google/wilco/Kconfig @@ -3,6 +3,7 @@ config EC_GOOGLE_WILCO default n select EC_GOOGLE_COMMON_MEC select EC_ACPI + select EC_SUPPORTS_DPTF_TEVT help Google Wilco Embedded Controller interface. diff --git a/src/ec/google/wilco/acpi/dptf.asl b/src/ec/google/wilco/acpi/dptf.asl index 0f1663f714..42fc9fdeed 100644 --- a/src/ec/google/wilco/acpi/dptf.asl +++ b/src/ec/google/wilco/acpi/dptf.asl @@ -115,8 +115,10 @@ Method (PATX, 0, Serialized) /* Handle bits that are set */ While (FindSetRightBit (Local1, Local2)) { +#ifdef HAVE_THERM_EVENT_HANDLER /* DPTF will Notify sensor devices */ \_SB.DPTF.TEVT (Local2) +#endif /* Clear current sensor number */ Local1 &= ~(1 << (Local2 - 1)) diff --git a/src/mainboard/google/cyan/acpi/dptf.asl b/src/mainboard/google/cyan/acpi/dptf.asl index 70ab86217b..81e9fee397 100644 --- a/src/mainboard/google/cyan/acpi/dptf.asl +++ b/src/mainboard/google/cyan/acpi/dptf.asl @@ -15,8 +15,6 @@ * GNU General Public License for more details. */ -#define HAVE_THERM_EVENT_HANDLER - /* Include Variant DPTF */ #include diff --git a/src/mainboard/google/cyan/variants/terra/include/variant/acpi/thermal.asl b/src/mainboard/google/cyan/variants/terra/include/variant/acpi/thermal.asl index 1ff308dd75..77482a4bd4 100644 --- a/src/mainboard/google/cyan/variants/terra/include/variant/acpi/thermal.asl +++ b/src/mainboard/google/cyan/variants/terra/include/variant/acpi/thermal.asl @@ -16,6 +16,8 @@ /* Thermal Threshold Event Handler */ #define HAVE_THERM_EVENT_HANDLER + +#if CONFIG(EC_SUPPORTS_DPTF_TEVT) Method (TEVT, 1, NotSerialized) { Store (ToInteger (Arg0), Local0) @@ -36,6 +38,7 @@ Method (TEVT, 1, NotSerialized) } #endif } +#endif /* Thermal device initialization - Disable Aux Trip Points */ Method (TINI) diff --git a/src/soc/intel/baytrail/acpi/dptf/thermal.asl b/src/soc/intel/baytrail/acpi/dptf/thermal.asl index d84ae4b040..106cd77015 100644 --- a/src/soc/intel/baytrail/acpi/dptf/thermal.asl +++ b/src/soc/intel/baytrail/acpi/dptf/thermal.asl @@ -14,6 +14,8 @@ /* Thermal Threshold Event Handler */ #define HAVE_THERM_EVENT_HANDLER + +#if CONFIG(EC_SUPPORTS_DPTF_TEVT) Method (TEVT, 1, NotSerialized) { Store (ToInteger (Arg0), Local0) @@ -34,6 +36,7 @@ Method (TEVT, 1, NotSerialized) } #endif } +#endif /* Thermal device initialization - Disable Aux Trip Points */ Method (TINI) diff --git a/src/soc/intel/braswell/acpi/dptf/thermal.asl b/src/soc/intel/braswell/acpi/dptf/thermal.asl index 1fdbea01ca..7daa36c8d4 100644 --- a/src/soc/intel/braswell/acpi/dptf/thermal.asl +++ b/src/soc/intel/braswell/acpi/dptf/thermal.asl @@ -15,7 +15,9 @@ */ /* Thermal Threshold Event Handler */ -#ifdef HAVE_THERM_EVENT_HANDLER +#define HAVE_THERM_EVENT_HANDLER + +#if CONFIG(EC_SUPPORTS_DPTF_TEVT) Method (TEVT, 1, NotSerialized) { Store (ToInteger (Arg0), Local0) diff --git a/src/soc/intel/common/acpi/dptf/thermal.asl b/src/soc/intel/common/acpi/dptf/thermal.asl index d41f62354b..7058b27f38 100644 --- a/src/soc/intel/common/acpi/dptf/thermal.asl +++ b/src/soc/intel/common/acpi/dptf/thermal.asl @@ -16,6 +16,8 @@ /* Thermal Threshold Event Handler */ #define HAVE_THERM_EVENT_HANDLER + +#if CONFIG(EC_SUPPORTS_DPTF_TEVT) Method (TEVT, 1, NotSerialized) { Store (ToInteger (Arg0), Local0) @@ -41,6 +43,7 @@ Method (TEVT, 1, NotSerialized) } #endif } +#endif /* Thermal device initialization - Disable Aux Trip Points */ Method (TINI) diff --git a/src/soc/intel/skylake/acpi/dptf/thermal.asl b/src/soc/intel/skylake/acpi/dptf/thermal.asl index 5f3548e014..742b092311 100644 --- a/src/soc/intel/skylake/acpi/dptf/thermal.asl +++ b/src/soc/intel/skylake/acpi/dptf/thermal.asl @@ -16,6 +16,8 @@ /* Thermal Threshold Event Handler */ #define HAVE_THERM_EVENT_HANDLER + +#if CONFIG(EC_SUPPORTS_DPTF_TEVT) Method (TEVT, 1, NotSerialized) { @@ -40,6 +42,7 @@ Method (TEVT, 1, NotSerialized) } #endif } +#endif /* Thermal device initialization - Disable Aux Trip Points */ Method (TINI) From d908916642eadf613e02d083cc54c9dacea28152 Mon Sep 17 00:00:00 2001 From: Wim Vervoorn Date: Fri, 13 Dec 2019 12:06:44 +0100 Subject: [PATCH 0717/1242] soc/intel{cannonlake,icelake}/northbridge.asl: Correct flash range The base address of the 16 MB flash range was reported as 0xFFF00000 this causes the range to extend above the 4GB boundary. Change the base to 0xFF000000 as is the case with e.g. Skylake. BUG=N/A TEST=build Change-Id: Ia8de01769ced00c5ae13f255760401933230b88c Signed-off-by: Wim Vervoorn Reviewed-on: https://review.coreboot.org/c/coreboot/+/37694 Tested-by: build bot (Jenkins) Reviewed-by: Frans Hendriks --- src/soc/intel/cannonlake/acpi/northbridge.asl | 2 +- src/soc/intel/icelake/acpi/northbridge.asl | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/src/soc/intel/cannonlake/acpi/northbridge.asl b/src/soc/intel/cannonlake/acpi/northbridge.asl index 22ddad7fbb..25291163cf 100644 --- a/src/soc/intel/cannonlake/acpi/northbridge.asl +++ b/src/soc/intel/cannonlake/acpi/northbridge.asl @@ -307,7 +307,7 @@ Device (PDRC) Memory32Fixed (ReadOnly, VTD_BASE_ADDRESS, VTD_BASE_SIZE) /* FLASH range */ - Memory32Fixed (ReadOnly, 0xFFF00000, 0x1000000, FIOH) + Memory32Fixed (ReadOnly, 0xFF000000, 0x1000000, FIOH) /* Local APIC range(0xFEE0_0000 to 0xFEEF_FFFF) */ Memory32Fixed (ReadOnly, 0xFEE00000, 0x100000, LIOH) diff --git a/src/soc/intel/icelake/acpi/northbridge.asl b/src/soc/intel/icelake/acpi/northbridge.asl index e99e7edf1f..68c7f9e9fd 100644 --- a/src/soc/intel/icelake/acpi/northbridge.asl +++ b/src/soc/intel/icelake/acpi/northbridge.asl @@ -308,7 +308,7 @@ Device (PDRC) Memory32Fixed (ReadOnly, VTD_BASE_ADDRESS, VTD_BASE_SIZE) /* FLASH range */ - Memory32Fixed (ReadOnly, 0xFFF00000, 0x1000000, FIOH) + Memory32Fixed (ReadOnly, 0xFF000000, 0x1000000, FIOH) /* Local APIC range(0xFEE0_0000 to 0xFEEF_FFFF) */ Memory32Fixed (ReadOnly, 0xFEE00000, 0x100000, LIOH) From 31e2188c385ce1d9326d18044c5e6a567a68b048 Mon Sep 17 00:00:00 2001 From: Jeremy Compostella Date: Mon, 9 Dec 2019 17:02:45 -0700 Subject: [PATCH 0718/1242] ifwitool: Introduce a use the Second Logical Boot Partition option The ApolloLake SoC allows two Logical Boot Partitions. This patch introduces a '-s' optional parameter to select the second Logical Boot Partition. Change-Id: If32ec11fc7291d52b821bf95c1e186690d06ba11 Signed-off-by: Jeremy Compostella Reviewed-on: https://review.coreboot.org/c/coreboot/+/37660 Reviewed-by: Furquan Shaikh Reviewed-by: Werner Zeh Tested-by: build bot (Jenkins) --- util/cbfstool/ifwitool.c | 61 +++++++++++++++++++++++++++++----------- 1 file changed, 44 insertions(+), 17 deletions(-) diff --git a/util/cbfstool/ifwitool.c b/util/cbfstool/ifwitool.c index 1fbb61bfac..76b84e26df 100644 --- a/util/cbfstool/ifwitool.c +++ b/util/cbfstool/ifwitool.c @@ -34,9 +34,13 @@ */ #define BPDT_SIGNATURE (0x000055AA) +#define LBP1 (0) +#define LBP2 (1) + /* Parameters passed in by caller. */ static struct param { const char *file_name; + size_t logical_boot_partition; const char *subpart_name; const char *image_name; bool dir_ops; @@ -851,6 +855,18 @@ static void parse_subpart_dir(struct buffer *subpart_dir_buf, print_subpart_dir(subpart_dir); } +/* Parse the bpdt entries to compute the size of the BPDT */ +static size_t bpdt_size(void *data) +{ + struct bpdt *b = (struct bpdt *)data; + size_t i, size = 0; + + for (i = 0; i < b->h.descriptor_count; i++) + size = MAX(size, b->e[i].offset + b->e[i].size); + + return size; +} + /* Parse input image file to identify different sub-partitions. */ static int ifwi_parse(void) { @@ -867,17 +883,22 @@ static int ifwi_parse(void) INFO("Buffer %p size 0x%zx\n", buff->data, buff->size); /* Look for BPDT signature at 4K intervals. */ - size_t offset = 0; + size_t offset = 0, lbp = LBP1; void *data = buffer_get(buff); while (offset < buffer_size(buff)) { - if (read_at_le32(data, offset) == BPDT_SIGNATURE) - break; - offset += 4 * KiB; + if (read_at_le32(data, offset) == BPDT_SIGNATURE) { + if (lbp == param.logical_boot_partition) + break; + offset += bpdt_size((uint8_t *)data + offset); + lbp++; + } else + offset += 4 * KiB; } if (offset >= buffer_size(buff)) { - ERROR("Image does not contain BPDT!!\n"); + ERROR("Image does not contain BPDT for LBP=%zd!!\n", + param.logical_boot_partition); return -1; } @@ -1850,12 +1871,12 @@ struct command { }; static const struct command commands[] = { - {"add", "f:n:e:dvh?", ifwi_add}, - {"create", "f:vh?", ifwi_create}, - {"delete", "f:n:vh?", ifwi_delete}, - {"extract", "f:n:e:dvh?", ifwi_extract}, - {"print", "dh?", ifwi_print}, - {"replace", "f:n:e:dvh?", ifwi_replace}, + {"add", "f:n:e:dsvh?", ifwi_add}, + {"create", "f:svh?", ifwi_create}, + {"delete", "f:n:svh?", ifwi_delete}, + {"extract", "f:n:e:dsvh?", ifwi_extract}, + {"print", "dsh?", ifwi_print}, + {"replace", "f:n:e:dsvh?", ifwi_replace}, }; static struct option long_options[] = { @@ -1865,6 +1886,7 @@ static struct option long_options[] = { {"name", required_argument, 0, 'n'}, {"dir_ops", no_argument, 0, 'd'}, {"verbose", no_argument, 0, 'v'}, + {"second_lbp", no_argument, 0, 's'}, {NULL, 0, 0, 0 } }; @@ -1875,14 +1897,15 @@ static void usage(const char *name) " %s [-h]\n" " %s FILE COMMAND [PARAMETERS]\n\n" "COMMANDs:\n" - " add -f FILE -n NAME [-d -e ENTRY]\n" - " create -f FILE\n" - " delete -n NAME\n" - " extract -f FILE -n NAME [-d -e ENTRY]\n" - " print [-d]\n" - " replace -f FILE -n NAME [-d -e ENTRY]\n" + " add -f FILE -n NAME [-d -e ENTRY] [-s]\n" + " create -f FILE [-s]\n" + " delete -n NAME [-s]\n" + " extract -f FILE -n NAME [-d -e ENTRY] [-s]\n" + " print [-d] [-s]\n" + " replace -f FILE -n NAME [-d -e ENTRY] [-s]\n" "OPTIONs:\n" " -f FILE : File to read/write/create/extract\n" + " -s : Use the second Logical Boot Partition\n" " -d : Perform directory operation\n" " -e ENTRY: Name of directory entry to operate on\n" " -v : Verbose level\n" @@ -1906,6 +1929,7 @@ int main(int argc, char **argv) } param.image_name = argv[1]; + param.logical_boot_partition = LBP1; char *cmd = argv[2]; optind += 2; @@ -1937,6 +1961,9 @@ int main(int argc, char **argv) case 'n': param.subpart_name = optarg; break; + case 's': + param.logical_boot_partition = LBP2; + break; case 'f': param.file_name = optarg; break; From 0f9858f5a1690bce8b7111c60a0d01206e67af34 Mon Sep 17 00:00:00 2001 From: Jeremy Compostella Date: Thu, 12 Dec 2019 14:39:11 -0700 Subject: [PATCH 0719/1242] soc/intel/apollolake: add support for extracting LBP2 from IFWI Add support for automatic extraction of the Second Logical Boot Partition from the supplied IFWI binary. Change-Id: Ia2a9ca233bddb8e9fb4e980f0ae5e6fcf3fc757c Signed-off-by: Jeremy Compostella Reviewed-on: https://review.coreboot.org/c/coreboot/+/37681 Reviewed-by: Furquan Shaikh Tested-by: build bot (Jenkins) --- src/soc/intel/apollolake/Kconfig | 10 +++++++++- src/soc/intel/apollolake/Makefile.inc | 12 ++++++++++-- 2 files changed, 19 insertions(+), 3 deletions(-) diff --git a/src/soc/intel/apollolake/Kconfig b/src/soc/intel/apollolake/Kconfig index 0b3b30a4f8..a39765f8f6 100644 --- a/src/soc/intel/apollolake/Kconfig +++ b/src/soc/intel/apollolake/Kconfig @@ -211,9 +211,17 @@ config LBP2_FMAP_NAME help Name of FMAP region to write logical boot partition 2 data. +config LBP2_FROM_IFWI + bool "Extract the LBP2 from the IFWI binary" + depends on NEED_LBP2 + default n + help + The Logical Boot Partition will be automatically extracted + from the supplied IFWI binary + config LBP2_FILE_NAME string "Path of file to write to logical boot partition 2 region" - depends on NEED_LBP2 + depends on NEED_LBP2 && !LBP2_FROM_IFWI default "3rdparty/blobs/mainboard/$(CONFIG_MAINBOARD_DIR)/lbp2.bin" help Name of file to store in the logical boot partition 2 region. diff --git a/src/soc/intel/apollolake/Makefile.inc b/src/soc/intel/apollolake/Makefile.inc index 24375b3599..d63316969b 100644 --- a/src/soc/intel/apollolake/Makefile.inc +++ b/src/soc/intel/apollolake/Makefile.inc @@ -117,8 +117,16 @@ pdpt-type := raw endif ifeq ($(CONFIG_NEED_LBP2),y) -files_added:: - $(CBFSTOOL) $(obj)/coreboot.rom write -r $(CONFIG_LBP2_FMAP_NAME) -f $(CONFIG_LBP2_FILE_NAME) --fill-upward +$(objcbfs)/lbp2.bin: $(IFWITOOL) +ifeq ($(CONFIG_LBP2_FROM_IFWI),y) + $(IFWITOOL) $(CONFIG_IFWI_FILE_NAME) create -f $@ -s + $(IFWITOOL) $@ delete -n OBBP +else + cp $(CONFIG_LBP2_FILE_NAME) $@ +endif + +files_added:: $(objcbfs)/lbp2.bin + $(CBFSTOOL) $(obj)/coreboot.rom write -r $(CONFIG_LBP2_FMAP_NAME) -f $< --fill-upward endif # Bootblock on Apollolake platform lies in the IFWI region. In order to place From b5ba8b6d1a57f8b57b3a6aec80ed6a47618d433d Mon Sep 17 00:00:00 2001 From: Aamir Bohra Date: Thu, 5 Dec 2019 17:49:39 +0530 Subject: [PATCH 0720/1242] mb/intel/icelake_rvp: Remove baseboard gpio configuration support Remove baseboard gpio.c and rely on variant override. Change-Id: I4657b1aa2c81a990b750e163e948b8495d8b97c7 Signed-off-by: Aamir Bohra Reviewed-on: https://review.coreboot.org/c/coreboot/+/37512 Reviewed-by: Karthik Ramasubramanian Reviewed-by: Rizwan Qureshi Reviewed-by: Maulik V Vaghela Tested-by: build bot (Jenkins) --- .../variants/baseboard/Makefile.inc | 3 - .../icelake_rvp/variants/baseboard/gpio.c | 126 ------------------ .../intel/icelake_rvp/variants/icl_u/gpio.c | 10 ++ .../intel/icelake_rvp/variants/icl_y/gpio.c | 10 ++ 4 files changed, 20 insertions(+), 129 deletions(-) delete mode 100644 src/mainboard/intel/icelake_rvp/variants/baseboard/Makefile.inc delete mode 100644 src/mainboard/intel/icelake_rvp/variants/baseboard/gpio.c diff --git a/src/mainboard/intel/icelake_rvp/variants/baseboard/Makefile.inc b/src/mainboard/intel/icelake_rvp/variants/baseboard/Makefile.inc deleted file mode 100644 index 9fb63f5f43..0000000000 --- a/src/mainboard/intel/icelake_rvp/variants/baseboard/Makefile.inc +++ /dev/null @@ -1,3 +0,0 @@ -bootblock-y += gpio.c - -ramstage-y += gpio.c diff --git a/src/mainboard/intel/icelake_rvp/variants/baseboard/gpio.c b/src/mainboard/intel/icelake_rvp/variants/baseboard/gpio.c deleted file mode 100644 index 20029cfb36..0000000000 --- a/src/mainboard/intel/icelake_rvp/variants/baseboard/gpio.c +++ /dev/null @@ -1,126 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2018 Intel Corporation. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include - -/* Pad configuration in ramstage*/ -static const struct pad_config gpio_table[] = { -/* I2S2_SCLK */ -PAD_CFG_GPI(GPP_A7, NONE, PLTRST), -/* I2S2_RXD */ -PAD_CFG_GPI(GPP_A10, NONE, PLTRST), -/* TCH_PNL2_RST_N */ -PAD_CFG_GPO(GPP_A13, 1, DEEP), -/* ONBOARD_X4_PCIE_SLOT1_PWREN_N */ -PAD_CFG_GPO(GPP_A14, 0, DEEP), -/* TCH_PNL2_INT_N */ -PAD_CFG_GPI_APIC_EDGE_LOW(GPP_B3, NONE, PLTRST), -/* TC_RETIMER_FORCE_PWR */ -PAD_CFG_GPO(GPP_B4, 0, DEEP), -/* FPS_RST_N */ -PAD_CFG_GPO(GPP_B14, 1, DEEP), -/* WIFI_RF_KILL_N */ -PAD_CFG_GPO(GPP_B15, 1, PLTRST), -/* M2_SSD_PWREN_N */ -PAD_CFG_GPO(GPP_B16, 1, DEEP), -/* WWAN_PERST_N */ -PAD_CFG_GPO(GPP_B17, 1, DEEP), -/* BT_RF_KILL_N */ -PAD_CFG_GPO(GPP_B18, 1, PLTRST), -/* CRD_CAM_PWREN_1 */ -PAD_CFG_GPO(GPP_B23, 1, PLTRST), -/* WF_CAM_CLK_EN */ -PAD_CFG_GPO(GPP_C2, 1, PLTRST), -/* ONBOARD_X4_PCIE_SLOT1_RESET_N */ -PAD_CFG_GPO(GPP_C5, 1, DEEP), -/* TCH_PAD_INT_N */ -PAD_CFG_GPI_APIC_EDGE_LOW(GPP_C8, NONE, PLTRST), -/* WWAN_RST_N */ -PAD_CFG_GPO(GPP_C10, 1, DEEP), -/* WWAN_FCP_OFF_N */ -PAD_CFG_GPO(GPP_C11, 1, DEEP), -/* CODEC_INT_N */ -PAD_CFG_GPI_APIC_LOW(GPP_C12, NONE, PLTRST), -/* SPKR_PD_N */ -PAD_CFG_GPO(GPP_C13, 1, PLTRST), -/* WF_CAM_RST_N */ -PAD_CFG_GPO(GPP_C15, 1, PLTRST), -/* CRD_CAM_STROBE_1 */ -PAD_CFG_GPO(GPP_C22, 0, PLTRST), -/* CRD_CAM_PRIVACY_LED_1 */ -PAD_CFG_GPO(GPP_C23, 0, PLTRST), -/* FLASH_DES_SEC_OVERRIDEs */ -PAD_CFG_GPO(GPP_D13, 0, DEEP), -/* TCH_PAD_LS_EN */ -PAD_CFG_GPO(GPP_D14, 1, PLTRST), -/* ONBOARD_X4_PCIE_SLOT1_DGPU_SEL */ -PAD_CFG_GPO(GPP_D15, 0, DEEP), -/* MFR_MODE_DET_STRAP */ -PAD_CFG_GPI(GPP_D16, NONE, PLTRST), -/* TBT_CIO_PWR_EN */ -PAD_CFG_GPO(GPP_E0, 1, DEEP), -/* FPS_INT */ -PAD_CFG_GPI_APIC(GPP_E3, NONE, PLTRST, LEVEL, NONE), -/* EC_SLP_S0_CS_N */ -PAD_CFG_GPO(GPP_E6, 1, DEEP), -/* EC_SMI_N */ -PAD_CFG_GPI_SMI(GPP_E7, NONE, DEEP, LEVEL, NONE), -/* TBT_CIO_PLUG_EVENT_N */ -PAD_CFG_GPI_SCI(GPP_E17, NONE, DEEP, EDGE_SINGLE, NONE), -/* DISP_AUX_P_BIAS_GPIO */ -PAD_CFG_GPO(GPP_E22, 0, PLTRST), -/* DISP_AUX_N_BIAS_GPIO */ -PAD_CFG_GPO(GPP_E23, 1, DEEP), -/* SATA_HDD_PWREN */ -PAD_CFG_GPO(GPP_F4, 1, PLTRST), -/* BIOS_REC */ -PAD_CFG_GPI(GPP_F5, NONE, PLTRST), -/* SD_CD# */ -PAD_CFG_NF(GPP_G5, UP_20K, PWROK, NF1), -/* SD_WP */ -PAD_CFG_NF(GPP_G7, DN_20K, PWROK, NF1), -/* M2_SSD_RST_N */ -PAD_CFG_GPO(GPP_H0, 1, DEEP), -}; - -/* Early pad configuration in bootblock */ -static const struct pad_config early_gpio_table[] = { - -}; - -const struct pad_config *__attribute__((weak)) variant_gpio_table(size_t *num) -{ - *num = ARRAY_SIZE(gpio_table); - return gpio_table; -} - -const struct pad_config *__attribute__((weak)) - variant_early_gpio_table(size_t *num) -{ - *num = ARRAY_SIZE(early_gpio_table); - return early_gpio_table; -} - -static const struct cros_gpio cros_gpios[] = { - CROS_GPIO_REC_AL(CROS_GPIO_VIRTUAL, CROS_GPIO_DEVICE_NAME), -}; - -const struct cros_gpio *__attribute__((weak)) variant_cros_gpios(size_t *num) -{ - *num = ARRAY_SIZE(cros_gpios); - return cros_gpios; -} diff --git a/src/mainboard/intel/icelake_rvp/variants/icl_u/gpio.c b/src/mainboard/intel/icelake_rvp/variants/icl_u/gpio.c index ea96cbcad7..36bfa233ee 100644 --- a/src/mainboard/intel/icelake_rvp/variants/icl_u/gpio.c +++ b/src/mainboard/intel/icelake_rvp/variants/icl_u/gpio.c @@ -114,3 +114,13 @@ const struct pad_config *variant_early_gpio_table(size_t *num) *num = ARRAY_SIZE(early_gpio_table); return early_gpio_table; } + +static const struct cros_gpio cros_gpios[] = { + CROS_GPIO_REC_AL(CROS_GPIO_VIRTUAL, CROS_GPIO_DEVICE_NAME), +}; + +const struct cros_gpio *variant_cros_gpios(size_t *num) +{ + *num = ARRAY_SIZE(cros_gpios); + return cros_gpios; +} diff --git a/src/mainboard/intel/icelake_rvp/variants/icl_y/gpio.c b/src/mainboard/intel/icelake_rvp/variants/icl_y/gpio.c index ea96cbcad7..36bfa233ee 100644 --- a/src/mainboard/intel/icelake_rvp/variants/icl_y/gpio.c +++ b/src/mainboard/intel/icelake_rvp/variants/icl_y/gpio.c @@ -114,3 +114,13 @@ const struct pad_config *variant_early_gpio_table(size_t *num) *num = ARRAY_SIZE(early_gpio_table); return early_gpio_table; } + +static const struct cros_gpio cros_gpios[] = { + CROS_GPIO_REC_AL(CROS_GPIO_VIRTUAL, CROS_GPIO_DEVICE_NAME), +}; + +const struct cros_gpio *variant_cros_gpios(size_t *num) +{ + *num = ARRAY_SIZE(cros_gpios); + return cros_gpios; +} From ee8f969e1eb49d7d8800f877bbbf654114d93535 Mon Sep 17 00:00:00 2001 From: Elyes HAOUAS Date: Sun, 15 Dec 2019 13:30:37 +0100 Subject: [PATCH 0721/1242] mb/msi/ms7721: Switch away from ROMCC_BOOTBLOCK MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Renze Nicolai tested it on hardware: boots into Linux without problems. Change-Id: I17e09c366ae0c9c99d5c65dd1f00672697a7c709 Signed-off-by: Elyes HAOUAS Reviewed-on: https://review.coreboot.org/c/coreboot/+/37737 Reviewed-by: Patrick Georgi Reviewed-by: Kyösti Mälkki Tested-by: build bot (Jenkins) --- src/mainboard/msi/ms7721/Kconfig | 4 - src/mainboard/msi/ms7721/Kconfig.name | 4 +- src/mainboard/msi/ms7721/Makefile.inc | 2 + src/mainboard/msi/ms7721/bootblock.c | 99 ++++++++++++++++++++++++ src/mainboard/msi/ms7721/romstage.c | 107 -------------------------- 5 files changed, 103 insertions(+), 113 deletions(-) create mode 100644 src/mainboard/msi/ms7721/bootblock.c diff --git a/src/mainboard/msi/ms7721/Kconfig b/src/mainboard/msi/ms7721/Kconfig index 5f68e750d5..1fee74790e 100644 --- a/src/mainboard/msi/ms7721/Kconfig +++ b/src/mainboard/msi/ms7721/Kconfig @@ -16,14 +16,10 @@ # GNU General Public License for more details. # -config BOARD_MSI_MS7721 - def_bool n - if BOARD_MSI_MS7721 config BOARD_SPECIFIC_OPTIONS def_bool y - #select ROMCC_BOOTBLOCK select CPU_AMD_AGESA_FAMILY15_TN select NORTHBRIDGE_AMD_AGESA_FAMILY15_TN select SOUTHBRIDGE_AMD_AGESA_HUDSON diff --git a/src/mainboard/msi/ms7721/Kconfig.name b/src/mainboard/msi/ms7721/Kconfig.name index 9ed5473acf..bce5b99d43 100644 --- a/src/mainboard/msi/ms7721/Kconfig.name +++ b/src/mainboard/msi/ms7721/Kconfig.name @@ -1,2 +1,2 @@ -#config BOARD_MSI_MS7721 -# bool"MS-7721 (FM2-A75MA-E35)" +config BOARD_MSI_MS7721 + bool "MS-7721 (FM2-A75MA-E35)" diff --git a/src/mainboard/msi/ms7721/Makefile.inc b/src/mainboard/msi/ms7721/Makefile.inc index f8895faa92..4dde2cfd1e 100644 --- a/src/mainboard/msi/ms7721/Makefile.inc +++ b/src/mainboard/msi/ms7721/Makefile.inc @@ -13,6 +13,8 @@ # GNU General Public License for more details. # +bootblock-y += bootblock.c + romstage-y += buildOpts.c romstage-y += BiosCallOuts.c romstage-y += OemCustomize.c diff --git a/src/mainboard/msi/ms7721/bootblock.c b/src/mainboard/msi/ms7721/bootblock.c new file mode 100644 index 0000000000..9ee7a37d00 --- /dev/null +++ b/src/mainboard/msi/ms7721/bootblock.c @@ -0,0 +1,99 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * Copyright (C) 2012 Rudolf Marek + * Copyright (C) 2016 Renze Nicolai + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include +#include +#include +#include +#include + +#define SB_MMIO_MISC32(x) *(volatile u32 *)(AMD_SB_ACPI_MMIO_ADDR + 0xE00 + (x)) + +/* Ensure Super I/O config address (i.e., 0x2e or 0x4e) matches that of devicetree.cb */ +#define SUPERIO_ADDRESS 0x4e + +#define SERIAL_DEV PNP_DEV(SUPERIO_ADDRESS, F71869AD_SP1) +#define GPIO_DEV PNP_DEV(SUPERIO_ADDRESS, F71869AD_GPIO) + +/* GPIO configuration */ +static void gpio_init(pnp_devfn_t dev) +{ + pnp_enter_conf_state(dev); + pnp_set_logical_device(dev); + pnp_set_enable(dev, 0); + pnp_write_config(dev, 0x60, 0x0a); //Base addr high + pnp_write_config(dev, 0x61, 0x00); //Base addr low + pnp_write_config(dev, 0xe0, 0x04); //GPIO1 output enable + pnp_write_config(dev, 0xe1, 0xff); //GPIO1 output data + pnp_write_config(dev, 0xe3, 0x04); //GPIO1 drive enable + pnp_write_config(dev, 0xe4, 0x00); //GPIO1 PME enable + pnp_write_config(dev, 0xe5, 0x00); //GPIO1 input detect select + pnp_write_config(dev, 0xe6, 0x40); //GPIO1 event status + pnp_write_config(dev, 0xd0, 0x00); //GPIO2 output enable + pnp_write_config(dev, 0xd1, 0xff); //GPIO2 output data + pnp_write_config(dev, 0xd3, 0x00); //GPIO2 drive enable + pnp_write_config(dev, 0xc0, 0x00); //GPIO3 output enable + pnp_write_config(dev, 0xc1, 0xff); //GPIO3 output data + pnp_write_config(dev, 0xb0, 0x04); //GPIO4 output enable + pnp_write_config(dev, 0xb1, 0x04); //GPIO4 output data + pnp_write_config(dev, 0xb3, 0x04); //GPIO4 drive enable + pnp_write_config(dev, 0xb4, 0x00); //GPIO4 PME enable + pnp_write_config(dev, 0xb5, 0x00); //GPIO4 input detect select + pnp_write_config(dev, 0xb6, 0x00); //GPIO4 event status + pnp_write_config(dev, 0xa0, 0x00); //GPIO5 output enable + pnp_write_config(dev, 0xa1, 0x1f); //GPIO5 output data + pnp_write_config(dev, 0xa3, 0x00); //GPIO5 drive enable + pnp_write_config(dev, 0xa4, 0x00); //GPIO5 PME enable + pnp_write_config(dev, 0xa5, 0xff); //GPIO5 input detect select + pnp_write_config(dev, 0xa6, 0xe0); //GPIO5 event status + pnp_write_config(dev, 0x90, 0x00); //GPIO6 output enable + pnp_write_config(dev, 0x91, 0xff); //GPIO6 output data + pnp_write_config(dev, 0x93, 0x00); //GPIO6 drive enable + pnp_write_config(dev, 0x80, 0x00); //GPIO7 output enable + pnp_write_config(dev, 0x81, 0xff); //GPIO7 output data + pnp_write_config(dev, 0x83, 0x00); //GPIO7 drive enable + pnp_set_enable(dev, 1); + pnp_exit_conf_state(dev); +} + +static void sbxxx_enable_48mhzout(void) +{ + /* most likely programming to 48MHz out signal */ + u32 reg32; + reg32 = SB_MMIO_MISC32(0x28); + reg32 &= 0xffc7ffff; + reg32 |= 0x00100000; + SB_MMIO_MISC32(0x28) = reg32; + + reg32 = SB_MMIO_MISC32(0x40); + reg32 &= ~0x80u; + SB_MMIO_MISC32(0x40) = reg32; +} + +void bootblock_mainboard_early_init(void) +{ + /* enable SIO clock */ + sbxxx_enable_48mhzout(); + + /* Initialize GPIO registers */ + gpio_init(GPIO_DEV); + + /* Enable serial console */ + fintek_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); +} diff --git a/src/mainboard/msi/ms7721/romstage.c b/src/mainboard/msi/ms7721/romstage.c index bec2f40bbb..cb87615424 100644 --- a/src/mainboard/msi/ms7721/romstage.c +++ b/src/mainboard/msi/ms7721/romstage.c @@ -15,116 +15,9 @@ * GNU General Public License for more details. */ -#include -#include -#include -#include -#include - #include -#include -#include - -#include -#include - - -#define MMIO_NON_POSTED_START 0xfed00000 -#define MMIO_NON_POSTED_END 0xfedfffff -#define SB_MMIO_MISC32(x) *(volatile u32 *)(AMD_SB_ACPI_MMIO_ADDR + 0xE00 + (x)) - -/* Ensure Super I/O config address (i.e., 0x2e or 0x4e) matches that of devicetree.cb */ -#define SUPERIO_ADDRESS 0x4e - -#define SERIAL_DEV PNP_DEV(SUPERIO_ADDRESS, F71869AD_SP1) -#define GPIO_DEV PNP_DEV(SUPERIO_ADDRESS, F71869AD_GPIO) - - -/* GPIO configuration */ -static void gpio_init(pnp_devfn_t dev) -{ - pnp_enter_conf_state(dev); - pnp_set_logical_device(dev); - pnp_set_enable(dev, 0); - pnp_write_config(dev, 0x60, 0x0a); //Base addr high - pnp_write_config(dev, 0x61, 0x00); //Base addr low - pnp_write_config(dev, 0xe0, 0x04); //GPIO1 output enable - pnp_write_config(dev, 0xe1, 0xff); //GPIO1 output data - pnp_write_config(dev, 0xe3, 0x04); //GPIO1 drive enable - pnp_write_config(dev, 0xe4, 0x00); //GPIO1 PME enable - pnp_write_config(dev, 0xe5, 0x00); //GPIO1 input detect select - pnp_write_config(dev, 0xe6, 0x40); //GPIO1 event status - pnp_write_config(dev, 0xd0, 0x00); //GPIO2 output enable - pnp_write_config(dev, 0xd1, 0xff); //GPIO2 output data - pnp_write_config(dev, 0xd3, 0x00); //GPIO2 drive enable - pnp_write_config(dev, 0xc0, 0x00); //GPIO3 output enable - pnp_write_config(dev, 0xc1, 0xff); //GPIO3 output data - pnp_write_config(dev, 0xb0, 0x04); //GPIO4 output enable - pnp_write_config(dev, 0xb1, 0x04); //GPIO4 output data - pnp_write_config(dev, 0xb3, 0x04); //GPIO4 drive enable - pnp_write_config(dev, 0xb4, 0x00); //GPIO4 PME enable - pnp_write_config(dev, 0xb5, 0x00); //GPIO4 input detect select - pnp_write_config(dev, 0xb6, 0x00); //GPIO4 event status - pnp_write_config(dev, 0xa0, 0x00); //GPIO5 output enable - pnp_write_config(dev, 0xa1, 0x1f); //GPIO5 output data - pnp_write_config(dev, 0xa3, 0x00); //GPIO5 drive enable - pnp_write_config(dev, 0xa4, 0x00); //GPIO5 PME enable - pnp_write_config(dev, 0xa5, 0xff); //GPIO5 input detect select - pnp_write_config(dev, 0xa6, 0xe0); //GPIO5 event status - pnp_write_config(dev, 0x90, 0x00); //GPIO6 output enable - pnp_write_config(dev, 0x91, 0xff); //GPIO6 output data - pnp_write_config(dev, 0x93, 0x00); //GPIO6 drive enable - pnp_write_config(dev, 0x80, 0x00); //GPIO7 output enable - pnp_write_config(dev, 0x81, 0xff); //GPIO7 output data - pnp_write_config(dev, 0x83, 0x00); //GPIO7 drive enable - pnp_set_enable(dev, 1); - pnp_exit_conf_state(dev); -} - - -static void sbxxx_enable_48mhzout(void) -{ - /* most likely programming to 48MHz out signal */ - u32 reg32; - reg32 = SB_MMIO_MISC32(0x28); - reg32 &= 0xffc7ffff; - reg32 |= 0x00100000; - SB_MMIO_MISC32(0x28) = reg32; - - reg32 = SB_MMIO_MISC32(0x40); - reg32 &= ~0x80u; - SB_MMIO_MISC32(0x40) = reg32; -} - void board_BeforeAgesa(struct sysinfo *cb) { - u8 byte; - pci_devfn_t dev; - - /* enable SIO LPC decode */ - dev = PCI_DEV(0, 0x14, 3); - byte = pci_read_config8(dev, 0x48); - byte |= 3; /* 2e, 2f */ - pci_write_config8(dev, 0x48, byte); - - /* enable serial decode */ - byte = pci_read_config8(dev, 0x44); - byte |= (1 << 6); /* 0x3f8 */ - pci_write_config8(dev, 0x44, byte); - post_code(0x30); - - /* enable SB MMIO space */ - outb(0x24, 0xcd6); - outb(0x1, 0xcd7); - - /* enable SIO clock */ - sbxxx_enable_48mhzout(); - - /* Initialize GPIO registers */ - gpio_init(GPIO_DEV); - - /* Enable serial console */ - fintek_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); } From 542919f3707916d00c5a0f4b414e8415b400264a Mon Sep 17 00:00:00 2001 From: Jitao Shi Date: Thu, 26 Sep 2019 10:22:08 +0800 Subject: [PATCH 0722/1242] drivers/analogix: Add anx7625 MIPI DSI/DPI to DP bridge driver The ANX7625 is an ultra-low power 4K Mobile HD Transmitter designed for portable devices. It converts MIPI DSI/DPI to DisplayPort 1.3 4K. BRANCH=none BUG=b:140132295 TEST=emerge-jacuzzi coreboot Change-Id: I02ef29798b0257632e0750f09a4390b3d0226367 Signed-off-by: Jitao Shi Reviewed-on: https://review.coreboot.org/c/coreboot/+/35623 Tested-by: build bot (Jenkins) Reviewed-by: Hung-Te Lin --- src/drivers/analogix/anx7625/Kconfig | 17 + src/drivers/analogix/anx7625/Makefile.inc | 16 + src/drivers/analogix/anx7625/anx7625.c | 892 ++++++++++++++++++++++ src/drivers/analogix/anx7625/anx7625.h | 363 +++++++++ 4 files changed, 1288 insertions(+) create mode 100644 src/drivers/analogix/anx7625/Kconfig create mode 100644 src/drivers/analogix/anx7625/Makefile.inc create mode 100644 src/drivers/analogix/anx7625/anx7625.c create mode 100644 src/drivers/analogix/anx7625/anx7625.h diff --git a/src/drivers/analogix/anx7625/Kconfig b/src/drivers/analogix/anx7625/Kconfig new file mode 100644 index 0000000000..196ae1123b --- /dev/null +++ b/src/drivers/analogix/anx7625/Kconfig @@ -0,0 +1,17 @@ +## +## This file is part of the coreboot project. +## +## Copyright 2019 Analogix Semiconductor. +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +config DRIVER_ANALOGIX_ANX7625 + bool diff --git a/src/drivers/analogix/anx7625/Makefile.inc b/src/drivers/analogix/anx7625/Makefile.inc new file mode 100644 index 0000000000..9a46338cd4 --- /dev/null +++ b/src/drivers/analogix/anx7625/Makefile.inc @@ -0,0 +1,16 @@ +## +## This file is part of the coreboot project. +## +## Copyright 2019 Analogix Semiconductor. +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +ramstage-$(CONFIG_DRIVER_ANALOGIX_ANX7625) += anx7625.c diff --git a/src/drivers/analogix/anx7625/anx7625.c b/src/drivers/analogix/anx7625/anx7625.c new file mode 100644 index 0000000000..293cc1c20e --- /dev/null +++ b/src/drivers/analogix/anx7625/anx7625.c @@ -0,0 +1,892 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2019 Analogix Semiconductor. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include +#include +#include +#include +#include + +#include "anx7625.h" + +#define ANXERROR(format, ...) \ + printk(BIOS_ERR, "ERROR: %s: " format, __func__, ##__VA_ARGS__) +#define ANXINFO(format, ...) \ + printk(BIOS_INFO, "%s: " format, __func__, ##__VA_ARGS__) +#define ANXDEBUG(format, ...) \ + printk(BIOS_DEBUG, "%s: " format, __func__, ##__VA_ARGS__) + +/* + * There is a sync issue while accessing I2C register between AP(CPU) and + * internal firmware(OCM). To avoid the race condition, AP should access the + * reserved slave address before slave address changes. + */ +static int i2c_access_workaround(uint8_t bus, uint8_t saddr) +{ + uint8_t offset; + static uint8_t saddr_backup = 0; + int ret = 0; + + if (saddr == saddr_backup) + return ret; + + saddr_backup = saddr; + + switch (saddr) { + case TCPC_INTERFACE_ADDR: + offset = RSVD_00_ADDR; + break; + case TX_P0_ADDR: + offset = RSVD_D1_ADDR; + break; + case TX_P1_ADDR: + offset = RSVD_60_ADDR; + break; + case RX_P0_ADDR: + offset = RSVD_39_ADDR; + break; + case RX_P1_ADDR: + offset = RSVD_7F_ADDR; + break; + default: + offset = RSVD_00_ADDR; + break; + } + + ret = i2c_writeb(bus, saddr, offset, 0x00); + if (ret < 0) + ANXERROR("Failed to access %#x:%#x\n", saddr, offset); + return ret; +} + +static int anx7625_reg_read(uint8_t bus, uint8_t saddr, uint8_t offset, + uint8_t *val) +{ + int ret; + + i2c_access_workaround(bus, saddr); + ret = i2c_readb(bus, saddr, offset, val); + if (ret < 0) { + ANXERROR("Failed to read i2c reg=%#x:%#x\n", saddr, offset); + return ret; + } + return *val; +} + +static int anx7625_reg_block_read(uint8_t bus, uint8_t saddr, uint8_t reg_addr, + uint8_t len, uint8_t *buf) +{ + int ret; + + i2c_access_workaround(bus, saddr); + ret = i2c_read_bytes(bus, saddr, reg_addr, buf, len); + if (ret < 0) + ANXERROR("Failed to read i2c block=%#x:%#x[len=%#x]\n", saddr, + reg_addr, len); + return ret; +} + +static int anx7625_reg_write(uint8_t bus, uint8_t saddr, uint8_t reg_addr, + uint8_t reg_val) +{ + int ret; + + i2c_access_workaround(bus, saddr); + ret = i2c_writeb(bus, saddr, reg_addr, reg_val); + if (ret < 0) + ANXERROR("Failed to write i2c id=%#x:%#x\n", saddr, reg_addr); + + return ret; +} + +static int anx7625_write_or(uint8_t bus, uint8_t saddr, uint8_t offset, + uint8_t mask) +{ + uint8_t val; + int ret; + + ret = anx7625_reg_read(bus, saddr, offset, &val); + if (ret < 0) + return ret; + + return anx7625_reg_write(bus, saddr, offset, val | mask); +} + +static int anx7625_write_and(uint8_t bus, uint8_t saddr, uint8_t offset, + uint8_t mask) +{ + int ret; + uint8_t val; + + ret = anx7625_reg_read(bus, saddr, offset, &val); + if (ret < 0) + return ret; + + return anx7625_reg_write(bus, saddr, offset, val & mask); +} + +static int wait_aux_op_finish(uint8_t bus) +{ + uint8_t val; + int ret = -1; + int loop; + + for (loop = 0; loop < 150; loop++) { + mdelay(2); + anx7625_reg_read(bus, RX_P0_ADDR, AP_AUX_CTRL_STATUS, &val); + if (!(val & AP_AUX_CTRL_OP_EN)) { + ret = 0; + break; + } + } + + if (ret != 0) { + ANXERROR("Timed out waiting aux operation.\n"); + return ret; + } + + ret = anx7625_reg_read(bus, RX_P0_ADDR, AP_AUX_CTRL_STATUS, &val); + if (ret < 0 || val & 0x0F) { + ANXDEBUG("aux status %02x\n", val); + ret = -1; + } + + return ret; +} + +static unsigned long gcd(unsigned long a, unsigned long b) +{ + if (a == 0) + return b; + + while (b != 0) { + if (a > b) + a = a - b; + else + b = b - a; + } + + return a; +} + +/* Reduce fraction a/b */ +static void anx7625_reduction_of_a_fraction(unsigned long *_a, + unsigned long *_b) +{ + unsigned long gcd_num; + unsigned long a = *_a, b = *_b, old_a, old_b; + u32 denom = 1; + + gcd_num = gcd(a, b); + a /= gcd_num; + b /= gcd_num; + + old_a = a; + old_b = b; + + while (a > MAX_UNSIGNED_24BIT || b > MAX_UNSIGNED_24BIT) { + denom++; + a = old_a / denom; + b = old_b / denom; + } + + /* Increase a, b to have higher ODFC PLL output frequency accuracy. */ + while ((a << 1) < MAX_UNSIGNED_24BIT && (b << 1) < MAX_UNSIGNED_24BIT) { + a <<= 1; + b <<= 1; + } + + *_a = a; + *_b = b; +} + +static int anx7625_calculate_m_n(u32 pixelclock, + unsigned long *m, unsigned long *n, + uint8_t *pd) +{ + uint8_t post_divider = *pd; + if (pixelclock > PLL_OUT_FREQ_ABS_MAX / POST_DIVIDER_MIN) { + /* pixel clock frequency is too high */ + ANXERROR("pixelclock %u higher than %lu, " + "output may be unstable\n", + pixelclock, PLL_OUT_FREQ_ABS_MAX / POST_DIVIDER_MIN); + return 1; + } + + if (pixelclock < PLL_OUT_FREQ_ABS_MIN / POST_DIVIDER_MAX) { + /* pixel clock frequency is too low */ + ANXERROR("pixelclock %u lower than %lu, " + "output may be unstable\n", + pixelclock, PLL_OUT_FREQ_ABS_MIN / POST_DIVIDER_MAX); + return 1; + } + + post_divider = 1; + + for (post_divider = 1; + pixelclock < PLL_OUT_FREQ_MIN / post_divider; + post_divider++) + ; + + if (post_divider > POST_DIVIDER_MAX) { + for (post_divider = 1; + pixelclock < PLL_OUT_FREQ_ABS_MIN / post_divider; + post_divider++) + ; + + if (post_divider > POST_DIVIDER_MAX) { + ANXERROR("cannot find property post_divider(%d)\n", + post_divider); + return 1; + } + } + + /* Patch to improve the accuracy */ + if (post_divider == 7) { + /* 27,000,000 is not divisible by 7 */ + post_divider = 8; + } else if (post_divider == 11) { + /* 27,000,000 is not divisible by 11 */ + post_divider = 12; + } else if (post_divider == 13 || post_divider == 14) { + /*27,000,000 is not divisible by 13 or 14*/ + post_divider = 15; + } + + if (pixelclock * post_divider > PLL_OUT_FREQ_ABS_MAX) { + ANXINFO("act clock(%u) large than maximum(%lu)\n", + pixelclock * post_divider, PLL_OUT_FREQ_ABS_MAX); + return 1; + } + + *m = (unsigned long long)pixelclock * 599 / 600; + *n = XTAL_FRQ / post_divider; + *pd = post_divider; + + anx7625_reduction_of_a_fraction(m, n); + + return 0; +} + +static int anx7625_odfc_config(uint8_t bus, uint8_t post_divider) +{ + int ret; + + /* config input reference clock frequency 27MHz/19.2MHz */ + ret = anx7625_write_and(bus, RX_P1_ADDR, MIPI_DIGITAL_PLL_16, + ~(REF_CLK_27000kHz << MIPI_FREF_D_IND)); + ret |= anx7625_write_or(bus, RX_P1_ADDR, MIPI_DIGITAL_PLL_16, + (REF_CLK_27000kHz << MIPI_FREF_D_IND)); + /* post divider */ + ret |= anx7625_write_and(bus, RX_P1_ADDR, MIPI_DIGITAL_PLL_8, 0x0f); + ret |= anx7625_write_or(bus, RX_P1_ADDR, MIPI_DIGITAL_PLL_8, + post_divider << 4); + + /* add patch for MIS2-125 (5pcs ANX7625 fail ATE MBIST test) */ + ret |= anx7625_write_and(bus, RX_P1_ADDR, MIPI_DIGITAL_PLL_7, + ~MIPI_PLL_VCO_TUNE_REG_VAL); + + /* reset ODFC PLL */ + ret |= anx7625_write_and(bus, RX_P1_ADDR, MIPI_DIGITAL_PLL_7, + ~MIPI_PLL_RESET_N); + ret |= anx7625_write_or(bus, RX_P1_ADDR, MIPI_DIGITAL_PLL_7, + MIPI_PLL_RESET_N); + + if (ret < 0) + ANXERROR("IO error.\n"); + + return ret; +} + +static int anx7625_dsi_video_config(uint8_t bus, struct display_timing *dt) +{ + unsigned long m, n; + u16 htotal; + int ret; + uint8_t post_divider = 0; + + ret = anx7625_calculate_m_n(dt->pixelclock * 1000, &m, &n, + &post_divider); + + if (ret != 0) { + ANXERROR("cannot get property m n value.\n"); + return -1; + } + + ANXINFO("compute M(%lu), N(%lu), divider(%d).\n", m, n, post_divider); + + /* configure pixel clock */ + ret = anx7625_reg_write(bus, RX_P0_ADDR, PIXEL_CLOCK_L, + (dt->pixelclock / 1000) & 0xFF); + ret |= anx7625_reg_write(bus, RX_P0_ADDR, PIXEL_CLOCK_H, + (dt->pixelclock / 1000) >> 8); + /* lane count */ + ret |= anx7625_write_and(bus, RX_P1_ADDR, MIPI_LANE_CTRL_0, 0xfc); + + ret |= anx7625_write_or(bus, RX_P1_ADDR, MIPI_LANE_CTRL_0, 3); + + /* Htotal */ + htotal = dt->hactive + dt->hfront_porch + + dt->hback_porch + dt->hsync_len; + ret |= anx7625_reg_write(bus, RX_P2_ADDR, + HORIZONTAL_TOTAL_PIXELS_L, htotal & 0xFF); + ret |= anx7625_reg_write(bus, RX_P2_ADDR, + HORIZONTAL_TOTAL_PIXELS_H, htotal >> 8); + /* Hactive */ + ret |= anx7625_reg_write(bus, RX_P2_ADDR, + HORIZONTAL_ACTIVE_PIXELS_L, dt->hactive & 0xFF); + ret |= anx7625_reg_write(bus, RX_P2_ADDR, + HORIZONTAL_ACTIVE_PIXELS_H, dt->hactive >> 8); + /* HFP */ + ret |= anx7625_reg_write(bus, RX_P2_ADDR, + HORIZONTAL_FRONT_PORCH_L, dt->hfront_porch); + ret |= anx7625_reg_write(bus, RX_P2_ADDR, + HORIZONTAL_FRONT_PORCH_H, + dt->hfront_porch >> 8); + /* HWS */ + ret |= anx7625_reg_write(bus, RX_P2_ADDR, + HORIZONTAL_SYNC_WIDTH_L, dt->hsync_len); + ret |= anx7625_reg_write(bus, RX_P2_ADDR, + HORIZONTAL_SYNC_WIDTH_H, dt->hsync_len >> 8); + /* HBP */ + ret |= anx7625_reg_write(bus, RX_P2_ADDR, + HORIZONTAL_BACK_PORCH_L, dt->hback_porch); + ret |= anx7625_reg_write(bus, RX_P2_ADDR, + HORIZONTAL_BACK_PORCH_H, dt->hback_porch >> 8); + /* Vactive */ + ret |= anx7625_reg_write(bus, RX_P2_ADDR, ACTIVE_LINES_L, dt->vactive); + ret |= anx7625_reg_write(bus, RX_P2_ADDR, ACTIVE_LINES_H, + dt->vactive >> 8); + /* VFP */ + ret |= anx7625_reg_write(bus, RX_P2_ADDR, + VERTICAL_FRONT_PORCH, dt->vfront_porch); + /* VWS */ + ret |= anx7625_reg_write(bus, RX_P2_ADDR, + VERTICAL_SYNC_WIDTH, dt->vsync_len); + /* VBP */ + ret |= anx7625_reg_write(bus, RX_P2_ADDR, + VERTICAL_BACK_PORCH, dt->vback_porch); + /* M value */ + ret |= anx7625_reg_write(bus, RX_P1_ADDR, + MIPI_PLL_M_NUM_23_16, (m >> 16) & 0xff); + ret |= anx7625_reg_write(bus, RX_P1_ADDR, + MIPI_PLL_M_NUM_15_8, (m >> 8) & 0xff); + ret |= anx7625_reg_write(bus, RX_P1_ADDR, + MIPI_PLL_M_NUM_7_0, (m & 0xff)); + /* N value */ + ret |= anx7625_reg_write(bus, RX_P1_ADDR, + MIPI_PLL_N_NUM_23_16, (n >> 16) & 0xff); + ret |= anx7625_reg_write(bus, RX_P1_ADDR, + MIPI_PLL_N_NUM_15_8, (n >> 8) & 0xff); + ret |= anx7625_reg_write(bus, RX_P1_ADDR, MIPI_PLL_N_NUM_7_0, + (n & 0xff)); + /* diff */ + ret |= anx7625_reg_write(bus, RX_P1_ADDR, MIPI_DIGITAL_ADJ_1, 0x37); + + ret |= anx7625_odfc_config(bus, post_divider - 1); + + if (ret < 0) + ANXERROR("mipi dsi setup IO error.\n"); + + return ret; +} + +static int anx7625_swap_dsi_lane3(uint8_t bus) +{ + int ret; + uint8_t val; + + /* swap MIPI-DSI data lane 3 P and N */ + ret = anx7625_reg_read(bus, RX_P1_ADDR, MIPI_SWAP, &val); + if (ret < 0) { + ANXERROR("IO error: access MIPI_SWAP.\n"); + return -1; + } + + val |= (1 << MIPI_SWAP_CH3); + return anx7625_reg_write(bus, RX_P1_ADDR, MIPI_SWAP, val); +} + +static int anx7625_api_dsi_config(uint8_t bus, struct display_timing *dt) + +{ + int val, ret; + + /* swap MIPI-DSI data lane 3 P and N */ + ret = anx7625_swap_dsi_lane3(bus); + if (ret < 0) { + ANXERROR("IO error: swap dsi lane 3 failed.\n"); + return ret; + } + + /* DSI clock settings */ + val = (0 << MIPI_HS_PWD_CLK) | + (0 << MIPI_HS_RT_CLK) | + (0 << MIPI_PD_CLK) | + (1 << MIPI_CLK_RT_MANUAL_PD_EN) | + (1 << MIPI_CLK_HS_MANUAL_PD_EN) | + (0 << MIPI_CLK_DET_DET_BYPASS) | + (0 << MIPI_CLK_MISS_CTRL) | + (0 << MIPI_PD_LPTX_CH_MANUAL_PD_EN); + ret = anx7625_reg_write(bus, RX_P1_ADDR, MIPI_PHY_CONTROL_3, val); + + /* + * Decreased HS prepare tg delay from 160ns to 80ns work with + * a) Dragon board 810 series (Qualcomm AP) + * b) Moving Pixel DSI source (PG3A pattern generator + + * P332 D-PHY Probe) default D-PHY tg 5ns/step + */ + ret |= anx7625_reg_write(bus, RX_P1_ADDR, MIPI_TIME_HS_PRPR, 0x10); + + /* enable DSI mode */ + ret |= anx7625_write_or(bus, RX_P1_ADDR, MIPI_DIGITAL_PLL_18, + SELECT_DSI << MIPI_DPI_SELECT); + + ret |= anx7625_dsi_video_config(bus, dt); + if (ret < 0) { + ANXERROR("dsi video tg config failed\n"); + return ret; + } + + /* toggle m, n ready */ + ret = anx7625_write_and(bus, RX_P1_ADDR, MIPI_DIGITAL_PLL_6, + ~(MIPI_M_NUM_READY | MIPI_N_NUM_READY)); + mdelay(1); + ret |= anx7625_write_or(bus, RX_P1_ADDR, MIPI_DIGITAL_PLL_6, + MIPI_M_NUM_READY | MIPI_N_NUM_READY); + + /* configure integer stable register */ + ret |= anx7625_reg_write(bus, RX_P1_ADDR, MIPI_VIDEO_STABLE_CNT, 0x02); + /* power on MIPI RX */ + ret |= anx7625_reg_write(bus, RX_P1_ADDR, MIPI_LANE_CTRL_10, 0x00); + ret |= anx7625_reg_write(bus, RX_P1_ADDR, MIPI_LANE_CTRL_10, 0x80); + + if (ret < 0) + ANXERROR("IO error: mipi dsi enable init failed.\n"); + + return ret; +} + +static int anx7625_dsi_config(uint8_t bus, struct display_timing *dt) +{ + int ret; + + ANXINFO("config dsi.\n"); + + /* DSC disable */ + ret = anx7625_write_and(bus, RX_P0_ADDR, R_DSC_CTRL_0, ~DSC_EN); + ret |= anx7625_api_dsi_config(bus, dt); + + if (ret < 0) { + ANXERROR("IO error: api dsi config error.\n"); + return ret; + } + + /* set MIPI RX EN */ + ret = anx7625_write_or(bus, RX_P0_ADDR, AP_AV_STATUS, AP_MIPI_RX_EN); + /* clear mute flag */ + ret |= anx7625_write_and(bus, RX_P0_ADDR, AP_AV_STATUS, ~AP_MIPI_MUTE); + + if (ret < 0) + ANXERROR("IO error: enable mipi rx failed.\n"); + else + ANXINFO("success to config DSI\n"); + + return ret; +} + +static int sp_tx_rst_aux(uint8_t bus) +{ + int ret; + + ret = anx7625_write_or(bus, TX_P2_ADDR, RST_CTRL2, AUX_RST); + ret |= anx7625_write_and(bus, TX_P2_ADDR, RST_CTRL2, ~AUX_RST); + return ret; +} + +static int sp_tx_aux_wr(uint8_t bus, uint8_t offset) +{ + int ret; + + ret = anx7625_reg_write(bus, RX_P0_ADDR, AP_AUX_BUFF_START, offset); + ret |= anx7625_reg_write(bus, RX_P0_ADDR, AP_AUX_COMMAND, 0x04); + ret |= anx7625_write_or(bus, RX_P0_ADDR, + AP_AUX_CTRL_STATUS, AP_AUX_CTRL_OP_EN); + return ret | wait_aux_op_finish(bus); +} + +static int sp_tx_aux_rd(uint8_t bus, uint8_t len_cmd) +{ + int ret; + + ret = anx7625_reg_write(bus, RX_P0_ADDR, AP_AUX_COMMAND, len_cmd); + ret |= anx7625_write_or(bus, RX_P0_ADDR, + AP_AUX_CTRL_STATUS, AP_AUX_CTRL_OP_EN); + return ret | wait_aux_op_finish(bus); +} + +static int sp_tx_get_edid_block(uint8_t bus) +{ + int ret; + uint8_t val = 0; + + sp_tx_aux_wr(bus, 0x7e); + sp_tx_aux_rd(bus, 0x01); + ret = anx7625_reg_read(bus, RX_P0_ADDR, AP_AUX_BUFF_START, &val); + + if (ret < 0) { + ANXERROR("IO error: access AUX BUFF.\n"); + return -1; + } + + ANXINFO("EDID Block = %d\n", val + 1); + + if (val > 3) + val = 1; + + return val; +} + +static int edid_read(uint8_t bus, uint8_t offset, uint8_t *pblock_buf) +{ + uint8_t c, cnt = 0; + + c = 0; + for (cnt = 0; cnt < 3; cnt++) { + sp_tx_aux_wr(bus, offset); + /* set I2C read com 0x01 mot = 0 and read 16 bytes */ + c = sp_tx_aux_rd(bus, 0xf1); + + if (c == 1) { + sp_tx_rst_aux(bus); + ANXERROR("edid read failed, reset!\n"); + cnt++; + } else { + anx7625_reg_block_read(bus, RX_P0_ADDR, + AP_AUX_BUFF_START, + MAX_DPCD_BUFFER_SIZE, pblock_buf); + return 0; + } + } + + return 1; +} + +static int segments_edid_read(uint8_t bus, uint8_t segment, uint8_t *buf, + uint8_t offset) +{ + uint8_t c, cnt = 0; + int ret; + + /* write address only */ + ret = anx7625_reg_write(bus, RX_P0_ADDR, AP_AUX_ADDR_7_0, 0x30); + ret |= anx7625_reg_write(bus, RX_P0_ADDR, AP_AUX_COMMAND, 0x04); + ret |= anx7625_reg_write(bus, RX_P0_ADDR, AP_AUX_CTRL_STATUS, + AP_AUX_CTRL_ADDRONLY | AP_AUX_CTRL_OP_EN); + + ret |= wait_aux_op_finish(bus); + /* write segment address */ + ret |= sp_tx_aux_wr(bus, segment); + /* data read */ + ret |= anx7625_reg_write(bus, RX_P0_ADDR, AP_AUX_ADDR_7_0, 0x50); + + if (ret < 0) { + ANXERROR("IO error: aux initial failed.\n"); + return ret; + } + + for (cnt = 0; cnt < 3; cnt++) { + sp_tx_aux_wr(bus, offset); + /* set I2C read com 0x01 mot = 0 and read 16 bytes */ + c = sp_tx_aux_rd(bus, 0xf1); + + if (c == 1) { + ret = sp_tx_rst_aux(bus); + ANXERROR("segment read failed, reset!\n"); + cnt++; + } else { + ret = anx7625_reg_block_read(bus, RX_P0_ADDR, + AP_AUX_BUFF_START, + MAX_DPCD_BUFFER_SIZE, buf); + return ret; + } + } + + return ret; +} + +static int sp_tx_edid_read(uint8_t bus, uint8_t *pedid_blocks_buf, + uint32_t size) +{ + uint8_t offset, edid_pos; + int count, blocks_num; + uint8_t pblock_buf[MAX_DPCD_BUFFER_SIZE]; + uint8_t i; + uint8_t g_edid_break = 0; + int ret; + + /* address initial */ + ret = anx7625_reg_write(bus, RX_P0_ADDR, AP_AUX_ADDR_7_0, 0x50); + ret |= anx7625_reg_write(bus, RX_P0_ADDR, AP_AUX_ADDR_15_8, 0); + ret |= anx7625_write_and(bus, RX_P0_ADDR, AP_AUX_ADDR_19_16, 0xf0); + + if (ret < 0) { + ANXERROR("access aux channel IO error.\n"); + return -1; + } + + blocks_num = sp_tx_get_edid_block(bus); + if (blocks_num < 0) + return blocks_num; + + count = 0; + + do { + switch (count) { + case 0: + case 1: + for (i = 0; i < 8; i++) { + offset = (i + count * 8) * MAX_DPCD_BUFFER_SIZE; + g_edid_break = edid_read(bus, offset, + pblock_buf); + + if (g_edid_break == 1) + break; + + if (offset <= size - MAX_DPCD_BUFFER_SIZE) + memcpy(&pedid_blocks_buf[offset], + pblock_buf, + MAX_DPCD_BUFFER_SIZE); + } + + break; + case 2: + case 3: + offset = (count == 2) ? 0x00 : 0x80; + + for (i = 0; i < 8; i++) { + edid_pos = (i + count * 8) * + MAX_DPCD_BUFFER_SIZE; + + if (g_edid_break == 1) + break; + + segments_edid_read(bus, count / 2, + pblock_buf, offset); + if (edid_pos <= size - MAX_DPCD_BUFFER_SIZE) + memcpy(&pedid_blocks_buf[edid_pos], + pblock_buf, + MAX_DPCD_BUFFER_SIZE); + offset = offset + 0x10; + } + + break; + default: + die("%s: count should be <= 3", __func__); + break; + } + + count++; + + } while (blocks_num >= count); + + /* reset aux channel */ + sp_tx_rst_aux(bus); + + return blocks_num; +} + +static void anx7625_disable_pd_protocol(uint8_t bus) +{ + int ret; + + /* reset main ocm */ + ret = anx7625_reg_write(bus, RX_P0_ADDR, 0x88, 0x40); + /* Disable PD */ + ret |= anx7625_reg_write(bus, RX_P0_ADDR, AP_AV_STATUS, AP_DISABLE_PD); + /* release main ocm */ + ret |= anx7625_reg_write(bus, RX_P0_ADDR, 0x88, 0x00); + + if (ret < 0) + ANXERROR("Failed to disable PD feature.\n"); + else + ANXINFO("Disabled PD feature.\n"); +} + +#define FLASH_LOAD_STA 0x05 +#define FLASH_LOAD_STA_CHK (1 << 7) + +static int anx7625_power_on_init(uint8_t bus) +{ + int i, ret; + uint8_t val, version, revision; + + anx7625_reg_write(bus, RX_P0_ADDR, XTAL_FRQ_SEL, XTAL_FRQ_27M); + + for (i = 0; i < OCM_LOADING_TIME; i++) { + /* check interface */ + ret = anx7625_reg_read(bus, RX_P0_ADDR, FLASH_LOAD_STA, &val); + if (ret < 0) { + ANXERROR("Failed to load flash\n"); + return ret; + } + + if ((val & FLASH_LOAD_STA_CHK) != FLASH_LOAD_STA_CHK) { + mdelay(1); + continue; + } + ANXINFO("Init interface.\n"); + + + anx7625_disable_pd_protocol(bus); + anx7625_reg_read(bus, RX_P0_ADDR, OCM_FW_VERSION, &version); + anx7625_reg_read(bus, RX_P0_ADDR, OCM_FW_REVERSION, &revision); + ANXINFO("Firmware: ver %#02x, rev %#02x.\n", version, revision); + return 0; + } + return -1; +} + +static void anx7625_start_dp_work(uint8_t bus) +{ + int ret; + uint8_t val; + + /* not support HDCP */ + ret = anx7625_write_and(bus, RX_P1_ADDR, 0xee, 0x9f); + + /* try auth flag */ + ret |= anx7625_write_or(bus, RX_P1_ADDR, 0xec, 0x10); + /* interrupt for DRM */ + ret |= anx7625_write_or(bus, RX_P1_ADDR, 0xff, 0x01); + if (ret < 0) + return; + + ret = anx7625_reg_read(bus, RX_P1_ADDR, 0x86, &val); + if (ret < 0) + return; + + ANXINFO("Secure OCM version=%02x\n", val); +} + +static int anx7625_hpd_change_detect(uint8_t bus) +{ + int ret; + uint8_t status; + + ret = anx7625_reg_read(bus, RX_P0_ADDR, SYSTEM_STSTUS, &status); + if (ret < 0) { + ANXERROR("IO error: Failed to clear interrupt status.\n"); + return ret; + } + + if (status & HPD_STATUS) { + anx7625_start_dp_work(bus); + ANXINFO("HPD received 0x7e:0x45=%#x\n", status); + return 1; + } + return 0; +} + +static void anx7625_parse_edid(const struct edid *edid, + struct display_timing *dt) +{ + dt->pixelclock = edid->mode.pixel_clock; + + dt->hactive = edid->mode.ha; + dt->hsync_len = edid->mode.hspw; + dt->hback_porch = (edid->mode.hbl - edid->mode.hso - + edid->mode.hborder - edid->mode.hspw); + dt->hfront_porch = edid->mode.hso - edid->mode.hborder; + + dt->vactive = edid->mode.va; + dt->vsync_len = edid->mode.vspw; + dt->vfront_porch = edid->mode.vso - edid->mode.vborder; + dt->vback_porch = (edid->mode.vbl - edid->mode.vso - + edid->mode.vspw - edid->mode.vborder); + + ANXINFO("pixelclock(%d).\n" + " hactive(%d), hsync(%d), hfp(%d), hbp(%d)\n" + " vactive(%d), vsync(%d), vfp(%d), vbp(%d)\n", + dt->pixelclock, + dt->hactive, dt->hsync_len, dt->hfront_porch, dt->hback_porch, + dt->vactive, dt->vsync_len, dt->vfront_porch, dt->vback_porch); +} + +int anx7625_dp_start(uint8_t bus, const struct edid *edid) +{ + int ret; + struct display_timing dt; + + anx7625_parse_edid(edid, &dt); + + ret = anx7625_dsi_config(bus, &dt); + if (ret < 0) + ANXERROR("MIPI phy setup error.\n"); + else + ANXINFO("MIPI phy setup OK.\n"); + + return ret; +} + +int anx7625_dp_get_edid(uint8_t bus, struct edid *out) +{ + int block_num; + int ret; + u8 edid[FOUR_BLOCK_SIZE]; + + block_num = sp_tx_edid_read(bus, edid, FOUR_BLOCK_SIZE); + if (block_num < 0) { + ANXERROR("Failed to get eDP EDID.\n"); + return -1; + } + + ret = decode_edid(edid, (block_num + 1) * ONE_BLOCK_SIZE, out); + if (ret != EDID_CONFORMANT) { + ANXERROR("Failed to decode EDID.\n"); + return -1; + } + + return 0; +} + +int anx7625_init(uint8_t bus) +{ + int retry_hpd_change = 50; + int retry_power_on = 3; + + while (--retry_power_on) { + if (anx7625_power_on_init(bus) == 0) + break; + } + if (!retry_power_on) { + ANXERROR("Failed to power on.\n"); + return -1; + } + + while (--retry_hpd_change) { + mdelay(10); + int detected = anx7625_hpd_change_detect(bus); + if (detected < 0) + return -1; + if (detected > 0) + return 0; + } + + ANXERROR("Timed out to detect HPD change on bus %d.\n", bus); + return -1; +} diff --git a/src/drivers/analogix/anx7625/anx7625.h b/src/drivers/analogix/anx7625/anx7625.h new file mode 100644 index 0000000000..361ab13b4b --- /dev/null +++ b/src/drivers/analogix/anx7625/anx7625.h @@ -0,0 +1,363 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright(c) 2016, Analogix Semiconductor. All rights reserved. + * + */ + + +#include +#include + +#ifndef __ANX7625_H__ +#define __ANX7625_H__ + +#ifndef LOG_TAG +#define LOG_TAG "anx7625dp" +#endif + +#define ANX7625_DRV_VERSION "0.1.04" + +/* Loading OCM re-trying times */ +#define OCM_LOADING_TIME 10 + +/********* ANX7625 Register **********/ +#define ANXI2CSIM +#ifdef ANXI2CSIM +#define TX_P0_ADDR 0x38 +#define TX_P1_ADDR 0x3D +#define TX_P2_ADDR 0x39 +#define RX_P0_ADDR 0x3F +#define RX_P1_ADDR 0x42 +#define RX_P2_ADDR 0x2A +#define TCPC_INTERFACE_ADDR 0x2C +#else +#define TX_P0_ADDR 0x70 +#define TX_P1_ADDR 0x7A +#define TX_P2_ADDR 0x72 +#define RX_P0_ADDR 0x7e +#define RX_P1_ADDR 0x84 +#define RX_P2_ADDR 0x54 +#define TCPC_INTERFACE_ADDR 0x58 +#endif + +#define RSVD_00_ADDR 0x00 +#define RSVD_D1_ADDR 0xD1 +#define RSVD_60_ADDR 0x60 +#define RSVD_39_ADDR 0x39 +#define RSVD_7F_ADDR 0x7F + +/* anx7625 clock frequency in Hz */ +#define XTAL_FRQ (27*1000000) + +#define POST_DIVIDER_MIN 1 +#define POST_DIVIDER_MAX 16 +#define PLL_OUT_FREQ_MIN 520000000UL +#define PLL_OUT_FREQ_MAX 730000000UL +#define PLL_OUT_FREQ_ABS_MIN 300000000UL +#define PLL_OUT_FREQ_ABS_MAX 800000000UL +#define MAX_UNSIGNED_24BIT 16777215UL + +/***************************************************************/ +/* Register definition of device address 0x58 */ + +#define PRODUCT_ID_L 0x02 +#define PRODUCT_ID_H 0x03 + +#define INTR_ALERT_1 0xCC +#define INTR_SOFTWARE_INT (1<<3) +#define INTR_RECEIVED_MSG (1<<5) + +#define SYSTEM_STSTUS 0x45 +#define INTERFACE_CHANGE_INT 0x44 +#define HPD_STATUS_CHANGE 0x80 +#define HPD_STATUS 0x80 + +/******** END of I2C Address 0x58 ********/ + +/***************************************************************/ +/* Register definition of device address 0x70 */ +#define I2C_ADDR_70_DPTX 0x70 + +#define SP_TX_LINK_BW_SET_REG 0xA0 +#define SP_TX_LANE_COUNT_SET_REG 0xA1 + +#define M_VID_0 0xC0 +#define M_VID_1 0xC1 +#define M_VID_2 0xC2 +#define N_VID_0 0xC3 +#define N_VID_1 0xC4 +#define N_VID_2 0xC5 + +/***************************************************************/ +/* Register definition of device address 0x72 */ +#define AUX_RST 0x04 +#define RST_CTRL2 0x07 + +#define SP_TX_TOTAL_LINE_STA_L 0x24 +#define SP_TX_TOTAL_LINE_STA_H 0x25 +#define SP_TX_ACT_LINE_STA_L 0x26 +#define SP_TX_ACT_LINE_STA_H 0x27 +#define SP_TX_V_F_PORCH_STA 0x28 +#define SP_TX_V_SYNC_STA 0x29 +#define SP_TX_V_B_PORCH_STA 0x2A +#define SP_TX_TOTAL_PIXEL_STA_L 0x2B +#define SP_TX_TOTAL_PIXEL_STA_H 0x2C +#define SP_TX_ACT_PIXEL_STA_L 0x2D +#define SP_TX_ACT_PIXEL_STA_H 0x2E +#define SP_TX_H_F_PORCH_STA_L 0x2F +#define SP_TX_H_F_PORCH_STA_H 0x30 +#define SP_TX_H_SYNC_STA_L 0x31 +#define SP_TX_H_SYNC_STA_H 0x32 +#define SP_TX_H_B_PORCH_STA_L 0x33 +#define SP_TX_H_B_PORCH_STA_H 0x34 + +#define SP_TX_VID_CTRL 0x84 +#define SP_TX_BPC_MASK 0xE0 +#define SP_TX_BPC_6 0x00 +#define SP_TX_BPC_8 0x20 +#define SP_TX_BPC_10 0x40 +#define SP_TX_BPC_12 0x60 + +#define VIDEO_BIT_MATRIX_12 0x4c + +#define AUDIO_CHANNEL_STATUS_1 0xd0 +#define AUDIO_CHANNEL_STATUS_2 0xd1 +#define AUDIO_CHANNEL_STATUS_3 0xd2 +#define AUDIO_CHANNEL_STATUS_4 0xd3 +#define AUDIO_CHANNEL_STATUS_5 0xd4 +#define AUDIO_CHANNEL_STATUS_6 0xd5 +#define TDM_SLAVE_MODE 0x10 +#define I2S_SLAVE_MODE 0x08 + +#define AUDIO_CONTROL_REGISTER 0xe6 +#define TDM_TIMING_MODE 0x08 + +#define I2C_ADDR_72_DPTX 0x72 + +#define VIDEO_CONTROL_0 0x08 + +#define ACTIVE_LINES_L 0x14 +#define ACTIVE_LINES_H 0x15 /* note: bit[7:6] are reserved */ +#define VERTICAL_FRONT_PORCH 0x16 +#define VERTICAL_SYNC_WIDTH 0x17 +#define VERTICAL_BACK_PORCH 0x18 + +#define HORIZONTAL_TOTAL_PIXELS_L 0x19 +#define HORIZONTAL_TOTAL_PIXELS_H 0x1A /* note: bit[7:6] are reserved */ +#define HORIZONTAL_ACTIVE_PIXELS_L 0x1B +#define HORIZONTAL_ACTIVE_PIXELS_H 0x1C /* note: bit[7:6] are reserved */ +#define HORIZONTAL_FRONT_PORCH_L 0x1D +#define HORIZONTAL_FRONT_PORCH_H 0x1E /* note: bit[7:4] are reserved */ +#define HORIZONTAL_SYNC_WIDTH_L 0x1F +#define HORIZONTAL_SYNC_WIDTH_H 0x20 /* note: bit[7:4] are reserved */ +#define HORIZONTAL_BACK_PORCH_L 0x21 +#define HORIZONTAL_BACK_PORCH_H 0x22 /* note: bit[7:4] are reserved */ + +/******** END of I2C Address 0x72 *********/ +/***************************************************************/ +/* Register definition of device address 0x7e */ + +#define I2C_ADDR_7E_FLASH_CONTROLLER 0x7E + +#define XTAL_FRQ_SEL 0x3F +/* bit field positions */ +#define XTAL_FRQ_SEL_POS 5 +/* bit field values */ +#define XTAL_FRQ_19M2 (0 << XTAL_FRQ_SEL_POS) +#define XTAL_FRQ_27M (4 << XTAL_FRQ_SEL_POS) + +#define R_DSC_CTRL_0 0x40 +#define READ_STATUS_EN 7 +#define CLK_1MEG_RB 6 /* 1MHz clock reset; 0=reset, 0=reset release */ +#define DSC_BIST_DONE 1 /* bit[5:1]: 1=DSC MBIST pass */ +#define DSC_EN 0x01 /* 1=DSC enabled, 0=DSC disabled */ + +#define OCM_FW_VERSION 0x31 +#define OCM_FW_REVERSION 0x32 + +#define AP_AUX_ADDR_7_0 0x11 +#define AP_AUX_ADDR_15_8 0x12 +#define AP_AUX_ADDR_19_16 0x13 + +/* note: bit[0:3] AUX status, bit 4 op_en, bit 5 address only */ +#define AP_AUX_CTRL_STATUS 0x14 +#define AP_AUX_CTRL_OP_EN 0x10 +#define AP_AUX_CTRL_ADDRONLY 0x20 + +#define AP_AUX_BUFF_START 0x15 +#define PIXEL_CLOCK_L 0x25 +#define PIXEL_CLOCK_H 0x26 + +#define AP_AUX_COMMAND 0x27 /* com+len */ +/* bit 0&1: 3D video structure */ +/* 0x01: frame packing, 0x02:Line alternative, 0x03:Side-by-side(full) */ +#define AP_AV_STATUS 0x28 +#define AP_VIDEO_CHG (1<<2) +#define AP_AUDIO_CHG (1<<3) +#define AP_MIPI_MUTE (1<<4) /* 1:MIPI input mute, 0: ummute */ +#define AP_MIPI_RX_EN (1<<5) /* 1: MIPI RX input in 0: no RX in */ +#define AP_DISABLE_PD (1<<6) +#define AP_DISABLE_DISPLAY (1<<7) +/***************************************************************/ +/* Register definition of device address 0x84 */ +#define MIPI_PHY_CONTROL_3 0x03 +#define MIPI_HS_PWD_CLK 7 +#define MIPI_HS_RT_CLK 6 +#define MIPI_PD_CLK 5 +#define MIPI_CLK_RT_MANUAL_PD_EN 4 +#define MIPI_CLK_HS_MANUAL_PD_EN 3 +#define MIPI_CLK_DET_DET_BYPASS 2 +#define MIPI_CLK_MISS_CTRL 1 +#define MIPI_PD_LPTX_CH_MANUAL_PD_EN 0 + +#define MIPI_LANE_CTRL_0 0x05 +#define MIPI_TIME_HS_PRPR 0x08 + +/* After MIPI RX protocol layer received this many video frames, */ +/* protocol layer starts to reconstruct video stream from PHY */ +#define MIPI_VIDEO_STABLE_CNT 0x0A + +#define MIPI_LANE_CTRL_10 0x0F +#define MIPI_DIGITAL_ADJ_1 0x1B + +#define MIPI_PLL_M_NUM_23_16 0x1E +#define MIPI_PLL_M_NUM_15_8 0x1F +#define MIPI_PLL_M_NUM_7_0 0x20 +#define MIPI_PLL_N_NUM_23_16 0x21 +#define MIPI_PLL_N_NUM_15_8 0x22 +#define MIPI_PLL_N_NUM_7_0 0x23 + +#define MIPI_DIGITAL_PLL_6 0x2A +/* bit[7:6]: VCO band control, only effective */ +/* when MIPI_PLL_FORCE_BAND_EN (0x84:0x2B[6]) is 1 */ +#define MIPI_M_NUM_READY 0x10 +#define MIPI_N_NUM_READY 0x08 +#define STABLE_INTEGER_CNT_EN 0x04 +#define MIPI_PLL_TEST_BIT 0 +/* bit[1:0]: test point output select - */ +/* 00: VCO power, 01: dvdd_pdt, 10: dvdd, 11: vcox */ + +#define MIPI_DIGITAL_PLL_7 0x2B +#define MIPI_PLL_FORCE_N_EN 7 +#define MIPI_PLL_FORCE_BAND_EN 6 + +#define MIPI_PLL_VCO_TUNE_REG 4 +/* bit[5:4]: VCO metal capacitance - */ +/* 00: +20% fast, 01: +10% fast (default), 10: typical, 11: -10% slow */ +#define MIPI_PLL_VCO_TUNE_REG_VAL 0x30 + +#define MIPI_PLL_PLL_LDO_BIT 2 +/* bit[3:2]: vco_v2i power - */ +/* 00: 1.40V, 01: 1.45V (default), 10: 1.50V, 11: 1.55V */ +#define MIPI_PLL_RESET_N 0x02 +#define MIPI_FRQ_FORCE_NDET 0 + +#define MIPI_ALERT_CLR_0 0x2D +#define HS_link_error_clear 7 +/* This bit itself is S/C, and it clears 0x84:0x31[7] */ + +#define MIPI_ALERT_OUT_0 0x31 +#define check_sum_err_hs_sync 7 +/* This bit is cleared by 0x84:0x2D[7] */ + +#define MIPI_DIGITAL_PLL_8 0x33 +#define MIPI_POST_DIV_VAL 4 +/* n means divided by (n+1), n = 0~15 */ +#define MIPI_EN_LOCK_FRZ 3 +#define MIPI_FRQ_COUNTER_RST 2 +#define MIPI_FRQ_SET_REG_8 1 +/* bit 0 is reserved */ + +#define MIPI_DIGITAL_PLL_9 0x34 + +#define MIPI_DIGITAL_PLL_16 0x3B +#define MIPI_FRQ_FREEZE_NDET 7 +#define MIPI_FRQ_REG_SET_ENABLE 6 +#define MIPI_REG_FORCE_SEL_EN 5 +#define MIPI_REG_SEL_DIV_REG 4 +#define MIPI_REG_FORCE_PRE_DIV_EN 3 +/* bit 2 is reserved */ +#define MIPI_FREF_D_IND 1 +#define REF_CLK_27000kHz 1 +#define REF_CLK_19200kHz 0 +#define MIPI_REG_PLL_PLL_TEST_ENABLE 0 + +#define MIPI_DIGITAL_PLL_18 0x3D +#define FRQ_COUNT_RB_SEL 7 +#define REG_FORCE_POST_DIV_EN 6 +#define MIPI_DPI_SELECT 5 +#define SELECT_DSI 1 +#define SELECT_DPI 0 +#define REG_BAUD_DIV_RATIO 0 + +#define H_BLANK_L 0x3E +/* for DSC only */ +#define H_BLANK_H 0x3F +/* for DSC only; note: bit[7:6] are reserved */ +#define MIPI_SWAP 0x4A +#define MIPI_SWAP_CH0 7 +#define MIPI_SWAP_CH1 6 +#define MIPI_SWAP_CH2 5 +#define MIPI_SWAP_CH3 4 +#define MIPI_SWAP_CLK 3 +/* bit[2:0] are reserved */ + +/******** END of I2C Address 0x84 *********/ + +/* DPCD regs */ +#define DPCD_DPCD_REV 0x00 +#define DPCD_MAX_LINK_RATE 0x01 +#define DPCD_MAX_LANE_COUNT 0x02 + +/********* ANX7625 Register End **********/ + +/***************** Display *****************/ +enum AudioFs { + AUDIO_FS_441K = 0x00, + AUDIO_FS_48K = 0x02, + AUDIO_FS_32K = 0x03, + AUDIO_FS_882K = 0x08, + AUDIO_FS_96K = 0x0a, + AUDIO_FS_1764K = 0x0c, + AUDIO_FS_192K = 0x0e +}; + +enum AudioWdLen { + AUDIO_W_LEN_16_20MAX = 0x02, + AUDIO_W_LEN_18_20MAX = 0x04, + AUDIO_W_LEN_17_20MAX = 0x0c, + AUDIO_W_LEN_19_20MAX = 0x08, + AUDIO_W_LEN_20_20MAX = 0x0a, + AUDIO_W_LEN_20_24MAX = 0x03, + AUDIO_W_LEN_22_24MAX = 0x05, + AUDIO_W_LEN_21_24MAX = 0x0d, + AUDIO_W_LEN_23_24MAX = 0x09, + AUDIO_W_LEN_24_24MAX = 0x0b +}; + +#define I2S_CH_2 0x01 +#define TDM_CH_4 0x03 +#define TDM_CH_6 0x05 +#define TDM_CH_8 0x07 + +#define MAX_DPCD_BUFFER_SIZE 16 + +#define ONE_BLOCK_SIZE 128 +#define FOUR_BLOCK_SIZE (128*4) + +struct display_timing { + unsigned int pixelclock; + unsigned int hactive; + unsigned int hfront_porch; + unsigned int hback_porch; + unsigned int hsync_len; + unsigned int vactive; + unsigned int vfront_porch; + unsigned int vback_porch; + unsigned int vsync_len; +}; + +int anx7625_dp_start(uint8_t bus, const struct edid *edid); +int anx7625_dp_get_edid(uint8_t bus, struct edid *out); +int anx7625_init(uint8_t bus); +#endif /* __ANX7625_H__ */ From f4b9ec67842fa169134d87e3e236c1f8525b8cdc Mon Sep 17 00:00:00 2001 From: Wim Vervoorn Date: Fri, 13 Dec 2019 11:03:25 +0100 Subject: [PATCH 0723/1242] soc/intel/skylake: Add irq 11 to the LNK* _PRS The _PRS for the LNK* items don't contain irq 11. So this is not supposed to be used. Add irq 11 to the list as there is no reason not to allow this. BUG=N/A TEST=tested on facebook monolith Change-Id: I634d0ea8506a5e93359c652f74131231f5c13b02 Signed-off-by: Wim Vervoorn Reviewed-on: https://review.coreboot.org/c/coreboot/+/37690 Reviewed-by: Frans Hendriks Reviewed-by: Paul Menzel Tested-by: build bot (Jenkins) --- src/soc/intel/skylake/acpi/irqlinks.asl | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/src/soc/intel/skylake/acpi/irqlinks.asl b/src/soc/intel/skylake/acpi/irqlinks.asl index 1dd50ba2f7..b83c1cb84c 100644 --- a/src/soc/intel/skylake/acpi/irqlinks.asl +++ b/src/soc/intel/skylake/acpi/irqlinks.asl @@ -51,7 +51,7 @@ Device (LNKA) Name (_PRS, ResourceTemplate () { IRQ (Level, ActiveLow, Shared) - { 3, 4, 5, 6, 10, 12, 14, 15 } + { 3, 4, 5, 6, 10, 11, 12, 14, 15 } }) Method (_CRS, 0, Serialized) @@ -100,7 +100,7 @@ Device (LNKB) Name (_PRS, ResourceTemplate () { IRQ (Level, ActiveLow, Shared) - { 3, 4, 5, 6, 10, 12, 14, 15 } + { 3, 4, 5, 6, 10, 11, 12, 14, 15 } }) Method (_CRS, 0, Serialized) @@ -149,7 +149,7 @@ Device (LNKC) Name (_PRS, ResourceTemplate () { IRQ (Level, ActiveLow, Shared) - { 3, 4, 5, 6, 10, 12, 14, 15 } + { 3, 4, 5, 6, 10, 11, 12, 14, 15 } }) Method (_CRS, 0, Serialized) @@ -198,7 +198,7 @@ Device (LNKD) Name (_PRS, ResourceTemplate () { IRQ (Level, ActiveLow, Shared) - { 3, 4, 5, 6, 10, 12, 14, 15 } + { 3, 4, 5, 6, 10, 11, 12, 14, 15 } }) Method (_CRS, 0, Serialized) @@ -247,7 +247,7 @@ Device (LNKE) Name (_PRS, ResourceTemplate () { IRQ (Level, ActiveLow, Shared) - { 3, 4, 5, 6, 10, 12, 14, 15 } + { 3, 4, 5, 6, 10, 11, 12, 14, 15 } }) Method (_CRS, 0, Serialized) @@ -296,7 +296,7 @@ Device (LNKF) Name (_PRS, ResourceTemplate () { IRQ (Level, ActiveLow, Shared) - { 3, 4, 5, 6, 10, 12, 14, 15 } + { 3, 4, 5, 6, 10, 11, 12, 14, 15 } }) Method (_CRS, 0, Serialized) @@ -345,7 +345,7 @@ Device (LNKG) Name (_PRS, ResourceTemplate () { IRQ (Level, ActiveLow, Shared) - { 3, 4, 5, 6, 10, 12, 14, 15 } + { 3, 4, 5, 6, 10, 11, 12, 14, 15 } }) Method (_CRS, 0, Serialized) @@ -394,7 +394,7 @@ Device (LNKH) Name (_PRS, ResourceTemplate () { IRQ (Level, ActiveLow, Shared) - { 3, 4, 5, 6, 10, 12, 14, 15 } + { 3, 4, 5, 6, 10, 11, 12, 14, 15 } }) Method (_CRS, 0, Serialized) From 555efe47922c8b347ad7cd2c9759740e3e228164 Mon Sep 17 00:00:00 2001 From: Wim Vervoorn Date: Fri, 13 Dec 2019 14:28:15 +0100 Subject: [PATCH 0724/1242] soc/intel/skylake: Change SA_PCIEX_LENGTH to 256MB Skylake soc code sets the length of the PCIe configuration space to 64 MB while the specification allows up to 256 MB. Linux reports "acpi PNP0A08:00: [Firmware Info]: MMCONFIG for domain 0000 [bos 00-3f] only partially covers this bridge". Remove "select PCIEX_LENGTH_64MB" from Kconfig so the default 256MB will be used and the size can be reduced on the mainboard level when required. BUG=N/A TEST=tested on facebook monolith Tested is by booting Linux 4.15 and analyzing the coreboot and Linux dmesg to make sure the memory range is reported correctly and doesn't create an overlap. Change-Id: I8a06b9fba5ad561d8595292a73136091ab532faa Signed-off-by: Wim Vervoorn Reviewed-on: https://review.coreboot.org/c/coreboot/+/37704 Reviewed-by: Arthur Heymans Reviewed-by: Patrick Rudolph Tested-by: build bot (Jenkins) --- src/soc/intel/skylake/Kconfig | 1 - 1 file changed, 1 deletion(-) diff --git a/src/soc/intel/skylake/Kconfig b/src/soc/intel/skylake/Kconfig index 31f809a475..5fc2a2d240 100644 --- a/src/soc/intel/skylake/Kconfig +++ b/src/soc/intel/skylake/Kconfig @@ -43,7 +43,6 @@ config CPU_SPECIFIC_OPTIONS select NO_FIXED_XIP_ROM_SIZE select PARALLEL_MP select PARALLEL_MP_AP_WORK - select PCIEX_LENGTH_64MB select PLATFORM_USES_FSP2_0 select REG_SCRIPT select SA_ENABLE_DPR From 9612a3c32a95791c1084ade5ae89e9147b2c2b7b Mon Sep 17 00:00:00 2001 From: Elyes HAOUAS Date: Mon, 16 Dec 2019 05:46:16 +0100 Subject: [PATCH 0725/1242] cpu/intel: Remove ROMCC header guards and code MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Intel's platforms use a GCC compiled bootblock. Change-Id: I779d7115fee75df9356873e9cc66d43280821812 Signed-off-by: Elyes HAOUAS Reviewed-on: https://review.coreboot.org/c/coreboot/+/37758 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki Reviewed-by: Nico Huber --- src/cpu/intel/car/non-evict/cache_as_ram.S | 3 --- src/cpu/intel/car/romstage.c | 13 ------------- src/cpu/intel/microcode/Kconfig | 2 +- src/cpu/intel/microcode/microcode.c | 18 +----------------- 4 files changed, 2 insertions(+), 34 deletions(-) diff --git a/src/cpu/intel/car/non-evict/cache_as_ram.S b/src/cpu/intel/car/non-evict/cache_as_ram.S index 5a668c42df..4dee0a8002 100644 --- a/src/cpu/intel/car/non-evict/cache_as_ram.S +++ b/src/cpu/intel/car/non-evict/cache_as_ram.S @@ -28,11 +28,8 @@ _cache_as_ram_setup: bootblock_pre_c_entry: - -#if !CONFIG(ROMCC_BOOTBLOCK) movl $cache_as_ram, %esp /* return address */ jmp check_mtrr /* Check if CPU properly reset */ -#endif cache_as_ram: post_code(0x20) diff --git a/src/cpu/intel/car/romstage.c b/src/cpu/intel/car/romstage.c index 1f8eb9a10e..bd6a5a9b8c 100644 --- a/src/cpu/intel/car/romstage.c +++ b/src/cpu/intel/car/romstage.c @@ -71,19 +71,6 @@ static void romstage_main(unsigned long bist) /* We do not return here. */ } -#if CONFIG(ROMCC_BOOTBLOCK) -/* This wrapper enables easy transition away from ROMCC_BOOTBLOCK - * keeping changes in cache_as_ram.S easy to manage. - */ -asmlinkage void bootblock_c_entry_bist(uint64_t base_timestamp, uint32_t bist) -{ - timestamp_init(base_timestamp); - timestamp_add_now(TS_START_ROMSTAGE); - romstage_main(bist); -} -#endif - - /* We don't carry BIST from bootblock in a good location to read from. * Any error should have been reported in bootblock already. */ diff --git a/src/cpu/intel/microcode/Kconfig b/src/cpu/intel/microcode/Kconfig index 73afe0bb45..238aad745d 100644 --- a/src/cpu/intel/microcode/Kconfig +++ b/src/cpu/intel/microcode/Kconfig @@ -1,7 +1,7 @@ config MICROCODE_UPDATE_PRE_RAM bool depends on SUPPORT_CPU_UCODE_IN_CBFS - default y if !ROMCC_BOOTBLOCK + default y help Select this option if you want to update the microcode during the cache as ram setup. diff --git a/src/cpu/intel/microcode/microcode.c b/src/cpu/intel/microcode/microcode.c index 80470bf236..90138be236 100644 --- a/src/cpu/intel/microcode/microcode.c +++ b/src/cpu/intel/microcode/microcode.c @@ -15,11 +15,7 @@ #include #include -#if !defined(__ROMCC__) #include -#else -#include -#endif #include #include #include @@ -141,22 +137,11 @@ const void *intel_microcode_find(void) unsigned int x86_model, x86_family; msr_t msr; -#ifdef __ROMCC__ - struct cbfs_file *microcode_file; - - microcode_file = walkcbfs_head((char *) MICROCODE_CBFS_FILE); - if (!microcode_file) - return NULL; - - ucode_updates = CBFS_SUBHEADER(microcode_file); - microcode_len = ntohl(microcode_file->len); -#else ucode_updates = cbfs_boot_map_with_leak(MICROCODE_CBFS_FILE, CBFS_TYPE_MICROCODE, µcode_len); if (ucode_updates == NULL) return NULL; -#endif /* CPUID sets MSR 0x8B if a microcode update has been loaded. */ msr.lo = 0; @@ -201,8 +186,7 @@ const void *intel_microcode_find(void) microcode_len -= update_size; } - /* ROMCC doesn't like NULL. */ - return (void *)0; + return NULL; } void intel_update_microcode_from_cbfs(void) From 7a1b60b694f397e4a7c3ddd8c7242f8c312212f8 Mon Sep 17 00:00:00 2001 From: Arthur Heymans Date: Thu, 28 Nov 2019 16:20:44 +0100 Subject: [PATCH 0726/1242] mb/emulation/qemu-q35: Drop unused romcc-related Kconfig MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Change-Id: Ib4adbd3f6e850ced1cb93e47ce4f45249dc032c5 Signed-off-by: Arthur Heymans Reviewed-on: https://review.coreboot.org/c/coreboot/+/37338 Tested-by: build bot (Jenkins) Reviewed-by: HAOUAS Elyes Reviewed-by: Kyösti Mälkki --- src/mainboard/emulation/qemu-q35/Kconfig | 4 ---- 1 file changed, 4 deletions(-) diff --git a/src/mainboard/emulation/qemu-q35/Kconfig b/src/mainboard/emulation/qemu-q35/Kconfig index 3a9bb6f04e..ee430d0aeb 100644 --- a/src/mainboard/emulation/qemu-q35/Kconfig +++ b/src/mainboard/emulation/qemu-q35/Kconfig @@ -47,10 +47,6 @@ config MAINBOARD_PART_NUMBER string default "QEMU x86 q35/ich9" -config BOOTBLOCK_MAINBOARD_INIT - string - default "mainboard/emulation/qemu-q35/bootblock.c" - config MMCONF_BASE_ADDRESS hex default 0xb0000000 From 297b6b862a724de70abf33f681f63b6a3d84c24b Mon Sep 17 00:00:00 2001 From: "Eugene D. Myers" Date: Tue, 2 Jul 2019 14:06:46 -0400 Subject: [PATCH 0727/1242] include/cpu/x86: Add STM Support Addtions to include/cpu/x86 include for STM support. Change-Id: I2b8e68b2928aefc7996b6a9560c52f71c7c0e1d0 Signed-off-by: Eugene D. Myers Reviewed-on: https://review.coreboot.org/c/coreboot/+/33985 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth Reviewed-by: ron minnich --- src/include/cpu/x86/msr.h | 6 ++++++ src/include/cpu/x86/smm.h | 3 +++ 2 files changed, 9 insertions(+) diff --git a/src/include/cpu/x86/msr.h b/src/include/cpu/x86/msr.h index 2710e7f1fc..0da8b564fa 100644 --- a/src/include/cpu/x86/msr.h +++ b/src/include/cpu/x86/msr.h @@ -30,6 +30,10 @@ #define IA32_BIOS_SIGN_ID 0x8b #define IA32_MPERF 0xe7 #define IA32_APERF 0xe8 +/* STM */ +#define IA32_SMM_MONITOR_CTL_MSR 0x9B +#define SMBASE_RO_MSR 0x98 +#define IA32_SMM_MONITOR_VALID (1<<0) #define IA32_MCG_CAP 0x179 #define MCG_CTL_P (1 << 3) #define MCA_BANKS_MASK 0xff @@ -48,6 +52,8 @@ #define IA32_PAT 0x277 #define IA32_MC0_CTL 0x400 #define IA32_MC0_STATUS 0x401 +#define IA32_VMX_BASIC_MSR 0x480 +#define IA32_VMX_MISC_MSR 0x485 #define MCA_STATUS_HI_VAL (1UL << (63 - 32)) #define MCA_STATUS_HI_OVERFLOW (1UL << (62 - 32)) #define MCA_STATUS_HI_UC (1UL << (61 - 32)) diff --git a/src/include/cpu/x86/smm.h b/src/include/cpu/x86/smm.h index cf107b121a..9efe2e04eb 100644 --- a/src/include/cpu/x86/smm.h +++ b/src/include/cpu/x86/smm.h @@ -64,6 +64,9 @@ extern unsigned char _binary_smm_end[]; struct smm_runtime { u32 smbase; u32 save_state_size; + u32 num_cpus; + /* STM's 32bit entry into SMI handler */ + u32 start32_offset; /* The apic_id_to_cpu provides a mapping from APIC id to CPU number. * The CPU number is indicated by the index into the array by matching * the default APIC id and value at the index. The stub loader From 413a742ad91a454ef2bf2d7f2e3ed149d3897ea3 Mon Sep 17 00:00:00 2001 From: Julius Werner Date: Mon, 16 Dec 2019 10:13:34 -0800 Subject: [PATCH 0728/1242] vboot: Fix MOCK_SECDATA for new naming scheme CB:37655 updated all secdata_xxx to secdata_firmware_xxx, but forgot the code that's only compiled when MOCK_SECDATA is set. This patch fixes it. Change-Id: Icf12fe405d7ce46345ccbdcb76f6aa1b56ed0194 Signed-off-by: Julius Werner Reviewed-on: https://review.coreboot.org/c/coreboot/+/37772 Reviewed-by: Furquan Shaikh Reviewed-by: Joel Kitching Tested-by: build bot (Jenkins) --- src/security/vboot/secdata_mock.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/security/vboot/secdata_mock.c b/src/security/vboot/secdata_mock.c index de58bf5909..a6c4afb170 100644 --- a/src/security/vboot/secdata_mock.c +++ b/src/security/vboot/secdata_mock.c @@ -45,7 +45,7 @@ vb2_error_t vb2ex_tpm_clear_owner(struct vb2_context *ctx) vb2_error_t antirollback_read_space_firmware(struct vb2_context *ctx) { - vb2api_secdata_create(ctx); + vb2api_secdata_firmware_create(ctx); return VB2_SUCCESS; } From 26060bc7c852b6b6ecf6ecb0e225d4ef414c8f6f Mon Sep 17 00:00:00 2001 From: Julius Werner Date: Mon, 16 Dec 2019 10:18:15 -0800 Subject: [PATCH 0729/1242] configs: add config.google_kevin_secdata_mock This patch adds a BOARD_GOOGLE_KEVIN variant config that enables CONFIG_VBOOT_MOCK_SECDATA. This is to ensure that Jenkins will build the MOCK_SECDATA-specific code at least once, to be sure we don't accidentally break it during refactoring. Change-Id: Ib0ffaccdf4601d6bfb889ae289d1d7df18bed1fd Signed-off-by: Julius Werner Reviewed-on: https://review.coreboot.org/c/coreboot/+/37773 Reviewed-by: Furquan Shaikh Reviewed-by: Joel Kitching Tested-by: build bot (Jenkins) --- configs/config.google_kevin_secdata_mock | 5 +++++ 1 file changed, 5 insertions(+) create mode 100644 configs/config.google_kevin_secdata_mock diff --git a/configs/config.google_kevin_secdata_mock b/configs/config.google_kevin_secdata_mock new file mode 100644 index 0000000000..97d6a3a30c --- /dev/null +++ b/configs/config.google_kevin_secdata_mock @@ -0,0 +1,5 @@ +CONFIG_VENDOR_GOOGLE=y +CONFIG_BOARD_GOOGLE_KEVIN=y +CONFIG_CHROMEOS=y +CONFIG_VBOOT_MOCK_SECDATA=y +CONFIG_PAYLOAD_NONE=y From 85d44f4a5e6c72e64f38ef613205994b25b4f992 Mon Sep 17 00:00:00 2001 From: Joel Kitching Date: Tue, 17 Dec 2019 17:34:05 +0800 Subject: [PATCH 0730/1242] vboot: remove 2lib headers from Makefile Only headers from firmware/lib should be imported. As far as I can tell, nothing imports 2lib headers directly anymore, so we can get rid of this CFLAG. BUG=b:124141368, chromium:968464 TEST=make clean && make test-abuild BRANCH=none Change-Id: Ie5f3fe1d0180113b332e57ed07d4cfe563e7ecf2 Signed-off-by: Joel Kitching Reviewed-on: https://review.coreboot.org/c/coreboot/+/37786 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin --- src/security/vboot/Makefile.inc | 2 -- 1 file changed, 2 deletions(-) diff --git a/src/security/vboot/Makefile.inc b/src/security/vboot/Makefile.inc index 5292bd142d..8052549bde 100644 --- a/src/security/vboot/Makefile.inc +++ b/src/security/vboot/Makefile.inc @@ -123,8 +123,6 @@ $(1)-srcs += $$(VBOOT_LIB_$(1)) endef # vboot-for-stage -CFLAGS_common += -I3rdparty/vboot/firmware/2lib/include - $(eval $(call vboot-for-stage,bootblock)) $(eval $(call vboot-for-stage,romstage)) $(eval $(call vboot-for-stage,ramstage)) From f0b79daeba20230d69b2d3e78d363f72dd3b331a Mon Sep 17 00:00:00 2001 From: Elyes HAOUAS Date: Thu, 5 Dec 2019 01:02:31 +0100 Subject: [PATCH 0731/1242] src: Remove unused 'include ' MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Change-Id: I72d7b83ef8c7f9b5b4b4376839279eff9b0a5f8f Signed-off-by: Elyes HAOUAS Reviewed-on: https://review.coreboot.org/c/coreboot/+/37484 Reviewed-by: Frans Hendriks Reviewed-by: Kyösti Mälkki Tested-by: build bot (Jenkins) --- src/cpu/intel/model_206ax/model_206ax_init.c | 1 - src/southbridge/intel/i82801gx/smihandler.c | 1 - src/southbridge/intel/i82801jx/smihandler.c | 1 - src/southbridge/intel/ibexpeak/smihandler.c | 1 - 4 files changed, 4 deletions(-) diff --git a/src/cpu/intel/model_206ax/model_206ax_init.c b/src/cpu/intel/model_206ax/model_206ax_init.c index cc20676fff..2571f8cb40 100644 --- a/src/cpu/intel/model_206ax/model_206ax_init.c +++ b/src/cpu/intel/model_206ax/model_206ax_init.c @@ -26,7 +26,6 @@ #include #include #include -#include #include "model_206ax.h" #include "chip.h" #include diff --git a/src/southbridge/intel/i82801gx/smihandler.c b/src/southbridge/intel/i82801gx/smihandler.c index 16ceb13e7e..c7ee5664bd 100644 --- a/src/southbridge/intel/i82801gx/smihandler.c +++ b/src/southbridge/intel/i82801gx/smihandler.c @@ -18,7 +18,6 @@ #include #include #include -#include #include #include "i82801gx.h" diff --git a/src/southbridge/intel/i82801jx/smihandler.c b/src/southbridge/intel/i82801jx/smihandler.c index 667a8531da..6a8a8daed7 100644 --- a/src/southbridge/intel/i82801jx/smihandler.c +++ b/src/southbridge/intel/i82801jx/smihandler.c @@ -20,7 +20,6 @@ #include #include #include -#include #include #include "i82801jx.h" diff --git a/src/southbridge/intel/ibexpeak/smihandler.c b/src/southbridge/intel/ibexpeak/smihandler.c index 36688422a6..05e7dd2b49 100644 --- a/src/southbridge/intel/ibexpeak/smihandler.c +++ b/src/southbridge/intel/ibexpeak/smihandler.c @@ -23,7 +23,6 @@ #include #include #include -#include #include #include #include From eb34d8bf18f213b85055189df95fa8b1cf2e928e Mon Sep 17 00:00:00 2001 From: Elyes HAOUAS Date: Wed, 27 Nov 2019 10:11:38 +0100 Subject: [PATCH 0732/1242] src: Remove unused 'include ' MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Change-Id: I9eedae837634beb5a545d97fdf9c1810faba5138 Signed-off-by: Elyes HAOUAS Reviewed-on: https://review.coreboot.org/c/coreboot/+/37271 Reviewed-by: Frans Hendriks Reviewed-by: Kyösti Mälkki Tested-by: build bot (Jenkins) --- src/mainboard/emulation/qemu-power8/bootblock.c | 1 - src/mainboard/google/cheza/mainboard.c | 1 - src/mainboard/google/mistral/mainboard.c | 1 - src/mainboard/google/trogdor/mainboard.c | 1 - src/soc/intel/apollolake/fspcar.c | 2 +- src/soc/intel/broadwell/romstage/romstage.c | 1 - 6 files changed, 1 insertion(+), 6 deletions(-) diff --git a/src/mainboard/emulation/qemu-power8/bootblock.c b/src/mainboard/emulation/qemu-power8/bootblock.c index ec30c879f1..d59ab37351 100644 --- a/src/mainboard/emulation/qemu-power8/bootblock.c +++ b/src/mainboard/emulation/qemu-power8/bootblock.c @@ -13,7 +13,6 @@ * GNU General Public License for more details. */ -#include #include #include diff --git a/src/mainboard/google/cheza/mainboard.c b/src/mainboard/google/cheza/mainboard.c index 7a19d32e9c..804906a37a 100644 --- a/src/mainboard/google/cheza/mainboard.c +++ b/src/mainboard/google/cheza/mainboard.c @@ -14,7 +14,6 @@ */ #include -#include #include #include diff --git a/src/mainboard/google/mistral/mainboard.c b/src/mainboard/google/mistral/mainboard.c index d50758c9e3..e36a1c70a7 100644 --- a/src/mainboard/google/mistral/mainboard.c +++ b/src/mainboard/google/mistral/mainboard.c @@ -14,7 +14,6 @@ */ #include -#include #include #include diff --git a/src/mainboard/google/trogdor/mainboard.c b/src/mainboard/google/trogdor/mainboard.c index 63fac19984..0dd26243a8 100644 --- a/src/mainboard/google/trogdor/mainboard.c +++ b/src/mainboard/google/trogdor/mainboard.c @@ -13,7 +13,6 @@ * GNU General Public License for more details. */ -#include #include #include #include diff --git a/src/soc/intel/apollolake/fspcar.c b/src/soc/intel/apollolake/fspcar.c index a284116bac..40bacd7ad2 100644 --- a/src/soc/intel/apollolake/fspcar.c +++ b/src/soc/intel/apollolake/fspcar.c @@ -13,7 +13,7 @@ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. */ -#include + #include const FSPT_UPD temp_ram_init_params = { diff --git a/src/soc/intel/broadwell/romstage/romstage.c b/src/soc/intel/broadwell/romstage/romstage.c index 96218f4ba4..6294b8adf3 100644 --- a/src/soc/intel/broadwell/romstage/romstage.c +++ b/src/soc/intel/broadwell/romstage/romstage.c @@ -17,7 +17,6 @@ #include #include #include -#include #include #include #include From 1a8dbfc89991d05362933f0cd8c9a2e53b389412 Mon Sep 17 00:00:00 2001 From: Elyes HAOUAS Date: Wed, 18 Dec 2019 13:40:50 +0100 Subject: [PATCH 0733/1242] cpu/x86/mp_init: Fix typo Change-Id: Iee9cd3dc51937774b990bc6f9e00bb82e0132e76 Signed-off-by: Elyes HAOUAS Reviewed-on: https://review.coreboot.org/c/coreboot/+/37811 Reviewed-by: Paul Menzel Reviewed-by: Frans Hendriks Tested-by: build bot (Jenkins) --- src/cpu/x86/mp_init.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/cpu/x86/mp_init.c b/src/cpu/x86/mp_init.c index 29ae3de87a..45776f8186 100644 --- a/src/cpu/x86/mp_init.c +++ b/src/cpu/x86/mp_init.c @@ -352,7 +352,7 @@ static atomic_t *load_sipi_vector(struct mp_params *mp_params) sp->msr_count = num_msrs; /* Provide pointer to microcode patch. */ sp->microcode_ptr = (uint32_t)mp_params->microcode_pointer; - /* Pass on abiility to load microcode in parallel. */ + /* Pass on ability to load microcode in parallel. */ if (mp_params->parallel_microcode_load) sp->microcode_lock = 0; else From 6dc2fda469954b53263cfd98f501b8a73985b68f Mon Sep 17 00:00:00 2001 From: Aaron Durbin Date: Wed, 18 Dec 2019 15:44:40 +0000 Subject: [PATCH 0734/1242] Revert "include/cpu/x86: Add STM Support" MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This reverts commit 297b6b862a724de70abf33f681f63b6a3d84c24b. Reason for revert: breaks smm. No code is using these fields. Original patch incomplete. Change-Id: I6acf15dc9d77ed8a83b98f086f2a0b306c584a9b Signed-off-by: Aaron Durbin Reviewed-on: https://review.coreboot.org/c/coreboot/+/37096 Reviewed-by: ron minnich Reviewed-by: Werner Zeh Reviewed-by: Kyösti Mälkki Tested-by: build bot (Jenkins) --- src/include/cpu/x86/msr.h | 6 ------ src/include/cpu/x86/smm.h | 3 --- 2 files changed, 9 deletions(-) diff --git a/src/include/cpu/x86/msr.h b/src/include/cpu/x86/msr.h index 0da8b564fa..2710e7f1fc 100644 --- a/src/include/cpu/x86/msr.h +++ b/src/include/cpu/x86/msr.h @@ -30,10 +30,6 @@ #define IA32_BIOS_SIGN_ID 0x8b #define IA32_MPERF 0xe7 #define IA32_APERF 0xe8 -/* STM */ -#define IA32_SMM_MONITOR_CTL_MSR 0x9B -#define SMBASE_RO_MSR 0x98 -#define IA32_SMM_MONITOR_VALID (1<<0) #define IA32_MCG_CAP 0x179 #define MCG_CTL_P (1 << 3) #define MCA_BANKS_MASK 0xff @@ -52,8 +48,6 @@ #define IA32_PAT 0x277 #define IA32_MC0_CTL 0x400 #define IA32_MC0_STATUS 0x401 -#define IA32_VMX_BASIC_MSR 0x480 -#define IA32_VMX_MISC_MSR 0x485 #define MCA_STATUS_HI_VAL (1UL << (63 - 32)) #define MCA_STATUS_HI_OVERFLOW (1UL << (62 - 32)) #define MCA_STATUS_HI_UC (1UL << (61 - 32)) diff --git a/src/include/cpu/x86/smm.h b/src/include/cpu/x86/smm.h index 9efe2e04eb..cf107b121a 100644 --- a/src/include/cpu/x86/smm.h +++ b/src/include/cpu/x86/smm.h @@ -64,9 +64,6 @@ extern unsigned char _binary_smm_end[]; struct smm_runtime { u32 smbase; u32 save_state_size; - u32 num_cpus; - /* STM's 32bit entry into SMI handler */ - u32 start32_offset; /* The apic_id_to_cpu provides a mapping from APIC id to CPU number. * The CPU number is indicated by the index into the array by matching * the default APIC id and value at the index. The stub loader From 025cb700a1e8c5d80f1f22fa57b817d8aae59234 Mon Sep 17 00:00:00 2001 From: Elyes HAOUAS Date: Sat, 30 Nov 2019 17:27:19 +0100 Subject: [PATCH 0735/1242] vendorcode/cavium/bdk/libbdk-hal: Add missing MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Change-Id: Id52603c525cce1bead423d188e23f6efd50511a9 Signed-off-by: Elyes HAOUAS Reviewed-on: https://review.coreboot.org/c/coreboot/+/37377 Reviewed-by: Kyösti Mälkki Tested-by: build bot (Jenkins) --- src/vendorcode/cavium/bdk/libbdk-hal/bdk-config.c | 1 + 1 file changed, 1 insertion(+) diff --git a/src/vendorcode/cavium/bdk/libbdk-hal/bdk-config.c b/src/vendorcode/cavium/bdk/libbdk-hal/bdk-config.c index e078e7476f..cc6a5ddb0b 100644 --- a/src/vendorcode/cavium/bdk/libbdk-hal/bdk-config.c +++ b/src/vendorcode/cavium/bdk/libbdk-hal/bdk-config.c @@ -12,6 +12,7 @@ #include #include +#include #include #include #include From c184e65ed9c7ea00fdc342da88e32e9caba53e66 Mon Sep 17 00:00:00 2001 From: Elyes HAOUAS Date: Sat, 30 Nov 2019 18:23:59 +0100 Subject: [PATCH 0736/1242] vendorcode/cavium/bdk/libbdk-hal/device: Add missing MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Change-Id: I64876a2b6cffdabf3e365fc07017adb14f086ecc Signed-off-by: Elyes HAOUAS Reviewed-on: https://review.coreboot.org/c/coreboot/+/37380 Reviewed-by: Kyösti Mälkki Tested-by: build bot (Jenkins) --- src/vendorcode/cavium/bdk/libbdk-hal/device/bdk-device.c | 1 + 1 file changed, 1 insertion(+) diff --git a/src/vendorcode/cavium/bdk/libbdk-hal/device/bdk-device.c b/src/vendorcode/cavium/bdk/libbdk-hal/device/bdk-device.c index 0df70ebc47..21e43a4326 100644 --- a/src/vendorcode/cavium/bdk/libbdk-hal/device/bdk-device.c +++ b/src/vendorcode/cavium/bdk/libbdk-hal/device/bdk-device.c @@ -37,6 +37,7 @@ * ARISING OUT OF USE OR PERFORMANCE OF THE SOFTWARE LIES WITH YOU. ***********************license end**************************************/ #include +#include #include #include "libbdk-arch/bdk-csrs-ap.h" #include "libbdk-arch/bdk-csrs-pccpf.h" From 3917904878ca1cfc16b553a1ba9e87922dc7e030 Mon Sep 17 00:00:00 2001 From: Elyes HAOUAS Date: Sat, 30 Nov 2019 19:06:14 +0100 Subject: [PATCH 0737/1242] vendorcode/cavium/bdk/libbdk-hal/bdk-qlm.c: Add missing MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Change-Id: I70029700bfb297ac06561056da730731a2ca1e8b Signed-off-by: Elyes HAOUAS Reviewed-on: https://review.coreboot.org/c/coreboot/+/33682 Reviewed-by: Kyösti Mälkki Tested-by: build bot (Jenkins) --- src/vendorcode/cavium/bdk/libbdk-hal/bdk-qlm.c | 1 + 1 file changed, 1 insertion(+) diff --git a/src/vendorcode/cavium/bdk/libbdk-hal/bdk-qlm.c b/src/vendorcode/cavium/bdk/libbdk-hal/bdk-qlm.c index b9552d4052..9fecfcc24c 100644 --- a/src/vendorcode/cavium/bdk/libbdk-hal/bdk-qlm.c +++ b/src/vendorcode/cavium/bdk/libbdk-hal/bdk-qlm.c @@ -37,6 +37,7 @@ * ARISING OUT OF USE OR PERFORMANCE OF THE SOFTWARE LIES WITH YOU. ***********************license end**************************************/ #include +#include #include #include "libbdk-arch/bdk-csrs-gser.h" #include "libbdk-arch/bdk-csrs-gsern.h" From 4f66cb9b2867bcdeb47df9fe76e8893d53f85fb8 Mon Sep 17 00:00:00 2001 From: Elyes HAOUAS Date: Sun, 1 Dec 2019 13:21:52 +0100 Subject: [PATCH 0738/1242] src: Add missing include MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Change-Id: Iabe55bfbc8e047c0791c21d162767081a181b6c5 Signed-off-by: Elyes HAOUAS Reviewed-on: https://review.coreboot.org/c/coreboot/+/37411 Reviewed-by: Kyösti Mälkki Tested-by: build bot (Jenkins) --- src/drivers/i2c/ptn3460/ptn3460.h | 2 +- src/drivers/ipmi/ipmi_ops.c | 1 + src/ec/lenovo/h8/bluetooth.c | 1 + 3 files changed, 3 insertions(+), 1 deletion(-) diff --git a/src/drivers/i2c/ptn3460/ptn3460.h b/src/drivers/i2c/ptn3460/ptn3460.h index 4b9834eb9d..f8242f8aef 100644 --- a/src/drivers/i2c/ptn3460/ptn3460.h +++ b/src/drivers/i2c/ptn3460/ptn3460.h @@ -16,7 +16,7 @@ #ifndef _I2C_PTN3460_H_ #define _I2C_PTN3460_H_ -#include +#include #define PTN_EDID_OFF 0x00 #define PTN_EDID_LEN 0x80 diff --git a/src/drivers/ipmi/ipmi_ops.c b/src/drivers/ipmi/ipmi_ops.c index 8a189bdbe1..a53929a29a 100644 --- a/src/drivers/ipmi/ipmi_ops.c +++ b/src/drivers/ipmi/ipmi_ops.c @@ -17,6 +17,7 @@ #include #include "ipmi_ops.h" #include +#include enum cb_err ipmi_init_and_start_bmc_wdt(const int port, uint16_t countdown, uint8_t action) diff --git a/src/ec/lenovo/h8/bluetooth.c b/src/ec/lenovo/h8/bluetooth.c index c3a2555780..436b319084 100644 --- a/src/ec/lenovo/h8/bluetooth.c +++ b/src/ec/lenovo/h8/bluetooth.c @@ -18,6 +18,7 @@ #include #include #include +#include #include "h8.h" #include "chip.h" From 1cb9cd5798966bf026e5f1ef3abf7642fa1bc41b Mon Sep 17 00:00:00 2001 From: Arthur Heymans Date: Thu, 28 Nov 2019 16:05:08 +0100 Subject: [PATCH 0739/1242] Drop ROMCC code and header guards MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Change-Id: I730f80afd8aad250f26534435aec24bea75a849c Signed-off-by: Arthur Heymans Reviewed-on: https://review.coreboot.org/c/coreboot/+/37334 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki Reviewed-by: HAOUAS Elyes --- src/arch/x86/assembly_entry.S | 25 ------- src/arch/x86/c_start.S | 2 +- src/arch/x86/include/arch/acpi.h | 2 +- src/arch/x86/include/arch/cpu.h | 9 +-- src/arch/x86/include/arch/hlt.h | 7 -- src/arch/x86/include/arch/io.h | 34 --------- src/arch/x86/include/arch/mmio.h | 4 -- .../x86/include/arch/pci_mmio_cfg_romcc.h | 70 ------------------- src/arch/x86/include/arch/pci_ops.h | 6 -- .../include/commonlib/cbfs_serialized.h | 7 -- src/commonlib/include/commonlib/helpers.h | 9 +-- src/console/die.c | 3 - src/console/post.c | 7 -- src/cpu/x86/16bit/entry16.inc | 3 - src/include/console/console.h | 9 --- src/include/console/uart.h | 3 - src/include/cpu/amd/mtrr.h | 2 +- src/include/cpu/x86/cache.h | 17 ----- src/include/cpu/x86/cr.h | 5 -- src/include/cpu/x86/msr.h | 16 ----- src/include/cpu/x86/mtrr.h | 6 +- src/include/cpu/x86/tsc.h | 3 - src/include/device/device.h | 9 --- src/include/device/mmio.h | 3 - src/include/device/pci_mmio_cfg.h | 3 - src/include/device/pci_ops.h | 4 -- src/include/endian.h | 2 - src/include/halt.h | 4 -- src/include/lib.h | 2 - src/include/stdbool.h | 5 +- src/include/stddef.h | 2 - src/include/stdint.h | 12 ---- src/include/string.h | 4 -- src/include/swab.h | 6 +- .../security/verified_boot/vboot_check.c | 7 -- 35 files changed, 13 insertions(+), 299 deletions(-) delete mode 100644 src/arch/x86/include/arch/pci_mmio_cfg_romcc.h diff --git a/src/arch/x86/assembly_entry.S b/src/arch/x86/assembly_entry.S index 9d6f5a42b4..fef5ce9240 100644 --- a/src/arch/x86/assembly_entry.S +++ b/src/arch/x86/assembly_entry.S @@ -13,8 +13,6 @@ #include -#if !CONFIG(ROMCC_BOOTBLOCK) - /* * This path is for stages that are post bootblock. The gdt is reloaded * to accommodate platforms that are executing out of CAR. In order to @@ -60,26 +58,3 @@ debug_spinloop: /* Expect to never return. */ 1: jmp 1b - -#else - -/* This file assembles the start of the romstage program by the order of the - * includes. Thus, it's extremely important that one pays very careful - * attention to the order of the includes. */ - -#include -#include -#include -#if CONFIG(SSE) -#include -#endif - -/* - * The assembly.inc is generated based on the requirements of the mainboard. - * For example, for ROMCC boards the MAINBOARDDIR/romstage.c would be - * processed by ROMCC and added. In non-ROMCC boards the chipsets' - * cache-as-ram setup files would be here. - */ -#include - -#endif diff --git a/src/arch/x86/c_start.S b/src/arch/x86/c_start.S index bd99c21c91..887243964e 100644 --- a/src/arch/x86/c_start.S +++ b/src/arch/x86/c_start.S @@ -148,7 +148,7 @@ gdtaddr: .data /* This is the gdt for GCC part of coreboot. - * It is different from the gdt in ROMCC/ASM part of coreboot + * It is different from the gdt in ASM part of coreboot * which is defined in entry32.inc * * When the machine is initially started, we use a very simple diff --git a/src/arch/x86/include/arch/acpi.h b/src/arch/x86/include/arch/acpi.h index 479067ffaa..68475c157e 100644 --- a/src/arch/x86/include/arch/acpi.h +++ b/src/arch/x86/include/arch/acpi.h @@ -45,7 +45,7 @@ #define ACPI_TABLE_CREATOR "COREBOOT" /* Must be exactly 8 bytes long! */ #define OEM_ID "COREv4" /* Must be exactly 6 bytes long! */ -#if !defined(__ASSEMBLER__) && !defined(__ACPI__) && !defined(__ROMCC__) +#if !defined(__ASSEMBLER__) && !defined(__ACPI__) #include #include #include diff --git a/src/arch/x86/include/arch/cpu.h b/src/arch/x86/include/arch/cpu.h index 50d636b1f6..c8cf8c76c3 100644 --- a/src/arch/x86/include/arch/cpu.h +++ b/src/arch/x86/include/arch/cpu.h @@ -218,9 +218,6 @@ static inline bool cpu_is_intel(void) return CONFIG(CPU_INTEL_COMMON) || CONFIG(SOC_INTEL_COMMON); } -#ifndef __ROMCC__ -/* romcc does not support anonymous structs. */ - struct device; struct cpu_device_id { @@ -288,13 +285,11 @@ static inline void get_fms(struct cpuinfo_x86 *c, uint32_t tfms) #define asmlinkage __attribute__((regparm(0))) /* - * When not using a romcc bootblock the car_stage_entry() is the symbol - * jumped to for each stage after bootblock using cache-as-ram. + * The car_stage_entry() is the symbol jumped to for each stage + * after bootblock using cache-as-ram. */ asmlinkage void car_stage_entry(void); -#endif - /* * Get processor id using cpuid eax=1 * return value in EAX register diff --git a/src/arch/x86/include/arch/hlt.h b/src/arch/x86/include/arch/hlt.h index 7b18f55657..a3f5c853f3 100644 --- a/src/arch/x86/include/arch/hlt.h +++ b/src/arch/x86/include/arch/hlt.h @@ -14,16 +14,9 @@ #ifndef ARCH_HLT_H #define ARCH_HLT_H -#if defined(__ROMCC__) -static void hlt(void) -{ - __builtin_hlt(); -} -#else static __always_inline void hlt(void) { asm("hlt"); } -#endif #endif /* ARCH_HLT_H */ diff --git a/src/arch/x86/include/arch/io.h b/src/arch/x86/include/arch/io.h index d39bbb3ff4..43cfc1be12 100644 --- a/src/arch/x86/include/arch/io.h +++ b/src/arch/x86/include/arch/io.h @@ -21,39 +21,6 @@ * inb/inw/inl/outb/outw/outl and the "string versions" of the same * (insb/insw/insl/outsb/outsw/outsl). */ -#if defined(__ROMCC__) -static inline void outb(uint8_t value, uint16_t port) -{ - __builtin_outb(value, port); -} - -static inline void outw(uint16_t value, uint16_t port) -{ - __builtin_outw(value, port); -} - -static inline void outl(uint32_t value, uint16_t port) -{ - __builtin_outl(value, port); -} - - -static inline uint8_t inb(uint16_t port) -{ - return __builtin_inb(port); -} - - -static inline uint16_t inw(uint16_t port) -{ - return __builtin_inw(port); -} - -static inline uint32_t inl(uint16_t port) -{ - return __builtin_inl(port); -} -#else static inline void outb(uint8_t value, uint16_t port) { __asm__ __volatile__ ("outb %b0, %w1" : : "a" (value), "Nd" (port)); @@ -89,7 +56,6 @@ static inline uint32_t inl(uint16_t port) __asm__ __volatile__ ("inl %w1, %0" : "=a"(value) : "Nd" (port)); return value; } -#endif /* __ROMCC__ */ static inline void outsb(uint16_t port, const void *addr, unsigned long count) { diff --git a/src/arch/x86/include/arch/mmio.h b/src/arch/x86/include/arch/mmio.h index f271a973eb..efdbe2752b 100644 --- a/src/arch/x86/include/arch/mmio.h +++ b/src/arch/x86/include/arch/mmio.h @@ -34,13 +34,11 @@ static __always_inline uint32_t read32( return *((volatile uint32_t *)(addr)); } -#ifndef __ROMCC__ static __always_inline uint64_t read64( const volatile void *addr) { return *((volatile uint64_t *)(addr)); } -#endif static __always_inline void write8(volatile void *addr, uint8_t value) @@ -60,12 +58,10 @@ static __always_inline void write32(volatile void *addr, *((volatile uint32_t *)(addr)) = value; } -#ifndef __ROMCC__ static __always_inline void write64(volatile void *addr, uint64_t value) { *((volatile uint64_t *)(addr)) = value; } -#endif #endif /* __ARCH_MMIO_H__ */ diff --git a/src/arch/x86/include/arch/pci_mmio_cfg_romcc.h b/src/arch/x86/include/arch/pci_mmio_cfg_romcc.h deleted file mode 100644 index 36a88f1e4d..0000000000 --- a/src/arch/x86/include/arch/pci_mmio_cfg_romcc.h +++ /dev/null @@ -1,70 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef _PCI_MMIO_CFG_ROMCC_H -#define _PCI_MMIO_CFG_ROMCC_H - -#include -#include -#include - - -static __always_inline -uint8_t pci_mmio_read_config8(pci_devfn_t dev, uint16_t reg) -{ - void *addr; - addr = (void *)(uintptr_t)(CONFIG_MMCONF_BASE_ADDRESS | dev | reg); - return read8(addr); -} - -static __always_inline -uint16_t pci_mmio_read_config16(pci_devfn_t dev, uint16_t reg) -{ - void *addr; - addr = (void *)(uintptr_t)(CONFIG_MMCONF_BASE_ADDRESS | dev | (reg & ~1)); - return read16(addr); -} - -static __always_inline -uint32_t pci_mmio_read_config32(pci_devfn_t dev, uint16_t reg) -{ - void *addr; - addr = (void *)(uintptr_t)(CONFIG_MMCONF_BASE_ADDRESS | dev | (reg & ~3)); - return read32(addr); -} - -static __always_inline -void pci_mmio_write_config8(pci_devfn_t dev, uint16_t reg, uint8_t value) -{ - void *addr; - addr = (void *)(uintptr_t)(CONFIG_MMCONF_BASE_ADDRESS | dev | reg); - write8(addr, value); -} - -static __always_inline -void pci_mmio_write_config16(pci_devfn_t dev, uint16_t reg, uint16_t value) -{ - void *addr; - addr = (void *)(uintptr_t)(CONFIG_MMCONF_BASE_ADDRESS | dev | (reg & ~1)); - write16(addr, value); -} - -static __always_inline -void pci_mmio_write_config32(pci_devfn_t dev, uint16_t reg, uint32_t value) -{ - void *addr; - addr = (void *)(uintptr_t)(CONFIG_MMCONF_BASE_ADDRESS | dev | (reg & ~3)); - write32(addr, value); -} - -#endif /* _PCI_MMIO_CFG_ROMCC_H */ diff --git a/src/arch/x86/include/arch/pci_ops.h b/src/arch/x86/include/arch/pci_ops.h index 4278ed0dfd..e706216586 100644 --- a/src/arch/x86/include/arch/pci_ops.h +++ b/src/arch/x86/include/arch/pci_ops.h @@ -15,12 +15,6 @@ #define ARCH_I386_PCI_OPS_H #include - -#if defined(__ROMCC__) -/* Must come before */ -#include -#endif - #include #endif /* ARCH_I386_PCI_OPS_H */ diff --git a/src/commonlib/include/commonlib/cbfs_serialized.h b/src/commonlib/include/commonlib/cbfs_serialized.h index a4708e8124..d3a18c600a 100644 --- a/src/commonlib/include/commonlib/cbfs_serialized.h +++ b/src/commonlib/include/commonlib/cbfs_serialized.h @@ -187,11 +187,6 @@ struct cbfs_file_attr_align { uint32_t alignment; } __packed; -/* - * ROMCC does not understand uint64_t, so we hide future definitions as they are - * unlikely to be ever needed from ROMCC - */ -#ifndef __ROMCC__ /*** Component sub-headers ***/ @@ -236,6 +231,4 @@ struct cbfs_optionrom { uint32_t len; } __packed; -#endif /* __ROMCC__ */ - #endif /* _CBFS_SERIALIZED_H_ */ diff --git a/src/commonlib/include/commonlib/helpers.h b/src/commonlib/include/commonlib/helpers.h index ca3b3c58f9..f07b6c22f1 100644 --- a/src/commonlib/include/commonlib/helpers.h +++ b/src/commonlib/include/commonlib/helpers.h @@ -41,13 +41,10 @@ var_a op var_b ? var_a : var_b; \ }) -#ifdef __ROMCC__ /* romcc doesn't support __builtin_choose_expr() */ -#define __CMP(a, b, op) __CMP_UNSAFE(a, b, op) -#else + #define __CMP(a, b, op) __builtin_choose_expr( \ __builtin_constant_p(a) && __builtin_constant_p(b), \ __CMP_UNSAFE(a, b, op), __CMP_SAFE(a, b, op, __TMPNAME, __TMPNAME)) -#endif #ifndef MIN #define MIN(a, b) __CMP(a, b, <) @@ -108,12 +105,8 @@ #define GHz (1000 * MHz) #ifndef offsetof -#ifdef __ROMCC__ -#define offsetof(TYPE, MEMBER) ((size_t) &((TYPE *)0)->MEMBER) -#else #define offsetof(TYPE, MEMBER) __builtin_offsetof(TYPE, MEMBER) #endif -#endif #define check_member(structure, member, offset) _Static_assert( \ offsetof(struct structure, member) == offset, \ diff --git a/src/console/die.c b/src/console/die.c index 76c456d1fb..e57c4e4bf2 100644 --- a/src/console/die.c +++ b/src/console/die.c @@ -15,8 +15,6 @@ #include #include -#ifndef __ROMCC__ - /* * The method should be overwritten in mainboard directory to signal that a * fatal error had occurred. On boards that do share the same EC and where the @@ -39,4 +37,3 @@ void __noreturn die(const char *fmt, ...) die_notify(); halt(); } -#endif diff --git a/src/console/post.c b/src/console/post.c index 64aa2a5513..8c28ceb672 100644 --- a/src/console/post.c +++ b/src/console/post.c @@ -24,8 +24,6 @@ /* Write POST information */ -/* someday romcc will be gone. */ -#ifndef __ROMCC__ /* Some mainboards have very nice features beyond just a simple display. * They can override this function. */ @@ -33,11 +31,6 @@ void __weak mainboard_post(uint8_t value) { } -#else -/* This just keeps the number of #ifs to a minimum */ -#define mainboard_post(x) -#endif - #if CONFIG(CMOS_POST) DECLARE_SPIN_LOCK(cmos_post_lock) diff --git a/src/cpu/x86/16bit/entry16.inc b/src/cpu/x86/16bit/entry16.inc index e0babd5a5a..40c0e991a6 100644 --- a/src/cpu/x86/16bit/entry16.inc +++ b/src/cpu/x86/16bit/entry16.inc @@ -29,13 +29,10 @@ #include -#if !CONFIG(ROMCC_BOOTBLOCK) || \ - CONFIG(SIPI_VECTOR_IN_ROM) /* Symbol _start16bit must be aligned to 4kB to start AP CPUs with * Startup IPI message without RAM. */ .align 4096 -#endif .code16 .globl _start16bit .type _start16bit, @function diff --git a/src/include/console/console.h b/src/include/console/console.h index 607c96862e..583420cb83 100644 --- a/src/include/console/console.h +++ b/src/include/console/console.h @@ -26,8 +26,6 @@ #define RAM_DEBUG (CONFIG(DEBUG_RAM_SETUP) ? BIOS_DEBUG : BIOS_NEVER) #define RAM_SPEW (CONFIG(DEBUG_RAM_SETUP) ? BIOS_SPEW : BIOS_NEVER) -#ifndef __ROMCC__ - #include void post_code(u8 value); @@ -101,11 +99,4 @@ int do_printk(int msg_level, const char *fmt, ...) int do_vprintk(int msg_level, const char *fmt, va_list args); -#else - -static inline void romcc_printk(void) { } -#define printk(...) romcc_printk() - -#endif /* !__ROMCC__ */ - #endif /* CONSOLE_CONSOLE_H_ */ diff --git a/src/include/console/uart.h b/src/include/console/uart.h index aed67c2c7b..162b1108a9 100644 --- a/src/include/console/uart.h +++ b/src/include/console/uart.h @@ -55,7 +55,6 @@ unsigned char uart_rx_byte(int idx); uintptr_t uart_platform_base(int idx); -#if !defined(__ROMCC__) static inline void *uart_platform_baseptr(int idx) { return (void *)uart_platform_base(idx); @@ -100,6 +99,4 @@ static inline u8 __gdb_rx_byte(void) } #endif -#endif /* __ROMCC__ */ - #endif /* CONSOLE_UART_H */ diff --git a/src/include/cpu/amd/mtrr.h b/src/include/cpu/amd/mtrr.h index edbf7bb2aa..906a7c00f0 100644 --- a/src/include/cpu/amd/mtrr.h +++ b/src/include/cpu/amd/mtrr.h @@ -38,7 +38,7 @@ #define TOP_MEM_MASK 0x007fffff #define TOP_MEM_MASK_KB (TOP_MEM_MASK >> 10) -#if !defined(__ROMCC__) && !defined(__ASSEMBLER__) +#if !defined(__ASSEMBLER__) #include diff --git a/src/include/cpu/x86/cache.h b/src/include/cpu/x86/cache.h index 713ca323a8..0331e27161 100644 --- a/src/include/cpu/x86/cache.h +++ b/src/include/cpu/x86/cache.h @@ -23,28 +23,11 @@ #if !defined(__ASSEMBLER__) -/* - * Need two versions because ROMCC chokes on certain clobbers: - * cache.h:29.71: cache.h:60.24: earlymtrr.c:117.23: romstage.c:144.33: - * 0x1559920 asm Internal compiler error: lhs 1 regcm == 0 - */ - -#if defined(__GNUC__) - static inline void wbinvd(void) { asm volatile ("wbinvd" ::: "memory"); } -#else - -static inline void wbinvd(void) -{ - asm volatile ("wbinvd"); -} - -#endif - static inline void invd(void) { asm volatile("invd" ::: "memory"); diff --git a/src/include/cpu/x86/cr.h b/src/include/cpu/x86/cr.h index 0f14d5451d..0339aa3937 100644 --- a/src/include/cpu/x86/cr.h +++ b/src/include/cpu/x86/cr.h @@ -20,12 +20,7 @@ #include -/* ROMCC apparently chokes certain clobber registers. */ -#if defined(__ROMCC__) -#define COMPILER_BARRIER -#else #define COMPILER_BARRIER "memory" -#endif #ifdef __x86_64__ #define CRx_TYPE uint64_t diff --git a/src/include/cpu/x86/msr.h b/src/include/cpu/x86/msr.h index 2710e7f1fc..63cb8bde28 100644 --- a/src/include/cpu/x86/msr.h +++ b/src/include/cpu/x86/msr.h @@ -81,21 +81,6 @@ #ifndef __ASSEMBLER__ #include -#if defined(__ROMCC__) - -typedef __builtin_msr_t msr_t; - -static msr_t rdmsr(unsigned long index) -{ - return __builtin_rdmsr(index); -} - -static void wrmsr(unsigned long index, msr_t msr) -{ - __builtin_wrmsr(index, msr.lo, msr.hi); -} - -#else typedef struct msr_struct { unsigned int lo; @@ -154,7 +139,6 @@ static __always_inline void wrmsr(unsigned int index, msr_t msr) } #endif /* CONFIG_SOC_SETS_MSRS */ -#endif /* __ROMCC__ */ /* Helpers for interpreting MC[i]_STATUS */ diff --git a/src/include/cpu/x86/mtrr.h b/src/include/cpu/x86/mtrr.h index 29256c8d46..07db3cb606 100644 --- a/src/include/cpu/x86/mtrr.h +++ b/src/include/cpu/x86/mtrr.h @@ -53,7 +53,7 @@ #define MTRR_FIX_4K_F0000 0x26e #define MTRR_FIX_4K_F8000 0x26f -#if !defined(__ASSEMBLER__) && !defined(__ROMCC__) +#if !defined(__ASSEMBLER__) #include #include @@ -140,9 +140,9 @@ static inline unsigned int fls(unsigned int x) "1:" : "=r" (r) : "mr" (x)); return r; } -#endif /* !defined(__ASSEMBLER__) && !defined(__ROMCC__) */ +#endif /* !defined(__ASSEMBLER__) */ -/* Align up/down to next power of 2, suitable for ROMCC and assembler +/* Align up/down to next power of 2, suitable for assembler too. Range of result 256kB to 128MB is good enough here. */ #define _POW2_MASK(x) ((x>>1)|(x>>2)|(x>>3)|(x>>4)|(x>>5)| \ (x>>6)|(x>>7)|(x>>8)|((1<<18)-1)) diff --git a/src/include/cpu/x86/tsc.h b/src/include/cpu/x86/tsc.h index c18f8782f0..6943b93018 100644 --- a/src/include/cpu/x86/tsc.h +++ b/src/include/cpu/x86/tsc.h @@ -28,7 +28,6 @@ static inline tsc_t rdtsc(void) return res; } -#if !defined(__ROMCC__) /* Simple 32- to 64-bit multiplication. Uses 16-bit words to avoid overflow. * This code is used to prevent use of libgcc's umoddi3. */ @@ -42,7 +41,6 @@ static inline void multiply_to_tsc(tsc_t *const tsc, const u32 a, const u32 b) tsc->hi = ((a >> 16) * (b >> 16)) + (tsc->hi >> 16); } -/* Too many registers for ROMCC */ static inline unsigned long long rdtscll(void) { unsigned long long val; @@ -58,7 +56,6 @@ static inline uint64_t tsc_to_uint64(tsc_t tstamp) { return (((uint64_t)tstamp.hi) << 32) + tstamp.lo; } -#endif /* Provided by CPU/chipset code for the TSC rate in MHz. */ unsigned long tsc_freq_mhz(void); diff --git a/src/include/device/device.h b/src/include/device/device.h index abcd0a453a..e391291084 100644 --- a/src/include/device/device.h +++ b/src/include/device/device.h @@ -2,13 +2,6 @@ #define DEVICE_H -/* - * NOTICE: Header is ROMCC tentative. - * This header is incompatible with ROMCC and its inclusion leads to 'odd' - * build failures. - */ -#if !defined(__ROMCC__) - #include #include #include @@ -330,6 +323,4 @@ void scan_smbus(struct device *bus); void scan_generic_bus(struct device *bus); void scan_static_bus(struct device *bus); -#endif /* !defined(__ROMCC__) */ - #endif /* DEVICE_H */ diff --git a/src/include/device/mmio.h b/src/include/device/mmio.h index 4007cff7c3..524284a077 100644 --- a/src/include/device/mmio.h +++ b/src/include/device/mmio.h @@ -37,7 +37,6 @@ #define clrbits32(addr, clear) clrsetbits32(addr, clear, 0) #define clrbits64(addr, clear) clrsetbits64(addr, clear, 0) -#ifndef __ROMCC__ /* * Reads a transfer buffer from 32-bit FIFO registers. fifo_stride is the * distance in bytes between registers (e.g. pass 4 for a normal array of 32-bit @@ -195,6 +194,4 @@ static inline void buffer_to_fifo32(void *buffer, size_t size, void *fifo, #define READ32_BITFIELD(addr, name) \ EXTRACT_BITFIELD(read32(addr), name) -#endif /* !__ROMCC__ */ - #endif /* __DEVICE_MMIO_H__ */ diff --git a/src/include/device/pci_mmio_cfg.h b/src/include/device/pci_mmio_cfg.h index 30945f4c27..aa159705d1 100644 --- a/src/include/device/pci_mmio_cfg.h +++ b/src/include/device/pci_mmio_cfg.h @@ -20,7 +20,6 @@ #include #include -#if !defined(__ROMCC__) /* By not assigning this to CONFIG_MMCONF_BASE_ADDRESS here we * prevent some sub-optimal constant folding. */ @@ -110,8 +109,6 @@ uint32_t *pci_mmio_config32_addr(pci_devfn_t dev, uint16_t reg) return (uint32_t *)&pcicfg(dev)->reg32[reg / sizeof(uint32_t)]; } -#endif /* !defined(__ROMCC__) */ - #if CONFIG(MMCONF_SUPPORT) #if CONFIG_MMCONF_BASE_ADDRESS == 0 diff --git a/src/include/device/pci_ops.h b/src/include/device/pci_ops.h index 9d64f037f6..805c087de7 100644 --- a/src/include/device/pci_ops.h +++ b/src/include/device/pci_ops.h @@ -23,7 +23,6 @@ #include #include -#ifndef __ROMCC__ void __noreturn pcidev_die(void); static __always_inline pci_devfn_t pcidev_bdf(const struct device *dev) @@ -37,7 +36,6 @@ static __always_inline pci_devfn_t pcidev_assert(const struct device *dev) pcidev_die(); return pcidev_bdf(dev); } -#endif #if defined(__SIMPLE_DEVICE__) #define ENV_PCI_SIMPLE_DEVICE 1 @@ -184,7 +182,6 @@ void pci_update_config32(const struct device *dev, u16 reg, u32 mask, u32 or) u16 pci_s_find_next_capability(pci_devfn_t dev, u16 cap, u16 last); u16 pci_s_find_capability(pci_devfn_t dev, u16 cap); -#ifndef __ROMCC__ static __always_inline u16 pci_find_next_capability(const struct device *dev, u16 cap, u16 last) { @@ -196,6 +193,5 @@ u16 pci_find_capability(const struct device *dev, u16 cap) { return pci_s_find_capability(PCI_BDF(dev), cap); } -#endif #endif /* PCI_OPS_H */ diff --git a/src/include/endian.h b/src/include/endian.h index f16f668a18..0f32b7484a 100644 --- a/src/include/endian.h +++ b/src/include/endian.h @@ -79,7 +79,6 @@ #define clrsetbits_le16(addr, clear, set) __clrsetbits(le, 16, addr, clear, set) #define clrsetbits_be16(addr, clear, set) __clrsetbits(be, 16, addr, clear, set) -#ifndef __ROMCC__ /* be16dec/be32dec/be64dec/le16dec/le32dec/le64dec family of functions. */ #define DEFINE_ENDIAN_DEC(endian, width) \ static inline uint##width##_t endian##width##dec(const void *p) \ @@ -169,6 +168,5 @@ static inline uint64_t le64toh(uint64_t little_endian_64bits) { return le64_to_cpu(little_endian_64bits); } -#endif #endif diff --git a/src/include/halt.h b/src/include/halt.h index 117c6c087a..e2aa11cb6f 100644 --- a/src/include/halt.h +++ b/src/include/halt.h @@ -17,14 +17,10 @@ #ifndef __HALT_H__ #define __HALT_H__ -#ifdef __ROMCC__ -#include -#else /** * halt the system reliably */ void __noreturn halt(void); -#endif /* __ROMCC__ */ /* Power off the system. */ void poweroff(void); diff --git a/src/include/lib.h b/src/include/lib.h index 098d62df52..d1bbe93a37 100644 --- a/src/include/lib.h +++ b/src/include/lib.h @@ -57,14 +57,12 @@ void hexdump32(char LEVEL, const void *d, size_t len); */ size_t hexstrtobin(const char *str, uint8_t *buf, size_t len); -#if !defined(__ROMCC__) /* Count Leading Zeroes: clz(0) == 32, clz(0xf) == 28, clz(1 << 31) == 0 */ static inline int clz(u32 x) { return x ? __builtin_clz(x) : sizeof(x) * 8; } /* Integer binary logarithm (rounding down): log2(0) == -1, log2(5) == 2 */ static inline int log2(u32 x) { return sizeof(x) * 8 - clz(x) - 1; } /* Find First Set: __ffs(1) == 0, __ffs(0) == -1, __ffs(1<<31) == 31 */ static inline int __ffs(u32 x) { return log2(x & (u32)(-(s32)x)); } -#endif /* Integer binary logarithm (rounding up): log2_ceil(0) == -1, log2(5) == 3 */ static inline int log2_ceil(u32 x) { return (x == 0) ? -1 : log2(x * 2 - 1); } diff --git a/src/include/stdbool.h b/src/include/stdbool.h index 2eeb70ef5b..d7f9e643ea 100644 --- a/src/include/stdbool.h +++ b/src/include/stdbool.h @@ -5,11 +5,8 @@ #include -#ifdef __ROMCC__ -typedef uint8_t bool; -#else + typedef _Bool bool; -#endif #define true 1 #define false 0 diff --git a/src/include/stddef.h b/src/include/stddef.h index a2c9c50cd2..e3183096a0 100644 --- a/src/include/stddef.h +++ b/src/include/stddef.h @@ -47,12 +47,10 @@ typedef unsigned int wint_t; #define MAYBE_STATIC_BSS #endif -#ifndef __ROMCC__ /* Provide a pointer to address 0 that thwarts any "accessing this is * undefined behaviour and do whatever" trickery in compilers. * Use when you _really_ need to read32(zeroptr) (ie. read address 0). */ extern char zeroptr[]; -#endif #endif /* STDDEF_H */ diff --git a/src/include/stdint.h b/src/include/stdint.h index 67b0b0be08..b534addfe2 100644 --- a/src/include/stdint.h +++ b/src/include/stdint.h @@ -28,17 +28,14 @@ typedef unsigned short uint16_t; typedef signed int int32_t; typedef unsigned int uint32_t; -#ifndef __ROMCC__ typedef signed long long int64_t; typedef unsigned long long uint64_t; -#endif /* Types for 'void *' pointers */ typedef signed long intptr_t; typedef unsigned long uintptr_t; /* Ensure that the widths are all correct */ -#ifndef __ROMCC__ _Static_assert(sizeof(int8_t) == 1, "Size of int8_t is incorrect"); _Static_assert(sizeof(uint8_t) == 1, "Size of uint8_t is incorrect"); @@ -53,13 +50,10 @@ _Static_assert(sizeof(uint64_t) == 8, "Size of uint64_t is incorrect"); _Static_assert(sizeof(intptr_t) == sizeof(void *), "Size of intptr_t is incorrect"); _Static_assert(sizeof(uintptr_t) == sizeof(void *), "Size of uintptr_t is incorrect"); -#endif /* Maximum width integer types */ -#ifndef __ROMCC__ typedef int64_t intmax_t; typedef uint64_t uintmax_t; -#endif /* Convenient typedefs */ typedef int8_t s8; @@ -71,10 +65,8 @@ typedef uint16_t u16; typedef int32_t s32; typedef uint32_t u32; -#ifndef __ROMCC__ typedef int64_t s64; typedef uint64_t u64; -#endif /* Limits of integer types */ #define INT8_MIN ((int8_t)0x80) @@ -89,16 +81,12 @@ typedef uint64_t u64; #define INT32_MAX ((int32_t)0x7FFFFFFF) #define UINT32_MAX ((uint32_t)0xFFFFFFFF) -#ifndef __ROMCC__ #define INT64_MIN ((int64_t)0x8000000000000000) #define INT64_MAX ((int64_t)0x7FFFFFFFFFFFFFFF) #define UINT64_MAX ((uint64_t)0xFFFFFFFFFFFFFFFF) -#endif -#ifndef __ROMCC__ #define INTMAX_MIN INT64_MIN #define INTMAX_MAX INT64_MAX #define UINTMAX_MAX UINT64_MAX -#endif #endif /* STDINT_H */ diff --git a/src/include/string.h b/src/include/string.h index d3f09ff102..bcfc111431 100644 --- a/src/include/string.h +++ b/src/include/string.h @@ -4,9 +4,7 @@ #include #include -#if !defined(__ROMCC__) #include -#endif /* Stringify a token */ #ifndef STRINGIFY @@ -19,10 +17,8 @@ void *memmove(void *dest, const void *src, size_t n); void *memset(void *s, int c, size_t n); int memcmp(const void *s1, const void *s2, size_t n); void *memchr(const void *s, int c, size_t n); -#if !defined(__ROMCC__) int snprintf(char *buf, size_t size, const char *fmt, ...); int vsnprintf(char *buf, size_t size, const char *fmt, va_list args); -#endif char *strdup(const char *s); char *strconcat(const char *s1, const char *s2); size_t strnlen(const char *src, size_t max); diff --git a/src/include/swab.h b/src/include/swab.h index 57fe5a2e53..6a33b3969f 100644 --- a/src/include/swab.h +++ b/src/include/swab.h @@ -21,7 +21,7 @@ #include -#if defined(__ROMCC__) || ENV_ARMV4 +#if ENV_ARMV4 #define swab16(x) \ ((unsigned short)( \ (((unsigned short)(x) & (unsigned short)0x00ffU) << 8) | \ @@ -44,10 +44,10 @@ (((uint64_t)(x) & (uint64_t)0x0000ff0000000000ULL) >> 24) | \ (((uint64_t)(x) & (uint64_t)0x00ff000000000000ULL) >> 40) | \ (((uint64_t)(x) & (uint64_t)0xff00000000000000ULL) >> 56))) -#else /* __ROMCC__ || ENV_ARMV4 */ +#else /* ENV_ARMV4 */ #define swab16(x) ((uint16_t)__builtin_bswap16(x)) #define swab32(x) ((uint32_t)__builtin_bswap32(x)) #define swab64(x) ((uint64_t)__builtin_bswap64(x)) -#endif /* !(__ROMCC__ || ENV_ARMV4) */ +#endif /* !ENV_ARMV4 */ #endif /* _SWAB_H */ diff --git a/src/vendorcode/eltan/security/verified_boot/vboot_check.c b/src/vendorcode/eltan/security/verified_boot/vboot_check.c index bc502c9d53..461a847b71 100644 --- a/src/vendorcode/eltan/security/verified_boot/vboot_check.c +++ b/src/vendorcode/eltan/security/verified_boot/vboot_check.c @@ -276,13 +276,6 @@ void verified_boot_early_check(void) { printk(BIOS_SPEW, "%s: processing early items\n", __func__); - if (CONFIG(ROMCC_BOOTBLOCK) && - CONFIG(VENDORCODE_ELTAN_VBOOT_SIGNED_MANIFEST)) { - printk(BIOS_SPEW, "%s: check the manifest\n", __func__); - if (verified_boot_check_manifest() != 0) - die("invalid manifest"); - } - if (CONFIG(VENDORCODE_ELTAN_MBOOT)) { printk(BIOS_DEBUG, "mb_measure returned 0x%x\n", mb_measure(vboot_platform_is_resuming())); From 494b031eb7e1d6cca38d41a80e96e872c8294d66 Mon Sep 17 00:00:00 2001 From: Arthur Heymans Date: Thu, 28 Nov 2019 16:22:06 +0100 Subject: [PATCH 0740/1242] arch/x86: Drop uses of ROMCC_BOOTBLOCK MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Change-Id: Ia0405fdd448cb31b3c6ca3b3d76e49e9f430bf74 Signed-off-by: Arthur Heymans Reviewed-on: https://review.coreboot.org/c/coreboot/+/37339 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki Reviewed-by: HAOUAS Elyes --- src/arch/x86/Kconfig | 2 -- src/console/Kconfig | 2 +- src/cpu/x86/Kconfig | 1 - src/mainboard/Kconfig | 4 ---- src/security/vboot/Kconfig | 1 - 5 files changed, 1 insertion(+), 9 deletions(-) diff --git a/src/arch/x86/Kconfig b/src/arch/x86/Kconfig index 5713a21d65..a6f9f608a5 100644 --- a/src/arch/x86/Kconfig +++ b/src/arch/x86/Kconfig @@ -21,7 +21,6 @@ config ARCH_X86 config ARCH_BOOTBLOCK_X86_32 bool select ARCH_X86 - select BOOTBLOCK_CUSTOM if ROMCC_BOOTBLOCK config ARCH_VERSTAGE_X86_32 bool @@ -44,7 +43,6 @@ config ARCH_RAMSTAGE_X86_32 config ARCH_BOOTBLOCK_X86_64 bool select ARCH_X86 - select BOOTBLOCK_CUSTOM if ROMCC_BOOTBLOCK config ARCH_VERSTAGE_X86_64 bool diff --git a/src/console/Kconfig b/src/console/Kconfig index 5225d11f50..cc18ec3756 100644 --- a/src/console/Kconfig +++ b/src/console/Kconfig @@ -5,7 +5,7 @@ config NO_BOOTBLOCK_CONSOLE config BOOTBLOCK_CONSOLE bool "Enable early (bootblock) console output." - depends on !ROMCC_BOOTBLOCK && !NO_BOOTBLOCK_CONSOLE + depends on !NO_BOOTBLOCK_CONSOLE default y help Use console during the bootblock if supported diff --git a/src/cpu/x86/Kconfig b/src/cpu/x86/Kconfig index efb5fa96e9..76446a04c0 100644 --- a/src/cpu/x86/Kconfig +++ b/src/cpu/x86/Kconfig @@ -77,7 +77,6 @@ config XIP_ROM_SIZE config SETUP_XIP_CACHE bool - depends on !ROMCC_BOOTBLOCK depends on !NO_XIP_EARLY_STAGES help Select this option to set up an MTRR to cache XIP stages loaded diff --git a/src/mainboard/Kconfig b/src/mainboard/Kconfig index a3895e9dc9..df80e646bb 100644 --- a/src/mainboard/Kconfig +++ b/src/mainboard/Kconfig @@ -1,9 +1,5 @@ comment "Important: Run 'make distclean' before switching boards" -if ROMCC_BOOTBLOCK -comment "Systems with ROMCC bootblocks will be deprecated soon!" -endif - choice prompt "Mainboard vendor" default VENDOR_EMULATION diff --git a/src/security/vboot/Kconfig b/src/security/vboot/Kconfig index a829443098..e03b51dd06 100644 --- a/src/security/vboot/Kconfig +++ b/src/security/vboot/Kconfig @@ -95,7 +95,6 @@ config VBOOT_VBNV_FLASH config VBOOT_STARTS_IN_BOOTBLOCK bool default n - depends on !ROMCC_BOOTBLOCK help Firmware verification happens during the end of or right after the bootblock. This implies that a static VBOOT2_WORK() buffer must be From add0b4712d5cda5edb97122a5e2a74a60f3051d6 Mon Sep 17 00:00:00 2001 From: Elyes HAOUAS Date: Tue, 27 Aug 2019 16:21:15 +0200 Subject: [PATCH 0741/1242] src: Remove unused 'include ' MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Change-Id: Ic25022bdba15219f79cfe172dc2512c3e18bca70 Signed-off-by: Elyes HAOUAS Reviewed-on: https://review.coreboot.org/c/coreboot/+/35124 Reviewed-by: Kyösti Mälkki Tested-by: build bot (Jenkins) --- src/soc/qualcomm/sdm845/aop_load_reset.c | 1 - src/southbridge/intel/ibexpeak/smihandler.c | 1 - 2 files changed, 2 deletions(-) diff --git a/src/soc/qualcomm/sdm845/aop_load_reset.c b/src/soc/qualcomm/sdm845/aop_load_reset.c index c1cf0579cc..317c4febbc 100644 --- a/src/soc/qualcomm/sdm845/aop_load_reset.c +++ b/src/soc/qualcomm/sdm845/aop_load_reset.c @@ -15,7 +15,6 @@ #include #include -#include #include #include #include diff --git a/src/southbridge/intel/ibexpeak/smihandler.c b/src/southbridge/intel/ibexpeak/smihandler.c index 05e7dd2b49..39881889f1 100644 --- a/src/southbridge/intel/ibexpeak/smihandler.c +++ b/src/southbridge/intel/ibexpeak/smihandler.c @@ -22,7 +22,6 @@ #include #include #include -#include #include #include #include From 3c24a40d53a15e33e5a1a0483cfa45ccae2ca992 Mon Sep 17 00:00:00 2001 From: Elyes HAOUAS Date: Thu, 11 Jul 2019 08:41:58 +0200 Subject: [PATCH 0742/1242] src: Remove unneeded 'include ' MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Change-Id: Ibf91c35aa389a91116463616a778212bb386756e Signed-off-by: Elyes HAOUAS Reviewed-on: https://review.coreboot.org/c/coreboot/+/34230 Reviewed-by: Frans Hendriks Reviewed-by: Kyösti Mälkki Tested-by: build bot (Jenkins) --- src/mainboard/getac/p470/mainboard.c | 1 - src/soc/mediatek/common/rtc.c | 1 - src/soc/qualcomm/qcs405/clock.c | 1 - src/soc/qualcomm/qcs405/gpio.c | 1 - src/soc/qualcomm/qcs405/i2c.c | 1 - src/soc/qualcomm/sdm845/usb.c | 1 - 6 files changed, 6 deletions(-) diff --git a/src/mainboard/getac/p470/mainboard.c b/src/mainboard/getac/p470/mainboard.c index 813b1d632e..da903494e3 100644 --- a/src/mainboard/getac/p470/mainboard.c +++ b/src/mainboard/getac/p470/mainboard.c @@ -17,7 +17,6 @@ #include #include #include -#include #include diff --git a/src/soc/mediatek/common/rtc.c b/src/soc/mediatek/common/rtc.c index fe252b5d64..080f334c48 100644 --- a/src/soc/mediatek/common/rtc.c +++ b/src/soc/mediatek/common/rtc.c @@ -13,7 +13,6 @@ * GNU General Public License for more details. */ -#include #include #include #include diff --git a/src/soc/qualcomm/qcs405/clock.c b/src/soc/qualcomm/qcs405/clock.c index da2e8a4603..28f1bc12b9 100644 --- a/src/soc/qualcomm/qcs405/clock.c +++ b/src/soc/qualcomm/qcs405/clock.c @@ -15,7 +15,6 @@ #include #include #include -#include #include #include diff --git a/src/soc/qualcomm/qcs405/gpio.c b/src/soc/qualcomm/qcs405/gpio.c index 19027c32bb..5eb99648d9 100644 --- a/src/soc/qualcomm/qcs405/gpio.c +++ b/src/soc/qualcomm/qcs405/gpio.c @@ -15,7 +15,6 @@ #include #include -#include #include void gpio_configure(gpio_t gpio, uint32_t func, uint32_t pull, diff --git a/src/soc/qualcomm/qcs405/i2c.c b/src/soc/qualcomm/qcs405/i2c.c index 94f8e0d4bb..77c381c33e 100644 --- a/src/soc/qualcomm/qcs405/i2c.c +++ b/src/soc/qualcomm/qcs405/i2c.c @@ -31,7 +31,6 @@ #include #include -#include #include #include #include diff --git a/src/soc/qualcomm/sdm845/usb.c b/src/soc/qualcomm/sdm845/usb.c index 56da28e44d..974fbec8d8 100644 --- a/src/soc/qualcomm/sdm845/usb.c +++ b/src/soc/qualcomm/sdm845/usb.c @@ -15,7 +15,6 @@ #include #include -#include #include #include #include From c00d46353c384016f0d2d4da2df0b2042c4e414b Mon Sep 17 00:00:00 2001 From: Elyes HAOUAS Date: Sat, 12 Oct 2019 18:21:59 +0200 Subject: [PATCH 0743/1242] src: Remove unused include MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Change-Id: Idba48b2182d38dd4945044c79c393c3fd514d720 Signed-off-by: Elyes HAOUAS Reviewed-on: https://review.coreboot.org/c/coreboot/+/35988 Reviewed-by: Frans Hendriks Reviewed-by: Kyösti Mälkki Tested-by: build bot (Jenkins) --- src/include/device/smbus.h | 1 - src/soc/intel/broadwell/smbus.c | 1 - 2 files changed, 2 deletions(-) diff --git a/src/include/device/smbus.h b/src/include/device/smbus.h index 2953b25bbb..863bc80d2a 100644 --- a/src/include/device/smbus.h +++ b/src/include/device/smbus.h @@ -4,7 +4,6 @@ #include #include #include -#include /* Common SMBus bus operations */ struct smbus_bus_operations { diff --git a/src/soc/intel/broadwell/smbus.c b/src/soc/intel/broadwell/smbus.c index 9367f3332e..68d39835ce 100644 --- a/src/soc/intel/broadwell/smbus.c +++ b/src/soc/intel/broadwell/smbus.c @@ -18,7 +18,6 @@ #include #include #include -#include #include #include #include From 43d5f7e8ea26eb15ce3998c88615cd2a754f9c38 Mon Sep 17 00:00:00 2001 From: Elyes HAOUAS Date: Sat, 30 Nov 2019 19:35:39 +0100 Subject: [PATCH 0744/1242] src/soc/rockchip: Remove unused MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Change-Id: Ifdfd37a59273c3647802bc7cb9774e61f90fe441 Signed-off-by: Elyes HAOUAS Reviewed-on: https://review.coreboot.org/c/coreboot/+/37381 Reviewed-by: Kyösti Mälkki Tested-by: build bot (Jenkins) --- src/soc/rockchip/common/gpio.c | 1 - src/soc/rockchip/common/i2c.c | 1 - src/soc/rockchip/common/include/soc/edp.h | 1 - src/soc/rockchip/common/pwm.c | 1 - src/soc/rockchip/common/rk808.c | 1 - src/soc/rockchip/common/vop.c | 1 - src/soc/rockchip/rk3288/clock.c | 1 - src/soc/rockchip/rk3288/display.c | 1 - src/soc/rockchip/rk3288/gpio.c | 1 - src/soc/rockchip/rk3288/hdmi.c | 1 - src/soc/rockchip/rk3288/include/soc/hdmi.h | 1 - src/soc/rockchip/rk3288/soc.c | 1 - src/soc/rockchip/rk3288/tsadc.c | 1 - src/soc/rockchip/rk3399/clock.c | 1 - src/soc/rockchip/rk3399/display.c | 1 - src/soc/rockchip/rk3399/gpio.c | 1 - src/soc/rockchip/rk3399/include/soc/mipi.h | 1 - src/soc/rockchip/rk3399/mipi.c | 1 - src/soc/rockchip/rk3399/saradc.c | 1 - src/soc/rockchip/rk3399/soc.c | 1 - src/soc/rockchip/rk3399/tsadc.c | 1 - 21 files changed, 21 deletions(-) diff --git a/src/soc/rockchip/common/gpio.c b/src/soc/rockchip/common/gpio.c index 16ab385b03..916ef22bad 100644 --- a/src/soc/rockchip/common/gpio.c +++ b/src/soc/rockchip/common/gpio.c @@ -19,7 +19,6 @@ #include #include #include -#include #include static void gpio_set_dir(gpio_t gpio, enum gpio_dir dir) diff --git a/src/soc/rockchip/common/i2c.c b/src/soc/rockchip/common/i2c.c index 953928ed92..391a335475 100644 --- a/src/soc/rockchip/common/i2c.c +++ b/src/soc/rockchip/common/i2c.c @@ -23,7 +23,6 @@ #include #include #include -#include #define RETRY_COUNT 3 /* 100000us = 100ms */ diff --git a/src/soc/rockchip/common/include/soc/edp.h b/src/soc/rockchip/common/include/soc/edp.h index a9ebbc5089..58986d123a 100644 --- a/src/soc/rockchip/common/include/soc/edp.h +++ b/src/soc/rockchip/common/include/soc/edp.h @@ -17,7 +17,6 @@ #define __RK_DP_H #include -#include struct rk_edp_regs { u8 res0[0x10]; diff --git a/src/soc/rockchip/common/pwm.c b/src/soc/rockchip/common/pwm.c index 82fc2596c0..4e6747de4b 100644 --- a/src/soc/rockchip/common/pwm.c +++ b/src/soc/rockchip/common/pwm.c @@ -19,7 +19,6 @@ #include #include #include -#include #include struct pwm_ctl { diff --git a/src/soc/rockchip/common/rk808.c b/src/soc/rockchip/common/rk808.c index 58d910c285..66a085cefe 100644 --- a/src/soc/rockchip/common/rk808.c +++ b/src/soc/rockchip/common/rk808.c @@ -21,7 +21,6 @@ #include #include #include -#include #if CONFIG_PMIC_BUS < 0 #error "PMIC_BUS must be set in mainboard's Kconfig." diff --git a/src/soc/rockchip/common/vop.c b/src/soc/rockchip/common/vop.c index 6e0ce4086c..1e970b1450 100644 --- a/src/soc/rockchip/common/vop.c +++ b/src/soc/rockchip/common/vop.c @@ -14,7 +14,6 @@ */ #include -#include #include #include #include diff --git a/src/soc/rockchip/rk3288/clock.c b/src/soc/rockchip/rk3288/clock.c index f025d30d4e..1c490b47a1 100644 --- a/src/soc/rockchip/rk3288/clock.c +++ b/src/soc/rockchip/rk3288/clock.c @@ -24,7 +24,6 @@ #include #include #include -#include #include struct pll_div { diff --git a/src/soc/rockchip/rk3288/display.c b/src/soc/rockchip/rk3288/display.c index 04a5992392..a66b2d42e5 100644 --- a/src/soc/rockchip/rk3288/display.c +++ b/src/soc/rockchip/rk3288/display.c @@ -20,7 +20,6 @@ #include #include #include -#include #include #include #include diff --git a/src/soc/rockchip/rk3288/gpio.c b/src/soc/rockchip/rk3288/gpio.c index 0f9d85c43a..8eeed888c6 100644 --- a/src/soc/rockchip/rk3288/gpio.c +++ b/src/soc/rockchip/rk3288/gpio.c @@ -18,7 +18,6 @@ #include #include #include -#include struct rockchip_gpio_regs *gpio_port[] = { (struct rockchip_gpio_regs *)0xff750000, diff --git a/src/soc/rockchip/rk3288/hdmi.c b/src/soc/rockchip/rk3288/hdmi.c index 6569d295ea..cd9890bc9b 100644 --- a/src/soc/rockchip/rk3288/hdmi.c +++ b/src/soc/rockchip/rk3288/hdmi.c @@ -24,7 +24,6 @@ #include #include #include -#include #include #include #include diff --git a/src/soc/rockchip/rk3288/include/soc/hdmi.h b/src/soc/rockchip/rk3288/include/soc/hdmi.h index fb20b4a26e..3089949082 100644 --- a/src/soc/rockchip/rk3288/include/soc/hdmi.h +++ b/src/soc/rockchip/rk3288/include/soc/hdmi.h @@ -19,7 +19,6 @@ #define __SOC_HDMI_H__ #include -#include #define HDMI_EDID_BLOCK_SIZE 128 diff --git a/src/soc/rockchip/rk3288/soc.c b/src/soc/rockchip/rk3288/soc.c index bda9553cd7..31c999806f 100644 --- a/src/soc/rockchip/rk3288/soc.c +++ b/src/soc/rockchip/rk3288/soc.c @@ -22,7 +22,6 @@ #include #include #include -#include #include #include "chip.h" diff --git a/src/soc/rockchip/rk3288/tsadc.c b/src/soc/rockchip/rk3288/tsadc.c index e0649754b4..de3d0580ff 100644 --- a/src/soc/rockchip/rk3288/tsadc.c +++ b/src/soc/rockchip/rk3288/tsadc.c @@ -19,7 +19,6 @@ #include #include #include -#include struct rk3288_tsadc_regs { u32 user_con; diff --git a/src/soc/rockchip/rk3399/clock.c b/src/soc/rockchip/rk3399/clock.c index f9c49c33d7..4cd2839547 100644 --- a/src/soc/rockchip/rk3399/clock.c +++ b/src/soc/rockchip/rk3399/clock.c @@ -23,7 +23,6 @@ #include #include #include -#include #include struct pll_div { diff --git a/src/soc/rockchip/rk3399/display.c b/src/soc/rockchip/rk3399/display.c index e2e9f7d49b..9cd4053335 100644 --- a/src/soc/rockchip/rk3399/display.c +++ b/src/soc/rockchip/rk3399/display.c @@ -21,7 +21,6 @@ #include #include #include -#include #include #include #include diff --git a/src/soc/rockchip/rk3399/gpio.c b/src/soc/rockchip/rk3399/gpio.c index 7fe2c1978b..9a01abc038 100644 --- a/src/soc/rockchip/rk3399/gpio.c +++ b/src/soc/rockchip/rk3399/gpio.c @@ -18,7 +18,6 @@ #include #include #include -#include struct rockchip_gpio_regs *gpio_port[] = { (struct rockchip_gpio_regs *)GPIO0_BASE, diff --git a/src/soc/rockchip/rk3399/include/soc/mipi.h b/src/soc/rockchip/rk3399/include/soc/mipi.h index 43ab7b914f..469a052a95 100644 --- a/src/soc/rockchip/rk3399/include/soc/mipi.h +++ b/src/soc/rockchip/rk3399/include/soc/mipi.h @@ -16,7 +16,6 @@ #ifndef __RK_MIPI_H #define __RK_MIPI_H -#include #include struct rk_mipi_regs { diff --git a/src/soc/rockchip/rk3399/mipi.c b/src/soc/rockchip/rk3399/mipi.c index 8b80bd724b..751c8a5e63 100644 --- a/src/soc/rockchip/rk3399/mipi.c +++ b/src/soc/rockchip/rk3399/mipi.c @@ -19,7 +19,6 @@ #include #include #include -#include #include #include #include diff --git a/src/soc/rockchip/rk3399/saradc.c b/src/soc/rockchip/rk3399/saradc.c index 358bb6a7e0..713acc04ad 100644 --- a/src/soc/rockchip/rk3399/saradc.c +++ b/src/soc/rockchip/rk3399/saradc.c @@ -20,7 +20,6 @@ #include #include #include -#include #include struct rk3399_saradc_regs { diff --git a/src/soc/rockchip/rk3399/soc.c b/src/soc/rockchip/rk3399/soc.c index 3f3ff97c7f..807a7bce35 100644 --- a/src/soc/rockchip/rk3399/soc.c +++ b/src/soc/rockchip/rk3399/soc.c @@ -23,7 +23,6 @@ #include #include #include -#include #include void bootmem_platform_add_ranges(void) diff --git a/src/soc/rockchip/rk3399/tsadc.c b/src/soc/rockchip/rk3399/tsadc.c index 78ce1e366e..1cdb355237 100644 --- a/src/soc/rockchip/rk3399/tsadc.c +++ b/src/soc/rockchip/rk3399/tsadc.c @@ -19,7 +19,6 @@ #include #include #include -#include struct rk3399_tsadc_regs { u32 user_con; From 8eeff1e0f462c862435fc512d8e79f8b85dba599 Mon Sep 17 00:00:00 2001 From: Elyes HAOUAS Date: Sat, 30 Nov 2019 19:40:16 +0100 Subject: [PATCH 0745/1242] src/soc/nvidia: Remove unused MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Change-Id: I404d149cd1052fa0aef233bd0e0867524c738477 Signed-off-by: Elyes HAOUAS Reviewed-on: https://review.coreboot.org/c/coreboot/+/37382 Reviewed-by: Kyösti Mälkki Tested-by: build bot (Jenkins) --- src/soc/nvidia/tegra124/clock.c | 1 - src/soc/nvidia/tegra124/display.c | 1 - src/soc/nvidia/tegra124/dma.c | 1 - src/soc/nvidia/tegra124/include/soc/clock.h | 1 - src/soc/nvidia/tegra124/sdram.c | 1 - src/soc/nvidia/tegra124/sdram_lp0.c | 1 - src/soc/nvidia/tegra124/sor.c | 1 - src/soc/nvidia/tegra124/verstage.c | 1 - src/soc/nvidia/tegra210/clock.c | 1 - src/soc/nvidia/tegra210/dma.c | 1 - src/soc/nvidia/tegra210/dsi.c | 1 - src/soc/nvidia/tegra210/include/soc/clock.h | 1 - src/soc/nvidia/tegra210/include/soc/mipi-phy.h | 1 - src/soc/nvidia/tegra210/mipi-phy.c | 1 - src/soc/nvidia/tegra210/sdram.c | 1 - src/soc/nvidia/tegra210/sdram_lp0.c | 1 - src/soc/nvidia/tegra210/sor.c | 1 - 17 files changed, 17 deletions(-) diff --git a/src/soc/nvidia/tegra124/clock.c b/src/soc/nvidia/tegra124/clock.c index 46ac4aca5d..04e7d79fef 100644 --- a/src/soc/nvidia/tegra124/clock.c +++ b/src/soc/nvidia/tegra124/clock.c @@ -25,7 +25,6 @@ #include #include #include -#include #include static struct clk_rst_ctlr *clk_rst = (void *)TEGRA_CLK_RST_BASE; diff --git a/src/soc/nvidia/tegra124/display.c b/src/soc/nvidia/tegra124/display.c index 51f7215c0f..6fa3bdf0be 100644 --- a/src/soc/nvidia/tegra124/display.c +++ b/src/soc/nvidia/tegra124/display.c @@ -26,7 +26,6 @@ #include #include #include -#include #include #include "chip.h" diff --git a/src/soc/nvidia/tegra124/dma.c b/src/soc/nvidia/tegra124/dma.c index 78a8d10e00..23efd4c084 100644 --- a/src/soc/nvidia/tegra124/dma.c +++ b/src/soc/nvidia/tegra124/dma.c @@ -21,7 +21,6 @@ #include #include #include -#include struct apb_dma * const apb_dma = (struct apb_dma *)TEGRA_APB_DMA_BASE; diff --git a/src/soc/nvidia/tegra124/include/soc/clock.h b/src/soc/nvidia/tegra124/include/soc/clock.h index f99e786180..712c479caa 100644 --- a/src/soc/nvidia/tegra124/include/soc/clock.h +++ b/src/soc/nvidia/tegra124/include/soc/clock.h @@ -22,7 +22,6 @@ #include #include #include -#include enum { CLK_L_CPU = 0x1 << 0, diff --git a/src/soc/nvidia/tegra124/sdram.c b/src/soc/nvidia/tegra124/sdram.c index cf529257a7..0057d2a21e 100644 --- a/src/soc/nvidia/tegra124/sdram.c +++ b/src/soc/nvidia/tegra124/sdram.c @@ -22,7 +22,6 @@ #include #include #include -#include #include diff --git a/src/soc/nvidia/tegra124/sdram_lp0.c b/src/soc/nvidia/tegra124/sdram_lp0.c index 731fc6155c..aade07c9b7 100644 --- a/src/soc/nvidia/tegra124/sdram_lp0.c +++ b/src/soc/nvidia/tegra124/sdram_lp0.c @@ -20,7 +20,6 @@ #include #include #include -#include /* * This function reads SDRAM parameters (and a few CLK_RST register values) from diff --git a/src/soc/nvidia/tegra124/sor.c b/src/soc/nvidia/tegra124/sor.c index 9554ce9173..1eac52917d 100644 --- a/src/soc/nvidia/tegra124/sor.c +++ b/src/soc/nvidia/tegra124/sor.c @@ -28,7 +28,6 @@ #include #include #include -#include #include "chip.h" diff --git a/src/soc/nvidia/tegra124/verstage.c b/src/soc/nvidia/tegra124/verstage.c index 7ecf31a84e..6564dcb966 100644 --- a/src/soc/nvidia/tegra124/verstage.c +++ b/src/soc/nvidia/tegra124/verstage.c @@ -20,7 +20,6 @@ #include #include #include -#include #include #include diff --git a/src/soc/nvidia/tegra210/clock.c b/src/soc/nvidia/tegra210/clock.c index 9117654e2a..574691a362 100644 --- a/src/soc/nvidia/tegra210/clock.c +++ b/src/soc/nvidia/tegra210/clock.c @@ -18,7 +18,6 @@ #include #include #include -#include #include #include #include diff --git a/src/soc/nvidia/tegra210/dma.c b/src/soc/nvidia/tegra210/dma.c index 2984abec97..155d348106 100644 --- a/src/soc/nvidia/tegra210/dma.c +++ b/src/soc/nvidia/tegra210/dma.c @@ -21,7 +21,6 @@ #include #include #include -#include struct apb_dma * const apb_dma = (struct apb_dma *)TEGRA_APB_DMA_BASE; diff --git a/src/soc/nvidia/tegra210/dsi.c b/src/soc/nvidia/tegra210/dsi.c index 7d54c9e8ac..72bf50f3fa 100644 --- a/src/soc/nvidia/tegra210/dsi.c +++ b/src/soc/nvidia/tegra210/dsi.c @@ -16,7 +16,6 @@ #include #include #include -#include #include #include #include diff --git a/src/soc/nvidia/tegra210/include/soc/clock.h b/src/soc/nvidia/tegra210/include/soc/clock.h index 8c4530c027..1e49299e80 100644 --- a/src/soc/nvidia/tegra210/include/soc/clock.h +++ b/src/soc/nvidia/tegra210/include/soc/clock.h @@ -22,7 +22,6 @@ #include #include #include -#include enum { CLK_L_CPU = 0x1 << 0, diff --git a/src/soc/nvidia/tegra210/include/soc/mipi-phy.h b/src/soc/nvidia/tegra210/include/soc/mipi-phy.h index 852c5a38af..e9b579718f 100644 --- a/src/soc/nvidia/tegra210/include/soc/mipi-phy.h +++ b/src/soc/nvidia/tegra210/include/soc/mipi-phy.h @@ -15,7 +15,6 @@ #ifndef _TEGRA_MIPI_PHY_H #define _TEGRA_MIPI_PHY_H -#include /* * Macros for calculating the phy timings diff --git a/src/soc/nvidia/tegra210/mipi-phy.c b/src/soc/nvidia/tegra210/mipi-phy.c index 4e56730d3b..72dd57deda 100644 --- a/src/soc/nvidia/tegra210/mipi-phy.c +++ b/src/soc/nvidia/tegra210/mipi-phy.c @@ -13,7 +13,6 @@ * GNU General Public License for more details. */ -#include #include #include #include diff --git a/src/soc/nvidia/tegra210/sdram.c b/src/soc/nvidia/tegra210/sdram.c index ce615476e6..8a7f3d955c 100644 --- a/src/soc/nvidia/tegra210/sdram.c +++ b/src/soc/nvidia/tegra210/sdram.c @@ -23,7 +23,6 @@ #include #include #include -#include #include static void sdram_patch(uintptr_t addr, uint32_t value) diff --git a/src/soc/nvidia/tegra210/sdram_lp0.c b/src/soc/nvidia/tegra210/sdram_lp0.c index 9eaf5f0550..09747ea269 100644 --- a/src/soc/nvidia/tegra210/sdram_lp0.c +++ b/src/soc/nvidia/tegra210/sdram_lp0.c @@ -19,7 +19,6 @@ #include #include #include -#include /* * This function reads SDRAM parameters from the common BCT format and diff --git a/src/soc/nvidia/tegra210/sor.c b/src/soc/nvidia/tegra210/sor.c index 3055b2953e..8caf05053a 100644 --- a/src/soc/nvidia/tegra210/sor.c +++ b/src/soc/nvidia/tegra210/sor.c @@ -18,7 +18,6 @@ #include #include -#include #include #include #include From cbea47c744efce06d5bcf4d22642c9af33e554aa Mon Sep 17 00:00:00 2001 From: Elyes HAOUAS Date: Sat, 30 Nov 2019 19:41:40 +0100 Subject: [PATCH 0746/1242] src/soc/qualcomm: Remove unused MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Change-Id: I0bb44636f9ce6a9f96f5909926b586d0a6cedd9e Signed-off-by: Elyes HAOUAS Reviewed-on: https://review.coreboot.org/c/coreboot/+/37383 Reviewed-by: Kyösti Mälkki Tested-by: build bot (Jenkins) --- src/soc/qualcomm/ipq40xx/i2c.c | 1 - src/soc/qualcomm/ipq40xx/lcc.c | 1 - src/soc/qualcomm/ipq40xx/qup.c | 1 - src/soc/qualcomm/ipq40xx/spi.c | 1 - src/soc/qualcomm/ipq40xx/uart.c | 1 - src/soc/qualcomm/ipq806x/i2c.c | 1 - src/soc/qualcomm/ipq806x/lcc.c | 1 - src/soc/qualcomm/ipq806x/qup.c | 1 - src/soc/qualcomm/ipq806x/uart.c | 1 - src/soc/qualcomm/qcs405/i2c.c | 1 - src/soc/qualcomm/qcs405/qup.c | 1 - src/soc/qualcomm/qcs405/spi.c | 1 - src/soc/qualcomm/qcs405/uart.c | 1 - src/soc/qualcomm/qcs405/usb.c | 1 - src/soc/qualcomm/sdm845/usb.c | 1 - 15 files changed, 15 deletions(-) diff --git a/src/soc/qualcomm/ipq40xx/i2c.c b/src/soc/qualcomm/ipq40xx/i2c.c index 17d772a974..32a6d1c16e 100644 --- a/src/soc/qualcomm/ipq40xx/i2c.c +++ b/src/soc/qualcomm/ipq40xx/i2c.c @@ -31,7 +31,6 @@ #include #include -#include #include #include #include diff --git a/src/soc/qualcomm/ipq40xx/lcc.c b/src/soc/qualcomm/ipq40xx/lcc.c index 392bd9c714..db534a41c5 100644 --- a/src/soc/qualcomm/ipq40xx/lcc.c +++ b/src/soc/qualcomm/ipq40xx/lcc.c @@ -27,7 +27,6 @@ * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ -#include #include #include #include diff --git a/src/soc/qualcomm/ipq40xx/qup.c b/src/soc/qualcomm/ipq40xx/qup.c index 1775c84628..e46e8fd4b0 100644 --- a/src/soc/qualcomm/ipq40xx/qup.c +++ b/src/soc/qualcomm/ipq40xx/qup.c @@ -33,7 +33,6 @@ #include #include #include -#include #include #define TIMEOUT_CNT 100 diff --git a/src/soc/qualcomm/ipq40xx/spi.c b/src/soc/qualcomm/ipq40xx/spi.c index 3b0d63603d..a02ef54ab7 100644 --- a/src/soc/qualcomm/ipq40xx/spi.c +++ b/src/soc/qualcomm/ipq40xx/spi.c @@ -33,7 +33,6 @@ #include #include #include -#include static const struct blsp_spi spi_reg[] = { /* BLSP0 registers for SPI interface */ diff --git a/src/soc/qualcomm/ipq40xx/uart.c b/src/soc/qualcomm/ipq40xx/uart.c index 9548bf0c16..2c4a1b0798 100644 --- a/src/soc/qualcomm/ipq40xx/uart.c +++ b/src/soc/qualcomm/ipq40xx/uart.c @@ -37,7 +37,6 @@ #include #include #include -#include #define FIFO_DATA_SIZE 4 diff --git a/src/soc/qualcomm/ipq806x/i2c.c b/src/soc/qualcomm/ipq806x/i2c.c index e24e76d51d..a94b2aee67 100644 --- a/src/soc/qualcomm/ipq806x/i2c.c +++ b/src/soc/qualcomm/ipq806x/i2c.c @@ -29,7 +29,6 @@ #include #include -#include #include #include #include diff --git a/src/soc/qualcomm/ipq806x/lcc.c b/src/soc/qualcomm/ipq806x/lcc.c index 7d8d7bf4d2..758447d805 100644 --- a/src/soc/qualcomm/ipq806x/lcc.c +++ b/src/soc/qualcomm/ipq806x/lcc.c @@ -27,7 +27,6 @@ * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ -#include #include #include #include diff --git a/src/soc/qualcomm/ipq806x/qup.c b/src/soc/qualcomm/ipq806x/qup.c index dcfc00cb84..dabc1f1410 100644 --- a/src/soc/qualcomm/ipq806x/qup.c +++ b/src/soc/qualcomm/ipq806x/qup.c @@ -31,7 +31,6 @@ #include #include #include -#include #include #define TIMEOUT_CNT 100000 diff --git a/src/soc/qualcomm/ipq806x/uart.c b/src/soc/qualcomm/ipq806x/uart.c index 36084f7806..1b559ceba9 100644 --- a/src/soc/qualcomm/ipq806x/uart.c +++ b/src/soc/qualcomm/ipq806x/uart.c @@ -40,7 +40,6 @@ #include #include #include -#include #define FIFO_DATA_SIZE 4 diff --git a/src/soc/qualcomm/qcs405/i2c.c b/src/soc/qualcomm/qcs405/i2c.c index 77c381c33e..399afa1cca 100644 --- a/src/soc/qualcomm/qcs405/i2c.c +++ b/src/soc/qualcomm/qcs405/i2c.c @@ -32,7 +32,6 @@ #include #include #include -#include #include #include #include diff --git a/src/soc/qualcomm/qcs405/qup.c b/src/soc/qualcomm/qcs405/qup.c index 6e84bcb2ff..29b28620af 100644 --- a/src/soc/qualcomm/qcs405/qup.c +++ b/src/soc/qualcomm/qcs405/qup.c @@ -34,7 +34,6 @@ #include #include #include -#include #include #define TIMEOUT_CNT 100 diff --git a/src/soc/qualcomm/qcs405/spi.c b/src/soc/qualcomm/qcs405/spi.c index f621778f65..e60891c899 100644 --- a/src/soc/qualcomm/qcs405/spi.c +++ b/src/soc/qualcomm/qcs405/spi.c @@ -34,7 +34,6 @@ #include #include #include -#include #include #include diff --git a/src/soc/qualcomm/qcs405/uart.c b/src/soc/qualcomm/qcs405/uart.c index 24045cd388..43a6daab91 100644 --- a/src/soc/qualcomm/qcs405/uart.c +++ b/src/soc/qualcomm/qcs405/uart.c @@ -38,7 +38,6 @@ #include #include #include -#include #include #define FIFO_DATA_SIZE 4 diff --git a/src/soc/qualcomm/qcs405/usb.c b/src/soc/qualcomm/qcs405/usb.c index 7ddfaa231e..b91dc87986 100644 --- a/src/soc/qualcomm/qcs405/usb.c +++ b/src/soc/qualcomm/qcs405/usb.c @@ -14,7 +14,6 @@ */ #include -#include #include #include #include diff --git a/src/soc/qualcomm/sdm845/usb.c b/src/soc/qualcomm/sdm845/usb.c index 974fbec8d8..85b3cbacc5 100644 --- a/src/soc/qualcomm/sdm845/usb.c +++ b/src/soc/qualcomm/sdm845/usb.c @@ -13,7 +13,6 @@ * GNU General Public License for more details. */ -#include #include #include #include From 3f870446a695f8970e59078b0d28a9d42de1f011 Mon Sep 17 00:00:00 2001 From: Elyes HAOUAS Date: Thu, 5 Dec 2019 09:08:47 +0100 Subject: [PATCH 0747/1242] src/arch/arm: Remove unused 'include ' MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Change-Id: I35f3559d68866a734666b3a18038bdae628703c8 Signed-off-by: Elyes HAOUAS Reviewed-on: https://review.coreboot.org/c/coreboot/+/37501 Reviewed-by: Kyösti Mälkki Tested-by: build bot (Jenkins) --- src/arch/arm/eabi_compat.c | 1 - 1 file changed, 1 deletion(-) diff --git a/src/arch/arm/eabi_compat.c b/src/arch/arm/eabi_compat.c index 45f4651a03..b2caf9c377 100644 --- a/src/arch/arm/eabi_compat.c +++ b/src/arch/arm/eabi_compat.c @@ -14,7 +14,6 @@ * Utility functions needed for (some) EABI conformant tool chains. */ -#include #include #include #include From 20a329718e0ef4c3648904b647aa37c23b77272b Mon Sep 17 00:00:00 2001 From: Elyes HAOUAS Date: Sat, 30 Nov 2019 19:49:55 +0100 Subject: [PATCH 0748/1242] mb/biostar: Remove unused MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Change-Id: I03d1af0858952972c92b83375a55dbda87e69f8a Signed-off-by: Elyes HAOUAS Reviewed-on: https://review.coreboot.org/c/coreboot/+/33891 Tested-by: build bot (Jenkins) Reviewed-by: Frans Hendriks Reviewed-by: Kyösti Mälkki --- src/mainboard/biostar/am1ml/BiosCallOuts.c | 1 - src/mainboard/biostar/am1ml/buildOpts.c | 1 - 2 files changed, 2 deletions(-) diff --git a/src/mainboard/biostar/am1ml/BiosCallOuts.c b/src/mainboard/biostar/am1ml/BiosCallOuts.c index 17c25aece6..6181226c30 100644 --- a/src/mainboard/biostar/am1ml/BiosCallOuts.c +++ b/src/mainboard/biostar/am1ml/BiosCallOuts.c @@ -20,7 +20,6 @@ #include #include #include -#include const BIOS_CALLOUT_STRUCT BiosCallouts[] = { diff --git a/src/mainboard/biostar/am1ml/buildOpts.c b/src/mainboard/biostar/am1ml/buildOpts.c index 30c06997e4..74216f0556 100644 --- a/src/mainboard/biostar/am1ml/buildOpts.c +++ b/src/mainboard/biostar/am1ml/buildOpts.c @@ -25,7 +25,6 @@ * */ -#include #include #define INSTALL_FT3_SOCKET_SUPPORT TRUE From 98b0ae65614beda2b01fb0270d34369920f51932 Mon Sep 17 00:00:00 2001 From: Elyes HAOUAS Date: Sat, 30 Nov 2019 19:52:18 +0100 Subject: [PATCH 0749/1242] mb/{gizmosphere,google}: Remove unused MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Change-Id: If99c8ea1aa437f261e8ab3c8a164d01be8bc58e9 Signed-off-by: Elyes HAOUAS Reviewed-on: https://review.coreboot.org/c/coreboot/+/33893 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki --- src/mainboard/gizmosphere/gizmo/BiosCallOuts.c | 1 - src/mainboard/gizmosphere/gizmo/buildOpts.c | 1 - src/mainboard/google/kahlee/variants/baseboard/gpio.c | 1 - src/mainboard/google/slippy/variants/leon/romstage.c | 1 - src/mainboard/google/slippy/variants/peppy/romstage.c | 1 - src/mainboard/google/slippy/variants/wolf/romstage.c | 1 - 6 files changed, 6 deletions(-) diff --git a/src/mainboard/gizmosphere/gizmo/BiosCallOuts.c b/src/mainboard/gizmosphere/gizmo/BiosCallOuts.c index 5fc17185e4..233c40f0ca 100644 --- a/src/mainboard/gizmosphere/gizmo/BiosCallOuts.c +++ b/src/mainboard/gizmosphere/gizmo/BiosCallOuts.c @@ -16,7 +16,6 @@ #include #include #include -#include static AGESA_STATUS board_BeforeDramInit (UINT32 Func, UINTN Data, VOID *ConfigPtr); diff --git a/src/mainboard/gizmosphere/gizmo/buildOpts.c b/src/mainboard/gizmosphere/gizmo/buildOpts.c index b9348080b9..1c72f7cf2d 100644 --- a/src/mainboard/gizmosphere/gizmo/buildOpts.c +++ b/src/mainboard/gizmosphere/gizmo/buildOpts.c @@ -26,7 +26,6 @@ * */ -#include diff --git a/src/mainboard/google/kahlee/variants/baseboard/gpio.c b/src/mainboard/google/kahlee/variants/baseboard/gpio.c index 9db26c70d2..4c2483f1b0 100644 --- a/src/mainboard/google/kahlee/variants/baseboard/gpio.c +++ b/src/mainboard/google/kahlee/variants/baseboard/gpio.c @@ -16,7 +16,6 @@ #include #include #include -#include #include #include diff --git a/src/mainboard/google/slippy/variants/leon/romstage.c b/src/mainboard/google/slippy/variants/leon/romstage.c index 3ef8eec5df..9e9cf73656 100644 --- a/src/mainboard/google/slippy/variants/leon/romstage.c +++ b/src/mainboard/google/slippy/variants/leon/romstage.c @@ -15,7 +15,6 @@ */ #include -#include #include #include #include diff --git a/src/mainboard/google/slippy/variants/peppy/romstage.c b/src/mainboard/google/slippy/variants/peppy/romstage.c index 71eafc2d7a..a6815c8817 100644 --- a/src/mainboard/google/slippy/variants/peppy/romstage.c +++ b/src/mainboard/google/slippy/variants/peppy/romstage.c @@ -15,7 +15,6 @@ */ #include -#include #include #include #include diff --git a/src/mainboard/google/slippy/variants/wolf/romstage.c b/src/mainboard/google/slippy/variants/wolf/romstage.c index 7fcf085455..651d8b1d35 100644 --- a/src/mainboard/google/slippy/variants/wolf/romstage.c +++ b/src/mainboard/google/slippy/variants/wolf/romstage.c @@ -15,7 +15,6 @@ */ #include -#include #include #include #include From 45f05a13edb1dbc62bc179ccc715d52dd78a5d00 Mon Sep 17 00:00:00 2001 From: Elyes HAOUAS Date: Sat, 30 Nov 2019 19:58:20 +0100 Subject: [PATCH 0750/1242] mb/{hp,intel}: Remove unused MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Change-Id: Ib6151ac245870a198afb71909a36a0840480d567 Signed-off-by: Elyes HAOUAS Reviewed-on: https://review.coreboot.org/c/coreboot/+/33906 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki --- src/mainboard/hp/pavilion_m6_1035dx/BiosCallOuts.c | 1 - src/mainboard/hp/pavilion_m6_1035dx/buildOpts.c | 1 - src/mainboard/intel/kblrvp/mainboard.c | 1 - src/mainboard/intel/kunimitsu/mainboard.c | 1 - src/mainboard/intel/strago/gpio.c | 1 - 5 files changed, 5 deletions(-) diff --git a/src/mainboard/hp/pavilion_m6_1035dx/BiosCallOuts.c b/src/mainboard/hp/pavilion_m6_1035dx/BiosCallOuts.c index 2b1ac04159..f36e11efec 100644 --- a/src/mainboard/hp/pavilion_m6_1035dx/BiosCallOuts.c +++ b/src/mainboard/hp/pavilion_m6_1035dx/BiosCallOuts.c @@ -19,7 +19,6 @@ #include #include -#include const BIOS_CALLOUT_STRUCT BiosCallouts[] = { diff --git a/src/mainboard/hp/pavilion_m6_1035dx/buildOpts.c b/src/mainboard/hp/pavilion_m6_1035dx/buildOpts.c index c6d62ed542..e56d513cf2 100644 --- a/src/mainboard/hp/pavilion_m6_1035dx/buildOpts.c +++ b/src/mainboard/hp/pavilion_m6_1035dx/buildOpts.c @@ -27,7 +27,6 @@ #include "mainboard.h" -#include #include diff --git a/src/mainboard/intel/kblrvp/mainboard.c b/src/mainboard/intel/kblrvp/mainboard.c index 78c7ae45fb..d2e8719f33 100644 --- a/src/mainboard/intel/kblrvp/mainboard.c +++ b/src/mainboard/intel/kblrvp/mainboard.c @@ -18,7 +18,6 @@ #include #include #include -#include #include #include #include "ec.h" diff --git a/src/mainboard/intel/kunimitsu/mainboard.c b/src/mainboard/intel/kunimitsu/mainboard.c index 4c93051dea..be2f262d2d 100644 --- a/src/mainboard/intel/kunimitsu/mainboard.c +++ b/src/mainboard/intel/kunimitsu/mainboard.c @@ -19,7 +19,6 @@ #include #include #include -#include #include #include #include "ec.h" diff --git a/src/mainboard/intel/strago/gpio.c b/src/mainboard/intel/strago/gpio.c index ed9ae4b4d1..9acc8a00c5 100644 --- a/src/mainboard/intel/strago/gpio.c +++ b/src/mainboard/intel/strago/gpio.c @@ -16,7 +16,6 @@ #include "irqroute.h" #include -#include #include #include "onboard.h" #include "gpio.h" From 7104cdb37546f5240e5a485874ac98809c08dca8 Mon Sep 17 00:00:00 2001 From: Elyes HAOUAS Date: Sat, 30 Nov 2019 20:03:42 +0100 Subject: [PATCH 0751/1242] mb/{cavium,opencellular,roda,scaleway,ti}: Remove unused MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Change-Id: Iad616e98feaebc6d5ec058fbf438ac2002a6b934 Signed-off-by: Elyes HAOUAS Reviewed-on: https://review.coreboot.org/c/coreboot/+/33903 Reviewed-by: Kyösti Mälkki Tested-by: build bot (Jenkins) --- src/mainboard/cavium/cn8100_sff_evb/romstage.c | 1 - src/mainboard/opencellular/elgon/romstage.c | 1 - src/mainboard/roda/rk886ex/m3885.c | 1 - src/mainboard/roda/rk9/mainboard.c | 1 - src/mainboard/scaleway/tagada/bmcinfo.c | 1 - src/mainboard/ti/beaglebone/leds.c | 1 - 6 files changed, 6 deletions(-) diff --git a/src/mainboard/cavium/cn8100_sff_evb/romstage.c b/src/mainboard/cavium/cn8100_sff_evb/romstage.c index b60b9cdc84..81a41009bc 100644 --- a/src/mainboard/cavium/cn8100_sff_evb/romstage.c +++ b/src/mainboard/cavium/cn8100_sff_evb/romstage.c @@ -18,7 +18,6 @@ #include #include #include -#include #include extern const struct bdk_devicetree_key_value devtree[]; diff --git a/src/mainboard/opencellular/elgon/romstage.c b/src/mainboard/opencellular/elgon/romstage.c index 94c09ecaf5..d907351d94 100644 --- a/src/mainboard/opencellular/elgon/romstage.c +++ b/src/mainboard/opencellular/elgon/romstage.c @@ -19,7 +19,6 @@ #include #include #include -#include #include #include #include diff --git a/src/mainboard/roda/rk886ex/m3885.c b/src/mainboard/roda/rk886ex/m3885.c index 60a4f486a8..d4e90b83cc 100644 --- a/src/mainboard/roda/rk886ex/m3885.c +++ b/src/mainboard/roda/rk886ex/m3885.c @@ -15,7 +15,6 @@ */ #include -#include #include #include #include diff --git a/src/mainboard/roda/rk9/mainboard.c b/src/mainboard/roda/rk9/mainboard.c index 3f72398624..6057901f2c 100644 --- a/src/mainboard/roda/rk9/mainboard.c +++ b/src/mainboard/roda/rk9/mainboard.c @@ -14,7 +14,6 @@ */ #include -#include #include #include #include diff --git a/src/mainboard/scaleway/tagada/bmcinfo.c b/src/mainboard/scaleway/tagada/bmcinfo.c index 93b45397ea..61dac153af 100644 --- a/src/mainboard/scaleway/tagada/bmcinfo.c +++ b/src/mainboard/scaleway/tagada/bmcinfo.c @@ -15,7 +15,6 @@ */ #include -#include #include #include diff --git a/src/mainboard/ti/beaglebone/leds.c b/src/mainboard/ti/beaglebone/leds.c index a4889b92fb..dd1471d06b 100644 --- a/src/mainboard/ti/beaglebone/leds.c +++ b/src/mainboard/ti/beaglebone/leds.c @@ -14,7 +14,6 @@ #include #include -#include #include "leds.h" From b85fe66e391c5982073ddcaa275f8a351d35e5ff Mon Sep 17 00:00:00 2001 From: Elyes HAOUAS Date: Sat, 30 Nov 2019 19:48:02 +0100 Subject: [PATCH 0752/1242] mb/{asrock,asus}: Remove unused MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Change-Id: I14d3579f232b1dcc95b4e0653520686965dbe727 Signed-off-by: Elyes HAOUAS Reviewed-on: https://review.coreboot.org/c/coreboot/+/33889 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki --- src/mainboard/asrock/e350m1/BiosCallOuts.c | 1 - src/mainboard/asrock/e350m1/buildOpts.c | 1 - src/mainboard/asrock/imb-a180/BiosCallOuts.c | 1 - src/mainboard/asrock/imb-a180/buildOpts.c | 1 - src/mainboard/asus/f2a85-m/BiosCallOuts.c | 1 - src/mainboard/asus/f2a85-m/buildOpts.c | 1 - 6 files changed, 6 deletions(-) diff --git a/src/mainboard/asrock/e350m1/BiosCallOuts.c b/src/mainboard/asrock/e350m1/BiosCallOuts.c index 491027ac5d..5d7211c3e6 100644 --- a/src/mainboard/asrock/e350m1/BiosCallOuts.c +++ b/src/mainboard/asrock/e350m1/BiosCallOuts.c @@ -17,7 +17,6 @@ #include #include #include -#include static AGESA_STATUS board_BeforeDramInit (UINT32 Func, UINTN Data, VOID *ConfigPtr); diff --git a/src/mainboard/asrock/e350m1/buildOpts.c b/src/mainboard/asrock/e350m1/buildOpts.c index 14621e0690..0125b5667f 100644 --- a/src/mainboard/asrock/e350m1/buildOpts.c +++ b/src/mainboard/asrock/e350m1/buildOpts.c @@ -25,7 +25,6 @@ * */ -#include #include diff --git a/src/mainboard/asrock/imb-a180/BiosCallOuts.c b/src/mainboard/asrock/imb-a180/BiosCallOuts.c index e05d5c0f72..983f9a83c3 100644 --- a/src/mainboard/asrock/imb-a180/BiosCallOuts.c +++ b/src/mainboard/asrock/imb-a180/BiosCallOuts.c @@ -18,7 +18,6 @@ #include #include #include -#include const BIOS_CALLOUT_STRUCT BiosCallouts[] = { diff --git a/src/mainboard/asrock/imb-a180/buildOpts.c b/src/mainboard/asrock/imb-a180/buildOpts.c index d9d62e27d4..caa5e3bc44 100644 --- a/src/mainboard/asrock/imb-a180/buildOpts.c +++ b/src/mainboard/asrock/imb-a180/buildOpts.c @@ -25,7 +25,6 @@ * */ -#include #include #define INSTALL_FT3_SOCKET_SUPPORT TRUE diff --git a/src/mainboard/asus/f2a85-m/BiosCallOuts.c b/src/mainboard/asus/f2a85-m/BiosCallOuts.c index 9e60ca758a..15ce47e17b 100644 --- a/src/mainboard/asus/f2a85-m/BiosCallOuts.c +++ b/src/mainboard/asus/f2a85-m/BiosCallOuts.c @@ -18,7 +18,6 @@ #include #include -#include const BIOS_CALLOUT_STRUCT BiosCallouts[] = { diff --git a/src/mainboard/asus/f2a85-m/buildOpts.c b/src/mainboard/asus/f2a85-m/buildOpts.c index dc20dc7dd8..8a1391d262 100644 --- a/src/mainboard/asus/f2a85-m/buildOpts.c +++ b/src/mainboard/asus/f2a85-m/buildOpts.c @@ -25,7 +25,6 @@ * */ -#include #include From 4540a990a5e65ac4e3e1354523b09b07e000f8c1 Mon Sep 17 00:00:00 2001 From: Elyes HAOUAS Date: Sat, 30 Nov 2019 19:45:36 +0100 Subject: [PATCH 0753/1242] src/mainboard/amd: Remove unused MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Change-Id: I61982309a4110f4f40193190e91224e909b575a9 Signed-off-by: Elyes HAOUAS Reviewed-on: https://review.coreboot.org/c/coreboot/+/33888 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki --- src/mainboard/amd/gardenia/BiosCallOuts.c | 1 - src/mainboard/amd/gardenia/gpio.c | 1 - src/mainboard/amd/padmelon/gpio.c | 1 - 3 files changed, 3 deletions(-) diff --git a/src/mainboard/amd/gardenia/BiosCallOuts.c b/src/mainboard/amd/gardenia/BiosCallOuts.c index d4fb55aac0..ee923265e9 100644 --- a/src/mainboard/amd/gardenia/BiosCallOuts.c +++ b/src/mainboard/amd/gardenia/BiosCallOuts.c @@ -16,7 +16,6 @@ #include #include #include -#include void platform_FchParams_env(FCH_DATA_BLOCK *FchParams_env) { diff --git a/src/mainboard/amd/gardenia/gpio.c b/src/mainboard/amd/gardenia/gpio.c index 7c5f47b25a..837d031abd 100644 --- a/src/mainboard/amd/gardenia/gpio.c +++ b/src/mainboard/amd/gardenia/gpio.c @@ -14,7 +14,6 @@ */ #include -#include #include #include "gpio.h" diff --git a/src/mainboard/amd/padmelon/gpio.c b/src/mainboard/amd/padmelon/gpio.c index e738618924..df53c4a516 100644 --- a/src/mainboard/amd/padmelon/gpio.c +++ b/src/mainboard/amd/padmelon/gpio.c @@ -16,7 +16,6 @@ #include #include #include -#include #include "gpio.h" /* From e5476db4aa9840d0e5b637212aad1423342b00f9 Mon Sep 17 00:00:00 2001 From: Elyes HAOUAS Date: Sat, 30 Nov 2019 20:01:14 +0100 Subject: [PATCH 0754/1242] mb/{msi,pcengines}: Remove unused MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Change-Id: I282d02d58a5740369371a6f0bbdf7e900e3edc56 Signed-off-by: Elyes HAOUAS Reviewed-on: https://review.coreboot.org/c/coreboot/+/33895 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki --- src/mainboard/msi/ms7721/BiosCallOuts.c | 1 - src/mainboard/msi/ms7721/buildOpts.c | 1 - src/mainboard/pcengines/apu1/BiosCallOuts.c | 1 - src/mainboard/pcengines/apu1/buildOpts.c | 1 - src/mainboard/pcengines/apu2/BiosCallOuts.c | 1 - 5 files changed, 5 deletions(-) diff --git a/src/mainboard/msi/ms7721/BiosCallOuts.c b/src/mainboard/msi/ms7721/BiosCallOuts.c index b3cac1d21e..eb3c43cb13 100644 --- a/src/mainboard/msi/ms7721/BiosCallOuts.c +++ b/src/mainboard/msi/ms7721/BiosCallOuts.c @@ -19,7 +19,6 @@ #include #include -#include const BIOS_CALLOUT_STRUCT BiosCallouts[] = { diff --git a/src/mainboard/msi/ms7721/buildOpts.c b/src/mainboard/msi/ms7721/buildOpts.c index 9e57e39613..2dd223d73d 100644 --- a/src/mainboard/msi/ms7721/buildOpts.c +++ b/src/mainboard/msi/ms7721/buildOpts.c @@ -25,7 +25,6 @@ * */ -#include #include diff --git a/src/mainboard/pcengines/apu1/BiosCallOuts.c b/src/mainboard/pcengines/apu1/BiosCallOuts.c index caaa1f421f..f738aa363d 100644 --- a/src/mainboard/pcengines/apu1/BiosCallOuts.c +++ b/src/mainboard/pcengines/apu1/BiosCallOuts.c @@ -18,7 +18,6 @@ #include #include #include -#include #include "gpio_ftns.h" diff --git a/src/mainboard/pcengines/apu1/buildOpts.c b/src/mainboard/pcengines/apu1/buildOpts.c index 1f73eee802..3c037e524b 100644 --- a/src/mainboard/pcengines/apu1/buildOpts.c +++ b/src/mainboard/pcengines/apu1/buildOpts.c @@ -25,7 +25,6 @@ * */ -#include /* Select the CPU family. */ diff --git a/src/mainboard/pcengines/apu2/BiosCallOuts.c b/src/mainboard/pcengines/apu2/BiosCallOuts.c index 264dd77835..1ae5301267 100644 --- a/src/mainboard/pcengines/apu2/BiosCallOuts.c +++ b/src/mainboard/pcengines/apu2/BiosCallOuts.c @@ -19,7 +19,6 @@ #include #include #include -#include #include "gpio_ftns.h" #include "imc.h" From aa57187f8220734dea52a6155361c1c7f9cadb2d Mon Sep 17 00:00:00 2001 From: Elyes HAOUAS Date: Fri, 13 Dec 2019 08:36:20 +0100 Subject: [PATCH 0755/1242] mb/*/*/early_init.c: Remove unused MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Change-Id: I4cd9d22d2105c270a3d1e8a0be40b594c7c8b226 Signed-off-by: Elyes HAOUAS Reviewed-on: https://review.coreboot.org/c/coreboot/+/37687 Reviewed-by: Kyösti Mälkki Tested-by: build bot (Jenkins) --- src/mainboard/apple/macbookair4_2/early_init.c | 2 -- src/mainboard/asrock/b75pro3-m/early_init.c | 1 - src/mainboard/asus/h61m-cs/early_init.c | 1 - src/mainboard/asus/maximus_iv_gene-z/early_init.c | 1 - src/mainboard/asus/p5gc-mx/early_init.c | 1 - src/mainboard/asus/p8h61-m_lx/early_init.c | 1 - src/mainboard/asus/p8h61-m_pro/early_init.c | 1 - src/mainboard/asus/p8z77-m_pro/early_init.c | 1 - src/mainboard/compulab/intense_pc/early_init.c | 1 - src/mainboard/foxconn/d41s/early_init.c | 1 - src/mainboard/gigabyte/ga-b75m-d3h/early_init.c | 1 - src/mainboard/gigabyte/ga-h61m-s2pv/early_init.c | 1 - src/mainboard/google/butterfly/early_init.c | 2 -- src/mainboard/google/parrot/early_init.c | 2 -- src/mainboard/google/stout/early_init.c | 2 -- src/mainboard/hp/2570p/early_init.c | 1 - src/mainboard/hp/2760p/early_init.c | 1 - src/mainboard/hp/8460p/early_init.c | 1 - src/mainboard/hp/8470p/early_init.c | 1 - src/mainboard/hp/8770w/early_init.c | 1 - src/mainboard/hp/compaq_8200_elite_sff/early_init.c | 2 -- src/mainboard/hp/folio_9470m/early_init.c | 1 - src/mainboard/hp/revolve_810_g1/early_init.c | 1 - src/mainboard/hp/z220_sff_workstation/early_init.c | 2 -- src/mainboard/intel/dcp847ske/early_southbridge.c | 2 -- src/mainboard/intel/emeraldlake2/early_init.c | 2 -- src/mainboard/lenovo/l520/early_init.c | 2 -- src/mainboard/lenovo/x131e/early_init.c | 2 -- src/mainboard/lenovo/x1_carbon_gen1/early_init.c | 2 -- src/mainboard/lenovo/x220/early_init.c | 2 -- src/mainboard/lenovo/x230/early_init.c | 2 -- src/mainboard/roda/rv11/variants/rv11/early_init.c | 1 - src/mainboard/roda/rv11/variants/rw11/early_init.c | 1 - src/mainboard/samsung/lumpy/early_init.c | 2 -- src/mainboard/samsung/stumpy/early_init.c | 2 -- 35 files changed, 50 deletions(-) diff --git a/src/mainboard/apple/macbookair4_2/early_init.c b/src/mainboard/apple/macbookair4_2/early_init.c index 860d9d46dd..29a2977444 100644 --- a/src/mainboard/apple/macbookair4_2/early_init.c +++ b/src/mainboard/apple/macbookair4_2/early_init.c @@ -13,8 +13,6 @@ #include #include -#include -#include #include #include #include diff --git a/src/mainboard/asrock/b75pro3-m/early_init.c b/src/mainboard/asrock/b75pro3-m/early_init.c index 296c2de0e7..8fed7994ae 100644 --- a/src/mainboard/asrock/b75pro3-m/early_init.c +++ b/src/mainboard/asrock/b75pro3-m/early_init.c @@ -15,7 +15,6 @@ */ #include -#include #include #include #include diff --git a/src/mainboard/asus/h61m-cs/early_init.c b/src/mainboard/asus/h61m-cs/early_init.c index 2720e7a676..726507e0f8 100644 --- a/src/mainboard/asus/h61m-cs/early_init.c +++ b/src/mainboard/asus/h61m-cs/early_init.c @@ -17,7 +17,6 @@ #include #include -#include #include #include #include diff --git a/src/mainboard/asus/maximus_iv_gene-z/early_init.c b/src/mainboard/asus/maximus_iv_gene-z/early_init.c index 4b4fbbe483..2c8b5d9280 100644 --- a/src/mainboard/asus/maximus_iv_gene-z/early_init.c +++ b/src/mainboard/asus/maximus_iv_gene-z/early_init.c @@ -16,7 +16,6 @@ #include #include -#include #include #include #include diff --git a/src/mainboard/asus/p5gc-mx/early_init.c b/src/mainboard/asus/p5gc-mx/early_init.c index 988d2328f6..2761016c45 100644 --- a/src/mainboard/asus/p5gc-mx/early_init.c +++ b/src/mainboard/asus/p5gc-mx/early_init.c @@ -19,7 +19,6 @@ #include #include #include -#include #include #include #include diff --git a/src/mainboard/asus/p8h61-m_lx/early_init.c b/src/mainboard/asus/p8h61-m_lx/early_init.c index a2fc02e2ce..e38e8822e4 100644 --- a/src/mainboard/asus/p8h61-m_lx/early_init.c +++ b/src/mainboard/asus/p8h61-m_lx/early_init.c @@ -15,7 +15,6 @@ */ #include -#include #include #include #include diff --git a/src/mainboard/asus/p8h61-m_pro/early_init.c b/src/mainboard/asus/p8h61-m_pro/early_init.c index df00e6dab1..27045bf594 100644 --- a/src/mainboard/asus/p8h61-m_pro/early_init.c +++ b/src/mainboard/asus/p8h61-m_pro/early_init.c @@ -14,7 +14,6 @@ */ #include -#include #include #include #include diff --git a/src/mainboard/asus/p8z77-m_pro/early_init.c b/src/mainboard/asus/p8z77-m_pro/early_init.c index ce479a8609..e60f2f3037 100644 --- a/src/mainboard/asus/p8z77-m_pro/early_init.c +++ b/src/mainboard/asus/p8z77-m_pro/early_init.c @@ -14,7 +14,6 @@ * GNU General Public License for more details. */ #include -#include #include #include #include diff --git a/src/mainboard/compulab/intense_pc/early_init.c b/src/mainboard/compulab/intense_pc/early_init.c index cb5f4454b5..7078199f7e 100644 --- a/src/mainboard/compulab/intense_pc/early_init.c +++ b/src/mainboard/compulab/intense_pc/early_init.c @@ -16,7 +16,6 @@ #include #include #include -#include #include #include #include diff --git a/src/mainboard/foxconn/d41s/early_init.c b/src/mainboard/foxconn/d41s/early_init.c index ab1dae14ca..ea3f6a9ca7 100644 --- a/src/mainboard/foxconn/d41s/early_init.c +++ b/src/mainboard/foxconn/d41s/early_init.c @@ -16,7 +16,6 @@ */ #include -#include #include #include #include diff --git a/src/mainboard/gigabyte/ga-b75m-d3h/early_init.c b/src/mainboard/gigabyte/ga-b75m-d3h/early_init.c index 265e5114bc..c370f9705f 100644 --- a/src/mainboard/gigabyte/ga-b75m-d3h/early_init.c +++ b/src/mainboard/gigabyte/ga-b75m-d3h/early_init.c @@ -14,7 +14,6 @@ */ #include -#include #include #include #include diff --git a/src/mainboard/gigabyte/ga-h61m-s2pv/early_init.c b/src/mainboard/gigabyte/ga-h61m-s2pv/early_init.c index 4157b09097..ea15d56488 100644 --- a/src/mainboard/gigabyte/ga-h61m-s2pv/early_init.c +++ b/src/mainboard/gigabyte/ga-h61m-s2pv/early_init.c @@ -14,7 +14,6 @@ */ #include -#include #include #include #include diff --git a/src/mainboard/google/butterfly/early_init.c b/src/mainboard/google/butterfly/early_init.c index 4980fa8dfb..13819f1b90 100644 --- a/src/mainboard/google/butterfly/early_init.c +++ b/src/mainboard/google/butterfly/early_init.c @@ -15,8 +15,6 @@ */ #include -#include -#include #include #include #include diff --git a/src/mainboard/google/parrot/early_init.c b/src/mainboard/google/parrot/early_init.c index 74c5c8694f..01c452637d 100644 --- a/src/mainboard/google/parrot/early_init.c +++ b/src/mainboard/google/parrot/early_init.c @@ -15,8 +15,6 @@ */ #include -#include -#include #include #include #include diff --git a/src/mainboard/google/stout/early_init.c b/src/mainboard/google/stout/early_init.c index 754bec60bb..07c19c5ae0 100644 --- a/src/mainboard/google/stout/early_init.c +++ b/src/mainboard/google/stout/early_init.c @@ -15,8 +15,6 @@ */ #include -#include -#include #include #include #include diff --git a/src/mainboard/hp/2570p/early_init.c b/src/mainboard/hp/2570p/early_init.c index 226367a569..b72dd304a4 100644 --- a/src/mainboard/hp/2570p/early_init.c +++ b/src/mainboard/hp/2570p/early_init.c @@ -15,7 +15,6 @@ */ #include -#include #include #include #include diff --git a/src/mainboard/hp/2760p/early_init.c b/src/mainboard/hp/2760p/early_init.c index 98806de9f4..b33216b620 100644 --- a/src/mainboard/hp/2760p/early_init.c +++ b/src/mainboard/hp/2760p/early_init.c @@ -14,7 +14,6 @@ */ #include -#include #include #include #include diff --git a/src/mainboard/hp/8460p/early_init.c b/src/mainboard/hp/8460p/early_init.c index 9c2a4b1139..1ff0f6ef15 100644 --- a/src/mainboard/hp/8460p/early_init.c +++ b/src/mainboard/hp/8460p/early_init.c @@ -15,7 +15,6 @@ */ #include -#include #include #include #include diff --git a/src/mainboard/hp/8470p/early_init.c b/src/mainboard/hp/8470p/early_init.c index 8dbe15815d..51b0b4dcbb 100644 --- a/src/mainboard/hp/8470p/early_init.c +++ b/src/mainboard/hp/8470p/early_init.c @@ -14,7 +14,6 @@ */ #include -#include #include #include #include diff --git a/src/mainboard/hp/8770w/early_init.c b/src/mainboard/hp/8770w/early_init.c index 3bd2ed7f51..6690196894 100644 --- a/src/mainboard/hp/8770w/early_init.c +++ b/src/mainboard/hp/8770w/early_init.c @@ -15,7 +15,6 @@ */ #include -#include #include #include #include diff --git a/src/mainboard/hp/compaq_8200_elite_sff/early_init.c b/src/mainboard/hp/compaq_8200_elite_sff/early_init.c index 882a604899..c0139eb4b9 100644 --- a/src/mainboard/hp/compaq_8200_elite_sff/early_init.c +++ b/src/mainboard/hp/compaq_8200_elite_sff/early_init.c @@ -18,8 +18,6 @@ #include #include -#include -#include #include #include #include diff --git a/src/mainboard/hp/folio_9470m/early_init.c b/src/mainboard/hp/folio_9470m/early_init.c index e5a1892023..ba507cc249 100644 --- a/src/mainboard/hp/folio_9470m/early_init.c +++ b/src/mainboard/hp/folio_9470m/early_init.c @@ -16,7 +16,6 @@ */ #include -#include #include #include #include diff --git a/src/mainboard/hp/revolve_810_g1/early_init.c b/src/mainboard/hp/revolve_810_g1/early_init.c index 1245201963..29be074db1 100644 --- a/src/mainboard/hp/revolve_810_g1/early_init.c +++ b/src/mainboard/hp/revolve_810_g1/early_init.c @@ -19,7 +19,6 @@ #include #include #include -#include #include #include #include diff --git a/src/mainboard/hp/z220_sff_workstation/early_init.c b/src/mainboard/hp/z220_sff_workstation/early_init.c index fd70690079..d0ea1affed 100644 --- a/src/mainboard/hp/z220_sff_workstation/early_init.c +++ b/src/mainboard/hp/z220_sff_workstation/early_init.c @@ -18,8 +18,6 @@ #include #include -#include -#include #include #include #include diff --git a/src/mainboard/intel/dcp847ske/early_southbridge.c b/src/mainboard/intel/dcp847ske/early_southbridge.c index 9cdcd5dec2..5610301fb3 100644 --- a/src/mainboard/intel/dcp847ske/early_southbridge.c +++ b/src/mainboard/intel/dcp847ske/early_southbridge.c @@ -19,8 +19,6 @@ #include #include #include -#include -#include #include #include #include diff --git a/src/mainboard/intel/emeraldlake2/early_init.c b/src/mainboard/intel/emeraldlake2/early_init.c index 7aabf7c1ec..2d97c8599c 100644 --- a/src/mainboard/intel/emeraldlake2/early_init.c +++ b/src/mainboard/intel/emeraldlake2/early_init.c @@ -17,8 +17,6 @@ #include #include #include -#include -#include #include #include #include diff --git a/src/mainboard/lenovo/l520/early_init.c b/src/mainboard/lenovo/l520/early_init.c index d63a667737..2d1f8b5c8f 100644 --- a/src/mainboard/lenovo/l520/early_init.c +++ b/src/mainboard/lenovo/l520/early_init.c @@ -15,8 +15,6 @@ * GNU General Public License for more details. */ -#include -#include #include #include #include diff --git a/src/mainboard/lenovo/x131e/early_init.c b/src/mainboard/lenovo/x131e/early_init.c index fe9fec0cb6..49ee92c37c 100644 --- a/src/mainboard/lenovo/x131e/early_init.c +++ b/src/mainboard/lenovo/x131e/early_init.c @@ -15,8 +15,6 @@ * GNU General Public License for more details. */ -#include -#include #include #include diff --git a/src/mainboard/lenovo/x1_carbon_gen1/early_init.c b/src/mainboard/lenovo/x1_carbon_gen1/early_init.c index c65b45482e..859148abc2 100644 --- a/src/mainboard/lenovo/x1_carbon_gen1/early_init.c +++ b/src/mainboard/lenovo/x1_carbon_gen1/early_init.c @@ -18,8 +18,6 @@ #include #include -#include -#include #include #include #include diff --git a/src/mainboard/lenovo/x220/early_init.c b/src/mainboard/lenovo/x220/early_init.c index 7a29d1840b..3429c1b9bf 100644 --- a/src/mainboard/lenovo/x220/early_init.c +++ b/src/mainboard/lenovo/x220/early_init.c @@ -16,8 +16,6 @@ */ #include -#include -#include #include #include #include diff --git a/src/mainboard/lenovo/x230/early_init.c b/src/mainboard/lenovo/x230/early_init.c index a6853a1d74..70240a7832 100644 --- a/src/mainboard/lenovo/x230/early_init.c +++ b/src/mainboard/lenovo/x230/early_init.c @@ -16,8 +16,6 @@ */ #include -#include -#include #include #include #include diff --git a/src/mainboard/roda/rv11/variants/rv11/early_init.c b/src/mainboard/roda/rv11/variants/rv11/early_init.c index 5081c005aa..80d8028b94 100644 --- a/src/mainboard/roda/rv11/variants/rv11/early_init.c +++ b/src/mainboard/roda/rv11/variants/rv11/early_init.c @@ -15,7 +15,6 @@ #include #include -#include #include #include #include diff --git a/src/mainboard/roda/rv11/variants/rw11/early_init.c b/src/mainboard/roda/rv11/variants/rw11/early_init.c index f3865fc359..b64facae1b 100644 --- a/src/mainboard/roda/rv11/variants/rw11/early_init.c +++ b/src/mainboard/roda/rv11/variants/rw11/early_init.c @@ -16,7 +16,6 @@ #include #include #include -#include #include #include #include diff --git a/src/mainboard/samsung/lumpy/early_init.c b/src/mainboard/samsung/lumpy/early_init.c index 28cd5c336e..33802537ab 100644 --- a/src/mainboard/samsung/lumpy/early_init.c +++ b/src/mainboard/samsung/lumpy/early_init.c @@ -18,8 +18,6 @@ #include #include #include -#include -#include #include #include #include diff --git a/src/mainboard/samsung/stumpy/early_init.c b/src/mainboard/samsung/stumpy/early_init.c index 157fdf18e4..d7f9b907be 100644 --- a/src/mainboard/samsung/stumpy/early_init.c +++ b/src/mainboard/samsung/stumpy/early_init.c @@ -16,8 +16,6 @@ #include #include -#include -#include #include #include #include From 4b463c71c04684476de83673182d8830c04efc4c Mon Sep 17 00:00:00 2001 From: Elyes HAOUAS Date: Fri, 13 Dec 2019 09:05:43 +0100 Subject: [PATCH 0756/1242] mb/*/{BiosCallOuts,mainboard,romstage}.c: Remove unused MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Change-Id: I4dcdcb734e20830ac97d4a826de61017afc6ee67 Signed-off-by: Elyes HAOUAS Reviewed-on: https://review.coreboot.org/c/coreboot/+/37688 Tested-by: build bot (Jenkins) Reviewed-by: Frans Hendriks Reviewed-by: Kyösti Mälkki --- src/mainboard/apple/macbook21/mainboard.c | 1 - src/mainboard/asus/p2b-ds/romstage.c | 1 - src/mainboard/asus/p2b-ls/romstage.c | 1 - src/mainboard/asus/p2b/romstage.c | 1 - src/mainboard/asus/p3b-f/romstage.c | 1 - src/mainboard/getac/p470/mainboard.c | 1 - src/mainboard/gizmosphere/gizmo/mainboard.c | 1 - src/mainboard/google/beltino/mainboard.c | 1 - src/mainboard/google/butterfly/mainboard.c | 1 - src/mainboard/google/link/early_init.c | 1 - src/mainboard/google/link/mainboard.c | 1 - src/mainboard/google/parrot/mainboard.c | 1 - src/mainboard/google/rambi/mainboard.c | 1 - src/mainboard/google/slippy/mainboard.c | 1 - src/mainboard/google/stout/mainboard.c | 1 - src/mainboard/intel/baskingridge/mainboard.c | 1 - src/mainboard/intel/d510mo/mainboard.c | 1 - src/mainboard/intel/emeraldlake2/mainboard.c | 1 - src/mainboard/intel/wtm2/mainboard.c | 1 - src/mainboard/kontron/986lcd-m/mainboard.c | 1 - src/mainboard/lenovo/s230u/early_init.c | 1 - src/mainboard/lenovo/t430s/variants/t431s/romstage.c | 1 - src/mainboard/lenovo/t60/mainboard.c | 1 - src/mainboard/lenovo/x201/mainboard.c | 1 - src/mainboard/lenovo/x201/romstage.c | 1 - src/mainboard/packardbell/ms2290/mainboard.c | 2 -- src/mainboard/packardbell/ms2290/romstage.c | 1 - src/mainboard/samsung/lumpy/mainboard.c | 1 - src/mainboard/supermicro/x10slm-f/mainboard.c | 1 - 29 files changed, 30 deletions(-) diff --git a/src/mainboard/apple/macbook21/mainboard.c b/src/mainboard/apple/macbook21/mainboard.c index 0423837736..6c649e0f81 100644 --- a/src/mainboard/apple/macbook21/mainboard.c +++ b/src/mainboard/apple/macbook21/mainboard.c @@ -16,7 +16,6 @@ */ #include -#include #include #include #include diff --git a/src/mainboard/asus/p2b-ds/romstage.c b/src/mainboard/asus/p2b-ds/romstage.c index 5b3a30b4f9..038e5edfaf 100644 --- a/src/mainboard/asus/p2b-ds/romstage.c +++ b/src/mainboard/asus/p2b-ds/romstage.c @@ -14,7 +14,6 @@ * GNU General Public License for more details. */ -#include #include #include #include diff --git a/src/mainboard/asus/p2b-ls/romstage.c b/src/mainboard/asus/p2b-ls/romstage.c index f933c772d2..a4f1671806 100644 --- a/src/mainboard/asus/p2b-ls/romstage.c +++ b/src/mainboard/asus/p2b-ls/romstage.c @@ -14,7 +14,6 @@ * GNU General Public License for more details. */ -#include #include #include #include diff --git a/src/mainboard/asus/p2b/romstage.c b/src/mainboard/asus/p2b/romstage.c index 1d7c928f17..805fc94152 100644 --- a/src/mainboard/asus/p2b/romstage.c +++ b/src/mainboard/asus/p2b/romstage.c @@ -14,7 +14,6 @@ * GNU General Public License for more details. */ -#include #include #include #include diff --git a/src/mainboard/asus/p3b-f/romstage.c b/src/mainboard/asus/p3b-f/romstage.c index 8fc135d1c8..e9630bfdb0 100644 --- a/src/mainboard/asus/p3b-f/romstage.c +++ b/src/mainboard/asus/p3b-f/romstage.c @@ -15,7 +15,6 @@ */ #include -#include #include #include #include diff --git a/src/mainboard/getac/p470/mainboard.c b/src/mainboard/getac/p470/mainboard.c index da903494e3..c20da65981 100644 --- a/src/mainboard/getac/p470/mainboard.c +++ b/src/mainboard/getac/p470/mainboard.c @@ -15,7 +15,6 @@ */ #include -#include #include #include diff --git a/src/mainboard/gizmosphere/gizmo/mainboard.c b/src/mainboard/gizmosphere/gizmo/mainboard.c index 8196922571..b65f56b074 100644 --- a/src/mainboard/gizmosphere/gizmo/mainboard.c +++ b/src/mainboard/gizmosphere/gizmo/mainboard.c @@ -18,7 +18,6 @@ #include #include #include -#include #include #include diff --git a/src/mainboard/google/beltino/mainboard.c b/src/mainboard/google/beltino/mainboard.c index e6cc01f01e..bbac6ecb48 100644 --- a/src/mainboard/google/beltino/mainboard.c +++ b/src/mainboard/google/beltino/mainboard.c @@ -18,7 +18,6 @@ #include #include #include -#include #include #include diff --git a/src/mainboard/google/butterfly/mainboard.c b/src/mainboard/google/butterfly/mainboard.c index b5f96b4145..b52351baa4 100644 --- a/src/mainboard/google/butterfly/mainboard.c +++ b/src/mainboard/google/butterfly/mainboard.c @@ -17,7 +17,6 @@ #include #include #include -#include #include #include #include diff --git a/src/mainboard/google/link/early_init.c b/src/mainboard/google/link/early_init.c index 8c58054463..19cd295948 100644 --- a/src/mainboard/google/link/early_init.c +++ b/src/mainboard/google/link/early_init.c @@ -18,7 +18,6 @@ #include #include #include -#include #include #include #include diff --git a/src/mainboard/google/link/mainboard.c b/src/mainboard/google/link/mainboard.c index a91930bd7f..21274b345f 100644 --- a/src/mainboard/google/link/mainboard.c +++ b/src/mainboard/google/link/mainboard.c @@ -16,7 +16,6 @@ #include #include -#include #include #include #if CONFIG(VGA_ROM_RUN) diff --git a/src/mainboard/google/parrot/mainboard.c b/src/mainboard/google/parrot/mainboard.c index 361215a1bd..5f47c05fa2 100644 --- a/src/mainboard/google/parrot/mainboard.c +++ b/src/mainboard/google/parrot/mainboard.c @@ -16,7 +16,6 @@ #include #include -#include #include #include #include diff --git a/src/mainboard/google/rambi/mainboard.c b/src/mainboard/google/rambi/mainboard.c index 64dc99f005..d4e38d0532 100644 --- a/src/mainboard/google/rambi/mainboard.c +++ b/src/mainboard/google/rambi/mainboard.c @@ -16,7 +16,6 @@ #include #include -#include #include #if CONFIG(VGA_ROM_RUN) #include diff --git a/src/mainboard/google/slippy/mainboard.c b/src/mainboard/google/slippy/mainboard.c index 4c50ea65a6..5a1af73a79 100644 --- a/src/mainboard/google/slippy/mainboard.c +++ b/src/mainboard/google/slippy/mainboard.c @@ -17,7 +17,6 @@ #include #include #include -#include #include #include #include diff --git a/src/mainboard/google/stout/mainboard.c b/src/mainboard/google/stout/mainboard.c index 782546a54d..2d4086a230 100644 --- a/src/mainboard/google/stout/mainboard.c +++ b/src/mainboard/google/stout/mainboard.c @@ -16,7 +16,6 @@ #include #include -#include #include #include #include diff --git a/src/mainboard/intel/baskingridge/mainboard.c b/src/mainboard/intel/baskingridge/mainboard.c index 37af13f8da..ca93d31f7d 100644 --- a/src/mainboard/intel/baskingridge/mainboard.c +++ b/src/mainboard/intel/baskingridge/mainboard.c @@ -16,7 +16,6 @@ #include #include -#include #include #include #include diff --git a/src/mainboard/intel/d510mo/mainboard.c b/src/mainboard/intel/d510mo/mainboard.c index cac5064704..f90ee89cea 100644 --- a/src/mainboard/intel/d510mo/mainboard.c +++ b/src/mainboard/intel/d510mo/mainboard.c @@ -14,7 +14,6 @@ */ #include -#include #include #include diff --git a/src/mainboard/intel/emeraldlake2/mainboard.c b/src/mainboard/intel/emeraldlake2/mainboard.c index 210588c93c..2f09a7850c 100644 --- a/src/mainboard/intel/emeraldlake2/mainboard.c +++ b/src/mainboard/intel/emeraldlake2/mainboard.c @@ -16,7 +16,6 @@ #include #include -#include #include #include #include diff --git a/src/mainboard/intel/wtm2/mainboard.c b/src/mainboard/intel/wtm2/mainboard.c index ce16815327..8ce494b5fc 100644 --- a/src/mainboard/intel/wtm2/mainboard.c +++ b/src/mainboard/intel/wtm2/mainboard.c @@ -16,7 +16,6 @@ #include #include -#include #include #include #include diff --git a/src/mainboard/kontron/986lcd-m/mainboard.c b/src/mainboard/kontron/986lcd-m/mainboard.c index b3e84278a3..fcf43e145e 100644 --- a/src/mainboard/kontron/986lcd-m/mainboard.c +++ b/src/mainboard/kontron/986lcd-m/mainboard.c @@ -16,7 +16,6 @@ #include #include #include -#include #include #include #include diff --git a/src/mainboard/lenovo/s230u/early_init.c b/src/mainboard/lenovo/s230u/early_init.c index 2de0637140..10ce300432 100644 --- a/src/mainboard/lenovo/s230u/early_init.c +++ b/src/mainboard/lenovo/s230u/early_init.c @@ -17,7 +17,6 @@ #include #include #include -#include #include #include #include diff --git a/src/mainboard/lenovo/t430s/variants/t431s/romstage.c b/src/mainboard/lenovo/t430s/variants/t431s/romstage.c index 3f62f06c58..fa6028dbee 100644 --- a/src/mainboard/lenovo/t430s/variants/t431s/romstage.c +++ b/src/mainboard/lenovo/t430s/variants/t431s/romstage.c @@ -16,7 +16,6 @@ */ #include -#include #include #include #include diff --git a/src/mainboard/lenovo/t60/mainboard.c b/src/mainboard/lenovo/t60/mainboard.c index 5f599465a1..93cad771ae 100644 --- a/src/mainboard/lenovo/t60/mainboard.c +++ b/src/mainboard/lenovo/t60/mainboard.c @@ -15,7 +15,6 @@ * GNU General Public License for more details. */ -#include #include #include #include diff --git a/src/mainboard/lenovo/x201/mainboard.c b/src/mainboard/lenovo/x201/mainboard.c index a403237e27..4cd3bdee5f 100644 --- a/src/mainboard/lenovo/x201/mainboard.c +++ b/src/mainboard/lenovo/x201/mainboard.c @@ -17,7 +17,6 @@ */ #include -#include #include #include #include diff --git a/src/mainboard/lenovo/x201/romstage.c b/src/mainboard/lenovo/x201/romstage.c index c8e8afbb30..7bab9576bc 100644 --- a/src/mainboard/lenovo/x201/romstage.c +++ b/src/mainboard/lenovo/x201/romstage.c @@ -18,7 +18,6 @@ #include #include -#include #include #include diff --git a/src/mainboard/packardbell/ms2290/mainboard.c b/src/mainboard/packardbell/ms2290/mainboard.c index f64e9e34c8..d4e48bc0be 100644 --- a/src/mainboard/packardbell/ms2290/mainboard.c +++ b/src/mainboard/packardbell/ms2290/mainboard.c @@ -18,8 +18,6 @@ #include #include -#include -#include #include #include #include diff --git a/src/mainboard/packardbell/ms2290/romstage.c b/src/mainboard/packardbell/ms2290/romstage.c index 4d94329b60..1f9d22982a 100644 --- a/src/mainboard/packardbell/ms2290/romstage.c +++ b/src/mainboard/packardbell/ms2290/romstage.c @@ -17,7 +17,6 @@ */ #include -#include #include #include diff --git a/src/mainboard/samsung/lumpy/mainboard.c b/src/mainboard/samsung/lumpy/mainboard.c index c64a51b7cb..e28e0d82ef 100644 --- a/src/mainboard/samsung/lumpy/mainboard.c +++ b/src/mainboard/samsung/lumpy/mainboard.c @@ -17,7 +17,6 @@ #include #include #include -#include #include #include #include diff --git a/src/mainboard/supermicro/x10slm-f/mainboard.c b/src/mainboard/supermicro/x10slm-f/mainboard.c index 4bd5d159c1..56674b9873 100644 --- a/src/mainboard/supermicro/x10slm-f/mainboard.c +++ b/src/mainboard/supermicro/x10slm-f/mainboard.c @@ -16,7 +16,6 @@ #include #include -#include #include #include #include From 88f107012abe6537fe7ce6d60a95aa66466ae2d1 Mon Sep 17 00:00:00 2001 From: Elyes HAOUAS Date: Tue, 27 Aug 2019 16:04:34 +0200 Subject: [PATCH 0757/1242] soc/qualcomm/sdm845: Remove unused 'include ' Change-Id: I9b91184ee1daf4dd40f17984ef2a30756e845906 Signed-off-by: Elyes HAOUAS Reviewed-on: https://review.coreboot.org/c/coreboot/+/35123 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin --- src/soc/qualcomm/sdm845/aop_load_reset.c | 1 - 1 file changed, 1 deletion(-) diff --git a/src/soc/qualcomm/sdm845/aop_load_reset.c b/src/soc/qualcomm/sdm845/aop_load_reset.c index 317c4febbc..782c83ae8e 100644 --- a/src/soc/qualcomm/sdm845/aop_load_reset.c +++ b/src/soc/qualcomm/sdm845/aop_load_reset.c @@ -16,7 +16,6 @@ #include #include #include -#include #include #include #include From dda17fa2220a4181971a0c6973aededea0e1517b Mon Sep 17 00:00:00 2001 From: Elyes HAOUAS Date: Sun, 27 Oct 2019 13:09:37 +0100 Subject: [PATCH 0758/1242] src: Use '#include ' when appropriate MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Change-Id: Icdd6b49751763ef0edd4c57e855cc1d042dc6d4d Signed-off-by: Elyes HAOUAS Reviewed-on: https://review.coreboot.org/c/coreboot/+/36373 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki --- src/cpu/intel/haswell/smmrelocate.c | 1 + src/cpu/intel/model_2065x/model_2065x_init.c | 1 + src/cpu/x86/lapic/lapic_cpu_init.c | 1 + src/include/cpu/x86/lapic.h | 1 - src/soc/intel/broadwell/smmrelocate.c | 1 + src/soc/intel/cannonlake/smmrelocate.c | 1 + src/soc/intel/icelake/smmrelocate.c | 1 + src/soc/intel/skylake/smmrelocate.c | 1 + src/soc/intel/tigerlake/smmrelocate.c | 1 + 9 files changed, 8 insertions(+), 1 deletion(-) diff --git a/src/cpu/intel/haswell/smmrelocate.c b/src/cpu/intel/haswell/smmrelocate.c index 8419746cdc..d259460dd7 100644 --- a/src/cpu/intel/haswell/smmrelocate.c +++ b/src/cpu/intel/haswell/smmrelocate.c @@ -27,6 +27,7 @@ #include #include #include +#include #include "haswell.h" #define MSR_PRMRR_PHYS_BASE 0x1f4 diff --git a/src/cpu/intel/model_2065x/model_2065x_init.c b/src/cpu/intel/model_2065x/model_2065x_init.c index d7e84ec006..a9c28f6fdc 100644 --- a/src/cpu/intel/model_2065x/model_2065x_init.c +++ b/src/cpu/intel/model_2065x/model_2065x_init.c @@ -30,6 +30,7 @@ #include "chip.h" #include #include +#include /* * List of supported C-states in this processor diff --git a/src/cpu/x86/lapic/lapic_cpu_init.c b/src/cpu/x86/lapic/lapic_cpu_init.c index 48350b3246..be825eccd2 100644 --- a/src/cpu/x86/lapic/lapic_cpu_init.c +++ b/src/cpu/x86/lapic/lapic_cpu_init.c @@ -28,6 +28,7 @@ #include #include #include +#include #include #include diff --git a/src/include/cpu/x86/lapic.h b/src/include/cpu/x86/lapic.h index 6fd1997e76..f8081b50da 100644 --- a/src/include/cpu/x86/lapic.h +++ b/src/include/cpu/x86/lapic.h @@ -4,7 +4,6 @@ #include #include #include -#include static __always_inline unsigned long lapic_read(unsigned long reg) { diff --git a/src/soc/intel/broadwell/smmrelocate.c b/src/soc/intel/broadwell/smmrelocate.c index b5af9895f9..7bf351a5ad 100644 --- a/src/soc/intel/broadwell/smmrelocate.c +++ b/src/soc/intel/broadwell/smmrelocate.c @@ -27,6 +27,7 @@ #include #include #include +#include #include #include #include diff --git a/src/soc/intel/cannonlake/smmrelocate.c b/src/soc/intel/cannonlake/smmrelocate.c index 54e2f927b8..e99a9a27be 100644 --- a/src/soc/intel/cannonlake/smmrelocate.c +++ b/src/soc/intel/cannonlake/smmrelocate.c @@ -28,6 +28,7 @@ #include #include #include +#include #include #include #include diff --git a/src/soc/intel/icelake/smmrelocate.c b/src/soc/intel/icelake/smmrelocate.c index cc8a5ff2e8..0bedc9e6dd 100644 --- a/src/soc/intel/icelake/smmrelocate.c +++ b/src/soc/intel/icelake/smmrelocate.c @@ -27,6 +27,7 @@ #include #include #include +#include #include #include #include diff --git a/src/soc/intel/skylake/smmrelocate.c b/src/soc/intel/skylake/smmrelocate.c index 65d96ae954..62fc7e415d 100644 --- a/src/soc/intel/skylake/smmrelocate.c +++ b/src/soc/intel/skylake/smmrelocate.c @@ -28,6 +28,7 @@ #include #include #include +#include #include #include #include diff --git a/src/soc/intel/tigerlake/smmrelocate.c b/src/soc/intel/tigerlake/smmrelocate.c index 46f550bfb5..9e21a233a3 100644 --- a/src/soc/intel/tigerlake/smmrelocate.c +++ b/src/soc/intel/tigerlake/smmrelocate.c @@ -27,6 +27,7 @@ #include #include #include +#include #include #include #include From 94b503094f8a424a02b18bb7f09c639c896df85e Mon Sep 17 00:00:00 2001 From: Elyes HAOUAS Date: Sat, 30 Nov 2019 20:06:24 +0100 Subject: [PATCH 0759/1242] src/security: Remove unused MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Change-Id: I0b5c375baf7911ebced2f8c43a88aae014c877ad Signed-off-by: Elyes HAOUAS Reviewed-on: https://review.coreboot.org/c/coreboot/+/33694 Reviewed-by: Kyösti Mälkki Tested-by: build bot (Jenkins) --- src/security/tpm/tspi/tspi.c | 1 - src/security/tpm/tss/tcg-2.0/tss_marshaling.c | 1 - src/security/vboot/secdata_mock.c | 1 - src/security/vboot/secdata_tpm.c | 1 - 4 files changed, 4 deletions(-) diff --git a/src/security/tpm/tspi/tspi.c b/src/security/tpm/tspi/tspi.c index 966b8b7c77..5fcf92df65 100644 --- a/src/security/tpm/tspi/tspi.c +++ b/src/security/tpm/tspi/tspi.c @@ -19,7 +19,6 @@ #include #include #include -#include #if CONFIG(VBOOT) #include #include diff --git a/src/security/tpm/tss/tcg-2.0/tss_marshaling.c b/src/security/tpm/tss/tcg-2.0/tss_marshaling.c index 720e7c4b68..48798c7a04 100644 --- a/src/security/tpm/tss/tcg-2.0/tss_marshaling.c +++ b/src/security/tpm/tss/tcg-2.0/tss_marshaling.c @@ -7,7 +7,6 @@ #include #include -#include #include #include "tss_marshaling.h" diff --git a/src/security/vboot/secdata_mock.c b/src/security/vboot/secdata_mock.c index a6c4afb170..a4957f9575 100644 --- a/src/security/vboot/secdata_mock.c +++ b/src/security/vboot/secdata_mock.c @@ -32,7 +32,6 @@ * stored in the TPM NVRAM. */ -#include #include #include diff --git a/src/security/vboot/secdata_tpm.c b/src/security/vboot/secdata_tpm.c index 0ce213662e..96fac29fcf 100644 --- a/src/security/vboot/secdata_tpm.c +++ b/src/security/vboot/secdata_tpm.c @@ -34,7 +34,6 @@ #include #include -#include #include #include #include From b12c2761f4c5dc0f812481620b0d73faf49d0495 Mon Sep 17 00:00:00 2001 From: Elyes HAOUAS Date: Sat, 30 Nov 2019 19:32:33 +0100 Subject: [PATCH 0760/1242] src/{drivers,device,ec}: Remove unused MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Change-Id: I05422ee4b0aa5c02525ef0b4eccb4dc3ecf871e8 Signed-off-by: Elyes HAOUAS Reviewed-on: https://review.coreboot.org/c/coreboot/+/32822 Reviewed-by: Kyösti Mälkki Tested-by: build bot (Jenkins) --- src/device/i2c_bus.c | 1 - src/device/oprom/realmode/x86.c | 1 - src/device/pci_class.c | 1 - src/device/pnp_device.c | 1 - src/drivers/aspeed/ast2050/ast2050.c | 1 - src/drivers/emulation/qemu/bochs.c | 1 - src/drivers/emulation/qemu/cirrus.c | 1 - src/drivers/i2c/rtd2132/rtd2132.c | 1 - src/drivers/intel/fsp2_0/include/fsp/info_header.h | 1 - src/drivers/intel/gma/intel_ddi.c | 1 - src/drivers/net/ne2k.c | 1 - src/drivers/parade/ps8625/ps8625.c | 1 - src/drivers/sil/3114/sil_sata.c | 1 - src/drivers/smmstore/store.c | 1 - src/drivers/uart/uart8250io.c | 1 - src/drivers/vpd/vpd.c | 1 - src/drivers/vpd/vpd_cbmem.c | 1 - src/ec/google/chromeec/ec_lpc.c | 1 - src/ec/google/chromeec/vstore.c | 1 - src/ec/google/wilco/chip.c | 1 - 20 files changed, 20 deletions(-) diff --git a/src/device/i2c_bus.c b/src/device/i2c_bus.c index 93634d223b..5d69efb73f 100644 --- a/src/device/i2c_bus.c +++ b/src/device/i2c_bus.c @@ -11,7 +11,6 @@ * GNU General Public License for more details. */ -#include #include #include #include diff --git a/src/device/oprom/realmode/x86.c b/src/device/oprom/realmode/x86.c index 1026ddb7ff..8ba0241ea4 100644 --- a/src/device/oprom/realmode/x86.c +++ b/src/device/oprom/realmode/x86.c @@ -21,7 +21,6 @@ #include #include #include -#include #include #include diff --git a/src/device/pci_class.c b/src/device/pci_class.c index 0aa2f2890a..e084c77bf1 100644 --- a/src/device/pci_class.c +++ b/src/device/pci_class.c @@ -14,7 +14,6 @@ #include #include #include -#include typedef struct { const unsigned char subclass_id; diff --git a/src/device/pnp_device.c b/src/device/pnp_device.c index 1852fc1b16..c58b375277 100644 --- a/src/device/pnp_device.c +++ b/src/device/pnp_device.c @@ -12,7 +12,6 @@ */ #include -#include #include #include #include diff --git a/src/drivers/aspeed/ast2050/ast2050.c b/src/drivers/aspeed/ast2050/ast2050.c index 67a1a803fe..8bc73078c7 100644 --- a/src/drivers/aspeed/ast2050/ast2050.c +++ b/src/drivers/aspeed/ast2050/ast2050.c @@ -11,7 +11,6 @@ * GNU General Public License for more details. */ -#include #include #include #include diff --git a/src/drivers/emulation/qemu/bochs.c b/src/drivers/emulation/qemu/bochs.c index f49b72cdfa..d9e4ce1d6e 100644 --- a/src/drivers/emulation/qemu/bochs.c +++ b/src/drivers/emulation/qemu/bochs.c @@ -13,7 +13,6 @@ #include #include -#include #include #include #include diff --git a/src/drivers/emulation/qemu/cirrus.c b/src/drivers/emulation/qemu/cirrus.c index 43710d9ece..6b1968c31d 100644 --- a/src/drivers/emulation/qemu/cirrus.c +++ b/src/drivers/emulation/qemu/cirrus.c @@ -14,7 +14,6 @@ #include #include -#include #include #include #include diff --git a/src/drivers/i2c/rtd2132/rtd2132.c b/src/drivers/i2c/rtd2132/rtd2132.c index 168f921e67..22eeaa83be 100644 --- a/src/drivers/i2c/rtd2132/rtd2132.c +++ b/src/drivers/i2c/rtd2132/rtd2132.c @@ -11,7 +11,6 @@ * GNU General Public License for more details. */ -#include #include #include #include diff --git a/src/drivers/intel/fsp2_0/include/fsp/info_header.h b/src/drivers/intel/fsp2_0/include/fsp/info_header.h index d9ca73fd7a..fd09f41305 100644 --- a/src/drivers/intel/fsp2_0/include/fsp/info_header.h +++ b/src/drivers/intel/fsp2_0/include/fsp/info_header.h @@ -16,7 +16,6 @@ #define _FSP2_0_INFO_HEADER_H_ #include -#include #include #define FSP_HDR_OFFSET 0x94 diff --git a/src/drivers/intel/gma/intel_ddi.c b/src/drivers/intel/gma/intel_ddi.c index 563f01bee6..d52b2933c6 100644 --- a/src/drivers/intel/gma/intel_ddi.c +++ b/src/drivers/intel/gma/intel_ddi.c @@ -27,7 +27,6 @@ */ #include -#include #include #include #include diff --git a/src/drivers/net/ne2k.c b/src/drivers/net/ne2k.c index 35d45ea624..b1d72de084 100644 --- a/src/drivers/net/ne2k.c +++ b/src/drivers/net/ne2k.c @@ -32,7 +32,6 @@ SMC8416 PIO support added by Andrew Bettison (andrewb@zip.com.au) on 4/3/02 #include #include #include -#include #include #include "ns8390.h" diff --git a/src/drivers/parade/ps8625/ps8625.c b/src/drivers/parade/ps8625/ps8625.c index c86c4d4100..8fd03b8b05 100644 --- a/src/drivers/parade/ps8625/ps8625.c +++ b/src/drivers/parade/ps8625/ps8625.c @@ -13,7 +13,6 @@ #include #include -#include #include "ps8625.h" diff --git a/src/drivers/sil/3114/sil_sata.c b/src/drivers/sil/3114/sil_sata.c index 5fc58c8a35..c38e642016 100644 --- a/src/drivers/sil/3114/sil_sata.c +++ b/src/drivers/sil/3114/sil_sata.c @@ -11,7 +11,6 @@ * GNU General Public License for more details. */ -#include #include #include #include diff --git a/src/drivers/smmstore/store.c b/src/drivers/smmstore/store.c index 23d2af015f..e0bfa10e0b 100644 --- a/src/drivers/smmstore/store.c +++ b/src/drivers/smmstore/store.c @@ -18,7 +18,6 @@ #include #include #include -#include #include /* diff --git a/src/drivers/uart/uart8250io.c b/src/drivers/uart/uart8250io.c index 58e014170a..1b9194ec2d 100644 --- a/src/drivers/uart/uart8250io.c +++ b/src/drivers/uart/uart8250io.c @@ -11,7 +11,6 @@ * GNU General Public License for more details. */ -#include #include #include #include diff --git a/src/drivers/vpd/vpd.c b/src/drivers/vpd/vpd.c index ab77a01bff..7ed1255357 100644 --- a/src/drivers/vpd/vpd.c +++ b/src/drivers/vpd/vpd.c @@ -8,7 +8,6 @@ #include #include #include -#include #include #include diff --git a/src/drivers/vpd/vpd_cbmem.c b/src/drivers/vpd/vpd_cbmem.c index 5b685069aa..a0bb161287 100644 --- a/src/drivers/vpd/vpd_cbmem.c +++ b/src/drivers/vpd/vpd_cbmem.c @@ -7,7 +7,6 @@ #include #include #include -#include #include #include diff --git a/src/ec/google/chromeec/ec_lpc.c b/src/ec/google/chromeec/ec_lpc.c index 1d7e7ee7c8..6bc4fbd310 100644 --- a/src/ec/google/chromeec/ec_lpc.c +++ b/src/ec/google/chromeec/ec_lpc.c @@ -20,7 +20,6 @@ #include #include #include -#include #include "chip.h" #include "ec.h" diff --git a/src/ec/google/chromeec/vstore.c b/src/ec/google/chromeec/vstore.c index 28c26036ba..50e964f27b 100644 --- a/src/ec/google/chromeec/vstore.c +++ b/src/ec/google/chromeec/vstore.c @@ -15,7 +15,6 @@ #include #include -#include #include "ec.h" #include "ec_commands.h" diff --git a/src/ec/google/wilco/chip.c b/src/ec/google/wilco/chip.c index 09211f82ab..70e612442c 100644 --- a/src/ec/google/wilco/chip.c +++ b/src/ec/google/wilco/chip.c @@ -22,7 +22,6 @@ #include #include #include -#include #include "commands.h" #include "ec.h" From dc987feccea6644c2fae7e02790a6ac32fff3752 Mon Sep 17 00:00:00 2001 From: Elyes HAOUAS Date: Sat, 30 Nov 2019 19:25:53 +0100 Subject: [PATCH 0761/1242] src/northbridge: Remove unused MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Change-Id: I7a214196b05d3af06c8cd742a6154b0627a0d82f Signed-off-by: Elyes HAOUAS Reviewed-on: https://review.coreboot.org/c/coreboot/+/33685 Reviewed-by: Kyösti Mälkki Tested-by: build bot (Jenkins) --- src/northbridge/amd/agesa/family14/dimmSpd.c | 1 - src/northbridge/amd/agesa/family14/northbridge.c | 1 - src/northbridge/amd/agesa/family15tn/dimmSpd.c | 1 - src/northbridge/amd/agesa/family15tn/northbridge.c | 1 - src/northbridge/amd/agesa/family16kb/dimmSpd.c | 1 - src/northbridge/amd/agesa/family16kb/northbridge.c | 1 - src/northbridge/amd/pi/00630F01/northbridge.c | 1 - src/northbridge/amd/pi/00660F01/dimmSpd.c | 1 - src/northbridge/amd/pi/00660F01/northbridge.c | 1 - src/northbridge/amd/pi/00730F01/northbridge.c | 1 - src/northbridge/intel/e7505/northbridge.c | 1 - src/northbridge/intel/e7505/raminit.c | 1 - src/northbridge/intel/gm45/northbridge.c | 1 - src/northbridge/intel/haswell/early_init.c | 1 - src/northbridge/intel/haswell/finalize.c | 1 - src/northbridge/intel/haswell/gma.c | 1 - src/northbridge/intel/haswell/minihd.c | 1 - src/northbridge/intel/haswell/northbridge.c | 1 - src/northbridge/intel/i440bx/northbridge.c | 1 - src/northbridge/intel/i440bx/raminit.c | 1 - src/northbridge/intel/i945/early_init.c | 1 - src/northbridge/intel/i945/northbridge.c | 1 - src/northbridge/intel/nehalem/early_init.c | 1 - src/northbridge/intel/nehalem/finalize.c | 1 - src/northbridge/intel/nehalem/northbridge.c | 1 - src/northbridge/intel/pineview/early_init.c | 1 - src/northbridge/intel/pineview/northbridge.c | 1 - src/northbridge/intel/sandybridge/early_init.c | 1 - src/northbridge/intel/sandybridge/finalize.c | 1 - src/northbridge/intel/sandybridge/northbridge.c | 1 - src/northbridge/intel/x4x/northbridge.c | 1 - 31 files changed, 31 deletions(-) diff --git a/src/northbridge/amd/agesa/family14/dimmSpd.c b/src/northbridge/amd/agesa/family14/dimmSpd.c index 98776505ba..652555236a 100644 --- a/src/northbridge/amd/agesa/family14/dimmSpd.c +++ b/src/northbridge/amd/agesa/family14/dimmSpd.c @@ -15,7 +15,6 @@ #include #include -#include #include /* SMBUS0_BASE_ADDRESS */ /* warning: Porting.h includes an open #pragma pack(1) */ diff --git a/src/northbridge/amd/agesa/family14/northbridge.c b/src/northbridge/amd/agesa/family14/northbridge.c index 83329a29cf..aba107bbcc 100644 --- a/src/northbridge/amd/agesa/family14/northbridge.c +++ b/src/northbridge/amd/agesa/family14/northbridge.c @@ -22,7 +22,6 @@ #include #include #include -#include #include #include #include diff --git a/src/northbridge/amd/agesa/family15tn/dimmSpd.c b/src/northbridge/amd/agesa/family15tn/dimmSpd.c index 7ca47097b2..30fd74bb72 100644 --- a/src/northbridge/amd/agesa/family15tn/dimmSpd.c +++ b/src/northbridge/amd/agesa/family15tn/dimmSpd.c @@ -15,7 +15,6 @@ #include #include -#include /* warning: Porting.h includes an open #pragma pack(1) */ #include diff --git a/src/northbridge/amd/agesa/family15tn/northbridge.c b/src/northbridge/amd/agesa/family15tn/northbridge.c index 01aedab94d..1733b28a72 100644 --- a/src/northbridge/amd/agesa/family15tn/northbridge.c +++ b/src/northbridge/amd/agesa/family15tn/northbridge.c @@ -23,7 +23,6 @@ #include #include #include -#include #include #include #include diff --git a/src/northbridge/amd/agesa/family16kb/dimmSpd.c b/src/northbridge/amd/agesa/family16kb/dimmSpd.c index 8c453bb7ae..78dc128fe4 100644 --- a/src/northbridge/amd/agesa/family16kb/dimmSpd.c +++ b/src/northbridge/amd/agesa/family16kb/dimmSpd.c @@ -15,7 +15,6 @@ #include #include -#include /* warning: Porting.h includes an open #pragma pack(1) */ #include diff --git a/src/northbridge/amd/agesa/family16kb/northbridge.c b/src/northbridge/amd/agesa/family16kb/northbridge.c index a05125593b..2e840987ae 100644 --- a/src/northbridge/amd/agesa/family16kb/northbridge.c +++ b/src/northbridge/amd/agesa/family16kb/northbridge.c @@ -22,7 +22,6 @@ #include #include #include -#include #include #include #include diff --git a/src/northbridge/amd/pi/00630F01/northbridge.c b/src/northbridge/amd/pi/00630F01/northbridge.c index 6afea7c890..b55b23c702 100644 --- a/src/northbridge/amd/pi/00630F01/northbridge.c +++ b/src/northbridge/amd/pi/00630F01/northbridge.c @@ -21,7 +21,6 @@ #include #include #include -#include #include #include #include diff --git a/src/northbridge/amd/pi/00660F01/dimmSpd.c b/src/northbridge/amd/pi/00660F01/dimmSpd.c index 349dacf4f4..d25a35f795 100644 --- a/src/northbridge/amd/pi/00660F01/dimmSpd.c +++ b/src/northbridge/amd/pi/00660F01/dimmSpd.c @@ -15,7 +15,6 @@ #include #include -#include /* warning: Porting.h includes an open #pragma pack(1) */ #include diff --git a/src/northbridge/amd/pi/00660F01/northbridge.c b/src/northbridge/amd/pi/00660F01/northbridge.c index c26f5aeed2..bef3c3c800 100644 --- a/src/northbridge/amd/pi/00660F01/northbridge.c +++ b/src/northbridge/amd/pi/00660F01/northbridge.c @@ -21,7 +21,6 @@ #include #include #include -#include #include #include #include diff --git a/src/northbridge/amd/pi/00730F01/northbridge.c b/src/northbridge/amd/pi/00730F01/northbridge.c index acb20e6c63..0f5305b8f2 100644 --- a/src/northbridge/amd/pi/00730F01/northbridge.c +++ b/src/northbridge/amd/pi/00730F01/northbridge.c @@ -23,7 +23,6 @@ #include #include #include -#include #include #include #include diff --git a/src/northbridge/intel/e7505/northbridge.c b/src/northbridge/intel/e7505/northbridge.c index 7cb0b5bfb7..074f63adaf 100644 --- a/src/northbridge/intel/e7505/northbridge.c +++ b/src/northbridge/intel/e7505/northbridge.c @@ -18,7 +18,6 @@ #include #include #include -#include #include "e7505.h" diff --git a/src/northbridge/intel/e7505/raminit.c b/src/northbridge/intel/e7505/raminit.c index ba07b3e69b..051b206523 100644 --- a/src/northbridge/intel/e7505/raminit.c +++ b/src/northbridge/intel/e7505/raminit.c @@ -30,7 +30,6 @@ #include #include #include -#include #include #include #include diff --git a/src/northbridge/intel/gm45/northbridge.c b/src/northbridge/intel/gm45/northbridge.c index e652090238..2625447ca5 100644 --- a/src/northbridge/intel/gm45/northbridge.c +++ b/src/northbridge/intel/gm45/northbridge.c @@ -19,7 +19,6 @@ #include #include #include -#include #include #include #include diff --git a/src/northbridge/intel/haswell/early_init.c b/src/northbridge/intel/haswell/early_init.c index 606c9c742d..666bda28f8 100644 --- a/src/northbridge/intel/haswell/early_init.c +++ b/src/northbridge/intel/haswell/early_init.c @@ -15,7 +15,6 @@ */ #include -#include #include #include #include diff --git a/src/northbridge/intel/haswell/finalize.c b/src/northbridge/intel/haswell/finalize.c index 1777006b63..ca36634f36 100644 --- a/src/northbridge/intel/haswell/finalize.c +++ b/src/northbridge/intel/haswell/finalize.c @@ -14,7 +14,6 @@ * GNU General Public License for more details. */ -#include #include #include "haswell.h" diff --git a/src/northbridge/intel/haswell/gma.c b/src/northbridge/intel/haswell/gma.c index 2081a396a1..3132c20136 100644 --- a/src/northbridge/intel/haswell/gma.c +++ b/src/northbridge/intel/haswell/gma.c @@ -29,7 +29,6 @@ #include #include #include -#include #include #include diff --git a/src/northbridge/intel/haswell/minihd.c b/src/northbridge/intel/haswell/minihd.c index 61265dd281..ff5b943f96 100644 --- a/src/northbridge/intel/haswell/minihd.c +++ b/src/northbridge/intel/haswell/minihd.c @@ -21,7 +21,6 @@ #include #include #include -#include #include static const u32 minihd_verb_table[] = { diff --git a/src/northbridge/intel/haswell/northbridge.c b/src/northbridge/intel/haswell/northbridge.c index 1efa6603d2..79ab747f6d 100644 --- a/src/northbridge/intel/haswell/northbridge.c +++ b/src/northbridge/intel/haswell/northbridge.c @@ -25,7 +25,6 @@ #include #include #include -#include #include #include diff --git a/src/northbridge/intel/i440bx/northbridge.c b/src/northbridge/intel/i440bx/northbridge.c index ef6329c172..d23a8436f8 100644 --- a/src/northbridge/intel/i440bx/northbridge.c +++ b/src/northbridge/intel/i440bx/northbridge.c @@ -17,7 +17,6 @@ #include #include #include -#include #include #include "northbridge.h" #include "i440bx.h" diff --git a/src/northbridge/intel/i440bx/raminit.c b/src/northbridge/intel/i440bx/raminit.c index 91959c7cd8..0f9f2f652a 100644 --- a/src/northbridge/intel/i440bx/raminit.c +++ b/src/northbridge/intel/i440bx/raminit.c @@ -18,7 +18,6 @@ #include #include #include -#include #include #include #include diff --git a/src/northbridge/intel/i945/early_init.c b/src/northbridge/intel/i945/early_init.c index 6629a0e0f8..6e650eb050 100644 --- a/src/northbridge/intel/i945/early_init.c +++ b/src/northbridge/intel/i945/early_init.c @@ -13,7 +13,6 @@ * GNU General Public License for more details. */ -#include #include #include #include diff --git a/src/northbridge/intel/i945/northbridge.c b/src/northbridge/intel/i945/northbridge.c index bcecd8854b..2242883186 100644 --- a/src/northbridge/intel/i945/northbridge.c +++ b/src/northbridge/intel/i945/northbridge.c @@ -20,7 +20,6 @@ #include #include #include -#include #include #include #include "i945.h" diff --git a/src/northbridge/intel/nehalem/early_init.c b/src/northbridge/intel/nehalem/early_init.c index 5bdb5d5e0a..a809121310 100644 --- a/src/northbridge/intel/nehalem/early_init.c +++ b/src/northbridge/intel/nehalem/early_init.c @@ -16,7 +16,6 @@ */ #include -#include #include #include #include diff --git a/src/northbridge/intel/nehalem/finalize.c b/src/northbridge/intel/nehalem/finalize.c index 33892491b5..c03b067cbf 100644 --- a/src/northbridge/intel/nehalem/finalize.c +++ b/src/northbridge/intel/nehalem/finalize.c @@ -14,7 +14,6 @@ * GNU General Public License for more details. */ -#include #include "nehalem.h" #define PCI_DEV_SNB PCI_DEV(0, 0, 0) diff --git a/src/northbridge/intel/nehalem/northbridge.c b/src/northbridge/intel/nehalem/northbridge.c index 8f415cb4bf..1718307797 100644 --- a/src/northbridge/intel/nehalem/northbridge.c +++ b/src/northbridge/intel/nehalem/northbridge.c @@ -25,7 +25,6 @@ #include #include #include -#include #include "chip.h" #include "nehalem.h" #include diff --git a/src/northbridge/intel/pineview/early_init.c b/src/northbridge/intel/pineview/early_init.c index 6698fa85e0..aec910c4ef 100644 --- a/src/northbridge/intel/pineview/early_init.c +++ b/src/northbridge/intel/pineview/early_init.c @@ -14,7 +14,6 @@ * GNU General Public License for more details. */ -#include #include #include #include diff --git a/src/northbridge/intel/pineview/northbridge.c b/src/northbridge/intel/pineview/northbridge.c index fc71bc3b6e..c08258653b 100644 --- a/src/northbridge/intel/pineview/northbridge.c +++ b/src/northbridge/intel/pineview/northbridge.c @@ -20,7 +20,6 @@ #include #include #include -#include #include #include #include diff --git a/src/northbridge/intel/sandybridge/early_init.c b/src/northbridge/intel/sandybridge/early_init.c index 0c6ef7ebdf..4866558ca9 100644 --- a/src/northbridge/intel/sandybridge/early_init.c +++ b/src/northbridge/intel/sandybridge/early_init.c @@ -16,7 +16,6 @@ * GNU General Public License for more details. */ -#include #include #include #include diff --git a/src/northbridge/intel/sandybridge/finalize.c b/src/northbridge/intel/sandybridge/finalize.c index 7051b240ed..a8f8603f02 100644 --- a/src/northbridge/intel/sandybridge/finalize.c +++ b/src/northbridge/intel/sandybridge/finalize.c @@ -14,7 +14,6 @@ * GNU General Public License for more details. */ -#include #include #include "sandybridge.h" diff --git a/src/northbridge/intel/sandybridge/northbridge.c b/src/northbridge/intel/sandybridge/northbridge.c index b34f07d696..5ff123e63b 100644 --- a/src/northbridge/intel/sandybridge/northbridge.c +++ b/src/northbridge/intel/sandybridge/northbridge.c @@ -24,7 +24,6 @@ #include #include #include -#include #include "chip.h" #include "sandybridge.h" #include diff --git a/src/northbridge/intel/x4x/northbridge.c b/src/northbridge/intel/x4x/northbridge.c index 252e14fda6..b7f9aaaff5 100644 --- a/src/northbridge/intel/x4x/northbridge.c +++ b/src/northbridge/intel/x4x/northbridge.c @@ -20,7 +20,6 @@ #include #include #include -#include #include #include #include From 38d2540674e07af2eba981c3be166c6127b02878 Mon Sep 17 00:00:00 2001 From: Elyes HAOUAS Date: Sat, 30 Nov 2019 19:22:58 +0100 Subject: [PATCH 0762/1242] src/southbridge: Remove unused MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Change-Id: I5728b44fdd680b21e951397a2390e24f9171ac34 Signed-off-by: Elyes HAOUAS Reviewed-on: https://review.coreboot.org/c/coreboot/+/32829 Reviewed-by: Kyösti Mälkki Tested-by: build bot (Jenkins) --- src/southbridge/amd/agesa/hudson/spi.c | 1 - src/southbridge/intel/bd82x6x/me_status.c | 1 - src/southbridge/intel/common/smbus.c | 1 - src/southbridge/intel/i82801ix/i82801ix.c | 1 - src/southbridge/intel/i82801jx/i82801jx.c | 1 - src/southbridge/intel/lynxpoint/me_status.c | 1 - src/southbridge/intel/lynxpoint/serialio.c | 1 - 7 files changed, 7 deletions(-) diff --git a/src/southbridge/amd/agesa/hudson/spi.c b/src/southbridge/amd/agesa/hudson/spi.c index 9c546c5c40..9656027993 100644 --- a/src/southbridge/amd/agesa/hudson/spi.c +++ b/src/southbridge/amd/agesa/hudson/spi.c @@ -13,7 +13,6 @@ * GNU General Public License for more details. */ #include -#include #include #include #include diff --git a/src/southbridge/intel/bd82x6x/me_status.c b/src/southbridge/intel/bd82x6x/me_status.c index 4d9540a074..e0b2cbeb47 100644 --- a/src/southbridge/intel/bd82x6x/me_status.c +++ b/src/southbridge/intel/bd82x6x/me_status.c @@ -14,7 +14,6 @@ * GNU General Public License for more details. */ -#include #include #include "me.h" diff --git a/src/southbridge/intel/common/smbus.c b/src/southbridge/intel/common/smbus.c index e575abc40e..db934a3f0b 100644 --- a/src/southbridge/intel/common/smbus.c +++ b/src/southbridge/intel/common/smbus.c @@ -19,7 +19,6 @@ #include #include #include -#include #include #include "smbus.h" diff --git a/src/southbridge/intel/i82801ix/i82801ix.c b/src/southbridge/intel/i82801ix/i82801ix.c index 132b684f30..753c336aac 100644 --- a/src/southbridge/intel/i82801ix/i82801ix.c +++ b/src/southbridge/intel/i82801ix/i82801ix.c @@ -16,7 +16,6 @@ * GNU General Public License for more details. */ -#include #include #include #include diff --git a/src/southbridge/intel/i82801jx/i82801jx.c b/src/southbridge/intel/i82801jx/i82801jx.c index 490ece73f0..ebd427fdd5 100644 --- a/src/southbridge/intel/i82801jx/i82801jx.c +++ b/src/southbridge/intel/i82801jx/i82801jx.c @@ -16,7 +16,6 @@ * GNU General Public License for more details. */ -#include #include #include #include diff --git a/src/southbridge/intel/lynxpoint/me_status.c b/src/southbridge/intel/lynxpoint/me_status.c index ad8362d9d1..8f6932bec4 100644 --- a/src/southbridge/intel/lynxpoint/me_status.c +++ b/src/southbridge/intel/lynxpoint/me_status.c @@ -14,7 +14,6 @@ * GNU General Public License for more details. */ -#include #include #include "me.h" diff --git a/src/southbridge/intel/lynxpoint/serialio.c b/src/southbridge/intel/lynxpoint/serialio.c index b5ccfa6338..60668dd4c1 100644 --- a/src/southbridge/intel/lynxpoint/serialio.c +++ b/src/southbridge/intel/lynxpoint/serialio.c @@ -21,7 +21,6 @@ #include #include #include -#include #include "chip.h" #include "pch.h" #include "nvs.h" From 8cf28dbf93a0b8a888ca813e05c4728d62188a45 Mon Sep 17 00:00:00 2001 From: Elyes HAOUAS Date: Sat, 30 Nov 2019 19:42:33 +0100 Subject: [PATCH 0763/1242] soc/{amd,cavium,mediatek,sifive}: Remove unused MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Change-Id: I83322e246fe81b97188be17a3fdda16d36df0678 Signed-off-by: Elyes HAOUAS Reviewed-on: https://review.coreboot.org/c/coreboot/+/33688 Reviewed-by: Kyösti Mälkki Tested-by: build bot (Jenkins) --- src/soc/amd/picasso/northbridge.c | 1 - src/soc/amd/picasso/sm.c | 1 - src/soc/amd/stoneyridge/BiosCallOuts.c | 1 - src/soc/amd/stoneyridge/northbridge.c | 1 - src/soc/amd/stoneyridge/sm.c | 1 - src/soc/cavium/cn81xx/cbmem.c | 1 - src/soc/cavium/cn81xx/spi.c | 1 - src/soc/mediatek/common/ddp.c | 1 - src/soc/mediatek/common/spi.c | 1 - src/soc/mediatek/mt8173/ddp.c | 1 - src/soc/mediatek/mt8173/include/soc/gpio.h | 1 - src/soc/mediatek/mt8183/ddp.c | 1 - src/soc/sifive/fu540/clock.c | 1 - 13 files changed, 13 deletions(-) diff --git a/src/soc/amd/picasso/northbridge.c b/src/soc/amd/picasso/northbridge.c index 4a1493cba3..282f9628ea 100644 --- a/src/soc/amd/picasso/northbridge.c +++ b/src/soc/amd/picasso/northbridge.c @@ -33,7 +33,6 @@ #include #include #include -#include #include #include diff --git a/src/soc/amd/picasso/sm.c b/src/soc/amd/picasso/sm.c index 803e628320..438909d7cb 100644 --- a/src/soc/amd/picasso/sm.c +++ b/src/soc/amd/picasso/sm.c @@ -20,7 +20,6 @@ #include #include #include -#include #include #include diff --git a/src/soc/amd/stoneyridge/BiosCallOuts.c b/src/soc/amd/stoneyridge/BiosCallOuts.c index c55e73499a..2ee92786ee 100644 --- a/src/soc/amd/stoneyridge/BiosCallOuts.c +++ b/src/soc/amd/stoneyridge/BiosCallOuts.c @@ -21,7 +21,6 @@ #include #include #include -#include #include #include #include diff --git a/src/soc/amd/stoneyridge/northbridge.c b/src/soc/amd/stoneyridge/northbridge.c index c98d0a9517..cd78ff83a2 100644 --- a/src/soc/amd/stoneyridge/northbridge.c +++ b/src/soc/amd/stoneyridge/northbridge.c @@ -36,7 +36,6 @@ #include #include #include -#include #include #include diff --git a/src/soc/amd/stoneyridge/sm.c b/src/soc/amd/stoneyridge/sm.c index fbcddfab84..2dba0d78df 100644 --- a/src/soc/amd/stoneyridge/sm.c +++ b/src/soc/amd/stoneyridge/sm.c @@ -19,7 +19,6 @@ #include #include #include -#include #include #include diff --git a/src/soc/cavium/cn81xx/cbmem.c b/src/soc/cavium/cn81xx/cbmem.c index a39bf4fe35..284608c3a7 100644 --- a/src/soc/cavium/cn81xx/cbmem.c +++ b/src/soc/cavium/cn81xx/cbmem.c @@ -17,7 +17,6 @@ #include #include #include -#include #include void *cbmem_top_chipset(void) diff --git a/src/soc/cavium/cn81xx/spi.c b/src/soc/cavium/cn81xx/spi.c index 2ba25a201a..6a5abb131a 100644 --- a/src/soc/cavium/cn81xx/spi.c +++ b/src/soc/cavium/cn81xx/spi.c @@ -25,7 +25,6 @@ #include #include #include -#include #include union cavium_spi_cfg { diff --git a/src/soc/mediatek/common/ddp.c b/src/soc/mediatek/common/ddp.c index 8f1f0e64ac..494f470d10 100644 --- a/src/soc/mediatek/common/ddp.c +++ b/src/soc/mediatek/common/ddp.c @@ -15,7 +15,6 @@ #include #include -#include #include #include #include diff --git a/src/soc/mediatek/common/spi.c b/src/soc/mediatek/common/spi.c index 9271d6e6dc..dbbc14dc18 100644 --- a/src/soc/mediatek/common/spi.c +++ b/src/soc/mediatek/common/spi.c @@ -18,7 +18,6 @@ #include #include #include -#include #include #include #include diff --git a/src/soc/mediatek/mt8173/ddp.c b/src/soc/mediatek/mt8173/ddp.c index 555bfe905f..0a57565d94 100644 --- a/src/soc/mediatek/mt8173/ddp.c +++ b/src/soc/mediatek/mt8173/ddp.c @@ -15,7 +15,6 @@ #include #include -#include #include #include #include diff --git a/src/soc/mediatek/mt8173/include/soc/gpio.h b/src/soc/mediatek/mt8173/include/soc/gpio.h index ec0833408e..8a6e13a6f2 100644 --- a/src/soc/mediatek/mt8173/include/soc/gpio.h +++ b/src/soc/mediatek/mt8173/include/soc/gpio.h @@ -16,7 +16,6 @@ #define SOC_MEDIATEK_MT8173_GPIO_H #include -#include #include #include diff --git a/src/soc/mediatek/mt8183/ddp.c b/src/soc/mediatek/mt8183/ddp.c index 50d6caf776..a54b134e6d 100644 --- a/src/soc/mediatek/mt8183/ddp.c +++ b/src/soc/mediatek/mt8183/ddp.c @@ -15,7 +15,6 @@ #include #include -#include #include #include #include diff --git a/src/soc/sifive/fu540/clock.c b/src/soc/sifive/fu540/clock.c index ef6221b262..a15e639839 100644 --- a/src/soc/sifive/fu540/clock.c +++ b/src/soc/sifive/fu540/clock.c @@ -17,7 +17,6 @@ #include #include #include -#include #include // 33.33 Mhz after reset From d51ee90f122de103756a26842f17ded2465db1a3 Mon Sep 17 00:00:00 2001 From: Elyes HAOUAS Date: Sat, 30 Nov 2019 19:27:54 +0100 Subject: [PATCH 0764/1242] src/soc/samsung: Remove unused MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Change-Id: I6a933295de7c41d62e6a95f955c098b49ea17f08 Signed-off-by: Elyes HAOUAS Reviewed-on: https://review.coreboot.org/c/coreboot/+/33689 Reviewed-by: Kyösti Mälkki Tested-by: build bot (Jenkins) --- src/soc/samsung/exynos5250/alternate_cbfs.c | 1 - src/soc/samsung/exynos5250/clock.c | 1 - src/soc/samsung/exynos5250/cpu.c | 1 - src/soc/samsung/exynos5250/fb.c | 1 - src/soc/samsung/exynos5250/spi.c | 1 - src/soc/samsung/exynos5420/alternate_cbfs.c | 1 - src/soc/samsung/exynos5420/clock.c | 1 - src/soc/samsung/exynos5420/cpu.c | 1 - src/soc/samsung/exynos5420/dp.c | 1 - src/soc/samsung/exynos5420/dp_lowlevel.c | 1 - src/soc/samsung/exynos5420/pinmux.c | 1 - src/soc/samsung/exynos5420/smp.c | 1 - src/soc/samsung/exynos5420/spi.c | 1 - 13 files changed, 13 deletions(-) diff --git a/src/soc/samsung/exynos5250/alternate_cbfs.c b/src/soc/samsung/exynos5250/alternate_cbfs.c index c319019eb6..1ff5d85bcb 100644 --- a/src/soc/samsung/exynos5250/alternate_cbfs.c +++ b/src/soc/samsung/exynos5250/alternate_cbfs.c @@ -18,7 +18,6 @@ #include #include #include -#include #include /* This allows USB A-A firmware upload from a compatible host in four parts: diff --git a/src/soc/samsung/exynos5250/clock.c b/src/soc/samsung/exynos5250/clock.c index e762af1908..f1b11b5a69 100644 --- a/src/soc/samsung/exynos5250/clock.c +++ b/src/soc/samsung/exynos5250/clock.c @@ -18,7 +18,6 @@ #include #include #include -#include #include /* input clock of PLL: SMDK5250 has 24MHz input clock */ diff --git a/src/soc/samsung/exynos5250/cpu.c b/src/soc/samsung/exynos5250/cpu.c index f00351ecf4..5f9989990d 100644 --- a/src/soc/samsung/exynos5250/cpu.c +++ b/src/soc/samsung/exynos5250/cpu.c @@ -23,7 +23,6 @@ #include #include #include -#include #include #include "chip.h" diff --git a/src/soc/samsung/exynos5250/fb.c b/src/soc/samsung/exynos5250/fb.c index 2e8acf2688..a29c61985f 100644 --- a/src/soc/samsung/exynos5250/fb.c +++ b/src/soc/samsung/exynos5250/fb.c @@ -25,7 +25,6 @@ #include #include #include -#include #include /* diff --git a/src/soc/samsung/exynos5250/spi.c b/src/soc/samsung/exynos5250/spi.c index 4d5e01f493..bacd08ca24 100644 --- a/src/soc/samsung/exynos5250/spi.c +++ b/src/soc/samsung/exynos5250/spi.c @@ -21,7 +21,6 @@ #include #include #include -#include #include #if defined(CONFIG_DEBUG_SPI) && CONFIG_DEBUG_SPI diff --git a/src/soc/samsung/exynos5420/alternate_cbfs.c b/src/soc/samsung/exynos5420/alternate_cbfs.c index fabc9cff7d..deb4f029a8 100644 --- a/src/soc/samsung/exynos5420/alternate_cbfs.c +++ b/src/soc/samsung/exynos5420/alternate_cbfs.c @@ -19,7 +19,6 @@ #include #include #include -#include #include /* This allows USB A-A firmware upload from a compatible host in four parts: diff --git a/src/soc/samsung/exynos5420/clock.c b/src/soc/samsung/exynos5420/clock.c index fe11cdecff..acfab976d5 100644 --- a/src/soc/samsung/exynos5420/clock.c +++ b/src/soc/samsung/exynos5420/clock.c @@ -18,7 +18,6 @@ #include #include #include -#include #include /* input clock of PLL: SMDK5420 has 24MHz input clock */ diff --git a/src/soc/samsung/exynos5420/cpu.c b/src/soc/samsung/exynos5420/cpu.c index 55b0512179..375b370a1b 100644 --- a/src/soc/samsung/exynos5420/cpu.c +++ b/src/soc/samsung/exynos5420/cpu.c @@ -24,7 +24,6 @@ #include #include #include -#include #include #include "chip.h" diff --git a/src/soc/samsung/exynos5420/dp.c b/src/soc/samsung/exynos5420/dp.c index 5ad3dd3e77..c48ea8c230 100644 --- a/src/soc/samsung/exynos5420/dp.c +++ b/src/soc/samsung/exynos5420/dp.c @@ -21,7 +21,6 @@ #include #include #include -#include #include /* diff --git a/src/soc/samsung/exynos5420/dp_lowlevel.c b/src/soc/samsung/exynos5420/dp_lowlevel.c index 164704bb8a..df579b0ad7 100644 --- a/src/soc/samsung/exynos5420/dp_lowlevel.c +++ b/src/soc/samsung/exynos5420/dp_lowlevel.c @@ -22,7 +22,6 @@ #include #include #include -#include /* FIXME: I think the DP controller shouldn't be hardcoded here... */ static struct exynos_dp * const dp_regs = (void *)EXYNOS5_DP1_BASE; diff --git a/src/soc/samsung/exynos5420/pinmux.c b/src/soc/samsung/exynos5420/pinmux.c index 999afa0247..347c6692c9 100644 --- a/src/soc/samsung/exynos5420/pinmux.c +++ b/src/soc/samsung/exynos5420/pinmux.c @@ -15,7 +15,6 @@ #include #include -#include static void exynos_pinmux_uart(int start, int count) { diff --git a/src/soc/samsung/exynos5420/smp.c b/src/soc/samsung/exynos5420/smp.c index 5e16063416..27c0fa60aa 100644 --- a/src/soc/samsung/exynos5420/smp.c +++ b/src/soc/samsung/exynos5420/smp.c @@ -18,7 +18,6 @@ #include #include #include -#include #include #include diff --git a/src/soc/samsung/exynos5420/spi.c b/src/soc/samsung/exynos5420/spi.c index 5637b0215d..a98f51d72c 100644 --- a/src/soc/samsung/exynos5420/spi.c +++ b/src/soc/samsung/exynos5420/spi.c @@ -20,7 +20,6 @@ #include #include #include -#include #include #include From 608fbf81109902cfd1775e61b18a2c37e2084d9d Mon Sep 17 00:00:00 2001 From: Elyes HAOUAS Date: Sat, 30 Nov 2019 19:38:23 +0100 Subject: [PATCH 0765/1242] src/soc/intel: Remove unused MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Change-Id: I71a5a6c3748d5a3910970bfb1ec3d7ecd3184cfd Signed-off-by: Elyes HAOUAS Reviewed-on: https://review.coreboot.org/c/coreboot/+/33686 Reviewed-by: Kyösti Mälkki Tested-by: build bot (Jenkins) --- src/soc/intel/baytrail/cpu.c | 1 - src/soc/intel/baytrail/gfx.c | 1 - src/soc/intel/baytrail/ramstage.c | 1 - src/soc/intel/baytrail/smihandler.c | 1 - src/soc/intel/braswell/cpu.c | 1 - src/soc/intel/braswell/ramstage.c | 1 - src/soc/intel/braswell/smihandler.c | 1 - src/soc/intel/broadwell/finalize.c | 1 - src/soc/intel/broadwell/igd.c | 1 - src/soc/intel/broadwell/me_status.c | 1 - src/soc/intel/broadwell/minihd.c | 1 - src/soc/intel/broadwell/pei_data.c | 1 - src/soc/intel/broadwell/ramstage.c | 1 - src/soc/intel/broadwell/romstage/cpu.c | 1 - src/soc/intel/broadwell/romstage/power_state.c | 1 - src/soc/intel/broadwell/romstage/systemagent.c | 1 - src/soc/intel/broadwell/serialio.c | 1 - src/soc/intel/broadwell/systemagent.c | 1 - src/soc/intel/cannonlake/finalize.c | 1 - src/soc/intel/cannonlake/me.c | 1 - src/soc/intel/cannonlake/pmutil.c | 1 - src/soc/intel/common/acpi_wake_source.c | 1 - src/soc/intel/common/block/fast_spi/fast_spi.c | 1 - src/soc/intel/common/block/smm/smihandler.c | 1 - src/soc/intel/common/block/systemagent/memmap.c | 1 - src/soc/intel/denverton_ns/csme_ie_kt.c | 1 - src/soc/intel/denverton_ns/smihandler.c | 1 - src/soc/intel/denverton_ns/systemagent.c | 1 - src/soc/intel/icelake/finalize.c | 1 - src/soc/intel/icelake/pmutil.c | 1 - src/soc/intel/skylake/finalize.c | 1 - src/soc/intel/skylake/me.c | 1 - src/soc/intel/skylake/pmutil.c | 1 - src/soc/intel/tigerlake/finalize.c | 1 - src/soc/intel/tigerlake/pmutil.c | 1 - 35 files changed, 35 deletions(-) diff --git a/src/soc/intel/baytrail/cpu.c b/src/soc/intel/baytrail/cpu.c index d12ece0930..90e045c718 100644 --- a/src/soc/intel/baytrail/cpu.c +++ b/src/soc/intel/baytrail/cpu.c @@ -13,7 +13,6 @@ * GNU General Public License for more details. */ -#include #include #include #include diff --git a/src/soc/intel/baytrail/gfx.c b/src/soc/intel/baytrail/gfx.c index 5100c8e777..bb83e337c4 100644 --- a/src/soc/intel/baytrail/gfx.c +++ b/src/soc/intel/baytrail/gfx.c @@ -21,7 +21,6 @@ #include #include #include -#include #include #include #include diff --git a/src/soc/intel/baytrail/ramstage.c b/src/soc/intel/baytrail/ramstage.c index 1715198c51..769e7ffd2b 100644 --- a/src/soc/intel/baytrail/ramstage.c +++ b/src/soc/intel/baytrail/ramstage.c @@ -23,7 +23,6 @@ #include #include #include -#include #include #include diff --git a/src/soc/intel/baytrail/smihandler.c b/src/soc/intel/baytrail/smihandler.c index 2a92cb954c..3a096e3d80 100644 --- a/src/soc/intel/baytrail/smihandler.c +++ b/src/soc/intel/baytrail/smihandler.c @@ -14,7 +14,6 @@ */ #include -#include #include #include #include diff --git a/src/soc/intel/braswell/cpu.c b/src/soc/intel/braswell/cpu.c index a44b9cb2e5..4288394808 100644 --- a/src/soc/intel/braswell/cpu.c +++ b/src/soc/intel/braswell/cpu.c @@ -33,7 +33,6 @@ #include #include #include -#include /* Core level MSRs */ static const struct reg_script core_msr_script[] = { diff --git a/src/soc/intel/braswell/ramstage.c b/src/soc/intel/braswell/ramstage.c index d6a1cda8b3..f8011fdb73 100644 --- a/src/soc/intel/braswell/ramstage.c +++ b/src/soc/intel/braswell/ramstage.c @@ -37,7 +37,6 @@ #include #include #include -#include #include #define SHOW_PATTRS 1 diff --git a/src/soc/intel/braswell/smihandler.c b/src/soc/intel/braswell/smihandler.c index d0306caaa3..80b142aad8 100644 --- a/src/soc/intel/braswell/smihandler.c +++ b/src/soc/intel/braswell/smihandler.c @@ -29,7 +29,6 @@ #include #include #include -#include #include /* GNVS needs to be set by coreboot initiating a software SMI. */ diff --git a/src/soc/intel/broadwell/finalize.c b/src/soc/intel/broadwell/finalize.c index 1c5fdb8885..7866c4cec9 100644 --- a/src/soc/intel/broadwell/finalize.c +++ b/src/soc/intel/broadwell/finalize.c @@ -20,7 +20,6 @@ #include #include #include -#include #include #include #include diff --git a/src/soc/intel/broadwell/igd.c b/src/soc/intel/broadwell/igd.c index 31476809dc..924ec61dd4 100644 --- a/src/soc/intel/broadwell/igd.c +++ b/src/soc/intel/broadwell/igd.c @@ -22,7 +22,6 @@ #include #include #include -#include #include #include #include diff --git a/src/soc/intel/broadwell/me_status.c b/src/soc/intel/broadwell/me_status.c index 1880da158b..d89f108416 100644 --- a/src/soc/intel/broadwell/me_status.c +++ b/src/soc/intel/broadwell/me_status.c @@ -16,7 +16,6 @@ #include #include #include -#include #include #include #include diff --git a/src/soc/intel/broadwell/minihd.c b/src/soc/intel/broadwell/minihd.c index d51230a3f7..2e987bd9e5 100644 --- a/src/soc/intel/broadwell/minihd.c +++ b/src/soc/intel/broadwell/minihd.c @@ -21,7 +21,6 @@ #include #include #include -#include #include #include #include diff --git a/src/soc/intel/broadwell/pei_data.c b/src/soc/intel/broadwell/pei_data.c index 09753addb8..7b384c7737 100644 --- a/src/soc/intel/broadwell/pei_data.c +++ b/src/soc/intel/broadwell/pei_data.c @@ -13,7 +13,6 @@ * GNU General Public License for more details. */ -#include #include #include #include diff --git a/src/soc/intel/broadwell/ramstage.c b/src/soc/intel/broadwell/ramstage.c index 706536940d..bad9f96135 100644 --- a/src/soc/intel/broadwell/ramstage.c +++ b/src/soc/intel/broadwell/ramstage.c @@ -16,7 +16,6 @@ #include #include #include -#include #include #include #include diff --git a/src/soc/intel/broadwell/romstage/cpu.c b/src/soc/intel/broadwell/romstage/cpu.c index f251652de4..5a456970c5 100644 --- a/src/soc/intel/broadwell/romstage/cpu.c +++ b/src/soc/intel/broadwell/romstage/cpu.c @@ -14,7 +14,6 @@ */ #include -#include #include #include #include diff --git a/src/soc/intel/broadwell/romstage/power_state.c b/src/soc/intel/broadwell/romstage/power_state.c index ca22b4ef5b..1970c31eb5 100644 --- a/src/soc/intel/broadwell/romstage/power_state.c +++ b/src/soc/intel/broadwell/romstage/power_state.c @@ -22,7 +22,6 @@ #include #include #include -#include #include #include #include diff --git a/src/soc/intel/broadwell/romstage/systemagent.c b/src/soc/intel/broadwell/romstage/systemagent.c index 8be5b82a9b..5c0224a7b9 100644 --- a/src/soc/intel/broadwell/romstage/systemagent.c +++ b/src/soc/intel/broadwell/romstage/systemagent.c @@ -14,7 +14,6 @@ * GNU General Public License for more details. */ -#include #include #include #include diff --git a/src/soc/intel/broadwell/serialio.c b/src/soc/intel/broadwell/serialio.c index 161c8753f2..1a59829108 100644 --- a/src/soc/intel/broadwell/serialio.c +++ b/src/soc/intel/broadwell/serialio.c @@ -20,7 +20,6 @@ #include #include #include -#include #include #include #include diff --git a/src/soc/intel/broadwell/systemagent.c b/src/soc/intel/broadwell/systemagent.c index b6b5608a24..8cc6516d2f 100644 --- a/src/soc/intel/broadwell/systemagent.c +++ b/src/soc/intel/broadwell/systemagent.c @@ -22,7 +22,6 @@ #include #include #include -#include #include #include #include diff --git a/src/soc/intel/cannonlake/finalize.c b/src/soc/intel/cannonlake/finalize.c index 115b73254e..002e8ea42b 100644 --- a/src/soc/intel/cannonlake/finalize.c +++ b/src/soc/intel/cannonlake/finalize.c @@ -33,7 +33,6 @@ #include #include #include -#include #include "chip.h" diff --git a/src/soc/intel/cannonlake/me.c b/src/soc/intel/cannonlake/me.c index 776ff8bae0..0414470ef7 100644 --- a/src/soc/intel/cannonlake/me.c +++ b/src/soc/intel/cannonlake/me.c @@ -22,7 +22,6 @@ #include #include #include -#include /* Miscellaneous constants */ enum { diff --git a/src/soc/intel/cannonlake/pmutil.c b/src/soc/intel/cannonlake/pmutil.c index 428a89fe4b..aded9c0cec 100644 --- a/src/soc/intel/cannonlake/pmutil.c +++ b/src/soc/intel/cannonlake/pmutil.c @@ -30,7 +30,6 @@ #include #include #include -#include #include #include #include diff --git a/src/soc/intel/common/acpi_wake_source.c b/src/soc/intel/common/acpi_wake_source.c index f66706c4cd..389807e48c 100644 --- a/src/soc/intel/common/acpi_wake_source.c +++ b/src/soc/intel/common/acpi_wake_source.c @@ -19,7 +19,6 @@ #include #include #include -#include #include "acpi.h" __weak int soc_fill_acpi_wake(uint32_t *pm1, uint32_t **gpe0) diff --git a/src/soc/intel/common/block/fast_spi/fast_spi.c b/src/soc/intel/common/block/fast_spi/fast_spi.c index 5c29addcc9..019976ad8c 100644 --- a/src/soc/intel/common/block/fast_spi/fast_spi.c +++ b/src/soc/intel/common/block/fast_spi/fast_spi.c @@ -25,7 +25,6 @@ #include #include #include -#include /* * Get the FAST_SPIBAR. diff --git a/src/soc/intel/common/block/smm/smihandler.c b/src/soc/intel/common/block/smm/smihandler.c index 0581d23021..4677d27943 100644 --- a/src/soc/intel/common/block/smm/smihandler.c +++ b/src/soc/intel/common/block/smm/smihandler.c @@ -38,7 +38,6 @@ #include #include #include -#include /* GNVS needs to be set by coreboot initiating a software SMI. */ static struct global_nvs_t *gnvs; diff --git a/src/soc/intel/common/block/systemagent/memmap.c b/src/soc/intel/common/block/systemagent/memmap.c index 2b0fdc4e14..487c1d885d 100644 --- a/src/soc/intel/common/block/systemagent/memmap.c +++ b/src/soc/intel/common/block/systemagent/memmap.c @@ -20,7 +20,6 @@ #include #include #include -#include /* * Expected Host Memory Map (we don't know 100% and not all regions are present on all SoCs): diff --git a/src/soc/intel/denverton_ns/csme_ie_kt.c b/src/soc/intel/denverton_ns/csme_ie_kt.c index 5967840609..143e7b60a8 100644 --- a/src/soc/intel/denverton_ns/csme_ie_kt.c +++ b/src/soc/intel/denverton_ns/csme_ie_kt.c @@ -15,7 +15,6 @@ */ #include -#include #include #include #include diff --git a/src/soc/intel/denverton_ns/smihandler.c b/src/soc/intel/denverton_ns/smihandler.c index c292e4d79d..b4d81017b9 100644 --- a/src/soc/intel/denverton_ns/smihandler.c +++ b/src/soc/intel/denverton_ns/smihandler.c @@ -16,7 +16,6 @@ */ #include -#include #include #include #include diff --git a/src/soc/intel/denverton_ns/systemagent.c b/src/soc/intel/denverton_ns/systemagent.c index 00d52287b6..264e139210 100644 --- a/src/soc/intel/denverton_ns/systemagent.c +++ b/src/soc/intel/denverton_ns/systemagent.c @@ -24,7 +24,6 @@ #include #include #include -#include #include #include diff --git a/src/soc/intel/icelake/finalize.c b/src/soc/intel/icelake/finalize.c index a70b5a1ed4..6afa61e33d 100644 --- a/src/soc/intel/icelake/finalize.c +++ b/src/soc/intel/icelake/finalize.c @@ -33,7 +33,6 @@ #include #include #include -#include #define CAMERA1_CLK 0x8000 /* Camera 1 Clock */ #define CAMERA2_CLK 0x8080 /* Camera 2 Clock */ diff --git a/src/soc/intel/icelake/pmutil.c b/src/soc/intel/icelake/pmutil.c index 8efd426606..7b6168b084 100644 --- a/src/soc/intel/icelake/pmutil.c +++ b/src/soc/intel/icelake/pmutil.c @@ -29,7 +29,6 @@ #include #include #include -#include #include #include #include diff --git a/src/soc/intel/skylake/finalize.c b/src/soc/intel/skylake/finalize.c index 58a87012d7..e5d32d7b6f 100644 --- a/src/soc/intel/skylake/finalize.c +++ b/src/soc/intel/skylake/finalize.c @@ -38,7 +38,6 @@ #include #include #include -#include #include #include "chip.h" diff --git a/src/soc/intel/skylake/me.c b/src/soc/intel/skylake/me.c index f90a165051..d53d91ebdb 100644 --- a/src/soc/intel/skylake/me.c +++ b/src/soc/intel/skylake/me.c @@ -23,7 +23,6 @@ #include #include #include -#include /* HFSTS1[3:0] Current Working State Values */ diff --git a/src/soc/intel/skylake/pmutil.c b/src/soc/intel/skylake/pmutil.c index eb36e48ace..2b2141b377 100644 --- a/src/soc/intel/skylake/pmutil.c +++ b/src/soc/intel/skylake/pmutil.c @@ -29,7 +29,6 @@ #include #include #include -#include #include #include #include diff --git a/src/soc/intel/tigerlake/finalize.c b/src/soc/intel/tigerlake/finalize.c index ac9dc24b50..2de58a9e70 100644 --- a/src/soc/intel/tigerlake/finalize.c +++ b/src/soc/intel/tigerlake/finalize.c @@ -39,7 +39,6 @@ #include #include #include -#include #define CAMERA1_CLK 0x8000 /* Camera 1 Clock */ #define CAMERA2_CLK 0x8080 /* Camera 2 Clock */ diff --git a/src/soc/intel/tigerlake/pmutil.c b/src/soc/intel/tigerlake/pmutil.c index c163dc2f12..39734bb4e9 100644 --- a/src/soc/intel/tigerlake/pmutil.c +++ b/src/soc/intel/tigerlake/pmutil.c @@ -36,7 +36,6 @@ #include #include #include -#include #include #include #include From 0420e50b6b0ee25ba7802493caf33b2b6e320da2 Mon Sep 17 00:00:00 2001 From: Elyes HAOUAS Date: Sat, 30 Nov 2019 19:29:28 +0100 Subject: [PATCH 0766/1242] src/arch: Remove unused MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Change-Id: I79f065703b5249ca9630b06de7142bc52675076e Signed-off-by: Elyes HAOUAS Reviewed-on: https://review.coreboot.org/c/coreboot/+/32820 Reviewed-by: Kyösti Mälkki Tested-by: build bot (Jenkins) --- src/arch/arm/armv7/mmu.c | 1 - src/arch/arm/cpu.c | 1 - src/arch/arm64/armv8/mmu.c | 1 - src/arch/arm64/fit_payload.c | 1 - src/arch/riscv/fit_payload.c | 1 - src/arch/x86/acpigen_dsm.c | 1 - src/arch/x86/cbmem.c | 1 - src/arch/x86/include/arch/acpigen.h | 1 - src/arch/x86/mmap_boot.c | 1 - src/arch/x86/smbios.c | 1 - 10 files changed, 10 deletions(-) diff --git a/src/arch/arm/armv7/mmu.c b/src/arch/arm/armv7/mmu.c index e9d10e2a3d..77b9b4b435 100644 --- a/src/arch/arm/armv7/mmu.c +++ b/src/arch/arm/armv7/mmu.c @@ -30,7 +30,6 @@ #include #include -#include #include #include diff --git a/src/arch/arm/cpu.c b/src/arch/arm/cpu.c index 87fc6b17cc..1e0e0fd60b 100644 --- a/src/arch/arm/cpu.c +++ b/src/arch/arm/cpu.c @@ -27,7 +27,6 @@ * SUCH DAMAGE. * */ -#include #include #include diff --git a/src/arch/arm64/armv8/mmu.c b/src/arch/arm64/armv8/mmu.c index 67dca48dbc..bdec55c8c2 100644 --- a/src/arch/arm64/armv8/mmu.c +++ b/src/arch/arm64/armv8/mmu.c @@ -28,7 +28,6 @@ */ #include -#include #include #include #include diff --git a/src/arch/arm64/fit_payload.c b/src/arch/arm64/fit_payload.c index 4ade1c719d..002df44fcc 100644 --- a/src/arch/arm64/fit_payload.c +++ b/src/arch/arm64/fit_payload.c @@ -14,7 +14,6 @@ #include #include -#include #include #include #include diff --git a/src/arch/riscv/fit_payload.c b/src/arch/riscv/fit_payload.c index 78e95fdd83..89263d3fad 100644 --- a/src/arch/riscv/fit_payload.c +++ b/src/arch/riscv/fit_payload.c @@ -16,7 +16,6 @@ #include #include -#include #include #include #include diff --git a/src/arch/x86/acpigen_dsm.c b/src/arch/x86/acpigen_dsm.c index 64cdd7228e..294c6c346b 100644 --- a/src/arch/x86/acpigen_dsm.c +++ b/src/arch/x86/acpigen_dsm.c @@ -13,7 +13,6 @@ #include #include -#include /* ------------------- I2C HID DSM ---------------------------- */ diff --git a/src/arch/x86/cbmem.c b/src/arch/x86/cbmem.c index fc85bc617f..b20eb67b9b 100644 --- a/src/arch/x86/cbmem.c +++ b/src/arch/x86/cbmem.c @@ -11,7 +11,6 @@ * GNU General Public License for more details. */ -#include #include #if CONFIG(CBMEM_TOP_BACKUP) diff --git a/src/arch/x86/include/arch/acpigen.h b/src/arch/x86/include/arch/acpigen.h index 8b8c873fb5..11fe232272 100644 --- a/src/arch/x86/include/arch/acpigen.h +++ b/src/arch/x86/include/arch/acpigen.h @@ -14,7 +14,6 @@ #ifndef LIBACPI_H #define LIBACPI_H -#include #include #include #include diff --git a/src/arch/x86/mmap_boot.c b/src/arch/x86/mmap_boot.c index 762193090b..74764fc4bf 100644 --- a/src/arch/x86/mmap_boot.c +++ b/src/arch/x86/mmap_boot.c @@ -13,7 +13,6 @@ #include #include -#include /* The ROM is memory mapped just below 4GiB. Form a pointer for the base. */ #define rom_base ((void *)(uintptr_t)(0x100000000ULL-CONFIG_ROM_SIZE)) diff --git a/src/arch/x86/smbios.c b/src/arch/x86/smbios.c index a599addb61..8cd4518d13 100644 --- a/src/arch/x86/smbios.c +++ b/src/arch/x86/smbios.c @@ -12,7 +12,6 @@ * GNU General Public License for more details. */ -#include #include #include #include From 88f5c7178ebd1bb4137f495192fffe13bbea1c7c Mon Sep 17 00:00:00 2001 From: Elyes HAOUAS Date: Wed, 16 Oct 2019 12:45:47 +0200 Subject: [PATCH 0767/1242] src: Remove unused 'include ' MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Change-Id: Iaa236f07aed52ccb8c4839047894a14a9446a109 Signed-off-by: Elyes HAOUAS Reviewed-on: https://review.coreboot.org/c/coreboot/+/36080 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki --- src/arch/x86/include/arch/romstage.h | 1 - src/cpu/intel/haswell/bootblock.c | 1 - src/cpu/intel/haswell/haswell.h | 2 +- src/cpu/x86/lapic/apic_timer.c | 1 - src/drivers/amd/agesa/state_machine.c | 1 - src/drivers/intel/fsp1_1/include/fsp/car.h | 1 - src/drivers/intel/fsp1_1/include/fsp/romstage.h | 1 - src/soc/intel/baytrail/include/soc/romstage.h | 1 - src/soc/intel/baytrail/southcluster.c | 1 - src/soc/intel/braswell/acpi.c | 1 - src/soc/intel/broadwell/include/soc/romstage.h | 1 - src/soc/intel/broadwell/lpc.c | 1 - src/soc/intel/denverton_ns/acpi.c | 1 - src/soc/intel/quark/memmap.c | 1 - src/southbridge/intel/bd82x6x/lpc.c | 1 - src/southbridge/intel/ibexpeak/lpc.c | 1 - src/southbridge/intel/lynxpoint/lpc.c | 1 - 17 files changed, 1 insertion(+), 17 deletions(-) diff --git a/src/arch/x86/include/arch/romstage.h b/src/arch/x86/include/arch/romstage.h index 15c93f24bd..86d4e63eda 100644 --- a/src/arch/x86/include/arch/romstage.h +++ b/src/arch/x86/include/arch/romstage.h @@ -14,7 +14,6 @@ #ifndef __ARCH_ROMSTAGE_H__ #define __ARCH_ROMSTAGE_H__ -#include #include #include diff --git a/src/cpu/intel/haswell/bootblock.c b/src/cpu/intel/haswell/bootblock.c index 70a4682175..e05936f59c 100644 --- a/src/cpu/intel/haswell/bootblock.c +++ b/src/cpu/intel/haswell/bootblock.c @@ -12,7 +12,6 @@ */ #include -#include #include #include #include diff --git a/src/cpu/intel/haswell/haswell.h b/src/cpu/intel/haswell/haswell.h index 4c67ba82ab..6ffb7e9a58 100644 --- a/src/cpu/intel/haswell/haswell.h +++ b/src/cpu/intel/haswell/haswell.h @@ -15,7 +15,7 @@ #ifndef _CPU_INTEL_HASWELL_H #define _CPU_INTEL_HASWELL_H -#include +#include /* Haswell CPU types */ #define HASWELL_FAMILY_MOBILE 0x306c0 diff --git a/src/cpu/x86/lapic/apic_timer.c b/src/cpu/x86/lapic/apic_timer.c index 0b3f6910ae..fbe4f08e0b 100644 --- a/src/cpu/x86/lapic/apic_timer.c +++ b/src/cpu/x86/lapic/apic_timer.c @@ -15,7 +15,6 @@ #include #include #include -#include #include #include diff --git a/src/drivers/amd/agesa/state_machine.c b/src/drivers/amd/agesa/state_machine.c index a7255ae44a..482b615c9c 100644 --- a/src/drivers/amd/agesa/state_machine.c +++ b/src/drivers/amd/agesa/state_machine.c @@ -14,7 +14,6 @@ #include #include #include -#include #include #include #include diff --git a/src/drivers/intel/fsp1_1/include/fsp/car.h b/src/drivers/intel/fsp1_1/include/fsp/car.h index 84f2fd841c..461f8463bc 100644 --- a/src/drivers/intel/fsp1_1/include/fsp/car.h +++ b/src/drivers/intel/fsp1_1/include/fsp/car.h @@ -14,7 +14,6 @@ #ifndef FSP1_1_CAR_H #define FSP1_1_CAR_H -#include #include #include diff --git a/src/drivers/intel/fsp1_1/include/fsp/romstage.h b/src/drivers/intel/fsp1_1/include/fsp/romstage.h index ac8247c845..bee49cf8ad 100644 --- a/src/drivers/intel/fsp1_1/include/fsp/romstage.h +++ b/src/drivers/intel/fsp1_1/include/fsp/romstage.h @@ -16,7 +16,6 @@ #include #include -#include #include #include #include diff --git a/src/soc/intel/baytrail/include/soc/romstage.h b/src/soc/intel/baytrail/include/soc/romstage.h index 16f80b4a4f..ac323058f1 100644 --- a/src/soc/intel/baytrail/include/soc/romstage.h +++ b/src/soc/intel/baytrail/include/soc/romstage.h @@ -17,7 +17,6 @@ #define _BAYTRAIL_ROMSTAGE_H_ #include -#include #include void mainboard_fill_mrc_params(struct mrc_params *mp); diff --git a/src/soc/intel/baytrail/southcluster.c b/src/soc/intel/baytrail/southcluster.c index 55bef11909..bd61f0821d 100644 --- a/src/soc/intel/baytrail/southcluster.c +++ b/src/soc/intel/baytrail/southcluster.c @@ -20,7 +20,6 @@ #include #include #include -#include #include #include #include diff --git a/src/soc/intel/braswell/acpi.c b/src/soc/intel/braswell/acpi.c index dbd29503c7..f68b7ce2da 100644 --- a/src/soc/intel/braswell/acpi.c +++ b/src/soc/intel/braswell/acpi.c @@ -18,7 +18,6 @@ #include #include -#include #include #include #include diff --git a/src/soc/intel/broadwell/include/soc/romstage.h b/src/soc/intel/broadwell/include/soc/romstage.h index cd37cf6316..7d0270fd05 100644 --- a/src/soc/intel/broadwell/include/soc/romstage.h +++ b/src/soc/intel/broadwell/include/soc/romstage.h @@ -17,7 +17,6 @@ #define _BROADWELL_ROMSTAGE_H_ #include -#include #include struct chipset_power_state; diff --git a/src/soc/intel/broadwell/lpc.c b/src/soc/intel/broadwell/lpc.c index 3392614303..007b56b515 100644 --- a/src/soc/intel/broadwell/lpc.c +++ b/src/soc/intel/broadwell/lpc.c @@ -21,7 +21,6 @@ #include #include #include -#include #include #include #include diff --git a/src/soc/intel/denverton_ns/acpi.c b/src/soc/intel/denverton_ns/acpi.c index 48b67b089d..163f76a4a6 100644 --- a/src/soc/intel/denverton_ns/acpi.c +++ b/src/soc/intel/denverton_ns/acpi.c @@ -19,7 +19,6 @@ #include #include -#include #include #include #include diff --git a/src/soc/intel/quark/memmap.c b/src/soc/intel/quark/memmap.c index 6cd2c9a73c..aeba5182c2 100644 --- a/src/soc/intel/quark/memmap.c +++ b/src/soc/intel/quark/memmap.c @@ -13,7 +13,6 @@ * GNU General Public License for more details. */ -#include #include #include #include diff --git a/src/southbridge/intel/bd82x6x/lpc.c b/src/southbridge/intel/bd82x6x/lpc.c index e7b7db86d8..ef66ca512a 100644 --- a/src/southbridge/intel/bd82x6x/lpc.c +++ b/src/southbridge/intel/bd82x6x/lpc.c @@ -26,7 +26,6 @@ #include #include #include -#include #include #include #include diff --git a/src/southbridge/intel/ibexpeak/lpc.c b/src/southbridge/intel/ibexpeak/lpc.c index 2b48eab5b0..324438ec6b 100644 --- a/src/southbridge/intel/ibexpeak/lpc.c +++ b/src/southbridge/intel/ibexpeak/lpc.c @@ -27,7 +27,6 @@ #include #include #include -#include #include #include #include diff --git a/src/southbridge/intel/lynxpoint/lpc.c b/src/southbridge/intel/lynxpoint/lpc.c index c8e91c35a9..62d8aa6385 100644 --- a/src/southbridge/intel/lynxpoint/lpc.c +++ b/src/southbridge/intel/lynxpoint/lpc.c @@ -26,7 +26,6 @@ #include #include #include -#include #include #include #include From 9a5fc849fda7c2e5e6a57c3ed6bd8483269b3dfb Mon Sep 17 00:00:00 2001 From: Elyes HAOUAS Date: Sat, 30 Nov 2019 19:55:05 +0100 Subject: [PATCH 0768/1242] mb/lenovo/g505s: Remove unused MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Change-Id: I6af1d44f9a05c153b6a355318a39adc9a3d6c0c9 Signed-off-by: Elyes HAOUAS Reviewed-on: https://review.coreboot.org/c/coreboot/+/33901 Reviewed-by: Werner Zeh Reviewed-by: Kyösti Mälkki Tested-by: build bot (Jenkins) --- src/mainboard/lenovo/g505s/BiosCallOuts.c | 1 - src/mainboard/lenovo/g505s/buildOpts.c | 1 - 2 files changed, 2 deletions(-) diff --git a/src/mainboard/lenovo/g505s/BiosCallOuts.c b/src/mainboard/lenovo/g505s/BiosCallOuts.c index 2b1ac04159..f36e11efec 100644 --- a/src/mainboard/lenovo/g505s/BiosCallOuts.c +++ b/src/mainboard/lenovo/g505s/BiosCallOuts.c @@ -19,7 +19,6 @@ #include #include -#include const BIOS_CALLOUT_STRUCT BiosCallouts[] = { diff --git a/src/mainboard/lenovo/g505s/buildOpts.c b/src/mainboard/lenovo/g505s/buildOpts.c index c3e40ce16f..3adf20d99d 100644 --- a/src/mainboard/lenovo/g505s/buildOpts.c +++ b/src/mainboard/lenovo/g505s/buildOpts.c @@ -27,7 +27,6 @@ #include "mainboard.h" -#include #include From bd3037bfa70e2a0ccc1e7a7c89353bcb6491d527 Mon Sep 17 00:00:00 2001 From: Kangheui Won Date: Wed, 18 Dec 2019 12:22:43 -0800 Subject: [PATCH 0769/1242] mainboard/google/puff: enable emmc enable eMMC in puff/overridetree.cb BRANCH=none BUG=b:146455177 TEST=./util/abuild/abuild -p none -t google/hatch -x -a Change-Id: I432f437e0c9a618bbbf76d22976ea757c8fbdb83 Signed-off-by: Kangheui Won Reviewed-on: https://review.coreboot.org/c/coreboot/+/37817 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan --- .../hatch/variants/puff/overridetree.cb | 49 +++++++++++++++++++ 1 file changed, 49 insertions(+) diff --git a/src/mainboard/google/hatch/variants/puff/overridetree.cb b/src/mainboard/google/hatch/variants/puff/overridetree.cb index d5e2e5afb5..384bb9a6d0 100644 --- a/src/mainboard/google/hatch/variants/puff/overridetree.cb +++ b/src/mainboard/google/hatch/variants/puff/overridetree.cb @@ -15,6 +15,54 @@ chip soc/intel/cannonlake [PchSerialIoIndexUART2] = PchSerialIoDisabled, }" + # Enable eMMC HS400 + register "ScsEmmcHs400Enabled" = "1" + + # EMMC Tx CMD Delay + # Refer to EDS-Vol2-14.3.7. + # [14:8] steps of delay for DDR mode, each 125ps, range: 0 - 39. + # [6:0] steps of delay for SDR mode, each 125ps, range: 0 - 39. + register "common_soc_config.emmc_dll.emmc_tx_cmd_cntl" = "0x505" + + # EMMC TX DATA Delay 1 + # Refer to EDS-Vol2-14.3.8. + # [14:8] steps of delay for HS400, each 125ps, range: 0 - 78. + # [6:0] steps of delay for SDR104/HS200, each 125ps, range: 0 - 79. + register "common_soc_config.emmc_dll.emmc_tx_data_cntl1" = "0x911" + + # EMMC TX DATA Delay 2 + # Refer to EDS-Vol2-14.3.9. + # [30:24] steps of delay for SDR50, each 125ps, range: 0 - 79. + # [22:16] steps of delay for DDR50, each 125ps, range: 0 - 78. + # [14:8] steps of delay for SDR25/HS50, each 125ps, range: 0 -79. + # [6:0] steps of delay for SDR12, each 125ps. Range: 0 - 79. + register "common_soc_config.emmc_dll.emmc_tx_data_cntl2" = "0x1C262828" + + # EMMC RX CMD/DATA Delay 1 + # Refer to EDS-Vol2-14.3.10. + # [30:24] steps of delay for SDR50, each 125ps, range: 0 - 119. + # [22:16] steps of delay for DDR50, each 125ps, range: 0 - 78. + # [14:8] steps of delay for SDR25/HS50, each 125ps, range: 0 - 119. + # [6:0] steps of delay for SDR12, each 125ps, range: 0 - 119. + register "common_soc_config.emmc_dll.emmc_rx_cmd_data_cntl1" = "0x1C16583b" + + # EMMC RX CMD/DATA Delay 2 + # Refer to EDS-Vol2-14.3.12. + # [17:16] stands for Rx Clock before Output Buffer, + # 00: Rx clock after output buffer, + # 01: Rx clock before output buffer, + # 10: Automatic selection based on working mode. + # 11: Reserved + # [14:8] steps of delay for Auto Tuning Mode, each 125ps, range: 0 - 39. + # [6:0] steps of delay for HS200, each 125ps, range: 0 - 79. + register "common_soc_config.emmc_dll.emmc_rx_cmd_data_cntl2" = "0x1001D" + + # EMMC Rx Strobe Delay + # Refer to EDS-Vol2-14.3.11. + # [14:8] Rx Strobe Delay DLL 1(HS400 Mode), each 125ps, range: 0 - 39. + # [6:0] Rx Strobe Delay DLL 2(HS400 Mode), each 125ps, range: 0 - 39. + register "common_soc_config.emmc_dll.emmc_rx_strobe_cntl" = "0x1515" + # Intel Common SoC Config #+-------------------+---------------------------+ #| Field | Value | @@ -94,6 +142,7 @@ chip soc/intel/cannonlake device i2c 1a on end end end #I2C #4 + device pci 1a.0 on end # eMMC device pci 1e.3 off end # GSPI #1 end From f82fa746bf9f5e07919f19563a9a0f2e136e40fe Mon Sep 17 00:00:00 2001 From: Bob Moragues Date: Fri, 6 Dec 2019 14:20:00 -0800 Subject: [PATCH 0770/1242] mb/google/hatch: Add mushu variant Create initial overlays and build for mushu Signed-off-by: Bob Moragues Change-Id: I81b5bf960ead0463159ac35f4f96e3ccc8c0364e Reviewed-on: https://review.coreboot.org/c/coreboot/+/37645 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh --- src/mainboard/google/hatch/Kconfig | 2 + src/mainboard/google/hatch/Kconfig.name | 5 + .../google/hatch/variants/mushu/Makefile.inc | 23 +++ .../google/hatch/variants/mushu/gpio.c | 69 +++++++ .../mushu/include/variant/acpi/dptf.asl | 16 ++ .../hatch/variants/mushu/include/variant/ec.h | 21 ++ .../variants/mushu/include/variant/gpio.h | 27 +++ .../hatch/variants/mushu/overridetree.cb | 181 ++++++++++++++++++ 8 files changed, 344 insertions(+) create mode 100644 src/mainboard/google/hatch/variants/mushu/Makefile.inc create mode 100644 src/mainboard/google/hatch/variants/mushu/gpio.c create mode 100644 src/mainboard/google/hatch/variants/mushu/include/variant/acpi/dptf.asl create mode 100644 src/mainboard/google/hatch/variants/mushu/include/variant/ec.h create mode 100644 src/mainboard/google/hatch/variants/mushu/include/variant/gpio.h create mode 100644 src/mainboard/google/hatch/variants/mushu/overridetree.cb diff --git a/src/mainboard/google/hatch/Kconfig b/src/mainboard/google/hatch/Kconfig index dff5273714..90c5ed3427 100644 --- a/src/mainboard/google/hatch/Kconfig +++ b/src/mainboard/google/hatch/Kconfig @@ -95,6 +95,7 @@ config MAINBOARD_PART_NUMBER default "Jinlon" if BOARD_GOOGLE_JINLON default "Kindred" if BOARD_GOOGLE_KINDRED default "Kohaku" if BOARD_GOOGLE_KOHAKU + default "Mushu" if BOARD_GOOGLE_MUSHU default "Puff" if BOARD_GOOGLE_PUFF default "Stryke" if BOARD_GOOGLE_STRYKE @@ -117,6 +118,7 @@ config VARIANT_DIR default "jinlon" if BOARD_GOOGLE_JINLON default "kindred" if BOARD_GOOGLE_KINDRED default "kohaku" if BOARD_GOOGLE_KOHAKU + default "mushu" if BOARD_GOOGLE_MUSHU default "puff" if BOARD_GOOGLE_PUFF default "stryke" if BOARD_GOOGLE_STRYKE diff --git a/src/mainboard/google/hatch/Kconfig.name b/src/mainboard/google/hatch/Kconfig.name index ed90de6c34..e216135419 100644 --- a/src/mainboard/google/hatch/Kconfig.name +++ b/src/mainboard/google/hatch/Kconfig.name @@ -38,6 +38,11 @@ config BOARD_GOOGLE_HELIOS select CHROMEOS_DSM_CALIB select DRIVERS_I2C_RT1011 +config BOARD_GOOGLE_MUSHU + bool "-> Mushu" + select BOARD_GOOGLE_BASEBOARD_HATCH + select BOARD_ROMSIZE_KB_16384 + config BOARD_GOOGLE_PUFF bool "-> Puff" select BOARD_GOOGLE_BASEBOARD_HATCH diff --git a/src/mainboard/google/hatch/variants/mushu/Makefile.inc b/src/mainboard/google/hatch/variants/mushu/Makefile.inc new file mode 100644 index 0000000000..a990b5ad05 --- /dev/null +++ b/src/mainboard/google/hatch/variants/mushu/Makefile.inc @@ -0,0 +1,23 @@ +## This file is part of the coreboot project. +## +## Copyright 2019 Google LLC +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +SPD_SOURCES = 4G_2400 # 0b000 +SPD_SOURCES += empty_ddr4 # 0b001 +SPD_SOURCES += 8G_2400 # 0b010 +SPD_SOURCES += 8G_2666 # 0b011 +SPD_SOURCES += 16G_2400 # 0b100 +SPD_SOURCES += 16G_2666 # 0b101 + +ramstage-y += gpio.c +bootblock-y += gpio.c diff --git a/src/mainboard/google/hatch/variants/mushu/gpio.c b/src/mainboard/google/hatch/variants/mushu/gpio.c new file mode 100644 index 0000000000..56f587b6b8 --- /dev/null +++ b/src/mainboard/google/hatch/variants/mushu/gpio.c @@ -0,0 +1,69 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2019 Google LLC + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the + * GNU General Public License for more details. + */ + +#include +#include +#include +#include + +static const struct pad_config gpio_table[] = { + /* C13 : EC_PCH_INT_L */ + PAD_CFG_GPI_APIC(GPP_C13, UP_20K, PLTRST, LEVEL, INVERT)}; + +const struct pad_config *override_gpio_table(size_t *num) +{ + *num = ARRAY_SIZE(gpio_table); + return gpio_table; +} + +/* + * GPIOs configured before ramstage + * Note: the Hatch platform's romstage will configure + * the MEM_STRAP_* (a.k.a GPIO_MEM_CONFIG_*) pins + * as inputs before it reads them, so they are not + * needed in this table. + */ +static const struct pad_config early_gpio_table[] = { + /* A12 : FPMCU_RST_ODL */ + PAD_CFG_GPO(GPP_A12, 0, DEEP), + /* B15 : H1_SLAVE_SPI_CS_L */ + PAD_CFG_NF(GPP_B15, NONE, DEEP, NF1), + /* B16 : H1_SLAVE_SPI_CLK */ + PAD_CFG_NF(GPP_B16, NONE, DEEP, NF1), + /* B17 : H1_SLAVE_SPI_MISO_R */ + PAD_CFG_NF(GPP_B17, NONE, DEEP, NF1), + /* B18 : H1_SLAVE_SPI_MOSI_R */ + PAD_CFG_NF(GPP_B18, NONE, DEEP, NF1), + /* C14 : BT_DISABLE_L */ + PAD_CFG_GPO(GPP_C14, 0, DEEP), + /* PCH_WP_OD */ + PAD_CFG_GPI(GPP_C20, NONE, DEEP), + /* C21 : H1_PCH_INT_ODL */ + PAD_CFG_GPI_APIC(GPP_C21, NONE, PLTRST, LEVEL, INVERT), + /* C23 : WLAN_PE_RST# */ + PAD_CFG_GPO(GPP_C23, 1, DEEP), + /* E1 : M2_SSD_PEDET */ + PAD_CFG_NF(GPP_E1, NONE, DEEP, NF1), + /* E5 : SATA_DEVSLP1 */ + PAD_CFG_NF(GPP_E5, NONE, PLTRST, NF1), + /* F2 : MEM_CH_SEL */ + PAD_CFG_GPI(GPP_F2, NONE, PLTRST), +}; + +const struct pad_config *variant_early_gpio_table(size_t *num) +{ + *num = ARRAY_SIZE(early_gpio_table); + return early_gpio_table; +} diff --git a/src/mainboard/google/hatch/variants/mushu/include/variant/acpi/dptf.asl b/src/mainboard/google/hatch/variants/mushu/include/variant/acpi/dptf.asl new file mode 100644 index 0000000000..31f72b3f03 --- /dev/null +++ b/src/mainboard/google/hatch/variants/mushu/include/variant/acpi/dptf.asl @@ -0,0 +1,16 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include diff --git a/src/mainboard/google/hatch/variants/mushu/include/variant/ec.h b/src/mainboard/google/hatch/variants/mushu/include/variant/ec.h new file mode 100644 index 0000000000..768987d225 --- /dev/null +++ b/src/mainboard/google/hatch/variants/mushu/include/variant/ec.h @@ -0,0 +1,21 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2019 Google LLC + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef VARIANT_EC_H +#define VARIANT_EC_H + +#include + +#endif diff --git a/src/mainboard/google/hatch/variants/mushu/include/variant/gpio.h b/src/mainboard/google/hatch/variants/mushu/include/variant/gpio.h new file mode 100644 index 0000000000..29e590422f --- /dev/null +++ b/src/mainboard/google/hatch/variants/mushu/include/variant/gpio.h @@ -0,0 +1,27 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2019 Google LLC + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the + * GNU General Public License for more details. + */ + +#ifndef VARIANT_GPIO_H +#define VARIANT_GPIO_H + +#include + +/* Memory configuration board straps */ +#define GPIO_MEM_CONFIG_0 GPP_F20 +#define GPIO_MEM_CONFIG_1 GPP_F21 +#define GPIO_MEM_CONFIG_2 GPP_F11 +#define GPIO_MEM_CONFIG_3 GPP_F22 + +#endif diff --git a/src/mainboard/google/hatch/variants/mushu/overridetree.cb b/src/mainboard/google/hatch/variants/mushu/overridetree.cb new file mode 100644 index 0000000000..75c14efad5 --- /dev/null +++ b/src/mainboard/google/hatch/variants/mushu/overridetree.cb @@ -0,0 +1,181 @@ +chip soc/intel/cannonlake + + register "SerialIoDevMode" = "{ + [PchSerialIoIndexI2C0] = PchSerialIoPci, + [PchSerialIoIndexI2C1] = PchSerialIoPci, + [PchSerialIoIndexI2C2] = PchSerialIoPci, + [PchSerialIoIndexI2C3] = PchSerialIoPci, + [PchSerialIoIndexI2C4] = PchSerialIoPci, + [PchSerialIoIndexI2C5] = PchSerialIoPci, + [PchSerialIoIndexSPI0] = PchSerialIoPci, + [PchSerialIoIndexSPI1] = PchSerialIoPci, + [PchSerialIoIndexSPI2] = PchSerialIoDisabled, + [PchSerialIoIndexUART0] = PchSerialIoSkipInit, + [PchSerialIoIndexUART1] = PchSerialIoDisabled, + [PchSerialIoIndexUART2] = PchSerialIoDisabled, + }" + + # VR Slew rate setting + register "AcousticNoiseMitigation" = "1" + register "SlowSlewRateForIa" = "2" + register "SlowSlewRateForGt" = "2" + register "SlowSlewRateForSa" = "2" + register "FastPkgCRampDisableIa" = "1" + register "FastPkgCRampDisableGt" = "1" + register "FastPkgCRampDisableSa" = "1" + + # Intel Common SoC Config + #+-------------------+---------------------------+ + #| Field | Value | + #+-------------------+---------------------------+ + #| GSPI0 | cr50 TPM. Early init is | + #| | required to set up a BAR | + #| | for TPM communication | + #| | before memory is up | + #| GSPI1 | FP MCU | + #| I2C0 | Touchpad | + #| I2C1 | Touch screen | + #| I2C4 | Audio | + #+-------------------+---------------------------+ + register "common_soc_config" = "{ + .gspi[0] = { + .speed_mhz = 1, + .early_init = 1, + }, + .i2c[0] = { + .speed = I2C_SPEED_FAST, + .rise_time_ns = 50, + .fall_time_ns = 15, + }, + .i2c[1] = { + .speed = I2C_SPEED_FAST, + .rise_time_ns = 60, + .fall_time_ns = 25, + }, + .i2c[3] = { + .speed = I2C_SPEED_FAST, + .rise_time_ns = 150, + .fall_time_ns = 150, + }, + .i2c[4] = { + .speed = I2C_SPEED_FAST, + .rise_time_ns = 120, + .fall_time_ns = 120, + }, + }" + + # GPIO for SD card detect + register "sdcard_cd_gpio" = "vSD3_CD_B" + + device domain 0 on + device pci 15.0 on + chip drivers/i2c/generic + register "hid" = ""ELAN0000"" + register "desc" = ""ELAN Touchpad"" + register "irq" = "ACPI_IRQ_WAKE_EDGE_LOW(GPP_A21_IRQ)" + register "wake" = "GPE0_DW0_21" + device i2c 15 on end + end + end # I2C #0 + device pci 15.1 on + chip drivers/i2c/generic + register "hid" = ""ELAN0001"" + register "desc" = ""ELAN Touchscreen"" + register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_D16_IRQ)" + register "probed" = "1" + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D15)" + register "reset_delay_ms" = "100" + register "reset_off_delay_ms" = "5" + register "has_power_resource" = "1" + register "stop_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C4)" + register "stop_off_delay_ms" = "5" + device i2c 49 on end + end + chip drivers/i2c/hid + register "generic.hid" = ""GDIX0000"" + register "generic.desc" = ""Goodix Touchscreen"" + register "generic.irq" = "ACPI_IRQ_EDGE_LOW(GPP_D16_IRQ)" + register "generic.probed" = "1" + register "generic.reset_gpio" = + "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D15)" + register "generic.reset_delay_ms" = "120" + register "generic.reset_off_delay_ms" = "3" + register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D9)" + register "generic.enable_delay_ms" = "12" + register "generic.has_power_resource" = "1" + register "hid_desc_reg_offset" = "0x01" + device i2c 5d on end + end + chip drivers/generic/gpio_keys + register "name" = ""PENH"" + register "gpio" = "ACPI_GPIO_IRQ_EDGE_BOTH(GPP_A8)" + register "key.wake" = "GPE0_DW0_08" + register "key.wakeup_event_action" = "EV_ACT_DEASSERTED" + register "key.dev_name" = ""EJCT"" + register "key.linux_code" = "SW_PEN_INSERTED" + register "key.linux_input_type" = "EV_SW" + register "key.label" = ""pen_eject"" + device generic 0 on end + end + end # I2C #1 + device pci 15.2 off end # I2C #2 + device pci 15.3 on + chip drivers/i2c/sx9310 + register "desc" = ""SAR Proximity Sensor"" + register "irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW(GPP_A0)" + register "speed" = "I2C_SPEED_FAST" + register "uid" = "1" + register "reg_prox_ctrl0" = "0x10" + register "reg_prox_ctrl1" = "0x00" + register "reg_prox_ctrl2" = "0x84" + register "reg_prox_ctrl3" = "0x0e" + register "reg_prox_ctrl4" = "0x07" + register "reg_prox_ctrl5" = "0xc6" + register "reg_prox_ctrl6" = "0x20" + register "reg_prox_ctrl7" = "0x0d" + register "reg_prox_ctrl8" = "0x8d" + register "reg_prox_ctrl9" = "0x43" + register "reg_prox_ctrl10" = "0x1f" + register "reg_prox_ctrl11" = "0x00" + register "reg_prox_ctrl12" = "0x00" + register "reg_prox_ctrl13" = "0x00" + register "reg_prox_ctrl14" = "0x00" + register "reg_prox_ctrl15" = "0x00" + register "reg_prox_ctrl16" = "0x00" + register "reg_prox_ctrl17" = "0x00" + register "reg_prox_ctrl18" = "0x00" + register "reg_prox_ctrl19" = "0x00" + register "reg_sar_ctrl0" = "0x50" + register "reg_sar_ctrl1" = "0x8a" + register "reg_sar_ctrl2" = "0x3c" + device i2c 28 on end + end + end # I2C #3 + device pci 19.0 on + chip drivers/i2c/generic + register "hid" = ""10EC5682"" + register "name" = ""RT58"" + register "desc" = ""Realtek RT5682"" + register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_BOTH(GPP_H0)" + register "property_count" = "1" + # Set the jd_src to RT5668_JD1 for jack detection + register "property_list[0].type" = "ACPI_DP_TYPE_INTEGER" + register "property_list[0].name" = ""realtek,jd-src"" + register "property_list[0].integer" = "1" + device i2c 1a on end + end + end #I2C #4 + device pci 1e.3 on + chip drivers/spi/acpi + register "name" = ""CRFP"" + register "hid" = "ACPI_DT_NAMESPACE_HID" + register "uid" = "1" + register "compat_string" = ""google,cros-ec-spi"" + register "irq" = "ACPI_IRQ_WAKE_LEVEL_LOW(GPP_A23_IRQ)" + register "wake" = "GPE0_DW0_23" + device spi 1 on end + end # FPMCU + end # GSPI #1 + end + +end From 629abbe7515cf9cd3b50d689c2fce3385805fc0d Mon Sep 17 00:00:00 2001 From: Eric Lai Date: Tue, 17 Dec 2019 15:35:06 +0800 Subject: [PATCH 0771/1242] mb/google/drallion: Remove Wilco 1.0 CML code from drallion code Drallion supports D3 hot not D3 cold. Remove the code which used for Wilco 1.0 CML. BUG=b:140068267 TEST=boot into OS without any issues BRANCH=none Signed-off-by: Eric Lai Change-Id: Ifc83fae7ac462d3e6595742d96952c2a2607c88b Reviewed-on: https://review.coreboot.org/c/coreboot/+/37779 Tested-by: build bot (Jenkins) Reviewed-by: Mathew King Reviewed-by: Mike Wiitala --- src/mainboard/google/drallion/ramstage.c | 11 ----------- .../google/drallion/variants/drallion/gpio.c | 10 ++++------ 2 files changed, 4 insertions(+), 17 deletions(-) diff --git a/src/mainboard/google/drallion/ramstage.c b/src/mainboard/google/drallion/ramstage.c index 6d3ebb46cb..385504522f 100644 --- a/src/mainboard/google/drallion/ramstage.c +++ b/src/mainboard/google/drallion/ramstage.c @@ -59,13 +59,6 @@ void smbios_fill_dimm_locator(const struct dimm_info *dimm, } } -static const struct pad_config gpio_unused[] = { -/* SUSWARN# */ PAD_NC(GPP_A13, NONE), -/* SUSACK# */ PAD_NC(GPP_A15, NONE), -/* M2_SKT2_CFG0 */ PAD_NC(GPP_H12, NONE), -/* M2_SKT2_CFG1 */ PAD_NC(GPP_H13, NONE), -}; - static void mainboard_init(void *chip_info) { const struct pad_config *gpio_table; @@ -73,10 +66,6 @@ static void mainboard_init(void *chip_info) gpio_table = variant_gpio_table(&num_gpios); cnl_configure_pads(gpio_table, num_gpios); - - /* Disable unused pads for devices with board ID > 2 */ - if (board_id() > 2) - gpio_configure_pads(gpio_unused, ARRAY_SIZE(gpio_unused)); } static void mainboard_enable(struct device *dev) diff --git a/src/mainboard/google/drallion/variants/drallion/gpio.c b/src/mainboard/google/drallion/variants/drallion/gpio.c index 086dca0265..f2b70792f7 100644 --- a/src/mainboard/google/drallion/variants/drallion/gpio.c +++ b/src/mainboard/google/drallion/variants/drallion/gpio.c @@ -36,9 +36,9 @@ static const struct pad_config gpio_table[] = { /* PME# */ PAD_NC(GPP_A11, NONE), /* ISH_LID_CL#_TAB */ /* ISH_GP6 */ PAD_CFG_NF(GPP_A12, NONE, DEEP, NF2), -/* SUSWARN# */ PAD_CFG_GPO(GPP_A13, 0, DEEP), +/* SUSWARN# */ PAD_NC(GPP_A13, NONE), /* ESPI_RESET# */ -/* SUSACK# */ PAD_CFG_GPO(GPP_A15, 0, DEEP), +/* SUSACK# */ PAD_NC(GPP_A15, NONE), /* SD_1P8_SEL */ PAD_CFG_GPI(GPP_A16, NONE, PLTRST), /* 2.7MM_CAM_DET# */ /* SD_PWR_EN# */ PAD_NC(GPP_A17, NONE), /* ISH_ACC1_INT# */ @@ -200,6 +200,8 @@ static const struct pad_config gpio_table[] = { /* I2C4_SCL */ PAD_CFG_NF(GPP_H9, NONE, DEEP, NF1), /* I2C5_SDA */ PAD_NC(GPP_H10, NONE), /* ISH_I2C2_SDA */ /* I2C5_SCL */ PAD_NC(GPP_H11, NONE), /* ISH_I2C2_SCL */ +/* M2_SKT2_CFG0 */ PAD_NC(GPP_H12, NONE), +/* M2_SKT2_CFG1 */ PAD_NC(GPP_H13, NONE), /* M2_SKT2_CFG2 */ PAD_NC(GPP_H14, NONE), /* M2_SKT2_CFG3 */ PAD_CFG_GPO(GPP_H15, 1, DEEP), /* BT_RADIO_DIS# */ /* DDPF_CTRLCLK */ PAD_NC(GPP_H16, NONE), @@ -226,9 +228,6 @@ static const struct pad_config gpio_table[] = { /* Early pad configuration in bootblock */ static const struct pad_config early_gpio_table[] = { -/* M2_SKT2_CFG1 */ PAD_CFG_GPO(GPP_H13, 1, DEEP), /* M.2 SSD D3 cold */ -/* SSD RESET pin will stay low first */ -/* M2_SKT2_CFG0 */ PAD_CFG_GPO(GPP_H12, 0, DEEP), /* D3 cold RST */ /* UART2_RXD */ PAD_CFG_NF(GPP_C8, NONE, DEEP, NF1), /* SERVOTX_UART */ /* UART2_TXD */ PAD_CFG_NF(GPP_C9, NONE, DEEP, NF1), /* SERVORX_UART */ /* I2C4_SDA */ PAD_CFG_NF(GPP_H8, NONE, DEEP, NF1), /* SDA_PCH_H1 */ @@ -240,7 +239,6 @@ static const struct pad_config early_gpio_table[] = { /* CPU_GP0 */ PAD_CFG_GPI(GPP_E3, NONE, DEEP), /* MEM_INTERLEAVED */ /* SATALED# */ PAD_CFG_GPI(GPP_E8, NONE, DEEP), /* RECOVERY# */ /* DDPD_HPD2 */ PAD_CFG_GPI(GPP_E15, NONE, DEEP), /* PCH_WP */ -/* M2_SKT2_CFG0 */ PAD_CFG_GPO(GPP_H12, 1, DEEP), /* D3 cold RST */ /* GPP_F1 */ PAD_CFG_GPI(GPP_F1, NONE, DEEP), /* DDR_CHA_EN_1P8 */ /* GPP_F2 */ PAD_CFG_GPI(GPP_F2, NONE, DEEP), /* DDR_CHB_EN_1P8 */ /* EMMC_DATA0 */ PAD_CFG_GPI(GPP_F12, NONE, DEEP), /* MEM_CONFIGO_1P8 */ From 25eb1b3149ccb3f1f0599b9bc05c5b5f196d303d Mon Sep 17 00:00:00 2001 From: Eric Lai Date: Tue, 17 Dec 2019 16:09:26 +0800 Subject: [PATCH 0772/1242] mb/google/drallion: Clean up unused weak function Drallion only supports on board dimm. Remove the spd read from SMBus. Since CB:37678 remove the Wilco 1.0 CML variants, weak function is not needed. BUG=b:140068267 TEST=boot into OS without issue BRANCH=none Signed-off-by: Eric Lai Change-Id: I662f87ccf48ba470998fa28fb14c9985673cb37d Reviewed-on: https://review.coreboot.org/c/coreboot/+/37780 Reviewed-by: Mathew King Tested-by: build bot (Jenkins) --- src/mainboard/google/drallion/romstage.c | 45 ------------------------ 1 file changed, 45 deletions(-) diff --git a/src/mainboard/google/drallion/romstage.c b/src/mainboard/google/drallion/romstage.c index 03bc17f185..ed9923f990 100644 --- a/src/mainboard/google/drallion/romstage.c +++ b/src/mainboard/google/drallion/romstage.c @@ -18,51 +18,6 @@ #include #include -void __weak variant_mainboard_post_init_params(FSPM_UPD *mupd) {} - -static const struct cnl_mb_cfg memcfg = { - /* Access memory info through SMBUS. */ - .spd[0] = { - .read_type = READ_SMBUS, - .spd_spec = {.spd_smbus_address = 0xa0}, - }, - .spd[1] = {.read_type = NOT_EXISTING}, - .spd[2] = { - .read_type = READ_SMBUS, - .spd_spec = {.spd_smbus_address = 0xa4}, - }, - .spd[3] = {.read_type = NOT_EXISTING}, - - /* - * The dqs_map arrays map the ddr4 pins to the SoC pins - * for both channels. - * - * the index = pin number on ddr4 part - * the value = pin number on SoC - */ - .dqs_map[DDR_CH0] = {0, 1, 4, 5, 2, 3, 6, 7}, - .dqs_map[DDR_CH1] = {0, 1, 4, 5, 2, 3, 6, 7}, - - /* Baseboard uses 121, 81 and 100 rcomp resistors */ - .rcomp_resistor = {121, 81, 100}, - - /* - * Baseboard Rcomp target values. - */ - .rcomp_targets = {100, 40, 20, 20, 26}, - - /* Disable Early Command Training */ - .ect = 0, - - /* Base on board design */ - .vref_ca_config = 2, -}; - -const struct cnl_mb_cfg * __weak get_variant_memory_cfg(struct cnl_mb_cfg *mem_cfg) -{ - return &memcfg; -} - void mainboard_memory_init_params(FSPM_UPD *memupd) { struct cnl_mb_cfg board_memcfg; From 3280b7672907cd70609f90010a653fa47b4e7c85 Mon Sep 17 00:00:00 2001 From: Bora Guvendik Date: Mon, 16 Dec 2019 16:51:38 -0800 Subject: [PATCH 0773/1242] storage/mmc: Fix wrong frequency setting for HS speed mode MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Emmc spec, JEDEC Standard No. 84-B51, section 6.6.2.3, selection flow of HS400 using Enhanced Strobe states that host should change frequency to ≤ 52MHz when switching to HS speed mode first. In current code, mmc_select_hs400() calls mmc_select_hs() to do this, however caps are not cleared, so when switching from HS200 to HS400, caps will still have DRVR_CAP_HS200, and mmc_recalculate_clock() will set 200Mhz instead of ≤ 52MHz. As a result, switching to HS400 will intermittently fail. BUG=b:140124451 TEST=Switch speed from HS200 to HS400 on WHL RVP. Change-Id: Ie639c7616105cca638417d7bc1db95b561afb7af Signed-off-by: Bora Guvendik Reviewed-on: https://review.coreboot.org/c/coreboot/+/37775 Reviewed-by: Selma Bensaid Reviewed-by: Subrata Banik Tested-by: build bot (Jenkins) --- src/commonlib/storage/mmc.c | 1 + 1 file changed, 1 insertion(+) diff --git a/src/commonlib/storage/mmc.c b/src/commonlib/storage/mmc.c index 0b682adc89..1e0f7d20f0 100644 --- a/src/commonlib/storage/mmc.c +++ b/src/commonlib/storage/mmc.c @@ -186,6 +186,7 @@ static int mmc_select_hs(struct storage_media *media) /* Increase the controller clock speed */ SET_TIMING(media->ctrlr, BUS_TIMING_MMC_HS); + media->caps &= ~(DRVR_CAP_HS200 | DRVR_CAP_HS400); media->caps |= DRVR_CAP_HS52 | DRVR_CAP_HS; mmc_recalculate_clock(media); ret = sd_mmc_send_status(media, SD_MMC_IO_RETRIES); From b9e84483848d03e0085f5eee1c20fc3932f52e3d Mon Sep 17 00:00:00 2001 From: Johnny Lin Date: Mon, 2 Dec 2019 19:44:04 +0800 Subject: [PATCH 0774/1242] drivers/ipmi: Add IPMI Read FRU function Implemented according to IPMI "Platform Management FRU Information Storage Definition" specification v1.0 for reading FRU data Product Info Area and Board Info Area. SMBIOS data can be updated with the FRU data. Tested on OCP Mono Lake. Change-Id: Id6353f5ce3f7ddd3bb161b91364b3cf276d020b8 Signed-off-by: Johnny Lin Reviewed-on: https://review.coreboot.org/c/coreboot/+/37444 Tested-by: build bot (Jenkins) Reviewed-by: David Hendricks (cherry picked from commit 8ac46b937c80822706c9d6c70ce7bbe61eb04f72) Reviewed-on: https://review.coreboot.org/c/coreboot/+/37095 --- src/drivers/ipmi/Kconfig | 10 + src/drivers/ipmi/Makefile.inc | 1 + src/drivers/ipmi/ipmi_fru.c | 409 ++++++++++++++++++++++++++++++++++ src/drivers/ipmi/ipmi_kcs.h | 1 + src/drivers/ipmi/ipmi_ops.h | 73 ++++++ 5 files changed, 494 insertions(+) create mode 100644 src/drivers/ipmi/ipmi_fru.c diff --git a/src/drivers/ipmi/Kconfig b/src/drivers/ipmi/Kconfig index 0f7152d558..37cfc0d230 100644 --- a/src/drivers/ipmi/Kconfig +++ b/src/drivers/ipmi/Kconfig @@ -8,3 +8,13 @@ config IPMI_KCS_REGISTER_SPACING depends on IPMI_KCS help KCS status and command register IO port address spacing + +config IPMI_FRU_SINGLE_RW_SZ + int + default 16 + depends on IPMI_KCS + help + The data size in a single IPMI FRU read/write command. + IPMB messages are limited to 32-bytes total. When the + data size is larger than this value, IPMI can complete + reading/writing the data over multiple commands. diff --git a/src/drivers/ipmi/Makefile.inc b/src/drivers/ipmi/Makefile.inc index 9d5b3d418f..973fff82c7 100644 --- a/src/drivers/ipmi/Makefile.inc +++ b/src/drivers/ipmi/Makefile.inc @@ -1,3 +1,4 @@ ramstage-$(CONFIG_IPMI_KCS) += ipmi_kcs.c ramstage-$(CONFIG_IPMI_KCS) += ipmi_kcs_ops.c ramstage-$(CONFIG_IPMI_KCS) += ipmi_ops.c +ramstage-$(CONFIG_IPMI_KCS) += ipmi_fru.c diff --git a/src/drivers/ipmi/ipmi_fru.c b/src/drivers/ipmi/ipmi_fru.c new file mode 100644 index 0000000000..a5e6ea60d5 --- /dev/null +++ b/src/drivers/ipmi/ipmi_fru.c @@ -0,0 +1,409 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 Wiwynn Corp. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include +#include "ipmi_ops.h" + +#define MAX_FRU_BUSY_RETRY 5 +#define READ_FRU_DATA_RETRY_INTERVAL_MS 30 /* From IPMI spec v2.0 rev 1.1 */ +#define OFFSET_LENGTH_MULTIPLIER 8 /* offsets/lengths are multiples of 8 */ +#define NUM_DATA_BYTES(t) (t & 0x3f) /* Encoded in type/length byte */ + +static enum cb_err ipmi_read_fru(const int port, struct ipmi_read_fru_data_req *req, + uint8_t *fru_data) +{ + int ret; + uint8_t total_size; + uint16_t offset = 0; + struct ipmi_read_fru_data_rsp rsp; + int retry_count = 0; + + if (req == NULL || fru_data == NULL) { + printk(BIOS_ERR, "%s failed, null pointer parameter\n", + __func__); + return CB_ERR; + } + + total_size = req->count; + do { + if (req->count > CONFIG_IPMI_FRU_SINGLE_RW_SZ) + req->count = CONFIG_IPMI_FRU_SINGLE_RW_SZ; + + while (retry_count <= MAX_FRU_BUSY_RETRY) { + ret = ipmi_kcs_message(port, IPMI_NETFN_STORAGE, 0x0, + IPMI_READ_FRU_DATA, (const unsigned char *) req, + sizeof(*req), (unsigned char *) &rsp, sizeof(rsp)); + if (rsp.resp.completion_code == 0x81) { + /* Device is busy */ + if (retry_count == MAX_FRU_BUSY_RETRY) { + printk(BIOS_ERR, "IPMI: %s command failed, " + "device busy timeout\n", __func__); + return CB_ERR; + } + printk(BIOS_ERR, "IPMI: FRU device is busy, " + "retry count:%d\n", retry_count); + retry_count++; + mdelay(READ_FRU_DATA_RETRY_INTERVAL_MS); + } else if (ret < sizeof(struct ipmi_rsp) || rsp.resp.completion_code) { + printk(BIOS_ERR, "IPMI: %s command failed (ret=%d resp=0x%x)\n", + __func__, ret, rsp.resp.completion_code); + return CB_ERR; + } + break; + } + retry_count = 0; + memcpy(fru_data + offset, rsp.data, rsp.count); + offset += rsp.count; + total_size -= rsp.count; + req->fru_offset += rsp.count; + req->count = total_size; + } while (total_size > 0); + + return CB_SUCCESS; +} + +/* data: data to check, offset: offset to checksum. */ +static uint8_t checksum(uint8_t *data, int offset) +{ + uint8_t c = 0; + for (; offset > 0; offset--, data++) + c += *data; + return -c; +} + +static uint8_t data2str(const uint8_t *frudata, char *stringdata, uint8_t length) +{ + uint8_t type; + + /* bit[7:6] is the type code. */ + type = ((frudata[0] & 0xc0) >> 6); + if (type != ASCII_8BIT) { + printk(BIOS_ERR, "%s typecode %d is unsupported, FRU string only " + "supports 8-bit ASCII + Latin 1 for now.\n", __func__, type); + return 0; + } + /* In the spec the string data is always the next byte to the type/length byte. */ + memcpy(stringdata, frudata + 1, length); + stringdata[length] = '\0'; + return length; +} + +static void read_fru_board_info_area(const int port, const uint8_t id, + uint8_t offset, struct fru_board_info *info) +{ + uint8_t length; + struct ipmi_read_fru_data_req req; + uint8_t *data_ptr; + + offset = offset * OFFSET_LENGTH_MULTIPLIER; + if (!offset) + return; + req.fru_device_id = id; + /* Read Board Info Area length first. */ + req.fru_offset = offset + 1; + req.count = sizeof(length); + if (ipmi_read_fru(port, &req, &length) != CB_SUCCESS || !length) { + printk(BIOS_ERR, "%s failed, length: %d\n", __func__, length); + return; + } + length = length * OFFSET_LENGTH_MULTIPLIER; + data_ptr = (uint8_t *)malloc(length); + if (!data_ptr) { + printk(BIOS_ERR, "malloc %d bytes for board info failed\n", length); + return; + } + + /* Read Board Info Area data. */ + req.fru_offset = offset; + req.count = length; + if (ipmi_read_fru(port, &req, data_ptr) != CB_SUCCESS) { + printk(BIOS_ERR, "%s failed to read fru\n", __func__); + goto out; + } + if (checksum(data_ptr, length)) { + printk(BIOS_ERR, "Bad FRU board info checksum.\n"); + goto out; + } + /* Read manufacturer string, bit[5:0] is the string length. */ + length = NUM_DATA_BYTES(data_ptr[BOARD_MAN_TYPE_LEN_OFFSET]); + data_ptr += BOARD_MAN_TYPE_LEN_OFFSET; + if (length > 0) { + info->manufacturer = malloc(length + 1); + if (!info->manufacturer) { + printk(BIOS_ERR, "%s failed to malloc %d bytes for " + "manufacturer.\n", __func__, length + 1); + goto out; + } + if (!data2str((const uint8_t *)data_ptr, info->manufacturer, length)) + free(info->manufacturer); + } + + /* Read product name string. */ + data_ptr += length + 1; + length = NUM_DATA_BYTES(data_ptr[0]); + if (length > 0) { + info->product_name = malloc(length+1); + if (!info->product_name) { + printk(BIOS_ERR, "%s failed to malloc %d bytes for " + "product_name.\n", __func__, length + 1); + goto out; + } + if (!data2str((const uint8_t *)data_ptr, info->product_name, length)) + free(info->product_name); + } + + /* Read serial number string. */ + data_ptr += length + 1; + length = NUM_DATA_BYTES(data_ptr[0]); + if (length > 0) { + info->serial_number = malloc(length + 1); + if (!info->serial_number) { + printk(BIOS_ERR, "%s failed to malloc %d bytes for " + "serial_number.\n", __func__, length + 1); + goto out; + } + if (!data2str((const uint8_t *)data_ptr, info->serial_number, length)) + free(info->serial_number); + } + + /* Read part number string. */ + data_ptr += length + 1; + length = NUM_DATA_BYTES(data_ptr[0]); + if (length > 0) { + info->part_number = malloc(length + 1); + if (!info->part_number) { + printk(BIOS_ERR, "%s failed to malloc %d bytes for " + "part_number.\n", __func__, length + 1); + goto out; + } + if (!data2str((const uint8_t *)data_ptr, info->part_number, length)) + free(info->part_number); + } + +out: + free(data_ptr); +} + +static void read_fru_product_info_area(const int port, const uint8_t id, + uint8_t offset, struct fru_product_info *info) +{ + uint8_t length; + struct ipmi_read_fru_data_req req; + uint8_t *data_ptr; + + offset = offset * OFFSET_LENGTH_MULTIPLIER; + if (!offset) + return; + + req.fru_device_id = id; + /* Read Product Info Area length first. */ + req.fru_offset = offset + 1; + req.count = sizeof(length); + if (ipmi_read_fru(port, &req, &length) != CB_SUCCESS || !length) { + printk(BIOS_ERR, "%s failed, length: %d\n", __func__, length); + return; + } + length = length * OFFSET_LENGTH_MULTIPLIER; + data_ptr = (uint8_t *)malloc(length); + if (!data_ptr) { + printk(BIOS_ERR, "malloc %d bytes for product info failed\n", length); + return; + } + + /* Read Product Info Area data. */ + req.fru_offset = offset; + req.count = length; + if (ipmi_read_fru(port, &req, data_ptr) != CB_SUCCESS) { + printk(BIOS_ERR, "%s failed to read fru\n", __func__); + goto out; + } + if (checksum(data_ptr, length)) { + printk(BIOS_ERR, "Bad FRU product info checksum.\n"); + goto out; + } + /* Read manufacturer string, bit[5:0] is the string length. */ + length = NUM_DATA_BYTES(data_ptr[PRODUCT_MAN_TYPE_LEN_OFFSET]); + data_ptr += PRODUCT_MAN_TYPE_LEN_OFFSET; + if (length > 0) { + info->manufacturer = malloc(length + 1); + if (!info->manufacturer) { + printk(BIOS_ERR, "%s failed to malloc %d bytes for " + "manufacturer.\n", __func__, length + 1); + goto out; + } + if (!data2str((const uint8_t *)data_ptr, info->manufacturer, length)) + free(info->manufacturer); + } + + /* Read product_name string. */ + data_ptr += length + 1; + length = NUM_DATA_BYTES(data_ptr[0]); + if (length > 0) { + info->product_name = malloc(length + 1); + if (!info->product_name) { + printk(BIOS_ERR, "%s failed to malloc %d bytes for " + "product_name.\n", __func__, length + 1); + goto out; + } + if (!data2str((const uint8_t *)data_ptr, info->product_name, length)) + free(info->product_name); + } + + /* Read product part/model number. */ + data_ptr += length + 1; + length = NUM_DATA_BYTES(data_ptr[0]); + if (length > 0) { + info->product_partnumber = malloc(length + 1); + if (!info->product_partnumber) { + printk(BIOS_ERR, "%s failed to malloc %d bytes for " + "product_partnumber.\n", __func__, length + 1); + goto out; + } + if (!data2str((const uint8_t *)data_ptr, info->product_partnumber, length)) + free(info->product_partnumber); + } + + /* Read product version string. */ + data_ptr += length + 1; + length = NUM_DATA_BYTES(data_ptr[0]); + if (length > 0) { + info->product_version = malloc(length + 1); + if (!info->product_version) { + printk(BIOS_ERR, "%s failed to malloc %d bytes for " + "product_version.\n", __func__, length + 1); + goto out; + } + if (!data2str((const uint8_t *)data_ptr, info->product_version, length)) + free(info->product_version); + } + + /* Read serial number string. */ + data_ptr += length + 1; + length = NUM_DATA_BYTES(data_ptr[0]); + if (length > 0) { + info->serial_number = malloc(length + 1); + if (!info->serial_number) { + printk(BIOS_ERR, "%s failed to malloc %d bytes for " + "serial_number.\n", __func__, length + 1); + goto out; + } + if (!data2str((const uint8_t *)data_ptr, info->serial_number, length)) + free(info->serial_number); + } + + /* Read asset tag string. */ + data_ptr += length + 1; + length = NUM_DATA_BYTES(data_ptr[0]); + if (length > 0) { + info->asset_tag = malloc(length + 1); + if (!info->asset_tag) { + printk(BIOS_ERR, "%s failed to malloc %d bytes for " + "asset_tag.\n", __func__, length + 1); + goto out; + } + if (!data2str((const uint8_t *)data_ptr, info->asset_tag, length)) + free(info->serial_number); + } + +out: + free(data_ptr); +} + +void read_fru_areas(const int port, const uint8_t id, uint16_t offset, + struct fru_info_str *fru_info_str) +{ + struct ipmi_read_fru_data_req req; + struct ipmi_fru_common_hdr fru_common_hdr; + + /* Set all the char pointers to 0 first, to avoid mainboard + * overwriting SMBIOS string with any non-NULL char pointer + * by accident. */ + memset(fru_info_str, 0, sizeof(*fru_info_str)); + req.fru_device_id = id; + req.fru_offset = offset; + req.count = sizeof(fru_common_hdr); + /* Read FRU common header first */ + if (ipmi_read_fru(port, &req, (uint8_t *)&fru_common_hdr) == CB_SUCCESS) { + if (checksum((uint8_t *)&fru_common_hdr, sizeof(fru_common_hdr))) { + printk(BIOS_ERR, "Bad FRU common header checksum.\n"); + return; + } + printk(BIOS_DEBUG, "FRU common header: format_version: %x\n" + "product_area_offset: %x\n" + "board_area_offset: %x\n" + "chassis_area_offset: %x\n", + fru_common_hdr.format_version, + fru_common_hdr.product_area_offset, + fru_common_hdr.board_area_offset, + fru_common_hdr.chassis_area_offset); + } else { + printk(BIOS_ERR, "Read FRU common header failed\n"); + return; + } + + read_fru_product_info_area(port, id, fru_common_hdr.product_area_offset, + &fru_info_str->prod_info); + read_fru_board_info_area(port, id, fru_common_hdr.board_area_offset, + &fru_info_str->board_info); + /* ToDo: Add read_fru_chassis_info_area(). */ +} + +void read_fru_one_area(const int port, const uint8_t id, uint16_t offset, + struct fru_info_str *fru_info_str, enum fru_area fru_area) +{ + struct ipmi_read_fru_data_req req; + struct ipmi_fru_common_hdr fru_common_hdr; + + req.fru_device_id = id; + req.fru_offset = offset; + req.count = sizeof(fru_common_hdr); + if (ipmi_read_fru(port, &req, (uint8_t *)&fru_common_hdr) == CB_SUCCESS) { + if (checksum((uint8_t *)&fru_common_hdr, sizeof(fru_common_hdr))) { + printk(BIOS_ERR, "Bad FRU common header checksum.\n"); + return; + } + printk(BIOS_DEBUG, "FRU common header: format_version: %x\n" + "product_area_offset: %x\n" + "board_area_offset: %x\n" + "chassis_area_offset: %x\n", + fru_common_hdr.format_version, + fru_common_hdr.product_area_offset, + fru_common_hdr.board_area_offset, + fru_common_hdr.chassis_area_offset); + } else { + printk(BIOS_ERR, "Read FRU common header failed\n"); + return; + } + + switch (fru_area) { + case PRODUCT_INFO_AREA: + memset(&fru_info_str->prod_info, 0, sizeof(fru_info_str->prod_info)); + read_fru_product_info_area(port, id, fru_common_hdr.product_area_offset, + &fru_info_str->prod_info); + break; + case BOARD_INFO_AREA: + memset(&fru_info_str->board_info, 0, sizeof(fru_info_str->board_info)); + read_fru_board_info_area(port, id, fru_common_hdr.board_area_offset, + &fru_info_str->board_info); + break; + /* ToDo: Add case for CHASSIS_INFO_AREA. */ + default: + printk(BIOS_ERR, "Invalid fru_area: %d\n", fru_area); + break; + } +} diff --git a/src/drivers/ipmi/ipmi_kcs.h b/src/drivers/ipmi/ipmi_kcs.h index b3775219c3..9a04377a0a 100644 --- a/src/drivers/ipmi/ipmi_kcs.h +++ b/src/drivers/ipmi/ipmi_kcs.h @@ -31,6 +31,7 @@ #define IPMI_NETFN_FIRMWARE 0x08 #define IPMI_NETFN_STORAGE 0x0a +#define IPMI_READ_FRU_DATA 0x11 #define IPMI_NETFN_TRANSPORT 0x0c #define IPMI_CMD_ACPI_POWERON 0x06 diff --git a/src/drivers/ipmi/ipmi_ops.h b/src/drivers/ipmi/ipmi_ops.h index 77fc727cc8..dd12786b8e 100644 --- a/src/drivers/ipmi/ipmi_ops.h +++ b/src/drivers/ipmi/ipmi_ops.h @@ -49,6 +49,70 @@ struct ipmi_get_system_guid_rsp { struct ipmi_rsp resp; uint8_t data[16]; } __packed; + +struct ipmi_read_fru_data_req { + uint8_t fru_device_id; + uint16_t fru_offset; + uint8_t count; /* count to read, 1-based. */ +} __packed; + +struct ipmi_read_fru_data_rsp { + struct ipmi_rsp resp; + uint8_t count; /* count returned, 1-based. */ + uint8_t data[CONFIG_IPMI_FRU_SINGLE_RW_SZ]; +} __packed; + +/* Platform Management FRU Information Storage Definition Spec. */ +#define PRODUCT_MAN_TYPE_LEN_OFFSET 3 +#define BOARD_MAN_TYPE_LEN_OFFSET 6 + +struct ipmi_fru_common_hdr { + uint8_t format_version; + uint8_t internal_use_area_offset; + uint8_t chassis_area_offset; + uint8_t board_area_offset; + uint8_t product_area_offset; + uint8_t multirecord_area_offset; + uint8_t pad; + uint8_t checksum; +} __packed; + +/* The fru_xxx_info only declares the strings that may be added to SMBIOS. */ +struct fru_product_info { + char *manufacturer; + char *product_name; + char *product_partnumber; + char *product_version; + char *serial_number; + char *asset_tag; +}; + +struct fru_board_info { + char *manufacturer; + char *product_name; + char *serial_number; + char *part_number; +}; + +struct fru_info_str { + struct fru_product_info prod_info; + struct fru_board_info board_info; +}; + +enum typecode { + BINARY = 0, + BCD_PLUS = 1, + ASCII_6BIT = 2, + ASCII_8BIT = 3, +}; + +enum fru_area { + INTERNAL_USE_AREA = 0, + CHASSIS_INFO_AREA = 1, + BOARD_INFO_AREA = 2, + PRODUCT_INFO_AREA = 3, + MULTIRECORD_INFO_AREA = 4, +}; /* * Initialize and start BMC FRB2 watchdog timer with the * provided timer countdown and action values. @@ -62,4 +126,13 @@ enum cb_err ipmi_stop_bmc_wdt(const int port); /* IPMI get BMC system GUID and store it to parameter uuid. * Returns CB_SUCCESS on success and CB_ERR if an error occurred */ enum cb_err ipmi_get_system_guid(const int port, uint8_t *uuid); + +/* Read all FRU inventory areas string data into fru_info_str with + * the same FRU device id. */ +void read_fru_areas(const int port, uint8_t id, uint16_t offset, + struct fru_info_str *fru_info_str); + +/* Read a particular FRU inventory area into fru_info_str. */ +void read_fru_one_area(const int port, uint8_t id, uint16_t offset, + struct fru_info_str *fru_info_str, enum fru_area fru_area); #endif From 1e83e5c61a3aa98f58f7d8cbf8d1eb9532896cc3 Mon Sep 17 00:00:00 2001 From: Karthikeyan Ramasubramanian Date: Mon, 16 Dec 2019 13:26:35 -0700 Subject: [PATCH 0775/1242] src/arch/x86: Build mainboard acpi_tables source if present Current build rules require adding blank acpi_tables in some of the mainboards (eg. octopus, hatch). Update the build rules to compile the acpi_tables.c only if it is present. This will help to avoid adding blank acpi_tables.c source file. BUG=None TEST=Build test with octopus and hatch without blank acpi_table.c file. Change-Id: I7dfacc6f4c737699b22acd96e17c9426d33574bd Signed-off-by: Karthikeyan Ramasubramanian Reviewed-on: https://review.coreboot.org/c/coreboot/+/37774 Tested-by: build bot (Jenkins) Reviewed-by: Justin TerAvest Reviewed-by: Furquan Shaikh Reviewed-by: Aamir Bohra --- src/arch/x86/Makefile.inc | 2 ++ 1 file changed, 2 insertions(+) diff --git a/src/arch/x86/Makefile.inc b/src/arch/x86/Makefile.inc index 423c35116b..f82148cf27 100644 --- a/src/arch/x86/Makefile.inc +++ b/src/arch/x86/Makefile.inc @@ -347,7 +347,9 @@ ifneq ($(wildcard src/mainboard/$(MAINBOARDDIR)/reset.c),) ramstage-srcs += src/mainboard/$(MAINBOARDDIR)/reset.c endif ifeq ($(CONFIG_HAVE_ACPI_TABLES),y) +ifneq ($(wildcard src/mainboard/$(MAINBOARDDIR)/acpi_tables.c),) ramstage-srcs += src/mainboard/$(MAINBOARDDIR)/acpi_tables.c +endif $(eval $(call asl_template,dsdt)) ifneq ($(wildcard src/mainboard/$(MAINBOARDDIR)/fadt.c),) ramstage-srcs += src/mainboard/$(MAINBOARDDIR)/fadt.c From 53490444f72605f53c81e3bdbf479d1013a2d617 Mon Sep 17 00:00:00 2001 From: Aamir Bohra Date: Mon, 16 Dec 2019 17:49:13 +0530 Subject: [PATCH 0776/1242] soc/intel/tigerlake: Add required header files in pch.c Add header files to fix build issues due to missing declaration for get_pch_series and die_with_post_code functions. Change-Id: Ie8ba4970ec1b73c1e481f54bcfbf95be87d9c442 Signed-off-by: Aamir Bohra Reviewed-on: https://review.coreboot.org/c/coreboot/+/37765 Tested-by: build bot (Jenkins) Reviewed-by: Maulik V Vaghela Reviewed-by: Karthik Ramasubramanian --- src/soc/intel/tigerlake/bootblock/pch.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/src/soc/intel/tigerlake/bootblock/pch.c b/src/soc/intel/tigerlake/bootblock/pch.c index 8599423f91..7a93182661 100644 --- a/src/soc/intel/tigerlake/bootblock/pch.c +++ b/src/soc/intel/tigerlake/bootblock/pch.c @@ -19,6 +19,8 @@ * Chapter number: 2, 3, 4, 27, 28 */ +#include +#include #include #include #include @@ -30,6 +32,7 @@ #include #include #include +#include #include #include #include From d1371508f525542f3b75de553dc338b9100bde20 Mon Sep 17 00:00:00 2001 From: Wim Vervoorn Date: Tue, 17 Dec 2019 14:10:16 +0100 Subject: [PATCH 0777/1242] {drivers,soc}/intel/fsp2_0: Move chipset specific logo handling to SoC FSP logo handling used FspsConfig.LogoPtr and FspsConfig.LogoSize which are chipset specific. Create soc_load_logo() which will pass the logo pointer and size. This function will call fsp_load_logo which will load the logo. BUG=NA TEST= Build and verified logo is displayed on Facebook Monolith Change-Id: I30c7bdc0532ff8823e06f4136f210b542385d5ce Signed-off-by: Wim Vervoorn Reviewed-on: https://review.coreboot.org/c/coreboot/+/37792 Reviewed-by: Frans Hendriks Reviewed-by: Aamir Bohra Reviewed-by: Subrata Banik Tested-by: build bot (Jenkins) --- src/drivers/intel/fsp2_0/Kconfig | 6 +++++- src/drivers/intel/fsp2_0/include/fsp/api.h | 4 +++- src/drivers/intel/fsp2_0/logo.c | 25 ++++++++++++++-------- src/drivers/intel/fsp2_0/silicon_init.c | 21 +++++++++--------- src/soc/intel/apollolake/Kconfig | 1 + src/soc/intel/apollolake/chip.c | 6 ++++++ src/soc/intel/cannonlake/Kconfig | 1 + src/soc/intel/cannonlake/fsp_params.c | 7 ++++++ src/soc/intel/skylake/Kconfig | 1 + src/soc/intel/skylake/chip.c | 7 ++++++ 10 files changed, 58 insertions(+), 21 deletions(-) diff --git a/src/drivers/intel/fsp2_0/Kconfig b/src/drivers/intel/fsp2_0/Kconfig index 824fd0b896..7ce7838642 100644 --- a/src/drivers/intel/fsp2_0/Kconfig +++ b/src/drivers/intel/fsp2_0/Kconfig @@ -156,10 +156,14 @@ config FSP_PEIM_TO_PEIM_INTERFACE is limited till EFI_PEI_MP_SERVICE_PPI and this option might be useful to add further PPI if required. +config HAVE_FSP_LOGO_SUPPORT + bool + default n + config FSP2_0_DISPLAY_LOGO bool "Enable logo" default n - depends on HAVE_FSP_GOP + depends on HAVE_FSP_LOGO_SUPPORT help Uses the FSP to display the boot logo. This method supports a BMP file only. The uncompressed size can be up to 1 MB. The logo can be compressed diff --git a/src/drivers/intel/fsp2_0/include/fsp/api.h b/src/drivers/intel/fsp2_0/include/fsp/api.h index fb42c7647b..60adb98513 100644 --- a/src/drivers/intel/fsp2_0/include/fsp/api.h +++ b/src/drivers/intel/fsp2_0/include/fsp/api.h @@ -70,13 +70,15 @@ uint8_t fsp_memory_mainboard_version(void); uint8_t fsp_memory_soc_version(void); /* Load logo to be displayed by FSP */ -void load_logo(FSPS_UPD *supd); +const struct cbmem_entry *fsp_load_logo(UINT32 *logo_ptr, UINT32 *logo_size); /* Callback after processing FSP notify */ void platform_fsp_notify_status(enum fsp_notify_phase phase); /* Initialize memory margin analysis settings. */ void setup_mma(FSP_M_CONFIG *memory_cfg); +/* Update the SOC specific logo param and load the logo. */ +const struct cbmem_entry *soc_load_logo(FSPS_UPD *supd); /* Update the SOC specific memory config param for mma. */ void soc_update_memory_params_for_mma(FSP_M_CONFIG *memory_cfg, struct mma_config_param *mma_cfg); diff --git a/src/drivers/intel/fsp2_0/logo.c b/src/drivers/intel/fsp2_0/logo.c index feeec3b995..ba2b5dcbcd 100644 --- a/src/drivers/intel/fsp2_0/logo.c +++ b/src/drivers/intel/fsp2_0/logo.c @@ -11,17 +11,24 @@ * GNU General Public License for more details. */ -#include -#include +#include +#include #include -#include -void load_logo(FSPS_UPD *supd) +const struct cbmem_entry *fsp_load_logo(UINT32 *logo_ptr, UINT32 *logo_size) { - FSP_S_CONFIG *params = &supd->FspsConfig; + const struct cbmem_entry *logo_entry = NULL; + void *logo_buffer; - params->LogoSize = cbfs_boot_load_file("logo.bmp", (void *)params->LogoPtr, - params->LogoSize, CBFS_TYPE_RAW); - if (!params->LogoSize) - params->LogoPtr = 0; + logo_entry = cbmem_entry_add(CBMEM_ID_FSP_LOGO, 1 * MiB); + if (logo_entry) { + logo_buffer = cbmem_entry_start(logo_entry); + if (logo_buffer) { + *logo_size = cbfs_boot_load_file("logo.bmp", (void *)logo_buffer, + 1 * MiB, CBFS_TYPE_RAW); + if (logo_size) + *logo_ptr = (UINT32)logo_buffer; + } + } + return (logo_entry); } diff --git a/src/drivers/intel/fsp2_0/silicon_init.c b/src/drivers/intel/fsp2_0/silicon_init.c index ebdbdbf2e6..33d15afad6 100644 --- a/src/drivers/intel/fsp2_0/silicon_init.c +++ b/src/drivers/intel/fsp2_0/silicon_init.c @@ -34,7 +34,7 @@ static void do_silicon_init(struct fsp_header *hdr) fsp_silicon_init_fn silicon_init; uint32_t status; uint8_t postcode; - const struct cbmem_entry *logo_entry; + const struct cbmem_entry *logo_entry = NULL; supd = (FSPS_UPD *) (hdr->cfg_region_offset + hdr->image_base); @@ -57,14 +57,9 @@ static void do_silicon_init(struct fsp_header *hdr) /* Give SoC/mainboard a chance to populate entries */ platform_fsp_silicon_init_params_cb(upd); -#if (CONFIG(HAVE_FSP_GOP)) - if (CONFIG(FSP2_0_DISPLAY_LOGO)) { - upd->FspsConfig.LogoSize = 1 * MiB; - logo_entry = cbmem_entry_add(CBMEM_ID_FSP_LOGO, upd->FspsConfig.LogoSize); - upd->FspsConfig.LogoPtr = (UINT32)cbmem_entry_start(logo_entry); - load_logo(upd); - } -#endif + /* Populate logo related entries */ + if (CONFIG(FSP2_0_DISPLAY_LOGO)) + logo_entry = soc_load_logo(upd); /* Call SiliconInit */ silicon_init = (void *) (hdr->image_base + @@ -77,7 +72,7 @@ static void do_silicon_init(struct fsp_header *hdr) timestamp_add_now(TS_FSP_SILICON_INIT_END); post_code(POST_FSP_SILICON_EXIT); - if (CONFIG(FSP2_0_DISPLAY_LOGO)) + if (logo_entry) cbmem_entry_remove(logo_entry); fsp_debug_after_silicon_init(status); @@ -160,3 +155,9 @@ void fsp_silicon_init(bool s3wake) fsps_load(s3wake); do_silicon_init(&fsps_hdr); } + +/* Load bmp and set FSP parameters, fsp_load_logo can be used */ +__weak const struct cbmem_entry *soc_load_logo(FSPS_UPD *supd) +{ + return NULL; +} diff --git a/src/soc/intel/apollolake/Kconfig b/src/soc/intel/apollolake/Kconfig index a39765f8f6..2f4ebb0540 100644 --- a/src/soc/intel/apollolake/Kconfig +++ b/src/soc/intel/apollolake/Kconfig @@ -102,6 +102,7 @@ config CPU_SPECIFIC_OPTIONS select HAVE_CF9_RESET_PREPARE select INTEL_GMA_ADD_VBT if RUN_FSP_GOP select HAVE_FSP_GOP + select HAVE_FSP_LOGO_SUPPORT select NO_UART_ON_SUPERIO select INTEL_GMA_ACPI select INTEL_GMA_SWSMISCI diff --git a/src/soc/intel/apollolake/chip.c b/src/soc/intel/apollolake/chip.c index 6c195bb6fd..907149a829 100644 --- a/src/soc/intel/apollolake/chip.c +++ b/src/soc/intel/apollolake/chip.c @@ -879,4 +879,10 @@ void mainboard_silicon_init_params(FSP_S_CONFIG *silconfig) printk(BIOS_DEBUG, "WEAK: %s/%s called\n", __FILE__, __func__); } +/* Handle FSP logo params */ +const struct cbmem_entry *soc_load_logo(FSPS_UPD *supd) +{ + return fsp_load_logo(&supd->FspsConfig.LogoPtr, &supd->FspsConfig.LogoSize); +} + BOOT_STATE_INIT_ENTRY(BS_PRE_DEVICE, BS_ON_ENTRY, spi_flash_init_cb, NULL); diff --git a/src/soc/intel/cannonlake/Kconfig b/src/soc/intel/cannonlake/Kconfig index 8820508259..26bae068df 100644 --- a/src/soc/intel/cannonlake/Kconfig +++ b/src/soc/intel/cannonlake/Kconfig @@ -66,6 +66,7 @@ config CPU_SPECIFIC_OPTIONS select FSP_M_XIP select GENERIC_GPIO_LIB select HAVE_FSP_GOP + select HAVE_FSP_LOGO_SUPPORT select INTEL_DESCRIPTOR_MODE_CAPABLE select HAVE_SMI_HANDLER select IDT_IN_EVERY_STAGE diff --git a/src/soc/intel/cannonlake/fsp_params.c b/src/soc/intel/cannonlake/fsp_params.c index dfc7e22522..dc4a2a841e 100644 --- a/src/soc/intel/cannonlake/fsp_params.c +++ b/src/soc/intel/cannonlake/fsp_params.c @@ -13,6 +13,7 @@ * GNU General Public License for more details. */ +#include #include #include #include @@ -483,3 +484,9 @@ const pci_devfn_t *soc_lpss_controllers_list(size_t *size) *size = ARRAY_SIZE(serial_io_dev); return serial_io_dev; } + +/* Handle FSP logo params */ +const struct cbmem_entry *soc_load_logo(FSPS_UPD *supd) +{ + return fsp_load_logo(&supd->FspsConfig.LogoPtr, &supd->FspsConfig.LogoSize); +} diff --git a/src/soc/intel/skylake/Kconfig b/src/soc/intel/skylake/Kconfig index 5fc2a2d240..d90fb6b9fb 100644 --- a/src/soc/intel/skylake/Kconfig +++ b/src/soc/intel/skylake/Kconfig @@ -33,6 +33,7 @@ config CPU_SPECIFIC_OPTIONS select FSP_M_XIP select GENERIC_GPIO_LIB select HAVE_FSP_GOP + select HAVE_FSP_LOGO_SUPPORT select INTEL_DESCRIPTOR_MODE_CAPABLE select HAVE_SMI_HANDLER select INTEL_CAR_NEM_ENHANCED diff --git a/src/soc/intel/skylake/chip.c b/src/soc/intel/skylake/chip.c index de11a9e1c7..8e86156a07 100644 --- a/src/soc/intel/skylake/chip.c +++ b/src/soc/intel/skylake/chip.c @@ -15,6 +15,7 @@ #include #include +#include #include #include #include @@ -416,3 +417,9 @@ __weak void mainboard_silicon_init_params(FSP_S_CONFIG *params) { printk(BIOS_DEBUG, "WEAK: %s/%s called\n", __FILE__, __func__); } + +/* Handle FSP logo params */ +const struct cbmem_entry *soc_load_logo(FSPS_UPD *supd) +{ + return fsp_load_logo(&supd->FspsConfig.LogoPtr, &supd->FspsConfig.LogoSize); +} From 94ce79d6c8d4ee04f55be0bb95feb62411ec8d88 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ky=C3=B6sti=20M=C3=A4lkki?= Date: Mon, 16 Dec 2019 17:21:13 +0200 Subject: [PATCH 0778/1242] device/pciexp: Match Max_Payload_Size between ends of a link MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Ends of a PCIe link may advertise different Max_Payload_Size in their PCIe Express Capabilities, Device Capabilities block. For correct operation, both ends of the link need to have their Device Control Max_Payload_Size programmed to match and not exceed the other end's Device Capabilities. Fixes: https://ticket.coreboot.org/issues/218 Change-Id: I8b1de13e9c73abb30e5ccc792918bb4f81e5fe84 Signed-off-by: Kyösti Mälkki Reviewed-on: https://review.coreboot.org/c/coreboot/+/37769 Tested-by: build bot (Jenkins) Reviewed-by: Marshall Dawson --- src/device/pciexp_device.c | 44 ++++++++++++++++++++++++++++++++++++++ 1 file changed, 44 insertions(+) diff --git a/src/device/pciexp_device.c b/src/device/pciexp_device.c index c73c548bb4..479891c5d6 100644 --- a/src/device/pciexp_device.c +++ b/src/device/pciexp_device.c @@ -12,6 +12,7 @@ */ #include +#include #include #include #include @@ -408,6 +409,46 @@ static void pciexp_enable_aspm(struct device *root, unsigned int root_cap, printk(BIOS_INFO, "ASPM: Enabled %s\n", aspm_type_str[apmc]); } +/* + * Set max payload size of endpoint in accordance with max payload size of root port. + */ +static void pciexp_set_max_payload_size(struct device *root, unsigned int root_cap, + struct device *endp, unsigned int endp_cap) +{ + unsigned int endp_max_payload, root_max_payload, max_payload; + u16 endp_devctl, root_devctl; + u32 endp_devcap, root_devcap; + + /* Get max payload size supported by endpoint */ + endp_devcap = pci_read_config32(endp, endp_cap + PCI_EXP_DEVCAP); + endp_max_payload = endp_devcap & PCI_EXP_DEVCAP_PAYLOAD; + + /* Get max payload size supported by root port */ + root_devcap = pci_read_config32(root, root_cap + PCI_EXP_DEVCAP); + root_max_payload = root_devcap & PCI_EXP_DEVCAP_PAYLOAD; + + /* Set max payload to smaller of the reported device capability. */ + max_payload = MIN(endp_max_payload, root_max_payload); + if (max_payload > 5) { + /* Values 6 and 7 are reserved in PCIe 3.0 specs. */ + printk(BIOS_ERR, "PCIe: Max_Payload_Size field restricted from %d to 5\n", + max_payload); + max_payload = 5; + } + + endp_devctl = pci_read_config16(endp, endp_cap + PCI_EXP_DEVCTL); + endp_devctl &= ~PCI_EXP_DEVCTL_PAYLOAD; + endp_devctl |= max_payload << 5; + pci_write_config16(endp, endp_cap + PCI_EXP_DEVCTL, endp_devctl); + + root_devctl = pci_read_config16(root, root_cap + PCI_EXP_DEVCTL); + root_devctl &= ~PCI_EXP_DEVCTL_PAYLOAD; + root_devctl |= max_payload << 5; + pci_write_config16(root, root_cap + PCI_EXP_DEVCTL, root_devctl); + + printk(BIOS_INFO, "PCIe: Max_Payload_Size adjusted to %d\n", (1 << (max_payload + 7))); +} + static void pciexp_tune_dev(struct device *dev) { struct device *root = dev->bus->dev; @@ -436,6 +477,9 @@ static void pciexp_tune_dev(struct device *dev) /* Check for and enable ASPM */ if (CONFIG(PCIEXP_ASPM)) pciexp_enable_aspm(root, root_cap, dev, cap); + + /* Adjust Max_Payload_Size of link ends. */ + pciexp_set_max_payload_size(root, root_cap, dev, cap); } void pciexp_scan_bus(struct bus *bus, unsigned int min_devfn, From 23c1c4e153e8f1311b2e04a19a7e0c66d648e972 Mon Sep 17 00:00:00 2001 From: Elyes HAOUAS Date: Wed, 18 Dec 2019 13:21:37 +0100 Subject: [PATCH 0779/1242] commonlib/fsp_relocate: Fix typos Change-Id: I9426b88c0936c68d02554b580cc312902b8e5e13 Signed-off-by: Elyes HAOUAS Reviewed-on: https://review.coreboot.org/c/coreboot/+/37810 Reviewed-by: Frans Hendriks Tested-by: build bot (Jenkins) --- src/commonlib/fsp_relocate.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/commonlib/fsp_relocate.c b/src/commonlib/fsp_relocate.c index 85deda2470..a8b45fa1fa 100644 --- a/src/commonlib/fsp_relocate.c +++ b/src/commonlib/fsp_relocate.c @@ -136,8 +136,8 @@ static int te_relocate(uintptr_t new_addr, void *te) /* * A TE image is created by converting a PE file. Because of this * the offsets within the headers are off. In order to calculate - * the correct releative offets one needs to subtract fixup_offset - * from the encoded offets. Similarly, the linked address of the + * the correct relative offsets one needs to subtract fixup_offset + * from the encoded offsets. Similarly, the linked address of the * program is found by adding the fixup_offset to the ImageBase. */ fixup_offset = read_le16(&teih->StrippedSize); From 6766f4fd046604e6376c9769cd5f8357dec6a80a Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ky=C3=B6sti=20M=C3=A4lkki?= Date: Wed, 18 Dec 2019 00:19:06 +0200 Subject: [PATCH 0780/1242] arch/x86: Fix S3 resume without stage cache MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit It was possible to have NO_STAGE_CACHE=n and at the same time have TSEG_STAGE_CACHE=n and CBMEM_STAGE_CACHE=n. This resulted with a failing attempt to load STAGE_POSTCAR from the stage cache, but not loading it from CBFS either. Make it a three-way choice between different STAGE_CACHE options. For AGESA disable CBMEM_STAGE_CACHE by default, as it is no longer needed to have functional ACPI S3 resume and it is not allowed se use keyword select for symbols inside choice blocks. Change-Id: I0da3e1cf4c92817ffabbb02eda3476ecdfdfa278 Signed-off-by: Kyösti Mälkki Reviewed-on: https://review.coreboot.org/c/coreboot/+/37683 Reviewed-by: Aaron Durbin Tested-by: build bot (Jenkins) --- src/Kconfig | 29 +++++++++++++++++------------ src/cpu/amd/agesa/Kconfig | 1 - 2 files changed, 17 insertions(+), 13 deletions(-) diff --git a/src/Kconfig b/src/Kconfig index 25bb450174..b78b162e9d 100644 --- a/src/Kconfig +++ b/src/Kconfig @@ -274,18 +274,28 @@ config RELOCATABLE_RAMSTAGE wake. When selecting this option the romstage is responsible for determing a stack location to use for loading the ramstage. +choice + prompt "Stage Cache for ACPI S3 resume" + default NO_STAGE_CACHE if !HAVE_ACPI_RESUME || !RELOCATABLE_RAMSTAGE + default TSEG_STAGE_CACHE if SMM_TSEG + +config NO_STAGE_CACHE + bool "Disabled" + help + Do not save any component in stage cache for resume path. On resume, + all components would be read back from CBFS again. + config TSEG_STAGE_CACHE - bool - default y - depends on !NO_STAGE_CACHE && SMM_TSEG + bool "TSEG" + depends on SMM_TSEG help The option enables stage cache support for platform. Platform can stash copies of postcar, ramstage and raw runtime data inside SMM TSEG, to be restored on S3 resume path. config CBMEM_STAGE_CACHE - bool "Cache stages in CBMEM" - depends on !NO_STAGE_CACHE && !TSEG_STAGE_CACHE + bool "CBMEM" + depends on !SMM_TSEG help The option enables stage cache support for platform. Platform can stash copies of postcar, ramstage and raw runtime data @@ -297,6 +307,8 @@ config CBMEM_STAGE_CACHE If unsure, select 'N' +endchoice + config UPDATE_IMAGE bool "Update existing coreboot.rom image" help @@ -1153,13 +1165,6 @@ config RELOCATABLE_MODULES building relocatable modules in the RAM stage. Those modules can be loaded anywhere and all the relocations are handled automatically. -config NO_STAGE_CACHE - bool - default y if !HAVE_ACPI_RESUME || !RELOCATABLE_RAMSTAGE - help - Do not save any component in stage cache for resume path. On resume, - all components would be read back from CBFS again. - config GENERIC_GPIO_LIB bool help diff --git a/src/cpu/amd/agesa/Kconfig b/src/cpu/amd/agesa/Kconfig index 2c8f9c5e37..fae2565a47 100644 --- a/src/cpu/amd/agesa/Kconfig +++ b/src/cpu/amd/agesa/Kconfig @@ -26,7 +26,6 @@ config CPU_AMD_AGESA select UDELAY_LAPIC select LAPIC_MONOTONIC_TIMER select SPI_FLASH if HAVE_ACPI_RESUME - select CBMEM_STAGE_CACHE if HAVE_ACPI_RESUME select SMM_ASEG select NO_FIXED_XIP_ROM_SIZE select SSE2 From 4f14cd8a39e65811af08296633842289efa42927 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ky=C3=B6sti=20M=C3=A4lkki?= Date: Wed, 18 Dec 2019 19:40:48 +0200 Subject: [PATCH 0781/1242] arch/x86,soc/intel: Drop RESET_ON_INVALID_RAMSTAGE_CACHE MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit If stage cache is enabled, we should not allow S3 resume to load firmware from non-volatile memory. This also adds board reset for failing to load postcar from stage cache. Change-Id: Ib6cc7ad0fe9dcdf05b814d324b680968a2870f23 Signed-off-by: Kyösti Mälkki Reviewed-on: https://review.coreboot.org/c/coreboot/+/37682 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin --- configs/config.google_meep_cros | 1 - configs/config.google_reef_cros | 1 - src/arch/x86/postcar_loader.c | 10 ++++++++++ src/cpu/intel/haswell/Kconfig | 12 ------------ src/drivers/intel/fsp1_1/Kconfig | 4 ---- src/drivers/intel/fsp2_0/Kconfig | 4 ---- src/lib/prog_loaders.c | 12 +++--------- src/soc/intel/apollolake/Makefile.inc | 4 ++-- src/soc/intel/baytrail/Kconfig | 11 ----------- src/soc/intel/braswell/Kconfig | 11 ----------- src/soc/intel/broadwell/Kconfig | 10 ---------- 11 files changed, 15 insertions(+), 65 deletions(-) diff --git a/configs/config.google_meep_cros b/configs/config.google_meep_cros index 3963fd4a98..f87b02b5e9 100644 --- a/configs/config.google_meep_cros +++ b/configs/config.google_meep_cros @@ -2,7 +2,6 @@ CONFIG_VENDOR_GOOGLE=y CONFIG_BOARD_GOOGLE_MEEP=y CONFIG_PAYLOAD_NONE=y -CONFIG_RESET_ON_INVALID_RAMSTAGE_CACHE=y CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH_SMM=y CONFIG_USE_BLOBS=y diff --git a/configs/config.google_reef_cros b/configs/config.google_reef_cros index 82b9b5234e..9bbb3b3f59 100644 --- a/configs/config.google_reef_cros +++ b/configs/config.google_reef_cros @@ -3,7 +3,6 @@ CONFIG_VENDOR_GOOGLE=y CONFIG_BOARD_GOOGLE_REEF=y CONFIG_CHROMEOS=y CONFIG_ADD_FSP_BINARIES=y -CONFIG_RESET_ON_INVALID_RAMSTAGE_CACHE=y CONFIG_ELOG_GSMI=y CONFIG_ELOG_BOOT_COUNT=y CONFIG_ELOG_BOOT_COUNT_CMOS_OFFSET=144 diff --git a/src/arch/x86/postcar_loader.c b/src/arch/x86/postcar_loader.c index b53cbf82af..ee2c01b2fc 100644 --- a/src/arch/x86/postcar_loader.c +++ b/src/arch/x86/postcar_loader.c @@ -19,6 +19,7 @@ #include #include #include +#include #include #include #include @@ -208,6 +209,12 @@ void postcar_enable_tseg_cache(struct postcar_frame *pcf) MTRR_TYPE_WRBACK); } +static void postcar_cache_invalid(void) +{ + printk(BIOS_ERR, "postcar cache invalid.\n"); + board_reset(); +} + void run_postcar_phase(struct postcar_frame *pcf) { struct prog prog = @@ -222,6 +229,9 @@ void run_postcar_phase(struct postcar_frame *pcf) parameters between S3 resume and normal boot. On the platforms where the values are the same it's a nop. */ finalize_load(prog.arg, pcf->stack); + + if (prog_entry(&prog) == NULL) + postcar_cache_invalid(); } else load_postcar_cbfs(&prog, pcf); diff --git a/src/cpu/intel/haswell/Kconfig b/src/cpu/intel/haswell/Kconfig index d8d8b97004..a82198a878 100644 --- a/src/cpu/intel/haswell/Kconfig +++ b/src/cpu/intel/haswell/Kconfig @@ -35,16 +35,4 @@ config IED_REGION_SIZE config SMM_RESERVED_SIZE hex default 0x100000 - -config RESET_ON_INVALID_RAMSTAGE_CACHE - bool "Reset the system on S3 wake when ramstage cache invalid." - default n - help - The haswell romstage code caches the loaded ramstage program - in SMM space. On S3 wake the romstage will copy over a fresh - ramstage that was cached in the SMM space. This option determines - the action to take when the ramstage cache is invalid. If selected - the system will reset otherwise the ramstage will be reloaded from - cbfs. - endif diff --git a/src/drivers/intel/fsp1_1/Kconfig b/src/drivers/intel/fsp1_1/Kconfig index 989c4547f5..93af4f7360 100644 --- a/src/drivers/intel/fsp1_1/Kconfig +++ b/src/drivers/intel/fsp1_1/Kconfig @@ -82,10 +82,6 @@ config USE_GENERIC_FSP_CAR_INC The chipset can select this to use a generic cache_as_ram.inc file that should be good for all FSP based platforms. -config RESET_ON_INVALID_RAMSTAGE_CACHE - bool "Reset the system on S3 wake when ramstage cache invalid." - default n - config SKIP_FSP_CAR def_bool n help diff --git a/src/drivers/intel/fsp2_0/Kconfig b/src/drivers/intel/fsp2_0/Kconfig index 7ce7838642..a8b3ac43a5 100644 --- a/src/drivers/intel/fsp2_0/Kconfig +++ b/src/drivers/intel/fsp2_0/Kconfig @@ -117,10 +117,6 @@ config FSP_TEMP_RAM_SIZE stack with coreboot/bootloader. Sync this value with Platform FSP integration guide recommendation. -config RESET_ON_INVALID_RAMSTAGE_CACHE - bool "Reset the system on S3 wake when ramstage cache invalid." - default n - config FSP2_0_USES_TPM_MRC_HASH bool depends on TPM1 || TPM2 diff --git a/src/lib/prog_loaders.c b/src/lib/prog_loaders.c index 57874967ec..978ec16e6a 100644 --- a/src/lib/prog_loaders.c +++ b/src/lib/prog_loaders.c @@ -83,14 +83,6 @@ fail: int __weak prog_locate_hook(struct prog *prog) { return 0; } -static void ramstage_cache_invalid(void) -{ - printk(BIOS_ERR, "ramstage cache invalid.\n"); - if (CONFIG(RESET_ON_INVALID_RAMSTAGE_CACHE)) { - board_reset(); - } -} - static void run_ramstage_from_resume(struct prog *ramstage) { if (!romstage_handoff_is_resume()) @@ -105,7 +97,9 @@ static void run_ramstage_from_resume(struct prog *ramstage) printk(BIOS_DEBUG, "Jumping to image.\n"); prog_run(ramstage); } - ramstage_cache_invalid(); + + printk(BIOS_ERR, "ramstage cache invalid.\n"); + board_reset(); } static int load_relocatable_ramstage(struct prog *ramstage) diff --git a/src/soc/intel/apollolake/Makefile.inc b/src/soc/intel/apollolake/Makefile.inc index d63316969b..1fbdc91c72 100644 --- a/src/soc/intel/apollolake/Makefile.inc +++ b/src/soc/intel/apollolake/Makefile.inc @@ -74,8 +74,8 @@ ramstage-y += xhci.c postcar-y += mmap_boot.c postcar-y += spi.c postcar-y += i2c.c -postcar-$(CONFIG_RESET_ON_INVALID_RAMSTAGE_CACHE) += heci.c -postcar-$(CONFIG_RESET_ON_INVALID_RAMSTAGE_CACHE) += reset.c +postcar-y += heci.c +postcar-y += reset.c postcar-y += uart.c postcar-$(CONFIG_VBOOT_MEASURED_BOOT) += gspi.c diff --git a/src/soc/intel/baytrail/Kconfig b/src/soc/intel/baytrail/Kconfig index 94ed887d5c..4e9223750e 100644 --- a/src/soc/intel/baytrail/Kconfig +++ b/src/soc/intel/baytrail/Kconfig @@ -124,17 +124,6 @@ config DCACHE_BSP_STACK_SIZE hex default 0x2000 -config RESET_ON_INVALID_RAMSTAGE_CACHE - bool "Reset the system on S3 wake when ramstage cache invalid." - default n - help - The baytrail romstage code caches the loaded ramstage program - in SMM space. On S3 wake the romstage will copy over a fresh - ramstage that was cached in the SMM space. This option determines - the action to take when the ramstage cache is invalid. If selected - the system will reset otherwise the ramstage will be reloaded from - cbfs. - config ENABLE_BUILTIN_COM1 bool "Enable builtin COM1 Serial Port" default n diff --git a/src/soc/intel/braswell/Kconfig b/src/soc/intel/braswell/Kconfig index ba2ac68bf8..5b6a9237e7 100644 --- a/src/soc/intel/braswell/Kconfig +++ b/src/soc/intel/braswell/Kconfig @@ -104,17 +104,6 @@ config DCACHE_RAM_SIZE and/or romstage. Note DCACHE_RAM_SIZE and DCACHE_RAM_MRC_VAR_SIZE must add up to a power of 2. -config RESET_ON_INVALID_RAMSTAGE_CACHE - bool "Reset the system on S3 wake when ramstage cache invalid." - default n - help - The haswell romstage code caches the loaded ramstage program - in SMM space. On S3 wake the romstage will copy over a fresh - ramstage that was cached in the SMM space. This option determines - the action to take when the ramstage cache is invalid. If selected - the system will reset otherwise the ramstage will be reloaded from - cbfs. - config ENABLE_BUILTIN_COM1 bool "Enable builtin COM1 Serial Port" default n diff --git a/src/soc/intel/broadwell/Kconfig b/src/soc/intel/broadwell/Kconfig index 21c9b6f12a..f01777f4f0 100644 --- a/src/soc/intel/broadwell/Kconfig +++ b/src/soc/intel/broadwell/Kconfig @@ -166,16 +166,6 @@ config PRE_GRAPHICS_DELAY VBIOS. On those systems we need to wait for a bit before executing the VBIOS. -config RESET_ON_INVALID_RAMSTAGE_CACHE - bool "Reset the system on S3 wake when ramstage cache invalid." - default n - help - The romstage code caches the loaded ramstage program in SMM space. - On S3 wake the romstage will copy over a fresh ramstage that was - cached in the SMM space. This option determines the action to take - when the ramstage cache is invalid. If selected the system will - reset otherwise the ramstage will be reloaded from cbfs. - config INTEL_PCH_UART_CONSOLE bool "Use Serial IO UART for console" default n From badd4602293835404036ad35528452a397648b5b Mon Sep 17 00:00:00 2001 From: Marshall Dawson Date: Sun, 17 Nov 2019 16:42:20 -0700 Subject: [PATCH 0782/1242] soc/amd/picasso: Remove unused Kconfig options MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit No AGESA v5 binaryPI features are still present in the picasso directory. Remove the PI and S3 selects. Remove DCACHE symbols. Remove all vboot options until the new PSP-based solution is developed. Change-Id: I6542578afafc0ee3c3117a971b1a021dbe53f42c Signed-off-by: Marshall Dawson Reviewed-on: https://review.coreboot.org/c/coreboot/+/37488 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki --- src/soc/amd/picasso/Kconfig | 28 ---------------------------- 1 file changed, 28 deletions(-) diff --git a/src/soc/amd/picasso/Kconfig b/src/soc/amd/picasso/Kconfig index e192818a0b..56c7da776d 100644 --- a/src/soc/amd/picasso/Kconfig +++ b/src/soc/amd/picasso/Kconfig @@ -37,7 +37,6 @@ config CPU_SPECIFIC_OPTIONS select SOC_AMD_COMMON_BLOCK_SPI select TSC_SYNC_LFENCE select UDELAY_TSC - select SOC_AMD_PI select SOC_AMD_COMMON select SOC_AMD_COMMON_BLOCK select SOC_AMD_COMMON_BLOCK_IOMMU @@ -48,7 +47,6 @@ config CPU_SPECIFIC_OPTIONS select SOC_AMD_COMMON_BLOCK_PCI select SOC_AMD_COMMON_BLOCK_HDA select SOC_AMD_COMMON_BLOCK_SATA - select SOC_AMD_COMMON_BLOCK_S3 select BOOT_DEVICE_SUPPORTS_WRITES if BOOT_DEVICE_SPI_FLASH select BOOT_DEVICE_SPI_FLASH_RW_NOMMAP_EARLY if BOOT_DEVICE_SPI_FLASH select PARALLEL_MP @@ -57,36 +55,10 @@ config CPU_SPECIFIC_OPTIONS select SSE2 select RTC -config VBOOT - select VBOOT_SEPARATE_VERSTAGE - select VBOOT_STARTS_IN_BOOTBLOCK - select VBOOT_SAVE_RECOVERY_REASON_ON_REBOOT - select VBOOT_VBNV_CMOS - select VBOOT_VBNV_CMOS_BACKUP_TO_FLASH - config HAVE_BOOTBLOCK bool default n -# TODO: Sync these with definitions in PI vendorcode. -# DCACHE_RAM_BASE must equal BSP_STACK_BASE_ADDR. -# DCACHE_RAM_SIZE must equal BSP_STACK_SIZE. - -config DCACHE_RAM_BASE - hex - default 0x30000 - -config DCACHE_RAM_SIZE - hex - default 0x10000 - -config DCACHE_BSP_STACK_SIZE - hex - default 0x4000 - help - The amount of anticipated stack usage in CAR by bootblock and - other stages. - config PRERAM_CBMEM_CONSOLE_SIZE hex default 0x1600 From 8f454fd2ea86edf2a0646d28a1451116c3de7a9a Mon Sep 17 00:00:00 2001 From: Marshall Dawson Date: Sun, 17 Nov 2019 14:34:52 -0700 Subject: [PATCH 0783/1242] soc/amd/picasso: Reduce romstage.c MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Remove the old Stoney Ridge postcar stack frame setup. Reduce romstage.c to basic functionality. Until AGESA's reporting of memory configuration is available, use the TOM register as an indicator for the top of usable memory. Change-Id: I516b79c3e798f5fc68c2771b2f66034c6867b19e Signed-off-by: Marshall Dawson Reviewed-on: https://review.coreboot.org/c/coreboot/+/37489 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki --- src/soc/amd/picasso/romstage.c | 58 ++++++++-------------------------- 1 file changed, 14 insertions(+), 44 deletions(-) diff --git a/src/soc/amd/picasso/romstage.c b/src/soc/amd/picasso/romstage.c index 257ae6789d..8b8d3297ac 100644 --- a/src/soc/amd/picasso/romstage.c +++ b/src/soc/amd/picasso/romstage.c @@ -1,9 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2015-2016 Advanced Micro Devices, Inc. - * Copyright (C) 2015 Intel Corp. - * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; version 2 of the License. @@ -14,26 +11,18 @@ * GNU General Public License for more details. */ -#include #include #include #include #include -#include -#include #include #include #include #include -#include #include #include #include -#include #include -#include - -#include "chip.h" void __weak mainboard_romstage_entry_s3(int s3_resume) { @@ -42,52 +31,33 @@ void __weak mainboard_romstage_entry_s3(int s3_resume) asmlinkage void car_stage_entry(void) { - struct postcar_frame pcf; - uintptr_t top_of_ram; - int s3_resume = acpi_s3_resume_allowed() && acpi_is_wakeup_s3(); + uintptr_t top_of_mem; + int s3_resume; + post_code(0x40); console_init(); + post_code(0x41); + s3_resume = acpi_s3_resume_allowed() && acpi_is_wakeup_s3(); mainboard_romstage_entry_s3(s3_resume); elog_boot_notify(s3_resume); - if (!s3_resume) { - post_code(0x40); - } else { - printk(BIOS_INFO, "S3 detected\n"); - post_code(0x60); - } + post_code(0x42); + u32 val = cpuid_eax(1); + printk(BIOS_DEBUG, "Family_Model: %08x\n", val); post_code(0x43); + top_of_mem = ALIGN_DOWN(rdmsr(TOP_MEM).lo, 8 * MiB); + backup_top_of_low_cacheable(top_of_mem); + + post_code(0x44); if (cbmem_recovery(s3_resume)) printk(BIOS_CRIT, "Failed to recover cbmem\n"); if (romstage_handoff_init(s3_resume)) printk(BIOS_ERR, "Failed to set romstage handoff data\n"); - if (CONFIG(SMM_TSEG)) - smm_list_regions(); - - post_code(0x44); - if (postcar_frame_init(&pcf, 1 * KiB)) - die("Unable to initialize postcar frame.\n"); - - /* - * We need to make sure ramstage will be run cached. At this point exact - * location of ramstage in cbmem is not known. Instruct postcar to cache - * 16 megs under cbmem top which is a safe bet to cover ramstage. - */ - top_of_ram = (uintptr_t) cbmem_top(); - postcar_frame_add_mtrr(&pcf, top_of_ram - 16*MiB, 16*MiB, - MTRR_TYPE_WRBACK); - - /* Cache the memory-mapped boot media. */ - postcar_frame_add_romcache(&pcf, MTRR_TYPE_WRPROT); - - /* Cache the TSEG region */ - postcar_enable_tseg_cache(&pcf); - post_code(0x45); - run_postcar_phase(&pcf); + run_ramstage(); - post_code(0x50); /* Should never see this post code. */ + post_code(0x50); /* Should never see this post code. */ } From d4823664a895546ac699cc70e41a94f943b364f8 Mon Sep 17 00:00:00 2001 From: Edward O'Callaghan Date: Sun, 15 Dec 2019 23:29:49 +1100 Subject: [PATCH 0784/1242] mainboard/google/puff: Clean up dt for pci 15.2 Seems nothing special is needed here from coreboot. V.2: Fix typo as well in speed map. BRANCH=none BUG=b:143047058 TEST=./util/abuild/abuild -p none -t google/hatch -x -a Change-Id: Ief750f98677b2017af78fb0b5bc98e1492dedbe4 Signed-off-by: Edward O'Callaghan Reviewed-on: https://review.coreboot.org/c/coreboot/+/37736 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh --- .../google/hatch/variants/puff/overridetree.cb | 13 ++----------- 1 file changed, 2 insertions(+), 11 deletions(-) diff --git a/src/mainboard/google/hatch/variants/puff/overridetree.cb b/src/mainboard/google/hatch/variants/puff/overridetree.cb index 384bb9a6d0..ca6c818128 100644 --- a/src/mainboard/google/hatch/variants/puff/overridetree.cb +++ b/src/mainboard/google/hatch/variants/puff/overridetree.cb @@ -86,7 +86,7 @@ chip soc/intel/cannonlake .rise_time_ns = 0, .fall_time_ns = 0, }, - .i2c[1] = { + .i2c[2] = { .speed = I2C_SPEED_FAST, .rise_time_ns = 0, .fall_time_ns = 0, @@ -111,16 +111,7 @@ chip soc/intel/cannonlake # RFU - Reserved for Future Use. end # I2C #0 device pci 15.1 off end # I2C #1 - device pci 15.2 on -# chip drivers/i2c/generic -# register "name" = ""PS175"" -# register "desc" = ""PCON PS175"" -# register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C10)" -# register "stop_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C11)" -# register "has_power_resource" = "1" -# device i2c 15 on end -# end - end # I2C #2 + device pci 15.2 on end # I2C #2, PCON PS175. device pci 15.3 on # chip drivers/i2c/generic # register "name" = ""RTD21"" From b61f33cd484ece8c86acdce2740d0ab4018f3f30 Mon Sep 17 00:00:00 2001 From: Edward O'Callaghan Date: Wed, 18 Dec 2019 11:04:20 +1100 Subject: [PATCH 0785/1242] mainboard/google/puff: Enable pcie7 ep in dt Missing bus init for RTL8111H ethernet chip hanging on bus. V.2: Include admendments from Kangheui. BRANCH=none BUG=b:146437819 TEST=./util/abuild/abuild -p none -t google/hatch -x -a Change-Id: I22aba312f183ea05eeb81d326ca0c05ce340a2e8 Signed-off-by: Edward O'Callaghan Reviewed-on: https://review.coreboot.org/c/coreboot/+/37804 Tested-by: build bot (Jenkins) Reviewed-by: Kangheui Won Reviewed-by: Patrick Georgi --- src/mainboard/google/hatch/Kconfig | 2 ++ src/mainboard/google/hatch/variants/puff/overridetree.cb | 8 ++++++++ 2 files changed, 10 insertions(+) diff --git a/src/mainboard/google/hatch/Kconfig b/src/mainboard/google/hatch/Kconfig index 90c5ed3427..3427ced44d 100644 --- a/src/mainboard/google/hatch/Kconfig +++ b/src/mainboard/google/hatch/Kconfig @@ -22,6 +22,8 @@ config BOARD_GOOGLE_BASEBOARD_HATCH select MB_HAS_ACTIVE_HIGH_SD_PWR_ENABLE select SOC_INTEL_COMETLAKE select SYSTEM_TYPE_LAPTOP + select RT8168_GET_MAC_FROM_VPD if BOARD_GOOGLE_PUFF + select RT8168_SET_LED_MODE if BOARD_GOOGLE_PUFF if BOARD_GOOGLE_BASEBOARD_HATCH diff --git a/src/mainboard/google/hatch/variants/puff/overridetree.cb b/src/mainboard/google/hatch/variants/puff/overridetree.cb index ca6c818128..d362b22770 100644 --- a/src/mainboard/google/hatch/variants/puff/overridetree.cb +++ b/src/mainboard/google/hatch/variants/puff/overridetree.cb @@ -103,6 +103,13 @@ chip soc/intel/cannonlake }, }" + # PCIe port 7 for LAN + register "PcieRpEnable[6]" = "1" + register "PcieRpLtrEnable[6]" = "1" + # Uses CLK SRC 0 + register "PcieClkSrcUsage[0]" = "6" + register "PcieClkSrcClkReq[0]" = "0" + # GPIO for SD card detect register "sdcard_cd_gpio" = "vSD3_CD_B" @@ -134,6 +141,7 @@ chip soc/intel/cannonlake end end #I2C #4 device pci 1a.0 on end # eMMC + device pci 1c.6 on end # PCI Express Port 7, RTL8111H Ethernet NIC. device pci 1e.3 off end # GSPI #1 end From 40a1f70bb0c844f20ae2201a32264a4d6a791668 Mon Sep 17 00:00:00 2001 From: Kangheui Won Date: Thu, 19 Dec 2019 13:24:29 -0800 Subject: [PATCH 0786/1242] mainboard/google/puff: Add extra USB configuration Adding extra USB configuration since Puff has different USB ports compared to hatch BRANCH=none BUG=b:146437609 TEST=none Change-Id: I42ef6b6b718274953711c84ebe90971f108501fa Signed-off-by: Kangheui Won Reviewed-on: https://review.coreboot.org/c/coreboot/+/37853 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan --- .../hatch/variants/puff/overridetree.cb | 34 +++++++++++++++++++ 1 file changed, 34 insertions(+) diff --git a/src/mainboard/google/hatch/variants/puff/overridetree.cb b/src/mainboard/google/hatch/variants/puff/overridetree.cb index d362b22770..a24d7fc80a 100644 --- a/src/mainboard/google/hatch/variants/puff/overridetree.cb +++ b/src/mainboard/google/hatch/variants/puff/overridetree.cb @@ -15,6 +15,11 @@ chip soc/intel/cannonlake [PchSerialIoIndexUART2] = PchSerialIoDisabled, }" + # USB configuration + register "usb2_ports[4]" = "USB2_PORT_SHORT(OC_SKIP)" + register "usb2_ports[6]" = "USB2_PORT_EMPTY" + register "usb3_ports[5]" = "USB3_PORT_DEFAULT(OC_SKIP)" + # Enable eMMC HS400 register "ScsEmmcHs400Enabled" = "1" @@ -114,6 +119,35 @@ chip soc/intel/cannonlake register "sdcard_cd_gpio" = "vSD3_CD_B" device domain 0 on + device pci 14.0 on + chip drivers/usb/acpi + device usb 0.0 on + chip drivers/usb/acpi + register "desc" = ""Type-A Port 4"" + register "type" = "UPC_TYPE_A" + device usb 2.4 on end + end + chip drivers/usb/acpi + register "desc" = ""Type-A Port 0"" + register "type" = "UPC_TYPE_A" + device usb 2.5 on end + end + chip drivers/usb/acpi + device usb 2.6 off end + end + chip drivers/usb/acpi + register "desc" = ""Type-A Port 0"" + register "type" = "UPC_TYPE_USB3_A" + device usb 3.4 on end + end + chip drivers/usb/acpi + register "desc" = ""Type-A Port 4"" + register "type" = "UPC_TYPE_USB3_A" + device usb 3.5 on end + end + end + end + end # USB xHCI device pci 15.0 off # RFU - Reserved for Future Use. end # I2C #0 From b4f1ecb3c7c0e8cc4bfefaf070e0e70b7d7bd2b9 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ky=C3=B6sti=20M=C3=A4lkki?= Date: Sun, 15 Dec 2019 21:05:40 +0200 Subject: [PATCH 0787/1242] AGESA fam14: Remove early p-state setting MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit No improvement was measured with this applied. Change-Id: I99166e03f2580828c66305326f5141d956707f08 Signed-off-by: Kyösti Mälkki Reviewed-on: https://review.coreboot.org/c/coreboot/+/37754 Reviewed-by: Michał Żygowski Tested-by: build bot (Jenkins) --- src/cpu/amd/agesa/family14/fixme.c | 4 ---- 1 file changed, 4 deletions(-) diff --git a/src/cpu/amd/agesa/family14/fixme.c b/src/cpu/amd/agesa/family14/fixme.c index c2e859e229..2b412fac1d 100644 --- a/src/cpu/amd/agesa/family14/fixme.c +++ b/src/cpu/amd/agesa/family14/fixme.c @@ -92,10 +92,6 @@ void amd_initmmio(void) LibAmdMsrWrite(MTRR_PHYS_BASE(6), &MsrReg, &StdHeader); MsrReg = ((1ULL << CONFIG_CPU_ADDR_BITS) - CACHE_ROM_SIZE) | MTRR_PHYS_MASK_VALID; LibAmdMsrWrite(MTRR_PHYS_MASK(6), &MsrReg, &StdHeader); - - /* Set P-state 0 (1600 MHz) early to save a few ms of boot time */ - MsrReg = 0; - LibAmdMsrWrite(PS_CTL_REG, &MsrReg, &StdHeader); } void amd_initenv(void) From fa0df7d316fc9b4be825b7ad60ada844660202c6 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ky=C3=B6sti=20M=C3=A4lkki?= Date: Sun, 15 Dec 2019 21:05:40 +0200 Subject: [PATCH 0788/1242] AGESA fam14: Remove early PCI subsystem ID setting MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Change-Id: Id4e95c68517b01647049b5cbd50bf5a3974a9c3a Signed-off-by: Kyösti Mälkki Reviewed-on: https://review.coreboot.org/c/coreboot/+/37816 Tested-by: build bot (Jenkins) Reviewed-by: Michał Żygowski --- src/cpu/amd/agesa/family14/fixme.c | 14 -------------- 1 file changed, 14 deletions(-) diff --git a/src/cpu/amd/agesa/family14/fixme.c b/src/cpu/amd/agesa/family14/fixme.c index 2b412fac1d..c9d30396aa 100644 --- a/src/cpu/amd/agesa/family14/fixme.c +++ b/src/cpu/amd/agesa/family14/fixme.c @@ -18,10 +18,6 @@ #include #include -/* Define AMD Ontario APPU SSID/SVID */ -#define AMD_APU_SVID 0x1022 -#define AMD_APU_SSID 0x1234 - void amd_initcpuio(void) { UINT64 MsrReg; @@ -68,8 +64,6 @@ void amd_initcpuio(void) void amd_initmmio(void) { UINT64 MsrReg; - UINT32 PciData; - PCI_ADDR PciAddress; AMD_CONFIG_PARAMS StdHeader; /* @@ -79,14 +73,6 @@ void amd_initmmio(void) MsrReg = CONFIG_MMCONF_BASE_ADDRESS | (LibAmdBitScanReverse(CONFIG_MMCONF_BUS_NUMBER) << 2) | 1; LibAmdMsrWrite(MMIO_CONF_BASE, &MsrReg, &StdHeader); - /* Set Ontario Link Data */ - PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0, 0, 0xE0); - PciData = 0x01308002; - LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); - PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0, 0, 0xE4); - PciData = (AMD_APU_SSID << 0x10) | AMD_APU_SVID; - LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); - /* Set ROM cache onto WP to decrease post time */ MsrReg = (0x0100000000ull - CACHE_ROM_SIZE) | MTRR_TYPE_WRPROT; LibAmdMsrWrite(MTRR_PHYS_BASE(6), &MsrReg, &StdHeader); From fedaac84da5bcfd035e0e348150db8cf3d800726 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ky=C3=B6sti=20M=C3=A4lkki?= Date: Sun, 15 Dec 2019 21:37:38 +0200 Subject: [PATCH 0789/1242] AGESA,binaryPI: Enable lapic early for udelay() MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Change-Id: I7200ac0256748d9372fc39be27b86d1c93b38321 Signed-off-by: Kyösti Mälkki Reviewed-on: https://review.coreboot.org/c/coreboot/+/37756 Tested-by: build bot (Jenkins) Reviewed-by: Michał Żygowski Reviewed-by: Angel Pons Reviewed-by: HAOUAS Elyes --- src/cpu/amd/pi/00630F01/fixme.c | 6 ------ src/cpu/amd/pi/00660F01/fixme.c | 6 ------ src/cpu/amd/pi/00730F01/fixme.c | 6 ------ src/drivers/amd/agesa/bootblock.c | 7 +++++++ 4 files changed, 7 insertions(+), 18 deletions(-) diff --git a/src/cpu/amd/pi/00630F01/fixme.c b/src/cpu/amd/pi/00630F01/fixme.c index 12f8062dfa..d94215a44b 100644 --- a/src/cpu/amd/pi/00630F01/fixme.c +++ b/src/cpu/amd/pi/00630F01/fixme.c @@ -85,10 +85,4 @@ void amd_initmmio(void) LibAmdMsrWrite(MTRR_PHYS_BASE(6), &MsrReg, &StdHeader); MsrReg = ((1ULL << CONFIG_CPU_ADDR_BITS) - CACHE_ROM_SIZE) | 0x800ull; LibAmdMsrWrite(MTRR_PHYS_MASK(6), &MsrReg, &StdHeader); - - if (CONFIG(UDELAY_LAPIC)){ - LibAmdMsrRead(0x1B, &MsrReg, &StdHeader); - MsrReg |= 1 << 11; - LibAmdMsrWrite(0x1B, &MsrReg, &StdHeader); - } } diff --git a/src/cpu/amd/pi/00660F01/fixme.c b/src/cpu/amd/pi/00660F01/fixme.c index 237d52b2c1..7d71e2ea1a 100644 --- a/src/cpu/amd/pi/00660F01/fixme.c +++ b/src/cpu/amd/pi/00660F01/fixme.c @@ -91,10 +91,4 @@ void amd_initmmio(void) LibAmdMsrWrite(MTRR_PHYS_BASE(6), &MsrReg, &StdHeader); MsrReg = ((1ULL << CONFIG_CPU_ADDR_BITS) - CACHE_ROM_SIZE) | 0x800ull; LibAmdMsrWrite(MTRR_PHYS_MASK(6), &MsrReg, &StdHeader); - - if (CONFIG(UDELAY_LAPIC)) { - LibAmdMsrRead(0x1B, &MsrReg, &StdHeader); - MsrReg |= 1 << 11; - LibAmdMsrWrite(0x1B, &MsrReg, &StdHeader); - } } diff --git a/src/cpu/amd/pi/00730F01/fixme.c b/src/cpu/amd/pi/00730F01/fixme.c index a0621cbb7f..7edd1b8fa2 100644 --- a/src/cpu/amd/pi/00730F01/fixme.c +++ b/src/cpu/amd/pi/00730F01/fixme.c @@ -96,10 +96,4 @@ void amd_initmmio(void) LibAmdMsrWrite(MTRR_PHYS_BASE(6), &MsrReg, &StdHeader); MsrReg = ((1ULL << CONFIG_CPU_ADDR_BITS) - CACHE_ROM_SIZE) | 0x800ull; LibAmdMsrWrite(MTRR_PHYS_MASK(6), &MsrReg, &StdHeader); - - if (CONFIG(UDELAY_LAPIC)) { - LibAmdMsrRead(0x1B, &MsrReg, &StdHeader); - MsrReg |= 1 << 11; - LibAmdMsrWrite(0x1B, &MsrReg, &StdHeader); - } } diff --git a/src/drivers/amd/agesa/bootblock.c b/src/drivers/amd/agesa/bootblock.c index 3763b98a3a..91fcc6b994 100644 --- a/src/drivers/amd/agesa/bootblock.c +++ b/src/drivers/amd/agesa/bootblock.c @@ -18,6 +18,7 @@ #include #include #include +#include #define EARLY_VMTRR_FLASH 6 @@ -33,6 +34,9 @@ asmlinkage void bootblock_c_entry(uint64_t base_timestamp) enable_pci_mmconf(); set_early_mtrrs(); + if (CONFIG(UDELAY_LAPIC)) + enable_lapic(); + bootblock_main_with_basetime(base_timestamp); } @@ -41,6 +45,9 @@ asmlinkage void ap_bootblock_c_entry(void) enable_pci_mmconf(); set_early_mtrrs(); + if (CONFIG(UDELAY_LAPIC)) + enable_lapic(); + void (*ap_romstage_entry)(void) = get_ap_entry_ptr(); ap_romstage_entry(); /* execution does not return */ halt(); From b2f3698781f8a77e4d08cdde841d8a0785c3592b Mon Sep 17 00:00:00 2001 From: Eric Lai Date: Fri, 13 Dec 2019 17:37:45 +0800 Subject: [PATCH 0790/1242] libpayload/drivers/i8042: add error messages to i8042_probe Print error message before error return for better debugging. Signed-off-by: Eric Lai Change-Id: I52039dcab72c6295dfb6b887a7000a6d2bd050ee Reviewed-on: https://review.coreboot.org/c/coreboot/+/37689 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel Reviewed-by: Mathew King --- payloads/libpayload/drivers/i8042/i8042.c | 11 +++++++++-- 1 file changed, 9 insertions(+), 2 deletions(-) diff --git a/payloads/libpayload/drivers/i8042/i8042.c b/payloads/libpayload/drivers/i8042/i8042.c index e97fab8429..ee9f5fd405 100644 --- a/payloads/libpayload/drivers/i8042/i8042.c +++ b/payloads/libpayload/drivers/i8042/i8042.c @@ -197,23 +197,29 @@ u8 i8042_probe(void) /* If 0x64 returns 0xff, then we have no keyboard * controller */ - if (read_status() == 0xFF) + if (read_status() == 0xFF) { + printf("ERROR: No keyboard controller found!\n"); return 0; + } - if (!i8042_wait_cmd_rdy()) + if (!i8042_wait_cmd_rdy()) { + printf("ERROR: i8042_wait_cmd_rdy failed!\n"); return 0; + } kbc_init = 1; /* Disable first device */ if (i8042_cmd(I8042_CMD_DIS_KB) != 0) { kbc_init = 0; + printf("ERROR: i8042_cmd I8042_CMD_DIS_KB failed!\n"); return 0; } /* Disable second device */ if (i8042_cmd(I8042_CMD_DIS_AUX) != 0) { kbc_init = 0; + printf("ERROR: i8042_cmd I8042_CMD_DIS_AUX failed!\n"); return 0; } @@ -225,6 +231,7 @@ u8 i8042_probe(void) if (i8042_cmd_with_response(I8042_CMD_SELF_TEST) != I8042_SELF_TEST_RSP) { kbc_init = 0; + printf("ERROR: i8042_cmd I8042_CMD_SELF_TEST failed!\n"); return 0; } From 836b8d2e4509fb041a15df6d1ce3b20e205260bb Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ky=C3=B6sti=20M=C3=A4lkki?= Date: Mon, 16 Dec 2019 06:54:11 +0200 Subject: [PATCH 0791/1242] drivers/pc80: Move normal/fallback mechanism outside __ROMCC__ MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Change-Id: I840885ca543375c77b7406434fd8bb4085e26938 Signed-off-by: Kyösti Mälkki Reviewed-on: https://review.coreboot.org/c/coreboot/+/37759 Tested-by: build bot (Jenkins) Reviewed-by: HAOUAS Elyes --- src/drivers/pc80/rtc/mc146818rtc_boot.c | 68 +++++++++++++++--- src/drivers/pc80/rtc/mc146818rtc_romcc.c | 87 ------------------------ src/include/pc80/mc146818rtc.h | 8 +-- 3 files changed, 62 insertions(+), 101 deletions(-) delete mode 100644 src/drivers/pc80/rtc/mc146818rtc_romcc.c diff --git a/src/drivers/pc80/rtc/mc146818rtc_boot.c b/src/drivers/pc80/rtc/mc146818rtc_boot.c index 0ac06b3152..3000946413 100644 --- a/src/drivers/pc80/rtc/mc146818rtc_boot.c +++ b/src/drivers/pc80/rtc/mc146818rtc_boot.c @@ -12,17 +12,13 @@ */ #include -#ifdef __ROMCC__ -#include -#else #include -#endif #include +#include #if CONFIG(USE_OPTION_TABLE) #include #endif -int cmos_error(void); int cmos_error(void) { unsigned char reg_d; @@ -31,7 +27,6 @@ int cmos_error(void) return (reg_d & RTC_VRT) == 0; } -int cmos_chksum_valid(void); int cmos_chksum_valid(void) { #if CONFIG(USE_OPTION_TABLE) @@ -60,12 +55,8 @@ void sanitize_cmos(void) CONFIG(STATIC_OPTION_TABLE)) { size_t length = 128; const unsigned char *cmos_default = -#ifdef __ROMCC__ - walkcbfs("cmos.default"); -#else cbfs_boot_map_with_leak("cmos.default", CBFS_COMPONENT_CMOS_DEFAULT, &length); -#endif if (cmos_default) { size_t i; cmos_disable_rtc(); @@ -76,3 +67,60 @@ void sanitize_cmos(void) } } #endif + +#if CONFIG_MAX_REBOOT_CNT > 15 +#error "CONFIG_MAX_REBOOT_CNT too high" +#endif + +static inline int boot_count(uint8_t rtc_byte) +{ + return rtc_byte >> 4; +} + +static inline uint8_t increment_boot_count(uint8_t rtc_byte) +{ + return rtc_byte + (1 << 4); +} + +static inline uint8_t boot_set_fallback(uint8_t rtc_byte) +{ + return rtc_byte & ~RTC_BOOT_NORMAL; +} + +static inline int boot_use_normal(uint8_t rtc_byte) +{ + return rtc_byte & RTC_BOOT_NORMAL; +} + +int do_normal_boot(void) +{ + unsigned char byte; + + if (cmos_error() || !cmos_chksum_valid()) { + /* Invalid CMOS checksum detected! + * Force fallback boot... + */ + byte = cmos_read(RTC_BOOT_BYTE); + byte &= boot_set_fallback(byte) & 0x0f; + byte |= 0xf << 4; + cmos_write(byte, RTC_BOOT_BYTE); + } + + /* The RTC_BOOT_BYTE is now o.k. see where to go. */ + byte = cmos_read(RTC_BOOT_BYTE); + + /* Are we attempting to boot normally? */ + if (boot_use_normal(byte)) { + /* Are we already at the max count? */ + if (boot_count(byte) < CONFIG_MAX_REBOOT_CNT) + byte = increment_boot_count(byte); + else + byte = boot_set_fallback(byte); + } + + /* Save the boot byte */ + cmos_write(byte, RTC_BOOT_BYTE); + + /* Return selected code path for this boot attempt */ + return boot_use_normal(byte); +} diff --git a/src/drivers/pc80/rtc/mc146818rtc_romcc.c b/src/drivers/pc80/rtc/mc146818rtc_romcc.c deleted file mode 100644 index 4405443501..0000000000 --- a/src/drivers/pc80/rtc/mc146818rtc_romcc.c +++ /dev/null @@ -1,87 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include - -#include "mc146818rtc_boot.c" - -#if CONFIG_MAX_REBOOT_CNT > 15 -#error "CONFIG_MAX_REBOOT_CNT too high" -#endif - -static inline __attribute__((unused)) int boot_count(uint8_t rtc_byte) -{ - return rtc_byte >> 4; -} - -static inline __attribute__((unused)) uint8_t increment_boot_count(uint8_t rtc_byte) -{ - return rtc_byte + (1 << 4); -} - -static inline __attribute__((unused)) uint8_t boot_set_fallback(uint8_t rtc_byte) -{ - return rtc_byte & ~RTC_BOOT_NORMAL; -} - -static inline __attribute__((unused)) int boot_use_normal(uint8_t rtc_byte) -{ - return rtc_byte & RTC_BOOT_NORMAL; -} - -static inline __attribute__((unused)) int do_normal_boot(void) -{ - unsigned char byte; - - if (cmos_error() || !cmos_chksum_valid()) { - /* Invalid CMOS checksum detected! - * Force fallback boot... - */ - byte = cmos_read(RTC_BOOT_BYTE); - byte &= boot_set_fallback(byte) & 0x0f; - byte |= 0xf << 4; - cmos_write(byte, RTC_BOOT_BYTE); - } - - /* The RTC_BOOT_BYTE is now o.k. see where to go. */ - byte = cmos_read(RTC_BOOT_BYTE); - - /* Are we attempting to boot normally? */ - if (boot_use_normal(byte)) { - /* Are we already at the max count? */ - if (boot_count(byte) < CONFIG_MAX_REBOOT_CNT) - byte = increment_boot_count(byte); - else - byte = boot_set_fallback(byte); - } - - /* Save the boot byte */ - cmos_write(byte, RTC_BOOT_BYTE); - - /* Return selected code path for this boot attempt */ - return boot_use_normal(byte); -} - -unsigned int read_option_lowlevel(unsigned int start, unsigned int size, unsigned int def) -{ -#if CONFIG(USE_OPTION_TABLE) - unsigned int byte; - - byte = cmos_read(start/8); - return (byte >> (start & 7U)) & ((1U << size) - 1U); -#else - return def; -#endif -} diff --git a/src/include/pc80/mc146818rtc.h b/src/include/pc80/mc146818rtc.h index 6fa5e46404..afa4d9714c 100644 --- a/src/include/pc80/mc146818rtc.h +++ b/src/include/pc80/mc146818rtc.h @@ -178,18 +178,18 @@ static inline void cmos_write32(u8 offset, u32 value) cmos_write((value >> (i << 3)) & 0xff, offset + i); } -#if !defined(__ROMCC__) void cmos_init(bool invalid); void cmos_check_update_date(void); +int cmos_error(void); +int cmos_chksum_valid(void); enum cb_err set_option(const char *name, void *val); enum cb_err get_option(void *dest, const char *name); unsigned int read_option_lowlevel(unsigned int start, unsigned int size, unsigned int def); -#else /* defined(__ROMCC__) */ -#include -#endif /* !defined(__ROMCC__) */ +int do_normal_boot(void); + #define read_option(name, default) read_option_lowlevel(CMOS_VSTART_ ##name, \ CMOS_VLEN_ ##name, (default)) From f97c1c9d86ff56ba9d1de4fc7c9499742224d365 Mon Sep 17 00:00:00 2001 From: Elyes HAOUAS Date: Tue, 3 Dec 2019 18:22:06 +0100 Subject: [PATCH 0792/1242] {nb,soc}: Replace min/max() with MIN/MAX() MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Use MIN() and MAX() defined in commonlib/helpers.h Change-Id: I02d0a47937bc2d6ab2cd01995a2c6b6db245da15 Signed-off-by: Elyes HAOUAS Reviewed-on: https://review.coreboot.org/c/coreboot/+/37454 Reviewed-by: Kyösti Mälkki Reviewed-by: Patrick Georgi Tested-by: build bot (Jenkins) --- src/northbridge/intel/pineview/raminit.c | 19 ++++++----- .../intel/sandybridge/raminit_common.c | 33 ++++++++++--------- src/soc/amd/common/block/spi/fch_spi_flash.c | 5 +-- .../common/block/fast_spi/fast_spi_flash.c | 5 +-- src/soc/intel/common/smbios.c | 3 +- src/soc/intel/quark/i2c.c | 3 +- src/soc/intel/skylake/elog.c | 3 +- 7 files changed, 39 insertions(+), 32 deletions(-) diff --git a/src/northbridge/intel/pineview/raminit.c b/src/northbridge/intel/pineview/raminit.c index 7f59d9197b..720bd6436e 100644 --- a/src/northbridge/intel/pineview/raminit.c +++ b/src/northbridge/intel/pineview/raminit.c @@ -17,6 +17,7 @@ #include #include #include +#include #include #include #include @@ -364,15 +365,15 @@ static void sdram_detect_smallest_params(struct sysinfo *s) u32 maxtrtp = 0; FOR_EACH_POPULATED_DIMM(s->dimms, i) { - maxtras = max(maxtras, s->dimms[i].spd_data[30] * 1000); - maxtrp = max(maxtrp, (s->dimms[i].spd_data[27] * 1000) >> 2); - maxtrcd = max(maxtrcd, (s->dimms[i].spd_data[29] * 1000) >> 2); - maxtwr = max(maxtwr, (s->dimms[i].spd_data[36] * 1000) >> 2); - maxtrfc = max(maxtrfc, s->dimms[i].spd_data[42] * 1000 + + maxtras = MAX(maxtras, s->dimms[i].spd_data[30] * 1000); + maxtrp = MAX(maxtrp, (s->dimms[i].spd_data[27] * 1000) >> 2); + maxtrcd = MAX(maxtrcd, (s->dimms[i].spd_data[29] * 1000) >> 2); + maxtwr = MAX(maxtwr, (s->dimms[i].spd_data[36] * 1000) >> 2); + maxtrfc = MAX(maxtrfc, s->dimms[i].spd_data[42] * 1000 + (s->dimms[i].spd_data[40] & 0xf)); - maxtwtr = max(maxtwtr, (s->dimms[i].spd_data[37] * 1000) >> 2); - maxtrrd = max(maxtrrd, (s->dimms[i].spd_data[28] * 1000) >> 2); - maxtrtp = max(maxtrtp, (s->dimms[i].spd_data[38] * 1000) >> 2); + maxtwtr = MAX(maxtwtr, (s->dimms[i].spd_data[37] * 1000) >> 2); + maxtrrd = MAX(maxtrrd, (s->dimms[i].spd_data[28] * 1000) >> 2); + maxtrtp = MAX(maxtrtp, (s->dimms[i].spd_data[38] * 1000) >> 2); } /* * TODO: on ddr3 there might be some minimal required values for some @@ -456,7 +457,7 @@ static void sdram_detect_ram_speed(struct sysinfo *s) // Start with fastest common CAS cas = 0; highcas = msbp; - lowcas = max(lsbp, 5); + lowcas = MAX(lsbp, 5); while (cas == 0 && highcas >= lowcas) { FOR_EACH_POPULATED_DIMM(s->dimms, i) { diff --git a/src/northbridge/intel/sandybridge/raminit_common.c b/src/northbridge/intel/sandybridge/raminit_common.c index 4974173ef1..44e5d3a8ff 100644 --- a/src/northbridge/intel/sandybridge/raminit_common.c +++ b/src/northbridge/intel/sandybridge/raminit_common.c @@ -15,6 +15,7 @@ * GNU General Public License for more details. */ +#include #include #include #include @@ -1461,7 +1462,7 @@ static void test_timC(ramctr_timing * ctrl, int channel, int slotrank) /* DRAM command ACT */ MCHBAR32(0x4220 + 0x400 * channel) = 0x1f006; MCHBAR32(0x4230 + 0x400 * channel) = - (max((ctrl->tFAW >> 2) + 1, ctrl->tRRD) << 10) + (MAX((ctrl->tFAW >> 2) + 1, ctrl->tRRD) << 10) | 4 | (ctrl->tRCD << 16); MCHBAR32(0x4200 + 0x400 * channel) = (slotrank << 24) | (6 << 16); MCHBAR32(0x4210 + 0x400 * channel) = 0x244; @@ -1499,7 +1500,7 @@ static void test_timC(ramctr_timing * ctrl, int channel, int slotrank) /* DRAM command ACT */ MCHBAR32(0x4224 + 0x400 * channel) = 0x1f006; MCHBAR32(0x4234 + 0x400 * channel) = - (max(ctrl->tRRD, (ctrl->tFAW >> 2) + 1) << 10) + (MAX(ctrl->tRRD, (ctrl->tFAW >> 2) + 1) << 10) | 8 | (ctrl->CAS << 16); MCHBAR32(0x4204 + 0x400 * channel) = (slotrank << 24) | 0x60000; MCHBAR32(0x4214 + 0x400 * channel) = 0x244; @@ -1507,7 +1508,7 @@ static void test_timC(ramctr_timing * ctrl, int channel, int slotrank) /* DRAM command RD */ MCHBAR32(0x4228 + 0x400 * channel) = 0x1f105; MCHBAR32(0x4238 + 0x400 * channel) = - 0x40011f4 | (max(ctrl->tRTP, 8) << 16); + 0x40011f4 | (MAX(ctrl->tRTP, 8) << 16); MCHBAR32(0x4208 + 0x400 * channel) = (slotrank << 24); MCHBAR32(0x4218 + 0x400 * channel) = 0x242; @@ -2101,7 +2102,7 @@ static int test_320c(ramctr_timing * ctrl, int channel, int slotrank) /* DRAM command ACT */ MCHBAR32(0x4220 + 0x400 * channel) = 0x1f006; MCHBAR32(0x4230 + 0x400 * channel) = - ((max(ctrl->tRRD, (ctrl->tFAW >> 2) + 1)) << 10) + ((MAX(ctrl->tRRD, (ctrl->tFAW >> 2) + 1)) << 10) | 8 | (ctrl->tRCD << 16); MCHBAR32(0x4200 + 0x400 * channel) = (slotrank << 24) | ctr | 0x60000; @@ -2118,7 +2119,7 @@ static int test_320c(ramctr_timing * ctrl, int channel, int slotrank) /* DRAM command RD */ MCHBAR32(0x4228 + 0x400 * channel) = 0x1f105; MCHBAR32(0x4238 + 0x400 * channel) = - 0x4001020 | (max(ctrl->tRTP, 8) << 16); + 0x4001020 | (MAX(ctrl->tRTP, 8) << 16); MCHBAR32(0x4208 + 0x400 * channel) = (slotrank << 24); MCHBAR32(0x4248 + 0x400 * channel) = 0x389abcd; MCHBAR32(0x4218 + 0x400 * channel) = 0x20e42; @@ -2662,7 +2663,7 @@ static int discover_edges_write_real(ramctr_timing *ctrl, int channel, MCHBAR32(0x4220 + 0x400 * channel) = 0x1f006; MCHBAR32(0x4230 + 0x400 * channel) = 0x4 | (ctrl->tRCD << 16) | - (max(ctrl->tRRD, (ctrl->tFAW >> 2) + 1) + (MAX(ctrl->tRRD, (ctrl->tFAW >> 2) + 1) << 10); MCHBAR32(0x4200 + 0x400 * channel) = (slotrank << 24) | 0x60000; @@ -2679,7 +2680,7 @@ static int discover_edges_write_real(ramctr_timing *ctrl, int channel, /* DRAM command RD */ MCHBAR32(0x4228 + 0x400 * channel) = 0x1f105; MCHBAR32(0x4238 + 0x400 * channel) = - 0x4005020 | (max(ctrl->tRTP, 8) << 16); + 0x4005020 | (MAX(ctrl->tRTP, 8) << 16); MCHBAR32(0x4208 + 0x400 * channel) = slotrank << 24; MCHBAR32(0x4218 + 0x400 * channel) = 0x242; @@ -2717,9 +2718,9 @@ static int discover_edges_write_real(ramctr_timing *ctrl, int channel, rn.end, rn.start + ctrl->edge_offset[i], rn.end - ctrl->edge_offset[i]); lower[lane] = - max(rn.start + ctrl->edge_offset[i], lower[lane]); + MAX(rn.start + ctrl->edge_offset[i], lower[lane]); upper[lane] = - min(rn.end - ctrl->edge_offset[i], upper[lane]); + MIN(rn.end - ctrl->edge_offset[i], upper[lane]); edges[lane] = (lower[lane] + upper[lane]) / 2; if (rn.all || (lower[lane] > upper[lane])) { printk(BIOS_EMERG, "edge write discovery failed: %d, %d, %d\n", @@ -2787,7 +2788,7 @@ static void test_timC_write(ramctr_timing *ctrl, int channel, int slotrank) /* DRAM command ACT */ MCHBAR32(0x4220 + 0x400 * channel) = 0x1f006; MCHBAR32(0x4230 + 0x400 * channel) = - (max((ctrl->tFAW >> 2) + 1, ctrl->tRRD) + (MAX((ctrl->tFAW >> 2) + 1, ctrl->tRRD) << 10) | (ctrl->tRCD << 16) | 4; MCHBAR32(0x4200 + 0x400 * channel) = (slotrank << 24) | 0x60000; @@ -2803,7 +2804,7 @@ static void test_timC_write(ramctr_timing *ctrl, int channel, int slotrank) /* DRAM command RD */ MCHBAR32(0x4228 + 0x400 * channel) = 0x1f105; MCHBAR32(0x4238 + 0x400 * channel) = - 0x40011e0 | (max(ctrl->tRTP, 8) << 16); + 0x40011e0 | (MAX(ctrl->tRTP, 8) << 16); MCHBAR32(0x4208 + 0x400 * channel) = slotrank << 24; MCHBAR32(0x4218 + 0x400 * channel) = 0x242; @@ -2883,10 +2884,10 @@ int discover_timC_write(ramctr_timing *ctrl) rn.start + ctrl->timC_offset[i], rn.end - ctrl->timC_offset[i]); lower[channel][slotrank][lane] = - max(rn.start + ctrl->timC_offset[i], + MAX(rn.start + ctrl->timC_offset[i], lower[channel][slotrank][lane]); upper[channel][slotrank][lane] = - min(rn.end - ctrl->timC_offset[i], + MIN(rn.end - ctrl->timC_offset[i], upper[channel][slotrank][lane]); } @@ -2927,7 +2928,7 @@ void normalize_training(ramctr_timing * ctrl) int delta; mat = 0; FOR_ALL_LANES mat = - max(ctrl->timings[channel][slotrank].lanes[lane].timA, mat); + MAX(ctrl->timings[channel][slotrank].lanes[lane].timA, mat); printram("normalize %d, %d, %d: mat %d\n", channel, slotrank, lane, mat); @@ -3080,8 +3081,8 @@ void set_4008c(ramctr_timing * ctrl) int max_320c = -10000; FOR_ALL_POPULATED_RANKS { - max_320c = max(ctrl->timings[channel][slotrank].val_320c, max_320c); - min_320c = min(ctrl->timings[channel][slotrank].val_320c, min_320c); + max_320c = MAX(ctrl->timings[channel][slotrank].val_320c, max_320c); + min_320c = MIN(ctrl->timings[channel][slotrank].val_320c, min_320c); } if (max_320c - min_320c > 51) diff --git a/src/soc/amd/common/block/spi/fch_spi_flash.c b/src/soc/amd/common/block/spi/fch_spi_flash.c index 72bc5d6ea5..d8eeefc7ed 100644 --- a/src/soc/amd/common/block/spi/fch_spi_flash.c +++ b/src/soc/amd/common/block/spi/fch_spi_flash.c @@ -13,6 +13,7 @@ * GNU General Public License for more details. */ +#include #include #include #include @@ -31,7 +32,7 @@ static void spi_flash_addr(u32 addr, u8 *cmd) static int crop_chunk(unsigned int cmd_len, unsigned int buf_len) { - return min((SPI_FIFO_DEPTH - (cmd_len - 1)), buf_len); + return MIN((SPI_FIFO_DEPTH - (cmd_len - 1)), buf_len); } int fch_spi_flash_cmd_write(const u8 *cmd, size_t cmd_len, const void *data, size_t data_len) @@ -192,7 +193,7 @@ static int fch_spi_flash_write(const struct spi_flash *flash, uint32_t offset, s for (actual = start; actual < len; actual += chunk_len) { byte_addr = offset % page_size; - chunk_len = min(len - actual, page_size - byte_addr); + chunk_len = MIN(len - actual, page_size - byte_addr); chunk_len = crop_chunk(sizeof(cmd), chunk_len); cmd[0] = spi_data_ptr->write_cmd; diff --git a/src/soc/intel/common/block/fast_spi/fast_spi_flash.c b/src/soc/intel/common/block/fast_spi/fast_spi_flash.c index 0a4344272e..f887b3c800 100644 --- a/src/soc/intel/common/block/fast_spi/fast_spi_flash.c +++ b/src/soc/intel/common/block/fast_spi/fast_spi_flash.c @@ -14,6 +14,7 @@ */ #include +#include #include #include #include @@ -157,11 +158,11 @@ static int exec_sync_hwseq_xfer(struct fast_spi_flash_ctx *ctx, static size_t get_xfer_len(const struct spi_flash *flash, uint32_t addr, size_t len) { - size_t xfer_len = min(len, SPIBAR_FDATA_FIFO_SIZE); + size_t xfer_len = MIN(len, SPIBAR_FDATA_FIFO_SIZE); size_t bytes_left = ALIGN_UP(addr, flash->page_size) - addr; if (bytes_left) - xfer_len = min(xfer_len, bytes_left); + xfer_len = MIN(xfer_len, bytes_left); return xfer_len; } diff --git a/src/soc/intel/common/smbios.c b/src/soc/intel/common/smbios.c index d315e15f28..e1b71ba1f0 100644 --- a/src/soc/intel/common/smbios.c +++ b/src/soc/intel/common/smbios.c @@ -16,6 +16,7 @@ #include #include "smbios.h" #include +#include #include #include @@ -63,7 +64,7 @@ void dimm_info_fill(struct dimm_info *dimm, u32 dimm_capacity, u8 ddr_type, strncpy((char *)dimm->module_part_number, module_part_num, - min(sizeof(dimm->module_part_number), + MIN(sizeof(dimm->module_part_number), module_part_number_size)); if (module_serial_num) memcpy(dimm->serial, module_serial_num, diff --git a/src/soc/intel/quark/i2c.c b/src/soc/intel/quark/i2c.c index 7ff2ddf93f..6430030e6b 100644 --- a/src/soc/intel/quark/i2c.c +++ b/src/soc/intel/quark/i2c.c @@ -14,6 +14,7 @@ */ #include +#include #include #include #include @@ -133,7 +134,7 @@ static int platform_i2c_read(uint32_t restart, uint8_t *rx_buffer, int length, } /* Fill the FIFO with read commands */ - fifo_bytes = min(length, 16); + fifo_bytes = MIN(length, 16); bytes_transferred = 0; while (length > 0) { status = regs->ic_raw_intr_stat; diff --git a/src/soc/intel/skylake/elog.c b/src/soc/intel/skylake/elog.c index 795139418d..411b3e99a1 100644 --- a/src/soc/intel/skylake/elog.c +++ b/src/soc/intel/skylake/elog.c @@ -16,6 +16,7 @@ #include #include +#include #include #include #include @@ -156,7 +157,7 @@ static void pch_log_rp_wake_source(void) { PCH_DEV_PCIE24, 0x60, ELOG_WAKE_SOURCE_PME_PCIE24 }, }; - maxports = min(CONFIG_MAX_ROOT_PORTS, ARRAY_SIZE(pme_status_info)); + maxports = MIN(CONFIG_MAX_ROOT_PORTS, ARRAY_SIZE(pme_status_info)); for (i = 0; i < maxports; i++) { dev = pme_status_info[i].dev; From 361a935332489c635192b39204c7ec7af1667c8f Mon Sep 17 00:00:00 2001 From: Elyes HAOUAS Date: Wed, 18 Dec 2019 21:26:33 +0100 Subject: [PATCH 0793/1242] {drivers,southbridge}: Replace min() with MIN() MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This is to remove min/max() from . Change-Id: Ica03d9aec8a81f57709abcac655dfb0ebce3f8c6 Signed-off-by: Elyes HAOUAS Reviewed-on: https://review.coreboot.org/c/coreboot/+/37818 Reviewed-by: Kyösti Mälkki Reviewed-by: Patrick Georgi Tested-by: build bot (Jenkins) --- src/drivers/i2c/tpm/cr50.c | 6 +++--- src/drivers/i2c/tpm/tis_atmel.c | 4 ++-- src/drivers/pc80/tpm/tis.c | 4 ++-- src/drivers/spi/adesto.c | 4 ++-- src/drivers/spi/amic.c | 4 ++-- src/drivers/spi/atmel.c | 4 ++-- src/drivers/spi/eon.c | 4 ++-- src/drivers/spi/flashconsole.c | 4 ++-- src/drivers/spi/gigadevice.c | 4 ++-- src/drivers/spi/macronix.c | 4 ++-- src/drivers/spi/spansion.c | 4 ++-- src/drivers/spi/spi-generic.c | 4 ++-- src/drivers/spi/sst.c | 4 ++-- src/drivers/spi/stmicro.c | 4 ++-- src/drivers/spi/winbond.c | 6 +++--- src/southbridge/intel/common/spi.c | 10 +++++----- 16 files changed, 37 insertions(+), 37 deletions(-) diff --git a/src/drivers/i2c/tpm/cr50.c b/src/drivers/i2c/tpm/cr50.c index 8ea544d0db..34873dc9e4 100644 --- a/src/drivers/i2c/tpm/cr50.c +++ b/src/drivers/i2c/tpm/cr50.c @@ -28,6 +28,7 @@ */ #include +#include #include #include #include @@ -36,7 +37,6 @@ #include #include #include -#include #include "tpm.h" @@ -341,7 +341,7 @@ static int cr50_i2c_tis_recv(struct tpm_chip *chip, uint8_t *buf, if (cr50_i2c_wait_burststs(chip, mask, &burstcnt, &status) < 0) goto out_err; - len = min(burstcnt, expected - current); + len = MIN(burstcnt, expected - current); if (cr50_i2c_read(chip, addr, buf + current, len) != 0) { printk(BIOS_ERR, "%s: Read failed\n", __func__); goto out_err; @@ -400,7 +400,7 @@ static int cr50_i2c_tis_send(struct tpm_chip *chip, uint8_t *buf, size_t len) /* Use burstcnt - 1 to account for the address byte * that is inserted by cr50_i2c_write() */ - limit = min(burstcnt - 1, len); + limit = MIN(burstcnt - 1, len); if (cr50_i2c_write(chip, TPM_DATA_FIFO(chip->vendor.locality), &buf[sent], limit) != 0) { printk(BIOS_ERR, "%s: Write failed\n", __func__); diff --git a/src/drivers/i2c/tpm/tis_atmel.c b/src/drivers/i2c/tpm/tis_atmel.c index 793418a96a..74b4830b6a 100644 --- a/src/drivers/i2c/tpm/tis_atmel.c +++ b/src/drivers/i2c/tpm/tis_atmel.c @@ -14,13 +14,13 @@ #include #include +#include #include #include #include #include #include #include -#include #include #include @@ -99,7 +99,7 @@ int tis_sendrecv(const uint8_t *sendbuf, size_t sbuf_size, return -1; /* Determine the number of bytes remaining */ - recv_bytes = min(be32_to_cpu(*(uint32_t *)&header->length), + recv_bytes = MIN(be32_to_cpu(*(uint32_t *)&header->length), max_recv_bytes); /* Determine if there is additional response data */ diff --git a/src/drivers/pc80/tpm/tis.c b/src/drivers/pc80/tpm/tis.c index 39fa70db3f..e9f14854c4 100644 --- a/src/drivers/pc80/tpm/tis.c +++ b/src/drivers/pc80/tpm/tis.c @@ -21,7 +21,7 @@ * Infineon slb9635), so this driver provides access to locality 0 only. */ -#include +#include #include #include #include @@ -488,7 +488,7 @@ static u32 tis_senddata(const u8 *const data, u32 len) * changes to zero exactly after the last byte is fed into the * FIFO. */ - count = min(burst, len - offset - 1); + count = MIN(burst, len - offset - 1); while (count--) tpm_write_data(data[offset++], locality); diff --git a/src/drivers/spi/adesto.c b/src/drivers/spi/adesto.c index f671247fba..974f8ad146 100644 --- a/src/drivers/spi/adesto.c +++ b/src/drivers/spi/adesto.c @@ -18,7 +18,7 @@ */ #include -#include +#include #include #include #include @@ -162,7 +162,7 @@ static int adesto_write(const struct spi_flash *flash, u32 offset, size_t len, for (actual = 0; actual < len; actual += chunk_len) { byte_addr = offset % page_size; - chunk_len = min(len - actual, page_size - byte_addr); + chunk_len = MIN(len - actual, page_size - byte_addr); chunk_len = spi_crop_chunk(&flash->spi, sizeof(cmd), chunk_len); cmd[0] = CMD_AT25DF_PP; diff --git a/src/drivers/spi/amic.c b/src/drivers/spi/amic.c index 9a23d9b527..254a5b2cff 100644 --- a/src/drivers/spi/amic.c +++ b/src/drivers/spi/amic.c @@ -13,7 +13,7 @@ */ #include -#include +#include #include #include #include @@ -133,7 +133,7 @@ static int amic_write(const struct spi_flash *flash, u32 offset, size_t len, byte_addr = offset % page_size; for (actual = 0; actual < len; actual += chunk_len) { - chunk_len = min(len - actual, page_size - byte_addr); + chunk_len = MIN(len - actual, page_size - byte_addr); chunk_len = spi_crop_chunk(&flash->spi, sizeof(cmd), chunk_len); cmd[0] = CMD_A25_PP; diff --git a/src/drivers/spi/atmel.c b/src/drivers/spi/atmel.c index 88321f03a2..4496f4b08c 100644 --- a/src/drivers/spi/atmel.c +++ b/src/drivers/spi/atmel.c @@ -13,7 +13,7 @@ */ #include -#include +#include #include #include #include @@ -117,7 +117,7 @@ static int atmel_write(const struct spi_flash *flash, u32 offset, size_t len, for (actual = 0; actual < len; actual += chunk_len) { byte_addr = offset % page_size; - chunk_len = min(len - actual, page_size - byte_addr); + chunk_len = MIN(len - actual, page_size - byte_addr); chunk_len = spi_crop_chunk(&flash->spi, sizeof(cmd), chunk_len); cmd[0] = CMD_AT25_PP; diff --git a/src/drivers/spi/eon.c b/src/drivers/spi/eon.c index a469fe228a..2cdbdbbe8d 100644 --- a/src/drivers/spi/eon.c +++ b/src/drivers/spi/eon.c @@ -13,7 +13,7 @@ */ #include -#include +#include #include #include #include @@ -249,7 +249,7 @@ static int eon_write(const struct spi_flash *flash, for (actual = 0; actual < len; actual += chunk_len) { byte_addr = offset % page_size; - chunk_len = min(len - actual, page_size - byte_addr); + chunk_len = MIN(len - actual, page_size - byte_addr); chunk_len = spi_crop_chunk(&flash->spi, sizeof(cmd), chunk_len); ret = spi_flash_cmd(&flash->spi, CMD_EN25_WREN, NULL, 0); diff --git a/src/drivers/spi/flashconsole.c b/src/drivers/spi/flashconsole.c index 98f3cb4796..80c63e07ea 100644 --- a/src/drivers/spi/flashconsole.c +++ b/src/drivers/spi/flashconsole.c @@ -11,12 +11,12 @@ * GNU General Public License for more details. */ +#include #include #include #include #include #include -#include #include #define LINE_BUFFER_SIZE 128 @@ -55,7 +55,7 @@ void flashconsole_init(void) for (i = 0; i < len && offset < size;) { // Fill the buffer on first iteration if (i == 0) { - len = min(READ_BUFFER_SIZE, size - offset); + len = MIN(READ_BUFFER_SIZE, size - offset); if (rdev_readat(&rdev, buffer, offset, len) != len) return; } diff --git a/src/drivers/spi/gigadevice.c b/src/drivers/spi/gigadevice.c index 9afc355336..65494fa240 100644 --- a/src/drivers/spi/gigadevice.c +++ b/src/drivers/spi/gigadevice.c @@ -13,7 +13,7 @@ */ #include -#include +#include #include #include #include @@ -178,7 +178,7 @@ static int gigadevice_write(const struct spi_flash *flash, u32 offset, for (actual = 0; actual < len; actual += chunk_len) { byte_addr = offset % page_size; - chunk_len = min(len - actual, page_size - byte_addr); + chunk_len = MIN(len - actual, page_size - byte_addr); chunk_len = spi_crop_chunk(&flash->spi, sizeof(cmd), chunk_len); ret = spi_flash_cmd(&flash->spi, CMD_GD25_WREN, NULL, 0); diff --git a/src/drivers/spi/macronix.c b/src/drivers/spi/macronix.c index 29489ee235..6643dfa579 100644 --- a/src/drivers/spi/macronix.c +++ b/src/drivers/spi/macronix.c @@ -13,7 +13,7 @@ */ #include -#include +#include #include #include #include @@ -214,7 +214,7 @@ static int macronix_write(const struct spi_flash *flash, u32 offset, size_t len, for (actual = 0; actual < len; actual += chunk_len) { byte_addr = offset % page_size; - chunk_len = min(len - actual, page_size - byte_addr); + chunk_len = MIN(len - actual, page_size - byte_addr); chunk_len = spi_crop_chunk(&flash->spi, sizeof(cmd), chunk_len); cmd[0] = CMD_MX25XX_PP; diff --git a/src/drivers/spi/spansion.c b/src/drivers/spi/spansion.c index cb665d0a59..0b119ebe98 100644 --- a/src/drivers/spi/spansion.c +++ b/src/drivers/spi/spansion.c @@ -13,7 +13,7 @@ */ #include -#include +#include #include #include #include @@ -232,7 +232,7 @@ static int spansion_write(const struct spi_flash *flash, u32 offset, size_t len, for (actual = 0; actual < len; actual += chunk_len) { byte_addr = offset % page_size; - chunk_len = min(len - actual, page_size - byte_addr); + chunk_len = MIN(len - actual, page_size - byte_addr); chunk_len = spi_crop_chunk(&flash->spi, sizeof(cmd), chunk_len); cmd[0] = CMD_S25FLXX_PP; diff --git a/src/drivers/spi/spi-generic.c b/src/drivers/spi/spi-generic.c index 05bfb82bf8..bc4fb086cd 100644 --- a/src/drivers/spi/spi-generic.c +++ b/src/drivers/spi/spi-generic.c @@ -13,9 +13,9 @@ */ #include +#include #include #include -#include #include int spi_claim_bus(const struct spi_slave *slave) @@ -113,7 +113,7 @@ unsigned int spi_crop_chunk(const struct spi_slave *slave, unsigned int cmd_len, if (deduct_cmd_len && (ctrlr_max > cmd_len)) ctrlr_max -= cmd_len; - return min(ctrlr_max, buf_len); + return MIN(ctrlr_max, buf_len); } void __weak spi_init(void) diff --git a/src/drivers/spi/sst.c b/src/drivers/spi/sst.c index 5367b70d21..6223cf98da 100644 --- a/src/drivers/spi/sst.c +++ b/src/drivers/spi/sst.c @@ -17,7 +17,7 @@ */ #include -#include +#include #include #include #include @@ -217,7 +217,7 @@ static int sst_write_256(const struct spi_flash *flash, u32 offset, size_t len, for (actual = 0; actual < len; actual += chunk_len) { byte_addr = offset % page_size; - chunk_len = min(len - actual, page_size - byte_addr); + chunk_len = MIN(len - actual, page_size - byte_addr); chunk_len = spi_crop_chunk(&flash->spi, sizeof(cmd), chunk_len); cmd[0] = CMD_SST_BP; diff --git a/src/drivers/spi/stmicro.c b/src/drivers/spi/stmicro.c index d397e6e669..ad0a0dc538 100644 --- a/src/drivers/spi/stmicro.c +++ b/src/drivers/spi/stmicro.c @@ -13,7 +13,7 @@ */ #include -#include +#include #include #include #include @@ -298,7 +298,7 @@ static int stmicro_write(const struct spi_flash *flash, for (actual = 0; actual < len; actual += chunk_len) { byte_addr = offset % page_size; - chunk_len = min(len - actual, page_size - byte_addr); + chunk_len = MIN(len - actual, page_size - byte_addr); chunk_len = spi_crop_chunk(&flash->spi, sizeof(cmd), chunk_len); cmd[0] = CMD_M25PXX_PP; diff --git a/src/drivers/spi/winbond.c b/src/drivers/spi/winbond.c index 432ad6a47e..3790ce7bf1 100644 --- a/src/drivers/spi/winbond.c +++ b/src/drivers/spi/winbond.c @@ -13,7 +13,7 @@ */ #include -#include +#include #include #include #include @@ -310,7 +310,7 @@ static int winbond_write(const struct spi_flash *flash, u32 offset, size_t len, for (actual = 0; actual < len; actual += chunk_len) { byte_addr = offset % page_size; - chunk_len = min(len - actual, page_size - byte_addr); + chunk_len = MIN(len - actual, page_size - byte_addr); chunk_len = spi_crop_chunk(&flash->spi, sizeof(cmd), chunk_len); cmd[0] = CMD_W25_PP; @@ -366,7 +366,7 @@ static void winbond_bpbits_to_region(const size_t granularity, struct region *out) { size_t protected_size = - min(bp ? granularity << (bp - 1) : 0, flash_size); + MIN(bp ? granularity << (bp - 1) : 0, flash_size); if (cmp) { protected_size = flash_size - protected_size; diff --git a/src/southbridge/intel/common/spi.c b/src/southbridge/intel/common/spi.c index cf678176ab..63206d0a83 100644 --- a/src/southbridge/intel/common/spi.c +++ b/src/southbridge/intel/common/spi.c @@ -18,8 +18,8 @@ #define __SIMPLE_DEVICE__ /* This file is derived from the flashrom project. */ + #include -#include #include #include #include @@ -637,9 +637,9 @@ static int spi_ctrlr_xfer(const struct spi_slave *slave, const void *dout, writel_(trans.offset & 0x00FFFFFF, cntlr.addr); if (trans.bytesout) - data_length = min(trans.bytesout, cntlr.databytes); + data_length = MIN(trans.bytesout, cntlr.databytes); else - data_length = min(trans.bytesin, cntlr.databytes); + data_length = MIN(trans.bytesin, cntlr.databytes); /* Program data into FDATA0 to N */ if (trans.bytesout) { @@ -815,7 +815,7 @@ static int ich_hwseq_read(const struct spi_flash *flash, u32 addr, size_t len, writew_(readw_(&cntlr.ich9_spi->hsfs), &cntlr.ich9_spi->hsfs); while (len > 0) { - block_len = min(len, cntlr.databytes); + block_len = MIN(len, cntlr.databytes); if (block_len > (~addr & 0xff)) block_len = (~addr & 0xff) + 1; ich_hwseq_set_addr(addr); @@ -883,7 +883,7 @@ static int ich_hwseq_write(const struct spi_flash *flash, u32 addr, size_t len, writew_(readw_(&cntlr.ich9_spi->hsfs), &cntlr.ich9_spi->hsfs); while (len > 0) { - block_len = min(len, cntlr.databytes); + block_len = MIN(len, cntlr.databytes); if (block_len > (~addr & 0xff)) block_len = (~addr & 0xff) + 1; From ba9b504ec5d8bc42f56cb085749c1296b1291ba9 Mon Sep 17 00:00:00 2001 From: Elyes HAOUAS Date: Thu, 19 Dec 2019 07:47:52 +0100 Subject: [PATCH 0794/1242] src: Replace min/max() with MIN/MAX() MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Change-Id: I63b95144f2022685c60a1bd6de5af3c1f059992e Signed-off-by: Elyes HAOUAS Reviewed-on: https://review.coreboot.org/c/coreboot/+/37828 Reviewed-by: Kyösti Mälkki Reviewed-by: Patrick Georgi Tested-by: build bot (Jenkins) --- src/lib/edid.c | 6 +-- src/northbridge/intel/gm45/raminit.c | 4 +- src/northbridge/intel/nehalem/raminit.c | 42 +++++++++---------- src/soc/mediatek/common/cbmem.c | 4 +- .../mt8173/dramc_pi_calibration_api.c | 4 +- src/soc/rockchip/common/cbmem.c | 4 +- src/soc/sifive/fu540/cbmem.c | 4 +- 7 files changed, 34 insertions(+), 34 deletions(-) diff --git a/src/lib/edid.c b/src/lib/edid.c index fd7f5ba252..4a2f07ae3e 100644 --- a/src/lib/edid.c +++ b/src/lib/edid.c @@ -29,12 +29,12 @@ */ #include +#include #include #include #include #include #include -#include #include #include @@ -178,7 +178,7 @@ extract_string(unsigned char *x, int *valid_termination, int len) memset(ret, 0, sizeof(ret)); - for (i = 0; i < min(len, EDID_ASCII_STRING_LENGTH); i++) { + for (i = 0; i < MIN(len, EDID_ASCII_STRING_LENGTH); i++) { if (seen_newline) { if (x[i] != 0x20) { *valid_termination = 0; @@ -1691,7 +1691,7 @@ void edid_set_framebuffer_bits_per_pixel(struct edid *edid, int fb_bpp, { /* Caller should pass a supported value, everything else is BUG(). */ assert(fb_bpp == 32 || fb_bpp == 24 || fb_bpp == 16); - row_byte_alignment = max(row_byte_alignment, 1); + row_byte_alignment = MAX(row_byte_alignment, 1); edid->framebuffer_bits_per_pixel = fb_bpp; edid->bytes_per_line = ALIGN_UP(edid->mode.ha * diff --git a/src/northbridge/intel/gm45/raminit.c b/src/northbridge/intel/gm45/raminit.c index a2c7643fb0..b1da177281 100644 --- a/src/northbridge/intel/gm45/raminit.c +++ b/src/northbridge/intel/gm45/raminit.c @@ -14,8 +14,8 @@ * GNU General Public License for more details. */ +#include #include -#include #include #include #include @@ -436,7 +436,7 @@ static unsigned int find_common_clock_cas(sysinfo_t *const sysinfo, unsigned int clock = 8000 / tCKmin; if ((clock > sysinfo->max_ddr3_mt / 2) || (clock > fsb_mhz / 2)) { - int new_clock = min(sysinfo->max_ddr3_mt / 2, fsb_mhz / 2); + int new_clock = MIN(sysinfo->max_ddr3_mt / 2, fsb_mhz / 2); printk(BIOS_SPEW, "DIMMs support %d MHz, but chipset only runs at up to %d. Limiting...\n", clock, new_clock); clock = new_clock; diff --git a/src/northbridge/intel/nehalem/raminit.c b/src/northbridge/intel/nehalem/raminit.c index a393cb7a51..8a2837e66e 100644 --- a/src/northbridge/intel/nehalem/raminit.c +++ b/src/northbridge/intel/nehalem/raminit.c @@ -14,8 +14,8 @@ * GNU General Public License for more details. */ -#include #include +#include #include #include #include @@ -571,7 +571,7 @@ static void calculate_timings(struct raminfo *info) spd[channel][slot][CAS_LATENCIES_MSB] << 8)); - max_clock_index = min(3, info->max_supported_clock_speed_index); + max_clock_index = MIN(3, info->max_supported_clock_speed_index); cycletime = min_cycletime[max_clock_index]; cas_latency_time = min_cas_latency_time[max_clock_index]; @@ -586,11 +586,11 @@ static void calculate_timings(struct raminfo *info) spd[channel][slot][TIMEBASE_DIVIDEND] / info->spd[channel][slot][TIMEBASE_DIVISOR]; cycletime = - max(cycletime, + MAX(cycletime, timebase * info->spd[channel][slot][CYCLETIME]); cas_latency_time = - max(cas_latency_time, + MAX(cas_latency_time, timebase * info-> spd[channel][slot][CAS_LATENCY_TIME]); @@ -865,7 +865,7 @@ static void compute_derived_timings(struct raminfo *info) if (info->revision_flag_1) some_delay_2_ps = halfcycle_ps(info) >> 6; some_delay_2_ps += - max(some_delay_1_ps - 30, + MAX(some_delay_1_ps - 30, 2 * halfcycle_ps(info) * (some_delay_1_cycle_ceil - 1) + 1000) + 375; some_delay_3_ps = @@ -977,8 +977,8 @@ static void compute_derived_timings(struct raminfo *info) clock_speed_index]; } } - min_of_unk_2 = min(min_of_unk_2, a); - min_of_unk_2 = min(min_of_unk_2, b); + min_of_unk_2 = MIN(min_of_unk_2, a); + min_of_unk_2 = MIN(min_of_unk_2, b); if (rank == 0) { sum += a; count++; @@ -993,7 +993,7 @@ static void compute_derived_timings(struct raminfo *info) clock_speed_index]; if (unk1 >= t) max_of_unk = - max(max_of_unk, + MAX(max_of_unk, unk1 - t); } } @@ -1005,7 +1005,7 @@ static void compute_derived_timings(struct raminfo *info) [channel]] [info->clock_speed_index] + min_of_unk_2; if (unk1 >= t) - max_of_unk = max(max_of_unk, unk1 - t); + max_of_unk = MAX(max_of_unk, unk1 - t); } } @@ -1177,7 +1177,7 @@ static void program_modules_memory_map(struct raminfo *info, int pre_jedec) info->total_memory_mb = total_mb[0] + total_mb[1]; info->interleaved_part_mb = - pre_jedec ? 0 : 2 * min(total_mb[0], total_mb[1]); + pre_jedec ? 0 : 2 * MIN(total_mb[0], total_mb[1]); info->non_interleaved_part_mb = total_mb[0] + total_mb[1] - info->interleaved_part_mb; channel_0_non_interleaved = total_mb[0] - info->interleaved_part_mb / 2; @@ -1247,7 +1247,7 @@ static void program_board_delay(struct raminfo *info) halfcycle_ps(info) + 2230); some_delay_3_half_cycles = - min((some_delay_2_half_cycles + + MIN((some_delay_2_half_cycles + (frequency_11(info) * 2) * (28 - some_delay_2_half_cycles) / (frequency_11(info) * 2 - @@ -1351,7 +1351,7 @@ static void program_board_delay(struct raminfo *info) program_modules_memory_map(info, 1); - MCHBAR16(0x610) = (min(ns_to_cycles(info, some_delay_ns) / 2, 127) << 9) + MCHBAR16(0x610) = (MIN(ns_to_cycles(info, some_delay_ns) / 2, 127) << 9) | (MCHBAR16(0x610) & 0x1C3) | 0x3C; MCHBAR16_OR(0x612, 0x100); MCHBAR16_OR(0x214, 0x3E00); @@ -1421,12 +1421,12 @@ static void program_total_memory_map(struct raminfo *info) if (TOM == 4096) TOM = 4032; TOUUD = ALIGN_DOWN(TOM - info->memory_reserved_for_heci_mb, 64); - TOLUD = ALIGN_DOWN(min(4096 - mmio_size + ALIGN_UP(uma_size_igd + uma_size_gtt, 64) + TOLUD = ALIGN_DOWN(MIN(4096 - mmio_size + ALIGN_UP(uma_size_igd + uma_size_gtt, 64) , TOUUD), 64); memory_remap = 0; if (TOUUD - TOLUD > 64) { memory_remap = 1; - REMAPbase = max(4096, TOUUD); + REMAPbase = MAX(4096, TOUUD); TOUUD = TOUUD - TOLUD + 4096; } if (TOUUD > 4096) @@ -1472,7 +1472,7 @@ static void program_total_memory_map(struct raminfo *info) memory_map[0] = ALIGN_DOWN(uma_base_gtt, 64) | 1; memory_map[1] = 4096; for (i = 0; i < ARRAY_SIZE(memory_map); i++) { - current_limit = max(current_limit, memory_map[i] & ~1); + current_limit = MAX(current_limit, memory_map[i] & ~1); pci_write_config32(PCI_DEV(QUICKPATH_BUS, 0, 1), 4 * i + 0x80, (memory_map[i] & 1) | ALIGN_DOWN(current_limit - 1, 64) | 2); @@ -2737,9 +2737,9 @@ choose_training(struct raminfo *info, int channel, int slot, int rank, upper_margin = timings[center_178][channel][slot][rank][lane].largest - result; if (upper_margin < 10 && lower_margin > 10) - result -= min(lower_margin - 10, 10 - upper_margin); + result -= MIN(lower_margin - 10, 10 - upper_margin); if (upper_margin > 10 && lower_margin < 10) - result += min(upper_margin - 10, 10 - lower_margin); + result += MIN(upper_margin - 10, 10 - lower_margin); return result; } @@ -3258,8 +3258,8 @@ compute_frequence_ratios(struct raminfo *info, u16 freq1, u16 freq2, g = gcd(freq1, freq2); freq1_reduced = freq1 / g; freq2_reduced = freq2 / g; - freq_min_reduced = min(freq1_reduced, freq2_reduced); - freq_max_reduced = max(freq1_reduced, freq2_reduced); + freq_min_reduced = MIN(freq1_reduced, freq2_reduced); + freq_max_reduced = MAX(freq1_reduced, freq2_reduced); common_time_unit_ps = div_roundup(900000, lcm(freq1, freq2)); freq3 = div_roundup(num_cycles_2, common_time_unit_ps) - 1; @@ -3347,7 +3347,7 @@ set_2d5x_reg(struct raminfo *info, u16 reg, u16 freq1, u16 freq2, 0, 1, &vv); multiplier = - div_roundup(max + div_roundup(MAX (div_roundup(num_cycles_2, vv.common_time_unit_ps) + div_roundup(num_cycles_3, vv.common_time_unit_ps), div_roundup(num_cycles_1, @@ -3527,7 +3527,7 @@ static u16 get_max_timing(struct raminfo *info, int channel) for (rank = 0; rank < NUM_RANKS; rank++) if (info->populated_ranks[channel][slot][rank]) for (lane = 0; lane < 8 + info->use_ecc; lane++) - ret = max(ret, read_500(info, channel, + ret = MAX(ret, read_500(info, channel, get_timing_register_addr (lane, 0, slot, rank), 9)); diff --git a/src/soc/mediatek/common/cbmem.c b/src/soc/mediatek/common/cbmem.c index 1a55d0113e..accafeb9c0 100644 --- a/src/soc/mediatek/common/cbmem.c +++ b/src/soc/mediatek/common/cbmem.c @@ -14,8 +14,8 @@ */ #include +#include #include -#include #include #include @@ -23,5 +23,5 @@ void *cbmem_top_chipset(void) { - return (void *)min((uintptr_t)_dram + sdram_size(), MAX_DRAM_ADDRESS); + return (void *)MIN((uintptr_t)_dram + sdram_size(), MAX_DRAM_ADDRESS); } diff --git a/src/soc/mediatek/mt8173/dramc_pi_calibration_api.c b/src/soc/mediatek/mt8173/dramc_pi_calibration_api.c index a22d7e22d1..492238a80c 100644 --- a/src/soc/mediatek/mt8173/dramc_pi_calibration_api.c +++ b/src/soc/mediatek/mt8173/dramc_pi_calibration_api.c @@ -308,7 +308,7 @@ static u8 dqs_gw_fine_tune_calib(u32 channel, u8 fine_val) int matches = 0, sum = 0; /* fine tune range from 0 to 127 */ - fine_val = min(max(fine_val, 0 - delta[0]), 127 - delta[6]); + fine_val = MIN(MAX(fine_val, 0 - delta[0]), 127 - delta[6]); /* test gw fine tune */ for (i = 0; i < ARRAY_SIZE(delta); i++) { @@ -443,7 +443,7 @@ void dramc_rankinctl_config(u32 channel, if (is_dual_rank(channel, sdram_params)) { /* RANKINCTL_ROOT1 = DQSINCTL + reg_TX_DLY_DQSGATE */ - value = min(opt_gw_coarse_value[channel][0], + value = MIN(opt_gw_coarse_value[channel][0], opt_gw_coarse_value[channel][1]) >> 2; clrsetbits32(&ch[channel].ao_regs->dummy, 0xf, value); diff --git a/src/soc/rockchip/common/cbmem.c b/src/soc/rockchip/common/cbmem.c index 6e3aabb81c..ccaa62433a 100644 --- a/src/soc/rockchip/common/cbmem.c +++ b/src/soc/rockchip/common/cbmem.c @@ -14,13 +14,13 @@ */ #include +#include #include #include -#include #include void *cbmem_top_chipset(void) { - return (void *)min((uintptr_t)_dram + sdram_size_mb() * MiB, + return (void *)MIN((uintptr_t)_dram + sdram_size_mb() * MiB, MAX_DRAM_ADDRESS); } diff --git a/src/soc/sifive/fu540/cbmem.c b/src/soc/sifive/fu540/cbmem.c index a7de16c56a..b6b568df8d 100644 --- a/src/soc/sifive/fu540/cbmem.c +++ b/src/soc/sifive/fu540/cbmem.c @@ -14,13 +14,13 @@ */ #include +#include #include #include -#include #include void *cbmem_top_chipset(void) { - return (void *)min((uintptr_t)_dram + sdram_size_mb() * MiB, + return (void *)MIN((uintptr_t)_dram + sdram_size_mb() * MiB, FU540_MAXDRAM); } From 0e45b2875add588ddada7f40e294db99d62c3c3c Mon Sep 17 00:00:00 2001 From: Arthur Heymans Date: Thu, 28 Nov 2019 16:09:28 +0100 Subject: [PATCH 0795/1242] arch/x86: Drop romcc bootblock MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Change-Id: I79accbe1d5a554fea75fbd866995f385f718421a Signed-off-by: Arthur Heymans Reviewed-on: https://review.coreboot.org/c/coreboot/+/37335 Tested-by: build bot (Jenkins) Reviewed-by: HAOUAS Elyes Reviewed-by: Kyösti Mälkki --- src/arch/x86/Kconfig | 14 ----- src/arch/x86/Makefile.inc | 57 ------------------ src/arch/x86/bootblock.ld | 23 ------- src/arch/x86/bootblock_normal.c | 66 --------------------- src/arch/x86/bootblock_romcc.S | 49 --------------- src/arch/x86/bootblock_simple.c | 36 ----------- src/arch/x86/car.ld | 8 --- src/arch/x86/failover.ld | 66 --------------------- src/arch/x86/include/arch/bootblock_romcc.h | 45 -------------- src/arch/x86/memlayout.ld | 1 - src/lib/Makefile.inc | 2 - 11 files changed, 367 deletions(-) delete mode 100644 src/arch/x86/bootblock.ld delete mode 100644 src/arch/x86/bootblock_normal.c delete mode 100644 src/arch/x86/bootblock_romcc.S delete mode 100644 src/arch/x86/bootblock_simple.c delete mode 100644 src/arch/x86/failover.ld delete mode 100644 src/arch/x86/include/arch/bootblock_romcc.h diff --git a/src/arch/x86/Kconfig b/src/arch/x86/Kconfig index a6f9f608a5..f4c0dc9e82 100644 --- a/src/arch/x86/Kconfig +++ b/src/arch/x86/Kconfig @@ -166,12 +166,6 @@ config BOOTBLOCK_DEBUG_SPINLOOP Add a spin (JMP .) in bootblock_crt0.S during early bootblock to wait for a JTAG debugger to break into the execution sequence. -config BOOTBLOCK_MAINBOARD_INIT - string - -config BOOTBLOCK_NORTHBRIDGE_INIT - string - config BOOTBLOCK_RESETS string @@ -184,9 +178,6 @@ config CMOS_DEFAULT_FILE default "src/mainboard/$(MAINBOARDDIR)/cmos.default" depends on HAVE_CMOS_DEFAULT -config BOOTBLOCK_SOUTHBRIDGE_INIT - string - config IOAPIC_INTERRUPTS_ON_FSB bool default y if !IOAPIC_INTERRUPTS_ON_APIC_SERIAL_BUS @@ -256,11 +247,6 @@ config BOOTBLOCK_NORMAL endchoice -config BOOTBLOCK_SOURCE - string - default "bootblock_simple.c" if BOOTBLOCK_SIMPLE - default "bootblock_normal.c" if BOOTBLOCK_NORMAL - config SKIP_MAX_REBOOT_CNT_CLEAR bool "Do not clear reboot count after successful boot" depends on BOOTBLOCK_NORMAL diff --git a/src/arch/x86/Makefile.inc b/src/arch/x86/Makefile.inc index f82148cf27..3b13efc46e 100644 --- a/src/arch/x86/Makefile.inc +++ b/src/arch/x86/Makefile.inc @@ -116,8 +116,6 @@ bootblock-$(CONFIG_X86_TOP4G_BOOTMEDIA_MAP) += mmap_boot.c bootblock-y += id.S $(call src-to-obj,bootblock,$(dir)/id.S): $(obj)/build.h -ifneq ($(CONFIG_ROMCC_BOOTBLOCK),y) - bootblock-y += bootblock_crt0.S ifeq ($(CONFIG_ARCH_BOOTBLOCK_X86_32),y) @@ -128,59 +126,6 @@ endif bootblock-$(CONFIG_ARCH_BOOTBLOCK_X86_32) += walkcbfs.S -else # ROMCC_BOOTBLOCK - -# x86-specific linker flags -ifeq ($(CONFIG_ARCH_BOOTBLOCK_X86_32),y) -LDFLAGS_bootblock += -m elf_i386 --oformat elf32-i386 -else -LDFLAGS_bootblock += -m elf_x86_64 --oformat elf64-x86-64 -endif - -# Add the assembly file that pulls in the rest of the dependencies in -# the right order. Make sure the auto generated bootblock.inc is a proper -# dependency. Make the same true for the linker sript. -bootblock-y += bootblock_romcc.S -bootblock-y += walkcbfs.S -$(call src-to-obj,bootblock,$(dir)/bootblock_romcc.S): $(objgenerated)/bootblock.inc - -bootblock-y += bootblock.ld -$(call src-to-obj,bootblock,$(dir)/bootblock.ld): $(objgenerated)/bootblock.ld - -bootblock_romccflags := -mcpu=i386 -O2 -D__BOOTBLOCK__ -ifeq ($(CONFIG_SSE),y) -bootblock_romccflags := -mcpu=k7 -mno-mmx -msse -O2 -D__BOOTBLOCK__ -endif - -# This is a hack in case there are no per chipset linker files. -$(objgenerated)/empty: build-dirs - touch $@ - -$(objgenerated)/bootblock.ld: $$(filter-out $(call src-to-obj,bootblock,src/arch/x86/bootblock.ld), $$(filter %.ld,$$(bootblock-objs))) $(objgenerated)/empty - @printf " GEN $(subst $(obj)/,,$(@))\n" - cat $^ >> $@.tmp - mv $@.tmp $@ - --include $(objgenerated)/bootblock.inc.d -$(objgenerated)/bootblock.inc: $(src)/arch/x86/$(subst ",,$(CONFIG_BOOTBLOCK_SOURCE)) $(objutil)/romcc/romcc $(OPTION_TABLE_H) $(KCONFIG_AUTOHEADER) -# The open quote in the subst messes with syntax highlighting. Fix it - ") - @printf " ROMCC $(subst $(obj)/,,$(@))\n" - $(CC_bootblock) -D__ROMCC__ -D__BOOTBLOCK__ $(CPPFLAGS_bootblock) -MM -MT$(objgenerated)/bootblock.inc \ - $< > $(objgenerated)/bootblock.inc.d - $(CC_bootblock) -D__ROMCC__ -D__BOOTBLOCK__ $(CPPFLAGS_bootblock) -E \ - $< -o $(objgenerated)/bootblock_romcc.c - $(ROMCC) -c -S $(bootblock_romccflags) -I. $(CPPFLAGS_bootblock) $< -o $@ - -# bootblock.ld is part of $(bootblock-objs) -$(objcbfs)/bootblock.debug: $$(bootblock-objs) - @printf " LINK $(subst $(obj)/,,$(@))\n" - $(LD_bootblock) $(LDFLAGS_bootblock) -o $@ -L$(obj) \ - $(filter-out %.ld,$(bootblock-objs)) \ - -T $(call src-to-obj,bootblock,src/arch/x86/bootblock.ld) - -endif # ROMCC_BOOTBLOCK - - endif # CONFIG_ARCH_BOOTBLOCK_X86_32 / CONFIG_ARCH_BOOTBLOCK_X86_64 ############################################################################### @@ -223,9 +168,7 @@ ifeq ($(CONFIG_ARCH_ROMSTAGE_X86_32)$(CONFIG_ARCH_ROMSTAGE_X86_64),y) romstage-$(CONFIG_HAVE_ACPI_RESUME) += acpi_s3.c # gdt_init.S is included by entry32.inc when romstage is the first C # environment. -ifneq ($(CONFIG_ROMCC_BOOTBLOCK),y) romstage-y += gdt_init.S -endif romstage-y += cbmem.c romstage-$(CONFIG_IDT_IN_EVERY_STAGE) += exception.c romstage-$(CONFIG_IDT_IN_EVERY_STAGE) += idt.S diff --git a/src/arch/x86/bootblock.ld b/src/arch/x86/bootblock.ld deleted file mode 100644 index 10cd700322..0000000000 --- a/src/arch/x86/bootblock.ld +++ /dev/null @@ -1,23 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include -#include -#if CONFIG(CPU_INTEL_FIRMWARE_INTERFACE_TABLE) -#include -#endif - -/* Include generated .ld files. */ -#include diff --git a/src/arch/x86/bootblock_normal.c b/src/arch/x86/bootblock_normal.c deleted file mode 100644 index 905ecb28fb..0000000000 --- a/src/arch/x86/bootblock_normal.c +++ /dev/null @@ -1,66 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include -#include - -static const char *get_fallback(const char *stagelist) -{ - while (*stagelist) - stagelist++; - return ++stagelist; -} - -static void main(unsigned long bist) -{ - u8 boot_mode; - const char *default_filenames = - "normal/romstage\0fallback/romstage"; - - if (boot_cpu()) { - bootblock_mainboard_init(); - - sanitize_cmos(); - - boot_mode = do_normal_boot(); - } else { - - /* Questionable single byte read from CMOS. - * Do not add any other CMOS access in the - * bootblock for AP CPUs. - */ - boot_mode = boot_use_normal(cmos_read(RTC_BOOT_BYTE)); - } - - char *normal_candidate = (char *)walkcbfs("coreboot-stages"); - - if (!normal_candidate) - normal_candidate = default_filenames; - - unsigned long entry; - - if (boot_mode) { - entry = findstage(normal_candidate); - if (entry) - call(entry, bist); - } - - entry = findstage(get_fallback(normal_candidate)); - if (entry) - call(entry, bist); - - /* duh. we're stuck */ - halt(); -} diff --git a/src/arch/x86/bootblock_romcc.S b/src/arch/x86/bootblock_romcc.S deleted file mode 100644 index 7d6f42f08a..0000000000 --- a/src/arch/x86/bootblock_romcc.S +++ /dev/null @@ -1,49 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -/* - * This is the original bootblock used by coreboot on x86 systems. It contains - * a monolithic code flow, assembled from the following stages: - * - reset16.inc: the reset vector - * - entry16.inc: protected mode setup - * - entry32.inc: segment descriptor setup - * - timestamp.inc: store TSC in MMX registers - * - generated/bootblock.inc: ROMCC part of the bootblock - * - * This is used on platforms which select ROMCC_BOOTBLOCK, and it - * tries to do the absolute minimum before walking CBFS and jumping to romstage. - * - * This file assembles the bootblock program by the order of the includes. Thus, - * it's extremely important that one pays very careful attention to the order - * of the includes. - */ - -#include -#include -#include -#include - -#include - -#if CONFIG(SSE) -#include -#endif - -/* - * This bootblock.inc file is generated by ROMCC. The above program flow - * falls through to this point. ROMCC assumes the last function it parsed - * is the main function and it places its instructions at the beginning of - * the generated file. Moreover, any library/common code needed in bootblock - * needs to come after bootblock.inc. - */ -#include diff --git a/src/arch/x86/bootblock_simple.c b/src/arch/x86/bootblock_simple.c deleted file mode 100644 index d161435424..0000000000 --- a/src/arch/x86/bootblock_simple.c +++ /dev/null @@ -1,36 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include -#include - -static void main(unsigned long bist) -{ - if (boot_cpu()) { - bootblock_mainboard_init(); - - sanitize_cmos(); -#if CONFIG(CMOS_POST) - cmos_post_init(); -#endif - } - - const char *target1 = "fallback/romstage"; - unsigned long entry; - entry = findstage(target1); - if (entry) - call(entry, bist); - halt(); -} diff --git a/src/arch/x86/car.ld b/src/arch/x86/car.ld index d8ff4b36b7..2e29112467 100644 --- a/src/arch/x86/car.ld +++ b/src/arch/x86/car.ld @@ -36,11 +36,9 @@ /* Stack for CAR stages. Since it persists across all stages that * use CAR it can be reused. The chipset/SoC is expected to provide * the stack size. */ -#if !CONFIG(ROMCC_BOOTBLOCK) _car_stack = .; . += CONFIG_DCACHE_BSP_STACK_SIZE; _ecar_stack = .; -#endif /* The pre-ram cbmem console as well as the timestamp region are fixed * in size. Therefore place them above the car global section so that * multiple stages (romstage and verstage) have a consistent @@ -86,10 +84,6 @@ _ebss = .; _car_unallocated_start = .; -#if CONFIG(ROMCC_BOOTBLOCK) - _car_stack = .; - _ecar_stack = _car_region_end; -#endif _car_region_end = . + CONFIG_DCACHE_RAM_SIZE - (. - _car_region_start); } @@ -108,6 +102,4 @@ _bogus = ASSERT((CONFIG_DCACHE_RAM_SIZE == 0) || (SIZEOF(.car.data) <= CONFIG_DC #if CONFIG(PAGING_IN_CACHE_AS_RAM) _bogus2 = ASSERT(_pagetables == ALIGN(_pagetables, 4096), "_pagetables aren't 4KiB aligned"); #endif -#if !CONFIG(ROMCC_BOOTBLOCK) _bogus3 = ASSERT(CONFIG_DCACHE_BSP_STACK_SIZE > 0x0, "BSP stack size not configured"); -#endif diff --git a/src/arch/x86/failover.ld b/src/arch/x86/failover.ld deleted file mode 100644 index 139136540c..0000000000 --- a/src/arch/x86/failover.ld +++ /dev/null @@ -1,66 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -ENTRY(_start) - -MEMORY { - rom : ORIGIN = CONFIG_X86_RESET_VECTOR - 0xfff0, LENGTH = 64K -} - -TARGET(binary) -SECTIONS -{ - /* Symbol ap_sipi_vector must be aligned to 4kB to start AP CPUs - * with Startup IPI message without RAM. Align .rom to next 4 byte - * boundary anyway, so no pad byte appears between _rom and _start. - */ - .bogus ROMLOC_MIN : { - . = CONFIG(SIPI_VECTOR_IN_ROM) ? ALIGN(4096) : ALIGN(4); - ROMLOC = .; - } >rom = 0xff - - /* This section might be better named .setup */ - .rom ROMLOC : { - _rom = .; - *(.rom.text); - *(.rom.data); - *(.rom.data.*); - *(.text); - *(.text.*); - *(.rodata); - *(.rodata.*); - _erom = .; - } >rom = 0xff - - /* Allocation reserves extra 16 bytes here. Alignment requirements - * may cause the total size of a section to change when the start - * address gets applied. - */ - ROMLOC_MIN = 0xffffff00 - (_erom - _rom + 16) - - (CONFIG(SIPI_VECTOR_IN_ROM) ? 4096 : 0); - - /* Post-check proper SIPI vector. */ - _bogus = ASSERT(!CONFIG(SIPI_VECTOR_IN_ROM) || (ap_sipi_vector_in_rom == 0xff), - "Address mismatch on AP_SIPI_VECTOR"); - - /DISCARD/ : { - *(.comment) - *(.note) - *(.comment.*) - *(.note.*) - *(.eh_frame) - *(.iplt) - *(.rel.*) - *(.igot.*) - } -} diff --git a/src/arch/x86/include/arch/bootblock_romcc.h b/src/arch/x86/include/arch/bootblock_romcc.h deleted file mode 100644 index 827e40e985..0000000000 --- a/src/arch/x86/include/arch/bootblock_romcc.h +++ /dev/null @@ -1,45 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include - -#ifdef CONFIG_BOOTBLOCK_RESETS -#include CONFIG_BOOTBLOCK_RESETS -#endif - -#ifdef CONFIG_BOOTBLOCK_CPU_INIT -#include CONFIG_BOOTBLOCK_CPU_INIT -#endif -#ifdef CONFIG_BOOTBLOCK_NORTHBRIDGE_INIT -#include CONFIG_BOOTBLOCK_NORTHBRIDGE_INIT -#endif -#ifdef CONFIG_BOOTBLOCK_SOUTHBRIDGE_INIT -#include CONFIG_BOOTBLOCK_SOUTHBRIDGE_INIT -#endif - -#ifdef CONFIG_BOOTBLOCK_MAINBOARD_INIT -#include CONFIG_BOOTBLOCK_MAINBOARD_INIT -#else -static void bootblock_mainboard_init(void) -{ -#ifdef CONFIG_BOOTBLOCK_NORTHBRIDGE_INIT - bootblock_northbridge_init(); -#endif -#ifdef CONFIG_BOOTBLOCK_SOUTHBRIDGE_INIT - bootblock_southbridge_init(); -#endif -#ifdef CONFIG_BOOTBLOCK_CPU_INIT - bootblock_cpu_init(); -#endif -} -#endif diff --git a/src/arch/x86/memlayout.ld b/src/arch/x86/memlayout.ld index b14fd624a7..eff3738a43 100644 --- a/src/arch/x86/memlayout.ld +++ b/src/arch/x86/memlayout.ld @@ -49,7 +49,6 @@ SECTIONS #include EARLY_MEMLAYOUT #elif ENV_BOOTBLOCK - /* arch/x86/bootblock.ld contains the logic for the ROMCC_BOOTBLOCK linking. */ BOOTBLOCK(CONFIG_X86_RESET_VECTOR - CONFIG_C_ENV_BOOTBLOCK_SIZE + 0x10, CONFIG_C_ENV_BOOTBLOCK_SIZE) diff --git a/src/lib/Makefile.inc b/src/lib/Makefile.inc index b444ea3c86..748f55aae8 100644 --- a/src/lib/Makefile.inc +++ b/src/lib/Makefile.inc @@ -268,9 +268,7 @@ postcar-$(CONFIG_COLLECT_TIMESTAMPS) += timestamp.c postcar-$(CONFIG_GENERIC_UDELAY) += timer.c # Use program.ld for all the platforms which use C fo the bootblock. -ifneq ($(CONFIG_ROMCC_BOOTBLOCK),y) bootblock-y += program.ld -endif decompressor-y += program.ld postcar-y += program.ld From 67117c3971f16e4b47e927821a19f110b4885111 Mon Sep 17 00:00:00 2001 From: Wim Vervoorn Date: Mon, 16 Dec 2019 14:21:09 +0100 Subject: [PATCH 0796/1242] {drivers,soc}/intel/fsp1_1: Move chipset specific logo handling to SoC FSP logo handling used PcdLogoPtr and PcdLogoSize which are elements of the chipset specific FSP structures. Create soc_load_logo() which will pass the logo pointer and size. This function will call fsp_load_logo which will load the logo. BUG=NA TEST= Build and verified logo is displayed on Facebook FBG1701 Change-Id: I86943e64ca1ddd05e7e88fc6b882cfd33b98272e Signed-off-by: Wim Vervoorn Reviewed-on: https://review.coreboot.org/c/coreboot/+/37791 Reviewed-by: Frans Hendriks Tested-by: build bot (Jenkins) --- .../intel/fsp1_1/include/fsp/ramstage.h | 3 ++- src/drivers/intel/fsp1_1/logo.c | 25 +++++++++++++------ src/drivers/intel/fsp1_1/ramstage.c | 19 +++++++------- src/soc/intel/braswell/chip.c | 5 ++++ 4 files changed, 34 insertions(+), 18 deletions(-) diff --git a/src/drivers/intel/fsp1_1/include/fsp/ramstage.h b/src/drivers/intel/fsp1_1/include/fsp/ramstage.h index a5eac0e279..e50edd8773 100644 --- a/src/drivers/intel/fsp1_1/include/fsp/ramstage.h +++ b/src/drivers/intel/fsp1_1/include/fsp/ramstage.h @@ -26,6 +26,7 @@ void fsp_load(void); /* Perform Intel silicon init. */ void intel_silicon_init(void); void fsp_run_silicon_init(FSP_INFO_HEADER *fsp_info_header, int is_s3_wakeup); +const struct cbmem_entry *fsp_load_logo(UINT32 *logo_ptr, UINT32 *logo_size); /* Called after the silicon init code has run. */ void soc_after_silicon_init(void); /* Initialize UPD data before SiliconInit call. */ @@ -33,7 +34,7 @@ void soc_silicon_init_params(SILICON_INIT_UPD *params); void mainboard_silicon_init_params(SILICON_INIT_UPD *params); void soc_display_silicon_init_params(const SILICON_INIT_UPD *old, SILICON_INIT_UPD *new); -void load_logo(SILICON_INIT_UPD *params); +const struct cbmem_entry *soc_load_logo(SILICON_INIT_UPD *params); void load_vbt(uint8_t s3_resume, SILICON_INIT_UPD *params); #endif /* _INTEL_COMMON_RAMSTAGE_H_ */ diff --git a/src/drivers/intel/fsp1_1/logo.c b/src/drivers/intel/fsp1_1/logo.c index 03b2715f43..23aad01c1b 100644 --- a/src/drivers/intel/fsp1_1/logo.c +++ b/src/drivers/intel/fsp1_1/logo.c @@ -11,15 +11,24 @@ * GNU General Public License for more details. */ +#include +#include #include -#include -#include -#include -void load_logo(SILICON_INIT_UPD *params) +const struct cbmem_entry *fsp_load_logo(UINT32 *logo_ptr, UINT32 *logo_size) { - params->PcdLogoSize = cbfs_boot_load_file("logo.bmp", (void *)params->PcdLogoPtr, - params->PcdLogoSize, CBFS_TYPE_RAW); - if (!params->PcdLogoSize) - params->PcdLogoPtr = 0; + const struct cbmem_entry *logo_entry = NULL; + void *logo_buffer; + + logo_entry = cbmem_entry_add(CBMEM_ID_FSP_LOGO, 1 * MiB); + if (logo_entry) { + logo_buffer = cbmem_entry_start(logo_entry); + if (logo_buffer) { + *logo_size = cbfs_boot_load_file("logo.bmp", (void *)logo_buffer, + 1 * MiB, CBFS_TYPE_RAW); + if (logo_size) + *logo_ptr = (UINT32)logo_buffer; + } + } + return (logo_entry); } diff --git a/src/drivers/intel/fsp1_1/ramstage.c b/src/drivers/intel/fsp1_1/ramstage.c index 9ecdfd658a..40e79cce21 100644 --- a/src/drivers/intel/fsp1_1/ramstage.c +++ b/src/drivers/intel/fsp1_1/ramstage.c @@ -69,7 +69,7 @@ void fsp_run_silicon_init(FSP_INFO_HEADER *fsp_info_header, int is_s3_wakeup) EFI_STATUS status; UPD_DATA_REGION *upd_ptr; VPD_DATA_REGION *vpd_ptr; - const struct cbmem_entry *logo_entry; + const struct cbmem_entry *logo_entry = NULL; /* Display the FSP header */ if (fsp_info_header == NULL) { @@ -96,13 +96,8 @@ void fsp_run_silicon_init(FSP_INFO_HEADER *fsp_info_header, int is_s3_wakeup) load_vbt(is_s3_wakeup, &silicon_init_params); mainboard_silicon_init_params(&silicon_init_params); - if (CONFIG(FSP1_1_DISPLAY_LOGO) && !is_s3_wakeup) { - silicon_init_params.PcdLogoSize = 1 * MiB; - logo_entry = cbmem_entry_add(CBMEM_ID_FSP_LOGO, - silicon_init_params.PcdLogoSize); - silicon_init_params.PcdLogoPtr = (UINT32)cbmem_entry_start(logo_entry); - load_logo(&silicon_init_params); - } + if (CONFIG(FSP1_1_DISPLAY_LOGO) && !is_s3_wakeup) + logo_entry = soc_load_logo(&silicon_init_params); /* Display the UPD data */ if (CONFIG(DISPLAY_UPD_DATA)) @@ -122,7 +117,7 @@ void fsp_run_silicon_init(FSP_INFO_HEADER *fsp_info_header, int is_s3_wakeup) printk(BIOS_DEBUG, "FspSiliconInit returned 0x%08x\n", status); /* The logo_entry can be freed up now as it is not required any longer */ - if (CONFIG(FSP1_1_DISPLAY_LOGO) && !is_s3_wakeup) + if (logo_entry && !is_s3_wakeup) cbmem_entry_remove(logo_entry); /* Mark graphics init done after SiliconInit if VBT was provided */ @@ -214,3 +209,9 @@ __weak void soc_display_silicon_init_params( __weak void soc_silicon_init_params(SILICON_INIT_UPD *params) { } + +/* Load bmp and set FSP parameters, fsp_load_logo can be used */ +__weak const struct cbmem_entry *soc_load_logo(SILICON_INIT_UPD *params) +{ + return NULL; +} diff --git a/src/soc/intel/braswell/chip.c b/src/soc/intel/braswell/chip.c index d179cead25..026b281881 100644 --- a/src/soc/intel/braswell/chip.c +++ b/src/soc/intel/braswell/chip.c @@ -181,6 +181,11 @@ void soc_silicon_init_params(SILICON_INIT_UPD *params) board_silicon_USB2_override(params); } +const struct cbmem_entry *soc_load_logo(SILICON_INIT_UPD *params) +{ + return fsp_load_logo(¶ms->PcdLogoPtr, ¶ms->PcdLogoSize); +} + void soc_display_silicon_init_params(const SILICON_INIT_UPD *old, SILICON_INIT_UPD *new) { From f86317642333f6c45f62ef607583562bbba29053 Mon Sep 17 00:00:00 2001 From: Wim Vervoorn Date: Thu, 19 Dec 2019 14:01:33 +0100 Subject: [PATCH 0797/1242] mb/facebook/fbg1701: Correct typo in hda verbs The MIC1 NID is configured incorrectly because of a typo. The value is 7 digits instead of 8. This is corrected by this patch. No issues are known because of this (the MIC is not connected). BUG=N/A TEST=build Change-Id: Ia12f3be7d7262829cce3400a8535a33ea1c54b78 Signed-off-by: Wim Vervoorn Reviewed-on: https://review.coreboot.org/c/coreboot/+/37836 Tested-by: build bot (Jenkins) Reviewed-by: Frans Hendriks Reviewed-by: Angel Pons --- src/mainboard/facebook/fbg1701/hda_verb.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/mainboard/facebook/fbg1701/hda_verb.c b/src/mainboard/facebook/fbg1701/hda_verb.c index 344443f09a..5cf820ded9 100644 --- a/src/mainboard/facebook/fbg1701/hda_verb.c +++ b/src/mainboard/facebook/fbg1701/hda_verb.c @@ -45,7 +45,7 @@ const u32 cim_verb_data[] = { AZALIA_PIN_CFG(0x0, 0x17, 0x01011120), /* Pin Complex (NID 0x18) MIC1 (Port-B) */ - AZALIA_PIN_CFG(0x0, 0x18, 0x41111F0), + AZALIA_PIN_CFG(0x0, 0x18, 0x411111F0), /* Pin Complex (NID 0x19) I2S-IN */ AZALIA_PIN_CFG(0x0, 0x19, 0x90870140), From bba4ec4ca1c9ed0ddf99cf61498bd565e9636983 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ky=C3=B6sti=20M=C3=A4lkki?= Date: Thu, 19 Dec 2019 06:43:13 +0200 Subject: [PATCH 0798/1242] superio/smsc/lpc47m10x: Expose pnp_enter/exit_conf_state MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Change-Id: I55915b63dbb097634a228193f62395e45a1f42fe Signed-off-by: Kyösti Mälkki Reviewed-on: https://review.coreboot.org/c/coreboot/+/37824 Tested-by: build bot (Jenkins) Reviewed-by: Felix Held Reviewed-by: Paul Menzel --- src/superio/smsc/lpc47m10x/early_serial.c | 4 ++-- src/superio/smsc/lpc47m10x/lpc47m10x.h | 9 ++++++--- 2 files changed, 8 insertions(+), 5 deletions(-) diff --git a/src/superio/smsc/lpc47m10x/early_serial.c b/src/superio/smsc/lpc47m10x/early_serial.c index 96c0b5df67..719faf4bc3 100644 --- a/src/superio/smsc/lpc47m10x/early_serial.c +++ b/src/superio/smsc/lpc47m10x/early_serial.c @@ -20,13 +20,13 @@ #include #include "lpc47m10x.h" -static void pnp_enter_conf_state(pnp_devfn_t dev) +void pnp_enter_conf_state(pnp_devfn_t dev) { u16 port = dev >> 8; outb(0x55, port); } -static void pnp_exit_conf_state(pnp_devfn_t dev) +void pnp_exit_conf_state(pnp_devfn_t dev) { u16 port = dev >> 8; outb(0xaa, port); diff --git a/src/superio/smsc/lpc47m10x/lpc47m10x.h b/src/superio/smsc/lpc47m10x/lpc47m10x.h index a83a6f242e..0c393c5344 100644 --- a/src/superio/smsc/lpc47m10x/lpc47m10x.h +++ b/src/superio/smsc/lpc47m10x/lpc47m10x.h @@ -19,6 +19,9 @@ #ifndef SUPERIO_SMSC_LPC47M10X_H #define SUPERIO_SMSC_LPC47M10X_H +#include +#include + #define LPC47M10X2_FDC 0 /* Floppy */ #define LPC47M10X2_PP 3 /* Parallel Port */ #define LPC47M10X2_SP1 4 /* Com1 */ @@ -30,9 +33,9 @@ #define LPC47M10X2_MAX_CONFIG_REGISTER 0x5F -#include -#include - void lpc47m10x_enable_serial(pnp_devfn_t dev, u16 iobase); +void pnp_enter_conf_state(pnp_devfn_t dev); +void pnp_exit_conf_state(pnp_devfn_t dev); + #endif /* SUPERIO_SMSC_LPC47M10X_H */ From a87a741b41ffb01612c7ef88d472d9092f707128 Mon Sep 17 00:00:00 2001 From: Elyes HAOUAS Date: Thu, 19 Dec 2019 11:50:43 +0100 Subject: [PATCH 0799/1242] crossgcc: Upgrade Python to version 3.8.1 Change-Id: I2867d62d2e6f5ca1e97ce52ecc45a794b4831686 Signed-off-by: Elyes HAOUAS Reviewed-on: https://review.coreboot.org/c/coreboot/+/37834 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi --- util/crossgcc/buildgcc | 2 +- util/crossgcc/sum/Python-3.8.0.tar.xz.cksum | 1 - util/crossgcc/sum/Python-3.8.1.tar.xz.cksum | 1 + 3 files changed, 2 insertions(+), 2 deletions(-) delete mode 100644 util/crossgcc/sum/Python-3.8.0.tar.xz.cksum create mode 100644 util/crossgcc/sum/Python-3.8.1.tar.xz.cksum diff --git a/util/crossgcc/buildgcc b/util/crossgcc/buildgcc index 5dac074a06..6150011f4d 100755 --- a/util/crossgcc/buildgcc +++ b/util/crossgcc/buildgcc @@ -55,7 +55,7 @@ GCC_AUTOCONF_VERSION=2.69 BINUTILS_VERSION=2.33.1 GDB_VERSION=8.3.1 IASL_VERSION=20190703 -PYTHON_VERSION=3.8.0 +PYTHON_VERSION=3.8.1 EXPAT_VERSION=2.2.9 # CLANG version number CLANG_VERSION=9.0.0 diff --git a/util/crossgcc/sum/Python-3.8.0.tar.xz.cksum b/util/crossgcc/sum/Python-3.8.0.tar.xz.cksum deleted file mode 100644 index d4566f82c1..0000000000 --- a/util/crossgcc/sum/Python-3.8.0.tar.xz.cksum +++ /dev/null @@ -1 +0,0 @@ -7720e0384558c598107cf046c48165fd7e1f5b2c tarballs/Python-3.8.0.tar.xz diff --git a/util/crossgcc/sum/Python-3.8.1.tar.xz.cksum b/util/crossgcc/sum/Python-3.8.1.tar.xz.cksum new file mode 100644 index 0000000000..e899a451ed --- /dev/null +++ b/util/crossgcc/sum/Python-3.8.1.tar.xz.cksum @@ -0,0 +1 @@ +a48fd28a037c0bcd7b7fc4d914c023f584e910ed tarballs/Python-3.8.1.tar.xz From 727ac0d26395e4522e56ee988f1ef0097d982d51 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Micha=C5=82=20=C5=BBygowski?= Date: Thu, 19 Dec 2019 12:56:21 +0100 Subject: [PATCH 0800/1242] AMD {SoC, AGESA, binaryPI}: Don't use both of _ADR and _HID MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit PCI devices starting from 18 are processor configuration devices for each node and are not a bus itself. According to ACPI specification 6.3 section 6.1.5: "... _HID object must be used to describe any device that will be enumerated by OSPM. OSPM only enumerates a device when no bus enumerator can detect the device ID. ... Use the _ADR object to describe devices enumerated by bus enumerators other than OSPM." PCI device 18 with its functions has a standard enumerator, which is PCI enumerator so it needs a _ADR. Create a separate ACPI device for the processor configuration space. This fixes the ACPI compliance problem from CB:36318. Signed-off-by: Michał Żygowski Change-Id: Ie7b45ce8d9e4fdd80d90752bf51bba4d30041507 Reviewed-on: https://review.coreboot.org/c/coreboot/+/37835 Reviewed-by: Patrick Georgi Reviewed-by: Paul Menzel Reviewed-by: HAOUAS Elyes Tested-by: build bot (Jenkins) --- src/northbridge/amd/agesa/family14/acpi/northbridge.asl | 5 ++++- src/northbridge/amd/agesa/family15tn/acpi/northbridge.asl | 5 ++++- src/northbridge/amd/agesa/family16kb/acpi/northbridge.asl | 5 ++++- src/northbridge/amd/pi/00630F01/acpi/northbridge.asl | 5 ++++- src/northbridge/amd/pi/00660F01/acpi/northbridge.asl | 5 ++++- src/northbridge/amd/pi/00730F01/acpi/northbridge.asl | 5 ++++- src/soc/amd/picasso/acpi/northbridge.asl | 5 ++++- src/soc/amd/stoneyridge/acpi/northbridge.asl | 5 ++++- 8 files changed, 32 insertions(+), 8 deletions(-) diff --git a/src/northbridge/amd/agesa/family14/acpi/northbridge.asl b/src/northbridge/amd/agesa/family14/acpi/northbridge.asl index 06199a1b07..6e3bc934b1 100644 --- a/src/northbridge/amd/agesa/family14/acpi/northbridge.asl +++ b/src/northbridge/amd/agesa/family14/acpi/northbridge.asl @@ -18,13 +18,16 @@ External (TOM1) External (TOM2) Name(_HID, EISAID("PNP0A08")) /* PCI Express Root Bridge */ Name(_CID, EISAID("PNP0A03")) /* PCI Root Bridge */ -Name(_ADR, 0x00180000) /* Dev# = BSP Dev#, Func# = 0 */ /* Describe the Northbridge devices */ Device(AMRT) { Name(_ADR, 0x00000000) } /* end AMRT */ +Device(PCSD) { /* Processor configuration space devices */ + Name(_ADR, 0x00180000) /* Dev# = BSP Dev#, Func# = 0 */ +} + /* The internal GFX bridge */ Device(AGPB) { Name(_ADR, 0x00010000) diff --git a/src/northbridge/amd/agesa/family15tn/acpi/northbridge.asl b/src/northbridge/amd/agesa/family15tn/acpi/northbridge.asl index 9a1fa9ed88..f679234e14 100644 --- a/src/northbridge/amd/agesa/family15tn/acpi/northbridge.asl +++ b/src/northbridge/amd/agesa/family15tn/acpi/northbridge.asl @@ -17,7 +17,6 @@ External (TOM1) External (TOM2) Name(_HID, EISAID("PNP0A03")) /* PCI Express Root Bridge */ -Name(_ADR, 0x00180000) /* Dev# = BSP Dev#, Func# = 0 */ /* Describe the Northbridge devices */ @@ -45,6 +44,10 @@ Device(AMRT) { Name(_ADR, 0x00000000) } /* end AMRT */ +Device(PCSD) { /* Processor configuration space devices */ + Name(_ADR, 0x00180000) /* Dev# = BSP Dev#, Func# = 0 */ +} + /* Dev2 is also an external GFX bridge */ Device(PBR2) { Name(_ADR, 0x00020000) diff --git a/src/northbridge/amd/agesa/family16kb/acpi/northbridge.asl b/src/northbridge/amd/agesa/family16kb/acpi/northbridge.asl index f74b31a080..3300db0c9c 100644 --- a/src/northbridge/amd/agesa/family16kb/acpi/northbridge.asl +++ b/src/northbridge/amd/agesa/family16kb/acpi/northbridge.asl @@ -18,7 +18,6 @@ External (TOM1) External (TOM2) Name(_HID, EISAID("PNP0A08")) /* PCI Express Root Bridge */ Name(_CID, EISAID("PNP0A03")) /* PCI Root Bridge */ -Name(_ADR, 0x00180000) /* Dev# = BSP Dev#, Func# = 0 */ /* Describe the Northbridge devices */ @@ -45,6 +44,10 @@ Device(AMRT) { Name(_ADR, 0x00000000) } /* end AMRT */ +Device(PCSD) { /* Processor configuration space devices */ + Name(_ADR, 0x00180000) /* Dev# = BSP Dev#, Func# = 0 */ +} + /* Gpp 0 */ Device(PBR4) { Name(_ADR, 0x00020001) diff --git a/src/northbridge/amd/pi/00630F01/acpi/northbridge.asl b/src/northbridge/amd/pi/00630F01/acpi/northbridge.asl index c2b3aac4c5..f3d42fa4ad 100644 --- a/src/northbridge/amd/pi/00630F01/acpi/northbridge.asl +++ b/src/northbridge/amd/pi/00630F01/acpi/northbridge.asl @@ -17,7 +17,6 @@ External (TOM1) External (TOM2) Name(_HID, EISAID("PNP0A03")) /* PCI Express Root Bridge */ -Name(_ADR, 0x00180000) /* Dev# = BSP Dev#, Func# = 0 */ /* Describe the Northbridge devices */ @@ -45,6 +44,10 @@ Device(AMRT) { Name(_ADR, 0x00000000) } /* end AMRT */ +Device(PCSD) { /* Processor configuration space devices */ + Name(_ADR, 0x00180000) /* Dev# = BSP Dev#, Func# = 0 */ +} + /* Dev2 is also an external GFX bridge */ Device(PBR2) { Name(_ADR, 0x00020000) diff --git a/src/northbridge/amd/pi/00660F01/acpi/northbridge.asl b/src/northbridge/amd/pi/00660F01/acpi/northbridge.asl index d54f985e90..761ff44399 100644 --- a/src/northbridge/amd/pi/00660F01/acpi/northbridge.asl +++ b/src/northbridge/amd/pi/00660F01/acpi/northbridge.asl @@ -18,7 +18,6 @@ External (TOM1) External (TOM2) Name(_HID, EISAID("PNP0A08")) /* PCI Express Root Bridge */ Name(_CID, EISAID("PNP0A03")) /* PCI Root Bridge */ -Name(_ADR, 0x00180000) /* Dev# = BSP Dev#, Func# = 0 */ /* Describe the Northbridge devices */ @@ -45,6 +44,10 @@ Device(AMRT) { Name(_ADR, 0x00000000) } /* end AMRT */ +Device(PCSD) { /* Processor configuration space devices */ + Name(_ADR, 0x00180000) /* Dev# = BSP Dev#, Func# = 0 */ +} + /* Gpp 0 */ Device(PBR4) { Name(_ADR, 0x00020001) diff --git a/src/northbridge/amd/pi/00730F01/acpi/northbridge.asl b/src/northbridge/amd/pi/00730F01/acpi/northbridge.asl index f74b31a080..3300db0c9c 100644 --- a/src/northbridge/amd/pi/00730F01/acpi/northbridge.asl +++ b/src/northbridge/amd/pi/00730F01/acpi/northbridge.asl @@ -18,7 +18,6 @@ External (TOM1) External (TOM2) Name(_HID, EISAID("PNP0A08")) /* PCI Express Root Bridge */ Name(_CID, EISAID("PNP0A03")) /* PCI Root Bridge */ -Name(_ADR, 0x00180000) /* Dev# = BSP Dev#, Func# = 0 */ /* Describe the Northbridge devices */ @@ -45,6 +44,10 @@ Device(AMRT) { Name(_ADR, 0x00000000) } /* end AMRT */ +Device(PCSD) { /* Processor configuration space devices */ + Name(_ADR, 0x00180000) /* Dev# = BSP Dev#, Func# = 0 */ +} + /* Gpp 0 */ Device(PBR4) { Name(_ADR, 0x00020001) diff --git a/src/soc/amd/picasso/acpi/northbridge.asl b/src/soc/amd/picasso/acpi/northbridge.asl index fe78534403..b1c2d31bc2 100644 --- a/src/soc/amd/picasso/acpi/northbridge.asl +++ b/src/soc/amd/picasso/acpi/northbridge.asl @@ -19,7 +19,6 @@ External (TOM1) External (TOM2) Name(_HID, EISAID("PNP0A08")) /* PCI Express Root Bridge */ Name(_CID, EISAID("PNP0A03")) /* PCI Root Bridge */ -Name(_ADR, 0x00180000) /* Dev# = BSP Dev#, Func# = 0 */ /* Describe the Northbridge devices */ @@ -46,6 +45,10 @@ Device(AMRT) { Name(_ADR, 0x00000000) } /* end AMRT */ +Device(PCSD) { /* Processor configuration space devices */ + Name(_ADR, 0x00180000) /* Dev# = BSP Dev#, Func# = 0 */ +} + /* Internal Graphics */ Device(IGFX) { Name(_ADR, 0x00010000) diff --git a/src/soc/amd/stoneyridge/acpi/northbridge.asl b/src/soc/amd/stoneyridge/acpi/northbridge.asl index fe78534403..b1c2d31bc2 100644 --- a/src/soc/amd/stoneyridge/acpi/northbridge.asl +++ b/src/soc/amd/stoneyridge/acpi/northbridge.asl @@ -19,7 +19,6 @@ External (TOM1) External (TOM2) Name(_HID, EISAID("PNP0A08")) /* PCI Express Root Bridge */ Name(_CID, EISAID("PNP0A03")) /* PCI Root Bridge */ -Name(_ADR, 0x00180000) /* Dev# = BSP Dev#, Func# = 0 */ /* Describe the Northbridge devices */ @@ -46,6 +45,10 @@ Device(AMRT) { Name(_ADR, 0x00000000) } /* end AMRT */ +Device(PCSD) { /* Processor configuration space devices */ + Name(_ADR, 0x00180000) /* Dev# = BSP Dev#, Func# = 0 */ +} + /* Internal Graphics */ Device(IGFX) { Name(_ADR, 0x00010000) From 9ac409c7e5062ee61d1259a20bf480ec6834d9b3 Mon Sep 17 00:00:00 2001 From: Wisley Chen Date: Thu, 19 Dec 2019 21:52:54 +0800 Subject: [PATCH 0801/1242] mb/google/hatch/var/jinlon: Config WWAN_RESET jinlon supports LTE, so remove WWAN_RESET NC configuration BUG=none TEST=emerge-hatch coreboot Change-Id: Ibc5d21f0a33952f519265a5ce2df559a79346d9e Signed-off-by: Wisley Chen Reviewed-on: https://review.coreboot.org/c/coreboot/+/37837 Reviewed-by: Paul Fagerburg Tested-by: build bot (Jenkins) --- src/mainboard/google/hatch/variants/jinlon/gpio.c | 2 -- 1 file changed, 2 deletions(-) diff --git a/src/mainboard/google/hatch/variants/jinlon/gpio.c b/src/mainboard/google/hatch/variants/jinlon/gpio.c index 7e475fa6a2..4622a72740 100644 --- a/src/mainboard/google/hatch/variants/jinlon/gpio.c +++ b/src/mainboard/google/hatch/variants/jinlon/gpio.c @@ -29,8 +29,6 @@ static const struct pad_config gpio_table[] = { PAD_NC(GPP_A10, NONE), /* C12 : FPMCU_PCH_BOOT1 */ PAD_CFG_GPO(GPP_C12, 0, DEEP), - /* F1 : NC */ - PAD_NC(GPP_F1, NONE), /* F3 : MEM_STRAP_3 */ PAD_CFG_GPI(GPP_F3, NONE, PLTRST), /* F10 : MEM_STRAP_2 */ From 6de7ecb585e705beab32e7464d364f2284ccae54 Mon Sep 17 00:00:00 2001 From: David Wu Date: Thu, 19 Dec 2019 17:20:53 +0800 Subject: [PATCH 0802/1242] mb/google/hatch/var/kindred: Decrease i2c frequency below 400 KHz Before tuning i2c frequency, I2C0: 479.4 KHz I2C1: 491.4 KHz I2C4: 476.4 KHz After tuning i2c frequency, I2C0: 391.8 KHz I2C1: 396.4 KHz I2C4: 388.8 KHz BUG=b:146535585 BRANCH=hatch TEST=emerge-hatch coreboot chromeos-bootimage Change-Id: I55d095efb60eba4e860b54bb90e8e0df62d88419 Signed-off-by: David Wu Reviewed-on: https://review.coreboot.org/c/coreboot/+/37831 Reviewed-by: Philip Chen Reviewed-by: Paul Fagerburg Reviewed-by: Paul Menzel Tested-by: build bot (Jenkins) --- src/mainboard/google/hatch/variants/kindred/overridetree.cb | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/src/mainboard/google/hatch/variants/kindred/overridetree.cb b/src/mainboard/google/hatch/variants/kindred/overridetree.cb index 1122609649..a000add5b0 100644 --- a/src/mainboard/google/hatch/variants/kindred/overridetree.cb +++ b/src/mainboard/google/hatch/variants/kindred/overridetree.cb @@ -36,12 +36,18 @@ chip soc/intel/cannonlake }, .i2c[0] = { .speed = I2C_SPEED_FAST, + .rise_time_ns = 50, + .fall_time_ns = 15, }, .i2c[1] = { .speed = I2C_SPEED_FAST, + .rise_time_ns = 60, + .fall_time_ns = 25, }, .i2c[4] = { .speed = I2C_SPEED_FAST, + .rise_time_ns = 60, + .fall_time_ns = 60, }, }" From 6ee5559d6a3c1ba452a53db58ec6b41d629d92b2 Mon Sep 17 00:00:00 2001 From: Huayang Duan Date: Wed, 20 Nov 2019 13:51:47 +0800 Subject: [PATCH 0803/1242] soc/mediatek/mt8183: Use DDR clock to compute Tx delay cell The delay cell result should use DDR clock PLL rate for computation, and should not be divided by 2. This helps to improve DRAM stability. BUG=b:80501386,b:142358843 BRANCH=kukui TEST=Boots correctly on Kukui Change-Id: Idf5cce206e248bb327f9a7d27c4f364ef1c68aa1 Signed-off-by: Huayang Duan Reviewed-on: https://review.coreboot.org/c/coreboot/+/36990 Tested-by: build bot (Jenkins) Reviewed-by: Hung-Te Lin Reviewed-by: Patrick Georgi --- .../mt8183/dramc_pi_calibration_api.c | 20 +++++++++++++------ 1 file changed, 14 insertions(+), 6 deletions(-) diff --git a/src/soc/mediatek/mt8183/dramc_pi_calibration_api.c b/src/soc/mediatek/mt8183/dramc_pi_calibration_api.c index 8c17d84df0..0ec0193664 100644 --- a/src/soc/mediatek/mt8183/dramc_pi_calibration_api.c +++ b/src/soc/mediatek/mt8183/dramc_pi_calibration_api.c @@ -1588,18 +1588,24 @@ static void dramc_set_tx_best_dly(u8 chn, u8 rank, bool bypass_tx, struct per_byte_dly center_dly[DQS_NUMBER]; u16 tune_diff, dq_delay_cell[DQ_DATA_WIDTH]; + + /* + * The clock rate is usually (frequency / 2 - delta), where the delta + * is introduced to avoid interference from RF peripherals like + * modem, WiFi, and Bluetooth. + */ switch (freq_group) { case LP4X_DDR1600: - clock_rate = 800; + clock_rate = 796; break; case LP4X_DDR2400: - clock_rate = 1200; + clock_rate = 1196; break; case LP4X_DDR3200: - clock_rate = 1600; + clock_rate = 1596; break; case LP4X_DDR3600: - clock_rate = 1866; + clock_rate = 1792; break; default: die("Invalid DDR frequency group %u\n", freq_group); @@ -1612,7 +1618,7 @@ static void dramc_set_tx_best_dly(u8 chn, u8 rank, bool bypass_tx, use_delay_cell = 0; if (fast_calib && bypass_tx) { - dramc_dbg("bypass TX\n"); + dramc_dbg("bypass TX, clock_rate: %d\n", clock_rate); for (u8 byte = 0; byte < DQS_NUMBER; byte++) { center_dly[byte].min_center = params->tx_center_min[chn][rank][byte]; center_dly[byte].max_center = params->tx_center_max[chn][rank][byte]; @@ -1645,8 +1651,10 @@ static void dramc_set_tx_best_dly(u8 chn, u8 rank, bool bypass_tx, tune_diff = vref_dly[index].win_center - center_dly[byte].min_center; dq_delay_cell[index] = ((tune_diff * 100000000) / - (clock_rate / 2 * 64)) / dly_cell_unit; + (clock_rate * 64)) / dly_cell_unit; byte_dly_cell[byte] |= (dq_delay_cell[index] << (bit * 4)); + dramc_show("u1DelayCellOfst[%d]=%d cells (%d PI)\n", + index, dq_delay_cell[index], tune_diff); } } } From e9b1e0fe8873cb3131b0dc4741e83540e0d90a31 Mon Sep 17 00:00:00 2001 From: Maulik V Vaghela Date: Mon, 16 Dec 2019 16:39:53 +0530 Subject: [PATCH 0804/1242] soc/intel/tigerlake: Update FSP stack and heap size Tigerlake and Jasperlake fsp requires stack size to be minimum 192 KiB and heap size to be minimum 128 KiB. Updating both Kconfig to meet size requirements. Also updated required CAR region size during boot block due to increment in stack & heap requirement by fsp Change-Id: I38e93b5986811ff3e0a8df5f4f36af35f308cb6b Signed-off-by: Maulik V Vaghela Reviewed-on: https://review.coreboot.org/c/coreboot/+/37764 Reviewed-by: Rizwan Qureshi Reviewed-by: Subrata Banik Reviewed-by: Wonkyu Kim Tested-by: build bot (Jenkins) --- src/soc/intel/tigerlake/Kconfig | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/src/soc/intel/tigerlake/Kconfig b/src/soc/intel/tigerlake/Kconfig index 7bb533ab71..be4e26c2cc 100644 --- a/src/soc/intel/tigerlake/Kconfig +++ b/src/soc/intel/tigerlake/Kconfig @@ -74,22 +74,22 @@ config DCACHE_RAM_BASE default 0xfef00000 config DCACHE_RAM_SIZE - default 0x40000 + default 0x80000 help The size of the cache-as-ram region required during bootblock and/or romstage. config DCACHE_BSP_STACK_SIZE hex - default 0x20400 + default 0x30400 help The amount of anticipated stack usage in CAR by bootblock and other stages. In the case of FSP_USES_CB_STACK default value will be - sum of FSP-M stack requirement (128KiB) and CB romstage stack requirement (~1KiB). + sum of FSP-M stack requirement (192KiB) and CB romstage stack requirement (~1KiB). config FSP_TEMP_RAM_SIZE hex - default 0x10000 + default 0x20000 help The amount of anticipated heap usage in CAR by FSP. Refer to Platform FSP integration guide document to know From cdf6f3a4ba8429ad76738ff46220c067da065001 Mon Sep 17 00:00:00 2001 From: Bill XIE Date: Tue, 17 Dec 2019 15:56:43 +0800 Subject: [PATCH 0805/1242] security/vboot: Add a dedicated flag for building of vboot library As discussed in CB:35077, since both measured boot and verified boot depends on vboot library, it had better to introduce a dedicated flag CONFIG_VBOOT_LIB to control the building and linking of the vboot library, and make other flags needing vboot library select it. Only the actual verification stuff should be conditional on CONFIG_VBOOT. Change-Id: Ia1907a11c851ee45a70582e02bdbe08fb18cc6a4 Signed-off-by: Bill XIE Reviewed-on: https://review.coreboot.org/c/coreboot/+/37787 Tested-by: build bot (Jenkins) Reviewed-by: Joel Kitching --- src/security/vboot/Kconfig | 9 +++++ src/security/vboot/Makefile.inc | 70 +++++++++++++++++---------------- 2 files changed, 46 insertions(+), 33 deletions(-) diff --git a/src/security/vboot/Kconfig b/src/security/vboot/Kconfig index e03b51dd06..787cdbefb1 100644 --- a/src/security/vboot/Kconfig +++ b/src/security/vboot/Kconfig @@ -15,9 +15,18 @@ menu "Verified Boot (vboot)" +config VBOOT_LIB + bool + depends on !VENDORCODE_ELTAN_VBOOT && !VENDORCODE_ELTAN_MBOOT + help + Build and link the vboot library. Makes the vboot API accessible across + all coreboot stages, without enabling vboot verification. For verification, + please see the VBOOT option below. + config VBOOT bool "Verify firmware with vboot." default n + select VBOOT_LIB select VBOOT_MOCK_SECDATA if !TPM1 && !TPM2 depends on !MISSING_BOARD_RESET help diff --git a/src/security/vboot/Makefile.inc b/src/security/vboot/Makefile.inc index 8052549bde..a700e0051a 100644 --- a/src/security/vboot/Makefile.inc +++ b/src/security/vboot/Makefile.inc @@ -14,6 +14,43 @@ ## GNU General Public License for more details. ## +ifeq ($(CONFIG_VBOOT_LIB),y) + +vboot-fixup-includes = $(patsubst -I%,-I$(top)/%,\ + $(patsubst $(src)/%.h,$(top)/$(src)/%.h,\ + $(filter-out -I$(obj),$(1)))) + +# call with $1 = stage name to create rules for building the library +# for the stage and adding it to the stage's set of object files. +define vboot-for-stage +VBOOT_LIB_$(1) = $(obj)/external/vboot_reference-$(1)/vboot_fw.a +VBOOT_CFLAGS_$(1) += $$(call vboot-fixup-includes,$$(CPPFLAGS_$(1))) +VBOOT_CFLAGS_$(1) += $$(CFLAGS_$(1)) +VBOOT_CFLAGS_$(1) += $$(call vboot-fixup-includes,$$($(1)-c-ccopts)) +VBOOT_CFLAGS_$(1) += -I$(abspath $(obj)) -Wno-missing-prototypes +VBOOT_CFLAGS_$(1) += -DVBOOT_DEBUG + +$$(VBOOT_LIB_$(1)): $(obj)/config.h + printf " MAKE $(subst $(obj)/,,$(@))\n" + +FIRMWARE_ARCH=$$(ARCHDIR-$$(ARCH-$(1)-y)) \ + CC="$$(CC_$(1))" \ + CFLAGS="$$(VBOOT_CFLAGS_$(1))" VBOOT2="y" \ + $(MAKE) -C $(VBOOT_SOURCE) \ + BUILD=$$(abspath $$(dir $$(VBOOT_LIB_$(1)))) \ + V=$(V) \ + fwlib + +$(1)-srcs += $$(VBOOT_LIB_$(1)) + +endef # vboot-for-stage + +$(eval $(call vboot-for-stage,bootblock)) +$(eval $(call vboot-for-stage,romstage)) +$(eval $(call vboot-for-stage,ramstage)) +$(eval $(call vboot-for-stage,postcar)) + +endif # CONFIG_VBOOT_LIB + ifeq ($(CONFIG_VBOOT),y) bootblock-y += bootmode.c @@ -95,39 +132,6 @@ postcar-y += common.c romstage-$(CONFIG_FSP2_0_USES_TPM_MRC_HASH) += mrc_cache_hash_tpm.c -vboot-fixup-includes = $(patsubst -I%,-I$(top)/%,\ - $(patsubst $(src)/%.h,$(top)/$(src)/%.h,\ - $(filter-out -I$(obj),$(1)))) - -# call with $1 = stage name to create rules for building the library -# for the stage and adding it to the stage's set of object files. -define vboot-for-stage -VBOOT_LIB_$(1) = $(obj)/external/vboot_reference-$(1)/vboot_fw.a -VBOOT_CFLAGS_$(1) += $$(call vboot-fixup-includes,$$(CPPFLAGS_$(1))) -VBOOT_CFLAGS_$(1) += $$(CFLAGS_$(1)) -VBOOT_CFLAGS_$(1) += $$(call vboot-fixup-includes,$$($(1)-c-ccopts)) -VBOOT_CFLAGS_$(1) += -I$(abspath $(obj)) -Wno-missing-prototypes -VBOOT_CFLAGS_$(1) += -DVBOOT_DEBUG - -$$(VBOOT_LIB_$(1)): $(obj)/config.h - printf " MAKE $(subst $(obj)/,,$(@))\n" - +FIRMWARE_ARCH=$$(ARCHDIR-$$(ARCH-$(1)-y)) \ - CC="$$(CC_$(1))" \ - CFLAGS="$$(VBOOT_CFLAGS_$(1))" VBOOT2="y" \ - $(MAKE) -C $(VBOOT_SOURCE) \ - BUILD=$$(abspath $$(dir $$(VBOOT_LIB_$(1)))) \ - V=$(V) \ - fwlib - -$(1)-srcs += $$(VBOOT_LIB_$(1)) - -endef # vboot-for-stage - -$(eval $(call vboot-for-stage,bootblock)) -$(eval $(call vboot-for-stage,romstage)) -$(eval $(call vboot-for-stage,ramstage)) -$(eval $(call vboot-for-stage,postcar)) - ifeq ($(CONFIG_VBOOT_SEPARATE_VERSTAGE),y) $(eval $(call vboot-for-stage,verstage)) From ed69de318f4a87a8fe2c82a9cd5b2893c8538f38 Mon Sep 17 00:00:00 2001 From: Elyes HAOUAS Date: Thu, 19 Dec 2019 17:36:53 +0100 Subject: [PATCH 0806/1242] mainboard: Add missing include Change-Id: I8a7c989540e8b62de7fd291f695adac849f4680c Signed-off-by: Elyes HAOUAS Reviewed-on: https://review.coreboot.org/c/coreboot/+/37843 Tested-by: build bot (Jenkins) Reviewed-by: Werner Zeh Reviewed-by: Paul Menzel --- src/mainboard/amd/gardenia/irq_tables.c | 1 + src/mainboard/aopen/dxplplusu/acpi_tables.c | 1 + src/mainboard/asrock/e350m1/irq_tables.c | 1 + src/mainboard/asrock/imb-a180/irq_tables.c | 1 + src/mainboard/emulation/qemu-i440fx/northbridge.c | 1 + src/mainboard/gizmosphere/gizmo/irq_tables.c | 1 + src/mainboard/pcengines/apu1/irq_tables.c | 1 + src/mainboard/pcengines/apu2/irq_tables.c | 1 + 8 files changed, 8 insertions(+) diff --git a/src/mainboard/amd/gardenia/irq_tables.c b/src/mainboard/amd/gardenia/irq_tables.c index bf1daec8a6..3af2757c1f 100644 --- a/src/mainboard/amd/gardenia/irq_tables.c +++ b/src/mainboard/amd/gardenia/irq_tables.c @@ -15,6 +15,7 @@ #include #include +#include #include #include #include diff --git a/src/mainboard/aopen/dxplplusu/acpi_tables.c b/src/mainboard/aopen/dxplplusu/acpi_tables.c index cc6835b939..70bfa27978 100644 --- a/src/mainboard/aopen/dxplplusu/acpi_tables.c +++ b/src/mainboard/aopen/dxplplusu/acpi_tables.c @@ -20,6 +20,7 @@ #include #include +#include #define IOAPIC_ICH4 2 #define IOAPIC_P64H2_BUS_B 3 /* IOAPIC 3 at 02:1c.0 */ diff --git a/src/mainboard/asrock/e350m1/irq_tables.c b/src/mainboard/asrock/e350m1/irq_tables.c index 9ebe58ae65..0bcb041558 100644 --- a/src/mainboard/asrock/e350m1/irq_tables.c +++ b/src/mainboard/asrock/e350m1/irq_tables.c @@ -15,6 +15,7 @@ #include #include +#include #include #include #include diff --git a/src/mainboard/asrock/imb-a180/irq_tables.c b/src/mainboard/asrock/imb-a180/irq_tables.c index e18e47842a..be71dd491f 100644 --- a/src/mainboard/asrock/imb-a180/irq_tables.c +++ b/src/mainboard/asrock/imb-a180/irq_tables.c @@ -15,6 +15,7 @@ #include #include +#include #include #include #include diff --git a/src/mainboard/emulation/qemu-i440fx/northbridge.c b/src/mainboard/emulation/qemu-i440fx/northbridge.c index 0bff4d7dd8..1c27a0fde8 100644 --- a/src/mainboard/emulation/qemu-i440fx/northbridge.c +++ b/src/mainboard/emulation/qemu-i440fx/northbridge.c @@ -15,6 +15,7 @@ #include #include #include +#include #include #include #include diff --git a/src/mainboard/gizmosphere/gizmo/irq_tables.c b/src/mainboard/gizmosphere/gizmo/irq_tables.c index ca30cc7ce3..bf2379c29e 100644 --- a/src/mainboard/gizmosphere/gizmo/irq_tables.c +++ b/src/mainboard/gizmosphere/gizmo/irq_tables.c @@ -16,6 +16,7 @@ #include #include +#include #include #include #include diff --git a/src/mainboard/pcengines/apu1/irq_tables.c b/src/mainboard/pcengines/apu1/irq_tables.c index 9ebe58ae65..0bcb041558 100644 --- a/src/mainboard/pcengines/apu1/irq_tables.c +++ b/src/mainboard/pcengines/apu1/irq_tables.c @@ -15,6 +15,7 @@ #include #include +#include #include #include #include diff --git a/src/mainboard/pcengines/apu2/irq_tables.c b/src/mainboard/pcengines/apu2/irq_tables.c index f7302baf06..2c9340199c 100644 --- a/src/mainboard/pcengines/apu2/irq_tables.c +++ b/src/mainboard/pcengines/apu2/irq_tables.c @@ -15,6 +15,7 @@ #include #include +#include #include #include #include From b9bd69e70ed355d89ff41d66ed7134338c5986fe Mon Sep 17 00:00:00 2001 From: Elyes HAOUAS Date: Thu, 5 Dec 2019 15:04:55 +0100 Subject: [PATCH 0807/1242] src/mainboard: Remove unused '#include ' Change-Id: I5791fddec8b2387df5979adbb1a0fa64c5dd23ea Signed-off-by: Elyes HAOUAS Reviewed-on: https://review.coreboot.org/c/coreboot/+/37522 Tested-by: build bot (Jenkins) Reviewed-by: Werner Zeh --- src/mainboard/amd/bettong/acpi_tables.c | 1 - src/mainboard/amd/bettong/irq_tables.c | 1 - src/mainboard/amd/bettong/mptable.c | 1 - src/mainboard/amd/db-ft3b-lc/acpi_tables.c | 1 - src/mainboard/amd/db-ft3b-lc/irq_tables.c | 1 - src/mainboard/amd/db-ft3b-lc/mainboard.c | 1 - src/mainboard/amd/db-ft3b-lc/mptable.c | 1 - src/mainboard/amd/gardenia/irq_tables.c | 1 - src/mainboard/amd/gardenia/mptable.c | 1 - src/mainboard/amd/inagua/acpi_tables.c | 1 - src/mainboard/amd/inagua/irq_tables.c | 1 - src/mainboard/amd/inagua/mptable.c | 1 - src/mainboard/amd/lamar/acpi_tables.c | 1 - src/mainboard/amd/lamar/irq_tables.c | 1 - src/mainboard/amd/lamar/mainboard.c | 1 - src/mainboard/amd/lamar/mptable.c | 1 - src/mainboard/amd/olivehill/acpi_tables.c | 1 - src/mainboard/amd/olivehill/irq_tables.c | 1 - src/mainboard/amd/olivehill/mptable.c | 1 - src/mainboard/amd/olivehillplus/acpi_tables.c | 1 - src/mainboard/amd/olivehillplus/irq_tables.c | 1 - src/mainboard/amd/olivehillplus/mainboard.c | 1 - src/mainboard/amd/olivehillplus/mptable.c | 1 - src/mainboard/amd/padmelon/bootblock/bootblock.c | 1 - src/mainboard/amd/parmer/acpi_tables.c | 1 - src/mainboard/amd/parmer/irq_tables.c | 1 - src/mainboard/amd/parmer/mptable.c | 1 - src/mainboard/amd/persimmon/acpi_tables.c | 1 - src/mainboard/amd/persimmon/irq_tables.c | 1 - src/mainboard/amd/persimmon/mptable.c | 1 - src/mainboard/amd/south_station/acpi_tables.c | 1 - src/mainboard/amd/south_station/irq_tables.c | 1 - src/mainboard/amd/south_station/mptable.c | 1 - src/mainboard/amd/thatcher/acpi_tables.c | 1 - src/mainboard/amd/thatcher/irq_tables.c | 1 - src/mainboard/amd/thatcher/mptable.c | 1 - src/mainboard/amd/union_station/acpi_tables.c | 1 - src/mainboard/amd/union_station/irq_tables.c | 1 - src/mainboard/amd/union_station/mptable.c | 1 - src/mainboard/aopen/dxplplusu/acpi_tables.c | 1 - src/mainboard/aopen/dxplplusu/fadt.c | 1 - src/mainboard/apple/macbook21/mptable.c | 1 - src/mainboard/asrock/e350m1/acpi_tables.c | 1 - src/mainboard/asrock/e350m1/irq_tables.c | 1 - src/mainboard/asrock/e350m1/mptable.c | 1 - src/mainboard/asrock/imb-a180/acpi_tables.c | 1 - src/mainboard/asrock/imb-a180/irq_tables.c | 1 - src/mainboard/asrock/imb-a180/mptable.c | 1 - src/mainboard/asus/am1i-a/acpi_tables.c | 1 - src/mainboard/asus/am1i-a/mptable.c | 1 - src/mainboard/asus/f2a85-m/acpi_tables.c | 1 - src/mainboard/asus/f2a85-m/mptable.c | 1 - src/mainboard/asus/p2b-d/mptable.c | 1 - src/mainboard/asus/p2b-ds/mptable.c | 1 - src/mainboard/bap/ode_e20XX/acpi_tables.c | 1 - src/mainboard/bap/ode_e20XX/irq_tables.c | 1 - src/mainboard/bap/ode_e20XX/mptable.c | 1 - src/mainboard/bap/ode_e21XX/acpi_tables.c | 1 - src/mainboard/bap/ode_e21XX/irq_tables.c | 1 - src/mainboard/bap/ode_e21XX/mainboard.c | 1 - src/mainboard/bap/ode_e21XX/mptable.c | 1 - src/mainboard/biostar/a68n_5200/acpi_tables.c | 1 - src/mainboard/biostar/a68n_5200/irq_tables.c | 1 - src/mainboard/biostar/a68n_5200/mptable.c | 1 - src/mainboard/biostar/am1ml/acpi_tables.c | 1 - src/mainboard/biostar/am1ml/mptable.c | 1 - src/mainboard/elmex/pcm205400/acpi_tables.c | 1 - src/mainboard/elmex/pcm205400/irq_tables.c | 1 - src/mainboard/elmex/pcm205400/mptable.c | 1 - src/mainboard/emulation/qemu-i440fx/northbridge.c | 1 - src/mainboard/emulation/qemu-q35/acpi_tables.c | 1 - src/mainboard/getac/p470/acpi_tables.c | 1 - src/mainboard/getac/p470/mptable.c | 1 - src/mainboard/gizmosphere/gizmo/acpi_tables.c | 1 - src/mainboard/gizmosphere/gizmo/irq_tables.c | 1 - src/mainboard/gizmosphere/gizmo/mptable.c | 1 - src/mainboard/gizmosphere/gizmo2/acpi_tables.c | 1 - src/mainboard/gizmosphere/gizmo2/irq_tables.c | 1 - src/mainboard/gizmosphere/gizmo2/mptable.c | 1 - src/mainboard/google/auron/variants/buddy/variant.c | 1 - src/mainboard/google/beltino/acpi_tables.c | 1 - src/mainboard/google/beltino/chromeos.c | 1 - src/mainboard/google/beltino/lan.c | 1 - src/mainboard/google/butterfly/chromeos.c | 1 - src/mainboard/google/butterfly/mainboard.c | 1 - src/mainboard/google/jecht/acpi_tables.c | 1 - src/mainboard/google/jecht/chromeos.c | 1 - src/mainboard/google/jecht/lan.c | 1 - src/mainboard/google/kahlee/irq_tables.c | 1 - src/mainboard/google/kahlee/mptable.c | 1 - src/mainboard/google/kahlee/variants/baseboard/mainboard.c | 1 - src/mainboard/google/link/early_init.c | 1 - src/mainboard/google/link/mainboard.c | 1 - src/mainboard/google/parrot/acpi_tables.c | 1 - src/mainboard/google/parrot/chromeos.c | 1 - src/mainboard/google/parrot/mainboard.c | 1 - src/mainboard/google/poppy/variants/nautilus/mainboard.c | 1 - src/mainboard/google/rambi/acpi_tables.c | 1 - src/mainboard/google/rambi/variants/ninja/lan.c | 1 - src/mainboard/google/rambi/variants/sumo/lan.c | 1 - src/mainboard/google/slippy/acpi_tables.c | 1 - src/mainboard/google/stout/acpi_tables.c | 1 - src/mainboard/google/stout/chromeos.c | 1 - src/mainboard/google/stout/ec.c | 1 - src/mainboard/google/stout/mainboard.c | 1 - src/mainboard/hp/abm/acpi_tables.c | 1 - src/mainboard/hp/abm/irq_tables.c | 1 - src/mainboard/hp/abm/mptable.c | 1 - src/mainboard/hp/pavilion_m6_1035dx/acpi_tables.c | 1 - src/mainboard/hp/pavilion_m6_1035dx/mptable.c | 1 - src/mainboard/ibase/mb899/mptable.c | 1 - src/mainboard/intel/baskingridge/acpi_tables.c | 1 - src/mainboard/intel/baskingridge/chromeos.c | 1 - src/mainboard/intel/d510mo/mainboard.c | 1 - src/mainboard/intel/d945gclf/mptable.c | 1 - src/mainboard/intel/emeraldlake2/acpi_tables.c | 1 - src/mainboard/intel/emeraldlake2/chromeos.c | 1 - src/mainboard/intel/harcuvar/acpi_tables.c | 1 - src/mainboard/intel/kblrvp/chromeos.c | 1 - src/mainboard/intel/strago/acpi_tables.c | 1 - src/mainboard/intel/wtm2/acpi_tables.c | 1 - src/mainboard/intel/wtm2/chromeos.c | 1 - src/mainboard/jetway/nf81-t56n-lf/acpi_tables.c | 1 - src/mainboard/jetway/nf81-t56n-lf/mptable.c | 1 - src/mainboard/kontron/986lcd-m/mptable.c | 1 - src/mainboard/lenovo/g505s/acpi_tables.c | 1 - src/mainboard/lenovo/g505s/mptable.c | 1 - src/mainboard/lenovo/t400/acpi_tables.c | 1 - src/mainboard/lenovo/t400/dock.c | 1 - src/mainboard/lenovo/t400/fadt.c | 1 - src/mainboard/lenovo/t420/early_init.c | 1 - src/mainboard/lenovo/t420s/early_init.c | 1 - src/mainboard/lenovo/t430/early_init.c | 1 - src/mainboard/lenovo/t520/early_init.c | 1 - src/mainboard/lenovo/t530/early_init.c | 1 - src/mainboard/lenovo/t60/mptable.c | 1 - src/mainboard/lenovo/x200/acpi_tables.c | 1 - src/mainboard/lenovo/x200/fadt.c | 1 - src/mainboard/lenovo/x60/mptable.c | 1 - src/mainboard/lippert/frontrunner-af/acpi_tables.c | 1 - src/mainboard/lippert/frontrunner-af/irq_tables.c | 1 - src/mainboard/lippert/frontrunner-af/mainboard.c | 1 - src/mainboard/lippert/frontrunner-af/mptable.c | 1 - src/mainboard/lippert/toucan-af/acpi_tables.c | 1 - src/mainboard/lippert/toucan-af/irq_tables.c | 1 - src/mainboard/lippert/toucan-af/mainboard.c | 1 - src/mainboard/lippert/toucan-af/mptable.c | 1 - src/mainboard/msi/ms7721/acpi_tables.c | 1 - src/mainboard/msi/ms7721/mptable.c | 1 - src/mainboard/packardbell/ms2290/mainboard.c | 1 - src/mainboard/pcengines/apu1/acpi_tables.c | 1 - src/mainboard/pcengines/apu1/irq_tables.c | 1 - src/mainboard/pcengines/apu1/mainboard.c | 1 - src/mainboard/pcengines/apu1/mptable.c | 1 - src/mainboard/pcengines/apu2/acpi_tables.c | 1 - src/mainboard/pcengines/apu2/irq_tables.c | 1 - src/mainboard/pcengines/apu2/mainboard.c | 1 - src/mainboard/roda/rk886ex/mptable.c | 1 - src/mainboard/roda/rk9/acpi_tables.c | 1 - src/mainboard/roda/rk9/fadt.c | 1 - src/mainboard/roda/rv11/variants/rv11/early_init.c | 1 - src/mainboard/roda/rv11/variants/rw11/early_init.c | 1 - src/mainboard/samsung/lumpy/acpi_tables.c | 1 - src/mainboard/samsung/lumpy/chromeos.c | 1 - src/mainboard/samsung/stumpy/acpi_tables.c | 1 - src/mainboard/samsung/stumpy/chromeos.c | 1 - src/mainboard/scaleway/tagada/acpi_tables.c | 1 - src/mainboard/siemens/mc_apl1/mainboard.c | 1 - 168 files changed, 168 deletions(-) diff --git a/src/mainboard/amd/bettong/acpi_tables.c b/src/mainboard/amd/bettong/acpi_tables.c index 8c6840476e..9117c1ffdf 100644 --- a/src/mainboard/amd/bettong/acpi_tables.c +++ b/src/mainboard/amd/bettong/acpi_tables.c @@ -15,7 +15,6 @@ #include #include -#include #define IO_APIC2_ADDR 0xFEC20000 diff --git a/src/mainboard/amd/bettong/irq_tables.c b/src/mainboard/amd/bettong/irq_tables.c index 2a961a4a15..45030994ba 100644 --- a/src/mainboard/amd/bettong/irq_tables.c +++ b/src/mainboard/amd/bettong/irq_tables.c @@ -14,7 +14,6 @@ */ #include -#include #include #include #include diff --git a/src/mainboard/amd/bettong/mptable.c b/src/mainboard/amd/bettong/mptable.c index af943f1212..d9632d58d1 100644 --- a/src/mainboard/amd/bettong/mptable.c +++ b/src/mainboard/amd/bettong/mptable.c @@ -14,7 +14,6 @@ */ #include -#include #include #include #include diff --git a/src/mainboard/amd/db-ft3b-lc/acpi_tables.c b/src/mainboard/amd/db-ft3b-lc/acpi_tables.c index 08f6076e7c..20509e9d31 100644 --- a/src/mainboard/amd/db-ft3b-lc/acpi_tables.c +++ b/src/mainboard/amd/db-ft3b-lc/acpi_tables.c @@ -15,7 +15,6 @@ #include #include -#include unsigned long acpi_fill_madt(unsigned long current) { diff --git a/src/mainboard/amd/db-ft3b-lc/irq_tables.c b/src/mainboard/amd/db-ft3b-lc/irq_tables.c index e18e47842a..530c132a05 100644 --- a/src/mainboard/amd/db-ft3b-lc/irq_tables.c +++ b/src/mainboard/amd/db-ft3b-lc/irq_tables.c @@ -14,7 +14,6 @@ */ #include -#include #include #include #include diff --git a/src/mainboard/amd/db-ft3b-lc/mainboard.c b/src/mainboard/amd/db-ft3b-lc/mainboard.c index 6ea80ed82c..a3396593f4 100644 --- a/src/mainboard/amd/db-ft3b-lc/mainboard.c +++ b/src/mainboard/amd/db-ft3b-lc/mainboard.c @@ -16,7 +16,6 @@ #include #include -#include #include #include #include diff --git a/src/mainboard/amd/db-ft3b-lc/mptable.c b/src/mainboard/amd/db-ft3b-lc/mptable.c index 3aad0e34f4..40a75ad1e1 100644 --- a/src/mainboard/amd/db-ft3b-lc/mptable.c +++ b/src/mainboard/amd/db-ft3b-lc/mptable.c @@ -15,7 +15,6 @@ */ #include -#include #include #include #include diff --git a/src/mainboard/amd/gardenia/irq_tables.c b/src/mainboard/amd/gardenia/irq_tables.c index 3af2757c1f..66dafb7f28 100644 --- a/src/mainboard/amd/gardenia/irq_tables.c +++ b/src/mainboard/amd/gardenia/irq_tables.c @@ -14,7 +14,6 @@ */ #include -#include #include #include #include diff --git a/src/mainboard/amd/gardenia/mptable.c b/src/mainboard/amd/gardenia/mptable.c index fa60d35605..5bb70e9449 100644 --- a/src/mainboard/amd/gardenia/mptable.c +++ b/src/mainboard/amd/gardenia/mptable.c @@ -14,7 +14,6 @@ */ #include -#include #include #include #include diff --git a/src/mainboard/amd/inagua/acpi_tables.c b/src/mainboard/amd/inagua/acpi_tables.c index 787c432041..97ea6492fb 100644 --- a/src/mainboard/amd/inagua/acpi_tables.c +++ b/src/mainboard/amd/inagua/acpi_tables.c @@ -15,7 +15,6 @@ #include #include -#include unsigned long acpi_fill_madt(unsigned long current) { diff --git a/src/mainboard/amd/inagua/irq_tables.c b/src/mainboard/amd/inagua/irq_tables.c index 9ebe58ae65..a066864abd 100644 --- a/src/mainboard/amd/inagua/irq_tables.c +++ b/src/mainboard/amd/inagua/irq_tables.c @@ -14,7 +14,6 @@ */ #include -#include #include #include #include diff --git a/src/mainboard/amd/inagua/mptable.c b/src/mainboard/amd/inagua/mptable.c index 8d1ec59d9c..1b4e64aa1a 100644 --- a/src/mainboard/amd/inagua/mptable.c +++ b/src/mainboard/amd/inagua/mptable.c @@ -14,7 +14,6 @@ */ #include -#include #include #include #include diff --git a/src/mainboard/amd/lamar/acpi_tables.c b/src/mainboard/amd/lamar/acpi_tables.c index 8b0c2c9690..65e74baf40 100644 --- a/src/mainboard/amd/lamar/acpi_tables.c +++ b/src/mainboard/amd/lamar/acpi_tables.c @@ -15,7 +15,6 @@ #include #include -#include unsigned long acpi_fill_madt(unsigned long current) { diff --git a/src/mainboard/amd/lamar/irq_tables.c b/src/mainboard/amd/lamar/irq_tables.c index be8c702736..9cc27f78ca 100644 --- a/src/mainboard/amd/lamar/irq_tables.c +++ b/src/mainboard/amd/lamar/irq_tables.c @@ -14,7 +14,6 @@ */ #include -#include #include #include #include diff --git a/src/mainboard/amd/lamar/mainboard.c b/src/mainboard/amd/lamar/mainboard.c index 3d338501a0..2f716d0c5d 100644 --- a/src/mainboard/amd/lamar/mainboard.c +++ b/src/mainboard/amd/lamar/mainboard.c @@ -15,7 +15,6 @@ #include #include -#include #include #include #include diff --git a/src/mainboard/amd/lamar/mptable.c b/src/mainboard/amd/lamar/mptable.c index d89e02fbef..1f2093dd3a 100644 --- a/src/mainboard/amd/lamar/mptable.c +++ b/src/mainboard/amd/lamar/mptable.c @@ -14,7 +14,6 @@ */ #include -#include #include #include #include diff --git a/src/mainboard/amd/olivehill/acpi_tables.c b/src/mainboard/amd/olivehill/acpi_tables.c index 08f6076e7c..20509e9d31 100644 --- a/src/mainboard/amd/olivehill/acpi_tables.c +++ b/src/mainboard/amd/olivehill/acpi_tables.c @@ -15,7 +15,6 @@ #include #include -#include unsigned long acpi_fill_madt(unsigned long current) { diff --git a/src/mainboard/amd/olivehill/irq_tables.c b/src/mainboard/amd/olivehill/irq_tables.c index e18e47842a..530c132a05 100644 --- a/src/mainboard/amd/olivehill/irq_tables.c +++ b/src/mainboard/amd/olivehill/irq_tables.c @@ -14,7 +14,6 @@ */ #include -#include #include #include #include diff --git a/src/mainboard/amd/olivehill/mptable.c b/src/mainboard/amd/olivehill/mptable.c index 3054effc19..52374f1529 100644 --- a/src/mainboard/amd/olivehill/mptable.c +++ b/src/mainboard/amd/olivehill/mptable.c @@ -14,7 +14,6 @@ */ #include -#include #include #include #include diff --git a/src/mainboard/amd/olivehillplus/acpi_tables.c b/src/mainboard/amd/olivehillplus/acpi_tables.c index 08f6076e7c..20509e9d31 100644 --- a/src/mainboard/amd/olivehillplus/acpi_tables.c +++ b/src/mainboard/amd/olivehillplus/acpi_tables.c @@ -15,7 +15,6 @@ #include #include -#include unsigned long acpi_fill_madt(unsigned long current) { diff --git a/src/mainboard/amd/olivehillplus/irq_tables.c b/src/mainboard/amd/olivehillplus/irq_tables.c index e18e47842a..530c132a05 100644 --- a/src/mainboard/amd/olivehillplus/irq_tables.c +++ b/src/mainboard/amd/olivehillplus/irq_tables.c @@ -14,7 +14,6 @@ */ #include -#include #include #include #include diff --git a/src/mainboard/amd/olivehillplus/mainboard.c b/src/mainboard/amd/olivehillplus/mainboard.c index 00ac1a4499..1367b03307 100644 --- a/src/mainboard/amd/olivehillplus/mainboard.c +++ b/src/mainboard/amd/olivehillplus/mainboard.c @@ -15,7 +15,6 @@ #include #include -#include #include #include #include diff --git a/src/mainboard/amd/olivehillplus/mptable.c b/src/mainboard/amd/olivehillplus/mptable.c index b04f5acb81..6c81d06cc5 100644 --- a/src/mainboard/amd/olivehillplus/mptable.c +++ b/src/mainboard/amd/olivehillplus/mptable.c @@ -14,7 +14,6 @@ */ #include -#include #include #include #include diff --git a/src/mainboard/amd/padmelon/bootblock/bootblock.c b/src/mainboard/amd/padmelon/bootblock/bootblock.c index 864928732c..9886b61b71 100644 --- a/src/mainboard/amd/padmelon/bootblock/bootblock.c +++ b/src/mainboard/amd/padmelon/bootblock/bootblock.c @@ -16,7 +16,6 @@ #include #include #include -#include #include #include #include diff --git a/src/mainboard/amd/parmer/acpi_tables.c b/src/mainboard/amd/parmer/acpi_tables.c index eba2d1da8b..fd59a3aade 100644 --- a/src/mainboard/amd/parmer/acpi_tables.c +++ b/src/mainboard/amd/parmer/acpi_tables.c @@ -15,7 +15,6 @@ #include #include -#include unsigned long acpi_fill_madt(unsigned long current) { diff --git a/src/mainboard/amd/parmer/irq_tables.c b/src/mainboard/amd/parmer/irq_tables.c index e18e47842a..530c132a05 100644 --- a/src/mainboard/amd/parmer/irq_tables.c +++ b/src/mainboard/amd/parmer/irq_tables.c @@ -14,7 +14,6 @@ */ #include -#include #include #include #include diff --git a/src/mainboard/amd/parmer/mptable.c b/src/mainboard/amd/parmer/mptable.c index ea1862495c..c2b9f98e68 100644 --- a/src/mainboard/amd/parmer/mptable.c +++ b/src/mainboard/amd/parmer/mptable.c @@ -14,7 +14,6 @@ */ #include -#include #include #include #include diff --git a/src/mainboard/amd/persimmon/acpi_tables.c b/src/mainboard/amd/persimmon/acpi_tables.c index 787c432041..97ea6492fb 100644 --- a/src/mainboard/amd/persimmon/acpi_tables.c +++ b/src/mainboard/amd/persimmon/acpi_tables.c @@ -15,7 +15,6 @@ #include #include -#include unsigned long acpi_fill_madt(unsigned long current) { diff --git a/src/mainboard/amd/persimmon/irq_tables.c b/src/mainboard/amd/persimmon/irq_tables.c index 9ebe58ae65..a066864abd 100644 --- a/src/mainboard/amd/persimmon/irq_tables.c +++ b/src/mainboard/amd/persimmon/irq_tables.c @@ -14,7 +14,6 @@ */ #include -#include #include #include #include diff --git a/src/mainboard/amd/persimmon/mptable.c b/src/mainboard/amd/persimmon/mptable.c index d9f550ea42..bc7a3ac38f 100644 --- a/src/mainboard/amd/persimmon/mptable.c +++ b/src/mainboard/amd/persimmon/mptable.c @@ -15,7 +15,6 @@ */ #include -#include #include #include #include diff --git a/src/mainboard/amd/south_station/acpi_tables.c b/src/mainboard/amd/south_station/acpi_tables.c index 787c432041..97ea6492fb 100644 --- a/src/mainboard/amd/south_station/acpi_tables.c +++ b/src/mainboard/amd/south_station/acpi_tables.c @@ -15,7 +15,6 @@ #include #include -#include unsigned long acpi_fill_madt(unsigned long current) { diff --git a/src/mainboard/amd/south_station/irq_tables.c b/src/mainboard/amd/south_station/irq_tables.c index 9ebe58ae65..a066864abd 100644 --- a/src/mainboard/amd/south_station/irq_tables.c +++ b/src/mainboard/amd/south_station/irq_tables.c @@ -14,7 +14,6 @@ */ #include -#include #include #include #include diff --git a/src/mainboard/amd/south_station/mptable.c b/src/mainboard/amd/south_station/mptable.c index 8052dc0d67..c38708e76b 100644 --- a/src/mainboard/amd/south_station/mptable.c +++ b/src/mainboard/amd/south_station/mptable.c @@ -14,7 +14,6 @@ */ #include -#include #include #include #include diff --git a/src/mainboard/amd/thatcher/acpi_tables.c b/src/mainboard/amd/thatcher/acpi_tables.c index eba2d1da8b..fd59a3aade 100644 --- a/src/mainboard/amd/thatcher/acpi_tables.c +++ b/src/mainboard/amd/thatcher/acpi_tables.c @@ -15,7 +15,6 @@ #include #include -#include unsigned long acpi_fill_madt(unsigned long current) { diff --git a/src/mainboard/amd/thatcher/irq_tables.c b/src/mainboard/amd/thatcher/irq_tables.c index e18e47842a..530c132a05 100644 --- a/src/mainboard/amd/thatcher/irq_tables.c +++ b/src/mainboard/amd/thatcher/irq_tables.c @@ -14,7 +14,6 @@ */ #include -#include #include #include #include diff --git a/src/mainboard/amd/thatcher/mptable.c b/src/mainboard/amd/thatcher/mptable.c index f7698bb16f..b23d036daf 100644 --- a/src/mainboard/amd/thatcher/mptable.c +++ b/src/mainboard/amd/thatcher/mptable.c @@ -14,7 +14,6 @@ */ #include -#include #include #include #include diff --git a/src/mainboard/amd/union_station/acpi_tables.c b/src/mainboard/amd/union_station/acpi_tables.c index 787c432041..97ea6492fb 100644 --- a/src/mainboard/amd/union_station/acpi_tables.c +++ b/src/mainboard/amd/union_station/acpi_tables.c @@ -15,7 +15,6 @@ #include #include -#include unsigned long acpi_fill_madt(unsigned long current) { diff --git a/src/mainboard/amd/union_station/irq_tables.c b/src/mainboard/amd/union_station/irq_tables.c index 9ebe58ae65..a066864abd 100644 --- a/src/mainboard/amd/union_station/irq_tables.c +++ b/src/mainboard/amd/union_station/irq_tables.c @@ -14,7 +14,6 @@ */ #include -#include #include #include #include diff --git a/src/mainboard/amd/union_station/mptable.c b/src/mainboard/amd/union_station/mptable.c index 8052dc0d67..c38708e76b 100644 --- a/src/mainboard/amd/union_station/mptable.c +++ b/src/mainboard/amd/union_station/mptable.c @@ -14,7 +14,6 @@ */ #include -#include #include #include #include diff --git a/src/mainboard/aopen/dxplplusu/acpi_tables.c b/src/mainboard/aopen/dxplplusu/acpi_tables.c index 70bfa27978..84bb64e993 100644 --- a/src/mainboard/aopen/dxplplusu/acpi_tables.c +++ b/src/mainboard/aopen/dxplplusu/acpi_tables.c @@ -19,7 +19,6 @@ */ #include -#include #include #define IOAPIC_ICH4 2 diff --git a/src/mainboard/aopen/dxplplusu/fadt.c b/src/mainboard/aopen/dxplplusu/fadt.c index adf94e95eb..a716a02e9b 100644 --- a/src/mainboard/aopen/dxplplusu/fadt.c +++ b/src/mainboard/aopen/dxplplusu/fadt.c @@ -14,7 +14,6 @@ */ #include -#include #include #include #include diff --git a/src/mainboard/apple/macbook21/mptable.c b/src/mainboard/apple/macbook21/mptable.c index 61296134a8..021115a85f 100644 --- a/src/mainboard/apple/macbook21/mptable.c +++ b/src/mainboard/apple/macbook21/mptable.c @@ -15,7 +15,6 @@ */ #include -#include #include #include #include diff --git a/src/mainboard/asrock/e350m1/acpi_tables.c b/src/mainboard/asrock/e350m1/acpi_tables.c index 787c432041..97ea6492fb 100644 --- a/src/mainboard/asrock/e350m1/acpi_tables.c +++ b/src/mainboard/asrock/e350m1/acpi_tables.c @@ -15,7 +15,6 @@ #include #include -#include unsigned long acpi_fill_madt(unsigned long current) { diff --git a/src/mainboard/asrock/e350m1/irq_tables.c b/src/mainboard/asrock/e350m1/irq_tables.c index 0bcb041558..1d1e81f05e 100644 --- a/src/mainboard/asrock/e350m1/irq_tables.c +++ b/src/mainboard/asrock/e350m1/irq_tables.c @@ -14,7 +14,6 @@ */ #include -#include #include #include #include diff --git a/src/mainboard/asrock/e350m1/mptable.c b/src/mainboard/asrock/e350m1/mptable.c index 9c62712aa2..6093e8f082 100644 --- a/src/mainboard/asrock/e350m1/mptable.c +++ b/src/mainboard/asrock/e350m1/mptable.c @@ -17,7 +17,6 @@ #include #include #include -#include #include #include diff --git a/src/mainboard/asrock/imb-a180/acpi_tables.c b/src/mainboard/asrock/imb-a180/acpi_tables.c index 08f6076e7c..20509e9d31 100644 --- a/src/mainboard/asrock/imb-a180/acpi_tables.c +++ b/src/mainboard/asrock/imb-a180/acpi_tables.c @@ -15,7 +15,6 @@ #include #include -#include unsigned long acpi_fill_madt(unsigned long current) { diff --git a/src/mainboard/asrock/imb-a180/irq_tables.c b/src/mainboard/asrock/imb-a180/irq_tables.c index be71dd491f..181908a8ad 100644 --- a/src/mainboard/asrock/imb-a180/irq_tables.c +++ b/src/mainboard/asrock/imb-a180/irq_tables.c @@ -14,7 +14,6 @@ */ #include -#include #include #include #include diff --git a/src/mainboard/asrock/imb-a180/mptable.c b/src/mainboard/asrock/imb-a180/mptable.c index fd4dff7f08..37080ea320 100644 --- a/src/mainboard/asrock/imb-a180/mptable.c +++ b/src/mainboard/asrock/imb-a180/mptable.c @@ -14,7 +14,6 @@ */ #include -#include #include #include #include diff --git a/src/mainboard/asus/am1i-a/acpi_tables.c b/src/mainboard/asus/am1i-a/acpi_tables.c index 411ebe7436..447c89573e 100644 --- a/src/mainboard/asus/am1i-a/acpi_tables.c +++ b/src/mainboard/asus/am1i-a/acpi_tables.c @@ -15,7 +15,6 @@ #include #include -#include unsigned long acpi_fill_madt(unsigned long current) { diff --git a/src/mainboard/asus/am1i-a/mptable.c b/src/mainboard/asus/am1i-a/mptable.c index d97e6ac7f0..9efcab35b9 100644 --- a/src/mainboard/asus/am1i-a/mptable.c +++ b/src/mainboard/asus/am1i-a/mptable.c @@ -15,7 +15,6 @@ */ #include -#include #include #include #include diff --git a/src/mainboard/asus/f2a85-m/acpi_tables.c b/src/mainboard/asus/f2a85-m/acpi_tables.c index eba2d1da8b..fd59a3aade 100644 --- a/src/mainboard/asus/f2a85-m/acpi_tables.c +++ b/src/mainboard/asus/f2a85-m/acpi_tables.c @@ -15,7 +15,6 @@ #include #include -#include unsigned long acpi_fill_madt(unsigned long current) { diff --git a/src/mainboard/asus/f2a85-m/mptable.c b/src/mainboard/asus/f2a85-m/mptable.c index 8bfe4d535a..303f3bf5c4 100644 --- a/src/mainboard/asus/f2a85-m/mptable.c +++ b/src/mainboard/asus/f2a85-m/mptable.c @@ -17,7 +17,6 @@ #include #include #include -#include #include #include #include diff --git a/src/mainboard/asus/p2b-d/mptable.c b/src/mainboard/asus/p2b-d/mptable.c index fde12814ab..8f643d1e99 100644 --- a/src/mainboard/asus/p2b-d/mptable.c +++ b/src/mainboard/asus/p2b-d/mptable.c @@ -16,7 +16,6 @@ #include #include -#include #include static void *smp_write_config_table(void *v) diff --git a/src/mainboard/asus/p2b-ds/mptable.c b/src/mainboard/asus/p2b-ds/mptable.c index 4e085b1327..b4925118a3 100644 --- a/src/mainboard/asus/p2b-ds/mptable.c +++ b/src/mainboard/asus/p2b-ds/mptable.c @@ -16,7 +16,6 @@ #include #include -#include #include static void *smp_write_config_table(void *v) diff --git a/src/mainboard/bap/ode_e20XX/acpi_tables.c b/src/mainboard/bap/ode_e20XX/acpi_tables.c index 08f6076e7c..20509e9d31 100644 --- a/src/mainboard/bap/ode_e20XX/acpi_tables.c +++ b/src/mainboard/bap/ode_e20XX/acpi_tables.c @@ -15,7 +15,6 @@ #include #include -#include unsigned long acpi_fill_madt(unsigned long current) { diff --git a/src/mainboard/bap/ode_e20XX/irq_tables.c b/src/mainboard/bap/ode_e20XX/irq_tables.c index e18e47842a..530c132a05 100644 --- a/src/mainboard/bap/ode_e20XX/irq_tables.c +++ b/src/mainboard/bap/ode_e20XX/irq_tables.c @@ -14,7 +14,6 @@ */ #include -#include #include #include #include diff --git a/src/mainboard/bap/ode_e20XX/mptable.c b/src/mainboard/bap/ode_e20XX/mptable.c index ea9f95947d..e4edc5fe7a 100644 --- a/src/mainboard/bap/ode_e20XX/mptable.c +++ b/src/mainboard/bap/ode_e20XX/mptable.c @@ -14,7 +14,6 @@ */ #include -#include #include #include #include diff --git a/src/mainboard/bap/ode_e21XX/acpi_tables.c b/src/mainboard/bap/ode_e21XX/acpi_tables.c index 08f6076e7c..20509e9d31 100644 --- a/src/mainboard/bap/ode_e21XX/acpi_tables.c +++ b/src/mainboard/bap/ode_e21XX/acpi_tables.c @@ -15,7 +15,6 @@ #include #include -#include unsigned long acpi_fill_madt(unsigned long current) { diff --git a/src/mainboard/bap/ode_e21XX/irq_tables.c b/src/mainboard/bap/ode_e21XX/irq_tables.c index f1dbc087fe..413ccf8718 100644 --- a/src/mainboard/bap/ode_e21XX/irq_tables.c +++ b/src/mainboard/bap/ode_e21XX/irq_tables.c @@ -14,7 +14,6 @@ */ #include -#include #include #include #include diff --git a/src/mainboard/bap/ode_e21XX/mainboard.c b/src/mainboard/bap/ode_e21XX/mainboard.c index 00ac1a4499..1367b03307 100644 --- a/src/mainboard/bap/ode_e21XX/mainboard.c +++ b/src/mainboard/bap/ode_e21XX/mainboard.c @@ -15,7 +15,6 @@ #include #include -#include #include #include #include diff --git a/src/mainboard/bap/ode_e21XX/mptable.c b/src/mainboard/bap/ode_e21XX/mptable.c index b04f5acb81..6c81d06cc5 100644 --- a/src/mainboard/bap/ode_e21XX/mptable.c +++ b/src/mainboard/bap/ode_e21XX/mptable.c @@ -14,7 +14,6 @@ */ #include -#include #include #include #include diff --git a/src/mainboard/biostar/a68n_5200/acpi_tables.c b/src/mainboard/biostar/a68n_5200/acpi_tables.c index 08f6076e7c..20509e9d31 100644 --- a/src/mainboard/biostar/a68n_5200/acpi_tables.c +++ b/src/mainboard/biostar/a68n_5200/acpi_tables.c @@ -15,7 +15,6 @@ #include #include -#include unsigned long acpi_fill_madt(unsigned long current) { diff --git a/src/mainboard/biostar/a68n_5200/irq_tables.c b/src/mainboard/biostar/a68n_5200/irq_tables.c index e18e47842a..530c132a05 100644 --- a/src/mainboard/biostar/a68n_5200/irq_tables.c +++ b/src/mainboard/biostar/a68n_5200/irq_tables.c @@ -14,7 +14,6 @@ */ #include -#include #include #include #include diff --git a/src/mainboard/biostar/a68n_5200/mptable.c b/src/mainboard/biostar/a68n_5200/mptable.c index 3054effc19..52374f1529 100644 --- a/src/mainboard/biostar/a68n_5200/mptable.c +++ b/src/mainboard/biostar/a68n_5200/mptable.c @@ -14,7 +14,6 @@ */ #include -#include #include #include #include diff --git a/src/mainboard/biostar/am1ml/acpi_tables.c b/src/mainboard/biostar/am1ml/acpi_tables.c index 411ebe7436..447c89573e 100644 --- a/src/mainboard/biostar/am1ml/acpi_tables.c +++ b/src/mainboard/biostar/am1ml/acpi_tables.c @@ -15,7 +15,6 @@ #include #include -#include unsigned long acpi_fill_madt(unsigned long current) { diff --git a/src/mainboard/biostar/am1ml/mptable.c b/src/mainboard/biostar/am1ml/mptable.c index 4d93361cba..659a141f95 100644 --- a/src/mainboard/biostar/am1ml/mptable.c +++ b/src/mainboard/biostar/am1ml/mptable.c @@ -14,7 +14,6 @@ */ #include -#include #include #include #include diff --git a/src/mainboard/elmex/pcm205400/acpi_tables.c b/src/mainboard/elmex/pcm205400/acpi_tables.c index 787c432041..97ea6492fb 100644 --- a/src/mainboard/elmex/pcm205400/acpi_tables.c +++ b/src/mainboard/elmex/pcm205400/acpi_tables.c @@ -15,7 +15,6 @@ #include #include -#include unsigned long acpi_fill_madt(unsigned long current) { diff --git a/src/mainboard/elmex/pcm205400/irq_tables.c b/src/mainboard/elmex/pcm205400/irq_tables.c index 591cabbaa1..804f52dcc5 100644 --- a/src/mainboard/elmex/pcm205400/irq_tables.c +++ b/src/mainboard/elmex/pcm205400/irq_tables.c @@ -15,7 +15,6 @@ #include -#include #include #include #include diff --git a/src/mainboard/elmex/pcm205400/mptable.c b/src/mainboard/elmex/pcm205400/mptable.c index d9f550ea42..bc7a3ac38f 100644 --- a/src/mainboard/elmex/pcm205400/mptable.c +++ b/src/mainboard/elmex/pcm205400/mptable.c @@ -15,7 +15,6 @@ */ #include -#include #include #include #include diff --git a/src/mainboard/emulation/qemu-i440fx/northbridge.c b/src/mainboard/emulation/qemu-i440fx/northbridge.c index 1c27a0fde8..b30723dd74 100644 --- a/src/mainboard/emulation/qemu-i440fx/northbridge.c +++ b/src/mainboard/emulation/qemu-i440fx/northbridge.c @@ -20,7 +20,6 @@ #include #include #include -#include #include #include #include diff --git a/src/mainboard/emulation/qemu-q35/acpi_tables.c b/src/mainboard/emulation/qemu-q35/acpi_tables.c index a609b5df38..5c48e956ce 100644 --- a/src/mainboard/emulation/qemu-q35/acpi_tables.c +++ b/src/mainboard/emulation/qemu-q35/acpi_tables.c @@ -19,7 +19,6 @@ #include #include #include -#include #include #include diff --git a/src/mainboard/getac/p470/acpi_tables.c b/src/mainboard/getac/p470/acpi_tables.c index 59c28768d5..3372ace792 100644 --- a/src/mainboard/getac/p470/acpi_tables.c +++ b/src/mainboard/getac/p470/acpi_tables.c @@ -20,7 +20,6 @@ #include #include #include -#include #include #include "mainboard.h" diff --git a/src/mainboard/getac/p470/mptable.c b/src/mainboard/getac/p470/mptable.c index 86006e1363..795ac08ff0 100644 --- a/src/mainboard/getac/p470/mptable.c +++ b/src/mainboard/getac/p470/mptable.c @@ -15,7 +15,6 @@ */ #include -#include #include #include #include diff --git a/src/mainboard/gizmosphere/gizmo/acpi_tables.c b/src/mainboard/gizmosphere/gizmo/acpi_tables.c index 2154cd842f..364c915efc 100644 --- a/src/mainboard/gizmosphere/gizmo/acpi_tables.c +++ b/src/mainboard/gizmosphere/gizmo/acpi_tables.c @@ -16,7 +16,6 @@ #include #include -#include unsigned long acpi_fill_madt(unsigned long current) { diff --git a/src/mainboard/gizmosphere/gizmo/irq_tables.c b/src/mainboard/gizmosphere/gizmo/irq_tables.c index bf2379c29e..9d74dc8942 100644 --- a/src/mainboard/gizmosphere/gizmo/irq_tables.c +++ b/src/mainboard/gizmosphere/gizmo/irq_tables.c @@ -15,7 +15,6 @@ */ #include -#include #include #include #include diff --git a/src/mainboard/gizmosphere/gizmo/mptable.c b/src/mainboard/gizmosphere/gizmo/mptable.c index d44e27613e..dca5f3c273 100644 --- a/src/mainboard/gizmosphere/gizmo/mptable.c +++ b/src/mainboard/gizmosphere/gizmo/mptable.c @@ -15,7 +15,6 @@ */ #include -#include #include #include #include diff --git a/src/mainboard/gizmosphere/gizmo2/acpi_tables.c b/src/mainboard/gizmosphere/gizmo2/acpi_tables.c index 08f6076e7c..20509e9d31 100644 --- a/src/mainboard/gizmosphere/gizmo2/acpi_tables.c +++ b/src/mainboard/gizmosphere/gizmo2/acpi_tables.c @@ -15,7 +15,6 @@ #include #include -#include unsigned long acpi_fill_madt(unsigned long current) { diff --git a/src/mainboard/gizmosphere/gizmo2/irq_tables.c b/src/mainboard/gizmosphere/gizmo2/irq_tables.c index e18e47842a..530c132a05 100644 --- a/src/mainboard/gizmosphere/gizmo2/irq_tables.c +++ b/src/mainboard/gizmosphere/gizmo2/irq_tables.c @@ -14,7 +14,6 @@ */ #include -#include #include #include #include diff --git a/src/mainboard/gizmosphere/gizmo2/mptable.c b/src/mainboard/gizmosphere/gizmo2/mptable.c index ea9f95947d..e4edc5fe7a 100644 --- a/src/mainboard/gizmosphere/gizmo2/mptable.c +++ b/src/mainboard/gizmosphere/gizmo2/mptable.c @@ -14,7 +14,6 @@ */ #include -#include #include #include #include diff --git a/src/mainboard/google/auron/variants/buddy/variant.c b/src/mainboard/google/auron/variants/buddy/variant.c index dcda04dbb6..58fee1ef18 100644 --- a/src/mainboard/google/auron/variants/buddy/variant.c +++ b/src/mainboard/google/auron/variants/buddy/variant.c @@ -18,7 +18,6 @@ #include #include #include -#include #include #include #include diff --git a/src/mainboard/google/beltino/acpi_tables.c b/src/mainboard/google/beltino/acpi_tables.c index 2b2acbad61..a04a9507ff 100644 --- a/src/mainboard/google/beltino/acpi_tables.c +++ b/src/mainboard/google/beltino/acpi_tables.c @@ -17,7 +17,6 @@ #include #include #include -#include #include #include #include diff --git a/src/mainboard/google/beltino/chromeos.c b/src/mainboard/google/beltino/chromeos.c index 1039707ec3..8940d360e3 100644 --- a/src/mainboard/google/beltino/chromeos.c +++ b/src/mainboard/google/beltino/chromeos.c @@ -17,7 +17,6 @@ #include #include #include -#include #include #include #include diff --git a/src/mainboard/google/beltino/lan.c b/src/mainboard/google/beltino/lan.c index 090f280a83..1c38e45e43 100644 --- a/src/mainboard/google/beltino/lan.c +++ b/src/mainboard/google/beltino/lan.c @@ -19,7 +19,6 @@ #include #include #include -#include #include #include #include "onboard.h" diff --git a/src/mainboard/google/butterfly/chromeos.c b/src/mainboard/google/butterfly/chromeos.c index ea4b8ac04f..63e582e48f 100644 --- a/src/mainboard/google/butterfly/chromeos.c +++ b/src/mainboard/google/butterfly/chromeos.c @@ -17,7 +17,6 @@ #include #include #include -#include #include #include diff --git a/src/mainboard/google/butterfly/mainboard.c b/src/mainboard/google/butterfly/mainboard.c index b52351baa4..eb4d15bea7 100644 --- a/src/mainboard/google/butterfly/mainboard.c +++ b/src/mainboard/google/butterfly/mainboard.c @@ -27,7 +27,6 @@ #include "ec.h" #include #include -#include #include #include diff --git a/src/mainboard/google/jecht/acpi_tables.c b/src/mainboard/google/jecht/acpi_tables.c index 879ff93d97..445f03771c 100644 --- a/src/mainboard/google/jecht/acpi_tables.c +++ b/src/mainboard/google/jecht/acpi_tables.c @@ -18,7 +18,6 @@ #include #include #include -#include #include #include #include diff --git a/src/mainboard/google/jecht/chromeos.c b/src/mainboard/google/jecht/chromeos.c index f2db756e5e..e8a9d1abd1 100644 --- a/src/mainboard/google/jecht/chromeos.c +++ b/src/mainboard/google/jecht/chromeos.c @@ -16,7 +16,6 @@ #include #include #include -#include #include #include #include diff --git a/src/mainboard/google/jecht/lan.c b/src/mainboard/google/jecht/lan.c index f733bca112..bd08b0916b 100644 --- a/src/mainboard/google/jecht/lan.c +++ b/src/mainboard/google/jecht/lan.c @@ -20,7 +20,6 @@ #include #include #include -#include #include #include "onboard.h" diff --git a/src/mainboard/google/kahlee/irq_tables.c b/src/mainboard/google/kahlee/irq_tables.c index 31cfbc199d..b134c6bac0 100644 --- a/src/mainboard/google/kahlee/irq_tables.c +++ b/src/mainboard/google/kahlee/irq_tables.c @@ -14,7 +14,6 @@ */ #include -#include #include #include #include diff --git a/src/mainboard/google/kahlee/mptable.c b/src/mainboard/google/kahlee/mptable.c index fa60d35605..5bb70e9449 100644 --- a/src/mainboard/google/kahlee/mptable.c +++ b/src/mainboard/google/kahlee/mptable.c @@ -14,7 +14,6 @@ */ #include -#include #include #include #include diff --git a/src/mainboard/google/kahlee/variants/baseboard/mainboard.c b/src/mainboard/google/kahlee/variants/baseboard/mainboard.c index 30fcc8c2a2..69b9b40f8d 100644 --- a/src/mainboard/google/kahlee/variants/baseboard/mainboard.c +++ b/src/mainboard/google/kahlee/variants/baseboard/mainboard.c @@ -21,7 +21,6 @@ #include #include #include -#include #include #include diff --git a/src/mainboard/google/link/early_init.c b/src/mainboard/google/link/early_init.c index 19cd295948..c234e5b848 100644 --- a/src/mainboard/google/link/early_init.c +++ b/src/mainboard/google/link/early_init.c @@ -17,7 +17,6 @@ #include #include #include -#include #include #include #include diff --git a/src/mainboard/google/link/mainboard.c b/src/mainboard/google/link/mainboard.c index 21274b345f..5a812e83e9 100644 --- a/src/mainboard/google/link/mainboard.c +++ b/src/mainboard/google/link/mainboard.c @@ -29,7 +29,6 @@ #include #include #include -#include #include #include diff --git a/src/mainboard/google/parrot/acpi_tables.c b/src/mainboard/google/parrot/acpi_tables.c index 93d77daf03..e92734da1a 100644 --- a/src/mainboard/google/parrot/acpi_tables.c +++ b/src/mainboard/google/parrot/acpi_tables.c @@ -17,7 +17,6 @@ #include #include #include -#include #include #include #include "ec.h" diff --git a/src/mainboard/google/parrot/chromeos.c b/src/mainboard/google/parrot/chromeos.c index 4587a127fd..ae8da676b3 100644 --- a/src/mainboard/google/parrot/chromeos.c +++ b/src/mainboard/google/parrot/chromeos.c @@ -18,7 +18,6 @@ #include #include #include -#include #include #include diff --git a/src/mainboard/google/parrot/mainboard.c b/src/mainboard/google/parrot/mainboard.c index 5f47c05fa2..873776beff 100644 --- a/src/mainboard/google/parrot/mainboard.c +++ b/src/mainboard/google/parrot/mainboard.c @@ -23,7 +23,6 @@ #include "ec.h" #include #include -#include #include #include diff --git a/src/mainboard/google/poppy/variants/nautilus/mainboard.c b/src/mainboard/google/poppy/variants/nautilus/mainboard.c index b78ec82aeb..84855078cf 100644 --- a/src/mainboard/google/poppy/variants/nautilus/mainboard.c +++ b/src/mainboard/google/poppy/variants/nautilus/mainboard.c @@ -17,7 +17,6 @@ #include #include #include -#include #include #include #include diff --git a/src/mainboard/google/rambi/acpi_tables.c b/src/mainboard/google/rambi/acpi_tables.c index 8e6db19a4d..867b2203a9 100644 --- a/src/mainboard/google/rambi/acpi_tables.c +++ b/src/mainboard/google/rambi/acpi_tables.c @@ -18,7 +18,6 @@ #include #include #include -#include #include #include #include diff --git a/src/mainboard/google/rambi/variants/ninja/lan.c b/src/mainboard/google/rambi/variants/ninja/lan.c index edf2a62bad..5b220e0efa 100644 --- a/src/mainboard/google/rambi/variants/ninja/lan.c +++ b/src/mainboard/google/rambi/variants/ninja/lan.c @@ -19,7 +19,6 @@ #include #include #include -#include #include #include diff --git a/src/mainboard/google/rambi/variants/sumo/lan.c b/src/mainboard/google/rambi/variants/sumo/lan.c index 9ed2b04967..d6cd580588 100644 --- a/src/mainboard/google/rambi/variants/sumo/lan.c +++ b/src/mainboard/google/rambi/variants/sumo/lan.c @@ -19,7 +19,6 @@ #include #include #include -#include #include #include diff --git a/src/mainboard/google/slippy/acpi_tables.c b/src/mainboard/google/slippy/acpi_tables.c index 0b303ae6dd..5838823ddd 100644 --- a/src/mainboard/google/slippy/acpi_tables.c +++ b/src/mainboard/google/slippy/acpi_tables.c @@ -17,7 +17,6 @@ #include #include #include -#include #include #include #include diff --git a/src/mainboard/google/stout/acpi_tables.c b/src/mainboard/google/stout/acpi_tables.c index 46aadaf75b..597cb8fb76 100644 --- a/src/mainboard/google/stout/acpi_tables.c +++ b/src/mainboard/google/stout/acpi_tables.c @@ -17,7 +17,6 @@ #include #include #include -#include #include #include #include diff --git a/src/mainboard/google/stout/chromeos.c b/src/mainboard/google/stout/chromeos.c index dc3f3abb45..fbb81907ce 100644 --- a/src/mainboard/google/stout/chromeos.c +++ b/src/mainboard/google/stout/chromeos.c @@ -18,7 +18,6 @@ #include #include #include -#include #include #include diff --git a/src/mainboard/google/stout/ec.c b/src/mainboard/google/stout/ec.c index 0ea32bcfc3..3e91282f10 100644 --- a/src/mainboard/google/stout/ec.c +++ b/src/mainboard/google/stout/ec.c @@ -20,7 +20,6 @@ #include #include #include -#include #include #include #include diff --git a/src/mainboard/google/stout/mainboard.c b/src/mainboard/google/stout/mainboard.c index 2d4086a230..dcd8fc656a 100644 --- a/src/mainboard/google/stout/mainboard.c +++ b/src/mainboard/google/stout/mainboard.c @@ -20,7 +20,6 @@ #include #include #include -#include #include #include diff --git a/src/mainboard/hp/abm/acpi_tables.c b/src/mainboard/hp/abm/acpi_tables.c index 08f6076e7c..20509e9d31 100644 --- a/src/mainboard/hp/abm/acpi_tables.c +++ b/src/mainboard/hp/abm/acpi_tables.c @@ -15,7 +15,6 @@ #include #include -#include unsigned long acpi_fill_madt(unsigned long current) { diff --git a/src/mainboard/hp/abm/irq_tables.c b/src/mainboard/hp/abm/irq_tables.c index e18e47842a..530c132a05 100644 --- a/src/mainboard/hp/abm/irq_tables.c +++ b/src/mainboard/hp/abm/irq_tables.c @@ -14,7 +14,6 @@ */ #include -#include #include #include #include diff --git a/src/mainboard/hp/abm/mptable.c b/src/mainboard/hp/abm/mptable.c index 3054effc19..52374f1529 100644 --- a/src/mainboard/hp/abm/mptable.c +++ b/src/mainboard/hp/abm/mptable.c @@ -14,7 +14,6 @@ */ #include -#include #include #include #include diff --git a/src/mainboard/hp/pavilion_m6_1035dx/acpi_tables.c b/src/mainboard/hp/pavilion_m6_1035dx/acpi_tables.c index eba2d1da8b..fd59a3aade 100644 --- a/src/mainboard/hp/pavilion_m6_1035dx/acpi_tables.c +++ b/src/mainboard/hp/pavilion_m6_1035dx/acpi_tables.c @@ -15,7 +15,6 @@ #include #include -#include unsigned long acpi_fill_madt(unsigned long current) { diff --git a/src/mainboard/hp/pavilion_m6_1035dx/mptable.c b/src/mainboard/hp/pavilion_m6_1035dx/mptable.c index 0d44397be5..f3c2f0a572 100644 --- a/src/mainboard/hp/pavilion_m6_1035dx/mptable.c +++ b/src/mainboard/hp/pavilion_m6_1035dx/mptable.c @@ -17,7 +17,6 @@ #include #include #include -#include #include #include #include diff --git a/src/mainboard/ibase/mb899/mptable.c b/src/mainboard/ibase/mb899/mptable.c index 14f93eca51..b24d8bf3c6 100644 --- a/src/mainboard/ibase/mb899/mptable.c +++ b/src/mainboard/ibase/mb899/mptable.c @@ -14,7 +14,6 @@ */ #include -#include #include #include #include diff --git a/src/mainboard/intel/baskingridge/acpi_tables.c b/src/mainboard/intel/baskingridge/acpi_tables.c index 497b10b3ee..60f9c463bc 100644 --- a/src/mainboard/intel/baskingridge/acpi_tables.c +++ b/src/mainboard/intel/baskingridge/acpi_tables.c @@ -17,7 +17,6 @@ #include #include #include -#include #include #include #include diff --git a/src/mainboard/intel/baskingridge/chromeos.c b/src/mainboard/intel/baskingridge/chromeos.c index 74eb788595..cf89f0da1e 100644 --- a/src/mainboard/intel/baskingridge/chromeos.c +++ b/src/mainboard/intel/baskingridge/chromeos.c @@ -16,7 +16,6 @@ #include #include #include -#include #include #include #include diff --git a/src/mainboard/intel/d510mo/mainboard.c b/src/mainboard/intel/d510mo/mainboard.c index f90ee89cea..3263f9a065 100644 --- a/src/mainboard/intel/d510mo/mainboard.c +++ b/src/mainboard/intel/d510mo/mainboard.c @@ -14,7 +14,6 @@ */ #include -#include #include static void mainboard_enable(struct device *dev) diff --git a/src/mainboard/intel/d945gclf/mptable.c b/src/mainboard/intel/d945gclf/mptable.c index c58cbf5999..89df425152 100644 --- a/src/mainboard/intel/d945gclf/mptable.c +++ b/src/mainboard/intel/d945gclf/mptable.c @@ -14,7 +14,6 @@ */ #include -#include #include #include #include diff --git a/src/mainboard/intel/emeraldlake2/acpi_tables.c b/src/mainboard/intel/emeraldlake2/acpi_tables.c index 74edc385c1..9d15eb6548 100644 --- a/src/mainboard/intel/emeraldlake2/acpi_tables.c +++ b/src/mainboard/intel/emeraldlake2/acpi_tables.c @@ -17,7 +17,6 @@ #include #include #include -#include #include #include diff --git a/src/mainboard/intel/emeraldlake2/chromeos.c b/src/mainboard/intel/emeraldlake2/chromeos.c index 470688fc98..4b52a2c794 100644 --- a/src/mainboard/intel/emeraldlake2/chromeos.c +++ b/src/mainboard/intel/emeraldlake2/chromeos.c @@ -16,7 +16,6 @@ #include #include #include -#include #include #include #include diff --git a/src/mainboard/intel/harcuvar/acpi_tables.c b/src/mainboard/intel/harcuvar/acpi_tables.c index 43818eebe4..1f92419a75 100644 --- a/src/mainboard/intel/harcuvar/acpi_tables.c +++ b/src/mainboard/intel/harcuvar/acpi_tables.c @@ -19,7 +19,6 @@ #include #include #include -#include #include #include diff --git a/src/mainboard/intel/kblrvp/chromeos.c b/src/mainboard/intel/kblrvp/chromeos.c index 29f05c9ec3..9db46744bc 100644 --- a/src/mainboard/intel/kblrvp/chromeos.c +++ b/src/mainboard/intel/kblrvp/chromeos.c @@ -16,7 +16,6 @@ #include #include -#include #include #include #include diff --git a/src/mainboard/intel/strago/acpi_tables.c b/src/mainboard/intel/strago/acpi_tables.c index 38ca9ff8a2..518e0aa41c 100644 --- a/src/mainboard/intel/strago/acpi_tables.c +++ b/src/mainboard/intel/strago/acpi_tables.c @@ -18,7 +18,6 @@ #include #include #include -#include #include #include #include diff --git a/src/mainboard/intel/wtm2/acpi_tables.c b/src/mainboard/intel/wtm2/acpi_tables.c index c94c7bff55..8ceea46e07 100644 --- a/src/mainboard/intel/wtm2/acpi_tables.c +++ b/src/mainboard/intel/wtm2/acpi_tables.c @@ -18,7 +18,6 @@ #include #include #include -#include #include #include #include "thermal.h" diff --git a/src/mainboard/intel/wtm2/chromeos.c b/src/mainboard/intel/wtm2/chromeos.c index 556677acb6..95664f1d42 100644 --- a/src/mainboard/intel/wtm2/chromeos.c +++ b/src/mainboard/intel/wtm2/chromeos.c @@ -16,7 +16,6 @@ #include #include #include -#include #include #include diff --git a/src/mainboard/jetway/nf81-t56n-lf/acpi_tables.c b/src/mainboard/jetway/nf81-t56n-lf/acpi_tables.c index 787c432041..97ea6492fb 100644 --- a/src/mainboard/jetway/nf81-t56n-lf/acpi_tables.c +++ b/src/mainboard/jetway/nf81-t56n-lf/acpi_tables.c @@ -15,7 +15,6 @@ #include #include -#include unsigned long acpi_fill_madt(unsigned long current) { diff --git a/src/mainboard/jetway/nf81-t56n-lf/mptable.c b/src/mainboard/jetway/nf81-t56n-lf/mptable.c index 8fbdc58a77..9a983b41f9 100644 --- a/src/mainboard/jetway/nf81-t56n-lf/mptable.c +++ b/src/mainboard/jetway/nf81-t56n-lf/mptable.c @@ -17,7 +17,6 @@ #include #include -#include #include #include #include diff --git a/src/mainboard/kontron/986lcd-m/mptable.c b/src/mainboard/kontron/986lcd-m/mptable.c index 1b5d45efb3..a5018f2233 100644 --- a/src/mainboard/kontron/986lcd-m/mptable.c +++ b/src/mainboard/kontron/986lcd-m/mptable.c @@ -14,7 +14,6 @@ */ #include -#include #include #include #include diff --git a/src/mainboard/lenovo/g505s/acpi_tables.c b/src/mainboard/lenovo/g505s/acpi_tables.c index eba2d1da8b..fd59a3aade 100644 --- a/src/mainboard/lenovo/g505s/acpi_tables.c +++ b/src/mainboard/lenovo/g505s/acpi_tables.c @@ -15,7 +15,6 @@ #include #include -#include unsigned long acpi_fill_madt(unsigned long current) { diff --git a/src/mainboard/lenovo/g505s/mptable.c b/src/mainboard/lenovo/g505s/mptable.c index 0d44397be5..f3c2f0a572 100644 --- a/src/mainboard/lenovo/g505s/mptable.c +++ b/src/mainboard/lenovo/g505s/mptable.c @@ -17,7 +17,6 @@ #include #include #include -#include #include #include #include diff --git a/src/mainboard/lenovo/t400/acpi_tables.c b/src/mainboard/lenovo/t400/acpi_tables.c index 8fb9056c51..953a2b84bf 100644 --- a/src/mainboard/lenovo/t400/acpi_tables.c +++ b/src/mainboard/lenovo/t400/acpi_tables.c @@ -19,7 +19,6 @@ #include #include #include -#include #include #include "thermal.h" diff --git a/src/mainboard/lenovo/t400/dock.c b/src/mainboard/lenovo/t400/dock.c index ccd6dcd5b8..2eb9903bb7 100644 --- a/src/mainboard/lenovo/t400/dock.c +++ b/src/mainboard/lenovo/t400/dock.c @@ -20,7 +20,6 @@ #include #include #include -#include #include #include #include "dock.h" diff --git a/src/mainboard/lenovo/t400/fadt.c b/src/mainboard/lenovo/t400/fadt.c index e335787100..9f4ebf6fe5 100644 --- a/src/mainboard/lenovo/t400/fadt.c +++ b/src/mainboard/lenovo/t400/fadt.c @@ -15,7 +15,6 @@ */ #include -#include #include #include #include diff --git a/src/mainboard/lenovo/t420/early_init.c b/src/mainboard/lenovo/t420/early_init.c index 8afd150129..2e39885b6b 100644 --- a/src/mainboard/lenovo/t420/early_init.c +++ b/src/mainboard/lenovo/t420/early_init.c @@ -21,7 +21,6 @@ #include #include #include -#include static void hybrid_graphics_init(void) { diff --git a/src/mainboard/lenovo/t420s/early_init.c b/src/mainboard/lenovo/t420s/early_init.c index e2cdebfe35..276c66e18e 100644 --- a/src/mainboard/lenovo/t420s/early_init.c +++ b/src/mainboard/lenovo/t420s/early_init.c @@ -21,7 +21,6 @@ #include #include #include -#include static void hybrid_graphics_init(void) { diff --git a/src/mainboard/lenovo/t430/early_init.c b/src/mainboard/lenovo/t430/early_init.c index 74c8b60883..27258a3a57 100644 --- a/src/mainboard/lenovo/t430/early_init.c +++ b/src/mainboard/lenovo/t430/early_init.c @@ -21,7 +21,6 @@ #include #include #include -#include static void hybrid_graphics_init(void) { diff --git a/src/mainboard/lenovo/t520/early_init.c b/src/mainboard/lenovo/t520/early_init.c index ad8e1520bb..8e5bf2ae44 100644 --- a/src/mainboard/lenovo/t520/early_init.c +++ b/src/mainboard/lenovo/t520/early_init.c @@ -23,7 +23,6 @@ #include #include #include -#include static void hybrid_graphics_init(void) { diff --git a/src/mainboard/lenovo/t530/early_init.c b/src/mainboard/lenovo/t530/early_init.c index aeb27a6d28..c6ff7e7038 100644 --- a/src/mainboard/lenovo/t530/early_init.c +++ b/src/mainboard/lenovo/t530/early_init.c @@ -23,7 +23,6 @@ #include #include #include -#include static void hybrid_graphics_init(void) { diff --git a/src/mainboard/lenovo/t60/mptable.c b/src/mainboard/lenovo/t60/mptable.c index 165b725ac6..85b569a560 100644 --- a/src/mainboard/lenovo/t60/mptable.c +++ b/src/mainboard/lenovo/t60/mptable.c @@ -15,7 +15,6 @@ */ #include -#include #include #include #include diff --git a/src/mainboard/lenovo/x200/acpi_tables.c b/src/mainboard/lenovo/x200/acpi_tables.c index 8fb9056c51..953a2b84bf 100644 --- a/src/mainboard/lenovo/x200/acpi_tables.c +++ b/src/mainboard/lenovo/x200/acpi_tables.c @@ -19,7 +19,6 @@ #include #include #include -#include #include #include "thermal.h" diff --git a/src/mainboard/lenovo/x200/fadt.c b/src/mainboard/lenovo/x200/fadt.c index e335787100..9f4ebf6fe5 100644 --- a/src/mainboard/lenovo/x200/fadt.c +++ b/src/mainboard/lenovo/x200/fadt.c @@ -15,7 +15,6 @@ */ #include -#include #include #include #include diff --git a/src/mainboard/lenovo/x60/mptable.c b/src/mainboard/lenovo/x60/mptable.c index 886f72da37..22c5907e8e 100644 --- a/src/mainboard/lenovo/x60/mptable.c +++ b/src/mainboard/lenovo/x60/mptable.c @@ -15,7 +15,6 @@ */ #include -#include #include #include #include diff --git a/src/mainboard/lippert/frontrunner-af/acpi_tables.c b/src/mainboard/lippert/frontrunner-af/acpi_tables.c index 787c432041..97ea6492fb 100644 --- a/src/mainboard/lippert/frontrunner-af/acpi_tables.c +++ b/src/mainboard/lippert/frontrunner-af/acpi_tables.c @@ -15,7 +15,6 @@ #include #include -#include unsigned long acpi_fill_madt(unsigned long current) { diff --git a/src/mainboard/lippert/frontrunner-af/irq_tables.c b/src/mainboard/lippert/frontrunner-af/irq_tables.c index 9ebe58ae65..a066864abd 100644 --- a/src/mainboard/lippert/frontrunner-af/irq_tables.c +++ b/src/mainboard/lippert/frontrunner-af/irq_tables.c @@ -14,7 +14,6 @@ */ #include -#include #include #include #include diff --git a/src/mainboard/lippert/frontrunner-af/mainboard.c b/src/mainboard/lippert/frontrunner-af/mainboard.c index ea473c035c..6ad5234d81 100644 --- a/src/mainboard/lippert/frontrunner-af/mainboard.c +++ b/src/mainboard/lippert/frontrunner-af/mainboard.c @@ -17,7 +17,6 @@ #include #include #include -#include #include #include #include diff --git a/src/mainboard/lippert/frontrunner-af/mptable.c b/src/mainboard/lippert/frontrunner-af/mptable.c index 5e3a9508cb..347b7810b6 100644 --- a/src/mainboard/lippert/frontrunner-af/mptable.c +++ b/src/mainboard/lippert/frontrunner-af/mptable.c @@ -14,7 +14,6 @@ */ #include -#include #include #include #include diff --git a/src/mainboard/lippert/toucan-af/acpi_tables.c b/src/mainboard/lippert/toucan-af/acpi_tables.c index 787c432041..97ea6492fb 100644 --- a/src/mainboard/lippert/toucan-af/acpi_tables.c +++ b/src/mainboard/lippert/toucan-af/acpi_tables.c @@ -15,7 +15,6 @@ #include #include -#include unsigned long acpi_fill_madt(unsigned long current) { diff --git a/src/mainboard/lippert/toucan-af/irq_tables.c b/src/mainboard/lippert/toucan-af/irq_tables.c index 9ebe58ae65..a066864abd 100644 --- a/src/mainboard/lippert/toucan-af/irq_tables.c +++ b/src/mainboard/lippert/toucan-af/irq_tables.c @@ -14,7 +14,6 @@ */ #include -#include #include #include #include diff --git a/src/mainboard/lippert/toucan-af/mainboard.c b/src/mainboard/lippert/toucan-af/mainboard.c index b000688da6..1c9c5a6b91 100644 --- a/src/mainboard/lippert/toucan-af/mainboard.c +++ b/src/mainboard/lippert/toucan-af/mainboard.c @@ -17,7 +17,6 @@ #include #include #include -#include #include #include #include diff --git a/src/mainboard/lippert/toucan-af/mptable.c b/src/mainboard/lippert/toucan-af/mptable.c index 5e3a9508cb..347b7810b6 100644 --- a/src/mainboard/lippert/toucan-af/mptable.c +++ b/src/mainboard/lippert/toucan-af/mptable.c @@ -14,7 +14,6 @@ */ #include -#include #include #include #include diff --git a/src/mainboard/msi/ms7721/acpi_tables.c b/src/mainboard/msi/ms7721/acpi_tables.c index eba2d1da8b..fd59a3aade 100644 --- a/src/mainboard/msi/ms7721/acpi_tables.c +++ b/src/mainboard/msi/ms7721/acpi_tables.c @@ -15,7 +15,6 @@ #include #include -#include unsigned long acpi_fill_madt(unsigned long current) { diff --git a/src/mainboard/msi/ms7721/mptable.c b/src/mainboard/msi/ms7721/mptable.c index 8bfe4d535a..303f3bf5c4 100644 --- a/src/mainboard/msi/ms7721/mptable.c +++ b/src/mainboard/msi/ms7721/mptable.c @@ -17,7 +17,6 @@ #include #include #include -#include #include #include #include diff --git a/src/mainboard/packardbell/ms2290/mainboard.c b/src/mainboard/packardbell/ms2290/mainboard.c index d4e48bc0be..169b0ac7f8 100644 --- a/src/mainboard/packardbell/ms2290/mainboard.c +++ b/src/mainboard/packardbell/ms2290/mainboard.c @@ -24,7 +24,6 @@ #include #include #include -#include #include static void mainboard_enable(struct device *dev) diff --git a/src/mainboard/pcengines/apu1/acpi_tables.c b/src/mainboard/pcengines/apu1/acpi_tables.c index 787c432041..97ea6492fb 100644 --- a/src/mainboard/pcengines/apu1/acpi_tables.c +++ b/src/mainboard/pcengines/apu1/acpi_tables.c @@ -15,7 +15,6 @@ #include #include -#include unsigned long acpi_fill_madt(unsigned long current) { diff --git a/src/mainboard/pcengines/apu1/irq_tables.c b/src/mainboard/pcengines/apu1/irq_tables.c index 0bcb041558..1d1e81f05e 100644 --- a/src/mainboard/pcengines/apu1/irq_tables.c +++ b/src/mainboard/pcengines/apu1/irq_tables.c @@ -14,7 +14,6 @@ */ #include -#include #include #include #include diff --git a/src/mainboard/pcengines/apu1/mainboard.c b/src/mainboard/pcengines/apu1/mainboard.c index 1c302912a9..854fb8ad4d 100644 --- a/src/mainboard/pcengines/apu1/mainboard.c +++ b/src/mainboard/pcengines/apu1/mainboard.c @@ -16,7 +16,6 @@ #include #include -#include #include #include #include diff --git a/src/mainboard/pcengines/apu1/mptable.c b/src/mainboard/pcengines/apu1/mptable.c index bb8d01ecb9..89e5dfc35b 100644 --- a/src/mainboard/pcengines/apu1/mptable.c +++ b/src/mainboard/pcengines/apu1/mptable.c @@ -15,7 +15,6 @@ */ #include -#include #include #include #include diff --git a/src/mainboard/pcengines/apu2/acpi_tables.c b/src/mainboard/pcengines/apu2/acpi_tables.c index 08f6076e7c..20509e9d31 100644 --- a/src/mainboard/pcengines/apu2/acpi_tables.c +++ b/src/mainboard/pcengines/apu2/acpi_tables.c @@ -15,7 +15,6 @@ #include #include -#include unsigned long acpi_fill_madt(unsigned long current) { diff --git a/src/mainboard/pcengines/apu2/irq_tables.c b/src/mainboard/pcengines/apu2/irq_tables.c index 2c9340199c..3d6346e3c0 100644 --- a/src/mainboard/pcengines/apu2/irq_tables.c +++ b/src/mainboard/pcengines/apu2/irq_tables.c @@ -14,7 +14,6 @@ */ #include -#include #include #include #include diff --git a/src/mainboard/pcengines/apu2/mainboard.c b/src/mainboard/pcengines/apu2/mainboard.c index d46361c93b..6cb504abd2 100644 --- a/src/mainboard/pcengines/apu2/mainboard.c +++ b/src/mainboard/pcengines/apu2/mainboard.c @@ -18,7 +18,6 @@ #include #include #include -#include #include #include #include diff --git a/src/mainboard/roda/rk886ex/mptable.c b/src/mainboard/roda/rk886ex/mptable.c index 2db0f75964..e17dcc2e4f 100644 --- a/src/mainboard/roda/rk886ex/mptable.c +++ b/src/mainboard/roda/rk886ex/mptable.c @@ -15,7 +15,6 @@ */ #include -#include #include #include #include diff --git a/src/mainboard/roda/rk9/acpi_tables.c b/src/mainboard/roda/rk9/acpi_tables.c index 0700ca06a0..3c76fac8b5 100644 --- a/src/mainboard/roda/rk9/acpi_tables.c +++ b/src/mainboard/roda/rk9/acpi_tables.c @@ -19,7 +19,6 @@ #include #include #include -#include #include void acpi_create_gnvs(global_nvs_t *gnvs) diff --git a/src/mainboard/roda/rk9/fadt.c b/src/mainboard/roda/rk9/fadt.c index e335787100..9f4ebf6fe5 100644 --- a/src/mainboard/roda/rk9/fadt.c +++ b/src/mainboard/roda/rk9/fadt.c @@ -15,7 +15,6 @@ */ #include -#include #include #include #include diff --git a/src/mainboard/roda/rv11/variants/rv11/early_init.c b/src/mainboard/roda/rv11/variants/rv11/early_init.c index 80d8028b94..bd4d5c5726 100644 --- a/src/mainboard/roda/rv11/variants/rv11/early_init.c +++ b/src/mainboard/roda/rv11/variants/rv11/early_init.c @@ -14,7 +14,6 @@ */ #include -#include #include #include #include diff --git a/src/mainboard/roda/rv11/variants/rw11/early_init.c b/src/mainboard/roda/rv11/variants/rw11/early_init.c index b64facae1b..cefb6d653b 100644 --- a/src/mainboard/roda/rv11/variants/rw11/early_init.c +++ b/src/mainboard/roda/rv11/variants/rw11/early_init.c @@ -15,7 +15,6 @@ #include #include -#include #include #include #include diff --git a/src/mainboard/samsung/lumpy/acpi_tables.c b/src/mainboard/samsung/lumpy/acpi_tables.c index 8038664025..413841c60b 100644 --- a/src/mainboard/samsung/lumpy/acpi_tables.c +++ b/src/mainboard/samsung/lumpy/acpi_tables.c @@ -17,7 +17,6 @@ #include #include #include -#include #include #if CONFIG(CHROMEOS) #include diff --git a/src/mainboard/samsung/lumpy/chromeos.c b/src/mainboard/samsung/lumpy/chromeos.c index c70ee1d22e..342f7a968a 100644 --- a/src/mainboard/samsung/lumpy/chromeos.c +++ b/src/mainboard/samsung/lumpy/chromeos.c @@ -17,7 +17,6 @@ #include #include #include -#include #include #include #include diff --git a/src/mainboard/samsung/stumpy/acpi_tables.c b/src/mainboard/samsung/stumpy/acpi_tables.c index 17d7e0e296..b913bd623d 100644 --- a/src/mainboard/samsung/stumpy/acpi_tables.c +++ b/src/mainboard/samsung/stumpy/acpi_tables.c @@ -17,7 +17,6 @@ #include #include #include -#include #include #include diff --git a/src/mainboard/samsung/stumpy/chromeos.c b/src/mainboard/samsung/stumpy/chromeos.c index 2cce8ad9fc..955ba5a620 100644 --- a/src/mainboard/samsung/stumpy/chromeos.c +++ b/src/mainboard/samsung/stumpy/chromeos.c @@ -17,7 +17,6 @@ #include #include #include -#include #include #include #include diff --git a/src/mainboard/scaleway/tagada/acpi_tables.c b/src/mainboard/scaleway/tagada/acpi_tables.c index 43818eebe4..1f92419a75 100644 --- a/src/mainboard/scaleway/tagada/acpi_tables.c +++ b/src/mainboard/scaleway/tagada/acpi_tables.c @@ -19,7 +19,6 @@ #include #include #include -#include #include #include diff --git a/src/mainboard/siemens/mc_apl1/mainboard.c b/src/mainboard/siemens/mc_apl1/mainboard.c index 22d37bfdc2..784a08c670 100644 --- a/src/mainboard/siemens/mc_apl1/mainboard.c +++ b/src/mainboard/siemens/mc_apl1/mainboard.c @@ -17,7 +17,6 @@ #include #include #include -#include #include #include #include From 520717dff196e1d1ed61f72a8abadbc114ee6ba1 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ky=C3=B6sti=20M=C3=A4lkki?= Date: Sun, 15 Dec 2019 21:37:48 +0200 Subject: [PATCH 0808/1242] AGESA,binaryPI: Drop remains of ROMCC_BOOTBLOCK MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Change-Id: I507ac6d483d9854852d6d01f10544c450b8d33cc Signed-off-by: Michał Żygowski Signed-off-by: Kyösti Mälkki Reviewed-on: https://review.coreboot.org/c/coreboot/+/37440 Reviewed-by: HAOUAS Elyes Tested-by: build bot (Jenkins) --- src/cpu/amd/agesa/family14/fixme.c | 19 ----------- src/cpu/amd/agesa/family15tn/fixme.c | 19 ----------- src/cpu/amd/agesa/family16kb/fixme.c | 19 ----------- src/cpu/amd/pi/00630F01/fixme.c | 21 ------------ src/cpu/amd/pi/00660F01/fixme.c | 28 ---------------- src/cpu/amd/pi/00730F01/fixme.c | 33 ------------------- src/drivers/amd/agesa/Makefile.inc | 4 --- src/drivers/amd/agesa/bootblock.c | 6 ++++ src/drivers/amd/agesa/romstage.c | 29 +--------------- src/northbridge/amd/agesa/agesa_helper.h | 1 - .../amd/agesa/family14/state_machine.c | 3 +- src/southbridge/amd/agesa/hudson/Kconfig | 4 --- src/southbridge/amd/agesa/hudson/Makefile.inc | 2 -- src/southbridge/amd/agesa/hudson/bootblock.c | 21 +++--------- src/southbridge/amd/cimx/sb800/Makefile.inc | 2 -- src/southbridge/amd/cimx/sb800/bootblock.c | 25 ++------------ src/southbridge/amd/pi/hudson/Kconfig | 4 --- src/southbridge/amd/pi/hudson/Makefile.inc | 2 -- src/southbridge/amd/pi/hudson/bootblock.c | 19 +++-------- 19 files changed, 21 insertions(+), 240 deletions(-) diff --git a/src/cpu/amd/agesa/family14/fixme.c b/src/cpu/amd/agesa/family14/fixme.c index c9d30396aa..be7c635471 100644 --- a/src/cpu/amd/agesa/family14/fixme.c +++ b/src/cpu/amd/agesa/family14/fixme.c @@ -61,25 +61,6 @@ void amd_initcpuio(void) LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); } -void amd_initmmio(void) -{ - UINT64 MsrReg; - AMD_CONFIG_PARAMS StdHeader; - - /* - Set the MMIO Configuration Base Address and Bus Range onto MMIO configuration base - Address MSR register. - */ - MsrReg = CONFIG_MMCONF_BASE_ADDRESS | (LibAmdBitScanReverse(CONFIG_MMCONF_BUS_NUMBER) << 2) | 1; - LibAmdMsrWrite(MMIO_CONF_BASE, &MsrReg, &StdHeader); - - /* Set ROM cache onto WP to decrease post time */ - MsrReg = (0x0100000000ull - CACHE_ROM_SIZE) | MTRR_TYPE_WRPROT; - LibAmdMsrWrite(MTRR_PHYS_BASE(6), &MsrReg, &StdHeader); - MsrReg = ((1ULL << CONFIG_CPU_ADDR_BITS) - CACHE_ROM_SIZE) | MTRR_PHYS_MASK_VALID; - LibAmdMsrWrite(MTRR_PHYS_MASK(6), &MsrReg, &StdHeader); -} - void amd_initenv(void) { AMD_INTERFACE_PARAMS AmdParamStruct; diff --git a/src/cpu/amd/agesa/family15tn/fixme.c b/src/cpu/amd/agesa/family15tn/fixme.c index e92aa9a9bf..03c6503300 100644 --- a/src/cpu/amd/agesa/family15tn/fixme.c +++ b/src/cpu/amd/agesa/family15tn/fixme.c @@ -60,22 +60,3 @@ void amd_initcpuio(void) PciData = 0x00000003; LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); } - -void amd_initmmio(void) -{ - UINT64 MsrReg; - AMD_CONFIG_PARAMS StdHeader; - - /* - Set the MMIO Configuration Base Address and Bus Range onto MMIO configuration base - Address MSR register. - */ - MsrReg = CONFIG_MMCONF_BASE_ADDRESS | (LibAmdBitScanReverse (CONFIG_MMCONF_BUS_NUMBER) << 2) | 1; - LibAmdMsrWrite(MMIO_CONF_BASE, &MsrReg, &StdHeader); - - /* Set ROM cache onto WP to decrease post time */ - MsrReg = (0x0100000000ull - CACHE_ROM_SIZE) | 5ull; - LibAmdMsrWrite(MTRR_PHYS_BASE(6), &MsrReg, &StdHeader); - MsrReg = ((1ULL << CONFIG_CPU_ADDR_BITS) - CACHE_ROM_SIZE) | 0x800ull; - LibAmdMsrWrite(MTRR_PHYS_MASK(6), &MsrReg, &StdHeader); -} diff --git a/src/cpu/amd/agesa/family16kb/fixme.c b/src/cpu/amd/agesa/family16kb/fixme.c index 73d09956cd..260efc2643 100644 --- a/src/cpu/amd/agesa/family16kb/fixme.c +++ b/src/cpu/amd/agesa/family16kb/fixme.c @@ -60,22 +60,3 @@ void amd_initcpuio(void) PciData = 0x00000003; LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); } - -void amd_initmmio(void) -{ - UINT64 MsrReg; - AMD_CONFIG_PARAMS StdHeader; - - /* - Set the MMIO Configuration Base Address and Bus Range onto MMIO configuration base - Address MSR register. - */ - MsrReg = CONFIG_MMCONF_BASE_ADDRESS | (LibAmdBitScanReverse (CONFIG_MMCONF_BUS_NUMBER) << 2) | 1; - LibAmdMsrWrite(MMIO_CONF_BASE, &MsrReg, &StdHeader); - - /* Set ROM cache onto WP to decrease post time */ - MsrReg = (0x0100000000ull - CACHE_ROM_SIZE) | 5ull; - LibAmdMsrWrite(MTRR_PHYS_BASE(6), &MsrReg, &StdHeader); - MsrReg = ((1ULL << CONFIG_CPU_ADDR_BITS) - CACHE_ROM_SIZE) | 0x800ull; - LibAmdMsrWrite(MTRR_PHYS_MASK(6), &MsrReg, &StdHeader); -} diff --git a/src/cpu/amd/pi/00630F01/fixme.c b/src/cpu/amd/pi/00630F01/fixme.c index d94215a44b..4699eeac26 100644 --- a/src/cpu/amd/pi/00630F01/fixme.c +++ b/src/cpu/amd/pi/00630F01/fixme.c @@ -65,24 +65,3 @@ void amd_initcpuio(void) PciData = 0x00000003; LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); } - -void amd_initmmio(void) -{ - UINT64 MsrReg; - AMD_CONFIG_PARAMS StdHeader; - - /* - * Set the MMIO Configuration Base Address - * and Bus Range onto MMIO configuration base - * Address MSR register. - */ - MsrReg = CONFIG_MMCONF_BASE_ADDRESS | - (LibAmdBitScanReverse(CONFIG_MMCONF_BUS_NUMBER) << 2) | 1; - LibAmdMsrWrite(MMIO_CONF_BASE, &MsrReg, &StdHeader); - - /* Set ROM cache onto WP to decrease post time */ - MsrReg = (0x0100000000ull - CACHE_ROM_SIZE) | 5ull; - LibAmdMsrWrite(MTRR_PHYS_BASE(6), &MsrReg, &StdHeader); - MsrReg = ((1ULL << CONFIG_CPU_ADDR_BITS) - CACHE_ROM_SIZE) | 0x800ull; - LibAmdMsrWrite(MTRR_PHYS_MASK(6), &MsrReg, &StdHeader); -} diff --git a/src/cpu/amd/pi/00660F01/fixme.c b/src/cpu/amd/pi/00660F01/fixme.c index 7d71e2ea1a..1ce7432fe4 100644 --- a/src/cpu/amd/pi/00660F01/fixme.c +++ b/src/cpu/amd/pi/00660F01/fixme.c @@ -64,31 +64,3 @@ void amd_initcpuio(void) PciData = 0x00000003; LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); } - -void amd_initmmio(void) -{ - UINT64 MsrReg; - UINT32 PciData; - PCI_ADDR PciAddress; - AMD_CONFIG_PARAMS StdHeader; - - /* - * Set the MMIO Configuration Base Address and - * Bus Range onto MMIO configuration base - * Address MSR register. - */ - MsrReg = CONFIG_MMCONF_BASE_ADDRESS | - (LibAmdBitScanReverse(CONFIG_MMCONF_BUS_NUMBER) << 2) | 1; - LibAmdMsrWrite(MMIO_CONF_BASE, &MsrReg, &StdHeader); - - /* For serial port */ - PciData = 0xFF03FFD5; - PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x14, 0x3, 0x44); - LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); - - /* Set ROM cache onto WP to decrease post time */ - MsrReg = (0x0100000000ull - CACHE_ROM_SIZE) | 5ull; - LibAmdMsrWrite(MTRR_PHYS_BASE(6), &MsrReg, &StdHeader); - MsrReg = ((1ULL << CONFIG_CPU_ADDR_BITS) - CACHE_ROM_SIZE) | 0x800ull; - LibAmdMsrWrite(MTRR_PHYS_MASK(6), &MsrReg, &StdHeader); -} diff --git a/src/cpu/amd/pi/00730F01/fixme.c b/src/cpu/amd/pi/00730F01/fixme.c index 7edd1b8fa2..1ce7432fe4 100644 --- a/src/cpu/amd/pi/00730F01/fixme.c +++ b/src/cpu/amd/pi/00730F01/fixme.c @@ -64,36 +64,3 @@ void amd_initcpuio(void) PciData = 0x00000003; LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); } - -void amd_initmmio(void) -{ - UINT64 MsrReg; - UINT32 PciData; - PCI_ADDR PciAddress; - AMD_CONFIG_PARAMS StdHeader; - - /* - * Set the MMIO Configuration Base Address and - * Bus Range onto MMIO configuration base - * Address MSR register. - */ - MsrReg = CONFIG_MMCONF_BASE_ADDRESS | - (LibAmdBitScanReverse(CONFIG_MMCONF_BUS_NUMBER) << 2) | 1; - LibAmdMsrWrite(MMIO_CONF_BASE, &MsrReg, &StdHeader); - - /* For serial port */ - PciData = 0xFF03FFD5; - PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x14, 0x3, 0x44); - LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); - - /* PSP */ - //PciData = 0xD; - //PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x8, 0x0, 0x48); - //LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); - - /* Set ROM cache onto WP to decrease post time */ - MsrReg = (0x0100000000ull - CACHE_ROM_SIZE) | 5ull; - LibAmdMsrWrite(MTRR_PHYS_BASE(6), &MsrReg, &StdHeader); - MsrReg = ((1ULL << CONFIG_CPU_ADDR_BITS) - CACHE_ROM_SIZE) | 0x800ull; - LibAmdMsrWrite(MTRR_PHYS_MASK(6), &MsrReg, &StdHeader); -} diff --git a/src/drivers/amd/agesa/Makefile.inc b/src/drivers/amd/agesa/Makefile.inc index 3c3c4fc621..4536fc9aca 100644 --- a/src/drivers/amd/agesa/Makefile.inc +++ b/src/drivers/amd/agesa/Makefile.inc @@ -19,12 +19,8 @@ romstage-y += state_machine.c ramstage-y += state_machine.c -ifneq ($(CONFIG_ROMCC_BOOTBLOCK),y) bootblock-y += bootblock.c bootblock-y += cache_as_ram.S -else -cpu_incs-y += $(src)/drivers/amd/agesa/cache_as_ram.S -endif postcar-y += exit_car.S diff --git a/src/drivers/amd/agesa/bootblock.c b/src/drivers/amd/agesa/bootblock.c index 91fcc6b994..7732f27fd5 100644 --- a/src/drivers/amd/agesa/bootblock.c +++ b/src/drivers/amd/agesa/bootblock.c @@ -16,6 +16,7 @@ #include #include #include +#include #include #include #include @@ -29,6 +30,11 @@ static void set_early_mtrrs(void) OPTIMAL_CACHE_ROM_SIZE, MTRR_TYPE_WRPROT); } +void bootblock_soc_early_init(void) +{ + bootblock_early_southbridge_init(); +} + asmlinkage void bootblock_c_entry(uint64_t base_timestamp) { enable_pci_mmconf(); diff --git a/src/drivers/amd/agesa/romstage.c b/src/drivers/amd/agesa/romstage.c index ee4d45e95b..e8f4da2f28 100644 --- a/src/drivers/amd/agesa/romstage.c +++ b/src/drivers/amd/agesa/romstage.c @@ -15,7 +15,6 @@ #include #include #include -#include #include #include #include @@ -50,16 +49,10 @@ static void romstage_main(void) u8 initial_apic_id = (u8) (cpuid_ebx(1) >> 24); int cbmem_initted = 0; - /* Enable PCI MMIO configuration. */ - if (CONFIG(ROMCC_BOOTBLOCK)) - amd_initmmio(); - fill_sysinfo(cb); if (initial_apic_id == 0) { - if (CONFIG(ROMCC_BOOTBLOCK)) - timestamp_init(timestamp_get()); timestamp_add_now(TS_START_ROMSTAGE); board_BeforeAgesa(cb); @@ -70,8 +63,7 @@ static void romstage_main(void) printk(BIOS_DEBUG, "APIC %02d: CPU Family_Model = %08x\n", initial_apic_id, cpuid_eax(1)); - if (!CONFIG(ROMCC_BOOTBLOCK)) - set_ap_entry_ptr(ap_romstage_main); + set_ap_entry_ptr(ap_romstage_main); agesa_execute_state(cb, AMD_INIT_RESET); @@ -112,10 +104,6 @@ static void ap_romstage_main(void) struct sysinfo romstage_state; struct sysinfo *cb = &romstage_state; - /* Enable PCI MMIO configuration. */ - if (CONFIG(ROMCC_BOOTBLOCK)) - amd_initmmio(); - fill_sysinfo(cb); agesa_execute_state(cb, AMD_INIT_RESET); @@ -126,22 +114,7 @@ static void ap_romstage_main(void) halt(); } -#if CONFIG(ROMCC_BOOTBLOCK) -/* This wrapper enables easy transition away from ROMCC_BOOTBLOCK - * keeping changes in cache_as_ram.S easy to manage. - */ -asmlinkage void bootblock_c_entry(uint64_t base_timestamp) -{ - romstage_main(); -} - -asmlinkage void ap_bootblock_c_entry(void) -{ - ap_romstage_main(); -} -#else asmlinkage void car_stage_entry(void) { romstage_main(); } -#endif diff --git a/src/northbridge/amd/agesa/agesa_helper.h b/src/northbridge/amd/agesa/agesa_helper.h index dcc336083f..a52b069d13 100644 --- a/src/northbridge/amd/agesa/agesa_helper.h +++ b/src/northbridge/amd/agesa/agesa_helper.h @@ -36,7 +36,6 @@ void agesawrapper_setlateinitptr (void *Late); void *agesawrapper_getlateinitptr (int pick); void amd_initcpuio(void); -void amd_initmmio(void); void amd_initenv(void); void *GetHeapBase(void); diff --git a/src/northbridge/amd/agesa/family14/state_machine.c b/src/northbridge/amd/agesa/family14/state_machine.c index 91a8f70259..ab96b75f40 100644 --- a/src/northbridge/amd/agesa/family14/state_machine.c +++ b/src/northbridge/amd/agesa/family14/state_machine.c @@ -32,8 +32,7 @@ void platform_BeforeInitReset(struct sysinfo *cb, AMD_RESET_PARAMS *Reset) if (!boot_cpu()) return; - if (!CONFIG(ROMCC_BOOTBLOCK)) - sb_Poweron_Init(); + sb_Poweron_Init(); /* Reboots with outb(3,0x92), outb(4,0xcf9) or triple-fault all * would fail later in AmdInitPost(), when DRAM is already configured diff --git a/src/southbridge/amd/agesa/hudson/Kconfig b/src/southbridge/amd/agesa/hudson/Kconfig index 93db1a920c..e56a493a63 100644 --- a/src/southbridge/amd/agesa/hudson/Kconfig +++ b/src/southbridge/amd/agesa/hudson/Kconfig @@ -31,10 +31,6 @@ config SOUTHBRIDGE_SPECIFIC_OPTIONS # dummy select SOC_AMD_COMMON_BLOCK select SOC_AMD_COMMON_BLOCK_ACPIMMIO -config BOOTBLOCK_SOUTHBRIDGE_INIT - string - default "southbridge/amd/agesa/hudson/bootblock.c" - config EHCI_BAR hex default 0xfef00000 diff --git a/src/southbridge/amd/agesa/hudson/Makefile.inc b/src/southbridge/amd/agesa/hudson/Makefile.inc index be4ea26bee..b8eb5b9b37 100644 --- a/src/southbridge/amd/agesa/hudson/Makefile.inc +++ b/src/southbridge/amd/agesa/hudson/Makefile.inc @@ -16,11 +16,9 @@ ramstage-y += sd.c ramstage-$(CONFIG_HAVE_ACPI_TABLES) += fadt.c -ifneq ($(CONFIG_ROMCC_BOOTBLOCK),y) bootblock-y += bootblock.c bootblock-y += early_setup.c bootblock-$(CONFIG_USBDEBUG) += enable_usbdebug.c -endif romstage-y += enable_usbdebug.c ramstage-y += enable_usbdebug.c diff --git a/src/southbridge/amd/agesa/hudson/bootblock.c b/src/southbridge/amd/agesa/hudson/bootblock.c index 4da030b89a..517b928d8d 100644 --- a/src/southbridge/amd/agesa/hudson/bootblock.c +++ b/src/southbridge/amd/agesa/hudson/bootblock.c @@ -14,7 +14,10 @@ */ #include +#include +#include #include +#include /* * Enable 4MB (LPC) ROM access at 0xFFC00000 - 0xFFFFFFFF. @@ -56,24 +59,12 @@ static void hudson_enable_rom(void) pci_io_write_config16(dev, 0x6e, 0xffff); } -static void bootblock_southbridge_init(void) -{ - hudson_enable_rom(); -} - - -#if !CONFIG(ROMCC_BOOTBLOCK) - -#include -#include -#include - -void bootblock_soc_early_init(void) +void bootblock_early_southbridge_init(void) { pci_devfn_t dev; u32 data; - bootblock_southbridge_init(); + hudson_enable_rom(); enable_acpimmio_decode_pm24(); hudson_lpc_decode(); @@ -94,7 +85,6 @@ void bootblock_soc_early_init(void) * Enable decoding of legacy TPM addresses: IO addresses 0x7f- * 0x7e and 0xef-0xee. */ - data = pci_read_config32(dev, LPC_TRUSTED_PLATFORM_MODULE); data |= TPM_12_EN | TPM_LEGACY_EN; pci_write_config32(dev, LPC_TRUSTED_PLATFORM_MODULE, data); @@ -109,4 +99,3 @@ void bootblock_soc_early_init(void) */ pm_write8(0xd2, 0); } -#endif diff --git a/src/southbridge/amd/cimx/sb800/Makefile.inc b/src/southbridge/amd/cimx/sb800/Makefile.inc index 5a68d0732e..2c516485f2 100644 --- a/src/southbridge/amd/cimx/sb800/Makefile.inc +++ b/src/southbridge/amd/cimx/sb800/Makefile.inc @@ -16,9 +16,7 @@ # SB800 Platform Files -ifneq ($(CONFIG_ROMCC_BOOTBLOCK),y) bootblock-y += bootblock.c -endif romstage-y += cfg.c romstage-y += early.c diff --git a/src/southbridge/amd/cimx/sb800/bootblock.c b/src/southbridge/amd/cimx/sb800/bootblock.c index b4f03dad7e..d42e7eef1d 100644 --- a/src/southbridge/amd/cimx/sb800/bootblock.c +++ b/src/southbridge/amd/cimx/sb800/bootblock.c @@ -13,7 +13,8 @@ * GNU General Public License for more details. */ -#include +#include +#include #include static void enable_rom(void) @@ -79,17 +80,6 @@ static void enable_spi_fast_mode(void) pci_io_write_config32(dev, 0xa0, save); } -static void enable_acpimmio_decode_pm24(void) -{ - u8 reg8; - - outb(0x24, 0xCD6); - reg8 = inb(0xCD7); - reg8 |= 1; - reg8 &= ~(1 << 1); - outb(reg8, 0xCD7); -} - static void enable_clocks(void) { u32 reg32; @@ -109,7 +99,7 @@ static void enable_clocks(void) *acpi_mmio = reg32; } -static void bootblock_southbridge_init(void) +void bootblock_early_southbridge_init(void) { /* Setup the ROM access for 2M */ enable_rom(); @@ -120,12 +110,3 @@ static void bootblock_southbridge_init(void) enable_acpimmio_decode_pm24(); enable_clocks(); } - -#if !CONFIG(ROMCC_BOOTBLOCK) -#include - -void bootblock_soc_early_init(void) -{ - bootblock_southbridge_init(); -} -#endif diff --git a/src/southbridge/amd/pi/hudson/Kconfig b/src/southbridge/amd/pi/hudson/Kconfig index 01f3937321..ea37e3ee12 100644 --- a/src/southbridge/amd/pi/hudson/Kconfig +++ b/src/southbridge/amd/pi/hudson/Kconfig @@ -34,10 +34,6 @@ config SOUTHBRIDGE_SPECIFIC_OPTIONS # dummy select SOC_AMD_COMMON_BLOCK select SOC_AMD_COMMON_BLOCK_ACPIMMIO -config BOOTBLOCK_SOUTHBRIDGE_INIT - string - default "southbridge/amd/pi/hudson/bootblock.c" - config EHCI_BAR hex default 0xfef00000 diff --git a/src/southbridge/amd/pi/hudson/Makefile.inc b/src/southbridge/amd/pi/hudson/Makefile.inc index 4aa9babafe..9d985e6d7b 100644 --- a/src/southbridge/amd/pi/hudson/Makefile.inc +++ b/src/southbridge/amd/pi/hudson/Makefile.inc @@ -28,11 +28,9 @@ # #***************************************************************************** -ifneq ($(CONFIG_ROMCC_BOOTBLOCK),y) bootblock-y += bootblock.c bootblock-y += early_setup.c bootblock-$(CONFIG_USBDEBUG) += enable_usbdebug.c -endif romstage-y += early_setup.c romstage-y += enable_usbdebug.c diff --git a/src/southbridge/amd/pi/hudson/bootblock.c b/src/southbridge/amd/pi/hudson/bootblock.c index d16aecc2a8..77a4570830 100644 --- a/src/southbridge/amd/pi/hudson/bootblock.c +++ b/src/southbridge/amd/pi/hudson/bootblock.c @@ -14,7 +14,10 @@ */ #include +#include +#include #include +#include /* * Enable 4MB (LPC) ROM access at 0xFFC00000 - 0xFFFFFFFF. @@ -56,23 +59,12 @@ static void hudson_enable_rom(void) pci_io_write_config16(dev, 0x6e, 0xffff); } -static void bootblock_southbridge_init(void) -{ - hudson_enable_rom(); -} - -#if !CONFIG(ROMCC_BOOTBLOCK) - -#include -#include -#include - -void bootblock_soc_early_init(void) +void bootblock_early_southbridge_init(void) { pci_devfn_t dev; u32 data; - bootblock_southbridge_init(); + hudson_enable_rom(); if (CONFIG(SOUTHBRIDGE_AMD_PI_BOLTON)) enable_acpimmio_decode_pm24(); else @@ -111,4 +103,3 @@ void bootblock_soc_early_init(void) */ pm_write8(0xd2, 0); } -#endif From b915faedd503f7904fef9f7ff531262981061473 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ky=C3=B6sti=20M=C3=A4lkki?= Date: Mon, 9 Dec 2019 08:08:58 +0200 Subject: [PATCH 0809/1242] sb/amd/{agesa,pi}/hudson: Use simple PCI config accessor MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Change-Id: I3d8e21e17a0f870d854694e326b10f7d2d04e5ad Signed-off-by: Kyösti Mälkki Reviewed-on: https://review.coreboot.org/c/coreboot/+/37596 Reviewed-by: Angel Pons Reviewed-by: HAOUAS Elyes Reviewed-by: Michał Żygowski Tested-by: build bot (Jenkins) --- src/southbridge/amd/agesa/hudson/reset.c | 4 ++-- src/southbridge/amd/pi/hudson/reset.c | 4 ++-- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/src/southbridge/amd/agesa/hudson/reset.c b/src/southbridge/amd/agesa/hudson/reset.c index e3290384dc..ff77eb87d3 100644 --- a/src/southbridge/amd/agesa/hudson/reset.c +++ b/src/southbridge/amd/agesa/hudson/reset.c @@ -28,9 +28,9 @@ void cf9_reset_prepare(void) { u32 htic; - htic = pci_io_read_config32(PCI_DEV(0, 0x18, 0), HT_INIT_CONTROL); + htic = pci_s_read_config32(PCI_DEV(0, 0x18, 0), HT_INIT_CONTROL); htic &= ~HTIC_BIOSR_Detect; - pci_io_write_config32(PCI_DEV(0, 0x18, 0), HT_INIT_CONTROL, htic); + pci_s_write_config32(PCI_DEV(0, 0x18, 0), HT_INIT_CONTROL, htic); } void do_board_reset(void) diff --git a/src/southbridge/amd/pi/hudson/reset.c b/src/southbridge/amd/pi/hudson/reset.c index e3290384dc..ff77eb87d3 100644 --- a/src/southbridge/amd/pi/hudson/reset.c +++ b/src/southbridge/amd/pi/hudson/reset.c @@ -28,9 +28,9 @@ void cf9_reset_prepare(void) { u32 htic; - htic = pci_io_read_config32(PCI_DEV(0, 0x18, 0), HT_INIT_CONTROL); + htic = pci_s_read_config32(PCI_DEV(0, 0x18, 0), HT_INIT_CONTROL); htic &= ~HTIC_BIOSR_Detect; - pci_io_write_config32(PCI_DEV(0, 0x18, 0), HT_INIT_CONTROL, htic); + pci_s_write_config32(PCI_DEV(0, 0x18, 0), HT_INIT_CONTROL, htic); } void do_board_reset(void) From 282717e5cc325595143d96036653b03ac0fcf480 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ky=C3=B6sti=20M=C3=A4lkki?= Date: Mon, 9 Dec 2019 08:08:58 +0200 Subject: [PATCH 0810/1242] sb/amd/{agesa,pi,cimx}/bootblock: Use simple PCI config accessor MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Change-Id: I5e1f2ceda37927d7a75660affee8504f9f8aff15 Signed-off-by: Kyösti Mälkki Reviewed-on: https://review.coreboot.org/c/coreboot/+/37597 Reviewed-by: Angel Pons Reviewed-by: HAOUAS Elyes Reviewed-by: Michał Żygowski Tested-by: build bot (Jenkins) --- src/southbridge/amd/agesa/hudson/bootblock.c | 12 +++++------ src/southbridge/amd/cimx/sb800/bootblock.c | 22 ++++++++++---------- src/southbridge/amd/pi/hudson/bootblock.c | 12 +++++------ 3 files changed, 23 insertions(+), 23 deletions(-) diff --git a/src/southbridge/amd/agesa/hudson/bootblock.c b/src/southbridge/amd/agesa/hudson/bootblock.c index 517b928d8d..2fa0da61e8 100644 --- a/src/southbridge/amd/agesa/hudson/bootblock.c +++ b/src/southbridge/amd/agesa/hudson/bootblock.c @@ -36,15 +36,15 @@ static void hudson_enable_rom(void) dev = PCI_DEV(0, 0x14, 3); /* Decode variable LPC ROM address ranges 1 and 2. */ - reg8 = pci_io_read_config8(dev, 0x48); + reg8 = pci_s_read_config8(dev, 0x48); reg8 |= (1 << 3) | (1 << 4); - pci_io_write_config8(dev, 0x48, reg8); + pci_s_write_config8(dev, 0x48, reg8); /* LPC ROM address range 1: */ /* Enable LPC ROM range mirroring start at 0x000e(0000). */ - pci_io_write_config16(dev, 0x68, 0x000e); + pci_s_write_config16(dev, 0x68, 0x000e); /* Enable LPC ROM range mirroring end at 0x000f(ffff). */ - pci_io_write_config16(dev, 0x6a, 0x000f); + pci_s_write_config16(dev, 0x6a, 0x000f); /* LPC ROM address range 2: */ /* @@ -54,9 +54,9 @@ static void hudson_enable_rom(void) * 0xffe0(0000): 2MB * 0xffc0(0000): 4MB */ - pci_io_write_config16(dev, 0x6c, 0x10000 - (CONFIG_COREBOOT_ROMSIZE_KB >> 6)); + pci_s_write_config16(dev, 0x6c, 0x10000 - (CONFIG_COREBOOT_ROMSIZE_KB >> 6)); /* Enable LPC ROM range end at 0xffff(ffff). */ - pci_io_write_config16(dev, 0x6e, 0xffff); + pci_s_write_config16(dev, 0x6e, 0xffff); } void bootblock_early_southbridge_init(void) diff --git a/src/southbridge/amd/cimx/sb800/bootblock.c b/src/southbridge/amd/cimx/sb800/bootblock.c index d42e7eef1d..5decebfac4 100644 --- a/src/southbridge/amd/cimx/sb800/bootblock.c +++ b/src/southbridge/amd/cimx/sb800/bootblock.c @@ -29,11 +29,11 @@ static void enable_rom(void) * BIT29: Port Enable for KBC port 0x60 and 0x64 * BIT30: Port Enable for ACPI Micro-Controller port 0x66 and 0x62 */ - dword = pci_io_read_config32(dev, 0x44); + dword = pci_s_read_config32(dev, 0x44); //dword |= (1<<6) | (1<<29) | (1<<30); /* Turn on all of LPC IO Port decode enable */ dword = 0xffffffff; - pci_io_write_config32(dev, 0x44, dword); + pci_s_write_config32(dev, 0x44, dword); /* SB800 LPC Bridge 0:20:3:48h. * BIT0: Port Enable for SuperIO 0x2E-0x2F @@ -42,14 +42,14 @@ static void enable_rom(void) * BIT6: Port Enable for RTC IO 0x70-0x73 * BIT21: Port Enable for Port 0x80 */ - dword = pci_io_read_config32(dev, 0x48); + dword = pci_s_read_config32(dev, 0x48); dword |= (1 << 0) | (1 << 1) | (1 << 4) | (1 << 6) | (1 << 21); - pci_io_write_config32(dev, 0x48, dword); + pci_s_write_config32(dev, 0x48, dword); /* Enable ROM access */ - word = pci_io_read_config16(dev, 0x6c); + word = pci_s_read_config16(dev, 0x6c); word = 0x10000 - (CONFIG_COREBOOT_ROMSIZE_KB >> 6); - pci_io_write_config16(dev, 0x6c, word); + pci_s_write_config16(dev, 0x6c, word); } static void enable_prefetch(void) @@ -58,8 +58,8 @@ static void enable_prefetch(void) pci_devfn_t dev = PCI_DEV(0, 0x14, 0x03); /* Enable PrefetchEnSPIFromHost */ - dword = pci_io_read_config32(dev, 0xb8); - pci_io_write_config32(dev, 0xb8, dword | (1 << 24)); + dword = pci_s_read_config32(dev, 0xb8); + pci_s_write_config32(dev, 0xb8, dword | (1 << 24)); } static void enable_spi_fast_mode(void) @@ -69,15 +69,15 @@ static void enable_spi_fast_mode(void) // set temp MMIO base volatile u32 *spi_base = (void *)0xa0000000; - u32 save = pci_io_read_config32(dev, 0xa0); - pci_io_write_config32(dev, 0xa0, (u32) spi_base | 2); + u32 save = pci_s_read_config32(dev, 0xa0); + pci_s_write_config32(dev, 0xa0, (u32) spi_base | 2); // early enable of SPI 33 MHz fast mode read dword = spi_base[3]; spi_base[3] = (dword & ~(3 << 14)) | (1 << 14); spi_base[0] = spi_base[0] | (1 << 18); // fast read enable - pci_io_write_config32(dev, 0xa0, save); + pci_s_write_config32(dev, 0xa0, save); } static void enable_clocks(void) diff --git a/src/southbridge/amd/pi/hudson/bootblock.c b/src/southbridge/amd/pi/hudson/bootblock.c index 77a4570830..6b7595fc0e 100644 --- a/src/southbridge/amd/pi/hudson/bootblock.c +++ b/src/southbridge/amd/pi/hudson/bootblock.c @@ -36,15 +36,15 @@ static void hudson_enable_rom(void) dev = PCI_DEV(0, 0x14, 3); /* Decode variable LPC ROM address ranges 1 and 2. */ - reg8 = pci_io_read_config8(dev, 0x48); + reg8 = pci_s_read_config8(dev, 0x48); reg8 |= (1 << 3) | (1 << 4); - pci_io_write_config8(dev, 0x48, reg8); + pci_s_write_config8(dev, 0x48, reg8); /* LPC ROM address range 1: */ /* Enable LPC ROM range mirroring start at 0x000e(0000). */ - pci_io_write_config16(dev, 0x68, 0x000e); + pci_s_write_config16(dev, 0x68, 0x000e); /* Enable LPC ROM range mirroring end at 0x000f(ffff). */ - pci_io_write_config16(dev, 0x6a, 0x000f); + pci_s_write_config16(dev, 0x6a, 0x000f); /* LPC ROM address range 2: */ /* @@ -54,9 +54,9 @@ static void hudson_enable_rom(void) * 0xffe0(0000): 2MB * 0xffc0(0000): 4MB */ - pci_io_write_config16(dev, 0x6c, 0x10000 - (CONFIG_COREBOOT_ROMSIZE_KB >> 6)); + pci_s_write_config16(dev, 0x6c, 0x10000 - (CONFIG_COREBOOT_ROMSIZE_KB >> 6)); /* Enable LPC ROM range end at 0xffff(ffff). */ - pci_io_write_config16(dev, 0x6e, 0xffff); + pci_s_write_config16(dev, 0x6e, 0xffff); } void bootblock_early_southbridge_init(void) From 0142d441c63a9bb1a7955ea0ba764a2ddbc38d48 Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Thu, 19 Dec 2019 22:55:30 +0100 Subject: [PATCH 0811/1242] mb/**/dsdt.asl: Remove "Some generic macros" comment It provides no useful information, so it might as well vanish. Change-Id: I0df6f4639a16058486c2e2d40fe4067d65670731 Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/37856 Tested-by: build bot (Jenkins) Reviewed-by: Frans Hendriks Reviewed-by: Wim Vervoorn Reviewed-by: Werner Zeh --- src/mainboard/apple/macbook21/dsdt.asl | 1 - src/mainboard/apple/macbookair4_2/dsdt.asl | 1 - src/mainboard/asrock/b75pro3-m/dsdt.asl | 1 - src/mainboard/asus/h61m-cs/dsdt.asl | 1 - src/mainboard/asus/p5gc-mx/dsdt.asl | 1 - src/mainboard/asus/p8h61-m_pro/dsdt.asl | 1 - src/mainboard/compulab/intense_pc/dsdt.asl | 1 - src/mainboard/facebook/fbg1701/dsdt.asl | 1 - src/mainboard/facebook/monolith/dsdt.asl | 1 - src/mainboard/getac/p470/dsdt.asl | 1 - src/mainboard/gigabyte/ga-945gcm-s2l/dsdt.asl | 1 - src/mainboard/gigabyte/ga-b75m-d3h/dsdt.asl | 1 - src/mainboard/google/auron/dsdt.asl | 1 - src/mainboard/google/beltino/dsdt.asl | 1 - src/mainboard/google/butterfly/dsdt.asl | 1 - src/mainboard/google/cyan/dsdt.asl | 1 - src/mainboard/google/dragonegg/dsdt.asl | 1 - src/mainboard/google/drallion/dsdt.asl | 1 - src/mainboard/google/eve/dsdt.asl | 1 - src/mainboard/google/fizz/dsdt.asl | 1 - src/mainboard/google/glados/dsdt.asl | 1 - src/mainboard/google/hatch/dsdt.asl | 1 - src/mainboard/google/jecht/dsdt.asl | 1 - src/mainboard/google/link/dsdt.asl | 1 - src/mainboard/google/parrot/dsdt.asl | 1 - src/mainboard/google/poppy/dsdt.asl | 1 - src/mainboard/google/rambi/dsdt.asl | 1 - src/mainboard/google/sarien/dsdt.asl | 1 - src/mainboard/google/slippy/dsdt.asl | 1 - src/mainboard/google/stout/dsdt.asl | 1 - src/mainboard/hp/2570p/dsdt.asl | 1 - src/mainboard/hp/2760p/dsdt.asl | 1 - src/mainboard/hp/8460p/dsdt.asl | 1 - src/mainboard/hp/8470p/dsdt.asl | 1 - src/mainboard/hp/8770w/dsdt.asl | 1 - src/mainboard/hp/compaq_8200_elite_sff/dsdt.asl | 1 - src/mainboard/hp/folio_9470m/dsdt.asl | 1 - src/mainboard/hp/revolve_810_g1/dsdt.asl | 1 - src/mainboard/hp/z220_sff_workstation/dsdt.asl | 1 - src/mainboard/ibase/mb899/dsdt.asl | 1 - src/mainboard/intel/baskingridge/dsdt.asl | 1 - src/mainboard/intel/cannonlake_rvp/dsdt.asl | 1 - src/mainboard/intel/coffeelake_rvp/dsdt.asl | 1 - src/mainboard/intel/d945gclf/dsdt.asl | 1 - src/mainboard/intel/dcp847ske/dsdt.asl | 1 - src/mainboard/intel/emeraldlake2/dsdt.asl | 1 - src/mainboard/intel/harcuvar/dsdt.asl | 1 - src/mainboard/intel/icelake_rvp/dsdt.asl | 1 - src/mainboard/intel/kblrvp/dsdt.asl | 1 - src/mainboard/intel/kunimitsu/dsdt.asl | 1 - src/mainboard/intel/saddlebrook/dsdt.asl | 1 - src/mainboard/intel/strago/dsdt.asl | 1 - src/mainboard/intel/wtm2/dsdt.asl | 2 +- src/mainboard/kontron/986lcd-m/dsdt.asl | 1 - src/mainboard/kontron/ktqm77/dsdt.asl | 1 - src/mainboard/lenovo/l520/dsdt.asl | 1 - src/mainboard/lenovo/t400/dsdt.asl | 1 - src/mainboard/lenovo/t410/dsdt.asl | 1 - src/mainboard/lenovo/t420/dsdt.asl | 1 - src/mainboard/lenovo/t420s/dsdt.asl | 1 - src/mainboard/lenovo/t430/dsdt.asl | 1 - src/mainboard/lenovo/t430s/dsdt.asl | 1 - src/mainboard/lenovo/t520/dsdt.asl | 1 - src/mainboard/lenovo/t530/dsdt.asl | 1 - src/mainboard/lenovo/t60/dsdt.asl | 1 - src/mainboard/lenovo/x131e/dsdt.asl | 1 - src/mainboard/lenovo/x1_carbon_gen1/dsdt.asl | 1 - src/mainboard/lenovo/x200/dsdt.asl | 1 - src/mainboard/lenovo/x201/dsdt.asl | 1 - src/mainboard/lenovo/x220/dsdt.asl | 1 - src/mainboard/lenovo/x230/dsdt.asl | 1 - src/mainboard/lenovo/x60/dsdt.asl | 1 - src/mainboard/msi/ms7707/dsdt.asl | 1 - src/mainboard/packardbell/ms2290/dsdt.asl | 1 - src/mainboard/portwell/m107/dsdt.asl | 1 - src/mainboard/purism/librem_bdw/dsdt.asl | 1 - src/mainboard/purism/librem_skl/dsdt.asl | 1 - src/mainboard/roda/rk886ex/dsdt.asl | 1 - src/mainboard/roda/rk9/dsdt.asl | 1 - src/mainboard/roda/rv11/dsdt.asl | 1 - src/mainboard/samsung/lumpy/dsdt.asl | 1 - src/mainboard/samsung/stumpy/dsdt.asl | 1 - src/mainboard/sapphire/pureplatinumh61/dsdt.asl | 1 - src/mainboard/scaleway/tagada/dsdt.asl | 1 - src/mainboard/siemens/mc_apl1/dsdt.asl | 1 - src/mainboard/supermicro/x11-lga1151-series/dsdt.asl | 1 - 86 files changed, 1 insertion(+), 86 deletions(-) diff --git a/src/mainboard/apple/macbook21/dsdt.asl b/src/mainboard/apple/macbook21/dsdt.asl index 40af217c47..7968c6e199 100644 --- a/src/mainboard/apple/macbook21/dsdt.asl +++ b/src/mainboard/apple/macbook21/dsdt.asl @@ -28,7 +28,6 @@ DefinitionBlock( 0x20090419 // OEM revision ) { - // Some generic macros #include "acpi/platform.asl" // global NVS and variables diff --git a/src/mainboard/apple/macbookair4_2/dsdt.asl b/src/mainboard/apple/macbookair4_2/dsdt.asl index 91e0b2087f..f48d0dd239 100644 --- a/src/mainboard/apple/macbookair4_2/dsdt.asl +++ b/src/mainboard/apple/macbookair4_2/dsdt.asl @@ -24,7 +24,6 @@ DefinitionBlock( 0x20141018 // OEM revision ) { - // Some generic macros #include "acpi/platform.asl" #include #include diff --git a/src/mainboard/asrock/b75pro3-m/dsdt.asl b/src/mainboard/asrock/b75pro3-m/dsdt.asl index e1b28db377..86b29d6a7c 100644 --- a/src/mainboard/asrock/b75pro3-m/dsdt.asl +++ b/src/mainboard/asrock/b75pro3-m/dsdt.asl @@ -27,7 +27,6 @@ DefinitionBlock( 0x20141018 // OEM revision ) { - // Some generic macros #include "acpi/platform.asl" #include #include diff --git a/src/mainboard/asus/h61m-cs/dsdt.asl b/src/mainboard/asus/h61m-cs/dsdt.asl index dc7a3674ae..8a052a321c 100644 --- a/src/mainboard/asus/h61m-cs/dsdt.asl +++ b/src/mainboard/asus/h61m-cs/dsdt.asl @@ -24,7 +24,6 @@ DefinitionBlock( 0x20141018 // OEM revision ) { - // Some generic macros #include "acpi/platform.asl" #include #include diff --git a/src/mainboard/asus/p5gc-mx/dsdt.asl b/src/mainboard/asus/p5gc-mx/dsdt.asl index 66f0efe49d..1c360f9aea 100644 --- a/src/mainboard/asus/p5gc-mx/dsdt.asl +++ b/src/mainboard/asus/p5gc-mx/dsdt.asl @@ -23,7 +23,6 @@ DefinitionBlock( 0x20090419 // OEM revision ) { - // Some generic macros /* #include "acpi/platform.asl" */ // global NVS and variables diff --git a/src/mainboard/asus/p8h61-m_pro/dsdt.asl b/src/mainboard/asus/p8h61-m_pro/dsdt.asl index c2b46f333b..e8ff31143e 100644 --- a/src/mainboard/asus/p8h61-m_pro/dsdt.asl +++ b/src/mainboard/asus/p8h61-m_pro/dsdt.asl @@ -24,7 +24,6 @@ DefinitionBlock( 0x20141018 // OEM revision ) { - // Some generic macros #include "acpi/platform.asl" #include "acpi/superio.asl" #include diff --git a/src/mainboard/compulab/intense_pc/dsdt.asl b/src/mainboard/compulab/intense_pc/dsdt.asl index 4e4351670b..f769a0fe43 100644 --- a/src/mainboard/compulab/intense_pc/dsdt.asl +++ b/src/mainboard/compulab/intense_pc/dsdt.asl @@ -27,7 +27,6 @@ DefinitionBlock( 0x20141018 // OEM revision ) { - // Some generic macros #include "acpi/platform.asl" #include #include diff --git a/src/mainboard/facebook/fbg1701/dsdt.asl b/src/mainboard/facebook/fbg1701/dsdt.asl index 518e249197..9b4dc817bf 100644 --- a/src/mainboard/facebook/fbg1701/dsdt.asl +++ b/src/mainboard/facebook/fbg1701/dsdt.asl @@ -29,7 +29,6 @@ DefinitionBlock( 0x20110725 /* OEM revision */ ) { - /* Some generic macros */ #include /* global NVS and variables */ diff --git a/src/mainboard/facebook/monolith/dsdt.asl b/src/mainboard/facebook/monolith/dsdt.asl index 2f00110e8a..8fea1d511a 100644 --- a/src/mainboard/facebook/monolith/dsdt.asl +++ b/src/mainboard/facebook/monolith/dsdt.asl @@ -26,7 +26,6 @@ DefinitionBlock( 0x20110725 // OEM revision ) { - // Some generic macros #include // global NVS and variables diff --git a/src/mainboard/getac/p470/dsdt.asl b/src/mainboard/getac/p470/dsdt.asl index 4e75968f91..9be21ad38a 100644 --- a/src/mainboard/getac/p470/dsdt.asl +++ b/src/mainboard/getac/p470/dsdt.asl @@ -29,7 +29,6 @@ DefinitionBlock( { #include - // Some generic macros #include "acpi/platform.asl" // global NVS and variables diff --git a/src/mainboard/gigabyte/ga-945gcm-s2l/dsdt.asl b/src/mainboard/gigabyte/ga-945gcm-s2l/dsdt.asl index afc53861bb..7d0ffe046d 100644 --- a/src/mainboard/gigabyte/ga-945gcm-s2l/dsdt.asl +++ b/src/mainboard/gigabyte/ga-945gcm-s2l/dsdt.asl @@ -23,7 +23,6 @@ DefinitionBlock( 0x20090419 // OEM revision ) { - // Some generic macros #include "acpi/platform.asl" // global NVS and variables diff --git a/src/mainboard/gigabyte/ga-b75m-d3h/dsdt.asl b/src/mainboard/gigabyte/ga-b75m-d3h/dsdt.asl index 8b81ebff61..47b2725cd7 100644 --- a/src/mainboard/gigabyte/ga-b75m-d3h/dsdt.asl +++ b/src/mainboard/gigabyte/ga-b75m-d3h/dsdt.asl @@ -23,7 +23,6 @@ DefinitionBlock( { #include - // Some generic macros #include "acpi/mainboard.asl" #include "acpi/platform.asl" #include "acpi/thermal.asl" diff --git a/src/mainboard/google/auron/dsdt.asl b/src/mainboard/google/auron/dsdt.asl index 9a5dcc7826..b463214547 100644 --- a/src/mainboard/google/auron/dsdt.asl +++ b/src/mainboard/google/auron/dsdt.asl @@ -24,7 +24,6 @@ DefinitionBlock( 0x20110725 // OEM revision ) { - // Some generic macros #include // Thermal handler diff --git a/src/mainboard/google/beltino/dsdt.asl b/src/mainboard/google/beltino/dsdt.asl index 7b369d8fd7..447ea02150 100644 --- a/src/mainboard/google/beltino/dsdt.asl +++ b/src/mainboard/google/beltino/dsdt.asl @@ -24,7 +24,6 @@ DefinitionBlock( 0x20110725 // OEM revision ) { - // Some generic macros #include "acpi/platform.asl" // Thermal handler diff --git a/src/mainboard/google/butterfly/dsdt.asl b/src/mainboard/google/butterfly/dsdt.asl index 8a9d71b560..ad9b77b5f7 100644 --- a/src/mainboard/google/butterfly/dsdt.asl +++ b/src/mainboard/google/butterfly/dsdt.asl @@ -26,7 +26,6 @@ DefinitionBlock( { #include - // Some generic macros #include "acpi/platform.asl" #include "acpi/mainboard.asl" diff --git a/src/mainboard/google/cyan/dsdt.asl b/src/mainboard/google/cyan/dsdt.asl index 7aa62f8fb4..53a92e0a41 100644 --- a/src/mainboard/google/cyan/dsdt.asl +++ b/src/mainboard/google/cyan/dsdt.asl @@ -25,7 +25,6 @@ DefinitionBlock( 0x20110725 /* OEM revision */ ) { - /* Some generic macros */ #include /* global NVS and variables */ diff --git a/src/mainboard/google/dragonegg/dsdt.asl b/src/mainboard/google/dragonegg/dsdt.asl index 4318dc35f3..cb2ce64a78 100644 --- a/src/mainboard/google/dragonegg/dsdt.asl +++ b/src/mainboard/google/dragonegg/dsdt.asl @@ -26,7 +26,6 @@ DefinitionBlock( 0x20110725 // OEM revision ) { - // Some generic macros #include // global NVS and variables diff --git a/src/mainboard/google/drallion/dsdt.asl b/src/mainboard/google/drallion/dsdt.asl index 0a092cff0f..92470a925b 100644 --- a/src/mainboard/google/drallion/dsdt.asl +++ b/src/mainboard/google/drallion/dsdt.asl @@ -25,7 +25,6 @@ DefinitionBlock( 0x20110725 /* OEM revision */ ) { - /* Some generic macros */ #include /* global NVS and variables */ diff --git a/src/mainboard/google/eve/dsdt.asl b/src/mainboard/google/eve/dsdt.asl index 3e9d570705..90463c85aa 100644 --- a/src/mainboard/google/eve/dsdt.asl +++ b/src/mainboard/google/eve/dsdt.asl @@ -26,7 +26,6 @@ DefinitionBlock( 0x20110725 // OEM revision ) { - /* Some generic macros */ #include /* global NVS and variables */ diff --git a/src/mainboard/google/fizz/dsdt.asl b/src/mainboard/google/fizz/dsdt.asl index 44d544c378..613fe31b26 100644 --- a/src/mainboard/google/fizz/dsdt.asl +++ b/src/mainboard/google/fizz/dsdt.asl @@ -26,7 +26,6 @@ DefinitionBlock( 0x20110725 // OEM revision ) { - /* Some generic macros */ #include /* global NVS and variables */ diff --git a/src/mainboard/google/glados/dsdt.asl b/src/mainboard/google/glados/dsdt.asl index 6dab56ea77..06209e4141 100644 --- a/src/mainboard/google/glados/dsdt.asl +++ b/src/mainboard/google/glados/dsdt.asl @@ -25,7 +25,6 @@ DefinitionBlock( 0x20110725 // OEM revision ) { - // Some generic macros #include // global NVS and variables diff --git a/src/mainboard/google/hatch/dsdt.asl b/src/mainboard/google/hatch/dsdt.asl index 62478293f3..1e7f760a7b 100644 --- a/src/mainboard/google/hatch/dsdt.asl +++ b/src/mainboard/google/hatch/dsdt.asl @@ -26,7 +26,6 @@ DefinitionBlock( 0x20110725 /* OEM revision */ ) { - /* Some generic macros */ #include /* global NVS and variables */ diff --git a/src/mainboard/google/jecht/dsdt.asl b/src/mainboard/google/jecht/dsdt.asl index fb8abe7e90..1cd2bd3e57 100644 --- a/src/mainboard/google/jecht/dsdt.asl +++ b/src/mainboard/google/jecht/dsdt.asl @@ -24,7 +24,6 @@ DefinitionBlock( 0x20110725 // OEM revision ) { - // Some generic macros #include #include "acpi/platform.asl" diff --git a/src/mainboard/google/link/dsdt.asl b/src/mainboard/google/link/dsdt.asl index 4c23e7dd0c..b39631909e 100644 --- a/src/mainboard/google/link/dsdt.asl +++ b/src/mainboard/google/link/dsdt.asl @@ -26,7 +26,6 @@ DefinitionBlock( { #include - // Some generic macros #include "acpi/platform.asl" #include "acpi/mainboard.asl" diff --git a/src/mainboard/google/parrot/dsdt.asl b/src/mainboard/google/parrot/dsdt.asl index 0465ceda26..a7623265c7 100644 --- a/src/mainboard/google/parrot/dsdt.asl +++ b/src/mainboard/google/parrot/dsdt.asl @@ -26,7 +26,6 @@ DefinitionBlock( { #include - // Some generic macros #include "acpi/platform.asl" // Thermal handler diff --git a/src/mainboard/google/poppy/dsdt.asl b/src/mainboard/google/poppy/dsdt.asl index 7e0eb9ae08..ce2f8fc43d 100644 --- a/src/mainboard/google/poppy/dsdt.asl +++ b/src/mainboard/google/poppy/dsdt.asl @@ -26,7 +26,6 @@ DefinitionBlock( 0x20110725 // OEM revision ) { - /* Some generic macros */ #include /* global NVS and variables */ diff --git a/src/mainboard/google/rambi/dsdt.asl b/src/mainboard/google/rambi/dsdt.asl index 2393830d13..ed57e43131 100644 --- a/src/mainboard/google/rambi/dsdt.asl +++ b/src/mainboard/google/rambi/dsdt.asl @@ -26,7 +26,6 @@ DefinitionBlock( 0x20110725 // OEM revision ) { - // Some generic macros #include // global NVS and variables diff --git a/src/mainboard/google/sarien/dsdt.asl b/src/mainboard/google/sarien/dsdt.asl index 9a5c787a25..99a8627853 100644 --- a/src/mainboard/google/sarien/dsdt.asl +++ b/src/mainboard/google/sarien/dsdt.asl @@ -25,7 +25,6 @@ DefinitionBlock( 0x20110725 /* OEM revision */ ) { - /* Some generic macros */ #include /* global NVS and variables */ diff --git a/src/mainboard/google/slippy/dsdt.asl b/src/mainboard/google/slippy/dsdt.asl index 6c45ea95aa..9881a5ff8c 100644 --- a/src/mainboard/google/slippy/dsdt.asl +++ b/src/mainboard/google/slippy/dsdt.asl @@ -24,7 +24,6 @@ DefinitionBlock( 0x20110725 // OEM revision ) { - // Some generic macros #include "acpi/platform.asl" // Thermal handler diff --git a/src/mainboard/google/stout/dsdt.asl b/src/mainboard/google/stout/dsdt.asl index 580ca1606d..a62fed2380 100644 --- a/src/mainboard/google/stout/dsdt.asl +++ b/src/mainboard/google/stout/dsdt.asl @@ -27,7 +27,6 @@ DefinitionBlock( { #include - // Some generic macros #include "acpi/platform.asl" #include "acpi/mainboard.asl" diff --git a/src/mainboard/hp/2570p/dsdt.asl b/src/mainboard/hp/2570p/dsdt.asl index 5730ea083e..81f45c155e 100644 --- a/src/mainboard/hp/2570p/dsdt.asl +++ b/src/mainboard/hp/2570p/dsdt.asl @@ -26,7 +26,6 @@ DefinitionBlock( 0x20141018 // OEM revision ) { - // Some generic macros #include "acpi/platform.asl" #include #include diff --git a/src/mainboard/hp/2760p/dsdt.asl b/src/mainboard/hp/2760p/dsdt.asl index 5730ea083e..81f45c155e 100644 --- a/src/mainboard/hp/2760p/dsdt.asl +++ b/src/mainboard/hp/2760p/dsdt.asl @@ -26,7 +26,6 @@ DefinitionBlock( 0x20141018 // OEM revision ) { - // Some generic macros #include "acpi/platform.asl" #include #include diff --git a/src/mainboard/hp/8460p/dsdt.asl b/src/mainboard/hp/8460p/dsdt.asl index 5730ea083e..81f45c155e 100644 --- a/src/mainboard/hp/8460p/dsdt.asl +++ b/src/mainboard/hp/8460p/dsdt.asl @@ -26,7 +26,6 @@ DefinitionBlock( 0x20141018 // OEM revision ) { - // Some generic macros #include "acpi/platform.asl" #include #include diff --git a/src/mainboard/hp/8470p/dsdt.asl b/src/mainboard/hp/8470p/dsdt.asl index 5730ea083e..81f45c155e 100644 --- a/src/mainboard/hp/8470p/dsdt.asl +++ b/src/mainboard/hp/8470p/dsdt.asl @@ -26,7 +26,6 @@ DefinitionBlock( 0x20141018 // OEM revision ) { - // Some generic macros #include "acpi/platform.asl" #include #include diff --git a/src/mainboard/hp/8770w/dsdt.asl b/src/mainboard/hp/8770w/dsdt.asl index 5730ea083e..81f45c155e 100644 --- a/src/mainboard/hp/8770w/dsdt.asl +++ b/src/mainboard/hp/8770w/dsdt.asl @@ -26,7 +26,6 @@ DefinitionBlock( 0x20141018 // OEM revision ) { - // Some generic macros #include "acpi/platform.asl" #include #include diff --git a/src/mainboard/hp/compaq_8200_elite_sff/dsdt.asl b/src/mainboard/hp/compaq_8200_elite_sff/dsdt.asl index 3f249e35a5..9bb96146ae 100644 --- a/src/mainboard/hp/compaq_8200_elite_sff/dsdt.asl +++ b/src/mainboard/hp/compaq_8200_elite_sff/dsdt.asl @@ -26,7 +26,6 @@ DefinitionBlock( 0x20141018 // OEM revision ) { - // Some generic macros #include "acpi/platform.asl" #include #include diff --git a/src/mainboard/hp/folio_9470m/dsdt.asl b/src/mainboard/hp/folio_9470m/dsdt.asl index 5730ea083e..81f45c155e 100644 --- a/src/mainboard/hp/folio_9470m/dsdt.asl +++ b/src/mainboard/hp/folio_9470m/dsdt.asl @@ -26,7 +26,6 @@ DefinitionBlock( 0x20141018 // OEM revision ) { - // Some generic macros #include "acpi/platform.asl" #include #include diff --git a/src/mainboard/hp/revolve_810_g1/dsdt.asl b/src/mainboard/hp/revolve_810_g1/dsdt.asl index 5730ea083e..81f45c155e 100644 --- a/src/mainboard/hp/revolve_810_g1/dsdt.asl +++ b/src/mainboard/hp/revolve_810_g1/dsdt.asl @@ -26,7 +26,6 @@ DefinitionBlock( 0x20141018 // OEM revision ) { - // Some generic macros #include "acpi/platform.asl" #include #include diff --git a/src/mainboard/hp/z220_sff_workstation/dsdt.asl b/src/mainboard/hp/z220_sff_workstation/dsdt.asl index 3f249e35a5..9bb96146ae 100644 --- a/src/mainboard/hp/z220_sff_workstation/dsdt.asl +++ b/src/mainboard/hp/z220_sff_workstation/dsdt.asl @@ -26,7 +26,6 @@ DefinitionBlock( 0x20141018 // OEM revision ) { - // Some generic macros #include "acpi/platform.asl" #include #include diff --git a/src/mainboard/ibase/mb899/dsdt.asl b/src/mainboard/ibase/mb899/dsdt.asl index 31b67a73d5..45cc48ff9a 100644 --- a/src/mainboard/ibase/mb899/dsdt.asl +++ b/src/mainboard/ibase/mb899/dsdt.asl @@ -23,7 +23,6 @@ DefinitionBlock( 0x20090419 // OEM revision ) { - // Some generic macros #include "acpi/platform.asl" // global NVS and variables diff --git a/src/mainboard/intel/baskingridge/dsdt.asl b/src/mainboard/intel/baskingridge/dsdt.asl index 28d743e598..066160d3e1 100644 --- a/src/mainboard/intel/baskingridge/dsdt.asl +++ b/src/mainboard/intel/baskingridge/dsdt.asl @@ -26,7 +26,6 @@ DefinitionBlock( 0x20110725 // OEM revision ) { - // Some generic macros #include "acpi/platform.asl" // global NVS and variables diff --git a/src/mainboard/intel/cannonlake_rvp/dsdt.asl b/src/mainboard/intel/cannonlake_rvp/dsdt.asl index 9a519c0b39..4fe13d44f6 100644 --- a/src/mainboard/intel/cannonlake_rvp/dsdt.asl +++ b/src/mainboard/intel/cannonlake_rvp/dsdt.asl @@ -25,7 +25,6 @@ DefinitionBlock( 0x20110725 // OEM revision ) { - // Some generic macros #include // global NVS and variables diff --git a/src/mainboard/intel/coffeelake_rvp/dsdt.asl b/src/mainboard/intel/coffeelake_rvp/dsdt.asl index 1d7216aecc..10418c3e64 100644 --- a/src/mainboard/intel/coffeelake_rvp/dsdt.asl +++ b/src/mainboard/intel/coffeelake_rvp/dsdt.asl @@ -25,7 +25,6 @@ DefinitionBlock( 0x20110725 // OEM revision ) { - // Some generic macros #include // global NVS and variables diff --git a/src/mainboard/intel/d945gclf/dsdt.asl b/src/mainboard/intel/d945gclf/dsdt.asl index afc53861bb..7d0ffe046d 100644 --- a/src/mainboard/intel/d945gclf/dsdt.asl +++ b/src/mainboard/intel/d945gclf/dsdt.asl @@ -23,7 +23,6 @@ DefinitionBlock( 0x20090419 // OEM revision ) { - // Some generic macros #include "acpi/platform.asl" // global NVS and variables diff --git a/src/mainboard/intel/dcp847ske/dsdt.asl b/src/mainboard/intel/dcp847ske/dsdt.asl index 39e7008759..3ef27ebe3d 100644 --- a/src/mainboard/intel/dcp847ske/dsdt.asl +++ b/src/mainboard/intel/dcp847ske/dsdt.asl @@ -24,7 +24,6 @@ DefinitionBlock( 0x20141018 // OEM revision ) { - // Some generic macros #include "acpi/platform.asl" #include #include diff --git a/src/mainboard/intel/emeraldlake2/dsdt.asl b/src/mainboard/intel/emeraldlake2/dsdt.asl index 74268ef60a..a27f21292c 100644 --- a/src/mainboard/intel/emeraldlake2/dsdt.asl +++ b/src/mainboard/intel/emeraldlake2/dsdt.asl @@ -26,7 +26,6 @@ DefinitionBlock( { #include - // Some generic macros #include "acpi/platform.asl" // Thermal handler diff --git a/src/mainboard/intel/harcuvar/dsdt.asl b/src/mainboard/intel/harcuvar/dsdt.asl index c7e7f7c91b..bd32687cb8 100644 --- a/src/mainboard/intel/harcuvar/dsdt.asl +++ b/src/mainboard/intel/harcuvar/dsdt.asl @@ -26,7 +26,6 @@ DefinitionBlock( 0x20110725 // OEM revision ) { - // Some generic macros #include #include "acpi/platform.asl" #include "acpi/mainboard.asl" diff --git a/src/mainboard/intel/icelake_rvp/dsdt.asl b/src/mainboard/intel/icelake_rvp/dsdt.asl index f8fcd4d88c..3fd6fcae24 100644 --- a/src/mainboard/intel/icelake_rvp/dsdt.asl +++ b/src/mainboard/intel/icelake_rvp/dsdt.asl @@ -26,7 +26,6 @@ DefinitionBlock( 0x20110725 // OEM revision ) { - // Some generic macros #include // global NVS and variables diff --git a/src/mainboard/intel/kblrvp/dsdt.asl b/src/mainboard/intel/kblrvp/dsdt.asl index 059bcd54c3..84872cb62d 100644 --- a/src/mainboard/intel/kblrvp/dsdt.asl +++ b/src/mainboard/intel/kblrvp/dsdt.asl @@ -25,7 +25,6 @@ DefinitionBlock( 0x20110725 // OEM revision ) { - // Some generic macros #include // global NVS and variables diff --git a/src/mainboard/intel/kunimitsu/dsdt.asl b/src/mainboard/intel/kunimitsu/dsdt.asl index 6dab56ea77..06209e4141 100644 --- a/src/mainboard/intel/kunimitsu/dsdt.asl +++ b/src/mainboard/intel/kunimitsu/dsdt.asl @@ -25,7 +25,6 @@ DefinitionBlock( 0x20110725 // OEM revision ) { - // Some generic macros #include // global NVS and variables diff --git a/src/mainboard/intel/saddlebrook/dsdt.asl b/src/mainboard/intel/saddlebrook/dsdt.asl index 86ea299aa9..b88b1d20f4 100644 --- a/src/mainboard/intel/saddlebrook/dsdt.asl +++ b/src/mainboard/intel/saddlebrook/dsdt.asl @@ -25,7 +25,6 @@ DefinitionBlock( 0x20110725 // OEM revision ) { - // Some generic macros #include // global NVS and variables diff --git a/src/mainboard/intel/strago/dsdt.asl b/src/mainboard/intel/strago/dsdt.asl index e89b88797f..7bbe1e407c 100644 --- a/src/mainboard/intel/strago/dsdt.asl +++ b/src/mainboard/intel/strago/dsdt.asl @@ -25,7 +25,6 @@ DefinitionBlock( 0x20110725 /* OEM revision */ ) { - /* Some generic macros */ #include /* global NVS and variables */ diff --git a/src/mainboard/intel/wtm2/dsdt.asl b/src/mainboard/intel/wtm2/dsdt.asl index d3febf511e..7245983ba0 100644 --- a/src/mainboard/intel/wtm2/dsdt.asl +++ b/src/mainboard/intel/wtm2/dsdt.asl @@ -27,7 +27,7 @@ DefinitionBlock( ) { #include - // Some generic macros + #include "acpi/platform.asl" // global NVS and variables diff --git a/src/mainboard/kontron/986lcd-m/dsdt.asl b/src/mainboard/kontron/986lcd-m/dsdt.asl index d4ffd7ba4c..a6ae2843fe 100644 --- a/src/mainboard/kontron/986lcd-m/dsdt.asl +++ b/src/mainboard/kontron/986lcd-m/dsdt.asl @@ -23,7 +23,6 @@ DefinitionBlock( 0x20090419 // OEM revision ) { - // Some generic macros #include "acpi/platform.asl" // global NVS and variables diff --git a/src/mainboard/kontron/ktqm77/dsdt.asl b/src/mainboard/kontron/ktqm77/dsdt.asl index 2d6ce7953b..da533b789e 100644 --- a/src/mainboard/kontron/ktqm77/dsdt.asl +++ b/src/mainboard/kontron/ktqm77/dsdt.asl @@ -26,7 +26,6 @@ DefinitionBlock( { #include - // Some generic macros #include "acpi/platform.asl" #include "acpi/mainboard.asl" diff --git a/src/mainboard/lenovo/l520/dsdt.asl b/src/mainboard/lenovo/l520/dsdt.asl index 8b2c3e6005..4fefb5e6de 100644 --- a/src/mainboard/lenovo/l520/dsdt.asl +++ b/src/mainboard/lenovo/l520/dsdt.asl @@ -27,7 +27,6 @@ DefinitionBlock( 0x20141018 // OEM revision ) { - // Some generic macros #include "acpi/platform.asl" #include #include diff --git a/src/mainboard/lenovo/t400/dsdt.asl b/src/mainboard/lenovo/t400/dsdt.asl index eb9c2adf53..c3c7dda6ae 100644 --- a/src/mainboard/lenovo/t400/dsdt.asl +++ b/src/mainboard/lenovo/t400/dsdt.asl @@ -30,7 +30,6 @@ DefinitionBlock( 0x20090419 // OEM revision ) { - // Some generic macros #include "acpi/platform.asl" // global NVS and variables diff --git a/src/mainboard/lenovo/t410/dsdt.asl b/src/mainboard/lenovo/t410/dsdt.asl index 9d0204e5cc..bf00489e80 100644 --- a/src/mainboard/lenovo/t410/dsdt.asl +++ b/src/mainboard/lenovo/t410/dsdt.asl @@ -32,7 +32,6 @@ DefinitionBlock( { #include - /* Some generic macros */ #include "acpi/platform.asl" /* global NVS and variables */ diff --git a/src/mainboard/lenovo/t420/dsdt.asl b/src/mainboard/lenovo/t420/dsdt.asl index a6a57e256e..b8418179b4 100644 --- a/src/mainboard/lenovo/t420/dsdt.asl +++ b/src/mainboard/lenovo/t420/dsdt.asl @@ -33,7 +33,6 @@ DefinitionBlock( { #include - // Some generic macros #include "acpi/platform.asl" // global NVS and variables diff --git a/src/mainboard/lenovo/t420s/dsdt.asl b/src/mainboard/lenovo/t420s/dsdt.asl index a6a57e256e..b8418179b4 100644 --- a/src/mainboard/lenovo/t420s/dsdt.asl +++ b/src/mainboard/lenovo/t420s/dsdt.asl @@ -33,7 +33,6 @@ DefinitionBlock( { #include - // Some generic macros #include "acpi/platform.asl" // global NVS and variables diff --git a/src/mainboard/lenovo/t430/dsdt.asl b/src/mainboard/lenovo/t430/dsdt.asl index 55781d6b5f..68f91e9014 100644 --- a/src/mainboard/lenovo/t430/dsdt.asl +++ b/src/mainboard/lenovo/t430/dsdt.asl @@ -31,7 +31,6 @@ DefinitionBlock( 0x20141018 // OEM revision ) { - // Some generic macros #include "acpi/platform.asl" #include #include diff --git a/src/mainboard/lenovo/t430s/dsdt.asl b/src/mainboard/lenovo/t430s/dsdt.asl index a6a57e256e..b8418179b4 100644 --- a/src/mainboard/lenovo/t430s/dsdt.asl +++ b/src/mainboard/lenovo/t430s/dsdt.asl @@ -33,7 +33,6 @@ DefinitionBlock( { #include - // Some generic macros #include "acpi/platform.asl" // global NVS and variables diff --git a/src/mainboard/lenovo/t520/dsdt.asl b/src/mainboard/lenovo/t520/dsdt.asl index a6a57e256e..b8418179b4 100644 --- a/src/mainboard/lenovo/t520/dsdt.asl +++ b/src/mainboard/lenovo/t520/dsdt.asl @@ -33,7 +33,6 @@ DefinitionBlock( { #include - // Some generic macros #include "acpi/platform.asl" // global NVS and variables diff --git a/src/mainboard/lenovo/t530/dsdt.asl b/src/mainboard/lenovo/t530/dsdt.asl index a6a57e256e..b8418179b4 100644 --- a/src/mainboard/lenovo/t530/dsdt.asl +++ b/src/mainboard/lenovo/t530/dsdt.asl @@ -33,7 +33,6 @@ DefinitionBlock( { #include - // Some generic macros #include "acpi/platform.asl" // global NVS and variables diff --git a/src/mainboard/lenovo/t60/dsdt.asl b/src/mainboard/lenovo/t60/dsdt.asl index 12923215d4..13742167e8 100644 --- a/src/mainboard/lenovo/t60/dsdt.asl +++ b/src/mainboard/lenovo/t60/dsdt.asl @@ -29,7 +29,6 @@ DefinitionBlock( 0x20090419 // OEM revision ) { - // Some generic macros #include "acpi/platform.asl" // global NVS and variables diff --git a/src/mainboard/lenovo/x131e/dsdt.asl b/src/mainboard/lenovo/x131e/dsdt.asl index 95eb2db254..842afff896 100644 --- a/src/mainboard/lenovo/x131e/dsdt.asl +++ b/src/mainboard/lenovo/x131e/dsdt.asl @@ -32,7 +32,6 @@ DefinitionBlock( 0x20141018 // OEM revision ) { - // Some generic macros #include "acpi/platform.asl" #include #include diff --git a/src/mainboard/lenovo/x1_carbon_gen1/dsdt.asl b/src/mainboard/lenovo/x1_carbon_gen1/dsdt.asl index 3acc87d33c..96f7e35cdd 100644 --- a/src/mainboard/lenovo/x1_carbon_gen1/dsdt.asl +++ b/src/mainboard/lenovo/x1_carbon_gen1/dsdt.asl @@ -33,7 +33,6 @@ DefinitionBlock( { #include - // Some generic macros #include "acpi/platform.asl" // global NVS and variables diff --git a/src/mainboard/lenovo/x200/dsdt.asl b/src/mainboard/lenovo/x200/dsdt.asl index e300234e87..9052a8f3b8 100644 --- a/src/mainboard/lenovo/x200/dsdt.asl +++ b/src/mainboard/lenovo/x200/dsdt.asl @@ -29,7 +29,6 @@ DefinitionBlock( 0x20090419 // OEM revision ) { - // Some generic macros #include "acpi/platform.asl" // global NVS and variables diff --git a/src/mainboard/lenovo/x201/dsdt.asl b/src/mainboard/lenovo/x201/dsdt.asl index 9d0204e5cc..bf00489e80 100644 --- a/src/mainboard/lenovo/x201/dsdt.asl +++ b/src/mainboard/lenovo/x201/dsdt.asl @@ -32,7 +32,6 @@ DefinitionBlock( { #include - /* Some generic macros */ #include "acpi/platform.asl" /* global NVS and variables */ diff --git a/src/mainboard/lenovo/x220/dsdt.asl b/src/mainboard/lenovo/x220/dsdt.asl index a6a57e256e..b8418179b4 100644 --- a/src/mainboard/lenovo/x220/dsdt.asl +++ b/src/mainboard/lenovo/x220/dsdt.asl @@ -33,7 +33,6 @@ DefinitionBlock( { #include - // Some generic macros #include "acpi/platform.asl" // global NVS and variables diff --git a/src/mainboard/lenovo/x230/dsdt.asl b/src/mainboard/lenovo/x230/dsdt.asl index a6a57e256e..b8418179b4 100644 --- a/src/mainboard/lenovo/x230/dsdt.asl +++ b/src/mainboard/lenovo/x230/dsdt.asl @@ -33,7 +33,6 @@ DefinitionBlock( { #include - // Some generic macros #include "acpi/platform.asl" // global NVS and variables diff --git a/src/mainboard/lenovo/x60/dsdt.asl b/src/mainboard/lenovo/x60/dsdt.asl index 00430bb62a..6f01f60052 100644 --- a/src/mainboard/lenovo/x60/dsdt.asl +++ b/src/mainboard/lenovo/x60/dsdt.asl @@ -29,7 +29,6 @@ DefinitionBlock( 0x20090419 // OEM revision ) { - // Some generic macros #include "acpi/platform.asl" // global NVS and variables diff --git a/src/mainboard/msi/ms7707/dsdt.asl b/src/mainboard/msi/ms7707/dsdt.asl index 1aa87fe332..553754d160 100644 --- a/src/mainboard/msi/ms7707/dsdt.asl +++ b/src/mainboard/msi/ms7707/dsdt.asl @@ -24,7 +24,6 @@ DefinitionBlock( 0x20141018 // OEM revision ) { - /* Some generic macros */ #include "acpi/platform.asl" #include #include diff --git a/src/mainboard/packardbell/ms2290/dsdt.asl b/src/mainboard/packardbell/ms2290/dsdt.asl index 72b7d4c78a..cbfd3a7439 100644 --- a/src/mainboard/packardbell/ms2290/dsdt.asl +++ b/src/mainboard/packardbell/ms2290/dsdt.asl @@ -26,7 +26,6 @@ DefinitionBlock( { #include - /* Some generic macros */ #include "acpi/platform.asl" /* global NVS and variables */ diff --git a/src/mainboard/portwell/m107/dsdt.asl b/src/mainboard/portwell/m107/dsdt.asl index 518e249197..9b4dc817bf 100644 --- a/src/mainboard/portwell/m107/dsdt.asl +++ b/src/mainboard/portwell/m107/dsdt.asl @@ -29,7 +29,6 @@ DefinitionBlock( 0x20110725 /* OEM revision */ ) { - /* Some generic macros */ #include /* global NVS and variables */ diff --git a/src/mainboard/purism/librem_bdw/dsdt.asl b/src/mainboard/purism/librem_bdw/dsdt.asl index 3cd4ef99ae..3a53a4db28 100644 --- a/src/mainboard/purism/librem_bdw/dsdt.asl +++ b/src/mainboard/purism/librem_bdw/dsdt.asl @@ -23,7 +23,6 @@ DefinitionBlock( 0x20160115 /* OEM revision */ ) { - /* Some generic macros */ #include /* Global NVS and variables */ diff --git a/src/mainboard/purism/librem_skl/dsdt.asl b/src/mainboard/purism/librem_skl/dsdt.asl index 1cd0531368..b058204faf 100644 --- a/src/mainboard/purism/librem_skl/dsdt.asl +++ b/src/mainboard/purism/librem_skl/dsdt.asl @@ -25,7 +25,6 @@ DefinitionBlock( 0x20110725 // OEM revision ) { - // Some generic macros #include // global NVS and variables diff --git a/src/mainboard/roda/rk886ex/dsdt.asl b/src/mainboard/roda/rk886ex/dsdt.asl index f9a2abed37..7011b44c6e 100644 --- a/src/mainboard/roda/rk886ex/dsdt.asl +++ b/src/mainboard/roda/rk886ex/dsdt.asl @@ -24,7 +24,6 @@ DefinitionBlock( 0x20090419 // OEM revision ) { - // Some generic macros #include "acpi/platform.asl" // global NVS and variables diff --git a/src/mainboard/roda/rk9/dsdt.asl b/src/mainboard/roda/rk9/dsdt.asl index e8fb13d22f..0206926ff3 100644 --- a/src/mainboard/roda/rk9/dsdt.asl +++ b/src/mainboard/roda/rk9/dsdt.asl @@ -24,7 +24,6 @@ DefinitionBlock( 0x20090419 // OEM revision ) { - // Some generic macros #include "acpi/platform.asl" // global NVS and variables diff --git a/src/mainboard/roda/rv11/dsdt.asl b/src/mainboard/roda/rv11/dsdt.asl index 67f88d0803..1784b540c9 100644 --- a/src/mainboard/roda/rv11/dsdt.asl +++ b/src/mainboard/roda/rv11/dsdt.asl @@ -25,7 +25,6 @@ DefinitionBlock( { #include - // Some generic macros #include "acpi/platform.asl" #include "acpi/mainboard.asl" diff --git a/src/mainboard/samsung/lumpy/dsdt.asl b/src/mainboard/samsung/lumpy/dsdt.asl index 7dd85b5cd6..3ecabb5935 100644 --- a/src/mainboard/samsung/lumpy/dsdt.asl +++ b/src/mainboard/samsung/lumpy/dsdt.asl @@ -26,7 +26,6 @@ DefinitionBlock( { #include - // Some generic macros #include "acpi/platform.asl" // Thermal handler diff --git a/src/mainboard/samsung/stumpy/dsdt.asl b/src/mainboard/samsung/stumpy/dsdt.asl index db8bfd45d2..9fc9e2f9ff 100644 --- a/src/mainboard/samsung/stumpy/dsdt.asl +++ b/src/mainboard/samsung/stumpy/dsdt.asl @@ -26,7 +26,6 @@ DefinitionBlock( { #include - // Some generic macros #include "acpi/platform.asl" #include "acpi/mainboard.asl" diff --git a/src/mainboard/sapphire/pureplatinumh61/dsdt.asl b/src/mainboard/sapphire/pureplatinumh61/dsdt.asl index fee7e9356f..be30f638e1 100644 --- a/src/mainboard/sapphire/pureplatinumh61/dsdt.asl +++ b/src/mainboard/sapphire/pureplatinumh61/dsdt.asl @@ -27,7 +27,6 @@ DefinitionBlock( 0x20141018 // OEM revision ) { - // Some generic macros #include "acpi/platform.asl" #include #include diff --git a/src/mainboard/scaleway/tagada/dsdt.asl b/src/mainboard/scaleway/tagada/dsdt.asl index c7e7f7c91b..bd32687cb8 100644 --- a/src/mainboard/scaleway/tagada/dsdt.asl +++ b/src/mainboard/scaleway/tagada/dsdt.asl @@ -26,7 +26,6 @@ DefinitionBlock( 0x20110725 // OEM revision ) { - // Some generic macros #include #include "acpi/platform.asl" #include "acpi/mainboard.asl" diff --git a/src/mainboard/siemens/mc_apl1/dsdt.asl b/src/mainboard/siemens/mc_apl1/dsdt.asl index 449bcf878f..ae40f39514 100644 --- a/src/mainboard/siemens/mc_apl1/dsdt.asl +++ b/src/mainboard/siemens/mc_apl1/dsdt.asl @@ -23,7 +23,6 @@ DefinitionBlock( 0x20110725 // OEM revision ) { - /* generic macros */ #include /* global NVS and variables */ diff --git a/src/mainboard/supermicro/x11-lga1151-series/dsdt.asl b/src/mainboard/supermicro/x11-lga1151-series/dsdt.asl index 86ea299aa9..b88b1d20f4 100644 --- a/src/mainboard/supermicro/x11-lga1151-series/dsdt.asl +++ b/src/mainboard/supermicro/x11-lga1151-series/dsdt.asl @@ -25,7 +25,6 @@ DefinitionBlock( 0x20110725 // OEM revision ) { - // Some generic macros #include // global NVS and variables From 7db16ddc8879a5b5acb7681135c7d9439dd1bd99 Mon Sep 17 00:00:00 2001 From: Patrick Rudolph Date: Tue, 10 Dec 2019 13:15:42 +0100 Subject: [PATCH 0812/1242] superio/common/conf_mode: Add op to write SSDT Add functions to write ACPI SSDT code for entering and leaving the config mode. To be used by ACPI generators. Tested on Linux 5.2 using the Aspeed SSDT generator. Change-Id: I14b55b885f1c384536bafafed39ad399639868e4 Signed-off-by: Patrick Rudolph Reviewed-on: https://review.coreboot.org/c/coreboot/+/37639 Tested-by: build bot (Jenkins) Reviewed-by: Felix Held --- src/device/pnp_device.c | 13 ++++ src/include/device/pnp.h | 23 +++++- src/superio/common/conf_mode.c | 136 +++++++++++++++++++++++++++++++++ 3 files changed, 171 insertions(+), 1 deletion(-) diff --git a/src/device/pnp_device.c b/src/device/pnp_device.c index c58b375277..81aa8890b2 100644 --- a/src/device/pnp_device.c +++ b/src/device/pnp_device.c @@ -31,6 +31,19 @@ void pnp_exit_conf_mode(struct device *dev) dev->ops->ops_pnp_mode->exit_conf_mode(dev); } +#if CONFIG(HAVE_ACPI_TABLES) +void pnp_ssdt_enter_conf_mode(struct device *dev, const char *idx, const char *data) +{ + if (dev->ops->ops_pnp_mode && dev->ops->ops_pnp_mode->ssdt_enter_conf_mode) + dev->ops->ops_pnp_mode->ssdt_enter_conf_mode(dev, idx, data); +} +void pnp_ssdt_exit_conf_mode(struct device *dev, const char *idx, const char *data) +{ + if (dev->ops->ops_pnp_mode && dev->ops->ops_pnp_mode->ssdt_exit_conf_mode) + dev->ops->ops_pnp_mode->ssdt_exit_conf_mode(dev, idx, data); +} +#endif + /* PNP fundamental operations */ void pnp_write_config(struct device *dev, u8 reg, u8 value) diff --git a/src/include/device/pnp.h b/src/include/device/pnp.h index d459fd2fd0..800bcc0557 100644 --- a/src/include/device/pnp.h +++ b/src/include/device/pnp.h @@ -67,13 +67,34 @@ struct resource *pnp_get_resource(struct device *dev, unsigned int index); void pnp_enable_devices(struct device *dev, struct device_operations *ops, unsigned int functions, struct pnp_info *info); + struct pnp_mode_ops { void (*enter_conf_mode)(struct device *dev); void (*exit_conf_mode)(struct device *dev); +#if CONFIG(HAVE_ACPI_TABLES) + /* + * Generates ASL code to enter/exit config mode. + * + * @param idx The ACPI name of the SuperIO index port register. eg. 'INDX'. + * @param data The ACPI name of the SuperIO data port register. eg. 'DATA'. + */ + void (*ssdt_enter_conf_mode)(struct device *dev, const char *idx, const char *data); + void (*ssdt_exit_conf_mode)(struct device *dev, const char *idx, const char *data); +#endif }; void pnp_enter_conf_mode(struct device *dev); void pnp_exit_conf_mode(struct device *dev); - +#if CONFIG(HAVE_ACPI_TABLES) +/* + * Generates ASL code to enter/exit config mode if supported. + * The calling code has to place this within an ASL MethodOP. + * + * @param idx The ACPI name of the SuperIO index port register. eg. 'INDX'. + * @param data The ACPI name of the SuperIO data port register. eg. 'DATA'. + */ +void pnp_ssdt_enter_conf_mode(struct device *dev, const char *idx, const char *data); +void pnp_ssdt_exit_conf_mode(struct device *dev, const char *idx, const char *data); +#endif /* PNP indexed I/O operations */ /* diff --git a/src/superio/common/conf_mode.c b/src/superio/common/conf_mode.c index 8ba1cddba9..1e62285444 100644 --- a/src/superio/common/conf_mode.c +++ b/src/superio/common/conf_mode.c @@ -17,6 +17,7 @@ #include #include #include +#include /* Common enter/exit implementations */ @@ -77,38 +78,173 @@ void pnp_exit_conf_mode_0202(struct device *dev) pnp_write_config(dev, 0x02, (1 << 1)); } +/* Functions for ACPI */ +#if CONFIG(HAVE_ACPI_TABLES) +static void pnp_ssdt_enter_conf_mode_55(struct device *dev, const char *idx, const char *data) +{ + acpigen_write_store(); + acpigen_write_byte(0x55); + acpigen_emit_namestring(idx); +} + +static void pnp_ssdt_enter_conf_mode_6767(struct device *dev, const char *idx, const char *data) +{ + acpigen_write_store(); + acpigen_write_byte(0x67); + acpigen_emit_namestring(idx); + + acpigen_write_store(); + acpigen_write_byte(0x67); + acpigen_emit_namestring(idx); +} + +static void pnp_ssdt_enter_conf_mode_7777(struct device *dev, const char *idx, const char *data) +{ + acpigen_write_store(); + acpigen_write_byte(0x77); + acpigen_emit_namestring(idx); + + acpigen_write_store(); + acpigen_write_byte(0x77); + acpigen_emit_namestring(idx); +} + +static void pnp_ssdt_enter_conf_mode_8787(struct device *dev, const char *idx, const char *data) +{ + acpigen_write_store(); + acpigen_write_byte(0x87); + acpigen_emit_namestring(idx); + + acpigen_write_store(); + acpigen_write_byte(0x87); + acpigen_emit_namestring(idx); +} + +static void pnp_ssdt_enter_conf_mode_a0a0(struct device *dev, const char *idx, const char *data) +{ + acpigen_write_store(); + acpigen_write_byte(0xa0); + acpigen_emit_namestring(idx); + + acpigen_write_store(); + acpigen_write_byte(0xa0); + acpigen_emit_namestring(idx); + +} + +static void pnp_ssdt_enter_conf_mode_a5a5(struct device *dev, const char *idx, const char *data) +{ + acpigen_write_store(); + acpigen_write_byte(0xa5); + acpigen_emit_namestring(idx); + + acpigen_write_store(); + acpigen_write_byte(0xa5); + acpigen_emit_namestring(idx); +} + +static void pnp_ssdt_enter_conf_mode_870155aa(struct device *dev, + const char *idx, const char *data) +{ + acpigen_write_store(); + acpigen_write_byte(0x87); + acpigen_emit_namestring(idx); + + acpigen_write_store(); + acpigen_write_byte(0x01); + acpigen_emit_namestring(idx); + + acpigen_write_store(); + acpigen_write_byte(0x55); + acpigen_emit_namestring(idx); + + acpigen_write_store(); + if (dev->path.pnp.port == 0x4e) + acpigen_write_byte(0xaa); + else + acpigen_write_byte(0x55); + acpigen_emit_namestring(idx); +} + +static void pnp_ssdt_exit_conf_mode_aa(struct device *dev, const char *idx, const char *data) +{ + acpigen_write_store(); + acpigen_write_byte(0xaa); + acpigen_emit_namestring(idx); +} + +static void pnp_ssdt_exit_conf_mode_0202(struct device *dev, const char *idx, const char *data) +{ + + acpigen_write_store(); + acpigen_write_byte(0x02); + acpigen_emit_namestring(idx); + + acpigen_write_store(); + acpigen_write_byte(0x02); + acpigen_emit_namestring(data); +} +#endif const struct pnp_mode_ops pnp_conf_mode_55_aa = { .enter_conf_mode = pnp_enter_conf_mode_55, .exit_conf_mode = pnp_exit_conf_mode_aa, +#if CONFIG(HAVE_ACPI_TABLES) + .ssdt_enter_conf_mode = pnp_ssdt_enter_conf_mode_55, + .ssdt_exit_conf_mode = pnp_ssdt_exit_conf_mode_aa, +#endif }; const struct pnp_mode_ops pnp_conf_mode_6767_aa = { .enter_conf_mode = pnp_enter_conf_mode_6767, .exit_conf_mode = pnp_exit_conf_mode_aa, +#if CONFIG(HAVE_ACPI_TABLES) + .ssdt_enter_conf_mode = pnp_ssdt_enter_conf_mode_6767, + .ssdt_exit_conf_mode = pnp_ssdt_exit_conf_mode_aa, +#endif }; const struct pnp_mode_ops pnp_conf_mode_7777_aa = { .enter_conf_mode = pnp_enter_conf_mode_7777, .exit_conf_mode = pnp_exit_conf_mode_aa, +#if CONFIG(HAVE_ACPI_TABLES) + .ssdt_enter_conf_mode = pnp_ssdt_enter_conf_mode_7777, + .ssdt_exit_conf_mode = pnp_ssdt_exit_conf_mode_aa, +#endif }; const struct pnp_mode_ops pnp_conf_mode_8787_aa = { .enter_conf_mode = pnp_enter_conf_mode_8787, .exit_conf_mode = pnp_exit_conf_mode_aa, +#if CONFIG(HAVE_ACPI_TABLES) + .ssdt_enter_conf_mode = pnp_ssdt_enter_conf_mode_8787, + .ssdt_exit_conf_mode = pnp_ssdt_exit_conf_mode_aa, +#endif }; const struct pnp_mode_ops pnp_conf_mode_a0a0_aa = { .enter_conf_mode = pnp_enter_conf_mode_a0a0, .exit_conf_mode = pnp_exit_conf_mode_aa, +#if CONFIG(HAVE_ACPI_TABLES) + .ssdt_enter_conf_mode = pnp_ssdt_enter_conf_mode_a0a0, + .ssdt_exit_conf_mode = pnp_ssdt_exit_conf_mode_aa, +#endif }; const struct pnp_mode_ops pnp_conf_mode_a5a5_aa = { .enter_conf_mode = pnp_enter_conf_mode_a5a5, .exit_conf_mode = pnp_exit_conf_mode_aa, +#if CONFIG(HAVE_ACPI_TABLES) + .ssdt_enter_conf_mode = pnp_ssdt_enter_conf_mode_a5a5, + .ssdt_exit_conf_mode = pnp_ssdt_exit_conf_mode_aa, +#endif }; const struct pnp_mode_ops pnp_conf_mode_870155_aa = { .enter_conf_mode = pnp_enter_conf_mode_870155aa, .exit_conf_mode = pnp_exit_conf_mode_0202, +#if CONFIG(HAVE_ACPI_TABLES) + .ssdt_enter_conf_mode = pnp_ssdt_enter_conf_mode_870155aa, + .ssdt_exit_conf_mode = pnp_ssdt_exit_conf_mode_0202, +#endif }; From 95bff2e17e8b9e84e588aeb9504e086174edd0b0 Mon Sep 17 00:00:00 2001 From: Patrick Rudolph Date: Tue, 10 Dec 2019 14:12:03 +0100 Subject: [PATCH 0813/1242] superio/common: Add more ACPI methods * Make use of introduced SSDT config mode access * Make use of introduced SSDT mutex * Provide ACPI functions to safely access SIO config space * Implement method to query LDN enable state * Implement method to set LDN enable state * Use introduced functions to implement _DIS and _STA in the device * Update documentation Tested on Aspeed AST2500 and Linux 5.2. Manually verified ACPI code that generates no errors in Linux. Change-Id: I520b29de925f368cd71ff8f1f58d2d57d72eff8d Signed-off-by: Patrick Rudolph Reviewed-on: https://review.coreboot.org/c/coreboot/+/37640 Tested-by: build bot (Jenkins) Reviewed-by: Felix Held --- Documentation/superio/common/ssdt.md | 29 +++++- src/superio/common/generic.c | 140 +++++++++++++++++++++++++++ src/superio/common/ssdt.c | 26 ++++- 3 files changed, 190 insertions(+), 5 deletions(-) diff --git a/Documentation/superio/common/ssdt.md b/Documentation/superio/common/ssdt.md index f2bb3346a0..2f4049ef12 100644 --- a/Documentation/superio/common/ssdt.md +++ b/Documentation/superio/common/ssdt.md @@ -45,12 +45,33 @@ chip superio/common end ``` +## Automatically generated methods + +The following methods are generated for each SuperIO: +## AMTX() +Acquire the global mutex and enter config mode. +It's called this at the begining of an atomic operation to make sure +no other ACPI code messes with the config space while working on it. + +## RMTX() +Exit config mode and release the global mutex. +It's called at the end of an atomic operation. + +## SLDN(Arg0) +Selects the (virtual) LDN given as Arg0. +This method isn't guarded with the global mutex. + +## DLDN(Arg0) +Disables the (virtual) LDN given as Arg0. +This method aquires the global mutex. + +## QLDN(Arg0) +Queries the state of the (virtual) LDN given as Arg0. +This method quires the global mutex. + ## TODO 1) Add ACPI HIDs to every SuperIO driver -2) Don't guess ACPI HID of LDNs if it's known -3) Add "enter config" and "exit config" bytes -4) Generate support methods that allow +2) Generate support methods that allow * Setting resource settings at runtime * Getting resource settings at runtime - * Disabling LDNs at runtime diff --git a/src/superio/common/generic.c b/src/superio/common/generic.c index 7ac1f8374e..85b70df1b5 100644 --- a/src/superio/common/generic.c +++ b/src/superio/common/generic.c @@ -156,6 +156,146 @@ static void generic_ssdt(struct device *dev) acpigen_write_indexfield("INDX", "DATA", i, ARRAY_SIZE(i), FIELD_BYTEACC | FIELD_NOLOCK | FIELD_PRESERVE); + const char *mutex = "MTX0"; + + acpigen_write_mutex(mutex, 0); + /* Backup LDN */ + acpigen_write_name_integer("BLDN", 0); + + /* Acquire mutex - Enter config mode */ + acpigen_write_method("AMTX", 0); + { + acpigen_write_acquire(mutex, 0xffff); + + /* Pick one of the children as the generic SIO doesn't have config mode */ + if (dev->link_list && dev->link_list->children) + pnp_ssdt_enter_conf_mode(dev->link_list->children, "^INDX", "^DATA"); + + /* Backup LDN */ + acpigen_write_store(); + acpigen_emit_namestring("^LDN"); + acpigen_emit_namestring("^BLDN"); + } + acpigen_pop_len(); /* Method */ + + /* Release mutex - Exit config mode */ + acpigen_write_method("RMTX", 0); + { + /* Restore LDN */ + acpigen_write_store(); + acpigen_emit_namestring("^BLDN"); + acpigen_emit_namestring("^LDN"); + + /* Pick one of the children as the generic SIO doesn't have config mode */ + if (dev->link_list && dev->link_list->children) + pnp_ssdt_exit_conf_mode(dev->link_list->children, "^INDX", "^DATA"); + + acpigen_write_release(mutex); + } + acpigen_pop_len(); /* Method */ + + /* Select a LDN */ + acpigen_write_method("SLDN", 1); + { + /* Local0 = Arg0 & 0xff */ + acpigen_emit_byte(AND_OP); + acpigen_write_integer(0xff); + acpigen_emit_byte(ARG0_OP); + acpigen_emit_byte(LOCAL0_OP); + + /* LDN = LOCAL0_OP */ + acpigen_write_store(); + acpigen_emit_byte(LOCAL0_OP); + acpigen_emit_namestring("^LDN"); + } + acpigen_pop_len(); /* Method */ + + /* Disable a LDN/VLDN */ + acpigen_write_method("DLDN", 1); + { + /* AMTX() */ + acpigen_emit_namestring("AMTX"); + + /* SLDN (Local0) */ + acpigen_emit_namestring("SLDN"); + acpigen_emit_byte(ARG0_OP); + + /* Local0 = Arg0 >> 8 */ + acpigen_emit_byte(SHIFT_RIGHT_OP); + acpigen_emit_byte(ARG0_OP); + acpigen_write_integer(8); + acpigen_emit_byte(LOCAL0_OP); + + /* Local0 = Local0 & 0x7 */ + acpigen_emit_byte(AND_OP); + acpigen_write_integer(0x7); + acpigen_emit_byte(LOCAL0_OP); + acpigen_emit_byte(LOCAL0_OP); + + for (int j = 0; j < 8; j++) { + char act[6] = "^ACT0"; + act[4] += j; + + /* If (Local0 == j) { */ + acpigen_write_if_lequal_op_int(LOCAL0_OP, j); + + /* ACT[j] = 0 */ + acpigen_write_store(); + acpigen_emit_byte(ZERO_OP); + acpigen_emit_namestring(act); + + acpigen_pop_len(); /* } */ + } + + /* RMTX() */ + acpigen_emit_namestring("RMTX"); + } + acpigen_pop_len(); /* Method */ + + /* Query LDN enable state. Returns 1 if LDN/VLDN is enabled. */ + acpigen_write_method("QLDN", 1); + { + acpigen_emit_namestring("AMTX"); + + /* SLDN (Local0) */ + acpigen_emit_namestring("SLDN"); + acpigen_emit_byte(ARG0_OP); + + /* Local0 = Arg0 >> 8 */ + acpigen_emit_byte(SHIFT_RIGHT_OP); + acpigen_emit_byte(ARG0_OP); + acpigen_write_integer(8); + acpigen_emit_byte(LOCAL0_OP); + + /* Local0 = Local0 & 0x7 */ + acpigen_emit_byte(AND_OP); + acpigen_write_integer(0x7); + acpigen_emit_byte(LOCAL0_OP); + acpigen_emit_byte(LOCAL0_OP); + + for (int j = 0; j < 8; j++) { + char act[6] = "^ACT0"; + act[4] += j; + /* If (Local0 == j) { */ + acpigen_write_if_lequal_op_int(LOCAL0_OP, j); + + /* Local1 = ACT[j] */ + acpigen_write_store(); + acpigen_emit_namestring(act); + acpigen_emit_byte(LOCAL1_OP); + + acpigen_pop_len(); /* } */ + } + + /* RMTX() */ + acpigen_emit_namestring("RMTX"); + + /* Return (Local1) */ + acpigen_emit_byte(RETURN_OP); + acpigen_emit_byte(LOCAL1_OP); + } + acpigen_pop_len(); /* Method */ + acpigen_pop_len(); /* Device */ acpigen_pop_len(); /* Scope */ } diff --git a/src/superio/common/ssdt.c b/src/superio/common/ssdt.c index a919aa5620..bc5d39460a 100644 --- a/src/superio/common/ssdt.c +++ b/src/superio/common/ssdt.c @@ -200,7 +200,24 @@ void superio_common_fill_ssdt_generator(struct device *dev) acpigen_write_name_byte("LDN", ldn); acpigen_write_name_byte("VLDN", vldn); - acpigen_write_STA(dev->enabled ? 0xf : 0); + acpigen_write_method("_STA", 0); + { + acpigen_write_store(); + acpigen_emit_namestring("^^QLDN"); + acpigen_write_integer(ldn); + acpigen_emit_byte(LOCAL0_OP); + + /* Multiply (Local0, 0xf, Local0) */ + acpigen_emit_byte(MULTIPLY_OP); + acpigen_emit_byte(LOCAL0_OP); + acpigen_write_integer(0xf); + acpigen_emit_byte(LOCAL0_OP); + + acpigen_emit_byte(RETURN_OP); + acpigen_emit_byte(LOCAL0_OP); + + } + acpigen_pop_len(); /* Method */ if (!dev->enabled) { acpigen_pop_len(); /* Device */ @@ -242,6 +259,13 @@ void superio_common_fill_ssdt_generator(struct device *dev) acpigen_write_name_string("_HID", hid); acpigen_write_name_string("_DDN", name_from_hid(hid)); + acpigen_write_method("_DIS", 0); + { + acpigen_emit_namestring("^^DLDN"); + acpigen_write_integer(ldn); + } + acpigen_pop_len(); /* Method */ + acpigen_pop_len(); /* Device */ acpigen_pop_len(); /* Scope */ } From e8b7ff1ab51be3fd8a98a3fc1dfdf15aa800cab5 Mon Sep 17 00:00:00 2001 From: Edward O'Callaghan Date: Mon, 23 Dec 2019 23:12:19 +1100 Subject: [PATCH 0814/1242] mainboard/google/puff: Enable func0 of 1c for nic Two things here: i. ) FSP requires that function 0 be enabled whenever any non-zero functions hang under the same bus:device. ii.) FSP reorders function 6 RP to be function 0 if function 0 is indeed unused. BUG=b:146437819 BRANCH=none TEST=none Change-Id: I0f499a23495e18cfcc712c7c96024433a6181a4c Signed-off-by: Edward O'Callaghan Reviewed-on: https://review.coreboot.org/c/coreboot/+/37913 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh --- src/mainboard/google/hatch/variants/puff/overridetree.cb | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/src/mainboard/google/hatch/variants/puff/overridetree.cb b/src/mainboard/google/hatch/variants/puff/overridetree.cb index a24d7fc80a..b99c1f240a 100644 --- a/src/mainboard/google/hatch/variants/puff/overridetree.cb +++ b/src/mainboard/google/hatch/variants/puff/overridetree.cb @@ -175,7 +175,8 @@ chip soc/intel/cannonlake end end #I2C #4 device pci 1a.0 on end # eMMC - device pci 1c.6 on end # PCI Express Port 7, RTL8111H Ethernet NIC. + device pci 1c.0 on end # FSP requires func0 be enabled. + device pci 1c.6 on end # RTL8111H Ethernet NIC (becomes RP1). device pci 1e.3 off end # GSPI #1 end From 295fdbef392e1ab6c8c7e4f0d7a9a01d95bb5bd5 Mon Sep 17 00:00:00 2001 From: Edward O'Callaghan Date: Fri, 20 Dec 2019 11:47:29 +1100 Subject: [PATCH 0815/1242] mainboard/google/puff: Configure HDA registers Enable PCH HDA and configure dmic+ssp registers. BRANCH=none BUG=b:146519004 TEST=./util/abuild/abuild -p none -t google/hatch -x -a Change-Id: If9495261201ca256cdb35352338c0b3a82a50196 Signed-off-by: Edward O'Callaghan Reviewed-on: https://review.coreboot.org/c/coreboot/+/37859 Tested-by: build bot (Jenkins) Reviewed-by: Daniel Kurtz --- src/mainboard/google/hatch/variants/puff/overridetree.cb | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/src/mainboard/google/hatch/variants/puff/overridetree.cb b/src/mainboard/google/hatch/variants/puff/overridetree.cb index b99c1f240a..342994d90a 100644 --- a/src/mainboard/google/hatch/variants/puff/overridetree.cb +++ b/src/mainboard/google/hatch/variants/puff/overridetree.cb @@ -68,6 +68,10 @@ chip soc/intel/cannonlake # [6:0] Rx Strobe Delay DLL 2(HS400 Mode), each 125ps, range: 0 - 39. register "common_soc_config.emmc_dll.emmc_rx_strobe_cntl" = "0x1515" + # Intel HDA - disable I2S Audio SSP1 and DMIC0 as puff variant does not have them. + register "PchHdaAudioLinkSsp1" = "0" + register "PchHdaAudioLinkDmic0" = "0" + # Intel Common SoC Config #+-------------------+---------------------------+ #| Field | Value | From b4177865254742fa7cb675a913a0c5c078cf5968 Mon Sep 17 00:00:00 2001 From: Edward O'Callaghan Date: Mon, 23 Dec 2019 18:14:23 +1100 Subject: [PATCH 0816/1242] mainboard/google/hatch: Remove MAX98357A assumption from baseboard Generally work towards a more loose baseboard definition by moving out some original assumptions to be board specifics. Specifically Puff does not have the MAX98357A speaker amp and enabling the driver winds up generating incorrect SSDT tables that confuse the kernel. Since devicetree inherits the chip from device node in base and an override will also inherit the chip and thus dispatch the unwanted fill_ssdt fn call. V.2: lean on linker to drop max98357a driver when not in dt. BRANCH=none BUG=b:146519004 TEST=./util/abuild/abuild -p none -t google/hatch -x -a Change-Id: I8e7fed69a4c6d9610ac100da6bae147828ebfa81 Signed-off-by: Edward O'Callaghan Reviewed-on: https://review.coreboot.org/c/coreboot/+/37909 Reviewed-by: Daniel Kurtz Reviewed-by: Furquan Shaikh Tested-by: build bot (Jenkins) --- src/mainboard/google/hatch/variants/akemi/overridetree.cb | 7 +++++++ .../google/hatch/variants/baseboard/devicetree.cb | 8 +------- .../google/hatch/variants/dratini/overridetree.cb | 7 +++++++ src/mainboard/google/hatch/variants/hatch/overridetree.cb | 7 +++++++ .../google/hatch/variants/helios/overridetree.cb | 7 +++++++ .../google/hatch/variants/helios_diskswap/overridetree.cb | 7 +++++++ .../google/hatch/variants/jinlon/overridetree.cb | 7 +++++++ .../google/hatch/variants/kindred/overridetree.cb | 7 +++++++ .../google/hatch/variants/kohaku/overridetree.cb | 7 +++++++ src/mainboard/google/hatch/variants/mushu/overridetree.cb | 7 +++++++ .../google/hatch/variants/stryke/overridetree.cb | 7 +++++++ 11 files changed, 71 insertions(+), 7 deletions(-) diff --git a/src/mainboard/google/hatch/variants/akemi/overridetree.cb b/src/mainboard/google/hatch/variants/akemi/overridetree.cb index de4a903993..9b0f5f7b60 100644 --- a/src/mainboard/google/hatch/variants/akemi/overridetree.cb +++ b/src/mainboard/google/hatch/variants/akemi/overridetree.cb @@ -233,6 +233,13 @@ chip soc/intel/cannonlake end #I2C #4 device pci 1a.0 on end # eMMC device pci 1e.3 off end # GSPI #1 + device pci 1f.3 on + chip drivers/generic/max98357a + register "sdmode_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_H3)" + register "sdmode_delay" = "5" + device generic 0 on end + end + end # Intel HDA end end diff --git a/src/mainboard/google/hatch/variants/baseboard/devicetree.cb b/src/mainboard/google/hatch/variants/baseboard/devicetree.cb index 7382209264..d944dcd40f 100644 --- a/src/mainboard/google/hatch/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/hatch/variants/baseboard/devicetree.cb @@ -344,13 +344,7 @@ chip soc/intel/cannonlake end # eSPI Interface device pci 1f.1 on end # P2SB device pci 1f.2 on end # Power Management Controller - device pci 1f.3 on - chip drivers/generic/max98357a - register "sdmode_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_H3)" - register "sdmode_delay" = "5" - device generic 0 on end - end - end # Intel HDA + device pci 1f.3 on end # Intel HDA device pci 1f.4 on end # SMBus device pci 1f.5 on end # PCH SPI device pci 1f.6 off end # GbE diff --git a/src/mainboard/google/hatch/variants/dratini/overridetree.cb b/src/mainboard/google/hatch/variants/dratini/overridetree.cb index 564a14d93c..c6a9ed70e3 100644 --- a/src/mainboard/google/hatch/variants/dratini/overridetree.cb +++ b/src/mainboard/google/hatch/variants/dratini/overridetree.cb @@ -157,6 +157,13 @@ chip soc/intel/cannonlake device spi 1 on end end # FPMCU end # GSPI #1 + device pci 1f.3 on + chip drivers/generic/max98357a + register "sdmode_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_H3)" + register "sdmode_delay" = "5" + device generic 0 on end + end + end # Intel HDA end end diff --git a/src/mainboard/google/hatch/variants/hatch/overridetree.cb b/src/mainboard/google/hatch/variants/hatch/overridetree.cb index 75c14efad5..c623fde5ba 100644 --- a/src/mainboard/google/hatch/variants/hatch/overridetree.cb +++ b/src/mainboard/google/hatch/variants/hatch/overridetree.cb @@ -176,6 +176,13 @@ chip soc/intel/cannonlake device spi 1 on end end # FPMCU end # GSPI #1 + device pci 1f.3 on + chip drivers/generic/max98357a + register "sdmode_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_H3)" + register "sdmode_delay" = "5" + device generic 0 on end + end + end # Intel HDA end end diff --git a/src/mainboard/google/hatch/variants/helios/overridetree.cb b/src/mainboard/google/hatch/variants/helios/overridetree.cb index 94639dcabe..cf86639d7a 100644 --- a/src/mainboard/google/hatch/variants/helios/overridetree.cb +++ b/src/mainboard/google/hatch/variants/helios/overridetree.cb @@ -193,5 +193,12 @@ chip soc/intel/cannonlake device spi 1 on end end # FPMCU end # GSPI #1 + device pci 1f.3 on + chip drivers/generic/max98357a + register "sdmode_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_H3)" + register "sdmode_delay" = "5" + device generic 0 on end + end + end # Intel HDA end end diff --git a/src/mainboard/google/hatch/variants/helios_diskswap/overridetree.cb b/src/mainboard/google/hatch/variants/helios_diskswap/overridetree.cb index 3bbf232a93..22534f32f9 100644 --- a/src/mainboard/google/hatch/variants/helios_diskswap/overridetree.cb +++ b/src/mainboard/google/hatch/variants/helios_diskswap/overridetree.cb @@ -205,5 +205,12 @@ chip soc/intel/cannonlake device spi 1 on end end # FPMCU end # GSPI #1 + device pci 1f.3 on + chip drivers/generic/max98357a + register "sdmode_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_H3)" + register "sdmode_delay" = "5" + device generic 0 on end + end + end # Intel HDA end end diff --git a/src/mainboard/google/hatch/variants/jinlon/overridetree.cb b/src/mainboard/google/hatch/variants/jinlon/overridetree.cb index 28b18b8b7f..fd2861e5f6 100644 --- a/src/mainboard/google/hatch/variants/jinlon/overridetree.cb +++ b/src/mainboard/google/hatch/variants/jinlon/overridetree.cb @@ -154,6 +154,13 @@ chip soc/intel/cannonlake device spi 1 on end end # FPMCU end # GSPI #1 + device pci 1f.3 on + chip drivers/generic/max98357a + register "sdmode_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_H3)" + register "sdmode_delay" = "5" + device generic 0 on end + end + end # Intel HDA end end diff --git a/src/mainboard/google/hatch/variants/kindred/overridetree.cb b/src/mainboard/google/hatch/variants/kindred/overridetree.cb index a000add5b0..5067991088 100644 --- a/src/mainboard/google/hatch/variants/kindred/overridetree.cb +++ b/src/mainboard/google/hatch/variants/kindred/overridetree.cb @@ -197,6 +197,13 @@ chip soc/intel/cannonlake end #I2C #4 device pci 1a.0 on end # eMMC device pci 1e.3 off end # GSPI #1 unused + device pci 1f.3 on + chip drivers/generic/max98357a + register "sdmode_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_H3)" + register "sdmode_delay" = "5" + device generic 0 on end + end + end # Intel HDA end end diff --git a/src/mainboard/google/hatch/variants/kohaku/overridetree.cb b/src/mainboard/google/hatch/variants/kohaku/overridetree.cb index cd5ce0e816..158731b8e7 100644 --- a/src/mainboard/google/hatch/variants/kohaku/overridetree.cb +++ b/src/mainboard/google/hatch/variants/kohaku/overridetree.cb @@ -259,5 +259,12 @@ chip soc/intel/cannonlake device spi 1 on end end # FPMCU end # GSPI #1 + device pci 1f.3 on + chip drivers/generic/max98357a + register "sdmode_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_H3)" + register "sdmode_delay" = "5" + device generic 0 on end + end + end # Intel HDA end # domain end diff --git a/src/mainboard/google/hatch/variants/mushu/overridetree.cb b/src/mainboard/google/hatch/variants/mushu/overridetree.cb index 75c14efad5..c623fde5ba 100644 --- a/src/mainboard/google/hatch/variants/mushu/overridetree.cb +++ b/src/mainboard/google/hatch/variants/mushu/overridetree.cb @@ -176,6 +176,13 @@ chip soc/intel/cannonlake device spi 1 on end end # FPMCU end # GSPI #1 + device pci 1f.3 on + chip drivers/generic/max98357a + register "sdmode_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_H3)" + register "sdmode_delay" = "5" + device generic 0 on end + end + end # Intel HDA end end diff --git a/src/mainboard/google/hatch/variants/stryke/overridetree.cb b/src/mainboard/google/hatch/variants/stryke/overridetree.cb index e04a2e7d11..796e589070 100644 --- a/src/mainboard/google/hatch/variants/stryke/overridetree.cb +++ b/src/mainboard/google/hatch/variants/stryke/overridetree.cb @@ -210,6 +210,13 @@ chip soc/intel/cannonlake end end #I2C #4 device pci 1e.3 off end # GSPI #1 + device pci 1f.3 on + chip drivers/generic/max98357a + register "sdmode_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_H3)" + register "sdmode_delay" = "5" + device generic 0 on end + end + end # Intel HDA end end From 028570b4453a3b9328ca953eaf77f097c6ed851e Mon Sep 17 00:00:00 2001 From: Raul E Rangel Date: Fri, 20 Dec 2019 15:00:40 -0700 Subject: [PATCH 0817/1242] vendorcode/amd/pi/Kconfig: Add prompt to pre/post pi files MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This allows the values to be set in a .config BUG=none TEST=Was able to set the value from a .config and built careena firmware Change-Id: I757e4b9a0b80ff42c1f49143a44f15550366fd0b Signed-off-by: Raul E Rangel Reviewed-on: https://review.coreboot.org/c/coreboot/+/37879 Reviewed-by: Marshall Dawson Reviewed-by: Michał Żygowski Tested-by: build bot (Jenkins) --- src/vendorcode/amd/pi/Kconfig | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/vendorcode/amd/pi/Kconfig b/src/vendorcode/amd/pi/Kconfig index 265a381eb6..9dcdf34025 100644 --- a/src/vendorcode/amd/pi/Kconfig +++ b/src/vendorcode/amd/pi/Kconfig @@ -68,7 +68,7 @@ config AGESA_SPLIT_MEMORY_FILES post-memory. config AGESA_PRE_MEMORY_BINARY_PI_FILE - string + string "Pre memory Binary PI file name" depends on AGESA_SPLIT_MEMORY_FILES default "3rdparty/blobs/pi/amd/00670F00/FT4/AGESA_premem.elf" if SOC_AMD_STONEYRIDGE && USE_AMD_BLOBS help @@ -76,7 +76,7 @@ config AGESA_PRE_MEMORY_BINARY_PI_FILE initialization. config AGESA_POST_MEMORY_BINARY_PI_FILE - string + string "Post memory Binary PI file name" depends on AGESA_SPLIT_MEMORY_FILES default "3rdparty/blobs/pi/amd/00670F00/FT4/AGESA_postmem.elf" if SOC_AMD_STONEYRIDGE && USE_AMD_BLOBS help From 60889e55ea0076f442833e0bfc94fe828bb5d4b3 Mon Sep 17 00:00:00 2001 From: Kangheui Won Date: Wed, 11 Dec 2019 17:29:47 +1100 Subject: [PATCH 0818/1242] mainboard/variant/puff: set PL values for puff To be safe for now, don't differentiate between SKUs and use lower values to ensure board won't be browned out. BUG=b:143246320 TEST=none BRANCH=none Change-Id: I041ebaa33bf2582386198290e625099ba8e2f3c9 Signed-off-by: Kangheui Won Reviewed-on: https://review.coreboot.org/c/coreboot/+/37651 Reviewed-by: Edward O'Callaghan Tested-by: build bot (Jenkins) --- src/mainboard/google/hatch/ramstage.c | 6 ++ .../baseboard/include/baseboard/variants.h | 3 + .../google/hatch/variants/puff/Makefile.inc | 1 + .../google/hatch/variants/puff/mainboard.c | 90 +++++++++++++++++++ 4 files changed, 100 insertions(+) create mode 100644 src/mainboard/google/hatch/variants/puff/mainboard.c diff --git a/src/mainboard/google/hatch/ramstage.c b/src/mainboard/google/hatch/ramstage.c index e84aa1861b..e4de3a2174 100644 --- a/src/mainboard/google/hatch/ramstage.c +++ b/src/mainboard/google/hatch/ramstage.c @@ -36,6 +36,11 @@ void __weak variant_ramstage_init(void) /* Default weak implementation */ } +void __weak variant_mainboard_enable(struct device *dev) +{ + /* Override mainboard settings per board */ +} + static void mainboard_init(struct device *dev) { mainboard_ec_init(); @@ -45,6 +50,7 @@ static void mainboard_enable(struct device *dev) { dev->ops->init = mainboard_init; dev->ops->acpi_inject_dsdt_generator = chromeos_dsdt_generator; + variant_mainboard_enable(dev); } static void mainboard_chip_init(void *chip_info) diff --git a/src/mainboard/google/hatch/variants/baseboard/include/baseboard/variants.h b/src/mainboard/google/hatch/variants/baseboard/include/baseboard/variants.h index 1542d9bc54..9d1b91e0c7 100644 --- a/src/mainboard/google/hatch/variants/baseboard/include/baseboard/variants.h +++ b/src/mainboard/google/hatch/variants/baseboard/include/baseboard/variants.h @@ -53,4 +53,7 @@ void variant_devtree_update(void); /* Perform variant specific initialization early on in ramstage. */ void variant_ramstage_init(void); +/* Perform variant specific mainboard initialization */ +void variant_mainboard_enable(struct device *dev); + #endif /* BASEBOARD_VARIANTS_H */ diff --git a/src/mainboard/google/hatch/variants/puff/Makefile.inc b/src/mainboard/google/hatch/variants/puff/Makefile.inc index 30daaf7f0c..2d1440e3ac 100644 --- a/src/mainboard/google/hatch/variants/puff/Makefile.inc +++ b/src/mainboard/google/hatch/variants/puff/Makefile.inc @@ -13,4 +13,5 @@ ## ramstage-y += gpio.c +ramstage-y += mainboard.c bootblock-y += gpio.c diff --git a/src/mainboard/google/hatch/variants/puff/mainboard.c b/src/mainboard/google/hatch/variants/puff/mainboard.c new file mode 100644 index 0000000000..9c2b5fb033 --- /dev/null +++ b/src/mainboard/google/hatch/variants/puff/mainboard.c @@ -0,0 +1,90 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include +#include + +/* + * For type-C chargers, set PL2 to 90% of max power to account for + * cable loss and FET Rdson loss in the path from the source. + */ +#define SET_PSYSPL2(w) (9 * (w) / 10) + +#define PUFF_PL2 (35) + +#define PUFF_PSYSPL2 (58) + +#define PUFF_MAX_TIME_WINDOW 6 +#define PUFF_MIN_DUTYCYCLE 4 + +/* + * mainboard_set_power_limits + * + * Set Pl2 and SysPl2 values based on detected charger. + * Values are defined below but we use U22 value for all SKUs for now. + * definitions: + * x = no value entered. Use default value in parenthesis. + * will set 0 to anything that shouldn't be set. + * n = max value of power adapter. + * +-------------+-----+---------+-----------+-------+ + * | sku_id | PL2 | PsysPL2 | PsysPL3 | PL4 | + * +-------------+-----+---------+-----------+-------+ + * | i7 U42 | 51 | 81 | x(.85PL4) | x(82) | + * | celeron U22 | 35 | 58 | x(.85PL4) | x(51) | + * +-------------+-----+---------+-----------+-------+ + * For USB C charger: + * +-------------+-----+---------+---------+-------+ + * | Max Power(W)| PL2 | PsysPL2 | PsysPL3 | PL4 | + * +-------------+-----+---------+---------+-------+ + * | 60 (U42) | 44 | 54 | 54 | 54 | + * | 60 (U22) | 29 | 54 | 54 | x(43) | + * | n (U42) | 44 | .9n | .9n | .9n | + * | n (U22) | 29 | .9n | .9n | x(43) | + * +-------------+-----+---------+---------+-------+ + */ +static void mainboard_set_power_limits(config_t *conf) +{ + enum usb_chg_type type; + u32 watts; + u32 psyspl2 = PUFF_PSYSPL2; // default barrel jack value for U22 + int rv = google_chromeec_get_usb_pd_power_info(&type, &watts); + + /* use SoC default value for PsysPL3 and PL4 unless we're on USB-PD*/ + conf->tdp_psyspl3 = 0; + conf->tdp_pl4 = 0; + + if (rv == 0 && type == USB_CHG_TYPE_PD) { + /* Detected USB-PD. Base on max value of adapter */ + psyspl2 = watts; + conf->tdp_psyspl3 = SET_PSYSPL2(psyspl2); + /* set max possible time window */ + conf->tdp_psyspl3_time = PUFF_MAX_TIME_WINDOW; + /* set minimum duty cycle */ + conf->tdp_psyspl3_dutycycle = PUFF_MIN_DUTYCYCLE; + conf->tdp_pl4 = SET_PSYSPL2(psyspl2); + } + + conf->tdp_pl2_override = PUFF_PL2; + /* set psyspl2 to 90% of max adapter power */ + conf->tdp_psyspl2 = SET_PSYSPL2(psyspl2); +} + +void variant_mainboard_enable(struct device *dev) +{ + config_t *conf = config_of_soc(); + mainboard_set_power_limits(conf); +} From c4a3f51618a7575628fb513133952ac57326fc24 Mon Sep 17 00:00:00 2001 From: Edward O'Callaghan Date: Tue, 24 Dec 2019 14:11:43 +1100 Subject: [PATCH 0819/1242] mainboard/google/hatch: Move gpio GPP_A* NC down into baseboard The baseboard GPIO table definitions are too straineous to the extend that variants need to redefine assumptions back to NC. Invert this so that baseboard by default assumes the safer NC and move the specific board configurations to their respective places. This patch handles the GPP_A* group for easier review. BUG=b:142094759 BRANCH=none TEST=builds Change-Id: I29b4323ac80b1288b2562846217c4f377714fc2c Signed-off-by: Edward O'Callaghan Reviewed-on: https://review.coreboot.org/c/coreboot/+/37920 Tested-by: build bot (Jenkins) Reviewed-by: Kangheui Won Reviewed-by: Furquan Shaikh --- .../google/hatch/variants/akemi/gpio.c | 24 ------------- .../google/hatch/variants/baseboard/gpio.c | 24 ++++++------- .../google/hatch/variants/dratini/gpio.c | 12 +++---- .../google/hatch/variants/hatch/gpio.c | 12 +++++++ .../google/hatch/variants/helios/gpio.c | 12 ++++--- .../google/hatch/variants/jinlon/gpio.c | 12 +++---- .../google/hatch/variants/kindred/gpio.c | 36 +++++++++++++++++++ .../google/hatch/variants/kohaku/gpio.c | 12 +++---- .../google/hatch/variants/mushu/gpio.c | 12 +++++++ .../google/hatch/variants/stryke/gpio.c | 12 ------- 10 files changed, 94 insertions(+), 74 deletions(-) diff --git a/src/mainboard/google/hatch/variants/akemi/gpio.c b/src/mainboard/google/hatch/variants/akemi/gpio.c index 0780ddb97a..41cf1410bc 100644 --- a/src/mainboard/google/hatch/variants/akemi/gpio.c +++ b/src/mainboard/google/hatch/variants/akemi/gpio.c @@ -19,18 +19,6 @@ #include static const struct pad_config ssd_sku_gpio_table[] = { - /* A0 : NC */ - PAD_NC(GPP_A0, NONE), - /* A6 : NC */ - PAD_NC(GPP_A6, NONE), - /* A8 : NC */ - PAD_NC(GPP_A8, NONE), - /* A10 : NC */ - PAD_NC(GPP_A10, NONE), - /* A11 : NC */ - PAD_NC(GPP_A11, NONE), - /* A12 : NC */ - PAD_NC(GPP_A12, NONE), /* A18 : NC */ PAD_NC(GPP_A18, NONE), /* A19 : NC */ @@ -90,18 +78,6 @@ static const struct pad_config ssd_sku_gpio_table[] = { }; static const struct pad_config gpio_table[] = { - /* A0 : NC */ - PAD_NC(GPP_A0, NONE), - /* A6 : NC */ - PAD_NC(GPP_A6, NONE), - /* A8 : NC */ - PAD_NC(GPP_A8, NONE), - /* A10 : NC */ - PAD_NC(GPP_A10, NONE), - /* A11 : NC */ - PAD_NC(GPP_A11, NONE), - /* A12 : NC */ - PAD_NC(GPP_A12, NONE), /* A18 : NC */ PAD_NC(GPP_A18, NONE), /* A19 : NC */ diff --git a/src/mainboard/google/hatch/variants/baseboard/gpio.c b/src/mainboard/google/hatch/variants/baseboard/gpio.c index 94cb2e53a2..42e9501d01 100644 --- a/src/mainboard/google/hatch/variants/baseboard/gpio.c +++ b/src/mainboard/google/hatch/variants/baseboard/gpio.c @@ -19,26 +19,26 @@ #include static const struct pad_config gpio_table[] = { - /* A0 : SAR0_INT_ODL */ - PAD_CFG_GPI_INT(GPP_A0, NONE, PLTRST, LEVEL), + /* A0 : GPP_A0 ==> NC */ + PAD_NC(GPP_A0, NONE), /* A1 : ESPI_IO0 */ /* A2 : ESPI_IO1 */ /* A3 : ESPI_IO2 */ /* A4 : ESPI_IO3 */ /* A5 : ESPI_CS# */ - /* A6 : SAR1_INT_ODL */ - PAD_CFG_GPI_INT(GPP_A6, NONE, PLTRST, LEVEL), + /* A6 : GPP_A6 ==> NC */ + PAD_NC(GPP_A6, NONE), /* A7 : PP3300_SOC_A */ PAD_NC(GPP_A7, NONE), - /* A8 : PEN_GARAGE_DET_L (wake) */ - PAD_CFG_GPI_SCI(GPP_A8, NONE, DEEP, EDGE_SINGLE, NONE), + /* A8 : GPP_A8 ==> NC */ + PAD_NC(GPP_A8, NONE), /* A9 : ESPI_CLK */ - /* A10 : FPMCU_PCH_BOOT1 */ - PAD_CFG_GPO(GPP_A10, 0, DEEP), - /* A11 : PCH_SPI_FPMCU_CS_L */ - PAD_CFG_NF(GPP_A11, NONE, DEEP, NF2), - /* A12 : FPMCU_RST_ODL */ - PAD_CFG_GPO(GPP_A12, 0, DEEP), + /* A10 : GPP_A10 ==> NC */ + PAD_NC(GPP_A10, NONE), + /* A11 : GPP_A11 ==> NC */ + PAD_NC(GPP_A11, NONE), + /* A12 : GPP_A12 ==> NC */ + PAD_NC(GPP_A12, NONE), /* A13 : SUSWARN_L */ PAD_CFG_NF(GPP_A13, NONE, DEEP, NF1), /* A14 : ESPI_RST_L */ diff --git a/src/mainboard/google/hatch/variants/dratini/gpio.c b/src/mainboard/google/hatch/variants/dratini/gpio.c index 30d56d78b8..b61748b268 100644 --- a/src/mainboard/google/hatch/variants/dratini/gpio.c +++ b/src/mainboard/google/hatch/variants/dratini/gpio.c @@ -19,14 +19,10 @@ #include static const struct pad_config gpio_table[] = { - /* A0 : NC */ - PAD_NC(GPP_A0, NONE), - /* A6 : NC */ - PAD_NC(GPP_A6, NONE), - /* A8 : NC */ - PAD_NC(GPP_A8, NONE), - /* A10 : NC */ - PAD_NC(GPP_A10, NONE), + /* A11 : PCH_SPI_FPMCU_CS_L */ + PAD_CFG_NF(GPP_A11, NONE, DEEP, NF2), + /* A12 : FPMCU_RST_ODL */ + PAD_CFG_GPO(GPP_A12, 0, DEEP), /* A18 : NC */ PAD_NC(GPP_A18, NONE), /* A19 : NC */ diff --git a/src/mainboard/google/hatch/variants/hatch/gpio.c b/src/mainboard/google/hatch/variants/hatch/gpio.c index 56f587b6b8..a2adf25371 100644 --- a/src/mainboard/google/hatch/variants/hatch/gpio.c +++ b/src/mainboard/google/hatch/variants/hatch/gpio.c @@ -19,6 +19,18 @@ #include static const struct pad_config gpio_table[] = { + /* A0 : SAR0_INT_ODL */ + PAD_CFG_GPI_INT(GPP_A0, NONE, PLTRST, LEVEL), + /* A6 : SAR1_INT_ODL */ + PAD_CFG_GPI_INT(GPP_A6, NONE, PLTRST, LEVEL), + /* A8 : PEN_GARAGE_DET_L (wake) */ + PAD_CFG_GPI_SCI(GPP_A8, NONE, DEEP, EDGE_SINGLE, NONE), + /* A10 : FPMCU_PCH_BOOT1 */ + PAD_CFG_GPO(GPP_A10, 0, DEEP), + /* A11 : PCH_SPI_FPMCU_CS_L */ + PAD_CFG_NF(GPP_A11, NONE, DEEP, NF2), + /* A12 : FPMCU_RST_ODL */ + PAD_CFG_GPO(GPP_A12, 0, DEEP), /* C13 : EC_PCH_INT_L */ PAD_CFG_GPI_APIC(GPP_C13, UP_20K, PLTRST, LEVEL, INVERT)}; diff --git a/src/mainboard/google/hatch/variants/helios/gpio.c b/src/mainboard/google/hatch/variants/helios/gpio.c index 456877c8ee..86630996e7 100644 --- a/src/mainboard/google/hatch/variants/helios/gpio.c +++ b/src/mainboard/google/hatch/variants/helios/gpio.c @@ -19,10 +19,14 @@ #include static const struct pad_config gpio_table[] = { - /* A0 : RCIN# ==> NC */ - PAD_NC(GPP_A0, NONE), - /* A6 : SERIRQ ==> NC */ - PAD_NC(GPP_A6, NONE), + /* A8 : PEN_GARAGE_DET_L (wake) */ + PAD_CFG_GPI_SCI(GPP_A8, NONE, DEEP, EDGE_SINGLE, NONE), + /* A10 : FPMCU_PCH_BOOT1 */ + PAD_CFG_GPO(GPP_A10, 0, DEEP), + /* A11 : PCH_SPI_FPMCU_CS_L */ + PAD_CFG_NF(GPP_A11, NONE, DEEP, NF2), + /* A12 : FPMCU_RST_ODL */ + PAD_CFG_GPO(GPP_A12, 0, DEEP), /* A18 : ISH_GP0 ==> NC */ PAD_NC(GPP_A18, NONE), /* A19 : ISH_GP1 ==> NC */ diff --git a/src/mainboard/google/hatch/variants/jinlon/gpio.c b/src/mainboard/google/hatch/variants/jinlon/gpio.c index 4622a72740..3cf2c9d13e 100644 --- a/src/mainboard/google/hatch/variants/jinlon/gpio.c +++ b/src/mainboard/google/hatch/variants/jinlon/gpio.c @@ -19,14 +19,10 @@ #include static const struct pad_config gpio_table[] = { - /* A0 : NC */ - PAD_NC(GPP_A0, NONE), - /* A6 : NC */ - PAD_NC(GPP_A6, NONE), - /* A8 : NC */ - PAD_NC(GPP_A8, NONE), - /* A10 : NC */ - PAD_NC(GPP_A10, NONE), + /* A11 : PCH_SPI_FPMCU_CS_L */ + PAD_CFG_NF(GPP_A11, NONE, DEEP, NF2), + /* A12 : FPMCU_RST_ODL */ + PAD_CFG_GPO(GPP_A12, 0, DEEP), /* C12 : FPMCU_PCH_BOOT1 */ PAD_CFG_GPO(GPP_C12, 0, DEEP), /* F3 : MEM_STRAP_3 */ diff --git a/src/mainboard/google/hatch/variants/kindred/gpio.c b/src/mainboard/google/hatch/variants/kindred/gpio.c index 9e2d818f9b..3c542437d6 100644 --- a/src/mainboard/google/hatch/variants/kindred/gpio.c +++ b/src/mainboard/google/hatch/variants/kindred/gpio.c @@ -19,6 +19,18 @@ #include static const struct pad_config ssd_sku_gpio_table[] = { + /* A0 : SAR0_INT_ODL */ + PAD_CFG_GPI_INT(GPP_A0, NONE, PLTRST, LEVEL), + /* A6 : SAR1_INT_ODL */ + PAD_CFG_GPI_INT(GPP_A6, NONE, PLTRST, LEVEL), + /* A8 : PEN_GARAGE_DET_L (wake) */ + PAD_CFG_GPI_SCI(GPP_A8, NONE, DEEP, EDGE_SINGLE, NONE), + /* A10 : FPMCU_PCH_BOOT1 */ + PAD_CFG_GPO(GPP_A10, 0, DEEP), + /* A11 : PCH_SPI_FPMCU_CS_L */ + PAD_CFG_NF(GPP_A11, NONE, DEEP, NF2), + /* A12 : FPMCU_RST_ODL */ + PAD_CFG_GPO(GPP_A12, 0, DEEP), /* F3 : MEM_STRAP_3 */ PAD_CFG_GPI(GPP_F3, NONE, PLTRST), /* F10 : MEM_STRAP_2 */ @@ -54,6 +66,18 @@ static const struct pad_config ssd_sku_gpio_table[] = { }; static const struct pad_config emmc_sku_gpio_table[] = { + /* A0 : SAR0_INT_ODL */ + PAD_CFG_GPI_INT(GPP_A0, NONE, PLTRST, LEVEL), + /* A6 : SAR1_INT_ODL */ + PAD_CFG_GPI_INT(GPP_A6, NONE, PLTRST, LEVEL), + /* A8 : PEN_GARAGE_DET_L (wake) */ + PAD_CFG_GPI_SCI(GPP_A8, NONE, DEEP, EDGE_SINGLE, NONE), + /* A10 : FPMCU_PCH_BOOT1 */ + PAD_CFG_GPO(GPP_A10, 0, DEEP), + /* A11 : PCH_SPI_FPMCU_CS_L */ + PAD_CFG_NF(GPP_A11, NONE, DEEP, NF2), + /* A12 : FPMCU_RST_ODL */ + PAD_CFG_GPO(GPP_A12, 0, DEEP), /* E1 : M2_SSD_PEDET ==> NC */ PAD_NC(GPP_E1, NONE), /* E4 : M2_SSD_PE_WAKE_ODL ==> NC */ @@ -95,6 +119,18 @@ static const struct pad_config emmc_sku_gpio_table[] = { }; static const struct pad_config gpio_table[] = { + /* A0 : SAR0_INT_ODL */ + PAD_CFG_GPI_INT(GPP_A0, NONE, PLTRST, LEVEL), + /* A6 : SAR1_INT_ODL */ + PAD_CFG_GPI_INT(GPP_A6, NONE, PLTRST, LEVEL), + /* A8 : PEN_GARAGE_DET_L (wake) */ + PAD_CFG_GPI_SCI(GPP_A8, NONE, DEEP, EDGE_SINGLE, NONE), + /* A10 : FPMCU_PCH_BOOT1 */ + PAD_CFG_GPO(GPP_A10, 0, DEEP), + /* A11 : PCH_SPI_FPMCU_CS_L */ + PAD_CFG_NF(GPP_A11, NONE, DEEP, NF2), + /* A12 : FPMCU_RST_ODL */ + PAD_CFG_GPO(GPP_A12, 0, DEEP), /* F3 : MEM_STRAP_3 */ PAD_CFG_GPI(GPP_F3, NONE, PLTRST), /* F10 : MEM_STRAP_2 */ diff --git a/src/mainboard/google/hatch/variants/kohaku/gpio.c b/src/mainboard/google/hatch/variants/kohaku/gpio.c index f52cc27724..837abb3e8b 100644 --- a/src/mainboard/google/hatch/variants/kohaku/gpio.c +++ b/src/mainboard/google/hatch/variants/kohaku/gpio.c @@ -19,12 +19,12 @@ #include static const struct pad_config gpio_table[] = { - /* A0 : RCIN# ==> NC */ - PAD_NC(GPP_A0, NONE), - /* A6 : SERIRQ ==> NC */ - PAD_NC(GPP_A6, NONE), - /* A10 : GPP_A10 ==> NC */ - PAD_NC(GPP_A10, NONE), + /* A8 : PEN_GARAGE_DET_L (wake) */ + PAD_CFG_GPI_SCI(GPP_A8, NONE, DEEP, EDGE_SINGLE, NONE), + /* A11 : PCH_SPI_FPMCU_CS_L */ + PAD_CFG_NF(GPP_A11, NONE, DEEP, NF2), + /* A12 : FPMCU_RST_ODL */ + PAD_CFG_GPO(GPP_A12, 0, DEEP), /* A16 : EMR_GARAGE_DET (notification) */ PAD_CFG_GPI_GPIO_DRIVER(GPP_A16, NONE, PLTRST), /* A17 : PIRQA# ==> NC */ diff --git a/src/mainboard/google/hatch/variants/mushu/gpio.c b/src/mainboard/google/hatch/variants/mushu/gpio.c index 56f587b6b8..a2adf25371 100644 --- a/src/mainboard/google/hatch/variants/mushu/gpio.c +++ b/src/mainboard/google/hatch/variants/mushu/gpio.c @@ -19,6 +19,18 @@ #include static const struct pad_config gpio_table[] = { + /* A0 : SAR0_INT_ODL */ + PAD_CFG_GPI_INT(GPP_A0, NONE, PLTRST, LEVEL), + /* A6 : SAR1_INT_ODL */ + PAD_CFG_GPI_INT(GPP_A6, NONE, PLTRST, LEVEL), + /* A8 : PEN_GARAGE_DET_L (wake) */ + PAD_CFG_GPI_SCI(GPP_A8, NONE, DEEP, EDGE_SINGLE, NONE), + /* A10 : FPMCU_PCH_BOOT1 */ + PAD_CFG_GPO(GPP_A10, 0, DEEP), + /* A11 : PCH_SPI_FPMCU_CS_L */ + PAD_CFG_NF(GPP_A11, NONE, DEEP, NF2), + /* A12 : FPMCU_RST_ODL */ + PAD_CFG_GPO(GPP_A12, 0, DEEP), /* C13 : EC_PCH_INT_L */ PAD_CFG_GPI_APIC(GPP_C13, UP_20K, PLTRST, LEVEL, INVERT)}; diff --git a/src/mainboard/google/hatch/variants/stryke/gpio.c b/src/mainboard/google/hatch/variants/stryke/gpio.c index 4d27554a6b..4fdbe6aa39 100644 --- a/src/mainboard/google/hatch/variants/stryke/gpio.c +++ b/src/mainboard/google/hatch/variants/stryke/gpio.c @@ -19,18 +19,6 @@ #include static const struct pad_config gpio_table[] = { - /* A0 : NC */ - PAD_NC(GPP_A0, NONE), - /* A6 : NC */ - PAD_NC(GPP_A6, NONE), - /* A8 : NC */ - PAD_NC(GPP_A8, NONE), - /* A10 : NC */ - PAD_NC(GPP_A10, NONE), - /* A11 : NC */ - PAD_NC(GPP_A11, NONE), - /* A12 : NC */ - PAD_NC(GPP_A12, NONE), /* A22 : NC */ PAD_NC(GPP_A22, NONE), /* A23 : NC */ From 3dbe593906d22ddcd113cad9065b38115d0163a6 Mon Sep 17 00:00:00 2001 From: Edward O'Callaghan Date: Tue, 24 Dec 2019 15:15:35 +1100 Subject: [PATCH 0820/1242] mainboard/google/hatch: Move gpio GPP_C* NC down into baseboard The baseboard GPIO table definitions are too straineous to the extend that variants need to redefine assumptions back to NC. Invert this so that baseboard by default assumes the safer NC and move the specific board configurations to their respective places. This patch handles the GPP_C15 group for easier review. BUG=b:142094759 BRANCH=none TEST=builds Change-Id: I578245e24895d361d80ad016a4f18204e2b6e1ca Signed-off-by: Edward O'Callaghan Reviewed-on: https://review.coreboot.org/c/coreboot/+/37921 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh --- .../google/hatch/variants/akemi/gpio.c | 4 ---- .../google/hatch/variants/baseboard/gpio.c | 8 ++------ .../google/hatch/variants/dratini/gpio.c | 2 -- .../google/hatch/variants/hatch/gpio.c | 9 ++++++++- .../google/hatch/variants/helios/gpio.c | 2 -- .../google/hatch/variants/jinlon/gpio.c | 6 ++++++ .../google/hatch/variants/kindred/gpio.c | 18 ++++++++++++++++++ .../google/hatch/variants/mushu/gpio.c | 9 ++++++++- .../google/hatch/variants/stryke/gpio.c | 6 ++++++ 9 files changed, 48 insertions(+), 16 deletions(-) diff --git a/src/mainboard/google/hatch/variants/akemi/gpio.c b/src/mainboard/google/hatch/variants/akemi/gpio.c index 41cf1410bc..0e3e46feb8 100644 --- a/src/mainboard/google/hatch/variants/akemi/gpio.c +++ b/src/mainboard/google/hatch/variants/akemi/gpio.c @@ -35,8 +35,6 @@ static const struct pad_config ssd_sku_gpio_table[] = { PAD_NC(GPP_B22, NONE), /* C11 : NC */ PAD_NC(GPP_C11, NONE), - /* C15 : NC */ - PAD_NC(GPP_C15, NONE), /* F1 : NC */ PAD_NC(GPP_F1, NONE), /* F3 : MEM_STRAP_3 */ @@ -94,8 +92,6 @@ static const struct pad_config gpio_table[] = { PAD_NC(GPP_B22, NONE), /* C11 : NC */ PAD_NC(GPP_C11, NONE), - /* C15 : NC */ - PAD_NC(GPP_C15, NONE), /* F1 : NC */ PAD_NC(GPP_F1, NONE), /* F3 : MEM_STRAP_3 */ diff --git a/src/mainboard/google/hatch/variants/baseboard/gpio.c b/src/mainboard/google/hatch/variants/baseboard/gpio.c index 42e9501d01..2c3bf8d546 100644 --- a/src/mainboard/google/hatch/variants/baseboard/gpio.c +++ b/src/mainboard/google/hatch/variants/baseboard/gpio.c @@ -140,12 +140,8 @@ static const struct pad_config gpio_table[] = { PAD_CFG_GPI_APIC(GPP_C13, NONE, PLTRST, LEVEL, INVERT), /* C14 : BT_DISABLE_L */ PAD_CFG_GPO(GPP_C14, 1, DEEP), - /* C15 : WWAN_DPR_SAR_ODL - * - * TODO: Driver doesn't use this pin as of now. In case driver starts - * using this pin, expose this pin to driver. - */ - PAD_CFG_GPO(GPP_C15, 1, DEEP), + /* C15 : NC */ + PAD_NC(GPP_C15, NONE), /* C16 : PCH_I2C_TRACKPAD_SDA */ PAD_CFG_NF(GPP_C16, NONE, DEEP, NF1), /* C17 : PCH_I2C_TRACKPAD_SCL */ diff --git a/src/mainboard/google/hatch/variants/dratini/gpio.c b/src/mainboard/google/hatch/variants/dratini/gpio.c index b61748b268..204715b216 100644 --- a/src/mainboard/google/hatch/variants/dratini/gpio.c +++ b/src/mainboard/google/hatch/variants/dratini/gpio.c @@ -29,8 +29,6 @@ static const struct pad_config gpio_table[] = { PAD_NC(GPP_A19, NONE), /* C12 : FPMCU_PCH_BOOT1 */ PAD_CFG_GPO(GPP_C12, 0, DEEP), - /* C15 : NC */ - PAD_NC(GPP_C15, NONE), /* F1 : NC */ PAD_NC(GPP_F1, NONE), /* F3 : MEM_STRAP_3 */ diff --git a/src/mainboard/google/hatch/variants/hatch/gpio.c b/src/mainboard/google/hatch/variants/hatch/gpio.c index a2adf25371..862b28fe4a 100644 --- a/src/mainboard/google/hatch/variants/hatch/gpio.c +++ b/src/mainboard/google/hatch/variants/hatch/gpio.c @@ -32,7 +32,14 @@ static const struct pad_config gpio_table[] = { /* A12 : FPMCU_RST_ODL */ PAD_CFG_GPO(GPP_A12, 0, DEEP), /* C13 : EC_PCH_INT_L */ - PAD_CFG_GPI_APIC(GPP_C13, UP_20K, PLTRST, LEVEL, INVERT)}; + PAD_CFG_GPI_APIC(GPP_C13, UP_20K, PLTRST, LEVEL, INVERT), + /* C15 : WWAN_DPR_SAR_ODL + * + * TODO: Driver doesn't use this pin as of now. In case driver starts + * using this pin, expose this pin to driver. + */ + PAD_CFG_GPO(GPP_C15, 1, DEEP), +}; const struct pad_config *override_gpio_table(size_t *num) { diff --git a/src/mainboard/google/hatch/variants/helios/gpio.c b/src/mainboard/google/hatch/variants/helios/gpio.c index 86630996e7..afe1c85160 100644 --- a/src/mainboard/google/hatch/variants/helios/gpio.c +++ b/src/mainboard/google/hatch/variants/helios/gpio.c @@ -43,8 +43,6 @@ static const struct pad_config gpio_table[] = { PAD_NC(GPP_C6, NONE), /* C7 : GPP_C7 ==> NC */ PAD_NC(GPP_C7, NONE), - /* C15 : UART1_CTS# ==> NC */ - PAD_NC(GPP_C15, NONE), /* C23 : UART2_CTS# ==> NC */ PAD_NC(GPP_C23, NONE), /* D5 : ISH_I2C0_SDA ==> NC */ diff --git a/src/mainboard/google/hatch/variants/jinlon/gpio.c b/src/mainboard/google/hatch/variants/jinlon/gpio.c index 3cf2c9d13e..7d2ecf279c 100644 --- a/src/mainboard/google/hatch/variants/jinlon/gpio.c +++ b/src/mainboard/google/hatch/variants/jinlon/gpio.c @@ -25,6 +25,12 @@ static const struct pad_config gpio_table[] = { PAD_CFG_GPO(GPP_A12, 0, DEEP), /* C12 : FPMCU_PCH_BOOT1 */ PAD_CFG_GPO(GPP_C12, 0, DEEP), + /* C15 : WWAN_DPR_SAR_ODL + * + * TODO: Driver doesn't use this pin as of now. In case driver starts + * using this pin, expose this pin to driver. + */ + PAD_CFG_GPO(GPP_C15, 1, DEEP), /* F3 : MEM_STRAP_3 */ PAD_CFG_GPI(GPP_F3, NONE, PLTRST), /* F10 : MEM_STRAP_2 */ diff --git a/src/mainboard/google/hatch/variants/kindred/gpio.c b/src/mainboard/google/hatch/variants/kindred/gpio.c index 3c542437d6..19956b4f1e 100644 --- a/src/mainboard/google/hatch/variants/kindred/gpio.c +++ b/src/mainboard/google/hatch/variants/kindred/gpio.c @@ -31,6 +31,12 @@ static const struct pad_config ssd_sku_gpio_table[] = { PAD_CFG_NF(GPP_A11, NONE, DEEP, NF2), /* A12 : FPMCU_RST_ODL */ PAD_CFG_GPO(GPP_A12, 0, DEEP), + /* C15 : WWAN_DPR_SAR_ODL + * + * TODO: Driver doesn't use this pin as of now. In case driver starts + * using this pin, expose this pin to driver. + */ + PAD_CFG_GPO(GPP_C15, 1, DEEP), /* F3 : MEM_STRAP_3 */ PAD_CFG_GPI(GPP_F3, NONE, PLTRST), /* F10 : MEM_STRAP_2 */ @@ -84,6 +90,12 @@ static const struct pad_config emmc_sku_gpio_table[] = { PAD_NC(GPP_E4, NONE), /* E5 : SATA_DEVSLP1 ==> NC */ PAD_NC(GPP_E5, NONE), + /* C15 : WWAN_DPR_SAR_ODL + * + * TODO: Driver doesn't use this pin as of now. In case driver starts + * using this pin, expose this pin to driver. + */ + PAD_CFG_GPO(GPP_C15, 1, DEEP), /* F3 : MEM_STRAP_3 */ PAD_CFG_GPI(GPP_F3, NONE, PLTRST), /* F10 : MEM_STRAP_2 */ @@ -131,6 +143,12 @@ static const struct pad_config gpio_table[] = { PAD_CFG_NF(GPP_A11, NONE, DEEP, NF2), /* A12 : FPMCU_RST_ODL */ PAD_CFG_GPO(GPP_A12, 0, DEEP), + /* C15 : WWAN_DPR_SAR_ODL + * + * TODO: Driver doesn't use this pin as of now. In case driver starts + * using this pin, expose this pin to driver. + */ + PAD_CFG_GPO(GPP_C15, 1, DEEP), /* F3 : MEM_STRAP_3 */ PAD_CFG_GPI(GPP_F3, NONE, PLTRST), /* F10 : MEM_STRAP_2 */ diff --git a/src/mainboard/google/hatch/variants/mushu/gpio.c b/src/mainboard/google/hatch/variants/mushu/gpio.c index a2adf25371..862b28fe4a 100644 --- a/src/mainboard/google/hatch/variants/mushu/gpio.c +++ b/src/mainboard/google/hatch/variants/mushu/gpio.c @@ -32,7 +32,14 @@ static const struct pad_config gpio_table[] = { /* A12 : FPMCU_RST_ODL */ PAD_CFG_GPO(GPP_A12, 0, DEEP), /* C13 : EC_PCH_INT_L */ - PAD_CFG_GPI_APIC(GPP_C13, UP_20K, PLTRST, LEVEL, INVERT)}; + PAD_CFG_GPI_APIC(GPP_C13, UP_20K, PLTRST, LEVEL, INVERT), + /* C15 : WWAN_DPR_SAR_ODL + * + * TODO: Driver doesn't use this pin as of now. In case driver starts + * using this pin, expose this pin to driver. + */ + PAD_CFG_GPO(GPP_C15, 1, DEEP), +}; const struct pad_config *override_gpio_table(size_t *num) { diff --git a/src/mainboard/google/hatch/variants/stryke/gpio.c b/src/mainboard/google/hatch/variants/stryke/gpio.c index 4fdbe6aa39..4d0eba9ed1 100644 --- a/src/mainboard/google/hatch/variants/stryke/gpio.c +++ b/src/mainboard/google/hatch/variants/stryke/gpio.c @@ -33,6 +33,12 @@ static const struct pad_config gpio_table[] = { PAD_NC(GPP_C11, NONE), /* C12 : NC */ PAD_NC(GPP_C12, NONE), + /* C15 : WWAN_DPR_SAR_ODL + * + * TODO: Driver doesn't use this pin as of now. In case driver starts + * using this pin, expose this pin to driver. + */ + PAD_CFG_GPO(GPP_C15, 1, DEEP), /* F1 : NC */ PAD_NC(GPP_F1, NONE), /* F3 : MEM_STRAP_3 */ From c735a31861d4d2fba4060184ef136b77166158b3 Mon Sep 17 00:00:00 2001 From: Edward O'Callaghan Date: Tue, 24 Dec 2019 15:35:44 +1100 Subject: [PATCH 0821/1242] mainboard/google/hatch: Move gpio GPP_H3 config up from baseboard The baseboard GPIO table definitions are too straineous to the extend that variants need to redefine assumptions back to NC. Invert this so that baseboard by default assumes the safer NC and move the specific board configurations to their respective places. This patch handles the GPP_H3 gpio config for easier review. This toggles the MAX amp which not all boards have. Move the pin configuration to boards with the respective devicetree configuration following on from the theme of commit b417786525. BUG=b:142094759 BRANCH=none TEST=builds Change-Id: Iefd2223af79a13c8a42d07bc10b2772dbff6d3e5 Signed-off-by: Edward O'Callaghan Reviewed-on: https://review.coreboot.org/c/coreboot/+/37922 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh --- src/mainboard/google/hatch/variants/akemi/gpio.c | 2 ++ src/mainboard/google/hatch/variants/baseboard/gpio.c | 4 ++-- src/mainboard/google/hatch/variants/dratini/gpio.c | 2 ++ src/mainboard/google/hatch/variants/jinlon/gpio.c | 2 ++ src/mainboard/google/hatch/variants/kindred/gpio.c | 6 ++++++ src/mainboard/google/hatch/variants/kohaku/gpio.c | 2 ++ src/mainboard/google/hatch/variants/mushu/gpio.c | 2 ++ src/mainboard/google/hatch/variants/stryke/gpio.c | 2 ++ 8 files changed, 20 insertions(+), 2 deletions(-) diff --git a/src/mainboard/google/hatch/variants/akemi/gpio.c b/src/mainboard/google/hatch/variants/akemi/gpio.c index 0e3e46feb8..cfc185e9a5 100644 --- a/src/mainboard/google/hatch/variants/akemi/gpio.c +++ b/src/mainboard/google/hatch/variants/akemi/gpio.c @@ -122,6 +122,8 @@ static const struct pad_config gpio_table[] = { PAD_CFG_NF(GPP_F21, NONE, DEEP, NF1), /* F22 : EMMC_RESET# ==> EMMC_RST_L */ PAD_CFG_NF(GPP_F22, NONE, DEEP, NF1), + /* H3 : SPKR_PA_EN */ + PAD_CFG_GPO(GPP_H3, 0, DEEP), /* H6 : NC */ PAD_NC(GPP_H6, NONE), /* H7 : NC */ diff --git a/src/mainboard/google/hatch/variants/baseboard/gpio.c b/src/mainboard/google/hatch/variants/baseboard/gpio.c index 2c3bf8d546..dcd987fbb4 100644 --- a/src/mainboard/google/hatch/variants/baseboard/gpio.c +++ b/src/mainboard/google/hatch/variants/baseboard/gpio.c @@ -334,8 +334,8 @@ static const struct pad_config gpio_table[] = { PAD_CFG_NF(GPP_H1, NONE, DEEP, NF3), /* H2 : CNV_CLKREQ0 */ PAD_CFG_NF(GPP_H2, NONE, DEEP, NF3), - /* H3 : SPKR_PA_EN */ - PAD_CFG_GPO(GPP_H3, 0, DEEP), + /* H3 : GPP_H3 ==> NC */ + PAD_NC(GPP_H3, NONE), /* H4 : PCH_I2C_PEN_SDA */ PAD_NC(GPP_H4, NONE), /* H5 : PCH_I2C_PEN_SCL */ diff --git a/src/mainboard/google/hatch/variants/dratini/gpio.c b/src/mainboard/google/hatch/variants/dratini/gpio.c index 204715b216..fd59060756 100644 --- a/src/mainboard/google/hatch/variants/dratini/gpio.c +++ b/src/mainboard/google/hatch/variants/dratini/gpio.c @@ -59,6 +59,8 @@ static const struct pad_config gpio_table[] = { PAD_CFG_NF(GPP_F21, NONE, DEEP, NF1), /* F22 : EMMC_RESET# ==> EMMC_RST_L */ PAD_CFG_NF(GPP_F22, NONE, DEEP, NF1), + /* H3 : SPKR_PA_EN */ + PAD_CFG_GPO(GPP_H3, 0, DEEP), /* H19 : MEM_STRAP_0 */ PAD_CFG_GPI(GPP_H19, NONE, PLTRST), /* H22 : MEM_STRAP_1 */ diff --git a/src/mainboard/google/hatch/variants/jinlon/gpio.c b/src/mainboard/google/hatch/variants/jinlon/gpio.c index 7d2ecf279c..12d96d8496 100644 --- a/src/mainboard/google/hatch/variants/jinlon/gpio.c +++ b/src/mainboard/google/hatch/variants/jinlon/gpio.c @@ -59,6 +59,8 @@ static const struct pad_config gpio_table[] = { PAD_NC(GPP_F21, NONE), /* F22 : EMMC_RESET# ==> NC */ PAD_NC(GPP_F22, NONE), + /* H3 : SPKR_PA_EN */ + PAD_CFG_GPO(GPP_H3, 0, DEEP), /* H19 : MEM_STRAP_0 */ PAD_CFG_GPI(GPP_H19, NONE, PLTRST), /* H22 : MEM_STRAP_1 */ diff --git a/src/mainboard/google/hatch/variants/kindred/gpio.c b/src/mainboard/google/hatch/variants/kindred/gpio.c index 19956b4f1e..fbb47f95de 100644 --- a/src/mainboard/google/hatch/variants/kindred/gpio.c +++ b/src/mainboard/google/hatch/variants/kindred/gpio.c @@ -65,6 +65,8 @@ static const struct pad_config ssd_sku_gpio_table[] = { PAD_NC(GPP_F21, NONE), /* F22 : EMMC_RESET# ==> NC */ PAD_NC(GPP_F22, NONE), + /* H3 : SPKR_PA_EN */ + PAD_CFG_GPO(GPP_H3, 0, DEEP), /* H19 : MEM_STRAP_0 */ PAD_CFG_GPI(GPP_H19, NONE, PLTRST), /* H22 : MEM_STRAP_1 */ @@ -124,6 +126,8 @@ static const struct pad_config emmc_sku_gpio_table[] = { PAD_CFG_NF(GPP_F21, NONE, DEEP, NF1), /* F22 : EMMC_RESET# ==> EMMC_RST_L */ PAD_CFG_NF(GPP_F22, NONE, DEEP, NF1), + /* H3 : SPKR_PA_EN */ + PAD_CFG_GPO(GPP_H3, 0, DEEP), /* H19 : MEM_STRAP_0 */ PAD_CFG_GPI(GPP_H19, NONE, PLTRST), /* H22 : MEM_STRAP_1 */ @@ -177,6 +181,8 @@ static const struct pad_config gpio_table[] = { PAD_CFG_NF(GPP_F21, NONE, DEEP, NF1), /* F22 : EMMC_RESET# ==> EMMC_RST_L */ PAD_CFG_NF(GPP_F22, NONE, DEEP, NF1), + /* H3 : SPKR_PA_EN */ + PAD_CFG_GPO(GPP_H3, 0, DEEP), /* H19 : MEM_STRAP_0 */ PAD_CFG_GPI(GPP_H19, NONE, PLTRST), /* H22 : MEM_STRAP_1 */ diff --git a/src/mainboard/google/hatch/variants/kohaku/gpio.c b/src/mainboard/google/hatch/variants/kohaku/gpio.c index 837abb3e8b..8fd203d18d 100644 --- a/src/mainboard/google/hatch/variants/kohaku/gpio.c +++ b/src/mainboard/google/hatch/variants/kohaku/gpio.c @@ -77,6 +77,8 @@ static const struct pad_config gpio_table[] = { PAD_NC(GPP_G5, NONE), /* G6 : GPP_G6 ==> NC */ PAD_NC(GPP_G6, NONE), + /* H3 : SPKR_PA_EN */ + PAD_CFG_GPO(GPP_H3, 0, DEEP), /* H4 : PCH_I2C_PEN_SDA */ PAD_CFG_NF(GPP_H4, NONE, DEEP, NF1), /* H5 : PCH_I2C_PEN_SCL */ diff --git a/src/mainboard/google/hatch/variants/mushu/gpio.c b/src/mainboard/google/hatch/variants/mushu/gpio.c index 862b28fe4a..09e159492c 100644 --- a/src/mainboard/google/hatch/variants/mushu/gpio.c +++ b/src/mainboard/google/hatch/variants/mushu/gpio.c @@ -39,6 +39,8 @@ static const struct pad_config gpio_table[] = { * using this pin, expose this pin to driver. */ PAD_CFG_GPO(GPP_C15, 1, DEEP), + /* H3 : SPKR_PA_EN */ + PAD_CFG_GPO(GPP_H3, 0, DEEP), }; const struct pad_config *override_gpio_table(size_t *num) diff --git a/src/mainboard/google/hatch/variants/stryke/gpio.c b/src/mainboard/google/hatch/variants/stryke/gpio.c index 4d0eba9ed1..82ffb6cb61 100644 --- a/src/mainboard/google/hatch/variants/stryke/gpio.c +++ b/src/mainboard/google/hatch/variants/stryke/gpio.c @@ -53,6 +53,8 @@ static const struct pad_config gpio_table[] = { PAD_NC(GPP_F21, NONE), /* F22 : NC */ PAD_NC(GPP_F22, NONE), + /* H3 : SPKR_PA_EN */ + PAD_CFG_GPO(GPP_H3, 0, DEEP), /* H19 : MEM_STRAP_0 */ PAD_CFG_GPI(GPP_H19, NONE, PLTRST), /* H22 : MEM_STRAP_1 */ From 7899cd9088e5d8c837c69d3b4d931db84ab9e65a Mon Sep 17 00:00:00 2001 From: Edward O'Callaghan Date: Mon, 9 Dec 2019 16:38:23 +1100 Subject: [PATCH 0822/1242] mb/google/hatch/variant/kohaku: Fix Kohaku baseboard/gpio.c mux comments Follow MEM_STRAP_* comment style to be consistent with other boards. BUG=b:144809606 BRANCH=hatch TEST=./util/abuild/abuild -p none -t google/hatch -x -a Change-Id: I4945f676f307af9b8c0baa1fbcaf33113de647c3 Signed-off-by: Edward O'Callaghan Reviewed-on: https://review.coreboot.org/c/coreboot/+/37592 Reviewed-by: Furquan Shaikh Tested-by: build bot (Jenkins) --- src/mainboard/google/hatch/variants/kohaku/gpio.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/src/mainboard/google/hatch/variants/kohaku/gpio.c b/src/mainboard/google/hatch/variants/kohaku/gpio.c index 8fd203d18d..921b8dd1e9 100644 --- a/src/mainboard/google/hatch/variants/kohaku/gpio.c +++ b/src/mainboard/google/hatch/variants/kohaku/gpio.c @@ -55,13 +55,13 @@ static const struct pad_config gpio_table[] = { PAD_NC(GPP_E23, NONE), /* F1 : GPP_F1 ==> NC */ PAD_NC(GPP_F1, NONE), - /* F11 : PCH_MEM_STRAP2 */ + /* F11 : PCH_MEM_STRAP_2 */ PAD_CFG_GPI(GPP_F11, NONE, PLTRST), - /* F20 : PCH_MEM_STRAP0 */ + /* F20 : PCH_MEM_STRAP_0 */ PAD_CFG_GPI(GPP_F20, NONE, PLTRST), - /* F21 : PCH_MEM_STRAP1 */ + /* F21 : PCH_MEM_STRAP_1 */ PAD_CFG_GPI(GPP_F21, NONE, PLTRST), - /* F22 : PCH_MEM_STRAP3 */ + /* F22 : PCH_MEM_STRAP_3 */ PAD_CFG_GPI(GPP_F22, NONE, PLTRST), /* G0 : GPP_G0 ==> NC */ PAD_NC(GPP_G0, NONE), From d33b02e7f3323e94bc093edebf0bb430c9676de6 Mon Sep 17 00:00:00 2001 From: Edward O'Callaghan Date: Mon, 23 Dec 2019 19:44:14 +1100 Subject: [PATCH 0823/1242] mainboard/google/puff: Add GPIO configuration BUG=b:144809606,142094759 BRANCH=none TEST=none Change-Id: Iae20d2262c910044dde84f10d795f4aee3318532 Signed-off-by: Edward O'Callaghan Signed-off-by: Kangheui Won Co-Author: Kangheui Won Reviewed-on: https://review.coreboot.org/c/coreboot/+/37925 Reviewed-by: Furquan Shaikh Tested-by: build bot (Jenkins) --- .../google/hatch/variants/puff/gpio.c | 70 +++++++++++++++++++ 1 file changed, 70 insertions(+) diff --git a/src/mainboard/google/hatch/variants/puff/gpio.c b/src/mainboard/google/hatch/variants/puff/gpio.c index b8b54d3c9c..57327fed9a 100644 --- a/src/mainboard/google/hatch/variants/puff/gpio.c +++ b/src/mainboard/google/hatch/variants/puff/gpio.c @@ -17,6 +17,76 @@ #include #include +static const struct pad_config gpio_table[] = { + /* A16 : SD_OC_ODL */ + PAD_CFG_GPI(GPP_A16, NONE, DEEP), + /* A18 : LAN_PE_ISOLATE_ODL */ + PAD_CFG_GPO(GPP_A18, 1, DEEP), + /* A23 : M2_WLAN_INT_ODL */ + PAD_CFG_GPI_APIC(GPP_A23, NONE, PLTRST, LEVEL, INVERT), + + /* B5 : LAN_CLKREQ_ODL */ + PAD_CFG_NF(GPP_B5, NONE, DEEP, NF1), + + /* C0 : SMBCLK */ + PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1), + /* C1 : SMBDATA */ + PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1), + /* C6: M2_WLAN_WAKE_ODL */ + PAD_CFG_GPI_SCI_LOW(GPP_C6, NONE, DEEP, EDGE_SINGLE), + /* C7 : LAN_WAKE_ODL */ + PAD_CFG_GPI_SCI_LOW(GPP_C7, NONE, DEEP, EDGE_SINGLE), + /* C10 : PCH_PCON_RST_ODL */ + PAD_CFG_GPO(GPP_C10, 1, DEEP), + /* C11 : PCH_PCON_PDB_ODL */ + PAD_CFG_GPO(GPP_C11, 1, DEEP), + + /* E2 : EN_PP_MST_OD */ + PAD_CFG_GPO(GPP_E2, 1, DEEP), + /* E9 : USB_A0_OC_ODL */ + PAD_CFG_NF(GPP_E9, NONE, DEEP, NF1), + /* E10 : USB_A1_OC_ODL */ + PAD_CFG_NF(GPP_E10, NONE, DEEP, NF1), + + /* F11 : EMMC_CMD */ + PAD_CFG_NF(GPP_F11, NONE, DEEP, NF1), + /* F12 : EMMC_DATA0 */ + PAD_CFG_NF(GPP_F12, NONE, DEEP, NF1), + /* F13 : EMMC_DATA1 */ + PAD_CFG_NF(GPP_F13, NONE, DEEP, NF1), + /* F14 : EMMC_DATA2 */ + PAD_CFG_NF(GPP_F14, NONE, DEEP, NF1), + /* F15 : EMMC_DATA3 */ + PAD_CFG_NF(GPP_F15, NONE, DEEP, NF1), + /* F16 : EMMC_DATA4 */ + PAD_CFG_NF(GPP_F16, NONE, DEEP, NF1), + /* F17 : EMMC_DATA5 */ + PAD_CFG_NF(GPP_F17, NONE, DEEP, NF1), + /* F18 : EMMC_DATA6 */ + PAD_CFG_NF(GPP_F18, NONE, DEEP, NF1), + /* F19 : EMMC_DATA7 */ + PAD_CFG_NF(GPP_F19, NONE, DEEP, NF1), + /* F20 : EMMC_RCLK */ + PAD_CFG_NF(GPP_F20, NONE, DEEP, NF1), + /* F21 : EMMC_CLK */ + PAD_CFG_NF(GPP_F21, NONE, DEEP, NF1), + /* F22 : EMMC_RST_L */ + PAD_CFG_NF(GPP_F22, NONE, DEEP, NF1), + + /* H4: PCH_I2C_PCON_SDA */ + PAD_CFG_NF(GPP_H4, NONE, DEEP, NF1), + /* H5: PCH_I2C_PCON_SCL */ + PAD_CFG_NF(GPP_H5, NONE, DEEP, NF1), + /* H22 : PWM_PP3300_BIOZZER */ + PAD_CFG_GPO(GPP_H22, 0, DEEP), +}; + +const struct pad_config *override_gpio_table(size_t *num) +{ + *num = ARRAY_SIZE(gpio_table); + return gpio_table; +} + /* Early pad configuration in bootblock */ static const struct pad_config early_gpio_table[] = { /* B14 : GPP_B14_STRAP */ From b824f7dbae82f9dba336b2f29f2f9ed9b3e617aa Mon Sep 17 00:00:00 2001 From: Patrick Rudolph Date: Mon, 9 Dec 2019 08:56:39 +0100 Subject: [PATCH 0824/1242] soc/intel/skylake/vr_config: Use lookup table by default MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit If the board doesn't provide VRconfig in devicetree make sure to use the lookup table for IccMax instead of defaults for some mobile SoC. Also use decimal values instead of hex. Change-Id: If31063f9b483a3bbd6cc90df1c1b76b4efc66445 Signed-off-by: Patrick Rudolph Reviewed-on: https://review.coreboot.org/c/coreboot/+/37598 Reviewed-by: Maxim Polyakov Reviewed-by: Michael Niewöhner Tested-by: build bot (Jenkins) --- src/soc/intel/skylake/vr_config.c | 25 +++++++++++++------------ 1 file changed, 13 insertions(+), 12 deletions(-) diff --git a/src/soc/intel/skylake/vr_config.c b/src/soc/intel/skylake/vr_config.c index 54dfd31ebe..9a4ddd899a 100644 --- a/src/soc/intel/skylake/vr_config.c +++ b/src/soc/intel/skylake/vr_config.c @@ -31,9 +31,9 @@ static const struct vr_config default_configs[NUM_VR_DOMAINS] = { .psi3threshold = VR_CFG_AMP(1), .psi3enable = 0, .psi4enable = 0, - .imon_slope = 0x0, - .imon_offset = 0x0, - .icc_max = VR_CFG_AMP(7), + .imon_slope = 0, + .imon_offset = 0, + .icc_max = 0, .voltage_limit = 1520, }, [VR_IA_CORE] = { @@ -43,9 +43,9 @@ static const struct vr_config default_configs[NUM_VR_DOMAINS] = { .psi3threshold = VR_CFG_AMP(1), .psi3enable = 0, .psi4enable = 0, - .imon_slope = 0x0, - .imon_offset = 0x0, - .icc_max = VR_CFG_AMP(34), + .imon_slope = 0, + .imon_offset = 0, + .icc_max = 0, .voltage_limit = 1520, }, [VR_GT_UNSLICED] = { @@ -55,9 +55,9 @@ static const struct vr_config default_configs[NUM_VR_DOMAINS] = { .psi3threshold = VR_CFG_AMP(1), .psi3enable = 0, .psi4enable = 0, - .imon_slope = 0x0, - .imon_offset = 0x0, - .icc_max = VR_CFG_AMP(35), + .imon_slope = 0, + .imon_offset = 0, + .icc_max = 0, .voltage_limit = 1520, }, [VR_GT_SLICED] = { @@ -67,9 +67,9 @@ static const struct vr_config default_configs[NUM_VR_DOMAINS] = { .psi3threshold = VR_CFG_AMP(1), .psi3enable = 0, .psi4enable = 0, - .imon_slope = 0x0, - .imon_offset = 0x0, - .icc_max = VR_CFG_AMP(35), + .imon_slope = 0, + .imon_offset = 0, + .icc_max = 0, .voltage_limit = 1520, }, }; @@ -334,6 +334,7 @@ void fill_vr_domain_config(void *params, vr_params->Psi4Enable[domain] = cfg->psi4enable; vr_params->ImonSlope[domain] = cfg->imon_slope; vr_params->ImonOffset[domain] = cfg->imon_offset; + /* If board provided non-zero value, use it. */ if (cfg->icc_max) vr_params->IccMax[domain] = cfg->icc_max; From 7a70a46ecc30decffbea0bb3ef8fee54b155c1cc Mon Sep 17 00:00:00 2001 From: Patrick Rudolph Date: Wed, 4 Dec 2019 13:52:11 +0100 Subject: [PATCH 0825/1242] mb/supermicro/x11-lga1151-series: Remove default devicetree values MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The same default values are used if the values are not present in devicetree. Change-Id: Ic910cdc8077e1b3e98eadc77a2d1fa0f9cb38e5b Signed-off-by: Patrick Rudolph Reviewed-on: https://review.coreboot.org/c/coreboot/+/37467 Tested-by: build bot (Jenkins) Reviewed-by: Christian Walter Reviewed-by: Michael Niewöhner --- .../x11-lga1151-series/devicetree.cb | 57 ------------------- 1 file changed, 57 deletions(-) diff --git a/src/mainboard/supermicro/x11-lga1151-series/devicetree.cb b/src/mainboard/supermicro/x11-lga1151-series/devicetree.cb index b58fbf1470..ee7c932dd8 100644 --- a/src/mainboard/supermicro/x11-lga1151-series/devicetree.cb +++ b/src/mainboard/supermicro/x11-lga1151-series/devicetree.cb @@ -95,63 +95,6 @@ chip soc/intel/skylake register "PmConfigSlpSusMinAssert" = "SLP_SUS_MIN_ASSERT_4S" register "PmConfigSlpAMinAssert" = "SLP_A_MIN_ASSERT_2S" - # VR Settings Configuration for 4 Domains - # ICC_MAX = 0 (Auto) - # Voltage limit 1.52V (not used on KBL-S and KBL-DT) - # Disable PS4 powerstate in S0ix, thus no package C10 support - # psi threshold is using FSP default values - register "domain_vr_config[VR_SYSTEM_AGENT]" = "{ - .vr_config_enable = 1, \ - .psi1threshold = VR_CFG_AMP(20), - .psi2threshold = VR_CFG_AMP(5), - .psi3threshold = VR_CFG_AMP(1), - .psi3enable = 1, \ - .psi4enable = 0, \ - .imon_slope = 0x0, \ - .imon_offset = 0x0, \ - .icc_max = 0, \ - .voltage_limit = 1520 \ - }" - - register "domain_vr_config[VR_IA_CORE]" = "{ - .vr_config_enable = 1, \ - .psi1threshold = VR_CFG_AMP(20), - .psi2threshold = VR_CFG_AMP(5), - .psi3threshold = VR_CFG_AMP(1), - .psi3enable = 1, \ - .psi4enable = 0, \ - .imon_slope = 0x0, \ - .imon_offset = 0x0, \ - .icc_max = 0, \ - .voltage_limit = 1520 \ - }" - - register "domain_vr_config[VR_GT_UNSLICED]" = "{ - .vr_config_enable = 1, \ - .psi1threshold = VR_CFG_AMP(20), - .psi2threshold = VR_CFG_AMP(5), - .psi3threshold = VR_CFG_AMP(1), - .psi3enable = 1, \ - .psi4enable = 0, \ - .imon_slope = 0x0, \ - .imon_offset = 0x0, \ - .icc_max = 0 ,\ - .voltage_limit = 1520 \ - }" - - register "domain_vr_config[VR_GT_SLICED]" = "{ - .vr_config_enable = 1, \ - .psi1threshold = VR_CFG_AMP(20), - .psi2threshold = VR_CFG_AMP(5), - .psi3threshold = VR_CFG_AMP(1), - .psi3enable = 1, \ - .psi4enable = 0, \ - .imon_slope = 0x0, \ - .imon_offset = 0x0, \ - .icc_max = 0, \ - .voltage_limit = 1520 \ - }" - # No extra VR mailbox command register "SendVrMbxCmd" = "0" From 2bdc05d89b25f17a041f0c95362b9013fbc91bae Mon Sep 17 00:00:00 2001 From: Mike Banon Date: Thu, 19 Dec 2019 11:16:07 +0300 Subject: [PATCH 0826/1242] asus/am1i-a: Switch away from ROMCC_BOOTBLOCK MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Switching was done by moving a SIO configuration and the clocks setup from 'romstage.c' to 'bootblock.c', following the example of change CB:37719 (fc749b2). TEST=Boots into Artix Linux 2019 without a problem. Signed-off-by: Mike Banon Change-Id: I780fa87cb9cb3c45844c388331ef89eb8eb70ebb Reviewed-on: https://review.coreboot.org/c/coreboot/+/37829 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki --- src/mainboard/asus/am1i-a/Kconfig | 4 -- src/mainboard/asus/am1i-a/Kconfig.name | 4 +- src/mainboard/asus/am1i-a/Makefile.inc | 2 + .../asus/am1i-a/{romstage.c => bootblock.c} | 46 +++---------------- 4 files changed, 11 insertions(+), 45 deletions(-) rename src/mainboard/asus/am1i-a/{romstage.c => bootblock.c} (78%) diff --git a/src/mainboard/asus/am1i-a/Kconfig b/src/mainboard/asus/am1i-a/Kconfig index 8ccb1742af..947c2c5bc9 100644 --- a/src/mainboard/asus/am1i-a/Kconfig +++ b/src/mainboard/asus/am1i-a/Kconfig @@ -1,12 +1,8 @@ -config BOARD_ASUS_AM1I_A - def_bool n - if BOARD_ASUS_AM1I_A config BOARD_SPECIFIC_OPTIONS def_bool y select BOARD_ROMSIZE_KB_8192 - #select ROMCC_BOOTBLOCK select CPU_AMD_AGESA_FAMILY16_KB select FORCE_AM1_SOCKET_SUPPORT select GFXUMA diff --git a/src/mainboard/asus/am1i-a/Kconfig.name b/src/mainboard/asus/am1i-a/Kconfig.name index 57c62278ca..840e821f65 100644 --- a/src/mainboard/asus/am1i-a/Kconfig.name +++ b/src/mainboard/asus/am1i-a/Kconfig.name @@ -1,2 +1,2 @@ -#config BOARD_ASUS_AM1I_A -# bool"AM1I-A" +config BOARD_ASUS_AM1I_A + bool "AM1I-A" diff --git a/src/mainboard/asus/am1i-a/Makefile.inc b/src/mainboard/asus/am1i-a/Makefile.inc index f8895faa92..4dde2cfd1e 100644 --- a/src/mainboard/asus/am1i-a/Makefile.inc +++ b/src/mainboard/asus/am1i-a/Makefile.inc @@ -13,6 +13,8 @@ # GNU General Public License for more details. # +bootblock-y += bootblock.c + romstage-y += buildOpts.c romstage-y += BiosCallOuts.c romstage-y += OemCustomize.c diff --git a/src/mainboard/asus/am1i-a/romstage.c b/src/mainboard/asus/am1i-a/bootblock.c similarity index 78% rename from src/mainboard/asus/am1i-a/romstage.c rename to src/mainboard/asus/am1i-a/bootblock.c index de8532504d..d4017cf282 100644 --- a/src/mainboard/asus/am1i-a/romstage.c +++ b/src/mainboard/asus/am1i-a/bootblock.c @@ -1,10 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * Copyright (C) 2015 Sergej Ivanov - * Copyright (C) 2018 Gergely Kiss - * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; version 2 of the License. @@ -15,12 +11,9 @@ * GNU General Public License for more details. */ -#include +#include +#include #include -#include -#include -#include -#include #include #include @@ -118,33 +111,12 @@ static void ite_gpio_conf(pnp_devfn_t dev) ite_reg_write(dev, 0xfb, 0x00); } -void board_BeforeAgesa(struct sysinfo *cb) +void bootblock_mainboard_early_init(void) { - int i; - u32 val; - u8 byte; - pci_devfn_t dev; - u32 *addr32; - - /* In Hudson RRG, PMIOxD2[5:4] is "Drive strength control for - * LpcClk[1:0]". To be consistent with Parmer, setting to 4mA - * even though the register is not documented in the Kabini BKDG. - * Otherwise the serial output is bad code. - */ - outb(0xD2, 0xcd6); - outb(0x00, 0xcd7); + volatile u32 i, val, *addr32; /* Disable PCI-PCI bridge and release GPIO32/33 for other uses. */ - outb(0xEA, 0xcd6); - outb(0x1, 0xcd7); - - /* Set LPC decode enables. */ - pci_devfn_t dev2 = PCI_DEV(0, 0x14, 3); - pci_write_config32(dev2, 0x44, 0xff03ffd5); - - /* Enable the AcpiMmio space */ - outb(0x24, 0xcd6); - outb(0x1, 0xcd7); + pm_write8(0xea, 0x1); /* Configure ClkDrvStr1 settings */ addr32 = (u32 *)0xfed80e24; @@ -154,15 +126,11 @@ void board_BeforeAgesa(struct sysinfo *cb) addr32 = (u32 *)0xfed80e40; *addr32 = 0x000c4050; - /* enable SIO LPC decode */ - dev = PCI_DEV(0, 0x14, 3); - byte = pci_read_config8(dev, 0x48); - byte |= 3; /* 2e, 2f & 4e, 4f */ - pci_write_config8(dev, 0x48, byte); - + /* Configure SIO as made under vendor BIOS */ ite_gpio_conf(GPIO_DEV); ite_evc_conf(ENVC_DEV); + /* Enable serial output on it8623e */ ite_conf_clkin(CLKIN_DEV, ITE_UART_CLK_PREDIVIDE_48); ite_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); ite_kill_watchdog(GPIO_DEV); From e6b313da365e801decd18db4b5a5c97cbdd31e47 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ky=C3=B6sti=20M=C3=A4lkki?= Date: Sat, 21 Dec 2019 07:01:31 +0200 Subject: [PATCH 0827/1242] cpu/intel/car/p4-netburst: Add assert for SIPI_VECTOR_IN_ROM MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Location of _start16bit in entry16.inc is about to see some changes, lets make sure they don't break the alignment requirement here. Change-Id: Id8a0964982387e5321e8c89254922e1242cf85ee Signed-off-by: Kyösti Mälkki Reviewed-on: https://review.coreboot.org/c/coreboot/+/37894 Tested-by: build bot (Jenkins) Reviewed-by: HAOUAS Elyes --- src/cpu/x86/16bit/entry16.ld | 26 +++++++++++++++++++++++--- 1 file changed, 23 insertions(+), 3 deletions(-) diff --git a/src/cpu/x86/16bit/entry16.ld b/src/cpu/x86/16bit/entry16.ld index 66bfbd58ca..b5c1592691 100644 --- a/src/cpu/x86/16bit/entry16.ld +++ b/src/cpu/x86/16bit/entry16.ld @@ -1,3 +1,23 @@ - gdtptr16_offset = gdtptr16 & 0xffff; - nullidt_offset = nullidt & 0xffff; - ap_sipi_vector_in_rom = (_start16bit >> 12) & 0xff; +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +gdtptr16_offset = gdtptr16 & 0xffff; +nullidt_offset = nullidt & 0xffff; + +/* Symbol _start16bit must be aligned to 4kB to start AP CPUs with + * Startup IPI message without RAM. + */ +#if CONFIG(SIPI_VECTOR_IN_ROM) +_bogus = ASSERT((_start16bit & 0xfff) == 0, "Symbol _start16bit is not at 4 KiB boundary"); +ap_sipi_vector_in_rom = (_start16bit >> 12) & 0xff; +#endif From b73111cfa74a76842c9403e534e8b8163a8a77e1 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ky=C3=B6sti=20M=C3=A4lkki?= Date: Sun, 22 Dec 2019 10:59:10 +0200 Subject: [PATCH 0828/1242] soc/amd/common/car: Remove unneeded header MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Change-Id: I9c65d3c54efcdec1ebb2648d078acdd9e7c11c49 Signed-off-by: Kyösti Mälkki Reviewed-on: https://review.coreboot.org/c/coreboot/+/37896 Tested-by: build bot (Jenkins) Reviewed-by: HAOUAS Elyes --- src/soc/amd/common/block/cpu/car/cache_as_ram.S | 1 - 1 file changed, 1 deletion(-) diff --git a/src/soc/amd/common/block/cpu/car/cache_as_ram.S b/src/soc/amd/common/block/cpu/car/cache_as_ram.S index 402da3acb6..78c672a887 100644 --- a/src/soc/amd/common/block/cpu/car/cache_as_ram.S +++ b/src/soc/amd/common/block/cpu/car/cache_as_ram.S @@ -22,7 +22,6 @@ */ #include "gcccar.inc" -#include #include /* From e69798b5ae43d0a71fcbe6e2b38b0dc8edf404bf Mon Sep 17 00:00:00 2001 From: Patrick Rudolph Date: Tue, 12 Nov 2019 16:56:43 +0100 Subject: [PATCH 0829/1242] util/pgtblgen: Fix qemu on KVM Running the x86_64 qemu mainboard target with '-accel kvm' results in hang, as the 'D' and 'A' bits needs to be set in read only page tables. Tested on QEMU Q35: Boots into payload with '-accel kvm'. Change-Id: I4beae8deec6bf34f9762e7b54c5da4e5b63f6d24 Signed-off-by: Patrick Rudolph Reviewed-on: https://review.coreboot.org/c/coreboot/+/36778 Reviewed-by: Arthur Heymans Tested-by: build bot (Jenkins) --- util/pgtblgen/pgtblgen.c | 14 ++++++++------ 1 file changed, 8 insertions(+), 6 deletions(-) diff --git a/util/pgtblgen/pgtblgen.c b/util/pgtblgen/pgtblgen.c index e9ebd8b0cf..3a41a90793 100644 --- a/util/pgtblgen/pgtblgen.c +++ b/util/pgtblgen/pgtblgen.c @@ -38,12 +38,14 @@ static void usage(char *argv[]) * * Page table attributes: WB, User+Supervisor, Present, Writeable */ -#define PRES (1ULL << 0) -#define RW (1ULL << 1) -#define US (1ULL << 2) -#define PS (1ULL << 7) -#define _GEN_DIR(a) (PRES | RW | US | (a)) -#define _GEN_PAGE(a) (PRES | RW | US | PS | (a)) +#define _PRES (1ULL << 0) +#define _RW (1ULL << 1) +#define _US (1ULL << 2) +#define _A (1ULL << 5) +#define _D (1ULL << 6) +#define _PS (1ULL << 7) +#define _GEN_DIR(a) (_PRES | _RW | _US | _A | (a)) +#define _GEN_PAGE(a) (_PRES | _RW | _US | _PS | _A | _D | (a)) /* * Generate x86_64 page tables. From 5dd4bf3644e13ad65edf2244ea672850a40e95e4 Mon Sep 17 00:00:00 2001 From: Bill XIE Date: Mon, 23 Dec 2019 13:53:56 +0800 Subject: [PATCH 0830/1242] mb/gigabyte/ga-b75m-d3h: enable superspeed ports for all variants Unlike other Panther Point boards, the ga-b75m-d3h lacks definitions to wire SuperSpeed-capable ports to XHCI in its devicetree, causing these ports being wired to the second EHCI, and only working as USB 2.0 ports. The missing register definitions are added to fix that. Tested on my ga-b75-d3v board. Change-Id: Ida4de26f1a493ead83065b1ab27c0c684a074513 Signed-off-by: Bill XIE Reviewed-on: https://review.coreboot.org/c/coreboot/+/37912 Tested-by: build bot (Jenkins) Reviewed-by: Angel Pons --- src/mainboard/gigabyte/ga-b75m-d3h/devicetree.cb | 3 +++ 1 file changed, 3 insertions(+) diff --git a/src/mainboard/gigabyte/ga-b75m-d3h/devicetree.cb b/src/mainboard/gigabyte/ga-b75m-d3h/devicetree.cb index 57b4960a12..7b470677b0 100644 --- a/src/mainboard/gigabyte/ga-b75m-d3h/devicetree.cb +++ b/src/mainboard/gigabyte/ga-b75m-d3h/devicetree.cb @@ -38,6 +38,9 @@ chip northbridge/intel/sandybridge register "sata_port_map" = "0x3f" register "sata_interface_speed_support" = "0x3" + register "xhci_switchable_ports" = "0xf" + register "superspeed_capable_ports" = "0xf" + register "pcie_port_coalesce" = "0" register "docking_supported" = "0" register "c2_latency" = "0x0065" From 1f7a11699a40b03162816ab2acd766c21aa24e8d Mon Sep 17 00:00:00 2001 From: Kevin Chiu Date: Tue, 24 Dec 2019 13:12:59 +0800 Subject: [PATCH 0831/1242] mb/google/octopus/variants/garg: update new SKU add new SKU ID below: 19 - Garg PVT (HDMI DB, Touch) 20 - Garg PVT (2A2C DB, Touch) 38 - Garg360 EVT (2A2C DB, touch, no stylues, rear camera) BUG=b:146260545 BRANCH=octopus TEST=emerge-octopus coreboot chromeos-bootimage Change-Id: Ic74ce14db7060f3124c1a277eb3625ce0ff0b9f0 Signed-off-by: Kevin Chiu Reviewed-on: https://review.coreboot.org/c/coreboot/+/37923 Tested-by: build bot (Jenkins) Reviewed-by: Marco Chen --- .../google/octopus/variants/garg/gpio.c | 10 ++----- .../variants/garg/include/variant/sku.h | 30 +++++++++++++++++++ .../google/octopus/variants/garg/variant.c | 10 ++----- 3 files changed, 34 insertions(+), 16 deletions(-) create mode 100644 src/mainboard/google/octopus/variants/garg/include/variant/sku.h diff --git a/src/mainboard/google/octopus/variants/garg/gpio.c b/src/mainboard/google/octopus/variants/garg/gpio.c index bcabac5001..eeeb4662e3 100644 --- a/src/mainboard/google/octopus/variants/garg/gpio.c +++ b/src/mainboard/google/octopus/variants/garg/gpio.c @@ -18,14 +18,7 @@ #include #include #include - -enum { - SKU_1_2A2C = 1, - SKU_9_HDMI = 9, - SKU_17_LTE = 17, - SKU_18_LTE_TS = 18, - SKU_37_2A2C_360 = 37, -}; +#include static const struct pad_config default_override_table[] = { PAD_NC(GPIO_104, UP_20K), @@ -83,6 +76,7 @@ const struct pad_config *variant_override_gpio_table(size_t *num) switch (sku_id) { case SKU_9_HDMI: + case SKU_19_HDMI_TS: *num = ARRAY_SIZE(hdmi_override_table); return hdmi_override_table; case SKU_17_LTE: diff --git a/src/mainboard/google/octopus/variants/garg/include/variant/sku.h b/src/mainboard/google/octopus/variants/garg/include/variant/sku.h new file mode 100644 index 0000000000..432f3c54cd --- /dev/null +++ b/src/mainboard/google/octopus/variants/garg/include/variant/sku.h @@ -0,0 +1,30 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2019 Google LLC + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __MAINBOARD_SKU_H__ +#define __MAINBOARD_SKU_H__ + +enum { + SKU_1_2A2C = 1, + SKU_9_HDMI = 9, + SKU_17_LTE = 17, + SKU_18_LTE_TS = 18, + SKU_19_HDMI_TS = 19, + SKU_20_2A2C_TS = 20, + SKU_37_2A2C_360 = 37, + SKU_38_2A2C_360_TS_NO_STYLUES = 38, +}; + +#endif /* __MAINBOARD_SKU_H__ */ diff --git a/src/mainboard/google/octopus/variants/garg/variant.c b/src/mainboard/google/octopus/variants/garg/variant.c index 942ea5f3b4..f5f350a8f0 100644 --- a/src/mainboard/google/octopus/variants/garg/variant.c +++ b/src/mainboard/google/octopus/variants/garg/variant.c @@ -20,14 +20,7 @@ #include #include #include - -enum { - SKU_1_2A2C = 1, - SKU_9_HDMI = 9, - SKU_17_LTE = 17, - SKU_18_LTE_TS = 18, - SKU_37_2A2C_360 = 37, -}; +#include struct gpio_with_delay { gpio_t gpio; @@ -65,6 +58,7 @@ const char *mainboard_vbt_filename(void) switch (sku_id) { case SKU_9_HDMI: + case SKU_19_HDMI_TS: return "vbt_garg_hdmi.bin"; default: return "vbt.bin"; From f814ff15f977bbb409d944dfad687573ac3672b2 Mon Sep 17 00:00:00 2001 From: Wisley Chen Date: Thu, 19 Dec 2019 17:16:42 +0800 Subject: [PATCH 0832/1242] mb/google/hatch/var/jinlon: Update DPTF parameters The change applies the DPTF parameters received from the thermal team. BUG=b:146540028 TEST=build and verified by thermal team. Change-Id: I222bac5f04ba5cdde1788c6d4ca8af80d323ca98 Signed-off-by: Wisley Chen Reviewed-on: https://review.coreboot.org/c/coreboot/+/37832 Tested-by: build bot (Jenkins) Reviewed-by: Paul Fagerburg Reviewed-by: Tim Wawrzynczak --- .../jinlon/include/variant/acpi/dptf.asl | 94 ++++++++++++++++++- .../hatch/variants/jinlon/overridetree.cb | 2 + 2 files changed, 95 insertions(+), 1 deletion(-) diff --git a/src/mainboard/google/hatch/variants/jinlon/include/variant/acpi/dptf.asl b/src/mainboard/google/hatch/variants/jinlon/include/variant/acpi/dptf.asl index f1f09438fa..74195e131a 100644 --- a/src/mainboard/google/hatch/variants/jinlon/include/variant/acpi/dptf.asl +++ b/src/mainboard/google/hatch/variants/jinlon/include/variant/acpi/dptf.asl @@ -13,4 +13,96 @@ * GNU General Public License for more details. */ -#include +#define DPTF_CPU_PASSIVE 70 +#define DPTF_CPU_CRITICAL 105 +#define DPTF_CPU_ACTIVE_AC0 70 +#define DPTF_CPU_ACTIVE_AC1 65 +#define DPTF_CPU_ACTIVE_AC2 60 +#define DPTF_CPU_ACTIVE_AC3 50 +#define DPTF_CPU_ACTIVE_AC4 40 + +#define DPTF_TSR0_SENSOR_ID 0 +#define DPTF_TSR0_SENSOR_NAME "Thermal Sensor 1" +#define DPTF_TSR0_PASSIVE 62 +#define DPTF_TSR0_CRITICAL 105 + +#define DPTF_TSR1_SENSOR_ID 1 +#define DPTF_TSR1_SENSOR_NAME "Thermal Sensor 2" +#define DPTF_TSR1_PASSIVE 54 +#define DPTF_TSR1_CRITICAL 105 + +#define DPTF_ENABLE_CHARGER +#define DPTF_ENABLE_FAN_CONTROL + +/* Charger performance states, board-specific values from charger and EC */ +Name (CHPS, Package () { + Package () { 0, 0, 0, 0, 255, 0x6a4, "mA", 0 }, /* 1.7A (MAX) */ + Package () { 0, 0, 0, 0, 24, 0x600, "mA", 0 }, /* 1.5A */ + Package () { 0, 0, 0, 0, 16, 0x400, "mA", 0 }, /* 1.0A */ + Package () { 0, 0, 0, 0, 8, 0x200, "mA", 0 }, /* 0.5A */ +}) + +/* DFPS: Fan Performance States */ +Name (DFPS, Package () { + 0, // Revision + /* + * TODO : Need to update this Table after characterization. + * These are initial reference values. + */ + /* Control, Trip Point, Speed, NoiseLevel, Power */ + Package () {90, 0xFFFFFFFF, 6700, 220, 2200}, + Package () {80, 0xFFFFFFFF, 5800, 180, 1800}, + Package () {70, 0xFFFFFFFF, 5000, 145, 1450}, + Package () {67, 0xFFFFFFFF, 4900, 115, 1150}, + Package () {60, 0xFFFFFFFF, 3838, 90, 900}, + Package () {50, 0xFFFFFFFF, 2904, 55, 550}, + Package () {40, 0xFFFFFFFF, 2337, 30, 300}, + Package () {20, 0xFFFFFFFF, 1608, 15, 150}, + Package () {10, 0xFFFFFFFF, 800, 10, 100}, + Package () {0, 0xFFFFFFFF, 0, 0, 50} +}) + +Name (DART, Package () { + /* Fan effect on CPU */ + 0, // Revision + Package () { + /* + * Source, Target, Weight, AC0, AC1, AC2, AC3, AC4, AC5, AC6, + * AC7, AC8, AC9 + */ + \_SB.DPTF.TFN1, \_SB.PCI0.TCPU, 100, 70, 67, 60, 50, 40, 0, 0, + 0, 0, 0 + }, +}) + +Name (DTRT, Package () { + /* CPU Throttle Effect on CPU */ + Package () { \_SB.PCI0.TCPU, \_SB.PCI0.TCPU, 100, 50, 0, 0, 0, 0 }, + + /* CPU Throttle Effect on Ambient (TSR0) */ + Package () { \_SB.PCI0.TCPU, \_SB.DPTF.TSR0, 100, 60, 0, 0, 0, 0 }, + + /* Charger Throttle Effect on Charger (TSR1) */ + Package () { \_SB.DPTF.TCHG, \_SB.DPTF.TSR1, 100, 60, 0, 0, 0, 0 }, +}) + +Name (MPPC, Package () +{ + 0x2, /* Revision */ + Package () { /* Power Limit 1 */ + 0, /* PowerLimitIndex, 0 for Power Limit 1 */ + 12000, /* PowerLimitMinimum */ + 15000, /* PowerLimitMaximum */ + 28000, /* TimeWindowMinimum */ + 32000, /* TimeWindowMaximum */ + 200 /* StepSize */ + }, + Package () { /* Power Limit 2 */ + 1, /* PowerLimitIndex, 1 for Power Limit 2 */ + 51000, /* PowerLimitMinimum */ + 51000, /* PowerLimitMaximum */ + 28000, /* TimeWindowMinimum */ + 32000, /* TimeWindowMaximum */ + 1000 /* StepSize */ + } +}) diff --git a/src/mainboard/google/hatch/variants/jinlon/overridetree.cb b/src/mainboard/google/hatch/variants/jinlon/overridetree.cb index fd2861e5f6..c9613d2677 100644 --- a/src/mainboard/google/hatch/variants/jinlon/overridetree.cb +++ b/src/mainboard/google/hatch/variants/jinlon/overridetree.cb @@ -1,4 +1,6 @@ chip soc/intel/cannonlake + register "tdp_pl1_override" = "15" + register "tdp_pl2_override" = "51" register "SerialIoDevMode" = "{ [PchSerialIoIndexI2C0] = PchSerialIoPci, From f96c638a60fdca149a716e773749c20bd4080ee3 Mon Sep 17 00:00:00 2001 From: Subrata Banik Date: Thu, 19 Dec 2019 14:45:52 +0530 Subject: [PATCH 0833/1242] vendorcode/intel/fsp/fsp2_0/tgl: Add FSP header files for Tiger Lake Add header files for FSP for Tiger Lake platform version 2457. Change-Id: I52bb2e164cc89d3535fe67493686d1e8e064e31e Signed-off-by: Subrata Banik Reviewed-on: https://review.coreboot.org/c/coreboot/+/37830 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh Reviewed-by: Wonkyu Kim --- .../fsp2_0/tigerlake/FirmwareVersionInfoHob.h | 68 ++ .../intel/fsp/fsp2_0/tigerlake/FspUpd.h | 48 ++ .../intel/fsp/fsp2_0/tigerlake/FspmUpd.h | 770 ++++++++++++++++++ .../intel/fsp/fsp2_0/tigerlake/FspsUpd.h | 683 ++++++++++++++++ .../intel/fsp/fsp2_0/tigerlake/MemInfoHob.h | 290 +++++++ 5 files changed, 1859 insertions(+) create mode 100644 src/vendorcode/intel/fsp/fsp2_0/tigerlake/FirmwareVersionInfoHob.h create mode 100644 src/vendorcode/intel/fsp/fsp2_0/tigerlake/FspUpd.h create mode 100644 src/vendorcode/intel/fsp/fsp2_0/tigerlake/FspmUpd.h create mode 100644 src/vendorcode/intel/fsp/fsp2_0/tigerlake/FspsUpd.h create mode 100644 src/vendorcode/intel/fsp/fsp2_0/tigerlake/MemInfoHob.h diff --git a/src/vendorcode/intel/fsp/fsp2_0/tigerlake/FirmwareVersionInfoHob.h b/src/vendorcode/intel/fsp/fsp2_0/tigerlake/FirmwareVersionInfoHob.h new file mode 100644 index 0000000000..98a16d7752 --- /dev/null +++ b/src/vendorcode/intel/fsp/fsp2_0/tigerlake/FirmwareVersionInfoHob.h @@ -0,0 +1,68 @@ +/** @file + Header file for Firmware Version Information + + @copyright + Copyright (c) 2015 - 2018, Intel Corporation. All rights reserved.
+ + This program and the accompanying materials are licensed and made available under + the terms and conditions of the BSD License which accompanies this distribution. + The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#ifndef _FIRMWARE_VERSION_INFO_HOB_H_ +#define _FIRMWARE_VERSION_INFO_HOB_H_ + +#include +#include +#include + +#pragma pack(1) +/// +/// Firmware Version Structure +/// +typedef struct { + UINT8 MajorVersion; + UINT8 MinorVersion; + UINT8 Revision; + UINT16 BuildNumber; +} FIRMWARE_VERSION; + +/// +/// Firmware Version Information Structure +/// +typedef struct { + UINT8 ComponentNameIndex; ///< Offset 0 Index of Component Name + UINT8 VersionStringIndex; ///< Offset 1 Index of Version String + FIRMWARE_VERSION Version; ///< Offset 2-6 Firmware version +} FIRMWARE_VERSION_INFO; + +#ifndef __SMBIOS_STANDARD_H__ +/// +/// The Smbios structure header. +/// +typedef struct { + UINT8 Type; + UINT8 Length; + UINT16 Handle; +} SMBIOS_STRUCTURE; +#endif + +/// +/// Firmware Version Information HOB Structure +/// +typedef struct { + EFI_HOB_GUID_TYPE Header; ///< Offset 0-23 The header of FVI HOB + SMBIOS_STRUCTURE SmbiosData; ///< Offset 24-27 The SMBIOS header of FVI HOB + UINT8 Count; ///< Offset 28 Number of FVI elements included. +/// +/// FIRMWARE_VERSION_INFO structures followed by the null terminated string buffer +/// +} FIRMWARE_VERSION_INFO_HOB; +#pragma pack() + +#endif // _FIRMWARE_VERSION_INFO_HOB_H_ diff --git a/src/vendorcode/intel/fsp/fsp2_0/tigerlake/FspUpd.h b/src/vendorcode/intel/fsp/fsp2_0/tigerlake/FspUpd.h new file mode 100644 index 0000000000..0c910f3d93 --- /dev/null +++ b/src/vendorcode/intel/fsp/fsp2_0/tigerlake/FspUpd.h @@ -0,0 +1,48 @@ +/** @file + +Copyright (c) 2019, Intel Corporation. All rights reserved.
+ +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + +* Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. +* Redistributions in binary form must reproduce the above copyright notice, this + list of conditions and the following disclaimer in the documentation and/or + other materials provided with the distribution. +* Neither the name of Intel Corporation nor the names of its contributors may + be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF + THE POSSIBILITY OF SUCH DAMAGE. + + This file is automatically generated. Please do NOT modify !!! + +**/ + +#ifndef __FSPUPD_H__ +#define __FSPUPD_H__ + +#include + +#pragma pack(1) + +#define FSPT_UPD_SIGNATURE 0x545F4450554C4754 /* 'TGLUPD_T' */ + +#define FSPM_UPD_SIGNATURE 0x4D5F4450554C4754 /* 'TGLUPD_M' */ + +#define FSPS_UPD_SIGNATURE 0x535F4450554C4754 /* 'TGLUPD_S' */ + +#pragma pack() + +#endif diff --git a/src/vendorcode/intel/fsp/fsp2_0/tigerlake/FspmUpd.h b/src/vendorcode/intel/fsp/fsp2_0/tigerlake/FspmUpd.h new file mode 100644 index 0000000000..f37e56cbf3 --- /dev/null +++ b/src/vendorcode/intel/fsp/fsp2_0/tigerlake/FspmUpd.h @@ -0,0 +1,770 @@ +/** @file + +Copyright (c) 2019, Intel Corporation. All rights reserved.
+ +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + +* Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. +* Redistributions in binary form must reproduce the above copyright notice, this + list of conditions and the following disclaimer in the documentation and/or + other materials provided with the distribution. +* Neither the name of Intel Corporation nor the names of its contributors may + be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF + THE POSSIBILITY OF SUCH DAMAGE. + + This file is automatically generated. Please do NOT modify !!! + +**/ + +#ifndef __FSPMUPD_H__ +#define __FSPMUPD_H__ + +#include + +#pragma pack(1) + + +#include + +/// +/// The ChipsetInit Info structure provides the information of ME ChipsetInit CRC and BIOS ChipsetInit CRC. +/// +typedef struct { + UINT8 Revision; ///< Chipset Init Info Revision + UINT8 Rsvd[3]; ///< Reserved + UINT16 MeChipInitCrc; ///< 16 bit CRC value of MeChipInit Table + UINT16 BiosChipInitCrc; ///< 16 bit CRC value of PchChipInit Table +} CHIPSET_INIT_INFO; + + +/** Fsp M Configuration +**/ +typedef struct { + +/** Offset 0x0040 - Platform Reserved Memory Size + The minimum platform memory size required to pass control into DXE +**/ + UINT64 PlatformMemorySize; + +/** Offset 0x0048 - SPD Data Length + Length of SPD Data + 0x100:256 Bytes, 0x200:512 Bytes, 0x400:1024 Bytes +**/ + UINT16 MemorySpdDataLen; + +/** Offset 0x004A - Reserved +**/ + UINT8 Reserved0[2]; + +/** Offset 0x004C - MemorySpdPtr00 +**/ + UINT32 MemorySpdPtr00; + +/** Offset 0x0050 - MemorySpdPtr01 +**/ + UINT32 MemorySpdPtr01; + +/** Offset 0x0054 - MemorySpdPtr02 +**/ + UINT32 MemorySpdPtr02; + +/** Offset 0x0058 - MemorySpdPtr03 +**/ + UINT32 MemorySpdPtr03; + +/** Offset 0x005C - MemorySpdPtr04 +**/ + UINT32 MemorySpdPtr04; + +/** Offset 0x0060 - MemorySpdPtr05 +**/ + UINT32 MemorySpdPtr05; + +/** Offset 0x0064 - MemorySpdPtr06 +**/ + UINT32 MemorySpdPtr06; + +/** Offset 0x0068 - MemorySpdPtr07 +**/ + UINT32 MemorySpdPtr07; + +/** Offset 0x006C - MemorySpdPtr08 +**/ + UINT32 MemorySpdPtr08; + +/** Offset 0x0070 - MemorySpdPtr09 +**/ + UINT32 MemorySpdPtr09; + +/** Offset 0x0074 - MemorySpdPtr10 +**/ + UINT32 MemorySpdPtr10; + +/** Offset 0x0078 - MemorySpdPtr11 +**/ + UINT32 MemorySpdPtr11; + +/** Offset 0x007C - MemorySpdPtr12 +**/ + UINT32 MemorySpdPtr12; + +/** Offset 0x0080 - MemorySpdPtr13 +**/ + UINT32 MemorySpdPtr13; + +/** Offset 0x0084 - MemorySpdPtr14 +**/ + UINT32 MemorySpdPtr14; + +/** Offset 0x0088 - MemorySpdPtr15 +**/ + UINT32 MemorySpdPtr15; + +/** Offset 0x008C - RcompResistor settings + Indicates RcompResistor settings: Board-dependent +**/ + UINT16 RcompResistor; + +/** Offset 0x008E - RcompTarget settings + RcompTarget settings: board-dependent +**/ + UINT16 RcompTarget[5]; + +/** Offset 0x0098 - DqsMapCpu2DramCh0 +**/ + UINT8 DqsMapCpu2DramCh0[2]; + +/** Offset 0x009A - DqsMapCpu2DramCh1 +**/ + UINT8 DqsMapCpu2DramCh1[2]; + +/** Offset 0x009C - DqsMapCpu2DramCh2 +**/ + UINT8 DqsMapCpu2DramCh2[2]; + +/** Offset 0x009E - DqsMapCpu2DramCh3 +**/ + UINT8 DqsMapCpu2DramCh3[2]; + +/** Offset 0x00A0 - DqsMapCpu2DramCh4 +**/ + UINT8 DqsMapCpu2DramCh4[2]; + +/** Offset 0x00A2 - DqsMapCpu2DramCh5 +**/ + UINT8 DqsMapCpu2DramCh5[2]; + +/** Offset 0x00A4 - DqsMapCpu2DramCh6 +**/ + UINT8 DqsMapCpu2DramCh6[2]; + +/** Offset 0x00A6 - DqsMapCpu2DramCh7 +**/ + UINT8 DqsMapCpu2DramCh7[2]; + +/** Offset 0x00A8 - DqMapCpu2DramCh0 +**/ + UINT8 DqMapCpu2DramCh0[16]; + +/** Offset 0x00B8 - DqMapCpu2DramCh1 +**/ + UINT8 DqMapCpu2DramCh1[16]; + +/** Offset 0x00C8 - DqMapCpu2DramCh2 +**/ + UINT8 DqMapCpu2DramCh2[16]; + +/** Offset 0x00D8 - DqMapCpu2DramCh3 +**/ + UINT8 DqMapCpu2DramCh3[16]; + +/** Offset 0x00E8 - DqMapCpu2DramCh4 +**/ + UINT8 DqMapCpu2DramCh4[16]; + +/** Offset 0x00F8 - DqMapCpu2DramCh5 +**/ + UINT8 DqMapCpu2DramCh5[16]; + +/** Offset 0x0108 - DqMapCpu2DramCh6 +**/ + UINT8 DqMapCpu2DramCh6[16]; + +/** Offset 0x0118 - DqMapCpu2DramCh7 +**/ + UINT8 DqMapCpu2DramCh7[16]; + +/** Offset 0x0128 - Dqs Pins Interleaved Setting + Indicates DqPinsInterleaved setting: board-dependent + $EN_DIS +**/ + UINT8 DqPinsInterleaved; + +/** Offset 0x0129 - Reserved +**/ + UINT8 Reserved1[7]; + +/** Offset 0x0130 - Intel Enhanced Debug + Intel Enhanced Debug (IED): 0=Disabled, 0x400000=Enabled and 4MB SMRAM occupied + 0 : Disable, 0x400000 : Enable +**/ + UINT32 IedSize; + +/** Offset 0x0134 - Tseg Size + Size of SMRAM memory reserved. 0x400000 for Release build and 0x1000000 for Debug build + 0x0400000:4MB, 0x01000000:16MB +**/ + UINT32 TsegSize; + +/** Offset 0x0138 - Reserved +**/ + UINT8 Reserved2[3]; + +/** Offset 0x013B - Enable SMBus + Enable/disable SMBus controller. + $EN_DIS +**/ + UINT8 SmbusEnable; + +/** Offset 0x013C - Spd Address Tabl + Specify SPD Address table for CH0D0/CH0D1/CH1D0&CH1D1. MemorySpdPtr will be used + if SPD Address is 00 +**/ + UINT8 SpdAddressTable[16]; + +/** Offset 0x014C - Platform Debug Consent + To 'opt-in' for debug, please select 'Enabled' with the desired debug probe type. + Enabling this BIOS option may alter the default value of other debug-related BIOS + options.\Manual: Do not use Platform Debug Consent to override other debug-relevant + policies, but the user must set each debug option manually, aimed at advanced users.\n + Note: DCI OOB (aka BSSB) uses CCA probe;[DCI OOB+DbC] and [USB2 DbC] have the same setting. + 0:Disabled, 1:Enabled (DCI OOB+[DbC]), 2:Enabled (DCI OOB), 3:Enabled (USB3 DbC), + 4:Enabled (XDP/MIPI60), 5:Enabled (USB2 DbC), 6:Enable (2-wire DCI OOB), 7:Manual +**/ + UINT8 PlatformDebugConsent; + +/** Offset 0x014D - Reserved +**/ + UINT8 Reserved3[14]; + +/** Offset 0x015B - State of X2APIC_OPT_OUT bit in the DMAR table + 0=Disable/Clear, 1=Enable/Set + $EN_DIS +**/ + UINT8 X2ApicOptOut; + +/** Offset 0x015C - Reserved +**/ + UINT8 Reserved4[40]; + +/** Offset 0x0184 - Disable VT-d + 0=Enable/FALSE(VT-d enabled), 1=Disable/TRUE (VT-d disabled) + $EN_DIS +**/ + UINT8 VtdDisable; + +/** Offset 0x0185 - Reserved +**/ + UINT8 Reserved5[4]; + +/** Offset 0x0189 - Internal Graphics Pre-allocated Memory + Size of memory preallocated for internal graphics. + 0x00:0MB, 0x01:32MB, 0x02:64MB, 0x03:96MB, 0x04:128MB, 0x05:160MB, 0xF0:4MB, 0xF1:8MB, + 0xF2:12MB, 0xF3:16MB, 0xF4:20MB, 0xF5:24MB, 0xF6:28MB, 0xF7:32MB, 0xF8:36MB, 0xF9:40MB, + 0xFA:44MB, 0xFB:48MB, 0xFC:52MB, 0xFD:56MB, 0xFE:60MB +**/ + UINT8 IgdDvmt50PreAlloc; + +/** Offset 0x018A - Internal Graphics + Enable/disable internal graphics. + $EN_DIS +**/ + UINT8 InternalGfx; + +/** Offset 0x018B - Reserved +**/ + UINT8 Reserved6; + +/** Offset 0x018C - Board Type + MrcBoardType, Options are 0=Mobile/Mobile Halo, 1=Desktop/DT Halo, 5=ULT/ULX/Mobile + Halo, 7=UP Server + 0:Mobile/Mobile Halo, 1:Desktop/DT Halo, 5:ULT/ULX/Mobile Halo, 7:UP Server +**/ + UINT8 UserBd; + +/** Offset 0x018D - Reserved +**/ + UINT8 Reserved7[3]; + +/** Offset 0x0190 - SA GV + System Agent dynamic frequency support and when enabled memory will be training + at three different frequencies. + 0:Disabled, 1:FixedPoint0, 2:FixedPoint1, 3:FixedPoint2, 4:FixedPoint3, 5:Enabled +**/ + UINT8 SaGv; + +/** Offset 0x0191 - Reserved +**/ + UINT8 Reserved8[2]; + +/** Offset 0x0193 - Rank Margin Tool + Enable/disable Rank Margin Tool. + $EN_DIS +**/ + UINT8 RMT; + +/** Offset 0x0194 - Reserved +**/ + UINT8 Reserved9[10]; + +/** Offset 0x019E - Memory Reference Clock + 100MHz, 133MHz. + 0:133MHz, 1:100MHz +**/ + UINT8 RefClk; + +/** Offset 0x019F - Reserved +**/ + UINT8 Reserved10[22]; + +/** Offset 0x01B5 - Enable Intel HD Audio (Azalia) + 0: Disable, 1: Enable (Default) Azalia controller + $EN_DIS +**/ + UINT8 PchHdaEnable; + +/** Offset 0x01B6 - Enable PCH ISH Controller + 0: Disable, 1: Enable (Default) ISH Controller + $EN_DIS +**/ + UINT8 PchIshEnable; + +/** Offset 0x01B7 - Reserved +**/ + UINT8 Reserved11[178]; + +/** Offset 0x0269 - RpClockReqMsgEnable +**/ + UINT8 RpClockReqMsgEnable; + +/** Offset 0x026A - RpPcieThresholdBytes +**/ + UINT8 RpPcieThresholdBytes[4]; + +/** Offset 0x026E - Reserved +**/ + UINT8 Reserved12[8]; + +/** Offset 0x0276 - Enable or disable HPD of DDI port 1 + 0=Disable, 1(Default)=Enable + $EN_DIS +**/ + UINT8 DdiPort1Hpd; + +/** Offset 0x0277 - Reserved +**/ + UINT8 Reserved13[6]; + +/** Offset 0x027D - Enable DDC setting of DDI Port 1 + 0(Default)=Disable, 1=Enable + $EN_DIS +**/ + UINT8 DdiPort1Ddc; + +/** Offset 0x027E - Reserved +**/ + UINT8 Reserved14[129]; + +/** Offset 0x02FF - DMI Gen3 Root port preset values per lane + Used for programming DMI Gen3 preset values per lane. Range: 0-9, 8 is default for each lane +**/ + UINT8 DmiGen3RootPortPreset[8]; + +/** Offset 0x0307 - Reserved +**/ + UINT8 Reserved15[22]; + +/** Offset 0x031D - C6DRAM power gating feature + This policy indicates whether or not BIOS should allocate PRMRR memory for C6DRAM + power gating feature.- 0: Don't allocate any PRMRR memory for C6DRAM power gating + feature.- 1: Allocate PRMRR memory for C6DRAM power gating feature. + $EN_DIS +**/ + UINT8 EnableC6Dram; + +/** Offset 0x031E - Reserved +**/ + UINT8 Reserved16[5]; + +/** Offset 0x0323 - Hyper Threading Enable/Disable + Enable or Disable Hyper Threading; 0: Disable; 1: Enable + $EN_DIS +**/ + UINT8 HyperThreading; + +/** Offset 0x0324 - Reserved +**/ + UINT8 Reserved17; + +/** Offset 0x0325 - CPU ratio value + CPU ratio value. Valid Range 0 to 63 +**/ + UINT8 CpuRatio; + +/** Offset 0x0326 - Reserved +**/ + UINT8 Reserved18[2]; + +/** Offset 0x0328 - Processor Early Power On Configuration FCLK setting + 0: 800 MHz (ULT/ULX). 1: 1 GHz (DT/Halo). Not supported on ULT/ULX.- + 2: 400 MHz. - 3: Reserved + 0:800 MHz, 1: 1 GHz, 2: 400 MHz, 3: Reserved +**/ + UINT8 FClkFrequency; + +/** Offset 0x0329 - Reserved +**/ + UINT8 Reserved19; + +/** Offset 0x032A - Enable or Disable VMX + Enable or Disable VMX; 0: Disable; 1: Enable. + $EN_DIS +**/ + UINT8 VmxEnable; + +/** Offset 0x032B - Reserved +**/ + UINT8 Reserved20[31]; + +/** Offset 0x034A - BiosGuard + Enable/Disable. 0: Disable, Enable/Disable BIOS Guard feature, 1: enable + $EN_DIS +**/ + UINT8 BiosGuard; + +/** Offset 0x034B +**/ + UINT8 BiosGuardToolsInterface; + +/** Offset 0x034C - Reserved +**/ + UINT8 Reserved21[4]; + +/** Offset 0x0350 - PrmrrSize + Enable/Disable. 0: Disable, define default value of PrmrrSize , 1: enable +**/ + UINT32 PrmrrSize; + +/** Offset 0x0354 - SinitMemorySize + Enable/Disable. 0: Disable, define default value of SinitMemorySize , 1: enable +**/ + UINT32 SinitMemorySize; + +/** Offset 0x0358 - Reserved +**/ + UINT8 Reserved22[8]; + +/** Offset 0x0360 - TxtHeapMemorySize + Enable/Disable. 0: Disable, define default value of TxtHeapMemorySize , 1: enable +**/ + UINT32 TxtHeapMemorySize; + +/** Offset 0x0364 - TxtDprMemorySize + Enable/Disable. 0: Disable, define default value of TxtDprMemorySize , 1: enable +**/ + UINT32 TxtDprMemorySize; + +/** Offset 0x0368 - Reserved +**/ + UINT8 Reserved23[522]; + +/** Offset 0x0572 - Number of RsvdSmbusAddressTable. + The number of elements in the RsvdSmbusAddressTable. +**/ + UINT8 PchNumRsvdSmbusAddresses; + +/** Offset 0x0573 - Reserved +**/ + UINT8 Reserved24[4]; + +/** Offset 0x0577 - Usage type for ClkSrc + 0-23: PCH rootport, 0x40-0x43: PEG port, 0x70:LAN, 0x80: unspecified but in use + (free running), 0xFF: not used +**/ + UINT8 PcieClkSrcUsage[16]; + +/** Offset 0x0587 - Reserved +**/ + UINT8 Reserved25[21]; + +/** Offset 0x059C - Enable PCIE RP Mask + Enable/disable PCIE Root Ports. 0: disable, 1: enable. One bit for each port, bit0 + for port1, bit1 for port2, and so on. +**/ + UINT32 PcieRpEnableMask; + +/** Offset 0x05A0 - Debug Interfaces + Debug Interfaces. BIT0-RAM, BIT1-UART, BIT3-USB3, BIT4-Serial IO, BIT5-TraceHub, + BIT2 - Not used. +**/ + UINT8 PcdDebugInterfaceFlags; + +/** Offset 0x05A1 - Serial Io Uart Debug Controller Number + Select SerialIo Uart Controller for debug. Note: If UART0 is selected as CNVi BT + Core interface, it cannot be used for debug purpose. + 0:SerialIoUart0, 1:SerialIoUart1, 2:SerialIoUart2 +**/ + UINT8 SerialIoUartDebugControllerNumber; + +/** Offset 0x05A2 - Reserved +**/ + UINT8 Reserved26[14]; + +/** Offset 0x05B0 - ISA Serial Base selection + Select ISA Serial Base address. Default is 0x3F8. + 0:0x3F8, 1:0x2F8 +**/ + UINT8 PcdIsaSerialUartBase; + +/** Offset 0x05B1 - Reserved +**/ + UINT8 Reserved27[4]; + +/** Offset 0x05B5 - MRC Safe Config + Enables/Disable MRC Safe Config + $EN_DIS +**/ + UINT8 MrcSafeConfig; + +/** Offset 0x05B6 - TCSS Thunderbolt PCIE Root Port 0 Enable + Set TCSS Thunderbolt PCIE Root Port 0. 0:Disabled 1:Enabled + $EN_DIS +**/ + UINT8 TcssItbtPcie0En; + +/** Offset 0x05B7 - TCSS Thunderbolt PCIE Root Port 1 Enable + Set TCSS Thunderbolt PCIE Root Port 1. 0:Disabled 1:Enabled + $EN_DIS +**/ + UINT8 TcssItbtPcie1En; + +/** Offset 0x05B8 - TCSS Thunderbolt PCIE Root Port 2 Enable + Set TCSS Thunderbolt PCIE Root Port 2. 0:Disabled 1:Enabled + $EN_DIS +**/ + UINT8 TcssItbtPcie2En; + +/** Offset 0x05B9 - TCSS Thunderbolt PCIE Root Port 3 Enable + Set TCSS Thunderbolt PCIE Root Port 3. 0:Disabled 1:Enabled + $EN_DIS +**/ + UINT8 TcssItbtPcie3En; + +/** Offset 0x05BA - TCSS USB HOST (xHCI) Enable + Set TCSS XHCI. 0:Disabled 1:Enabled - Must be enabled if xDCI is enabled below + $EN_DIS +**/ + UINT8 TcssXhciEn; + +/** Offset 0x05BB - TCSS USB DEVICE (xDCI) Enable + Set TCSS XDCI. 0:Disabled 1:Enabled - xHCI must be enabled if xDCI is enabled + $EN_DIS +**/ + UINT8 TcssXdciEn; + +/** Offset 0x05BC - Reserved +**/ + UINT8 Reserved28[4]; + +/** Offset 0x05C0 - Early Command Training + Enables/Disable Early Command Training + $EN_DIS +**/ + UINT8 ECT; + +/** Offset 0x05C1 - Reserved +**/ + UINT8 Reserved29[109]; + +/** Offset 0x062E - Ch Hash Mask + Set the BIT(s) to be included in the XOR function. NOTE BIT mask corresponds to + BITS [19:6] Default is 0x0830 +**/ + UINT16 ChHashMask; + +/** Offset 0x0630 - Reserved +**/ + UINT8 Reserved30[62]; + +/** Offset 0x066E - PcdSerialDebugLevel + Serial Debug Message Level. 0:Disable, 1:Error Only, 2:Error & Warnings, 3:Load, + Error, Warnings & Info, 4:Load, Error, Warnings, Info & Event, 5:Load, Error, Warnings, + Info & Verbose. + 0:Disable, 1:Error Only, 2:Error and Warnings, 3:Load Error Warnings and Info, 4:Load + Error Warnings and Info & Event, 5:Load Error Warnings Info and Verbose +**/ + UINT8 PcdSerialDebugLevel; + +/** Offset 0x066F - Reserved +**/ + UINT8 Reserved31[2]; + +/** Offset 0x0671 - Safe Mode Support + This option configures the varous items in the IO and MC to be more conservative.(def=Disable) + $EN_DIS +**/ + UINT8 SafeMode; + +/** Offset 0x0672 - Reserved +**/ + UINT8 Reserved32[2]; + +/** Offset 0x0674 - TCSS USB Port Enable + Bitmap for per port enabling +**/ + UINT8 UsbTcPortEnPreMem; + +/** Offset 0x0675 - Reserved +**/ + UINT8 Reserved33[80]; + +/** Offset 0x06C5 - Skip external display device scanning + Enable: Do not scan for external display device, Disable (Default): Scan external + display devices + $EN_DIS +**/ + UINT8 SkipExtGfxScan; + +/** Offset 0x06C6 - Reserved +**/ + UINT8 Reserved34[2]; + +/** Offset 0x06C8 - Lock PCU Thermal Management registers + Lock PCU Thermal Management registers. Enable(Default)=1, Disable=0 + $EN_DIS +**/ + UINT8 LockPTMregs; + +/** Offset 0x06C9 - Reserved +**/ + UINT8 Reserved35[122]; + +/** Offset 0x0743 - Enable HD Audio Link + Enable/disable HD Audio Link. Muxed with SSP0/SSP1/SNDW1. + $EN_DIS +**/ + UINT8 PchHdaAudioLinkHdaEnable; + +/** Offset 0x0744 - Reserved +**/ + UINT8 Reserved36[3]; + +/** Offset 0x0747 - Enable HD Audio DMIC_N Link + Enable/disable HD Audio DMIC1 link. Muxed with SNDW3. +**/ + UINT8 PchHdaAudioLinkDmicEnable[2]; + +/** Offset 0x0749 - Reserved +**/ + UINT8 Reserved37[3]; + +/** Offset 0x074C - DMIC ClkA Pin Muxing (N - DMIC number) + Determines DMIC ClkA Pin muxing. See GPIO_*_MUXING_DMIC_CLKA_* +**/ + UINT32 PchHdaAudioLinkDmicClkAPinMux[2]; + +/** Offset 0x0754 - DMIC ClkB Pin Muxing + Determines DMIC ClkA Pin muxing. See GPIO_*_MUXING_DMIC_CLKB_* +**/ + UINT32 PchHdaAudioLinkDmicClkBPinMux[2]; + +/** Offset 0x075C - Enable HD Audio DSP + Enable/disable HD Audio DSP feature. + $EN_DIS +**/ + UINT8 PchHdaDspEnable; + +/** Offset 0x075D - Reserved +**/ + UINT8 Reserved38[3]; + +/** Offset 0x0760 - DMIC Data Pin Muxing + Determines DMIC Data Pin muxing. See GPIO_*_MUXING_DMIC_DATA_* +**/ + UINT32 PchHdaAudioLinkDmicDataPinMux[2]; + +/** Offset 0x0768 - Enable HD Audio SSP0 Link + Enable/disable HD Audio SSP_N/I2S link. Muxed with HDA. N-number 0-5 +**/ + UINT8 PchHdaAudioLinkSspEnable[6]; + +/** Offset 0x076E - Enable HD Audio SoundWire#N Link + Enable/disable HD Audio SNDW#N link. Muxed with HDA. +**/ + UINT8 PchHdaAudioLinkSndwEnable[4]; + +/** Offset 0x0772 - iDisp-Link Frequency + iDisp-Link Freq (PCH_HDAUDIO_LINK_FREQUENCY enum): 4: 96MHz, 3: 48MHz. + 4: 96MHz, 3: 48MHz +**/ + UINT8 PchHdaIDispLinkFrequency; + +/** Offset 0x0773 - iDisp-Link T-mode + iDisp-Link T-Mode (PCH_HDAUDIO_IDISP_TMODE enum): 0: 2T, 2: 4T, 3: 8T, 4: 16T + 0: 2T, 2: 4T, 3: 8T, 4: 16T +**/ + UINT8 PchHdaIDispLinkTmode; + +/** Offset 0x0774 - iDisplay Audio Codec disconnection + 0: Not disconnected, enumerable, 1: Disconnected SDI, not enumerable. + $EN_DIS +**/ + UINT8 PchHdaIDispCodecDisconnect; + +/** Offset 0x0775 - Reserved +**/ + UINT8 Reserved39[315]; +} FSP_M_CONFIG; + +/** Fsp M UPD Configuration +**/ +typedef struct { + +/** Offset 0x0000 +**/ + FSP_UPD_HEADER FspUpdHeader; + +/** Offset 0x0020 +**/ + FSPM_ARCH_UPD FspmArchUpd; + +/** Offset 0x0040 +**/ + FSP_M_CONFIG FspmConfig; + +/** Offset 0x08B0 +**/ + UINT8 UnusedUpdSpace23[6]; + +/** Offset 0x08B6 +**/ + UINT16 UpdTerminator; +} FSPM_UPD; + +#pragma pack() + +#endif diff --git a/src/vendorcode/intel/fsp/fsp2_0/tigerlake/FspsUpd.h b/src/vendorcode/intel/fsp/fsp2_0/tigerlake/FspsUpd.h new file mode 100644 index 0000000000..69f27b99e4 --- /dev/null +++ b/src/vendorcode/intel/fsp/fsp2_0/tigerlake/FspsUpd.h @@ -0,0 +1,683 @@ +/** @file + +Copyright (c) 2019, Intel Corporation. All rights reserved.
+ +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + +* Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. +* Redistributions in binary form must reproduce the above copyright notice, this + list of conditions and the following disclaimer in the documentation and/or + other materials provided with the distribution. +* Neither the name of Intel Corporation nor the names of its contributors may + be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF + THE POSSIBILITY OF SUCH DAMAGE. + + This file is automatically generated. Please do NOT modify !!! + +**/ + +#ifndef __FSPSUPD_H__ +#define __FSPSUPD_H__ + +#include + +#pragma pack(1) + + +/// +/// Azalia Header structure +/// +typedef struct { + UINT16 VendorId; ///< Codec Vendor ID + UINT16 DeviceId; ///< Codec Device ID + UINT8 RevisionId; ///< Revision ID of the codec. 0xFF matches any revision. + UINT8 SdiNum; ///< SDI number, 0xFF matches any SDI. + UINT16 DataDwords; ///< Number of data DWORDs pointed by the codec data buffer. + UINT32 Reserved; ///< Reserved for future use. Must be set to 0. +} AZALIA_HEADER; + +/// +/// Audio Azalia Verb Table structure +/// +typedef struct { + AZALIA_HEADER Header; ///< AZALIA PCH header + UINT32 *Data; ///< Pointer to the data buffer. Its length is specified in the header +} AUDIO_AZALIA_VERB_TABLE; + +/// +/// Refer to the definition of PCH_INT_PIN +/// +typedef enum { + SiPchNoInt, ///< No Interrupt Pin + SiPchIntA, + SiPchIntB, + SiPchIntC, + SiPchIntD +} SI_PCH_INT_PIN; +/// +/// The PCH_DEVICE_INTERRUPT_CONFIG block describes interrupt pin, IRQ and interrupt mode for PCH device. +/// +typedef struct { + UINT8 Device; ///< Device number + UINT8 Function; ///< Device function + UINT8 IntX; ///< Interrupt pin: INTA-INTD (see SI_PCH_INT_PIN) + UINT8 Irq; ///< IRQ to be set for device. +} SI_PCH_DEVICE_INTERRUPT_CONFIG; + +#define SI_PCH_MAX_DEVICE_INTERRUPT_CONFIG 64 ///< Number of all PCH devices + + +/** Fsp S Configuration +**/ +typedef struct { + +/** Offset 0x0020 - Reserved +**/ + UINT8 Reserved0[16]; + +/** Offset 0x0030 - Graphics Configuration Ptr + Points to VBT +**/ + UINT32 GraphicsConfigPtr; + +/** Offset 0x0034 - Enable Device 4 + Enable/disable Device 4 + $EN_DIS +**/ + UINT8 Device4Enable; + +/** Offset 0x0035 - Reserved +**/ + UINT8 Reserved1[12]; + +/** Offset 0x0041 - Enable SATA SALP Support + Enable/disable SATA Aggressive Link Power Management. + $EN_DIS +**/ + UINT8 SataSalpSupport; + +/** Offset 0x0042 - Enable SATA ports + Enable/disable SATA ports. One byte for each port, byte0 for port0, byte1 for port1, + and so on. +**/ + UINT8 SataPortsEnable[8]; + +/** Offset 0x004A - Enable SATA DEVSLP Feature + Enable/disable SATA DEVSLP per port. 0 is disable, 1 is enable. One byte for each + port, byte0 for port0, byte1 for port1, and so on. +**/ + UINT8 SataPortsDevSlp[8]; + +/** Offset 0x0052 - Enable USB2 ports + Enable/disable per USB2 ports. One byte for each port, byte0 for port0, byte1 for + port1, and so on. +**/ + UINT8 PortUsb20Enable[16]; + +/** Offset 0x0062 - Enable USB3 ports + Enable/disable per USB3 ports. One byte for each port, byte0 for port0, byte1 for + port1, and so on. +**/ + UINT8 PortUsb30Enable[10]; + +/** Offset 0x006C - Enable xDCI controller + Enable/disable to xDCI controller. + $EN_DIS +**/ + UINT8 XdciEnable; + +/** Offset 0x006D - Reserved +**/ + UINT8 Reserved2[28]; + +/** Offset 0x0089 - Enable SATA + Enable/disable SATA controller. + $EN_DIS +**/ + UINT8 SataEnable; + +/** Offset 0x008A - SATA Mode + Select SATA controller working mode. + 0:AHCI, 1:RAID +**/ + UINT8 SataMode; + +/** Offset 0x008B - SPIn Device Mode + Selects SPI operation mode. N represents controller index: SPI0, SPI1, ... Available + modes: 0:SerialIoSpiDisabled, 1:SerialIoSpiPci, 2:SerialIoSpiHidden +**/ + UINT8 SerialIoSpiMode[7]; + +/** Offset 0x0092 - Reserved +**/ + UINT8 Reserved3[35]; + +/** Offset 0x00B5 - SPIn Default Chip Select Mode HW/SW + Sets Default CS Mode Hardware or Software. N represents controller index: SPI0, + SPI1, ... Available options: 0:HW, 1:SW +**/ + UINT8 SerialIoSpiCsMode[7]; + +/** Offset 0x00BC - SPIn Default Chip Select State Low/High + Sets Default CS State Low or High. N represents controller index: SPI0, SPI1, ... + Available options: 0:Low, 1:High +**/ + UINT8 SerialIoSpiCsState[7]; + +/** Offset 0x00C3 - UARTn Device Mode + Selects Uart operation mode. N represents controller index: Uart0, Uart1, ... Available + modes: 0:SerialIoUartDisabled, 1:SerialIoUartPci, 2:SerialIoUartHidden, 3:SerialIoUartCom, + 4:SerialIoUartSkipInit +**/ + UINT8 SerialIoUartMode[7]; + +/** Offset 0x00CA - Reserved +**/ + UINT8 Reserved4[74]; + +/** Offset 0x0114 - SerialIoUartRtsPinMuxPolicy + Select SerialIo Uart Rts pin muxing. Refer to GPIO_*_MUXING_SERIALIO_UARTx_RTS* + for possible values. +**/ + UINT32 SerialIoUartRtsPinMuxPolicy[7]; + +/** Offset 0x0130 - SerialIoUartCtsPinMuxPolicy + Select SerialIo Uart Cts pin muxing. Refer to GPIO_*_MUXING_SERIALIO_UARTx_CTS* + for possible values. +**/ + UINT32 SerialIoUartCtsPinMuxPolicy[7]; + +/** Offset 0x014C - SerialIoUartRxPinMuxPolicy + Select SerialIo Uart Rx pin muxing. Refer to GPIO_*_MUXING_SERIALIO_UARTx_RX* for + possible values. +**/ + UINT32 SerialIoUartRxPinMuxPolicy[7]; + +/** Offset 0x0168 - SerialIoUartTxPinMuxPolicy + Select SerialIo Uart Tx pin muxing. Refer to GPIO_*_MUXING_SERIALIO_UARTx_TX* for + possible values. +**/ + UINT32 SerialIoUartTxPinMuxPolicy[7]; + +/** Offset 0x0184 - UART Number For Debug Purpose + UART number for debug purpose. 0:UART0, 1:UART1, 2:UART2, 3:UART3, 4:UART4, 5:UART5, + 6:UART6. Note: If UART0 is selected as CNVi BT Core interface, it cannot be used + for debug purpose. + 0:UART0, 1:UART1, 2:UART2, 3:UART3, 4:UART4, 5:UART5, 6:UART6 +**/ + UINT8 SerialIoDebugUartNumber; + +/** Offset 0x0185 - Reserved +**/ + UINT8 Reserved5[7]; + +/** Offset 0x018C - I2Cn Device Mode + Selects I2c operation mode. N represents controller index: I2c0, I2c1, ... Available + modes: 0:SerialIoI2cDisabled, 1:SerialIoI2cPci, 2:SerialIoI2cHidden +**/ + UINT8 SerialIoI2cMode[8]; + +/** Offset 0x0194 - Serial IO I2C SDA Pin Muxing + Select SerialIo I2c Sda pin muxing. Refer to GPIO_*_MUXING_SERIALIO_I2Cx_SDA* for + possible values. +**/ + UINT32 PchSerialIoI2cSdaPinMux[8]; + +/** Offset 0x01B4 - Serial IO I2C SCL Pin Muxing + Select SerialIo I2c Scl pin muxing. Refer to GPIO_*_MUXING_SERIALIO_I2Cx_SCL* for + possible values. +**/ + UINT32 PchSerialIoI2cSclPinMux[8]; + +/** Offset 0x01D4 - Reserved +**/ + UINT8 Reserved6[192]; + +/** Offset 0x0294 - USB Per Port HS Preemphasis Bias + USB Per Port HS Preemphasis Bias. 000b-0mV, 001b-11.25mV, 010b-16.9mV, 011b-28.15mV, + 100b-28.15mV, 101b-39.35mV, 110b-45mV, 111b-56.3mV. One byte for each port. +**/ + UINT8 Usb2PhyPetxiset[16]; + +/** Offset 0x02A4 - USB Per Port HS Transmitter Bias + USB Per Port HS Transmitter Bias. 000b-0mV, 001b-11.25mV, 010b-16.9mV, 011b-28.15mV, + 100b-28.15mV, 101b-39.35mV, 110b-45mV, 111b-56.3mV, One byte for each port. +**/ + UINT8 Usb2PhyTxiset[16]; + +/** Offset 0x02B4 - USB Per Port HS Transmitter Emphasis + USB Per Port HS Transmitter Emphasis. 00b - Emphasis OFF, 01b - De-emphasis ON, + 10b - Pre-emphasis ON, 11b - Pre-emphasis & De-emphasis ON. One byte for each port. +**/ + UINT8 Usb2PhyPredeemp[16]; + +/** Offset 0x02C4 - USB Per Port Half Bit Pre-emphasis + USB Per Port Half Bit Pre-emphasis. 1b - half-bit pre-emphasis, 0b - full-bit pre-emphasis. + One byte for each port. +**/ + UINT8 Usb2PhyPehalfbit[16]; + +/** Offset 0x02D4 - Enable the write to USB 3.0 TX Output -3.5dB De-Emphasis Adjustment + Enable the write to USB 3.0 TX Output -3.5dB De-Emphasis Adjustment. Each value + in arrary can be between 0-1. One byte for each port. +**/ + UINT8 Usb3HsioTxDeEmphEnable[10]; + +/** Offset 0x02DE - USB 3.0 TX Output -3.5dB De-Emphasis Adjustment Setting + USB 3.0 TX Output -3.5dB De-Emphasis Adjustment Setting, HSIO_TX_DWORD5[21:16], + Default = 29h (approximately -3.5dB De-Emphasis). One byte for each port. +**/ + UINT8 Usb3HsioTxDeEmph[10]; + +/** Offset 0x02E8 - Enable the write to USB 3.0 TX Output Downscale Amplitude Adjustment + Enable the write to USB 3.0 TX Output Downscale Amplitude Adjustment, Each value + in arrary can be between 0-1. One byte for each port. +**/ + UINT8 Usb3HsioTxDownscaleAmpEnable[10]; + +/** Offset 0x02F2 - USB 3.0 TX Output Downscale Amplitude Adjustment + USB 3.0 TX Output Downscale Amplitude Adjustment, HSIO_TX_DWORD8[21:16], Default + = 00h. One byte for each port. +**/ + UINT8 Usb3HsioTxDownscaleAmp[10]; + +/** Offset 0x02FC - Reserved +**/ + UINT8 Reserved7[80]; + +/** Offset 0x034C - Enable LAN + Enable/disable LAN controller. + $EN_DIS +**/ + UINT8 PchLanEnable; + +/** Offset 0x034D - Reserved +**/ + UINT8 Reserved8[11]; + +/** Offset 0x0358 - PCIe PTM enable/disable + Enable/disable Precision Time Measurement for PCIE Root Ports. +**/ + UINT8 PciePtm[24]; + +/** Offset 0x0370 - Reserved +**/ + UINT8 Reserved9[73]; + +/** Offset 0x03B9 - Transition time in microseconds from Low Current Mode Voltage to High Current Mode Voltage + This field has 1us resolution. When value is 0 PCH will not transition VCCIN_AUX + to low current mode voltage. +**/ + UINT8 PchFivrVccinAuxLowToHighCurModeVolTranTime; + +/** Offset 0x03BA - Transition time in microseconds from Retention Mode Voltage to High Current Mode Voltage + This field has 1us resolution. When value is 0 PCH will not transition VCCIN_AUX + to retention mode voltage. +**/ + UINT8 PchFivrVccinAuxRetToHighCurModeVolTranTime; + +/** Offset 0x03BB - Reserved +**/ + UINT8 Reserved10; + +/** Offset 0x03BC - Transition time in microseconds from Off (0V) to High Current Mode Voltage + This field has 1us resolution. When value is 0 Transition to 0V is disabled. +**/ + UINT16 PchFivrVccinAuxOffToHighCurModeVolTranTime; + +/** Offset 0x03BE - Reserved +**/ + UINT8 Reserved11[38]; + +/** Offset 0x03E4 - CNVi Configuration + This option allows for automatic detection of Connectivity Solution. [Auto Detection] + assumes that CNVi will be enabled when available, [Disable] allows for disabling CNVi. + 0:Disable, 1:Auto +**/ + UINT8 CnviMode; + +/** Offset 0x03E5 - CNVi BT Core + Enable/Disable CNVi BT Core, Default is ENABLE. 0: DISABLE, 1: ENABLE + $EN_DIS +**/ + UINT8 CnviBtCore; + +/** Offset 0x03E6 - CNVi BT Audio Offload + Enable/Disable BT Audio Offload, Default is DISABLE. 0: DISABLE, 1: ENABLE + $EN_DIS +**/ + UINT8 CnviBtAudioOffload; + +/** Offset 0x03E7 - Reserved +**/ + UINT8 Reserved12; + +/** Offset 0x03E8 - CNVi RF_RESET pin muxing + Select CNVi RF_RESET# pin depending on board routing. TGP-LP: GPP_A8 = 0x2942E408(default) + or GPP_F4 = 0x194CE404. TGP-H: 0. Refer to GPIO_*_MUXING_CNVI_RF_RESET_* in GpioPins*.h. +**/ + UINT32 CnviRfResetPinMux; + +/** Offset 0x03EC - CNVi CLKREQ pin muxing + Select CNVi CLKREQ pin depending on board routing. TGP-LP: GPP_A9 = 0x3942E609(default) + or GPP_F5 = 0x394CE605. TGP-H: 0. Refer to GPIO_*_MUXING_CNVI_MODEM_CLKREQ_* in + GpioPins*.h. +**/ + UINT32 CnviClkreqPinMux; + +/** Offset 0x03F0 - Reserved +**/ + UINT8 Reserved13[14]; + +/** Offset 0x03FE - HECI3 state + The HECI3 state from Mbp for reference in S3 path or when MbpHob is not installed. + 0: disable, 1: enable + $EN_DIS +**/ + UINT8 Heci3Enabled; + +/** Offset 0x03FF - Reserved +**/ + UINT8 Reserved14[141]; + +/** Offset 0x048C - CdClock Frequency selection + 0 (Default) Auto (Max based on reference clock frequency), 0: 192, 1: 307.2, 2: + 312 Mhz, 3: 552 Mhz, 4: 556.8 Mhz, 5: 648 Mhz, 6: 652.8 Mhz + 0xFF: Auto (Max based on reference clock frequency), 0: 192, 1: 307.2, 2: 312 Mhz, + 3: 552 Mhz, 4: 556.8 Mhz, 5: 648 Mhz, 6: 652.8 Mhz +**/ + UINT8 CdClock; + +/** Offset 0x048D - Enable/Disable PeiGraphicsPeimInit + Enable(Default): Enable PeiGraphicsPeimInit, Disable: Disable PeiGraphicsPeimInit + $EN_DIS +**/ + UINT8 PeiGraphicsPeimInit; + +/** Offset 0x048E - Reserved +**/ + UINT8 Reserved15[2]; + +/** Offset 0x0490 - TypeC port GPIO setting + GPIO Ping number for Type C Aux Oritation setting, use the GpioPad that is defined + in GpioPinsXXXH.h and GpioPinsXXXLp.h as argument.(XXX is platform name, Ex: Tgl + = TigerLake) +**/ + UINT32 IomTypeCPortPadCfg[8]; + +/** Offset 0x04B0 - Reserved +**/ + UINT8 Reserved16[30]; + +/** Offset 0x04CE - TCSS Aux Orientation Override Enable + Bits 0, 2, ... 10 control override enables, bits 1, 3, ... 11 control overrides +**/ + UINT16 TcssAuxOri; + +/** Offset 0x04D0 - TCSS HSL Orientation Override Enable + Bits 0, 2, ... 10 control override enables, bits 1, 3, ... 11 control overrides +**/ + UINT16 TcssHslOri; + +/** Offset 0x04D2 - Reserved +**/ + UINT8 Reserved17[2]; + +/** Offset 0x04D4 - ITBT Root Port Enable + ITBT Root Port Enable, 0:Disable, 1:Enable + 0:Disable, 1:Enable +**/ + UINT8 ITbtPcieRootPortEn[4]; + +/** Offset 0x04D8 - Reserved +**/ + UINT8 Reserved18[11]; + +/** Offset 0x04E3 - Enable/Disable PTM + This policy will enable/disable Precision Time Measurement for TCSS PCIe Root Ports + $EN_DIS +**/ + UINT8 PtmEnabled[4]; + +/** Offset 0x04E7 - Reserved +**/ + UINT8 Reserved19[194]; + +/** Offset 0x05A9 - Skip Multi-Processor Initialization + When this is skipped, boot loader must initialize processors before SilicionInit + API. 0: Initialize; 1: Skip + $EN_DIS +**/ + UINT8 SkipMpInit; + +/** Offset 0x05AA - Reserved +**/ + UINT8 Reserved20[60]; + +/** Offset 0x05E6 - Enable Power Optimizer + Enable DMI Power Optimizer on PCH side. + $EN_DIS +**/ + UINT8 PchPwrOptEnable; + +/** Offset 0x05E7 - Reserved +**/ + UINT8 Reserved21[36]; + +/** Offset 0x060B - Enable PCH ISH SPI Cs0 pins assigned + Set if ISH SPI Cs0 pins are to be enabled by BIOS. 0: Disable; 1: Enable. +**/ + UINT8 PchIshSpiCs0Enable[1]; + +/** Offset 0x060C - Reserved +**/ + UINT8 Reserved22[2]; + +/** Offset 0x060E - Enable PCH ISH SPI pins assigned + Set if ISH SPI native pins are to be enabled by BIOS. 0: Disable; 1: Enable. +**/ + UINT8 PchIshSpiEnable[1]; + +/** Offset 0x060F - Enable PCH ISH UART pins assigned + Set if ISH UART native pins are to be enabled by BIOS. 0: Disable; 1: Enable. +**/ + UINT8 PchIshUartEnable[2]; + +/** Offset 0x0611 - Enable PCH ISH I2C pins assigned + Set if ISH I2C native pins are to be enabled by BIOS. 0: Disable; 1: Enable. +**/ + UINT8 PchIshI2cEnable[3]; + +/** Offset 0x0614 - Enable PCH ISH GP pins assigned + Set if ISH GP native pins are to be enabled by BIOS. 0: Disable; 1: Enable. +**/ + UINT8 PchIshGpEnable[8]; + +/** Offset 0x061C - Reserved +**/ + UINT8 Reserved23[2]; + +/** Offset 0x061E - Enable LOCKDOWN BIOS LOCK + Enable the BIOS Lock feature and set EISS bit (D31:F5:RegDCh[5]) for the BIOS region + protection. + $EN_DIS +**/ + UINT8 PchLockDownBiosLock; + +/** Offset 0x061F - Reserved +**/ + UINT8 Reserved24[75]; + +/** Offset 0x066A - Enable PCIE RP Clk Req Detect + Probe CLKREQ# signal before enabling CLKREQ# based power management. +**/ + UINT8 PcieRpClkReqDetect[24]; + +/** Offset 0x0682 - PCIE RP Advanced Error Report + Indicate whether the Advanced Error Reporting is enabled. +**/ + UINT8 PcieRpAdvancedErrorReporting[24]; + +/** Offset 0x069A - Reserved +**/ + UINT8 Reserved25[168]; + +/** Offset 0x0742 - PCIE RP Max Payload + Max Payload Size supported, Default 128B, see enum PCH_PCIE_MAX_PAYLOAD. +**/ + UINT8 PcieRpMaxPayload[24]; + +/** Offset 0x075A - Reserved +**/ + UINT8 Reserved26[86]; + +/** Offset 0x07B0 - PCIE RP Aspm + The ASPM configuration of the root port (see: PCH_PCIE_ASPM_CONTROL). Default is + PchPcieAspmAutoConfig. +**/ + UINT8 PcieRpAspm[24]; + +/** Offset 0x07C8 - PCIE RP L1 Substates + The L1 Substates configuration of the root port (see: PCH_PCIE_L1SUBSTATES_CONTROL). + Default is PchPcieL1SubstatesL1_1_2. +**/ + UINT8 PcieRpL1Substates[24]; + +/** Offset 0x07E0 - PCIE RP Ltr Enable + Latency Tolerance Reporting Mechanism. +**/ + UINT8 PcieRpLtrEnable[24]; + +/** Offset 0x07F8 - Reserved +**/ + UINT8 Reserved27[98]; + +/** Offset 0x085A - PCH Sata Pwr Opt Enable + SATA Power Optimizer on PCH side. + $EN_DIS +**/ + UINT8 SataPwrOptEnable; + +/** Offset 0x085B - Reserved +**/ + UINT8 Reserved28[50]; + +/** Offset 0x088D - Enable SATA Port DmVal + DITO multiplier. Default is 15. +**/ + UINT8 SataPortsDmVal[8]; + +/** Offset 0x0895 - Reserved +**/ + UINT8 Reserved29; + +/** Offset 0x0896 - Enable SATA Port DmVal + DEVSLP Idle Timeout (DITO), Default is 625. +**/ + UINT16 SataPortsDitoVal[8]; + +/** Offset 0x08A6 - Reserved +**/ + UINT8 Reserved30[72]; + +/** Offset 0x08EE - USB2 Port Over Current Pin + Describe the specific over current pin number of USB 2.0 Port N. +**/ + UINT8 Usb2OverCurrentPin[16]; + +/** Offset 0x08FE - USB3 Port Over Current Pin + Describe the specific over current pin number of USB 3.0 Port N. +**/ + UINT8 Usb3OverCurrentPin[10]; + +/** Offset 0x0908 - Reserved +**/ + UINT8 Reserved31[456]; + +/** Offset 0x0AD0 - RpPtmBytes +**/ + UINT8 RpPtmBytes[4]; + +/** Offset 0x0AD4 - Reserved +**/ + UINT8 Reserved32[101]; + +/** Offset 0x0B39 - GT Frequency Limit + 0xFF: Auto(Default), 2: 100 Mhz, 3: 150 Mhz, 4: 200 Mhz, 5: 250 Mhz, 6: 300 Mhz, + 7: 350 Mhz, 8: 400 Mhz, 9: 450 Mhz, 0xA: 500 Mhz, 0xB: 550 Mhz, 0xC: 600 Mhz, 0xD: + 650 Mhz, 0xE: 700 Mhz, 0xF: 750 Mhz, 0x10: 800 Mhz, 0x11: 850 Mhz, 0x12:900 Mhz, + 0x13: 950 Mhz, 0x14: 1000 Mhz, 0x15: 1050 Mhz, 0x16: 1100 Mhz, 0x17: 1150 Mhz, + 0x18: 1200 Mhz + 0xFF: Auto(Default), 2: 100 Mhz, 3: 150 Mhz, 4: 200 Mhz, 5: 250 Mhz, 6: 300 Mhz, + 7: 350 Mhz, 8: 400 Mhz, 9: 450 Mhz, 0xA: 500 Mhz, 0xB: 550 Mhz, 0xC: 600 Mhz, 0xD: + 650 Mhz, 0xE: 700 Mhz, 0xF: 750 Mhz, 0x10: 800 Mhz, 0x11: 850 Mhz, 0x12:900 Mhz, + 0x13: 950 Mhz, 0x14: 1000 Mhz, 0x15: 1050 Mhz, 0x16: 1100 Mhz, 0x17: 1150 Mhz, + 0x18: 1200 Mhz +**/ + UINT8 GtFreqMax; + +/** Offset 0x0B3A - Reserved +**/ + UINT8 Reserved33[264]; + +/** Offset 0x0C42 - PCIE RP Ltr Max Snoop Latency + Latency Tolerance Reporting, Max Snoop Latency. +**/ + UINT16 PcieRpLtrMaxSnoopLatency[24]; + +/** Offset 0x0C72 - PCIE RP Ltr Max No Snoop Latency + Latency Tolerance Reporting, Max Non-Snoop Latency. +**/ + UINT16 PcieRpLtrMaxNoSnoopLatency[24]; + +/** Offset 0x0CA2 - Reserved +**/ + UINT8 Reserved34[269]; + +/** Offset 0x0DAF - LpmStateEnableMask +**/ + UINT8 LpmStateEnableMask; + +/** Offset 0x0DB0 - Reserved +**/ + UINT8 Reserved35[80]; +} FSP_S_CONFIG; + +/** Fsp S UPD Configuration +**/ +typedef struct { + +/** Offset 0x0000 +**/ + FSP_UPD_HEADER FspUpdHeader; + +/** Offset 0x0020 +**/ + FSP_S_CONFIG FspsConfig; + +/** Offset 0x0E00 +**/ + UINT8 UnusedUpdSpace34[6]; + +/** Offset 0x0E06 +**/ + UINT16 UpdTerminator; +} FSPS_UPD; + +#pragma pack() + +#endif diff --git a/src/vendorcode/intel/fsp/fsp2_0/tigerlake/MemInfoHob.h b/src/vendorcode/intel/fsp/fsp2_0/tigerlake/MemInfoHob.h new file mode 100644 index 0000000000..07de7d7f5a --- /dev/null +++ b/src/vendorcode/intel/fsp/fsp2_0/tigerlake/MemInfoHob.h @@ -0,0 +1,290 @@ +/** @file + This file contains definitions required for creation of + Memory S3 Save data, Memory Info data and Memory Platform + data hobs. + + @copyright + Copyright (c) 1999 - 2019, Intel Corporation. All rights reserved.
+ This program and the accompanying materials are licensed and made available under + the terms and conditions of the BSD License that accompanies this distribution. + The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php. + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +@par Specification Reference: +**/ +#ifndef _MEM_INFO_HOB_H_ +#define _MEM_INFO_HOB_H_ + +#include +#include +#include + +#pragma pack (push, 1) + +extern EFI_GUID gSiMemoryS3DataGuid; +extern EFI_GUID gSiMemoryInfoDataGuid; +extern EFI_GUID gSiMemoryPlatformDataGuid; + +#define MAX_TRACE_CACHE_TYPE 3 + +#define MAX_NODE 2 +#define MAX_CH 4 +#define MAX_DIMM 2 + +/// +/// Host reset states from MRC. +/// +#define WARM_BOOT 2 + +#define R_MC_CHNL_RANK_PRESENT 0x7C +#define B_RANK0_PRS BIT0 +#define B_RANK1_PRS BIT1 +#define B_RANK2_PRS BIT4 +#define B_RANK3_PRS BIT5 + +// @todo remove and use the MdePkg\Include\Pi\PiHob.h +#if !defined(_PEI_HOB_H_) && !defined(__PI_HOB_H__) +#ifndef __HOB__H__ +typedef struct _EFI_HOB_GENERIC_HEADER { + UINT16 HobType; + UINT16 HobLength; + UINT32 Reserved; +} EFI_HOB_GENERIC_HEADER; + +typedef struct _EFI_HOB_GUID_TYPE { + EFI_HOB_GENERIC_HEADER Header; + EFI_GUID Name; + /// + /// Guid specific data goes here + /// +} EFI_HOB_GUID_TYPE; +#endif +#endif + +/// +/// Defines taken from MRC so avoid having to include MrcInterface.h +/// + +// +// Matches MAX_SPD_SAVE define in MRC +// +#ifndef MAX_SPD_SAVE +#define MAX_SPD_SAVE 29 +#endif + +// +// MRC version description. +// +typedef struct { + UINT8 Major; ///< Major version number + UINT8 Minor; ///< Minor version number + UINT8 Rev; ///< Revision number + UINT8 Build; ///< Build number +} SiMrcVersion; + +// +// Matches MrcChannelSts enum in MRC +// +#ifndef CHANNEL_NOT_PRESENT +#define CHANNEL_NOT_PRESENT 0 // There is no channel present on the controller. +#endif +#ifndef CHANNEL_DISABLED +#define CHANNEL_DISABLED 1 // There is a channel present but it is disabled. +#endif +#ifndef CHANNEL_PRESENT +#define CHANNEL_PRESENT 2 // There is a channel present and it is enabled. +#endif + +// +// Matches MrcDimmSts enum in MRC +// +#ifndef DIMM_ENABLED +#define DIMM_ENABLED 0 // DIMM/rank Pair is enabled, presence will be detected. +#endif +#ifndef DIMM_DISABLED +#define DIMM_DISABLED 1 // DIMM/rank Pair is disabled, regardless of presence. +#endif +#ifndef DIMM_PRESENT +#define DIMM_PRESENT 2 // There is a DIMM present in the slot/rank pair and it will be used. +#endif +#ifndef DIMM_NOT_PRESENT +#define DIMM_NOT_PRESENT 3 // There is no DIMM present in the slot/rank pair. +#endif + +// +// Matches MrcBootMode enum in MRC +// +#ifndef __MRC_BOOT_MODE__ +#define __MRC_BOOT_MODE__ //The below values are originated from MrcCommonTypes.h + #ifndef INT32_MAX + #define INT32_MAX (0x7FFFFFFF) + #endif //INT32_MAX +typedef enum { + bmCold, ///< Cold boot + bmWarm, ///< Warm boot + bmS3, ///< S3 resume + bmFast, ///< Fast boot + MrcBootModeMax, ///< MRC_BOOT_MODE enumeration maximum value. + MrcBootModeDelim = INT32_MAX ///< This value ensures the enum size is consistent on both sides of the PPI. +} MRC_BOOT_MODE; +#endif //__MRC_BOOT_MODE__ + +// +// Matches MrcDdrType enum in MRC +// +#ifndef MRC_DDR_TYPE_DDR4 +#define MRC_DDR_TYPE_DDR4 0 +#endif +#ifndef MRC_DDR_TYPE_DDR3 +#define MRC_DDR_TYPE_DDR3 1 +#endif +#ifndef MRC_DDR_TYPE_LPDDR3 +#define MRC_DDR_TYPE_LPDDR3 2 +#endif +#ifndef MRC_DDR_TYPE_LPDDR4 +#define MRC_DDR_TYPE_LPDDR4 3 +#endif +#ifndef MRC_DDR_TYPE_WIO2 +#define MRC_DDR_TYPE_WIO2 4 +#endif +#ifndef MRC_DDR_TYPE_UNKNOWN +#define MRC_DDR_TYPE_UNKNOWN 5 +#endif + +#define MAX_PROFILE_NUM 4 // number of memory profiles supported +#define MAX_XMP_PROFILE_NUM 2 // number of XMP profiles supported + +// +// DIMM timings +// +typedef struct { + UINT32 tCK; ///< Memory cycle time, in femtoseconds. + UINT16 NMode; ///< Number of tCK cycles for the channel DIMM's command rate mode. + UINT16 tCL; ///< Number of tCK cycles for the channel DIMM's CAS latency. + UINT16 tCWL; ///< Number of tCK cycles for the channel DIMM's minimum CAS write latency time. + UINT16 tFAW; ///< Number of tCK cycles for the channel DIMM's minimum four activate window delay time. + UINT16 tRAS; ///< Number of tCK cycles for the channel DIMM's minimum active to precharge delay time. + UINT16 tRCDtRP; ///< Number of tCK cycles for the channel DIMM's minimum RAS# to CAS# delay time and Row Precharge delay time. + UINT16 tREFI; ///< Number of tCK cycles for the channel DIMM's minimum Average Periodic Refresh Interval. + UINT16 tRFC; ///< Number of tCK cycles for the channel DIMM's minimum refresh recovery delay time. + UINT16 tRFCpb; ///< Number of tCK cycles for the channel DIMM's minimum per bank refresh recovery delay time. + UINT16 tRFC2; ///< Number of tCK cycles for the channel DIMM's minimum refresh recovery delay time. + UINT16 tRFC4; ///< Number of tCK cycles for the channel DIMM's minimum refresh recovery delay time. + UINT16 tRPab; ///< Number of tCK cycles for the channel DIMM's minimum row precharge delay time for all banks. + UINT16 tRRD; ///< Number of tCK cycles for the channel DIMM's minimum row active to row active delay time. + UINT16 tRRD_L; ///< Number of tCK cycles for the channel DIMM's minimum row active to row active delay time for same bank groups. + UINT16 tRRD_S; ///< Number of tCK cycles for the channel DIMM's minimum row active to row active delay time for different bank groups. + UINT16 tRTP; ///< Number of tCK cycles for the channel DIMM's minimum internal read to precharge command delay time. + UINT16 tWR; ///< Number of tCK cycles for the channel DIMM's minimum write recovery time. + UINT16 tWTR; ///< Number of tCK cycles for the channel DIMM's minimum internal write to read command delay time. + UINT16 tWTR_L; ///< Number of tCK cycles for the channel DIMM's minimum internal write to read command delay time for same bank groups. + UINT16 tWTR_S; ///< Number of tCK cycles for the channel DIMM's minimum internal write to read command delay time for different bank groups. + UINT16 tCCD_L; ///< Number of tCK cycles for the channel DIMM's minimum CAS-to-CAS delay for same bank group. +} MRC_CH_TIMING; + +/// +/// Memory SMBIOS & OC Memory Data Hob +/// +typedef struct { + UINT8 Status; ///< See MrcDimmStatus for the definition of this field. + UINT8 DimmId; + UINT32 DimmCapacity; ///< DIMM size in MBytes. + UINT16 MfgId; + UINT8 ModulePartNum[20]; ///< Module part number for DDR3 is 18 bytes however for DRR4 20 bytes as per JEDEC Spec, so reserving 20 bytes + UINT8 RankInDimm; ///< The number of ranks in this DIMM. + UINT8 SpdDramDeviceType; ///< Save SPD DramDeviceType information needed for SMBIOS structure creation. + UINT8 SpdModuleType; ///< Save SPD ModuleType information needed for SMBIOS structure creation. + UINT8 SpdModuleMemoryBusWidth; ///< Save SPD ModuleMemoryBusWidth information needed for SMBIOS structure creation. + UINT8 SpdSave[MAX_SPD_SAVE]; ///< Save SPD Manufacturing information needed for SMBIOS structure creation. + UINT16 Speed; ///< The maximum capable speed of the device, in MHz + UINT8 MdSocket; ///< MdSocket: 0 = Memory Down, 1 = Socketed. Needed for SMBIOS structure creation. +} DIMM_INFO; + +typedef struct { + UINT8 Status; ///< Indicates whether this channel should be used. + UINT8 ChannelId; + UINT8 DimmCount; ///< Number of valid DIMMs that exist in the channel. + MRC_CH_TIMING Timing[MAX_PROFILE_NUM]; ///< The channel timing values. + DIMM_INFO DimmInfo[MAX_DIMM]; ///< Save the DIMM output characteristics. +} CHANNEL_INFO; + +typedef struct { + UINT8 Status; ///< Indicates whether this controller should be used. + UINT16 DeviceId; ///< The PCI device id of this memory controller. + UINT8 RevisionId; ///< The PCI revision id of this memory controller. + UINT8 ChannelCount; ///< Number of valid channels that exist on the controller. + CHANNEL_INFO ChannelInfo[MAX_CH]; ///< The following are channel level definitions. +} CONTROLLER_INFO; + +typedef struct { + UINT64 BaseAddress; ///< Trace Base Address + UINT64 TotalSize; ///< Total Trace Region of Same Cache type + UINT8 CacheType; ///< Trace Cache Type + UINT8 ErrorCode; ///< Trace Region Allocation Fail Error code + UINT8 Rsvd[2]; +} PSMI_MEM_INFO; + +typedef struct { + UINT8 Revision; + UINT16 DataWidth; ///< Data width, in bits, of this memory device + /** As defined in SMBIOS 3.0 spec + Section 7.18.2 and Table 75 + **/ + UINT8 MemoryType; ///< DDR type: DDR3, DDR4, or LPDDR3 + UINT16 MaximumMemoryClockSpeed;///< The maximum capable speed of the device, in megahertz (MHz) + UINT16 ConfiguredMemoryClockSpeed; ///< The configured clock speed to the memory device, in megahertz (MHz) + /** As defined in SMBIOS 3.0 spec + Section 7.17.3 and Table 72 + **/ + UINT8 ErrorCorrectionType; + + SiMrcVersion Version; + BOOLEAN EccSupport; + UINT8 MemoryProfile; + UINT32 TotalPhysicalMemorySize; + UINT32 DefaultXmptCK[MAX_XMP_PROFILE_NUM];///< Stores the tCK value read from SPD XMP profiles if they exist. + UINT8 XmpProfileEnable; ///< If XMP capable DIMMs are detected, this will indicate which XMP Profiles are common among all DIMMs. + UINT8 Ratio; + UINT8 RefClk; + UINT32 VddVoltage[MAX_PROFILE_NUM]; + CONTROLLER_INFO Controller[MAX_NODE]; +} MEMORY_INFO_DATA_HOB; + +/** + Memory Platform Data Hob + + Revision 1: + - Initial version. + Revision 2: + - Added TsegBase, PrmrrSize, PrmrrBase, Gttbase, MmioSize, PciEBaseAddress fields +**/ +typedef struct { + UINT8 Revision; + UINT8 Reserved[3]; + UINT32 BootMode; + UINT32 TsegSize; + UINT32 TsegBase; + UINT32 PrmrrSize; + UINT64 PrmrrBase; + UINT32 PramSize; + UINT64 PramBase; + UINT64 DismLimit; + UINT64 DismBase; + UINT32 GttBase; + UINT32 MmioSize; + UINT32 PciEBaseAddress; + PSMI_MEM_INFO PsmiInfo[MAX_TRACE_CACHE_TYPE]; +} MEMORY_PLATFORM_DATA; + +typedef struct { + EFI_HOB_GUID_TYPE EfiHobGuidType; + MEMORY_PLATFORM_DATA Data; + UINT8 *Buffer; +} MEMORY_PLATFORM_DATA_HOB; + +#pragma pack (pop) + +#endif // _MEM_INFO_HOB_H_ From 5395123b849da143d9621b67a6837defe9501acf Mon Sep 17 00:00:00 2001 From: Usha P Date: Mon, 23 Dec 2019 13:21:36 +0530 Subject: [PATCH 0834/1242] soc/intel/skylake: Rename pch_init() code This patch renames pch_init function to bootblock_pch_init and romstage_pch_init according to the stage it is defined in. TEST=Able to build and boot soraka successfully. Change-Id: Idf7b04edc3fce147f7957561ce7d5a0cd05f53fe Signed-off-by: Usha P Reviewed-on: https://review.coreboot.org/c/coreboot/+/37910 Tested-by: build bot (Jenkins) Reviewed-by: Subrata Banik --- src/soc/intel/skylake/bootblock/bootblock.c | 2 +- src/soc/intel/skylake/bootblock/pch.c | 2 +- src/soc/intel/skylake/include/soc/bootblock.h | 2 +- src/soc/intel/skylake/include/soc/romstage.h | 2 +- src/soc/intel/skylake/romstage/pch.c | 6 +++--- src/soc/intel/skylake/romstage/romstage.c | 2 +- 6 files changed, 8 insertions(+), 8 deletions(-) diff --git a/src/soc/intel/skylake/bootblock/bootblock.c b/src/soc/intel/skylake/bootblock/bootblock.c index d1fbb83b8a..26454e4b09 100644 --- a/src/soc/intel/skylake/bootblock/bootblock.c +++ b/src/soc/intel/skylake/bootblock/bootblock.c @@ -44,6 +44,6 @@ void bootblock_soc_init(void) * and abase, i2c programming and print platform info */ report_platform_info(); - pch_init(); + bootblock_pch_init(); gspi_early_bar_init(); } diff --git a/src/soc/intel/skylake/bootblock/pch.c b/src/soc/intel/skylake/bootblock/pch.c index 332060ed2d..ddf1139aa0 100644 --- a/src/soc/intel/skylake/bootblock/pch.c +++ b/src/soc/intel/skylake/bootblock/pch.c @@ -146,7 +146,7 @@ void pch_early_iorange_init(void) pch_enable_lpc(); } -void pch_init(void) +void bootblock_pch_init(void) { /* * Enabling ABASE for accessing PM1_STS, PM1_EN, PM1_CNT, diff --git a/src/soc/intel/skylake/include/soc/bootblock.h b/src/soc/intel/skylake/include/soc/bootblock.h index 302db50fb3..2121821126 100644 --- a/src/soc/intel/skylake/include/soc/bootblock.h +++ b/src/soc/intel/skylake/include/soc/bootblock.h @@ -24,7 +24,7 @@ void bootblock_pch_early_init(void); /* Bootblock post console init programming */ void i2c_early_init(void); -void pch_init(void); +void bootblock_pch_init(void); void pch_early_iorange_init(void); void report_platform_info(void); void report_memory_config(void); diff --git a/src/soc/intel/skylake/include/soc/romstage.h b/src/soc/intel/skylake/include/soc/romstage.h index 674652625b..bd98a2bba8 100644 --- a/src/soc/intel/skylake/include/soc/romstage.h +++ b/src/soc/intel/skylake/include/soc/romstage.h @@ -21,7 +21,7 @@ void mainboard_memory_init_params(FSPM_UPD *mupd); void systemagent_early_init(void); -void pch_init(void); +void romstage_pch_init(void); int smbus_read_byte(unsigned int device, unsigned int address); /* Board type */ enum board_type { diff --git a/src/soc/intel/skylake/romstage/pch.c b/src/soc/intel/skylake/romstage/pch.c index 88a7cc7163..8e783da6f9 100644 --- a/src/soc/intel/skylake/romstage/pch.c +++ b/src/soc/intel/skylake/romstage/pch.c @@ -17,11 +17,11 @@ #include #include -void pch_init(void) +void romstage_pch_init(void) { - /* Programming TCO_BASE_ADDRESS and TCO Timer Halt */ + /* Program TCO_BASE_ADDRESS and TCO Timer Halt */ tco_configure(); - /* Program SMBUS_BASE_ADDRESS and Enable it */ + /* Program SMBUS_BASE_ADDRESS and enable it */ smbus_common_init(); } diff --git a/src/soc/intel/skylake/romstage/romstage.c b/src/soc/intel/skylake/romstage/romstage.c index d381caa104..51428dfe28 100644 --- a/src/soc/intel/skylake/romstage/romstage.c +++ b/src/soc/intel/skylake/romstage/romstage.c @@ -147,7 +147,7 @@ void mainboard_romstage_entry(void) /* Program MCHBAR, DMIBAR, GDXBAR and EDRAMBAR */ systemagent_early_init(); /* Program PCH init */ - pch_init(); + romstage_pch_init(); ps = pmc_get_power_state(); s3wake = pmc_fill_power_state(ps) == ACPI_S3; fsp_memory_init(s3wake); From 33ff4cc137e501b14859bc67cc7e85dd60a863cc Mon Sep 17 00:00:00 2001 From: Usha P Date: Thu, 28 Nov 2019 10:05:45 +0530 Subject: [PATCH 0835/1242] soc/intel/cannonlake: Refactor pch_early_init() code This patch keeps required pch_early_init() function like ABASE programming, GPE and RTC init into bootblock and moves remaining functions like TCO configuration and SMBus init into romstage/pch.c in order to maintain only required chipset programming for bootblock and verstage. Rename the pch_init function to bootblock_pch_init and romstage_pch_init according to the stage it is defined in. TEST=Able to build and boot hatch successfully. Change-Id: Idf7b04edc3fce147f7857561ce7d5b0cd05f43fe Signed-off-by: Usha P Reviewed-on: https://review.coreboot.org/c/coreboot/+/37308 Tested-by: build bot (Jenkins) Reviewed-by: Subrata Banik --- .../intel/cannonlake/bootblock/bootblock.c | 2 +- src/soc/intel/cannonlake/bootblock/pch.c | 13 ++------- .../intel/cannonlake/include/soc/bootblock.h | 2 +- .../intel/cannonlake/include/soc/romstage.h | 1 + .../intel/cannonlake/romstage/Makefile.inc | 1 + src/soc/intel/cannonlake/romstage/pch.c | 27 +++++++++++++++++++ src/soc/intel/cannonlake/romstage/romstage.c | 2 ++ 7 files changed, 35 insertions(+), 13 deletions(-) create mode 100644 src/soc/intel/cannonlake/romstage/pch.c diff --git a/src/soc/intel/cannonlake/bootblock/bootblock.c b/src/soc/intel/cannonlake/bootblock/bootblock.c index 6a6dd8be25..4cc15fca46 100644 --- a/src/soc/intel/cannonlake/bootblock/bootblock.c +++ b/src/soc/intel/cannonlake/bootblock/bootblock.c @@ -74,5 +74,5 @@ void bootblock_soc_init(void) */ gpi_clear_int_cfg(); report_platform_info(); - pch_early_init(); + bootblock_pch_init(); } diff --git a/src/soc/intel/cannonlake/bootblock/pch.c b/src/soc/intel/cannonlake/bootblock/pch.c index 9ad7e86178..a6e9f9db52 100644 --- a/src/soc/intel/cannonlake/bootblock/pch.c +++ b/src/soc/intel/cannonlake/bootblock/pch.c @@ -2,7 +2,7 @@ * This file is part of the coreboot project. * * Copyright (C) 2014 Google Inc. - * Copyright (C) 2017-2018 Intel Corporation. + * Copyright (C) 2017-2019 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -25,8 +25,6 @@ #include #include #include -#include -#include #include #include #include @@ -36,7 +34,6 @@ #include #include #include -#include #define PCR_PSF3_TO_SHDW_PMC_REG_BASE_CNP_LP 0x1400 #define PCR_PSF3_TO_SHDW_PMC_REG_BASE_CNP_H 0x0980 @@ -181,7 +178,7 @@ void pch_early_iorange_init(void) pch_enable_lpc(); } -void pch_early_init(void) +void bootblock_pch_init(void) { /* * Enabling ABASE for accessing PM1_STS, PM1_EN, PM1_CNT, @@ -189,12 +186,6 @@ void pch_early_init(void) */ soc_config_acpibase(); - /* Programming TCO_BASE_ADDRESS and TCO Timer Halt */ - tco_configure(); - - /* Program SMBUS_BASE_ADDRESS and Enable it */ - smbus_common_init(); - /* Set up GPE configuration */ pmc_gpe_init(); diff --git a/src/soc/intel/cannonlake/include/soc/bootblock.h b/src/soc/intel/cannonlake/include/soc/bootblock.h index a5c3c323ae..efc837eb80 100644 --- a/src/soc/intel/cannonlake/include/soc/bootblock.h +++ b/src/soc/intel/cannonlake/include/soc/bootblock.h @@ -23,7 +23,7 @@ void bootblock_cpu_init(void); void bootblock_pch_early_init(void); /* Bootblock post console init programming */ -void pch_early_init(void); +void bootblock_pch_init(void); void pch_early_iorange_init(void); void report_platform_info(void); diff --git a/src/soc/intel/cannonlake/include/soc/romstage.h b/src/soc/intel/cannonlake/include/soc/romstage.h index 643105a0a2..ab20ee7e3f 100644 --- a/src/soc/intel/cannonlake/include/soc/romstage.h +++ b/src/soc/intel/cannonlake/include/soc/romstage.h @@ -24,6 +24,7 @@ void mainboard_memory_init_params(FSPM_UPD *mupd); /* Provide a callback to allow mainboard to override the DRAM part number. */ void mainboard_get_dram_part_num(const char **part_num, size_t *len); void systemagent_early_init(void); +void romstage_pch_init(void); /* Board type */ enum board_type { diff --git a/src/soc/intel/cannonlake/romstage/Makefile.inc b/src/soc/intel/cannonlake/romstage/Makefile.inc index 33d9629e1d..ff3d73dee0 100644 --- a/src/soc/intel/cannonlake/romstage/Makefile.inc +++ b/src/soc/intel/cannonlake/romstage/Makefile.inc @@ -17,3 +17,4 @@ romstage-y += ../../../../cpu/intel/car/romstage.c romstage-y += romstage.c romstage-y += fsp_params.c romstage-y += systemagent.c +romstage-y += pch.c diff --git a/src/soc/intel/cannonlake/romstage/pch.c b/src/soc/intel/cannonlake/romstage/pch.c new file mode 100644 index 0000000000..8e783da6f9 --- /dev/null +++ b/src/soc/intel/cannonlake/romstage/pch.c @@ -0,0 +1,27 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include + +void romstage_pch_init(void) +{ + /* Program TCO_BASE_ADDRESS and TCO Timer Halt */ + tco_configure(); + + /* Program SMBUS_BASE_ADDRESS and enable it */ + smbus_common_init(); +} diff --git a/src/soc/intel/cannonlake/romstage/romstage.c b/src/soc/intel/cannonlake/romstage/romstage.c index f782f63622..2505683479 100644 --- a/src/soc/intel/cannonlake/romstage/romstage.c +++ b/src/soc/intel/cannonlake/romstage/romstage.c @@ -132,6 +132,8 @@ void mainboard_romstage_entry(void) /* Program MCHBAR, DMIBAR, GDXBAR and EDRAMBAR */ systemagent_early_init(); + /* Program PCH init */ + romstage_pch_init(); /* initialize Heci interface */ heci_init(HECI1_BASE_ADDRESS); From e15087691064157532410050c87f6a27f9b85353 Mon Sep 17 00:00:00 2001 From: Usha P Date: Thu, 28 Nov 2019 10:21:02 +0530 Subject: [PATCH 0836/1242] soc/intel/cannonlake: Clean up report_cpu_info() function This patch makes below clean-up for report_cpu_info() function. 1. Remove unused variables. 3. Reuse fill_processor_name. TEST = Successfully able to boot hatch and verify the cpu_name "CPU: Intel(R) Core(TM) i5-10210U CPU @ 1.60GHz" Change-Id: I41c76eb93f0c5229c4a49ab041339b6ad51ad24a Signed-off-by: Usha P Reviewed-on: https://review.coreboot.org/c/coreboot/+/37309 Tested-by: build bot (Jenkins) Reviewed-by: Subrata Banik --- .../cannonlake/bootblock/report_platform.c | 28 +++---------------- 1 file changed, 4 insertions(+), 24 deletions(-) diff --git a/src/soc/intel/cannonlake/bootblock/report_platform.c b/src/soc/intel/cannonlake/bootblock/report_platform.c index 8cdf38e64b..523c1a8f7f 100644 --- a/src/soc/intel/cannonlake/bootblock/report_platform.c +++ b/src/soc/intel/cannonlake/bootblock/report_platform.c @@ -18,6 +18,7 @@ #include #include #include +#include #include #include #include @@ -178,35 +179,14 @@ static uint16_t get_dev_id(pci_devfn_t dev) static void report_cpu_info(void) { - struct cpuid_result cpuidr; - u32 i, index, cpu_id, cpu_feature_flag; - char cpu_string[50], *cpu_name = cpu_string; /* 48 bytes are reported */ + u32 i, cpu_id, cpu_feature_flag; + char cpu_name[49]; int vt, txt, aes; msr_t microcode_ver; static const char *const mode[] = {"NOT ", ""}; const char *cpu_type = "Unknown"; - u32 p[13]; - index = 0x80000000; - cpuidr = cpuid(index); - if (cpuidr.eax < 0x80000004) { - strcpy(cpu_string, "Platform info not available"); - } else { - int j=0; - - for (i = 2; i <= 4; i++) { - cpuidr = cpuid(index + i); - p[j++] = cpuidr.eax; - p[j++] = cpuidr.ebx; - p[j++] = cpuidr.ecx; - p[j++] = cpuidr.edx; - } - p[12]=0; - cpu_name = (char *)p; - } - /* Skip leading spaces in CPU name string */ - while (cpu_name[0] == ' ') - cpu_name++; + fill_processor_name(cpu_name); microcode_ver.lo = 0; microcode_ver.hi = 0; From a8a7374e843bae6c98ad242d2870bef6043d165d Mon Sep 17 00:00:00 2001 From: Wisley Chen Date: Thu, 19 Dec 2019 18:08:09 +0800 Subject: [PATCH 0837/1242] hatch: Fix FPMCU pwr/rst gpio handling for dratini/jinlon In https://review.coreboot.org/c/coreboot/+/37459 (commit fcd8c9e99e7f70e2b9494f2fa28a08ba13126daa) which moves power/reset pin control of FPMCU to var/board/ramstage, but does not implement it for dratini/jinlon. So, add it in dratini/jinlon. BUG=b:146366921 TEST=emerge-hatch coreboot Change-Id: I1b6dbe4ba0a1242aa64346410beed4152b4f457f Signed-off-by: Wisley Chen Reviewed-on: https://review.coreboot.org/c/coreboot/+/37833 Reviewed-by: Tim Wawrzynczak Reviewed-by: Paul Fagerburg Reviewed-by: Paul Menzel Tested-by: build bot (Jenkins) --- .../hatch/variants/dratini/Makefile.inc | 1 + .../google/hatch/variants/dratini/gpio.c | 29 +++++++++++++++++ .../google/hatch/variants/dratini/ramstage.c | 32 +++++++++++++++++++ .../google/hatch/variants/jinlon/Makefile.inc | 1 + .../google/hatch/variants/jinlon/gpio.c | 29 +++++++++++++++++ .../google/hatch/variants/jinlon/ramstage.c | 32 +++++++++++++++++++ 6 files changed, 124 insertions(+) create mode 100644 src/mainboard/google/hatch/variants/dratini/ramstage.c create mode 100644 src/mainboard/google/hatch/variants/jinlon/ramstage.c diff --git a/src/mainboard/google/hatch/variants/dratini/Makefile.inc b/src/mainboard/google/hatch/variants/dratini/Makefile.inc index 4ed09c9a76..0d577cde51 100644 --- a/src/mainboard/google/hatch/variants/dratini/Makefile.inc +++ b/src/mainboard/google/hatch/variants/dratini/Makefile.inc @@ -26,3 +26,4 @@ SPD_SOURCES += 16G_3200_4bg # 0b1001 bootblock-y += gpio.c ramstage-y += gpio.c ramstage-y += variant.c +ramstage-y += ramstage.c diff --git a/src/mainboard/google/hatch/variants/dratini/gpio.c b/src/mainboard/google/hatch/variants/dratini/gpio.c index fd59060756..e3b3d8a23a 100644 --- a/src/mainboard/google/hatch/variants/dratini/gpio.c +++ b/src/mainboard/google/hatch/variants/dratini/gpio.c @@ -134,3 +134,32 @@ const struct pad_config *variant_early_gpio_table(size_t *num) *num = ARRAY_SIZE(early_gpio_table); return early_gpio_table; } + +/* + * Default GPIO settings before entering non-S5 sleep states. + * Configure A12: FPMCU_RST_ODL as GPO before entering sleep. + * This guarantees that A12's native3 function is disabled. + * See commit c41b0e8ea3b2714bf6d6d88a6b66c333c6919f07. + */ +static const struct pad_config default_sleep_gpio_table[] = { + PAD_CFG_GPO(GPP_A12, 1, DEEP), /* FPMCU_RST_ODL */ +}; + +/* + * GPIO settings before entering S5, which are same as default_sleep_gpio_table + * but also, turn off FPMCU. + */ +static const struct pad_config s5_sleep_gpio_table[] = { + PAD_CFG_GPO(GPP_A12, 0, DEEP), /* FPMCU_RST_ODL */ + PAD_CFG_GPO(GPP_C11, 0, DEEP), /* PCH_FP_PWR_EN */ +}; + +const struct pad_config *variant_sleep_gpio_table(u8 slp_typ, size_t *num) +{ + if (slp_typ == ACPI_S5) { + *num = ARRAY_SIZE(s5_sleep_gpio_table); + return s5_sleep_gpio_table; + } + *num = ARRAY_SIZE(default_sleep_gpio_table); + return default_sleep_gpio_table; +} diff --git a/src/mainboard/google/hatch/variants/dratini/ramstage.c b/src/mainboard/google/hatch/variants/dratini/ramstage.c new file mode 100644 index 0000000000..9b919fccd8 --- /dev/null +++ b/src/mainboard/google/hatch/variants/dratini/ramstage.c @@ -0,0 +1,32 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2019 Google LLC + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include +#include + +void variant_ramstage_init(void) +{ + /* + * Enable power to FPMCU, wait for power rail to stabilize, + * and then deassert FPMCU reset. + * Waiting for the power rail to stabilize can take a while, + * a minimum of 400us on Kohaku. + */ + gpio_output(GPP_C11, 1); + mdelay(1); + gpio_output(GPP_A12, 1); +} diff --git a/src/mainboard/google/hatch/variants/jinlon/Makefile.inc b/src/mainboard/google/hatch/variants/jinlon/Makefile.inc index 6e5d8835db..c57d0908ab 100644 --- a/src/mainboard/google/hatch/variants/jinlon/Makefile.inc +++ b/src/mainboard/google/hatch/variants/jinlon/Makefile.inc @@ -25,3 +25,4 @@ SPD_SOURCES += 16G_3200_4bg # 0b1001 bootblock-y += gpio.c ramstage-y += gpio.c +ramstage-y += ramstage.c diff --git a/src/mainboard/google/hatch/variants/jinlon/gpio.c b/src/mainboard/google/hatch/variants/jinlon/gpio.c index 12d96d8496..2bf97b1046 100644 --- a/src/mainboard/google/hatch/variants/jinlon/gpio.c +++ b/src/mainboard/google/hatch/variants/jinlon/gpio.c @@ -110,3 +110,32 @@ const struct pad_config *variant_early_gpio_table(size_t *num) *num = ARRAY_SIZE(early_gpio_table); return early_gpio_table; } + +/* + * Default GPIO settings before entering non-S5 sleep states. + * Configure A12: FPMCU_RST_ODL as GPO before entering sleep. + * This guarantees that A12's native3 function is disabled. + * See commit c41b0e8ea3b2714bf6d6d88a6b66c333c6919f07. + */ +static const struct pad_config default_sleep_gpio_table[] = { + PAD_CFG_GPO(GPP_A12, 1, DEEP), /* FPMCU_RST_ODL */ +}; + +/* + * GPIO settings before entering S5, which are same as default_sleep_gpio_table + * but also, turn off FPMCU. + */ +static const struct pad_config s5_sleep_gpio_table[] = { + PAD_CFG_GPO(GPP_A12, 0, DEEP), /* FPMCU_RST_ODL */ + PAD_CFG_GPO(GPP_C11, 0, DEEP), /* PCH_FP_PWR_EN */ +}; + +const struct pad_config *variant_sleep_gpio_table(u8 slp_typ, size_t *num) +{ + if (slp_typ == ACPI_S5) { + *num = ARRAY_SIZE(s5_sleep_gpio_table); + return s5_sleep_gpio_table; + } + *num = ARRAY_SIZE(default_sleep_gpio_table); + return default_sleep_gpio_table; +} diff --git a/src/mainboard/google/hatch/variants/jinlon/ramstage.c b/src/mainboard/google/hatch/variants/jinlon/ramstage.c new file mode 100644 index 0000000000..9b919fccd8 --- /dev/null +++ b/src/mainboard/google/hatch/variants/jinlon/ramstage.c @@ -0,0 +1,32 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2019 Google LLC + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include +#include + +void variant_ramstage_init(void) +{ + /* + * Enable power to FPMCU, wait for power rail to stabilize, + * and then deassert FPMCU reset. + * Waiting for the power rail to stabilize can take a while, + * a minimum of 400us on Kohaku. + */ + gpio_output(GPP_C11, 1); + mdelay(1); + gpio_output(GPP_A12, 1); +} From 4200a5226305f91e996e415348dcfb7607be4a59 Mon Sep 17 00:00:00 2001 From: Elyes HAOUAS Date: Sat, 21 Dec 2019 08:14:07 +0100 Subject: [PATCH 0838/1242] src: Remove unused include Change-Id: Ic6b66dd8fa387e67bb0ce609fb7e2553eeb66b3c Signed-off-by: Elyes HAOUAS Reviewed-on: https://review.coreboot.org/c/coreboot/+/37888 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin --- src/arch/x86/ebda.c | 1 - src/drivers/generic/gfx/gfx.c | 1 - src/lib/hexdump.c | 1 - src/lib/hexstrtobin.c | 1 - src/security/vboot/common.c | 1 - src/soc/intel/baytrail/acpi.c | 1 - src/soc/intel/skylake/bootblock/report_platform.c | 1 - src/soc/qualcomm/sc7180/aop_load_reset.c | 1 - 8 files changed, 8 deletions(-) diff --git a/src/arch/x86/ebda.c b/src/arch/x86/ebda.c index f2727bb8fe..f92f305d6f 100644 --- a/src/arch/x86/ebda.c +++ b/src/arch/x86/ebda.c @@ -13,7 +13,6 @@ */ #include -#include #include #include #include diff --git a/src/drivers/generic/gfx/gfx.c b/src/drivers/generic/gfx/gfx.c index 76d311cc9c..b2bda4a43c 100644 --- a/src/drivers/generic/gfx/gfx.c +++ b/src/drivers/generic/gfx/gfx.c @@ -19,7 +19,6 @@ #include #include #include -#include #include "chip.h" diff --git a/src/lib/hexdump.c b/src/lib/hexdump.c index 2c9e483d1d..8ecba6d512 100644 --- a/src/lib/hexdump.c +++ b/src/lib/hexdump.c @@ -15,7 +15,6 @@ #include #include #include -#include void hexdump(const void *memory, size_t length) { diff --git a/src/lib/hexstrtobin.c b/src/lib/hexstrtobin.c index 61290b86d3..f0d3e9daba 100644 --- a/src/lib/hexstrtobin.c +++ b/src/lib/hexstrtobin.c @@ -13,7 +13,6 @@ #include #include -#include size_t hexstrtobin(const char *str, uint8_t *buf, size_t len) { diff --git a/src/security/vboot/common.c b/src/security/vboot/common.c index 214f6fa208..aeb4498839 100644 --- a/src/security/vboot/common.c +++ b/src/security/vboot/common.c @@ -18,7 +18,6 @@ #include #include #include -#include #include #include #include diff --git a/src/soc/intel/baytrail/acpi.c b/src/soc/intel/baytrail/acpi.c index db6b27148b..77cc21bb91 100644 --- a/src/soc/intel/baytrail/acpi.c +++ b/src/soc/intel/baytrail/acpi.c @@ -22,7 +22,6 @@ #include #include #include -#include #include #include #include diff --git a/src/soc/intel/skylake/bootblock/report_platform.c b/src/soc/intel/skylake/bootblock/report_platform.c index b0b416e1a0..4a519cfdc2 100644 --- a/src/soc/intel/skylake/bootblock/report_platform.c +++ b/src/soc/intel/skylake/bootblock/report_platform.c @@ -27,7 +27,6 @@ #include #include #include -#include static struct { u32 cpuid; diff --git a/src/soc/qualcomm/sc7180/aop_load_reset.c b/src/soc/qualcomm/sc7180/aop_load_reset.c index 8d22d62056..5cf2311b70 100644 --- a/src/soc/qualcomm/sc7180/aop_load_reset.c +++ b/src/soc/qualcomm/sc7180/aop_load_reset.c @@ -13,7 +13,6 @@ * GNU General Public License for more details. */ -#include #include #include #include From 0405109eed3ddb4305bdb8ac59517e690732adc5 Mon Sep 17 00:00:00 2001 From: Matt DeVillier Date: Fri, 20 Dec 2019 15:36:44 -0600 Subject: [PATCH 0839/1242] mb/google/eve: Update and fix VBT Update Eve's VBT from v211 to v221, and change the backlight control type from PWM to VESA eDP/AUX. This allows the OS to select the proper backlight control type for the panel. Test: Eve backlight control now functional under Windows 10 (Linux requires some pending patches to fix) Change-Id: I8be2a719765891b3f2702c1869981009fa73ca05 Signed-off-by: Matt DeVillier Reviewed-on: https://review.coreboot.org/c/coreboot/+/37880 Tested-by: build bot (Jenkins) Reviewed-by: Angel Pons --- src/mainboard/google/eve/data.vbt | Bin 4608 -> 4608 bytes 1 file changed, 0 insertions(+), 0 deletions(-) diff --git a/src/mainboard/google/eve/data.vbt b/src/mainboard/google/eve/data.vbt index 2f950c82393325948d31ab28f56b2826a7b89636..0f17726d8f37659317b525410e8bd8618b626136 100644 GIT binary patch delta 400 zcmY+)KPZJ^6vy%NzW06cp67X9?>!1Pe>(nzL~a>a#7#&BB!di+#a$E=QLe-yp(i#o zWsvSDll)mQNG7qF43rEKr&#>zGkiNIQ=O^aEcVCaGmx|?w_qz7`43PC$)m0YC%4UU zJ%Cy}>(n54a6So9l=o)$oH7L+f9VDG+9^d~kjc5wCfxEM`YouF+OPwzXZPK*@u{F3 z`eSvl5OZNQ)(Z9BB}4&3v;2395pnAyJcwuUDn5mugOD#0qDnN17LgKtVpxocbhajT zn6uc4oJN{QTtPlSIzhZZenI+13=}shN-6A9JgsP1;kx3iqBDgzir*FGYK&`c(bTJP zNb{VgHI3Vvk2PIsyx07tDc@kiaJ!*FgQJF*3|WJ_hEEOM8GI};?1xkoVnxV3A&rDM c5t@4PGwzdPkFYYkg=2nv$NfJ)>qH;U4}vC0m;e9( delta 384 zcmZ9@&nrYx6bJD8-prWy&b{|}bCihDNn=crnT?nfrb&{N$wIQ4jo2u$AYn>2B=qtZ z*eDD1SV>lXltf9ERu&W+X*MQKvGT3Y;@kI}LaY$mtO|`p-bKpGm=#+oH*_y5MdGlh z*$B59W>AQ@H*3W0ptu+pu4}z|yG9hc|Js-3-5Iqu2@a2r7d4}{``ZL@+wcy|XnxGD z6TN|imv0Xzmc19}E50vM7SC8i~0B~3`2m#`vfPvWVBOG$4Mza`j;k_s~l z`V~znTvo8I$X9r-;8xM6!mx&jrZ$az8iq8@X Date: Thu, 19 Dec 2019 01:09:57 -0600 Subject: [PATCH 0840/1242] mb/google/kefka: Add missing SPD Adapted from Chromium commit 9522225e [Kefka: Add memory SPD info for Hynix H9CCNNN8GTALAR-NUD] Add current available ram_id to support Hynix H9CCNNN8GTALAR-NUD spd info. RAM_ID: 0110 4GiB Hynix H9CCNNN8GTALAR-NUD RAM_ID: 0111 2GiB Hynix H9CCNNN8GTALAR-NUD Original-Change-Id: I48386ff3e5f80de94ea87359a09a5ec2577043b5 Original-Signed-off-by: Peggy Chuang Original-Reviewed-on: https://chromium-review.googlesource.com/664517 Original-Reviewed-by: Aaron Durbin Change-Id: I0ae76c4d8313246927bbc3f71b21f3611c89a6e3 Signed-off-by: Matt DeVillier Reviewed-on: https://review.coreboot.org/c/coreboot/+/37901 Tested-by: build bot (Jenkins) Reviewed-by: Angel Pons --- src/mainboard/google/cyan/variants/kefka/Makefile.inc | 2 ++ src/mainboard/google/cyan/variants/kefka/spd_util.c | 11 ++++++++++- 2 files changed, 12 insertions(+), 1 deletion(-) diff --git a/src/mainboard/google/cyan/variants/kefka/Makefile.inc b/src/mainboard/google/cyan/variants/kefka/Makefile.inc index 7799e8d2b3..d37ba1da08 100644 --- a/src/mainboard/google/cyan/variants/kefka/Makefile.inc +++ b/src/mainboard/google/cyan/variants/kefka/Makefile.inc @@ -28,6 +28,8 @@ SPD_SOURCES += micron_dimm_MT52L256M32D1PF-107 SPD_SOURCES += micron_dimm_MT52L256M32D1PF-107 SPD_SOURCES += samsung_2GiB_dimm_K4E8E324EB-EGCF SPD_SOURCES += samsung_2GiB_dimm_K4E8E324EB-EGCF +SPD_SOURCES += hynix_dimm_H9CCNNN8GTALAR-NUD +SPD_SOURCES += hynix_dimm_H9CCNNN8GTALAR-NUD SPD_DEPS := $(foreach f, $(SPD_SOURCES), src/mainboard/$(MAINBOARDDIR)/spd/$(f).spd.hex) diff --git a/src/mainboard/google/cyan/variants/kefka/spd_util.c b/src/mainboard/google/cyan/variants/kefka/spd_util.c index d9adb721d1..9db56b9492 100644 --- a/src/mainboard/google/cyan/variants/kefka/spd_util.c +++ b/src/mainboard/google/cyan/variants/kefka/spd_util.c @@ -25,10 +25,13 @@ * 0b0011 - 2GiB total - 1 x 2GiB Micron MT52L256M32D1PF-107 * 0b0100 - 4GiB total - 2 x 2GiB Samsung K4E8E324EB-EGCF 1600MHz * 0b0101 - 2GiB total - 1 x 2GiB Samsung K4E8E324EB-EGCF 1600MHz + * 0b0110 - 4GiB total - 2 x 2GiB Hynix H9CCNNN8GTALAR-NUD + * 0b0111 - 2GiB total - 1 x 2GiB Hynix H9CCNNN8GTALAR-NUD * */ -static const uint32_t dual_channel_config = (1 << 0) | (1 << 2) | (1 << 4); +static const uint32_t dual_channel_config = + (1 << 0) | (1 << 2) | (1 << 4) | (1 << 6); int get_variant_spd_index(int ram_id, int *dual) { @@ -55,6 +58,12 @@ int get_variant_spd_index(int ram_id, int *dual) case 5: printk(BIOS_DEBUG, "2GiB Samsung K4E8E324EB-EGCF\n"); break; + case 6: + printk(BIOS_DEBUG, "4GiB Hynix H9CCNNN8GTALAR-NUD\n"); + break; + case 7: + printk(BIOS_DEBUG, "2GiB Hynix H9CCNNN8GTALAR-NUD\n"); + break; } /* 1:1 mapping between ram_id and spd_index for kefka */ From 66406d475480755870fceae6b05f32a8936030de Mon Sep 17 00:00:00 2001 From: Matt DeVillier Date: Sun, 22 Dec 2019 18:34:05 -0600 Subject: [PATCH 0841/1242] mb/google/eve: select SYSTEM_TYPE_CONVERTIBLE select SYSTEM_TYPE_CONVERTIBLE, which properly sets the SMBIOS chassis type, and allows the OS driver to recognize tablet mode capability Change-Id: Ic61659e9fa6f7428afd1f018fb8cb25fe49e8747 Signed-off-by: Matt DeVillier Reviewed-on: https://review.coreboot.org/c/coreboot/+/37903 Tested-by: build bot (Jenkins) Reviewed-by: Angel Pons --- src/mainboard/google/eve/Kconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/src/mainboard/google/eve/Kconfig b/src/mainboard/google/eve/Kconfig index 31ff6e9335..dcc5b383ba 100644 --- a/src/mainboard/google/eve/Kconfig +++ b/src/mainboard/google/eve/Kconfig @@ -21,6 +21,7 @@ config BOARD_SPECIFIC_OPTIONS select MAINBOARD_HAS_LIBGFXINIT select MAINBOARD_HAS_TPM2 select SOC_INTEL_KABYLAKE + select SYSTEM_TYPE_CONVERTIBLE config VBOOT select EC_GOOGLE_CHROMEEC_SWITCHES From 58ececfb28f71cd2560fde3a914cca8c7a49c693 Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Fri, 13 Dec 2019 16:15:50 +0100 Subject: [PATCH 0842/1242] Doc/releases/checklist.md: Correct some inconsistencies Use periods on every element of a list, and make `IRC` uppercase. Also, correct a grammar mistake that slipped through. Change-Id: Id05865719c7c845265416e89bfd9b02b6d22ca6c Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/37709 Tested-by: build bot (Jenkins) Reviewed-by: Matt DeVillier --- Documentation/releases/checklist.md | 34 ++++++++++++++--------------- 1 file changed, 17 insertions(+), 17 deletions(-) diff --git a/Documentation/releases/checklist.md b/Documentation/releases/checklist.md index 49045573d3..706d08e379 100644 --- a/Documentation/releases/checklist.md +++ b/Documentation/releases/checklist.md @@ -49,34 +49,34 @@ be more frequent than was needed, so we scaled it back to twice a year. ## Checklist ### ~2 weeks prior to release - [ ] Announce upcoming release to mailing list, ask people to test and - to update release notes + to update release notes. ### ~1 week prior to release - [ ] Send reminder email to mailing list, ask for people to test, - and to update the release notes -- [ ] Update the topic in the irc channel with the date of the upcoming - release + and to update the release notes. +- [ ] Update the topic in the IRC channel with the date of the upcoming + release. - [ ] If there are any deprecations announced for the following release, - make sure that a list of currently affected board and chipsets is + make sure that a list of currently affected boards and chipsets is part of the release notes. - [ ] Finalize release notes (as much as possible), without specifying - release commit ids + release commit ids. ### Day of release - [ ] Select a commit ID to base the release upon, announce to IRC, ask for testing. -- [ ] Test the commit selected for release -- [ ] Update release notes with actual commit id, push to repo -- [ ] Run release script -- [ ] Test the release from the actual release tarballs -- [ ] Push signed Tag to repo -- [ ] Announce that the release tag is done on IRC +- [ ] Test the commit selected for release. +- [ ] Update release notes with actual commit id, push to repo. +- [ ] Run release script. +- [ ] Test the release from the actual release tarballs. +- [ ] Push signed Tag to repo. +- [ ] Announce that the release tag is done on IRC. - [ ] Upload release files to web server -- [ ] Upload crossgcc sources to web server -- [ ] Update download page to point to files, push to repo +- [ ] Upload crossgcc sources to web server. +- [ ] Update download page to point to files, push to repo. - [ ] Write and publish blog post with release notes. -- [ ] Update the topic in the irc channel that the release is done. -- [ ] Announce the release to the mailing list +- [ ] Update the topic in the IRC channel that the release is done. +- [ ] Announce the release to the mailing list. ## Pre-Release tasks Announce the upcoming release to the mailing list release 2 weeks ahead @@ -102,7 +102,7 @@ to have in the release. The release was based on the final of those patches to be pulled in. When a release candidate has been selected, announce the commit ID to -the #coreboot irc channel, and request that it get some testing, just +the #coreboot IRC channel, and request that it get some testing, just to make sure that everything is sane. ## Generate the release From da6170a22337af4cf227bdfb4e53fac21516d143 Mon Sep 17 00:00:00 2001 From: Peichao Wang Date: Thu, 28 Nov 2019 17:26:19 +0800 Subject: [PATCH 0843/1242] mb/google/hatch/akemi: Set touchpad data hold time more than 300ns According to SI team and vendor request, need to tune I2C bus 0 data hold time more than 300ns BUG=b:146163044 TEST=build firmware and measure I2C bus 0 data hold time Signed-off-by: Peichao Wang Change-Id: I75e33419cbaef746487de6ee8628d07cf08adaa9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/37322 Reviewed-by: Tim Wawrzynczak Reviewed-by: Philip Chen Tested-by: build bot (Jenkins) --- src/mainboard/google/hatch/variants/akemi/overridetree.cb | 1 + 1 file changed, 1 insertion(+) diff --git a/src/mainboard/google/hatch/variants/akemi/overridetree.cb b/src/mainboard/google/hatch/variants/akemi/overridetree.cb index 9b0f5f7b60..d236cb0c94 100644 --- a/src/mainboard/google/hatch/variants/akemi/overridetree.cb +++ b/src/mainboard/google/hatch/variants/akemi/overridetree.cb @@ -57,6 +57,7 @@ chip soc/intel/cannonlake .speed = I2C_SPEED_FAST, .rise_time_ns = 50, .fall_time_ns = 15, + .data_hold_time_ns = 400, }, .i2c[1] = { .speed = I2C_SPEED_FAST, From cca74861202b12033df87b72bad9e5b8b1fccf43 Mon Sep 17 00:00:00 2001 From: Marshall Dawson Date: Thu, 12 Dec 2019 12:38:45 -0700 Subject: [PATCH 0844/1242] soc/amd/picasso: Configure APOB NV only with ACPI resume The APOB NV region holds the save data for resuming. Omit it if the mainboard doesn't use HAVE_ACPI_RESUME. The APOB information will also be board-specific so remove the default values. Change-Id: I65a70bb86ad1f3c11ce37d0afa5a6fdd08bc46e2 Signed-off-by: Marshall Dawson Reviewed-on: https://review.coreboot.org/c/coreboot/+/37722 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth --- src/soc/amd/picasso/Kconfig | 6 ------ src/soc/amd/picasso/Makefile.inc | 2 ++ 2 files changed, 2 insertions(+), 6 deletions(-) diff --git a/src/soc/amd/picasso/Kconfig b/src/soc/amd/picasso/Kconfig index 56c7da776d..7561414c55 100644 --- a/src/soc/amd/picasso/Kconfig +++ b/src/soc/amd/picasso/Kconfig @@ -297,21 +297,15 @@ config PSP_APOB_DESTINATION config PSP_APOB_NV_ADDRESS hex "Base address of APOB NV" - default 0xffa68000 help Location in flash where the PSP can find the S3 restore information. Place this on a boundary that the flash device can erase. - TODO: The above default value is arbitrary, but eventually coreboot's - MRC cache base address should be used. config PSP_APOB_NV_SIZE hex "Size of APOB NV to be reserved" - default 0x10000 help Size of the S3 restore information. Make this a multiple of the size the flash device can erase. - TODO: The above default value is arbitrary, but eventually coreboot's - MRC cache size should be used. config USE_PSPSCUREOS bool "Include PSP SecureOS blobs in PSP build" diff --git a/src/soc/amd/picasso/Makefile.inc b/src/soc/amd/picasso/Makefile.inc index 4492653713..f1e10c183f 100644 --- a/src/soc/amd/picasso/Makefile.inc +++ b/src/soc/amd/picasso/Makefile.inc @@ -207,8 +207,10 @@ PSP_BIOSBIN_DEST=$(CONFIG_ROMSTAGE_ADDR) PSP_BIOSBIN_SIZE=$(CONFIG_RAM_RESET_VECTOR_STAGE_SIZE) # type = 0x63 +ifeq ($(CONFIG_HAVE_ACPI_RESUME),y) PSP_APOBNV_BASE=$(CONFIG_PSP_APOB_NV_ADDRESS) PSP_APOBNV_SIZE=$(CONFIG_PSP_APOB_NV_SIZE) +endif # type2 = 0x64, 0x65 PSP_PMUI_FILE1=$(top)/$(FIRMWARE_LOCATE)/Appb_Rv_1D_Ddr4_Udimm_Imem.csbin From f9ad22d9f7defafd5cccdb8cf40f28f6e9366425 Mon Sep 17 00:00:00 2001 From: Marshall Dawson Date: Fri, 20 Dec 2019 12:26:44 -0700 Subject: [PATCH 0845/1242] src/x86|cpu/intel: Hardcode FIT and ID MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Revert two of the changes made in "arch|cpu/x86: Add Kconfig option for x86 reset vector" I6a814f7179ee4251aeeccb2555221616e944e03d The Intel FIT pointer and the ID section should be offsets from the top of flash, and aren't inherently tied to the reset vector or to bootblock. Signed-off-by: Marshall Dawson Change-Id: I2c9d5e2b2c4248c999d493a72d90cfddd92197cf Reviewed-on: https://review.coreboot.org/c/coreboot/+/37877 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki Reviewed-by: Martin Roth --- src/arch/x86/id.ld | 2 +- src/cpu/intel/fit/fit.ld | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/src/arch/x86/id.ld b/src/arch/x86/id.ld index 3d9ef37ab9..2a50f9ca4f 100644 --- a/src/arch/x86/id.ld +++ b/src/arch/x86/id.ld @@ -12,7 +12,7 @@ */ SECTIONS { - . = (CONFIG_X86_RESET_VECTOR - CONFIG_ID_SECTION_OFFSET) - (__id_end - __id_start) + 0x10; + . = (0xffffffff - CONFIG_ID_SECTION_OFFSET) - (__id_end - __id_start) + 1; .id (.): { KEEP(*(.id)) } diff --git a/src/cpu/intel/fit/fit.ld b/src/cpu/intel/fit/fit.ld index 2e65186e40..6e30ea168a 100644 --- a/src/cpu/intel/fit/fit.ld +++ b/src/cpu/intel/fit/fit.ld @@ -12,7 +12,7 @@ */ SECTIONS { - . = CONFIG_X86_RESET_VECTOR - 0x30; /* 0xffffffc0 */ + . = 0xffffffc0; .fit_pointer (.): { KEEP(*(.fit_pointer)) } From 92b0e8dcae99fea39f167b07063818581a83b1c3 Mon Sep 17 00:00:00 2001 From: Matt DeVillier Date: Mon, 23 Dec 2019 16:08:37 -0600 Subject: [PATCH 0846/1242] drivers/generic/cbfs-serial: Add driver to read serial from CBFS Add a new driver to support reading a board serial number from a text file in CBFS and injecting into the SMBIOS tables. Allow driver to be selected at the .config level and not require inclusion at the board level. Signed-off-by: Matt DeVillier Change-Id: Ieae39f39ab36e5b1f240383b7cf47681d9a311af Reviewed-on: https://review.coreboot.org/c/coreboot/+/37917 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth --- src/drivers/generic/cbfs-serial/Kconfig | 6 +++ src/drivers/generic/cbfs-serial/Makefile.inc | 1 + src/drivers/generic/cbfs-serial/cbfs-serial.c | 50 +++++++++++++++++++ 3 files changed, 57 insertions(+) create mode 100644 src/drivers/generic/cbfs-serial/Kconfig create mode 100644 src/drivers/generic/cbfs-serial/Makefile.inc create mode 100644 src/drivers/generic/cbfs-serial/cbfs-serial.c diff --git a/src/drivers/generic/cbfs-serial/Kconfig b/src/drivers/generic/cbfs-serial/Kconfig new file mode 100644 index 0000000000..209c242dba --- /dev/null +++ b/src/drivers/generic/cbfs-serial/Kconfig @@ -0,0 +1,6 @@ +config DRIVERS_GENERIC_CBFS_SERIAL + bool "Serial number in CBFS" + default n + help + Enable this option to read the board serial number from a + text file located in CBFS. diff --git a/src/drivers/generic/cbfs-serial/Makefile.inc b/src/drivers/generic/cbfs-serial/Makefile.inc new file mode 100644 index 0000000000..163d439ba9 --- /dev/null +++ b/src/drivers/generic/cbfs-serial/Makefile.inc @@ -0,0 +1 @@ +ramstage-$(CONFIG_DRIVERS_GENERIC_CBFS_SERIAL) += cbfs-serial.c diff --git a/src/drivers/generic/cbfs-serial/cbfs-serial.c b/src/drivers/generic/cbfs-serial/cbfs-serial.c new file mode 100644 index 0000000000..ee3e36620c --- /dev/null +++ b/src/drivers/generic/cbfs-serial/cbfs-serial.c @@ -0,0 +1,50 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include +#include + + +#define MAX_SERIAL_LENGTH 0x100 + +const char *smbios_mainboard_serial_number(void) +{ + static char serial_number[MAX_SERIAL_LENGTH + 1] = {0}; + struct cbfsf file; + + if (serial_number[0] != 0) + return serial_number; + + if (cbfs_boot_locate(&file, "serial_number", NULL) == 0) { + struct region_device cbfs_region; + size_t serial_len; + + cbfs_file_data(&cbfs_region, &file); + + serial_len = region_device_sz(&cbfs_region); + if (serial_len <= MAX_SERIAL_LENGTH) { + if (rdev_readat(&cbfs_region, serial_number, 0, + serial_len) == serial_len) { + serial_number[serial_len] = 0; + return serial_number; + } + } + } + + strncpy(serial_number, CONFIG_MAINBOARD_SERIAL_NUMBER, + MAX_SERIAL_LENGTH); + + return serial_number; +} From d28b74ce6a90aad0d555a1a98e2a1c1fa1609c54 Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Wed, 25 Dec 2019 12:19:26 +0100 Subject: [PATCH 0847/1242] Doc/index.md: Fix a typo Change-Id: Ib2f48d03e78f6da97383e67b1d50dfe859e59612 Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/37934 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Rudolph --- Documentation/index.md | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Documentation/index.md b/Documentation/index.md index bfc9cea992..b636b61911 100644 --- a/Documentation/index.md +++ b/Documentation/index.md @@ -175,7 +175,7 @@ Contents: * [Native Graphics Initialization with libgfxinit](gfx/libgfxinit.md) * [Display panel](gfx/display-panel.md) * [CPU Architecture](arch/index.md) -* [Platform independend drivers](drivers/index.md) +* [Platform independent drivers](drivers/index.md) * [Northbridge](northbridge/index.md) * [System on Chip](soc/index.md) * [Mainboard](mainboard/index.md) From 93b343a7793af3975dad8fc2724a9e113eeff79a Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Wed, 25 Dec 2019 11:55:36 +0100 Subject: [PATCH 0848/1242] Doc/tutorial/part1.md: Fix minor formatting issues Make sure all titles are capitalized, and add a missing period. Change-Id: I48b8d6c85b915cc422bdfa3a89804f92f46800ba Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/37932 Tested-by: build bot (Jenkins) Reviewed-by: Jacob Garber --- Documentation/tutorial/part1.md | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/Documentation/tutorial/part1.md b/Documentation/tutorial/part1.md index 75a9ba375f..48145c2dc3 100644 --- a/Documentation/tutorial/part1.md +++ b/Documentation/tutorial/part1.md @@ -15,7 +15,7 @@ Download, configure, and build coreboot $ cd coreboot ### Step 3 - Build the coreboot toolchain -Please note that this can take a significant amount of time +Please note that this can take a significant amount of time. $ make crossgcc-i386 CPUS=$(nproc) @@ -53,7 +53,7 @@ These should be the default selections, so if anything else was set, run select < Exit > select < Yes > -##### check your configuration (optional step): +##### Check your configuration (optional step): $ make savedefconfig $ cat defconfig From a8ab2b33a41ac05899885608c6ca9fcd658859b6 Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Wed, 25 Dec 2019 12:10:46 +0100 Subject: [PATCH 0849/1242] Doc/tutorial/part2.md: Align headings with part1.md Substitute `Part` with `Step` on this file's headings and use present tense instead of gerund. Change-Id: Ic130ed9865be43716e7de3121534761d9fc2ae8d Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/37933 Tested-by: build bot (Jenkins) Reviewed-by: Jacob Garber --- Documentation/tutorial/part2.md | 26 +++++++++++++------------- 1 file changed, 13 insertions(+), 13 deletions(-) diff --git a/Documentation/tutorial/part2.md b/Documentation/tutorial/part2.md index 43e9253fde..5ab210a591 100644 --- a/Documentation/tutorial/part2.md +++ b/Documentation/tutorial/part2.md @@ -1,8 +1,8 @@ # Tutorial, part 2: Submitting a patch to coreboot.org -## Part 1: Setting up an account at coreboot.org +## Step 1: Set up an account at coreboot.org -If you already have an account, skip to Part 2. +If you already have an account, skip to Step 2. Otherwise, go to in your preferred web browser. Select **Sign in** in the upper right corner. @@ -12,13 +12,13 @@ select **Google OAuth2** (gerrit-oauth-provider plugin). **Note:** Your username for the account will be the username of the account you used to sign-in with. (ex. your Google username). -## Part 2a: Set up RSA Private/Public Key +## Step 2a: Set up RSA Private/Public Key -If you prefer to use an HTTP password instead, skip to Part 2b. +If you prefer to use an HTTP password instead, skip to Step 2b. For the most up-to-date instructions on how to set up SSH keys with Gerrit go to -and follow the instructions there. Then, skip to Part 3. +and follow the instructions there. Then, skip to Step 3. Additionally, that section of the Web site provides explanation on starting an ssh-agent, which may be particularly helpful for those who anticipate @@ -44,7 +44,7 @@ forego the password altogether as you will be using it very often. Open `id_rsa.pub`, copy all contents and paste into the textbox under "Add SSH Public Key" in the https://review.coreboot.org webpage. -## Part 2b: Setting up an HTTP Password +## Step 2b: Set up an HTTP Password Alternatively, instead of using SSH keys, you can use an HTTP password. To do so, after you select your name and click on **Settings** on the left-hand side, rather @@ -72,7 +72,7 @@ If that still doesn't allow you to pull or push changes to the server, the proxy is likely tampering with the data stream, in which case there's nothing we can do. -## Part 3: Clone coreboot and configure it for submitting patches +## Step 3: Clone coreboot and configure it for submitting patches On Gerrit, click on the **Browse** tab in the upper left corner and select **Repositories**. From the listing, select the "coreboot" repo. You may have @@ -101,7 +101,7 @@ and other configurations. cd coreboot make gitconfig -## Part 4: Submit a commit +## Step 4: Submit a commit An easy first commit to make is fixing existing checkpatch errors and warnings in the source files. To see errors that are already present, build the files in @@ -119,9 +119,9 @@ and can be submitted for review. Once you finish making your desired changes, use the command line to stage and submit your changes. An alternative and potentially easier way to stage and submit commits is to use git cola, a graphical user interface for git. For -instructions on how to do so, skip to Part 4b. +instructions on how to do so, skip to Step 4b. -## Part 4a: Using the command line to stage and submit a commit +## Step 4a: Use the command line to stage and submit a commit To use the command line to stage a commit, run @@ -181,7 +181,7 @@ using git. You may wish to review the [Gerrit code review workflow documentation](https://gerrit-review.googlesource.com/Documentation/intro-user.html#code-review), especially if you plan to work on multiple changes at the same time. -## Part 4b: Using git cola to stage and submit a commit +## Step 4b: Use git cola to stage and submit a commit If git cola is not installed on your machine, see for download instructions. @@ -242,7 +242,7 @@ explained in the extended description. When ready, select 'Commit' again. Once all errors have been satisfied and the commit succeeds, move to the command line and run `git push`. -## Part 5: Getting your commit reviewed +## Step 5: Let others review your commit Your commits can now be seen on review.coreboot.org if you select "Your" and click on "Changes" and can be reviewed by others. Your code will @@ -252,7 +252,7 @@ users may also give your commit +1. For a commit to be merged, it needs to receive a +2. **Note:** A +1 and a +1 does not make a +2. Only certain users can give a +2. -## Part 6 (optional): bash-git-prompt +## Step 6 (optional): bash-git-prompt To help make it easier to understand the state of the git repository without running `git status` or `git log`, there is a way to make the From 086f0faf756a2d4e71fd9c1d27335af240418b19 Mon Sep 17 00:00:00 2001 From: Eric Lai Date: Fri, 13 Dec 2019 12:31:46 +0800 Subject: [PATCH 0850/1242] soc/intel/cannonlake: Move GPIO PM configuration to soc level Enable GPIO clock gating when enter s0ix/Sx and save the PM bits. Restore the PM bits when exit s0ix/Sx. BUG=b:144002424 TEST=Check GPIO PM bits when enter/exit s0ix are expected Signed-off-by: Eric Lai Change-Id: I120f8369b8d3cf7ac821332bdfa124f6ed0570e9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/37685 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh --- src/soc/intel/cannonlake/acpi/gpio.asl | 41 ++++++++++++++++++++++++++ src/soc/intel/cannonlake/acpi/lpit.asl | 17 +++++++++++ src/soc/intel/common/acpi/platform.asl | 15 ++++++++++ 3 files changed, 73 insertions(+) diff --git a/src/soc/intel/cannonlake/acpi/gpio.asl b/src/soc/intel/cannonlake/acpi/gpio.asl index 65332ad7c0..7702ad556c 100644 --- a/src/soc/intel/cannonlake/acpi/gpio.asl +++ b/src/soc/intel/cannonlake/acpi/gpio.asl @@ -157,3 +157,44 @@ Method (CGPM, 2, Serialized) PCRO (Local0, GPIO_MISCCFG, And (Arg1, MISCCFG_ENABLE_GPIO_PM_CONFIG)) } } + +/* GPIO Power Management bits */ +Name(GPMB, Package(TOTAL_GPIO_COMM) {0}) + +/* + * Save GPIO Power Management bits + */ +Method (SGPM, 0, Serialized) +{ + For (Local0 = 0, Local0 < TOTAL_GPIO_COMM, Local0++) + { + Local1 = GPID (Local0) + GPMB[Local0] = PCRR (Local1, GPIO_MISCCFG) + } +} + +/* + * Restore GPIO Power Management bits + */ +Method (RGPM, 0, Serialized) +{ + For (Local0 = 0, Local0 < TOTAL_GPIO_COMM, Local0++) + { + CGPM (Local0, DerefOf(GPMB[Local0])) + } +} + +/* + * Save current setting of GPIO Power Management bits and + * enable all Power Management bits for all communities + */ +Method (EGPM, 0, Serialized) +{ + /* Save current setting and will restore it when resuming */ + SGPM () + /* Enable PM bits */ + For (Local0 = 0, Local0 < TOTAL_GPIO_COMM, Local0++) + { + CGPM (Local0, MISCCFG_ENABLE_GPIO_PM_CONFIG) + } +} diff --git a/src/soc/intel/cannonlake/acpi/lpit.asl b/src/soc/intel/cannonlake/acpi/lpit.asl index 74d4fe6396..e0e23cac4e 100644 --- a/src/soc/intel/cannonlake/acpi/lpit.asl +++ b/src/soc/intel/cannonlake/acpi/lpit.asl @@ -16,6 +16,8 @@ External(\_SB.MS0X, MethodObj) External(\_SB.PCI0.LPCB.EC0.S0IX, MethodObj) +External(\_SB.PCI0.EGPM, MethodObj) +External(\_SB.PCI0.RGPM, MethodObj) scope(\_SB) { @@ -73,6 +75,15 @@ scope(\_SB) If (CondRefOf (\_SB.MS0X)) { \_SB.MS0X(1) } + + /* + * Save the current PM bits then + * enable GPIO PM with MISCCFG_ENABLE_GPIO_PM_CONFIG + */ + If (CondRefOf (\_SB.PCI0.EGPM)) + { + \_SB.PCI0.EGPM () + } } /* * Function 6 - Low Power S0 Exit Notification @@ -87,6 +98,12 @@ scope(\_SB) If (CondRefOf (\_SB.MS0X)) { \_SB.MS0X(0) } + + /* Restore GPIO all Community PM */ + If (CondRefOf (\_SB.PCI0.RGPM)) + { + \_SB.PCI0.RGPM () + } } } Return(Buffer(One) {0x00}) diff --git a/src/soc/intel/common/acpi/platform.asl b/src/soc/intel/common/acpi/platform.asl index 9aa2edc6df..c41ccbe0cb 100644 --- a/src/soc/intel/common/acpi/platform.asl +++ b/src/soc/intel/common/acpi/platform.asl @@ -19,6 +19,8 @@ External(\_SB.MPTS, MethodObj) External(\_SB.MWAK, MethodObj) +External(\_SB.PCI0.EGPM, MethodObj) +External(\_SB.PCI0.RGPM, MethodObj) /* Port 80 POST */ @@ -41,6 +43,14 @@ Method (_PTS, 1) { \_SB.MPTS (Arg0) } + /* + * Save the current PM bits then + * enable GPIO PM with MISCCFG_ENABLE_GPIO_PM_CONFIG + */ + If (CondRefOf (\_SB.PCI0.EGPM)) + { + \_SB.PCI0.EGPM () + } } /* The _WAK method is called on system wakeup */ @@ -53,6 +63,11 @@ Method (_WAK, 1) { \_SB.MWAK (Arg0) } + /* Restore GPIO all Community PM */ + If (CondRefOf (\_SB.PCI0.RGPM)) + { + \_SB.PCI0.RGPM () + } Return (Package(){0,0}) } From 325fd3462e0b4088f915a7583295334779f5270e Mon Sep 17 00:00:00 2001 From: Tommie Date: Mon, 23 Dec 2019 13:33:34 +0800 Subject: [PATCH 0851/1242] mb/google/octopus: Add two new sku IDs for foob Declare these sku IDs: -SKU: 1 Foob, 1-cam, no touch, no pen. -SKU: 9 Foob360, 2-cam, touch, pen. BUG=b:145837644 BRANCH=octopus TEST=emerge-octopus coreboot Signed-off-by: tong.lin Change-Id: Iffcbb3f6f945ea299ff687a383a82b88dcd11ea1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/37906 Tested-by: build bot (Jenkins) Reviewed-by: Marco Chen --- .../google/octopus/variants/foob/Makefile.inc | 2 +- .../google/octopus/variants/foob/gpio.c | 45 ++++++++++++++++++- .../google/octopus/variants/foob/variant.c | 36 +++++++++++++++ 3 files changed, 80 insertions(+), 3 deletions(-) create mode 100644 src/mainboard/google/octopus/variants/foob/variant.c diff --git a/src/mainboard/google/octopus/variants/foob/Makefile.inc b/src/mainboard/google/octopus/variants/foob/Makefile.inc index 9fb63f5f43..a291304bc0 100644 --- a/src/mainboard/google/octopus/variants/foob/Makefile.inc +++ b/src/mainboard/google/octopus/variants/foob/Makefile.inc @@ -1,3 +1,3 @@ bootblock-y += gpio.c - ramstage-y += gpio.c +ramstage-y += variant.c diff --git a/src/mainboard/google/octopus/variants/foob/gpio.c b/src/mainboard/google/octopus/variants/foob/gpio.c index 27ce0eea61..dec2ff550d 100644 --- a/src/mainboard/google/octopus/variants/foob/gpio.c +++ b/src/mainboard/google/octopus/variants/foob/gpio.c @@ -20,6 +20,8 @@ #include #include +#define SKU_UNKNOWN 0xFFFFFFFF + static const struct pad_config default_override_table[] = { PAD_NC(GPIO_52, UP_20K), PAD_NC(GPIO_53, UP_20K), @@ -37,8 +39,47 @@ static const struct pad_config default_override_table[] = { PAD_NC(GPIO_214, DN_20K), }; +static const struct pad_config non_touchscreen_override_table[] = { + /* disable I2C7 SCL and SDA */ + PAD_NC(GPIO_114, UP_20K), /* LPSS_I2C7_SDA */ + PAD_NC(GPIO_115, UP_20K), /* LPSS_I2C7_SCL */ + + PAD_NC(GPIO_52, UP_20K), + PAD_NC(GPIO_53, UP_20K), + PAD_NC(GPIO_67, UP_20K), + PAD_NC(GPIO_117, UP_20K), + PAD_NC(GPIO_143, UP_20K), + + /* EN_PP3300_TOUCHSCREEN */ + PAD_NC(GPIO_146, UP_20K), + + PAD_NC(GPIO_161, DN_20K), + + PAD_NC(GPIO_213, DN_20K), + PAD_NC(GPIO_214, DN_20K), +}; + +bool no_touchscreen_sku(uint32_t sku_id) +{ + if (sku_id != 9) + return true; + else + return false; +} + const struct pad_config *variant_override_gpio_table(size_t *num) { - *num = ARRAY_SIZE(default_override_table); - return default_override_table; + const struct pad_config *c; + uint32_t sku_id = SKU_UNKNOWN; + + sku_id = get_board_sku(); + if (no_touchscreen_sku(sku_id)) { + c = non_touchscreen_override_table; + *num = ARRAY_SIZE(non_touchscreen_override_table); + } else { + c = default_override_table; + *num = ARRAY_SIZE(default_override_table); + } + + return c; } diff --git a/src/mainboard/google/octopus/variants/foob/variant.c b/src/mainboard/google/octopus/variants/foob/variant.c new file mode 100644 index 0000000000..dcc11dd0bb --- /dev/null +++ b/src/mainboard/google/octopus/variants/foob/variant.c @@ -0,0 +1,36 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2019 Google LLC + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include + +#define SKU_UNKNOWN 0xFFFFFFFF + +void variant_update_devtree(struct device *dev) +{ + uint32_t sku_id = SKU_UNKNOWN; + struct device *touchscreen_i2c_host; + + touchscreen_i2c_host = pcidev_path_on_root(PCH_DEVFN_I2C7); + + if (touchscreen_i2c_host == NULL) + return; + + /* SKU ID 1 does not have a touchscreen device, hence disable it. */ + sku_id = get_board_sku(); + if (no_touchscreen_sku(sku_id)) + touchscreen_i2c_host->enabled = 0; +} From b091b33c2a4695fdc422126128da05d3d5c9fb77 Mon Sep 17 00:00:00 2001 From: Sheng-Liang Pan Date: Wed, 11 Dec 2019 08:35:04 +0800 Subject: [PATCH 0852/1242] mb/google/octopus/variants/bobba: fix LTE power sequence and move get_board_sku to smm stage. fix Power_off section power sequence. power_off_lte_module() should run in smm stage, add variant.c in smm stage. also move get_board_sku() to mainboard_misc.c so that we can use it in smm stage and ramstage. BUG=b:144327240 BRANCH=octopus TEST=build image and verify on the DUT with LTE DB. Change-Id: I287ba1cb092a95b3a9dd1f960a3b84fd85b9b221 Signed-off-by: Pan Sheng-Liang Reviewed-on: https://review.coreboot.org/c/coreboot/+/37649 Reviewed-by: Marco Chen Reviewed-by: Ren Kuo Tested-by: build bot (Jenkins) --- src/mainboard/google/octopus/Makefile.inc | 2 + src/mainboard/google/octopus/mainboard.c | 32 ----------- src/mainboard/google/octopus/mainboard_misc.c | 54 +++++++++++++++++++ .../octopus/variants/bobba/Makefile.inc | 2 + 4 files changed, 58 insertions(+), 32 deletions(-) create mode 100644 src/mainboard/google/octopus/mainboard_misc.c diff --git a/src/mainboard/google/octopus/Makefile.inc b/src/mainboard/google/octopus/Makefile.inc index aa055246d2..d36d5f7dbe 100644 --- a/src/mainboard/google/octopus/Makefile.inc +++ b/src/mainboard/google/octopus/Makefile.inc @@ -5,10 +5,12 @@ romstage-$(CONFIG_CHROMEOS) += chromeos.c ramstage-$(CONFIG_CHROMEOS) += chromeos.c ramstage-y += ec.c +ramstage-y += mainboard_misc.c ramstage-y += mainboard.c verstage-$(CONFIG_CHROMEOS) += chromeos.c smm-y += smihandler.c +smm-y += mainboard_misc.c subdirs-y += variants/baseboard CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/variants/baseboard/include diff --git a/src/mainboard/google/octopus/mainboard.c b/src/mainboard/google/octopus/mainboard.c index 3312d4d988..0ab4693bfc 100644 --- a/src/mainboard/google/octopus/mainboard.c +++ b/src/mainboard/google/octopus/mainboard.c @@ -117,38 +117,6 @@ struct chip_operations mainboard_ops = { .enable_dev = mainboard_enable, }; -#define SKU_UNKNOWN 0xFFFFFFFF -#define SKU_MAX 255 - -uint32_t get_board_sku(void) -{ - static uint32_t sku_id = SKU_UNKNOWN; - - if (sku_id != SKU_UNKNOWN) - return sku_id; - - if (google_chromeec_cbi_get_sku_id(&sku_id)) - sku_id = SKU_UNKNOWN; - - return sku_id; -} - -const char *smbios_system_sku(void) -{ - static char sku_str[7]; /* sku{0..255} */ - uint32_t sku_id = get_board_sku(); - - if ((sku_id == SKU_UNKNOWN) || (sku_id > SKU_MAX)) { - printk(BIOS_ERR, "%s: Unexpected SKU ID %u\n", - __func__, sku_id); - return ""; - } - - snprintf(sku_str, sizeof(sku_str), "sku%u", sku_id); - - return sku_str; -} - void __weak variant_update_devtree(struct device *dev) { /* Place holder for common updates. */ diff --git a/src/mainboard/google/octopus/mainboard_misc.c b/src/mainboard/google/octopus/mainboard_misc.c new file mode 100644 index 0000000000..3672f66692 --- /dev/null +++ b/src/mainboard/google/octopus/mainboard_misc.c @@ -0,0 +1,54 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2019 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include +#include +#include +#include +#include + +#define SKU_UNKNOWN 0xFFFFFFFF +#define SKU_MAX 255 + +uint32_t get_board_sku(void) +{ + static uint32_t sku_id = SKU_UNKNOWN; + + if (sku_id != SKU_UNKNOWN) + return sku_id; + + if (google_chromeec_cbi_get_sku_id(&sku_id)) + sku_id = SKU_UNKNOWN; + + return sku_id; +} + +const char *smbios_system_sku(void) +{ + static char sku_str[7]; /* sku{0..255} */ + uint32_t sku_id = get_board_sku(); + + if ((sku_id == SKU_UNKNOWN) || (sku_id > SKU_MAX)) { + printk(BIOS_ERR, "%s: Unexpected SKU ID %u\n", + __func__, sku_id); + return ""; + } + + snprintf(sku_str, sizeof(sku_str), "sku%u", sku_id); + + return sku_str; +} diff --git a/src/mainboard/google/octopus/variants/bobba/Makefile.inc b/src/mainboard/google/octopus/variants/bobba/Makefile.inc index ba865e9f82..7ee7e70d4b 100644 --- a/src/mainboard/google/octopus/variants/bobba/Makefile.inc +++ b/src/mainboard/google/octopus/variants/bobba/Makefile.inc @@ -2,3 +2,5 @@ bootblock-y += gpio.c ramstage-y += gpio.c ramstage-y += variant.c + +smm-y += variant.c From d4f39abebf069517321b5fc6157ad65318b13cf3 Mon Sep 17 00:00:00 2001 From: Ren Kuo Date: Wed, 25 Dec 2019 14:18:08 +0800 Subject: [PATCH 0853/1242] mb/google/octopus/variants/dood: support LTE module related LTE GPIOs: GPIO_67 - EN_PP3300 GPIO_117 - FULL_CARD_POWER_ON_OFF GPIO_161 - PLT_RST_LTE_L 1. Power on: GPIO_67 -> 0ms -> GPIO_117 -> 30ms -> GPIO_161 2. Power off: GPIO_161 -> 30ms -> GPIO_117 -> 100ms -> GPIO_67 3. Power reset: - keep GPIO_67 and GPIO_117 high and - pull down GPIO_161 for 30ms then release it. BUG=b:146843935 BRANCH=octopus TEST=build and verify on the DUT with LTE Signed-off-by: Ren Kuo Change-Id: Ief6c993ede2bb4b3effbb05cfe22b7af4fcf7faf Reviewed-on: https://review.coreboot.org/c/coreboot/+/37931 Tested-by: build bot (Jenkins) Reviewed-by: Marco Chen --- .../google/octopus/variants/dood/Makefile.inc | 3 + .../google/octopus/variants/dood/gpio.c | 56 ++++++++++++++- .../google/octopus/variants/dood/variant.c | 71 +++++++++++++++++++ 3 files changed, 128 insertions(+), 2 deletions(-) create mode 100644 src/mainboard/google/octopus/variants/dood/variant.c diff --git a/src/mainboard/google/octopus/variants/dood/Makefile.inc b/src/mainboard/google/octopus/variants/dood/Makefile.inc index 9fb63f5f43..7ee7e70d4b 100644 --- a/src/mainboard/google/octopus/variants/dood/Makefile.inc +++ b/src/mainboard/google/octopus/variants/dood/Makefile.inc @@ -1,3 +1,6 @@ bootblock-y += gpio.c ramstage-y += gpio.c +ramstage-y += variant.c + +smm-y += variant.c diff --git a/src/mainboard/google/octopus/variants/dood/gpio.c b/src/mainboard/google/octopus/variants/dood/gpio.c index 05a05f6565..5b567b3691 100644 --- a/src/mainboard/google/octopus/variants/dood/gpio.c +++ b/src/mainboard/google/octopus/variants/dood/gpio.c @@ -19,6 +19,11 @@ #include #include +enum { + SKU_1_LTE = 1, /* Wifi + LTE */ + SKU_2_WIFI = 2, /* Wifi */ +}; + static const struct pad_config default_override_table[] = { PAD_NC(GPIO_104, UP_20K), @@ -29,9 +34,56 @@ static const struct pad_config default_override_table[] = { PAD_NC(GPIO_213, DN_20K), }; +static const struct pad_config lte_override_table[] = { + /* Default override table. */ + PAD_NC(GPIO_104, UP_20K), + + /* EN_PP3300_TOUCHSCREEN */ + PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_146, 0, DEEP, NONE, Tx0RxDCRx0, + DISPUPD), + + PAD_NC(GPIO_213, DN_20K), + + /* Be specific to LTE SKU */ + /* UART2-CTS_B -- EN_PP3300_DX_LTE_SOC */ + PAD_CFG_GPO(GPIO_67, 1, PWROK), + + /* PCIE_WAKE1_B -- FULL_CARD_POWER_OFF */ + PAD_CFG_GPO(GPIO_117, 1, PWROK), + + /* AVS_I2S1_MCLK -- PLT_RST_LTE_L */ + PAD_CFG_GPO(GPIO_161, 1, DEEP), +}; + const struct pad_config *variant_override_gpio_table(size_t *num) { - *num = ARRAY_SIZE(default_override_table); + uint32_t sku_id; + sku_id = get_board_sku(); - return default_override_table; + switch (sku_id) { + case SKU_1_LTE: + *num = ARRAY_SIZE(lte_override_table); + return lte_override_table; + default: + *num = ARRAY_SIZE(default_override_table); + return default_override_table; + } +} + +static const struct pad_config lte_early_override_table[] = { + /* UART2-CTS_B -- EN_PP3300_DX_LTE_SOC */ + PAD_CFG_GPO(GPIO_67, 1, PWROK), + + /* PCIE_WAKE1_B -- FULL_CARD_POWER_OFF */ + PAD_CFG_GPO(GPIO_117, 1, PWROK), + + /* AVS_I2S1_MCLK -- PLT_RST_LTE_L */ + PAD_CFG_GPO(GPIO_161, 0, DEEP), +}; + +const struct pad_config *variant_early_override_gpio_table(size_t *num) +{ + *num = ARRAY_SIZE(lte_early_override_table); + + return lte_early_override_table; } diff --git a/src/mainboard/google/octopus/variants/dood/variant.c b/src/mainboard/google/octopus/variants/dood/variant.c new file mode 100644 index 0000000000..7116061019 --- /dev/null +++ b/src/mainboard/google/octopus/variants/dood/variant.c @@ -0,0 +1,71 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2019 Google LLC + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include +#include +#include +#include + +enum { + SKU_1_LTE = 1, /* Wifi + LTE */ + SKU_2_WIFI = 2, /* Wifi */ +}; + +struct gpio_with_delay { + gpio_t gpio; + unsigned int delay_msecs; +}; + +static void power_off_lte_module(u8 slp_typ) +{ + const struct gpio_with_delay lte_power_off_gpios[] = { + { + GPIO_161, /* AVS_I2S1_MCLK -- PLT_RST_LTE_L */ + 30, + }, + { + GPIO_117, /* PCIE_WAKE1_B -- FULL_CARD_POWER_OFF */ + 100 + }, + { + GPIO_67, /* UART2-CTS_B -- EN_PP3300_DX_LTE_SOC */ + 0 + } + }; + + for (int i = 0; i < ARRAY_SIZE(lte_power_off_gpios); i++) { + gpio_output(lte_power_off_gpios[i].gpio, 0); + mdelay(lte_power_off_gpios[i].delay_msecs); + } +} + + +void variant_smi_sleep(u8 slp_typ) +{ + /* Currently use cases here all target to S5 therefore we do early return + * here for saving one transaction to the EC for getting SKU ID. */ + if (slp_typ != ACPI_S5) + return; + + switch (get_board_sku()) { + case SKU_1_LTE: + power_off_lte_module(slp_typ); + return; + default: + return; + } +} From f107b6c3a0beff0eea343d051dc460e033acd04c Mon Sep 17 00:00:00 2001 From: Eric Lai Date: Fri, 13 Dec 2019 18:08:51 +0800 Subject: [PATCH 0854/1242] mb/google/hatch: Clean up duplicate method Moving Enable/disable GPIO clock gating to soc level. Signed-off-by: Eric Lai Change-Id: I9be77908b4e44e08a707812fd8b23b23bcb56671 Reviewed-on: https://review.coreboot.org/c/coreboot/+/37691 Tested-by: build bot (Jenkins) Reviewed-by: Tim Wawrzynczak Reviewed-by: Furquan Shaikh --- src/mainboard/google/hatch/dsdt.asl | 3 -- src/mainboard/google/hatch/mainboard.asl | 57 ------------------------ 2 files changed, 60 deletions(-) delete mode 100644 src/mainboard/google/hatch/mainboard.asl diff --git a/src/mainboard/google/hatch/dsdt.asl b/src/mainboard/google/hatch/dsdt.asl index 1e7f760a7b..8807191fcb 100644 --- a/src/mainboard/google/hatch/dsdt.asl +++ b/src/mainboard/google/hatch/dsdt.asl @@ -40,9 +40,6 @@ DefinitionBlock( #include #include } - - /* Mainboard hooks */ - #include "mainboard.asl" } #if CONFIG(CHROMEOS) diff --git a/src/mainboard/google/hatch/mainboard.asl b/src/mainboard/google/hatch/mainboard.asl deleted file mode 100644 index dff1a75959..0000000000 --- a/src/mainboard/google/hatch/mainboard.asl +++ /dev/null @@ -1,57 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright 2019 Google, LLC - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include - -Method (LOCL, 1, Serialized) -{ - For (Local0 = 0, Local0 < 5, Local0++) - { - \_SB.PCI0.CGPM (Local0, Arg0) - } -} - -/* - * Method called from _PTS prior to system sleep state entry - * Enables dynamic clock gating for all 5 GPIO communities - */ -Method (MPTS, 1, Serialized) -{ - LOCL (MISCCFG_ENABLE_GPIO_PM_CONFIG) -} - -/* - * Method called from _WAK prior to system sleep state wakeup - * Disables dynamic clock gating for all 5 GPIO communities - */ -Method (MWAK, 1, Serialized) -{ - LOCL (0) -} - -/* - * S0ix Entry/Exit Notifications - * Called from \_SB.LPID._DSM - */ -Method (MS0X, 1, Serialized) -{ - If (Arg0 == 1) { - /* S0ix Entry */ - LOCL (MISCCFG_ENABLE_GPIO_PM_CONFIG) - } Else { - /* S0ix Exit */ - LOCL (0) - } -} From eafa2035ce71324d16cbc2a0ab1efd9c2f138dee Mon Sep 17 00:00:00 2001 From: Matt DeVillier Date: Thu, 19 Dec 2019 19:39:25 -0600 Subject: [PATCH 0855/1242] soc/broadwell/minihd: correct vendor, subsystem IDs Codec vendor ID was copy/pasted from Haswell, should be 0x80862808. Subsystem ID for Intel Mini-HD is always 0x80860101. Change-Id: Idf4446d3437de0dc533baa3b2b4eb49f816807a6 Signed-off-by: Matt DeVillier Reviewed-on: https://review.coreboot.org/c/coreboot/+/37860 Reviewed-by: Angel Pons Tested-by: build bot (Jenkins) --- src/soc/intel/broadwell/minihd.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/soc/intel/broadwell/minihd.c b/src/soc/intel/broadwell/minihd.c index 2e987bd9e5..40c257126a 100644 --- a/src/soc/intel/broadwell/minihd.c +++ b/src/soc/intel/broadwell/minihd.c @@ -27,8 +27,8 @@ static const u32 minihd_verb_table[] = { /* coreboot specific header */ - 0x80862807, // Codec Vendor / Device ID: Intel Mini-HD - 0x00000000, // Subsystem ID + 0x80862808, // Codec Vendor / Device ID: Intel Broadwell Mini-HD + 0x80860101, // Subsystem ID 0x00000004, // Number of jacks /* Enable 3rd Pin and Converter Widget */ From b5b8a7d540aae3bb1facb07792ac7ff93c78f415 Mon Sep 17 00:00:00 2001 From: Matt DeVillier Date: Thu, 19 Dec 2019 19:37:36 -0600 Subject: [PATCH 0856/1242] nb/haswell/minihd: correct subsystem ID The subsystem ID for Intel Mini-HD is always 0x80860101. Change-Id: I74cbba31e93f9bb5b18d3ada780a0f24614ba029 Signed-off-by: Matt DeVillier Reviewed-on: https://review.coreboot.org/c/coreboot/+/37861 Tested-by: build bot (Jenkins) Reviewed-by: Angel Pons --- src/northbridge/intel/haswell/minihd.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/northbridge/intel/haswell/minihd.c b/src/northbridge/intel/haswell/minihd.c index ff5b943f96..52b158e0c1 100644 --- a/src/northbridge/intel/haswell/minihd.c +++ b/src/northbridge/intel/haswell/minihd.c @@ -26,7 +26,7 @@ static const u32 minihd_verb_table[] = { /* coreboot specific header */ 0x80862807, // Codec Vendor / Device ID: Intel Haswell Mini-HD - 0x00000000, // Subsystem ID + 0x80860101, // Subsystem ID 0x00000004, // Number of jacks /* Enable 3rd Pin and Converter Widget */ From 7abc037da4f173755c7b303b42336b7eb605ae62 Mon Sep 17 00:00:00 2001 From: Idwer Vollering Date: Mon, 16 Dec 2019 15:39:00 +0100 Subject: [PATCH 0857/1242] util/superiotool: alter Makefile to build the binary on FreeBSD Change-Id: Ia96bee18abcdf278ae9178471cd4af2de454facf Signed-off-by: Idwer Vollering Reviewed-on: https://review.coreboot.org/c/coreboot/+/37768 Tested-by: build bot (Jenkins) Reviewed-by: Felix Held --- util/superiotool/Makefile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/util/superiotool/Makefile b/util/superiotool/Makefile index 2bc88aba64..32f468366d 100644 --- a/util/superiotool/Makefile +++ b/util/superiotool/Makefile @@ -103,7 +103,7 @@ export LIBPCI_TEST pciutils: @printf "\nChecking for pciutils and zlib... " @echo "$$LIBPCI_TEST" > .test.c - @$(CC) $(CFLAGS) .test.c -o .test $(LIBS) >/dev/null 2>&1 && \ + @$(CC) $(CFLAGS) .test.c -o .test $(LIBS) $(LDFLAGS) >/dev/null 2>&1 && \ printf "found.\n" || ( printf "not found.\n\n"; \ printf "Please install pciutils-devel and zlib-devel.\n"; \ printf "See README for more information.\n\n"; \ From 2ad6f8138a2f36fbf71ac24d9f2450c03993002f Mon Sep 17 00:00:00 2001 From: Elyes HAOUAS Date: Tue, 10 Dec 2019 17:21:57 +0100 Subject: [PATCH 0858/1242] mb/*/*/early_init.c: Remove defined but not used macro Change-Id: I69c3b0b96fde8dc44a961c3d687f5aadbbdddde0 Signed-off-by: Elyes HAOUAS Reviewed-on: https://review.coreboot.org/c/coreboot/+/37644 Reviewed-by: Angel Pons Tested-by: build bot (Jenkins) --- src/mainboard/asrock/g41c-gs/early_init.c | 1 - src/mainboard/gigabyte/ga-945gcm-s2l/early_init.c | 1 - src/mainboard/gigabyte/ga-b75m-d3h/early_init.c | 1 - src/mainboard/gigabyte/ga-g41m-es2l/early_init.c | 1 - src/mainboard/intel/d510mo/early_init.c | 1 - src/mainboard/kontron/986lcd-m/early_init.c | 2 -- 6 files changed, 7 deletions(-) diff --git a/src/mainboard/asrock/g41c-gs/early_init.c b/src/mainboard/asrock/g41c-gs/early_init.c index c7c7b730a6..b86c2d2c9d 100644 --- a/src/mainboard/asrock/g41c-gs/early_init.c +++ b/src/mainboard/asrock/g41c-gs/early_init.c @@ -26,7 +26,6 @@ #define SERIAL_DEV_R2 PNP_DEV(0x2e, NCT6776_SP1) #define SERIAL_DEV_R1 PNP_DEV(0x2e, W83627DHG_SP1) -#define SUPERIO_DEV PNP_DEV(0x2e, 0) void bootblock_mainboard_early_init(void) { diff --git a/src/mainboard/gigabyte/ga-945gcm-s2l/early_init.c b/src/mainboard/gigabyte/ga-945gcm-s2l/early_init.c index f0f598b7af..0f6190f7e2 100644 --- a/src/mainboard/gigabyte/ga-945gcm-s2l/early_init.c +++ b/src/mainboard/gigabyte/ga-945gcm-s2l/early_init.c @@ -23,7 +23,6 @@ #define SERIAL_DEV PNP_DEV(0x2e, IT8718F_SP1) #define GPIO_DEV PNP_DEV(0x2e, IT8718F_GPIO) #define EC_DEV PNP_DEV(0x2e, IT8718F_EC) -#define SUPERIO_DEV PNP_DEV(0x2e, 0) void bootblock_mainboard_early_init(void) { diff --git a/src/mainboard/gigabyte/ga-b75m-d3h/early_init.c b/src/mainboard/gigabyte/ga-b75m-d3h/early_init.c index c370f9705f..9fb3cad618 100644 --- a/src/mainboard/gigabyte/ga-b75m-d3h/early_init.c +++ b/src/mainboard/gigabyte/ga-b75m-d3h/early_init.c @@ -21,7 +21,6 @@ #include #define SUPERIO_BASE 0x2e -#define SUPERIO_DEV PNP_DEV(SUPERIO_BASE, 0) #define SIO_GPIO PNP_DEV(SUPERIO_BASE, IT8728F_GPIO) #define SERIAL_DEV PNP_DEV(SUPERIO_BASE, 0x01) diff --git a/src/mainboard/gigabyte/ga-g41m-es2l/early_init.c b/src/mainboard/gigabyte/ga-g41m-es2l/early_init.c index 4540d4e03d..aa92671f3b 100644 --- a/src/mainboard/gigabyte/ga-g41m-es2l/early_init.c +++ b/src/mainboard/gigabyte/ga-g41m-es2l/early_init.c @@ -24,7 +24,6 @@ #define SERIAL_DEV PNP_DEV(0x2e, IT8718F_SP1) #define GPIO_DEV PNP_DEV(0x2e, IT8718F_GPIO) #define EC_DEV PNP_DEV(0x2e, IT8718F_EC) -#define SUPERIO_DEV PNP_DEV(0x2e, 0) /* Early mainboard specific GPIO setup. * We should use standard gpio.h eventually diff --git a/src/mainboard/intel/d510mo/early_init.c b/src/mainboard/intel/d510mo/early_init.c index 2719e87fe6..3181d3f91b 100644 --- a/src/mainboard/intel/d510mo/early_init.c +++ b/src/mainboard/intel/d510mo/early_init.c @@ -22,7 +22,6 @@ #include #define SERIAL_DEV PNP_DEV(0x4e, W83627THG_SP1) -#define SUPERIO_DEV PNP_DEV(0x4e, 0) void bootblock_mainboard_early_init(void) { diff --git a/src/mainboard/kontron/986lcd-m/early_init.c b/src/mainboard/kontron/986lcd-m/early_init.c index 31cb20998d..0423b2c373 100644 --- a/src/mainboard/kontron/986lcd-m/early_init.c +++ b/src/mainboard/kontron/986lcd-m/early_init.c @@ -25,8 +25,6 @@ #include "option_table.h" -#define SERIAL_DEV PNP_DEV(0x2e, W83627THG_SP1) - /* Override the default lpc decode ranges */ void mainboard_lpc_decode(void) { From d6de92ef1ed8bcfc3660998b5ea0aaafc1d18678 Mon Sep 17 00:00:00 2001 From: Elyes HAOUAS Date: Sat, 30 Nov 2019 17:54:02 +0100 Subject: [PATCH 0859/1242] src/include: Remove min/max() from MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Change-Id: I9ded44422a267e244343502dd5d6ab355e5a788d Signed-off-by: Elyes HAOUAS Reviewed-on: https://review.coreboot.org/c/coreboot/+/37378 Reviewed-by: Patrick Georgi Reviewed-by: Kyösti Mälkki Tested-by: build bot (Jenkins) --- src/include/stdlib.h | 3 --- src/vendorcode/cavium/bdk/libdram/dram-util.h | 3 --- 2 files changed, 6 deletions(-) diff --git a/src/include/stdlib.h b/src/include/stdlib.h index 34ef93abc5..a8297f82a5 100644 --- a/src/include/stdlib.h +++ b/src/include/stdlib.h @@ -3,9 +3,6 @@ #include -#define min(a, b) MIN((a), (b)) -#define max(a, b) MAX((a), (b)) - void *memalign(size_t boundary, size_t size); void *malloc(size_t size); /* We never free memory */ diff --git a/src/vendorcode/cavium/bdk/libdram/dram-util.h b/src/vendorcode/cavium/bdk/libdram/dram-util.h index c9a96ba5ae..f8ab6c1552 100644 --- a/src/vendorcode/cavium/bdk/libdram/dram-util.h +++ b/src/vendorcode/cavium/bdk/libdram/dram-util.h @@ -42,8 +42,6 @@ * are not meant for users's of the libdram API. */ -#if 0 -/* FIXME(dhendrix): min/max are defined in stdlib.h */ /** * Standard min(a,b) macro */ @@ -58,7 +56,6 @@ #define max(X, Y) \ ({ typeof (X) __x = (X); typeof(Y) __y = (Y); \ (__x > __y) ? __x : __y; }) -#endif /** * Absolute value of an integer From f07d7dc2fdd71b3f8b5fd9cbde57068a98a9e602 Mon Sep 17 00:00:00 2001 From: Elyes HAOUAS Date: Sat, 21 Dec 2019 07:24:22 +0100 Subject: [PATCH 0860/1242] drivers/ipmi/ipmi_fru: Add missing MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit malloc() needs Change-Id: I0cf6a5b76543cb6dac584de6628cfc459d5a60a8 Signed-off-by: Elyes HAOUAS Reviewed-on: https://review.coreboot.org/c/coreboot/+/37884 Reviewed-by: Kyösti Mälkki Tested-by: build bot (Jenkins) --- src/drivers/ipmi/ipmi_fru.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/src/drivers/ipmi/ipmi_fru.c b/src/drivers/ipmi/ipmi_fru.c index a5e6ea60d5..8be53f8e0a 100644 --- a/src/drivers/ipmi/ipmi_fru.c +++ b/src/drivers/ipmi/ipmi_fru.c @@ -17,6 +17,8 @@ #include #include #include +#include + #include "ipmi_ops.h" #define MAX_FRU_BUSY_RETRY 5 From 0d9fb55ae2e9e7d83bcfbcec70e5e3e1f58a62ca Mon Sep 17 00:00:00 2001 From: Tim Wawrzynczak Date: Wed, 25 Dec 2019 19:14:30 +1100 Subject: [PATCH 0861/1242] ec/google: Fix wedging AP on early ec sw sync If the EC doesn't support the EARLY_EC_SYNC we don't properly set power limits to reasonable defaults and can wedge the AP by browning out at the end of vboot. BRANCH=none BUG=b:146165519 TEST=./util/abuild/abuild -p none -t google/hatch -x -a Change-Id: I4e683e5a1c5b453b3742a12a519cad9069e8b7f7 Signed-off-by: Edward O'Callaghan Reviewed-on: https://review.coreboot.org/c/coreboot/+/37930 Reviewed-by: Tim Wawrzynczak Tested-by: build bot (Jenkins) --- src/ec/google/chromeec/ec.c | 11 ++++++++--- 1 file changed, 8 insertions(+), 3 deletions(-) diff --git a/src/ec/google/chromeec/ec.c b/src/ec/google/chromeec/ec.c index 5dff16252b..de43eb5b74 100644 --- a/src/ec/google/chromeec/ec.c +++ b/src/ec/google/chromeec/ec.c @@ -757,12 +757,17 @@ int google_chromeec_read_limit_power_request(int *limit_power) .cmd_data_out = &resp, .cmd_dev_index = 0, }; + int rv; - if (google_chromeec_command(&cmd)) - return -1; + rv = google_chromeec_command(&cmd); + if (rv == -EC_RES_INVALID_PARAM || rv == -EC_RES_INVALID_COMMAND) { + printk(BIOS_INFO, "PARAM_LIMIT_POWER not supported by EC.\n"); + *limit_power = 0; + return 0; + } *limit_power = resp.get_param.value; - return 0; + return rv; } int google_chromeec_get_protocol_info( From 12b1d7df70f8b73de250727fdfd81f2b2cea54a9 Mon Sep 17 00:00:00 2001 From: Wisley Chen Date: Fri, 20 Dec 2019 13:06:43 +0800 Subject: [PATCH 0862/1242] mb/google/hatch/var/dratini: Add a new sku for dragonair Add a new sku for dragonair BUG=b:146504217 TEST=emerge-hatch coreboot Change-Id: I4492d65f35d3583df1606c5f2901228b3ae14e4a Signed-off-by: Wisley Chen Reviewed-on: https://review.coreboot.org/c/coreboot/+/37864 Tested-by: build bot (Jenkins) Reviewed-by: Paul Fagerburg Reviewed-by: Tim Wawrzynczak --- .../google/hatch/variants/dratini/include/variant/sku.h | 7 ++++--- src/mainboard/google/hatch/variants/dratini/variant.c | 1 + 2 files changed, 5 insertions(+), 3 deletions(-) diff --git a/src/mainboard/google/hatch/variants/dratini/include/variant/sku.h b/src/mainboard/google/hatch/variants/dratini/include/variant/sku.h index e36d335c1f..a9a50e499a 100644 --- a/src/mainboard/google/hatch/variants/dratini/include/variant/sku.h +++ b/src/mainboard/google/hatch/variants/dratini/include/variant/sku.h @@ -17,9 +17,10 @@ #define __MAINBOARD_SKU_H__ enum { - SKU_21_DRAGONAIR = 21, /* TS + FPS + Stylus */ - SKU_22_DRAGONAIR = 22, /* TS + KB_BL + FPS + Stylus */ - SKU_23_DRAGONAIR = 23, /* TS + Stylus */ + SKU_21_DRAGONAIR = 21, + SKU_22_DRAGONAIR = 22, + SKU_23_DRAGONAIR = 23, + SKU_24_DRAGONAIR = 24, }; #endif /* __MAINBOARD_SKU_H__ */ diff --git a/src/mainboard/google/hatch/variants/dratini/variant.c b/src/mainboard/google/hatch/variants/dratini/variant.c index 3a00385d1d..3a51a55bd4 100644 --- a/src/mainboard/google/hatch/variants/dratini/variant.c +++ b/src/mainboard/google/hatch/variants/dratini/variant.c @@ -26,6 +26,7 @@ const char *get_wifi_sar_cbfs_filename(void) case SKU_21_DRAGONAIR: case SKU_22_DRAGONAIR: case SKU_23_DRAGONAIR: + case SKU_24_DRAGONAIR: filename = "wifi_sar-dragonair.hex"; break; } From b8d575c644011c2c771595e860bf1a2d4c8be392 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ky=C3=B6sti=20M=C3=A4lkki?= Date: Mon, 16 Dec 2019 16:00:49 +0200 Subject: [PATCH 0863/1242] bootblock: Support normal/fallback mechanism again MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Change-Id: I7395e62f6682f4ef123da10ac125127a57711ec6 Signed-off-by: Kyösti Mälkki Reviewed-on: https://review.coreboot.org/c/coreboot/+/37760 Reviewed-by: Nico Huber Reviewed-by: HAOUAS Elyes Reviewed-by: Paul Menzel Tested-by: build bot (Jenkins) --- src/arch/x86/Kconfig | 3 +-- src/arch/x86/Makefile.inc | 2 +- src/arch/x86/bootblock_normal.c | 45 +++++++++++++++++++++++++++++++++ src/include/program_loading.h | 3 +++ src/lib/prog_loaders.c | 9 +++++-- 5 files changed, 57 insertions(+), 5 deletions(-) create mode 100644 src/arch/x86/bootblock_normal.c diff --git a/src/arch/x86/Kconfig b/src/arch/x86/Kconfig index f4c0dc9e82..212c9f9acc 100644 --- a/src/arch/x86/Kconfig +++ b/src/arch/x86/Kconfig @@ -232,11 +232,10 @@ config ROMSTAGE_DEBUG_SPINLOOP Add a spin (JMP .) in assembly_entry.S during early romstage to wait for a JTAG debugger to break into the execution sequence. -# Selecting a cbfs prefix from the bootblock is only implemented with romcc choice prompt "Bootblock behaviour" default BOOTBLOCK_SIMPLE - depends on ROMCC_BOOTBLOCK + depends on !VBOOT config BOOTBLOCK_SIMPLE bool "Always load fallback" diff --git a/src/arch/x86/Makefile.inc b/src/arch/x86/Makefile.inc index 3b13efc46e..7e150ff06d 100644 --- a/src/arch/x86/Makefile.inc +++ b/src/arch/x86/Makefile.inc @@ -112,7 +112,7 @@ bootblock-$(CONFIG_IDT_IN_EVERY_STAGE) += exception.c bootblock-$(CONFIG_IDT_IN_EVERY_STAGE) += idt.S bootblock-$(CONFIG_COLLECT_TIMESTAMPS_TSC) += timestamp.c bootblock-$(CONFIG_X86_TOP4G_BOOTMEDIA_MAP) += mmap_boot.c - +bootblock-$(CONFIG_BOOTBLOCK_NORMAL) += bootblock_normal.c bootblock-y += id.S $(call src-to-obj,bootblock,$(dir)/id.S): $(obj)/build.h diff --git a/src/arch/x86/bootblock_normal.c b/src/arch/x86/bootblock_normal.c new file mode 100644 index 0000000000..8001ed0641 --- /dev/null +++ b/src/arch/x86/bootblock_normal.c @@ -0,0 +1,45 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include +#include +#include + +static const char *get_fallback(const char *stagelist) +{ + while (*stagelist) + stagelist++; + return ++stagelist; +} + +int legacy_romstage_selector(struct prog *romstage) +{ + static const char *default_filenames = "normal/romstage\0fallback/romstage"; + const char *boot_candidate; + size_t stages_len; + + boot_candidate = cbfs_boot_map_with_leak("coreboot-stages", CBFS_TYPE_RAW, &stages_len); + if (!boot_candidate) + boot_candidate = default_filenames; + + if (do_normal_boot()) { + romstage->name = boot_candidate; + if (!prog_locate(romstage)) + return 0; + } + + romstage->name = get_fallback(boot_candidate); + return prog_locate(romstage); +} diff --git a/src/include/program_loading.h b/src/include/program_loading.h index 1b71fadb1b..320ff3cc1e 100644 --- a/src/include/program_loading.h +++ b/src/include/program_loading.h @@ -179,6 +179,9 @@ struct prog_loader_ops { /* Run romstage from bootblock. */ void run_romstage(void); +/* Runtime selector for CBFS_PREFIX of romstage. */ +int legacy_romstage_selector(struct prog *romstage); + /************************ * RAMSTAGE LOADING * ************************/ diff --git a/src/lib/prog_loaders.c b/src/lib/prog_loaders.c index 978ec16e6a..0319325841 100644 --- a/src/lib/prog_loaders.c +++ b/src/lib/prog_loaders.c @@ -60,8 +60,13 @@ void run_romstage(void) vboot_run_logic(); - if (prog_locate(&romstage)) - goto fail; + if (CONFIG(ARCH_X86) && CONFIG(BOOTBLOCK_NORMAL)) { + if (legacy_romstage_selector(&romstage)) + goto fail; + } else { + if (prog_locate(&romstage)) + goto fail; + } timestamp_add_now(TS_START_COPYROM); From efa56ab12bf174021b187f506c89b44d0e38e7f9 Mon Sep 17 00:00:00 2001 From: Arthur Heymans Date: Thu, 28 Nov 2019 16:11:47 +0100 Subject: [PATCH 0864/1242] arch/x86: Drop ROMCC_BOOTBLOCK symbol Change-Id: I968c4392849045cd50bfe2c83de44daba38ee245 Signed-off-by: Arthur Heymans Reviewed-on: https://review.coreboot.org/c/coreboot/+/37336 Tested-by: build bot (Jenkins) Reviewed-by: HAOUAS Elyes --- src/Kconfig | 3 --- 1 file changed, 3 deletions(-) diff --git a/src/Kconfig b/src/Kconfig index b78b162e9d..762cf8901b 100644 --- a/src/Kconfig +++ b/src/Kconfig @@ -1177,9 +1177,6 @@ config BOOTBLOCK_CUSTOM # src/lib/bootblock.c#main() C entry point. bool -config ROMCC_BOOTBLOCK - bool - ############################################################################### # Set default values for symbols created before mainboards. This allows the # option to be displayed in the general menu, but the default to be loaded in From c2092569d5d21e0cdd3690d8021c2d46dfeaeabd Mon Sep 17 00:00:00 2001 From: Elyes HAOUAS Date: Tue, 17 Dec 2019 12:18:31 +0100 Subject: [PATCH 0865/1242] Makefile: Remove romcc MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Change-Id: I2fe7fa8b23da3b909adc2b8bce59304acfb5b807 Signed-off-by: Elyes HAOUAS Signed-off-by: Kyösti Mälkki Reviewed-on: https://review.coreboot.org/c/coreboot/+/37788 Tested-by: build bot (Jenkins) Reviewed-by: Jacob Garber --- Makefile.inc | 14 ++------------ payloads/libpayload/Makefile | 1 - toolchain.inc | 2 -- 3 files changed, 2 insertions(+), 15 deletions(-) diff --git a/Makefile.inc b/Makefile.inc index dc5272efb5..82adc1d0f9 100644 --- a/Makefile.inc +++ b/Makefile.inc @@ -486,7 +486,7 @@ ifeq ($(CONFIG_DEBUG_ADA_CODE),y) ADAFLAGS_common += -gnata endif -additional-dirs := $(objutil)/cbfstool $(objutil)/romcc $(objutil)/ifdtool \ +additional-dirs := $(objutil)/cbfstool $(objutil)/ifdtool \ $(objutil)/options $(objutil)/amdfwtool \ $(objutil)/cbootimage @@ -552,16 +552,6 @@ ifeq ($(_WINCHECK),Cygwin) STACK=-Wl,--stack,16384000 endif -# this allows ccache to prepend itself -# (ccache handling happens first) -ROMCC_BIN= $(objutil)/romcc/romcc -ROMCC?=$(ROMCC_BIN) -$(ROMCC_BIN): $(top)/util/romcc/romcc.c - @printf " HOSTCC $(subst $(obj)/,,$(@)) (this may take a while)\n" - @# Note: Adding -O2 here might cause problems. For details see: - @# https://www.coreboot.org/pipermail/coreboot/2010-February/055825.html - $(HOSTCC) -g $(STACK) -Wall -o $@ $< - BINCFG:=$(objutil)/bincfg/bincfg IFDTOOL:=$(objutil)/ifdtool/ifdtool @@ -651,7 +641,7 @@ install-git-commit-clangfmt: include util/crossgcc/Makefile.inc .PHONY: tools -tools: $(objutil)/kconfig/conf $(objutil)/kconfig/toada $(CBFSTOOL) $(objutil)/cbfstool/cbfs-compression-tool $(FMAPTOOL) $(RMODTOOL) $(IFWITOOL) $(objutil)/nvramtool/nvramtool $(ROMCC_BIN) $(objutil)/sconfig/sconfig $(IFDTOOL) $(CBOOTIMAGE) $(AMDFWTOOL) $(AMDCOMPRESS) $(FUTILITY) $(BINCFG) $(IFITTOOL) +tools: $(objutil)/kconfig/conf $(objutil)/kconfig/toada $(CBFSTOOL) $(objutil)/cbfstool/cbfs-compression-tool $(FMAPTOOL) $(RMODTOOL) $(IFWITOOL) $(objutil)/nvramtool/nvramtool $(objutil)/sconfig/sconfig $(IFDTOOL) $(CBOOTIMAGE) $(AMDFWTOOL) $(AMDCOMPRESS) $(FUTILITY) $(BINCFG) $(IFITTOOL) ########################################################################### # Common recipes for all stages diff --git a/payloads/libpayload/Makefile b/payloads/libpayload/Makefile index e5f49a6701..03fb153d5c 100644 --- a/payloads/libpayload/Makefile +++ b/payloads/libpayload/Makefile @@ -163,7 +163,6 @@ CCACHE:=CCACHE_COMPILERCHECK=content CCACHE_BASEDIR=$(top) $(CCACHE) CC := $(CCACHE) $(CC) HOSTCC := $(CCACHE) $(HOSTCC) HOSTCXX := $(CCACHE) $(HOSTCXX) -ROMCC := $(CCACHE) $(ROMCC) endif strip_quotes = $(subst ",,$(subst \",,$(1))) diff --git a/toolchain.inc b/toolchain.inc index c3aa3e50fa..865227b3a7 100644 --- a/toolchain.inc +++ b/toolchain.inc @@ -29,7 +29,6 @@ $(foreach arch,$(ARCH_SUPPORTED), \ HOSTCC:=$(CCACHE) $(HOSTCC) HOSTCXX:=$(CCACHE) $(HOSTCXX) -ROMCC=$(CCACHE) $(ROMCC_BIN) endif # scan-build integration @@ -44,7 +43,6 @@ $(foreach arch,$(ARCH_SUPPORTED), \ HOSTCC:=CCC_CC="$(HOSTCC)" $(CC) HOSTCXX:=CCC_CXX="$(HOSTCXX)" $(CXX) -ROMCC=CCC_CC="$(ROMCC_BIN)" $(CC) endif COREBOOT_STANDARD_STAGES := decompressor bootblock verstage romstage ramstage From 945b698f82279fdb42f83f6a3eb2e6f74db2869c Mon Sep 17 00:00:00 2001 From: Arthur Heymans Date: Thu, 28 Nov 2019 16:14:56 +0100 Subject: [PATCH 0866/1242] util/romcc: Drop romcc support Finally all boards use a GCC compiled bootblock! Change-Id: I0c9a1b19dbdc32b43875da7d685718bae9d7f5f4 Signed-off-by: Arthur Heymans Reviewed-on: https://review.coreboot.org/c/coreboot/+/37337 Reviewed-by: HAOUAS Elyes Reviewed-by: Jacob Garber Tested-by: build bot (Jenkins) --- util/romcc/COPYING | 341 - util/romcc/Makefile | 30 - util/romcc/description.md | 2 - util/romcc/results/linux_test1.out | Bin 13 -> 0 bytes util/romcc/results/linux_test10.out | 1 - util/romcc/results/linux_test11.out | 1 - util/romcc/results/linux_test12.out | 11 - util/romcc/results/linux_test13.out | 14 - util/romcc/results/linux_test2.out | 59 - util/romcc/results/linux_test3.out | 11 - util/romcc/results/linux_test4.out | 11 - util/romcc/results/linux_test5.out | 34 - util/romcc/results/linux_test6.out | 2 - util/romcc/results/linux_test7.out | 32 - util/romcc/results/linux_test8.out | 1 - util/romcc/results/linux_test9.out | 134 - util/romcc/romcc.1 | 244 - util/romcc/romcc.c | 25199 ----------------- util/romcc/test.sh | 232 - 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It is safest -to attach them to the start of each source file to most effectively -convey the exclusion of warranty; and each file should have at least -the "copyright" line and a pointer to where the full notice is found. - - - Copyright (C) 19yy - - This program is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. - - This program is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program; if not, write to the Free Software - Foundation, Inc. - - -Also add information on how to contact you by electronic and paper mail. - -If the program is interactive, make it output a short notice like this -when it starts in an interactive mode: - - Gnomovision version 69, Copyright (C) 19yy name of author - Gnomovision comes with ABSOLUTELY NO WARRANTY; for details type `show w'. - This is free software, and you are welcome to redistribute it - under certain conditions; type `show c' for details. - -The hypothetical commands `show w' and `show c' should show the appropriate -parts of the General Public License. Of course, the commands you use may -be called something other than `show w' and `show c'; they could even be -mouse-clicks or menu items--whatever suits your program. - -You should also get your employer (if you work as a programmer) or your -school, if any, to sign a "copyright disclaimer" for the program, if -necessary. Here is a sample; alter the names: - - Yoyodyne, Inc., hereby disclaims all copyright interest in the program - `Gnomovision' (which makes passes at compilers) written by James Hacker. - - , 1 April 1989 - Ty Coon, President of Vice - -This General Public License does not permit incorporating your program into -proprietary programs. If your program is a subroutine library, you may -consider it more useful to permit linking proprietary applications with the -library. If this is what you want to do, use the GNU Library General -Public License instead of this License. diff --git a/util/romcc/Makefile b/util/romcc/Makefile deleted file mode 100644 index 2c5f174cf2..0000000000 --- a/util/romcc/Makefile +++ /dev/null @@ -1,30 +0,0 @@ -CC=gcc -CPPFLAGS= -CFLAGS= -g -Wall -Werror $(CPPFLAGS) -CPROF_FLAGS=-pg -fprofile-arcs -BUILD_DIR=build - -default: $(BUILD_DIR)/romcc - -$(BUILD_DIR)/romcc: romcc.c $(BUILD_DIR) - $(CC) $(CFLAGS) -o $@ $< - -$(BUILD_DIR)/romcc_pg: romcc.c $(BUILD_DIR) - $(CC) $(CFLAGS) $(CPROF_FLAGS) -o $@ $< - -$(BUILD_DIR): - mkdir -p $(BUILD_DIR) - -test: $(BUILD_DIR)/romcc - ./test.sh all - -test-simple: $(BUILD_DIR)/romcc - ./test.sh simple - -test-linux: $(BUILD_DIR)/romcc - ./test.sh linux - -clean distclean: - rm -rf $(BUILD_DIR) - -.PHONY: all test test-simple test-linux clean distclean diff --git a/util/romcc/description.md b/util/romcc/description.md deleted file mode 100644 index 4c12261730..0000000000 --- a/util/romcc/description.md +++ /dev/null @@ -1,2 +0,0 @@ -Compile a C source file generating a binary that does not implicitly -use RAM. `C` diff --git a/util/romcc/results/linux_test1.out b/util/romcc/results/linux_test1.out deleted file mode 100644 index e139c33ef93769e968c6b578f476969394a8a6b2..0000000000000000000000000000000000000000 GIT binary patch literal 0 HcmV?d00001 literal 13 Ucmc~u&B@7ED9.c -.SH DESCRIPTION -.B romcc -is a C compiler which produces binaries which do not rely on RAM, but -instead only use CPU registers. -.PP -It is prominently used in the coreboot project to compile C code which -needs to run before the firmware has initialized the RAM, but can be -used for other purposes, too. -.SH OPTIONS -.TP -.B "\-o" -Output file name. -.TP -.B "\-f